From 0ef476be9416da247a1ec0966b59ac2f3805f35f Mon Sep 17 00:00:00 2001 From: Jeremy Boynes Date: Fri, 6 Jan 2023 18:36:53 -0800 Subject: [PATCH 1/3] Add SVD files for SAMC2x parts --- svd/ATSAMC20E18A.svd | 21842 +++++++++++++++++++++++++++++++ svd/ATSAMC20G18A.svd | 21842 +++++++++++++++++++++++++++++++ svd/ATSAMC20J18A.svd | 21842 +++++++++++++++++++++++++++++++ svd/ATSAMC20J18AU.svd | 21842 +++++++++++++++++++++++++++++++ svd/ATSAMC20N18A.svd | 22961 ++++++++++++++++++++++++++++++++ svd/ATSAMC21E18A.svd | 27893 +++++++++++++++++++++++++++++++++++++++ svd/ATSAMC21G18A.svd | 27996 +++++++++++++++++++++++++++++++++++++++ svd/ATSAMC21J18A.svd | 27996 +++++++++++++++++++++++++++++++++++++++ svd/ATSAMC21J18AU.svd | 27996 +++++++++++++++++++++++++++++++++++++++ svd/ATSAMC21N18A.svd | 28372 ++++++++++++++++++++++++++++++++++++++++ 10 files changed, 250582 insertions(+) create mode 100644 svd/ATSAMC20E18A.svd create mode 100644 svd/ATSAMC20G18A.svd create mode 100644 svd/ATSAMC20J18A.svd create mode 100644 svd/ATSAMC20J18AU.svd create mode 100644 svd/ATSAMC20N18A.svd create mode 100644 svd/ATSAMC21E18A.svd create mode 100644 svd/ATSAMC21G18A.svd create mode 100644 svd/ATSAMC21J18A.svd create mode 100644 svd/ATSAMC21J18AU.svd create mode 100644 svd/ATSAMC21N18A.svd diff --git a/svd/ATSAMC20E18A.svd b/svd/ATSAMC20E18A.svd new file mode 100644 index 000000000000..5761dc744167 --- /dev/null +++ b/svd/ATSAMC20E18A.svd @@ -0,0 +1,21842 @@ + + + + Microchip Technology + MCHP + ATSAMC20E18A + SAMC20 + 0 + Microchip ATSAMC20E18A Microcontroller + + CM0+ + r0p0 + selectable + true + false + 2 + false + + 8 + 32 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + AC + U22451.1.1 + Analog Comparators + AC + AC_ + 0x42005000 + + 0 + 0x24 + registers + + + AC + 27 + + + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + + + CTRLB + Control B + 0x1 + 8 + write-only + 0x00 + + + START0 + Comparator 0 Start Comparison + 0 + 1 + + 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GENCTRL4Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + + + GENCTRL5 + Generic Clock Generator Control 5 Synchronization Busy bits + 7 + 1 + + GENCTRL5Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + + + GENCTRL6 + Generic Clock Generator Control 6 Synchronization Busy bits + 8 + 1 + + GENCTRL6Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + + + GENCTRL7 + Generic Clock Generator Control 7 Synchronization Busy bits + 9 + 1 + + GENCTRL7Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + + + GENCTRL8 + Generic Clock Generator Control 8 Synchronization Busy bits + 10 + 1 + + GENCTRL8Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + + + + + 9 + 4 + GENCTRL[%s] + Generic Clock Generator Control + 0x20 + 32 + 0x00000000 + + + SRC + Source Select + 0 + 3 + + SRCSelect + + XOSC + XOSC oscillator output + 0 + + + GCLKIN + Generator input pad + 1 + + + GCLKGEN1 + Generic clock generator 1 output + 2 + + + OSCULP32K + OSCULP32K oscillator output + 3 + + + OSC32K + OSC32K oscillator output + 4 + + + XOSC32K + XOSC32K oscillator output + 5 + + + OSC48M + OSC48M oscillator output + 6 + + + DPLL96M + DPLL96M output + 7 + + + + + GENEN + Generic Clock Generator Enable + 8 + 1 + + + IDC + Improve Duty Cycle + 9 + 1 + + + OOV + Output Off Value + 10 + 1 + + + OE + Output Enable + 11 + 1 + + + DIVSEL + Divide Selection + 12 + 1 + + DIVSELSelect + + DIV1 + Divide input directly by divider factor + 0x0 + + + DIV2 + Divide input by 2^(divider factor+ 1) + 0x1 + + + + + RUNSTDBY + Run in Standby + 13 + 1 + + + DIV + Division Factor + 16 + 16 + + + + + 41 + 4 + PCHCTRL[%s] + Peripheral Clock Control + 0x80 + 32 + 0x00000000 + + + GEN + Generic Clock Generator + 0 + 4 + + GENSelect + + GCLK0 + Generic clock generator 0 + 0x0 + + + GCLK1 + Generic clock generator 1 + 0x1 + + + GCLK2 + Generic clock generator 2 + 0x2 + + + GCLK3 + Generic clock generator 3 + 0x3 + + + GCLK4 + Generic clock generator 4 + 0x4 + + + GCLK5 + Generic clock generator 5 + 0x5 + + + GCLK6 + Generic clock generator 6 + 0x6 + + + GCLK7 + Generic clock generator 7 + 0x7 + + + GCLK8 + Generic clock generator 8 + 0x8 + + + + + CHEN + Channel Enable + 6 + 1 + + + WRTLOCK + Write Lock + 7 + 1 + + + + + + + HMATRIXHS + I76382.1.3 + HSB Matrix + HMATRIXB + HMATRIXB_ + 0x4100A000 + + 0 + 0x168 + registers + + + + 16 + 4 + MCFG[%s] + Master Configuration + 0x0 + 32 + 0x00000002 + + + ULBT + Undefined Length Burst Type + 0 + 3 + + ULBTSelect + + INFINITE + Infinite Length + 0 + + + SINGLE + Single Access + 1 + + + FOUR_BEAT + Four Beat Burst + 2 + + + EIGHT_BEAT + Eight Beat Burst + 3 + + + SIXTEEN_BEAT + Sixteen Beat Burst + 4 + + + + + + + 16 + 4 + SCFG[%s] + Slave Configuration + 0x40 + 32 + 0x00000010 + + + SLOT_CYCLE + Maximum Number of Allowed Cycles for a Burst + 0 + 8 + + + DEFMSTR_TYPE + Default Master Type + 16 + 2 + + DEFMSTR_TYPESelect + + NO_DEFAULT + No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. + 0 + + + LAST_DEFAULT + Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. + 1 + + + FIXED_DEFAULT + Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave. + 2 + + + + + FIXED_DEFMSTR + Fixed Index of Default Master + 18 + 4 + + + ARBT + Arbitration Type + 24 + 1 + + ARBTSelect + + ROUND_ROBIN + Round-Robin Arbitration + 0 + + + FIXED_PRIORITY + Fixed Priority Arbitration + 1 + + + + + + + 4 + 0x8 + PRS[%s] + + 0x080 + + PRAS + Priority A for Slave + 0x0 + 32 + 0x00000000 + + + M0PR + Master 0 Priority + 0 + 4 + + + M1PR + Master 1 Priority + 4 + 4 + + + M2PR + Master 2 Priority + 8 + 4 + + + M3PR + Master 3 Priority + 12 + 4 + + + M4PR + Master 4 Priority + 16 + 4 + + + M5PR + Master 5 Priority + 20 + 4 + + + M6PR + Master 6 Priority + 24 + 4 + + + M7PR + Master 7 Priority + 28 + 4 + + + + + PRBS + Priority B for Slave + 0x4 + 32 + 0x00000000 + + + M8PR + Master 8 Priority + 0 + 4 + + + M9PR + Master 9 Priority + 4 + 4 + + + M10PR + Master 10 Priority + 8 + 4 + + + M11PR + Master 11 Priority + 12 + 4 + + + M12PR + Master 12 Priority + 16 + 4 + + + M13PR + Master 13 Priority + 20 + 4 + + + M14PR + Master 14 Priority + 24 + 4 + + + M15PR + Master 15 Priority + 28 + 4 + + + + + + MRCR + Master Remap Control + 0x100 + 32 + 0x00000000 + + + RCB0 + Remap Command Bit for Master 0 + 0 + 1 + + RCB0Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB1 + Remap Command Bit for Master 1 + 1 + 1 + + RCB1Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB2 + Remap Command Bit for Master 2 + 2 + 1 + + RCB2Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB3 + Remap Command Bit for Master 3 + 3 + 1 + + RCB3Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB4 + Remap Command Bit for Master 4 + 4 + 1 + + RCB4Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB5 + Remap Command Bit for Master 5 + 5 + 1 + + RCB5Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB6 + Remap Command Bit for Master 6 + 6 + 1 + + RCB6Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB7 + Remap Command Bit for Master 7 + 7 + 1 + + RCB7Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB8 + Remap Command Bit for Master 8 + 8 + 1 + + RCB8Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB9 + Remap Command Bit for Master 9 + 9 + 1 + + RCB9Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB10 + Remap Command Bit for Master 10 + 10 + 1 + + RCB10Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB11 + Remap Command Bit for Master 11 + 11 + 1 + + RCB11Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB12 + Remap Command Bit for Master 12 + 12 + 1 + + RCB12Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB13 + Remap Command Bit for Master 13 + 13 + 1 + + RCB13Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB14 + Remap Command Bit for Master 14 + 14 + 1 + + RCB14Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB15 + Remap Command Bit for Master 15 + 15 + 1 + + RCB15Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + + + 16 + 4 + SFR[%s] + Special Function + 0x110 + 32 + 0x00000000 + + + SFR + Special Function Register + 0 + 32 + + + + + + + MCLK + U22342.0.0 + Main Clock + MCLK + MCLK_ + 0x40000800 + + 0 + 0x20 + registers + + + + INTENCLR + Interrupt Enable Clear + 0x1 + 8 + 0x00 + + + CKRDY + Clock Ready Interrupt Enable + 0 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x2 + 8 + 0x00 + + + CKRDY + Clock Ready Interrupt Enable + 0 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x3 + 8 + 0x01 + + + CKRDY + Clock Ready + 0 + 1 + + + + + CPUDIV + CPU Clock Division + 0x4 + 8 + 0x01 + + + CPUDIV + CPU Clock Division Factor + 0 + 8 + + CPUDIVSelect + + DIV1 + Divide by 1 + 0x01 + + + DIV2 + Divide by 2 + 0x02 + + + DIV4 + Divide by 4 + 0x04 + + + DIV8 + Divide by 8 + 0x08 + + + DIV16 + Divide by 16 + 0x10 + + + DIV32 + Divide by 32 + 0x20 + + + DIV64 + Divide by 64 + 0x40 + + + DIV128 + Divide by 128 + 0x80 + + + + + + + AHBMASK + AHB Mask + 0x10 + 32 + 0x00001CFF + + + HPB0_ + HPB0 AHB Clock Mask + 0 + 1 + + + HPB1_ + HPB1 AHB Clock Mask + 1 + 1 + + + HPB2_ + HPB2 AHB Clock Mask + 2 + 1 + + + DSU_ + DSU AHB Clock Mask + 3 + 1 + + + HMATRIXHS_ + HMATRIXHS AHB Clock Mask + 4 + 1 + + + NVMCTRL_ + NVMCTRL AHB Clock Mask + 5 + 1 + + + HSRAM_ + HSRAM AHB Clock Mask + 6 + 1 + + + DMAC_ + DMAC AHB Clock Mask + 7 + 1 + + + PAC_ + PAC AHB Clock Mask + 10 + 1 + + + NVMCTRL_PICACHU_ + NVMCTRL_PICACHU AHB Clock Mask + 11 + 1 + + + DIVAS_ + DIVAS AHB Clock Mask + 12 + 1 + + + + + APBAMASK + APBA Mask + 0x14 + 32 + 0x00000FFF + + + PAC_ + PAC APB Clock Enable + 0 + 1 + + + PM_ + PM APB Clock Enable + 1 + 1 + + + MCLK_ + MCLK APB Clock Enable + 2 + 1 + + + RSTC_ + RSTC APB Clock Enable + 3 + 1 + + + OSCCTRL_ + OSCCTRL APB Clock Enable + 4 + 1 + + + OSC32KCTRL_ + OSC32KCTRL APB Clock Enable + 5 + 1 + + + SUPC_ + SUPC APB Clock Enable + 6 + 1 + + + GCLK_ + GCLK APB Clock Enable + 7 + 1 + + + WDT_ + WDT APB Clock Enable + 8 + 1 + + + RTC_ + RTC APB Clock Enable + 9 + 1 + + + EIC_ + EIC APB Clock Enable + 10 + 1 + + + FREQM_ + FREQM APB Clock Enable + 11 + 1 + + + + + APBBMASK + APBB Mask + 0x18 + 32 + 0x00000007 + + + PORT_ + PORT APB Clock Enable + 0 + 1 + + + DSU_ + DSU APB Clock Enable + 1 + 1 + + + NVMCTRL_ + NVMCTRL APB Clock Enable + 2 + 1 + + + HMATRIXHS_ + HMATRIXHS APB Clock Enable + 5 + 1 + + + + + APBCMASK + APBC Mask + 0x1C + 32 + 0x00000000 + + + EVSYS_ + EVSYS APB Clock Enable + 0 + 1 + + + SERCOM0_ + SERCOM0 APB Clock Enable + 1 + 1 + + + SERCOM1_ + SERCOM1 APB Clock Enable + 2 + 1 + + + SERCOM2_ + SERCOM2 APB Clock Enable + 3 + 1 + + + SERCOM3_ + SERCOM3 APB Clock Enable + 4 + 1 + + + TCC0_ + TCC0 APB Clock Enable + 9 + 1 + + + TCC1_ + TCC1 APB Clock Enable + 10 + 1 + + + TCC2_ + TCC2 APB Clock Enable + 11 + 1 + + + TC0_ + TC0 APB Clock Enable + 12 + 1 + + + TC1_ + TC1 APB Clock Enable + 13 + 1 + + + TC2_ + TC2 APB Clock Enable + 14 + 1 + + + TC3_ + TC3 APB Clock Enable + 15 + 1 + + + TC4_ + TC4 APB Clock Enable + 16 + 1 + + + ADC0_ + ADC0 APB Clock Enable + 17 + 1 + + + AC_ + AC APB Clock Enable + 20 + 1 + + + PTC_ + PTC APB Clock Enable + 22 + 1 + + + CCL_ + CCL APB Clock Enable + 23 + 1 + + + + + + + MTB + U20021.0.0 + Cortex-M0+ Micro-Trace Buffer + MTB + MTB_ + 0x41008000 + + 0 + 0x1000 + registers + + + + POSITION + MTB Position + 0x0 + 32 + + + WRAP + Pointer Value Wraps + 2 + 1 + + + POINTER + Trace Packet Location Pointer + 3 + 29 + + + + + MASTER + MTB Master + 0x4 + 32 + 0x00000000 + + + MASK + Maximum Value of the Trace Buffer in SRAM + 0 + 5 + + + TSTARTEN + Trace Start Input Enable + 5 + 1 + + + TSTOPEN + Trace Stop Input Enable + 6 + 1 + + + SFRWPRIV + Special Function Register Write Privilege + 7 + 1 + + + RAMPRIV + SRAM Privilege + 8 + 1 + + + HALTREQ + Halt Request + 9 + 1 + + + EN + Main Trace Enable + 31 + 1 + + + + + FLOW + MTB Flow + 0x8 + 32 + 0x00000000 + + + AUTOSTOP + Auto Stop Tracing + 0 + 1 + + + AUTOHALT + Auto Halt Request + 1 + 1 + + + WATERMARK + Watermark value + 3 + 29 + + + + + BASE + MTB Base + 0xC + 32 + read-only + + + ITCTRL + MTB Integration Mode Control + 0xF00 + 32 + + + CLAIMSET + MTB Claim Set + 0xFA0 + 32 + + + CLAIMCLR + MTB Claim Clear + 0xFA4 + 32 + + + LOCKACCESS + MTB Lock Access + 0xFB0 + 32 + + + LOCKSTATUS + MTB Lock Status + 0xFB4 + 32 + read-only + + + AUTHSTATUS + MTB Authentication Status + 0xFB8 + 32 + read-only + + + DEVARCH + MTB Device Architecture + 0xFBC + 32 + read-only + + + DEVID + MTB Device Configuration + 0xFC8 + 32 + read-only + + + DEVTYPE + MTB Device Type + 0xFCC + 32 + read-only + + + PID4 + Peripheral Identification 4 + 0xFD0 + 32 + read-only + + + PID5 + Peripheral Identification 5 + 0xFD4 + 32 + read-only + + + PID6 + Peripheral Identification 6 + 0xFD8 + 32 + read-only + + + PID7 + Peripheral Identification 7 + 0xFDC + 32 + read-only + + + PID0 + Peripheral Identification 0 + 0xFE0 + 32 + read-only + + + PID1 + Peripheral Identification 1 + 0xFE4 + 32 + read-only + + + PID2 + Peripheral Identification 2 + 0xFE8 + 32 + read-only + + + PID3 + Peripheral Identification 3 + 0xFEC + 32 + read-only + + + CID0 + Component Identification 0 + 0xFF0 + 32 + read-only + + + CID1 + Component Identification 1 + 0xFF4 + 32 + read-only + + + CID2 + Component Identification 2 + 0xFF8 + 32 + read-only + + + CID3 + Component Identification 3 + 0xFFC + 32 + read-only + + + + + NVMCTRL + U22074.0.1.1 + Non-Volatile Memory Controller + NVMCTRL + NVMCTRL_ + 0x41004000 + + 0 + 0x30 + registers + + + NVMCTRL + 6 + + + + CTRLA + Control A + 0x0 + 16 + 0x0000 + + + CMD + Command + 0 + 7 + + CMDSelect + + ER + Erase Row - Erases the row addressed by the ADDR register. + 0x02 + + + WP + Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. + 0x04 + + + EAR + Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. + 0x05 + + + WAP + Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. + 0x06 + + + SF + Security Flow Command + 0x0A + + + WL + Write lockbits + 0x0F + + + RWWEEER + RWW EEPROM area Erase Row - Erases the row addressed by the ADDR register. + 0x1A + + + RWWEEWP + RWW EEPROM Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. + 0x1C + + + LR + Lock Region - Locks the region containing the address location in the ADDR register. + 0x40 + + + UR + Unlock Region - Unlocks the region containing the address location in the ADDR register. + 0x41 + + + SPRM + Sets the power reduction mode. + 0x42 + + + CPRM + Clears the power reduction mode. + 0x43 + + + PBC + Page Buffer Clear - Clears the page buffer. + 0x44 + + + SSB + Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row. + 0x45 + + + INVALL + Invalidate all cache lines. + 0x46 + + + + + CMDEX + Command Execution + 8 + 8 + + CMDEXSelect + + KEY + Execution Key + 0xA5 + + + + + + + CTRLB + Control B + 0x4 + 32 + 0x00000080 + + + RWS + NVM Read Wait States + 1 + 4 + + RWSSelect + + SINGLE + Single Auto Wait State + 0 + + + HALF + Half Auto Wait State + 1 + + + DUAL + Dual Auto Wait State + 2 + + + + + MANW + Manual Write + 7 + 1 + + + SLEEPPRM + Power Reduction Mode during Sleep + 8 + 2 + + SLEEPPRMSelect + + WAKEONACCESS + NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access. + 0 + + + WAKEUPINSTANT + NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep. + 1 + + + DISABLED + Auto power reduction disabled. + 3 + + + + + READMODE + NVMCTRL Read Mode + 16 + 2 + + READMODESelect + + NO_MISS_PENALTY + The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance. + 0x0 + + + LOW_POWER + Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time. + 0x1 + + + DETERMINISTIC + The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings. + 0x2 + + + + + CACHEDIS + Cache Disable + 18 + 2 + + + + + PARAM + NVM Parameter + 0x8 + 32 + 0x00000000 + + + NVMP + NVM Pages + 0 + 16 + + + PSZ + Page Size + 16 + 3 + + PSZSelect + + 8 + 8 bytes + 0x0 + + + 16 + 16 bytes + 0x1 + + + 32 + 32 bytes + 0x2 + + + 64 + 64 bytes + 0x3 + + + 128 + 128 bytes + 0x4 + + + 256 + 256 bytes + 0x5 + + + 512 + 512 bytes + 0x6 + + + 1024 + 1024 bytes + 0x7 + + + + + RWWEEP + RWW EEPROM Pages + 20 + 12 + + + + + INTENCLR + Interrupt Enable Clear + 0xC + 8 + 0x00 + + + READY + NVM Ready Interrupt Enable + 0 + 1 + + + ERROR + Error Interrupt Enable + 1 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x10 + 8 + 0x00 + + + READY + NVM Ready Interrupt Enable + 0 + 1 + + + ERROR + Error Interrupt Enable + 1 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x14 + 8 + 0x00 + + + READY + NVM Ready + 0 + 1 + + + ERROR + Error + 1 + 1 + + + + + STATUS + Status + 0x18 + 16 + 0x0000 + + + PRM + Power Reduction Mode + 0 + 1 + + + LOAD + NVM Page Buffer Active Loading + 1 + 1 + + + PROGE + Programming Error Status + 2 + 1 + + + LOCKE + Lock Error Status + 3 + 1 + + + NVME + NVM Error + 4 + 1 + + + SB + Security Bit Status + 8 + 1 + + + + + ADDR + Address + 0x1C + 32 + 0x00000000 + + + ADDR + NVM Address + 0 + 22 + + + + + LOCK + Lock Section + 0x20 + 16 + 0x0000 + + + LOCK + Region Lock Bits + 0 + 16 + + + + + PBLDATA0 + Page Buffer Load Data 0 + 0x28 + 32 + read-only + 0x00000000 + + + PBLDATA1 + Page Buffer Load Data 1 + 0x2C + 32 + read-only + 0x00000000 + + + + + OSCCTRL + U21192.1.0 + Oscillators Control + OSCCTRL + OSCCTRL_ + 0x40001000 + + 0 + 0x3C + registers + + + + INTENCLR + Interrupt Enable Clear + 0x0 + 32 + 0x00000000 + + + XOSCRDY + XOSC Ready Interrupt Enable + 0 + 1 + + + XOSCFAIL + XOSC Clock Failure Detector Interrupt Enable + 1 + 1 + + + OSC48MRDY + OSC48M Ready Interrupt Enable + 4 + 1 + + + DPLLLCKR + DPLL Lock Rise Interrupt Enable + 8 + 1 + + + DPLLLCKF + DPLL Lock Fall Interrupt Enable + 9 + 1 + + + DPLLLTO + DPLL Time Out Interrupt Enable + 10 + 1 + + + DPLLLDRTO + DPLL Ratio Ready Interrupt Enable + 11 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x4 + 32 + 0x00000000 + + + XOSCRDY + XOSC Ready Interrupt Enable + 0 + 1 + + + XOSCFAIL + XOSC Clock Failure Detector Interrupt Enable + 1 + 1 + + + OSC48MRDY + OSC48M Ready Interrupt Enable + 4 + 1 + + + DPLLLCKR + DPLL Lock Rise Interrupt Enable + 8 + 1 + + + DPLLLCKF + DPLL Lock Fall Interrupt Enable + 9 + 1 + + + DPLLLTO + DPLL Time Out Interrupt Enable + 10 + 1 + + + DPLLLDRTO + DPLL Ratio Ready Interrupt Enable + 11 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x8 + 32 + 0x00000000 + + + XOSCRDY + XOSC Ready + 0 + 1 + + + XOSCFAIL + XOSC Clock Failure Detector + 1 + 1 + + + OSC48MRDY + OSC48M Ready + 4 + 1 + + + DPLLLCKR + DPLL Lock Rise + 8 + 1 + + + DPLLLCKF + DPLL Lock Fall + 9 + 1 + + + DPLLLTO + DPLL Timeout + 10 + 1 + + + DPLLLDRTO + DPLL Ratio Ready + 11 + 1 + + + + + STATUS + Power and Clocks Status + 0xC + 32 + read-only + 0x00000000 + + + XOSCRDY + XOSC Ready + 0 + 1 + + + XOSCFAIL + XOSC Clock Failure Detector + 1 + 1 + + + XOSCCKSW + XOSC Clock Switch + 2 + 1 + + + OSC48MRDY + OSC48M Ready + 4 + 1 + + + DPLLLCKR + DPLL Lock Rise + 8 + 1 + + + DPLLLCKF + DPLL Lock Fall + 9 + 1 + + + DPLLTO + DPLL Timeout + 10 + 1 + + + DPLLLDRTO + DPLL Ratio Ready + 11 + 1 + + + + + XOSCCTRL + External Multipurpose Crystal Oscillator (XOSC) Control + 0x10 + 16 + 0x0080 + + + ENABLE + Oscillator Enable + 1 + 1 + + + XTALEN + Crystal Oscillator Enable + 2 + 1 + + + CFDEN + Xosc Clock Failure Detector Enable + 3 + 1 + + + SWBEN + Xosc Clock Switch Enable + 4 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + GAIN + Oscillator Gain + 8 + 3 + + GAINSelect + + GAIN2 + 2 MHz + 0 + + + GAIN4 + 4 MHz + 1 + + + GAIN8 + 8 MHz + 2 + + + GAIN16 + 16 MHz + 3 + + + GAIN30 + 30 MHz + 4 + + + + + AMPGC + Automatic Amplitude Gain Control + 11 + 1 + + + STARTUP + Start-Up Time + 12 + 4 + + STARTUPSelect + + CYCLE1 + 31 us + 0 + + + CYCLE2 + 61 us + 1 + + + CYCLE4 + 122 us + 2 + + + CYCLE8 + 244 us + 3 + + + CYCLE16 + 488 us + 4 + + + CYCLE32 + 977 us + 5 + + + CYCLE64 + 1953 us + 6 + + + CYCLE128 + 3906 us + 7 + + + CYCLE256 + 7813 us + 8 + + + CYCLE512 + 15625 us + 9 + + + CYCLE1024 + 31250 us + 10 + + + CYCLE2048 + 62500 us + 11 + + + CYCLE4096 + 125000 us + 12 + + + CYCLE8192 + 250000 us + 13 + + + CYCLE16384 + 500000 us + 14 + + + CYCLE32768 + 1000000 us + 15 + + + + + + + CFDPRESC + Clock Failure Detector Prescaler + 0x12 + 8 + 0x00 + + + CFDPRESC + Clock Failure Detector Prescaler + 0 + 3 + + CFDPRESCSelect + + DIV1 + 48 MHz + 0 + + + DIV2 + 24 MHz + 1 + + + DIV4 + 12 MHz + 2 + + + DIV8 + 6 MHz + 3 + + + DIV16 + 3 MHz + 4 + + + DIV32 + 1.5 MHz + 5 + + + DIV64 + 0.75 MHz + 6 + + + DIV128 + 0.3125 MHz + 7 + + + + + + + EVCTRL + Event Control + 0x13 + 8 + 0x00 + + + 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1.333 us + 3 + + + CYCLE128 + 2.667 us + 4 + + + CYCLE256 + 5.333 us + 5 + + + CYCLE512 + 10.667 us + 6 + + + CYCLE1024 + 21.333 us + 7 + + + + + + + OSC48MSYNCBUSY + OSC48M Synchronization Busy + 0x18 + 32 + read-only + 0x00000000 + + + OSC48MDIV + OSC48MDIV Synchronization Status + 2 + 1 + + + + + DPLLCTRLA + DPLL Control + 0x1C + 8 + 0x80 + + + ENABLE + Enable + 1 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand + 7 + 1 + + + + + DPLLRATIO + DPLL Ratio Control + 0x20 + 32 + 0x00000000 + + + LDR + Loop Divider Ratio + 0 + 12 + + + LDRFRAC + Loop Divider Ratio Fractional Part + 16 + 4 + + + + + DPLLCTRLB + Digital Core Configuration + 0x24 + 32 + 0x00000000 + + + FILTER + Proportional Integral Filter Selection + 0 + 2 + + FILTERSelect + + DEFAULT + Default filter mode + 0 + + + LBFILT + Low bandwidth filter + 1 + + + HBFILT + High bandwidth filter + 2 + + + HDFILT + High damping filter + 3 + + + + + LPEN + Low-Power Enable + 2 + 1 + + + WUF + Wake Up Fast + 3 + 1 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Automatic lock. + 0 + + + 8MS + Time-out if no lock within 8ms + 4 + + + 9MS + Time-out if no lock within 9ms + 5 + + + 10MS + Time-out if no lock within 10ms + 6 + + + 11MS + Time-out if no lock within 11ms + 7 + + + + + LBYPASS + Lock Bypass + 12 + 1 + + + DIV + Clock Divider + 16 + 11 + + + + + DPLLPRESC + DPLL Prescaler + 0x28 + 8 + 0x00 + + + PRESC + Output Clock Prescaler + 0 + 2 + + PRESCSelect + + DIV1 + DPLL output is divided by 1 + 0 + + + DIV2 + DPLL output is divided by 2 + 1 + + + DIV4 + DPLL output is divided by 4 + 2 + + + + + + + DPLLSYNCBUSY + DPLL Synchronization Busy + 0x2C + 8 + read-only + 0x00 + + + ENABLE + DPLL Enable Synchronization Status + 1 + 1 + + + DPLLRATIO + DPLL Ratio Synchronization Status + 2 + 1 + + + DPLLPRESC + DPLL Prescaler Synchronization Status + 3 + 1 + + + + + DPLLSTATUS + DPLL Status + 0x30 + 8 + read-only + 0x00 + + + LOCK + DPLL Lock Status + 0 + 1 + + + CLKRDY + DPLL Clock Ready + 1 + 1 + + + + + CAL48M + 48MHz Oscillator Calibration + 0x38 + 32 + 0x00000000 + + + FCAL + Frequency Calibration (48MHz) + 0 + 6 + + + FRANGE + Frequency Range (48MHz) + 8 + 2 + + + TCAL + Temperature Calibration (48MHz) + 16 + 6 + + + + + + + OSC32KCTRL + U22462.1.0 + 32k Oscillators Control + OSC32KCTRL + OSC32KCTRL_ + 0x40001400 + + 0 + 0x20 + registers + + + + INTENCLR + Interrupt Enable Clear + 0x0 + 32 + 0x00000000 + + + XOSC32KRDY + XOSC32K Ready Interrupt Enable + 0 + 1 + + + OSC32KRDY + OSC32K Ready Interrupt Enable + 1 + 1 + + + CLKFAIL + XOSC32K Clock Failure Detector Interrupt Enable + 2 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x4 + 32 + 0x00000000 + + + XOSC32KRDY + XOSC32K Ready Interrupt Enable + 0 + 1 + + + OSC32KRDY + OSC32K Ready Interrupt Enable + 1 + 1 + + + CLKFAIL + XOSC32K Clock Failure Detector Interrupt Enable + 2 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x8 + 32 + 0x00000000 + + + XOSC32KRDY + XOSC32K Ready + 0 + 1 + + + OSC32KRDY + OSC32K Ready + 1 + 1 + + + CLKFAIL + XOSC32K Clock Failure Detector + 2 + 1 + + + + + STATUS + Power and Clocks Status + 0xC + 32 + read-only + 0x00000000 + + + XOSC32KRDY + XOSC32K Ready + 0 + 1 + + + OSC32KRDY + OSC32K Ready + 1 + 1 + + + CLKFAIL + XOSC32K Clock Failure Detector + 2 + 1 + + + CLKSW + XOSC32K Clock switch + 3 + 1 + + + + + RTCCTRL + Clock selection + 0x10 + 32 + 0x00000000 + + + RTCSEL + RTC Clock Selection + 0 + 3 + + RTCSELSelect + + ULP1K + 1.024kHz from 32kHz internal ULP oscillator + 0 + + + ULP32K + 32.768kHz from 32kHz internal ULP oscillator + 1 + + + OSC1K + 1.024kHz from 32.768kHz internal oscillator + 2 + + + OSC32K + 32.768kHz from 32.768kHz internal oscillator + 3 + + + XOSC1K + 1.024kHz from 32.768kHz internal oscillator + 4 + + + XOSC32K + 32.768kHz from 32.768kHz external crystal oscillator + 5 + + + + + + + XOSC32K + 32kHz External Crystal Oscillator (XOSC32K) Control + 0x14 + 16 + 0x0080 + + + ENABLE + Oscillator Enable + 1 + 1 + + + XTALEN + Crystal Oscillator Enable + 2 + 1 + + + EN32K + 32kHz Output Enable + 3 + 1 + + + EN1K + 1kHz Output Enable + 4 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + STARTUP + Oscillator Start-Up Time + 8 + 3 + + STARTUPSelect + + CYCLE1 + 0.122 ms + 0 + + + CYCLE32 + 1.068 ms + 1 + + + CYCLE2048 + 62.6 ms + 2 + + + CYCLE4096 + 125 ms + 3 + + + CYCLE16384 + 500 ms + 4 + + + CYCLE32768 + 1000 ms + 5 + + + CYCLE65536 + 2000 ms + 6 + + + CYCLE131072 + 4000 ms + 7 + + + + + WRTLOCK + Write Lock + 12 + 1 + + + + + CFDCTRL + Clock Failure Detector Control + 0x16 + 8 + 0x00 + + + CFDEN + Clock Failure Detector Enable + 0 + 1 + + + SWBACK + Clock Switch Back + 1 + 1 + + + CFDPRESC + Clock Failure Detector Prescaler + 2 + 1 + + + + + EVCTRL + Event Control + 0x17 + 8 + 0x00 + + + CFDEO + Clock Failure Detector Event Output Enable + 0 + 1 + + + + + OSC32K + 32kHz Internal Oscillator (OSC32K) Control + 0x18 + 32 + 0x003F0080 + + + ENABLE + Oscillator Enable + 1 + 1 + + + EN32K + 32kHz Output Enable + 2 + 1 + + + EN1K + 1kHz Output Enable + 3 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + STARTUP + Oscillator Start-Up Time + 8 + 3 + + STARTUPSelect + + CYCLE3 + 0.092 ms + 0 + + + CYCLE4 + 0.122 ms + 1 + + + CYCLE6 + 0.183 ms + 2 + + + CYCLE10 + 0.305 ms + 3 + + + CYCLE18 + 0.549 ms + 4 + + + CYCLE34 + 1.038 ms + 5 + + + CYCLE66 + 2.014 ms + 6 + + + CYCLE130 + 3.967 ms + 7 + + + + + WRTLOCK + Write Lock + 12 + 1 + + + CALIB + Oscillator Calibration + 16 + 7 + + + + + OSCULP32K + 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control + 0x1C + 32 + + + CALIB + Oscillator Calibration + 8 + 5 + + + WRTLOCK + Write Lock + 15 + 1 + + + + + + + PAC + U21201.1.0 + Peripheral Access Controller + PAC + PAC_ + 0x40000000 + + 0 + 0x40 + registers + + + + WRCTRL + Write control + 0x0 + 32 + 0x00000000 + + + PERID + Peripheral identifier + 0 + 16 + + + KEY + Peripheral access control key + 16 + 8 + + KEYSelect + + OFF + No action + 0 + + + CLR + Clear protection + 1 + + + SET + Set protection + 2 + + + SETLCK + Set and lock protection + 3 + + + + + + + EVCTRL + Event control + 0x4 + 8 + 0x00 + + + ERREO + Peripheral acess error event output + 0 + 1 + + + + + INTENCLR + Interrupt enable clear + 0x8 + 8 + 0x00 + + + ERR + Peripheral access error interrupt disable + 0 + 1 + + + + + INTENSET + Interrupt enable set + 0x9 + 8 + 0x00 + + + ERR + Peripheral access error interrupt enable + 0 + 1 + + + + + INTFLAGAHB + Bridge interrupt flag status + 0x10 + 32 + 0x00000000 + + + FLASH_ + FLASH + 0 + 1 + + + HSRAMCM0P_ + HSRAMCM0P + 1 + 1 + + + HSRAMDSU_ + HSRAMDSU + 2 + 1 + + + HPB1_ + HPB1 + 3 + 1 + + + HPB0_ + HPB0 + 4 + 1 + + + HPB2_ + HPB2 + 5 + 1 + + + LPRAMDMAC_ + LPRAMDMAC + 6 + 1 + + + DIVAS_ + DIVAS + 7 + 1 + + + + + INTFLAGA + Peripheral interrupt flag status - Bridge A + 0x14 + 32 + 0x00000000 + + + PAC_ + PAC + 0 + 1 + + + PM_ + PM + 1 + 1 + + + MCLK_ + MCLK + 2 + 1 + + + RSTC_ + RSTC + 3 + 1 + + + OSCCTRL_ + OSCCTRL + 4 + 1 + + + OSC32KCTRL_ + OSC32KCTRL + 5 + 1 + + + SUPC_ + SUPC + 6 + 1 + + + GCLK_ + GCLK + 7 + 1 + + + WDT_ + WDT + 8 + 1 + + + RTC_ + RTC + 9 + 1 + + + EIC_ + EIC + 10 + 1 + + + FREQM_ + FREQM + 11 + 1 + + + + + INTFLAGB + Peripheral interrupt flag status - Bridge B + 0x18 + 32 + 0x00000000 + + + PORT_ + PORT + 0 + 1 + + + DSU_ + DSU + 1 + 1 + + + NVMCTRL_ + NVMCTRL + 2 + 1 + + + DMAC_ + DMAC + 3 + 1 + + + MTB_ + MTB + 4 + 1 + + + HMATRIXHS_ + HMATRIXHS + 5 + 1 + + + + + INTFLAGC + Peripheral interrupt flag status - Bridge C + 0x1C + 32 + 0x00000000 + + + EVSYS_ + EVSYS + 0 + 1 + + + SERCOM0_ + SERCOM0 + 1 + 1 + + + SERCOM1_ + SERCOM1 + 2 + 1 + + + SERCOM2_ + SERCOM2 + 3 + 1 + + + SERCOM3_ + SERCOM3 + 4 + 1 + + + TCC0_ + TCC0 + 9 + 1 + + + TCC1_ + TCC1 + 10 + 1 + + + TCC2_ + TCC2 + 11 + 1 + + + TC0_ + TC0 + 12 + 1 + + + TC1_ + TC1 + 13 + 1 + + + TC2_ + TC2 + 14 + 1 + + + TC3_ + TC3 + 15 + 1 + + + TC4_ + TC4 + 16 + 1 + + + ADC0_ + ADC0 + 17 + 1 + + + AC_ + AC + 20 + 1 + + + PTC_ + PTC + 22 + 1 + + + CCL_ + CCL + 23 + 1 + + + + + STATUSA + Peripheral write protection status - Bridge A + 0x34 + 32 + read-only + 0x00000000 + + + PAC_ + PAC APB Protect Enable + 0 + 1 + + + PM_ + PM APB Protect Enable + 1 + 1 + + + MCLK_ + MCLK APB Protect Enable + 2 + 1 + + + RSTC_ + RSTC APB Protect Enable + 3 + 1 + + + OSCCTRL_ + OSCCTRL APB Protect Enable + 4 + 1 + + + OSC32KCTRL_ + OSC32KCTRL APB Protect Enable + 5 + 1 + + + SUPC_ + SUPC APB Protect Enable + 6 + 1 + + + GCLK_ + GCLK APB Protect Enable + 7 + 1 + + + WDT_ + WDT APB Protect Enable + 8 + 1 + + + RTC_ + RTC APB Protect Enable + 9 + 1 + + + EIC_ + EIC APB Protect Enable + 10 + 1 + + + FREQM_ + FREQM APB Protect Enable + 11 + 1 + + + + + STATUSB + Peripheral write protection status - Bridge B + 0x38 + 32 + read-only + 0x00000002 + + + PORT_ + PORT APB Protect Enable + 0 + 1 + + + DSU_ + DSU APB Protect Enable + 1 + 1 + + + NVMCTRL_ + NVMCTRL APB Protect Enable + 2 + 1 + + + DMAC_ + DMAC APB Protect Enable + 3 + 1 + + + MTB_ + MTB APB Protect Enable + 4 + 1 + + + HMATRIXHS_ + HMATRIXHS APB Protect Enable + 5 + 1 + + + + + STATUSC + Peripheral write protection status - Bridge C + 0x3C + 32 + read-only + 0x02000000 + + + EVSYS_ + EVSYS APB Protect Enable + 0 + 1 + + + SERCOM0_ + SERCOM0 APB Protect Enable + 1 + 1 + + + SERCOM1_ + SERCOM1 APB Protect Enable + 2 + 1 + + + SERCOM2_ + SERCOM2 APB Protect Enable + 3 + 1 + + + SERCOM3_ + SERCOM3 APB Protect Enable + 4 + 1 + + + TCC0_ + TCC0 APB Protect Enable + 9 + 1 + + + TCC1_ + TCC1 APB Protect Enable + 10 + 1 + + + TCC2_ + TCC2 APB Protect Enable + 11 + 1 + + + TC0_ + TC0 APB Protect Enable + 12 + 1 + + + TC1_ + TC1 APB Protect Enable + 13 + 1 + + + TC2_ + TC2 APB Protect Enable + 14 + 1 + + + TC3_ + TC3 APB Protect Enable + 15 + 1 + + + TC4_ + TC4 APB Protect Enable + 16 + 1 + + + ADC0_ + ADC0 APB Protect Enable + 17 + 1 + + + AC_ + AC APB Protect Enable + 20 + 1 + + + PTC_ + PTC APB Protect Enable + 22 + 1 + + + CCL_ + CCL APB Protect Enable + 23 + 1 + + + + + + + PM + U22402.1.0 + Power Manager + PM + PM_ + 0x40000400 + + 0 + 0xA + registers + + + + SLEEPCFG + Sleep Configuration + 0x1 + 8 + 0x00 + + + SLEEPMODE + Sleep Mode + 0 + 3 + + SLEEPMODESelect + + IDLE0 + CPU clock is OFF + 0 + + + IDLE1 + AHB clock is OFF + 1 + + + IDLE2 + APB clock are OFF + 2 + + + STANDBY + All Clocks are OFF + 4 + + + + + + + STDBYCFG + Standby Configuration + 0x8 + 16 + 0x0400 + + + VREGSMOD + Voltage Regulator Standby mode + 6 + 2 + + VREGSMODSelect + + AUTO + Automatic mode + 0 + + + PERFORMANCE + Performance oriented + 1 + + + LP + Low Power oriented + 2 + + + + + BBIASHS + Back Bias for HMCRAMCHS + 10 + 1 + + + + + + + PORT + U22102.1.1 + Port Module + PORT + PORT_ + 0x41000000 + + 0 + 0x80 + registers + + + + 1 + 0x80 + GROUP[%s] + + 0x00 + + DIR + Data Direction + 0x0 + 32 + 0x00000000 + + + DIRCLR + Data Direction Clear + 0x4 + 32 + 0x00000000 + + + DIRSET + Data Direction Set + 0x8 + 32 + 0x00000000 + + + DIRTGL + Data Direction Toggle + 0xC + 32 + 0x00000000 + + + OUT + Data Output Value + 0x10 + 32 + 0x00000000 + + + OUTCLR + Data Output Value Clear + 0x14 + 32 + 0x00000000 + + + OUTSET + Data Output Value Set + 0x18 + 32 + 0x00000000 + + + OUTTGL + Data Output Value Toggle + 0x1C + 32 + 0x00000000 + + + IN + Data Input Value + 0x20 + 32 + read-only + 0x00000000 + + + CTRL + Control + 0x24 + 32 + 0x00000000 + + + SAMPLING + Input Sampling Mode + 0 + 32 + + + + + WRCONFIG + Write Configuration + 0x28 + 32 + write-only + 0x00000000 + + + PINMASK + Pin Mask for Multiple Pin Configuration + 0 + 16 + + + PMUXEN + Select Peripheral Multiplexer + 16 + 1 + + + INEN + Input Enable + 17 + 1 + + + PULLEN + Pull Enable + 18 + 1 + + + DRVSTR + Output Driver Strength Selection + 22 + 1 + + + PMUX + Peripheral Multiplexing Template + 24 + 4 + + + WRPMUX + Write PMUX Registers + 28 + 1 + + + WRPINCFG + Write PINCFG Registers + 30 + 1 + + + HWSEL + Half-Word Select + 31 + 1 + + + + + EVCTRL + Event Input Control + 0x2C + 32 + 0x00000000 + + + PID0 + Port Event Pin Identifier 0 + 0 + 5 + + + EVACT0 + Port Event Action 0 + 5 + 2 + + EVACT0Select + + OUT + Event output to pin + 0x0 + + + SET + Set output register of pin on event + 0x1 + + + CLR + Clear output register of pin on event + 0x2 + + + TGL + Toggle output register of pin on event + 0x3 + + + + + PORTEI0 + Port Event Enable Input 0 + 7 + 1 + + + PID1 + Port Event Pin Identifier 1 + 8 + 5 + + + EVACT1 + Port Event Action 1 + 13 + 2 + + + PORTEI1 + Port Event Enable Input 1 + 15 + 1 + + + PID2 + Port Event Pin Identifier 2 + 16 + 5 + + + EVACT2 + Port Event Action 2 + 21 + 2 + + + PORTEI2 + Port Event Enable Input 2 + 23 + 1 + + + PID3 + Port Event Pin Identifier 3 + 24 + 5 + + + EVACT3 + Port Event Action 3 + 29 + 2 + + + PORTEI3 + Port Event Enable Input 3 + 31 + 1 + + + + + 16 + 1 + PMUX[%s] + Peripheral Multiplexing n + 0x30 + 8 + 0x00 + + + PMUXE + Peripheral Multiplexing for Even-Numbered Pin + 0 + 4 + + + PMUXO + Peripheral Multiplexing for Odd-Numbered Pin + 4 + 4 + + + + + 32 + 1 + PINCFG[%s] + Pin Configuration n + 0x40 + 8 + 0x00 + + + PMUXEN + Select Peripheral Multiplexer + 0 + 1 + + + INEN + Input Enable + 1 + 1 + + + PULLEN + Pull Enable + 2 + 1 + + + DRVSTR + Output Driver Strength Selection + 6 + 1 + + + + + + + + PORT_IOBUS + PORT_IOBUS_ + 0x60000000 + + + PTC + U22153.1.0 + Peripheral Touch Controller + PTC + PTC_ + 0x42005800 + + 0 + 0x1 + reserved + + + PTC + 30 + + + + RSTC + U22392.0.2 + Reset Controller + RSTC + RSTC_ + 0x40000C00 + + 0 + 0x1 + registers + + + + RCAUSE + Reset Cause + 0x0 + 8 + read-only + + + POR + Power On Reset + 0 + 1 + + + BODCORE + Brown Out CORE Detector Reset + 1 + 1 + + + BODVDD + Brown Out VDD Detector Reset + 2 + 1 + + + EXT + External Reset + 4 + 1 + + + WDT + Watchdog Reset + 5 + 1 + + + SYST + System Reset Request + 6 + 1 + + + + + + + RTC + U22501.1.1 + Real-Time Counter + RTC + RTC_ + 0x40002400 + + 0 + 0x25 + registers + + + RTC + 2 + + + + MODE0 + 32-bit Counter with Single 32-bit Compare + RtcMode0 + 0x0 + + CTRLA + MODE0 Control A + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 2 + + MODESelect + + COUNT32 + Mode 0: 32-bit Counter + 0x0 + + + COUNT16 + Mode 1: 16-bit Counter + 0x1 + + + CLOCK + Mode 2: Clock/Calendar + 0x2 + + + + + MATCHCLR + Clear on Match + 7 + 1 + + + PRESCALER + Prescaler + 8 + 4 + + PRESCALERSelect + + OFF + CLK_RTC_CNT = GCLK_RTC/1 + 0x0 + + + DIV1 + CLK_RTC_CNT = GCLK_RTC/1 + 0x1 + + + DIV2 + CLK_RTC_CNT = GCLK_RTC/2 + 0x2 + + + DIV4 + CLK_RTC_CNT = GCLK_RTC/4 + 0x3 + + + DIV8 + CLK_RTC_CNT = GCLK_RTC/8 + 0x4 + + + DIV16 + CLK_RTC_CNT = GCLK_RTC/16 + 0x5 + + + DIV32 + CLK_RTC_CNT = GCLK_RTC/32 + 0x6 + + + DIV64 + CLK_RTC_CNT = GCLK_RTC/64 + 0x7 + + + DIV128 + CLK_RTC_CNT = GCLK_RTC/128 + 0x8 + + + DIV256 + CLK_RTC_CNT = GCLK_RTC/256 + 0x9 + + + DIV512 + CLK_RTC_CNT = GCLK_RTC/512 + 0xA + + + DIV1024 + CLK_RTC_CNT = GCLK_RTC/1024 + 0xB + + + + + COUNTSYNC + Count Read Synchronization Enable + 15 + 1 + + + + + EVCTRL + MODE0 Event Control + 0x4 + 32 + 0x00000000 + + + PEREO0 + Periodic Interval 0 Event Output Enable + 0 + 1 + + + PEREO1 + Periodic Interval 1 Event Output Enable + 1 + 1 + + + PEREO2 + Periodic Interval 2 Event Output Enable + 2 + 1 + + + PEREO3 + Periodic Interval 3 Event Output Enable + 3 + 1 + + + PEREO4 + Periodic Interval 4 Event Output Enable + 4 + 1 + + + PEREO5 + Periodic Interval 5 Event Output Enable + 5 + 1 + + + PEREO6 + Periodic Interval 6 Event Output Enable + 6 + 1 + + + PEREO7 + Periodic Interval 7 Event Output Enable + 7 + 1 + + + CMPEO0 + Compare 0 Event Output Enable + 8 + 1 + + + OVFEO + Overflow Event Output Enable + 15 + 1 + + + + + INTENCLR + MODE0 Interrupt Enable Clear + 0x8 + 16 + 0x0000 + + + PER0 + Periodic Interval 0 Interrupt Enable + 0 + 1 + + + PER1 + Periodic Interval 1 Interrupt Enable + 1 + 1 + + + PER2 + Periodic Interval 2 Interrupt Enable + 2 + 1 + + + PER3 + Periodic Interval 3 Interrupt Enable + 3 + 1 + + + PER4 + Periodic Interval 4 Interrupt Enable + 4 + 1 + + + PER5 + Periodic Interval 5 Interrupt Enable + 5 + 1 + + + PER6 + Periodic Interval 6 Interrupt Enable + 6 + 1 + + + PER7 + Periodic Interval 7 Interrupt Enable + 7 + 1 + + + CMP0 + Compare 0 Interrupt Enable + 8 + 1 + + + OVF + Overflow Interrupt Enable + 15 + 1 + + + + + INTENSET + MODE0 Interrupt Enable Set + 0xA + 16 + 0x0000 + + + PER0 + Periodic Interval 0 Interrupt Enable + 0 + 1 + + + PER1 + Periodic Interval 1 Interrupt Enable + 1 + 1 + + + PER2 + Periodic Interval 2 Interrupt Enable + 2 + 1 + + + PER3 + Periodic Interval 3 Interrupt Enable + 3 + 1 + + + PER4 + Periodic Interval 4 Interrupt Enable + 4 + 1 + + + PER5 + Periodic Interval 5 Interrupt Enable + 5 + 1 + + + PER6 + Periodic Interval 6 Interrupt Enable + 6 + 1 + + + PER7 + Periodic Interval 7 Interrupt Enable + 7 + 1 + + + CMP0 + Compare 0 Interrupt Enable + 8 + 1 + + + OVF + Overflow Interrupt Enable + 15 + 1 + + + + + INTFLAG + MODE0 Interrupt Flag Status and Clear + 0xC + 16 + 0x0000 + + + PER0 + Periodic Interval 0 + 0 + 1 + + + PER1 + Periodic Interval 1 + 1 + 1 + + + PER2 + Periodic Interval 2 + 2 + 1 + + + PER3 + Periodic Interval 3 + 3 + 1 + + + PER4 + Periodic Interval 4 + 4 + 1 + + + PER5 + Periodic Interval 5 + 5 + 1 + + + PER6 + Periodic Interval 6 + 6 + 1 + + + PER7 + Periodic Interval 7 + 7 + 1 + + + CMP0 + Compare 0 + 8 + 1 + + + OVF + Overflow + 15 + 1 + + + + + DBGCTRL + Debug Control + 0xE + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + SYNCBUSY + MODE0 Synchronization Busy Status + 0x10 + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Busy + 0 + 1 + + + ENABLE + Enable Bit Busy + 1 + 1 + + + FREQCORR + FREQCORR Register Busy + 2 + 1 + + + COUNT + COUNT Register Busy + 3 + 1 + + + COMP0 + COMP 0 Register Busy + 5 + 1 + + + COUNTSYNC + Count Read Synchronization Enable Bit Busy + 15 + 1 + + + + + FREQCORR + Frequency Correction + 0x14 + 8 + 0x00 + + + VALUE + Correction Value + 0 + 7 + + + SIGN + Correction Sign + 7 + 1 + + + + + COUNT + MODE0 Counter Value + 0x18 + 32 + 0x00000000 + + + COUNT + Counter Value + 0 + 32 + + + + + COMP + MODE0 Compare n Value + 0x20 + 32 + 0x00000000 + + + COMP + Compare Value + 0 + 32 + + + + + + MODE1 + 16-bit Counter with Two 16-bit Compares + MODE0 + RtcMode1 + 0x0 + + CTRLA + MODE1 Control A + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 2 + + MODESelect + + COUNT32 + Mode 0: 32-bit Counter + 0 + + + COUNT16 + Mode 1: 16-bit Counter + 1 + + + CLOCK + Mode 2: Clock/Calendar + 2 + + + + + PRESCALER + Prescaler + 8 + 4 + + PRESCALERSelect + + OFF + CLK_RTC_CNT = GCLK_RTC/1 + 0 + + + DIV1 + CLK_RTC_CNT = GCLK_RTC/1 + 1 + + + DIV2 + CLK_RTC_CNT = GCLK_RTC/2 + 2 + + + DIV4 + CLK_RTC_CNT = GCLK_RTC/4 + 3 + + + DIV8 + CLK_RTC_CNT = GCLK_RTC/8 + 4 + + + DIV16 + CLK_RTC_CNT = GCLK_RTC/16 + 5 + + + DIV32 + CLK_RTC_CNT = GCLK_RTC/32 + 6 + + + DIV64 + CLK_RTC_CNT = GCLK_RTC/64 + 7 + + + DIV128 + CLK_RTC_CNT = GCLK_RTC/128 + 8 + + + DIV256 + CLK_RTC_CNT = GCLK_RTC/256 + 9 + + + DIV512 + CLK_RTC_CNT = GCLK_RTC/512 + 0xA + + + DIV1024 + CLK_RTC_CNT = GCLK_RTC/1024 + 0xB + + + + + COUNTSYNC + Count Read Synchronization Enable + 15 + 1 + + + + + EVCTRL + MODE1 Event Control + 0x4 + 32 + 0x00000000 + + + PEREO0 + Periodic Interval 0 Event Output Enable + 0 + 1 + + + PEREO1 + Periodic Interval 1 Event Output Enable + 1 + 1 + + + PEREO2 + Periodic Interval 2 Event Output Enable + 2 + 1 + + + PEREO3 + Periodic Interval 3 Event Output Enable + 3 + 1 + + + PEREO4 + Periodic Interval 4 Event Output Enable + 4 + 1 + + + PEREO5 + Periodic Interval 5 Event Output Enable + 5 + 1 + + + PEREO6 + Periodic Interval 6 Event Output Enable + 6 + 1 + + + PEREO7 + Periodic Interval 7 Event Output Enable + 7 + 1 + + + CMPEO0 + Compare 0 Event Output Enable + 8 + 1 + + + CMPEO1 + Compare 1 Event Output Enable + 9 + 1 + + + OVFEO + Overflow Event Output Enable + 15 + 1 + + + + + INTENCLR + MODE1 Interrupt Enable Clear + 0x8 + 16 + 0x0000 + + + PER0 + Periodic Interval 0 Interrupt Enable + 0 + 1 + + + PER1 + Periodic Interval 1 Interrupt Enable + 1 + 1 + + + PER2 + Periodic Interval 2 Interrupt Enable + 2 + 1 + + + PER3 + Periodic Interval 3 Interrupt Enable + 3 + 1 + + + PER4 + Periodic Interval 4 Interrupt Enable + 4 + 1 + + + PER5 + Periodic Interval 5 Interrupt Enable + 5 + 1 + + + PER6 + Periodic Interval 6 Interrupt Enable + 6 + 1 + + + PER7 + Periodic Interval 7 Interrupt Enable + 7 + 1 + + + CMP0 + Compare 0 Interrupt Enable + 8 + 1 + + + CMP1 + Compare 1 Interrupt Enable + 9 + 1 + + + OVF + Overflow Interrupt Enable + 15 + 1 + + + + + INTENSET + MODE1 Interrupt Enable Set + 0xA + 16 + 0x0000 + + + PER0 + Periodic Interval 0 Interrupt Enable + 0 + 1 + + + PER1 + Periodic Interval 1 Interrupt Enable + 1 + 1 + + + PER2 + Periodic Interval 2 Interrupt Enable + 2 + 1 + + + PER3 + Periodic Interval 3 Interrupt Enable + 3 + 1 + + + PER4 + Periodic Interval 4 Interrupt Enable + 4 + 1 + + + PER5 + Periodic Interval 5 Interrupt Enable + 5 + 1 + + + PER6 + Periodic Interval 6 Interrupt Enable + 6 + 1 + + + PER7 + Periodic Interval 7 Interrupt Enable + 7 + 1 + + + CMP0 + Compare 0 Interrupt Enable + 8 + 1 + + + CMP1 + Compare 1 Interrupt Enable + 9 + 1 + + + OVF + Overflow Interrupt Enable + 15 + 1 + + + + + INTFLAG + MODE1 Interrupt Flag Status and Clear + 0xC + 16 + 0x0000 + + + PER0 + Periodic Interval 0 + 0 + 1 + + + PER1 + Periodic Interval 1 + 1 + 1 + + + PER2 + Periodic Interval 2 + 2 + 1 + + + PER3 + Periodic Interval 3 + 3 + 1 + + + PER4 + Periodic Interval 4 + 4 + 1 + + + PER5 + Periodic Interval 5 + 5 + 1 + + + PER6 + Periodic Interval 6 + 6 + 1 + + + PER7 + Periodic Interval 7 + 7 + 1 + + + CMP0 + Compare 0 + 8 + 1 + + + CMP1 + Compare 1 + 9 + 1 + + + OVF + Overflow + 15 + 1 + + + + + DBGCTRL + Debug Control + 0xE + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + SYNCBUSY + MODE1 Synchronization Busy Status + 0x10 + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Bit Busy + 0 + 1 + + + ENABLE + Enable Bit Busy + 1 + 1 + + + FREQCORR + FREQCORR Register Busy + 2 + 1 + + + COUNT + COUNT Register Busy + 3 + 1 + + + PER + PER Register Busy + 4 + 1 + + + COMP0 + COMP 0 Register Busy + 5 + 1 + + + COMP1 + COMP 1 Register Busy + 6 + 1 + + + COUNTSYNC + Count Read Synchronization Enable Bit Busy + 15 + 1 + + + + + FREQCORR + Frequency Correction + 0x14 + 8 + 0x00 + + + VALUE + Correction Value + 0 + 7 + + + SIGN + Correction Sign + 7 + 1 + + + + + COUNT + MODE1 Counter Value + 0x18 + 16 + 0x0000 + + + COUNT + Counter Value + 0 + 16 + + + + + PER + MODE1 Counter Period + 0x1C + 16 + 0x0000 + + + PER + Counter Period + 0 + 16 + + + + + 2 + 2 + COMP[%s] + MODE1 Compare n Value + 0x20 + 16 + 0x0000 + + + COMP + Compare Value + 0 + 16 + + + + + + MODE2 + Clock/Calendar with Alarm + MODE0 + RtcMode2 + 0x0 + + CTRLA + MODE2 Control A + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 2 + + MODESelect + + COUNT32 + Mode 0: 32-bit Counter + 0 + + + COUNT16 + Mode 1: 16-bit Counter + 1 + + + CLOCK + Mode 2: Clock/Calendar + 2 + + + + + CLKREP + Clock Representation + 6 + 1 + + + MATCHCLR + Clear on Match + 7 + 1 + + + PRESCALER + Prescaler + 8 + 4 + + PRESCALERSelect + + OFF + CLK_RTC_CNT = GCLK_RTC/1 + 0x0 + + + DIV1 + CLK_RTC_CNT = GCLK_RTC/1 + 0x1 + + + DIV2 + CLK_RTC_CNT = GCLK_RTC/2 + 0x2 + + + DIV4 + CLK_RTC_CNT = GCLK_RTC/4 + 0x3 + + + DIV8 + CLK_RTC_CNT = GCLK_RTC/8 + 0x4 + + + DIV16 + CLK_RTC_CNT = GCLK_RTC/16 + 0x5 + + + DIV32 + CLK_RTC_CNT = GCLK_RTC/32 + 0x6 + + + DIV64 + CLK_RTC_CNT = GCLK_RTC/64 + 0x7 + + + DIV128 + CLK_RTC_CNT = GCLK_RTC/128 + 0x8 + + + DIV256 + CLK_RTC_CNT = GCLK_RTC/256 + 0x9 + + + DIV512 + CLK_RTC_CNT = GCLK_RTC/512 + 0xA + + + DIV1024 + CLK_RTC_CNT = GCLK_RTC/1024 + 0xB + + + + + CLOCKSYNC + Clock Read Synchronization Enable + 15 + 1 + + + + + EVCTRL + MODE2 Event Control + 0x4 + 32 + 0x00000000 + + + PEREO0 + Periodic Interval 0 Event Output Enable + 0 + 1 + + + PEREO1 + Periodic Interval 1 Event Output Enable + 1 + 1 + + + PEREO2 + Periodic Interval 2 Event Output Enable + 2 + 1 + + + PEREO3 + Periodic Interval 3 Event Output Enable + 3 + 1 + + + PEREO4 + Periodic Interval 4 Event Output Enable + 4 + 1 + + + PEREO5 + Periodic Interval 5 Event Output Enable + 5 + 1 + + + PEREO6 + Periodic Interval 6 Event Output Enable + 6 + 1 + + + PEREO7 + Periodic Interval 7 Event Output Enable + 7 + 1 + + + ALARMEO0 + Alarm 0 Event Output Enable + 8 + 1 + + + OVFEO + Overflow Event Output Enable + 15 + 1 + + + + + INTENCLR + MODE2 Interrupt Enable Clear + 0x8 + 16 + 0x0000 + + + PER0 + Periodic Interval 0 Interrupt Enable + 0 + 1 + + + PER1 + Periodic Interval 1 Interrupt Enable + 1 + 1 + + + PER2 + Periodic Interval 2 Interrupt Enable + 2 + 1 + + + PER3 + Periodic Interval 3 Interrupt Enable + 3 + 1 + + + PER4 + Periodic Interval 4 Interrupt Enable + 4 + 1 + + + PER5 + Periodic Interval 5 Interrupt Enable + 5 + 1 + + + PER6 + Periodic Interval 6 Interrupt Enable + 6 + 1 + + + PER7 + Periodic Interval 7 Interrupt Enable + 7 + 1 + + + ALARM0 + Alarm 0 Interrupt Enable + 8 + 1 + + + OVF + Overflow Interrupt Enable + 15 + 1 + + + + + INTENSET + MODE2 Interrupt Enable Set + 0xA + 16 + 0x0000 + + + PER0 + Periodic Interval 0 Enable + 0 + 1 + + + PER1 + Periodic Interval 1 Enable + 1 + 1 + + + PER2 + Periodic Interval 2 Enable + 2 + 1 + + + PER3 + Periodic Interval 3 Enable + 3 + 1 + + + PER4 + Periodic Interval 4 Enable + 4 + 1 + + + PER5 + Periodic Interval 5 Enable + 5 + 1 + + + PER6 + Periodic Interval 6 Enable + 6 + 1 + + + PER7 + Periodic Interval 7 Enable + 7 + 1 + + + ALARM0 + Alarm 0 Interrupt Enable + 8 + 1 + + + OVF + Overflow Interrupt Enable + 15 + 1 + + + + + INTFLAG + MODE2 Interrupt Flag Status and Clear + 0xC + 16 + 0x0000 + + + PER0 + Periodic Interval 0 + 0 + 1 + + + PER1 + Periodic Interval 1 + 1 + 1 + + + PER2 + Periodic Interval 2 + 2 + 1 + + + PER3 + Periodic Interval 3 + 3 + 1 + + + PER4 + Periodic Interval 4 + 4 + 1 + + + PER5 + Periodic Interval 5 + 5 + 1 + + + PER6 + Periodic Interval 6 + 6 + 1 + + + PER7 + Periodic Interval 7 + 7 + 1 + + + ALARM0 + Alarm 0 + 8 + 1 + + + OVF + Overflow + 15 + 1 + + + + + DBGCTRL + Debug Control + 0xE + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + SYNCBUSY + MODE2 Synchronization Busy Status + 0x10 + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Bit Busy + 0 + 1 + + + ENABLE + Enable Bit Busy + 1 + 1 + + + FREQCORR + FREQCORR Register Busy + 2 + 1 + + + CLOCK + CLOCK Register Busy + 3 + 1 + + + ALARM0 + ALARM 0 Register Busy + 5 + 1 + + + MASK0 + MASK 0 Register Busy + 11 + 1 + + + CLOCKSYNC + Clock Read Synchronization Enable Bit Busy + 15 + 1 + + + + + FREQCORR + Frequency Correction + 0x14 + 8 + 0x00 + + + VALUE + Correction Value + 0 + 7 + + + SIGN + Correction Sign + 7 + 1 + + + + + CLOCK + MODE2 Clock Value + 0x18 + 32 + 0x00000000 + + + SECOND + Second + 0 + 6 + + + MINUTE + Minute + 6 + 6 + + + HOUR + Hour + 12 + 5 + + HOURSelect + + AM + AM when CLKREP in 12-hour + 0x00 + + + PM + PM when CLKREP in 12-hour + 0x10 + + + + + DAY + Day + 17 + 5 + + + MONTH + Month + 22 + 4 + + + YEAR + Year + 26 + 6 + + + + + ALARM + MODE2_ALARM Alarm n Value + 0x20 + 32 + 0x00000000 + + + SECOND + Second + 0 + 6 + + + MINUTE + Minute + 6 + 6 + + + HOUR + Hour + 12 + 5 + + HOURSelect + + AM + Morning hour + 0x00 + + + PM + Afternoon hour + 0x10 + + + + + DAY + Day + 17 + 5 + + + MONTH + Month + 22 + 4 + + + YEAR + Year + 26 + 6 + + + + + MASK + MODE2_ALARM Alarm n Mask + 0x24 + 8 + 0x00 + + + SEL + Alarm Mask Selection + 0 + 3 + + SELSelect + + OFF + Alarm Disabled + 0x0 + + + SS + Match seconds only + 0x1 + + + MMSS + Match seconds and minutes only + 0x2 + + + HHMMSS + Match seconds, minutes, and hours only + 0x3 + + + DDHHMMSS + Match seconds, minutes, hours, and days only + 0x4 + + + MMDDHHMMSS + Match seconds, minutes, hours, days, and months only + 0x5 + + + YYMMDDHHMMSS + Match seconds, minutes, hours, days, months, and years + 0x6 + + + + + + + + + + SERCOM0 + U22013.1.1 + Serial Communication Interface + SERCOM + SERCOM_ + 0x42000400 + + 0 + 0x31 + registers + + + SERCOM0 + 9 + + + + I2CM + I2C Master Mode + SercomI2cm + 0x0 + + CTRLA + I2CM Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run in Standby + 7 + 1 + + + PINOUT + Pin Usage + 16 + 1 + + + SDAHOLD + SDA Hold Time + 20 + 2 + + SDAHOLDSelect + + DISABLE + Disabled + 0x0 + + + 75NS + 50-100ns hold time + 0x1 + + + 450NS + 300-600ns hold time + 0x2 + + + 600NS + 400-800ns hold time + 0x3 + + + + + MEXTTOEN + Master SCL Low Extend Timeout + 22 + 1 + + + SEXTTOEN + Slave SCL Low Extend Timeout + 23 + 1 + + + SPEED + Transfer Speed + 24 + 2 + + SPEEDSelect + + STANDARD_AND_FAST_MODE + Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz + 0x0 + + + FASTPLUS_MODE + Fast-mode Plus Upto 1MHz + 0x1 + + + HIGH_SPEED_MODE + High-speed mode Upto 3.4MHz + 0x2 + + + + + SCLSM + SCL Clock Stretch Mode + 27 + 1 + + + INACTOUT + Inactive Time-Out + 28 + 2 + + INACTOUTSelect + + DISABLE + Disabled + 0x0 + + + 55US + 5-6 SCL Time-Out(50-60us) + 0x1 + + + 105US + 10-11 SCL Time-Out(100-110us) + 0x2 + + + 205US + 20-21 SCL Time-Out(200-210us) + 0x3 + + + + + LOWTOUTEN + SCL Low Timeout Enable + 30 + 1 + + + + + CTRLB + I2CM Control B + 0x4 + 32 + 0x00000000 + + + SMEN + Smart Mode Enable + 8 + 1 + + + QCEN + Quick Command Enable + 9 + 1 + + + CMD + Command + 16 + 2 + + + ACKACT + Acknowledge Action + 18 + 1 + + + + + BAUD + I2CM Baud Rate + 0xC + 32 + 0x00000000 + + + BAUD + Baud Rate Value + 0 + 8 + + + BAUDLOW + Baud Rate Value Low + 8 + 8 + + + HSBAUD + High Speed Baud Rate Value + 16 + 8 + + + HSBAUDLOW + High Speed Baud Rate Value Low + 24 + 8 + + + + + INTENCLR + I2CM Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + MB + Master On Bus Interrupt Disable + 0 + 1 + + + SB + Slave On Bus Interrupt Disable + 1 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + I2CM Interrupt Enable Set + 0x16 + 8 + 0x00 + + + MB + Master On Bus Interrupt Enable + 0 + 1 + + + SB + Slave On Bus Interrupt Enable + 1 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + I2CM Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + MB + Master On Bus Interrupt + 0 + 1 + + + SB + Slave On Bus Interrupt + 1 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + I2CM Status + 0x1A + 16 + 0x0000 + + + BUSERR + Bus Error + 0 + 1 + + + ARBLOST + Arbitration Lost + 1 + 1 + + + RXNACK + Received Not Acknowledge + 2 + 1 + + + BUSSTATE + Bus State + 4 + 2 + + + LOWTOUT + SCL Low Timeout + 6 + 1 + + + CLKHOLD + Clock Hold + 7 + 1 + + + MEXTTOUT + Master SCL Low Extend Timeout + 8 + 1 + + + SEXTTOUT + Slave SCL Low Extend Timeout + 9 + 1 + + + LENERR + Length Error + 10 + 1 + + + + + SYNCBUSY + I2CM Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + SYSOP + System Operation Synchronization Busy + 2 + 1 + + + + + ADDR + I2CM Address + 0x24 + 32 + 0x00000000 + + + ADDR + Address Value + 0 + 11 + + + LENEN + Length Enable + 13 + 1 + + + HS + High Speed Mode + 14 + 1 + + + TENBITEN + Ten Bit Addressing Enable + 15 + 1 + + + LEN + Length + 16 + 8 + + + + + DATA + I2CM Data + 0x28 + 8 + 0x00 + + + DATA + Data Value + 0 + 8 + + + + + DBGCTRL + I2CM Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + I2CS + I2C Slave Mode + I2CM + SercomI2cs + 0x0 + + CTRLA + I2CS Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + PINOUT + Pin Usage + 16 + 1 + + + SDAHOLD + SDA Hold Time + 20 + 2 + + SDAHOLDSelect + + DISABLE + Disabled + 0x0 + + + 75NS + 50-100ns hold time + 0x1 + + + 450NS + 300-600ns hold time + 0x2 + + + 600NS + 400-800ns hold time + 0x3 + + + + + SEXTTOEN + Slave SCL Low Extend Timeout + 23 + 1 + + + SPEED + Transfer Speed + 24 + 2 + + SPEEDSelect + + STANDARD_AND_FAST_MODE + Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz + 0x0 + + + FASTPLUS_MODE + Fast-mode Plus Upto 1MHz + 0x1 + + + HIGH_SPEED_MODE + High-speed mode Upto 3.4MHz + 0x2 + + + + + SCLSM + SCL Clock Stretch Mode + 27 + 1 + + + LOWTOUTEN + SCL Low Timeout Enable + 30 + 1 + + + + + CTRLB + I2CS Control B + 0x4 + 32 + 0x00000000 + + + SMEN + Smart Mode Enable + 8 + 1 + + + GCMD + PMBus Group Command + 9 + 1 + + + AACKEN + Automatic Address Acknowledge + 10 + 1 + + + AMODE + Address Mode + 14 + 2 + + + CMD + Command + 16 + 2 + + + ACKACT + Acknowledge Action + 18 + 1 + + + + + INTENCLR + I2CS Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + PREC + Stop Received Interrupt Disable + 0 + 1 + + + AMATCH + Address Match Interrupt Disable + 1 + 1 + + + DRDY + Data Interrupt Disable + 2 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + I2CS Interrupt Enable Set + 0x16 + 8 + 0x00 + + + PREC + Stop Received Interrupt Enable + 0 + 1 + + + AMATCH + Address Match Interrupt Enable + 1 + 1 + + + DRDY + Data Interrupt Enable + 2 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + I2CS Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + PREC + Stop Received Interrupt + 0 + 1 + + + AMATCH + Address Match Interrupt + 1 + 1 + + + DRDY + Data Interrupt + 2 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + I2CS Status + 0x1A + 16 + 0x0000 + + + BUSERR + Bus Error + 0 + 1 + + + COLL + Transmit Collision + 1 + 1 + + + RXNACK + Received Not Acknowledge + 2 + 1 + + + DIR + Read/Write Direction + 3 + 1 + + + SR + Repeated Start + 4 + 1 + + + LOWTOUT + SCL Low Timeout + 6 + 1 + + + CLKHOLD + Clock Hold + 7 + 1 + + + SEXTTOUT + Slave SCL Low Extend Timeout + 9 + 1 + + + HS + High Speed + 10 + 1 + + + + + SYNCBUSY + I2CS Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + + + ADDR + I2CS Address + 0x24 + 32 + 0x00000000 + + + GENCEN + General Call Address Enable + 0 + 1 + + + ADDR + Address Value + 1 + 10 + + + TENBITEN + Ten Bit Addressing Enable + 15 + 1 + + + ADDRMASK + Address Mask + 17 + 10 + + + + + DATA + I2CS Data + 0x28 + 8 + 0x00 + + + DATA + Data Value + 0 + 8 + + + + + + SPIS + SPI Slave Mode + I2CM + SercomSpis + 0x0 + + CTRLA + SPIS Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + IBON + Immediate Buffer Overflow Notification + 8 + 1 + + + DOPO + Data Out Pinout + 16 + 2 + + DOPOSelect + + PAD0 + DO on PAD[0], SCK on PAD[1] and SS on PAD[2] + 0x0 + + + PAD1 + DO on PAD[2], SCK on PAD[3] and SS on PAD[1] + 0x1 + + + PAD2 + DO on PAD[3], SCK on PAD[1] and SS on PAD[2] + 0x2 + + + PAD3 + DO on PAD[0], SCK on PAD[3] and SS on PAD[1] + 0x3 + + + + + DIPO + Data In Pinout + 20 + 2 + + DIPOSelect + + PAD0 + SERCOM PAD[0] + 0x0 + + + PAD1 + SERCOM PAD[1] + 0x1 + + + PAD2 + SERCOM PAD[2] + 0x2 + + + PAD3 + SERCOM PAD[3] + 0x3 + + + + + FORM + Frame Format + 24 + 4 + + FORMSelect + + SPI_FRAME + SPI Frame + 0x0 + + + SPI_FRAME_WITH_ADDR + SPI Frame with Addr + 0x2 + + + + + CPHA + Clock Phase + 28 + 1 + + CPHASelect + + LEADING_EDGE + The data is sampled on a leading SCK edge and changed on a trailing SCK edge + 0x0 + + + TRAILING_EDGE + The data is sampled on a trailing SCK edge and changed on a leading SCK edge + 0x1 + + + + + CPOL + Clock Polarity + 29 + 1 + + CPOLSelect + + IDLE_LOW + SCK is low when idle + 0x0 + + + IDLE_HIGH + SCK is high when idle + 0x1 + + + + + DORD + Data Order + 30 + 1 + + DORDSelect + + MSB + MSB is transferred first + 0x0 + + + LSB + LSB is transferred first + 0x1 + + + + + + + CTRLB + SPIS Control B + 0x4 + 32 + 0x00000000 + + + CHSIZE + Character Size + 0 + 3 + + CHSIZESelect + + 8_BIT + 8 bits + 0x0 + + + 9_BIT + 9 bits + 0x1 + + + + + PLOADEN + Data Preload Enable + 6 + 1 + + + SSDE + Slave Select Low Detect Enable + 9 + 1 + + + MSSEN + Master Slave Select Enable + 13 + 1 + + + AMODE + Address Mode + 14 + 2 + + AMODESelect + + MASK + SPI Address mask + 0x0 + + + 2_ADDRESSES + Two unique Addressess + 0x1 + + + RANGE + Address Range + 0x2 + + + + + RXEN + Receiver Enable + 17 + 1 + + + + + BAUD + SPIS Baud Rate + 0xC + 8 + 0x00 + + + BAUD + Baud Rate Value + 0 + 8 + + + + + INTENCLR + SPIS Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Disable + 0 + 1 + + + TXC + Transmit Complete Interrupt Disable + 1 + 1 + + + RXC + Receive Complete Interrupt Disable + 2 + 1 + + + SSL + Slave Select Low Interrupt Disable + 3 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + SPIS Interrupt Enable Set + 0x16 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Enable + 0 + 1 + + + TXC + Transmit Complete Interrupt Enable + 1 + 1 + + + RXC + Receive Complete Interrupt Enable + 2 + 1 + + + SSL + Slave Select Low Interrupt Enable + 3 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + SPIS Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt + 0 + 1 + + + TXC + Transmit Complete Interrupt + 1 + 1 + + + RXC + Receive Complete Interrupt + 2 + 1 + + + SSL + Slave Select Low Interrupt Flag + 3 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + SPIS Status + 0x1A + 16 + 0x0000 + + + BUFOVF + Buffer Overflow + 2 + 1 + + + + + SYNCBUSY + SPIS Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + CTRLB + CTRLB Synchronization Busy + 2 + 1 + + + + + ADDR + SPIS Address + 0x24 + 32 + 0x00000000 + + + ADDR + Address Value + 0 + 8 + + + ADDRMASK + Address Mask + 16 + 8 + + + + + DATA + SPIS Data + 0x28 + 32 + 0x00000000 + + + DATA + Data Value + 0 + 9 + + + + + DBGCTRL + SPIS Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + SPIM + SPI Master Mode + I2CM + SercomSpim + 0x0 + + CTRLA + SPIM Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + IBON + Immediate Buffer Overflow Notification + 8 + 1 + + + DOPO + Data Out Pinout + 16 + 2 + + DOPOSelect + + PAD0 + DO on PAD[0], SCK on PAD[1] and SS on PAD[2] + 0x0 + + + PAD1 + DO on PAD[2], SCK on PAD[3] and SS on PAD[1] + 0x1 + + + PAD2 + DO on PAD[3], SCK on PAD[1] and SS on PAD[2] + 0x2 + + + PAD3 + DO on PAD[0], SCK on PAD[3] and SS on PAD[1] + 0x3 + + + + + DIPO + Data In Pinout + 20 + 2 + + DIPOSelect + + PAD0 + SERCOM PAD[0] + 0x0 + + + PAD1 + SERCOM PAD[1] + 0x1 + + + PAD2 + SERCOM PAD[2] + 0x2 + + + PAD3 + SERCOM PAD[3] + 0x3 + + + + + FORM + Frame Format + 24 + 4 + + FORMSelect + + SPI_FRAME + SPI Frame + 0x0 + + + SPI_FRAME_WITH_ADDR + SPI Frame with Addr + 0x2 + + + + + CPHA + Clock Phase + 28 + 1 + + CPHASelect + + LEADING_EDGE + The data is sampled on a leading SCK edge and changed on a trailing SCK edge + 0x0 + + + TRAILING_EDGE + The data is sampled on a trailing SCK edge and changed on a leading SCK edge + 0x1 + + + + + CPOL + Clock Polarity + 29 + 1 + + CPOLSelect + + IDLE_LOW + SCK is low when idle + 0x0 + + + IDLE_HIGH + SCK is high when idle + 0x1 + + + + + DORD + Data Order + 30 + 1 + + DORDSelect + + MSB + MSB is transferred first + 0x0 + + + LSB + LSB is transferred first + 0x1 + + + + + + + CTRLB + SPIM Control B + 0x4 + 32 + 0x00000000 + + + CHSIZE + Character Size + 0 + 3 + + CHSIZESelect + + 8_BIT + 8 bits + 0x0 + + + 9_BIT + 9 bits + 0x1 + + + + + PLOADEN + Data Preload Enable + 6 + 1 + + + SSDE + Slave Select Low Detect Enable + 9 + 1 + + + MSSEN + Master Slave Select Enable + 13 + 1 + + + AMODE + Address Mode + 14 + 2 + + AMODESelect + + MASK + SPI Address mask + 0x0 + + + 2_ADDRESSES + Two unique Addressess + 0x1 + + + RANGE + Address Range + 0x2 + + + + + RXEN + Receiver Enable + 17 + 1 + + + + + BAUD + SPIM Baud Rate + 0xC + 8 + 0x00 + + + BAUD + Baud Rate Value + 0 + 8 + + + + + INTENCLR + SPIM Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Disable + 0 + 1 + + + TXC + Transmit Complete Interrupt Disable + 1 + 1 + + + RXC + Receive Complete Interrupt Disable + 2 + 1 + + + SSL + Slave Select Low Interrupt Disable + 3 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + SPIM Interrupt Enable Set + 0x16 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Enable + 0 + 1 + + + TXC + Transmit Complete Interrupt Enable + 1 + 1 + + + RXC + Receive Complete Interrupt Enable + 2 + 1 + + + SSL + Slave Select Low Interrupt Enable + 3 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + SPIM Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt + 0 + 1 + + + TXC + Transmit Complete Interrupt + 1 + 1 + + + RXC + Receive Complete Interrupt + 2 + 1 + + + SSL + Slave Select Low Interrupt Flag + 3 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + SPIM Status + 0x1A + 16 + 0x0000 + + + BUFOVF + Buffer Overflow + 2 + 1 + + + + + SYNCBUSY + SPIM Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + CTRLB + CTRLB Synchronization Busy + 2 + 1 + + + + + ADDR + SPIM Address + 0x24 + 32 + 0x00000000 + + + ADDR + Address Value + 0 + 8 + + + ADDRMASK + Address Mask + 16 + 8 + + + + + DATA + SPIM Data + 0x28 + 32 + 0x00000000 + + + DATA + Data Value + 0 + 9 + + + + + DBGCTRL + SPIM Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + USART_EXT + USART EXTERNAL CLOCK Mode + I2CM + SercomUsart_ext + 0x0 + + CTRLA + USART_EXT Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + IBON + Immediate Buffer Overflow Notification + 8 + 1 + + + SAMPR + Sample + 13 + 3 + + SAMPRSelect + + 16X_ARITHMETIC + 16x over-sampling using arithmetic baudrate generation + 0x0 + + + 16X_FRACTIONAL + 16x over-sampling using fractional baudrate generation + 0x1 + + + 8X_ARITHMETIC + 8x over-sampling using arithmetic baudrate generation + 0x2 + + + 8X_FRACTIONAL + 8x over-sampling using fractional baudrate generation + 0x3 + + + 3X_ARITHMETIC + 3x over-sampling using arithmetic baudrate generation + 0x4 + + + + + TXPO + Transmit Data Pinout + 16 + 2 + + TXPOSelect + + PAD0 + SERCOM PAD[0] is used for data transmission + 0x0 + + + PAD2 + SERCOM PAD[2] is used for data transmission + 0x1 + + + + + RXPO + Receive Data Pinout + 20 + 2 + + RXPOSelect + + PAD0 + SERCOM PAD[0] is used for data reception + 0x0 + + + PAD1 + SERCOM PAD[1] is used for data reception + 0x1 + + + PAD2 + SERCOM PAD[2] is used for data reception + 0x2 + + + PAD3 + SERCOM PAD[3] is used for data reception + 0x3 + + + + + SAMPA + Sample Adjustment + 22 + 2 + + + FORM + Frame Format + 24 + 4 + + FORMSelect + + USART_FRAME_NO_PARITY + USART frame + 0x0 + + + USART_FRAME_WITH_PARITY + USART frame with parity + 0x1 + + + USART_FRAME_LIN_MASTER_MODE + LIN Master - Break and sync generation + 0x2 + + + USART_FRAME_AUTO_BAUD_NO_PARITY + Auto-baud - break detection and auto-baud + 0x4 + + + USART_FRAME_AUTO_BAUD_WITH_PARITY + Auto-baud - break detection and auto-baud with parity + 0x5 + + + + + CMODE + Communication Mode + 28 + 1 + + CMODESelect + + ASYNC + Asynchronous Communication + 0x0 + + + SYNC + Synchronous Communication + 0x1 + + + + + CPOL + Clock Polarity + 29 + 1 + + CPOLSelect + + IDLE_LOW + TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge + 0x0 + + + IDLE_HIGH + TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge + 0x1 + + + + + DORD + Data Order + 30 + 1 + + DORDSelect + + MSB + MSB is transmitted first + 0x0 + + + LSB + LSB is transmitted first + 0x1 + + + + + + + CTRLB + USART_EXT Control B + 0x4 + 32 + 0x00000000 + + + CHSIZE + Character Size + 0 + 3 + + CHSIZESelect + + 8_BIT + 8 Bits + 0x0 + + + 9_BIT + 9 Bits + 0x1 + + + 5_BIT + 5 Bits + 0x5 + + + 6_BIT + 6 Bits + 0x6 + + + 7_BIT + 7 Bits + 0x7 + + + + + SBMODE + Stop Bit Mode + 6 + 1 + + SBMODESelect + + 1_BIT + One Stop Bit + 0x0 + + + 2_BIT + Two Stop Bits + 0x1 + + + + + COLDEN + Collision Detection Enable + 8 + 1 + + + SFDE + Start of Frame Detection Enable + 9 + 1 + + + ENC + Encoding Format + 10 + 1 + + + PMODE + Parity Mode + 13 + 1 + + PMODESelect + + EVEN + Even Parity + 0x0 + + + ODD + Odd Parity + 0x1 + + + + + TXEN + Transmitter Enable + 16 + 1 + + + RXEN + Receiver Enable + 17 + 1 + + + LINCMD + LIN Command + 24 + 2 + + + + + CTRLC + USART_EXT Control C + 0x8 + 32 + 0x00000000 + + + GTIME + RS485 Guard Time + 0 + 3 + + + BRKLEN + LIN Master Break Length + 8 + 2 + + + HDRDLY + LIN Master Header Delay + 10 + 2 + + + + + BAUD + USART_EXT Baud Rate + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 16 + + + + + BAUD_FRAC_MODE + USART_EXT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 13 + + + FP + Fractional Part + 13 + 3 + + + + + BAUD_FRACFP_MODE + USART_EXT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 13 + + + FP + Fractional Part + 13 + 3 + + + + + BAUD_USARTFP_MODE + USART_EXT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 16 + + + + + RXPL + USART_EXT Receive Pulse Length + 0xE + 8 + 0x00 + + + RXPL + Receive Pulse Length + 0 + 8 + + + + + INTENCLR + USART_EXT Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Disable + 0 + 1 + + + TXC + Transmit Complete Interrupt Disable + 1 + 1 + + + RXC + Receive Complete Interrupt Disable + 2 + 1 + + + RXS + Receive Start Interrupt Disable + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt Disable + 4 + 1 + + + RXBRK + Break Received Interrupt Disable + 5 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + USART_EXT Interrupt Enable Set + 0x16 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Enable + 0 + 1 + + + TXC + Transmit Complete Interrupt Enable + 1 + 1 + + + RXC + Receive Complete Interrupt Enable + 2 + 1 + + + RXS + Receive Start Interrupt Enable + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt Enable + 4 + 1 + + + RXBRK + Break Received Interrupt Enable + 5 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + USART_EXT Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt + 0 + 1 + + + TXC + Transmit Complete Interrupt + 1 + 1 + + + RXC + Receive Complete Interrupt + 2 + 1 + + + RXS + Receive Start Interrupt + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt + 4 + 1 + + + RXBRK + Break Received Interrupt + 5 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + USART_EXT Status + 0x1A + 16 + 0x0000 + + + PERR + Parity Error + 0 + 1 + + + FERR + Frame Error + 1 + 1 + + + BUFOVF + Buffer Overflow + 2 + 1 + + + CTS + Clear To Send + 3 + 1 + + + ISF + Inconsistent Sync Field + 4 + 1 + + + COLL + Collision Detected + 5 + 1 + + + TXE + Transmitter Empty + 6 + 1 + + + + + SYNCBUSY + USART_EXT Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + CTRLB + CTRLB Synchronization Busy + 2 + 1 + + + + + DATA + USART_EXT Data + 0x28 + 16 + 0x0000 + + + DATA + Data Value + 0 + 9 + + + + + DBGCTRL + USART_EXT Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + USART_INT + USART INTERNAL CLOCK Mode + I2CM + SercomUsart_int + 0x0 + + CTRLA + USART_INT Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + IBON + Immediate Buffer Overflow Notification + 8 + 1 + + + SAMPR + Sample + 13 + 3 + + SAMPRSelect + + 16X_ARITHMETIC + 16x over-sampling using arithmetic baudrate generation + 0x0 + + + 16X_FRACTIONAL + 16x over-sampling using fractional baudrate generation + 0x1 + + + 8X_ARITHMETIC + 8x over-sampling using arithmetic baudrate generation + 0x2 + + + 8X_FRACTIONAL + 8x over-sampling using fractional baudrate generation + 0x3 + + + 3X_ARITHMETIC + 3x over-sampling using arithmetic baudrate generation + 0x4 + + + + + TXPO + Transmit Data Pinout + 16 + 2 + + TXPOSelect + + PAD0 + SERCOM PAD[0] is used for data transmission + 0x0 + + + PAD2 + SERCOM PAD[2] is used for data transmission + 0x1 + + + + + RXPO + Receive Data Pinout + 20 + 2 + + RXPOSelect + + PAD0 + SERCOM PAD[0] is used for data reception + 0x0 + + + PAD1 + SERCOM PAD[1] is used for data reception + 0x1 + + + PAD2 + SERCOM PAD[2] is used for data reception + 0x2 + + + PAD3 + SERCOM PAD[3] is used for data reception + 0x3 + + + + + SAMPA + Sample Adjustment + 22 + 2 + + + FORM + Frame Format + 24 + 4 + + FORMSelect + + USART_FRAME_NO_PARITY + USART frame + 0x0 + + + USART_FRAME_WITH_PARITY + USART frame with parity + 0x1 + + + USART_FRAME_LIN_MASTER_MODE + LIN Master - Break and sync generation + 0x2 + + + USART_FRAME_AUTO_BAUD_NO_PARITY + Auto-baud - break detection and auto-baud + 0x4 + + + USART_FRAME_AUTO_BAUD_WITH_PARITY + Auto-baud - break detection and auto-baud with parity + 0x5 + + + + + CMODE + Communication Mode + 28 + 1 + + CMODESelect + + ASYNC + Asynchronous Communication + 0x0 + + + SYNC + Synchronous Communication + 0x1 + + + + + CPOL + Clock Polarity + 29 + 1 + + CPOLSelect + + IDLE_LOW + TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge + 0x0 + + + IDLE_HIGH + TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge + 0x1 + + + + + DORD + Data Order + 30 + 1 + + DORDSelect + + MSB + MSB is transmitted first + 0x0 + + + LSB + LSB is transmitted first + 0x1 + + + + + + + CTRLB + USART_INT Control B + 0x4 + 32 + 0x00000000 + + + CHSIZE + Character Size + 0 + 3 + + CHSIZESelect + + 8_BIT + 8 Bits + 0x0 + + + 9_BIT + 9 Bits + 0x1 + + + 5_BIT + 5 Bits + 0x5 + + + 6_BIT + 6 Bits + 0x6 + + + 7_BIT + 7 Bits + 0x7 + + + + + SBMODE + Stop Bit Mode + 6 + 1 + + SBMODESelect + + 1_BIT + One Stop Bit + 0x0 + + + 2_BIT + Two Stop Bits + 0x1 + + + + + COLDEN + Collision Detection Enable + 8 + 1 + + + SFDE + Start of Frame Detection Enable + 9 + 1 + + + ENC + Encoding Format + 10 + 1 + + + PMODE + Parity Mode + 13 + 1 + + PMODESelect + + EVEN + Even Parity + 0x0 + + + ODD + Odd Parity + 0x1 + + + + + TXEN + Transmitter Enable + 16 + 1 + + + RXEN + Receiver Enable + 17 + 1 + + + LINCMD + LIN Command + 24 + 2 + + + + + CTRLC + USART_INT Control C + 0x8 + 32 + 0x00000000 + + + GTIME + RS485 Guard Time + 0 + 3 + + + BRKLEN + LIN Master Break Length + 8 + 2 + + + HDRDLY + LIN Master Header Delay + 10 + 2 + + + + + BAUD + USART_INT Baud Rate + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 16 + + + + + BAUD_FRAC_MODE + USART_INT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 13 + + + FP + Fractional Part + 13 + 3 + + + + + BAUD_FRACFP_MODE + USART_INT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 13 + + + FP + Fractional Part + 13 + 3 + + + + + BAUD_USARTFP_MODE + USART_INT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 16 + + + + + RXPL + USART_INT Receive Pulse Length + 0xE + 8 + 0x00 + + + RXPL + Receive Pulse Length + 0 + 8 + + + + + INTENCLR + USART_INT Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Disable + 0 + 1 + + + TXC + Transmit Complete Interrupt Disable + 1 + 1 + + + RXC + Receive Complete Interrupt Disable + 2 + 1 + + + RXS + Receive Start Interrupt Disable + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt Disable + 4 + 1 + + + RXBRK + Break Received Interrupt Disable + 5 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + USART_INT Interrupt Enable Set + 0x16 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Enable + 0 + 1 + + + TXC + Transmit Complete Interrupt Enable + 1 + 1 + + + RXC + Receive Complete Interrupt Enable + 2 + 1 + + + RXS + Receive Start Interrupt Enable + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt Enable + 4 + 1 + + + RXBRK + Break Received Interrupt Enable + 5 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + USART_INT Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt + 0 + 1 + + + TXC + Transmit Complete Interrupt + 1 + 1 + + + RXC + Receive Complete Interrupt + 2 + 1 + + + RXS + Receive Start Interrupt + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt + 4 + 1 + + + RXBRK + Break Received Interrupt + 5 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + USART_INT Status + 0x1A + 16 + 0x0000 + + + PERR + Parity Error + 0 + 1 + + + FERR + Frame Error + 1 + 1 + + + BUFOVF + Buffer Overflow + 2 + 1 + + + CTS + Clear To Send + 3 + 1 + + + ISF + Inconsistent Sync Field + 4 + 1 + + + COLL + Collision Detected + 5 + 1 + + + TXE + Transmitter Empty + 6 + 1 + + + + + SYNCBUSY + USART_INT Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + CTRLB + CTRLB Synchronization Busy + 2 + 1 + + + + + DATA + USART_INT Data + 0x28 + 16 + 0x0000 + + + DATA + Data Value + 0 + 9 + + + + + DBGCTRL + USART_INT Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + + + SERCOM1 + 0x42000800 + + SERCOM1 + 10 + + + + SERCOM2 + 0x42000C00 + + SERCOM2 + 11 + + + + SERCOM3 + 0x42001000 + + SERCOM3 + 12 + + + + SUPC + U21172.1.1 + Supply Controller + SUPC + SUPC_ + 0x40001800 + + 0 + 0x20 + registers + + + + INTENCLR + Interrupt Enable Clear + 0x0 + 32 + 0x00000000 + + + BODVDDRDY + BODVDD Ready + 0 + 1 + + + BODVDDDET + BODVDD Detection + 1 + 1 + + + BVDDSRDY + BODVDD Synchronization Ready + 2 + 1 + + + BODCORERDY + BODCORE Ready + 3 + 1 + + + BODCOREDET + BODCORE Detection + 4 + 1 + + + BCORESRDY + BODCORE Synchronization Ready + 5 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x4 + 32 + 0x00000000 + + + BODVDDRDY + BODVDD Ready + 0 + 1 + + + BODVDDDET + BODVDD Detection + 1 + 1 + + + BVDDSRDY + BODVDD Synchronization Ready + 2 + 1 + + + BODCORERDY + BODCORE Ready + 3 + 1 + + + BODCOREDET + BODCORE Detection + 4 + 1 + + + BCORESRDY + BODCORE Synchronization Ready + 5 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x8 + 32 + 0x00000000 + + + BODVDDRDY + BODVDD Ready + 0 + 1 + + + BODVDDDET + BODVDD Detection + 1 + 1 + + + BVDDSRDY + BODVDD Synchronization Ready + 2 + 1 + + + BODCORERDY + BODCORE Ready + 3 + 1 + + + BODCOREDET + BODCORE Detection + 4 + 1 + + + BCORESRDY + BODCORE Synchronization Ready + 5 + 1 + + + + + STATUS + Power and Clocks Status + 0xC + 32 + read-only + 0x00000000 + + + BODVDDRDY + BODVDD Ready + 0 + 1 + + + BODVDDDET + BODVDD Detection + 1 + 1 + + + BVDDSRDY + BODVDD Synchronization Ready + 2 + 1 + + + BODCORERDY + BODCORE Ready + 3 + 1 + + + BODCOREDET + BODCORE Detection + 4 + 1 + + + BCORESRDY + BODCORE Synchronization Ready + 5 + 1 + + + + + BODVDD + BODVDD Control + 0x10 + 32 + 0x00000000 + + + ENABLE + Enable + 1 + 1 + + + HYST + Hysteresis Enable + 2 + 1 + + + ACTION + Action when Threshold Crossed + 3 + 2 + + ACTIONSelect + + NONE + No action + 0x0 + + + RESET + The BODVDD generates a reset + 0x1 + + + INT + The BODVDD generates an interrupt + 0x2 + + + + + STDBYCFG + Configuration in Standby mode + 5 + 1 + + + RUNSTDBY + Run during Standby + 6 + 1 + + + ACTCFG + Configuration in Active mode + 8 + 1 + + + PSEL + Prescaler Select + 12 + 4 + + PSELSelect + + DIV2 + Divide clock by 2 + 0x0 + + + DIV4 + Divide clock by 4 + 0x1 + + + DIV8 + Divide clock by 8 + 0x2 + + + DIV16 + Divide clock by 16 + 0x3 + + + DIV32 + Divide clock by 32 + 0x4 + + + DIV64 + Divide clock by 64 + 0x5 + + + DIV128 + Divide clock by 128 + 0x6 + + + DIV256 + Divide clock by 256 + 0x7 + + + DIV512 + Divide clock by 512 + 0x8 + + + DIV1024 + Divide clock by 1024 + 0x9 + + + DIV2048 + Divide clock by 2048 + 0xA + + + DIV4096 + Divide clock by 4096 + 0xB + + + DIV8192 + Divide clock by 8192 + 0xC + + + DIV16384 + Divide clock by 16384 + 0xD + + + DIV32768 + Divide clock by 32768 + 0xE + + + DIV65536 + Divide clock by 65536 + 0xF + + + + + LEVEL + Threshold Level for VDD + 16 + 6 + + + + + BODCORE + BODCORE Control + 0x14 + 32 + 0x00000000 + + + ENABLE + Enable + 1 + 1 + + + HYST + Hysteresis Enable + 2 + 1 + + + ACTION + Action when Threshold Crossed + 3 + 2 + + ACTIONSelect + + NONE + No action + 0x0 + + + RESET + The BODCORE generates a reset + 0x1 + + + INT + The BODCORE generates an interrupt + 0x2 + + + + + STDBYCFG + Configuration in Standby mode + 5 + 1 + + + RUNSTDBY + Run during Standby + 6 + 1 + + + ACTCFG + Configuration in Active mode + 8 + 1 + + + PSEL + Prescaler Select + 12 + 4 + + PSELSelect + + DIV2 + Divide clock by 2 + 0x0 + + + DIV4 + Divide clock by 4 + 0x1 + + + DIV8 + Divide clock by 8 + 0x2 + + + DIV16 + Divide clock by 16 + 0x3 + + + DIV32 + Divide clock by 32 + 0x4 + + + DIV64 + Divide clock by 64 + 0x5 + + + DIV128 + Divide clock by 128 + 0x6 + + + DIV256 + Divide clock by 256 + 0x7 + + + DIV512 + Divide clock by 512 + 0x8 + + + DIV1024 + Divide clock by 1024 + 0x9 + + + DIV2048 + Divide clock by 2048 + 0xA + + + DIV4096 + Divide clock by 4096 + 0xB + + + DIV8192 + Divide clock by 8192 + 0xC + + + DIV16384 + Divide clock by 16384 + 0xD + + + DIV32768 + Divide clock by 32768 + 0xE + + + DIV65536 + Divide clock by 65536 + 0xF + + + + + LEVEL + Threshold Level + 16 + 6 + + + + + VREG + VREG Control + 0x18 + 32 + 0x00000000 + + + ENABLE + Enable + 1 + 1 + + + RUNSTDBY + Run during Standby + 6 + 1 + + + + + VREF + VREF Control + 0x1C + 32 + 0x00000000 + + + TSEN + Temperature Sensor Output Enable + 1 + 1 + + + VREFOE + Voltage Reference Output Enable + 2 + 1 + + + RUNSTDBY + Run during Standby + 6 + 1 + + + ONDEMAND + On Demand Contrl + 7 + 1 + + + SEL + Voltage Reference Selection + 16 + 4 + + SELSelect + + 1V024 + 1.024V voltage reference typical value + 0x0 + + + 2V048 + 2.048V voltage reference typical value + 0x2 + + + 4V096 + 4.096V voltage reference typical value + 0x3 + + + + + + + + + TC0 + U22492.0.0 + Basic Timer Counter + TC + TC_ + 0x42003000 + + 0 + 0x38 + registers + + + TC0 + 20 + + + + COUNT8 + 8-bit Counter Mode + TcCount8 + 0x0 + + CTRLA + Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Timer Counter Mode + 2 + 2 + + MODESelect + + COUNT16 + Counter in 16-bit mode + 0 + + + COUNT8 + Counter in 8-bit mode + 1 + + + COUNT32 + Counter in 32-bit mode + 2 + + + + + PRESCSYNC + Prescaler and Counter Synchronization + 4 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset the counter on next generic clock + 0 + + + PRESC + Reload or reset the counter on next prescaler clock + 1 + + + RESYNC + Reload or reset the counter on next generic clock and reset the prescaler counter + 2 + + + + + RUNSTDBY + Run during Standby + 6 + 1 + + + ONDEMAND + Clock On Demand + 7 + 1 + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + Prescaler: GCLK_TC + 0 + + + DIV2 + Prescaler: GCLK_TC/2 + 1 + + + DIV4 + Prescaler: GCLK_TC/4 + 2 + + + DIV8 + Prescaler: GCLK_TC/8 + 3 + + + DIV16 + Prescaler: GCLK_TC/16 + 4 + + + DIV64 + Prescaler: GCLK_TC/64 + 5 + + + DIV256 + Prescaler: GCLK_TC/256 + 6 + + + DIV1024 + Prescaler: GCLK_TC/1024 + 7 + + + + + ALOCK + Auto Lock + 11 + 1 + + + CAPTEN0 + Capture Channel 0 Enable + 16 + 1 + + + CAPTEN1 + Capture Channel 1 Enable + 17 + 1 + + + COPEN0 + Capture On Pin 0 Enable + 20 + 1 + + + COPEN1 + Capture On Pin 1 Enable + 21 + 1 + + + + + CTRLBCLR + Control B Clear + 0x4 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot on Counter + 2 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + UPDATE + Force update of double-buffered register + 3 + + + READSYNC + Force a read synchronization of COUNT + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + CTRLBSET + Control B Set + 0x5 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot on Counter + 2 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + UPDATE + Force update of double-buffered register + 3 + + + READSYNC + Force a read synchronization of COUNT + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + EVCTRL + Event Control + 0x6 + 16 + 0x0000 + + + EVACT + Event Action + 0 + 3 + + EVACTSelect + + OFF + Event action disabled + 0 + + + RETRIGGER + Start, restart or retrigger TC on event + 1 + + + COUNT + Count on event + 2 + + + START + Start TC on event + 3 + + + STAMP + Time stamp capture + 4 + + + PPW + Period catured in CC0, pulse width in CC1 + 5 + + + PWP + Period catured in CC1, pulse width in CC0 + 6 + + + PW + Pulse width capture + 7 + + + + + TCINV + TC Event Input Polarity + 4 + 1 + + + TCEI + TC Event Enable + 5 + 1 + + + OVFEO + Event Output Enable + 8 + 1 + + + MCEO0 + MC Event Output Enable 0 + 12 + 1 + + + MCEO1 + MC Event Output Enable 1 + 13 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x8 + 8 + 0x00 + + + OVF + OVF Interrupt Disable + 0 + 1 + + + ERR + ERR Interrupt Disable + 1 + 1 + + + MC0 + MC Interrupt Disable 0 + 4 + 1 + + + MC1 + MC Interrupt Disable 1 + 5 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x9 + 8 + 0x00 + + + OVF + OVF Interrupt Enable + 0 + 1 + + + ERR + ERR Interrupt Enable + 1 + 1 + + + MC0 + MC Interrupt Enable 0 + 4 + 1 + + + MC1 + MC Interrupt Enable 1 + 5 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0xA + 8 + 0x00 + + + OVF + OVF Interrupt Flag + 0 + 1 + + + ERR + ERR Interrupt Flag + 1 + 1 + + + MC0 + MC Interrupt Flag 0 + 4 + 1 + + + MC1 + MC Interrupt Flag 1 + 5 + 1 + + + + + STATUS + Status + 0xB + 8 + 0x01 + + + STOP + Stop Status Flag + 0 + 1 + + + SLAVE + Slave Status Flag + 1 + 1 + + + PERBUFV + Synchronization Busy Status + 3 + 1 + + + CCBUFV0 + Compare channel buffer 0 valid + 4 + 1 + + + CCBUFV1 + Compare channel buffer 1 valid + 5 + 1 + + + + + WAVE + Waveform Generation Control + 0xC + 8 + 0x00 + + + WAVEGEN + Waveform Generation Mode + 0 + 2 + + WAVEGENSelect + + NFRQ + Normal frequency + 0 + + + MFRQ + Match frequency + 1 + + + NPWM + Normal PWM + 2 + + + MPWM + Match PWM + 3 + + + + + + + DRVCTRL + Control C + 0xD + 8 + 0x00 + + + INVEN0 + Output Waveform Invert Enable 0 + 0 + 1 + + + INVEN1 + Output Waveform Invert Enable 1 + 1 + 1 + + + + + DBGCTRL + Debug Control + 0xF + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + SYNCBUSY + Synchronization Status + 0x10 + 32 + read-only + 0x00000000 + + + SWRST + swrst + 0 + 1 + + + ENABLE + enable + 1 + 1 + + + CTRLB + CTRLB + 2 + 1 + + + STATUS + STATUS + 3 + 1 + + + COUNT + Counter + 4 + 1 + + + PER + Period + 5 + 1 + + + CC0 + Compare Channel 0 + 6 + 1 + + + CC1 + Compare Channel 1 + 7 + 1 + + + + + COUNT + COUNT8 Count + 0x14 + 8 + 0x00 + + + COUNT + Counter Value + 0 + 8 + + + + + PER + COUNT8 Period + 0x1B + 8 + 0xFF + + + PER + Period Value + 0 + 8 + + + + + 2 + 1 + CC[%s] + COUNT8 Compare and Capture + 0x1C + 8 + 0x00 + + + CC + Counter/Compare Value + 0 + 8 + + + + + PERBUF + COUNT8 Period Buffer + 0x2F + 8 + 0xFF + + + PERBUF + Period Buffer Value + 0 + 8 + + + + + 2 + 1 + CCBUF[%s] + COUNT8 Compare and Capture Buffer + 0x30 + 8 + 0x00 + + + CCBUF + Counter/Compare Buffer Value + 0 + 8 + + + + + + COUNT16 + 16-bit Counter Mode + COUNT8 + TcCount16 + 0x0 + + CTRLA + Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Timer Counter Mode + 2 + 2 + + MODESelect + + COUNT16 + Counter in 16-bit mode + 0 + + + COUNT8 + Counter in 8-bit mode + 1 + + + COUNT32 + Counter in 32-bit mode + 2 + + + + + PRESCSYNC + Prescaler and Counter Synchronization + 4 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset the counter on next generic clock + 0 + + + PRESC + Reload or reset the counter on next prescaler clock + 1 + + + RESYNC + Reload or reset the counter on next generic clock and reset the prescaler counter + 2 + + + + + RUNSTDBY + Run during Standby + 6 + 1 + + + ONDEMAND + Clock On Demand + 7 + 1 + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + Prescaler: GCLK_TC + 0 + + + DIV2 + Prescaler: GCLK_TC/2 + 1 + + + DIV4 + Prescaler: GCLK_TC/4 + 2 + + + DIV8 + Prescaler: GCLK_TC/8 + 3 + + + DIV16 + Prescaler: GCLK_TC/16 + 4 + + + DIV64 + Prescaler: GCLK_TC/64 + 5 + + + DIV256 + Prescaler: GCLK_TC/256 + 6 + + + DIV1024 + Prescaler: GCLK_TC/1024 + 7 + + + + + ALOCK + Auto Lock + 11 + 1 + + + CAPTEN0 + Capture Channel 0 Enable + 16 + 1 + + + CAPTEN1 + Capture Channel 1 Enable + 17 + 1 + + + COPEN0 + Capture On Pin 0 Enable + 20 + 1 + + + COPEN1 + Capture On Pin 1 Enable + 21 + 1 + + + + + CTRLBCLR + Control B Clear + 0x4 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot on Counter + 2 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + UPDATE + Force update of double-buffered register + 3 + + + READSYNC + Force a read synchronization of COUNT + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + CTRLBSET + Control B Set + 0x5 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot on Counter + 2 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + UPDATE + Force update of double-buffered register + 3 + + + READSYNC + Force a read synchronization of COUNT + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + EVCTRL + Event Control + 0x6 + 16 + 0x0000 + + + EVACT + Event Action + 0 + 3 + + EVACTSelect + + OFF + Event action disabled + 0 + + + RETRIGGER + Start, restart or retrigger TC on event + 1 + + + COUNT + Count on event + 2 + + + START + Start TC on event + 3 + + + STAMP + Time stamp capture + 4 + + + PPW + Period catured in CC0, pulse width in CC1 + 5 + + + PWP + Period catured in CC1, pulse width in CC0 + 6 + + + PW + Pulse width capture + 7 + + + + + TCINV + TC Event Input Polarity + 4 + 1 + + + TCEI + TC Event Enable + 5 + 1 + + + OVFEO + Event Output Enable + 8 + 1 + + + MCEO0 + MC Event Output Enable 0 + 12 + 1 + + + MCEO1 + MC Event Output Enable 1 + 13 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x8 + 8 + 0x00 + + + OVF + OVF Interrupt Disable + 0 + 1 + + + ERR + ERR Interrupt Disable + 1 + 1 + + + MC0 + MC Interrupt Disable 0 + 4 + 1 + + + MC1 + MC Interrupt Disable 1 + 5 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x9 + 8 + 0x00 + + + OVF + OVF Interrupt Enable + 0 + 1 + + + ERR + ERR Interrupt Enable + 1 + 1 + + + MC0 + MC Interrupt Enable 0 + 4 + 1 + + + MC1 + MC Interrupt Enable 1 + 5 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0xA + 8 + 0x00 + + + OVF + OVF Interrupt Flag + 0 + 1 + + + ERR + ERR Interrupt Flag + 1 + 1 + + + MC0 + MC Interrupt Flag 0 + 4 + 1 + + + MC1 + MC Interrupt Flag 1 + 5 + 1 + + + + + STATUS + Status + 0xB + 8 + 0x01 + + + STOP + Stop Status Flag + 0 + 1 + + + SLAVE + Slave Status Flag + 1 + 1 + + + PERBUFV + Synchronization Busy Status + 3 + 1 + + + CCBUFV0 + Compare channel buffer 0 valid + 4 + 1 + + + CCBUFV1 + Compare channel buffer 1 valid + 5 + 1 + + + + + WAVE + Waveform Generation Control + 0xC + 8 + 0x00 + + + WAVEGEN + Waveform Generation Mode + 0 + 2 + + WAVEGENSelect + + NFRQ + Normal frequency + 0 + + + MFRQ + Match frequency + 1 + + + NPWM + Normal PWM + 2 + + + MPWM + Match PWM + 3 + + + + + + + DRVCTRL + Control C + 0xD + 8 + 0x00 + + + INVEN0 + Output Waveform Invert Enable 0 + 0 + 1 + + + INVEN1 + Output Waveform Invert Enable 1 + 1 + 1 + + + + + DBGCTRL + Debug Control + 0xF + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + SYNCBUSY + Synchronization Status + 0x10 + 32 + read-only + 0x00000000 + + + SWRST + swrst + 0 + 1 + + + ENABLE + enable + 1 + 1 + + + CTRLB + CTRLB + 2 + 1 + + + STATUS + STATUS + 3 + 1 + + + COUNT + Counter + 4 + 1 + + + PER + Period + 5 + 1 + + + CC0 + Compare Channel 0 + 6 + 1 + + + CC1 + Compare Channel 1 + 7 + 1 + + + + + COUNT + COUNT16 Count + 0x14 + 16 + 0x0000 + + + COUNT + Counter Value + 0 + 16 + + + + + 2 + 2 + CC[%s] + COUNT16 Compare and Capture + 0x1C + 16 + 0x0000 + + + CC + Counter/Compare Value + 0 + 16 + + + + + 2 + 2 + CCBUF[%s] + COUNT16 Compare and Capture Buffer + 0x30 + 16 + 0x0000 + + + CCBUF + Counter/Compare Buffer Value + 0 + 16 + + + + + + COUNT32 + 32-bit Counter Mode + COUNT8 + TcCount32 + 0x0 + + CTRLA + Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Timer Counter Mode + 2 + 2 + + MODESelect + + COUNT16 + Counter in 16-bit mode + 0 + + + COUNT8 + Counter in 8-bit mode + 1 + + + COUNT32 + Counter in 32-bit mode + 2 + + + + + PRESCSYNC + Prescaler and Counter Synchronization + 4 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset the counter on next generic clock + 0 + + + PRESC + Reload or reset the counter on next prescaler clock + 1 + + + RESYNC + Reload or reset the counter on next generic clock and reset the prescaler counter + 2 + + + + + RUNSTDBY + Run during Standby + 6 + 1 + + + ONDEMAND + Clock On Demand + 7 + 1 + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + Prescaler: GCLK_TC + 0 + + + DIV2 + Prescaler: GCLK_TC/2 + 1 + + + DIV4 + Prescaler: GCLK_TC/4 + 2 + + + DIV8 + Prescaler: GCLK_TC/8 + 3 + + + DIV16 + Prescaler: GCLK_TC/16 + 4 + + + DIV64 + Prescaler: GCLK_TC/64 + 5 + + + DIV256 + Prescaler: GCLK_TC/256 + 6 + + + DIV1024 + Prescaler: GCLK_TC/1024 + 7 + + + + + ALOCK + Auto Lock + 11 + 1 + + + CAPTEN0 + Capture Channel 0 Enable + 16 + 1 + + + CAPTEN1 + Capture Channel 1 Enable + 17 + 1 + + + COPEN0 + Capture On Pin 0 Enable + 20 + 1 + + + COPEN1 + Capture On Pin 1 Enable + 21 + 1 + + + + + CTRLBCLR + Control B Clear + 0x4 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot on Counter + 2 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + UPDATE + Force update of double-buffered register + 3 + + + READSYNC + Force a read synchronization of COUNT + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + CTRLBSET + Control B Set + 0x5 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot on Counter + 2 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + UPDATE + Force update of double-buffered register + 3 + + + READSYNC + Force a read synchronization of COUNT + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + EVCTRL + Event Control + 0x6 + 16 + 0x0000 + + + EVACT + Event Action + 0 + 3 + + EVACTSelect + + OFF + Event action disabled + 0 + + + RETRIGGER + Start, restart or retrigger TC on event + 1 + + + COUNT + Count on event + 2 + + + START + Start TC on event + 3 + + + STAMP + Time stamp capture + 4 + + + PPW + Period catured in CC0, pulse width in CC1 + 5 + + + PWP + Period catured in CC1, pulse width in CC0 + 6 + + + PW + Pulse width capture + 7 + + + + + TCINV + TC Event Input Polarity + 4 + 1 + + + TCEI + TC Event Enable + 5 + 1 + + + OVFEO + Event Output Enable + 8 + 1 + + + MCEO0 + MC Event Output Enable 0 + 12 + 1 + + + MCEO1 + MC Event Output Enable 1 + 13 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x8 + 8 + 0x00 + + + OVF + OVF Interrupt Disable + 0 + 1 + + + ERR + ERR Interrupt Disable + 1 + 1 + + + MC0 + MC Interrupt Disable 0 + 4 + 1 + + + MC1 + MC Interrupt Disable 1 + 5 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x9 + 8 + 0x00 + + + OVF + OVF Interrupt Enable + 0 + 1 + + + ERR + ERR Interrupt Enable + 1 + 1 + + + MC0 + MC Interrupt Enable 0 + 4 + 1 + + + MC1 + MC Interrupt Enable 1 + 5 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0xA + 8 + 0x00 + + + OVF + OVF Interrupt Flag + 0 + 1 + + + ERR + ERR Interrupt Flag + 1 + 1 + + + MC0 + MC Interrupt Flag 0 + 4 + 1 + + + MC1 + MC Interrupt Flag 1 + 5 + 1 + + + + + STATUS + Status + 0xB + 8 + 0x01 + + + STOP + Stop Status Flag + 0 + 1 + + + SLAVE + Slave Status Flag + 1 + 1 + + + PERBUFV + Synchronization Busy Status + 3 + 1 + + + CCBUFV0 + Compare channel buffer 0 valid + 4 + 1 + + + CCBUFV1 + Compare channel buffer 1 valid + 5 + 1 + + + + + WAVE + Waveform Generation Control + 0xC + 8 + 0x00 + + + WAVEGEN + Waveform Generation Mode + 0 + 2 + + WAVEGENSelect + + NFRQ + Normal frequency + 0 + + + MFRQ + Match frequency + 1 + + + NPWM + Normal PWM + 2 + + + MPWM + Match PWM + 3 + + + + + + + DRVCTRL + Control C + 0xD + 8 + 0x00 + + + INVEN0 + Output Waveform Invert Enable 0 + 0 + 1 + + + INVEN1 + Output Waveform Invert Enable 1 + 1 + 1 + + + + + DBGCTRL + Debug Control + 0xF + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + SYNCBUSY + Synchronization Status + 0x10 + 32 + read-only + 0x00000000 + + + SWRST + swrst + 0 + 1 + + + ENABLE + enable + 1 + 1 + + + CTRLB + CTRLB + 2 + 1 + + + STATUS + STATUS + 3 + 1 + + + COUNT + Counter + 4 + 1 + + + PER + Period + 5 + 1 + + + CC0 + Compare Channel 0 + 6 + 1 + + + CC1 + Compare Channel 1 + 7 + 1 + + + + + COUNT + COUNT32 Count + 0x14 + 32 + 0x00000000 + + + COUNT + Counter Value + 0 + 32 + + + + + 2 + 4 + CC[%s] + COUNT32 Compare and Capture + 0x1C + 32 + 0x00000000 + + + CC + Counter/Compare Value + 0 + 32 + + + + + 2 + 4 + CCBUF[%s] + COUNT32 Compare and Capture Buffer + 0x30 + 32 + 0x00000000 + + + CCBUF + Counter/Compare Buffer Value + 0 + 32 + + + + + + + + TC1 + 0x42003400 + + TC1 + 21 + + + + TC2 + 0x42003800 + + TC2 + 22 + + + + TC3 + 0x42003C00 + + TC3 + 23 + + + + TC4 + 0x42004000 + + TC4 + 24 + + + + TCC0 + U22133.0.0 + Timer Counter Control + TCC + TCC_ + 0x42002400 + + 0 + 0x80 + registers + + + TCC0 + 17 + + + + CTRLA + Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + RESOLUTION + Enhanced Resolution + 5 + 2 + + RESOLUTIONSelect + + NONE + Dithering is disabled + 0 + + + DITH4 + Dithering is done every 16 PWM frames + 1 + + + DITH5 + Dithering is done every 32 PWM frames + 2 + + + DITH6 + Dithering is done every 64 PWM frames + 3 + + + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + No division + 0 + + + DIV2 + Divide by 2 + 1 + + + DIV4 + Divide by 4 + 2 + + + DIV8 + Divide by 8 + 3 + + + DIV16 + Divide by 16 + 4 + + + DIV64 + Divide by 64 + 5 + + + DIV256 + Divide by 256 + 6 + + + DIV1024 + Divide by 1024 + 7 + + + + + RUNSTDBY + Run in Standby + 11 + 1 + + + PRESCSYNC + Prescaler and Counter Synchronization Selection + 12 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset counter on next GCLK + 0 + + + PRESC + Reload or reset counter on next prescaler clock + 1 + + + RESYNC + Reload or reset counter on next GCLK and reset prescaler counter + 2 + + + + + ALOCK + Auto Lock + 14 + 1 + + + MSYNC + Master Synchronization (only for TCC Slave Instance) + 15 + 1 + + + DMAOS + DMA One-shot Trigger Mode + 23 + 1 + + + CPTEN0 + Capture Channel 0 Enable + 24 + 1 + + + CPTEN1 + Capture Channel 1 Enable + 25 + 1 + + + CPTEN2 + Capture Channel 2 Enable + 26 + 1 + + + CPTEN3 + Capture Channel 3 Enable + 27 + 1 + + + + + CTRLBCLR + Control B Clear + 0x4 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + IDXCMD + Ramp Index Command + 3 + 2 + + IDXCMDSelect + + DISABLE + Command disabled: Index toggles between cycles A and B + 0 + + + SET + Set index: cycle B will be forced in the next cycle + 1 + + + CLEAR + Clear index: cycle A will be forced in the next cycle + 2 + + + HOLD + Hold index: the next cycle will be the same as the current cycle + 3 + + + + + CMD + TCC Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Clear start, restart or retrigger + 1 + + + STOP + Force stop + 2 + + + UPDATE + Force update or double buffered registers + 3 + + + READSYNC + Force COUNT read synchronization + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + CTRLBSET + Control B Set + 0x5 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + IDXCMD + Ramp Index Command + 3 + 2 + + IDXCMDSelect + + DISABLE + Command disabled: Index toggles between cycles A and B + 0 + + + SET + Set index: cycle B will be forced in the next cycle + 1 + + + CLEAR + Clear index: cycle A will be forced in the next cycle + 2 + + + HOLD + Hold index: the next cycle will be the same as the current cycle + 3 + + + + + CMD + TCC Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Clear start, restart or retrigger + 1 + + + STOP + Force stop + 2 + + + UPDATE + Force update or double buffered registers + 3 + + + READSYNC + Force COUNT read synchronization + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + SYNCBUSY + Synchronization Busy + 0x8 + 32 + read-only + 0x00000000 + + + SWRST + Swrst Busy + 0 + 1 + + + ENABLE + Enable Busy + 1 + 1 + + + CTRLB + Ctrlb Busy + 2 + 1 + + + STATUS + Status Busy + 3 + 1 + + + COUNT + Count Busy + 4 + 1 + + + PATT + Pattern Busy + 5 + 1 + + + WAVE + Wave Busy + 6 + 1 + + + PER + Period Busy + 7 + 1 + + + CC0 + Compare Channel 0 Busy + 8 + 1 + + + CC1 + Compare Channel 1 Busy + 9 + 1 + + + CC2 + Compare Channel 2 Busy + 10 + 1 + + + CC3 + Compare Channel 3 Busy + 11 + 1 + + + + + FCTRLA + Recoverable Fault A Configuration + 0xC + 32 + 0x00000000 + + + SRC + Fault A Source + 0 + 2 + + SRCSelect + + DISABLE + Fault input disabled + 0 + + + ENABLE + MCEx (x=0,1) event input + 1 + + + INVERT + Inverted MCEx (x=0,1) event input + 2 + + + ALTFAULT + Alternate fault (A or B) state at the end of the previous period + 3 + + + + + KEEP + Fault A Keeper + 3 + 1 + + + QUAL + Fault A Qualification + 4 + 1 + + + BLANK + Fault A Blanking Mode + 5 + 2 + + BLANKSelect + + START + Blanking applied from start of the ramp + 0 + + + RISE + Blanking applied from rising edge of the output waveform + 1 + + + FALL + Blanking applied from falling edge of the output waveform + 2 + + + BOTH + Blanking applied from each toggle of the output waveform + 3 + + + + + RESTART + Fault A Restart + 7 + 1 + + + HALT + Fault A Halt Mode + 8 + 2 + + HALTSelect + + DISABLE + Halt action disabled + 0 + + + HW + Hardware halt action + 1 + + + SW + Software halt action + 2 + + + NR + Non-recoverable fault + 3 + + + + + CHSEL + Fault A Capture Channel + 10 + 2 + + CHSELSelect + + CC0 + Capture value stored in channel 0 + 0 + + + CC1 + Capture value stored in channel 1 + 1 + + + CC2 + Capture value stored in channel 2 + 2 + + + CC3 + Capture value stored in channel 3 + 3 + + + + + CAPTURE + Fault A Capture Action + 12 + 3 + + CAPTURESelect + + DISABLE + No capture + 0 + + + CAPT + Capture on fault + 1 + + + CAPTMIN + Minimum capture + 2 + + + CAPTMAX + Maximum capture + 3 + + + LOCMIN + Minimum local detection + 4 + + + LOCMAX + Maximum local detection + 5 + + + DERIV0 + Minimum and maximum local detection + 6 + + + CAPTMARK + Capture with ramp index as MSB value + 7 + + + + + BLANKPRESC + Fault A Blanking Prescaler + 15 + 1 + + + BLANKVAL + Fault A Blanking Time + 16 + 8 + + + FILTERVAL + Fault A Filter Value + 24 + 4 + + + + + FCTRLB + Recoverable Fault B Configuration + 0x10 + 32 + 0x00000000 + + + SRC + Fault B Source + 0 + 2 + + SRCSelect + + DISABLE + Fault input disabled + 0 + + + ENABLE + MCEx (x=0,1) event input + 1 + + + INVERT + Inverted MCEx (x=0,1) event input + 2 + + + ALTFAULT + Alternate fault (A or B) state at the end of the previous period + 3 + + + + + KEEP + Fault B Keeper + 3 + 1 + + + QUAL + Fault B Qualification + 4 + 1 + + + BLANK + Fault B Blanking Mode + 5 + 2 + + BLANKSelect + + START + Blanking applied from start of the ramp + 0 + + + RISE + Blanking applied from rising edge of the output waveform + 1 + + + FALL + Blanking applied from falling edge of the output waveform + 2 + + + BOTH + Blanking applied from each toggle of the output waveform + 3 + + + + + RESTART + Fault B Restart + 7 + 1 + + + HALT + Fault B Halt Mode + 8 + 2 + + HALTSelect + + DISABLE + Halt action disabled + 0 + + + HW + Hardware halt action + 1 + + + SW + Software halt action + 2 + + + NR + Non-recoverable fault + 3 + + + + + CHSEL + Fault B Capture Channel + 10 + 2 + + CHSELSelect + + CC0 + Capture value stored in channel 0 + 0 + + + CC1 + Capture value stored in channel 1 + 1 + + + CC2 + Capture value stored in channel 2 + 2 + + + CC3 + Capture value stored in channel 3 + 3 + + + + + CAPTURE + Fault B Capture Action + 12 + 3 + + CAPTURESelect + + DISABLE + No capture + 0 + + + CAPT + Capture on fault + 1 + + + CAPTMIN + Minimum capture + 2 + + + CAPTMAX + Maximum capture + 3 + + + LOCMIN + Minimum local detection + 4 + + + LOCMAX + Maximum local detection + 5 + + + DERIV0 + Minimum and maximum local detection + 6 + + + CAPTMARK + Capture with ramp index as MSB value + 7 + + + + + BLANKPRESC + Fault B Blanking Prescaler + 15 + 1 + + + BLANKVAL + Fault B Blanking Time + 16 + 8 + + + FILTERVAL + Fault B Filter Value + 24 + 4 + + + + + WEXCTRL + Waveform Extension Configuration + 0x14 + 32 + 0x00000000 + + + OTMX + Output Matrix + 0 + 2 + + + DTIEN0 + Dead-time Insertion Generator 0 Enable + 8 + 1 + + + DTIEN1 + Dead-time Insertion Generator 1 Enable + 9 + 1 + + + DTIEN2 + Dead-time Insertion Generator 2 Enable + 10 + 1 + + + DTIEN3 + Dead-time Insertion Generator 3 Enable + 11 + 1 + + + DTLS + Dead-time Low Side Outputs Value + 16 + 8 + + + DTHS + Dead-time High Side Outputs Value + 24 + 8 + + + + + DRVCTRL + Driver Control + 0x18 + 32 + 0x00000000 + + + NRE0 + Non-Recoverable State 0 Output Enable + 0 + 1 + + + NRE1 + Non-Recoverable State 1 Output Enable + 1 + 1 + + + NRE2 + Non-Recoverable State 2 Output Enable + 2 + 1 + + + NRE3 + Non-Recoverable State 3 Output Enable + 3 + 1 + + + NRE4 + Non-Recoverable State 4 Output Enable + 4 + 1 + + + NRE5 + Non-Recoverable State 5 Output Enable + 5 + 1 + + + NRE6 + Non-Recoverable State 6 Output Enable + 6 + 1 + + + NRE7 + Non-Recoverable State 7 Output Enable + 7 + 1 + + + NRV0 + Non-Recoverable State 0 Output Value + 8 + 1 + + + NRV1 + Non-Recoverable State 1 Output Value + 9 + 1 + + + NRV2 + Non-Recoverable State 2 Output Value + 10 + 1 + + + NRV3 + Non-Recoverable State 3 Output Value + 11 + 1 + + + NRV4 + Non-Recoverable State 4 Output Value + 12 + 1 + + + NRV5 + Non-Recoverable State 5 Output Value + 13 + 1 + + + NRV6 + Non-Recoverable State 6 Output Value + 14 + 1 + + + NRV7 + Non-Recoverable State 7 Output Value + 15 + 1 + + + INVEN0 + Output Waveform 0 Inversion + 16 + 1 + + + INVEN1 + Output Waveform 1 Inversion + 17 + 1 + + + INVEN2 + Output Waveform 2 Inversion + 18 + 1 + + + INVEN3 + Output Waveform 3 Inversion + 19 + 1 + + + INVEN4 + Output Waveform 4 Inversion + 20 + 1 + + + INVEN5 + Output Waveform 5 Inversion + 21 + 1 + + + INVEN6 + Output Waveform 6 Inversion + 22 + 1 + + + INVEN7 + Output Waveform 7 Inversion + 23 + 1 + + + FILTERVAL0 + Non-Recoverable Fault Input 0 Filter Value + 24 + 4 + + + FILTERVAL1 + Non-Recoverable Fault Input 1 Filter Value + 28 + 4 + + + + + DBGCTRL + Debug Control + 0x1E + 8 + 0x00 + + + DBGRUN + Debug Running Mode + 0 + 1 + + + FDDBD + Fault Detection on Debug Break Detection + 2 + 1 + + + + + EVCTRL + Event Control + 0x20 + 32 + 0x00000000 + + + EVACT0 + Timer/counter Input Event0 Action + 0 + 3 + + EVACT0Select + + OFF + Event action disabled + 0 + + + RETRIGGER + Start, restart or re-trigger counter on event + 1 + + + COUNTEV + Count on event + 2 + + + START + Start counter on event + 3 + + + INC + Increment counter on event + 4 + + + COUNT + Count on active state of asynchronous event + 5 + + + STAMP + Stamp capture + 6 + + + FAULT + Non-recoverable fault + 7 + + + + + EVACT1 + Timer/counter Input Event1 Action + 3 + 3 + + EVACT1Select + + OFF + Event action disabled + 0 + + + RETRIGGER + Re-trigger counter on event + 1 + + + DIR + Direction control + 2 + + + STOP + Stop counter on event + 3 + + + DEC + Decrement counter on event + 4 + + + PPW + Period capture value in CC0 register, pulse width capture value in CC1 register + 5 + + + PWP + Period capture value in CC1 register, pulse width capture value in CC0 register + 6 + + + FAULT + Non-recoverable fault + 7 + + + + + CNTSEL + Timer/counter Output Event Mode + 6 + 2 + + CNTSELSelect + + START + An interrupt/event is generated when a new counter cycle starts + 0 + + + END + An interrupt/event is generated when a counter cycle ends + 1 + + + BETWEEN + An interrupt/event is generated when a counter cycle ends, except for the first and last cycles + 2 + + + BOUNDARY + An interrupt/event is generated when a new counter cycle starts or a counter cycle ends + 3 + + + + + OVFEO + Overflow/Underflow Output Event Enable + 8 + 1 + + + TRGEO + Retrigger Output Event Enable + 9 + 1 + + + CNTEO + Timer/counter Output Event Enable + 10 + 1 + + + TCINV0 + Inverted Event 0 Input Enable + 12 + 1 + + + TCINV1 + Inverted Event 1 Input Enable + 13 + 1 + + + TCEI0 + Timer/counter Event 0 Input Enable + 14 + 1 + + + TCEI1 + Timer/counter Event 1 Input Enable + 15 + 1 + + + MCEI0 + Match or Capture Channel 0 Event Input Enable + 16 + 1 + + + MCEI1 + Match or Capture Channel 1 Event Input Enable + 17 + 1 + + + MCEI2 + Match or Capture Channel 2 Event Input Enable + 18 + 1 + + + MCEI3 + Match or Capture Channel 3 Event Input Enable + 19 + 1 + + + MCEO0 + Match or Capture Channel 0 Event Output Enable + 24 + 1 + + + MCEO1 + Match or Capture Channel 1 Event Output Enable + 25 + 1 + + + MCEO2 + Match or Capture Channel 2 Event Output Enable + 26 + 1 + + + MCEO3 + Match or Capture Channel 3 Event Output Enable + 27 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x24 + 32 + 0x00000000 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + TRG + Retrigger Interrupt Enable + 1 + 1 + + + CNT + Counter Interrupt Enable + 2 + 1 + + + ERR + Error Interrupt Enable + 3 + 1 + + + UFS + Non-Recoverable Update Fault Interrupt Enable + 10 + 1 + + + DFS + Non-Recoverable Debug Fault Interrupt Enable + 11 + 1 + + + FAULTA + Recoverable Fault A Interrupt Enable + 12 + 1 + + + FAULTB + Recoverable Fault B Interrupt Enable + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 Interrupt Enable + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 Interrupt Enable + 15 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 16 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 17 + 1 + + + MC2 + Match or Capture Channel 2 Interrupt Enable + 18 + 1 + + + MC3 + Match or Capture Channel 3 Interrupt Enable + 19 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x28 + 32 + 0x00000000 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + TRG + Retrigger Interrupt Enable + 1 + 1 + + + CNT + Counter Interrupt Enable + 2 + 1 + + + ERR + Error Interrupt Enable + 3 + 1 + + + UFS + Non-Recoverable Update Fault Interrupt Enable + 10 + 1 + + + DFS + Non-Recoverable Debug Fault Interrupt Enable + 11 + 1 + + + FAULTA + Recoverable Fault A Interrupt Enable + 12 + 1 + + + FAULTB + Recoverable Fault B Interrupt Enable + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 Interrupt Enable + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 Interrupt Enable + 15 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 16 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 17 + 1 + + + MC2 + Match or Capture Channel 2 Interrupt Enable + 18 + 1 + + + MC3 + Match or Capture Channel 3 Interrupt Enable + 19 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x2C + 32 + 0x00000000 + + + OVF + Overflow + 0 + 1 + + + TRG + Retrigger + 1 + 1 + + + CNT + Counter + 2 + 1 + + + ERR + Error + 3 + 1 + + + UFS + Non-Recoverable Update Fault + 10 + 1 + + + DFS + Non-Recoverable Debug Fault + 11 + 1 + + + FAULTA + Recoverable Fault A + 12 + 1 + + + FAULTB + Recoverable Fault B + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 + 15 + 1 + + + MC0 + Match or Capture 0 + 16 + 1 + + + MC1 + Match or Capture 1 + 17 + 1 + + + MC2 + Match or Capture 2 + 18 + 1 + + + MC3 + Match or Capture 3 + 19 + 1 + + + + + STATUS + Status + 0x30 + 32 + 0x00000001 + + + STOP + Stop + 0 + 1 + + + IDX + Ramp + 1 + 1 + + + UFS + Non-recoverable Update Fault State + 2 + 1 + + + DFS + Non-Recoverable Debug Fault State + 3 + 1 + + + SLAVE + Slave + 4 + 1 + + + PATTBUFV + Pattern Buffer Valid + 5 + 1 + + + PERBUFV + Period Buffer Valid + 7 + 1 + + + FAULTAIN + Recoverable Fault A Input + 8 + 1 + + + FAULTBIN + Recoverable Fault B Input + 9 + 1 + + + FAULT0IN + Non-Recoverable Fault0 Input + 10 + 1 + + + FAULT1IN + Non-Recoverable Fault1 Input + 11 + 1 + + + FAULTA + Recoverable Fault A State + 12 + 1 + + + FAULTB + Recoverable Fault B State + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 State + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 State + 15 + 1 + + + CCBUFV0 + Compare Channel 0 Buffer Valid + 16 + 1 + + + CCBUFV1 + Compare Channel 1 Buffer Valid + 17 + 1 + + + CCBUFV2 + Compare Channel 2 Buffer Valid + 18 + 1 + + + CCBUFV3 + Compare Channel 3 Buffer Valid + 19 + 1 + + + CMP0 + Compare Channel 0 Value + 24 + 1 + + + CMP1 + Compare Channel 1 Value + 25 + 1 + + + CMP2 + Compare Channel 2 Value + 26 + 1 + + + CMP3 + Compare Channel 3 Value + 27 + 1 + + + + + COUNT + Count + 0x34 + 32 + 0x00000000 + + + COUNT + Counter Value + 0 + 24 + + + + + COUNT_DITH4_MODE + Count + COUNT + 0x34 + 32 + 0x00000000 + + + COUNT + Counter Value + 4 + 20 + + + + + COUNT_DITH5_MODE + Count + COUNT + 0x34 + 32 + 0x00000000 + + + COUNT + Counter Value + 5 + 19 + + + + + COUNT_DITH6_MODE + Count + COUNT + 0x34 + 32 + 0x00000000 + + + COUNT + Counter Value + 6 + 18 + + + + + PATT + Pattern + 0x38 + 16 + 0x0000 + + + PGE0 + Pattern Generator 0 Output Enable + 0 + 1 + + + PGE1 + Pattern Generator 1 Output Enable + 1 + 1 + + + PGE2 + Pattern Generator 2 Output Enable + 2 + 1 + + + PGE3 + Pattern Generator 3 Output Enable + 3 + 1 + + + PGE4 + Pattern Generator 4 Output Enable + 4 + 1 + + + PGE5 + Pattern Generator 5 Output Enable + 5 + 1 + + + PGE6 + Pattern Generator 6 Output Enable + 6 + 1 + + + PGE7 + Pattern Generator 7 Output Enable + 7 + 1 + + + PGV0 + Pattern Generator 0 Output Value + 8 + 1 + + + PGV1 + Pattern Generator 1 Output Value + 9 + 1 + + + PGV2 + Pattern Generator 2 Output Value + 10 + 1 + + + PGV3 + Pattern Generator 3 Output Value + 11 + 1 + + + PGV4 + Pattern Generator 4 Output Value + 12 + 1 + + + PGV5 + Pattern Generator 5 Output Value + 13 + 1 + + + PGV6 + Pattern Generator 6 Output Value + 14 + 1 + + + PGV7 + Pattern Generator 7 Output Value + 15 + 1 + + + + + WAVE + Waveform Control + 0x3C + 32 + 0x00000000 + + + WAVEGEN + Waveform Generation + 0 + 3 + + WAVEGENSelect + + NFRQ + Normal frequency + 0 + + + MFRQ + Match frequency + 1 + + + NPWM + Normal PWM + 2 + + + DSCRITICAL + Dual-slope critical + 4 + + + DSBOTTOM + Dual-slope with interrupt/event condition when COUNT reaches ZERO + 5 + + + DSBOTH + Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP + 6 + + + DSTOP + Dual-slope with interrupt/event condition when COUNT reaches TOP + 7 + + + + + RAMP + Ramp Mode + 4 + 2 + + RAMPSelect + + RAMP1 + RAMP1 operation + 0 + + + RAMP2A + Alternative RAMP2 operation + 1 + + + RAMP2 + RAMP2 operation + 2 + + + RAMP2C + Critical RAMP2 operation + 3 + + + + + CIPEREN + Circular period Enable + 7 + 1 + + + CICCEN0 + Circular Channel 0 Enable + 8 + 1 + + + CICCEN1 + Circular Channel 1 Enable + 9 + 1 + + + CICCEN2 + Circular Channel 2 Enable + 10 + 1 + + + CICCEN3 + Circular Channel 3 Enable + 11 + 1 + + + POL0 + Channel 0 Polarity + 16 + 1 + + + POL1 + Channel 1 Polarity + 17 + 1 + + + POL2 + Channel 2 Polarity + 18 + 1 + + + POL3 + Channel 3 Polarity + 19 + 1 + + + SWAP0 + Swap DTI Output Pair 0 + 24 + 1 + + + SWAP1 + Swap DTI Output Pair 1 + 25 + 1 + + + SWAP2 + Swap DTI Output Pair 2 + 26 + 1 + + + SWAP3 + Swap DTI Output Pair 3 + 27 + 1 + + + + + PER + Period + 0x40 + 32 + 0xFFFFFFFF + + + PER + Period Value + 0 + 24 + + + + + PER_DITH4_MODE + Period + PER + 0x40 + 32 + 0xFFFFFFFF + + + DITHER + Dithering Cycle Number + 0 + 4 + + + PER + Period Value + 4 + 20 + + + + + PER_DITH5_MODE + Period + PER + 0x40 + 32 + 0xFFFFFFFF + + + DITHER + Dithering Cycle Number + 0 + 5 + + + PER + Period Value + 5 + 19 + + + + + PER_DITH6_MODE + Period + PER + 0x40 + 32 + 0xFFFFFFFF + + + DITHER + Dithering Cycle Number + 0 + 6 + + + PER + Period Value + 6 + 18 + + + + + 4 + 4 + CC[%s] + Compare and Capture + 0x44 + 32 + 0x00000000 + + + CC + Channel Compare/Capture Value + 0 + 24 + + + + + 4 + 4 + CC_DITH4_MODE[%s] + Compare and Capture + CC[%s] + 0x44 + 32 + 0x00000000 + + + DITHER + Dithering Cycle Number + 0 + 4 + + + CC + Channel Compare/Capture Value + 4 + 20 + + + + + 4 + 4 + CC_DITH5_MODE[%s] + Compare and Capture + CC[%s] + 0x44 + 32 + 0x00000000 + + + DITHER + Dithering Cycle Number + 0 + 5 + + + CC + Channel Compare/Capture Value + 5 + 19 + + + + + 4 + 4 + CC_DITH6_MODE[%s] + Compare and Capture + CC[%s] + 0x44 + 32 + 0x00000000 + + + DITHER + Dithering Cycle Number + 0 + 6 + + + CC + Channel Compare/Capture Value + 6 + 18 + + + + + PATTBUF + Pattern Buffer + 0x64 + 16 + 0x0000 + + + PGEB0 + Pattern Generator 0 Output Enable Buffer + 0 + 1 + + + PGEB1 + Pattern Generator 1 Output Enable Buffer + 1 + 1 + + + PGEB2 + Pattern Generator 2 Output Enable Buffer + 2 + 1 + + + PGEB3 + Pattern Generator 3 Output Enable Buffer + 3 + 1 + + + PGEB4 + Pattern Generator 4 Output Enable Buffer + 4 + 1 + + + PGEB5 + Pattern Generator 5 Output Enable Buffer + 5 + 1 + + + PGEB6 + Pattern Generator 6 Output Enable Buffer + 6 + 1 + + + PGEB7 + Pattern Generator 7 Output Enable Buffer + 7 + 1 + + + PGVB0 + Pattern Generator 0 Output Enable + 8 + 1 + + + PGVB1 + Pattern Generator 1 Output Enable + 9 + 1 + + + PGVB2 + Pattern Generator 2 Output Enable + 10 + 1 + + + PGVB3 + Pattern Generator 3 Output Enable + 11 + 1 + + + PGVB4 + Pattern Generator 4 Output Enable + 12 + 1 + + + PGVB5 + Pattern Generator 5 Output Enable + 13 + 1 + + + PGVB6 + Pattern Generator 6 Output Enable + 14 + 1 + + + PGVB7 + Pattern Generator 7 Output Enable + 15 + 1 + + + + + PERBUF + Period Buffer + 0x6C + 32 + 0xFFFFFFFF + + + PERBUF + Period Buffer Value + 0 + 24 + + + + + PERBUF_DITH4_MODE + Period Buffer + PERBUF + 0x6C + 32 + 0xFFFFFFFF + + + DITHERBUF + Dithering Buffer Cycle Number + 0 + 4 + + + PERBUF + Period Buffer Value + 4 + 20 + + + + + PERBUF_DITH5_MODE + Period Buffer + PERBUF + 0x6C + 32 + 0xFFFFFFFF + + + DITHERBUF + Dithering Buffer Cycle Number + 0 + 5 + + + PERBUF + Period Buffer Value + 5 + 19 + + + + + PERBUF_DITH6_MODE + Period Buffer + PERBUF + 0x6C + 32 + 0xFFFFFFFF + + + DITHERBUF + Dithering Buffer Cycle Number + 0 + 6 + + + PERBUF + Period Buffer Value + 6 + 18 + + + + + 4 + 4 + CCBUF[%s] + Compare and Capture Buffer + 0x70 + 32 + 0x00000000 + + + CCBUF + Channel Compare/Capture Buffer Value + 0 + 24 + + + + + 4 + 4 + CCBUF_DITH4_MODE[%s] + Compare and Capture Buffer + CCBUF[%s] + 0x70 + 32 + 0x00000000 + + + CCBUF + Channel Compare/Capture Buffer Value + 0 + 4 + + + DITHERBUF + Dithering Buffer Cycle Number + 4 + 20 + + + + + 4 + 4 + CCBUF_DITH5_MODE[%s] + Compare and Capture Buffer + CCBUF[%s] + 0x70 + 32 + 0x00000000 + + + DITHERBUF + Dithering Buffer Cycle Number + 0 + 5 + + + CCBUF + Channel Compare/Capture Buffer Value + 5 + 19 + + + + + 4 + 4 + CCBUF_DITH6_MODE[%s] + Compare and Capture Buffer + CCBUF[%s] + 0x70 + 32 + 0x00000000 + + + DITHERBUF + Dithering Buffer Cycle Number + 0 + 6 + + + CCBUF + Channel Compare/Capture Buffer Value + 6 + 18 + + + + + + + TCC1 + 0x42002800 + + TCC1 + 18 + + + + TCC2 + 0x42002C00 + + TCC2 + 19 + + + + WDT + U22511.0.1 + Watchdog Timer + WDT + WDT_ + 0x40002000 + + 0 + 0xD + registers + + + WDT + 1 + + + + CTRLA + Control + 0x0 + 8 + 0x00 + + + ENABLE + Enable + 1 + 1 + + + WEN + Watchdog Timer Window Mode Enable + 2 + 1 + + + ALWAYSON + Always-On + 7 + 1 + + + + + CONFIG + Configuration + 0x1 + 8 + 0xBB + + + PER + Time-Out Period + 0 + 4 + + PERSelect + + CYC8 + 8 clock cycles + 0x0 + + + CYC16 + 16 clock cycles + 0x1 + + + CYC32 + 32 clock cycles + 0x2 + + + CYC64 + 64 clock cycles + 0x3 + + + CYC128 + 128 clock cycles + 0x4 + + + CYC256 + 256 clock cycles + 0x5 + + + CYC512 + 512 clock cycles + 0x6 + + + CYC1024 + 1024 clock cycles + 0x7 + + + CYC2048 + 2048 clock cycles + 0x8 + + + CYC4096 + 4096 clock cycles + 0x9 + + + CYC8192 + 8192 clock cycles + 0xA + + + CYC16384 + 16384 clock cycles + 0xB + + + + + WINDOW + Window Mode Time-Out Period + 4 + 4 + + WINDOWSelect + + CYC8 + 8 clock cycles + 0x0 + + + CYC16 + 16 clock cycles + 0x1 + + + CYC32 + 32 clock cycles + 0x2 + + + CYC64 + 64 clock cycles + 0x3 + + + CYC128 + 128 clock cycles + 0x4 + + + CYC256 + 256 clock cycles + 0x5 + + + CYC512 + 512 clock cycles + 0x6 + + + CYC1024 + 1024 clock cycles + 0x7 + + + CYC2048 + 2048 clock cycles + 0x8 + + + CYC4096 + 4096 clock cycles + 0x9 + + + CYC8192 + 8192 clock cycles + 0xA + + + CYC16384 + 16384 clock cycles + 0xB + + + + + + + EWCTRL + Early Warning Interrupt Control + 0x2 + 8 + 0x0B + + + EWOFFSET + Early Warning Interrupt Time Offset + 0 + 4 + + EWOFFSETSelect + + CYC8 + 8 clock cycles + 0x0 + + + CYC16 + 16 clock cycles + 0x1 + + + CYC32 + 32 clock cycles + 0x2 + + + CYC64 + 64 clock cycles + 0x3 + + + CYC128 + 128 clock cycles + 0x4 + + + CYC256 + 256 clock cycles + 0x5 + + + CYC512 + 512 clock cycles + 0x6 + + + CYC1024 + 1024 clock cycles + 0x7 + + + CYC2048 + 2048 clock cycles + 0x8 + + + CYC4096 + 4096 clock cycles + 0x9 + + + CYC8192 + 8192 clock cycles + 0xA + + + CYC16384 + 16384 clock cycles + 0xB + + + + + + + INTENCLR + Interrupt Enable Clear + 0x4 + 8 + 0x00 + + + EW + Early Warning Interrupt Enable + 0 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x5 + 8 + 0x00 + + + EW + Early Warning Interrupt Enable + 0 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x6 + 8 + 0x00 + + + EW + Early Warning + 0 + 1 + + + + + SYNCBUSY + Synchronization Busy + 0x8 + 32 + read-only + 0x00000000 + + + ENABLE + Enable Busy + 1 + 1 + + + WEN + Window Enable Busy + 2 + 1 + + + ALWAYSON + Always-On Busy + 3 + 1 + + + CLEAR + Clear Busy + 4 + 1 + + + + + CLEAR + Clear + 0xC + 8 + write-only + 0x00 + + + CLEAR + Watchdog Clear + 0 + 8 + + CLEARSelect + + KEY + Clear Key + 0xA5 + + + + + + + + + MPU + Memory Protection Unit + MPU + MPU_ + 0xE000ED90 + + 0 + 0x14 + registers + + + + TYPE + MPU Type Register + 0x0 + 32 + read-only + + + SEPARATE + Separate instruction and Data Memory MapsRegions + 0 + 1 + + + DREGION + Number of Data Regions + 8 + 8 + + + IREGION + Number of Instruction Regions + 16 + 8 + + + + + CTRL + MPU Control Register + 0x4 + 32 + + + ENABLE + MPU Enable + 0 + 1 + + + HFNMIENA + Enable Hard Fault and NMI handlers + 1 + 1 + + + PRIVDEFENA + Enables privileged software access to default memory map + 2 + 1 + + + + + RNR + MPU Region Number Register + 0x8 + 32 + + + REGION + Region referenced by RBAR and RASR + 0 + 8 + + + + + RBAR + MPU Region Base Address Register + 0xC + 32 + + + REGION + Region number + 0 + 4 + + + VALID + Region number valid + 4 + 1 + + + ADDR + Region base address + 5 + 27 + + + + + RASR + MPU Region Attribute and Size Register + 0x10 + 32 + + + ENABLE + Region Enable + 0 + 1 + + + SIZE + Region Size + 1 + 5 + + + SRD + Sub-region disable + 8 + 8 + + + B + Bufferable bit + 16 + 1 + + + C + Cacheable bit + 17 + 1 + + + S + Shareable bit + 18 + 1 + + + TEX + TEX bit + 19 + 3 + + + AP + Access Permission + 24 + 3 + + + XN + Execute Never Attribute + 28 + 1 + + + + + + + NVIC + Nested Vectored Interrupt Controller + NVIC + NVIC_ + 0xE000E100 + + 0 + 0x320 + registers + + + + ISER + Interrupt Set Enable Register + 0x0 + 32 + 0x00000000 + + + SETENA + Interrupt set enable bits + 0 + 31 + + + + + ICER + Interrupt Clear Enable Register + 0x80 + 32 + 0x00000000 + + + CLRENA + Interrupt clear-enable bits + 0 + 31 + + + + + ISPR + Interrupt Set Pending Register + 0x100 + 32 + 0x00000000 + + + SETPEND + Interrupt set-pending bits + 0 + 31 + + + + + ICPR + Interrupt Clear Pending Register + 0x180 + 32 + 0x00000000 + + + CLRPEND + Interrupt clear-pending bits + 0 + 31 + + + + + 8 + 4 + IPR[%s] + Interrupt Priority Register n + 0x300 + 32 + 0x00000000 + + + PRI0 + Priority of interrupt n + 0 + 2 + + + PRI1 + Priority of interrupt n + 8 + 2 + + + PRI2 + Priority of interrupt n + 16 + 2 + + + PRI3 + Priority of interrupt n + 24 + 2 + + + + + + + SysTick + System timer + SysTick + SysTick_ + 0xE000E010 + + 0 + 0x10 + registers + + + + CSR + SysTick Control and Status Register + 0x0 + 32 + 0x4 + + + ENABLE + SysTick Counter Enable + 0 + 1 + + ENABLESelect + + VALUE_0 + Counter disabled + 0 + + + VALUE_1 + Counter enabled + 1 + + + + + TICKINT + SysTick Exception Request Enable + 1 + 1 + + TICKINTSelect + + VALUE_0 + Counting down to 0 does not assert the SysTick exception request + 0 + + + VALUE_1 + Counting down to 0 asserts the SysTick exception request + 1 + + + + + CLKSOURCE + Clock Source 0=external, 1=processor + 2 + 1 + + CLKSOURCESelect + + VALUE_0 + External clock + 0 + + + VALUE_1 + Processor clock + 1 + + + + + COUNTFLAG + Timer counted to 0 since last read of register + 16 + 1 + + + + + RVR + SysTick Reload Value Register + 0x4 + 32 + + + RELOAD + Value to load into the SysTick Current Value Register when the counter reaches 0 + 0 + 24 + + + + + CVR + SysTick Current Value Register + 0x8 + 32 + + + CURRENT + Current value at the time the register is accessed + 0 + 24 + + + + + CALIB + SysTick Calibration Value Register + 0xC + 32 + read-only + 0 + + + TENMS + Reload value to use for 10ms timing + 0 + 24 + + + SKEW + TENMS is rounded from non-integer ratio + 30 + 1 + + SKEWSelect + + VALUE_0 + 10ms calibration value is exact + 0 + + + VALUE_1 + 10ms calibration value is inexact, because of the clock frequency + 1 + + + + + NOREF + No Separate Reference Clock + 31 + 1 + + NOREFSelect + + VALUE_0 + The reference clock is provided + 0 + + + VALUE_1 + The reference clock is not provided + 1 + + + + + + + + + SystemControl + System Control Registers + SystemControl + SystemControl_ + 0xE000E000 + + 0 + 0xD34 + registers + + + + CPUID + CPUID Base Register + 0xD00 + 32 + read-only + 0x410CC601 + + + REVISION + Minor revision number + 0 + 4 + + + PARTNO + Processor Part Number, 0xC60=Cortex-M0+ + 4 + 12 + + + ARCHITECTURE + Processor Architecture, 0xC=ARMv6-M + 16 + 4 + + + VARIANT + Major revision number + 20 + 4 + + + IMPLEMENTER + Implementer code, ARM=0x41 + 24 + 8 + + + + + ICSR + Interrupt Control and State Register + 0xD04 + 32 + 0x00000000 + + + VECTACTIVE + Debug: Exception number of currently executing exception, or 0 if thread mode + 0 + 9 + + + VECTPENDING + Exception number of the highest priority pending enabled exception + 12 + 9 + + + ISRPENDING + Debug: NVIC interrupt pending + 22 + 1 + + + ISRPREEMPT + Debug: Pending exception serviced on exit from debug halt + 23 + 1 + + + PENDSTCLR + SysTick exception clear-pending bit + 25 + 1 + + PENDSTCLRSelect + + VALUE_0 + No effect + 0 + + + VALUE_1 + Removes the pending state from the SysTick exception + 1 + + + + + PENDSTSET + SysTick exception set-pending bit + 26 + 1 + + PENDSTSETSelect + + VALUE_0 + Write: no effect; read: SysTick exception is not pending + 0 + + + VALUE_1 + Write: changes SysTick exception state to pending; read: SysTick exception is pending + 1 + + + + + PENDSVCLR + PendSV clear-pending bit + 27 + 1 + + PENDSVCLRSelect + + VALUE_0 + No effect + 0 + + + VALUE_1 + Removes the pending state from the PendSV exception + 1 + + + + + PENDSVSET + PendSV set-pending bit + 28 + 1 + + PENDSVSETSelect + + VALUE_0 + Write: no effect; read: PendSV exception is not pending + 0 + + + VALUE_1 + Write: changes PendSV exception state to pending; read: PendSV exception is pending + 1 + + + + + NMIPENDSET + NMI set-pending bit + 31 + 1 + + NMIPENDSETSelect + + VALUE_0 + Write: no effect; read: NMI exception is not pending + 0 + + + VALUE_1 + Write: changes NMI exception state to pending; read: NMI exception is pending + 1 + + + + + + + VTOR + Vector Table Offset Register + 0xD08 + 32 + 0x00000000 + + + TBLOFF + Vector table base offset + 7 + 25 + + + + + AIRCR + Application Interrupt and Reset Control Register + 0xD0C + 32 + 0x00000000 + + + VECTCLRACTIVE + Debug: Clear state information + 1 + 1 + + + SYSRESETREQ + System Reset Request + 2 + 1 + + SYSRESETREQSelect + + VALUE_0 + No system reset request + 0 + + + VALUE_1 + Asserts a signal to the outer system that requests a reset + 1 + + + + + ENDIANNESS + Data Endianness, 0=little, 1=big + 15 + 1 + + ENDIANNESSSelect + + VALUE_0 + Little-endian + 0 + + + VALUE_1 + Big-endian + 1 + + + + + VECTKEY + Register key (0x05FA) + 16 + 16 + + + + + SCR + System Control Register + 0xD10 + 32 + 0x00000000 + + + SLEEPONEXIT + Sleep-On-Exit when exiting Handler mode + 1 + 1 + + SLEEPONEXITSelect + + VALUE_0 + O not sleep when returning to Thread mode + 0 + + + VALUE_1 + Enter sleep, or deep sleep, on return from an ISR + 1 + + + + + SLEEPDEEP + Uses Deep Sleep as low power mode + 2 + 1 + + SLEEPDEEPSelect + + VALUE_0 + Sleep + 0 + + + VALUE_1 + Deep sleep + 1 + + + + + SEVONPEND + Send Event on Pending bit + 4 + 1 + + SEVONPENDSelect + + VALUE_0 + Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded + 0 + + + VALUE_1 + Enabled events and all interrupts, including disabled interrupts, can wakeup the processor + 1 + + + + + + + CCR + Configuration and Control Register + 0xD14 + 32 + read-only + 0x00000204 + + + UNALIGN_TRP + Unaligned accesses generates a Hard Fault + 3 + 1 + + UNALIGN_TRPSelect + + VALUE_0 + Do not trap unaligned halfword and word accesses + 0 + + + VALUE_1 + Trap unaligned halfword and word accesses + 1 + + + + + STKALIGN + Stack 8-byte aligned on exception entry + 9 + 1 + + STKALIGNSelect + + VALUE_0 + 4-byte aligned + 0 + + + VALUE_1 + 8-byte aligned + 1 + + + + + + + SHPR2 + System Handler Priority Register 2 + 0xD1C + 32 + 0x00000000 + + + PRI_11 + Priority of system handler 11, SVCall + 24 + 8 + + + + + SHPR3 + System Handler Priority Register 3 + 0xD20 + 32 + 0x00000000 + + + PRI_14 + Priority of system handler 14, PendSV + 16 + 8 + + + PRI_15 + Priority of system handler 15, SysTick exception + 24 + 8 + + + + + SHCSR + System Handler Control and State Register + 0xD24 + 32 + 0x00000000 + + + SVCALLPENDED + 15 + 1 + + + + + DFSR + Debug Fault Status Register + 0xD30 + 32 + 0x00000000 + + + HALTED + Halt request debug event active + 0 + 1 + + + BKPT + Breakpoint debug event + 1 + 1 + + + DWTTRAP + DWT debug event + 2 + 1 + + + VCATCH + Vector catch debug event + 3 + 1 + + + EXTERNAL + EDBGRQ debug event + 4 + 1 + + + + + + + diff --git a/svd/ATSAMC20G18A.svd b/svd/ATSAMC20G18A.svd new file mode 100644 index 000000000000..30b1e20145c1 --- /dev/null +++ b/svd/ATSAMC20G18A.svd @@ -0,0 +1,21842 @@ + + + + Microchip Technology + MCHP + ATSAMC20G18A + SAMC20 + 0 + Microchip ATSAMC20G18A Microcontroller + + CM0+ + r0p0 + selectable + true + false + 2 + false + + 8 + 32 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + AC + U22451.1.1 + Analog Comparators + AC + AC_ + 0x42005000 + + 0 + 0x24 + registers + + + AC + 27 + + + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + + + CTRLB + Control B + 0x1 + 8 + write-only + 0x00 + + + START0 + Comparator 0 Start Comparison + 0 + 1 + + + START1 + Comparator 1 Start Comparison + 1 + 1 + + + + + EVCTRL + Event Control + 0x2 + 16 + 0x0000 + + + COMPEO0 + Comparator 0 Event Output Enable + 0 + 1 + + + COMPEO1 + Comparator 1 Event Output Enable + 1 + 1 + + + WINEO0 + Window 0 Event Output Enable + 4 + 1 + + + COMPEI0 + Comparator 0 Event Input Enable + 8 + 1 + + + COMPEI1 + Comparator 1 Event Input Enable + 9 + 1 + + + INVEI0 + Comparator 0 Input Event Invert Enable + 12 + 1 + + + INVEI1 + Comparator 1 Input Event Invert Enable + 13 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x4 + 8 + 0x00 + + + COMP0 + Comparator 0 Interrupt Enable + 0 + 1 + + + COMP1 + Comparator 1 Interrupt Enable + 1 + 1 + + + WIN0 + Window 0 Interrupt Enable + 4 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x5 + 8 + 0x00 + + + COMP0 + Comparator 0 Interrupt Enable + 0 + 1 + + + COMP1 + Comparator 1 Interrupt Enable + 1 + 1 + + + WIN0 + Window 0 Interrupt Enable + 4 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x6 + 8 + 0x00 + + + COMP0 + Comparator 0 + 0 + 1 + + + COMP1 + Comparator 1 + 1 + 1 + + + WIN0 + Window 0 + 4 + 1 + + + + + STATUSA + Status A + 0x7 + 8 + read-only + 0x00 + + + STATE0 + Comparator 0 Current State + 0 + 1 + + + STATE1 + Comparator 1 Current State + 1 + 1 + + + WSTATE0 + Window 0 Current State + 4 + 2 + + WSTATE0Select + + ABOVE + Signal is above window + 0 + + + INSIDE + Signal is inside window + 1 + + + BELOW + Signal is below window + 2 + + + + + + + STATUSB + Status B + 0x8 + 8 + read-only + 0x00 + + + READY0 + Comparator 0 Ready + 0 + 1 + + + READY1 + Comparator 1 Ready + 1 + 1 + + + + + DBGCTRL + Debug Control + 0x9 + 8 + 0x00 + + + DBGRUN + Debug Run + 0 + 1 + + + + + WINCTRL + Window Control + 0xA + 8 + 0x00 + + + WEN0 + Window 0 Mode Enable + 0 + 1 + + + WINTSEL0 + Window 0 Interrupt Selection + 1 + 2 + + WINTSEL0Select + + ABOVE + Interrupt on signal above window + 0 + + + INSIDE + Interrupt on signal inside window + 1 + + + BELOW + Interrupt on signal below window + 2 + + + OUTSIDE + Interrupt on signal outside window + 3 + + + + + + + 4 + 1 + SCALER[%s] + Scaler n + 0xC + 8 + 0x00 + + + VALUE + Scaler Value + 0 + 6 + + + + + 4 + 4 + COMPCTRL[%s] + Comparator Control n + 0x10 + 32 + 0x00000000 + + + ENABLE + Enable + 1 + 1 + + + SINGLE + Single-Shot Mode + 2 + 1 + + + INTSEL + Interrupt Selection + 3 + 2 + + INTSELSelect + + TOGGLE + Interrupt on comparator output toggle + 0 + + + RISING + Interrupt on comparator output rising + 1 + + + FALLING + Interrupt on comparator output falling + 2 + + + EOC + Interrupt on end of comparison (single-shot mode only) + 3 + + + + + RUNSTDBY + Run in Standby + 6 + 1 + + + MUXNEG + Negative Input Mux Selection + 8 + 3 + + MUXNEGSelect + + PIN0 + I/O pin 0 + 0 + + + PIN1 + I/O pin 1 + 1 + + + PIN2 + I/O pin 2 + 2 + + + PIN3 + I/O pin 3 + 3 + + + GND + Ground + 4 + + + VSCALE + VDD scaler + 5 + + + BANDGAP + Internal bandgap voltage + 6 + + + + + MUXPOS + Positive Input Mux Selection + 12 + 3 + + MUXPOSSelect + + PIN0 + I/O pin 0 + 0 + + + PIN1 + I/O pin 1 + 1 + + + PIN2 + I/O pin 2 + 2 + + + PIN3 + I/O pin 3 + 3 + + + VSCALE + VDD Scaler + 4 + + + + + SWAP + Swap Inputs and Invert + 15 + 1 + + + SPEED + Speed Selection + 16 + 2 + + SPEEDSelect + + LOW + Low speed + 0 + + + HIGH + High speed + 3 + + + + + HYSTEN + Hysteresis Enable + 19 + 1 + + + FLEN + Filter Length + 24 + 3 + + FLENSelect + + OFF + No filtering + 0 + + + MAJ3 + 3-bit majority function (2 of 3) + 1 + + + MAJ5 + 5-bit majority function (3 of 5) + 2 + + + + + OUT + Output + 28 + 2 + + OUTSelect + + OFF + The output of COMPn is not routed to the COMPn I/O port + 0 + + + ASYNC + The asynchronous output of COMPn is routed to the COMPn I/O port + 1 + + + SYNC + The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port + 2 + + + + + + + SYNCBUSY + Synchronization Busy + 0x20 + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + Enable Synchronization Busy + 1 + 1 + + + WINCTRL + WINCTRL Synchronization Busy + 2 + 1 + + + COMPCTRL0 + COMPCTRL 0 Synchronization Busy + 3 + 1 + + + COMPCTRL1 + COMPCTRL 1 Synchronization Busy + 4 + 1 + + + + + + + ADC0 + U22472.2.0 + Analog Digital Converter + ADC + ADC_ + 0x42004400 + + 0 + 0x2E + registers + + + ADC0 + 25 + + + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + SLAVEEN + Slave Enable + 5 + 1 + + + RUNSTDBY + Run During Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + + + CTRLB + Control B + 0x1 + 8 + 0x00 + + + PRESCALER + Prescaler Configuration + 0 + 3 + + PRESCALERSelect + + DIV2 + Peripheral clock / 2 + 0x0 + + + DIV4 + Peripheral clock / 4 + 0x1 + + + DIV8 + Peripheral clock / 8 + 0x2 + + + DIV16 + Peripheral clock / 16 + 0x3 + + + DIV32 + Peripheral clock / 32 + 0x4 + + + DIV64 + Peripheral clock / 64 + 0x5 + + + DIV128 + Peripheral clock / 128 + 0x6 + + + DIV256 + Peripheral clock / 256 + 0x7 + + + + + + + REFCTRL + Reference Control + 0x2 + 8 + 0x00 + + + REFSEL + Reference Selection + 0 + 4 + + REFSELSelect + + INTREF + Internal Bandgap Reference + 0x0 + + + INTVCC0 + 1/1.6 VDDANA + 0x1 + + + INTVCC1 + 1/2 VDDANA + 0x2 + + + AREFA + External Reference + 0x3 + + + INTVCC2 + VDDANA + 0x5 + + + + + REFCOMP + Reference Buffer Offset Compensation Enable + 7 + 1 + + + + + EVCTRL + Event Control + 0x3 + 8 + 0x00 + + + FLUSHEI + Flush Event Input Enable + 0 + 1 + + + STARTEI + Start Conversion Event Input Enable + 1 + 1 + + + FLUSHINV + Flush Event Invert Enable + 2 + 1 + + + STARTINV + Start Event Invert Enable + 3 + 1 + + + RESRDYEO + Result Ready Event Out + 4 + 1 + + + WINMONEO + Window Monitor Event Out + 5 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x4 + 8 + 0x00 + + + RESRDY + Result Ready Interrupt Disable + 0 + 1 + + + OVERRUN + Overrun Interrupt Disable + 1 + 1 + + + WINMON + Window Monitor Interrupt Disable + 2 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x5 + 8 + 0x00 + + + RESRDY + Result Ready Interrupt Enable + 0 + 1 + + + OVERRUN + Overrun Interrupt Enable + 1 + 1 + + + WINMON + Window Monitor Interrupt Enable + 2 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x6 + 8 + 0x00 + + + RESRDY + Result Ready Interrupt Flag + 0 + 1 + + + OVERRUN + Overrun Interrupt Flag + 1 + 1 + + + WINMON + Window Monitor Interrupt Flag + 2 + 1 + + + + + SEQSTATUS + Sequence Status + 0x7 + 8 + read-only + 0x00 + + + SEQSTATE + Sequence State + 0 + 5 + + + SEQBUSY + Sequence Busy + 7 + 1 + + + + + INPUTCTRL + Input Control + 0x8 + 16 + 0x0000 + + + MUXPOS + Positive Mux Input Selection + 0 + 5 + + MUXPOSSelect + + AIN0 + ADC AIN0 Pin + 0x0 + + + AIN1 + ADC AIN1 Pin + 0x1 + + + AIN2 + ADC AIN2 Pin + 0x2 + + + AIN3 + ADC AIN3 Pin + 0x3 + + + AIN4 + ADC AIN4 Pin + 0x4 + + + AIN5 + ADC AIN5 Pin + 0x5 + + + AIN6 + ADC AIN6 Pin + 0x6 + + + AIN7 + ADC AIN7 Pin + 0x7 + + + AIN8 + ADC AIN8 Pin + 0x8 + + + AIN9 + ADC AIN9 Pin + 0x9 + + + AIN10 + ADC AIN10 Pin + 0xA + + + AIN11 + ADC AIN11 Pin + 0xB + + + BANDGAP + Bandgap Voltage + 0x19 + + + SCALEDCOREVCC + 1/4 Scaled Core Supply + 0x1A + + + SCALEDIOVCC + 1/4 Scaled I/O Supply + 0x1B + + + + + MUXNEG + Negative Mux Input Selection + 8 + 5 + + MUXNEGSelect + + AIN0 + ADC AIN0 Pin + 0x0 + + + AIN1 + ADC AIN1 Pin + 0x1 + + + AIN2 + ADC AIN2 Pin + 0x2 + + + AIN3 + ADC AIN3 Pin + 0x3 + + + AIN4 + ADC AIN4 Pin + 0x4 + + + AIN5 + ADC AIN5 Pin + 0x5 + + + GND + Internal Ground + 0x18 + + + + + + + CTRLC + Control C + 0xA + 16 + 0x0000 + + + DIFFMODE + Differential Mode + 0 + 1 + + + LEFTADJ + Left-Adjusted Result + 1 + 1 + + + FREERUN + Free Running Mode + 2 + 1 + + + CORREN + Digital Correction Logic Enable + 3 + 1 + + + RESSEL + Conversion Result Resolution + 4 + 2 + + RESSELSelect + + 12BIT + 12-bit + 0x0 + + + 16BIT + 16-bit averaging mode + 0x1 + + + 10BIT + 10-bit + 0x2 + + + 8BIT + 8-bit + 0x3 + + + + + R2R + Rail-to-Rail mode enable + 7 + 1 + + + WINMODE + Window Monitor Mode + 8 + 3 + + WINMODESelect + + DISABLE + No window mode (default) + 0 + + + MODE1 + RESULT > WINLT + 1 + + + MODE2 + RESULT < WINUT + 2 + + + MODE3 + WINLT < RESULT < WINUT + 3 + + + MODE4 + !(WINLT < RESULT < WINUT) + 4 + + + + + + + AVGCTRL + Average Control + 0xC + 8 + 0x00 + + + SAMPLENUM + Number of Samples to be Collected + 0 + 4 + + SAMPLENUMSelect + + 1 + 1 sample + 0x0 + + + 2 + 2 samples + 0x1 + + + 4 + 4 samples + 0x2 + + + 8 + 8 samples + 0x3 + + + 16 + 16 samples + 0x4 + + + 32 + 32 samples + 0x5 + + + 64 + 64 samples + 0x6 + + + 128 + 128 samples + 0x7 + + + 256 + 256 samples + 0x8 + + + 512 + 512 samples + 0x9 + + + 1024 + 1024 samples + 0xA + + + + + ADJRES + Adjusting Result / Division Coefficient + 4 + 3 + + + + + SAMPCTRL + Sample Time Control + 0xD + 8 + 0x00 + + + SAMPLEN + Sampling Time Length + 0 + 6 + + + OFFCOMP + Comparator Offset Compensation Enable + 7 + 1 + + + + + WINLT + Window Monitor Lower Threshold + 0xE + 16 + 0x0000 + + + WINLT + Window Lower Threshold + 0 + 16 + + + + + WINUT + Window Monitor Upper Threshold + 0x10 + 16 + 0x0000 + + + WINUT + Window Upper Threshold + 0 + 16 + + + + + GAINCORR + Gain Correction + 0x12 + 16 + 0x0000 + + + GAINCORR + Gain Correction Value + 0 + 12 + + + + + OFFSETCORR + Offset Correction + 0x14 + 16 + 0x0000 + + + OFFSETCORR + Offset Correction Value + 0 + 12 + + + + + SWTRIG + Software Trigger + 0x18 + 8 + 0x00 + + + FLUSH + ADC Flush + 0 + 1 + + + START + Start ADC Conversion + 1 + 1 + + + + + DBGCTRL + Debug Control + 0x1C + 8 + 0x00 + + + DBGRUN + Debug Run + 0 + 1 + + + + + SYNCBUSY + Synchronization Busy + 0x20 + 16 + read-only + 0x0000 + + + SWRST + SWRST Synchronization Busy + 0 + 1 + + + ENABLE + ENABLE Synchronization Busy + 1 + 1 + + + INPUTCTRL + INPUTCTRL Synchronization Busy + 2 + 1 + + + CTRLC + CTRLC Synchronization Busy + 3 + 1 + + + AVGCTRL + AVGCTRL Synchronization Busy + 4 + 1 + + + SAMPCTRL + SAMPCTRL Synchronization Busy + 5 + 1 + + + WINLT + WINLT Synchronization Busy + 6 + 1 + + + WINUT + WINUT Synchronization Busy + 7 + 1 + + + GAINCORR + GAINCORR Synchronization Busy + 8 + 1 + + + OFFSETCORR + OFFSETCTRL Synchronization Busy + 9 + 1 + + + SWTRIG + SWTRG Synchronization Busy + 10 + 1 + + + + + RESULT + Result + 0x24 + 16 + read-only + 0x0000 + + + RESULT + Result Value + 0 + 16 + + + + + SEQCTRL + Sequence Control + 0x28 + 32 + 0x00000000 + + + SEQEN + Enable Positive Input in the Sequence + 0 + 32 + + + + + CALIB + Calibration + 0x2C + 16 + 0x0000 + + + BIASCOMP + Bias Comparator Scaling + 0 + 3 + + + BIASREFBUF + Bias Reference Buffer Scaling + 8 + 3 + + + + + + + CCL + U22251.0.1 + Configurable Custom Logic + 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Enable + 0 + 1 + + + OVR1 + Channel 1 Overrun Interrupt Enable + 1 + 1 + + + OVR2 + Channel 2 Overrun Interrupt Enable + 2 + 1 + + + OVR3 + Channel 3 Overrun Interrupt Enable + 3 + 1 + + + OVR4 + Channel 4 Overrun Interrupt Enable + 4 + 1 + + + OVR5 + Channel 5 Overrun Interrupt Enable + 5 + 1 + + + EVD0 + Channel 0 Event Detection Interrupt Enable + 16 + 1 + + + EVD1 + Channel 1 Event Detection Interrupt Enable + 17 + 1 + + + EVD2 + Channel 2 Event Detection Interrupt Enable + 18 + 1 + + + EVD3 + Channel 3 Event Detection Interrupt Enable + 19 + 1 + + + EVD4 + Channel 4 Event Detection Interrupt Enable + 20 + 1 + + + EVD5 + Channel 5 Event Detection Interrupt Enable + 21 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x14 + 32 + 0x00000000 + + + OVR0 + Channel 0 Overrun Interrupt Enable + 0 + 1 + + + OVR1 + Channel 1 Overrun Interrupt Enable + 1 + 1 + + + OVR2 + Channel 2 Overrun Interrupt Enable + 2 + 1 + + + OVR3 + Channel 3 Overrun Interrupt Enable + 3 + 1 + + + OVR4 + Channel 4 Overrun Interrupt Enable + 4 + 1 + + + OVR5 + Channel 5 Overrun Interrupt Enable + 5 + 1 + + + EVD0 + Channel 0 Event Detection Interrupt Enable + 16 + 1 + + + EVD1 + Channel 1 Event Detection Interrupt Enable + 17 + 1 + + + EVD2 + Channel 2 Event Detection Interrupt Enable + 18 + 1 + + + EVD3 + Channel 3 Event Detection Interrupt Enable + 19 + 1 + + + EVD4 + Channel 4 Event Detection Interrupt Enable + 20 + 1 + + + EVD5 + Channel 5 Event Detection Interrupt Enable + 21 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x18 + 32 + 0x00000000 + + + OVR0 + Channel 0 Overrun + 0 + 1 + + + OVR1 + Channel 1 Overrun + 1 + 1 + + + OVR2 + Channel 2 Overrun + 2 + 1 + + + OVR3 + Channel 3 Overrun + 3 + 1 + + + OVR4 + Channel 4 Overrun + 4 + 1 + + + OVR5 + Channel 5 Overrun + 5 + 1 + + + EVD0 + Channel 0 Event Detection + 16 + 1 + + + EVD1 + Channel 1 Event Detection + 17 + 1 + + + EVD2 + Channel 2 Event Detection + 18 + 1 + + + EVD3 + Channel 3 Event Detection + 19 + 1 + + + EVD4 + Channel 4 Event Detection + 20 + 1 + + + EVD5 + Channel 5 Event Detection + 21 + 1 + + + + + SWEVT + Software Event + 0x1C + 32 + write-only + 0x00000000 + + + CHANNEL0 + Channel 0 Software Selection + 0 + 1 + + + CHANNEL1 + Channel 1 Software Selection + 1 + 1 + + + CHANNEL2 + Channel 2 Software Selection + 2 + 1 + + + CHANNEL3 + Channel 3 Software Selection + 3 + 1 + + + CHANNEL4 + Channel 4 Software Selection + 4 + 1 + + + CHANNEL5 + Channel 5 Software Selection + 5 + 1 + + + + + 6 + 4 + CHANNEL[%s] + Channel n + 0x20 + 32 + 0x00008000 + + + EVGEN + Event Generator Selection + 0 + 7 + + + PATH + Path Selection + 8 + 2 + + PATHSelect + + SYNCHRONOUS + Synchronous path + 0 + + + RESYNCHRONIZED + Resynchronized path + 1 + + + ASYNCHRONOUS + Asynchronous path + 2 + + + + + EDGSEL + Edge Detection Selection + 10 + 2 + + EDGSELSelect + + NO_EVT_OUTPUT + No event output when using the resynchronized or synchronous path + 0 + + + RISING_EDGE + Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path + 1 + + + FALLING_EDGE + Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path + 2 + + + BOTH_EDGES + Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path + 3 + + + + + RUNSTDBY + Run in standby + 14 + 1 + + + ONDEMAND + Generic Clock On Demand + 15 + 1 + + + + + 47 + 4 + USER[%s] + User Multiplexer n + 0x80 + 32 + 0x00000000 + + + CHANNEL + Channel Event Selection + 0 + 4 + + + + + + + FREQM + U22571.0.1 + Frequency Meter + FREQM + FREQM_ + 0x40002C00 + + 0 + 0x14 + registers + + + FREQM + 4 + + + + CTRLA + Control A Register + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + + + CTRLB + Control B Register + 0x1 + 8 + write-only + 0x00 + + + START + Start Measurement + 0 + 1 + + + + + CFGA + Config A register + 0x2 + 16 + 0x0000 + + + REFNUM + Number of Reference Clock Cycles + 0 + 8 + + + + + INTENCLR + Interrupt Enable Clear Register + 0x8 + 8 + 0x00 + + + DONE + Measurement Done Interrupt Enable + 0 + 1 + + + + + INTENSET + Interrupt Enable Set Register + 0x9 + 8 + 0x00 + + + DONE + Measurement Done Interrupt Enable + 0 + 1 + + + + + INTFLAG + Interrupt Flag Register + 0xA + 8 + 0x00 + + + DONE + Measurement Done + 0 + 1 + + + + + STATUS + Status Register + 0xB + 8 + 0x00 + + + BUSY + FREQM Status + 0 + 1 + + + OVF + Sticky Count Value Overflow + 1 + 1 + + + + + SYNCBUSY + Synchronization Busy Register + 0xC + 32 + read-only + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + + + VALUE + Count Value Register + 0x10 + 32 + read-only + 0x00000000 + + + VALUE + Measurement Value + 0 + 24 + + + + + + + GCLK + U21221.1.1 + Generic Clock Generator + GCLK + GCLK_ + 0x40001C00 + + 0 + 0x184 + registers + + + + CTRLA + Control + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + + + SYNCBUSY + Synchronization Busy + 0x4 + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchroniation Busy bit + 0 + 1 + + + GENCTRL0 + Generic Clock Generator Control 0 Synchronization Busy bits + 2 + 1 + + GENCTRL0Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + + + GENCTRL1 + Generic Clock Generator Control 1 Synchronization Busy bits + 3 + 1 + + GENCTRL1Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + + + GENCTRL2 + Generic Clock Generator Control 2 Synchronization Busy bits + 4 + 1 + + GENCTRL2Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + + + GENCTRL3 + Generic Clock Generator Control 3 Synchronization Busy bits + 5 + 1 + + GENCTRL3Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + + + GENCTRL4 + Generic Clock Generator Control 4 Synchronization Busy bits + 6 + 1 + + GENCTRL4Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + + + GENCTRL5 + Generic Clock Generator Control 5 Synchronization Busy bits + 7 + 1 + + GENCTRL5Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + + + GENCTRL6 + Generic Clock Generator Control 6 Synchronization Busy bits + 8 + 1 + + GENCTRL6Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + + + GENCTRL7 + Generic Clock Generator Control 7 Synchronization Busy bits + 9 + 1 + + GENCTRL7Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + + + GENCTRL8 + Generic Clock Generator Control 8 Synchronization Busy bits + 10 + 1 + + GENCTRL8Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + + + + + 9 + 4 + GENCTRL[%s] + Generic Clock Generator Control + 0x20 + 32 + 0x00000000 + + + SRC + Source Select + 0 + 3 + + SRCSelect + + XOSC + XOSC oscillator output + 0 + + + GCLKIN + Generator input pad + 1 + + + GCLKGEN1 + Generic clock generator 1 output + 2 + + + OSCULP32K + OSCULP32K oscillator output + 3 + + + OSC32K + OSC32K oscillator output + 4 + + + XOSC32K + XOSC32K oscillator output + 5 + + + OSC48M + OSC48M oscillator output + 6 + + + DPLL96M + DPLL96M output + 7 + + + + + GENEN + Generic Clock Generator Enable + 8 + 1 + + + IDC + Improve Duty Cycle + 9 + 1 + + + OOV + Output Off Value + 10 + 1 + + + OE + Output Enable + 11 + 1 + + + DIVSEL + Divide Selection + 12 + 1 + + DIVSELSelect + + DIV1 + Divide input directly by divider factor + 0x0 + + + DIV2 + Divide input by 2^(divider factor+ 1) + 0x1 + + + + + RUNSTDBY + Run in Standby + 13 + 1 + + + DIV + Division Factor + 16 + 16 + + + + + 41 + 4 + PCHCTRL[%s] + Peripheral Clock Control + 0x80 + 32 + 0x00000000 + + + GEN + Generic Clock Generator + 0 + 4 + + GENSelect + + GCLK0 + Generic clock generator 0 + 0x0 + + + GCLK1 + Generic clock generator 1 + 0x1 + + + GCLK2 + Generic clock generator 2 + 0x2 + + + GCLK3 + Generic clock generator 3 + 0x3 + + + GCLK4 + Generic clock generator 4 + 0x4 + + + GCLK5 + Generic clock generator 5 + 0x5 + + + GCLK6 + Generic clock generator 6 + 0x6 + + + GCLK7 + Generic clock generator 7 + 0x7 + + + GCLK8 + Generic clock generator 8 + 0x8 + + + + + CHEN + Channel Enable + 6 + 1 + + + WRTLOCK + Write Lock + 7 + 1 + + + + + + + HMATRIXHS + I76382.1.3 + HSB Matrix + HMATRIXB + HMATRIXB_ + 0x4100A000 + + 0 + 0x168 + registers + + + + 16 + 4 + MCFG[%s] + Master Configuration + 0x0 + 32 + 0x00000002 + + + ULBT + Undefined Length Burst Type + 0 + 3 + + ULBTSelect + + INFINITE + Infinite Length + 0 + + + SINGLE + Single Access + 1 + + + FOUR_BEAT + Four Beat Burst + 2 + + + EIGHT_BEAT + Eight Beat Burst + 3 + + + SIXTEEN_BEAT + Sixteen Beat Burst + 4 + + + + + + + 16 + 4 + SCFG[%s] + Slave Configuration + 0x40 + 32 + 0x00000010 + + + SLOT_CYCLE + Maximum Number of Allowed Cycles for a Burst + 0 + 8 + + + DEFMSTR_TYPE + Default Master Type + 16 + 2 + + DEFMSTR_TYPESelect + + NO_DEFAULT + No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. + 0 + + + LAST_DEFAULT + Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. + 1 + + + FIXED_DEFAULT + Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave. + 2 + + + + + FIXED_DEFMSTR + Fixed Index of Default Master + 18 + 4 + + + ARBT + Arbitration Type + 24 + 1 + + ARBTSelect + + ROUND_ROBIN + Round-Robin Arbitration + 0 + + + FIXED_PRIORITY + Fixed Priority Arbitration + 1 + + + + + + + 4 + 0x8 + PRS[%s] + + 0x080 + + PRAS + Priority A for Slave + 0x0 + 32 + 0x00000000 + + + M0PR + Master 0 Priority + 0 + 4 + + + M1PR + Master 1 Priority + 4 + 4 + + + M2PR + Master 2 Priority + 8 + 4 + + + M3PR + Master 3 Priority + 12 + 4 + + + M4PR + Master 4 Priority + 16 + 4 + + + M5PR + Master 5 Priority + 20 + 4 + + + M6PR + Master 6 Priority + 24 + 4 + + + M7PR + Master 7 Priority + 28 + 4 + + + + + PRBS + Priority B for Slave + 0x4 + 32 + 0x00000000 + + + M8PR + Master 8 Priority + 0 + 4 + + + M9PR + Master 9 Priority + 4 + 4 + + + M10PR + Master 10 Priority + 8 + 4 + + + M11PR + Master 11 Priority + 12 + 4 + + + M12PR + Master 12 Priority + 16 + 4 + + + M13PR + Master 13 Priority + 20 + 4 + + + M14PR + Master 14 Priority + 24 + 4 + + + M15PR + Master 15 Priority + 28 + 4 + + + + + + MRCR + Master Remap Control + 0x100 + 32 + 0x00000000 + + + RCB0 + Remap Command Bit for Master 0 + 0 + 1 + + RCB0Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB1 + Remap Command Bit for Master 1 + 1 + 1 + + RCB1Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB2 + Remap Command Bit for Master 2 + 2 + 1 + + RCB2Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB3 + Remap Command Bit for Master 3 + 3 + 1 + + RCB3Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB4 + Remap Command Bit for Master 4 + 4 + 1 + + RCB4Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB5 + Remap Command Bit for Master 5 + 5 + 1 + + RCB5Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB6 + Remap Command Bit for Master 6 + 6 + 1 + + RCB6Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB7 + Remap Command Bit for Master 7 + 7 + 1 + + RCB7Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB8 + Remap Command Bit for Master 8 + 8 + 1 + + RCB8Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB9 + Remap Command Bit for Master 9 + 9 + 1 + + RCB9Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB10 + Remap Command Bit for Master 10 + 10 + 1 + + RCB10Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB11 + Remap Command Bit for Master 11 + 11 + 1 + + RCB11Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB12 + Remap Command Bit for Master 12 + 12 + 1 + + RCB12Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB13 + Remap Command Bit for Master 13 + 13 + 1 + + RCB13Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB14 + Remap Command Bit for Master 14 + 14 + 1 + + RCB14Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB15 + Remap Command Bit for Master 15 + 15 + 1 + + RCB15Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + + + 16 + 4 + SFR[%s] + Special Function + 0x110 + 32 + 0x00000000 + + + SFR + Special Function Register + 0 + 32 + + + + + + + MCLK + U22342.0.0 + Main Clock + MCLK + MCLK_ + 0x40000800 + + 0 + 0x20 + registers + + + + INTENCLR + Interrupt Enable Clear + 0x1 + 8 + 0x00 + + + CKRDY + Clock Ready Interrupt Enable + 0 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x2 + 8 + 0x00 + + + CKRDY + Clock Ready Interrupt Enable + 0 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x3 + 8 + 0x01 + + + CKRDY + Clock Ready + 0 + 1 + + + + + CPUDIV + CPU Clock Division + 0x4 + 8 + 0x01 + + + CPUDIV + CPU Clock Division Factor + 0 + 8 + + CPUDIVSelect + + DIV1 + Divide by 1 + 0x01 + + + DIV2 + Divide by 2 + 0x02 + + + DIV4 + Divide by 4 + 0x04 + + + DIV8 + Divide by 8 + 0x08 + + + DIV16 + Divide by 16 + 0x10 + + + DIV32 + Divide by 32 + 0x20 + + + DIV64 + Divide by 64 + 0x40 + + + DIV128 + Divide by 128 + 0x80 + + + + + + + AHBMASK + AHB Mask + 0x10 + 32 + 0x00001CFF + + + HPB0_ + HPB0 AHB Clock Mask + 0 + 1 + + + HPB1_ + HPB1 AHB Clock Mask + 1 + 1 + + + HPB2_ + HPB2 AHB Clock Mask + 2 + 1 + + + DSU_ + DSU AHB Clock Mask + 3 + 1 + + + HMATRIXHS_ + HMATRIXHS AHB Clock Mask + 4 + 1 + + + NVMCTRL_ + NVMCTRL AHB Clock Mask + 5 + 1 + + + HSRAM_ + HSRAM AHB Clock Mask + 6 + 1 + + + DMAC_ + DMAC AHB Clock Mask + 7 + 1 + + + PAC_ + PAC AHB Clock Mask + 10 + 1 + + + NVMCTRL_PICACHU_ + NVMCTRL_PICACHU AHB Clock Mask + 11 + 1 + + + DIVAS_ + DIVAS AHB Clock Mask + 12 + 1 + + + + + APBAMASK + APBA Mask + 0x14 + 32 + 0x00000FFF + + + PAC_ + PAC APB Clock Enable + 0 + 1 + + + PM_ + PM APB Clock Enable + 1 + 1 + + + MCLK_ + MCLK APB Clock Enable + 2 + 1 + + + RSTC_ + RSTC APB Clock Enable + 3 + 1 + + + OSCCTRL_ + OSCCTRL APB Clock Enable + 4 + 1 + + + OSC32KCTRL_ + OSC32KCTRL APB Clock Enable + 5 + 1 + + + SUPC_ + SUPC APB Clock Enable + 6 + 1 + + + GCLK_ + GCLK APB Clock Enable + 7 + 1 + + + WDT_ + WDT APB Clock Enable + 8 + 1 + + + RTC_ + RTC APB Clock Enable + 9 + 1 + + + EIC_ + EIC APB Clock Enable + 10 + 1 + + + FREQM_ + FREQM APB Clock Enable + 11 + 1 + + + + + APBBMASK + APBB Mask + 0x18 + 32 + 0x00000007 + + + PORT_ + PORT APB Clock Enable + 0 + 1 + + + DSU_ + DSU APB Clock Enable + 1 + 1 + + + NVMCTRL_ + NVMCTRL APB Clock Enable + 2 + 1 + + + HMATRIXHS_ + HMATRIXHS APB Clock Enable + 5 + 1 + + + + + APBCMASK + APBC Mask + 0x1C + 32 + 0x00000000 + + + EVSYS_ + EVSYS APB Clock Enable + 0 + 1 + + + SERCOM0_ + SERCOM0 APB Clock Enable + 1 + 1 + + + SERCOM1_ + SERCOM1 APB Clock Enable + 2 + 1 + + + SERCOM2_ + SERCOM2 APB Clock Enable + 3 + 1 + + + SERCOM3_ + SERCOM3 APB Clock Enable + 4 + 1 + + + TCC0_ + TCC0 APB Clock Enable + 9 + 1 + + + TCC1_ + TCC1 APB Clock Enable + 10 + 1 + + + TCC2_ + TCC2 APB Clock Enable + 11 + 1 + + + TC0_ + TC0 APB Clock Enable + 12 + 1 + + + TC1_ + TC1 APB Clock Enable + 13 + 1 + + + TC2_ + TC2 APB Clock Enable + 14 + 1 + + + TC3_ + TC3 APB Clock Enable + 15 + 1 + + + TC4_ + TC4 APB Clock Enable + 16 + 1 + + + ADC0_ + ADC0 APB Clock Enable + 17 + 1 + + + AC_ + AC APB Clock Enable + 20 + 1 + + + PTC_ + PTC APB Clock Enable + 22 + 1 + + + CCL_ + CCL APB Clock Enable + 23 + 1 + + + + + + + MTB + U20021.0.0 + Cortex-M0+ Micro-Trace Buffer + MTB + MTB_ + 0x41008000 + + 0 + 0x1000 + registers + + + + POSITION + MTB Position + 0x0 + 32 + + + WRAP + Pointer Value Wraps + 2 + 1 + + + POINTER + Trace Packet Location Pointer + 3 + 29 + + + + + MASTER + MTB Master + 0x4 + 32 + 0x00000000 + + + MASK + Maximum Value of the Trace Buffer in SRAM + 0 + 5 + + + TSTARTEN + Trace Start Input Enable + 5 + 1 + + + TSTOPEN + Trace Stop Input Enable + 6 + 1 + + + SFRWPRIV + Special Function Register Write Privilege + 7 + 1 + + + RAMPRIV + SRAM Privilege + 8 + 1 + + + HALTREQ + Halt Request + 9 + 1 + + + EN + Main Trace Enable + 31 + 1 + + + + + FLOW + MTB Flow + 0x8 + 32 + 0x00000000 + + + AUTOSTOP + Auto Stop Tracing + 0 + 1 + + + AUTOHALT + Auto Halt Request + 1 + 1 + + + WATERMARK + Watermark value + 3 + 29 + + + + + BASE + MTB Base + 0xC + 32 + read-only + + + ITCTRL + MTB Integration Mode Control + 0xF00 + 32 + + + CLAIMSET + MTB Claim Set + 0xFA0 + 32 + + + CLAIMCLR + MTB Claim Clear + 0xFA4 + 32 + + + LOCKACCESS + MTB Lock Access + 0xFB0 + 32 + + + LOCKSTATUS + MTB Lock Status + 0xFB4 + 32 + read-only + + + AUTHSTATUS + MTB Authentication Status + 0xFB8 + 32 + read-only + + + DEVARCH + MTB Device Architecture + 0xFBC + 32 + read-only + + + DEVID + MTB Device Configuration + 0xFC8 + 32 + read-only + + + DEVTYPE + MTB Device Type + 0xFCC + 32 + read-only + + + PID4 + Peripheral Identification 4 + 0xFD0 + 32 + read-only + + + PID5 + Peripheral Identification 5 + 0xFD4 + 32 + read-only + + + PID6 + Peripheral Identification 6 + 0xFD8 + 32 + read-only + + + PID7 + Peripheral Identification 7 + 0xFDC + 32 + read-only + + + PID0 + Peripheral Identification 0 + 0xFE0 + 32 + read-only + + + PID1 + Peripheral Identification 1 + 0xFE4 + 32 + read-only + + + PID2 + Peripheral Identification 2 + 0xFE8 + 32 + read-only + + + PID3 + Peripheral Identification 3 + 0xFEC + 32 + read-only + + + CID0 + Component Identification 0 + 0xFF0 + 32 + read-only + + + CID1 + Component Identification 1 + 0xFF4 + 32 + read-only + + + CID2 + Component Identification 2 + 0xFF8 + 32 + read-only + + + CID3 + Component Identification 3 + 0xFFC + 32 + read-only + + + + + NVMCTRL + U22074.0.1.1 + Non-Volatile Memory Controller + NVMCTRL + NVMCTRL_ + 0x41004000 + + 0 + 0x30 + registers + + + NVMCTRL + 6 + + + + CTRLA + Control A + 0x0 + 16 + 0x0000 + + + CMD + Command + 0 + 7 + + CMDSelect + + ER + Erase Row - Erases the row addressed by the ADDR register. + 0x02 + + + WP + Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. + 0x04 + + + EAR + Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. + 0x05 + + + WAP + Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. + 0x06 + + + SF + Security Flow Command + 0x0A + + + WL + Write lockbits + 0x0F + + + RWWEEER + RWW EEPROM area Erase Row - Erases the row addressed by the ADDR register. + 0x1A + + + RWWEEWP + RWW EEPROM Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. + 0x1C + + + LR + Lock Region - Locks the region containing the address location in the ADDR register. + 0x40 + + + UR + Unlock Region - Unlocks the region containing the address location in the ADDR register. + 0x41 + + + SPRM + Sets the power reduction mode. + 0x42 + + + CPRM + Clears the power reduction mode. + 0x43 + + + PBC + Page Buffer Clear - Clears the page buffer. + 0x44 + + + SSB + Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row. + 0x45 + + + INVALL + Invalidate all cache lines. + 0x46 + + + + + CMDEX + Command Execution + 8 + 8 + + CMDEXSelect + + KEY + Execution Key + 0xA5 + + + + + + + CTRLB + Control B + 0x4 + 32 + 0x00000080 + + + RWS + NVM Read Wait States + 1 + 4 + + RWSSelect + + SINGLE + Single Auto Wait State + 0 + + + HALF + Half Auto Wait State + 1 + + + DUAL + Dual Auto Wait State + 2 + + + + + MANW + Manual Write + 7 + 1 + + + SLEEPPRM + Power Reduction Mode during Sleep + 8 + 2 + + SLEEPPRMSelect + + WAKEONACCESS + NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access. + 0 + + + WAKEUPINSTANT + NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep. + 1 + + + DISABLED + Auto power reduction disabled. + 3 + + + + + READMODE + NVMCTRL Read Mode + 16 + 2 + + READMODESelect + + NO_MISS_PENALTY + The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance. + 0x0 + + + LOW_POWER + Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time. + 0x1 + + + DETERMINISTIC + The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings. + 0x2 + + + + + CACHEDIS + Cache Disable + 18 + 2 + + + + + PARAM + NVM Parameter + 0x8 + 32 + 0x00000000 + + + NVMP + NVM Pages + 0 + 16 + + + PSZ + Page Size + 16 + 3 + + PSZSelect + + 8 + 8 bytes + 0x0 + + + 16 + 16 bytes + 0x1 + + + 32 + 32 bytes + 0x2 + + + 64 + 64 bytes + 0x3 + + + 128 + 128 bytes + 0x4 + + + 256 + 256 bytes + 0x5 + + + 512 + 512 bytes + 0x6 + + + 1024 + 1024 bytes + 0x7 + + + + + RWWEEP + RWW EEPROM Pages + 20 + 12 + + + + + INTENCLR + Interrupt Enable Clear + 0xC + 8 + 0x00 + + + READY + NVM Ready Interrupt Enable + 0 + 1 + + + ERROR + Error Interrupt Enable + 1 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x10 + 8 + 0x00 + + + READY + NVM Ready Interrupt Enable + 0 + 1 + + + ERROR + Error Interrupt Enable + 1 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x14 + 8 + 0x00 + + + READY + NVM Ready + 0 + 1 + + + ERROR + Error + 1 + 1 + + + + + STATUS + Status + 0x18 + 16 + 0x0000 + + + PRM + Power Reduction Mode + 0 + 1 + + + LOAD + NVM Page Buffer Active Loading + 1 + 1 + + + PROGE + Programming Error Status + 2 + 1 + + + LOCKE + Lock Error Status + 3 + 1 + + + NVME + NVM Error + 4 + 1 + + + SB + Security Bit Status + 8 + 1 + + + + + ADDR + Address + 0x1C + 32 + 0x00000000 + + + ADDR + NVM Address + 0 + 22 + + + + + LOCK + Lock Section + 0x20 + 16 + 0x0000 + + + LOCK + Region Lock Bits + 0 + 16 + + + + + PBLDATA0 + Page Buffer Load Data 0 + 0x28 + 32 + read-only + 0x00000000 + + + PBLDATA1 + Page Buffer Load Data 1 + 0x2C + 32 + read-only + 0x00000000 + + + + + OSCCTRL + U21192.1.0 + Oscillators Control + OSCCTRL + OSCCTRL_ + 0x40001000 + + 0 + 0x3C + registers + + + + INTENCLR + Interrupt Enable Clear + 0x0 + 32 + 0x00000000 + + + XOSCRDY + XOSC Ready Interrupt Enable + 0 + 1 + + + XOSCFAIL + XOSC Clock Failure Detector Interrupt Enable + 1 + 1 + + + OSC48MRDY + OSC48M Ready Interrupt Enable + 4 + 1 + + + DPLLLCKR + DPLL Lock Rise Interrupt Enable + 8 + 1 + + + DPLLLCKF + DPLL Lock Fall Interrupt Enable + 9 + 1 + + + DPLLLTO + DPLL Time Out Interrupt Enable + 10 + 1 + + + DPLLLDRTO + DPLL Ratio Ready Interrupt Enable + 11 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x4 + 32 + 0x00000000 + + + XOSCRDY + XOSC Ready Interrupt Enable + 0 + 1 + + + XOSCFAIL + XOSC Clock Failure Detector Interrupt Enable + 1 + 1 + + + OSC48MRDY + OSC48M Ready Interrupt Enable + 4 + 1 + + + DPLLLCKR + DPLL Lock Rise Interrupt Enable + 8 + 1 + + + DPLLLCKF + DPLL Lock Fall Interrupt Enable + 9 + 1 + + + DPLLLTO + DPLL Time Out Interrupt Enable + 10 + 1 + + + DPLLLDRTO + DPLL Ratio Ready Interrupt Enable + 11 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x8 + 32 + 0x00000000 + + + XOSCRDY + XOSC Ready + 0 + 1 + + + XOSCFAIL + XOSC Clock Failure Detector + 1 + 1 + + + OSC48MRDY + OSC48M Ready + 4 + 1 + + + DPLLLCKR + DPLL Lock Rise + 8 + 1 + + + DPLLLCKF + DPLL Lock Fall + 9 + 1 + + + DPLLLTO + DPLL Timeout + 10 + 1 + + + DPLLLDRTO + DPLL Ratio Ready + 11 + 1 + + + + + STATUS + Power and Clocks Status + 0xC + 32 + read-only + 0x00000000 + + + XOSCRDY + XOSC Ready + 0 + 1 + + + XOSCFAIL + XOSC Clock Failure Detector + 1 + 1 + + + XOSCCKSW + XOSC Clock Switch + 2 + 1 + + + OSC48MRDY + OSC48M Ready + 4 + 1 + + + DPLLLCKR + DPLL Lock Rise + 8 + 1 + + + DPLLLCKF + DPLL Lock Fall + 9 + 1 + + + DPLLTO + DPLL Timeout + 10 + 1 + + + DPLLLDRTO + DPLL Ratio Ready + 11 + 1 + + + + + XOSCCTRL + External Multipurpose Crystal Oscillator (XOSC) Control + 0x10 + 16 + 0x0080 + + + ENABLE + Oscillator Enable + 1 + 1 + + + XTALEN + Crystal Oscillator Enable + 2 + 1 + + + CFDEN + Xosc Clock Failure Detector Enable + 3 + 1 + + + SWBEN + Xosc Clock Switch Enable + 4 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + GAIN + Oscillator Gain + 8 + 3 + + GAINSelect + + GAIN2 + 2 MHz + 0 + + + GAIN4 + 4 MHz + 1 + + + GAIN8 + 8 MHz + 2 + + + GAIN16 + 16 MHz + 3 + + + GAIN30 + 30 MHz + 4 + + + + + AMPGC + Automatic Amplitude Gain Control + 11 + 1 + + + STARTUP + Start-Up Time + 12 + 4 + + STARTUPSelect + + CYCLE1 + 31 us + 0 + + + CYCLE2 + 61 us + 1 + + + CYCLE4 + 122 us + 2 + + + CYCLE8 + 244 us + 3 + + + CYCLE16 + 488 us + 4 + + + CYCLE32 + 977 us + 5 + + + CYCLE64 + 1953 us + 6 + + + CYCLE128 + 3906 us + 7 + + + CYCLE256 + 7813 us + 8 + + + CYCLE512 + 15625 us + 9 + + + CYCLE1024 + 31250 us + 10 + + + CYCLE2048 + 62500 us + 11 + + + CYCLE4096 + 125000 us + 12 + + + CYCLE8192 + 250000 us + 13 + + + CYCLE16384 + 500000 us + 14 + + + CYCLE32768 + 1000000 us + 15 + + + + + + + CFDPRESC + Clock Failure Detector Prescaler + 0x12 + 8 + 0x00 + + + CFDPRESC + Clock Failure Detector Prescaler + 0 + 3 + + CFDPRESCSelect + + DIV1 + 48 MHz + 0 + + + DIV2 + 24 MHz + 1 + + + DIV4 + 12 MHz + 2 + + + DIV8 + 6 MHz + 3 + + + DIV16 + 3 MHz + 4 + + + DIV32 + 1.5 MHz + 5 + + + DIV64 + 0.75 MHz + 6 + + + DIV128 + 0.3125 MHz + 7 + + + + + + + EVCTRL + Event Control + 0x13 + 8 + 0x00 + + + CFDEO + Clock Failure Detector Event Output Enable + 0 + 1 + + + + + OSC48MCTRL + 48MHz Internal Oscillator (OSC48M) Control + 0x14 + 8 + 0x82 + + + ENABLE + Oscillator Enable + 1 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + + + OSC48MDIV + OSC48M Divider + 0x15 + 8 + 0x0B + + + DIV + OSC48M Division Factor + 0 + 4 + + DIVSelect + + DIV1 + 48 MHz + 0 + + + DIV2 + 24 MHz + 1 + + + DIV3 + 16 MHz + 2 + + + DIV4 + 12 MHz + 3 + + + DIV5 + 9.6 MHz + 4 + + + DIV6 + 8 MHz + 5 + + + DIV7 + 6.86 MHz + 6 + + + DIV8 + 6 MHz + 7 + + + DIV9 + 5.33 MHz + 8 + + + DIV10 + 4.8 MHz + 9 + + + DIV11 + 4.36 MHz + 10 + + + DIV12 + 4 MHz + 11 + + + DIV13 + 3.69 MHz + 12 + + + DIV14 + 3.43 MHz + 13 + + + DIV15 + 3.2 MHz + 14 + + + DIV16 + 3 MHz + 15 + + + + + + + OSC48MSTUP + OSC48M Startup Time + 0x16 + 8 + 0x07 + + + STARTUP + Startup Time + 0 + 3 + + STARTUPSelect + + CYCLE8 + 166 ns + 0 + + + CYCLE16 + 333 ns + 1 + + + CYCLE32 + 667 ns + 2 + + + CYCLE64 + 1.333 us + 3 + + + CYCLE128 + 2.667 us + 4 + + + CYCLE256 + 5.333 us + 5 + + + CYCLE512 + 10.667 us + 6 + + + CYCLE1024 + 21.333 us + 7 + + + + + + + OSC48MSYNCBUSY + OSC48M Synchronization Busy + 0x18 + 32 + read-only + 0x00000000 + + + OSC48MDIV + OSC48MDIV Synchronization Status + 2 + 1 + + + + + DPLLCTRLA + DPLL Control + 0x1C + 8 + 0x80 + + + ENABLE + Enable + 1 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand + 7 + 1 + + + + + DPLLRATIO + DPLL Ratio Control + 0x20 + 32 + 0x00000000 + + + LDR + Loop Divider Ratio + 0 + 12 + + + LDRFRAC + Loop Divider Ratio Fractional Part + 16 + 4 + + + + + DPLLCTRLB + Digital Core Configuration + 0x24 + 32 + 0x00000000 + + + FILTER + Proportional Integral Filter Selection + 0 + 2 + + FILTERSelect + + DEFAULT + Default filter mode + 0 + + + LBFILT + Low bandwidth filter + 1 + + + HBFILT + High bandwidth filter + 2 + + + HDFILT + High damping filter + 3 + + + + + LPEN + Low-Power Enable + 2 + 1 + + + WUF + Wake Up Fast + 3 + 1 + + + REFCLK + Reference Clock Selection + 4 + 2 + + REFCLKSelect + + XOSC32K + XOSC32K clock reference + 0 + + + XOSC + XOSC clock reference + 1 + + + GCLK + GCLK clock reference + 2 + + + + + LTIME + Lock Time + 8 + 3 + + LTIMESelect + + DEFAULT + No time-out. Automatic lock. + 0 + + + 8MS + Time-out if no lock within 8ms + 4 + + + 9MS + Time-out if no lock within 9ms + 5 + + + 10MS + Time-out if no lock within 10ms + 6 + + + 11MS + Time-out if no lock within 11ms + 7 + + + + + LBYPASS + Lock Bypass + 12 + 1 + + + DIV + Clock Divider + 16 + 11 + + + + + DPLLPRESC + DPLL Prescaler + 0x28 + 8 + 0x00 + + + PRESC + Output Clock Prescaler + 0 + 2 + + PRESCSelect + + DIV1 + DPLL output is divided by 1 + 0 + + + DIV2 + DPLL output is divided by 2 + 1 + + + DIV4 + DPLL output is divided by 4 + 2 + + + + + + + DPLLSYNCBUSY + DPLL Synchronization Busy + 0x2C + 8 + read-only + 0x00 + + + ENABLE + DPLL Enable Synchronization Status + 1 + 1 + + + DPLLRATIO + DPLL Ratio Synchronization Status + 2 + 1 + + + DPLLPRESC + DPLL Prescaler Synchronization Status + 3 + 1 + + + + + DPLLSTATUS + DPLL Status + 0x30 + 8 + read-only + 0x00 + + + LOCK + DPLL Lock Status + 0 + 1 + + + CLKRDY + DPLL Clock Ready + 1 + 1 + + + + + CAL48M + 48MHz Oscillator Calibration + 0x38 + 32 + 0x00000000 + + + FCAL + Frequency Calibration (48MHz) + 0 + 6 + + + FRANGE + Frequency Range (48MHz) + 8 + 2 + + + TCAL + Temperature Calibration (48MHz) + 16 + 6 + + + + + + + OSC32KCTRL + U22462.1.0 + 32k Oscillators Control + OSC32KCTRL + OSC32KCTRL_ + 0x40001400 + + 0 + 0x20 + registers + + + + INTENCLR + Interrupt Enable Clear + 0x0 + 32 + 0x00000000 + + + XOSC32KRDY + XOSC32K Ready Interrupt Enable + 0 + 1 + + + OSC32KRDY + OSC32K Ready Interrupt Enable + 1 + 1 + + + CLKFAIL + XOSC32K Clock Failure Detector Interrupt Enable + 2 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x4 + 32 + 0x00000000 + + + XOSC32KRDY + XOSC32K Ready Interrupt Enable + 0 + 1 + + + OSC32KRDY + OSC32K Ready Interrupt Enable + 1 + 1 + + + CLKFAIL + XOSC32K Clock Failure Detector Interrupt Enable + 2 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x8 + 32 + 0x00000000 + + + XOSC32KRDY + XOSC32K Ready + 0 + 1 + + + OSC32KRDY + OSC32K Ready + 1 + 1 + + + CLKFAIL + XOSC32K Clock Failure Detector + 2 + 1 + + + + + STATUS + Power and Clocks Status + 0xC + 32 + read-only + 0x00000000 + + + XOSC32KRDY + XOSC32K Ready + 0 + 1 + + + OSC32KRDY + OSC32K Ready + 1 + 1 + + + CLKFAIL + XOSC32K Clock Failure Detector + 2 + 1 + + + CLKSW + XOSC32K Clock switch + 3 + 1 + + + + + RTCCTRL + Clock selection + 0x10 + 32 + 0x00000000 + + + RTCSEL + RTC Clock Selection + 0 + 3 + + RTCSELSelect + + ULP1K + 1.024kHz from 32kHz internal ULP oscillator + 0 + + + ULP32K + 32.768kHz from 32kHz internal ULP oscillator + 1 + + + OSC1K + 1.024kHz from 32.768kHz internal oscillator + 2 + + + OSC32K + 32.768kHz from 32.768kHz internal oscillator + 3 + + + XOSC1K + 1.024kHz from 32.768kHz internal oscillator + 4 + + + XOSC32K + 32.768kHz from 32.768kHz external crystal oscillator + 5 + + + + + + + XOSC32K + 32kHz External Crystal Oscillator (XOSC32K) Control + 0x14 + 16 + 0x0080 + + + ENABLE + Oscillator Enable + 1 + 1 + + + XTALEN + Crystal Oscillator Enable + 2 + 1 + + + EN32K + 32kHz Output Enable + 3 + 1 + + + EN1K + 1kHz Output Enable + 4 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + STARTUP + Oscillator Start-Up Time + 8 + 3 + + STARTUPSelect + + CYCLE1 + 0.122 ms + 0 + + + CYCLE32 + 1.068 ms + 1 + + + CYCLE2048 + 62.6 ms + 2 + + + CYCLE4096 + 125 ms + 3 + + + CYCLE16384 + 500 ms + 4 + + + CYCLE32768 + 1000 ms + 5 + + + CYCLE65536 + 2000 ms + 6 + + + CYCLE131072 + 4000 ms + 7 + + + + + WRTLOCK + Write Lock + 12 + 1 + + + + + CFDCTRL + Clock Failure Detector Control + 0x16 + 8 + 0x00 + + + CFDEN + Clock Failure Detector Enable + 0 + 1 + + + SWBACK + Clock Switch Back + 1 + 1 + + + CFDPRESC + Clock Failure Detector Prescaler + 2 + 1 + + + + + EVCTRL + Event Control + 0x17 + 8 + 0x00 + + + CFDEO + Clock Failure Detector Event Output Enable + 0 + 1 + + + + + OSC32K + 32kHz Internal Oscillator (OSC32K) Control + 0x18 + 32 + 0x003F0080 + + + ENABLE + Oscillator Enable + 1 + 1 + + + EN32K + 32kHz Output Enable + 2 + 1 + + + EN1K + 1kHz Output Enable + 3 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + STARTUP + Oscillator Start-Up Time + 8 + 3 + + STARTUPSelect + + CYCLE3 + 0.092 ms + 0 + + + CYCLE4 + 0.122 ms + 1 + + + CYCLE6 + 0.183 ms + 2 + + + CYCLE10 + 0.305 ms + 3 + + + CYCLE18 + 0.549 ms + 4 + + + CYCLE34 + 1.038 ms + 5 + + + CYCLE66 + 2.014 ms + 6 + + + CYCLE130 + 3.967 ms + 7 + + + + + WRTLOCK + Write Lock + 12 + 1 + + + CALIB + Oscillator Calibration + 16 + 7 + + + + + OSCULP32K + 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control + 0x1C + 32 + + + CALIB + Oscillator Calibration + 8 + 5 + + + WRTLOCK + Write Lock + 15 + 1 + + + + + + + PAC + U21201.1.0 + Peripheral Access Controller + PAC + PAC_ + 0x40000000 + + 0 + 0x40 + registers + + + + WRCTRL + Write control + 0x0 + 32 + 0x00000000 + + + PERID + Peripheral identifier + 0 + 16 + + + KEY + Peripheral access control key + 16 + 8 + + KEYSelect + + OFF + No action + 0 + + + CLR + Clear protection + 1 + + + SET + Set protection + 2 + + + SETLCK + Set and lock protection + 3 + + + + + + + EVCTRL + Event control + 0x4 + 8 + 0x00 + + + ERREO + Peripheral acess error event output + 0 + 1 + + + + + INTENCLR + Interrupt enable clear + 0x8 + 8 + 0x00 + + + ERR + Peripheral access error interrupt disable + 0 + 1 + + + + + INTENSET + Interrupt enable set + 0x9 + 8 + 0x00 + + + ERR + Peripheral access error interrupt enable + 0 + 1 + + + + + INTFLAGAHB + Bridge interrupt flag status + 0x10 + 32 + 0x00000000 + + + FLASH_ + FLASH + 0 + 1 + + + HSRAMCM0P_ + HSRAMCM0P + 1 + 1 + + + HSRAMDSU_ + HSRAMDSU + 2 + 1 + + + HPB1_ + HPB1 + 3 + 1 + + + HPB0_ + HPB0 + 4 + 1 + + + HPB2_ + HPB2 + 5 + 1 + + + LPRAMDMAC_ + LPRAMDMAC + 6 + 1 + + + DIVAS_ + DIVAS + 7 + 1 + + + + + INTFLAGA + Peripheral interrupt flag status - Bridge A + 0x14 + 32 + 0x00000000 + + + PAC_ + PAC + 0 + 1 + + + PM_ + PM + 1 + 1 + + + MCLK_ + MCLK + 2 + 1 + + + RSTC_ + RSTC + 3 + 1 + + + OSCCTRL_ + OSCCTRL + 4 + 1 + + + OSC32KCTRL_ + OSC32KCTRL + 5 + 1 + + + SUPC_ + SUPC + 6 + 1 + + + GCLK_ + GCLK + 7 + 1 + + + WDT_ + WDT + 8 + 1 + + + RTC_ + RTC + 9 + 1 + + + EIC_ + EIC + 10 + 1 + + + FREQM_ + FREQM + 11 + 1 + + + + + INTFLAGB + Peripheral interrupt flag status - Bridge B + 0x18 + 32 + 0x00000000 + + + PORT_ + PORT + 0 + 1 + + + DSU_ + DSU + 1 + 1 + + + NVMCTRL_ + NVMCTRL + 2 + 1 + + + DMAC_ + DMAC + 3 + 1 + + + MTB_ + MTB + 4 + 1 + + + HMATRIXHS_ + HMATRIXHS + 5 + 1 + + + + + INTFLAGC + Peripheral interrupt flag status - Bridge C + 0x1C + 32 + 0x00000000 + + + EVSYS_ + EVSYS + 0 + 1 + + + SERCOM0_ + SERCOM0 + 1 + 1 + + + SERCOM1_ + SERCOM1 + 2 + 1 + + + SERCOM2_ + SERCOM2 + 3 + 1 + + + SERCOM3_ + SERCOM3 + 4 + 1 + + + TCC0_ + TCC0 + 9 + 1 + + + TCC1_ + TCC1 + 10 + 1 + + + TCC2_ + TCC2 + 11 + 1 + + + TC0_ + TC0 + 12 + 1 + + + TC1_ + TC1 + 13 + 1 + + + TC2_ + TC2 + 14 + 1 + + + TC3_ + TC3 + 15 + 1 + + + TC4_ + TC4 + 16 + 1 + + + ADC0_ + ADC0 + 17 + 1 + + + AC_ + AC + 20 + 1 + + + PTC_ + PTC + 22 + 1 + + + CCL_ + CCL + 23 + 1 + + + + + STATUSA + Peripheral write protection status - Bridge A + 0x34 + 32 + read-only + 0x00000000 + + + PAC_ + PAC APB Protect Enable + 0 + 1 + + + PM_ + PM APB Protect Enable + 1 + 1 + + + MCLK_ + MCLK APB Protect Enable + 2 + 1 + + + RSTC_ + RSTC APB Protect Enable + 3 + 1 + + + OSCCTRL_ + OSCCTRL APB Protect Enable + 4 + 1 + + + OSC32KCTRL_ + OSC32KCTRL APB Protect Enable + 5 + 1 + + + SUPC_ + SUPC APB Protect Enable + 6 + 1 + + + GCLK_ + GCLK APB Protect Enable + 7 + 1 + + + WDT_ + WDT APB Protect Enable + 8 + 1 + + + RTC_ + RTC APB Protect Enable + 9 + 1 + + + EIC_ + EIC APB Protect Enable + 10 + 1 + + + FREQM_ + FREQM APB Protect Enable + 11 + 1 + + + + + STATUSB + Peripheral write protection status - Bridge B + 0x38 + 32 + read-only + 0x00000002 + + + PORT_ + PORT APB Protect Enable + 0 + 1 + + + DSU_ + DSU APB Protect Enable + 1 + 1 + + + NVMCTRL_ + NVMCTRL APB Protect Enable + 2 + 1 + + + DMAC_ + DMAC APB Protect Enable + 3 + 1 + + + MTB_ + MTB APB Protect Enable + 4 + 1 + + + HMATRIXHS_ + HMATRIXHS APB Protect Enable + 5 + 1 + + + + + STATUSC + Peripheral write protection status - Bridge C + 0x3C + 32 + read-only + 0x02000000 + + + EVSYS_ + EVSYS APB Protect Enable + 0 + 1 + + + SERCOM0_ + SERCOM0 APB Protect Enable + 1 + 1 + + + SERCOM1_ + SERCOM1 APB Protect Enable + 2 + 1 + + + SERCOM2_ + SERCOM2 APB Protect Enable + 3 + 1 + + + SERCOM3_ + SERCOM3 APB Protect Enable + 4 + 1 + + + TCC0_ + TCC0 APB Protect Enable + 9 + 1 + + + TCC1_ + TCC1 APB Protect Enable + 10 + 1 + + + TCC2_ + TCC2 APB Protect Enable + 11 + 1 + + + TC0_ + TC0 APB Protect Enable + 12 + 1 + + + TC1_ + TC1 APB Protect Enable + 13 + 1 + + + TC2_ + TC2 APB Protect Enable + 14 + 1 + + + TC3_ + TC3 APB Protect Enable + 15 + 1 + + + TC4_ + TC4 APB Protect Enable + 16 + 1 + + + ADC0_ + ADC0 APB Protect Enable + 17 + 1 + + + AC_ + AC APB Protect Enable + 20 + 1 + + + PTC_ + PTC APB Protect Enable + 22 + 1 + + + CCL_ + CCL APB Protect Enable + 23 + 1 + + + + + + + PM + U22402.1.0 + Power Manager + PM + PM_ + 0x40000400 + + 0 + 0xA + registers + + + + SLEEPCFG + Sleep Configuration + 0x1 + 8 + 0x00 + + + SLEEPMODE + Sleep Mode + 0 + 3 + + SLEEPMODESelect + + IDLE0 + CPU clock is OFF + 0 + + + IDLE1 + AHB clock is OFF + 1 + + + IDLE2 + APB clock are OFF + 2 + + + STANDBY + All Clocks are OFF + 4 + + + + + + + STDBYCFG + Standby Configuration + 0x8 + 16 + 0x0400 + + + VREGSMOD + Voltage Regulator Standby mode + 6 + 2 + + VREGSMODSelect + + AUTO + Automatic mode + 0 + + + PERFORMANCE + Performance oriented + 1 + + + LP + Low Power oriented + 2 + + + + + BBIASHS + Back Bias for HMCRAMCHS + 10 + 1 + + + + + + + PORT + U22102.1.1 + Port Module + PORT + PORT_ + 0x41000000 + + 0 + 0x100 + registers + + + + 2 + 0x80 + GROUP[%s] + + 0x00 + + DIR + Data Direction + 0x0 + 32 + 0x00000000 + + + DIRCLR + Data Direction Clear + 0x4 + 32 + 0x00000000 + + + DIRSET + Data Direction Set + 0x8 + 32 + 0x00000000 + + + DIRTGL + Data Direction Toggle + 0xC + 32 + 0x00000000 + + + OUT + Data Output Value + 0x10 + 32 + 0x00000000 + + + OUTCLR + Data Output Value Clear + 0x14 + 32 + 0x00000000 + + + OUTSET + Data Output Value Set + 0x18 + 32 + 0x00000000 + + + OUTTGL + Data Output Value Toggle + 0x1C + 32 + 0x00000000 + + + IN + Data Input Value + 0x20 + 32 + read-only + 0x00000000 + + + CTRL + Control + 0x24 + 32 + 0x00000000 + + + SAMPLING + Input Sampling Mode + 0 + 32 + + + + + WRCONFIG + Write Configuration + 0x28 + 32 + write-only + 0x00000000 + + + PINMASK + Pin Mask for Multiple Pin Configuration + 0 + 16 + + + PMUXEN + Select Peripheral Multiplexer + 16 + 1 + + + INEN + Input Enable + 17 + 1 + + + PULLEN + Pull Enable + 18 + 1 + + + DRVSTR + Output Driver Strength Selection + 22 + 1 + + + PMUX + Peripheral Multiplexing Template + 24 + 4 + + + WRPMUX + Write PMUX Registers + 28 + 1 + + + WRPINCFG + Write PINCFG Registers + 30 + 1 + + + HWSEL + Half-Word Select + 31 + 1 + + + + + EVCTRL + Event Input Control + 0x2C + 32 + 0x00000000 + + + PID0 + Port Event Pin Identifier 0 + 0 + 5 + + + EVACT0 + Port Event Action 0 + 5 + 2 + + EVACT0Select + + OUT + Event output to pin + 0x0 + + + SET + Set output register of pin on event + 0x1 + + + CLR + Clear output register of pin on event + 0x2 + + + TGL + Toggle output register of pin on event + 0x3 + + + + + PORTEI0 + Port Event Enable Input 0 + 7 + 1 + + + PID1 + Port Event Pin Identifier 1 + 8 + 5 + + + EVACT1 + Port Event Action 1 + 13 + 2 + + + PORTEI1 + Port Event Enable Input 1 + 15 + 1 + + + PID2 + Port Event Pin Identifier 2 + 16 + 5 + + + EVACT2 + Port Event Action 2 + 21 + 2 + + + PORTEI2 + Port Event Enable Input 2 + 23 + 1 + + + PID3 + Port Event Pin Identifier 3 + 24 + 5 + + + EVACT3 + Port Event Action 3 + 29 + 2 + + + PORTEI3 + Port Event Enable Input 3 + 31 + 1 + + + + + 16 + 1 + PMUX[%s] + Peripheral Multiplexing n + 0x30 + 8 + 0x00 + + + PMUXE + Peripheral Multiplexing for Even-Numbered Pin + 0 + 4 + + + PMUXO + Peripheral Multiplexing for Odd-Numbered Pin + 4 + 4 + + + + + 32 + 1 + PINCFG[%s] + Pin Configuration n + 0x40 + 8 + 0x00 + + + PMUXEN + Select Peripheral Multiplexer + 0 + 1 + + + INEN + Input Enable + 1 + 1 + + + PULLEN + Pull Enable + 2 + 1 + + + DRVSTR + Output Driver Strength Selection + 6 + 1 + + + + + + + + PORT_IOBUS + PORT_IOBUS_ + 0x60000000 + + + PTC + U22153.1.0 + Peripheral Touch Controller + PTC + PTC_ + 0x42005800 + + 0 + 0x1 + reserved + + + PTC + 30 + + + + RSTC + U22392.0.2 + Reset Controller + RSTC + RSTC_ + 0x40000C00 + + 0 + 0x1 + registers + + + + RCAUSE + Reset Cause + 0x0 + 8 + read-only + + + POR + Power On Reset + 0 + 1 + + + BODCORE + Brown Out CORE Detector Reset + 1 + 1 + + + BODVDD + Brown Out VDD Detector Reset + 2 + 1 + + + EXT + External Reset + 4 + 1 + + + WDT + Watchdog Reset + 5 + 1 + + + SYST + System Reset Request + 6 + 1 + + + + + + + RTC + U22501.1.1 + Real-Time Counter + RTC + RTC_ + 0x40002400 + + 0 + 0x25 + registers + + + RTC + 2 + + + + MODE0 + 32-bit Counter with Single 32-bit Compare + RtcMode0 + 0x0 + + CTRLA + MODE0 Control A + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 2 + + MODESelect + + COUNT32 + Mode 0: 32-bit Counter + 0x0 + + + COUNT16 + Mode 1: 16-bit Counter + 0x1 + + + CLOCK + Mode 2: Clock/Calendar + 0x2 + + + + + MATCHCLR + Clear on Match + 7 + 1 + + + PRESCALER + Prescaler + 8 + 4 + + PRESCALERSelect + + OFF + CLK_RTC_CNT = GCLK_RTC/1 + 0x0 + + + DIV1 + CLK_RTC_CNT = GCLK_RTC/1 + 0x1 + + + DIV2 + CLK_RTC_CNT = GCLK_RTC/2 + 0x2 + + + DIV4 + CLK_RTC_CNT = GCLK_RTC/4 + 0x3 + + + DIV8 + CLK_RTC_CNT = GCLK_RTC/8 + 0x4 + + + DIV16 + CLK_RTC_CNT = GCLK_RTC/16 + 0x5 + + + DIV32 + CLK_RTC_CNT = GCLK_RTC/32 + 0x6 + + + DIV64 + CLK_RTC_CNT = GCLK_RTC/64 + 0x7 + + + DIV128 + CLK_RTC_CNT = GCLK_RTC/128 + 0x8 + + + DIV256 + CLK_RTC_CNT = GCLK_RTC/256 + 0x9 + + + DIV512 + CLK_RTC_CNT = GCLK_RTC/512 + 0xA + + + DIV1024 + CLK_RTC_CNT = GCLK_RTC/1024 + 0xB + + + + + COUNTSYNC + Count Read Synchronization Enable + 15 + 1 + + + + + EVCTRL + MODE0 Event Control + 0x4 + 32 + 0x00000000 + + + PEREO0 + Periodic Interval 0 Event Output Enable + 0 + 1 + + + PEREO1 + Periodic Interval 1 Event Output Enable + 1 + 1 + + + PEREO2 + Periodic Interval 2 Event Output Enable + 2 + 1 + + + PEREO3 + Periodic Interval 3 Event Output Enable + 3 + 1 + + + PEREO4 + Periodic Interval 4 Event Output Enable + 4 + 1 + + + PEREO5 + Periodic Interval 5 Event Output Enable + 5 + 1 + + + PEREO6 + Periodic Interval 6 Event Output Enable + 6 + 1 + + + PEREO7 + Periodic Interval 7 Event Output Enable + 7 + 1 + + + CMPEO0 + Compare 0 Event Output Enable + 8 + 1 + + + OVFEO + Overflow Event Output Enable + 15 + 1 + + + + + INTENCLR + MODE0 Interrupt Enable Clear + 0x8 + 16 + 0x0000 + + + PER0 + Periodic Interval 0 Interrupt Enable + 0 + 1 + + + PER1 + Periodic Interval 1 Interrupt Enable + 1 + 1 + + + PER2 + Periodic Interval 2 Interrupt Enable + 2 + 1 + + + PER3 + Periodic Interval 3 Interrupt Enable + 3 + 1 + + + PER4 + Periodic Interval 4 Interrupt Enable + 4 + 1 + + + PER5 + Periodic Interval 5 Interrupt Enable + 5 + 1 + + + PER6 + Periodic Interval 6 Interrupt Enable + 6 + 1 + + + PER7 + Periodic Interval 7 Interrupt Enable + 7 + 1 + + + CMP0 + Compare 0 Interrupt Enable + 8 + 1 + + + OVF + Overflow Interrupt Enable + 15 + 1 + + + + + INTENSET + MODE0 Interrupt Enable Set + 0xA + 16 + 0x0000 + + + PER0 + Periodic Interval 0 Interrupt Enable + 0 + 1 + + + PER1 + Periodic Interval 1 Interrupt Enable + 1 + 1 + + + PER2 + Periodic Interval 2 Interrupt Enable + 2 + 1 + + + PER3 + Periodic Interval 3 Interrupt Enable + 3 + 1 + + + PER4 + Periodic Interval 4 Interrupt Enable + 4 + 1 + + + PER5 + Periodic Interval 5 Interrupt Enable + 5 + 1 + + + PER6 + Periodic Interval 6 Interrupt Enable + 6 + 1 + + + PER7 + Periodic Interval 7 Interrupt Enable + 7 + 1 + + + CMP0 + Compare 0 Interrupt Enable + 8 + 1 + + + OVF + Overflow Interrupt Enable + 15 + 1 + + + + + INTFLAG + MODE0 Interrupt Flag Status and Clear + 0xC + 16 + 0x0000 + + + PER0 + Periodic Interval 0 + 0 + 1 + + + PER1 + Periodic Interval 1 + 1 + 1 + + + PER2 + Periodic Interval 2 + 2 + 1 + + + PER3 + Periodic Interval 3 + 3 + 1 + + + PER4 + Periodic Interval 4 + 4 + 1 + + + PER5 + Periodic Interval 5 + 5 + 1 + + + PER6 + Periodic Interval 6 + 6 + 1 + + + PER7 + Periodic Interval 7 + 7 + 1 + + + CMP0 + Compare 0 + 8 + 1 + + + OVF + Overflow + 15 + 1 + + + + + DBGCTRL + Debug Control + 0xE + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + SYNCBUSY + MODE0 Synchronization Busy Status + 0x10 + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Busy + 0 + 1 + + + ENABLE + Enable Bit Busy + 1 + 1 + + + FREQCORR + FREQCORR Register Busy + 2 + 1 + + + COUNT + COUNT Register Busy + 3 + 1 + + + COMP0 + COMP 0 Register Busy + 5 + 1 + + + COUNTSYNC + Count Read Synchronization Enable Bit Busy + 15 + 1 + + + + + FREQCORR + Frequency Correction + 0x14 + 8 + 0x00 + + + VALUE + Correction Value + 0 + 7 + + + SIGN + Correction Sign + 7 + 1 + + + + + COUNT + MODE0 Counter Value + 0x18 + 32 + 0x00000000 + + + COUNT + Counter Value + 0 + 32 + + + + + COMP + MODE0 Compare n Value + 0x20 + 32 + 0x00000000 + + + COMP + Compare Value + 0 + 32 + + + + + + MODE1 + 16-bit Counter with Two 16-bit Compares + MODE0 + RtcMode1 + 0x0 + + CTRLA + MODE1 Control A + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 2 + + MODESelect + + COUNT32 + Mode 0: 32-bit Counter + 0 + + + COUNT16 + Mode 1: 16-bit Counter + 1 + + + CLOCK + Mode 2: Clock/Calendar + 2 + + + + + PRESCALER + Prescaler + 8 + 4 + + PRESCALERSelect + + OFF + CLK_RTC_CNT = GCLK_RTC/1 + 0 + + + DIV1 + CLK_RTC_CNT = GCLK_RTC/1 + 1 + + + DIV2 + CLK_RTC_CNT = GCLK_RTC/2 + 2 + + + DIV4 + CLK_RTC_CNT = GCLK_RTC/4 + 3 + + + DIV8 + CLK_RTC_CNT = GCLK_RTC/8 + 4 + + + DIV16 + CLK_RTC_CNT = GCLK_RTC/16 + 5 + + + DIV32 + CLK_RTC_CNT = GCLK_RTC/32 + 6 + + + DIV64 + CLK_RTC_CNT = GCLK_RTC/64 + 7 + + + DIV128 + CLK_RTC_CNT = GCLK_RTC/128 + 8 + + + DIV256 + CLK_RTC_CNT = GCLK_RTC/256 + 9 + + + DIV512 + CLK_RTC_CNT = GCLK_RTC/512 + 0xA + + + DIV1024 + CLK_RTC_CNT = GCLK_RTC/1024 + 0xB + + + + + COUNTSYNC + Count Read Synchronization Enable + 15 + 1 + + + + + EVCTRL + MODE1 Event Control + 0x4 + 32 + 0x00000000 + + + PEREO0 + Periodic Interval 0 Event Output Enable + 0 + 1 + + + PEREO1 + Periodic Interval 1 Event Output Enable + 1 + 1 + + + PEREO2 + Periodic Interval 2 Event Output Enable + 2 + 1 + + + PEREO3 + Periodic Interval 3 Event Output Enable + 3 + 1 + + + PEREO4 + Periodic Interval 4 Event Output Enable + 4 + 1 + + + PEREO5 + Periodic Interval 5 Event Output Enable + 5 + 1 + + + PEREO6 + Periodic Interval 6 Event Output Enable + 6 + 1 + + + PEREO7 + Periodic Interval 7 Event Output Enable + 7 + 1 + + + CMPEO0 + Compare 0 Event Output Enable + 8 + 1 + + + CMPEO1 + Compare 1 Event Output Enable + 9 + 1 + + + OVFEO + Overflow Event Output Enable + 15 + 1 + + + + + INTENCLR + MODE1 Interrupt Enable Clear + 0x8 + 16 + 0x0000 + + + PER0 + Periodic Interval 0 Interrupt Enable + 0 + 1 + + + PER1 + Periodic Interval 1 Interrupt Enable + 1 + 1 + + + PER2 + Periodic Interval 2 Interrupt Enable + 2 + 1 + + + PER3 + Periodic Interval 3 Interrupt Enable + 3 + 1 + + + PER4 + Periodic Interval 4 Interrupt Enable + 4 + 1 + + + PER5 + Periodic Interval 5 Interrupt Enable + 5 + 1 + + + PER6 + Periodic Interval 6 Interrupt Enable + 6 + 1 + + + PER7 + Periodic Interval 7 Interrupt Enable + 7 + 1 + + + CMP0 + Compare 0 Interrupt Enable + 8 + 1 + + + CMP1 + Compare 1 Interrupt Enable + 9 + 1 + + + OVF + Overflow Interrupt Enable + 15 + 1 + + + + + INTENSET + MODE1 Interrupt Enable Set + 0xA + 16 + 0x0000 + + + PER0 + Periodic Interval 0 Interrupt Enable + 0 + 1 + + + PER1 + Periodic Interval 1 Interrupt Enable + 1 + 1 + + + PER2 + Periodic Interval 2 Interrupt Enable + 2 + 1 + + + PER3 + Periodic Interval 3 Interrupt Enable + 3 + 1 + + + PER4 + Periodic Interval 4 Interrupt Enable + 4 + 1 + + + PER5 + Periodic Interval 5 Interrupt Enable + 5 + 1 + + + PER6 + Periodic Interval 6 Interrupt Enable + 6 + 1 + + + PER7 + Periodic Interval 7 Interrupt Enable + 7 + 1 + + + CMP0 + Compare 0 Interrupt Enable + 8 + 1 + + + CMP1 + Compare 1 Interrupt Enable + 9 + 1 + + + OVF + Overflow Interrupt Enable + 15 + 1 + + + + + INTFLAG + MODE1 Interrupt Flag Status and Clear + 0xC + 16 + 0x0000 + + + PER0 + Periodic Interval 0 + 0 + 1 + + + PER1 + Periodic Interval 1 + 1 + 1 + + + PER2 + Periodic Interval 2 + 2 + 1 + + + PER3 + Periodic Interval 3 + 3 + 1 + + + PER4 + Periodic Interval 4 + 4 + 1 + + + PER5 + Periodic Interval 5 + 5 + 1 + + + PER6 + Periodic Interval 6 + 6 + 1 + + + PER7 + Periodic Interval 7 + 7 + 1 + + + CMP0 + Compare 0 + 8 + 1 + + + CMP1 + Compare 1 + 9 + 1 + + + OVF + Overflow + 15 + 1 + + + + + DBGCTRL + Debug Control + 0xE + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + SYNCBUSY + MODE1 Synchronization Busy Status + 0x10 + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Bit Busy + 0 + 1 + + + ENABLE + Enable Bit Busy + 1 + 1 + + + FREQCORR + FREQCORR Register Busy + 2 + 1 + + + COUNT + COUNT Register Busy + 3 + 1 + + + PER + PER Register Busy + 4 + 1 + + + COMP0 + COMP 0 Register Busy + 5 + 1 + + + COMP1 + COMP 1 Register Busy + 6 + 1 + + + COUNTSYNC + Count Read Synchronization Enable Bit Busy + 15 + 1 + + + + + FREQCORR + Frequency Correction + 0x14 + 8 + 0x00 + + + VALUE + Correction Value + 0 + 7 + + + SIGN + Correction Sign + 7 + 1 + + + + + COUNT + MODE1 Counter Value + 0x18 + 16 + 0x0000 + + + COUNT + Counter Value + 0 + 16 + + + + + PER + MODE1 Counter Period + 0x1C + 16 + 0x0000 + + + PER + Counter Period + 0 + 16 + + + + + 2 + 2 + COMP[%s] + MODE1 Compare n Value + 0x20 + 16 + 0x0000 + + + COMP + Compare Value + 0 + 16 + + + + + + MODE2 + Clock/Calendar with Alarm + MODE0 + RtcMode2 + 0x0 + + CTRLA + MODE2 Control A + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 2 + + MODESelect + + COUNT32 + Mode 0: 32-bit Counter + 0 + + + COUNT16 + Mode 1: 16-bit Counter + 1 + + + CLOCK + Mode 2: Clock/Calendar + 2 + + + + + CLKREP + Clock Representation + 6 + 1 + + + MATCHCLR + Clear on Match + 7 + 1 + + + PRESCALER + Prescaler + 8 + 4 + + PRESCALERSelect + + OFF + CLK_RTC_CNT = GCLK_RTC/1 + 0x0 + + + DIV1 + CLK_RTC_CNT = GCLK_RTC/1 + 0x1 + + + DIV2 + CLK_RTC_CNT = GCLK_RTC/2 + 0x2 + + + DIV4 + CLK_RTC_CNT = GCLK_RTC/4 + 0x3 + + + DIV8 + CLK_RTC_CNT = GCLK_RTC/8 + 0x4 + + + DIV16 + CLK_RTC_CNT = GCLK_RTC/16 + 0x5 + + + DIV32 + CLK_RTC_CNT = GCLK_RTC/32 + 0x6 + + + DIV64 + CLK_RTC_CNT = GCLK_RTC/64 + 0x7 + + + DIV128 + CLK_RTC_CNT = GCLK_RTC/128 + 0x8 + + + DIV256 + CLK_RTC_CNT = GCLK_RTC/256 + 0x9 + + + DIV512 + CLK_RTC_CNT = GCLK_RTC/512 + 0xA + + + DIV1024 + CLK_RTC_CNT = GCLK_RTC/1024 + 0xB + + + + + CLOCKSYNC + Clock Read Synchronization Enable + 15 + 1 + + + + + EVCTRL + MODE2 Event Control + 0x4 + 32 + 0x00000000 + + + PEREO0 + Periodic Interval 0 Event Output Enable + 0 + 1 + + + PEREO1 + Periodic Interval 1 Event Output Enable + 1 + 1 + + + PEREO2 + Periodic Interval 2 Event Output Enable + 2 + 1 + + + PEREO3 + Periodic Interval 3 Event Output Enable + 3 + 1 + + + PEREO4 + Periodic Interval 4 Event Output Enable + 4 + 1 + + + PEREO5 + Periodic Interval 5 Event Output Enable + 5 + 1 + + + PEREO6 + Periodic Interval 6 Event Output Enable + 6 + 1 + + + PEREO7 + Periodic Interval 7 Event Output Enable + 7 + 1 + + + ALARMEO0 + Alarm 0 Event Output Enable + 8 + 1 + + + OVFEO + Overflow Event Output Enable + 15 + 1 + + + + + INTENCLR + MODE2 Interrupt Enable Clear + 0x8 + 16 + 0x0000 + + + PER0 + Periodic Interval 0 Interrupt Enable + 0 + 1 + + + PER1 + Periodic Interval 1 Interrupt Enable + 1 + 1 + + + PER2 + Periodic Interval 2 Interrupt Enable + 2 + 1 + + + PER3 + Periodic Interval 3 Interrupt Enable + 3 + 1 + + + PER4 + Periodic Interval 4 Interrupt Enable + 4 + 1 + + + PER5 + Periodic Interval 5 Interrupt Enable + 5 + 1 + + + PER6 + Periodic Interval 6 Interrupt Enable + 6 + 1 + + + PER7 + Periodic Interval 7 Interrupt Enable + 7 + 1 + + + ALARM0 + Alarm 0 Interrupt Enable + 8 + 1 + + + OVF + Overflow Interrupt Enable + 15 + 1 + + + + + INTENSET + MODE2 Interrupt Enable Set + 0xA + 16 + 0x0000 + + + PER0 + Periodic Interval 0 Enable + 0 + 1 + + + PER1 + Periodic Interval 1 Enable + 1 + 1 + + + PER2 + Periodic Interval 2 Enable + 2 + 1 + + + PER3 + Periodic Interval 3 Enable + 3 + 1 + + + PER4 + Periodic Interval 4 Enable + 4 + 1 + + + PER5 + Periodic Interval 5 Enable + 5 + 1 + + + PER6 + Periodic Interval 6 Enable + 6 + 1 + + + PER7 + Periodic Interval 7 Enable + 7 + 1 + + + ALARM0 + Alarm 0 Interrupt Enable + 8 + 1 + + + OVF + Overflow Interrupt Enable + 15 + 1 + + + + + INTFLAG + MODE2 Interrupt Flag Status and Clear + 0xC + 16 + 0x0000 + + + PER0 + Periodic Interval 0 + 0 + 1 + + + PER1 + Periodic Interval 1 + 1 + 1 + + + PER2 + Periodic Interval 2 + 2 + 1 + + + PER3 + Periodic Interval 3 + 3 + 1 + + + PER4 + Periodic Interval 4 + 4 + 1 + + + PER5 + Periodic Interval 5 + 5 + 1 + + + PER6 + Periodic Interval 6 + 6 + 1 + + + PER7 + Periodic Interval 7 + 7 + 1 + + + ALARM0 + Alarm 0 + 8 + 1 + + + OVF + Overflow + 15 + 1 + + + + + DBGCTRL + Debug Control + 0xE + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + SYNCBUSY + MODE2 Synchronization Busy Status + 0x10 + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Bit Busy + 0 + 1 + + + ENABLE + Enable Bit Busy + 1 + 1 + + + FREQCORR + FREQCORR Register Busy + 2 + 1 + + + CLOCK + CLOCK Register Busy + 3 + 1 + + + ALARM0 + ALARM 0 Register Busy + 5 + 1 + + + MASK0 + MASK 0 Register Busy + 11 + 1 + + + CLOCKSYNC + Clock Read Synchronization Enable Bit Busy + 15 + 1 + + + + + FREQCORR + Frequency Correction + 0x14 + 8 + 0x00 + + + VALUE + Correction Value + 0 + 7 + + + SIGN + Correction Sign + 7 + 1 + + + + + CLOCK + MODE2 Clock Value + 0x18 + 32 + 0x00000000 + + + SECOND + Second + 0 + 6 + + + MINUTE + Minute + 6 + 6 + + + HOUR + Hour + 12 + 5 + + HOURSelect + + AM + AM when CLKREP in 12-hour + 0x00 + + + PM + PM when CLKREP in 12-hour + 0x10 + + + + + DAY + Day + 17 + 5 + + + MONTH + Month + 22 + 4 + + + YEAR + Year + 26 + 6 + + + + + ALARM + MODE2_ALARM Alarm n Value + 0x20 + 32 + 0x00000000 + + + SECOND + Second + 0 + 6 + + + MINUTE + Minute + 6 + 6 + + + HOUR + Hour + 12 + 5 + + HOURSelect + + AM + Morning hour + 0x00 + + + PM + Afternoon hour + 0x10 + + + + + DAY + Day + 17 + 5 + + + MONTH + Month + 22 + 4 + + + YEAR + Year + 26 + 6 + + + + + MASK + MODE2_ALARM Alarm n Mask + 0x24 + 8 + 0x00 + + + SEL + Alarm Mask Selection + 0 + 3 + + SELSelect + + OFF + Alarm Disabled + 0x0 + + + SS + Match seconds only + 0x1 + + + MMSS + Match seconds and minutes only + 0x2 + + + HHMMSS + Match seconds, minutes, and hours only + 0x3 + + + DDHHMMSS + Match seconds, minutes, hours, and days only + 0x4 + + + MMDDHHMMSS + Match seconds, minutes, hours, days, and months only + 0x5 + + + YYMMDDHHMMSS + Match seconds, minutes, hours, days, months, and years + 0x6 + + + + + + + + + + SERCOM0 + U22013.1.1 + Serial Communication Interface + SERCOM + SERCOM_ + 0x42000400 + + 0 + 0x31 + registers + + + SERCOM0 + 9 + + + + I2CM + I2C Master Mode + SercomI2cm + 0x0 + + CTRLA + I2CM Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run in Standby + 7 + 1 + + + PINOUT + Pin Usage + 16 + 1 + + + SDAHOLD + SDA Hold Time + 20 + 2 + + SDAHOLDSelect + + DISABLE + Disabled + 0x0 + + + 75NS + 50-100ns hold time + 0x1 + + + 450NS + 300-600ns hold time + 0x2 + + + 600NS + 400-800ns hold time + 0x3 + + + + + MEXTTOEN + Master SCL Low Extend Timeout + 22 + 1 + + + SEXTTOEN + Slave SCL Low Extend Timeout + 23 + 1 + + + SPEED + Transfer Speed + 24 + 2 + + SPEEDSelect + + STANDARD_AND_FAST_MODE + Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz + 0x0 + + + FASTPLUS_MODE + Fast-mode Plus Upto 1MHz + 0x1 + + + HIGH_SPEED_MODE + High-speed mode Upto 3.4MHz + 0x2 + + + + + SCLSM + SCL Clock Stretch Mode + 27 + 1 + + + INACTOUT + Inactive Time-Out + 28 + 2 + + INACTOUTSelect + + DISABLE + Disabled + 0x0 + + + 55US + 5-6 SCL Time-Out(50-60us) + 0x1 + + + 105US + 10-11 SCL Time-Out(100-110us) + 0x2 + + + 205US + 20-21 SCL Time-Out(200-210us) + 0x3 + + + + + LOWTOUTEN + SCL Low Timeout Enable + 30 + 1 + + + + + CTRLB + I2CM Control B + 0x4 + 32 + 0x00000000 + + + SMEN + Smart Mode Enable + 8 + 1 + + + QCEN + Quick Command Enable + 9 + 1 + + + CMD + Command + 16 + 2 + + + ACKACT + Acknowledge Action + 18 + 1 + + + + + BAUD + I2CM Baud Rate + 0xC + 32 + 0x00000000 + + + BAUD + Baud Rate Value + 0 + 8 + + + BAUDLOW + Baud Rate Value Low + 8 + 8 + + + HSBAUD + High Speed Baud Rate Value + 16 + 8 + + + HSBAUDLOW + High Speed Baud Rate Value Low + 24 + 8 + + + + + INTENCLR + I2CM Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + MB + Master On Bus Interrupt Disable + 0 + 1 + + + SB + Slave On Bus Interrupt Disable + 1 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + I2CM Interrupt Enable Set + 0x16 + 8 + 0x00 + + + MB + Master On Bus Interrupt Enable + 0 + 1 + + + SB + Slave On Bus Interrupt Enable + 1 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + I2CM Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + MB + Master On Bus Interrupt + 0 + 1 + + + SB + Slave On Bus Interrupt + 1 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + I2CM Status + 0x1A + 16 + 0x0000 + + + BUSERR + Bus Error + 0 + 1 + + + ARBLOST + Arbitration Lost + 1 + 1 + + + RXNACK + Received Not Acknowledge + 2 + 1 + + + BUSSTATE + Bus State + 4 + 2 + + + LOWTOUT + SCL Low Timeout + 6 + 1 + + + CLKHOLD + Clock Hold + 7 + 1 + + + MEXTTOUT + Master SCL Low Extend Timeout + 8 + 1 + + + SEXTTOUT + Slave SCL Low Extend Timeout + 9 + 1 + + + LENERR + Length Error + 10 + 1 + + + + + SYNCBUSY + I2CM Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + SYSOP + System Operation Synchronization Busy + 2 + 1 + + + + + ADDR + I2CM Address + 0x24 + 32 + 0x00000000 + + + ADDR + Address Value + 0 + 11 + + + LENEN + Length Enable + 13 + 1 + + + HS + High Speed Mode + 14 + 1 + + + TENBITEN + Ten Bit Addressing Enable + 15 + 1 + + + LEN + Length + 16 + 8 + + + + + DATA + I2CM Data + 0x28 + 8 + 0x00 + + + DATA + Data Value + 0 + 8 + + + + + DBGCTRL + I2CM Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + I2CS + I2C Slave Mode + I2CM + SercomI2cs + 0x0 + + CTRLA + I2CS Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + PINOUT + Pin Usage + 16 + 1 + + + SDAHOLD + SDA Hold Time + 20 + 2 + + SDAHOLDSelect + + DISABLE + Disabled + 0x0 + + + 75NS + 50-100ns hold time + 0x1 + + + 450NS + 300-600ns hold time + 0x2 + + + 600NS + 400-800ns hold time + 0x3 + + + + + SEXTTOEN + Slave SCL Low Extend Timeout + 23 + 1 + + + SPEED + Transfer Speed + 24 + 2 + + SPEEDSelect + + STANDARD_AND_FAST_MODE + Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz + 0x0 + + + FASTPLUS_MODE + Fast-mode Plus Upto 1MHz + 0x1 + + + HIGH_SPEED_MODE + High-speed mode Upto 3.4MHz + 0x2 + + + + + SCLSM + SCL Clock Stretch Mode + 27 + 1 + + + LOWTOUTEN + SCL Low Timeout Enable + 30 + 1 + + + + + CTRLB + I2CS Control B + 0x4 + 32 + 0x00000000 + + + SMEN + Smart Mode Enable + 8 + 1 + + + GCMD + PMBus Group Command + 9 + 1 + + + AACKEN + Automatic Address Acknowledge + 10 + 1 + + + AMODE + Address Mode + 14 + 2 + + + CMD + Command + 16 + 2 + + + ACKACT + Acknowledge Action + 18 + 1 + + + + + INTENCLR + I2CS Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + PREC + Stop Received Interrupt Disable + 0 + 1 + + + AMATCH + Address Match Interrupt Disable + 1 + 1 + + + DRDY + Data Interrupt Disable + 2 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + I2CS Interrupt Enable Set + 0x16 + 8 + 0x00 + + + PREC + Stop Received Interrupt Enable + 0 + 1 + + + AMATCH + Address Match Interrupt Enable + 1 + 1 + + + DRDY + Data Interrupt Enable + 2 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + I2CS Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + PREC + Stop Received Interrupt + 0 + 1 + + + AMATCH + Address Match Interrupt + 1 + 1 + + + DRDY + Data Interrupt + 2 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + I2CS Status + 0x1A + 16 + 0x0000 + + + BUSERR + Bus Error + 0 + 1 + + + COLL + Transmit Collision + 1 + 1 + + + RXNACK + Received Not Acknowledge + 2 + 1 + + + DIR + Read/Write Direction + 3 + 1 + + + SR + Repeated Start + 4 + 1 + + + LOWTOUT + SCL Low Timeout + 6 + 1 + + + CLKHOLD + Clock Hold + 7 + 1 + + + SEXTTOUT + Slave SCL Low Extend Timeout + 9 + 1 + + + HS + High Speed + 10 + 1 + + + + + SYNCBUSY + I2CS Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + + + ADDR + I2CS Address + 0x24 + 32 + 0x00000000 + + + GENCEN + General Call Address Enable + 0 + 1 + + + ADDR + Address Value + 1 + 10 + + + TENBITEN + Ten Bit Addressing Enable + 15 + 1 + + + ADDRMASK + Address Mask + 17 + 10 + + + + + DATA + I2CS Data + 0x28 + 8 + 0x00 + + + DATA + Data Value + 0 + 8 + + + + + + SPIS + SPI Slave Mode + I2CM + SercomSpis + 0x0 + + CTRLA + SPIS Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + IBON + Immediate Buffer Overflow Notification + 8 + 1 + + + DOPO + Data Out Pinout + 16 + 2 + + DOPOSelect + + PAD0 + DO on PAD[0], SCK on PAD[1] and SS on PAD[2] + 0x0 + + + PAD1 + DO on PAD[2], SCK on PAD[3] and SS on PAD[1] + 0x1 + + + PAD2 + DO on PAD[3], SCK on PAD[1] and SS on PAD[2] + 0x2 + + + PAD3 + DO on PAD[0], SCK on PAD[3] and SS on PAD[1] + 0x3 + + + + + DIPO + Data In Pinout + 20 + 2 + + DIPOSelect + + PAD0 + SERCOM PAD[0] + 0x0 + + + PAD1 + SERCOM PAD[1] + 0x1 + + + PAD2 + SERCOM PAD[2] + 0x2 + + + PAD3 + SERCOM PAD[3] + 0x3 + + + + + FORM + Frame Format + 24 + 4 + + FORMSelect + + SPI_FRAME + SPI Frame + 0x0 + + + SPI_FRAME_WITH_ADDR + SPI Frame with Addr + 0x2 + + + + + CPHA + Clock Phase + 28 + 1 + + CPHASelect + + LEADING_EDGE + The data is sampled on a leading SCK edge and changed on a trailing SCK edge + 0x0 + + + TRAILING_EDGE + The data is sampled on a trailing SCK edge and changed on a leading SCK edge + 0x1 + + + + + CPOL + Clock Polarity + 29 + 1 + + CPOLSelect + + IDLE_LOW + SCK is low when idle + 0x0 + + + IDLE_HIGH + SCK is high when idle + 0x1 + + + + + DORD + Data Order + 30 + 1 + + DORDSelect + + MSB + MSB is transferred first + 0x0 + + + LSB + LSB is transferred first + 0x1 + + + + + + + CTRLB + SPIS Control B + 0x4 + 32 + 0x00000000 + + + CHSIZE + Character Size + 0 + 3 + + CHSIZESelect + + 8_BIT + 8 bits + 0x0 + + + 9_BIT + 9 bits + 0x1 + + + + + PLOADEN + Data Preload Enable + 6 + 1 + + + SSDE + Slave Select Low Detect Enable + 9 + 1 + + + MSSEN + Master Slave Select Enable + 13 + 1 + + + AMODE + Address Mode + 14 + 2 + + AMODESelect + + MASK + SPI Address mask + 0x0 + + + 2_ADDRESSES + Two unique Addressess + 0x1 + + + RANGE + Address Range + 0x2 + + + + + RXEN + Receiver Enable + 17 + 1 + + + + + BAUD + SPIS Baud Rate + 0xC + 8 + 0x00 + + + BAUD + Baud Rate Value + 0 + 8 + + + + + INTENCLR + SPIS Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Disable + 0 + 1 + + + TXC + Transmit Complete Interrupt Disable + 1 + 1 + + + RXC + Receive Complete Interrupt Disable + 2 + 1 + + + SSL + Slave Select Low Interrupt Disable + 3 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + SPIS Interrupt Enable Set + 0x16 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Enable + 0 + 1 + + + TXC + Transmit Complete Interrupt Enable + 1 + 1 + + + RXC + Receive Complete Interrupt Enable + 2 + 1 + + + SSL + Slave Select Low Interrupt Enable + 3 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + SPIS Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt + 0 + 1 + + + TXC + Transmit Complete Interrupt + 1 + 1 + + + RXC + Receive Complete Interrupt + 2 + 1 + + + SSL + Slave Select Low Interrupt Flag + 3 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + SPIS Status + 0x1A + 16 + 0x0000 + + + BUFOVF + Buffer Overflow + 2 + 1 + + + + + SYNCBUSY + SPIS Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + CTRLB + CTRLB Synchronization Busy + 2 + 1 + + + + + ADDR + SPIS Address + 0x24 + 32 + 0x00000000 + + + ADDR + Address Value + 0 + 8 + + + ADDRMASK + Address Mask + 16 + 8 + + + + + DATA + SPIS Data + 0x28 + 32 + 0x00000000 + + + DATA + Data Value + 0 + 9 + + + + + DBGCTRL + SPIS Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + SPIM + SPI Master Mode + I2CM + SercomSpim + 0x0 + + CTRLA + SPIM Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + IBON + Immediate Buffer Overflow Notification + 8 + 1 + + + DOPO + Data Out Pinout + 16 + 2 + + DOPOSelect + + PAD0 + DO on PAD[0], SCK on PAD[1] and SS on PAD[2] + 0x0 + + + PAD1 + DO on PAD[2], SCK on PAD[3] and SS on PAD[1] + 0x1 + + + PAD2 + DO on PAD[3], SCK on PAD[1] and SS on PAD[2] + 0x2 + + + PAD3 + DO on PAD[0], SCK on PAD[3] and SS on PAD[1] + 0x3 + + + + + DIPO + Data In Pinout + 20 + 2 + + DIPOSelect + + PAD0 + SERCOM PAD[0] + 0x0 + + + PAD1 + SERCOM PAD[1] + 0x1 + + + PAD2 + SERCOM PAD[2] + 0x2 + + + PAD3 + SERCOM PAD[3] + 0x3 + + + + + FORM + Frame Format + 24 + 4 + + FORMSelect + + SPI_FRAME + SPI Frame + 0x0 + + + SPI_FRAME_WITH_ADDR + SPI Frame with Addr + 0x2 + + + + + CPHA + Clock Phase + 28 + 1 + + CPHASelect + + LEADING_EDGE + The data is sampled on a leading SCK edge and changed on a trailing SCK edge + 0x0 + + + TRAILING_EDGE + The data is sampled on a trailing SCK edge and changed on a leading SCK edge + 0x1 + + + + + CPOL + Clock Polarity + 29 + 1 + + CPOLSelect + + IDLE_LOW + SCK is low when idle + 0x0 + + + IDLE_HIGH + SCK is high when idle + 0x1 + + + + + DORD + Data Order + 30 + 1 + + DORDSelect + + MSB + MSB is transferred first + 0x0 + + + LSB + LSB is transferred first + 0x1 + + + + + + + CTRLB + SPIM Control B + 0x4 + 32 + 0x00000000 + + + CHSIZE + Character Size + 0 + 3 + + CHSIZESelect + + 8_BIT + 8 bits + 0x0 + + + 9_BIT + 9 bits + 0x1 + + + + + PLOADEN + Data Preload Enable + 6 + 1 + + + SSDE + Slave Select Low Detect Enable + 9 + 1 + + + MSSEN + Master Slave Select Enable + 13 + 1 + + + AMODE + Address Mode + 14 + 2 + + AMODESelect + + MASK + SPI Address mask + 0x0 + + + 2_ADDRESSES + Two unique Addressess + 0x1 + + + RANGE + Address Range + 0x2 + + + + + RXEN + Receiver Enable + 17 + 1 + + + + + BAUD + SPIM Baud Rate + 0xC + 8 + 0x00 + + + BAUD + Baud Rate Value + 0 + 8 + + + + + INTENCLR + SPIM Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Disable + 0 + 1 + + + TXC + Transmit Complete Interrupt Disable + 1 + 1 + + + RXC + Receive Complete Interrupt Disable + 2 + 1 + + + SSL + Slave Select Low Interrupt Disable + 3 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + SPIM Interrupt Enable Set + 0x16 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Enable + 0 + 1 + + + TXC + Transmit Complete Interrupt Enable + 1 + 1 + + + RXC + Receive Complete Interrupt Enable + 2 + 1 + + + SSL + Slave Select Low Interrupt Enable + 3 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + SPIM Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt + 0 + 1 + + + TXC + Transmit Complete Interrupt + 1 + 1 + + + RXC + Receive Complete Interrupt + 2 + 1 + + + SSL + Slave Select Low Interrupt Flag + 3 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + SPIM Status + 0x1A + 16 + 0x0000 + + + BUFOVF + Buffer Overflow + 2 + 1 + + + + + SYNCBUSY + SPIM Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + CTRLB + CTRLB Synchronization Busy + 2 + 1 + + + + + ADDR + SPIM Address + 0x24 + 32 + 0x00000000 + + + ADDR + Address Value + 0 + 8 + + + ADDRMASK + Address Mask + 16 + 8 + + + + + DATA + SPIM Data + 0x28 + 32 + 0x00000000 + + + DATA + Data Value + 0 + 9 + + + + + DBGCTRL + SPIM Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + USART_EXT + USART EXTERNAL CLOCK Mode + I2CM + SercomUsart_ext + 0x0 + + CTRLA + USART_EXT Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + IBON + Immediate Buffer Overflow Notification + 8 + 1 + + + SAMPR + Sample + 13 + 3 + + SAMPRSelect + + 16X_ARITHMETIC + 16x over-sampling using arithmetic baudrate generation + 0x0 + + + 16X_FRACTIONAL + 16x over-sampling using fractional baudrate generation + 0x1 + + + 8X_ARITHMETIC + 8x over-sampling using arithmetic baudrate generation + 0x2 + + + 8X_FRACTIONAL + 8x over-sampling using fractional baudrate generation + 0x3 + + + 3X_ARITHMETIC + 3x over-sampling using arithmetic baudrate generation + 0x4 + + + + + TXPO + Transmit Data Pinout + 16 + 2 + + TXPOSelect + + PAD0 + SERCOM PAD[0] is used for data transmission + 0x0 + + + PAD2 + SERCOM PAD[2] is used for data transmission + 0x1 + + + + + RXPO + Receive Data Pinout + 20 + 2 + + RXPOSelect + + PAD0 + SERCOM PAD[0] is used for data reception + 0x0 + + + PAD1 + SERCOM PAD[1] is used for data reception + 0x1 + + + PAD2 + SERCOM PAD[2] is used for data reception + 0x2 + + + PAD3 + SERCOM PAD[3] is used for data reception + 0x3 + + + + + SAMPA + Sample Adjustment + 22 + 2 + + + FORM + Frame Format + 24 + 4 + + FORMSelect + + USART_FRAME_NO_PARITY + USART frame + 0x0 + + + USART_FRAME_WITH_PARITY + USART frame with parity + 0x1 + + + USART_FRAME_LIN_MASTER_MODE + LIN Master - Break and sync generation + 0x2 + + + USART_FRAME_AUTO_BAUD_NO_PARITY + Auto-baud - break detection and auto-baud + 0x4 + + + USART_FRAME_AUTO_BAUD_WITH_PARITY + Auto-baud - break detection and auto-baud with parity + 0x5 + + + + + CMODE + Communication Mode + 28 + 1 + + CMODESelect + + ASYNC + Asynchronous Communication + 0x0 + + + SYNC + Synchronous Communication + 0x1 + + + + + CPOL + Clock Polarity + 29 + 1 + + CPOLSelect + + IDLE_LOW + TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge + 0x0 + + + IDLE_HIGH + TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge + 0x1 + + + + + DORD + Data Order + 30 + 1 + + DORDSelect + + MSB + MSB is transmitted first + 0x0 + + + LSB + LSB is transmitted first + 0x1 + + + + + + + CTRLB + USART_EXT Control B + 0x4 + 32 + 0x00000000 + + + CHSIZE + Character Size + 0 + 3 + + CHSIZESelect + + 8_BIT + 8 Bits + 0x0 + + + 9_BIT + 9 Bits + 0x1 + + + 5_BIT + 5 Bits + 0x5 + + + 6_BIT + 6 Bits + 0x6 + + + 7_BIT + 7 Bits + 0x7 + + + + + SBMODE + Stop Bit Mode + 6 + 1 + + SBMODESelect + + 1_BIT + One Stop Bit + 0x0 + + + 2_BIT + Two Stop Bits + 0x1 + + + + + COLDEN + Collision Detection Enable + 8 + 1 + + + SFDE + Start of Frame Detection Enable + 9 + 1 + + + ENC + Encoding Format + 10 + 1 + + + PMODE + Parity Mode + 13 + 1 + + PMODESelect + + EVEN + Even Parity + 0x0 + + + ODD + Odd Parity + 0x1 + + + + + TXEN + Transmitter Enable + 16 + 1 + + + RXEN + Receiver Enable + 17 + 1 + + + LINCMD + LIN Command + 24 + 2 + + + + + CTRLC + USART_EXT Control C + 0x8 + 32 + 0x00000000 + + + GTIME + RS485 Guard Time + 0 + 3 + + + BRKLEN + LIN Master Break Length + 8 + 2 + + + HDRDLY + LIN Master Header Delay + 10 + 2 + + + + + BAUD + USART_EXT Baud Rate + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 16 + + + + + BAUD_FRAC_MODE + USART_EXT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 13 + + + FP + Fractional Part + 13 + 3 + + + + + BAUD_FRACFP_MODE + USART_EXT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 13 + + + FP + Fractional Part + 13 + 3 + + + + + BAUD_USARTFP_MODE + USART_EXT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 16 + + + + + RXPL + USART_EXT Receive Pulse Length + 0xE + 8 + 0x00 + + + RXPL + Receive Pulse Length + 0 + 8 + + + + + INTENCLR + USART_EXT Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Disable + 0 + 1 + + + TXC + Transmit Complete Interrupt Disable + 1 + 1 + + + RXC + Receive Complete Interrupt Disable + 2 + 1 + + + RXS + Receive Start Interrupt Disable + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt Disable + 4 + 1 + + + RXBRK + Break Received Interrupt Disable + 5 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + USART_EXT Interrupt Enable Set + 0x16 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Enable + 0 + 1 + + + TXC + Transmit Complete Interrupt Enable + 1 + 1 + + + RXC + Receive Complete Interrupt Enable + 2 + 1 + + + RXS + Receive Start Interrupt Enable + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt Enable + 4 + 1 + + + RXBRK + Break Received Interrupt Enable + 5 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + USART_EXT Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt + 0 + 1 + + + TXC + Transmit Complete Interrupt + 1 + 1 + + + RXC + Receive Complete Interrupt + 2 + 1 + + + RXS + Receive Start Interrupt + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt + 4 + 1 + + + RXBRK + Break Received Interrupt + 5 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + USART_EXT Status + 0x1A + 16 + 0x0000 + + + PERR + Parity Error + 0 + 1 + + + FERR + Frame Error + 1 + 1 + + + BUFOVF + Buffer Overflow + 2 + 1 + + + CTS + Clear To Send + 3 + 1 + + + ISF + Inconsistent Sync Field + 4 + 1 + + + COLL + Collision Detected + 5 + 1 + + + TXE + Transmitter Empty + 6 + 1 + + + + + SYNCBUSY + USART_EXT Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + CTRLB + CTRLB Synchronization Busy + 2 + 1 + + + + + DATA + USART_EXT Data + 0x28 + 16 + 0x0000 + + + DATA + Data Value + 0 + 9 + + + + + DBGCTRL + USART_EXT Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + USART_INT + USART INTERNAL CLOCK Mode + I2CM + SercomUsart_int + 0x0 + + CTRLA + USART_INT Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + IBON + Immediate Buffer Overflow Notification + 8 + 1 + + + SAMPR + Sample + 13 + 3 + + SAMPRSelect + + 16X_ARITHMETIC + 16x over-sampling using arithmetic baudrate generation + 0x0 + + + 16X_FRACTIONAL + 16x over-sampling using fractional baudrate generation + 0x1 + + + 8X_ARITHMETIC + 8x over-sampling using arithmetic baudrate generation + 0x2 + + + 8X_FRACTIONAL + 8x over-sampling using fractional baudrate generation + 0x3 + + + 3X_ARITHMETIC + 3x over-sampling using arithmetic baudrate generation + 0x4 + + + + + TXPO + Transmit Data Pinout + 16 + 2 + + TXPOSelect + + PAD0 + SERCOM PAD[0] is used for data transmission + 0x0 + + + PAD2 + SERCOM PAD[2] is used for data transmission + 0x1 + + + + + RXPO + Receive Data Pinout + 20 + 2 + + RXPOSelect + + PAD0 + SERCOM PAD[0] is used for data reception + 0x0 + + + PAD1 + SERCOM PAD[1] is used for data reception + 0x1 + + + PAD2 + SERCOM PAD[2] is used for data reception + 0x2 + + + PAD3 + SERCOM PAD[3] is used for data reception + 0x3 + + + + + SAMPA + Sample Adjustment + 22 + 2 + + + FORM + Frame Format + 24 + 4 + + FORMSelect + + USART_FRAME_NO_PARITY + USART frame + 0x0 + + + USART_FRAME_WITH_PARITY + USART frame with parity + 0x1 + + + USART_FRAME_LIN_MASTER_MODE + LIN Master - Break and sync generation + 0x2 + + + USART_FRAME_AUTO_BAUD_NO_PARITY + Auto-baud - break detection and auto-baud + 0x4 + + + USART_FRAME_AUTO_BAUD_WITH_PARITY + Auto-baud - break detection and auto-baud with parity + 0x5 + + + + + CMODE + Communication Mode + 28 + 1 + + CMODESelect + + ASYNC + Asynchronous Communication + 0x0 + + + SYNC + Synchronous Communication + 0x1 + + + + + CPOL + Clock Polarity + 29 + 1 + + CPOLSelect + + IDLE_LOW + TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge + 0x0 + + + IDLE_HIGH + TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge + 0x1 + + + + + DORD + Data Order + 30 + 1 + + DORDSelect + + MSB + MSB is transmitted first + 0x0 + + + LSB + LSB is transmitted first + 0x1 + + + + + + + CTRLB + USART_INT Control B + 0x4 + 32 + 0x00000000 + + + CHSIZE + Character Size + 0 + 3 + + CHSIZESelect + + 8_BIT + 8 Bits + 0x0 + + + 9_BIT + 9 Bits + 0x1 + + + 5_BIT + 5 Bits + 0x5 + + + 6_BIT + 6 Bits + 0x6 + + + 7_BIT + 7 Bits + 0x7 + + + + + SBMODE + Stop Bit Mode + 6 + 1 + + SBMODESelect + + 1_BIT + One Stop Bit + 0x0 + + + 2_BIT + Two Stop Bits + 0x1 + + + + + COLDEN + Collision Detection Enable + 8 + 1 + + + SFDE + Start of Frame Detection Enable + 9 + 1 + + + ENC + Encoding Format + 10 + 1 + + + PMODE + Parity Mode + 13 + 1 + + PMODESelect + + EVEN + Even Parity + 0x0 + + + ODD + Odd Parity + 0x1 + + + + + TXEN + Transmitter Enable + 16 + 1 + + + RXEN + Receiver Enable + 17 + 1 + + + LINCMD + LIN Command + 24 + 2 + + + + + CTRLC + USART_INT Control C + 0x8 + 32 + 0x00000000 + + + GTIME + RS485 Guard Time + 0 + 3 + + + BRKLEN + LIN Master Break Length + 8 + 2 + + + HDRDLY + LIN Master Header Delay + 10 + 2 + + + + + BAUD + USART_INT Baud Rate + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 16 + + + + + BAUD_FRAC_MODE + USART_INT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 13 + + + FP + Fractional Part + 13 + 3 + + + + + BAUD_FRACFP_MODE + USART_INT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 13 + + + FP + Fractional Part + 13 + 3 + + + + + BAUD_USARTFP_MODE + USART_INT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 16 + + + + + RXPL + USART_INT Receive Pulse Length + 0xE + 8 + 0x00 + + + RXPL + Receive Pulse Length + 0 + 8 + + + + + INTENCLR + USART_INT Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Disable + 0 + 1 + + + TXC + Transmit Complete Interrupt Disable + 1 + 1 + + + RXC + Receive Complete Interrupt Disable + 2 + 1 + + + RXS + Receive Start Interrupt Disable + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt Disable + 4 + 1 + + + RXBRK + Break Received Interrupt Disable + 5 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + USART_INT Interrupt Enable Set + 0x16 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Enable + 0 + 1 + + + TXC + Transmit Complete Interrupt Enable + 1 + 1 + + + RXC + Receive Complete Interrupt Enable + 2 + 1 + + + RXS + Receive Start Interrupt Enable + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt Enable + 4 + 1 + + + RXBRK + Break Received Interrupt Enable + 5 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + USART_INT Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt + 0 + 1 + + + TXC + Transmit Complete Interrupt + 1 + 1 + + + RXC + Receive Complete Interrupt + 2 + 1 + + + RXS + Receive Start Interrupt + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt + 4 + 1 + + + RXBRK + Break Received Interrupt + 5 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + USART_INT Status + 0x1A + 16 + 0x0000 + + + PERR + Parity Error + 0 + 1 + + + FERR + Frame Error + 1 + 1 + + + BUFOVF + Buffer Overflow + 2 + 1 + + + CTS + Clear To Send + 3 + 1 + + + ISF + Inconsistent Sync Field + 4 + 1 + + + COLL + Collision Detected + 5 + 1 + + + TXE + Transmitter Empty + 6 + 1 + + + + + SYNCBUSY + USART_INT Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + CTRLB + CTRLB Synchronization Busy + 2 + 1 + + + + + DATA + USART_INT Data + 0x28 + 16 + 0x0000 + + + DATA + Data Value + 0 + 9 + + + + + DBGCTRL + USART_INT Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + + + SERCOM1 + 0x42000800 + + SERCOM1 + 10 + + + + SERCOM2 + 0x42000C00 + + SERCOM2 + 11 + + + + SERCOM3 + 0x42001000 + + SERCOM3 + 12 + + + + SUPC + U21172.1.1 + Supply Controller + SUPC + SUPC_ + 0x40001800 + + 0 + 0x20 + registers + + + + INTENCLR + Interrupt Enable Clear + 0x0 + 32 + 0x00000000 + + + BODVDDRDY + BODVDD Ready + 0 + 1 + + + BODVDDDET + BODVDD Detection + 1 + 1 + + + BVDDSRDY + BODVDD Synchronization Ready + 2 + 1 + + + BODCORERDY + BODCORE Ready + 3 + 1 + + + BODCOREDET + BODCORE Detection + 4 + 1 + + + BCORESRDY + BODCORE Synchronization Ready + 5 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x4 + 32 + 0x00000000 + + + BODVDDRDY + BODVDD Ready + 0 + 1 + + + BODVDDDET + BODVDD Detection + 1 + 1 + + + BVDDSRDY + BODVDD Synchronization Ready + 2 + 1 + + + BODCORERDY + BODCORE Ready + 3 + 1 + + + BODCOREDET + BODCORE Detection + 4 + 1 + + + BCORESRDY + BODCORE Synchronization Ready + 5 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x8 + 32 + 0x00000000 + + + BODVDDRDY + BODVDD Ready + 0 + 1 + + + BODVDDDET + BODVDD Detection + 1 + 1 + + + BVDDSRDY + BODVDD Synchronization Ready + 2 + 1 + + + BODCORERDY + BODCORE Ready + 3 + 1 + + + BODCOREDET + BODCORE Detection + 4 + 1 + + + BCORESRDY + BODCORE Synchronization Ready + 5 + 1 + + + + + STATUS + Power and Clocks Status + 0xC + 32 + read-only + 0x00000000 + + + BODVDDRDY + BODVDD Ready + 0 + 1 + + + BODVDDDET + BODVDD Detection + 1 + 1 + + + BVDDSRDY + BODVDD Synchronization Ready + 2 + 1 + + + BODCORERDY + BODCORE Ready + 3 + 1 + + + BODCOREDET + BODCORE Detection + 4 + 1 + + + BCORESRDY + BODCORE Synchronization Ready + 5 + 1 + + + + + BODVDD + BODVDD Control + 0x10 + 32 + 0x00000000 + + + ENABLE + Enable + 1 + 1 + + + HYST + Hysteresis Enable + 2 + 1 + + + ACTION + Action when Threshold Crossed + 3 + 2 + + ACTIONSelect + + NONE + No action + 0x0 + + + RESET + The BODVDD generates a reset + 0x1 + + + INT + The BODVDD generates an interrupt + 0x2 + + + + + STDBYCFG + Configuration in Standby mode + 5 + 1 + + + RUNSTDBY + Run during Standby + 6 + 1 + + + ACTCFG + Configuration in Active mode + 8 + 1 + + + PSEL + Prescaler Select + 12 + 4 + + PSELSelect + + DIV2 + Divide clock by 2 + 0x0 + + + DIV4 + Divide clock by 4 + 0x1 + + + DIV8 + Divide clock by 8 + 0x2 + + + DIV16 + Divide clock by 16 + 0x3 + + + DIV32 + Divide clock by 32 + 0x4 + + + DIV64 + Divide clock by 64 + 0x5 + + + DIV128 + Divide clock by 128 + 0x6 + + + DIV256 + Divide clock by 256 + 0x7 + + + DIV512 + Divide clock by 512 + 0x8 + + + DIV1024 + Divide clock by 1024 + 0x9 + + + DIV2048 + Divide clock by 2048 + 0xA + + + DIV4096 + Divide clock by 4096 + 0xB + + + DIV8192 + Divide clock by 8192 + 0xC + + + DIV16384 + Divide clock by 16384 + 0xD + + + DIV32768 + Divide clock by 32768 + 0xE + + + DIV65536 + Divide clock by 65536 + 0xF + + + + + LEVEL + Threshold Level for VDD + 16 + 6 + + + + + BODCORE + BODCORE Control + 0x14 + 32 + 0x00000000 + + + ENABLE + Enable + 1 + 1 + + + HYST + Hysteresis Enable + 2 + 1 + + + ACTION + Action when Threshold Crossed + 3 + 2 + + ACTIONSelect + + NONE + No action + 0x0 + + + RESET + The BODCORE generates a reset + 0x1 + + + INT + The BODCORE generates an interrupt + 0x2 + + + + + STDBYCFG + Configuration in Standby mode + 5 + 1 + + + RUNSTDBY + Run during Standby + 6 + 1 + + + ACTCFG + Configuration in Active mode + 8 + 1 + + + PSEL + Prescaler Select + 12 + 4 + + PSELSelect + + DIV2 + Divide clock by 2 + 0x0 + + + DIV4 + Divide clock by 4 + 0x1 + + + DIV8 + Divide clock by 8 + 0x2 + + + DIV16 + Divide clock by 16 + 0x3 + + + DIV32 + Divide clock by 32 + 0x4 + + + DIV64 + Divide clock by 64 + 0x5 + + + DIV128 + Divide clock by 128 + 0x6 + + + DIV256 + Divide clock by 256 + 0x7 + + + DIV512 + Divide clock by 512 + 0x8 + + + DIV1024 + Divide clock by 1024 + 0x9 + + + DIV2048 + Divide clock by 2048 + 0xA + + + DIV4096 + Divide clock by 4096 + 0xB + + + DIV8192 + Divide clock by 8192 + 0xC + + + DIV16384 + Divide clock by 16384 + 0xD + + + DIV32768 + Divide clock by 32768 + 0xE + + + DIV65536 + Divide clock by 65536 + 0xF + + + + + LEVEL + Threshold Level + 16 + 6 + + + + + VREG + VREG Control + 0x18 + 32 + 0x00000000 + + + ENABLE + Enable + 1 + 1 + + + RUNSTDBY + Run during Standby + 6 + 1 + + + + + VREF + VREF Control + 0x1C + 32 + 0x00000000 + + + TSEN + Temperature Sensor Output Enable + 1 + 1 + + + VREFOE + Voltage Reference Output Enable + 2 + 1 + + + RUNSTDBY + Run during Standby + 6 + 1 + + + ONDEMAND + On Demand Contrl + 7 + 1 + + + SEL + Voltage Reference Selection + 16 + 4 + + SELSelect + + 1V024 + 1.024V voltage reference typical value + 0x0 + + + 2V048 + 2.048V voltage reference typical value + 0x2 + + + 4V096 + 4.096V voltage reference typical value + 0x3 + + + + + + + + + TC0 + U22492.0.0 + Basic Timer Counter + TC + TC_ + 0x42003000 + + 0 + 0x38 + registers + + + TC0 + 20 + + + + COUNT8 + 8-bit Counter Mode + TcCount8 + 0x0 + + CTRLA + Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Timer Counter Mode + 2 + 2 + + MODESelect + + COUNT16 + Counter in 16-bit mode + 0 + + + COUNT8 + Counter in 8-bit mode + 1 + + + COUNT32 + Counter in 32-bit mode + 2 + + + + + PRESCSYNC + Prescaler and Counter Synchronization + 4 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset the counter on next generic clock + 0 + + + PRESC + Reload or reset the counter on next prescaler clock + 1 + + + RESYNC + Reload or reset the counter on next generic clock and reset the prescaler counter + 2 + + + + + RUNSTDBY + Run during Standby + 6 + 1 + + + ONDEMAND + Clock On Demand + 7 + 1 + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + Prescaler: GCLK_TC + 0 + + + DIV2 + Prescaler: GCLK_TC/2 + 1 + + + DIV4 + Prescaler: GCLK_TC/4 + 2 + + + DIV8 + Prescaler: GCLK_TC/8 + 3 + + + DIV16 + Prescaler: GCLK_TC/16 + 4 + + + DIV64 + Prescaler: GCLK_TC/64 + 5 + + + DIV256 + Prescaler: GCLK_TC/256 + 6 + + + DIV1024 + Prescaler: GCLK_TC/1024 + 7 + + + + + ALOCK + Auto Lock + 11 + 1 + + + CAPTEN0 + Capture Channel 0 Enable + 16 + 1 + + + CAPTEN1 + Capture Channel 1 Enable + 17 + 1 + + + COPEN0 + Capture On Pin 0 Enable + 20 + 1 + + + COPEN1 + Capture On Pin 1 Enable + 21 + 1 + + + + + CTRLBCLR + Control B Clear + 0x4 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot on Counter + 2 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + UPDATE + Force update of double-buffered register + 3 + + + READSYNC + Force a read synchronization of COUNT + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + CTRLBSET + Control B Set + 0x5 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot on Counter + 2 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + UPDATE + Force update of double-buffered register + 3 + + + READSYNC + Force a read synchronization of COUNT + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + EVCTRL + Event Control + 0x6 + 16 + 0x0000 + + + EVACT + Event Action + 0 + 3 + + EVACTSelect + + OFF + Event action disabled + 0 + + + RETRIGGER + Start, restart or retrigger TC on event + 1 + + + COUNT + Count on event + 2 + + + START + Start TC on event + 3 + + + STAMP + Time stamp capture + 4 + + + PPW + Period catured in CC0, pulse width in CC1 + 5 + + + PWP + Period catured in CC1, pulse width in CC0 + 6 + + + PW + Pulse width capture + 7 + + + + + TCINV + TC Event Input Polarity + 4 + 1 + + + TCEI + TC Event Enable + 5 + 1 + + + OVFEO + Event Output Enable + 8 + 1 + + + MCEO0 + MC Event Output Enable 0 + 12 + 1 + + + MCEO1 + MC Event Output Enable 1 + 13 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x8 + 8 + 0x00 + + + OVF + OVF Interrupt Disable + 0 + 1 + + + ERR + ERR Interrupt Disable + 1 + 1 + + + MC0 + MC Interrupt Disable 0 + 4 + 1 + + + MC1 + MC Interrupt Disable 1 + 5 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x9 + 8 + 0x00 + + + OVF + OVF Interrupt Enable + 0 + 1 + + + ERR + ERR Interrupt Enable + 1 + 1 + + + MC0 + MC Interrupt Enable 0 + 4 + 1 + + + MC1 + MC Interrupt Enable 1 + 5 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0xA + 8 + 0x00 + + + OVF + OVF Interrupt Flag + 0 + 1 + + + ERR + ERR Interrupt Flag + 1 + 1 + + + MC0 + MC Interrupt Flag 0 + 4 + 1 + + + MC1 + MC Interrupt Flag 1 + 5 + 1 + + + + + STATUS + Status + 0xB + 8 + 0x01 + + + STOP + Stop Status Flag + 0 + 1 + + + SLAVE + Slave Status Flag + 1 + 1 + + + PERBUFV + Synchronization Busy Status + 3 + 1 + + + CCBUFV0 + Compare channel buffer 0 valid + 4 + 1 + + + CCBUFV1 + Compare channel buffer 1 valid + 5 + 1 + + + + + WAVE + Waveform Generation Control + 0xC + 8 + 0x00 + + + WAVEGEN + Waveform Generation Mode + 0 + 2 + + WAVEGENSelect + + NFRQ + Normal frequency + 0 + + + MFRQ + Match frequency + 1 + + + NPWM + Normal PWM + 2 + + + MPWM + Match PWM + 3 + + + + + + + DRVCTRL + Control C + 0xD + 8 + 0x00 + + + INVEN0 + Output Waveform Invert Enable 0 + 0 + 1 + + + INVEN1 + Output Waveform Invert Enable 1 + 1 + 1 + + + + + DBGCTRL + Debug Control + 0xF + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + SYNCBUSY + Synchronization Status + 0x10 + 32 + read-only + 0x00000000 + + + SWRST + swrst + 0 + 1 + + + ENABLE + enable + 1 + 1 + + + CTRLB + CTRLB + 2 + 1 + + + STATUS + STATUS + 3 + 1 + + + COUNT + Counter + 4 + 1 + + + PER + Period + 5 + 1 + + + CC0 + Compare Channel 0 + 6 + 1 + + + CC1 + Compare Channel 1 + 7 + 1 + + + + + COUNT + COUNT8 Count + 0x14 + 8 + 0x00 + + + COUNT + Counter Value + 0 + 8 + + + + + PER + COUNT8 Period + 0x1B + 8 + 0xFF + + + PER + Period Value + 0 + 8 + + + + + 2 + 1 + CC[%s] + COUNT8 Compare and Capture + 0x1C + 8 + 0x00 + + + CC + Counter/Compare Value + 0 + 8 + + + + + PERBUF + COUNT8 Period Buffer + 0x2F + 8 + 0xFF + + + PERBUF + Period Buffer Value + 0 + 8 + + + + + 2 + 1 + CCBUF[%s] + COUNT8 Compare and Capture Buffer + 0x30 + 8 + 0x00 + + + CCBUF + Counter/Compare Buffer Value + 0 + 8 + + + + + + COUNT16 + 16-bit Counter Mode + COUNT8 + TcCount16 + 0x0 + + CTRLA + Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Timer Counter Mode + 2 + 2 + + MODESelect + + COUNT16 + Counter in 16-bit mode + 0 + + + COUNT8 + Counter in 8-bit mode + 1 + + + COUNT32 + Counter in 32-bit mode + 2 + + + + + PRESCSYNC + Prescaler and Counter Synchronization + 4 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset the counter on next generic clock + 0 + + + PRESC + Reload or reset the counter on next prescaler clock + 1 + + + RESYNC + Reload or reset the counter on next generic clock and reset the prescaler counter + 2 + + + + + RUNSTDBY + Run during Standby + 6 + 1 + + + ONDEMAND + Clock On Demand + 7 + 1 + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + Prescaler: GCLK_TC + 0 + + + DIV2 + Prescaler: GCLK_TC/2 + 1 + + + DIV4 + Prescaler: GCLK_TC/4 + 2 + + + DIV8 + Prescaler: GCLK_TC/8 + 3 + + + DIV16 + Prescaler: GCLK_TC/16 + 4 + + + DIV64 + Prescaler: GCLK_TC/64 + 5 + + + DIV256 + Prescaler: GCLK_TC/256 + 6 + + + DIV1024 + Prescaler: GCLK_TC/1024 + 7 + + + + + ALOCK + Auto Lock + 11 + 1 + + + CAPTEN0 + Capture Channel 0 Enable + 16 + 1 + + + CAPTEN1 + Capture Channel 1 Enable + 17 + 1 + + + COPEN0 + Capture On Pin 0 Enable + 20 + 1 + + + COPEN1 + Capture On Pin 1 Enable + 21 + 1 + + + + + CTRLBCLR + Control B Clear + 0x4 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot on Counter + 2 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + UPDATE + Force update of double-buffered register + 3 + + + READSYNC + Force a read synchronization of COUNT + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + CTRLBSET + Control B Set + 0x5 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot on Counter + 2 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + UPDATE + Force update of double-buffered register + 3 + + + READSYNC + Force a read synchronization of COUNT + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + EVCTRL + Event Control + 0x6 + 16 + 0x0000 + + + EVACT + Event Action + 0 + 3 + + EVACTSelect + + OFF + Event action disabled + 0 + + + RETRIGGER + Start, restart or retrigger TC on event + 1 + + + COUNT + Count on event + 2 + + + START + Start TC on event + 3 + + + STAMP + Time stamp capture + 4 + + + PPW + Period catured in CC0, pulse width in CC1 + 5 + + + PWP + Period catured in CC1, pulse width in CC0 + 6 + + + PW + Pulse width capture + 7 + + + + + TCINV + TC Event Input Polarity + 4 + 1 + + + TCEI + TC Event Enable + 5 + 1 + + + OVFEO + Event Output Enable + 8 + 1 + + + MCEO0 + MC Event Output Enable 0 + 12 + 1 + + + MCEO1 + MC Event Output Enable 1 + 13 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x8 + 8 + 0x00 + + + OVF + OVF Interrupt Disable + 0 + 1 + + + ERR + ERR Interrupt Disable + 1 + 1 + + + MC0 + MC Interrupt Disable 0 + 4 + 1 + + + MC1 + MC Interrupt Disable 1 + 5 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x9 + 8 + 0x00 + + + OVF + OVF Interrupt Enable + 0 + 1 + + + ERR + ERR Interrupt Enable + 1 + 1 + + + MC0 + MC Interrupt Enable 0 + 4 + 1 + + + MC1 + MC Interrupt Enable 1 + 5 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0xA + 8 + 0x00 + + + OVF + OVF Interrupt Flag + 0 + 1 + + + ERR + ERR Interrupt Flag + 1 + 1 + + + MC0 + MC Interrupt Flag 0 + 4 + 1 + + + MC1 + MC Interrupt Flag 1 + 5 + 1 + + + + + STATUS + Status + 0xB + 8 + 0x01 + + + STOP + Stop Status Flag + 0 + 1 + + + SLAVE + Slave Status Flag + 1 + 1 + + + PERBUFV + Synchronization Busy Status + 3 + 1 + + + CCBUFV0 + Compare channel buffer 0 valid + 4 + 1 + + + CCBUFV1 + Compare channel buffer 1 valid + 5 + 1 + + + + + WAVE + Waveform Generation Control + 0xC + 8 + 0x00 + + + WAVEGEN + Waveform Generation Mode + 0 + 2 + + WAVEGENSelect + + NFRQ + Normal frequency + 0 + + + MFRQ + Match frequency + 1 + + + NPWM + Normal PWM + 2 + + + MPWM + Match PWM + 3 + + + + + + + DRVCTRL + Control C + 0xD + 8 + 0x00 + + + INVEN0 + Output Waveform Invert Enable 0 + 0 + 1 + + + INVEN1 + Output Waveform Invert Enable 1 + 1 + 1 + + + + + DBGCTRL + Debug Control + 0xF + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + SYNCBUSY + Synchronization Status + 0x10 + 32 + read-only + 0x00000000 + + + SWRST + swrst + 0 + 1 + + + ENABLE + enable + 1 + 1 + + + CTRLB + CTRLB + 2 + 1 + + + STATUS + STATUS + 3 + 1 + + + COUNT + Counter + 4 + 1 + + + PER + Period + 5 + 1 + + + CC0 + Compare Channel 0 + 6 + 1 + + + CC1 + Compare Channel 1 + 7 + 1 + + + + + COUNT + COUNT16 Count + 0x14 + 16 + 0x0000 + + + COUNT + Counter Value + 0 + 16 + + + + + 2 + 2 + CC[%s] + COUNT16 Compare and Capture + 0x1C + 16 + 0x0000 + + + CC + Counter/Compare Value + 0 + 16 + + + + + 2 + 2 + CCBUF[%s] + COUNT16 Compare and Capture Buffer + 0x30 + 16 + 0x0000 + + + CCBUF + Counter/Compare Buffer Value + 0 + 16 + + + + + + COUNT32 + 32-bit Counter Mode + COUNT8 + TcCount32 + 0x0 + + CTRLA + Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Timer Counter Mode + 2 + 2 + + MODESelect + + COUNT16 + Counter in 16-bit mode + 0 + + + COUNT8 + Counter in 8-bit mode + 1 + + + COUNT32 + Counter in 32-bit mode + 2 + + + + + PRESCSYNC + Prescaler and Counter Synchronization + 4 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset the counter on next generic clock + 0 + + + PRESC + Reload or reset the counter on next prescaler clock + 1 + + + RESYNC + Reload or reset the counter on next generic clock and reset the prescaler counter + 2 + + + + + RUNSTDBY + Run during Standby + 6 + 1 + + + ONDEMAND + Clock On Demand + 7 + 1 + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + Prescaler: GCLK_TC + 0 + + + DIV2 + Prescaler: GCLK_TC/2 + 1 + + + DIV4 + Prescaler: GCLK_TC/4 + 2 + + + DIV8 + Prescaler: GCLK_TC/8 + 3 + + + DIV16 + Prescaler: GCLK_TC/16 + 4 + + + DIV64 + Prescaler: GCLK_TC/64 + 5 + + + DIV256 + Prescaler: GCLK_TC/256 + 6 + + + DIV1024 + Prescaler: GCLK_TC/1024 + 7 + + + + + ALOCK + Auto Lock + 11 + 1 + + + CAPTEN0 + Capture Channel 0 Enable + 16 + 1 + + + CAPTEN1 + Capture Channel 1 Enable + 17 + 1 + + + COPEN0 + Capture On Pin 0 Enable + 20 + 1 + + + COPEN1 + Capture On Pin 1 Enable + 21 + 1 + + + + + CTRLBCLR + Control B Clear + 0x4 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot on Counter + 2 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + UPDATE + Force update of double-buffered register + 3 + + + READSYNC + Force a read synchronization of COUNT + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + CTRLBSET + Control B Set + 0x5 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot on Counter + 2 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + UPDATE + Force update of double-buffered register + 3 + + + READSYNC + Force a read synchronization of COUNT + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + EVCTRL + Event Control + 0x6 + 16 + 0x0000 + + + EVACT + Event Action + 0 + 3 + + EVACTSelect + + OFF + Event action disabled + 0 + + + RETRIGGER + Start, restart or retrigger TC on event + 1 + + + COUNT + Count on event + 2 + + + START + Start TC on event + 3 + + + STAMP + Time stamp capture + 4 + + + PPW + Period catured in CC0, pulse width in CC1 + 5 + + + PWP + Period catured in CC1, pulse width in CC0 + 6 + + + PW + Pulse width capture + 7 + + + + + TCINV + TC Event Input Polarity + 4 + 1 + + + TCEI + TC Event Enable + 5 + 1 + + + OVFEO + Event Output Enable + 8 + 1 + + + MCEO0 + MC Event Output Enable 0 + 12 + 1 + + + MCEO1 + MC Event Output Enable 1 + 13 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x8 + 8 + 0x00 + + + OVF + OVF Interrupt Disable + 0 + 1 + + + ERR + ERR Interrupt Disable + 1 + 1 + + + MC0 + MC Interrupt Disable 0 + 4 + 1 + + + MC1 + MC Interrupt Disable 1 + 5 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x9 + 8 + 0x00 + + + OVF + OVF Interrupt Enable + 0 + 1 + + + ERR + ERR Interrupt Enable + 1 + 1 + + + MC0 + MC Interrupt Enable 0 + 4 + 1 + + + MC1 + MC Interrupt Enable 1 + 5 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0xA + 8 + 0x00 + + + OVF + OVF Interrupt Flag + 0 + 1 + + + ERR + ERR Interrupt Flag + 1 + 1 + + + MC0 + MC Interrupt Flag 0 + 4 + 1 + + + MC1 + MC Interrupt Flag 1 + 5 + 1 + + + + + STATUS + Status + 0xB + 8 + 0x01 + + + STOP + Stop Status Flag + 0 + 1 + + + SLAVE + Slave Status Flag + 1 + 1 + + + PERBUFV + Synchronization Busy Status + 3 + 1 + + + CCBUFV0 + Compare channel buffer 0 valid + 4 + 1 + + + CCBUFV1 + Compare channel buffer 1 valid + 5 + 1 + + + + + WAVE + Waveform Generation Control + 0xC + 8 + 0x00 + + + WAVEGEN + Waveform Generation Mode + 0 + 2 + + WAVEGENSelect + + NFRQ + Normal frequency + 0 + + + MFRQ + Match frequency + 1 + + + NPWM + Normal PWM + 2 + + + MPWM + Match PWM + 3 + + + + + + + DRVCTRL + Control C + 0xD + 8 + 0x00 + + + INVEN0 + Output Waveform Invert Enable 0 + 0 + 1 + + + INVEN1 + Output Waveform Invert Enable 1 + 1 + 1 + + + + + DBGCTRL + Debug Control + 0xF + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + SYNCBUSY + Synchronization Status + 0x10 + 32 + read-only + 0x00000000 + + + SWRST + swrst + 0 + 1 + + + ENABLE + enable + 1 + 1 + + + CTRLB + CTRLB + 2 + 1 + + + STATUS + STATUS + 3 + 1 + + + COUNT + Counter + 4 + 1 + + + PER + Period + 5 + 1 + + + CC0 + Compare Channel 0 + 6 + 1 + + + CC1 + Compare Channel 1 + 7 + 1 + + + + + COUNT + COUNT32 Count + 0x14 + 32 + 0x00000000 + + + COUNT + Counter Value + 0 + 32 + + + + + 2 + 4 + CC[%s] + COUNT32 Compare and Capture + 0x1C + 32 + 0x00000000 + + + CC + Counter/Compare Value + 0 + 32 + + + + + 2 + 4 + CCBUF[%s] + COUNT32 Compare and Capture Buffer + 0x30 + 32 + 0x00000000 + + + CCBUF + Counter/Compare Buffer Value + 0 + 32 + + + + + + + + TC1 + 0x42003400 + + TC1 + 21 + + + + TC2 + 0x42003800 + + TC2 + 22 + + + + TC3 + 0x42003C00 + + TC3 + 23 + + + + TC4 + 0x42004000 + + TC4 + 24 + + + + TCC0 + U22133.0.0 + Timer Counter Control + TCC + TCC_ + 0x42002400 + + 0 + 0x80 + registers + + + TCC0 + 17 + + + + CTRLA + Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + RESOLUTION + Enhanced Resolution + 5 + 2 + + RESOLUTIONSelect + + NONE + Dithering is disabled + 0 + + + DITH4 + Dithering is done every 16 PWM frames + 1 + + + DITH5 + Dithering is done every 32 PWM frames + 2 + + + DITH6 + Dithering is done every 64 PWM frames + 3 + + + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + No division + 0 + + + DIV2 + Divide by 2 + 1 + + + DIV4 + Divide by 4 + 2 + + + DIV8 + Divide by 8 + 3 + + + DIV16 + Divide by 16 + 4 + + + DIV64 + Divide by 64 + 5 + + + DIV256 + Divide by 256 + 6 + + + DIV1024 + Divide by 1024 + 7 + + + + + RUNSTDBY + Run in Standby + 11 + 1 + + + PRESCSYNC + Prescaler and Counter Synchronization Selection + 12 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset counter on next GCLK + 0 + + + PRESC + Reload or reset counter on next prescaler clock + 1 + + + RESYNC + Reload or reset counter on next GCLK and reset prescaler counter + 2 + + + + + ALOCK + Auto Lock + 14 + 1 + + + MSYNC + Master Synchronization (only for TCC Slave Instance) + 15 + 1 + + + DMAOS + DMA One-shot Trigger Mode + 23 + 1 + + + CPTEN0 + Capture Channel 0 Enable + 24 + 1 + + + CPTEN1 + Capture Channel 1 Enable + 25 + 1 + + + CPTEN2 + Capture Channel 2 Enable + 26 + 1 + + + CPTEN3 + Capture Channel 3 Enable + 27 + 1 + + + + + CTRLBCLR + Control B Clear + 0x4 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + IDXCMD + Ramp Index Command + 3 + 2 + + IDXCMDSelect + + DISABLE + Command disabled: Index toggles between cycles A and B + 0 + + + SET + Set index: cycle B will be forced in the next cycle + 1 + + + CLEAR + Clear index: cycle A will be forced in the next cycle + 2 + + + HOLD + Hold index: the next cycle will be the same as the current cycle + 3 + + + + + CMD + TCC Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Clear start, restart or retrigger + 1 + + + STOP + Force stop + 2 + + + UPDATE + Force update or double buffered registers + 3 + + + READSYNC + Force COUNT read synchronization + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + CTRLBSET + Control B Set + 0x5 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + IDXCMD + Ramp Index Command + 3 + 2 + + IDXCMDSelect + + DISABLE + Command disabled: Index toggles between cycles A and B + 0 + + + SET + Set index: cycle B will be forced in the next cycle + 1 + + + CLEAR + Clear index: cycle A will be forced in the next cycle + 2 + + + HOLD + Hold index: the next cycle will be the same as the current cycle + 3 + + + + + CMD + TCC Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Clear start, restart or retrigger + 1 + + + STOP + Force stop + 2 + + + UPDATE + Force update or double buffered registers + 3 + + + READSYNC + Force COUNT read synchronization + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + SYNCBUSY + Synchronization Busy + 0x8 + 32 + read-only + 0x00000000 + + + SWRST + Swrst Busy + 0 + 1 + + + ENABLE + Enable Busy + 1 + 1 + + + CTRLB + Ctrlb Busy + 2 + 1 + + + STATUS + Status Busy + 3 + 1 + + + COUNT + Count Busy + 4 + 1 + + + PATT + Pattern Busy + 5 + 1 + + + WAVE + Wave Busy + 6 + 1 + + + PER + Period Busy + 7 + 1 + + + CC0 + Compare Channel 0 Busy + 8 + 1 + + + CC1 + Compare Channel 1 Busy + 9 + 1 + + + CC2 + Compare Channel 2 Busy + 10 + 1 + + + CC3 + Compare Channel 3 Busy + 11 + 1 + + + + + FCTRLA + Recoverable Fault A Configuration + 0xC + 32 + 0x00000000 + + + SRC + Fault A Source + 0 + 2 + + SRCSelect + + DISABLE + Fault input disabled + 0 + + + ENABLE + MCEx (x=0,1) event input + 1 + + + INVERT + Inverted MCEx (x=0,1) event input + 2 + + + ALTFAULT + Alternate fault (A or B) state at the end of the previous period + 3 + + + + + KEEP + Fault A Keeper + 3 + 1 + + + QUAL + Fault A Qualification + 4 + 1 + + + BLANK + Fault A Blanking Mode + 5 + 2 + + BLANKSelect + + START + Blanking applied from start of the ramp + 0 + + + RISE + Blanking applied from rising edge of the output waveform + 1 + + + FALL + Blanking applied from falling edge of the output waveform + 2 + + + BOTH + Blanking applied from each toggle of the output waveform + 3 + + + + + RESTART + Fault A Restart + 7 + 1 + + + HALT + Fault A Halt Mode + 8 + 2 + + HALTSelect + + DISABLE + Halt action disabled + 0 + + + HW + Hardware halt action + 1 + + + SW + Software halt action + 2 + + + NR + Non-recoverable fault + 3 + + + + + CHSEL + Fault A Capture Channel + 10 + 2 + + CHSELSelect + + CC0 + Capture value stored in channel 0 + 0 + + + CC1 + Capture value stored in channel 1 + 1 + + + CC2 + Capture value stored in channel 2 + 2 + + + CC3 + Capture value stored in channel 3 + 3 + + + + + CAPTURE + Fault A Capture Action + 12 + 3 + + CAPTURESelect + + DISABLE + No capture + 0 + + + CAPT + Capture on fault + 1 + + + CAPTMIN + Minimum capture + 2 + + + CAPTMAX + Maximum capture + 3 + + + LOCMIN + Minimum local detection + 4 + + + LOCMAX + Maximum local detection + 5 + + + DERIV0 + Minimum and maximum local detection + 6 + + + CAPTMARK + Capture with ramp index as MSB value + 7 + + + + + BLANKPRESC + Fault A Blanking Prescaler + 15 + 1 + + + BLANKVAL + Fault A Blanking Time + 16 + 8 + + + FILTERVAL + Fault A Filter Value + 24 + 4 + + + + + FCTRLB + Recoverable Fault B Configuration + 0x10 + 32 + 0x00000000 + + + SRC + Fault B Source + 0 + 2 + + SRCSelect + + DISABLE + Fault input disabled + 0 + + + ENABLE + MCEx (x=0,1) event input + 1 + + + INVERT + Inverted MCEx (x=0,1) event input + 2 + + + ALTFAULT + Alternate fault (A or B) state at the end of the previous period + 3 + + + + + KEEP + Fault B Keeper + 3 + 1 + + + QUAL + Fault B Qualification + 4 + 1 + + + BLANK + Fault B Blanking Mode + 5 + 2 + + BLANKSelect + + START + Blanking applied from start of the ramp + 0 + + + RISE + Blanking applied from rising edge of the output waveform + 1 + + + FALL + Blanking applied from falling edge of the output waveform + 2 + + + BOTH + Blanking applied from each toggle of the output waveform + 3 + + + + + RESTART + Fault B Restart + 7 + 1 + + + HALT + Fault B Halt Mode + 8 + 2 + + HALTSelect + + DISABLE + Halt action disabled + 0 + + + HW + Hardware halt action + 1 + + + SW + Software halt action + 2 + + + NR + Non-recoverable fault + 3 + + + + + CHSEL + Fault B Capture Channel + 10 + 2 + + CHSELSelect + + CC0 + Capture value stored in channel 0 + 0 + + + CC1 + Capture value stored in channel 1 + 1 + + + CC2 + Capture value stored in channel 2 + 2 + + + CC3 + Capture value stored in channel 3 + 3 + + + + + CAPTURE + Fault B Capture Action + 12 + 3 + + CAPTURESelect + + DISABLE + No capture + 0 + + + CAPT + Capture on fault + 1 + + + CAPTMIN + Minimum capture + 2 + + + CAPTMAX + Maximum capture + 3 + + + LOCMIN + Minimum local detection + 4 + + + LOCMAX + Maximum local detection + 5 + + + DERIV0 + Minimum and maximum local detection + 6 + + + CAPTMARK + Capture with ramp index as MSB value + 7 + + + + + BLANKPRESC + Fault B Blanking Prescaler + 15 + 1 + + + BLANKVAL + Fault B Blanking Time + 16 + 8 + + + FILTERVAL + Fault B Filter Value + 24 + 4 + + + + + WEXCTRL + Waveform Extension Configuration + 0x14 + 32 + 0x00000000 + + + OTMX + Output Matrix + 0 + 2 + + + DTIEN0 + Dead-time Insertion Generator 0 Enable + 8 + 1 + + + DTIEN1 + Dead-time Insertion Generator 1 Enable + 9 + 1 + + + DTIEN2 + Dead-time Insertion Generator 2 Enable + 10 + 1 + + + DTIEN3 + Dead-time Insertion Generator 3 Enable + 11 + 1 + + + DTLS + Dead-time Low Side Outputs Value + 16 + 8 + + + DTHS + Dead-time High Side Outputs Value + 24 + 8 + + + + + DRVCTRL + Driver Control + 0x18 + 32 + 0x00000000 + + + NRE0 + Non-Recoverable State 0 Output Enable + 0 + 1 + + + NRE1 + Non-Recoverable State 1 Output Enable + 1 + 1 + + + NRE2 + Non-Recoverable State 2 Output Enable + 2 + 1 + + + NRE3 + Non-Recoverable State 3 Output Enable + 3 + 1 + + + NRE4 + Non-Recoverable State 4 Output Enable + 4 + 1 + + + NRE5 + Non-Recoverable State 5 Output Enable + 5 + 1 + + + NRE6 + Non-Recoverable State 6 Output Enable + 6 + 1 + + + NRE7 + Non-Recoverable State 7 Output Enable + 7 + 1 + + + NRV0 + Non-Recoverable State 0 Output Value + 8 + 1 + + + NRV1 + Non-Recoverable State 1 Output Value + 9 + 1 + + + NRV2 + Non-Recoverable State 2 Output Value + 10 + 1 + + + NRV3 + Non-Recoverable State 3 Output Value + 11 + 1 + + + NRV4 + Non-Recoverable State 4 Output Value + 12 + 1 + + + NRV5 + Non-Recoverable State 5 Output Value + 13 + 1 + + + NRV6 + Non-Recoverable State 6 Output Value + 14 + 1 + + + NRV7 + Non-Recoverable State 7 Output Value + 15 + 1 + + + INVEN0 + Output Waveform 0 Inversion + 16 + 1 + + + INVEN1 + Output Waveform 1 Inversion + 17 + 1 + + + INVEN2 + Output Waveform 2 Inversion + 18 + 1 + + + INVEN3 + Output Waveform 3 Inversion + 19 + 1 + + + INVEN4 + Output Waveform 4 Inversion + 20 + 1 + + + INVEN5 + Output Waveform 5 Inversion + 21 + 1 + + + INVEN6 + Output Waveform 6 Inversion + 22 + 1 + + + INVEN7 + Output Waveform 7 Inversion + 23 + 1 + + + FILTERVAL0 + Non-Recoverable Fault Input 0 Filter Value + 24 + 4 + + + FILTERVAL1 + Non-Recoverable Fault Input 1 Filter Value + 28 + 4 + + + + + DBGCTRL + Debug Control + 0x1E + 8 + 0x00 + + + DBGRUN + Debug Running Mode + 0 + 1 + + + FDDBD + Fault Detection on Debug Break Detection + 2 + 1 + + + + + EVCTRL + Event Control + 0x20 + 32 + 0x00000000 + + + EVACT0 + Timer/counter Input Event0 Action + 0 + 3 + + EVACT0Select + + OFF + Event action disabled + 0 + + + RETRIGGER + Start, restart or re-trigger counter on event + 1 + + + COUNTEV + Count on event + 2 + + + START + Start counter on event + 3 + + + INC + Increment counter on event + 4 + + + COUNT + Count on active state of asynchronous event + 5 + + + STAMP + Stamp capture + 6 + + + FAULT + Non-recoverable fault + 7 + + + + + EVACT1 + Timer/counter Input Event1 Action + 3 + 3 + + EVACT1Select + + OFF + Event action disabled + 0 + + + RETRIGGER + Re-trigger counter on event + 1 + + + DIR + Direction control + 2 + + + STOP + Stop counter on event + 3 + + + DEC + Decrement counter on event + 4 + + + PPW + Period capture value in CC0 register, pulse width capture value in CC1 register + 5 + + + PWP + Period capture value in CC1 register, pulse width capture value in CC0 register + 6 + + + FAULT + Non-recoverable fault + 7 + + + + + CNTSEL + Timer/counter Output Event Mode + 6 + 2 + + CNTSELSelect + + START + An interrupt/event is generated when a new counter cycle starts + 0 + + + END + An interrupt/event is generated when a counter cycle ends + 1 + + + BETWEEN + An interrupt/event is generated when a counter cycle ends, except for the first and last cycles + 2 + + + BOUNDARY + An interrupt/event is generated when a new counter cycle starts or a counter cycle ends + 3 + + + + + OVFEO + Overflow/Underflow Output Event Enable + 8 + 1 + + + TRGEO + Retrigger Output Event Enable + 9 + 1 + + + CNTEO + Timer/counter Output Event Enable + 10 + 1 + + + TCINV0 + Inverted Event 0 Input Enable + 12 + 1 + + + TCINV1 + Inverted Event 1 Input Enable + 13 + 1 + + + TCEI0 + Timer/counter Event 0 Input Enable + 14 + 1 + + + TCEI1 + Timer/counter Event 1 Input Enable + 15 + 1 + + + MCEI0 + Match or Capture Channel 0 Event Input Enable + 16 + 1 + + + MCEI1 + Match or Capture Channel 1 Event Input Enable + 17 + 1 + + + MCEI2 + Match or Capture Channel 2 Event Input Enable + 18 + 1 + + + MCEI3 + Match or Capture Channel 3 Event Input Enable + 19 + 1 + + + MCEO0 + Match or Capture Channel 0 Event Output Enable + 24 + 1 + + + MCEO1 + Match or Capture Channel 1 Event Output Enable + 25 + 1 + + + MCEO2 + Match or Capture Channel 2 Event Output Enable + 26 + 1 + + + MCEO3 + Match or Capture Channel 3 Event Output Enable + 27 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x24 + 32 + 0x00000000 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + TRG + Retrigger Interrupt Enable + 1 + 1 + + + CNT + Counter Interrupt Enable + 2 + 1 + + + ERR + Error Interrupt Enable + 3 + 1 + + + UFS + Non-Recoverable Update Fault Interrupt Enable + 10 + 1 + + + DFS + Non-Recoverable Debug Fault Interrupt Enable + 11 + 1 + + + FAULTA + Recoverable Fault A Interrupt Enable + 12 + 1 + + + FAULTB + Recoverable Fault B Interrupt Enable + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 Interrupt Enable + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 Interrupt Enable + 15 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 16 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 17 + 1 + + + MC2 + Match or Capture Channel 2 Interrupt Enable + 18 + 1 + + + MC3 + Match or Capture Channel 3 Interrupt Enable + 19 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x28 + 32 + 0x00000000 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + TRG + Retrigger Interrupt Enable + 1 + 1 + + + CNT + Counter Interrupt Enable + 2 + 1 + + + ERR + Error Interrupt Enable + 3 + 1 + + + UFS + Non-Recoverable Update Fault Interrupt Enable + 10 + 1 + + + DFS + Non-Recoverable Debug Fault Interrupt Enable + 11 + 1 + + + FAULTA + Recoverable Fault A Interrupt Enable + 12 + 1 + + + FAULTB + Recoverable Fault B Interrupt Enable + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 Interrupt Enable + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 Interrupt Enable + 15 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 16 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 17 + 1 + + + MC2 + Match or Capture Channel 2 Interrupt Enable + 18 + 1 + + + MC3 + Match or Capture Channel 3 Interrupt Enable + 19 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x2C + 32 + 0x00000000 + + + OVF + Overflow + 0 + 1 + + + TRG + Retrigger + 1 + 1 + + + CNT + Counter + 2 + 1 + + + ERR + Error + 3 + 1 + + + UFS + Non-Recoverable Update Fault + 10 + 1 + + + DFS + Non-Recoverable Debug Fault + 11 + 1 + + + FAULTA + Recoverable Fault A + 12 + 1 + + + FAULTB + Recoverable Fault B + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 + 15 + 1 + + + MC0 + Match or Capture 0 + 16 + 1 + + + MC1 + Match or Capture 1 + 17 + 1 + + + MC2 + Match or Capture 2 + 18 + 1 + + + MC3 + Match or Capture 3 + 19 + 1 + + + + + STATUS + Status + 0x30 + 32 + 0x00000001 + + + STOP + Stop + 0 + 1 + + + IDX + Ramp + 1 + 1 + + + UFS + Non-recoverable Update Fault State + 2 + 1 + + + DFS + Non-Recoverable Debug Fault State + 3 + 1 + + + SLAVE + Slave + 4 + 1 + + + PATTBUFV + Pattern Buffer Valid + 5 + 1 + + + PERBUFV + Period Buffer Valid + 7 + 1 + + + FAULTAIN + Recoverable Fault A Input + 8 + 1 + + + FAULTBIN + Recoverable Fault B Input + 9 + 1 + + + FAULT0IN + Non-Recoverable Fault0 Input + 10 + 1 + + + FAULT1IN + Non-Recoverable Fault1 Input + 11 + 1 + + + FAULTA + Recoverable Fault A State + 12 + 1 + + + FAULTB + Recoverable Fault B State + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 State + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 State + 15 + 1 + + + CCBUFV0 + Compare Channel 0 Buffer Valid + 16 + 1 + + + CCBUFV1 + Compare Channel 1 Buffer Valid + 17 + 1 + + + CCBUFV2 + Compare Channel 2 Buffer Valid + 18 + 1 + + + CCBUFV3 + Compare Channel 3 Buffer Valid + 19 + 1 + + + CMP0 + Compare Channel 0 Value + 24 + 1 + + + CMP1 + Compare Channel 1 Value + 25 + 1 + + + CMP2 + Compare Channel 2 Value + 26 + 1 + + + CMP3 + Compare Channel 3 Value + 27 + 1 + + + + + COUNT + Count + 0x34 + 32 + 0x00000000 + + + COUNT + Counter Value + 0 + 24 + + + + + COUNT_DITH4_MODE + Count + COUNT + 0x34 + 32 + 0x00000000 + + + COUNT + Counter Value + 4 + 20 + + + + + COUNT_DITH5_MODE + Count + COUNT + 0x34 + 32 + 0x00000000 + + + COUNT + Counter Value + 5 + 19 + + + + + COUNT_DITH6_MODE + Count + COUNT + 0x34 + 32 + 0x00000000 + + + COUNT + Counter Value + 6 + 18 + + + + + PATT + Pattern + 0x38 + 16 + 0x0000 + + + PGE0 + Pattern Generator 0 Output Enable + 0 + 1 + + + PGE1 + Pattern Generator 1 Output Enable + 1 + 1 + + + PGE2 + Pattern Generator 2 Output Enable + 2 + 1 + + + PGE3 + Pattern Generator 3 Output Enable + 3 + 1 + + + PGE4 + Pattern Generator 4 Output Enable + 4 + 1 + + + PGE5 + Pattern Generator 5 Output Enable + 5 + 1 + + + PGE6 + Pattern Generator 6 Output Enable + 6 + 1 + + + PGE7 + Pattern Generator 7 Output Enable + 7 + 1 + + + PGV0 + Pattern Generator 0 Output Value + 8 + 1 + + + PGV1 + Pattern Generator 1 Output Value + 9 + 1 + + + PGV2 + Pattern Generator 2 Output Value + 10 + 1 + + + PGV3 + Pattern Generator 3 Output Value + 11 + 1 + + + PGV4 + Pattern Generator 4 Output Value + 12 + 1 + + + PGV5 + Pattern Generator 5 Output Value + 13 + 1 + + + PGV6 + Pattern Generator 6 Output Value + 14 + 1 + + + PGV7 + Pattern Generator 7 Output Value + 15 + 1 + + + + + WAVE + Waveform Control + 0x3C + 32 + 0x00000000 + + + WAVEGEN + Waveform Generation + 0 + 3 + + WAVEGENSelect + + NFRQ + Normal frequency + 0 + + + MFRQ + Match frequency + 1 + + + NPWM + Normal PWM + 2 + + + DSCRITICAL + Dual-slope critical + 4 + + + DSBOTTOM + Dual-slope with interrupt/event condition when COUNT reaches ZERO + 5 + + + DSBOTH + Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP + 6 + + + DSTOP + Dual-slope with interrupt/event condition when COUNT reaches TOP + 7 + + + + + RAMP + Ramp Mode + 4 + 2 + + RAMPSelect + + RAMP1 + RAMP1 operation + 0 + + + RAMP2A + Alternative RAMP2 operation + 1 + + + RAMP2 + RAMP2 operation + 2 + + + RAMP2C + Critical RAMP2 operation + 3 + + + + + CIPEREN + Circular period Enable + 7 + 1 + + + CICCEN0 + Circular Channel 0 Enable + 8 + 1 + + + CICCEN1 + Circular Channel 1 Enable + 9 + 1 + + + CICCEN2 + Circular Channel 2 Enable + 10 + 1 + + + CICCEN3 + Circular Channel 3 Enable + 11 + 1 + + + POL0 + Channel 0 Polarity + 16 + 1 + + + POL1 + Channel 1 Polarity + 17 + 1 + + + POL2 + Channel 2 Polarity + 18 + 1 + + + POL3 + Channel 3 Polarity + 19 + 1 + + + SWAP0 + Swap DTI Output Pair 0 + 24 + 1 + + + SWAP1 + Swap DTI Output Pair 1 + 25 + 1 + + + SWAP2 + Swap DTI Output Pair 2 + 26 + 1 + + + SWAP3 + Swap DTI Output Pair 3 + 27 + 1 + + + + + PER + Period + 0x40 + 32 + 0xFFFFFFFF + + + PER + Period Value + 0 + 24 + + + + + PER_DITH4_MODE + Period + PER + 0x40 + 32 + 0xFFFFFFFF + + + DITHER + Dithering Cycle Number + 0 + 4 + + + PER + Period Value + 4 + 20 + + + + + PER_DITH5_MODE + Period + PER + 0x40 + 32 + 0xFFFFFFFF + + + DITHER + Dithering Cycle Number + 0 + 5 + + + PER + Period Value + 5 + 19 + + + + + PER_DITH6_MODE + Period + PER + 0x40 + 32 + 0xFFFFFFFF + + + DITHER + Dithering Cycle Number + 0 + 6 + + + PER + Period Value + 6 + 18 + + + + + 4 + 4 + CC[%s] + Compare and Capture + 0x44 + 32 + 0x00000000 + + + CC + Channel Compare/Capture Value + 0 + 24 + + + + + 4 + 4 + CC_DITH4_MODE[%s] + Compare and Capture + CC[%s] + 0x44 + 32 + 0x00000000 + + + DITHER + Dithering Cycle Number + 0 + 4 + + + CC + Channel Compare/Capture Value + 4 + 20 + + + + + 4 + 4 + CC_DITH5_MODE[%s] + Compare and Capture + CC[%s] + 0x44 + 32 + 0x00000000 + + + DITHER + Dithering Cycle Number + 0 + 5 + + + CC + Channel Compare/Capture Value + 5 + 19 + + + + + 4 + 4 + CC_DITH6_MODE[%s] + Compare and Capture + CC[%s] + 0x44 + 32 + 0x00000000 + + + DITHER + Dithering Cycle Number + 0 + 6 + + + CC + Channel Compare/Capture Value + 6 + 18 + + + + + PATTBUF + Pattern Buffer + 0x64 + 16 + 0x0000 + + + PGEB0 + Pattern Generator 0 Output Enable Buffer + 0 + 1 + + + PGEB1 + Pattern Generator 1 Output Enable Buffer + 1 + 1 + + + PGEB2 + Pattern Generator 2 Output Enable Buffer + 2 + 1 + + + PGEB3 + Pattern Generator 3 Output Enable Buffer + 3 + 1 + + + PGEB4 + Pattern Generator 4 Output Enable Buffer + 4 + 1 + + + PGEB5 + Pattern Generator 5 Output Enable Buffer + 5 + 1 + + + PGEB6 + Pattern Generator 6 Output Enable Buffer + 6 + 1 + + + PGEB7 + Pattern Generator 7 Output Enable Buffer + 7 + 1 + + + PGVB0 + Pattern Generator 0 Output Enable + 8 + 1 + + + PGVB1 + Pattern Generator 1 Output Enable + 9 + 1 + + + PGVB2 + Pattern Generator 2 Output Enable + 10 + 1 + + + PGVB3 + Pattern Generator 3 Output Enable + 11 + 1 + + + PGVB4 + Pattern Generator 4 Output Enable + 12 + 1 + + + PGVB5 + Pattern Generator 5 Output Enable + 13 + 1 + + + PGVB6 + Pattern Generator 6 Output Enable + 14 + 1 + + + PGVB7 + Pattern Generator 7 Output Enable + 15 + 1 + + + + + PERBUF + Period Buffer + 0x6C + 32 + 0xFFFFFFFF + + + PERBUF + Period Buffer Value + 0 + 24 + + + + + PERBUF_DITH4_MODE + Period Buffer + PERBUF + 0x6C + 32 + 0xFFFFFFFF + + + DITHERBUF + Dithering Buffer Cycle Number + 0 + 4 + + + PERBUF + Period Buffer Value + 4 + 20 + + + + + PERBUF_DITH5_MODE + Period Buffer + PERBUF + 0x6C + 32 + 0xFFFFFFFF + + + DITHERBUF + Dithering Buffer Cycle Number + 0 + 5 + + + PERBUF + Period Buffer Value + 5 + 19 + + + + + PERBUF_DITH6_MODE + Period Buffer + PERBUF + 0x6C + 32 + 0xFFFFFFFF + + + DITHERBUF + Dithering Buffer Cycle Number + 0 + 6 + + + PERBUF + Period Buffer Value + 6 + 18 + + + + + 4 + 4 + CCBUF[%s] + Compare and Capture Buffer + 0x70 + 32 + 0x00000000 + + + CCBUF + Channel Compare/Capture Buffer Value + 0 + 24 + + + + + 4 + 4 + CCBUF_DITH4_MODE[%s] + Compare and Capture Buffer + CCBUF[%s] + 0x70 + 32 + 0x00000000 + + + CCBUF + Channel Compare/Capture Buffer Value + 0 + 4 + + + DITHERBUF + Dithering Buffer Cycle Number + 4 + 20 + + + + + 4 + 4 + CCBUF_DITH5_MODE[%s] + Compare and Capture Buffer + CCBUF[%s] + 0x70 + 32 + 0x00000000 + + + DITHERBUF + Dithering Buffer Cycle Number + 0 + 5 + + + CCBUF + Channel Compare/Capture Buffer Value + 5 + 19 + + + + + 4 + 4 + CCBUF_DITH6_MODE[%s] + Compare and Capture Buffer + CCBUF[%s] + 0x70 + 32 + 0x00000000 + + + DITHERBUF + Dithering Buffer Cycle Number + 0 + 6 + + + CCBUF + Channel Compare/Capture Buffer Value + 6 + 18 + + + + + + + TCC1 + 0x42002800 + + TCC1 + 18 + + + + TCC2 + 0x42002C00 + + TCC2 + 19 + + + + WDT + U22511.0.1 + Watchdog Timer + WDT + WDT_ + 0x40002000 + + 0 + 0xD + registers + + + WDT + 1 + + + + CTRLA + Control + 0x0 + 8 + 0x00 + + + ENABLE + Enable + 1 + 1 + + + WEN + Watchdog Timer Window Mode Enable + 2 + 1 + + + ALWAYSON + Always-On + 7 + 1 + + + + + CONFIG + Configuration + 0x1 + 8 + 0xBB + + + PER + Time-Out Period + 0 + 4 + + PERSelect + + CYC8 + 8 clock cycles + 0x0 + + + CYC16 + 16 clock cycles + 0x1 + + + CYC32 + 32 clock cycles + 0x2 + + + CYC64 + 64 clock cycles + 0x3 + + + CYC128 + 128 clock cycles + 0x4 + + + CYC256 + 256 clock cycles + 0x5 + + + CYC512 + 512 clock cycles + 0x6 + + + CYC1024 + 1024 clock cycles + 0x7 + + + CYC2048 + 2048 clock cycles + 0x8 + + + CYC4096 + 4096 clock cycles + 0x9 + + + CYC8192 + 8192 clock cycles + 0xA + + + CYC16384 + 16384 clock cycles + 0xB + + + + + WINDOW + Window Mode Time-Out Period + 4 + 4 + + WINDOWSelect + + CYC8 + 8 clock cycles + 0x0 + + + CYC16 + 16 clock cycles + 0x1 + + + CYC32 + 32 clock cycles + 0x2 + + + CYC64 + 64 clock cycles + 0x3 + + + CYC128 + 128 clock cycles + 0x4 + + + CYC256 + 256 clock cycles + 0x5 + + + CYC512 + 512 clock cycles + 0x6 + + + CYC1024 + 1024 clock cycles + 0x7 + + + CYC2048 + 2048 clock cycles + 0x8 + + + CYC4096 + 4096 clock cycles + 0x9 + + + CYC8192 + 8192 clock cycles + 0xA + + + CYC16384 + 16384 clock cycles + 0xB + + + + + + + EWCTRL + Early Warning Interrupt Control + 0x2 + 8 + 0x0B + + + EWOFFSET + Early Warning Interrupt Time Offset + 0 + 4 + + EWOFFSETSelect + + CYC8 + 8 clock cycles + 0x0 + + + CYC16 + 16 clock cycles + 0x1 + + + CYC32 + 32 clock cycles + 0x2 + + + CYC64 + 64 clock cycles + 0x3 + + + CYC128 + 128 clock cycles + 0x4 + + + CYC256 + 256 clock cycles + 0x5 + + + CYC512 + 512 clock cycles + 0x6 + + + CYC1024 + 1024 clock cycles + 0x7 + + + CYC2048 + 2048 clock cycles + 0x8 + + + CYC4096 + 4096 clock cycles + 0x9 + + + CYC8192 + 8192 clock cycles + 0xA + + + CYC16384 + 16384 clock cycles + 0xB + + + + + + + INTENCLR + Interrupt Enable Clear + 0x4 + 8 + 0x00 + + + EW + Early Warning Interrupt Enable + 0 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x5 + 8 + 0x00 + + + EW + Early Warning Interrupt Enable + 0 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x6 + 8 + 0x00 + + + EW + Early Warning + 0 + 1 + + + + + SYNCBUSY + Synchronization Busy + 0x8 + 32 + read-only + 0x00000000 + + + ENABLE + Enable Busy + 1 + 1 + + + WEN + Window Enable Busy + 2 + 1 + + + ALWAYSON + Always-On Busy + 3 + 1 + + + CLEAR + Clear Busy + 4 + 1 + + + + + CLEAR + Clear + 0xC + 8 + write-only + 0x00 + + + CLEAR + Watchdog Clear + 0 + 8 + + CLEARSelect + + KEY + Clear Key + 0xA5 + + + + + + + + + MPU + Memory Protection Unit + MPU + MPU_ + 0xE000ED90 + + 0 + 0x14 + registers + + + + TYPE + MPU Type Register + 0x0 + 32 + read-only + + + SEPARATE + Separate instruction and Data Memory MapsRegions + 0 + 1 + + + DREGION + Number of Data Regions + 8 + 8 + + + IREGION + Number of Instruction Regions + 16 + 8 + + + + + CTRL + MPU Control Register + 0x4 + 32 + + + ENABLE + MPU Enable + 0 + 1 + + + HFNMIENA + Enable Hard Fault and NMI handlers + 1 + 1 + + + PRIVDEFENA + Enables privileged software access to default memory map + 2 + 1 + + + + + RNR + MPU Region Number Register + 0x8 + 32 + + + REGION + Region referenced by RBAR and RASR + 0 + 8 + + + + + RBAR + MPU Region Base Address Register + 0xC + 32 + + + REGION + Region number + 0 + 4 + + + VALID + Region number valid + 4 + 1 + + + ADDR + Region base address + 5 + 27 + + + + + RASR + MPU Region Attribute and Size Register + 0x10 + 32 + + + ENABLE + Region Enable + 0 + 1 + + + SIZE + Region Size + 1 + 5 + + + SRD + Sub-region disable + 8 + 8 + + + B + Bufferable bit + 16 + 1 + + + C + Cacheable bit + 17 + 1 + + + S + Shareable bit + 18 + 1 + + + TEX + TEX bit + 19 + 3 + + + AP + Access Permission + 24 + 3 + + + XN + Execute Never Attribute + 28 + 1 + + + + + + + NVIC + Nested Vectored Interrupt Controller + NVIC + NVIC_ + 0xE000E100 + + 0 + 0x320 + registers + + + + ISER + Interrupt Set Enable Register + 0x0 + 32 + 0x00000000 + + + SETENA + Interrupt set enable bits + 0 + 31 + + + + + ICER + Interrupt Clear Enable Register + 0x80 + 32 + 0x00000000 + + + CLRENA + Interrupt clear-enable bits + 0 + 31 + + + + + ISPR + Interrupt Set Pending Register + 0x100 + 32 + 0x00000000 + + + SETPEND + Interrupt set-pending bits + 0 + 31 + + + + + ICPR + Interrupt Clear Pending Register + 0x180 + 32 + 0x00000000 + + + CLRPEND + Interrupt clear-pending bits + 0 + 31 + + + + + 8 + 4 + IPR[%s] + Interrupt Priority Register n + 0x300 + 32 + 0x00000000 + + + PRI0 + Priority of interrupt n + 0 + 2 + + + PRI1 + Priority of interrupt n + 8 + 2 + + + PRI2 + Priority of interrupt n + 16 + 2 + + + PRI3 + Priority of interrupt n + 24 + 2 + + + + + + + SysTick + System timer + SysTick + SysTick_ + 0xE000E010 + + 0 + 0x10 + registers + + + + CSR + SysTick Control and Status Register + 0x0 + 32 + 0x4 + + + ENABLE + SysTick Counter Enable + 0 + 1 + + ENABLESelect + + VALUE_0 + Counter disabled + 0 + + + VALUE_1 + Counter enabled + 1 + + + + + TICKINT + SysTick Exception Request Enable + 1 + 1 + + TICKINTSelect + + VALUE_0 + Counting down to 0 does not assert the SysTick exception request + 0 + + + VALUE_1 + Counting down to 0 asserts the SysTick exception request + 1 + + + + + CLKSOURCE + Clock Source 0=external, 1=processor + 2 + 1 + + CLKSOURCESelect + + VALUE_0 + External clock + 0 + + + VALUE_1 + Processor clock + 1 + + + + + COUNTFLAG + Timer counted to 0 since last read of register + 16 + 1 + + + + + RVR + SysTick Reload Value Register + 0x4 + 32 + + + RELOAD + Value to load into the SysTick Current Value Register when the counter reaches 0 + 0 + 24 + + + + + CVR + SysTick Current Value Register + 0x8 + 32 + + + CURRENT + Current value at the time the register is accessed + 0 + 24 + + + + + CALIB + SysTick Calibration Value Register + 0xC + 32 + read-only + 0 + + + TENMS + Reload value to use for 10ms timing + 0 + 24 + + + SKEW + TENMS is rounded from non-integer ratio + 30 + 1 + + SKEWSelect + + VALUE_0 + 10ms calibration value is exact + 0 + + + VALUE_1 + 10ms calibration value is inexact, because of the clock frequency + 1 + + + + + NOREF + No Separate Reference Clock + 31 + 1 + + NOREFSelect + + VALUE_0 + The reference clock is provided + 0 + + + VALUE_1 + The reference clock is not provided + 1 + + + + + + + + + SystemControl + System Control Registers + SystemControl + SystemControl_ + 0xE000E000 + + 0 + 0xD34 + registers + + + + CPUID + CPUID Base Register + 0xD00 + 32 + read-only + 0x410CC601 + + + REVISION + Minor revision number + 0 + 4 + + + PARTNO + Processor Part Number, 0xC60=Cortex-M0+ + 4 + 12 + + + ARCHITECTURE + Processor Architecture, 0xC=ARMv6-M + 16 + 4 + + + VARIANT + Major revision number + 20 + 4 + + + IMPLEMENTER + Implementer code, ARM=0x41 + 24 + 8 + + + + + ICSR + Interrupt Control and State Register + 0xD04 + 32 + 0x00000000 + + + VECTACTIVE + Debug: Exception number of currently executing exception, or 0 if thread mode + 0 + 9 + + + VECTPENDING + Exception number of the highest priority pending enabled exception + 12 + 9 + + + ISRPENDING + Debug: NVIC interrupt pending + 22 + 1 + + + ISRPREEMPT + Debug: Pending exception serviced on exit from debug halt + 23 + 1 + + + PENDSTCLR + SysTick exception clear-pending bit + 25 + 1 + + PENDSTCLRSelect + + VALUE_0 + No effect + 0 + + + VALUE_1 + Removes the pending state from the SysTick exception + 1 + + + + + PENDSTSET + SysTick exception set-pending bit + 26 + 1 + + PENDSTSETSelect + + VALUE_0 + Write: no effect; read: SysTick exception is not pending + 0 + + + VALUE_1 + Write: changes SysTick exception state to pending; read: SysTick exception is pending + 1 + + + + + PENDSVCLR + PendSV clear-pending bit + 27 + 1 + + PENDSVCLRSelect + + VALUE_0 + No effect + 0 + + + VALUE_1 + Removes the pending state from the PendSV exception + 1 + + + + + PENDSVSET + PendSV set-pending bit + 28 + 1 + + PENDSVSETSelect + + VALUE_0 + Write: no effect; read: PendSV exception is not pending + 0 + + + VALUE_1 + Write: changes PendSV exception state to pending; read: PendSV exception is pending + 1 + + + + + NMIPENDSET + NMI set-pending bit + 31 + 1 + + NMIPENDSETSelect + + VALUE_0 + Write: no effect; read: NMI exception is not pending + 0 + + + VALUE_1 + Write: changes NMI exception state to pending; read: NMI exception is pending + 1 + + + + + + + VTOR + Vector Table Offset Register + 0xD08 + 32 + 0x00000000 + + + TBLOFF + Vector table base offset + 7 + 25 + + + + + AIRCR + Application Interrupt and Reset Control Register + 0xD0C + 32 + 0x00000000 + + + VECTCLRACTIVE + Debug: Clear state information + 1 + 1 + + + SYSRESETREQ + System Reset Request + 2 + 1 + + SYSRESETREQSelect + + VALUE_0 + No system reset request + 0 + + + VALUE_1 + Asserts a signal to the outer system that requests a reset + 1 + + + + + ENDIANNESS + Data Endianness, 0=little, 1=big + 15 + 1 + + ENDIANNESSSelect + + VALUE_0 + Little-endian + 0 + + + VALUE_1 + Big-endian + 1 + + + + + VECTKEY + Register key (0x05FA) + 16 + 16 + + + + + SCR + System Control Register + 0xD10 + 32 + 0x00000000 + + + SLEEPONEXIT + Sleep-On-Exit when exiting Handler mode + 1 + 1 + + SLEEPONEXITSelect + + VALUE_0 + O not sleep when returning to Thread mode + 0 + + + VALUE_1 + Enter sleep, or deep sleep, on return from an ISR + 1 + + + + + SLEEPDEEP + Uses Deep Sleep as low power mode + 2 + 1 + + SLEEPDEEPSelect + + VALUE_0 + Sleep + 0 + + + VALUE_1 + Deep sleep + 1 + + + + + SEVONPEND + Send Event on Pending bit + 4 + 1 + + SEVONPENDSelect + + VALUE_0 + Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded + 0 + + + VALUE_1 + Enabled events and all interrupts, including disabled interrupts, can wakeup the processor + 1 + + + + + + + CCR + Configuration and Control Register + 0xD14 + 32 + read-only + 0x00000204 + + + UNALIGN_TRP + Unaligned accesses generates a Hard Fault + 3 + 1 + + UNALIGN_TRPSelect + + VALUE_0 + Do not trap unaligned halfword and word accesses + 0 + + + VALUE_1 + Trap unaligned halfword and word accesses + 1 + + + + + STKALIGN + Stack 8-byte aligned on exception entry + 9 + 1 + + STKALIGNSelect + + VALUE_0 + 4-byte aligned + 0 + + + VALUE_1 + 8-byte aligned + 1 + + + + + + + SHPR2 + System Handler Priority Register 2 + 0xD1C + 32 + 0x00000000 + + + PRI_11 + Priority of system handler 11, SVCall + 24 + 8 + + + + + SHPR3 + System Handler Priority Register 3 + 0xD20 + 32 + 0x00000000 + + + PRI_14 + Priority of system handler 14, PendSV + 16 + 8 + + + PRI_15 + Priority of system handler 15, SysTick exception + 24 + 8 + + + + + SHCSR + System Handler Control and State Register + 0xD24 + 32 + 0x00000000 + + + SVCALLPENDED + 15 + 1 + + + + + DFSR + Debug Fault Status Register + 0xD30 + 32 + 0x00000000 + + + HALTED + Halt request debug event active + 0 + 1 + + + BKPT + Breakpoint debug event + 1 + 1 + + + DWTTRAP + DWT debug event + 2 + 1 + + + VCATCH + Vector catch debug event + 3 + 1 + + + EXTERNAL + EDBGRQ debug event + 4 + 1 + + + + + + + diff --git a/svd/ATSAMC20J18A.svd b/svd/ATSAMC20J18A.svd new file mode 100644 index 000000000000..7a5346ef8039 --- /dev/null +++ b/svd/ATSAMC20J18A.svd @@ -0,0 +1,21842 @@ + + + + Microchip Technology + MCHP + ATSAMC20J18A + SAMC20 + 0 + Microchip ATSAMC20J18A Microcontroller + + CM0+ + r0p0 + selectable + true + false + 2 + false + + 8 + 32 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + AC + U22451.1.1 + Analog Comparators + AC + AC_ + 0x42005000 + + 0 + 0x24 + registers + + + AC + 27 + + + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + + + CTRLB + Control B + 0x1 + 8 + write-only + 0x00 + + + START0 + Comparator 0 Start Comparison + 0 + 1 + + + START1 + Comparator 1 Start Comparison + 1 + 1 + + + + + EVCTRL + Event Control + 0x2 + 16 + 0x0000 + + + COMPEO0 + Comparator 0 Event Output Enable + 0 + 1 + + + COMPEO1 + Comparator 1 Event Output Enable + 1 + 1 + + + WINEO0 + Window 0 Event Output Enable + 4 + 1 + + + COMPEI0 + Comparator 0 Event Input Enable + 8 + 1 + + + COMPEI1 + Comparator 1 Event Input Enable + 9 + 1 + + + INVEI0 + Comparator 0 Input Event Invert Enable + 12 + 1 + + + INVEI1 + Comparator 1 Input Event Invert Enable + 13 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x4 + 8 + 0x00 + + + COMP0 + Comparator 0 Interrupt Enable + 0 + 1 + + + COMP1 + Comparator 1 Interrupt Enable + 1 + 1 + + + WIN0 + Window 0 Interrupt Enable + 4 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x5 + 8 + 0x00 + + + COMP0 + Comparator 0 Interrupt Enable + 0 + 1 + + + COMP1 + Comparator 1 Interrupt Enable + 1 + 1 + + + WIN0 + Window 0 Interrupt Enable + 4 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x6 + 8 + 0x00 + + + COMP0 + Comparator 0 + 0 + 1 + + + COMP1 + Comparator 1 + 1 + 1 + + + WIN0 + Window 0 + 4 + 1 + + + + + STATUSA + Status A + 0x7 + 8 + read-only + 0x00 + + + STATE0 + Comparator 0 Current State + 0 + 1 + + + STATE1 + Comparator 1 Current State + 1 + 1 + + + WSTATE0 + Window 0 Current State + 4 + 2 + + WSTATE0Select + + ABOVE + Signal is above window + 0 + + + INSIDE + Signal is inside window + 1 + + + BELOW + Signal is below window + 2 + + + + + + + STATUSB + Status B + 0x8 + 8 + read-only + 0x00 + + + READY0 + Comparator 0 Ready + 0 + 1 + + + READY1 + Comparator 1 Ready + 1 + 1 + + + + + DBGCTRL + Debug Control + 0x9 + 8 + 0x00 + + + DBGRUN + Debug Run + 0 + 1 + + + + + WINCTRL + Window Control + 0xA + 8 + 0x00 + + + WEN0 + Window 0 Mode Enable + 0 + 1 + + + WINTSEL0 + Window 0 Interrupt Selection + 1 + 2 + + WINTSEL0Select + + ABOVE + Interrupt on signal above window + 0 + + + INSIDE + Interrupt on signal inside window + 1 + + + BELOW + Interrupt on signal below window + 2 + + + OUTSIDE + Interrupt on signal outside window + 3 + + + + + + + 4 + 1 + SCALER[%s] + Scaler n + 0xC + 8 + 0x00 + + + VALUE + Scaler Value + 0 + 6 + + + + + 4 + 4 + COMPCTRL[%s] + Comparator Control n + 0x10 + 32 + 0x00000000 + + + ENABLE + Enable + 1 + 1 + + + SINGLE + Single-Shot Mode + 2 + 1 + + + INTSEL + Interrupt Selection + 3 + 2 + + INTSELSelect + + TOGGLE + Interrupt on comparator output toggle + 0 + + + RISING + Interrupt on comparator output rising + 1 + + + FALLING + Interrupt on comparator output falling + 2 + + + EOC + Interrupt on end of comparison (single-shot mode only) + 3 + + + + + RUNSTDBY + Run in Standby + 6 + 1 + + + MUXNEG + Negative Input Mux Selection + 8 + 3 + + MUXNEGSelect + + PIN0 + I/O pin 0 + 0 + + + PIN1 + I/O pin 1 + 1 + + + PIN2 + I/O pin 2 + 2 + + + PIN3 + I/O pin 3 + 3 + + + GND + Ground + 4 + + + VSCALE + VDD scaler + 5 + + + BANDGAP + Internal bandgap voltage + 6 + + + + + MUXPOS + Positive Input Mux Selection + 12 + 3 + + MUXPOSSelect + + PIN0 + I/O pin 0 + 0 + + + PIN1 + I/O pin 1 + 1 + + + PIN2 + I/O pin 2 + 2 + + + PIN3 + I/O pin 3 + 3 + + + VSCALE + VDD Scaler + 4 + + + + + SWAP + Swap Inputs and Invert + 15 + 1 + + + SPEED + Speed Selection + 16 + 2 + + SPEEDSelect + + LOW + Low speed + 0 + + + HIGH + High speed + 3 + + + + + HYSTEN + Hysteresis Enable + 19 + 1 + + + FLEN + Filter Length + 24 + 3 + + FLENSelect + + OFF + No filtering + 0 + + + MAJ3 + 3-bit majority function (2 of 3) + 1 + + + MAJ5 + 5-bit majority function (3 of 5) + 2 + + + + + OUT + Output + 28 + 2 + + OUTSelect + + OFF + The output of COMPn is not routed to the COMPn I/O port + 0 + + + ASYNC + The asynchronous output of COMPn is routed to the COMPn I/O port + 1 + + + SYNC + The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port + 2 + + + + + + + SYNCBUSY + Synchronization Busy + 0x20 + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + Enable Synchronization Busy + 1 + 1 + + + WINCTRL + WINCTRL Synchronization Busy + 2 + 1 + + + COMPCTRL0 + COMPCTRL 0 Synchronization Busy + 3 + 1 + + + COMPCTRL1 + COMPCTRL 1 Synchronization Busy + 4 + 1 + + + + + + + ADC0 + U22472.2.0 + Analog Digital Converter + ADC + ADC_ + 0x42004400 + + 0 + 0x2E + registers + + + ADC0 + 25 + + + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + SLAVEEN + Slave Enable + 5 + 1 + + + RUNSTDBY + Run During Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + + + CTRLB + Control B + 0x1 + 8 + 0x00 + + + PRESCALER + Prescaler Configuration + 0 + 3 + + PRESCALERSelect + + DIV2 + Peripheral clock / 2 + 0x0 + + + DIV4 + Peripheral clock / 4 + 0x1 + + + DIV8 + Peripheral clock / 8 + 0x2 + + + DIV16 + Peripheral clock / 16 + 0x3 + + + DIV32 + Peripheral clock / 32 + 0x4 + + + DIV64 + Peripheral clock / 64 + 0x5 + + + DIV128 + Peripheral clock / 128 + 0x6 + + + DIV256 + Peripheral clock / 256 + 0x7 + + + + + + + REFCTRL + Reference Control + 0x2 + 8 + 0x00 + + + REFSEL + Reference Selection + 0 + 4 + + REFSELSelect + + INTREF + Internal Bandgap Reference + 0x0 + + + INTVCC0 + 1/1.6 VDDANA + 0x1 + + + INTVCC1 + 1/2 VDDANA + 0x2 + + + AREFA + External Reference + 0x3 + + + INTVCC2 + VDDANA + 0x5 + + + + + REFCOMP + Reference Buffer Offset Compensation Enable + 7 + 1 + + + + + EVCTRL + Event Control + 0x3 + 8 + 0x00 + + + FLUSHEI + Flush Event Input Enable + 0 + 1 + + + STARTEI + Start Conversion Event Input Enable + 1 + 1 + + + FLUSHINV + Flush Event Invert Enable + 2 + 1 + + + STARTINV + Start Event Invert Enable + 3 + 1 + + + RESRDYEO + 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read-only + 0x00000000 + + + PID7 + Peripheral Identification 7 + 0x1FDC + 32 + read-only + 0x00000000 + + + PID0 + Peripheral Identification 0 + 0x1FE0 + 32 + read-only + 0x000000D0 + + + PARTNBL + Part Number Low + 0 + 8 + + + + + PID1 + Peripheral Identification 1 + 0x1FE4 + 32 + read-only + 0x000000FC + + + PARTNBH + Part Number High + 0 + 4 + + + JEPIDCL + Low part of the JEP-106 Identity Code + 4 + 4 + + + + + PID2 + Peripheral Identification 2 + 0x1FE8 + 32 + read-only + 0x00000009 + + + JEPIDCH + JEP-106 Identity Code High + 0 + 3 + + + JEPU + JEP-106 Identity Code is used + 3 + 1 + + + REVISION + Revision Number + 4 + 4 + + + + + PID3 + Peripheral Identification 3 + 0x1FEC + 32 + read-only + 0x00000000 + + + CUSMOD + ARM CUSMOD + 0 + 4 + + + REVAND + Revision Number + 4 + 4 + + + + + CID0 + Component Identification 0 + 0x1FF0 + 32 + read-only + 0x0000000D + + + PREAMBLEB0 + Preamble Byte 0 + 0 + 8 + + + + + CID1 + Component Identification 1 + 0x1FF4 + 32 + read-only + 0x00000010 + + + PREAMBLE + Preamble + 0 + 4 + + + CCLASS + Component Class + 4 + 4 + + + + + CID2 + Component Identification 2 + 0x1FF8 + 32 + read-only + 0x00000005 + + + PREAMBLEB2 + Preamble Byte 2 + 0 + 8 + + + + + CID3 + Component Identification 3 + 0x1FFC + 32 + read-only + 0x000000B1 + + + PREAMBLEB3 + Preamble Byte 3 + 0 + 8 + + + + + + + EIC + U22542.0.4 + External Interrupt Controller + EIC + EIC_ + 0x40002800 + + 0 + 0x24 + registers + + + EIC + 3 + + + + CTRLA + Control + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + CKSEL + Clock Selection + 4 + 1 + + CKSELSelect + + CLK_GCLK + Clocked by GCLK + 0 + + + CLK_ULP32K + Clocked by ULP32K + 1 + + + + + + + NMICTRL + NMI Control + 0x1 + 8 + 0x00 + + + NMISENSE + NMI Input Sense Configuration + 0 + 3 + + NMISENSESelect + + NONE + No detection + 0 + + + RISE + Rising-edge detection + 1 + + + FALL + Falling-edge detection + 2 + + + BOTH + Both-edges detection + 3 + + + HIGH + High-level detection + 4 + + + LOW + Low-level detection + 5 + + + + + NMIFILTEN + NMI Filter Enable + 3 + 1 + + + NMIASYNCH + NMI Asynchronous edge Detection Enable + 4 + 1 + + NMIASYNCHSelect + + SYNC + Edge detection is clock synchronously operated + 0 + + + ASYNC + Edge detection is clock asynchronously operated + 1 + + + + + + + NMIFLAG + NMI Interrupt Flag + 0x2 + 16 + 0x0000 + + + NMI + NMI Interrupt Flag + 0 + 1 + + + + + SYNCBUSY + Syncbusy register + 0x4 + 32 + read-only + 0x00000000 + + + SWRST + Software reset synchronisation + 0 + 1 + + + ENABLE + Enable synchronisation + 1 + 1 + + + + + EVCTRL + Event Control + 0x8 + 32 + 0x00000000 + + + EXTINTEO + External Interrupt Event Output Enable + 0 + 16 + + + + + INTENCLR + Interrupt Enable Clear + 0xC + 32 + 0x00000000 + + + EXTINT + External Interrupt Disable + 0 + 16 + + + + + INTENSET + Interrupt Enable Set + 0x10 + 32 + 0x00000000 + + + EXTINT + External Interrupt Enable + 0 + 16 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x14 + 32 + 0x00000000 + + + EXTINT + External Interrupt Flag + 0 + 16 + + + + + ASYNCH + EIC Asynchronous edge Detection Enable + 0x18 + 32 + 0x00000000 + + + ASYNCH + EIC Asynchronous edge Detection Enable + 0 + 16 + + ASYNCHSelect + + SYNC + Edge detection is clock synchronously operated + 0 + + + ASYNC + Edge detection is clock asynchronously operated + 1 + + + + + + + 2 + 4 + CONFIG[%s] + Configuration n + 0x1C + 32 + 0x00000000 + + + SENSE0 + Input Sense Configuration 0 + 0 + 3 + + SENSE0Select + + NONE + No detection + 0 + + + RISE + Rising edge detection + 1 + + + FALL + Falling edge detection + 2 + + + BOTH + Both edges detection + 3 + + + HIGH + High level detection + 4 + + + LOW + Low level detection + 5 + + + + + FILTEN0 + Filter Enable 0 + 3 + 1 + + + SENSE1 + Input Sense Configuration 1 + 4 + 3 + + SENSE1Select + + NONE + No detection + 0 + + + RISE + Rising edge detection + 1 + + + FALL + Falling edge detection + 2 + + + BOTH + Both edges detection + 3 + + + HIGH + High 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level detection + 4 + + + LOW + Low level detection + 5 + + + + + FILTEN4 + Filter Enable 4 + 19 + 1 + + + SENSE5 + Input Sense Configuration 5 + 20 + 3 + + SENSE5Select + + NONE + No detection + 0 + + + RISE + Rising edge detection + 1 + + + FALL + Falling edge detection + 2 + + + BOTH + Both edges detection + 3 + + + HIGH + High level detection + 4 + + + LOW + Low level detection + 5 + + + + + FILTEN5 + Filter Enable 5 + 23 + 1 + + + SENSE6 + Input Sense Configuration 6 + 24 + 3 + + SENSE6Select + + NONE + No detection + 0 + + + RISE + Rising edge detection + 1 + + + FALL + Falling edge detection + 2 + + + BOTH + Both edges detection + 3 + + + HIGH + High level detection + 4 + + + LOW + Low level detection + 5 + + + + + FILTEN6 + Filter Enable 6 + 27 + 1 + + + SENSE7 + Input Sense Configuration 7 + 28 + 3 + + SENSE7Select + + NONE + No detection + 0 + + + RISE + Rising edge detection + 1 + + + FALL + Falling edge detection + 2 + + + BOTH + Both edges detection + 3 + + + HIGH + High level detection + 4 + + + LOW + Low level detection + 5 + + + + + FILTEN7 + Filter Enable 7 + 31 + 1 + + + + + + + EVSYS + U22561.0.2 + Event System Interface + EVSYS + EVSYS_ + 0x42000000 + + 0 + 0x19C + registers + + + EVSYS + 8 + + + + CTRLA + Control + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + + + CHSTATUS + Channel Status + 0xC + 32 + read-only + 0x00000000 + + + USRRDY0 + Channel 0 User Ready + 0 + 1 + + + USRRDY1 + Channel 1 User Ready + 1 + 1 + + + USRRDY2 + Channel 2 User Ready + 2 + 1 + + + USRRDY3 + Channel 3 User Ready + 3 + 1 + + + USRRDY4 + Channel 4 User Ready + 4 + 1 + + + USRRDY5 + Channel 5 User Ready + 5 + 1 + + + CHBUSY0 + Channel 0 Busy + 16 + 1 + + + CHBUSY1 + Channel 1 Busy + 17 + 1 + + + CHBUSY2 + Channel 2 Busy + 18 + 1 + + + CHBUSY3 + Channel 3 Busy + 19 + 1 + + + CHBUSY4 + Channel 4 Busy + 20 + 1 + + + CHBUSY5 + Channel 5 Busy + 21 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x10 + 32 + 0x00000000 + + + OVR0 + Channel 0 Overrun Interrupt Enable + 0 + 1 + + + OVR1 + Channel 1 Overrun Interrupt Enable + 1 + 1 + + + OVR2 + Channel 2 Overrun Interrupt Enable + 2 + 1 + + + OVR3 + Channel 3 Overrun Interrupt Enable + 3 + 1 + + + OVR4 + Channel 4 Overrun Interrupt Enable + 4 + 1 + + + OVR5 + Channel 5 Overrun Interrupt Enable + 5 + 1 + + + EVD0 + Channel 0 Event Detection Interrupt Enable + 16 + 1 + + + EVD1 + Channel 1 Event Detection Interrupt Enable + 17 + 1 + + + EVD2 + Channel 2 Event Detection Interrupt Enable + 18 + 1 + + + EVD3 + Channel 3 Event Detection Interrupt Enable + 19 + 1 + + + EVD4 + Channel 4 Event Detection Interrupt Enable + 20 + 1 + + + EVD5 + Channel 5 Event Detection Interrupt Enable + 21 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x14 + 32 + 0x00000000 + + + OVR0 + Channel 0 Overrun Interrupt Enable + 0 + 1 + + + OVR1 + Channel 1 Overrun Interrupt Enable + 1 + 1 + + + OVR2 + Channel 2 Overrun Interrupt Enable + 2 + 1 + + + OVR3 + Channel 3 Overrun Interrupt Enable + 3 + 1 + + + OVR4 + Channel 4 Overrun Interrupt Enable + 4 + 1 + + + OVR5 + Channel 5 Overrun Interrupt Enable + 5 + 1 + + + EVD0 + Channel 0 Event Detection Interrupt Enable + 16 + 1 + + + EVD1 + Channel 1 Event Detection Interrupt Enable + 17 + 1 + + + EVD2 + Channel 2 Event Detection Interrupt Enable + 18 + 1 + + + EVD3 + Channel 3 Event Detection Interrupt Enable + 19 + 1 + + + EVD4 + Channel 4 Event Detection Interrupt Enable + 20 + 1 + + + EVD5 + Channel 5 Event Detection Interrupt Enable + 21 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x18 + 32 + 0x00000000 + + + OVR0 + Channel 0 Overrun + 0 + 1 + + + OVR1 + Channel 1 Overrun + 1 + 1 + + + OVR2 + Channel 2 Overrun + 2 + 1 + + + OVR3 + Channel 3 Overrun + 3 + 1 + + + OVR4 + Channel 4 Overrun + 4 + 1 + + + OVR5 + Channel 5 Overrun + 5 + 1 + + + EVD0 + Channel 0 Event Detection + 16 + 1 + + + EVD1 + Channel 1 Event Detection + 17 + 1 + + + EVD2 + Channel 2 Event Detection + 18 + 1 + + + EVD3 + Channel 3 Event Detection + 19 + 1 + + + EVD4 + Channel 4 Event Detection + 20 + 1 + + + EVD5 + Channel 5 Event Detection + 21 + 1 + + + + + SWEVT + Software Event + 0x1C + 32 + write-only + 0x00000000 + + + CHANNEL0 + Channel 0 Software Selection + 0 + 1 + + + CHANNEL1 + Channel 1 Software Selection + 1 + 1 + + + CHANNEL2 + Channel 2 Software Selection + 2 + 1 + + + CHANNEL3 + Channel 3 Software Selection + 3 + 1 + + + CHANNEL4 + Channel 4 Software Selection + 4 + 1 + + + CHANNEL5 + Channel 5 Software Selection + 5 + 1 + + + + + 6 + 4 + CHANNEL[%s] + Channel n + 0x20 + 32 + 0x00008000 + + + EVGEN + Event Generator Selection + 0 + 7 + + + PATH + Path Selection + 8 + 2 + + PATHSelect + + SYNCHRONOUS + Synchronous path + 0 + + + RESYNCHRONIZED + Resynchronized path + 1 + + + ASYNCHRONOUS + Asynchronous path + 2 + + + + + EDGSEL + Edge Detection Selection + 10 + 2 + + EDGSELSelect + + NO_EVT_OUTPUT + No event output when using the resynchronized or synchronous path + 0 + + + RISING_EDGE + Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path + 1 + + + FALLING_EDGE + Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path + 2 + + + BOTH_EDGES + Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path + 3 + + + + + RUNSTDBY + Run in standby + 14 + 1 + + + ONDEMAND + Generic Clock On Demand + 15 + 1 + + + + + 47 + 4 + USER[%s] + User Multiplexer n + 0x80 + 32 + 0x00000000 + + + CHANNEL + Channel Event Selection + 0 + 4 + + + + + + + FREQM + U22571.0.1 + Frequency Meter + FREQM + FREQM_ + 0x40002C00 + + 0 + 0x14 + registers + + + FREQM + 4 + + + + CTRLA + Control A Register + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + + + CTRLB + Control B Register + 0x1 + 8 + write-only + 0x00 + + + START + Start Measurement + 0 + 1 + + + + + CFGA + Config A register + 0x2 + 16 + 0x0000 + + + REFNUM + Number of Reference Clock Cycles + 0 + 8 + + + + + INTENCLR + Interrupt Enable Clear Register + 0x8 + 8 + 0x00 + + + DONE + Measurement Done Interrupt Enable + 0 + 1 + + + + + INTENSET + Interrupt Enable Set Register + 0x9 + 8 + 0x00 + + + DONE + Measurement Done Interrupt Enable + 0 + 1 + + + + + INTFLAG + Interrupt Flag Register + 0xA + 8 + 0x00 + + + DONE + Measurement Done + 0 + 1 + + + + + STATUS + Status Register + 0xB + 8 + 0x00 + + + BUSY + FREQM Status + 0 + 1 + + + OVF + Sticky Count Value Overflow + 1 + 1 + + + + + SYNCBUSY + Synchronization Busy Register + 0xC + 32 + read-only + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + + + VALUE + Count Value Register + 0x10 + 32 + read-only + 0x00000000 + + + VALUE + Measurement Value + 0 + 24 + + + + + + + GCLK + U21221.1.1 + Generic Clock Generator + GCLK + GCLK_ + 0x40001C00 + + 0 + 0x184 + registers + + + + CTRLA + Control + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + + + SYNCBUSY + Synchronization Busy + 0x4 + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchroniation Busy bit + 0 + 1 + + + GENCTRL0 + Generic Clock Generator Control 0 Synchronization Busy bits + 2 + 1 + + GENCTRL0Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + + + GENCTRL1 + Generic Clock Generator Control 1 Synchronization Busy bits + 3 + 1 + + GENCTRL1Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + + + GENCTRL2 + Generic Clock Generator Control 2 Synchronization Busy bits + 4 + 1 + + GENCTRL2Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + + + GENCTRL3 + Generic Clock Generator Control 3 Synchronization Busy bits + 5 + 1 + + GENCTRL3Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + + + GENCTRL4 + Generic Clock Generator Control 4 Synchronization Busy bits + 6 + 1 + + GENCTRL4Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + + + GENCTRL5 + Generic Clock Generator Control 5 Synchronization Busy bits + 7 + 1 + + GENCTRL5Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + + + GENCTRL6 + Generic Clock Generator Control 6 Synchronization Busy bits + 8 + 1 + + GENCTRL6Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + + + GENCTRL7 + Generic Clock Generator Control 7 Synchronization Busy bits + 9 + 1 + + GENCTRL7Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + + + GENCTRL8 + Generic Clock Generator Control 8 Synchronization Busy bits + 10 + 1 + + GENCTRL8Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + + + + + 9 + 4 + GENCTRL[%s] + Generic Clock Generator Control + 0x20 + 32 + 0x00000000 + + + SRC + Source Select + 0 + 3 + + SRCSelect + + XOSC + XOSC oscillator output + 0 + + + GCLKIN + Generator input pad + 1 + + + GCLKGEN1 + Generic clock generator 1 output + 2 + + + OSCULP32K + OSCULP32K oscillator output + 3 + + + OSC32K + OSC32K oscillator output + 4 + + + XOSC32K + XOSC32K oscillator output + 5 + + + OSC48M + OSC48M oscillator output + 6 + + + DPLL96M + DPLL96M output + 7 + + + + + GENEN + Generic Clock Generator Enable + 8 + 1 + + + IDC + Improve Duty Cycle + 9 + 1 + + + OOV + Output Off Value + 10 + 1 + + + OE + Output Enable + 11 + 1 + + + DIVSEL + Divide Selection + 12 + 1 + + DIVSELSelect + + DIV1 + Divide input directly by divider factor + 0x0 + + + DIV2 + Divide input by 2^(divider factor+ 1) + 0x1 + + + + + RUNSTDBY + Run in Standby + 13 + 1 + + + DIV + Division Factor + 16 + 16 + + + + + 41 + 4 + PCHCTRL[%s] + Peripheral Clock Control + 0x80 + 32 + 0x00000000 + + + GEN + Generic Clock Generator + 0 + 4 + + GENSelect + + GCLK0 + Generic clock generator 0 + 0x0 + + + GCLK1 + Generic clock generator 1 + 0x1 + + + GCLK2 + Generic clock generator 2 + 0x2 + + + GCLK3 + Generic clock generator 3 + 0x3 + + + GCLK4 + Generic clock generator 4 + 0x4 + + + GCLK5 + Generic clock generator 5 + 0x5 + + + GCLK6 + Generic clock generator 6 + 0x6 + + + GCLK7 + Generic clock generator 7 + 0x7 + + + GCLK8 + Generic clock generator 8 + 0x8 + + + + + CHEN + Channel Enable + 6 + 1 + + + WRTLOCK + Write Lock + 7 + 1 + + + + + + + HMATRIXHS + I76382.1.3 + HSB Matrix + HMATRIXB + HMATRIXB_ + 0x4100A000 + + 0 + 0x168 + registers + + + + 16 + 4 + MCFG[%s] + Master Configuration + 0x0 + 32 + 0x00000002 + + + ULBT + Undefined Length Burst Type + 0 + 3 + + ULBTSelect + + INFINITE + Infinite Length + 0 + + + SINGLE + Single Access + 1 + + + FOUR_BEAT + Four Beat Burst + 2 + + + EIGHT_BEAT + Eight Beat Burst + 3 + + + SIXTEEN_BEAT + Sixteen Beat Burst + 4 + + + + + + + 16 + 4 + SCFG[%s] + Slave Configuration + 0x40 + 32 + 0x00000010 + + + SLOT_CYCLE + Maximum Number of Allowed Cycles for a Burst + 0 + 8 + + + DEFMSTR_TYPE + Default Master Type + 16 + 2 + + DEFMSTR_TYPESelect + + NO_DEFAULT + No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. + 0 + + + LAST_DEFAULT + Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. + 1 + + + FIXED_DEFAULT + Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave. + 2 + + + + + FIXED_DEFMSTR + Fixed Index of Default Master + 18 + 4 + + + ARBT + Arbitration Type + 24 + 1 + + ARBTSelect + + ROUND_ROBIN + Round-Robin Arbitration + 0 + + + FIXED_PRIORITY + Fixed Priority Arbitration + 1 + + + + + + + 4 + 0x8 + PRS[%s] + + 0x080 + + PRAS + Priority A for Slave + 0x0 + 32 + 0x00000000 + + + M0PR + Master 0 Priority + 0 + 4 + + + M1PR + Master 1 Priority + 4 + 4 + + + M2PR + Master 2 Priority + 8 + 4 + + + M3PR + Master 3 Priority + 12 + 4 + + + M4PR + Master 4 Priority + 16 + 4 + + + M5PR + Master 5 Priority + 20 + 4 + + + M6PR + Master 6 Priority + 24 + 4 + + + M7PR + Master 7 Priority + 28 + 4 + + + + + PRBS + Priority B for Slave + 0x4 + 32 + 0x00000000 + + + M8PR + Master 8 Priority + 0 + 4 + + + M9PR + Master 9 Priority + 4 + 4 + + + M10PR + Master 10 Priority + 8 + 4 + + + M11PR + Master 11 Priority + 12 + 4 + + + M12PR + Master 12 Priority + 16 + 4 + + + M13PR + Master 13 Priority + 20 + 4 + + + M14PR + Master 14 Priority + 24 + 4 + + + M15PR + Master 15 Priority + 28 + 4 + + + + + + MRCR + Master Remap Control + 0x100 + 32 + 0x00000000 + + + RCB0 + Remap Command Bit for Master 0 + 0 + 1 + + RCB0Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB1 + Remap Command Bit for Master 1 + 1 + 1 + + RCB1Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB2 + Remap Command Bit for Master 2 + 2 + 1 + + RCB2Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB3 + Remap Command Bit for Master 3 + 3 + 1 + + RCB3Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB4 + Remap Command Bit for Master 4 + 4 + 1 + + RCB4Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB5 + Remap Command Bit for Master 5 + 5 + 1 + + RCB5Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB6 + Remap Command Bit for Master 6 + 6 + 1 + + RCB6Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB7 + Remap Command Bit for Master 7 + 7 + 1 + + RCB7Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB8 + Remap Command Bit for Master 8 + 8 + 1 + + RCB8Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB9 + Remap Command Bit for Master 9 + 9 + 1 + + RCB9Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB10 + Remap Command Bit for Master 10 + 10 + 1 + + RCB10Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB11 + Remap Command Bit for Master 11 + 11 + 1 + + RCB11Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB12 + Remap Command Bit for Master 12 + 12 + 1 + + RCB12Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB13 + Remap Command Bit for Master 13 + 13 + 1 + + RCB13Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB14 + Remap Command Bit for Master 14 + 14 + 1 + + RCB14Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB15 + Remap Command Bit for Master 15 + 15 + 1 + + RCB15Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + + + 16 + 4 + SFR[%s] + Special Function + 0x110 + 32 + 0x00000000 + + + SFR + Special Function Register + 0 + 32 + + + + + + + MCLK + U22342.0.0 + Main Clock + MCLK + MCLK_ + 0x40000800 + + 0 + 0x20 + registers + + + + INTENCLR + Interrupt Enable Clear + 0x1 + 8 + 0x00 + + + CKRDY + Clock Ready Interrupt Enable + 0 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x2 + 8 + 0x00 + + + CKRDY + Clock Ready Interrupt Enable + 0 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x3 + 8 + 0x01 + + + CKRDY + Clock Ready + 0 + 1 + + + + + CPUDIV + CPU Clock Division + 0x4 + 8 + 0x01 + + + CPUDIV + CPU Clock Division Factor + 0 + 8 + + CPUDIVSelect + + DIV1 + Divide by 1 + 0x01 + + + DIV2 + Divide by 2 + 0x02 + + + DIV4 + Divide by 4 + 0x04 + + + DIV8 + Divide by 8 + 0x08 + + + DIV16 + Divide by 16 + 0x10 + + + DIV32 + Divide by 32 + 0x20 + + + DIV64 + Divide by 64 + 0x40 + + + DIV128 + Divide by 128 + 0x80 + + + + + + + AHBMASK + AHB Mask + 0x10 + 32 + 0x00001CFF + + + HPB0_ + HPB0 AHB Clock Mask + 0 + 1 + + + HPB1_ + HPB1 AHB Clock Mask + 1 + 1 + + + HPB2_ + HPB2 AHB Clock Mask + 2 + 1 + + + DSU_ + DSU AHB Clock Mask + 3 + 1 + + + HMATRIXHS_ + HMATRIXHS AHB Clock Mask + 4 + 1 + + + NVMCTRL_ + NVMCTRL AHB Clock Mask + 5 + 1 + + + HSRAM_ + HSRAM AHB Clock Mask + 6 + 1 + + + DMAC_ + DMAC AHB Clock Mask + 7 + 1 + + + PAC_ + PAC AHB Clock Mask + 10 + 1 + + + NVMCTRL_PICACHU_ + NVMCTRL_PICACHU AHB Clock Mask + 11 + 1 + + + DIVAS_ + DIVAS AHB Clock Mask + 12 + 1 + + + + + APBAMASK + APBA Mask + 0x14 + 32 + 0x00000FFF + + + PAC_ + PAC APB Clock Enable + 0 + 1 + + + PM_ + PM APB Clock Enable + 1 + 1 + + + MCLK_ + MCLK APB Clock Enable + 2 + 1 + + + RSTC_ + RSTC APB Clock Enable + 3 + 1 + + + OSCCTRL_ + OSCCTRL APB Clock Enable + 4 + 1 + + + OSC32KCTRL_ + OSC32KCTRL APB Clock Enable + 5 + 1 + + + SUPC_ + SUPC APB Clock Enable + 6 + 1 + + + GCLK_ + GCLK APB Clock Enable + 7 + 1 + + + WDT_ + WDT APB Clock Enable + 8 + 1 + + + RTC_ + RTC APB Clock Enable + 9 + 1 + + + EIC_ + EIC APB Clock Enable + 10 + 1 + + + FREQM_ + FREQM APB Clock Enable + 11 + 1 + + + + + APBBMASK + APBB Mask + 0x18 + 32 + 0x00000007 + + + PORT_ + PORT APB Clock Enable + 0 + 1 + + + DSU_ + DSU APB Clock Enable + 1 + 1 + + + NVMCTRL_ + NVMCTRL APB Clock Enable + 2 + 1 + + + HMATRIXHS_ + HMATRIXHS APB Clock Enable + 5 + 1 + + + + + APBCMASK + APBC Mask + 0x1C + 32 + 0x00000000 + + + EVSYS_ + EVSYS APB Clock Enable + 0 + 1 + + + SERCOM0_ + SERCOM0 APB Clock Enable + 1 + 1 + + + SERCOM1_ + SERCOM1 APB Clock Enable + 2 + 1 + + + SERCOM2_ + SERCOM2 APB Clock Enable + 3 + 1 + + + SERCOM3_ + SERCOM3 APB Clock Enable + 4 + 1 + + + TCC0_ + TCC0 APB Clock Enable + 9 + 1 + + + TCC1_ + TCC1 APB Clock Enable + 10 + 1 + + + TCC2_ + TCC2 APB Clock Enable + 11 + 1 + + + TC0_ + TC0 APB Clock Enable + 12 + 1 + + + TC1_ + TC1 APB Clock Enable + 13 + 1 + + + TC2_ + TC2 APB Clock Enable + 14 + 1 + + + TC3_ + TC3 APB Clock Enable + 15 + 1 + + + TC4_ + TC4 APB Clock Enable + 16 + 1 + + + ADC0_ + ADC0 APB Clock Enable + 17 + 1 + + + AC_ + AC APB Clock Enable + 20 + 1 + + + PTC_ + PTC APB Clock Enable + 22 + 1 + + + CCL_ + CCL APB Clock Enable + 23 + 1 + + + + + + + MTB + U20021.0.0 + Cortex-M0+ Micro-Trace Buffer + MTB + MTB_ + 0x41008000 + + 0 + 0x1000 + registers + + + + POSITION + MTB Position + 0x0 + 32 + + + WRAP + Pointer Value Wraps + 2 + 1 + + + POINTER + Trace Packet Location Pointer + 3 + 29 + + + + + MASTER + MTB Master + 0x4 + 32 + 0x00000000 + + + MASK + Maximum Value of the Trace Buffer in SRAM + 0 + 5 + + + TSTARTEN + Trace Start Input Enable + 5 + 1 + + + TSTOPEN + Trace Stop Input Enable + 6 + 1 + + + SFRWPRIV + Special Function Register Write Privilege + 7 + 1 + + + RAMPRIV + SRAM Privilege + 8 + 1 + + + HALTREQ + Halt Request + 9 + 1 + + + EN + Main Trace Enable + 31 + 1 + + + + + FLOW + MTB Flow + 0x8 + 32 + 0x00000000 + + + AUTOSTOP + Auto Stop Tracing + 0 + 1 + + + AUTOHALT + Auto Halt Request + 1 + 1 + + + WATERMARK + Watermark value + 3 + 29 + + + + + BASE + MTB Base + 0xC + 32 + read-only + + + ITCTRL + MTB Integration Mode Control + 0xF00 + 32 + + + CLAIMSET + MTB Claim Set + 0xFA0 + 32 + + + CLAIMCLR + MTB Claim Clear + 0xFA4 + 32 + + + LOCKACCESS + MTB Lock Access + 0xFB0 + 32 + + + LOCKSTATUS + MTB Lock Status + 0xFB4 + 32 + read-only + + + AUTHSTATUS + MTB Authentication Status + 0xFB8 + 32 + read-only + + + DEVARCH + MTB Device Architecture + 0xFBC + 32 + read-only + + + DEVID + MTB Device Configuration + 0xFC8 + 32 + read-only + + + DEVTYPE + MTB Device Type + 0xFCC + 32 + read-only + + + PID4 + Peripheral Identification 4 + 0xFD0 + 32 + read-only + + + PID5 + Peripheral Identification 5 + 0xFD4 + 32 + read-only + + + PID6 + Peripheral Identification 6 + 0xFD8 + 32 + read-only + + + PID7 + Peripheral Identification 7 + 0xFDC + 32 + read-only + + + PID0 + Peripheral Identification 0 + 0xFE0 + 32 + read-only + + + PID1 + Peripheral Identification 1 + 0xFE4 + 32 + read-only + + + PID2 + Peripheral Identification 2 + 0xFE8 + 32 + read-only + + + PID3 + Peripheral Identification 3 + 0xFEC + 32 + read-only + + + CID0 + Component Identification 0 + 0xFF0 + 32 + read-only + + + CID1 + Component Identification 1 + 0xFF4 + 32 + read-only + + + CID2 + Component Identification 2 + 0xFF8 + 32 + read-only + + + CID3 + Component Identification 3 + 0xFFC + 32 + read-only + + + + + NVMCTRL + U22074.0.1.1 + Non-Volatile Memory Controller + NVMCTRL + NVMCTRL_ + 0x41004000 + + 0 + 0x30 + registers + + + NVMCTRL + 6 + + + + CTRLA + Control A + 0x0 + 16 + 0x0000 + + + CMD + Command + 0 + 7 + + CMDSelect + + ER + Erase Row - Erases the row addressed by the ADDR register. + 0x02 + + + WP + Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. + 0x04 + + + EAR + Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. + 0x05 + + + WAP + Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. + 0x06 + + + SF + Security Flow Command + 0x0A + + + WL + Write lockbits + 0x0F + + + RWWEEER + RWW EEPROM area Erase Row - Erases the row addressed by the ADDR register. + 0x1A + + + RWWEEWP + RWW EEPROM Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. + 0x1C + + + LR + Lock Region - Locks the region containing the address location in the ADDR register. + 0x40 + + + UR + Unlock Region - Unlocks the region containing the address location in the ADDR register. + 0x41 + + + SPRM + Sets the power reduction mode. + 0x42 + + + CPRM + Clears the power reduction mode. + 0x43 + + + PBC + Page Buffer Clear - Clears the page buffer. + 0x44 + + + SSB + Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row. + 0x45 + + + INVALL + Invalidate all cache lines. + 0x46 + + + + + CMDEX + Command Execution + 8 + 8 + + CMDEXSelect + + KEY + Execution Key + 0xA5 + + + + + + + CTRLB + Control B + 0x4 + 32 + 0x00000080 + + + RWS + NVM Read Wait States + 1 + 4 + + RWSSelect + + SINGLE + Single Auto Wait State + 0 + + + HALF + Half Auto Wait State + 1 + + + DUAL + Dual Auto Wait State + 2 + + + + + MANW + Manual Write + 7 + 1 + + + SLEEPPRM + Power Reduction Mode during Sleep + 8 + 2 + + SLEEPPRMSelect + + WAKEONACCESS + NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access. + 0 + + + WAKEUPINSTANT + NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep. + 1 + + + DISABLED + Auto power reduction disabled. + 3 + + + + + READMODE + NVMCTRL Read Mode + 16 + 2 + + READMODESelect + + NO_MISS_PENALTY + The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance. + 0x0 + + + LOW_POWER + Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time. + 0x1 + + + DETERMINISTIC + The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings. + 0x2 + + + + + CACHEDIS + Cache Disable + 18 + 2 + + + + + PARAM + NVM Parameter + 0x8 + 32 + 0x00000000 + + + NVMP + NVM Pages + 0 + 16 + + + PSZ + Page Size + 16 + 3 + + PSZSelect + + 8 + 8 bytes + 0x0 + + + 16 + 16 bytes + 0x1 + + + 32 + 32 bytes + 0x2 + + + 64 + 64 bytes + 0x3 + + + 128 + 128 bytes + 0x4 + + + 256 + 256 bytes + 0x5 + + + 512 + 512 bytes + 0x6 + + + 1024 + 1024 bytes + 0x7 + + + + + RWWEEP + RWW EEPROM Pages + 20 + 12 + + + + + INTENCLR + Interrupt Enable Clear + 0xC + 8 + 0x00 + + + READY + NVM Ready Interrupt Enable + 0 + 1 + + + ERROR + Error Interrupt Enable + 1 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x10 + 8 + 0x00 + + + READY + NVM Ready Interrupt Enable + 0 + 1 + + + ERROR + Error Interrupt Enable + 1 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x14 + 8 + 0x00 + + + READY + NVM Ready + 0 + 1 + + + ERROR + Error + 1 + 1 + + + + + STATUS + Status + 0x18 + 16 + 0x0000 + + + PRM + Power Reduction Mode + 0 + 1 + + + LOAD + NVM Page Buffer Active Loading + 1 + 1 + + + PROGE + Programming Error Status + 2 + 1 + + + LOCKE + Lock Error Status + 3 + 1 + + + NVME + NVM Error + 4 + 1 + + + SB + Security Bit Status + 8 + 1 + + + + + ADDR + Address + 0x1C + 32 + 0x00000000 + + + ADDR + NVM Address + 0 + 22 + + + + + LOCK + Lock Section + 0x20 + 16 + 0x0000 + + + LOCK + Region Lock Bits + 0 + 16 + + + + + PBLDATA0 + Page Buffer Load Data 0 + 0x28 + 32 + read-only + 0x00000000 + + + PBLDATA1 + Page Buffer Load Data 1 + 0x2C + 32 + read-only + 0x00000000 + + + + + OSCCTRL + U21192.1.0 + Oscillators Control + OSCCTRL + OSCCTRL_ + 0x40001000 + + 0 + 0x3C + registers + + + + INTENCLR + Interrupt Enable Clear + 0x0 + 32 + 0x00000000 + + + XOSCRDY + XOSC Ready Interrupt Enable + 0 + 1 + + + XOSCFAIL + XOSC Clock Failure Detector Interrupt Enable + 1 + 1 + + + OSC48MRDY + OSC48M Ready Interrupt Enable + 4 + 1 + + + DPLLLCKR + DPLL Lock Rise Interrupt Enable + 8 + 1 + + + DPLLLCKF + DPLL Lock Fall Interrupt Enable + 9 + 1 + + + DPLLLTO + DPLL Time Out Interrupt Enable + 10 + 1 + + + DPLLLDRTO + DPLL Ratio Ready Interrupt Enable + 11 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x4 + 32 + 0x00000000 + + + XOSCRDY + XOSC Ready Interrupt Enable + 0 + 1 + + + XOSCFAIL + XOSC Clock Failure Detector Interrupt Enable + 1 + 1 + + + OSC48MRDY + OSC48M Ready Interrupt Enable + 4 + 1 + + + DPLLLCKR + DPLL Lock Rise Interrupt Enable + 8 + 1 + + + DPLLLCKF + DPLL Lock Fall Interrupt Enable + 9 + 1 + + + DPLLLTO + DPLL Time Out Interrupt Enable + 10 + 1 + + + DPLLLDRTO + DPLL Ratio Ready Interrupt Enable + 11 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x8 + 32 + 0x00000000 + + + XOSCRDY + XOSC Ready + 0 + 1 + + + XOSCFAIL + XOSC Clock Failure Detector + 1 + 1 + + + OSC48MRDY + OSC48M Ready + 4 + 1 + + + DPLLLCKR + DPLL Lock Rise + 8 + 1 + + + DPLLLCKF + DPLL Lock Fall + 9 + 1 + + + DPLLLTO + DPLL Timeout + 10 + 1 + + + DPLLLDRTO + DPLL Ratio Ready + 11 + 1 + + + + + STATUS + Power and Clocks Status + 0xC + 32 + read-only + 0x00000000 + + + XOSCRDY + XOSC Ready + 0 + 1 + + + XOSCFAIL + XOSC Clock Failure Detector + 1 + 1 + + + XOSCCKSW + XOSC Clock Switch + 2 + 1 + + + OSC48MRDY + OSC48M Ready + 4 + 1 + + + DPLLLCKR + DPLL Lock Rise + 8 + 1 + + + DPLLLCKF + DPLL Lock Fall + 9 + 1 + + + DPLLTO + DPLL Timeout + 10 + 1 + + + DPLLLDRTO + DPLL Ratio Ready + 11 + 1 + + + + + XOSCCTRL + External Multipurpose Crystal Oscillator (XOSC) Control + 0x10 + 16 + 0x0080 + + + ENABLE + Oscillator Enable + 1 + 1 + + + XTALEN + Crystal Oscillator Enable + 2 + 1 + + + CFDEN + Xosc Clock Failure Detector Enable + 3 + 1 + + + SWBEN + Xosc Clock Switch Enable + 4 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + GAIN + Oscillator Gain + 8 + 3 + + GAINSelect + + GAIN2 + 2 MHz + 0 + + + GAIN4 + 4 MHz + 1 + + + GAIN8 + 8 MHz + 2 + + + GAIN16 + 16 MHz + 3 + + + GAIN30 + 30 MHz + 4 + + + + + AMPGC + Automatic Amplitude Gain Control + 11 + 1 + + + STARTUP + Start-Up Time + 12 + 4 + + STARTUPSelect + + CYCLE1 + 31 us + 0 + + + CYCLE2 + 61 us + 1 + + + CYCLE4 + 122 us + 2 + + + CYCLE8 + 244 us + 3 + + + CYCLE16 + 488 us + 4 + + + CYCLE32 + 977 us + 5 + + + CYCLE64 + 1953 us + 6 + + + CYCLE128 + 3906 us + 7 + + + CYCLE256 + 7813 us + 8 + + + CYCLE512 + 15625 us + 9 + + + CYCLE1024 + 31250 us + 10 + + + CYCLE2048 + 62500 us + 11 + + + CYCLE4096 + 125000 us + 12 + + + CYCLE8192 + 250000 us + 13 + + + CYCLE16384 + 500000 us + 14 + + + CYCLE32768 + 1000000 us + 15 + + + + + + + CFDPRESC + Clock Failure Detector Prescaler + 0x12 + 8 + 0x00 + + + CFDPRESC + Clock Failure Detector Prescaler + 0 + 3 + + CFDPRESCSelect + + DIV1 + 48 MHz + 0 + + + DIV2 + 24 MHz + 1 + + + DIV4 + 12 MHz + 2 + + + DIV8 + 6 MHz + 3 + + + DIV16 + 3 MHz + 4 + + + DIV32 + 1.5 MHz + 5 + + + DIV64 + 0.75 MHz + 6 + + + DIV128 + 0.3125 MHz + 7 + + + + + + + EVCTRL + Event Control + 0x13 + 8 + 0x00 + + + CFDEO + Clock Failure Detector Event Output Enable + 0 + 1 + + + + + OSC48MCTRL + 48MHz Internal Oscillator (OSC48M) Control + 0x14 + 8 + 0x82 + + + ENABLE + Oscillator Enable + 1 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + + + OSC48MDIV + OSC48M Divider + 0x15 + 8 + 0x0B + + + DIV + OSC48M Division Factor + 0 + 4 + + DIVSelect + + DIV1 + 48 MHz + 0 + + + DIV2 + 24 MHz + 1 + + + DIV3 + 16 MHz + 2 + + + DIV4 + 12 MHz + 3 + + + DIV5 + 9.6 MHz + 4 + + + DIV6 + 8 MHz + 5 + + + DIV7 + 6.86 MHz + 6 + + + DIV8 + 6 MHz + 7 + + + DIV9 + 5.33 MHz + 8 + + + DIV10 + 4.8 MHz + 9 + + + DIV11 + 4.36 MHz + 10 + + + DIV12 + 4 MHz + 11 + + + DIV13 + 3.69 MHz + 12 + + + DIV14 + 3.43 MHz + 13 + + + DIV15 + 3.2 MHz + 14 + + + DIV16 + 3 MHz + 15 + + + + + + + OSC48MSTUP + OSC48M Startup Time + 0x16 + 8 + 0x07 + + + STARTUP + Startup Time + 0 + 3 + + STARTUPSelect + + CYCLE8 + 166 ns + 0 + + + CYCLE16 + 333 ns + 1 + + + CYCLE32 + 667 ns + 2 + + + CYCLE64 + 1.333 us + 3 + + + CYCLE128 + 2.667 us + 4 + + + CYCLE256 + 5.333 us + 5 + + + CYCLE512 + 10.667 us + 6 + + + CYCLE1024 + 21.333 us + 7 + + + + + + + OSC48MSYNCBUSY + OSC48M Synchronization Busy + 0x18 + 32 + read-only + 0x00000000 + + + OSC48MDIV + OSC48MDIV Synchronization Status + 2 + 1 + + + + + DPLLCTRLA + DPLL Control + 0x1C + 8 + 0x80 + + + ENABLE + Enable + 1 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand + 7 + 1 + + + + + DPLLRATIO + DPLL Ratio Control + 0x20 + 32 + 0x00000000 + + + LDR + Loop Divider Ratio + 0 + 12 + + + LDRFRAC + Loop Divider Ratio Fractional Part + 16 + 4 + + + + + DPLLCTRLB + Digital Core Configuration + 0x24 + 32 + 0x00000000 + + + FILTER + Proportional Integral Filter Selection + 0 + 2 + + FILTERSelect + + DEFAULT + Default filter mode + 0 + + + LBFILT + Low bandwidth filter + 1 + + + HBFILT + High bandwidth filter + 2 + + + HDFILT + High damping filter + 3 + + + + + LPEN + Low-Power Enable + 2 + 1 + + + WUF + Wake Up Fast + 3 + 1 + + + REFCLK + Reference Clock Selection + 4 + 2 + + REFCLKSelect + + XOSC32K + XOSC32K clock reference + 0 + + + XOSC + XOSC clock reference + 1 + + + GCLK + GCLK clock reference + 2 + + + + + LTIME + Lock Time + 8 + 3 + + LTIMESelect + + DEFAULT + No time-out. Automatic lock. + 0 + + + 8MS + Time-out if no lock within 8ms + 4 + + + 9MS + Time-out if no lock within 9ms + 5 + + + 10MS + Time-out if no lock within 10ms + 6 + + + 11MS + Time-out if no lock within 11ms + 7 + + + + + LBYPASS + Lock Bypass + 12 + 1 + + + DIV + Clock Divider + 16 + 11 + + + + + DPLLPRESC + DPLL Prescaler + 0x28 + 8 + 0x00 + + + PRESC + Output Clock Prescaler + 0 + 2 + + PRESCSelect + + DIV1 + DPLL output is divided by 1 + 0 + + + DIV2 + DPLL output is divided by 2 + 1 + + + DIV4 + DPLL output is divided by 4 + 2 + + + + + + + DPLLSYNCBUSY + DPLL Synchronization Busy + 0x2C + 8 + read-only + 0x00 + + + ENABLE + DPLL Enable Synchronization Status + 1 + 1 + + + DPLLRATIO + DPLL Ratio Synchronization Status + 2 + 1 + + + DPLLPRESC + DPLL Prescaler Synchronization Status + 3 + 1 + + + + + DPLLSTATUS + DPLL Status + 0x30 + 8 + read-only + 0x00 + + + LOCK + DPLL Lock Status + 0 + 1 + + + CLKRDY + DPLL Clock Ready + 1 + 1 + + + + + CAL48M + 48MHz Oscillator Calibration + 0x38 + 32 + 0x00000000 + + + FCAL + Frequency Calibration (48MHz) + 0 + 6 + + + FRANGE + Frequency Range (48MHz) + 8 + 2 + + + TCAL + Temperature Calibration (48MHz) + 16 + 6 + + + + + + + OSC32KCTRL + U22462.1.0 + 32k Oscillators Control + OSC32KCTRL + OSC32KCTRL_ + 0x40001400 + + 0 + 0x20 + registers + + + + INTENCLR + Interrupt Enable Clear + 0x0 + 32 + 0x00000000 + + + XOSC32KRDY + XOSC32K Ready Interrupt Enable + 0 + 1 + + + OSC32KRDY + OSC32K Ready Interrupt Enable + 1 + 1 + + + CLKFAIL + XOSC32K Clock Failure Detector Interrupt Enable + 2 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x4 + 32 + 0x00000000 + + + XOSC32KRDY + XOSC32K Ready Interrupt Enable + 0 + 1 + + + OSC32KRDY + OSC32K Ready Interrupt Enable + 1 + 1 + + + CLKFAIL + XOSC32K Clock Failure Detector Interrupt Enable + 2 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x8 + 32 + 0x00000000 + + + XOSC32KRDY + XOSC32K Ready + 0 + 1 + + + OSC32KRDY + OSC32K Ready + 1 + 1 + + + CLKFAIL + XOSC32K Clock Failure Detector + 2 + 1 + + + + + STATUS + Power and Clocks Status + 0xC + 32 + read-only + 0x00000000 + + + XOSC32KRDY + XOSC32K Ready + 0 + 1 + + + OSC32KRDY + OSC32K Ready + 1 + 1 + + + CLKFAIL + XOSC32K Clock Failure Detector + 2 + 1 + + + CLKSW + XOSC32K Clock switch + 3 + 1 + + + + + RTCCTRL + Clock selection + 0x10 + 32 + 0x00000000 + + + RTCSEL + RTC Clock Selection + 0 + 3 + + RTCSELSelect + + ULP1K + 1.024kHz from 32kHz internal ULP oscillator + 0 + + + ULP32K + 32.768kHz from 32kHz internal ULP oscillator + 1 + + + OSC1K + 1.024kHz from 32.768kHz internal oscillator + 2 + + + OSC32K + 32.768kHz from 32.768kHz internal oscillator + 3 + + + XOSC1K + 1.024kHz from 32.768kHz internal oscillator + 4 + + + XOSC32K + 32.768kHz from 32.768kHz external crystal oscillator + 5 + + + + + + + XOSC32K + 32kHz External Crystal Oscillator (XOSC32K) Control + 0x14 + 16 + 0x0080 + + + ENABLE + Oscillator Enable + 1 + 1 + + + XTALEN + Crystal Oscillator Enable + 2 + 1 + + + EN32K + 32kHz Output Enable + 3 + 1 + + + EN1K + 1kHz Output Enable + 4 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + STARTUP + Oscillator Start-Up Time + 8 + 3 + + STARTUPSelect + + CYCLE1 + 0.122 ms + 0 + + + CYCLE32 + 1.068 ms + 1 + + + CYCLE2048 + 62.6 ms + 2 + + + CYCLE4096 + 125 ms + 3 + + + CYCLE16384 + 500 ms + 4 + + + CYCLE32768 + 1000 ms + 5 + + + CYCLE65536 + 2000 ms + 6 + + + CYCLE131072 + 4000 ms + 7 + + + + + WRTLOCK + Write Lock + 12 + 1 + + + + + CFDCTRL + Clock Failure Detector Control + 0x16 + 8 + 0x00 + + + CFDEN + Clock Failure Detector Enable + 0 + 1 + + + SWBACK + Clock Switch Back + 1 + 1 + + + CFDPRESC + Clock Failure Detector Prescaler + 2 + 1 + + + + + EVCTRL + Event Control + 0x17 + 8 + 0x00 + + + CFDEO + Clock Failure Detector Event Output Enable + 0 + 1 + + + + + OSC32K + 32kHz Internal Oscillator (OSC32K) Control + 0x18 + 32 + 0x003F0080 + + + ENABLE + Oscillator Enable + 1 + 1 + + + EN32K + 32kHz Output Enable + 2 + 1 + + + EN1K + 1kHz Output Enable + 3 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + STARTUP + Oscillator Start-Up Time + 8 + 3 + + STARTUPSelect + + CYCLE3 + 0.092 ms + 0 + + + CYCLE4 + 0.122 ms + 1 + + + CYCLE6 + 0.183 ms + 2 + + + CYCLE10 + 0.305 ms + 3 + + + CYCLE18 + 0.549 ms + 4 + + + CYCLE34 + 1.038 ms + 5 + + + CYCLE66 + 2.014 ms + 6 + + + CYCLE130 + 3.967 ms + 7 + + + + + WRTLOCK + Write Lock + 12 + 1 + + + CALIB + Oscillator Calibration + 16 + 7 + + + + + OSCULP32K + 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control + 0x1C + 32 + + + CALIB + Oscillator Calibration + 8 + 5 + + + WRTLOCK + Write Lock + 15 + 1 + + + + + + + PAC + U21201.1.0 + Peripheral Access Controller + PAC + PAC_ + 0x40000000 + + 0 + 0x40 + registers + + + + WRCTRL + Write control + 0x0 + 32 + 0x00000000 + + + PERID + Peripheral identifier + 0 + 16 + + + KEY + Peripheral access control key + 16 + 8 + + KEYSelect + + OFF + No action + 0 + + + CLR + Clear protection + 1 + + + SET + Set protection + 2 + + + SETLCK + Set and lock protection + 3 + + + + + + + EVCTRL + Event control + 0x4 + 8 + 0x00 + + + ERREO + Peripheral acess error event output + 0 + 1 + + + + + INTENCLR + Interrupt enable clear + 0x8 + 8 + 0x00 + + + ERR + Peripheral access error interrupt disable + 0 + 1 + + + + + INTENSET + Interrupt enable set + 0x9 + 8 + 0x00 + + + ERR + Peripheral access error interrupt enable + 0 + 1 + + + + + INTFLAGAHB + Bridge interrupt flag status + 0x10 + 32 + 0x00000000 + + + FLASH_ + FLASH + 0 + 1 + + + HSRAMCM0P_ + HSRAMCM0P + 1 + 1 + + + HSRAMDSU_ + HSRAMDSU + 2 + 1 + + + HPB1_ + HPB1 + 3 + 1 + + + HPB0_ + HPB0 + 4 + 1 + + + HPB2_ + HPB2 + 5 + 1 + + + LPRAMDMAC_ + LPRAMDMAC + 6 + 1 + + + DIVAS_ + DIVAS + 7 + 1 + + + + + INTFLAGA + Peripheral interrupt flag status - Bridge A + 0x14 + 32 + 0x00000000 + + + PAC_ + PAC + 0 + 1 + + + PM_ + PM + 1 + 1 + + + MCLK_ + MCLK + 2 + 1 + + + RSTC_ + RSTC + 3 + 1 + + + OSCCTRL_ + OSCCTRL + 4 + 1 + + + OSC32KCTRL_ + OSC32KCTRL + 5 + 1 + + + SUPC_ + SUPC + 6 + 1 + + + GCLK_ + GCLK + 7 + 1 + + + WDT_ + WDT + 8 + 1 + + + RTC_ + RTC + 9 + 1 + + + EIC_ + EIC + 10 + 1 + + + FREQM_ + FREQM + 11 + 1 + + + + + INTFLAGB + Peripheral interrupt flag status - Bridge B + 0x18 + 32 + 0x00000000 + + + PORT_ + PORT + 0 + 1 + + + DSU_ + DSU + 1 + 1 + + + NVMCTRL_ + NVMCTRL + 2 + 1 + + + DMAC_ + DMAC + 3 + 1 + + + MTB_ + MTB + 4 + 1 + + + HMATRIXHS_ + HMATRIXHS + 5 + 1 + + + + + INTFLAGC + Peripheral interrupt flag status - Bridge C + 0x1C + 32 + 0x00000000 + + + EVSYS_ + EVSYS + 0 + 1 + + + SERCOM0_ + SERCOM0 + 1 + 1 + + + SERCOM1_ + SERCOM1 + 2 + 1 + + + SERCOM2_ + SERCOM2 + 3 + 1 + + + SERCOM3_ + SERCOM3 + 4 + 1 + + + TCC0_ + TCC0 + 9 + 1 + + + TCC1_ + TCC1 + 10 + 1 + + + TCC2_ + TCC2 + 11 + 1 + + + TC0_ + TC0 + 12 + 1 + + + TC1_ + TC1 + 13 + 1 + + + TC2_ + TC2 + 14 + 1 + + + TC3_ + TC3 + 15 + 1 + + + TC4_ + TC4 + 16 + 1 + + + ADC0_ + ADC0 + 17 + 1 + + + AC_ + AC + 20 + 1 + + + PTC_ + PTC + 22 + 1 + + + CCL_ + CCL + 23 + 1 + + + + + STATUSA + Peripheral write protection status - Bridge A + 0x34 + 32 + read-only + 0x00000000 + + + PAC_ + PAC APB Protect Enable + 0 + 1 + + + PM_ + PM APB Protect Enable + 1 + 1 + + + MCLK_ + MCLK APB Protect Enable + 2 + 1 + + + RSTC_ + RSTC APB Protect Enable + 3 + 1 + + + OSCCTRL_ + OSCCTRL APB Protect Enable + 4 + 1 + + + OSC32KCTRL_ + OSC32KCTRL APB Protect Enable + 5 + 1 + + + SUPC_ + SUPC APB Protect Enable + 6 + 1 + + + GCLK_ + GCLK APB Protect Enable + 7 + 1 + + + WDT_ + WDT APB Protect Enable + 8 + 1 + + + RTC_ + RTC APB Protect Enable + 9 + 1 + + + EIC_ + EIC APB Protect Enable + 10 + 1 + + + FREQM_ + FREQM APB Protect Enable + 11 + 1 + + + + + STATUSB + Peripheral write protection status - Bridge B + 0x38 + 32 + read-only + 0x00000002 + + + PORT_ + PORT APB Protect Enable + 0 + 1 + + + DSU_ + DSU APB Protect Enable + 1 + 1 + + + NVMCTRL_ + NVMCTRL APB Protect Enable + 2 + 1 + + + DMAC_ + DMAC APB Protect Enable + 3 + 1 + + + MTB_ + MTB APB Protect Enable + 4 + 1 + + + HMATRIXHS_ + HMATRIXHS APB Protect Enable + 5 + 1 + + + + + STATUSC + Peripheral write protection status - Bridge C + 0x3C + 32 + read-only + 0x02000000 + + + EVSYS_ + EVSYS APB Protect Enable + 0 + 1 + + + SERCOM0_ + SERCOM0 APB Protect Enable + 1 + 1 + + + SERCOM1_ + SERCOM1 APB Protect Enable + 2 + 1 + + + SERCOM2_ + SERCOM2 APB Protect Enable + 3 + 1 + + + SERCOM3_ + SERCOM3 APB Protect Enable + 4 + 1 + + + TCC0_ + TCC0 APB Protect Enable + 9 + 1 + + + TCC1_ + TCC1 APB Protect Enable + 10 + 1 + + + TCC2_ + TCC2 APB Protect Enable + 11 + 1 + + + TC0_ + TC0 APB Protect Enable + 12 + 1 + + + TC1_ + TC1 APB Protect Enable + 13 + 1 + + + TC2_ + TC2 APB Protect Enable + 14 + 1 + + + TC3_ + TC3 APB Protect Enable + 15 + 1 + + + TC4_ + TC4 APB Protect Enable + 16 + 1 + + + ADC0_ + ADC0 APB Protect Enable + 17 + 1 + + + AC_ + AC APB Protect Enable + 20 + 1 + + + PTC_ + PTC APB Protect Enable + 22 + 1 + + + CCL_ + CCL APB Protect Enable + 23 + 1 + + + + + + + PM + U22402.1.0 + Power Manager + PM + PM_ + 0x40000400 + + 0 + 0xA + registers + + + + SLEEPCFG + Sleep Configuration + 0x1 + 8 + 0x00 + + + SLEEPMODE + Sleep Mode + 0 + 3 + + SLEEPMODESelect + + IDLE0 + CPU clock is OFF + 0 + + + IDLE1 + AHB clock is OFF + 1 + + + IDLE2 + APB clock are OFF + 2 + + + STANDBY + All Clocks are OFF + 4 + + + + + + + STDBYCFG + Standby Configuration + 0x8 + 16 + 0x0400 + + + VREGSMOD + Voltage Regulator Standby mode + 6 + 2 + + VREGSMODSelect + + AUTO + Automatic mode + 0 + + + PERFORMANCE + Performance oriented + 1 + + + LP + Low Power oriented + 2 + + + + + BBIASHS + Back Bias for HMCRAMCHS + 10 + 1 + + + + + + + PORT + U22102.1.1 + Port Module + PORT + PORT_ + 0x41000000 + + 0 + 0x100 + registers + + + + 2 + 0x80 + GROUP[%s] + + 0x00 + + DIR + Data Direction + 0x0 + 32 + 0x00000000 + + + DIRCLR + Data Direction Clear + 0x4 + 32 + 0x00000000 + + + DIRSET + Data Direction Set + 0x8 + 32 + 0x00000000 + + + DIRTGL + Data Direction Toggle + 0xC + 32 + 0x00000000 + + + OUT + Data Output Value + 0x10 + 32 + 0x00000000 + + + OUTCLR + Data Output Value Clear + 0x14 + 32 + 0x00000000 + + + OUTSET + Data Output Value Set + 0x18 + 32 + 0x00000000 + + + OUTTGL + Data Output Value Toggle + 0x1C + 32 + 0x00000000 + + + IN + Data Input Value + 0x20 + 32 + read-only + 0x00000000 + + + CTRL + Control + 0x24 + 32 + 0x00000000 + + + SAMPLING + Input Sampling Mode + 0 + 32 + + + + + WRCONFIG + Write Configuration + 0x28 + 32 + write-only + 0x00000000 + + + PINMASK + Pin Mask for Multiple Pin Configuration + 0 + 16 + + + PMUXEN + Select Peripheral Multiplexer + 16 + 1 + + + INEN + Input Enable + 17 + 1 + + + PULLEN + Pull Enable + 18 + 1 + + + DRVSTR + Output Driver Strength Selection + 22 + 1 + + + PMUX + Peripheral Multiplexing Template + 24 + 4 + + + WRPMUX + Write PMUX Registers + 28 + 1 + + + WRPINCFG + Write PINCFG Registers + 30 + 1 + + + HWSEL + Half-Word Select + 31 + 1 + + + + + EVCTRL + Event Input Control + 0x2C + 32 + 0x00000000 + + + PID0 + Port Event Pin Identifier 0 + 0 + 5 + + + EVACT0 + Port Event Action 0 + 5 + 2 + + EVACT0Select + + OUT + Event output to pin + 0x0 + + + SET + Set output register of pin on event + 0x1 + + + CLR + Clear output register of pin on event + 0x2 + + + TGL + Toggle output register of pin on event + 0x3 + + + + + PORTEI0 + Port Event Enable Input 0 + 7 + 1 + + + PID1 + Port Event Pin Identifier 1 + 8 + 5 + + + EVACT1 + Port Event Action 1 + 13 + 2 + + + PORTEI1 + Port Event Enable Input 1 + 15 + 1 + + + PID2 + Port Event Pin Identifier 2 + 16 + 5 + + + EVACT2 + Port Event Action 2 + 21 + 2 + + + PORTEI2 + Port Event Enable Input 2 + 23 + 1 + + + PID3 + Port Event Pin Identifier 3 + 24 + 5 + + + EVACT3 + Port Event Action 3 + 29 + 2 + + + PORTEI3 + Port Event Enable Input 3 + 31 + 1 + + + + + 16 + 1 + PMUX[%s] + Peripheral Multiplexing n + 0x30 + 8 + 0x00 + + + PMUXE + Peripheral Multiplexing for Even-Numbered Pin + 0 + 4 + + + PMUXO + Peripheral Multiplexing for Odd-Numbered Pin + 4 + 4 + + + + + 32 + 1 + PINCFG[%s] + Pin Configuration n + 0x40 + 8 + 0x00 + + + PMUXEN + Select Peripheral Multiplexer + 0 + 1 + + + INEN + Input Enable + 1 + 1 + + + PULLEN + Pull Enable + 2 + 1 + + + DRVSTR + Output Driver Strength Selection + 6 + 1 + + + + + + + + PORT_IOBUS + PORT_IOBUS_ + 0x60000000 + + + PTC + U22153.1.0 + Peripheral Touch Controller + PTC + PTC_ + 0x42005800 + + 0 + 0x1 + reserved + + + PTC + 30 + + + + RSTC + U22392.0.2 + Reset Controller + RSTC + RSTC_ + 0x40000C00 + + 0 + 0x1 + registers + + + + RCAUSE + Reset Cause + 0x0 + 8 + read-only + + + POR + Power On Reset + 0 + 1 + + + BODCORE + Brown Out CORE Detector Reset + 1 + 1 + + + BODVDD + Brown Out VDD Detector Reset + 2 + 1 + + + EXT + External Reset + 4 + 1 + + + WDT + Watchdog Reset + 5 + 1 + + + SYST + System Reset Request + 6 + 1 + + + + + + + RTC + U22501.1.1 + Real-Time Counter + RTC + RTC_ + 0x40002400 + + 0 + 0x25 + registers + + + RTC + 2 + + + + MODE0 + 32-bit Counter with Single 32-bit Compare + RtcMode0 + 0x0 + + CTRLA + MODE0 Control A + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 2 + + MODESelect + + COUNT32 + Mode 0: 32-bit Counter + 0x0 + + + COUNT16 + Mode 1: 16-bit Counter + 0x1 + + + CLOCK + Mode 2: Clock/Calendar + 0x2 + + + + + MATCHCLR + Clear on Match + 7 + 1 + + + PRESCALER + Prescaler + 8 + 4 + + PRESCALERSelect + + OFF + CLK_RTC_CNT = GCLK_RTC/1 + 0x0 + + + DIV1 + CLK_RTC_CNT = GCLK_RTC/1 + 0x1 + + + DIV2 + CLK_RTC_CNT = GCLK_RTC/2 + 0x2 + + + DIV4 + CLK_RTC_CNT = GCLK_RTC/4 + 0x3 + + + DIV8 + CLK_RTC_CNT = GCLK_RTC/8 + 0x4 + + + DIV16 + CLK_RTC_CNT = GCLK_RTC/16 + 0x5 + + + DIV32 + CLK_RTC_CNT = GCLK_RTC/32 + 0x6 + + + DIV64 + CLK_RTC_CNT = GCLK_RTC/64 + 0x7 + + + DIV128 + CLK_RTC_CNT = GCLK_RTC/128 + 0x8 + + + DIV256 + CLK_RTC_CNT = GCLK_RTC/256 + 0x9 + + + DIV512 + CLK_RTC_CNT = GCLK_RTC/512 + 0xA + + + DIV1024 + CLK_RTC_CNT = GCLK_RTC/1024 + 0xB + + + + + COUNTSYNC + Count Read Synchronization Enable + 15 + 1 + + + + + EVCTRL + MODE0 Event Control + 0x4 + 32 + 0x00000000 + + + PEREO0 + Periodic Interval 0 Event Output Enable + 0 + 1 + + + PEREO1 + Periodic Interval 1 Event Output Enable + 1 + 1 + + + PEREO2 + Periodic Interval 2 Event Output Enable + 2 + 1 + + + PEREO3 + Periodic Interval 3 Event Output Enable + 3 + 1 + + + PEREO4 + Periodic Interval 4 Event Output Enable + 4 + 1 + + + PEREO5 + Periodic Interval 5 Event Output Enable + 5 + 1 + + + PEREO6 + Periodic Interval 6 Event Output Enable + 6 + 1 + + + PEREO7 + Periodic Interval 7 Event Output Enable + 7 + 1 + + + CMPEO0 + Compare 0 Event Output Enable + 8 + 1 + + + OVFEO + Overflow Event Output Enable + 15 + 1 + + + + + INTENCLR + MODE0 Interrupt Enable Clear + 0x8 + 16 + 0x0000 + + + PER0 + Periodic Interval 0 Interrupt Enable + 0 + 1 + + + PER1 + Periodic Interval 1 Interrupt Enable + 1 + 1 + + + PER2 + Periodic Interval 2 Interrupt Enable + 2 + 1 + + + PER3 + Periodic Interval 3 Interrupt Enable + 3 + 1 + + + PER4 + Periodic Interval 4 Interrupt Enable + 4 + 1 + + + PER5 + Periodic Interval 5 Interrupt Enable + 5 + 1 + + + PER6 + Periodic Interval 6 Interrupt Enable + 6 + 1 + + + PER7 + Periodic Interval 7 Interrupt Enable + 7 + 1 + + + CMP0 + Compare 0 Interrupt Enable + 8 + 1 + + + OVF + Overflow Interrupt Enable + 15 + 1 + + + + + INTENSET + MODE0 Interrupt Enable Set + 0xA + 16 + 0x0000 + + + PER0 + Periodic Interval 0 Interrupt Enable + 0 + 1 + + + PER1 + Periodic Interval 1 Interrupt Enable + 1 + 1 + + + PER2 + Periodic Interval 2 Interrupt Enable + 2 + 1 + + + PER3 + Periodic Interval 3 Interrupt Enable + 3 + 1 + + + PER4 + Periodic Interval 4 Interrupt Enable + 4 + 1 + + + PER5 + Periodic Interval 5 Interrupt Enable + 5 + 1 + + + PER6 + Periodic Interval 6 Interrupt Enable + 6 + 1 + + + PER7 + Periodic Interval 7 Interrupt Enable + 7 + 1 + + + CMP0 + Compare 0 Interrupt Enable + 8 + 1 + + + OVF + Overflow Interrupt Enable + 15 + 1 + + + + + INTFLAG + MODE0 Interrupt Flag Status and Clear + 0xC + 16 + 0x0000 + + + PER0 + Periodic Interval 0 + 0 + 1 + + + PER1 + Periodic Interval 1 + 1 + 1 + + + PER2 + Periodic Interval 2 + 2 + 1 + + + PER3 + Periodic Interval 3 + 3 + 1 + + + PER4 + Periodic Interval 4 + 4 + 1 + + + PER5 + Periodic Interval 5 + 5 + 1 + + + PER6 + Periodic Interval 6 + 6 + 1 + + + PER7 + Periodic Interval 7 + 7 + 1 + + + CMP0 + Compare 0 + 8 + 1 + + + OVF + Overflow + 15 + 1 + + + + + DBGCTRL + Debug Control + 0xE + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + SYNCBUSY + MODE0 Synchronization Busy Status + 0x10 + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Busy + 0 + 1 + + + ENABLE + Enable Bit Busy + 1 + 1 + + + FREQCORR + FREQCORR Register Busy + 2 + 1 + + + COUNT + COUNT Register Busy + 3 + 1 + + + COMP0 + COMP 0 Register Busy + 5 + 1 + + + COUNTSYNC + Count Read Synchronization Enable Bit Busy + 15 + 1 + + + + + FREQCORR + Frequency Correction + 0x14 + 8 + 0x00 + + + VALUE + Correction Value + 0 + 7 + + + SIGN + Correction Sign + 7 + 1 + + + + + COUNT + MODE0 Counter Value + 0x18 + 32 + 0x00000000 + + + COUNT + Counter Value + 0 + 32 + + + + + COMP + MODE0 Compare n Value + 0x20 + 32 + 0x00000000 + + + COMP + Compare Value + 0 + 32 + + + + + + MODE1 + 16-bit Counter with Two 16-bit Compares + MODE0 + RtcMode1 + 0x0 + + CTRLA + MODE1 Control A + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 2 + + MODESelect + + COUNT32 + Mode 0: 32-bit Counter + 0 + + + COUNT16 + Mode 1: 16-bit Counter + 1 + + + CLOCK + Mode 2: Clock/Calendar + 2 + + + + + PRESCALER + Prescaler + 8 + 4 + + PRESCALERSelect + + OFF + CLK_RTC_CNT = GCLK_RTC/1 + 0 + + + DIV1 + CLK_RTC_CNT = GCLK_RTC/1 + 1 + + + DIV2 + CLK_RTC_CNT = GCLK_RTC/2 + 2 + + + DIV4 + CLK_RTC_CNT = GCLK_RTC/4 + 3 + + + DIV8 + CLK_RTC_CNT = GCLK_RTC/8 + 4 + + + DIV16 + CLK_RTC_CNT = GCLK_RTC/16 + 5 + + + DIV32 + CLK_RTC_CNT = GCLK_RTC/32 + 6 + + + DIV64 + CLK_RTC_CNT = GCLK_RTC/64 + 7 + + + DIV128 + CLK_RTC_CNT = GCLK_RTC/128 + 8 + + + DIV256 + CLK_RTC_CNT = GCLK_RTC/256 + 9 + + + DIV512 + CLK_RTC_CNT = GCLK_RTC/512 + 0xA + + + DIV1024 + CLK_RTC_CNT = GCLK_RTC/1024 + 0xB + + + + + COUNTSYNC + Count Read Synchronization Enable + 15 + 1 + + + + + EVCTRL + MODE1 Event Control + 0x4 + 32 + 0x00000000 + + + PEREO0 + Periodic Interval 0 Event Output Enable + 0 + 1 + + + PEREO1 + Periodic Interval 1 Event Output Enable + 1 + 1 + + + PEREO2 + Periodic Interval 2 Event Output Enable + 2 + 1 + + + PEREO3 + Periodic Interval 3 Event Output Enable + 3 + 1 + + + PEREO4 + Periodic Interval 4 Event Output Enable + 4 + 1 + + + PEREO5 + Periodic Interval 5 Event Output Enable + 5 + 1 + + + PEREO6 + Periodic Interval 6 Event Output Enable + 6 + 1 + + + PEREO7 + Periodic Interval 7 Event Output Enable + 7 + 1 + + + CMPEO0 + Compare 0 Event Output Enable + 8 + 1 + + + CMPEO1 + Compare 1 Event Output Enable + 9 + 1 + + + OVFEO + Overflow Event Output Enable + 15 + 1 + + + + + INTENCLR + MODE1 Interrupt Enable Clear + 0x8 + 16 + 0x0000 + + + PER0 + Periodic Interval 0 Interrupt Enable + 0 + 1 + + + PER1 + Periodic Interval 1 Interrupt Enable + 1 + 1 + + + PER2 + Periodic Interval 2 Interrupt Enable + 2 + 1 + + + PER3 + Periodic Interval 3 Interrupt Enable + 3 + 1 + + + PER4 + Periodic Interval 4 Interrupt Enable + 4 + 1 + + + PER5 + Periodic Interval 5 Interrupt Enable + 5 + 1 + + + PER6 + Periodic Interval 6 Interrupt Enable + 6 + 1 + + + PER7 + Periodic Interval 7 Interrupt Enable + 7 + 1 + + + CMP0 + Compare 0 Interrupt Enable + 8 + 1 + + + CMP1 + Compare 1 Interrupt Enable + 9 + 1 + + + OVF + Overflow Interrupt Enable + 15 + 1 + + + + + INTENSET + MODE1 Interrupt Enable Set + 0xA + 16 + 0x0000 + + + PER0 + Periodic Interval 0 Interrupt Enable + 0 + 1 + + + PER1 + Periodic Interval 1 Interrupt Enable + 1 + 1 + + + PER2 + Periodic Interval 2 Interrupt Enable + 2 + 1 + + + PER3 + Periodic Interval 3 Interrupt Enable + 3 + 1 + + + PER4 + Periodic Interval 4 Interrupt Enable + 4 + 1 + + + PER5 + Periodic Interval 5 Interrupt Enable + 5 + 1 + + + PER6 + Periodic Interval 6 Interrupt Enable + 6 + 1 + + + PER7 + Periodic Interval 7 Interrupt Enable + 7 + 1 + + + CMP0 + Compare 0 Interrupt Enable + 8 + 1 + + + CMP1 + Compare 1 Interrupt Enable + 9 + 1 + + + OVF + Overflow Interrupt Enable + 15 + 1 + + + + + INTFLAG + MODE1 Interrupt Flag Status and Clear + 0xC + 16 + 0x0000 + + + PER0 + Periodic Interval 0 + 0 + 1 + + + PER1 + Periodic Interval 1 + 1 + 1 + + + PER2 + Periodic Interval 2 + 2 + 1 + + + PER3 + Periodic Interval 3 + 3 + 1 + + + PER4 + Periodic Interval 4 + 4 + 1 + + + PER5 + Periodic Interval 5 + 5 + 1 + + + PER6 + Periodic Interval 6 + 6 + 1 + + + PER7 + Periodic Interval 7 + 7 + 1 + + + CMP0 + Compare 0 + 8 + 1 + + + CMP1 + Compare 1 + 9 + 1 + + + OVF + Overflow + 15 + 1 + + + + + DBGCTRL + Debug Control + 0xE + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + SYNCBUSY + MODE1 Synchronization Busy Status + 0x10 + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Bit Busy + 0 + 1 + + + ENABLE + Enable Bit Busy + 1 + 1 + + + FREQCORR + FREQCORR Register Busy + 2 + 1 + + + COUNT + COUNT Register Busy + 3 + 1 + + + PER + PER Register Busy + 4 + 1 + + + COMP0 + COMP 0 Register Busy + 5 + 1 + + + COMP1 + COMP 1 Register Busy + 6 + 1 + + + COUNTSYNC + Count Read Synchronization Enable Bit Busy + 15 + 1 + + + + + FREQCORR + Frequency Correction + 0x14 + 8 + 0x00 + + + VALUE + Correction Value + 0 + 7 + + + SIGN + Correction Sign + 7 + 1 + + + + + COUNT + MODE1 Counter Value + 0x18 + 16 + 0x0000 + + + COUNT + Counter Value + 0 + 16 + + + + + PER + MODE1 Counter Period + 0x1C + 16 + 0x0000 + + + PER + Counter Period + 0 + 16 + + + + + 2 + 2 + COMP[%s] + MODE1 Compare n Value + 0x20 + 16 + 0x0000 + + + COMP + Compare Value + 0 + 16 + + + + + + MODE2 + Clock/Calendar with Alarm + MODE0 + RtcMode2 + 0x0 + + CTRLA + MODE2 Control A + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 2 + + MODESelect + + COUNT32 + Mode 0: 32-bit Counter + 0 + + + COUNT16 + Mode 1: 16-bit Counter + 1 + + + CLOCK + Mode 2: Clock/Calendar + 2 + + + + + CLKREP + Clock Representation + 6 + 1 + + + MATCHCLR + Clear on Match + 7 + 1 + + + PRESCALER + Prescaler + 8 + 4 + + PRESCALERSelect + + OFF + CLK_RTC_CNT = GCLK_RTC/1 + 0x0 + + + DIV1 + CLK_RTC_CNT = GCLK_RTC/1 + 0x1 + + + DIV2 + CLK_RTC_CNT = GCLK_RTC/2 + 0x2 + + + DIV4 + CLK_RTC_CNT = GCLK_RTC/4 + 0x3 + + + DIV8 + CLK_RTC_CNT = GCLK_RTC/8 + 0x4 + + + DIV16 + CLK_RTC_CNT = GCLK_RTC/16 + 0x5 + + + DIV32 + CLK_RTC_CNT = GCLK_RTC/32 + 0x6 + + + DIV64 + CLK_RTC_CNT = GCLK_RTC/64 + 0x7 + + + DIV128 + CLK_RTC_CNT = GCLK_RTC/128 + 0x8 + + + DIV256 + CLK_RTC_CNT = GCLK_RTC/256 + 0x9 + + + DIV512 + CLK_RTC_CNT = GCLK_RTC/512 + 0xA + + + DIV1024 + CLK_RTC_CNT = GCLK_RTC/1024 + 0xB + + + + + CLOCKSYNC + Clock Read Synchronization Enable + 15 + 1 + + + + + EVCTRL + MODE2 Event Control + 0x4 + 32 + 0x00000000 + + + PEREO0 + Periodic Interval 0 Event Output Enable + 0 + 1 + + + PEREO1 + Periodic Interval 1 Event Output Enable + 1 + 1 + + + PEREO2 + Periodic Interval 2 Event Output Enable + 2 + 1 + + + PEREO3 + Periodic Interval 3 Event Output Enable + 3 + 1 + + + PEREO4 + Periodic Interval 4 Event Output Enable + 4 + 1 + + + PEREO5 + Periodic Interval 5 Event Output Enable + 5 + 1 + + + PEREO6 + Periodic Interval 6 Event Output Enable + 6 + 1 + + + PEREO7 + Periodic Interval 7 Event Output Enable + 7 + 1 + + + ALARMEO0 + Alarm 0 Event Output Enable + 8 + 1 + + + OVFEO + Overflow Event Output Enable + 15 + 1 + + + + + INTENCLR + MODE2 Interrupt Enable Clear + 0x8 + 16 + 0x0000 + + + PER0 + Periodic Interval 0 Interrupt Enable + 0 + 1 + + + PER1 + Periodic Interval 1 Interrupt Enable + 1 + 1 + + + PER2 + Periodic Interval 2 Interrupt Enable + 2 + 1 + + + PER3 + Periodic Interval 3 Interrupt Enable + 3 + 1 + + + PER4 + Periodic Interval 4 Interrupt Enable + 4 + 1 + + + PER5 + Periodic Interval 5 Interrupt Enable + 5 + 1 + + + PER6 + Periodic Interval 6 Interrupt Enable + 6 + 1 + + + PER7 + Periodic Interval 7 Interrupt Enable + 7 + 1 + + + ALARM0 + Alarm 0 Interrupt Enable + 8 + 1 + + + OVF + Overflow Interrupt Enable + 15 + 1 + + + + + INTENSET + MODE2 Interrupt Enable Set + 0xA + 16 + 0x0000 + + + PER0 + Periodic Interval 0 Enable + 0 + 1 + + + PER1 + Periodic Interval 1 Enable + 1 + 1 + + + PER2 + Periodic Interval 2 Enable + 2 + 1 + + + PER3 + Periodic Interval 3 Enable + 3 + 1 + + + PER4 + Periodic Interval 4 Enable + 4 + 1 + + + PER5 + Periodic Interval 5 Enable + 5 + 1 + + + PER6 + Periodic Interval 6 Enable + 6 + 1 + + + PER7 + Periodic Interval 7 Enable + 7 + 1 + + + ALARM0 + Alarm 0 Interrupt Enable + 8 + 1 + + + OVF + Overflow Interrupt Enable + 15 + 1 + + + + + INTFLAG + MODE2 Interrupt Flag Status and Clear + 0xC + 16 + 0x0000 + + + PER0 + Periodic Interval 0 + 0 + 1 + + + PER1 + Periodic Interval 1 + 1 + 1 + + + PER2 + Periodic Interval 2 + 2 + 1 + + + PER3 + Periodic Interval 3 + 3 + 1 + + + PER4 + Periodic Interval 4 + 4 + 1 + + + PER5 + Periodic Interval 5 + 5 + 1 + + + PER6 + Periodic Interval 6 + 6 + 1 + + + PER7 + Periodic Interval 7 + 7 + 1 + + + ALARM0 + Alarm 0 + 8 + 1 + + + OVF + Overflow + 15 + 1 + + + + + DBGCTRL + Debug Control + 0xE + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + SYNCBUSY + MODE2 Synchronization Busy Status + 0x10 + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Bit Busy + 0 + 1 + + + ENABLE + Enable Bit Busy + 1 + 1 + + + FREQCORR + FREQCORR Register Busy + 2 + 1 + + + CLOCK + CLOCK Register Busy + 3 + 1 + + + ALARM0 + ALARM 0 Register Busy + 5 + 1 + + + MASK0 + MASK 0 Register Busy + 11 + 1 + + + CLOCKSYNC + Clock Read Synchronization Enable Bit Busy + 15 + 1 + + + + + FREQCORR + Frequency Correction + 0x14 + 8 + 0x00 + + + VALUE + Correction Value + 0 + 7 + + + SIGN + Correction Sign + 7 + 1 + + + + + CLOCK + MODE2 Clock Value + 0x18 + 32 + 0x00000000 + + + SECOND + Second + 0 + 6 + + + MINUTE + Minute + 6 + 6 + + + HOUR + Hour + 12 + 5 + + HOURSelect + + AM + AM when CLKREP in 12-hour + 0x00 + + + PM + PM when CLKREP in 12-hour + 0x10 + + + + + DAY + Day + 17 + 5 + + + MONTH + Month + 22 + 4 + + + YEAR + Year + 26 + 6 + + + + + ALARM + MODE2_ALARM Alarm n Value + 0x20 + 32 + 0x00000000 + + + SECOND + Second + 0 + 6 + + + MINUTE + Minute + 6 + 6 + + + HOUR + Hour + 12 + 5 + + HOURSelect + + AM + Morning hour + 0x00 + + + PM + Afternoon hour + 0x10 + + + + + DAY + Day + 17 + 5 + + + MONTH + Month + 22 + 4 + + + YEAR + Year + 26 + 6 + + + + + MASK + MODE2_ALARM Alarm n Mask + 0x24 + 8 + 0x00 + + + SEL + Alarm Mask Selection + 0 + 3 + + SELSelect + + OFF + Alarm Disabled + 0x0 + + + SS + Match seconds only + 0x1 + + + MMSS + Match seconds and minutes only + 0x2 + + + HHMMSS + Match seconds, minutes, and hours only + 0x3 + + + DDHHMMSS + Match seconds, minutes, hours, and days only + 0x4 + + + MMDDHHMMSS + Match seconds, minutes, hours, days, and months only + 0x5 + + + YYMMDDHHMMSS + Match seconds, minutes, hours, days, months, and years + 0x6 + + + + + + + + + + SERCOM0 + U22013.1.1 + Serial Communication Interface + SERCOM + SERCOM_ + 0x42000400 + + 0 + 0x31 + registers + + + SERCOM0 + 9 + + + + I2CM + I2C Master Mode + SercomI2cm + 0x0 + + CTRLA + I2CM Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run in Standby + 7 + 1 + + + PINOUT + Pin Usage + 16 + 1 + + + SDAHOLD + SDA Hold Time + 20 + 2 + + SDAHOLDSelect + + DISABLE + Disabled + 0x0 + + + 75NS + 50-100ns hold time + 0x1 + + + 450NS + 300-600ns hold time + 0x2 + + + 600NS + 400-800ns hold time + 0x3 + + + + + MEXTTOEN + Master SCL Low Extend Timeout + 22 + 1 + + + SEXTTOEN + Slave SCL Low Extend Timeout + 23 + 1 + + + SPEED + Transfer Speed + 24 + 2 + + SPEEDSelect + + STANDARD_AND_FAST_MODE + Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz + 0x0 + + + FASTPLUS_MODE + Fast-mode Plus Upto 1MHz + 0x1 + + + HIGH_SPEED_MODE + High-speed mode Upto 3.4MHz + 0x2 + + + + + SCLSM + SCL Clock Stretch Mode + 27 + 1 + + + INACTOUT + Inactive Time-Out + 28 + 2 + + INACTOUTSelect + + DISABLE + Disabled + 0x0 + + + 55US + 5-6 SCL Time-Out(50-60us) + 0x1 + + + 105US + 10-11 SCL Time-Out(100-110us) + 0x2 + + + 205US + 20-21 SCL Time-Out(200-210us) + 0x3 + + + + + LOWTOUTEN + SCL Low Timeout Enable + 30 + 1 + + + + + CTRLB + I2CM Control B + 0x4 + 32 + 0x00000000 + + + SMEN + Smart Mode Enable + 8 + 1 + + + QCEN + Quick Command Enable + 9 + 1 + + + CMD + Command + 16 + 2 + + + ACKACT + Acknowledge Action + 18 + 1 + + + + + BAUD + I2CM Baud Rate + 0xC + 32 + 0x00000000 + + + BAUD + Baud Rate Value + 0 + 8 + + + BAUDLOW + Baud Rate Value Low + 8 + 8 + + + HSBAUD + High Speed Baud Rate Value + 16 + 8 + + + HSBAUDLOW + High Speed Baud Rate Value Low + 24 + 8 + + + + + INTENCLR + I2CM Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + MB + Master On Bus Interrupt Disable + 0 + 1 + + + SB + Slave On Bus Interrupt Disable + 1 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + I2CM Interrupt Enable Set + 0x16 + 8 + 0x00 + + + MB + Master On Bus Interrupt Enable + 0 + 1 + + + SB + Slave On Bus Interrupt Enable + 1 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + I2CM Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + MB + Master On Bus Interrupt + 0 + 1 + + + SB + Slave On Bus Interrupt + 1 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + I2CM Status + 0x1A + 16 + 0x0000 + + + BUSERR + Bus Error + 0 + 1 + + + ARBLOST + Arbitration Lost + 1 + 1 + + + RXNACK + Received Not Acknowledge + 2 + 1 + + + BUSSTATE + Bus State + 4 + 2 + + + LOWTOUT + SCL Low Timeout + 6 + 1 + + + CLKHOLD + Clock Hold + 7 + 1 + + + MEXTTOUT + Master SCL Low Extend Timeout + 8 + 1 + + + SEXTTOUT + Slave SCL Low Extend Timeout + 9 + 1 + + + LENERR + Length Error + 10 + 1 + + + + + SYNCBUSY + I2CM Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + SYSOP + System Operation Synchronization Busy + 2 + 1 + + + + + ADDR + I2CM Address + 0x24 + 32 + 0x00000000 + + + ADDR + Address Value + 0 + 11 + + + LENEN + Length Enable + 13 + 1 + + + HS + High Speed Mode + 14 + 1 + + + TENBITEN + Ten Bit Addressing Enable + 15 + 1 + + + LEN + Length + 16 + 8 + + + + + DATA + I2CM Data + 0x28 + 8 + 0x00 + + + DATA + Data Value + 0 + 8 + + + + + DBGCTRL + I2CM Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + I2CS + I2C Slave Mode + I2CM + SercomI2cs + 0x0 + + CTRLA + I2CS Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + PINOUT + Pin Usage + 16 + 1 + + + SDAHOLD + SDA Hold Time + 20 + 2 + + SDAHOLDSelect + + DISABLE + Disabled + 0x0 + + + 75NS + 50-100ns hold time + 0x1 + + + 450NS + 300-600ns hold time + 0x2 + + + 600NS + 400-800ns hold time + 0x3 + + + + + SEXTTOEN + Slave SCL Low Extend Timeout + 23 + 1 + + + SPEED + Transfer Speed + 24 + 2 + + SPEEDSelect + + STANDARD_AND_FAST_MODE + Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz + 0x0 + + + FASTPLUS_MODE + Fast-mode Plus Upto 1MHz + 0x1 + + + HIGH_SPEED_MODE + High-speed mode Upto 3.4MHz + 0x2 + + + + + SCLSM + SCL Clock Stretch Mode + 27 + 1 + + + LOWTOUTEN + SCL Low Timeout Enable + 30 + 1 + + + + + CTRLB + I2CS Control B + 0x4 + 32 + 0x00000000 + + + SMEN + Smart Mode Enable + 8 + 1 + + + GCMD + PMBus Group Command + 9 + 1 + + + AACKEN + Automatic Address Acknowledge + 10 + 1 + + + AMODE + Address Mode + 14 + 2 + + + CMD + Command + 16 + 2 + + + ACKACT + Acknowledge Action + 18 + 1 + + + + + INTENCLR + I2CS Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + PREC + Stop Received Interrupt Disable + 0 + 1 + + + AMATCH + Address Match Interrupt Disable + 1 + 1 + + + DRDY + Data Interrupt Disable + 2 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + I2CS Interrupt Enable Set + 0x16 + 8 + 0x00 + + + PREC + Stop Received Interrupt Enable + 0 + 1 + + + AMATCH + Address Match Interrupt Enable + 1 + 1 + + + DRDY + Data Interrupt Enable + 2 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + I2CS Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + PREC + Stop Received Interrupt + 0 + 1 + + + AMATCH + Address Match Interrupt + 1 + 1 + + + DRDY + Data Interrupt + 2 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + I2CS Status + 0x1A + 16 + 0x0000 + + + BUSERR + Bus Error + 0 + 1 + + + COLL + Transmit Collision + 1 + 1 + + + RXNACK + Received Not Acknowledge + 2 + 1 + + + DIR + Read/Write Direction + 3 + 1 + + + SR + Repeated Start + 4 + 1 + + + LOWTOUT + SCL Low Timeout + 6 + 1 + + + CLKHOLD + Clock Hold + 7 + 1 + + + SEXTTOUT + Slave SCL Low Extend Timeout + 9 + 1 + + + HS + High Speed + 10 + 1 + + + + + SYNCBUSY + I2CS Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + + + ADDR + I2CS Address + 0x24 + 32 + 0x00000000 + + + GENCEN + General Call Address Enable + 0 + 1 + + + ADDR + Address Value + 1 + 10 + + + TENBITEN + Ten Bit Addressing Enable + 15 + 1 + + + ADDRMASK + Address Mask + 17 + 10 + + + + + DATA + I2CS Data + 0x28 + 8 + 0x00 + + + DATA + Data Value + 0 + 8 + + + + + + SPIS + SPI Slave Mode + I2CM + SercomSpis + 0x0 + + CTRLA + SPIS Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + IBON + Immediate Buffer Overflow Notification + 8 + 1 + + + DOPO + Data Out Pinout + 16 + 2 + + DOPOSelect + + PAD0 + DO on PAD[0], SCK on PAD[1] and SS on PAD[2] + 0x0 + + + PAD1 + DO on PAD[2], SCK on PAD[3] and SS on PAD[1] + 0x1 + + + PAD2 + DO on PAD[3], SCK on PAD[1] and SS on PAD[2] + 0x2 + + + PAD3 + DO on PAD[0], SCK on PAD[3] and SS on PAD[1] + 0x3 + + + + + DIPO + Data In Pinout + 20 + 2 + + DIPOSelect + + PAD0 + SERCOM PAD[0] + 0x0 + + + PAD1 + SERCOM PAD[1] + 0x1 + + + PAD2 + SERCOM PAD[2] + 0x2 + + + PAD3 + SERCOM PAD[3] + 0x3 + + + + + FORM + Frame Format + 24 + 4 + + FORMSelect + + SPI_FRAME + SPI Frame + 0x0 + + + SPI_FRAME_WITH_ADDR + SPI Frame with Addr + 0x2 + + + + + CPHA + Clock Phase + 28 + 1 + + CPHASelect + + LEADING_EDGE + The data is sampled on a leading SCK edge and changed on a trailing SCK edge + 0x0 + + + TRAILING_EDGE + The data is sampled on a trailing SCK edge and changed on a leading SCK edge + 0x1 + + + + + CPOL + Clock Polarity + 29 + 1 + + CPOLSelect + + IDLE_LOW + SCK is low when idle + 0x0 + + + IDLE_HIGH + SCK is high when idle + 0x1 + + + + + DORD + Data Order + 30 + 1 + + DORDSelect + + MSB + MSB is transferred first + 0x0 + + + LSB + LSB is transferred first + 0x1 + + + + + + + CTRLB + SPIS Control B + 0x4 + 32 + 0x00000000 + + + CHSIZE + Character Size + 0 + 3 + + CHSIZESelect + + 8_BIT + 8 bits + 0x0 + + + 9_BIT + 9 bits + 0x1 + + + + + PLOADEN + Data Preload Enable + 6 + 1 + + + SSDE + Slave Select Low Detect Enable + 9 + 1 + + + MSSEN + Master Slave Select Enable + 13 + 1 + + + AMODE + Address Mode + 14 + 2 + + AMODESelect + + MASK + SPI Address mask + 0x0 + + + 2_ADDRESSES + Two unique Addressess + 0x1 + + + RANGE + Address Range + 0x2 + + + + + RXEN + Receiver Enable + 17 + 1 + + + + + BAUD + SPIS Baud Rate + 0xC + 8 + 0x00 + + + BAUD + Baud Rate Value + 0 + 8 + + + + + INTENCLR + SPIS Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Disable + 0 + 1 + + + TXC + Transmit Complete Interrupt Disable + 1 + 1 + + + RXC + Receive Complete Interrupt Disable + 2 + 1 + + + SSL + Slave Select Low Interrupt Disable + 3 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + SPIS Interrupt Enable Set + 0x16 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Enable + 0 + 1 + + + TXC + Transmit Complete Interrupt Enable + 1 + 1 + + + RXC + Receive Complete Interrupt Enable + 2 + 1 + + + SSL + Slave Select Low Interrupt Enable + 3 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + SPIS Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt + 0 + 1 + + + TXC + Transmit Complete Interrupt + 1 + 1 + + + RXC + Receive Complete Interrupt + 2 + 1 + + + SSL + Slave Select Low Interrupt Flag + 3 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + SPIS Status + 0x1A + 16 + 0x0000 + + + BUFOVF + Buffer Overflow + 2 + 1 + + + + + SYNCBUSY + SPIS Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + CTRLB + CTRLB Synchronization Busy + 2 + 1 + + + + + ADDR + SPIS Address + 0x24 + 32 + 0x00000000 + + + ADDR + Address Value + 0 + 8 + + + ADDRMASK + Address Mask + 16 + 8 + + + + + DATA + SPIS Data + 0x28 + 32 + 0x00000000 + + + DATA + Data Value + 0 + 9 + + + + + DBGCTRL + SPIS Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + SPIM + SPI Master Mode + I2CM + SercomSpim + 0x0 + + CTRLA + SPIM Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + IBON + Immediate Buffer Overflow Notification + 8 + 1 + + + DOPO + Data Out Pinout + 16 + 2 + + DOPOSelect + + PAD0 + DO on PAD[0], SCK on PAD[1] and SS on PAD[2] + 0x0 + + + PAD1 + DO on PAD[2], SCK on PAD[3] and SS on PAD[1] + 0x1 + + + PAD2 + DO on PAD[3], SCK on PAD[1] and SS on PAD[2] + 0x2 + + + PAD3 + DO on PAD[0], SCK on PAD[3] and SS on PAD[1] + 0x3 + + + + + DIPO + Data In Pinout + 20 + 2 + + DIPOSelect + + PAD0 + SERCOM PAD[0] + 0x0 + + + PAD1 + SERCOM PAD[1] + 0x1 + + + PAD2 + SERCOM PAD[2] + 0x2 + + + PAD3 + SERCOM PAD[3] + 0x3 + + + + + FORM + Frame Format + 24 + 4 + + FORMSelect + + SPI_FRAME + SPI Frame + 0x0 + + + SPI_FRAME_WITH_ADDR + SPI Frame with Addr + 0x2 + + + + + CPHA + Clock Phase + 28 + 1 + + CPHASelect + + LEADING_EDGE + The data is sampled on a leading SCK edge and changed on a trailing SCK edge + 0x0 + + + TRAILING_EDGE + The data is sampled on a trailing SCK edge and changed on a leading SCK edge + 0x1 + + + + + CPOL + Clock Polarity + 29 + 1 + + CPOLSelect + + IDLE_LOW + SCK is low when idle + 0x0 + + + IDLE_HIGH + SCK is high when idle + 0x1 + + + + + DORD + Data Order + 30 + 1 + + DORDSelect + + MSB + MSB is transferred first + 0x0 + + + LSB + LSB is transferred first + 0x1 + + + + + + + CTRLB + SPIM Control B + 0x4 + 32 + 0x00000000 + + + CHSIZE + Character Size + 0 + 3 + + CHSIZESelect + + 8_BIT + 8 bits + 0x0 + + + 9_BIT + 9 bits + 0x1 + + + + + PLOADEN + Data Preload Enable + 6 + 1 + + + SSDE + Slave Select Low Detect Enable + 9 + 1 + + + MSSEN + Master Slave Select Enable + 13 + 1 + + + AMODE + Address Mode + 14 + 2 + + AMODESelect + + MASK + SPI Address mask + 0x0 + + + 2_ADDRESSES + Two unique Addressess + 0x1 + + + RANGE + Address Range + 0x2 + + + + + RXEN + Receiver Enable + 17 + 1 + + + + + BAUD + SPIM Baud Rate + 0xC + 8 + 0x00 + + + BAUD + Baud Rate Value + 0 + 8 + + + + + INTENCLR + SPIM Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Disable + 0 + 1 + + + TXC + Transmit Complete Interrupt Disable + 1 + 1 + + + RXC + Receive Complete Interrupt Disable + 2 + 1 + + + SSL + Slave Select Low Interrupt Disable + 3 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + SPIM Interrupt Enable Set + 0x16 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Enable + 0 + 1 + + + TXC + Transmit Complete Interrupt Enable + 1 + 1 + + + RXC + Receive Complete Interrupt Enable + 2 + 1 + + + SSL + Slave Select Low Interrupt Enable + 3 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + SPIM Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt + 0 + 1 + + + TXC + Transmit Complete Interrupt + 1 + 1 + + + RXC + Receive Complete Interrupt + 2 + 1 + + + SSL + Slave Select Low Interrupt Flag + 3 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + SPIM Status + 0x1A + 16 + 0x0000 + + + BUFOVF + Buffer Overflow + 2 + 1 + + + + + SYNCBUSY + SPIM Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + CTRLB + CTRLB Synchronization Busy + 2 + 1 + + + + + ADDR + SPIM Address + 0x24 + 32 + 0x00000000 + + + ADDR + Address Value + 0 + 8 + + + ADDRMASK + Address Mask + 16 + 8 + + + + + DATA + SPIM Data + 0x28 + 32 + 0x00000000 + + + DATA + Data Value + 0 + 9 + + + + + DBGCTRL + SPIM Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + USART_EXT + USART EXTERNAL CLOCK Mode + I2CM + SercomUsart_ext + 0x0 + + CTRLA + USART_EXT Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + IBON + Immediate Buffer Overflow Notification + 8 + 1 + + + SAMPR + Sample + 13 + 3 + + SAMPRSelect + + 16X_ARITHMETIC + 16x over-sampling using arithmetic baudrate generation + 0x0 + + + 16X_FRACTIONAL + 16x over-sampling using fractional baudrate generation + 0x1 + + + 8X_ARITHMETIC + 8x over-sampling using arithmetic baudrate generation + 0x2 + + + 8X_FRACTIONAL + 8x over-sampling using fractional baudrate generation + 0x3 + + + 3X_ARITHMETIC + 3x over-sampling using arithmetic baudrate generation + 0x4 + + + + + TXPO + Transmit Data Pinout + 16 + 2 + + TXPOSelect + + PAD0 + SERCOM PAD[0] is used for data transmission + 0x0 + + + PAD2 + SERCOM PAD[2] is used for data transmission + 0x1 + + + + + RXPO + Receive Data Pinout + 20 + 2 + + RXPOSelect + + PAD0 + SERCOM PAD[0] is used for data reception + 0x0 + + + PAD1 + SERCOM PAD[1] is used for data reception + 0x1 + + + PAD2 + SERCOM PAD[2] is used for data reception + 0x2 + + + PAD3 + SERCOM PAD[3] is used for data reception + 0x3 + + + + + SAMPA + Sample Adjustment + 22 + 2 + + + FORM + Frame Format + 24 + 4 + + FORMSelect + + USART_FRAME_NO_PARITY + USART frame + 0x0 + + + USART_FRAME_WITH_PARITY + USART frame with parity + 0x1 + + + USART_FRAME_LIN_MASTER_MODE + LIN Master - Break and sync generation + 0x2 + + + USART_FRAME_AUTO_BAUD_NO_PARITY + Auto-baud - break detection and auto-baud + 0x4 + + + USART_FRAME_AUTO_BAUD_WITH_PARITY + Auto-baud - break detection and auto-baud with parity + 0x5 + + + + + CMODE + Communication Mode + 28 + 1 + + CMODESelect + + ASYNC + Asynchronous Communication + 0x0 + + + SYNC + Synchronous Communication + 0x1 + + + + + CPOL + Clock Polarity + 29 + 1 + + CPOLSelect + + IDLE_LOW + TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge + 0x0 + + + IDLE_HIGH + TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge + 0x1 + + + + + DORD + Data Order + 30 + 1 + + DORDSelect + + MSB + MSB is transmitted first + 0x0 + + + LSB + LSB is transmitted first + 0x1 + + + + + + + CTRLB + USART_EXT Control B + 0x4 + 32 + 0x00000000 + + + CHSIZE + Character Size + 0 + 3 + + CHSIZESelect + + 8_BIT + 8 Bits + 0x0 + + + 9_BIT + 9 Bits + 0x1 + + + 5_BIT + 5 Bits + 0x5 + + + 6_BIT + 6 Bits + 0x6 + + + 7_BIT + 7 Bits + 0x7 + + + + + SBMODE + Stop Bit Mode + 6 + 1 + + SBMODESelect + + 1_BIT + One Stop Bit + 0x0 + + + 2_BIT + Two Stop Bits + 0x1 + + + + + COLDEN + Collision Detection Enable + 8 + 1 + + + SFDE + Start of Frame Detection Enable + 9 + 1 + + + ENC + Encoding Format + 10 + 1 + + + PMODE + Parity Mode + 13 + 1 + + PMODESelect + + EVEN + Even Parity + 0x0 + + + ODD + Odd Parity + 0x1 + + + + + TXEN + Transmitter Enable + 16 + 1 + + + RXEN + Receiver Enable + 17 + 1 + + + LINCMD + LIN Command + 24 + 2 + + + + + CTRLC + USART_EXT Control C + 0x8 + 32 + 0x00000000 + + + GTIME + RS485 Guard Time + 0 + 3 + + + BRKLEN + LIN Master Break Length + 8 + 2 + + + HDRDLY + LIN Master Header Delay + 10 + 2 + + + + + BAUD + USART_EXT Baud Rate + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 16 + + + + + BAUD_FRAC_MODE + USART_EXT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 13 + + + FP + Fractional Part + 13 + 3 + + + + + BAUD_FRACFP_MODE + USART_EXT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 13 + + + FP + Fractional Part + 13 + 3 + + + + + BAUD_USARTFP_MODE + USART_EXT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 16 + + + + + RXPL + USART_EXT Receive Pulse Length + 0xE + 8 + 0x00 + + + RXPL + Receive Pulse Length + 0 + 8 + + + + + INTENCLR + USART_EXT Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Disable + 0 + 1 + + + TXC + Transmit Complete Interrupt Disable + 1 + 1 + + + RXC + Receive Complete Interrupt Disable + 2 + 1 + + + RXS + Receive Start Interrupt Disable + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt Disable + 4 + 1 + + + RXBRK + Break Received Interrupt Disable + 5 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + USART_EXT Interrupt Enable Set + 0x16 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Enable + 0 + 1 + + + TXC + Transmit Complete Interrupt Enable + 1 + 1 + + + RXC + Receive Complete Interrupt Enable + 2 + 1 + + + RXS + Receive Start Interrupt Enable + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt Enable + 4 + 1 + + + RXBRK + Break Received Interrupt Enable + 5 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + USART_EXT Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt + 0 + 1 + + + TXC + Transmit Complete Interrupt + 1 + 1 + + + RXC + Receive Complete Interrupt + 2 + 1 + + + RXS + Receive Start Interrupt + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt + 4 + 1 + + + RXBRK + Break Received Interrupt + 5 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + USART_EXT Status + 0x1A + 16 + 0x0000 + + + PERR + Parity Error + 0 + 1 + + + FERR + Frame Error + 1 + 1 + + + BUFOVF + Buffer Overflow + 2 + 1 + + + CTS + Clear To Send + 3 + 1 + + + ISF + Inconsistent Sync Field + 4 + 1 + + + COLL + Collision Detected + 5 + 1 + + + TXE + Transmitter Empty + 6 + 1 + + + + + SYNCBUSY + USART_EXT Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + CTRLB + CTRLB Synchronization Busy + 2 + 1 + + + + + DATA + USART_EXT Data + 0x28 + 16 + 0x0000 + + + DATA + Data Value + 0 + 9 + + + + + DBGCTRL + USART_EXT Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + USART_INT + USART INTERNAL CLOCK Mode + I2CM + SercomUsart_int + 0x0 + + CTRLA + USART_INT Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + IBON + Immediate Buffer Overflow Notification + 8 + 1 + + + SAMPR + Sample + 13 + 3 + + SAMPRSelect + + 16X_ARITHMETIC + 16x over-sampling using arithmetic baudrate generation + 0x0 + + + 16X_FRACTIONAL + 16x over-sampling using fractional baudrate generation + 0x1 + + + 8X_ARITHMETIC + 8x over-sampling using arithmetic baudrate generation + 0x2 + + + 8X_FRACTIONAL + 8x over-sampling using fractional baudrate generation + 0x3 + + + 3X_ARITHMETIC + 3x over-sampling using arithmetic baudrate generation + 0x4 + + + + + TXPO + Transmit Data Pinout + 16 + 2 + + TXPOSelect + + PAD0 + SERCOM PAD[0] is used for data transmission + 0x0 + + + PAD2 + SERCOM PAD[2] is used for data transmission + 0x1 + + + + + RXPO + Receive Data Pinout + 20 + 2 + + RXPOSelect + + PAD0 + SERCOM PAD[0] is used for data reception + 0x0 + + + PAD1 + SERCOM PAD[1] is used for data reception + 0x1 + + + PAD2 + SERCOM PAD[2] is used for data reception + 0x2 + + + PAD3 + SERCOM PAD[3] is used for data reception + 0x3 + + + + + SAMPA + Sample Adjustment + 22 + 2 + + + FORM + Frame Format + 24 + 4 + + FORMSelect + + USART_FRAME_NO_PARITY + USART frame + 0x0 + + + USART_FRAME_WITH_PARITY + USART frame with parity + 0x1 + + + USART_FRAME_LIN_MASTER_MODE + LIN Master - Break and sync generation + 0x2 + + + USART_FRAME_AUTO_BAUD_NO_PARITY + Auto-baud - break detection and auto-baud + 0x4 + + + USART_FRAME_AUTO_BAUD_WITH_PARITY + Auto-baud - break detection and auto-baud with parity + 0x5 + + + + + CMODE + Communication Mode + 28 + 1 + + CMODESelect + + ASYNC + Asynchronous Communication + 0x0 + + + SYNC + Synchronous Communication + 0x1 + + + + + CPOL + Clock Polarity + 29 + 1 + + CPOLSelect + + IDLE_LOW + TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge + 0x0 + + + IDLE_HIGH + TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge + 0x1 + + + + + DORD + Data Order + 30 + 1 + + DORDSelect + + MSB + MSB is transmitted first + 0x0 + + + LSB + LSB is transmitted first + 0x1 + + + + + + + CTRLB + USART_INT Control B + 0x4 + 32 + 0x00000000 + + + CHSIZE + Character Size + 0 + 3 + + CHSIZESelect + + 8_BIT + 8 Bits + 0x0 + + + 9_BIT + 9 Bits + 0x1 + + + 5_BIT + 5 Bits + 0x5 + + + 6_BIT + 6 Bits + 0x6 + + + 7_BIT + 7 Bits + 0x7 + + + + + SBMODE + Stop Bit Mode + 6 + 1 + + SBMODESelect + + 1_BIT + One Stop Bit + 0x0 + + + 2_BIT + Two Stop Bits + 0x1 + + + + + COLDEN + Collision Detection Enable + 8 + 1 + + + SFDE + Start of Frame Detection Enable + 9 + 1 + + + ENC + Encoding Format + 10 + 1 + + + PMODE + Parity Mode + 13 + 1 + + PMODESelect + + EVEN + Even Parity + 0x0 + + + ODD + Odd Parity + 0x1 + + + + + TXEN + Transmitter Enable + 16 + 1 + + + RXEN + Receiver Enable + 17 + 1 + + + LINCMD + LIN Command + 24 + 2 + + + + + CTRLC + USART_INT Control C + 0x8 + 32 + 0x00000000 + + + GTIME + RS485 Guard Time + 0 + 3 + + + BRKLEN + LIN Master Break Length + 8 + 2 + + + HDRDLY + LIN Master Header Delay + 10 + 2 + + + + + BAUD + USART_INT Baud Rate + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 16 + + + + + BAUD_FRAC_MODE + USART_INT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 13 + + + FP + Fractional Part + 13 + 3 + + + + + BAUD_FRACFP_MODE + USART_INT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 13 + + + FP + Fractional Part + 13 + 3 + + + + + BAUD_USARTFP_MODE + USART_INT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 16 + + + + + RXPL + USART_INT Receive Pulse Length + 0xE + 8 + 0x00 + + + RXPL + Receive Pulse Length + 0 + 8 + + + + + INTENCLR + USART_INT Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Disable + 0 + 1 + + + TXC + Transmit Complete Interrupt Disable + 1 + 1 + + + RXC + Receive Complete Interrupt Disable + 2 + 1 + + + RXS + Receive Start Interrupt Disable + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt Disable + 4 + 1 + + + RXBRK + Break Received Interrupt Disable + 5 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + USART_INT Interrupt Enable Set + 0x16 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Enable + 0 + 1 + + + TXC + Transmit Complete Interrupt Enable + 1 + 1 + + + RXC + Receive Complete Interrupt Enable + 2 + 1 + + + RXS + Receive Start Interrupt Enable + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt Enable + 4 + 1 + + + RXBRK + Break Received Interrupt Enable + 5 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + USART_INT Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt + 0 + 1 + + + TXC + Transmit Complete Interrupt + 1 + 1 + + + RXC + Receive Complete Interrupt + 2 + 1 + + + RXS + Receive Start Interrupt + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt + 4 + 1 + + + RXBRK + Break Received Interrupt + 5 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + USART_INT Status + 0x1A + 16 + 0x0000 + + + PERR + Parity Error + 0 + 1 + + + FERR + Frame Error + 1 + 1 + + + BUFOVF + Buffer Overflow + 2 + 1 + + + CTS + Clear To Send + 3 + 1 + + + ISF + Inconsistent Sync Field + 4 + 1 + + + COLL + Collision Detected + 5 + 1 + + + TXE + Transmitter Empty + 6 + 1 + + + + + SYNCBUSY + USART_INT Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + CTRLB + CTRLB Synchronization Busy + 2 + 1 + + + + + DATA + USART_INT Data + 0x28 + 16 + 0x0000 + + + DATA + Data Value + 0 + 9 + + + + + DBGCTRL + USART_INT Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + + + SERCOM1 + 0x42000800 + + SERCOM1 + 10 + + + + SERCOM2 + 0x42000C00 + + SERCOM2 + 11 + + + + SERCOM3 + 0x42001000 + + SERCOM3 + 12 + + + + SUPC + U21172.1.1 + Supply Controller + SUPC + SUPC_ + 0x40001800 + + 0 + 0x20 + registers + + + + INTENCLR + Interrupt Enable Clear + 0x0 + 32 + 0x00000000 + + + BODVDDRDY + BODVDD Ready + 0 + 1 + + + BODVDDDET + BODVDD Detection + 1 + 1 + + + BVDDSRDY + BODVDD Synchronization Ready + 2 + 1 + + + BODCORERDY + BODCORE Ready + 3 + 1 + + + BODCOREDET + BODCORE Detection + 4 + 1 + + + BCORESRDY + BODCORE Synchronization Ready + 5 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x4 + 32 + 0x00000000 + + + BODVDDRDY + BODVDD Ready + 0 + 1 + + + BODVDDDET + BODVDD Detection + 1 + 1 + + + BVDDSRDY + BODVDD Synchronization Ready + 2 + 1 + + + BODCORERDY + BODCORE Ready + 3 + 1 + + + BODCOREDET + BODCORE Detection + 4 + 1 + + + BCORESRDY + BODCORE Synchronization Ready + 5 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x8 + 32 + 0x00000000 + + + BODVDDRDY + BODVDD Ready + 0 + 1 + + + BODVDDDET + BODVDD Detection + 1 + 1 + + + BVDDSRDY + BODVDD Synchronization Ready + 2 + 1 + + + BODCORERDY + BODCORE Ready + 3 + 1 + + + BODCOREDET + BODCORE Detection + 4 + 1 + + + BCORESRDY + BODCORE Synchronization Ready + 5 + 1 + + + + + STATUS + Power and Clocks Status + 0xC + 32 + read-only + 0x00000000 + + + BODVDDRDY + BODVDD Ready + 0 + 1 + + + BODVDDDET + BODVDD Detection + 1 + 1 + + + BVDDSRDY + BODVDD Synchronization Ready + 2 + 1 + + + BODCORERDY + BODCORE Ready + 3 + 1 + + + BODCOREDET + BODCORE Detection + 4 + 1 + + + BCORESRDY + BODCORE Synchronization Ready + 5 + 1 + + + + + BODVDD + BODVDD Control + 0x10 + 32 + 0x00000000 + + + ENABLE + Enable + 1 + 1 + + + HYST + Hysteresis Enable + 2 + 1 + + + ACTION + Action when Threshold Crossed + 3 + 2 + + ACTIONSelect + + NONE + No action + 0x0 + + + RESET + The BODVDD generates a reset + 0x1 + + + INT + The BODVDD generates an interrupt + 0x2 + + + + + STDBYCFG + Configuration in Standby mode + 5 + 1 + + + RUNSTDBY + Run during Standby + 6 + 1 + + + ACTCFG + Configuration in Active mode + 8 + 1 + + + PSEL + Prescaler Select + 12 + 4 + + PSELSelect + + DIV2 + Divide clock by 2 + 0x0 + + + DIV4 + Divide clock by 4 + 0x1 + + + DIV8 + Divide clock by 8 + 0x2 + + + DIV16 + Divide clock by 16 + 0x3 + + + DIV32 + Divide clock by 32 + 0x4 + + + DIV64 + Divide clock by 64 + 0x5 + + + DIV128 + Divide clock by 128 + 0x6 + + + DIV256 + Divide clock by 256 + 0x7 + + + DIV512 + Divide clock by 512 + 0x8 + + + DIV1024 + Divide clock by 1024 + 0x9 + + + DIV2048 + Divide clock by 2048 + 0xA + + + DIV4096 + Divide clock by 4096 + 0xB + + + DIV8192 + Divide clock by 8192 + 0xC + + + DIV16384 + Divide clock by 16384 + 0xD + + + DIV32768 + Divide clock by 32768 + 0xE + + + DIV65536 + Divide clock by 65536 + 0xF + + + + + LEVEL + Threshold Level for VDD + 16 + 6 + + + + + BODCORE + BODCORE Control + 0x14 + 32 + 0x00000000 + + + ENABLE + Enable + 1 + 1 + + + HYST + Hysteresis Enable + 2 + 1 + + + ACTION + Action when Threshold Crossed + 3 + 2 + + ACTIONSelect + + NONE + No action + 0x0 + + + RESET + The BODCORE generates a reset + 0x1 + + + INT + The BODCORE generates an interrupt + 0x2 + + + + + STDBYCFG + Configuration in Standby mode + 5 + 1 + + + RUNSTDBY + Run during Standby + 6 + 1 + + + ACTCFG + Configuration in Active mode + 8 + 1 + + + PSEL + Prescaler Select + 12 + 4 + + PSELSelect + + DIV2 + Divide clock by 2 + 0x0 + + + DIV4 + Divide clock by 4 + 0x1 + + + DIV8 + Divide clock by 8 + 0x2 + + + DIV16 + Divide clock by 16 + 0x3 + + + DIV32 + Divide clock by 32 + 0x4 + + + DIV64 + Divide clock by 64 + 0x5 + + + DIV128 + Divide clock by 128 + 0x6 + + + DIV256 + Divide clock by 256 + 0x7 + + + DIV512 + Divide clock by 512 + 0x8 + + + DIV1024 + Divide clock by 1024 + 0x9 + + + DIV2048 + Divide clock by 2048 + 0xA + + + DIV4096 + Divide clock by 4096 + 0xB + + + DIV8192 + Divide clock by 8192 + 0xC + + + DIV16384 + Divide clock by 16384 + 0xD + + + DIV32768 + Divide clock by 32768 + 0xE + + + DIV65536 + Divide clock by 65536 + 0xF + + + + + LEVEL + Threshold Level + 16 + 6 + + + + + VREG + VREG Control + 0x18 + 32 + 0x00000000 + + + ENABLE + Enable + 1 + 1 + + + RUNSTDBY + Run during Standby + 6 + 1 + + + + + VREF + VREF Control + 0x1C + 32 + 0x00000000 + + + TSEN + Temperature Sensor Output Enable + 1 + 1 + + + VREFOE + Voltage Reference Output Enable + 2 + 1 + + + RUNSTDBY + Run during Standby + 6 + 1 + + + ONDEMAND + On Demand Contrl + 7 + 1 + + + SEL + Voltage Reference Selection + 16 + 4 + + SELSelect + + 1V024 + 1.024V voltage reference typical value + 0x0 + + + 2V048 + 2.048V voltage reference typical value + 0x2 + + + 4V096 + 4.096V voltage reference typical value + 0x3 + + + + + + + + + TC0 + U22492.0.0 + Basic Timer Counter + TC + TC_ + 0x42003000 + + 0 + 0x38 + registers + + + TC0 + 20 + + + + COUNT8 + 8-bit Counter Mode + TcCount8 + 0x0 + + CTRLA + Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Timer Counter Mode + 2 + 2 + + MODESelect + + COUNT16 + Counter in 16-bit mode + 0 + + + COUNT8 + Counter in 8-bit mode + 1 + + + COUNT32 + Counter in 32-bit mode + 2 + + + + + PRESCSYNC + Prescaler and Counter Synchronization + 4 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset the counter on next generic clock + 0 + + + PRESC + Reload or reset the counter on next prescaler clock + 1 + + + RESYNC + Reload or reset the counter on next generic clock and reset the prescaler counter + 2 + + + + + RUNSTDBY + Run during Standby + 6 + 1 + + + ONDEMAND + Clock On Demand + 7 + 1 + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + Prescaler: GCLK_TC + 0 + + + DIV2 + Prescaler: GCLK_TC/2 + 1 + + + DIV4 + Prescaler: GCLK_TC/4 + 2 + + + DIV8 + Prescaler: GCLK_TC/8 + 3 + + + DIV16 + Prescaler: GCLK_TC/16 + 4 + + + DIV64 + Prescaler: GCLK_TC/64 + 5 + + + DIV256 + Prescaler: GCLK_TC/256 + 6 + + + DIV1024 + Prescaler: GCLK_TC/1024 + 7 + + + + + ALOCK + Auto Lock + 11 + 1 + + + CAPTEN0 + Capture Channel 0 Enable + 16 + 1 + + + CAPTEN1 + Capture Channel 1 Enable + 17 + 1 + + + COPEN0 + Capture On Pin 0 Enable + 20 + 1 + + + COPEN1 + Capture On Pin 1 Enable + 21 + 1 + + + + + CTRLBCLR + Control B Clear + 0x4 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot on Counter + 2 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + UPDATE + Force update of double-buffered register + 3 + + + READSYNC + Force a read synchronization of COUNT + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + CTRLBSET + Control B Set + 0x5 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot on Counter + 2 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + UPDATE + Force update of double-buffered register + 3 + + + READSYNC + Force a read synchronization of COUNT + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + EVCTRL + Event Control + 0x6 + 16 + 0x0000 + + + EVACT + Event Action + 0 + 3 + + EVACTSelect + + OFF + Event action disabled + 0 + + + RETRIGGER + Start, restart or retrigger TC on event + 1 + + + COUNT + Count on event + 2 + + + START + Start TC on event + 3 + + + STAMP + Time stamp capture + 4 + + + PPW + Period catured in CC0, pulse width in CC1 + 5 + + + PWP + Period catured in CC1, pulse width in CC0 + 6 + + + PW + Pulse width capture + 7 + + + + + TCINV + TC Event Input Polarity + 4 + 1 + + + TCEI + TC Event Enable + 5 + 1 + + + OVFEO + Event Output Enable + 8 + 1 + + + MCEO0 + MC Event Output Enable 0 + 12 + 1 + + + MCEO1 + MC Event Output Enable 1 + 13 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x8 + 8 + 0x00 + + + OVF + OVF Interrupt Disable + 0 + 1 + + + ERR + ERR Interrupt Disable + 1 + 1 + + + MC0 + MC Interrupt Disable 0 + 4 + 1 + + + MC1 + MC Interrupt Disable 1 + 5 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x9 + 8 + 0x00 + + + OVF + OVF Interrupt Enable + 0 + 1 + + + ERR + ERR Interrupt Enable + 1 + 1 + + + MC0 + MC Interrupt Enable 0 + 4 + 1 + + + MC1 + MC Interrupt Enable 1 + 5 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0xA + 8 + 0x00 + + + OVF + OVF Interrupt Flag + 0 + 1 + + + ERR + ERR Interrupt Flag + 1 + 1 + + + MC0 + MC Interrupt Flag 0 + 4 + 1 + + + MC1 + MC Interrupt Flag 1 + 5 + 1 + + + + + STATUS + Status + 0xB + 8 + 0x01 + + + STOP + Stop Status Flag + 0 + 1 + + + SLAVE + Slave Status Flag + 1 + 1 + + + PERBUFV + Synchronization Busy Status + 3 + 1 + + + CCBUFV0 + Compare channel buffer 0 valid + 4 + 1 + + + CCBUFV1 + Compare channel buffer 1 valid + 5 + 1 + + + + + WAVE + Waveform Generation Control + 0xC + 8 + 0x00 + + + WAVEGEN + Waveform Generation Mode + 0 + 2 + + WAVEGENSelect + + NFRQ + Normal frequency + 0 + + + MFRQ + Match frequency + 1 + + + NPWM + Normal PWM + 2 + + + MPWM + Match PWM + 3 + + + + + + + DRVCTRL + Control C + 0xD + 8 + 0x00 + + + INVEN0 + Output Waveform Invert Enable 0 + 0 + 1 + + + INVEN1 + Output Waveform Invert Enable 1 + 1 + 1 + + + + + DBGCTRL + Debug Control + 0xF + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + SYNCBUSY + Synchronization Status + 0x10 + 32 + read-only + 0x00000000 + + + SWRST + swrst + 0 + 1 + + + ENABLE + enable + 1 + 1 + + + CTRLB + CTRLB + 2 + 1 + + + STATUS + STATUS + 3 + 1 + + + COUNT + Counter + 4 + 1 + + + PER + Period + 5 + 1 + + + CC0 + Compare Channel 0 + 6 + 1 + + + CC1 + Compare Channel 1 + 7 + 1 + + + + + COUNT + COUNT8 Count + 0x14 + 8 + 0x00 + + + COUNT + Counter Value + 0 + 8 + + + + + PER + COUNT8 Period + 0x1B + 8 + 0xFF + + + PER + Period Value + 0 + 8 + + + + + 2 + 1 + CC[%s] + COUNT8 Compare and Capture + 0x1C + 8 + 0x00 + + + CC + Counter/Compare Value + 0 + 8 + + + + + PERBUF + COUNT8 Period Buffer + 0x2F + 8 + 0xFF + + + PERBUF + Period Buffer Value + 0 + 8 + + + + + 2 + 1 + CCBUF[%s] + COUNT8 Compare and Capture Buffer + 0x30 + 8 + 0x00 + + + CCBUF + Counter/Compare Buffer Value + 0 + 8 + + + + + + COUNT16 + 16-bit Counter Mode + COUNT8 + TcCount16 + 0x0 + + CTRLA + Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Timer Counter Mode + 2 + 2 + + MODESelect + + COUNT16 + Counter in 16-bit mode + 0 + + + COUNT8 + Counter in 8-bit mode + 1 + + + COUNT32 + Counter in 32-bit mode + 2 + + + + + PRESCSYNC + Prescaler and Counter Synchronization + 4 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset the counter on next generic clock + 0 + + + PRESC + Reload or reset the counter on next prescaler clock + 1 + + + RESYNC + Reload or reset the counter on next generic clock and reset the prescaler counter + 2 + + + + + RUNSTDBY + Run during Standby + 6 + 1 + + + ONDEMAND + Clock On Demand + 7 + 1 + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + Prescaler: GCLK_TC + 0 + + + DIV2 + Prescaler: GCLK_TC/2 + 1 + + + DIV4 + Prescaler: GCLK_TC/4 + 2 + + + DIV8 + Prescaler: GCLK_TC/8 + 3 + + + DIV16 + Prescaler: GCLK_TC/16 + 4 + + + DIV64 + Prescaler: GCLK_TC/64 + 5 + + + DIV256 + Prescaler: GCLK_TC/256 + 6 + + + DIV1024 + Prescaler: GCLK_TC/1024 + 7 + + + + + ALOCK + Auto Lock + 11 + 1 + + + CAPTEN0 + Capture Channel 0 Enable + 16 + 1 + + + CAPTEN1 + Capture Channel 1 Enable + 17 + 1 + + + COPEN0 + Capture On Pin 0 Enable + 20 + 1 + + + COPEN1 + Capture On Pin 1 Enable + 21 + 1 + + + + + CTRLBCLR + Control B Clear + 0x4 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot on Counter + 2 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + UPDATE + Force update of double-buffered register + 3 + + + READSYNC + Force a read synchronization of COUNT + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + CTRLBSET + Control B Set + 0x5 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot on Counter + 2 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + UPDATE + Force update of double-buffered register + 3 + + + READSYNC + Force a read synchronization of COUNT + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + EVCTRL + Event Control + 0x6 + 16 + 0x0000 + + + EVACT + Event Action + 0 + 3 + + EVACTSelect + + OFF + Event action disabled + 0 + + + RETRIGGER + Start, restart or retrigger TC on event + 1 + + + COUNT + Count on event + 2 + + + START + Start TC on event + 3 + + + STAMP + Time stamp capture + 4 + + + PPW + Period catured in CC0, pulse width in CC1 + 5 + + + PWP + Period catured in CC1, pulse width in CC0 + 6 + + + PW + Pulse width capture + 7 + + + + + TCINV + TC Event Input Polarity + 4 + 1 + + + TCEI + TC Event Enable + 5 + 1 + + + OVFEO + Event Output Enable + 8 + 1 + + + MCEO0 + MC Event Output Enable 0 + 12 + 1 + + + MCEO1 + MC Event Output Enable 1 + 13 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x8 + 8 + 0x00 + + + OVF + OVF Interrupt Disable + 0 + 1 + + + ERR + ERR Interrupt Disable + 1 + 1 + + + MC0 + MC Interrupt Disable 0 + 4 + 1 + + + MC1 + MC Interrupt Disable 1 + 5 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x9 + 8 + 0x00 + + + OVF + OVF Interrupt Enable + 0 + 1 + + + ERR + ERR Interrupt Enable + 1 + 1 + + + MC0 + MC Interrupt Enable 0 + 4 + 1 + + + MC1 + MC Interrupt Enable 1 + 5 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0xA + 8 + 0x00 + + + OVF + OVF Interrupt Flag + 0 + 1 + + + ERR + ERR Interrupt Flag + 1 + 1 + + + MC0 + MC Interrupt Flag 0 + 4 + 1 + + + MC1 + MC Interrupt Flag 1 + 5 + 1 + + + + + STATUS + Status + 0xB + 8 + 0x01 + + + STOP + Stop Status Flag + 0 + 1 + + + SLAVE + Slave Status Flag + 1 + 1 + + + PERBUFV + Synchronization Busy Status + 3 + 1 + + + CCBUFV0 + Compare channel buffer 0 valid + 4 + 1 + + + CCBUFV1 + Compare channel buffer 1 valid + 5 + 1 + + + + + WAVE + Waveform Generation Control + 0xC + 8 + 0x00 + + + WAVEGEN + Waveform Generation Mode + 0 + 2 + + WAVEGENSelect + + NFRQ + Normal frequency + 0 + + + MFRQ + Match frequency + 1 + + + NPWM + Normal PWM + 2 + + + MPWM + Match PWM + 3 + + + + + + + DRVCTRL + Control C + 0xD + 8 + 0x00 + + + INVEN0 + Output Waveform Invert Enable 0 + 0 + 1 + + + INVEN1 + Output Waveform Invert Enable 1 + 1 + 1 + + + + + DBGCTRL + Debug Control + 0xF + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + SYNCBUSY + Synchronization Status + 0x10 + 32 + read-only + 0x00000000 + + + SWRST + swrst + 0 + 1 + + + ENABLE + enable + 1 + 1 + + + CTRLB + CTRLB + 2 + 1 + + + STATUS + STATUS + 3 + 1 + + + COUNT + Counter + 4 + 1 + + + PER + Period + 5 + 1 + + + CC0 + Compare Channel 0 + 6 + 1 + + + CC1 + Compare Channel 1 + 7 + 1 + + + + + COUNT + COUNT16 Count + 0x14 + 16 + 0x0000 + + + COUNT + Counter Value + 0 + 16 + + + + + 2 + 2 + CC[%s] + COUNT16 Compare and Capture + 0x1C + 16 + 0x0000 + + + CC + Counter/Compare Value + 0 + 16 + + + + + 2 + 2 + CCBUF[%s] + COUNT16 Compare and Capture Buffer + 0x30 + 16 + 0x0000 + + + CCBUF + Counter/Compare Buffer Value + 0 + 16 + + + + + + COUNT32 + 32-bit Counter Mode + COUNT8 + TcCount32 + 0x0 + + CTRLA + Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Timer Counter Mode + 2 + 2 + + MODESelect + + COUNT16 + Counter in 16-bit mode + 0 + + + COUNT8 + Counter in 8-bit mode + 1 + + + COUNT32 + Counter in 32-bit mode + 2 + + + + + PRESCSYNC + Prescaler and Counter Synchronization + 4 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset the counter on next generic clock + 0 + + + PRESC + Reload or reset the counter on next prescaler clock + 1 + + + RESYNC + Reload or reset the counter on next generic clock and reset the prescaler counter + 2 + + + + + RUNSTDBY + Run during Standby + 6 + 1 + + + ONDEMAND + Clock On Demand + 7 + 1 + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + Prescaler: GCLK_TC + 0 + + + DIV2 + Prescaler: GCLK_TC/2 + 1 + + + DIV4 + Prescaler: GCLK_TC/4 + 2 + + + DIV8 + Prescaler: GCLK_TC/8 + 3 + + + DIV16 + Prescaler: GCLK_TC/16 + 4 + + + DIV64 + Prescaler: GCLK_TC/64 + 5 + + + DIV256 + Prescaler: GCLK_TC/256 + 6 + + + DIV1024 + Prescaler: GCLK_TC/1024 + 7 + + + + + ALOCK + Auto Lock + 11 + 1 + + + CAPTEN0 + Capture Channel 0 Enable + 16 + 1 + + + CAPTEN1 + Capture Channel 1 Enable + 17 + 1 + + + COPEN0 + Capture On Pin 0 Enable + 20 + 1 + + + COPEN1 + Capture On Pin 1 Enable + 21 + 1 + + + + + CTRLBCLR + Control B Clear + 0x4 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot on Counter + 2 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + UPDATE + Force update of double-buffered register + 3 + + + READSYNC + Force a read synchronization of COUNT + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + CTRLBSET + Control B Set + 0x5 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot on Counter + 2 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + UPDATE + Force update of double-buffered register + 3 + + + READSYNC + Force a read synchronization of COUNT + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + EVCTRL + Event Control + 0x6 + 16 + 0x0000 + + + EVACT + Event Action + 0 + 3 + + EVACTSelect + + OFF + Event action disabled + 0 + + + RETRIGGER + Start, restart or retrigger TC on event + 1 + + + COUNT + Count on event + 2 + + + START + Start TC on event + 3 + + + STAMP + Time stamp capture + 4 + + + PPW + Period catured in CC0, pulse width in CC1 + 5 + + + PWP + Period catured in CC1, pulse width in CC0 + 6 + + + PW + Pulse width capture + 7 + + + + + TCINV + TC Event Input Polarity + 4 + 1 + + + TCEI + TC Event Enable + 5 + 1 + + + OVFEO + Event Output Enable + 8 + 1 + + + MCEO0 + MC Event Output Enable 0 + 12 + 1 + + + MCEO1 + MC Event Output Enable 1 + 13 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x8 + 8 + 0x00 + + + OVF + OVF Interrupt Disable + 0 + 1 + + + ERR + ERR Interrupt Disable + 1 + 1 + + + MC0 + MC Interrupt Disable 0 + 4 + 1 + + + MC1 + MC Interrupt Disable 1 + 5 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x9 + 8 + 0x00 + + + OVF + OVF Interrupt Enable + 0 + 1 + + + ERR + ERR Interrupt Enable + 1 + 1 + + + MC0 + MC Interrupt Enable 0 + 4 + 1 + + + MC1 + MC Interrupt Enable 1 + 5 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0xA + 8 + 0x00 + + + OVF + OVF Interrupt Flag + 0 + 1 + + + ERR + ERR Interrupt Flag + 1 + 1 + + + MC0 + MC Interrupt Flag 0 + 4 + 1 + + + MC1 + MC Interrupt Flag 1 + 5 + 1 + + + + + STATUS + Status + 0xB + 8 + 0x01 + + + STOP + Stop Status Flag + 0 + 1 + + + SLAVE + Slave Status Flag + 1 + 1 + + + PERBUFV + Synchronization Busy Status + 3 + 1 + + + CCBUFV0 + Compare channel buffer 0 valid + 4 + 1 + + + CCBUFV1 + Compare channel buffer 1 valid + 5 + 1 + + + + + WAVE + Waveform Generation Control + 0xC + 8 + 0x00 + + + WAVEGEN + Waveform Generation Mode + 0 + 2 + + WAVEGENSelect + + NFRQ + Normal frequency + 0 + + + MFRQ + Match frequency + 1 + + + NPWM + Normal PWM + 2 + + + MPWM + Match PWM + 3 + + + + + + + DRVCTRL + Control C + 0xD + 8 + 0x00 + + + INVEN0 + Output Waveform Invert Enable 0 + 0 + 1 + + + INVEN1 + Output Waveform Invert Enable 1 + 1 + 1 + + + + + DBGCTRL + Debug Control + 0xF + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + SYNCBUSY + Synchronization Status + 0x10 + 32 + read-only + 0x00000000 + + + SWRST + swrst + 0 + 1 + + + ENABLE + enable + 1 + 1 + + + CTRLB + CTRLB + 2 + 1 + + + STATUS + STATUS + 3 + 1 + + + COUNT + Counter + 4 + 1 + + + PER + Period + 5 + 1 + + + CC0 + Compare Channel 0 + 6 + 1 + + + CC1 + Compare Channel 1 + 7 + 1 + + + + + COUNT + COUNT32 Count + 0x14 + 32 + 0x00000000 + + + COUNT + Counter Value + 0 + 32 + + + + + 2 + 4 + CC[%s] + COUNT32 Compare and Capture + 0x1C + 32 + 0x00000000 + + + CC + Counter/Compare Value + 0 + 32 + + + + + 2 + 4 + CCBUF[%s] + COUNT32 Compare and Capture Buffer + 0x30 + 32 + 0x00000000 + + + CCBUF + Counter/Compare Buffer Value + 0 + 32 + + + + + + + + TC1 + 0x42003400 + + TC1 + 21 + + + + TC2 + 0x42003800 + + TC2 + 22 + + + + TC3 + 0x42003C00 + + TC3 + 23 + + + + TC4 + 0x42004000 + + TC4 + 24 + + + + TCC0 + U22133.0.0 + Timer Counter Control + TCC + TCC_ + 0x42002400 + + 0 + 0x80 + registers + + + TCC0 + 17 + + + + CTRLA + Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + RESOLUTION + Enhanced Resolution + 5 + 2 + + RESOLUTIONSelect + + NONE + Dithering is disabled + 0 + + + DITH4 + Dithering is done every 16 PWM frames + 1 + + + DITH5 + Dithering is done every 32 PWM frames + 2 + + + DITH6 + Dithering is done every 64 PWM frames + 3 + + + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + No division + 0 + + + DIV2 + Divide by 2 + 1 + + + DIV4 + Divide by 4 + 2 + + + DIV8 + Divide by 8 + 3 + + + DIV16 + Divide by 16 + 4 + + + DIV64 + Divide by 64 + 5 + + + DIV256 + Divide by 256 + 6 + + + DIV1024 + Divide by 1024 + 7 + + + + + RUNSTDBY + Run in Standby + 11 + 1 + + + PRESCSYNC + Prescaler and Counter Synchronization Selection + 12 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset counter on next GCLK + 0 + + + PRESC + Reload or reset counter on next prescaler clock + 1 + + + RESYNC + Reload or reset counter on next GCLK and reset prescaler counter + 2 + + + + + ALOCK + Auto Lock + 14 + 1 + + + MSYNC + Master Synchronization (only for TCC Slave Instance) + 15 + 1 + + + DMAOS + DMA One-shot Trigger Mode + 23 + 1 + + + CPTEN0 + Capture Channel 0 Enable + 24 + 1 + + + CPTEN1 + Capture Channel 1 Enable + 25 + 1 + + + CPTEN2 + Capture Channel 2 Enable + 26 + 1 + + + CPTEN3 + Capture Channel 3 Enable + 27 + 1 + + + + + CTRLBCLR + Control B Clear + 0x4 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + IDXCMD + Ramp Index Command + 3 + 2 + + IDXCMDSelect + + DISABLE + Command disabled: Index toggles between cycles A and B + 0 + + + SET + Set index: cycle B will be forced in the next cycle + 1 + + + CLEAR + Clear index: cycle A will be forced in the next cycle + 2 + + + HOLD + Hold index: the next cycle will be the same as the current cycle + 3 + + + + + CMD + TCC Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Clear start, restart or retrigger + 1 + + + STOP + Force stop + 2 + + + UPDATE + Force update or double buffered registers + 3 + + + READSYNC + Force COUNT read synchronization + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + CTRLBSET + Control B Set + 0x5 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + IDXCMD + Ramp Index Command + 3 + 2 + + IDXCMDSelect + + DISABLE + Command disabled: Index toggles between cycles A and B + 0 + + + SET + Set index: cycle B will be forced in the next cycle + 1 + + + CLEAR + Clear index: cycle A will be forced in the next cycle + 2 + + + HOLD + Hold index: the next cycle will be the same as the current cycle + 3 + + + + + CMD + TCC Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Clear start, restart or retrigger + 1 + + + STOP + Force stop + 2 + + + UPDATE + Force update or double buffered registers + 3 + + + READSYNC + Force COUNT read synchronization + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + SYNCBUSY + Synchronization Busy + 0x8 + 32 + read-only + 0x00000000 + + + SWRST + Swrst Busy + 0 + 1 + + + ENABLE + Enable Busy + 1 + 1 + + + CTRLB + Ctrlb Busy + 2 + 1 + + + STATUS + Status Busy + 3 + 1 + + + COUNT + Count Busy + 4 + 1 + + + PATT + Pattern Busy + 5 + 1 + + + WAVE + Wave Busy + 6 + 1 + + + PER + Period Busy + 7 + 1 + + + CC0 + Compare Channel 0 Busy + 8 + 1 + + + CC1 + Compare Channel 1 Busy + 9 + 1 + + + CC2 + Compare Channel 2 Busy + 10 + 1 + + + CC3 + Compare Channel 3 Busy + 11 + 1 + + + + + FCTRLA + Recoverable Fault A Configuration + 0xC + 32 + 0x00000000 + + + SRC + Fault A Source + 0 + 2 + + SRCSelect + + DISABLE + Fault input disabled + 0 + + + ENABLE + MCEx (x=0,1) event input + 1 + + + INVERT + Inverted MCEx (x=0,1) event input + 2 + + + ALTFAULT + Alternate fault (A or B) state at the end of the previous period + 3 + + + + + KEEP + Fault A Keeper + 3 + 1 + + + QUAL + Fault A Qualification + 4 + 1 + + + BLANK + Fault A Blanking Mode + 5 + 2 + + BLANKSelect + + START + Blanking applied from start of the ramp + 0 + + + RISE + Blanking applied from rising edge of the output waveform + 1 + + + FALL + Blanking applied from falling edge of the output waveform + 2 + + + BOTH + Blanking applied from each toggle of the output waveform + 3 + + + + + RESTART + Fault A Restart + 7 + 1 + + + HALT + Fault A Halt Mode + 8 + 2 + + HALTSelect + + DISABLE + Halt action disabled + 0 + + + HW + Hardware halt action + 1 + + + SW + Software halt action + 2 + + + NR + Non-recoverable fault + 3 + + + + + CHSEL + Fault A Capture Channel + 10 + 2 + + CHSELSelect + + CC0 + Capture value stored in channel 0 + 0 + + + CC1 + Capture value stored in channel 1 + 1 + + + CC2 + Capture value stored in channel 2 + 2 + + + CC3 + Capture value stored in channel 3 + 3 + + + + + CAPTURE + Fault A Capture Action + 12 + 3 + + CAPTURESelect + + DISABLE + No capture + 0 + + + CAPT + Capture on fault + 1 + + + CAPTMIN + Minimum capture + 2 + + + CAPTMAX + Maximum capture + 3 + + + LOCMIN + Minimum local detection + 4 + + + LOCMAX + Maximum local detection + 5 + + + DERIV0 + Minimum and maximum local detection + 6 + + + CAPTMARK + Capture with ramp index as MSB value + 7 + + + + + BLANKPRESC + Fault A Blanking Prescaler + 15 + 1 + + + BLANKVAL + Fault A Blanking Time + 16 + 8 + + + FILTERVAL + Fault A Filter Value + 24 + 4 + + + + + FCTRLB + Recoverable Fault B Configuration + 0x10 + 32 + 0x00000000 + + + SRC + Fault B Source + 0 + 2 + + SRCSelect + + DISABLE + Fault input disabled + 0 + + + ENABLE + MCEx (x=0,1) event input + 1 + + + INVERT + Inverted MCEx (x=0,1) event input + 2 + + + ALTFAULT + Alternate fault (A or B) state at the end of the previous period + 3 + + + + + KEEP + Fault B Keeper + 3 + 1 + + + QUAL + Fault B Qualification + 4 + 1 + + + BLANK + Fault B Blanking Mode + 5 + 2 + + BLANKSelect + + START + Blanking applied from start of the ramp + 0 + + + RISE + Blanking applied from rising edge of the output waveform + 1 + + + FALL + Blanking applied from falling edge of the output waveform + 2 + + + BOTH + Blanking applied from each toggle of the output waveform + 3 + + + + + RESTART + Fault B Restart + 7 + 1 + + + HALT + Fault B Halt Mode + 8 + 2 + + HALTSelect + + DISABLE + Halt action disabled + 0 + + + HW + Hardware halt action + 1 + + + SW + Software halt action + 2 + + + NR + Non-recoverable fault + 3 + + + + + CHSEL + Fault B Capture Channel + 10 + 2 + + CHSELSelect + + CC0 + Capture value stored in channel 0 + 0 + + + CC1 + Capture value stored in channel 1 + 1 + + + CC2 + Capture value stored in channel 2 + 2 + + + CC3 + Capture value stored in channel 3 + 3 + + + + + CAPTURE + Fault B Capture Action + 12 + 3 + + CAPTURESelect + + DISABLE + No capture + 0 + + + CAPT + Capture on fault + 1 + + + CAPTMIN + Minimum capture + 2 + + + CAPTMAX + Maximum capture + 3 + + + LOCMIN + Minimum local detection + 4 + + + LOCMAX + Maximum local detection + 5 + + + DERIV0 + Minimum and maximum local detection + 6 + + + CAPTMARK + Capture with ramp index as MSB value + 7 + + + + + BLANKPRESC + Fault B Blanking Prescaler + 15 + 1 + + + BLANKVAL + Fault B Blanking Time + 16 + 8 + + + FILTERVAL + Fault B Filter Value + 24 + 4 + + + + + WEXCTRL + Waveform Extension Configuration + 0x14 + 32 + 0x00000000 + + + OTMX + Output Matrix + 0 + 2 + + + DTIEN0 + Dead-time Insertion Generator 0 Enable + 8 + 1 + + + DTIEN1 + Dead-time Insertion Generator 1 Enable + 9 + 1 + + + DTIEN2 + Dead-time Insertion Generator 2 Enable + 10 + 1 + + + DTIEN3 + Dead-time Insertion Generator 3 Enable + 11 + 1 + + + DTLS + Dead-time Low Side Outputs Value + 16 + 8 + + + DTHS + Dead-time High Side Outputs Value + 24 + 8 + + + + + DRVCTRL + Driver Control + 0x18 + 32 + 0x00000000 + + + NRE0 + Non-Recoverable State 0 Output Enable + 0 + 1 + + + NRE1 + Non-Recoverable State 1 Output Enable + 1 + 1 + + + NRE2 + Non-Recoverable State 2 Output Enable + 2 + 1 + + + NRE3 + Non-Recoverable State 3 Output Enable + 3 + 1 + + + NRE4 + Non-Recoverable State 4 Output Enable + 4 + 1 + + + NRE5 + Non-Recoverable State 5 Output Enable + 5 + 1 + + + NRE6 + Non-Recoverable State 6 Output Enable + 6 + 1 + + + NRE7 + Non-Recoverable State 7 Output Enable + 7 + 1 + + + NRV0 + Non-Recoverable State 0 Output Value + 8 + 1 + + + NRV1 + Non-Recoverable State 1 Output Value + 9 + 1 + + + NRV2 + Non-Recoverable State 2 Output Value + 10 + 1 + + + NRV3 + Non-Recoverable State 3 Output Value + 11 + 1 + + + NRV4 + Non-Recoverable State 4 Output Value + 12 + 1 + + + NRV5 + Non-Recoverable State 5 Output Value + 13 + 1 + + + NRV6 + Non-Recoverable State 6 Output Value + 14 + 1 + + + NRV7 + Non-Recoverable State 7 Output Value + 15 + 1 + + + INVEN0 + Output Waveform 0 Inversion + 16 + 1 + + + INVEN1 + Output Waveform 1 Inversion + 17 + 1 + + + INVEN2 + Output Waveform 2 Inversion + 18 + 1 + + + INVEN3 + Output Waveform 3 Inversion + 19 + 1 + + + INVEN4 + Output Waveform 4 Inversion + 20 + 1 + + + INVEN5 + Output Waveform 5 Inversion + 21 + 1 + + + INVEN6 + Output Waveform 6 Inversion + 22 + 1 + + + INVEN7 + Output Waveform 7 Inversion + 23 + 1 + + + FILTERVAL0 + Non-Recoverable Fault Input 0 Filter Value + 24 + 4 + + + FILTERVAL1 + Non-Recoverable Fault Input 1 Filter Value + 28 + 4 + + + + + DBGCTRL + Debug Control + 0x1E + 8 + 0x00 + + + DBGRUN + Debug Running Mode + 0 + 1 + + + FDDBD + Fault Detection on Debug Break Detection + 2 + 1 + + + + + EVCTRL + Event Control + 0x20 + 32 + 0x00000000 + + + EVACT0 + Timer/counter Input Event0 Action + 0 + 3 + + EVACT0Select + + OFF + Event action disabled + 0 + + + RETRIGGER + Start, restart or re-trigger counter on event + 1 + + + COUNTEV + Count on event + 2 + + + START + Start counter on event + 3 + + + INC + Increment counter on event + 4 + + + COUNT + Count on active state of asynchronous event + 5 + + + STAMP + Stamp capture + 6 + + + FAULT + Non-recoverable fault + 7 + + + + + EVACT1 + Timer/counter Input Event1 Action + 3 + 3 + + EVACT1Select + + OFF + Event action disabled + 0 + + + RETRIGGER + Re-trigger counter on event + 1 + + + DIR + Direction control + 2 + + + STOP + Stop counter on event + 3 + + + DEC + Decrement counter on event + 4 + + + PPW + Period capture value in CC0 register, pulse width capture value in CC1 register + 5 + + + PWP + Period capture value in CC1 register, pulse width capture value in CC0 register + 6 + + + FAULT + Non-recoverable fault + 7 + + + + + CNTSEL + Timer/counter Output Event Mode + 6 + 2 + + CNTSELSelect + + START + An interrupt/event is generated when a new counter cycle starts + 0 + + + END + An interrupt/event is generated when a counter cycle ends + 1 + + + BETWEEN + An interrupt/event is generated when a counter cycle ends, except for the first and last cycles + 2 + + + BOUNDARY + An interrupt/event is generated when a new counter cycle starts or a counter cycle ends + 3 + + + + + OVFEO + Overflow/Underflow Output Event Enable + 8 + 1 + + + TRGEO + Retrigger Output Event Enable + 9 + 1 + + + CNTEO + Timer/counter Output Event Enable + 10 + 1 + + + TCINV0 + Inverted Event 0 Input Enable + 12 + 1 + + + TCINV1 + Inverted Event 1 Input Enable + 13 + 1 + + + TCEI0 + Timer/counter Event 0 Input Enable + 14 + 1 + + + TCEI1 + Timer/counter Event 1 Input Enable + 15 + 1 + + + MCEI0 + Match or Capture Channel 0 Event Input Enable + 16 + 1 + + + MCEI1 + Match or Capture Channel 1 Event Input Enable + 17 + 1 + + + MCEI2 + Match or Capture Channel 2 Event Input Enable + 18 + 1 + + + MCEI3 + Match or Capture Channel 3 Event Input Enable + 19 + 1 + + + MCEO0 + Match or Capture Channel 0 Event Output Enable + 24 + 1 + + + MCEO1 + Match or Capture Channel 1 Event Output Enable + 25 + 1 + + + MCEO2 + Match or Capture Channel 2 Event Output Enable + 26 + 1 + + + MCEO3 + Match or Capture Channel 3 Event Output Enable + 27 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x24 + 32 + 0x00000000 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + TRG + Retrigger Interrupt Enable + 1 + 1 + + + CNT + Counter Interrupt Enable + 2 + 1 + + + ERR + Error Interrupt Enable + 3 + 1 + + + UFS + Non-Recoverable Update Fault Interrupt Enable + 10 + 1 + + + DFS + Non-Recoverable Debug Fault Interrupt Enable + 11 + 1 + + + FAULTA + Recoverable Fault A Interrupt Enable + 12 + 1 + + + FAULTB + Recoverable Fault B Interrupt Enable + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 Interrupt Enable + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 Interrupt Enable + 15 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 16 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 17 + 1 + + + MC2 + Match or Capture Channel 2 Interrupt Enable + 18 + 1 + + + MC3 + Match or Capture Channel 3 Interrupt Enable + 19 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x28 + 32 + 0x00000000 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + TRG + Retrigger Interrupt Enable + 1 + 1 + + + CNT + Counter Interrupt Enable + 2 + 1 + + + ERR + Error Interrupt Enable + 3 + 1 + + + UFS + Non-Recoverable Update Fault Interrupt Enable + 10 + 1 + + + DFS + Non-Recoverable Debug Fault Interrupt Enable + 11 + 1 + + + FAULTA + Recoverable Fault A Interrupt Enable + 12 + 1 + + + FAULTB + Recoverable Fault B Interrupt Enable + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 Interrupt Enable + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 Interrupt Enable + 15 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 16 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 17 + 1 + + + MC2 + Match or Capture Channel 2 Interrupt Enable + 18 + 1 + + + MC3 + Match or Capture Channel 3 Interrupt Enable + 19 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x2C + 32 + 0x00000000 + + + OVF + Overflow + 0 + 1 + + + TRG + Retrigger + 1 + 1 + + + CNT + Counter + 2 + 1 + + + ERR + Error + 3 + 1 + + + UFS + Non-Recoverable Update Fault + 10 + 1 + + + DFS + Non-Recoverable Debug Fault + 11 + 1 + + + FAULTA + Recoverable Fault A + 12 + 1 + + + FAULTB + Recoverable Fault B + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 + 15 + 1 + + + MC0 + Match or Capture 0 + 16 + 1 + + + MC1 + Match or Capture 1 + 17 + 1 + + + MC2 + Match or Capture 2 + 18 + 1 + + + MC3 + Match or Capture 3 + 19 + 1 + + + + + STATUS + Status + 0x30 + 32 + 0x00000001 + + + STOP + Stop + 0 + 1 + + + IDX + Ramp + 1 + 1 + + + UFS + Non-recoverable Update Fault State + 2 + 1 + + + DFS + Non-Recoverable Debug Fault State + 3 + 1 + + + SLAVE + Slave + 4 + 1 + + + PATTBUFV + Pattern Buffer Valid + 5 + 1 + + + PERBUFV + Period Buffer Valid + 7 + 1 + + + FAULTAIN + Recoverable Fault A Input + 8 + 1 + + + FAULTBIN + Recoverable Fault B Input + 9 + 1 + + + FAULT0IN + Non-Recoverable Fault0 Input + 10 + 1 + + + FAULT1IN + Non-Recoverable Fault1 Input + 11 + 1 + + + FAULTA + Recoverable Fault A State + 12 + 1 + + + FAULTB + Recoverable Fault B State + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 State + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 State + 15 + 1 + + + CCBUFV0 + Compare Channel 0 Buffer Valid + 16 + 1 + + + CCBUFV1 + Compare Channel 1 Buffer Valid + 17 + 1 + + + CCBUFV2 + Compare Channel 2 Buffer Valid + 18 + 1 + + + CCBUFV3 + Compare Channel 3 Buffer Valid + 19 + 1 + + + CMP0 + Compare Channel 0 Value + 24 + 1 + + + CMP1 + Compare Channel 1 Value + 25 + 1 + + + CMP2 + Compare Channel 2 Value + 26 + 1 + + + CMP3 + Compare Channel 3 Value + 27 + 1 + + + + + COUNT + Count + 0x34 + 32 + 0x00000000 + + + COUNT + Counter Value + 0 + 24 + + + + + COUNT_DITH4_MODE + Count + COUNT + 0x34 + 32 + 0x00000000 + + + COUNT + Counter Value + 4 + 20 + + + + + COUNT_DITH5_MODE + Count + COUNT + 0x34 + 32 + 0x00000000 + + + COUNT + Counter Value + 5 + 19 + + + + + COUNT_DITH6_MODE + Count + COUNT + 0x34 + 32 + 0x00000000 + + + COUNT + Counter Value + 6 + 18 + + + + + PATT + Pattern + 0x38 + 16 + 0x0000 + + + PGE0 + Pattern Generator 0 Output Enable + 0 + 1 + + + PGE1 + Pattern Generator 1 Output Enable + 1 + 1 + + + PGE2 + Pattern Generator 2 Output Enable + 2 + 1 + + + PGE3 + Pattern Generator 3 Output Enable + 3 + 1 + + + PGE4 + Pattern Generator 4 Output Enable + 4 + 1 + + + PGE5 + Pattern Generator 5 Output Enable + 5 + 1 + + + PGE6 + Pattern Generator 6 Output Enable + 6 + 1 + + + PGE7 + Pattern Generator 7 Output Enable + 7 + 1 + + + PGV0 + Pattern Generator 0 Output Value + 8 + 1 + + + PGV1 + Pattern Generator 1 Output Value + 9 + 1 + + + PGV2 + Pattern Generator 2 Output Value + 10 + 1 + + + PGV3 + Pattern Generator 3 Output Value + 11 + 1 + + + PGV4 + Pattern Generator 4 Output Value + 12 + 1 + + + PGV5 + Pattern Generator 5 Output Value + 13 + 1 + + + PGV6 + Pattern Generator 6 Output Value + 14 + 1 + + + PGV7 + Pattern Generator 7 Output Value + 15 + 1 + + + + + WAVE + Waveform Control + 0x3C + 32 + 0x00000000 + + + WAVEGEN + Waveform Generation + 0 + 3 + + WAVEGENSelect + + NFRQ + Normal frequency + 0 + + + MFRQ + Match frequency + 1 + + + NPWM + Normal PWM + 2 + + + DSCRITICAL + Dual-slope critical + 4 + + + DSBOTTOM + Dual-slope with interrupt/event condition when COUNT reaches ZERO + 5 + + + DSBOTH + Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP + 6 + + + DSTOP + Dual-slope with interrupt/event condition when COUNT reaches TOP + 7 + + + + + RAMP + Ramp Mode + 4 + 2 + + RAMPSelect + + RAMP1 + RAMP1 operation + 0 + + + RAMP2A + Alternative RAMP2 operation + 1 + + + RAMP2 + RAMP2 operation + 2 + + + RAMP2C + Critical RAMP2 operation + 3 + + + + + CIPEREN + Circular period Enable + 7 + 1 + + + CICCEN0 + Circular Channel 0 Enable + 8 + 1 + + + CICCEN1 + Circular Channel 1 Enable + 9 + 1 + + + CICCEN2 + Circular Channel 2 Enable + 10 + 1 + + + CICCEN3 + Circular Channel 3 Enable + 11 + 1 + + + POL0 + Channel 0 Polarity + 16 + 1 + + + POL1 + Channel 1 Polarity + 17 + 1 + + + POL2 + Channel 2 Polarity + 18 + 1 + + + POL3 + Channel 3 Polarity + 19 + 1 + + + SWAP0 + Swap DTI Output Pair 0 + 24 + 1 + + + SWAP1 + Swap DTI Output Pair 1 + 25 + 1 + + + SWAP2 + Swap DTI Output Pair 2 + 26 + 1 + + + SWAP3 + Swap DTI Output Pair 3 + 27 + 1 + + + + + PER + Period + 0x40 + 32 + 0xFFFFFFFF + + + PER + Period Value + 0 + 24 + + + + + PER_DITH4_MODE + Period + PER + 0x40 + 32 + 0xFFFFFFFF + + + DITHER + Dithering Cycle Number + 0 + 4 + + + PER + Period Value + 4 + 20 + + + + + PER_DITH5_MODE + Period + PER + 0x40 + 32 + 0xFFFFFFFF + + + DITHER + Dithering Cycle Number + 0 + 5 + + + PER + Period Value + 5 + 19 + + + + + PER_DITH6_MODE + Period + PER + 0x40 + 32 + 0xFFFFFFFF + + + DITHER + Dithering Cycle Number + 0 + 6 + + + PER + Period Value + 6 + 18 + + + + + 4 + 4 + CC[%s] + Compare and Capture + 0x44 + 32 + 0x00000000 + + + CC + Channel Compare/Capture Value + 0 + 24 + + + + + 4 + 4 + CC_DITH4_MODE[%s] + Compare and Capture + CC[%s] + 0x44 + 32 + 0x00000000 + + + DITHER + Dithering Cycle Number + 0 + 4 + + + CC + Channel Compare/Capture Value + 4 + 20 + + + + + 4 + 4 + CC_DITH5_MODE[%s] + Compare and Capture + CC[%s] + 0x44 + 32 + 0x00000000 + + + DITHER + Dithering Cycle Number + 0 + 5 + + + CC + Channel Compare/Capture Value + 5 + 19 + + + + + 4 + 4 + CC_DITH6_MODE[%s] + Compare and Capture + CC[%s] + 0x44 + 32 + 0x00000000 + + + DITHER + Dithering Cycle Number + 0 + 6 + + + CC + Channel Compare/Capture Value + 6 + 18 + + + + + PATTBUF + Pattern Buffer + 0x64 + 16 + 0x0000 + + + PGEB0 + Pattern Generator 0 Output Enable Buffer + 0 + 1 + + + PGEB1 + Pattern Generator 1 Output Enable Buffer + 1 + 1 + + + PGEB2 + Pattern Generator 2 Output Enable Buffer + 2 + 1 + + + PGEB3 + Pattern Generator 3 Output Enable Buffer + 3 + 1 + + + PGEB4 + Pattern Generator 4 Output Enable Buffer + 4 + 1 + + + PGEB5 + Pattern Generator 5 Output Enable Buffer + 5 + 1 + + + PGEB6 + Pattern Generator 6 Output Enable Buffer + 6 + 1 + + + PGEB7 + Pattern Generator 7 Output Enable Buffer + 7 + 1 + + + PGVB0 + Pattern Generator 0 Output Enable + 8 + 1 + + + PGVB1 + Pattern Generator 1 Output Enable + 9 + 1 + + + PGVB2 + Pattern Generator 2 Output Enable + 10 + 1 + + + PGVB3 + Pattern Generator 3 Output Enable + 11 + 1 + + + PGVB4 + Pattern Generator 4 Output Enable + 12 + 1 + + + PGVB5 + Pattern Generator 5 Output Enable + 13 + 1 + + + PGVB6 + Pattern Generator 6 Output Enable + 14 + 1 + + + PGVB7 + Pattern Generator 7 Output Enable + 15 + 1 + + + + + PERBUF + Period Buffer + 0x6C + 32 + 0xFFFFFFFF + + + PERBUF + Period Buffer Value + 0 + 24 + + + + + PERBUF_DITH4_MODE + Period Buffer + PERBUF + 0x6C + 32 + 0xFFFFFFFF + + + DITHERBUF + Dithering Buffer Cycle Number + 0 + 4 + + + PERBUF + Period Buffer Value + 4 + 20 + + + + + PERBUF_DITH5_MODE + Period Buffer + PERBUF + 0x6C + 32 + 0xFFFFFFFF + + + DITHERBUF + Dithering Buffer Cycle Number + 0 + 5 + + + PERBUF + Period Buffer Value + 5 + 19 + + + + + PERBUF_DITH6_MODE + Period Buffer + PERBUF + 0x6C + 32 + 0xFFFFFFFF + + + DITHERBUF + Dithering Buffer Cycle Number + 0 + 6 + + + PERBUF + Period Buffer Value + 6 + 18 + + + + + 4 + 4 + CCBUF[%s] + Compare and Capture Buffer + 0x70 + 32 + 0x00000000 + + + CCBUF + Channel Compare/Capture Buffer Value + 0 + 24 + + + + + 4 + 4 + CCBUF_DITH4_MODE[%s] + Compare and Capture Buffer + CCBUF[%s] + 0x70 + 32 + 0x00000000 + + + CCBUF + Channel Compare/Capture Buffer Value + 0 + 4 + + + DITHERBUF + Dithering Buffer Cycle Number + 4 + 20 + + + + + 4 + 4 + CCBUF_DITH5_MODE[%s] + Compare and Capture Buffer + CCBUF[%s] + 0x70 + 32 + 0x00000000 + + + DITHERBUF + Dithering Buffer Cycle Number + 0 + 5 + + + CCBUF + Channel Compare/Capture Buffer Value + 5 + 19 + + + + + 4 + 4 + CCBUF_DITH6_MODE[%s] + Compare and Capture Buffer + CCBUF[%s] + 0x70 + 32 + 0x00000000 + + + DITHERBUF + Dithering Buffer Cycle Number + 0 + 6 + + + CCBUF + Channel Compare/Capture Buffer Value + 6 + 18 + + + + + + + TCC1 + 0x42002800 + + TCC1 + 18 + + + + TCC2 + 0x42002C00 + + TCC2 + 19 + + + + WDT + U22511.0.1 + Watchdog Timer + WDT + WDT_ + 0x40002000 + + 0 + 0xD + registers + + + WDT + 1 + + + + CTRLA + Control + 0x0 + 8 + 0x00 + + + ENABLE + Enable + 1 + 1 + + + WEN + Watchdog Timer Window Mode Enable + 2 + 1 + + + ALWAYSON + Always-On + 7 + 1 + + + + + CONFIG + Configuration + 0x1 + 8 + 0xBB + + + PER + Time-Out Period + 0 + 4 + + PERSelect + + CYC8 + 8 clock cycles + 0x0 + + + CYC16 + 16 clock cycles + 0x1 + + + CYC32 + 32 clock cycles + 0x2 + + + CYC64 + 64 clock cycles + 0x3 + + + CYC128 + 128 clock cycles + 0x4 + + + CYC256 + 256 clock cycles + 0x5 + + + CYC512 + 512 clock cycles + 0x6 + + + CYC1024 + 1024 clock cycles + 0x7 + + + CYC2048 + 2048 clock cycles + 0x8 + + + CYC4096 + 4096 clock cycles + 0x9 + + + CYC8192 + 8192 clock cycles + 0xA + + + CYC16384 + 16384 clock cycles + 0xB + + + + + WINDOW + Window Mode Time-Out Period + 4 + 4 + + WINDOWSelect + + CYC8 + 8 clock cycles + 0x0 + + + CYC16 + 16 clock cycles + 0x1 + + + CYC32 + 32 clock cycles + 0x2 + + + CYC64 + 64 clock cycles + 0x3 + + + CYC128 + 128 clock cycles + 0x4 + + + CYC256 + 256 clock cycles + 0x5 + + + CYC512 + 512 clock cycles + 0x6 + + + CYC1024 + 1024 clock cycles + 0x7 + + + CYC2048 + 2048 clock cycles + 0x8 + + + CYC4096 + 4096 clock cycles + 0x9 + + + CYC8192 + 8192 clock cycles + 0xA + + + CYC16384 + 16384 clock cycles + 0xB + + + + + + + EWCTRL + Early Warning Interrupt Control + 0x2 + 8 + 0x0B + + + EWOFFSET + Early Warning Interrupt Time Offset + 0 + 4 + + EWOFFSETSelect + + CYC8 + 8 clock cycles + 0x0 + + + CYC16 + 16 clock cycles + 0x1 + + + CYC32 + 32 clock cycles + 0x2 + + + CYC64 + 64 clock cycles + 0x3 + + + CYC128 + 128 clock cycles + 0x4 + + + CYC256 + 256 clock cycles + 0x5 + + + CYC512 + 512 clock cycles + 0x6 + + + CYC1024 + 1024 clock cycles + 0x7 + + + CYC2048 + 2048 clock cycles + 0x8 + + + CYC4096 + 4096 clock cycles + 0x9 + + + CYC8192 + 8192 clock cycles + 0xA + + + CYC16384 + 16384 clock cycles + 0xB + + + + + + + INTENCLR + Interrupt Enable Clear + 0x4 + 8 + 0x00 + + + EW + Early Warning Interrupt Enable + 0 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x5 + 8 + 0x00 + + + EW + Early Warning Interrupt Enable + 0 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x6 + 8 + 0x00 + + + EW + Early Warning + 0 + 1 + + + + + SYNCBUSY + Synchronization Busy + 0x8 + 32 + read-only + 0x00000000 + + + ENABLE + Enable Busy + 1 + 1 + + + WEN + Window Enable Busy + 2 + 1 + + + ALWAYSON + Always-On Busy + 3 + 1 + + + CLEAR + Clear Busy + 4 + 1 + + + + + CLEAR + Clear + 0xC + 8 + write-only + 0x00 + + + CLEAR + Watchdog Clear + 0 + 8 + + CLEARSelect + + KEY + Clear Key + 0xA5 + + + + + + + + + MPU + Memory Protection Unit + MPU + MPU_ + 0xE000ED90 + + 0 + 0x14 + registers + + + + TYPE + MPU Type Register + 0x0 + 32 + read-only + + + SEPARATE + Separate instruction and Data Memory MapsRegions + 0 + 1 + + + DREGION + Number of Data Regions + 8 + 8 + + + IREGION + Number of Instruction Regions + 16 + 8 + + + + + CTRL + MPU Control Register + 0x4 + 32 + + + ENABLE + MPU Enable + 0 + 1 + + + HFNMIENA + Enable Hard Fault and NMI handlers + 1 + 1 + + + PRIVDEFENA + Enables privileged software access to default memory map + 2 + 1 + + + + + RNR + MPU Region Number Register + 0x8 + 32 + + + REGION + Region referenced by RBAR and RASR + 0 + 8 + + + + + RBAR + MPU Region Base Address Register + 0xC + 32 + + + REGION + Region number + 0 + 4 + + + VALID + Region number valid + 4 + 1 + + + ADDR + Region base address + 5 + 27 + + + + + RASR + MPU Region Attribute and Size Register + 0x10 + 32 + + + ENABLE + Region Enable + 0 + 1 + + + SIZE + Region Size + 1 + 5 + + + SRD + Sub-region disable + 8 + 8 + + + B + Bufferable bit + 16 + 1 + + + C + Cacheable bit + 17 + 1 + + + S + Shareable bit + 18 + 1 + + + TEX + TEX bit + 19 + 3 + + + AP + Access Permission + 24 + 3 + + + XN + Execute Never Attribute + 28 + 1 + + + + + + + NVIC + Nested Vectored Interrupt Controller + NVIC + NVIC_ + 0xE000E100 + + 0 + 0x320 + registers + + + + ISER + Interrupt Set Enable Register + 0x0 + 32 + 0x00000000 + + + SETENA + Interrupt set enable bits + 0 + 31 + + + + + ICER + Interrupt Clear Enable Register + 0x80 + 32 + 0x00000000 + + + CLRENA + Interrupt clear-enable bits + 0 + 31 + + + + + ISPR + Interrupt Set Pending Register + 0x100 + 32 + 0x00000000 + + + SETPEND + Interrupt set-pending bits + 0 + 31 + + + + + ICPR + Interrupt Clear Pending Register + 0x180 + 32 + 0x00000000 + + + CLRPEND + Interrupt clear-pending bits + 0 + 31 + + + + + 8 + 4 + IPR[%s] + Interrupt Priority Register n + 0x300 + 32 + 0x00000000 + + + PRI0 + Priority of interrupt n + 0 + 2 + + + PRI1 + Priority of interrupt n + 8 + 2 + + + PRI2 + Priority of interrupt n + 16 + 2 + + + PRI3 + Priority of interrupt n + 24 + 2 + + + + + + + SysTick + System timer + SysTick + SysTick_ + 0xE000E010 + + 0 + 0x10 + registers + + + + CSR + SysTick Control and Status Register + 0x0 + 32 + 0x4 + + + ENABLE + SysTick Counter Enable + 0 + 1 + + ENABLESelect + + VALUE_0 + Counter disabled + 0 + + + VALUE_1 + Counter enabled + 1 + + + + + TICKINT + SysTick Exception Request Enable + 1 + 1 + + TICKINTSelect + + VALUE_0 + Counting down to 0 does not assert the SysTick exception request + 0 + + + VALUE_1 + Counting down to 0 asserts the SysTick exception request + 1 + + + + + CLKSOURCE + Clock Source 0=external, 1=processor + 2 + 1 + + CLKSOURCESelect + + VALUE_0 + External clock + 0 + + + VALUE_1 + Processor clock + 1 + + + + + COUNTFLAG + Timer counted to 0 since last read of register + 16 + 1 + + + + + RVR + SysTick Reload Value Register + 0x4 + 32 + + + RELOAD + Value to load into the SysTick Current Value Register when the counter reaches 0 + 0 + 24 + + + + + CVR + SysTick Current Value Register + 0x8 + 32 + + + CURRENT + Current value at the time the register is accessed + 0 + 24 + + + + + CALIB + SysTick Calibration Value Register + 0xC + 32 + read-only + 0 + + + TENMS + Reload value to use for 10ms timing + 0 + 24 + + + SKEW + TENMS is rounded from non-integer ratio + 30 + 1 + + SKEWSelect + + VALUE_0 + 10ms calibration value is exact + 0 + + + VALUE_1 + 10ms calibration value is inexact, because of the clock frequency + 1 + + + + + NOREF + No Separate Reference Clock + 31 + 1 + + NOREFSelect + + VALUE_0 + The reference clock is provided + 0 + + + VALUE_1 + The reference clock is not provided + 1 + + + + + + + + + SystemControl + System Control Registers + SystemControl + SystemControl_ + 0xE000E000 + + 0 + 0xD34 + registers + + + + CPUID + CPUID Base Register + 0xD00 + 32 + read-only + 0x410CC601 + + + REVISION + Minor revision number + 0 + 4 + + + PARTNO + Processor Part Number, 0xC60=Cortex-M0+ + 4 + 12 + + + ARCHITECTURE + Processor Architecture, 0xC=ARMv6-M + 16 + 4 + + + VARIANT + Major revision number + 20 + 4 + + + IMPLEMENTER + Implementer code, ARM=0x41 + 24 + 8 + + + + + ICSR + Interrupt Control and State Register + 0xD04 + 32 + 0x00000000 + + + VECTACTIVE + Debug: Exception number of currently executing exception, or 0 if thread mode + 0 + 9 + + + VECTPENDING + Exception number of the highest priority pending enabled exception + 12 + 9 + + + ISRPENDING + Debug: NVIC interrupt pending + 22 + 1 + + + ISRPREEMPT + Debug: Pending exception serviced on exit from debug halt + 23 + 1 + + + PENDSTCLR + SysTick exception clear-pending bit + 25 + 1 + + PENDSTCLRSelect + + VALUE_0 + No effect + 0 + + + VALUE_1 + Removes the pending state from the SysTick exception + 1 + + + + + PENDSTSET + SysTick exception set-pending bit + 26 + 1 + + PENDSTSETSelect + + VALUE_0 + Write: no effect; read: SysTick exception is not pending + 0 + + + VALUE_1 + Write: changes SysTick exception state to pending; read: SysTick exception is pending + 1 + + + + + PENDSVCLR + PendSV clear-pending bit + 27 + 1 + + PENDSVCLRSelect + + VALUE_0 + No effect + 0 + + + VALUE_1 + Removes the pending state from the PendSV exception + 1 + + + + + PENDSVSET + PendSV set-pending bit + 28 + 1 + + PENDSVSETSelect + + VALUE_0 + Write: no effect; read: PendSV exception is not pending + 0 + + + VALUE_1 + Write: changes PendSV exception state to pending; read: PendSV exception is pending + 1 + + + + + NMIPENDSET + NMI set-pending bit + 31 + 1 + + NMIPENDSETSelect + + VALUE_0 + Write: no effect; read: NMI exception is not pending + 0 + + + VALUE_1 + Write: changes NMI exception state to pending; read: NMI exception is pending + 1 + + + + + + + VTOR + Vector Table Offset Register + 0xD08 + 32 + 0x00000000 + + + TBLOFF + Vector table base offset + 7 + 25 + + + + + AIRCR + Application Interrupt and Reset Control Register + 0xD0C + 32 + 0x00000000 + + + VECTCLRACTIVE + Debug: Clear state information + 1 + 1 + + + SYSRESETREQ + System Reset Request + 2 + 1 + + SYSRESETREQSelect + + VALUE_0 + No system reset request + 0 + + + VALUE_1 + Asserts a signal to the outer system that requests a reset + 1 + + + + + ENDIANNESS + Data Endianness, 0=little, 1=big + 15 + 1 + + ENDIANNESSSelect + + VALUE_0 + Little-endian + 0 + + + VALUE_1 + Big-endian + 1 + + + + + VECTKEY + Register key (0x05FA) + 16 + 16 + + + + + SCR + System Control Register + 0xD10 + 32 + 0x00000000 + + + SLEEPONEXIT + Sleep-On-Exit when exiting Handler mode + 1 + 1 + + SLEEPONEXITSelect + + VALUE_0 + O not sleep when returning to Thread mode + 0 + + + VALUE_1 + Enter sleep, or deep sleep, on return from an ISR + 1 + + + + + SLEEPDEEP + Uses Deep Sleep as low power mode + 2 + 1 + + SLEEPDEEPSelect + + VALUE_0 + Sleep + 0 + + + VALUE_1 + Deep sleep + 1 + + + + + SEVONPEND + Send Event on Pending bit + 4 + 1 + + SEVONPENDSelect + + VALUE_0 + Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded + 0 + + + VALUE_1 + Enabled events and all interrupts, including disabled interrupts, can wakeup the processor + 1 + + + + + + + CCR + Configuration and Control Register + 0xD14 + 32 + read-only + 0x00000204 + + + UNALIGN_TRP + Unaligned accesses generates a Hard Fault + 3 + 1 + + UNALIGN_TRPSelect + + VALUE_0 + Do not trap unaligned halfword and word accesses + 0 + + + VALUE_1 + Trap unaligned halfword and word accesses + 1 + + + + + STKALIGN + Stack 8-byte aligned on exception entry + 9 + 1 + + STKALIGNSelect + + VALUE_0 + 4-byte aligned + 0 + + + VALUE_1 + 8-byte aligned + 1 + + + + + + + SHPR2 + System Handler Priority Register 2 + 0xD1C + 32 + 0x00000000 + + + PRI_11 + Priority of system handler 11, SVCall + 24 + 8 + + + + + SHPR3 + System Handler Priority Register 3 + 0xD20 + 32 + 0x00000000 + + + PRI_14 + Priority of system handler 14, PendSV + 16 + 8 + + + PRI_15 + Priority of system handler 15, SysTick exception + 24 + 8 + + + + + SHCSR + System Handler Control and State Register + 0xD24 + 32 + 0x00000000 + + + SVCALLPENDED + 15 + 1 + + + + + DFSR + Debug Fault Status Register + 0xD30 + 32 + 0x00000000 + + + HALTED + Halt request debug event active + 0 + 1 + + + BKPT + Breakpoint debug event + 1 + 1 + + + DWTTRAP + DWT debug event + 2 + 1 + + + VCATCH + Vector catch debug event + 3 + 1 + + + EXTERNAL + EDBGRQ debug event + 4 + 1 + + + + + + + diff --git a/svd/ATSAMC20J18AU.svd b/svd/ATSAMC20J18AU.svd new file mode 100644 index 000000000000..002c6a264508 --- /dev/null +++ b/svd/ATSAMC20J18AU.svd @@ -0,0 +1,21842 @@ + + + + Microchip Technology + MCHP + ATSAMC20J18AU + SAMC20 + 0 + Microchip ATSAMC20J18AU Microcontroller + + CM0+ + r0p0 + selectable + true + false + 2 + false + + 8 + 32 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + AC + U22451.1.1 + Analog Comparators + AC + AC_ + 0x42005000 + + 0 + 0x24 + registers + + + AC + 27 + + + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + + + CTRLB + Control B + 0x1 + 8 + write-only + 0x00 + + + START0 + Comparator 0 Start Comparison + 0 + 1 + + + START1 + Comparator 1 Start Comparison + 1 + 1 + + + + + EVCTRL + Event Control + 0x2 + 16 + 0x0000 + + + COMPEO0 + Comparator 0 Event Output Enable + 0 + 1 + + + COMPEO1 + Comparator 1 Event Output Enable + 1 + 1 + + + WINEO0 + Window 0 Event Output Enable + 4 + 1 + + + COMPEI0 + Comparator 0 Event Input Enable + 8 + 1 + + + COMPEI1 + Comparator 1 Event Input Enable + 9 + 1 + + + INVEI0 + Comparator 0 Input Event Invert Enable + 12 + 1 + + + INVEI1 + Comparator 1 Input Event Invert Enable + 13 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x4 + 8 + 0x00 + + + COMP0 + Comparator 0 Interrupt Enable + 0 + 1 + + + COMP1 + Comparator 1 Interrupt Enable + 1 + 1 + + + WIN0 + Window 0 Interrupt Enable + 4 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x5 + 8 + 0x00 + + + COMP0 + Comparator 0 Interrupt Enable + 0 + 1 + + + COMP1 + Comparator 1 Interrupt Enable + 1 + 1 + + + WIN0 + Window 0 Interrupt Enable + 4 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x6 + 8 + 0x00 + + + COMP0 + Comparator 0 + 0 + 1 + + + COMP1 + Comparator 1 + 1 + 1 + + + WIN0 + Window 0 + 4 + 1 + + + + + STATUSA + Status A + 0x7 + 8 + read-only + 0x00 + + + STATE0 + Comparator 0 Current State + 0 + 1 + + + STATE1 + Comparator 1 Current State + 1 + 1 + + + WSTATE0 + Window 0 Current State + 4 + 2 + + WSTATE0Select + + ABOVE + Signal is above window + 0 + + + INSIDE + Signal is inside window + 1 + + + BELOW + Signal is below window + 2 + + + + + + + STATUSB + Status B + 0x8 + 8 + read-only + 0x00 + + + READY0 + Comparator 0 Ready + 0 + 1 + + + READY1 + Comparator 1 Ready + 1 + 1 + + + + + DBGCTRL + Debug Control + 0x9 + 8 + 0x00 + + + DBGRUN + Debug Run + 0 + 1 + + + + + WINCTRL + Window Control + 0xA + 8 + 0x00 + + + WEN0 + Window 0 Mode Enable + 0 + 1 + + + WINTSEL0 + Window 0 Interrupt Selection + 1 + 2 + + WINTSEL0Select + + ABOVE + Interrupt on signal above window + 0 + + + INSIDE + Interrupt on signal inside window + 1 + + + BELOW + Interrupt on signal below window + 2 + + + OUTSIDE + Interrupt on signal outside window + 3 + + + + + + + 4 + 1 + SCALER[%s] + Scaler n + 0xC + 8 + 0x00 + + + VALUE + Scaler Value + 0 + 6 + + + + + 4 + 4 + COMPCTRL[%s] + Comparator Control n + 0x10 + 32 + 0x00000000 + + + ENABLE + Enable + 1 + 1 + + + SINGLE + Single-Shot Mode + 2 + 1 + + + INTSEL + Interrupt Selection + 3 + 2 + + INTSELSelect + + TOGGLE + Interrupt on comparator output toggle + 0 + + + RISING + Interrupt on comparator output rising + 1 + + + FALLING + Interrupt on comparator output falling + 2 + + + EOC + Interrupt on end of comparison (single-shot mode only) + 3 + + + + + RUNSTDBY + Run in Standby + 6 + 1 + + + MUXNEG + Negative Input Mux Selection + 8 + 3 + + MUXNEGSelect + + PIN0 + I/O pin 0 + 0 + + + PIN1 + I/O pin 1 + 1 + + + PIN2 + I/O pin 2 + 2 + + + PIN3 + I/O pin 3 + 3 + + + GND + Ground + 4 + + + VSCALE + VDD scaler + 5 + + + BANDGAP + Internal bandgap voltage + 6 + + + + + MUXPOS + Positive Input Mux Selection + 12 + 3 + + MUXPOSSelect + + PIN0 + I/O pin 0 + 0 + + + PIN1 + I/O pin 1 + 1 + + + PIN2 + I/O pin 2 + 2 + + + PIN3 + I/O pin 3 + 3 + + + VSCALE + VDD Scaler + 4 + + + + + SWAP + Swap Inputs and Invert + 15 + 1 + + + SPEED + Speed Selection + 16 + 2 + + SPEEDSelect + + LOW + Low speed + 0 + + + HIGH + High speed + 3 + + + + + HYSTEN + Hysteresis Enable + 19 + 1 + + + FLEN + Filter Length + 24 + 3 + + FLENSelect + + OFF + No filtering + 0 + + + MAJ3 + 3-bit majority function (2 of 3) + 1 + + + MAJ5 + 5-bit majority function (3 of 5) + 2 + + + + + OUT + Output + 28 + 2 + + OUTSelect + + OFF + The output of COMPn is not routed to the COMPn I/O port + 0 + + + ASYNC + The asynchronous output of COMPn is routed to the COMPn I/O port + 1 + + + SYNC + The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port + 2 + + + + + + + SYNCBUSY + Synchronization Busy + 0x20 + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + Enable Synchronization Busy + 1 + 1 + + + WINCTRL + WINCTRL Synchronization Busy + 2 + 1 + + + COMPCTRL0 + COMPCTRL 0 Synchronization Busy + 3 + 1 + + + COMPCTRL1 + COMPCTRL 1 Synchronization Busy + 4 + 1 + + + + + + + ADC0 + U22472.2.0 + Analog Digital Converter + ADC + ADC_ + 0x42004400 + + 0 + 0x2E + registers + + + ADC0 + 25 + + + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + SLAVEEN + Slave Enable + 5 + 1 + + + RUNSTDBY + Run During Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + + + CTRLB + Control B + 0x1 + 8 + 0x00 + + + PRESCALER + Prescaler Configuration + 0 + 3 + + PRESCALERSelect + + DIV2 + Peripheral clock / 2 + 0x0 + + + DIV4 + Peripheral clock / 4 + 0x1 + + + DIV8 + Peripheral clock / 8 + 0x2 + + + DIV16 + Peripheral clock / 16 + 0x3 + + + DIV32 + Peripheral clock / 32 + 0x4 + + + DIV64 + Peripheral clock / 64 + 0x5 + + + DIV128 + Peripheral clock / 128 + 0x6 + + + DIV256 + Peripheral clock / 256 + 0x7 + + + + + + + REFCTRL + Reference Control + 0x2 + 8 + 0x00 + + + REFSEL + Reference Selection + 0 + 4 + + REFSELSelect + + INTREF + Internal Bandgap Reference + 0x0 + + + INTVCC0 + 1/1.6 VDDANA + 0x1 + + + INTVCC1 + 1/2 VDDANA + 0x2 + + + AREFA + External Reference + 0x3 + + + INTVCC2 + VDDANA + 0x5 + + + + + REFCOMP + Reference Buffer Offset Compensation Enable + 7 + 1 + + + + + EVCTRL + Event Control + 0x3 + 8 + 0x00 + + + FLUSHEI + Flush Event Input Enable + 0 + 1 + + + STARTEI + Start Conversion Event Input Enable + 1 + 1 + + + FLUSHINV + Flush Event Invert Enable + 2 + 1 + + + STARTINV + Start Event Invert Enable + 3 + 1 + + + RESRDYEO + Result Ready Event Out + 4 + 1 + + + WINMONEO + Window Monitor Event Out + 5 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x4 + 8 + 0x00 + + + RESRDY + Result Ready Interrupt Disable + 0 + 1 + + + OVERRUN + Overrun Interrupt Disable + 1 + 1 + + + WINMON + Window Monitor Interrupt Disable + 2 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x5 + 8 + 0x00 + + + RESRDY + Result Ready Interrupt Enable + 0 + 1 + + + OVERRUN + Overrun Interrupt Enable + 1 + 1 + + + WINMON + Window Monitor Interrupt Enable + 2 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x6 + 8 + 0x00 + + + RESRDY + Result Ready Interrupt Flag + 0 + 1 + + + OVERRUN + Overrun Interrupt Flag + 1 + 1 + + + WINMON + Window Monitor Interrupt Flag + 2 + 1 + + + + + SEQSTATUS + Sequence Status + 0x7 + 8 + read-only + 0x00 + + + SEQSTATE + Sequence State + 0 + 5 + + + SEQBUSY + Sequence Busy + 7 + 1 + + + + + INPUTCTRL + Input Control + 0x8 + 16 + 0x0000 + + + MUXPOS + Positive Mux Input Selection + 0 + 5 + + MUXPOSSelect + + AIN0 + ADC AIN0 Pin + 0x0 + + + AIN1 + ADC AIN1 Pin + 0x1 + + + AIN2 + ADC AIN2 Pin + 0x2 + + + AIN3 + ADC AIN3 Pin + 0x3 + + + AIN4 + ADC AIN4 Pin + 0x4 + + + AIN5 + ADC AIN5 Pin + 0x5 + + + AIN6 + ADC AIN6 Pin + 0x6 + + + AIN7 + ADC AIN7 Pin + 0x7 + + + AIN8 + ADC AIN8 Pin + 0x8 + + + AIN9 + ADC AIN9 Pin + 0x9 + + + AIN10 + ADC AIN10 Pin + 0xA + + + AIN11 + ADC AIN11 Pin + 0xB + + + BANDGAP + Bandgap Voltage + 0x19 + + + SCALEDCOREVCC + 1/4 Scaled Core Supply + 0x1A + + + SCALEDIOVCC + 1/4 Scaled I/O Supply + 0x1B + + + + + MUXNEG + Negative Mux Input Selection + 8 + 5 + + MUXNEGSelect + + AIN0 + ADC AIN0 Pin + 0x0 + + + AIN1 + ADC AIN1 Pin + 0x1 + + + AIN2 + ADC AIN2 Pin + 0x2 + + + AIN3 + ADC AIN3 Pin + 0x3 + + + AIN4 + ADC AIN4 Pin + 0x4 + + + AIN5 + ADC AIN5 Pin + 0x5 + + + GND + Internal Ground + 0x18 + + + + + + + CTRLC + Control C + 0xA + 16 + 0x0000 + + + DIFFMODE + Differential Mode + 0 + 1 + + + LEFTADJ + Left-Adjusted Result + 1 + 1 + + + FREERUN + Free Running Mode + 2 + 1 + + + CORREN + Digital Correction Logic Enable + 3 + 1 + + + RESSEL + Conversion Result Resolution + 4 + 2 + + RESSELSelect + + 12BIT + 12-bit + 0x0 + + + 16BIT + 16-bit averaging mode + 0x1 + + + 10BIT + 10-bit + 0x2 + + + 8BIT + 8-bit + 0x3 + + + + + R2R + Rail-to-Rail mode enable + 7 + 1 + + + WINMODE + Window Monitor Mode + 8 + 3 + + WINMODESelect + + DISABLE + No window mode (default) + 0 + + + MODE1 + RESULT > WINLT + 1 + + + MODE2 + RESULT < WINUT + 2 + + + MODE3 + WINLT < RESULT < WINUT + 3 + + + MODE4 + !(WINLT < RESULT < WINUT) + 4 + + + + + + + AVGCTRL + Average Control + 0xC + 8 + 0x00 + + + SAMPLENUM + Number of Samples to be Collected + 0 + 4 + + SAMPLENUMSelect + + 1 + 1 sample + 0x0 + + + 2 + 2 samples + 0x1 + + + 4 + 4 samples + 0x2 + + + 8 + 8 samples + 0x3 + + + 16 + 16 samples + 0x4 + + + 32 + 32 samples + 0x5 + + + 64 + 64 samples + 0x6 + + + 128 + 128 samples + 0x7 + + + 256 + 256 samples + 0x8 + + + 512 + 512 samples + 0x9 + + + 1024 + 1024 samples + 0xA + + + + + ADJRES + Adjusting Result / Division Coefficient + 4 + 3 + + + + + SAMPCTRL + Sample Time Control + 0xD + 8 + 0x00 + + + SAMPLEN + Sampling Time Length + 0 + 6 + + + OFFCOMP + Comparator Offset Compensation Enable + 7 + 1 + + + + + WINLT + Window Monitor Lower Threshold + 0xE + 16 + 0x0000 + + + WINLT + Window Lower Threshold + 0 + 16 + + + + + WINUT + Window Monitor Upper Threshold + 0x10 + 16 + 0x0000 + + + WINUT + Window Upper Threshold + 0 + 16 + + + + + GAINCORR + Gain Correction + 0x12 + 16 + 0x0000 + + + GAINCORR + Gain Correction Value + 0 + 12 + + + + + OFFSETCORR + Offset Correction + 0x14 + 16 + 0x0000 + + + OFFSETCORR + Offset Correction Value + 0 + 12 + + + + + SWTRIG + Software Trigger + 0x18 + 8 + 0x00 + + + FLUSH + ADC Flush + 0 + 1 + + + START + Start ADC Conversion + 1 + 1 + + + + + DBGCTRL + Debug Control + 0x1C + 8 + 0x00 + + + DBGRUN + Debug Run + 0 + 1 + + + + + SYNCBUSY + Synchronization Busy + 0x20 + 16 + read-only + 0x0000 + + + SWRST + SWRST Synchronization Busy + 0 + 1 + + + ENABLE + ENABLE Synchronization Busy + 1 + 1 + + + INPUTCTRL + INPUTCTRL Synchronization Busy + 2 + 1 + + + CTRLC + CTRLC Synchronization Busy + 3 + 1 + + + AVGCTRL + AVGCTRL Synchronization Busy + 4 + 1 + + + SAMPCTRL + SAMPCTRL Synchronization Busy + 5 + 1 + + + WINLT + WINLT Synchronization Busy + 6 + 1 + + + WINUT + WINUT Synchronization Busy + 7 + 1 + + + GAINCORR + GAINCORR Synchronization Busy + 8 + 1 + + + OFFSETCORR + OFFSETCTRL Synchronization Busy + 9 + 1 + + + SWTRIG + SWTRG Synchronization Busy + 10 + 1 + + + + + RESULT + Result + 0x24 + 16 + read-only + 0x0000 + + + RESULT + Result Value + 0 + 16 + + + + + SEQCTRL + Sequence Control + 0x28 + 32 + 0x00000000 + + + SEQEN + Enable Positive Input in the Sequence + 0 + 32 + + + + + CALIB + Calibration + 0x2C + 16 + 0x0000 + + + BIASCOMP + Bias Comparator Scaling + 0 + 3 + + + BIASREFBUF + Bias Reference Buffer Scaling + 8 + 3 + + + + + + + CCL + U22251.0.1 + Configurable Custom Logic + CCL + CCL_ + 0x42005C00 + + 0 + 0x18 + registers + + + + CTRL + Control + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + RUNSTDBY + Run during Standby + 6 + 1 + + + + + 2 + 1 + SEQCTRL[%s] + SEQ Control x + 0x4 + 8 + 0x00 + + + SEQSEL + Sequential Selection + 0 + 4 + + SEQSELSelect + + DISABLE + Sequential logic is disabled + 0 + + + DFF + D flip flop + 1 + + + JK + JK flip flop + 2 + + + LATCH + D latch + 3 + + + RS + RS latch + 4 + + + + + + + 4 + 4 + LUTCTRL[%s] + LUT Control x + 0x8 + 32 + 0x00000000 + + + ENABLE + LUT Enable + 1 + 1 + + + FILTSEL + Filter Selection + 4 + 2 + + FILTSELSelect + + DISABLE + Filter disabled + 0 + + + SYNCH + Synchronizer enabled + 1 + + + FILTER + Filter enabled + 2 + + + + + EDGESEL + Edge Selection + 7 + 1 + + + INSEL0 + Input Selection 0 + 8 + 4 + + INSEL0Select + + MASK + Masked input + 0 + + + FEEDBACK + Feedback input source + 1 + + + LINK + Linked LUT input source + 2 + + + EVENT + Event in put source + 3 + + + IO + I/O pin input source + 4 + + + AC + AC input source + 5 + + + TC + TC input source + 6 + + + ALTTC + Alternate TC input source + 7 + + + TCC + TCC input source + 8 + + + SERCOM + SERCOM inout source + 9 + + + + + INSEL1 + Input Selection 1 + 12 + 4 + + + INSEL2 + Input Selection 2 + 16 + 4 + + + INVEI + Input Event Invert + 20 + 1 + + + LUTEI + Event Input Enable + 21 + 1 + + + LUTEO + Event Output Enable + 22 + 1 + + + TRUTH + Truth Value + 24 + 8 + + + + + + + DIVAS + U22581.0.0 + Divide and Square Root Accelerator + DIVAS + DIVAS_ + 0x48000000 + + 0 + 0x1C + registers + + + + CTRLA + Control + 0x0 + 8 + 0x00 + + + SIGNED + Signed + 0 + 1 + + + DLZ + Disable Leading Zero Optimization + 1 + 1 + + + + + STATUS + Status + 0x4 + 8 + 0x00 + + + BUSY + DIVAS Accelerator Busy + 0 + 1 + + + DBZ + Writing a one to this bit clears DBZ to zero + 1 + 1 + + + + + DIVIDEND + Dividend + 0x8 + 32 + 0x00000000 + + + DIVIDEND + DIVIDEND + 0 + 32 + + + + + DIVISOR + Divisor + 0xC + 32 + 0x00000000 + + + DIVISOR + DIVISOR + 0 + 32 + + + + + RESULT + Result + 0x10 + 32 + read-only + 0x00000000 + + + RESULT + RESULT + 0 + 32 + + + + + REM + Remainder + 0x14 + 32 + read-only + 0x00000000 + + + REM + REM + 0 + 32 + + + + + SQRNUM + Square Root Input + 0x18 + 32 + 0x00000000 + + + SQRNUM + Square Root Input + 0 + 32 + + + + + + + DMAC + U22232.2.3 + Direct Memory Access Controller + DMAC + DMAC_ + 0x41006000 + + 0 + 0x50 + registers + + + DMAC + 7 + + + + CTRL + Control + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + DMAENABLE + DMA Enable + 1 + 1 + + + CRCENABLE + CRC Enable + 2 + 1 + + + LVLEN0 + Priority Level 0 Enable + 8 + 1 + + + LVLEN1 + Priority Level 1 Enable + 9 + 1 + + + LVLEN2 + Priority Level 2 Enable + 10 + 1 + + + LVLEN3 + Priority Level 3 Enable + 11 + 1 + + + + + CRCCTRL + CRC Control + 0x2 + 16 + 0x0000 + + + CRCBEATSIZE + CRC Beat Size + 0 + 2 + + CRCBEATSIZESelect + + BYTE + 8-bit bus transfer + 0x0 + + + HWORD + 16-bit bus transfer + 0x1 + + + WORD + 32-bit bus transfer + 0x2 + + + + + CRCPOLY + CRC Polynomial Type + 2 + 2 + + CRCPOLYSelect + + CRC16 + CRC-16 (CRC-CCITT) + 0x0 + + + CRC32 + CRC32 (IEEE 802.3) + 0x1 + + + + + CRCSRC + CRC Input Source + 8 + 6 + + CRCSRCSelect + + NOACT + No action + 0x00 + + + IO + I/O interface + 0x01 + + + + + + + CRCDATAIN + CRC Data Input + 0x4 + 32 + 0x00000000 + + + CRCDATAIN + CRC Data Input + 0 + 32 + + + + + CRCCHKSUM + CRC Checksum + 0x8 + 32 + 0x00000000 + + + CRCCHKSUM + CRC Checksum + 0 + 32 + + + + + CRCSTATUS + CRC Status + 0xC + 8 + 0x00 + + + CRCBUSY + CRC Module Busy + 0 + 1 + + + CRCZERO + CRC Zero + 1 + 1 + + + + + DBGCTRL + Debug Control + 0xD + 8 + 0x00 + + + DBGRUN + Debug Run + 0 + 1 + + + + + QOSCTRL + QOS Control + 0xE + 8 + 0x2A + + + WRBQOS + Write-Back Quality of Service + 0 + 2 + + WRBQOSSelect + + DISABLE + Background (no sensitive operation) + 0x0 + + + LOW + Sensitive Bandwidth + 0x1 + + + MEDIUM + Sensitive Latency + 0x2 + + + HIGH + Critical Latency + 0x3 + + + + + FQOS + Fetch Quality of Service + 2 + 2 + + FQOSSelect + + DISABLE + Background (no sensitive operation) + 0x0 + + + LOW + Sensitive Bandwidth + 0x1 + + + MEDIUM + Sensitive Latency + 0x2 + + + HIGH + Critical Latency + 0x3 + + + + + DQOS + Data Transfer Quality of Service + 4 + 2 + + DQOSSelect + + DISABLE + Background (no sensitive operation) + 0x0 + + + LOW + Sensitive Bandwidth + 0x1 + + + MEDIUM + Sensitive Latency + 0x2 + + + HIGH + Critical Latency + 0x3 + + + + + + + SWTRIGCTRL + Software Trigger Control + 0x10 + 32 + 0x00000000 + + + SWTRIG0 + Channel 0 Software Trigger + 0 + 1 + + + SWTRIG1 + Channel 1 Software Trigger + 1 + 1 + + + SWTRIG2 + Channel 2 Software Trigger + 2 + 1 + + + SWTRIG3 + Channel 3 Software Trigger + 3 + 1 + + + SWTRIG4 + Channel 4 Software Trigger + 4 + 1 + + + SWTRIG5 + Channel 5 Software Trigger + 5 + 1 + + + + + PRICTRL0 + Priority Control 0 + 0x14 + 32 + 0x00000000 + + + LVLPRI0 + Level 0 Channel Priority Number + 0 + 3 + + + RRLVLEN0 + Level 0 Round-Robin Scheduling Enable + 7 + 1 + + RRLVLEN0Select + + STATIC_LVL + Static arbitration scheme for channels with level 3 priority + 0x0 + + + ROUND_ROBIN_LVL + Round-robin arbitration scheme for channels with level 3 priority + 0x1 + + + + + LVLPRI1 + Level 1 Channel Priority Number + 8 + 3 + + + RRLVLEN1 + Level 1 Round-Robin Scheduling Enable + 15 + 1 + + + LVLPRI2 + Level 2 Channel Priority Number + 16 + 3 + + + RRLVLEN2 + Level 2 Round-Robin Scheduling Enable + 23 + 1 + + + LVLPRI3 + Level 3 Channel Priority Number + 24 + 3 + + + RRLVLEN3 + Level 3 Round-Robin Scheduling Enable + 31 + 1 + + + + + INTPEND + Interrupt Pending + 0x20 + 16 + 0x0000 + + + ID + Channel ID + 0 + 3 + + + TERR + Transfer Error + 8 + 1 + + + TCMPL + Transfer Complete + 9 + 1 + + + SUSP + Channel Suspend + 10 + 1 + + + FERR + Fetch Error + 13 + 1 + + + BUSY + Busy + 14 + 1 + + + PEND + Pending + 15 + 1 + + + + + INTSTATUS + Interrupt Status + 0x24 + 32 + read-only + 0x00000000 + + + CHINT0 + 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clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + + + GENCTRL2 + Generic Clock Generator Control 2 Synchronization Busy bits + 4 + 1 + + GENCTRL2Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + + + GENCTRL3 + Generic Clock Generator Control 3 Synchronization Busy bits + 5 + 1 + + GENCTRL3Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + + + GENCTRL4 + Generic Clock Generator Control 4 Synchronization Busy bits + 6 + 1 + + GENCTRL4Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + + + GENCTRL5 + Generic Clock Generator Control 5 Synchronization Busy bits + 7 + 1 + + GENCTRL5Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + + + GENCTRL6 + Generic Clock Generator Control 6 Synchronization Busy bits + 8 + 1 + + GENCTRL6Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + + + GENCTRL7 + Generic Clock Generator Control 7 Synchronization Busy bits + 9 + 1 + + GENCTRL7Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + + + GENCTRL8 + Generic Clock Generator Control 8 Synchronization Busy bits + 10 + 1 + + GENCTRL8Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + + + + + 9 + 4 + GENCTRL[%s] + Generic Clock Generator Control + 0x20 + 32 + 0x00000000 + + + SRC + Source Select + 0 + 3 + + SRCSelect + + XOSC + XOSC oscillator output + 0 + + + GCLKIN + Generator input pad + 1 + + + GCLKGEN1 + Generic clock generator 1 output + 2 + + + OSCULP32K + OSCULP32K oscillator output + 3 + + + OSC32K + OSC32K oscillator output + 4 + + + XOSC32K + XOSC32K oscillator output + 5 + + + OSC48M + OSC48M oscillator output + 6 + + + DPLL96M + DPLL96M output + 7 + + + + + GENEN + Generic Clock Generator Enable + 8 + 1 + + + IDC + Improve Duty Cycle + 9 + 1 + + + OOV + Output Off Value + 10 + 1 + + + OE + Output Enable + 11 + 1 + + + DIVSEL + Divide Selection + 12 + 1 + + DIVSELSelect + + DIV1 + Divide input directly by divider factor + 0x0 + + + DIV2 + Divide input by 2^(divider factor+ 1) + 0x1 + + + + + RUNSTDBY + Run in Standby + 13 + 1 + + + DIV + Division Factor + 16 + 16 + + + + + 41 + 4 + PCHCTRL[%s] + Peripheral Clock Control + 0x80 + 32 + 0x00000000 + + + GEN + Generic Clock Generator + 0 + 4 + + GENSelect + + GCLK0 + Generic clock generator 0 + 0x0 + + + GCLK1 + Generic clock generator 1 + 0x1 + + + GCLK2 + Generic clock generator 2 + 0x2 + + + GCLK3 + Generic clock generator 3 + 0x3 + + + GCLK4 + Generic clock generator 4 + 0x4 + + + GCLK5 + Generic clock generator 5 + 0x5 + + + GCLK6 + Generic clock generator 6 + 0x6 + + + GCLK7 + Generic clock generator 7 + 0x7 + + + GCLK8 + Generic clock generator 8 + 0x8 + + + + + CHEN + Channel Enable + 6 + 1 + + + WRTLOCK + Write Lock + 7 + 1 + + + + + + + HMATRIXHS + I76382.1.3 + HSB Matrix + HMATRIXB + HMATRIXB_ + 0x4100A000 + + 0 + 0x168 + registers + + + + 16 + 4 + MCFG[%s] + Master Configuration + 0x0 + 32 + 0x00000002 + + + ULBT + Undefined Length Burst Type + 0 + 3 + + ULBTSelect + + INFINITE + Infinite Length + 0 + + + SINGLE + Single Access + 1 + + + FOUR_BEAT + Four Beat Burst + 2 + + + EIGHT_BEAT + Eight Beat Burst + 3 + + + SIXTEEN_BEAT + Sixteen Beat Burst + 4 + + + + + + + 16 + 4 + SCFG[%s] + Slave Configuration + 0x40 + 32 + 0x00000010 + + + SLOT_CYCLE + Maximum Number of Allowed Cycles for a Burst + 0 + 8 + + + DEFMSTR_TYPE + Default Master Type + 16 + 2 + + DEFMSTR_TYPESelect + + NO_DEFAULT + No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. + 0 + + + LAST_DEFAULT + Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. + 1 + + + FIXED_DEFAULT + Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave. + 2 + + + + + FIXED_DEFMSTR + Fixed Index of Default Master + 18 + 4 + + + ARBT + Arbitration Type + 24 + 1 + + ARBTSelect + + ROUND_ROBIN + Round-Robin Arbitration + 0 + + + FIXED_PRIORITY + Fixed Priority Arbitration + 1 + + + + + + + 4 + 0x8 + PRS[%s] + + 0x080 + + PRAS + Priority A for Slave + 0x0 + 32 + 0x00000000 + + + M0PR + Master 0 Priority + 0 + 4 + + + M1PR + Master 1 Priority + 4 + 4 + + + M2PR + Master 2 Priority + 8 + 4 + + + M3PR + Master 3 Priority + 12 + 4 + + + M4PR + Master 4 Priority + 16 + 4 + + + M5PR + Master 5 Priority + 20 + 4 + + + M6PR + Master 6 Priority + 24 + 4 + + + M7PR + Master 7 Priority + 28 + 4 + + + + + PRBS + Priority B for Slave + 0x4 + 32 + 0x00000000 + + + M8PR + Master 8 Priority + 0 + 4 + + + M9PR + Master 9 Priority + 4 + 4 + + + M10PR + Master 10 Priority + 8 + 4 + + + M11PR + Master 11 Priority + 12 + 4 + + + M12PR + Master 12 Priority + 16 + 4 + + + M13PR + Master 13 Priority + 20 + 4 + + + M14PR + Master 14 Priority + 24 + 4 + + + M15PR + Master 15 Priority + 28 + 4 + + + + + + MRCR + Master Remap Control + 0x100 + 32 + 0x00000000 + + + RCB0 + Remap Command Bit for Master 0 + 0 + 1 + + RCB0Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB1 + Remap Command Bit for Master 1 + 1 + 1 + + RCB1Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB2 + Remap Command Bit for Master 2 + 2 + 1 + + RCB2Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB3 + Remap Command Bit for Master 3 + 3 + 1 + + RCB3Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB4 + Remap Command Bit for Master 4 + 4 + 1 + + RCB4Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB5 + Remap Command Bit for Master 5 + 5 + 1 + + RCB5Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB6 + Remap Command Bit for Master 6 + 6 + 1 + + RCB6Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB7 + Remap Command Bit for Master 7 + 7 + 1 + + RCB7Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB8 + Remap Command Bit for Master 8 + 8 + 1 + + RCB8Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB9 + Remap Command Bit for Master 9 + 9 + 1 + + RCB9Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB10 + Remap Command Bit for Master 10 + 10 + 1 + + RCB10Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB11 + Remap Command Bit for Master 11 + 11 + 1 + + RCB11Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB12 + Remap Command Bit for Master 12 + 12 + 1 + + RCB12Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB13 + Remap Command Bit for Master 13 + 13 + 1 + + RCB13Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB14 + Remap Command Bit for Master 14 + 14 + 1 + + RCB14Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB15 + Remap Command Bit for Master 15 + 15 + 1 + + RCB15Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + + + 16 + 4 + SFR[%s] + Special Function + 0x110 + 32 + 0x00000000 + + + SFR + Special Function Register + 0 + 32 + + + + + + + MCLK + U22342.0.0 + Main Clock + MCLK + MCLK_ + 0x40000800 + + 0 + 0x20 + registers + + + + INTENCLR + Interrupt Enable Clear + 0x1 + 8 + 0x00 + + + CKRDY + Clock Ready Interrupt Enable + 0 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x2 + 8 + 0x00 + + + CKRDY + Clock Ready Interrupt Enable + 0 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x3 + 8 + 0x01 + + + CKRDY + Clock Ready + 0 + 1 + + + + + CPUDIV + CPU Clock Division + 0x4 + 8 + 0x01 + + + CPUDIV + CPU Clock Division Factor + 0 + 8 + + CPUDIVSelect + + DIV1 + Divide by 1 + 0x01 + + + DIV2 + Divide by 2 + 0x02 + + + DIV4 + Divide by 4 + 0x04 + + + DIV8 + Divide by 8 + 0x08 + + + DIV16 + Divide by 16 + 0x10 + + + DIV32 + Divide by 32 + 0x20 + + + DIV64 + Divide by 64 + 0x40 + + + DIV128 + Divide by 128 + 0x80 + + + + + + + AHBMASK + AHB Mask + 0x10 + 32 + 0x00001CFF + + + HPB0_ + HPB0 AHB Clock Mask + 0 + 1 + + + HPB1_ + HPB1 AHB Clock Mask + 1 + 1 + + + HPB2_ + HPB2 AHB Clock Mask + 2 + 1 + + + DSU_ + DSU AHB Clock Mask + 3 + 1 + + + HMATRIXHS_ + HMATRIXHS AHB Clock Mask + 4 + 1 + + + NVMCTRL_ + NVMCTRL AHB Clock Mask + 5 + 1 + + + HSRAM_ + HSRAM AHB Clock Mask + 6 + 1 + + + DMAC_ + DMAC AHB Clock Mask + 7 + 1 + + + PAC_ + PAC AHB Clock Mask + 10 + 1 + + + NVMCTRL_PICACHU_ + NVMCTRL_PICACHU AHB Clock Mask + 11 + 1 + + + DIVAS_ + DIVAS AHB Clock Mask + 12 + 1 + + + + + APBAMASK + APBA Mask + 0x14 + 32 + 0x00000FFF + + + PAC_ + PAC APB Clock Enable + 0 + 1 + + + PM_ + PM APB Clock Enable + 1 + 1 + + + MCLK_ + MCLK APB Clock Enable + 2 + 1 + + + RSTC_ + RSTC APB Clock Enable + 3 + 1 + + + OSCCTRL_ + OSCCTRL APB Clock Enable + 4 + 1 + + + OSC32KCTRL_ + OSC32KCTRL APB Clock Enable + 5 + 1 + + + SUPC_ + SUPC APB Clock Enable + 6 + 1 + + + GCLK_ + GCLK APB Clock Enable + 7 + 1 + + + WDT_ + WDT APB Clock Enable + 8 + 1 + + + RTC_ + RTC APB Clock Enable + 9 + 1 + + + EIC_ + EIC APB Clock Enable + 10 + 1 + + + FREQM_ + FREQM APB Clock Enable + 11 + 1 + + + + + APBBMASK + APBB Mask + 0x18 + 32 + 0x00000007 + + + PORT_ + PORT APB Clock Enable + 0 + 1 + + + DSU_ + DSU APB Clock Enable + 1 + 1 + + + NVMCTRL_ + NVMCTRL APB Clock Enable + 2 + 1 + + + HMATRIXHS_ + HMATRIXHS APB Clock Enable + 5 + 1 + + + + + APBCMASK + APBC Mask + 0x1C + 32 + 0x00000000 + + + EVSYS_ + EVSYS APB Clock Enable + 0 + 1 + + + SERCOM0_ + SERCOM0 APB Clock Enable + 1 + 1 + + + SERCOM1_ + SERCOM1 APB Clock Enable + 2 + 1 + + + SERCOM2_ + SERCOM2 APB Clock Enable + 3 + 1 + + + SERCOM3_ + SERCOM3 APB Clock Enable + 4 + 1 + + + TCC0_ + TCC0 APB Clock Enable + 9 + 1 + + + TCC1_ + TCC1 APB Clock Enable + 10 + 1 + + + TCC2_ + TCC2 APB Clock Enable + 11 + 1 + + + TC0_ + TC0 APB Clock Enable + 12 + 1 + + + TC1_ + TC1 APB Clock Enable + 13 + 1 + + + TC2_ + TC2 APB Clock Enable + 14 + 1 + + + TC3_ + TC3 APB Clock Enable + 15 + 1 + + + TC4_ + TC4 APB Clock Enable + 16 + 1 + + + ADC0_ + ADC0 APB Clock Enable + 17 + 1 + + + AC_ + AC APB Clock Enable + 20 + 1 + + + PTC_ + PTC APB Clock Enable + 22 + 1 + + + CCL_ + CCL APB Clock Enable + 23 + 1 + + + + + + + MTB + U20021.0.0 + Cortex-M0+ Micro-Trace Buffer + MTB + MTB_ + 0x41008000 + + 0 + 0x1000 + registers + + + + POSITION + MTB Position + 0x0 + 32 + + + WRAP + Pointer Value Wraps + 2 + 1 + + + POINTER + Trace Packet Location Pointer + 3 + 29 + + + + + MASTER + MTB Master + 0x4 + 32 + 0x00000000 + + + MASK + Maximum Value of the Trace Buffer in SRAM + 0 + 5 + + + TSTARTEN + Trace Start Input Enable + 5 + 1 + + + TSTOPEN + Trace Stop Input Enable + 6 + 1 + + + SFRWPRIV + Special Function Register Write Privilege + 7 + 1 + + + RAMPRIV + SRAM Privilege + 8 + 1 + + + HALTREQ + Halt Request + 9 + 1 + + + EN + Main Trace Enable + 31 + 1 + + + + + FLOW + MTB Flow + 0x8 + 32 + 0x00000000 + + + AUTOSTOP + Auto Stop Tracing + 0 + 1 + + + AUTOHALT + Auto Halt Request + 1 + 1 + + + WATERMARK + Watermark value + 3 + 29 + + + + + BASE + MTB Base + 0xC + 32 + read-only + + + ITCTRL + MTB Integration Mode Control + 0xF00 + 32 + + + CLAIMSET + MTB Claim Set + 0xFA0 + 32 + + + CLAIMCLR + MTB Claim Clear + 0xFA4 + 32 + + + LOCKACCESS + MTB Lock Access + 0xFB0 + 32 + + + LOCKSTATUS + MTB Lock Status + 0xFB4 + 32 + read-only + + + AUTHSTATUS + MTB Authentication Status + 0xFB8 + 32 + read-only + + + DEVARCH + MTB Device Architecture + 0xFBC + 32 + read-only + + + DEVID + MTB Device Configuration + 0xFC8 + 32 + read-only + + + DEVTYPE + MTB Device Type + 0xFCC + 32 + read-only + + + PID4 + Peripheral Identification 4 + 0xFD0 + 32 + read-only + + + PID5 + Peripheral Identification 5 + 0xFD4 + 32 + read-only + + + PID6 + Peripheral Identification 6 + 0xFD8 + 32 + read-only + + + PID7 + Peripheral Identification 7 + 0xFDC + 32 + read-only + + + PID0 + Peripheral Identification 0 + 0xFE0 + 32 + read-only + + + PID1 + Peripheral Identification 1 + 0xFE4 + 32 + read-only + + + PID2 + Peripheral Identification 2 + 0xFE8 + 32 + read-only + + + PID3 + Peripheral Identification 3 + 0xFEC + 32 + read-only + + + CID0 + Component Identification 0 + 0xFF0 + 32 + read-only + + + CID1 + Component Identification 1 + 0xFF4 + 32 + read-only + + + CID2 + Component Identification 2 + 0xFF8 + 32 + read-only + + + CID3 + Component Identification 3 + 0xFFC + 32 + read-only + + + + + NVMCTRL + U22074.0.1.1 + Non-Volatile Memory Controller + NVMCTRL + NVMCTRL_ + 0x41004000 + + 0 + 0x30 + registers + + + NVMCTRL + 6 + + + + CTRLA + Control A + 0x0 + 16 + 0x0000 + + + CMD + Command + 0 + 7 + + CMDSelect + + ER + Erase Row - Erases the row addressed by the ADDR register. + 0x02 + + + WP + Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. + 0x04 + + + EAR + Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. + 0x05 + + + WAP + Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. + 0x06 + + + SF + Security Flow Command + 0x0A + + + WL + Write lockbits + 0x0F + + + RWWEEER + RWW EEPROM area Erase Row - Erases the row addressed by the ADDR register. + 0x1A + + + RWWEEWP + RWW EEPROM Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. + 0x1C + + + LR + Lock Region - Locks the region containing the address location in the ADDR register. + 0x40 + + + UR + Unlock Region - Unlocks the region containing the address location in the ADDR register. + 0x41 + + + SPRM + Sets the power reduction mode. + 0x42 + + + CPRM + Clears the power reduction mode. + 0x43 + + + PBC + Page Buffer Clear - Clears the page buffer. + 0x44 + + + SSB + Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row. + 0x45 + + + INVALL + Invalidate all cache lines. + 0x46 + + + + + CMDEX + Command Execution + 8 + 8 + + CMDEXSelect + + KEY + Execution Key + 0xA5 + + + + + + + CTRLB + Control B + 0x4 + 32 + 0x00000080 + + + RWS + NVM Read Wait States + 1 + 4 + + RWSSelect + + SINGLE + Single Auto Wait State + 0 + + + HALF + Half Auto Wait State + 1 + + + DUAL + Dual Auto Wait State + 2 + + + + + MANW + Manual Write + 7 + 1 + + + SLEEPPRM + Power Reduction Mode during Sleep + 8 + 2 + + SLEEPPRMSelect + + WAKEONACCESS + NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access. + 0 + + + WAKEUPINSTANT + NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep. + 1 + + + DISABLED + Auto power reduction disabled. + 3 + + + + + READMODE + NVMCTRL Read Mode + 16 + 2 + + READMODESelect + + NO_MISS_PENALTY + The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance. + 0x0 + + + LOW_POWER + Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time. + 0x1 + + + DETERMINISTIC + The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings. + 0x2 + + + + + CACHEDIS + Cache Disable + 18 + 2 + + + + + PARAM + NVM Parameter + 0x8 + 32 + 0x00000000 + + + NVMP + NVM Pages + 0 + 16 + + + PSZ + Page Size + 16 + 3 + + PSZSelect + + 8 + 8 bytes + 0x0 + + + 16 + 16 bytes + 0x1 + + + 32 + 32 bytes + 0x2 + + + 64 + 64 bytes + 0x3 + + + 128 + 128 bytes + 0x4 + + + 256 + 256 bytes + 0x5 + + + 512 + 512 bytes + 0x6 + + + 1024 + 1024 bytes + 0x7 + + + + + RWWEEP + RWW EEPROM Pages + 20 + 12 + + + + + INTENCLR + Interrupt Enable Clear + 0xC + 8 + 0x00 + + + READY + NVM Ready Interrupt Enable + 0 + 1 + + + ERROR + Error Interrupt Enable + 1 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x10 + 8 + 0x00 + + + READY + NVM Ready Interrupt Enable + 0 + 1 + + + ERROR + Error Interrupt Enable + 1 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x14 + 8 + 0x00 + + + READY + NVM Ready + 0 + 1 + + + ERROR + Error + 1 + 1 + + + + + STATUS + Status + 0x18 + 16 + 0x0000 + + + PRM + Power Reduction Mode + 0 + 1 + + + LOAD + NVM Page Buffer Active Loading + 1 + 1 + + + PROGE + Programming Error Status + 2 + 1 + + + LOCKE + Lock Error Status + 3 + 1 + + + NVME + NVM Error + 4 + 1 + + + SB + Security Bit Status + 8 + 1 + + + + + ADDR + Address + 0x1C + 32 + 0x00000000 + + + ADDR + NVM Address + 0 + 22 + + + + + LOCK + Lock Section + 0x20 + 16 + 0x0000 + + + LOCK + Region Lock Bits + 0 + 16 + + + + + PBLDATA0 + Page Buffer Load Data 0 + 0x28 + 32 + read-only + 0x00000000 + + + PBLDATA1 + Page Buffer Load Data 1 + 0x2C + 32 + read-only + 0x00000000 + + + + + OSCCTRL + U21192.1.0 + Oscillators Control + OSCCTRL + OSCCTRL_ + 0x40001000 + + 0 + 0x3C + registers + + + + INTENCLR + Interrupt Enable Clear + 0x0 + 32 + 0x00000000 + + + XOSCRDY + XOSC Ready Interrupt Enable + 0 + 1 + + + XOSCFAIL + XOSC Clock Failure Detector Interrupt Enable + 1 + 1 + + + OSC48MRDY + OSC48M Ready Interrupt Enable + 4 + 1 + + + DPLLLCKR + DPLL Lock Rise Interrupt Enable + 8 + 1 + + + DPLLLCKF + DPLL Lock Fall Interrupt Enable + 9 + 1 + + + DPLLLTO + DPLL Time Out Interrupt Enable + 10 + 1 + + + DPLLLDRTO + DPLL Ratio Ready Interrupt Enable + 11 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x4 + 32 + 0x00000000 + + + XOSCRDY + XOSC Ready Interrupt Enable + 0 + 1 + + + XOSCFAIL + XOSC Clock Failure Detector Interrupt Enable + 1 + 1 + + + OSC48MRDY + OSC48M Ready Interrupt Enable + 4 + 1 + + + DPLLLCKR + DPLL Lock Rise Interrupt Enable + 8 + 1 + + + DPLLLCKF + DPLL Lock Fall Interrupt Enable + 9 + 1 + + + DPLLLTO + DPLL Time Out Interrupt Enable + 10 + 1 + + + DPLLLDRTO + DPLL Ratio Ready Interrupt Enable + 11 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x8 + 32 + 0x00000000 + + + XOSCRDY + XOSC Ready + 0 + 1 + + + XOSCFAIL + XOSC Clock Failure Detector + 1 + 1 + + + OSC48MRDY + OSC48M Ready + 4 + 1 + + + DPLLLCKR + DPLL Lock Rise + 8 + 1 + + + DPLLLCKF + DPLL Lock Fall + 9 + 1 + + + DPLLLTO + DPLL Timeout + 10 + 1 + + + DPLLLDRTO + DPLL Ratio Ready + 11 + 1 + + + + + STATUS + Power and Clocks Status + 0xC + 32 + read-only + 0x00000000 + + + XOSCRDY + XOSC Ready + 0 + 1 + + + XOSCFAIL + XOSC Clock Failure Detector + 1 + 1 + + + XOSCCKSW + XOSC Clock Switch + 2 + 1 + + + OSC48MRDY + OSC48M Ready + 4 + 1 + + + DPLLLCKR + DPLL Lock Rise + 8 + 1 + + + DPLLLCKF + DPLL Lock Fall + 9 + 1 + + + DPLLTO + DPLL Timeout + 10 + 1 + + + DPLLLDRTO + DPLL Ratio Ready + 11 + 1 + + + + + XOSCCTRL + External Multipurpose Crystal Oscillator (XOSC) Control + 0x10 + 16 + 0x0080 + + + ENABLE + Oscillator Enable + 1 + 1 + + + XTALEN + Crystal Oscillator Enable + 2 + 1 + + + CFDEN + Xosc Clock Failure Detector Enable + 3 + 1 + + + SWBEN + Xosc Clock Switch Enable + 4 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + GAIN + Oscillator Gain + 8 + 3 + + GAINSelect + + GAIN2 + 2 MHz + 0 + + + GAIN4 + 4 MHz + 1 + + + GAIN8 + 8 MHz + 2 + + + GAIN16 + 16 MHz + 3 + + + GAIN30 + 30 MHz + 4 + + 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1.333 us + 3 + + + CYCLE128 + 2.667 us + 4 + + + CYCLE256 + 5.333 us + 5 + + + CYCLE512 + 10.667 us + 6 + + + CYCLE1024 + 21.333 us + 7 + + + + + + + OSC48MSYNCBUSY + OSC48M Synchronization Busy + 0x18 + 32 + read-only + 0x00000000 + + + OSC48MDIV + OSC48MDIV Synchronization Status + 2 + 1 + + + + + DPLLCTRLA + DPLL Control + 0x1C + 8 + 0x80 + + + ENABLE + Enable + 1 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand + 7 + 1 + + + + + DPLLRATIO + DPLL Ratio Control + 0x20 + 32 + 0x00000000 + + + LDR + Loop Divider Ratio + 0 + 12 + + + LDRFRAC + Loop Divider Ratio Fractional Part + 16 + 4 + + + + + DPLLCTRLB + Digital Core Configuration + 0x24 + 32 + 0x00000000 + + + FILTER + Proportional Integral Filter Selection + 0 + 2 + + FILTERSelect + + DEFAULT + Default filter mode + 0 + + + LBFILT + Low bandwidth filter + 1 + + + HBFILT + High bandwidth filter + 2 + + + HDFILT + High damping filter + 3 + + + + + LPEN + Low-Power Enable + 2 + 1 + + + WUF + Wake Up Fast + 3 + 1 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Automatic lock. + 0 + + + 8MS + Time-out if no lock within 8ms + 4 + + + 9MS + Time-out if no lock within 9ms + 5 + + + 10MS + Time-out if no lock within 10ms + 6 + + + 11MS + Time-out if no lock within 11ms + 7 + + + + + LBYPASS + Lock Bypass + 12 + 1 + + + DIV + Clock Divider + 16 + 11 + + + + + DPLLPRESC + DPLL Prescaler + 0x28 + 8 + 0x00 + + + PRESC + Output Clock Prescaler + 0 + 2 + + PRESCSelect + + DIV1 + DPLL output is divided by 1 + 0 + + + DIV2 + DPLL output is divided by 2 + 1 + + + DIV4 + DPLL output is divided by 4 + 2 + + + + + + + DPLLSYNCBUSY + DPLL Synchronization Busy + 0x2C + 8 + read-only + 0x00 + + + ENABLE + DPLL Enable Synchronization Status + 1 + 1 + + + DPLLRATIO + DPLL Ratio Synchronization Status + 2 + 1 + + + DPLLPRESC + DPLL Prescaler Synchronization Status + 3 + 1 + + + + + DPLLSTATUS + DPLL Status + 0x30 + 8 + read-only + 0x00 + + + LOCK + DPLL Lock Status + 0 + 1 + + + CLKRDY + DPLL Clock Ready + 1 + 1 + + + + + CAL48M + 48MHz Oscillator Calibration + 0x38 + 32 + 0x00000000 + + + FCAL + Frequency Calibration (48MHz) + 0 + 6 + + + FRANGE + Frequency Range (48MHz) + 8 + 2 + + + TCAL + Temperature Calibration (48MHz) + 16 + 6 + + + + + + + OSC32KCTRL + U22462.1.0 + 32k Oscillators Control + OSC32KCTRL + OSC32KCTRL_ + 0x40001400 + + 0 + 0x20 + registers + + + + INTENCLR + Interrupt Enable Clear + 0x0 + 32 + 0x00000000 + + + XOSC32KRDY + XOSC32K Ready Interrupt Enable + 0 + 1 + + + OSC32KRDY + OSC32K Ready Interrupt Enable + 1 + 1 + + + CLKFAIL + XOSC32K Clock Failure Detector Interrupt Enable + 2 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x4 + 32 + 0x00000000 + + + XOSC32KRDY + XOSC32K Ready Interrupt Enable + 0 + 1 + + + OSC32KRDY + OSC32K Ready Interrupt Enable + 1 + 1 + + + CLKFAIL + XOSC32K Clock Failure Detector Interrupt Enable + 2 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x8 + 32 + 0x00000000 + + + XOSC32KRDY + XOSC32K Ready + 0 + 1 + + + OSC32KRDY + OSC32K Ready + 1 + 1 + + + CLKFAIL + XOSC32K Clock Failure Detector + 2 + 1 + + + + + STATUS + Power and Clocks Status + 0xC + 32 + read-only + 0x00000000 + + + XOSC32KRDY + XOSC32K Ready + 0 + 1 + + + OSC32KRDY + OSC32K Ready + 1 + 1 + + + CLKFAIL + XOSC32K Clock Failure Detector + 2 + 1 + + + CLKSW + XOSC32K Clock switch + 3 + 1 + + + + + RTCCTRL + Clock selection + 0x10 + 32 + 0x00000000 + + + RTCSEL + RTC Clock Selection + 0 + 3 + + RTCSELSelect + + ULP1K + 1.024kHz from 32kHz internal ULP oscillator + 0 + + + ULP32K + 32.768kHz from 32kHz internal ULP oscillator + 1 + + + OSC1K + 1.024kHz from 32.768kHz internal oscillator + 2 + + + OSC32K + 32.768kHz from 32.768kHz internal oscillator + 3 + + + XOSC1K + 1.024kHz from 32.768kHz internal oscillator + 4 + + + XOSC32K + 32.768kHz from 32.768kHz external crystal oscillator + 5 + + + + + + + XOSC32K + 32kHz External Crystal Oscillator (XOSC32K) Control + 0x14 + 16 + 0x0080 + + + ENABLE + Oscillator Enable + 1 + 1 + + + XTALEN + Crystal Oscillator Enable + 2 + 1 + + + EN32K + 32kHz Output Enable + 3 + 1 + + + EN1K + 1kHz Output Enable + 4 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + STARTUP + Oscillator Start-Up Time + 8 + 3 + + STARTUPSelect + + CYCLE1 + 0.122 ms + 0 + + + CYCLE32 + 1.068 ms + 1 + + + CYCLE2048 + 62.6 ms + 2 + + + CYCLE4096 + 125 ms + 3 + + + CYCLE16384 + 500 ms + 4 + + + CYCLE32768 + 1000 ms + 5 + + + CYCLE65536 + 2000 ms + 6 + + + CYCLE131072 + 4000 ms + 7 + + + + + WRTLOCK + Write Lock + 12 + 1 + + + + + CFDCTRL + Clock Failure Detector Control + 0x16 + 8 + 0x00 + + + CFDEN + Clock Failure Detector Enable + 0 + 1 + + + SWBACK + Clock Switch Back + 1 + 1 + + + CFDPRESC + Clock Failure Detector Prescaler + 2 + 1 + + + + + EVCTRL + Event Control + 0x17 + 8 + 0x00 + + + CFDEO + Clock Failure Detector Event Output Enable + 0 + 1 + + + + + OSC32K + 32kHz Internal Oscillator (OSC32K) Control + 0x18 + 32 + 0x003F0080 + + + ENABLE + Oscillator Enable + 1 + 1 + + + EN32K + 32kHz Output Enable + 2 + 1 + + + EN1K + 1kHz Output Enable + 3 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + STARTUP + Oscillator Start-Up Time + 8 + 3 + + STARTUPSelect + + CYCLE3 + 0.092 ms + 0 + + + CYCLE4 + 0.122 ms + 1 + + + CYCLE6 + 0.183 ms + 2 + + + CYCLE10 + 0.305 ms + 3 + + + CYCLE18 + 0.549 ms + 4 + + + CYCLE34 + 1.038 ms + 5 + + + CYCLE66 + 2.014 ms + 6 + + + CYCLE130 + 3.967 ms + 7 + + + + + WRTLOCK + Write Lock + 12 + 1 + + + CALIB + Oscillator Calibration + 16 + 7 + + + + + OSCULP32K + 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control + 0x1C + 32 + + + CALIB + Oscillator Calibration + 8 + 5 + + + WRTLOCK + Write Lock + 15 + 1 + + + + + + + PAC + U21201.1.0 + Peripheral Access Controller + PAC + PAC_ + 0x40000000 + + 0 + 0x40 + registers + + + + WRCTRL + Write control + 0x0 + 32 + 0x00000000 + + + PERID + Peripheral identifier + 0 + 16 + + + KEY + Peripheral access control key + 16 + 8 + + KEYSelect + + OFF + No action + 0 + + + CLR + Clear protection + 1 + + + SET + Set protection + 2 + + + SETLCK + Set and lock protection + 3 + + + + + + + EVCTRL + Event control + 0x4 + 8 + 0x00 + + + ERREO + Peripheral acess error event output + 0 + 1 + + + + + INTENCLR + Interrupt enable clear + 0x8 + 8 + 0x00 + + + ERR + Peripheral access error interrupt disable + 0 + 1 + + + + + INTENSET + Interrupt enable set + 0x9 + 8 + 0x00 + + + ERR + Peripheral access error interrupt enable + 0 + 1 + + + + + INTFLAGAHB + Bridge interrupt flag status + 0x10 + 32 + 0x00000000 + + + FLASH_ + FLASH + 0 + 1 + + + HSRAMCM0P_ + HSRAMCM0P + 1 + 1 + + + HSRAMDSU_ + HSRAMDSU + 2 + 1 + + + HPB1_ + HPB1 + 3 + 1 + + + HPB0_ + HPB0 + 4 + 1 + + + HPB2_ + HPB2 + 5 + 1 + + + LPRAMDMAC_ + LPRAMDMAC + 6 + 1 + + + DIVAS_ + DIVAS + 7 + 1 + + + + + INTFLAGA + Peripheral interrupt flag status - Bridge A + 0x14 + 32 + 0x00000000 + + + PAC_ + PAC + 0 + 1 + + + PM_ + PM + 1 + 1 + + + MCLK_ + MCLK + 2 + 1 + + + RSTC_ + RSTC + 3 + 1 + + + OSCCTRL_ + OSCCTRL + 4 + 1 + + + OSC32KCTRL_ + OSC32KCTRL + 5 + 1 + + + SUPC_ + SUPC + 6 + 1 + + + GCLK_ + GCLK + 7 + 1 + + + WDT_ + WDT + 8 + 1 + + + RTC_ + RTC + 9 + 1 + + + EIC_ + EIC + 10 + 1 + + + FREQM_ + FREQM + 11 + 1 + + + + + INTFLAGB + Peripheral interrupt flag status - Bridge B + 0x18 + 32 + 0x00000000 + + + PORT_ + PORT + 0 + 1 + + + DSU_ + DSU + 1 + 1 + + + NVMCTRL_ + NVMCTRL + 2 + 1 + + + DMAC_ + DMAC + 3 + 1 + + + MTB_ + MTB + 4 + 1 + + + HMATRIXHS_ + HMATRIXHS + 5 + 1 + + + + + INTFLAGC + Peripheral interrupt flag status - Bridge C + 0x1C + 32 + 0x00000000 + + + EVSYS_ + EVSYS + 0 + 1 + + + SERCOM0_ + SERCOM0 + 1 + 1 + + + SERCOM1_ + SERCOM1 + 2 + 1 + + + SERCOM2_ + SERCOM2 + 3 + 1 + + + SERCOM3_ + SERCOM3 + 4 + 1 + + + TCC0_ + TCC0 + 9 + 1 + + + TCC1_ + TCC1 + 10 + 1 + + + TCC2_ + TCC2 + 11 + 1 + + + TC0_ + TC0 + 12 + 1 + + + TC1_ + TC1 + 13 + 1 + + + TC2_ + TC2 + 14 + 1 + + + TC3_ + TC3 + 15 + 1 + + + TC4_ + TC4 + 16 + 1 + + + ADC0_ + ADC0 + 17 + 1 + + + AC_ + AC + 20 + 1 + + + PTC_ + PTC + 22 + 1 + + + CCL_ + CCL + 23 + 1 + + + + + STATUSA + Peripheral write protection status - Bridge A + 0x34 + 32 + read-only + 0x00000000 + + + PAC_ + PAC APB Protect Enable + 0 + 1 + + + PM_ + PM APB Protect Enable + 1 + 1 + + + MCLK_ + MCLK APB Protect Enable + 2 + 1 + + + RSTC_ + RSTC APB Protect Enable + 3 + 1 + + + OSCCTRL_ + OSCCTRL APB Protect Enable + 4 + 1 + + + OSC32KCTRL_ + OSC32KCTRL APB Protect Enable + 5 + 1 + + + SUPC_ + SUPC APB Protect Enable + 6 + 1 + + + GCLK_ + GCLK APB Protect Enable + 7 + 1 + + + WDT_ + WDT APB Protect Enable + 8 + 1 + + + RTC_ + RTC APB Protect Enable + 9 + 1 + + + EIC_ + EIC APB Protect Enable + 10 + 1 + + + FREQM_ + FREQM APB Protect Enable + 11 + 1 + + + + + STATUSB + Peripheral write protection status - Bridge B + 0x38 + 32 + read-only + 0x00000002 + + + PORT_ + PORT APB Protect Enable + 0 + 1 + + + DSU_ + DSU APB Protect Enable + 1 + 1 + + + NVMCTRL_ + NVMCTRL APB Protect Enable + 2 + 1 + + + DMAC_ + DMAC APB Protect Enable + 3 + 1 + + + MTB_ + MTB APB Protect Enable + 4 + 1 + + + HMATRIXHS_ + HMATRIXHS APB Protect Enable + 5 + 1 + + + + + STATUSC + Peripheral write protection status - Bridge C + 0x3C + 32 + read-only + 0x02000000 + + + EVSYS_ + EVSYS APB Protect Enable + 0 + 1 + + + SERCOM0_ + SERCOM0 APB Protect Enable + 1 + 1 + + + SERCOM1_ + SERCOM1 APB Protect Enable + 2 + 1 + + + SERCOM2_ + SERCOM2 APB Protect Enable + 3 + 1 + + + SERCOM3_ + SERCOM3 APB Protect Enable + 4 + 1 + + + TCC0_ + TCC0 APB Protect Enable + 9 + 1 + + + TCC1_ + TCC1 APB Protect Enable + 10 + 1 + + + TCC2_ + TCC2 APB Protect Enable + 11 + 1 + + + TC0_ + TC0 APB Protect Enable + 12 + 1 + + + TC1_ + TC1 APB Protect Enable + 13 + 1 + + + TC2_ + TC2 APB Protect Enable + 14 + 1 + + + TC3_ + TC3 APB Protect Enable + 15 + 1 + + + TC4_ + TC4 APB Protect Enable + 16 + 1 + + + ADC0_ + ADC0 APB Protect Enable + 17 + 1 + + + AC_ + AC APB Protect Enable + 20 + 1 + + + PTC_ + PTC APB Protect Enable + 22 + 1 + + + CCL_ + CCL APB Protect Enable + 23 + 1 + + + + + + + PM + U22402.1.0 + Power Manager + PM + PM_ + 0x40000400 + + 0 + 0xA + registers + + + + SLEEPCFG + Sleep Configuration + 0x1 + 8 + 0x00 + + + SLEEPMODE + Sleep Mode + 0 + 3 + + SLEEPMODESelect + + IDLE0 + CPU clock is OFF + 0 + + + IDLE1 + AHB clock is OFF + 1 + + + IDLE2 + APB clock are OFF + 2 + + + STANDBY + All Clocks are OFF + 4 + + + + + + + STDBYCFG + Standby Configuration + 0x8 + 16 + 0x0400 + + + VREGSMOD + Voltage Regulator Standby mode + 6 + 2 + + VREGSMODSelect + + AUTO + Automatic mode + 0 + + + PERFORMANCE + Performance oriented + 1 + + + LP + Low Power oriented + 2 + + + + + BBIASHS + Back Bias for HMCRAMCHS + 10 + 1 + + + + + + + PORT + U22102.1.1 + Port Module + PORT + PORT_ + 0x41000000 + + 0 + 0x100 + registers + + + + 2 + 0x80 + GROUP[%s] + + 0x00 + + DIR + Data Direction + 0x0 + 32 + 0x00000000 + + + DIRCLR + Data Direction Clear + 0x4 + 32 + 0x00000000 + + + DIRSET + Data Direction Set + 0x8 + 32 + 0x00000000 + + + DIRTGL + Data Direction Toggle + 0xC + 32 + 0x00000000 + + + OUT + Data Output Value + 0x10 + 32 + 0x00000000 + + + OUTCLR + Data Output Value Clear + 0x14 + 32 + 0x00000000 + + + OUTSET + Data Output Value Set + 0x18 + 32 + 0x00000000 + + + OUTTGL + Data Output Value Toggle + 0x1C + 32 + 0x00000000 + + + IN + Data Input Value + 0x20 + 32 + read-only + 0x00000000 + + + CTRL + Control + 0x24 + 32 + 0x00000000 + + + SAMPLING + Input Sampling Mode + 0 + 32 + + + + + WRCONFIG + Write Configuration + 0x28 + 32 + write-only + 0x00000000 + + + PINMASK + Pin Mask for Multiple Pin Configuration + 0 + 16 + + + PMUXEN + Select Peripheral Multiplexer + 16 + 1 + + + INEN + Input Enable + 17 + 1 + + + PULLEN + Pull Enable + 18 + 1 + + + DRVSTR + Output Driver Strength Selection + 22 + 1 + + + PMUX + Peripheral Multiplexing Template + 24 + 4 + + + WRPMUX + Write PMUX Registers + 28 + 1 + + + WRPINCFG + Write PINCFG Registers + 30 + 1 + + + HWSEL + Half-Word Select + 31 + 1 + + + + + EVCTRL + Event Input Control + 0x2C + 32 + 0x00000000 + + + PID0 + Port Event Pin Identifier 0 + 0 + 5 + + + EVACT0 + Port Event Action 0 + 5 + 2 + + EVACT0Select + + OUT + Event output to pin + 0x0 + + + SET + Set output register of pin on event + 0x1 + + + CLR + Clear output register of pin on event + 0x2 + + + TGL + Toggle output register of pin on event + 0x3 + + + + + PORTEI0 + Port Event Enable Input 0 + 7 + 1 + + + PID1 + Port Event Pin Identifier 1 + 8 + 5 + + + EVACT1 + Port Event Action 1 + 13 + 2 + + + PORTEI1 + Port Event Enable Input 1 + 15 + 1 + + + PID2 + Port Event Pin Identifier 2 + 16 + 5 + + + EVACT2 + Port Event Action 2 + 21 + 2 + + + PORTEI2 + Port Event Enable Input 2 + 23 + 1 + + + PID3 + Port Event Pin Identifier 3 + 24 + 5 + + + EVACT3 + Port Event Action 3 + 29 + 2 + + + PORTEI3 + Port Event Enable Input 3 + 31 + 1 + + + + + 16 + 1 + PMUX[%s] + Peripheral Multiplexing n + 0x30 + 8 + 0x00 + + + PMUXE + Peripheral Multiplexing for Even-Numbered Pin + 0 + 4 + + + PMUXO + Peripheral Multiplexing for Odd-Numbered Pin + 4 + 4 + + + + + 32 + 1 + PINCFG[%s] + Pin Configuration n + 0x40 + 8 + 0x00 + + + PMUXEN + Select Peripheral Multiplexer + 0 + 1 + + + INEN + Input Enable + 1 + 1 + + + PULLEN + Pull Enable + 2 + 1 + + + DRVSTR + Output Driver Strength Selection + 6 + 1 + + + + + + + + PORT_IOBUS + PORT_IOBUS_ + 0x60000000 + + + PTC + U22153.1.0 + Peripheral Touch Controller + PTC + PTC_ + 0x42005800 + + 0 + 0x1 + reserved + + + PTC + 30 + + + + RSTC + U22392.0.2 + Reset Controller + RSTC + RSTC_ + 0x40000C00 + + 0 + 0x1 + registers + + + + RCAUSE + Reset Cause + 0x0 + 8 + read-only + + + POR + Power On Reset + 0 + 1 + + + BODCORE + Brown Out CORE Detector Reset + 1 + 1 + + + BODVDD + Brown Out VDD Detector Reset + 2 + 1 + + + EXT + External Reset + 4 + 1 + + + WDT + Watchdog Reset + 5 + 1 + + + SYST + System Reset Request + 6 + 1 + + + + + + + RTC + U22501.1.1 + Real-Time Counter + RTC + RTC_ + 0x40002400 + + 0 + 0x25 + registers + + + RTC + 2 + + + + MODE0 + 32-bit Counter with Single 32-bit Compare + RtcMode0 + 0x0 + + CTRLA + MODE0 Control A + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 2 + + MODESelect + + COUNT32 + Mode 0: 32-bit Counter + 0x0 + + + COUNT16 + Mode 1: 16-bit Counter + 0x1 + + + CLOCK + Mode 2: Clock/Calendar + 0x2 + + + + + MATCHCLR + Clear on Match + 7 + 1 + + + PRESCALER + Prescaler + 8 + 4 + + PRESCALERSelect + + OFF + CLK_RTC_CNT = GCLK_RTC/1 + 0x0 + + + DIV1 + CLK_RTC_CNT = GCLK_RTC/1 + 0x1 + + + DIV2 + CLK_RTC_CNT = GCLK_RTC/2 + 0x2 + + + DIV4 + CLK_RTC_CNT = GCLK_RTC/4 + 0x3 + + + DIV8 + CLK_RTC_CNT = GCLK_RTC/8 + 0x4 + + + DIV16 + CLK_RTC_CNT = GCLK_RTC/16 + 0x5 + + + DIV32 + CLK_RTC_CNT = GCLK_RTC/32 + 0x6 + + + DIV64 + CLK_RTC_CNT = GCLK_RTC/64 + 0x7 + + + DIV128 + CLK_RTC_CNT = GCLK_RTC/128 + 0x8 + + + DIV256 + CLK_RTC_CNT = GCLK_RTC/256 + 0x9 + + + DIV512 + CLK_RTC_CNT = GCLK_RTC/512 + 0xA + + + DIV1024 + CLK_RTC_CNT = GCLK_RTC/1024 + 0xB + + + + + COUNTSYNC + Count Read Synchronization Enable + 15 + 1 + + + + + EVCTRL + MODE0 Event Control + 0x4 + 32 + 0x00000000 + + + PEREO0 + Periodic Interval 0 Event Output Enable + 0 + 1 + + + PEREO1 + Periodic Interval 1 Event Output Enable + 1 + 1 + + + PEREO2 + Periodic Interval 2 Event Output Enable + 2 + 1 + + + PEREO3 + Periodic Interval 3 Event Output Enable + 3 + 1 + + + PEREO4 + Periodic Interval 4 Event Output Enable + 4 + 1 + + + PEREO5 + Periodic Interval 5 Event Output Enable + 5 + 1 + + + PEREO6 + Periodic Interval 6 Event Output Enable + 6 + 1 + + + PEREO7 + Periodic Interval 7 Event Output Enable + 7 + 1 + + + CMPEO0 + Compare 0 Event Output Enable + 8 + 1 + + + OVFEO + Overflow Event Output Enable + 15 + 1 + + + + + INTENCLR + MODE0 Interrupt Enable Clear + 0x8 + 16 + 0x0000 + + + PER0 + Periodic Interval 0 Interrupt Enable + 0 + 1 + + + PER1 + Periodic Interval 1 Interrupt Enable + 1 + 1 + + + PER2 + Periodic Interval 2 Interrupt Enable + 2 + 1 + + + PER3 + Periodic Interval 3 Interrupt Enable + 3 + 1 + + + PER4 + Periodic Interval 4 Interrupt Enable + 4 + 1 + + + PER5 + Periodic Interval 5 Interrupt Enable + 5 + 1 + + + PER6 + Periodic Interval 6 Interrupt Enable + 6 + 1 + + + PER7 + Periodic Interval 7 Interrupt Enable + 7 + 1 + + + CMP0 + Compare 0 Interrupt Enable + 8 + 1 + + + OVF + Overflow Interrupt Enable + 15 + 1 + + + + + INTENSET + MODE0 Interrupt Enable Set + 0xA + 16 + 0x0000 + + + PER0 + Periodic Interval 0 Interrupt Enable + 0 + 1 + + + PER1 + Periodic Interval 1 Interrupt Enable + 1 + 1 + + + PER2 + Periodic Interval 2 Interrupt Enable + 2 + 1 + + + PER3 + Periodic Interval 3 Interrupt Enable + 3 + 1 + + + PER4 + Periodic Interval 4 Interrupt Enable + 4 + 1 + + + PER5 + Periodic Interval 5 Interrupt Enable + 5 + 1 + + + PER6 + Periodic Interval 6 Interrupt Enable + 6 + 1 + + + PER7 + Periodic Interval 7 Interrupt Enable + 7 + 1 + + + CMP0 + Compare 0 Interrupt Enable + 8 + 1 + + + OVF + Overflow Interrupt Enable + 15 + 1 + + + + + INTFLAG + MODE0 Interrupt Flag Status and Clear + 0xC + 16 + 0x0000 + + + PER0 + Periodic Interval 0 + 0 + 1 + + + PER1 + Periodic Interval 1 + 1 + 1 + + + PER2 + Periodic Interval 2 + 2 + 1 + + + PER3 + Periodic Interval 3 + 3 + 1 + + + PER4 + Periodic Interval 4 + 4 + 1 + + + PER5 + Periodic Interval 5 + 5 + 1 + + + PER6 + Periodic Interval 6 + 6 + 1 + + + PER7 + Periodic Interval 7 + 7 + 1 + + + CMP0 + Compare 0 + 8 + 1 + + + OVF + Overflow + 15 + 1 + + + + + DBGCTRL + Debug Control + 0xE + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + SYNCBUSY + MODE0 Synchronization Busy Status + 0x10 + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Busy + 0 + 1 + + + ENABLE + Enable Bit Busy + 1 + 1 + + + FREQCORR + FREQCORR Register Busy + 2 + 1 + + + COUNT + COUNT Register Busy + 3 + 1 + + + COMP0 + COMP 0 Register Busy + 5 + 1 + + + COUNTSYNC + Count Read Synchronization Enable Bit Busy + 15 + 1 + + + + + FREQCORR + Frequency Correction + 0x14 + 8 + 0x00 + + + VALUE + Correction Value + 0 + 7 + + + SIGN + Correction Sign + 7 + 1 + + + + + COUNT + MODE0 Counter Value + 0x18 + 32 + 0x00000000 + + + COUNT + Counter Value + 0 + 32 + + + + + COMP + MODE0 Compare n Value + 0x20 + 32 + 0x00000000 + + + COMP + Compare Value + 0 + 32 + + + + + + MODE1 + 16-bit Counter with Two 16-bit Compares + MODE0 + RtcMode1 + 0x0 + + CTRLA + MODE1 Control A + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 2 + + MODESelect + + COUNT32 + Mode 0: 32-bit Counter + 0 + + + COUNT16 + Mode 1: 16-bit Counter + 1 + + + CLOCK + Mode 2: Clock/Calendar + 2 + + + + + PRESCALER + Prescaler + 8 + 4 + + PRESCALERSelect + + OFF + CLK_RTC_CNT = GCLK_RTC/1 + 0 + + + DIV1 + CLK_RTC_CNT = GCLK_RTC/1 + 1 + + + DIV2 + CLK_RTC_CNT = GCLK_RTC/2 + 2 + + + DIV4 + CLK_RTC_CNT = GCLK_RTC/4 + 3 + + + DIV8 + CLK_RTC_CNT = GCLK_RTC/8 + 4 + + + DIV16 + CLK_RTC_CNT = GCLK_RTC/16 + 5 + + + DIV32 + CLK_RTC_CNT = GCLK_RTC/32 + 6 + + + DIV64 + CLK_RTC_CNT = GCLK_RTC/64 + 7 + + + DIV128 + CLK_RTC_CNT = GCLK_RTC/128 + 8 + + + DIV256 + CLK_RTC_CNT = GCLK_RTC/256 + 9 + + + DIV512 + CLK_RTC_CNT = GCLK_RTC/512 + 0xA + + + DIV1024 + CLK_RTC_CNT = GCLK_RTC/1024 + 0xB + + + + + COUNTSYNC + Count Read Synchronization Enable + 15 + 1 + + + + + EVCTRL + MODE1 Event Control + 0x4 + 32 + 0x00000000 + + + PEREO0 + Periodic Interval 0 Event Output Enable + 0 + 1 + + + PEREO1 + Periodic Interval 1 Event Output Enable + 1 + 1 + + + PEREO2 + Periodic Interval 2 Event Output Enable + 2 + 1 + + + PEREO3 + Periodic Interval 3 Event Output Enable + 3 + 1 + + + PEREO4 + Periodic Interval 4 Event Output Enable + 4 + 1 + + + PEREO5 + Periodic Interval 5 Event Output Enable + 5 + 1 + + + PEREO6 + Periodic Interval 6 Event Output Enable + 6 + 1 + + + PEREO7 + Periodic Interval 7 Event Output Enable + 7 + 1 + + + CMPEO0 + Compare 0 Event Output Enable + 8 + 1 + + + CMPEO1 + Compare 1 Event Output Enable + 9 + 1 + + + OVFEO + Overflow Event Output Enable + 15 + 1 + + + + + INTENCLR + MODE1 Interrupt Enable Clear + 0x8 + 16 + 0x0000 + + + PER0 + Periodic Interval 0 Interrupt Enable + 0 + 1 + + + PER1 + Periodic Interval 1 Interrupt Enable + 1 + 1 + + + PER2 + Periodic Interval 2 Interrupt Enable + 2 + 1 + + + PER3 + Periodic Interval 3 Interrupt Enable + 3 + 1 + + + PER4 + Periodic Interval 4 Interrupt Enable + 4 + 1 + + + PER5 + Periodic Interval 5 Interrupt Enable + 5 + 1 + + + PER6 + Periodic Interval 6 Interrupt Enable + 6 + 1 + + + PER7 + Periodic Interval 7 Interrupt Enable + 7 + 1 + + + CMP0 + Compare 0 Interrupt Enable + 8 + 1 + + + CMP1 + Compare 1 Interrupt Enable + 9 + 1 + + + OVF + Overflow Interrupt Enable + 15 + 1 + + + + + INTENSET + MODE1 Interrupt Enable Set + 0xA + 16 + 0x0000 + + + PER0 + Periodic Interval 0 Interrupt Enable + 0 + 1 + + + PER1 + Periodic Interval 1 Interrupt Enable + 1 + 1 + + + PER2 + Periodic Interval 2 Interrupt Enable + 2 + 1 + + + PER3 + Periodic Interval 3 Interrupt Enable + 3 + 1 + + + PER4 + Periodic Interval 4 Interrupt Enable + 4 + 1 + + + PER5 + Periodic Interval 5 Interrupt Enable + 5 + 1 + + + PER6 + Periodic Interval 6 Interrupt Enable + 6 + 1 + + + PER7 + Periodic Interval 7 Interrupt Enable + 7 + 1 + + + CMP0 + Compare 0 Interrupt Enable + 8 + 1 + + + CMP1 + Compare 1 Interrupt Enable + 9 + 1 + + + OVF + Overflow Interrupt Enable + 15 + 1 + + + + + INTFLAG + MODE1 Interrupt Flag Status and Clear + 0xC + 16 + 0x0000 + + + PER0 + Periodic Interval 0 + 0 + 1 + + + PER1 + Periodic Interval 1 + 1 + 1 + + + PER2 + Periodic Interval 2 + 2 + 1 + + + PER3 + Periodic Interval 3 + 3 + 1 + + + PER4 + Periodic Interval 4 + 4 + 1 + + + PER5 + Periodic Interval 5 + 5 + 1 + + + PER6 + Periodic Interval 6 + 6 + 1 + + + PER7 + Periodic Interval 7 + 7 + 1 + + + CMP0 + Compare 0 + 8 + 1 + + + CMP1 + Compare 1 + 9 + 1 + + + OVF + Overflow + 15 + 1 + + + + + DBGCTRL + Debug Control + 0xE + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + SYNCBUSY + MODE1 Synchronization Busy Status + 0x10 + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Bit Busy + 0 + 1 + + + ENABLE + Enable Bit Busy + 1 + 1 + + + FREQCORR + FREQCORR Register Busy + 2 + 1 + + + COUNT + COUNT Register Busy + 3 + 1 + + + PER + PER Register Busy + 4 + 1 + + + COMP0 + COMP 0 Register Busy + 5 + 1 + + + COMP1 + COMP 1 Register Busy + 6 + 1 + + + COUNTSYNC + Count Read Synchronization Enable Bit Busy + 15 + 1 + + + + + FREQCORR + Frequency Correction + 0x14 + 8 + 0x00 + + + VALUE + Correction Value + 0 + 7 + + + SIGN + Correction Sign + 7 + 1 + + + + + COUNT + MODE1 Counter Value + 0x18 + 16 + 0x0000 + + + COUNT + Counter Value + 0 + 16 + + + + + PER + MODE1 Counter Period + 0x1C + 16 + 0x0000 + + + PER + Counter Period + 0 + 16 + + + + + 2 + 2 + COMP[%s] + MODE1 Compare n Value + 0x20 + 16 + 0x0000 + + + COMP + Compare Value + 0 + 16 + + + + + + MODE2 + Clock/Calendar with Alarm + MODE0 + RtcMode2 + 0x0 + + CTRLA + MODE2 Control A + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 2 + + MODESelect + + COUNT32 + Mode 0: 32-bit Counter + 0 + + + COUNT16 + Mode 1: 16-bit Counter + 1 + + + CLOCK + Mode 2: Clock/Calendar + 2 + + + + + CLKREP + Clock Representation + 6 + 1 + + + MATCHCLR + Clear on Match + 7 + 1 + + + PRESCALER + Prescaler + 8 + 4 + + PRESCALERSelect + + OFF + CLK_RTC_CNT = GCLK_RTC/1 + 0x0 + + + DIV1 + CLK_RTC_CNT = GCLK_RTC/1 + 0x1 + + + DIV2 + CLK_RTC_CNT = GCLK_RTC/2 + 0x2 + + + DIV4 + CLK_RTC_CNT = GCLK_RTC/4 + 0x3 + + + DIV8 + CLK_RTC_CNT = GCLK_RTC/8 + 0x4 + + + DIV16 + CLK_RTC_CNT = GCLK_RTC/16 + 0x5 + + + DIV32 + CLK_RTC_CNT = GCLK_RTC/32 + 0x6 + + + DIV64 + CLK_RTC_CNT = GCLK_RTC/64 + 0x7 + + + DIV128 + CLK_RTC_CNT = GCLK_RTC/128 + 0x8 + + + DIV256 + CLK_RTC_CNT = GCLK_RTC/256 + 0x9 + + + DIV512 + CLK_RTC_CNT = GCLK_RTC/512 + 0xA + + + DIV1024 + CLK_RTC_CNT = GCLK_RTC/1024 + 0xB + + + + + CLOCKSYNC + Clock Read Synchronization Enable + 15 + 1 + + + + + EVCTRL + MODE2 Event Control + 0x4 + 32 + 0x00000000 + + + PEREO0 + Periodic Interval 0 Event Output Enable + 0 + 1 + + + PEREO1 + Periodic Interval 1 Event Output Enable + 1 + 1 + + + PEREO2 + Periodic Interval 2 Event Output Enable + 2 + 1 + + + PEREO3 + Periodic Interval 3 Event Output Enable + 3 + 1 + + + PEREO4 + Periodic Interval 4 Event Output Enable + 4 + 1 + + + PEREO5 + Periodic Interval 5 Event Output Enable + 5 + 1 + + + PEREO6 + Periodic Interval 6 Event Output Enable + 6 + 1 + + + PEREO7 + Periodic Interval 7 Event Output Enable + 7 + 1 + + + ALARMEO0 + Alarm 0 Event Output Enable + 8 + 1 + + + OVFEO + Overflow Event Output Enable + 15 + 1 + + + + + INTENCLR + MODE2 Interrupt Enable Clear + 0x8 + 16 + 0x0000 + + + PER0 + Periodic Interval 0 Interrupt Enable + 0 + 1 + + + PER1 + Periodic Interval 1 Interrupt Enable + 1 + 1 + + + PER2 + Periodic Interval 2 Interrupt Enable + 2 + 1 + + + PER3 + Periodic Interval 3 Interrupt Enable + 3 + 1 + + + PER4 + Periodic Interval 4 Interrupt Enable + 4 + 1 + + + PER5 + Periodic Interval 5 Interrupt Enable + 5 + 1 + + + PER6 + Periodic Interval 6 Interrupt Enable + 6 + 1 + + + PER7 + Periodic Interval 7 Interrupt Enable + 7 + 1 + + + ALARM0 + Alarm 0 Interrupt Enable + 8 + 1 + + + OVF + Overflow Interrupt Enable + 15 + 1 + + + + + INTENSET + MODE2 Interrupt Enable Set + 0xA + 16 + 0x0000 + + + PER0 + Periodic Interval 0 Enable + 0 + 1 + + + PER1 + Periodic Interval 1 Enable + 1 + 1 + + + PER2 + Periodic Interval 2 Enable + 2 + 1 + + + PER3 + Periodic Interval 3 Enable + 3 + 1 + + + PER4 + Periodic Interval 4 Enable + 4 + 1 + + + PER5 + Periodic Interval 5 Enable + 5 + 1 + + + PER6 + Periodic Interval 6 Enable + 6 + 1 + + + PER7 + Periodic Interval 7 Enable + 7 + 1 + + + ALARM0 + Alarm 0 Interrupt Enable + 8 + 1 + + + OVF + Overflow Interrupt Enable + 15 + 1 + + + + + INTFLAG + MODE2 Interrupt Flag Status and Clear + 0xC + 16 + 0x0000 + + + PER0 + Periodic Interval 0 + 0 + 1 + + + PER1 + Periodic Interval 1 + 1 + 1 + + + PER2 + Periodic Interval 2 + 2 + 1 + + + PER3 + Periodic Interval 3 + 3 + 1 + + + PER4 + Periodic Interval 4 + 4 + 1 + + + PER5 + Periodic Interval 5 + 5 + 1 + + + PER6 + Periodic Interval 6 + 6 + 1 + + + PER7 + Periodic Interval 7 + 7 + 1 + + + ALARM0 + Alarm 0 + 8 + 1 + + + OVF + Overflow + 15 + 1 + + + + + DBGCTRL + Debug Control + 0xE + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + SYNCBUSY + MODE2 Synchronization Busy Status + 0x10 + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Bit Busy + 0 + 1 + + + ENABLE + Enable Bit Busy + 1 + 1 + + + FREQCORR + FREQCORR Register Busy + 2 + 1 + + + CLOCK + CLOCK Register Busy + 3 + 1 + + + ALARM0 + ALARM 0 Register Busy + 5 + 1 + + + MASK0 + MASK 0 Register Busy + 11 + 1 + + + CLOCKSYNC + Clock Read Synchronization Enable Bit Busy + 15 + 1 + + + + + FREQCORR + Frequency Correction + 0x14 + 8 + 0x00 + + + VALUE + Correction Value + 0 + 7 + + + SIGN + Correction Sign + 7 + 1 + + + + + CLOCK + MODE2 Clock Value + 0x18 + 32 + 0x00000000 + + + SECOND + Second + 0 + 6 + + + MINUTE + Minute + 6 + 6 + + + HOUR + Hour + 12 + 5 + + HOURSelect + + AM + AM when CLKREP in 12-hour + 0x00 + + + PM + PM when CLKREP in 12-hour + 0x10 + + + + + DAY + Day + 17 + 5 + + + MONTH + Month + 22 + 4 + + + YEAR + Year + 26 + 6 + + + + + ALARM + MODE2_ALARM Alarm n Value + 0x20 + 32 + 0x00000000 + + + SECOND + Second + 0 + 6 + + + MINUTE + Minute + 6 + 6 + + + HOUR + Hour + 12 + 5 + + HOURSelect + + AM + Morning hour + 0x00 + + + PM + Afternoon hour + 0x10 + + + + + DAY + Day + 17 + 5 + + + MONTH + Month + 22 + 4 + + + YEAR + Year + 26 + 6 + + + + + MASK + MODE2_ALARM Alarm n Mask + 0x24 + 8 + 0x00 + + + SEL + Alarm Mask Selection + 0 + 3 + + SELSelect + + OFF + Alarm Disabled + 0x0 + + + SS + Match seconds only + 0x1 + + + MMSS + Match seconds and minutes only + 0x2 + + + HHMMSS + Match seconds, minutes, and hours only + 0x3 + + + DDHHMMSS + Match seconds, minutes, hours, and days only + 0x4 + + + MMDDHHMMSS + Match seconds, minutes, hours, days, and months only + 0x5 + + + YYMMDDHHMMSS + Match seconds, minutes, hours, days, months, and years + 0x6 + + + + + + + + + + SERCOM0 + U22013.1.1 + Serial Communication Interface + SERCOM + SERCOM_ + 0x42000400 + + 0 + 0x31 + registers + + + SERCOM0 + 9 + + + + I2CM + I2C Master Mode + SercomI2cm + 0x0 + + CTRLA + I2CM Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run in Standby + 7 + 1 + + + PINOUT + Pin Usage + 16 + 1 + + + SDAHOLD + SDA Hold Time + 20 + 2 + + SDAHOLDSelect + + DISABLE + Disabled + 0x0 + + + 75NS + 50-100ns hold time + 0x1 + + + 450NS + 300-600ns hold time + 0x2 + + + 600NS + 400-800ns hold time + 0x3 + + + + + MEXTTOEN + Master SCL Low Extend Timeout + 22 + 1 + + + SEXTTOEN + Slave SCL Low Extend Timeout + 23 + 1 + + + SPEED + Transfer Speed + 24 + 2 + + SPEEDSelect + + STANDARD_AND_FAST_MODE + Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz + 0x0 + + + FASTPLUS_MODE + Fast-mode Plus Upto 1MHz + 0x1 + + + HIGH_SPEED_MODE + High-speed mode Upto 3.4MHz + 0x2 + + + + + SCLSM + SCL Clock Stretch Mode + 27 + 1 + + + INACTOUT + Inactive Time-Out + 28 + 2 + + INACTOUTSelect + + DISABLE + Disabled + 0x0 + + + 55US + 5-6 SCL Time-Out(50-60us) + 0x1 + + + 105US + 10-11 SCL Time-Out(100-110us) + 0x2 + + + 205US + 20-21 SCL Time-Out(200-210us) + 0x3 + + + + + LOWTOUTEN + SCL Low Timeout Enable + 30 + 1 + + + + + CTRLB + I2CM Control B + 0x4 + 32 + 0x00000000 + + + SMEN + Smart Mode Enable + 8 + 1 + + + QCEN + Quick Command Enable + 9 + 1 + + + CMD + Command + 16 + 2 + + + ACKACT + Acknowledge Action + 18 + 1 + + + + + BAUD + I2CM Baud Rate + 0xC + 32 + 0x00000000 + + + BAUD + Baud Rate Value + 0 + 8 + + + BAUDLOW + Baud Rate Value Low + 8 + 8 + + + HSBAUD + High Speed Baud Rate Value + 16 + 8 + + + HSBAUDLOW + High Speed Baud Rate Value Low + 24 + 8 + + + + + INTENCLR + I2CM Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + MB + Master On Bus Interrupt Disable + 0 + 1 + + + SB + Slave On Bus Interrupt Disable + 1 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + I2CM Interrupt Enable Set + 0x16 + 8 + 0x00 + + + MB + Master On Bus Interrupt Enable + 0 + 1 + + + SB + Slave On Bus Interrupt Enable + 1 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + I2CM Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + MB + Master On Bus Interrupt + 0 + 1 + + + SB + Slave On Bus Interrupt + 1 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + I2CM Status + 0x1A + 16 + 0x0000 + + + BUSERR + Bus Error + 0 + 1 + + + ARBLOST + Arbitration Lost + 1 + 1 + + + RXNACK + Received Not Acknowledge + 2 + 1 + + + BUSSTATE + Bus State + 4 + 2 + + + LOWTOUT + SCL Low Timeout + 6 + 1 + + + CLKHOLD + Clock Hold + 7 + 1 + + + MEXTTOUT + Master SCL Low Extend Timeout + 8 + 1 + + + SEXTTOUT + Slave SCL Low Extend Timeout + 9 + 1 + + + LENERR + Length Error + 10 + 1 + + + + + SYNCBUSY + I2CM Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + SYSOP + System Operation Synchronization Busy + 2 + 1 + + + + + ADDR + I2CM Address + 0x24 + 32 + 0x00000000 + + + ADDR + Address Value + 0 + 11 + + + LENEN + Length Enable + 13 + 1 + + + HS + High Speed Mode + 14 + 1 + + + TENBITEN + Ten Bit Addressing Enable + 15 + 1 + + + LEN + Length + 16 + 8 + + + + + DATA + I2CM Data + 0x28 + 8 + 0x00 + + + DATA + Data Value + 0 + 8 + + + + + DBGCTRL + I2CM Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + I2CS + I2C Slave Mode + I2CM + SercomI2cs + 0x0 + + CTRLA + I2CS Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + PINOUT + Pin Usage + 16 + 1 + + + SDAHOLD + SDA Hold Time + 20 + 2 + + SDAHOLDSelect + + DISABLE + Disabled + 0x0 + + + 75NS + 50-100ns hold time + 0x1 + + + 450NS + 300-600ns hold time + 0x2 + + + 600NS + 400-800ns hold time + 0x3 + + + + + SEXTTOEN + Slave SCL Low Extend Timeout + 23 + 1 + + + SPEED + Transfer Speed + 24 + 2 + + SPEEDSelect + + STANDARD_AND_FAST_MODE + Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz + 0x0 + + + FASTPLUS_MODE + Fast-mode Plus Upto 1MHz + 0x1 + + + HIGH_SPEED_MODE + High-speed mode Upto 3.4MHz + 0x2 + + + + + SCLSM + SCL Clock Stretch Mode + 27 + 1 + + + LOWTOUTEN + SCL Low Timeout Enable + 30 + 1 + + + + + CTRLB + I2CS Control B + 0x4 + 32 + 0x00000000 + + + SMEN + Smart Mode Enable + 8 + 1 + + + GCMD + PMBus Group Command + 9 + 1 + + + AACKEN + Automatic Address Acknowledge + 10 + 1 + + + AMODE + Address Mode + 14 + 2 + + + CMD + Command + 16 + 2 + + + ACKACT + Acknowledge Action + 18 + 1 + + + + + INTENCLR + I2CS Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + PREC + Stop Received Interrupt Disable + 0 + 1 + + + AMATCH + Address Match Interrupt Disable + 1 + 1 + + + DRDY + Data Interrupt Disable + 2 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + I2CS Interrupt Enable Set + 0x16 + 8 + 0x00 + + + PREC + Stop Received Interrupt Enable + 0 + 1 + + + AMATCH + Address Match Interrupt Enable + 1 + 1 + + + DRDY + Data Interrupt Enable + 2 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + I2CS Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + PREC + Stop Received Interrupt + 0 + 1 + + + AMATCH + Address Match Interrupt + 1 + 1 + + + DRDY + Data Interrupt + 2 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + I2CS Status + 0x1A + 16 + 0x0000 + + + BUSERR + Bus Error + 0 + 1 + + + COLL + Transmit Collision + 1 + 1 + + + RXNACK + Received Not Acknowledge + 2 + 1 + + + DIR + Read/Write Direction + 3 + 1 + + + SR + Repeated Start + 4 + 1 + + + LOWTOUT + SCL Low Timeout + 6 + 1 + + + CLKHOLD + Clock Hold + 7 + 1 + + + SEXTTOUT + Slave SCL Low Extend Timeout + 9 + 1 + + + HS + High Speed + 10 + 1 + + + + + SYNCBUSY + I2CS Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + + + ADDR + I2CS Address + 0x24 + 32 + 0x00000000 + + + GENCEN + General Call Address Enable + 0 + 1 + + + ADDR + Address Value + 1 + 10 + + + TENBITEN + Ten Bit Addressing Enable + 15 + 1 + + + ADDRMASK + Address Mask + 17 + 10 + + + + + DATA + I2CS Data + 0x28 + 8 + 0x00 + + + DATA + Data Value + 0 + 8 + + + + + + SPIS + SPI Slave Mode + I2CM + SercomSpis + 0x0 + + CTRLA + SPIS Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + IBON + Immediate Buffer Overflow Notification + 8 + 1 + + + DOPO + Data Out Pinout + 16 + 2 + + DOPOSelect + + PAD0 + DO on PAD[0], SCK on PAD[1] and SS on PAD[2] + 0x0 + + + PAD1 + DO on PAD[2], SCK on PAD[3] and SS on PAD[1] + 0x1 + + + PAD2 + DO on PAD[3], SCK on PAD[1] and SS on PAD[2] + 0x2 + + + PAD3 + DO on PAD[0], SCK on PAD[3] and SS on PAD[1] + 0x3 + + + + + DIPO + Data In Pinout + 20 + 2 + + DIPOSelect + + PAD0 + SERCOM PAD[0] + 0x0 + + + PAD1 + SERCOM PAD[1] + 0x1 + + + PAD2 + SERCOM PAD[2] + 0x2 + + + PAD3 + SERCOM PAD[3] + 0x3 + + + + + FORM + Frame Format + 24 + 4 + + FORMSelect + + SPI_FRAME + SPI Frame + 0x0 + + + SPI_FRAME_WITH_ADDR + SPI Frame with Addr + 0x2 + + + + + CPHA + Clock Phase + 28 + 1 + + CPHASelect + + LEADING_EDGE + The data is sampled on a leading SCK edge and changed on a trailing SCK edge + 0x0 + + + TRAILING_EDGE + The data is sampled on a trailing SCK edge and changed on a leading SCK edge + 0x1 + + + + + CPOL + Clock Polarity + 29 + 1 + + CPOLSelect + + IDLE_LOW + SCK is low when idle + 0x0 + + + IDLE_HIGH + SCK is high when idle + 0x1 + + + + + DORD + Data Order + 30 + 1 + + DORDSelect + + MSB + MSB is transferred first + 0x0 + + + LSB + LSB is transferred first + 0x1 + + + + + + + CTRLB + SPIS Control B + 0x4 + 32 + 0x00000000 + + + CHSIZE + Character Size + 0 + 3 + + CHSIZESelect + + 8_BIT + 8 bits + 0x0 + + + 9_BIT + 9 bits + 0x1 + + + + + PLOADEN + Data Preload Enable + 6 + 1 + + + SSDE + Slave Select Low Detect Enable + 9 + 1 + + + MSSEN + Master Slave Select Enable + 13 + 1 + + + AMODE + Address Mode + 14 + 2 + + AMODESelect + + MASK + SPI Address mask + 0x0 + + + 2_ADDRESSES + Two unique Addressess + 0x1 + + + RANGE + Address Range + 0x2 + + + + + RXEN + Receiver Enable + 17 + 1 + + + + + BAUD + SPIS Baud Rate + 0xC + 8 + 0x00 + + + BAUD + Baud Rate Value + 0 + 8 + + + + + INTENCLR + SPIS Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Disable + 0 + 1 + + + TXC + Transmit Complete Interrupt Disable + 1 + 1 + + + RXC + Receive Complete Interrupt Disable + 2 + 1 + + + SSL + Slave Select Low Interrupt Disable + 3 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + SPIS Interrupt Enable Set + 0x16 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Enable + 0 + 1 + + + TXC + Transmit Complete Interrupt Enable + 1 + 1 + + + RXC + Receive Complete Interrupt Enable + 2 + 1 + + + SSL + Slave Select Low Interrupt Enable + 3 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + SPIS Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt + 0 + 1 + + + TXC + Transmit Complete Interrupt + 1 + 1 + + + RXC + Receive Complete Interrupt + 2 + 1 + + + SSL + Slave Select Low Interrupt Flag + 3 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + SPIS Status + 0x1A + 16 + 0x0000 + + + BUFOVF + Buffer Overflow + 2 + 1 + + + + + SYNCBUSY + SPIS Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + CTRLB + CTRLB Synchronization Busy + 2 + 1 + + + + + ADDR + SPIS Address + 0x24 + 32 + 0x00000000 + + + ADDR + Address Value + 0 + 8 + + + ADDRMASK + Address Mask + 16 + 8 + + + + + DATA + SPIS Data + 0x28 + 32 + 0x00000000 + + + DATA + Data Value + 0 + 9 + + + + + DBGCTRL + SPIS Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + SPIM + SPI Master Mode + I2CM + SercomSpim + 0x0 + + CTRLA + SPIM Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + IBON + Immediate Buffer Overflow Notification + 8 + 1 + + + DOPO + Data Out Pinout + 16 + 2 + + DOPOSelect + + PAD0 + DO on PAD[0], SCK on PAD[1] and SS on PAD[2] + 0x0 + + + PAD1 + DO on PAD[2], SCK on PAD[3] and SS on PAD[1] + 0x1 + + + PAD2 + DO on PAD[3], SCK on PAD[1] and SS on PAD[2] + 0x2 + + + PAD3 + DO on PAD[0], SCK on PAD[3] and SS on PAD[1] + 0x3 + + + + + DIPO + Data In Pinout + 20 + 2 + + DIPOSelect + + PAD0 + SERCOM PAD[0] + 0x0 + + + PAD1 + SERCOM PAD[1] + 0x1 + + + PAD2 + SERCOM PAD[2] + 0x2 + + + PAD3 + SERCOM PAD[3] + 0x3 + + + + + FORM + Frame Format + 24 + 4 + + FORMSelect + + SPI_FRAME + SPI Frame + 0x0 + + + SPI_FRAME_WITH_ADDR + SPI Frame with Addr + 0x2 + + + + + CPHA + Clock Phase + 28 + 1 + + CPHASelect + + LEADING_EDGE + The data is sampled on a leading SCK edge and changed on a trailing SCK edge + 0x0 + + + TRAILING_EDGE + The data is sampled on a trailing SCK edge and changed on a leading SCK edge + 0x1 + + + + + CPOL + Clock Polarity + 29 + 1 + + CPOLSelect + + IDLE_LOW + SCK is low when idle + 0x0 + + + IDLE_HIGH + SCK is high when idle + 0x1 + + + + + DORD + Data Order + 30 + 1 + + DORDSelect + + MSB + MSB is transferred first + 0x0 + + + LSB + LSB is transferred first + 0x1 + + + + + + + CTRLB + SPIM Control B + 0x4 + 32 + 0x00000000 + + + CHSIZE + Character Size + 0 + 3 + + CHSIZESelect + + 8_BIT + 8 bits + 0x0 + + + 9_BIT + 9 bits + 0x1 + + + + + PLOADEN + Data Preload Enable + 6 + 1 + + + SSDE + Slave Select Low Detect Enable + 9 + 1 + + + MSSEN + Master Slave Select Enable + 13 + 1 + + + AMODE + Address Mode + 14 + 2 + + AMODESelect + + MASK + SPI Address mask + 0x0 + + + 2_ADDRESSES + Two unique Addressess + 0x1 + + + RANGE + Address Range + 0x2 + + + + + RXEN + Receiver Enable + 17 + 1 + + + + + BAUD + SPIM Baud Rate + 0xC + 8 + 0x00 + + + BAUD + Baud Rate Value + 0 + 8 + + + + + INTENCLR + SPIM Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Disable + 0 + 1 + + + TXC + Transmit Complete Interrupt Disable + 1 + 1 + + + RXC + Receive Complete Interrupt Disable + 2 + 1 + + + SSL + Slave Select Low Interrupt Disable + 3 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + SPIM Interrupt Enable Set + 0x16 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Enable + 0 + 1 + + + TXC + Transmit Complete Interrupt Enable + 1 + 1 + + + RXC + Receive Complete Interrupt Enable + 2 + 1 + + + SSL + Slave Select Low Interrupt Enable + 3 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + SPIM Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt + 0 + 1 + + + TXC + Transmit Complete Interrupt + 1 + 1 + + + RXC + Receive Complete Interrupt + 2 + 1 + + + SSL + Slave Select Low Interrupt Flag + 3 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + SPIM Status + 0x1A + 16 + 0x0000 + + + BUFOVF + Buffer Overflow + 2 + 1 + + + + + SYNCBUSY + SPIM Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + CTRLB + CTRLB Synchronization Busy + 2 + 1 + + + + + ADDR + SPIM Address + 0x24 + 32 + 0x00000000 + + + ADDR + Address Value + 0 + 8 + + + ADDRMASK + Address Mask + 16 + 8 + + + + + DATA + SPIM Data + 0x28 + 32 + 0x00000000 + + + DATA + Data Value + 0 + 9 + + + + + DBGCTRL + SPIM Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + USART_EXT + USART EXTERNAL CLOCK Mode + I2CM + SercomUsart_ext + 0x0 + + CTRLA + USART_EXT Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + IBON + Immediate Buffer Overflow Notification + 8 + 1 + + + SAMPR + Sample + 13 + 3 + + SAMPRSelect + + 16X_ARITHMETIC + 16x over-sampling using arithmetic baudrate generation + 0x0 + + + 16X_FRACTIONAL + 16x over-sampling using fractional baudrate generation + 0x1 + + + 8X_ARITHMETIC + 8x over-sampling using arithmetic baudrate generation + 0x2 + + + 8X_FRACTIONAL + 8x over-sampling using fractional baudrate generation + 0x3 + + + 3X_ARITHMETIC + 3x over-sampling using arithmetic baudrate generation + 0x4 + + + + + TXPO + Transmit Data Pinout + 16 + 2 + + TXPOSelect + + PAD0 + SERCOM PAD[0] is used for data transmission + 0x0 + + + PAD2 + SERCOM PAD[2] is used for data transmission + 0x1 + + + + + RXPO + Receive Data Pinout + 20 + 2 + + RXPOSelect + + PAD0 + SERCOM PAD[0] is used for data reception + 0x0 + + + PAD1 + SERCOM PAD[1] is used for data reception + 0x1 + + + PAD2 + SERCOM PAD[2] is used for data reception + 0x2 + + + PAD3 + SERCOM PAD[3] is used for data reception + 0x3 + + + + + SAMPA + Sample Adjustment + 22 + 2 + + + FORM + Frame Format + 24 + 4 + + FORMSelect + + USART_FRAME_NO_PARITY + USART frame + 0x0 + + + USART_FRAME_WITH_PARITY + USART frame with parity + 0x1 + + + USART_FRAME_LIN_MASTER_MODE + LIN Master - Break and sync generation + 0x2 + + + USART_FRAME_AUTO_BAUD_NO_PARITY + Auto-baud - break detection and auto-baud + 0x4 + + + USART_FRAME_AUTO_BAUD_WITH_PARITY + Auto-baud - break detection and auto-baud with parity + 0x5 + + + + + CMODE + Communication Mode + 28 + 1 + + CMODESelect + + ASYNC + Asynchronous Communication + 0x0 + + + SYNC + Synchronous Communication + 0x1 + + + + + CPOL + Clock Polarity + 29 + 1 + + CPOLSelect + + IDLE_LOW + TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge + 0x0 + + + IDLE_HIGH + TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge + 0x1 + + + + + DORD + Data Order + 30 + 1 + + DORDSelect + + MSB + MSB is transmitted first + 0x0 + + + LSB + LSB is transmitted first + 0x1 + + + + + + + CTRLB + USART_EXT Control B + 0x4 + 32 + 0x00000000 + + + CHSIZE + Character Size + 0 + 3 + + CHSIZESelect + + 8_BIT + 8 Bits + 0x0 + + + 9_BIT + 9 Bits + 0x1 + + + 5_BIT + 5 Bits + 0x5 + + + 6_BIT + 6 Bits + 0x6 + + + 7_BIT + 7 Bits + 0x7 + + + + + SBMODE + Stop Bit Mode + 6 + 1 + + SBMODESelect + + 1_BIT + One Stop Bit + 0x0 + + + 2_BIT + Two Stop Bits + 0x1 + + + + + COLDEN + Collision Detection Enable + 8 + 1 + + + SFDE + Start of Frame Detection Enable + 9 + 1 + + + ENC + Encoding Format + 10 + 1 + + + PMODE + Parity Mode + 13 + 1 + + PMODESelect + + EVEN + Even Parity + 0x0 + + + ODD + Odd Parity + 0x1 + + + + + TXEN + Transmitter Enable + 16 + 1 + + + RXEN + Receiver Enable + 17 + 1 + + + LINCMD + LIN Command + 24 + 2 + + + + + CTRLC + USART_EXT Control C + 0x8 + 32 + 0x00000000 + + + GTIME + RS485 Guard Time + 0 + 3 + + + BRKLEN + LIN Master Break Length + 8 + 2 + + + HDRDLY + LIN Master Header Delay + 10 + 2 + + + + + BAUD + USART_EXT Baud Rate + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 16 + + + + + BAUD_FRAC_MODE + USART_EXT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 13 + + + FP + Fractional Part + 13 + 3 + + + + + BAUD_FRACFP_MODE + USART_EXT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 13 + + + FP + Fractional Part + 13 + 3 + + + + + BAUD_USARTFP_MODE + USART_EXT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 16 + + + + + RXPL + USART_EXT Receive Pulse Length + 0xE + 8 + 0x00 + + + RXPL + Receive Pulse Length + 0 + 8 + + + + + INTENCLR + USART_EXT Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Disable + 0 + 1 + + + TXC + Transmit Complete Interrupt Disable + 1 + 1 + + + RXC + Receive Complete Interrupt Disable + 2 + 1 + + + RXS + Receive Start Interrupt Disable + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt Disable + 4 + 1 + + + RXBRK + Break Received Interrupt Disable + 5 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + USART_EXT Interrupt Enable Set + 0x16 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Enable + 0 + 1 + + + TXC + Transmit Complete Interrupt Enable + 1 + 1 + + + RXC + Receive Complete Interrupt Enable + 2 + 1 + + + RXS + Receive Start Interrupt Enable + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt Enable + 4 + 1 + + + RXBRK + Break Received Interrupt Enable + 5 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + USART_EXT Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt + 0 + 1 + + + TXC + Transmit Complete Interrupt + 1 + 1 + + + RXC + Receive Complete Interrupt + 2 + 1 + + + RXS + Receive Start Interrupt + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt + 4 + 1 + + + RXBRK + Break Received Interrupt + 5 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + USART_EXT Status + 0x1A + 16 + 0x0000 + + + PERR + Parity Error + 0 + 1 + + + FERR + Frame Error + 1 + 1 + + + BUFOVF + Buffer Overflow + 2 + 1 + + + CTS + Clear To Send + 3 + 1 + + + ISF + Inconsistent Sync Field + 4 + 1 + + + COLL + Collision Detected + 5 + 1 + + + TXE + Transmitter Empty + 6 + 1 + + + + + SYNCBUSY + USART_EXT Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + CTRLB + CTRLB Synchronization Busy + 2 + 1 + + + + + DATA + USART_EXT Data + 0x28 + 16 + 0x0000 + + + DATA + Data Value + 0 + 9 + + + + + DBGCTRL + USART_EXT Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + USART_INT + USART INTERNAL CLOCK Mode + I2CM + SercomUsart_int + 0x0 + + CTRLA + USART_INT Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + IBON + Immediate Buffer Overflow Notification + 8 + 1 + + + SAMPR + Sample + 13 + 3 + + SAMPRSelect + + 16X_ARITHMETIC + 16x over-sampling using arithmetic baudrate generation + 0x0 + + + 16X_FRACTIONAL + 16x over-sampling using fractional baudrate generation + 0x1 + + + 8X_ARITHMETIC + 8x over-sampling using arithmetic baudrate generation + 0x2 + + + 8X_FRACTIONAL + 8x over-sampling using fractional baudrate generation + 0x3 + + + 3X_ARITHMETIC + 3x over-sampling using arithmetic baudrate generation + 0x4 + + + + + TXPO + Transmit Data Pinout + 16 + 2 + + TXPOSelect + + PAD0 + SERCOM PAD[0] is used for data transmission + 0x0 + + + PAD2 + SERCOM PAD[2] is used for data transmission + 0x1 + + + + + RXPO + Receive Data Pinout + 20 + 2 + + RXPOSelect + + PAD0 + SERCOM PAD[0] is used for data reception + 0x0 + + + PAD1 + SERCOM PAD[1] is used for data reception + 0x1 + + + PAD2 + SERCOM PAD[2] is used for data reception + 0x2 + + + PAD3 + SERCOM PAD[3] is used for data reception + 0x3 + + + + + SAMPA + Sample Adjustment + 22 + 2 + + + FORM + Frame Format + 24 + 4 + + FORMSelect + + USART_FRAME_NO_PARITY + USART frame + 0x0 + + + USART_FRAME_WITH_PARITY + USART frame with parity + 0x1 + + + USART_FRAME_LIN_MASTER_MODE + LIN Master - Break and sync generation + 0x2 + + + USART_FRAME_AUTO_BAUD_NO_PARITY + Auto-baud - break detection and auto-baud + 0x4 + + + USART_FRAME_AUTO_BAUD_WITH_PARITY + Auto-baud - break detection and auto-baud with parity + 0x5 + + + + + CMODE + Communication Mode + 28 + 1 + + CMODESelect + + ASYNC + Asynchronous Communication + 0x0 + + + SYNC + Synchronous Communication + 0x1 + + + + + CPOL + Clock Polarity + 29 + 1 + + CPOLSelect + + IDLE_LOW + TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge + 0x0 + + + IDLE_HIGH + TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge + 0x1 + + + + + DORD + Data Order + 30 + 1 + + DORDSelect + + MSB + MSB is transmitted first + 0x0 + + + LSB + LSB is transmitted first + 0x1 + + + + + + + CTRLB + USART_INT Control B + 0x4 + 32 + 0x00000000 + + + CHSIZE + Character Size + 0 + 3 + + CHSIZESelect + + 8_BIT + 8 Bits + 0x0 + + + 9_BIT + 9 Bits + 0x1 + + + 5_BIT + 5 Bits + 0x5 + + + 6_BIT + 6 Bits + 0x6 + + + 7_BIT + 7 Bits + 0x7 + + + + + SBMODE + Stop Bit Mode + 6 + 1 + + SBMODESelect + + 1_BIT + One Stop Bit + 0x0 + + + 2_BIT + Two Stop Bits + 0x1 + + + + + COLDEN + Collision Detection Enable + 8 + 1 + + + SFDE + Start of Frame Detection Enable + 9 + 1 + + + ENC + Encoding Format + 10 + 1 + + + PMODE + Parity Mode + 13 + 1 + + PMODESelect + + EVEN + Even Parity + 0x0 + + + ODD + Odd Parity + 0x1 + + + + + TXEN + Transmitter Enable + 16 + 1 + + + RXEN + Receiver Enable + 17 + 1 + + + LINCMD + LIN Command + 24 + 2 + + + + + CTRLC + USART_INT Control C + 0x8 + 32 + 0x00000000 + + + GTIME + RS485 Guard Time + 0 + 3 + + + BRKLEN + LIN Master Break Length + 8 + 2 + + + HDRDLY + LIN Master Header Delay + 10 + 2 + + + + + BAUD + USART_INT Baud Rate + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 16 + + + + + BAUD_FRAC_MODE + USART_INT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 13 + + + FP + Fractional Part + 13 + 3 + + + + + BAUD_FRACFP_MODE + USART_INT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 13 + + + FP + Fractional Part + 13 + 3 + + + + + BAUD_USARTFP_MODE + USART_INT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 16 + + + + + RXPL + USART_INT Receive Pulse Length + 0xE + 8 + 0x00 + + + RXPL + Receive Pulse Length + 0 + 8 + + + + + INTENCLR + USART_INT Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Disable + 0 + 1 + + + TXC + Transmit Complete Interrupt Disable + 1 + 1 + + + RXC + Receive Complete Interrupt Disable + 2 + 1 + + + RXS + Receive Start Interrupt Disable + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt Disable + 4 + 1 + + + RXBRK + Break Received Interrupt Disable + 5 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + USART_INT Interrupt Enable Set + 0x16 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Enable + 0 + 1 + + + TXC + Transmit Complete Interrupt Enable + 1 + 1 + + + RXC + Receive Complete Interrupt Enable + 2 + 1 + + + RXS + Receive Start Interrupt Enable + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt Enable + 4 + 1 + + + RXBRK + Break Received Interrupt Enable + 5 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + USART_INT Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt + 0 + 1 + + + TXC + Transmit Complete Interrupt + 1 + 1 + + + RXC + Receive Complete Interrupt + 2 + 1 + + + RXS + Receive Start Interrupt + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt + 4 + 1 + + + RXBRK + Break Received Interrupt + 5 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + USART_INT Status + 0x1A + 16 + 0x0000 + + + PERR + Parity Error + 0 + 1 + + + FERR + Frame Error + 1 + 1 + + + BUFOVF + Buffer Overflow + 2 + 1 + + + CTS + Clear To Send + 3 + 1 + + + ISF + Inconsistent Sync Field + 4 + 1 + + + COLL + Collision Detected + 5 + 1 + + + TXE + Transmitter Empty + 6 + 1 + + + + + SYNCBUSY + USART_INT Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + CTRLB + CTRLB Synchronization Busy + 2 + 1 + + + + + DATA + USART_INT Data + 0x28 + 16 + 0x0000 + + + DATA + Data Value + 0 + 9 + + + + + DBGCTRL + USART_INT Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + + + SERCOM1 + 0x42000800 + + SERCOM1 + 10 + + + + SERCOM2 + 0x42000C00 + + SERCOM2 + 11 + + + + SERCOM3 + 0x42001000 + + SERCOM3 + 12 + + + + SUPC + U21172.1.1 + Supply Controller + SUPC + SUPC_ + 0x40001800 + + 0 + 0x20 + registers + + + + INTENCLR + Interrupt Enable Clear + 0x0 + 32 + 0x00000000 + + + BODVDDRDY + BODVDD Ready + 0 + 1 + + + BODVDDDET + BODVDD Detection + 1 + 1 + + + BVDDSRDY + BODVDD Synchronization Ready + 2 + 1 + + + BODCORERDY + BODCORE Ready + 3 + 1 + + + BODCOREDET + BODCORE Detection + 4 + 1 + + + BCORESRDY + BODCORE Synchronization Ready + 5 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x4 + 32 + 0x00000000 + + + BODVDDRDY + BODVDD Ready + 0 + 1 + + + BODVDDDET + BODVDD Detection + 1 + 1 + + + BVDDSRDY + BODVDD Synchronization Ready + 2 + 1 + + + BODCORERDY + BODCORE Ready + 3 + 1 + + + BODCOREDET + BODCORE Detection + 4 + 1 + + + BCORESRDY + BODCORE Synchronization Ready + 5 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x8 + 32 + 0x00000000 + + + BODVDDRDY + BODVDD Ready + 0 + 1 + + + BODVDDDET + BODVDD Detection + 1 + 1 + + + BVDDSRDY + BODVDD Synchronization Ready + 2 + 1 + + + BODCORERDY + BODCORE Ready + 3 + 1 + + + BODCOREDET + BODCORE Detection + 4 + 1 + + + BCORESRDY + BODCORE Synchronization Ready + 5 + 1 + + + + + STATUS + Power and Clocks Status + 0xC + 32 + read-only + 0x00000000 + + + BODVDDRDY + BODVDD Ready + 0 + 1 + + + BODVDDDET + BODVDD Detection + 1 + 1 + + + BVDDSRDY + BODVDD Synchronization Ready + 2 + 1 + + + BODCORERDY + BODCORE Ready + 3 + 1 + + + BODCOREDET + BODCORE Detection + 4 + 1 + + + BCORESRDY + BODCORE Synchronization Ready + 5 + 1 + + + + + BODVDD + BODVDD Control + 0x10 + 32 + 0x00000000 + + + ENABLE + Enable + 1 + 1 + + + HYST + Hysteresis Enable + 2 + 1 + + + ACTION + Action when Threshold Crossed + 3 + 2 + + ACTIONSelect + + NONE + No action + 0x0 + + + RESET + The BODVDD generates a reset + 0x1 + + + INT + The BODVDD generates an interrupt + 0x2 + + + + + STDBYCFG + Configuration in Standby mode + 5 + 1 + + + RUNSTDBY + Run during Standby + 6 + 1 + + + ACTCFG + Configuration in Active mode + 8 + 1 + + + PSEL + Prescaler Select + 12 + 4 + + PSELSelect + + DIV2 + Divide clock by 2 + 0x0 + + + DIV4 + Divide clock by 4 + 0x1 + + + DIV8 + Divide clock by 8 + 0x2 + + + DIV16 + Divide clock by 16 + 0x3 + + + DIV32 + Divide clock by 32 + 0x4 + + + DIV64 + Divide clock by 64 + 0x5 + + + DIV128 + Divide clock by 128 + 0x6 + + + DIV256 + Divide clock by 256 + 0x7 + + + DIV512 + Divide clock by 512 + 0x8 + + + DIV1024 + Divide clock by 1024 + 0x9 + + + DIV2048 + Divide clock by 2048 + 0xA + + + DIV4096 + Divide clock by 4096 + 0xB + + + DIV8192 + Divide clock by 8192 + 0xC + + + DIV16384 + Divide clock by 16384 + 0xD + + + DIV32768 + Divide clock by 32768 + 0xE + + + DIV65536 + Divide clock by 65536 + 0xF + + + + + LEVEL + Threshold Level for VDD + 16 + 6 + + + + + BODCORE + BODCORE Control + 0x14 + 32 + 0x00000000 + + + ENABLE + Enable + 1 + 1 + + + HYST + Hysteresis Enable + 2 + 1 + + + ACTION + Action when Threshold Crossed + 3 + 2 + + ACTIONSelect + + NONE + No action + 0x0 + + + RESET + The BODCORE generates a reset + 0x1 + + + INT + The BODCORE generates an interrupt + 0x2 + + + + + STDBYCFG + Configuration in Standby mode + 5 + 1 + + + RUNSTDBY + Run during Standby + 6 + 1 + + + ACTCFG + Configuration in Active mode + 8 + 1 + + + PSEL + Prescaler Select + 12 + 4 + + PSELSelect + + DIV2 + Divide clock by 2 + 0x0 + + + DIV4 + Divide clock by 4 + 0x1 + + + DIV8 + Divide clock by 8 + 0x2 + + + DIV16 + Divide clock by 16 + 0x3 + + + DIV32 + Divide clock by 32 + 0x4 + + + DIV64 + Divide clock by 64 + 0x5 + + + DIV128 + Divide clock by 128 + 0x6 + + + DIV256 + Divide clock by 256 + 0x7 + + + DIV512 + Divide clock by 512 + 0x8 + + + DIV1024 + Divide clock by 1024 + 0x9 + + + DIV2048 + Divide clock by 2048 + 0xA + + + DIV4096 + Divide clock by 4096 + 0xB + + + DIV8192 + Divide clock by 8192 + 0xC + + + DIV16384 + Divide clock by 16384 + 0xD + + + DIV32768 + Divide clock by 32768 + 0xE + + + DIV65536 + Divide clock by 65536 + 0xF + + + + + LEVEL + Threshold Level + 16 + 6 + + + + + VREG + VREG Control + 0x18 + 32 + 0x00000000 + + + ENABLE + Enable + 1 + 1 + + + RUNSTDBY + Run during Standby + 6 + 1 + + + + + VREF + VREF Control + 0x1C + 32 + 0x00000000 + + + TSEN + Temperature Sensor Output Enable + 1 + 1 + + + VREFOE + Voltage Reference Output Enable + 2 + 1 + + + RUNSTDBY + Run during Standby + 6 + 1 + + + ONDEMAND + On Demand Contrl + 7 + 1 + + + SEL + Voltage Reference Selection + 16 + 4 + + SELSelect + + 1V024 + 1.024V voltage reference typical value + 0x0 + + + 2V048 + 2.048V voltage reference typical value + 0x2 + + + 4V096 + 4.096V voltage reference typical value + 0x3 + + + + + + + + + TC0 + U22492.0.0 + Basic Timer Counter + TC + TC_ + 0x42003000 + + 0 + 0x38 + registers + + + TC0 + 20 + + + + COUNT8 + 8-bit Counter Mode + TcCount8 + 0x0 + + CTRLA + Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Timer Counter Mode + 2 + 2 + + MODESelect + + COUNT16 + Counter in 16-bit mode + 0 + + + COUNT8 + Counter in 8-bit mode + 1 + + + COUNT32 + Counter in 32-bit mode + 2 + + + + + PRESCSYNC + Prescaler and Counter Synchronization + 4 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset the counter on next generic clock + 0 + + + PRESC + Reload or reset the counter on next prescaler clock + 1 + + + RESYNC + Reload or reset the counter on next generic clock and reset the prescaler counter + 2 + + + + + RUNSTDBY + Run during Standby + 6 + 1 + + + ONDEMAND + Clock On Demand + 7 + 1 + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + Prescaler: GCLK_TC + 0 + + + DIV2 + Prescaler: GCLK_TC/2 + 1 + + + DIV4 + Prescaler: GCLK_TC/4 + 2 + + + DIV8 + Prescaler: GCLK_TC/8 + 3 + + + DIV16 + Prescaler: GCLK_TC/16 + 4 + + + DIV64 + Prescaler: GCLK_TC/64 + 5 + + + DIV256 + Prescaler: GCLK_TC/256 + 6 + + + DIV1024 + Prescaler: GCLK_TC/1024 + 7 + + + + + ALOCK + Auto Lock + 11 + 1 + + + CAPTEN0 + Capture Channel 0 Enable + 16 + 1 + + + CAPTEN1 + Capture Channel 1 Enable + 17 + 1 + + + COPEN0 + Capture On Pin 0 Enable + 20 + 1 + + + COPEN1 + Capture On Pin 1 Enable + 21 + 1 + + + + + CTRLBCLR + Control B Clear + 0x4 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot on Counter + 2 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + UPDATE + Force update of double-buffered register + 3 + + + READSYNC + Force a read synchronization of COUNT + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + CTRLBSET + Control B Set + 0x5 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot on Counter + 2 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + UPDATE + Force update of double-buffered register + 3 + + + READSYNC + Force a read synchronization of COUNT + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + EVCTRL + Event Control + 0x6 + 16 + 0x0000 + + + EVACT + Event Action + 0 + 3 + + EVACTSelect + + OFF + Event action disabled + 0 + + + RETRIGGER + Start, restart or retrigger TC on event + 1 + + + COUNT + Count on event + 2 + + + START + Start TC on event + 3 + + + STAMP + Time stamp capture + 4 + + + PPW + Period catured in CC0, pulse width in CC1 + 5 + + + PWP + Period catured in CC1, pulse width in CC0 + 6 + + + PW + Pulse width capture + 7 + + + + + TCINV + TC Event Input Polarity + 4 + 1 + + + TCEI + TC Event Enable + 5 + 1 + + + OVFEO + Event Output Enable + 8 + 1 + + + MCEO0 + MC Event Output Enable 0 + 12 + 1 + + + MCEO1 + MC Event Output Enable 1 + 13 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x8 + 8 + 0x00 + + + OVF + OVF Interrupt Disable + 0 + 1 + + + ERR + ERR Interrupt Disable + 1 + 1 + + + MC0 + MC Interrupt Disable 0 + 4 + 1 + + + MC1 + MC Interrupt Disable 1 + 5 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x9 + 8 + 0x00 + + + OVF + OVF Interrupt Enable + 0 + 1 + + + ERR + ERR Interrupt Enable + 1 + 1 + + + MC0 + MC Interrupt Enable 0 + 4 + 1 + + + MC1 + MC Interrupt Enable 1 + 5 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0xA + 8 + 0x00 + + + OVF + OVF Interrupt Flag + 0 + 1 + + + ERR + ERR Interrupt Flag + 1 + 1 + + + MC0 + MC Interrupt Flag 0 + 4 + 1 + + + MC1 + MC Interrupt Flag 1 + 5 + 1 + + + + + STATUS + Status + 0xB + 8 + 0x01 + + + STOP + Stop Status Flag + 0 + 1 + + + SLAVE + Slave Status Flag + 1 + 1 + + + PERBUFV + Synchronization Busy Status + 3 + 1 + + + CCBUFV0 + Compare channel buffer 0 valid + 4 + 1 + + + CCBUFV1 + Compare channel buffer 1 valid + 5 + 1 + + + + + WAVE + Waveform Generation Control + 0xC + 8 + 0x00 + + + WAVEGEN + Waveform Generation Mode + 0 + 2 + + WAVEGENSelect + + NFRQ + Normal frequency + 0 + + + MFRQ + Match frequency + 1 + + + NPWM + Normal PWM + 2 + + + MPWM + Match PWM + 3 + + + + + + + DRVCTRL + Control C + 0xD + 8 + 0x00 + + + INVEN0 + Output Waveform Invert Enable 0 + 0 + 1 + + + INVEN1 + Output Waveform Invert Enable 1 + 1 + 1 + + + + + DBGCTRL + Debug Control + 0xF + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + SYNCBUSY + Synchronization Status + 0x10 + 32 + read-only + 0x00000000 + + + SWRST + swrst + 0 + 1 + + + ENABLE + enable + 1 + 1 + + + CTRLB + CTRLB + 2 + 1 + + + STATUS + STATUS + 3 + 1 + + + COUNT + Counter + 4 + 1 + + + PER + Period + 5 + 1 + + + CC0 + Compare Channel 0 + 6 + 1 + + + CC1 + Compare Channel 1 + 7 + 1 + + + + + COUNT + COUNT8 Count + 0x14 + 8 + 0x00 + + + COUNT + Counter Value + 0 + 8 + + + + + PER + COUNT8 Period + 0x1B + 8 + 0xFF + + + PER + Period Value + 0 + 8 + + + + + 2 + 1 + CC[%s] + COUNT8 Compare and Capture + 0x1C + 8 + 0x00 + + + CC + Counter/Compare Value + 0 + 8 + + + + + PERBUF + COUNT8 Period Buffer + 0x2F + 8 + 0xFF + + + PERBUF + Period Buffer Value + 0 + 8 + + + + + 2 + 1 + CCBUF[%s] + COUNT8 Compare and Capture Buffer + 0x30 + 8 + 0x00 + + + CCBUF + Counter/Compare Buffer Value + 0 + 8 + + + + + + COUNT16 + 16-bit Counter Mode + COUNT8 + TcCount16 + 0x0 + + CTRLA + Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Timer Counter Mode + 2 + 2 + + MODESelect + + COUNT16 + Counter in 16-bit mode + 0 + + + COUNT8 + Counter in 8-bit mode + 1 + + + COUNT32 + Counter in 32-bit mode + 2 + + + + + PRESCSYNC + Prescaler and Counter Synchronization + 4 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset the counter on next generic clock + 0 + + + PRESC + Reload or reset the counter on next prescaler clock + 1 + + + RESYNC + Reload or reset the counter on next generic clock and reset the prescaler counter + 2 + + + + + RUNSTDBY + Run during Standby + 6 + 1 + + + ONDEMAND + Clock On Demand + 7 + 1 + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + Prescaler: GCLK_TC + 0 + + + DIV2 + Prescaler: GCLK_TC/2 + 1 + + + DIV4 + Prescaler: GCLK_TC/4 + 2 + + + DIV8 + Prescaler: GCLK_TC/8 + 3 + + + DIV16 + Prescaler: GCLK_TC/16 + 4 + + + DIV64 + Prescaler: GCLK_TC/64 + 5 + + + DIV256 + Prescaler: GCLK_TC/256 + 6 + + + DIV1024 + Prescaler: GCLK_TC/1024 + 7 + + + + + ALOCK + Auto Lock + 11 + 1 + + + CAPTEN0 + Capture Channel 0 Enable + 16 + 1 + + + CAPTEN1 + Capture Channel 1 Enable + 17 + 1 + + + COPEN0 + Capture On Pin 0 Enable + 20 + 1 + + + COPEN1 + Capture On Pin 1 Enable + 21 + 1 + + + + + CTRLBCLR + Control B Clear + 0x4 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot on Counter + 2 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + UPDATE + Force update of double-buffered register + 3 + + + READSYNC + Force a read synchronization of COUNT + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + CTRLBSET + Control B Set + 0x5 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot on Counter + 2 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + UPDATE + Force update of double-buffered register + 3 + + + READSYNC + Force a read synchronization of COUNT + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + EVCTRL + Event Control + 0x6 + 16 + 0x0000 + + + EVACT + Event Action + 0 + 3 + + EVACTSelect + + OFF + Event action disabled + 0 + + + RETRIGGER + Start, restart or retrigger TC on event + 1 + + + COUNT + Count on event + 2 + + + START + Start TC on event + 3 + + + STAMP + Time stamp capture + 4 + + + PPW + Period catured in CC0, pulse width in CC1 + 5 + + + PWP + Period catured in CC1, pulse width in CC0 + 6 + + + PW + Pulse width capture + 7 + + + + + TCINV + TC Event Input Polarity + 4 + 1 + + + TCEI + TC Event Enable + 5 + 1 + + + OVFEO + Event Output Enable + 8 + 1 + + + MCEO0 + MC Event Output Enable 0 + 12 + 1 + + + MCEO1 + MC Event Output Enable 1 + 13 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x8 + 8 + 0x00 + + + OVF + OVF Interrupt Disable + 0 + 1 + + + ERR + ERR Interrupt Disable + 1 + 1 + + + MC0 + MC Interrupt Disable 0 + 4 + 1 + + + MC1 + MC Interrupt Disable 1 + 5 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x9 + 8 + 0x00 + + + OVF + OVF Interrupt Enable + 0 + 1 + + + ERR + ERR Interrupt Enable + 1 + 1 + + + MC0 + MC Interrupt Enable 0 + 4 + 1 + + + MC1 + MC Interrupt Enable 1 + 5 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0xA + 8 + 0x00 + + + OVF + OVF Interrupt Flag + 0 + 1 + + + ERR + ERR Interrupt Flag + 1 + 1 + + + MC0 + MC Interrupt Flag 0 + 4 + 1 + + + MC1 + MC Interrupt Flag 1 + 5 + 1 + + + + + STATUS + Status + 0xB + 8 + 0x01 + + + STOP + Stop Status Flag + 0 + 1 + + + SLAVE + Slave Status Flag + 1 + 1 + + + PERBUFV + Synchronization Busy Status + 3 + 1 + + + CCBUFV0 + Compare channel buffer 0 valid + 4 + 1 + + + CCBUFV1 + Compare channel buffer 1 valid + 5 + 1 + + + + + WAVE + Waveform Generation Control + 0xC + 8 + 0x00 + + + WAVEGEN + Waveform Generation Mode + 0 + 2 + + WAVEGENSelect + + NFRQ + Normal frequency + 0 + + + MFRQ + Match frequency + 1 + + + NPWM + Normal PWM + 2 + + + MPWM + Match PWM + 3 + + + + + + + DRVCTRL + Control C + 0xD + 8 + 0x00 + + + INVEN0 + Output Waveform Invert Enable 0 + 0 + 1 + + + INVEN1 + Output Waveform Invert Enable 1 + 1 + 1 + + + + + DBGCTRL + Debug Control + 0xF + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + SYNCBUSY + Synchronization Status + 0x10 + 32 + read-only + 0x00000000 + + + SWRST + swrst + 0 + 1 + + + ENABLE + enable + 1 + 1 + + + CTRLB + CTRLB + 2 + 1 + + + STATUS + STATUS + 3 + 1 + + + COUNT + Counter + 4 + 1 + + + PER + Period + 5 + 1 + + + CC0 + Compare Channel 0 + 6 + 1 + + + CC1 + Compare Channel 1 + 7 + 1 + + + + + COUNT + COUNT16 Count + 0x14 + 16 + 0x0000 + + + COUNT + Counter Value + 0 + 16 + + + + + 2 + 2 + CC[%s] + COUNT16 Compare and Capture + 0x1C + 16 + 0x0000 + + + CC + Counter/Compare Value + 0 + 16 + + + + + 2 + 2 + CCBUF[%s] + COUNT16 Compare and Capture Buffer + 0x30 + 16 + 0x0000 + + + CCBUF + Counter/Compare Buffer Value + 0 + 16 + + + + + + COUNT32 + 32-bit Counter Mode + COUNT8 + TcCount32 + 0x0 + + CTRLA + Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Timer Counter Mode + 2 + 2 + + MODESelect + + COUNT16 + Counter in 16-bit mode + 0 + + + COUNT8 + Counter in 8-bit mode + 1 + + + COUNT32 + Counter in 32-bit mode + 2 + + + + + PRESCSYNC + Prescaler and Counter Synchronization + 4 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset the counter on next generic clock + 0 + + + PRESC + Reload or reset the counter on next prescaler clock + 1 + + + RESYNC + Reload or reset the counter on next generic clock and reset the prescaler counter + 2 + + + + + RUNSTDBY + Run during Standby + 6 + 1 + + + ONDEMAND + Clock On Demand + 7 + 1 + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + Prescaler: GCLK_TC + 0 + + + DIV2 + Prescaler: GCLK_TC/2 + 1 + + + DIV4 + Prescaler: GCLK_TC/4 + 2 + + + DIV8 + Prescaler: GCLK_TC/8 + 3 + + + DIV16 + Prescaler: GCLK_TC/16 + 4 + + + DIV64 + Prescaler: GCLK_TC/64 + 5 + + + DIV256 + Prescaler: GCLK_TC/256 + 6 + + + DIV1024 + Prescaler: GCLK_TC/1024 + 7 + + + + + ALOCK + Auto Lock + 11 + 1 + + + CAPTEN0 + Capture Channel 0 Enable + 16 + 1 + + + CAPTEN1 + Capture Channel 1 Enable + 17 + 1 + + + COPEN0 + Capture On Pin 0 Enable + 20 + 1 + + + COPEN1 + Capture On Pin 1 Enable + 21 + 1 + + + + + CTRLBCLR + Control B Clear + 0x4 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot on Counter + 2 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + UPDATE + Force update of double-buffered register + 3 + + + READSYNC + Force a read synchronization of COUNT + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + CTRLBSET + Control B Set + 0x5 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot on Counter + 2 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + UPDATE + Force update of double-buffered register + 3 + + + READSYNC + Force a read synchronization of COUNT + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + EVCTRL + Event Control + 0x6 + 16 + 0x0000 + + + EVACT + Event Action + 0 + 3 + + EVACTSelect + + OFF + Event action disabled + 0 + + + RETRIGGER + Start, restart or retrigger TC on event + 1 + + + COUNT + Count on event + 2 + + + START + Start TC on event + 3 + + + STAMP + Time stamp capture + 4 + + + PPW + Period catured in CC0, pulse width in CC1 + 5 + + + PWP + Period catured in CC1, pulse width in CC0 + 6 + + + PW + Pulse width capture + 7 + + + + + TCINV + TC Event Input Polarity + 4 + 1 + + + TCEI + TC Event Enable + 5 + 1 + + + OVFEO + Event Output Enable + 8 + 1 + + + MCEO0 + MC Event Output Enable 0 + 12 + 1 + + + MCEO1 + MC Event Output Enable 1 + 13 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x8 + 8 + 0x00 + + + OVF + OVF Interrupt Disable + 0 + 1 + + + ERR + ERR Interrupt Disable + 1 + 1 + + + MC0 + MC Interrupt Disable 0 + 4 + 1 + + + MC1 + MC Interrupt Disable 1 + 5 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x9 + 8 + 0x00 + + + OVF + OVF Interrupt Enable + 0 + 1 + + + ERR + ERR Interrupt Enable + 1 + 1 + + + MC0 + MC Interrupt Enable 0 + 4 + 1 + + + MC1 + MC Interrupt Enable 1 + 5 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0xA + 8 + 0x00 + + + OVF + OVF Interrupt Flag + 0 + 1 + + + ERR + ERR Interrupt Flag + 1 + 1 + + + MC0 + MC Interrupt Flag 0 + 4 + 1 + + + MC1 + MC Interrupt Flag 1 + 5 + 1 + + + + + STATUS + Status + 0xB + 8 + 0x01 + + + STOP + Stop Status Flag + 0 + 1 + + + SLAVE + Slave Status Flag + 1 + 1 + + + PERBUFV + Synchronization Busy Status + 3 + 1 + + + CCBUFV0 + Compare channel buffer 0 valid + 4 + 1 + + + CCBUFV1 + Compare channel buffer 1 valid + 5 + 1 + + + + + WAVE + Waveform Generation Control + 0xC + 8 + 0x00 + + + WAVEGEN + Waveform Generation Mode + 0 + 2 + + WAVEGENSelect + + NFRQ + Normal frequency + 0 + + + MFRQ + Match frequency + 1 + + + NPWM + Normal PWM + 2 + + + MPWM + Match PWM + 3 + + + + + + + DRVCTRL + Control C + 0xD + 8 + 0x00 + + + INVEN0 + Output Waveform Invert Enable 0 + 0 + 1 + + + INVEN1 + Output Waveform Invert Enable 1 + 1 + 1 + + + + + DBGCTRL + Debug Control + 0xF + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + SYNCBUSY + Synchronization Status + 0x10 + 32 + read-only + 0x00000000 + + + SWRST + swrst + 0 + 1 + + + ENABLE + enable + 1 + 1 + + + CTRLB + CTRLB + 2 + 1 + + + STATUS + STATUS + 3 + 1 + + + COUNT + Counter + 4 + 1 + + + PER + Period + 5 + 1 + + + CC0 + Compare Channel 0 + 6 + 1 + + + CC1 + Compare Channel 1 + 7 + 1 + + + + + COUNT + COUNT32 Count + 0x14 + 32 + 0x00000000 + + + COUNT + Counter Value + 0 + 32 + + + + + 2 + 4 + CC[%s] + COUNT32 Compare and Capture + 0x1C + 32 + 0x00000000 + + + CC + Counter/Compare Value + 0 + 32 + + + + + 2 + 4 + CCBUF[%s] + COUNT32 Compare and Capture Buffer + 0x30 + 32 + 0x00000000 + + + CCBUF + Counter/Compare Buffer Value + 0 + 32 + + + + + + + + TC1 + 0x42003400 + + TC1 + 21 + + + + TC2 + 0x42003800 + + TC2 + 22 + + + + TC3 + 0x42003C00 + + TC3 + 23 + + + + TC4 + 0x42004000 + + TC4 + 24 + + + + TCC0 + U22133.0.0 + Timer Counter Control + TCC + TCC_ + 0x42002400 + + 0 + 0x80 + registers + + + TCC0 + 17 + + + + CTRLA + Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + RESOLUTION + Enhanced Resolution + 5 + 2 + + RESOLUTIONSelect + + NONE + Dithering is disabled + 0 + + + DITH4 + Dithering is done every 16 PWM frames + 1 + + + DITH5 + Dithering is done every 32 PWM frames + 2 + + + DITH6 + Dithering is done every 64 PWM frames + 3 + + + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + No division + 0 + + + DIV2 + Divide by 2 + 1 + + + DIV4 + Divide by 4 + 2 + + + DIV8 + Divide by 8 + 3 + + + DIV16 + Divide by 16 + 4 + + + DIV64 + Divide by 64 + 5 + + + DIV256 + Divide by 256 + 6 + + + DIV1024 + Divide by 1024 + 7 + + + + + RUNSTDBY + Run in Standby + 11 + 1 + + + PRESCSYNC + Prescaler and Counter Synchronization Selection + 12 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset counter on next GCLK + 0 + + + PRESC + Reload or reset counter on next prescaler clock + 1 + + + RESYNC + Reload or reset counter on next GCLK and reset prescaler counter + 2 + + + + + ALOCK + Auto Lock + 14 + 1 + + + MSYNC + Master Synchronization (only for TCC Slave Instance) + 15 + 1 + + + DMAOS + DMA One-shot Trigger Mode + 23 + 1 + + + CPTEN0 + Capture Channel 0 Enable + 24 + 1 + + + CPTEN1 + Capture Channel 1 Enable + 25 + 1 + + + CPTEN2 + Capture Channel 2 Enable + 26 + 1 + + + CPTEN3 + Capture Channel 3 Enable + 27 + 1 + + + + + CTRLBCLR + Control B Clear + 0x4 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + IDXCMD + Ramp Index Command + 3 + 2 + + IDXCMDSelect + + DISABLE + Command disabled: Index toggles between cycles A and B + 0 + + + SET + Set index: cycle B will be forced in the next cycle + 1 + + + CLEAR + Clear index: cycle A will be forced in the next cycle + 2 + + + HOLD + Hold index: the next cycle will be the same as the current cycle + 3 + + + + + CMD + TCC Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Clear start, restart or retrigger + 1 + + + STOP + Force stop + 2 + + + UPDATE + Force update or double buffered registers + 3 + + + READSYNC + Force COUNT read synchronization + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + CTRLBSET + Control B Set + 0x5 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + IDXCMD + Ramp Index Command + 3 + 2 + + IDXCMDSelect + + DISABLE + Command disabled: Index toggles between cycles A and B + 0 + + + SET + Set index: cycle B will be forced in the next cycle + 1 + + + CLEAR + Clear index: cycle A will be forced in the next cycle + 2 + + + HOLD + Hold index: the next cycle will be the same as the current cycle + 3 + + + + + CMD + TCC Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Clear start, restart or retrigger + 1 + + + STOP + Force stop + 2 + + + UPDATE + Force update or double buffered registers + 3 + + + READSYNC + Force COUNT read synchronization + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + SYNCBUSY + Synchronization Busy + 0x8 + 32 + read-only + 0x00000000 + + + SWRST + Swrst Busy + 0 + 1 + + + ENABLE + Enable Busy + 1 + 1 + + + CTRLB + Ctrlb Busy + 2 + 1 + + + STATUS + Status Busy + 3 + 1 + + + COUNT + Count Busy + 4 + 1 + + + PATT + Pattern Busy + 5 + 1 + + + WAVE + Wave Busy + 6 + 1 + + + PER + Period Busy + 7 + 1 + + + CC0 + Compare Channel 0 Busy + 8 + 1 + + + CC1 + Compare Channel 1 Busy + 9 + 1 + + + CC2 + Compare Channel 2 Busy + 10 + 1 + + + CC3 + Compare Channel 3 Busy + 11 + 1 + + + + + FCTRLA + Recoverable Fault A Configuration + 0xC + 32 + 0x00000000 + + + SRC + Fault A Source + 0 + 2 + + SRCSelect + + DISABLE + Fault input disabled + 0 + + + ENABLE + MCEx (x=0,1) event input + 1 + + + INVERT + Inverted MCEx (x=0,1) event input + 2 + + + ALTFAULT + Alternate fault (A or B) state at the end of the previous period + 3 + + + + + KEEP + Fault A Keeper + 3 + 1 + + + QUAL + Fault A Qualification + 4 + 1 + + + BLANK + Fault A Blanking Mode + 5 + 2 + + BLANKSelect + + START + Blanking applied from start of the ramp + 0 + + + RISE + Blanking applied from rising edge of the output waveform + 1 + + + FALL + Blanking applied from falling edge of the output waveform + 2 + + + BOTH + Blanking applied from each toggle of the output waveform + 3 + + + + + RESTART + Fault A Restart + 7 + 1 + + + HALT + Fault A Halt Mode + 8 + 2 + + HALTSelect + + DISABLE + Halt action disabled + 0 + + + HW + Hardware halt action + 1 + + + SW + Software halt action + 2 + + + NR + Non-recoverable fault + 3 + + + + + CHSEL + Fault A Capture Channel + 10 + 2 + + CHSELSelect + + CC0 + Capture value stored in channel 0 + 0 + + + CC1 + Capture value stored in channel 1 + 1 + + + CC2 + Capture value stored in channel 2 + 2 + + + CC3 + Capture value stored in channel 3 + 3 + + + + + CAPTURE + Fault A Capture Action + 12 + 3 + + CAPTURESelect + + DISABLE + No capture + 0 + + + CAPT + Capture on fault + 1 + + + CAPTMIN + Minimum capture + 2 + + + CAPTMAX + Maximum capture + 3 + + + LOCMIN + Minimum local detection + 4 + + + LOCMAX + Maximum local detection + 5 + + + DERIV0 + Minimum and maximum local detection + 6 + + + CAPTMARK + Capture with ramp index as MSB value + 7 + + + + + BLANKPRESC + Fault A Blanking Prescaler + 15 + 1 + + + BLANKVAL + Fault A Blanking Time + 16 + 8 + + + FILTERVAL + Fault A Filter Value + 24 + 4 + + + + + FCTRLB + Recoverable Fault B Configuration + 0x10 + 32 + 0x00000000 + + + SRC + Fault B Source + 0 + 2 + + SRCSelect + + DISABLE + Fault input disabled + 0 + + + ENABLE + MCEx (x=0,1) event input + 1 + + + INVERT + Inverted MCEx (x=0,1) event input + 2 + + + ALTFAULT + Alternate fault (A or B) state at the end of the previous period + 3 + + + + + KEEP + Fault B Keeper + 3 + 1 + + + QUAL + Fault B Qualification + 4 + 1 + + + BLANK + Fault B Blanking Mode + 5 + 2 + + BLANKSelect + + START + Blanking applied from start of the ramp + 0 + + + RISE + Blanking applied from rising edge of the output waveform + 1 + + + FALL + Blanking applied from falling edge of the output waveform + 2 + + + BOTH + Blanking applied from each toggle of the output waveform + 3 + + + + + RESTART + Fault B Restart + 7 + 1 + + + HALT + Fault B Halt Mode + 8 + 2 + + HALTSelect + + DISABLE + Halt action disabled + 0 + + + HW + Hardware halt action + 1 + + + SW + Software halt action + 2 + + + NR + Non-recoverable fault + 3 + + + + + CHSEL + Fault B Capture Channel + 10 + 2 + + CHSELSelect + + CC0 + Capture value stored in channel 0 + 0 + + + CC1 + Capture value stored in channel 1 + 1 + + + CC2 + Capture value stored in channel 2 + 2 + + + CC3 + Capture value stored in channel 3 + 3 + + + + + CAPTURE + Fault B Capture Action + 12 + 3 + + CAPTURESelect + + DISABLE + No capture + 0 + + + CAPT + Capture on fault + 1 + + + CAPTMIN + Minimum capture + 2 + + + CAPTMAX + Maximum capture + 3 + + + LOCMIN + Minimum local detection + 4 + + + LOCMAX + Maximum local detection + 5 + + + DERIV0 + Minimum and maximum local detection + 6 + + + CAPTMARK + Capture with ramp index as MSB value + 7 + + + + + BLANKPRESC + Fault B Blanking Prescaler + 15 + 1 + + + BLANKVAL + Fault B Blanking Time + 16 + 8 + + + FILTERVAL + Fault B Filter Value + 24 + 4 + + + + + WEXCTRL + Waveform Extension Configuration + 0x14 + 32 + 0x00000000 + + + OTMX + Output Matrix + 0 + 2 + + + DTIEN0 + Dead-time Insertion Generator 0 Enable + 8 + 1 + + + DTIEN1 + Dead-time Insertion Generator 1 Enable + 9 + 1 + + + DTIEN2 + Dead-time Insertion Generator 2 Enable + 10 + 1 + + + DTIEN3 + Dead-time Insertion Generator 3 Enable + 11 + 1 + + + DTLS + Dead-time Low Side Outputs Value + 16 + 8 + + + DTHS + Dead-time High Side Outputs Value + 24 + 8 + + + + + DRVCTRL + Driver Control + 0x18 + 32 + 0x00000000 + + + NRE0 + Non-Recoverable State 0 Output Enable + 0 + 1 + + + NRE1 + Non-Recoverable State 1 Output Enable + 1 + 1 + + + NRE2 + Non-Recoverable State 2 Output Enable + 2 + 1 + + + NRE3 + Non-Recoverable State 3 Output Enable + 3 + 1 + + + NRE4 + Non-Recoverable State 4 Output Enable + 4 + 1 + + + NRE5 + Non-Recoverable State 5 Output Enable + 5 + 1 + + + NRE6 + Non-Recoverable State 6 Output Enable + 6 + 1 + + + NRE7 + Non-Recoverable State 7 Output Enable + 7 + 1 + + + NRV0 + Non-Recoverable State 0 Output Value + 8 + 1 + + + NRV1 + Non-Recoverable State 1 Output Value + 9 + 1 + + + NRV2 + Non-Recoverable State 2 Output Value + 10 + 1 + + + NRV3 + Non-Recoverable State 3 Output Value + 11 + 1 + + + NRV4 + Non-Recoverable State 4 Output Value + 12 + 1 + + + NRV5 + Non-Recoverable State 5 Output Value + 13 + 1 + + + NRV6 + Non-Recoverable State 6 Output Value + 14 + 1 + + + NRV7 + Non-Recoverable State 7 Output Value + 15 + 1 + + + INVEN0 + Output Waveform 0 Inversion + 16 + 1 + + + INVEN1 + Output Waveform 1 Inversion + 17 + 1 + + + INVEN2 + Output Waveform 2 Inversion + 18 + 1 + + + INVEN3 + Output Waveform 3 Inversion + 19 + 1 + + + INVEN4 + Output Waveform 4 Inversion + 20 + 1 + + + INVEN5 + Output Waveform 5 Inversion + 21 + 1 + + + INVEN6 + Output Waveform 6 Inversion + 22 + 1 + + + INVEN7 + Output Waveform 7 Inversion + 23 + 1 + + + FILTERVAL0 + Non-Recoverable Fault Input 0 Filter Value + 24 + 4 + + + FILTERVAL1 + Non-Recoverable Fault Input 1 Filter Value + 28 + 4 + + + + + DBGCTRL + Debug Control + 0x1E + 8 + 0x00 + + + DBGRUN + Debug Running Mode + 0 + 1 + + + FDDBD + Fault Detection on Debug Break Detection + 2 + 1 + + + + + EVCTRL + Event Control + 0x20 + 32 + 0x00000000 + + + EVACT0 + Timer/counter Input Event0 Action + 0 + 3 + + EVACT0Select + + OFF + Event action disabled + 0 + + + RETRIGGER + Start, restart or re-trigger counter on event + 1 + + + COUNTEV + Count on event + 2 + + + START + Start counter on event + 3 + + + INC + Increment counter on event + 4 + + + COUNT + Count on active state of asynchronous event + 5 + + + STAMP + Stamp capture + 6 + + + FAULT + Non-recoverable fault + 7 + + + + + EVACT1 + Timer/counter Input Event1 Action + 3 + 3 + + EVACT1Select + + OFF + Event action disabled + 0 + + + RETRIGGER + Re-trigger counter on event + 1 + + + DIR + Direction control + 2 + + + STOP + Stop counter on event + 3 + + + DEC + Decrement counter on event + 4 + + + PPW + Period capture value in CC0 register, pulse width capture value in CC1 register + 5 + + + PWP + Period capture value in CC1 register, pulse width capture value in CC0 register + 6 + + + FAULT + Non-recoverable fault + 7 + + + + + CNTSEL + Timer/counter Output Event Mode + 6 + 2 + + CNTSELSelect + + START + An interrupt/event is generated when a new counter cycle starts + 0 + + + END + An interrupt/event is generated when a counter cycle ends + 1 + + + BETWEEN + An interrupt/event is generated when a counter cycle ends, except for the first and last cycles + 2 + + + BOUNDARY + An interrupt/event is generated when a new counter cycle starts or a counter cycle ends + 3 + + + + + OVFEO + Overflow/Underflow Output Event Enable + 8 + 1 + + + TRGEO + Retrigger Output Event Enable + 9 + 1 + + + CNTEO + Timer/counter Output Event Enable + 10 + 1 + + + TCINV0 + Inverted Event 0 Input Enable + 12 + 1 + + + TCINV1 + Inverted Event 1 Input Enable + 13 + 1 + + + TCEI0 + Timer/counter Event 0 Input Enable + 14 + 1 + + + TCEI1 + Timer/counter Event 1 Input Enable + 15 + 1 + + + MCEI0 + Match or Capture Channel 0 Event Input Enable + 16 + 1 + + + MCEI1 + Match or Capture Channel 1 Event Input Enable + 17 + 1 + + + MCEI2 + Match or Capture Channel 2 Event Input Enable + 18 + 1 + + + MCEI3 + Match or Capture Channel 3 Event Input Enable + 19 + 1 + + + MCEO0 + Match or Capture Channel 0 Event Output Enable + 24 + 1 + + + MCEO1 + Match or Capture Channel 1 Event Output Enable + 25 + 1 + + + MCEO2 + Match or Capture Channel 2 Event Output Enable + 26 + 1 + + + MCEO3 + Match or Capture Channel 3 Event Output Enable + 27 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x24 + 32 + 0x00000000 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + TRG + Retrigger Interrupt Enable + 1 + 1 + + + CNT + Counter Interrupt Enable + 2 + 1 + + + ERR + Error Interrupt Enable + 3 + 1 + + + UFS + Non-Recoverable Update Fault Interrupt Enable + 10 + 1 + + + DFS + Non-Recoverable Debug Fault Interrupt Enable + 11 + 1 + + + FAULTA + Recoverable Fault A Interrupt Enable + 12 + 1 + + + FAULTB + Recoverable Fault B Interrupt Enable + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 Interrupt Enable + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 Interrupt Enable + 15 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 16 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 17 + 1 + + + MC2 + Match or Capture Channel 2 Interrupt Enable + 18 + 1 + + + MC3 + Match or Capture Channel 3 Interrupt Enable + 19 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x28 + 32 + 0x00000000 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + TRG + Retrigger Interrupt Enable + 1 + 1 + + + CNT + Counter Interrupt Enable + 2 + 1 + + + ERR + Error Interrupt Enable + 3 + 1 + + + UFS + Non-Recoverable Update Fault Interrupt Enable + 10 + 1 + + + DFS + Non-Recoverable Debug Fault Interrupt Enable + 11 + 1 + + + FAULTA + Recoverable Fault A Interrupt Enable + 12 + 1 + + + FAULTB + Recoverable Fault B Interrupt Enable + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 Interrupt Enable + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 Interrupt Enable + 15 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 16 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 17 + 1 + + + MC2 + Match or Capture Channel 2 Interrupt Enable + 18 + 1 + + + MC3 + Match or Capture Channel 3 Interrupt Enable + 19 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x2C + 32 + 0x00000000 + + + OVF + Overflow + 0 + 1 + + + TRG + Retrigger + 1 + 1 + + + CNT + Counter + 2 + 1 + + + ERR + Error + 3 + 1 + + + UFS + Non-Recoverable Update Fault + 10 + 1 + + + DFS + Non-Recoverable Debug Fault + 11 + 1 + + + FAULTA + Recoverable Fault A + 12 + 1 + + + FAULTB + Recoverable Fault B + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 + 15 + 1 + + + MC0 + Match or Capture 0 + 16 + 1 + + + MC1 + Match or Capture 1 + 17 + 1 + + + MC2 + Match or Capture 2 + 18 + 1 + + + MC3 + Match or Capture 3 + 19 + 1 + + + + + STATUS + Status + 0x30 + 32 + 0x00000001 + + + STOP + Stop + 0 + 1 + + + IDX + Ramp + 1 + 1 + + + UFS + Non-recoverable Update Fault State + 2 + 1 + + + DFS + Non-Recoverable Debug Fault State + 3 + 1 + + + SLAVE + Slave + 4 + 1 + + + PATTBUFV + Pattern Buffer Valid + 5 + 1 + + + PERBUFV + Period Buffer Valid + 7 + 1 + + + FAULTAIN + Recoverable Fault A Input + 8 + 1 + + + FAULTBIN + Recoverable Fault B Input + 9 + 1 + + + FAULT0IN + Non-Recoverable Fault0 Input + 10 + 1 + + + FAULT1IN + Non-Recoverable Fault1 Input + 11 + 1 + + + FAULTA + Recoverable Fault A State + 12 + 1 + + + FAULTB + Recoverable Fault B State + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 State + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 State + 15 + 1 + + + CCBUFV0 + Compare Channel 0 Buffer Valid + 16 + 1 + + + CCBUFV1 + Compare Channel 1 Buffer Valid + 17 + 1 + + + CCBUFV2 + Compare Channel 2 Buffer Valid + 18 + 1 + + + CCBUFV3 + Compare Channel 3 Buffer Valid + 19 + 1 + + + CMP0 + Compare Channel 0 Value + 24 + 1 + + + CMP1 + Compare Channel 1 Value + 25 + 1 + + + CMP2 + Compare Channel 2 Value + 26 + 1 + + + CMP3 + Compare Channel 3 Value + 27 + 1 + + + + + COUNT + Count + 0x34 + 32 + 0x00000000 + + + COUNT + Counter Value + 0 + 24 + + + + + COUNT_DITH4_MODE + Count + COUNT + 0x34 + 32 + 0x00000000 + + + COUNT + Counter Value + 4 + 20 + + + + + COUNT_DITH5_MODE + Count + COUNT + 0x34 + 32 + 0x00000000 + + + COUNT + Counter Value + 5 + 19 + + + + + COUNT_DITH6_MODE + Count + COUNT + 0x34 + 32 + 0x00000000 + + + COUNT + Counter Value + 6 + 18 + + + + + PATT + Pattern + 0x38 + 16 + 0x0000 + + + PGE0 + Pattern Generator 0 Output Enable + 0 + 1 + + + PGE1 + Pattern Generator 1 Output Enable + 1 + 1 + + + PGE2 + Pattern Generator 2 Output Enable + 2 + 1 + + + PGE3 + Pattern Generator 3 Output Enable + 3 + 1 + + + PGE4 + Pattern Generator 4 Output Enable + 4 + 1 + + + PGE5 + Pattern Generator 5 Output Enable + 5 + 1 + + + PGE6 + Pattern Generator 6 Output Enable + 6 + 1 + + + PGE7 + Pattern Generator 7 Output Enable + 7 + 1 + + + PGV0 + Pattern Generator 0 Output Value + 8 + 1 + + + PGV1 + Pattern Generator 1 Output Value + 9 + 1 + + + PGV2 + Pattern Generator 2 Output Value + 10 + 1 + + + PGV3 + Pattern Generator 3 Output Value + 11 + 1 + + + PGV4 + Pattern Generator 4 Output Value + 12 + 1 + + + PGV5 + Pattern Generator 5 Output Value + 13 + 1 + + + PGV6 + Pattern Generator 6 Output Value + 14 + 1 + + + PGV7 + Pattern Generator 7 Output Value + 15 + 1 + + + + + WAVE + Waveform Control + 0x3C + 32 + 0x00000000 + + + WAVEGEN + Waveform Generation + 0 + 3 + + WAVEGENSelect + + NFRQ + Normal frequency + 0 + + + MFRQ + Match frequency + 1 + + + NPWM + Normal PWM + 2 + + + DSCRITICAL + Dual-slope critical + 4 + + + DSBOTTOM + Dual-slope with interrupt/event condition when COUNT reaches ZERO + 5 + + + DSBOTH + Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP + 6 + + + DSTOP + Dual-slope with interrupt/event condition when COUNT reaches TOP + 7 + + + + + RAMP + Ramp Mode + 4 + 2 + + RAMPSelect + + RAMP1 + RAMP1 operation + 0 + + + RAMP2A + Alternative RAMP2 operation + 1 + + + RAMP2 + RAMP2 operation + 2 + + + RAMP2C + Critical RAMP2 operation + 3 + + + + + CIPEREN + Circular period Enable + 7 + 1 + + + CICCEN0 + Circular Channel 0 Enable + 8 + 1 + + + CICCEN1 + Circular Channel 1 Enable + 9 + 1 + + + CICCEN2 + Circular Channel 2 Enable + 10 + 1 + + + CICCEN3 + Circular Channel 3 Enable + 11 + 1 + + + POL0 + Channel 0 Polarity + 16 + 1 + + + POL1 + Channel 1 Polarity + 17 + 1 + + + POL2 + Channel 2 Polarity + 18 + 1 + + + POL3 + Channel 3 Polarity + 19 + 1 + + + SWAP0 + Swap DTI Output Pair 0 + 24 + 1 + + + SWAP1 + Swap DTI Output Pair 1 + 25 + 1 + + + SWAP2 + Swap DTI Output Pair 2 + 26 + 1 + + + SWAP3 + Swap DTI Output Pair 3 + 27 + 1 + + + + + PER + Period + 0x40 + 32 + 0xFFFFFFFF + + + PER + Period Value + 0 + 24 + + + + + PER_DITH4_MODE + Period + PER + 0x40 + 32 + 0xFFFFFFFF + + + DITHER + Dithering Cycle Number + 0 + 4 + + + PER + Period Value + 4 + 20 + + + + + PER_DITH5_MODE + Period + PER + 0x40 + 32 + 0xFFFFFFFF + + + DITHER + Dithering Cycle Number + 0 + 5 + + + PER + Period Value + 5 + 19 + + + + + PER_DITH6_MODE + Period + PER + 0x40 + 32 + 0xFFFFFFFF + + + DITHER + Dithering Cycle Number + 0 + 6 + + + PER + Period Value + 6 + 18 + + + + + 4 + 4 + CC[%s] + Compare and Capture + 0x44 + 32 + 0x00000000 + + + CC + Channel Compare/Capture Value + 0 + 24 + + + + + 4 + 4 + CC_DITH4_MODE[%s] + Compare and Capture + CC[%s] + 0x44 + 32 + 0x00000000 + + + DITHER + Dithering Cycle Number + 0 + 4 + + + CC + Channel Compare/Capture Value + 4 + 20 + + + + + 4 + 4 + CC_DITH5_MODE[%s] + Compare and Capture + CC[%s] + 0x44 + 32 + 0x00000000 + + + DITHER + Dithering Cycle Number + 0 + 5 + + + CC + Channel Compare/Capture Value + 5 + 19 + + + + + 4 + 4 + CC_DITH6_MODE[%s] + Compare and Capture + CC[%s] + 0x44 + 32 + 0x00000000 + + + DITHER + Dithering Cycle Number + 0 + 6 + + + CC + Channel Compare/Capture Value + 6 + 18 + + + + + PATTBUF + Pattern Buffer + 0x64 + 16 + 0x0000 + + + PGEB0 + Pattern Generator 0 Output Enable Buffer + 0 + 1 + + + PGEB1 + Pattern Generator 1 Output Enable Buffer + 1 + 1 + + + PGEB2 + Pattern Generator 2 Output Enable Buffer + 2 + 1 + + + PGEB3 + Pattern Generator 3 Output Enable Buffer + 3 + 1 + + + PGEB4 + Pattern Generator 4 Output Enable Buffer + 4 + 1 + + + PGEB5 + Pattern Generator 5 Output Enable Buffer + 5 + 1 + + + PGEB6 + Pattern Generator 6 Output Enable Buffer + 6 + 1 + + + PGEB7 + Pattern Generator 7 Output Enable Buffer + 7 + 1 + + + PGVB0 + Pattern Generator 0 Output Enable + 8 + 1 + + + PGVB1 + Pattern Generator 1 Output Enable + 9 + 1 + + + PGVB2 + Pattern Generator 2 Output Enable + 10 + 1 + + + PGVB3 + Pattern Generator 3 Output Enable + 11 + 1 + + + PGVB4 + Pattern Generator 4 Output Enable + 12 + 1 + + + PGVB5 + Pattern Generator 5 Output Enable + 13 + 1 + + + PGVB6 + Pattern Generator 6 Output Enable + 14 + 1 + + + PGVB7 + Pattern Generator 7 Output Enable + 15 + 1 + + + + + PERBUF + Period Buffer + 0x6C + 32 + 0xFFFFFFFF + + + PERBUF + Period Buffer Value + 0 + 24 + + + + + PERBUF_DITH4_MODE + Period Buffer + PERBUF + 0x6C + 32 + 0xFFFFFFFF + + + DITHERBUF + Dithering Buffer Cycle Number + 0 + 4 + + + PERBUF + Period Buffer Value + 4 + 20 + + + + + PERBUF_DITH5_MODE + Period Buffer + PERBUF + 0x6C + 32 + 0xFFFFFFFF + + + DITHERBUF + Dithering Buffer Cycle Number + 0 + 5 + + + PERBUF + Period Buffer Value + 5 + 19 + + + + + PERBUF_DITH6_MODE + Period Buffer + PERBUF + 0x6C + 32 + 0xFFFFFFFF + + + DITHERBUF + Dithering Buffer Cycle Number + 0 + 6 + + + PERBUF + Period Buffer Value + 6 + 18 + + + + + 4 + 4 + CCBUF[%s] + Compare and Capture Buffer + 0x70 + 32 + 0x00000000 + + + CCBUF + Channel Compare/Capture Buffer Value + 0 + 24 + + + + + 4 + 4 + CCBUF_DITH4_MODE[%s] + Compare and Capture Buffer + CCBUF[%s] + 0x70 + 32 + 0x00000000 + + + CCBUF + Channel Compare/Capture Buffer Value + 0 + 4 + + + DITHERBUF + Dithering Buffer Cycle Number + 4 + 20 + + + + + 4 + 4 + CCBUF_DITH5_MODE[%s] + Compare and Capture Buffer + CCBUF[%s] + 0x70 + 32 + 0x00000000 + + + DITHERBUF + Dithering Buffer Cycle Number + 0 + 5 + + + CCBUF + Channel Compare/Capture Buffer Value + 5 + 19 + + + + + 4 + 4 + CCBUF_DITH6_MODE[%s] + Compare and Capture Buffer + CCBUF[%s] + 0x70 + 32 + 0x00000000 + + + DITHERBUF + Dithering Buffer Cycle Number + 0 + 6 + + + CCBUF + Channel Compare/Capture Buffer Value + 6 + 18 + + + + + + + TCC1 + 0x42002800 + + TCC1 + 18 + + + + TCC2 + 0x42002C00 + + TCC2 + 19 + + + + WDT + U22511.0.1 + Watchdog Timer + WDT + WDT_ + 0x40002000 + + 0 + 0xD + registers + + + WDT + 1 + + + + CTRLA + Control + 0x0 + 8 + 0x00 + + + ENABLE + Enable + 1 + 1 + + + WEN + Watchdog Timer Window Mode Enable + 2 + 1 + + + ALWAYSON + Always-On + 7 + 1 + + + + + CONFIG + Configuration + 0x1 + 8 + 0xBB + + + PER + Time-Out Period + 0 + 4 + + PERSelect + + CYC8 + 8 clock cycles + 0x0 + + + CYC16 + 16 clock cycles + 0x1 + + + CYC32 + 32 clock cycles + 0x2 + + + CYC64 + 64 clock cycles + 0x3 + + + CYC128 + 128 clock cycles + 0x4 + + + CYC256 + 256 clock cycles + 0x5 + + + CYC512 + 512 clock cycles + 0x6 + + + CYC1024 + 1024 clock cycles + 0x7 + + + CYC2048 + 2048 clock cycles + 0x8 + + + CYC4096 + 4096 clock cycles + 0x9 + + + CYC8192 + 8192 clock cycles + 0xA + + + CYC16384 + 16384 clock cycles + 0xB + + + + + WINDOW + Window Mode Time-Out Period + 4 + 4 + + WINDOWSelect + + CYC8 + 8 clock cycles + 0x0 + + + CYC16 + 16 clock cycles + 0x1 + + + CYC32 + 32 clock cycles + 0x2 + + + CYC64 + 64 clock cycles + 0x3 + + + CYC128 + 128 clock cycles + 0x4 + + + CYC256 + 256 clock cycles + 0x5 + + + CYC512 + 512 clock cycles + 0x6 + + + CYC1024 + 1024 clock cycles + 0x7 + + + CYC2048 + 2048 clock cycles + 0x8 + + + CYC4096 + 4096 clock cycles + 0x9 + + + CYC8192 + 8192 clock cycles + 0xA + + + CYC16384 + 16384 clock cycles + 0xB + + + + + + + EWCTRL + Early Warning Interrupt Control + 0x2 + 8 + 0x0B + + + EWOFFSET + Early Warning Interrupt Time Offset + 0 + 4 + + EWOFFSETSelect + + CYC8 + 8 clock cycles + 0x0 + + + CYC16 + 16 clock cycles + 0x1 + + + CYC32 + 32 clock cycles + 0x2 + + + CYC64 + 64 clock cycles + 0x3 + + + CYC128 + 128 clock cycles + 0x4 + + + CYC256 + 256 clock cycles + 0x5 + + + CYC512 + 512 clock cycles + 0x6 + + + CYC1024 + 1024 clock cycles + 0x7 + + + CYC2048 + 2048 clock cycles + 0x8 + + + CYC4096 + 4096 clock cycles + 0x9 + + + CYC8192 + 8192 clock cycles + 0xA + + + CYC16384 + 16384 clock cycles + 0xB + + + + + + + INTENCLR + Interrupt Enable Clear + 0x4 + 8 + 0x00 + + + EW + Early Warning Interrupt Enable + 0 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x5 + 8 + 0x00 + + + EW + Early Warning Interrupt Enable + 0 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x6 + 8 + 0x00 + + + EW + Early Warning + 0 + 1 + + + + + SYNCBUSY + Synchronization Busy + 0x8 + 32 + read-only + 0x00000000 + + + ENABLE + Enable Busy + 1 + 1 + + + WEN + Window Enable Busy + 2 + 1 + + + ALWAYSON + Always-On Busy + 3 + 1 + + + CLEAR + Clear Busy + 4 + 1 + + + + + CLEAR + Clear + 0xC + 8 + write-only + 0x00 + + + CLEAR + Watchdog Clear + 0 + 8 + + CLEARSelect + + KEY + Clear Key + 0xA5 + + + + + + + + + MPU + Memory Protection Unit + MPU + MPU_ + 0xE000ED90 + + 0 + 0x14 + registers + + + + TYPE + MPU Type Register + 0x0 + 32 + read-only + + + SEPARATE + Separate instruction and Data Memory MapsRegions + 0 + 1 + + + DREGION + Number of Data Regions + 8 + 8 + + + IREGION + Number of Instruction Regions + 16 + 8 + + + + + CTRL + MPU Control Register + 0x4 + 32 + + + ENABLE + MPU Enable + 0 + 1 + + + HFNMIENA + Enable Hard Fault and NMI handlers + 1 + 1 + + + PRIVDEFENA + Enables privileged software access to default memory map + 2 + 1 + + + + + RNR + MPU Region Number Register + 0x8 + 32 + + + REGION + Region referenced by RBAR and RASR + 0 + 8 + + + + + RBAR + MPU Region Base Address Register + 0xC + 32 + + + REGION + Region number + 0 + 4 + + + VALID + Region number valid + 4 + 1 + + + ADDR + Region base address + 5 + 27 + + + + + RASR + MPU Region Attribute and Size Register + 0x10 + 32 + + + ENABLE + Region Enable + 0 + 1 + + + SIZE + Region Size + 1 + 5 + + + SRD + Sub-region disable + 8 + 8 + + + B + Bufferable bit + 16 + 1 + + + C + Cacheable bit + 17 + 1 + + + S + Shareable bit + 18 + 1 + + + TEX + TEX bit + 19 + 3 + + + AP + Access Permission + 24 + 3 + + + XN + Execute Never Attribute + 28 + 1 + + + + + + + NVIC + Nested Vectored Interrupt Controller + NVIC + NVIC_ + 0xE000E100 + + 0 + 0x320 + registers + + + + ISER + Interrupt Set Enable Register + 0x0 + 32 + 0x00000000 + + + SETENA + Interrupt set enable bits + 0 + 31 + + + + + ICER + Interrupt Clear Enable Register + 0x80 + 32 + 0x00000000 + + + CLRENA + Interrupt clear-enable bits + 0 + 31 + + + + + ISPR + Interrupt Set Pending Register + 0x100 + 32 + 0x00000000 + + + SETPEND + Interrupt set-pending bits + 0 + 31 + + + + + ICPR + Interrupt Clear Pending Register + 0x180 + 32 + 0x00000000 + + + CLRPEND + Interrupt clear-pending bits + 0 + 31 + + + + + 8 + 4 + IPR[%s] + Interrupt Priority Register n + 0x300 + 32 + 0x00000000 + + + PRI0 + Priority of interrupt n + 0 + 2 + + + PRI1 + Priority of interrupt n + 8 + 2 + + + PRI2 + Priority of interrupt n + 16 + 2 + + + PRI3 + Priority of interrupt n + 24 + 2 + + + + + + + SysTick + System timer + SysTick + SysTick_ + 0xE000E010 + + 0 + 0x10 + registers + + + + CSR + SysTick Control and Status Register + 0x0 + 32 + 0x4 + + + ENABLE + SysTick Counter Enable + 0 + 1 + + ENABLESelect + + VALUE_0 + Counter disabled + 0 + + + VALUE_1 + Counter enabled + 1 + + + + + TICKINT + SysTick Exception Request Enable + 1 + 1 + + TICKINTSelect + + VALUE_0 + Counting down to 0 does not assert the SysTick exception request + 0 + + + VALUE_1 + Counting down to 0 asserts the SysTick exception request + 1 + + + + + CLKSOURCE + Clock Source 0=external, 1=processor + 2 + 1 + + CLKSOURCESelect + + VALUE_0 + External clock + 0 + + + VALUE_1 + Processor clock + 1 + + + + + COUNTFLAG + Timer counted to 0 since last read of register + 16 + 1 + + + + + RVR + SysTick Reload Value Register + 0x4 + 32 + + + RELOAD + Value to load into the SysTick Current Value Register when the counter reaches 0 + 0 + 24 + + + + + CVR + SysTick Current Value Register + 0x8 + 32 + + + CURRENT + Current value at the time the register is accessed + 0 + 24 + + + + + CALIB + SysTick Calibration Value Register + 0xC + 32 + read-only + 0 + + + TENMS + Reload value to use for 10ms timing + 0 + 24 + + + SKEW + TENMS is rounded from non-integer ratio + 30 + 1 + + SKEWSelect + + VALUE_0 + 10ms calibration value is exact + 0 + + + VALUE_1 + 10ms calibration value is inexact, because of the clock frequency + 1 + + + + + NOREF + No Separate Reference Clock + 31 + 1 + + NOREFSelect + + VALUE_0 + The reference clock is provided + 0 + + + VALUE_1 + The reference clock is not provided + 1 + + + + + + + + + SystemControl + System Control Registers + SystemControl + SystemControl_ + 0xE000E000 + + 0 + 0xD34 + registers + + + + CPUID + CPUID Base Register + 0xD00 + 32 + read-only + 0x410CC601 + + + REVISION + Minor revision number + 0 + 4 + + + PARTNO + Processor Part Number, 0xC60=Cortex-M0+ + 4 + 12 + + + ARCHITECTURE + Processor Architecture, 0xC=ARMv6-M + 16 + 4 + + + VARIANT + Major revision number + 20 + 4 + + + IMPLEMENTER + Implementer code, ARM=0x41 + 24 + 8 + + + + + ICSR + Interrupt Control and State Register + 0xD04 + 32 + 0x00000000 + + + VECTACTIVE + Debug: Exception number of currently executing exception, or 0 if thread mode + 0 + 9 + + + VECTPENDING + Exception number of the highest priority pending enabled exception + 12 + 9 + + + ISRPENDING + Debug: NVIC interrupt pending + 22 + 1 + + + ISRPREEMPT + Debug: Pending exception serviced on exit from debug halt + 23 + 1 + + + PENDSTCLR + SysTick exception clear-pending bit + 25 + 1 + + PENDSTCLRSelect + + VALUE_0 + No effect + 0 + + + VALUE_1 + Removes the pending state from the SysTick exception + 1 + + + + + PENDSTSET + SysTick exception set-pending bit + 26 + 1 + + PENDSTSETSelect + + VALUE_0 + Write: no effect; read: SysTick exception is not pending + 0 + + + VALUE_1 + Write: changes SysTick exception state to pending; read: SysTick exception is pending + 1 + + + + + PENDSVCLR + PendSV clear-pending bit + 27 + 1 + + PENDSVCLRSelect + + VALUE_0 + No effect + 0 + + + VALUE_1 + Removes the pending state from the PendSV exception + 1 + + + + + PENDSVSET + PendSV set-pending bit + 28 + 1 + + PENDSVSETSelect + + VALUE_0 + Write: no effect; read: PendSV exception is not pending + 0 + + + VALUE_1 + Write: changes PendSV exception state to pending; read: PendSV exception is pending + 1 + + + + + NMIPENDSET + NMI set-pending bit + 31 + 1 + + NMIPENDSETSelect + + VALUE_0 + Write: no effect; read: NMI exception is not pending + 0 + + + VALUE_1 + Write: changes NMI exception state to pending; read: NMI exception is pending + 1 + + + + + + + VTOR + Vector Table Offset Register + 0xD08 + 32 + 0x00000000 + + + TBLOFF + Vector table base offset + 7 + 25 + + + + + AIRCR + Application Interrupt and Reset Control Register + 0xD0C + 32 + 0x00000000 + + + VECTCLRACTIVE + Debug: Clear state information + 1 + 1 + + + SYSRESETREQ + System Reset Request + 2 + 1 + + SYSRESETREQSelect + + VALUE_0 + No system reset request + 0 + + + VALUE_1 + Asserts a signal to the outer system that requests a reset + 1 + + + + + ENDIANNESS + Data Endianness, 0=little, 1=big + 15 + 1 + + ENDIANNESSSelect + + VALUE_0 + Little-endian + 0 + + + VALUE_1 + Big-endian + 1 + + + + + VECTKEY + Register key (0x05FA) + 16 + 16 + + + + + SCR + System Control Register + 0xD10 + 32 + 0x00000000 + + + SLEEPONEXIT + Sleep-On-Exit when exiting Handler mode + 1 + 1 + + SLEEPONEXITSelect + + VALUE_0 + O not sleep when returning to Thread mode + 0 + + + VALUE_1 + Enter sleep, or deep sleep, on return from an ISR + 1 + + + + + SLEEPDEEP + Uses Deep Sleep as low power mode + 2 + 1 + + SLEEPDEEPSelect + + VALUE_0 + Sleep + 0 + + + VALUE_1 + Deep sleep + 1 + + + + + SEVONPEND + Send Event on Pending bit + 4 + 1 + + SEVONPENDSelect + + VALUE_0 + Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded + 0 + + + VALUE_1 + Enabled events and all interrupts, including disabled interrupts, can wakeup the processor + 1 + + + + + + + CCR + Configuration and Control Register + 0xD14 + 32 + read-only + 0x00000204 + + + UNALIGN_TRP + Unaligned accesses generates a Hard Fault + 3 + 1 + + UNALIGN_TRPSelect + + VALUE_0 + Do not trap unaligned halfword and word accesses + 0 + + + VALUE_1 + Trap unaligned halfword and word accesses + 1 + + + + + STKALIGN + Stack 8-byte aligned on exception entry + 9 + 1 + + STKALIGNSelect + + VALUE_0 + 4-byte aligned + 0 + + + VALUE_1 + 8-byte aligned + 1 + + + + + + + SHPR2 + System Handler Priority Register 2 + 0xD1C + 32 + 0x00000000 + + + PRI_11 + Priority of system handler 11, SVCall + 24 + 8 + + + + + SHPR3 + System Handler Priority Register 3 + 0xD20 + 32 + 0x00000000 + + + PRI_14 + Priority of system handler 14, PendSV + 16 + 8 + + + PRI_15 + Priority of system handler 15, SysTick exception + 24 + 8 + + + + + SHCSR + System Handler Control and State Register + 0xD24 + 32 + 0x00000000 + + + SVCALLPENDED + 15 + 1 + + + + + DFSR + Debug Fault Status Register + 0xD30 + 32 + 0x00000000 + + + HALTED + Halt request debug event active + 0 + 1 + + + BKPT + Breakpoint debug event + 1 + 1 + + + DWTTRAP + DWT debug event + 2 + 1 + + + VCATCH + Vector catch debug event + 3 + 1 + + + EXTERNAL + EDBGRQ debug event + 4 + 1 + + + + + + + diff --git a/svd/ATSAMC20N18A.svd b/svd/ATSAMC20N18A.svd new file mode 100644 index 000000000000..8319e3b2d6f2 --- /dev/null +++ b/svd/ATSAMC20N18A.svd @@ -0,0 +1,22961 @@ + + + + Microchip Technology + MCHP + ATSAMC20N18A + SAMC20 + 0 + Microchip ATSAMC20N18A Microcontroller + + CM0+ + r0p0 + selectable + true + false + 2 + false + + 8 + 32 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + AC + U22451.1.1 + Analog Comparators + AC + AC_ + 0x42005000 + + 0 + 0x24 + registers + + + AC + 27 + + + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + + + CTRLB + Control B + 0x1 + 8 + write-only + 0x00 + + + START0 + Comparator 0 Start Comparison + 0 + 1 + + + START1 + Comparator 1 Start Comparison + 1 + 1 + + + START2 + Comparator 2 Start Comparison + 2 + 1 + + + START3 + Comparator 3 Start Comparison + 3 + 1 + + + + + EVCTRL + Event Control + 0x2 + 16 + 0x0000 + + + COMPEO0 + Comparator 0 Event Output Enable + 0 + 1 + + + COMPEO1 + Comparator 1 Event Output Enable + 1 + 1 + + + COMPEO2 + Comparator 2 Event Output Enable + 2 + 1 + + + COMPEO3 + Comparator 3 Event Output Enable + 3 + 1 + + + WINEO0 + Window 0 Event Output Enable + 4 + 1 + + + WINEO1 + Window 1 Event Output Enable + 5 + 1 + + + COMPEI0 + Comparator 0 Event Input Enable + 8 + 1 + + + COMPEI1 + Comparator 1 Event Input Enable + 9 + 1 + + + COMPEI2 + Comparator 2 Event Input Enable + 10 + 1 + + + COMPEI3 + Comparator 3 Event Input Enable + 11 + 1 + + + INVEI0 + Comparator 0 Input Event Invert Enable + 12 + 1 + + + INVEI1 + Comparator 1 Input Event Invert Enable + 13 + 1 + + + INVEI2 + Comparator 2 Input Event Invert Enable + 14 + 1 + + + INVEI3 + Comparator 3 Input Event Invert Enable + 15 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x4 + 8 + 0x00 + + + COMP0 + Comparator 0 Interrupt Enable + 0 + 1 + + + COMP1 + Comparator 1 Interrupt Enable + 1 + 1 + + + COMP2 + Comparator 2 Interrupt Enable + 2 + 1 + + + COMP3 + Comparator 3 Interrupt Enable + 3 + 1 + + + WIN0 + Window 0 Interrupt Enable + 4 + 1 + + + WIN1 + Window 1 Interrupt Enable + 5 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x5 + 8 + 0x00 + + + COMP0 + Comparator 0 Interrupt Enable + 0 + 1 + + + COMP1 + Comparator 1 Interrupt Enable + 1 + 1 + + + COMP2 + Comparator 2 Interrupt Enable + 2 + 1 + + + COMP3 + Comparator 3 Interrupt Enable + 3 + 1 + + + WIN0 + Window 0 Interrupt Enable + 4 + 1 + + + WIN1 + Window 1 Interrupt Enable + 5 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x6 + 8 + 0x00 + + + COMP0 + Comparator 0 + 0 + 1 + + + COMP1 + Comparator 1 + 1 + 1 + + + COMP2 + Comparator 2 + 2 + 1 + + + COMP3 + Comparator 3 + 3 + 1 + + + WIN0 + Window 0 + 4 + 1 + + + WIN1 + Window 1 + 5 + 1 + + + + + STATUSA + Status A + 0x7 + 8 + read-only + 0x00 + + + STATE0 + Comparator 0 Current State + 0 + 1 + + + STATE1 + Comparator 1 Current State + 1 + 1 + + + STATE2 + Comparator 2 Current State + 2 + 1 + + + STATE3 + Comparator 3 Current State + 3 + 1 + + + WSTATE0 + Window 0 Current State + 4 + 2 + + WSTATE0Select + + ABOVE + Signal is above window + 0 + + + INSIDE + Signal is inside window + 1 + + + BELOW + Signal is below window + 2 + + + + + WSTATE1 + Window 1 Current State + 6 + 2 + + WSTATE1Select + + ABOVE + Signal is above window + 0 + + + INSIDE + Signal is inside window + 1 + + + BELOW + Signal is below window + 2 + + + + + + + STATUSB + Status B + 0x8 + 8 + read-only + 0x00 + + + READY0 + Comparator 0 Ready + 0 + 1 + + + READY1 + Comparator 1 Ready + 1 + 1 + + + READY2 + Comparator 2 Ready + 2 + 1 + + + READY3 + Comparator 3 Ready + 3 + 1 + + + + + DBGCTRL + Debug Control + 0x9 + 8 + 0x00 + + + DBGRUN + Debug Run + 0 + 1 + + + + + WINCTRL + Window Control + 0xA + 8 + 0x00 + + + WEN0 + Window 0 Mode Enable + 0 + 1 + + + WINTSEL0 + Window 0 Interrupt Selection + 1 + 2 + + WINTSEL0Select + + ABOVE + Interrupt on signal above window + 0 + + + INSIDE + Interrupt on signal inside window + 1 + + + BELOW + Interrupt on signal below window + 2 + + + OUTSIDE + Interrupt on signal outside window + 3 + + + + + WEN1 + Window 1 Mode Enable + 4 + 1 + + + WINTSEL1 + Window 1 Interrupt Selection + 5 + 2 + + WINTSEL1Select + + ABOVE + Interrupt on signal above window + 0 + + + INSIDE + Interrupt on signal inside window + 1 + + + BELOW + Interrupt on signal below window + 2 + + + OUTSIDE + Interrupt on signal outside window + 3 + + + + + + + 4 + 1 + SCALER[%s] + Scaler n + 0xC + 8 + 0x00 + + + VALUE + Scaler Value + 0 + 6 + + + + + 4 + 4 + COMPCTRL[%s] + Comparator Control n + 0x10 + 32 + 0x00000000 + + + ENABLE + Enable + 1 + 1 + + + SINGLE + Single-Shot Mode + 2 + 1 + + + INTSEL + Interrupt Selection + 3 + 2 + + INTSELSelect + + TOGGLE + Interrupt on comparator output toggle + 0 + + + RISING + Interrupt on comparator output rising + 1 + + + FALLING + Interrupt on comparator output falling + 2 + + + EOC + Interrupt on end of comparison (single-shot mode only) + 3 + + + + + RUNSTDBY + Run in Standby + 6 + 1 + + + MUXNEG + Negative Input Mux Selection + 8 + 3 + + MUXNEGSelect + + PIN0 + I/O pin 0 + 0 + + + PIN1 + I/O pin 1 + 1 + + + PIN2 + I/O pin 2 + 2 + + + PIN3 + I/O pin 3 + 3 + + + GND + Ground + 4 + + + VSCALE + VDD scaler + 5 + + + BANDGAP + Internal bandgap voltage + 6 + + + + + MUXPOS + Positive Input Mux Selection + 12 + 3 + + MUXPOSSelect + + PIN0 + I/O pin 0 + 0 + + + PIN1 + I/O pin 1 + 1 + + + PIN2 + I/O pin 2 + 2 + + + PIN3 + I/O pin 3 + 3 + + + VSCALE + VDD Scaler + 4 + + + + + SWAP + Swap Inputs and Invert + 15 + 1 + + + SPEED + Speed Selection + 16 + 2 + + SPEEDSelect + + LOW + Low speed + 0 + + + HIGH + High speed + 3 + + + + + HYSTEN + Hysteresis Enable + 19 + 1 + + + FLEN + Filter Length + 24 + 3 + + FLENSelect + + OFF + No filtering + 0 + + + MAJ3 + 3-bit majority function (2 of 3) + 1 + + + MAJ5 + 5-bit majority function (3 of 5) + 2 + + + + + OUT + Output + 28 + 2 + + OUTSelect + + OFF + The output of COMPn is not routed to the COMPn I/O port + 0 + + + ASYNC + The asynchronous output of COMPn is routed to the COMPn I/O port + 1 + + + SYNC + The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port + 2 + + + + + + + SYNCBUSY + Synchronization Busy + 0x20 + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + Enable Synchronization Busy + 1 + 1 + + + WINCTRL + WINCTRL Synchronization Busy + 2 + 1 + + + COMPCTRL0 + COMPCTRL 0 Synchronization Busy + 3 + 1 + + + COMPCTRL1 + COMPCTRL 1 Synchronization Busy + 4 + 1 + + + COMPCTRL2 + COMPCTRL 2 Synchronization Busy + 5 + 1 + + + COMPCTRL3 + COMPCTRL 3 Synchronization Busy + 6 + 1 + + + + + + + ADC0 + U22472.3.0 + Analog Digital Converter + ADC + ADC_ + 0x42004400 + + 0 + 0x2E + registers + + + ADC0 + 25 + + + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + SLAVEEN + Slave Enable + 5 + 1 + + + RUNSTDBY + Run During Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + + + CTRLB + Control B + 0x1 + 8 + 0x00 + + + PRESCALER + Prescaler Configuration + 0 + 3 + + PRESCALERSelect + + DIV2 + Peripheral clock divided by 2 + 0x0 + + + DIV4 + Peripheral clock divided by 4 + 0x1 + + + DIV8 + Peripheral clock divided by 8 + 0x2 + + + DIV16 + Peripheral clock divided by 16 + 0x3 + + + DIV32 + Peripheral clock divided by 32 + 0x4 + + + DIV64 + Peripheral clock divided by 64 + 0x5 + + + DIV128 + Peripheral clock divided by 128 + 0x6 + + + DIV256 + Peripheral clock divided by 256 + 0x7 + + + + + + + REFCTRL + Reference Control + 0x2 + 8 + 0x00 + + + REFSEL + Reference Selection + 0 + 4 + + REFSELSelect + + INTREF + Internal Bandgap Reference + 0x0 + + + INTVCC0 + 1/1.6 VDDANA + 0x1 + + + INTVCC1 + 1/2 VDDANA + 0x2 + + + AREFA + External Reference + 0x3 + + + INTVCC2 + VDDANA + 0x5 + + + + + REFCOMP + Reference Buffer Offset Compensation Enable + 7 + 1 + + + + + EVCTRL + Event Control + 0x3 + 8 + 0x00 + + + FLUSHEI + Flush Event Input Enable + 0 + 1 + + + STARTEI + Start Conversion Event Input Enable + 1 + 1 + + + FLUSHINV + Flush Event Invert Enable + 2 + 1 + + + STARTINV + Start Event Invert Enable + 3 + 1 + + + RESRDYEO + Result Ready Event Out + 4 + 1 + + + WINMONEO + Window Monitor Event Out + 5 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x4 + 8 + 0x00 + + + RESRDY + Result Ready Interrupt Disable + 0 + 1 + + + OVERRUN + Overrun Interrupt Disable + 1 + 1 + + + WINMON + Window Monitor Interrupt Disable + 2 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x5 + 8 + 0x00 + + + RESRDY + Result Ready Interrupt Enable + 0 + 1 + + + OVERRUN + Overrun Interrupt Enable + 1 + 1 + + + WINMON + Window Monitor Interrupt Enable + 2 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x6 + 8 + 0x00 + + + RESRDY + Result Ready Interrupt Flag + 0 + 1 + + + OVERRUN + Overrun Interrupt Flag + 1 + 1 + + + WINMON + Window Monitor Interrupt Flag + 2 + 1 + + + + + SEQSTATUS + Sequence Status + 0x7 + 8 + read-only + 0x00 + + + SEQSTATE + Sequence State + 0 + 5 + + + SEQBUSY + Sequence Busy + 7 + 1 + + + + + INPUTCTRL + Input Control + 0x8 + 16 + 0x0000 + + + MUXPOS + Positive Mux Input Selection + 0 + 5 + + MUXPOSSelect + + AIN0 + ADC AIN0 Pin + 0x0 + + + AIN1 + ADC AIN1 Pin + 0x1 + + + AIN2 + ADC AIN2 Pin + 0x2 + + + AIN3 + ADC AIN3 Pin + 0x3 + + + AIN4 + ADC AIN4 Pin + 0x4 + + + AIN5 + ADC AIN5 Pin + 0x5 + + + AIN6 + ADC AIN6 Pin + 0x6 + + + AIN7 + ADC AIN7 Pin + 0x7 + + + AIN8 + ADC AIN8 Pin + 0x8 + + + AIN9 + ADC AIN9 Pin + 0x9 + + + AIN10 + ADC AIN10 Pin + 0xA + + + AIN11 + ADC AIN11 Pin + 0xB + + + TEMP + Temperature Sensor + 0x18 + + + BANDGAP + Bandgap Voltage + 0x19 + + + SCALEDCOREVCC + 1/4 Scaled Core Supply + 0x1A + + + SCALEDIOVCC + 1/4 Scaled I/O Supply + 0x1B + + + + + MUXNEG + Negative Mux Input Selection + 8 + 5 + + MUXNEGSelect + + AIN0 + ADC AIN0 Pin + 0x0 + + + AIN1 + ADC AIN1 Pin + 0x1 + + + AIN2 + ADC AIN2 Pin + 0x2 + + + AIN3 + ADC AIN3 Pin + 0x3 + + + AIN4 + ADC AIN4 Pin + 0x4 + + + AIN5 + ADC AIN5 Pin + 0x5 + + + GND + Internal Ground + 0x18 + + + + + + + CTRLC + Control C + 0xA + 16 + 0x0000 + + + DIFFMODE + Differential Mode + 0 + 1 + + + LEFTADJ + Left-Adjusted Result + 1 + 1 + + + FREERUN + Free Running Mode + 2 + 1 + + + CORREN + Digital Correction Logic Enable + 3 + 1 + + + RESSEL + Conversion Result Resolution + 4 + 2 + + RESSELSelect + + 12BIT + 12-bit + 0x0 + + + 16BIT + 16-bit averaging mode + 0x1 + + + 10BIT + 10-bit + 0x2 + + + 8BIT + 8-bit + 0x3 + + + + + R2R + Rail-to-Rail mode enable + 7 + 1 + + + WINMODE + Window Monitor Mode + 8 + 3 + + WINMODESelect + + DISABLE + No window mode (default) + 0 + + + MODE1 + RESULT > WINLT + 1 + + + MODE2 + RESULT < WINUT + 2 + + + MODE3 + WINLT < RESULT < WINUT + 3 + + + MODE4 + !(WINLT < RESULT < WINUT) + 4 + + + + + + + AVGCTRL + Average Control + 0xC + 8 + 0x00 + + + SAMPLENUM + Number of Samples to be Collected + 0 + 4 + + SAMPLENUMSelect + + 1 + 1 sample + 0x0 + + + 2 + 2 samples + 0x1 + + + 4 + 4 samples + 0x2 + + + 8 + 8 samples + 0x3 + + + 16 + 16 samples + 0x4 + + + 32 + 32 samples + 0x5 + + + 64 + 64 samples + 0x6 + + + 128 + 128 samples + 0x7 + + + 256 + 256 samples + 0x8 + + + 512 + 512 samples + 0x9 + + + 1024 + 1024 samples + 0xA + + + + + ADJRES + Adjusting Result / Division Coefficient + 4 + 3 + + + + + SAMPCTRL + Sample Time Control + 0xD + 8 + 0x00 + + + SAMPLEN + Sampling Time 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+ + + + + + + EIC + U22543.0.0 + External Interrupt Controller + EIC + EIC_ + 0x40002800 + + 0 + 0x3C + registers + + + EIC + 3 + + + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + CKSEL + Clock Selection + 4 + 1 + + CKSELSelect + + CLK_GCLK + Clocked by GCLK + 0 + + + CLK_ULP32K + Clocked by ULP32K + 1 + + + + + + + NMICTRL + Non-Maskable Interrupt Control + 0x1 + 8 + 0x00 + + + NMISENSE + Non-Maskable Interrupt Sense Configuration + 0 + 3 + + NMISENSESelect + + NONE + No detection + 0 + + + RISE + Rising-edge detection + 1 + + + FALL + Falling-edge detection + 2 + + + BOTH + Both-edges detection + 3 + + + HIGH + High-level detection + 4 + + + LOW + Low-level detection + 5 + + + + + NMIFILTEN + Non-Maskable Interrupt Filter Enable + 3 + 1 + + + NMIASYNCH + Asynchronous Edge Detection Mode + 4 + 1 + + NMIASYNCHSelect + + SYNC + Edge detection is clock synchronously operated + 0 + + + ASYNC + Edge detection is clock asynchronously operated + 1 + + + + + + + NMIFLAG + Non-Maskable Interrupt Flag Status and Clear + 0x2 + 16 + 0x0000 + + + NMI + Non-Maskable Interrupt + 0 + 1 + + + + + SYNCBUSY + Synchronization Busy + 0x4 + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy Status + 0 + 1 + + + ENABLE + Enable Synchronization Busy Status + 1 + 1 + + + + + EVCTRL + Event Control + 0x8 + 32 + 0x00000000 + + + EXTINTEO + External Interrupt Event Output Enable + 0 + 16 + + + + + INTENCLR + Interrupt Enable Clear + 0xC + 32 + 0x00000000 + + + EXTINT + External Interrupt Enable + 0 + 16 + + + + + INTENSET + Interrupt Enable Set + 0x10 + 32 + 0x00000000 + + + EXTINT + External Interrupt Enable + 0 + 16 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x14 + 32 + 0x00000000 + + + EXTINT + External Interrupt + 0 + 16 + + + + + ASYNCH + External Interrupt Asynchronous Mode + 0x18 + 32 + 0x00000000 + + + ASYNCH + Asynchronous Edge Detection Mode + 0 + 16 + + ASYNCHSelect + + SYNC + Edge detection is clock synchronously operated + 0 + + + ASYNC + Edge detection is clock asynchronously operated + 1 + + + + + + + 2 + 4 + CONFIG[%s] + External Interrupt Sense Configuration + 0x1C + 32 + 0x00000000 + + + SENSE0 + Input Sense Configuration 0 + 0 + 3 + + SENSE0Select + + NONE + No detection + 0 + + + RISE + Rising edge detection + 1 + + + FALL + Falling edge detection + 2 + + + BOTH + Both edges detection + 3 + + + HIGH + High level detection + 4 + + + LOW + Low level detection + 5 + + + + + FILTEN0 + Filter Enable 0 + 3 + 1 + + + SENSE1 + Input Sense Configuration 1 + 4 + 3 + + SENSE1Select + + NONE + No detection + 0 + + + RISE + Rising edge detection + 1 + + + FALL + Falling edge detection + 2 + + + BOTH + Both edges detection + 3 + + + HIGH + High level detection + 4 + + + LOW + Low level detection + 5 + + + + + FILTEN1 + Filter Enable 1 + 7 + 1 + + + SENSE2 + Input Sense Configuration 2 + 8 + 3 + + SENSE2Select + + NONE + No detection + 0 + + + RISE + Rising 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edge detection + 1 + + + FALL + Falling edge detection + 2 + + + BOTH + Both edges detection + 3 + + + HIGH + High level detection + 4 + + + LOW + Low level detection + 5 + + + + + FILTEN5 + Filter Enable 5 + 23 + 1 + + + SENSE6 + Input Sense Configuration 6 + 24 + 3 + + SENSE6Select + + NONE + No detection + 0 + + + RISE + Rising edge detection + 1 + + + FALL + Falling edge detection + 2 + + + BOTH + Both edges detection + 3 + + + HIGH + High level detection + 4 + + + LOW + Low level detection + 5 + + + + + FILTEN6 + Filter Enable 6 + 27 + 1 + + + SENSE7 + Input Sense Configuration 7 + 28 + 3 + + SENSE7Select + + NONE + No detection + 0 + + + RISE + Rising edge detection + 1 + + + FALL + Falling edge detection + 2 + + + BOTH + Both edges detection + 3 + + + HIGH + High level detection + 4 + + + LOW + Low level detection + 5 + + + + + FILTEN7 + Filter Enable 7 + 31 + 1 + + + + + DEBOUNCEN + Debouncer Enable + 0x30 + 32 + 0x00000000 + + + DEBOUNCEN + Debouncer Enable + 0 + 16 + + + + + DPRESCALER + Debouncer Prescaler + 0x34 + 32 + 0x00000000 + + + PRESCALER0 + Debouncer Prescaler + 0 + 3 + + PRESCALER0Select + + DIV2 + EIC clock divided by 2 + 0 + + + DIV4 + EIC clock divided by 4 + 1 + + + DIV8 + EIC clock divided by 8 + 2 + + + DIV16 + EIC clock divided by 16 + 3 + + + DIV32 + EIC clock divided by 32 + 4 + + + DIV64 + EIC clock divided by 64 + 5 + + + DIV128 + EIC clock divided by 128 + 6 + + + DIV256 + EIC clock divided by 256 + 7 + + + + + STATES0 + Debouncer number of states + 3 + 1 + + STATES0Select + + LFREQ3 + 3 low frequency samples + 0 + + + LFREQ7 + 7 low frequency samples + 1 + + + + + PRESCALER1 + Debouncer Prescaler + 4 + 3 + + PRESCALER1Select + + DIV2 + EIC clock divided by 2 + 0 + + + DIV4 + EIC clock divided by 4 + 1 + + + DIV8 + EIC clock divided by 8 + 2 + + + DIV16 + EIC clock divided by 16 + 3 + + + DIV32 + EIC clock divided by 32 + 4 + + + DIV64 + EIC clock divided by 64 + 5 + + + DIV128 + EIC clock divided by 128 + 6 + + + DIV256 + EIC clock divided by 256 + 7 + + + + + STATES1 + Debouncer number of states + 7 + 1 + + STATES1Select + + LFREQ3 + 3 low frequency samples + 0 + + + LFREQ7 + 7 low frequency samples + 1 + + + + + TICKON + Pin Sampler frequency selection + 16 + 1 + + TICKONSelect + + CLK_GCLK_EIC + Clocked by GCLK + 0 + + + CLK_LFREQ + Clocked by Low Frequency Clock + 1 + + + + + + + PINSTATE + Pin State + 0x38 + 32 + read-only + 0x00000000 + + + PINSTATE + Pin State + 0 + 16 + + + + + + + EVSYS + U22561.1.0 + Event System Interface + EVSYS + EVSYS_ + 0x42000000 + + 0 + 0x1C0 + registers + + + EVSYS + 8 + + + + CTRLA + Control + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + + + CHSTATUS + Channel Status + 0xC + 32 + read-only + 0x00000000 + + + USRRDY0 + Channel 0 User Ready + 0 + 1 + + + USRRDY1 + Channel 1 User Ready + 1 + 1 + + + USRRDY2 + Channel 2 User Ready + 2 + 1 + + + USRRDY3 + Channel 3 User Ready + 3 + 1 + + + USRRDY4 + Channel 4 User Ready + 4 + 1 + + + USRRDY5 + Channel 5 User Ready + 5 + 1 + + + USRRDY6 + Channel 6 User Ready + 6 + 1 + + + USRRDY7 + Channel 7 User Ready + 7 + 1 + + + USRRDY8 + Channel 8 User Ready + 8 + 1 + + + USRRDY9 + Channel 9 User Ready + 9 + 1 + + + USRRDY10 + Channel 10 User Ready + 10 + 1 + + + USRRDY11 + Channel 11 User Ready + 11 + 1 + + + CHBUSY0 + Channel 0 Busy + 16 + 1 + + + CHBUSY1 + Channel 1 Busy + 17 + 1 + + + CHBUSY2 + Channel 2 Busy + 18 + 1 + + + CHBUSY3 + Channel 3 Busy + 19 + 1 + + + CHBUSY4 + Channel 4 Busy + 20 + 1 + + + CHBUSY5 + Channel 5 Busy + 21 + 1 + + + CHBUSY6 + Channel 6 Busy + 22 + 1 + + + CHBUSY7 + Channel 7 Busy + 23 + 1 + + + CHBUSY8 + Channel 8 Busy + 24 + 1 + + + CHBUSY9 + Channel 9 Busy + 25 + 1 + + + CHBUSY10 + Channel 10 Busy + 26 + 1 + + + CHBUSY11 + Channel 11 Busy + 27 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x10 + 32 + 0x00000000 + + + OVR0 + Channel 0 Overrun Interrupt Enable + 0 + 1 + + + OVR1 + Channel 1 Overrun Interrupt Enable + 1 + 1 + + + OVR2 + Channel 2 Overrun Interrupt Enable + 2 + 1 + + + OVR3 + Channel 3 Overrun Interrupt Enable + 3 + 1 + + + OVR4 + Channel 4 Overrun Interrupt Enable + 4 + 1 + + + OVR5 + Channel 5 Overrun Interrupt Enable + 5 + 1 + + + OVR6 + Channel 6 Overrun Interrupt Enable + 6 + 1 + + + OVR7 + Channel 7 Overrun Interrupt Enable + 7 + 1 + + + OVR8 + Channel 8 Overrun Interrupt Enable + 8 + 1 + + + OVR9 + Channel 9 Overrun Interrupt Enable + 9 + 1 + + + OVR10 + Channel 10 Overrun Interrupt Enable + 10 + 1 + + + OVR11 + Channel 11 Overrun Interrupt Enable + 11 + 1 + + + EVD0 + Channel 0 Event Detection Interrupt Enable + 16 + 1 + + + EVD1 + Channel 1 Event Detection Interrupt Enable + 17 + 1 + + + EVD2 + Channel 2 Event Detection Interrupt Enable + 18 + 1 + + + EVD3 + Channel 3 Event Detection Interrupt Enable + 19 + 1 + + + EVD4 + Channel 4 Event Detection Interrupt Enable + 20 + 1 + + + EVD5 + Channel 5 Event Detection Interrupt Enable + 21 + 1 + + + EVD6 + Channel 6 Event Detection Interrupt Enable + 22 + 1 + + + EVD7 + Channel 7 Event Detection Interrupt Enable + 23 + 1 + + + EVD8 + Channel 8 Event Detection Interrupt Enable + 24 + 1 + + + EVD9 + Channel 9 Event Detection Interrupt Enable + 25 + 1 + + + EVD10 + Channel 10 Event Detection Interrupt Enable + 26 + 1 + + + EVD11 + Channel 11 Event Detection Interrupt Enable + 27 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x14 + 32 + 0x00000000 + + + OVR0 + Channel 0 Overrun Interrupt Enable + 0 + 1 + + + OVR1 + Channel 1 Overrun Interrupt Enable + 1 + 1 + + + OVR2 + Channel 2 Overrun Interrupt Enable + 2 + 1 + + + OVR3 + Channel 3 Overrun Interrupt Enable + 3 + 1 + + + OVR4 + Channel 4 Overrun Interrupt Enable + 4 + 1 + + + OVR5 + Channel 5 Overrun Interrupt Enable + 5 + 1 + + + OVR6 + Channel 6 Overrun Interrupt Enable + 6 + 1 + + + OVR7 + Channel 7 Overrun Interrupt Enable + 7 + 1 + + + OVR8 + Channel 8 Overrun Interrupt Enable + 8 + 1 + + + OVR9 + Channel 9 Overrun Interrupt Enable + 9 + 1 + + + OVR10 + Channel 10 Overrun Interrupt Enable + 10 + 1 + + + OVR11 + Channel 11 Overrun Interrupt Enable + 11 + 1 + + + EVD0 + Channel 0 Event Detection Interrupt Enable + 16 + 1 + + + EVD1 + Channel 1 Event Detection Interrupt Enable + 17 + 1 + + + EVD2 + Channel 2 Event Detection Interrupt Enable + 18 + 1 + + + EVD3 + Channel 3 Event Detection Interrupt Enable + 19 + 1 + + + EVD4 + Channel 4 Event Detection Interrupt Enable + 20 + 1 + + + EVD5 + Channel 5 Event Detection Interrupt Enable + 21 + 1 + + + EVD6 + Channel 6 Event Detection Interrupt Enable + 22 + 1 + + + EVD7 + Channel 7 Event Detection Interrupt Enable + 23 + 1 + + + EVD8 + Channel 8 Event Detection Interrupt Enable + 24 + 1 + + + EVD9 + Channel 9 Event Detection Interrupt Enable + 25 + 1 + + + EVD10 + Channel 10 Event Detection Interrupt Enable + 26 + 1 + + + EVD11 + Channel 11 Event Detection Interrupt Enable + 27 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x18 + 32 + 0x00000000 + + + OVR0 + Channel 0 Overrun + 0 + 1 + + + OVR1 + Channel 1 Overrun + 1 + 1 + + + OVR2 + Channel 2 Overrun + 2 + 1 + + + OVR3 + Channel 3 Overrun + 3 + 1 + + + OVR4 + Channel 4 Overrun + 4 + 1 + + + OVR5 + Channel 5 Overrun + 5 + 1 + + + OVR6 + Channel 6 Overrun + 6 + 1 + + + OVR7 + Channel 7 Overrun + 7 + 1 + + + OVR8 + Channel 8 Overrun + 8 + 1 + + + OVR9 + Channel 9 Overrun + 9 + 1 + + + OVR10 + Channel 10 Overrun + 10 + 1 + + + OVR11 + Channel 11 Overrun + 11 + 1 + + + EVD0 + Channel 0 Event Detection + 16 + 1 + + + EVD1 + Channel 1 Event Detection + 17 + 1 + + + EVD2 + Channel 2 Event Detection + 18 + 1 + + + EVD3 + Channel 3 Event Detection + 19 + 1 + + + EVD4 + Channel 4 Event Detection + 20 + 1 + + + EVD5 + Channel 5 Event Detection + 21 + 1 + + + EVD6 + Channel 6 Event Detection + 22 + 1 + + + EVD7 + Channel 7 Event Detection + 23 + 1 + + + EVD8 + Channel 8 Event Detection + 24 + 1 + + + EVD9 + Channel 9 Event Detection + 25 + 1 + + + EVD10 + Channel 10 Event Detection + 26 + 1 + + + EVD11 + Channel 11 Event Detection + 27 + 1 + + + + + SWEVT + Software Event + 0x1C + 32 + write-only + 0x00000000 + + + CHANNEL0 + Channel 0 Software Selection + 0 + 1 + + + CHANNEL1 + Channel 1 Software Selection + 1 + 1 + + + CHANNEL2 + Channel 2 Software Selection + 2 + 1 + + + CHANNEL3 + Channel 3 Software Selection + 3 + 1 + + + CHANNEL4 + Channel 4 Software Selection + 4 + 1 + + + CHANNEL5 + Channel 5 Software Selection + 5 + 1 + + + CHANNEL6 + Channel 6 Software Selection + 6 + 1 + + + CHANNEL7 + Channel 7 Software Selection + 7 + 1 + + + CHANNEL8 + Channel 8 Software Selection + 8 + 1 + + + CHANNEL9 + Channel 9 Software Selection + 9 + 1 + + + CHANNEL10 + Channel 10 Software Selection + 10 + 1 + + + CHANNEL11 + Channel 11 Software Selection + 11 + 1 + + + + + 12 + 4 + CHANNEL[%s] + Channel n + 0x20 + 32 + 0x00008000 + + + EVGEN + Event Generator Selection + 0 + 7 + + + PATH + Path Selection + 8 + 2 + + PATHSelect + + SYNCHRONOUS + Synchronous path + 0 + + + RESYNCHRONIZED + Resynchronized path + 1 + + + ASYNCHRONOUS + Asynchronous path + 2 + + + + + EDGSEL + Edge Detection Selection + 10 + 2 + + EDGSELSelect + + NO_EVT_OUTPUT + No event output when using the resynchronized or synchronous path + 0 + + + RISING_EDGE + Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path + 1 + + + FALLING_EDGE + Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path + 2 + + + BOTH_EDGES + Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path + 3 + + + + + RUNSTDBY + Run in standby + 14 + 1 + + + ONDEMAND + Generic Clock On Demand + 15 + 1 + + + + + 50 + 4 + USER[%s] + User Multiplexer n + 0x80 + 32 + 0x00000000 + + + CHANNEL + Channel Event Selection + 0 + 5 + + + + + + + FREQM + U22572.0.0 + Frequency Meter + FREQM + FREQM_ + 0x40002C00 + + 0 + 0x14 + registers + + + FREQM + 4 + + + + CTRLA + Control A Register + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + + + CTRLB + Control B Register + 0x1 + 8 + write-only + 0x00 + + + START + Start Measurement + 0 + 1 + + + + + CFGA + Config A register + 0x2 + 16 + 0x0000 + + + REFNUM + Number of Reference Clock Cycles + 0 + 8 + + + DIVREF + Divide Reference Clock + 15 + 1 + + + + + INTENCLR + Interrupt Enable Clear Register + 0x8 + 8 + 0x00 + + + DONE + Measurement Done Interrupt Enable + 0 + 1 + + + + + INTENSET + Interrupt Enable Set Register + 0x9 + 8 + 0x00 + + + DONE + Measurement Done Interrupt Enable + 0 + 1 + + + + + INTFLAG + Interrupt Flag Register + 0xA + 8 + 0x00 + + + DONE + Measurement Done + 0 + 1 + + + + + STATUS + Status Register + 0xB + 8 + 0x00 + + + BUSY + FREQM Status + 0 + 1 + + + OVF + Sticky Count Value Overflow + 1 + 1 + + + + + SYNCBUSY + Synchronization Busy Register + 0xC + 32 + read-only + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + + + VALUE + Count Value Register + 0x10 + 32 + read-only + 0x00000000 + + + VALUE + Measurement Value + 0 + 24 + + + + + + + GCLK + U21221.1.1 + Generic Clock Generator + GCLK + GCLK_ + 0x40001C00 + + 0 + 0x198 + registers + + + + CTRLA + Control + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + + + SYNCBUSY + Synchronization Busy + 0x4 + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchroniation Busy bit + 0 + 1 + + + GENCTRL0 + Generic Clock Generator Control 0 Synchronization Busy bits + 2 + 1 + + GENCTRL0Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + + + GENCTRL1 + Generic Clock Generator Control 1 Synchronization Busy bits + 3 + 1 + + GENCTRL1Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + + + GENCTRL2 + Generic Clock Generator Control 2 Synchronization Busy bits + 4 + 1 + + GENCTRL2Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + + + GENCTRL3 + Generic Clock Generator Control 3 Synchronization Busy bits + 5 + 1 + + GENCTRL3Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + + + GENCTRL4 + Generic Clock Generator Control 4 Synchronization Busy bits + 6 + 1 + + GENCTRL4Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + + + GENCTRL5 + Generic Clock Generator Control 5 Synchronization Busy bits + 7 + 1 + + GENCTRL5Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + + + GENCTRL6 + Generic Clock Generator Control 6 Synchronization Busy bits + 8 + 1 + + GENCTRL6Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + + + GENCTRL7 + Generic Clock Generator Control 7 Synchronization Busy bits + 9 + 1 + + GENCTRL7Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + + + GENCTRL8 + Generic Clock Generator Control 8 Synchronization Busy bits + 10 + 1 + + GENCTRL8Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + + + + + 9 + 4 + GENCTRL[%s] + Generic Clock Generator Control + 0x20 + 32 + 0x00000000 + + + SRC + Source Select + 0 + 3 + + SRCSelect + + XOSC + XOSC oscillator output + 0 + + + GCLKIN + Generator input pad + 1 + + + GCLKGEN1 + Generic clock generator 1 output + 2 + + + OSCULP32K + OSCULP32K oscillator output + 3 + + + OSC32K + OSC32K oscillator output + 4 + + + XOSC32K + XOSC32K oscillator output + 5 + + + OSC48M + OSC48M oscillator output + 6 + + + DPLL96M + DPLL96M output + 7 + + + + + GENEN + Generic Clock Generator Enable + 8 + 1 + + + IDC + Improve Duty Cycle + 9 + 1 + + + OOV + Output Off Value + 10 + 1 + + + OE + Output Enable + 11 + 1 + + + DIVSEL + Divide Selection + 12 + 1 + + DIVSELSelect + + DIV1 + Divide input directly by divider factor + 0x0 + + + DIV2 + Divide input by 2^(divider factor+ 1) + 0x1 + + + + + RUNSTDBY + Run in Standby + 13 + 1 + + + DIV + Division Factor + 16 + 16 + + + + + 46 + 4 + PCHCTRL[%s] + Peripheral Clock Control + 0x80 + 32 + 0x00000000 + + + GEN + Generic Clock Generator + 0 + 4 + + GENSelect + + GCLK0 + Generic clock generator 0 + 0x0 + + + GCLK1 + Generic clock generator 1 + 0x1 + + + GCLK2 + Generic clock generator 2 + 0x2 + + + GCLK3 + Generic clock generator 3 + 0x3 + + + GCLK4 + Generic clock generator 4 + 0x4 + + + GCLK5 + Generic clock generator 5 + 0x5 + + + GCLK6 + Generic clock generator 6 + 0x6 + + + GCLK7 + Generic clock generator 7 + 0x7 + + + GCLK8 + Generic clock generator 8 + 0x8 + + + + + CHEN + Channel Enable + 6 + 1 + + + WRTLOCK + Write Lock + 7 + 1 + + + + + + + HMATRIXHS + I76382.1.4 + HSB Matrix + HMATRIXB + HMATRIXB_ + 0x4100A000 + + 0 + 0x168 + registers + + + + 16 + 4 + MCFG[%s] + Master Configuration + 0x0 + 32 + 0x00000002 + + + ULBT + Undefined Length Burst Type + 0 + 3 + + ULBTSelect + + INFINITE + Infinite Length + 0 + + + SINGLE + Single Access + 1 + + + FOUR_BEAT + Four Beat Burst + 2 + + + EIGHT_BEAT + Eight Beat Burst + 3 + + + SIXTEEN_BEAT + Sixteen Beat Burst + 4 + + + + + + + 16 + 4 + SCFG[%s] + Slave Configuration + 0x40 + 32 + 0x00000010 + + + SLOT_CYCLE + Maximum Number of Allowed Cycles for a Burst + 0 + 8 + + + DEFMSTR_TYPE + Default Master Type + 16 + 2 + + DEFMSTR_TYPESelect + + NO_DEFAULT + No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. + 0 + + + LAST_DEFAULT + Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. + 1 + + + FIXED_DEFAULT + Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave. + 2 + + + + + FIXED_DEFMSTR + Fixed Index of Default Master + 18 + 4 + + + ARBT + Arbitration Type + 24 + 1 + + ARBTSelect + + ROUND_ROBIN + Round-Robin Arbitration + 0 + + + FIXED_PRIORITY + Fixed Priority Arbitration + 1 + + + + + + + 4 + 0x8 + PRS[%s] + + 0x080 + + PRAS + Priority A for Slave + 0x0 + 32 + 0x00000000 + + + M0PR + Master 0 Priority + 0 + 4 + + + M1PR + Master 1 Priority + 4 + 4 + + + M2PR + Master 2 Priority + 8 + 4 + + + M3PR + Master 3 Priority + 12 + 4 + + + M4PR + Master 4 Priority + 16 + 4 + + + M5PR + Master 5 Priority + 20 + 4 + + + M6PR + Master 6 Priority + 24 + 4 + + + M7PR + Master 7 Priority + 28 + 4 + + + + + PRBS + Priority B for Slave + 0x4 + 32 + 0x00000000 + + + M8PR + Master 8 Priority + 0 + 4 + + + M9PR + Master 9 Priority + 4 + 4 + + + M10PR + Master 10 Priority + 8 + 4 + + + M11PR + Master 11 Priority + 12 + 4 + + + M12PR + Master 12 Priority + 16 + 4 + + + M13PR + Master 13 Priority + 20 + 4 + + + M14PR + Master 14 Priority + 24 + 4 + + + M15PR + Master 15 Priority + 28 + 4 + + + + + + MRCR + Master Remap Control + 0x100 + 32 + 0x00000000 + + + RCB0 + Remap Command Bit for Master 0 + 0 + 1 + + RCB0Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB1 + Remap Command Bit for Master 1 + 1 + 1 + + RCB1Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB2 + Remap Command Bit for Master 2 + 2 + 1 + + RCB2Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB3 + Remap Command Bit for Master 3 + 3 + 1 + + RCB3Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB4 + Remap Command Bit for Master 4 + 4 + 1 + + RCB4Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB5 + Remap Command Bit for Master 5 + 5 + 1 + + RCB5Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB6 + Remap Command Bit for Master 6 + 6 + 1 + + RCB6Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB7 + Remap Command Bit for Master 7 + 7 + 1 + + RCB7Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB8 + Remap Command Bit for Master 8 + 8 + 1 + + RCB8Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB9 + Remap Command Bit for Master 9 + 9 + 1 + + RCB9Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB10 + Remap Command Bit for Master 10 + 10 + 1 + + RCB10Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB11 + Remap Command Bit for Master 11 + 11 + 1 + + RCB11Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB12 + Remap Command Bit for Master 12 + 12 + 1 + + RCB12Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB13 + Remap Command Bit for Master 13 + 13 + 1 + + RCB13Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB14 + Remap Command Bit for Master 14 + 14 + 1 + + RCB14Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB15 + Remap Command Bit for Master 15 + 15 + 1 + + RCB15Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + + + 16 + 4 + SFR[%s] + Special Function + 0x110 + 32 + 0x00000000 + + + SFR + Special Function Register + 0 + 32 + + + + + + + MCLK + U22342.0.0 + Main Clock + MCLK + MCLK_ + 0x40000800 + + 0 + 0x24 + registers + + + + INTENCLR + Interrupt Enable Clear + 0x1 + 8 + 0x00 + + + CKRDY + Clock Ready Interrupt Enable + 0 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x2 + 8 + 0x00 + + + CKRDY + Clock Ready Interrupt Enable + 0 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x3 + 8 + 0x01 + + + CKRDY + Clock Ready + 0 + 1 + + + + + CPUDIV + CPU Clock Division + 0x4 + 8 + 0x01 + + + CPUDIV + CPU Clock Division Factor + 0 + 8 + + CPUDIVSelect + + DIV1 + Divide by 1 + 0x01 + + + DIV2 + Divide by 2 + 0x02 + + + DIV4 + Divide by 4 + 0x04 + + + DIV8 + Divide by 8 + 0x08 + + + DIV16 + Divide by 16 + 0x10 + + + DIV32 + Divide by 32 + 0x20 + + + DIV64 + Divide by 64 + 0x40 + + + DIV128 + Divide by 128 + 0x80 + + + + + + + AHBMASK + AHB Mask + 0x10 + 32 + 0x00003CFF + + + HPB0_ + HPB0 AHB Clock Mask + 0 + 1 + + + HPB1_ + HPB1 AHB Clock Mask + 1 + 1 + + + HPB2_ + HPB2 AHB Clock Mask + 2 + 1 + + + DSU_ + DSU AHB Clock Mask + 3 + 1 + + + HMATRIXHS_ + HMATRIXHS AHB Clock Mask + 4 + 1 + + + NVMCTRL_ + NVMCTRL AHB Clock Mask + 5 + 1 + + + HSRAM_ + HSRAM AHB Clock Mask + 6 + 1 + + + DMAC_ + DMAC AHB Clock Mask + 7 + 1 + + + PAC_ + PAC AHB Clock Mask + 10 + 1 + + + NVMCTRL_PICACHU_ + NVMCTRL_PICACHU AHB Clock Mask + 11 + 1 + + + DIVAS_ + DIVAS AHB Clock Mask + 12 + 1 + + + HPB3_ + HPB3 AHB Clock Mask + 13 + 1 + + + + + APBAMASK + APBA Mask + 0x14 + 32 + 0x00000FFF + + + PAC_ + PAC APB Clock Enable + 0 + 1 + + + PM_ + PM APB Clock Enable + 1 + 1 + + + MCLK_ + MCLK APB Clock Enable + 2 + 1 + + + RSTC_ + RSTC APB Clock Enable + 3 + 1 + + + OSCCTRL_ + OSCCTRL APB Clock Enable + 4 + 1 + + + OSC32KCTRL_ + OSC32KCTRL APB Clock Enable + 5 + 1 + + + SUPC_ + SUPC APB Clock Enable + 6 + 1 + + + GCLK_ + GCLK APB Clock Enable + 7 + 1 + + + WDT_ + WDT APB Clock Enable + 8 + 1 + + + RTC_ + RTC APB Clock Enable + 9 + 1 + + + EIC_ + EIC APB Clock Enable + 10 + 1 + + + FREQM_ + FREQM APB Clock Enable + 11 + 1 + + + + + APBBMASK + APBB Mask + 0x18 + 32 + 0x00000007 + + + PORT_ + PORT APB Clock Enable + 0 + 1 + + + DSU_ + DSU APB Clock Enable + 1 + 1 + + + NVMCTRL_ + NVMCTRL APB Clock Enable + 2 + 1 + + + HMATRIXHS_ + HMATRIXHS APB Clock Enable + 5 + 1 + + + + + APBCMASK + APBC Mask + 0x1C + 32 + 0x00000000 + + + EVSYS_ + EVSYS APB Clock Enable + 0 + 1 + + + SERCOM0_ + SERCOM0 APB Clock Enable + 1 + 1 + + + SERCOM1_ + SERCOM1 APB Clock Enable + 2 + 1 + + + SERCOM2_ + SERCOM2 APB Clock Enable + 3 + 1 + + + SERCOM3_ + SERCOM3 APB Clock Enable + 4 + 1 + + + SERCOM4_ + SERCOM4 APB Clock Enable + 5 + 1 + + + SERCOM5_ + SERCOM5 APB Clock Enable + 6 + 1 + + + TCC0_ + TCC0 APB Clock Enable + 9 + 1 + + + TCC1_ + TCC1 APB Clock Enable + 10 + 1 + + + TCC2_ + TCC2 APB Clock Enable + 11 + 1 + + + TC0_ + TC0 APB Clock Enable + 12 + 1 + + + TC1_ + TC1 APB Clock Enable + 13 + 1 + + + TC2_ + TC2 APB Clock Enable + 14 + 1 + + + TC3_ + TC3 APB Clock Enable + 15 + 1 + + + TC4_ + TC4 APB Clock Enable + 16 + 1 + + + ADC0_ + ADC0 APB Clock Enable + 17 + 1 + + + AC_ + AC APB Clock Enable + 20 + 1 + + + PTC_ + PTC APB Clock Enable + 22 + 1 + + + CCL_ + CCL APB Clock Enable + 23 + 1 + + + + + APBDMASK + APBD Mask + 0x20 + 32 + 0x00000000 + + + SERCOM6_ + SERCOM6 APB Clock Enable + 0 + 1 + + + SERCOM7_ + SERCOM7 APB Clock Enable + 1 + 1 + + + TC5_ + TC5 APB Clock Enable + 2 + 1 + + + TC6_ + TC6 APB Clock Enable + 3 + 1 + + + TC7_ + TC7 APB Clock Enable + 4 + 1 + + + + + + + MTB + U20021.0.0 + Cortex-M0+ Micro-Trace Buffer + MTB + MTB_ + 0x41008000 + + 0 + 0x1000 + registers + + + + POSITION + MTB Position + 0x0 + 32 + + + WRAP + Pointer Value Wraps + 2 + 1 + + + POINTER + Trace Packet Location Pointer + 3 + 29 + + + + + MASTER + MTB Master + 0x4 + 32 + 0x00000000 + + + MASK + Maximum Value of the Trace Buffer in SRAM + 0 + 5 + + + TSTARTEN + Trace Start Input Enable + 5 + 1 + + + TSTOPEN + Trace Stop Input Enable + 6 + 1 + + + SFRWPRIV + Special Function Register Write Privilege + 7 + 1 + + + RAMPRIV + SRAM Privilege + 8 + 1 + + + HALTREQ + Halt Request + 9 + 1 + + + EN + Main Trace Enable + 31 + 1 + + + + + FLOW + MTB Flow + 0x8 + 32 + 0x00000000 + + + AUTOSTOP + Auto Stop Tracing + 0 + 1 + + + AUTOHALT + Auto Halt Request + 1 + 1 + + + WATERMARK + Watermark value + 3 + 29 + + + + + BASE + MTB Base + 0xC + 32 + read-only + + + ITCTRL + MTB Integration Mode Control + 0xF00 + 32 + + + CLAIMSET + MTB Claim Set + 0xFA0 + 32 + + + CLAIMCLR + MTB Claim Clear + 0xFA4 + 32 + + + LOCKACCESS + MTB Lock Access + 0xFB0 + 32 + + + LOCKSTATUS + MTB Lock Status + 0xFB4 + 32 + read-only + + + AUTHSTATUS + MTB Authentication Status + 0xFB8 + 32 + read-only + + + DEVARCH + MTB Device Architecture + 0xFBC + 32 + read-only + + + DEVID + MTB Device Configuration + 0xFC8 + 32 + read-only + + + DEVTYPE + MTB Device Type + 0xFCC + 32 + read-only + + + PID4 + Peripheral Identification 4 + 0xFD0 + 32 + read-only + + + PID5 + Peripheral Identification 5 + 0xFD4 + 32 + read-only + + + PID6 + Peripheral Identification 6 + 0xFD8 + 32 + read-only + + + PID7 + Peripheral Identification 7 + 0xFDC + 32 + read-only + + + PID0 + Peripheral Identification 0 + 0xFE0 + 32 + read-only + + + PID1 + Peripheral Identification 1 + 0xFE4 + 32 + read-only + + + PID2 + Peripheral Identification 2 + 0xFE8 + 32 + read-only + + + PID3 + Peripheral Identification 3 + 0xFEC + 32 + read-only + + + CID0 + Component Identification 0 + 0xFF0 + 32 + read-only + + + CID1 + Component Identification 1 + 0xFF4 + 32 + read-only + + + CID2 + Component Identification 2 + 0xFF8 + 32 + read-only + + + CID3 + Component Identification 3 + 0xFFC + 32 + read-only + + + + + NVMCTRL + U22074.0.2 + Non-Volatile Memory Controller + NVMCTRL + NVMCTRL_ + 0x41004000 + + 0 + 0x30 + registers + + + NVMCTRL + 6 + + + + CTRLA + Control A + 0x0 + 16 + 0x0000 + + + CMD + Command + 0 + 7 + + CMDSelect + + ER + Erase Row - Erases the row addressed by the ADDR register. + 0x02 + + + WP + Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. + 0x04 + + + EAR + Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. + 0x05 + + + WAP + Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. + 0x06 + + + SF + Security Flow Command + 0x0A + + + WL + Write lockbits + 0x0F + + + RWWEEER + RWW EEPROM area Erase Row - Erases the row addressed by the ADDR register. + 0x1A + + + RWWEEWP + RWW EEPROM Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. + 0x1C + + + LR + Lock Region - Locks the region containing the address location in the ADDR register. + 0x40 + + + UR + Unlock Region - Unlocks the region containing the address location in the ADDR register. + 0x41 + + + SPRM + Sets the power reduction mode. + 0x42 + + + CPRM + Clears the power reduction mode. + 0x43 + + + PBC + Page Buffer Clear - Clears the page buffer. + 0x44 + + + SSB + Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row. + 0x45 + + + INVALL + Invalidate all cache lines. + 0x46 + + + + + CMDEX + Command Execution + 8 + 8 + + CMDEXSelect + + KEY + Execution Key + 0xA5 + + + + + + + CTRLB + Control B + 0x4 + 32 + 0x00000080 + + + RWS + NVM Read Wait States + 1 + 4 + + RWSSelect + + SINGLE + Single Auto Wait State + 0 + + + HALF + Half Auto Wait State + 1 + + + DUAL + Dual Auto Wait State + 2 + + + + + MANW + Manual Write + 7 + 1 + + + SLEEPPRM + Power Reduction Mode during Sleep + 8 + 2 + + SLEEPPRMSelect + + WAKEONACCESS + NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access. + 0 + + + WAKEUPINSTANT + NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep. + 1 + + + DISABLED + Auto power reduction disabled. + 3 + + + + + READMODE + NVMCTRL Read Mode + 16 + 2 + + READMODESelect + + NO_MISS_PENALTY + The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance. + 0x0 + + + LOW_POWER + Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time. + 0x1 + + + DETERMINISTIC + The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings. + 0x2 + + + + + CACHEDIS + Cache Disable + 18 + 2 + + + + + PARAM + NVM Parameter + 0x8 + 32 + 0x00000000 + + + NVMP + NVM Pages + 0 + 16 + + + PSZ + Page Size + 16 + 3 + + PSZSelect + + 8 + 8 bytes + 0x0 + + + 16 + 16 bytes + 0x1 + + + 32 + 32 bytes + 0x2 + + + 64 + 64 bytes + 0x3 + + + 128 + 128 bytes + 0x4 + + + 256 + 256 bytes + 0x5 + + + 512 + 512 bytes + 0x6 + + + 1024 + 1024 bytes + 0x7 + + + + + RWWEEP + RWW EEPROM Pages + 20 + 12 + + + + + INTENCLR + Interrupt Enable Clear + 0xC + 8 + 0x00 + + + READY + NVM Ready Interrupt Enable + 0 + 1 + + + ERROR + Error Interrupt Enable + 1 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x10 + 8 + 0x00 + + + READY + NVM Ready Interrupt Enable + 0 + 1 + + + ERROR + Error Interrupt Enable + 1 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x14 + 8 + 0x00 + + + READY + NVM Ready + 0 + 1 + + + ERROR + Error + 1 + 1 + + + + + STATUS + Status + 0x18 + 16 + 0x0000 + + + PRM + Power Reduction Mode + 0 + 1 + + + LOAD + NVM Page Buffer Active Loading + 1 + 1 + + + PROGE + Programming Error Status + 2 + 1 + + + LOCKE + Lock Error Status + 3 + 1 + + + NVME + NVM Error + 4 + 1 + + + SB + Security Bit Status + 8 + 1 + + + + + ADDR + Address + 0x1C + 32 + 0x00000000 + + + ADDR + NVM Address + 0 + 22 + + + + + LOCK + Lock Section + 0x20 + 16 + 0x0000 + + + LOCK + Region Lock Bits + 0 + 16 + + + + + PBLDATA0 + Page Buffer Load Data 0 + 0x28 + 32 + read-only + 0x00000000 + + + PBLDATA1 + Page Buffer Load Data 1 + 0x2C + 32 + read-only + 0x00000000 + + + + + OSCCTRL + U21192.1.0 + Oscillators Control + OSCCTRL + OSCCTRL_ + 0x40001000 + + 0 + 0x3C + registers + + + + INTENCLR + Interrupt Enable Clear + 0x0 + 32 + 0x00000000 + + + XOSCRDY + XOSC Ready Interrupt Enable + 0 + 1 + + + XOSCFAIL + XOSC Clock Failure Detector Interrupt Enable + 1 + 1 + + + OSC48MRDY + OSC48M Ready Interrupt Enable + 4 + 1 + + + DPLLLCKR + DPLL Lock Rise Interrupt Enable + 8 + 1 + + + DPLLLCKF + DPLL Lock Fall Interrupt Enable + 9 + 1 + + + DPLLLTO + DPLL Time Out Interrupt Enable + 10 + 1 + + + DPLLLDRTO + DPLL Ratio Ready Interrupt Enable + 11 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x4 + 32 + 0x00000000 + + + XOSCRDY + XOSC Ready Interrupt Enable + 0 + 1 + + + XOSCFAIL + XOSC Clock Failure Detector Interrupt Enable + 1 + 1 + + + OSC48MRDY + OSC48M Ready Interrupt Enable + 4 + 1 + + + DPLLLCKR + DPLL Lock Rise Interrupt Enable + 8 + 1 + + + DPLLLCKF + DPLL Lock Fall Interrupt Enable + 9 + 1 + + + DPLLLTO + DPLL Time Out Interrupt Enable + 10 + 1 + + + DPLLLDRTO + DPLL Ratio Ready Interrupt Enable + 11 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x8 + 32 + 0x00000000 + + + XOSCRDY + XOSC Ready + 0 + 1 + + + XOSCFAIL + XOSC Clock Failure Detector + 1 + 1 + + + OSC48MRDY + OSC48M Ready + 4 + 1 + + + DPLLLCKR + DPLL Lock Rise + 8 + 1 + + + DPLLLCKF + DPLL Lock Fall + 9 + 1 + + + DPLLLTO + DPLL Timeout + 10 + 1 + + + DPLLLDRTO + DPLL Ratio Ready + 11 + 1 + + + + + STATUS + Power and Clocks Status + 0xC + 32 + read-only + 0x00000000 + + + XOSCRDY + XOSC Ready + 0 + 1 + + + XOSCFAIL + XOSC Clock Failure Detector + 1 + 1 + + + XOSCCKSW + XOSC Clock Switch + 2 + 1 + + + OSC48MRDY + OSC48M Ready + 4 + 1 + + + DPLLLCKR + DPLL Lock Rise + 8 + 1 + + + DPLLLCKF + DPLL Lock Fall + 9 + 1 + + + DPLLTO + DPLL Timeout + 10 + 1 + + + DPLLLDRTO + DPLL Ratio Ready + 11 + 1 + + + + + XOSCCTRL + External Multipurpose Crystal Oscillator (XOSC) Control + 0x10 + 16 + 0x0080 + + + ENABLE + Oscillator Enable + 1 + 1 + + + XTALEN + Crystal Oscillator Enable + 2 + 1 + + + CFDEN + Xosc Clock Failure Detector Enable + 3 + 1 + + + SWBEN + Xosc Clock Switch Enable + 4 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + GAIN + Oscillator Gain + 8 + 3 + + GAINSelect + + GAIN2 + 2 MHz + 0 + + + GAIN4 + 4 MHz + 1 + + + GAIN8 + 8 MHz + 2 + + + GAIN16 + 16 MHz + 3 + + + GAIN30 + 30 MHz + 4 + + + + + AMPGC + Automatic Amplitude Gain Control + 11 + 1 + + + STARTUP + Start-Up Time + 12 + 4 + + STARTUPSelect + + CYCLE1 + 31 us + 0 + + + CYCLE2 + 61 us + 1 + + + CYCLE4 + 122 us + 2 + + + CYCLE8 + 244 us + 3 + + + CYCLE16 + 488 us + 4 + + + CYCLE32 + 977 us + 5 + + + CYCLE64 + 1953 us + 6 + + + CYCLE128 + 3906 us + 7 + + + CYCLE256 + 7813 us + 8 + + + CYCLE512 + 15625 us + 9 + + + CYCLE1024 + 31250 us + 10 + + + CYCLE2048 + 62500 us + 11 + + + CYCLE4096 + 125000 us + 12 + + + CYCLE8192 + 250000 us + 13 + + + CYCLE16384 + 500000 us + 14 + + + CYCLE32768 + 1000000 us + 15 + + + + + + + CFDPRESC + Clock Failure Detector Prescaler + 0x12 + 8 + 0x00 + + + CFDPRESC + Clock Failure Detector Prescaler + 0 + 3 + + CFDPRESCSelect + + DIV1 + 48 MHz + 0 + + + DIV2 + 24 MHz + 1 + + + DIV4 + 12 MHz + 2 + + + DIV8 + 6 MHz + 3 + + + DIV16 + 3 MHz + 4 + + + DIV32 + 1.5 MHz + 5 + + + DIV64 + 0.75 MHz + 6 + + + DIV128 + 0.3125 MHz + 7 + + + + + + + EVCTRL + Event Control + 0x13 + 8 + 0x00 + + + CFDEO + Clock Failure Detector Event Output Enable + 0 + 1 + + + + + OSC48MCTRL + 48MHz Internal Oscillator (OSC48M) Control + 0x14 + 8 + 0x82 + + + ENABLE + Oscillator Enable + 1 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + + + OSC48MDIV + OSC48M Divider + 0x15 + 8 + 0x0B + + + DIV + OSC48M Division Factor + 0 + 4 + + DIVSelect + + DIV1 + 48 MHz + 0 + + + DIV2 + 24 MHz + 1 + + + DIV3 + 16 MHz + 2 + + + DIV4 + 12 MHz + 3 + + + DIV5 + 9.6 MHz + 4 + + + DIV6 + 8 MHz + 5 + + + DIV7 + 6.86 MHz + 6 + + + DIV8 + 6 MHz + 7 + + + DIV9 + 5.33 MHz + 8 + + + DIV10 + 4.8 MHz + 9 + + + DIV11 + 4.36 MHz + 10 + + + DIV12 + 4 MHz + 11 + + + DIV13 + 3.69 MHz + 12 + + + DIV14 + 3.43 MHz + 13 + + + DIV15 + 3.2 MHz + 14 + + + DIV16 + 3 MHz + 15 + + + + + + + OSC48MSTUP + OSC48M Startup Time + 0x16 + 8 + 0x07 + + + STARTUP + Startup Time + 0 + 3 + + STARTUPSelect + + CYCLE8 + 166 ns + 0 + + + CYCLE16 + 333 ns + 1 + + + CYCLE32 + 667 ns + 2 + + + CYCLE64 + 1.333 us + 3 + + + CYCLE128 + 2.667 us + 4 + + + CYCLE256 + 5.333 us + 5 + + + CYCLE512 + 10.667 us + 6 + + + CYCLE1024 + 21.333 us + 7 + + + + + + + OSC48MSYNCBUSY + OSC48M Synchronization Busy + 0x18 + 32 + read-only + 0x00000000 + + + OSC48MDIV + OSC48MDIV Synchronization Status + 2 + 1 + + + + + DPLLCTRLA + DPLL Control + 0x1C + 8 + 0x80 + + + ENABLE + Enable + 1 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand + 7 + 1 + + + + + DPLLRATIO + DPLL Ratio Control + 0x20 + 32 + 0x00000000 + + + LDR + Loop Divider Ratio + 0 + 12 + + + LDRFRAC + Loop Divider Ratio Fractional Part + 16 + 4 + + + + + DPLLCTRLB + Digital Core Configuration + 0x24 + 32 + 0x00000000 + + + FILTER + Proportional Integral Filter Selection + 0 + 2 + + FILTERSelect + + DEFAULT + Default filter mode + 0 + + + LBFILT + Low bandwidth filter + 1 + + + HBFILT + High bandwidth filter + 2 + + + HDFILT + High damping filter + 3 + + + + + LPEN + Low-Power Enable + 2 + 1 + + + WUF + Wake Up Fast + 3 + 1 + + + REFCLK + Reference Clock Selection + 4 + 2 + + REFCLKSelect + + XOSC32K + XOSC32K clock reference + 0 + + + XOSC + XOSC clock reference + 1 + + + GCLK + GCLK clock reference + 2 + + + + + LTIME + Lock Time + 8 + 3 + + LTIMESelect + + DEFAULT + No time-out. Automatic lock. + 0 + + + 8MS + Time-out if no lock within 8ms + 4 + + + 9MS + Time-out if no lock within 9ms + 5 + + + 10MS + Time-out if no lock within 10ms + 6 + + + 11MS + Time-out if no lock within 11ms + 7 + + + + + LBYPASS + Lock Bypass + 12 + 1 + + + DIV + Clock Divider + 16 + 11 + + + + + DPLLPRESC + DPLL Prescaler + 0x28 + 8 + 0x00 + + + PRESC + Output Clock Prescaler + 0 + 2 + + PRESCSelect + + DIV1 + DPLL output is divided by 1 + 0 + + + DIV2 + DPLL output is divided by 2 + 1 + + + DIV4 + DPLL output is divided by 4 + 2 + + + + + + + DPLLSYNCBUSY + DPLL Synchronization Busy + 0x2C + 8 + read-only + 0x00 + + + ENABLE + DPLL Enable Synchronization Status + 1 + 1 + + + DPLLRATIO + DPLL Ratio Synchronization Status + 2 + 1 + + + DPLLPRESC + DPLL Prescaler Synchronization Status + 3 + 1 + + + + + DPLLSTATUS + DPLL Status + 0x30 + 8 + read-only + 0x00 + + + LOCK + DPLL Lock Status + 0 + 1 + + + CLKRDY + DPLL Clock Ready + 1 + 1 + + + + + CAL48M + 48MHz Oscillator Calibration + 0x38 + 32 + 0x00000000 + + + FCAL + Frequency Calibration (48MHz) + 0 + 6 + + + FRANGE + Frequency Range (48MHz) + 8 + 2 + + + TCAL + Temperature Calibration (48MHz) + 16 + 6 + + + + + + + OSC32KCTRL + U22462.1.0 + 32k Oscillators Control + OSC32KCTRL + OSC32KCTRL_ + 0x40001400 + + 0 + 0x20 + registers + + + + INTENCLR + Interrupt Enable Clear + 0x0 + 32 + 0x00000000 + + + XOSC32KRDY + XOSC32K Ready Interrupt Enable + 0 + 1 + + + OSC32KRDY + OSC32K Ready Interrupt Enable + 1 + 1 + + + CLKFAIL + XOSC32K Clock Failure Detector Interrupt Enable + 2 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x4 + 32 + 0x00000000 + + + XOSC32KRDY + XOSC32K Ready Interrupt Enable + 0 + 1 + + + OSC32KRDY + OSC32K Ready Interrupt Enable + 1 + 1 + + + CLKFAIL + XOSC32K Clock Failure Detector Interrupt Enable + 2 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x8 + 32 + 0x00000000 + + + XOSC32KRDY + XOSC32K Ready + 0 + 1 + + + OSC32KRDY + OSC32K Ready + 1 + 1 + + + CLKFAIL + XOSC32K Clock Failure Detector + 2 + 1 + + + + + STATUS + Power and Clocks Status + 0xC + 32 + read-only + 0x00000000 + + + XOSC32KRDY + XOSC32K Ready + 0 + 1 + + + OSC32KRDY + OSC32K Ready + 1 + 1 + + + CLKFAIL + XOSC32K Clock Failure Detector + 2 + 1 + + + CLKSW + XOSC32K Clock switch + 3 + 1 + + + + + RTCCTRL + Clock selection + 0x10 + 32 + 0x00000000 + + + RTCSEL + RTC Clock Selection + 0 + 3 + + RTCSELSelect + + ULP1K + 1.024kHz from 32kHz internal ULP oscillator + 0 + + + ULP32K + 32.768kHz from 32kHz internal ULP oscillator + 1 + + + OSC1K + 1.024kHz from 32.768kHz internal oscillator + 2 + + + OSC32K + 32.768kHz from 32.768kHz internal oscillator + 3 + + + XOSC1K + 1.024kHz from 32.768kHz internal oscillator + 4 + + + XOSC32K + 32.768kHz from 32.768kHz external crystal oscillator + 5 + + + + + + + XOSC32K + 32kHz External Crystal Oscillator (XOSC32K) Control + 0x14 + 16 + 0x0080 + + + ENABLE + Oscillator Enable + 1 + 1 + + + XTALEN + Crystal Oscillator Enable + 2 + 1 + + + EN32K + 32kHz Output Enable + 3 + 1 + + + EN1K + 1kHz Output Enable + 4 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + STARTUP + Oscillator Start-Up Time + 8 + 3 + + STARTUPSelect + + CYCLE1 + 0.122 ms + 0 + + + CYCLE32 + 1.068 ms + 1 + + + CYCLE2048 + 62.6 ms + 2 + + + CYCLE4096 + 125 ms + 3 + + + CYCLE16384 + 500 ms + 4 + + + CYCLE32768 + 1000 ms + 5 + + + CYCLE65536 + 2000 ms + 6 + + + CYCLE131072 + 4000 ms + 7 + + + + + WRTLOCK + Write Lock + 12 + 1 + + + + + CFDCTRL + Clock Failure Detector Control + 0x16 + 8 + 0x00 + + + CFDEN + Clock Failure Detector Enable + 0 + 1 + + + SWBACK + Clock Switch Back + 1 + 1 + + + CFDPRESC + Clock Failure Detector Prescaler + 2 + 1 + + + + + EVCTRL + Event Control + 0x17 + 8 + 0x00 + + + CFDEO + Clock Failure Detector Event Output Enable + 0 + 1 + + + + + OSC32K + 32kHz Internal Oscillator (OSC32K) Control + 0x18 + 32 + 0x003F0080 + + + ENABLE + Oscillator Enable + 1 + 1 + + + EN32K + 32kHz Output Enable + 2 + 1 + + + EN1K + 1kHz Output Enable + 3 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + STARTUP + Oscillator Start-Up Time + 8 + 3 + + STARTUPSelect + + CYCLE3 + 0.092 ms + 0 + + + CYCLE4 + 0.122 ms + 1 + + + CYCLE6 + 0.183 ms + 2 + + + CYCLE10 + 0.305 ms + 3 + + + CYCLE18 + 0.549 ms + 4 + + + CYCLE34 + 1.038 ms + 5 + + + CYCLE66 + 2.014 ms + 6 + + + CYCLE130 + 3.967 ms + 7 + + + + + WRTLOCK + Write Lock + 12 + 1 + + + CALIB + Oscillator Calibration + 16 + 7 + + + + + OSCULP32K + 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control + 0x1C + 32 + + + CALIB + Oscillator Calibration + 8 + 5 + + + WRTLOCK + Write Lock + 15 + 1 + + + + + + + PAC + U21201.1.0 + Peripheral Access Controller + PAC + PAC_ + 0x40000000 + + 0 + 0x44 + registers + + + + WRCTRL + Write control + 0x0 + 32 + 0x00000000 + + + PERID + Peripheral identifier + 0 + 16 + + + KEY + Peripheral access control key + 16 + 8 + + KEYSelect + + OFF + No action + 0 + + + CLR + Clear protection + 1 + + + SET + Set protection + 2 + + + SETLCK + Set and lock protection + 3 + + + + + + + EVCTRL + Event control + 0x4 + 8 + 0x00 + + + ERREO + Peripheral acess error event output + 0 + 1 + + + + + INTENCLR + Interrupt enable clear + 0x8 + 8 + 0x00 + + + ERR + Peripheral access error interrupt disable + 0 + 1 + + + + + INTENSET + Interrupt enable set + 0x9 + 8 + 0x00 + + + ERR + Peripheral access error interrupt enable + 0 + 1 + + + + + INTFLAGAHB + Bridge interrupt flag status + 0x10 + 32 + 0x00000000 + + + FLASH_ + FLASH + 0 + 1 + + + HSRAMCM0P_ + HSRAMCM0P + 1 + 1 + + + HSRAMDSU_ + HSRAMDSU + 2 + 1 + + + HPB1_ + HPB1 + 3 + 1 + + + HPB0_ + HPB0 + 4 + 1 + + + HPB2_ + HPB2 + 5 + 1 + + + LPRAMDMAC_ + LPRAMDMAC + 6 + 1 + + + DIVAS_ + DIVAS + 7 + 1 + + + HPB3_ + HPB3 + 8 + 1 + + + + + INTFLAGA + Peripheral interrupt flag status - Bridge A + 0x14 + 32 + 0x00000000 + + + PAC_ + PAC + 0 + 1 + + + PM_ + PM + 1 + 1 + + + MCLK_ + MCLK + 2 + 1 + + + RSTC_ + RSTC + 3 + 1 + + + OSCCTRL_ + OSCCTRL + 4 + 1 + + + OSC32KCTRL_ + OSC32KCTRL + 5 + 1 + + + SUPC_ + SUPC + 6 + 1 + + + GCLK_ + GCLK + 7 + 1 + + + WDT_ + WDT + 8 + 1 + + + RTC_ + RTC + 9 + 1 + + + EIC_ + EIC + 10 + 1 + + + FREQM_ + FREQM + 11 + 1 + + + + + INTFLAGB + Peripheral interrupt flag status - Bridge B + 0x18 + 32 + 0x00000000 + + + PORT_ + PORT + 0 + 1 + + + DSU_ + DSU + 1 + 1 + + + NVMCTRL_ + NVMCTRL + 2 + 1 + + + DMAC_ + DMAC + 3 + 1 + + + MTB_ + MTB + 4 + 1 + + + HMATRIXHS_ + HMATRIXHS + 5 + 1 + + + + + INTFLAGC + Peripheral interrupt flag status - Bridge C + 0x1C + 32 + 0x00000000 + + + EVSYS_ + EVSYS + 0 + 1 + + + SERCOM0_ + SERCOM0 + 1 + 1 + + + SERCOM1_ + SERCOM1 + 2 + 1 + + + SERCOM2_ + SERCOM2 + 3 + 1 + + + SERCOM3_ + SERCOM3 + 4 + 1 + + + SERCOM4_ + SERCOM4 + 5 + 1 + + + SERCOM5_ + SERCOM5 + 6 + 1 + + + TCC0_ + TCC0 + 9 + 1 + + + TCC1_ + TCC1 + 10 + 1 + + + TCC2_ + TCC2 + 11 + 1 + + + TC0_ + TC0 + 12 + 1 + + + TC1_ + TC1 + 13 + 1 + + + TC2_ + TC2 + 14 + 1 + + + TC3_ + TC3 + 15 + 1 + + + TC4_ + TC4 + 16 + 1 + + + ADC0_ + ADC0 + 17 + 1 + + + AC_ + AC + 20 + 1 + + + PTC_ + PTC + 22 + 1 + + + CCL_ + CCL + 23 + 1 + + + + + INTFLAGD + Peripheral interrupt flag status - Bridge D + 0x20 + 32 + 0x00000000 + + + SERCOM6_ + SERCOM6 + 0 + 1 + + + SERCOM7_ + SERCOM7 + 1 + 1 + + + TC5_ + TC5 + 2 + 1 + + + TC6_ + TC6 + 3 + 1 + + + TC7_ + TC7 + 4 + 1 + + + + + STATUSA + Peripheral write protection status - Bridge A + 0x34 + 32 + read-only + 0x00000000 + + + PAC_ + PAC APB Protect Enable + 0 + 1 + + + PM_ + PM APB Protect Enable + 1 + 1 + + + MCLK_ + MCLK APB Protect Enable + 2 + 1 + + + RSTC_ + RSTC APB Protect Enable + 3 + 1 + + + OSCCTRL_ + OSCCTRL APB Protect Enable + 4 + 1 + + + OSC32KCTRL_ + OSC32KCTRL APB Protect Enable + 5 + 1 + + + SUPC_ + SUPC APB Protect Enable + 6 + 1 + + + GCLK_ + GCLK APB Protect Enable + 7 + 1 + + + WDT_ + WDT APB Protect Enable + 8 + 1 + + + RTC_ + RTC APB Protect Enable + 9 + 1 + + + EIC_ + EIC APB Protect Enable + 10 + 1 + + + FREQM_ + FREQM APB Protect Enable + 11 + 1 + + + + + STATUSB + Peripheral write protection status - Bridge B + 0x38 + 32 + read-only + 0x00000002 + + + PORT_ + PORT APB Protect Enable + 0 + 1 + + + DSU_ + DSU APB Protect Enable + 1 + 1 + + + NVMCTRL_ + NVMCTRL APB Protect Enable + 2 + 1 + + + DMAC_ + DMAC APB Protect Enable + 3 + 1 + + + MTB_ + MTB APB Protect Enable + 4 + 1 + + + HMATRIXHS_ + HMATRIXHS APB Protect Enable + 5 + 1 + + + + + STATUSC + Peripheral write protection status - Bridge C + 0x3C + 32 + read-only + 0x02000000 + + + EVSYS_ + EVSYS APB Protect Enable + 0 + 1 + + + SERCOM0_ + SERCOM0 APB Protect Enable + 1 + 1 + + + SERCOM1_ + SERCOM1 APB Protect Enable + 2 + 1 + + + SERCOM2_ + SERCOM2 APB Protect Enable + 3 + 1 + + + SERCOM3_ + SERCOM3 APB Protect Enable + 4 + 1 + + + SERCOM4_ + SERCOM4 APB Protect Enable + 5 + 1 + + + SERCOM5_ + SERCOM5 APB Protect Enable + 6 + 1 + + + TCC0_ + TCC0 APB Protect Enable + 9 + 1 + + + TCC1_ + TCC1 APB Protect Enable + 10 + 1 + + + TCC2_ + TCC2 APB Protect Enable + 11 + 1 + + + TC0_ + TC0 APB Protect Enable + 12 + 1 + + + TC1_ + TC1 APB Protect Enable + 13 + 1 + + + TC2_ + TC2 APB Protect Enable + 14 + 1 + + + TC3_ + TC3 APB Protect Enable + 15 + 1 + + + TC4_ + TC4 APB Protect Enable + 16 + 1 + + + ADC0_ + ADC0 APB Protect Enable + 17 + 1 + + + AC_ + AC APB Protect Enable + 20 + 1 + + + PTC_ + PTC APB Protect Enable + 22 + 1 + + + CCL_ + CCL APB Protect Enable + 23 + 1 + + + + + STATUSD + Peripheral write protection status - Bridge D + 0x40 + 32 + read-only + 0x00000000 + + + SERCOM6_ + SERCOM6 APB Protect Enable + 0 + 1 + + + SERCOM7_ + SERCOM7 APB Protect Enable + 1 + 1 + + + TC5_ + TC5 APB Protect Enable + 2 + 1 + + + TC6_ + TC6 APB Protect Enable + 3 + 1 + + + TC7_ + TC7 APB Protect Enable + 4 + 1 + + + + + + + PM + U22402.1.1 + Power Manager + PM + PM_ + 0x40000400 + + 0 + 0xA + registers + + + + SLEEPCFG + Sleep Configuration + 0x1 + 8 + 0x00 + + + SLEEPMODE + Sleep Mode + 0 + 3 + + SLEEPMODESelect + + IDLE0 + CPU clock is OFF + 0 + + + IDLE1 + AHB clock is OFF + 1 + + + IDLE2 + APB clock are OFF + 2 + + + STANDBY + All Clocks are OFF + 4 + + + BACKUP + Only Backup domain is powered ON + 5 + + + OFF + All power domains are powered OFF + 6 + + + + + + + STDBYCFG + Standby Configuration + 0x8 + 16 + 0x0400 + + + VREGSMOD + Voltage Regulator Standby mode + 6 + 2 + + VREGSMODSelect + + AUTO + Automatic mode + 0 + + + PERFORMANCE + Performance oriented + 1 + + + LP + Low Power oriented + 2 + + + + + BBIASHS + Back Bias for HMCRAMCHS + 10 + 2 + + + + + + + PORT + U22102.1.1 + Port Module + PORT + PORT_ + 0x41000000 + + 0 + 0x180 + registers + + + + 3 + 0x80 + GROUP[%s] + + 0x00 + + DIR + Data Direction + 0x0 + 32 + 0x00000000 + + + DIRCLR + Data Direction Clear + 0x4 + 32 + 0x00000000 + + + DIRSET + Data Direction Set + 0x8 + 32 + 0x00000000 + + + DIRTGL + Data Direction Toggle + 0xC + 32 + 0x00000000 + + + OUT + Data Output Value + 0x10 + 32 + 0x00000000 + + + OUTCLR + Data Output Value Clear + 0x14 + 32 + 0x00000000 + + + OUTSET + Data Output Value Set + 0x18 + 32 + 0x00000000 + + + OUTTGL + Data Output Value Toggle + 0x1C + 32 + 0x00000000 + + + IN + Data Input Value + 0x20 + 32 + read-only + 0x00000000 + + + CTRL + Control + 0x24 + 32 + 0x00000000 + + + SAMPLING + Input Sampling Mode + 0 + 32 + + + + + WRCONFIG + Write Configuration + 0x28 + 32 + write-only + 0x00000000 + + + PINMASK + Pin Mask for Multiple Pin Configuration + 0 + 16 + + + PMUXEN + Select Peripheral Multiplexer + 16 + 1 + + + INEN + Input Enable + 17 + 1 + + + PULLEN + Pull Enable + 18 + 1 + + + DRVSTR + Output Driver Strength Selection + 22 + 1 + + + PMUX + Peripheral Multiplexing Template + 24 + 4 + + + WRPMUX + Write PMUX Registers + 28 + 1 + + + WRPINCFG + Write PINCFG Registers + 30 + 1 + + + HWSEL + Half-Word Select + 31 + 1 + + + + + EVCTRL + Event Input Control + 0x2C + 32 + 0x00000000 + + + PID0 + Port Event Pin Identifier 0 + 0 + 5 + + + EVACT0 + Port Event Action 0 + 5 + 2 + + EVACT0Select + + OUT + Event output to pin + 0x0 + + + SET + Set output register of pin on event + 0x1 + + + CLR + Clear output register of pin on event + 0x2 + + + TGL + Toggle output register of pin on event + 0x3 + + + + + PORTEI0 + Port Event Enable Input 0 + 7 + 1 + + + PID1 + Port Event Pin Identifier 1 + 8 + 5 + + + EVACT1 + Port Event Action 1 + 13 + 2 + + + PORTEI1 + Port Event Enable Input 1 + 15 + 1 + + + PID2 + Port Event Pin Identifier 2 + 16 + 5 + + + EVACT2 + Port Event Action 2 + 21 + 2 + + + PORTEI2 + Port Event Enable Input 2 + 23 + 1 + + + PID3 + Port Event Pin Identifier 3 + 24 + 5 + + + EVACT3 + Port Event Action 3 + 29 + 2 + + + PORTEI3 + Port Event Enable Input 3 + 31 + 1 + + + + + 16 + 1 + PMUX[%s] + Peripheral Multiplexing n + 0x30 + 8 + 0x00 + + + PMUXE + Peripheral Multiplexing for Even-Numbered Pin + 0 + 4 + + + PMUXO + Peripheral Multiplexing for Odd-Numbered Pin + 4 + 4 + + + + + 32 + 1 + PINCFG[%s] + Pin Configuration n + 0x40 + 8 + 0x00 + + + PMUXEN + Select Peripheral Multiplexer + 0 + 1 + + + INEN + Input Enable + 1 + 1 + + + PULLEN + Pull Enable + 2 + 1 + + + DRVSTR + Output Driver Strength Selection + 6 + 1 + + + + + + + + PORT_IOBUS + PORT_IOBUS_ + 0x60000000 + + + PTC + U22153.2.0 + Peripheral Touch Controller + PTC + PTC_ + 0x42005800 + + 0 + 0x1 + reserved + + + PTC + 30 + + + + RSTC + U22392.0.2 + Reset Controller + RSTC + RSTC_ + 0x40000C00 + + 0 + 0x1 + registers + + + + RCAUSE + Reset Cause + 0x0 + 8 + read-only + + + POR + Power On Reset + 0 + 1 + + + BODCORE + Brown Out CORE Detector Reset + 1 + 1 + + + BODVDD + Brown Out VDD Detector Reset + 2 + 1 + + + EXT + External Reset + 4 + 1 + + + WDT + Watchdog Reset + 5 + 1 + + + SYST + System Reset Request + 6 + 1 + + + + + + + RTC + U22501.1.1 + Real-Time Counter + RTC + RTC_ + 0x40002400 + + 0 + 0x25 + registers + + + RTC + 2 + + + + MODE0 + 32-bit Counter with Single 32-bit Compare + RtcMode0 + 0x0 + + CTRLA + MODE0 Control A + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 2 + + MODESelect + + COUNT32 + Mode 0: 32-bit Counter + 0x0 + + + COUNT16 + Mode 1: 16-bit Counter + 0x1 + + + CLOCK + Mode 2: Clock/Calendar + 0x2 + + + + + MATCHCLR + Clear on Match + 7 + 1 + + + PRESCALER + Prescaler + 8 + 4 + + PRESCALERSelect + + OFF + CLK_RTC_CNT = GCLK_RTC/1 + 0x0 + + + DIV1 + CLK_RTC_CNT = GCLK_RTC/1 + 0x1 + + + DIV2 + CLK_RTC_CNT = GCLK_RTC/2 + 0x2 + + + DIV4 + CLK_RTC_CNT = GCLK_RTC/4 + 0x3 + + + DIV8 + CLK_RTC_CNT = GCLK_RTC/8 + 0x4 + + + DIV16 + CLK_RTC_CNT = GCLK_RTC/16 + 0x5 + + + DIV32 + CLK_RTC_CNT = GCLK_RTC/32 + 0x6 + + + DIV64 + CLK_RTC_CNT = GCLK_RTC/64 + 0x7 + + + DIV128 + CLK_RTC_CNT = GCLK_RTC/128 + 0x8 + + + DIV256 + CLK_RTC_CNT = GCLK_RTC/256 + 0x9 + + + DIV512 + CLK_RTC_CNT = GCLK_RTC/512 + 0xA + + + DIV1024 + CLK_RTC_CNT = GCLK_RTC/1024 + 0xB + + + + + COUNTSYNC + Count Read Synchronization Enable + 15 + 1 + + + + + EVCTRL + MODE0 Event Control + 0x4 + 32 + 0x00000000 + + + PEREO0 + Periodic Interval 0 Event Output Enable + 0 + 1 + + + PEREO1 + Periodic Interval 1 Event Output Enable + 1 + 1 + + + PEREO2 + Periodic Interval 2 Event Output Enable + 2 + 1 + + + PEREO3 + Periodic Interval 3 Event Output Enable + 3 + 1 + + + PEREO4 + Periodic Interval 4 Event Output Enable + 4 + 1 + + + PEREO5 + Periodic Interval 5 Event Output Enable + 5 + 1 + + + PEREO6 + Periodic Interval 6 Event Output Enable + 6 + 1 + + + PEREO7 + Periodic Interval 7 Event Output Enable + 7 + 1 + + + CMPEO0 + Compare 0 Event Output Enable + 8 + 1 + + + OVFEO + Overflow Event Output Enable + 15 + 1 + + + + + INTENCLR + MODE0 Interrupt Enable Clear + 0x8 + 16 + 0x0000 + + + PER0 + Periodic Interval 0 Interrupt Enable + 0 + 1 + + + PER1 + Periodic Interval 1 Interrupt Enable + 1 + 1 + + + PER2 + Periodic Interval 2 Interrupt Enable + 2 + 1 + + + PER3 + Periodic Interval 3 Interrupt Enable + 3 + 1 + + + PER4 + Periodic Interval 4 Interrupt Enable + 4 + 1 + + + PER5 + Periodic Interval 5 Interrupt Enable + 5 + 1 + + + PER6 + Periodic Interval 6 Interrupt Enable + 6 + 1 + + + PER7 + Periodic Interval 7 Interrupt Enable + 7 + 1 + + + CMP0 + Compare 0 Interrupt Enable + 8 + 1 + + + OVF + Overflow Interrupt Enable + 15 + 1 + + + + + INTENSET + MODE0 Interrupt Enable Set + 0xA + 16 + 0x0000 + + + PER0 + Periodic Interval 0 Interrupt Enable + 0 + 1 + + + PER1 + Periodic Interval 1 Interrupt Enable + 1 + 1 + + + PER2 + Periodic Interval 2 Interrupt Enable + 2 + 1 + + + PER3 + Periodic Interval 3 Interrupt Enable + 3 + 1 + + + PER4 + Periodic Interval 4 Interrupt Enable + 4 + 1 + + + PER5 + Periodic Interval 5 Interrupt Enable + 5 + 1 + + + PER6 + Periodic Interval 6 Interrupt Enable + 6 + 1 + + + PER7 + Periodic Interval 7 Interrupt Enable + 7 + 1 + + + CMP0 + Compare 0 Interrupt Enable + 8 + 1 + + + OVF + Overflow Interrupt Enable + 15 + 1 + + + + + INTFLAG + MODE0 Interrupt Flag Status and Clear + 0xC + 16 + 0x0000 + + + PER0 + Periodic Interval 0 + 0 + 1 + + + PER1 + Periodic Interval 1 + 1 + 1 + + + PER2 + Periodic Interval 2 + 2 + 1 + + + PER3 + Periodic Interval 3 + 3 + 1 + + + PER4 + Periodic Interval 4 + 4 + 1 + + + PER5 + Periodic Interval 5 + 5 + 1 + + + PER6 + Periodic Interval 6 + 6 + 1 + + + PER7 + Periodic Interval 7 + 7 + 1 + + + CMP0 + Compare 0 + 8 + 1 + + + OVF + Overflow + 15 + 1 + + + + + DBGCTRL + Debug Control + 0xE + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + SYNCBUSY + MODE0 Synchronization Busy Status + 0x10 + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Busy + 0 + 1 + + + ENABLE + Enable Bit Busy + 1 + 1 + + + FREQCORR + FREQCORR Register Busy + 2 + 1 + + + COUNT + COUNT Register Busy + 3 + 1 + + + COMP0 + COMP 0 Register Busy + 5 + 1 + + + COUNTSYNC + Count Read Synchronization Enable Bit Busy + 15 + 1 + + + + + FREQCORR + Frequency Correction + 0x14 + 8 + 0x00 + + + VALUE + Correction Value + 0 + 7 + + + SIGN + Correction Sign + 7 + 1 + + + + + COUNT + MODE0 Counter Value + 0x18 + 32 + 0x00000000 + + + COUNT + Counter Value + 0 + 32 + + + + + COMP + MODE0 Compare n Value + 0x20 + 32 + 0x00000000 + + + COMP + Compare Value + 0 + 32 + + + + + + MODE1 + 16-bit Counter with Two 16-bit Compares + MODE0 + RtcMode1 + 0x0 + + CTRLA + MODE1 Control A + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 2 + + MODESelect + + COUNT32 + Mode 0: 32-bit Counter + 0 + + + COUNT16 + Mode 1: 16-bit Counter + 1 + + + CLOCK + Mode 2: Clock/Calendar + 2 + + + + + PRESCALER + Prescaler + 8 + 4 + + PRESCALERSelect + + OFF + CLK_RTC_CNT = GCLK_RTC/1 + 0 + + + DIV1 + CLK_RTC_CNT = GCLK_RTC/1 + 1 + + + DIV2 + CLK_RTC_CNT = GCLK_RTC/2 + 2 + + + DIV4 + CLK_RTC_CNT = GCLK_RTC/4 + 3 + + + DIV8 + CLK_RTC_CNT = GCLK_RTC/8 + 4 + + + DIV16 + CLK_RTC_CNT = GCLK_RTC/16 + 5 + + + DIV32 + CLK_RTC_CNT = GCLK_RTC/32 + 6 + + + DIV64 + CLK_RTC_CNT = GCLK_RTC/64 + 7 + + + DIV128 + CLK_RTC_CNT = GCLK_RTC/128 + 8 + + + DIV256 + CLK_RTC_CNT = GCLK_RTC/256 + 9 + + + DIV512 + CLK_RTC_CNT = GCLK_RTC/512 + 0xA + + + DIV1024 + CLK_RTC_CNT = GCLK_RTC/1024 + 0xB + + + + + COUNTSYNC + Count Read Synchronization Enable + 15 + 1 + + + + + EVCTRL + MODE1 Event Control + 0x4 + 32 + 0x00000000 + + + PEREO0 + Periodic Interval 0 Event Output Enable + 0 + 1 + + + PEREO1 + Periodic Interval 1 Event Output Enable + 1 + 1 + + + PEREO2 + Periodic Interval 2 Event Output Enable + 2 + 1 + + + PEREO3 + Periodic Interval 3 Event Output Enable + 3 + 1 + + + PEREO4 + Periodic Interval 4 Event Output Enable + 4 + 1 + + + PEREO5 + Periodic Interval 5 Event Output Enable + 5 + 1 + + + PEREO6 + Periodic Interval 6 Event Output Enable + 6 + 1 + + + PEREO7 + Periodic Interval 7 Event Output Enable + 7 + 1 + + + CMPEO0 + Compare 0 Event Output Enable + 8 + 1 + + + CMPEO1 + Compare 1 Event Output Enable + 9 + 1 + + + OVFEO + Overflow Event Output Enable + 15 + 1 + + + + + INTENCLR + MODE1 Interrupt Enable Clear + 0x8 + 16 + 0x0000 + + + PER0 + Periodic Interval 0 Interrupt Enable + 0 + 1 + + + PER1 + Periodic Interval 1 Interrupt Enable + 1 + 1 + + + PER2 + Periodic Interval 2 Interrupt Enable + 2 + 1 + + + PER3 + Periodic Interval 3 Interrupt Enable + 3 + 1 + + + PER4 + Periodic Interval 4 Interrupt Enable + 4 + 1 + + + PER5 + Periodic Interval 5 Interrupt Enable + 5 + 1 + + + PER6 + Periodic Interval 6 Interrupt Enable + 6 + 1 + + + PER7 + Periodic Interval 7 Interrupt Enable + 7 + 1 + + + CMP0 + Compare 0 Interrupt Enable + 8 + 1 + + + CMP1 + Compare 1 Interrupt Enable + 9 + 1 + + + OVF + Overflow Interrupt Enable + 15 + 1 + + + + + INTENSET + MODE1 Interrupt Enable Set + 0xA + 16 + 0x0000 + + + PER0 + Periodic Interval 0 Interrupt Enable + 0 + 1 + + + PER1 + Periodic Interval 1 Interrupt Enable + 1 + 1 + + + PER2 + Periodic Interval 2 Interrupt Enable + 2 + 1 + + + PER3 + Periodic Interval 3 Interrupt Enable + 3 + 1 + + + PER4 + Periodic Interval 4 Interrupt Enable + 4 + 1 + + + PER5 + Periodic Interval 5 Interrupt Enable + 5 + 1 + + + PER6 + Periodic Interval 6 Interrupt Enable + 6 + 1 + + + PER7 + Periodic Interval 7 Interrupt Enable + 7 + 1 + + + CMP0 + Compare 0 Interrupt Enable + 8 + 1 + + + CMP1 + Compare 1 Interrupt Enable + 9 + 1 + + + OVF + Overflow Interrupt Enable + 15 + 1 + + + + + INTFLAG + MODE1 Interrupt Flag Status and Clear + 0xC + 16 + 0x0000 + + + PER0 + Periodic Interval 0 + 0 + 1 + + + PER1 + Periodic Interval 1 + 1 + 1 + + + PER2 + Periodic Interval 2 + 2 + 1 + + + PER3 + Periodic Interval 3 + 3 + 1 + + + PER4 + Periodic Interval 4 + 4 + 1 + + + PER5 + Periodic Interval 5 + 5 + 1 + + + PER6 + Periodic Interval 6 + 6 + 1 + + + PER7 + Periodic Interval 7 + 7 + 1 + + + CMP0 + Compare 0 + 8 + 1 + + + CMP1 + Compare 1 + 9 + 1 + + + OVF + Overflow + 15 + 1 + + + + + DBGCTRL + Debug Control + 0xE + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + SYNCBUSY + MODE1 Synchronization Busy Status + 0x10 + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Bit Busy + 0 + 1 + + + ENABLE + Enable Bit Busy + 1 + 1 + + + FREQCORR + FREQCORR Register Busy + 2 + 1 + + + COUNT + COUNT Register Busy + 3 + 1 + + + PER + PER Register Busy + 4 + 1 + + + COMP0 + COMP 0 Register Busy + 5 + 1 + + + COMP1 + COMP 1 Register Busy + 6 + 1 + + + COUNTSYNC + Count Read Synchronization Enable Bit Busy + 15 + 1 + + + + + FREQCORR + Frequency Correction + 0x14 + 8 + 0x00 + + + VALUE + Correction Value + 0 + 7 + + + SIGN + Correction Sign + 7 + 1 + + + + + COUNT + MODE1 Counter Value + 0x18 + 16 + 0x0000 + + + COUNT + Counter Value + 0 + 16 + + + + + PER + MODE1 Counter Period + 0x1C + 16 + 0x0000 + + + PER + Counter Period + 0 + 16 + + + + + 2 + 2 + COMP[%s] + MODE1 Compare n Value + 0x20 + 16 + 0x0000 + + + COMP + Compare Value + 0 + 16 + + + + + + MODE2 + Clock/Calendar with Alarm + MODE0 + RtcMode2 + 0x0 + + CTRLA + MODE2 Control A + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 2 + + MODESelect + + COUNT32 + Mode 0: 32-bit Counter + 0 + + + COUNT16 + Mode 1: 16-bit Counter + 1 + + + CLOCK + Mode 2: Clock/Calendar + 2 + + + + + CLKREP + Clock Representation + 6 + 1 + + + MATCHCLR + Clear on Match + 7 + 1 + + + PRESCALER + Prescaler + 8 + 4 + + PRESCALERSelect + + OFF + CLK_RTC_CNT = GCLK_RTC/1 + 0x0 + + + DIV1 + CLK_RTC_CNT = GCLK_RTC/1 + 0x1 + + + DIV2 + CLK_RTC_CNT = GCLK_RTC/2 + 0x2 + + + DIV4 + CLK_RTC_CNT = GCLK_RTC/4 + 0x3 + + + DIV8 + CLK_RTC_CNT = GCLK_RTC/8 + 0x4 + + + DIV16 + CLK_RTC_CNT = GCLK_RTC/16 + 0x5 + + + DIV32 + CLK_RTC_CNT = GCLK_RTC/32 + 0x6 + + + DIV64 + CLK_RTC_CNT = GCLK_RTC/64 + 0x7 + + + DIV128 + CLK_RTC_CNT = GCLK_RTC/128 + 0x8 + + + DIV256 + CLK_RTC_CNT = GCLK_RTC/256 + 0x9 + + + DIV512 + CLK_RTC_CNT = GCLK_RTC/512 + 0xA + + + DIV1024 + CLK_RTC_CNT = GCLK_RTC/1024 + 0xB + + + + + CLOCKSYNC + Clock Read Synchronization Enable + 15 + 1 + + + + + EVCTRL + MODE2 Event Control + 0x4 + 32 + 0x00000000 + + + PEREO0 + Periodic Interval 0 Event Output Enable + 0 + 1 + + + PEREO1 + Periodic Interval 1 Event Output Enable + 1 + 1 + + + PEREO2 + Periodic Interval 2 Event Output Enable + 2 + 1 + + + PEREO3 + Periodic Interval 3 Event Output Enable + 3 + 1 + + + PEREO4 + Periodic Interval 4 Event Output Enable + 4 + 1 + + + PEREO5 + Periodic Interval 5 Event Output Enable + 5 + 1 + + + PEREO6 + Periodic Interval 6 Event Output Enable + 6 + 1 + + + PEREO7 + Periodic Interval 7 Event Output Enable + 7 + 1 + + + ALARMEO0 + Alarm 0 Event Output Enable + 8 + 1 + + + OVFEO + Overflow Event Output Enable + 15 + 1 + + + + + INTENCLR + MODE2 Interrupt Enable Clear + 0x8 + 16 + 0x0000 + + + PER0 + Periodic Interval 0 Interrupt Enable + 0 + 1 + + + PER1 + Periodic Interval 1 Interrupt Enable + 1 + 1 + + + PER2 + Periodic Interval 2 Interrupt Enable + 2 + 1 + + + PER3 + Periodic Interval 3 Interrupt Enable + 3 + 1 + + + PER4 + Periodic Interval 4 Interrupt Enable + 4 + 1 + + + PER5 + Periodic Interval 5 Interrupt Enable + 5 + 1 + + + PER6 + Periodic Interval 6 Interrupt Enable + 6 + 1 + + + PER7 + Periodic Interval 7 Interrupt Enable + 7 + 1 + + + ALARM0 + Alarm 0 Interrupt Enable + 8 + 1 + + + OVF + Overflow Interrupt Enable + 15 + 1 + + + + + INTENSET + MODE2 Interrupt Enable Set + 0xA + 16 + 0x0000 + + + PER0 + Periodic Interval 0 Enable + 0 + 1 + + + PER1 + Periodic Interval 1 Enable + 1 + 1 + + + PER2 + Periodic Interval 2 Enable + 2 + 1 + + + PER3 + Periodic Interval 3 Enable + 3 + 1 + + + PER4 + Periodic Interval 4 Enable + 4 + 1 + + + PER5 + Periodic Interval 5 Enable + 5 + 1 + + + PER6 + Periodic Interval 6 Enable + 6 + 1 + + + PER7 + Periodic Interval 7 Enable + 7 + 1 + + + ALARM0 + Alarm 0 Interrupt Enable + 8 + 1 + + + OVF + Overflow Interrupt Enable + 15 + 1 + + + + + INTFLAG + MODE2 Interrupt Flag Status and Clear + 0xC + 16 + 0x0000 + + + PER0 + Periodic Interval 0 + 0 + 1 + + + PER1 + Periodic Interval 1 + 1 + 1 + + + PER2 + Periodic Interval 2 + 2 + 1 + + + PER3 + Periodic Interval 3 + 3 + 1 + + + PER4 + Periodic Interval 4 + 4 + 1 + + + PER5 + Periodic Interval 5 + 5 + 1 + + + PER6 + Periodic Interval 6 + 6 + 1 + + + PER7 + Periodic Interval 7 + 7 + 1 + + + ALARM0 + Alarm 0 + 8 + 1 + + + OVF + Overflow + 15 + 1 + + + + + DBGCTRL + Debug Control + 0xE + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + SYNCBUSY + MODE2 Synchronization Busy Status + 0x10 + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Bit Busy + 0 + 1 + + + ENABLE + Enable Bit Busy + 1 + 1 + + + FREQCORR + FREQCORR Register Busy + 2 + 1 + + + CLOCK + CLOCK Register Busy + 3 + 1 + + + ALARM0 + ALARM 0 Register Busy + 5 + 1 + + + MASK0 + MASK 0 Register Busy + 11 + 1 + + + CLOCKSYNC + Clock Read Synchronization Enable Bit Busy + 15 + 1 + + + + + FREQCORR + Frequency Correction + 0x14 + 8 + 0x00 + + + VALUE + Correction Value + 0 + 7 + + + SIGN + Correction Sign + 7 + 1 + + + + + CLOCK + MODE2 Clock Value + 0x18 + 32 + 0x00000000 + + + SECOND + Second + 0 + 6 + + + MINUTE + Minute + 6 + 6 + + + HOUR + Hour + 12 + 5 + + HOURSelect + + AM + AM when CLKREP in 12-hour + 0x00 + + + PM + PM when CLKREP in 12-hour + 0x10 + + + + + DAY + Day + 17 + 5 + + + MONTH + Month + 22 + 4 + + + YEAR + Year + 26 + 6 + + + + + ALARM + MODE2_ALARM Alarm n Value + 0x20 + 32 + 0x00000000 + + + SECOND + Second + 0 + 6 + + + MINUTE + Minute + 6 + 6 + + + HOUR + Hour + 12 + 5 + + HOURSelect + + AM + Morning hour + 0x00 + + + PM + Afternoon hour + 0x10 + + + + + DAY + Day + 17 + 5 + + + MONTH + Month + 22 + 4 + + + YEAR + Year + 26 + 6 + + + + + MASK + MODE2_ALARM Alarm n Mask + 0x24 + 8 + 0x00 + + + SEL + Alarm Mask Selection + 0 + 3 + + SELSelect + + OFF + Alarm Disabled + 0x0 + + + SS + Match seconds only + 0x1 + + + MMSS + Match seconds and minutes only + 0x2 + + + HHMMSS + Match seconds, minutes, and hours only + 0x3 + + + DDHHMMSS + Match seconds, minutes, hours, and days only + 0x4 + + + MMDDHHMMSS + Match seconds, minutes, hours, days, and months only + 0x5 + + + YYMMDDHHMMSS + Match seconds, minutes, hours, days, months, and years + 0x6 + + + + + + + + + + SERCOM0 + U22013.2.0 + Serial Communication Interface + SERCOM + SERCOM_ + 0x42000400 + + 0 + 0x31 + registers + + + + I2CM + I2C Master Mode + SercomI2cm + 0x0 + + CTRLA + I2CM Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run in Standby + 7 + 1 + + + PINOUT + Pin Usage + 16 + 1 + + + SDAHOLD + SDA Hold Time + 20 + 2 + + SDAHOLDSelect + + DISABLE + Disabled + 0x0 + + + 75NS + 50-100ns hold time + 0x1 + + + 450NS + 300-600ns hold time + 0x2 + + + 600NS + 400-800ns hold time + 0x3 + + + + + MEXTTOEN + Master SCL Low Extend Timeout + 22 + 1 + + + SEXTTOEN + Slave SCL Low Extend Timeout + 23 + 1 + + + SPEED + Transfer Speed + 24 + 2 + + SPEEDSelect + + STANDARD_AND_FAST_MODE + Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz + 0x0 + + + FASTPLUS_MODE + Fast-mode Plus Upto 1MHz + 0x1 + + + HIGH_SPEED_MODE + High-speed mode Upto 3.4MHz + 0x2 + + + + + SCLSM + SCL Clock Stretch Mode + 27 + 1 + + + INACTOUT + Inactive Time-Out + 28 + 2 + + INACTOUTSelect + + DISABLE + Disabled + 0x0 + + + 55US + 5-6 SCL Time-Out(50-60us) + 0x1 + + + 105US + 10-11 SCL Time-Out(100-110us) + 0x2 + + + 205US + 20-21 SCL Time-Out(200-210us) + 0x3 + + + + + LOWTOUTEN + SCL Low Timeout Enable + 30 + 1 + + + + + CTRLB + I2CM Control B + 0x4 + 32 + 0x00000000 + + + SMEN + Smart Mode Enable + 8 + 1 + + + QCEN + Quick Command Enable + 9 + 1 + + + CMD + Command + 16 + 2 + + + ACKACT + Acknowledge Action + 18 + 1 + + + + + BAUD + I2CM Baud Rate + 0xC + 32 + 0x00000000 + + + BAUD + Baud Rate Value + 0 + 8 + + + BAUDLOW + Baud Rate Value Low + 8 + 8 + + + HSBAUD + High Speed Baud Rate Value + 16 + 8 + + + HSBAUDLOW + High Speed Baud Rate Value Low + 24 + 8 + + + + + INTENCLR + I2CM Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + MB + Master On Bus Interrupt Disable + 0 + 1 + + + SB + Slave On Bus Interrupt Disable + 1 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + I2CM Interrupt Enable Set + 0x16 + 8 + 0x00 + + + MB + Master On Bus Interrupt Enable + 0 + 1 + + + SB + Slave On Bus Interrupt Enable + 1 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + I2CM Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + MB + Master On Bus Interrupt + 0 + 1 + + + SB + Slave On Bus Interrupt + 1 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + I2CM Status + 0x1A + 16 + 0x0000 + + + BUSERR + Bus Error + 0 + 1 + + + ARBLOST + Arbitration Lost + 1 + 1 + + + RXNACK + Received Not Acknowledge + 2 + 1 + + + BUSSTATE + Bus State + 4 + 2 + + + LOWTOUT + SCL Low Timeout + 6 + 1 + + + CLKHOLD + Clock Hold + 7 + 1 + + + MEXTTOUT + Master SCL Low Extend Timeout + 8 + 1 + + + SEXTTOUT + Slave SCL Low Extend Timeout + 9 + 1 + + + LENERR + Length Error + 10 + 1 + + + + + SYNCBUSY + I2CM Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + SYSOP + System Operation Synchronization Busy + 2 + 1 + + + + + ADDR + I2CM Address + 0x24 + 32 + 0x00000000 + + + ADDR + Address Value + 0 + 11 + + + LENEN + Length Enable + 13 + 1 + + + HS + High Speed Mode + 14 + 1 + + + TENBITEN + Ten Bit Addressing Enable + 15 + 1 + + + LEN + Length + 16 + 8 + + + + + DATA + I2CM Data + 0x28 + 8 + 0x00 + + + DATA + Data Value + 0 + 8 + + + + + DBGCTRL + I2CM Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + I2CS + I2C Slave Mode + I2CM + SercomI2cs + 0x0 + + CTRLA + I2CS Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + PINOUT + Pin Usage + 16 + 1 + + + SDAHOLD + SDA Hold Time + 20 + 2 + + SDAHOLDSelect + + DISABLE + Disabled + 0x0 + + + 75NS + 50-100ns hold time + 0x1 + + + 450NS + 300-600ns hold time + 0x2 + + + 600NS + 400-800ns hold time + 0x3 + + + + + SEXTTOEN + Slave SCL Low Extend Timeout + 23 + 1 + + + SPEED + Transfer Speed + 24 + 2 + + SPEEDSelect + + STANDARD_AND_FAST_MODE + Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz + 0x0 + + + FASTPLUS_MODE + Fast-mode Plus Upto 1MHz + 0x1 + + + HIGH_SPEED_MODE + High-speed mode Upto 3.4MHz + 0x2 + + + + + SCLSM + SCL Clock Stretch Mode + 27 + 1 + + + LOWTOUTEN + SCL Low Timeout Enable + 30 + 1 + + + + + CTRLB + I2CS Control B + 0x4 + 32 + 0x00000000 + + + SMEN + Smart Mode Enable + 8 + 1 + + + GCMD + PMBus Group Command + 9 + 1 + + + AACKEN + Automatic Address Acknowledge + 10 + 1 + + + AMODE + Address Mode + 14 + 2 + + + CMD + Command + 16 + 2 + + + ACKACT + Acknowledge Action + 18 + 1 + + + + + INTENCLR + I2CS Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + PREC + Stop Received Interrupt Disable + 0 + 1 + + + AMATCH + Address Match Interrupt Disable + 1 + 1 + + + DRDY + Data Interrupt Disable + 2 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + I2CS Interrupt Enable Set + 0x16 + 8 + 0x00 + + + PREC + Stop Received Interrupt Enable + 0 + 1 + + + AMATCH + Address Match Interrupt Enable + 1 + 1 + + + DRDY + Data Interrupt Enable + 2 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + I2CS Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + PREC + Stop Received Interrupt + 0 + 1 + + + AMATCH + Address Match Interrupt + 1 + 1 + + + DRDY + Data Interrupt + 2 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + I2CS Status + 0x1A + 16 + 0x0000 + + + BUSERR + Bus Error + 0 + 1 + + + COLL + Transmit Collision + 1 + 1 + + + RXNACK + Received Not Acknowledge + 2 + 1 + + + DIR + Read/Write Direction + 3 + 1 + + + SR + Repeated Start + 4 + 1 + + + LOWTOUT + SCL Low Timeout + 6 + 1 + + + CLKHOLD + Clock Hold + 7 + 1 + + + SEXTTOUT + Slave SCL Low Extend Timeout + 9 + 1 + + + HS + High Speed + 10 + 1 + + + + + SYNCBUSY + I2CS Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + + + ADDR + I2CS Address + 0x24 + 32 + 0x00000000 + + + GENCEN + General Call Address Enable + 0 + 1 + + + ADDR + Address Value + 1 + 10 + + + TENBITEN + Ten Bit Addressing Enable + 15 + 1 + + + ADDRMASK + Address Mask + 17 + 10 + + + + + DATA + I2CS Data + 0x28 + 8 + 0x00 + + + DATA + Data Value + 0 + 8 + + + + + + SPIS + SPI Slave Mode + I2CM + SercomSpis + 0x0 + + CTRLA + SPIS Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + IBON + Immediate Buffer Overflow Notification + 8 + 1 + + + DOPO + Data Out Pinout + 16 + 2 + + DOPOSelect + + PAD0 + DO on PAD[0], SCK on PAD[1] and SS on PAD[2] + 0x0 + + + PAD1 + DO on PAD[2], SCK on PAD[3] and SS on PAD[1] + 0x1 + + + PAD2 + DO on PAD[3], SCK on PAD[1] and SS on PAD[2] + 0x2 + + + PAD3 + DO on PAD[0], SCK on PAD[3] and SS on PAD[1] + 0x3 + + + + + DIPO + Data In Pinout + 20 + 2 + + DIPOSelect + + PAD0 + SERCOM PAD[0] + 0x0 + + + PAD1 + SERCOM PAD[1] + 0x1 + + + PAD2 + SERCOM PAD[2] + 0x2 + + + PAD3 + SERCOM PAD[3] + 0x3 + + + + + FORM + Frame Format + 24 + 4 + + FORMSelect + + SPI_FRAME + SPI Frame + 0x0 + + + SPI_FRAME_WITH_ADDR + SPI Frame with Addr + 0x2 + + + + + CPHA + Clock Phase + 28 + 1 + + CPHASelect + + LEADING_EDGE + The data is sampled on a leading SCK edge and changed on a trailing SCK edge + 0x0 + + + TRAILING_EDGE + The data is sampled on a trailing SCK edge and changed on a leading SCK edge + 0x1 + + + + + CPOL + Clock Polarity + 29 + 1 + + CPOLSelect + + IDLE_LOW + SCK is low when idle + 0x0 + + + IDLE_HIGH + SCK is high when idle + 0x1 + + + + + DORD + Data Order + 30 + 1 + + DORDSelect + + MSB + MSB is transferred first + 0x0 + + + LSB + LSB is transferred first + 0x1 + + + + + + + CTRLB + SPIS Control B + 0x4 + 32 + 0x00000000 + + + CHSIZE + Character Size + 0 + 3 + + CHSIZESelect + + 8_BIT + 8 bits + 0x0 + + + 9_BIT + 9 bits + 0x1 + + + + + PLOADEN + Data Preload Enable + 6 + 1 + + + SSDE + Slave Select Low Detect Enable + 9 + 1 + + + MSSEN + Master Slave Select Enable + 13 + 1 + + + AMODE + Address Mode + 14 + 2 + + AMODESelect + + MASK + SPI Address mask + 0x0 + + + 2_ADDRESSES + Two unique Addressess + 0x1 + + + RANGE + Address Range + 0x2 + + + + + RXEN + Receiver Enable + 17 + 1 + + + + + BAUD + SPIS Baud Rate + 0xC + 8 + 0x00 + + + BAUD + Baud Rate Value + 0 + 8 + + + + + INTENCLR + SPIS Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Disable + 0 + 1 + + + TXC + Transmit Complete Interrupt Disable + 1 + 1 + + + RXC + Receive Complete Interrupt Disable + 2 + 1 + + + SSL + Slave Select Low Interrupt Disable + 3 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + SPIS Interrupt Enable Set + 0x16 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Enable + 0 + 1 + + + TXC + Transmit Complete Interrupt Enable + 1 + 1 + + + RXC + Receive Complete Interrupt Enable + 2 + 1 + + + SSL + Slave Select Low Interrupt Enable + 3 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + SPIS Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt + 0 + 1 + + + TXC + Transmit Complete Interrupt + 1 + 1 + + + RXC + Receive Complete Interrupt + 2 + 1 + + + SSL + Slave Select Low Interrupt Flag + 3 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + SPIS Status + 0x1A + 16 + 0x0000 + + + BUFOVF + Buffer Overflow + 2 + 1 + + + + + SYNCBUSY + SPIS Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + CTRLB + CTRLB Synchronization Busy + 2 + 1 + + + + + ADDR + SPIS Address + 0x24 + 32 + 0x00000000 + + + ADDR + Address Value + 0 + 8 + + + ADDRMASK + Address Mask + 16 + 8 + + + + + DATA + SPIS Data + 0x28 + 32 + 0x00000000 + + + DATA + Data Value + 0 + 9 + + + + + DBGCTRL + SPIS Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + SPIM + SPI Master Mode + I2CM + SercomSpim + 0x0 + + CTRLA + SPIM Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + IBON + Immediate Buffer Overflow Notification + 8 + 1 + + + DOPO + Data Out Pinout + 16 + 2 + + DOPOSelect + + PAD0 + DO on PAD[0], SCK on PAD[1] and SS on PAD[2] + 0x0 + + + PAD1 + DO on PAD[2], SCK on PAD[3] and SS on PAD[1] + 0x1 + + + PAD2 + DO on PAD[3], SCK on PAD[1] and SS on PAD[2] + 0x2 + + + PAD3 + DO on PAD[0], SCK on PAD[3] and SS on PAD[1] + 0x3 + + + + + DIPO + Data In Pinout + 20 + 2 + + DIPOSelect + + PAD0 + SERCOM PAD[0] + 0x0 + + + PAD1 + SERCOM PAD[1] + 0x1 + + + PAD2 + SERCOM PAD[2] + 0x2 + + + PAD3 + SERCOM PAD[3] + 0x3 + + + + + FORM + Frame Format + 24 + 4 + + FORMSelect + + SPI_FRAME + SPI Frame + 0x0 + + + SPI_FRAME_WITH_ADDR + SPI Frame with Addr + 0x2 + + + + + CPHA + Clock Phase + 28 + 1 + + CPHASelect + + LEADING_EDGE + The data is sampled on a leading SCK edge and changed on a trailing SCK edge + 0x0 + + + TRAILING_EDGE + The data is sampled on a trailing SCK edge and changed on a leading SCK edge + 0x1 + + + + + CPOL + Clock Polarity + 29 + 1 + + CPOLSelect + + IDLE_LOW + SCK is low when idle + 0x0 + + + IDLE_HIGH + SCK is high when idle + 0x1 + + + + + DORD + Data Order + 30 + 1 + + DORDSelect + + MSB + MSB is transferred first + 0x0 + + + LSB + LSB is transferred first + 0x1 + + + + + + + CTRLB + SPIM Control B + 0x4 + 32 + 0x00000000 + + + CHSIZE + Character Size + 0 + 3 + + CHSIZESelect + + 8_BIT + 8 bits + 0x0 + + + 9_BIT + 9 bits + 0x1 + + + + + PLOADEN + Data Preload Enable + 6 + 1 + + + SSDE + Slave Select Low Detect Enable + 9 + 1 + + + MSSEN + Master Slave Select Enable + 13 + 1 + + + AMODE + Address Mode + 14 + 2 + + AMODESelect + + MASK + SPI Address mask + 0x0 + + + 2_ADDRESSES + Two unique Addressess + 0x1 + + + RANGE + Address Range + 0x2 + + + + + RXEN + Receiver Enable + 17 + 1 + + + + + BAUD + SPIM Baud Rate + 0xC + 8 + 0x00 + + + BAUD + Baud Rate Value + 0 + 8 + + + + + INTENCLR + SPIM Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Disable + 0 + 1 + + + TXC + Transmit Complete Interrupt Disable + 1 + 1 + + + RXC + Receive Complete Interrupt Disable + 2 + 1 + + + SSL + Slave Select Low Interrupt Disable + 3 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + SPIM Interrupt Enable Set + 0x16 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Enable + 0 + 1 + + + TXC + Transmit Complete Interrupt Enable + 1 + 1 + + + RXC + Receive Complete Interrupt Enable + 2 + 1 + + + SSL + Slave Select Low Interrupt Enable + 3 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + SPIM Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt + 0 + 1 + + + TXC + Transmit Complete Interrupt + 1 + 1 + + + RXC + Receive Complete Interrupt + 2 + 1 + + + SSL + Slave Select Low Interrupt Flag + 3 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + SPIM Status + 0x1A + 16 + 0x0000 + + + BUFOVF + Buffer Overflow + 2 + 1 + + + + + SYNCBUSY + SPIM Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + CTRLB + CTRLB Synchronization Busy + 2 + 1 + + + + + ADDR + SPIM Address + 0x24 + 32 + 0x00000000 + + + ADDR + Address Value + 0 + 8 + + + ADDRMASK + Address Mask + 16 + 8 + + + + + DATA + SPIM Data + 0x28 + 32 + 0x00000000 + + + DATA + Data Value + 0 + 9 + + + + + DBGCTRL + SPIM Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + USART_EXT + USART EXTERNAL CLOCK Mode + I2CM + SercomUsart_ext + 0x0 + + CTRLA + USART_EXT Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + IBON + Immediate Buffer Overflow Notification + 8 + 1 + + + SAMPR + Sample + 13 + 3 + + SAMPRSelect + + 16X_ARITHMETIC + 16x over-sampling using arithmetic baudrate generation + 0x0 + + + 16X_FRACTIONAL + 16x over-sampling using fractional baudrate generation + 0x1 + + + 8X_ARITHMETIC + 8x over-sampling using arithmetic baudrate generation + 0x2 + + + 8X_FRACTIONAL + 8x over-sampling using fractional baudrate generation + 0x3 + + + 3X_ARITHMETIC + 3x over-sampling using arithmetic baudrate generation + 0x4 + + + + + TXPO + Transmit Data Pinout + 16 + 2 + + TXPOSelect + + PAD0 + SERCOM PAD[0] is used for data transmission + 0x0 + + + PAD2 + SERCOM PAD[2] is used for data transmission + 0x1 + + + + + RXPO + Receive Data Pinout + 20 + 2 + + RXPOSelect + + PAD0 + SERCOM PAD[0] is used for data reception + 0x0 + + + PAD1 + SERCOM PAD[1] is used for data reception + 0x1 + + + PAD2 + SERCOM PAD[2] is used for data reception + 0x2 + + + PAD3 + SERCOM PAD[3] is used for data reception + 0x3 + + + + + SAMPA + Sample Adjustment + 22 + 2 + + + FORM + Frame Format + 24 + 4 + + FORMSelect + + USART_FRAME_NO_PARITY + USART frame + 0x0 + + + USART_FRAME_WITH_PARITY + USART frame with parity + 0x1 + + + USART_FRAME_LIN_MASTER_MODE + LIN Master - Break and sync generation + 0x2 + + + USART_FRAME_AUTO_BAUD_NO_PARITY + Auto-baud - break detection and auto-baud + 0x4 + + + USART_FRAME_AUTO_BAUD_WITH_PARITY + Auto-baud - break detection and auto-baud with parity + 0x5 + + + + + CMODE + Communication Mode + 28 + 1 + + CMODESelect + + ASYNC + Asynchronous Communication + 0x0 + + + SYNC + Synchronous Communication + 0x1 + + + + + CPOL + Clock Polarity + 29 + 1 + + CPOLSelect + + IDLE_LOW + TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge + 0x0 + + + IDLE_HIGH + TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge + 0x1 + + + + + DORD + Data Order + 30 + 1 + + DORDSelect + + MSB + MSB is transmitted first + 0x0 + + + LSB + LSB is transmitted first + 0x1 + + + + + + + CTRLB + USART_EXT Control B + 0x4 + 32 + 0x00000000 + + + CHSIZE + Character Size + 0 + 3 + + CHSIZESelect + + 8_BIT + 8 Bits + 0x0 + + + 9_BIT + 9 Bits + 0x1 + + + 5_BIT + 5 Bits + 0x5 + + + 6_BIT + 6 Bits + 0x6 + + + 7_BIT + 7 Bits + 0x7 + + + + + SBMODE + Stop Bit Mode + 6 + 1 + + SBMODESelect + + 1_BIT + One Stop Bit + 0x0 + + + 2_BIT + Two Stop Bits + 0x1 + + + + + COLDEN + Collision Detection Enable + 8 + 1 + + + SFDE + Start of Frame Detection Enable + 9 + 1 + + + ENC + Encoding Format + 10 + 1 + + + PMODE + Parity Mode + 13 + 1 + + PMODESelect + + EVEN + Even Parity + 0x0 + + + ODD + Odd Parity + 0x1 + + + + + TXEN + Transmitter Enable + 16 + 1 + + + RXEN + Receiver Enable + 17 + 1 + + + LINCMD + LIN Command + 24 + 2 + + + + + CTRLC + USART_EXT Control C + 0x8 + 32 + 0x00000000 + + + GTIME + RS485 Guard Time + 0 + 3 + + + BRKLEN + LIN Master Break Length + 8 + 2 + + + HDRDLY + LIN Master Header Delay + 10 + 2 + + + + + BAUD + USART_EXT Baud Rate + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 16 + + + + + BAUD_FRAC_MODE + USART_EXT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 13 + + + FP + Fractional Part + 13 + 3 + + + + + BAUD_FRACFP_MODE + USART_EXT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 13 + + + FP + Fractional Part + 13 + 3 + + + + + BAUD_USARTFP_MODE + USART_EXT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 16 + + + + + RXPL + USART_EXT Receive Pulse Length + 0xE + 8 + 0x00 + + + RXPL + Receive Pulse Length + 0 + 8 + + + + + INTENCLR + USART_EXT Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Disable + 0 + 1 + + + TXC + Transmit Complete Interrupt Disable + 1 + 1 + + + RXC + Receive Complete Interrupt Disable + 2 + 1 + + + RXS + Receive Start Interrupt Disable + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt Disable + 4 + 1 + + + RXBRK + Break Received Interrupt Disable + 5 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + USART_EXT Interrupt Enable Set + 0x16 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Enable + 0 + 1 + + + TXC + Transmit Complete Interrupt Enable + 1 + 1 + + + RXC + Receive Complete Interrupt Enable + 2 + 1 + + + RXS + Receive Start Interrupt Enable + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt Enable + 4 + 1 + + + RXBRK + Break Received Interrupt Enable + 5 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + USART_EXT Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt + 0 + 1 + + + TXC + Transmit Complete Interrupt + 1 + 1 + + + RXC + Receive Complete Interrupt + 2 + 1 + + + RXS + Receive Start Interrupt + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt + 4 + 1 + + + RXBRK + Break Received Interrupt + 5 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + USART_EXT Status + 0x1A + 16 + 0x0000 + + + PERR + Parity Error + 0 + 1 + + + FERR + Frame Error + 1 + 1 + + + BUFOVF + Buffer Overflow + 2 + 1 + + + CTS + Clear To Send + 3 + 1 + + + ISF + Inconsistent Sync Field + 4 + 1 + + + COLL + Collision Detected + 5 + 1 + + + TXE + Transmitter Empty + 6 + 1 + + + + + SYNCBUSY + USART_EXT Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + CTRLB + CTRLB Synchronization Busy + 2 + 1 + + + + + DATA + USART_EXT Data + 0x28 + 16 + 0x0000 + + + DATA + Data Value + 0 + 9 + + + + + DBGCTRL + USART_EXT Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + USART_INT + USART INTERNAL CLOCK Mode + I2CM + SercomUsart_int + 0x0 + + CTRLA + USART_INT Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + IBON + Immediate Buffer Overflow Notification + 8 + 1 + + + SAMPR + Sample + 13 + 3 + + SAMPRSelect + + 16X_ARITHMETIC + 16x over-sampling using arithmetic baudrate generation + 0x0 + + + 16X_FRACTIONAL + 16x over-sampling using fractional baudrate generation + 0x1 + + + 8X_ARITHMETIC + 8x over-sampling using arithmetic baudrate generation + 0x2 + + + 8X_FRACTIONAL + 8x over-sampling using fractional baudrate generation + 0x3 + + + 3X_ARITHMETIC + 3x over-sampling using arithmetic baudrate generation + 0x4 + + + + + TXPO + Transmit Data Pinout + 16 + 2 + + TXPOSelect + + PAD0 + SERCOM PAD[0] is used for data transmission + 0x0 + + + PAD2 + SERCOM PAD[2] is used for data transmission + 0x1 + + + + + RXPO + Receive Data Pinout + 20 + 2 + + RXPOSelect + + PAD0 + SERCOM PAD[0] is used for data reception + 0x0 + + + PAD1 + SERCOM PAD[1] is used for data reception + 0x1 + + + PAD2 + SERCOM PAD[2] is used for data reception + 0x2 + + + PAD3 + SERCOM PAD[3] is used for data reception + 0x3 + + + + + SAMPA + Sample Adjustment + 22 + 2 + + + FORM + Frame Format + 24 + 4 + + FORMSelect + + USART_FRAME_NO_PARITY + USART frame + 0x0 + + + USART_FRAME_WITH_PARITY + USART frame with parity + 0x1 + + + USART_FRAME_LIN_MASTER_MODE + LIN Master - Break and sync generation + 0x2 + + + USART_FRAME_AUTO_BAUD_NO_PARITY + Auto-baud - break detection and auto-baud + 0x4 + + + USART_FRAME_AUTO_BAUD_WITH_PARITY + Auto-baud - break detection and auto-baud with parity + 0x5 + + + + + CMODE + Communication Mode + 28 + 1 + + CMODESelect + + ASYNC + Asynchronous Communication + 0x0 + + + SYNC + Synchronous Communication + 0x1 + + + + + CPOL + Clock Polarity + 29 + 1 + + CPOLSelect + + IDLE_LOW + TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge + 0x0 + + + IDLE_HIGH + TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge + 0x1 + + + + + DORD + Data Order + 30 + 1 + + DORDSelect + + MSB + MSB is transmitted first + 0x0 + + + LSB + LSB is transmitted first + 0x1 + + + + + + + CTRLB + USART_INT Control B + 0x4 + 32 + 0x00000000 + + + CHSIZE + Character Size + 0 + 3 + + CHSIZESelect + + 8_BIT + 8 Bits + 0x0 + + + 9_BIT + 9 Bits + 0x1 + + + 5_BIT + 5 Bits + 0x5 + + + 6_BIT + 6 Bits + 0x6 + + + 7_BIT + 7 Bits + 0x7 + + + + + SBMODE + Stop Bit Mode + 6 + 1 + + SBMODESelect + + 1_BIT + One Stop Bit + 0x0 + + + 2_BIT + Two Stop Bits + 0x1 + + + + + COLDEN + Collision Detection Enable + 8 + 1 + + + SFDE + Start of Frame Detection Enable + 9 + 1 + + + ENC + Encoding Format + 10 + 1 + + + PMODE + Parity Mode + 13 + 1 + + PMODESelect + + EVEN + Even Parity + 0x0 + + + ODD + Odd Parity + 0x1 + + + + + TXEN + Transmitter Enable + 16 + 1 + + + RXEN + Receiver Enable + 17 + 1 + + + LINCMD + LIN Command + 24 + 2 + + + + + CTRLC + USART_INT Control C + 0x8 + 32 + 0x00000000 + + + GTIME + RS485 Guard Time + 0 + 3 + + + BRKLEN + LIN Master Break Length + 8 + 2 + + + HDRDLY + LIN Master Header Delay + 10 + 2 + + + + + BAUD + USART_INT Baud Rate + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 16 + + + + + BAUD_FRAC_MODE + USART_INT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 13 + + + FP + Fractional Part + 13 + 3 + + + + + BAUD_FRACFP_MODE + USART_INT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 13 + + + FP + Fractional Part + 13 + 3 + + + + + BAUD_USARTFP_MODE + USART_INT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 16 + + + + + RXPL + USART_INT Receive Pulse Length + 0xE + 8 + 0x00 + + + RXPL + Receive Pulse Length + 0 + 8 + + + + + INTENCLR + USART_INT Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Disable + 0 + 1 + + + TXC + Transmit Complete Interrupt Disable + 1 + 1 + + + RXC + Receive Complete Interrupt Disable + 2 + 1 + + + RXS + Receive Start Interrupt Disable + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt Disable + 4 + 1 + + + RXBRK + Break Received Interrupt Disable + 5 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + USART_INT Interrupt Enable Set + 0x16 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Enable + 0 + 1 + + + TXC + Transmit Complete Interrupt Enable + 1 + 1 + + + RXC + Receive Complete Interrupt Enable + 2 + 1 + + + RXS + Receive Start Interrupt Enable + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt Enable + 4 + 1 + + + RXBRK + Break Received Interrupt Enable + 5 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + USART_INT Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt + 0 + 1 + + + TXC + Transmit Complete Interrupt + 1 + 1 + + + RXC + Receive Complete Interrupt + 2 + 1 + + + RXS + Receive Start Interrupt + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt + 4 + 1 + + + RXBRK + Break Received Interrupt + 5 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + USART_INT Status + 0x1A + 16 + 0x0000 + + + PERR + Parity Error + 0 + 1 + + + FERR + Frame Error + 1 + 1 + + + BUFOVF + Buffer Overflow + 2 + 1 + + + CTS + Clear To Send + 3 + 1 + + + ISF + Inconsistent Sync Field + 4 + 1 + + + COLL + Collision Detected + 5 + 1 + + + TXE + Transmitter Empty + 6 + 1 + + + + + SYNCBUSY + USART_INT Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + CTRLB + CTRLB Synchronization Busy + 2 + 1 + + + + + DATA + USART_INT Data + 0x28 + 16 + 0x0000 + + + DATA + Data Value + 0 + 9 + + + + + DBGCTRL + USART_INT Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + + + SERCOM1 + 0x42000800 + + + SERCOM2 + 0x42000C00 + + SERCOM2 + 11 + + + + SERCOM3 + 0x42001000 + + SERCOM3 + 12 + + + + SERCOM4 + 0x42001400 + + SERCOM4 + 13 + + + + SERCOM5 + 0x42001800 + + SERCOM5 + 14 + + + + SERCOM6 + 0x43000000 + + + SERCOM7 + 0x43000400 + + + SUPC + U21172.2.0 + Supply Controller + SUPC + SUPC_ + 0x40001800 + + 0 + 0x24 + registers + + + + INTENCLR + Interrupt Enable Clear + 0x0 + 32 + 0x00000000 + + + BODVDDRDY + BODVDD Ready + 0 + 1 + + + BODVDDDET + BODVDD Detection + 1 + 1 + + + BVDDSRDY + BODVDD Synchronization Ready + 2 + 1 + + + VREG33RDY + VREG33 Ready + 6 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x4 + 32 + 0x00000000 + + + BODVDDRDY + BODVDD Ready + 0 + 1 + + + BODVDDDET + BODVDD Detection + 1 + 1 + + + BVDDSRDY + BODVDD Synchronization Ready + 2 + 1 + + + VREG33RDY + VREG33 Ready + 6 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x8 + 32 + 0x00000000 + + + BODVDDRDY + BODVDD Ready + 0 + 1 + + + BODVDDDET + BODVDD Detection + 1 + 1 + + + BVDDSRDY + BODVDD Synchronization Ready + 2 + 1 + + + VREG33RDY + VREG33 Ready + 6 + 1 + + + + + STATUS + Power and Clocks Status + 0xC + 32 + read-only + 0x00000000 + + + BODVDDRDY + BODVDD Ready + 0 + 1 + + + BODVDDDET + BODVDD Detection + 1 + 1 + + + BVDDSRDY + BODVDD Synchronization Ready + 2 + 1 + + + VREG33RDY + VREG33 Ready + 6 + 1 + + + + + BODVDD + BODVDD Control + 0x10 + 32 + 0x00000000 + + + ENABLE + Enable + 1 + 1 + + + HYST + Hysteresis Enable + 2 + 1 + + + ACTION + Action when Threshold Crossed + 3 + 2 + + ACTIONSelect + + NONE + No action + 0x0 + + + RESET + The BODVDD generates a reset + 0x1 + + + INT + The BODVDD generates an interrupt + 0x2 + + + + + STDBYCFG + Configuration in Standby mode + 5 + 1 + + + RUNSTDBY + Run during Standby + 6 + 1 + + + ACTCFG + Configuration in Active mode + 8 + 1 + + + PSEL + Prescaler Select + 12 + 4 + + PSELSelect + + DIV2 + Divide clock by 2 + 0x0 + + + DIV4 + Divide clock by 4 + 0x1 + + + DIV8 + Divide clock by 8 + 0x2 + + + DIV16 + Divide clock by 16 + 0x3 + + + DIV32 + Divide clock by 32 + 0x4 + + + DIV64 + Divide clock by 64 + 0x5 + + + DIV128 + Divide clock by 128 + 0x6 + + + DIV256 + Divide clock by 256 + 0x7 + + + DIV512 + Divide clock by 512 + 0x8 + + + DIV1024 + Divide clock by 1024 + 0x9 + + + DIV2048 + Divide clock by 2048 + 0xA + + + DIV4096 + Divide clock by 4096 + 0xB + + + DIV8192 + Divide clock by 8192 + 0xC + + + DIV16384 + Divide clock by 16384 + 0xD + + + DIV32768 + Divide clock by 32768 + 0xE + + + DIV65536 + Divide clock by 65536 + 0xF + + + + + LEVEL + Threshold Level for VDD + 16 + 6 + + + + + VREG + VREG Control + 0x18 + 32 + 0x00000000 + + + ENABLE + Enable + 1 + 1 + + + RUNSTDBY + Run during Standby + 6 + 1 + + + + + VREF + VREF Control + 0x1C + 32 + 0x00000000 + + + TSEN + Temperature Sensor Output Enable + 1 + 1 + + + VREFOE + Voltage Reference Output Enable + 2 + 1 + + + RUNSTDBY + Run during Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + SEL + Voltage Reference Selection + 16 + 4 + + SELSelect + + 1V024 + 1.024V voltage reference typical value + 0x0 + + + 2V048 + 2.048V voltage reference typical value + 0x2 + + + 4V096 + 4.096V voltage reference typical value + 0x3 + + + + + + + VREG33 + VREG33 Control + 0x20 + 32 + 0x00000010 + + + ENABLE + VREG33 Enable + 1 + 1 + + + ENRDY + VREG33 Ready Enable + 2 + 1 + + + BYPASS + VREG33 Bypass + 3 + 1 + + + ISOEN + Isolation Enable + 4 + 1 + + + + + + + TC0 + U22493.0.0 + Basic Timer Counter + TC + TC_ + 0x42003000 + + 0 + 0x38 + registers + + + + COUNT8 + 8-bit Counter Mode + TcCount8 + 0x0 + + CTRLA + Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Timer Counter Mode + 2 + 2 + + MODESelect + + COUNT16 + Counter in 16-bit mode + 0 + + + COUNT8 + Counter in 8-bit mode + 1 + + + COUNT32 + Counter in 32-bit mode + 2 + + + + + PRESCSYNC + Prescaler and Counter Synchronization + 4 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset the counter on next generic clock + 0 + + + PRESC + Reload or reset the counter on next prescaler clock + 1 + + + RESYNC + Reload or reset the counter on next generic clock and reset the prescaler counter + 2 + + + + + RUNSTDBY + Run during Standby + 6 + 1 + + + ONDEMAND + Clock On Demand + 7 + 1 + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + Prescaler: GCLK_TC + 0 + + + DIV2 + Prescaler: GCLK_TC/2 + 1 + + + DIV4 + Prescaler: GCLK_TC/4 + 2 + + + DIV8 + Prescaler: GCLK_TC/8 + 3 + + + DIV16 + Prescaler: GCLK_TC/16 + 4 + + + DIV64 + Prescaler: GCLK_TC/64 + 5 + + + DIV256 + Prescaler: GCLK_TC/256 + 6 + + + DIV1024 + Prescaler: GCLK_TC/1024 + 7 + + + + + ALOCK + Auto Lock + 11 + 1 + + + CAPTEN0 + Capture Channel 0 Enable + 16 + 1 + + + CAPTEN1 + Capture Channel 1 Enable + 17 + 1 + + + COPEN0 + Capture On Pin 0 Enable + 20 + 1 + + + COPEN1 + Capture On Pin 1 Enable + 21 + 1 + + + CAPTMODE0 + Capture Mode Channel 0 + 24 + 2 + + CAPTMODE0Select + + DEFAULT + Default capture + 0 + + + CAPTMIN + Minimum capture + 1 + + + CAPTMAX + Maximum capture + 2 + + + + + CAPTMODE1 + Capture mode Channel 1 + 27 + 2 + + CAPTMODE1Select + + DEFAULT + Default capture + 0 + + + CAPTMIN + Minimum capture + 1 + + + CAPTMAX + Maximum capture + 2 + + + + + + + CTRLBCLR + Control B Clear + 0x4 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot on Counter + 2 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + UPDATE + Force update of double-buffered register + 3 + + + READSYNC + Force a read synchronization of COUNT + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + CTRLBSET + Control B Set + 0x5 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot on Counter + 2 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + UPDATE + Force update of double-buffered register + 3 + + + READSYNC + Force a read synchronization of COUNT + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + EVCTRL + Event Control + 0x6 + 16 + 0x0000 + + + EVACT + Event Action + 0 + 3 + + EVACTSelect + + OFF + Event action disabled + 0 + + + RETRIGGER + Start, restart or retrigger TC on event + 1 + + + COUNT + Count on event + 2 + + + START + Start TC on event + 3 + + + STAMP + Time stamp capture + 4 + + + PPW + Period catured in CC0, pulse width in CC1 + 5 + + + PWP + Period catured in CC1, pulse width in CC0 + 6 + + + PW + Pulse width capture + 7 + + + + + TCINV + TC Event Input Polarity + 4 + 1 + + + TCEI + TC Event Enable + 5 + 1 + + + OVFEO + Event Output Enable + 8 + 1 + + + MCEO0 + MC Event Output Enable 0 + 12 + 1 + + + MCEO1 + MC Event Output Enable 1 + 13 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x8 + 8 + 0x00 + + + OVF + OVF Interrupt Disable + 0 + 1 + + + ERR + ERR Interrupt Disable + 1 + 1 + + + MC0 + MC Interrupt Disable 0 + 4 + 1 + + + MC1 + MC Interrupt Disable 1 + 5 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x9 + 8 + 0x00 + + + OVF + OVF Interrupt Enable + 0 + 1 + + + ERR + ERR Interrupt Enable + 1 + 1 + + + MC0 + MC Interrupt Enable 0 + 4 + 1 + + + MC1 + MC Interrupt Enable 1 + 5 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0xA + 8 + 0x00 + + + OVF + OVF Interrupt Flag + 0 + 1 + + + ERR + ERR Interrupt Flag + 1 + 1 + + + MC0 + MC Interrupt Flag 0 + 4 + 1 + + + MC1 + MC Interrupt Flag 1 + 5 + 1 + + + + + STATUS + Status + 0xB + 8 + 0x01 + + + STOP + Stop Status Flag + 0 + 1 + + + SLAVE + Slave Status Flag + 1 + 1 + + + PERBUFV + Synchronization Busy Status + 3 + 1 + + + CCBUFV0 + Compare channel buffer 0 valid + 4 + 1 + + + CCBUFV1 + Compare channel buffer 1 valid + 5 + 1 + + + + + WAVE + Waveform Generation Control + 0xC + 8 + 0x00 + + + WAVEGEN + Waveform Generation Mode + 0 + 2 + + WAVEGENSelect + + NFRQ + Normal frequency + 0 + + + MFRQ + Match frequency + 1 + + + NPWM + Normal PWM + 2 + + + MPWM + Match PWM + 3 + + + + + + + DRVCTRL + Control C + 0xD + 8 + 0x00 + + + INVEN0 + Output Waveform Invert Enable 0 + 0 + 1 + + + INVEN1 + Output Waveform Invert Enable 1 + 1 + 1 + + + + + DBGCTRL + Debug Control + 0xF + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + SYNCBUSY + Synchronization Status + 0x10 + 32 + read-only + 0x00000000 + + + SWRST + swrst + 0 + 1 + + + ENABLE + enable + 1 + 1 + + + CTRLB + CTRLB + 2 + 1 + + + STATUS + STATUS + 3 + 1 + + + COUNT + Counter + 4 + 1 + + + PER + Period + 5 + 1 + + + CC0 + Compare Channel 0 + 6 + 1 + + + CC1 + Compare Channel 1 + 7 + 1 + + + + + COUNT + COUNT8 Count + 0x14 + 8 + 0x00 + + + COUNT + Counter Value + 0 + 8 + + + + + PER + COUNT8 Period + 0x1B + 8 + 0xFF + + + PER + Period Value + 0 + 8 + + + + + 2 + 1 + CC[%s] + COUNT8 Compare and Capture + 0x1C + 8 + 0x00 + + + CC + Counter/Compare Value + 0 + 8 + + + + + PERBUF + COUNT8 Period Buffer + 0x2F + 8 + 0xFF + + + PERBUF + Period Buffer Value + 0 + 8 + + + + + 2 + 1 + CCBUF[%s] + COUNT8 Compare and Capture Buffer + 0x30 + 8 + 0x00 + + + CCBUF + Counter/Compare Buffer Value + 0 + 8 + + + + + + COUNT16 + 16-bit Counter Mode + COUNT8 + TcCount16 + 0x0 + + CTRLA + Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Timer Counter Mode + 2 + 2 + + MODESelect + + COUNT16 + Counter in 16-bit mode + 0 + + + COUNT8 + Counter in 8-bit mode + 1 + + + COUNT32 + Counter in 32-bit mode + 2 + + + + + PRESCSYNC + Prescaler and Counter Synchronization + 4 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset the counter on next generic clock + 0 + + + PRESC + Reload or reset the counter on next prescaler clock + 1 + + + RESYNC + Reload or reset the counter on next generic clock and reset the prescaler counter + 2 + + + + + RUNSTDBY + Run during Standby + 6 + 1 + + + ONDEMAND + Clock On Demand + 7 + 1 + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + Prescaler: GCLK_TC + 0 + + + DIV2 + Prescaler: GCLK_TC/2 + 1 + + + DIV4 + Prescaler: GCLK_TC/4 + 2 + + + DIV8 + Prescaler: GCLK_TC/8 + 3 + + + DIV16 + Prescaler: GCLK_TC/16 + 4 + + + DIV64 + Prescaler: GCLK_TC/64 + 5 + + + DIV256 + Prescaler: GCLK_TC/256 + 6 + + + DIV1024 + Prescaler: GCLK_TC/1024 + 7 + + + + + ALOCK + Auto Lock + 11 + 1 + + + CAPTEN0 + Capture Channel 0 Enable + 16 + 1 + + + CAPTEN1 + Capture Channel 1 Enable + 17 + 1 + + + COPEN0 + Capture On Pin 0 Enable + 20 + 1 + + + COPEN1 + Capture On Pin 1 Enable + 21 + 1 + + + CAPTMODE0 + Capture Mode Channel 0 + 24 + 2 + + CAPTMODE0Select + + DEFAULT + Default capture + 0 + + + CAPTMIN + Minimum capture + 1 + + + CAPTMAX + Maximum capture + 2 + + + + + CAPTMODE1 + Capture mode Channel 1 + 27 + 2 + + CAPTMODE1Select + + DEFAULT + Default capture + 0 + + + CAPTMIN + Minimum capture + 1 + + + CAPTMAX + Maximum capture + 2 + + + + + + + CTRLBCLR + Control B Clear + 0x4 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot on Counter + 2 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + UPDATE + Force update of double-buffered register + 3 + + + READSYNC + Force a read synchronization of COUNT + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + CTRLBSET + Control B Set + 0x5 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot on Counter + 2 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + UPDATE + Force update of double-buffered register + 3 + + + READSYNC + Force a read synchronization of COUNT + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + EVCTRL + Event Control + 0x6 + 16 + 0x0000 + + + EVACT + Event Action + 0 + 3 + + EVACTSelect + + OFF + Event action disabled + 0 + + + RETRIGGER + Start, restart or retrigger TC on event + 1 + + + COUNT + Count on event + 2 + + + START + Start TC on event + 3 + + + STAMP + Time stamp capture + 4 + + + PPW + Period catured in CC0, pulse width in CC1 + 5 + + + PWP + Period catured in CC1, pulse width in CC0 + 6 + + + PW + Pulse width capture + 7 + + + + + TCINV + TC Event Input Polarity + 4 + 1 + + + TCEI + TC Event Enable + 5 + 1 + + + OVFEO + Event Output Enable + 8 + 1 + + + MCEO0 + MC Event Output Enable 0 + 12 + 1 + + + MCEO1 + MC Event Output Enable 1 + 13 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x8 + 8 + 0x00 + + + OVF + OVF Interrupt Disable + 0 + 1 + + + ERR + ERR Interrupt Disable + 1 + 1 + + + MC0 + MC Interrupt Disable 0 + 4 + 1 + + + MC1 + MC Interrupt Disable 1 + 5 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x9 + 8 + 0x00 + + + OVF + OVF Interrupt Enable + 0 + 1 + + + ERR + ERR Interrupt Enable + 1 + 1 + + + MC0 + MC Interrupt Enable 0 + 4 + 1 + + + MC1 + MC Interrupt Enable 1 + 5 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0xA + 8 + 0x00 + + + OVF + OVF Interrupt Flag + 0 + 1 + + + ERR + ERR Interrupt Flag + 1 + 1 + + + MC0 + MC Interrupt Flag 0 + 4 + 1 + + + MC1 + MC Interrupt Flag 1 + 5 + 1 + + + + + STATUS + Status + 0xB + 8 + 0x01 + + + STOP + Stop Status Flag + 0 + 1 + + + SLAVE + Slave Status Flag + 1 + 1 + + + PERBUFV + Synchronization Busy Status + 3 + 1 + + + CCBUFV0 + Compare channel buffer 0 valid + 4 + 1 + + + CCBUFV1 + Compare channel buffer 1 valid + 5 + 1 + + + + + WAVE + Waveform Generation Control + 0xC + 8 + 0x00 + + + WAVEGEN + Waveform Generation Mode + 0 + 2 + + WAVEGENSelect + + NFRQ + Normal frequency + 0 + + + MFRQ + Match frequency + 1 + + + NPWM + Normal PWM + 2 + + + MPWM + Match PWM + 3 + + + + + + + DRVCTRL + Control C + 0xD + 8 + 0x00 + + + INVEN0 + Output Waveform Invert Enable 0 + 0 + 1 + + + INVEN1 + Output Waveform Invert Enable 1 + 1 + 1 + + + + + DBGCTRL + Debug Control + 0xF + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + SYNCBUSY + Synchronization Status + 0x10 + 32 + read-only + 0x00000000 + + + SWRST + swrst + 0 + 1 + + + ENABLE + enable + 1 + 1 + + + CTRLB + CTRLB + 2 + 1 + + + STATUS + STATUS + 3 + 1 + + + COUNT + Counter + 4 + 1 + + + PER + Period + 5 + 1 + + + CC0 + Compare Channel 0 + 6 + 1 + + + CC1 + Compare Channel 1 + 7 + 1 + + + + + COUNT + COUNT16 Count + 0x14 + 16 + 0x0000 + + + COUNT + Counter Value + 0 + 16 + + + + + 2 + 2 + CC[%s] + COUNT16 Compare and Capture + 0x1C + 16 + 0x0000 + + + CC + Counter/Compare Value + 0 + 16 + + + + + 2 + 2 + CCBUF[%s] + COUNT16 Compare and Capture Buffer + 0x30 + 16 + 0x0000 + + + CCBUF + Counter/Compare Buffer Value + 0 + 16 + + + + + + COUNT32 + 32-bit Counter Mode + COUNT8 + TcCount32 + 0x0 + + CTRLA + Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Timer Counter Mode + 2 + 2 + + MODESelect + + COUNT16 + Counter in 16-bit mode + 0 + + + COUNT8 + Counter in 8-bit mode + 1 + + + COUNT32 + Counter in 32-bit mode + 2 + + + + + PRESCSYNC + Prescaler and Counter Synchronization + 4 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset the counter on next generic clock + 0 + + + PRESC + Reload or reset the counter on next prescaler clock + 1 + + + RESYNC + Reload or reset the counter on next generic clock and reset the prescaler counter + 2 + + + + + RUNSTDBY + Run during Standby + 6 + 1 + + + ONDEMAND + Clock On Demand + 7 + 1 + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + Prescaler: GCLK_TC + 0 + + + DIV2 + Prescaler: GCLK_TC/2 + 1 + + + DIV4 + Prescaler: GCLK_TC/4 + 2 + + + DIV8 + Prescaler: GCLK_TC/8 + 3 + + + DIV16 + Prescaler: GCLK_TC/16 + 4 + + + DIV64 + Prescaler: GCLK_TC/64 + 5 + + + DIV256 + Prescaler: GCLK_TC/256 + 6 + + + DIV1024 + Prescaler: GCLK_TC/1024 + 7 + + + + + ALOCK + Auto Lock + 11 + 1 + + + CAPTEN0 + Capture Channel 0 Enable + 16 + 1 + + + CAPTEN1 + Capture Channel 1 Enable + 17 + 1 + + + COPEN0 + Capture On Pin 0 Enable + 20 + 1 + + + COPEN1 + Capture On Pin 1 Enable + 21 + 1 + + + CAPTMODE0 + Capture Mode Channel 0 + 24 + 2 + + CAPTMODE0Select + + DEFAULT + Default capture + 0 + + + CAPTMIN + Minimum capture + 1 + + + CAPTMAX + Maximum capture + 2 + + + + + CAPTMODE1 + Capture mode Channel 1 + 27 + 2 + + CAPTMODE1Select + + DEFAULT + Default capture + 0 + + + CAPTMIN + Minimum capture + 1 + + + CAPTMAX + Maximum capture + 2 + + + + + + + CTRLBCLR + Control B Clear + 0x4 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot on Counter + 2 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + UPDATE + Force update of double-buffered register + 3 + + + READSYNC + Force a read synchronization of COUNT + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + CTRLBSET + Control B Set + 0x5 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot on Counter + 2 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + UPDATE + Force update of double-buffered register + 3 + + + READSYNC + Force a read synchronization of COUNT + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + EVCTRL + Event Control + 0x6 + 16 + 0x0000 + + + EVACT + Event Action + 0 + 3 + + EVACTSelect + + OFF + Event action disabled + 0 + + + RETRIGGER + Start, restart or retrigger TC on event + 1 + + + COUNT + Count on event + 2 + + + START + Start TC on event + 3 + + + STAMP + Time stamp capture + 4 + + + PPW + Period catured in CC0, pulse width in CC1 + 5 + + + PWP + Period catured in CC1, pulse width in CC0 + 6 + + + PW + Pulse width capture + 7 + + + + + TCINV + TC Event Input Polarity + 4 + 1 + + + TCEI + TC Event Enable + 5 + 1 + + + OVFEO + Event Output Enable + 8 + 1 + + + MCEO0 + MC Event Output Enable 0 + 12 + 1 + + + MCEO1 + MC Event Output Enable 1 + 13 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x8 + 8 + 0x00 + + + OVF + OVF Interrupt Disable + 0 + 1 + + + ERR + ERR Interrupt Disable + 1 + 1 + + + MC0 + MC Interrupt Disable 0 + 4 + 1 + + + MC1 + MC Interrupt Disable 1 + 5 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x9 + 8 + 0x00 + + + OVF + OVF Interrupt Enable + 0 + 1 + + + ERR + ERR Interrupt Enable + 1 + 1 + + + MC0 + MC Interrupt Enable 0 + 4 + 1 + + + MC1 + MC Interrupt Enable 1 + 5 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0xA + 8 + 0x00 + + + OVF + OVF Interrupt Flag + 0 + 1 + + + ERR + ERR Interrupt Flag + 1 + 1 + + + MC0 + MC Interrupt Flag 0 + 4 + 1 + + + MC1 + MC Interrupt Flag 1 + 5 + 1 + + + + + STATUS + Status + 0xB + 8 + 0x01 + + + STOP + Stop Status Flag + 0 + 1 + + + SLAVE + Slave Status Flag + 1 + 1 + + + PERBUFV + Synchronization Busy Status + 3 + 1 + + + CCBUFV0 + Compare channel buffer 0 valid + 4 + 1 + + + CCBUFV1 + Compare channel buffer 1 valid + 5 + 1 + + + + + WAVE + Waveform Generation Control + 0xC + 8 + 0x00 + + + WAVEGEN + Waveform Generation Mode + 0 + 2 + + WAVEGENSelect + + NFRQ + Normal frequency + 0 + + + MFRQ + Match frequency + 1 + + + NPWM + Normal PWM + 2 + + + MPWM + Match PWM + 3 + + + + + + + DRVCTRL + Control C + 0xD + 8 + 0x00 + + + INVEN0 + Output Waveform Invert Enable 0 + 0 + 1 + + + INVEN1 + Output Waveform Invert Enable 1 + 1 + 1 + + + + + DBGCTRL + Debug Control + 0xF + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + SYNCBUSY + Synchronization Status + 0x10 + 32 + read-only + 0x00000000 + + + SWRST + swrst + 0 + 1 + + + ENABLE + enable + 1 + 1 + + + CTRLB + CTRLB + 2 + 1 + + + STATUS + STATUS + 3 + 1 + + + COUNT + Counter + 4 + 1 + + + PER + Period + 5 + 1 + + + CC0 + Compare Channel 0 + 6 + 1 + + + CC1 + Compare Channel 1 + 7 + 1 + + + + + COUNT + COUNT32 Count + 0x14 + 32 + 0x00000000 + + + COUNT + Counter Value + 0 + 32 + + + + + 2 + 4 + CC[%s] + COUNT32 Compare and Capture + 0x1C + 32 + 0x00000000 + + + CC + Counter/Compare Value + 0 + 32 + + + + + 2 + 4 + CCBUF[%s] + COUNT32 Compare and Capture Buffer + 0x30 + 32 + 0x00000000 + + + CCBUF + Counter/Compare Buffer Value + 0 + 32 + + + + + + + + TC1 + 0x42003400 + + + TC2 + 0x42003800 + + + TC3 + 0x42003C00 + + TC3 + 23 + + + + TC4 + 0x42004000 + + TC4 + 24 + + + + TC5 + 0x43000800 + + + TC6 + 0x43000C00 + + + TC7 + 0x43001000 + + + TCC0 + U22133.1.0 + Timer Counter Control + TCC + TCC_ + 0x42002400 + + 0 + 0x80 + registers + + + TCC0 + 17 + + + + CTRLA + Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + RESOLUTION + Enhanced Resolution + 5 + 2 + + RESOLUTIONSelect + + NONE + Dithering is disabled + 0 + + + DITH4 + Dithering is done every 16 PWM frames + 1 + + + DITH5 + Dithering is done every 32 PWM frames + 2 + + + DITH6 + Dithering is done every 64 PWM frames + 3 + + + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + No division + 0 + + + DIV2 + Divide by 2 + 1 + + + DIV4 + Divide by 4 + 2 + + + DIV8 + Divide by 8 + 3 + + + DIV16 + Divide by 16 + 4 + + + DIV64 + Divide by 64 + 5 + + + DIV256 + Divide by 256 + 6 + + + DIV1024 + Divide by 1024 + 7 + + + + + RUNSTDBY + Run in Standby + 11 + 1 + + + PRESCSYNC + Prescaler and Counter Synchronization Selection + 12 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset counter on next GCLK + 0 + + + PRESC + Reload or reset counter on next prescaler clock + 1 + + + RESYNC + Reload or reset counter on next GCLK and reset prescaler counter + 2 + + + + + ALOCK + Auto Lock + 14 + 1 + + + MSYNC + Master Synchronization (only for TCC Slave Instance) + 15 + 1 + + + DMAOS + DMA One-shot Trigger Mode + 23 + 1 + + + CPTEN0 + Capture Channel 0 Enable + 24 + 1 + + + CPTEN1 + Capture Channel 1 Enable + 25 + 1 + + + CPTEN2 + Capture Channel 2 Enable + 26 + 1 + + + CPTEN3 + Capture Channel 3 Enable + 27 + 1 + + + + + CTRLBCLR + Control B Clear + 0x4 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + IDXCMD + Ramp Index Command + 3 + 2 + + IDXCMDSelect + + DISABLE + Command disabled: Index toggles between cycles A and B + 0 + + + SET + Set index: cycle B will be forced in the next cycle + 1 + + + CLEAR + Clear index: cycle A will be forced in the next cycle + 2 + + + HOLD + Hold index: the next cycle will be the same as the current cycle + 3 + + + + + CMD + TCC Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Clear start, restart or retrigger + 1 + + + STOP + Force stop + 2 + + + UPDATE + Force update or double buffered registers + 3 + + + READSYNC + Force COUNT read synchronization + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + CTRLBSET + Control B Set + 0x5 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + IDXCMD + Ramp Index Command + 3 + 2 + + IDXCMDSelect + + DISABLE + Command disabled: Index toggles between cycles A and B + 0 + + + SET + Set index: cycle B will be forced in the next cycle + 1 + + + CLEAR + Clear index: cycle A will be forced in the next cycle + 2 + + + HOLD + Hold index: the next cycle will be the same as the current cycle + 3 + + + + + CMD + TCC Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Clear start, restart or retrigger + 1 + + + STOP + Force stop + 2 + + + UPDATE + Force update or double buffered registers + 3 + + + READSYNC + Force COUNT read synchronization + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + SYNCBUSY + Synchronization Busy + 0x8 + 32 + read-only + 0x00000000 + + + SWRST + Swrst Busy + 0 + 1 + + + ENABLE + Enable Busy + 1 + 1 + + + CTRLB + Ctrlb Busy + 2 + 1 + + + STATUS + Status Busy + 3 + 1 + + + COUNT + Count Busy + 4 + 1 + + + PATT + Pattern Busy + 5 + 1 + + + WAVE + Wave Busy + 6 + 1 + + + PER + Period Busy + 7 + 1 + + + CC0 + Compare Channel 0 Busy + 8 + 1 + + + CC1 + Compare Channel 1 Busy + 9 + 1 + + + CC2 + Compare Channel 2 Busy + 10 + 1 + + + CC3 + Compare Channel 3 Busy + 11 + 1 + + + + + FCTRLA + Recoverable Fault A Configuration + 0xC + 32 + 0x00000000 + + + SRC + Fault A Source + 0 + 2 + + SRCSelect + + DISABLE + Fault input disabled + 0 + + + ENABLE + MCEx (x=0,1) event input + 1 + + + INVERT + Inverted MCEx (x=0,1) event input + 2 + + + ALTFAULT + Alternate fault (A or B) state at the end of the previous period + 3 + + + + + KEEP + Fault A Keeper + 3 + 1 + + + QUAL + Fault A Qualification + 4 + 1 + + + BLANK + Fault A Blanking Mode + 5 + 2 + + BLANKSelect + + START + Blanking applied from start of the ramp + 0 + + + RISE + Blanking applied from rising edge of the output waveform + 1 + + + FALL + Blanking applied from falling edge of the output waveform + 2 + + + BOTH + Blanking applied from each toggle of the output waveform + 3 + + + + + RESTART + Fault A Restart + 7 + 1 + + + HALT + Fault A Halt Mode + 8 + 2 + + HALTSelect + + DISABLE + Halt action disabled + 0 + + + HW + Hardware halt action + 1 + + + SW + Software halt action + 2 + + + NR + Non-recoverable fault + 3 + + + + + CHSEL + Fault A Capture Channel + 10 + 2 + + CHSELSelect + + CC0 + Capture value stored in channel 0 + 0 + + + CC1 + Capture value stored in channel 1 + 1 + + + CC2 + Capture value stored in channel 2 + 2 + + + CC3 + Capture value stored in channel 3 + 3 + + + + + CAPTURE + Fault A Capture Action + 12 + 3 + + CAPTURESelect + + DISABLE + No capture + 0 + + + CAPT + Capture on fault + 1 + + + CAPTMIN + Minimum capture + 2 + + + CAPTMAX + Maximum capture + 3 + + + LOCMIN + Minimum local detection + 4 + + + LOCMAX + Maximum local detection + 5 + + + DERIV0 + Minimum and maximum local detection + 6 + + + CAPTMARK + Capture with ramp index as MSB value + 7 + + + + + BLANKPRESC + Fault A Blanking Prescaler + 15 + 1 + + + BLANKVAL + Fault A Blanking Time + 16 + 8 + + + FILTERVAL + Fault A Filter Value + 24 + 4 + + + + + FCTRLB + Recoverable Fault B Configuration + 0x10 + 32 + 0x00000000 + + + SRC + Fault B Source + 0 + 2 + + SRCSelect + + DISABLE + Fault input disabled + 0 + + + ENABLE + MCEx (x=0,1) event input + 1 + + + INVERT + Inverted MCEx (x=0,1) event input + 2 + + + ALTFAULT + Alternate fault (A or B) state at the end of the previous period + 3 + + + + + KEEP + Fault B Keeper + 3 + 1 + + + QUAL + Fault B Qualification + 4 + 1 + + + BLANK + Fault B Blanking Mode + 5 + 2 + + BLANKSelect + + START + Blanking applied from start of the ramp + 0 + + + RISE + Blanking applied from rising edge of the output waveform + 1 + + + FALL + Blanking applied from falling edge of the output waveform + 2 + + + BOTH + Blanking applied from each toggle of the output waveform + 3 + + + + + RESTART + Fault B Restart + 7 + 1 + + + HALT + Fault B Halt Mode + 8 + 2 + + HALTSelect + + DISABLE + Halt action disabled + 0 + + + HW + Hardware halt action + 1 + + + SW + Software halt action + 2 + + + NR + Non-recoverable fault + 3 + + + + + CHSEL + Fault B Capture Channel + 10 + 2 + + CHSELSelect + + CC0 + Capture value stored in channel 0 + 0 + + + CC1 + Capture value stored in channel 1 + 1 + + + CC2 + Capture value stored in channel 2 + 2 + + + CC3 + Capture value stored in channel 3 + 3 + + + + + CAPTURE + Fault B Capture Action + 12 + 3 + + CAPTURESelect + + DISABLE + No capture + 0 + + + CAPT + Capture on fault + 1 + + + CAPTMIN + Minimum capture + 2 + + + CAPTMAX + Maximum capture + 3 + + + LOCMIN + Minimum local detection + 4 + + + LOCMAX + Maximum local detection + 5 + + + DERIV0 + Minimum and maximum local detection + 6 + + + CAPTMARK + Capture with ramp index as MSB value + 7 + + + + + BLANKPRESC + Fault B Blanking Prescaler + 15 + 1 + + + BLANKVAL + Fault B Blanking Time + 16 + 8 + + + FILTERVAL + Fault B Filter Value + 24 + 4 + + + + + WEXCTRL + Waveform Extension Configuration + 0x14 + 32 + 0x00000000 + + + OTMX + Output Matrix + 0 + 2 + + + DTIEN0 + Dead-time Insertion Generator 0 Enable + 8 + 1 + + + DTIEN1 + Dead-time Insertion Generator 1 Enable + 9 + 1 + + + DTIEN2 + Dead-time Insertion Generator 2 Enable + 10 + 1 + + + DTIEN3 + Dead-time Insertion Generator 3 Enable + 11 + 1 + + + DTLS + Dead-time Low Side Outputs Value + 16 + 8 + + + DTHS + Dead-time High Side Outputs Value + 24 + 8 + + + + + DRVCTRL + Driver Control + 0x18 + 32 + 0x00000000 + + + NRE0 + Non-Recoverable State 0 Output Enable + 0 + 1 + + + NRE1 + Non-Recoverable State 1 Output Enable + 1 + 1 + + + NRE2 + Non-Recoverable State 2 Output Enable + 2 + 1 + + + NRE3 + Non-Recoverable State 3 Output Enable + 3 + 1 + + + NRE4 + Non-Recoverable State 4 Output Enable + 4 + 1 + + + NRE5 + Non-Recoverable State 5 Output Enable + 5 + 1 + + + NRE6 + Non-Recoverable State 6 Output Enable + 6 + 1 + + + NRE7 + Non-Recoverable State 7 Output Enable + 7 + 1 + + + NRV0 + Non-Recoverable State 0 Output Value + 8 + 1 + + + NRV1 + Non-Recoverable State 1 Output Value + 9 + 1 + + + NRV2 + Non-Recoverable State 2 Output Value + 10 + 1 + + + NRV3 + Non-Recoverable State 3 Output Value + 11 + 1 + + + NRV4 + Non-Recoverable State 4 Output Value + 12 + 1 + + + NRV5 + Non-Recoverable State 5 Output Value + 13 + 1 + + + NRV6 + Non-Recoverable State 6 Output Value + 14 + 1 + + + NRV7 + Non-Recoverable State 7 Output Value + 15 + 1 + + + INVEN0 + Output Waveform 0 Inversion + 16 + 1 + + + INVEN1 + Output Waveform 1 Inversion + 17 + 1 + + + INVEN2 + Output Waveform 2 Inversion + 18 + 1 + + + INVEN3 + Output Waveform 3 Inversion + 19 + 1 + + + INVEN4 + Output Waveform 4 Inversion + 20 + 1 + + + INVEN5 + Output Waveform 5 Inversion + 21 + 1 + + + INVEN6 + Output Waveform 6 Inversion + 22 + 1 + + + INVEN7 + Output Waveform 7 Inversion + 23 + 1 + + + FILTERVAL0 + Non-Recoverable Fault Input 0 Filter Value + 24 + 4 + + + FILTERVAL1 + Non-Recoverable Fault Input 1 Filter Value + 28 + 4 + + + + + DBGCTRL + Debug Control + 0x1E + 8 + 0x00 + + + DBGRUN + Debug Running Mode + 0 + 1 + + + FDDBD + Fault Detection on Debug Break Detection + 2 + 1 + + + + + EVCTRL + Event Control + 0x20 + 32 + 0x00000000 + + + EVACT0 + Timer/counter Input Event0 Action + 0 + 3 + + EVACT0Select + + OFF + Event action disabled + 0 + + + RETRIGGER + Start, restart or re-trigger counter on event + 1 + + + COUNTEV + Count on event + 2 + + + START + Start counter on event + 3 + + + INC + Increment counter on event + 4 + + + COUNT + Count on active state of asynchronous event + 5 + + + STAMP + Stamp capture + 6 + + + FAULT + Non-recoverable fault + 7 + + + + + EVACT1 + Timer/counter Input Event1 Action + 3 + 3 + + EVACT1Select + + OFF + Event action disabled + 0 + + + RETRIGGER + Re-trigger counter on event + 1 + + + DIR + Direction control + 2 + + + STOP + Stop counter on event + 3 + + + DEC + Decrement counter on event + 4 + + + PPW + Period capture value in CC0 register, pulse width capture value in CC1 register + 5 + + + PWP + Period capture value in CC1 register, pulse width capture value in CC0 register + 6 + + + FAULT + Non-recoverable fault + 7 + + + + + CNTSEL + Timer/counter Output Event Mode + 6 + 2 + + CNTSELSelect + + START + An interrupt/event is generated when a new counter cycle starts + 0 + + + END + An interrupt/event is generated when a counter cycle ends + 1 + + + BETWEEN + An interrupt/event is generated when a counter cycle ends, except for the first and last cycles + 2 + + + BOUNDARY + An interrupt/event is generated when a new counter cycle starts or a counter cycle ends + 3 + + + + + OVFEO + Overflow/Underflow Output Event Enable + 8 + 1 + + + TRGEO + Retrigger Output Event Enable + 9 + 1 + + + CNTEO + Timer/counter Output Event Enable + 10 + 1 + + + TCINV0 + Inverted Event 0 Input Enable + 12 + 1 + + + TCINV1 + Inverted Event 1 Input Enable + 13 + 1 + + + TCEI0 + Timer/counter Event 0 Input Enable + 14 + 1 + + + TCEI1 + Timer/counter Event 1 Input Enable + 15 + 1 + + + MCEI0 + Match or Capture Channel 0 Event Input Enable + 16 + 1 + + + MCEI1 + Match or Capture Channel 1 Event Input Enable + 17 + 1 + + + MCEI2 + Match or Capture Channel 2 Event Input Enable + 18 + 1 + + + MCEI3 + Match or Capture Channel 3 Event Input Enable + 19 + 1 + + + MCEO0 + Match or Capture Channel 0 Event Output Enable + 24 + 1 + + + MCEO1 + Match or Capture Channel 1 Event Output Enable + 25 + 1 + + + MCEO2 + Match or Capture Channel 2 Event Output Enable + 26 + 1 + + + MCEO3 + Match or Capture Channel 3 Event Output Enable + 27 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x24 + 32 + 0x00000000 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + TRG + Retrigger Interrupt Enable + 1 + 1 + + + CNT + Counter Interrupt Enable + 2 + 1 + + + ERR + Error Interrupt Enable + 3 + 1 + + + UFS + Non-Recoverable Update Fault Interrupt Enable + 10 + 1 + + + DFS + Non-Recoverable Debug Fault Interrupt Enable + 11 + 1 + + + FAULTA + Recoverable Fault A Interrupt Enable + 12 + 1 + + + FAULTB + Recoverable Fault B Interrupt Enable + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 Interrupt Enable + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 Interrupt Enable + 15 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 16 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 17 + 1 + + + MC2 + Match or Capture Channel 2 Interrupt Enable + 18 + 1 + + + MC3 + Match or Capture Channel 3 Interrupt Enable + 19 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x28 + 32 + 0x00000000 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + TRG + Retrigger Interrupt Enable + 1 + 1 + + + CNT + Counter Interrupt Enable + 2 + 1 + + + ERR + Error Interrupt Enable + 3 + 1 + + + UFS + Non-Recoverable Update Fault Interrupt Enable + 10 + 1 + + + DFS + Non-Recoverable Debug Fault Interrupt Enable + 11 + 1 + + + FAULTA + Recoverable Fault A Interrupt Enable + 12 + 1 + + + FAULTB + Recoverable Fault B Interrupt Enable + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 Interrupt Enable + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 Interrupt Enable + 15 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 16 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 17 + 1 + + + MC2 + Match or Capture Channel 2 Interrupt Enable + 18 + 1 + + + MC3 + Match or Capture Channel 3 Interrupt Enable + 19 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x2C + 32 + 0x00000000 + + + OVF + Overflow + 0 + 1 + + + TRG + Retrigger + 1 + 1 + + + CNT + Counter + 2 + 1 + + + ERR + Error + 3 + 1 + + + UFS + Non-Recoverable Update Fault + 10 + 1 + + + DFS + Non-Recoverable Debug Fault + 11 + 1 + + + FAULTA + Recoverable Fault A + 12 + 1 + + + FAULTB + Recoverable Fault B + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 + 15 + 1 + + + MC0 + Match or Capture 0 + 16 + 1 + + + MC1 + Match or Capture 1 + 17 + 1 + + + MC2 + Match or Capture 2 + 18 + 1 + + + MC3 + Match or Capture 3 + 19 + 1 + + + + + STATUS + Status + 0x30 + 32 + 0x00000001 + + + STOP + Stop + 0 + 1 + + + IDX + Ramp + 1 + 1 + + + UFS + Non-recoverable Update Fault State + 2 + 1 + + + DFS + Non-Recoverable Debug Fault State + 3 + 1 + + + SLAVE + Slave + 4 + 1 + + + PATTBUFV + Pattern Buffer Valid + 5 + 1 + + + PERBUFV + Period Buffer Valid + 7 + 1 + + + FAULTAIN + Recoverable Fault A Input + 8 + 1 + + + FAULTBIN + Recoverable Fault B Input + 9 + 1 + + + FAULT0IN + Non-Recoverable Fault0 Input + 10 + 1 + + + FAULT1IN + Non-Recoverable Fault1 Input + 11 + 1 + + + FAULTA + Recoverable Fault A State + 12 + 1 + + + FAULTB + Recoverable Fault B State + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 State + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 State + 15 + 1 + + + CCBUFV0 + Compare Channel 0 Buffer Valid + 16 + 1 + + + CCBUFV1 + Compare Channel 1 Buffer Valid + 17 + 1 + + + CCBUFV2 + Compare Channel 2 Buffer Valid + 18 + 1 + + + CCBUFV3 + Compare Channel 3 Buffer Valid + 19 + 1 + + + CMP0 + Compare Channel 0 Value + 24 + 1 + + + CMP1 + Compare Channel 1 Value + 25 + 1 + + + CMP2 + Compare Channel 2 Value + 26 + 1 + + + CMP3 + Compare Channel 3 Value + 27 + 1 + + + + + COUNT + Count + 0x34 + 32 + 0x00000000 + + + COUNT + Counter Value + 0 + 24 + + + + + COUNT_DITH4_MODE + Count + COUNT + 0x34 + 32 + 0x00000000 + + + COUNT + Counter Value + 4 + 20 + + + + + COUNT_DITH5_MODE + Count + COUNT + 0x34 + 32 + 0x00000000 + + + COUNT + Counter Value + 5 + 19 + + + + + COUNT_DITH6_MODE + Count + COUNT + 0x34 + 32 + 0x00000000 + + + COUNT + Counter Value + 6 + 18 + + + + + PATT + Pattern + 0x38 + 16 + 0x0000 + + + PGE0 + Pattern Generator 0 Output Enable + 0 + 1 + + + PGE1 + Pattern Generator 1 Output Enable + 1 + 1 + + + PGE2 + Pattern Generator 2 Output Enable + 2 + 1 + + + PGE3 + Pattern Generator 3 Output Enable + 3 + 1 + + + PGE4 + Pattern Generator 4 Output Enable + 4 + 1 + + + PGE5 + Pattern Generator 5 Output Enable + 5 + 1 + + + PGE6 + Pattern Generator 6 Output Enable + 6 + 1 + + + PGE7 + Pattern Generator 7 Output Enable + 7 + 1 + + + PGV0 + Pattern Generator 0 Output Value + 8 + 1 + + + PGV1 + Pattern Generator 1 Output Value + 9 + 1 + + + PGV2 + Pattern Generator 2 Output Value + 10 + 1 + + + PGV3 + Pattern Generator 3 Output Value + 11 + 1 + + + PGV4 + Pattern Generator 4 Output Value + 12 + 1 + + + PGV5 + Pattern Generator 5 Output Value + 13 + 1 + + + PGV6 + Pattern Generator 6 Output Value + 14 + 1 + + + PGV7 + Pattern Generator 7 Output Value + 15 + 1 + + + + + WAVE + Waveform Control + 0x3C + 32 + 0x00000000 + + + WAVEGEN + Waveform Generation + 0 + 3 + + WAVEGENSelect + + NFRQ + Normal frequency + 0 + + + MFRQ + Match frequency + 1 + + + NPWM + Normal PWM + 2 + + + DSCRITICAL + Dual-slope critical + 4 + + + DSBOTTOM + Dual-slope with interrupt/event condition when COUNT reaches ZERO + 5 + + + DSBOTH + Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP + 6 + + + DSTOP + Dual-slope with interrupt/event condition when COUNT reaches TOP + 7 + + + + + RAMP + Ramp Mode + 4 + 2 + + RAMPSelect + + RAMP1 + RAMP1 operation + 0 + + + RAMP2A + Alternative RAMP2 operation + 1 + + + RAMP2 + RAMP2 operation + 2 + + + RAMP2C + Critical RAMP2 operation + 3 + + + + + CIPEREN + Circular period Enable + 7 + 1 + + + CICCEN0 + Circular Channel 0 Enable + 8 + 1 + + + CICCEN1 + Circular Channel 1 Enable + 9 + 1 + + + CICCEN2 + Circular Channel 2 Enable + 10 + 1 + + + CICCEN3 + Circular Channel 3 Enable + 11 + 1 + + + POL0 + Channel 0 Polarity + 16 + 1 + + + POL1 + Channel 1 Polarity + 17 + 1 + + + POL2 + Channel 2 Polarity + 18 + 1 + + + POL3 + Channel 3 Polarity + 19 + 1 + + + SWAP0 + Swap DTI Output Pair 0 + 24 + 1 + + + SWAP1 + Swap DTI Output Pair 1 + 25 + 1 + + + SWAP2 + Swap DTI Output Pair 2 + 26 + 1 + + + SWAP3 + Swap DTI Output Pair 3 + 27 + 1 + + + + + PER + Period + 0x40 + 32 + 0xFFFFFFFF + + + PER + Period Value + 0 + 24 + + + + + PER_DITH4_MODE + Period + PER + 0x40 + 32 + 0xFFFFFFFF + + + DITHER + Dithering Cycle Number + 0 + 4 + + + PER + Period Value + 4 + 20 + + + + + PER_DITH5_MODE + Period + PER + 0x40 + 32 + 0xFFFFFFFF + + + DITHER + Dithering Cycle Number + 0 + 5 + + + PER + Period Value + 5 + 19 + + + + + PER_DITH6_MODE + Period + PER + 0x40 + 32 + 0xFFFFFFFF + + + DITHER + Dithering Cycle Number + 0 + 6 + + + PER + Period Value + 6 + 18 + + + + + 4 + 4 + CC[%s] + Compare and Capture + 0x44 + 32 + 0x00000000 + + + CC + Channel Compare/Capture Value + 0 + 24 + + + + + 4 + 4 + CC_DITH4_MODE[%s] + Compare and Capture + CC[%s] + 0x44 + 32 + 0x00000000 + + + DITHER + Dithering Cycle Number + 0 + 4 + + + CC + Channel Compare/Capture Value + 4 + 20 + + + + + 4 + 4 + CC_DITH5_MODE[%s] + Compare and Capture + CC[%s] + 0x44 + 32 + 0x00000000 + + + DITHER + Dithering Cycle Number + 0 + 5 + + + CC + Channel Compare/Capture Value + 5 + 19 + + + + + 4 + 4 + CC_DITH6_MODE[%s] + Compare and Capture + CC[%s] + 0x44 + 32 + 0x00000000 + + + DITHER + Dithering Cycle Number + 0 + 6 + + + CC + Channel Compare/Capture Value + 6 + 18 + + + + + PATTBUF + Pattern Buffer + 0x64 + 16 + 0x0000 + + + PGEB0 + Pattern Generator 0 Output Enable Buffer + 0 + 1 + + + PGEB1 + Pattern Generator 1 Output Enable Buffer + 1 + 1 + + + PGEB2 + Pattern Generator 2 Output Enable Buffer + 2 + 1 + + + PGEB3 + Pattern Generator 3 Output Enable Buffer + 3 + 1 + + + PGEB4 + Pattern Generator 4 Output Enable Buffer + 4 + 1 + + + PGEB5 + Pattern Generator 5 Output Enable Buffer + 5 + 1 + + + PGEB6 + Pattern Generator 6 Output Enable Buffer + 6 + 1 + + + PGEB7 + Pattern Generator 7 Output Enable Buffer + 7 + 1 + + + PGVB0 + Pattern Generator 0 Output Enable + 8 + 1 + + + PGVB1 + Pattern Generator 1 Output Enable + 9 + 1 + + + PGVB2 + Pattern Generator 2 Output Enable + 10 + 1 + + + PGVB3 + Pattern Generator 3 Output Enable + 11 + 1 + + + PGVB4 + Pattern Generator 4 Output Enable + 12 + 1 + + + PGVB5 + Pattern Generator 5 Output Enable + 13 + 1 + + + PGVB6 + Pattern Generator 6 Output Enable + 14 + 1 + + + PGVB7 + Pattern Generator 7 Output Enable + 15 + 1 + + + + + PERBUF + Period Buffer + 0x6C + 32 + 0xFFFFFFFF + + + PERBUF + Period Buffer Value + 0 + 24 + + + + + PERBUF_DITH4_MODE + Period Buffer + PERBUF + 0x6C + 32 + 0xFFFFFFFF + + + DITHERBUF + Dithering Buffer Cycle Number + 0 + 4 + + + PERBUF + Period Buffer Value + 4 + 20 + + + + + PERBUF_DITH5_MODE + Period Buffer + PERBUF + 0x6C + 32 + 0xFFFFFFFF + + + DITHERBUF + Dithering Buffer Cycle Number + 0 + 5 + + + PERBUF + Period Buffer Value + 5 + 19 + + + + + PERBUF_DITH6_MODE + Period Buffer + PERBUF + 0x6C + 32 + 0xFFFFFFFF + + + DITHERBUF + Dithering Buffer Cycle Number + 0 + 6 + + + PERBUF + Period Buffer Value + 6 + 18 + + + + + 4 + 4 + CCBUF[%s] + Compare and Capture Buffer + 0x70 + 32 + 0x00000000 + + + CCBUF + Channel Compare/Capture Buffer Value + 0 + 24 + + + + + 4 + 4 + CCBUF_DITH4_MODE[%s] + Compare and Capture Buffer + CCBUF[%s] + 0x70 + 32 + 0x00000000 + + + CCBUF + Channel Compare/Capture Buffer Value + 0 + 4 + + + DITHERBUF + Dithering Buffer Cycle Number + 4 + 20 + + + + + 4 + 4 + CCBUF_DITH5_MODE[%s] + Compare and Capture Buffer + CCBUF[%s] + 0x70 + 32 + 0x00000000 + + + DITHERBUF + Dithering Buffer Cycle Number + 0 + 5 + + + CCBUF + Channel Compare/Capture Buffer Value + 5 + 19 + + + + + 4 + 4 + CCBUF_DITH6_MODE[%s] + Compare and Capture Buffer + CCBUF[%s] + 0x70 + 32 + 0x00000000 + + + DITHERBUF + Dithering Buffer Cycle Number + 0 + 6 + + + CCBUF + Channel Compare/Capture Buffer Value + 6 + 18 + + + + + + + TCC1 + 0x42002800 + + TCC1 + 18 + + + + TCC2 + 0x42002C00 + + TCC2 + 19 + + + + WDT + U22511.0.1 + Watchdog Timer + WDT + WDT_ + 0x40002000 + + 0 + 0xD + registers + + + WDT + 1 + + + + CTRLA + Control + 0x0 + 8 + 0x00 + + + ENABLE + Enable + 1 + 1 + + + WEN + Watchdog Timer Window Mode Enable + 2 + 1 + + + ALWAYSON + Always-On + 7 + 1 + + + + + CONFIG + Configuration + 0x1 + 8 + 0xBB + + + PER + Time-Out Period + 0 + 4 + + PERSelect + + CYC8 + 8 clock cycles + 0x0 + + + CYC16 + 16 clock cycles + 0x1 + + + CYC32 + 32 clock cycles + 0x2 + + + CYC64 + 64 clock cycles + 0x3 + + + CYC128 + 128 clock cycles + 0x4 + + + CYC256 + 256 clock cycles + 0x5 + + + CYC512 + 512 clock cycles + 0x6 + + + CYC1024 + 1024 clock cycles + 0x7 + + + CYC2048 + 2048 clock cycles + 0x8 + + + CYC4096 + 4096 clock cycles + 0x9 + + + CYC8192 + 8192 clock cycles + 0xA + + + CYC16384 + 16384 clock cycles + 0xB + + + + + WINDOW + Window Mode Time-Out Period + 4 + 4 + + WINDOWSelect + + CYC8 + 8 clock cycles + 0x0 + + + CYC16 + 16 clock cycles + 0x1 + + + CYC32 + 32 clock cycles + 0x2 + + + CYC64 + 64 clock cycles + 0x3 + + + CYC128 + 128 clock cycles + 0x4 + + + CYC256 + 256 clock cycles + 0x5 + + + CYC512 + 512 clock cycles + 0x6 + + + CYC1024 + 1024 clock cycles + 0x7 + + + CYC2048 + 2048 clock cycles + 0x8 + + + CYC4096 + 4096 clock cycles + 0x9 + + + CYC8192 + 8192 clock cycles + 0xA + + + CYC16384 + 16384 clock cycles + 0xB + + + + + + + EWCTRL + Early Warning Interrupt Control + 0x2 + 8 + 0x0B + + + EWOFFSET + Early Warning Interrupt Time Offset + 0 + 4 + + EWOFFSETSelect + + CYC8 + 8 clock cycles + 0x0 + + + CYC16 + 16 clock cycles + 0x1 + + + CYC32 + 32 clock cycles + 0x2 + + + CYC64 + 64 clock cycles + 0x3 + + + CYC128 + 128 clock cycles + 0x4 + + + CYC256 + 256 clock cycles + 0x5 + + + CYC512 + 512 clock cycles + 0x6 + + + CYC1024 + 1024 clock cycles + 0x7 + + + CYC2048 + 2048 clock cycles + 0x8 + + + CYC4096 + 4096 clock cycles + 0x9 + + + CYC8192 + 8192 clock cycles + 0xA + + + CYC16384 + 16384 clock cycles + 0xB + + + + + + + INTENCLR + Interrupt Enable Clear + 0x4 + 8 + 0x00 + + + EW + Early Warning Interrupt Enable + 0 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x5 + 8 + 0x00 + + + EW + Early Warning Interrupt Enable + 0 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x6 + 8 + 0x00 + + + EW + Early Warning + 0 + 1 + + + + + SYNCBUSY + Synchronization Busy + 0x8 + 32 + read-only + 0x00000000 + + + ENABLE + Enable Busy + 1 + 1 + + + WEN + Window Enable Busy + 2 + 1 + + + ALWAYSON + Always-On Busy + 3 + 1 + + + CLEAR + Clear Busy + 4 + 1 + + + + + CLEAR + Clear + 0xC + 8 + write-only + 0x00 + + + CLEAR + Watchdog Clear + 0 + 8 + + CLEARSelect + + KEY + Clear Key + 0xA5 + + + + + + + + + MPU + Memory Protection Unit + MPU + MPU_ + 0xE000ED90 + + 0 + 0x14 + registers + + + + TYPE + MPU Type Register + 0x0 + 32 + read-only + + + SEPARATE + Separate instruction and Data Memory MapsRegions + 0 + 1 + + + DREGION + Number of Data Regions + 8 + 8 + + + IREGION + Number of Instruction Regions + 16 + 8 + + + + + CTRL + MPU Control Register + 0x4 + 32 + + + ENABLE + MPU Enable + 0 + 1 + + + HFNMIENA + Enable Hard Fault and NMI handlers + 1 + 1 + + + PRIVDEFENA + Enables privileged software access to default memory map + 2 + 1 + + + + + RNR + MPU Region Number Register + 0x8 + 32 + + + REGION + Region referenced by RBAR and RASR + 0 + 8 + + + + + RBAR + MPU Region Base Address Register + 0xC + 32 + + + REGION + Region number + 0 + 4 + + + VALID + Region number valid + 4 + 1 + + + ADDR + Region base address + 5 + 27 + + + + + RASR + MPU Region Attribute and Size Register + 0x10 + 32 + + + ENABLE + Region Enable + 0 + 1 + + + SIZE + Region Size + 1 + 5 + + + SRD + Sub-region disable + 8 + 8 + + + B + Bufferable bit + 16 + 1 + + + C + Cacheable bit + 17 + 1 + + + S + Shareable bit + 18 + 1 + + + TEX + TEX bit + 19 + 3 + + + AP + Access Permission + 24 + 3 + + + XN + Execute Never Attribute + 28 + 1 + + + + + + + NVIC + Nested Vectored Interrupt Controller + NVIC + NVIC_ + 0xE000E100 + + 0 + 0x320 + registers + + + + ISER + Interrupt Set Enable Register + 0x0 + 32 + 0x00000000 + + + SETENA + Interrupt set enable bits + 0 + 31 + + + + + ICER + Interrupt Clear Enable Register + 0x80 + 32 + 0x00000000 + + + CLRENA + Interrupt clear-enable bits + 0 + 31 + + + + + ISPR + Interrupt Set Pending Register + 0x100 + 32 + 0x00000000 + + + SETPEND + Interrupt set-pending bits + 0 + 31 + + + + + ICPR + Interrupt Clear Pending Register + 0x180 + 32 + 0x00000000 + + + CLRPEND + Interrupt clear-pending bits + 0 + 31 + + + + + 8 + 4 + IPR[%s] + Interrupt Priority Register n + 0x300 + 32 + 0x00000000 + + + PRI0 + Priority of interrupt n + 0 + 2 + + + PRI1 + Priority of interrupt n + 8 + 2 + + + PRI2 + Priority of interrupt n + 16 + 2 + + + PRI3 + Priority of interrupt n + 24 + 2 + + + + + + + SysTick + System timer + SysTick + SysTick_ + 0xE000E010 + + 0 + 0x10 + registers + + + + CSR + SysTick Control and Status Register + 0x0 + 32 + 0x4 + + + ENABLE + SysTick Counter Enable + 0 + 1 + + ENABLESelect + + VALUE_0 + Counter disabled + 0 + + + VALUE_1 + Counter enabled + 1 + + + + + TICKINT + SysTick Exception Request Enable + 1 + 1 + + TICKINTSelect + + VALUE_0 + Counting down to 0 does not assert the SysTick exception request + 0 + + + VALUE_1 + Counting down to 0 asserts the SysTick exception request + 1 + + + + + CLKSOURCE + Clock Source 0=external, 1=processor + 2 + 1 + + CLKSOURCESelect + + VALUE_0 + External clock + 0 + + + VALUE_1 + Processor clock + 1 + + + + + COUNTFLAG + Timer counted to 0 since last read of register + 16 + 1 + + + + + RVR + SysTick Reload Value Register + 0x4 + 32 + + + RELOAD + Value to load into the SysTick Current Value Register when the counter reaches 0 + 0 + 24 + + + + + CVR + SysTick Current Value Register + 0x8 + 32 + + + CURRENT + Current value at the time the register is accessed + 0 + 24 + + + + + CALIB + SysTick Calibration Value Register + 0xC + 32 + read-only + 0 + + + TENMS + Reload value to use for 10ms timing + 0 + 24 + + + SKEW + TENMS is rounded from non-integer ratio + 30 + 1 + + SKEWSelect + + VALUE_0 + 10ms calibration value is exact + 0 + + + VALUE_1 + 10ms calibration value is inexact, because of the clock frequency + 1 + + + + + NOREF + No Separate Reference Clock + 31 + 1 + + NOREFSelect + + VALUE_0 + The reference clock is provided + 0 + + + VALUE_1 + The reference clock is not provided + 1 + + + + + + + + + SystemControl + System Control Registers + SystemControl + SystemControl_ + 0xE000E000 + + 0 + 0xD34 + registers + + + + CPUID + CPUID Base Register + 0xD00 + 32 + read-only + 0x410CC601 + + + REVISION + Minor revision number + 0 + 4 + + + PARTNO + Processor Part Number, 0xC60=Cortex-M0+ + 4 + 12 + + + ARCHITECTURE + Processor Architecture, 0xC=ARMv6-M + 16 + 4 + + + VARIANT + Major revision number + 20 + 4 + + + IMPLEMENTER + Implementer code, ARM=0x41 + 24 + 8 + + + + + ICSR + Interrupt Control and State Register + 0xD04 + 32 + 0x00000000 + + + VECTACTIVE + Debug: Exception number of currently executing exception, or 0 if thread mode + 0 + 9 + + + VECTPENDING + Exception number of the highest priority pending enabled exception + 12 + 9 + + + ISRPENDING + Debug: NVIC interrupt pending + 22 + 1 + + + ISRPREEMPT + Debug: Pending exception serviced on exit from debug halt + 23 + 1 + + + PENDSTCLR + SysTick exception clear-pending bit + 25 + 1 + + PENDSTCLRSelect + + VALUE_0 + No effect + 0 + + + VALUE_1 + Removes the pending state from the SysTick exception + 1 + + + + + PENDSTSET + SysTick exception set-pending bit + 26 + 1 + + PENDSTSETSelect + + VALUE_0 + Write: no effect; read: SysTick exception is not pending + 0 + + + VALUE_1 + Write: changes SysTick exception state to pending; read: SysTick exception is pending + 1 + + + + + PENDSVCLR + PendSV clear-pending bit + 27 + 1 + + PENDSVCLRSelect + + VALUE_0 + No effect + 0 + + + VALUE_1 + Removes the pending state from the PendSV exception + 1 + + + + + PENDSVSET + PendSV set-pending bit + 28 + 1 + + PENDSVSETSelect + + VALUE_0 + Write: no effect; read: PendSV exception is not pending + 0 + + + VALUE_1 + Write: changes PendSV exception state to pending; read: PendSV exception is pending + 1 + + + + + NMIPENDSET + NMI set-pending bit + 31 + 1 + + NMIPENDSETSelect + + VALUE_0 + Write: no effect; read: NMI exception is not pending + 0 + + + VALUE_1 + Write: changes NMI exception state to pending; read: NMI exception is pending + 1 + + + + + + + VTOR + Vector Table Offset Register + 0xD08 + 32 + 0x00000000 + + + TBLOFF + Vector table base offset + 7 + 25 + + + + + AIRCR + Application Interrupt and Reset Control Register + 0xD0C + 32 + 0x00000000 + + + VECTCLRACTIVE + Debug: Clear state information + 1 + 1 + + + SYSRESETREQ + System Reset Request + 2 + 1 + + SYSRESETREQSelect + + VALUE_0 + No system reset request + 0 + + + VALUE_1 + Asserts a signal to the outer system that requests a reset + 1 + + + + + ENDIANNESS + Data Endianness, 0=little, 1=big + 15 + 1 + + ENDIANNESSSelect + + VALUE_0 + Little-endian + 0 + + + VALUE_1 + Big-endian + 1 + + + + + VECTKEY + Register key (0x05FA) + 16 + 16 + + + + + SCR + System Control Register + 0xD10 + 32 + 0x00000000 + + + SLEEPONEXIT + Sleep-On-Exit when exiting Handler mode + 1 + 1 + + SLEEPONEXITSelect + + VALUE_0 + O not sleep when returning to Thread mode + 0 + + + VALUE_1 + Enter sleep, or deep sleep, on return from an ISR + 1 + + + + + SLEEPDEEP + Uses Deep Sleep as low power mode + 2 + 1 + + SLEEPDEEPSelect + + VALUE_0 + Sleep + 0 + + + VALUE_1 + Deep sleep + 1 + + + + + SEVONPEND + Send Event on Pending bit + 4 + 1 + + SEVONPENDSelect + + VALUE_0 + Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded + 0 + + + VALUE_1 + Enabled events and all interrupts, including disabled interrupts, can wakeup the processor + 1 + + + + + + + CCR + Configuration and Control Register + 0xD14 + 32 + read-only + 0x00000204 + + + UNALIGN_TRP + Unaligned accesses generates a Hard Fault + 3 + 1 + + UNALIGN_TRPSelect + + VALUE_0 + Do not trap unaligned halfword and word accesses + 0 + + + VALUE_1 + Trap unaligned halfword and word accesses + 1 + + + + + STKALIGN + Stack 8-byte aligned on exception entry + 9 + 1 + + STKALIGNSelect + + VALUE_0 + 4-byte aligned + 0 + + + VALUE_1 + 8-byte aligned + 1 + + + + + + + SHPR2 + System Handler Priority Register 2 + 0xD1C + 32 + 0x00000000 + + + PRI_11 + Priority of system handler 11, SVCall + 24 + 8 + + + + + SHPR3 + System Handler Priority Register 3 + 0xD20 + 32 + 0x00000000 + + + PRI_14 + Priority of system handler 14, PendSV + 16 + 8 + + + PRI_15 + Priority of system handler 15, SysTick exception + 24 + 8 + + + + + SHCSR + System Handler Control and State Register + 0xD24 + 32 + 0x00000000 + + + SVCALLPENDED + 15 + 1 + + + + + DFSR + Debug Fault Status Register + 0xD30 + 32 + 0x00000000 + + + HALTED + Halt request debug event active + 0 + 1 + + + BKPT + Breakpoint debug event + 1 + 1 + + + DWTTRAP + DWT debug event + 2 + 1 + + + VCATCH + Vector catch debug event + 3 + 1 + + + EXTERNAL + EDBGRQ debug event + 4 + 1 + + + + + + + diff --git a/svd/ATSAMC21E18A.svd b/svd/ATSAMC21E18A.svd new file mode 100644 index 000000000000..11922ec1a115 --- /dev/null +++ b/svd/ATSAMC21E18A.svd @@ -0,0 +1,27893 @@ + + + + Microchip Technology + MCHP + ATSAMC21E18A + SAMC21 + 0 + Microchip ATSAMC21E18A Microcontroller + + CM0+ + r0p0 + selectable + true + false + 2 + false + + 8 + 32 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + AC + U22451.1.1 + Analog Comparators + AC + AC_ + 0x42005000 + + 0 + 0x24 + registers + + + AC + 27 + + + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + + + CTRLB + Control B + 0x1 + 8 + write-only + 0x00 + + + START0 + Comparator 0 Start Comparison + 0 + 1 + + + START1 + Comparator 1 Start Comparison + 1 + 1 + + + START2 + Comparator 2 Start Comparison + 2 + 1 + + + START3 + Comparator 3 Start Comparison + 3 + 1 + + + + + EVCTRL + Event Control + 0x2 + 16 + 0x0000 + + + COMPEO0 + Comparator 0 Event Output Enable + 0 + 1 + + + COMPEO1 + Comparator 1 Event Output Enable + 1 + 1 + + + COMPEO2 + Comparator 2 Event Output Enable + 2 + 1 + + + COMPEO3 + Comparator 3 Event Output Enable + 3 + 1 + + + WINEO0 + Window 0 Event Output Enable + 4 + 1 + + + WINEO1 + Window 1 Event Output Enable + 5 + 1 + + + COMPEI0 + Comparator 0 Event Input Enable + 8 + 1 + + + COMPEI1 + Comparator 1 Event Input Enable + 9 + 1 + + + COMPEI2 + Comparator 2 Event Input Enable + 10 + 1 + + + COMPEI3 + Comparator 3 Event Input Enable + 11 + 1 + + + INVEI0 + Comparator 0 Input Event Invert Enable + 12 + 1 + + + INVEI1 + Comparator 1 Input Event Invert Enable + 13 + 1 + + + INVEI2 + Comparator 2 Input Event Invert Enable + 14 + 1 + + + INVEI3 + Comparator 3 Input Event Invert Enable + 15 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x4 + 8 + 0x00 + + + COMP0 + Comparator 0 Interrupt Enable + 0 + 1 + + + COMP1 + Comparator 1 Interrupt Enable + 1 + 1 + + + COMP2 + Comparator 2 Interrupt Enable + 2 + 1 + + + COMP3 + Comparator 3 Interrupt Enable + 3 + 1 + + + WIN0 + Window 0 Interrupt Enable + 4 + 1 + + + WIN1 + Window 1 Interrupt Enable + 5 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x5 + 8 + 0x00 + + + COMP0 + Comparator 0 Interrupt Enable + 0 + 1 + + + COMP1 + Comparator 1 Interrupt Enable + 1 + 1 + + + COMP2 + Comparator 2 Interrupt Enable + 2 + 1 + + + COMP3 + Comparator 3 Interrupt Enable + 3 + 1 + + + WIN0 + Window 0 Interrupt Enable + 4 + 1 + + + WIN1 + Window 1 Interrupt Enable + 5 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x6 + 8 + 0x00 + + + COMP0 + Comparator 0 + 0 + 1 + + + COMP1 + Comparator 1 + 1 + 1 + + + COMP2 + Comparator 2 + 2 + 1 + + + COMP3 + Comparator 3 + 3 + 1 + + + WIN0 + Window 0 + 4 + 1 + + + WIN1 + Window 1 + 5 + 1 + + + + + STATUSA + Status A + 0x7 + 8 + read-only + 0x00 + + + STATE0 + Comparator 0 Current State + 0 + 1 + + + STATE1 + Comparator 1 Current State + 1 + 1 + + + STATE2 + Comparator 2 Current State + 2 + 1 + + + STATE3 + Comparator 3 Current State + 3 + 1 + + + WSTATE0 + Window 0 Current State + 4 + 2 + + WSTATE0Select + + ABOVE + Signal is above window + 0 + + + INSIDE + Signal is inside window + 1 + + + BELOW + Signal is below window + 2 + + + + + WSTATE1 + Window 1 Current State + 6 + 2 + + WSTATE1Select + + ABOVE + Signal is above window + 0 + + + INSIDE + Signal is inside window + 1 + + + BELOW + Signal is below window + 2 + + + + + + + STATUSB + Status B + 0x8 + 8 + read-only + 0x00 + + + READY0 + Comparator 0 Ready + 0 + 1 + + + READY1 + Comparator 1 Ready + 1 + 1 + + + READY2 + Comparator 2 Ready + 2 + 1 + + + READY3 + Comparator 3 Ready + 3 + 1 + + + + + DBGCTRL + Debug Control + 0x9 + 8 + 0x00 + + + DBGRUN + Debug Run + 0 + 1 + + + + + WINCTRL + Window Control + 0xA + 8 + 0x00 + + + WEN0 + Window 0 Mode Enable + 0 + 1 + + + WINTSEL0 + Window 0 Interrupt Selection + 1 + 2 + + WINTSEL0Select + + ABOVE + Interrupt on signal above window + 0 + + + INSIDE + Interrupt on signal inside window + 1 + + + BELOW + Interrupt on signal below window + 2 + + + OUTSIDE + Interrupt on signal outside window + 3 + + + + + WEN1 + Window 1 Mode Enable + 4 + 1 + + + WINTSEL1 + Window 1 Interrupt Selection + 5 + 2 + + WINTSEL1Select + + ABOVE + Interrupt on signal above window + 0 + + + INSIDE + Interrupt on signal inside window + 1 + + + BELOW + Interrupt on signal below window + 2 + + + OUTSIDE + Interrupt on signal outside window + 3 + + + + + + + 4 + 1 + SCALER[%s] + Scaler n + 0xC + 8 + 0x00 + + + VALUE + Scaler Value + 0 + 6 + + + + + 4 + 4 + COMPCTRL[%s] + Comparator Control n + 0x10 + 32 + 0x00000000 + + + ENABLE + Enable + 1 + 1 + + + SINGLE + Single-Shot Mode + 2 + 1 + + + INTSEL + Interrupt Selection + 3 + 2 + + INTSELSelect + + TOGGLE + Interrupt on comparator output toggle + 0 + + + RISING + Interrupt on comparator output rising + 1 + + + FALLING + Interrupt on comparator output falling + 2 + + + EOC + Interrupt on end of comparison (single-shot mode only) + 3 + + + + + RUNSTDBY + Run in Standby + 6 + 1 + + + MUXNEG + Negative Input Mux Selection + 8 + 3 + + MUXNEGSelect + + PIN0 + I/O pin 0 + 0 + + + PIN1 + I/O pin 1 + 1 + + + PIN2 + I/O pin 2 + 2 + + + PIN3 + I/O pin 3 + 3 + + + GND + Ground + 4 + + + VSCALE + VDD scaler + 5 + + + BANDGAP + Internal bandgap voltage + 6 + + + DAC + DAC output + 7 + + + + + MUXPOS + Positive Input Mux Selection + 12 + 3 + + MUXPOSSelect + + PIN0 + I/O pin 0 + 0 + + + PIN1 + I/O pin 1 + 1 + + + PIN2 + I/O pin 2 + 2 + + + PIN3 + I/O pin 3 + 3 + + + VSCALE + VDD Scaler + 4 + + + + + SWAP + Swap Inputs and Invert + 15 + 1 + + + SPEED + Speed Selection + 16 + 2 + + SPEEDSelect + + LOW + Low speed + 0 + + + HIGH + High speed + 3 + + + + + HYSTEN + Hysteresis Enable + 19 + 1 + + + FLEN + Filter Length + 24 + 3 + + FLENSelect + + OFF + No filtering + 0 + + + MAJ3 + 3-bit majority function (2 of 3) + 1 + + + MAJ5 + 5-bit majority function (3 of 5) + 2 + + + + + OUT + Output + 28 + 2 + + OUTSelect + + OFF + The output of COMPn is not routed to the COMPn I/O port + 0 + + + ASYNC + The asynchronous output of COMPn is routed to the COMPn I/O port + 1 + + + SYNC + The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port + 2 + + + + + + + SYNCBUSY + Synchronization Busy + 0x20 + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + Enable Synchronization Busy + 1 + 1 + + + WINCTRL + WINCTRL Synchronization Busy + 2 + 1 + + + COMPCTRL0 + COMPCTRL 0 Synchronization Busy + 3 + 1 + + + COMPCTRL1 + COMPCTRL 1 Synchronization Busy + 4 + 1 + + + COMPCTRL2 + COMPCTRL 2 Synchronization Busy + 5 + 1 + + + COMPCTRL3 + COMPCTRL 3 Synchronization Busy + 6 + 1 + + + + + + + ADC0 + U22472.2.0 + Analog Digital Converter + ADC + ADC_ + 0x42004400 + + 0 + 0x2E + registers + + + ADC0 + 25 + + + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + SLAVEEN + Slave Enable + 5 + 1 + + + RUNSTDBY + Run During Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + + + CTRLB + Control B + 0x1 + 8 + 0x00 + + + PRESCALER + Prescaler Configuration + 0 + 3 + + PRESCALERSelect + + DIV2 + Peripheral clock / 2 + 0x0 + + + DIV4 + Peripheral clock / 4 + 0x1 + + + DIV8 + Peripheral clock / 8 + 0x2 + + + DIV16 + Peripheral clock / 16 + 0x3 + + + DIV32 + Peripheral clock / 32 + 0x4 + + + DIV64 + Peripheral clock / 64 + 0x5 + + + DIV128 + Peripheral clock / 128 + 0x6 + + + DIV256 + Peripheral clock / 256 + 0x7 + + + + + + + REFCTRL + Reference Control + 0x2 + 8 + 0x00 + + + REFSEL + Reference Selection + 0 + 4 + + REFSELSelect + + INTREF + Internal Bandgap Reference + 0x0 + + + INTVCC0 + 1/1.6 VDDANA + 0x1 + + + INTVCC1 + 1/2 VDDANA + 0x2 + + + AREFA + External Reference + 0x3 + + + DAC + DAC + 0x4 + + + INTVCC2 + VDDANA + 0x5 + + + + + REFCOMP + Reference Buffer Offset Compensation Enable + 7 + 1 + + + + + EVCTRL + Event Control + 0x3 + 8 + 0x00 + + + FLUSHEI + Flush Event Input Enable + 0 + 1 + + + STARTEI + Start Conversion Event Input Enable + 1 + 1 + + + FLUSHINV + Flush Event Invert Enable + 2 + 1 + + + STARTINV + Start Event Invert Enable + 3 + 1 + + + RESRDYEO + Result Ready Event Out + 4 + 1 + + + WINMONEO + Window Monitor Event Out + 5 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x4 + 8 + 0x00 + + + RESRDY + Result Ready Interrupt Disable + 0 + 1 + + + OVERRUN + Overrun Interrupt Disable + 1 + 1 + + + WINMON + Window Monitor Interrupt Disable + 2 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x5 + 8 + 0x00 + + + RESRDY + Result Ready Interrupt Enable + 0 + 1 + + + OVERRUN + Overrun Interrupt Enable + 1 + 1 + + + WINMON + Window Monitor Interrupt Enable + 2 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x6 + 8 + 0x00 + + + RESRDY + Result Ready Interrupt Flag + 0 + 1 + + + OVERRUN + Overrun Interrupt Flag + 1 + 1 + + + WINMON + Window Monitor Interrupt Flag + 2 + 1 + + + + + SEQSTATUS + Sequence Status + 0x7 + 8 + read-only + 0x00 + + + SEQSTATE + Sequence State + 0 + 5 + + + SEQBUSY + Sequence Busy + 7 + 1 + + + + + INPUTCTRL + Input Control + 0x8 + 16 + 0x0000 + + + MUXPOS + Positive Mux Input Selection + 0 + 5 + + MUXPOSSelect + + AIN0 + ADC AIN0 Pin + 0x0 + + + AIN1 + ADC AIN1 Pin + 0x1 + + + AIN2 + ADC AIN2 Pin + 0x2 + + + AIN3 + ADC AIN3 Pin + 0x3 + + + AIN4 + ADC AIN4 Pin + 0x4 + + + AIN5 + ADC AIN5 Pin + 0x5 + + + AIN6 + ADC AIN6 Pin + 0x6 + + + AIN7 + ADC AIN7 Pin + 0x7 + + + AIN8 + ADC AIN8 Pin + 0x8 + + + AIN9 + ADC AIN9 Pin + 0x9 + + + AIN10 + ADC AIN10 Pin + 0xA + + + AIN11 + ADC AIN11 Pin + 0xB + + + BANDGAP + Bandgap Voltage + 0x19 + + + SCALEDCOREVCC + 1/4 Scaled Core Supply + 0x1A + + + SCALEDIOVCC + 1/4 Scaled I/O Supply + 0x1B + + + DAC + DAC Output + 0x1C + + + + + MUXNEG + Negative Mux Input Selection + 8 + 5 + + MUXNEGSelect + + AIN0 + ADC AIN0 Pin + 0x0 + + + AIN1 + ADC AIN1 Pin + 0x1 + + + AIN2 + ADC AIN2 Pin + 0x2 + + + AIN3 + ADC AIN3 Pin + 0x3 + + + AIN4 + ADC AIN4 Pin + 0x4 + + + AIN5 + ADC AIN5 Pin + 0x5 + + + GND + Internal Ground + 0x18 + + + + + + + CTRLC + Control C + 0xA + 16 + 0x0000 + + + DIFFMODE + Differential Mode + 0 + 1 + + + LEFTADJ + Left-Adjusted Result + 1 + 1 + + + FREERUN + Free Running Mode + 2 + 1 + + + CORREN + Digital Correction Logic Enable + 3 + 1 + + + RESSEL + Conversion Result Resolution + 4 + 2 + + RESSELSelect + + 12BIT + 12-bit + 0x0 + + + 16BIT + 16-bit averaging mode + 0x1 + + + 10BIT + 10-bit + 0x2 + + + 8BIT + 8-bit + 0x3 + + + + + R2R + Rail-to-Rail mode enable + 7 + 1 + + + WINMODE + Window Monitor Mode + 8 + 3 + + WINMODESelect + + DISABLE + No window mode (default) + 0 + + + MODE1 + RESULT > WINLT + 1 + + + MODE2 + RESULT < WINUT + 2 + + + MODE3 + WINLT < RESULT < WINUT + 3 + + + MODE4 + !(WINLT < RESULT < WINUT) + 4 + + + + + DUALSEL + Dual Mode Trigger Selection + 12 + 2 + + DUALSELSelect + + BOTH + Start event or software trigger will start a conversion on both ADCs + 0 + + + INTERLEAVE + START event or software trigger will alternately start a conversion on ADC0 and ADC1 + 1 + + + + + + + AVGCTRL + Average Control + 0xC + 8 + 0x00 + + + SAMPLENUM + Number of Samples to be Collected + 0 + 4 + + SAMPLENUMSelect + + 1 + 1 sample + 0x0 + + + 2 + 2 samples + 0x1 + + + 4 + 4 samples + 0x2 + + + 8 + 8 samples + 0x3 + + + 16 + 16 samples + 0x4 + + + 32 + 32 samples + 0x5 + + + 64 + 64 samples + 0x6 + + + 128 + 128 samples + 0x7 + + + 256 + 256 samples + 0x8 + + + 512 + 512 samples + 0x9 + + + 1024 + 1024 samples + 0xA + + + + + ADJRES + Adjusting Result / Division Coefficient + 4 + 3 + + + + + SAMPCTRL + Sample Time Control + 0xD + 8 + 0x00 + + + SAMPLEN + Sampling Time Length + 0 + 6 + + + OFFCOMP + Comparator Offset Compensation Enable + 7 + 1 + + + + + WINLT + Window Monitor Lower Threshold + 0xE + 16 + 0x0000 + + + WINLT + Window Lower Threshold + 0 + 16 + + + + + WINUT + Window Monitor Upper Threshold + 0x10 + 16 + 0x0000 + + + WINUT + Window Upper Threshold + 0 + 16 + + + + + GAINCORR + Gain Correction + 0x12 + 16 + 0x0000 + + + GAINCORR + Gain Correction Value + 0 + 12 + + + + + OFFSETCORR + Offset Correction + 0x14 + 16 + 0x0000 + + + OFFSETCORR + Offset Correction Value + 0 + 12 + + + + + SWTRIG + Software Trigger + 0x18 + 8 + 0x00 + + + FLUSH + ADC Flush + 0 + 1 + + + START + Start ADC Conversion + 1 + 1 + + + + + DBGCTRL + Debug Control + 0x1C + 8 + 0x00 + + + DBGRUN + Debug Run + 0 + 1 + + + + + SYNCBUSY + Synchronization Busy + 0x20 + 16 + read-only + 0x0000 + + + SWRST + SWRST Synchronization Busy + 0 + 1 + + + ENABLE + ENABLE Synchronization Busy + 1 + 1 + + + INPUTCTRL + INPUTCTRL Synchronization Busy + 2 + 1 + + + CTRLC + CTRLC Synchronization Busy + 3 + 1 + + + AVGCTRL + AVGCTRL Synchronization Busy + 4 + 1 + + + SAMPCTRL + SAMPCTRL Synchronization Busy + 5 + 1 + + + WINLT + WINLT Synchronization Busy + 6 + 1 + + + WINUT + WINUT Synchronization Busy + 7 + 1 + + + GAINCORR + GAINCORR Synchronization Busy + 8 + 1 + + + OFFSETCORR + OFFSETCTRL Synchronization Busy + 9 + 1 + + + SWTRIG + SWTRG Synchronization Busy + 10 + 1 + + + + + RESULT + Result + 0x24 + 16 + read-only + 0x0000 + + + RESULT + Result Value + 0 + 16 + + + + + SEQCTRL + Sequence Control + 0x28 + 32 + 0x00000000 + + + SEQEN + Enable Positive Input in the Sequence + 0 + 32 + + + + + CALIB + Calibration + 0x2C + 16 + 0x0000 + + + BIASCOMP + Bias Comparator Scaling + 0 + 3 + + + BIASREFBUF + Bias Reference Buffer Scaling + 8 + 3 + + + + + + + ADC1 + 0x42004800 + + ADC1 + 26 + + + + CAN0 + U20032.0.0 + Control Area Network + CAN + CAN_ + 0x42001C00 + + 0 + 0xFC + registers + + + CAN0 + 15 + + + + CREL + Core Release + 0x0 + 32 + read-only + 0x32100000 + + + SUBSTEP + Sub-step of Core Release + 20 + 4 + + + STEP + Step of Core Release + 24 + 4 + + + REL + Core Release + 28 + 4 + + + + + ENDN + Endian + 0x4 + 32 + read-only + 0x87654321 + + + ETV + Endianness Test Value + 0 + 32 + + + + + MRCFG + Message RAM Configuration + 0x8 + 32 + 0x00000002 + + + QOS + Quality of Service + 0 + 2 + + QOSSelect + + DISABLE + Background (no sensitive operation) + 0 + + + LOW + Sensitive Bandwidth + 1 + + + MEDIUM + Sensitive Latency + 2 + + + HIGH + Critical Latency + 3 + + + + + + + DBTP + Fast Bit Timing and Prescaler + 0xC + 32 + 0x00000A33 + + + DSJW + Data (Re)Synchronization Jump Width + 0 + 4 + + + DTSEG2 + Data time segment after sample point + 4 + 4 + + + DTSEG1 + Data time segment before sample point + 8 + 5 + + + DBRP + Data Baud Rate Prescaler + 16 + 5 + + + TDC + Tranceiver Delay Compensation + 23 + 1 + + + + + TEST + Test + 0x10 + 32 + 0x00000000 + + + LBCK + Loop Back Mode + 4 + 1 + + + TX + Control of Transmit Pin + 5 + 2 + + TXSelect + + CORE + TX controlled by CAN core + 0 + + + SAMPLE + TX monitoring sample point + 1 + + + DOMINANT + Dominant (0) level at pin CAN_TX + 2 + + + RECESSIVE + Recessive (1) level at pin CAN_TX + 3 + + + + + RX + Receive Pin + 7 + 1 + + + + + RWD + RAM Watchdog + 0x14 + 32 + 0x00000000 + + + WDC + Watchdog Configuration + 0 + 8 + + + WDV + Watchdog Value + 8 + 8 + + + + + CCCR + CC Control + 0x18 + 32 + 0x00000001 + + + INIT + Initialization + 0 + 1 + + + CCE + Configuration Change Enable + 1 + 1 + + + ASM + ASM Restricted Operation Mode + 2 + 1 + + + CSA + Clock Stop Acknowledge + 3 + 1 + + + CSR + Clock Stop Request + 4 + 1 + + + MON + Bus Monitoring Mode + 5 + 1 + + + DAR + Disable Automatic Retransmission + 6 + 1 + + + TEST + Test Mode Enable + 7 + 1 + + + FDOE + FD Operation Enable + 8 + 1 + + + BRSE + Bit Rate Switch Enable + 9 + 1 + + + PXHD + Protocol Exception Handling Disable + 12 + 1 + + + EFBI + Edge Filtering during Bus Integration + 13 + 1 + + + TXP + Transmit Pause + 14 + 1 + + + NISO + Non ISO Operation + 15 + 1 + + + + + NBTP + Nominal Bit Timing and Prescaler + 0x1C + 32 + 0x06000A03 + + + NTSEG2 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generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + + + GENCTRL7 + Generic Clock Generator Control 7 Synchronization Busy bits + 9 + 1 + + GENCTRL7Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + + + GENCTRL8 + Generic Clock Generator Control 8 Synchronization Busy bits + 10 + 1 + + GENCTRL8Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + + + + + 9 + 4 + GENCTRL[%s] + Generic Clock Generator Control + 0x20 + 32 + 0x00000000 + + + SRC + Source Select + 0 + 3 + + SRCSelect + + XOSC + XOSC oscillator output + 0 + + + GCLKIN + Generator input pad + 1 + + + GCLKGEN1 + Generic clock generator 1 output + 2 + + + OSCULP32K + OSCULP32K oscillator output + 3 + + + OSC32K + OSC32K oscillator output + 4 + + + XOSC32K + XOSC32K oscillator output + 5 + + + OSC48M + OSC48M oscillator output + 6 + + + DPLL96M + DPLL96M output + 7 + + + + + GENEN + Generic Clock Generator Enable + 8 + 1 + + + IDC + Improve Duty Cycle + 9 + 1 + + + OOV + Output Off Value + 10 + 1 + + + OE + Output Enable + 11 + 1 + + + DIVSEL + Divide Selection + 12 + 1 + + DIVSELSelect + + DIV1 + Divide input directly by divider factor + 0x0 + + + DIV2 + Divide input by 2^(divider factor+ 1) + 0x1 + + + + + RUNSTDBY + Run in Standby + 13 + 1 + + + DIV + Division Factor + 16 + 16 + + + + + 41 + 4 + PCHCTRL[%s] + Peripheral Clock Control + 0x80 + 32 + 0x00000000 + + + GEN + Generic Clock Generator + 0 + 4 + + GENSelect + + GCLK0 + Generic clock generator 0 + 0x0 + + + GCLK1 + Generic clock generator 1 + 0x1 + + + GCLK2 + Generic clock generator 2 + 0x2 + + + GCLK3 + Generic clock generator 3 + 0x3 + + + GCLK4 + Generic clock generator 4 + 0x4 + + + GCLK5 + Generic clock generator 5 + 0x5 + + + GCLK6 + Generic clock generator 6 + 0x6 + + + GCLK7 + Generic clock generator 7 + 0x7 + + + GCLK8 + Generic clock generator 8 + 0x8 + + + + + CHEN + Channel Enable + 6 + 1 + + + WRTLOCK + Write Lock + 7 + 1 + + + + + + + HMATRIXHS + I76382.1.3 + HSB Matrix + HMATRIXB + HMATRIXB_ + 0x4100A000 + + 0 + 0x168 + registers + + + + 16 + 4 + MCFG[%s] + Master Configuration + 0x0 + 32 + 0x00000002 + + + ULBT + Undefined Length Burst Type + 0 + 3 + + ULBTSelect + + INFINITE + Infinite Length + 0 + + + SINGLE + Single Access + 1 + + + FOUR_BEAT + Four Beat Burst + 2 + + + EIGHT_BEAT + Eight Beat Burst + 3 + + + SIXTEEN_BEAT + Sixteen Beat Burst + 4 + + + + + + + 16 + 4 + SCFG[%s] + Slave Configuration + 0x40 + 32 + 0x00000010 + + + SLOT_CYCLE + Maximum Number of Allowed Cycles for a Burst + 0 + 8 + + + DEFMSTR_TYPE + Default Master Type + 16 + 2 + + DEFMSTR_TYPESelect + + NO_DEFAULT + No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. + 0 + + + LAST_DEFAULT + Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. + 1 + + + FIXED_DEFAULT + Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave. + 2 + + + + + FIXED_DEFMSTR + Fixed Index of Default Master + 18 + 4 + + + ARBT + Arbitration Type + 24 + 1 + + ARBTSelect + + ROUND_ROBIN + Round-Robin Arbitration + 0 + + + FIXED_PRIORITY + Fixed Priority Arbitration + 1 + + + + + + + 4 + 0x8 + PRS[%s] + + 0x080 + + PRAS + Priority A for Slave + 0x0 + 32 + 0x00000000 + + + M0PR + Master 0 Priority + 0 + 4 + + + M1PR + Master 1 Priority + 4 + 4 + + + M2PR + Master 2 Priority + 8 + 4 + + + M3PR + Master 3 Priority + 12 + 4 + + + M4PR + Master 4 Priority + 16 + 4 + + + M5PR + Master 5 Priority + 20 + 4 + + + M6PR + Master 6 Priority + 24 + 4 + + + M7PR + Master 7 Priority + 28 + 4 + + + + + PRBS + Priority B for Slave + 0x4 + 32 + 0x00000000 + + + M8PR + Master 8 Priority + 0 + 4 + + + M9PR + Master 9 Priority + 4 + 4 + + + M10PR + Master 10 Priority + 8 + 4 + + + M11PR + Master 11 Priority + 12 + 4 + + + M12PR + Master 12 Priority + 16 + 4 + + + M13PR + Master 13 Priority + 20 + 4 + + + M14PR + Master 14 Priority + 24 + 4 + + + M15PR + Master 15 Priority + 28 + 4 + + + + + + MRCR + Master Remap Control + 0x100 + 32 + 0x00000000 + + + RCB0 + Remap Command Bit for Master 0 + 0 + 1 + + RCB0Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB1 + Remap Command Bit for Master 1 + 1 + 1 + + RCB1Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB2 + Remap Command Bit for Master 2 + 2 + 1 + + RCB2Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB3 + Remap Command Bit for Master 3 + 3 + 1 + + RCB3Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB4 + Remap Command Bit for Master 4 + 4 + 1 + + RCB4Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB5 + Remap Command Bit for Master 5 + 5 + 1 + + RCB5Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB6 + Remap Command Bit for Master 6 + 6 + 1 + + RCB6Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB7 + Remap Command Bit for Master 7 + 7 + 1 + + RCB7Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB8 + Remap Command Bit for Master 8 + 8 + 1 + + RCB8Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB9 + Remap Command Bit for Master 9 + 9 + 1 + + RCB9Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB10 + Remap Command Bit for Master 10 + 10 + 1 + + RCB10Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB11 + Remap Command Bit for Master 11 + 11 + 1 + + RCB11Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB12 + Remap Command Bit for Master 12 + 12 + 1 + + RCB12Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB13 + Remap Command Bit for Master 13 + 13 + 1 + + RCB13Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB14 + Remap Command Bit for Master 14 + 14 + 1 + + RCB14Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB15 + Remap Command Bit for Master 15 + 15 + 1 + + RCB15Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + + + 16 + 4 + SFR[%s] + Special Function + 0x110 + 32 + 0x00000000 + + + SFR + Special Function Register + 0 + 32 + + + + + + + MCLK + U22342.0.0 + Main Clock + MCLK + MCLK_ + 0x40000800 + + 0 + 0x20 + registers + + + + INTENCLR + Interrupt Enable Clear + 0x1 + 8 + 0x00 + + + CKRDY + Clock Ready Interrupt Enable + 0 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x2 + 8 + 0x00 + + + CKRDY + Clock Ready Interrupt Enable + 0 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x3 + 8 + 0x01 + + + CKRDY + Clock Ready + 0 + 1 + + + + + CPUDIV + CPU Clock Division + 0x4 + 8 + 0x01 + + + CPUDIV + CPU Clock Division Factor + 0 + 8 + + CPUDIVSelect + + DIV1 + Divide by 1 + 0x01 + + + DIV2 + Divide by 2 + 0x02 + + + DIV4 + Divide by 4 + 0x04 + + + DIV8 + Divide by 8 + 0x08 + + + DIV16 + Divide by 16 + 0x10 + + + DIV32 + Divide by 32 + 0x20 + + + DIV64 + Divide by 64 + 0x40 + + + DIV128 + Divide by 128 + 0x80 + + + + + + + AHBMASK + AHB Mask + 0x10 + 32 + 0x00001CFF + + + HPB0_ + HPB0 AHB Clock Mask + 0 + 1 + + + HPB1_ + HPB1 AHB Clock Mask + 1 + 1 + + + HPB2_ + HPB2 AHB Clock Mask + 2 + 1 + + + DSU_ + DSU AHB Clock Mask + 3 + 1 + + + HMATRIXHS_ + HMATRIXHS AHB Clock Mask + 4 + 1 + + + NVMCTRL_ + NVMCTRL AHB Clock Mask + 5 + 1 + + + HSRAM_ + HSRAM AHB Clock Mask + 6 + 1 + + + DMAC_ + DMAC AHB Clock Mask + 7 + 1 + + + CAN0_ + CAN0 AHB Clock Mask + 8 + 1 + + + PAC_ + PAC AHB Clock Mask + 10 + 1 + + + NVMCTRL_PICACHU_ + NVMCTRL_PICACHU AHB Clock Mask + 11 + 1 + + + DIVAS_ + DIVAS AHB Clock Mask + 12 + 1 + + + + + APBAMASK + APBA Mask + 0x14 + 32 + 0x00000FFF + + + PAC_ + PAC APB Clock Enable + 0 + 1 + + + PM_ + PM APB Clock Enable + 1 + 1 + + + MCLK_ + MCLK APB Clock Enable + 2 + 1 + + + RSTC_ + RSTC APB Clock Enable + 3 + 1 + + + OSCCTRL_ + OSCCTRL APB Clock Enable + 4 + 1 + + + OSC32KCTRL_ + OSC32KCTRL APB Clock Enable + 5 + 1 + + + SUPC_ + SUPC APB Clock Enable + 6 + 1 + + + GCLK_ + GCLK APB Clock Enable + 7 + 1 + + + WDT_ + WDT APB Clock Enable + 8 + 1 + + + RTC_ + RTC APB Clock Enable + 9 + 1 + + + EIC_ + EIC APB Clock Enable + 10 + 1 + + + FREQM_ + FREQM APB Clock Enable + 11 + 1 + + + TSENS_ + TSENS APB Clock Enable + 12 + 1 + + + + + APBBMASK + APBB Mask + 0x18 + 32 + 0x00000007 + + + PORT_ + PORT APB Clock Enable + 0 + 1 + + + DSU_ + DSU APB Clock Enable + 1 + 1 + + + NVMCTRL_ + NVMCTRL APB Clock Enable + 2 + 1 + + + HMATRIXHS_ + HMATRIXHS APB Clock Enable + 5 + 1 + + + + + APBCMASK + APBC Mask + 0x1C + 32 + 0x00000000 + + + EVSYS_ + EVSYS APB Clock Enable + 0 + 1 + + + SERCOM0_ + SERCOM0 APB Clock Enable + 1 + 1 + + + SERCOM1_ + SERCOM1 APB Clock Enable + 2 + 1 + + + SERCOM2_ + SERCOM2 APB Clock Enable + 3 + 1 + + + SERCOM3_ + SERCOM3 APB Clock Enable + 4 + 1 + + + TCC0_ + TCC0 APB Clock Enable + 9 + 1 + + + TCC1_ + TCC1 APB Clock Enable + 10 + 1 + + + TCC2_ + TCC2 APB Clock Enable + 11 + 1 + + + TC0_ + TC0 APB Clock Enable + 12 + 1 + + + TC1_ + TC1 APB Clock Enable + 13 + 1 + + + TC2_ + TC2 APB Clock Enable + 14 + 1 + + + TC3_ + TC3 APB Clock Enable + 15 + 1 + + + TC4_ + TC4 APB Clock Enable + 16 + 1 + + + ADC0_ + ADC0 APB Clock Enable + 17 + 1 + + + ADC1_ + ADC1 APB Clock Enable + 18 + 1 + + + SDADC_ + SDADC APB Clock Enable + 19 + 1 + + + AC_ + AC APB Clock Enable + 20 + 1 + + + DAC_ + DAC APB Clock Enable + 21 + 1 + + + PTC_ + PTC APB Clock Enable + 22 + 1 + + + CCL_ + CCL APB Clock Enable + 23 + 1 + + + + + + + MTB + U20021.0.0 + Cortex-M0+ Micro-Trace Buffer + MTB + MTB_ + 0x41008000 + + 0 + 0x1000 + registers + + + + POSITION + MTB Position + 0x0 + 32 + + + WRAP + Pointer Value Wraps + 2 + 1 + + + POINTER + Trace Packet Location Pointer + 3 + 29 + + + + + MASTER + MTB Master + 0x4 + 32 + 0x00000000 + + + MASK + Maximum Value of the Trace Buffer in SRAM + 0 + 5 + + + TSTARTEN + Trace Start Input Enable + 5 + 1 + + + TSTOPEN + Trace Stop Input Enable + 6 + 1 + + + SFRWPRIV + Special Function Register Write Privilege + 7 + 1 + + + RAMPRIV + SRAM Privilege + 8 + 1 + + + HALTREQ + Halt Request + 9 + 1 + + + EN + Main Trace Enable + 31 + 1 + + + + + FLOW + MTB Flow + 0x8 + 32 + 0x00000000 + + + AUTOSTOP + Auto Stop Tracing + 0 + 1 + + + AUTOHALT + Auto Halt Request + 1 + 1 + + + WATERMARK + Watermark value + 3 + 29 + + + + + BASE + MTB Base + 0xC + 32 + read-only + + + ITCTRL + MTB Integration Mode Control + 0xF00 + 32 + + + CLAIMSET + MTB Claim Set + 0xFA0 + 32 + + + CLAIMCLR + MTB Claim Clear + 0xFA4 + 32 + + + LOCKACCESS + MTB Lock Access + 0xFB0 + 32 + + + LOCKSTATUS + MTB Lock Status + 0xFB4 + 32 + read-only + + + AUTHSTATUS + MTB Authentication Status + 0xFB8 + 32 + read-only + + + DEVARCH + MTB Device Architecture + 0xFBC + 32 + read-only + + + DEVID + MTB Device Configuration + 0xFC8 + 32 + read-only + + + DEVTYPE + MTB Device Type + 0xFCC + 32 + read-only + + + PID4 + Peripheral Identification 4 + 0xFD0 + 32 + read-only + + + PID5 + Peripheral Identification 5 + 0xFD4 + 32 + read-only + + + PID6 + Peripheral Identification 6 + 0xFD8 + 32 + read-only + + + PID7 + Peripheral Identification 7 + 0xFDC + 32 + read-only + + + PID0 + Peripheral Identification 0 + 0xFE0 + 32 + read-only + + + PID1 + Peripheral Identification 1 + 0xFE4 + 32 + read-only + + + PID2 + Peripheral Identification 2 + 0xFE8 + 32 + read-only + + + PID3 + Peripheral Identification 3 + 0xFEC + 32 + read-only + + + CID0 + Component Identification 0 + 0xFF0 + 32 + read-only + + + CID1 + Component Identification 1 + 0xFF4 + 32 + read-only + + + CID2 + Component Identification 2 + 0xFF8 + 32 + read-only + + + CID3 + Component Identification 3 + 0xFFC + 32 + read-only + + + + + NVMCTRL + U22074.0.1.1 + Non-Volatile Memory Controller + NVMCTRL + NVMCTRL_ + 0x41004000 + + 0 + 0x30 + registers + + + NVMCTRL + 6 + + + + CTRLA + Control A + 0x0 + 16 + 0x0000 + + + CMD + Command + 0 + 7 + + CMDSelect + + ER + Erase Row - Erases the row addressed by the ADDR register. + 0x02 + + + WP + Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. + 0x04 + + + EAR + Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. + 0x05 + + + WAP + Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. + 0x06 + + + SF + Security Flow Command + 0x0A + + + WL + Write lockbits + 0x0F + + + RWWEEER + RWW EEPROM area Erase Row - Erases the row addressed by the ADDR register. + 0x1A + + + RWWEEWP + RWW EEPROM Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. + 0x1C + + + LR + Lock Region - Locks the region containing the address location in the ADDR register. + 0x40 + + + UR + Unlock Region - Unlocks the region containing the address location in the ADDR register. + 0x41 + + + SPRM + Sets the power reduction mode. + 0x42 + + + CPRM + Clears the power reduction mode. + 0x43 + + + PBC + Page Buffer Clear - Clears the page buffer. + 0x44 + + + SSB + Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row. + 0x45 + + + INVALL + Invalidate all cache lines. + 0x46 + + + + + CMDEX + Command Execution + 8 + 8 + + CMDEXSelect + + KEY + Execution Key + 0xA5 + + + + + + + CTRLB + Control B + 0x4 + 32 + 0x00000080 + + + RWS + NVM Read Wait States + 1 + 4 + + RWSSelect + + SINGLE + Single Auto Wait State + 0 + + + HALF + Half Auto Wait State + 1 + + + DUAL + Dual Auto Wait State + 2 + + + + + MANW + Manual Write + 7 + 1 + + + SLEEPPRM + Power Reduction Mode during Sleep + 8 + 2 + + SLEEPPRMSelect + + WAKEONACCESS + NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access. + 0 + + + WAKEUPINSTANT + NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep. + 1 + + + DISABLED + Auto power reduction disabled. + 3 + + + + + READMODE + NVMCTRL Read Mode + 16 + 2 + + READMODESelect + + NO_MISS_PENALTY + The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance. + 0x0 + + + LOW_POWER + Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time. + 0x1 + + + DETERMINISTIC + The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings. + 0x2 + + + + + CACHEDIS + Cache Disable + 18 + 2 + + + + + PARAM + NVM Parameter + 0x8 + 32 + 0x00000000 + + + NVMP + NVM Pages + 0 + 16 + + + PSZ + Page Size + 16 + 3 + + PSZSelect + + 8 + 8 bytes + 0x0 + + + 16 + 16 bytes + 0x1 + + + 32 + 32 bytes + 0x2 + + + 64 + 64 bytes + 0x3 + + + 128 + 128 bytes + 0x4 + + + 256 + 256 bytes + 0x5 + + + 512 + 512 bytes + 0x6 + + + 1024 + 1024 bytes + 0x7 + + + + + RWWEEP + RWW EEPROM Pages + 20 + 12 + + + + + INTENCLR + Interrupt Enable Clear + 0xC + 8 + 0x00 + + + READY + NVM Ready Interrupt Enable + 0 + 1 + + + ERROR + Error Interrupt Enable + 1 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x10 + 8 + 0x00 + + + READY + NVM Ready Interrupt Enable + 0 + 1 + + + ERROR + Error Interrupt Enable + 1 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x14 + 8 + 0x00 + + + READY + NVM Ready + 0 + 1 + + + ERROR + Error + 1 + 1 + + + + + STATUS + Status + 0x18 + 16 + 0x0000 + + + PRM + Power Reduction Mode + 0 + 1 + + + LOAD + NVM Page Buffer Active Loading + 1 + 1 + + + PROGE + Programming Error Status + 2 + 1 + + + LOCKE + Lock Error Status + 3 + 1 + + + NVME + NVM Error + 4 + 1 + + + SB + Security Bit Status + 8 + 1 + + + + + ADDR + Address + 0x1C + 32 + 0x00000000 + + + ADDR + NVM Address + 0 + 22 + + + + + LOCK + Lock Section + 0x20 + 16 + 0x0000 + + + LOCK + Region Lock Bits + 0 + 16 + + + + + PBLDATA0 + Page Buffer Load Data 0 + 0x28 + 32 + read-only + 0x00000000 + + + PBLDATA1 + Page Buffer Load Data 1 + 0x2C + 32 + read-only + 0x00000000 + + + + + OSCCTRL + U21192.1.0 + Oscillators Control + OSCCTRL + OSCCTRL_ + 0x40001000 + + 0 + 0x3C + registers + + + + INTENCLR + Interrupt Enable Clear + 0x0 + 32 + 0x00000000 + + + XOSCRDY + XOSC Ready Interrupt Enable + 0 + 1 + + + XOSCFAIL + XOSC Clock Failure Detector Interrupt Enable + 1 + 1 + + + OSC48MRDY + OSC48M Ready Interrupt Enable + 4 + 1 + + + DPLLLCKR + DPLL Lock Rise Interrupt Enable + 8 + 1 + + + DPLLLCKF + DPLL Lock Fall Interrupt Enable + 9 + 1 + + + DPLLLTO + DPLL Time Out Interrupt Enable + 10 + 1 + + + DPLLLDRTO + DPLL Ratio Ready Interrupt Enable + 11 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x4 + 32 + 0x00000000 + + + XOSCRDY + XOSC Ready Interrupt Enable + 0 + 1 + + + XOSCFAIL + XOSC Clock Failure Detector Interrupt Enable + 1 + 1 + + + OSC48MRDY + OSC48M Ready Interrupt Enable + 4 + 1 + + + DPLLLCKR + DPLL Lock Rise Interrupt Enable + 8 + 1 + + + DPLLLCKF + DPLL Lock Fall Interrupt Enable + 9 + 1 + + + DPLLLTO + DPLL Time Out Interrupt Enable + 10 + 1 + + + DPLLLDRTO + DPLL Ratio Ready Interrupt Enable + 11 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x8 + 32 + 0x00000000 + + + XOSCRDY + XOSC Ready + 0 + 1 + + + XOSCFAIL + XOSC Clock Failure Detector + 1 + 1 + + + OSC48MRDY + OSC48M Ready + 4 + 1 + + + DPLLLCKR + DPLL Lock Rise + 8 + 1 + + + DPLLLCKF + DPLL Lock Fall + 9 + 1 + + + DPLLLTO + DPLL Timeout + 10 + 1 + + + DPLLLDRTO + DPLL Ratio Ready + 11 + 1 + + + + + STATUS + Power and Clocks Status + 0xC + 32 + read-only + 0x00000000 + + + XOSCRDY + XOSC Ready + 0 + 1 + + + XOSCFAIL + XOSC Clock Failure Detector + 1 + 1 + + + XOSCCKSW + XOSC Clock Switch + 2 + 1 + + + OSC48MRDY + OSC48M Ready + 4 + 1 + + + DPLLLCKR + DPLL Lock Rise + 8 + 1 + + + DPLLLCKF + DPLL Lock Fall + 9 + 1 + + + DPLLTO + DPLL Timeout + 10 + 1 + + + DPLLLDRTO + DPLL Ratio Ready + 11 + 1 + + + + + XOSCCTRL + External Multipurpose Crystal Oscillator (XOSC) Control + 0x10 + 16 + 0x0080 + + + ENABLE + Oscillator Enable + 1 + 1 + + + XTALEN + Crystal Oscillator Enable + 2 + 1 + + + CFDEN + Xosc Clock Failure Detector Enable + 3 + 1 + + + SWBEN + Xosc Clock Switch Enable + 4 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + GAIN + Oscillator Gain + 8 + 3 + + GAINSelect + + GAIN2 + 2 MHz + 0 + + + GAIN4 + 4 MHz + 1 + + + GAIN8 + 8 MHz + 2 + + + GAIN16 + 16 MHz + 3 + + + GAIN30 + 30 MHz + 4 + + + + + AMPGC + Automatic Amplitude Gain Control + 11 + 1 + + + STARTUP + Start-Up Time + 12 + 4 + + STARTUPSelect + + CYCLE1 + 31 us + 0 + + + CYCLE2 + 61 us + 1 + + + CYCLE4 + 122 us + 2 + + + CYCLE8 + 244 us + 3 + + + CYCLE16 + 488 us + 4 + + + CYCLE32 + 977 us + 5 + + + CYCLE64 + 1953 us + 6 + + + CYCLE128 + 3906 us + 7 + + + CYCLE256 + 7813 us + 8 + + + CYCLE512 + 15625 us + 9 + + + CYCLE1024 + 31250 us + 10 + + + CYCLE2048 + 62500 us + 11 + + + CYCLE4096 + 125000 us + 12 + + + CYCLE8192 + 250000 us + 13 + + + CYCLE16384 + 500000 us + 14 + + + CYCLE32768 + 1000000 us + 15 + + + + + + + CFDPRESC + Clock Failure Detector Prescaler + 0x12 + 8 + 0x00 + + + CFDPRESC + Clock Failure Detector Prescaler + 0 + 3 + + CFDPRESCSelect + + DIV1 + 48 MHz + 0 + + + DIV2 + 24 MHz + 1 + + + DIV4 + 12 MHz + 2 + + + DIV8 + 6 MHz + 3 + + + DIV16 + 3 MHz + 4 + + + DIV32 + 1.5 MHz + 5 + + + DIV64 + 0.75 MHz + 6 + + + DIV128 + 0.3125 MHz + 7 + + + + + + + EVCTRL + Event Control + 0x13 + 8 + 0x00 + + + CFDEO + Clock Failure Detector Event Output Enable + 0 + 1 + + + + + OSC48MCTRL + 48MHz Internal Oscillator (OSC48M) Control + 0x14 + 8 + 0x82 + + + ENABLE + Oscillator Enable + 1 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + + + OSC48MDIV + OSC48M Divider + 0x15 + 8 + 0x0B + + + DIV + OSC48M Division Factor + 0 + 4 + + DIVSelect + + DIV1 + 48 MHz + 0 + + + DIV2 + 24 MHz + 1 + + + DIV3 + 16 MHz + 2 + + + DIV4 + 12 MHz + 3 + + + DIV5 + 9.6 MHz + 4 + + + DIV6 + 8 MHz + 5 + + + DIV7 + 6.86 MHz + 6 + + + DIV8 + 6 MHz + 7 + + + DIV9 + 5.33 MHz + 8 + + + DIV10 + 4.8 MHz + 9 + + + DIV11 + 4.36 MHz + 10 + + + DIV12 + 4 MHz + 11 + + + DIV13 + 3.69 MHz + 12 + + + DIV14 + 3.43 MHz + 13 + + + DIV15 + 3.2 MHz + 14 + + + DIV16 + 3 MHz + 15 + + + + + + + OSC48MSTUP + OSC48M Startup Time + 0x16 + 8 + 0x07 + + + STARTUP + Startup Time + 0 + 3 + + STARTUPSelect + + CYCLE8 + 166 ns + 0 + + + CYCLE16 + 333 ns + 1 + + + CYCLE32 + 667 ns + 2 + + + CYCLE64 + 1.333 us + 3 + + + CYCLE128 + 2.667 us + 4 + + + CYCLE256 + 5.333 us + 5 + + + CYCLE512 + 10.667 us + 6 + + + CYCLE1024 + 21.333 us + 7 + + + + + + + OSC48MSYNCBUSY + OSC48M Synchronization Busy + 0x18 + 32 + read-only + 0x00000000 + + + OSC48MDIV + OSC48MDIV Synchronization Status + 2 + 1 + + + + + DPLLCTRLA + DPLL Control + 0x1C + 8 + 0x80 + + + ENABLE + Enable + 1 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand + 7 + 1 + + + + + DPLLRATIO + DPLL Ratio Control + 0x20 + 32 + 0x00000000 + + + LDR + Loop Divider Ratio + 0 + 12 + + + LDRFRAC + Loop Divider Ratio Fractional Part + 16 + 4 + + + + + DPLLCTRLB + Digital Core Configuration + 0x24 + 32 + 0x00000000 + + + FILTER + Proportional Integral Filter Selection + 0 + 2 + + FILTERSelect + + DEFAULT + Default filter mode + 0 + + + LBFILT + Low bandwidth filter + 1 + + + HBFILT + High bandwidth filter + 2 + + + HDFILT + High damping filter + 3 + + + + + LPEN + Low-Power Enable + 2 + 1 + + + WUF + Wake Up Fast + 3 + 1 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Automatic lock. + 0 + + + 8MS + Time-out if no lock within 8ms + 4 + + + 9MS + Time-out if no lock within 9ms + 5 + + + 10MS + Time-out if no lock within 10ms + 6 + + + 11MS + Time-out if no lock within 11ms + 7 + + + + + LBYPASS + Lock Bypass + 12 + 1 + + + DIV + Clock Divider + 16 + 11 + + + + + DPLLPRESC + DPLL Prescaler + 0x28 + 8 + 0x00 + + + PRESC + Output Clock Prescaler + 0 + 2 + + PRESCSelect + + DIV1 + DPLL output is divided by 1 + 0 + + + DIV2 + DPLL output is divided by 2 + 1 + + + DIV4 + DPLL output is divided by 4 + 2 + + + + + + + DPLLSYNCBUSY + DPLL Synchronization Busy + 0x2C + 8 + read-only + 0x00 + + + ENABLE + DPLL Enable Synchronization Status + 1 + 1 + + + DPLLRATIO + DPLL Ratio Synchronization Status + 2 + 1 + + + DPLLPRESC + DPLL Prescaler Synchronization Status + 3 + 1 + + + + + DPLLSTATUS + DPLL Status + 0x30 + 8 + read-only + 0x00 + + + LOCK + DPLL Lock Status + 0 + 1 + + + CLKRDY + DPLL Clock Ready + 1 + 1 + + + + + CAL48M + 48MHz Oscillator Calibration + 0x38 + 32 + 0x00000000 + + + FCAL + Frequency Calibration (48MHz) + 0 + 6 + + + FRANGE + Frequency Range (48MHz) + 8 + 2 + + + TCAL + Temperature Calibration (48MHz) + 16 + 6 + + + + + + + OSC32KCTRL + U22462.1.0 + 32k Oscillators Control + OSC32KCTRL + OSC32KCTRL_ + 0x40001400 + + 0 + 0x20 + registers + + + + INTENCLR + Interrupt Enable Clear + 0x0 + 32 + 0x00000000 + + + XOSC32KRDY + XOSC32K Ready Interrupt Enable + 0 + 1 + + + OSC32KRDY + OSC32K Ready Interrupt Enable + 1 + 1 + + + CLKFAIL + XOSC32K Clock Failure Detector Interrupt Enable + 2 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x4 + 32 + 0x00000000 + + + XOSC32KRDY + XOSC32K Ready Interrupt Enable + 0 + 1 + + + OSC32KRDY + OSC32K Ready Interrupt Enable + 1 + 1 + + + CLKFAIL + XOSC32K Clock Failure Detector Interrupt Enable + 2 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x8 + 32 + 0x00000000 + + + XOSC32KRDY + XOSC32K Ready + 0 + 1 + + + OSC32KRDY + OSC32K Ready + 1 + 1 + + + CLKFAIL + XOSC32K Clock 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Output Enable + 3 + 1 + + + EN1K + 1kHz Output Enable + 4 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + STARTUP + Oscillator Start-Up Time + 8 + 3 + + STARTUPSelect + + CYCLE1 + 0.122 ms + 0 + + + CYCLE32 + 1.068 ms + 1 + + + CYCLE2048 + 62.6 ms + 2 + + + CYCLE4096 + 125 ms + 3 + + + CYCLE16384 + 500 ms + 4 + + + CYCLE32768 + 1000 ms + 5 + + + CYCLE65536 + 2000 ms + 6 + + + CYCLE131072 + 4000 ms + 7 + + + + + WRTLOCK + Write Lock + 12 + 1 + + + + + CFDCTRL + Clock Failure Detector Control + 0x16 + 8 + 0x00 + + + CFDEN + Clock Failure Detector Enable + 0 + 1 + + + SWBACK + Clock Switch Back + 1 + 1 + + + CFDPRESC + Clock Failure Detector Prescaler + 2 + 1 + + + + + EVCTRL + Event Control + 0x17 + 8 + 0x00 + + + CFDEO + Clock Failure Detector Event Output Enable + 0 + 1 + + + + + OSC32K + 32kHz Internal Oscillator (OSC32K) Control + 0x18 + 32 + 0x003F0080 + + + ENABLE + Oscillator Enable + 1 + 1 + + + EN32K + 32kHz Output Enable + 2 + 1 + + + EN1K + 1kHz Output Enable + 3 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + STARTUP + Oscillator Start-Up Time + 8 + 3 + + STARTUPSelect + + CYCLE3 + 0.092 ms + 0 + + + CYCLE4 + 0.122 ms + 1 + + + CYCLE6 + 0.183 ms + 2 + + + CYCLE10 + 0.305 ms + 3 + + + CYCLE18 + 0.549 ms + 4 + + + CYCLE34 + 1.038 ms + 5 + + + CYCLE66 + 2.014 ms + 6 + + + CYCLE130 + 3.967 ms + 7 + + + + + WRTLOCK + Write Lock + 12 + 1 + + + CALIB + Oscillator Calibration + 16 + 7 + + + + + OSCULP32K + 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control + 0x1C + 32 + + + CALIB + Oscillator Calibration + 8 + 5 + + + WRTLOCK + Write Lock + 15 + 1 + + + + + + + PAC + U21201.1.0 + Peripheral Access Controller + PAC + PAC_ + 0x40000000 + + 0 + 0x40 + registers + + + + WRCTRL + Write control + 0x0 + 32 + 0x00000000 + + + PERID + Peripheral identifier + 0 + 16 + + + KEY + Peripheral access control key + 16 + 8 + + KEYSelect + + OFF + No action + 0 + + + CLR + Clear protection + 1 + + + SET + Set protection + 2 + + + SETLCK + Set and lock protection + 3 + + + + + + + EVCTRL + Event control + 0x4 + 8 + 0x00 + + + ERREO + Peripheral acess error event output + 0 + 1 + + + + + INTENCLR + Interrupt enable clear + 0x8 + 8 + 0x00 + + + ERR + Peripheral access error interrupt disable + 0 + 1 + + + + + INTENSET + Interrupt enable set + 0x9 + 8 + 0x00 + + + ERR + Peripheral access error interrupt enable + 0 + 1 + + + + + INTFLAGAHB + Bridge interrupt flag status + 0x10 + 32 + 0x00000000 + + + FLASH_ + FLASH + 0 + 1 + + + HSRAMCM0P_ + HSRAMCM0P + 1 + 1 + + + HSRAMDSU_ + HSRAMDSU + 2 + 1 + + + HPB1_ + HPB1 + 3 + 1 + + + HPB0_ + HPB0 + 4 + 1 + + + HPB2_ + HPB2 + 5 + 1 + + + LPRAMDMAC_ + LPRAMDMAC + 6 + 1 + + + DIVAS_ + DIVAS + 7 + 1 + + + + + INTFLAGA + Peripheral interrupt flag status - Bridge A + 0x14 + 32 + 0x00000000 + + + PAC_ + PAC + 0 + 1 + + + PM_ + PM + 1 + 1 + + + MCLK_ + MCLK + 2 + 1 + + + RSTC_ + RSTC + 3 + 1 + + + OSCCTRL_ + OSCCTRL + 4 + 1 + + + OSC32KCTRL_ + OSC32KCTRL + 5 + 1 + + + SUPC_ + SUPC + 6 + 1 + + + GCLK_ + GCLK + 7 + 1 + + + WDT_ + WDT + 8 + 1 + + + RTC_ + RTC + 9 + 1 + + + EIC_ + EIC + 10 + 1 + + + FREQM_ + FREQM + 11 + 1 + + + TSENS_ + TSENS + 12 + 1 + + + + + INTFLAGB + Peripheral interrupt flag status - Bridge B + 0x18 + 32 + 0x00000000 + + + PORT_ + PORT + 0 + 1 + + + DSU_ + DSU + 1 + 1 + + + NVMCTRL_ + NVMCTRL + 2 + 1 + + + DMAC_ + DMAC + 3 + 1 + + + MTB_ + MTB + 4 + 1 + + + HMATRIXHS_ + HMATRIXHS + 5 + 1 + + + + + INTFLAGC + Peripheral interrupt flag status - Bridge C + 0x1C + 32 + 0x00000000 + + + EVSYS_ + EVSYS + 0 + 1 + + + SERCOM0_ + SERCOM0 + 1 + 1 + + + SERCOM1_ + SERCOM1 + 2 + 1 + + + SERCOM2_ + SERCOM2 + 3 + 1 + + + SERCOM3_ + SERCOM3 + 4 + 1 + + + CAN0_ + CAN0 + 7 + 1 + + + TCC0_ + TCC0 + 9 + 1 + + + TCC1_ + TCC1 + 10 + 1 + + + TCC2_ + TCC2 + 11 + 1 + + + TC0_ + TC0 + 12 + 1 + + + TC1_ + TC1 + 13 + 1 + + + TC2_ + TC2 + 14 + 1 + + + TC3_ + TC3 + 15 + 1 + + + TC4_ + TC4 + 16 + 1 + + + ADC0_ + ADC0 + 17 + 1 + + + ADC1_ + ADC1 + 18 + 1 + + + SDADC_ + SDADC + 19 + 1 + + + AC_ + AC + 20 + 1 + + + DAC_ + DAC + 21 + 1 + + + PTC_ + PTC + 22 + 1 + + + CCL_ + CCL + 23 + 1 + + + + + STATUSA + Peripheral write protection status - Bridge A + 0x34 + 32 + read-only + 0x00000000 + + + PAC_ + PAC APB Protect Enable + 0 + 1 + + + PM_ + PM APB Protect Enable + 1 + 1 + + + MCLK_ + MCLK APB Protect Enable + 2 + 1 + + + RSTC_ + RSTC APB Protect Enable + 3 + 1 + + + OSCCTRL_ + OSCCTRL APB Protect Enable + 4 + 1 + + + OSC32KCTRL_ + OSC32KCTRL APB Protect Enable + 5 + 1 + + + SUPC_ + SUPC APB Protect Enable + 6 + 1 + + + GCLK_ + GCLK APB Protect Enable + 7 + 1 + + + WDT_ + WDT APB Protect Enable + 8 + 1 + + + RTC_ + RTC APB Protect Enable + 9 + 1 + + + EIC_ + EIC APB Protect Enable + 10 + 1 + + + FREQM_ + FREQM APB Protect Enable + 11 + 1 + + + TSENS_ + TSENS APB Protect Enable + 12 + 1 + + + + + STATUSB + Peripheral write protection status - Bridge B + 0x38 + 32 + read-only + 0x00000002 + + + PORT_ + PORT APB Protect Enable + 0 + 1 + + + DSU_ + DSU APB Protect Enable + 1 + 1 + + + NVMCTRL_ + NVMCTRL APB Protect Enable + 2 + 1 + + + DMAC_ + DMAC APB Protect Enable + 3 + 1 + + + MTB_ + MTB APB Protect Enable + 4 + 1 + + + HMATRIXHS_ + HMATRIXHS APB Protect Enable + 5 + 1 + + + + + STATUSC + Peripheral write protection status - Bridge C + 0x3C + 32 + read-only + 0x02000000 + + + EVSYS_ + EVSYS APB Protect Enable + 0 + 1 + + + SERCOM0_ + SERCOM0 APB Protect Enable + 1 + 1 + + + SERCOM1_ + SERCOM1 APB Protect Enable + 2 + 1 + + + SERCOM2_ + SERCOM2 APB Protect Enable + 3 + 1 + + + SERCOM3_ + SERCOM3 APB Protect Enable + 4 + 1 + + + CAN0_ + CAN0 APB Protect Enable + 7 + 1 + + + TCC0_ + TCC0 APB Protect Enable + 9 + 1 + + + TCC1_ + TCC1 APB Protect Enable + 10 + 1 + + + TCC2_ + TCC2 APB Protect Enable + 11 + 1 + + + TC0_ + TC0 APB Protect Enable + 12 + 1 + + + TC1_ + TC1 APB Protect Enable + 13 + 1 + + + TC2_ + TC2 APB Protect Enable + 14 + 1 + + + TC3_ + TC3 APB Protect Enable + 15 + 1 + + + TC4_ + TC4 APB Protect Enable + 16 + 1 + + + ADC0_ + ADC0 APB Protect Enable + 17 + 1 + + + ADC1_ + ADC1 APB Protect Enable + 18 + 1 + + + SDADC_ + SDADC APB Protect Enable + 19 + 1 + + + AC_ + AC APB Protect Enable + 20 + 1 + + + DAC_ + DAC APB Protect Enable + 21 + 1 + + + PTC_ + PTC APB Protect Enable + 22 + 1 + + + CCL_ + CCL APB Protect Enable + 23 + 1 + + + + + + + PM + U22402.1.0 + Power Manager + PM + PM_ + 0x40000400 + + 0 + 0xA + registers + + + + SLEEPCFG + Sleep Configuration + 0x1 + 8 + 0x00 + + + SLEEPMODE + Sleep Mode + 0 + 3 + + SLEEPMODESelect + + IDLE0 + CPU clock is OFF + 0 + + + IDLE1 + AHB clock is OFF + 1 + + + IDLE2 + APB clock are OFF + 2 + + + STANDBY + All Clocks are OFF + 4 + + + + + + + STDBYCFG + Standby Configuration + 0x8 + 16 + 0x0400 + + + VREGSMOD + Voltage Regulator Standby mode + 6 + 2 + + VREGSMODSelect + + AUTO + Automatic mode + 0 + + + PERFORMANCE + Performance oriented + 1 + + + LP + Low Power oriented + 2 + + + + + BBIASHS + Back Bias for HMCRAMCHS + 10 + 1 + + + + + + + PORT + U22102.1.1 + Port Module + PORT + PORT_ + 0x41000000 + + 0 + 0x80 + registers + + + + 1 + 0x80 + GROUP[%s] + + 0x00 + + DIR + Data Direction + 0x0 + 32 + 0x00000000 + + + DIRCLR + Data Direction Clear + 0x4 + 32 + 0x00000000 + + + DIRSET + Data Direction Set + 0x8 + 32 + 0x00000000 + + + DIRTGL + Data Direction Toggle + 0xC + 32 + 0x00000000 + + + OUT + Data Output Value + 0x10 + 32 + 0x00000000 + + + OUTCLR + Data Output Value Clear + 0x14 + 32 + 0x00000000 + + + OUTSET + Data Output Value Set + 0x18 + 32 + 0x00000000 + + + OUTTGL + Data Output Value Toggle + 0x1C + 32 + 0x00000000 + + + IN + Data Input Value + 0x20 + 32 + read-only + 0x00000000 + + + CTRL + Control + 0x24 + 32 + 0x00000000 + + + SAMPLING + Input Sampling Mode + 0 + 32 + + + + + WRCONFIG + Write Configuration + 0x28 + 32 + write-only + 0x00000000 + + + PINMASK + Pin Mask for Multiple Pin Configuration + 0 + 16 + + + PMUXEN + Select Peripheral Multiplexer + 16 + 1 + + + INEN + Input Enable + 17 + 1 + + + PULLEN + Pull Enable + 18 + 1 + + + DRVSTR + Output Driver Strength Selection + 22 + 1 + + + PMUX + Peripheral Multiplexing Template + 24 + 4 + + + WRPMUX + Write PMUX Registers + 28 + 1 + + + WRPINCFG + Write PINCFG Registers + 30 + 1 + + + HWSEL + Half-Word Select + 31 + 1 + + + + + EVCTRL + Event Input Control + 0x2C + 32 + 0x00000000 + + + PID0 + Port Event Pin Identifier 0 + 0 + 5 + + + EVACT0 + Port Event Action 0 + 5 + 2 + + EVACT0Select + + OUT + Event output to pin + 0x0 + + + SET + Set output register of pin on event + 0x1 + + + CLR + Clear output register of pin on event + 0x2 + + + TGL + Toggle output register of pin on event + 0x3 + + + + + PORTEI0 + Port Event Enable Input 0 + 7 + 1 + + + PID1 + Port Event Pin Identifier 1 + 8 + 5 + + + EVACT1 + Port Event Action 1 + 13 + 2 + + + PORTEI1 + Port Event Enable Input 1 + 15 + 1 + + + PID2 + Port Event Pin Identifier 2 + 16 + 5 + + + EVACT2 + Port Event Action 2 + 21 + 2 + + + PORTEI2 + Port Event Enable Input 2 + 23 + 1 + + + PID3 + Port Event Pin Identifier 3 + 24 + 5 + + + EVACT3 + Port Event Action 3 + 29 + 2 + + + PORTEI3 + Port Event Enable Input 3 + 31 + 1 + + + + + 16 + 1 + PMUX[%s] + Peripheral Multiplexing n + 0x30 + 8 + 0x00 + + + PMUXE + Peripheral Multiplexing for Even-Numbered Pin + 0 + 4 + + + PMUXO + Peripheral Multiplexing for Odd-Numbered Pin + 4 + 4 + + + + + 32 + 1 + PINCFG[%s] + Pin Configuration n + 0x40 + 8 + 0x00 + + + PMUXEN + Select Peripheral Multiplexer + 0 + 1 + + + INEN + Input Enable + 1 + 1 + + + PULLEN + Pull Enable + 2 + 1 + + + DRVSTR + Output Driver Strength Selection + 6 + 1 + + + + + + + + PORT_IOBUS + PORT_IOBUS_ + 0x60000000 + + + PTC + U22153.1.0 + Peripheral Touch Controller + PTC + PTC_ + 0x42005800 + + 0 + 0x1 + reserved + + + PTC + 30 + + + + RSTC + U22392.0.2 + Reset Controller + RSTC + RSTC_ + 0x40000C00 + + 0 + 0x1 + registers + + + + RCAUSE + Reset Cause + 0x0 + 8 + read-only + + + POR + Power On Reset + 0 + 1 + + + BODCORE + Brown Out CORE Detector Reset + 1 + 1 + + + BODVDD + Brown Out VDD Detector Reset + 2 + 1 + + + EXT + External Reset + 4 + 1 + + + WDT + Watchdog Reset + 5 + 1 + + + SYST + System Reset Request + 6 + 1 + + + + + + + RTC + U22501.1.1 + Real-Time Counter + RTC + RTC_ + 0x40002400 + + 0 + 0x25 + registers + + + RTC + 2 + + + + MODE0 + 32-bit Counter with Single 32-bit Compare + RtcMode0 + 0x0 + + CTRLA + MODE0 Control A + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 2 + + MODESelect + + COUNT32 + Mode 0: 32-bit Counter + 0x0 + + + COUNT16 + Mode 1: 16-bit Counter + 0x1 + + + CLOCK + Mode 2: Clock/Calendar + 0x2 + + + + + MATCHCLR + Clear on Match + 7 + 1 + + + PRESCALER + Prescaler + 8 + 4 + + PRESCALERSelect + + OFF + CLK_RTC_CNT = GCLK_RTC/1 + 0x0 + + + DIV1 + CLK_RTC_CNT = GCLK_RTC/1 + 0x1 + + + DIV2 + CLK_RTC_CNT = GCLK_RTC/2 + 0x2 + + + DIV4 + CLK_RTC_CNT = GCLK_RTC/4 + 0x3 + + + DIV8 + CLK_RTC_CNT = GCLK_RTC/8 + 0x4 + + + DIV16 + CLK_RTC_CNT = GCLK_RTC/16 + 0x5 + + + DIV32 + CLK_RTC_CNT = GCLK_RTC/32 + 0x6 + + + DIV64 + CLK_RTC_CNT = GCLK_RTC/64 + 0x7 + + + DIV128 + CLK_RTC_CNT = GCLK_RTC/128 + 0x8 + + + DIV256 + CLK_RTC_CNT = GCLK_RTC/256 + 0x9 + + + DIV512 + CLK_RTC_CNT = GCLK_RTC/512 + 0xA + + + DIV1024 + CLK_RTC_CNT = GCLK_RTC/1024 + 0xB + + + + + COUNTSYNC + Count Read Synchronization Enable + 15 + 1 + + + + + EVCTRL + MODE0 Event Control + 0x4 + 32 + 0x00000000 + + + PEREO0 + Periodic Interval 0 Event Output Enable + 0 + 1 + + + PEREO1 + Periodic Interval 1 Event Output Enable + 1 + 1 + + + PEREO2 + Periodic Interval 2 Event Output Enable + 2 + 1 + + + PEREO3 + Periodic Interval 3 Event Output Enable + 3 + 1 + + + PEREO4 + Periodic Interval 4 Event Output Enable + 4 + 1 + + + PEREO5 + Periodic Interval 5 Event Output Enable + 5 + 1 + + + PEREO6 + Periodic Interval 6 Event Output Enable + 6 + 1 + + + PEREO7 + Periodic Interval 7 Event Output Enable + 7 + 1 + + + CMPEO0 + Compare 0 Event Output Enable + 8 + 1 + + + OVFEO + Overflow Event Output Enable + 15 + 1 + + + + + INTENCLR + MODE0 Interrupt Enable Clear + 0x8 + 16 + 0x0000 + + + PER0 + Periodic Interval 0 Interrupt Enable + 0 + 1 + + + PER1 + Periodic Interval 1 Interrupt Enable + 1 + 1 + + + PER2 + Periodic Interval 2 Interrupt Enable + 2 + 1 + + + PER3 + Periodic Interval 3 Interrupt Enable + 3 + 1 + + + PER4 + Periodic Interval 4 Interrupt Enable + 4 + 1 + + + PER5 + Periodic Interval 5 Interrupt Enable + 5 + 1 + + + PER6 + Periodic Interval 6 Interrupt Enable + 6 + 1 + + + PER7 + Periodic Interval 7 Interrupt Enable + 7 + 1 + + + CMP0 + Compare 0 Interrupt Enable + 8 + 1 + + + OVF + Overflow Interrupt Enable + 15 + 1 + + + + + INTENSET + MODE0 Interrupt Enable Set + 0xA + 16 + 0x0000 + + + PER0 + Periodic Interval 0 Interrupt Enable + 0 + 1 + + + PER1 + Periodic Interval 1 Interrupt Enable + 1 + 1 + + + PER2 + Periodic Interval 2 Interrupt Enable + 2 + 1 + + + PER3 + Periodic Interval 3 Interrupt Enable + 3 + 1 + + + PER4 + Periodic Interval 4 Interrupt Enable + 4 + 1 + + + PER5 + Periodic Interval 5 Interrupt Enable + 5 + 1 + + + PER6 + Periodic Interval 6 Interrupt Enable + 6 + 1 + + + PER7 + Periodic Interval 7 Interrupt Enable + 7 + 1 + + + CMP0 + Compare 0 Interrupt Enable + 8 + 1 + + + OVF + Overflow Interrupt Enable + 15 + 1 + + + + + INTFLAG + MODE0 Interrupt Flag Status and Clear + 0xC + 16 + 0x0000 + + + PER0 + Periodic Interval 0 + 0 + 1 + + + PER1 + Periodic Interval 1 + 1 + 1 + + + PER2 + Periodic Interval 2 + 2 + 1 + + + PER3 + Periodic Interval 3 + 3 + 1 + + + PER4 + Periodic Interval 4 + 4 + 1 + + + PER5 + Periodic Interval 5 + 5 + 1 + + + PER6 + Periodic Interval 6 + 6 + 1 + + + PER7 + Periodic Interval 7 + 7 + 1 + + + CMP0 + Compare 0 + 8 + 1 + + + OVF + Overflow + 15 + 1 + + + + + DBGCTRL + Debug Control + 0xE + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + SYNCBUSY + MODE0 Synchronization Busy Status + 0x10 + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Busy + 0 + 1 + + + ENABLE + Enable Bit Busy + 1 + 1 + + + FREQCORR + FREQCORR Register Busy + 2 + 1 + + + COUNT + COUNT Register Busy + 3 + 1 + + + COMP0 + COMP 0 Register Busy + 5 + 1 + + + COUNTSYNC + Count Read Synchronization Enable Bit Busy + 15 + 1 + + + + + FREQCORR + Frequency Correction + 0x14 + 8 + 0x00 + + + VALUE + Correction Value + 0 + 7 + + + SIGN + Correction Sign + 7 + 1 + + + + + COUNT + MODE0 Counter Value + 0x18 + 32 + 0x00000000 + + + COUNT + Counter Value + 0 + 32 + + + + + COMP + MODE0 Compare n Value + 0x20 + 32 + 0x00000000 + + + COMP + Compare Value + 0 + 32 + + + + + + MODE1 + 16-bit Counter with Two 16-bit Compares + MODE0 + RtcMode1 + 0x0 + + CTRLA + MODE1 Control A + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 2 + + MODESelect + + COUNT32 + Mode 0: 32-bit Counter + 0 + + + COUNT16 + Mode 1: 16-bit Counter + 1 + + + CLOCK + Mode 2: Clock/Calendar + 2 + + + + + PRESCALER + Prescaler + 8 + 4 + + PRESCALERSelect + + OFF + CLK_RTC_CNT = GCLK_RTC/1 + 0 + + + DIV1 + CLK_RTC_CNT = GCLK_RTC/1 + 1 + + + DIV2 + CLK_RTC_CNT = GCLK_RTC/2 + 2 + + + DIV4 + CLK_RTC_CNT = GCLK_RTC/4 + 3 + + + DIV8 + CLK_RTC_CNT = GCLK_RTC/8 + 4 + + + DIV16 + CLK_RTC_CNT = GCLK_RTC/16 + 5 + + + DIV32 + CLK_RTC_CNT = GCLK_RTC/32 + 6 + + + DIV64 + CLK_RTC_CNT = GCLK_RTC/64 + 7 + + + DIV128 + CLK_RTC_CNT = GCLK_RTC/128 + 8 + + + DIV256 + CLK_RTC_CNT = GCLK_RTC/256 + 9 + + + DIV512 + CLK_RTC_CNT = GCLK_RTC/512 + 0xA + + + DIV1024 + CLK_RTC_CNT = GCLK_RTC/1024 + 0xB + + + + + COUNTSYNC + Count Read Synchronization Enable + 15 + 1 + + + + + EVCTRL + MODE1 Event Control + 0x4 + 32 + 0x00000000 + + + PEREO0 + Periodic Interval 0 Event Output Enable + 0 + 1 + + + PEREO1 + Periodic Interval 1 Event Output Enable + 1 + 1 + + + PEREO2 + Periodic Interval 2 Event Output Enable + 2 + 1 + + + PEREO3 + Periodic Interval 3 Event Output Enable + 3 + 1 + + + PEREO4 + Periodic Interval 4 Event Output Enable + 4 + 1 + + + PEREO5 + Periodic Interval 5 Event Output Enable + 5 + 1 + + + PEREO6 + Periodic Interval 6 Event Output Enable + 6 + 1 + + + PEREO7 + Periodic Interval 7 Event Output Enable + 7 + 1 + + + CMPEO0 + Compare 0 Event Output Enable + 8 + 1 + + + CMPEO1 + Compare 1 Event Output Enable + 9 + 1 + + + OVFEO + Overflow Event Output Enable + 15 + 1 + + + + + INTENCLR + MODE1 Interrupt Enable Clear + 0x8 + 16 + 0x0000 + + + PER0 + Periodic Interval 0 Interrupt Enable + 0 + 1 + + + PER1 + Periodic Interval 1 Interrupt Enable + 1 + 1 + + + PER2 + Periodic Interval 2 Interrupt Enable + 2 + 1 + + + PER3 + Periodic Interval 3 Interrupt Enable + 3 + 1 + + + PER4 + Periodic Interval 4 Interrupt Enable + 4 + 1 + + + PER5 + Periodic Interval 5 Interrupt Enable + 5 + 1 + + + PER6 + Periodic Interval 6 Interrupt Enable + 6 + 1 + + + PER7 + Periodic Interval 7 Interrupt Enable + 7 + 1 + + + CMP0 + Compare 0 Interrupt Enable + 8 + 1 + + + CMP1 + Compare 1 Interrupt Enable + 9 + 1 + + + OVF + Overflow Interrupt Enable + 15 + 1 + + + + + INTENSET + MODE1 Interrupt Enable Set + 0xA + 16 + 0x0000 + + + PER0 + Periodic Interval 0 Interrupt Enable + 0 + 1 + + + PER1 + Periodic Interval 1 Interrupt Enable + 1 + 1 + + + PER2 + Periodic Interval 2 Interrupt Enable + 2 + 1 + + + PER3 + Periodic Interval 3 Interrupt Enable + 3 + 1 + + + PER4 + Periodic Interval 4 Interrupt Enable + 4 + 1 + + + PER5 + Periodic Interval 5 Interrupt Enable + 5 + 1 + + + PER6 + Periodic Interval 6 Interrupt Enable + 6 + 1 + + + PER7 + Periodic Interval 7 Interrupt Enable + 7 + 1 + + + CMP0 + Compare 0 Interrupt Enable + 8 + 1 + + + CMP1 + Compare 1 Interrupt Enable + 9 + 1 + + + OVF + Overflow Interrupt Enable + 15 + 1 + + + + + INTFLAG + MODE1 Interrupt Flag Status and Clear + 0xC + 16 + 0x0000 + + + PER0 + Periodic Interval 0 + 0 + 1 + + + PER1 + Periodic Interval 1 + 1 + 1 + + + PER2 + Periodic Interval 2 + 2 + 1 + + + PER3 + Periodic Interval 3 + 3 + 1 + + + PER4 + Periodic Interval 4 + 4 + 1 + + + PER5 + Periodic Interval 5 + 5 + 1 + + + PER6 + Periodic Interval 6 + 6 + 1 + + + PER7 + Periodic Interval 7 + 7 + 1 + + + CMP0 + Compare 0 + 8 + 1 + + + CMP1 + Compare 1 + 9 + 1 + + + OVF + Overflow + 15 + 1 + + + + + DBGCTRL + Debug Control + 0xE + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + SYNCBUSY + MODE1 Synchronization Busy Status + 0x10 + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Bit Busy + 0 + 1 + + + ENABLE + Enable Bit Busy + 1 + 1 + + + FREQCORR + FREQCORR Register Busy + 2 + 1 + + + COUNT + COUNT Register Busy + 3 + 1 + + + PER + PER Register Busy + 4 + 1 + + + COMP0 + COMP 0 Register Busy + 5 + 1 + + + COMP1 + COMP 1 Register Busy + 6 + 1 + + + COUNTSYNC + Count Read Synchronization Enable Bit Busy + 15 + 1 + + + + + FREQCORR + Frequency Correction + 0x14 + 8 + 0x00 + + + VALUE + Correction Value + 0 + 7 + + + SIGN + Correction Sign + 7 + 1 + + + + + COUNT + MODE1 Counter Value + 0x18 + 16 + 0x0000 + + + COUNT + Counter Value + 0 + 16 + + + + + PER + MODE1 Counter Period + 0x1C + 16 + 0x0000 + + + PER + Counter Period + 0 + 16 + + + + + 2 + 2 + COMP[%s] + MODE1 Compare n Value + 0x20 + 16 + 0x0000 + + + COMP + Compare Value + 0 + 16 + + + + + + MODE2 + Clock/Calendar with Alarm + MODE0 + RtcMode2 + 0x0 + + CTRLA + MODE2 Control A + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 2 + + MODESelect + + COUNT32 + Mode 0: 32-bit Counter + 0 + + + COUNT16 + Mode 1: 16-bit Counter + 1 + + + CLOCK + Mode 2: Clock/Calendar + 2 + + + + + CLKREP + Clock Representation + 6 + 1 + + + MATCHCLR + Clear on Match + 7 + 1 + + + PRESCALER + Prescaler + 8 + 4 + + PRESCALERSelect + + OFF + CLK_RTC_CNT = GCLK_RTC/1 + 0x0 + + + DIV1 + CLK_RTC_CNT = GCLK_RTC/1 + 0x1 + + + DIV2 + CLK_RTC_CNT = GCLK_RTC/2 + 0x2 + + + DIV4 + CLK_RTC_CNT = GCLK_RTC/4 + 0x3 + + + DIV8 + CLK_RTC_CNT = GCLK_RTC/8 + 0x4 + + + DIV16 + CLK_RTC_CNT = GCLK_RTC/16 + 0x5 + + + DIV32 + CLK_RTC_CNT = GCLK_RTC/32 + 0x6 + + + DIV64 + CLK_RTC_CNT = GCLK_RTC/64 + 0x7 + + + DIV128 + CLK_RTC_CNT = GCLK_RTC/128 + 0x8 + + + DIV256 + CLK_RTC_CNT = GCLK_RTC/256 + 0x9 + + + DIV512 + CLK_RTC_CNT = GCLK_RTC/512 + 0xA + + + DIV1024 + CLK_RTC_CNT = GCLK_RTC/1024 + 0xB + + + + + CLOCKSYNC + Clock Read Synchronization Enable + 15 + 1 + + + + + EVCTRL + MODE2 Event Control + 0x4 + 32 + 0x00000000 + + + PEREO0 + Periodic Interval 0 Event Output Enable + 0 + 1 + + + PEREO1 + Periodic Interval 1 Event Output Enable + 1 + 1 + + + PEREO2 + Periodic Interval 2 Event Output Enable + 2 + 1 + + + PEREO3 + Periodic Interval 3 Event Output Enable + 3 + 1 + + + PEREO4 + Periodic Interval 4 Event Output Enable + 4 + 1 + + + PEREO5 + Periodic Interval 5 Event Output Enable + 5 + 1 + + + PEREO6 + Periodic Interval 6 Event Output Enable + 6 + 1 + + + PEREO7 + Periodic Interval 7 Event Output Enable + 7 + 1 + + + ALARMEO0 + Alarm 0 Event Output Enable + 8 + 1 + + + OVFEO + Overflow Event Output Enable + 15 + 1 + + + + + INTENCLR + MODE2 Interrupt Enable Clear + 0x8 + 16 + 0x0000 + + + PER0 + Periodic Interval 0 Interrupt Enable + 0 + 1 + + + PER1 + Periodic Interval 1 Interrupt Enable + 1 + 1 + + + PER2 + Periodic Interval 2 Interrupt Enable + 2 + 1 + + + PER3 + Periodic Interval 3 Interrupt Enable + 3 + 1 + + + PER4 + Periodic Interval 4 Interrupt Enable + 4 + 1 + + + PER5 + Periodic Interval 5 Interrupt Enable + 5 + 1 + + + PER6 + Periodic Interval 6 Interrupt Enable + 6 + 1 + + + PER7 + Periodic Interval 7 Interrupt Enable + 7 + 1 + + + ALARM0 + Alarm 0 Interrupt Enable + 8 + 1 + + + OVF + Overflow Interrupt Enable + 15 + 1 + + + + + INTENSET + MODE2 Interrupt Enable Set + 0xA + 16 + 0x0000 + + + PER0 + Periodic Interval 0 Enable + 0 + 1 + + + PER1 + Periodic Interval 1 Enable + 1 + 1 + + + PER2 + Periodic Interval 2 Enable + 2 + 1 + + + PER3 + Periodic Interval 3 Enable + 3 + 1 + + + PER4 + Periodic Interval 4 Enable + 4 + 1 + + + PER5 + Periodic Interval 5 Enable + 5 + 1 + + + PER6 + Periodic Interval 6 Enable + 6 + 1 + + + PER7 + Periodic Interval 7 Enable + 7 + 1 + + + ALARM0 + Alarm 0 Interrupt Enable + 8 + 1 + + + OVF + Overflow Interrupt Enable + 15 + 1 + + + + + INTFLAG + MODE2 Interrupt Flag Status and Clear + 0xC + 16 + 0x0000 + + + PER0 + Periodic Interval 0 + 0 + 1 + + + PER1 + Periodic Interval 1 + 1 + 1 + + + PER2 + Periodic Interval 2 + 2 + 1 + + + PER3 + Periodic Interval 3 + 3 + 1 + + + PER4 + Periodic Interval 4 + 4 + 1 + + + PER5 + Periodic Interval 5 + 5 + 1 + + + PER6 + Periodic Interval 6 + 6 + 1 + + + PER7 + Periodic Interval 7 + 7 + 1 + + + ALARM0 + Alarm 0 + 8 + 1 + + + OVF + Overflow + 15 + 1 + + + + + DBGCTRL + Debug Control + 0xE + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + SYNCBUSY + MODE2 Synchronization Busy Status + 0x10 + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Bit Busy + 0 + 1 + + + ENABLE + Enable Bit Busy + 1 + 1 + + + FREQCORR + FREQCORR Register Busy + 2 + 1 + + + CLOCK + CLOCK Register Busy + 3 + 1 + + + ALARM0 + ALARM 0 Register Busy + 5 + 1 + + + MASK0 + MASK 0 Register Busy + 11 + 1 + + + CLOCKSYNC + Clock Read Synchronization Enable Bit Busy + 15 + 1 + + + + + FREQCORR + Frequency Correction + 0x14 + 8 + 0x00 + + + VALUE + Correction Value + 0 + 7 + + + SIGN + Correction Sign + 7 + 1 + + + + + CLOCK + MODE2 Clock Value + 0x18 + 32 + 0x00000000 + + + SECOND + Second + 0 + 6 + + + MINUTE + Minute + 6 + 6 + + + HOUR + Hour + 12 + 5 + + HOURSelect + + AM + AM when CLKREP in 12-hour + 0x00 + + + PM + PM when CLKREP in 12-hour + 0x10 + + + + + DAY + Day + 17 + 5 + + + MONTH + Month + 22 + 4 + + + YEAR + Year + 26 + 6 + + + + + ALARM + MODE2_ALARM Alarm n Value + 0x20 + 32 + 0x00000000 + + + SECOND + Second + 0 + 6 + + + MINUTE + Minute + 6 + 6 + + + HOUR + Hour + 12 + 5 + + HOURSelect + + AM + Morning hour + 0x00 + + + PM + Afternoon hour + 0x10 + + + + + DAY + Day + 17 + 5 + + + MONTH + Month + 22 + 4 + + + YEAR + Year + 26 + 6 + + + + + MASK + MODE2_ALARM Alarm n Mask + 0x24 + 8 + 0x00 + + + SEL + Alarm Mask Selection + 0 + 3 + + SELSelect + + OFF + Alarm Disabled + 0x0 + + + SS + Match seconds only + 0x1 + + + MMSS + Match seconds and minutes only + 0x2 + + + HHMMSS + Match seconds, minutes, and hours only + 0x3 + + + DDHHMMSS + Match seconds, minutes, hours, and days only + 0x4 + + + MMDDHHMMSS + Match seconds, minutes, hours, days, and months only + 0x5 + + + YYMMDDHHMMSS + Match seconds, minutes, hours, days, months, and years + 0x6 + + + + + + + + + + SDADC + U22601.0.1 + Sigma-Delta Analog Digital Converter + SDADC + SDADC_ + 0x42004C00 + + 0 + 0x2F + registers + + + SDADC + 29 + + + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + RUNSTDBY + Run during Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + + + REFCTRL + Reference Control + 0x1 + 8 + 0x00 + + + REFSEL + Reference Selection + 0 + 2 + + REFSELSelect + + INTREF + Internal Bandgap Reference + 0 + + + AREFB + External Reference + 1 + + + DAC + Internal DAC Output + 2 + + + INTVCC + VDDANA + 3 + + + + + REFRANGE + Reference Range + 4 + 2 + + + ONREFBUF + Reference Buffer + 7 + 1 + + + + + CTRLB + Control B + 0x2 + 16 + 0x2000 + + + PRESCALER + Prescaler Configuration + 0 + 8 + + PRESCALERSelect + + DIV2 + Peripheral clock divided by 2 + 0x0 + + + DIV4 + Peripheral clock divided by 4 + 0x1 + + + DIV8 + Peripheral clock divided by 8 + 0x2 + + + DIV16 + Peripheral clock divided by 16 + 0x3 + + + DIV32 + Peripheral clock divided by 32 + 0x4 + + + DIV64 + Peripheral clock divided by 64 + 0x5 + + + DIV128 + Peripheral clock divided by 128 + 0x6 + + + DIV256 + Peripheral clock divided by 256 + 0x7 + + + + + OSR + Over Sampling Ratio + 8 + 3 + + OSRSelect + + OSR64 + Over Sampling Ratio is 64 + 0x0 + + + OSR128 + Over Sampling Ratio is 128 + 0x1 + + + OSR256 + Over Sampling Ratio is 256 + 0x2 + + + OSR512 + Over Sampling Ratio is 512 + 0x3 + + + OSR1024 + Over Sampling Ratio is 1024 + 0x4 + + + + + SKPCNT + Skip Sample Count + 12 + 4 + + + + + EVCTRL + Event Control + 0x4 + 8 + 0x00 + + + FLUSHEI + Flush Event Input Enable + 0 + 1 + + + STARTEI + Start Conversion Event Input Enable + 1 + 1 + + + FLUSHINV + Flush Event Invert Enable + 2 + 1 + + + STARTINV + Satrt Event Invert Enable + 3 + 1 + + + RESRDYEO + Result Ready Event Out + 4 + 1 + + + WINMONEO + Window Monitor Event Out + 5 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x5 + 8 + 0x00 + + + RESRDY + Result Ready Interrupt Disable + 0 + 1 + + + OVERRUN + Overrun Interrupt Disable + 1 + 1 + + + WINMON + Window Monitor Interrupt Disable + 2 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x6 + 8 + 0x00 + + + RESRDY + Result Ready Interrupt Enable + 0 + 1 + + + OVERRUN + Overrun Interrupt Enable + 1 + 1 + + + WINMON + Window Monitor Interrupt Enable + 2 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x7 + 8 + 0x00 + + + RESRDY + Result Ready Interrupt Flag + 0 + 1 + + + OVERRUN + Overrun Interrupt Flag + 1 + 1 + + + WINMON + Window Monitor Interrupt Flag + 2 + 1 + + + + + SEQSTATUS + Sequence Status + 0x8 + 8 + read-only + 0x00 + + + SEQSTATE + Sequence State + 0 + 4 + + + SEQBUSY + Sequence Busy + 7 + 1 + + + + + INPUTCTRL + Input Control + 0x9 + 8 + 0x00 + + + MUXSEL + SDADC Input Selection + 0 + 4 + + MUXSELSelect + + AIN0 + SDADC AIN0 Pin + 0x0 + + + AIN1 + SDADC AIN1 Pin + 0x1 + + + AIN2 + SDADC AIN2 Pin + 0x2 + + + + + + + CTRLC + Control C + 0xA + 8 + 0x00 + + + FREERUN + Free Running Mode + 0 + 1 + + + + + WINCTRL + Window Monitor Control + 0xB + 8 + 0x00 + + + WINMODE + Window Monitor Mode + 0 + 3 + + + + + WINLT + Window Monitor Lower Threshold + 0xC + 32 + 0x00000000 + + + WINLT + Window Lower Threshold + 0 + 24 + + + + + WINUT + Window Monitor Upper Threshold + 0x10 + 32 + 0x00000000 + + + WINUT + Window Upper Threshold + 0 + 24 + + + + + OFFSETCORR + Offset Correction + 0x14 + 32 + 0x00000000 + + + OFFSETCORR + Offset Correction Value + 0 + 24 + + + + + GAINCORR + Gain Correction + 0x18 + 16 + 0x0001 + + + GAINCORR + Gain Correction Value + 0 + 14 + + + + + SHIFTCORR + Shift Correction + 0x1A + 8 + 0x00 + + + SHIFTCORR + Shift Correction Value + 0 + 4 + + + + + SWTRIG + Software Trigger + 0x1C + 8 + 0x00 + + + FLUSH + SDADC Flush + 0 + 1 + + + START + Start SDADC Conversion + 1 + 1 + + + + + SYNCBUSY + Synchronization Busy + 0x20 + 32 + read-only + 0x00000000 + + + SWRST + SWRST Synchronization Busy + 0 + 1 + + + ENABLE + ENABLE Synchronization Busy + 1 + 1 + + + CTRLC + CTRLC Synchronization Busy + 2 + 1 + + + INPUTCTRL + INPUTCTRL Synchronization Busy + 3 + 1 + + + WINCTRL + WINCTRL Synchronization Busy + 4 + 1 + + + WINLT + WINLT Synchronization Busy + 5 + 1 + + + WINUT + WINUT Synchronization Busy + 6 + 1 + + + OFFSETCORR + OFFSETCTRL Synchronization Busy + 7 + 1 + + + GAINCORR + GAINCORR Synchronization Busy + 8 + 1 + + + SHIFTCORR + SHIFTCORR Synchronization Busy + 9 + 1 + + + SWTRIG + SWTRG Synchronization Busy + 10 + 1 + + + ANACTRL + ANACTRL Synchronization Busy + 11 + 1 + + + + + RESULT + Result + 0x24 + 32 + read-only + 0x00000000 + + + RESULT + Result Value + 0 + 24 + + + RESERVED + 24 + 8 + + + + + SEQCTRL + Sequence Control + 0x28 + 8 + 0x00 + + + SEQEN + Enable Positive Input in the Sequence + 0 + 3 + + + + + ANACTRL + Analog Control + 0x2C + 8 + 0x00 + + + CTRSDADC + SDADC Control + 0 + 6 + + + ONCHOP + Chopper + 6 + 1 + + + BUFTEST + BUFTEST + 7 + 1 + + + + + DBGCTRL + Debug Control + 0x2E + 8 + 0x00 + + + DBGRUN + Debug Run + 0 + 1 + + + + + + + SERCOM0 + U22013.1.1 + Serial Communication Interface + SERCOM + SERCOM_ + 0x42000400 + + 0 + 0x31 + registers + + + SERCOM0 + 9 + + + + I2CM + I2C Master Mode + SercomI2cm + 0x0 + + CTRLA + I2CM Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run in Standby + 7 + 1 + + + PINOUT + Pin Usage + 16 + 1 + + + SDAHOLD + SDA Hold Time + 20 + 2 + + SDAHOLDSelect + + DISABLE + Disabled + 0x0 + + + 75NS + 50-100ns hold time + 0x1 + + + 450NS + 300-600ns hold time + 0x2 + + + 600NS + 400-800ns hold time + 0x3 + + + + + MEXTTOEN + Master SCL Low Extend Timeout + 22 + 1 + + + SEXTTOEN + Slave SCL Low Extend Timeout + 23 + 1 + + + SPEED + Transfer Speed + 24 + 2 + + SPEEDSelect + + STANDARD_AND_FAST_MODE + Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz + 0x0 + + + FASTPLUS_MODE + Fast-mode Plus Upto 1MHz + 0x1 + + + HIGH_SPEED_MODE + High-speed mode Upto 3.4MHz + 0x2 + + + + + SCLSM + SCL Clock Stretch Mode + 27 + 1 + + + INACTOUT + Inactive Time-Out + 28 + 2 + + INACTOUTSelect + + DISABLE + Disabled + 0x0 + + + 55US + 5-6 SCL Time-Out(50-60us) + 0x1 + + + 105US + 10-11 SCL Time-Out(100-110us) + 0x2 + + + 205US + 20-21 SCL Time-Out(200-210us) + 0x3 + + + + + LOWTOUTEN + SCL Low Timeout Enable + 30 + 1 + + + + + CTRLB + I2CM Control B + 0x4 + 32 + 0x00000000 + + + SMEN + Smart Mode Enable + 8 + 1 + + + QCEN + Quick Command Enable + 9 + 1 + + + CMD + Command + 16 + 2 + + + ACKACT + Acknowledge Action + 18 + 1 + + + + + BAUD + I2CM Baud Rate + 0xC + 32 + 0x00000000 + + + BAUD + Baud Rate Value + 0 + 8 + + + BAUDLOW + Baud Rate Value Low + 8 + 8 + + + HSBAUD + High Speed Baud Rate Value + 16 + 8 + + + HSBAUDLOW + High Speed Baud Rate Value Low + 24 + 8 + + + + + INTENCLR + I2CM Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + MB + Master On Bus Interrupt Disable + 0 + 1 + + + SB + Slave On Bus Interrupt Disable + 1 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + I2CM Interrupt Enable Set + 0x16 + 8 + 0x00 + + + MB + Master On Bus Interrupt Enable + 0 + 1 + + + SB + Slave On Bus Interrupt Enable + 1 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + I2CM Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + MB + Master On Bus Interrupt + 0 + 1 + + + SB + Slave On Bus Interrupt + 1 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + I2CM Status + 0x1A + 16 + 0x0000 + + + BUSERR + Bus Error + 0 + 1 + + + ARBLOST + Arbitration Lost + 1 + 1 + + + RXNACK + Received Not Acknowledge + 2 + 1 + + + BUSSTATE + Bus State + 4 + 2 + + + LOWTOUT + SCL Low Timeout + 6 + 1 + + + CLKHOLD + Clock Hold + 7 + 1 + + + MEXTTOUT + Master SCL Low Extend Timeout + 8 + 1 + + + SEXTTOUT + Slave SCL Low Extend Timeout + 9 + 1 + + + LENERR + Length Error + 10 + 1 + + + + + SYNCBUSY + I2CM Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + SYSOP + System Operation Synchronization Busy + 2 + 1 + + + + + ADDR + I2CM Address + 0x24 + 32 + 0x00000000 + + + ADDR + Address Value + 0 + 11 + + + LENEN + Length Enable + 13 + 1 + + + HS + High Speed Mode + 14 + 1 + + + TENBITEN + Ten Bit Addressing Enable + 15 + 1 + + + LEN + Length + 16 + 8 + + + + + DATA + I2CM Data + 0x28 + 8 + 0x00 + + + DATA + Data Value + 0 + 8 + + + + + DBGCTRL + I2CM Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + I2CS + I2C Slave Mode + I2CM + SercomI2cs + 0x0 + + CTRLA + I2CS Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + PINOUT + Pin Usage + 16 + 1 + + + SDAHOLD + SDA Hold Time + 20 + 2 + + SDAHOLDSelect + + DISABLE + Disabled + 0x0 + + + 75NS + 50-100ns hold time + 0x1 + + + 450NS + 300-600ns hold time + 0x2 + + + 600NS + 400-800ns hold time + 0x3 + + + + + SEXTTOEN + Slave SCL Low Extend Timeout + 23 + 1 + + + SPEED + Transfer Speed + 24 + 2 + + SPEEDSelect + + STANDARD_AND_FAST_MODE + Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz + 0x0 + + + FASTPLUS_MODE + Fast-mode Plus Upto 1MHz + 0x1 + + + HIGH_SPEED_MODE + High-speed mode Upto 3.4MHz + 0x2 + + + + + SCLSM + SCL Clock Stretch Mode + 27 + 1 + + + LOWTOUTEN + SCL Low Timeout Enable + 30 + 1 + + + + + CTRLB + I2CS Control B + 0x4 + 32 + 0x00000000 + + + SMEN + Smart Mode Enable + 8 + 1 + + + GCMD + PMBus Group Command + 9 + 1 + + + AACKEN + Automatic Address Acknowledge + 10 + 1 + + + AMODE + Address Mode + 14 + 2 + + + CMD + Command + 16 + 2 + + + ACKACT + Acknowledge Action + 18 + 1 + + + + + INTENCLR + I2CS Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + PREC + Stop Received Interrupt Disable + 0 + 1 + + + AMATCH + Address Match Interrupt Disable + 1 + 1 + + + DRDY + Data Interrupt Disable + 2 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + I2CS Interrupt Enable Set + 0x16 + 8 + 0x00 + + + PREC + Stop Received Interrupt Enable + 0 + 1 + + + AMATCH + Address Match Interrupt Enable + 1 + 1 + + + DRDY + Data Interrupt Enable + 2 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + I2CS Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + PREC + Stop Received Interrupt + 0 + 1 + + + AMATCH + Address Match Interrupt + 1 + 1 + + + DRDY + Data Interrupt + 2 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + I2CS Status + 0x1A + 16 + 0x0000 + + + BUSERR + Bus Error + 0 + 1 + + + COLL + Transmit Collision + 1 + 1 + + + RXNACK + Received Not Acknowledge + 2 + 1 + + + DIR + Read/Write Direction + 3 + 1 + + + SR + Repeated Start + 4 + 1 + + + LOWTOUT + SCL Low Timeout + 6 + 1 + + + CLKHOLD + Clock Hold + 7 + 1 + + + SEXTTOUT + Slave SCL Low Extend Timeout + 9 + 1 + + + HS + High Speed + 10 + 1 + + + + + SYNCBUSY + I2CS Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + + + ADDR + I2CS Address + 0x24 + 32 + 0x00000000 + + + GENCEN + General Call Address Enable + 0 + 1 + + + ADDR + Address Value + 1 + 10 + + + TENBITEN + Ten Bit Addressing Enable + 15 + 1 + + + ADDRMASK + Address Mask + 17 + 10 + + + + + DATA + I2CS Data + 0x28 + 8 + 0x00 + + + DATA + Data Value + 0 + 8 + + + + + + SPIS + SPI Slave Mode + I2CM + SercomSpis + 0x0 + + CTRLA + SPIS Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + IBON + Immediate Buffer Overflow Notification + 8 + 1 + + + DOPO + Data Out Pinout + 16 + 2 + + DOPOSelect + + PAD0 + DO on PAD[0], SCK on PAD[1] and SS on PAD[2] + 0x0 + + + PAD1 + DO on PAD[2], SCK on PAD[3] and SS on PAD[1] + 0x1 + + + PAD2 + DO on PAD[3], SCK on PAD[1] and SS on PAD[2] + 0x2 + + + PAD3 + DO on PAD[0], SCK on PAD[3] and SS on PAD[1] + 0x3 + + + + + DIPO + Data In Pinout + 20 + 2 + + DIPOSelect + + PAD0 + SERCOM PAD[0] + 0x0 + + + PAD1 + SERCOM PAD[1] + 0x1 + + + PAD2 + SERCOM PAD[2] + 0x2 + + + PAD3 + SERCOM PAD[3] + 0x3 + + + + + FORM + Frame Format + 24 + 4 + + FORMSelect + + SPI_FRAME + SPI Frame + 0x0 + + + SPI_FRAME_WITH_ADDR + SPI Frame with Addr + 0x2 + + + + + CPHA + Clock Phase + 28 + 1 + + CPHASelect + + LEADING_EDGE + The data is sampled on a leading SCK edge and changed on a trailing SCK edge + 0x0 + + + TRAILING_EDGE + The data is sampled on a trailing SCK edge and changed on a leading SCK edge + 0x1 + + + + + CPOL + Clock Polarity + 29 + 1 + + CPOLSelect + + IDLE_LOW + SCK is low when idle + 0x0 + + + IDLE_HIGH + SCK is high when idle + 0x1 + + + + + DORD + Data Order + 30 + 1 + + DORDSelect + + MSB + MSB is transferred first + 0x0 + + + LSB + LSB is transferred first + 0x1 + + + + + + + CTRLB + SPIS Control B + 0x4 + 32 + 0x00000000 + + + CHSIZE + Character Size + 0 + 3 + + CHSIZESelect + + 8_BIT + 8 bits + 0x0 + + + 9_BIT + 9 bits + 0x1 + + + + + PLOADEN + Data Preload Enable + 6 + 1 + + + SSDE + Slave Select Low Detect Enable + 9 + 1 + + + MSSEN + Master Slave Select Enable + 13 + 1 + + + AMODE + Address Mode + 14 + 2 + + AMODESelect + + MASK + SPI Address mask + 0x0 + + + 2_ADDRESSES + Two unique Addressess + 0x1 + + + RANGE + Address Range + 0x2 + + + + + RXEN + Receiver Enable + 17 + 1 + + + + + BAUD + SPIS Baud Rate + 0xC + 8 + 0x00 + + + BAUD + Baud Rate Value + 0 + 8 + + + + + INTENCLR + SPIS Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Disable + 0 + 1 + + + TXC + Transmit Complete Interrupt Disable + 1 + 1 + + + RXC + Receive Complete Interrupt Disable + 2 + 1 + + + SSL + Slave Select Low Interrupt Disable + 3 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + SPIS Interrupt Enable Set + 0x16 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Enable + 0 + 1 + + + TXC + Transmit Complete Interrupt Enable + 1 + 1 + + + RXC + Receive Complete Interrupt Enable + 2 + 1 + + + SSL + Slave Select Low Interrupt Enable + 3 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + SPIS Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt + 0 + 1 + + + TXC + Transmit Complete Interrupt + 1 + 1 + + + RXC + Receive Complete Interrupt + 2 + 1 + + + SSL + Slave Select Low Interrupt Flag + 3 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + SPIS Status + 0x1A + 16 + 0x0000 + + + BUFOVF + Buffer Overflow + 2 + 1 + + + + + SYNCBUSY + SPIS Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + CTRLB + CTRLB Synchronization Busy + 2 + 1 + + + + + ADDR + SPIS Address + 0x24 + 32 + 0x00000000 + + + ADDR + Address Value + 0 + 8 + + + ADDRMASK + Address Mask + 16 + 8 + + + + + DATA + SPIS Data + 0x28 + 32 + 0x00000000 + + + DATA + Data Value + 0 + 9 + + + + + DBGCTRL + SPIS Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + SPIM + SPI Master Mode + I2CM + SercomSpim + 0x0 + + CTRLA + SPIM Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + IBON + Immediate Buffer Overflow Notification + 8 + 1 + + + DOPO + Data Out Pinout + 16 + 2 + + DOPOSelect + + PAD0 + DO on PAD[0], SCK on PAD[1] and SS on PAD[2] + 0x0 + + + PAD1 + DO on PAD[2], SCK on PAD[3] and SS on PAD[1] + 0x1 + + + PAD2 + DO on PAD[3], SCK on PAD[1] and SS on PAD[2] + 0x2 + + + PAD3 + DO on PAD[0], SCK on PAD[3] and SS on PAD[1] + 0x3 + + + + + DIPO + Data In Pinout + 20 + 2 + + DIPOSelect + + PAD0 + SERCOM PAD[0] + 0x0 + + + PAD1 + SERCOM PAD[1] + 0x1 + + + PAD2 + SERCOM PAD[2] + 0x2 + + + PAD3 + SERCOM PAD[3] + 0x3 + + + + + FORM + Frame Format + 24 + 4 + + FORMSelect + + SPI_FRAME + SPI Frame + 0x0 + + + SPI_FRAME_WITH_ADDR + SPI Frame with Addr + 0x2 + + + + + CPHA + Clock Phase + 28 + 1 + + CPHASelect + + LEADING_EDGE + The data is sampled on a leading SCK edge and changed on a trailing SCK edge + 0x0 + + + TRAILING_EDGE + The data is sampled on a trailing SCK edge and changed on a leading SCK edge + 0x1 + + + + + CPOL + Clock Polarity + 29 + 1 + + CPOLSelect + + IDLE_LOW + SCK is low when idle + 0x0 + + + IDLE_HIGH + SCK is high when idle + 0x1 + + + + + DORD + Data Order + 30 + 1 + + DORDSelect + + MSB + MSB is transferred first + 0x0 + + + LSB + LSB is transferred first + 0x1 + + + + + + + CTRLB + SPIM Control B + 0x4 + 32 + 0x00000000 + + + CHSIZE + Character Size + 0 + 3 + + CHSIZESelect + + 8_BIT + 8 bits + 0x0 + + + 9_BIT + 9 bits + 0x1 + + + + + PLOADEN + Data Preload Enable + 6 + 1 + + + SSDE + Slave Select Low Detect Enable + 9 + 1 + + + MSSEN + Master Slave Select Enable + 13 + 1 + + + AMODE + Address Mode + 14 + 2 + + AMODESelect + + MASK + SPI Address mask + 0x0 + + + 2_ADDRESSES + Two unique Addressess + 0x1 + + + RANGE + Address Range + 0x2 + + + + + RXEN + Receiver Enable + 17 + 1 + + + + + BAUD + SPIM Baud Rate + 0xC + 8 + 0x00 + + + BAUD + Baud Rate Value + 0 + 8 + + + + + INTENCLR + SPIM Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Disable + 0 + 1 + + + TXC + Transmit Complete Interrupt Disable + 1 + 1 + + + RXC + Receive Complete Interrupt Disable + 2 + 1 + + + SSL + Slave Select Low Interrupt Disable + 3 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + SPIM Interrupt Enable Set + 0x16 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Enable + 0 + 1 + + + TXC + Transmit Complete Interrupt Enable + 1 + 1 + + + RXC + Receive Complete Interrupt Enable + 2 + 1 + + + SSL + Slave Select Low Interrupt Enable + 3 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + SPIM Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt + 0 + 1 + + + TXC + Transmit Complete Interrupt + 1 + 1 + + + RXC + Receive Complete Interrupt + 2 + 1 + + + SSL + Slave Select Low Interrupt Flag + 3 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + SPIM Status + 0x1A + 16 + 0x0000 + + + BUFOVF + Buffer Overflow + 2 + 1 + + + + + SYNCBUSY + SPIM Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + CTRLB + CTRLB Synchronization Busy + 2 + 1 + + + + + ADDR + SPIM Address + 0x24 + 32 + 0x00000000 + + + ADDR + Address Value + 0 + 8 + + + ADDRMASK + Address Mask + 16 + 8 + + + + + DATA + SPIM Data + 0x28 + 32 + 0x00000000 + + + DATA + Data Value + 0 + 9 + + + + + DBGCTRL + SPIM Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + USART_EXT + USART EXTERNAL CLOCK Mode + I2CM + SercomUsart_ext + 0x0 + + CTRLA + USART_EXT Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + IBON + Immediate Buffer Overflow Notification + 8 + 1 + + + SAMPR + Sample + 13 + 3 + + SAMPRSelect + + 16X_ARITHMETIC + 16x over-sampling using arithmetic baudrate generation + 0x0 + + + 16X_FRACTIONAL + 16x over-sampling using fractional baudrate generation + 0x1 + + + 8X_ARITHMETIC + 8x over-sampling using arithmetic baudrate generation + 0x2 + + + 8X_FRACTIONAL + 8x over-sampling using fractional baudrate generation + 0x3 + + + 3X_ARITHMETIC + 3x over-sampling using arithmetic baudrate generation + 0x4 + + + + + TXPO + Transmit Data Pinout + 16 + 2 + + TXPOSelect + + PAD0 + SERCOM PAD[0] is used for data transmission + 0x0 + + + PAD2 + SERCOM PAD[2] is used for data transmission + 0x1 + + + + + RXPO + Receive Data Pinout + 20 + 2 + + RXPOSelect + + PAD0 + SERCOM PAD[0] is used for data reception + 0x0 + + + PAD1 + SERCOM PAD[1] is used for data reception + 0x1 + + + PAD2 + SERCOM PAD[2] is used for data reception + 0x2 + + + PAD3 + SERCOM PAD[3] is used for data reception + 0x3 + + + + + SAMPA + Sample Adjustment + 22 + 2 + + + FORM + Frame Format + 24 + 4 + + FORMSelect + + USART_FRAME_NO_PARITY + USART frame + 0x0 + + + USART_FRAME_WITH_PARITY + USART frame with parity + 0x1 + + + USART_FRAME_LIN_MASTER_MODE + LIN Master - Break and sync generation + 0x2 + + + USART_FRAME_AUTO_BAUD_NO_PARITY + Auto-baud - break detection and auto-baud + 0x4 + + + USART_FRAME_AUTO_BAUD_WITH_PARITY + Auto-baud - break detection and auto-baud with parity + 0x5 + + + + + CMODE + Communication Mode + 28 + 1 + + CMODESelect + + ASYNC + Asynchronous Communication + 0x0 + + + SYNC + Synchronous Communication + 0x1 + + + + + CPOL + Clock Polarity + 29 + 1 + + CPOLSelect + + IDLE_LOW + TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge + 0x0 + + + IDLE_HIGH + TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge + 0x1 + + + + + DORD + Data Order + 30 + 1 + + DORDSelect + + MSB + MSB is transmitted first + 0x0 + + + LSB + LSB is transmitted first + 0x1 + + + + + + + CTRLB + USART_EXT Control B + 0x4 + 32 + 0x00000000 + + + CHSIZE + Character Size + 0 + 3 + + CHSIZESelect + + 8_BIT + 8 Bits + 0x0 + + + 9_BIT + 9 Bits + 0x1 + + + 5_BIT + 5 Bits + 0x5 + + + 6_BIT + 6 Bits + 0x6 + + + 7_BIT + 7 Bits + 0x7 + + + + + SBMODE + Stop Bit Mode + 6 + 1 + + SBMODESelect + + 1_BIT + One Stop Bit + 0x0 + + + 2_BIT + Two Stop Bits + 0x1 + + + + + COLDEN + Collision Detection Enable + 8 + 1 + + + SFDE + Start of Frame Detection Enable + 9 + 1 + + + ENC + Encoding Format + 10 + 1 + + + PMODE + Parity Mode + 13 + 1 + + PMODESelect + + EVEN + Even Parity + 0x0 + + + ODD + Odd Parity + 0x1 + + + + + TXEN + Transmitter Enable + 16 + 1 + + + RXEN + Receiver Enable + 17 + 1 + + + LINCMD + LIN Command + 24 + 2 + + + + + CTRLC + USART_EXT Control C + 0x8 + 32 + 0x00000000 + + + GTIME + RS485 Guard Time + 0 + 3 + + + BRKLEN + LIN Master Break Length + 8 + 2 + + + HDRDLY + LIN Master Header Delay + 10 + 2 + + + + + BAUD + USART_EXT Baud Rate + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 16 + + + + + BAUD_FRAC_MODE + USART_EXT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 13 + + + FP + Fractional Part + 13 + 3 + + + + + BAUD_FRACFP_MODE + USART_EXT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 13 + + + FP + Fractional Part + 13 + 3 + + + + + BAUD_USARTFP_MODE + USART_EXT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 16 + + + + + RXPL + USART_EXT Receive Pulse Length + 0xE + 8 + 0x00 + + + RXPL + Receive Pulse Length + 0 + 8 + + + + + INTENCLR + USART_EXT Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Disable + 0 + 1 + + + TXC + Transmit Complete Interrupt Disable + 1 + 1 + + + RXC + Receive Complete Interrupt Disable + 2 + 1 + + + RXS + Receive Start Interrupt Disable + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt Disable + 4 + 1 + + + RXBRK + Break Received Interrupt Disable + 5 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + USART_EXT Interrupt Enable Set + 0x16 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Enable + 0 + 1 + + + TXC + Transmit Complete Interrupt Enable + 1 + 1 + + + RXC + Receive Complete Interrupt Enable + 2 + 1 + + + RXS + Receive Start Interrupt Enable + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt Enable + 4 + 1 + + + RXBRK + Break Received Interrupt Enable + 5 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + USART_EXT Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt + 0 + 1 + + + TXC + Transmit Complete Interrupt + 1 + 1 + + + RXC + Receive Complete Interrupt + 2 + 1 + + + RXS + Receive Start Interrupt + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt + 4 + 1 + + + RXBRK + Break Received Interrupt + 5 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + USART_EXT Status + 0x1A + 16 + 0x0000 + + + PERR + Parity Error + 0 + 1 + + + FERR + Frame Error + 1 + 1 + + + BUFOVF + Buffer Overflow + 2 + 1 + + + CTS + Clear To Send + 3 + 1 + + + ISF + Inconsistent Sync Field + 4 + 1 + + + COLL + Collision Detected + 5 + 1 + + + TXE + Transmitter Empty + 6 + 1 + + + + + SYNCBUSY + USART_EXT Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + CTRLB + CTRLB Synchronization Busy + 2 + 1 + + + + + DATA + USART_EXT Data + 0x28 + 16 + 0x0000 + + + DATA + Data Value + 0 + 9 + + + + + DBGCTRL + USART_EXT Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + USART_INT + USART INTERNAL CLOCK Mode + I2CM + SercomUsart_int + 0x0 + + CTRLA + USART_INT Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + IBON + Immediate Buffer Overflow Notification + 8 + 1 + + + SAMPR + Sample + 13 + 3 + + SAMPRSelect + + 16X_ARITHMETIC + 16x over-sampling using arithmetic baudrate generation + 0x0 + + + 16X_FRACTIONAL + 16x over-sampling using fractional baudrate generation + 0x1 + + + 8X_ARITHMETIC + 8x over-sampling using arithmetic baudrate generation + 0x2 + + + 8X_FRACTIONAL + 8x over-sampling using fractional baudrate generation + 0x3 + + + 3X_ARITHMETIC + 3x over-sampling using arithmetic baudrate generation + 0x4 + + + + + TXPO + Transmit Data Pinout + 16 + 2 + + TXPOSelect + + PAD0 + SERCOM PAD[0] is used for data transmission + 0x0 + + + PAD2 + SERCOM PAD[2] is used for data transmission + 0x1 + + + + + RXPO + Receive Data Pinout + 20 + 2 + + RXPOSelect + + PAD0 + SERCOM PAD[0] is used for data reception + 0x0 + + + PAD1 + SERCOM PAD[1] is used for data reception + 0x1 + + + PAD2 + SERCOM PAD[2] is used for data reception + 0x2 + + + PAD3 + SERCOM PAD[3] is used for data reception + 0x3 + + + + + SAMPA + Sample Adjustment + 22 + 2 + + + FORM + Frame Format + 24 + 4 + + FORMSelect + + USART_FRAME_NO_PARITY + USART frame + 0x0 + + + USART_FRAME_WITH_PARITY + USART frame with parity + 0x1 + + + USART_FRAME_LIN_MASTER_MODE + LIN Master - Break and sync generation + 0x2 + + + USART_FRAME_AUTO_BAUD_NO_PARITY + Auto-baud - break detection and auto-baud + 0x4 + + + USART_FRAME_AUTO_BAUD_WITH_PARITY + Auto-baud - break detection and auto-baud with parity + 0x5 + + + + + CMODE + Communication Mode + 28 + 1 + + CMODESelect + + ASYNC + Asynchronous Communication + 0x0 + + + SYNC + Synchronous Communication + 0x1 + + + + + CPOL + Clock Polarity + 29 + 1 + + CPOLSelect + + IDLE_LOW + TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge + 0x0 + + + IDLE_HIGH + TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge + 0x1 + + + + + DORD + Data Order + 30 + 1 + + DORDSelect + + MSB + MSB is transmitted first + 0x0 + + + LSB + LSB is transmitted first + 0x1 + + + + + + + CTRLB + USART_INT Control B + 0x4 + 32 + 0x00000000 + + + CHSIZE + Character Size + 0 + 3 + + CHSIZESelect + + 8_BIT + 8 Bits + 0x0 + + + 9_BIT + 9 Bits + 0x1 + + + 5_BIT + 5 Bits + 0x5 + + + 6_BIT + 6 Bits + 0x6 + + + 7_BIT + 7 Bits + 0x7 + + + + + SBMODE + Stop Bit Mode + 6 + 1 + + SBMODESelect + + 1_BIT + One Stop Bit + 0x0 + + + 2_BIT + Two Stop Bits + 0x1 + + + + + COLDEN + Collision Detection Enable + 8 + 1 + + + SFDE + Start of Frame Detection Enable + 9 + 1 + + + ENC + Encoding Format + 10 + 1 + + + PMODE + Parity Mode + 13 + 1 + + PMODESelect + + EVEN + Even Parity + 0x0 + + + ODD + Odd Parity + 0x1 + + + + + TXEN + Transmitter Enable + 16 + 1 + + + RXEN + Receiver Enable + 17 + 1 + + + LINCMD + LIN Command + 24 + 2 + + + + + CTRLC + USART_INT Control C + 0x8 + 32 + 0x00000000 + + + GTIME + RS485 Guard Time + 0 + 3 + + + BRKLEN + LIN Master Break Length + 8 + 2 + + + HDRDLY + LIN Master Header Delay + 10 + 2 + + + + + BAUD + USART_INT Baud Rate + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 16 + + + + + BAUD_FRAC_MODE + USART_INT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 13 + + + FP + Fractional Part + 13 + 3 + + + + + BAUD_FRACFP_MODE + USART_INT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 13 + + + FP + Fractional Part + 13 + 3 + + + + + BAUD_USARTFP_MODE + USART_INT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 16 + + + + + RXPL + USART_INT Receive Pulse Length + 0xE + 8 + 0x00 + + + RXPL + Receive Pulse Length + 0 + 8 + + + + + INTENCLR + USART_INT Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Disable + 0 + 1 + + + TXC + Transmit Complete Interrupt Disable + 1 + 1 + + + RXC + Receive Complete Interrupt Disable + 2 + 1 + + + RXS + Receive Start Interrupt Disable + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt Disable + 4 + 1 + + + RXBRK + Break Received Interrupt Disable + 5 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + USART_INT Interrupt Enable Set + 0x16 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Enable + 0 + 1 + + + TXC + Transmit Complete Interrupt Enable + 1 + 1 + + + RXC + Receive Complete Interrupt Enable + 2 + 1 + + + RXS + Receive Start Interrupt Enable + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt Enable + 4 + 1 + + + RXBRK + Break Received Interrupt Enable + 5 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + USART_INT Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt + 0 + 1 + + + TXC + Transmit Complete Interrupt + 1 + 1 + + + RXC + Receive Complete Interrupt + 2 + 1 + + + RXS + Receive Start Interrupt + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt + 4 + 1 + + + RXBRK + Break Received Interrupt + 5 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + USART_INT Status + 0x1A + 16 + 0x0000 + + + PERR + Parity Error + 0 + 1 + + + FERR + Frame Error + 1 + 1 + + + BUFOVF + Buffer Overflow + 2 + 1 + + + CTS + Clear To Send + 3 + 1 + + + ISF + Inconsistent Sync Field + 4 + 1 + + + COLL + Collision Detected + 5 + 1 + + + TXE + Transmitter Empty + 6 + 1 + + + + + SYNCBUSY + USART_INT Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + CTRLB + CTRLB Synchronization Busy + 2 + 1 + + + + + DATA + USART_INT Data + 0x28 + 16 + 0x0000 + + + DATA + Data Value + 0 + 9 + + + + + DBGCTRL + USART_INT Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + + + SERCOM1 + 0x42000800 + + SERCOM1 + 10 + + + + SERCOM2 + 0x42000C00 + + SERCOM2 + 11 + + + + SERCOM3 + 0x42001000 + + SERCOM3 + 12 + + + + SUPC + U21172.1.1 + Supply Controller + SUPC + SUPC_ + 0x40001800 + + 0 + 0x20 + registers + + + + INTENCLR + Interrupt Enable Clear + 0x0 + 32 + 0x00000000 + + + BODVDDRDY + BODVDD Ready + 0 + 1 + + + BODVDDDET + BODVDD Detection + 1 + 1 + + + BVDDSRDY + BODVDD Synchronization Ready + 2 + 1 + + + BODCORERDY + BODCORE Ready + 3 + 1 + + + BODCOREDET + BODCORE Detection + 4 + 1 + + + BCORESRDY + BODCORE Synchronization Ready + 5 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x4 + 32 + 0x00000000 + + + BODVDDRDY + BODVDD Ready + 0 + 1 + + + BODVDDDET + BODVDD Detection + 1 + 1 + + + BVDDSRDY + BODVDD Synchronization Ready + 2 + 1 + + + BODCORERDY + BODCORE Ready + 3 + 1 + + + BODCOREDET + BODCORE Detection + 4 + 1 + + + BCORESRDY + BODCORE Synchronization Ready + 5 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x8 + 32 + 0x00000000 + + + BODVDDRDY + BODVDD Ready + 0 + 1 + + + BODVDDDET + BODVDD Detection + 1 + 1 + + + BVDDSRDY + BODVDD Synchronization Ready + 2 + 1 + + + BODCORERDY + BODCORE Ready + 3 + 1 + + + BODCOREDET + BODCORE Detection + 4 + 1 + + + BCORESRDY + BODCORE Synchronization Ready + 5 + 1 + + + + + STATUS + Power and Clocks Status + 0xC + 32 + read-only + 0x00000000 + + + BODVDDRDY + BODVDD Ready + 0 + 1 + + + BODVDDDET + BODVDD Detection + 1 + 1 + + + BVDDSRDY + BODVDD Synchronization Ready + 2 + 1 + + + BODCORERDY + BODCORE Ready + 3 + 1 + + + BODCOREDET + BODCORE Detection + 4 + 1 + + + BCORESRDY + BODCORE Synchronization Ready + 5 + 1 + + + + + BODVDD + BODVDD Control + 0x10 + 32 + 0x00000000 + + + ENABLE + Enable + 1 + 1 + + + HYST + Hysteresis Enable + 2 + 1 + + + ACTION + Action when Threshold Crossed + 3 + 2 + + ACTIONSelect + + NONE + No action + 0x0 + + + RESET + The BODVDD generates a reset + 0x1 + + + INT + The BODVDD generates an interrupt + 0x2 + + + + + STDBYCFG + Configuration in Standby mode + 5 + 1 + + + RUNSTDBY + Run during Standby + 6 + 1 + + + ACTCFG + Configuration in Active mode + 8 + 1 + + + PSEL + Prescaler Select + 12 + 4 + + PSELSelect + + DIV2 + Divide clock by 2 + 0x0 + + + DIV4 + Divide clock by 4 + 0x1 + + + DIV8 + Divide clock by 8 + 0x2 + + + DIV16 + Divide clock by 16 + 0x3 + + + DIV32 + Divide clock by 32 + 0x4 + + + DIV64 + Divide clock by 64 + 0x5 + + + DIV128 + Divide clock by 128 + 0x6 + + + DIV256 + Divide clock by 256 + 0x7 + + + DIV512 + Divide clock by 512 + 0x8 + + + DIV1024 + Divide clock by 1024 + 0x9 + + + DIV2048 + Divide clock by 2048 + 0xA + + + DIV4096 + Divide clock by 4096 + 0xB + + + DIV8192 + Divide clock by 8192 + 0xC + + + DIV16384 + Divide clock by 16384 + 0xD + + + DIV32768 + Divide clock by 32768 + 0xE + + + DIV65536 + Divide clock by 65536 + 0xF + + + + + LEVEL + Threshold Level for VDD + 16 + 6 + + + + + BODCORE + BODCORE Control + 0x14 + 32 + 0x00000000 + + + ENABLE + Enable + 1 + 1 + + + HYST + Hysteresis Enable + 2 + 1 + + + ACTION + Action when Threshold Crossed + 3 + 2 + + ACTIONSelect + + NONE + No action + 0x0 + + + RESET + The BODCORE generates a reset + 0x1 + + + INT + The BODCORE generates an interrupt + 0x2 + + + + + STDBYCFG + Configuration in Standby mode + 5 + 1 + + + RUNSTDBY + Run during Standby + 6 + 1 + + + ACTCFG + Configuration in Active mode + 8 + 1 + + + PSEL + Prescaler Select + 12 + 4 + + PSELSelect + + DIV2 + Divide clock by 2 + 0x0 + + + DIV4 + Divide clock by 4 + 0x1 + + + DIV8 + Divide clock by 8 + 0x2 + + + DIV16 + Divide clock by 16 + 0x3 + + + DIV32 + Divide clock by 32 + 0x4 + + + DIV64 + Divide clock by 64 + 0x5 + + + DIV128 + Divide clock by 128 + 0x6 + + + DIV256 + Divide clock by 256 + 0x7 + + + DIV512 + Divide clock by 512 + 0x8 + + + DIV1024 + Divide clock by 1024 + 0x9 + + + DIV2048 + Divide clock by 2048 + 0xA + + + DIV4096 + Divide clock by 4096 + 0xB + + + DIV8192 + Divide clock by 8192 + 0xC + + + DIV16384 + Divide clock by 16384 + 0xD + + + DIV32768 + Divide clock by 32768 + 0xE + + + DIV65536 + Divide clock by 65536 + 0xF + + + + + LEVEL + Threshold Level + 16 + 6 + + + + + VREG + VREG Control + 0x18 + 32 + 0x00000000 + + + ENABLE + Enable + 1 + 1 + + + RUNSTDBY + Run during Standby + 6 + 1 + + + + + VREF + VREF Control + 0x1C + 32 + 0x00000000 + + + TSEN + Temperature Sensor Output Enable + 1 + 1 + + + VREFOE + Voltage Reference Output Enable + 2 + 1 + + + RUNSTDBY + Run during Standby + 6 + 1 + + + ONDEMAND + On Demand Contrl + 7 + 1 + + + SEL + Voltage Reference Selection + 16 + 4 + + SELSelect + + 1V024 + 1.024V voltage reference typical value + 0x0 + + + 2V048 + 2.048V voltage reference typical value + 0x2 + + + 4V096 + 4.096V voltage reference typical value + 0x3 + + + + + + + + + TC0 + U22492.0.0 + Basic Timer Counter + TC + TC_ + 0x42003000 + + 0 + 0x38 + registers + + + TC0 + 20 + + + + COUNT8 + 8-bit Counter Mode + TcCount8 + 0x0 + + CTRLA + Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Timer Counter Mode + 2 + 2 + + MODESelect + + COUNT16 + Counter in 16-bit mode + 0 + + + COUNT8 + Counter in 8-bit mode + 1 + + + COUNT32 + Counter in 32-bit mode + 2 + + + + + PRESCSYNC + Prescaler and Counter Synchronization + 4 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset the counter on next generic clock + 0 + + + PRESC + Reload or reset the counter on next prescaler clock + 1 + + + RESYNC + Reload or reset the counter on next generic clock and reset the prescaler counter + 2 + + + + + RUNSTDBY + Run during Standby + 6 + 1 + + + ONDEMAND + Clock On Demand + 7 + 1 + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + Prescaler: GCLK_TC + 0 + + + DIV2 + Prescaler: GCLK_TC/2 + 1 + + + DIV4 + Prescaler: GCLK_TC/4 + 2 + + + DIV8 + Prescaler: GCLK_TC/8 + 3 + + + DIV16 + Prescaler: GCLK_TC/16 + 4 + + + DIV64 + Prescaler: GCLK_TC/64 + 5 + + + DIV256 + Prescaler: GCLK_TC/256 + 6 + + + DIV1024 + Prescaler: GCLK_TC/1024 + 7 + + + + + ALOCK + Auto Lock + 11 + 1 + + + CAPTEN0 + Capture Channel 0 Enable + 16 + 1 + + + CAPTEN1 + Capture Channel 1 Enable + 17 + 1 + + + COPEN0 + Capture On Pin 0 Enable + 20 + 1 + + + COPEN1 + Capture On Pin 1 Enable + 21 + 1 + + + + + CTRLBCLR + Control B Clear + 0x4 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot on Counter + 2 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + UPDATE + Force update of double-buffered register + 3 + + + READSYNC + Force a read synchronization of COUNT + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + CTRLBSET + Control B Set + 0x5 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot on Counter + 2 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + UPDATE + Force update of double-buffered register + 3 + + + READSYNC + Force a read synchronization of COUNT + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + EVCTRL + Event Control + 0x6 + 16 + 0x0000 + + + EVACT + Event Action + 0 + 3 + + EVACTSelect + + OFF + Event action disabled + 0 + + + RETRIGGER + Start, restart or retrigger TC on event + 1 + + + COUNT + Count on event + 2 + + + START + Start TC on event + 3 + + + STAMP + Time stamp capture + 4 + + + PPW + Period catured in CC0, pulse width in CC1 + 5 + + + PWP + Period catured in CC1, pulse width in CC0 + 6 + + + PW + Pulse width capture + 7 + + + + + TCINV + TC Event Input Polarity + 4 + 1 + + + TCEI + TC Event Enable + 5 + 1 + + + OVFEO + Event Output Enable + 8 + 1 + + + MCEO0 + MC Event Output Enable 0 + 12 + 1 + + + MCEO1 + MC Event Output Enable 1 + 13 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x8 + 8 + 0x00 + + + OVF + OVF Interrupt Disable + 0 + 1 + + + ERR + ERR Interrupt Disable + 1 + 1 + + + MC0 + MC Interrupt Disable 0 + 4 + 1 + + + MC1 + MC Interrupt Disable 1 + 5 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x9 + 8 + 0x00 + + + OVF + OVF Interrupt Enable + 0 + 1 + + + ERR + ERR Interrupt Enable + 1 + 1 + + + MC0 + MC Interrupt Enable 0 + 4 + 1 + + + MC1 + MC Interrupt Enable 1 + 5 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0xA + 8 + 0x00 + + + OVF + OVF Interrupt Flag + 0 + 1 + + + ERR + ERR Interrupt Flag + 1 + 1 + + + MC0 + MC Interrupt Flag 0 + 4 + 1 + + + MC1 + MC Interrupt Flag 1 + 5 + 1 + + + + + STATUS + Status + 0xB + 8 + 0x01 + + + STOP + Stop Status Flag + 0 + 1 + + + SLAVE + Slave Status Flag + 1 + 1 + + + PERBUFV + Synchronization Busy Status + 3 + 1 + + + CCBUFV0 + Compare channel buffer 0 valid + 4 + 1 + + + CCBUFV1 + Compare channel buffer 1 valid + 5 + 1 + + + + + WAVE + Waveform Generation Control + 0xC + 8 + 0x00 + + + WAVEGEN + Waveform Generation Mode + 0 + 2 + + WAVEGENSelect + + NFRQ + Normal frequency + 0 + + + MFRQ + Match frequency + 1 + + + NPWM + Normal PWM + 2 + + + MPWM + Match PWM + 3 + + + + + + + DRVCTRL + Control C + 0xD + 8 + 0x00 + + + INVEN0 + Output Waveform Invert Enable 0 + 0 + 1 + + + INVEN1 + Output Waveform Invert Enable 1 + 1 + 1 + + + + + DBGCTRL + Debug Control + 0xF + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + SYNCBUSY + Synchronization Status + 0x10 + 32 + read-only + 0x00000000 + + + SWRST + swrst + 0 + 1 + + + ENABLE + enable + 1 + 1 + + + CTRLB + CTRLB + 2 + 1 + + + STATUS + STATUS + 3 + 1 + + + COUNT + Counter + 4 + 1 + + + PER + Period + 5 + 1 + + + CC0 + Compare Channel 0 + 6 + 1 + + + CC1 + Compare Channel 1 + 7 + 1 + + + + + COUNT + COUNT8 Count + 0x14 + 8 + 0x00 + + + COUNT + Counter Value + 0 + 8 + + + + + PER + COUNT8 Period + 0x1B + 8 + 0xFF + + + PER + Period Value + 0 + 8 + + + + + 2 + 1 + CC[%s] + COUNT8 Compare and Capture + 0x1C + 8 + 0x00 + + + CC + Counter/Compare Value + 0 + 8 + + + + + PERBUF + COUNT8 Period Buffer + 0x2F + 8 + 0xFF + + + PERBUF + Period Buffer Value + 0 + 8 + + + + + 2 + 1 + CCBUF[%s] + COUNT8 Compare and Capture Buffer + 0x30 + 8 + 0x00 + + + CCBUF + Counter/Compare Buffer Value + 0 + 8 + + + + + + COUNT16 + 16-bit Counter Mode + COUNT8 + TcCount16 + 0x0 + + CTRLA + Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Timer Counter Mode + 2 + 2 + + MODESelect + + COUNT16 + Counter in 16-bit mode + 0 + + + COUNT8 + Counter in 8-bit mode + 1 + + + COUNT32 + Counter in 32-bit mode + 2 + + + + + PRESCSYNC + Prescaler and Counter Synchronization + 4 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset the counter on next generic clock + 0 + + + PRESC + Reload or reset the counter on next prescaler clock + 1 + + + RESYNC + Reload or reset the counter on next generic clock and reset the prescaler counter + 2 + + + + + RUNSTDBY + Run during Standby + 6 + 1 + + + ONDEMAND + Clock On Demand + 7 + 1 + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + Prescaler: GCLK_TC + 0 + + + DIV2 + Prescaler: GCLK_TC/2 + 1 + + + DIV4 + Prescaler: GCLK_TC/4 + 2 + + + DIV8 + Prescaler: GCLK_TC/8 + 3 + + + DIV16 + Prescaler: GCLK_TC/16 + 4 + + + DIV64 + Prescaler: GCLK_TC/64 + 5 + + + DIV256 + Prescaler: GCLK_TC/256 + 6 + + + DIV1024 + Prescaler: GCLK_TC/1024 + 7 + + + + + ALOCK + Auto Lock + 11 + 1 + + + CAPTEN0 + Capture Channel 0 Enable + 16 + 1 + + + CAPTEN1 + Capture Channel 1 Enable + 17 + 1 + + + COPEN0 + Capture On Pin 0 Enable + 20 + 1 + + + COPEN1 + Capture On Pin 1 Enable + 21 + 1 + + + + + CTRLBCLR + Control B Clear + 0x4 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot on Counter + 2 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + UPDATE + Force update of double-buffered register + 3 + + + READSYNC + Force a read synchronization of COUNT + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + CTRLBSET + Control B Set + 0x5 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot on Counter + 2 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + UPDATE + Force update of double-buffered register + 3 + + + READSYNC + Force a read synchronization of COUNT + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + EVCTRL + Event Control + 0x6 + 16 + 0x0000 + + + EVACT + Event Action + 0 + 3 + + EVACTSelect + + OFF + Event action disabled + 0 + + + RETRIGGER + Start, restart or retrigger TC on event + 1 + + + COUNT + Count on event + 2 + + + START + Start TC on event + 3 + + + STAMP + Time stamp capture + 4 + + + PPW + Period catured in CC0, pulse width in CC1 + 5 + + + PWP + Period catured in CC1, pulse width in CC0 + 6 + + + PW + Pulse width capture + 7 + + + + + TCINV + TC Event Input Polarity + 4 + 1 + + + TCEI + TC Event Enable + 5 + 1 + + + OVFEO + Event Output Enable + 8 + 1 + + + MCEO0 + MC Event Output Enable 0 + 12 + 1 + + + MCEO1 + MC Event Output Enable 1 + 13 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x8 + 8 + 0x00 + + + OVF + OVF Interrupt Disable + 0 + 1 + + + ERR + ERR Interrupt Disable + 1 + 1 + + + MC0 + MC Interrupt Disable 0 + 4 + 1 + + + MC1 + MC Interrupt Disable 1 + 5 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x9 + 8 + 0x00 + + + OVF + OVF Interrupt Enable + 0 + 1 + + + ERR + ERR Interrupt Enable + 1 + 1 + + + MC0 + MC Interrupt Enable 0 + 4 + 1 + + + MC1 + MC Interrupt Enable 1 + 5 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0xA + 8 + 0x00 + + + OVF + OVF Interrupt Flag + 0 + 1 + + + ERR + ERR Interrupt Flag + 1 + 1 + + + MC0 + MC Interrupt Flag 0 + 4 + 1 + + + MC1 + MC Interrupt Flag 1 + 5 + 1 + + + + + STATUS + Status + 0xB + 8 + 0x01 + + + STOP + Stop Status Flag + 0 + 1 + + + SLAVE + Slave Status Flag + 1 + 1 + + + PERBUFV + Synchronization Busy Status + 3 + 1 + + + CCBUFV0 + Compare channel buffer 0 valid + 4 + 1 + + + CCBUFV1 + Compare channel buffer 1 valid + 5 + 1 + + + + + WAVE + Waveform Generation Control + 0xC + 8 + 0x00 + + + WAVEGEN + Waveform Generation Mode + 0 + 2 + + WAVEGENSelect + + NFRQ + Normal frequency + 0 + + + MFRQ + Match frequency + 1 + + + NPWM + Normal PWM + 2 + + + MPWM + Match PWM + 3 + + + + + + + DRVCTRL + Control C + 0xD + 8 + 0x00 + + + INVEN0 + Output Waveform Invert Enable 0 + 0 + 1 + + + INVEN1 + Output Waveform Invert Enable 1 + 1 + 1 + + + + + DBGCTRL + Debug Control + 0xF + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + SYNCBUSY + Synchronization Status + 0x10 + 32 + read-only + 0x00000000 + + + SWRST + swrst + 0 + 1 + + + ENABLE + enable + 1 + 1 + + + CTRLB + CTRLB + 2 + 1 + + + STATUS + STATUS + 3 + 1 + + + COUNT + Counter + 4 + 1 + + + PER + Period + 5 + 1 + + + CC0 + Compare Channel 0 + 6 + 1 + + + CC1 + Compare Channel 1 + 7 + 1 + + + + + COUNT + COUNT16 Count + 0x14 + 16 + 0x0000 + + + COUNT + Counter Value + 0 + 16 + + + + + 2 + 2 + CC[%s] + COUNT16 Compare and Capture + 0x1C + 16 + 0x0000 + + + CC + Counter/Compare Value + 0 + 16 + + + + + 2 + 2 + CCBUF[%s] + COUNT16 Compare and Capture Buffer + 0x30 + 16 + 0x0000 + + + CCBUF + Counter/Compare Buffer Value + 0 + 16 + + + + + + COUNT32 + 32-bit Counter Mode + COUNT8 + TcCount32 + 0x0 + + CTRLA + Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Timer Counter Mode + 2 + 2 + + MODESelect + + COUNT16 + Counter in 16-bit mode + 0 + + + COUNT8 + Counter in 8-bit mode + 1 + + + COUNT32 + Counter in 32-bit mode + 2 + + + + + PRESCSYNC + Prescaler and Counter Synchronization + 4 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset the counter on next generic clock + 0 + + + PRESC + Reload or reset the counter on next prescaler clock + 1 + + + RESYNC + Reload or reset the counter on next generic clock and reset the prescaler counter + 2 + + + + + RUNSTDBY + Run during Standby + 6 + 1 + + + ONDEMAND + Clock On Demand + 7 + 1 + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + Prescaler: GCLK_TC + 0 + + + DIV2 + Prescaler: GCLK_TC/2 + 1 + + + DIV4 + Prescaler: GCLK_TC/4 + 2 + + + DIV8 + Prescaler: GCLK_TC/8 + 3 + + + DIV16 + Prescaler: GCLK_TC/16 + 4 + + + DIV64 + Prescaler: GCLK_TC/64 + 5 + + + DIV256 + Prescaler: GCLK_TC/256 + 6 + + + DIV1024 + Prescaler: GCLK_TC/1024 + 7 + + + + + ALOCK + Auto Lock + 11 + 1 + + + CAPTEN0 + Capture Channel 0 Enable + 16 + 1 + + + CAPTEN1 + Capture Channel 1 Enable + 17 + 1 + + + COPEN0 + Capture On Pin 0 Enable + 20 + 1 + + + COPEN1 + Capture On Pin 1 Enable + 21 + 1 + + + + + CTRLBCLR + Control B Clear + 0x4 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot on Counter + 2 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + UPDATE + Force update of double-buffered register + 3 + + + READSYNC + Force a read synchronization of COUNT + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + CTRLBSET + Control B Set + 0x5 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot on Counter + 2 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + UPDATE + Force update of double-buffered register + 3 + + + READSYNC + Force a read synchronization of COUNT + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + EVCTRL + Event Control + 0x6 + 16 + 0x0000 + + + EVACT + Event Action + 0 + 3 + + EVACTSelect + + OFF + Event action disabled + 0 + + + RETRIGGER + Start, restart or retrigger TC on event + 1 + + + COUNT + Count on event + 2 + + + START + Start TC on event + 3 + + + STAMP + Time stamp capture + 4 + + + PPW + Period catured in CC0, pulse width in CC1 + 5 + + + PWP + Period catured in CC1, pulse width in CC0 + 6 + + + PW + Pulse width capture + 7 + + + + + TCINV + TC Event Input Polarity + 4 + 1 + + + TCEI + TC Event Enable + 5 + 1 + + + OVFEO + Event Output Enable + 8 + 1 + + + MCEO0 + MC Event Output Enable 0 + 12 + 1 + + + MCEO1 + MC Event Output Enable 1 + 13 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x8 + 8 + 0x00 + + + OVF + OVF Interrupt Disable + 0 + 1 + + + ERR + ERR Interrupt Disable + 1 + 1 + + + MC0 + MC Interrupt Disable 0 + 4 + 1 + + + MC1 + MC Interrupt Disable 1 + 5 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x9 + 8 + 0x00 + + + OVF + OVF Interrupt Enable + 0 + 1 + + + ERR + ERR Interrupt Enable + 1 + 1 + + + MC0 + MC Interrupt Enable 0 + 4 + 1 + + + MC1 + MC Interrupt Enable 1 + 5 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0xA + 8 + 0x00 + + + OVF + OVF Interrupt Flag + 0 + 1 + + + ERR + ERR Interrupt Flag + 1 + 1 + + + MC0 + MC Interrupt Flag 0 + 4 + 1 + + + MC1 + MC Interrupt Flag 1 + 5 + 1 + + + + + STATUS + Status + 0xB + 8 + 0x01 + + + STOP + Stop Status Flag + 0 + 1 + + + SLAVE + Slave Status Flag + 1 + 1 + + + PERBUFV + Synchronization Busy Status + 3 + 1 + + + CCBUFV0 + Compare channel buffer 0 valid + 4 + 1 + + + CCBUFV1 + Compare channel buffer 1 valid + 5 + 1 + + + + + WAVE + Waveform Generation Control + 0xC + 8 + 0x00 + + + WAVEGEN + Waveform Generation Mode + 0 + 2 + + WAVEGENSelect + + NFRQ + Normal frequency + 0 + + + MFRQ + Match frequency + 1 + + + NPWM + Normal PWM + 2 + + + MPWM + Match PWM + 3 + + + + + + + DRVCTRL + Control C + 0xD + 8 + 0x00 + + + INVEN0 + Output Waveform Invert Enable 0 + 0 + 1 + + + INVEN1 + Output Waveform Invert Enable 1 + 1 + 1 + + + + + DBGCTRL + Debug Control + 0xF + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + SYNCBUSY + Synchronization Status + 0x10 + 32 + read-only + 0x00000000 + + + SWRST + swrst + 0 + 1 + + + ENABLE + enable + 1 + 1 + + + CTRLB + CTRLB + 2 + 1 + + + STATUS + STATUS + 3 + 1 + + + COUNT + Counter + 4 + 1 + + + PER + Period + 5 + 1 + + + CC0 + Compare Channel 0 + 6 + 1 + + + CC1 + Compare Channel 1 + 7 + 1 + + + + + COUNT + COUNT32 Count + 0x14 + 32 + 0x00000000 + + + COUNT + Counter Value + 0 + 32 + + + + + 2 + 4 + CC[%s] + COUNT32 Compare and Capture + 0x1C + 32 + 0x00000000 + + + CC + Counter/Compare Value + 0 + 32 + + + + + 2 + 4 + CCBUF[%s] + COUNT32 Compare and Capture Buffer + 0x30 + 32 + 0x00000000 + + + CCBUF + Counter/Compare Buffer Value + 0 + 32 + + + + + + + + TC1 + 0x42003400 + + TC1 + 21 + + + + TC2 + 0x42003800 + + TC2 + 22 + + + + TC3 + 0x42003C00 + + TC3 + 23 + + + + TC4 + 0x42004000 + + TC4 + 24 + + + + TCC0 + U22133.0.0 + Timer Counter Control + TCC + TCC_ + 0x42002400 + + 0 + 0x80 + registers + + + TCC0 + 17 + + + + CTRLA + Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + RESOLUTION + Enhanced Resolution + 5 + 2 + + RESOLUTIONSelect + + NONE + Dithering is disabled + 0 + + + DITH4 + Dithering is done every 16 PWM frames + 1 + + + DITH5 + Dithering is done every 32 PWM frames + 2 + + + DITH6 + Dithering is done every 64 PWM frames + 3 + + + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + No division + 0 + + + DIV2 + Divide by 2 + 1 + + + DIV4 + Divide by 4 + 2 + + + DIV8 + Divide by 8 + 3 + + + DIV16 + Divide by 16 + 4 + + + DIV64 + Divide by 64 + 5 + + + DIV256 + Divide by 256 + 6 + + + DIV1024 + Divide by 1024 + 7 + + + + + RUNSTDBY + Run in Standby + 11 + 1 + + + PRESCSYNC + Prescaler and Counter Synchronization Selection + 12 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset counter on next GCLK + 0 + + + PRESC + Reload or reset counter on next prescaler clock + 1 + + + RESYNC + Reload or reset counter on next GCLK and reset prescaler counter + 2 + + + + + ALOCK + Auto Lock + 14 + 1 + + + MSYNC + Master Synchronization (only for TCC Slave Instance) + 15 + 1 + + + DMAOS + DMA One-shot Trigger Mode + 23 + 1 + + + CPTEN0 + Capture Channel 0 Enable + 24 + 1 + + + CPTEN1 + Capture Channel 1 Enable + 25 + 1 + + + CPTEN2 + Capture Channel 2 Enable + 26 + 1 + + + CPTEN3 + Capture Channel 3 Enable + 27 + 1 + + + + + CTRLBCLR + Control B Clear + 0x4 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + IDXCMD + Ramp Index Command + 3 + 2 + + IDXCMDSelect + + DISABLE + Command disabled: Index toggles between cycles A and B + 0 + + + SET + Set index: cycle B will be forced in the next cycle + 1 + + + CLEAR + Clear index: cycle A will be forced in the next cycle + 2 + + + HOLD + Hold index: the next cycle will be the same as the current cycle + 3 + + + + + CMD + TCC Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Clear start, restart or retrigger + 1 + + + STOP + Force stop + 2 + + + UPDATE + Force update or double buffered registers + 3 + + + READSYNC + Force COUNT read synchronization + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + CTRLBSET + Control B Set + 0x5 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + IDXCMD + Ramp Index Command + 3 + 2 + + IDXCMDSelect + + DISABLE + Command disabled: Index toggles between cycles A and B + 0 + + + SET + Set index: cycle B will be forced in the next cycle + 1 + + + CLEAR + Clear index: cycle A will be forced in the next cycle + 2 + + + HOLD + Hold index: the next cycle will be the same as the current cycle + 3 + + + + + CMD + TCC Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Clear start, restart or retrigger + 1 + + + STOP + Force stop + 2 + + + UPDATE + Force update or double buffered registers + 3 + + + READSYNC + Force COUNT read synchronization + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + SYNCBUSY + Synchronization Busy + 0x8 + 32 + read-only + 0x00000000 + + + SWRST + Swrst Busy + 0 + 1 + + + ENABLE + Enable Busy + 1 + 1 + + + CTRLB + Ctrlb Busy + 2 + 1 + + + STATUS + Status Busy + 3 + 1 + + + COUNT + Count Busy + 4 + 1 + + + PATT + Pattern Busy + 5 + 1 + + + WAVE + Wave Busy + 6 + 1 + + + PER + Period Busy + 7 + 1 + + + CC0 + Compare Channel 0 Busy + 8 + 1 + + + CC1 + Compare Channel 1 Busy + 9 + 1 + + + CC2 + Compare Channel 2 Busy + 10 + 1 + + + CC3 + Compare Channel 3 Busy + 11 + 1 + + + + + FCTRLA + Recoverable Fault A Configuration + 0xC + 32 + 0x00000000 + + + SRC + Fault A Source + 0 + 2 + + SRCSelect + + DISABLE + Fault input disabled + 0 + + + ENABLE + MCEx (x=0,1) event input + 1 + + + INVERT + Inverted MCEx (x=0,1) event input + 2 + + + ALTFAULT + Alternate fault (A or B) state at the end of the previous period + 3 + + + + + KEEP + Fault A Keeper + 3 + 1 + + + QUAL + Fault A Qualification + 4 + 1 + + + BLANK + Fault A Blanking Mode + 5 + 2 + + BLANKSelect + + START + Blanking applied from start of the ramp + 0 + + + RISE + Blanking applied from rising edge of the output waveform + 1 + + + FALL + Blanking applied from falling edge of the output waveform + 2 + + + BOTH + Blanking applied from each toggle of the output waveform + 3 + + + + + RESTART + Fault A Restart + 7 + 1 + + + HALT + Fault A Halt Mode + 8 + 2 + + HALTSelect + + DISABLE + Halt action disabled + 0 + + + HW + Hardware halt action + 1 + + + SW + Software halt action + 2 + + + NR + Non-recoverable fault + 3 + + + + + CHSEL + Fault A Capture Channel + 10 + 2 + + CHSELSelect + + CC0 + Capture value stored in channel 0 + 0 + + + CC1 + Capture value stored in channel 1 + 1 + + + CC2 + Capture value stored in channel 2 + 2 + + + CC3 + Capture value stored in channel 3 + 3 + + + + + CAPTURE + Fault A Capture Action + 12 + 3 + + CAPTURESelect + + DISABLE + No capture + 0 + + + CAPT + Capture on fault + 1 + + + CAPTMIN + Minimum capture + 2 + + + CAPTMAX + Maximum capture + 3 + + + LOCMIN + Minimum local detection + 4 + + + LOCMAX + Maximum local detection + 5 + + + DERIV0 + Minimum and maximum local detection + 6 + + + CAPTMARK + Capture with ramp index as MSB value + 7 + + + + + BLANKPRESC + Fault A Blanking Prescaler + 15 + 1 + + + BLANKVAL + Fault A Blanking Time + 16 + 8 + + + FILTERVAL + Fault A Filter Value + 24 + 4 + + + + + FCTRLB + Recoverable Fault B Configuration + 0x10 + 32 + 0x00000000 + + + SRC + Fault B Source + 0 + 2 + + SRCSelect + + DISABLE + Fault input disabled + 0 + + + ENABLE + MCEx (x=0,1) event input + 1 + + + INVERT + Inverted MCEx (x=0,1) event input + 2 + + + ALTFAULT + Alternate fault (A or B) state at the end of the previous period + 3 + + + + + KEEP + Fault B Keeper + 3 + 1 + + + QUAL + Fault B Qualification + 4 + 1 + + + BLANK + Fault B Blanking Mode + 5 + 2 + + BLANKSelect + + START + Blanking applied from start of the ramp + 0 + + + RISE + Blanking applied from rising edge of the output waveform + 1 + + + FALL + Blanking applied from falling edge of the output waveform + 2 + + + BOTH + Blanking applied from each toggle of the output waveform + 3 + + + + + RESTART + Fault B Restart + 7 + 1 + + + HALT + Fault B Halt Mode + 8 + 2 + + HALTSelect + + DISABLE + Halt action disabled + 0 + + + HW + Hardware halt action + 1 + + + SW + Software halt action + 2 + + + NR + Non-recoverable fault + 3 + + + + + CHSEL + Fault B Capture Channel + 10 + 2 + + CHSELSelect + + CC0 + Capture value stored in channel 0 + 0 + + + CC1 + Capture value stored in channel 1 + 1 + + + CC2 + Capture value stored in channel 2 + 2 + + + CC3 + Capture value stored in channel 3 + 3 + + + + + CAPTURE + Fault B Capture Action + 12 + 3 + + CAPTURESelect + + DISABLE + No capture + 0 + + + CAPT + Capture on fault + 1 + + + CAPTMIN + Minimum capture + 2 + + + CAPTMAX + Maximum capture + 3 + + + LOCMIN + Minimum local detection + 4 + + + LOCMAX + Maximum local detection + 5 + + + DERIV0 + Minimum and maximum local detection + 6 + + + CAPTMARK + Capture with ramp index as MSB value + 7 + + + + + BLANKPRESC + Fault B Blanking Prescaler + 15 + 1 + + + BLANKVAL + Fault B Blanking Time + 16 + 8 + + + FILTERVAL + Fault B Filter Value + 24 + 4 + + + + + WEXCTRL + Waveform Extension Configuration + 0x14 + 32 + 0x00000000 + + + OTMX + Output Matrix + 0 + 2 + + + DTIEN0 + Dead-time Insertion Generator 0 Enable + 8 + 1 + + + DTIEN1 + Dead-time Insertion Generator 1 Enable + 9 + 1 + + + DTIEN2 + Dead-time Insertion Generator 2 Enable + 10 + 1 + + + DTIEN3 + Dead-time Insertion Generator 3 Enable + 11 + 1 + + + DTLS + Dead-time Low Side Outputs Value + 16 + 8 + + + DTHS + Dead-time High Side Outputs Value + 24 + 8 + + + + + DRVCTRL + Driver Control + 0x18 + 32 + 0x00000000 + + + NRE0 + Non-Recoverable State 0 Output Enable + 0 + 1 + + + NRE1 + Non-Recoverable State 1 Output Enable + 1 + 1 + + + NRE2 + Non-Recoverable State 2 Output Enable + 2 + 1 + + + NRE3 + Non-Recoverable State 3 Output Enable + 3 + 1 + + + NRE4 + Non-Recoverable State 4 Output Enable + 4 + 1 + + + NRE5 + Non-Recoverable State 5 Output Enable + 5 + 1 + + + NRE6 + Non-Recoverable State 6 Output Enable + 6 + 1 + + + NRE7 + Non-Recoverable State 7 Output Enable + 7 + 1 + + + NRV0 + Non-Recoverable State 0 Output Value + 8 + 1 + + + NRV1 + Non-Recoverable State 1 Output Value + 9 + 1 + + + NRV2 + Non-Recoverable State 2 Output Value + 10 + 1 + + + NRV3 + Non-Recoverable State 3 Output Value + 11 + 1 + + + NRV4 + Non-Recoverable State 4 Output Value + 12 + 1 + + + NRV5 + Non-Recoverable State 5 Output Value + 13 + 1 + + + NRV6 + Non-Recoverable State 6 Output Value + 14 + 1 + + + NRV7 + Non-Recoverable State 7 Output Value + 15 + 1 + + + INVEN0 + Output Waveform 0 Inversion + 16 + 1 + + + INVEN1 + Output Waveform 1 Inversion + 17 + 1 + + + INVEN2 + Output Waveform 2 Inversion + 18 + 1 + + + INVEN3 + Output Waveform 3 Inversion + 19 + 1 + + + INVEN4 + Output Waveform 4 Inversion + 20 + 1 + + + INVEN5 + Output Waveform 5 Inversion + 21 + 1 + + + INVEN6 + Output Waveform 6 Inversion + 22 + 1 + + + INVEN7 + Output Waveform 7 Inversion + 23 + 1 + + + FILTERVAL0 + Non-Recoverable Fault Input 0 Filter Value + 24 + 4 + + + FILTERVAL1 + Non-Recoverable Fault Input 1 Filter Value + 28 + 4 + + + + + DBGCTRL + Debug Control + 0x1E + 8 + 0x00 + + + DBGRUN + Debug Running Mode + 0 + 1 + + + FDDBD + Fault Detection on Debug Break Detection + 2 + 1 + + + + + EVCTRL + Event Control + 0x20 + 32 + 0x00000000 + + + EVACT0 + Timer/counter Input Event0 Action + 0 + 3 + + EVACT0Select + + OFF + Event action disabled + 0 + + + RETRIGGER + Start, restart or re-trigger counter on event + 1 + + + COUNTEV + Count on event + 2 + + + START + Start counter on event + 3 + + + INC + Increment counter on event + 4 + + + COUNT + Count on active state of asynchronous event + 5 + + + STAMP + Stamp capture + 6 + + + FAULT + Non-recoverable fault + 7 + + + + + EVACT1 + Timer/counter Input Event1 Action + 3 + 3 + + EVACT1Select + + OFF + Event action disabled + 0 + + + RETRIGGER + Re-trigger counter on event + 1 + + + DIR + Direction control + 2 + + + STOP + Stop counter on event + 3 + + + DEC + Decrement counter on event + 4 + + + PPW + Period capture value in CC0 register, pulse width capture value in CC1 register + 5 + + + PWP + Period capture value in CC1 register, pulse width capture value in CC0 register + 6 + + + FAULT + Non-recoverable fault + 7 + + + + + CNTSEL + Timer/counter Output Event Mode + 6 + 2 + + CNTSELSelect + + START + An interrupt/event is generated when a new counter cycle starts + 0 + + + END + An interrupt/event is generated when a counter cycle ends + 1 + + + BETWEEN + An interrupt/event is generated when a counter cycle ends, except for the first and last cycles + 2 + + + BOUNDARY + An interrupt/event is generated when a new counter cycle starts or a counter cycle ends + 3 + + + + + OVFEO + Overflow/Underflow Output Event Enable + 8 + 1 + + + TRGEO + Retrigger Output Event Enable + 9 + 1 + + + CNTEO + Timer/counter Output Event Enable + 10 + 1 + + + TCINV0 + Inverted Event 0 Input Enable + 12 + 1 + + + TCINV1 + Inverted Event 1 Input Enable + 13 + 1 + + + TCEI0 + Timer/counter Event 0 Input Enable + 14 + 1 + + + TCEI1 + Timer/counter Event 1 Input Enable + 15 + 1 + + + MCEI0 + Match or Capture Channel 0 Event Input Enable + 16 + 1 + + + MCEI1 + Match or Capture Channel 1 Event Input Enable + 17 + 1 + + + MCEI2 + Match or Capture Channel 2 Event Input Enable + 18 + 1 + + + MCEI3 + Match or Capture Channel 3 Event Input Enable + 19 + 1 + + + MCEO0 + Match or Capture Channel 0 Event Output Enable + 24 + 1 + + + MCEO1 + Match or Capture Channel 1 Event Output Enable + 25 + 1 + + + MCEO2 + Match or Capture Channel 2 Event Output Enable + 26 + 1 + + + MCEO3 + Match or Capture Channel 3 Event Output Enable + 27 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x24 + 32 + 0x00000000 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + TRG + Retrigger Interrupt Enable + 1 + 1 + + + CNT + Counter Interrupt Enable + 2 + 1 + + + ERR + Error Interrupt Enable + 3 + 1 + + + UFS + Non-Recoverable Update Fault Interrupt Enable + 10 + 1 + + + DFS + Non-Recoverable Debug Fault Interrupt Enable + 11 + 1 + + + FAULTA + Recoverable Fault A Interrupt Enable + 12 + 1 + + + FAULTB + Recoverable Fault B Interrupt Enable + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 Interrupt Enable + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 Interrupt Enable + 15 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 16 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 17 + 1 + + + MC2 + Match or Capture Channel 2 Interrupt Enable + 18 + 1 + + + MC3 + Match or Capture Channel 3 Interrupt Enable + 19 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x28 + 32 + 0x00000000 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + TRG + Retrigger Interrupt Enable + 1 + 1 + + + CNT + Counter Interrupt Enable + 2 + 1 + + + ERR + Error Interrupt Enable + 3 + 1 + + + UFS + Non-Recoverable Update Fault Interrupt Enable + 10 + 1 + + + DFS + Non-Recoverable Debug Fault Interrupt Enable + 11 + 1 + + + FAULTA + Recoverable Fault A Interrupt Enable + 12 + 1 + + + FAULTB + Recoverable Fault B Interrupt Enable + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 Interrupt Enable + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 Interrupt Enable + 15 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 16 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 17 + 1 + + + MC2 + Match or Capture Channel 2 Interrupt Enable + 18 + 1 + + + MC3 + Match or Capture Channel 3 Interrupt Enable + 19 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x2C + 32 + 0x00000000 + + + OVF + Overflow + 0 + 1 + + + TRG + Retrigger + 1 + 1 + + + CNT + Counter + 2 + 1 + + + ERR + Error + 3 + 1 + + + UFS + Non-Recoverable Update Fault + 10 + 1 + + + DFS + Non-Recoverable Debug Fault + 11 + 1 + + + FAULTA + Recoverable Fault A + 12 + 1 + + + FAULTB + Recoverable Fault B + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 + 15 + 1 + + + MC0 + Match or Capture 0 + 16 + 1 + + + MC1 + Match or Capture 1 + 17 + 1 + + + MC2 + Match or Capture 2 + 18 + 1 + + + MC3 + Match or Capture 3 + 19 + 1 + + + + + STATUS + Status + 0x30 + 32 + 0x00000001 + + + STOP + Stop + 0 + 1 + + + IDX + Ramp + 1 + 1 + + + UFS + Non-recoverable Update Fault State + 2 + 1 + + + DFS + Non-Recoverable Debug Fault State + 3 + 1 + + + SLAVE + Slave + 4 + 1 + + + PATTBUFV + Pattern Buffer Valid + 5 + 1 + + + PERBUFV + Period Buffer Valid + 7 + 1 + + + FAULTAIN + Recoverable Fault A Input + 8 + 1 + + + FAULTBIN + Recoverable Fault B Input + 9 + 1 + + + FAULT0IN + Non-Recoverable Fault0 Input + 10 + 1 + + + FAULT1IN + Non-Recoverable Fault1 Input + 11 + 1 + + + FAULTA + Recoverable Fault A State + 12 + 1 + + + FAULTB + Recoverable Fault B State + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 State + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 State + 15 + 1 + + + CCBUFV0 + Compare Channel 0 Buffer Valid + 16 + 1 + + + CCBUFV1 + Compare Channel 1 Buffer Valid + 17 + 1 + + + CCBUFV2 + Compare Channel 2 Buffer Valid + 18 + 1 + + + CCBUFV3 + Compare Channel 3 Buffer Valid + 19 + 1 + + + CMP0 + Compare Channel 0 Value + 24 + 1 + + + CMP1 + Compare Channel 1 Value + 25 + 1 + + + CMP2 + Compare Channel 2 Value + 26 + 1 + + + CMP3 + Compare Channel 3 Value + 27 + 1 + + + + + COUNT + Count + 0x34 + 32 + 0x00000000 + + + COUNT + Counter Value + 0 + 24 + + + + + COUNT_DITH4_MODE + Count + COUNT + 0x34 + 32 + 0x00000000 + + + COUNT + Counter Value + 4 + 20 + + + + + COUNT_DITH5_MODE + Count + COUNT + 0x34 + 32 + 0x00000000 + + + COUNT + Counter Value + 5 + 19 + + + + + COUNT_DITH6_MODE + Count + COUNT + 0x34 + 32 + 0x00000000 + + + COUNT + Counter Value + 6 + 18 + + + + + PATT + Pattern + 0x38 + 16 + 0x0000 + + + PGE0 + Pattern Generator 0 Output Enable + 0 + 1 + + + PGE1 + Pattern Generator 1 Output Enable + 1 + 1 + + + PGE2 + Pattern Generator 2 Output Enable + 2 + 1 + + + PGE3 + Pattern Generator 3 Output Enable + 3 + 1 + + + PGE4 + Pattern Generator 4 Output Enable + 4 + 1 + + + PGE5 + Pattern Generator 5 Output Enable + 5 + 1 + + + PGE6 + Pattern Generator 6 Output Enable + 6 + 1 + + + PGE7 + Pattern Generator 7 Output Enable + 7 + 1 + + + PGV0 + Pattern Generator 0 Output Value + 8 + 1 + + + PGV1 + Pattern Generator 1 Output Value + 9 + 1 + + + PGV2 + Pattern Generator 2 Output Value + 10 + 1 + + + PGV3 + Pattern Generator 3 Output Value + 11 + 1 + + + PGV4 + Pattern Generator 4 Output Value + 12 + 1 + + + PGV5 + Pattern Generator 5 Output Value + 13 + 1 + + + PGV6 + Pattern Generator 6 Output Value + 14 + 1 + + + PGV7 + Pattern Generator 7 Output Value + 15 + 1 + + + + + WAVE + Waveform Control + 0x3C + 32 + 0x00000000 + + + WAVEGEN + Waveform Generation + 0 + 3 + + WAVEGENSelect + + NFRQ + Normal frequency + 0 + + + MFRQ + Match frequency + 1 + + + NPWM + Normal PWM + 2 + + + DSCRITICAL + Dual-slope critical + 4 + + + DSBOTTOM + Dual-slope with interrupt/event condition when COUNT reaches ZERO + 5 + + + DSBOTH + Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP + 6 + + + DSTOP + Dual-slope with interrupt/event condition when COUNT reaches TOP + 7 + + + + + RAMP + Ramp Mode + 4 + 2 + + RAMPSelect + + RAMP1 + RAMP1 operation + 0 + + + RAMP2A + Alternative RAMP2 operation + 1 + + + RAMP2 + RAMP2 operation + 2 + + + RAMP2C + Critical RAMP2 operation + 3 + + + + + CIPEREN + Circular period Enable + 7 + 1 + + + CICCEN0 + Circular Channel 0 Enable + 8 + 1 + + + CICCEN1 + Circular Channel 1 Enable + 9 + 1 + + + CICCEN2 + Circular Channel 2 Enable + 10 + 1 + + + CICCEN3 + Circular Channel 3 Enable + 11 + 1 + + + POL0 + Channel 0 Polarity + 16 + 1 + + + POL1 + Channel 1 Polarity + 17 + 1 + + + POL2 + Channel 2 Polarity + 18 + 1 + + + POL3 + Channel 3 Polarity + 19 + 1 + + + SWAP0 + Swap DTI Output Pair 0 + 24 + 1 + + + SWAP1 + Swap DTI Output Pair 1 + 25 + 1 + + + SWAP2 + Swap DTI Output Pair 2 + 26 + 1 + + + SWAP3 + Swap DTI Output Pair 3 + 27 + 1 + + + + + PER + Period + 0x40 + 32 + 0xFFFFFFFF + + + PER + Period Value + 0 + 24 + + + + + PER_DITH4_MODE + Period + PER + 0x40 + 32 + 0xFFFFFFFF + + + DITHER + Dithering Cycle Number + 0 + 4 + + + PER + Period Value + 4 + 20 + + + + + PER_DITH5_MODE + Period + PER + 0x40 + 32 + 0xFFFFFFFF + + + DITHER + Dithering Cycle Number + 0 + 5 + + + PER + Period Value + 5 + 19 + + + + + PER_DITH6_MODE + Period + PER + 0x40 + 32 + 0xFFFFFFFF + + + DITHER + Dithering Cycle Number + 0 + 6 + + + PER + Period Value + 6 + 18 + + + + + 4 + 4 + CC[%s] + Compare and Capture + 0x44 + 32 + 0x00000000 + + + CC + Channel Compare/Capture Value + 0 + 24 + + + + + 4 + 4 + CC_DITH4_MODE[%s] + Compare and Capture + CC[%s] + 0x44 + 32 + 0x00000000 + + + DITHER + Dithering Cycle Number + 0 + 4 + + + CC + Channel Compare/Capture Value + 4 + 20 + + + + + 4 + 4 + CC_DITH5_MODE[%s] + Compare and Capture + CC[%s] + 0x44 + 32 + 0x00000000 + + + DITHER + Dithering Cycle Number + 0 + 5 + + + CC + Channel Compare/Capture Value + 5 + 19 + + + + + 4 + 4 + CC_DITH6_MODE[%s] + Compare and Capture + CC[%s] + 0x44 + 32 + 0x00000000 + + + DITHER + Dithering Cycle Number + 0 + 6 + + + CC + Channel Compare/Capture Value + 6 + 18 + + + + + PATTBUF + Pattern Buffer + 0x64 + 16 + 0x0000 + + + PGEB0 + Pattern Generator 0 Output Enable Buffer + 0 + 1 + + + PGEB1 + Pattern Generator 1 Output Enable Buffer + 1 + 1 + + + PGEB2 + Pattern Generator 2 Output Enable Buffer + 2 + 1 + + + PGEB3 + Pattern Generator 3 Output Enable Buffer + 3 + 1 + + + PGEB4 + Pattern Generator 4 Output Enable Buffer + 4 + 1 + + + PGEB5 + Pattern Generator 5 Output Enable Buffer + 5 + 1 + + + PGEB6 + Pattern Generator 6 Output Enable Buffer + 6 + 1 + + + PGEB7 + Pattern Generator 7 Output Enable Buffer + 7 + 1 + + + PGVB0 + Pattern Generator 0 Output Enable + 8 + 1 + + + PGVB1 + Pattern Generator 1 Output Enable + 9 + 1 + + + PGVB2 + Pattern Generator 2 Output Enable + 10 + 1 + + + PGVB3 + Pattern Generator 3 Output Enable + 11 + 1 + + + PGVB4 + Pattern Generator 4 Output Enable + 12 + 1 + + + PGVB5 + Pattern Generator 5 Output Enable + 13 + 1 + + + PGVB6 + Pattern Generator 6 Output Enable + 14 + 1 + + + PGVB7 + Pattern Generator 7 Output Enable + 15 + 1 + + + + + PERBUF + Period Buffer + 0x6C + 32 + 0xFFFFFFFF + + + PERBUF + Period Buffer Value + 0 + 24 + + + + + PERBUF_DITH4_MODE + Period Buffer + PERBUF + 0x6C + 32 + 0xFFFFFFFF + + + DITHERBUF + Dithering Buffer Cycle Number + 0 + 4 + + + PERBUF + Period Buffer Value + 4 + 20 + + + + + PERBUF_DITH5_MODE + Period Buffer + PERBUF + 0x6C + 32 + 0xFFFFFFFF + + + DITHERBUF + Dithering Buffer Cycle Number + 0 + 5 + + + PERBUF + Period Buffer Value + 5 + 19 + + + + + PERBUF_DITH6_MODE + Period Buffer + PERBUF + 0x6C + 32 + 0xFFFFFFFF + + + DITHERBUF + Dithering Buffer Cycle Number + 0 + 6 + + + PERBUF + Period Buffer Value + 6 + 18 + + + + + 4 + 4 + CCBUF[%s] + Compare and Capture Buffer + 0x70 + 32 + 0x00000000 + + + CCBUF + Channel Compare/Capture Buffer Value + 0 + 24 + + + + + 4 + 4 + CCBUF_DITH4_MODE[%s] + Compare and Capture Buffer + CCBUF[%s] + 0x70 + 32 + 0x00000000 + + + CCBUF + Channel Compare/Capture Buffer Value + 0 + 4 + + + DITHERBUF + Dithering Buffer Cycle Number + 4 + 20 + + + + + 4 + 4 + CCBUF_DITH5_MODE[%s] + Compare and Capture Buffer + CCBUF[%s] + 0x70 + 32 + 0x00000000 + + + DITHERBUF + Dithering Buffer Cycle Number + 0 + 5 + + + CCBUF + Channel Compare/Capture Buffer Value + 5 + 19 + + + + + 4 + 4 + CCBUF_DITH6_MODE[%s] + Compare and Capture Buffer + CCBUF[%s] + 0x70 + 32 + 0x00000000 + + + DITHERBUF + Dithering Buffer Cycle Number + 0 + 6 + + + CCBUF + Channel Compare/Capture Buffer Value + 6 + 18 + + + + + + + TCC1 + 0x42002800 + + TCC1 + 18 + + + + TCC2 + 0x42002C00 + + TCC2 + 19 + + + + TSENS + U22611.0.1 + Temperature Sensor + TSENS + TSENS_ + 0x40003000 + + 0 + 0x25 + registers + + + TSENS + 5 + + + + CTRLA + Control A Register + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + + + CTRLB + Control B Register + 0x1 + 8 + write-only + 0x00 + + + START + Start Measurement + 0 + 1 + + + + + CTRLC + Control C Register + 0x2 + 8 + 0x00 + + + WINMODE + Window Monitor Mode + 0 + 3 + + WINMODESelect + + DISABLE + No window mode (default) + 0 + + + ABOVE + VALUE greater than WINLT + 1 + + + BELOW + VALUE less than WINUT + 2 + + + INSIDE + VALUE greater than WINLT and VALUE less than WINUT + 3 + + + OUTSIDE + VALUE less than WINLT or VALUE greater than WINUT + 4 + + + HYST_ABOVE + VALUE greater than WINUT with hysteresis to WINLT + 5 + + + HYST_BELOW + VALUE less than WINLST with hysteresis to WINUT + 6 + + + + + FREERUN + Free Running Measurement + 4 + 1 + + + + + EVCTRL + Event Control Register + 0x3 + 8 + 0x00 + + + STARTEI + Start Conversion Event Input Enable + 0 + 1 + + + STARTINV + Start Conversion Event Invert Enable + 1 + 1 + + + WINEO + Window Monitor Event Out + 2 + 1 + + + + + INTENCLR + Interrupt Enable Clear Register + 0x4 + 8 + 0x00 + + + RESRDY + Result Ready Interrupt Enable + 0 + 1 + + + OVERRUN + Overrun Interrupt Enable + 1 + 1 + + + WINMON + Window Monitor Interrupt Enable + 2 + 1 + + + OVF + Overflow Interrupt Enable + 3 + 1 + + + + + INTENSET + Interrupt Enable Set Register + 0x5 + 8 + 0x00 + + + RESRDY + Result Ready Interrupt Enable + 0 + 1 + + + OVERRUN + Overrun Interrupt Enable + 1 + 1 + + + WINMON + Window Monitor Interrupt Enable + 2 + 1 + + + OVF + Overflow Interrupt Enable + 3 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear Register + 0x6 + 8 + 0x00 + + + RESRDY + Result Ready + 0 + 1 + + + OVERRUN + Overrun + 1 + 1 + + + WINMON + Window Monitor + 2 + 1 + + + OVF + Overflow + 3 + 1 + + + + + STATUS + Status Register + 0x7 + 8 + read-only + 0x00 + + + OVF + Result Overflow + 0 + 1 + + + + + SYNCBUSY + Synchronization Busy Register + 0x8 + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Busy + 0 + 1 + + + ENABLE + Enable Busy + 1 + 1 + + + + + VALUE + Value Register + 0xC + 32 + read-only + 0x00000000 + + + VALUE + Measurement Value + 0 + 24 + + + + + WINLT + Window Monitor Lower Threshold Register + 0x10 + 32 + 0x00000000 + + + WINLT + Window Lower Threshold + 0 + 24 + + + + + WINUT + Window Monitor Upper Threshold Register + 0x14 + 32 + 0x00000000 + + + WINUT + Window Upper Threshold + 0 + 24 + + + + + GAIN + Gain Register + 0x18 + 32 + 0x00000000 + + + GAIN + Time Amplifier Gain + 0 + 24 + + + + + OFFSET + Offset Register + 0x1C + 32 + 0x00000000 + + + OFFSETC + Offset Correction + 0 + 24 + + + + + CAL + Calibration Register + 0x20 + 32 + 0x00000000 + + + FCAL + Frequency Calibration + 0 + 6 + + + TCAL + Temperature Calibration + 8 + 6 + + + + + DBGCTRL + Debug Control Register + 0x24 + 8 + 0x00 + + + DBGRUN + Debug Run + 0 + 1 + + + + + + + WDT + U22511.0.1 + Watchdog Timer + WDT + WDT_ + 0x40002000 + + 0 + 0xD + registers + + + WDT + 1 + + + + CTRLA + Control + 0x0 + 8 + 0x00 + + + ENABLE + Enable + 1 + 1 + + + WEN + Watchdog Timer Window Mode Enable + 2 + 1 + + + ALWAYSON + Always-On + 7 + 1 + + + + + CONFIG + Configuration + 0x1 + 8 + 0xBB + + + PER + Time-Out Period + 0 + 4 + + PERSelect + + CYC8 + 8 clock cycles + 0x0 + + + CYC16 + 16 clock cycles + 0x1 + + + CYC32 + 32 clock cycles + 0x2 + + + CYC64 + 64 clock cycles + 0x3 + + + CYC128 + 128 clock cycles + 0x4 + + + CYC256 + 256 clock cycles + 0x5 + + + CYC512 + 512 clock cycles + 0x6 + + + CYC1024 + 1024 clock cycles + 0x7 + + + CYC2048 + 2048 clock cycles + 0x8 + + + CYC4096 + 4096 clock cycles + 0x9 + + + CYC8192 + 8192 clock cycles + 0xA + + + CYC16384 + 16384 clock cycles + 0xB + + + + + WINDOW + Window Mode Time-Out Period + 4 + 4 + + WINDOWSelect + + CYC8 + 8 clock cycles + 0x0 + + + CYC16 + 16 clock cycles + 0x1 + + + CYC32 + 32 clock cycles + 0x2 + + + CYC64 + 64 clock cycles + 0x3 + + + CYC128 + 128 clock cycles + 0x4 + + + CYC256 + 256 clock cycles + 0x5 + + + CYC512 + 512 clock cycles + 0x6 + + + CYC1024 + 1024 clock cycles + 0x7 + + + CYC2048 + 2048 clock cycles + 0x8 + + + CYC4096 + 4096 clock cycles + 0x9 + + + CYC8192 + 8192 clock cycles + 0xA + + + CYC16384 + 16384 clock cycles + 0xB + + + + + + + EWCTRL + Early Warning Interrupt Control + 0x2 + 8 + 0x0B + + + EWOFFSET + Early Warning Interrupt Time Offset + 0 + 4 + + EWOFFSETSelect + + CYC8 + 8 clock cycles + 0x0 + + + CYC16 + 16 clock cycles + 0x1 + + + CYC32 + 32 clock cycles + 0x2 + + + CYC64 + 64 clock cycles + 0x3 + + + CYC128 + 128 clock cycles + 0x4 + + + CYC256 + 256 clock cycles + 0x5 + + + CYC512 + 512 clock cycles + 0x6 + + + CYC1024 + 1024 clock cycles + 0x7 + + + CYC2048 + 2048 clock cycles + 0x8 + + + CYC4096 + 4096 clock cycles + 0x9 + + + CYC8192 + 8192 clock cycles + 0xA + + + CYC16384 + 16384 clock cycles + 0xB + + + + + + + INTENCLR + Interrupt Enable Clear + 0x4 + 8 + 0x00 + + + EW + Early Warning Interrupt Enable + 0 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x5 + 8 + 0x00 + + + EW + Early Warning Interrupt Enable + 0 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x6 + 8 + 0x00 + + + EW + Early Warning + 0 + 1 + + + + + SYNCBUSY + Synchronization Busy + 0x8 + 32 + read-only + 0x00000000 + + + ENABLE + Enable Busy + 1 + 1 + + + WEN + Window Enable Busy + 2 + 1 + + + ALWAYSON + Always-On Busy + 3 + 1 + + + CLEAR + Clear Busy + 4 + 1 + + + + + CLEAR + Clear + 0xC + 8 + write-only + 0x00 + + + CLEAR + Watchdog Clear + 0 + 8 + + CLEARSelect + + KEY + Clear Key + 0xA5 + + + + + + + + + MPU + Memory Protection Unit + MPU + MPU_ + 0xE000ED90 + + 0 + 0x14 + registers + + + + TYPE + MPU Type Register + 0x0 + 32 + read-only + + + SEPARATE + Separate instruction and Data Memory MapsRegions + 0 + 1 + + + DREGION + Number of Data Regions + 8 + 8 + + + IREGION + Number of Instruction Regions + 16 + 8 + + + + + CTRL + MPU Control Register + 0x4 + 32 + + + ENABLE + MPU Enable + 0 + 1 + + + HFNMIENA + Enable Hard Fault and NMI handlers + 1 + 1 + + + PRIVDEFENA + Enables privileged software access to default memory map + 2 + 1 + + + + + RNR + MPU Region Number Register + 0x8 + 32 + + + REGION + Region referenced by RBAR and RASR + 0 + 8 + + + + + RBAR + MPU Region Base Address Register + 0xC + 32 + + + REGION + Region number + 0 + 4 + + + VALID + Region number valid + 4 + 1 + + + ADDR + Region base address + 5 + 27 + + + + + RASR + MPU Region Attribute and Size Register + 0x10 + 32 + + + ENABLE + Region Enable + 0 + 1 + + + SIZE + Region Size + 1 + 5 + + + SRD + Sub-region disable + 8 + 8 + + + B + Bufferable bit + 16 + 1 + + + C + Cacheable bit + 17 + 1 + + + S + Shareable bit + 18 + 1 + + + TEX + TEX bit + 19 + 3 + + + AP + Access Permission + 24 + 3 + + + XN + Execute Never Attribute + 28 + 1 + + + + + + + NVIC + Nested Vectored Interrupt Controller + NVIC + NVIC_ + 0xE000E100 + + 0 + 0x320 + registers + + + + ISER + Interrupt Set Enable Register + 0x0 + 32 + 0x00000000 + + + SETENA + Interrupt set enable bits + 0 + 31 + + + + + ICER + Interrupt Clear Enable Register + 0x80 + 32 + 0x00000000 + + + CLRENA + Interrupt clear-enable bits + 0 + 31 + + + + + ISPR + Interrupt Set Pending Register + 0x100 + 32 + 0x00000000 + + + SETPEND + Interrupt set-pending bits + 0 + 31 + + + + + ICPR + Interrupt Clear Pending Register + 0x180 + 32 + 0x00000000 + + + CLRPEND + Interrupt clear-pending bits + 0 + 31 + + + + + 8 + 4 + IPR[%s] + Interrupt Priority Register n + 0x300 + 32 + 0x00000000 + + + PRI0 + Priority of interrupt n + 0 + 2 + + + PRI1 + Priority of interrupt n + 8 + 2 + + + PRI2 + Priority of interrupt n + 16 + 2 + + + PRI3 + Priority of interrupt n + 24 + 2 + + + + + + + SysTick + System timer + SysTick + SysTick_ + 0xE000E010 + + 0 + 0x10 + registers + + + + CSR + SysTick Control and Status Register + 0x0 + 32 + 0x4 + + + ENABLE + SysTick Counter Enable + 0 + 1 + + ENABLESelect + + VALUE_0 + Counter disabled + 0 + + + VALUE_1 + Counter enabled + 1 + + + + + TICKINT + SysTick Exception Request Enable + 1 + 1 + + TICKINTSelect + + VALUE_0 + Counting down to 0 does not assert the SysTick exception request + 0 + + + VALUE_1 + Counting down to 0 asserts the SysTick exception request + 1 + + + + + CLKSOURCE + Clock Source 0=external, 1=processor + 2 + 1 + + CLKSOURCESelect + + VALUE_0 + External clock + 0 + + + VALUE_1 + Processor clock + 1 + + + + + COUNTFLAG + Timer counted to 0 since last read of register + 16 + 1 + + + + + RVR + SysTick Reload Value Register + 0x4 + 32 + + + RELOAD + Value to load into the SysTick Current Value Register when the counter reaches 0 + 0 + 24 + + + + + CVR + SysTick Current Value Register + 0x8 + 32 + + + CURRENT + Current value at the time the register is accessed + 0 + 24 + + + + + CALIB + SysTick Calibration Value Register + 0xC + 32 + read-only + 0 + + + TENMS + Reload value to use for 10ms timing + 0 + 24 + + + SKEW + TENMS is rounded from non-integer ratio + 30 + 1 + + SKEWSelect + + VALUE_0 + 10ms calibration value is exact + 0 + + + VALUE_1 + 10ms calibration value is inexact, because of the clock frequency + 1 + + + + + NOREF + No Separate Reference Clock + 31 + 1 + + NOREFSelect + + VALUE_0 + The reference clock is provided + 0 + + + VALUE_1 + The reference clock is not provided + 1 + + + + + + + + + SystemControl + System Control Registers + SystemControl + SystemControl_ + 0xE000E000 + + 0 + 0xD34 + registers + + + + CPUID + CPUID Base Register + 0xD00 + 32 + read-only + 0x410CC601 + + + REVISION + Minor revision number + 0 + 4 + + + PARTNO + Processor Part Number, 0xC60=Cortex-M0+ + 4 + 12 + + + ARCHITECTURE + Processor Architecture, 0xC=ARMv6-M + 16 + 4 + + + VARIANT + Major revision number + 20 + 4 + + + IMPLEMENTER + Implementer code, ARM=0x41 + 24 + 8 + + + + + ICSR + Interrupt Control and State Register + 0xD04 + 32 + 0x00000000 + + + VECTACTIVE + Debug: Exception number of currently executing exception, or 0 if thread mode + 0 + 9 + + + VECTPENDING + Exception number of the highest priority pending enabled exception + 12 + 9 + + + ISRPENDING + Debug: NVIC interrupt pending + 22 + 1 + + + ISRPREEMPT + Debug: Pending exception serviced on exit from debug halt + 23 + 1 + + + PENDSTCLR + SysTick exception clear-pending bit + 25 + 1 + + PENDSTCLRSelect + + VALUE_0 + No effect + 0 + + + VALUE_1 + Removes the pending state from the SysTick exception + 1 + + + + + PENDSTSET + SysTick exception set-pending bit + 26 + 1 + + PENDSTSETSelect + + VALUE_0 + Write: no effect; read: SysTick exception is not pending + 0 + + + VALUE_1 + Write: changes SysTick exception state to pending; read: SysTick exception is pending + 1 + + + + + PENDSVCLR + PendSV clear-pending bit + 27 + 1 + + PENDSVCLRSelect + + VALUE_0 + No effect + 0 + + + VALUE_1 + Removes the pending state from the PendSV exception + 1 + + + + + PENDSVSET + PendSV set-pending bit + 28 + 1 + + PENDSVSETSelect + + VALUE_0 + Write: no effect; read: PendSV exception is not pending + 0 + + + VALUE_1 + Write: changes PendSV exception state to pending; read: PendSV exception is pending + 1 + + + + + NMIPENDSET + NMI set-pending bit + 31 + 1 + + NMIPENDSETSelect + + VALUE_0 + Write: no effect; read: NMI exception is not pending + 0 + + + VALUE_1 + Write: changes NMI exception state to pending; read: NMI exception is pending + 1 + + + + + + + VTOR + Vector Table Offset Register + 0xD08 + 32 + 0x00000000 + + + TBLOFF + Vector table base offset + 7 + 25 + + + + + AIRCR + Application Interrupt and Reset Control Register + 0xD0C + 32 + 0x00000000 + + + VECTCLRACTIVE + Debug: Clear state information + 1 + 1 + + + SYSRESETREQ + System Reset Request + 2 + 1 + + SYSRESETREQSelect + + VALUE_0 + No system reset request + 0 + + + VALUE_1 + Asserts a signal to the outer system that requests a reset + 1 + + + + + ENDIANNESS + Data Endianness, 0=little, 1=big + 15 + 1 + + ENDIANNESSSelect + + VALUE_0 + Little-endian + 0 + + + VALUE_1 + Big-endian + 1 + + + + + VECTKEY + Register key (0x05FA) + 16 + 16 + + + + + SCR + System Control Register + 0xD10 + 32 + 0x00000000 + + + SLEEPONEXIT + Sleep-On-Exit when exiting Handler mode + 1 + 1 + + SLEEPONEXITSelect + + VALUE_0 + O not sleep when returning to Thread mode + 0 + + + VALUE_1 + Enter sleep, or deep sleep, on return from an ISR + 1 + + + + + SLEEPDEEP + Uses Deep Sleep as low power mode + 2 + 1 + + SLEEPDEEPSelect + + VALUE_0 + Sleep + 0 + + + VALUE_1 + Deep sleep + 1 + + + + + SEVONPEND + Send Event on Pending bit + 4 + 1 + + SEVONPENDSelect + + VALUE_0 + Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded + 0 + + + VALUE_1 + Enabled events and all interrupts, including disabled interrupts, can wakeup the processor + 1 + + + + + + + CCR + Configuration and Control Register + 0xD14 + 32 + read-only + 0x00000204 + + + UNALIGN_TRP + Unaligned accesses generates a Hard Fault + 3 + 1 + + UNALIGN_TRPSelect + + VALUE_0 + Do not trap unaligned halfword and word accesses + 0 + + + VALUE_1 + Trap unaligned halfword and word accesses + 1 + + + + + STKALIGN + Stack 8-byte aligned on exception entry + 9 + 1 + + STKALIGNSelect + + VALUE_0 + 4-byte aligned + 0 + + + VALUE_1 + 8-byte aligned + 1 + + + + + + + SHPR2 + System Handler Priority Register 2 + 0xD1C + 32 + 0x00000000 + + + PRI_11 + Priority of system handler 11, SVCall + 24 + 8 + + + + + SHPR3 + System Handler Priority Register 3 + 0xD20 + 32 + 0x00000000 + + + PRI_14 + Priority of system handler 14, PendSV + 16 + 8 + + + PRI_15 + Priority of system handler 15, SysTick exception + 24 + 8 + + + + + SHCSR + System Handler Control and State Register + 0xD24 + 32 + 0x00000000 + + + SVCALLPENDED + 15 + 1 + + + + + DFSR + Debug Fault Status Register + 0xD30 + 32 + 0x00000000 + + + HALTED + Halt request debug event active + 0 + 1 + + + BKPT + Breakpoint debug event + 1 + 1 + + + DWTTRAP + DWT debug event + 2 + 1 + + + VCATCH + Vector catch debug event + 3 + 1 + + + EXTERNAL + EDBGRQ debug event + 4 + 1 + + + + + + + diff --git a/svd/ATSAMC21G18A.svd b/svd/ATSAMC21G18A.svd new file mode 100644 index 000000000000..cf5c25b04e1c --- /dev/null +++ b/svd/ATSAMC21G18A.svd @@ -0,0 +1,27996 @@ + + + + Microchip Technology + MCHP + ATSAMC21G18A + SAMC21 + 0 + Microchip ATSAMC21G18A Microcontroller + + CM0+ + r0p0 + selectable + true + false + 2 + false + + 8 + 32 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + AC + U22451.1.1 + Analog Comparators + AC + AC_ + 0x42005000 + + 0 + 0x24 + registers + + + AC + 27 + + + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + + + CTRLB + Control B + 0x1 + 8 + write-only + 0x00 + + + START0 + Comparator 0 Start Comparison + 0 + 1 + + + START1 + Comparator 1 Start Comparison + 1 + 1 + + + START2 + Comparator 2 Start Comparison + 2 + 1 + + + START3 + Comparator 3 Start Comparison + 3 + 1 + + + + + EVCTRL + Event Control + 0x2 + 16 + 0x0000 + + + COMPEO0 + Comparator 0 Event Output Enable + 0 + 1 + + + COMPEO1 + Comparator 1 Event Output Enable + 1 + 1 + + + COMPEO2 + Comparator 2 Event Output Enable + 2 + 1 + + + COMPEO3 + Comparator 3 Event Output Enable + 3 + 1 + + + WINEO0 + Window 0 Event Output Enable + 4 + 1 + + + WINEO1 + Window 1 Event Output Enable + 5 + 1 + + + COMPEI0 + Comparator 0 Event Input Enable + 8 + 1 + + + COMPEI1 + Comparator 1 Event Input Enable + 9 + 1 + + + COMPEI2 + Comparator 2 Event Input Enable + 10 + 1 + + + COMPEI3 + Comparator 3 Event Input Enable + 11 + 1 + + + INVEI0 + Comparator 0 Input Event Invert Enable + 12 + 1 + + + INVEI1 + Comparator 1 Input Event Invert Enable + 13 + 1 + + + INVEI2 + Comparator 2 Input Event Invert Enable + 14 + 1 + + + INVEI3 + Comparator 3 Input Event Invert Enable + 15 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x4 + 8 + 0x00 + + + COMP0 + Comparator 0 Interrupt Enable + 0 + 1 + + + COMP1 + Comparator 1 Interrupt Enable + 1 + 1 + + + COMP2 + Comparator 2 Interrupt Enable + 2 + 1 + + + COMP3 + Comparator 3 Interrupt Enable + 3 + 1 + + + WIN0 + Window 0 Interrupt Enable + 4 + 1 + + + WIN1 + Window 1 Interrupt Enable + 5 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x5 + 8 + 0x00 + + + COMP0 + Comparator 0 Interrupt Enable + 0 + 1 + + + COMP1 + Comparator 1 Interrupt Enable + 1 + 1 + + + COMP2 + Comparator 2 Interrupt Enable + 2 + 1 + + + COMP3 + Comparator 3 Interrupt Enable + 3 + 1 + + + WIN0 + Window 0 Interrupt Enable + 4 + 1 + + + WIN1 + Window 1 Interrupt Enable + 5 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x6 + 8 + 0x00 + + + COMP0 + Comparator 0 + 0 + 1 + + + COMP1 + Comparator 1 + 1 + 1 + + + COMP2 + Comparator 2 + 2 + 1 + + + COMP3 + Comparator 3 + 3 + 1 + + + WIN0 + Window 0 + 4 + 1 + + + WIN1 + Window 1 + 5 + 1 + + + + + STATUSA + Status A + 0x7 + 8 + read-only + 0x00 + + + STATE0 + Comparator 0 Current State + 0 + 1 + + + STATE1 + Comparator 1 Current State + 1 + 1 + + + STATE2 + Comparator 2 Current State + 2 + 1 + + + STATE3 + Comparator 3 Current State + 3 + 1 + + + WSTATE0 + Window 0 Current State + 4 + 2 + + WSTATE0Select + + ABOVE + Signal is above window + 0 + + + INSIDE + Signal is inside window + 1 + + + BELOW + Signal is below window + 2 + + + + + WSTATE1 + Window 1 Current State + 6 + 2 + + WSTATE1Select + + ABOVE + Signal is above window + 0 + + + INSIDE + Signal is inside window + 1 + + + BELOW + Signal is below window + 2 + + + + + + + STATUSB + Status B + 0x8 + 8 + read-only + 0x00 + + + READY0 + Comparator 0 Ready + 0 + 1 + + + READY1 + Comparator 1 Ready + 1 + 1 + + + READY2 + Comparator 2 Ready + 2 + 1 + + + READY3 + Comparator 3 Ready + 3 + 1 + + + + + DBGCTRL + Debug Control + 0x9 + 8 + 0x00 + + + DBGRUN + Debug Run + 0 + 1 + + + + + WINCTRL + Window Control + 0xA + 8 + 0x00 + + + WEN0 + Window 0 Mode Enable + 0 + 1 + + + WINTSEL0 + Window 0 Interrupt Selection + 1 + 2 + + WINTSEL0Select + + ABOVE + Interrupt on signal above window + 0 + + + INSIDE + Interrupt on signal inside window + 1 + + + BELOW + Interrupt on signal below window + 2 + + + OUTSIDE + Interrupt on signal outside window + 3 + + + + + WEN1 + Window 1 Mode Enable + 4 + 1 + + + WINTSEL1 + Window 1 Interrupt Selection + 5 + 2 + + WINTSEL1Select + + ABOVE + Interrupt on signal above window + 0 + + + INSIDE + Interrupt on signal inside window + 1 + + + BELOW + Interrupt on signal below window + 2 + + + OUTSIDE + Interrupt on signal outside window + 3 + + + + + + + 4 + 1 + SCALER[%s] + Scaler n + 0xC + 8 + 0x00 + + + VALUE + Scaler Value + 0 + 6 + + + + + 4 + 4 + COMPCTRL[%s] + Comparator Control n + 0x10 + 32 + 0x00000000 + + + ENABLE + Enable + 1 + 1 + + + SINGLE + Single-Shot Mode + 2 + 1 + + + INTSEL + Interrupt Selection + 3 + 2 + + INTSELSelect + + TOGGLE + Interrupt on comparator output toggle + 0 + + + RISING + Interrupt on comparator output rising + 1 + + + FALLING + Interrupt on comparator output falling + 2 + + + EOC + Interrupt on end of comparison (single-shot mode only) + 3 + + + + + RUNSTDBY + Run in Standby + 6 + 1 + + + MUXNEG + Negative Input Mux Selection + 8 + 3 + + MUXNEGSelect + + PIN0 + I/O pin 0 + 0 + + + PIN1 + I/O pin 1 + 1 + + + PIN2 + I/O pin 2 + 2 + + + PIN3 + I/O pin 3 + 3 + + + GND + Ground + 4 + + + VSCALE + VDD scaler + 5 + + + BANDGAP + Internal bandgap voltage + 6 + + + DAC + DAC output + 7 + + + + + MUXPOS + Positive Input Mux Selection + 12 + 3 + + MUXPOSSelect + + PIN0 + I/O pin 0 + 0 + + + PIN1 + I/O pin 1 + 1 + + + PIN2 + I/O pin 2 + 2 + + + PIN3 + I/O pin 3 + 3 + + + VSCALE + VDD Scaler + 4 + + + + + SWAP + Swap Inputs and Invert + 15 + 1 + + + SPEED + Speed Selection + 16 + 2 + + SPEEDSelect + + LOW + Low speed + 0 + + + HIGH + High speed + 3 + + + + + HYSTEN + Hysteresis Enable + 19 + 1 + + + FLEN + Filter Length + 24 + 3 + + FLENSelect + + OFF + No filtering + 0 + + + MAJ3 + 3-bit majority function (2 of 3) + 1 + + + MAJ5 + 5-bit majority function (3 of 5) + 2 + + + + + OUT + Output + 28 + 2 + + OUTSelect + + OFF + The output of COMPn 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USRRDY1 + Channel 1 User Ready + 1 + 1 + + + USRRDY2 + Channel 2 User Ready + 2 + 1 + + + USRRDY3 + Channel 3 User Ready + 3 + 1 + + + USRRDY4 + Channel 4 User Ready + 4 + 1 + + + USRRDY5 + Channel 5 User Ready + 5 + 1 + + + USRRDY6 + Channel 6 User Ready + 6 + 1 + + + USRRDY7 + Channel 7 User Ready + 7 + 1 + + + USRRDY8 + Channel 8 User Ready + 8 + 1 + + + USRRDY9 + Channel 9 User Ready + 9 + 1 + + + USRRDY10 + Channel 10 User Ready + 10 + 1 + + + USRRDY11 + Channel 11 User Ready + 11 + 1 + + + CHBUSY0 + Channel 0 Busy + 16 + 1 + + + CHBUSY1 + Channel 1 Busy + 17 + 1 + + + CHBUSY2 + Channel 2 Busy + 18 + 1 + + + CHBUSY3 + Channel 3 Busy + 19 + 1 + + + CHBUSY4 + Channel 4 Busy + 20 + 1 + + + CHBUSY5 + Channel 5 Busy + 21 + 1 + + + CHBUSY6 + Channel 6 Busy + 22 + 1 + + + CHBUSY7 + Channel 7 Busy + 23 + 1 + + + CHBUSY8 + Channel 8 Busy + 24 + 1 + + + CHBUSY9 + Channel 9 Busy + 25 + 1 + + + CHBUSY10 + Channel 10 Busy + 26 + 1 + + + CHBUSY11 + Channel 11 Busy + 27 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x10 + 32 + 0x00000000 + + + OVR0 + Channel 0 Overrun Interrupt Enable + 0 + 1 + + + OVR1 + Channel 1 Overrun Interrupt Enable + 1 + 1 + + + OVR2 + Channel 2 Overrun Interrupt Enable + 2 + 1 + + + OVR3 + Channel 3 Overrun Interrupt Enable + 3 + 1 + + + OVR4 + Channel 4 Overrun Interrupt Enable + 4 + 1 + + + OVR5 + Channel 5 Overrun Interrupt Enable + 5 + 1 + + + OVR6 + Channel 6 Overrun Interrupt Enable + 6 + 1 + + + OVR7 + Channel 7 Overrun Interrupt Enable + 7 + 1 + + + OVR8 + Channel 8 Overrun Interrupt Enable + 8 + 1 + + + OVR9 + Channel 9 Overrun Interrupt Enable + 9 + 1 + + + OVR10 + Channel 10 Overrun Interrupt Enable + 10 + 1 + + + OVR11 + Channel 11 Overrun Interrupt Enable + 11 + 1 + + + EVD0 + Channel 0 Event Detection Interrupt Enable + 16 + 1 + + + EVD1 + Channel 1 Event Detection Interrupt Enable + 17 + 1 + + + EVD2 + Channel 2 Event Detection Interrupt Enable + 18 + 1 + + + EVD3 + Channel 3 Event Detection Interrupt Enable + 19 + 1 + + + EVD4 + Channel 4 Event Detection Interrupt Enable + 20 + 1 + + + EVD5 + Channel 5 Event Detection Interrupt Enable + 21 + 1 + + + EVD6 + Channel 6 Event Detection Interrupt Enable + 22 + 1 + + + EVD7 + Channel 7 Event Detection Interrupt Enable + 23 + 1 + + + EVD8 + Channel 8 Event Detection Interrupt Enable + 24 + 1 + + + EVD9 + Channel 9 Event Detection Interrupt Enable + 25 + 1 + + + EVD10 + Channel 10 Event Detection Interrupt Enable + 26 + 1 + + + EVD11 + Channel 11 Event Detection Interrupt Enable + 27 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x14 + 32 + 0x00000000 + + + OVR0 + Channel 0 Overrun Interrupt Enable + 0 + 1 + + + OVR1 + Channel 1 Overrun Interrupt Enable + 1 + 1 + + + OVR2 + Channel 2 Overrun Interrupt Enable + 2 + 1 + + + OVR3 + Channel 3 Overrun Interrupt Enable + 3 + 1 + + + OVR4 + Channel 4 Overrun Interrupt Enable + 4 + 1 + + + OVR5 + Channel 5 Overrun Interrupt Enable + 5 + 1 + + + OVR6 + Channel 6 Overrun Interrupt Enable + 6 + 1 + + + OVR7 + Channel 7 Overrun Interrupt Enable + 7 + 1 + + + OVR8 + Channel 8 Overrun Interrupt Enable + 8 + 1 + + + OVR9 + Channel 9 Overrun Interrupt Enable + 9 + 1 + + + OVR10 + Channel 10 Overrun Interrupt Enable + 10 + 1 + + + OVR11 + Channel 11 Overrun Interrupt Enable + 11 + 1 + + + EVD0 + Channel 0 Event Detection Interrupt Enable + 16 + 1 + + + EVD1 + Channel 1 Event Detection Interrupt Enable + 17 + 1 + + + EVD2 + Channel 2 Event Detection Interrupt Enable + 18 + 1 + + + EVD3 + Channel 3 Event Detection Interrupt Enable + 19 + 1 + + + EVD4 + Channel 4 Event Detection Interrupt Enable + 20 + 1 + + + EVD5 + Channel 5 Event Detection Interrupt Enable + 21 + 1 + + + EVD6 + Channel 6 Event Detection Interrupt Enable + 22 + 1 + + + EVD7 + Channel 7 Event Detection Interrupt Enable + 23 + 1 + + + EVD8 + Channel 8 Event Detection Interrupt Enable + 24 + 1 + + + EVD9 + Channel 9 Event Detection Interrupt Enable + 25 + 1 + + + EVD10 + Channel 10 Event Detection Interrupt Enable + 26 + 1 + + + EVD11 + Channel 11 Event Detection Interrupt Enable + 27 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x18 + 32 + 0x00000000 + + + OVR0 + Channel 0 Overrun + 0 + 1 + + + OVR1 + Channel 1 Overrun + 1 + 1 + + + OVR2 + Channel 2 Overrun + 2 + 1 + + + OVR3 + Channel 3 Overrun + 3 + 1 + + + OVR4 + Channel 4 Overrun + 4 + 1 + + + OVR5 + Channel 5 Overrun + 5 + 1 + + + OVR6 + Channel 6 Overrun + 6 + 1 + + + OVR7 + Channel 7 Overrun + 7 + 1 + + + OVR8 + Channel 8 Overrun + 8 + 1 + + + OVR9 + Channel 9 Overrun + 9 + 1 + + + OVR10 + Channel 10 Overrun + 10 + 1 + + + OVR11 + Channel 11 Overrun + 11 + 1 + + + EVD0 + Channel 0 Event Detection + 16 + 1 + + + EVD1 + Channel 1 Event Detection + 17 + 1 + + + EVD2 + Channel 2 Event Detection + 18 + 1 + + + EVD3 + Channel 3 Event Detection + 19 + 1 + + + EVD4 + Channel 4 Event Detection + 20 + 1 + + + EVD5 + Channel 5 Event Detection + 21 + 1 + + + EVD6 + Channel 6 Event Detection + 22 + 1 + + + EVD7 + Channel 7 Event Detection + 23 + 1 + + + EVD8 + Channel 8 Event Detection + 24 + 1 + + + EVD9 + Channel 9 Event Detection + 25 + 1 + + + EVD10 + Channel 10 Event Detection + 26 + 1 + + + EVD11 + Channel 11 Event Detection + 27 + 1 + + + + + SWEVT + Software Event + 0x1C + 32 + write-only + 0x00000000 + + + CHANNEL0 + Channel 0 Software Selection + 0 + 1 + + + CHANNEL1 + Channel 1 Software Selection + 1 + 1 + + + CHANNEL2 + Channel 2 Software Selection + 2 + 1 + + + CHANNEL3 + Channel 3 Software Selection + 3 + 1 + + + CHANNEL4 + Channel 4 Software Selection + 4 + 1 + + + CHANNEL5 + Channel 5 Software Selection + 5 + 1 + + + CHANNEL6 + Channel 6 Software Selection + 6 + 1 + + + CHANNEL7 + Channel 7 Software Selection + 7 + 1 + + + CHANNEL8 + Channel 8 Software Selection + 8 + 1 + + + CHANNEL9 + Channel 9 Software Selection + 9 + 1 + + + CHANNEL10 + Channel 10 Software Selection + 10 + 1 + + + CHANNEL11 + Channel 11 Software Selection + 11 + 1 + + + + + 12 + 4 + CHANNEL[%s] + Channel n + 0x20 + 32 + 0x00008000 + + + EVGEN + Event Generator Selection + 0 + 7 + + + PATH + Path Selection + 8 + 2 + + PATHSelect + + SYNCHRONOUS + Synchronous path + 0 + + + RESYNCHRONIZED + Resynchronized path + 1 + + + ASYNCHRONOUS + Asynchronous path + 2 + + + + + EDGSEL + Edge Detection Selection + 10 + 2 + + EDGSELSelect + + NO_EVT_OUTPUT + No event output when using the resynchronized or synchronous path + 0 + + + RISING_EDGE + Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path + 1 + + + FALLING_EDGE + Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path + 2 + + + BOTH_EDGES + Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path + 3 + + + + + RUNSTDBY + Run in standby + 14 + 1 + + + ONDEMAND + Generic Clock On Demand + 15 + 1 + + + + + 47 + 4 + USER[%s] + User Multiplexer n + 0x80 + 32 + 0x00000000 + + + CHANNEL + Channel Event Selection + 0 + 5 + + + + + + + FREQM + U22571.0.1 + Frequency Meter + FREQM + FREQM_ + 0x40002C00 + + 0 + 0x14 + registers + + + FREQM + 4 + + + + CTRLA + Control A Register + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + + + CTRLB + Control B Register + 0x1 + 8 + write-only + 0x00 + + + START + Start Measurement + 0 + 1 + + + + + CFGA + Config A register + 0x2 + 16 + 0x0000 + + + REFNUM + Number of Reference Clock Cycles + 0 + 8 + + + + + INTENCLR + Interrupt Enable Clear Register + 0x8 + 8 + 0x00 + + + DONE + Measurement Done Interrupt Enable + 0 + 1 + + + + + INTENSET + Interrupt Enable Set Register + 0x9 + 8 + 0x00 + + + DONE + Measurement Done Interrupt Enable + 0 + 1 + + + + + INTFLAG + Interrupt Flag Register + 0xA + 8 + 0x00 + + + DONE + Measurement Done + 0 + 1 + + + + + STATUS + Status Register + 0xB + 8 + 0x00 + + + BUSY + FREQM Status + 0 + 1 + + + OVF + Sticky Count Value Overflow + 1 + 1 + + + + + SYNCBUSY + Synchronization Busy Register + 0xC + 32 + read-only + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + + + VALUE + Count Value Register + 0x10 + 32 + read-only + 0x00000000 + + + VALUE + Measurement Value + 0 + 24 + + + + + + + GCLK + U21221.1.1 + Generic Clock Generator + GCLK + GCLK_ + 0x40001C00 + + 0 + 0x184 + registers + + + + CTRLA + Control + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + + + SYNCBUSY + Synchronization Busy + 0x4 + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchroniation Busy bit + 0 + 1 + + + GENCTRL0 + Generic Clock Generator Control 0 Synchronization Busy bits + 2 + 1 + + GENCTRL0Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + + + GENCTRL1 + Generic Clock Generator Control 1 Synchronization Busy bits + 3 + 1 + + GENCTRL1Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + + + GENCTRL2 + Generic Clock Generator Control 2 Synchronization Busy bits + 4 + 1 + + GENCTRL2Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + + + GENCTRL3 + Generic Clock Generator Control 3 Synchronization Busy bits + 5 + 1 + + GENCTRL3Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + + + GENCTRL4 + Generic Clock Generator Control 4 Synchronization Busy bits + 6 + 1 + + GENCTRL4Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + + + GENCTRL5 + Generic Clock Generator Control 5 Synchronization Busy bits + 7 + 1 + + GENCTRL5Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + + + GENCTRL6 + Generic Clock Generator Control 6 Synchronization Busy bits + 8 + 1 + + GENCTRL6Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + + + GENCTRL7 + Generic Clock Generator Control 7 Synchronization Busy bits + 9 + 1 + + GENCTRL7Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + + + GENCTRL8 + Generic Clock Generator Control 8 Synchronization Busy bits + 10 + 1 + + GENCTRL8Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + + + + + 9 + 4 + GENCTRL[%s] + Generic Clock Generator Control + 0x20 + 32 + 0x00000000 + + + SRC + Source Select + 0 + 3 + + SRCSelect + + XOSC + XOSC oscillator output + 0 + + + GCLKIN + Generator input pad + 1 + + + GCLKGEN1 + Generic clock generator 1 output + 2 + + + OSCULP32K + OSCULP32K oscillator output + 3 + + + OSC32K + OSC32K oscillator output + 4 + + + XOSC32K + XOSC32K oscillator output + 5 + + + OSC48M + OSC48M oscillator output + 6 + + + DPLL96M + DPLL96M output + 7 + + + + + GENEN + Generic Clock Generator Enable + 8 + 1 + + + IDC + Improve Duty Cycle + 9 + 1 + + + OOV + Output Off Value + 10 + 1 + + + OE + Output Enable + 11 + 1 + + + DIVSEL + Divide Selection + 12 + 1 + + DIVSELSelect + + DIV1 + Divide input directly by divider factor + 0x0 + + + DIV2 + Divide input by 2^(divider factor+ 1) + 0x1 + + + + + RUNSTDBY + Run in Standby + 13 + 1 + + + DIV + Division Factor + 16 + 16 + + + + + 41 + 4 + PCHCTRL[%s] + Peripheral Clock Control + 0x80 + 32 + 0x00000000 + + + GEN + Generic Clock Generator + 0 + 4 + + GENSelect + + GCLK0 + Generic clock generator 0 + 0x0 + + + GCLK1 + Generic clock generator 1 + 0x1 + + + GCLK2 + Generic clock generator 2 + 0x2 + + + GCLK3 + Generic clock generator 3 + 0x3 + + + GCLK4 + Generic clock generator 4 + 0x4 + + + GCLK5 + Generic clock generator 5 + 0x5 + + + GCLK6 + Generic clock generator 6 + 0x6 + + + GCLK7 + Generic clock generator 7 + 0x7 + + + GCLK8 + Generic clock generator 8 + 0x8 + + + + + CHEN + Channel Enable + 6 + 1 + + + WRTLOCK + Write Lock + 7 + 1 + + + + + + + HMATRIXHS + I76382.1.3 + HSB Matrix + HMATRIXB + HMATRIXB_ + 0x4100A000 + + 0 + 0x168 + registers + + + + 16 + 4 + MCFG[%s] + Master Configuration + 0x0 + 32 + 0x00000002 + + + ULBT + Undefined Length Burst Type + 0 + 3 + + ULBTSelect + + INFINITE + Infinite Length + 0 + + + SINGLE + Single Access + 1 + + + FOUR_BEAT + Four Beat Burst + 2 + + + EIGHT_BEAT + Eight Beat Burst + 3 + + + SIXTEEN_BEAT + Sixteen Beat Burst + 4 + + + + + + + 16 + 4 + SCFG[%s] + Slave Configuration + 0x40 + 32 + 0x00000010 + + + SLOT_CYCLE + Maximum Number of Allowed Cycles for a Burst + 0 + 8 + + + DEFMSTR_TYPE + Default Master Type + 16 + 2 + + DEFMSTR_TYPESelect + + NO_DEFAULT + No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. + 0 + + + LAST_DEFAULT + Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. + 1 + + + FIXED_DEFAULT + Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave. + 2 + + + + + FIXED_DEFMSTR + Fixed Index of Default Master + 18 + 4 + + + ARBT + Arbitration Type + 24 + 1 + + ARBTSelect + + ROUND_ROBIN + Round-Robin Arbitration + 0 + + + FIXED_PRIORITY + Fixed Priority Arbitration + 1 + + + + + + + 4 + 0x8 + PRS[%s] + + 0x080 + + PRAS + Priority A for Slave + 0x0 + 32 + 0x00000000 + + + M0PR + Master 0 Priority + 0 + 4 + + + M1PR + Master 1 Priority + 4 + 4 + + + M2PR + Master 2 Priority + 8 + 4 + + + M3PR + Master 3 Priority + 12 + 4 + + + M4PR + Master 4 Priority + 16 + 4 + + + M5PR + Master 5 Priority + 20 + 4 + + + M6PR + Master 6 Priority + 24 + 4 + + + M7PR + Master 7 Priority + 28 + 4 + + + + + PRBS + Priority B for Slave + 0x4 + 32 + 0x00000000 + + + M8PR + Master 8 Priority + 0 + 4 + + + M9PR + Master 9 Priority + 4 + 4 + + + M10PR + Master 10 Priority + 8 + 4 + + + M11PR + Master 11 Priority + 12 + 4 + + + M12PR + Master 12 Priority + 16 + 4 + + + M13PR + Master 13 Priority + 20 + 4 + + + M14PR + Master 14 Priority + 24 + 4 + + + M15PR + Master 15 Priority + 28 + 4 + + + + + + MRCR + Master Remap Control + 0x100 + 32 + 0x00000000 + + + RCB0 + Remap Command Bit for Master 0 + 0 + 1 + + RCB0Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB1 + Remap Command Bit for Master 1 + 1 + 1 + + RCB1Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB2 + Remap Command Bit for Master 2 + 2 + 1 + + RCB2Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB3 + Remap Command Bit for Master 3 + 3 + 1 + + RCB3Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB4 + Remap Command Bit for Master 4 + 4 + 1 + + RCB4Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB5 + Remap Command Bit for Master 5 + 5 + 1 + + RCB5Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB6 + Remap Command Bit for Master 6 + 6 + 1 + + RCB6Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB7 + Remap Command Bit for Master 7 + 7 + 1 + + RCB7Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB8 + Remap Command Bit for Master 8 + 8 + 1 + + RCB8Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB9 + Remap Command Bit for Master 9 + 9 + 1 + + RCB9Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB10 + Remap Command Bit for Master 10 + 10 + 1 + + RCB10Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB11 + Remap Command Bit for Master 11 + 11 + 1 + + RCB11Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB12 + Remap Command Bit for Master 12 + 12 + 1 + + RCB12Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB13 + Remap Command Bit for Master 13 + 13 + 1 + + RCB13Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB14 + Remap Command Bit for Master 14 + 14 + 1 + + RCB14Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB15 + Remap Command Bit for Master 15 + 15 + 1 + + RCB15Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + + + 16 + 4 + SFR[%s] + Special Function + 0x110 + 32 + 0x00000000 + + + SFR + Special Function Register + 0 + 32 + + + + + + + MCLK + U22342.0.0 + Main Clock + MCLK + MCLK_ + 0x40000800 + + 0 + 0x20 + registers + + + + INTENCLR + Interrupt Enable Clear + 0x1 + 8 + 0x00 + + + CKRDY + Clock Ready Interrupt Enable + 0 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x2 + 8 + 0x00 + + + CKRDY + Clock Ready Interrupt Enable + 0 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x3 + 8 + 0x01 + + + CKRDY + Clock Ready + 0 + 1 + + + + + CPUDIV + CPU Clock Division + 0x4 + 8 + 0x01 + + + CPUDIV + CPU Clock Division Factor + 0 + 8 + + CPUDIVSelect + + DIV1 + Divide by 1 + 0x01 + + + DIV2 + Divide by 2 + 0x02 + + + DIV4 + Divide by 4 + 0x04 + + + DIV8 + Divide by 8 + 0x08 + + + DIV16 + Divide by 16 + 0x10 + + + DIV32 + Divide by 32 + 0x20 + + + DIV64 + Divide by 64 + 0x40 + + + DIV128 + Divide by 128 + 0x80 + + + + + + + AHBMASK + AHB Mask + 0x10 + 32 + 0x00001CFF + + + HPB0_ + HPB0 AHB Clock Mask + 0 + 1 + + + HPB1_ + HPB1 AHB Clock Mask + 1 + 1 + + + HPB2_ + HPB2 AHB Clock Mask + 2 + 1 + + + DSU_ + DSU AHB Clock Mask + 3 + 1 + + + HMATRIXHS_ + HMATRIXHS AHB Clock Mask + 4 + 1 + + + NVMCTRL_ + NVMCTRL AHB Clock Mask + 5 + 1 + + + HSRAM_ + HSRAM AHB Clock Mask + 6 + 1 + + + DMAC_ + DMAC AHB Clock Mask + 7 + 1 + + + CAN0_ + CAN0 AHB Clock Mask + 8 + 1 + + + CAN1_ + CAN1 AHB Clock Mask + 9 + 1 + + + PAC_ + PAC AHB Clock Mask + 10 + 1 + + + NVMCTRL_PICACHU_ + NVMCTRL_PICACHU AHB Clock Mask + 11 + 1 + + + DIVAS_ + DIVAS AHB Clock Mask + 12 + 1 + + + + + APBAMASK + APBA Mask + 0x14 + 32 + 0x00000FFF + + + PAC_ + PAC APB Clock Enable + 0 + 1 + + + PM_ + PM APB Clock Enable + 1 + 1 + + + MCLK_ + MCLK APB Clock Enable + 2 + 1 + + + RSTC_ + RSTC APB Clock Enable + 3 + 1 + + + OSCCTRL_ + OSCCTRL APB Clock Enable + 4 + 1 + + + OSC32KCTRL_ + OSC32KCTRL APB Clock Enable + 5 + 1 + + + SUPC_ + SUPC APB Clock Enable + 6 + 1 + + + GCLK_ + GCLK APB Clock Enable + 7 + 1 + + + WDT_ + WDT APB Clock Enable + 8 + 1 + + + RTC_ + RTC APB Clock Enable + 9 + 1 + + + EIC_ + EIC APB Clock Enable + 10 + 1 + + + FREQM_ + FREQM APB Clock Enable + 11 + 1 + + + TSENS_ + TSENS APB Clock Enable + 12 + 1 + + + + + APBBMASK + APBB Mask + 0x18 + 32 + 0x00000007 + + + PORT_ + PORT APB Clock Enable + 0 + 1 + + + DSU_ + DSU APB Clock Enable + 1 + 1 + + + NVMCTRL_ + NVMCTRL APB Clock Enable + 2 + 1 + + + HMATRIXHS_ + HMATRIXHS APB Clock Enable + 5 + 1 + + + + + APBCMASK + APBC Mask + 0x1C + 32 + 0x00000000 + + + EVSYS_ + EVSYS APB Clock Enable + 0 + 1 + + + SERCOM0_ + SERCOM0 APB Clock Enable + 1 + 1 + + + SERCOM1_ + SERCOM1 APB Clock Enable + 2 + 1 + + + SERCOM2_ + SERCOM2 APB Clock Enable + 3 + 1 + + + SERCOM3_ + SERCOM3 APB Clock Enable + 4 + 1 + + + SERCOM4_ + SERCOM4 APB Clock Enable + 5 + 1 + + + SERCOM5_ + SERCOM5 APB Clock Enable + 6 + 1 + + + TCC0_ + TCC0 APB Clock Enable + 9 + 1 + + + TCC1_ + TCC1 APB Clock Enable + 10 + 1 + + + TCC2_ + TCC2 APB Clock Enable + 11 + 1 + + + TC0_ + TC0 APB Clock Enable + 12 + 1 + + + TC1_ + TC1 APB Clock Enable + 13 + 1 + + + TC2_ + TC2 APB Clock Enable + 14 + 1 + + + TC3_ + TC3 APB Clock Enable + 15 + 1 + + + TC4_ + TC4 APB Clock Enable + 16 + 1 + + + ADC0_ + ADC0 APB Clock Enable + 17 + 1 + + + ADC1_ + ADC1 APB Clock Enable + 18 + 1 + + + SDADC_ + SDADC APB Clock Enable + 19 + 1 + + + AC_ + AC APB Clock Enable + 20 + 1 + + + DAC_ + DAC APB Clock Enable + 21 + 1 + + + PTC_ + PTC APB Clock Enable + 22 + 1 + + + CCL_ + CCL APB Clock Enable + 23 + 1 + + + + + + + MTB + U20021.0.0 + Cortex-M0+ Micro-Trace Buffer + MTB + MTB_ + 0x41008000 + + 0 + 0x1000 + registers + + + + POSITION + MTB Position + 0x0 + 32 + + + WRAP + Pointer Value Wraps + 2 + 1 + + + POINTER + Trace Packet Location Pointer + 3 + 29 + + + + + MASTER + MTB Master + 0x4 + 32 + 0x00000000 + + + MASK + Maximum Value of the Trace Buffer in SRAM + 0 + 5 + + + TSTARTEN + Trace Start Input Enable + 5 + 1 + + + TSTOPEN + Trace Stop Input Enable + 6 + 1 + + + SFRWPRIV + Special Function Register Write Privilege + 7 + 1 + + + RAMPRIV + SRAM Privilege + 8 + 1 + + + HALTREQ + Halt Request + 9 + 1 + + + EN + Main Trace Enable + 31 + 1 + + + + + FLOW + MTB Flow + 0x8 + 32 + 0x00000000 + + + AUTOSTOP + Auto Stop Tracing + 0 + 1 + + + AUTOHALT + Auto Halt Request + 1 + 1 + + + WATERMARK + Watermark value + 3 + 29 + + + + + BASE + MTB Base + 0xC + 32 + read-only + + + ITCTRL + MTB Integration Mode Control + 0xF00 + 32 + + + CLAIMSET + MTB Claim Set + 0xFA0 + 32 + + + CLAIMCLR + MTB Claim Clear + 0xFA4 + 32 + + + LOCKACCESS + MTB Lock Access + 0xFB0 + 32 + + + LOCKSTATUS + MTB Lock Status + 0xFB4 + 32 + read-only + + + AUTHSTATUS + MTB Authentication Status + 0xFB8 + 32 + read-only + + + DEVARCH + MTB Device Architecture + 0xFBC + 32 + read-only + + + DEVID + MTB Device Configuration + 0xFC8 + 32 + read-only + + + DEVTYPE + MTB Device Type + 0xFCC + 32 + read-only + + + PID4 + Peripheral Identification 4 + 0xFD0 + 32 + read-only + + + PID5 + Peripheral Identification 5 + 0xFD4 + 32 + read-only + + + PID6 + Peripheral Identification 6 + 0xFD8 + 32 + read-only + + + PID7 + Peripheral Identification 7 + 0xFDC + 32 + read-only + + + PID0 + Peripheral Identification 0 + 0xFE0 + 32 + read-only + + + PID1 + Peripheral Identification 1 + 0xFE4 + 32 + read-only + + + PID2 + Peripheral Identification 2 + 0xFE8 + 32 + read-only + + + PID3 + Peripheral Identification 3 + 0xFEC + 32 + read-only + + + CID0 + Component Identification 0 + 0xFF0 + 32 + read-only + + + CID1 + Component Identification 1 + 0xFF4 + 32 + read-only + + + CID2 + Component Identification 2 + 0xFF8 + 32 + read-only + + + CID3 + Component Identification 3 + 0xFFC + 32 + read-only + + + + + NVMCTRL + U22074.0.1.1 + Non-Volatile Memory Controller + NVMCTRL + NVMCTRL_ + 0x41004000 + + 0 + 0x30 + registers + + + NVMCTRL + 6 + + + + CTRLA + Control A + 0x0 + 16 + 0x0000 + + + CMD + Command + 0 + 7 + + CMDSelect + + ER + Erase Row - Erases the row addressed by the ADDR register. + 0x02 + + + WP + Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. + 0x04 + + + EAR + Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. + 0x05 + + + WAP + Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. + 0x06 + + + SF + Security Flow Command + 0x0A + + + WL + Write lockbits + 0x0F + + + RWWEEER + RWW EEPROM area Erase Row - Erases the row addressed by the ADDR register. + 0x1A + + + RWWEEWP + RWW EEPROM Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. + 0x1C + + + LR + Lock Region - Locks the region containing the address location in the ADDR register. + 0x40 + + + UR + Unlock Region - Unlocks the region containing the address location in the ADDR register. + 0x41 + + + SPRM + Sets the power reduction mode. + 0x42 + + + CPRM + Clears the power reduction mode. + 0x43 + + + PBC + Page Buffer Clear - Clears the page buffer. + 0x44 + + + SSB + Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row. + 0x45 + + + INVALL + Invalidate all cache lines. + 0x46 + + + + + CMDEX + Command Execution + 8 + 8 + + CMDEXSelect + + KEY + Execution Key + 0xA5 + + + + + + + CTRLB + Control B + 0x4 + 32 + 0x00000080 + + + RWS + NVM Read Wait States + 1 + 4 + + RWSSelect + + SINGLE + Single Auto Wait State + 0 + + + HALF + Half Auto Wait State + 1 + + + DUAL + Dual Auto Wait State + 2 + + + + + MANW + Manual Write + 7 + 1 + + + SLEEPPRM + Power Reduction Mode during Sleep + 8 + 2 + + SLEEPPRMSelect + + WAKEONACCESS + NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access. + 0 + + + WAKEUPINSTANT + NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep. + 1 + + + DISABLED + Auto power reduction disabled. + 3 + + + + + READMODE + NVMCTRL Read Mode + 16 + 2 + + READMODESelect + + NO_MISS_PENALTY + The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance. + 0x0 + + + LOW_POWER + Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time. + 0x1 + + + DETERMINISTIC + The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings. + 0x2 + + + + + CACHEDIS + Cache Disable + 18 + 2 + + + + + PARAM + NVM Parameter + 0x8 + 32 + 0x00000000 + + + NVMP + NVM Pages + 0 + 16 + + + PSZ + Page Size + 16 + 3 + + PSZSelect + + 8 + 8 bytes + 0x0 + + + 16 + 16 bytes + 0x1 + + + 32 + 32 bytes + 0x2 + + + 64 + 64 bytes + 0x3 + + + 128 + 128 bytes + 0x4 + + + 256 + 256 bytes + 0x5 + + + 512 + 512 bytes + 0x6 + + + 1024 + 1024 bytes + 0x7 + + + + + RWWEEP + RWW EEPROM Pages + 20 + 12 + + + + + INTENCLR + Interrupt Enable Clear + 0xC + 8 + 0x00 + + + READY + NVM Ready Interrupt Enable + 0 + 1 + + + ERROR + Error Interrupt Enable + 1 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x10 + 8 + 0x00 + + + READY + NVM Ready Interrupt Enable + 0 + 1 + + + ERROR + Error Interrupt Enable + 1 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x14 + 8 + 0x00 + + + READY + NVM Ready + 0 + 1 + + + ERROR + Error + 1 + 1 + + + + + STATUS + Status + 0x18 + 16 + 0x0000 + + + PRM + Power Reduction Mode + 0 + 1 + + + LOAD + NVM Page Buffer Active Loading + 1 + 1 + + + PROGE + Programming Error Status + 2 + 1 + + + LOCKE + Lock Error Status + 3 + 1 + + + NVME + NVM Error + 4 + 1 + + + SB + Security Bit Status + 8 + 1 + + + + + ADDR + Address + 0x1C + 32 + 0x00000000 + + + ADDR + NVM Address + 0 + 22 + + + + + LOCK + Lock Section + 0x20 + 16 + 0x0000 + + + LOCK + Region Lock Bits + 0 + 16 + + + + + PBLDATA0 + Page Buffer Load Data 0 + 0x28 + 32 + read-only + 0x00000000 + + + PBLDATA1 + Page Buffer Load Data 1 + 0x2C + 32 + read-only + 0x00000000 + + + + + OSCCTRL + U21192.1.0 + Oscillators Control + OSCCTRL + OSCCTRL_ + 0x40001000 + + 0 + 0x3C + registers + + + + INTENCLR + Interrupt Enable Clear + 0x0 + 32 + 0x00000000 + + + XOSCRDY + XOSC Ready Interrupt Enable + 0 + 1 + + + XOSCFAIL + XOSC Clock Failure Detector Interrupt Enable + 1 + 1 + + + OSC48MRDY + OSC48M Ready Interrupt Enable + 4 + 1 + + + DPLLLCKR + DPLL Lock Rise Interrupt Enable + 8 + 1 + + + DPLLLCKF + DPLL Lock Fall Interrupt Enable + 9 + 1 + + + DPLLLTO + DPLL Time Out Interrupt Enable + 10 + 1 + + + DPLLLDRTO + DPLL Ratio Ready Interrupt Enable + 11 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x4 + 32 + 0x00000000 + + + XOSCRDY + XOSC Ready Interrupt Enable + 0 + 1 + + + XOSCFAIL + XOSC Clock Failure Detector Interrupt Enable + 1 + 1 + + + OSC48MRDY + OSC48M Ready Interrupt Enable + 4 + 1 + + + DPLLLCKR + DPLL Lock Rise Interrupt Enable + 8 + 1 + + + DPLLLCKF + DPLL Lock Fall Interrupt Enable + 9 + 1 + + + DPLLLTO + DPLL Time Out Interrupt Enable + 10 + 1 + + + DPLLLDRTO + DPLL Ratio Ready Interrupt Enable + 11 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x8 + 32 + 0x00000000 + + + XOSCRDY + XOSC Ready + 0 + 1 + + + XOSCFAIL + XOSC Clock Failure Detector + 1 + 1 + + + OSC48MRDY + OSC48M Ready + 4 + 1 + + + DPLLLCKR + DPLL Lock Rise + 8 + 1 + + + DPLLLCKF + DPLL Lock Fall + 9 + 1 + + + DPLLLTO + DPLL Timeout + 10 + 1 + + + DPLLLDRTO + DPLL Ratio Ready + 11 + 1 + + + + + STATUS + Power and Clocks Status + 0xC + 32 + read-only + 0x00000000 + + + XOSCRDY + XOSC Ready + 0 + 1 + + + XOSCFAIL + XOSC Clock Failure Detector + 1 + 1 + + + XOSCCKSW + XOSC Clock Switch + 2 + 1 + + + OSC48MRDY + OSC48M Ready + 4 + 1 + + + DPLLLCKR + DPLL Lock Rise + 8 + 1 + + + DPLLLCKF + DPLL Lock Fall + 9 + 1 + + + DPLLTO + DPLL Timeout + 10 + 1 + + + DPLLLDRTO + DPLL Ratio Ready + 11 + 1 + + + + + XOSCCTRL + External Multipurpose Crystal Oscillator (XOSC) Control + 0x10 + 16 + 0x0080 + + + ENABLE + Oscillator Enable + 1 + 1 + + + XTALEN + Crystal Oscillator Enable + 2 + 1 + + + CFDEN + Xosc Clock Failure Detector Enable + 3 + 1 + + + SWBEN + Xosc Clock Switch Enable + 4 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + GAIN + Oscillator Gain + 8 + 3 + + GAINSelect + + GAIN2 + 2 MHz + 0 + + + GAIN4 + 4 MHz + 1 + + + GAIN8 + 8 MHz + 2 + + + GAIN16 + 16 MHz + 3 + + + GAIN30 + 30 MHz + 4 + + + + + AMPGC + Automatic Amplitude Gain Control + 11 + 1 + + + STARTUP + Start-Up Time + 12 + 4 + + STARTUPSelect + + CYCLE1 + 31 us + 0 + + + CYCLE2 + 61 us + 1 + + + CYCLE4 + 122 us + 2 + + + CYCLE8 + 244 us + 3 + + + CYCLE16 + 488 us + 4 + + + CYCLE32 + 977 us + 5 + + + CYCLE64 + 1953 us + 6 + + + CYCLE128 + 3906 us + 7 + + + CYCLE256 + 7813 us + 8 + + + CYCLE512 + 15625 us + 9 + + + CYCLE1024 + 31250 us + 10 + + + CYCLE2048 + 62500 us + 11 + + + CYCLE4096 + 125000 us + 12 + + + CYCLE8192 + 250000 us + 13 + + + CYCLE16384 + 500000 us + 14 + + + CYCLE32768 + 1000000 us + 15 + + + + + + + CFDPRESC + Clock Failure Detector Prescaler + 0x12 + 8 + 0x00 + + + CFDPRESC + Clock Failure Detector Prescaler + 0 + 3 + + CFDPRESCSelect + + DIV1 + 48 MHz + 0 + + + DIV2 + 24 MHz + 1 + + + DIV4 + 12 MHz + 2 + + + DIV8 + 6 MHz + 3 + + + DIV16 + 3 MHz + 4 + + + DIV32 + 1.5 MHz + 5 + + + DIV64 + 0.75 MHz + 6 + + + DIV128 + 0.3125 MHz + 7 + + + + + + + EVCTRL + Event Control + 0x13 + 8 + 0x00 + + + CFDEO + Clock Failure Detector Event Output Enable + 0 + 1 + + + + + OSC48MCTRL + 48MHz Internal Oscillator (OSC48M) Control + 0x14 + 8 + 0x82 + + + ENABLE + Oscillator Enable + 1 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + + + OSC48MDIV + OSC48M Divider + 0x15 + 8 + 0x0B + + + DIV + OSC48M Division Factor + 0 + 4 + + DIVSelect + + DIV1 + 48 MHz + 0 + + + DIV2 + 24 MHz + 1 + + + DIV3 + 16 MHz + 2 + + + DIV4 + 12 MHz + 3 + + + DIV5 + 9.6 MHz + 4 + + + DIV6 + 8 MHz + 5 + + + DIV7 + 6.86 MHz + 6 + + + DIV8 + 6 MHz + 7 + + + DIV9 + 5.33 MHz + 8 + + + DIV10 + 4.8 MHz + 9 + + + DIV11 + 4.36 MHz + 10 + + + DIV12 + 4 MHz + 11 + + + DIV13 + 3.69 MHz + 12 + + + DIV14 + 3.43 MHz + 13 + + + DIV15 + 3.2 MHz + 14 + + + DIV16 + 3 MHz + 15 + + + + + + + OSC48MSTUP + OSC48M Startup Time + 0x16 + 8 + 0x07 + + + STARTUP + Startup Time + 0 + 3 + + STARTUPSelect + + CYCLE8 + 166 ns + 0 + + + CYCLE16 + 333 ns + 1 + + + CYCLE32 + 667 ns + 2 + + + CYCLE64 + 1.333 us + 3 + + + CYCLE128 + 2.667 us + 4 + + + CYCLE256 + 5.333 us + 5 + + + CYCLE512 + 10.667 us + 6 + + + CYCLE1024 + 21.333 us + 7 + + + + + + + OSC48MSYNCBUSY + OSC48M Synchronization Busy + 0x18 + 32 + read-only + 0x00000000 + + + OSC48MDIV + OSC48MDIV Synchronization Status + 2 + 1 + + + + + DPLLCTRLA + DPLL Control + 0x1C + 8 + 0x80 + + + ENABLE + Enable + 1 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand + 7 + 1 + + + + + DPLLRATIO + DPLL Ratio Control + 0x20 + 32 + 0x00000000 + + + LDR + Loop Divider Ratio + 0 + 12 + + + LDRFRAC + Loop Divider Ratio Fractional Part + 16 + 4 + + + + + DPLLCTRLB + Digital Core Configuration + 0x24 + 32 + 0x00000000 + + + FILTER + Proportional Integral Filter Selection + 0 + 2 + + FILTERSelect + + DEFAULT + Default filter mode + 0 + + + LBFILT + Low bandwidth filter + 1 + + + HBFILT + High bandwidth filter + 2 + + + HDFILT + High damping filter + 3 + + + + + LPEN + Low-Power Enable + 2 + 1 + + + WUF + Wake Up Fast + 3 + 1 + + + REFCLK + Reference Clock Selection + 4 + 2 + + REFCLKSelect + + XOSC32K + XOSC32K clock reference + 0 + + + XOSC + XOSC clock reference + 1 + + + GCLK + GCLK clock reference + 2 + + + + + LTIME + Lock Time + 8 + 3 + + LTIMESelect + + DEFAULT + No time-out. Automatic lock. + 0 + + + 8MS + Time-out if no lock within 8ms + 4 + + + 9MS + Time-out if no lock within 9ms + 5 + + + 10MS + Time-out if no lock within 10ms + 6 + + + 11MS + Time-out if no lock within 11ms + 7 + + + + + LBYPASS + Lock Bypass + 12 + 1 + + + DIV + Clock Divider + 16 + 11 + + + + + DPLLPRESC + DPLL Prescaler + 0x28 + 8 + 0x00 + + + PRESC + Output Clock Prescaler + 0 + 2 + + PRESCSelect + + DIV1 + DPLL output is divided by 1 + 0 + + + DIV2 + DPLL output is divided by 2 + 1 + + + DIV4 + DPLL output is divided by 4 + 2 + + + + + + + DPLLSYNCBUSY + DPLL Synchronization Busy + 0x2C + 8 + read-only + 0x00 + + + ENABLE + DPLL Enable Synchronization Status + 1 + 1 + + + DPLLRATIO + DPLL Ratio Synchronization Status + 2 + 1 + + + DPLLPRESC + DPLL Prescaler Synchronization Status + 3 + 1 + + + + + DPLLSTATUS + DPLL Status + 0x30 + 8 + read-only + 0x00 + + + LOCK + DPLL Lock Status + 0 + 1 + + + CLKRDY + DPLL Clock Ready + 1 + 1 + + + + + CAL48M + 48MHz Oscillator Calibration + 0x38 + 32 + 0x00000000 + + + FCAL + Frequency Calibration (48MHz) + 0 + 6 + + + FRANGE + Frequency Range (48MHz) + 8 + 2 + + + TCAL + Temperature Calibration (48MHz) + 16 + 6 + + + + + + + OSC32KCTRL + U22462.1.0 + 32k Oscillators Control + OSC32KCTRL + OSC32KCTRL_ + 0x40001400 + + 0 + 0x20 + registers + + + + INTENCLR + Interrupt Enable Clear + 0x0 + 32 + 0x00000000 + + + XOSC32KRDY + XOSC32K Ready Interrupt Enable + 0 + 1 + + + OSC32KRDY + OSC32K Ready Interrupt Enable + 1 + 1 + + + CLKFAIL + XOSC32K Clock Failure Detector Interrupt Enable + 2 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x4 + 32 + 0x00000000 + + + XOSC32KRDY + XOSC32K Ready Interrupt Enable + 0 + 1 + + + OSC32KRDY + OSC32K Ready Interrupt Enable + 1 + 1 + + + CLKFAIL + XOSC32K Clock Failure Detector Interrupt Enable + 2 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x8 + 32 + 0x00000000 + + + XOSC32KRDY + XOSC32K Ready + 0 + 1 + + + OSC32KRDY + OSC32K Ready + 1 + 1 + + + CLKFAIL + XOSC32K Clock Failure Detector + 2 + 1 + + + + + STATUS + Power and Clocks Status + 0xC + 32 + read-only + 0x00000000 + + + XOSC32KRDY + XOSC32K Ready + 0 + 1 + + + OSC32KRDY + OSC32K Ready + 1 + 1 + + + CLKFAIL + XOSC32K Clock Failure Detector + 2 + 1 + + + CLKSW + XOSC32K Clock switch + 3 + 1 + + + + + RTCCTRL + Clock selection + 0x10 + 32 + 0x00000000 + + + RTCSEL + RTC Clock Selection + 0 + 3 + + RTCSELSelect + + ULP1K + 1.024kHz from 32kHz internal ULP oscillator + 0 + + + ULP32K + 32.768kHz from 32kHz internal ULP oscillator + 1 + + + OSC1K + 1.024kHz from 32.768kHz internal oscillator + 2 + + + OSC32K + 32.768kHz from 32.768kHz internal oscillator + 3 + + + XOSC1K + 1.024kHz from 32.768kHz internal oscillator + 4 + + + XOSC32K + 32.768kHz from 32.768kHz external crystal oscillator + 5 + + + + + + + XOSC32K + 32kHz External Crystal Oscillator (XOSC32K) Control + 0x14 + 16 + 0x0080 + + + ENABLE + Oscillator Enable + 1 + 1 + + + XTALEN + Crystal Oscillator Enable + 2 + 1 + + + EN32K + 32kHz Output Enable + 3 + 1 + + + EN1K + 1kHz Output Enable + 4 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + STARTUP + Oscillator Start-Up Time + 8 + 3 + + STARTUPSelect + + CYCLE1 + 0.122 ms + 0 + + + CYCLE32 + 1.068 ms + 1 + + + CYCLE2048 + 62.6 ms + 2 + + + CYCLE4096 + 125 ms + 3 + + + CYCLE16384 + 500 ms + 4 + + + CYCLE32768 + 1000 ms + 5 + + + CYCLE65536 + 2000 ms + 6 + + + CYCLE131072 + 4000 ms + 7 + + + + + WRTLOCK + Write Lock + 12 + 1 + + + + + CFDCTRL + Clock Failure Detector Control + 0x16 + 8 + 0x00 + + + CFDEN + Clock Failure Detector Enable + 0 + 1 + + + SWBACK + Clock Switch Back + 1 + 1 + + + CFDPRESC + Clock Failure Detector Prescaler + 2 + 1 + + + + + EVCTRL + Event Control + 0x17 + 8 + 0x00 + + + CFDEO + Clock Failure Detector Event Output Enable + 0 + 1 + + + + + OSC32K + 32kHz Internal Oscillator (OSC32K) Control + 0x18 + 32 + 0x003F0080 + + + ENABLE + Oscillator Enable + 1 + 1 + + + EN32K + 32kHz Output Enable + 2 + 1 + + + EN1K + 1kHz Output Enable + 3 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + STARTUP + Oscillator Start-Up Time + 8 + 3 + + STARTUPSelect + + CYCLE3 + 0.092 ms + 0 + + + CYCLE4 + 0.122 ms + 1 + + + CYCLE6 + 0.183 ms + 2 + + + CYCLE10 + 0.305 ms + 3 + + + CYCLE18 + 0.549 ms + 4 + + + CYCLE34 + 1.038 ms + 5 + + + CYCLE66 + 2.014 ms + 6 + + + CYCLE130 + 3.967 ms + 7 + + + + + WRTLOCK + Write Lock + 12 + 1 + + + CALIB + Oscillator Calibration + 16 + 7 + + + + + OSCULP32K + 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control + 0x1C + 32 + + + CALIB + Oscillator Calibration + 8 + 5 + + + WRTLOCK + Write Lock + 15 + 1 + + + + + + + PAC + U21201.1.0 + Peripheral Access Controller + PAC + PAC_ + 0x40000000 + + 0 + 0x40 + registers + + + + WRCTRL + Write control + 0x0 + 32 + 0x00000000 + + + PERID + Peripheral identifier + 0 + 16 + + + KEY + Peripheral access control key + 16 + 8 + + KEYSelect + + OFF + No action + 0 + + + CLR + Clear protection + 1 + + + SET + Set protection + 2 + + + SETLCK + Set and lock protection + 3 + + + + + + + EVCTRL + Event control + 0x4 + 8 + 0x00 + + + ERREO + Peripheral acess error event output + 0 + 1 + + + + + INTENCLR + Interrupt enable clear + 0x8 + 8 + 0x00 + + + ERR + Peripheral access error interrupt disable + 0 + 1 + + + + + INTENSET + Interrupt enable set + 0x9 + 8 + 0x00 + + + ERR + Peripheral access error interrupt enable + 0 + 1 + + + + + INTFLAGAHB + Bridge interrupt flag status + 0x10 + 32 + 0x00000000 + + + FLASH_ + FLASH + 0 + 1 + + + HSRAMCM0P_ + HSRAMCM0P + 1 + 1 + + + HSRAMDSU_ + HSRAMDSU + 2 + 1 + + + HPB1_ + HPB1 + 3 + 1 + + + HPB0_ + HPB0 + 4 + 1 + + + HPB2_ + HPB2 + 5 + 1 + + + LPRAMDMAC_ + LPRAMDMAC + 6 + 1 + + + DIVAS_ + DIVAS + 7 + 1 + + + + + INTFLAGA + Peripheral interrupt flag status - Bridge A + 0x14 + 32 + 0x00000000 + + + PAC_ + PAC + 0 + 1 + + + PM_ + PM + 1 + 1 + + + MCLK_ + MCLK + 2 + 1 + + + RSTC_ + RSTC + 3 + 1 + + + OSCCTRL_ + OSCCTRL + 4 + 1 + + + OSC32KCTRL_ + OSC32KCTRL + 5 + 1 + + + SUPC_ + SUPC + 6 + 1 + + + GCLK_ + GCLK + 7 + 1 + + + WDT_ + WDT + 8 + 1 + + + RTC_ + RTC + 9 + 1 + + + EIC_ + EIC + 10 + 1 + + + FREQM_ + FREQM + 11 + 1 + + + TSENS_ + TSENS + 12 + 1 + + + + + INTFLAGB + Peripheral interrupt flag status - Bridge B + 0x18 + 32 + 0x00000000 + + + PORT_ + PORT + 0 + 1 + + + DSU_ + DSU + 1 + 1 + + + NVMCTRL_ + NVMCTRL + 2 + 1 + + + DMAC_ + DMAC + 3 + 1 + + + MTB_ + MTB + 4 + 1 + + + HMATRIXHS_ + HMATRIXHS + 5 + 1 + + + + + INTFLAGC + Peripheral interrupt flag status - Bridge C + 0x1C + 32 + 0x00000000 + + + EVSYS_ + EVSYS + 0 + 1 + + + SERCOM0_ + SERCOM0 + 1 + 1 + + + SERCOM1_ + SERCOM1 + 2 + 1 + + + SERCOM2_ + SERCOM2 + 3 + 1 + + + SERCOM3_ + SERCOM3 + 4 + 1 + + + SERCOM4_ + SERCOM4 + 5 + 1 + + + SERCOM5_ + SERCOM5 + 6 + 1 + + + CAN0_ + CAN0 + 7 + 1 + + + CAN1_ + CAN1 + 8 + 1 + + + TCC0_ + TCC0 + 9 + 1 + + + TCC1_ + TCC1 + 10 + 1 + + + TCC2_ + TCC2 + 11 + 1 + + + TC0_ + TC0 + 12 + 1 + + + TC1_ + TC1 + 13 + 1 + + + TC2_ + TC2 + 14 + 1 + + + TC3_ + TC3 + 15 + 1 + + + TC4_ + TC4 + 16 + 1 + + + ADC0_ + ADC0 + 17 + 1 + + + ADC1_ + ADC1 + 18 + 1 + + + SDADC_ + SDADC + 19 + 1 + + + AC_ + AC + 20 + 1 + + + DAC_ + DAC + 21 + 1 + + + PTC_ + PTC + 22 + 1 + + + CCL_ + CCL + 23 + 1 + + + + + STATUSA + Peripheral write protection status - Bridge A + 0x34 + 32 + read-only + 0x00000000 + + + PAC_ + PAC APB Protect Enable + 0 + 1 + + + PM_ + PM APB Protect Enable + 1 + 1 + + + MCLK_ + MCLK APB Protect Enable + 2 + 1 + + + RSTC_ + RSTC APB Protect Enable + 3 + 1 + + + OSCCTRL_ + OSCCTRL APB Protect Enable + 4 + 1 + + + OSC32KCTRL_ + OSC32KCTRL APB Protect Enable + 5 + 1 + + + SUPC_ + SUPC APB Protect Enable + 6 + 1 + + + GCLK_ + GCLK APB Protect Enable + 7 + 1 + + + WDT_ + WDT APB Protect Enable + 8 + 1 + + + RTC_ + RTC APB Protect Enable + 9 + 1 + + + EIC_ + EIC APB Protect Enable + 10 + 1 + + + FREQM_ + FREQM APB Protect Enable + 11 + 1 + + + TSENS_ + TSENS APB Protect Enable + 12 + 1 + + + + + STATUSB + Peripheral write protection status - Bridge B + 0x38 + 32 + read-only + 0x00000002 + + + PORT_ + PORT APB Protect Enable + 0 + 1 + + + DSU_ + DSU APB Protect Enable + 1 + 1 + + + NVMCTRL_ + NVMCTRL APB Protect Enable + 2 + 1 + + + DMAC_ + DMAC APB Protect Enable + 3 + 1 + + + MTB_ + MTB APB Protect Enable + 4 + 1 + + + HMATRIXHS_ + HMATRIXHS APB Protect Enable + 5 + 1 + + + + + STATUSC + Peripheral write protection status - Bridge C + 0x3C + 32 + read-only + 0x02000000 + + + EVSYS_ + EVSYS APB Protect Enable + 0 + 1 + + + SERCOM0_ + SERCOM0 APB Protect Enable + 1 + 1 + + + SERCOM1_ + SERCOM1 APB Protect Enable + 2 + 1 + + + SERCOM2_ + SERCOM2 APB Protect Enable + 3 + 1 + + + SERCOM3_ + SERCOM3 APB Protect Enable + 4 + 1 + + + SERCOM4_ + SERCOM4 APB Protect Enable + 5 + 1 + + + SERCOM5_ + SERCOM5 APB Protect Enable + 6 + 1 + + + CAN0_ + CAN0 APB Protect Enable + 7 + 1 + + + CAN1_ + CAN1 APB Protect Enable + 8 + 1 + + + TCC0_ + TCC0 APB Protect Enable + 9 + 1 + + + TCC1_ + TCC1 APB Protect Enable + 10 + 1 + + + TCC2_ + TCC2 APB Protect Enable + 11 + 1 + + + TC0_ + TC0 APB Protect Enable + 12 + 1 + + + TC1_ + TC1 APB Protect Enable + 13 + 1 + + + TC2_ + TC2 APB Protect Enable + 14 + 1 + + + TC3_ + TC3 APB Protect Enable + 15 + 1 + + + TC4_ + TC4 APB Protect Enable + 16 + 1 + + + ADC0_ + ADC0 APB Protect Enable + 17 + 1 + + + ADC1_ + ADC1 APB Protect Enable + 18 + 1 + + + SDADC_ + SDADC APB Protect Enable + 19 + 1 + + + AC_ + AC APB Protect Enable + 20 + 1 + + + DAC_ + DAC APB Protect Enable + 21 + 1 + + + PTC_ + PTC APB Protect Enable + 22 + 1 + + + CCL_ + CCL APB Protect Enable + 23 + 1 + + + + + + + PM + U22402.1.0 + Power Manager + PM + PM_ + 0x40000400 + + 0 + 0xA + registers + + + + SLEEPCFG + Sleep Configuration + 0x1 + 8 + 0x00 + + + SLEEPMODE + Sleep Mode + 0 + 3 + + SLEEPMODESelect + + IDLE0 + CPU clock is OFF + 0 + + + IDLE1 + AHB clock is OFF + 1 + + + IDLE2 + APB clock are OFF + 2 + + + STANDBY + All Clocks are OFF + 4 + + + + + + + STDBYCFG + Standby Configuration + 0x8 + 16 + 0x0400 + + + VREGSMOD + Voltage Regulator Standby mode + 6 + 2 + + VREGSMODSelect + + AUTO + Automatic mode + 0 + + + PERFORMANCE + Performance oriented + 1 + + + LP + Low Power oriented + 2 + + + + + BBIASHS + Back Bias for HMCRAMCHS + 10 + 1 + + + + + + + PORT + U22102.1.1 + Port Module + PORT + PORT_ + 0x41000000 + + 0 + 0x100 + registers + + + + 2 + 0x80 + GROUP[%s] + + 0x00 + + DIR + Data Direction + 0x0 + 32 + 0x00000000 + + + DIRCLR + Data Direction Clear + 0x4 + 32 + 0x00000000 + + + DIRSET + Data Direction Set + 0x8 + 32 + 0x00000000 + + + DIRTGL + Data Direction Toggle + 0xC + 32 + 0x00000000 + + + OUT + Data Output Value + 0x10 + 32 + 0x00000000 + + + OUTCLR + Data Output Value Clear + 0x14 + 32 + 0x00000000 + + + OUTSET + Data Output Value Set + 0x18 + 32 + 0x00000000 + + + OUTTGL + Data Output Value Toggle + 0x1C + 32 + 0x00000000 + + + IN + Data Input Value + 0x20 + 32 + read-only + 0x00000000 + + + CTRL + Control + 0x24 + 32 + 0x00000000 + + + SAMPLING + Input Sampling Mode + 0 + 32 + + + + + WRCONFIG + Write Configuration + 0x28 + 32 + write-only + 0x00000000 + + + PINMASK + Pin Mask for Multiple Pin Configuration + 0 + 16 + + + PMUXEN + Select Peripheral Multiplexer + 16 + 1 + + + INEN + Input Enable + 17 + 1 + + + PULLEN + Pull Enable + 18 + 1 + + + DRVSTR + Output Driver Strength Selection + 22 + 1 + + + PMUX + Peripheral Multiplexing Template + 24 + 4 + + + WRPMUX + Write PMUX Registers + 28 + 1 + + + WRPINCFG + Write PINCFG Registers + 30 + 1 + + + HWSEL + Half-Word Select + 31 + 1 + + + + + EVCTRL + Event Input Control + 0x2C + 32 + 0x00000000 + + + PID0 + Port Event Pin Identifier 0 + 0 + 5 + + + EVACT0 + Port Event Action 0 + 5 + 2 + + EVACT0Select + + OUT + Event output to pin + 0x0 + + + SET + Set output register of pin on event + 0x1 + + + CLR + Clear output register of pin on event + 0x2 + + + TGL + Toggle output register of pin on event + 0x3 + + + + + PORTEI0 + Port Event Enable Input 0 + 7 + 1 + + + PID1 + Port Event Pin Identifier 1 + 8 + 5 + + + EVACT1 + Port Event Action 1 + 13 + 2 + + + PORTEI1 + Port Event Enable Input 1 + 15 + 1 + + + PID2 + Port Event Pin Identifier 2 + 16 + 5 + + + EVACT2 + Port Event Action 2 + 21 + 2 + + + PORTEI2 + Port Event Enable Input 2 + 23 + 1 + + + PID3 + Port Event Pin Identifier 3 + 24 + 5 + + + EVACT3 + Port Event Action 3 + 29 + 2 + + + PORTEI3 + Port Event Enable Input 3 + 31 + 1 + + + + + 16 + 1 + PMUX[%s] + Peripheral Multiplexing n + 0x30 + 8 + 0x00 + + + PMUXE + Peripheral Multiplexing for Even-Numbered Pin + 0 + 4 + + + PMUXO + Peripheral Multiplexing for Odd-Numbered Pin + 4 + 4 + + + + + 32 + 1 + PINCFG[%s] + Pin Configuration n + 0x40 + 8 + 0x00 + + + PMUXEN + Select Peripheral Multiplexer + 0 + 1 + + + INEN + Input Enable + 1 + 1 + + + PULLEN + Pull Enable + 2 + 1 + + + DRVSTR + Output Driver Strength Selection + 6 + 1 + + + + + + + + PORT_IOBUS + PORT_IOBUS_ + 0x60000000 + + + PTC + U22153.1.0 + Peripheral Touch Controller + PTC + PTC_ + 0x42005800 + + 0 + 0x1 + reserved + + + PTC + 30 + + + + RSTC + U22392.0.2 + Reset Controller + RSTC + RSTC_ + 0x40000C00 + + 0 + 0x1 + registers + + + + RCAUSE + Reset Cause + 0x0 + 8 + read-only + + + POR + Power On Reset + 0 + 1 + + + BODCORE + Brown Out CORE Detector Reset + 1 + 1 + + + BODVDD + Brown Out VDD Detector Reset + 2 + 1 + + + EXT + External Reset + 4 + 1 + + + WDT + Watchdog Reset + 5 + 1 + + + SYST + System Reset Request + 6 + 1 + + + + + + + RTC + U22501.1.1 + Real-Time Counter + RTC + RTC_ + 0x40002400 + + 0 + 0x25 + registers + + + RTC + 2 + + + + MODE0 + 32-bit Counter with Single 32-bit Compare + RtcMode0 + 0x0 + + CTRLA + MODE0 Control A + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 2 + + MODESelect + + COUNT32 + Mode 0: 32-bit Counter + 0x0 + + + COUNT16 + Mode 1: 16-bit Counter + 0x1 + + + CLOCK + Mode 2: Clock/Calendar + 0x2 + + + + + MATCHCLR + Clear on Match + 7 + 1 + + + PRESCALER + Prescaler + 8 + 4 + + PRESCALERSelect + + OFF + CLK_RTC_CNT = GCLK_RTC/1 + 0x0 + + + DIV1 + CLK_RTC_CNT = GCLK_RTC/1 + 0x1 + + + DIV2 + CLK_RTC_CNT = GCLK_RTC/2 + 0x2 + + + DIV4 + CLK_RTC_CNT = GCLK_RTC/4 + 0x3 + + + DIV8 + CLK_RTC_CNT = GCLK_RTC/8 + 0x4 + + + DIV16 + CLK_RTC_CNT = GCLK_RTC/16 + 0x5 + + + DIV32 + CLK_RTC_CNT = GCLK_RTC/32 + 0x6 + + + DIV64 + CLK_RTC_CNT = GCLK_RTC/64 + 0x7 + + + DIV128 + CLK_RTC_CNT = GCLK_RTC/128 + 0x8 + + + DIV256 + CLK_RTC_CNT = GCLK_RTC/256 + 0x9 + + + DIV512 + CLK_RTC_CNT = GCLK_RTC/512 + 0xA + + + DIV1024 + CLK_RTC_CNT = GCLK_RTC/1024 + 0xB + + + + + COUNTSYNC + Count Read Synchronization Enable + 15 + 1 + + + + + EVCTRL + MODE0 Event Control + 0x4 + 32 + 0x00000000 + + + PEREO0 + Periodic Interval 0 Event Output Enable + 0 + 1 + + + PEREO1 + Periodic Interval 1 Event Output Enable + 1 + 1 + + + PEREO2 + Periodic Interval 2 Event Output Enable + 2 + 1 + + + PEREO3 + Periodic Interval 3 Event Output Enable + 3 + 1 + + + PEREO4 + Periodic Interval 4 Event Output Enable + 4 + 1 + + + PEREO5 + Periodic Interval 5 Event Output Enable + 5 + 1 + + + PEREO6 + Periodic Interval 6 Event Output Enable + 6 + 1 + + + PEREO7 + Periodic Interval 7 Event Output Enable + 7 + 1 + + + CMPEO0 + Compare 0 Event Output Enable + 8 + 1 + + + OVFEO + Overflow Event Output Enable + 15 + 1 + + + + + INTENCLR + MODE0 Interrupt Enable Clear + 0x8 + 16 + 0x0000 + + + PER0 + Periodic Interval 0 Interrupt Enable + 0 + 1 + + + PER1 + Periodic Interval 1 Interrupt Enable + 1 + 1 + + + PER2 + Periodic Interval 2 Interrupt Enable + 2 + 1 + + + PER3 + Periodic Interval 3 Interrupt Enable + 3 + 1 + + + PER4 + Periodic Interval 4 Interrupt Enable + 4 + 1 + + + PER5 + Periodic Interval 5 Interrupt Enable + 5 + 1 + + + PER6 + Periodic Interval 6 Interrupt Enable + 6 + 1 + + + PER7 + Periodic Interval 7 Interrupt Enable + 7 + 1 + + + CMP0 + Compare 0 Interrupt Enable + 8 + 1 + + + OVF + Overflow Interrupt Enable + 15 + 1 + + + + + INTENSET + MODE0 Interrupt Enable Set + 0xA + 16 + 0x0000 + + + PER0 + Periodic Interval 0 Interrupt Enable + 0 + 1 + + + PER1 + Periodic Interval 1 Interrupt Enable + 1 + 1 + + + PER2 + Periodic Interval 2 Interrupt Enable + 2 + 1 + + + PER3 + Periodic Interval 3 Interrupt Enable + 3 + 1 + + + PER4 + Periodic Interval 4 Interrupt Enable + 4 + 1 + + + PER5 + Periodic Interval 5 Interrupt Enable + 5 + 1 + + + PER6 + Periodic Interval 6 Interrupt Enable + 6 + 1 + + + PER7 + Periodic Interval 7 Interrupt Enable + 7 + 1 + + + CMP0 + Compare 0 Interrupt Enable + 8 + 1 + + + OVF + Overflow Interrupt Enable + 15 + 1 + + + + + INTFLAG + MODE0 Interrupt Flag Status and Clear + 0xC + 16 + 0x0000 + + + PER0 + Periodic Interval 0 + 0 + 1 + + + PER1 + Periodic Interval 1 + 1 + 1 + + + PER2 + Periodic Interval 2 + 2 + 1 + + + PER3 + Periodic Interval 3 + 3 + 1 + + + PER4 + Periodic Interval 4 + 4 + 1 + + + PER5 + Periodic Interval 5 + 5 + 1 + + + PER6 + Periodic Interval 6 + 6 + 1 + + + PER7 + Periodic Interval 7 + 7 + 1 + + + CMP0 + Compare 0 + 8 + 1 + + + OVF + Overflow + 15 + 1 + + + + + DBGCTRL + Debug Control + 0xE + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + SYNCBUSY + MODE0 Synchronization Busy Status + 0x10 + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Busy + 0 + 1 + + + ENABLE + Enable Bit Busy + 1 + 1 + + + FREQCORR + FREQCORR Register Busy + 2 + 1 + + + COUNT + COUNT Register Busy + 3 + 1 + + + COMP0 + COMP 0 Register Busy + 5 + 1 + + + COUNTSYNC + Count Read Synchronization Enable Bit Busy + 15 + 1 + + + + + FREQCORR + Frequency Correction + 0x14 + 8 + 0x00 + + + VALUE + Correction Value + 0 + 7 + + + SIGN + Correction Sign + 7 + 1 + + + + + COUNT + MODE0 Counter Value + 0x18 + 32 + 0x00000000 + + + COUNT + Counter Value + 0 + 32 + + + + + COMP + MODE0 Compare n Value + 0x20 + 32 + 0x00000000 + + + COMP + Compare Value + 0 + 32 + + + + + + MODE1 + 16-bit Counter with Two 16-bit Compares + MODE0 + RtcMode1 + 0x0 + + CTRLA + MODE1 Control A + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 2 + + MODESelect + + COUNT32 + Mode 0: 32-bit Counter + 0 + + + COUNT16 + Mode 1: 16-bit Counter + 1 + + + CLOCK + Mode 2: Clock/Calendar + 2 + + + + + PRESCALER + Prescaler + 8 + 4 + + PRESCALERSelect + + OFF + CLK_RTC_CNT = GCLK_RTC/1 + 0 + + + DIV1 + CLK_RTC_CNT = GCLK_RTC/1 + 1 + + + DIV2 + CLK_RTC_CNT = GCLK_RTC/2 + 2 + + + DIV4 + CLK_RTC_CNT = GCLK_RTC/4 + 3 + + + DIV8 + CLK_RTC_CNT = GCLK_RTC/8 + 4 + + + DIV16 + CLK_RTC_CNT = GCLK_RTC/16 + 5 + + + DIV32 + CLK_RTC_CNT = GCLK_RTC/32 + 6 + + + DIV64 + CLK_RTC_CNT = GCLK_RTC/64 + 7 + + + DIV128 + CLK_RTC_CNT = GCLK_RTC/128 + 8 + + + DIV256 + CLK_RTC_CNT = GCLK_RTC/256 + 9 + + + DIV512 + CLK_RTC_CNT = GCLK_RTC/512 + 0xA + + + DIV1024 + CLK_RTC_CNT = GCLK_RTC/1024 + 0xB + + + + + COUNTSYNC + Count Read Synchronization Enable + 15 + 1 + + + + + EVCTRL + MODE1 Event Control + 0x4 + 32 + 0x00000000 + + + PEREO0 + Periodic Interval 0 Event Output Enable + 0 + 1 + + + PEREO1 + Periodic Interval 1 Event Output Enable + 1 + 1 + + + PEREO2 + Periodic Interval 2 Event Output Enable + 2 + 1 + + + PEREO3 + Periodic Interval 3 Event Output Enable + 3 + 1 + + + PEREO4 + Periodic Interval 4 Event Output Enable + 4 + 1 + + + PEREO5 + Periodic Interval 5 Event Output Enable + 5 + 1 + + + PEREO6 + Periodic Interval 6 Event Output Enable + 6 + 1 + + + PEREO7 + Periodic Interval 7 Event Output Enable + 7 + 1 + + + CMPEO0 + Compare 0 Event Output Enable + 8 + 1 + + + CMPEO1 + Compare 1 Event Output Enable + 9 + 1 + + + OVFEO + Overflow Event Output Enable + 15 + 1 + + + + + INTENCLR + MODE1 Interrupt Enable Clear + 0x8 + 16 + 0x0000 + + + PER0 + Periodic Interval 0 Interrupt Enable + 0 + 1 + + + PER1 + Periodic Interval 1 Interrupt Enable + 1 + 1 + + + PER2 + Periodic Interval 2 Interrupt Enable + 2 + 1 + + + PER3 + Periodic Interval 3 Interrupt Enable + 3 + 1 + + + PER4 + Periodic Interval 4 Interrupt Enable + 4 + 1 + + + PER5 + Periodic Interval 5 Interrupt Enable + 5 + 1 + + + PER6 + Periodic Interval 6 Interrupt Enable + 6 + 1 + + + PER7 + Periodic Interval 7 Interrupt Enable + 7 + 1 + + + CMP0 + Compare 0 Interrupt Enable + 8 + 1 + + + CMP1 + Compare 1 Interrupt Enable + 9 + 1 + + + OVF + Overflow Interrupt Enable + 15 + 1 + + + + + INTENSET + MODE1 Interrupt Enable Set + 0xA + 16 + 0x0000 + + + PER0 + Periodic Interval 0 Interrupt Enable + 0 + 1 + + + PER1 + Periodic Interval 1 Interrupt Enable + 1 + 1 + + + PER2 + Periodic Interval 2 Interrupt Enable + 2 + 1 + + + PER3 + Periodic Interval 3 Interrupt Enable + 3 + 1 + + + PER4 + Periodic Interval 4 Interrupt Enable + 4 + 1 + + + PER5 + Periodic Interval 5 Interrupt Enable + 5 + 1 + + + PER6 + Periodic Interval 6 Interrupt Enable + 6 + 1 + + + PER7 + Periodic Interval 7 Interrupt Enable + 7 + 1 + + + CMP0 + Compare 0 Interrupt Enable + 8 + 1 + + + CMP1 + Compare 1 Interrupt Enable + 9 + 1 + + + OVF + Overflow Interrupt Enable + 15 + 1 + + + + + INTFLAG + MODE1 Interrupt Flag Status and Clear + 0xC + 16 + 0x0000 + + + PER0 + Periodic Interval 0 + 0 + 1 + + + PER1 + Periodic Interval 1 + 1 + 1 + + + PER2 + Periodic Interval 2 + 2 + 1 + + + PER3 + Periodic Interval 3 + 3 + 1 + + + PER4 + Periodic Interval 4 + 4 + 1 + + + PER5 + Periodic Interval 5 + 5 + 1 + + + PER6 + Periodic Interval 6 + 6 + 1 + + + PER7 + Periodic Interval 7 + 7 + 1 + + + CMP0 + Compare 0 + 8 + 1 + + + CMP1 + Compare 1 + 9 + 1 + + + OVF + Overflow + 15 + 1 + + + + + DBGCTRL + Debug Control + 0xE + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + SYNCBUSY + MODE1 Synchronization Busy Status + 0x10 + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Bit Busy + 0 + 1 + + + ENABLE + Enable Bit Busy + 1 + 1 + + + FREQCORR + FREQCORR Register Busy + 2 + 1 + + + COUNT + COUNT Register Busy + 3 + 1 + + + PER + PER Register Busy + 4 + 1 + + + COMP0 + COMP 0 Register Busy + 5 + 1 + + + COMP1 + COMP 1 Register Busy + 6 + 1 + + + COUNTSYNC + Count Read Synchronization Enable Bit Busy + 15 + 1 + + + + + FREQCORR + Frequency Correction + 0x14 + 8 + 0x00 + + + VALUE + Correction Value + 0 + 7 + + + SIGN + Correction Sign + 7 + 1 + + + + + COUNT + MODE1 Counter Value + 0x18 + 16 + 0x0000 + + + COUNT + Counter Value + 0 + 16 + + + + + PER + MODE1 Counter Period + 0x1C + 16 + 0x0000 + + + PER + Counter Period + 0 + 16 + + + + + 2 + 2 + COMP[%s] + MODE1 Compare n Value + 0x20 + 16 + 0x0000 + + + COMP + Compare Value + 0 + 16 + + + + + + MODE2 + Clock/Calendar with Alarm + MODE0 + RtcMode2 + 0x0 + + CTRLA + MODE2 Control A + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 2 + + MODESelect + + COUNT32 + Mode 0: 32-bit Counter + 0 + + + COUNT16 + Mode 1: 16-bit Counter + 1 + + + CLOCK + Mode 2: Clock/Calendar + 2 + + + + + CLKREP + Clock Representation + 6 + 1 + + + MATCHCLR + Clear on Match + 7 + 1 + + + PRESCALER + Prescaler + 8 + 4 + + PRESCALERSelect + + OFF + CLK_RTC_CNT = GCLK_RTC/1 + 0x0 + + + DIV1 + CLK_RTC_CNT = GCLK_RTC/1 + 0x1 + + + DIV2 + CLK_RTC_CNT = GCLK_RTC/2 + 0x2 + + + DIV4 + CLK_RTC_CNT = GCLK_RTC/4 + 0x3 + + + DIV8 + CLK_RTC_CNT = GCLK_RTC/8 + 0x4 + + + DIV16 + CLK_RTC_CNT = GCLK_RTC/16 + 0x5 + + + DIV32 + CLK_RTC_CNT = GCLK_RTC/32 + 0x6 + + + DIV64 + CLK_RTC_CNT = GCLK_RTC/64 + 0x7 + + + DIV128 + CLK_RTC_CNT = GCLK_RTC/128 + 0x8 + + + DIV256 + CLK_RTC_CNT = GCLK_RTC/256 + 0x9 + + + DIV512 + CLK_RTC_CNT = GCLK_RTC/512 + 0xA + + + DIV1024 + CLK_RTC_CNT = GCLK_RTC/1024 + 0xB + + + + + CLOCKSYNC + Clock Read Synchronization Enable + 15 + 1 + + + + + EVCTRL + MODE2 Event Control + 0x4 + 32 + 0x00000000 + + + PEREO0 + Periodic Interval 0 Event Output Enable + 0 + 1 + + + PEREO1 + Periodic Interval 1 Event Output Enable + 1 + 1 + + + PEREO2 + Periodic Interval 2 Event Output Enable + 2 + 1 + + + PEREO3 + Periodic Interval 3 Event Output Enable + 3 + 1 + + + PEREO4 + Periodic Interval 4 Event Output Enable + 4 + 1 + + + PEREO5 + Periodic Interval 5 Event Output Enable + 5 + 1 + + + PEREO6 + Periodic Interval 6 Event Output Enable + 6 + 1 + + + PEREO7 + Periodic Interval 7 Event Output Enable + 7 + 1 + + + ALARMEO0 + Alarm 0 Event Output Enable + 8 + 1 + + + OVFEO + Overflow Event Output Enable + 15 + 1 + + + + + INTENCLR + MODE2 Interrupt Enable Clear + 0x8 + 16 + 0x0000 + + + PER0 + Periodic Interval 0 Interrupt Enable + 0 + 1 + + + PER1 + Periodic Interval 1 Interrupt Enable + 1 + 1 + + + PER2 + Periodic Interval 2 Interrupt Enable + 2 + 1 + + + PER3 + Periodic Interval 3 Interrupt Enable + 3 + 1 + + + PER4 + Periodic Interval 4 Interrupt Enable + 4 + 1 + + + PER5 + Periodic Interval 5 Interrupt Enable + 5 + 1 + + + PER6 + Periodic Interval 6 Interrupt Enable + 6 + 1 + + + PER7 + Periodic Interval 7 Interrupt Enable + 7 + 1 + + + ALARM0 + Alarm 0 Interrupt Enable + 8 + 1 + + + OVF + Overflow Interrupt Enable + 15 + 1 + + + + + INTENSET + MODE2 Interrupt Enable Set + 0xA + 16 + 0x0000 + + + PER0 + Periodic Interval 0 Enable + 0 + 1 + + + PER1 + Periodic Interval 1 Enable + 1 + 1 + + + PER2 + Periodic Interval 2 Enable + 2 + 1 + + + PER3 + Periodic Interval 3 Enable + 3 + 1 + + + PER4 + Periodic Interval 4 Enable + 4 + 1 + + + PER5 + Periodic Interval 5 Enable + 5 + 1 + + + PER6 + Periodic Interval 6 Enable + 6 + 1 + + + PER7 + Periodic Interval 7 Enable + 7 + 1 + + + ALARM0 + Alarm 0 Interrupt Enable + 8 + 1 + + + OVF + Overflow Interrupt Enable + 15 + 1 + + + + + INTFLAG + MODE2 Interrupt Flag Status and Clear + 0xC + 16 + 0x0000 + + + PER0 + Periodic Interval 0 + 0 + 1 + + + PER1 + Periodic Interval 1 + 1 + 1 + + + PER2 + Periodic Interval 2 + 2 + 1 + + + PER3 + Periodic Interval 3 + 3 + 1 + + + PER4 + Periodic Interval 4 + 4 + 1 + + + PER5 + Periodic Interval 5 + 5 + 1 + + + PER6 + Periodic Interval 6 + 6 + 1 + + + PER7 + Periodic Interval 7 + 7 + 1 + + + ALARM0 + Alarm 0 + 8 + 1 + + + OVF + Overflow + 15 + 1 + + + + + DBGCTRL + Debug Control + 0xE + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + SYNCBUSY + MODE2 Synchronization Busy Status + 0x10 + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Bit Busy + 0 + 1 + + + ENABLE + Enable Bit Busy + 1 + 1 + + + FREQCORR + FREQCORR Register Busy + 2 + 1 + + + CLOCK + CLOCK Register Busy + 3 + 1 + + + ALARM0 + ALARM 0 Register Busy + 5 + 1 + + + MASK0 + MASK 0 Register Busy + 11 + 1 + + + CLOCKSYNC + Clock Read Synchronization Enable Bit Busy + 15 + 1 + + + + + FREQCORR + Frequency Correction + 0x14 + 8 + 0x00 + + + VALUE + Correction Value + 0 + 7 + + + SIGN + Correction Sign + 7 + 1 + + + + + CLOCK + MODE2 Clock Value + 0x18 + 32 + 0x00000000 + + + SECOND + Second + 0 + 6 + + + MINUTE + Minute + 6 + 6 + + + HOUR + Hour + 12 + 5 + + HOURSelect + + AM + AM when CLKREP in 12-hour + 0x00 + + + PM + PM when CLKREP in 12-hour + 0x10 + + + + + DAY + Day + 17 + 5 + + + MONTH + Month + 22 + 4 + + + YEAR + Year + 26 + 6 + + + + + ALARM + MODE2_ALARM Alarm n Value + 0x20 + 32 + 0x00000000 + + + SECOND + Second + 0 + 6 + + + MINUTE + Minute + 6 + 6 + + + HOUR + Hour + 12 + 5 + + HOURSelect + + AM + Morning hour + 0x00 + + + PM + Afternoon hour + 0x10 + + + + + DAY + Day + 17 + 5 + + + MONTH + Month + 22 + 4 + + + YEAR + Year + 26 + 6 + + + + + MASK + MODE2_ALARM Alarm n Mask + 0x24 + 8 + 0x00 + + + SEL + Alarm Mask Selection + 0 + 3 + + SELSelect + + OFF + Alarm Disabled + 0x0 + + + SS + Match seconds only + 0x1 + + + MMSS + Match seconds and minutes only + 0x2 + + + HHMMSS + Match seconds, minutes, and hours only + 0x3 + + + DDHHMMSS + Match seconds, minutes, hours, and days only + 0x4 + + + MMDDHHMMSS + Match seconds, minutes, hours, days, and months only + 0x5 + + + YYMMDDHHMMSS + Match seconds, minutes, hours, days, months, and years + 0x6 + + + + + + + + + + SDADC + U22601.0.1 + Sigma-Delta Analog Digital Converter + SDADC + SDADC_ + 0x42004C00 + + 0 + 0x2F + registers + + + SDADC + 29 + + + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + RUNSTDBY + Run during Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + + + REFCTRL + Reference Control + 0x1 + 8 + 0x00 + + + REFSEL + Reference Selection + 0 + 2 + + REFSELSelect + + INTREF + Internal Bandgap Reference + 0 + + + AREFB + External Reference + 1 + + + DAC + Internal DAC Output + 2 + + + INTVCC + VDDANA + 3 + + + + + REFRANGE + Reference Range + 4 + 2 + + + ONREFBUF + Reference Buffer + 7 + 1 + + + + + CTRLB + Control B + 0x2 + 16 + 0x2000 + + + PRESCALER + Prescaler Configuration + 0 + 8 + + PRESCALERSelect + + DIV2 + Peripheral clock divided by 2 + 0x0 + + + DIV4 + Peripheral clock divided by 4 + 0x1 + + + DIV8 + Peripheral clock divided by 8 + 0x2 + + + DIV16 + Peripheral clock divided by 16 + 0x3 + + + DIV32 + Peripheral clock divided by 32 + 0x4 + + + DIV64 + Peripheral clock divided by 64 + 0x5 + + + DIV128 + Peripheral clock divided by 128 + 0x6 + + + DIV256 + Peripheral clock divided by 256 + 0x7 + + + + + OSR + Over Sampling Ratio + 8 + 3 + + OSRSelect + + OSR64 + Over Sampling Ratio is 64 + 0x0 + + + OSR128 + Over Sampling Ratio is 128 + 0x1 + + + OSR256 + Over Sampling Ratio is 256 + 0x2 + + + OSR512 + Over Sampling Ratio is 512 + 0x3 + + + OSR1024 + Over Sampling Ratio is 1024 + 0x4 + + + + + SKPCNT + Skip Sample Count + 12 + 4 + + + + + EVCTRL + Event Control + 0x4 + 8 + 0x00 + + + FLUSHEI + Flush Event Input Enable + 0 + 1 + + + STARTEI + Start Conversion Event Input Enable + 1 + 1 + + + FLUSHINV + Flush Event Invert Enable + 2 + 1 + + + STARTINV + Satrt Event Invert Enable + 3 + 1 + + + RESRDYEO + Result Ready Event Out + 4 + 1 + + + WINMONEO + Window Monitor Event Out + 5 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x5 + 8 + 0x00 + + + RESRDY + Result Ready Interrupt Disable + 0 + 1 + + + OVERRUN + Overrun Interrupt Disable + 1 + 1 + + + WINMON + Window Monitor Interrupt Disable + 2 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x6 + 8 + 0x00 + + + RESRDY + Result Ready Interrupt Enable + 0 + 1 + + + OVERRUN + Overrun Interrupt Enable + 1 + 1 + + + WINMON + Window Monitor Interrupt Enable + 2 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x7 + 8 + 0x00 + + + RESRDY + Result Ready Interrupt Flag + 0 + 1 + + + OVERRUN + Overrun Interrupt Flag + 1 + 1 + + + WINMON + Window Monitor Interrupt Flag + 2 + 1 + + + + + SEQSTATUS + Sequence Status + 0x8 + 8 + read-only + 0x00 + + + SEQSTATE + Sequence State + 0 + 4 + + + SEQBUSY + Sequence Busy + 7 + 1 + + + + + INPUTCTRL + Input Control + 0x9 + 8 + 0x00 + + + MUXSEL + SDADC Input Selection + 0 + 4 + + MUXSELSelect + + AIN0 + SDADC AIN0 Pin + 0x0 + + + AIN1 + SDADC AIN1 Pin + 0x1 + + + AIN2 + SDADC AIN2 Pin + 0x2 + + + + + + + CTRLC + Control C + 0xA + 8 + 0x00 + + + FREERUN + Free Running Mode + 0 + 1 + + + + + WINCTRL + Window Monitor Control + 0xB + 8 + 0x00 + + + WINMODE + Window Monitor Mode + 0 + 3 + + + + + WINLT + Window Monitor Lower Threshold + 0xC + 32 + 0x00000000 + + + WINLT + Window Lower Threshold + 0 + 24 + + + + + WINUT + Window Monitor Upper Threshold + 0x10 + 32 + 0x00000000 + + + WINUT + Window Upper Threshold + 0 + 24 + + + + + OFFSETCORR + Offset Correction + 0x14 + 32 + 0x00000000 + + + OFFSETCORR + Offset Correction Value + 0 + 24 + + + + + GAINCORR + Gain Correction + 0x18 + 16 + 0x0001 + + + GAINCORR + Gain Correction Value + 0 + 14 + + + + + SHIFTCORR + Shift Correction + 0x1A + 8 + 0x00 + + + SHIFTCORR + Shift Correction Value + 0 + 4 + + + + + SWTRIG + Software Trigger + 0x1C + 8 + 0x00 + + + FLUSH + SDADC Flush + 0 + 1 + + + START + Start SDADC Conversion + 1 + 1 + + + + + SYNCBUSY + Synchronization Busy + 0x20 + 32 + read-only + 0x00000000 + + + SWRST + SWRST Synchronization Busy + 0 + 1 + + + ENABLE + ENABLE Synchronization Busy + 1 + 1 + + + CTRLC + CTRLC Synchronization Busy + 2 + 1 + + + INPUTCTRL + INPUTCTRL Synchronization Busy + 3 + 1 + + + WINCTRL + WINCTRL Synchronization Busy + 4 + 1 + + + WINLT + WINLT Synchronization Busy + 5 + 1 + + + WINUT + WINUT Synchronization Busy + 6 + 1 + + + OFFSETCORR + OFFSETCTRL Synchronization Busy + 7 + 1 + + + GAINCORR + GAINCORR Synchronization Busy + 8 + 1 + + + SHIFTCORR + SHIFTCORR Synchronization Busy + 9 + 1 + + + SWTRIG + SWTRG Synchronization Busy + 10 + 1 + + + ANACTRL + ANACTRL Synchronization Busy + 11 + 1 + + + + + RESULT + Result + 0x24 + 32 + read-only + 0x00000000 + + + RESULT + Result Value + 0 + 24 + + + RESERVED + 24 + 8 + + + + + SEQCTRL + Sequence Control + 0x28 + 8 + 0x00 + + + SEQEN + Enable Positive Input in the Sequence + 0 + 3 + + + + + ANACTRL + Analog Control + 0x2C + 8 + 0x00 + + + CTRSDADC + SDADC Control + 0 + 6 + + + ONCHOP + Chopper + 6 + 1 + + + BUFTEST + BUFTEST + 7 + 1 + + + + + DBGCTRL + Debug Control + 0x2E + 8 + 0x00 + + + DBGRUN + Debug Run + 0 + 1 + + + + + + + SERCOM0 + U22013.1.1 + Serial Communication Interface + SERCOM + SERCOM_ + 0x42000400 + + 0 + 0x31 + registers + + + SERCOM0 + 9 + + + + I2CM + I2C Master Mode + SercomI2cm + 0x0 + + CTRLA + I2CM Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run in Standby + 7 + 1 + + + PINOUT + Pin Usage + 16 + 1 + + + SDAHOLD + SDA Hold Time + 20 + 2 + + SDAHOLDSelect + + DISABLE + Disabled + 0x0 + + + 75NS + 50-100ns hold time + 0x1 + + + 450NS + 300-600ns hold time + 0x2 + + + 600NS + 400-800ns hold time + 0x3 + + + + + MEXTTOEN + Master SCL Low Extend Timeout + 22 + 1 + + + SEXTTOEN + Slave SCL Low Extend Timeout + 23 + 1 + + + SPEED + Transfer Speed + 24 + 2 + + SPEEDSelect + + STANDARD_AND_FAST_MODE + Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz + 0x0 + + + FASTPLUS_MODE + Fast-mode Plus Upto 1MHz + 0x1 + + + HIGH_SPEED_MODE + High-speed mode Upto 3.4MHz + 0x2 + + + + + SCLSM + SCL Clock Stretch Mode + 27 + 1 + + + INACTOUT + Inactive Time-Out + 28 + 2 + + INACTOUTSelect + + DISABLE + Disabled + 0x0 + + + 55US + 5-6 SCL Time-Out(50-60us) + 0x1 + + + 105US + 10-11 SCL Time-Out(100-110us) + 0x2 + + + 205US + 20-21 SCL Time-Out(200-210us) + 0x3 + + + + + LOWTOUTEN + SCL Low Timeout Enable + 30 + 1 + + + + + CTRLB + I2CM Control B + 0x4 + 32 + 0x00000000 + + + SMEN + Smart Mode Enable + 8 + 1 + + + QCEN + Quick Command Enable + 9 + 1 + + + CMD + Command + 16 + 2 + + + ACKACT + Acknowledge Action + 18 + 1 + + + + + BAUD + I2CM Baud Rate + 0xC + 32 + 0x00000000 + + + BAUD + Baud Rate Value + 0 + 8 + + + BAUDLOW + Baud Rate Value Low + 8 + 8 + + + HSBAUD + High Speed Baud Rate Value + 16 + 8 + + + HSBAUDLOW + High Speed Baud Rate Value Low + 24 + 8 + + + + + INTENCLR + I2CM Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + MB + Master On Bus Interrupt Disable + 0 + 1 + + + SB + Slave On Bus Interrupt Disable + 1 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + I2CM Interrupt Enable Set + 0x16 + 8 + 0x00 + + + MB + Master On Bus Interrupt Enable + 0 + 1 + + + SB + Slave On Bus Interrupt Enable + 1 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + I2CM Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + MB + Master On Bus Interrupt + 0 + 1 + + + SB + Slave On Bus Interrupt + 1 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + I2CM Status + 0x1A + 16 + 0x0000 + + + BUSERR + Bus Error + 0 + 1 + + + ARBLOST + Arbitration Lost + 1 + 1 + + + RXNACK + Received Not Acknowledge + 2 + 1 + + + BUSSTATE + Bus State + 4 + 2 + + + LOWTOUT + SCL Low Timeout + 6 + 1 + + + CLKHOLD + Clock Hold + 7 + 1 + + + MEXTTOUT + Master SCL Low Extend Timeout + 8 + 1 + + + SEXTTOUT + Slave SCL Low Extend Timeout + 9 + 1 + + + LENERR + Length Error + 10 + 1 + + + + + SYNCBUSY + I2CM Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + SYSOP + System Operation Synchronization Busy + 2 + 1 + + + + + ADDR + I2CM Address + 0x24 + 32 + 0x00000000 + + + ADDR + Address Value + 0 + 11 + + + LENEN + Length Enable + 13 + 1 + + + HS + High Speed Mode + 14 + 1 + + + TENBITEN + Ten Bit Addressing Enable + 15 + 1 + + + LEN + Length + 16 + 8 + + + + + DATA + I2CM Data + 0x28 + 8 + 0x00 + + + DATA + Data Value + 0 + 8 + + + + + DBGCTRL + I2CM Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + I2CS + I2C Slave Mode + I2CM + SercomI2cs + 0x0 + + CTRLA + I2CS Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + PINOUT + Pin Usage + 16 + 1 + + + SDAHOLD + SDA Hold Time + 20 + 2 + + SDAHOLDSelect + + DISABLE + Disabled + 0x0 + + + 75NS + 50-100ns hold time + 0x1 + + + 450NS + 300-600ns hold time + 0x2 + + + 600NS + 400-800ns hold time + 0x3 + + + + + SEXTTOEN + Slave SCL Low Extend Timeout + 23 + 1 + + + SPEED + Transfer Speed + 24 + 2 + + SPEEDSelect + + STANDARD_AND_FAST_MODE + Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz + 0x0 + + + FASTPLUS_MODE + Fast-mode Plus Upto 1MHz + 0x1 + + + HIGH_SPEED_MODE + High-speed mode Upto 3.4MHz + 0x2 + + + + + SCLSM + SCL Clock Stretch Mode + 27 + 1 + + + LOWTOUTEN + SCL Low Timeout Enable + 30 + 1 + + + + + CTRLB + I2CS Control B + 0x4 + 32 + 0x00000000 + + + SMEN + Smart Mode Enable + 8 + 1 + + + GCMD + PMBus Group Command + 9 + 1 + + + AACKEN + Automatic Address Acknowledge + 10 + 1 + + + AMODE + Address Mode + 14 + 2 + + + CMD + Command + 16 + 2 + + + ACKACT + Acknowledge Action + 18 + 1 + + + + + INTENCLR + I2CS Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + PREC + Stop Received Interrupt Disable + 0 + 1 + + + AMATCH + Address Match Interrupt Disable + 1 + 1 + + + DRDY + Data Interrupt Disable + 2 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + I2CS Interrupt Enable Set + 0x16 + 8 + 0x00 + + + PREC + Stop Received Interrupt Enable + 0 + 1 + + + AMATCH + Address Match Interrupt Enable + 1 + 1 + + + DRDY + Data Interrupt Enable + 2 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + I2CS Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + PREC + Stop Received Interrupt + 0 + 1 + + + AMATCH + Address Match Interrupt + 1 + 1 + + + DRDY + Data Interrupt + 2 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + I2CS Status + 0x1A + 16 + 0x0000 + + + BUSERR + Bus Error + 0 + 1 + + + COLL + Transmit Collision + 1 + 1 + + + RXNACK + Received Not Acknowledge + 2 + 1 + + + DIR + Read/Write Direction + 3 + 1 + + + SR + Repeated Start + 4 + 1 + + + LOWTOUT + SCL Low Timeout + 6 + 1 + + + CLKHOLD + Clock Hold + 7 + 1 + + + SEXTTOUT + Slave SCL Low Extend Timeout + 9 + 1 + + + HS + High Speed + 10 + 1 + + + + + SYNCBUSY + I2CS Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + + + ADDR + I2CS Address + 0x24 + 32 + 0x00000000 + + + GENCEN + General Call Address Enable + 0 + 1 + + + ADDR + Address Value + 1 + 10 + + + TENBITEN + Ten Bit Addressing Enable + 15 + 1 + + + ADDRMASK + Address Mask + 17 + 10 + + + + + DATA + I2CS Data + 0x28 + 8 + 0x00 + + + DATA + Data Value + 0 + 8 + + + + + + SPIS + SPI Slave Mode + I2CM + SercomSpis + 0x0 + + CTRLA + SPIS Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + IBON + Immediate Buffer Overflow Notification + 8 + 1 + + + DOPO + Data Out Pinout + 16 + 2 + + DOPOSelect + + PAD0 + DO on PAD[0], SCK on PAD[1] and SS on PAD[2] + 0x0 + + + PAD1 + DO on PAD[2], SCK on PAD[3] and SS on PAD[1] + 0x1 + + + PAD2 + DO on PAD[3], SCK on PAD[1] and SS on PAD[2] + 0x2 + + + PAD3 + DO on PAD[0], SCK on PAD[3] and SS on PAD[1] + 0x3 + + + + + DIPO + Data In Pinout + 20 + 2 + + DIPOSelect + + PAD0 + SERCOM PAD[0] + 0x0 + + + PAD1 + SERCOM PAD[1] + 0x1 + + + PAD2 + SERCOM PAD[2] + 0x2 + + + PAD3 + SERCOM PAD[3] + 0x3 + + + + + FORM + Frame Format + 24 + 4 + + FORMSelect + + SPI_FRAME + SPI Frame + 0x0 + + + SPI_FRAME_WITH_ADDR + SPI Frame with Addr + 0x2 + + + + + CPHA + Clock Phase + 28 + 1 + + CPHASelect + + LEADING_EDGE + The data is sampled on a leading SCK edge and changed on a trailing SCK edge + 0x0 + + + TRAILING_EDGE + The data is sampled on a trailing SCK edge and changed on a leading SCK edge + 0x1 + + + + + CPOL + Clock Polarity + 29 + 1 + + CPOLSelect + + IDLE_LOW + SCK is low when idle + 0x0 + + + IDLE_HIGH + SCK is high when idle + 0x1 + + + + + DORD + Data Order + 30 + 1 + + DORDSelect + + MSB + MSB is transferred first + 0x0 + + + LSB + LSB is transferred first + 0x1 + + + + + + + CTRLB + SPIS Control B + 0x4 + 32 + 0x00000000 + + + CHSIZE + Character Size + 0 + 3 + + CHSIZESelect + + 8_BIT + 8 bits + 0x0 + + + 9_BIT + 9 bits + 0x1 + + + + + PLOADEN + Data Preload Enable + 6 + 1 + + + SSDE + Slave Select Low Detect Enable + 9 + 1 + + + MSSEN + Master Slave Select Enable + 13 + 1 + + + AMODE + Address Mode + 14 + 2 + + AMODESelect + + MASK + SPI Address mask + 0x0 + + + 2_ADDRESSES + Two unique Addressess + 0x1 + + + RANGE + Address Range + 0x2 + + + + + RXEN + Receiver Enable + 17 + 1 + + + + + BAUD + SPIS Baud Rate + 0xC + 8 + 0x00 + + + BAUD + Baud Rate Value + 0 + 8 + + + + + INTENCLR + SPIS Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Disable + 0 + 1 + + + TXC + Transmit Complete Interrupt Disable + 1 + 1 + + + RXC + Receive Complete Interrupt Disable + 2 + 1 + + + SSL + Slave Select Low Interrupt Disable + 3 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + SPIS Interrupt Enable Set + 0x16 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Enable + 0 + 1 + + + TXC + Transmit Complete Interrupt Enable + 1 + 1 + + + RXC + Receive Complete Interrupt Enable + 2 + 1 + + + SSL + Slave Select Low Interrupt Enable + 3 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + SPIS Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt + 0 + 1 + + + TXC + Transmit Complete Interrupt + 1 + 1 + + + RXC + Receive Complete Interrupt + 2 + 1 + + + SSL + Slave Select Low Interrupt Flag + 3 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + SPIS Status + 0x1A + 16 + 0x0000 + + + BUFOVF + Buffer Overflow + 2 + 1 + + + + + SYNCBUSY + SPIS Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + CTRLB + CTRLB Synchronization Busy + 2 + 1 + + + + + ADDR + SPIS Address + 0x24 + 32 + 0x00000000 + + + ADDR + Address Value + 0 + 8 + + + ADDRMASK + Address Mask + 16 + 8 + + + + + DATA + SPIS Data + 0x28 + 32 + 0x00000000 + + + DATA + Data Value + 0 + 9 + + + + + DBGCTRL + SPIS Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + SPIM + SPI Master Mode + I2CM + SercomSpim + 0x0 + + CTRLA + SPIM Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + IBON + Immediate Buffer Overflow Notification + 8 + 1 + + + DOPO + Data Out Pinout + 16 + 2 + + DOPOSelect + + PAD0 + DO on PAD[0], SCK on PAD[1] and SS on PAD[2] + 0x0 + + + PAD1 + DO on PAD[2], SCK on PAD[3] and SS on PAD[1] + 0x1 + + + PAD2 + DO on PAD[3], SCK on PAD[1] and SS on PAD[2] + 0x2 + + + PAD3 + DO on PAD[0], SCK on PAD[3] and SS on PAD[1] + 0x3 + + + + + DIPO + Data In Pinout + 20 + 2 + + DIPOSelect + + PAD0 + SERCOM PAD[0] + 0x0 + + + PAD1 + SERCOM PAD[1] + 0x1 + + + PAD2 + SERCOM PAD[2] + 0x2 + + + PAD3 + SERCOM PAD[3] + 0x3 + + + + + FORM + Frame Format + 24 + 4 + + FORMSelect + + SPI_FRAME + SPI Frame + 0x0 + + + SPI_FRAME_WITH_ADDR + SPI Frame with Addr + 0x2 + + + + + CPHA + Clock Phase + 28 + 1 + + CPHASelect + + LEADING_EDGE + The data is sampled on a leading SCK edge and changed on a trailing SCK edge + 0x0 + + + TRAILING_EDGE + The data is sampled on a trailing SCK edge and changed on a leading SCK edge + 0x1 + + + + + CPOL + Clock Polarity + 29 + 1 + + CPOLSelect + + IDLE_LOW + SCK is low when idle + 0x0 + + + IDLE_HIGH + SCK is high when idle + 0x1 + + + + + DORD + Data Order + 30 + 1 + + DORDSelect + + MSB + MSB is transferred first + 0x0 + + + LSB + LSB is transferred first + 0x1 + + + + + + + CTRLB + SPIM Control B + 0x4 + 32 + 0x00000000 + + + CHSIZE + Character Size + 0 + 3 + + CHSIZESelect + + 8_BIT + 8 bits + 0x0 + + + 9_BIT + 9 bits + 0x1 + + + + + PLOADEN + Data Preload Enable + 6 + 1 + + + SSDE + Slave Select Low Detect Enable + 9 + 1 + + + MSSEN + Master Slave Select Enable + 13 + 1 + + + AMODE + Address Mode + 14 + 2 + + AMODESelect + + MASK + SPI Address mask + 0x0 + + + 2_ADDRESSES + Two unique Addressess + 0x1 + + + RANGE + Address Range + 0x2 + + + + + RXEN + Receiver Enable + 17 + 1 + + + + + BAUD + SPIM Baud Rate + 0xC + 8 + 0x00 + + + BAUD + Baud Rate Value + 0 + 8 + + + + + INTENCLR + SPIM Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Disable + 0 + 1 + + + TXC + Transmit Complete Interrupt Disable + 1 + 1 + + + RXC + Receive Complete Interrupt Disable + 2 + 1 + + + SSL + Slave Select Low Interrupt Disable + 3 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + SPIM Interrupt Enable Set + 0x16 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Enable + 0 + 1 + + + TXC + Transmit Complete Interrupt Enable + 1 + 1 + + + RXC + Receive Complete Interrupt Enable + 2 + 1 + + + SSL + Slave Select Low Interrupt Enable + 3 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + SPIM Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt + 0 + 1 + + + TXC + Transmit Complete Interrupt + 1 + 1 + + + RXC + Receive Complete Interrupt + 2 + 1 + + + SSL + Slave Select Low Interrupt Flag + 3 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + SPIM Status + 0x1A + 16 + 0x0000 + + + BUFOVF + Buffer Overflow + 2 + 1 + + + + + SYNCBUSY + SPIM Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + CTRLB + CTRLB Synchronization Busy + 2 + 1 + + + + + ADDR + SPIM Address + 0x24 + 32 + 0x00000000 + + + ADDR + Address Value + 0 + 8 + + + ADDRMASK + Address Mask + 16 + 8 + + + + + DATA + SPIM Data + 0x28 + 32 + 0x00000000 + + + DATA + Data Value + 0 + 9 + + + + + DBGCTRL + SPIM Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + USART_EXT + USART EXTERNAL CLOCK Mode + I2CM + SercomUsart_ext + 0x0 + + CTRLA + USART_EXT Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + IBON + Immediate Buffer Overflow Notification + 8 + 1 + + + SAMPR + Sample + 13 + 3 + + SAMPRSelect + + 16X_ARITHMETIC + 16x over-sampling using arithmetic baudrate generation + 0x0 + + + 16X_FRACTIONAL + 16x over-sampling using fractional baudrate generation + 0x1 + + + 8X_ARITHMETIC + 8x over-sampling using arithmetic baudrate generation + 0x2 + + + 8X_FRACTIONAL + 8x over-sampling using fractional baudrate generation + 0x3 + + + 3X_ARITHMETIC + 3x over-sampling using arithmetic baudrate generation + 0x4 + + + + + TXPO + Transmit Data Pinout + 16 + 2 + + TXPOSelect + + PAD0 + SERCOM PAD[0] is used for data transmission + 0x0 + + + PAD2 + SERCOM PAD[2] is used for data transmission + 0x1 + + + + + RXPO + Receive Data Pinout + 20 + 2 + + RXPOSelect + + PAD0 + SERCOM PAD[0] is used for data reception + 0x0 + + + PAD1 + SERCOM PAD[1] is used for data reception + 0x1 + + + PAD2 + SERCOM PAD[2] is used for data reception + 0x2 + + + PAD3 + SERCOM PAD[3] is used for data reception + 0x3 + + + + + SAMPA + Sample Adjustment + 22 + 2 + + + FORM + Frame Format + 24 + 4 + + FORMSelect + + USART_FRAME_NO_PARITY + USART frame + 0x0 + + + USART_FRAME_WITH_PARITY + USART frame with parity + 0x1 + + + USART_FRAME_LIN_MASTER_MODE + LIN Master - Break and sync generation + 0x2 + + + USART_FRAME_AUTO_BAUD_NO_PARITY + Auto-baud - break detection and auto-baud + 0x4 + + + USART_FRAME_AUTO_BAUD_WITH_PARITY + Auto-baud - break detection and auto-baud with parity + 0x5 + + + + + CMODE + Communication Mode + 28 + 1 + + CMODESelect + + ASYNC + Asynchronous Communication + 0x0 + + + SYNC + Synchronous Communication + 0x1 + + + + + CPOL + Clock Polarity + 29 + 1 + + CPOLSelect + + IDLE_LOW + TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge + 0x0 + + + IDLE_HIGH + TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge + 0x1 + + + + + DORD + Data Order + 30 + 1 + + DORDSelect + + MSB + MSB is transmitted first + 0x0 + + + LSB + LSB is transmitted first + 0x1 + + + + + + + CTRLB + USART_EXT Control B + 0x4 + 32 + 0x00000000 + + + CHSIZE + Character Size + 0 + 3 + + CHSIZESelect + + 8_BIT + 8 Bits + 0x0 + + + 9_BIT + 9 Bits + 0x1 + + + 5_BIT + 5 Bits + 0x5 + + + 6_BIT + 6 Bits + 0x6 + + + 7_BIT + 7 Bits + 0x7 + + + + + SBMODE + Stop Bit Mode + 6 + 1 + + SBMODESelect + + 1_BIT + One Stop Bit + 0x0 + + + 2_BIT + Two Stop Bits + 0x1 + + + + + COLDEN + Collision Detection Enable + 8 + 1 + + + SFDE + Start of Frame Detection Enable + 9 + 1 + + + ENC + Encoding Format + 10 + 1 + + + PMODE + Parity Mode + 13 + 1 + + PMODESelect + + EVEN + Even Parity + 0x0 + + + ODD + Odd Parity + 0x1 + + + + + TXEN + Transmitter Enable + 16 + 1 + + + RXEN + Receiver Enable + 17 + 1 + + + LINCMD + LIN Command + 24 + 2 + + + + + CTRLC + USART_EXT Control C + 0x8 + 32 + 0x00000000 + + + GTIME + RS485 Guard Time + 0 + 3 + + + BRKLEN + LIN Master Break Length + 8 + 2 + + + HDRDLY + LIN Master Header Delay + 10 + 2 + + + + + BAUD + USART_EXT Baud Rate + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 16 + + + + + BAUD_FRAC_MODE + USART_EXT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 13 + + + FP + Fractional Part + 13 + 3 + + + + + BAUD_FRACFP_MODE + USART_EXT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 13 + + + FP + Fractional Part + 13 + 3 + + + + + BAUD_USARTFP_MODE + USART_EXT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 16 + + + + + RXPL + USART_EXT Receive Pulse Length + 0xE + 8 + 0x00 + + + RXPL + Receive Pulse Length + 0 + 8 + + + + + INTENCLR + USART_EXT Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Disable + 0 + 1 + + + TXC + Transmit Complete Interrupt Disable + 1 + 1 + + + RXC + Receive Complete Interrupt Disable + 2 + 1 + + + RXS + Receive Start Interrupt Disable + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt Disable + 4 + 1 + + + RXBRK + Break Received Interrupt Disable + 5 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + USART_EXT Interrupt Enable Set + 0x16 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Enable + 0 + 1 + + + TXC + Transmit Complete Interrupt Enable + 1 + 1 + + + RXC + Receive Complete Interrupt Enable + 2 + 1 + + + RXS + Receive Start Interrupt Enable + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt Enable + 4 + 1 + + + RXBRK + Break Received Interrupt Enable + 5 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + USART_EXT Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt + 0 + 1 + + + TXC + Transmit Complete Interrupt + 1 + 1 + + + RXC + Receive Complete Interrupt + 2 + 1 + + + RXS + Receive Start Interrupt + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt + 4 + 1 + + + RXBRK + Break Received Interrupt + 5 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + USART_EXT Status + 0x1A + 16 + 0x0000 + + + PERR + Parity Error + 0 + 1 + + + FERR + Frame Error + 1 + 1 + + + BUFOVF + Buffer Overflow + 2 + 1 + + + CTS + Clear To Send + 3 + 1 + + + ISF + Inconsistent Sync Field + 4 + 1 + + + COLL + Collision Detected + 5 + 1 + + + TXE + Transmitter Empty + 6 + 1 + + + + + SYNCBUSY + USART_EXT Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + CTRLB + CTRLB Synchronization Busy + 2 + 1 + + + + + DATA + USART_EXT Data + 0x28 + 16 + 0x0000 + + + DATA + Data Value + 0 + 9 + + + + + DBGCTRL + USART_EXT Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + USART_INT + USART INTERNAL CLOCK Mode + I2CM + SercomUsart_int + 0x0 + + CTRLA + USART_INT Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + IBON + Immediate Buffer Overflow Notification + 8 + 1 + + + SAMPR + Sample + 13 + 3 + + SAMPRSelect + + 16X_ARITHMETIC + 16x over-sampling using arithmetic baudrate generation + 0x0 + + + 16X_FRACTIONAL + 16x over-sampling using fractional baudrate generation + 0x1 + + + 8X_ARITHMETIC + 8x over-sampling using arithmetic baudrate generation + 0x2 + + + 8X_FRACTIONAL + 8x over-sampling using fractional baudrate generation + 0x3 + + + 3X_ARITHMETIC + 3x over-sampling using arithmetic baudrate generation + 0x4 + + + + + TXPO + Transmit Data Pinout + 16 + 2 + + TXPOSelect + + PAD0 + SERCOM PAD[0] is used for data transmission + 0x0 + + + PAD2 + SERCOM PAD[2] is used for data transmission + 0x1 + + + + + RXPO + Receive Data Pinout + 20 + 2 + + RXPOSelect + + PAD0 + SERCOM PAD[0] is used for data reception + 0x0 + + + PAD1 + SERCOM PAD[1] is used for data reception + 0x1 + + + PAD2 + SERCOM PAD[2] is used for data reception + 0x2 + + + PAD3 + SERCOM PAD[3] is used for data reception + 0x3 + + + + + SAMPA + Sample Adjustment + 22 + 2 + + + FORM + Frame Format + 24 + 4 + + FORMSelect + + USART_FRAME_NO_PARITY + USART frame + 0x0 + + + USART_FRAME_WITH_PARITY + USART frame with parity + 0x1 + + + USART_FRAME_LIN_MASTER_MODE + LIN Master - Break and sync generation + 0x2 + + + USART_FRAME_AUTO_BAUD_NO_PARITY + Auto-baud - break detection and auto-baud + 0x4 + + + USART_FRAME_AUTO_BAUD_WITH_PARITY + Auto-baud - break detection and auto-baud with parity + 0x5 + + + + + CMODE + Communication Mode + 28 + 1 + + CMODESelect + + ASYNC + Asynchronous Communication + 0x0 + + + SYNC + Synchronous Communication + 0x1 + + + + + CPOL + Clock Polarity + 29 + 1 + + CPOLSelect + + IDLE_LOW + TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge + 0x0 + + + IDLE_HIGH + TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge + 0x1 + + + + + DORD + Data Order + 30 + 1 + + DORDSelect + + MSB + MSB is transmitted first + 0x0 + + + LSB + LSB is transmitted first + 0x1 + + + + + + + CTRLB + USART_INT Control B + 0x4 + 32 + 0x00000000 + + + CHSIZE + Character Size + 0 + 3 + + CHSIZESelect + + 8_BIT + 8 Bits + 0x0 + + + 9_BIT + 9 Bits + 0x1 + + + 5_BIT + 5 Bits + 0x5 + + + 6_BIT + 6 Bits + 0x6 + + + 7_BIT + 7 Bits + 0x7 + + + + + SBMODE + Stop Bit Mode + 6 + 1 + + SBMODESelect + + 1_BIT + One Stop Bit + 0x0 + + + 2_BIT + Two Stop Bits + 0x1 + + + + + COLDEN + Collision Detection Enable + 8 + 1 + + + SFDE + Start of Frame Detection Enable + 9 + 1 + + + ENC + Encoding Format + 10 + 1 + + + PMODE + Parity Mode + 13 + 1 + + PMODESelect + + EVEN + Even Parity + 0x0 + + + ODD + Odd Parity + 0x1 + + + + + TXEN + Transmitter Enable + 16 + 1 + + + RXEN + Receiver Enable + 17 + 1 + + + LINCMD + LIN Command + 24 + 2 + + + + + CTRLC + USART_INT Control C + 0x8 + 32 + 0x00000000 + + + GTIME + RS485 Guard Time + 0 + 3 + + + BRKLEN + LIN Master Break Length + 8 + 2 + + + HDRDLY + LIN Master Header Delay + 10 + 2 + + + + + BAUD + USART_INT Baud Rate + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 16 + + + + + BAUD_FRAC_MODE + USART_INT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 13 + + + FP + Fractional Part + 13 + 3 + + + + + BAUD_FRACFP_MODE + USART_INT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 13 + + + FP + Fractional Part + 13 + 3 + + + + + BAUD_USARTFP_MODE + USART_INT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 16 + + + + + RXPL + USART_INT Receive Pulse Length + 0xE + 8 + 0x00 + + + RXPL + Receive Pulse Length + 0 + 8 + + + + + INTENCLR + USART_INT Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Disable + 0 + 1 + + + TXC + Transmit Complete Interrupt Disable + 1 + 1 + + + RXC + Receive Complete Interrupt Disable + 2 + 1 + + + RXS + Receive Start Interrupt Disable + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt Disable + 4 + 1 + + + RXBRK + Break Received Interrupt Disable + 5 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + USART_INT Interrupt Enable Set + 0x16 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Enable + 0 + 1 + + + TXC + Transmit Complete Interrupt Enable + 1 + 1 + + + RXC + Receive Complete Interrupt Enable + 2 + 1 + + + RXS + Receive Start Interrupt Enable + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt Enable + 4 + 1 + + + RXBRK + Break Received Interrupt Enable + 5 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + USART_INT Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt + 0 + 1 + + + TXC + Transmit Complete Interrupt + 1 + 1 + + + RXC + Receive Complete Interrupt + 2 + 1 + + + RXS + Receive Start Interrupt + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt + 4 + 1 + + + RXBRK + Break Received Interrupt + 5 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + USART_INT Status + 0x1A + 16 + 0x0000 + + + PERR + Parity Error + 0 + 1 + + + FERR + Frame Error + 1 + 1 + + + BUFOVF + Buffer Overflow + 2 + 1 + + + CTS + Clear To Send + 3 + 1 + + + ISF + Inconsistent Sync Field + 4 + 1 + + + COLL + Collision Detected + 5 + 1 + + + TXE + Transmitter Empty + 6 + 1 + + + + + SYNCBUSY + USART_INT Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + CTRLB + CTRLB Synchronization Busy + 2 + 1 + + + + + DATA + USART_INT Data + 0x28 + 16 + 0x0000 + + + DATA + Data Value + 0 + 9 + + + + + DBGCTRL + USART_INT Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + + + SERCOM1 + 0x42000800 + + SERCOM1 + 10 + + + + SERCOM2 + 0x42000C00 + + SERCOM2 + 11 + + + + SERCOM3 + 0x42001000 + + SERCOM3 + 12 + + + + SERCOM4 + 0x42001400 + + SERCOM4 + 13 + + + + SERCOM5 + 0x42001800 + + SERCOM5 + 14 + + + + SUPC + U21172.1.1 + Supply Controller + SUPC + SUPC_ + 0x40001800 + + 0 + 0x20 + registers + + + + INTENCLR + Interrupt Enable Clear + 0x0 + 32 + 0x00000000 + + + BODVDDRDY + BODVDD Ready + 0 + 1 + + + BODVDDDET + BODVDD Detection + 1 + 1 + + + BVDDSRDY + BODVDD Synchronization Ready + 2 + 1 + + + BODCORERDY + BODCORE Ready + 3 + 1 + + + BODCOREDET + BODCORE Detection + 4 + 1 + + + BCORESRDY + BODCORE Synchronization Ready + 5 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x4 + 32 + 0x00000000 + + + BODVDDRDY + BODVDD Ready + 0 + 1 + + + BODVDDDET + BODVDD Detection + 1 + 1 + + + BVDDSRDY + BODVDD Synchronization Ready + 2 + 1 + + + BODCORERDY + BODCORE Ready + 3 + 1 + + + BODCOREDET + BODCORE Detection + 4 + 1 + + + BCORESRDY + BODCORE Synchronization Ready + 5 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x8 + 32 + 0x00000000 + + + BODVDDRDY + BODVDD Ready + 0 + 1 + + + BODVDDDET + BODVDD Detection + 1 + 1 + + + BVDDSRDY + BODVDD Synchronization Ready + 2 + 1 + + + BODCORERDY + BODCORE Ready + 3 + 1 + + + BODCOREDET + BODCORE Detection + 4 + 1 + + + BCORESRDY + BODCORE Synchronization Ready + 5 + 1 + + + + + STATUS + Power and Clocks Status + 0xC + 32 + read-only + 0x00000000 + + + BODVDDRDY + BODVDD Ready + 0 + 1 + + + BODVDDDET + BODVDD Detection + 1 + 1 + + + BVDDSRDY + BODVDD Synchronization Ready + 2 + 1 + + + BODCORERDY + BODCORE Ready + 3 + 1 + + + BODCOREDET + BODCORE Detection + 4 + 1 + + + BCORESRDY + BODCORE Synchronization Ready + 5 + 1 + + + + + BODVDD + BODVDD Control + 0x10 + 32 + 0x00000000 + + + ENABLE + Enable + 1 + 1 + + + HYST + Hysteresis Enable + 2 + 1 + + + ACTION + Action when Threshold Crossed + 3 + 2 + + ACTIONSelect + + NONE + No action + 0x0 + + + RESET + The BODVDD generates a reset + 0x1 + + + INT + The BODVDD generates an interrupt + 0x2 + + + + + STDBYCFG + Configuration in Standby mode + 5 + 1 + + + RUNSTDBY + Run during Standby + 6 + 1 + + + ACTCFG + Configuration in Active mode + 8 + 1 + + + PSEL + Prescaler Select + 12 + 4 + + PSELSelect + + DIV2 + Divide clock by 2 + 0x0 + + + DIV4 + Divide clock by 4 + 0x1 + + + DIV8 + Divide clock by 8 + 0x2 + + + DIV16 + Divide clock by 16 + 0x3 + + + DIV32 + Divide clock by 32 + 0x4 + + + DIV64 + Divide clock by 64 + 0x5 + + + DIV128 + Divide clock by 128 + 0x6 + + + DIV256 + Divide clock by 256 + 0x7 + + + DIV512 + Divide clock by 512 + 0x8 + + + DIV1024 + Divide clock by 1024 + 0x9 + + + DIV2048 + Divide clock by 2048 + 0xA + + + DIV4096 + Divide clock by 4096 + 0xB + + + DIV8192 + Divide clock by 8192 + 0xC + + + DIV16384 + Divide clock by 16384 + 0xD + + + DIV32768 + Divide clock by 32768 + 0xE + + + DIV65536 + Divide clock by 65536 + 0xF + + + + + LEVEL + Threshold Level for VDD + 16 + 6 + + + + + BODCORE + BODCORE Control + 0x14 + 32 + 0x00000000 + + + ENABLE + Enable + 1 + 1 + + + HYST + Hysteresis Enable + 2 + 1 + + + ACTION + Action when Threshold Crossed + 3 + 2 + + ACTIONSelect + + NONE + No action + 0x0 + + + RESET + The BODCORE generates a reset + 0x1 + + + INT + The BODCORE generates an interrupt + 0x2 + + + + + STDBYCFG + Configuration in Standby mode + 5 + 1 + + + RUNSTDBY + Run during Standby + 6 + 1 + + + ACTCFG + Configuration in Active mode + 8 + 1 + + + PSEL + Prescaler Select + 12 + 4 + + PSELSelect + + DIV2 + Divide clock by 2 + 0x0 + + + DIV4 + Divide clock by 4 + 0x1 + + + DIV8 + Divide clock by 8 + 0x2 + + + DIV16 + Divide clock by 16 + 0x3 + + + DIV32 + Divide clock by 32 + 0x4 + + + DIV64 + Divide clock by 64 + 0x5 + + + DIV128 + Divide clock by 128 + 0x6 + + + DIV256 + Divide clock by 256 + 0x7 + + + DIV512 + Divide clock by 512 + 0x8 + + + DIV1024 + Divide clock by 1024 + 0x9 + + + DIV2048 + Divide clock by 2048 + 0xA + + + DIV4096 + Divide clock by 4096 + 0xB + + + DIV8192 + Divide clock by 8192 + 0xC + + + DIV16384 + Divide clock by 16384 + 0xD + + + DIV32768 + Divide clock by 32768 + 0xE + + + DIV65536 + Divide clock by 65536 + 0xF + + + + + LEVEL + Threshold Level + 16 + 6 + + + + + VREG + VREG Control + 0x18 + 32 + 0x00000000 + + + ENABLE + Enable + 1 + 1 + + + RUNSTDBY + Run during Standby + 6 + 1 + + + + + VREF + VREF Control + 0x1C + 32 + 0x00000000 + + + TSEN + Temperature Sensor Output Enable + 1 + 1 + + + VREFOE + Voltage Reference Output Enable + 2 + 1 + + + RUNSTDBY + Run during Standby + 6 + 1 + + + ONDEMAND + On Demand Contrl + 7 + 1 + + + SEL + Voltage Reference Selection + 16 + 4 + + SELSelect + + 1V024 + 1.024V voltage reference typical value + 0x0 + + + 2V048 + 2.048V voltage reference typical value + 0x2 + + + 4V096 + 4.096V voltage reference typical value + 0x3 + + + + + + + + + TC0 + U22492.0.0 + Basic Timer Counter + TC + TC_ + 0x42003000 + + 0 + 0x38 + registers + + + TC0 + 20 + + + + COUNT8 + 8-bit Counter Mode + TcCount8 + 0x0 + + CTRLA + Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Timer Counter Mode + 2 + 2 + + MODESelect + + COUNT16 + Counter in 16-bit mode + 0 + + + COUNT8 + Counter in 8-bit mode + 1 + + + COUNT32 + Counter in 32-bit mode + 2 + + + + + PRESCSYNC + Prescaler and Counter Synchronization + 4 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset the counter on next generic clock + 0 + + + PRESC + Reload or reset the counter on next prescaler clock + 1 + + + RESYNC + Reload or reset the counter on next generic clock and reset the prescaler counter + 2 + + + + + RUNSTDBY + Run during Standby + 6 + 1 + + + ONDEMAND + Clock On Demand + 7 + 1 + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + Prescaler: GCLK_TC + 0 + + + DIV2 + Prescaler: GCLK_TC/2 + 1 + + + DIV4 + Prescaler: GCLK_TC/4 + 2 + + + DIV8 + Prescaler: GCLK_TC/8 + 3 + + + DIV16 + Prescaler: GCLK_TC/16 + 4 + + + DIV64 + Prescaler: GCLK_TC/64 + 5 + + + DIV256 + Prescaler: GCLK_TC/256 + 6 + + + DIV1024 + Prescaler: GCLK_TC/1024 + 7 + + + + + ALOCK + Auto Lock + 11 + 1 + + + CAPTEN0 + Capture Channel 0 Enable + 16 + 1 + + + CAPTEN1 + Capture Channel 1 Enable + 17 + 1 + + + COPEN0 + Capture On Pin 0 Enable + 20 + 1 + + + COPEN1 + Capture On Pin 1 Enable + 21 + 1 + + + + + CTRLBCLR + Control B Clear + 0x4 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot on Counter + 2 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + UPDATE + Force update of double-buffered register + 3 + + + READSYNC + Force a read synchronization of COUNT + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + CTRLBSET + Control B Set + 0x5 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot on Counter + 2 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + UPDATE + Force update of double-buffered register + 3 + + + READSYNC + Force a read synchronization of COUNT + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + EVCTRL + Event Control + 0x6 + 16 + 0x0000 + + + EVACT + Event Action + 0 + 3 + + EVACTSelect + + OFF + Event action disabled + 0 + + + RETRIGGER + Start, restart or retrigger TC on event + 1 + + + COUNT + Count on event + 2 + + + START + Start TC on event + 3 + + + STAMP + Time stamp capture + 4 + + + PPW + Period catured in CC0, pulse width in CC1 + 5 + + + PWP + Period catured in CC1, pulse width in CC0 + 6 + + + PW + Pulse width capture + 7 + + + + + TCINV + TC Event Input Polarity + 4 + 1 + + + TCEI + TC Event Enable + 5 + 1 + + + OVFEO + Event Output Enable + 8 + 1 + + + MCEO0 + MC Event Output Enable 0 + 12 + 1 + + + MCEO1 + MC Event Output Enable 1 + 13 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x8 + 8 + 0x00 + + + OVF + OVF Interrupt Disable + 0 + 1 + + + ERR + ERR Interrupt Disable + 1 + 1 + + + MC0 + MC Interrupt Disable 0 + 4 + 1 + + + MC1 + MC Interrupt Disable 1 + 5 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x9 + 8 + 0x00 + + + OVF + OVF Interrupt Enable + 0 + 1 + + + ERR + ERR Interrupt Enable + 1 + 1 + + + MC0 + MC Interrupt Enable 0 + 4 + 1 + + + MC1 + MC Interrupt Enable 1 + 5 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0xA + 8 + 0x00 + + + OVF + OVF Interrupt Flag + 0 + 1 + + + ERR + ERR Interrupt Flag + 1 + 1 + + + MC0 + MC Interrupt Flag 0 + 4 + 1 + + + MC1 + MC Interrupt Flag 1 + 5 + 1 + + + + + STATUS + Status + 0xB + 8 + 0x01 + + + STOP + Stop Status Flag + 0 + 1 + + + SLAVE + Slave Status Flag + 1 + 1 + + + PERBUFV + Synchronization Busy Status + 3 + 1 + + + CCBUFV0 + Compare channel buffer 0 valid + 4 + 1 + + + CCBUFV1 + Compare channel buffer 1 valid + 5 + 1 + + + + + WAVE + Waveform Generation Control + 0xC + 8 + 0x00 + + + WAVEGEN + Waveform Generation Mode + 0 + 2 + + WAVEGENSelect + + NFRQ + Normal frequency + 0 + + + MFRQ + Match frequency + 1 + + + NPWM + Normal PWM + 2 + + + MPWM + Match PWM + 3 + + + + + + + DRVCTRL + Control C + 0xD + 8 + 0x00 + + + INVEN0 + Output Waveform Invert Enable 0 + 0 + 1 + + + INVEN1 + Output Waveform Invert Enable 1 + 1 + 1 + + + + + DBGCTRL + Debug Control + 0xF + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + SYNCBUSY + Synchronization Status + 0x10 + 32 + read-only + 0x00000000 + + + SWRST + swrst + 0 + 1 + + + ENABLE + enable + 1 + 1 + + + CTRLB + CTRLB + 2 + 1 + + + STATUS + STATUS + 3 + 1 + + + COUNT + Counter + 4 + 1 + + + PER + Period + 5 + 1 + + + CC0 + Compare Channel 0 + 6 + 1 + + + CC1 + Compare Channel 1 + 7 + 1 + + + + + COUNT + COUNT8 Count + 0x14 + 8 + 0x00 + + + COUNT + Counter Value + 0 + 8 + + + + + PER + COUNT8 Period + 0x1B + 8 + 0xFF + + + PER + Period Value + 0 + 8 + + + + + 2 + 1 + CC[%s] + COUNT8 Compare and Capture + 0x1C + 8 + 0x00 + + + CC + Counter/Compare Value + 0 + 8 + + + + + PERBUF + COUNT8 Period Buffer + 0x2F + 8 + 0xFF + + + PERBUF + Period Buffer Value + 0 + 8 + + + + + 2 + 1 + CCBUF[%s] + COUNT8 Compare and Capture Buffer + 0x30 + 8 + 0x00 + + + CCBUF + Counter/Compare Buffer Value + 0 + 8 + + + + + + COUNT16 + 16-bit Counter Mode + COUNT8 + TcCount16 + 0x0 + + CTRLA + Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Timer Counter Mode + 2 + 2 + + MODESelect + + COUNT16 + Counter in 16-bit mode + 0 + + + COUNT8 + Counter in 8-bit mode + 1 + + + COUNT32 + Counter in 32-bit mode + 2 + + + + + PRESCSYNC + Prescaler and Counter Synchronization + 4 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset the counter on next generic clock + 0 + + + PRESC + Reload or reset the counter on next prescaler clock + 1 + + + RESYNC + Reload or reset the counter on next generic clock and reset the prescaler counter + 2 + + + + + RUNSTDBY + Run during Standby + 6 + 1 + + + ONDEMAND + Clock On Demand + 7 + 1 + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + Prescaler: GCLK_TC + 0 + + + DIV2 + Prescaler: GCLK_TC/2 + 1 + + + DIV4 + Prescaler: GCLK_TC/4 + 2 + + + DIV8 + Prescaler: GCLK_TC/8 + 3 + + + DIV16 + Prescaler: GCLK_TC/16 + 4 + + + DIV64 + Prescaler: GCLK_TC/64 + 5 + + + DIV256 + Prescaler: GCLK_TC/256 + 6 + + + DIV1024 + Prescaler: GCLK_TC/1024 + 7 + + + + + ALOCK + Auto Lock + 11 + 1 + + + CAPTEN0 + Capture Channel 0 Enable + 16 + 1 + + + CAPTEN1 + Capture Channel 1 Enable + 17 + 1 + + + COPEN0 + Capture On Pin 0 Enable + 20 + 1 + + + COPEN1 + Capture On Pin 1 Enable + 21 + 1 + + + + + CTRLBCLR + Control B Clear + 0x4 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot on Counter + 2 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + UPDATE + Force update of double-buffered register + 3 + + + READSYNC + Force a read synchronization of COUNT + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + CTRLBSET + Control B Set + 0x5 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot on Counter + 2 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + UPDATE + Force update of double-buffered register + 3 + + + READSYNC + Force a read synchronization of COUNT + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + EVCTRL + Event Control + 0x6 + 16 + 0x0000 + + + EVACT + Event Action + 0 + 3 + + EVACTSelect + + OFF + Event action disabled + 0 + + + RETRIGGER + Start, restart or retrigger TC on event + 1 + + + COUNT + Count on event + 2 + + + START + Start TC on event + 3 + + + STAMP + Time stamp capture + 4 + + + PPW + Period catured in CC0, pulse width in CC1 + 5 + + + PWP + Period catured in CC1, pulse width in CC0 + 6 + + + PW + Pulse width capture + 7 + + + + + TCINV + TC Event Input Polarity + 4 + 1 + + + TCEI + TC Event Enable + 5 + 1 + + + OVFEO + Event Output Enable + 8 + 1 + + + MCEO0 + MC Event Output Enable 0 + 12 + 1 + + + MCEO1 + MC Event Output Enable 1 + 13 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x8 + 8 + 0x00 + + + OVF + OVF Interrupt Disable + 0 + 1 + + + ERR + ERR Interrupt Disable + 1 + 1 + + + MC0 + MC Interrupt Disable 0 + 4 + 1 + + + MC1 + MC Interrupt Disable 1 + 5 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x9 + 8 + 0x00 + + + OVF + OVF Interrupt Enable + 0 + 1 + + + ERR + ERR Interrupt Enable + 1 + 1 + + + MC0 + MC Interrupt Enable 0 + 4 + 1 + + + MC1 + MC Interrupt Enable 1 + 5 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0xA + 8 + 0x00 + + + OVF + OVF Interrupt Flag + 0 + 1 + + + ERR + ERR Interrupt Flag + 1 + 1 + + + MC0 + MC Interrupt Flag 0 + 4 + 1 + + + MC1 + MC Interrupt Flag 1 + 5 + 1 + + + + + STATUS + Status + 0xB + 8 + 0x01 + + + STOP + Stop Status Flag + 0 + 1 + + + SLAVE + Slave Status Flag + 1 + 1 + + + PERBUFV + Synchronization Busy Status + 3 + 1 + + + CCBUFV0 + Compare channel buffer 0 valid + 4 + 1 + + + CCBUFV1 + Compare channel buffer 1 valid + 5 + 1 + + + + + WAVE + Waveform Generation Control + 0xC + 8 + 0x00 + + + WAVEGEN + Waveform Generation Mode + 0 + 2 + + WAVEGENSelect + + NFRQ + Normal frequency + 0 + + + MFRQ + Match frequency + 1 + + + NPWM + Normal PWM + 2 + + + MPWM + Match PWM + 3 + + + + + + + DRVCTRL + Control C + 0xD + 8 + 0x00 + + + INVEN0 + Output Waveform Invert Enable 0 + 0 + 1 + + + INVEN1 + Output Waveform Invert Enable 1 + 1 + 1 + + + + + DBGCTRL + Debug Control + 0xF + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + SYNCBUSY + Synchronization Status + 0x10 + 32 + read-only + 0x00000000 + + + SWRST + swrst + 0 + 1 + + + ENABLE + enable + 1 + 1 + + + CTRLB + CTRLB + 2 + 1 + + + STATUS + STATUS + 3 + 1 + + + COUNT + Counter + 4 + 1 + + + PER + Period + 5 + 1 + + + CC0 + Compare Channel 0 + 6 + 1 + + + CC1 + Compare Channel 1 + 7 + 1 + + + + + COUNT + COUNT16 Count + 0x14 + 16 + 0x0000 + + + COUNT + Counter Value + 0 + 16 + + + + + 2 + 2 + CC[%s] + COUNT16 Compare and Capture + 0x1C + 16 + 0x0000 + + + CC + Counter/Compare Value + 0 + 16 + + + + + 2 + 2 + CCBUF[%s] + COUNT16 Compare and Capture Buffer + 0x30 + 16 + 0x0000 + + + CCBUF + Counter/Compare Buffer Value + 0 + 16 + + + + + + COUNT32 + 32-bit Counter Mode + COUNT8 + TcCount32 + 0x0 + + CTRLA + Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Timer Counter Mode + 2 + 2 + + MODESelect + + COUNT16 + Counter in 16-bit mode + 0 + + + COUNT8 + Counter in 8-bit mode + 1 + + + COUNT32 + Counter in 32-bit mode + 2 + + + + + PRESCSYNC + Prescaler and Counter Synchronization + 4 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset the counter on next generic clock + 0 + + + PRESC + Reload or reset the counter on next prescaler clock + 1 + + + RESYNC + Reload or reset the counter on next generic clock and reset the prescaler counter + 2 + + + + + RUNSTDBY + Run during Standby + 6 + 1 + + + ONDEMAND + Clock On Demand + 7 + 1 + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + Prescaler: GCLK_TC + 0 + + + DIV2 + Prescaler: GCLK_TC/2 + 1 + + + DIV4 + Prescaler: GCLK_TC/4 + 2 + + + DIV8 + Prescaler: GCLK_TC/8 + 3 + + + DIV16 + Prescaler: GCLK_TC/16 + 4 + + + DIV64 + Prescaler: GCLK_TC/64 + 5 + + + DIV256 + Prescaler: GCLK_TC/256 + 6 + + + DIV1024 + Prescaler: GCLK_TC/1024 + 7 + + + + + ALOCK + Auto Lock + 11 + 1 + + + CAPTEN0 + Capture Channel 0 Enable + 16 + 1 + + + CAPTEN1 + Capture Channel 1 Enable + 17 + 1 + + + COPEN0 + Capture On Pin 0 Enable + 20 + 1 + + + COPEN1 + Capture On Pin 1 Enable + 21 + 1 + + + + + CTRLBCLR + Control B Clear + 0x4 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot on Counter + 2 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + UPDATE + Force update of double-buffered register + 3 + + + READSYNC + Force a read synchronization of COUNT + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + CTRLBSET + Control B Set + 0x5 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot on Counter + 2 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + UPDATE + Force update of double-buffered register + 3 + + + READSYNC + Force a read synchronization of COUNT + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + EVCTRL + Event Control + 0x6 + 16 + 0x0000 + + + EVACT + Event Action + 0 + 3 + + EVACTSelect + + OFF + Event action disabled + 0 + + + RETRIGGER + Start, restart or retrigger TC on event + 1 + + + COUNT + Count on event + 2 + + + START + Start TC on event + 3 + + + STAMP + Time stamp capture + 4 + + + PPW + Period catured in CC0, pulse width in CC1 + 5 + + + PWP + Period catured in CC1, pulse width in CC0 + 6 + + + PW + Pulse width capture + 7 + + + + + TCINV + TC Event Input Polarity + 4 + 1 + + + TCEI + TC Event Enable + 5 + 1 + + + OVFEO + Event Output Enable + 8 + 1 + + + MCEO0 + MC Event Output Enable 0 + 12 + 1 + + + MCEO1 + MC Event Output Enable 1 + 13 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x8 + 8 + 0x00 + + + OVF + OVF Interrupt Disable + 0 + 1 + + + ERR + ERR Interrupt Disable + 1 + 1 + + + MC0 + MC Interrupt Disable 0 + 4 + 1 + + + MC1 + MC Interrupt Disable 1 + 5 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x9 + 8 + 0x00 + + + OVF + OVF Interrupt Enable + 0 + 1 + + + ERR + ERR Interrupt Enable + 1 + 1 + + + MC0 + MC Interrupt Enable 0 + 4 + 1 + + + MC1 + MC Interrupt Enable 1 + 5 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0xA + 8 + 0x00 + + + OVF + OVF Interrupt Flag + 0 + 1 + + + ERR + ERR Interrupt Flag + 1 + 1 + + + MC0 + MC Interrupt Flag 0 + 4 + 1 + + + MC1 + MC Interrupt Flag 1 + 5 + 1 + + + + + STATUS + Status + 0xB + 8 + 0x01 + + + STOP + Stop Status Flag + 0 + 1 + + + SLAVE + Slave Status Flag + 1 + 1 + + + PERBUFV + Synchronization Busy Status + 3 + 1 + + + CCBUFV0 + Compare channel buffer 0 valid + 4 + 1 + + + CCBUFV1 + Compare channel buffer 1 valid + 5 + 1 + + + + + WAVE + Waveform Generation Control + 0xC + 8 + 0x00 + + + WAVEGEN + Waveform Generation Mode + 0 + 2 + + WAVEGENSelect + + NFRQ + Normal frequency + 0 + + + MFRQ + Match frequency + 1 + + + NPWM + Normal PWM + 2 + + + MPWM + Match PWM + 3 + + + + + + + DRVCTRL + Control C + 0xD + 8 + 0x00 + + + INVEN0 + Output Waveform Invert Enable 0 + 0 + 1 + + + INVEN1 + Output Waveform Invert Enable 1 + 1 + 1 + + + + + DBGCTRL + Debug Control + 0xF + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + SYNCBUSY + Synchronization Status + 0x10 + 32 + read-only + 0x00000000 + + + SWRST + swrst + 0 + 1 + + + ENABLE + enable + 1 + 1 + + + CTRLB + CTRLB + 2 + 1 + + + STATUS + STATUS + 3 + 1 + + + COUNT + Counter + 4 + 1 + + + PER + Period + 5 + 1 + + + CC0 + Compare Channel 0 + 6 + 1 + + + CC1 + Compare Channel 1 + 7 + 1 + + + + + COUNT + COUNT32 Count + 0x14 + 32 + 0x00000000 + + + COUNT + Counter Value + 0 + 32 + + + + + 2 + 4 + CC[%s] + COUNT32 Compare and Capture + 0x1C + 32 + 0x00000000 + + + CC + Counter/Compare Value + 0 + 32 + + + + + 2 + 4 + CCBUF[%s] + COUNT32 Compare and Capture Buffer + 0x30 + 32 + 0x00000000 + + + CCBUF + Counter/Compare Buffer Value + 0 + 32 + + + + + + + + TC1 + 0x42003400 + + TC1 + 21 + + + + TC2 + 0x42003800 + + TC2 + 22 + + + + TC3 + 0x42003C00 + + TC3 + 23 + + + + TC4 + 0x42004000 + + TC4 + 24 + + + + TCC0 + U22133.0.0 + Timer Counter Control + TCC + TCC_ + 0x42002400 + + 0 + 0x80 + registers + + + TCC0 + 17 + + + + CTRLA + Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + RESOLUTION + Enhanced Resolution + 5 + 2 + + RESOLUTIONSelect + + NONE + Dithering is disabled + 0 + + + DITH4 + Dithering is done every 16 PWM frames + 1 + + + DITH5 + Dithering is done every 32 PWM frames + 2 + + + DITH6 + Dithering is done every 64 PWM frames + 3 + + + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + No division + 0 + + + DIV2 + Divide by 2 + 1 + + + DIV4 + Divide by 4 + 2 + + + DIV8 + Divide by 8 + 3 + + + DIV16 + Divide by 16 + 4 + + + DIV64 + Divide by 64 + 5 + + + DIV256 + Divide by 256 + 6 + + + DIV1024 + Divide by 1024 + 7 + + + + + RUNSTDBY + Run in Standby + 11 + 1 + + + PRESCSYNC + Prescaler and Counter Synchronization Selection + 12 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset counter on next GCLK + 0 + + + PRESC + Reload or reset counter on next prescaler clock + 1 + + + RESYNC + Reload or reset counter on next GCLK and reset prescaler counter + 2 + + + + + ALOCK + Auto Lock + 14 + 1 + + + MSYNC + Master Synchronization (only for TCC Slave Instance) + 15 + 1 + + + DMAOS + DMA One-shot Trigger Mode + 23 + 1 + + + CPTEN0 + Capture Channel 0 Enable + 24 + 1 + + + CPTEN1 + Capture Channel 1 Enable + 25 + 1 + + + CPTEN2 + Capture Channel 2 Enable + 26 + 1 + + + CPTEN3 + Capture Channel 3 Enable + 27 + 1 + + + + + CTRLBCLR + Control B Clear + 0x4 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + IDXCMD + Ramp Index Command + 3 + 2 + + IDXCMDSelect + + DISABLE + Command disabled: Index toggles between cycles A and B + 0 + + + SET + Set index: cycle B will be forced in the next cycle + 1 + + + CLEAR + Clear index: cycle A will be forced in the next cycle + 2 + + + HOLD + Hold index: the next cycle will be the same as the current cycle + 3 + + + + + CMD + TCC Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Clear start, restart or retrigger + 1 + + + STOP + Force stop + 2 + + + UPDATE + Force update or double buffered registers + 3 + + + READSYNC + Force COUNT read synchronization + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + CTRLBSET + Control B Set + 0x5 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + IDXCMD + Ramp Index Command + 3 + 2 + + IDXCMDSelect + + DISABLE + Command disabled: Index toggles between cycles A and B + 0 + + + SET + Set index: cycle B will be forced in the next cycle + 1 + + + CLEAR + Clear index: cycle A will be forced in the next cycle + 2 + + + HOLD + Hold index: the next cycle will be the same as the current cycle + 3 + + + + + CMD + TCC Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Clear start, restart or retrigger + 1 + + + STOP + Force stop + 2 + + + UPDATE + Force update or double buffered registers + 3 + + + READSYNC + Force COUNT read synchronization + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + SYNCBUSY + Synchronization Busy + 0x8 + 32 + read-only + 0x00000000 + + + SWRST + Swrst Busy + 0 + 1 + + + ENABLE + Enable Busy + 1 + 1 + + + CTRLB + Ctrlb Busy + 2 + 1 + + + STATUS + Status Busy + 3 + 1 + + + COUNT + Count Busy + 4 + 1 + + + PATT + Pattern Busy + 5 + 1 + + + WAVE + Wave Busy + 6 + 1 + + + PER + Period Busy + 7 + 1 + + + CC0 + Compare Channel 0 Busy + 8 + 1 + + + CC1 + Compare Channel 1 Busy + 9 + 1 + + + CC2 + Compare Channel 2 Busy + 10 + 1 + + + CC3 + Compare Channel 3 Busy + 11 + 1 + + + + + FCTRLA + Recoverable Fault A Configuration + 0xC + 32 + 0x00000000 + + + SRC + Fault A Source + 0 + 2 + + SRCSelect + + DISABLE + Fault input disabled + 0 + + + ENABLE + MCEx (x=0,1) event input + 1 + + + INVERT + Inverted MCEx (x=0,1) event input + 2 + + + ALTFAULT + Alternate fault (A or B) state at the end of the previous period + 3 + + + + + KEEP + Fault A Keeper + 3 + 1 + + + QUAL + Fault A Qualification + 4 + 1 + + + BLANK + Fault A Blanking Mode + 5 + 2 + + BLANKSelect + + START + Blanking applied from start of the ramp + 0 + + + RISE + Blanking applied from rising edge of the output waveform + 1 + + + FALL + Blanking applied from falling edge of the output waveform + 2 + + + BOTH + Blanking applied from each toggle of the output waveform + 3 + + + + + RESTART + Fault A Restart + 7 + 1 + + + HALT + Fault A Halt Mode + 8 + 2 + + HALTSelect + + DISABLE + Halt action disabled + 0 + + + HW + Hardware halt action + 1 + + + SW + Software halt action + 2 + + + NR + Non-recoverable fault + 3 + + + + + CHSEL + Fault A Capture Channel + 10 + 2 + + CHSELSelect + + CC0 + Capture value stored in channel 0 + 0 + + + CC1 + Capture value stored in channel 1 + 1 + + + CC2 + Capture value stored in channel 2 + 2 + + + CC3 + Capture value stored in channel 3 + 3 + + + + + CAPTURE + Fault A Capture Action + 12 + 3 + + CAPTURESelect + + DISABLE + No capture + 0 + + + CAPT + Capture on fault + 1 + + + CAPTMIN + Minimum capture + 2 + + + CAPTMAX + Maximum capture + 3 + + + LOCMIN + Minimum local detection + 4 + + + LOCMAX + Maximum local detection + 5 + + + DERIV0 + Minimum and maximum local detection + 6 + + + CAPTMARK + Capture with ramp index as MSB value + 7 + + + + + BLANKPRESC + Fault A Blanking Prescaler + 15 + 1 + + + BLANKVAL + Fault A Blanking Time + 16 + 8 + + + FILTERVAL + Fault A Filter Value + 24 + 4 + + + + + FCTRLB + Recoverable Fault B Configuration + 0x10 + 32 + 0x00000000 + + + SRC + Fault B Source + 0 + 2 + + SRCSelect + + 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12 + 1 + + + NRV5 + Non-Recoverable State 5 Output Value + 13 + 1 + + + NRV6 + Non-Recoverable State 6 Output Value + 14 + 1 + + + NRV7 + Non-Recoverable State 7 Output Value + 15 + 1 + + + INVEN0 + Output Waveform 0 Inversion + 16 + 1 + + + INVEN1 + Output Waveform 1 Inversion + 17 + 1 + + + INVEN2 + Output Waveform 2 Inversion + 18 + 1 + + + INVEN3 + Output Waveform 3 Inversion + 19 + 1 + + + INVEN4 + Output Waveform 4 Inversion + 20 + 1 + + + INVEN5 + Output Waveform 5 Inversion + 21 + 1 + + + INVEN6 + Output Waveform 6 Inversion + 22 + 1 + + + INVEN7 + Output Waveform 7 Inversion + 23 + 1 + + + FILTERVAL0 + Non-Recoverable Fault Input 0 Filter Value + 24 + 4 + + + FILTERVAL1 + Non-Recoverable Fault Input 1 Filter Value + 28 + 4 + + + + + DBGCTRL + Debug Control + 0x1E + 8 + 0x00 + + + DBGRUN + Debug Running Mode + 0 + 1 + + + FDDBD + Fault Detection on Debug Break Detection + 2 + 1 + + + + + EVCTRL + Event Control + 0x20 + 32 + 0x00000000 + + + EVACT0 + Timer/counter Input Event0 Action + 0 + 3 + + EVACT0Select + + OFF + Event action disabled + 0 + + + RETRIGGER + Start, restart or re-trigger counter on event + 1 + + + COUNTEV + Count on event + 2 + + + START + Start counter on event + 3 + + + INC + Increment counter on event + 4 + + + COUNT + Count on active state of asynchronous event + 5 + + + STAMP + Stamp capture + 6 + + + FAULT + Non-recoverable fault + 7 + + + + + EVACT1 + Timer/counter Input Event1 Action + 3 + 3 + + EVACT1Select + + OFF + Event action disabled + 0 + + + RETRIGGER + Re-trigger counter on event + 1 + + + DIR + Direction control + 2 + + + STOP + Stop counter on event + 3 + + + DEC + Decrement counter on event + 4 + + + PPW + Period capture value in CC0 register, pulse width capture value in CC1 register + 5 + + + PWP + Period capture value in CC1 register, pulse width capture value in CC0 register + 6 + + + FAULT + Non-recoverable fault + 7 + + + + + CNTSEL + Timer/counter Output Event Mode + 6 + 2 + + CNTSELSelect + + START + An interrupt/event is generated when a new counter cycle starts + 0 + + + END + An interrupt/event is generated when a counter cycle ends + 1 + + + BETWEEN + An interrupt/event is generated when a counter cycle ends, except for the first and last cycles + 2 + + + BOUNDARY + An interrupt/event is generated when a new counter cycle starts or a counter cycle ends + 3 + + + + + OVFEO + Overflow/Underflow Output Event Enable + 8 + 1 + + + TRGEO + Retrigger Output Event Enable + 9 + 1 + + + CNTEO + Timer/counter Output Event Enable + 10 + 1 + + + TCINV0 + Inverted Event 0 Input Enable + 12 + 1 + + + TCINV1 + Inverted Event 1 Input Enable + 13 + 1 + + + TCEI0 + Timer/counter Event 0 Input Enable + 14 + 1 + + + TCEI1 + Timer/counter Event 1 Input Enable + 15 + 1 + + + MCEI0 + Match or Capture Channel 0 Event Input Enable + 16 + 1 + + + MCEI1 + Match or Capture Channel 1 Event Input Enable + 17 + 1 + + + MCEI2 + Match or Capture Channel 2 Event Input Enable + 18 + 1 + + + MCEI3 + Match or Capture Channel 3 Event Input Enable + 19 + 1 + + + MCEO0 + Match or Capture Channel 0 Event Output Enable + 24 + 1 + + + MCEO1 + Match or Capture Channel 1 Event Output Enable + 25 + 1 + + + MCEO2 + Match or Capture Channel 2 Event Output Enable + 26 + 1 + + + MCEO3 + Match or Capture Channel 3 Event Output Enable + 27 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x24 + 32 + 0x00000000 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + TRG + Retrigger Interrupt Enable + 1 + 1 + + + CNT + Counter Interrupt Enable + 2 + 1 + + + ERR + Error Interrupt Enable + 3 + 1 + + + UFS + Non-Recoverable Update Fault Interrupt Enable + 10 + 1 + + + DFS + Non-Recoverable Debug Fault Interrupt Enable + 11 + 1 + + + FAULTA + Recoverable Fault A Interrupt Enable + 12 + 1 + + + FAULTB + Recoverable Fault B Interrupt Enable + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 Interrupt Enable + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 Interrupt Enable + 15 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 16 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 17 + 1 + + + MC2 + Match or Capture Channel 2 Interrupt Enable + 18 + 1 + + + MC3 + Match or Capture Channel 3 Interrupt Enable + 19 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x28 + 32 + 0x00000000 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + TRG + Retrigger Interrupt Enable + 1 + 1 + + + CNT + Counter Interrupt Enable + 2 + 1 + + + ERR + Error Interrupt Enable + 3 + 1 + + + UFS + Non-Recoverable Update Fault Interrupt Enable + 10 + 1 + + + DFS + Non-Recoverable Debug Fault Interrupt Enable + 11 + 1 + + + FAULTA + Recoverable Fault A Interrupt Enable + 12 + 1 + + + FAULTB + Recoverable Fault B Interrupt Enable + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 Interrupt Enable + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 Interrupt Enable + 15 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 16 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 17 + 1 + + + MC2 + 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clock cycles + 0x7 + + + CYC2048 + 2048 clock cycles + 0x8 + + + CYC4096 + 4096 clock cycles + 0x9 + + + CYC8192 + 8192 clock cycles + 0xA + + + CYC16384 + 16384 clock cycles + 0xB + + + + + WINDOW + Window Mode Time-Out Period + 4 + 4 + + WINDOWSelect + + CYC8 + 8 clock cycles + 0x0 + + + CYC16 + 16 clock cycles + 0x1 + + + CYC32 + 32 clock cycles + 0x2 + + + CYC64 + 64 clock cycles + 0x3 + + + CYC128 + 128 clock cycles + 0x4 + + + CYC256 + 256 clock cycles + 0x5 + + + CYC512 + 512 clock cycles + 0x6 + + + CYC1024 + 1024 clock cycles + 0x7 + + + CYC2048 + 2048 clock cycles + 0x8 + + + CYC4096 + 4096 clock cycles + 0x9 + + + CYC8192 + 8192 clock cycles + 0xA + + + CYC16384 + 16384 clock cycles + 0xB + + + + + + + EWCTRL + Early Warning Interrupt Control + 0x2 + 8 + 0x0B + + + EWOFFSET + Early Warning Interrupt Time Offset + 0 + 4 + + EWOFFSETSelect + + CYC8 + 8 clock cycles + 0x0 + + + CYC16 + 16 clock cycles + 0x1 + + + CYC32 + 32 clock cycles + 0x2 + + + CYC64 + 64 clock cycles + 0x3 + + + CYC128 + 128 clock cycles + 0x4 + + + CYC256 + 256 clock cycles + 0x5 + + + CYC512 + 512 clock cycles + 0x6 + + + CYC1024 + 1024 clock cycles + 0x7 + + + CYC2048 + 2048 clock cycles + 0x8 + + + CYC4096 + 4096 clock cycles + 0x9 + + + CYC8192 + 8192 clock cycles + 0xA + + + CYC16384 + 16384 clock cycles + 0xB + + + + + + + INTENCLR + Interrupt Enable Clear + 0x4 + 8 + 0x00 + + + EW + Early Warning Interrupt Enable + 0 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x5 + 8 + 0x00 + + + EW + Early Warning Interrupt Enable + 0 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x6 + 8 + 0x00 + + + EW + Early Warning + 0 + 1 + + + + + SYNCBUSY + Synchronization Busy + 0x8 + 32 + read-only + 0x00000000 + + + ENABLE + Enable Busy + 1 + 1 + + + WEN + Window Enable Busy + 2 + 1 + + + ALWAYSON + Always-On Busy + 3 + 1 + + + CLEAR + Clear Busy + 4 + 1 + + + + + CLEAR + Clear + 0xC + 8 + write-only + 0x00 + + + CLEAR + Watchdog Clear + 0 + 8 + + CLEARSelect + + KEY + Clear Key + 0xA5 + + + + + + + + + MPU + Memory Protection Unit + MPU + MPU_ + 0xE000ED90 + + 0 + 0x14 + registers + + + + TYPE + MPU Type Register + 0x0 + 32 + read-only + + + SEPARATE + Separate instruction and Data Memory MapsRegions + 0 + 1 + + + DREGION + Number of Data Regions + 8 + 8 + + + IREGION + Number of Instruction Regions + 16 + 8 + + + + + CTRL + MPU Control Register + 0x4 + 32 + + + ENABLE + MPU Enable + 0 + 1 + + + HFNMIENA + Enable Hard Fault and NMI handlers + 1 + 1 + + + PRIVDEFENA + Enables privileged software access to default memory map + 2 + 1 + + + + + RNR + MPU Region Number Register + 0x8 + 32 + + + REGION + Region referenced by RBAR and RASR + 0 + 8 + + + + + RBAR + MPU Region Base Address Register + 0xC + 32 + + + REGION + Region number + 0 + 4 + + + VALID + Region number valid + 4 + 1 + + + ADDR + Region base address + 5 + 27 + + + + + RASR + MPU Region Attribute and Size Register + 0x10 + 32 + + + ENABLE + Region Enable + 0 + 1 + + + SIZE + Region Size + 1 + 5 + + + SRD + Sub-region disable + 8 + 8 + + + B + Bufferable bit + 16 + 1 + + + C + Cacheable bit + 17 + 1 + + + S + Shareable bit + 18 + 1 + + + TEX + TEX bit + 19 + 3 + + + AP + Access Permission + 24 + 3 + + + XN + Execute Never Attribute + 28 + 1 + + + + + + + NVIC + Nested Vectored Interrupt Controller + NVIC + NVIC_ + 0xE000E100 + + 0 + 0x320 + registers + + + + ISER + Interrupt Set Enable Register + 0x0 + 32 + 0x00000000 + + + SETENA + Interrupt set enable bits + 0 + 31 + + + + + ICER + Interrupt Clear Enable Register + 0x80 + 32 + 0x00000000 + + + CLRENA + Interrupt clear-enable bits + 0 + 31 + + + + + ISPR + Interrupt Set Pending Register + 0x100 + 32 + 0x00000000 + + + SETPEND + Interrupt set-pending bits + 0 + 31 + + + + + ICPR + Interrupt Clear Pending Register + 0x180 + 32 + 0x00000000 + + + CLRPEND + Interrupt clear-pending bits + 0 + 31 + + + + + 8 + 4 + IPR[%s] + Interrupt Priority Register n + 0x300 + 32 + 0x00000000 + + + PRI0 + Priority of interrupt n + 0 + 2 + + + PRI1 + Priority of interrupt n + 8 + 2 + + + PRI2 + Priority of interrupt n + 16 + 2 + + + PRI3 + Priority of interrupt n + 24 + 2 + + + + + + + SysTick + System timer + SysTick + SysTick_ + 0xE000E010 + + 0 + 0x10 + registers + + + + CSR + SysTick Control and Status Register + 0x0 + 32 + 0x4 + + + ENABLE + SysTick Counter Enable + 0 + 1 + + ENABLESelect + + VALUE_0 + Counter disabled + 0 + + + VALUE_1 + Counter enabled + 1 + + + + + TICKINT + SysTick Exception Request Enable + 1 + 1 + + TICKINTSelect + + VALUE_0 + Counting down to 0 does not assert the SysTick exception request + 0 + + + VALUE_1 + Counting down to 0 asserts the SysTick exception request + 1 + + + + + CLKSOURCE + Clock Source 0=external, 1=processor + 2 + 1 + + CLKSOURCESelect + + VALUE_0 + External clock + 0 + + + VALUE_1 + Processor clock + 1 + + + + + COUNTFLAG + Timer counted to 0 since last read of register + 16 + 1 + + + + + RVR + SysTick Reload Value Register + 0x4 + 32 + + + RELOAD + Value to load into the SysTick Current Value Register when the counter reaches 0 + 0 + 24 + + + + + CVR + SysTick Current Value Register + 0x8 + 32 + + + CURRENT + Current value at the time the register is accessed + 0 + 24 + + + + + CALIB + SysTick Calibration Value Register + 0xC + 32 + read-only + 0 + + + TENMS + Reload value to use for 10ms timing + 0 + 24 + + + SKEW + TENMS is rounded from non-integer ratio + 30 + 1 + + SKEWSelect + + VALUE_0 + 10ms calibration value is exact + 0 + + + VALUE_1 + 10ms calibration value is inexact, because of the clock frequency + 1 + + + + + NOREF + No Separate Reference Clock + 31 + 1 + + NOREFSelect + + VALUE_0 + The reference clock is provided + 0 + + + VALUE_1 + The reference clock is not provided + 1 + + + + + + + + + SystemControl + System Control Registers + SystemControl + SystemControl_ + 0xE000E000 + + 0 + 0xD34 + registers + + + + CPUID + CPUID Base Register + 0xD00 + 32 + read-only + 0x410CC601 + + + REVISION + Minor revision number + 0 + 4 + + + PARTNO + Processor Part Number, 0xC60=Cortex-M0+ + 4 + 12 + + + ARCHITECTURE + Processor Architecture, 0xC=ARMv6-M + 16 + 4 + + + VARIANT + Major revision number + 20 + 4 + + + IMPLEMENTER + Implementer code, ARM=0x41 + 24 + 8 + + + + + ICSR + Interrupt Control and State Register + 0xD04 + 32 + 0x00000000 + + + VECTACTIVE + Debug: Exception number of currently executing exception, or 0 if thread mode + 0 + 9 + + + VECTPENDING + Exception number of the highest priority pending enabled exception + 12 + 9 + + + ISRPENDING + Debug: NVIC interrupt pending + 22 + 1 + + + ISRPREEMPT + Debug: Pending exception serviced on exit from debug halt + 23 + 1 + + + PENDSTCLR + SysTick exception clear-pending bit + 25 + 1 + + PENDSTCLRSelect + + VALUE_0 + No effect + 0 + + + VALUE_1 + Removes the pending state from the SysTick exception + 1 + + + + + PENDSTSET + SysTick exception set-pending bit + 26 + 1 + + PENDSTSETSelect + + VALUE_0 + Write: no effect; read: SysTick exception is not pending + 0 + + + VALUE_1 + Write: changes SysTick exception state to pending; read: SysTick exception is pending + 1 + + + + + PENDSVCLR + PendSV clear-pending bit + 27 + 1 + + PENDSVCLRSelect + + VALUE_0 + No effect + 0 + + + VALUE_1 + Removes the pending state from the PendSV exception + 1 + + + + + PENDSVSET + PendSV set-pending bit + 28 + 1 + + PENDSVSETSelect + + VALUE_0 + Write: no effect; read: PendSV exception is not pending + 0 + + + VALUE_1 + Write: changes PendSV exception state to pending; read: PendSV exception is pending + 1 + + + + + NMIPENDSET + NMI set-pending bit + 31 + 1 + + NMIPENDSETSelect + + VALUE_0 + Write: no effect; read: NMI exception is not pending + 0 + + + VALUE_1 + Write: changes NMI exception state to pending; read: NMI exception is pending + 1 + + + + + + + VTOR + Vector Table Offset Register + 0xD08 + 32 + 0x00000000 + + + TBLOFF + Vector table base offset + 7 + 25 + + + + + AIRCR + Application Interrupt and Reset Control Register + 0xD0C + 32 + 0x00000000 + + + VECTCLRACTIVE + Debug: Clear state information + 1 + 1 + + + SYSRESETREQ + System Reset Request + 2 + 1 + + SYSRESETREQSelect + + VALUE_0 + No system reset request + 0 + + + VALUE_1 + Asserts a signal to the outer system that requests a reset + 1 + + + + + ENDIANNESS + Data Endianness, 0=little, 1=big + 15 + 1 + + ENDIANNESSSelect + + VALUE_0 + Little-endian + 0 + + + VALUE_1 + Big-endian + 1 + + + + + VECTKEY + Register key (0x05FA) + 16 + 16 + + + + + SCR + System Control Register + 0xD10 + 32 + 0x00000000 + + + SLEEPONEXIT + Sleep-On-Exit when exiting Handler mode + 1 + 1 + + SLEEPONEXITSelect + + VALUE_0 + O not sleep when returning to Thread mode + 0 + + + VALUE_1 + Enter sleep, or deep sleep, on return from an ISR + 1 + + + + + SLEEPDEEP + Uses Deep Sleep as low power mode + 2 + 1 + + SLEEPDEEPSelect + + VALUE_0 + Sleep + 0 + + + VALUE_1 + Deep sleep + 1 + + + + + SEVONPEND + Send Event on Pending bit + 4 + 1 + + SEVONPENDSelect + + VALUE_0 + Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded + 0 + + + VALUE_1 + Enabled events and all interrupts, including disabled interrupts, can wakeup the processor + 1 + + + + + + + CCR + Configuration and Control Register + 0xD14 + 32 + read-only + 0x00000204 + + + UNALIGN_TRP + Unaligned accesses generates a Hard Fault + 3 + 1 + + UNALIGN_TRPSelect + + VALUE_0 + Do not trap unaligned halfword and word accesses + 0 + + + VALUE_1 + Trap unaligned halfword and word accesses + 1 + + + + + STKALIGN + Stack 8-byte aligned on exception entry + 9 + 1 + + STKALIGNSelect + + VALUE_0 + 4-byte aligned + 0 + + + VALUE_1 + 8-byte aligned + 1 + + + + + + + SHPR2 + System Handler Priority Register 2 + 0xD1C + 32 + 0x00000000 + + + PRI_11 + Priority of system handler 11, SVCall + 24 + 8 + + + + + SHPR3 + System Handler Priority Register 3 + 0xD20 + 32 + 0x00000000 + + + PRI_14 + Priority of system handler 14, PendSV + 16 + 8 + + + PRI_15 + Priority of system handler 15, SysTick exception + 24 + 8 + + + + + SHCSR + System Handler Control and State Register + 0xD24 + 32 + 0x00000000 + + + SVCALLPENDED + 15 + 1 + + + + + DFSR + Debug Fault Status Register + 0xD30 + 32 + 0x00000000 + + + HALTED + Halt request debug event active + 0 + 1 + + + BKPT + Breakpoint debug event + 1 + 1 + + + DWTTRAP + DWT debug event + 2 + 1 + + + VCATCH + Vector catch debug event + 3 + 1 + + + EXTERNAL + EDBGRQ debug event + 4 + 1 + + + + + + + diff --git a/svd/ATSAMC21J18A.svd b/svd/ATSAMC21J18A.svd new file mode 100644 index 000000000000..862e95a7d497 --- /dev/null +++ b/svd/ATSAMC21J18A.svd @@ -0,0 +1,27996 @@ + + + + Microchip Technology + MCHP + ATSAMC21J18A + SAMC21 + 0 + Microchip ATSAMC21J18A Microcontroller + + CM0+ + r0p0 + selectable + true + false + 2 + false + + 8 + 32 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + AC + U22451.1.1 + Analog Comparators + AC + AC_ + 0x42005000 + + 0 + 0x24 + registers + + + AC + 27 + + + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + + + CTRLB + Control B + 0x1 + 8 + write-only + 0x00 + + + START0 + Comparator 0 Start Comparison + 0 + 1 + + + START1 + Comparator 1 Start Comparison + 1 + 1 + + + START2 + Comparator 2 Start Comparison + 2 + 1 + + + START3 + Comparator 3 Start Comparison + 3 + 1 + + + + + EVCTRL + Event Control + 0x2 + 16 + 0x0000 + + + COMPEO0 + Comparator 0 Event Output Enable + 0 + 1 + + + COMPEO1 + Comparator 1 Event Output Enable + 1 + 1 + + + COMPEO2 + Comparator 2 Event Output Enable + 2 + 1 + + + COMPEO3 + Comparator 3 Event Output Enable + 3 + 1 + + + WINEO0 + Window 0 Event Output Enable + 4 + 1 + + + WINEO1 + Window 1 Event Output Enable + 5 + 1 + + + COMPEI0 + Comparator 0 Event Input Enable + 8 + 1 + + + COMPEI1 + Comparator 1 Event Input Enable + 9 + 1 + + + COMPEI2 + Comparator 2 Event Input Enable + 10 + 1 + + + COMPEI3 + Comparator 3 Event Input Enable + 11 + 1 + + + INVEI0 + Comparator 0 Input Event Invert Enable + 12 + 1 + + + INVEI1 + Comparator 1 Input Event Invert Enable + 13 + 1 + + + INVEI2 + Comparator 2 Input Event Invert Enable + 14 + 1 + + + INVEI3 + Comparator 3 Input Event Invert Enable + 15 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x4 + 8 + 0x00 + + + COMP0 + Comparator 0 Interrupt Enable + 0 + 1 + + + COMP1 + Comparator 1 Interrupt Enable + 1 + 1 + + + COMP2 + Comparator 2 Interrupt Enable + 2 + 1 + + + COMP3 + Comparator 3 Interrupt Enable + 3 + 1 + + + WIN0 + Window 0 Interrupt Enable + 4 + 1 + + + WIN1 + Window 1 Interrupt Enable + 5 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x5 + 8 + 0x00 + + + COMP0 + Comparator 0 Interrupt Enable + 0 + 1 + + + COMP1 + Comparator 1 Interrupt Enable + 1 + 1 + + + COMP2 + Comparator 2 Interrupt Enable + 2 + 1 + + + COMP3 + Comparator 3 Interrupt Enable + 3 + 1 + + + WIN0 + Window 0 Interrupt Enable + 4 + 1 + + + WIN1 + Window 1 Interrupt Enable + 5 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x6 + 8 + 0x00 + + + COMP0 + Comparator 0 + 0 + 1 + + + COMP1 + Comparator 1 + 1 + 1 + + + COMP2 + Comparator 2 + 2 + 1 + + + COMP3 + Comparator 3 + 3 + 1 + + + WIN0 + Window 0 + 4 + 1 + + + WIN1 + Window 1 + 5 + 1 + + + + + STATUSA + Status A + 0x7 + 8 + read-only + 0x00 + + + STATE0 + Comparator 0 Current State + 0 + 1 + + + STATE1 + Comparator 1 Current State + 1 + 1 + + + STATE2 + Comparator 2 Current State + 2 + 1 + + + STATE3 + Comparator 3 Current State + 3 + 1 + + + WSTATE0 + Window 0 Current State + 4 + 2 + + WSTATE0Select + + ABOVE + Signal is above window + 0 + + + INSIDE + Signal is inside window + 1 + + + BELOW + Signal is below window + 2 + + + + + WSTATE1 + Window 1 Current State + 6 + 2 + + WSTATE1Select + + ABOVE + Signal is above window + 0 + + + INSIDE + Signal is inside window + 1 + + + BELOW + Signal is below window + 2 + + + + + + + STATUSB + Status B + 0x8 + 8 + read-only + 0x00 + + + READY0 + Comparator 0 Ready + 0 + 1 + + + READY1 + Comparator 1 Ready + 1 + 1 + + + READY2 + Comparator 2 Ready + 2 + 1 + + + READY3 + Comparator 3 Ready + 3 + 1 + + + + + DBGCTRL + Debug Control + 0x9 + 8 + 0x00 + + + DBGRUN + Debug Run + 0 + 1 + + + + + WINCTRL + Window Control + 0xA + 8 + 0x00 + + + WEN0 + Window 0 Mode Enable + 0 + 1 + + + WINTSEL0 + Window 0 Interrupt Selection + 1 + 2 + + WINTSEL0Select + + ABOVE + Interrupt on signal above window + 0 + + + INSIDE + Interrupt on signal inside window + 1 + + + BELOW + Interrupt on signal below window + 2 + + + OUTSIDE + Interrupt on signal outside window + 3 + + + + + WEN1 + Window 1 Mode Enable + 4 + 1 + + + WINTSEL1 + Window 1 Interrupt Selection + 5 + 2 + + WINTSEL1Select + + ABOVE + Interrupt on signal above window + 0 + + + INSIDE + Interrupt on signal inside window + 1 + + + BELOW + Interrupt on signal below window + 2 + + + OUTSIDE + Interrupt on signal outside window + 3 + + + + + + + 4 + 1 + SCALER[%s] + Scaler n + 0xC + 8 + 0x00 + + + VALUE + Scaler Value + 0 + 6 + + + + + 4 + 4 + COMPCTRL[%s] + Comparator Control n + 0x10 + 32 + 0x00000000 + + + ENABLE + Enable + 1 + 1 + + + SINGLE + Single-Shot Mode + 2 + 1 + + + INTSEL + Interrupt Selection + 3 + 2 + + INTSELSelect + + TOGGLE + Interrupt on comparator output toggle + 0 + + + RISING + Interrupt on comparator output rising + 1 + + + FALLING + Interrupt on comparator output falling + 2 + + + EOC + Interrupt on end of comparison (single-shot mode only) + 3 + + + + + RUNSTDBY + Run in Standby + 6 + 1 + + + MUXNEG + Negative Input Mux Selection + 8 + 3 + + MUXNEGSelect + + PIN0 + I/O pin 0 + 0 + + + PIN1 + I/O pin 1 + 1 + + + PIN2 + I/O pin 2 + 2 + + + PIN3 + I/O pin 3 + 3 + + + GND + Ground + 4 + + + VSCALE + VDD scaler + 5 + + + BANDGAP + Internal bandgap voltage + 6 + + + DAC + DAC output + 7 + + + + + MUXPOS + Positive Input Mux Selection + 12 + 3 + + MUXPOSSelect + + PIN0 + I/O pin 0 + 0 + + + PIN1 + I/O pin 1 + 1 + + + PIN2 + I/O pin 2 + 2 + + + PIN3 + I/O pin 3 + 3 + + + VSCALE + VDD Scaler + 4 + + + + + SWAP + Swap Inputs and Invert + 15 + 1 + + + SPEED + Speed Selection + 16 + 2 + + SPEEDSelect + + LOW + Low speed + 0 + + + HIGH + High speed + 3 + + + + + HYSTEN + Hysteresis Enable + 19 + 1 + + + FLEN + Filter Length + 24 + 3 + + FLENSelect + + OFF + No filtering + 0 + + + MAJ3 + 3-bit majority function (2 of 3) + 1 + + + MAJ5 + 5-bit majority function (3 of 5) + 2 + + + + + OUT + Output + 28 + 2 + + OUTSelect + + OFF + The output of COMPn is not routed to the COMPn I/O port + 0 + + + ASYNC + The asynchronous output of COMPn is routed to the COMPn I/O port + 1 + + + SYNC + The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port + 2 + + + + + + + SYNCBUSY + Synchronization Busy + 0x20 + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + Enable Synchronization Busy + 1 + 1 + + + WINCTRL + WINCTRL Synchronization Busy + 2 + 1 + + + COMPCTRL0 + COMPCTRL 0 Synchronization Busy + 3 + 1 + + + COMPCTRL1 + COMPCTRL 1 Synchronization Busy + 4 + 1 + + + COMPCTRL2 + COMPCTRL 2 Synchronization Busy + 5 + 1 + + + COMPCTRL3 + COMPCTRL 3 Synchronization Busy + 6 + 1 + + + + + + + ADC0 + U22472.2.0 + Analog Digital Converter + ADC + ADC_ + 0x42004400 + + 0 + 0x2E + registers + + + ADC0 + 25 + + + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + SLAVEEN + Slave Enable + 5 + 1 + + + RUNSTDBY + Run During Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + + + CTRLB + Control B + 0x1 + 8 + 0x00 + + + PRESCALER + Prescaler Configuration + 0 + 3 + + PRESCALERSelect + + DIV2 + Peripheral clock / 2 + 0x0 + + + DIV4 + Peripheral clock / 4 + 0x1 + + + DIV8 + Peripheral clock / 8 + 0x2 + + + DIV16 + Peripheral clock / 16 + 0x3 + + + DIV32 + Peripheral clock / 32 + 0x4 + + + DIV64 + Peripheral clock / 64 + 0x5 + + + DIV128 + Peripheral clock / 128 + 0x6 + + + DIV256 + Peripheral clock / 256 + 0x7 + + + + + + + REFCTRL + Reference Control + 0x2 + 8 + 0x00 + + + REFSEL + Reference Selection + 0 + 4 + + REFSELSelect + + INTREF + Internal Bandgap Reference + 0x0 + + + INTVCC0 + 1/1.6 VDDANA + 0x1 + + + INTVCC1 + 1/2 VDDANA + 0x2 + + + AREFA + External Reference + 0x3 + + + DAC + DAC + 0x4 + + + INTVCC2 + VDDANA + 0x5 + + + + + REFCOMP + Reference Buffer Offset Compensation Enable + 7 + 1 + + + + + EVCTRL + Event Control + 0x3 + 8 + 0x00 + + + FLUSHEI + Flush Event Input Enable + 0 + 1 + + + STARTEI + Start Conversion Event Input Enable + 1 + 1 + + + FLUSHINV + Flush Event Invert Enable + 2 + 1 + + + STARTINV + Start Event Invert Enable + 3 + 1 + + + RESRDYEO + Result Ready Event Out + 4 + 1 + + + WINMONEO + Window Monitor Event Out + 5 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x4 + 8 + 0x00 + + + RESRDY + Result Ready Interrupt Disable + 0 + 1 + + + OVERRUN + Overrun Interrupt Disable + 1 + 1 + + + WINMON + Window Monitor Interrupt Disable + 2 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x5 + 8 + 0x00 + + + RESRDY + Result Ready Interrupt Enable + 0 + 1 + + + OVERRUN + Overrun Interrupt Enable + 1 + 1 + + + WINMON + Window Monitor Interrupt Enable + 2 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x6 + 8 + 0x00 + + + RESRDY + Result Ready Interrupt Flag + 0 + 1 + + + OVERRUN + Overrun Interrupt Flag + 1 + 1 + + + WINMON + Window Monitor Interrupt Flag + 2 + 1 + + + + + SEQSTATUS + Sequence Status + 0x7 + 8 + read-only + 0x00 + + + SEQSTATE + Sequence State + 0 + 5 + + + SEQBUSY + Sequence Busy + 7 + 1 + + + + + INPUTCTRL + Input Control + 0x8 + 16 + 0x0000 + + + MUXPOS + Positive Mux Input Selection + 0 + 5 + + MUXPOSSelect + + AIN0 + ADC AIN0 Pin + 0x0 + + + AIN1 + ADC AIN1 Pin + 0x1 + + + AIN2 + ADC AIN2 Pin + 0x2 + + + AIN3 + ADC AIN3 Pin + 0x3 + + + AIN4 + ADC AIN4 Pin + 0x4 + + + AIN5 + ADC AIN5 Pin + 0x5 + + + AIN6 + ADC AIN6 Pin + 0x6 + + + AIN7 + ADC AIN7 Pin + 0x7 + + + AIN8 + ADC AIN8 Pin + 0x8 + + + AIN9 + ADC AIN9 Pin + 0x9 + + + AIN10 + ADC AIN10 Pin + 0xA + + + AIN11 + ADC AIN11 Pin + 0xB + + + BANDGAP + Bandgap Voltage + 0x19 + + + SCALEDCOREVCC + 1/4 Scaled Core Supply + 0x1A + + + SCALEDIOVCC + 1/4 Scaled I/O Supply + 0x1B + + + DAC + DAC Output + 0x1C + + + + + MUXNEG + Negative Mux Input Selection + 8 + 5 + + MUXNEGSelect + + AIN0 + ADC AIN0 Pin + 0x0 + + + AIN1 + ADC AIN1 Pin + 0x1 + + + AIN2 + ADC AIN2 Pin + 0x2 + + + AIN3 + ADC AIN3 Pin + 0x3 + + + AIN4 + ADC AIN4 Pin + 0x4 + + + AIN5 + ADC AIN5 Pin + 0x5 + + + GND + Internal Ground + 0x18 + + + + + + + CTRLC + Control C + 0xA + 16 + 0x0000 + + + DIFFMODE + Differential Mode + 0 + 1 + + + LEFTADJ + Left-Adjusted Result + 1 + 1 + + + FREERUN + Free Running Mode + 2 + 1 + + + CORREN + Digital Correction Logic Enable + 3 + 1 + + + RESSEL + Conversion Result Resolution + 4 + 2 + + RESSELSelect + + 12BIT + 12-bit + 0x0 + + + 16BIT + 16-bit averaging mode + 0x1 + + + 10BIT + 10-bit + 0x2 + + + 8BIT + 8-bit + 0x3 + + + + + R2R + Rail-to-Rail mode enable + 7 + 1 + + + WINMODE + Window Monitor Mode + 8 + 3 + + WINMODESelect + + DISABLE + No window mode (default) + 0 + + + MODE1 + RESULT > WINLT + 1 + + + MODE2 + RESULT < WINUT + 2 + + + MODE3 + WINLT < RESULT < WINUT + 3 + + + MODE4 + !(WINLT < RESULT < WINUT) + 4 + + + + + DUALSEL + Dual Mode Trigger Selection + 12 + 2 + + DUALSELSelect + + BOTH + Start event or software trigger will start a conversion on both ADCs + 0 + + + INTERLEAVE + START event or software trigger will alternately start a conversion on ADC0 and ADC1 + 1 + + + + + + + AVGCTRL + Average Control + 0xC + 8 + 0x00 + + + SAMPLENUM + Number of Samples to be Collected + 0 + 4 + + SAMPLENUMSelect + + 1 + 1 sample + 0x0 + + + 2 + 2 samples + 0x1 + + + 4 + 4 samples + 0x2 + + + 8 + 8 samples + 0x3 + + + 16 + 16 samples + 0x4 + + + 32 + 32 samples + 0x5 + + + 64 + 64 samples + 0x6 + + + 128 + 128 samples + 0x7 + + + 256 + 256 samples + 0x8 + + + 512 + 512 samples + 0x9 + + + 1024 + 1024 samples + 0xA + + + + + ADJRES + Adjusting Result / Division Coefficient + 4 + 3 + + + + + SAMPCTRL + Sample Time Control + 0xD + 8 + 0x00 + + + SAMPLEN + Sampling Time Length + 0 + 6 + + + OFFCOMP + Comparator Offset Compensation Enable + 7 + 1 + + + + + WINLT + Window Monitor Lower Threshold + 0xE + 16 + 0x0000 + + + WINLT + Window Lower Threshold + 0 + 16 + + + + + WINUT + Window Monitor Upper Threshold + 0x10 + 16 + 0x0000 + + + WINUT + Window Upper Threshold + 0 + 16 + + + + + GAINCORR + Gain Correction + 0x12 + 16 + 0x0000 + + + GAINCORR + Gain Correction Value + 0 + 12 + + + + + OFFSETCORR + Offset Correction + 0x14 + 16 + 0x0000 + + + OFFSETCORR + Offset Correction Value + 0 + 12 + + + + + SWTRIG + Software Trigger + 0x18 + 8 + 0x00 + + + FLUSH + ADC Flush + 0 + 1 + + + START + Start ADC Conversion + 1 + 1 + + + + + DBGCTRL + Debug Control + 0x1C + 8 + 0x00 + + + DBGRUN + Debug Run + 0 + 1 + + + + + SYNCBUSY + Synchronization Busy + 0x20 + 16 + read-only + 0x0000 + + + SWRST + SWRST Synchronization Busy + 0 + 1 + + + ENABLE + ENABLE Synchronization Busy + 1 + 1 + + + INPUTCTRL + INPUTCTRL Synchronization Busy + 2 + 1 + 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Interrupt Enable + 0 + 1 + + + + + INTENSET + Interrupt Enable Set Register + 0x9 + 8 + 0x00 + + + DONE + Measurement Done Interrupt Enable + 0 + 1 + + + + + INTFLAG + Interrupt Flag Register + 0xA + 8 + 0x00 + + + DONE + Measurement Done + 0 + 1 + + + + + STATUS + Status Register + 0xB + 8 + 0x00 + + + BUSY + FREQM Status + 0 + 1 + + + OVF + Sticky Count Value Overflow + 1 + 1 + + + + + SYNCBUSY + Synchronization Busy Register + 0xC + 32 + read-only + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + + + VALUE + Count Value Register + 0x10 + 32 + read-only + 0x00000000 + + + VALUE + Measurement Value + 0 + 24 + + + + + + + GCLK + U21221.1.1 + Generic Clock Generator + GCLK + GCLK_ + 0x40001C00 + + 0 + 0x184 + registers + + + + CTRLA + Control + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + + + SYNCBUSY + Synchronization Busy + 0x4 + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchroniation Busy bit + 0 + 1 + + + GENCTRL0 + Generic Clock Generator Control 0 Synchronization Busy bits + 2 + 1 + + GENCTRL0Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + + + GENCTRL1 + Generic Clock Generator Control 1 Synchronization Busy bits + 3 + 1 + + GENCTRL1Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + + + GENCTRL2 + Generic Clock Generator Control 2 Synchronization Busy bits + 4 + 1 + + GENCTRL2Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + + + GENCTRL3 + Generic Clock Generator Control 3 Synchronization Busy bits + 5 + 1 + + GENCTRL3Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + + + GENCTRL4 + Generic Clock Generator Control 4 Synchronization Busy bits + 6 + 1 + + GENCTRL4Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + + + GENCTRL5 + Generic Clock Generator Control 5 Synchronization Busy bits + 7 + 1 + + GENCTRL5Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + + + GENCTRL6 + Generic Clock Generator Control 6 Synchronization Busy bits + 8 + 1 + + GENCTRL6Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + + + GENCTRL7 + Generic Clock Generator Control 7 Synchronization Busy bits + 9 + 1 + + GENCTRL7Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + + + GENCTRL8 + Generic Clock Generator Control 8 Synchronization Busy bits + 10 + 1 + + GENCTRL8Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + + + + + 9 + 4 + GENCTRL[%s] + Generic Clock Generator Control + 0x20 + 32 + 0x00000000 + + + SRC + Source Select + 0 + 3 + + SRCSelect + + XOSC + XOSC oscillator output + 0 + + + GCLKIN + Generator input pad + 1 + + + GCLKGEN1 + Generic clock generator 1 output + 2 + + + OSCULP32K + OSCULP32K oscillator output + 3 + + + OSC32K + OSC32K oscillator output + 4 + + + XOSC32K + XOSC32K oscillator output + 5 + + + OSC48M + OSC48M oscillator output + 6 + + + DPLL96M + DPLL96M output + 7 + + + + + GENEN + Generic Clock Generator Enable + 8 + 1 + + + IDC + Improve Duty Cycle + 9 + 1 + + + OOV + Output Off Value + 10 + 1 + + + OE + Output Enable + 11 + 1 + + + DIVSEL + Divide Selection + 12 + 1 + + DIVSELSelect + + DIV1 + Divide input directly by divider factor + 0x0 + + + DIV2 + Divide input by 2^(divider factor+ 1) + 0x1 + + + + + RUNSTDBY + Run in Standby + 13 + 1 + + + DIV + Division Factor + 16 + 16 + + + + + 41 + 4 + PCHCTRL[%s] + Peripheral Clock Control + 0x80 + 32 + 0x00000000 + + + GEN + Generic Clock Generator + 0 + 4 + + GENSelect + + GCLK0 + Generic clock generator 0 + 0x0 + + + GCLK1 + Generic clock generator 1 + 0x1 + + + GCLK2 + Generic clock generator 2 + 0x2 + + + GCLK3 + Generic clock generator 3 + 0x3 + + + GCLK4 + Generic clock generator 4 + 0x4 + + + GCLK5 + Generic clock generator 5 + 0x5 + + + GCLK6 + Generic clock generator 6 + 0x6 + + + GCLK7 + Generic clock generator 7 + 0x7 + + + GCLK8 + Generic clock generator 8 + 0x8 + + + + + CHEN + Channel Enable + 6 + 1 + + + WRTLOCK + Write Lock + 7 + 1 + + + + + + + HMATRIXHS + I76382.1.3 + HSB Matrix + HMATRIXB + HMATRIXB_ + 0x4100A000 + + 0 + 0x168 + registers + + + + 16 + 4 + MCFG[%s] + Master Configuration + 0x0 + 32 + 0x00000002 + + + ULBT + Undefined Length Burst Type + 0 + 3 + + ULBTSelect + + INFINITE + Infinite Length + 0 + + + SINGLE + Single Access + 1 + + + FOUR_BEAT + Four Beat Burst + 2 + + + EIGHT_BEAT + Eight Beat Burst + 3 + + + SIXTEEN_BEAT + Sixteen Beat Burst + 4 + + + + + + + 16 + 4 + SCFG[%s] + Slave Configuration + 0x40 + 32 + 0x00000010 + + + SLOT_CYCLE + Maximum Number of Allowed Cycles for a Burst + 0 + 8 + + + DEFMSTR_TYPE + Default Master Type + 16 + 2 + + DEFMSTR_TYPESelect + + NO_DEFAULT + No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. + 0 + + + LAST_DEFAULT + Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. + 1 + + + FIXED_DEFAULT + Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave. + 2 + + + + + FIXED_DEFMSTR + Fixed Index of Default Master + 18 + 4 + + + ARBT + Arbitration Type + 24 + 1 + + ARBTSelect + + ROUND_ROBIN + Round-Robin Arbitration + 0 + + + FIXED_PRIORITY + Fixed Priority Arbitration + 1 + + + + + + + 4 + 0x8 + PRS[%s] + + 0x080 + + PRAS + Priority A for Slave + 0x0 + 32 + 0x00000000 + + + M0PR + Master 0 Priority + 0 + 4 + + + M1PR + Master 1 Priority + 4 + 4 + + + M2PR + Master 2 Priority + 8 + 4 + + + M3PR + Master 3 Priority + 12 + 4 + + + M4PR + Master 4 Priority + 16 + 4 + + + M5PR + Master 5 Priority + 20 + 4 + + + M6PR + Master 6 Priority + 24 + 4 + + + M7PR + Master 7 Priority + 28 + 4 + + + + + PRBS + Priority B for Slave + 0x4 + 32 + 0x00000000 + + + M8PR + Master 8 Priority + 0 + 4 + + + M9PR + Master 9 Priority + 4 + 4 + + + M10PR + Master 10 Priority + 8 + 4 + + + M11PR + Master 11 Priority + 12 + 4 + + + M12PR + Master 12 Priority + 16 + 4 + + + M13PR + Master 13 Priority + 20 + 4 + + + M14PR + Master 14 Priority + 24 + 4 + + + M15PR + Master 15 Priority + 28 + 4 + + + + + + MRCR + Master Remap Control + 0x100 + 32 + 0x00000000 + + + RCB0 + Remap Command Bit for Master 0 + 0 + 1 + + RCB0Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB1 + Remap Command Bit for Master 1 + 1 + 1 + + RCB1Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB2 + Remap Command Bit for Master 2 + 2 + 1 + + RCB2Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB3 + Remap Command Bit for Master 3 + 3 + 1 + + RCB3Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB4 + Remap Command Bit for Master 4 + 4 + 1 + + RCB4Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB5 + Remap Command Bit for Master 5 + 5 + 1 + + RCB5Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB6 + Remap Command Bit for Master 6 + 6 + 1 + + RCB6Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB7 + Remap Command Bit for Master 7 + 7 + 1 + + RCB7Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB8 + Remap Command Bit for Master 8 + 8 + 1 + + RCB8Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB9 + Remap Command Bit for Master 9 + 9 + 1 + + RCB9Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB10 + Remap Command Bit for Master 10 + 10 + 1 + + RCB10Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB11 + Remap Command Bit for Master 11 + 11 + 1 + + RCB11Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB12 + Remap Command Bit for Master 12 + 12 + 1 + + RCB12Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB13 + Remap Command Bit for Master 13 + 13 + 1 + + RCB13Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB14 + Remap Command Bit for Master 14 + 14 + 1 + + RCB14Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB15 + Remap Command Bit for Master 15 + 15 + 1 + + RCB15Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + + + 16 + 4 + SFR[%s] + Special Function + 0x110 + 32 + 0x00000000 + + + SFR + Special Function Register + 0 + 32 + + + + + + + MCLK + U22342.0.0 + Main Clock + MCLK + MCLK_ + 0x40000800 + + 0 + 0x20 + registers + + + + INTENCLR + Interrupt Enable Clear + 0x1 + 8 + 0x00 + + + CKRDY + Clock Ready Interrupt Enable + 0 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x2 + 8 + 0x00 + + + CKRDY + Clock Ready Interrupt Enable + 0 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x3 + 8 + 0x01 + + + CKRDY + Clock Ready + 0 + 1 + + + + + CPUDIV + CPU Clock Division + 0x4 + 8 + 0x01 + + + CPUDIV + CPU Clock Division Factor + 0 + 8 + + CPUDIVSelect + + DIV1 + Divide by 1 + 0x01 + + + DIV2 + Divide by 2 + 0x02 + + + DIV4 + Divide by 4 + 0x04 + + + DIV8 + Divide by 8 + 0x08 + + + DIV16 + Divide by 16 + 0x10 + + + DIV32 + Divide by 32 + 0x20 + + + DIV64 + Divide by 64 + 0x40 + + + DIV128 + Divide by 128 + 0x80 + + + + + + + AHBMASK + AHB Mask + 0x10 + 32 + 0x00001CFF + + + HPB0_ + HPB0 AHB Clock Mask + 0 + 1 + + + HPB1_ + HPB1 AHB Clock Mask + 1 + 1 + + + HPB2_ + HPB2 AHB Clock Mask + 2 + 1 + + + DSU_ + DSU AHB Clock Mask + 3 + 1 + + + HMATRIXHS_ + HMATRIXHS AHB Clock Mask + 4 + 1 + + + NVMCTRL_ + NVMCTRL AHB Clock Mask + 5 + 1 + + + HSRAM_ + HSRAM AHB Clock Mask + 6 + 1 + + + DMAC_ + DMAC AHB Clock Mask + 7 + 1 + + + CAN0_ + CAN0 AHB Clock Mask + 8 + 1 + + + CAN1_ + CAN1 AHB Clock Mask + 9 + 1 + + + PAC_ + PAC AHB Clock Mask + 10 + 1 + + + NVMCTRL_PICACHU_ + NVMCTRL_PICACHU AHB Clock Mask + 11 + 1 + + + DIVAS_ + DIVAS AHB Clock Mask + 12 + 1 + + + + + APBAMASK + APBA Mask + 0x14 + 32 + 0x00000FFF + + + PAC_ + PAC APB Clock Enable + 0 + 1 + + + PM_ + PM APB Clock Enable + 1 + 1 + + + MCLK_ + MCLK APB Clock Enable + 2 + 1 + + + RSTC_ + RSTC APB Clock Enable + 3 + 1 + + + OSCCTRL_ + OSCCTRL APB Clock Enable + 4 + 1 + + + OSC32KCTRL_ + OSC32KCTRL APB Clock Enable + 5 + 1 + + + SUPC_ + SUPC APB Clock Enable + 6 + 1 + + + GCLK_ + GCLK APB Clock Enable + 7 + 1 + + + WDT_ + WDT APB Clock Enable + 8 + 1 + + + RTC_ + RTC APB Clock Enable + 9 + 1 + + + EIC_ + EIC APB Clock Enable + 10 + 1 + + + FREQM_ + FREQM APB Clock Enable + 11 + 1 + + + TSENS_ + TSENS APB Clock Enable + 12 + 1 + + + + + APBBMASK + APBB Mask + 0x18 + 32 + 0x00000007 + + + PORT_ + PORT APB Clock Enable + 0 + 1 + + + DSU_ + DSU APB Clock Enable + 1 + 1 + + + NVMCTRL_ + NVMCTRL APB Clock Enable + 2 + 1 + + + HMATRIXHS_ + HMATRIXHS APB Clock Enable + 5 + 1 + + + + + APBCMASK + APBC Mask + 0x1C + 32 + 0x00000000 + + + EVSYS_ + EVSYS APB Clock Enable + 0 + 1 + + + SERCOM0_ + SERCOM0 APB Clock Enable + 1 + 1 + + + SERCOM1_ + SERCOM1 APB Clock Enable + 2 + 1 + + + SERCOM2_ + SERCOM2 APB Clock Enable + 3 + 1 + + + SERCOM3_ + SERCOM3 APB Clock Enable + 4 + 1 + + + SERCOM4_ + SERCOM4 APB Clock Enable + 5 + 1 + + + SERCOM5_ + SERCOM5 APB Clock Enable + 6 + 1 + + + TCC0_ + TCC0 APB Clock Enable + 9 + 1 + + + TCC1_ + TCC1 APB Clock Enable + 10 + 1 + + + TCC2_ + TCC2 APB Clock Enable + 11 + 1 + + + TC0_ + TC0 APB Clock Enable + 12 + 1 + + + TC1_ + TC1 APB Clock Enable + 13 + 1 + + + TC2_ + TC2 APB Clock Enable + 14 + 1 + + + TC3_ + TC3 APB Clock Enable + 15 + 1 + + + TC4_ + TC4 APB Clock Enable + 16 + 1 + + + ADC0_ + ADC0 APB Clock Enable + 17 + 1 + + + ADC1_ + ADC1 APB Clock Enable + 18 + 1 + + + SDADC_ + SDADC APB Clock Enable + 19 + 1 + + + AC_ + AC APB Clock Enable + 20 + 1 + + + DAC_ + DAC APB Clock Enable + 21 + 1 + + + PTC_ + PTC APB Clock Enable + 22 + 1 + + + CCL_ + CCL APB Clock Enable + 23 + 1 + + + + + + + MTB + U20021.0.0 + Cortex-M0+ Micro-Trace Buffer + MTB + MTB_ + 0x41008000 + + 0 + 0x1000 + registers + + + + POSITION + MTB Position + 0x0 + 32 + + + WRAP + Pointer Value Wraps + 2 + 1 + + + POINTER + Trace Packet Location Pointer + 3 + 29 + + + + + MASTER + MTB Master + 0x4 + 32 + 0x00000000 + + + MASK + Maximum Value of the Trace Buffer in SRAM + 0 + 5 + + + TSTARTEN + Trace Start Input Enable + 5 + 1 + + + TSTOPEN + Trace Stop Input Enable + 6 + 1 + + + SFRWPRIV + Special Function Register Write Privilege + 7 + 1 + + + RAMPRIV + SRAM Privilege + 8 + 1 + + + HALTREQ + Halt Request + 9 + 1 + + + EN + Main Trace Enable + 31 + 1 + + + + + FLOW + MTB Flow + 0x8 + 32 + 0x00000000 + + + AUTOSTOP + Auto Stop Tracing + 0 + 1 + + + AUTOHALT + Auto Halt Request + 1 + 1 + + + WATERMARK + Watermark value + 3 + 29 + + + + + BASE + MTB Base + 0xC + 32 + read-only + + + ITCTRL + MTB Integration Mode Control + 0xF00 + 32 + + + CLAIMSET + MTB Claim Set + 0xFA0 + 32 + + + CLAIMCLR + MTB Claim Clear + 0xFA4 + 32 + + + LOCKACCESS + MTB Lock Access + 0xFB0 + 32 + + + LOCKSTATUS + MTB Lock Status + 0xFB4 + 32 + read-only + + + AUTHSTATUS + MTB Authentication Status + 0xFB8 + 32 + read-only + + + DEVARCH + MTB Device Architecture + 0xFBC + 32 + read-only + + + DEVID + MTB Device Configuration + 0xFC8 + 32 + read-only + + + DEVTYPE + MTB Device Type + 0xFCC + 32 + read-only + + + PID4 + Peripheral Identification 4 + 0xFD0 + 32 + read-only + + + PID5 + Peripheral Identification 5 + 0xFD4 + 32 + read-only + + + PID6 + Peripheral Identification 6 + 0xFD8 + 32 + read-only + + + PID7 + Peripheral Identification 7 + 0xFDC + 32 + read-only + + + PID0 + Peripheral Identification 0 + 0xFE0 + 32 + read-only + + + PID1 + Peripheral Identification 1 + 0xFE4 + 32 + read-only + + + PID2 + Peripheral Identification 2 + 0xFE8 + 32 + read-only + + + PID3 + Peripheral Identification 3 + 0xFEC + 32 + read-only + + + CID0 + Component Identification 0 + 0xFF0 + 32 + read-only + + + CID1 + Component Identification 1 + 0xFF4 + 32 + read-only + + + CID2 + Component Identification 2 + 0xFF8 + 32 + read-only + + + CID3 + Component Identification 3 + 0xFFC + 32 + read-only + + + + + NVMCTRL + U22074.0.1.1 + Non-Volatile Memory Controller + NVMCTRL + NVMCTRL_ + 0x41004000 + + 0 + 0x30 + registers + + + NVMCTRL + 6 + + + + CTRLA + Control A + 0x0 + 16 + 0x0000 + + + CMD + Command + 0 + 7 + + CMDSelect + + ER + Erase Row - Erases the row addressed by the ADDR register. + 0x02 + + + WP + Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. + 0x04 + + + EAR + Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. + 0x05 + + + WAP + Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. + 0x06 + + + SF + Security Flow Command + 0x0A + + + WL + Write lockbits + 0x0F + + + RWWEEER + RWW EEPROM area Erase Row - Erases the row addressed by the ADDR register. + 0x1A + + + RWWEEWP + RWW EEPROM Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. + 0x1C + + + LR + Lock Region - Locks the region containing the address location in the ADDR register. + 0x40 + + + UR + Unlock Region - Unlocks the region containing the address location in the ADDR register. + 0x41 + + + SPRM + Sets the power reduction mode. + 0x42 + + + CPRM + Clears the power reduction mode. + 0x43 + + + PBC + Page Buffer Clear - Clears the page buffer. + 0x44 + + + SSB + Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row. + 0x45 + + + INVALL + Invalidate all cache lines. + 0x46 + + + + + CMDEX + Command Execution + 8 + 8 + + CMDEXSelect + + KEY + Execution Key + 0xA5 + + + + + + + CTRLB + Control B + 0x4 + 32 + 0x00000080 + + + RWS + NVM Read Wait States + 1 + 4 + + RWSSelect + + SINGLE + Single Auto Wait State + 0 + + + HALF + Half Auto Wait State + 1 + + + DUAL + Dual Auto Wait State + 2 + + + + + MANW + Manual Write + 7 + 1 + + + SLEEPPRM + Power Reduction Mode during Sleep + 8 + 2 + + SLEEPPRMSelect + + WAKEONACCESS + NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access. + 0 + + + WAKEUPINSTANT + NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep. + 1 + + + DISABLED + Auto power reduction disabled. + 3 + + + + + READMODE + NVMCTRL Read Mode + 16 + 2 + + READMODESelect + + NO_MISS_PENALTY + The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance. + 0x0 + + + LOW_POWER + Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time. + 0x1 + + + DETERMINISTIC + The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings. + 0x2 + + + + + CACHEDIS + Cache Disable + 18 + 2 + + + + + PARAM + NVM Parameter + 0x8 + 32 + 0x00000000 + + + NVMP + NVM Pages + 0 + 16 + + + PSZ + Page Size + 16 + 3 + + PSZSelect + + 8 + 8 bytes + 0x0 + + + 16 + 16 bytes + 0x1 + + + 32 + 32 bytes + 0x2 + + + 64 + 64 bytes + 0x3 + + + 128 + 128 bytes + 0x4 + + + 256 + 256 bytes + 0x5 + + + 512 + 512 bytes + 0x6 + + + 1024 + 1024 bytes + 0x7 + + + + + RWWEEP + RWW EEPROM Pages + 20 + 12 + + + + + INTENCLR + Interrupt Enable Clear + 0xC + 8 + 0x00 + + + READY + NVM Ready Interrupt Enable + 0 + 1 + + + ERROR + Error Interrupt Enable + 1 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x10 + 8 + 0x00 + + + READY + NVM Ready Interrupt Enable + 0 + 1 + + + ERROR + Error Interrupt Enable + 1 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x14 + 8 + 0x00 + + + READY + NVM Ready + 0 + 1 + + + ERROR + Error + 1 + 1 + + + + + STATUS + Status + 0x18 + 16 + 0x0000 + + + PRM + Power Reduction Mode + 0 + 1 + + + LOAD + NVM Page Buffer Active Loading + 1 + 1 + + + PROGE + Programming Error Status + 2 + 1 + + + LOCKE + Lock Error Status + 3 + 1 + + + NVME + NVM Error + 4 + 1 + + + SB + Security Bit Status + 8 + 1 + + + + + ADDR + Address + 0x1C + 32 + 0x00000000 + + + ADDR + NVM Address + 0 + 22 + + + + + LOCK + Lock Section + 0x20 + 16 + 0x0000 + + + LOCK + Region Lock Bits + 0 + 16 + + + + + PBLDATA0 + Page Buffer Load Data 0 + 0x28 + 32 + read-only + 0x00000000 + + + PBLDATA1 + Page Buffer Load Data 1 + 0x2C + 32 + read-only + 0x00000000 + + + + + OSCCTRL + U21192.1.0 + Oscillators Control + OSCCTRL + OSCCTRL_ + 0x40001000 + + 0 + 0x3C + registers + + + + INTENCLR + Interrupt Enable Clear + 0x0 + 32 + 0x00000000 + + + XOSCRDY + XOSC Ready Interrupt Enable + 0 + 1 + + + XOSCFAIL + XOSC Clock Failure Detector Interrupt Enable + 1 + 1 + + + OSC48MRDY + OSC48M Ready Interrupt Enable + 4 + 1 + + + DPLLLCKR + DPLL Lock Rise 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Port Event Pin Identifier 1 + 8 + 5 + + + EVACT1 + Port Event Action 1 + 13 + 2 + + + PORTEI1 + Port Event Enable Input 1 + 15 + 1 + + + PID2 + Port Event Pin Identifier 2 + 16 + 5 + + + EVACT2 + Port Event Action 2 + 21 + 2 + + + PORTEI2 + Port Event Enable Input 2 + 23 + 1 + + + PID3 + Port Event Pin Identifier 3 + 24 + 5 + + + EVACT3 + Port Event Action 3 + 29 + 2 + + + PORTEI3 + Port Event Enable Input 3 + 31 + 1 + + + + + 16 + 1 + PMUX[%s] + Peripheral Multiplexing n + 0x30 + 8 + 0x00 + + + PMUXE + Peripheral Multiplexing for Even-Numbered Pin + 0 + 4 + + + PMUXO + Peripheral Multiplexing for Odd-Numbered Pin + 4 + 4 + + + + + 32 + 1 + PINCFG[%s] + Pin Configuration n + 0x40 + 8 + 0x00 + + + PMUXEN + Select Peripheral Multiplexer + 0 + 1 + + + INEN + Input Enable + 1 + 1 + + + PULLEN + Pull Enable + 2 + 1 + + + DRVSTR + Output Driver Strength Selection + 6 + 1 + + + + + + + + PORT_IOBUS + PORT_IOBUS_ + 0x60000000 + + + PTC + U22153.1.0 + Peripheral Touch Controller + PTC + PTC_ + 0x42005800 + + 0 + 0x1 + reserved + + + PTC + 30 + + + + RSTC + U22392.0.2 + Reset Controller + RSTC + RSTC_ + 0x40000C00 + + 0 + 0x1 + registers + + + + RCAUSE + Reset Cause + 0x0 + 8 + read-only + + + POR + Power On Reset + 0 + 1 + + + BODCORE + Brown Out CORE Detector Reset + 1 + 1 + + + BODVDD + Brown Out VDD Detector Reset + 2 + 1 + + + EXT + External Reset + 4 + 1 + + + WDT + Watchdog Reset + 5 + 1 + + + SYST + System Reset Request + 6 + 1 + + + + + + + RTC + U22501.1.1 + Real-Time Counter + RTC + RTC_ + 0x40002400 + + 0 + 0x25 + registers + + + RTC + 2 + + + + MODE0 + 32-bit Counter with Single 32-bit Compare + RtcMode0 + 0x0 + + CTRLA + MODE0 Control A + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 2 + + MODESelect + + COUNT32 + Mode 0: 32-bit Counter + 0x0 + + + COUNT16 + Mode 1: 16-bit Counter + 0x1 + + + CLOCK + Mode 2: Clock/Calendar + 0x2 + + + + + MATCHCLR + Clear on Match + 7 + 1 + + + PRESCALER + Prescaler + 8 + 4 + + PRESCALERSelect + + OFF + CLK_RTC_CNT = GCLK_RTC/1 + 0x0 + + + DIV1 + CLK_RTC_CNT = GCLK_RTC/1 + 0x1 + + + DIV2 + CLK_RTC_CNT = GCLK_RTC/2 + 0x2 + + + DIV4 + CLK_RTC_CNT = GCLK_RTC/4 + 0x3 + + + DIV8 + CLK_RTC_CNT = GCLK_RTC/8 + 0x4 + + + DIV16 + CLK_RTC_CNT = GCLK_RTC/16 + 0x5 + + + DIV32 + CLK_RTC_CNT = GCLK_RTC/32 + 0x6 + + + DIV64 + CLK_RTC_CNT = GCLK_RTC/64 + 0x7 + + + DIV128 + CLK_RTC_CNT = GCLK_RTC/128 + 0x8 + + + DIV256 + CLK_RTC_CNT = GCLK_RTC/256 + 0x9 + + + DIV512 + CLK_RTC_CNT = GCLK_RTC/512 + 0xA + + + DIV1024 + CLK_RTC_CNT = GCLK_RTC/1024 + 0xB + + + + + COUNTSYNC + Count Read Synchronization Enable + 15 + 1 + + + + + EVCTRL + MODE0 Event Control + 0x4 + 32 + 0x00000000 + + + PEREO0 + Periodic Interval 0 Event Output Enable + 0 + 1 + + + PEREO1 + Periodic Interval 1 Event Output Enable + 1 + 1 + + + PEREO2 + Periodic Interval 2 Event Output Enable + 2 + 1 + + + PEREO3 + Periodic Interval 3 Event Output Enable + 3 + 1 + + + PEREO4 + Periodic Interval 4 Event Output Enable + 4 + 1 + + + PEREO5 + Periodic Interval 5 Event Output Enable + 5 + 1 + + + PEREO6 + Periodic Interval 6 Event Output Enable + 6 + 1 + + + PEREO7 + Periodic Interval 7 Event Output Enable + 7 + 1 + + + CMPEO0 + Compare 0 Event Output Enable + 8 + 1 + + + OVFEO + Overflow Event Output Enable + 15 + 1 + + + + + INTENCLR + MODE0 Interrupt Enable Clear + 0x8 + 16 + 0x0000 + + + PER0 + Periodic Interval 0 Interrupt Enable + 0 + 1 + + + PER1 + Periodic Interval 1 Interrupt Enable + 1 + 1 + + + PER2 + Periodic Interval 2 Interrupt Enable + 2 + 1 + + + PER3 + Periodic Interval 3 Interrupt Enable + 3 + 1 + + + PER4 + Periodic Interval 4 Interrupt Enable + 4 + 1 + + + PER5 + Periodic Interval 5 Interrupt Enable + 5 + 1 + + + PER6 + Periodic Interval 6 Interrupt Enable + 6 + 1 + + + PER7 + Periodic Interval 7 Interrupt Enable + 7 + 1 + + + CMP0 + Compare 0 Interrupt Enable + 8 + 1 + + + OVF + Overflow Interrupt Enable + 15 + 1 + + + + + INTENSET + MODE0 Interrupt Enable Set + 0xA + 16 + 0x0000 + + + PER0 + Periodic Interval 0 Interrupt Enable + 0 + 1 + + + PER1 + Periodic Interval 1 Interrupt Enable + 1 + 1 + + + PER2 + Periodic Interval 2 Interrupt Enable + 2 + 1 + + + PER3 + Periodic Interval 3 Interrupt Enable + 3 + 1 + + + PER4 + Periodic Interval 4 Interrupt Enable + 4 + 1 + + + PER5 + Periodic Interval 5 Interrupt Enable + 5 + 1 + + + PER6 + Periodic Interval 6 Interrupt Enable + 6 + 1 + + + PER7 + Periodic Interval 7 Interrupt Enable + 7 + 1 + + + CMP0 + Compare 0 Interrupt Enable + 8 + 1 + + + OVF + Overflow Interrupt Enable + 15 + 1 + + + + + INTFLAG + MODE0 Interrupt Flag Status and Clear + 0xC + 16 + 0x0000 + + + PER0 + Periodic Interval 0 + 0 + 1 + + + PER1 + Periodic Interval 1 + 1 + 1 + + + PER2 + Periodic Interval 2 + 2 + 1 + + + PER3 + Periodic Interval 3 + 3 + 1 + + + PER4 + Periodic Interval 4 + 4 + 1 + + + PER5 + Periodic Interval 5 + 5 + 1 + + + PER6 + Periodic Interval 6 + 6 + 1 + + + PER7 + Periodic Interval 7 + 7 + 1 + + + CMP0 + Compare 0 + 8 + 1 + + + OVF + Overflow + 15 + 1 + + + + + DBGCTRL + Debug Control + 0xE + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + SYNCBUSY + MODE0 Synchronization Busy Status + 0x10 + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Busy + 0 + 1 + + + ENABLE + Enable Bit Busy + 1 + 1 + + + FREQCORR + FREQCORR Register Busy + 2 + 1 + + + COUNT + COUNT Register Busy + 3 + 1 + + + COMP0 + COMP 0 Register Busy + 5 + 1 + + + COUNTSYNC + Count Read Synchronization Enable Bit Busy + 15 + 1 + + + + + FREQCORR + Frequency Correction + 0x14 + 8 + 0x00 + + + VALUE + Correction Value + 0 + 7 + + + SIGN + Correction Sign + 7 + 1 + + + + + COUNT + MODE0 Counter Value + 0x18 + 32 + 0x00000000 + + + COUNT + Counter Value + 0 + 32 + + + + + COMP + MODE0 Compare n Value + 0x20 + 32 + 0x00000000 + + + COMP + Compare Value + 0 + 32 + + + + + + MODE1 + 16-bit Counter with Two 16-bit Compares + MODE0 + RtcMode1 + 0x0 + + CTRLA + MODE1 Control A + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 2 + + MODESelect + + COUNT32 + Mode 0: 32-bit Counter + 0 + + + COUNT16 + Mode 1: 16-bit Counter + 1 + + + CLOCK + Mode 2: Clock/Calendar + 2 + + + + + PRESCALER + Prescaler + 8 + 4 + + PRESCALERSelect + + OFF + CLK_RTC_CNT = GCLK_RTC/1 + 0 + + + DIV1 + CLK_RTC_CNT = GCLK_RTC/1 + 1 + + + DIV2 + CLK_RTC_CNT = GCLK_RTC/2 + 2 + + + DIV4 + CLK_RTC_CNT = GCLK_RTC/4 + 3 + + + DIV8 + CLK_RTC_CNT = GCLK_RTC/8 + 4 + + + DIV16 + CLK_RTC_CNT = GCLK_RTC/16 + 5 + + + DIV32 + CLK_RTC_CNT = GCLK_RTC/32 + 6 + + + DIV64 + CLK_RTC_CNT = GCLK_RTC/64 + 7 + + + DIV128 + CLK_RTC_CNT = GCLK_RTC/128 + 8 + + + DIV256 + CLK_RTC_CNT = GCLK_RTC/256 + 9 + + + DIV512 + CLK_RTC_CNT = GCLK_RTC/512 + 0xA + + + DIV1024 + CLK_RTC_CNT = GCLK_RTC/1024 + 0xB + + + + + COUNTSYNC + Count Read Synchronization Enable + 15 + 1 + + + + + EVCTRL + MODE1 Event Control + 0x4 + 32 + 0x00000000 + + + PEREO0 + Periodic Interval 0 Event Output Enable + 0 + 1 + + + PEREO1 + Periodic Interval 1 Event Output Enable + 1 + 1 + + + PEREO2 + Periodic Interval 2 Event Output Enable + 2 + 1 + + + PEREO3 + Periodic Interval 3 Event Output Enable + 3 + 1 + + + PEREO4 + Periodic Interval 4 Event Output Enable + 4 + 1 + + + PEREO5 + Periodic Interval 5 Event Output Enable + 5 + 1 + + + PEREO6 + Periodic Interval 6 Event Output Enable + 6 + 1 + + + PEREO7 + Periodic Interval 7 Event Output Enable + 7 + 1 + + + CMPEO0 + Compare 0 Event Output Enable + 8 + 1 + + + CMPEO1 + Compare 1 Event Output Enable + 9 + 1 + + + OVFEO + Overflow Event Output Enable + 15 + 1 + + + + + INTENCLR + MODE1 Interrupt Enable Clear + 0x8 + 16 + 0x0000 + + + PER0 + Periodic Interval 0 Interrupt Enable + 0 + 1 + + + PER1 + Periodic Interval 1 Interrupt Enable + 1 + 1 + + + PER2 + Periodic Interval 2 Interrupt Enable + 2 + 1 + + + PER3 + Periodic Interval 3 Interrupt Enable + 3 + 1 + + + PER4 + Periodic Interval 4 Interrupt Enable + 4 + 1 + + + PER5 + Periodic Interval 5 Interrupt Enable + 5 + 1 + + + PER6 + Periodic Interval 6 Interrupt Enable + 6 + 1 + + + PER7 + Periodic Interval 7 Interrupt Enable + 7 + 1 + + + CMP0 + Compare 0 Interrupt Enable + 8 + 1 + + + CMP1 + Compare 1 Interrupt Enable + 9 + 1 + + + OVF + Overflow Interrupt Enable + 15 + 1 + + + + + INTENSET + MODE1 Interrupt Enable Set + 0xA + 16 + 0x0000 + + + PER0 + Periodic Interval 0 Interrupt Enable + 0 + 1 + + + PER1 + Periodic Interval 1 Interrupt Enable + 1 + 1 + + + PER2 + Periodic Interval 2 Interrupt Enable + 2 + 1 + + + PER3 + Periodic Interval 3 Interrupt Enable + 3 + 1 + + + PER4 + Periodic Interval 4 Interrupt Enable + 4 + 1 + + + PER5 + Periodic Interval 5 Interrupt Enable + 5 + 1 + + + PER6 + Periodic Interval 6 Interrupt Enable + 6 + 1 + + + PER7 + Periodic Interval 7 Interrupt Enable + 7 + 1 + + + CMP0 + Compare 0 Interrupt Enable + 8 + 1 + + + CMP1 + Compare 1 Interrupt Enable + 9 + 1 + + + OVF + Overflow Interrupt Enable + 15 + 1 + + + + + INTFLAG + MODE1 Interrupt Flag Status and Clear + 0xC + 16 + 0x0000 + + + PER0 + Periodic Interval 0 + 0 + 1 + + + PER1 + Periodic Interval 1 + 1 + 1 + + + PER2 + Periodic Interval 2 + 2 + 1 + + + PER3 + Periodic Interval 3 + 3 + 1 + + + PER4 + Periodic Interval 4 + 4 + 1 + + + PER5 + Periodic Interval 5 + 5 + 1 + + + PER6 + Periodic Interval 6 + 6 + 1 + + + PER7 + Periodic Interval 7 + 7 + 1 + + + CMP0 + Compare 0 + 8 + 1 + + + CMP1 + Compare 1 + 9 + 1 + + + OVF + Overflow + 15 + 1 + + + + + DBGCTRL + Debug Control + 0xE + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + SYNCBUSY + MODE1 Synchronization Busy Status + 0x10 + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Bit Busy + 0 + 1 + + + ENABLE + Enable Bit Busy + 1 + 1 + + + FREQCORR + FREQCORR Register Busy + 2 + 1 + + + COUNT + COUNT Register Busy + 3 + 1 + + + PER + PER Register Busy + 4 + 1 + + + COMP0 + COMP 0 Register Busy + 5 + 1 + + + COMP1 + COMP 1 Register Busy + 6 + 1 + + + COUNTSYNC + Count Read Synchronization Enable Bit Busy + 15 + 1 + + + + + FREQCORR + Frequency Correction + 0x14 + 8 + 0x00 + + + VALUE + Correction Value + 0 + 7 + + + SIGN + Correction Sign + 7 + 1 + + + + + COUNT + MODE1 Counter Value + 0x18 + 16 + 0x0000 + + + COUNT + Counter Value + 0 + 16 + + + + + PER + MODE1 Counter Period + 0x1C + 16 + 0x0000 + + + PER + Counter Period + 0 + 16 + + + + + 2 + 2 + COMP[%s] + MODE1 Compare n Value + 0x20 + 16 + 0x0000 + + + COMP + Compare Value + 0 + 16 + + + + + + MODE2 + Clock/Calendar with Alarm + MODE0 + RtcMode2 + 0x0 + + CTRLA + MODE2 Control A + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 2 + + MODESelect + + COUNT32 + Mode 0: 32-bit Counter + 0 + + + COUNT16 + Mode 1: 16-bit Counter + 1 + + + CLOCK + Mode 2: Clock/Calendar + 2 + + + + + CLKREP + Clock Representation + 6 + 1 + + + MATCHCLR + Clear on Match + 7 + 1 + + + PRESCALER + Prescaler + 8 + 4 + + PRESCALERSelect + + OFF + CLK_RTC_CNT = GCLK_RTC/1 + 0x0 + + + DIV1 + CLK_RTC_CNT = GCLK_RTC/1 + 0x1 + + + DIV2 + CLK_RTC_CNT = GCLK_RTC/2 + 0x2 + + + DIV4 + CLK_RTC_CNT = GCLK_RTC/4 + 0x3 + + + DIV8 + CLK_RTC_CNT = GCLK_RTC/8 + 0x4 + + + DIV16 + CLK_RTC_CNT = GCLK_RTC/16 + 0x5 + + + DIV32 + CLK_RTC_CNT = GCLK_RTC/32 + 0x6 + + + DIV64 + CLK_RTC_CNT = GCLK_RTC/64 + 0x7 + + + DIV128 + CLK_RTC_CNT = GCLK_RTC/128 + 0x8 + + + DIV256 + CLK_RTC_CNT = GCLK_RTC/256 + 0x9 + + + DIV512 + CLK_RTC_CNT = GCLK_RTC/512 + 0xA + + + DIV1024 + CLK_RTC_CNT = GCLK_RTC/1024 + 0xB + + + + + CLOCKSYNC + Clock Read Synchronization Enable + 15 + 1 + + + + + EVCTRL + MODE2 Event Control + 0x4 + 32 + 0x00000000 + + + PEREO0 + Periodic Interval 0 Event Output Enable + 0 + 1 + + + PEREO1 + Periodic Interval 1 Event Output Enable + 1 + 1 + + + PEREO2 + Periodic Interval 2 Event Output Enable + 2 + 1 + + + PEREO3 + Periodic Interval 3 Event Output Enable + 3 + 1 + + + PEREO4 + Periodic Interval 4 Event Output Enable + 4 + 1 + + + PEREO5 + Periodic Interval 5 Event Output Enable + 5 + 1 + + + PEREO6 + Periodic Interval 6 Event Output Enable + 6 + 1 + + + PEREO7 + Periodic Interval 7 Event Output Enable + 7 + 1 + + + ALARMEO0 + Alarm 0 Event Output Enable + 8 + 1 + + + OVFEO + Overflow Event Output Enable + 15 + 1 + + + + + INTENCLR + MODE2 Interrupt Enable Clear + 0x8 + 16 + 0x0000 + + + PER0 + Periodic Interval 0 Interrupt Enable + 0 + 1 + + + PER1 + Periodic Interval 1 Interrupt Enable + 1 + 1 + + + PER2 + Periodic Interval 2 Interrupt Enable + 2 + 1 + + + PER3 + Periodic Interval 3 Interrupt Enable + 3 + 1 + + + PER4 + Periodic Interval 4 Interrupt Enable + 4 + 1 + + + PER5 + Periodic Interval 5 Interrupt Enable + 5 + 1 + + + PER6 + Periodic Interval 6 Interrupt Enable + 6 + 1 + + + PER7 + Periodic Interval 7 Interrupt Enable + 7 + 1 + + + ALARM0 + Alarm 0 Interrupt Enable + 8 + 1 + + + OVF + Overflow Interrupt Enable + 15 + 1 + + + + + INTENSET + MODE2 Interrupt Enable Set + 0xA + 16 + 0x0000 + + + PER0 + Periodic Interval 0 Enable + 0 + 1 + + + PER1 + Periodic Interval 1 Enable + 1 + 1 + + + PER2 + Periodic Interval 2 Enable + 2 + 1 + + + PER3 + Periodic Interval 3 Enable + 3 + 1 + + + PER4 + Periodic Interval 4 Enable + 4 + 1 + + + PER5 + Periodic Interval 5 Enable + 5 + 1 + + + PER6 + Periodic Interval 6 Enable + 6 + 1 + + + PER7 + Periodic Interval 7 Enable + 7 + 1 + + + ALARM0 + Alarm 0 Interrupt Enable + 8 + 1 + + + OVF + Overflow Interrupt Enable + 15 + 1 + + + + + INTFLAG + MODE2 Interrupt Flag Status and Clear + 0xC + 16 + 0x0000 + + + PER0 + Periodic Interval 0 + 0 + 1 + + + PER1 + Periodic Interval 1 + 1 + 1 + + + PER2 + Periodic Interval 2 + 2 + 1 + + + PER3 + Periodic Interval 3 + 3 + 1 + + + PER4 + Periodic Interval 4 + 4 + 1 + + + PER5 + Periodic Interval 5 + 5 + 1 + + + PER6 + Periodic Interval 6 + 6 + 1 + + + PER7 + Periodic Interval 7 + 7 + 1 + + + ALARM0 + Alarm 0 + 8 + 1 + + + OVF + Overflow + 15 + 1 + + + + + DBGCTRL + Debug Control + 0xE + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + SYNCBUSY + MODE2 Synchronization Busy Status + 0x10 + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Bit Busy + 0 + 1 + + + ENABLE + Enable Bit Busy + 1 + 1 + + + FREQCORR + FREQCORR Register Busy + 2 + 1 + + + CLOCK + CLOCK Register Busy + 3 + 1 + + + ALARM0 + ALARM 0 Register Busy + 5 + 1 + + + MASK0 + MASK 0 Register Busy + 11 + 1 + + + CLOCKSYNC + Clock Read Synchronization Enable Bit Busy + 15 + 1 + + + + + FREQCORR + Frequency Correction + 0x14 + 8 + 0x00 + + + VALUE + Correction Value + 0 + 7 + + + SIGN + Correction Sign + 7 + 1 + + + + + CLOCK + MODE2 Clock Value + 0x18 + 32 + 0x00000000 + + + SECOND + Second + 0 + 6 + + + MINUTE + Minute + 6 + 6 + + + HOUR + Hour + 12 + 5 + + HOURSelect + + AM + AM when CLKREP in 12-hour + 0x00 + + + PM + PM when CLKREP in 12-hour + 0x10 + + + + + DAY + Day + 17 + 5 + + + MONTH + Month + 22 + 4 + + + YEAR + Year + 26 + 6 + + + + + ALARM + MODE2_ALARM Alarm n Value + 0x20 + 32 + 0x00000000 + + + SECOND + Second + 0 + 6 + + + MINUTE + Minute + 6 + 6 + + + HOUR + Hour + 12 + 5 + + HOURSelect + + AM + Morning hour + 0x00 + + + PM + Afternoon hour + 0x10 + + + + + DAY + Day + 17 + 5 + + + MONTH + Month + 22 + 4 + + + YEAR + Year + 26 + 6 + + + + + MASK + MODE2_ALARM Alarm n Mask + 0x24 + 8 + 0x00 + + + SEL + Alarm Mask Selection + 0 + 3 + + SELSelect + + OFF + Alarm Disabled + 0x0 + + + SS + Match seconds only + 0x1 + + + MMSS + Match seconds and minutes only + 0x2 + + + HHMMSS + Match seconds, minutes, and hours only + 0x3 + + + DDHHMMSS + Match seconds, minutes, hours, and days only + 0x4 + + + MMDDHHMMSS + Match seconds, minutes, hours, days, and months only + 0x5 + + + YYMMDDHHMMSS + Match seconds, minutes, hours, days, months, and years + 0x6 + + + + + + + + + + SDADC + U22601.0.1 + Sigma-Delta Analog Digital Converter + SDADC + SDADC_ + 0x42004C00 + + 0 + 0x2F + registers + + + SDADC + 29 + + + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + RUNSTDBY + Run during Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + + + REFCTRL + Reference Control + 0x1 + 8 + 0x00 + + + REFSEL + Reference Selection + 0 + 2 + + REFSELSelect + + INTREF + Internal Bandgap Reference + 0 + + + AREFB + External Reference + 1 + + + DAC + Internal DAC Output + 2 + + + INTVCC + VDDANA + 3 + + + + + REFRANGE + Reference Range + 4 + 2 + + + ONREFBUF + Reference Buffer + 7 + 1 + + + + + CTRLB + Control B + 0x2 + 16 + 0x2000 + + + PRESCALER + Prescaler Configuration + 0 + 8 + + PRESCALERSelect + + DIV2 + Peripheral clock divided by 2 + 0x0 + + + DIV4 + Peripheral clock divided by 4 + 0x1 + + + DIV8 + Peripheral clock divided by 8 + 0x2 + + + DIV16 + Peripheral clock divided by 16 + 0x3 + + + DIV32 + Peripheral clock divided by 32 + 0x4 + + + DIV64 + Peripheral clock divided by 64 + 0x5 + + + DIV128 + Peripheral clock divided by 128 + 0x6 + + + DIV256 + Peripheral clock divided by 256 + 0x7 + + + + + OSR + Over Sampling Ratio + 8 + 3 + + OSRSelect + + OSR64 + Over Sampling Ratio is 64 + 0x0 + + + OSR128 + Over Sampling Ratio is 128 + 0x1 + + + OSR256 + Over Sampling Ratio is 256 + 0x2 + + + OSR512 + Over Sampling Ratio is 512 + 0x3 + + + OSR1024 + Over Sampling Ratio is 1024 + 0x4 + + + + + SKPCNT + Skip Sample Count + 12 + 4 + + + + + EVCTRL + Event Control + 0x4 + 8 + 0x00 + + + FLUSHEI + Flush Event Input Enable + 0 + 1 + + + STARTEI + Start Conversion Event Input Enable + 1 + 1 + + + FLUSHINV + Flush Event Invert Enable + 2 + 1 + + + STARTINV + Satrt Event Invert Enable + 3 + 1 + + + RESRDYEO + Result Ready Event Out + 4 + 1 + + + WINMONEO + Window Monitor Event Out + 5 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x5 + 8 + 0x00 + + + RESRDY + Result Ready Interrupt Disable + 0 + 1 + + + OVERRUN + Overrun Interrupt Disable + 1 + 1 + + + WINMON + Window Monitor Interrupt Disable + 2 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x6 + 8 + 0x00 + + + RESRDY + Result Ready Interrupt Enable + 0 + 1 + + + OVERRUN + Overrun Interrupt Enable + 1 + 1 + + + WINMON + Window Monitor Interrupt Enable + 2 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x7 + 8 + 0x00 + + + RESRDY + Result Ready Interrupt Flag + 0 + 1 + + + OVERRUN + Overrun Interrupt Flag + 1 + 1 + + + WINMON + Window Monitor Interrupt Flag + 2 + 1 + + + + + SEQSTATUS + Sequence Status + 0x8 + 8 + read-only + 0x00 + + + SEQSTATE + Sequence State + 0 + 4 + + + SEQBUSY + Sequence Busy + 7 + 1 + + + + + INPUTCTRL + Input Control + 0x9 + 8 + 0x00 + + + MUXSEL + SDADC Input Selection + 0 + 4 + + MUXSELSelect + + AIN0 + SDADC AIN0 Pin + 0x0 + + + AIN1 + SDADC AIN1 Pin + 0x1 + + + AIN2 + SDADC AIN2 Pin + 0x2 + + + + + + + CTRLC + Control C + 0xA + 8 + 0x00 + + + FREERUN + Free Running Mode + 0 + 1 + + + + + WINCTRL + Window Monitor Control + 0xB + 8 + 0x00 + + + WINMODE + Window Monitor Mode + 0 + 3 + + + + + WINLT + Window Monitor Lower Threshold + 0xC + 32 + 0x00000000 + + + WINLT + Window Lower Threshold + 0 + 24 + + + + + WINUT + Window Monitor Upper Threshold + 0x10 + 32 + 0x00000000 + + + WINUT + Window Upper Threshold + 0 + 24 + + + + + OFFSETCORR + Offset Correction + 0x14 + 32 + 0x00000000 + + + OFFSETCORR + Offset Correction Value + 0 + 24 + + + + + GAINCORR + Gain Correction + 0x18 + 16 + 0x0001 + + + GAINCORR + Gain Correction Value + 0 + 14 + + + + + SHIFTCORR + Shift Correction + 0x1A + 8 + 0x00 + + + SHIFTCORR + Shift Correction Value + 0 + 4 + + + + + SWTRIG + Software Trigger + 0x1C + 8 + 0x00 + + + FLUSH + SDADC Flush + 0 + 1 + + + START + Start SDADC Conversion + 1 + 1 + + + + + SYNCBUSY + Synchronization Busy + 0x20 + 32 + read-only + 0x00000000 + + + SWRST + SWRST Synchronization Busy + 0 + 1 + + + ENABLE + ENABLE Synchronization Busy + 1 + 1 + + + CTRLC + CTRLC Synchronization Busy + 2 + 1 + + + INPUTCTRL + INPUTCTRL Synchronization Busy + 3 + 1 + + + WINCTRL + WINCTRL Synchronization Busy + 4 + 1 + + + WINLT + WINLT Synchronization Busy + 5 + 1 + + + WINUT + WINUT Synchronization Busy + 6 + 1 + + + OFFSETCORR + OFFSETCTRL Synchronization Busy + 7 + 1 + + + GAINCORR + GAINCORR Synchronization Busy + 8 + 1 + + + SHIFTCORR + SHIFTCORR Synchronization Busy + 9 + 1 + + + SWTRIG + SWTRG Synchronization Busy + 10 + 1 + + + ANACTRL + ANACTRL Synchronization Busy + 11 + 1 + + + + + RESULT + Result + 0x24 + 32 + read-only + 0x00000000 + + + RESULT + Result Value + 0 + 24 + + + RESERVED + 24 + 8 + + + + + SEQCTRL + Sequence Control + 0x28 + 8 + 0x00 + + + SEQEN + Enable Positive Input in the Sequence + 0 + 3 + + + + + ANACTRL + Analog Control + 0x2C + 8 + 0x00 + + + CTRSDADC + SDADC Control + 0 + 6 + + + ONCHOP + Chopper + 6 + 1 + + + BUFTEST + BUFTEST + 7 + 1 + + + + + DBGCTRL + Debug Control + 0x2E + 8 + 0x00 + + + DBGRUN + Debug Run + 0 + 1 + + + + + + + SERCOM0 + U22013.1.1 + Serial Communication Interface + SERCOM + SERCOM_ + 0x42000400 + + 0 + 0x31 + registers + + + SERCOM0 + 9 + + + + I2CM + I2C Master Mode + SercomI2cm + 0x0 + + CTRLA + I2CM Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run in Standby + 7 + 1 + + + PINOUT + Pin Usage + 16 + 1 + + + SDAHOLD + SDA Hold Time + 20 + 2 + + SDAHOLDSelect + + DISABLE + Disabled + 0x0 + + + 75NS + 50-100ns hold time + 0x1 + + + 450NS + 300-600ns hold time + 0x2 + + + 600NS + 400-800ns hold time + 0x3 + + + + + MEXTTOEN + Master SCL Low Extend Timeout + 22 + 1 + + + SEXTTOEN + Slave SCL Low Extend Timeout + 23 + 1 + + + SPEED + Transfer Speed + 24 + 2 + + SPEEDSelect + + STANDARD_AND_FAST_MODE + Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz + 0x0 + + + FASTPLUS_MODE + Fast-mode Plus Upto 1MHz + 0x1 + + + HIGH_SPEED_MODE + High-speed mode Upto 3.4MHz + 0x2 + + + + + SCLSM + SCL Clock Stretch Mode + 27 + 1 + + + INACTOUT + Inactive Time-Out + 28 + 2 + + INACTOUTSelect + + DISABLE + Disabled + 0x0 + + + 55US + 5-6 SCL Time-Out(50-60us) + 0x1 + + + 105US + 10-11 SCL Time-Out(100-110us) + 0x2 + + + 205US + 20-21 SCL Time-Out(200-210us) + 0x3 + + + + + LOWTOUTEN + SCL Low Timeout Enable + 30 + 1 + + + + + CTRLB + I2CM Control B + 0x4 + 32 + 0x00000000 + + + SMEN + Smart Mode Enable + 8 + 1 + + + QCEN + Quick Command Enable + 9 + 1 + + + CMD + Command + 16 + 2 + + + ACKACT + Acknowledge Action + 18 + 1 + + + + + BAUD + I2CM Baud Rate + 0xC + 32 + 0x00000000 + + + BAUD + Baud Rate Value + 0 + 8 + + + BAUDLOW + Baud Rate Value Low + 8 + 8 + + + HSBAUD + High Speed Baud Rate Value + 16 + 8 + + + HSBAUDLOW + High Speed Baud Rate Value Low + 24 + 8 + + + + + INTENCLR + I2CM Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + MB + Master On Bus Interrupt Disable + 0 + 1 + + + SB + Slave On Bus Interrupt Disable + 1 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + I2CM Interrupt Enable Set + 0x16 + 8 + 0x00 + + + MB + Master On Bus Interrupt Enable + 0 + 1 + + + SB + Slave On Bus Interrupt Enable + 1 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + I2CM Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + MB + Master On Bus Interrupt + 0 + 1 + + + SB + Slave On Bus Interrupt + 1 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + I2CM Status + 0x1A + 16 + 0x0000 + + + BUSERR + Bus Error + 0 + 1 + + + ARBLOST + Arbitration Lost + 1 + 1 + + + RXNACK + Received Not Acknowledge + 2 + 1 + + + BUSSTATE + Bus State + 4 + 2 + + + LOWTOUT + SCL Low Timeout + 6 + 1 + + + CLKHOLD + Clock Hold + 7 + 1 + + + MEXTTOUT + Master SCL Low Extend Timeout + 8 + 1 + + + SEXTTOUT + Slave SCL Low Extend Timeout + 9 + 1 + + + LENERR + Length Error + 10 + 1 + + + + + SYNCBUSY + I2CM Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + SYSOP + System Operation Synchronization Busy + 2 + 1 + + + + + ADDR + I2CM Address + 0x24 + 32 + 0x00000000 + + + ADDR + Address Value + 0 + 11 + + + LENEN + Length Enable + 13 + 1 + + + HS + High Speed Mode + 14 + 1 + + + TENBITEN + Ten Bit Addressing Enable + 15 + 1 + + + LEN + Length + 16 + 8 + + + + + DATA + I2CM Data + 0x28 + 8 + 0x00 + + + DATA + Data Value + 0 + 8 + + + + + DBGCTRL + I2CM Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + I2CS + I2C Slave Mode + I2CM + SercomI2cs + 0x0 + + CTRLA + I2CS Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + PINOUT + Pin Usage + 16 + 1 + + + SDAHOLD + SDA Hold Time + 20 + 2 + + SDAHOLDSelect + + DISABLE + Disabled + 0x0 + + + 75NS + 50-100ns hold time + 0x1 + + + 450NS + 300-600ns hold time + 0x2 + + + 600NS + 400-800ns hold time + 0x3 + + + + + SEXTTOEN + Slave SCL Low Extend Timeout + 23 + 1 + + + SPEED + Transfer Speed + 24 + 2 + + SPEEDSelect + + STANDARD_AND_FAST_MODE + Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz + 0x0 + + + FASTPLUS_MODE + Fast-mode Plus Upto 1MHz + 0x1 + + + HIGH_SPEED_MODE + High-speed mode Upto 3.4MHz + 0x2 + + + + + SCLSM + SCL Clock Stretch Mode + 27 + 1 + + + LOWTOUTEN + SCL Low Timeout Enable + 30 + 1 + + + + + CTRLB + I2CS Control B + 0x4 + 32 + 0x00000000 + + + SMEN + Smart Mode Enable + 8 + 1 + + + GCMD + PMBus Group Command + 9 + 1 + + + AACKEN + Automatic Address Acknowledge + 10 + 1 + + + AMODE + Address Mode + 14 + 2 + + + CMD + Command + 16 + 2 + + + ACKACT + Acknowledge Action + 18 + 1 + + + + + INTENCLR + I2CS Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + PREC + Stop Received Interrupt Disable + 0 + 1 + + + AMATCH + Address Match Interrupt Disable + 1 + 1 + + + DRDY + Data Interrupt Disable + 2 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + I2CS Interrupt Enable Set + 0x16 + 8 + 0x00 + + + PREC + Stop Received Interrupt Enable + 0 + 1 + + + AMATCH + Address Match Interrupt Enable + 1 + 1 + + + DRDY + Data Interrupt Enable + 2 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + I2CS Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + PREC + Stop Received Interrupt + 0 + 1 + + + AMATCH + Address Match Interrupt + 1 + 1 + + + DRDY + Data Interrupt + 2 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + I2CS Status + 0x1A + 16 + 0x0000 + + + BUSERR + Bus Error + 0 + 1 + + + COLL + Transmit Collision + 1 + 1 + + + RXNACK + Received Not Acknowledge + 2 + 1 + + + DIR + Read/Write Direction + 3 + 1 + + + SR + Repeated Start + 4 + 1 + + + LOWTOUT + SCL Low Timeout + 6 + 1 + + + CLKHOLD + Clock Hold + 7 + 1 + + + SEXTTOUT + Slave SCL Low Extend Timeout + 9 + 1 + + + HS + High Speed + 10 + 1 + + + + + SYNCBUSY + I2CS Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + + + ADDR + I2CS Address + 0x24 + 32 + 0x00000000 + + + GENCEN + General Call Address Enable + 0 + 1 + + + ADDR + Address Value + 1 + 10 + + + TENBITEN + Ten Bit Addressing Enable + 15 + 1 + + + ADDRMASK + Address Mask + 17 + 10 + + + + + DATA + I2CS Data + 0x28 + 8 + 0x00 + + + DATA + Data Value + 0 + 8 + + + + + + SPIS + SPI Slave Mode + I2CM + SercomSpis + 0x0 + + CTRLA + SPIS Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + IBON + Immediate Buffer Overflow Notification + 8 + 1 + + + DOPO + Data Out Pinout + 16 + 2 + + DOPOSelect + + PAD0 + DO on PAD[0], SCK on PAD[1] and SS on PAD[2] + 0x0 + + + PAD1 + DO on PAD[2], SCK on PAD[3] and SS on PAD[1] + 0x1 + + + PAD2 + DO on PAD[3], SCK on PAD[1] and SS on PAD[2] + 0x2 + + + PAD3 + DO on PAD[0], SCK on PAD[3] and SS on PAD[1] + 0x3 + + + + + DIPO + Data In Pinout + 20 + 2 + + DIPOSelect + + PAD0 + SERCOM PAD[0] + 0x0 + + + PAD1 + SERCOM PAD[1] + 0x1 + + + PAD2 + SERCOM PAD[2] + 0x2 + + + PAD3 + SERCOM PAD[3] + 0x3 + + + + + FORM + Frame Format + 24 + 4 + + FORMSelect + + SPI_FRAME + SPI Frame + 0x0 + + + SPI_FRAME_WITH_ADDR + SPI Frame with Addr + 0x2 + + + + + CPHA + Clock Phase + 28 + 1 + + CPHASelect + + LEADING_EDGE + The data is sampled on a leading SCK edge and changed on a trailing SCK edge + 0x0 + + + TRAILING_EDGE + The data is sampled on a trailing SCK edge and changed on a leading SCK edge + 0x1 + + + + + CPOL + Clock Polarity + 29 + 1 + + CPOLSelect + + IDLE_LOW + SCK is low when idle + 0x0 + + + IDLE_HIGH + SCK is high when idle + 0x1 + + + + + DORD + Data Order + 30 + 1 + + DORDSelect + + MSB + MSB is transferred first + 0x0 + + + LSB + LSB is transferred first + 0x1 + + + + + + + CTRLB + SPIS Control B + 0x4 + 32 + 0x00000000 + + + CHSIZE + Character Size + 0 + 3 + + CHSIZESelect + + 8_BIT + 8 bits + 0x0 + + + 9_BIT + 9 bits + 0x1 + + + + + PLOADEN + Data Preload Enable + 6 + 1 + + + SSDE + Slave Select Low Detect Enable + 9 + 1 + + + MSSEN + Master Slave Select Enable + 13 + 1 + + + AMODE + Address Mode + 14 + 2 + + AMODESelect + + MASK + SPI Address mask + 0x0 + + + 2_ADDRESSES + Two unique Addressess + 0x1 + + + RANGE + Address Range + 0x2 + + + + + RXEN + Receiver Enable + 17 + 1 + + + + + BAUD + SPIS Baud Rate + 0xC + 8 + 0x00 + + + BAUD + Baud Rate Value + 0 + 8 + + + + + INTENCLR + SPIS Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Disable + 0 + 1 + + + TXC + Transmit Complete Interrupt Disable + 1 + 1 + + + RXC + Receive Complete Interrupt Disable + 2 + 1 + + + SSL + Slave Select Low Interrupt Disable + 3 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + SPIS Interrupt Enable Set + 0x16 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Enable + 0 + 1 + + + TXC + Transmit Complete Interrupt Enable + 1 + 1 + + + RXC + Receive Complete Interrupt Enable + 2 + 1 + + + SSL + Slave Select Low Interrupt Enable + 3 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + SPIS Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt + 0 + 1 + + + TXC + Transmit Complete Interrupt + 1 + 1 + + + RXC + Receive Complete Interrupt + 2 + 1 + + + SSL + Slave Select Low Interrupt Flag + 3 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + SPIS Status + 0x1A + 16 + 0x0000 + + + BUFOVF + Buffer Overflow + 2 + 1 + + + + + SYNCBUSY + SPIS Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + CTRLB + CTRLB Synchronization Busy + 2 + 1 + + + + + ADDR + SPIS Address + 0x24 + 32 + 0x00000000 + + + ADDR + Address Value + 0 + 8 + + + ADDRMASK + Address Mask + 16 + 8 + + + + + DATA + SPIS Data + 0x28 + 32 + 0x00000000 + + + DATA + Data Value + 0 + 9 + + + + + DBGCTRL + SPIS Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + SPIM + SPI Master Mode + I2CM + SercomSpim + 0x0 + + CTRLA + SPIM Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + IBON + Immediate Buffer Overflow Notification + 8 + 1 + + + DOPO + Data Out Pinout + 16 + 2 + + DOPOSelect + + PAD0 + DO on PAD[0], SCK on PAD[1] and SS on PAD[2] + 0x0 + + + PAD1 + DO on PAD[2], SCK on PAD[3] and SS on PAD[1] + 0x1 + + + PAD2 + DO on PAD[3], SCK on PAD[1] and SS on PAD[2] + 0x2 + + + PAD3 + DO on PAD[0], SCK on PAD[3] and SS on PAD[1] + 0x3 + + + + + DIPO + Data In Pinout + 20 + 2 + + DIPOSelect + + PAD0 + SERCOM PAD[0] + 0x0 + + + PAD1 + SERCOM PAD[1] + 0x1 + + + PAD2 + SERCOM PAD[2] + 0x2 + + + PAD3 + SERCOM PAD[3] + 0x3 + + + + + FORM + Frame Format + 24 + 4 + + FORMSelect + + SPI_FRAME + SPI Frame + 0x0 + + + SPI_FRAME_WITH_ADDR + SPI Frame with Addr + 0x2 + + + + + CPHA + Clock Phase + 28 + 1 + + CPHASelect + + LEADING_EDGE + The data is sampled on a leading SCK edge and changed on a trailing SCK edge + 0x0 + + + TRAILING_EDGE + The data is sampled on a trailing SCK edge and changed on a leading SCK edge + 0x1 + + + + + CPOL + Clock Polarity + 29 + 1 + + CPOLSelect + + IDLE_LOW + SCK is low when idle + 0x0 + + + IDLE_HIGH + SCK is high when idle + 0x1 + + + + + DORD + Data Order + 30 + 1 + + DORDSelect + + MSB + MSB is transferred first + 0x0 + + + LSB + LSB is transferred first + 0x1 + + + + + + + CTRLB + SPIM Control B + 0x4 + 32 + 0x00000000 + + + CHSIZE + Character Size + 0 + 3 + + CHSIZESelect + + 8_BIT + 8 bits + 0x0 + + + 9_BIT + 9 bits + 0x1 + + + + + PLOADEN + Data Preload Enable + 6 + 1 + + + SSDE + Slave Select Low Detect Enable + 9 + 1 + + + MSSEN + Master Slave Select Enable + 13 + 1 + + + AMODE + Address Mode + 14 + 2 + + AMODESelect + + MASK + SPI Address mask + 0x0 + + + 2_ADDRESSES + Two unique Addressess + 0x1 + + + RANGE + Address Range + 0x2 + + + + + RXEN + Receiver Enable + 17 + 1 + + + + + BAUD + SPIM Baud Rate + 0xC + 8 + 0x00 + + + BAUD + Baud Rate Value + 0 + 8 + + + + + INTENCLR + SPIM Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Disable + 0 + 1 + + + TXC + Transmit Complete Interrupt Disable + 1 + 1 + + + RXC + Receive Complete Interrupt Disable + 2 + 1 + + + SSL + Slave Select Low Interrupt Disable + 3 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + SPIM Interrupt Enable Set + 0x16 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Enable + 0 + 1 + + + TXC + Transmit Complete Interrupt Enable + 1 + 1 + + + RXC + Receive Complete Interrupt Enable + 2 + 1 + + + SSL + Slave Select Low Interrupt Enable + 3 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + SPIM Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt + 0 + 1 + + + TXC + Transmit Complete Interrupt + 1 + 1 + + + RXC + Receive Complete Interrupt + 2 + 1 + + + SSL + Slave Select Low Interrupt Flag + 3 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + SPIM Status + 0x1A + 16 + 0x0000 + + + BUFOVF + Buffer Overflow + 2 + 1 + + + + + SYNCBUSY + SPIM Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + CTRLB + CTRLB Synchronization Busy + 2 + 1 + + + + + ADDR + SPIM Address + 0x24 + 32 + 0x00000000 + + + ADDR + Address Value + 0 + 8 + + + ADDRMASK + Address Mask + 16 + 8 + + + + + DATA + SPIM Data + 0x28 + 32 + 0x00000000 + + + DATA + Data Value + 0 + 9 + + + + + DBGCTRL + SPIM Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + USART_EXT + USART EXTERNAL CLOCK Mode + I2CM + SercomUsart_ext + 0x0 + + CTRLA + USART_EXT Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + IBON + Immediate Buffer Overflow Notification + 8 + 1 + + + SAMPR + Sample + 13 + 3 + + SAMPRSelect + + 16X_ARITHMETIC + 16x over-sampling using arithmetic baudrate generation + 0x0 + + + 16X_FRACTIONAL + 16x over-sampling using fractional baudrate generation + 0x1 + + + 8X_ARITHMETIC + 8x over-sampling using arithmetic baudrate generation + 0x2 + + + 8X_FRACTIONAL + 8x over-sampling using fractional baudrate generation + 0x3 + + + 3X_ARITHMETIC + 3x over-sampling using arithmetic baudrate generation + 0x4 + + + + + TXPO + Transmit Data Pinout + 16 + 2 + + TXPOSelect + + PAD0 + SERCOM PAD[0] is used for data transmission + 0x0 + + + PAD2 + SERCOM PAD[2] is used for data transmission + 0x1 + + + + + RXPO + Receive Data Pinout + 20 + 2 + + RXPOSelect + + PAD0 + SERCOM PAD[0] is used for data reception + 0x0 + + + PAD1 + SERCOM PAD[1] is used for data reception + 0x1 + + + PAD2 + SERCOM PAD[2] is used for data reception + 0x2 + + + PAD3 + SERCOM PAD[3] is used for data reception + 0x3 + + + + + SAMPA + Sample Adjustment + 22 + 2 + + + FORM + Frame Format + 24 + 4 + + FORMSelect + + USART_FRAME_NO_PARITY + USART frame + 0x0 + + + USART_FRAME_WITH_PARITY + USART frame with parity + 0x1 + + + USART_FRAME_LIN_MASTER_MODE + LIN Master - Break and sync generation + 0x2 + + + USART_FRAME_AUTO_BAUD_NO_PARITY + Auto-baud - break detection and auto-baud + 0x4 + + + USART_FRAME_AUTO_BAUD_WITH_PARITY + Auto-baud - break detection and auto-baud with parity + 0x5 + + + + + CMODE + Communication Mode + 28 + 1 + + CMODESelect + + ASYNC + Asynchronous Communication + 0x0 + + + SYNC + Synchronous Communication + 0x1 + + + + + CPOL + Clock Polarity + 29 + 1 + + CPOLSelect + + IDLE_LOW + TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge + 0x0 + + + IDLE_HIGH + TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge + 0x1 + + + + + DORD + Data Order + 30 + 1 + + DORDSelect + + MSB + MSB is transmitted first + 0x0 + + + LSB + LSB is transmitted first + 0x1 + + + + + + + CTRLB + USART_EXT Control B + 0x4 + 32 + 0x00000000 + + + CHSIZE + Character Size + 0 + 3 + + CHSIZESelect + + 8_BIT + 8 Bits + 0x0 + + + 9_BIT + 9 Bits + 0x1 + + + 5_BIT + 5 Bits + 0x5 + + + 6_BIT + 6 Bits + 0x6 + + + 7_BIT + 7 Bits + 0x7 + + + + + SBMODE + Stop Bit Mode + 6 + 1 + + SBMODESelect + + 1_BIT + One Stop Bit + 0x0 + + + 2_BIT + Two Stop Bits + 0x1 + + + + + COLDEN + Collision Detection Enable + 8 + 1 + + + SFDE + Start of Frame Detection Enable + 9 + 1 + + + ENC + Encoding Format + 10 + 1 + + + PMODE + Parity Mode + 13 + 1 + + PMODESelect + + EVEN + Even Parity + 0x0 + + + ODD + Odd Parity + 0x1 + + + + + TXEN + Transmitter Enable + 16 + 1 + + + RXEN + Receiver Enable + 17 + 1 + + + LINCMD + LIN Command + 24 + 2 + + + + + CTRLC + USART_EXT Control C + 0x8 + 32 + 0x00000000 + + + GTIME + RS485 Guard Time + 0 + 3 + + + BRKLEN + LIN Master Break Length + 8 + 2 + + + HDRDLY + LIN Master Header Delay + 10 + 2 + + + + + BAUD + USART_EXT Baud Rate + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 16 + + + + + BAUD_FRAC_MODE + USART_EXT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 13 + + + FP + Fractional Part + 13 + 3 + + + + + BAUD_FRACFP_MODE + USART_EXT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 13 + + + FP + Fractional Part + 13 + 3 + + + + + BAUD_USARTFP_MODE + USART_EXT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 16 + + + + + RXPL + USART_EXT Receive Pulse Length + 0xE + 8 + 0x00 + + + RXPL + Receive Pulse Length + 0 + 8 + + + + + INTENCLR + USART_EXT Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Disable + 0 + 1 + + + TXC + Transmit Complete Interrupt Disable + 1 + 1 + + + RXC + Receive Complete Interrupt Disable + 2 + 1 + + + RXS + Receive Start Interrupt Disable + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt Disable + 4 + 1 + + + RXBRK + Break Received Interrupt Disable + 5 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + USART_EXT Interrupt Enable Set + 0x16 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Enable + 0 + 1 + + + TXC + Transmit Complete Interrupt Enable + 1 + 1 + + + RXC + Receive Complete Interrupt Enable + 2 + 1 + + + RXS + Receive Start Interrupt Enable + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt Enable + 4 + 1 + + + RXBRK + Break Received Interrupt Enable + 5 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + USART_EXT Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt + 0 + 1 + + + TXC + Transmit Complete Interrupt + 1 + 1 + + + RXC + Receive Complete Interrupt + 2 + 1 + + + RXS + Receive Start Interrupt + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt + 4 + 1 + + + RXBRK + Break Received Interrupt + 5 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + USART_EXT Status + 0x1A + 16 + 0x0000 + + + PERR + Parity Error + 0 + 1 + + + FERR + Frame Error + 1 + 1 + + + BUFOVF + Buffer Overflow + 2 + 1 + + + CTS + Clear To Send + 3 + 1 + + + ISF + Inconsistent Sync Field + 4 + 1 + + + COLL + Collision Detected + 5 + 1 + + + TXE + Transmitter Empty + 6 + 1 + + + + + SYNCBUSY + USART_EXT Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + CTRLB + CTRLB Synchronization Busy + 2 + 1 + + + + + DATA + USART_EXT Data + 0x28 + 16 + 0x0000 + + + DATA + Data Value + 0 + 9 + + + + + DBGCTRL + USART_EXT Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + USART_INT + USART INTERNAL CLOCK Mode + I2CM + SercomUsart_int + 0x0 + + CTRLA + USART_INT Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + IBON + Immediate Buffer Overflow Notification + 8 + 1 + + + SAMPR + Sample + 13 + 3 + + SAMPRSelect + + 16X_ARITHMETIC + 16x over-sampling using arithmetic baudrate generation + 0x0 + + + 16X_FRACTIONAL + 16x over-sampling using fractional baudrate generation + 0x1 + + + 8X_ARITHMETIC + 8x over-sampling using arithmetic baudrate generation + 0x2 + + + 8X_FRACTIONAL + 8x over-sampling using fractional baudrate generation + 0x3 + + + 3X_ARITHMETIC + 3x over-sampling using arithmetic baudrate generation + 0x4 + + + + + TXPO + Transmit Data Pinout + 16 + 2 + + TXPOSelect + + PAD0 + SERCOM PAD[0] is used for data transmission + 0x0 + + + PAD2 + SERCOM PAD[2] is used for data transmission + 0x1 + + + + + RXPO + Receive Data Pinout + 20 + 2 + + RXPOSelect + + PAD0 + SERCOM PAD[0] is used for data reception + 0x0 + + + PAD1 + SERCOM PAD[1] is used for data reception + 0x1 + + + PAD2 + SERCOM PAD[2] is used for data reception + 0x2 + + + PAD3 + SERCOM PAD[3] is used for data reception + 0x3 + + + + + SAMPA + Sample Adjustment + 22 + 2 + + + FORM + Frame Format + 24 + 4 + + FORMSelect + + USART_FRAME_NO_PARITY + USART frame + 0x0 + + + USART_FRAME_WITH_PARITY + USART frame with parity + 0x1 + + + USART_FRAME_LIN_MASTER_MODE + LIN Master - Break and sync generation + 0x2 + + + USART_FRAME_AUTO_BAUD_NO_PARITY + Auto-baud - break detection and auto-baud + 0x4 + + + USART_FRAME_AUTO_BAUD_WITH_PARITY + Auto-baud - break detection and auto-baud with parity + 0x5 + + + + + CMODE + Communication Mode + 28 + 1 + + CMODESelect + + ASYNC + Asynchronous Communication + 0x0 + + + SYNC + Synchronous Communication + 0x1 + + + + + CPOL + Clock Polarity + 29 + 1 + + CPOLSelect + + IDLE_LOW + TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge + 0x0 + + + IDLE_HIGH + TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge + 0x1 + + + + + DORD + Data Order + 30 + 1 + + DORDSelect + + MSB + MSB is transmitted first + 0x0 + + + LSB + LSB is transmitted first + 0x1 + + + + + + + CTRLB + USART_INT Control B + 0x4 + 32 + 0x00000000 + + + CHSIZE + Character Size + 0 + 3 + + CHSIZESelect + + 8_BIT + 8 Bits + 0x0 + + + 9_BIT + 9 Bits + 0x1 + + + 5_BIT + 5 Bits + 0x5 + + + 6_BIT + 6 Bits + 0x6 + + + 7_BIT + 7 Bits + 0x7 + + + + + SBMODE + Stop Bit Mode + 6 + 1 + + SBMODESelect + + 1_BIT + One Stop Bit + 0x0 + + + 2_BIT + Two Stop Bits + 0x1 + + + + + COLDEN + Collision Detection Enable + 8 + 1 + + + SFDE + Start of Frame Detection Enable + 9 + 1 + + + ENC + Encoding Format + 10 + 1 + + + PMODE + Parity Mode + 13 + 1 + + PMODESelect + + EVEN + Even Parity + 0x0 + + + ODD + Odd Parity + 0x1 + + + + + TXEN + Transmitter Enable + 16 + 1 + + + RXEN + Receiver Enable + 17 + 1 + + + LINCMD + LIN Command + 24 + 2 + + + + + CTRLC + USART_INT Control C + 0x8 + 32 + 0x00000000 + + + GTIME + RS485 Guard Time + 0 + 3 + + + BRKLEN + LIN Master Break Length + 8 + 2 + + + HDRDLY + LIN Master Header Delay + 10 + 2 + + + + + BAUD + USART_INT Baud Rate + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 16 + + + + + BAUD_FRAC_MODE + USART_INT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 13 + + + FP + Fractional Part + 13 + 3 + + + + + BAUD_FRACFP_MODE + USART_INT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 13 + + + FP + Fractional Part + 13 + 3 + + + + + BAUD_USARTFP_MODE + USART_INT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 16 + + + + + RXPL + USART_INT Receive Pulse Length + 0xE + 8 + 0x00 + + + RXPL + Receive Pulse Length + 0 + 8 + + + + + INTENCLR + USART_INT Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Disable + 0 + 1 + + + TXC + Transmit Complete Interrupt Disable + 1 + 1 + + + RXC + Receive Complete Interrupt Disable + 2 + 1 + + + RXS + Receive Start Interrupt Disable + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt Disable + 4 + 1 + + + RXBRK + Break Received Interrupt Disable + 5 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + USART_INT Interrupt Enable Set + 0x16 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Enable + 0 + 1 + + + TXC + Transmit Complete Interrupt Enable + 1 + 1 + + + RXC + Receive Complete Interrupt Enable + 2 + 1 + + + RXS + Receive Start Interrupt Enable + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt Enable + 4 + 1 + + + RXBRK + Break Received Interrupt Enable + 5 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + USART_INT Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt + 0 + 1 + + + TXC + Transmit Complete Interrupt + 1 + 1 + + + RXC + Receive Complete Interrupt + 2 + 1 + + + RXS + Receive Start Interrupt + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt + 4 + 1 + + + RXBRK + Break Received Interrupt + 5 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + USART_INT Status + 0x1A + 16 + 0x0000 + + + PERR + Parity Error + 0 + 1 + + + FERR + Frame Error + 1 + 1 + + + BUFOVF + Buffer Overflow + 2 + 1 + + + CTS + Clear To Send + 3 + 1 + + + ISF + Inconsistent Sync Field + 4 + 1 + + + COLL + Collision Detected + 5 + 1 + + + TXE + Transmitter Empty + 6 + 1 + + + + + SYNCBUSY + USART_INT Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + CTRLB + CTRLB Synchronization Busy + 2 + 1 + + + + + DATA + USART_INT Data + 0x28 + 16 + 0x0000 + + + DATA + Data Value + 0 + 9 + + + + + DBGCTRL + USART_INT Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + + + SERCOM1 + 0x42000800 + + SERCOM1 + 10 + + + + SERCOM2 + 0x42000C00 + + SERCOM2 + 11 + + + + SERCOM3 + 0x42001000 + + SERCOM3 + 12 + + + + SERCOM4 + 0x42001400 + + SERCOM4 + 13 + + + + SERCOM5 + 0x42001800 + + SERCOM5 + 14 + + + + SUPC + U21172.1.1 + Supply Controller + SUPC + SUPC_ + 0x40001800 + + 0 + 0x20 + registers + + + + INTENCLR + Interrupt Enable Clear + 0x0 + 32 + 0x00000000 + + + BODVDDRDY + BODVDD Ready + 0 + 1 + + + BODVDDDET + BODVDD Detection + 1 + 1 + + + BVDDSRDY + BODVDD Synchronization Ready + 2 + 1 + + + BODCORERDY + BODCORE Ready + 3 + 1 + + + BODCOREDET + BODCORE Detection + 4 + 1 + + + BCORESRDY + BODCORE Synchronization Ready + 5 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x4 + 32 + 0x00000000 + + + BODVDDRDY + BODVDD Ready + 0 + 1 + + + BODVDDDET + BODVDD Detection + 1 + 1 + + + BVDDSRDY + BODVDD Synchronization Ready + 2 + 1 + + + BODCORERDY + BODCORE Ready + 3 + 1 + + + BODCOREDET + BODCORE Detection + 4 + 1 + + + BCORESRDY + BODCORE Synchronization Ready + 5 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x8 + 32 + 0x00000000 + + + BODVDDRDY + BODVDD Ready + 0 + 1 + + + BODVDDDET + BODVDD Detection + 1 + 1 + + + BVDDSRDY + BODVDD Synchronization Ready + 2 + 1 + + + BODCORERDY + BODCORE Ready + 3 + 1 + + + BODCOREDET + BODCORE Detection + 4 + 1 + + + BCORESRDY + BODCORE Synchronization Ready + 5 + 1 + + + + + STATUS + Power and Clocks Status + 0xC + 32 + read-only + 0x00000000 + + + BODVDDRDY + BODVDD Ready + 0 + 1 + + + BODVDDDET + BODVDD Detection + 1 + 1 + + + BVDDSRDY + BODVDD Synchronization Ready + 2 + 1 + + + BODCORERDY + BODCORE Ready + 3 + 1 + + + BODCOREDET + BODCORE Detection + 4 + 1 + + + BCORESRDY + BODCORE Synchronization Ready + 5 + 1 + + + + + BODVDD + BODVDD Control + 0x10 + 32 + 0x00000000 + + + ENABLE + Enable + 1 + 1 + + + HYST + Hysteresis Enable + 2 + 1 + + + ACTION + Action when Threshold Crossed + 3 + 2 + + ACTIONSelect + + NONE + No action + 0x0 + + + RESET + The BODVDD generates a reset + 0x1 + + + INT + The BODVDD generates an interrupt + 0x2 + + + + + STDBYCFG + Configuration in Standby mode + 5 + 1 + + + RUNSTDBY + Run during Standby + 6 + 1 + + + ACTCFG + Configuration in Active mode + 8 + 1 + + + PSEL + Prescaler Select + 12 + 4 + + PSELSelect + + DIV2 + Divide clock by 2 + 0x0 + + + DIV4 + Divide clock by 4 + 0x1 + + + DIV8 + Divide clock by 8 + 0x2 + + + DIV16 + Divide clock by 16 + 0x3 + + + DIV32 + Divide clock by 32 + 0x4 + + + DIV64 + Divide clock by 64 + 0x5 + + + DIV128 + Divide clock by 128 + 0x6 + + + DIV256 + Divide clock by 256 + 0x7 + + + DIV512 + Divide clock by 512 + 0x8 + + + DIV1024 + Divide clock by 1024 + 0x9 + + + DIV2048 + Divide clock by 2048 + 0xA + + + DIV4096 + Divide clock by 4096 + 0xB + + + DIV8192 + Divide clock by 8192 + 0xC + + + DIV16384 + Divide clock by 16384 + 0xD + + + DIV32768 + Divide clock by 32768 + 0xE + + + DIV65536 + Divide clock by 65536 + 0xF + + + + + LEVEL + Threshold Level for VDD + 16 + 6 + + + + + BODCORE + BODCORE Control + 0x14 + 32 + 0x00000000 + + + ENABLE + Enable + 1 + 1 + + + HYST + Hysteresis Enable + 2 + 1 + + + ACTION + Action when Threshold Crossed + 3 + 2 + + ACTIONSelect + + NONE + No action + 0x0 + + + RESET + The BODCORE generates a reset + 0x1 + + + INT + The BODCORE generates an interrupt + 0x2 + + + + + STDBYCFG + Configuration in Standby mode + 5 + 1 + + + RUNSTDBY + Run during Standby + 6 + 1 + + + ACTCFG + Configuration in Active mode + 8 + 1 + + + PSEL + Prescaler Select + 12 + 4 + + PSELSelect + + DIV2 + Divide clock by 2 + 0x0 + + + DIV4 + Divide clock by 4 + 0x1 + + + DIV8 + Divide clock by 8 + 0x2 + + + DIV16 + Divide clock by 16 + 0x3 + + + DIV32 + Divide clock by 32 + 0x4 + + + DIV64 + Divide clock by 64 + 0x5 + + + DIV128 + Divide clock by 128 + 0x6 + + + DIV256 + Divide clock by 256 + 0x7 + + + DIV512 + Divide clock by 512 + 0x8 + + + DIV1024 + Divide clock by 1024 + 0x9 + + + DIV2048 + Divide clock by 2048 + 0xA + + + DIV4096 + Divide clock by 4096 + 0xB + + + DIV8192 + Divide clock by 8192 + 0xC + + + DIV16384 + Divide clock by 16384 + 0xD + + + DIV32768 + Divide clock by 32768 + 0xE + + + DIV65536 + Divide clock by 65536 + 0xF + + + + + LEVEL + Threshold Level + 16 + 6 + + + + + VREG + VREG Control + 0x18 + 32 + 0x00000000 + + + ENABLE + Enable + 1 + 1 + + + RUNSTDBY + Run during Standby + 6 + 1 + + + + + VREF + VREF Control + 0x1C + 32 + 0x00000000 + + + TSEN + Temperature Sensor Output Enable + 1 + 1 + + + VREFOE + Voltage Reference Output Enable + 2 + 1 + + + RUNSTDBY + Run during Standby + 6 + 1 + + + ONDEMAND + On Demand Contrl + 7 + 1 + + + SEL + Voltage Reference Selection + 16 + 4 + + SELSelect + + 1V024 + 1.024V voltage reference typical value + 0x0 + + + 2V048 + 2.048V voltage reference typical value + 0x2 + + + 4V096 + 4.096V voltage reference typical value + 0x3 + + + + + + + + + TC0 + U22492.0.0 + Basic Timer Counter + TC + TC_ + 0x42003000 + + 0 + 0x38 + registers + + + TC0 + 20 + + + + COUNT8 + 8-bit Counter Mode + TcCount8 + 0x0 + + CTRLA + Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Timer Counter Mode + 2 + 2 + + MODESelect + + COUNT16 + Counter in 16-bit mode + 0 + + + COUNT8 + Counter in 8-bit mode + 1 + + + COUNT32 + Counter in 32-bit mode + 2 + + + + + PRESCSYNC + Prescaler and Counter Synchronization + 4 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset the counter on next generic clock + 0 + + + PRESC + Reload or reset the counter on next prescaler clock + 1 + + + RESYNC + Reload or reset the counter on next generic clock and reset the prescaler counter + 2 + + + + + RUNSTDBY + Run during Standby + 6 + 1 + + + ONDEMAND + Clock On Demand + 7 + 1 + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + Prescaler: GCLK_TC + 0 + + + DIV2 + Prescaler: GCLK_TC/2 + 1 + + + DIV4 + Prescaler: GCLK_TC/4 + 2 + + + DIV8 + Prescaler: GCLK_TC/8 + 3 + + + DIV16 + Prescaler: GCLK_TC/16 + 4 + + + DIV64 + Prescaler: GCLK_TC/64 + 5 + + + DIV256 + Prescaler: GCLK_TC/256 + 6 + + + DIV1024 + Prescaler: GCLK_TC/1024 + 7 + + + + + ALOCK + Auto Lock + 11 + 1 + + + CAPTEN0 + Capture Channel 0 Enable + 16 + 1 + + + CAPTEN1 + Capture Channel 1 Enable + 17 + 1 + + + COPEN0 + Capture On Pin 0 Enable + 20 + 1 + + + COPEN1 + Capture On Pin 1 Enable + 21 + 1 + + + + + CTRLBCLR + Control B Clear + 0x4 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot on Counter + 2 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + UPDATE + Force update of double-buffered register + 3 + + + READSYNC + Force a read synchronization of COUNT + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + CTRLBSET + Control B Set + 0x5 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot on Counter + 2 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + UPDATE + Force update of double-buffered register + 3 + + + READSYNC + Force a read synchronization of COUNT + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + EVCTRL + Event Control + 0x6 + 16 + 0x0000 + + + EVACT + Event Action + 0 + 3 + + EVACTSelect + + OFF + Event action disabled + 0 + + + RETRIGGER + Start, restart or retrigger TC on event + 1 + + + COUNT + Count on event + 2 + + + START + Start TC on event + 3 + + + STAMP + Time stamp capture + 4 + + + PPW + Period catured in CC0, pulse width in CC1 + 5 + + + PWP + Period catured in CC1, pulse width in CC0 + 6 + + + PW + Pulse width capture + 7 + + + + + TCINV + TC Event Input Polarity + 4 + 1 + + + TCEI + TC Event Enable + 5 + 1 + + + OVFEO + Event Output Enable + 8 + 1 + + + MCEO0 + MC Event Output Enable 0 + 12 + 1 + + + MCEO1 + MC Event Output Enable 1 + 13 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x8 + 8 + 0x00 + + + OVF + OVF Interrupt Disable + 0 + 1 + + + ERR + ERR Interrupt Disable + 1 + 1 + + + MC0 + MC Interrupt Disable 0 + 4 + 1 + + + MC1 + MC Interrupt Disable 1 + 5 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x9 + 8 + 0x00 + + + OVF + OVF Interrupt Enable + 0 + 1 + + + ERR + ERR Interrupt Enable + 1 + 1 + + + MC0 + MC Interrupt Enable 0 + 4 + 1 + + + MC1 + MC Interrupt Enable 1 + 5 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0xA + 8 + 0x00 + + + OVF + OVF Interrupt Flag + 0 + 1 + + + ERR + ERR Interrupt Flag + 1 + 1 + + + MC0 + MC Interrupt Flag 0 + 4 + 1 + + + MC1 + MC Interrupt Flag 1 + 5 + 1 + + + + + STATUS + Status + 0xB + 8 + 0x01 + + + STOP + Stop Status Flag + 0 + 1 + + + SLAVE + Slave Status Flag + 1 + 1 + + + PERBUFV + Synchronization Busy Status + 3 + 1 + + + CCBUFV0 + Compare channel buffer 0 valid + 4 + 1 + + + CCBUFV1 + Compare channel buffer 1 valid + 5 + 1 + + + + + WAVE + Waveform Generation Control + 0xC + 8 + 0x00 + + + WAVEGEN + Waveform Generation Mode + 0 + 2 + + WAVEGENSelect + + NFRQ + Normal frequency + 0 + + + MFRQ + Match frequency + 1 + + + NPWM + Normal PWM + 2 + + + MPWM + Match PWM + 3 + + + + + + + DRVCTRL + Control C + 0xD + 8 + 0x00 + + + INVEN0 + Output Waveform Invert Enable 0 + 0 + 1 + + + INVEN1 + Output Waveform Invert Enable 1 + 1 + 1 + + + + + DBGCTRL + Debug Control + 0xF + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + SYNCBUSY + Synchronization Status + 0x10 + 32 + read-only + 0x00000000 + + + SWRST + swrst + 0 + 1 + + + ENABLE + enable + 1 + 1 + + + CTRLB + CTRLB + 2 + 1 + + + STATUS + STATUS + 3 + 1 + + + COUNT + Counter + 4 + 1 + + + PER + Period + 5 + 1 + + + CC0 + Compare Channel 0 + 6 + 1 + + + CC1 + Compare Channel 1 + 7 + 1 + + + + + COUNT + COUNT8 Count + 0x14 + 8 + 0x00 + + + COUNT + Counter Value + 0 + 8 + + + + + PER + COUNT8 Period + 0x1B + 8 + 0xFF + + + PER + Period Value + 0 + 8 + + + + + 2 + 1 + CC[%s] + COUNT8 Compare and Capture + 0x1C + 8 + 0x00 + + + CC + Counter/Compare Value + 0 + 8 + + + + + PERBUF + COUNT8 Period Buffer + 0x2F + 8 + 0xFF + + + PERBUF + Period Buffer Value + 0 + 8 + + + + + 2 + 1 + CCBUF[%s] + COUNT8 Compare and Capture Buffer + 0x30 + 8 + 0x00 + + + CCBUF + Counter/Compare Buffer Value + 0 + 8 + + + + + + COUNT16 + 16-bit Counter Mode + COUNT8 + TcCount16 + 0x0 + + CTRLA + Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Timer Counter Mode + 2 + 2 + + MODESelect + + COUNT16 + Counter in 16-bit mode + 0 + + + COUNT8 + Counter in 8-bit mode + 1 + + + COUNT32 + Counter in 32-bit mode + 2 + + + + + PRESCSYNC + Prescaler and Counter Synchronization + 4 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset the counter on next generic clock + 0 + + + PRESC + Reload or reset the counter on next prescaler clock + 1 + + + RESYNC + Reload or reset the counter on next generic clock and reset the prescaler counter + 2 + + + + + RUNSTDBY + Run during Standby + 6 + 1 + + + ONDEMAND + Clock On Demand + 7 + 1 + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + Prescaler: GCLK_TC + 0 + + + DIV2 + Prescaler: GCLK_TC/2 + 1 + + + DIV4 + Prescaler: GCLK_TC/4 + 2 + + + DIV8 + Prescaler: GCLK_TC/8 + 3 + + + DIV16 + Prescaler: GCLK_TC/16 + 4 + + + DIV64 + Prescaler: GCLK_TC/64 + 5 + + + DIV256 + Prescaler: GCLK_TC/256 + 6 + + + DIV1024 + Prescaler: GCLK_TC/1024 + 7 + + + + + ALOCK + Auto Lock + 11 + 1 + + + CAPTEN0 + Capture Channel 0 Enable + 16 + 1 + + + CAPTEN1 + Capture Channel 1 Enable + 17 + 1 + + + COPEN0 + Capture On Pin 0 Enable + 20 + 1 + + + COPEN1 + Capture On Pin 1 Enable + 21 + 1 + + + + + CTRLBCLR + Control B Clear + 0x4 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot on Counter + 2 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + UPDATE + Force update of double-buffered register + 3 + + + READSYNC + Force a read synchronization of COUNT + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + CTRLBSET + Control B Set + 0x5 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot on Counter + 2 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + UPDATE + Force update of double-buffered register + 3 + + + READSYNC + Force a read synchronization of COUNT + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + EVCTRL + Event Control + 0x6 + 16 + 0x0000 + + + EVACT + Event Action + 0 + 3 + + EVACTSelect + + OFF + Event action disabled + 0 + + + RETRIGGER + Start, restart or retrigger TC on event + 1 + + + COUNT + Count on event + 2 + + + START + Start TC on event + 3 + + + STAMP + Time stamp capture + 4 + + + PPW + Period catured in CC0, pulse width in CC1 + 5 + + + PWP + Period catured in CC1, pulse width in CC0 + 6 + + + PW + Pulse width capture + 7 + + + + + TCINV + TC Event Input Polarity + 4 + 1 + + + TCEI + TC Event Enable + 5 + 1 + + + OVFEO + Event Output Enable + 8 + 1 + + + MCEO0 + MC Event Output Enable 0 + 12 + 1 + + + MCEO1 + MC Event Output Enable 1 + 13 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x8 + 8 + 0x00 + + + OVF + OVF Interrupt Disable + 0 + 1 + + + ERR + ERR Interrupt Disable + 1 + 1 + + + MC0 + MC Interrupt Disable 0 + 4 + 1 + + + MC1 + MC Interrupt Disable 1 + 5 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x9 + 8 + 0x00 + + + OVF + OVF Interrupt Enable + 0 + 1 + + + ERR + ERR Interrupt Enable + 1 + 1 + + + MC0 + MC Interrupt Enable 0 + 4 + 1 + + + MC1 + MC Interrupt Enable 1 + 5 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0xA + 8 + 0x00 + + + OVF + OVF Interrupt Flag + 0 + 1 + + + ERR + ERR Interrupt Flag + 1 + 1 + + + MC0 + MC Interrupt Flag 0 + 4 + 1 + + + MC1 + MC Interrupt Flag 1 + 5 + 1 + + + + + STATUS + Status + 0xB + 8 + 0x01 + + + STOP + Stop Status Flag + 0 + 1 + + + SLAVE + Slave Status Flag + 1 + 1 + + + PERBUFV + Synchronization Busy Status + 3 + 1 + + + CCBUFV0 + Compare channel buffer 0 valid + 4 + 1 + + + CCBUFV1 + Compare channel buffer 1 valid + 5 + 1 + + + + + WAVE + Waveform Generation Control + 0xC + 8 + 0x00 + + + WAVEGEN + Waveform Generation Mode + 0 + 2 + + WAVEGENSelect + + NFRQ + Normal frequency + 0 + + + MFRQ + Match frequency + 1 + + + NPWM + Normal PWM + 2 + + + MPWM + Match PWM + 3 + + + + + + + DRVCTRL + Control C + 0xD + 8 + 0x00 + + + INVEN0 + Output Waveform Invert Enable 0 + 0 + 1 + + + INVEN1 + Output Waveform Invert Enable 1 + 1 + 1 + + + + + DBGCTRL + Debug Control + 0xF + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + SYNCBUSY + Synchronization Status + 0x10 + 32 + read-only + 0x00000000 + + + SWRST + swrst + 0 + 1 + + + ENABLE + enable + 1 + 1 + + + CTRLB + CTRLB + 2 + 1 + + + STATUS + STATUS + 3 + 1 + + + COUNT + Counter + 4 + 1 + + + PER + Period + 5 + 1 + + + CC0 + Compare Channel 0 + 6 + 1 + + + CC1 + Compare Channel 1 + 7 + 1 + + + + + COUNT + COUNT16 Count + 0x14 + 16 + 0x0000 + + + COUNT + Counter Value + 0 + 16 + + + + + 2 + 2 + CC[%s] + COUNT16 Compare and Capture + 0x1C + 16 + 0x0000 + + + CC + Counter/Compare Value + 0 + 16 + + + + + 2 + 2 + CCBUF[%s] + COUNT16 Compare and Capture Buffer + 0x30 + 16 + 0x0000 + + + CCBUF + Counter/Compare Buffer Value + 0 + 16 + + + + + + COUNT32 + 32-bit Counter Mode + COUNT8 + TcCount32 + 0x0 + + CTRLA + Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Timer Counter Mode + 2 + 2 + + MODESelect + + COUNT16 + Counter in 16-bit mode + 0 + + + COUNT8 + Counter in 8-bit mode + 1 + + + COUNT32 + Counter in 32-bit mode + 2 + + + + + PRESCSYNC + Prescaler and Counter Synchronization + 4 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset the counter on next generic clock + 0 + + + PRESC + Reload or reset the counter on next prescaler clock + 1 + + + RESYNC + Reload or reset the counter on next generic clock and reset the prescaler counter + 2 + + + + + RUNSTDBY + Run during Standby + 6 + 1 + + + ONDEMAND + Clock On Demand + 7 + 1 + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + Prescaler: GCLK_TC + 0 + + + DIV2 + Prescaler: GCLK_TC/2 + 1 + + + DIV4 + Prescaler: GCLK_TC/4 + 2 + + + DIV8 + Prescaler: GCLK_TC/8 + 3 + + + DIV16 + Prescaler: GCLK_TC/16 + 4 + + + DIV64 + Prescaler: GCLK_TC/64 + 5 + + + DIV256 + Prescaler: GCLK_TC/256 + 6 + + + DIV1024 + Prescaler: GCLK_TC/1024 + 7 + + + + + ALOCK + Auto Lock + 11 + 1 + + + CAPTEN0 + Capture Channel 0 Enable + 16 + 1 + + + CAPTEN1 + Capture Channel 1 Enable + 17 + 1 + + + COPEN0 + Capture On Pin 0 Enable + 20 + 1 + + + COPEN1 + Capture On Pin 1 Enable + 21 + 1 + + + + + CTRLBCLR + Control B Clear + 0x4 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot on Counter + 2 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + UPDATE + Force update of double-buffered register + 3 + + + READSYNC + Force a read synchronization of COUNT + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + CTRLBSET + Control B Set + 0x5 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot on Counter + 2 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + UPDATE + Force update of double-buffered register + 3 + + + READSYNC + Force a read synchronization of COUNT + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + EVCTRL + Event Control + 0x6 + 16 + 0x0000 + + + EVACT + Event Action + 0 + 3 + + EVACTSelect + + OFF + Event action disabled + 0 + + + RETRIGGER + Start, restart or retrigger TC on event + 1 + + + COUNT + Count on event + 2 + + + START + Start TC on event + 3 + + + STAMP + Time stamp capture + 4 + + + PPW + Period catured in CC0, pulse width in CC1 + 5 + + + PWP + Period catured in CC1, pulse width in CC0 + 6 + + + PW + Pulse width capture + 7 + + + + + TCINV + TC Event Input Polarity + 4 + 1 + + + TCEI + TC Event Enable + 5 + 1 + + + OVFEO + Event Output Enable + 8 + 1 + + + MCEO0 + MC Event Output Enable 0 + 12 + 1 + + + MCEO1 + MC Event Output Enable 1 + 13 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x8 + 8 + 0x00 + + + OVF + OVF Interrupt Disable + 0 + 1 + + + ERR + ERR Interrupt Disable + 1 + 1 + + + MC0 + MC Interrupt Disable 0 + 4 + 1 + + + MC1 + MC Interrupt Disable 1 + 5 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x9 + 8 + 0x00 + + + OVF + OVF Interrupt Enable + 0 + 1 + + + ERR + ERR Interrupt Enable + 1 + 1 + + + MC0 + MC Interrupt Enable 0 + 4 + 1 + + + MC1 + MC Interrupt Enable 1 + 5 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0xA + 8 + 0x00 + + + OVF + OVF Interrupt Flag + 0 + 1 + + + ERR + ERR Interrupt Flag + 1 + 1 + + + MC0 + MC Interrupt Flag 0 + 4 + 1 + + + MC1 + MC Interrupt Flag 1 + 5 + 1 + + + + + STATUS + Status + 0xB + 8 + 0x01 + + + STOP + Stop Status Flag + 0 + 1 + + + SLAVE + Slave Status Flag + 1 + 1 + + + PERBUFV + Synchronization Busy Status + 3 + 1 + + + CCBUFV0 + Compare channel buffer 0 valid + 4 + 1 + + + CCBUFV1 + Compare channel buffer 1 valid + 5 + 1 + + + + + WAVE + Waveform Generation Control + 0xC + 8 + 0x00 + + + WAVEGEN + Waveform Generation Mode + 0 + 2 + + WAVEGENSelect + + NFRQ + Normal frequency + 0 + + + MFRQ + Match frequency + 1 + + + NPWM + Normal PWM + 2 + + + MPWM + Match PWM + 3 + + + + + + + DRVCTRL + Control C + 0xD + 8 + 0x00 + + + INVEN0 + Output Waveform Invert Enable 0 + 0 + 1 + + + INVEN1 + Output Waveform Invert Enable 1 + 1 + 1 + + + + + DBGCTRL + Debug Control + 0xF + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + SYNCBUSY + Synchronization Status + 0x10 + 32 + read-only + 0x00000000 + + + SWRST + swrst + 0 + 1 + + + ENABLE + enable + 1 + 1 + + + CTRLB + CTRLB + 2 + 1 + + + STATUS + STATUS + 3 + 1 + + + COUNT + Counter + 4 + 1 + + + PER + Period + 5 + 1 + + + CC0 + Compare Channel 0 + 6 + 1 + + + CC1 + Compare Channel 1 + 7 + 1 + + + + + COUNT + COUNT32 Count + 0x14 + 32 + 0x00000000 + + + COUNT + Counter Value + 0 + 32 + + + + + 2 + 4 + CC[%s] + COUNT32 Compare and Capture + 0x1C + 32 + 0x00000000 + + + CC + Counter/Compare Value + 0 + 32 + + + + + 2 + 4 + CCBUF[%s] + COUNT32 Compare and Capture Buffer + 0x30 + 32 + 0x00000000 + + + CCBUF + Counter/Compare Buffer Value + 0 + 32 + + + + + + + + TC1 + 0x42003400 + + TC1 + 21 + + + + TC2 + 0x42003800 + + TC2 + 22 + + + + TC3 + 0x42003C00 + + TC3 + 23 + + + + TC4 + 0x42004000 + + TC4 + 24 + + + + TCC0 + U22133.0.0 + Timer Counter Control + TCC + TCC_ + 0x42002400 + + 0 + 0x80 + registers + + + TCC0 + 17 + + + + CTRLA + Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + RESOLUTION + Enhanced Resolution + 5 + 2 + + RESOLUTIONSelect + + NONE + Dithering is disabled + 0 + + + DITH4 + Dithering is done every 16 PWM frames + 1 + + + DITH5 + Dithering is done every 32 PWM frames + 2 + + + DITH6 + Dithering is done every 64 PWM frames + 3 + + + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + No division + 0 + + + DIV2 + Divide by 2 + 1 + + + DIV4 + Divide by 4 + 2 + + + DIV8 + Divide by 8 + 3 + + + DIV16 + Divide by 16 + 4 + + + DIV64 + Divide by 64 + 5 + + + DIV256 + Divide by 256 + 6 + + + DIV1024 + Divide by 1024 + 7 + + + + + RUNSTDBY + Run in Standby + 11 + 1 + + + PRESCSYNC + Prescaler and Counter Synchronization Selection + 12 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset counter on next GCLK + 0 + + + PRESC + Reload or reset counter on next prescaler clock + 1 + + + RESYNC + Reload or reset counter on next GCLK and reset prescaler counter + 2 + + + + + ALOCK + Auto Lock + 14 + 1 + + + MSYNC + Master Synchronization (only for TCC Slave Instance) + 15 + 1 + + + DMAOS + DMA One-shot Trigger Mode + 23 + 1 + + + CPTEN0 + Capture Channel 0 Enable + 24 + 1 + + + CPTEN1 + Capture Channel 1 Enable + 25 + 1 + + + CPTEN2 + Capture Channel 2 Enable + 26 + 1 + + + CPTEN3 + Capture Channel 3 Enable + 27 + 1 + + + + + CTRLBCLR + Control B Clear + 0x4 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + IDXCMD + Ramp Index Command + 3 + 2 + + IDXCMDSelect + + DISABLE + Command disabled: Index toggles between cycles A and B + 0 + + + SET + Set index: cycle B will be forced in the next cycle + 1 + + + CLEAR + Clear index: cycle A will be forced in the next cycle + 2 + + + HOLD + Hold index: the next cycle will be the same as the current cycle + 3 + + + + + CMD + TCC Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Clear start, restart or retrigger + 1 + + + STOP + Force stop + 2 + + + UPDATE + Force update or double buffered registers + 3 + + + READSYNC + Force COUNT read synchronization + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + CTRLBSET + Control B Set + 0x5 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + IDXCMD + Ramp Index Command + 3 + 2 + + IDXCMDSelect + + DISABLE + Command disabled: Index toggles between cycles A and B + 0 + + + SET + Set index: cycle B will be forced in the next cycle + 1 + + + CLEAR + Clear index: cycle A will be forced in the next cycle + 2 + + + HOLD + Hold index: the next cycle will be the same as the current cycle + 3 + + + + + CMD + TCC Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Clear start, restart or retrigger + 1 + + + STOP + Force stop + 2 + + + UPDATE + Force update or double buffered registers + 3 + + + READSYNC + Force COUNT read synchronization + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + SYNCBUSY + Synchronization Busy + 0x8 + 32 + read-only + 0x00000000 + + + SWRST + Swrst Busy + 0 + 1 + + + ENABLE + Enable Busy + 1 + 1 + + + CTRLB + Ctrlb Busy + 2 + 1 + + + STATUS + Status Busy + 3 + 1 + + + COUNT + Count Busy + 4 + 1 + + + PATT + Pattern Busy + 5 + 1 + + + WAVE + Wave Busy + 6 + 1 + + + PER + Period Busy + 7 + 1 + + + CC0 + Compare Channel 0 Busy + 8 + 1 + + + CC1 + Compare Channel 1 Busy + 9 + 1 + + + CC2 + Compare Channel 2 Busy + 10 + 1 + + + CC3 + Compare Channel 3 Busy + 11 + 1 + + + + + FCTRLA + Recoverable Fault A Configuration + 0xC + 32 + 0x00000000 + + + SRC + Fault A Source + 0 + 2 + + SRCSelect + + DISABLE + Fault input disabled + 0 + + + ENABLE + MCEx (x=0,1) event input + 1 + + + INVERT + Inverted MCEx (x=0,1) event input + 2 + + + ALTFAULT + Alternate fault (A or B) state at the end of the previous period + 3 + + + + + KEEP + Fault A Keeper + 3 + 1 + + + QUAL + Fault A Qualification + 4 + 1 + + + BLANK + Fault A Blanking Mode + 5 + 2 + + BLANKSelect + + START + Blanking applied from start of the ramp + 0 + + + RISE + Blanking applied from rising edge of the output waveform + 1 + + + FALL + Blanking applied from falling edge of the output waveform + 2 + + + BOTH + Blanking applied from each toggle of the output waveform + 3 + + + + + RESTART + Fault A Restart + 7 + 1 + + + HALT + Fault A Halt Mode + 8 + 2 + + HALTSelect + + DISABLE + Halt action disabled + 0 + + + HW + Hardware halt action + 1 + + + SW + Software halt action + 2 + + + NR + Non-recoverable fault + 3 + + + + + CHSEL + Fault A Capture Channel + 10 + 2 + + CHSELSelect + + CC0 + Capture value stored in channel 0 + 0 + + + CC1 + Capture value stored in channel 1 + 1 + + + CC2 + Capture value stored in channel 2 + 2 + + + CC3 + Capture value stored in channel 3 + 3 + + + + + CAPTURE + Fault A Capture Action + 12 + 3 + + CAPTURESelect + + DISABLE + No capture + 0 + + + CAPT + Capture on fault + 1 + + + CAPTMIN + Minimum capture + 2 + + + CAPTMAX + Maximum capture + 3 + + + LOCMIN + Minimum local detection + 4 + + + LOCMAX + Maximum local detection + 5 + + + DERIV0 + Minimum and maximum local detection + 6 + + + CAPTMARK + Capture with ramp index as MSB value + 7 + + + + + BLANKPRESC + Fault A Blanking Prescaler + 15 + 1 + + + BLANKVAL + Fault A Blanking Time + 16 + 8 + + + FILTERVAL + Fault A Filter Value + 24 + 4 + + + + + FCTRLB + Recoverable Fault B Configuration + 0x10 + 32 + 0x00000000 + + + SRC + Fault B Source + 0 + 2 + + SRCSelect + + DISABLE + Fault input disabled + 0 + + + ENABLE + MCEx (x=0,1) event input + 1 + + + INVERT + Inverted MCEx (x=0,1) event input + 2 + + + ALTFAULT + Alternate fault (A or B) state at the end of the previous period + 3 + + + + + KEEP + Fault B Keeper + 3 + 1 + + + QUAL + Fault B Qualification + 4 + 1 + + + BLANK + Fault B Blanking Mode + 5 + 2 + + BLANKSelect + + START + Blanking applied from start of the ramp + 0 + + + RISE + Blanking applied from rising edge of the output waveform + 1 + + + FALL + Blanking applied from falling edge of the output waveform + 2 + + + BOTH + Blanking applied from each toggle of the output waveform + 3 + + + + + RESTART + Fault B Restart + 7 + 1 + + + HALT + Fault B Halt Mode + 8 + 2 + + HALTSelect + + DISABLE + Halt action disabled + 0 + + + HW + Hardware halt action + 1 + + + SW + Software halt action + 2 + + + NR + Non-recoverable fault + 3 + + + + + CHSEL + Fault B Capture Channel + 10 + 2 + + CHSELSelect + + CC0 + Capture value stored in channel 0 + 0 + + + CC1 + Capture value stored in channel 1 + 1 + + + CC2 + Capture value stored in channel 2 + 2 + + + CC3 + Capture value stored in channel 3 + 3 + + + + + CAPTURE + Fault B Capture Action + 12 + 3 + + CAPTURESelect + + DISABLE + No capture + 0 + + + CAPT + Capture on fault + 1 + + + CAPTMIN + Minimum capture + 2 + + + CAPTMAX + Maximum capture + 3 + + + LOCMIN + Minimum local detection + 4 + + + LOCMAX + Maximum local detection + 5 + + + DERIV0 + Minimum and maximum local detection + 6 + + + CAPTMARK + Capture with ramp index as MSB value + 7 + + + + + BLANKPRESC + Fault B Blanking Prescaler + 15 + 1 + + + BLANKVAL + Fault B Blanking Time + 16 + 8 + + + FILTERVAL + Fault B Filter Value + 24 + 4 + + + + + WEXCTRL + Waveform Extension Configuration + 0x14 + 32 + 0x00000000 + + + OTMX + Output Matrix + 0 + 2 + + + DTIEN0 + Dead-time Insertion Generator 0 Enable + 8 + 1 + + + DTIEN1 + Dead-time Insertion Generator 1 Enable + 9 + 1 + + + DTIEN2 + Dead-time Insertion Generator 2 Enable + 10 + 1 + + + DTIEN3 + Dead-time Insertion Generator 3 Enable + 11 + 1 + + + DTLS + Dead-time Low Side Outputs Value + 16 + 8 + + + DTHS + Dead-time High Side Outputs Value + 24 + 8 + + + + + DRVCTRL + Driver Control + 0x18 + 32 + 0x00000000 + + + NRE0 + Non-Recoverable State 0 Output Enable + 0 + 1 + + + NRE1 + Non-Recoverable State 1 Output Enable + 1 + 1 + + + NRE2 + Non-Recoverable State 2 Output Enable + 2 + 1 + + + NRE3 + Non-Recoverable State 3 Output Enable + 3 + 1 + + + NRE4 + Non-Recoverable State 4 Output Enable + 4 + 1 + + + NRE5 + Non-Recoverable State 5 Output Enable + 5 + 1 + + + NRE6 + Non-Recoverable State 6 Output Enable + 6 + 1 + + + NRE7 + Non-Recoverable State 7 Output Enable + 7 + 1 + + + NRV0 + Non-Recoverable State 0 Output Value + 8 + 1 + + + NRV1 + Non-Recoverable State 1 Output Value + 9 + 1 + + + NRV2 + Non-Recoverable State 2 Output Value + 10 + 1 + + + NRV3 + Non-Recoverable State 3 Output Value + 11 + 1 + + + NRV4 + Non-Recoverable State 4 Output Value + 12 + 1 + + + NRV5 + Non-Recoverable State 5 Output Value + 13 + 1 + + + NRV6 + Non-Recoverable State 6 Output Value + 14 + 1 + + + NRV7 + Non-Recoverable State 7 Output Value + 15 + 1 + + + INVEN0 + Output Waveform 0 Inversion + 16 + 1 + + + INVEN1 + Output Waveform 1 Inversion + 17 + 1 + + + INVEN2 + Output Waveform 2 Inversion + 18 + 1 + + + INVEN3 + Output Waveform 3 Inversion + 19 + 1 + + + INVEN4 + Output Waveform 4 Inversion + 20 + 1 + + + INVEN5 + Output Waveform 5 Inversion + 21 + 1 + + + INVEN6 + Output Waveform 6 Inversion + 22 + 1 + + + INVEN7 + Output Waveform 7 Inversion + 23 + 1 + + + FILTERVAL0 + Non-Recoverable Fault Input 0 Filter Value + 24 + 4 + + + FILTERVAL1 + Non-Recoverable Fault Input 1 Filter Value + 28 + 4 + + + + + DBGCTRL + Debug Control + 0x1E + 8 + 0x00 + + + DBGRUN + Debug Running Mode + 0 + 1 + + + FDDBD + Fault Detection on Debug Break Detection + 2 + 1 + + + + + EVCTRL + Event Control + 0x20 + 32 + 0x00000000 + + + EVACT0 + Timer/counter Input Event0 Action + 0 + 3 + + EVACT0Select + + OFF + Event action disabled + 0 + + + RETRIGGER + Start, restart or re-trigger counter on event + 1 + + + COUNTEV + Count on event + 2 + + + START + Start counter on event + 3 + + + INC + Increment counter on event + 4 + + + COUNT + Count on active state of asynchronous event + 5 + + + STAMP + Stamp capture + 6 + + + FAULT + Non-recoverable fault + 7 + + + + + EVACT1 + Timer/counter Input Event1 Action + 3 + 3 + + EVACT1Select + + OFF + Event action disabled + 0 + + + RETRIGGER + Re-trigger counter on event + 1 + + + DIR + Direction control + 2 + + + STOP + Stop counter on event + 3 + + + DEC + Decrement counter on event + 4 + + + PPW + Period capture value in CC0 register, pulse width capture value in CC1 register + 5 + + + PWP + Period capture value in CC1 register, pulse width capture value in CC0 register + 6 + + + FAULT + Non-recoverable fault + 7 + + + + + CNTSEL + Timer/counter Output Event Mode + 6 + 2 + + CNTSELSelect + + START + An interrupt/event is generated when a new counter cycle starts + 0 + + + END + An interrupt/event is generated when a counter cycle ends + 1 + + + BETWEEN + An interrupt/event is generated when a counter cycle ends, except for the first and last cycles + 2 + + + BOUNDARY + An interrupt/event is generated when a new counter cycle starts or a counter cycle ends + 3 + + + + + OVFEO + Overflow/Underflow Output Event Enable + 8 + 1 + + + TRGEO + Retrigger Output Event Enable + 9 + 1 + + + CNTEO + Timer/counter Output Event Enable + 10 + 1 + + + TCINV0 + Inverted Event 0 Input Enable + 12 + 1 + + + TCINV1 + Inverted Event 1 Input Enable + 13 + 1 + + + TCEI0 + Timer/counter Event 0 Input Enable + 14 + 1 + + + TCEI1 + Timer/counter Event 1 Input Enable + 15 + 1 + + + MCEI0 + Match or Capture Channel 0 Event Input Enable + 16 + 1 + + + MCEI1 + Match or Capture Channel 1 Event Input Enable + 17 + 1 + + + MCEI2 + Match or Capture Channel 2 Event Input Enable + 18 + 1 + + + MCEI3 + Match or Capture Channel 3 Event Input Enable + 19 + 1 + + + MCEO0 + Match or Capture Channel 0 Event Output Enable + 24 + 1 + + + MCEO1 + Match or Capture Channel 1 Event Output Enable + 25 + 1 + + + MCEO2 + Match or Capture Channel 2 Event Output Enable + 26 + 1 + + + MCEO3 + Match or Capture Channel 3 Event Output Enable + 27 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x24 + 32 + 0x00000000 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + TRG + Retrigger Interrupt Enable + 1 + 1 + + + CNT + Counter Interrupt Enable + 2 + 1 + + + ERR + Error Interrupt Enable + 3 + 1 + + + UFS + Non-Recoverable Update Fault Interrupt Enable + 10 + 1 + + + DFS + Non-Recoverable Debug Fault Interrupt Enable + 11 + 1 + + + FAULTA + Recoverable Fault A Interrupt Enable + 12 + 1 + + + FAULTB + Recoverable Fault B Interrupt Enable + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 Interrupt Enable + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 Interrupt Enable + 15 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 16 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 17 + 1 + + + MC2 + Match or Capture Channel 2 Interrupt Enable + 18 + 1 + + + MC3 + Match or Capture Channel 3 Interrupt Enable + 19 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x28 + 32 + 0x00000000 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + TRG + Retrigger Interrupt Enable + 1 + 1 + + + CNT + Counter Interrupt Enable + 2 + 1 + + + ERR + Error Interrupt Enable + 3 + 1 + + + UFS + Non-Recoverable Update Fault Interrupt Enable + 10 + 1 + + + DFS + Non-Recoverable Debug Fault Interrupt Enable + 11 + 1 + + + FAULTA + Recoverable Fault A Interrupt Enable + 12 + 1 + + + FAULTB + Recoverable Fault B Interrupt Enable + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 Interrupt Enable + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 Interrupt Enable + 15 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 16 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 17 + 1 + + + MC2 + Match or Capture Channel 2 Interrupt Enable + 18 + 1 + + + MC3 + Match or Capture Channel 3 Interrupt Enable + 19 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x2C + 32 + 0x00000000 + + + OVF + Overflow + 0 + 1 + + + TRG + Retrigger + 1 + 1 + + + CNT + Counter + 2 + 1 + + + ERR + Error + 3 + 1 + + + UFS + Non-Recoverable Update Fault + 10 + 1 + + + DFS + Non-Recoverable Debug Fault + 11 + 1 + + + FAULTA + Recoverable Fault A + 12 + 1 + + + FAULTB + Recoverable Fault B + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 + 15 + 1 + + + MC0 + Match or Capture 0 + 16 + 1 + + + MC1 + Match or Capture 1 + 17 + 1 + + + MC2 + Match or Capture 2 + 18 + 1 + + + MC3 + Match or Capture 3 + 19 + 1 + + + + + STATUS + Status + 0x30 + 32 + 0x00000001 + + + STOP + Stop + 0 + 1 + + + IDX + Ramp + 1 + 1 + + + UFS + Non-recoverable Update Fault State + 2 + 1 + + + DFS + Non-Recoverable Debug Fault State + 3 + 1 + + + SLAVE + Slave + 4 + 1 + + + PATTBUFV + Pattern Buffer Valid + 5 + 1 + + + PERBUFV + Period Buffer Valid + 7 + 1 + + + FAULTAIN + Recoverable Fault A Input + 8 + 1 + + + FAULTBIN + Recoverable Fault B Input + 9 + 1 + + + FAULT0IN + Non-Recoverable Fault0 Input + 10 + 1 + + + FAULT1IN + Non-Recoverable Fault1 Input + 11 + 1 + + + FAULTA + Recoverable Fault A State + 12 + 1 + + + FAULTB + Recoverable Fault B State + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 State + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 State + 15 + 1 + + + CCBUFV0 + Compare Channel 0 Buffer Valid + 16 + 1 + + + CCBUFV1 + Compare Channel 1 Buffer Valid + 17 + 1 + + + CCBUFV2 + Compare Channel 2 Buffer Valid + 18 + 1 + + + CCBUFV3 + Compare Channel 3 Buffer Valid + 19 + 1 + + + CMP0 + Compare Channel 0 Value + 24 + 1 + + + CMP1 + Compare Channel 1 Value + 25 + 1 + + + CMP2 + Compare Channel 2 Value + 26 + 1 + + + CMP3 + Compare Channel 3 Value + 27 + 1 + + + + + COUNT + Count + 0x34 + 32 + 0x00000000 + + + COUNT + Counter Value + 0 + 24 + + + + + COUNT_DITH4_MODE + Count + COUNT + 0x34 + 32 + 0x00000000 + + + COUNT + Counter Value + 4 + 20 + + + + + COUNT_DITH5_MODE + Count + COUNT + 0x34 + 32 + 0x00000000 + + + COUNT + Counter Value + 5 + 19 + + + + + COUNT_DITH6_MODE + Count + COUNT + 0x34 + 32 + 0x00000000 + + + COUNT + Counter Value + 6 + 18 + + + + + PATT + Pattern + 0x38 + 16 + 0x0000 + + + PGE0 + Pattern Generator 0 Output Enable + 0 + 1 + + + PGE1 + Pattern Generator 1 Output Enable + 1 + 1 + + + PGE2 + Pattern Generator 2 Output Enable + 2 + 1 + + + PGE3 + Pattern Generator 3 Output Enable + 3 + 1 + + + PGE4 + Pattern Generator 4 Output Enable + 4 + 1 + + + PGE5 + Pattern Generator 5 Output Enable + 5 + 1 + + + PGE6 + Pattern Generator 6 Output Enable + 6 + 1 + + + PGE7 + Pattern Generator 7 Output Enable + 7 + 1 + + + PGV0 + Pattern Generator 0 Output Value + 8 + 1 + + + PGV1 + Pattern Generator 1 Output Value + 9 + 1 + + + PGV2 + Pattern Generator 2 Output Value + 10 + 1 + + + PGV3 + Pattern Generator 3 Output Value + 11 + 1 + + + PGV4 + Pattern Generator 4 Output Value + 12 + 1 + + + PGV5 + Pattern Generator 5 Output Value + 13 + 1 + + + PGV6 + Pattern Generator 6 Output Value + 14 + 1 + + + PGV7 + Pattern Generator 7 Output Value + 15 + 1 + + + + + WAVE + Waveform Control + 0x3C + 32 + 0x00000000 + + + WAVEGEN + Waveform Generation + 0 + 3 + + WAVEGENSelect + + NFRQ + Normal frequency + 0 + + + MFRQ + Match frequency + 1 + + + NPWM + Normal PWM + 2 + + + DSCRITICAL + Dual-slope critical + 4 + + + DSBOTTOM + Dual-slope with interrupt/event condition when COUNT reaches ZERO + 5 + + + DSBOTH + Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP + 6 + + + DSTOP + Dual-slope with interrupt/event condition when COUNT reaches TOP + 7 + + + + + RAMP + Ramp Mode + 4 + 2 + + RAMPSelect + + RAMP1 + RAMP1 operation + 0 + + + RAMP2A + Alternative RAMP2 operation + 1 + + + RAMP2 + RAMP2 operation + 2 + + + RAMP2C + Critical RAMP2 operation + 3 + + + + + CIPEREN + Circular period Enable + 7 + 1 + + + CICCEN0 + Circular Channel 0 Enable + 8 + 1 + + + CICCEN1 + Circular Channel 1 Enable + 9 + 1 + + + CICCEN2 + Circular Channel 2 Enable + 10 + 1 + + + CICCEN3 + Circular Channel 3 Enable + 11 + 1 + + + POL0 + Channel 0 Polarity + 16 + 1 + + + POL1 + Channel 1 Polarity + 17 + 1 + + + POL2 + Channel 2 Polarity + 18 + 1 + + + POL3 + Channel 3 Polarity + 19 + 1 + + + SWAP0 + Swap DTI Output Pair 0 + 24 + 1 + + + SWAP1 + Swap DTI Output Pair 1 + 25 + 1 + + + SWAP2 + Swap DTI Output Pair 2 + 26 + 1 + + + SWAP3 + Swap DTI Output Pair 3 + 27 + 1 + + + + + PER + Period + 0x40 + 32 + 0xFFFFFFFF + + + PER + Period Value + 0 + 24 + + + + + PER_DITH4_MODE + Period + PER + 0x40 + 32 + 0xFFFFFFFF + + + DITHER + Dithering Cycle Number + 0 + 4 + + + PER + Period Value + 4 + 20 + + + + + PER_DITH5_MODE + Period + PER + 0x40 + 32 + 0xFFFFFFFF + + + DITHER + Dithering Cycle Number + 0 + 5 + + + PER + Period Value + 5 + 19 + + + + + PER_DITH6_MODE + Period + PER + 0x40 + 32 + 0xFFFFFFFF + + + DITHER + Dithering Cycle Number + 0 + 6 + + + PER + Period Value + 6 + 18 + + + + + 4 + 4 + CC[%s] + Compare and Capture + 0x44 + 32 + 0x00000000 + + + CC + Channel Compare/Capture Value + 0 + 24 + + + + + 4 + 4 + CC_DITH4_MODE[%s] + Compare and Capture + CC[%s] + 0x44 + 32 + 0x00000000 + + + DITHER + Dithering Cycle Number + 0 + 4 + + + CC + Channel Compare/Capture Value + 4 + 20 + + + + + 4 + 4 + CC_DITH5_MODE[%s] + Compare and Capture + CC[%s] + 0x44 + 32 + 0x00000000 + + + DITHER + Dithering Cycle Number + 0 + 5 + + + CC + Channel Compare/Capture Value + 5 + 19 + + + + + 4 + 4 + CC_DITH6_MODE[%s] + Compare and Capture + CC[%s] + 0x44 + 32 + 0x00000000 + + + DITHER + Dithering Cycle Number + 0 + 6 + + + CC + Channel Compare/Capture Value + 6 + 18 + + + + + PATTBUF + Pattern Buffer + 0x64 + 16 + 0x0000 + + + PGEB0 + Pattern Generator 0 Output Enable Buffer + 0 + 1 + + + PGEB1 + Pattern Generator 1 Output Enable Buffer + 1 + 1 + + + PGEB2 + Pattern Generator 2 Output Enable Buffer + 2 + 1 + + + PGEB3 + Pattern Generator 3 Output Enable Buffer + 3 + 1 + + + PGEB4 + Pattern Generator 4 Output Enable Buffer + 4 + 1 + + + PGEB5 + Pattern Generator 5 Output Enable Buffer + 5 + 1 + + + PGEB6 + Pattern Generator 6 Output Enable Buffer + 6 + 1 + + + PGEB7 + Pattern Generator 7 Output Enable Buffer + 7 + 1 + + + PGVB0 + Pattern Generator 0 Output Enable + 8 + 1 + + + PGVB1 + Pattern Generator 1 Output Enable + 9 + 1 + + + PGVB2 + Pattern Generator 2 Output Enable + 10 + 1 + + + PGVB3 + Pattern Generator 3 Output Enable + 11 + 1 + + + PGVB4 + Pattern Generator 4 Output Enable + 12 + 1 + + + PGVB5 + Pattern Generator 5 Output Enable + 13 + 1 + + + PGVB6 + Pattern Generator 6 Output Enable + 14 + 1 + + + PGVB7 + Pattern Generator 7 Output Enable + 15 + 1 + + + + + PERBUF + Period Buffer + 0x6C + 32 + 0xFFFFFFFF + + + PERBUF + Period Buffer Value + 0 + 24 + + + + + PERBUF_DITH4_MODE + Period Buffer + PERBUF + 0x6C + 32 + 0xFFFFFFFF + + + DITHERBUF + Dithering Buffer Cycle Number + 0 + 4 + + + PERBUF + Period Buffer Value + 4 + 20 + + + + + PERBUF_DITH5_MODE + Period Buffer + PERBUF + 0x6C + 32 + 0xFFFFFFFF + + + DITHERBUF + Dithering Buffer Cycle Number + 0 + 5 + + + PERBUF + Period Buffer Value + 5 + 19 + + + + + PERBUF_DITH6_MODE + Period Buffer + PERBUF + 0x6C + 32 + 0xFFFFFFFF + + + DITHERBUF + Dithering Buffer Cycle Number + 0 + 6 + + + PERBUF + Period Buffer Value + 6 + 18 + + + + + 4 + 4 + CCBUF[%s] + Compare and Capture Buffer + 0x70 + 32 + 0x00000000 + + + CCBUF + Channel Compare/Capture Buffer Value + 0 + 24 + + + + + 4 + 4 + CCBUF_DITH4_MODE[%s] + Compare and Capture Buffer + CCBUF[%s] + 0x70 + 32 + 0x00000000 + + + CCBUF + Channel Compare/Capture Buffer Value + 0 + 4 + + + DITHERBUF + Dithering Buffer Cycle Number + 4 + 20 + + + + + 4 + 4 + CCBUF_DITH5_MODE[%s] + Compare and Capture Buffer + CCBUF[%s] + 0x70 + 32 + 0x00000000 + + + DITHERBUF + Dithering Buffer Cycle Number + 0 + 5 + + + CCBUF + Channel Compare/Capture Buffer Value + 5 + 19 + + + + + 4 + 4 + CCBUF_DITH6_MODE[%s] + Compare and Capture Buffer + CCBUF[%s] + 0x70 + 32 + 0x00000000 + + + DITHERBUF + Dithering Buffer Cycle Number + 0 + 6 + + + CCBUF + Channel Compare/Capture Buffer Value + 6 + 18 + + + + + + + TCC1 + 0x42002800 + + TCC1 + 18 + + + + TCC2 + 0x42002C00 + + TCC2 + 19 + + + + TSENS + U22611.0.1 + Temperature Sensor + TSENS + TSENS_ + 0x40003000 + + 0 + 0x25 + registers + + + TSENS + 5 + + + + CTRLA + Control A Register + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + + + CTRLB + Control B Register + 0x1 + 8 + write-only + 0x00 + + + START + Start Measurement + 0 + 1 + + + + + CTRLC + Control C Register + 0x2 + 8 + 0x00 + + + WINMODE + Window Monitor Mode + 0 + 3 + + WINMODESelect + + DISABLE + No window mode (default) + 0 + + + ABOVE + VALUE greater than WINLT + 1 + + + BELOW + VALUE less than WINUT + 2 + + + INSIDE + VALUE greater than WINLT and VALUE less than WINUT + 3 + + + OUTSIDE + VALUE less than WINLT or VALUE greater than WINUT + 4 + + + HYST_ABOVE + VALUE greater than WINUT with hysteresis to WINLT + 5 + + + HYST_BELOW + VALUE less than WINLST with hysteresis to WINUT + 6 + + + + + FREERUN + Free Running Measurement + 4 + 1 + + + + + EVCTRL + Event Control Register + 0x3 + 8 + 0x00 + + + STARTEI + Start Conversion Event Input Enable + 0 + 1 + + + STARTINV + Start Conversion Event Invert Enable + 1 + 1 + + + WINEO + Window Monitor Event Out + 2 + 1 + + + + + INTENCLR + Interrupt Enable Clear Register + 0x4 + 8 + 0x00 + + + RESRDY + Result Ready Interrupt Enable + 0 + 1 + + + OVERRUN + Overrun Interrupt Enable + 1 + 1 + + + WINMON + Window Monitor Interrupt Enable + 2 + 1 + + + OVF + Overflow Interrupt Enable + 3 + 1 + + + + + INTENSET + Interrupt Enable Set Register + 0x5 + 8 + 0x00 + + + RESRDY + Result Ready Interrupt Enable + 0 + 1 + + + OVERRUN + Overrun Interrupt Enable + 1 + 1 + + + WINMON + Window Monitor Interrupt Enable + 2 + 1 + + + OVF + Overflow Interrupt Enable + 3 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear Register + 0x6 + 8 + 0x00 + + + RESRDY + Result Ready + 0 + 1 + + + OVERRUN + Overrun + 1 + 1 + + + WINMON + Window Monitor + 2 + 1 + + + OVF + Overflow + 3 + 1 + + + + + STATUS + Status Register + 0x7 + 8 + read-only + 0x00 + + + OVF + Result Overflow + 0 + 1 + + + + + SYNCBUSY + Synchronization Busy Register + 0x8 + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Busy + 0 + 1 + + + ENABLE + Enable Busy + 1 + 1 + + + + + VALUE + Value Register + 0xC + 32 + read-only + 0x00000000 + + + VALUE + Measurement Value + 0 + 24 + + + + + WINLT + Window Monitor Lower Threshold Register + 0x10 + 32 + 0x00000000 + + + WINLT + Window Lower Threshold + 0 + 24 + + + + + WINUT + Window Monitor Upper Threshold Register + 0x14 + 32 + 0x00000000 + + + WINUT + Window Upper Threshold + 0 + 24 + + + + + GAIN + Gain Register + 0x18 + 32 + 0x00000000 + + + GAIN + Time Amplifier Gain + 0 + 24 + + + + + OFFSET + Offset Register + 0x1C + 32 + 0x00000000 + + + OFFSETC + Offset Correction + 0 + 24 + + + + + CAL + Calibration Register + 0x20 + 32 + 0x00000000 + + + FCAL + Frequency Calibration + 0 + 6 + + + TCAL + Temperature Calibration + 8 + 6 + + + + + DBGCTRL + Debug Control Register + 0x24 + 8 + 0x00 + + + DBGRUN + Debug Run + 0 + 1 + + + + + + + WDT + U22511.0.1 + Watchdog Timer + WDT + WDT_ + 0x40002000 + + 0 + 0xD + registers + + + WDT + 1 + + + + CTRLA + Control + 0x0 + 8 + 0x00 + + + ENABLE + Enable + 1 + 1 + + + WEN + Watchdog Timer Window Mode Enable + 2 + 1 + + + ALWAYSON + Always-On + 7 + 1 + + + + + CONFIG + Configuration + 0x1 + 8 + 0xBB + + + PER + Time-Out Period + 0 + 4 + + PERSelect + + CYC8 + 8 clock cycles + 0x0 + + + CYC16 + 16 clock cycles + 0x1 + + + CYC32 + 32 clock cycles + 0x2 + + + CYC64 + 64 clock cycles + 0x3 + + + CYC128 + 128 clock cycles + 0x4 + + + CYC256 + 256 clock cycles + 0x5 + + + CYC512 + 512 clock cycles + 0x6 + + + CYC1024 + 1024 clock cycles + 0x7 + + + CYC2048 + 2048 clock cycles + 0x8 + + + CYC4096 + 4096 clock cycles + 0x9 + + + CYC8192 + 8192 clock cycles + 0xA + + + CYC16384 + 16384 clock cycles + 0xB + + + + + WINDOW + Window Mode Time-Out Period + 4 + 4 + + WINDOWSelect + + CYC8 + 8 clock cycles + 0x0 + + + CYC16 + 16 clock cycles + 0x1 + + + CYC32 + 32 clock cycles + 0x2 + + + CYC64 + 64 clock cycles + 0x3 + + + CYC128 + 128 clock cycles + 0x4 + + + CYC256 + 256 clock cycles + 0x5 + + + CYC512 + 512 clock cycles + 0x6 + + + CYC1024 + 1024 clock cycles + 0x7 + + + CYC2048 + 2048 clock cycles + 0x8 + + + CYC4096 + 4096 clock cycles + 0x9 + + + CYC8192 + 8192 clock cycles + 0xA + + + CYC16384 + 16384 clock cycles + 0xB + + + + + + + EWCTRL + Early Warning Interrupt Control + 0x2 + 8 + 0x0B + + + EWOFFSET + Early Warning Interrupt Time Offset + 0 + 4 + + EWOFFSETSelect + + CYC8 + 8 clock cycles + 0x0 + + + CYC16 + 16 clock cycles + 0x1 + + + CYC32 + 32 clock cycles + 0x2 + + + CYC64 + 64 clock cycles + 0x3 + + + CYC128 + 128 clock cycles + 0x4 + + + CYC256 + 256 clock cycles + 0x5 + + + CYC512 + 512 clock cycles + 0x6 + + + CYC1024 + 1024 clock cycles + 0x7 + + + CYC2048 + 2048 clock cycles + 0x8 + + + CYC4096 + 4096 clock cycles + 0x9 + + + CYC8192 + 8192 clock cycles + 0xA + + + CYC16384 + 16384 clock cycles + 0xB + + + + + + + INTENCLR + Interrupt Enable Clear + 0x4 + 8 + 0x00 + + + EW + Early Warning Interrupt Enable + 0 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x5 + 8 + 0x00 + + + EW + Early Warning Interrupt Enable + 0 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x6 + 8 + 0x00 + + + EW + Early Warning + 0 + 1 + + + + + SYNCBUSY + Synchronization Busy + 0x8 + 32 + read-only + 0x00000000 + + + ENABLE + Enable Busy + 1 + 1 + + + WEN + Window Enable Busy + 2 + 1 + + + ALWAYSON + Always-On Busy + 3 + 1 + + + CLEAR + Clear Busy + 4 + 1 + + + + + CLEAR + Clear + 0xC + 8 + write-only + 0x00 + + + CLEAR + Watchdog Clear + 0 + 8 + + CLEARSelect + + KEY + Clear Key + 0xA5 + + + + + + + + + MPU + Memory Protection Unit + MPU + MPU_ + 0xE000ED90 + + 0 + 0x14 + registers + + + + TYPE + MPU Type Register + 0x0 + 32 + read-only + + + SEPARATE + Separate instruction and Data Memory MapsRegions + 0 + 1 + + + DREGION + Number of Data Regions + 8 + 8 + + + IREGION + Number of Instruction Regions + 16 + 8 + + + + + CTRL + MPU Control Register + 0x4 + 32 + + + ENABLE + MPU Enable + 0 + 1 + + + HFNMIENA + Enable Hard Fault and NMI handlers + 1 + 1 + + + PRIVDEFENA + Enables privileged software access to default memory map + 2 + 1 + + + + + RNR + MPU Region Number Register + 0x8 + 32 + + + REGION + Region referenced by RBAR and RASR + 0 + 8 + + + + + RBAR + MPU Region Base Address Register + 0xC + 32 + + + REGION + Region number + 0 + 4 + + + VALID + Region number valid + 4 + 1 + + + ADDR + Region base address + 5 + 27 + + + + + RASR + MPU Region Attribute and Size Register + 0x10 + 32 + + + ENABLE + Region Enable + 0 + 1 + + + SIZE + Region Size + 1 + 5 + + + SRD + Sub-region disable + 8 + 8 + + + B + Bufferable bit + 16 + 1 + + + C + Cacheable bit + 17 + 1 + + + S + Shareable bit + 18 + 1 + + + TEX + TEX bit + 19 + 3 + + + AP + Access Permission + 24 + 3 + + + XN + Execute Never Attribute + 28 + 1 + + + + + + + NVIC + Nested Vectored Interrupt Controller + NVIC + NVIC_ + 0xE000E100 + + 0 + 0x320 + registers + + + + ISER + Interrupt Set Enable Register + 0x0 + 32 + 0x00000000 + + + SETENA + Interrupt set enable bits + 0 + 31 + + + + + ICER + Interrupt Clear Enable Register + 0x80 + 32 + 0x00000000 + + + CLRENA + Interrupt clear-enable bits + 0 + 31 + + + + + ISPR + Interrupt Set Pending Register + 0x100 + 32 + 0x00000000 + + + SETPEND + Interrupt set-pending bits + 0 + 31 + + + + + ICPR + Interrupt Clear Pending Register + 0x180 + 32 + 0x00000000 + + + CLRPEND + Interrupt clear-pending bits + 0 + 31 + + + + + 8 + 4 + IPR[%s] + Interrupt Priority Register n + 0x300 + 32 + 0x00000000 + + + PRI0 + Priority of interrupt n + 0 + 2 + + + PRI1 + Priority of interrupt n + 8 + 2 + + + PRI2 + Priority of interrupt n + 16 + 2 + + + PRI3 + Priority of interrupt n + 24 + 2 + + + + + + + SysTick + System timer + SysTick + SysTick_ + 0xE000E010 + + 0 + 0x10 + registers + + + + CSR + SysTick Control and Status Register + 0x0 + 32 + 0x4 + + + ENABLE + SysTick Counter Enable + 0 + 1 + + ENABLESelect + + VALUE_0 + Counter disabled + 0 + + + VALUE_1 + Counter enabled + 1 + + + + + TICKINT + SysTick Exception Request Enable + 1 + 1 + + TICKINTSelect + + VALUE_0 + Counting down to 0 does not assert the SysTick exception request + 0 + + + VALUE_1 + Counting down to 0 asserts the SysTick exception request + 1 + + + + + CLKSOURCE + Clock Source 0=external, 1=processor + 2 + 1 + + CLKSOURCESelect + + VALUE_0 + External clock + 0 + + + VALUE_1 + Processor clock + 1 + + + + + COUNTFLAG + Timer counted to 0 since last read of register + 16 + 1 + + + + + RVR + SysTick Reload Value Register + 0x4 + 32 + + + RELOAD + Value to load into the SysTick Current Value Register when the counter reaches 0 + 0 + 24 + + + + + CVR + SysTick Current Value Register + 0x8 + 32 + + + CURRENT + Current value at the time the register is accessed + 0 + 24 + + + + + CALIB + SysTick Calibration Value Register + 0xC + 32 + read-only + 0 + + + TENMS + Reload value to use for 10ms timing + 0 + 24 + + + SKEW + TENMS is rounded from non-integer ratio + 30 + 1 + + SKEWSelect + + VALUE_0 + 10ms calibration value is exact + 0 + + + VALUE_1 + 10ms calibration value is inexact, because of the clock frequency + 1 + + + + + NOREF + No Separate Reference Clock + 31 + 1 + + NOREFSelect + + VALUE_0 + The reference clock is provided + 0 + + + VALUE_1 + The reference clock is not provided + 1 + + + + + + + + + SystemControl + System Control Registers + SystemControl + SystemControl_ + 0xE000E000 + + 0 + 0xD34 + registers + + + + CPUID + CPUID Base Register + 0xD00 + 32 + read-only + 0x410CC601 + + + REVISION + Minor revision number + 0 + 4 + + + PARTNO + Processor Part Number, 0xC60=Cortex-M0+ + 4 + 12 + + + ARCHITECTURE + Processor Architecture, 0xC=ARMv6-M + 16 + 4 + + + VARIANT + Major revision number + 20 + 4 + + + IMPLEMENTER + Implementer code, ARM=0x41 + 24 + 8 + + + + + ICSR + Interrupt Control and State Register + 0xD04 + 32 + 0x00000000 + + + VECTACTIVE + Debug: Exception number of currently executing exception, or 0 if thread mode + 0 + 9 + + + VECTPENDING + Exception number of the highest priority pending enabled exception + 12 + 9 + + + ISRPENDING + Debug: NVIC interrupt pending + 22 + 1 + + + ISRPREEMPT + Debug: Pending exception serviced on exit from debug halt + 23 + 1 + + + PENDSTCLR + SysTick exception clear-pending bit + 25 + 1 + + PENDSTCLRSelect + + VALUE_0 + No effect + 0 + + + VALUE_1 + Removes the pending state from the SysTick exception + 1 + + + + + PENDSTSET + SysTick exception set-pending bit + 26 + 1 + + PENDSTSETSelect + + VALUE_0 + Write: no effect; read: SysTick exception is not pending + 0 + + + VALUE_1 + Write: changes SysTick exception state to pending; read: SysTick exception is pending + 1 + + + + + PENDSVCLR + PendSV clear-pending bit + 27 + 1 + + PENDSVCLRSelect + + VALUE_0 + No effect + 0 + + + VALUE_1 + Removes the pending state from the PendSV exception + 1 + + + + + PENDSVSET + PendSV set-pending bit + 28 + 1 + + PENDSVSETSelect + + VALUE_0 + Write: no effect; read: PendSV exception is not pending + 0 + + + VALUE_1 + Write: changes PendSV exception state to pending; read: PendSV exception is pending + 1 + + + + + NMIPENDSET + NMI set-pending bit + 31 + 1 + + NMIPENDSETSelect + + VALUE_0 + Write: no effect; read: NMI exception is not pending + 0 + + + VALUE_1 + Write: changes NMI exception state to pending; read: NMI exception is pending + 1 + + + + + + + VTOR + Vector Table Offset Register + 0xD08 + 32 + 0x00000000 + + + TBLOFF + Vector table base offset + 7 + 25 + + + + + AIRCR + Application Interrupt and Reset Control Register + 0xD0C + 32 + 0x00000000 + + + VECTCLRACTIVE + Debug: Clear state information + 1 + 1 + + + SYSRESETREQ + System Reset Request + 2 + 1 + + SYSRESETREQSelect + + VALUE_0 + No system reset request + 0 + + + VALUE_1 + Asserts a signal to the outer system that requests a reset + 1 + + + + + ENDIANNESS + Data Endianness, 0=little, 1=big + 15 + 1 + + ENDIANNESSSelect + + VALUE_0 + Little-endian + 0 + + + VALUE_1 + Big-endian + 1 + + + + + VECTKEY + Register key (0x05FA) + 16 + 16 + + + + + SCR + System Control Register + 0xD10 + 32 + 0x00000000 + + + SLEEPONEXIT + Sleep-On-Exit when exiting Handler mode + 1 + 1 + + SLEEPONEXITSelect + + VALUE_0 + O not sleep when returning to Thread mode + 0 + + + VALUE_1 + Enter sleep, or deep sleep, on return from an ISR + 1 + + + + + SLEEPDEEP + Uses Deep Sleep as low power mode + 2 + 1 + + SLEEPDEEPSelect + + VALUE_0 + Sleep + 0 + + + VALUE_1 + Deep sleep + 1 + + + + + SEVONPEND + Send Event on Pending bit + 4 + 1 + + SEVONPENDSelect + + VALUE_0 + Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded + 0 + + + VALUE_1 + Enabled events and all interrupts, including disabled interrupts, can wakeup the processor + 1 + + + + + + + CCR + Configuration and Control Register + 0xD14 + 32 + read-only + 0x00000204 + + + UNALIGN_TRP + Unaligned accesses generates a Hard Fault + 3 + 1 + + UNALIGN_TRPSelect + + VALUE_0 + Do not trap unaligned halfword and word accesses + 0 + + + VALUE_1 + Trap unaligned halfword and word accesses + 1 + + + + + STKALIGN + Stack 8-byte aligned on exception entry + 9 + 1 + + STKALIGNSelect + + VALUE_0 + 4-byte aligned + 0 + + + VALUE_1 + 8-byte aligned + 1 + + + + + + + SHPR2 + System Handler Priority Register 2 + 0xD1C + 32 + 0x00000000 + + + PRI_11 + Priority of system handler 11, SVCall + 24 + 8 + + + + + SHPR3 + System Handler Priority Register 3 + 0xD20 + 32 + 0x00000000 + + + PRI_14 + Priority of system handler 14, PendSV + 16 + 8 + + + PRI_15 + Priority of system handler 15, SysTick exception + 24 + 8 + + + + + SHCSR + System Handler Control and State Register + 0xD24 + 32 + 0x00000000 + + + SVCALLPENDED + 15 + 1 + + + + + DFSR + Debug Fault Status Register + 0xD30 + 32 + 0x00000000 + + + HALTED + Halt request debug event active + 0 + 1 + + + BKPT + Breakpoint debug event + 1 + 1 + + + DWTTRAP + DWT debug event + 2 + 1 + + + VCATCH + Vector catch debug event + 3 + 1 + + + EXTERNAL + EDBGRQ debug event + 4 + 1 + + + + + + + diff --git a/svd/ATSAMC21J18AU.svd b/svd/ATSAMC21J18AU.svd new file mode 100644 index 000000000000..dd38920c0010 --- /dev/null +++ b/svd/ATSAMC21J18AU.svd @@ -0,0 +1,27996 @@ + + + + Microchip Technology + MCHP + ATSAMC21J18AU + SAMC21 + 0 + Microchip ATSAMC21J18AU Microcontroller + + CM0+ + r0p0 + selectable + true + false + 2 + false + + 8 + 32 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + AC + U22451.1.1 + Analog Comparators + AC + AC_ + 0x42005000 + + 0 + 0x24 + registers + + + AC + 27 + + + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + + + CTRLB + Control B + 0x1 + 8 + write-only + 0x00 + + + START0 + Comparator 0 Start Comparison + 0 + 1 + + + START1 + Comparator 1 Start Comparison + 1 + 1 + + + START2 + Comparator 2 Start Comparison + 2 + 1 + + + START3 + Comparator 3 Start Comparison + 3 + 1 + + + + + EVCTRL + Event Control + 0x2 + 16 + 0x0000 + + + COMPEO0 + Comparator 0 Event Output Enable + 0 + 1 + + + COMPEO1 + Comparator 1 Event Output Enable + 1 + 1 + + + COMPEO2 + Comparator 2 Event Output Enable + 2 + 1 + + + COMPEO3 + Comparator 3 Event Output Enable + 3 + 1 + + + WINEO0 + Window 0 Event Output Enable + 4 + 1 + + + WINEO1 + Window 1 Event Output Enable + 5 + 1 + + + COMPEI0 + Comparator 0 Event Input Enable + 8 + 1 + + + COMPEI1 + Comparator 1 Event Input Enable + 9 + 1 + + + COMPEI2 + Comparator 2 Event Input Enable + 10 + 1 + + + COMPEI3 + Comparator 3 Event Input Enable + 11 + 1 + + + INVEI0 + Comparator 0 Input Event Invert Enable + 12 + 1 + + + INVEI1 + Comparator 1 Input Event Invert Enable + 13 + 1 + + + INVEI2 + Comparator 2 Input Event Invert Enable + 14 + 1 + + + INVEI3 + Comparator 3 Input Event Invert Enable + 15 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x4 + 8 + 0x00 + + + COMP0 + Comparator 0 Interrupt Enable + 0 + 1 + + + COMP1 + Comparator 1 Interrupt Enable + 1 + 1 + + + COMP2 + Comparator 2 Interrupt Enable + 2 + 1 + + + COMP3 + Comparator 3 Interrupt Enable + 3 + 1 + + + WIN0 + Window 0 Interrupt Enable + 4 + 1 + + + WIN1 + Window 1 Interrupt Enable + 5 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x5 + 8 + 0x00 + + + COMP0 + Comparator 0 Interrupt Enable + 0 + 1 + + + COMP1 + Comparator 1 Interrupt Enable + 1 + 1 + + + COMP2 + Comparator 2 Interrupt Enable + 2 + 1 + + + COMP3 + Comparator 3 Interrupt Enable + 3 + 1 + + + WIN0 + Window 0 Interrupt Enable + 4 + 1 + + + WIN1 + Window 1 Interrupt Enable + 5 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x6 + 8 + 0x00 + + + COMP0 + Comparator 0 + 0 + 1 + + + COMP1 + Comparator 1 + 1 + 1 + + + COMP2 + Comparator 2 + 2 + 1 + + + COMP3 + Comparator 3 + 3 + 1 + + + WIN0 + Window 0 + 4 + 1 + + + WIN1 + Window 1 + 5 + 1 + + + + + STATUSA + Status A + 0x7 + 8 + read-only + 0x00 + + + STATE0 + Comparator 0 Current State + 0 + 1 + + + STATE1 + Comparator 1 Current State + 1 + 1 + + + STATE2 + Comparator 2 Current State + 2 + 1 + + + STATE3 + Comparator 3 Current State + 3 + 1 + + + WSTATE0 + Window 0 Current State + 4 + 2 + + WSTATE0Select + + ABOVE + Signal is above window + 0 + + + INSIDE + Signal is inside window + 1 + + + BELOW + Signal is below window + 2 + + + + + WSTATE1 + Window 1 Current State + 6 + 2 + + WSTATE1Select + + ABOVE + Signal is above window + 0 + + + INSIDE + Signal is inside window + 1 + + + BELOW + Signal is below window + 2 + + + + + + + STATUSB + Status B + 0x8 + 8 + read-only + 0x00 + + + READY0 + Comparator 0 Ready + 0 + 1 + + + READY1 + Comparator 1 Ready + 1 + 1 + + + READY2 + Comparator 2 Ready + 2 + 1 + + + READY3 + Comparator 3 Ready + 3 + 1 + + + + + DBGCTRL + Debug Control + 0x9 + 8 + 0x00 + + + DBGRUN + Debug Run + 0 + 1 + + + + + WINCTRL + Window Control + 0xA + 8 + 0x00 + + + WEN0 + Window 0 Mode Enable + 0 + 1 + + + WINTSEL0 + Window 0 Interrupt Selection + 1 + 2 + + WINTSEL0Select + + ABOVE + Interrupt on signal above window + 0 + + + INSIDE + Interrupt on signal inside window + 1 + + + BELOW + Interrupt on signal below window + 2 + + + OUTSIDE + Interrupt on signal outside window + 3 + + + + + WEN1 + Window 1 Mode Enable + 4 + 1 + + + WINTSEL1 + Window 1 Interrupt Selection + 5 + 2 + + WINTSEL1Select + + ABOVE + Interrupt on signal above window + 0 + + + INSIDE + Interrupt on signal inside window + 1 + + + BELOW + Interrupt on signal below window + 2 + + + OUTSIDE + Interrupt on signal outside window + 3 + + + + + + + 4 + 1 + SCALER[%s] + Scaler n + 0xC + 8 + 0x00 + + + VALUE + Scaler Value + 0 + 6 + + + + + 4 + 4 + COMPCTRL[%s] + Comparator Control n + 0x10 + 32 + 0x00000000 + + + ENABLE + Enable + 1 + 1 + + + SINGLE + Single-Shot Mode + 2 + 1 + + + INTSEL + Interrupt Selection + 3 + 2 + + INTSELSelect + + TOGGLE + Interrupt on comparator output toggle + 0 + + + RISING + Interrupt on comparator output rising + 1 + + + FALLING + Interrupt on comparator output falling + 2 + + + EOC + Interrupt on end of comparison (single-shot mode only) + 3 + + + + + RUNSTDBY + Run in Standby + 6 + 1 + + + MUXNEG + Negative Input Mux Selection + 8 + 3 + + MUXNEGSelect + + PIN0 + I/O pin 0 + 0 + + + PIN1 + I/O pin 1 + 1 + + + PIN2 + I/O pin 2 + 2 + + + PIN3 + I/O pin 3 + 3 + + + GND + Ground + 4 + + + VSCALE + VDD scaler + 5 + + + BANDGAP + Internal bandgap voltage + 6 + + + DAC + DAC output + 7 + + + + + MUXPOS + Positive Input Mux Selection + 12 + 3 + + MUXPOSSelect + + PIN0 + I/O pin 0 + 0 + + + PIN1 + I/O pin 1 + 1 + + + PIN2 + I/O pin 2 + 2 + + + PIN3 + I/O pin 3 + 3 + + + VSCALE + VDD Scaler + 4 + + + + + SWAP + Swap Inputs and Invert + 15 + 1 + + + SPEED + Speed Selection + 16 + 2 + + SPEEDSelect + + LOW + Low speed + 0 + + + HIGH + High speed + 3 + + + + + HYSTEN + Hysteresis Enable + 19 + 1 + + + FLEN + Filter Length + 24 + 3 + + FLENSelect + + OFF + No filtering + 0 + + + MAJ3 + 3-bit majority function (2 of 3) + 1 + + + MAJ5 + 5-bit majority function (3 of 5) + 2 + + + + + OUT + Output + 28 + 2 + + OUTSelect + + OFF + The output of COMPn is not routed to the COMPn I/O port + 0 + + + ASYNC + The asynchronous output of COMPn is routed to the COMPn I/O port + 1 + + + SYNC + The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port + 2 + + + + + + + SYNCBUSY + Synchronization Busy + 0x20 + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + Enable Synchronization Busy + 1 + 1 + + + WINCTRL + WINCTRL Synchronization Busy + 2 + 1 + + + COMPCTRL0 + COMPCTRL 0 Synchronization Busy + 3 + 1 + + + COMPCTRL1 + COMPCTRL 1 Synchronization Busy + 4 + 1 + + + COMPCTRL2 + COMPCTRL 2 Synchronization Busy + 5 + 1 + + + COMPCTRL3 + COMPCTRL 3 Synchronization Busy + 6 + 1 + + + + + + + ADC0 + U22472.2.0 + Analog Digital Converter + ADC + ADC_ + 0x42004400 + + 0 + 0x2E + registers + + + ADC0 + 25 + + + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + SLAVEEN + Slave Enable + 5 + 1 + + + RUNSTDBY + Run During Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + + + CTRLB + Control B + 0x1 + 8 + 0x00 + + + PRESCALER + Prescaler Configuration + 0 + 3 + + PRESCALERSelect + + DIV2 + Peripheral clock / 2 + 0x0 + + + DIV4 + Peripheral clock / 4 + 0x1 + + + DIV8 + Peripheral clock / 8 + 0x2 + + + DIV16 + Peripheral clock / 16 + 0x3 + + + DIV32 + Peripheral clock / 32 + 0x4 + + + DIV64 + Peripheral clock / 64 + 0x5 + + + DIV128 + Peripheral clock / 128 + 0x6 + + + DIV256 + Peripheral clock / 256 + 0x7 + + + + + + + REFCTRL + Reference Control + 0x2 + 8 + 0x00 + + + REFSEL + Reference Selection + 0 + 4 + + REFSELSelect + + INTREF + Internal Bandgap Reference + 0x0 + + + INTVCC0 + 1/1.6 VDDANA + 0x1 + + + INTVCC1 + 1/2 VDDANA + 0x2 + + + AREFA + External Reference + 0x3 + + + DAC + DAC + 0x4 + + + INTVCC2 + VDDANA + 0x5 + + + + + REFCOMP + Reference Buffer Offset Compensation Enable + 7 + 1 + + + + + EVCTRL + Event Control + 0x3 + 8 + 0x00 + + + FLUSHEI + Flush Event Input Enable + 0 + 1 + + + STARTEI + Start Conversion Event Input Enable + 1 + 1 + + + FLUSHINV + Flush Event Invert Enable + 2 + 1 + + + STARTINV + Start Event Invert Enable + 3 + 1 + + + RESRDYEO + Result Ready Event Out + 4 + 1 + + + WINMONEO + Window Monitor Event Out + 5 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x4 + 8 + 0x00 + + + RESRDY + Result Ready Interrupt Disable + 0 + 1 + + + OVERRUN + Overrun Interrupt Disable + 1 + 1 + + + WINMON + Window Monitor Interrupt Disable + 2 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x5 + 8 + 0x00 + + + RESRDY + Result Ready Interrupt Enable + 0 + 1 + + + OVERRUN + Overrun Interrupt Enable + 1 + 1 + + + WINMON + Window Monitor Interrupt Enable + 2 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x6 + 8 + 0x00 + + + RESRDY + Result Ready Interrupt Flag + 0 + 1 + + + OVERRUN + Overrun Interrupt Flag + 1 + 1 + + + WINMON + Window Monitor Interrupt Flag + 2 + 1 + + + + + SEQSTATUS + Sequence Status + 0x7 + 8 + read-only + 0x00 + + + SEQSTATE + Sequence State + 0 + 5 + + + SEQBUSY + Sequence Busy + 7 + 1 + + + + + INPUTCTRL + Input Control + 0x8 + 16 + 0x0000 + + + MUXPOS + Positive Mux Input Selection + 0 + 5 + + MUXPOSSelect + + AIN0 + ADC AIN0 Pin + 0x0 + + + AIN1 + ADC AIN1 Pin + 0x1 + + + AIN2 + ADC AIN2 Pin + 0x2 + + + AIN3 + ADC AIN3 Pin + 0x3 + + + AIN4 + ADC AIN4 Pin + 0x4 + + + AIN5 + ADC AIN5 Pin + 0x5 + + + AIN6 + ADC AIN6 Pin + 0x6 + + + AIN7 + ADC AIN7 Pin + 0x7 + + + AIN8 + ADC AIN8 Pin + 0x8 + + + AIN9 + ADC AIN9 Pin + 0x9 + + + AIN10 + ADC AIN10 Pin + 0xA + + + AIN11 + ADC AIN11 Pin + 0xB + + + BANDGAP + Bandgap Voltage + 0x19 + + + SCALEDCOREVCC + 1/4 Scaled Core Supply + 0x1A + + + SCALEDIOVCC + 1/4 Scaled I/O Supply + 0x1B + + + DAC + DAC Output + 0x1C + + + + + MUXNEG + Negative Mux Input Selection + 8 + 5 + + MUXNEGSelect + + AIN0 + ADC AIN0 Pin + 0x0 + + + AIN1 + ADC AIN1 Pin + 0x1 + + + AIN2 + ADC AIN2 Pin + 0x2 + + + AIN3 + ADC AIN3 Pin + 0x3 + + + AIN4 + ADC AIN4 Pin + 0x4 + + + AIN5 + ADC AIN5 Pin + 0x5 + + + GND + Internal Ground + 0x18 + + + + + + + CTRLC + Control C + 0xA + 16 + 0x0000 + + + DIFFMODE + Differential Mode + 0 + 1 + + + LEFTADJ + Left-Adjusted Result + 1 + 1 + + + FREERUN + Free Running Mode + 2 + 1 + + + CORREN + Digital Correction Logic Enable + 3 + 1 + + + RESSEL + Conversion Result Resolution + 4 + 2 + + RESSELSelect + + 12BIT + 12-bit + 0x0 + + + 16BIT + 16-bit averaging mode + 0x1 + + + 10BIT + 10-bit + 0x2 + + + 8BIT + 8-bit + 0x3 + + + + + R2R + Rail-to-Rail mode enable + 7 + 1 + + + WINMODE + Window Monitor Mode + 8 + 3 + + WINMODESelect + + DISABLE + No window mode (default) + 0 + + + MODE1 + RESULT > WINLT + 1 + + + MODE2 + RESULT < WINUT + 2 + + + MODE3 + WINLT < RESULT < WINUT + 3 + + + MODE4 + !(WINLT < RESULT < WINUT) + 4 + + + + + DUALSEL + Dual Mode Trigger Selection + 12 + 2 + + DUALSELSelect + + BOTH + Start event or software trigger will start a conversion on both ADCs + 0 + + + INTERLEAVE + START event or software trigger will alternately start a conversion on ADC0 and ADC1 + 1 + + + + + + + AVGCTRL + Average Control + 0xC + 8 + 0x00 + + + SAMPLENUM + Number of Samples to be Collected + 0 + 4 + + SAMPLENUMSelect + + 1 + 1 sample + 0x0 + + + 2 + 2 samples + 0x1 + + + 4 + 4 samples + 0x2 + + + 8 + 8 samples + 0x3 + + + 16 + 16 samples + 0x4 + + + 32 + 32 samples + 0x5 + + + 64 + 64 samples + 0x6 + + + 128 + 128 samples + 0x7 + + + 256 + 256 samples + 0x8 + + + 512 + 512 samples + 0x9 + + + 1024 + 1024 samples + 0xA + + + + + ADJRES + Adjusting Result / Division Coefficient + 4 + 3 + + + + + SAMPCTRL + Sample Time Control + 0xD + 8 + 0x00 + + + SAMPLEN + Sampling Time Length + 0 + 6 + + + OFFCOMP + Comparator Offset Compensation Enable + 7 + 1 + + + + + WINLT + Window Monitor Lower Threshold + 0xE + 16 + 0x0000 + + + WINLT + Window Lower Threshold + 0 + 16 + + + + + WINUT + Window Monitor Upper Threshold + 0x10 + 16 + 0x0000 + + + WINUT + Window Upper Threshold + 0 + 16 + + + + + GAINCORR + Gain Correction + 0x12 + 16 + 0x0000 + + + GAINCORR + Gain Correction Value + 0 + 12 + + + + + OFFSETCORR + Offset Correction + 0x14 + 16 + 0x0000 + + + OFFSETCORR + Offset Correction Value + 0 + 12 + + + + + SWTRIG + Software Trigger + 0x18 + 8 + 0x00 + + + FLUSH + ADC Flush + 0 + 1 + + + START + Start ADC Conversion + 1 + 1 + + + + + DBGCTRL + Debug Control + 0x1C + 8 + 0x00 + + + DBGRUN + Debug Run + 0 + 1 + + + + + SYNCBUSY + Synchronization Busy + 0x20 + 16 + read-only + 0x0000 + + + SWRST + SWRST Synchronization Busy + 0 + 1 + + + ENABLE + ENABLE Synchronization Busy + 1 + 1 + + + INPUTCTRL + INPUTCTRL Synchronization Busy + 2 + 1 + + + CTRLC + CTRLC Synchronization Busy + 3 + 1 + + + AVGCTRL + AVGCTRL Synchronization Busy + 4 + 1 + + + SAMPCTRL + SAMPCTRL Synchronization Busy + 5 + 1 + + + WINLT + WINLT Synchronization Busy + 6 + 1 + + + WINUT + WINUT Synchronization Busy + 7 + 1 + + + GAINCORR + GAINCORR Synchronization Busy + 8 + 1 + + + OFFSETCORR + OFFSETCTRL Synchronization Busy + 9 + 1 + + + SWTRIG + SWTRG Synchronization Busy + 10 + 1 + + + + + RESULT + Result + 0x24 + 16 + read-only + 0x0000 + + + RESULT + Result Value + 0 + 16 + + + + + SEQCTRL + Sequence Control + 0x28 + 32 + 0x00000000 + + + SEQEN + Enable Positive Input in the Sequence + 0 + 32 + + + + + CALIB + Calibration + 0x2C + 16 + 0x0000 + + + BIASCOMP + Bias Comparator Scaling + 0 + 3 + + + BIASREFBUF + Bias Reference Buffer Scaling + 8 + 3 + + + + + + + ADC1 + 0x42004800 + + ADC1 + 26 + + + + CAN0 + U20032.0.0 + Control Area Network + CAN + CAN_ + 0x42001C00 + + 0 + 0xFC + registers + + + CAN0 + 15 + + + + CREL + Core Release + 0x0 + 32 + read-only + 0x32100000 + + + SUBSTEP + Sub-step of Core Release + 20 + 4 + + + STEP + Step of Core Release + 24 + 4 + + + REL + Core Release + 28 + 4 + + + + + ENDN + Endian + 0x4 + 32 + read-only + 0x87654321 + + + ETV + Endianness Test Value + 0 + 32 + + + + + MRCFG + Message RAM Configuration + 0x8 + 32 + 0x00000002 + + + QOS + Quality of Service + 0 + 2 + + QOSSelect + + DISABLE + Background (no sensitive operation) + 0 + + + LOW + Sensitive Bandwidth + 1 + + + MEDIUM + Sensitive Latency + 2 + + + HIGH + Critical Latency + 3 + + + + + + + DBTP + Fast Bit Timing and Prescaler + 0xC + 32 + 0x00000A33 + + + DSJW + Data (Re)Synchronization Jump Width + 0 + 4 + + + DTSEG2 + Data time segment after sample point + 4 + 4 + + + DTSEG1 + Data time segment before sample point + 8 + 5 + + + DBRP + Data Baud Rate Prescaler + 16 + 5 + + + TDC + Tranceiver Delay Compensation + 23 + 1 + + + + + TEST + Test + 0x10 + 32 + 0x00000000 + + + LBCK + Loop Back Mode + 4 + 1 + + + TX + Control of Transmit Pin + 5 + 2 + + TXSelect + + CORE + TX controlled by CAN core + 0 + + + SAMPLE + TX monitoring sample point + 1 + + + DOMINANT + Dominant (0) level at pin CAN_TX + 2 + + + RECESSIVE + Recessive (1) level at pin CAN_TX + 3 + + + + + RX + Receive Pin + 7 + 1 + + + + + RWD + RAM Watchdog + 0x14 + 32 + 0x00000000 + + + WDC + Watchdog Configuration + 0 + 8 + + + WDV + Watchdog Value + 8 + 8 + + + + + CCCR + CC Control + 0x18 + 32 + 0x00000001 + + + INIT + Initialization + 0 + 1 + + + CCE + Configuration Change Enable + 1 + 1 + + + ASM + ASM Restricted Operation Mode + 2 + 1 + + + CSA + Clock Stop Acknowledge + 3 + 1 + + + CSR + Clock Stop Request + 4 + 1 + + + MON + Bus Monitoring Mode + 5 + 1 + + + DAR + Disable Automatic Retransmission + 6 + 1 + + + TEST + Test Mode Enable + 7 + 1 + + + FDOE + FD Operation Enable + 8 + 1 + + + BRSE + Bit Rate Switch Enable + 9 + 1 + + + PXHD + Protocol Exception Handling Disable + 12 + 1 + + + EFBI + Edge Filtering during Bus Integration + 13 + 1 + + + TXP + Transmit Pause + 14 + 1 + + + NISO + Non ISO Operation + 15 + 1 + + + + + NBTP + Nominal Bit Timing and Prescaler + 0x1C + 32 + 0x06000A03 + + + NTSEG2 + Nominal Time segment after sample point + 0 + 7 + + + NTSEG1 + Nominal Time segment before sample point + 8 + 8 + + + NBRP + Nominal Baud Rate Prescaler + 16 + 9 + + + NSJW + Nominal (Re)Synchronization Jump Width + 25 + 7 + + + + + TSCC + Timestamp Counter Configuration + 0x20 + 32 + 0x00000000 + + + TSS + Timestamp Select + 0 + 2 + + TSSSelect + + ZERO + Timestamp counter value always 0x0000 + 0 + + + INC + Timestamp counter value incremented by TCP + 1 + + + EXT + External timestamp counter value used + 2 + + + + + TCP + Timestamp Counter Prescaler + 16 + 4 + + + + + TSCV + Timestamp Counter Value + 0x24 + 32 + read-only + 0x00000000 + + + TSC + Timestamp Counter + 0 + 16 + + + + + TOCC + Timeout Counter Configuration + 0x28 + 32 + 0xFFFF0000 + + + ETOC + Enable Timeout Counter + 0 + 1 + + + TOS + Timeout Select + 1 + 2 + + TOSSelect + + CONT + Continuout operation + 0 + + + TXEF + Timeout controlled by TX Event FIFO + 1 + + + RXF0 + Timeout controlled by Rx FIFO 0 + 2 + + + RXF1 + Timeout controlled by Rx FIFO 1 + 3 + + + + + TOP + Timeout Period + 16 + 16 + + + + + TOCV + Timeout Counter Value + 0x2C + 32 + 0x0000FFFF + + + TOC + Timeout Counter + 0 + 16 + + + + + ECR + Error Counter + 0x40 + 32 + read-only + 0x00000000 + + + TEC + Transmit Error Counter + 0 + 8 + + + REC + Receive Error Counter + 8 + 7 + + + RP + Receive Error Passive + 15 + 1 + + + CEL + CAN Error Logging + 16 + 8 + + + + + PSR + Protocol Status + 0x44 + 32 + read-only + 0x00000707 + + + LEC + Last Error Code + 0 + 3 + + LECSelect + + NONE + No Error + 0 + + + STUFF + Stuff Error + 1 + + + FORM + Form Error + 2 + + + ACK + Ack Error + 3 + + + BIT1 + Bit1 Error + 4 + + + BIT0 + Bit0 Error + 5 + + + CRC + CRC Error + 6 + + + NC + No Change + 7 + + + + + ACT + Activity + 3 + 2 + + ACTSelect + + SYNC + Node is synchronizing on CAN communication + 0 + + + IDLE + Node is neither receiver nor transmitter + 1 + + + RX + Node is operating as receiver + 2 + + + TX + Node is operating as transmitter + 3 + + + + + EP + Error Passive + 5 + 1 + + + EW + Warning Status + 6 + 1 + + + BO + Bus_Off Status + 7 + 1 + + + DLEC + Data Phase Last Error Code + 8 + 3 + + DLECSelect + + NONE + No Error + 0 + + + STUFF + Stuff Error + 1 + + + FORM + Form Error + 2 + + + ACK + Ack Error + 3 + + + BIT1 + Bit1 Error + 4 + + + BIT0 + Bit0 Error + 5 + + + CRC + CRC Error + 6 + + + NC + No Change + 7 + + + + + RESI + ESI flag of last received CAN FD Message + 11 + 1 + + + RBRS + BRS flag of last received CAN FD Message + 12 + 1 + + + RFDF + Received a CAN FD Message + 13 + 1 + + + PXE + Protocol Exception Event + 14 + 1 + + + TDCV + Transmitter Delay Compensation Value + 16 + 7 + + + + + TDCR + Extended ID Filter Configuration + 0x48 + 32 + 0x00000000 + + + TDCF + Transmitter Delay Compensation Filter Length + 0 + 7 + + + TDCO + Transmitter Delay Compensation Offset + 8 + 7 + + + + + IR + Interrupt + 0x50 + 32 + 0x00000000 + + + RF0N + Rx FIFO 0 New Message + 0 + 1 + + + RF0W + Rx FIFO 0 Watermark Reached + 1 + 1 + + + RF0F + Rx FIFO 0 Full + 2 + 1 + + + RF0L + Rx FIFO 0 Message Lost + 3 + 1 + + + RF1N + Rx FIFO 1 New Message + 4 + 1 + + + RF1W + Rx FIFO 1 Watermark Reached + 5 + 1 + + + RF1F + Rx FIFO 1 FIFO Full + 6 + 1 + + + RF1L + Rx FIFO 1 Message Lost + 7 + 1 + + + HPM + High Priority Message + 8 + 1 + + + TC + Timestamp Completed + 9 + 1 + + + TCF + Transmission Cancellation Finished + 10 + 1 + + + TFE + Tx FIFO Empty + 11 + 1 + + + TEFN + Tx Event FIFO New Entry + 12 + 1 + + + TEFW + Tx Event FIFO Watermark Reached + 13 + 1 + + + TEFF + Tx Event FIFO Full + 14 + 1 + + + TEFL + Tx Event FIFO Element Lost + 15 + 1 + + + TSW + Timestamp Wraparound + 16 + 1 + + + MRAF + Message RAM Access Failure + 17 + 1 + + + TOO + Timeout Occurred + 18 + 1 + + + DRX + Message stored to Dedicated Rx Buffer + 19 + 1 + + + BEC + Bit Error Corrected + 20 + 1 + + + BEU + Bit Error Uncorrected + 21 + 1 + + + ELO + Error Logging Overflow + 22 + 1 + + + EP + Error Passive + 23 + 1 + + + EW + Warning Status + 24 + 1 + + + BO + Bus_Off Status + 25 + 1 + + + WDI + Watchdog Interrupt + 26 + 1 + + + PEA + Protocol Error in Arbitration Phase + 27 + 1 + + + PED + Protocol Error in Data Phase + 28 + 1 + + + ARA + Access to Reserved Address + 29 + 1 + + + + + IE + Interrupt Enable + 0x54 + 32 + 0x00000000 + + + RF0NE + Rx FIFO 0 New Message Interrupt Enable + 0 + 1 + + + RF0WE + Rx FIFO 0 Watermark Reached Interrupt Enable + 1 + 1 + + + RF0FE + Rx FIFO 0 Full Interrupt Enable + 2 + 1 + + + RF0LE + Rx FIFO 0 Message Lost Interrupt Enable + 3 + 1 + + + RF1NE + Rx FIFO 1 New Message Interrupt Enable + 4 + 1 + + + RF1WE + Rx FIFO 1 Watermark Reached Interrupt Enable + 5 + 1 + + + RF1FE + Rx FIFO 1 FIFO Full Interrupt Enable + 6 + 1 + + + RF1LE + Rx FIFO 1 Message Lost Interrupt Enable + 7 + 1 + + + HPME + High Priority Message Interrupt Enable + 8 + 1 + + + TCE + Timestamp Completed Interrupt Enable + 9 + 1 + + + TCFE + Transmission Cancellation Finished Interrupt Enable + 10 + 1 + + + TFEE + Tx FIFO Empty Interrupt Enable + 11 + 1 + + + TEFNE + Tx Event FIFO New Entry Interrupt Enable + 12 + 1 + + + TEFWE + Tx Event FIFO Watermark Reached Interrupt Enable + 13 + 1 + + + TEFFE + Tx Event FIFO Full Interrupt Enable + 14 + 1 + + + TEFLE + Tx Event FIFO Element Lost Interrupt Enable + 15 + 1 + + + TSWE + Timestamp Wraparound Interrupt Enable + 16 + 1 + + + MRAFE + Message RAM Access Failure Interrupt Enable + 17 + 1 + + + TOOE + Timeout Occurred Interrupt Enable + 18 + 1 + + + DRXE + Message stored to Dedicated Rx Buffer Interrupt Enable + 19 + 1 + + + BECE + Bit Error Corrected Interrupt Enable + 20 + 1 + + + BEUE + Bit Error Uncorrected Interrupt Enable + 21 + 1 + + + ELOE + Error Logging Overflow Interrupt Enable + 22 + 1 + + + EPE + Error Passive Interrupt Enable + 23 + 1 + + + EWE + Warning Status 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detection + 5 + + + + + FILTEN4 + Filter Enable 4 + 19 + 1 + + + SENSE5 + Input Sense Configuration 5 + 20 + 3 + + SENSE5Select + + NONE + No detection + 0 + + + RISE + Rising edge detection + 1 + + + FALL + Falling edge detection + 2 + + + BOTH + Both edges detection + 3 + + + HIGH + High level detection + 4 + + + LOW + Low level detection + 5 + + + + + FILTEN5 + Filter Enable 5 + 23 + 1 + + + SENSE6 + Input Sense Configuration 6 + 24 + 3 + + SENSE6Select + + NONE + No detection + 0 + + + RISE + Rising edge detection + 1 + + + FALL + Falling edge detection + 2 + + + BOTH + Both edges detection + 3 + + + HIGH + High level detection + 4 + + + LOW + Low level detection + 5 + + + + + FILTEN6 + Filter Enable 6 + 27 + 1 + + + SENSE7 + Input Sense Configuration 7 + 28 + 3 + + SENSE7Select + + NONE + No detection + 0 + + + RISE + Rising edge detection + 1 + + + FALL + Falling edge detection + 2 + + + BOTH + Both edges detection + 3 + + + HIGH + High level detection + 4 + + + LOW + Low level detection + 5 + + + + + FILTEN7 + Filter Enable 7 + 31 + 1 + + + + + + + EVSYS + U22561.0.2 + Event System Interface + EVSYS + EVSYS_ + 0x42000000 + + 0 + 0x19C + registers + + + EVSYS + 8 + + + + CTRLA + Control + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + + + CHSTATUS + Channel Status + 0xC + 32 + read-only + 0x00000000 + + + USRRDY0 + Channel 0 User Ready + 0 + 1 + + + USRRDY1 + Channel 1 User Ready + 1 + 1 + + + USRRDY2 + Channel 2 User Ready + 2 + 1 + + + USRRDY3 + Channel 3 User Ready + 3 + 1 + + + USRRDY4 + Channel 4 User Ready + 4 + 1 + + + USRRDY5 + Channel 5 User Ready + 5 + 1 + + + USRRDY6 + Channel 6 User Ready + 6 + 1 + + + USRRDY7 + Channel 7 User Ready + 7 + 1 + + + USRRDY8 + Channel 8 User Ready + 8 + 1 + + + USRRDY9 + Channel 9 User Ready + 9 + 1 + + + USRRDY10 + Channel 10 User Ready + 10 + 1 + + + USRRDY11 + Channel 11 User Ready + 11 + 1 + + + CHBUSY0 + Channel 0 Busy + 16 + 1 + + + CHBUSY1 + Channel 1 Busy + 17 + 1 + + + CHBUSY2 + Channel 2 Busy + 18 + 1 + + + CHBUSY3 + Channel 3 Busy + 19 + 1 + + + CHBUSY4 + Channel 4 Busy + 20 + 1 + + + CHBUSY5 + Channel 5 Busy + 21 + 1 + + + CHBUSY6 + Channel 6 Busy + 22 + 1 + + + CHBUSY7 + Channel 7 Busy + 23 + 1 + + + CHBUSY8 + Channel 8 Busy + 24 + 1 + + + CHBUSY9 + Channel 9 Busy + 25 + 1 + + + CHBUSY10 + Channel 10 Busy + 26 + 1 + + + CHBUSY11 + Channel 11 Busy + 27 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x10 + 32 + 0x00000000 + + + OVR0 + Channel 0 Overrun Interrupt Enable + 0 + 1 + + + OVR1 + Channel 1 Overrun Interrupt Enable + 1 + 1 + + + OVR2 + Channel 2 Overrun Interrupt Enable + 2 + 1 + + + OVR3 + Channel 3 Overrun Interrupt Enable + 3 + 1 + + + OVR4 + Channel 4 Overrun Interrupt Enable + 4 + 1 + + + OVR5 + Channel 5 Overrun Interrupt Enable + 5 + 1 + + + OVR6 + Channel 6 Overrun Interrupt Enable + 6 + 1 + + + OVR7 + Channel 7 Overrun Interrupt Enable + 7 + 1 + + + OVR8 + Channel 8 Overrun Interrupt Enable + 8 + 1 + + + OVR9 + Channel 9 Overrun Interrupt Enable + 9 + 1 + + + OVR10 + Channel 10 Overrun Interrupt Enable + 10 + 1 + + + OVR11 + Channel 11 Overrun Interrupt Enable + 11 + 1 + + + EVD0 + Channel 0 Event Detection Interrupt Enable + 16 + 1 + + + EVD1 + Channel 1 Event Detection Interrupt Enable + 17 + 1 + + + EVD2 + Channel 2 Event Detection Interrupt Enable + 18 + 1 + + + EVD3 + Channel 3 Event Detection Interrupt Enable + 19 + 1 + + + EVD4 + Channel 4 Event Detection Interrupt Enable + 20 + 1 + + + EVD5 + Channel 5 Event Detection Interrupt Enable + 21 + 1 + + + EVD6 + Channel 6 Event Detection Interrupt Enable + 22 + 1 + + + EVD7 + Channel 7 Event Detection Interrupt Enable + 23 + 1 + + + EVD8 + Channel 8 Event Detection Interrupt Enable + 24 + 1 + + + EVD9 + Channel 9 Event Detection Interrupt Enable + 25 + 1 + + + EVD10 + Channel 10 Event Detection Interrupt Enable + 26 + 1 + + + EVD11 + Channel 11 Event Detection Interrupt Enable + 27 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x14 + 32 + 0x00000000 + + + OVR0 + Channel 0 Overrun Interrupt Enable + 0 + 1 + + + OVR1 + Channel 1 Overrun Interrupt Enable + 1 + 1 + + + OVR2 + Channel 2 Overrun Interrupt Enable + 2 + 1 + + + OVR3 + Channel 3 Overrun Interrupt Enable + 3 + 1 + + + OVR4 + Channel 4 Overrun Interrupt Enable + 4 + 1 + + + OVR5 + Channel 5 Overrun Interrupt Enable + 5 + 1 + + + OVR6 + Channel 6 Overrun Interrupt Enable + 6 + 1 + + + OVR7 + Channel 7 Overrun Interrupt Enable + 7 + 1 + + + OVR8 + Channel 8 Overrun Interrupt Enable + 8 + 1 + + + OVR9 + Channel 9 Overrun Interrupt Enable + 9 + 1 + + + OVR10 + Channel 10 Overrun Interrupt Enable + 10 + 1 + + + OVR11 + Channel 11 Overrun Interrupt Enable + 11 + 1 + + + EVD0 + Channel 0 Event Detection Interrupt Enable + 16 + 1 + + + EVD1 + Channel 1 Event Detection Interrupt Enable + 17 + 1 + + + EVD2 + Channel 2 Event Detection Interrupt Enable + 18 + 1 + + + EVD3 + Channel 3 Event Detection Interrupt Enable + 19 + 1 + + + EVD4 + Channel 4 Event Detection Interrupt Enable + 20 + 1 + + + EVD5 + Channel 5 Event Detection Interrupt Enable + 21 + 1 + + + EVD6 + Channel 6 Event Detection Interrupt Enable + 22 + 1 + + + EVD7 + Channel 7 Event Detection Interrupt Enable + 23 + 1 + + + EVD8 + Channel 8 Event Detection Interrupt Enable + 24 + 1 + + + EVD9 + Channel 9 Event Detection Interrupt Enable + 25 + 1 + + + EVD10 + Channel 10 Event Detection Interrupt Enable + 26 + 1 + + + EVD11 + Channel 11 Event Detection Interrupt Enable + 27 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x18 + 32 + 0x00000000 + + + OVR0 + Channel 0 Overrun + 0 + 1 + + + OVR1 + Channel 1 Overrun + 1 + 1 + + + OVR2 + Channel 2 Overrun + 2 + 1 + + + OVR3 + Channel 3 Overrun + 3 + 1 + + + OVR4 + Channel 4 Overrun + 4 + 1 + + + OVR5 + Channel 5 Overrun + 5 + 1 + + + OVR6 + Channel 6 Overrun + 6 + 1 + + + OVR7 + Channel 7 Overrun + 7 + 1 + + + OVR8 + Channel 8 Overrun + 8 + 1 + + + OVR9 + Channel 9 Overrun + 9 + 1 + + + OVR10 + Channel 10 Overrun + 10 + 1 + + + OVR11 + Channel 11 Overrun + 11 + 1 + + + EVD0 + Channel 0 Event Detection + 16 + 1 + + + EVD1 + Channel 1 Event Detection + 17 + 1 + + + EVD2 + Channel 2 Event Detection + 18 + 1 + + + EVD3 + Channel 3 Event Detection + 19 + 1 + + + EVD4 + Channel 4 Event Detection + 20 + 1 + + + EVD5 + Channel 5 Event Detection + 21 + 1 + + + EVD6 + Channel 6 Event Detection + 22 + 1 + + + EVD7 + Channel 7 Event Detection + 23 + 1 + + + EVD8 + Channel 8 Event Detection + 24 + 1 + + + EVD9 + Channel 9 Event Detection + 25 + 1 + + + EVD10 + Channel 10 Event Detection + 26 + 1 + + + EVD11 + Channel 11 Event Detection + 27 + 1 + + + + + SWEVT + Software Event + 0x1C + 32 + write-only + 0x00000000 + + + CHANNEL0 + Channel 0 Software Selection + 0 + 1 + + + CHANNEL1 + Channel 1 Software Selection + 1 + 1 + + + CHANNEL2 + Channel 2 Software Selection + 2 + 1 + + + CHANNEL3 + Channel 3 Software Selection + 3 + 1 + + + CHANNEL4 + Channel 4 Software Selection + 4 + 1 + + + CHANNEL5 + Channel 5 Software Selection + 5 + 1 + + + CHANNEL6 + Channel 6 Software Selection + 6 + 1 + + + CHANNEL7 + Channel 7 Software Selection + 7 + 1 + + + CHANNEL8 + Channel 8 Software Selection + 8 + 1 + + + CHANNEL9 + Channel 9 Software Selection + 9 + 1 + + + CHANNEL10 + Channel 10 Software Selection + 10 + 1 + + + CHANNEL11 + Channel 11 Software Selection + 11 + 1 + + + + + 12 + 4 + CHANNEL[%s] + Channel n + 0x20 + 32 + 0x00008000 + + + EVGEN + Event Generator Selection + 0 + 7 + + + PATH + Path Selection + 8 + 2 + + PATHSelect + + SYNCHRONOUS + Synchronous path + 0 + + + RESYNCHRONIZED + Resynchronized path + 1 + + + ASYNCHRONOUS + Asynchronous path + 2 + + + + + EDGSEL + Edge Detection Selection + 10 + 2 + + EDGSELSelect + + NO_EVT_OUTPUT + No event output when using the resynchronized or synchronous path + 0 + + + RISING_EDGE + Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path + 1 + + + FALLING_EDGE + Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path + 2 + + + BOTH_EDGES + Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path + 3 + + + + + RUNSTDBY + Run in standby + 14 + 1 + + + ONDEMAND + Generic Clock On Demand + 15 + 1 + + + + + 47 + 4 + USER[%s] + User Multiplexer n + 0x80 + 32 + 0x00000000 + + + CHANNEL + Channel Event Selection + 0 + 5 + + + + + + + FREQM + U22571.0.1 + Frequency Meter + FREQM + FREQM_ + 0x40002C00 + + 0 + 0x14 + registers + + + FREQM + 4 + + + + CTRLA + Control A Register + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + + + CTRLB + Control B Register + 0x1 + 8 + write-only + 0x00 + + + START + Start Measurement + 0 + 1 + + + + + CFGA + Config A register + 0x2 + 16 + 0x0000 + + + REFNUM + Number of Reference Clock Cycles + 0 + 8 + + + + + INTENCLR + Interrupt Enable Clear Register + 0x8 + 8 + 0x00 + + + DONE + Measurement Done Interrupt Enable + 0 + 1 + + + + + INTENSET + Interrupt Enable Set Register + 0x9 + 8 + 0x00 + + + DONE + Measurement Done Interrupt Enable + 0 + 1 + + + + + INTFLAG + Interrupt Flag Register + 0xA + 8 + 0x00 + + + DONE + Measurement Done + 0 + 1 + + + + + STATUS + Status Register + 0xB + 8 + 0x00 + + + BUSY + FREQM Status + 0 + 1 + + + OVF + Sticky Count Value Overflow + 1 + 1 + + + + + SYNCBUSY + Synchronization Busy Register + 0xC + 32 + read-only + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + + + VALUE + Count Value Register + 0x10 + 32 + read-only + 0x00000000 + + + VALUE + Measurement Value + 0 + 24 + + + + + + + GCLK + U21221.1.1 + Generic Clock Generator + GCLK + GCLK_ + 0x40001C00 + + 0 + 0x184 + registers + + + + CTRLA + Control + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + + + SYNCBUSY + Synchronization Busy + 0x4 + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchroniation Busy bit + 0 + 1 + + + GENCTRL0 + Generic Clock Generator Control 0 Synchronization Busy bits + 2 + 1 + + GENCTRL0Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + + + GENCTRL1 + Generic Clock Generator Control 1 Synchronization Busy bits + 3 + 1 + + GENCTRL1Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + + + GENCTRL2 + Generic Clock Generator Control 2 Synchronization Busy bits + 4 + 1 + + GENCTRL2Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + + + GENCTRL3 + Generic Clock Generator Control 3 Synchronization Busy bits + 5 + 1 + + GENCTRL3Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + + + GENCTRL4 + Generic Clock Generator Control 4 Synchronization Busy bits + 6 + 1 + + GENCTRL4Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + + + GENCTRL5 + Generic Clock Generator Control 5 Synchronization Busy bits + 7 + 1 + + GENCTRL5Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + + + GENCTRL6 + Generic Clock Generator Control 6 Synchronization Busy bits + 8 + 1 + + GENCTRL6Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + + + GENCTRL7 + Generic Clock Generator Control 7 Synchronization Busy bits + 9 + 1 + + GENCTRL7Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + + + GENCTRL8 + Generic Clock Generator Control 8 Synchronization Busy bits + 10 + 1 + + GENCTRL8Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + + + + + 9 + 4 + GENCTRL[%s] + Generic Clock Generator Control + 0x20 + 32 + 0x00000000 + + + SRC + Source Select + 0 + 3 + + SRCSelect + + XOSC + XOSC oscillator output + 0 + + + GCLKIN + Generator input pad + 1 + + + GCLKGEN1 + Generic clock generator 1 output + 2 + + + OSCULP32K + OSCULP32K oscillator output + 3 + + + OSC32K + OSC32K oscillator output + 4 + + + XOSC32K + XOSC32K oscillator output + 5 + + + OSC48M + OSC48M oscillator output + 6 + + + DPLL96M + DPLL96M output + 7 + + + + + GENEN + Generic Clock Generator Enable + 8 + 1 + + + IDC + Improve Duty Cycle + 9 + 1 + + + OOV + Output Off Value + 10 + 1 + + + OE + Output Enable + 11 + 1 + + + DIVSEL + Divide Selection + 12 + 1 + + DIVSELSelect + + DIV1 + Divide input directly by divider factor + 0x0 + + + DIV2 + Divide input by 2^(divider factor+ 1) + 0x1 + + + + + RUNSTDBY + Run in Standby + 13 + 1 + + + DIV + Division Factor + 16 + 16 + + + + + 41 + 4 + PCHCTRL[%s] + Peripheral Clock Control + 0x80 + 32 + 0x00000000 + + + GEN + Generic Clock Generator + 0 + 4 + + GENSelect + + GCLK0 + Generic clock generator 0 + 0x0 + + + GCLK1 + Generic clock generator 1 + 0x1 + + + GCLK2 + Generic clock generator 2 + 0x2 + + + GCLK3 + Generic clock generator 3 + 0x3 + + + GCLK4 + Generic clock generator 4 + 0x4 + + + GCLK5 + Generic clock generator 5 + 0x5 + + + GCLK6 + Generic clock generator 6 + 0x6 + + + GCLK7 + Generic clock generator 7 + 0x7 + + + GCLK8 + Generic clock generator 8 + 0x8 + + + + + CHEN + Channel Enable + 6 + 1 + + + WRTLOCK + Write Lock + 7 + 1 + + + + + + + HMATRIXHS + I76382.1.3 + HSB Matrix + HMATRIXB + HMATRIXB_ + 0x4100A000 + + 0 + 0x168 + registers + + + + 16 + 4 + MCFG[%s] + Master Configuration + 0x0 + 32 + 0x00000002 + + + ULBT + Undefined Length Burst Type + 0 + 3 + + ULBTSelect + + INFINITE + Infinite Length + 0 + + + SINGLE + Single Access + 1 + + + FOUR_BEAT + Four Beat Burst + 2 + + + EIGHT_BEAT + Eight Beat Burst + 3 + + + SIXTEEN_BEAT + Sixteen Beat Burst + 4 + + + + + + + 16 + 4 + SCFG[%s] + Slave Configuration + 0x40 + 32 + 0x00000010 + + + SLOT_CYCLE + Maximum Number of Allowed Cycles for a Burst + 0 + 8 + + + DEFMSTR_TYPE + Default Master Type + 16 + 2 + + DEFMSTR_TYPESelect + + NO_DEFAULT + No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. + 0 + + + LAST_DEFAULT + Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. + 1 + + + FIXED_DEFAULT + Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave. + 2 + + + + + FIXED_DEFMSTR + Fixed Index of Default Master + 18 + 4 + + + ARBT + Arbitration Type + 24 + 1 + + ARBTSelect + + ROUND_ROBIN + Round-Robin Arbitration + 0 + + + FIXED_PRIORITY + Fixed Priority Arbitration + 1 + + + + + + + 4 + 0x8 + PRS[%s] + + 0x080 + + PRAS + Priority A for Slave + 0x0 + 32 + 0x00000000 + + + M0PR + Master 0 Priority + 0 + 4 + + + M1PR + Master 1 Priority + 4 + 4 + + + M2PR + Master 2 Priority + 8 + 4 + + + M3PR + Master 3 Priority + 12 + 4 + + + M4PR + Master 4 Priority + 16 + 4 + + + M5PR + Master 5 Priority + 20 + 4 + + + M6PR + Master 6 Priority + 24 + 4 + + + M7PR + Master 7 Priority + 28 + 4 + + + + + PRBS + Priority B for Slave + 0x4 + 32 + 0x00000000 + + + M8PR + Master 8 Priority + 0 + 4 + + + M9PR + Master 9 Priority + 4 + 4 + + + M10PR + Master 10 Priority + 8 + 4 + + + M11PR + Master 11 Priority + 12 + 4 + + + M12PR + Master 12 Priority + 16 + 4 + + + M13PR + Master 13 Priority + 20 + 4 + + + M14PR + Master 14 Priority + 24 + 4 + + + M15PR + Master 15 Priority + 28 + 4 + + + + + + MRCR + Master Remap Control + 0x100 + 32 + 0x00000000 + + + RCB0 + Remap Command Bit for Master 0 + 0 + 1 + + RCB0Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB1 + Remap Command Bit for Master 1 + 1 + 1 + + RCB1Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB2 + Remap Command Bit for Master 2 + 2 + 1 + + RCB2Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB3 + Remap Command Bit for Master 3 + 3 + 1 + + RCB3Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB4 + Remap Command Bit for Master 4 + 4 + 1 + + RCB4Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB5 + Remap Command Bit for Master 5 + 5 + 1 + + RCB5Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB6 + Remap Command Bit for Master 6 + 6 + 1 + + RCB6Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB7 + Remap Command Bit for Master 7 + 7 + 1 + + RCB7Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB8 + Remap Command Bit for Master 8 + 8 + 1 + + RCB8Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB9 + Remap Command Bit for Master 9 + 9 + 1 + + RCB9Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB10 + Remap Command Bit for Master 10 + 10 + 1 + + RCB10Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB11 + Remap Command Bit for Master 11 + 11 + 1 + + RCB11Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB12 + Remap Command Bit for Master 12 + 12 + 1 + + RCB12Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB13 + Remap Command Bit for Master 13 + 13 + 1 + + RCB13Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB14 + Remap Command Bit for Master 14 + 14 + 1 + + RCB14Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB15 + Remap Command Bit for Master 15 + 15 + 1 + + RCB15Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + + + 16 + 4 + SFR[%s] + Special Function + 0x110 + 32 + 0x00000000 + + + SFR + Special Function Register + 0 + 32 + + + + + + + MCLK + U22342.0.0 + Main Clock + MCLK + MCLK_ + 0x40000800 + + 0 + 0x20 + registers + + + + INTENCLR + Interrupt Enable Clear + 0x1 + 8 + 0x00 + + + CKRDY + Clock Ready Interrupt Enable + 0 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x2 + 8 + 0x00 + + + CKRDY + Clock Ready Interrupt Enable + 0 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x3 + 8 + 0x01 + + + CKRDY + Clock Ready + 0 + 1 + + + + + CPUDIV + CPU Clock Division + 0x4 + 8 + 0x01 + + + CPUDIV + CPU Clock Division Factor + 0 + 8 + + CPUDIVSelect + + DIV1 + Divide by 1 + 0x01 + + + DIV2 + Divide by 2 + 0x02 + + + DIV4 + Divide by 4 + 0x04 + + + DIV8 + Divide by 8 + 0x08 + + + DIV16 + Divide by 16 + 0x10 + + + DIV32 + Divide by 32 + 0x20 + + + DIV64 + Divide by 64 + 0x40 + + + DIV128 + Divide by 128 + 0x80 + + + + + + + AHBMASK + AHB Mask + 0x10 + 32 + 0x00001CFF + + + HPB0_ + HPB0 AHB Clock Mask + 0 + 1 + + + HPB1_ + HPB1 AHB Clock Mask + 1 + 1 + + + HPB2_ + HPB2 AHB Clock Mask + 2 + 1 + + + DSU_ + DSU AHB Clock Mask + 3 + 1 + + + HMATRIXHS_ + HMATRIXHS AHB Clock Mask + 4 + 1 + + + NVMCTRL_ + NVMCTRL AHB Clock Mask + 5 + 1 + + + HSRAM_ + HSRAM AHB Clock Mask + 6 + 1 + + + DMAC_ + DMAC AHB Clock Mask + 7 + 1 + + + CAN0_ + CAN0 AHB Clock Mask + 8 + 1 + + + CAN1_ + CAN1 AHB Clock Mask + 9 + 1 + + + PAC_ + PAC AHB Clock Mask + 10 + 1 + + + NVMCTRL_PICACHU_ + NVMCTRL_PICACHU AHB Clock Mask + 11 + 1 + + + DIVAS_ + DIVAS AHB Clock Mask + 12 + 1 + + + + + APBAMASK + APBA Mask + 0x14 + 32 + 0x00000FFF + + + PAC_ + PAC APB Clock Enable + 0 + 1 + + + PM_ + PM APB Clock Enable + 1 + 1 + + + MCLK_ + MCLK APB Clock Enable + 2 + 1 + + + RSTC_ + RSTC APB Clock Enable + 3 + 1 + + + OSCCTRL_ + OSCCTRL APB Clock Enable + 4 + 1 + + + OSC32KCTRL_ + OSC32KCTRL APB Clock Enable + 5 + 1 + + + SUPC_ + SUPC APB Clock Enable + 6 + 1 + + + GCLK_ + GCLK APB Clock Enable + 7 + 1 + + + WDT_ + WDT APB Clock Enable + 8 + 1 + + + RTC_ + RTC APB Clock Enable + 9 + 1 + + + EIC_ + EIC APB Clock Enable + 10 + 1 + + + FREQM_ + FREQM APB Clock Enable + 11 + 1 + + + TSENS_ + TSENS APB Clock Enable + 12 + 1 + + + + + APBBMASK + APBB Mask + 0x18 + 32 + 0x00000007 + + + PORT_ + PORT APB Clock Enable + 0 + 1 + + + DSU_ + DSU APB Clock Enable + 1 + 1 + + + NVMCTRL_ + NVMCTRL APB Clock Enable + 2 + 1 + + + HMATRIXHS_ + HMATRIXHS APB Clock Enable + 5 + 1 + + + + + APBCMASK + APBC Mask + 0x1C + 32 + 0x00000000 + + + EVSYS_ + EVSYS APB Clock Enable + 0 + 1 + + + SERCOM0_ + SERCOM0 APB Clock Enable + 1 + 1 + + + SERCOM1_ + SERCOM1 APB Clock Enable + 2 + 1 + + + SERCOM2_ + SERCOM2 APB Clock Enable + 3 + 1 + + + SERCOM3_ + SERCOM3 APB Clock Enable + 4 + 1 + + + SERCOM4_ + SERCOM4 APB Clock Enable + 5 + 1 + + + SERCOM5_ + SERCOM5 APB Clock Enable + 6 + 1 + + + TCC0_ + TCC0 APB Clock Enable + 9 + 1 + + + TCC1_ + TCC1 APB Clock Enable + 10 + 1 + + + TCC2_ + TCC2 APB Clock Enable + 11 + 1 + + + TC0_ + TC0 APB Clock Enable + 12 + 1 + + + TC1_ + TC1 APB Clock Enable + 13 + 1 + + + TC2_ + TC2 APB Clock Enable + 14 + 1 + + + TC3_ + TC3 APB Clock Enable + 15 + 1 + + + TC4_ + TC4 APB Clock Enable + 16 + 1 + + + ADC0_ + ADC0 APB Clock Enable + 17 + 1 + + + ADC1_ + ADC1 APB Clock Enable + 18 + 1 + + + SDADC_ + SDADC APB Clock Enable + 19 + 1 + + + AC_ + AC APB Clock Enable + 20 + 1 + + + DAC_ + DAC APB Clock Enable + 21 + 1 + + + PTC_ + PTC APB Clock Enable + 22 + 1 + + + CCL_ + CCL APB Clock Enable + 23 + 1 + + + + + + + MTB + U20021.0.0 + Cortex-M0+ Micro-Trace Buffer + MTB + MTB_ + 0x41008000 + + 0 + 0x1000 + registers + + + + POSITION + MTB Position + 0x0 + 32 + + + WRAP + Pointer Value Wraps + 2 + 1 + + + POINTER + Trace Packet Location Pointer + 3 + 29 + + + + + MASTER + MTB Master + 0x4 + 32 + 0x00000000 + + + MASK + Maximum Value of the Trace Buffer in SRAM + 0 + 5 + + + TSTARTEN + Trace Start Input Enable + 5 + 1 + + + TSTOPEN + Trace Stop Input Enable + 6 + 1 + + + SFRWPRIV + Special Function Register Write Privilege + 7 + 1 + + + RAMPRIV + SRAM Privilege + 8 + 1 + + + HALTREQ + Halt Request + 9 + 1 + + + EN + Main Trace Enable + 31 + 1 + + + + + FLOW + MTB Flow + 0x8 + 32 + 0x00000000 + + + AUTOSTOP + Auto Stop Tracing + 0 + 1 + + + AUTOHALT + Auto Halt Request + 1 + 1 + + + WATERMARK + Watermark value + 3 + 29 + + + + + BASE + MTB Base + 0xC + 32 + read-only + + + ITCTRL + MTB Integration Mode Control + 0xF00 + 32 + + + CLAIMSET + MTB Claim Set + 0xFA0 + 32 + + + CLAIMCLR + MTB Claim Clear + 0xFA4 + 32 + + + LOCKACCESS + MTB Lock Access + 0xFB0 + 32 + + + LOCKSTATUS + MTB Lock Status + 0xFB4 + 32 + read-only + + + AUTHSTATUS + MTB Authentication Status + 0xFB8 + 32 + read-only + + + DEVARCH + MTB Device Architecture + 0xFBC + 32 + read-only + + + DEVID + MTB Device Configuration + 0xFC8 + 32 + read-only + + + DEVTYPE + MTB Device Type + 0xFCC + 32 + read-only + + + PID4 + Peripheral Identification 4 + 0xFD0 + 32 + read-only + + + PID5 + Peripheral Identification 5 + 0xFD4 + 32 + read-only + + + PID6 + Peripheral Identification 6 + 0xFD8 + 32 + read-only + + + PID7 + Peripheral Identification 7 + 0xFDC + 32 + read-only + + + PID0 + Peripheral Identification 0 + 0xFE0 + 32 + read-only + + + PID1 + Peripheral Identification 1 + 0xFE4 + 32 + read-only + + + PID2 + Peripheral Identification 2 + 0xFE8 + 32 + read-only + + + PID3 + Peripheral Identification 3 + 0xFEC + 32 + read-only + + + CID0 + Component Identification 0 + 0xFF0 + 32 + read-only + + + CID1 + Component Identification 1 + 0xFF4 + 32 + read-only + + + CID2 + Component Identification 2 + 0xFF8 + 32 + read-only + + + CID3 + Component Identification 3 + 0xFFC + 32 + read-only + + + + + NVMCTRL + U22074.0.1.1 + Non-Volatile Memory Controller + NVMCTRL + NVMCTRL_ + 0x41004000 + + 0 + 0x30 + registers + + + NVMCTRL + 6 + + + + CTRLA + Control A + 0x0 + 16 + 0x0000 + + + CMD + Command + 0 + 7 + + CMDSelect + + ER + Erase Row - Erases the row addressed by the ADDR register. + 0x02 + + + WP + Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. + 0x04 + + + EAR + Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. + 0x05 + + + WAP + Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. + 0x06 + + + SF + Security Flow Command + 0x0A + + + WL + Write lockbits + 0x0F + + + RWWEEER + RWW EEPROM area Erase Row - Erases the row addressed by the ADDR register. + 0x1A + + + RWWEEWP + RWW EEPROM Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. + 0x1C + + + LR + Lock Region - Locks the region containing the address location in the ADDR register. + 0x40 + + + UR + Unlock Region - Unlocks the region containing the address location in the ADDR register. + 0x41 + + + SPRM + Sets the power reduction mode. + 0x42 + + + CPRM + Clears the power reduction mode. + 0x43 + + + PBC + Page Buffer Clear - Clears the page buffer. + 0x44 + + + SSB + Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row. + 0x45 + + + INVALL + Invalidate all cache lines. + 0x46 + + + + + CMDEX + Command Execution + 8 + 8 + + CMDEXSelect + + KEY + Execution Key + 0xA5 + + + + + + + CTRLB + Control B + 0x4 + 32 + 0x00000080 + + + RWS + NVM Read Wait States + 1 + 4 + + RWSSelect + + SINGLE + Single Auto Wait State + 0 + + + HALF + Half Auto Wait State + 1 + + + DUAL + Dual Auto Wait State + 2 + + + + + MANW + Manual Write + 7 + 1 + + + SLEEPPRM + Power Reduction Mode during Sleep + 8 + 2 + + SLEEPPRMSelect + + WAKEONACCESS + NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access. + 0 + + + WAKEUPINSTANT + NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep. + 1 + + + DISABLED + Auto power reduction disabled. + 3 + + + + + READMODE + NVMCTRL Read Mode + 16 + 2 + + READMODESelect + + NO_MISS_PENALTY + The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance. + 0x0 + + + LOW_POWER + Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time. + 0x1 + + + DETERMINISTIC + The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings. + 0x2 + + + + + CACHEDIS + Cache Disable + 18 + 2 + + + + + PARAM + NVM Parameter + 0x8 + 32 + 0x00000000 + + + NVMP + NVM Pages + 0 + 16 + + + PSZ + Page Size + 16 + 3 + + PSZSelect + + 8 + 8 bytes + 0x0 + + + 16 + 16 bytes + 0x1 + + + 32 + 32 bytes + 0x2 + + + 64 + 64 bytes + 0x3 + + + 128 + 128 bytes + 0x4 + + + 256 + 256 bytes + 0x5 + + + 512 + 512 bytes + 0x6 + + + 1024 + 1024 bytes + 0x7 + + + + + RWWEEP + RWW EEPROM Pages + 20 + 12 + + + + + INTENCLR + Interrupt Enable Clear + 0xC + 8 + 0x00 + + + READY + NVM Ready Interrupt Enable + 0 + 1 + + + ERROR + Error Interrupt Enable + 1 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x10 + 8 + 0x00 + + + READY + NVM Ready Interrupt Enable + 0 + 1 + + + ERROR + Error Interrupt Enable + 1 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x14 + 8 + 0x00 + + + READY + NVM Ready + 0 + 1 + + + ERROR + Error + 1 + 1 + + + + + STATUS + Status + 0x18 + 16 + 0x0000 + + + PRM + Power Reduction Mode + 0 + 1 + + + LOAD + NVM Page Buffer Active Loading + 1 + 1 + + + PROGE + Programming Error Status + 2 + 1 + + + LOCKE + Lock Error Status + 3 + 1 + + + NVME + NVM Error + 4 + 1 + + + SB + Security Bit Status + 8 + 1 + + + + + ADDR + Address + 0x1C + 32 + 0x00000000 + + + ADDR + NVM Address + 0 + 22 + + + + + LOCK + Lock Section + 0x20 + 16 + 0x0000 + + + LOCK + Region Lock Bits + 0 + 16 + + + + + PBLDATA0 + Page Buffer Load Data 0 + 0x28 + 32 + read-only + 0x00000000 + + + PBLDATA1 + Page Buffer Load Data 1 + 0x2C + 32 + read-only + 0x00000000 + + + + + OSCCTRL + U21192.1.0 + Oscillators Control + OSCCTRL + OSCCTRL_ + 0x40001000 + + 0 + 0x3C + registers + + + + INTENCLR + Interrupt Enable Clear + 0x0 + 32 + 0x00000000 + + + XOSCRDY + XOSC Ready Interrupt Enable + 0 + 1 + + + XOSCFAIL + XOSC Clock Failure Detector Interrupt Enable + 1 + 1 + + + OSC48MRDY + OSC48M Ready Interrupt Enable + 4 + 1 + + + DPLLLCKR + DPLL Lock Rise Interrupt Enable + 8 + 1 + + + DPLLLCKF + DPLL Lock Fall Interrupt Enable + 9 + 1 + + + DPLLLTO + DPLL Time Out Interrupt Enable + 10 + 1 + + + DPLLLDRTO + DPLL Ratio Ready Interrupt Enable + 11 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x4 + 32 + 0x00000000 + + + XOSCRDY + XOSC Ready Interrupt Enable + 0 + 1 + + + XOSCFAIL + XOSC Clock Failure Detector Interrupt Enable + 1 + 1 + + + OSC48MRDY + OSC48M Ready Interrupt Enable + 4 + 1 + + + DPLLLCKR + DPLL Lock Rise Interrupt Enable + 8 + 1 + + + DPLLLCKF + DPLL Lock Fall Interrupt Enable + 9 + 1 + + + DPLLLTO + DPLL Time Out Interrupt Enable + 10 + 1 + + + DPLLLDRTO + DPLL Ratio Ready Interrupt Enable + 11 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x8 + 32 + 0x00000000 + + + XOSCRDY + XOSC Ready + 0 + 1 + + + XOSCFAIL + XOSC Clock Failure Detector + 1 + 1 + + + OSC48MRDY + OSC48M Ready + 4 + 1 + + + DPLLLCKR + DPLL Lock Rise + 8 + 1 + + + DPLLLCKF + DPLL Lock Fall + 9 + 1 + + + DPLLLTO + DPLL Timeout + 10 + 1 + + + DPLLLDRTO + DPLL Ratio Ready + 11 + 1 + + + + + STATUS + Power and Clocks Status + 0xC + 32 + read-only + 0x00000000 + + + XOSCRDY + XOSC Ready + 0 + 1 + + + XOSCFAIL + XOSC Clock Failure Detector + 1 + 1 + + + XOSCCKSW + XOSC Clock Switch + 2 + 1 + + + OSC48MRDY + OSC48M Ready + 4 + 1 + + + DPLLLCKR + DPLL Lock Rise + 8 + 1 + + + DPLLLCKF + DPLL Lock Fall + 9 + 1 + + + DPLLTO + DPLL Timeout + 10 + 1 + + + DPLLLDRTO + DPLL Ratio Ready + 11 + 1 + + + + + XOSCCTRL + External Multipurpose Crystal Oscillator (XOSC) Control + 0x10 + 16 + 0x0080 + + + ENABLE + Oscillator Enable + 1 + 1 + + + XTALEN + Crystal Oscillator Enable + 2 + 1 + + + CFDEN + Xosc Clock Failure Detector Enable + 3 + 1 + + + SWBEN + Xosc Clock Switch Enable + 4 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + GAIN + Oscillator Gain + 8 + 3 + + GAINSelect + + GAIN2 + 2 MHz + 0 + + + GAIN4 + 4 MHz + 1 + + + GAIN8 + 8 MHz + 2 + + + GAIN16 + 16 MHz + 3 + + + GAIN30 + 30 MHz + 4 + + + + + AMPGC + Automatic Amplitude Gain Control + 11 + 1 + + + STARTUP + Start-Up Time + 12 + 4 + + STARTUPSelect + + CYCLE1 + 31 us + 0 + + + CYCLE2 + 61 us + 1 + + + CYCLE4 + 122 us + 2 + + + CYCLE8 + 244 us + 3 + + + CYCLE16 + 488 us + 4 + + + CYCLE32 + 977 us + 5 + + + CYCLE64 + 1953 us + 6 + + + CYCLE128 + 3906 us + 7 + + + CYCLE256 + 7813 us + 8 + + + CYCLE512 + 15625 us + 9 + + + CYCLE1024 + 31250 us + 10 + + + CYCLE2048 + 62500 us + 11 + + + CYCLE4096 + 125000 us + 12 + + + CYCLE8192 + 250000 us + 13 + + + CYCLE16384 + 500000 us + 14 + + + CYCLE32768 + 1000000 us + 15 + + + + + + + CFDPRESC + Clock Failure Detector Prescaler + 0x12 + 8 + 0x00 + + + CFDPRESC + Clock Failure Detector Prescaler + 0 + 3 + + CFDPRESCSelect + + DIV1 + 48 MHz + 0 + + + DIV2 + 24 MHz + 1 + + + DIV4 + 12 MHz + 2 + + + DIV8 + 6 MHz + 3 + + + DIV16 + 3 MHz + 4 + + + DIV32 + 1.5 MHz + 5 + + + DIV64 + 0.75 MHz + 6 + + + DIV128 + 0.3125 MHz + 7 + + + + + + + EVCTRL + Event Control + 0x13 + 8 + 0x00 + + + CFDEO + Clock Failure Detector Event Output Enable + 0 + 1 + + + + + OSC48MCTRL + 48MHz Internal Oscillator (OSC48M) Control + 0x14 + 8 + 0x82 + + + ENABLE + Oscillator Enable + 1 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + + + OSC48MDIV + OSC48M Divider + 0x15 + 8 + 0x0B + + + DIV + OSC48M Division Factor + 0 + 4 + + DIVSelect + + DIV1 + 48 MHz + 0 + + + DIV2 + 24 MHz + 1 + + + DIV3 + 16 MHz + 2 + + + DIV4 + 12 MHz + 3 + + + DIV5 + 9.6 MHz + 4 + + + DIV6 + 8 MHz + 5 + + + DIV7 + 6.86 MHz + 6 + + + DIV8 + 6 MHz + 7 + + + DIV9 + 5.33 MHz + 8 + + + DIV10 + 4.8 MHz + 9 + + + DIV11 + 4.36 MHz + 10 + + + DIV12 + 4 MHz + 11 + + + DIV13 + 3.69 MHz + 12 + + + DIV14 + 3.43 MHz + 13 + + + DIV15 + 3.2 MHz + 14 + + + DIV16 + 3 MHz + 15 + + + + + + + OSC48MSTUP + OSC48M Startup Time + 0x16 + 8 + 0x07 + + + STARTUP + Startup Time + 0 + 3 + + STARTUPSelect + + CYCLE8 + 166 ns + 0 + + + CYCLE16 + 333 ns + 1 + + + CYCLE32 + 667 ns + 2 + + + CYCLE64 + 1.333 us + 3 + + + CYCLE128 + 2.667 us + 4 + + + CYCLE256 + 5.333 us + 5 + + + CYCLE512 + 10.667 us + 6 + + + CYCLE1024 + 21.333 us + 7 + + + + + + + OSC48MSYNCBUSY + OSC48M Synchronization Busy + 0x18 + 32 + read-only + 0x00000000 + + + OSC48MDIV + OSC48MDIV Synchronization Status + 2 + 1 + + + + + DPLLCTRLA + DPLL Control + 0x1C + 8 + 0x80 + + + ENABLE + Enable + 1 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand + 7 + 1 + + + + + DPLLRATIO + DPLL Ratio Control + 0x20 + 32 + 0x00000000 + + + LDR + Loop Divider Ratio + 0 + 12 + + + LDRFRAC + Loop Divider Ratio Fractional Part + 16 + 4 + + + + + DPLLCTRLB + Digital Core Configuration + 0x24 + 32 + 0x00000000 + + + FILTER + Proportional Integral Filter Selection + 0 + 2 + + FILTERSelect + + DEFAULT + Default filter mode + 0 + + + LBFILT + Low bandwidth filter + 1 + + + HBFILT + High bandwidth filter + 2 + + + HDFILT + High damping filter + 3 + + + + + LPEN + Low-Power Enable + 2 + 1 + + + WUF + Wake Up Fast + 3 + 1 + + + REFCLK + Reference Clock Selection + 4 + 2 + + REFCLKSelect + + XOSC32K + XOSC32K clock reference + 0 + + + XOSC + XOSC clock reference + 1 + + + GCLK + GCLK clock reference + 2 + + + + + LTIME + Lock Time + 8 + 3 + + LTIMESelect + + DEFAULT + No time-out. Automatic lock. + 0 + + + 8MS + Time-out if no lock within 8ms + 4 + + + 9MS + Time-out if no lock within 9ms + 5 + + + 10MS + Time-out if no lock within 10ms + 6 + + + 11MS + Time-out if no lock within 11ms + 7 + + + + + LBYPASS + Lock Bypass + 12 + 1 + + + DIV + Clock Divider + 16 + 11 + + + + + DPLLPRESC + DPLL Prescaler + 0x28 + 8 + 0x00 + + + PRESC + Output Clock Prescaler + 0 + 2 + + PRESCSelect + + DIV1 + DPLL output is divided by 1 + 0 + + + DIV2 + DPLL output is divided by 2 + 1 + + + DIV4 + DPLL output is divided by 4 + 2 + + + + + + + DPLLSYNCBUSY + DPLL Synchronization Busy + 0x2C + 8 + read-only + 0x00 + + + ENABLE + DPLL Enable Synchronization Status + 1 + 1 + + + DPLLRATIO + DPLL Ratio Synchronization Status + 2 + 1 + + + DPLLPRESC + DPLL Prescaler Synchronization Status + 3 + 1 + + + + + DPLLSTATUS + DPLL Status + 0x30 + 8 + read-only + 0x00 + + + LOCK + DPLL Lock Status + 0 + 1 + + + CLKRDY + DPLL Clock Ready + 1 + 1 + + + + + CAL48M + 48MHz Oscillator Calibration + 0x38 + 32 + 0x00000000 + + + FCAL + Frequency Calibration (48MHz) + 0 + 6 + + + FRANGE + Frequency Range (48MHz) + 8 + 2 + + + TCAL + Temperature Calibration (48MHz) + 16 + 6 + + + + + + + OSC32KCTRL + U22462.1.0 + 32k Oscillators Control + OSC32KCTRL + OSC32KCTRL_ + 0x40001400 + + 0 + 0x20 + registers + + + + INTENCLR + Interrupt Enable Clear + 0x0 + 32 + 0x00000000 + + + XOSC32KRDY + XOSC32K Ready Interrupt Enable + 0 + 1 + + + OSC32KRDY + OSC32K Ready Interrupt Enable + 1 + 1 + + + CLKFAIL + XOSC32K Clock Failure Detector Interrupt Enable + 2 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x4 + 32 + 0x00000000 + + + XOSC32KRDY + XOSC32K Ready Interrupt Enable + 0 + 1 + + + OSC32KRDY + OSC32K Ready Interrupt Enable + 1 + 1 + + + CLKFAIL + XOSC32K Clock Failure Detector Interrupt Enable + 2 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x8 + 32 + 0x00000000 + + + XOSC32KRDY + XOSC32K Ready + 0 + 1 + + + OSC32KRDY + OSC32K Ready + 1 + 1 + + + CLKFAIL + XOSC32K Clock Failure Detector + 2 + 1 + + + + + STATUS + Power and Clocks Status + 0xC + 32 + read-only + 0x00000000 + + + XOSC32KRDY + XOSC32K Ready + 0 + 1 + + + OSC32KRDY + OSC32K Ready + 1 + 1 + + + CLKFAIL + XOSC32K Clock Failure Detector + 2 + 1 + + + CLKSW + XOSC32K Clock switch + 3 + 1 + + + + + RTCCTRL + Clock selection + 0x10 + 32 + 0x00000000 + + + RTCSEL + RTC Clock Selection + 0 + 3 + + RTCSELSelect + + ULP1K + 1.024kHz from 32kHz internal ULP oscillator + 0 + + + ULP32K + 32.768kHz from 32kHz internal ULP oscillator + 1 + + + OSC1K + 1.024kHz from 32.768kHz internal oscillator + 2 + + + OSC32K + 32.768kHz from 32.768kHz internal oscillator + 3 + + + XOSC1K + 1.024kHz from 32.768kHz internal oscillator + 4 + + + XOSC32K + 32.768kHz from 32.768kHz external crystal oscillator + 5 + + + + + + + XOSC32K + 32kHz External Crystal Oscillator (XOSC32K) Control + 0x14 + 16 + 0x0080 + + + ENABLE + Oscillator Enable + 1 + 1 + + + XTALEN + Crystal Oscillator Enable + 2 + 1 + + + EN32K + 32kHz Output Enable + 3 + 1 + + + EN1K + 1kHz Output Enable + 4 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + STARTUP + Oscillator Start-Up Time + 8 + 3 + + STARTUPSelect + + CYCLE1 + 0.122 ms + 0 + + + CYCLE32 + 1.068 ms + 1 + + + CYCLE2048 + 62.6 ms + 2 + + + CYCLE4096 + 125 ms + 3 + + + CYCLE16384 + 500 ms + 4 + + + CYCLE32768 + 1000 ms + 5 + + + CYCLE65536 + 2000 ms + 6 + + + CYCLE131072 + 4000 ms + 7 + + + + + WRTLOCK + Write Lock + 12 + 1 + + + + + CFDCTRL + Clock Failure Detector Control + 0x16 + 8 + 0x00 + + + CFDEN + Clock Failure Detector Enable + 0 + 1 + + + SWBACK + Clock Switch Back + 1 + 1 + + + CFDPRESC + Clock Failure Detector Prescaler + 2 + 1 + + + + + EVCTRL + Event Control + 0x17 + 8 + 0x00 + + + CFDEO + Clock Failure Detector Event Output Enable + 0 + 1 + + + + + OSC32K + 32kHz Internal Oscillator (OSC32K) Control + 0x18 + 32 + 0x003F0080 + + + ENABLE + Oscillator Enable + 1 + 1 + + + EN32K + 32kHz Output Enable + 2 + 1 + + + EN1K + 1kHz Output Enable + 3 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + STARTUP + Oscillator Start-Up Time + 8 + 3 + + STARTUPSelect + + CYCLE3 + 0.092 ms + 0 + + + CYCLE4 + 0.122 ms + 1 + + + CYCLE6 + 0.183 ms + 2 + + + CYCLE10 + 0.305 ms + 3 + + + CYCLE18 + 0.549 ms + 4 + + + CYCLE34 + 1.038 ms + 5 + + + CYCLE66 + 2.014 ms + 6 + + + CYCLE130 + 3.967 ms + 7 + + + + + WRTLOCK + Write Lock + 12 + 1 + + + CALIB + Oscillator Calibration + 16 + 7 + + + + + OSCULP32K + 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control + 0x1C + 32 + + + CALIB + Oscillator Calibration + 8 + 5 + + + WRTLOCK + Write Lock + 15 + 1 + + + + + + + PAC + U21201.1.0 + Peripheral Access Controller + PAC + PAC_ + 0x40000000 + + 0 + 0x40 + registers + + + + WRCTRL + Write control + 0x0 + 32 + 0x00000000 + + + PERID + Peripheral identifier + 0 + 16 + + + KEY + Peripheral access control key + 16 + 8 + + KEYSelect + + OFF + No action + 0 + + + CLR + Clear protection + 1 + + + SET + Set protection + 2 + + + SETLCK + Set and lock protection + 3 + + + + + + + EVCTRL + Event control + 0x4 + 8 + 0x00 + + + ERREO + Peripheral acess error event output + 0 + 1 + + + + + INTENCLR + Interrupt enable clear + 0x8 + 8 + 0x00 + + + ERR + Peripheral access error interrupt disable + 0 + 1 + + + + + INTENSET + Interrupt enable set + 0x9 + 8 + 0x00 + + + ERR + Peripheral access error interrupt enable + 0 + 1 + + + + + INTFLAGAHB + Bridge interrupt flag status + 0x10 + 32 + 0x00000000 + + + FLASH_ + FLASH + 0 + 1 + + + HSRAMCM0P_ + HSRAMCM0P + 1 + 1 + + + HSRAMDSU_ + HSRAMDSU + 2 + 1 + + + HPB1_ + HPB1 + 3 + 1 + + + HPB0_ + HPB0 + 4 + 1 + + + HPB2_ + HPB2 + 5 + 1 + + + LPRAMDMAC_ + LPRAMDMAC + 6 + 1 + + + DIVAS_ + DIVAS + 7 + 1 + + + + + INTFLAGA + Peripheral interrupt flag status - Bridge A + 0x14 + 32 + 0x00000000 + + + PAC_ + PAC + 0 + 1 + + + PM_ + PM + 1 + 1 + + + MCLK_ + MCLK + 2 + 1 + + + RSTC_ + RSTC + 3 + 1 + + + OSCCTRL_ + OSCCTRL + 4 + 1 + + + OSC32KCTRL_ + OSC32KCTRL + 5 + 1 + + + SUPC_ + SUPC + 6 + 1 + + + GCLK_ + GCLK + 7 + 1 + + + WDT_ + WDT + 8 + 1 + + + RTC_ + RTC + 9 + 1 + + + EIC_ + EIC + 10 + 1 + + + FREQM_ + FREQM + 11 + 1 + + + TSENS_ + TSENS + 12 + 1 + + + + + INTFLAGB + Peripheral interrupt flag status - Bridge B + 0x18 + 32 + 0x00000000 + + + PORT_ + PORT + 0 + 1 + + + DSU_ + DSU + 1 + 1 + + + NVMCTRL_ + NVMCTRL + 2 + 1 + + + DMAC_ + DMAC + 3 + 1 + + + MTB_ + MTB + 4 + 1 + + + HMATRIXHS_ + HMATRIXHS + 5 + 1 + + + + + INTFLAGC + Peripheral interrupt flag status - Bridge C + 0x1C + 32 + 0x00000000 + + + EVSYS_ + EVSYS + 0 + 1 + + + SERCOM0_ + SERCOM0 + 1 + 1 + + + SERCOM1_ + SERCOM1 + 2 + 1 + + + SERCOM2_ + SERCOM2 + 3 + 1 + + + SERCOM3_ + SERCOM3 + 4 + 1 + + + SERCOM4_ + SERCOM4 + 5 + 1 + + + SERCOM5_ + SERCOM5 + 6 + 1 + + + CAN0_ + CAN0 + 7 + 1 + + + CAN1_ + CAN1 + 8 + 1 + + + TCC0_ + TCC0 + 9 + 1 + + + TCC1_ + TCC1 + 10 + 1 + + + TCC2_ + TCC2 + 11 + 1 + + + TC0_ + TC0 + 12 + 1 + + + TC1_ + TC1 + 13 + 1 + + + TC2_ + TC2 + 14 + 1 + + + TC3_ + TC3 + 15 + 1 + + + TC4_ + TC4 + 16 + 1 + + + ADC0_ + ADC0 + 17 + 1 + + + ADC1_ + ADC1 + 18 + 1 + + + SDADC_ + SDADC + 19 + 1 + + + AC_ + AC + 20 + 1 + + + DAC_ + DAC + 21 + 1 + + + PTC_ + PTC + 22 + 1 + + + CCL_ + CCL + 23 + 1 + + + + + STATUSA + Peripheral write protection status - Bridge A + 0x34 + 32 + read-only + 0x00000000 + + + PAC_ + PAC APB Protect Enable + 0 + 1 + + + PM_ + PM APB Protect Enable + 1 + 1 + + + MCLK_ + MCLK APB Protect Enable + 2 + 1 + + + RSTC_ + RSTC APB Protect Enable + 3 + 1 + + + OSCCTRL_ + OSCCTRL APB Protect Enable + 4 + 1 + + + OSC32KCTRL_ + OSC32KCTRL APB Protect Enable + 5 + 1 + + + SUPC_ + SUPC APB Protect Enable + 6 + 1 + + + GCLK_ + GCLK APB Protect Enable + 7 + 1 + + + WDT_ + WDT APB Protect Enable + 8 + 1 + + + RTC_ + RTC APB Protect Enable + 9 + 1 + + + EIC_ + EIC APB Protect Enable + 10 + 1 + + + FREQM_ + FREQM APB Protect Enable + 11 + 1 + + + TSENS_ + TSENS APB Protect Enable + 12 + 1 + + + + + STATUSB + Peripheral write protection status - Bridge B + 0x38 + 32 + read-only + 0x00000002 + + + PORT_ + PORT APB Protect Enable + 0 + 1 + + + DSU_ + DSU APB Protect Enable + 1 + 1 + + + NVMCTRL_ + NVMCTRL APB Protect Enable + 2 + 1 + + + DMAC_ + DMAC APB Protect Enable + 3 + 1 + + + MTB_ + MTB APB Protect Enable + 4 + 1 + + + HMATRIXHS_ + HMATRIXHS APB Protect Enable + 5 + 1 + + + + + STATUSC + Peripheral write protection status - Bridge C + 0x3C + 32 + read-only + 0x02000000 + + + EVSYS_ + EVSYS APB Protect Enable + 0 + 1 + + + SERCOM0_ + SERCOM0 APB Protect Enable + 1 + 1 + + + SERCOM1_ + SERCOM1 APB Protect Enable + 2 + 1 + + + SERCOM2_ + SERCOM2 APB Protect Enable + 3 + 1 + + + SERCOM3_ + SERCOM3 APB Protect Enable + 4 + 1 + + + SERCOM4_ + SERCOM4 APB Protect Enable + 5 + 1 + + + SERCOM5_ + SERCOM5 APB Protect Enable + 6 + 1 + + + CAN0_ + CAN0 APB Protect Enable + 7 + 1 + + + CAN1_ + CAN1 APB Protect Enable + 8 + 1 + + + TCC0_ + TCC0 APB Protect Enable + 9 + 1 + + + TCC1_ + TCC1 APB Protect Enable + 10 + 1 + + + TCC2_ + TCC2 APB Protect Enable + 11 + 1 + + + TC0_ + TC0 APB Protect Enable + 12 + 1 + + + TC1_ + TC1 APB Protect Enable + 13 + 1 + + + TC2_ + TC2 APB Protect Enable + 14 + 1 + + + TC3_ + TC3 APB Protect Enable + 15 + 1 + + + TC4_ + TC4 APB Protect Enable + 16 + 1 + + + ADC0_ + ADC0 APB Protect Enable + 17 + 1 + + + ADC1_ + ADC1 APB Protect Enable + 18 + 1 + + + SDADC_ + SDADC APB Protect Enable + 19 + 1 + + + AC_ + AC APB Protect Enable + 20 + 1 + + + DAC_ + DAC APB Protect Enable + 21 + 1 + + + PTC_ + PTC APB Protect Enable + 22 + 1 + + + CCL_ + CCL APB Protect Enable + 23 + 1 + + + + + + + PM + U22402.1.0 + Power Manager + PM + PM_ + 0x40000400 + + 0 + 0xA + registers + + + + SLEEPCFG + Sleep Configuration + 0x1 + 8 + 0x00 + + + SLEEPMODE + Sleep Mode + 0 + 3 + + SLEEPMODESelect + + IDLE0 + CPU clock is OFF + 0 + + + IDLE1 + AHB clock is OFF + 1 + + + IDLE2 + APB clock are OFF + 2 + + + STANDBY + All Clocks are OFF + 4 + + + + + + + STDBYCFG + Standby Configuration + 0x8 + 16 + 0x0400 + + + VREGSMOD + Voltage Regulator Standby mode + 6 + 2 + + VREGSMODSelect + + AUTO + Automatic mode + 0 + + + PERFORMANCE + Performance oriented + 1 + + + LP + Low Power oriented + 2 + + + + + BBIASHS + Back Bias for HMCRAMCHS + 10 + 1 + + + + + + + PORT + U22102.1.1 + Port Module + PORT + PORT_ + 0x41000000 + + 0 + 0x100 + registers + + + + 2 + 0x80 + GROUP[%s] + + 0x00 + + DIR + Data Direction + 0x0 + 32 + 0x00000000 + + + DIRCLR + Data Direction Clear + 0x4 + 32 + 0x00000000 + + + DIRSET + Data Direction Set + 0x8 + 32 + 0x00000000 + + + DIRTGL + Data Direction Toggle + 0xC + 32 + 0x00000000 + + + OUT + Data Output Value + 0x10 + 32 + 0x00000000 + + + OUTCLR + Data Output Value Clear + 0x14 + 32 + 0x00000000 + + + OUTSET + Data Output Value Set + 0x18 + 32 + 0x00000000 + + + OUTTGL + Data Output Value Toggle + 0x1C + 32 + 0x00000000 + + + IN + Data Input Value + 0x20 + 32 + read-only + 0x00000000 + + + CTRL + Control + 0x24 + 32 + 0x00000000 + + + SAMPLING + Input Sampling Mode + 0 + 32 + + + + + WRCONFIG + Write Configuration + 0x28 + 32 + write-only + 0x00000000 + + + PINMASK + Pin Mask for Multiple Pin Configuration + 0 + 16 + + + PMUXEN + Select Peripheral Multiplexer + 16 + 1 + + + INEN + Input Enable + 17 + 1 + + + PULLEN + Pull Enable + 18 + 1 + + + DRVSTR + Output Driver Strength Selection + 22 + 1 + + + PMUX + Peripheral Multiplexing Template + 24 + 4 + + + WRPMUX + Write PMUX Registers + 28 + 1 + + + WRPINCFG + Write PINCFG Registers + 30 + 1 + + + HWSEL + Half-Word Select + 31 + 1 + + + + + EVCTRL + Event Input Control + 0x2C + 32 + 0x00000000 + + + PID0 + Port Event Pin Identifier 0 + 0 + 5 + + + EVACT0 + Port Event Action 0 + 5 + 2 + + EVACT0Select + + OUT + Event output to pin + 0x0 + + + SET + Set output register of pin on event + 0x1 + + + CLR + Clear output register of pin on event + 0x2 + + + TGL + Toggle output register of pin on event + 0x3 + + + + + PORTEI0 + Port Event Enable Input 0 + 7 + 1 + + + PID1 + Port Event Pin Identifier 1 + 8 + 5 + + + EVACT1 + Port Event Action 1 + 13 + 2 + + + PORTEI1 + Port Event Enable Input 1 + 15 + 1 + + + PID2 + Port Event Pin Identifier 2 + 16 + 5 + + + EVACT2 + Port Event Action 2 + 21 + 2 + + + PORTEI2 + Port Event Enable Input 2 + 23 + 1 + + + PID3 + Port Event Pin Identifier 3 + 24 + 5 + + + EVACT3 + Port Event Action 3 + 29 + 2 + + + PORTEI3 + Port Event Enable Input 3 + 31 + 1 + + + + + 16 + 1 + PMUX[%s] + Peripheral Multiplexing n + 0x30 + 8 + 0x00 + + + PMUXE + Peripheral Multiplexing for Even-Numbered Pin + 0 + 4 + + + PMUXO + Peripheral Multiplexing for Odd-Numbered Pin + 4 + 4 + + + + + 32 + 1 + PINCFG[%s] + Pin Configuration n + 0x40 + 8 + 0x00 + + + PMUXEN + Select Peripheral Multiplexer + 0 + 1 + + + INEN + Input Enable + 1 + 1 + + + PULLEN + Pull Enable + 2 + 1 + + + DRVSTR + Output Driver Strength Selection + 6 + 1 + + + + + + + + PORT_IOBUS + PORT_IOBUS_ + 0x60000000 + + + PTC + U22153.1.0 + Peripheral Touch Controller + PTC + PTC_ + 0x42005800 + + 0 + 0x1 + reserved + + + PTC + 30 + + + + RSTC + U22392.0.2 + Reset Controller + RSTC + RSTC_ + 0x40000C00 + + 0 + 0x1 + registers + + + + RCAUSE + Reset Cause + 0x0 + 8 + read-only + + + POR + Power On Reset + 0 + 1 + + + BODCORE + Brown Out CORE Detector Reset + 1 + 1 + + + BODVDD + Brown Out VDD Detector Reset + 2 + 1 + + + EXT + External Reset + 4 + 1 + + + WDT + Watchdog Reset + 5 + 1 + + + SYST + System Reset Request + 6 + 1 + + + + + + + RTC + U22501.1.1 + Real-Time Counter + RTC + RTC_ + 0x40002400 + + 0 + 0x25 + registers + + + RTC + 2 + + + + MODE0 + 32-bit Counter with Single 32-bit Compare + RtcMode0 + 0x0 + + CTRLA + MODE0 Control A + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 2 + + MODESelect + + COUNT32 + Mode 0: 32-bit Counter + 0x0 + + + COUNT16 + Mode 1: 16-bit Counter + 0x1 + + + CLOCK + Mode 2: Clock/Calendar + 0x2 + + + + + MATCHCLR + Clear on Match + 7 + 1 + + + PRESCALER + Prescaler + 8 + 4 + + PRESCALERSelect + + OFF + CLK_RTC_CNT = GCLK_RTC/1 + 0x0 + + + DIV1 + CLK_RTC_CNT = GCLK_RTC/1 + 0x1 + + + DIV2 + CLK_RTC_CNT = GCLK_RTC/2 + 0x2 + + + DIV4 + CLK_RTC_CNT = GCLK_RTC/4 + 0x3 + + + DIV8 + CLK_RTC_CNT = GCLK_RTC/8 + 0x4 + + + DIV16 + CLK_RTC_CNT = GCLK_RTC/16 + 0x5 + + + DIV32 + CLK_RTC_CNT = GCLK_RTC/32 + 0x6 + + + DIV64 + CLK_RTC_CNT = GCLK_RTC/64 + 0x7 + + + DIV128 + CLK_RTC_CNT = GCLK_RTC/128 + 0x8 + + + DIV256 + CLK_RTC_CNT = GCLK_RTC/256 + 0x9 + + + DIV512 + CLK_RTC_CNT = GCLK_RTC/512 + 0xA + + + DIV1024 + CLK_RTC_CNT = GCLK_RTC/1024 + 0xB + + + + + COUNTSYNC + Count Read Synchronization Enable + 15 + 1 + + + + + EVCTRL + MODE0 Event Control + 0x4 + 32 + 0x00000000 + + + PEREO0 + Periodic Interval 0 Event Output Enable + 0 + 1 + + + PEREO1 + Periodic Interval 1 Event Output Enable + 1 + 1 + + + PEREO2 + Periodic Interval 2 Event Output Enable + 2 + 1 + + + PEREO3 + Periodic Interval 3 Event Output Enable + 3 + 1 + + + PEREO4 + Periodic Interval 4 Event Output Enable + 4 + 1 + + + PEREO5 + Periodic Interval 5 Event Output Enable + 5 + 1 + + + PEREO6 + Periodic Interval 6 Event Output Enable + 6 + 1 + + + PEREO7 + Periodic Interval 7 Event Output Enable + 7 + 1 + + + CMPEO0 + Compare 0 Event Output Enable + 8 + 1 + + + OVFEO + Overflow Event Output Enable + 15 + 1 + + + + + INTENCLR + MODE0 Interrupt Enable Clear + 0x8 + 16 + 0x0000 + + + PER0 + Periodic Interval 0 Interrupt Enable + 0 + 1 + + + PER1 + Periodic Interval 1 Interrupt Enable + 1 + 1 + + + PER2 + Periodic Interval 2 Interrupt Enable + 2 + 1 + + + PER3 + Periodic Interval 3 Interrupt Enable + 3 + 1 + + + PER4 + Periodic Interval 4 Interrupt Enable + 4 + 1 + + + PER5 + Periodic Interval 5 Interrupt Enable + 5 + 1 + + + PER6 + Periodic Interval 6 Interrupt Enable + 6 + 1 + + + PER7 + Periodic Interval 7 Interrupt Enable + 7 + 1 + + + CMP0 + Compare 0 Interrupt Enable + 8 + 1 + + + OVF + Overflow Interrupt Enable + 15 + 1 + + + + + INTENSET + MODE0 Interrupt Enable Set + 0xA + 16 + 0x0000 + + + PER0 + Periodic Interval 0 Interrupt Enable + 0 + 1 + + + PER1 + Periodic Interval 1 Interrupt Enable + 1 + 1 + + + PER2 + Periodic Interval 2 Interrupt Enable + 2 + 1 + + + PER3 + Periodic Interval 3 Interrupt Enable + 3 + 1 + + + PER4 + Periodic Interval 4 Interrupt Enable + 4 + 1 + + + PER5 + Periodic Interval 5 Interrupt Enable + 5 + 1 + + + PER6 + Periodic Interval 6 Interrupt Enable + 6 + 1 + + + PER7 + Periodic Interval 7 Interrupt Enable + 7 + 1 + + + CMP0 + Compare 0 Interrupt Enable + 8 + 1 + + + OVF + Overflow Interrupt Enable + 15 + 1 + + + + + INTFLAG + MODE0 Interrupt Flag Status and Clear + 0xC + 16 + 0x0000 + + + PER0 + Periodic Interval 0 + 0 + 1 + + + PER1 + Periodic Interval 1 + 1 + 1 + + + PER2 + Periodic Interval 2 + 2 + 1 + + + PER3 + Periodic Interval 3 + 3 + 1 + + + PER4 + Periodic Interval 4 + 4 + 1 + + + PER5 + Periodic Interval 5 + 5 + 1 + + + PER6 + Periodic Interval 6 + 6 + 1 + + + PER7 + Periodic Interval 7 + 7 + 1 + + + CMP0 + Compare 0 + 8 + 1 + + + OVF + Overflow + 15 + 1 + + + + + DBGCTRL + Debug Control + 0xE + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + SYNCBUSY + MODE0 Synchronization Busy Status + 0x10 + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Busy + 0 + 1 + + + ENABLE + Enable Bit Busy + 1 + 1 + + + FREQCORR + FREQCORR Register Busy + 2 + 1 + + + COUNT + COUNT Register Busy + 3 + 1 + + + COMP0 + COMP 0 Register Busy + 5 + 1 + + + COUNTSYNC + Count Read Synchronization Enable Bit Busy + 15 + 1 + + + + + FREQCORR + Frequency Correction + 0x14 + 8 + 0x00 + + + VALUE + Correction Value + 0 + 7 + + + SIGN + Correction Sign + 7 + 1 + + + + + COUNT + MODE0 Counter Value + 0x18 + 32 + 0x00000000 + + + COUNT + Counter Value + 0 + 32 + + + + + COMP + MODE0 Compare n Value + 0x20 + 32 + 0x00000000 + + + COMP + Compare Value + 0 + 32 + + + + + + MODE1 + 16-bit Counter with Two 16-bit Compares + MODE0 + RtcMode1 + 0x0 + + CTRLA + MODE1 Control A + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 2 + + MODESelect + + COUNT32 + Mode 0: 32-bit Counter + 0 + + + COUNT16 + Mode 1: 16-bit Counter + 1 + + + CLOCK + Mode 2: Clock/Calendar + 2 + + + + + PRESCALER + Prescaler + 8 + 4 + + PRESCALERSelect + + OFF + CLK_RTC_CNT = GCLK_RTC/1 + 0 + + + DIV1 + CLK_RTC_CNT = GCLK_RTC/1 + 1 + + + DIV2 + CLK_RTC_CNT = GCLK_RTC/2 + 2 + + + DIV4 + CLK_RTC_CNT = GCLK_RTC/4 + 3 + + + DIV8 + CLK_RTC_CNT = GCLK_RTC/8 + 4 + + + DIV16 + CLK_RTC_CNT = GCLK_RTC/16 + 5 + + + DIV32 + CLK_RTC_CNT = GCLK_RTC/32 + 6 + + + DIV64 + CLK_RTC_CNT = GCLK_RTC/64 + 7 + + + DIV128 + CLK_RTC_CNT = GCLK_RTC/128 + 8 + + + DIV256 + CLK_RTC_CNT = GCLK_RTC/256 + 9 + + + DIV512 + CLK_RTC_CNT = GCLK_RTC/512 + 0xA + + + DIV1024 + CLK_RTC_CNT = GCLK_RTC/1024 + 0xB + + + + + COUNTSYNC + Count Read Synchronization Enable + 15 + 1 + + + + + EVCTRL + MODE1 Event Control + 0x4 + 32 + 0x00000000 + + + PEREO0 + Periodic Interval 0 Event Output Enable + 0 + 1 + + + PEREO1 + Periodic Interval 1 Event Output Enable + 1 + 1 + + + PEREO2 + Periodic Interval 2 Event Output Enable + 2 + 1 + + + PEREO3 + Periodic Interval 3 Event Output Enable + 3 + 1 + + + PEREO4 + Periodic Interval 4 Event Output Enable + 4 + 1 + + + PEREO5 + Periodic Interval 5 Event Output Enable + 5 + 1 + + + PEREO6 + Periodic Interval 6 Event Output Enable + 6 + 1 + + + PEREO7 + Periodic Interval 7 Event Output Enable + 7 + 1 + + + CMPEO0 + Compare 0 Event Output Enable + 8 + 1 + + + CMPEO1 + Compare 1 Event Output Enable + 9 + 1 + + + OVFEO + Overflow Event Output Enable + 15 + 1 + + + + + INTENCLR + MODE1 Interrupt Enable Clear + 0x8 + 16 + 0x0000 + + + PER0 + Periodic Interval 0 Interrupt Enable + 0 + 1 + + + PER1 + Periodic Interval 1 Interrupt Enable + 1 + 1 + + + PER2 + Periodic Interval 2 Interrupt Enable + 2 + 1 + + + PER3 + Periodic Interval 3 Interrupt Enable + 3 + 1 + + + PER4 + Periodic Interval 4 Interrupt Enable + 4 + 1 + + + PER5 + Periodic Interval 5 Interrupt Enable + 5 + 1 + + + PER6 + Periodic Interval 6 Interrupt Enable + 6 + 1 + + + PER7 + Periodic Interval 7 Interrupt Enable + 7 + 1 + + + CMP0 + Compare 0 Interrupt Enable + 8 + 1 + + + CMP1 + Compare 1 Interrupt Enable + 9 + 1 + + + OVF + Overflow Interrupt Enable + 15 + 1 + + + + + INTENSET + MODE1 Interrupt Enable Set + 0xA + 16 + 0x0000 + + + PER0 + Periodic Interval 0 Interrupt Enable + 0 + 1 + + + PER1 + Periodic Interval 1 Interrupt Enable + 1 + 1 + + + PER2 + Periodic Interval 2 Interrupt Enable + 2 + 1 + + + PER3 + Periodic Interval 3 Interrupt Enable + 3 + 1 + + + PER4 + Periodic Interval 4 Interrupt Enable + 4 + 1 + + + PER5 + Periodic Interval 5 Interrupt Enable + 5 + 1 + + + PER6 + Periodic Interval 6 Interrupt Enable + 6 + 1 + + + PER7 + Periodic Interval 7 Interrupt Enable + 7 + 1 + + + CMP0 + Compare 0 Interrupt Enable + 8 + 1 + + + CMP1 + Compare 1 Interrupt Enable + 9 + 1 + + + OVF + Overflow Interrupt Enable + 15 + 1 + + + + + INTFLAG + MODE1 Interrupt Flag Status and Clear + 0xC + 16 + 0x0000 + + + PER0 + Periodic Interval 0 + 0 + 1 + + + PER1 + Periodic Interval 1 + 1 + 1 + + + PER2 + Periodic Interval 2 + 2 + 1 + + + PER3 + Periodic Interval 3 + 3 + 1 + + + PER4 + Periodic Interval 4 + 4 + 1 + + + PER5 + Periodic Interval 5 + 5 + 1 + + + PER6 + Periodic Interval 6 + 6 + 1 + + + PER7 + Periodic Interval 7 + 7 + 1 + + + CMP0 + Compare 0 + 8 + 1 + + + CMP1 + Compare 1 + 9 + 1 + + + OVF + Overflow + 15 + 1 + + + + + DBGCTRL + Debug Control + 0xE + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + SYNCBUSY + MODE1 Synchronization Busy Status + 0x10 + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Bit Busy + 0 + 1 + + + ENABLE + Enable Bit Busy + 1 + 1 + + + FREQCORR + FREQCORR Register Busy + 2 + 1 + + + COUNT + COUNT Register Busy + 3 + 1 + + + PER + PER Register Busy + 4 + 1 + + + COMP0 + COMP 0 Register Busy + 5 + 1 + + + COMP1 + COMP 1 Register Busy + 6 + 1 + + + COUNTSYNC + Count Read Synchronization Enable Bit Busy + 15 + 1 + + + + + FREQCORR + Frequency Correction + 0x14 + 8 + 0x00 + + + VALUE + Correction Value + 0 + 7 + + + SIGN + Correction Sign + 7 + 1 + + + + + COUNT + MODE1 Counter Value + 0x18 + 16 + 0x0000 + + + COUNT + Counter Value + 0 + 16 + + + + + PER + MODE1 Counter Period + 0x1C + 16 + 0x0000 + + + PER + Counter Period + 0 + 16 + + + + + 2 + 2 + COMP[%s] + MODE1 Compare n Value + 0x20 + 16 + 0x0000 + + + COMP + Compare Value + 0 + 16 + + + + + + MODE2 + Clock/Calendar with Alarm + MODE0 + RtcMode2 + 0x0 + + CTRLA + MODE2 Control A + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 2 + + MODESelect + + COUNT32 + Mode 0: 32-bit Counter + 0 + + + COUNT16 + Mode 1: 16-bit Counter + 1 + + + CLOCK + Mode 2: Clock/Calendar + 2 + + + + + CLKREP + Clock Representation + 6 + 1 + + + MATCHCLR + Clear on Match + 7 + 1 + + + PRESCALER + Prescaler + 8 + 4 + + PRESCALERSelect + + OFF + CLK_RTC_CNT = GCLK_RTC/1 + 0x0 + + + DIV1 + CLK_RTC_CNT = GCLK_RTC/1 + 0x1 + + + DIV2 + CLK_RTC_CNT = GCLK_RTC/2 + 0x2 + + + DIV4 + CLK_RTC_CNT = GCLK_RTC/4 + 0x3 + + + DIV8 + CLK_RTC_CNT = GCLK_RTC/8 + 0x4 + + + DIV16 + CLK_RTC_CNT = GCLK_RTC/16 + 0x5 + + + DIV32 + CLK_RTC_CNT = GCLK_RTC/32 + 0x6 + + + DIV64 + CLK_RTC_CNT = GCLK_RTC/64 + 0x7 + + + DIV128 + CLK_RTC_CNT = GCLK_RTC/128 + 0x8 + + + DIV256 + CLK_RTC_CNT = GCLK_RTC/256 + 0x9 + + + DIV512 + CLK_RTC_CNT = GCLK_RTC/512 + 0xA + + + DIV1024 + CLK_RTC_CNT = GCLK_RTC/1024 + 0xB + + + + + CLOCKSYNC + Clock Read Synchronization Enable + 15 + 1 + + + + + EVCTRL + MODE2 Event Control + 0x4 + 32 + 0x00000000 + + + PEREO0 + Periodic Interval 0 Event Output Enable + 0 + 1 + + + PEREO1 + Periodic Interval 1 Event Output Enable + 1 + 1 + + + PEREO2 + Periodic Interval 2 Event Output Enable + 2 + 1 + + + PEREO3 + Periodic Interval 3 Event Output Enable + 3 + 1 + + + PEREO4 + Periodic Interval 4 Event Output Enable + 4 + 1 + + + PEREO5 + Periodic Interval 5 Event Output Enable + 5 + 1 + + + PEREO6 + Periodic Interval 6 Event Output Enable + 6 + 1 + + + PEREO7 + Periodic Interval 7 Event Output Enable + 7 + 1 + + + ALARMEO0 + Alarm 0 Event Output Enable + 8 + 1 + + + OVFEO + Overflow Event Output Enable + 15 + 1 + + + + + INTENCLR + MODE2 Interrupt Enable Clear + 0x8 + 16 + 0x0000 + + + PER0 + Periodic Interval 0 Interrupt Enable + 0 + 1 + + + PER1 + Periodic Interval 1 Interrupt Enable + 1 + 1 + + + PER2 + Periodic Interval 2 Interrupt Enable + 2 + 1 + + + PER3 + Periodic Interval 3 Interrupt Enable + 3 + 1 + + + PER4 + Periodic Interval 4 Interrupt Enable + 4 + 1 + + + PER5 + Periodic Interval 5 Interrupt Enable + 5 + 1 + + + PER6 + Periodic Interval 6 Interrupt Enable + 6 + 1 + + + PER7 + Periodic Interval 7 Interrupt Enable + 7 + 1 + + + ALARM0 + Alarm 0 Interrupt Enable + 8 + 1 + + + OVF + Overflow Interrupt Enable + 15 + 1 + + + + + INTENSET + MODE2 Interrupt Enable Set + 0xA + 16 + 0x0000 + + + PER0 + Periodic Interval 0 Enable + 0 + 1 + + + PER1 + Periodic Interval 1 Enable + 1 + 1 + + + PER2 + Periodic Interval 2 Enable + 2 + 1 + + + PER3 + Periodic Interval 3 Enable + 3 + 1 + + + PER4 + Periodic Interval 4 Enable + 4 + 1 + + + PER5 + Periodic Interval 5 Enable + 5 + 1 + + + PER6 + Periodic Interval 6 Enable + 6 + 1 + + + PER7 + Periodic Interval 7 Enable + 7 + 1 + + + ALARM0 + Alarm 0 Interrupt Enable + 8 + 1 + + + OVF + Overflow Interrupt Enable + 15 + 1 + + + + + INTFLAG + MODE2 Interrupt Flag Status and Clear + 0xC + 16 + 0x0000 + + + PER0 + Periodic Interval 0 + 0 + 1 + + + PER1 + Periodic Interval 1 + 1 + 1 + + + PER2 + Periodic Interval 2 + 2 + 1 + + + PER3 + Periodic Interval 3 + 3 + 1 + + + PER4 + Periodic Interval 4 + 4 + 1 + + + PER5 + Periodic Interval 5 + 5 + 1 + + + PER6 + Periodic Interval 6 + 6 + 1 + + + PER7 + Periodic Interval 7 + 7 + 1 + + + ALARM0 + Alarm 0 + 8 + 1 + + + OVF + Overflow + 15 + 1 + + + + + DBGCTRL + Debug Control + 0xE + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + SYNCBUSY + MODE2 Synchronization Busy Status + 0x10 + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Bit Busy + 0 + 1 + + + ENABLE + Enable Bit Busy + 1 + 1 + + + FREQCORR + FREQCORR Register Busy + 2 + 1 + + + CLOCK + CLOCK Register Busy + 3 + 1 + + + ALARM0 + ALARM 0 Register Busy + 5 + 1 + + + MASK0 + MASK 0 Register Busy + 11 + 1 + + + CLOCKSYNC + Clock Read Synchronization Enable Bit Busy + 15 + 1 + + + + + FREQCORR + Frequency Correction + 0x14 + 8 + 0x00 + + + VALUE + Correction Value + 0 + 7 + + + SIGN + Correction Sign + 7 + 1 + + + + + CLOCK + MODE2 Clock Value + 0x18 + 32 + 0x00000000 + + + SECOND + Second + 0 + 6 + + + MINUTE + Minute + 6 + 6 + + + HOUR + Hour + 12 + 5 + + HOURSelect + + AM + AM when CLKREP in 12-hour + 0x00 + + + PM + PM when CLKREP in 12-hour + 0x10 + + + + + DAY + Day + 17 + 5 + + + MONTH + Month + 22 + 4 + + + YEAR + Year + 26 + 6 + + + + + ALARM + MODE2_ALARM Alarm n Value + 0x20 + 32 + 0x00000000 + + + SECOND + Second + 0 + 6 + + + MINUTE + Minute + 6 + 6 + + + HOUR + Hour + 12 + 5 + + HOURSelect + + AM + Morning hour + 0x00 + + + PM + Afternoon hour + 0x10 + + + + + DAY + Day + 17 + 5 + + + MONTH + Month + 22 + 4 + + + YEAR + Year + 26 + 6 + + + + + MASK + MODE2_ALARM Alarm n Mask + 0x24 + 8 + 0x00 + + + SEL + Alarm Mask Selection + 0 + 3 + + SELSelect + + OFF + Alarm Disabled + 0x0 + + + SS + Match seconds only + 0x1 + + + MMSS + Match seconds and minutes only + 0x2 + + + HHMMSS + Match seconds, minutes, and hours only + 0x3 + + + DDHHMMSS + Match seconds, minutes, hours, and days only + 0x4 + + + MMDDHHMMSS + Match seconds, minutes, hours, days, and months only + 0x5 + + + YYMMDDHHMMSS + Match seconds, minutes, hours, days, months, and years + 0x6 + + + + + + + + + + SDADC + U22601.0.1 + Sigma-Delta Analog Digital Converter + SDADC + SDADC_ + 0x42004C00 + + 0 + 0x2F + registers + + + SDADC + 29 + + + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + RUNSTDBY + Run during Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + + + REFCTRL + Reference Control + 0x1 + 8 + 0x00 + + + REFSEL + Reference Selection + 0 + 2 + + REFSELSelect + + INTREF + Internal Bandgap Reference + 0 + + + AREFB + External Reference + 1 + + + DAC + Internal DAC Output + 2 + + + INTVCC + VDDANA + 3 + + + + + REFRANGE + Reference Range + 4 + 2 + + + ONREFBUF + Reference Buffer + 7 + 1 + + + + + CTRLB + Control B + 0x2 + 16 + 0x2000 + + + PRESCALER + Prescaler Configuration + 0 + 8 + + PRESCALERSelect + + DIV2 + Peripheral clock divided by 2 + 0x0 + + + DIV4 + Peripheral clock divided by 4 + 0x1 + + + DIV8 + Peripheral clock divided by 8 + 0x2 + + + DIV16 + Peripheral clock divided by 16 + 0x3 + + + DIV32 + Peripheral clock divided by 32 + 0x4 + + + DIV64 + Peripheral clock divided by 64 + 0x5 + + + DIV128 + Peripheral clock divided by 128 + 0x6 + + + DIV256 + Peripheral clock divided by 256 + 0x7 + + + + + OSR + Over Sampling Ratio + 8 + 3 + + OSRSelect + + OSR64 + Over Sampling Ratio is 64 + 0x0 + + + OSR128 + Over Sampling Ratio is 128 + 0x1 + + + OSR256 + Over Sampling Ratio is 256 + 0x2 + + + OSR512 + Over Sampling Ratio is 512 + 0x3 + + + OSR1024 + Over Sampling Ratio is 1024 + 0x4 + + + + + SKPCNT + Skip Sample Count + 12 + 4 + + + + + EVCTRL + Event Control + 0x4 + 8 + 0x00 + + + FLUSHEI + Flush Event Input Enable + 0 + 1 + + + STARTEI + Start Conversion Event Input Enable + 1 + 1 + + + FLUSHINV + Flush Event Invert Enable + 2 + 1 + + + STARTINV + Satrt Event Invert Enable + 3 + 1 + + + RESRDYEO + Result Ready Event Out + 4 + 1 + + + WINMONEO + Window Monitor Event Out + 5 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x5 + 8 + 0x00 + + + RESRDY + Result Ready Interrupt Disable + 0 + 1 + + + OVERRUN + Overrun Interrupt Disable + 1 + 1 + + + WINMON + Window Monitor Interrupt Disable + 2 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x6 + 8 + 0x00 + + + RESRDY + Result Ready Interrupt Enable + 0 + 1 + + + OVERRUN + Overrun Interrupt Enable + 1 + 1 + + + WINMON + Window Monitor Interrupt Enable + 2 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x7 + 8 + 0x00 + + + RESRDY + Result Ready Interrupt Flag + 0 + 1 + + + OVERRUN + Overrun Interrupt Flag + 1 + 1 + + + WINMON + Window Monitor Interrupt Flag + 2 + 1 + + + + + SEQSTATUS + Sequence Status + 0x8 + 8 + read-only + 0x00 + + + SEQSTATE + Sequence State + 0 + 4 + + + SEQBUSY + Sequence Busy + 7 + 1 + + + + + INPUTCTRL + Input Control + 0x9 + 8 + 0x00 + + + MUXSEL + SDADC Input Selection + 0 + 4 + + MUXSELSelect + + AIN0 + SDADC AIN0 Pin + 0x0 + + + AIN1 + SDADC AIN1 Pin + 0x1 + + + AIN2 + SDADC AIN2 Pin + 0x2 + + + + + + + CTRLC + Control C + 0xA + 8 + 0x00 + + + FREERUN + Free Running Mode + 0 + 1 + + + + + WINCTRL + Window Monitor Control + 0xB + 8 + 0x00 + + + WINMODE + Window Monitor Mode + 0 + 3 + + + + + WINLT + Window Monitor Lower Threshold + 0xC + 32 + 0x00000000 + + + WINLT + Window Lower Threshold + 0 + 24 + + + + + WINUT + Window Monitor Upper Threshold + 0x10 + 32 + 0x00000000 + + + WINUT + Window Upper Threshold + 0 + 24 + + + + + OFFSETCORR + Offset Correction + 0x14 + 32 + 0x00000000 + + + OFFSETCORR + Offset Correction Value + 0 + 24 + + + + + GAINCORR + Gain Correction + 0x18 + 16 + 0x0001 + + + GAINCORR + Gain Correction Value + 0 + 14 + + + + + SHIFTCORR + Shift Correction + 0x1A + 8 + 0x00 + + + SHIFTCORR + Shift Correction Value + 0 + 4 + + + + + SWTRIG + Software Trigger + 0x1C + 8 + 0x00 + + + FLUSH + SDADC Flush + 0 + 1 + + + START + Start SDADC Conversion + 1 + 1 + + + + + SYNCBUSY + Synchronization Busy + 0x20 + 32 + read-only + 0x00000000 + + + SWRST + SWRST Synchronization Busy + 0 + 1 + + + ENABLE + ENABLE Synchronization Busy + 1 + 1 + + + CTRLC + CTRLC Synchronization Busy + 2 + 1 + + + INPUTCTRL + INPUTCTRL Synchronization Busy + 3 + 1 + + + WINCTRL + WINCTRL Synchronization Busy + 4 + 1 + + + WINLT + WINLT Synchronization Busy + 5 + 1 + + + WINUT + WINUT Synchronization Busy + 6 + 1 + + + OFFSETCORR + OFFSETCTRL Synchronization Busy + 7 + 1 + + + GAINCORR + GAINCORR Synchronization Busy + 8 + 1 + + + SHIFTCORR + SHIFTCORR Synchronization Busy + 9 + 1 + + + SWTRIG + SWTRG Synchronization Busy + 10 + 1 + + + ANACTRL + ANACTRL Synchronization Busy + 11 + 1 + + + + + RESULT + Result + 0x24 + 32 + read-only + 0x00000000 + + + RESULT + Result Value + 0 + 24 + + + RESERVED + 24 + 8 + + + + + SEQCTRL + Sequence Control + 0x28 + 8 + 0x00 + + + SEQEN + Enable Positive Input in the Sequence + 0 + 3 + + + + + ANACTRL + Analog Control + 0x2C + 8 + 0x00 + + + CTRSDADC + SDADC Control + 0 + 6 + + + ONCHOP + Chopper + 6 + 1 + + + BUFTEST + BUFTEST + 7 + 1 + + + + + DBGCTRL + Debug Control + 0x2E + 8 + 0x00 + + + DBGRUN + Debug Run + 0 + 1 + + + + + + + SERCOM0 + U22013.1.1 + Serial Communication Interface + SERCOM + SERCOM_ + 0x42000400 + + 0 + 0x31 + registers + + + SERCOM0 + 9 + + + + I2CM + I2C Master Mode + SercomI2cm + 0x0 + + CTRLA + I2CM Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run in Standby + 7 + 1 + + + PINOUT + Pin Usage + 16 + 1 + + + SDAHOLD + SDA Hold Time + 20 + 2 + + SDAHOLDSelect + + DISABLE + Disabled + 0x0 + + + 75NS + 50-100ns hold time + 0x1 + + + 450NS + 300-600ns hold time + 0x2 + + + 600NS + 400-800ns hold time + 0x3 + + + + + MEXTTOEN + Master SCL Low Extend Timeout + 22 + 1 + + + SEXTTOEN + Slave SCL Low Extend Timeout + 23 + 1 + + + SPEED + Transfer Speed + 24 + 2 + + SPEEDSelect + + STANDARD_AND_FAST_MODE + Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz + 0x0 + + + FASTPLUS_MODE + Fast-mode Plus Upto 1MHz + 0x1 + + + HIGH_SPEED_MODE + High-speed mode Upto 3.4MHz + 0x2 + + + + + SCLSM + SCL Clock Stretch Mode + 27 + 1 + + + INACTOUT + Inactive Time-Out + 28 + 2 + + INACTOUTSelect + + DISABLE + Disabled + 0x0 + + + 55US + 5-6 SCL Time-Out(50-60us) + 0x1 + + + 105US + 10-11 SCL Time-Out(100-110us) + 0x2 + + + 205US + 20-21 SCL Time-Out(200-210us) + 0x3 + + + + + LOWTOUTEN + SCL Low Timeout Enable + 30 + 1 + + + + + CTRLB + I2CM Control B + 0x4 + 32 + 0x00000000 + + + SMEN + Smart Mode Enable + 8 + 1 + + + QCEN + Quick Command Enable + 9 + 1 + + + CMD + Command + 16 + 2 + + + ACKACT + Acknowledge Action + 18 + 1 + + + + + BAUD + I2CM Baud Rate + 0xC + 32 + 0x00000000 + + + BAUD + Baud Rate Value + 0 + 8 + + + BAUDLOW + Baud Rate Value Low + 8 + 8 + + + HSBAUD + High Speed Baud Rate Value + 16 + 8 + + + HSBAUDLOW + High Speed Baud Rate Value Low + 24 + 8 + + + + + INTENCLR + I2CM Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + MB + Master On Bus Interrupt Disable + 0 + 1 + + + SB + Slave On Bus Interrupt Disable + 1 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + I2CM Interrupt Enable Set + 0x16 + 8 + 0x00 + + + MB + Master On Bus Interrupt Enable + 0 + 1 + + + SB + Slave On Bus Interrupt Enable + 1 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + I2CM Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + MB + Master On Bus Interrupt + 0 + 1 + + + SB + Slave On Bus Interrupt + 1 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + I2CM Status + 0x1A + 16 + 0x0000 + + + BUSERR + Bus Error + 0 + 1 + + + ARBLOST + Arbitration Lost + 1 + 1 + + + RXNACK + Received Not Acknowledge + 2 + 1 + + + BUSSTATE + Bus State + 4 + 2 + + + LOWTOUT + SCL Low Timeout + 6 + 1 + + + CLKHOLD + Clock Hold + 7 + 1 + + + MEXTTOUT + Master SCL Low Extend Timeout + 8 + 1 + + + SEXTTOUT + Slave SCL Low Extend Timeout + 9 + 1 + + + LENERR + Length Error + 10 + 1 + + + + + SYNCBUSY + I2CM Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + SYSOP + System Operation Synchronization Busy + 2 + 1 + + + + + ADDR + I2CM Address + 0x24 + 32 + 0x00000000 + + + ADDR + Address Value + 0 + 11 + + + LENEN + Length Enable + 13 + 1 + + + HS + High Speed Mode + 14 + 1 + + + TENBITEN + Ten Bit Addressing Enable + 15 + 1 + + + LEN + Length + 16 + 8 + + + + + DATA + I2CM Data + 0x28 + 8 + 0x00 + + + DATA + Data Value + 0 + 8 + + + + + DBGCTRL + I2CM Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + I2CS + I2C Slave Mode + I2CM + SercomI2cs + 0x0 + + CTRLA + I2CS Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + PINOUT + Pin Usage + 16 + 1 + + + SDAHOLD + SDA Hold Time + 20 + 2 + + SDAHOLDSelect + + DISABLE + Disabled + 0x0 + + + 75NS + 50-100ns hold time + 0x1 + + + 450NS + 300-600ns hold time + 0x2 + + + 600NS + 400-800ns hold time + 0x3 + + + + + SEXTTOEN + Slave SCL Low Extend Timeout + 23 + 1 + + + SPEED + Transfer Speed + 24 + 2 + + SPEEDSelect + + STANDARD_AND_FAST_MODE + Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz + 0x0 + + + FASTPLUS_MODE + Fast-mode Plus Upto 1MHz + 0x1 + + + HIGH_SPEED_MODE + High-speed mode Upto 3.4MHz + 0x2 + + + + + SCLSM + SCL Clock Stretch Mode + 27 + 1 + + + LOWTOUTEN + SCL Low Timeout Enable + 30 + 1 + + + + + CTRLB + I2CS Control B + 0x4 + 32 + 0x00000000 + + + SMEN + Smart Mode Enable + 8 + 1 + + + GCMD + PMBus Group Command + 9 + 1 + + + AACKEN + Automatic Address Acknowledge + 10 + 1 + + + AMODE + Address Mode + 14 + 2 + + + CMD + Command + 16 + 2 + + + ACKACT + Acknowledge Action + 18 + 1 + + + + + INTENCLR + I2CS Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + PREC + Stop Received Interrupt Disable + 0 + 1 + + + AMATCH + Address Match Interrupt Disable + 1 + 1 + + + DRDY + Data Interrupt Disable + 2 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + I2CS Interrupt Enable Set + 0x16 + 8 + 0x00 + + + PREC + Stop Received Interrupt Enable + 0 + 1 + + + AMATCH + Address Match Interrupt Enable + 1 + 1 + + + DRDY + Data Interrupt Enable + 2 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + I2CS Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + PREC + Stop Received Interrupt + 0 + 1 + + + AMATCH + Address Match Interrupt + 1 + 1 + + + DRDY + Data Interrupt + 2 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + I2CS Status + 0x1A + 16 + 0x0000 + + + BUSERR + Bus Error + 0 + 1 + + + COLL + Transmit Collision + 1 + 1 + + + RXNACK + Received Not Acknowledge + 2 + 1 + + + DIR + Read/Write Direction + 3 + 1 + + + SR + Repeated Start + 4 + 1 + + + LOWTOUT + SCL Low Timeout + 6 + 1 + + + CLKHOLD + Clock Hold + 7 + 1 + + + SEXTTOUT + Slave SCL Low Extend Timeout + 9 + 1 + + + HS + High Speed + 10 + 1 + + + + + SYNCBUSY + I2CS Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + + + ADDR + I2CS Address + 0x24 + 32 + 0x00000000 + + + GENCEN + General Call Address Enable + 0 + 1 + + + ADDR + Address Value + 1 + 10 + + + TENBITEN + Ten Bit Addressing Enable + 15 + 1 + + + ADDRMASK + Address Mask + 17 + 10 + + + + + DATA + I2CS Data + 0x28 + 8 + 0x00 + + + DATA + Data Value + 0 + 8 + + + + + + SPIS + SPI Slave Mode + I2CM + SercomSpis + 0x0 + + CTRLA + SPIS Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + IBON + Immediate Buffer Overflow Notification + 8 + 1 + + + DOPO + Data Out Pinout + 16 + 2 + + DOPOSelect + + PAD0 + DO on PAD[0], SCK on PAD[1] and SS on PAD[2] + 0x0 + + + PAD1 + DO on PAD[2], SCK on PAD[3] and SS on PAD[1] + 0x1 + + + PAD2 + DO on PAD[3], SCK on PAD[1] and SS on PAD[2] + 0x2 + + + PAD3 + DO on PAD[0], SCK on PAD[3] and SS on PAD[1] + 0x3 + + + + + DIPO + Data In Pinout + 20 + 2 + + DIPOSelect + + PAD0 + SERCOM PAD[0] + 0x0 + + + PAD1 + SERCOM PAD[1] + 0x1 + + + PAD2 + SERCOM PAD[2] + 0x2 + + + PAD3 + SERCOM PAD[3] + 0x3 + + + + + FORM + Frame Format + 24 + 4 + + FORMSelect + + SPI_FRAME + SPI Frame + 0x0 + + + SPI_FRAME_WITH_ADDR + SPI Frame with Addr + 0x2 + + + + + CPHA + Clock Phase + 28 + 1 + + CPHASelect + + LEADING_EDGE + The data is sampled on a leading SCK edge and changed on a trailing SCK edge + 0x0 + + + TRAILING_EDGE + The data is sampled on a trailing SCK edge and changed on a leading SCK edge + 0x1 + + + + + CPOL + Clock Polarity + 29 + 1 + + CPOLSelect + + IDLE_LOW + SCK is low when idle + 0x0 + + + IDLE_HIGH + SCK is high when idle + 0x1 + + + + + DORD + Data Order + 30 + 1 + + DORDSelect + + MSB + MSB is transferred first + 0x0 + + + LSB + LSB is transferred first + 0x1 + + + + + + + CTRLB + SPIS Control B + 0x4 + 32 + 0x00000000 + + + CHSIZE + Character Size + 0 + 3 + + CHSIZESelect + + 8_BIT + 8 bits + 0x0 + + + 9_BIT + 9 bits + 0x1 + + + + + PLOADEN + Data Preload Enable + 6 + 1 + + + SSDE + Slave Select Low Detect Enable + 9 + 1 + + + MSSEN + Master Slave Select Enable + 13 + 1 + + + AMODE + Address Mode + 14 + 2 + + AMODESelect + + MASK + SPI Address mask + 0x0 + + + 2_ADDRESSES + Two unique Addressess + 0x1 + + + RANGE + Address Range + 0x2 + + + + + RXEN + Receiver Enable + 17 + 1 + + + + + BAUD + SPIS Baud Rate + 0xC + 8 + 0x00 + + + BAUD + Baud Rate Value + 0 + 8 + + + + + INTENCLR + SPIS Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Disable + 0 + 1 + + + TXC + Transmit Complete Interrupt Disable + 1 + 1 + + + RXC + Receive Complete Interrupt Disable + 2 + 1 + + + SSL + Slave Select Low Interrupt Disable + 3 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + SPIS Interrupt Enable Set + 0x16 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Enable + 0 + 1 + + + TXC + Transmit Complete Interrupt Enable + 1 + 1 + + + RXC + Receive Complete Interrupt Enable + 2 + 1 + + + SSL + Slave Select Low Interrupt Enable + 3 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + SPIS Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt + 0 + 1 + + + TXC + Transmit Complete Interrupt + 1 + 1 + + + RXC + Receive Complete Interrupt + 2 + 1 + + + SSL + Slave Select Low Interrupt Flag + 3 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + SPIS Status + 0x1A + 16 + 0x0000 + + + BUFOVF + Buffer Overflow + 2 + 1 + + + + + SYNCBUSY + SPIS Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + CTRLB + CTRLB Synchronization Busy + 2 + 1 + + + + + ADDR + SPIS Address + 0x24 + 32 + 0x00000000 + + + ADDR + Address Value + 0 + 8 + + + ADDRMASK + Address Mask + 16 + 8 + + + + + DATA + SPIS Data + 0x28 + 32 + 0x00000000 + + + DATA + Data Value + 0 + 9 + + + + + DBGCTRL + SPIS Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + SPIM + SPI Master Mode + I2CM + SercomSpim + 0x0 + + CTRLA + SPIM Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + IBON + Immediate Buffer Overflow Notification + 8 + 1 + + + DOPO + Data Out Pinout + 16 + 2 + + DOPOSelect + + PAD0 + DO on PAD[0], SCK on PAD[1] and SS on PAD[2] + 0x0 + + + PAD1 + DO on PAD[2], SCK on PAD[3] and SS on PAD[1] + 0x1 + + + PAD2 + DO on PAD[3], SCK on PAD[1] and SS on PAD[2] + 0x2 + + + PAD3 + DO on PAD[0], SCK on PAD[3] and SS on PAD[1] + 0x3 + + + + + DIPO + Data In Pinout + 20 + 2 + + DIPOSelect + + PAD0 + SERCOM PAD[0] + 0x0 + + + PAD1 + SERCOM PAD[1] + 0x1 + + + PAD2 + SERCOM PAD[2] + 0x2 + + + PAD3 + SERCOM PAD[3] + 0x3 + + + + + FORM + Frame Format + 24 + 4 + + FORMSelect + + SPI_FRAME + SPI Frame + 0x0 + + + SPI_FRAME_WITH_ADDR + SPI Frame with Addr + 0x2 + + + + + CPHA + Clock Phase + 28 + 1 + + CPHASelect + + LEADING_EDGE + The data is sampled on a leading SCK edge and changed on a trailing SCK edge + 0x0 + + + TRAILING_EDGE + The data is sampled on a trailing SCK edge and changed on a leading SCK edge + 0x1 + + + + + CPOL + Clock Polarity + 29 + 1 + + CPOLSelect + + IDLE_LOW + SCK is low when idle + 0x0 + + + IDLE_HIGH + SCK is high when idle + 0x1 + + + + + DORD + Data Order + 30 + 1 + + DORDSelect + + MSB + MSB is transferred first + 0x0 + + + LSB + LSB is transferred first + 0x1 + + + + + + + CTRLB + SPIM Control B + 0x4 + 32 + 0x00000000 + + + CHSIZE + Character Size + 0 + 3 + + CHSIZESelect + + 8_BIT + 8 bits + 0x0 + + + 9_BIT + 9 bits + 0x1 + + + + + PLOADEN + Data Preload Enable + 6 + 1 + + + SSDE + Slave Select Low Detect Enable + 9 + 1 + + + MSSEN + Master Slave Select Enable + 13 + 1 + + + AMODE + Address Mode + 14 + 2 + + AMODESelect + + MASK + SPI Address mask + 0x0 + + + 2_ADDRESSES + Two unique Addressess + 0x1 + + + RANGE + Address Range + 0x2 + + + + + RXEN + Receiver Enable + 17 + 1 + + + + + BAUD + SPIM Baud Rate + 0xC + 8 + 0x00 + + + BAUD + Baud Rate Value + 0 + 8 + + + + + INTENCLR + SPIM Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Disable + 0 + 1 + + + TXC + Transmit Complete Interrupt Disable + 1 + 1 + + + RXC + Receive Complete Interrupt Disable + 2 + 1 + + + SSL + Slave Select Low Interrupt Disable + 3 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + SPIM Interrupt Enable Set + 0x16 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Enable + 0 + 1 + + + TXC + Transmit Complete Interrupt Enable + 1 + 1 + + + RXC + Receive Complete Interrupt Enable + 2 + 1 + + + SSL + Slave Select Low Interrupt Enable + 3 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + SPIM Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt + 0 + 1 + + + TXC + Transmit Complete Interrupt + 1 + 1 + + + RXC + Receive Complete Interrupt + 2 + 1 + + + SSL + Slave Select Low Interrupt Flag + 3 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + SPIM Status + 0x1A + 16 + 0x0000 + + + BUFOVF + Buffer Overflow + 2 + 1 + + + + + SYNCBUSY + SPIM Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + CTRLB + CTRLB Synchronization Busy + 2 + 1 + + + + + ADDR + SPIM Address + 0x24 + 32 + 0x00000000 + + + ADDR + Address Value + 0 + 8 + + + ADDRMASK + Address Mask + 16 + 8 + + + + + DATA + SPIM Data + 0x28 + 32 + 0x00000000 + + + DATA + Data Value + 0 + 9 + + + + + DBGCTRL + SPIM Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + USART_EXT + USART EXTERNAL CLOCK Mode + I2CM + SercomUsart_ext + 0x0 + + CTRLA + USART_EXT Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + IBON + Immediate Buffer Overflow Notification + 8 + 1 + + + SAMPR + Sample + 13 + 3 + + SAMPRSelect + + 16X_ARITHMETIC + 16x over-sampling using arithmetic baudrate generation + 0x0 + + + 16X_FRACTIONAL + 16x over-sampling using fractional baudrate generation + 0x1 + + + 8X_ARITHMETIC + 8x over-sampling using arithmetic baudrate generation + 0x2 + + + 8X_FRACTIONAL + 8x over-sampling using fractional baudrate generation + 0x3 + + + 3X_ARITHMETIC + 3x over-sampling using arithmetic baudrate generation + 0x4 + + + + + TXPO + Transmit Data Pinout + 16 + 2 + + TXPOSelect + + PAD0 + SERCOM PAD[0] is used for data transmission + 0x0 + + + PAD2 + SERCOM PAD[2] is used for data transmission + 0x1 + + + + + RXPO + Receive Data Pinout + 20 + 2 + + RXPOSelect + + PAD0 + SERCOM PAD[0] is used for data reception + 0x0 + + + PAD1 + SERCOM PAD[1] is used for data reception + 0x1 + + + PAD2 + SERCOM PAD[2] is used for data reception + 0x2 + + + PAD3 + SERCOM PAD[3] is used for data reception + 0x3 + + + + + SAMPA + Sample Adjustment + 22 + 2 + + + FORM + Frame Format + 24 + 4 + + FORMSelect + + USART_FRAME_NO_PARITY + USART frame + 0x0 + + + USART_FRAME_WITH_PARITY + USART frame with parity + 0x1 + + + USART_FRAME_LIN_MASTER_MODE + LIN Master - Break and sync generation + 0x2 + + + USART_FRAME_AUTO_BAUD_NO_PARITY + Auto-baud - break detection and auto-baud + 0x4 + + + USART_FRAME_AUTO_BAUD_WITH_PARITY + Auto-baud - break detection and auto-baud with parity + 0x5 + + + + + CMODE + Communication Mode + 28 + 1 + + CMODESelect + + ASYNC + Asynchronous Communication + 0x0 + + + SYNC + Synchronous Communication + 0x1 + + + + + CPOL + Clock Polarity + 29 + 1 + + CPOLSelect + + IDLE_LOW + TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge + 0x0 + + + IDLE_HIGH + TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge + 0x1 + + + + + DORD + Data Order + 30 + 1 + + DORDSelect + + MSB + MSB is transmitted first + 0x0 + + + LSB + LSB is transmitted first + 0x1 + + + + + + + CTRLB + USART_EXT Control B + 0x4 + 32 + 0x00000000 + + + CHSIZE + Character Size + 0 + 3 + + CHSIZESelect + + 8_BIT + 8 Bits + 0x0 + + + 9_BIT + 9 Bits + 0x1 + + + 5_BIT + 5 Bits + 0x5 + + + 6_BIT + 6 Bits + 0x6 + + + 7_BIT + 7 Bits + 0x7 + + + + + SBMODE + Stop Bit Mode + 6 + 1 + + SBMODESelect + + 1_BIT + One Stop Bit + 0x0 + + + 2_BIT + Two Stop Bits + 0x1 + + + + + COLDEN + Collision Detection Enable + 8 + 1 + + + SFDE + Start of Frame Detection Enable + 9 + 1 + + + ENC + Encoding Format + 10 + 1 + + + PMODE + Parity Mode + 13 + 1 + + PMODESelect + + EVEN + Even Parity + 0x0 + + + ODD + Odd Parity + 0x1 + + + + + TXEN + Transmitter Enable + 16 + 1 + + + RXEN + Receiver Enable + 17 + 1 + + + LINCMD + LIN Command + 24 + 2 + + + + + CTRLC + USART_EXT Control C + 0x8 + 32 + 0x00000000 + + + GTIME + RS485 Guard Time + 0 + 3 + + + BRKLEN + LIN Master Break Length + 8 + 2 + + + HDRDLY + LIN Master Header Delay + 10 + 2 + + + + + BAUD + USART_EXT Baud Rate + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 16 + + + + + BAUD_FRAC_MODE + USART_EXT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 13 + + + FP + Fractional Part + 13 + 3 + + + + + BAUD_FRACFP_MODE + USART_EXT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 13 + + + FP + Fractional Part + 13 + 3 + + + + + BAUD_USARTFP_MODE + USART_EXT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 16 + + + + + RXPL + USART_EXT Receive Pulse Length + 0xE + 8 + 0x00 + + + RXPL + Receive Pulse Length + 0 + 8 + + + + + INTENCLR + USART_EXT Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Disable + 0 + 1 + + + TXC + Transmit Complete Interrupt Disable + 1 + 1 + + + RXC + Receive Complete Interrupt Disable + 2 + 1 + + + RXS + Receive Start Interrupt Disable + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt Disable + 4 + 1 + + + RXBRK + Break Received Interrupt Disable + 5 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + USART_EXT Interrupt Enable Set + 0x16 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Enable + 0 + 1 + + + TXC + Transmit Complete Interrupt Enable + 1 + 1 + + + RXC + Receive Complete Interrupt Enable + 2 + 1 + + + RXS + Receive Start Interrupt Enable + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt Enable + 4 + 1 + + + RXBRK + Break Received Interrupt Enable + 5 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + USART_EXT Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt + 0 + 1 + + + TXC + Transmit Complete Interrupt + 1 + 1 + + + RXC + Receive Complete Interrupt + 2 + 1 + + + RXS + Receive Start Interrupt + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt + 4 + 1 + + + RXBRK + Break Received Interrupt + 5 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + USART_EXT Status + 0x1A + 16 + 0x0000 + + + PERR + Parity Error + 0 + 1 + + + FERR + Frame Error + 1 + 1 + + + BUFOVF + Buffer Overflow + 2 + 1 + + + CTS + Clear To Send + 3 + 1 + + + ISF + Inconsistent Sync Field + 4 + 1 + + + COLL + Collision Detected + 5 + 1 + + + TXE + Transmitter Empty + 6 + 1 + + + + + SYNCBUSY + USART_EXT Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + CTRLB + CTRLB Synchronization Busy + 2 + 1 + + + + + DATA + USART_EXT Data + 0x28 + 16 + 0x0000 + + + DATA + Data Value + 0 + 9 + + + + + DBGCTRL + USART_EXT Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + USART_INT + USART INTERNAL CLOCK Mode + I2CM + SercomUsart_int + 0x0 + + CTRLA + USART_INT Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + IBON + Immediate Buffer Overflow Notification + 8 + 1 + + + SAMPR + Sample + 13 + 3 + + SAMPRSelect + + 16X_ARITHMETIC + 16x over-sampling using arithmetic baudrate generation + 0x0 + + + 16X_FRACTIONAL + 16x over-sampling using fractional baudrate generation + 0x1 + + + 8X_ARITHMETIC + 8x over-sampling using arithmetic baudrate generation + 0x2 + + + 8X_FRACTIONAL + 8x over-sampling using fractional baudrate generation + 0x3 + + + 3X_ARITHMETIC + 3x over-sampling using arithmetic baudrate generation + 0x4 + + + + + TXPO + Transmit Data Pinout + 16 + 2 + + TXPOSelect + + PAD0 + SERCOM PAD[0] is used for data transmission + 0x0 + + + PAD2 + SERCOM PAD[2] is used for data transmission + 0x1 + + + + + RXPO + Receive Data Pinout + 20 + 2 + + RXPOSelect + + PAD0 + SERCOM PAD[0] is used for data reception + 0x0 + + + PAD1 + SERCOM PAD[1] is used for data reception + 0x1 + + + PAD2 + SERCOM PAD[2] is used for data reception + 0x2 + + + PAD3 + SERCOM PAD[3] is used for data reception + 0x3 + + + + + SAMPA + Sample Adjustment + 22 + 2 + + + FORM + Frame Format + 24 + 4 + + FORMSelect + + USART_FRAME_NO_PARITY + USART frame + 0x0 + + + USART_FRAME_WITH_PARITY + USART frame with parity + 0x1 + + + USART_FRAME_LIN_MASTER_MODE + LIN Master - Break and sync generation + 0x2 + + + USART_FRAME_AUTO_BAUD_NO_PARITY + Auto-baud - break detection and auto-baud + 0x4 + + + USART_FRAME_AUTO_BAUD_WITH_PARITY + Auto-baud - break detection and auto-baud with parity + 0x5 + + + + + CMODE + Communication Mode + 28 + 1 + + CMODESelect + + ASYNC + Asynchronous Communication + 0x0 + + + SYNC + Synchronous Communication + 0x1 + + + + + CPOL + Clock Polarity + 29 + 1 + + CPOLSelect + + IDLE_LOW + TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge + 0x0 + + + IDLE_HIGH + TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge + 0x1 + + + + + DORD + Data Order + 30 + 1 + + DORDSelect + + MSB + MSB is transmitted first + 0x0 + + + LSB + LSB is transmitted first + 0x1 + + + + + + + CTRLB + USART_INT Control B + 0x4 + 32 + 0x00000000 + + + CHSIZE + Character Size + 0 + 3 + + CHSIZESelect + + 8_BIT + 8 Bits + 0x0 + + + 9_BIT + 9 Bits + 0x1 + + + 5_BIT + 5 Bits + 0x5 + + + 6_BIT + 6 Bits + 0x6 + + + 7_BIT + 7 Bits + 0x7 + + + + + SBMODE + Stop Bit Mode + 6 + 1 + + SBMODESelect + + 1_BIT + One Stop Bit + 0x0 + + + 2_BIT + Two Stop Bits + 0x1 + + + + + COLDEN + Collision Detection Enable + 8 + 1 + + + SFDE + Start of Frame Detection Enable + 9 + 1 + + + ENC + Encoding Format + 10 + 1 + + + PMODE + Parity Mode + 13 + 1 + + PMODESelect + + EVEN + Even Parity + 0x0 + + + ODD + Odd Parity + 0x1 + + + + + TXEN + Transmitter Enable + 16 + 1 + + + RXEN + Receiver Enable + 17 + 1 + + + LINCMD + LIN Command + 24 + 2 + + + + + CTRLC + USART_INT Control C + 0x8 + 32 + 0x00000000 + + + GTIME + RS485 Guard Time + 0 + 3 + + + BRKLEN + LIN Master Break Length + 8 + 2 + + + HDRDLY + LIN Master Header Delay + 10 + 2 + + + + + BAUD + USART_INT Baud Rate + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 16 + + + + + BAUD_FRAC_MODE + USART_INT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 13 + + + FP + Fractional Part + 13 + 3 + + + + + BAUD_FRACFP_MODE + USART_INT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 13 + + + FP + Fractional Part + 13 + 3 + + + + + BAUD_USARTFP_MODE + USART_INT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 16 + + + + + RXPL + USART_INT Receive Pulse Length + 0xE + 8 + 0x00 + + + RXPL + Receive Pulse Length + 0 + 8 + + + + + INTENCLR + USART_INT Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Disable + 0 + 1 + + + TXC + Transmit Complete Interrupt Disable + 1 + 1 + + + RXC + Receive Complete Interrupt Disable + 2 + 1 + + + RXS + Receive Start Interrupt Disable + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt Disable + 4 + 1 + + + RXBRK + Break Received Interrupt Disable + 5 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + USART_INT Interrupt Enable Set + 0x16 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Enable + 0 + 1 + + + TXC + Transmit Complete Interrupt Enable + 1 + 1 + + + RXC + Receive Complete Interrupt Enable + 2 + 1 + + + RXS + Receive Start Interrupt Enable + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt Enable + 4 + 1 + + + RXBRK + Break Received Interrupt Enable + 5 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + USART_INT Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt + 0 + 1 + + + TXC + Transmit Complete Interrupt + 1 + 1 + + + RXC + Receive Complete Interrupt + 2 + 1 + + + RXS + Receive Start Interrupt + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt + 4 + 1 + + + RXBRK + Break Received Interrupt + 5 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + USART_INT Status + 0x1A + 16 + 0x0000 + + + PERR + Parity Error + 0 + 1 + + + FERR + Frame Error + 1 + 1 + + + BUFOVF + Buffer Overflow + 2 + 1 + + + CTS + Clear To Send + 3 + 1 + + + ISF + Inconsistent Sync Field + 4 + 1 + + + COLL + Collision Detected + 5 + 1 + + + TXE + Transmitter Empty + 6 + 1 + + + + + SYNCBUSY + USART_INT Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + CTRLB + CTRLB Synchronization Busy + 2 + 1 + + + + + DATA + USART_INT Data + 0x28 + 16 + 0x0000 + + + DATA + Data Value + 0 + 9 + + + + + DBGCTRL + USART_INT Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + + + SERCOM1 + 0x42000800 + + SERCOM1 + 10 + + + + SERCOM2 + 0x42000C00 + + SERCOM2 + 11 + + + + SERCOM3 + 0x42001000 + + SERCOM3 + 12 + + + + SERCOM4 + 0x42001400 + + SERCOM4 + 13 + + + + SERCOM5 + 0x42001800 + + SERCOM5 + 14 + + + + SUPC + U21172.1.1 + Supply Controller + SUPC + SUPC_ + 0x40001800 + + 0 + 0x20 + registers + + + + INTENCLR + Interrupt Enable Clear + 0x0 + 32 + 0x00000000 + + + BODVDDRDY + BODVDD Ready + 0 + 1 + + + BODVDDDET + BODVDD Detection + 1 + 1 + + + BVDDSRDY + BODVDD Synchronization Ready + 2 + 1 + + + BODCORERDY + BODCORE Ready + 3 + 1 + + + BODCOREDET + BODCORE Detection + 4 + 1 + + + BCORESRDY + BODCORE Synchronization Ready + 5 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x4 + 32 + 0x00000000 + + + BODVDDRDY + BODVDD Ready + 0 + 1 + + + BODVDDDET + BODVDD Detection + 1 + 1 + + + BVDDSRDY + BODVDD Synchronization Ready + 2 + 1 + + + BODCORERDY + BODCORE Ready + 3 + 1 + + + BODCOREDET + BODCORE Detection + 4 + 1 + + + BCORESRDY + BODCORE Synchronization Ready + 5 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x8 + 32 + 0x00000000 + + + BODVDDRDY + BODVDD Ready + 0 + 1 + + + BODVDDDET + BODVDD Detection + 1 + 1 + + + BVDDSRDY + BODVDD Synchronization Ready + 2 + 1 + + + BODCORERDY + BODCORE Ready + 3 + 1 + + + BODCOREDET + BODCORE Detection + 4 + 1 + + + BCORESRDY + BODCORE Synchronization Ready + 5 + 1 + + + + + STATUS + Power and Clocks Status + 0xC + 32 + read-only + 0x00000000 + + + BODVDDRDY + BODVDD Ready + 0 + 1 + + + BODVDDDET + BODVDD Detection + 1 + 1 + + + BVDDSRDY + BODVDD Synchronization Ready + 2 + 1 + + + BODCORERDY + BODCORE Ready + 3 + 1 + + + BODCOREDET + BODCORE Detection + 4 + 1 + + + BCORESRDY + BODCORE Synchronization Ready + 5 + 1 + + + + + BODVDD + BODVDD Control + 0x10 + 32 + 0x00000000 + + + ENABLE + Enable + 1 + 1 + + + HYST + Hysteresis Enable + 2 + 1 + + + ACTION + Action when Threshold Crossed + 3 + 2 + + ACTIONSelect + + NONE + No action + 0x0 + + + RESET + The BODVDD generates a reset + 0x1 + + + INT + The BODVDD generates an interrupt + 0x2 + + + + + STDBYCFG + Configuration in Standby mode + 5 + 1 + + + RUNSTDBY + Run during Standby + 6 + 1 + + + ACTCFG + Configuration in Active mode + 8 + 1 + + + PSEL + Prescaler Select + 12 + 4 + + PSELSelect + + DIV2 + Divide clock by 2 + 0x0 + + + DIV4 + Divide clock by 4 + 0x1 + + + DIV8 + Divide clock by 8 + 0x2 + + + DIV16 + Divide clock by 16 + 0x3 + + + DIV32 + Divide clock by 32 + 0x4 + + + DIV64 + Divide clock by 64 + 0x5 + + + DIV128 + Divide clock by 128 + 0x6 + + + DIV256 + Divide clock by 256 + 0x7 + + + DIV512 + Divide clock by 512 + 0x8 + + + DIV1024 + Divide clock by 1024 + 0x9 + + + DIV2048 + Divide clock by 2048 + 0xA + + + DIV4096 + Divide clock by 4096 + 0xB + + + DIV8192 + Divide clock by 8192 + 0xC + + + DIV16384 + Divide clock by 16384 + 0xD + + + DIV32768 + Divide clock by 32768 + 0xE + + + DIV65536 + Divide clock by 65536 + 0xF + + + + + LEVEL + Threshold Level for VDD + 16 + 6 + + + + + BODCORE + BODCORE Control + 0x14 + 32 + 0x00000000 + + + ENABLE + Enable + 1 + 1 + + + HYST + Hysteresis Enable + 2 + 1 + + + ACTION + Action when Threshold Crossed + 3 + 2 + + ACTIONSelect + + NONE + No action + 0x0 + + + RESET + The BODCORE generates a reset + 0x1 + + + INT + The BODCORE generates an interrupt + 0x2 + + + + + STDBYCFG + Configuration in Standby mode + 5 + 1 + + + RUNSTDBY + Run during Standby + 6 + 1 + + + ACTCFG + Configuration in Active mode + 8 + 1 + + + PSEL + Prescaler Select + 12 + 4 + + PSELSelect + + DIV2 + Divide clock by 2 + 0x0 + + + DIV4 + Divide clock by 4 + 0x1 + + + DIV8 + Divide clock by 8 + 0x2 + + + DIV16 + Divide clock by 16 + 0x3 + + + DIV32 + Divide clock by 32 + 0x4 + + + DIV64 + Divide clock by 64 + 0x5 + + + DIV128 + Divide clock by 128 + 0x6 + + + DIV256 + Divide clock by 256 + 0x7 + + + DIV512 + Divide clock by 512 + 0x8 + + + DIV1024 + Divide clock by 1024 + 0x9 + + + DIV2048 + Divide clock by 2048 + 0xA + + + DIV4096 + Divide clock by 4096 + 0xB + + + DIV8192 + Divide clock by 8192 + 0xC + + + DIV16384 + Divide clock by 16384 + 0xD + + + DIV32768 + Divide clock by 32768 + 0xE + + + DIV65536 + Divide clock by 65536 + 0xF + + + + + LEVEL + Threshold Level + 16 + 6 + + + + + VREG + VREG Control + 0x18 + 32 + 0x00000000 + + + ENABLE + Enable + 1 + 1 + + + RUNSTDBY + Run during Standby + 6 + 1 + + + + + VREF + VREF Control + 0x1C + 32 + 0x00000000 + + + TSEN + Temperature Sensor Output Enable + 1 + 1 + + + VREFOE + Voltage Reference Output Enable + 2 + 1 + + + RUNSTDBY + Run during Standby + 6 + 1 + + + ONDEMAND + On Demand Contrl + 7 + 1 + + + SEL + Voltage Reference Selection + 16 + 4 + + SELSelect + + 1V024 + 1.024V voltage reference typical value + 0x0 + + + 2V048 + 2.048V voltage reference typical value + 0x2 + + + 4V096 + 4.096V voltage reference typical value + 0x3 + + + + + + + + + TC0 + U22492.0.0 + Basic Timer Counter + TC + TC_ + 0x42003000 + + 0 + 0x38 + registers + + + TC0 + 20 + + + + COUNT8 + 8-bit Counter Mode + TcCount8 + 0x0 + + CTRLA + Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Timer Counter Mode + 2 + 2 + + MODESelect + + COUNT16 + Counter in 16-bit mode + 0 + + + COUNT8 + Counter in 8-bit mode + 1 + + + COUNT32 + Counter in 32-bit mode + 2 + + + + + PRESCSYNC + Prescaler and Counter Synchronization + 4 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset the counter on next generic clock + 0 + + + PRESC + Reload or reset the counter on next prescaler clock + 1 + + + RESYNC + Reload or reset the counter on next generic clock and reset the prescaler counter + 2 + + + + + RUNSTDBY + Run during Standby + 6 + 1 + + + ONDEMAND + Clock On Demand + 7 + 1 + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + Prescaler: GCLK_TC + 0 + + + DIV2 + Prescaler: GCLK_TC/2 + 1 + + + DIV4 + Prescaler: GCLK_TC/4 + 2 + + + DIV8 + Prescaler: GCLK_TC/8 + 3 + + + DIV16 + Prescaler: GCLK_TC/16 + 4 + + + DIV64 + Prescaler: GCLK_TC/64 + 5 + + + DIV256 + Prescaler: GCLK_TC/256 + 6 + + + DIV1024 + Prescaler: GCLK_TC/1024 + 7 + + + + + ALOCK + Auto Lock + 11 + 1 + + + CAPTEN0 + Capture Channel 0 Enable + 16 + 1 + + + CAPTEN1 + Capture Channel 1 Enable + 17 + 1 + + + COPEN0 + Capture On Pin 0 Enable + 20 + 1 + + + COPEN1 + Capture On Pin 1 Enable + 21 + 1 + + + + + CTRLBCLR + Control B Clear + 0x4 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot on Counter + 2 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + UPDATE + Force update of double-buffered register + 3 + + + READSYNC + Force a read synchronization of COUNT + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + CTRLBSET + Control B Set + 0x5 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot on Counter + 2 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + UPDATE + Force update of double-buffered register + 3 + + + READSYNC + Force a read synchronization of COUNT + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + EVCTRL + Event Control + 0x6 + 16 + 0x0000 + + + EVACT + Event Action + 0 + 3 + + EVACTSelect + + OFF + Event action disabled + 0 + + + RETRIGGER + Start, restart or retrigger TC on event + 1 + + + COUNT + Count on event + 2 + + + START + Start TC on event + 3 + + + STAMP + Time stamp capture + 4 + + + PPW + Period catured in CC0, pulse width in CC1 + 5 + + + PWP + Period catured in CC1, pulse width in CC0 + 6 + + + PW + Pulse width capture + 7 + + + + + TCINV + TC Event Input Polarity + 4 + 1 + + + TCEI + TC Event Enable + 5 + 1 + + + OVFEO + Event Output Enable + 8 + 1 + + + MCEO0 + MC Event Output Enable 0 + 12 + 1 + + + MCEO1 + MC Event Output Enable 1 + 13 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x8 + 8 + 0x00 + + + OVF + OVF Interrupt Disable + 0 + 1 + + + ERR + ERR Interrupt Disable + 1 + 1 + + + MC0 + MC Interrupt Disable 0 + 4 + 1 + + + MC1 + MC Interrupt Disable 1 + 5 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x9 + 8 + 0x00 + + + OVF + OVF Interrupt Enable + 0 + 1 + + + ERR + ERR Interrupt Enable + 1 + 1 + + + MC0 + MC Interrupt Enable 0 + 4 + 1 + + + MC1 + MC Interrupt Enable 1 + 5 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0xA + 8 + 0x00 + + + OVF + OVF Interrupt Flag + 0 + 1 + + + ERR + ERR Interrupt Flag + 1 + 1 + + + MC0 + MC Interrupt Flag 0 + 4 + 1 + + + MC1 + MC Interrupt Flag 1 + 5 + 1 + + + + + STATUS + Status + 0xB + 8 + 0x01 + + + STOP + Stop Status Flag + 0 + 1 + + + SLAVE + Slave Status Flag + 1 + 1 + + + PERBUFV + Synchronization Busy Status + 3 + 1 + + + CCBUFV0 + Compare channel buffer 0 valid + 4 + 1 + + + CCBUFV1 + Compare channel buffer 1 valid + 5 + 1 + + + + + WAVE + Waveform Generation Control + 0xC + 8 + 0x00 + + + WAVEGEN + Waveform Generation Mode + 0 + 2 + + WAVEGENSelect + + NFRQ + Normal frequency + 0 + + + MFRQ + Match frequency + 1 + + + NPWM + Normal PWM + 2 + + + MPWM + Match PWM + 3 + + + + + + + DRVCTRL + Control C + 0xD + 8 + 0x00 + + + INVEN0 + Output Waveform Invert Enable 0 + 0 + 1 + + + INVEN1 + Output Waveform Invert Enable 1 + 1 + 1 + + + + + DBGCTRL + Debug Control + 0xF + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + SYNCBUSY + Synchronization Status + 0x10 + 32 + read-only + 0x00000000 + + + SWRST + swrst + 0 + 1 + + + ENABLE + enable + 1 + 1 + + + CTRLB + CTRLB + 2 + 1 + + + STATUS + STATUS + 3 + 1 + + + COUNT + Counter + 4 + 1 + + + PER + Period + 5 + 1 + + + CC0 + Compare Channel 0 + 6 + 1 + + + CC1 + Compare Channel 1 + 7 + 1 + + + + + COUNT + COUNT8 Count + 0x14 + 8 + 0x00 + + + COUNT + Counter Value + 0 + 8 + + + + + PER + COUNT8 Period + 0x1B + 8 + 0xFF + + + PER + Period Value + 0 + 8 + + + + + 2 + 1 + CC[%s] + COUNT8 Compare and Capture + 0x1C + 8 + 0x00 + + + CC + Counter/Compare Value + 0 + 8 + + + + + PERBUF + COUNT8 Period Buffer + 0x2F + 8 + 0xFF + + + PERBUF + Period Buffer Value + 0 + 8 + + + + + 2 + 1 + CCBUF[%s] + COUNT8 Compare and Capture Buffer + 0x30 + 8 + 0x00 + + + CCBUF + Counter/Compare Buffer Value + 0 + 8 + + + + + + COUNT16 + 16-bit Counter Mode + COUNT8 + TcCount16 + 0x0 + + CTRLA + Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Timer Counter Mode + 2 + 2 + + MODESelect + + COUNT16 + Counter in 16-bit mode + 0 + + + COUNT8 + Counter in 8-bit mode + 1 + + + COUNT32 + Counter in 32-bit mode + 2 + + + + + PRESCSYNC + Prescaler and Counter Synchronization + 4 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset the counter on next generic clock + 0 + + + PRESC + Reload or reset the counter on next prescaler clock + 1 + + + RESYNC + Reload or reset the counter on next generic clock and reset the prescaler counter + 2 + + + + + RUNSTDBY + Run during Standby + 6 + 1 + + + ONDEMAND + Clock On Demand + 7 + 1 + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + Prescaler: GCLK_TC + 0 + + + DIV2 + Prescaler: GCLK_TC/2 + 1 + + + DIV4 + Prescaler: GCLK_TC/4 + 2 + + + DIV8 + Prescaler: GCLK_TC/8 + 3 + + + DIV16 + Prescaler: GCLK_TC/16 + 4 + + + DIV64 + Prescaler: GCLK_TC/64 + 5 + + + DIV256 + Prescaler: GCLK_TC/256 + 6 + + + DIV1024 + Prescaler: GCLK_TC/1024 + 7 + + + + + ALOCK + Auto Lock + 11 + 1 + + + CAPTEN0 + Capture Channel 0 Enable + 16 + 1 + + + CAPTEN1 + Capture Channel 1 Enable + 17 + 1 + + + COPEN0 + Capture On Pin 0 Enable + 20 + 1 + + + COPEN1 + Capture On Pin 1 Enable + 21 + 1 + + + + + CTRLBCLR + Control B Clear + 0x4 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot on Counter + 2 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + UPDATE + Force update of double-buffered register + 3 + + + READSYNC + Force a read synchronization of COUNT + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + CTRLBSET + Control B Set + 0x5 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot on Counter + 2 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + UPDATE + Force update of double-buffered register + 3 + + + READSYNC + Force a read synchronization of COUNT + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + EVCTRL + Event Control + 0x6 + 16 + 0x0000 + + + EVACT + Event Action + 0 + 3 + + EVACTSelect + + OFF + Event action disabled + 0 + + + RETRIGGER + Start, restart or retrigger TC on event + 1 + + + COUNT + Count on event + 2 + + + START + Start TC on event + 3 + + + STAMP + Time stamp capture + 4 + + + PPW + Period catured in CC0, pulse width in CC1 + 5 + + + PWP + Period catured in CC1, pulse width in CC0 + 6 + + + PW + Pulse width capture + 7 + + + + + TCINV + TC Event Input Polarity + 4 + 1 + + + TCEI + TC Event Enable + 5 + 1 + + + OVFEO + Event Output Enable + 8 + 1 + + + MCEO0 + MC Event Output Enable 0 + 12 + 1 + + + MCEO1 + MC Event Output Enable 1 + 13 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x8 + 8 + 0x00 + + + OVF + OVF Interrupt Disable + 0 + 1 + + + ERR + ERR Interrupt Disable + 1 + 1 + + + MC0 + MC Interrupt Disable 0 + 4 + 1 + + + MC1 + MC Interrupt Disable 1 + 5 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x9 + 8 + 0x00 + + + OVF + OVF Interrupt Enable + 0 + 1 + + + ERR + ERR Interrupt Enable + 1 + 1 + + + MC0 + MC Interrupt Enable 0 + 4 + 1 + + + MC1 + MC Interrupt Enable 1 + 5 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0xA + 8 + 0x00 + + + OVF + OVF Interrupt Flag + 0 + 1 + + + ERR + ERR Interrupt Flag + 1 + 1 + + + MC0 + MC Interrupt Flag 0 + 4 + 1 + + + MC1 + MC Interrupt Flag 1 + 5 + 1 + + + + + STATUS + Status + 0xB + 8 + 0x01 + + + STOP + Stop Status Flag + 0 + 1 + + + SLAVE + Slave Status Flag + 1 + 1 + + + PERBUFV + Synchronization Busy Status + 3 + 1 + + + CCBUFV0 + Compare channel buffer 0 valid + 4 + 1 + + + CCBUFV1 + Compare channel buffer 1 valid + 5 + 1 + + + + + WAVE + Waveform Generation Control + 0xC + 8 + 0x00 + + + WAVEGEN + Waveform Generation Mode + 0 + 2 + + WAVEGENSelect + + NFRQ + Normal frequency + 0 + + + MFRQ + Match frequency + 1 + + + NPWM + Normal PWM + 2 + + + MPWM + Match PWM + 3 + + + + + + + DRVCTRL + Control C + 0xD + 8 + 0x00 + + + INVEN0 + Output Waveform Invert Enable 0 + 0 + 1 + + + INVEN1 + Output Waveform Invert Enable 1 + 1 + 1 + + + + + DBGCTRL + Debug Control + 0xF + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + SYNCBUSY + Synchronization Status + 0x10 + 32 + read-only + 0x00000000 + + + SWRST + swrst + 0 + 1 + + + ENABLE + enable + 1 + 1 + + + CTRLB + CTRLB + 2 + 1 + + + STATUS + STATUS + 3 + 1 + + + COUNT + Counter + 4 + 1 + + + PER + Period + 5 + 1 + + + CC0 + Compare Channel 0 + 6 + 1 + + + CC1 + Compare Channel 1 + 7 + 1 + + + + + COUNT + COUNT16 Count + 0x14 + 16 + 0x0000 + + + COUNT + Counter Value + 0 + 16 + + + + + 2 + 2 + CC[%s] + COUNT16 Compare and Capture + 0x1C + 16 + 0x0000 + + + CC + Counter/Compare Value + 0 + 16 + + + + + 2 + 2 + CCBUF[%s] + COUNT16 Compare and Capture Buffer + 0x30 + 16 + 0x0000 + + + CCBUF + Counter/Compare Buffer Value + 0 + 16 + + + + + + COUNT32 + 32-bit Counter Mode + COUNT8 + TcCount32 + 0x0 + + CTRLA + Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Timer Counter Mode + 2 + 2 + + MODESelect + + COUNT16 + Counter in 16-bit mode + 0 + + + COUNT8 + Counter in 8-bit mode + 1 + + + COUNT32 + Counter in 32-bit mode + 2 + + + + + PRESCSYNC + Prescaler and Counter Synchronization + 4 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset the counter on next generic clock + 0 + + + PRESC + Reload or reset the counter on next prescaler clock + 1 + + + RESYNC + Reload or reset the counter on next generic clock and reset the prescaler counter + 2 + + + + + RUNSTDBY + Run during Standby + 6 + 1 + + + ONDEMAND + Clock On Demand + 7 + 1 + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + Prescaler: GCLK_TC + 0 + + + DIV2 + Prescaler: GCLK_TC/2 + 1 + + + DIV4 + Prescaler: GCLK_TC/4 + 2 + + + DIV8 + Prescaler: GCLK_TC/8 + 3 + + + DIV16 + Prescaler: GCLK_TC/16 + 4 + + + DIV64 + Prescaler: GCLK_TC/64 + 5 + + + DIV256 + Prescaler: GCLK_TC/256 + 6 + + + DIV1024 + Prescaler: GCLK_TC/1024 + 7 + + + + + ALOCK + Auto Lock + 11 + 1 + + + CAPTEN0 + Capture Channel 0 Enable + 16 + 1 + + + CAPTEN1 + Capture Channel 1 Enable + 17 + 1 + + + COPEN0 + Capture On Pin 0 Enable + 20 + 1 + + + COPEN1 + Capture On Pin 1 Enable + 21 + 1 + + + + + CTRLBCLR + Control B Clear + 0x4 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot on Counter + 2 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + UPDATE + Force update of double-buffered register + 3 + + + READSYNC + Force a read synchronization of COUNT + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + CTRLBSET + Control B Set + 0x5 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot on Counter + 2 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + UPDATE + Force update of double-buffered register + 3 + + + READSYNC + Force a read synchronization of COUNT + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + EVCTRL + Event Control + 0x6 + 16 + 0x0000 + + + EVACT + Event Action + 0 + 3 + + EVACTSelect + + OFF + Event action disabled + 0 + + + RETRIGGER + Start, restart or retrigger TC on event + 1 + + + COUNT + Count on event + 2 + + + START + Start TC on event + 3 + + + STAMP + Time stamp capture + 4 + + + PPW + Period catured in CC0, pulse width in CC1 + 5 + + + PWP + Period catured in CC1, pulse width in CC0 + 6 + + + PW + Pulse width capture + 7 + + + + + TCINV + TC Event Input Polarity + 4 + 1 + + + TCEI + TC Event Enable + 5 + 1 + + + OVFEO + Event Output Enable + 8 + 1 + + + MCEO0 + MC Event Output Enable 0 + 12 + 1 + + + MCEO1 + MC Event Output Enable 1 + 13 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x8 + 8 + 0x00 + + + OVF + OVF Interrupt Disable + 0 + 1 + + + ERR + ERR Interrupt Disable + 1 + 1 + + + MC0 + MC Interrupt Disable 0 + 4 + 1 + + + MC1 + MC Interrupt Disable 1 + 5 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x9 + 8 + 0x00 + + + OVF + OVF Interrupt Enable + 0 + 1 + + + ERR + ERR Interrupt Enable + 1 + 1 + + + MC0 + MC Interrupt Enable 0 + 4 + 1 + + + MC1 + MC Interrupt Enable 1 + 5 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0xA + 8 + 0x00 + + + OVF + OVF Interrupt Flag + 0 + 1 + + + ERR + ERR Interrupt Flag + 1 + 1 + + + MC0 + MC Interrupt Flag 0 + 4 + 1 + + + MC1 + MC Interrupt Flag 1 + 5 + 1 + + + + + STATUS + Status + 0xB + 8 + 0x01 + + + STOP + Stop Status Flag + 0 + 1 + + + SLAVE + Slave Status Flag + 1 + 1 + + + PERBUFV + Synchronization Busy Status + 3 + 1 + + + CCBUFV0 + Compare channel buffer 0 valid + 4 + 1 + + + CCBUFV1 + Compare channel buffer 1 valid + 5 + 1 + + + + + WAVE + Waveform Generation Control + 0xC + 8 + 0x00 + + + WAVEGEN + Waveform Generation Mode + 0 + 2 + + WAVEGENSelect + + NFRQ + Normal frequency + 0 + + + MFRQ + Match frequency + 1 + + + NPWM + Normal PWM + 2 + + + MPWM + Match PWM + 3 + + + + + + + DRVCTRL + Control C + 0xD + 8 + 0x00 + + + INVEN0 + Output Waveform Invert Enable 0 + 0 + 1 + + + INVEN1 + Output Waveform Invert Enable 1 + 1 + 1 + + + + + DBGCTRL + Debug Control + 0xF + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + SYNCBUSY + Synchronization Status + 0x10 + 32 + read-only + 0x00000000 + + + SWRST + swrst + 0 + 1 + + + ENABLE + enable + 1 + 1 + + + CTRLB + CTRLB + 2 + 1 + + + STATUS + STATUS + 3 + 1 + + + COUNT + Counter + 4 + 1 + + + PER + Period + 5 + 1 + + + CC0 + Compare Channel 0 + 6 + 1 + + + CC1 + Compare Channel 1 + 7 + 1 + + + + + COUNT + COUNT32 Count + 0x14 + 32 + 0x00000000 + + + COUNT + Counter Value + 0 + 32 + + + + + 2 + 4 + CC[%s] + COUNT32 Compare and Capture + 0x1C + 32 + 0x00000000 + + + CC + Counter/Compare Value + 0 + 32 + + + + + 2 + 4 + CCBUF[%s] + COUNT32 Compare and Capture Buffer + 0x30 + 32 + 0x00000000 + + + CCBUF + Counter/Compare Buffer Value + 0 + 32 + + + + + + + + TC1 + 0x42003400 + + TC1 + 21 + + + + TC2 + 0x42003800 + + TC2 + 22 + + + + TC3 + 0x42003C00 + + TC3 + 23 + + + + TC4 + 0x42004000 + + TC4 + 24 + + + + TCC0 + U22133.0.0 + Timer Counter Control + TCC + TCC_ + 0x42002400 + + 0 + 0x80 + registers + + + TCC0 + 17 + + + + CTRLA + Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + RESOLUTION + Enhanced Resolution + 5 + 2 + + RESOLUTIONSelect + + NONE + Dithering is disabled + 0 + + + DITH4 + Dithering is done every 16 PWM frames + 1 + + + DITH5 + Dithering is done every 32 PWM frames + 2 + + + DITH6 + Dithering is done every 64 PWM frames + 3 + + + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + No division + 0 + + + DIV2 + Divide by 2 + 1 + + + DIV4 + Divide by 4 + 2 + + + DIV8 + Divide by 8 + 3 + + + DIV16 + Divide by 16 + 4 + + + DIV64 + Divide by 64 + 5 + + + DIV256 + Divide by 256 + 6 + + + DIV1024 + Divide by 1024 + 7 + + + + + RUNSTDBY + Run in Standby + 11 + 1 + + + PRESCSYNC + Prescaler and Counter Synchronization Selection + 12 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset counter on next GCLK + 0 + + + PRESC + Reload or reset counter on next prescaler clock + 1 + + + RESYNC + Reload or reset counter on next GCLK and reset prescaler counter + 2 + + + + + ALOCK + Auto Lock + 14 + 1 + + + MSYNC + Master Synchronization (only for TCC Slave Instance) + 15 + 1 + + + DMAOS + DMA One-shot Trigger Mode + 23 + 1 + + + CPTEN0 + Capture Channel 0 Enable + 24 + 1 + + + CPTEN1 + Capture Channel 1 Enable + 25 + 1 + + + CPTEN2 + Capture Channel 2 Enable + 26 + 1 + + + CPTEN3 + Capture Channel 3 Enable + 27 + 1 + + + + + CTRLBCLR + Control B Clear + 0x4 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + IDXCMD + Ramp Index Command + 3 + 2 + + IDXCMDSelect + + DISABLE + Command disabled: Index toggles between cycles A and B + 0 + + + SET + Set index: cycle B will be forced in the next cycle + 1 + + + CLEAR + Clear index: cycle A will be forced in the next cycle + 2 + + + HOLD + Hold index: the next cycle will be the same as the current cycle + 3 + + + + + CMD + TCC Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Clear start, restart or retrigger + 1 + + + STOP + Force stop + 2 + + + UPDATE + Force update or double buffered registers + 3 + + + READSYNC + Force COUNT read synchronization + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + CTRLBSET + Control B Set + 0x5 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + IDXCMD + Ramp Index Command + 3 + 2 + + IDXCMDSelect + + DISABLE + Command disabled: Index toggles between cycles A and B + 0 + + + SET + Set index: cycle B will be forced in the next cycle + 1 + + + CLEAR + Clear index: cycle A will be forced in the next cycle + 2 + + + HOLD + Hold index: the next cycle will be the same as the current cycle + 3 + + + + + CMD + TCC Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Clear start, restart or retrigger + 1 + + + STOP + Force stop + 2 + + + UPDATE + Force update or double buffered registers + 3 + + + READSYNC + Force COUNT read synchronization + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + SYNCBUSY + Synchronization Busy + 0x8 + 32 + read-only + 0x00000000 + + + SWRST + Swrst Busy + 0 + 1 + + + ENABLE + Enable Busy + 1 + 1 + + + CTRLB + Ctrlb Busy + 2 + 1 + + + STATUS + Status Busy + 3 + 1 + + + COUNT + Count Busy + 4 + 1 + + + PATT + Pattern Busy + 5 + 1 + + + WAVE + Wave Busy + 6 + 1 + + + PER + Period Busy + 7 + 1 + + + CC0 + Compare Channel 0 Busy + 8 + 1 + + + CC1 + Compare Channel 1 Busy + 9 + 1 + + + CC2 + Compare Channel 2 Busy + 10 + 1 + + + CC3 + Compare Channel 3 Busy + 11 + 1 + + + + + FCTRLA + Recoverable Fault A Configuration + 0xC + 32 + 0x00000000 + + + SRC + Fault A Source + 0 + 2 + + SRCSelect + + DISABLE + Fault input disabled + 0 + + + ENABLE + MCEx (x=0,1) event input + 1 + + + INVERT + Inverted MCEx (x=0,1) event input + 2 + + + ALTFAULT + Alternate fault (A or B) state at the end of the previous period + 3 + + + + + KEEP + Fault A Keeper + 3 + 1 + + + QUAL + Fault A Qualification + 4 + 1 + + + BLANK + Fault A Blanking Mode + 5 + 2 + + BLANKSelect + + START + Blanking applied from start of the ramp + 0 + + + RISE + Blanking applied from rising edge of the output waveform + 1 + + + FALL + Blanking applied from falling edge of the output waveform + 2 + + + BOTH + Blanking applied from each toggle of the output waveform + 3 + + + + + RESTART + Fault A Restart + 7 + 1 + + + HALT + Fault A Halt Mode + 8 + 2 + + HALTSelect + + DISABLE + Halt action disabled + 0 + + + HW + Hardware halt action + 1 + + + SW + Software halt action + 2 + + + NR + Non-recoverable fault + 3 + + + + + CHSEL + Fault A Capture Channel + 10 + 2 + + CHSELSelect + + CC0 + Capture value stored in channel 0 + 0 + + + CC1 + Capture value stored in channel 1 + 1 + + + CC2 + Capture value stored in channel 2 + 2 + + + CC3 + Capture value stored in channel 3 + 3 + + + + + CAPTURE + Fault A Capture Action + 12 + 3 + + CAPTURESelect + + DISABLE + No capture + 0 + + + CAPT + Capture on fault + 1 + + + CAPTMIN + Minimum capture + 2 + + + CAPTMAX + Maximum capture + 3 + + + LOCMIN + Minimum local detection + 4 + + + LOCMAX + Maximum local detection + 5 + + + DERIV0 + Minimum and maximum local detection + 6 + + + CAPTMARK + Capture with ramp index as MSB value + 7 + + + + + BLANKPRESC + Fault A Blanking Prescaler + 15 + 1 + + + BLANKVAL + Fault A Blanking Time + 16 + 8 + + + FILTERVAL + Fault A Filter Value + 24 + 4 + + + + + FCTRLB + Recoverable Fault B Configuration + 0x10 + 32 + 0x00000000 + + + SRC + Fault B Source + 0 + 2 + + SRCSelect + + DISABLE + Fault input disabled + 0 + + + ENABLE + MCEx (x=0,1) event input + 1 + + + INVERT + Inverted MCEx (x=0,1) event input + 2 + + + ALTFAULT + Alternate fault (A or B) state at the end of the previous period + 3 + + + + + KEEP + Fault B Keeper + 3 + 1 + + + QUAL + Fault B Qualification + 4 + 1 + + + BLANK + Fault B Blanking Mode + 5 + 2 + + BLANKSelect + + START + Blanking applied from start of the ramp + 0 + + + RISE + Blanking applied from rising edge of the output waveform + 1 + + + FALL + Blanking applied from falling edge of the output waveform + 2 + + + BOTH + Blanking applied from each toggle of the output waveform + 3 + + + + + RESTART + Fault B Restart + 7 + 1 + + + HALT + Fault B Halt Mode + 8 + 2 + + HALTSelect + + DISABLE + Halt action disabled + 0 + + + HW + Hardware halt action + 1 + + + SW + Software halt action + 2 + + + NR + Non-recoverable fault + 3 + + + + + CHSEL + Fault B Capture Channel + 10 + 2 + + CHSELSelect + + CC0 + Capture value stored in channel 0 + 0 + + + CC1 + Capture value stored in channel 1 + 1 + + + CC2 + Capture value stored in channel 2 + 2 + + + CC3 + Capture value stored in channel 3 + 3 + + + + + CAPTURE + Fault B Capture Action + 12 + 3 + + CAPTURESelect + + DISABLE + No capture + 0 + + + CAPT + Capture on fault + 1 + + + CAPTMIN + Minimum capture + 2 + + + CAPTMAX + Maximum capture + 3 + + + LOCMIN + Minimum local detection + 4 + + + LOCMAX + Maximum local detection + 5 + + + DERIV0 + Minimum and maximum local detection + 6 + + + CAPTMARK + Capture with ramp index as MSB value + 7 + + + + + BLANKPRESC + Fault B Blanking Prescaler + 15 + 1 + + + BLANKVAL + Fault B Blanking Time + 16 + 8 + + + FILTERVAL + Fault B Filter Value + 24 + 4 + + + + + WEXCTRL + Waveform Extension Configuration + 0x14 + 32 + 0x00000000 + + + OTMX + Output Matrix + 0 + 2 + + + DTIEN0 + Dead-time Insertion Generator 0 Enable + 8 + 1 + + + DTIEN1 + Dead-time Insertion Generator 1 Enable + 9 + 1 + + + DTIEN2 + Dead-time Insertion Generator 2 Enable + 10 + 1 + + + DTIEN3 + Dead-time Insertion Generator 3 Enable + 11 + 1 + + + DTLS + Dead-time Low Side Outputs Value + 16 + 8 + + + DTHS + Dead-time High Side Outputs Value + 24 + 8 + + + + + DRVCTRL + Driver Control + 0x18 + 32 + 0x00000000 + + + NRE0 + Non-Recoverable State 0 Output Enable + 0 + 1 + + + NRE1 + Non-Recoverable State 1 Output Enable + 1 + 1 + + + NRE2 + Non-Recoverable State 2 Output Enable + 2 + 1 + + + NRE3 + Non-Recoverable State 3 Output Enable + 3 + 1 + + + NRE4 + Non-Recoverable State 4 Output Enable + 4 + 1 + + + NRE5 + Non-Recoverable State 5 Output Enable + 5 + 1 + + + NRE6 + Non-Recoverable State 6 Output Enable + 6 + 1 + + + NRE7 + Non-Recoverable State 7 Output Enable + 7 + 1 + + + NRV0 + Non-Recoverable State 0 Output Value + 8 + 1 + + + NRV1 + Non-Recoverable State 1 Output Value + 9 + 1 + + + NRV2 + Non-Recoverable State 2 Output Value + 10 + 1 + + + NRV3 + Non-Recoverable State 3 Output Value + 11 + 1 + + + NRV4 + Non-Recoverable State 4 Output Value + 12 + 1 + + + NRV5 + Non-Recoverable State 5 Output Value + 13 + 1 + + + NRV6 + Non-Recoverable State 6 Output Value + 14 + 1 + + + NRV7 + Non-Recoverable State 7 Output Value + 15 + 1 + + + INVEN0 + Output Waveform 0 Inversion + 16 + 1 + + + INVEN1 + Output Waveform 1 Inversion + 17 + 1 + + + INVEN2 + Output Waveform 2 Inversion + 18 + 1 + + + INVEN3 + Output Waveform 3 Inversion + 19 + 1 + + + INVEN4 + Output Waveform 4 Inversion + 20 + 1 + + + INVEN5 + Output Waveform 5 Inversion + 21 + 1 + + + INVEN6 + Output Waveform 6 Inversion + 22 + 1 + + + INVEN7 + Output Waveform 7 Inversion + 23 + 1 + + + FILTERVAL0 + Non-Recoverable Fault Input 0 Filter Value + 24 + 4 + + + FILTERVAL1 + Non-Recoverable Fault Input 1 Filter Value + 28 + 4 + + + + + DBGCTRL + Debug Control + 0x1E + 8 + 0x00 + + + DBGRUN + Debug Running Mode + 0 + 1 + + + FDDBD + Fault Detection on Debug Break Detection + 2 + 1 + + + + + EVCTRL + Event Control + 0x20 + 32 + 0x00000000 + + + EVACT0 + Timer/counter Input Event0 Action + 0 + 3 + + EVACT0Select + + OFF + Event action disabled + 0 + + + RETRIGGER + Start, restart or re-trigger counter on event + 1 + + + COUNTEV + Count on event + 2 + + + START + Start counter on event + 3 + + + INC + Increment counter on event + 4 + + + COUNT + Count on active state of asynchronous event + 5 + + + STAMP + Stamp capture + 6 + + + FAULT + Non-recoverable fault + 7 + + + + + EVACT1 + Timer/counter Input Event1 Action + 3 + 3 + + EVACT1Select + + OFF + Event action disabled + 0 + + + RETRIGGER + Re-trigger counter on event + 1 + + + DIR + Direction control + 2 + + + STOP + Stop counter on event + 3 + + + DEC + Decrement counter on event + 4 + + + PPW + Period capture value in CC0 register, pulse width capture value in CC1 register + 5 + + + PWP + Period capture value in CC1 register, pulse width capture value in CC0 register + 6 + + + FAULT + Non-recoverable fault + 7 + + + + + CNTSEL + Timer/counter Output Event Mode + 6 + 2 + + CNTSELSelect + + START + An interrupt/event is generated when a new counter cycle starts + 0 + + + END + An interrupt/event is generated when a counter cycle ends + 1 + + + BETWEEN + An interrupt/event is generated when a counter cycle ends, except for the first and last cycles + 2 + + + BOUNDARY + An interrupt/event is generated when a new counter cycle starts or a counter cycle ends + 3 + + + + + OVFEO + Overflow/Underflow Output Event Enable + 8 + 1 + + + TRGEO + Retrigger Output Event Enable + 9 + 1 + + + CNTEO + Timer/counter Output Event Enable + 10 + 1 + + + TCINV0 + Inverted Event 0 Input Enable + 12 + 1 + + + TCINV1 + Inverted Event 1 Input Enable + 13 + 1 + + + TCEI0 + Timer/counter Event 0 Input Enable + 14 + 1 + + + TCEI1 + Timer/counter Event 1 Input Enable + 15 + 1 + + + MCEI0 + Match or Capture Channel 0 Event Input Enable + 16 + 1 + + + MCEI1 + Match or Capture Channel 1 Event Input Enable + 17 + 1 + + + MCEI2 + Match or Capture Channel 2 Event Input Enable + 18 + 1 + + + MCEI3 + Match or Capture Channel 3 Event Input Enable + 19 + 1 + + + MCEO0 + Match or Capture Channel 0 Event Output Enable + 24 + 1 + + + MCEO1 + Match or Capture Channel 1 Event Output Enable + 25 + 1 + + + MCEO2 + Match or Capture Channel 2 Event Output Enable + 26 + 1 + + + MCEO3 + Match or Capture Channel 3 Event Output Enable + 27 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x24 + 32 + 0x00000000 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + TRG + Retrigger Interrupt Enable + 1 + 1 + + + CNT + Counter Interrupt Enable + 2 + 1 + + + ERR + Error Interrupt Enable + 3 + 1 + + + UFS + Non-Recoverable Update Fault Interrupt Enable + 10 + 1 + + + DFS + Non-Recoverable Debug Fault Interrupt Enable + 11 + 1 + + + FAULTA + Recoverable Fault A Interrupt Enable + 12 + 1 + + + FAULTB + Recoverable Fault B Interrupt Enable + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 Interrupt Enable + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 Interrupt Enable + 15 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 16 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 17 + 1 + + + MC2 + Match or Capture Channel 2 Interrupt Enable + 18 + 1 + + + MC3 + Match or Capture Channel 3 Interrupt Enable + 19 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x28 + 32 + 0x00000000 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + TRG + Retrigger Interrupt Enable + 1 + 1 + + + CNT + Counter Interrupt Enable + 2 + 1 + + + ERR + Error Interrupt Enable + 3 + 1 + + + UFS + Non-Recoverable Update Fault Interrupt Enable + 10 + 1 + + + DFS + Non-Recoverable Debug Fault Interrupt Enable + 11 + 1 + + + FAULTA + Recoverable Fault A Interrupt Enable + 12 + 1 + + + FAULTB + Recoverable Fault B Interrupt Enable + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 Interrupt Enable + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 Interrupt Enable + 15 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 16 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 17 + 1 + + + MC2 + Match or Capture Channel 2 Interrupt Enable + 18 + 1 + + + MC3 + Match or Capture Channel 3 Interrupt Enable + 19 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x2C + 32 + 0x00000000 + + + OVF + Overflow + 0 + 1 + + + TRG + Retrigger + 1 + 1 + + + CNT + Counter + 2 + 1 + + + ERR + Error + 3 + 1 + + + UFS + Non-Recoverable Update Fault + 10 + 1 + + + DFS + Non-Recoverable Debug Fault + 11 + 1 + + + FAULTA + Recoverable Fault A + 12 + 1 + + + FAULTB + Recoverable Fault B + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 + 15 + 1 + + + MC0 + Match or Capture 0 + 16 + 1 + + + MC1 + Match or Capture 1 + 17 + 1 + + + MC2 + Match or Capture 2 + 18 + 1 + + + MC3 + Match or Capture 3 + 19 + 1 + + + + + STATUS + Status + 0x30 + 32 + 0x00000001 + + + STOP + Stop + 0 + 1 + + + IDX + Ramp + 1 + 1 + + + UFS + Non-recoverable Update Fault State + 2 + 1 + + + DFS + Non-Recoverable Debug Fault State + 3 + 1 + + + SLAVE + Slave + 4 + 1 + + + PATTBUFV + Pattern Buffer Valid + 5 + 1 + + + PERBUFV + Period Buffer Valid + 7 + 1 + + + FAULTAIN + Recoverable Fault A Input + 8 + 1 + + + FAULTBIN + Recoverable Fault B Input + 9 + 1 + + + FAULT0IN + Non-Recoverable Fault0 Input + 10 + 1 + + + FAULT1IN + Non-Recoverable Fault1 Input + 11 + 1 + + + FAULTA + Recoverable Fault A State + 12 + 1 + + + FAULTB + Recoverable Fault B State + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 State + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 State + 15 + 1 + + + CCBUFV0 + Compare Channel 0 Buffer Valid + 16 + 1 + + + CCBUFV1 + Compare Channel 1 Buffer Valid + 17 + 1 + + + CCBUFV2 + Compare Channel 2 Buffer Valid + 18 + 1 + + + CCBUFV3 + Compare Channel 3 Buffer Valid + 19 + 1 + + + CMP0 + Compare Channel 0 Value + 24 + 1 + + + CMP1 + Compare Channel 1 Value + 25 + 1 + + + CMP2 + Compare Channel 2 Value + 26 + 1 + + + CMP3 + Compare Channel 3 Value + 27 + 1 + + + + + COUNT + Count + 0x34 + 32 + 0x00000000 + + + COUNT + Counter Value + 0 + 24 + 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Enable + 2 + 1 + + + OVF + Overflow Interrupt Enable + 3 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear Register + 0x6 + 8 + 0x00 + + + RESRDY + Result Ready + 0 + 1 + + + OVERRUN + Overrun + 1 + 1 + + + WINMON + Window Monitor + 2 + 1 + + + OVF + Overflow + 3 + 1 + + + + + STATUS + Status Register + 0x7 + 8 + read-only + 0x00 + + + OVF + Result Overflow + 0 + 1 + + + + + SYNCBUSY + Synchronization Busy Register + 0x8 + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Busy + 0 + 1 + + + ENABLE + Enable Busy + 1 + 1 + + + + + VALUE + Value Register + 0xC + 32 + read-only + 0x00000000 + + + VALUE + Measurement Value + 0 + 24 + + + + + WINLT + Window Monitor Lower Threshold Register + 0x10 + 32 + 0x00000000 + + + WINLT + Window Lower Threshold + 0 + 24 + + + + + WINUT + Window Monitor Upper Threshold Register + 0x14 + 32 + 0x00000000 + + + WINUT + Window Upper Threshold + 0 + 24 + + + + + GAIN + Gain Register + 0x18 + 32 + 0x00000000 + + + GAIN + Time Amplifier Gain + 0 + 24 + + + + + OFFSET + Offset Register + 0x1C + 32 + 0x00000000 + + + OFFSETC + Offset Correction + 0 + 24 + + + + + CAL + Calibration Register + 0x20 + 32 + 0x00000000 + + + FCAL + Frequency Calibration + 0 + 6 + + + TCAL + Temperature Calibration + 8 + 6 + + + + + DBGCTRL + Debug Control Register + 0x24 + 8 + 0x00 + + + DBGRUN + Debug Run + 0 + 1 + + + + + + + WDT + U22511.0.1 + Watchdog Timer + WDT + WDT_ + 0x40002000 + + 0 + 0xD + registers + + + WDT + 1 + + + + CTRLA + Control + 0x0 + 8 + 0x00 + + + ENABLE + Enable + 1 + 1 + + + WEN + Watchdog Timer Window Mode Enable + 2 + 1 + + + ALWAYSON + Always-On + 7 + 1 + + + + + CONFIG + Configuration + 0x1 + 8 + 0xBB + + + PER + Time-Out Period + 0 + 4 + + PERSelect + + CYC8 + 8 clock cycles + 0x0 + + + CYC16 + 16 clock cycles + 0x1 + + + CYC32 + 32 clock cycles + 0x2 + + + CYC64 + 64 clock cycles + 0x3 + + + CYC128 + 128 clock cycles + 0x4 + + + CYC256 + 256 clock cycles + 0x5 + + + CYC512 + 512 clock cycles + 0x6 + + + CYC1024 + 1024 clock cycles + 0x7 + + + CYC2048 + 2048 clock cycles + 0x8 + + + CYC4096 + 4096 clock cycles + 0x9 + + + CYC8192 + 8192 clock cycles + 0xA + + + CYC16384 + 16384 clock cycles + 0xB + + + + + WINDOW + Window Mode Time-Out Period + 4 + 4 + + WINDOWSelect + + CYC8 + 8 clock cycles + 0x0 + + + CYC16 + 16 clock cycles + 0x1 + + + CYC32 + 32 clock cycles + 0x2 + + + CYC64 + 64 clock cycles + 0x3 + + + CYC128 + 128 clock cycles + 0x4 + + + CYC256 + 256 clock cycles + 0x5 + + + CYC512 + 512 clock cycles + 0x6 + + + CYC1024 + 1024 clock cycles + 0x7 + + + CYC2048 + 2048 clock cycles + 0x8 + + + CYC4096 + 4096 clock cycles + 0x9 + + + CYC8192 + 8192 clock cycles + 0xA + + + CYC16384 + 16384 clock cycles + 0xB + + + + + + + EWCTRL + Early Warning Interrupt Control + 0x2 + 8 + 0x0B + + + EWOFFSET + Early Warning Interrupt Time Offset + 0 + 4 + + EWOFFSETSelect + + CYC8 + 8 clock cycles + 0x0 + + + CYC16 + 16 clock cycles + 0x1 + + + CYC32 + 32 clock cycles + 0x2 + + + CYC64 + 64 clock cycles + 0x3 + + + CYC128 + 128 clock cycles + 0x4 + + + CYC256 + 256 clock cycles + 0x5 + + + CYC512 + 512 clock cycles + 0x6 + + + CYC1024 + 1024 clock cycles + 0x7 + + + CYC2048 + 2048 clock cycles + 0x8 + + + CYC4096 + 4096 clock cycles + 0x9 + + + CYC8192 + 8192 clock cycles + 0xA + + + CYC16384 + 16384 clock cycles + 0xB + + + + + + + INTENCLR + Interrupt Enable Clear + 0x4 + 8 + 0x00 + + + EW + Early Warning Interrupt Enable + 0 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x5 + 8 + 0x00 + + + EW + Early Warning Interrupt Enable + 0 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x6 + 8 + 0x00 + + + EW + Early Warning + 0 + 1 + + + + + SYNCBUSY + Synchronization Busy + 0x8 + 32 + read-only + 0x00000000 + + + ENABLE + Enable Busy + 1 + 1 + + + WEN + Window Enable Busy + 2 + 1 + + + ALWAYSON + Always-On Busy + 3 + 1 + + + CLEAR + Clear Busy + 4 + 1 + + + + + CLEAR + Clear + 0xC + 8 + write-only + 0x00 + + + CLEAR + Watchdog Clear + 0 + 8 + + CLEARSelect + + KEY + Clear Key + 0xA5 + + + + + + + + + MPU + Memory Protection Unit + MPU + MPU_ + 0xE000ED90 + + 0 + 0x14 + registers + + + + TYPE + MPU Type Register + 0x0 + 32 + read-only + + + SEPARATE + Separate instruction and Data Memory MapsRegions + 0 + 1 + + + DREGION + Number of Data Regions + 8 + 8 + + + IREGION + Number of Instruction Regions + 16 + 8 + + + + + CTRL + MPU Control Register + 0x4 + 32 + + + ENABLE + MPU Enable + 0 + 1 + + + HFNMIENA + Enable Hard Fault and NMI handlers + 1 + 1 + + + PRIVDEFENA + Enables privileged software access to default memory map + 2 + 1 + + + + + RNR + MPU Region Number Register + 0x8 + 32 + + + REGION + Region referenced by RBAR and RASR + 0 + 8 + + + + + RBAR + MPU Region Base Address Register + 0xC + 32 + + + REGION + Region number + 0 + 4 + + + VALID + Region number valid + 4 + 1 + + + ADDR + Region base address + 5 + 27 + + + + + RASR + MPU Region Attribute and Size Register + 0x10 + 32 + + + ENABLE + Region Enable + 0 + 1 + + + SIZE + Region Size + 1 + 5 + + + SRD + Sub-region disable + 8 + 8 + + + B + Bufferable bit + 16 + 1 + + + C + Cacheable bit + 17 + 1 + + + S + Shareable bit + 18 + 1 + + + TEX + TEX bit + 19 + 3 + + + AP + Access Permission + 24 + 3 + + + XN + Execute Never Attribute + 28 + 1 + + + + + + + NVIC + Nested Vectored Interrupt Controller + NVIC + NVIC_ + 0xE000E100 + + 0 + 0x320 + registers + + + + ISER + Interrupt Set Enable Register + 0x0 + 32 + 0x00000000 + + + SETENA + Interrupt set enable bits + 0 + 31 + + + + + ICER + Interrupt Clear Enable Register + 0x80 + 32 + 0x00000000 + + + CLRENA + Interrupt clear-enable bits + 0 + 31 + + + + + ISPR + Interrupt Set Pending Register + 0x100 + 32 + 0x00000000 + + + SETPEND + Interrupt set-pending bits + 0 + 31 + + + + + ICPR + Interrupt Clear Pending Register + 0x180 + 32 + 0x00000000 + + + CLRPEND + Interrupt clear-pending bits + 0 + 31 + + + + + 8 + 4 + IPR[%s] + Interrupt Priority Register n + 0x300 + 32 + 0x00000000 + + + PRI0 + Priority of interrupt n + 0 + 2 + + + PRI1 + Priority of interrupt n + 8 + 2 + + + PRI2 + Priority of interrupt n + 16 + 2 + + + PRI3 + Priority of interrupt n + 24 + 2 + + + + + + + SysTick + System timer + SysTick + SysTick_ + 0xE000E010 + + 0 + 0x10 + registers + + + + CSR + SysTick Control and Status Register + 0x0 + 32 + 0x4 + + + ENABLE + SysTick Counter Enable + 0 + 1 + + ENABLESelect + + VALUE_0 + Counter disabled + 0 + + + VALUE_1 + Counter enabled + 1 + + + + + TICKINT + SysTick Exception Request Enable + 1 + 1 + + TICKINTSelect + + VALUE_0 + Counting down to 0 does not assert the SysTick exception request + 0 + + + VALUE_1 + Counting down to 0 asserts the SysTick exception request + 1 + + + + + CLKSOURCE + Clock Source 0=external, 1=processor + 2 + 1 + + CLKSOURCESelect + + VALUE_0 + External clock + 0 + + + VALUE_1 + Processor clock + 1 + + + + + COUNTFLAG + Timer counted to 0 since last read of register + 16 + 1 + + + + + RVR + SysTick Reload Value Register + 0x4 + 32 + + + RELOAD + Value to load into the SysTick Current Value Register when the counter reaches 0 + 0 + 24 + + + + + CVR + SysTick Current Value Register + 0x8 + 32 + + + CURRENT + Current value at the time the register is accessed + 0 + 24 + + + + + CALIB + SysTick Calibration Value Register + 0xC + 32 + read-only + 0 + + + TENMS + Reload value to use for 10ms timing + 0 + 24 + + + SKEW + TENMS is rounded from non-integer ratio + 30 + 1 + + SKEWSelect + + VALUE_0 + 10ms calibration value is exact + 0 + + + VALUE_1 + 10ms calibration value is inexact, because of the clock frequency + 1 + + + + + NOREF + No Separate Reference Clock + 31 + 1 + + NOREFSelect + + VALUE_0 + The reference clock is provided + 0 + + + VALUE_1 + The reference clock is not provided + 1 + + + + + + + + + SystemControl + System Control Registers + SystemControl + SystemControl_ + 0xE000E000 + + 0 + 0xD34 + registers + + + + CPUID + CPUID Base Register + 0xD00 + 32 + read-only + 0x410CC601 + + + REVISION + Minor revision number + 0 + 4 + + + PARTNO + Processor Part Number, 0xC60=Cortex-M0+ + 4 + 12 + + + ARCHITECTURE + Processor Architecture, 0xC=ARMv6-M + 16 + 4 + + + VARIANT + Major revision number + 20 + 4 + + + IMPLEMENTER + Implementer code, ARM=0x41 + 24 + 8 + + + + + ICSR + Interrupt Control and State Register + 0xD04 + 32 + 0x00000000 + + + VECTACTIVE + Debug: Exception number of currently executing exception, or 0 if thread mode + 0 + 9 + + + VECTPENDING + Exception number of the highest priority pending enabled exception + 12 + 9 + + + ISRPENDING + Debug: NVIC interrupt pending + 22 + 1 + + + ISRPREEMPT + Debug: Pending exception serviced on exit from debug halt + 23 + 1 + + + PENDSTCLR + SysTick exception clear-pending bit + 25 + 1 + + PENDSTCLRSelect + + VALUE_0 + No effect + 0 + + + VALUE_1 + Removes the pending state from the SysTick exception + 1 + + + + + PENDSTSET + SysTick exception set-pending bit + 26 + 1 + + PENDSTSETSelect + + VALUE_0 + Write: no effect; read: SysTick exception is not pending + 0 + + + VALUE_1 + Write: changes SysTick exception state to pending; read: SysTick exception is pending + 1 + + + + + PENDSVCLR + PendSV clear-pending bit + 27 + 1 + + PENDSVCLRSelect + + VALUE_0 + No effect + 0 + + + VALUE_1 + Removes the pending state from the PendSV exception + 1 + + + + + PENDSVSET + PendSV set-pending bit + 28 + 1 + + PENDSVSETSelect + + VALUE_0 + Write: no effect; read: PendSV exception is not pending + 0 + + + VALUE_1 + Write: changes PendSV exception state to pending; read: PendSV exception is pending + 1 + + + + + NMIPENDSET + NMI set-pending bit + 31 + 1 + + NMIPENDSETSelect + + VALUE_0 + Write: no effect; read: NMI exception is not pending + 0 + + + VALUE_1 + Write: changes NMI exception state to pending; read: NMI exception is pending + 1 + + + + + + + VTOR + Vector Table Offset Register + 0xD08 + 32 + 0x00000000 + + + TBLOFF + Vector table base offset + 7 + 25 + + + + + AIRCR + Application Interrupt and Reset Control Register + 0xD0C + 32 + 0x00000000 + + + VECTCLRACTIVE + Debug: Clear state information + 1 + 1 + + + SYSRESETREQ + System Reset Request + 2 + 1 + + SYSRESETREQSelect + + VALUE_0 + No system reset request + 0 + + + VALUE_1 + Asserts a signal to the outer system that requests a reset + 1 + + + + + ENDIANNESS + Data Endianness, 0=little, 1=big + 15 + 1 + + ENDIANNESSSelect + + VALUE_0 + Little-endian + 0 + + + VALUE_1 + Big-endian + 1 + + + + + VECTKEY + Register key (0x05FA) + 16 + 16 + + + + + SCR + System Control Register + 0xD10 + 32 + 0x00000000 + + + SLEEPONEXIT + Sleep-On-Exit when exiting Handler mode + 1 + 1 + + SLEEPONEXITSelect + + VALUE_0 + O not sleep when returning to Thread mode + 0 + + + VALUE_1 + Enter sleep, or deep sleep, on return from an ISR + 1 + + + + + SLEEPDEEP + Uses Deep Sleep as low power mode + 2 + 1 + + SLEEPDEEPSelect + + VALUE_0 + Sleep + 0 + + + VALUE_1 + Deep sleep + 1 + + + + + SEVONPEND + Send Event on Pending bit + 4 + 1 + + SEVONPENDSelect + + VALUE_0 + Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded + 0 + + + VALUE_1 + Enabled events and all interrupts, including disabled interrupts, can wakeup the processor + 1 + + + + + + + CCR + Configuration and Control Register + 0xD14 + 32 + read-only + 0x00000204 + + + UNALIGN_TRP + Unaligned accesses generates a Hard Fault + 3 + 1 + + UNALIGN_TRPSelect + + VALUE_0 + Do not trap unaligned halfword and word accesses + 0 + + + VALUE_1 + Trap unaligned halfword and word accesses + 1 + + + + + STKALIGN + Stack 8-byte aligned on exception entry + 9 + 1 + + STKALIGNSelect + + VALUE_0 + 4-byte aligned + 0 + + + VALUE_1 + 8-byte aligned + 1 + + + + + + + SHPR2 + System Handler Priority Register 2 + 0xD1C + 32 + 0x00000000 + + + PRI_11 + Priority of system handler 11, SVCall + 24 + 8 + + + + + SHPR3 + System Handler Priority Register 3 + 0xD20 + 32 + 0x00000000 + + + PRI_14 + Priority of system handler 14, PendSV + 16 + 8 + + + PRI_15 + Priority of system handler 15, SysTick exception + 24 + 8 + + + + + SHCSR + System Handler Control and State Register + 0xD24 + 32 + 0x00000000 + + + SVCALLPENDED + 15 + 1 + + + + + DFSR + Debug Fault Status Register + 0xD30 + 32 + 0x00000000 + + + HALTED + Halt request debug event active + 0 + 1 + + + BKPT + Breakpoint debug event + 1 + 1 + + + DWTTRAP + DWT debug event + 2 + 1 + + + VCATCH + Vector catch debug event + 3 + 1 + + + EXTERNAL + EDBGRQ debug event + 4 + 1 + + + + + + + diff --git a/svd/ATSAMC21N18A.svd b/svd/ATSAMC21N18A.svd new file mode 100644 index 000000000000..5c44cb07f197 --- /dev/null +++ b/svd/ATSAMC21N18A.svd @@ -0,0 +1,28372 @@ + + + + Microchip Technology + MCHP + ATSAMC21N18A + SAMC21 + 0 + Microchip ATSAMC21N18A Microcontroller + + CM0+ + r0p0 + selectable + true + false + 2 + false + + 8 + 32 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + AC + U22451.1.1 + Analog Comparators + AC + AC_ + 0x42005000 + + 0 + 0x24 + registers + + + AC + 27 + + + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + + + CTRLB + Control B + 0x1 + 8 + write-only + 0x00 + + + START0 + Comparator 0 Start Comparison + 0 + 1 + + + START1 + Comparator 1 Start Comparison + 1 + 1 + + + START2 + Comparator 2 Start Comparison + 2 + 1 + + + START3 + Comparator 3 Start Comparison + 3 + 1 + + + + + EVCTRL + Event Control + 0x2 + 16 + 0x0000 + + + COMPEO0 + Comparator 0 Event Output Enable + 0 + 1 + + + COMPEO1 + Comparator 1 Event Output Enable + 1 + 1 + + + COMPEO2 + Comparator 2 Event Output Enable + 2 + 1 + + + COMPEO3 + Comparator 3 Event Output Enable + 3 + 1 + + + WINEO0 + Window 0 Event Output Enable + 4 + 1 + + + WINEO1 + Window 1 Event Output Enable + 5 + 1 + + + COMPEI0 + Comparator 0 Event Input Enable + 8 + 1 + + + COMPEI1 + Comparator 1 Event Input Enable + 9 + 1 + + + COMPEI2 + Comparator 2 Event Input Enable + 10 + 1 + + + COMPEI3 + Comparator 3 Event Input Enable + 11 + 1 + + + INVEI0 + Comparator 0 Input Event Invert Enable + 12 + 1 + + + INVEI1 + Comparator 1 Input Event Invert Enable + 13 + 1 + + + INVEI2 + Comparator 2 Input Event Invert Enable + 14 + 1 + + + INVEI3 + Comparator 3 Input Event Invert Enable + 15 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x4 + 8 + 0x00 + + + COMP0 + Comparator 0 Interrupt Enable + 0 + 1 + + + COMP1 + Comparator 1 Interrupt Enable + 1 + 1 + + + COMP2 + Comparator 2 Interrupt Enable + 2 + 1 + + + COMP3 + Comparator 3 Interrupt Enable + 3 + 1 + + + WIN0 + Window 0 Interrupt Enable + 4 + 1 + + + WIN1 + Window 1 Interrupt Enable + 5 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x5 + 8 + 0x00 + + + COMP0 + Comparator 0 Interrupt Enable + 0 + 1 + + + COMP1 + Comparator 1 Interrupt Enable + 1 + 1 + + + COMP2 + Comparator 2 Interrupt Enable + 2 + 1 + + + COMP3 + Comparator 3 Interrupt Enable + 3 + 1 + + + WIN0 + Window 0 Interrupt Enable + 4 + 1 + + + WIN1 + Window 1 Interrupt Enable + 5 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x6 + 8 + 0x00 + + + COMP0 + Comparator 0 + 0 + 1 + + + COMP1 + Comparator 1 + 1 + 1 + + + COMP2 + Comparator 2 + 2 + 1 + + + COMP3 + Comparator 3 + 3 + 1 + + + WIN0 + Window 0 + 4 + 1 + + + WIN1 + Window 1 + 5 + 1 + + + + + STATUSA + Status A + 0x7 + 8 + read-only + 0x00 + + + STATE0 + Comparator 0 Current State + 0 + 1 + + + STATE1 + Comparator 1 Current State + 1 + 1 + + + STATE2 + Comparator 2 Current State + 2 + 1 + + + STATE3 + Comparator 3 Current State + 3 + 1 + + + WSTATE0 + Window 0 Current State + 4 + 2 + + WSTATE0Select + + ABOVE + Signal is above window + 0 + + + INSIDE + Signal is inside window + 1 + + + BELOW + Signal is below window + 2 + + + + + WSTATE1 + Window 1 Current State + 6 + 2 + + WSTATE1Select + + ABOVE + Signal is above window + 0 + + + INSIDE + Signal is inside window + 1 + + + BELOW + Signal is below window + 2 + + + + + + + STATUSB + Status B + 0x8 + 8 + read-only + 0x00 + + + READY0 + Comparator 0 Ready + 0 + 1 + + + READY1 + Comparator 1 Ready + 1 + 1 + + + READY2 + Comparator 2 Ready + 2 + 1 + + + READY3 + Comparator 3 Ready + 3 + 1 + + + + + DBGCTRL + Debug Control + 0x9 + 8 + 0x00 + + + DBGRUN + Debug Run + 0 + 1 + + + + + WINCTRL + Window Control + 0xA + 8 + 0x00 + + + WEN0 + Window 0 Mode Enable + 0 + 1 + + + WINTSEL0 + Window 0 Interrupt Selection + 1 + 2 + + WINTSEL0Select + + ABOVE + Interrupt on signal above window + 0 + + + INSIDE + Interrupt on signal inside window + 1 + + + BELOW + Interrupt on signal below window + 2 + + + OUTSIDE + Interrupt on signal outside window + 3 + + + + + WEN1 + Window 1 Mode Enable + 4 + 1 + + + WINTSEL1 + Window 1 Interrupt Selection + 5 + 2 + + WINTSEL1Select + + ABOVE + Interrupt on signal above window + 0 + + + INSIDE + Interrupt on signal inside window + 1 + + + BELOW + Interrupt on signal below window + 2 + + + OUTSIDE + Interrupt on signal outside window + 3 + + + + + + + 4 + 1 + SCALER[%s] + Scaler n + 0xC + 8 + 0x00 + + + VALUE + Scaler Value + 0 + 6 + + + + + 4 + 4 + COMPCTRL[%s] + Comparator Control n + 0x10 + 32 + 0x00000000 + + + ENABLE + Enable + 1 + 1 + + + SINGLE + Single-Shot Mode + 2 + 1 + + + INTSEL + Interrupt Selection + 3 + 2 + + INTSELSelect + + TOGGLE + Interrupt on comparator output toggle + 0 + + + RISING + Interrupt on comparator output rising + 1 + + + FALLING + Interrupt on comparator output falling + 2 + + + EOC + Interrupt on end of comparison (single-shot mode only) + 3 + + + + + RUNSTDBY + Run in Standby + 6 + 1 + + + MUXNEG + Negative Input Mux Selection + 8 + 3 + + MUXNEGSelect + + PIN0 + I/O pin 0 + 0 + + + PIN1 + I/O pin 1 + 1 + + + PIN2 + I/O pin 2 + 2 + + + PIN3 + I/O pin 3 + 3 + + + GND + Ground + 4 + + + VSCALE + VDD scaler + 5 + + + BANDGAP + Internal bandgap voltage + 6 + + + DAC + DAC output + 7 + + + + + MUXPOS + Positive Input Mux Selection + 12 + 3 + + MUXPOSSelect + + PIN0 + I/O pin 0 + 0 + + + PIN1 + I/O pin 1 + 1 + + + PIN2 + I/O pin 2 + 2 + + + PIN3 + I/O pin 3 + 3 + + + VSCALE + VDD Scaler + 4 + + + + + SWAP + Swap Inputs and Invert + 15 + 1 + + + SPEED + Speed Selection + 16 + 2 + + SPEEDSelect + + LOW + Low speed + 0 + + + HIGH + High speed + 3 + + + + + HYSTEN + Hysteresis Enable + 19 + 1 + + + FLEN + Filter Length + 24 + 3 + + FLENSelect + + OFF + No filtering + 0 + + + MAJ3 + 3-bit majority function (2 of 3) + 1 + + + MAJ5 + 5-bit majority function (3 of 5) + 2 + + + + + OUT + Output + 28 + 2 + + OUTSelect + + OFF + The output of COMPn is not routed to the COMPn I/O port + 0 + + + ASYNC + The asynchronous output of COMPn is routed to the COMPn I/O port + 1 + + + SYNC + The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port + 2 + + + + + + + SYNCBUSY + Synchronization Busy + 0x20 + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + Enable Synchronization Busy + 1 + 1 + + + WINCTRL + WINCTRL Synchronization Busy + 2 + 1 + + + COMPCTRL0 + COMPCTRL 0 Synchronization Busy + 3 + 1 + + + COMPCTRL1 + COMPCTRL 1 Synchronization Busy + 4 + 1 + + + COMPCTRL2 + COMPCTRL 2 Synchronization Busy + 5 + 1 + + + COMPCTRL3 + COMPCTRL 3 Synchronization Busy + 6 + 1 + + + + + + + ADC0 + U22472.3.0 + Analog Digital Converter + ADC + ADC_ + 0x42004400 + + 0 + 0x2E + registers + + + ADC0 + 25 + + + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + SLAVEEN + Slave Enable + 5 + 1 + + + RUNSTDBY + Run During Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + + + CTRLB + Control B + 0x1 + 8 + 0x00 + + + PRESCALER + Prescaler Configuration + 0 + 3 + + PRESCALERSelect + + DIV2 + Peripheral clock divided by 2 + 0x0 + + + DIV4 + Peripheral clock divided by 4 + 0x1 + + + DIV8 + Peripheral clock divided by 8 + 0x2 + + + DIV16 + Peripheral clock divided by 16 + 0x3 + + + DIV32 + Peripheral clock divided by 32 + 0x4 + + + DIV64 + Peripheral clock divided by 64 + 0x5 + + + DIV128 + Peripheral clock divided by 128 + 0x6 + + + DIV256 + Peripheral clock divided by 256 + 0x7 + + + + + + + REFCTRL + Reference Control + 0x2 + 8 + 0x00 + + + REFSEL + Reference Selection + 0 + 4 + + REFSELSelect + + INTREF + Internal Bandgap Reference + 0x0 + + + INTVCC0 + 1/1.6 VDDANA + 0x1 + + + INTVCC1 + 1/2 VDDANA + 0x2 + + + AREFA + External Reference + 0x3 + + + DAC + DAC + 0x4 + + + INTVCC2 + VDDANA + 0x5 + + + + + REFCOMP + Reference Buffer Offset Compensation Enable + 7 + 1 + + + + + EVCTRL + Event Control + 0x3 + 8 + 0x00 + + + FLUSHEI + Flush Event Input Enable + 0 + 1 + + + STARTEI + Start Conversion Event Input Enable + 1 + 1 + + + FLUSHINV + Flush Event Invert Enable + 2 + 1 + + + STARTINV + Start Event Invert Enable + 3 + 1 + + + RESRDYEO + Result Ready Event Out + 4 + 1 + + + WINMONEO + Window Monitor Event Out + 5 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x4 + 8 + 0x00 + + + RESRDY + Result Ready Interrupt Disable + 0 + 1 + + + OVERRUN + Overrun Interrupt Disable + 1 + 1 + + + WINMON + Window Monitor Interrupt Disable + 2 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x5 + 8 + 0x00 + + + RESRDY + Result Ready Interrupt Enable + 0 + 1 + + + OVERRUN + Overrun Interrupt Enable + 1 + 1 + + + WINMON + Window Monitor Interrupt Enable + 2 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x6 + 8 + 0x00 + + + RESRDY + Result Ready Interrupt Flag + 0 + 1 + + + OVERRUN + Overrun Interrupt Flag + 1 + 1 + + + WINMON + Window Monitor Interrupt Flag + 2 + 1 + + + + + SEQSTATUS + Sequence Status + 0x7 + 8 + read-only + 0x00 + + + SEQSTATE + Sequence State + 0 + 5 + + + SEQBUSY + Sequence Busy + 7 + 1 + + + + + INPUTCTRL + Input Control + 0x8 + 16 + 0x0000 + + + MUXPOS + Positive Mux Input Selection + 0 + 5 + + MUXPOSSelect + + AIN0 + ADC AIN0 Pin + 0x0 + + + AIN1 + ADC AIN1 Pin + 0x1 + + + AIN2 + ADC AIN2 Pin + 0x2 + + + AIN3 + ADC AIN3 Pin + 0x3 + + + AIN4 + ADC AIN4 Pin + 0x4 + + + AIN5 + ADC AIN5 Pin + 0x5 + + + AIN6 + ADC AIN6 Pin + 0x6 + + + AIN7 + ADC AIN7 Pin + 0x7 + + + AIN8 + ADC AIN8 Pin + 0x8 + + + AIN9 + ADC AIN9 Pin + 0x9 + + + AIN10 + ADC AIN10 Pin + 0xA + + + AIN11 + ADC AIN11 Pin + 0xB + + + TEMP + Temperature Sensor + 0x18 + + + BANDGAP + Bandgap Voltage + 0x19 + + + SCALEDCOREVCC + 1/4 Scaled Core Supply + 0x1A + + + SCALEDIOVCC + 1/4 Scaled I/O Supply + 0x1B + + + DAC + DAC Output + 0x1C + + + + + MUXNEG + Negative Mux Input Selection + 8 + 5 + + MUXNEGSelect + + AIN0 + ADC AIN0 Pin + 0x0 + + + AIN1 + ADC AIN1 Pin + 0x1 + + + AIN2 + ADC AIN2 Pin + 0x2 + + + AIN3 + ADC AIN3 Pin + 0x3 + + + AIN4 + ADC AIN4 Pin + 0x4 + + + AIN5 + ADC AIN5 Pin + 0x5 + + + GND + Internal Ground + 0x18 + + + + + + + CTRLC + Control C + 0xA + 16 + 0x0000 + + + DIFFMODE + Differential Mode + 0 + 1 + + + LEFTADJ + Left-Adjusted Result + 1 + 1 + + + FREERUN + Free Running Mode + 2 + 1 + + + CORREN + Digital Correction Logic Enable + 3 + 1 + + + RESSEL + Conversion Result Resolution + 4 + 2 + + RESSELSelect + + 12BIT + 12-bit + 0x0 + + + 16BIT + 16-bit averaging mode + 0x1 + + + 10BIT + 10-bit + 0x2 + + + 8BIT + 8-bit + 0x3 + + + + + R2R + Rail-to-Rail mode enable + 7 + 1 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Interrupt Enable + 6 + 1 + + + OVR7 + Channel 7 Overrun Interrupt Enable + 7 + 1 + + + OVR8 + Channel 8 Overrun Interrupt Enable + 8 + 1 + + + OVR9 + Channel 9 Overrun Interrupt Enable + 9 + 1 + + + OVR10 + Channel 10 Overrun Interrupt Enable + 10 + 1 + + + OVR11 + Channel 11 Overrun Interrupt Enable + 11 + 1 + + + EVD0 + Channel 0 Event Detection Interrupt Enable + 16 + 1 + + + EVD1 + Channel 1 Event Detection Interrupt Enable + 17 + 1 + + + EVD2 + Channel 2 Event Detection Interrupt Enable + 18 + 1 + + + EVD3 + Channel 3 Event Detection Interrupt Enable + 19 + 1 + + + EVD4 + Channel 4 Event Detection Interrupt Enable + 20 + 1 + + + EVD5 + Channel 5 Event Detection Interrupt Enable + 21 + 1 + + + EVD6 + Channel 6 Event Detection Interrupt Enable + 22 + 1 + + + EVD7 + Channel 7 Event Detection Interrupt Enable + 23 + 1 + + + EVD8 + Channel 8 Event Detection Interrupt Enable + 24 + 1 + + + EVD9 + Channel 9 Event Detection Interrupt Enable + 25 + 1 + + + EVD10 + Channel 10 Event Detection Interrupt Enable + 26 + 1 + + + EVD11 + Channel 11 Event Detection Interrupt Enable + 27 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x18 + 32 + 0x00000000 + + + OVR0 + Channel 0 Overrun + 0 + 1 + + + OVR1 + Channel 1 Overrun + 1 + 1 + + + OVR2 + Channel 2 Overrun + 2 + 1 + + + OVR3 + Channel 3 Overrun + 3 + 1 + + + OVR4 + Channel 4 Overrun + 4 + 1 + + + OVR5 + Channel 5 Overrun + 5 + 1 + + + OVR6 + Channel 6 Overrun + 6 + 1 + + + OVR7 + Channel 7 Overrun + 7 + 1 + + + OVR8 + Channel 8 Overrun + 8 + 1 + + + OVR9 + Channel 9 Overrun + 9 + 1 + + + OVR10 + Channel 10 Overrun + 10 + 1 + + + OVR11 + Channel 11 Overrun + 11 + 1 + + + EVD0 + Channel 0 Event Detection + 16 + 1 + + + EVD1 + Channel 1 Event Detection + 17 + 1 + + + EVD2 + Channel 2 Event Detection + 18 + 1 + + + EVD3 + Channel 3 Event Detection + 19 + 1 + + + EVD4 + Channel 4 Event Detection + 20 + 1 + + + EVD5 + Channel 5 Event Detection + 21 + 1 + + + EVD6 + Channel 6 Event Detection + 22 + 1 + + + EVD7 + Channel 7 Event Detection + 23 + 1 + + + EVD8 + Channel 8 Event Detection + 24 + 1 + + + EVD9 + Channel 9 Event Detection + 25 + 1 + + + EVD10 + Channel 10 Event Detection + 26 + 1 + + + EVD11 + Channel 11 Event Detection + 27 + 1 + + + + + SWEVT + Software Event + 0x1C + 32 + write-only + 0x00000000 + + + CHANNEL0 + Channel 0 Software Selection + 0 + 1 + + + CHANNEL1 + Channel 1 Software Selection + 1 + 1 + + + CHANNEL2 + Channel 2 Software Selection + 2 + 1 + + + CHANNEL3 + Channel 3 Software Selection + 3 + 1 + + + CHANNEL4 + Channel 4 Software Selection + 4 + 1 + + + CHANNEL5 + Channel 5 Software Selection + 5 + 1 + + + CHANNEL6 + Channel 6 Software Selection + 6 + 1 + + + CHANNEL7 + Channel 7 Software Selection + 7 + 1 + + + CHANNEL8 + Channel 8 Software Selection + 8 + 1 + + + CHANNEL9 + Channel 9 Software Selection + 9 + 1 + + + CHANNEL10 + Channel 10 Software Selection + 10 + 1 + + + CHANNEL11 + Channel 11 Software Selection + 11 + 1 + + + + + 12 + 4 + CHANNEL[%s] + Channel n + 0x20 + 32 + 0x00008000 + + + EVGEN + Event Generator Selection + 0 + 7 + + + PATH + Path Selection + 8 + 2 + + PATHSelect + + SYNCHRONOUS + Synchronous path + 0 + + + RESYNCHRONIZED + Resynchronized path + 1 + + + ASYNCHRONOUS + Asynchronous path + 2 + + + + + EDGSEL + Edge Detection Selection + 10 + 2 + + EDGSELSelect + + NO_EVT_OUTPUT + No event output when using the resynchronized or synchronous path + 0 + + + RISING_EDGE + Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path + 1 + + + FALLING_EDGE + Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path + 2 + + + BOTH_EDGES + Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path + 3 + + + + + RUNSTDBY + Run in standby + 14 + 1 + + + ONDEMAND + Generic Clock On Demand + 15 + 1 + + + + + 50 + 4 + USER[%s] + User Multiplexer n + 0x80 + 32 + 0x00000000 + + + CHANNEL + Channel Event Selection + 0 + 5 + + + + + + + FREQM + U22572.0.0 + Frequency Meter + FREQM + FREQM_ + 0x40002C00 + + 0 + 0x14 + registers + + + FREQM + 4 + + + + CTRLA + Control A Register + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + + + CTRLB + Control B Register + 0x1 + 8 + write-only + 0x00 + + + START + Start Measurement + 0 + 1 + + + + + CFGA + Config A register + 0x2 + 16 + 0x0000 + + + REFNUM + Number of Reference Clock Cycles + 0 + 8 + + + DIVREF + Divide Reference Clock + 15 + 1 + + + + + INTENCLR + Interrupt Enable Clear Register + 0x8 + 8 + 0x00 + + + DONE + Measurement Done Interrupt Enable + 0 + 1 + + + + + INTENSET + Interrupt Enable Set Register + 0x9 + 8 + 0x00 + + + DONE + Measurement Done Interrupt Enable + 0 + 1 + + + + + INTFLAG + Interrupt Flag Register + 0xA + 8 + 0x00 + + + DONE + Measurement Done + 0 + 1 + + + + + STATUS + Status Register + 0xB + 8 + 0x00 + + + BUSY + FREQM Status + 0 + 1 + + + OVF + Sticky Count Value Overflow + 1 + 1 + + + + + SYNCBUSY + Synchronization Busy Register + 0xC + 32 + read-only + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + + + VALUE + Count Value Register + 0x10 + 32 + read-only + 0x00000000 + + + VALUE + Measurement Value + 0 + 24 + + + + + + + GCLK + U21221.1.1 + Generic Clock Generator + GCLK + GCLK_ + 0x40001C00 + + 0 + 0x198 + registers + + + + CTRLA + Control + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + + + SYNCBUSY + Synchronization Busy + 0x4 + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchroniation Busy bit + 0 + 1 + + + GENCTRL0 + Generic Clock Generator Control 0 Synchronization Busy bits + 2 + 1 + + GENCTRL0Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + + + GENCTRL1 + Generic Clock Generator Control 1 Synchronization Busy bits + 3 + 1 + + GENCTRL1Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + + + GENCTRL2 + Generic Clock Generator Control 2 Synchronization Busy bits + 4 + 1 + + GENCTRL2Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + + + GENCTRL3 + Generic Clock Generator Control 3 Synchronization Busy bits + 5 + 1 + + GENCTRL3Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + + + GENCTRL4 + Generic Clock Generator Control 4 Synchronization Busy bits + 6 + 1 + + GENCTRL4Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + + + GENCTRL5 + Generic Clock Generator Control 5 Synchronization Busy bits + 7 + 1 + + GENCTRL5Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + + + GENCTRL6 + Generic Clock Generator Control 6 Synchronization Busy bits + 8 + 1 + + GENCTRL6Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + + + GENCTRL7 + Generic Clock Generator Control 7 Synchronization Busy bits + 9 + 1 + + GENCTRL7Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + + + GENCTRL8 + Generic Clock Generator Control 8 Synchronization Busy bits + 10 + 1 + + GENCTRL8Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + + + + + 9 + 4 + GENCTRL[%s] + Generic Clock Generator Control + 0x20 + 32 + 0x00000000 + + + SRC + Source Select + 0 + 3 + + SRCSelect + + XOSC + XOSC oscillator output + 0 + + + GCLKIN + Generator input pad + 1 + + + GCLKGEN1 + Generic clock generator 1 output + 2 + + + OSCULP32K + OSCULP32K oscillator output + 3 + + + OSC32K + OSC32K oscillator output + 4 + + + XOSC32K + XOSC32K oscillator output + 5 + + + OSC48M + OSC48M oscillator output + 6 + + + DPLL96M + DPLL96M output + 7 + + + + + GENEN + Generic Clock Generator Enable + 8 + 1 + + + IDC + Improve Duty Cycle + 9 + 1 + + + OOV + Output Off Value + 10 + 1 + + + OE + Output Enable + 11 + 1 + + + DIVSEL + Divide Selection + 12 + 1 + + DIVSELSelect + + DIV1 + Divide input directly by divider factor + 0x0 + + + DIV2 + Divide input by 2^(divider factor+ 1) + 0x1 + + + + + RUNSTDBY + Run in Standby + 13 + 1 + + + DIV + Division Factor + 16 + 16 + + + + + 46 + 4 + PCHCTRL[%s] + Peripheral Clock Control + 0x80 + 32 + 0x00000000 + + + GEN + Generic Clock Generator + 0 + 4 + + GENSelect + + GCLK0 + Generic clock generator 0 + 0x0 + + + GCLK1 + Generic clock generator 1 + 0x1 + + + GCLK2 + Generic clock generator 2 + 0x2 + + + GCLK3 + Generic clock generator 3 + 0x3 + + + GCLK4 + Generic clock generator 4 + 0x4 + + + GCLK5 + Generic clock generator 5 + 0x5 + + + GCLK6 + Generic clock generator 6 + 0x6 + + + GCLK7 + Generic clock generator 7 + 0x7 + + + GCLK8 + Generic clock generator 8 + 0x8 + + + + + CHEN + Channel Enable + 6 + 1 + + + WRTLOCK + Write Lock + 7 + 1 + + + + + + + HMATRIXHS + I76382.1.4 + HSB Matrix + HMATRIXB + HMATRIXB_ + 0x4100A000 + + 0 + 0x168 + registers + + + + 16 + 4 + MCFG[%s] + Master Configuration + 0x0 + 32 + 0x00000002 + + + ULBT + Undefined Length Burst Type + 0 + 3 + + ULBTSelect + + INFINITE + Infinite Length + 0 + + + SINGLE + Single Access + 1 + + + FOUR_BEAT + Four Beat Burst + 2 + + + EIGHT_BEAT + Eight Beat Burst + 3 + + + SIXTEEN_BEAT + Sixteen Beat Burst + 4 + + + + + + + 16 + 4 + SCFG[%s] + Slave Configuration + 0x40 + 32 + 0x00000010 + + + SLOT_CYCLE + Maximum Number of Allowed Cycles for a Burst + 0 + 8 + + + DEFMSTR_TYPE + Default Master Type + 16 + 2 + + DEFMSTR_TYPESelect + + NO_DEFAULT + No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. + 0 + + + LAST_DEFAULT + Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. + 1 + + + FIXED_DEFAULT + Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave. + 2 + + + + + FIXED_DEFMSTR + Fixed Index of Default Master + 18 + 4 + + + ARBT + Arbitration Type + 24 + 1 + + ARBTSelect + + ROUND_ROBIN + Round-Robin Arbitration + 0 + + + FIXED_PRIORITY + Fixed Priority Arbitration + 1 + + + + + + + 4 + 0x8 + PRS[%s] + + 0x080 + + PRAS + Priority A for Slave + 0x0 + 32 + 0x00000000 + + + M0PR + Master 0 Priority + 0 + 4 + + + M1PR + Master 1 Priority + 4 + 4 + + + M2PR + Master 2 Priority + 8 + 4 + + + M3PR + Master 3 Priority + 12 + 4 + + + M4PR + Master 4 Priority + 16 + 4 + + + M5PR + Master 5 Priority + 20 + 4 + + + M6PR + Master 6 Priority + 24 + 4 + + + M7PR + Master 7 Priority + 28 + 4 + + + + + PRBS + Priority B for Slave + 0x4 + 32 + 0x00000000 + + + M8PR + Master 8 Priority + 0 + 4 + + + M9PR + Master 9 Priority + 4 + 4 + + + M10PR + Master 10 Priority + 8 + 4 + + + M11PR + Master 11 Priority + 12 + 4 + + + M12PR + Master 12 Priority + 16 + 4 + + + M13PR + Master 13 Priority + 20 + 4 + + + M14PR + Master 14 Priority + 24 + 4 + + + M15PR + Master 15 Priority + 28 + 4 + + + + + + MRCR + Master Remap Control + 0x100 + 32 + 0x00000000 + + + RCB0 + Remap Command Bit for Master 0 + 0 + 1 + + RCB0Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB1 + Remap Command Bit for Master 1 + 1 + 1 + + RCB1Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB2 + Remap Command Bit for Master 2 + 2 + 1 + + RCB2Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB3 + Remap Command Bit for Master 3 + 3 + 1 + + RCB3Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB4 + Remap Command Bit for Master 4 + 4 + 1 + + RCB4Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB5 + Remap Command Bit for Master 5 + 5 + 1 + + RCB5Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB6 + Remap Command Bit for Master 6 + 6 + 1 + + RCB6Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB7 + Remap Command Bit for Master 7 + 7 + 1 + + RCB7Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB8 + Remap Command Bit for Master 8 + 8 + 1 + + RCB8Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB9 + Remap Command Bit for Master 9 + 9 + 1 + + RCB9Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB10 + Remap Command Bit for Master 10 + 10 + 1 + + RCB10Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB11 + Remap Command Bit for Master 11 + 11 + 1 + + RCB11Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB12 + Remap Command Bit for Master 12 + 12 + 1 + + RCB12Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB13 + Remap Command Bit for Master 13 + 13 + 1 + + RCB13Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB14 + Remap Command Bit for Master 14 + 14 + 1 + + RCB14Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + RCB15 + Remap Command Bit for Master 15 + 15 + 1 + + RCB15Select + + DIS + Disable remapped address decoding for master + 0 + + + ENA + Enable remapped address decoding for master + 1 + + + + + + + 16 + 4 + SFR[%s] + Special Function + 0x110 + 32 + 0x00000000 + + + SFR + Special Function Register + 0 + 32 + + + + + + + MCLK + U22342.0.0 + Main Clock + MCLK + MCLK_ + 0x40000800 + + 0 + 0x24 + registers + + + + INTENCLR + Interrupt Enable Clear + 0x1 + 8 + 0x00 + + + CKRDY + Clock Ready Interrupt Enable + 0 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x2 + 8 + 0x00 + + + CKRDY + Clock Ready Interrupt Enable + 0 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x3 + 8 + 0x01 + + + CKRDY + Clock Ready + 0 + 1 + + + + + CPUDIV + CPU Clock Division + 0x4 + 8 + 0x01 + + + CPUDIV + CPU Clock Division Factor + 0 + 8 + + CPUDIVSelect + + DIV1 + Divide by 1 + 0x01 + + + DIV2 + Divide by 2 + 0x02 + + + DIV4 + Divide by 4 + 0x04 + + + DIV8 + Divide by 8 + 0x08 + + + DIV16 + Divide by 16 + 0x10 + + + DIV32 + Divide by 32 + 0x20 + + + DIV64 + Divide by 64 + 0x40 + + + DIV128 + Divide by 128 + 0x80 + + + + + + + AHBMASK + AHB Mask + 0x10 + 32 + 0x00003CFF + + + HPB0_ + HPB0 AHB Clock Mask + 0 + 1 + + + HPB1_ + HPB1 AHB Clock Mask + 1 + 1 + + + HPB2_ + HPB2 AHB Clock Mask + 2 + 1 + + + DSU_ + DSU AHB Clock Mask + 3 + 1 + + + HMATRIXHS_ + HMATRIXHS AHB Clock Mask + 4 + 1 + + + NVMCTRL_ + NVMCTRL AHB Clock Mask + 5 + 1 + + + HSRAM_ + HSRAM AHB Clock Mask + 6 + 1 + + + DMAC_ + DMAC AHB Clock Mask + 7 + 1 + + + CAN0_ + CAN0 AHB Clock Mask + 8 + 1 + + + CAN1_ + CAN1 AHB Clock Mask + 9 + 1 + + + PAC_ + PAC AHB Clock Mask + 10 + 1 + + + NVMCTRL_PICACHU_ + NVMCTRL_PICACHU AHB Clock Mask + 11 + 1 + + + DIVAS_ + DIVAS AHB Clock Mask + 12 + 1 + + + HPB3_ + HPB3 AHB Clock Mask + 13 + 1 + + + + + APBAMASK + APBA Mask + 0x14 + 32 + 0x00000FFF + + + PAC_ + PAC APB Clock Enable + 0 + 1 + + + PM_ + PM APB Clock Enable + 1 + 1 + + + MCLK_ + MCLK APB Clock Enable + 2 + 1 + + + RSTC_ + RSTC APB Clock Enable + 3 + 1 + + + OSCCTRL_ + OSCCTRL APB Clock Enable + 4 + 1 + + + OSC32KCTRL_ + OSC32KCTRL APB Clock Enable + 5 + 1 + + + SUPC_ + SUPC APB Clock Enable + 6 + 1 + + + GCLK_ + GCLK APB Clock Enable + 7 + 1 + + + WDT_ + WDT APB Clock Enable + 8 + 1 + + + RTC_ + RTC APB Clock Enable + 9 + 1 + + + EIC_ + EIC APB Clock Enable + 10 + 1 + + + FREQM_ + FREQM APB Clock Enable + 11 + 1 + + + TSENS_ + TSENS APB Clock Enable + 12 + 1 + + + + + APBBMASK + APBB Mask + 0x18 + 32 + 0x00000007 + + + PORT_ + PORT APB Clock Enable + 0 + 1 + + + DSU_ + DSU APB Clock Enable + 1 + 1 + + + NVMCTRL_ + NVMCTRL APB Clock Enable + 2 + 1 + + + HMATRIXHS_ + HMATRIXHS APB Clock Enable + 5 + 1 + + + + + APBCMASK + APBC Mask + 0x1C + 32 + 0x00000000 + + + EVSYS_ + EVSYS APB Clock Enable + 0 + 1 + + + SERCOM0_ + SERCOM0 APB Clock Enable + 1 + 1 + + + SERCOM1_ + SERCOM1 APB Clock Enable + 2 + 1 + + + SERCOM2_ + SERCOM2 APB Clock Enable + 3 + 1 + + + SERCOM3_ + SERCOM3 APB Clock Enable + 4 + 1 + + + SERCOM4_ + SERCOM4 APB Clock Enable + 5 + 1 + + + SERCOM5_ + SERCOM5 APB Clock Enable + 6 + 1 + + + TCC0_ + TCC0 APB Clock Enable + 9 + 1 + + + TCC1_ + TCC1 APB Clock Enable + 10 + 1 + + + TCC2_ + TCC2 APB Clock Enable + 11 + 1 + + + TC0_ + TC0 APB Clock Enable + 12 + 1 + + + TC1_ + TC1 APB Clock Enable + 13 + 1 + + + TC2_ + TC2 APB Clock Enable + 14 + 1 + + + TC3_ + TC3 APB Clock Enable + 15 + 1 + + + TC4_ + TC4 APB Clock Enable + 16 + 1 + + + ADC0_ + ADC0 APB Clock Enable + 17 + 1 + + + ADC1_ + ADC1 APB Clock Enable + 18 + 1 + + + SDADC_ + SDADC APB Clock Enable + 19 + 1 + + + AC_ + AC APB Clock Enable + 20 + 1 + + + DAC_ + DAC APB Clock Enable + 21 + 1 + + + PTC_ + PTC APB Clock Enable + 22 + 1 + + + CCL_ + CCL APB Clock Enable + 23 + 1 + + + + + APBDMASK + APBD Mask + 0x20 + 32 + 0x00000000 + + + SERCOM6_ + SERCOM6 APB Clock Enable + 0 + 1 + + + SERCOM7_ + SERCOM7 APB Clock Enable + 1 + 1 + + + TC5_ + TC5 APB Clock Enable + 2 + 1 + + + TC6_ + TC6 APB Clock Enable + 3 + 1 + + + TC7_ + TC7 APB Clock Enable + 4 + 1 + + + + + + + MTB + U20021.0.0 + Cortex-M0+ Micro-Trace Buffer + MTB + MTB_ + 0x41008000 + + 0 + 0x1000 + registers + + + + POSITION + MTB Position + 0x0 + 32 + + + WRAP + Pointer Value Wraps + 2 + 1 + + + POINTER + Trace Packet Location Pointer + 3 + 29 + + + + + MASTER + MTB Master + 0x4 + 32 + 0x00000000 + + + MASK + Maximum Value of the Trace Buffer in SRAM + 0 + 5 + + + TSTARTEN + Trace Start Input Enable + 5 + 1 + + + TSTOPEN + Trace Stop Input Enable + 6 + 1 + + + SFRWPRIV + Special Function Register Write Privilege + 7 + 1 + + + RAMPRIV + SRAM Privilege + 8 + 1 + + + HALTREQ + Halt Request + 9 + 1 + + + EN + Main Trace Enable + 31 + 1 + + + + + FLOW + MTB Flow + 0x8 + 32 + 0x00000000 + + + AUTOSTOP + Auto Stop Tracing + 0 + 1 + + + AUTOHALT + Auto Halt Request + 1 + 1 + + + WATERMARK + Watermark value + 3 + 29 + + + + + BASE + MTB Base + 0xC + 32 + read-only + + + ITCTRL + MTB Integration Mode Control + 0xF00 + 32 + + + CLAIMSET + MTB Claim Set + 0xFA0 + 32 + + + CLAIMCLR + MTB Claim Clear + 0xFA4 + 32 + + + LOCKACCESS + MTB Lock Access + 0xFB0 + 32 + + + LOCKSTATUS + MTB Lock Status + 0xFB4 + 32 + read-only + + + AUTHSTATUS + MTB Authentication Status + 0xFB8 + 32 + read-only + + + DEVARCH + MTB Device Architecture + 0xFBC + 32 + read-only + + + DEVID + MTB Device Configuration + 0xFC8 + 32 + read-only + + + DEVTYPE + MTB Device Type + 0xFCC + 32 + read-only + + + PID4 + Peripheral Identification 4 + 0xFD0 + 32 + read-only + + + PID5 + Peripheral Identification 5 + 0xFD4 + 32 + read-only + + + PID6 + Peripheral Identification 6 + 0xFD8 + 32 + read-only + + + PID7 + Peripheral Identification 7 + 0xFDC + 32 + read-only + + + PID0 + Peripheral Identification 0 + 0xFE0 + 32 + read-only + + + PID1 + Peripheral Identification 1 + 0xFE4 + 32 + read-only + + + PID2 + Peripheral Identification 2 + 0xFE8 + 32 + read-only + + + PID3 + Peripheral Identification 3 + 0xFEC + 32 + read-only + + + CID0 + Component Identification 0 + 0xFF0 + 32 + read-only + + + CID1 + Component Identification 1 + 0xFF4 + 32 + read-only + + + CID2 + Component Identification 2 + 0xFF8 + 32 + read-only + + + CID3 + Component Identification 3 + 0xFFC + 32 + read-only + + + + + NVMCTRL + U22074.0.2 + Non-Volatile Memory Controller + NVMCTRL + NVMCTRL_ + 0x41004000 + + 0 + 0x30 + registers + + + NVMCTRL + 6 + + + + CTRLA + Control A + 0x0 + 16 + 0x0000 + + + CMD + Command + 0 + 7 + + CMDSelect + + ER + Erase Row - Erases the row addressed by the ADDR register. + 0x02 + + + WP + Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. + 0x04 + + + EAR + Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. + 0x05 + + + WAP + Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. + 0x06 + + + SF + Security Flow Command + 0x0A + + + WL + Write lockbits + 0x0F + + + RWWEEER + RWW EEPROM area Erase Row - Erases the row addressed by the ADDR register. + 0x1A + + + RWWEEWP + RWW EEPROM Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. + 0x1C + + + LR + Lock Region - Locks the region containing the address location in the ADDR register. + 0x40 + + + UR + Unlock Region - Unlocks the region containing the address location in the ADDR register. + 0x41 + + + SPRM + Sets the power reduction mode. + 0x42 + + + CPRM + Clears the power reduction mode. + 0x43 + + + PBC + Page Buffer Clear - Clears the page buffer. + 0x44 + + + SSB + Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row. + 0x45 + + + INVALL + Invalidate all cache lines. + 0x46 + + + + + CMDEX + Command Execution + 8 + 8 + + CMDEXSelect + + KEY + Execution Key + 0xA5 + + + + + + + CTRLB + Control B + 0x4 + 32 + 0x00000080 + + + RWS + NVM Read Wait States + 1 + 4 + + RWSSelect + + SINGLE + Single Auto Wait State + 0 + + + HALF + Half Auto Wait State + 1 + + + DUAL + Dual Auto Wait State + 2 + + + + + MANW + Manual Write + 7 + 1 + + + SLEEPPRM + Power Reduction Mode during Sleep + 8 + 2 + + SLEEPPRMSelect + + WAKEONACCESS + NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access. + 0 + + + WAKEUPINSTANT + NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep. + 1 + + + DISABLED + Auto power reduction disabled. + 3 + + + + + READMODE + NVMCTRL Read Mode + 16 + 2 + + READMODESelect + + NO_MISS_PENALTY + The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance. + 0x0 + + + LOW_POWER + Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time. + 0x1 + + + DETERMINISTIC + The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings. + 0x2 + + + + + CACHEDIS + Cache Disable + 18 + 2 + + + + + PARAM + NVM Parameter + 0x8 + 32 + 0x00000000 + + + NVMP + NVM Pages + 0 + 16 + + + PSZ + Page Size + 16 + 3 + + PSZSelect + + 8 + 8 bytes + 0x0 + + + 16 + 16 bytes + 0x1 + + + 32 + 32 bytes + 0x2 + + + 64 + 64 bytes + 0x3 + + + 128 + 128 bytes + 0x4 + + + 256 + 256 bytes + 0x5 + + + 512 + 512 bytes + 0x6 + + + 1024 + 1024 bytes + 0x7 + + + + + RWWEEP + RWW EEPROM Pages + 20 + 12 + + + + + INTENCLR + Interrupt Enable Clear + 0xC + 8 + 0x00 + + + READY + NVM Ready Interrupt Enable + 0 + 1 + + + ERROR + Error Interrupt Enable + 1 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x10 + 8 + 0x00 + + + READY + NVM Ready Interrupt Enable + 0 + 1 + + + ERROR + Error Interrupt Enable + 1 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x14 + 8 + 0x00 + + + READY + NVM Ready + 0 + 1 + + + ERROR + Error + 1 + 1 + + + + + STATUS + Status + 0x18 + 16 + 0x0000 + + + PRM + Power Reduction Mode + 0 + 1 + + + LOAD + NVM Page Buffer Active Loading + 1 + 1 + + + PROGE + Programming Error Status + 2 + 1 + + + LOCKE + Lock Error Status + 3 + 1 + + + NVME + NVM Error + 4 + 1 + + + SB + Security Bit Status + 8 + 1 + + + + + ADDR + Address + 0x1C + 32 + 0x00000000 + + + ADDR + NVM Address + 0 + 22 + + + + + LOCK + Lock Section + 0x20 + 16 + 0x0000 + + + LOCK + Region Lock Bits + 0 + 16 + + + + + PBLDATA0 + Page Buffer Load Data 0 + 0x28 + 32 + read-only + 0x00000000 + + + PBLDATA1 + Page Buffer Load Data 1 + 0x2C + 32 + read-only + 0x00000000 + + + + + OSCCTRL + U21192.1.0 + Oscillators Control + OSCCTRL + OSCCTRL_ + 0x40001000 + + 0 + 0x3C + registers + + + + INTENCLR + Interrupt Enable Clear + 0x0 + 32 + 0x00000000 + + + XOSCRDY + XOSC Ready Interrupt Enable + 0 + 1 + + + XOSCFAIL + XOSC Clock Failure Detector Interrupt Enable + 1 + 1 + + + OSC48MRDY + OSC48M Ready Interrupt Enable + 4 + 1 + + + DPLLLCKR + DPLL Lock Rise Interrupt Enable + 8 + 1 + + + DPLLLCKF + DPLL Lock Fall Interrupt Enable + 9 + 1 + + + DPLLLTO + DPLL Time Out Interrupt Enable + 10 + 1 + + + DPLLLDRTO + DPLL Ratio Ready Interrupt Enable + 11 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x4 + 32 + 0x00000000 + + + XOSCRDY + XOSC Ready Interrupt Enable + 0 + 1 + + + XOSCFAIL + XOSC Clock Failure Detector Interrupt Enable + 1 + 1 + + + OSC48MRDY + OSC48M Ready Interrupt Enable + 4 + 1 + + + DPLLLCKR + DPLL Lock Rise Interrupt Enable + 8 + 1 + + + DPLLLCKF + DPLL Lock Fall Interrupt Enable + 9 + 1 + + + DPLLLTO + DPLL Time Out Interrupt Enable + 10 + 1 + + + DPLLLDRTO + DPLL Ratio Ready Interrupt Enable + 11 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x8 + 32 + 0x00000000 + + + XOSCRDY + XOSC Ready + 0 + 1 + + + XOSCFAIL + XOSC Clock Failure Detector + 1 + 1 + + + OSC48MRDY + OSC48M Ready + 4 + 1 + + + DPLLLCKR + DPLL Lock Rise + 8 + 1 + + + DPLLLCKF + DPLL Lock Fall + 9 + 1 + + + DPLLLTO + DPLL Timeout + 10 + 1 + + + DPLLLDRTO + DPLL Ratio Ready + 11 + 1 + + + + + STATUS + Power and Clocks Status + 0xC + 32 + read-only + 0x00000000 + + + XOSCRDY + XOSC Ready + 0 + 1 + + + XOSCFAIL + XOSC Clock Failure Detector + 1 + 1 + + + XOSCCKSW + XOSC Clock Switch + 2 + 1 + + + OSC48MRDY + OSC48M Ready + 4 + 1 + + + DPLLLCKR + DPLL Lock Rise + 8 + 1 + + + DPLLLCKF + DPLL Lock Fall + 9 + 1 + + + DPLLTO + DPLL Timeout + 10 + 1 + + + DPLLLDRTO + DPLL Ratio Ready + 11 + 1 + + + + + XOSCCTRL + External Multipurpose Crystal Oscillator (XOSC) Control + 0x10 + 16 + 0x0080 + + + ENABLE + Oscillator Enable + 1 + 1 + + + XTALEN + Crystal Oscillator Enable + 2 + 1 + + + CFDEN + Xosc Clock Failure Detector Enable + 3 + 1 + + + SWBEN + Xosc Clock Switch Enable + 4 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + GAIN + Oscillator Gain + 8 + 3 + + GAINSelect + + GAIN2 + 2 MHz + 0 + + + GAIN4 + 4 MHz + 1 + + + GAIN8 + 8 MHz + 2 + + + GAIN16 + 16 MHz + 3 + + + GAIN30 + 30 MHz + 4 + + + + + AMPGC + Automatic Amplitude Gain Control + 11 + 1 + + + STARTUP + Start-Up Time + 12 + 4 + + STARTUPSelect + + CYCLE1 + 31 us + 0 + + + CYCLE2 + 61 us + 1 + + + CYCLE4 + 122 us + 2 + + + CYCLE8 + 244 us + 3 + + + CYCLE16 + 488 us + 4 + + + CYCLE32 + 977 us + 5 + + + CYCLE64 + 1953 us + 6 + + + CYCLE128 + 3906 us + 7 + + + CYCLE256 + 7813 us + 8 + + + CYCLE512 + 15625 us + 9 + + + CYCLE1024 + 31250 us + 10 + + + CYCLE2048 + 62500 us + 11 + + + CYCLE4096 + 125000 us + 12 + + + CYCLE8192 + 250000 us + 13 + + + CYCLE16384 + 500000 us + 14 + + + CYCLE32768 + 1000000 us + 15 + + + + + + + CFDPRESC + Clock Failure Detector Prescaler + 0x12 + 8 + 0x00 + + + CFDPRESC + Clock Failure Detector Prescaler + 0 + 3 + + CFDPRESCSelect + + DIV1 + 48 MHz + 0 + + + DIV2 + 24 MHz + 1 + + + DIV4 + 12 MHz + 2 + + + DIV8 + 6 MHz + 3 + + + DIV16 + 3 MHz + 4 + + + DIV32 + 1.5 MHz + 5 + + + DIV64 + 0.75 MHz + 6 + + + DIV128 + 0.3125 MHz + 7 + + + + + + + EVCTRL + Event Control + 0x13 + 8 + 0x00 + + + CFDEO + Clock Failure Detector Event Output Enable + 0 + 1 + + + + + OSC48MCTRL + 48MHz Internal Oscillator (OSC48M) Control + 0x14 + 8 + 0x82 + + + ENABLE + Oscillator Enable + 1 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + + + OSC48MDIV + OSC48M Divider + 0x15 + 8 + 0x0B + + + DIV + OSC48M Division Factor + 0 + 4 + + DIVSelect + + DIV1 + 48 MHz + 0 + + + DIV2 + 24 MHz + 1 + + + DIV3 + 16 MHz + 2 + + + DIV4 + 12 MHz + 3 + + + DIV5 + 9.6 MHz + 4 + + + DIV6 + 8 MHz + 5 + + + DIV7 + 6.86 MHz + 6 + + + DIV8 + 6 MHz + 7 + + + DIV9 + 5.33 MHz + 8 + + + DIV10 + 4.8 MHz + 9 + + + DIV11 + 4.36 MHz + 10 + + + DIV12 + 4 MHz + 11 + + + DIV13 + 3.69 MHz + 12 + + + DIV14 + 3.43 MHz + 13 + + + DIV15 + 3.2 MHz + 14 + + + DIV16 + 3 MHz + 15 + + + + + + + OSC48MSTUP + OSC48M Startup Time + 0x16 + 8 + 0x07 + + + STARTUP + Startup Time + 0 + 3 + + STARTUPSelect + + CYCLE8 + 166 ns + 0 + + + CYCLE16 + 333 ns + 1 + + + CYCLE32 + 667 ns + 2 + + + CYCLE64 + 1.333 us + 3 + + + CYCLE128 + 2.667 us + 4 + + + CYCLE256 + 5.333 us + 5 + + + CYCLE512 + 10.667 us + 6 + + + CYCLE1024 + 21.333 us + 7 + + + + + + + OSC48MSYNCBUSY + OSC48M Synchronization Busy + 0x18 + 32 + read-only + 0x00000000 + + + OSC48MDIV + OSC48MDIV Synchronization Status + 2 + 1 + + + + + DPLLCTRLA + DPLL Control + 0x1C + 8 + 0x80 + + + ENABLE + Enable + 1 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand + 7 + 1 + + + + + DPLLRATIO + DPLL Ratio Control + 0x20 + 32 + 0x00000000 + + + LDR + Loop Divider Ratio + 0 + 12 + + + LDRFRAC + Loop Divider Ratio Fractional Part + 16 + 4 + + + + + DPLLCTRLB + Digital Core Configuration + 0x24 + 32 + 0x00000000 + + + FILTER + Proportional Integral Filter Selection + 0 + 2 + + FILTERSelect + + DEFAULT + Default filter mode + 0 + + + LBFILT + Low bandwidth filter + 1 + + + HBFILT + High bandwidth filter + 2 + + + HDFILT + High damping filter + 3 + + + + + LPEN + Low-Power Enable + 2 + 1 + + + WUF + Wake Up Fast + 3 + 1 + + + REFCLK + Reference Clock Selection + 4 + 2 + + REFCLKSelect + + XOSC32K + XOSC32K clock reference + 0 + + + XOSC + XOSC clock reference + 1 + + + GCLK + GCLK clock reference + 2 + + + + + LTIME + Lock Time + 8 + 3 + + LTIMESelect + + DEFAULT + No time-out. Automatic lock. + 0 + + + 8MS + Time-out if no lock within 8ms + 4 + + + 9MS + Time-out if no lock within 9ms + 5 + + + 10MS + Time-out if no lock within 10ms + 6 + + + 11MS + Time-out if no lock within 11ms + 7 + + + + + LBYPASS + Lock Bypass + 12 + 1 + + + DIV + Clock Divider + 16 + 11 + + + + + DPLLPRESC + DPLL Prescaler + 0x28 + 8 + 0x00 + + + PRESC + Output Clock Prescaler + 0 + 2 + + PRESCSelect + + DIV1 + DPLL output is divided by 1 + 0 + + + DIV2 + DPLL output is divided by 2 + 1 + + + DIV4 + DPLL output is divided by 4 + 2 + + + + + + + DPLLSYNCBUSY + DPLL Synchronization Busy + 0x2C + 8 + read-only + 0x00 + + + ENABLE + DPLL Enable Synchronization Status + 1 + 1 + + + DPLLRATIO + DPLL Ratio Synchronization Status + 2 + 1 + + + DPLLPRESC + DPLL Prescaler Synchronization Status + 3 + 1 + + + + + DPLLSTATUS + DPLL Status + 0x30 + 8 + read-only + 0x00 + + + LOCK + DPLL Lock Status + 0 + 1 + + + CLKRDY + DPLL Clock Ready + 1 + 1 + + + + + CAL48M + 48MHz Oscillator Calibration + 0x38 + 32 + 0x00000000 + + + FCAL + Frequency Calibration (48MHz) + 0 + 6 + + + FRANGE + Frequency Range (48MHz) + 8 + 2 + + + TCAL + Temperature Calibration (48MHz) + 16 + 6 + + + + + + + OSC32KCTRL + U22462.1.0 + 32k Oscillators Control + OSC32KCTRL + OSC32KCTRL_ + 0x40001400 + + 0 + 0x20 + registers + + + + INTENCLR + Interrupt Enable Clear + 0x0 + 32 + 0x00000000 + + + XOSC32KRDY + XOSC32K Ready Interrupt Enable + 0 + 1 + + + OSC32KRDY + OSC32K Ready Interrupt Enable + 1 + 1 + + + CLKFAIL + XOSC32K Clock Failure Detector Interrupt Enable + 2 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x4 + 32 + 0x00000000 + + + XOSC32KRDY + XOSC32K Ready Interrupt Enable + 0 + 1 + + + OSC32KRDY + OSC32K Ready Interrupt Enable + 1 + 1 + + + CLKFAIL + XOSC32K Clock Failure Detector Interrupt Enable + 2 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x8 + 32 + 0x00000000 + + + XOSC32KRDY + XOSC32K Ready + 0 + 1 + + + OSC32KRDY + OSC32K Ready + 1 + 1 + + + CLKFAIL + XOSC32K Clock Failure Detector + 2 + 1 + + + + + STATUS + Power and Clocks Status + 0xC + 32 + read-only + 0x00000000 + + + XOSC32KRDY + XOSC32K Ready + 0 + 1 + + + OSC32KRDY + OSC32K Ready + 1 + 1 + + + CLKFAIL + XOSC32K Clock Failure Detector + 2 + 1 + + + CLKSW + XOSC32K Clock switch + 3 + 1 + + + + + RTCCTRL + Clock selection + 0x10 + 32 + 0x00000000 + + + RTCSEL + RTC Clock Selection + 0 + 3 + + RTCSELSelect + + ULP1K + 1.024kHz from 32kHz internal ULP oscillator + 0 + + + ULP32K + 32.768kHz from 32kHz internal ULP oscillator + 1 + + + OSC1K + 1.024kHz from 32.768kHz internal oscillator + 2 + + + OSC32K + 32.768kHz from 32.768kHz internal oscillator + 3 + + + XOSC1K + 1.024kHz from 32.768kHz internal oscillator + 4 + + + XOSC32K + 32.768kHz from 32.768kHz external crystal oscillator + 5 + + + + + + + XOSC32K + 32kHz External Crystal Oscillator (XOSC32K) Control + 0x14 + 16 + 0x0080 + + + ENABLE + Oscillator Enable + 1 + 1 + + + XTALEN + Crystal Oscillator Enable + 2 + 1 + + + EN32K + 32kHz Output Enable + 3 + 1 + + + EN1K + 1kHz Output Enable + 4 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + STARTUP + Oscillator Start-Up Time + 8 + 3 + + STARTUPSelect + + CYCLE1 + 0.122 ms + 0 + + + CYCLE32 + 1.068 ms + 1 + + + CYCLE2048 + 62.6 ms + 2 + + + CYCLE4096 + 125 ms + 3 + + + CYCLE16384 + 500 ms + 4 + + + CYCLE32768 + 1000 ms + 5 + + + CYCLE65536 + 2000 ms + 6 + + + CYCLE131072 + 4000 ms + 7 + + + + + WRTLOCK + Write Lock + 12 + 1 + + + + + CFDCTRL + Clock Failure Detector Control + 0x16 + 8 + 0x00 + + + CFDEN + Clock Failure Detector Enable + 0 + 1 + + + SWBACK + Clock Switch Back + 1 + 1 + + + CFDPRESC + Clock Failure Detector Prescaler + 2 + 1 + + + + + EVCTRL + Event Control + 0x17 + 8 + 0x00 + + + CFDEO + Clock Failure Detector Event Output Enable + 0 + 1 + + + + + OSC32K + 32kHz Internal Oscillator (OSC32K) Control + 0x18 + 32 + 0x003F0080 + + + ENABLE + Oscillator Enable + 1 + 1 + + + EN32K + 32kHz Output Enable + 2 + 1 + + + EN1K + 1kHz Output Enable + 3 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + STARTUP + Oscillator Start-Up Time + 8 + 3 + + STARTUPSelect + + CYCLE3 + 0.092 ms + 0 + + + CYCLE4 + 0.122 ms + 1 + + + CYCLE6 + 0.183 ms + 2 + + + CYCLE10 + 0.305 ms + 3 + + + CYCLE18 + 0.549 ms + 4 + + + CYCLE34 + 1.038 ms + 5 + + + CYCLE66 + 2.014 ms + 6 + + + CYCLE130 + 3.967 ms + 7 + + + + + WRTLOCK + Write Lock + 12 + 1 + + + CALIB + Oscillator Calibration + 16 + 7 + + + + + OSCULP32K + 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control + 0x1C + 32 + + + CALIB + Oscillator Calibration + 8 + 5 + + + WRTLOCK + Write Lock + 15 + 1 + + + + + + + PAC + U21201.1.0 + Peripheral Access Controller + PAC + PAC_ + 0x40000000 + + 0 + 0x44 + registers + + + + WRCTRL + Write control + 0x0 + 32 + 0x00000000 + + + PERID + Peripheral identifier + 0 + 16 + + + KEY + Peripheral access control key + 16 + 8 + + KEYSelect + + OFF + No action + 0 + + + CLR + Clear protection + 1 + + + SET + Set protection + 2 + + + SETLCK + Set and lock protection + 3 + + + + + + + EVCTRL + Event control + 0x4 + 8 + 0x00 + + + ERREO + Peripheral acess error event output + 0 + 1 + + + + + INTENCLR + Interrupt enable clear + 0x8 + 8 + 0x00 + + + ERR + Peripheral access error interrupt disable + 0 + 1 + + + + + INTENSET + Interrupt enable set + 0x9 + 8 + 0x00 + + + ERR + Peripheral access error interrupt enable + 0 + 1 + + + + + INTFLAGAHB + Bridge interrupt flag status + 0x10 + 32 + 0x00000000 + + + FLASH_ + FLASH + 0 + 1 + + + HSRAMCM0P_ + HSRAMCM0P + 1 + 1 + + + HSRAMDSU_ + HSRAMDSU + 2 + 1 + + + HPB1_ + HPB1 + 3 + 1 + + + HPB0_ + HPB0 + 4 + 1 + + + HPB2_ + HPB2 + 5 + 1 + + + LPRAMDMAC_ + LPRAMDMAC + 6 + 1 + + + DIVAS_ + DIVAS + 7 + 1 + + + HPB3_ + HPB3 + 8 + 1 + + + + + INTFLAGA + Peripheral interrupt flag status - Bridge A + 0x14 + 32 + 0x00000000 + + + PAC_ + PAC + 0 + 1 + + + PM_ + PM + 1 + 1 + + + MCLK_ + MCLK + 2 + 1 + + + RSTC_ + RSTC + 3 + 1 + + + OSCCTRL_ + OSCCTRL + 4 + 1 + + + OSC32KCTRL_ + OSC32KCTRL + 5 + 1 + + + SUPC_ + SUPC + 6 + 1 + + + GCLK_ + GCLK + 7 + 1 + + + WDT_ + WDT + 8 + 1 + + + RTC_ + RTC + 9 + 1 + + + EIC_ + EIC + 10 + 1 + + + FREQM_ + FREQM + 11 + 1 + + + TSENS_ + TSENS + 12 + 1 + + + + + INTFLAGB + Peripheral interrupt flag status - Bridge B + 0x18 + 32 + 0x00000000 + + + PORT_ + PORT + 0 + 1 + + + DSU_ + DSU + 1 + 1 + + + NVMCTRL_ + NVMCTRL + 2 + 1 + + + DMAC_ + DMAC + 3 + 1 + + + MTB_ + MTB + 4 + 1 + + + HMATRIXHS_ + HMATRIXHS + 5 + 1 + + + + + INTFLAGC + Peripheral interrupt flag status - Bridge C + 0x1C + 32 + 0x00000000 + + + EVSYS_ + EVSYS + 0 + 1 + + + SERCOM0_ + SERCOM0 + 1 + 1 + + + SERCOM1_ + SERCOM1 + 2 + 1 + + + SERCOM2_ + SERCOM2 + 3 + 1 + + + SERCOM3_ + SERCOM3 + 4 + 1 + + + SERCOM4_ + SERCOM4 + 5 + 1 + + + SERCOM5_ + SERCOM5 + 6 + 1 + + + CAN0_ + CAN0 + 7 + 1 + + + CAN1_ + CAN1 + 8 + 1 + + + TCC0_ + TCC0 + 9 + 1 + + + TCC1_ + TCC1 + 10 + 1 + + + TCC2_ + TCC2 + 11 + 1 + + + TC0_ + TC0 + 12 + 1 + + + TC1_ + TC1 + 13 + 1 + + + TC2_ + TC2 + 14 + 1 + + + TC3_ + TC3 + 15 + 1 + + + TC4_ + TC4 + 16 + 1 + + + ADC0_ + ADC0 + 17 + 1 + + + ADC1_ + ADC1 + 18 + 1 + + + SDADC_ + SDADC + 19 + 1 + + + AC_ + AC + 20 + 1 + + + DAC_ + DAC + 21 + 1 + + + PTC_ + PTC + 22 + 1 + + + CCL_ + CCL + 23 + 1 + + + + + INTFLAGD + Peripheral interrupt flag status - Bridge D + 0x20 + 32 + 0x00000000 + + + SERCOM6_ + SERCOM6 + 0 + 1 + + + SERCOM7_ + SERCOM7 + 1 + 1 + + + TC5_ + TC5 + 2 + 1 + + + TC6_ + TC6 + 3 + 1 + + + TC7_ + TC7 + 4 + 1 + + + + + STATUSA + Peripheral write protection status - Bridge A + 0x34 + 32 + read-only + 0x00000000 + + + PAC_ + PAC APB Protect Enable + 0 + 1 + + + PM_ + PM APB Protect Enable + 1 + 1 + + + MCLK_ + MCLK APB Protect Enable + 2 + 1 + + + RSTC_ + RSTC APB Protect Enable + 3 + 1 + + + OSCCTRL_ + OSCCTRL APB Protect Enable + 4 + 1 + + + OSC32KCTRL_ + OSC32KCTRL APB Protect Enable + 5 + 1 + + + SUPC_ + SUPC APB Protect Enable + 6 + 1 + + + GCLK_ + GCLK APB Protect Enable + 7 + 1 + + + WDT_ + WDT APB Protect Enable + 8 + 1 + + + RTC_ + RTC APB Protect Enable + 9 + 1 + + + EIC_ + EIC APB Protect Enable + 10 + 1 + + + FREQM_ + FREQM APB Protect Enable + 11 + 1 + + + TSENS_ + TSENS APB Protect Enable + 12 + 1 + + + + + STATUSB + Peripheral write protection status - Bridge B + 0x38 + 32 + read-only + 0x00000002 + + + PORT_ + PORT APB Protect Enable + 0 + 1 + + + DSU_ + DSU APB Protect Enable + 1 + 1 + + + NVMCTRL_ + NVMCTRL APB Protect Enable + 2 + 1 + + + DMAC_ + DMAC APB Protect Enable + 3 + 1 + + + MTB_ + MTB APB Protect Enable + 4 + 1 + + + HMATRIXHS_ + HMATRIXHS APB Protect Enable + 5 + 1 + + + + + STATUSC + Peripheral write protection status - Bridge C + 0x3C + 32 + read-only + 0x02000000 + + + EVSYS_ + EVSYS APB Protect Enable + 0 + 1 + + + SERCOM0_ + SERCOM0 APB Protect Enable + 1 + 1 + + + SERCOM1_ + SERCOM1 APB Protect Enable + 2 + 1 + + + SERCOM2_ + SERCOM2 APB Protect Enable + 3 + 1 + + + SERCOM3_ + SERCOM3 APB Protect Enable + 4 + 1 + + + SERCOM4_ + SERCOM4 APB Protect Enable + 5 + 1 + + + SERCOM5_ + SERCOM5 APB Protect Enable + 6 + 1 + + + CAN0_ + CAN0 APB Protect Enable + 7 + 1 + + + CAN1_ + CAN1 APB Protect Enable + 8 + 1 + + + TCC0_ + TCC0 APB Protect Enable + 9 + 1 + + + TCC1_ + TCC1 APB Protect Enable + 10 + 1 + + + TCC2_ + TCC2 APB Protect Enable + 11 + 1 + + + TC0_ + TC0 APB Protect Enable + 12 + 1 + + + TC1_ + TC1 APB Protect Enable + 13 + 1 + + + TC2_ + TC2 APB Protect Enable + 14 + 1 + + + TC3_ + TC3 APB Protect Enable + 15 + 1 + + + TC4_ + TC4 APB Protect Enable + 16 + 1 + + + ADC0_ + ADC0 APB Protect Enable + 17 + 1 + + + ADC1_ + ADC1 APB Protect Enable + 18 + 1 + + + SDADC_ + SDADC APB Protect Enable + 19 + 1 + + + AC_ + AC APB Protect Enable + 20 + 1 + + + DAC_ + DAC APB Protect Enable + 21 + 1 + + + PTC_ + PTC APB Protect Enable + 22 + 1 + + + CCL_ + CCL APB Protect Enable + 23 + 1 + + + + + STATUSD + Peripheral write protection status - Bridge D + 0x40 + 32 + read-only + 0x00000000 + + + SERCOM6_ + SERCOM6 APB Protect Enable + 0 + 1 + + + SERCOM7_ + SERCOM7 APB Protect Enable + 1 + 1 + + + TC5_ + TC5 APB Protect Enable + 2 + 1 + + + TC6_ + TC6 APB Protect Enable + 3 + 1 + + + TC7_ + TC7 APB Protect Enable + 4 + 1 + + + + + + + PM + U22402.1.1 + Power Manager + PM + PM_ + 0x40000400 + + 0 + 0xA + registers + + + + SLEEPCFG + Sleep Configuration + 0x1 + 8 + 0x00 + + + SLEEPMODE + Sleep Mode + 0 + 3 + + SLEEPMODESelect + + IDLE0 + CPU clock is OFF + 0 + + + IDLE1 + AHB clock is OFF + 1 + + + IDLE2 + APB clock are OFF + 2 + + + STANDBY + All Clocks are OFF + 4 + + + BACKUP + Only Backup domain is powered ON + 5 + + + OFF + All power domains are powered OFF + 6 + + + + + + + STDBYCFG + Standby Configuration + 0x8 + 16 + 0x0400 + + + VREGSMOD + Voltage Regulator Standby mode + 6 + 2 + + VREGSMODSelect + + AUTO + Automatic mode + 0 + + + PERFORMANCE + Performance oriented + 1 + + + LP + Low Power oriented + 2 + + + + + BBIASHS + Back Bias for HMCRAMCHS + 10 + 2 + + + + + + + PORT + U22102.1.1 + Port Module + PORT + PORT_ + 0x41000000 + + 0 + 0x180 + registers + + + + 3 + 0x80 + GROUP[%s] + + 0x00 + + DIR + Data Direction + 0x0 + 32 + 0x00000000 + + + DIRCLR + Data Direction Clear + 0x4 + 32 + 0x00000000 + + + DIRSET + Data Direction Set + 0x8 + 32 + 0x00000000 + + + DIRTGL + Data Direction Toggle + 0xC + 32 + 0x00000000 + + + OUT + Data Output Value + 0x10 + 32 + 0x00000000 + + + OUTCLR + Data Output Value Clear + 0x14 + 32 + 0x00000000 + + + OUTSET + Data Output Value Set + 0x18 + 32 + 0x00000000 + + + OUTTGL + Data Output Value Toggle + 0x1C + 32 + 0x00000000 + + + IN + Data Input Value + 0x20 + 32 + read-only + 0x00000000 + + + CTRL + Control + 0x24 + 32 + 0x00000000 + + + SAMPLING + Input Sampling Mode + 0 + 32 + + + + + WRCONFIG + Write Configuration + 0x28 + 32 + write-only + 0x00000000 + + + PINMASK + Pin Mask for Multiple Pin Configuration + 0 + 16 + + + PMUXEN + Select Peripheral Multiplexer + 16 + 1 + + + INEN + Input Enable + 17 + 1 + + + PULLEN + Pull Enable + 18 + 1 + + + DRVSTR + Output Driver Strength Selection + 22 + 1 + + + PMUX + Peripheral Multiplexing Template + 24 + 4 + + + WRPMUX + Write PMUX Registers + 28 + 1 + + + WRPINCFG + Write PINCFG Registers + 30 + 1 + + + HWSEL + Half-Word Select + 31 + 1 + + + + + EVCTRL + Event Input Control + 0x2C + 32 + 0x00000000 + + + PID0 + Port Event Pin Identifier 0 + 0 + 5 + + + EVACT0 + Port Event Action 0 + 5 + 2 + + EVACT0Select + + OUT + Event output to pin + 0x0 + + + SET + Set output register of pin on event + 0x1 + + + CLR + Clear output register of pin on event + 0x2 + + + TGL + Toggle output register of pin on event + 0x3 + + + + + PORTEI0 + Port Event Enable Input 0 + 7 + 1 + + + PID1 + Port Event Pin Identifier 1 + 8 + 5 + + + EVACT1 + Port Event Action 1 + 13 + 2 + + + PORTEI1 + Port Event Enable Input 1 + 15 + 1 + + + PID2 + Port Event Pin Identifier 2 + 16 + 5 + + + EVACT2 + Port Event Action 2 + 21 + 2 + + + PORTEI2 + Port Event Enable Input 2 + 23 + 1 + + + PID3 + Port Event Pin Identifier 3 + 24 + 5 + + + EVACT3 + Port Event Action 3 + 29 + 2 + + + PORTEI3 + Port Event Enable Input 3 + 31 + 1 + + + + + 16 + 1 + PMUX[%s] + Peripheral Multiplexing n + 0x30 + 8 + 0x00 + + + PMUXE + Peripheral Multiplexing for Even-Numbered Pin + 0 + 4 + + + PMUXO + Peripheral Multiplexing for Odd-Numbered Pin + 4 + 4 + + + + + 32 + 1 + PINCFG[%s] + Pin Configuration n + 0x40 + 8 + 0x00 + + + PMUXEN + Select Peripheral Multiplexer + 0 + 1 + + + INEN + Input Enable + 1 + 1 + + + PULLEN + Pull Enable + 2 + 1 + + + DRVSTR + Output Driver Strength Selection + 6 + 1 + + + + + + + + PORT_IOBUS + PORT_IOBUS_ + 0x60000000 + + + PTC + U22153.2.0 + Peripheral Touch Controller + PTC + PTC_ + 0x42005800 + + 0 + 0x1 + reserved + + + PTC + 30 + + + + RSTC + U22392.0.2 + Reset Controller + RSTC + RSTC_ + 0x40000C00 + + 0 + 0x1 + registers + + + + RCAUSE + Reset Cause + 0x0 + 8 + read-only + + + POR + Power On Reset + 0 + 1 + + + BODCORE + Brown Out CORE Detector Reset + 1 + 1 + + + BODVDD + Brown Out VDD Detector Reset + 2 + 1 + + + EXT + External Reset + 4 + 1 + + + WDT + Watchdog Reset + 5 + 1 + + + SYST + System Reset Request + 6 + 1 + + + + + + + RTC + U22501.1.1 + Real-Time Counter + RTC + RTC_ + 0x40002400 + + 0 + 0x25 + registers + + + RTC + 2 + + + + MODE0 + 32-bit Counter with Single 32-bit Compare + RtcMode0 + 0x0 + + CTRLA + MODE0 Control A + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 2 + + MODESelect + + COUNT32 + Mode 0: 32-bit Counter + 0x0 + + + COUNT16 + Mode 1: 16-bit Counter + 0x1 + + + CLOCK + Mode 2: Clock/Calendar + 0x2 + + + + + MATCHCLR + Clear on Match + 7 + 1 + + + PRESCALER + Prescaler + 8 + 4 + + PRESCALERSelect + + OFF + CLK_RTC_CNT = GCLK_RTC/1 + 0x0 + + + DIV1 + CLK_RTC_CNT = GCLK_RTC/1 + 0x1 + + + DIV2 + CLK_RTC_CNT = GCLK_RTC/2 + 0x2 + + + DIV4 + CLK_RTC_CNT = GCLK_RTC/4 + 0x3 + + + DIV8 + CLK_RTC_CNT = GCLK_RTC/8 + 0x4 + + + DIV16 + CLK_RTC_CNT = GCLK_RTC/16 + 0x5 + + + DIV32 + CLK_RTC_CNT = GCLK_RTC/32 + 0x6 + + + DIV64 + CLK_RTC_CNT = GCLK_RTC/64 + 0x7 + + + DIV128 + CLK_RTC_CNT = GCLK_RTC/128 + 0x8 + + + DIV256 + CLK_RTC_CNT = GCLK_RTC/256 + 0x9 + + + DIV512 + CLK_RTC_CNT = GCLK_RTC/512 + 0xA + + + DIV1024 + CLK_RTC_CNT = GCLK_RTC/1024 + 0xB + + + + + COUNTSYNC + Count Read Synchronization Enable + 15 + 1 + + + + + EVCTRL + MODE0 Event Control + 0x4 + 32 + 0x00000000 + + + PEREO0 + Periodic Interval 0 Event Output Enable + 0 + 1 + + + PEREO1 + Periodic Interval 1 Event Output Enable + 1 + 1 + + + PEREO2 + Periodic Interval 2 Event Output Enable + 2 + 1 + + + PEREO3 + Periodic Interval 3 Event Output Enable + 3 + 1 + + + PEREO4 + Periodic Interval 4 Event Output Enable + 4 + 1 + + + PEREO5 + Periodic Interval 5 Event Output Enable + 5 + 1 + + + PEREO6 + Periodic Interval 6 Event Output Enable + 6 + 1 + + + PEREO7 + Periodic Interval 7 Event Output Enable + 7 + 1 + + + CMPEO0 + Compare 0 Event Output Enable + 8 + 1 + + + OVFEO + Overflow Event Output Enable + 15 + 1 + + + + + INTENCLR + MODE0 Interrupt Enable Clear + 0x8 + 16 + 0x0000 + + + PER0 + Periodic Interval 0 Interrupt Enable + 0 + 1 + + + PER1 + Periodic Interval 1 Interrupt Enable + 1 + 1 + + + PER2 + Periodic Interval 2 Interrupt Enable + 2 + 1 + + + PER3 + Periodic Interval 3 Interrupt Enable + 3 + 1 + + + PER4 + Periodic Interval 4 Interrupt Enable + 4 + 1 + + + PER5 + Periodic Interval 5 Interrupt Enable + 5 + 1 + + + PER6 + Periodic Interval 6 Interrupt Enable + 6 + 1 + + + PER7 + Periodic Interval 7 Interrupt Enable + 7 + 1 + + + CMP0 + Compare 0 Interrupt Enable + 8 + 1 + + + OVF + Overflow Interrupt Enable + 15 + 1 + + + + + INTENSET + MODE0 Interrupt Enable Set + 0xA + 16 + 0x0000 + + + PER0 + Periodic Interval 0 Interrupt Enable + 0 + 1 + + + PER1 + Periodic Interval 1 Interrupt Enable + 1 + 1 + + + PER2 + Periodic Interval 2 Interrupt Enable + 2 + 1 + + + PER3 + Periodic Interval 3 Interrupt Enable + 3 + 1 + + + PER4 + Periodic Interval 4 Interrupt Enable + 4 + 1 + + + PER5 + Periodic Interval 5 Interrupt Enable + 5 + 1 + + + PER6 + Periodic Interval 6 Interrupt Enable + 6 + 1 + + + PER7 + Periodic Interval 7 Interrupt Enable + 7 + 1 + + + CMP0 + Compare 0 Interrupt Enable + 8 + 1 + + + OVF + Overflow Interrupt Enable + 15 + 1 + + + + + INTFLAG + MODE0 Interrupt Flag Status and Clear + 0xC + 16 + 0x0000 + + + PER0 + Periodic Interval 0 + 0 + 1 + + + PER1 + Periodic Interval 1 + 1 + 1 + + + PER2 + Periodic Interval 2 + 2 + 1 + + + PER3 + Periodic Interval 3 + 3 + 1 + + + PER4 + Periodic Interval 4 + 4 + 1 + + + PER5 + Periodic Interval 5 + 5 + 1 + + + PER6 + Periodic Interval 6 + 6 + 1 + + + PER7 + Periodic Interval 7 + 7 + 1 + + + CMP0 + Compare 0 + 8 + 1 + + + OVF + Overflow + 15 + 1 + + + + + DBGCTRL + Debug Control + 0xE + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + SYNCBUSY + MODE0 Synchronization Busy Status + 0x10 + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Busy + 0 + 1 + + + ENABLE + Enable Bit Busy + 1 + 1 + + + FREQCORR + FREQCORR Register Busy + 2 + 1 + + + COUNT + COUNT Register Busy + 3 + 1 + + + COMP0 + COMP 0 Register Busy + 5 + 1 + + + COUNTSYNC + Count Read Synchronization Enable Bit Busy + 15 + 1 + + + + + FREQCORR + Frequency Correction + 0x14 + 8 + 0x00 + + + VALUE + Correction Value + 0 + 7 + + + SIGN + Correction Sign + 7 + 1 + + + + + COUNT + MODE0 Counter Value + 0x18 + 32 + 0x00000000 + + + COUNT + Counter Value + 0 + 32 + + + + + COMP + MODE0 Compare n Value + 0x20 + 32 + 0x00000000 + + + COMP + Compare Value + 0 + 32 + + + + + + MODE1 + 16-bit Counter with Two 16-bit Compares + MODE0 + RtcMode1 + 0x0 + + CTRLA + MODE1 Control A + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 2 + + MODESelect + + COUNT32 + Mode 0: 32-bit Counter + 0 + + + COUNT16 + Mode 1: 16-bit Counter + 1 + + + CLOCK + Mode 2: Clock/Calendar + 2 + + + + + PRESCALER + Prescaler + 8 + 4 + + PRESCALERSelect + + OFF + CLK_RTC_CNT = GCLK_RTC/1 + 0 + + + DIV1 + CLK_RTC_CNT = GCLK_RTC/1 + 1 + + + DIV2 + CLK_RTC_CNT = GCLK_RTC/2 + 2 + + + DIV4 + CLK_RTC_CNT = GCLK_RTC/4 + 3 + + + DIV8 + CLK_RTC_CNT = GCLK_RTC/8 + 4 + + + DIV16 + CLK_RTC_CNT = GCLK_RTC/16 + 5 + + + DIV32 + CLK_RTC_CNT = GCLK_RTC/32 + 6 + + + DIV64 + CLK_RTC_CNT = GCLK_RTC/64 + 7 + + + DIV128 + CLK_RTC_CNT = GCLK_RTC/128 + 8 + + + DIV256 + CLK_RTC_CNT = GCLK_RTC/256 + 9 + + + DIV512 + CLK_RTC_CNT = GCLK_RTC/512 + 0xA + + + DIV1024 + CLK_RTC_CNT = GCLK_RTC/1024 + 0xB + + + + + COUNTSYNC + Count Read Synchronization Enable + 15 + 1 + + + + + EVCTRL + MODE1 Event Control + 0x4 + 32 + 0x00000000 + + + PEREO0 + Periodic Interval 0 Event Output Enable + 0 + 1 + + + PEREO1 + Periodic Interval 1 Event Output Enable + 1 + 1 + + + PEREO2 + Periodic Interval 2 Event Output Enable + 2 + 1 + + + PEREO3 + Periodic Interval 3 Event Output Enable + 3 + 1 + + + PEREO4 + Periodic Interval 4 Event Output Enable + 4 + 1 + + + PEREO5 + Periodic Interval 5 Event Output Enable + 5 + 1 + + + PEREO6 + Periodic Interval 6 Event Output Enable + 6 + 1 + + + PEREO7 + Periodic Interval 7 Event Output Enable + 7 + 1 + + + CMPEO0 + Compare 0 Event Output Enable + 8 + 1 + + + CMPEO1 + Compare 1 Event Output Enable + 9 + 1 + + + OVFEO + Overflow Event Output Enable + 15 + 1 + + + + + INTENCLR + MODE1 Interrupt Enable Clear + 0x8 + 16 + 0x0000 + + + PER0 + Periodic Interval 0 Interrupt Enable + 0 + 1 + + + PER1 + Periodic Interval 1 Interrupt Enable + 1 + 1 + + + PER2 + Periodic Interval 2 Interrupt Enable + 2 + 1 + + + PER3 + Periodic Interval 3 Interrupt Enable + 3 + 1 + + + PER4 + Periodic Interval 4 Interrupt Enable + 4 + 1 + + + PER5 + Periodic Interval 5 Interrupt Enable + 5 + 1 + + + PER6 + Periodic Interval 6 Interrupt Enable + 6 + 1 + + + PER7 + Periodic Interval 7 Interrupt Enable + 7 + 1 + + + CMP0 + Compare 0 Interrupt Enable + 8 + 1 + + + CMP1 + Compare 1 Interrupt Enable + 9 + 1 + + + OVF + Overflow Interrupt Enable + 15 + 1 + + + + + INTENSET + MODE1 Interrupt Enable Set + 0xA + 16 + 0x0000 + + + PER0 + Periodic Interval 0 Interrupt Enable + 0 + 1 + + + PER1 + Periodic Interval 1 Interrupt Enable + 1 + 1 + + + PER2 + Periodic Interval 2 Interrupt Enable + 2 + 1 + + + PER3 + Periodic Interval 3 Interrupt Enable + 3 + 1 + + + PER4 + Periodic Interval 4 Interrupt Enable + 4 + 1 + + + PER5 + Periodic Interval 5 Interrupt Enable + 5 + 1 + + + PER6 + Periodic Interval 6 Interrupt Enable + 6 + 1 + + + PER7 + Periodic Interval 7 Interrupt Enable + 7 + 1 + + + CMP0 + Compare 0 Interrupt Enable + 8 + 1 + + + CMP1 + Compare 1 Interrupt Enable + 9 + 1 + + + OVF + Overflow Interrupt Enable + 15 + 1 + + + + + INTFLAG + MODE1 Interrupt Flag Status and Clear + 0xC + 16 + 0x0000 + + + PER0 + Periodic Interval 0 + 0 + 1 + + + PER1 + Periodic Interval 1 + 1 + 1 + + + PER2 + Periodic Interval 2 + 2 + 1 + + + PER3 + Periodic Interval 3 + 3 + 1 + + + PER4 + Periodic Interval 4 + 4 + 1 + + + PER5 + Periodic Interval 5 + 5 + 1 + + + PER6 + Periodic Interval 6 + 6 + 1 + + + PER7 + Periodic Interval 7 + 7 + 1 + + + CMP0 + Compare 0 + 8 + 1 + + + CMP1 + Compare 1 + 9 + 1 + + + OVF + Overflow + 15 + 1 + + + + + DBGCTRL + Debug Control + 0xE + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + SYNCBUSY + MODE1 Synchronization Busy Status + 0x10 + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Bit Busy + 0 + 1 + + + ENABLE + Enable Bit Busy + 1 + 1 + + + FREQCORR + FREQCORR Register Busy + 2 + 1 + + + COUNT + COUNT Register Busy + 3 + 1 + + + PER + PER Register Busy + 4 + 1 + + + COMP0 + COMP 0 Register Busy + 5 + 1 + + + COMP1 + COMP 1 Register Busy + 6 + 1 + + + COUNTSYNC + Count Read Synchronization Enable Bit Busy + 15 + 1 + + + + + FREQCORR + Frequency Correction + 0x14 + 8 + 0x00 + + + VALUE + Correction Value + 0 + 7 + + + SIGN + Correction Sign + 7 + 1 + + + + + COUNT + MODE1 Counter Value + 0x18 + 16 + 0x0000 + + + COUNT + Counter Value + 0 + 16 + + + + + PER + MODE1 Counter Period + 0x1C + 16 + 0x0000 + + + PER + Counter Period + 0 + 16 + + + + + 2 + 2 + COMP[%s] + MODE1 Compare n Value + 0x20 + 16 + 0x0000 + + + COMP + Compare Value + 0 + 16 + + + + + + MODE2 + Clock/Calendar with Alarm + MODE0 + RtcMode2 + 0x0 + + CTRLA + MODE2 Control A + 0x0 + 16 + 0x0000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 2 + + MODESelect + + COUNT32 + Mode 0: 32-bit Counter + 0 + + + COUNT16 + Mode 1: 16-bit Counter + 1 + + + CLOCK + Mode 2: Clock/Calendar + 2 + + + + + CLKREP + Clock Representation + 6 + 1 + + + MATCHCLR + Clear on Match + 7 + 1 + + + PRESCALER + Prescaler + 8 + 4 + + PRESCALERSelect + + OFF + CLK_RTC_CNT = GCLK_RTC/1 + 0x0 + + + DIV1 + CLK_RTC_CNT = GCLK_RTC/1 + 0x1 + + + DIV2 + CLK_RTC_CNT = GCLK_RTC/2 + 0x2 + + + DIV4 + CLK_RTC_CNT = GCLK_RTC/4 + 0x3 + + + DIV8 + CLK_RTC_CNT = GCLK_RTC/8 + 0x4 + + + DIV16 + CLK_RTC_CNT = GCLK_RTC/16 + 0x5 + + + DIV32 + CLK_RTC_CNT = GCLK_RTC/32 + 0x6 + + + DIV64 + CLK_RTC_CNT = GCLK_RTC/64 + 0x7 + + + DIV128 + CLK_RTC_CNT = GCLK_RTC/128 + 0x8 + + + DIV256 + CLK_RTC_CNT = GCLK_RTC/256 + 0x9 + + + DIV512 + CLK_RTC_CNT = GCLK_RTC/512 + 0xA + + + DIV1024 + CLK_RTC_CNT = GCLK_RTC/1024 + 0xB + + + + + CLOCKSYNC + Clock Read Synchronization Enable + 15 + 1 + + + + + EVCTRL + MODE2 Event Control + 0x4 + 32 + 0x00000000 + + + PEREO0 + Periodic Interval 0 Event Output Enable + 0 + 1 + + + PEREO1 + Periodic Interval 1 Event Output Enable + 1 + 1 + + + PEREO2 + Periodic Interval 2 Event Output Enable + 2 + 1 + + + PEREO3 + Periodic Interval 3 Event Output Enable + 3 + 1 + + + PEREO4 + Periodic Interval 4 Event Output Enable + 4 + 1 + + + PEREO5 + Periodic Interval 5 Event Output Enable + 5 + 1 + + + PEREO6 + Periodic Interval 6 Event Output Enable + 6 + 1 + + + PEREO7 + Periodic Interval 7 Event Output Enable + 7 + 1 + + + ALARMEO0 + Alarm 0 Event Output Enable + 8 + 1 + + + OVFEO + Overflow Event Output Enable + 15 + 1 + + + + + INTENCLR + MODE2 Interrupt Enable Clear + 0x8 + 16 + 0x0000 + + + PER0 + Periodic Interval 0 Interrupt Enable + 0 + 1 + + + PER1 + Periodic Interval 1 Interrupt Enable + 1 + 1 + + + PER2 + Periodic Interval 2 Interrupt Enable + 2 + 1 + + + PER3 + Periodic Interval 3 Interrupt Enable + 3 + 1 + + + PER4 + Periodic Interval 4 Interrupt Enable + 4 + 1 + + + PER5 + Periodic Interval 5 Interrupt Enable + 5 + 1 + + + PER6 + Periodic Interval 6 Interrupt Enable + 6 + 1 + + + PER7 + Periodic Interval 7 Interrupt Enable + 7 + 1 + + + ALARM0 + Alarm 0 Interrupt Enable + 8 + 1 + + + OVF + Overflow Interrupt Enable + 15 + 1 + + + + + INTENSET + MODE2 Interrupt Enable Set + 0xA + 16 + 0x0000 + + + PER0 + Periodic Interval 0 Enable + 0 + 1 + + + PER1 + Periodic Interval 1 Enable + 1 + 1 + + + PER2 + Periodic Interval 2 Enable + 2 + 1 + + + PER3 + Periodic Interval 3 Enable + 3 + 1 + + + PER4 + Periodic Interval 4 Enable + 4 + 1 + + + PER5 + Periodic Interval 5 Enable + 5 + 1 + + + PER6 + Periodic Interval 6 Enable + 6 + 1 + + + PER7 + Periodic Interval 7 Enable + 7 + 1 + + + ALARM0 + Alarm 0 Interrupt Enable + 8 + 1 + + + OVF + Overflow Interrupt Enable + 15 + 1 + + + + + INTFLAG + MODE2 Interrupt Flag Status and Clear + 0xC + 16 + 0x0000 + + + PER0 + Periodic Interval 0 + 0 + 1 + + + PER1 + Periodic Interval 1 + 1 + 1 + + + PER2 + Periodic Interval 2 + 2 + 1 + + + PER3 + Periodic Interval 3 + 3 + 1 + + + PER4 + Periodic Interval 4 + 4 + 1 + + + PER5 + Periodic Interval 5 + 5 + 1 + + + PER6 + Periodic Interval 6 + 6 + 1 + + + PER7 + Periodic Interval 7 + 7 + 1 + + + ALARM0 + Alarm 0 + 8 + 1 + + + OVF + Overflow + 15 + 1 + + + + + DBGCTRL + Debug Control + 0xE + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + SYNCBUSY + MODE2 Synchronization Busy Status + 0x10 + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Bit Busy + 0 + 1 + + + ENABLE + Enable Bit Busy + 1 + 1 + + + FREQCORR + FREQCORR Register Busy + 2 + 1 + + + CLOCK + CLOCK Register Busy + 3 + 1 + + + ALARM0 + ALARM 0 Register Busy + 5 + 1 + + + MASK0 + MASK 0 Register Busy + 11 + 1 + + + CLOCKSYNC + Clock Read Synchronization Enable Bit Busy + 15 + 1 + + + + + FREQCORR + Frequency Correction + 0x14 + 8 + 0x00 + + + VALUE + Correction Value + 0 + 7 + + + SIGN + Correction Sign + 7 + 1 + + + + + CLOCK + MODE2 Clock Value + 0x18 + 32 + 0x00000000 + + + SECOND + Second + 0 + 6 + + + MINUTE + Minute + 6 + 6 + + + HOUR + Hour + 12 + 5 + + HOURSelect + + AM + AM when CLKREP in 12-hour + 0x00 + + + PM + PM when CLKREP in 12-hour + 0x10 + + + + + DAY + Day + 17 + 5 + + + MONTH + Month + 22 + 4 + + + YEAR + Year + 26 + 6 + + + + + ALARM + MODE2_ALARM Alarm n Value + 0x20 + 32 + 0x00000000 + + + SECOND + Second + 0 + 6 + + + MINUTE + Minute + 6 + 6 + + + HOUR + Hour + 12 + 5 + + HOURSelect + + AM + Morning hour + 0x00 + + + PM + Afternoon hour + 0x10 + + + + + DAY + Day + 17 + 5 + + + MONTH + Month + 22 + 4 + + + YEAR + Year + 26 + 6 + + + + + MASK + MODE2_ALARM Alarm n Mask + 0x24 + 8 + 0x00 + + + SEL + Alarm Mask Selection + 0 + 3 + + SELSelect + + OFF + Alarm Disabled + 0x0 + + + SS + Match seconds only + 0x1 + + + MMSS + Match seconds and minutes only + 0x2 + + + HHMMSS + Match seconds, minutes, and hours only + 0x3 + + + DDHHMMSS + Match seconds, minutes, hours, and days only + 0x4 + + + MMDDHHMMSS + Match seconds, minutes, hours, days, and months only + 0x5 + + + YYMMDDHHMMSS + Match seconds, minutes, hours, days, months, and years + 0x6 + + + + + + + + + + SDADC + U22601.0.1 + Sigma-Delta Analog Digital Converter + SDADC + SDADC_ + 0x42004C00 + + 0 + 0x2F + registers + + + SDADC + 29 + + + + CTRLA + Control A + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + RUNSTDBY + Run during Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + + + REFCTRL + Reference Control + 0x1 + 8 + 0x00 + + + REFSEL + Reference Selection + 0 + 2 + + REFSELSelect + + INTREF + Internal Bandgap Reference + 0 + + + AREFB + External Reference + 1 + + + DAC + Internal DAC Output + 2 + + + INTVCC + VDDANA + 3 + + + + + REFRANGE + Reference Range + 4 + 2 + + + ONREFBUF + Reference Buffer + 7 + 1 + + + + + CTRLB + Control B + 0x2 + 16 + 0x2000 + + + PRESCALER + Prescaler Configuration + 0 + 8 + + PRESCALERSelect + + DIV2 + Peripheral clock divided by 2 + 0x0 + + + DIV4 + Peripheral clock divided by 4 + 0x1 + + + DIV8 + Peripheral clock divided by 8 + 0x2 + + + DIV16 + Peripheral clock divided by 16 + 0x3 + + + DIV32 + Peripheral clock divided by 32 + 0x4 + + + DIV64 + Peripheral clock divided by 64 + 0x5 + + + DIV128 + Peripheral clock divided by 128 + 0x6 + + + DIV256 + Peripheral clock divided by 256 + 0x7 + + + + + OSR + Over Sampling Ratio + 8 + 3 + + OSRSelect + + OSR64 + Over Sampling Ratio is 64 + 0x0 + + + OSR128 + Over Sampling Ratio is 128 + 0x1 + + + OSR256 + Over Sampling Ratio is 256 + 0x2 + + + OSR512 + Over Sampling Ratio is 512 + 0x3 + + + OSR1024 + Over Sampling Ratio is 1024 + 0x4 + + + + + SKPCNT + Skip Sample Count + 12 + 4 + + + + + EVCTRL + Event Control + 0x4 + 8 + 0x00 + + + FLUSHEI + Flush Event Input Enable + 0 + 1 + + + STARTEI + Start Conversion Event Input Enable + 1 + 1 + + + FLUSHINV + Flush Event Invert Enable + 2 + 1 + + + STARTINV + Satrt Event Invert Enable + 3 + 1 + + + RESRDYEO + Result Ready Event Out + 4 + 1 + + + WINMONEO + Window Monitor Event Out + 5 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x5 + 8 + 0x00 + + + RESRDY + Result Ready Interrupt Disable + 0 + 1 + + + OVERRUN + Overrun Interrupt Disable + 1 + 1 + + + WINMON + Window Monitor Interrupt Disable + 2 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x6 + 8 + 0x00 + + + RESRDY + Result Ready Interrupt Enable + 0 + 1 + + + OVERRUN + Overrun Interrupt Enable + 1 + 1 + + + WINMON + Window Monitor Interrupt Enable + 2 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x7 + 8 + 0x00 + + + RESRDY + Result Ready Interrupt Flag + 0 + 1 + + + OVERRUN + Overrun Interrupt Flag + 1 + 1 + + + WINMON + Window Monitor Interrupt Flag + 2 + 1 + + + + + SEQSTATUS + Sequence Status + 0x8 + 8 + read-only + 0x00 + + + SEQSTATE + Sequence State + 0 + 4 + + + SEQBUSY + Sequence Busy + 7 + 1 + + + + + INPUTCTRL + Input Control + 0x9 + 8 + 0x00 + + + MUXSEL + SDADC Input Selection + 0 + 4 + + MUXSELSelect + + AIN0 + SDADC AIN0 Pin + 0x0 + + + AIN1 + SDADC AIN1 Pin + 0x1 + + + AIN2 + SDADC AIN2 Pin + 0x2 + + + + + + + CTRLC + Control C + 0xA + 8 + 0x00 + + + FREERUN + Free Running Mode + 0 + 1 + + + + + WINCTRL + Window Monitor Control + 0xB + 8 + 0x00 + + + WINMODE + Window Monitor Mode + 0 + 3 + + + + + WINLT + Window Monitor Lower Threshold + 0xC + 32 + 0x00000000 + + + WINLT + Window Lower Threshold + 0 + 24 + + + + + WINUT + Window Monitor Upper Threshold + 0x10 + 32 + 0x00000000 + + + WINUT + Window Upper Threshold + 0 + 24 + + + + + OFFSETCORR + Offset Correction + 0x14 + 32 + 0x00000000 + + + OFFSETCORR + Offset Correction Value + 0 + 24 + + + + + GAINCORR + Gain Correction + 0x18 + 16 + 0x0001 + + + GAINCORR + Gain Correction Value + 0 + 14 + + + + + SHIFTCORR + Shift Correction + 0x1A + 8 + 0x00 + + + SHIFTCORR + Shift Correction Value + 0 + 4 + + + + + SWTRIG + Software Trigger + 0x1C + 8 + 0x00 + + + FLUSH + SDADC Flush + 0 + 1 + + + START + Start SDADC Conversion + 1 + 1 + + + + + SYNCBUSY + Synchronization Busy + 0x20 + 32 + read-only + 0x00000000 + + + SWRST + SWRST Synchronization Busy + 0 + 1 + + + ENABLE + ENABLE Synchronization Busy + 1 + 1 + + + CTRLC + CTRLC Synchronization Busy + 2 + 1 + + + INPUTCTRL + INPUTCTRL Synchronization Busy + 3 + 1 + + + WINCTRL + WINCTRL Synchronization Busy + 4 + 1 + + + WINLT + WINLT Synchronization Busy + 5 + 1 + + + WINUT + WINUT Synchronization Busy + 6 + 1 + + + OFFSETCORR + OFFSETCTRL Synchronization Busy + 7 + 1 + + + GAINCORR + GAINCORR Synchronization Busy + 8 + 1 + + + SHIFTCORR + SHIFTCORR Synchronization Busy + 9 + 1 + + + SWTRIG + SWTRG Synchronization Busy + 10 + 1 + + + ANACTRL + ANACTRL Synchronization Busy + 11 + 1 + + + + + RESULT + Result + 0x24 + 32 + read-only + 0x00000000 + + + RESULT + Result Value + 0 + 24 + + + RESERVED + 24 + 8 + + + + + SEQCTRL + Sequence Control + 0x28 + 8 + 0x00 + + + SEQEN + Enable Positive Input in the Sequence + 0 + 3 + + + + + ANACTRL + Analog Control + 0x2C + 8 + 0x00 + + + CTRSDADC + SDADC Control + 0 + 6 + + + ONCHOP + Chopper + 6 + 1 + + + BUFTEST + BUFTEST + 7 + 1 + + + + + DBGCTRL + Debug Control + 0x2E + 8 + 0x00 + + + DBGRUN + Debug Run + 0 + 1 + + + + + + + SERCOM0 + U22013.2.0 + Serial Communication Interface + SERCOM + SERCOM_ + 0x42000400 + + 0 + 0x31 + registers + + + + I2CM + I2C Master Mode + SercomI2cm + 0x0 + + CTRLA + I2CM Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run in Standby + 7 + 1 + + + PINOUT + Pin Usage + 16 + 1 + + + SDAHOLD + SDA Hold Time + 20 + 2 + + SDAHOLDSelect + + DISABLE + Disabled + 0x0 + + + 75NS + 50-100ns hold time + 0x1 + + + 450NS + 300-600ns hold time + 0x2 + + + 600NS + 400-800ns hold time + 0x3 + + + + + MEXTTOEN + Master SCL Low Extend Timeout + 22 + 1 + + + SEXTTOEN + Slave SCL Low Extend Timeout + 23 + 1 + + + SPEED + Transfer Speed + 24 + 2 + + SPEEDSelect + + STANDARD_AND_FAST_MODE + Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz + 0x0 + + + FASTPLUS_MODE + Fast-mode Plus Upto 1MHz + 0x1 + + + HIGH_SPEED_MODE + High-speed mode Upto 3.4MHz + 0x2 + + + + + SCLSM + SCL Clock Stretch Mode + 27 + 1 + + + INACTOUT + Inactive Time-Out + 28 + 2 + + INACTOUTSelect + + DISABLE + Disabled + 0x0 + + + 55US + 5-6 SCL Time-Out(50-60us) + 0x1 + + + 105US + 10-11 SCL Time-Out(100-110us) + 0x2 + + + 205US + 20-21 SCL Time-Out(200-210us) + 0x3 + + + + + LOWTOUTEN + SCL Low Timeout Enable + 30 + 1 + + + + + CTRLB + I2CM Control B + 0x4 + 32 + 0x00000000 + + + SMEN + Smart Mode Enable + 8 + 1 + + + QCEN + Quick Command Enable + 9 + 1 + + + CMD + Command + 16 + 2 + + + ACKACT + Acknowledge Action + 18 + 1 + + + + + BAUD + I2CM Baud Rate + 0xC + 32 + 0x00000000 + + + BAUD + Baud Rate Value + 0 + 8 + + + BAUDLOW + Baud Rate Value Low + 8 + 8 + + + HSBAUD + High Speed Baud Rate Value + 16 + 8 + + + HSBAUDLOW + High Speed Baud Rate Value Low + 24 + 8 + + + + + INTENCLR + I2CM Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + MB + Master On Bus Interrupt Disable + 0 + 1 + + + SB + Slave On Bus Interrupt Disable + 1 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + I2CM Interrupt Enable Set + 0x16 + 8 + 0x00 + + + MB + Master On Bus Interrupt Enable + 0 + 1 + + + SB + Slave On Bus Interrupt Enable + 1 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + I2CM Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + MB + Master On Bus Interrupt + 0 + 1 + + + SB + Slave On Bus Interrupt + 1 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + I2CM Status + 0x1A + 16 + 0x0000 + + + BUSERR + Bus Error + 0 + 1 + + + ARBLOST + Arbitration Lost + 1 + 1 + + + RXNACK + Received Not Acknowledge + 2 + 1 + + + BUSSTATE + Bus State + 4 + 2 + + + LOWTOUT + SCL Low Timeout + 6 + 1 + + + CLKHOLD + Clock Hold + 7 + 1 + + + MEXTTOUT + Master SCL Low Extend Timeout + 8 + 1 + + + SEXTTOUT + Slave SCL Low Extend Timeout + 9 + 1 + + + LENERR + Length Error + 10 + 1 + + + + + SYNCBUSY + I2CM Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + SYSOP + System Operation Synchronization Busy + 2 + 1 + + + + + ADDR + I2CM Address + 0x24 + 32 + 0x00000000 + + + ADDR + Address Value + 0 + 11 + + + LENEN + Length Enable + 13 + 1 + + + HS + High Speed Mode + 14 + 1 + + + TENBITEN + Ten Bit Addressing Enable + 15 + 1 + + + LEN + Length + 16 + 8 + + + + + DATA + I2CM Data + 0x28 + 8 + 0x00 + + + DATA + Data Value + 0 + 8 + + + + + DBGCTRL + I2CM Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + I2CS + I2C Slave Mode + I2CM + SercomI2cs + 0x0 + + CTRLA + I2CS Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + PINOUT + Pin Usage + 16 + 1 + + + SDAHOLD + SDA Hold Time + 20 + 2 + + SDAHOLDSelect + + DISABLE + Disabled + 0x0 + + + 75NS + 50-100ns hold time + 0x1 + + + 450NS + 300-600ns hold time + 0x2 + + + 600NS + 400-800ns hold time + 0x3 + + + + + SEXTTOEN + Slave SCL Low Extend Timeout + 23 + 1 + + + SPEED + Transfer Speed + 24 + 2 + + SPEEDSelect + + STANDARD_AND_FAST_MODE + Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz + 0x0 + + + FASTPLUS_MODE + Fast-mode Plus Upto 1MHz + 0x1 + + + HIGH_SPEED_MODE + High-speed mode Upto 3.4MHz + 0x2 + + + + + SCLSM + SCL Clock Stretch Mode + 27 + 1 + + + LOWTOUTEN + SCL Low Timeout Enable + 30 + 1 + + + + + CTRLB + I2CS Control B + 0x4 + 32 + 0x00000000 + + + SMEN + Smart Mode Enable + 8 + 1 + + + GCMD + PMBus Group Command + 9 + 1 + + + AACKEN + Automatic Address Acknowledge + 10 + 1 + + + AMODE + Address Mode + 14 + 2 + + + CMD + Command + 16 + 2 + + + ACKACT + Acknowledge Action + 18 + 1 + + + + + INTENCLR + I2CS Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + PREC + Stop Received Interrupt Disable + 0 + 1 + + + AMATCH + Address Match Interrupt Disable + 1 + 1 + + + DRDY + Data Interrupt Disable + 2 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + I2CS Interrupt Enable Set + 0x16 + 8 + 0x00 + + + PREC + Stop Received Interrupt Enable + 0 + 1 + + + AMATCH + Address Match Interrupt Enable + 1 + 1 + + + DRDY + Data Interrupt Enable + 2 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + I2CS Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + PREC + Stop Received Interrupt + 0 + 1 + + + AMATCH + Address Match Interrupt + 1 + 1 + + + DRDY + Data Interrupt + 2 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + I2CS Status + 0x1A + 16 + 0x0000 + + + BUSERR + Bus Error + 0 + 1 + + + COLL + Transmit Collision + 1 + 1 + + + RXNACK + Received Not Acknowledge + 2 + 1 + + + DIR + Read/Write Direction + 3 + 1 + + + SR + Repeated Start + 4 + 1 + + + LOWTOUT + SCL Low Timeout + 6 + 1 + + + CLKHOLD + Clock Hold + 7 + 1 + + + SEXTTOUT + Slave SCL Low Extend Timeout + 9 + 1 + + + HS + High Speed + 10 + 1 + + + + + SYNCBUSY + I2CS Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + + + ADDR + I2CS Address + 0x24 + 32 + 0x00000000 + + + GENCEN + General Call Address Enable + 0 + 1 + + + ADDR + Address Value + 1 + 10 + + + TENBITEN + Ten Bit Addressing Enable + 15 + 1 + + + ADDRMASK + Address Mask + 17 + 10 + + + + + DATA + I2CS Data + 0x28 + 8 + 0x00 + + + DATA + Data Value + 0 + 8 + + + + + + SPIS + SPI Slave Mode + I2CM + SercomSpis + 0x0 + + CTRLA + SPIS Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + IBON + Immediate Buffer Overflow Notification + 8 + 1 + + + DOPO + Data Out Pinout + 16 + 2 + + DOPOSelect + + PAD0 + DO on PAD[0], SCK on PAD[1] and SS on PAD[2] + 0x0 + + + PAD1 + DO on PAD[2], SCK on PAD[3] and SS on PAD[1] + 0x1 + + + PAD2 + DO on PAD[3], SCK on PAD[1] and SS on PAD[2] + 0x2 + + + PAD3 + DO on PAD[0], SCK on PAD[3] and SS on PAD[1] + 0x3 + + + + + DIPO + Data In Pinout + 20 + 2 + + DIPOSelect + + PAD0 + SERCOM PAD[0] + 0x0 + + + PAD1 + SERCOM PAD[1] + 0x1 + + + PAD2 + SERCOM PAD[2] + 0x2 + + + PAD3 + SERCOM PAD[3] + 0x3 + + + + + FORM + Frame Format + 24 + 4 + + FORMSelect + + SPI_FRAME + SPI Frame + 0x0 + + + SPI_FRAME_WITH_ADDR + SPI Frame with Addr + 0x2 + + + + + CPHA + Clock Phase + 28 + 1 + + CPHASelect + + LEADING_EDGE + The data is sampled on a leading SCK edge and changed on a trailing SCK edge + 0x0 + + + TRAILING_EDGE + The data is sampled on a trailing SCK edge and changed on a leading SCK edge + 0x1 + + + + + CPOL + Clock Polarity + 29 + 1 + + CPOLSelect + + IDLE_LOW + SCK is low when idle + 0x0 + + + IDLE_HIGH + SCK is high when idle + 0x1 + + + + + DORD + Data Order + 30 + 1 + + DORDSelect + + MSB + MSB is transferred first + 0x0 + + + LSB + LSB is transferred first + 0x1 + + + + + + + CTRLB + SPIS Control B + 0x4 + 32 + 0x00000000 + + + CHSIZE + Character Size + 0 + 3 + + CHSIZESelect + + 8_BIT + 8 bits + 0x0 + + + 9_BIT + 9 bits + 0x1 + + + + + PLOADEN + Data Preload Enable + 6 + 1 + + + SSDE + Slave Select Low Detect Enable + 9 + 1 + + + MSSEN + Master Slave Select Enable + 13 + 1 + + + AMODE + Address Mode + 14 + 2 + + AMODESelect + + MASK + SPI Address mask + 0x0 + + + 2_ADDRESSES + Two unique Addressess + 0x1 + + + RANGE + Address Range + 0x2 + + + + + RXEN + Receiver Enable + 17 + 1 + + + + + BAUD + SPIS Baud Rate + 0xC + 8 + 0x00 + + + BAUD + Baud Rate Value + 0 + 8 + + + + + INTENCLR + SPIS Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Disable + 0 + 1 + + + TXC + Transmit Complete Interrupt Disable + 1 + 1 + + + RXC + Receive Complete Interrupt Disable + 2 + 1 + + + SSL + Slave Select Low Interrupt Disable + 3 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + SPIS Interrupt Enable Set + 0x16 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Enable + 0 + 1 + + + TXC + Transmit Complete Interrupt Enable + 1 + 1 + + + RXC + Receive Complete Interrupt Enable + 2 + 1 + + + SSL + Slave Select Low Interrupt Enable + 3 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + SPIS Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt + 0 + 1 + + + TXC + Transmit Complete Interrupt + 1 + 1 + + + RXC + Receive Complete Interrupt + 2 + 1 + + + SSL + Slave Select Low Interrupt Flag + 3 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + SPIS Status + 0x1A + 16 + 0x0000 + + + BUFOVF + Buffer Overflow + 2 + 1 + + + + + SYNCBUSY + SPIS Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + CTRLB + CTRLB Synchronization Busy + 2 + 1 + + + + + ADDR + SPIS Address + 0x24 + 32 + 0x00000000 + + + ADDR + Address Value + 0 + 8 + + + ADDRMASK + Address Mask + 16 + 8 + + + + + DATA + SPIS Data + 0x28 + 32 + 0x00000000 + + + DATA + Data Value + 0 + 9 + + + + + DBGCTRL + SPIS Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + SPIM + SPI Master Mode + I2CM + SercomSpim + 0x0 + + CTRLA + SPIM Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + IBON + Immediate Buffer Overflow Notification + 8 + 1 + + + DOPO + Data Out Pinout + 16 + 2 + + DOPOSelect + + PAD0 + DO on PAD[0], SCK on PAD[1] and SS on PAD[2] + 0x0 + + + PAD1 + DO on PAD[2], SCK on PAD[3] and SS on PAD[1] + 0x1 + + + PAD2 + DO on PAD[3], SCK on PAD[1] and SS on PAD[2] + 0x2 + + + PAD3 + DO on PAD[0], SCK on PAD[3] and SS on PAD[1] + 0x3 + + + + + DIPO + Data In Pinout + 20 + 2 + + DIPOSelect + + PAD0 + SERCOM PAD[0] + 0x0 + + + PAD1 + SERCOM PAD[1] + 0x1 + + + PAD2 + SERCOM PAD[2] + 0x2 + + + PAD3 + SERCOM PAD[3] + 0x3 + + + + + FORM + Frame Format + 24 + 4 + + FORMSelect + + SPI_FRAME + SPI Frame + 0x0 + + + SPI_FRAME_WITH_ADDR + SPI Frame with Addr + 0x2 + + + + + CPHA + Clock Phase + 28 + 1 + + CPHASelect + + LEADING_EDGE + The data is sampled on a leading SCK edge and changed on a trailing SCK edge + 0x0 + + + TRAILING_EDGE + The data is sampled on a trailing SCK edge and changed on a leading SCK edge + 0x1 + + + + + CPOL + Clock Polarity + 29 + 1 + + CPOLSelect + + IDLE_LOW + SCK is low when idle + 0x0 + + + IDLE_HIGH + SCK is high when idle + 0x1 + + + + + DORD + Data Order + 30 + 1 + + DORDSelect + + MSB + MSB is transferred first + 0x0 + + + LSB + LSB is transferred first + 0x1 + + + + + + + CTRLB + SPIM Control B + 0x4 + 32 + 0x00000000 + + + CHSIZE + Character Size + 0 + 3 + + CHSIZESelect + + 8_BIT + 8 bits + 0x0 + + + 9_BIT + 9 bits + 0x1 + + + + + PLOADEN + Data Preload Enable + 6 + 1 + + + SSDE + Slave Select Low Detect Enable + 9 + 1 + + + MSSEN + Master Slave Select Enable + 13 + 1 + + + AMODE + Address Mode + 14 + 2 + + AMODESelect + + MASK + SPI Address mask + 0x0 + + + 2_ADDRESSES + Two unique Addressess + 0x1 + + + RANGE + Address Range + 0x2 + + + + + RXEN + Receiver Enable + 17 + 1 + + + + + BAUD + SPIM Baud Rate + 0xC + 8 + 0x00 + + + BAUD + Baud Rate Value + 0 + 8 + + + + + INTENCLR + SPIM Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Disable + 0 + 1 + + + TXC + Transmit Complete Interrupt Disable + 1 + 1 + + + RXC + Receive Complete Interrupt Disable + 2 + 1 + + + SSL + Slave Select Low Interrupt Disable + 3 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + SPIM Interrupt Enable Set + 0x16 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Enable + 0 + 1 + + + TXC + Transmit Complete Interrupt Enable + 1 + 1 + + + RXC + Receive Complete Interrupt Enable + 2 + 1 + + + SSL + Slave Select Low Interrupt Enable + 3 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + SPIM Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt + 0 + 1 + + + TXC + Transmit Complete Interrupt + 1 + 1 + + + RXC + Receive Complete Interrupt + 2 + 1 + + + SSL + Slave Select Low Interrupt Flag + 3 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + SPIM Status + 0x1A + 16 + 0x0000 + + + BUFOVF + Buffer Overflow + 2 + 1 + + + + + SYNCBUSY + SPIM Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + CTRLB + CTRLB Synchronization Busy + 2 + 1 + + + + + ADDR + SPIM Address + 0x24 + 32 + 0x00000000 + + + ADDR + Address Value + 0 + 8 + + + ADDRMASK + Address Mask + 16 + 8 + + + + + DATA + SPIM Data + 0x28 + 32 + 0x00000000 + + + DATA + Data Value + 0 + 9 + + + + + DBGCTRL + SPIM Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + USART_EXT + USART EXTERNAL CLOCK Mode + I2CM + SercomUsart_ext + 0x0 + + CTRLA + USART_EXT Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + IBON + Immediate Buffer Overflow Notification + 8 + 1 + + + SAMPR + Sample + 13 + 3 + + SAMPRSelect + + 16X_ARITHMETIC + 16x over-sampling using arithmetic baudrate generation + 0x0 + + + 16X_FRACTIONAL + 16x over-sampling using fractional baudrate generation + 0x1 + + + 8X_ARITHMETIC + 8x over-sampling using arithmetic baudrate generation + 0x2 + + + 8X_FRACTIONAL + 8x over-sampling using fractional baudrate generation + 0x3 + + + 3X_ARITHMETIC + 3x over-sampling using arithmetic baudrate generation + 0x4 + + + + + TXPO + Transmit Data Pinout + 16 + 2 + + TXPOSelect + + PAD0 + SERCOM PAD[0] is used for data transmission + 0x0 + + + PAD2 + SERCOM PAD[2] is used for data transmission + 0x1 + + + + + RXPO + Receive Data Pinout + 20 + 2 + + RXPOSelect + + PAD0 + SERCOM PAD[0] is used for data reception + 0x0 + + + PAD1 + SERCOM PAD[1] is used for data reception + 0x1 + + + PAD2 + SERCOM PAD[2] is used for data reception + 0x2 + + + PAD3 + SERCOM PAD[3] is used for data reception + 0x3 + + + + + SAMPA + Sample Adjustment + 22 + 2 + + + FORM + Frame Format + 24 + 4 + + FORMSelect + + USART_FRAME_NO_PARITY + USART frame + 0x0 + + + USART_FRAME_WITH_PARITY + USART frame with parity + 0x1 + + + USART_FRAME_LIN_MASTER_MODE + LIN Master - Break and sync generation + 0x2 + + + USART_FRAME_AUTO_BAUD_NO_PARITY + Auto-baud - break detection and auto-baud + 0x4 + + + USART_FRAME_AUTO_BAUD_WITH_PARITY + Auto-baud - break detection and auto-baud with parity + 0x5 + + + + + CMODE + Communication Mode + 28 + 1 + + CMODESelect + + ASYNC + Asynchronous Communication + 0x0 + + + SYNC + Synchronous Communication + 0x1 + + + + + CPOL + Clock Polarity + 29 + 1 + + CPOLSelect + + IDLE_LOW + TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge + 0x0 + + + IDLE_HIGH + TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge + 0x1 + + + + + DORD + Data Order + 30 + 1 + + DORDSelect + + MSB + MSB is transmitted first + 0x0 + + + LSB + LSB is transmitted first + 0x1 + + + + + + + CTRLB + USART_EXT Control B + 0x4 + 32 + 0x00000000 + + + CHSIZE + Character Size + 0 + 3 + + CHSIZESelect + + 8_BIT + 8 Bits + 0x0 + + + 9_BIT + 9 Bits + 0x1 + + + 5_BIT + 5 Bits + 0x5 + + + 6_BIT + 6 Bits + 0x6 + + + 7_BIT + 7 Bits + 0x7 + + + + + SBMODE + Stop Bit Mode + 6 + 1 + + SBMODESelect + + 1_BIT + One Stop Bit + 0x0 + + + 2_BIT + Two Stop Bits + 0x1 + + + + + COLDEN + Collision Detection Enable + 8 + 1 + + + SFDE + Start of Frame Detection Enable + 9 + 1 + + + ENC + Encoding Format + 10 + 1 + + + PMODE + Parity Mode + 13 + 1 + + PMODESelect + + EVEN + Even Parity + 0x0 + + + ODD + Odd Parity + 0x1 + + + + + TXEN + Transmitter Enable + 16 + 1 + + + RXEN + Receiver Enable + 17 + 1 + + + LINCMD + LIN Command + 24 + 2 + + + + + CTRLC + USART_EXT Control C + 0x8 + 32 + 0x00000000 + + + GTIME + RS485 Guard Time + 0 + 3 + + + BRKLEN + LIN Master Break Length + 8 + 2 + + + HDRDLY + LIN Master Header Delay + 10 + 2 + + + + + BAUD + USART_EXT Baud Rate + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 16 + + + + + BAUD_FRAC_MODE + USART_EXT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 13 + + + FP + Fractional Part + 13 + 3 + + + + + BAUD_FRACFP_MODE + USART_EXT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 13 + + + FP + Fractional Part + 13 + 3 + + + + + BAUD_USARTFP_MODE + USART_EXT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 16 + + + + + RXPL + USART_EXT Receive Pulse Length + 0xE + 8 + 0x00 + + + RXPL + Receive Pulse Length + 0 + 8 + + + + + INTENCLR + USART_EXT Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Disable + 0 + 1 + + + TXC + Transmit Complete Interrupt Disable + 1 + 1 + + + RXC + Receive Complete Interrupt Disable + 2 + 1 + + + RXS + Receive Start Interrupt Disable + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt Disable + 4 + 1 + + + RXBRK + Break Received Interrupt Disable + 5 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + USART_EXT Interrupt Enable Set + 0x16 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Enable + 0 + 1 + + + TXC + Transmit Complete Interrupt Enable + 1 + 1 + + + RXC + Receive Complete Interrupt Enable + 2 + 1 + + + RXS + Receive Start Interrupt Enable + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt Enable + 4 + 1 + + + RXBRK + Break Received Interrupt Enable + 5 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + USART_EXT Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt + 0 + 1 + + + TXC + Transmit Complete Interrupt + 1 + 1 + + + RXC + Receive Complete Interrupt + 2 + 1 + + + RXS + Receive Start Interrupt + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt + 4 + 1 + + + RXBRK + Break Received Interrupt + 5 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + USART_EXT Status + 0x1A + 16 + 0x0000 + + + PERR + Parity Error + 0 + 1 + + + FERR + Frame Error + 1 + 1 + + + BUFOVF + Buffer Overflow + 2 + 1 + + + CTS + Clear To Send + 3 + 1 + + + ISF + Inconsistent Sync Field + 4 + 1 + + + COLL + Collision Detected + 5 + 1 + + + TXE + Transmitter Empty + 6 + 1 + + + + + SYNCBUSY + USART_EXT Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + CTRLB + CTRLB Synchronization Busy + 2 + 1 + + + + + DATA + USART_EXT Data + 0x28 + 16 + 0x0000 + + + DATA + Data Value + 0 + 9 + + + + + DBGCTRL + USART_EXT Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + USART_INT + USART INTERNAL CLOCK Mode + I2CM + SercomUsart_int + 0x0 + + CTRLA + USART_INT Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + MODESelect + + USART_EXT_CLK + USART with external clock + 0x0 + + + USART_INT_CLK + USART with internal clock + 0x1 + + + SPI_SLAVE + SPI in slave operation + 0x2 + + + SPI_MASTER + SPI in master operation + 0x3 + + + I2C_SLAVE + I2C slave operation + 0x4 + + + I2C_MASTER + I2C master operation + 0x5 + + + + + RUNSTDBY + Run during Standby + 7 + 1 + + + IBON + Immediate Buffer Overflow Notification + 8 + 1 + + + SAMPR + Sample + 13 + 3 + + SAMPRSelect + + 16X_ARITHMETIC + 16x over-sampling using arithmetic baudrate generation + 0x0 + + + 16X_FRACTIONAL + 16x over-sampling using fractional baudrate generation + 0x1 + + + 8X_ARITHMETIC + 8x over-sampling using arithmetic baudrate generation + 0x2 + + + 8X_FRACTIONAL + 8x over-sampling using fractional baudrate generation + 0x3 + + + 3X_ARITHMETIC + 3x over-sampling using arithmetic baudrate generation + 0x4 + + + + + TXPO + Transmit Data Pinout + 16 + 2 + + TXPOSelect + + PAD0 + SERCOM PAD[0] is used for data transmission + 0x0 + + + PAD2 + SERCOM PAD[2] is used for data transmission + 0x1 + + + + + RXPO + Receive Data Pinout + 20 + 2 + + RXPOSelect + + PAD0 + SERCOM PAD[0] is used for data reception + 0x0 + + + PAD1 + SERCOM PAD[1] is used for data reception + 0x1 + + + PAD2 + SERCOM PAD[2] is used for data reception + 0x2 + + + PAD3 + SERCOM PAD[3] is used for data reception + 0x3 + + + + + SAMPA + Sample Adjustment + 22 + 2 + + + FORM + Frame Format + 24 + 4 + + FORMSelect + + USART_FRAME_NO_PARITY + USART frame + 0x0 + + + USART_FRAME_WITH_PARITY + USART frame with parity + 0x1 + + + USART_FRAME_LIN_MASTER_MODE + LIN Master - Break and sync generation + 0x2 + + + USART_FRAME_AUTO_BAUD_NO_PARITY + Auto-baud - break detection and auto-baud + 0x4 + + + USART_FRAME_AUTO_BAUD_WITH_PARITY + Auto-baud - break detection and auto-baud with parity + 0x5 + + + + + CMODE + Communication Mode + 28 + 1 + + CMODESelect + + ASYNC + Asynchronous Communication + 0x0 + + + SYNC + Synchronous Communication + 0x1 + + + + + CPOL + Clock Polarity + 29 + 1 + + CPOLSelect + + IDLE_LOW + TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge + 0x0 + + + IDLE_HIGH + TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge + 0x1 + + + + + DORD + Data Order + 30 + 1 + + DORDSelect + + MSB + MSB is transmitted first + 0x0 + + + LSB + LSB is transmitted first + 0x1 + + + + + + + CTRLB + USART_INT Control B + 0x4 + 32 + 0x00000000 + + + CHSIZE + Character Size + 0 + 3 + + CHSIZESelect + + 8_BIT + 8 Bits + 0x0 + + + 9_BIT + 9 Bits + 0x1 + + + 5_BIT + 5 Bits + 0x5 + + + 6_BIT + 6 Bits + 0x6 + + + 7_BIT + 7 Bits + 0x7 + + + + + SBMODE + Stop Bit Mode + 6 + 1 + + SBMODESelect + + 1_BIT + One Stop Bit + 0x0 + + + 2_BIT + Two Stop Bits + 0x1 + + + + + COLDEN + Collision Detection Enable + 8 + 1 + + + SFDE + Start of Frame Detection Enable + 9 + 1 + + + ENC + Encoding Format + 10 + 1 + + + PMODE + Parity Mode + 13 + 1 + + PMODESelect + + EVEN + Even Parity + 0x0 + + + ODD + Odd Parity + 0x1 + + + + + TXEN + Transmitter Enable + 16 + 1 + + + RXEN + Receiver Enable + 17 + 1 + + + LINCMD + LIN Command + 24 + 2 + + + + + CTRLC + USART_INT Control C + 0x8 + 32 + 0x00000000 + + + GTIME + RS485 Guard Time + 0 + 3 + + + BRKLEN + LIN Master Break Length + 8 + 2 + + + HDRDLY + LIN Master Header Delay + 10 + 2 + + + + + BAUD + USART_INT Baud Rate + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 16 + + + + + BAUD_FRAC_MODE + USART_INT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 13 + + + FP + Fractional Part + 13 + 3 + + + + + BAUD_FRACFP_MODE + USART_INT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 13 + + + FP + Fractional Part + 13 + 3 + + + + + BAUD_USARTFP_MODE + USART_INT Baud Rate + BAUD + 0xC + 16 + 0x0000 + + + BAUD + Baud Rate Value + 0 + 16 + + + + + RXPL + USART_INT Receive Pulse Length + 0xE + 8 + 0x00 + + + RXPL + Receive Pulse Length + 0 + 8 + + + + + INTENCLR + USART_INT Interrupt Enable Clear + 0x14 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Disable + 0 + 1 + + + TXC + Transmit Complete Interrupt Disable + 1 + 1 + + + RXC + Receive Complete Interrupt Disable + 2 + 1 + + + RXS + Receive Start Interrupt Disable + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt Disable + 4 + 1 + + + RXBRK + Break Received Interrupt Disable + 5 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + USART_INT Interrupt Enable Set + 0x16 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt Enable + 0 + 1 + + + TXC + Transmit Complete Interrupt Enable + 1 + 1 + + + RXC + Receive Complete Interrupt Enable + 2 + 1 + + + RXS + Receive Start Interrupt Enable + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt Enable + 4 + 1 + + + RXBRK + Break Received Interrupt Enable + 5 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + USART_INT Interrupt Flag Status and Clear + 0x18 + 8 + 0x00 + + + DRE + Data Register Empty Interrupt + 0 + 1 + + + TXC + Transmit Complete Interrupt + 1 + 1 + + + RXC + Receive Complete Interrupt + 2 + 1 + + + RXS + Receive Start Interrupt + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt + 4 + 1 + + + RXBRK + Break Received Interrupt + 5 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + USART_INT Status + 0x1A + 16 + 0x0000 + + + PERR + Parity Error + 0 + 1 + + + FERR + Frame Error + 1 + 1 + + + BUFOVF + Buffer Overflow + 2 + 1 + + + CTS + Clear To Send + 3 + 1 + + + ISF + Inconsistent Sync Field + 4 + 1 + + + COLL + Collision Detected + 5 + 1 + + + TXE + Transmitter Empty + 6 + 1 + + + + + SYNCBUSY + USART_INT Synchronization Busy + 0x1C + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + + + CTRLB + CTRLB Synchronization Busy + 2 + 1 + + + + + DATA + USART_INT Data + 0x28 + 16 + 0x0000 + + + DATA + Data Value + 0 + 9 + + + + + DBGCTRL + USART_INT Debug Control + 0x30 + 8 + 0x00 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + + + SERCOM1 + 0x42000800 + + + SERCOM2 + 0x42000C00 + + SERCOM2 + 11 + + + + SERCOM3 + 0x42001000 + + SERCOM3 + 12 + + + + SERCOM4 + 0x42001400 + + SERCOM4 + 13 + + + + SERCOM5 + 0x42001800 + + SERCOM5 + 14 + + + + SERCOM6 + 0x43000000 + + + SERCOM7 + 0x43000400 + + + SUPC + U21172.2.0 + Supply Controller + SUPC + SUPC_ + 0x40001800 + + 0 + 0x24 + registers + + + + INTENCLR + Interrupt Enable Clear + 0x0 + 32 + 0x00000000 + + + BODVDDRDY + BODVDD Ready + 0 + 1 + + + BODVDDDET + BODVDD Detection + 1 + 1 + + + BVDDSRDY + BODVDD Synchronization Ready + 2 + 1 + + + VREG33RDY + VREG33 Ready + 6 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x4 + 32 + 0x00000000 + + + BODVDDRDY + BODVDD Ready + 0 + 1 + + + BODVDDDET + BODVDD Detection + 1 + 1 + + + BVDDSRDY + BODVDD Synchronization Ready + 2 + 1 + + + VREG33RDY + VREG33 Ready + 6 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x8 + 32 + 0x00000000 + + + BODVDDRDY + BODVDD Ready + 0 + 1 + + + BODVDDDET + BODVDD Detection + 1 + 1 + + + BVDDSRDY + BODVDD Synchronization Ready + 2 + 1 + + + VREG33RDY + VREG33 Ready + 6 + 1 + + + + + STATUS + Power and Clocks Status + 0xC + 32 + read-only + 0x00000000 + + + BODVDDRDY + BODVDD Ready + 0 + 1 + + + BODVDDDET + BODVDD Detection + 1 + 1 + + + BVDDSRDY + BODVDD Synchronization Ready + 2 + 1 + + + VREG33RDY + VREG33 Ready + 6 + 1 + + + + + BODVDD + BODVDD Control + 0x10 + 32 + 0x00000000 + + + ENABLE + Enable + 1 + 1 + + + HYST + Hysteresis Enable + 2 + 1 + + + ACTION + Action when Threshold Crossed + 3 + 2 + + ACTIONSelect + + NONE + No action + 0x0 + + + RESET + The BODVDD generates a reset + 0x1 + + + INT + The BODVDD generates an interrupt + 0x2 + + + + + STDBYCFG + Configuration in Standby mode + 5 + 1 + + + RUNSTDBY + Run during Standby + 6 + 1 + + + ACTCFG + Configuration in Active mode + 8 + 1 + + + PSEL + Prescaler Select + 12 + 4 + + PSELSelect + + DIV2 + Divide clock by 2 + 0x0 + + + DIV4 + Divide clock by 4 + 0x1 + + + DIV8 + Divide clock by 8 + 0x2 + + + DIV16 + Divide clock by 16 + 0x3 + + + DIV32 + Divide clock by 32 + 0x4 + + + DIV64 + Divide clock by 64 + 0x5 + + + DIV128 + Divide clock by 128 + 0x6 + + + DIV256 + Divide clock by 256 + 0x7 + + + DIV512 + Divide clock by 512 + 0x8 + + + DIV1024 + Divide clock by 1024 + 0x9 + + + DIV2048 + Divide clock by 2048 + 0xA + + + DIV4096 + Divide clock by 4096 + 0xB + + + DIV8192 + Divide clock by 8192 + 0xC + + + DIV16384 + Divide clock by 16384 + 0xD + + + DIV32768 + Divide clock by 32768 + 0xE + + + DIV65536 + Divide clock by 65536 + 0xF + + + + + LEVEL + Threshold Level for VDD + 16 + 6 + + + + + VREG + VREG Control + 0x18 + 32 + 0x00000000 + + + ENABLE + Enable + 1 + 1 + + + RUNSTDBY + Run during Standby + 6 + 1 + + + + + VREF + VREF Control + 0x1C + 32 + 0x00000000 + + + TSEN + Temperature Sensor Output Enable + 1 + 1 + + + VREFOE + Voltage Reference Output Enable + 2 + 1 + + + RUNSTDBY + Run during Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + SEL + Voltage Reference Selection + 16 + 4 + + SELSelect + + 1V024 + 1.024V voltage reference typical value + 0x0 + + + 2V048 + 2.048V voltage reference typical value + 0x2 + + + 4V096 + 4.096V voltage reference typical value + 0x3 + + + + + + + VREG33 + VREG33 Control + 0x20 + 32 + 0x00000010 + + + ENABLE + VREG33 Enable + 1 + 1 + + + ENRDY + VREG33 Ready Enable + 2 + 1 + + + BYPASS + VREG33 Bypass + 3 + 1 + + + ISOEN + Isolation Enable + 4 + 1 + + + + + + + TC0 + U22493.0.0 + Basic Timer Counter + TC + TC_ + 0x42003000 + + 0 + 0x38 + registers + + + + COUNT8 + 8-bit Counter Mode + TcCount8 + 0x0 + + CTRLA + Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Timer Counter Mode + 2 + 2 + + MODESelect + + COUNT16 + Counter in 16-bit mode + 0 + + + COUNT8 + Counter in 8-bit mode + 1 + + + COUNT32 + Counter in 32-bit mode + 2 + + + + + PRESCSYNC + Prescaler and Counter Synchronization + 4 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset the counter on next generic clock + 0 + + + PRESC + Reload or reset the counter on next prescaler clock + 1 + + + RESYNC + Reload or reset the counter on next generic clock and reset the prescaler counter + 2 + + + + + RUNSTDBY + Run during Standby + 6 + 1 + + + ONDEMAND + Clock On Demand + 7 + 1 + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + Prescaler: GCLK_TC + 0 + + + DIV2 + Prescaler: GCLK_TC/2 + 1 + + + DIV4 + Prescaler: GCLK_TC/4 + 2 + + + DIV8 + Prescaler: GCLK_TC/8 + 3 + + + DIV16 + Prescaler: GCLK_TC/16 + 4 + + + DIV64 + Prescaler: GCLK_TC/64 + 5 + + + DIV256 + Prescaler: GCLK_TC/256 + 6 + + + DIV1024 + Prescaler: GCLK_TC/1024 + 7 + + + + + ALOCK + Auto Lock + 11 + 1 + + + CAPTEN0 + Capture Channel 0 Enable + 16 + 1 + + + CAPTEN1 + Capture Channel 1 Enable + 17 + 1 + + + COPEN0 + Capture On Pin 0 Enable + 20 + 1 + + + COPEN1 + Capture On Pin 1 Enable + 21 + 1 + + + CAPTMODE0 + Capture Mode Channel 0 + 24 + 2 + + CAPTMODE0Select + + DEFAULT + Default capture + 0 + + + CAPTMIN + Minimum capture + 1 + + + CAPTMAX + Maximum capture + 2 + + + + + CAPTMODE1 + Capture mode Channel 1 + 27 + 2 + + CAPTMODE1Select + + DEFAULT + Default capture + 0 + + + CAPTMIN + Minimum capture + 1 + + + CAPTMAX + Maximum capture + 2 + + + + + + + CTRLBCLR + Control B Clear + 0x4 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot on Counter + 2 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + UPDATE + Force update of double-buffered register + 3 + + + READSYNC + Force a read synchronization of COUNT + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + CTRLBSET + Control B Set + 0x5 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot on Counter + 2 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + UPDATE + Force update of double-buffered register + 3 + + + READSYNC + Force a read synchronization of COUNT + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + EVCTRL + Event Control + 0x6 + 16 + 0x0000 + + + EVACT + Event Action + 0 + 3 + + EVACTSelect + + OFF + Event action disabled + 0 + + + RETRIGGER + Start, restart or retrigger TC on event + 1 + + + COUNT + Count on event + 2 + + + START + Start TC on event + 3 + + + STAMP + Time stamp capture + 4 + + + PPW + Period catured in CC0, pulse width in CC1 + 5 + + + PWP + Period catured in CC1, pulse width in CC0 + 6 + + + PW + Pulse width capture + 7 + + + + + TCINV + TC Event Input Polarity + 4 + 1 + + + TCEI + TC Event Enable + 5 + 1 + + + OVFEO + Event Output Enable + 8 + 1 + + + MCEO0 + MC Event Output Enable 0 + 12 + 1 + + + MCEO1 + MC Event Output Enable 1 + 13 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x8 + 8 + 0x00 + + + OVF + OVF Interrupt Disable + 0 + 1 + + + ERR + ERR Interrupt Disable + 1 + 1 + + + MC0 + MC Interrupt Disable 0 + 4 + 1 + + + MC1 + MC Interrupt Disable 1 + 5 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x9 + 8 + 0x00 + + + OVF + OVF Interrupt Enable + 0 + 1 + + + ERR + ERR Interrupt Enable + 1 + 1 + + + MC0 + MC Interrupt Enable 0 + 4 + 1 + + + MC1 + MC Interrupt Enable 1 + 5 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0xA + 8 + 0x00 + + + OVF + OVF Interrupt Flag + 0 + 1 + + + ERR + ERR Interrupt Flag + 1 + 1 + + + MC0 + MC Interrupt Flag 0 + 4 + 1 + + + MC1 + MC Interrupt Flag 1 + 5 + 1 + + + + + STATUS + Status + 0xB + 8 + 0x01 + + + STOP + Stop Status Flag + 0 + 1 + + + SLAVE + Slave Status Flag + 1 + 1 + + + PERBUFV + Synchronization Busy Status + 3 + 1 + + + CCBUFV0 + Compare channel buffer 0 valid + 4 + 1 + + + CCBUFV1 + Compare channel buffer 1 valid + 5 + 1 + + + + + WAVE + Waveform Generation Control + 0xC + 8 + 0x00 + + + WAVEGEN + Waveform Generation Mode + 0 + 2 + + WAVEGENSelect + + NFRQ + Normal frequency + 0 + + + MFRQ + Match frequency + 1 + + + NPWM + Normal PWM + 2 + + + MPWM + Match PWM + 3 + + + + + + + DRVCTRL + Control C + 0xD + 8 + 0x00 + + + INVEN0 + Output Waveform Invert Enable 0 + 0 + 1 + + + INVEN1 + Output Waveform Invert Enable 1 + 1 + 1 + + + + + DBGCTRL + Debug Control + 0xF + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + SYNCBUSY + Synchronization Status + 0x10 + 32 + read-only + 0x00000000 + + + SWRST + swrst + 0 + 1 + + + ENABLE + enable + 1 + 1 + + + CTRLB + CTRLB + 2 + 1 + + + STATUS + STATUS + 3 + 1 + + + COUNT + Counter + 4 + 1 + + + PER + Period + 5 + 1 + + + CC0 + Compare Channel 0 + 6 + 1 + + + CC1 + Compare Channel 1 + 7 + 1 + + + + + COUNT + COUNT8 Count + 0x14 + 8 + 0x00 + + + COUNT + Counter Value + 0 + 8 + + + + + PER + COUNT8 Period + 0x1B + 8 + 0xFF + + + PER + Period Value + 0 + 8 + + + + + 2 + 1 + CC[%s] + COUNT8 Compare and Capture + 0x1C + 8 + 0x00 + + + CC + Counter/Compare Value + 0 + 8 + + + + + PERBUF + COUNT8 Period Buffer + 0x2F + 8 + 0xFF + + + PERBUF + Period Buffer Value + 0 + 8 + + + + + 2 + 1 + CCBUF[%s] + COUNT8 Compare and Capture Buffer + 0x30 + 8 + 0x00 + + + CCBUF + Counter/Compare Buffer Value + 0 + 8 + + + + + + COUNT16 + 16-bit Counter Mode + COUNT8 + TcCount16 + 0x0 + + CTRLA + Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Timer Counter Mode + 2 + 2 + + MODESelect + + COUNT16 + Counter in 16-bit mode + 0 + + + COUNT8 + Counter in 8-bit mode + 1 + + + COUNT32 + Counter in 32-bit mode + 2 + + + + + PRESCSYNC + Prescaler and Counter Synchronization + 4 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset the counter on next generic clock + 0 + + + PRESC + Reload or reset the counter on next prescaler clock + 1 + + + RESYNC + Reload or reset the counter on next generic clock and reset the prescaler counter + 2 + + + + + RUNSTDBY + Run during Standby + 6 + 1 + + + ONDEMAND + Clock On Demand + 7 + 1 + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + Prescaler: GCLK_TC + 0 + + + DIV2 + Prescaler: GCLK_TC/2 + 1 + + + DIV4 + Prescaler: GCLK_TC/4 + 2 + + + DIV8 + Prescaler: GCLK_TC/8 + 3 + + + DIV16 + Prescaler: GCLK_TC/16 + 4 + + + DIV64 + Prescaler: GCLK_TC/64 + 5 + + + DIV256 + Prescaler: GCLK_TC/256 + 6 + + + DIV1024 + Prescaler: GCLK_TC/1024 + 7 + + + + + ALOCK + Auto Lock + 11 + 1 + + + CAPTEN0 + Capture Channel 0 Enable + 16 + 1 + + + CAPTEN1 + Capture Channel 1 Enable + 17 + 1 + + + COPEN0 + Capture On Pin 0 Enable + 20 + 1 + + + COPEN1 + Capture On Pin 1 Enable + 21 + 1 + + + CAPTMODE0 + Capture Mode Channel 0 + 24 + 2 + + CAPTMODE0Select + + DEFAULT + Default capture + 0 + + + CAPTMIN + Minimum capture + 1 + + + CAPTMAX + Maximum capture + 2 + + + + + CAPTMODE1 + Capture mode Channel 1 + 27 + 2 + + CAPTMODE1Select + + DEFAULT + Default capture + 0 + + + CAPTMIN + Minimum capture + 1 + + + CAPTMAX + Maximum capture + 2 + + + + + + + CTRLBCLR + Control B Clear + 0x4 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot on Counter + 2 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + UPDATE + Force update of double-buffered register + 3 + + + READSYNC + Force a read synchronization of COUNT + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + CTRLBSET + Control B Set + 0x5 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot on Counter + 2 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + UPDATE + Force update of double-buffered register + 3 + + + READSYNC + Force a read synchronization of COUNT + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + EVCTRL + Event Control + 0x6 + 16 + 0x0000 + + + EVACT + Event Action + 0 + 3 + + EVACTSelect + + OFF + Event action disabled + 0 + + + RETRIGGER + Start, restart or retrigger TC on event + 1 + + + COUNT + Count on event + 2 + + + START + Start TC on event + 3 + + + STAMP + Time stamp capture + 4 + + + PPW + Period catured in CC0, pulse width in CC1 + 5 + + + PWP + Period catured in CC1, pulse width in CC0 + 6 + + + PW + Pulse width capture + 7 + + + + + TCINV + TC Event Input Polarity + 4 + 1 + + + TCEI + TC Event Enable + 5 + 1 + + + OVFEO + Event Output Enable + 8 + 1 + + + MCEO0 + MC Event Output Enable 0 + 12 + 1 + + + MCEO1 + MC Event Output Enable 1 + 13 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x8 + 8 + 0x00 + + + OVF + OVF Interrupt Disable + 0 + 1 + + + ERR + ERR Interrupt Disable + 1 + 1 + + + MC0 + MC Interrupt Disable 0 + 4 + 1 + + + MC1 + MC Interrupt Disable 1 + 5 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x9 + 8 + 0x00 + + + OVF + OVF Interrupt Enable + 0 + 1 + + + ERR + ERR Interrupt Enable + 1 + 1 + + + MC0 + MC Interrupt Enable 0 + 4 + 1 + + + MC1 + MC Interrupt Enable 1 + 5 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0xA + 8 + 0x00 + + + OVF + OVF Interrupt Flag + 0 + 1 + + + ERR + ERR Interrupt Flag + 1 + 1 + + + MC0 + MC Interrupt Flag 0 + 4 + 1 + + + MC1 + MC Interrupt Flag 1 + 5 + 1 + + + + + STATUS + Status + 0xB + 8 + 0x01 + + + STOP + Stop Status Flag + 0 + 1 + + + SLAVE + Slave Status Flag + 1 + 1 + + + PERBUFV + Synchronization Busy Status + 3 + 1 + + + CCBUFV0 + Compare channel buffer 0 valid + 4 + 1 + + + CCBUFV1 + Compare channel buffer 1 valid + 5 + 1 + + + + + WAVE + Waveform Generation Control + 0xC + 8 + 0x00 + + + WAVEGEN + Waveform Generation Mode + 0 + 2 + + WAVEGENSelect + + NFRQ + Normal frequency + 0 + + + MFRQ + Match frequency + 1 + + + NPWM + Normal PWM + 2 + + + MPWM + Match PWM + 3 + + + + + + + DRVCTRL + Control C + 0xD + 8 + 0x00 + + + INVEN0 + Output Waveform Invert Enable 0 + 0 + 1 + + + INVEN1 + Output Waveform Invert Enable 1 + 1 + 1 + + + + + DBGCTRL + Debug Control + 0xF + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + SYNCBUSY + Synchronization Status + 0x10 + 32 + read-only + 0x00000000 + + + SWRST + swrst + 0 + 1 + + + ENABLE + enable + 1 + 1 + + + CTRLB + CTRLB + 2 + 1 + + + STATUS + STATUS + 3 + 1 + + + COUNT + Counter + 4 + 1 + + + PER + Period + 5 + 1 + + + CC0 + Compare Channel 0 + 6 + 1 + + + CC1 + Compare Channel 1 + 7 + 1 + + + + + COUNT + COUNT16 Count + 0x14 + 16 + 0x0000 + + + COUNT + Counter Value + 0 + 16 + + + + + 2 + 2 + CC[%s] + COUNT16 Compare and Capture + 0x1C + 16 + 0x0000 + + + CC + Counter/Compare Value + 0 + 16 + + + + + 2 + 2 + CCBUF[%s] + COUNT16 Compare and Capture Buffer + 0x30 + 16 + 0x0000 + + + CCBUF + Counter/Compare Buffer Value + 0 + 16 + + + + + + COUNT32 + 32-bit Counter Mode + COUNT8 + TcCount32 + 0x0 + + CTRLA + Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Timer Counter Mode + 2 + 2 + + MODESelect + + COUNT16 + Counter in 16-bit mode + 0 + + + COUNT8 + Counter in 8-bit mode + 1 + + + COUNT32 + Counter in 32-bit mode + 2 + + + + + PRESCSYNC + Prescaler and Counter Synchronization + 4 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset the counter on next generic clock + 0 + + + PRESC + Reload or reset the counter on next prescaler clock + 1 + + + RESYNC + Reload or reset the counter on next generic clock and reset the prescaler counter + 2 + + + + + RUNSTDBY + Run during Standby + 6 + 1 + + + ONDEMAND + Clock On Demand + 7 + 1 + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + Prescaler: GCLK_TC + 0 + + + DIV2 + Prescaler: GCLK_TC/2 + 1 + + + DIV4 + Prescaler: GCLK_TC/4 + 2 + + + DIV8 + Prescaler: GCLK_TC/8 + 3 + + + DIV16 + Prescaler: GCLK_TC/16 + 4 + + + DIV64 + Prescaler: GCLK_TC/64 + 5 + + + DIV256 + Prescaler: GCLK_TC/256 + 6 + + + DIV1024 + Prescaler: GCLK_TC/1024 + 7 + + + + + ALOCK + Auto Lock + 11 + 1 + + + CAPTEN0 + Capture Channel 0 Enable + 16 + 1 + + + CAPTEN1 + Capture Channel 1 Enable + 17 + 1 + + + COPEN0 + Capture On Pin 0 Enable + 20 + 1 + + + COPEN1 + Capture On Pin 1 Enable + 21 + 1 + + + CAPTMODE0 + Capture Mode Channel 0 + 24 + 2 + + CAPTMODE0Select + + DEFAULT + Default capture + 0 + + + CAPTMIN + Minimum capture + 1 + + + CAPTMAX + Maximum capture + 2 + + + + + CAPTMODE1 + Capture mode Channel 1 + 27 + 2 + + CAPTMODE1Select + + DEFAULT + Default capture + 0 + + + CAPTMIN + Minimum capture + 1 + + + CAPTMAX + Maximum capture + 2 + + + + + + + CTRLBCLR + Control B Clear + 0x4 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot on Counter + 2 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + UPDATE + Force update of double-buffered register + 3 + + + READSYNC + Force a read synchronization of COUNT + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + CTRLBSET + Control B Set + 0x5 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot on Counter + 2 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Force a start, restart or retrigger + 1 + + + STOP + Force a stop + 2 + + + UPDATE + Force update of double-buffered register + 3 + + + READSYNC + Force a read synchronization of COUNT + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + EVCTRL + Event Control + 0x6 + 16 + 0x0000 + + + EVACT + Event Action + 0 + 3 + + EVACTSelect + + OFF + Event action disabled + 0 + + + RETRIGGER + Start, restart or retrigger TC on event + 1 + + + COUNT + Count on event + 2 + + + START + Start TC on event + 3 + + + STAMP + Time stamp capture + 4 + + + PPW + Period catured in CC0, pulse width in CC1 + 5 + + + PWP + Period catured in CC1, pulse width in CC0 + 6 + + + PW + Pulse width capture + 7 + + + + + TCINV + TC Event Input Polarity + 4 + 1 + + + TCEI + TC Event Enable + 5 + 1 + + + OVFEO + Event Output Enable + 8 + 1 + + + MCEO0 + MC Event Output Enable 0 + 12 + 1 + + + MCEO1 + MC Event Output Enable 1 + 13 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x8 + 8 + 0x00 + + + OVF + OVF Interrupt Disable + 0 + 1 + + + ERR + ERR Interrupt Disable + 1 + 1 + + + MC0 + MC Interrupt Disable 0 + 4 + 1 + + + MC1 + MC Interrupt Disable 1 + 5 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x9 + 8 + 0x00 + + + OVF + OVF Interrupt Enable + 0 + 1 + + + ERR + ERR Interrupt Enable + 1 + 1 + + + MC0 + MC Interrupt Enable 0 + 4 + 1 + + + MC1 + MC Interrupt Enable 1 + 5 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0xA + 8 + 0x00 + + + OVF + OVF Interrupt Flag + 0 + 1 + + + ERR + ERR Interrupt Flag + 1 + 1 + + + MC0 + MC Interrupt Flag 0 + 4 + 1 + + + MC1 + MC Interrupt Flag 1 + 5 + 1 + + + + + STATUS + Status + 0xB + 8 + 0x01 + + + STOP + Stop Status Flag + 0 + 1 + + + SLAVE + Slave Status Flag + 1 + 1 + + + PERBUFV + Synchronization Busy Status + 3 + 1 + + + CCBUFV0 + Compare channel buffer 0 valid + 4 + 1 + + + CCBUFV1 + Compare channel buffer 1 valid + 5 + 1 + + + + + WAVE + Waveform Generation Control + 0xC + 8 + 0x00 + + + WAVEGEN + Waveform Generation Mode + 0 + 2 + + WAVEGENSelect + + NFRQ + Normal frequency + 0 + + + MFRQ + Match frequency + 1 + + + NPWM + Normal PWM + 2 + + + MPWM + Match PWM + 3 + + + + + + + DRVCTRL + Control C + 0xD + 8 + 0x00 + + + INVEN0 + Output Waveform Invert Enable 0 + 0 + 1 + + + INVEN1 + Output Waveform Invert Enable 1 + 1 + 1 + + + + + DBGCTRL + Debug Control + 0xF + 8 + 0x00 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + SYNCBUSY + Synchronization Status + 0x10 + 32 + read-only + 0x00000000 + + + SWRST + swrst + 0 + 1 + + + ENABLE + enable + 1 + 1 + + + CTRLB + CTRLB + 2 + 1 + + + STATUS + STATUS + 3 + 1 + + + COUNT + Counter + 4 + 1 + + + PER + Period + 5 + 1 + + + CC0 + Compare Channel 0 + 6 + 1 + + + CC1 + Compare Channel 1 + 7 + 1 + + + + + COUNT + COUNT32 Count + 0x14 + 32 + 0x00000000 + + + COUNT + Counter Value + 0 + 32 + + + + + 2 + 4 + CC[%s] + COUNT32 Compare and Capture + 0x1C + 32 + 0x00000000 + + + CC + Counter/Compare Value + 0 + 32 + + + + + 2 + 4 + CCBUF[%s] + COUNT32 Compare and Capture Buffer + 0x30 + 32 + 0x00000000 + + + CCBUF + Counter/Compare Buffer Value + 0 + 32 + + + + + + + + TC1 + 0x42003400 + + + TC2 + 0x42003800 + + + TC3 + 0x42003C00 + + TC3 + 23 + + + + TC4 + 0x42004000 + + TC4 + 24 + + + + TC5 + 0x43000800 + + + TC6 + 0x43000C00 + + + TC7 + 0x43001000 + + + TCC0 + U22133.1.0 + Timer Counter Control + TCC + TCC_ + 0x42002400 + + 0 + 0x80 + registers + + + TCC0 + 17 + + + + CTRLA + Control A + 0x0 + 32 + 0x00000000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + RESOLUTION + Enhanced Resolution + 5 + 2 + + RESOLUTIONSelect + + NONE + Dithering is disabled + 0 + + + DITH4 + Dithering is done every 16 PWM frames + 1 + + + DITH5 + Dithering is done every 32 PWM frames + 2 + + + DITH6 + Dithering is done every 64 PWM frames + 3 + + + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + No division + 0 + + + DIV2 + Divide by 2 + 1 + + + DIV4 + Divide by 4 + 2 + + + DIV8 + Divide by 8 + 3 + + + DIV16 + Divide by 16 + 4 + + + DIV64 + Divide by 64 + 5 + + + DIV256 + Divide by 256 + 6 + + + DIV1024 + Divide by 1024 + 7 + + + + + RUNSTDBY + Run in Standby + 11 + 1 + + + PRESCSYNC + Prescaler and Counter Synchronization Selection + 12 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset counter on next GCLK + 0 + + + PRESC + Reload or reset counter on next prescaler clock + 1 + + + RESYNC + Reload or reset counter on next GCLK and reset prescaler counter + 2 + + + + + ALOCK + Auto Lock + 14 + 1 + + + MSYNC + Master Synchronization (only for TCC Slave Instance) + 15 + 1 + + + DMAOS + DMA One-shot Trigger Mode + 23 + 1 + + + CPTEN0 + Capture Channel 0 Enable + 24 + 1 + + + CPTEN1 + Capture Channel 1 Enable + 25 + 1 + + + CPTEN2 + Capture Channel 2 Enable + 26 + 1 + + + CPTEN3 + Capture Channel 3 Enable + 27 + 1 + + + + + CTRLBCLR + Control B Clear + 0x4 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + IDXCMD + Ramp Index Command + 3 + 2 + + IDXCMDSelect + + DISABLE + Command disabled: Index toggles between cycles A and B + 0 + + + SET + Set index: cycle B will be forced in the next cycle + 1 + + + CLEAR + Clear index: cycle A will be forced in the next cycle + 2 + + + HOLD + Hold index: the next cycle will be the same as the current cycle + 3 + + + + + CMD + TCC Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Clear start, restart or retrigger + 1 + + + STOP + Force stop + 2 + + + UPDATE + Force update or double buffered registers + 3 + + + READSYNC + Force COUNT read synchronization + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + CTRLBSET + Control B Set + 0x5 + 8 + 0x00 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + IDXCMD + Ramp Index Command + 3 + 2 + + IDXCMDSelect + + DISABLE + Command disabled: Index toggles between cycles A and B + 0 + + + SET + Set index: cycle B will be forced in the next cycle + 1 + + + CLEAR + Clear index: cycle A will be forced in the next cycle + 2 + + + HOLD + Hold index: the next cycle will be the same as the current cycle + 3 + + + + + CMD + TCC Command + 5 + 3 + + CMDSelect + + NONE + No action + 0 + + + RETRIGGER + Clear start, restart or retrigger + 1 + + + STOP + Force stop + 2 + + + UPDATE + Force update or double buffered registers + 3 + + + READSYNC + Force COUNT read synchronization + 4 + + + DMAOS + One-shot DMA trigger + 5 + + + + + + + SYNCBUSY + Synchronization Busy + 0x8 + 32 + read-only + 0x00000000 + + + SWRST + Swrst Busy + 0 + 1 + + + ENABLE + Enable Busy + 1 + 1 + + + CTRLB + Ctrlb Busy + 2 + 1 + + + STATUS + Status Busy + 3 + 1 + + + COUNT + Count Busy + 4 + 1 + + + PATT + Pattern Busy + 5 + 1 + + + WAVE + Wave Busy + 6 + 1 + + + PER + Period Busy + 7 + 1 + + + CC0 + Compare Channel 0 Busy + 8 + 1 + + + CC1 + Compare Channel 1 Busy + 9 + 1 + + + CC2 + Compare Channel 2 Busy + 10 + 1 + + + CC3 + Compare Channel 3 Busy + 11 + 1 + + + + + FCTRLA + Recoverable Fault A Configuration + 0xC + 32 + 0x00000000 + + + SRC + Fault A Source + 0 + 2 + + SRCSelect + + DISABLE + Fault input disabled + 0 + + + ENABLE + MCEx (x=0,1) event input + 1 + + + INVERT + Inverted MCEx (x=0,1) event input + 2 + + + ALTFAULT + Alternate fault (A or B) state at the end of the previous period + 3 + + + + + KEEP + Fault A Keeper + 3 + 1 + + + QUAL + Fault A Qualification + 4 + 1 + + + BLANK + Fault A Blanking Mode + 5 + 2 + + BLANKSelect + + START + Blanking applied from start of the ramp + 0 + + + RISE + Blanking applied from rising edge of the output waveform + 1 + + + FALL + Blanking applied from falling edge of the output waveform + 2 + + + BOTH + Blanking applied from each toggle of the output waveform + 3 + + + + + RESTART + Fault A Restart + 7 + 1 + + + HALT + Fault A Halt Mode + 8 + 2 + + HALTSelect + + DISABLE + Halt action disabled + 0 + + + HW + Hardware halt action + 1 + + + SW + Software halt action + 2 + + + NR + Non-recoverable fault + 3 + + + + + CHSEL + Fault A Capture Channel + 10 + 2 + + CHSELSelect + + CC0 + Capture value stored in channel 0 + 0 + + + CC1 + Capture value stored in channel 1 + 1 + + + CC2 + Capture value stored in channel 2 + 2 + + + CC3 + Capture value stored in channel 3 + 3 + + + + + CAPTURE + Fault A Capture Action + 12 + 3 + + CAPTURESelect + + DISABLE + No capture + 0 + + + CAPT + Capture on fault + 1 + + + CAPTMIN + Minimum capture + 2 + + + CAPTMAX + Maximum capture + 3 + + + LOCMIN + Minimum local detection + 4 + + + LOCMAX + Maximum local detection + 5 + + + DERIV0 + Minimum and maximum local detection + 6 + + + CAPTMARK + Capture with ramp index as MSB value + 7 + + + + + BLANKPRESC + Fault A Blanking Prescaler + 15 + 1 + + + BLANKVAL + Fault A Blanking Time + 16 + 8 + + + FILTERVAL + Fault A Filter Value + 24 + 4 + + + + + FCTRLB + Recoverable Fault B Configuration + 0x10 + 32 + 0x00000000 + + + SRC + Fault B Source + 0 + 2 + + SRCSelect + + DISABLE + Fault input disabled + 0 + + + ENABLE + MCEx (x=0,1) event input + 1 + + + INVERT + Inverted MCEx (x=0,1) event input + 2 + + + ALTFAULT + Alternate fault (A or B) state at the end of the previous period + 3 + + + + + KEEP + Fault B Keeper + 3 + 1 + + + QUAL + Fault B Qualification + 4 + 1 + + + BLANK + Fault B Blanking Mode + 5 + 2 + + BLANKSelect + + START + Blanking applied from start of the ramp + 0 + + + RISE + Blanking applied from rising edge of the output waveform + 1 + + + FALL + Blanking applied from falling edge of the output waveform + 2 + + + BOTH + Blanking applied from each toggle of the output waveform + 3 + + + + + RESTART + Fault B Restart + 7 + 1 + + + HALT + Fault B Halt Mode + 8 + 2 + + HALTSelect + + DISABLE + Halt action disabled + 0 + + + HW + Hardware halt action + 1 + + + SW + Software halt action + 2 + + + NR + Non-recoverable fault + 3 + + + + + CHSEL + Fault B Capture Channel + 10 + 2 + + CHSELSelect + + CC0 + Capture value stored in channel 0 + 0 + + + CC1 + Capture value stored in channel 1 + 1 + + + CC2 + Capture value stored in channel 2 + 2 + + + CC3 + Capture value stored in channel 3 + 3 + + + + + CAPTURE + Fault B Capture Action + 12 + 3 + + CAPTURESelect + + DISABLE + No capture + 0 + + + CAPT + Capture on fault + 1 + + + CAPTMIN + Minimum capture + 2 + + + CAPTMAX + Maximum capture + 3 + + + LOCMIN + Minimum local detection + 4 + + + LOCMAX + Maximum local detection + 5 + + + DERIV0 + Minimum and maximum local detection + 6 + + + CAPTMARK + Capture with ramp index as MSB value + 7 + + + + + BLANKPRESC + Fault B Blanking Prescaler + 15 + 1 + + + BLANKVAL + Fault B Blanking Time + 16 + 8 + + + FILTERVAL + Fault B Filter Value + 24 + 4 + + + + + WEXCTRL + Waveform Extension Configuration + 0x14 + 32 + 0x00000000 + + + OTMX + Output Matrix + 0 + 2 + + + DTIEN0 + Dead-time Insertion Generator 0 Enable + 8 + 1 + + + DTIEN1 + Dead-time Insertion Generator 1 Enable + 9 + 1 + + + DTIEN2 + Dead-time Insertion Generator 2 Enable + 10 + 1 + + + DTIEN3 + Dead-time Insertion Generator 3 Enable + 11 + 1 + + + DTLS + Dead-time Low Side Outputs Value + 16 + 8 + + + DTHS + Dead-time High Side Outputs Value + 24 + 8 + + + + + DRVCTRL + Driver Control + 0x18 + 32 + 0x00000000 + + + NRE0 + Non-Recoverable State 0 Output Enable + 0 + 1 + + + NRE1 + Non-Recoverable State 1 Output Enable + 1 + 1 + + + NRE2 + Non-Recoverable State 2 Output Enable + 2 + 1 + + + NRE3 + Non-Recoverable State 3 Output Enable + 3 + 1 + + + NRE4 + Non-Recoverable State 4 Output Enable + 4 + 1 + + + NRE5 + Non-Recoverable State 5 Output Enable + 5 + 1 + + + NRE6 + Non-Recoverable State 6 Output Enable + 6 + 1 + + + NRE7 + Non-Recoverable State 7 Output Enable + 7 + 1 + + + NRV0 + Non-Recoverable State 0 Output Value + 8 + 1 + + + NRV1 + Non-Recoverable State 1 Output Value + 9 + 1 + + + NRV2 + Non-Recoverable State 2 Output Value + 10 + 1 + + + NRV3 + Non-Recoverable State 3 Output Value + 11 + 1 + + + NRV4 + Non-Recoverable State 4 Output Value + 12 + 1 + + + NRV5 + Non-Recoverable State 5 Output Value + 13 + 1 + + + NRV6 + Non-Recoverable State 6 Output Value + 14 + 1 + + + NRV7 + Non-Recoverable State 7 Output Value + 15 + 1 + + + INVEN0 + Output Waveform 0 Inversion + 16 + 1 + + + INVEN1 + Output Waveform 1 Inversion + 17 + 1 + + + INVEN2 + Output Waveform 2 Inversion + 18 + 1 + + + INVEN3 + Output Waveform 3 Inversion + 19 + 1 + + + INVEN4 + Output Waveform 4 Inversion + 20 + 1 + + + INVEN5 + Output Waveform 5 Inversion + 21 + 1 + + + INVEN6 + Output Waveform 6 Inversion + 22 + 1 + + + INVEN7 + Output Waveform 7 Inversion + 23 + 1 + + + FILTERVAL0 + Non-Recoverable Fault Input 0 Filter Value + 24 + 4 + + + FILTERVAL1 + Non-Recoverable Fault Input 1 Filter Value + 28 + 4 + + + + + DBGCTRL + Debug Control + 0x1E + 8 + 0x00 + + + DBGRUN + Debug Running Mode + 0 + 1 + + + FDDBD + Fault Detection on Debug Break Detection + 2 + 1 + + + + + EVCTRL + Event Control + 0x20 + 32 + 0x00000000 + + + EVACT0 + Timer/counter Input Event0 Action + 0 + 3 + + EVACT0Select + + OFF + Event action disabled + 0 + + + RETRIGGER + Start, restart or re-trigger counter on event + 1 + + + COUNTEV + Count on event + 2 + + + START + Start counter on event + 3 + + + INC + Increment counter on event + 4 + + + COUNT + Count on active state of asynchronous event + 5 + + + STAMP + Stamp capture + 6 + + + FAULT + Non-recoverable fault + 7 + + + + + EVACT1 + Timer/counter Input Event1 Action + 3 + 3 + + EVACT1Select + + OFF + Event action disabled + 0 + + + RETRIGGER + Re-trigger counter on event + 1 + + + DIR + Direction control + 2 + + + STOP + Stop counter on event + 3 + + + DEC + Decrement counter on event + 4 + + + PPW + Period capture value in CC0 register, pulse width capture value in CC1 register + 5 + + + PWP + Period capture value in CC1 register, pulse width capture value in CC0 register + 6 + + + FAULT + Non-recoverable fault + 7 + + + + + CNTSEL + Timer/counter Output Event Mode + 6 + 2 + + CNTSELSelect + + START + An interrupt/event is generated when a new counter cycle starts + 0 + + + END + An interrupt/event is generated when a counter cycle ends + 1 + + + BETWEEN + An interrupt/event is generated when a counter cycle ends, except for the first and last cycles + 2 + + + BOUNDARY + An interrupt/event is generated when a new counter cycle starts or a counter cycle ends + 3 + + + + + OVFEO + Overflow/Underflow Output Event Enable + 8 + 1 + + + TRGEO + Retrigger Output Event Enable + 9 + 1 + + + CNTEO + Timer/counter Output Event Enable + 10 + 1 + + + TCINV0 + Inverted Event 0 Input Enable + 12 + 1 + + + TCINV1 + Inverted Event 1 Input Enable + 13 + 1 + + + TCEI0 + Timer/counter Event 0 Input Enable + 14 + 1 + + + TCEI1 + Timer/counter Event 1 Input Enable + 15 + 1 + + + MCEI0 + Match or Capture Channel 0 Event Input Enable + 16 + 1 + + + MCEI1 + Match or Capture Channel 1 Event Input Enable + 17 + 1 + + + MCEI2 + Match or Capture Channel 2 Event Input Enable + 18 + 1 + + + MCEI3 + Match or Capture Channel 3 Event Input Enable + 19 + 1 + + + MCEO0 + Match or Capture Channel 0 Event Output Enable + 24 + 1 + + + MCEO1 + Match or Capture Channel 1 Event Output Enable + 25 + 1 + + + MCEO2 + Match or Capture Channel 2 Event Output Enable + 26 + 1 + + + MCEO3 + Match or Capture Channel 3 Event Output Enable + 27 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x24 + 32 + 0x00000000 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + TRG + Retrigger Interrupt Enable + 1 + 1 + + + CNT + Counter Interrupt Enable + 2 + 1 + + + ERR + Error Interrupt Enable + 3 + 1 + + + UFS + Non-Recoverable Update Fault Interrupt Enable + 10 + 1 + + + DFS + Non-Recoverable Debug Fault Interrupt Enable + 11 + 1 + + + FAULTA + Recoverable Fault A Interrupt Enable + 12 + 1 + + + FAULTB + Recoverable Fault B Interrupt Enable + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 Interrupt Enable + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 Interrupt Enable + 15 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 16 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 17 + 1 + + + MC2 + Match or Capture Channel 2 Interrupt Enable + 18 + 1 + + + MC3 + Match or Capture Channel 3 Interrupt Enable + 19 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x28 + 32 + 0x00000000 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + TRG + Retrigger Interrupt Enable + 1 + 1 + + + CNT + Counter Interrupt Enable + 2 + 1 + + + ERR + Error Interrupt Enable + 3 + 1 + + + UFS + Non-Recoverable Update Fault Interrupt Enable + 10 + 1 + + + DFS + Non-Recoverable Debug Fault Interrupt Enable + 11 + 1 + + + FAULTA + Recoverable Fault A Interrupt Enable + 12 + 1 + + + FAULTB + Recoverable Fault B Interrupt Enable + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 Interrupt Enable + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 Interrupt Enable + 15 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 16 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 17 + 1 + + + MC2 + Match or Capture Channel 2 Interrupt Enable + 18 + 1 + + + MC3 + Match or Capture Channel 3 Interrupt Enable + 19 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x2C + 32 + 0x00000000 + + + OVF + Overflow + 0 + 1 + + + TRG + Retrigger + 1 + 1 + + + CNT + Counter + 2 + 1 + + + ERR + Error + 3 + 1 + + + UFS + Non-Recoverable Update Fault + 10 + 1 + + + DFS + Non-Recoverable Debug Fault + 11 + 1 + + + FAULTA + Recoverable Fault A + 12 + 1 + + + FAULTB + Recoverable Fault B + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 + 15 + 1 + + + MC0 + Match or Capture 0 + 16 + 1 + + + MC1 + Match or Capture 1 + 17 + 1 + + + MC2 + Match or Capture 2 + 18 + 1 + + + MC3 + Match or Capture 3 + 19 + 1 + + + + + STATUS + Status + 0x30 + 32 + 0x00000001 + + + STOP + Stop + 0 + 1 + + + IDX + Ramp + 1 + 1 + + + UFS + Non-recoverable Update Fault State + 2 + 1 + + + DFS + Non-Recoverable Debug Fault State + 3 + 1 + + + SLAVE + Slave + 4 + 1 + + + PATTBUFV + Pattern Buffer Valid + 5 + 1 + + + PERBUFV + Period Buffer Valid + 7 + 1 + + + FAULTAIN + Recoverable Fault A Input + 8 + 1 + + + FAULTBIN + Recoverable Fault B Input + 9 + 1 + + + FAULT0IN + Non-Recoverable Fault0 Input + 10 + 1 + + + FAULT1IN + Non-Recoverable Fault1 Input + 11 + 1 + + + FAULTA + Recoverable Fault A State + 12 + 1 + + + FAULTB + Recoverable Fault B State + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 State + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 State + 15 + 1 + + + CCBUFV0 + Compare Channel 0 Buffer Valid + 16 + 1 + + + CCBUFV1 + Compare Channel 1 Buffer Valid + 17 + 1 + + + CCBUFV2 + Compare Channel 2 Buffer Valid + 18 + 1 + + + CCBUFV3 + Compare Channel 3 Buffer Valid + 19 + 1 + + + CMP0 + Compare Channel 0 Value + 24 + 1 + + + CMP1 + Compare Channel 1 Value + 25 + 1 + + + CMP2 + Compare Channel 2 Value + 26 + 1 + + + CMP3 + Compare Channel 3 Value + 27 + 1 + + + + + COUNT + Count + 0x34 + 32 + 0x00000000 + + + COUNT + Counter Value + 0 + 24 + + + + + COUNT_DITH4_MODE + Count + COUNT + 0x34 + 32 + 0x00000000 + + + COUNT + Counter Value + 4 + 20 + + + + + COUNT_DITH5_MODE + Count + COUNT + 0x34 + 32 + 0x00000000 + + + COUNT + Counter Value + 5 + 19 + + + + + COUNT_DITH6_MODE + Count + COUNT + 0x34 + 32 + 0x00000000 + + + COUNT + Counter Value + 6 + 18 + + + + + PATT + Pattern + 0x38 + 16 + 0x0000 + + + PGE0 + Pattern Generator 0 Output Enable + 0 + 1 + + + PGE1 + Pattern Generator 1 Output Enable + 1 + 1 + + + PGE2 + Pattern Generator 2 Output Enable + 2 + 1 + + + PGE3 + Pattern Generator 3 Output Enable + 3 + 1 + + + PGE4 + Pattern Generator 4 Output Enable + 4 + 1 + + + PGE5 + Pattern Generator 5 Output Enable + 5 + 1 + + + PGE6 + Pattern Generator 6 Output Enable + 6 + 1 + + + PGE7 + Pattern Generator 7 Output Enable + 7 + 1 + + + PGV0 + Pattern Generator 0 Output Value + 8 + 1 + + + PGV1 + Pattern Generator 1 Output Value + 9 + 1 + + + PGV2 + Pattern Generator 2 Output Value + 10 + 1 + + + PGV3 + Pattern Generator 3 Output Value + 11 + 1 + + + PGV4 + Pattern Generator 4 Output Value + 12 + 1 + + + PGV5 + Pattern Generator 5 Output Value + 13 + 1 + + + PGV6 + Pattern Generator 6 Output Value + 14 + 1 + + + PGV7 + Pattern Generator 7 Output Value + 15 + 1 + + + + + WAVE + Waveform Control + 0x3C + 32 + 0x00000000 + + + WAVEGEN + Waveform Generation + 0 + 3 + + WAVEGENSelect + + NFRQ + Normal frequency + 0 + + + MFRQ + Match frequency + 1 + + + NPWM + Normal PWM + 2 + + + DSCRITICAL + Dual-slope critical + 4 + + + DSBOTTOM + Dual-slope with interrupt/event condition when COUNT reaches ZERO + 5 + + + DSBOTH + Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP + 6 + + + DSTOP + Dual-slope with interrupt/event condition when COUNT reaches TOP + 7 + + + + + RAMP + Ramp Mode + 4 + 2 + + RAMPSelect + + RAMP1 + RAMP1 operation + 0 + + + RAMP2A + Alternative RAMP2 operation + 1 + + + RAMP2 + RAMP2 operation + 2 + + + RAMP2C + Critical RAMP2 operation + 3 + + + + + CIPEREN + Circular period Enable + 7 + 1 + + + CICCEN0 + Circular Channel 0 Enable + 8 + 1 + + + CICCEN1 + Circular Channel 1 Enable + 9 + 1 + + + CICCEN2 + Circular Channel 2 Enable + 10 + 1 + + + CICCEN3 + Circular Channel 3 Enable + 11 + 1 + + + POL0 + Channel 0 Polarity + 16 + 1 + + + POL1 + Channel 1 Polarity + 17 + 1 + + + POL2 + Channel 2 Polarity + 18 + 1 + + + POL3 + Channel 3 Polarity + 19 + 1 + + + SWAP0 + Swap DTI Output Pair 0 + 24 + 1 + + + SWAP1 + Swap DTI Output Pair 1 + 25 + 1 + + + SWAP2 + Swap DTI Output Pair 2 + 26 + 1 + + + SWAP3 + Swap DTI Output Pair 3 + 27 + 1 + + + + + PER + Period + 0x40 + 32 + 0xFFFFFFFF + + + PER + Period Value + 0 + 24 + + + + + PER_DITH4_MODE + Period + PER + 0x40 + 32 + 0xFFFFFFFF + + + DITHER + Dithering Cycle Number + 0 + 4 + + + PER + Period Value + 4 + 20 + + + + + PER_DITH5_MODE + Period + PER + 0x40 + 32 + 0xFFFFFFFF + + + DITHER + Dithering Cycle Number + 0 + 5 + + + PER + Period Value + 5 + 19 + + + + + PER_DITH6_MODE + Period + PER + 0x40 + 32 + 0xFFFFFFFF + + + DITHER + Dithering Cycle Number + 0 + 6 + + + PER + Period Value + 6 + 18 + + + + + 4 + 4 + CC[%s] + Compare and Capture + 0x44 + 32 + 0x00000000 + + + CC + Channel Compare/Capture Value + 0 + 24 + + + + + 4 + 4 + CC_DITH4_MODE[%s] + Compare and Capture + CC[%s] + 0x44 + 32 + 0x00000000 + + + DITHER + Dithering Cycle Number + 0 + 4 + + + CC + Channel Compare/Capture Value + 4 + 20 + + + + + 4 + 4 + CC_DITH5_MODE[%s] + Compare and Capture + CC[%s] + 0x44 + 32 + 0x00000000 + + + DITHER + Dithering Cycle Number + 0 + 5 + + + CC + Channel Compare/Capture Value + 5 + 19 + + + + + 4 + 4 + CC_DITH6_MODE[%s] + Compare and Capture + CC[%s] + 0x44 + 32 + 0x00000000 + + + DITHER + Dithering Cycle Number + 0 + 6 + + + CC + Channel Compare/Capture Value + 6 + 18 + + + + + PATTBUF + Pattern Buffer + 0x64 + 16 + 0x0000 + + + PGEB0 + Pattern Generator 0 Output Enable Buffer + 0 + 1 + + + PGEB1 + Pattern Generator 1 Output Enable Buffer + 1 + 1 + + + PGEB2 + Pattern Generator 2 Output Enable Buffer + 2 + 1 + + + PGEB3 + Pattern Generator 3 Output Enable Buffer + 3 + 1 + + + PGEB4 + Pattern Generator 4 Output Enable Buffer + 4 + 1 + + + PGEB5 + Pattern Generator 5 Output Enable Buffer + 5 + 1 + + + PGEB6 + Pattern Generator 6 Output Enable Buffer + 6 + 1 + + + PGEB7 + Pattern Generator 7 Output Enable Buffer + 7 + 1 + + + PGVB0 + Pattern Generator 0 Output Enable + 8 + 1 + + + PGVB1 + Pattern Generator 1 Output Enable + 9 + 1 + + + PGVB2 + Pattern Generator 2 Output Enable + 10 + 1 + + + PGVB3 + Pattern Generator 3 Output Enable + 11 + 1 + + + PGVB4 + Pattern Generator 4 Output Enable + 12 + 1 + + + PGVB5 + Pattern Generator 5 Output Enable + 13 + 1 + + + PGVB6 + Pattern Generator 6 Output Enable + 14 + 1 + + + PGVB7 + Pattern Generator 7 Output Enable + 15 + 1 + + + + + PERBUF + Period Buffer + 0x6C + 32 + 0xFFFFFFFF + + + PERBUF + Period Buffer Value + 0 + 24 + + + + + PERBUF_DITH4_MODE + Period Buffer + PERBUF + 0x6C + 32 + 0xFFFFFFFF + + + DITHERBUF + Dithering Buffer Cycle Number + 0 + 4 + + + PERBUF + Period Buffer Value + 4 + 20 + + + + + PERBUF_DITH5_MODE + Period Buffer + PERBUF + 0x6C + 32 + 0xFFFFFFFF + + + DITHERBUF + Dithering Buffer Cycle Number + 0 + 5 + + + PERBUF + Period Buffer Value + 5 + 19 + + + + + PERBUF_DITH6_MODE + Period Buffer + PERBUF + 0x6C + 32 + 0xFFFFFFFF + + + DITHERBUF + Dithering Buffer Cycle Number + 0 + 6 + + + PERBUF + Period Buffer Value + 6 + 18 + + + + + 4 + 4 + CCBUF[%s] + Compare and Capture Buffer + 0x70 + 32 + 0x00000000 + + + CCBUF + Channel Compare/Capture Buffer Value + 0 + 24 + + + + + 4 + 4 + CCBUF_DITH4_MODE[%s] + Compare and Capture Buffer + CCBUF[%s] + 0x70 + 32 + 0x00000000 + + + CCBUF + Channel Compare/Capture Buffer Value + 0 + 4 + + + DITHERBUF + Dithering Buffer Cycle Number + 4 + 20 + + + + + 4 + 4 + CCBUF_DITH5_MODE[%s] + Compare and Capture Buffer + CCBUF[%s] + 0x70 + 32 + 0x00000000 + + + DITHERBUF + Dithering Buffer Cycle Number + 0 + 5 + + + CCBUF + Channel Compare/Capture Buffer Value + 5 + 19 + + + + + 4 + 4 + CCBUF_DITH6_MODE[%s] + Compare and Capture Buffer + CCBUF[%s] + 0x70 + 32 + 0x00000000 + + + DITHERBUF + Dithering Buffer Cycle Number + 0 + 6 + + + CCBUF + Channel Compare/Capture Buffer Value + 6 + 18 + + + + + + + TCC1 + 0x42002800 + + TCC1 + 18 + + + + TCC2 + 0x42002C00 + + TCC2 + 19 + + + + TSENS + U22611.0.1 + Temperature Sensor + TSENS + TSENS_ + 0x40003000 + + 0 + 0x25 + registers + + + TSENS + 5 + + + + CTRLA + Control A Register + 0x0 + 8 + 0x00 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + + + CTRLB + Control B Register + 0x1 + 8 + write-only + 0x00 + + + START + Start Measurement + 0 + 1 + + + + + CTRLC + Control C Register + 0x2 + 8 + 0x00 + + + WINMODE + Window Monitor Mode + 0 + 3 + + WINMODESelect + + DISABLE + No window mode (default) + 0 + + + ABOVE + VALUE greater than WINLT + 1 + + + BELOW + VALUE less than WINUT + 2 + + + INSIDE + VALUE greater than WINLT and VALUE less than WINUT + 3 + + + OUTSIDE + VALUE less than WINLT or VALUE greater than WINUT + 4 + + + HYST_ABOVE + VALUE greater than WINUT with hysteresis to WINLT + 5 + + + HYST_BELOW + VALUE less than WINLST with hysteresis to WINUT + 6 + + + + + FREERUN + Free Running Measurement + 4 + 1 + + + + + EVCTRL + Event Control Register + 0x3 + 8 + 0x00 + + + STARTEI + Start Conversion Event Input Enable + 0 + 1 + + + STARTINV + Start Conversion Event Invert Enable + 1 + 1 + + + WINEO + Window Monitor Event Out + 2 + 1 + + + + + INTENCLR + Interrupt Enable Clear Register + 0x4 + 8 + 0x00 + + + RESRDY + Result Ready Interrupt Enable + 0 + 1 + + + OVERRUN + Overrun Interrupt Enable + 1 + 1 + + + WINMON + Window Monitor Interrupt Enable + 2 + 1 + + + OVF + Overflow Interrupt Enable + 3 + 1 + + + + + INTENSET + Interrupt Enable Set Register + 0x5 + 8 + 0x00 + + + RESRDY + Result Ready Interrupt Enable + 0 + 1 + + + OVERRUN + Overrun Interrupt Enable + 1 + 1 + + + WINMON + Window Monitor Interrupt Enable + 2 + 1 + + + OVF + Overflow Interrupt Enable + 3 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear Register + 0x6 + 8 + 0x00 + + + RESRDY + Result Ready + 0 + 1 + + + OVERRUN + Overrun + 1 + 1 + + + WINMON + Window Monitor + 2 + 1 + + + OVF + Overflow + 3 + 1 + + + + + STATUS + Status Register + 0x7 + 8 + read-only + 0x00 + + + OVF + Result Overflow + 0 + 1 + + + + + SYNCBUSY + Synchronization Busy Register + 0x8 + 32 + read-only + 0x00000000 + + + SWRST + Software Reset Busy + 0 + 1 + + + ENABLE + Enable Busy + 1 + 1 + + + + + VALUE + Value Register + 0xC + 32 + read-only + 0x00000000 + + + VALUE + Measurement Value + 0 + 24 + + + + + WINLT + Window Monitor Lower Threshold Register + 0x10 + 32 + 0x00000000 + + + WINLT + Window Lower Threshold + 0 + 24 + + + + + WINUT + Window Monitor Upper Threshold Register + 0x14 + 32 + 0x00000000 + + + WINUT + Window Upper Threshold + 0 + 24 + + + + + GAIN + Gain Register + 0x18 + 32 + 0x00000000 + + + GAIN + Time Amplifier Gain + 0 + 24 + + + + + OFFSET + Offset Register + 0x1C + 32 + 0x00000000 + + + OFFSETC + Offset Correction + 0 + 24 + + + + + CAL + Calibration Register + 0x20 + 32 + 0x00000000 + + + FCAL + Frequency Calibration + 0 + 6 + + + TCAL + Temperature Calibration + 8 + 6 + + + + + DBGCTRL + Debug Control Register + 0x24 + 8 + 0x00 + + + DBGRUN + Debug Run + 0 + 1 + + + + + + + WDT + U22511.0.1 + Watchdog Timer + WDT + WDT_ + 0x40002000 + + 0 + 0xD + registers + + + WDT + 1 + + + + CTRLA + Control + 0x0 + 8 + 0x00 + + + ENABLE + Enable + 1 + 1 + + + WEN + Watchdog Timer Window Mode Enable + 2 + 1 + + + ALWAYSON + Always-On + 7 + 1 + + + + + CONFIG + Configuration + 0x1 + 8 + 0xBB + + + PER + Time-Out Period + 0 + 4 + + PERSelect + + CYC8 + 8 clock cycles + 0x0 + + + CYC16 + 16 clock cycles + 0x1 + + + CYC32 + 32 clock cycles + 0x2 + + + CYC64 + 64 clock cycles + 0x3 + + + CYC128 + 128 clock cycles + 0x4 + + + CYC256 + 256 clock cycles + 0x5 + + + CYC512 + 512 clock cycles + 0x6 + + + CYC1024 + 1024 clock cycles + 0x7 + + + CYC2048 + 2048 clock cycles + 0x8 + + + CYC4096 + 4096 clock cycles + 0x9 + + + CYC8192 + 8192 clock cycles + 0xA + + + CYC16384 + 16384 clock cycles + 0xB + + + + + WINDOW + Window Mode Time-Out Period + 4 + 4 + + WINDOWSelect + + CYC8 + 8 clock cycles + 0x0 + + + CYC16 + 16 clock cycles + 0x1 + + + CYC32 + 32 clock cycles + 0x2 + + + CYC64 + 64 clock cycles + 0x3 + + + CYC128 + 128 clock cycles + 0x4 + + + CYC256 + 256 clock cycles + 0x5 + + + CYC512 + 512 clock cycles + 0x6 + + + CYC1024 + 1024 clock cycles + 0x7 + + + CYC2048 + 2048 clock cycles + 0x8 + + + CYC4096 + 4096 clock cycles + 0x9 + + + CYC8192 + 8192 clock cycles + 0xA + + + CYC16384 + 16384 clock cycles + 0xB + + + + + + + EWCTRL + Early Warning Interrupt Control + 0x2 + 8 + 0x0B + + + EWOFFSET + Early Warning Interrupt Time Offset + 0 + 4 + + EWOFFSETSelect + + CYC8 + 8 clock cycles + 0x0 + + + CYC16 + 16 clock cycles + 0x1 + + + CYC32 + 32 clock cycles + 0x2 + + + CYC64 + 64 clock cycles + 0x3 + + + CYC128 + 128 clock cycles + 0x4 + + + CYC256 + 256 clock cycles + 0x5 + + + CYC512 + 512 clock cycles + 0x6 + + + CYC1024 + 1024 clock cycles + 0x7 + + + CYC2048 + 2048 clock cycles + 0x8 + + + CYC4096 + 4096 clock cycles + 0x9 + + + CYC8192 + 8192 clock cycles + 0xA + + + CYC16384 + 16384 clock cycles + 0xB + + + + + + + INTENCLR + Interrupt Enable Clear + 0x4 + 8 + 0x00 + + + EW + Early Warning Interrupt Enable + 0 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x5 + 8 + 0x00 + + + EW + Early Warning Interrupt Enable + 0 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x6 + 8 + 0x00 + + + EW + Early Warning + 0 + 1 + + + + + SYNCBUSY + Synchronization Busy + 0x8 + 32 + read-only + 0x00000000 + + + ENABLE + Enable Busy + 1 + 1 + + + WEN + Window Enable Busy + 2 + 1 + + + ALWAYSON + Always-On Busy + 3 + 1 + + + CLEAR + Clear Busy + 4 + 1 + + + + + CLEAR + Clear + 0xC + 8 + write-only + 0x00 + + + CLEAR + Watchdog Clear + 0 + 8 + + CLEARSelect + + KEY + Clear Key + 0xA5 + + + + + + + + + MPU + Memory Protection Unit + MPU + MPU_ + 0xE000ED90 + + 0 + 0x14 + registers + + + + TYPE + MPU Type Register + 0x0 + 32 + read-only + + + SEPARATE + Separate instruction and Data Memory MapsRegions + 0 + 1 + + + DREGION + Number of Data Regions + 8 + 8 + + + IREGION + Number of Instruction Regions + 16 + 8 + + + + + CTRL + MPU Control Register + 0x4 + 32 + + + ENABLE + MPU Enable + 0 + 1 + + + HFNMIENA + Enable Hard Fault and NMI handlers + 1 + 1 + + + PRIVDEFENA + Enables privileged software access to default memory map + 2 + 1 + + + + + RNR + MPU Region Number Register + 0x8 + 32 + + + REGION + Region referenced by RBAR and RASR + 0 + 8 + + + + + RBAR + MPU Region Base Address Register + 0xC + 32 + + + REGION + Region number + 0 + 4 + + + VALID + Region number valid + 4 + 1 + + + ADDR + Region base address + 5 + 27 + + + + + RASR + MPU Region Attribute and Size Register + 0x10 + 32 + + + ENABLE + Region Enable + 0 + 1 + + + SIZE + Region Size + 1 + 5 + + + SRD + Sub-region disable + 8 + 8 + + + B + Bufferable bit + 16 + 1 + + + C + Cacheable bit + 17 + 1 + + + S + Shareable bit + 18 + 1 + + + TEX + TEX bit + 19 + 3 + + + AP + Access Permission + 24 + 3 + + + XN + Execute Never Attribute + 28 + 1 + + + + + + + NVIC + Nested Vectored Interrupt Controller + NVIC + NVIC_ + 0xE000E100 + + 0 + 0x320 + registers + + + + ISER + Interrupt Set Enable Register + 0x0 + 32 + 0x00000000 + + + SETENA + Interrupt set enable bits + 0 + 31 + + + + + ICER + Interrupt Clear Enable Register + 0x80 + 32 + 0x00000000 + + + CLRENA + Interrupt clear-enable bits + 0 + 31 + + + + + ISPR + Interrupt Set Pending Register + 0x100 + 32 + 0x00000000 + + + SETPEND + Interrupt set-pending bits + 0 + 31 + + + + + ICPR + Interrupt Clear Pending Register + 0x180 + 32 + 0x00000000 + + + CLRPEND + Interrupt clear-pending bits + 0 + 31 + + + + + 8 + 4 + IPR[%s] + Interrupt Priority Register n + 0x300 + 32 + 0x00000000 + + + PRI0 + Priority of interrupt n + 0 + 2 + + + PRI1 + Priority of interrupt n + 8 + 2 + + + PRI2 + Priority of interrupt n + 16 + 2 + + + PRI3 + Priority of interrupt n + 24 + 2 + + + + + + + SysTick + System timer + SysTick + SysTick_ + 0xE000E010 + + 0 + 0x10 + registers + + + + CSR + SysTick Control and Status Register + 0x0 + 32 + 0x4 + + + ENABLE + SysTick Counter Enable + 0 + 1 + + ENABLESelect + + VALUE_0 + Counter disabled + 0 + + + VALUE_1 + Counter enabled + 1 + + + + + TICKINT + SysTick Exception Request Enable + 1 + 1 + + TICKINTSelect + + VALUE_0 + Counting down to 0 does not assert the SysTick exception request + 0 + + + VALUE_1 + Counting down to 0 asserts the SysTick exception request + 1 + + + + + CLKSOURCE + Clock Source 0=external, 1=processor + 2 + 1 + + CLKSOURCESelect + + VALUE_0 + External clock + 0 + + + VALUE_1 + Processor clock + 1 + + + + + COUNTFLAG + Timer counted to 0 since last read of register + 16 + 1 + + + + + RVR + SysTick Reload Value Register + 0x4 + 32 + + + RELOAD + Value to load into the SysTick Current Value Register when the counter reaches 0 + 0 + 24 + + + + + CVR + SysTick Current Value Register + 0x8 + 32 + + + CURRENT + Current value at the time the register is accessed + 0 + 24 + + + + + CALIB + SysTick Calibration Value Register + 0xC + 32 + read-only + 0 + + + TENMS + Reload value to use for 10ms timing + 0 + 24 + + + SKEW + TENMS is rounded from non-integer ratio + 30 + 1 + + SKEWSelect + + VALUE_0 + 10ms calibration value is exact + 0 + + + VALUE_1 + 10ms calibration value is inexact, because of the clock frequency + 1 + + + + + NOREF + No Separate Reference Clock + 31 + 1 + + NOREFSelect + + VALUE_0 + The reference clock is provided + 0 + + + VALUE_1 + The reference clock is not provided + 1 + + + + + + + + + SystemControl + System Control Registers + SystemControl + SystemControl_ + 0xE000E000 + + 0 + 0xD34 + registers + + + + CPUID + CPUID Base Register + 0xD00 + 32 + read-only + 0x410CC601 + + + REVISION + Minor revision number + 0 + 4 + + + PARTNO + Processor Part Number, 0xC60=Cortex-M0+ + 4 + 12 + + + ARCHITECTURE + Processor Architecture, 0xC=ARMv6-M + 16 + 4 + + + VARIANT + Major revision number + 20 + 4 + + + IMPLEMENTER + Implementer code, ARM=0x41 + 24 + 8 + + + + + ICSR + Interrupt Control and State Register + 0xD04 + 32 + 0x00000000 + + + VECTACTIVE + Debug: Exception number of currently executing exception, or 0 if thread mode + 0 + 9 + + + VECTPENDING + Exception number of the highest priority pending enabled exception + 12 + 9 + + + ISRPENDING + Debug: NVIC interrupt pending + 22 + 1 + + + ISRPREEMPT + Debug: Pending exception serviced on exit from debug halt + 23 + 1 + + + PENDSTCLR + SysTick exception clear-pending bit + 25 + 1 + + PENDSTCLRSelect + + VALUE_0 + No effect + 0 + + + VALUE_1 + Removes the pending state from the SysTick exception + 1 + + + + + PENDSTSET + SysTick exception set-pending bit + 26 + 1 + + PENDSTSETSelect + + VALUE_0 + Write: no effect; read: SysTick exception is not pending + 0 + + + VALUE_1 + Write: changes SysTick exception state to pending; read: SysTick exception is pending + 1 + + + + + PENDSVCLR + PendSV clear-pending bit + 27 + 1 + + PENDSVCLRSelect + + VALUE_0 + No effect + 0 + + + VALUE_1 + Removes the pending state from the PendSV exception + 1 + + + + + PENDSVSET + PendSV set-pending bit + 28 + 1 + + PENDSVSETSelect + + VALUE_0 + Write: no effect; read: PendSV exception is not pending + 0 + + + VALUE_1 + Write: changes PendSV exception state to pending; read: PendSV exception is pending + 1 + + + + + NMIPENDSET + NMI set-pending bit + 31 + 1 + + NMIPENDSETSelect + + VALUE_0 + Write: no effect; read: NMI exception is not pending + 0 + + + VALUE_1 + Write: changes NMI exception state to pending; read: NMI exception is pending + 1 + + + + + + + VTOR + Vector Table Offset Register + 0xD08 + 32 + 0x00000000 + + + TBLOFF + Vector table base offset + 7 + 25 + + + + + AIRCR + Application Interrupt and Reset Control Register + 0xD0C + 32 + 0x00000000 + + + VECTCLRACTIVE + Debug: Clear state information + 1 + 1 + + + SYSRESETREQ + System Reset Request + 2 + 1 + + SYSRESETREQSelect + + VALUE_0 + No system reset request + 0 + + + VALUE_1 + Asserts a signal to the outer system that requests a reset + 1 + + + + + ENDIANNESS + Data Endianness, 0=little, 1=big + 15 + 1 + + ENDIANNESSSelect + + VALUE_0 + Little-endian + 0 + + + VALUE_1 + Big-endian + 1 + + + + + VECTKEY + Register key (0x05FA) + 16 + 16 + + + + + SCR + System Control Register + 0xD10 + 32 + 0x00000000 + + + SLEEPONEXIT + Sleep-On-Exit when exiting Handler mode + 1 + 1 + + SLEEPONEXITSelect + + VALUE_0 + O not sleep when returning to Thread mode + 0 + + + VALUE_1 + Enter sleep, or deep sleep, on return from an ISR + 1 + + + + + SLEEPDEEP + Uses Deep Sleep as low power mode + 2 + 1 + + SLEEPDEEPSelect + + VALUE_0 + Sleep + 0 + + + VALUE_1 + Deep sleep + 1 + + + + + SEVONPEND + Send Event on Pending bit + 4 + 1 + + SEVONPENDSelect + + VALUE_0 + Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded + 0 + + + VALUE_1 + Enabled events and all interrupts, including disabled interrupts, can wakeup the processor + 1 + + + + + + + CCR + Configuration and Control Register + 0xD14 + 32 + read-only + 0x00000204 + + + UNALIGN_TRP + Unaligned accesses generates a Hard Fault + 3 + 1 + + UNALIGN_TRPSelect + + VALUE_0 + Do not trap unaligned halfword and word accesses + 0 + + + VALUE_1 + Trap unaligned halfword and word accesses + 1 + + + + + STKALIGN + Stack 8-byte aligned on exception entry + 9 + 1 + + STKALIGNSelect + + VALUE_0 + 4-byte aligned + 0 + + + VALUE_1 + 8-byte aligned + 1 + + + + + + + SHPR2 + System Handler Priority Register 2 + 0xD1C + 32 + 0x00000000 + + + PRI_11 + Priority of system handler 11, SVCall + 24 + 8 + + + + + SHPR3 + System Handler Priority Register 3 + 0xD20 + 32 + 0x00000000 + + + PRI_14 + Priority of system handler 14, PendSV + 16 + 8 + + + PRI_15 + Priority of system handler 15, SysTick exception + 24 + 8 + + + + + SHCSR + System Handler Control and State Register + 0xD24 + 32 + 0x00000000 + + + SVCALLPENDED + 15 + 1 + + + + + DFSR + Debug Fault Status Register + 0xD30 + 32 + 0x00000000 + + + HALTED + Halt request debug event active + 0 + 1 + + + BKPT + Breakpoint debug event + 1 + 1 + + + DWTTRAP + DWT debug event + 2 + 1 + + + VCATCH + Vector catch debug event + 3 + 1 + + + EXTERNAL + EDBGRQ debug event + 4 + 1 + + + + + + + From e3477b0f2d7e28e992d439ed0a1514bb387f77d1 Mon Sep 17 00:00:00 2001 From: Jeremy Boynes Date: Fri, 6 Jan 2023 20:57:31 -0800 Subject: [PATCH 2/3] Generate SAM C2x PACs from SVDs --- pac/atsamc20e/CHANGELOG.md | 6 + pac/atsamc20e/Cargo.toml | 22 + pac/atsamc20e/README.md | 26 + pac/atsamc20e/build.rs | 16 + pac/atsamc20e/device.x | 23 + pac/atsamc20e/src/ac.rs | 83 + pac/atsamc20e/src/ac/compctrl.rs | 974 + pac/atsamc20e/src/ac/ctrla.rs | 160 + pac/atsamc20e/src/ac/ctrlb.rs | 99 + pac/atsamc20e/src/ac/dbgctrl.rs | 113 + pac/atsamc20e/src/ac/evctrl.rs | 395 + pac/atsamc20e/src/ac/intenclr.rs | 207 + pac/atsamc20e/src/ac/intenset.rs | 207 + pac/atsamc20e/src/ac/intflag.rs | 207 + pac/atsamc20e/src/ac/scaler.rs | 104 + pac/atsamc20e/src/ac/statusa.rs | 135 + pac/atsamc20e/src/ac/statusb.rs | 73 + pac/atsamc20e/src/ac/syncbusy.rs | 133 + pac/atsamc20e/src/ac/winctrl.rs | 225 + pac/atsamc20e/src/adc0.rs | 141 + pac/atsamc20e/src/adc0/avgctrl.rs | 306 + pac/atsamc20e/src/adc0/calib.rs | 140 + pac/atsamc20e/src/adc0/ctrla.rs | 301 + pac/atsamc20e/src/adc0/ctrlb.rs | 230 + pac/atsamc20e/src/adc0/ctrlc.rs | 538 + pac/atsamc20e/src/adc0/dbgctrl.rs | 113 + pac/atsamc20e/src/adc0/evctrl.rs | 348 + pac/atsamc20e/src/adc0/gaincorr.rs | 103 + pac/atsamc20e/src/adc0/inputctrl.rs | 472 + pac/atsamc20e/src/adc0/intenclr.rs | 207 + pac/atsamc20e/src/adc0/intenset.rs | 207 + pac/atsamc20e/src/adc0/intflag.rs | 207 + pac/atsamc20e/src/adc0/offsetcorr.rs | 103 + pac/atsamc20e/src/adc0/refctrl.rs | 238 + pac/atsamc20e/src/adc0/result.rs | 53 + pac/atsamc20e/src/adc0/sampctrl.rs | 150 + pac/atsamc20e/src/adc0/seqctrl.rs | 103 + pac/atsamc20e/src/adc0/seqstatus.rs | 73 + pac/atsamc20e/src/adc0/swtrig.rs | 160 + pac/atsamc20e/src/adc0/syncbusy.rs | 253 + pac/atsamc20e/src/adc0/winlt.rs | 103 + pac/atsamc20e/src/adc0/winut.rs | 103 + pac/atsamc20e/src/ccl.rs | 24 + pac/atsamc20e/src/ccl/ctrl.rs | 207 + pac/atsamc20e/src/ccl/lutctrl.rs | 702 + pac/atsamc20e/src/ccl/seqctrl.rs | 192 + pac/atsamc20e/src/divas.rs | 48 + pac/atsamc20e/src/divas/ctrla.rs | 160 + pac/atsamc20e/src/divas/dividend.rs | 103 + pac/atsamc20e/src/divas/divisor.rs | 103 + pac/atsamc20e/src/divas/rem.rs | 53 + pac/atsamc20e/src/divas/result.rs | 53 + pac/atsamc20e/src/divas/sqrnum.rs | 103 + pac/atsamc20e/src/divas/status.rs | 160 + pac/atsamc20e/src/dmac.rs | 148 + pac/atsamc20e/src/dmac/active.rs | 173 + pac/atsamc20e/src/dmac/baseaddr.rs | 103 + pac/atsamc20e/src/dmac/busych.rs | 153 + pac/atsamc20e/src/dmac/chctrla.rs | 207 + pac/atsamc20e/src/dmac/chctrlb.rs | 1188 + pac/atsamc20e/src/dmac/chid.rs | 103 + pac/atsamc20e/src/dmac/chintenclr.rs | 207 + pac/atsamc20e/src/dmac/chintenset.rs | 207 + pac/atsamc20e/src/dmac/chintflag.rs | 207 + pac/atsamc20e/src/dmac/chstatus.rs | 93 + pac/atsamc20e/src/dmac/crcchksum.rs | 103 + pac/atsamc20e/src/dmac/crcctrl.rs | 337 + pac/atsamc20e/src/dmac/crcdatain.rs | 103 + pac/atsamc20e/src/dmac/crcstatus.rs | 160 + pac/atsamc20e/src/dmac/ctrl.rs | 395 + pac/atsamc20e/src/dmac/dbgctrl.rs | 113 + pac/atsamc20e/src/dmac/intpend.rs | 385 + pac/atsamc20e/src/dmac/intstatus.rs | 153 + pac/atsamc20e/src/dmac/pendch.rs | 153 + pac/atsamc20e/src/dmac/prictrl0.rs | 449 + pac/atsamc20e/src/dmac/qosctrl.rs | 402 + pac/atsamc20e/src/dmac/swtrigctrl.rs | 348 + pac/atsamc20e/src/dmac/wrbaddr.rs | 103 + pac/atsamc20e/src/dsu.rs | 163 + pac/atsamc20e/src/dsu/addr.rs | 140 + pac/atsamc20e/src/dsu/cid0.rs | 53 + pac/atsamc20e/src/dsu/cid1.rs | 73 + pac/atsamc20e/src/dsu/cid2.rs | 53 + pac/atsamc20e/src/dsu/cid3.rs | 53 + pac/atsamc20e/src/dsu/ctrl.rs | 207 + pac/atsamc20e/src/dsu/data.rs | 103 + pac/atsamc20e/src/dsu/dcc.rs | 104 + pac/atsamc20e/src/dsu/dcfg.rs | 104 + pac/atsamc20e/src/dsu/did.rs | 279 + pac/atsamc20e/src/dsu/end.rs | 53 + pac/atsamc20e/src/dsu/entry0.rs | 93 + pac/atsamc20e/src/dsu/entry1.rs | 31 + pac/atsamc20e/src/dsu/length.rs | 103 + pac/atsamc20e/src/dsu/memtype.rs | 53 + pac/atsamc20e/src/dsu/pid0.rs | 53 + pac/atsamc20e/src/dsu/pid1.rs | 73 + pac/atsamc20e/src/dsu/pid2.rs | 93 + pac/atsamc20e/src/dsu/pid3.rs | 73 + pac/atsamc20e/src/dsu/pid4.rs | 73 + pac/atsamc20e/src/dsu/pid5.rs | 31 + pac/atsamc20e/src/dsu/pid6.rs | 31 + pac/atsamc20e/src/dsu/pid7.rs | 31 + pac/atsamc20e/src/dsu/statusa.rs | 301 + pac/atsamc20e/src/dsu/statusb.rs | 133 + pac/atsamc20e/src/dsu/statusc.rs | 53 + pac/atsamc20e/src/eic.rs | 64 + pac/atsamc20e/src/eic/asynch.rs | 152 + pac/atsamc20e/src/eic/config.rs | 1547 + pac/atsamc20e/src/eic/ctrla.rs | 254 + pac/atsamc20e/src/eic/evctrl.rs | 103 + pac/atsamc20e/src/eic/intenclr.rs | 103 + pac/atsamc20e/src/eic/intenset.rs | 103 + pac/atsamc20e/src/eic/intflag.rs | 103 + pac/atsamc20e/src/eic/nmictrl.rs | 345 + pac/atsamc20e/src/eic/nmiflag.rs | 113 + pac/atsamc20e/src/eic/syncbusy.rs | 73 + pac/atsamc20e/src/evsys.rs | 54 + pac/atsamc20e/src/evsys/channel.rs | 409 + pac/atsamc20e/src/evsys/chstatus.rs | 273 + pac/atsamc20e/src/evsys/ctrla.rs | 113 + pac/atsamc20e/src/evsys/intenclr.rs | 630 + pac/atsamc20e/src/evsys/intenset.rs | 630 + pac/atsamc20e/src/evsys/intflag.rs | 630 + pac/atsamc20e/src/evsys/swevt.rs | 207 + pac/atsamc20e/src/evsys/user.rs | 104 + pac/atsamc20e/src/freqm.rs | 59 + pac/atsamc20e/src/freqm/cfga.rs | 103 + pac/atsamc20e/src/freqm/ctrla.rs | 160 + pac/atsamc20e/src/freqm/ctrlb.rs | 72 + pac/atsamc20e/src/freqm/intenclr.rs | 113 + pac/atsamc20e/src/freqm/intenset.rs | 113 + pac/atsamc20e/src/freqm/intflag.rs | 113 + pac/atsamc20e/src/freqm/status.rs | 160 + pac/atsamc20e/src/freqm/syncbusy.rs | 73 + pac/atsamc20e/src/freqm/value.rs | 53 + pac/atsamc20e/src/gclk.rs | 31 + pac/atsamc20e/src/gclk/ctrla.rs | 113 + pac/atsamc20e/src/gclk/genctrl.rs | 597 + pac/atsamc20e/src/gclk/pchctrl.rs | 338 + pac/atsamc20e/src/gclk/syncbusy.rs | 233 + pac/atsamc20e/src/generic.rs | 260 + pac/atsamc20e/src/hmatrixhs.rs | 43 + pac/atsamc20e/src/hmatrixhs/mcfg.rs | 192 + pac/atsamc20e/src/hmatrixhs/mrcr.rs | 1570 + pac/atsamc20e/src/hmatrixhs/prs.rs | 8 + pac/atsamc20e/src/hmatrixhs/prs/pras.rs | 362 + pac/atsamc20e/src/hmatrixhs/prs/prbs.rs | 362 + pac/atsamc20e/src/hmatrixhs/scfg.rs | 334 + pac/atsamc20e/src/hmatrixhs/sfr.rs | 104 + pac/atsamc20e/src/lib.rs | 1437 + pac/atsamc20e/src/mclk.rs | 54 + pac/atsamc20e/src/mclk/ahbmask.rs | 583 + pac/atsamc20e/src/mclk/apbamask.rs | 630 + pac/atsamc20e/src/mclk/apbbmask.rs | 254 + pac/atsamc20e/src/mclk/apbcmask.rs | 865 + pac/atsamc20e/src/mclk/cpudiv.rs | 230 + pac/atsamc20e/src/mclk/intenclr.rs | 113 + pac/atsamc20e/src/mclk/intenset.rs | 113 + pac/atsamc20e/src/mclk/intflag.rs | 113 + pac/atsamc20e/src/mtb.rs | 158 + pac/atsamc20e/src/mtb/authstatus.rs | 31 + pac/atsamc20e/src/mtb/base.rs | 31 + pac/atsamc20e/src/mtb/cid0.rs | 31 + pac/atsamc20e/src/mtb/cid1.rs | 31 + pac/atsamc20e/src/mtb/cid2.rs | 31 + pac/atsamc20e/src/mtb/cid3.rs | 31 + pac/atsamc20e/src/mtb/claimclr.rs | 64 + pac/atsamc20e/src/mtb/claimset.rs | 64 + pac/atsamc20e/src/mtb/devarch.rs | 31 + pac/atsamc20e/src/mtb/devid.rs | 31 + pac/atsamc20e/src/mtb/devtype.rs | 31 + pac/atsamc20e/src/mtb/flow.rs | 197 + pac/atsamc20e/src/mtb/itctrl.rs | 64 + pac/atsamc20e/src/mtb/lockaccess.rs | 64 + pac/atsamc20e/src/mtb/lockstatus.rs | 31 + pac/atsamc20e/src/mtb/master.rs | 385 + pac/atsamc20e/src/mtb/pid0.rs | 31 + pac/atsamc20e/src/mtb/pid1.rs | 31 + pac/atsamc20e/src/mtb/pid2.rs | 31 + pac/atsamc20e/src/mtb/pid3.rs | 31 + pac/atsamc20e/src/mtb/pid4.rs | 31 + pac/atsamc20e/src/mtb/pid5.rs | 31 + pac/atsamc20e/src/mtb/pid6.rs | 31 + pac/atsamc20e/src/mtb/pid7.rs | 31 + pac/atsamc20e/src/mtb/position.rs | 150 + pac/atsamc20e/src/nvmctrl.rs | 76 + pac/atsamc20e/src/nvmctrl/addr.rs | 103 + pac/atsamc20e/src/nvmctrl/ctrla.rs | 394 + pac/atsamc20e/src/nvmctrl/ctrlb.rs | 447 + pac/atsamc20e/src/nvmctrl/intenclr.rs | 160 + pac/atsamc20e/src/nvmctrl/intenset.rs | 160 + pac/atsamc20e/src/nvmctrl/intflag.rs | 160 + pac/atsamc20e/src/nvmctrl/lock.rs | 103 + pac/atsamc20e/src/nvmctrl/param.rs | 304 + pac/atsamc20e/src/nvmctrl/pbldata0.rs | 31 + pac/atsamc20e/src/nvmctrl/pbldata1.rs | 31 + pac/atsamc20e/src/nvmctrl/status.rs | 348 + pac/atsamc20e/src/osc32kctrl.rs | 64 + pac/atsamc20e/src/osc32kctrl/cfdctrl.rs | 207 + pac/atsamc20e/src/osc32kctrl/evctrl.rs | 113 + pac/atsamc20e/src/osc32kctrl/intenclr.rs | 207 + pac/atsamc20e/src/osc32kctrl/intenset.rs | 207 + pac/atsamc20e/src/osc32kctrl/intflag.rs | 207 + pac/atsamc20e/src/osc32kctrl/osc32k.rs | 549 + pac/atsamc20e/src/osc32kctrl/osculp32k.rs | 150 + pac/atsamc20e/src/osc32kctrl/rtcctrl.rs | 204 + pac/atsamc20e/src/osc32kctrl/status.rs | 113 + pac/atsamc20e/src/osc32kctrl/xosc32k.rs | 559 + pac/atsamc20e/src/oscctrl.rs | 117 + pac/atsamc20e/src/oscctrl/cal48m.rs | 177 + pac/atsamc20e/src/oscctrl/cfdpresc.rs | 230 + pac/atsamc20e/src/oscctrl/dpllctrla.rs | 207 + pac/atsamc20e/src/oscctrl/dpllctrlb.rs | 580 + pac/atsamc20e/src/oscctrl/dpllpresc.rs | 165 + pac/atsamc20e/src/oscctrl/dpllratio.rs | 140 + pac/atsamc20e/src/oscctrl/dpllstatus.rs | 73 + pac/atsamc20e/src/oscctrl/dpllsyncbusy.rs | 93 + pac/atsamc20e/src/oscctrl/evctrl.rs | 113 + pac/atsamc20e/src/oscctrl/intenclr.rs | 395 + pac/atsamc20e/src/oscctrl/intenset.rs | 395 + pac/atsamc20e/src/oscctrl/intflag.rs | 395 + pac/atsamc20e/src/oscctrl/osc48mctrl.rs | 207 + pac/atsamc20e/src/oscctrl/osc48mdiv.rs | 334 + pac/atsamc20e/src/oscctrl/osc48mstup.rs | 230 + pac/atsamc20e/src/oscctrl/osc48msyncbusy.rs | 53 + pac/atsamc20e/src/oscctrl/status.rs | 193 + pac/atsamc20e/src/oscctrl/xoscctrl.rs | 788 + pac/atsamc20e/src/pac.rs | 73 + pac/atsamc20e/src/pac/evctrl.rs | 113 + pac/atsamc20e/src/pac/intenclr.rs | 113 + pac/atsamc20e/src/pac/intenset.rs | 113 + pac/atsamc20e/src/pac/intflaga.rs | 630 + pac/atsamc20e/src/pac/intflagahb.rs | 442 + pac/atsamc20e/src/pac/intflagb.rs | 348 + pac/atsamc20e/src/pac/intflagc.rs | 865 + pac/atsamc20e/src/pac/statusa.rs | 273 + pac/atsamc20e/src/pac/statusb.rs | 153 + pac/atsamc20e/src/pac/statusc.rs | 373 + pac/atsamc20e/src/pac/wrctrl.rs | 215 + pac/atsamc20e/src/pm.rs | 18 + pac/atsamc20e/src/pm/sleepcfg.rs | 178 + pac/atsamc20e/src/pm/stdbycfg.rs | 212 + pac/atsamc20e/src/port.rs | 41 + pac/atsamc20e/src/port/group.rs | 56 + pac/atsamc20e/src/port/group/ctrl.rs | 103 + pac/atsamc20e/src/port/group/dir.rs | 64 + pac/atsamc20e/src/port/group/dirclr.rs | 64 + pac/atsamc20e/src/port/group/dirset.rs | 64 + pac/atsamc20e/src/port/group/dirtgl.rs | 64 + pac/atsamc20e/src/port/group/evctrl.rs | 625 + pac/atsamc20e/src/port/group/in_.rs | 31 + pac/atsamc20e/src/port/group/out.rs | 64 + pac/atsamc20e/src/port/group/outclr.rs | 64 + pac/atsamc20e/src/port/group/outset.rs | 64 + pac/atsamc20e/src/port/group/outtgl.rs | 64 + pac/atsamc20e/src/port/group/pincfg.rs | 255 + pac/atsamc20e/src/port/group/pmux.rs | 141 + pac/atsamc20e/src/port/group/wrconfig.rs | 268 + pac/atsamc20e/src/rstc.rs | 10 + pac/atsamc20e/src/rstc/rcause.rs | 153 + pac/atsamc20e/src/rtc.rs | 120 + pac/atsamc20e/src/rtc/mode0.rs | 40 + pac/atsamc20e/src/rtc/mode0/comp.rs | 103 + pac/atsamc20e/src/rtc/mode0/count.rs | 103 + pac/atsamc20e/src/rtc/mode0/ctrla.rs | 569 + pac/atsamc20e/src/rtc/mode0/dbgctrl.rs | 113 + pac/atsamc20e/src/rtc/mode0/evctrl.rs | 536 + pac/atsamc20e/src/rtc/mode0/freqcorr.rs | 150 + pac/atsamc20e/src/rtc/mode0/intenclr.rs | 536 + pac/atsamc20e/src/rtc/mode0/intenset.rs | 536 + pac/atsamc20e/src/rtc/mode0/intflag.rs | 536 + pac/atsamc20e/src/rtc/mode0/syncbusy.rs | 153 + pac/atsamc20e/src/rtc/mode1.rs | 44 + pac/atsamc20e/src/rtc/mode1/comp.rs | 104 + pac/atsamc20e/src/rtc/mode1/count.rs | 103 + pac/atsamc20e/src/rtc/mode1/ctrla.rs | 522 + pac/atsamc20e/src/rtc/mode1/dbgctrl.rs | 113 + pac/atsamc20e/src/rtc/mode1/evctrl.rs | 583 + pac/atsamc20e/src/rtc/mode1/freqcorr.rs | 150 + pac/atsamc20e/src/rtc/mode1/intenclr.rs | 583 + pac/atsamc20e/src/rtc/mode1/intenset.rs | 583 + pac/atsamc20e/src/rtc/mode1/intflag.rs | 583 + pac/atsamc20e/src/rtc/mode1/per.rs | 103 + pac/atsamc20e/src/rtc/mode1/syncbusy.rs | 193 + pac/atsamc20e/src/rtc/mode2.rs | 44 + pac/atsamc20e/src/rtc/mode2/alarm.rs | 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svd/devices/include/atsamc2x.xsl diff --git a/pac/atsamc20e/CHANGELOG.md b/pac/atsamc20e/CHANGELOG.md new file mode 100644 index 000000000000..e28d85f63b31 --- /dev/null +++ b/pac/atsamc20e/CHANGELOG.md @@ -0,0 +1,6 @@ +# Unreleased + +- Initial version +--- + +Changelog tracking started at v0.0.1 diff --git a/pac/atsamc20e/Cargo.toml b/pac/atsamc20e/Cargo.toml new file mode 100644 index 000000000000..d54e399f0cd7 --- /dev/null +++ b/pac/atsamc20e/Cargo.toml @@ -0,0 +1,22 @@ +[package] +name = "atsamc20e" +description = "Peripheral access API for ATSAMC20E microcontrollers (generated using svd2rust)" +version = "0.0.1" +authors = ["Jeremy Boynes "] +keywords = ["no-std", "arm", "cortex-m"] +categories = ["embedded", "hardware-support", "no-std"] +license = "MIT OR Apache-2.0" +repository = "https://github.com/atsamd-rs/atsamd" +readme = "README.md" +edition = "2021" + +[dependencies] +cortex-m = "0.7" +vcell = "0.1" + +[dependencies.cortex-m-rt] +version = "0.7" +optional = true + +[features] +rt = ["cortex-m-rt/device"] diff --git a/pac/atsamc20e/README.md b/pac/atsamc20e/README.md new file mode 100644 index 000000000000..be5e482993f5 --- /dev/null +++ b/pac/atsamc20e/README.md @@ -0,0 +1,26 @@ +# ATSAMC20E + +A peripheral access crate for the ATSAMC20E chip from Microchip (née Atmel) for Rust Embedded projects. + +[![Build Status](https://travis-ci.org/atsamd-rs/atsamd.svg?branch=master)](https://travis-ci.org/atsamd-rs/atsamd) +[![Crates.io](https://img.shields.io/crates/v/atsamc20e.svg)](https://crates.io/crates/atsamc20e) + +## [Documentation](https://docs.rs/atsamc20e) + +This source was automatically generated using `svd2rust`, split into smaller pieces using `form` and formatted via `rustfmt`. + +## License + +Licensed under either of: + +- Apache License, Version 2.0 ([LICENSE-APACHE](https://github.com/atsamd-rs/atsamd/blob/master/LICENSE-APACHE) or + http://www.apache.org/licenses/LICENSE-2.0) +- MIT license ([LICENSE-MIT](https://github.com/atsamd-rs/atsamd/blob/master/LICENSE-MIT) or http://opensource.org/licenses/MIT) + +at your option. + +### Contribution + +Unless you explicitly state otherwise, any contribution intentionally submitted +for inclusion in the work by you, as defined in the Apache-2.0 license, shall +be dual licensed as above, without any additional terms or conditions. diff --git a/pac/atsamc20e/build.rs b/pac/atsamc20e/build.rs new file mode 100644 index 000000000000..597923f50892 --- /dev/null +++ b/pac/atsamc20e/build.rs @@ -0,0 +1,16 @@ +use std::env; +use std::fs::File; +use std::io::Write; +use std::path::PathBuf; +fn main() { + if env::var_os("CARGO_FEATURE_RT").is_some() { + let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap()); + File::create(out.join("device.x")) + .unwrap() + .write_all(include_bytes!("device.x")) + .unwrap(); + println!("cargo:rustc-link-search={}", out.display()); + println!("cargo:rerun-if-changed=device.x"); + } + println!("cargo:rerun-if-changed=build.rs"); +} diff --git a/pac/atsamc20e/device.x b/pac/atsamc20e/device.x new file mode 100644 index 000000000000..c9ef51bf7250 --- /dev/null +++ b/pac/atsamc20e/device.x @@ -0,0 +1,23 @@ +PROVIDE(WDT = DefaultHandler); +PROVIDE(RTC = DefaultHandler); +PROVIDE(EIC = DefaultHandler); +PROVIDE(FREQM = DefaultHandler); +PROVIDE(NVMCTRL = DefaultHandler); +PROVIDE(DMAC = DefaultHandler); +PROVIDE(EVSYS = DefaultHandler); +PROVIDE(SERCOM0 = DefaultHandler); +PROVIDE(SERCOM1 = DefaultHandler); +PROVIDE(SERCOM2 = DefaultHandler); +PROVIDE(SERCOM3 = DefaultHandler); +PROVIDE(TCC0 = DefaultHandler); +PROVIDE(TCC1 = DefaultHandler); +PROVIDE(TCC2 = DefaultHandler); +PROVIDE(TC0 = DefaultHandler); +PROVIDE(TC1 = DefaultHandler); +PROVIDE(TC2 = DefaultHandler); +PROVIDE(TC3 = DefaultHandler); +PROVIDE(TC4 = DefaultHandler); +PROVIDE(ADC0 = DefaultHandler); +PROVIDE(AC = DefaultHandler); +PROVIDE(PTC = DefaultHandler); + diff --git a/pac/atsamc20e/src/ac.rs b/pac/atsamc20e/src/ac.rs new file mode 100644 index 000000000000..b66620475572 --- /dev/null +++ b/pac/atsamc20e/src/ac.rs @@ -0,0 +1,83 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + #[doc = "0x01 - Control B"] + pub ctrlb: crate::Reg, + #[doc = "0x02 - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x04 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x05 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x06 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x07 - Status A"] + pub statusa: crate::Reg, + #[doc = "0x08 - Status B"] + pub statusb: crate::Reg, + #[doc = "0x09 - Debug Control"] + pub dbgctrl: crate::Reg, + #[doc = "0x0a - Window Control"] + pub winctrl: crate::Reg, + _reserved10: [u8; 0x01], + #[doc = "0x0c - Scaler n"] + pub scaler: [crate::Reg; 4], + #[doc = "0x10..0x20 - Comparator Control n"] + pub compctrl: [crate::Reg; 4], + #[doc = "0x20 - Synchronization Busy"] + pub syncbusy: crate::Reg, +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "Control B"] +pub mod ctrlb; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUSA register accessor: an alias for `Reg`"] +pub type STATUSA = crate::Reg; +#[doc = "Status A"] +pub mod statusa; +#[doc = "STATUSB register accessor: an alias for `Reg`"] +pub type STATUSB = crate::Reg; +#[doc = "Status B"] +pub mod statusb; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "WINCTRL register accessor: an alias for `Reg`"] +pub type WINCTRL = crate::Reg; +#[doc = "Window Control"] +pub mod winctrl; +#[doc = "SCALER register accessor: an alias for `Reg`"] +pub type SCALER = crate::Reg; +#[doc = "Scaler n"] +pub mod scaler; +#[doc = "COMPCTRL register accessor: an alias for `Reg`"] +pub type COMPCTRL = crate::Reg; +#[doc = "Comparator Control n"] +pub mod compctrl; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Busy"] +pub mod syncbusy; diff --git a/pac/atsamc20e/src/ac/compctrl.rs b/pac/atsamc20e/src/ac/compctrl.rs new file mode 100644 index 000000000000..c52cb53fe56f --- /dev/null +++ b/pac/atsamc20e/src/ac/compctrl.rs @@ -0,0 +1,974 @@ +#[doc = "Register `COMPCTRL[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COMPCTRL[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SINGLE` reader - Single-Shot Mode"] +pub struct SINGLE_R(crate::FieldReader); +impl SINGLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SINGLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SINGLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SINGLE` writer - Single-Shot Mode"] +pub struct SINGLE_W<'a> { + w: &'a mut W, +} +impl<'a> SINGLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Interrupt Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum INTSEL_A { + #[doc = "0: Interrupt on comparator output toggle"] + TOGGLE = 0, + #[doc = "1: Interrupt on comparator output rising"] + RISING = 1, + #[doc = "2: Interrupt on comparator output falling"] + FALLING = 2, + #[doc = "3: Interrupt on end of comparison (single-shot mode only)"] + EOC = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: INTSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `INTSEL` reader - Interrupt Selection"] +pub struct INTSEL_R(crate::FieldReader); +impl INTSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + INTSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INTSEL_A { + match self.bits { + 0 => INTSEL_A::TOGGLE, + 1 => INTSEL_A::RISING, + 2 => INTSEL_A::FALLING, + 3 => INTSEL_A::EOC, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `TOGGLE`"] + #[inline(always)] + pub fn is_toggle(&self) -> bool { + **self == INTSEL_A::TOGGLE + } + #[doc = "Checks if the value of the field is `RISING`"] + #[inline(always)] + pub fn is_rising(&self) -> bool { + **self == INTSEL_A::RISING + } + #[doc = "Checks if the value of the field is `FALLING`"] + #[inline(always)] + pub fn is_falling(&self) -> bool { + **self == INTSEL_A::FALLING + } + #[doc = "Checks if the value of the field is `EOC`"] + #[inline(always)] + pub fn is_eoc(&self) -> bool { + **self == INTSEL_A::EOC + } +} +impl core::ops::Deref for INTSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INTSEL` writer - Interrupt Selection"] +pub struct INTSEL_W<'a> { + w: &'a mut W, +} +impl<'a> INTSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: INTSEL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Interrupt on comparator output toggle"] + #[inline(always)] + pub fn toggle(self) -> &'a mut W { + self.variant(INTSEL_A::TOGGLE) + } + #[doc = "Interrupt on comparator output rising"] + #[inline(always)] + pub fn rising(self) -> &'a mut W { + self.variant(INTSEL_A::RISING) + } + #[doc = "Interrupt on comparator output falling"] + #[inline(always)] + pub fn falling(self) -> &'a mut W { + self.variant(INTSEL_A::FALLING) + } + #[doc = "Interrupt on end of comparison (single-shot mode only)"] + #[inline(always)] + pub fn eoc(self) -> &'a mut W { + self.variant(INTSEL_A::EOC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 3)) | ((value as u32 & 0x03) << 3); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Negative Input Mux Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MUXNEG_A { + #[doc = "0: I/O pin 0"] + PIN0 = 0, + #[doc = "1: I/O pin 1"] + PIN1 = 1, + #[doc = "2: I/O pin 2"] + PIN2 = 2, + #[doc = "3: I/O pin 3"] + PIN3 = 3, + #[doc = "4: Ground"] + GND = 4, + #[doc = "5: VDD scaler"] + VSCALE = 5, + #[doc = "6: Internal bandgap voltage"] + BANDGAP = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MUXNEG_A) -> Self { + variant as _ + } +} +#[doc = "Field `MUXNEG` reader - Negative Input Mux Selection"] +pub struct MUXNEG_R(crate::FieldReader); +impl MUXNEG_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MUXNEG_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MUXNEG_A::PIN0), + 1 => Some(MUXNEG_A::PIN1), + 2 => Some(MUXNEG_A::PIN2), + 3 => Some(MUXNEG_A::PIN3), + 4 => Some(MUXNEG_A::GND), + 5 => Some(MUXNEG_A::VSCALE), + 6 => Some(MUXNEG_A::BANDGAP), + _ => None, + } + } + #[doc = "Checks if the value of the field is `PIN0`"] + #[inline(always)] + pub fn is_pin0(&self) -> bool { + **self == MUXNEG_A::PIN0 + } + #[doc = "Checks if the value of the field is `PIN1`"] + #[inline(always)] + pub fn is_pin1(&self) -> bool { + **self == MUXNEG_A::PIN1 + } + #[doc = "Checks if the value of the field is `PIN2`"] + #[inline(always)] + pub fn is_pin2(&self) -> bool { + **self == MUXNEG_A::PIN2 + } + #[doc = "Checks if the value of the field is `PIN3`"] + #[inline(always)] + pub fn is_pin3(&self) -> bool { + **self == MUXNEG_A::PIN3 + } + #[doc = "Checks if the value of the field is `GND`"] + #[inline(always)] + pub fn is_gnd(&self) -> bool { + **self == MUXNEG_A::GND + } + #[doc = "Checks if the value of the field is `VSCALE`"] + #[inline(always)] + pub fn is_vscale(&self) -> bool { + **self == MUXNEG_A::VSCALE + } + #[doc = "Checks if the value of the field is `BANDGAP`"] + #[inline(always)] + pub fn is_bandgap(&self) -> bool { + **self == MUXNEG_A::BANDGAP + } +} +impl core::ops::Deref for MUXNEG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MUXNEG` writer - Negative Input Mux Selection"] +pub struct MUXNEG_W<'a> { + w: &'a mut W, +} +impl<'a> MUXNEG_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MUXNEG_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "I/O pin 0"] + #[inline(always)] + pub fn pin0(self) -> &'a mut W { + self.variant(MUXNEG_A::PIN0) + } + #[doc = "I/O pin 1"] + #[inline(always)] + pub fn pin1(self) -> &'a mut W { + self.variant(MUXNEG_A::PIN1) + } + #[doc = "I/O pin 2"] + #[inline(always)] + pub fn pin2(self) -> &'a mut W { + self.variant(MUXNEG_A::PIN2) + } + #[doc = "I/O pin 3"] + #[inline(always)] + pub fn pin3(self) -> &'a mut W { + self.variant(MUXNEG_A::PIN3) + } + #[doc = "Ground"] + #[inline(always)] + pub fn gnd(self) -> &'a mut W { + self.variant(MUXNEG_A::GND) + } + #[doc = "VDD scaler"] + #[inline(always)] + pub fn vscale(self) -> &'a mut W { + self.variant(MUXNEG_A::VSCALE) + } + #[doc = "Internal bandgap voltage"] + #[inline(always)] + pub fn bandgap(self) -> &'a mut W { + self.variant(MUXNEG_A::BANDGAP) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +#[doc = "Positive Input Mux Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MUXPOS_A { + #[doc = "0: I/O pin 0"] + PIN0 = 0, + #[doc = "1: I/O pin 1"] + PIN1 = 1, + #[doc = "2: I/O pin 2"] + PIN2 = 2, + #[doc = "3: I/O pin 3"] + PIN3 = 3, + #[doc = "4: VDD Scaler"] + VSCALE = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MUXPOS_A) -> Self { + variant as _ + } +} +#[doc = "Field `MUXPOS` reader - Positive Input Mux Selection"] +pub struct MUXPOS_R(crate::FieldReader); +impl MUXPOS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MUXPOS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MUXPOS_A::PIN0), + 1 => Some(MUXPOS_A::PIN1), + 2 => Some(MUXPOS_A::PIN2), + 3 => Some(MUXPOS_A::PIN3), + 4 => Some(MUXPOS_A::VSCALE), + _ => None, + } + } + #[doc = "Checks if the value of the field is `PIN0`"] + #[inline(always)] + pub fn is_pin0(&self) -> bool { + **self == MUXPOS_A::PIN0 + } + #[doc = "Checks if the value of the field is `PIN1`"] + #[inline(always)] + pub fn is_pin1(&self) -> bool { + **self == MUXPOS_A::PIN1 + } + #[doc = "Checks if the value of the field is `PIN2`"] + #[inline(always)] + pub fn is_pin2(&self) -> bool { + **self == MUXPOS_A::PIN2 + } + #[doc = "Checks if the value of the field is `PIN3`"] + #[inline(always)] + pub fn is_pin3(&self) -> bool { + **self == MUXPOS_A::PIN3 + } + #[doc = "Checks if the value of the field is `VSCALE`"] + #[inline(always)] + pub fn is_vscale(&self) -> bool { + **self == MUXPOS_A::VSCALE + } +} +impl core::ops::Deref for MUXPOS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MUXPOS` writer - Positive Input Mux Selection"] +pub struct MUXPOS_W<'a> { + w: &'a mut W, +} +impl<'a> MUXPOS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MUXPOS_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "I/O pin 0"] + #[inline(always)] + pub fn pin0(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN0) + } + #[doc = "I/O pin 1"] + #[inline(always)] + pub fn pin1(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN1) + } + #[doc = "I/O pin 2"] + #[inline(always)] + pub fn pin2(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN2) + } + #[doc = "I/O pin 3"] + #[inline(always)] + pub fn pin3(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN3) + } + #[doc = "VDD Scaler"] + #[inline(always)] + pub fn vscale(self) -> &'a mut W { + self.variant(MUXPOS_A::VSCALE) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 12)) | ((value as u32 & 0x07) << 12); + self.w + } +} +#[doc = "Field `SWAP` reader - Swap Inputs and Invert"] +pub struct SWAP_R(crate::FieldReader); +impl SWAP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWAP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWAP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWAP` writer - Swap Inputs and Invert"] +pub struct SWAP_W<'a> { + w: &'a mut W, +} +impl<'a> SWAP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Speed Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SPEED_A { + #[doc = "0: Low speed"] + LOW = 0, + #[doc = "3: High speed"] + HIGH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SPEED_A) -> Self { + variant as _ + } +} +#[doc = "Field `SPEED` reader - Speed Selection"] +pub struct SPEED_R(crate::FieldReader); +impl SPEED_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SPEED_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SPEED_A::LOW), + 3 => Some(SPEED_A::HIGH), + _ => None, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SPEED_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SPEED_A::HIGH + } +} +impl core::ops::Deref for SPEED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SPEED` writer - Speed Selection"] +pub struct SPEED_W<'a> { + w: &'a mut W, +} +impl<'a> SPEED_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SPEED_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Low speed"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SPEED_A::LOW) + } + #[doc = "High speed"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SPEED_A::HIGH) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Field `HYSTEN` reader - Hysteresis Enable"] +pub struct HYSTEN_R(crate::FieldReader); +impl HYSTEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HYSTEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HYSTEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HYSTEN` writer - Hysteresis Enable"] +pub struct HYSTEN_W<'a> { + w: &'a mut W, +} +impl<'a> HYSTEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Filter Length\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FLEN_A { + #[doc = "0: No filtering"] + OFF = 0, + #[doc = "1: 3-bit majority function (2 of 3)"] + MAJ3 = 1, + #[doc = "2: 5-bit majority function (3 of 5)"] + MAJ5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FLEN_A) -> Self { + variant as _ + } +} +#[doc = "Field `FLEN` reader - Filter Length"] +pub struct FLEN_R(crate::FieldReader); +impl FLEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FLEN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(FLEN_A::OFF), + 1 => Some(FLEN_A::MAJ3), + 2 => Some(FLEN_A::MAJ5), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == FLEN_A::OFF + } + #[doc = "Checks if the value of the field is `MAJ3`"] + #[inline(always)] + pub fn is_maj3(&self) -> bool { + **self == FLEN_A::MAJ3 + } + #[doc = "Checks if the value of the field is `MAJ5`"] + #[inline(always)] + pub fn is_maj5(&self) -> bool { + **self == FLEN_A::MAJ5 + } +} +impl core::ops::Deref for FLEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLEN` writer - Filter Length"] +pub struct FLEN_W<'a> { + w: &'a mut W, +} +impl<'a> FLEN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FLEN_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No filtering"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(FLEN_A::OFF) + } + #[doc = "3-bit majority function (2 of 3)"] + #[inline(always)] + pub fn maj3(self) -> &'a mut W { + self.variant(FLEN_A::MAJ3) + } + #[doc = "5-bit majority function (3 of 5)"] + #[inline(always)] + pub fn maj5(self) -> &'a mut W { + self.variant(FLEN_A::MAJ5) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 24)) | ((value as u32 & 0x07) << 24); + self.w + } +} +#[doc = "Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum OUT_A { + #[doc = "0: The output of COMPn is not routed to the COMPn I/O port"] + OFF = 0, + #[doc = "1: The asynchronous output of COMPn is routed to the COMPn I/O port"] + ASYNC = 1, + #[doc = "2: The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port"] + SYNC = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: OUT_A) -> Self { + variant as _ + } +} +#[doc = "Field `OUT` reader - Output"] +pub struct OUT_R(crate::FieldReader); +impl OUT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + OUT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(OUT_A::OFF), + 1 => Some(OUT_A::ASYNC), + 2 => Some(OUT_A::SYNC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == OUT_A::OFF + } + #[doc = "Checks if the value of the field is `ASYNC`"] + #[inline(always)] + pub fn is_async(&self) -> bool { + **self == OUT_A::ASYNC + } + #[doc = "Checks if the value of the field is `SYNC`"] + #[inline(always)] + pub fn is_sync(&self) -> bool { + **self == OUT_A::SYNC + } +} +impl core::ops::Deref for OUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OUT` writer - Output"] +pub struct OUT_W<'a> { + w: &'a mut W, +} +impl<'a> OUT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: OUT_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "The output of COMPn is not routed to the COMPn I/O port"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(OUT_A::OFF) + } + #[doc = "The asynchronous output of COMPn is routed to the COMPn I/O port"] + #[inline(always)] + pub fn async_(self) -> &'a mut W { + self.variant(OUT_A::ASYNC) + } + #[doc = "The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port"] + #[inline(always)] + pub fn sync(self) -> &'a mut W { + self.variant(OUT_A::SYNC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 28)) | ((value as u32 & 0x03) << 28); + self.w + } +} +impl R { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Single-Shot Mode"] + #[inline(always)] + pub fn single(&self) -> SINGLE_R { + SINGLE_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 3:4 - Interrupt Selection"] + #[inline(always)] + pub fn intsel(&self) -> INTSEL_R { + INTSEL_R::new(((self.bits >> 3) & 0x03) as u8) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Negative Input Mux Selection"] + #[inline(always)] + pub fn muxneg(&self) -> MUXNEG_R { + MUXNEG_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bits 12:14 - Positive Input Mux Selection"] + #[inline(always)] + pub fn muxpos(&self) -> MUXPOS_R { + MUXPOS_R::new(((self.bits >> 12) & 0x07) as u8) + } + #[doc = "Bit 15 - Swap Inputs and Invert"] + #[inline(always)] + pub fn swap(&self) -> SWAP_R { + SWAP_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:17 - Speed Selection"] + #[inline(always)] + pub fn speed(&self) -> SPEED_R { + SPEED_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bit 19 - Hysteresis Enable"] + #[inline(always)] + pub fn hysten(&self) -> HYSTEN_R { + HYSTEN_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bits 24:26 - Filter Length"] + #[inline(always)] + pub fn flen(&self) -> FLEN_R { + FLEN_R::new(((self.bits >> 24) & 0x07) as u8) + } + #[doc = "Bits 28:29 - Output"] + #[inline(always)] + pub fn out(&self) -> OUT_R { + OUT_R::new(((self.bits >> 28) & 0x03) as u8) + } +} +impl W { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - Single-Shot Mode"] + #[inline(always)] + pub fn single(&mut self) -> SINGLE_W { + SINGLE_W { w: self } + } + #[doc = "Bits 3:4 - Interrupt Selection"] + #[inline(always)] + pub fn intsel(&mut self) -> INTSEL_W { + INTSEL_W { w: self } + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bits 8:10 - Negative Input Mux Selection"] + #[inline(always)] + pub fn muxneg(&mut self) -> MUXNEG_W { + MUXNEG_W { w: self } + } + #[doc = "Bits 12:14 - Positive Input Mux Selection"] + #[inline(always)] + pub fn muxpos(&mut self) -> MUXPOS_W { + MUXPOS_W { w: self } + } + #[doc = "Bit 15 - Swap Inputs and Invert"] + #[inline(always)] + pub fn swap(&mut self) -> SWAP_W { + SWAP_W { w: self } + } + #[doc = "Bits 16:17 - Speed Selection"] + #[inline(always)] + pub fn speed(&mut self) -> SPEED_W { + SPEED_W { w: self } + } + #[doc = "Bit 19 - Hysteresis Enable"] + #[inline(always)] + pub fn hysten(&mut self) -> HYSTEN_W { + HYSTEN_W { w: self } + } + #[doc = "Bits 24:26 - Filter Length"] + #[inline(always)] + pub fn flen(&mut self) -> FLEN_W { + FLEN_W { w: self } + } + #[doc = "Bits 28:29 - Output"] + #[inline(always)] + pub fn out(&mut self) -> OUT_W { + OUT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Comparator Control n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [compctrl](index.html) module"] +pub struct COMPCTRL_SPEC; +impl crate::RegisterSpec for COMPCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [compctrl::R](R) reader structure"] +impl crate::Readable for COMPCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [compctrl::W](W) writer structure"] +impl crate::Writable for COMPCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COMPCTRL[%s] +to value 0"] +impl crate::Resettable for COMPCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/ac/ctrla.rs b/pac/atsamc20e/src/ac/ctrla.rs new file mode 100644 index 000000000000..5f2c406226f4 --- /dev/null +++ b/pac/atsamc20e/src/ac/ctrla.rs @@ -0,0 +1,160 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/ac/ctrlb.rs b/pac/atsamc20e/src/ac/ctrlb.rs new file mode 100644 index 000000000000..68aa8d2a20ba --- /dev/null +++ b/pac/atsamc20e/src/ac/ctrlb.rs @@ -0,0 +1,99 @@ +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `START0` writer - Comparator 0 Start Comparison"] +pub struct START0_W<'a> { + w: &'a mut W, +} +impl<'a> START0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `START1` writer - Comparator 1 Start Comparison"] +pub struct START1_W<'a> { + w: &'a mut W, +} +impl<'a> START1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl W { + #[doc = "Bit 0 - Comparator 0 Start Comparison"] + #[inline(always)] + pub fn start0(&mut self) -> START0_W { + START0_W { w: self } + } + #[doc = "Bit 1 - Comparator 1 Start Comparison"] + #[inline(always)] + pub fn start1(&mut self) -> START1_W { + START1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u8; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/ac/dbgctrl.rs b/pac/atsamc20e/src/ac/dbgctrl.rs new file mode 100644 index 000000000000..53636eb2b339 --- /dev/null +++ b/pac/atsamc20e/src/ac/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Debug Run"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Debug Run"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/ac/evctrl.rs b/pac/atsamc20e/src/ac/evctrl.rs new file mode 100644 index 000000000000..5e5e650d6de9 --- /dev/null +++ b/pac/atsamc20e/src/ac/evctrl.rs @@ -0,0 +1,395 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COMPEO0` reader - Comparator 0 Event Output Enable"] +pub struct COMPEO0_R(crate::FieldReader); +impl COMPEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPEO0` writer - Comparator 0 Event Output Enable"] +pub struct COMPEO0_W<'a> { + w: &'a mut W, +} +impl<'a> COMPEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `COMPEO1` reader - Comparator 1 Event Output Enable"] +pub struct COMPEO1_R(crate::FieldReader); +impl COMPEO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPEO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPEO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPEO1` writer - Comparator 1 Event Output Enable"] +pub struct COMPEO1_W<'a> { + w: &'a mut W, +} +impl<'a> COMPEO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WINEO0` reader - Window 0 Event Output Enable"] +pub struct WINEO0_R(crate::FieldReader); +impl WINEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINEO0` writer - Window 0 Event Output Enable"] +pub struct WINEO0_W<'a> { + w: &'a mut W, +} +impl<'a> WINEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `COMPEI0` reader - Comparator 0 Event Input Enable"] +pub struct COMPEI0_R(crate::FieldReader); +impl COMPEI0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPEI0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPEI0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPEI0` writer - Comparator 0 Event Input Enable"] +pub struct COMPEI0_W<'a> { + w: &'a mut W, +} +impl<'a> COMPEI0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `COMPEI1` reader - Comparator 1 Event Input Enable"] +pub struct COMPEI1_R(crate::FieldReader); +impl COMPEI1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPEI1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPEI1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPEI1` writer - Comparator 1 Event Input Enable"] +pub struct COMPEI1_W<'a> { + w: &'a mut W, +} +impl<'a> COMPEI1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `INVEI0` reader - Comparator 0 Input Event Invert Enable"] +pub struct INVEI0_R(crate::FieldReader); +impl INVEI0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEI0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEI0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEI0` writer - Comparator 0 Input Event Invert Enable"] +pub struct INVEI0_W<'a> { + w: &'a mut W, +} +impl<'a> INVEI0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u16 & 0x01) << 12); + self.w + } +} +#[doc = "Field `INVEI1` reader - Comparator 1 Input Event Invert Enable"] +pub struct INVEI1_R(crate::FieldReader); +impl INVEI1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEI1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEI1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEI1` writer - Comparator 1 Input Event Invert Enable"] +pub struct INVEI1_W<'a> { + w: &'a mut W, +} +impl<'a> INVEI1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u16 & 0x01) << 13); + self.w + } +} +impl R { + #[doc = "Bit 0 - Comparator 0 Event Output Enable"] + #[inline(always)] + pub fn compeo0(&self) -> COMPEO0_R { + COMPEO0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Comparator 1 Event Output Enable"] + #[inline(always)] + pub fn compeo1(&self) -> COMPEO1_R { + COMPEO1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - Window 0 Event Output Enable"] + #[inline(always)] + pub fn wineo0(&self) -> WINEO0_R { + WINEO0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 8 - Comparator 0 Event Input Enable"] + #[inline(always)] + pub fn compei0(&self) -> COMPEI0_R { + COMPEI0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Comparator 1 Event Input Enable"] + #[inline(always)] + pub fn compei1(&self) -> COMPEI1_R { + COMPEI1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 12 - Comparator 0 Input Event Invert Enable"] + #[inline(always)] + pub fn invei0(&self) -> INVEI0_R { + INVEI0_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Comparator 1 Input Event Invert Enable"] + #[inline(always)] + pub fn invei1(&self) -> INVEI1_R { + INVEI1_R::new(((self.bits >> 13) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Comparator 0 Event Output Enable"] + #[inline(always)] + pub fn compeo0(&mut self) -> COMPEO0_W { + COMPEO0_W { w: self } + } + #[doc = "Bit 1 - Comparator 1 Event Output Enable"] + #[inline(always)] + pub fn compeo1(&mut self) -> COMPEO1_W { + COMPEO1_W { w: self } + } + #[doc = "Bit 4 - Window 0 Event Output Enable"] + #[inline(always)] + pub fn wineo0(&mut self) -> WINEO0_W { + WINEO0_W { w: self } + } + #[doc = "Bit 8 - Comparator 0 Event Input Enable"] + #[inline(always)] + pub fn compei0(&mut self) -> COMPEI0_W { + COMPEI0_W { w: self } + } + #[doc = "Bit 9 - Comparator 1 Event Input Enable"] + #[inline(always)] + pub fn compei1(&mut self) -> COMPEI1_W { + COMPEI1_W { w: self } + } + #[doc = "Bit 12 - Comparator 0 Input Event Invert Enable"] + #[inline(always)] + pub fn invei0(&mut self) -> INVEI0_W { + INVEI0_W { w: self } + } + #[doc = "Bit 13 - Comparator 1 Input Event Invert Enable"] + #[inline(always)] + pub fn invei1(&mut self) -> INVEI1_W { + INVEI1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/ac/intenclr.rs b/pac/atsamc20e/src/ac/intenclr.rs new file mode 100644 index 000000000000..45e3320d293e --- /dev/null +++ b/pac/atsamc20e/src/ac/intenclr.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COMP0` reader - Comparator 0 Interrupt Enable"] +pub struct COMP0_R(crate::FieldReader); +impl COMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP0` writer - Comparator 0 Interrupt Enable"] +pub struct COMP0_W<'a> { + w: &'a mut W, +} +impl<'a> COMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `COMP1` reader - Comparator 1 Interrupt Enable"] +pub struct COMP1_R(crate::FieldReader); +impl COMP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP1` writer - Comparator 1 Interrupt Enable"] +pub struct COMP1_W<'a> { + w: &'a mut W, +} +impl<'a> COMP1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WIN0` reader - Window 0 Interrupt Enable"] +pub struct WIN0_R(crate::FieldReader); +impl WIN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WIN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WIN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WIN0` writer - Window 0 Interrupt Enable"] +pub struct WIN0_W<'a> { + w: &'a mut W, +} +impl<'a> WIN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +impl R { + #[doc = "Bit 0 - Comparator 0 Interrupt Enable"] + #[inline(always)] + pub fn comp0(&self) -> COMP0_R { + COMP0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Comparator 1 Interrupt Enable"] + #[inline(always)] + pub fn comp1(&self) -> COMP1_R { + COMP1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - Window 0 Interrupt Enable"] + #[inline(always)] + pub fn win0(&self) -> WIN0_R { + WIN0_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Comparator 0 Interrupt Enable"] + #[inline(always)] + pub fn comp0(&mut self) -> COMP0_W { + COMP0_W { w: self } + } + #[doc = "Bit 1 - Comparator 1 Interrupt Enable"] + #[inline(always)] + pub fn comp1(&mut self) -> COMP1_W { + COMP1_W { w: self } + } + #[doc = "Bit 4 - Window 0 Interrupt Enable"] + #[inline(always)] + pub fn win0(&mut self) -> WIN0_W { + WIN0_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/ac/intenset.rs b/pac/atsamc20e/src/ac/intenset.rs new file mode 100644 index 000000000000..5354a4d111d0 --- /dev/null +++ b/pac/atsamc20e/src/ac/intenset.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COMP0` reader - Comparator 0 Interrupt Enable"] +pub struct COMP0_R(crate::FieldReader); +impl COMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP0` writer - Comparator 0 Interrupt Enable"] +pub struct COMP0_W<'a> { + w: &'a mut W, +} +impl<'a> COMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `COMP1` reader - Comparator 1 Interrupt Enable"] +pub struct COMP1_R(crate::FieldReader); +impl COMP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP1` writer - Comparator 1 Interrupt Enable"] +pub struct COMP1_W<'a> { + w: &'a mut W, +} +impl<'a> COMP1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WIN0` reader - Window 0 Interrupt Enable"] +pub struct WIN0_R(crate::FieldReader); +impl WIN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WIN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WIN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WIN0` writer - Window 0 Interrupt Enable"] +pub struct WIN0_W<'a> { + w: &'a mut W, +} +impl<'a> WIN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +impl R { + #[doc = "Bit 0 - Comparator 0 Interrupt Enable"] + #[inline(always)] + pub fn comp0(&self) -> COMP0_R { + COMP0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Comparator 1 Interrupt Enable"] + #[inline(always)] + pub fn comp1(&self) -> COMP1_R { + COMP1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - Window 0 Interrupt Enable"] + #[inline(always)] + pub fn win0(&self) -> WIN0_R { + WIN0_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Comparator 0 Interrupt Enable"] + #[inline(always)] + pub fn comp0(&mut self) -> COMP0_W { + COMP0_W { w: self } + } + #[doc = "Bit 1 - Comparator 1 Interrupt Enable"] + #[inline(always)] + pub fn comp1(&mut self) -> COMP1_W { + COMP1_W { w: self } + } + #[doc = "Bit 4 - Window 0 Interrupt Enable"] + #[inline(always)] + pub fn win0(&mut self) -> WIN0_W { + WIN0_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/ac/intflag.rs b/pac/atsamc20e/src/ac/intflag.rs new file mode 100644 index 000000000000..7da0fea7569f --- /dev/null +++ b/pac/atsamc20e/src/ac/intflag.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COMP0` reader - Comparator 0"] +pub struct COMP0_R(crate::FieldReader); +impl COMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP0` writer - Comparator 0"] +pub struct COMP0_W<'a> { + w: &'a mut W, +} +impl<'a> COMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `COMP1` reader - Comparator 1"] +pub struct COMP1_R(crate::FieldReader); +impl COMP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP1` writer - Comparator 1"] +pub struct COMP1_W<'a> { + w: &'a mut W, +} +impl<'a> COMP1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WIN0` reader - Window 0"] +pub struct WIN0_R(crate::FieldReader); +impl WIN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WIN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WIN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WIN0` writer - Window 0"] +pub struct WIN0_W<'a> { + w: &'a mut W, +} +impl<'a> WIN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +impl R { + #[doc = "Bit 0 - Comparator 0"] + #[inline(always)] + pub fn comp0(&self) -> COMP0_R { + COMP0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Comparator 1"] + #[inline(always)] + pub fn comp1(&self) -> COMP1_R { + COMP1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - Window 0"] + #[inline(always)] + pub fn win0(&self) -> WIN0_R { + WIN0_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Comparator 0"] + #[inline(always)] + pub fn comp0(&mut self) -> COMP0_W { + COMP0_W { w: self } + } + #[doc = "Bit 1 - Comparator 1"] + #[inline(always)] + pub fn comp1(&mut self) -> COMP1_W { + COMP1_W { w: self } + } + #[doc = "Bit 4 - Window 0"] + #[inline(always)] + pub fn win0(&mut self) -> WIN0_W { + WIN0_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/ac/scaler.rs b/pac/atsamc20e/src/ac/scaler.rs new file mode 100644 index 000000000000..091cacfaeb4b --- /dev/null +++ b/pac/atsamc20e/src/ac/scaler.rs @@ -0,0 +1,104 @@ +#[doc = "Register `SCALER[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SCALER[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `VALUE` reader - Scaler Value"] +pub struct VALUE_R(crate::FieldReader); +impl VALUE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + VALUE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VALUE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VALUE` writer - Scaler Value"] +pub struct VALUE_W<'a> { + w: &'a mut W, +} +impl<'a> VALUE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u8 & 0x3f); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Scaler Value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - Scaler Value"] + #[inline(always)] + pub fn value(&mut self) -> VALUE_W { + VALUE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Scaler n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [scaler](index.html) module"] +pub struct SCALER_SPEC; +impl crate::RegisterSpec for SCALER_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [scaler::R](R) reader structure"] +impl crate::Readable for SCALER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [scaler::W](W) writer structure"] +impl crate::Writable for SCALER_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SCALER[%s] +to value 0"] +impl crate::Resettable for SCALER_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/ac/statusa.rs b/pac/atsamc20e/src/ac/statusa.rs new file mode 100644 index 000000000000..7b98c567e8a6 --- /dev/null +++ b/pac/atsamc20e/src/ac/statusa.rs @@ -0,0 +1,135 @@ +#[doc = "Register `STATUSA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `STATE0` reader - Comparator 0 Current State"] +pub struct STATE0_R(crate::FieldReader); +impl STATE0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STATE0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STATE0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STATE1` reader - Comparator 1 Current State"] +pub struct STATE1_R(crate::FieldReader); +impl STATE1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STATE1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STATE1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Window 0 Current State\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WSTATE0_A { + #[doc = "0: Signal is above window"] + ABOVE = 0, + #[doc = "1: Signal is inside window"] + INSIDE = 1, + #[doc = "2: Signal is below window"] + BELOW = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WSTATE0_A) -> Self { + variant as _ + } +} +#[doc = "Field `WSTATE0` reader - Window 0 Current State"] +pub struct WSTATE0_R(crate::FieldReader); +impl WSTATE0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WSTATE0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(WSTATE0_A::ABOVE), + 1 => Some(WSTATE0_A::INSIDE), + 2 => Some(WSTATE0_A::BELOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `ABOVE`"] + #[inline(always)] + pub fn is_above(&self) -> bool { + **self == WSTATE0_A::ABOVE + } + #[doc = "Checks if the value of the field is `INSIDE`"] + #[inline(always)] + pub fn is_inside(&self) -> bool { + **self == WSTATE0_A::INSIDE + } + #[doc = "Checks if the value of the field is `BELOW`"] + #[inline(always)] + pub fn is_below(&self) -> bool { + **self == WSTATE0_A::BELOW + } +} +impl core::ops::Deref for WSTATE0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Comparator 0 Current State"] + #[inline(always)] + pub fn state0(&self) -> STATE0_R { + STATE0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Comparator 1 Current State"] + #[inline(always)] + pub fn state1(&self) -> STATE1_R { + STATE1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 4:5 - Window 0 Current State"] + #[inline(always)] + pub fn wstate0(&self) -> WSTATE0_R { + WSTATE0_R::new(((self.bits >> 4) & 0x03) as u8) + } +} +#[doc = "Status A\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [statusa](index.html) module"] +pub struct STATUSA_SPEC; +impl crate::RegisterSpec for STATUSA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [statusa::R](R) reader structure"] +impl crate::Readable for STATUSA_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUSA to value 0"] +impl crate::Resettable for STATUSA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/ac/statusb.rs b/pac/atsamc20e/src/ac/statusb.rs new file mode 100644 index 000000000000..dd27eb62fd27 --- /dev/null +++ b/pac/atsamc20e/src/ac/statusb.rs @@ -0,0 +1,73 @@ +#[doc = "Register `STATUSB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `READY0` reader - Comparator 0 Ready"] +pub struct READY0_R(crate::FieldReader); +impl READY0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + READY0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for READY0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `READY1` reader - Comparator 1 Ready"] +pub struct READY1_R(crate::FieldReader); +impl READY1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + READY1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for READY1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Comparator 0 Ready"] + #[inline(always)] + pub fn ready0(&self) -> READY0_R { + READY0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Comparator 1 Ready"] + #[inline(always)] + pub fn ready1(&self) -> READY1_R { + READY1_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +#[doc = "Status B\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [statusb](index.html) module"] +pub struct STATUSB_SPEC; +impl crate::RegisterSpec for STATUSB_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [statusb::R](R) reader structure"] +impl crate::Readable for STATUSB_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUSB to value 0"] +impl crate::Resettable for STATUSB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/ac/syncbusy.rs b/pac/atsamc20e/src/ac/syncbusy.rs new file mode 100644 index 000000000000..f3f2b1f4f1a6 --- /dev/null +++ b/pac/atsamc20e/src/ac/syncbusy.rs @@ -0,0 +1,133 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - Enable Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINCTRL` reader - WINCTRL Synchronization Busy"] +pub struct WINCTRL_R(crate::FieldReader); +impl WINCTRL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINCTRL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINCTRL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPCTRL0` reader - COMPCTRL 0 Synchronization Busy"] +pub struct COMPCTRL0_R(crate::FieldReader); +impl COMPCTRL0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPCTRL0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPCTRL0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPCTRL1` reader - COMPCTRL 1 Synchronization Busy"] +pub struct COMPCTRL1_R(crate::FieldReader); +impl COMPCTRL1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPCTRL1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPCTRL1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - WINCTRL Synchronization Busy"] + #[inline(always)] + pub fn winctrl(&self) -> WINCTRL_R { + WINCTRL_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - COMPCTRL 0 Synchronization Busy"] + #[inline(always)] + pub fn compctrl0(&self) -> COMPCTRL0_R { + COMPCTRL0_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - COMPCTRL 1 Synchronization Busy"] + #[inline(always)] + pub fn compctrl1(&self) -> COMPCTRL1_R { + COMPCTRL1_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +#[doc = "Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/ac/winctrl.rs b/pac/atsamc20e/src/ac/winctrl.rs new file mode 100644 index 000000000000..3259570489e0 --- /dev/null +++ b/pac/atsamc20e/src/ac/winctrl.rs @@ -0,0 +1,225 @@ +#[doc = "Register `WINCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WINCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WEN0` reader - Window 0 Mode Enable"] +pub struct WEN0_R(crate::FieldReader); +impl WEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WEN0` writer - Window 0 Mode Enable"] +pub struct WEN0_W<'a> { + w: &'a mut W, +} +impl<'a> WEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Window 0 Interrupt Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WINTSEL0_A { + #[doc = "0: Interrupt on signal above window"] + ABOVE = 0, + #[doc = "1: Interrupt on signal inside window"] + INSIDE = 1, + #[doc = "2: Interrupt on signal below window"] + BELOW = 2, + #[doc = "3: Interrupt on signal outside window"] + OUTSIDE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WINTSEL0_A) -> Self { + variant as _ + } +} +#[doc = "Field `WINTSEL0` reader - Window 0 Interrupt Selection"] +pub struct WINTSEL0_R(crate::FieldReader); +impl WINTSEL0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WINTSEL0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> WINTSEL0_A { + match self.bits { + 0 => WINTSEL0_A::ABOVE, + 1 => WINTSEL0_A::INSIDE, + 2 => WINTSEL0_A::BELOW, + 3 => WINTSEL0_A::OUTSIDE, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `ABOVE`"] + #[inline(always)] + pub fn is_above(&self) -> bool { + **self == WINTSEL0_A::ABOVE + } + #[doc = "Checks if the value of the field is `INSIDE`"] + #[inline(always)] + pub fn is_inside(&self) -> bool { + **self == WINTSEL0_A::INSIDE + } + #[doc = "Checks if the value of the field is `BELOW`"] + #[inline(always)] + pub fn is_below(&self) -> bool { + **self == WINTSEL0_A::BELOW + } + #[doc = "Checks if the value of the field is `OUTSIDE`"] + #[inline(always)] + pub fn is_outside(&self) -> bool { + **self == WINTSEL0_A::OUTSIDE + } +} +impl core::ops::Deref for WINTSEL0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINTSEL0` writer - Window 0 Interrupt Selection"] +pub struct WINTSEL0_W<'a> { + w: &'a mut W, +} +impl<'a> WINTSEL0_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WINTSEL0_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Interrupt on signal above window"] + #[inline(always)] + pub fn above(self) -> &'a mut W { + self.variant(WINTSEL0_A::ABOVE) + } + #[doc = "Interrupt on signal inside window"] + #[inline(always)] + pub fn inside(self) -> &'a mut W { + self.variant(WINTSEL0_A::INSIDE) + } + #[doc = "Interrupt on signal below window"] + #[inline(always)] + pub fn below(self) -> &'a mut W { + self.variant(WINTSEL0_A::BELOW) + } + #[doc = "Interrupt on signal outside window"] + #[inline(always)] + pub fn outside(self) -> &'a mut W { + self.variant(WINTSEL0_A::OUTSIDE) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 1)) | ((value as u8 & 0x03) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - Window 0 Mode Enable"] + #[inline(always)] + pub fn wen0(&self) -> WEN0_R { + WEN0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bits 1:2 - Window 0 Interrupt Selection"] + #[inline(always)] + pub fn wintsel0(&self) -> WINTSEL0_R { + WINTSEL0_R::new(((self.bits >> 1) & 0x03) as u8) + } +} +impl W { + #[doc = "Bit 0 - Window 0 Mode Enable"] + #[inline(always)] + pub fn wen0(&mut self) -> WEN0_W { + WEN0_W { w: self } + } + #[doc = "Bits 1:2 - Window 0 Interrupt Selection"] + #[inline(always)] + pub fn wintsel0(&mut self) -> WINTSEL0_W { + WINTSEL0_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Window Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [winctrl](index.html) module"] +pub struct WINCTRL_SPEC; +impl crate::RegisterSpec for WINCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [winctrl::R](R) reader structure"] +impl crate::Readable for WINCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [winctrl::W](W) writer structure"] +impl crate::Writable for WINCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WINCTRL to value 0"] +impl crate::Resettable for WINCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/adc0.rs b/pac/atsamc20e/src/adc0.rs new file mode 100644 index 000000000000..453f56ed28c8 --- /dev/null +++ b/pac/atsamc20e/src/adc0.rs @@ -0,0 +1,141 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + #[doc = "0x01 - Control B"] + pub ctrlb: crate::Reg, + #[doc = "0x02 - Reference Control"] + pub refctrl: crate::Reg, + #[doc = "0x03 - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x04 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x05 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x06 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x07 - Sequence Status"] + pub seqstatus: crate::Reg, + #[doc = "0x08 - Input Control"] + pub inputctrl: crate::Reg, + #[doc = "0x0a - Control C"] + pub ctrlc: crate::Reg, + #[doc = "0x0c - Average Control"] + pub avgctrl: crate::Reg, + #[doc = "0x0d - Sample Time Control"] + pub sampctrl: crate::Reg, + #[doc = "0x0e - Window Monitor Lower Threshold"] + pub winlt: crate::Reg, + #[doc = "0x10 - Window Monitor Upper Threshold"] + pub winut: crate::Reg, + #[doc = "0x12 - Gain Correction"] + pub gaincorr: crate::Reg, + #[doc = "0x14 - Offset Correction"] + pub offsetcorr: crate::Reg, + _reserved16: [u8; 0x02], + #[doc = "0x18 - Software Trigger"] + pub swtrig: crate::Reg, + _reserved17: [u8; 0x03], + #[doc = "0x1c - Debug Control"] + pub dbgctrl: crate::Reg, + _reserved18: [u8; 0x03], + #[doc = "0x20 - Synchronization Busy"] + pub syncbusy: crate::Reg, + _reserved19: [u8; 0x02], + #[doc = "0x24 - Result"] + pub result: crate::Reg, + _reserved20: [u8; 0x02], + #[doc = "0x28 - Sequence Control"] + pub seqctrl: crate::Reg, + #[doc = "0x2c - Calibration"] + pub calib: crate::Reg, +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "Control B"] +pub mod ctrlb; +#[doc = "REFCTRL register accessor: an alias for `Reg`"] +pub type REFCTRL = crate::Reg; +#[doc = "Reference Control"] +pub mod refctrl; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "SEQSTATUS register accessor: an alias for `Reg`"] +pub type SEQSTATUS = crate::Reg; +#[doc = "Sequence Status"] +pub mod seqstatus; +#[doc = "INPUTCTRL register accessor: an alias for `Reg`"] +pub type INPUTCTRL = crate::Reg; +#[doc = "Input Control"] +pub mod inputctrl; +#[doc = "CTRLC register accessor: an alias for `Reg`"] +pub type CTRLC = crate::Reg; +#[doc = "Control C"] +pub mod ctrlc; +#[doc = "AVGCTRL register accessor: an alias for `Reg`"] +pub type AVGCTRL = crate::Reg; +#[doc = "Average Control"] +pub mod avgctrl; +#[doc = "SAMPCTRL register accessor: an alias for `Reg`"] +pub type SAMPCTRL = crate::Reg; +#[doc = "Sample Time Control"] +pub mod sampctrl; +#[doc = "WINLT register accessor: an alias for `Reg`"] +pub type WINLT = crate::Reg; +#[doc = "Window Monitor Lower Threshold"] +pub mod winlt; +#[doc = "WINUT register accessor: an alias for `Reg`"] +pub type WINUT = crate::Reg; +#[doc = "Window Monitor Upper Threshold"] +pub mod winut; +#[doc = "GAINCORR register accessor: an alias for `Reg`"] +pub type GAINCORR = crate::Reg; +#[doc = "Gain Correction"] +pub mod gaincorr; +#[doc = "OFFSETCORR register accessor: an alias for `Reg`"] +pub type OFFSETCORR = crate::Reg; +#[doc = "Offset Correction"] +pub mod offsetcorr; +#[doc = "SWTRIG register accessor: an alias for `Reg`"] +pub type SWTRIG = crate::Reg; +#[doc = "Software Trigger"] +pub mod swtrig; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Busy"] +pub mod syncbusy; +#[doc = "RESULT register accessor: an alias for `Reg`"] +pub type RESULT = crate::Reg; +#[doc = "Result"] +pub mod result; +#[doc = "SEQCTRL register accessor: an alias for `Reg`"] +pub type SEQCTRL = crate::Reg; +#[doc = "Sequence Control"] +pub mod seqctrl; +#[doc = "CALIB register accessor: an alias for `Reg`"] +pub type CALIB = crate::Reg; +#[doc = "Calibration"] +pub mod calib; diff --git a/pac/atsamc20e/src/adc0/avgctrl.rs b/pac/atsamc20e/src/adc0/avgctrl.rs new file mode 100644 index 000000000000..ddb735715c98 --- /dev/null +++ b/pac/atsamc20e/src/adc0/avgctrl.rs @@ -0,0 +1,306 @@ +#[doc = "Register `AVGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `AVGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Number of Samples to be Collected\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SAMPLENUM_A { + #[doc = "0: 1 sample"] + _1 = 0, + #[doc = "1: 2 samples"] + _2 = 1, + #[doc = "2: 4 samples"] + _4 = 2, + #[doc = "3: 8 samples"] + _8 = 3, + #[doc = "4: 16 samples"] + _16 = 4, + #[doc = "5: 32 samples"] + _32 = 5, + #[doc = "6: 64 samples"] + _64 = 6, + #[doc = "7: 128 samples"] + _128 = 7, + #[doc = "8: 256 samples"] + _256 = 8, + #[doc = "9: 512 samples"] + _512 = 9, + #[doc = "10: 1024 samples"] + _1024 = 10, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SAMPLENUM_A) -> Self { + variant as _ + } +} +#[doc = "Field `SAMPLENUM` reader - Number of Samples to be Collected"] +pub struct SAMPLENUM_R(crate::FieldReader); +impl SAMPLENUM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SAMPLENUM_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SAMPLENUM_A::_1), + 1 => Some(SAMPLENUM_A::_2), + 2 => Some(SAMPLENUM_A::_4), + 3 => Some(SAMPLENUM_A::_8), + 4 => Some(SAMPLENUM_A::_16), + 5 => Some(SAMPLENUM_A::_32), + 6 => Some(SAMPLENUM_A::_64), + 7 => Some(SAMPLENUM_A::_128), + 8 => Some(SAMPLENUM_A::_256), + 9 => Some(SAMPLENUM_A::_512), + 10 => Some(SAMPLENUM_A::_1024), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_1`"] + #[inline(always)] + pub fn is_1(&self) -> bool { + **self == SAMPLENUM_A::_1 + } + #[doc = "Checks if the value of the field is `_2`"] + #[inline(always)] + pub fn is_2(&self) -> bool { + **self == SAMPLENUM_A::_2 + } + #[doc = "Checks if the value of the field is `_4`"] + #[inline(always)] + pub fn is_4(&self) -> bool { + **self == SAMPLENUM_A::_4 + } + #[doc = "Checks if the value of the field is `_8`"] + #[inline(always)] + pub fn is_8(&self) -> bool { + **self == SAMPLENUM_A::_8 + } + #[doc = "Checks if the value of the field is `_16`"] + #[inline(always)] + pub fn is_16(&self) -> bool { + **self == SAMPLENUM_A::_16 + } + #[doc = "Checks if the value of the field is `_32`"] + #[inline(always)] + pub fn is_32(&self) -> bool { + **self == SAMPLENUM_A::_32 + } + #[doc = "Checks if the value of the field is `_64`"] + #[inline(always)] + pub fn is_64(&self) -> bool { + **self == SAMPLENUM_A::_64 + } + #[doc = "Checks if the value of the field is `_128`"] + #[inline(always)] + pub fn is_128(&self) -> bool { + **self == SAMPLENUM_A::_128 + } + #[doc = "Checks if the value of the field is `_256`"] + #[inline(always)] + pub fn is_256(&self) -> bool { + **self == SAMPLENUM_A::_256 + } + #[doc = "Checks if the value of the field is `_512`"] + #[inline(always)] + pub fn is_512(&self) -> bool { + **self == SAMPLENUM_A::_512 + } + #[doc = "Checks if the value of the field is `_1024`"] + #[inline(always)] + pub fn is_1024(&self) -> bool { + **self == SAMPLENUM_A::_1024 + } +} +impl core::ops::Deref for SAMPLENUM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SAMPLENUM` writer - Number of Samples to be Collected"] +pub struct SAMPLENUM_W<'a> { + w: &'a mut W, +} +impl<'a> SAMPLENUM_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SAMPLENUM_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "1 sample"] + #[inline(always)] + pub fn _1(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_1) + } + #[doc = "2 samples"] + #[inline(always)] + pub fn _2(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_2) + } + #[doc = "4 samples"] + #[inline(always)] + pub fn _4(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_4) + } + #[doc = "8 samples"] + #[inline(always)] + pub fn _8(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_8) + } + #[doc = "16 samples"] + #[inline(always)] + pub fn _16(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_16) + } + #[doc = "32 samples"] + #[inline(always)] + pub fn _32(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_32) + } + #[doc = "64 samples"] + #[inline(always)] + pub fn _64(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_64) + } + #[doc = "128 samples"] + #[inline(always)] + pub fn _128(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_128) + } + #[doc = "256 samples"] + #[inline(always)] + pub fn _256(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_256) + } + #[doc = "512 samples"] + #[inline(always)] + pub fn _512(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_512) + } + #[doc = "1024 samples"] + #[inline(always)] + pub fn _1024(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +#[doc = "Field `ADJRES` reader - Adjusting Result / Division Coefficient"] +pub struct ADJRES_R(crate::FieldReader); +impl ADJRES_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ADJRES_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADJRES_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADJRES` writer - Adjusting Result / Division Coefficient"] +pub struct ADJRES_W<'a> { + w: &'a mut W, +} +impl<'a> ADJRES_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 4)) | ((value as u8 & 0x07) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Number of Samples to be Collected"] + #[inline(always)] + pub fn samplenum(&self) -> SAMPLENUM_R { + SAMPLENUM_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:6 - Adjusting Result / Division Coefficient"] + #[inline(always)] + pub fn adjres(&self) -> ADJRES_R { + ADJRES_R::new(((self.bits >> 4) & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Number of Samples to be Collected"] + #[inline(always)] + pub fn samplenum(&mut self) -> SAMPLENUM_W { + SAMPLENUM_W { w: self } + } + #[doc = "Bits 4:6 - Adjusting Result / Division Coefficient"] + #[inline(always)] + pub fn adjres(&mut self) -> ADJRES_W { + ADJRES_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Average Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [avgctrl](index.html) module"] +pub struct AVGCTRL_SPEC; +impl crate::RegisterSpec for AVGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [avgctrl::R](R) reader structure"] +impl crate::Readable for AVGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [avgctrl::W](W) writer structure"] +impl crate::Writable for AVGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets AVGCTRL to value 0"] +impl crate::Resettable for AVGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/adc0/calib.rs b/pac/atsamc20e/src/adc0/calib.rs new file mode 100644 index 000000000000..8a1a99b8c47d --- /dev/null +++ b/pac/atsamc20e/src/adc0/calib.rs @@ -0,0 +1,140 @@ +#[doc = "Register `CALIB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CALIB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BIASCOMP` reader - Bias Comparator Scaling"] +pub struct BIASCOMP_R(crate::FieldReader); +impl BIASCOMP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BIASCOMP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BIASCOMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BIASCOMP` writer - Bias Comparator Scaling"] +pub struct BIASCOMP_W<'a> { + w: &'a mut W, +} +impl<'a> BIASCOMP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u16 & 0x07); + self.w + } +} +#[doc = "Field `BIASREFBUF` reader - Bias Reference Buffer Scaling"] +pub struct BIASREFBUF_R(crate::FieldReader); +impl BIASREFBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BIASREFBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BIASREFBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BIASREFBUF` writer - Bias Reference Buffer Scaling"] +pub struct BIASREFBUF_W<'a> { + w: &'a mut W, +} +impl<'a> BIASREFBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u16 & 0x07) << 8); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Bias Comparator Scaling"] + #[inline(always)] + pub fn biascomp(&self) -> BIASCOMP_R { + BIASCOMP_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bits 8:10 - Bias Reference Buffer Scaling"] + #[inline(always)] + pub fn biasrefbuf(&self) -> BIASREFBUF_R { + BIASREFBUF_R::new(((self.bits >> 8) & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Bias Comparator Scaling"] + #[inline(always)] + pub fn biascomp(&mut self) -> BIASCOMP_W { + BIASCOMP_W { w: self } + } + #[doc = "Bits 8:10 - Bias Reference Buffer Scaling"] + #[inline(always)] + pub fn biasrefbuf(&mut self) -> BIASREFBUF_W { + BIASREFBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Calibration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [calib](index.html) module"] +pub struct CALIB_SPEC; +impl crate::RegisterSpec for CALIB_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [calib::R](R) reader structure"] +impl crate::Readable for CALIB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [calib::W](W) writer structure"] +impl crate::Writable for CALIB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CALIB to value 0"] +impl crate::Resettable for CALIB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/adc0/ctrla.rs b/pac/atsamc20e/src/adc0/ctrla.rs new file mode 100644 index 000000000000..47c681045f95 --- /dev/null +++ b/pac/atsamc20e/src/adc0/ctrla.rs @@ -0,0 +1,301 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SLAVEEN` reader - Slave Enable"] +pub struct SLAVEEN_R(crate::FieldReader); +impl SLAVEEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLAVEEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SLAVEEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLAVEEN` writer - Slave Enable"] +pub struct SLAVEEN_W<'a> { + w: &'a mut W, +} +impl<'a> SLAVEEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run During Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run During Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - On Demand Control"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - On Demand Control"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 5 - Slave Enable"] + #[inline(always)] + pub fn slaveen(&self) -> SLAVEEN_R { + SLAVEEN_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Run During Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 5 - Slave Enable"] + #[inline(always)] + pub fn slaveen(&mut self) -> SLAVEEN_W { + SLAVEEN_W { w: self } + } + #[doc = "Bit 6 - Run During Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/adc0/ctrlb.rs b/pac/atsamc20e/src/adc0/ctrlb.rs new file mode 100644 index 000000000000..4d39688fc975 --- /dev/null +++ b/pac/atsamc20e/src/adc0/ctrlb.rs @@ -0,0 +1,230 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Prescaler Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: Peripheral clock / 2"] + DIV2 = 0, + #[doc = "1: Peripheral clock / 4"] + DIV4 = 1, + #[doc = "2: Peripheral clock / 8"] + DIV8 = 2, + #[doc = "3: Peripheral clock / 16"] + DIV16 = 3, + #[doc = "4: Peripheral clock / 32"] + DIV32 = 4, + #[doc = "5: Peripheral clock / 64"] + DIV64 = 5, + #[doc = "6: Peripheral clock / 128"] + DIV128 = 6, + #[doc = "7: Peripheral clock / 256"] + DIV256 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler Configuration"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PRESCALER_A { + match self.bits { + 0 => PRESCALER_A::DIV2, + 1 => PRESCALER_A::DIV4, + 2 => PRESCALER_A::DIV8, + 3 => PRESCALER_A::DIV16, + 4 => PRESCALER_A::DIV32, + 5 => PRESCALER_A::DIV64, + 6 => PRESCALER_A::DIV128, + 7 => PRESCALER_A::DIV256, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == PRESCALER_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == PRESCALER_A::DIV128 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler Configuration"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Peripheral clock / 2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "Peripheral clock / 4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "Peripheral clock / 8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "Peripheral clock / 16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "Peripheral clock / 32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV32) + } + #[doc = "Peripheral clock / 64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "Peripheral clock / 128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV128) + } + #[doc = "Peripheral clock / 256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Prescaler Configuration"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Prescaler Configuration"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/adc0/ctrlc.rs b/pac/atsamc20e/src/adc0/ctrlc.rs new file mode 100644 index 000000000000..fa45a771545a --- /dev/null +++ b/pac/atsamc20e/src/adc0/ctrlc.rs @@ -0,0 +1,538 @@ +#[doc = "Register `CTRLC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIFFMODE` reader - Differential Mode"] +pub struct DIFFMODE_R(crate::FieldReader); +impl DIFFMODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIFFMODE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIFFMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIFFMODE` writer - Differential Mode"] +pub struct DIFFMODE_W<'a> { + w: &'a mut W, +} +impl<'a> DIFFMODE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `LEFTADJ` reader - Left-Adjusted Result"] +pub struct LEFTADJ_R(crate::FieldReader); +impl LEFTADJ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LEFTADJ_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LEFTADJ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LEFTADJ` writer - Left-Adjusted Result"] +pub struct LEFTADJ_W<'a> { + w: &'a mut W, +} +impl<'a> LEFTADJ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `FREERUN` reader - Free Running Mode"] +pub struct FREERUN_R(crate::FieldReader); +impl FREERUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FREERUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FREERUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FREERUN` writer - Free Running Mode"] +pub struct FREERUN_W<'a> { + w: &'a mut W, +} +impl<'a> FREERUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CORREN` reader - Digital Correction Logic Enable"] +pub struct CORREN_R(crate::FieldReader); +impl CORREN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CORREN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CORREN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CORREN` writer - Digital Correction Logic Enable"] +pub struct CORREN_W<'a> { + w: &'a mut W, +} +impl<'a> CORREN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Conversion Result Resolution\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum RESSEL_A { + #[doc = "0: 12-bit"] + _12BIT = 0, + #[doc = "1: 16-bit averaging mode"] + _16BIT = 1, + #[doc = "2: 10-bit"] + _10BIT = 2, + #[doc = "3: 8-bit"] + _8BIT = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RESSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `RESSEL` reader - Conversion Result Resolution"] +pub struct RESSEL_R(crate::FieldReader); +impl RESSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RESSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RESSEL_A { + match self.bits { + 0 => RESSEL_A::_12BIT, + 1 => RESSEL_A::_16BIT, + 2 => RESSEL_A::_10BIT, + 3 => RESSEL_A::_8BIT, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `_12BIT`"] + #[inline(always)] + pub fn is_12bit(&self) -> bool { + **self == RESSEL_A::_12BIT + } + #[doc = "Checks if the value of the field is `_16BIT`"] + #[inline(always)] + pub fn is_16bit(&self) -> bool { + **self == RESSEL_A::_16BIT + } + #[doc = "Checks if the value of the field is `_10BIT`"] + #[inline(always)] + pub fn is_10bit(&self) -> bool { + **self == RESSEL_A::_10BIT + } + #[doc = "Checks if the value of the field is `_8BIT`"] + #[inline(always)] + pub fn is_8bit(&self) -> bool { + **self == RESSEL_A::_8BIT + } +} +impl core::ops::Deref for RESSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESSEL` writer - Conversion Result Resolution"] +pub struct RESSEL_W<'a> { + w: &'a mut W, +} +impl<'a> RESSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RESSEL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "12-bit"] + #[inline(always)] + pub fn _12bit(self) -> &'a mut W { + self.variant(RESSEL_A::_12BIT) + } + #[doc = "16-bit averaging mode"] + #[inline(always)] + pub fn _16bit(self) -> &'a mut W { + self.variant(RESSEL_A::_16BIT) + } + #[doc = "10-bit"] + #[inline(always)] + pub fn _10bit(self) -> &'a mut W { + self.variant(RESSEL_A::_10BIT) + } + #[doc = "8-bit"] + #[inline(always)] + pub fn _8bit(self) -> &'a mut W { + self.variant(RESSEL_A::_8BIT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u16 & 0x03) << 4); + self.w + } +} +#[doc = "Field `R2R` reader - Rail-to-Rail mode enable"] +pub struct R2R_R(crate::FieldReader); +impl R2R_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + R2R_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for R2R_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `R2R` writer - Rail-to-Rail mode enable"] +pub struct R2R_W<'a> { + w: &'a mut W, +} +impl<'a> R2R_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Window Monitor Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WINMODE_A { + #[doc = "0: No window mode (default)"] + DISABLE = 0, + #[doc = "1: RESULT > WINLT"] + MODE1 = 1, + #[doc = "2: RESULT < WINUT"] + MODE2 = 2, + #[doc = "3: WINLT < RESULT < WINUT"] + MODE3 = 3, + #[doc = "4: !(WINLT < RESULT < WINUT)"] + MODE4 = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WINMODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `WINMODE` reader - Window Monitor Mode"] +pub struct WINMODE_R(crate::FieldReader); +impl WINMODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WINMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(WINMODE_A::DISABLE), + 1 => Some(WINMODE_A::MODE1), + 2 => Some(WINMODE_A::MODE2), + 3 => Some(WINMODE_A::MODE3), + 4 => Some(WINMODE_A::MODE4), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == WINMODE_A::DISABLE + } + #[doc = "Checks if the value of the field is `MODE1`"] + #[inline(always)] + pub fn is_mode1(&self) -> bool { + **self == WINMODE_A::MODE1 + } + #[doc = "Checks if the value of the field is `MODE2`"] + #[inline(always)] + pub fn is_mode2(&self) -> bool { + **self == WINMODE_A::MODE2 + } + #[doc = "Checks if the value of the field is `MODE3`"] + #[inline(always)] + pub fn is_mode3(&self) -> bool { + **self == WINMODE_A::MODE3 + } + #[doc = "Checks if the value of the field is `MODE4`"] + #[inline(always)] + pub fn is_mode4(&self) -> bool { + **self == WINMODE_A::MODE4 + } +} +impl core::ops::Deref for WINMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMODE` writer - Window Monitor Mode"] +pub struct WINMODE_W<'a> { + w: &'a mut W, +} +impl<'a> WINMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WINMODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No window mode (default)"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(WINMODE_A::DISABLE) + } + #[doc = "RESULT > WINLT"] + #[inline(always)] + pub fn mode1(self) -> &'a mut W { + self.variant(WINMODE_A::MODE1) + } + #[doc = "RESULT < WINUT"] + #[inline(always)] + pub fn mode2(self) -> &'a mut W { + self.variant(WINMODE_A::MODE2) + } + #[doc = "WINLT < RESULT < WINUT"] + #[inline(always)] + pub fn mode3(self) -> &'a mut W { + self.variant(WINMODE_A::MODE3) + } + #[doc = "!(WINLT < RESULT < WINUT)"] + #[inline(always)] + pub fn mode4(self) -> &'a mut W { + self.variant(WINMODE_A::MODE4) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u16 & 0x07) << 8); + self.w + } +} +impl R { + #[doc = "Bit 0 - Differential Mode"] + #[inline(always)] + pub fn diffmode(&self) -> DIFFMODE_R { + DIFFMODE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Left-Adjusted Result"] + #[inline(always)] + pub fn leftadj(&self) -> LEFTADJ_R { + LEFTADJ_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Free Running Mode"] + #[inline(always)] + pub fn freerun(&self) -> FREERUN_R { + FREERUN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Digital Correction Logic Enable"] + #[inline(always)] + pub fn corren(&self) -> CORREN_R { + CORREN_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bits 4:5 - Conversion Result Resolution"] + #[inline(always)] + pub fn ressel(&self) -> RESSEL_R { + RESSEL_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bit 7 - Rail-to-Rail mode enable"] + #[inline(always)] + pub fn r2r(&self) -> R2R_R { + R2R_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Window Monitor Mode"] + #[inline(always)] + pub fn winmode(&self) -> WINMODE_R { + WINMODE_R::new(((self.bits >> 8) & 0x07) as u8) + } +} +impl W { + #[doc = "Bit 0 - Differential Mode"] + #[inline(always)] + pub fn diffmode(&mut self) -> DIFFMODE_W { + DIFFMODE_W { w: self } + } + #[doc = "Bit 1 - Left-Adjusted Result"] + #[inline(always)] + pub fn leftadj(&mut self) -> LEFTADJ_W { + LEFTADJ_W { w: self } + } + #[doc = "Bit 2 - Free Running Mode"] + #[inline(always)] + pub fn freerun(&mut self) -> FREERUN_W { + FREERUN_W { w: self } + } + #[doc = "Bit 3 - Digital Correction Logic Enable"] + #[inline(always)] + pub fn corren(&mut self) -> CORREN_W { + CORREN_W { w: self } + } + #[doc = "Bits 4:5 - Conversion Result Resolution"] + #[inline(always)] + pub fn ressel(&mut self) -> RESSEL_W { + RESSEL_W { w: self } + } + #[doc = "Bit 7 - Rail-to-Rail mode enable"] + #[inline(always)] + pub fn r2r(&mut self) -> R2R_W { + R2R_W { w: self } + } + #[doc = "Bits 8:10 - Window Monitor Mode"] + #[inline(always)] + pub fn winmode(&mut self) -> WINMODE_W { + WINMODE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control C\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlc](index.html) module"] +pub struct CTRLC_SPEC; +impl crate::RegisterSpec for CTRLC_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrlc::R](R) reader structure"] +impl crate::Readable for CTRLC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlc::W](W) writer structure"] +impl crate::Writable for CTRLC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLC to value 0"] +impl crate::Resettable for CTRLC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/adc0/dbgctrl.rs b/pac/atsamc20e/src/adc0/dbgctrl.rs new file mode 100644 index 000000000000..53636eb2b339 --- /dev/null +++ b/pac/atsamc20e/src/adc0/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Debug Run"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Debug Run"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/adc0/evctrl.rs b/pac/atsamc20e/src/adc0/evctrl.rs new file mode 100644 index 000000000000..295508f82de3 --- /dev/null +++ b/pac/atsamc20e/src/adc0/evctrl.rs @@ -0,0 +1,348 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FLUSHEI` reader - Flush Event Input Enable"] +pub struct FLUSHEI_R(crate::FieldReader); +impl FLUSHEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FLUSHEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FLUSHEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLUSHEI` writer - Flush Event Input Enable"] +pub struct FLUSHEI_W<'a> { + w: &'a mut W, +} +impl<'a> FLUSHEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `STARTEI` reader - Start Conversion Event Input Enable"] +pub struct STARTEI_R(crate::FieldReader); +impl STARTEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STARTEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STARTEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STARTEI` writer - Start Conversion Event Input Enable"] +pub struct STARTEI_W<'a> { + w: &'a mut W, +} +impl<'a> STARTEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `FLUSHINV` reader - Flush Event Invert Enable"] +pub struct FLUSHINV_R(crate::FieldReader); +impl FLUSHINV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FLUSHINV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FLUSHINV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLUSHINV` writer - Flush Event Invert Enable"] +pub struct FLUSHINV_W<'a> { + w: &'a mut W, +} +impl<'a> FLUSHINV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `STARTINV` reader - Start Event Invert Enable"] +pub struct STARTINV_R(crate::FieldReader); +impl STARTINV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STARTINV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STARTINV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STARTINV` writer - Start Event Invert Enable"] +pub struct STARTINV_W<'a> { + w: &'a mut W, +} +impl<'a> STARTINV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `RESRDYEO` reader - Result Ready Event Out"] +pub struct RESRDYEO_R(crate::FieldReader); +impl RESRDYEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESRDYEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESRDYEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESRDYEO` writer - Result Ready Event Out"] +pub struct RESRDYEO_W<'a> { + w: &'a mut W, +} +impl<'a> RESRDYEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `WINMONEO` reader - Window Monitor Event Out"] +pub struct WINMONEO_R(crate::FieldReader); +impl WINMONEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINMONEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINMONEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMONEO` writer - Window Monitor Event Out"] +pub struct WINMONEO_W<'a> { + w: &'a mut W, +} +impl<'a> WINMONEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Flush Event Input Enable"] + #[inline(always)] + pub fn flushei(&self) -> FLUSHEI_R { + FLUSHEI_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Start Conversion Event Input Enable"] + #[inline(always)] + pub fn startei(&self) -> STARTEI_R { + STARTEI_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Flush Event Invert Enable"] + #[inline(always)] + pub fn flushinv(&self) -> FLUSHINV_R { + FLUSHINV_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Start Event Invert Enable"] + #[inline(always)] + pub fn startinv(&self) -> STARTINV_R { + STARTINV_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Result Ready Event Out"] + #[inline(always)] + pub fn resrdyeo(&self) -> RESRDYEO_R { + RESRDYEO_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Window Monitor Event Out"] + #[inline(always)] + pub fn winmoneo(&self) -> WINMONEO_R { + WINMONEO_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Flush Event Input Enable"] + #[inline(always)] + pub fn flushei(&mut self) -> FLUSHEI_W { + FLUSHEI_W { w: self } + } + #[doc = "Bit 1 - Start Conversion Event Input Enable"] + #[inline(always)] + pub fn startei(&mut self) -> STARTEI_W { + STARTEI_W { w: self } + } + #[doc = "Bit 2 - Flush Event Invert Enable"] + #[inline(always)] + pub fn flushinv(&mut self) -> FLUSHINV_W { + FLUSHINV_W { w: self } + } + #[doc = "Bit 3 - Start Event Invert Enable"] + #[inline(always)] + pub fn startinv(&mut self) -> STARTINV_W { + STARTINV_W { w: self } + } + #[doc = "Bit 4 - Result Ready Event Out"] + #[inline(always)] + pub fn resrdyeo(&mut self) -> RESRDYEO_W { + RESRDYEO_W { w: self } + } + #[doc = "Bit 5 - Window Monitor Event Out"] + #[inline(always)] + pub fn winmoneo(&mut self) -> WINMONEO_W { + WINMONEO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/adc0/gaincorr.rs b/pac/atsamc20e/src/adc0/gaincorr.rs new file mode 100644 index 000000000000..496cb8c6021c --- /dev/null +++ b/pac/atsamc20e/src/adc0/gaincorr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `GAINCORR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GAINCORR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `GAINCORR` reader - Gain Correction Value"] +pub struct GAINCORR_R(crate::FieldReader); +impl GAINCORR_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + GAINCORR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GAINCORR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GAINCORR` writer - Gain Correction Value"] +pub struct GAINCORR_W<'a> { + w: &'a mut W, +} +impl<'a> GAINCORR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0fff) | (value as u16 & 0x0fff); + self.w + } +} +impl R { + #[doc = "Bits 0:11 - Gain Correction Value"] + #[inline(always)] + pub fn gaincorr(&self) -> GAINCORR_R { + GAINCORR_R::new((self.bits & 0x0fff) as u16) + } +} +impl W { + #[doc = "Bits 0:11 - Gain Correction Value"] + #[inline(always)] + pub fn gaincorr(&mut self) -> GAINCORR_W { + GAINCORR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Gain Correction\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gaincorr](index.html) module"] +pub struct GAINCORR_SPEC; +impl crate::RegisterSpec for GAINCORR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [gaincorr::R](R) reader structure"] +impl crate::Readable for GAINCORR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gaincorr::W](W) writer structure"] +impl crate::Writable for GAINCORR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets GAINCORR to value 0"] +impl crate::Resettable for GAINCORR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/adc0/inputctrl.rs b/pac/atsamc20e/src/adc0/inputctrl.rs new file mode 100644 index 000000000000..e0bd7489b5a5 --- /dev/null +++ b/pac/atsamc20e/src/adc0/inputctrl.rs @@ -0,0 +1,472 @@ +#[doc = "Register `INPUTCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INPUTCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Positive Mux Input Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MUXPOS_A { + #[doc = "0: ADC AIN0 Pin"] + AIN0 = 0, + #[doc = "1: ADC AIN1 Pin"] + AIN1 = 1, + #[doc = "2: ADC AIN2 Pin"] + AIN2 = 2, + #[doc = "3: ADC AIN3 Pin"] + AIN3 = 3, + #[doc = "4: ADC AIN4 Pin"] + AIN4 = 4, + #[doc = "5: ADC AIN5 Pin"] + AIN5 = 5, + #[doc = "6: ADC AIN6 Pin"] + AIN6 = 6, + #[doc = "7: ADC AIN7 Pin"] + AIN7 = 7, + #[doc = "8: ADC AIN8 Pin"] + AIN8 = 8, + #[doc = "9: ADC AIN9 Pin"] + AIN9 = 9, + #[doc = "10: ADC AIN10 Pin"] + AIN10 = 10, + #[doc = "11: ADC AIN11 Pin"] + AIN11 = 11, + #[doc = "25: Bandgap Voltage"] + BANDGAP = 25, + #[doc = "26: 1/4 Scaled Core Supply"] + SCALEDCOREVCC = 26, + #[doc = "27: 1/4 Scaled I/O Supply"] + SCALEDIOVCC = 27, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MUXPOS_A) -> Self { + variant as _ + } +} +#[doc = "Field `MUXPOS` reader - Positive Mux Input Selection"] +pub struct MUXPOS_R(crate::FieldReader); +impl MUXPOS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MUXPOS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MUXPOS_A::AIN0), + 1 => Some(MUXPOS_A::AIN1), + 2 => Some(MUXPOS_A::AIN2), + 3 => Some(MUXPOS_A::AIN3), + 4 => Some(MUXPOS_A::AIN4), + 5 => Some(MUXPOS_A::AIN5), + 6 => Some(MUXPOS_A::AIN6), + 7 => Some(MUXPOS_A::AIN7), + 8 => Some(MUXPOS_A::AIN8), + 9 => Some(MUXPOS_A::AIN9), + 10 => Some(MUXPOS_A::AIN10), + 11 => Some(MUXPOS_A::AIN11), + 25 => Some(MUXPOS_A::BANDGAP), + 26 => Some(MUXPOS_A::SCALEDCOREVCC), + 27 => Some(MUXPOS_A::SCALEDIOVCC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `AIN0`"] + #[inline(always)] + pub fn is_ain0(&self) -> bool { + **self == MUXPOS_A::AIN0 + } + #[doc = "Checks if the value of the field is `AIN1`"] + #[inline(always)] + pub fn is_ain1(&self) -> bool { + **self == MUXPOS_A::AIN1 + } + #[doc = "Checks if the value of the field is `AIN2`"] + #[inline(always)] + pub fn is_ain2(&self) -> bool { + **self == MUXPOS_A::AIN2 + } + #[doc = "Checks if the value of the field is `AIN3`"] + #[inline(always)] + pub fn is_ain3(&self) -> bool { + **self == MUXPOS_A::AIN3 + } + #[doc = "Checks if the value of the field is `AIN4`"] + #[inline(always)] + pub fn is_ain4(&self) -> bool { + **self == MUXPOS_A::AIN4 + } + #[doc = "Checks if the value of the field is `AIN5`"] + #[inline(always)] + pub fn is_ain5(&self) -> bool { + **self == MUXPOS_A::AIN5 + } + #[doc = "Checks if the value of the field is `AIN6`"] + #[inline(always)] + pub fn is_ain6(&self) -> bool { + **self == MUXPOS_A::AIN6 + } + #[doc = "Checks if the value of the field is `AIN7`"] + #[inline(always)] + pub fn is_ain7(&self) -> bool { + **self == MUXPOS_A::AIN7 + } + #[doc = "Checks if the value of the field is `AIN8`"] + #[inline(always)] + pub fn is_ain8(&self) -> bool { + **self == MUXPOS_A::AIN8 + } + #[doc = "Checks if the value of the field is `AIN9`"] + #[inline(always)] + pub fn is_ain9(&self) -> bool { + **self == MUXPOS_A::AIN9 + } + #[doc = "Checks if the value of the field is `AIN10`"] + #[inline(always)] + pub fn is_ain10(&self) -> bool { + **self == MUXPOS_A::AIN10 + } + #[doc = "Checks if the value of the field is `AIN11`"] + #[inline(always)] + pub fn is_ain11(&self) -> bool { + **self == MUXPOS_A::AIN11 + } + #[doc = "Checks if the value of the field is `BANDGAP`"] + #[inline(always)] + pub fn is_bandgap(&self) -> bool { + **self == MUXPOS_A::BANDGAP + } + #[doc = "Checks if the value of the field is `SCALEDCOREVCC`"] + #[inline(always)] + pub fn is_scaledcorevcc(&self) -> bool { + **self == MUXPOS_A::SCALEDCOREVCC + } + #[doc = "Checks if the value of the field is `SCALEDIOVCC`"] + #[inline(always)] + pub fn is_scalediovcc(&self) -> bool { + **self == MUXPOS_A::SCALEDIOVCC + } +} +impl core::ops::Deref for MUXPOS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MUXPOS` writer - Positive Mux Input Selection"] +pub struct MUXPOS_W<'a> { + w: &'a mut W, +} +impl<'a> MUXPOS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MUXPOS_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "ADC AIN0 Pin"] + #[inline(always)] + pub fn ain0(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN0) + } + #[doc = "ADC AIN1 Pin"] + #[inline(always)] + pub fn ain1(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN1) + } + #[doc = "ADC AIN2 Pin"] + #[inline(always)] + pub fn ain2(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN2) + } + #[doc = "ADC AIN3 Pin"] + #[inline(always)] + pub fn ain3(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN3) + } + #[doc = "ADC AIN4 Pin"] + #[inline(always)] + pub fn ain4(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN4) + } + #[doc = "ADC AIN5 Pin"] + #[inline(always)] + pub fn ain5(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN5) + } + #[doc = "ADC AIN6 Pin"] + #[inline(always)] + pub fn ain6(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN6) + } + #[doc = "ADC AIN7 Pin"] + #[inline(always)] + pub fn ain7(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN7) + } + #[doc = "ADC AIN8 Pin"] + #[inline(always)] + pub fn ain8(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN8) + } + #[doc = "ADC AIN9 Pin"] + #[inline(always)] + pub fn ain9(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN9) + } + #[doc = "ADC AIN10 Pin"] + #[inline(always)] + pub fn ain10(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN10) + } + #[doc = "ADC AIN11 Pin"] + #[inline(always)] + pub fn ain11(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN11) + } + #[doc = "Bandgap Voltage"] + #[inline(always)] + pub fn bandgap(self) -> &'a mut W { + self.variant(MUXPOS_A::BANDGAP) + } + #[doc = "1/4 Scaled Core Supply"] + #[inline(always)] + pub fn scaledcorevcc(self) -> &'a mut W { + self.variant(MUXPOS_A::SCALEDCOREVCC) + } + #[doc = "1/4 Scaled I/O Supply"] + #[inline(always)] + pub fn scalediovcc(self) -> &'a mut W { + self.variant(MUXPOS_A::SCALEDIOVCC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u16 & 0x1f); + self.w + } +} +#[doc = "Negative Mux Input Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MUXNEG_A { + #[doc = "0: ADC AIN0 Pin"] + AIN0 = 0, + #[doc = "1: ADC AIN1 Pin"] + AIN1 = 1, + #[doc = "2: ADC AIN2 Pin"] + AIN2 = 2, + #[doc = "3: ADC AIN3 Pin"] + AIN3 = 3, + #[doc = "4: ADC AIN4 Pin"] + AIN4 = 4, + #[doc = "5: ADC AIN5 Pin"] + AIN5 = 5, + #[doc = "24: Internal Ground"] + GND = 24, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MUXNEG_A) -> Self { + variant as _ + } +} +#[doc = "Field `MUXNEG` reader - Negative Mux Input Selection"] +pub struct MUXNEG_R(crate::FieldReader); +impl MUXNEG_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MUXNEG_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MUXNEG_A::AIN0), + 1 => Some(MUXNEG_A::AIN1), + 2 => Some(MUXNEG_A::AIN2), + 3 => Some(MUXNEG_A::AIN3), + 4 => Some(MUXNEG_A::AIN4), + 5 => Some(MUXNEG_A::AIN5), + 24 => Some(MUXNEG_A::GND), + _ => None, + } + } + #[doc = "Checks if the value of the field is `AIN0`"] + #[inline(always)] + pub fn is_ain0(&self) -> bool { + **self == MUXNEG_A::AIN0 + } + #[doc = "Checks if the value of the field is `AIN1`"] + #[inline(always)] + pub fn is_ain1(&self) -> bool { + **self == MUXNEG_A::AIN1 + } + #[doc = "Checks if the value of the field is `AIN2`"] + #[inline(always)] + pub fn is_ain2(&self) -> bool { + **self == MUXNEG_A::AIN2 + } + #[doc = "Checks if the value of the field is `AIN3`"] + #[inline(always)] + pub fn is_ain3(&self) -> bool { + **self == MUXNEG_A::AIN3 + } + #[doc = "Checks if the value of the field is `AIN4`"] + #[inline(always)] + pub fn is_ain4(&self) -> bool { + **self == MUXNEG_A::AIN4 + } + #[doc = "Checks if the value of the field is `AIN5`"] + #[inline(always)] + pub fn is_ain5(&self) -> bool { + **self == MUXNEG_A::AIN5 + } + #[doc = "Checks if the value of the field is `GND`"] + #[inline(always)] + pub fn is_gnd(&self) -> bool { + **self == MUXNEG_A::GND + } +} +impl core::ops::Deref for MUXNEG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MUXNEG` writer - Negative Mux Input Selection"] +pub struct MUXNEG_W<'a> { + w: &'a mut W, +} +impl<'a> MUXNEG_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MUXNEG_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "ADC AIN0 Pin"] + #[inline(always)] + pub fn ain0(self) -> &'a mut W { + self.variant(MUXNEG_A::AIN0) + } + #[doc = "ADC AIN1 Pin"] + #[inline(always)] + pub fn ain1(self) -> &'a mut W { + self.variant(MUXNEG_A::AIN1) + } + #[doc = "ADC AIN2 Pin"] + #[inline(always)] + pub fn ain2(self) -> &'a mut W { + self.variant(MUXNEG_A::AIN2) + } + #[doc = "ADC AIN3 Pin"] + #[inline(always)] + pub fn ain3(self) -> &'a mut W { + self.variant(MUXNEG_A::AIN3) + } + #[doc = "ADC AIN4 Pin"] + #[inline(always)] + pub fn ain4(self) -> &'a mut W { + self.variant(MUXNEG_A::AIN4) + } + #[doc = "ADC AIN5 Pin"] + #[inline(always)] + pub fn ain5(self) -> &'a mut W { + self.variant(MUXNEG_A::AIN5) + } + #[doc = "Internal Ground"] + #[inline(always)] + pub fn gnd(self) -> &'a mut W { + self.variant(MUXNEG_A::GND) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 8)) | ((value as u16 & 0x1f) << 8); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Positive Mux Input Selection"] + #[inline(always)] + pub fn muxpos(&self) -> MUXPOS_R { + MUXPOS_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 8:12 - Negative Mux Input Selection"] + #[inline(always)] + pub fn muxneg(&self) -> MUXNEG_R { + MUXNEG_R::new(((self.bits >> 8) & 0x1f) as u8) + } +} +impl W { + #[doc = "Bits 0:4 - Positive Mux Input Selection"] + #[inline(always)] + pub fn muxpos(&mut self) -> MUXPOS_W { + MUXPOS_W { w: self } + } + #[doc = "Bits 8:12 - Negative Mux Input Selection"] + #[inline(always)] + pub fn muxneg(&mut self) -> MUXNEG_W { + MUXNEG_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Input Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [inputctrl](index.html) module"] +pub struct INPUTCTRL_SPEC; +impl crate::RegisterSpec for INPUTCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [inputctrl::R](R) reader structure"] +impl crate::Readable for INPUTCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [inputctrl::W](W) writer structure"] +impl crate::Writable for INPUTCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INPUTCTRL to value 0"] +impl crate::Resettable for INPUTCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/adc0/intenclr.rs b/pac/atsamc20e/src/adc0/intenclr.rs new file mode 100644 index 000000000000..b10f428d30b1 --- /dev/null +++ b/pac/atsamc20e/src/adc0/intenclr.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RESRDY` reader - Result Ready Interrupt Disable"] +pub struct RESRDY_R(crate::FieldReader); +impl RESRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESRDY` writer - Result Ready Interrupt Disable"] +pub struct RESRDY_W<'a> { + w: &'a mut W, +} +impl<'a> RESRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `OVERRUN` reader - Overrun Interrupt Disable"] +pub struct OVERRUN_R(crate::FieldReader); +impl OVERRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVERRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVERRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVERRUN` writer - Overrun Interrupt Disable"] +pub struct OVERRUN_W<'a> { + w: &'a mut W, +} +impl<'a> OVERRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WINMON` reader - Window Monitor Interrupt Disable"] +pub struct WINMON_R(crate::FieldReader); +impl WINMON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINMON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINMON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMON` writer - Window Monitor Interrupt Disable"] +pub struct WINMON_W<'a> { + w: &'a mut W, +} +impl<'a> WINMON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Result Ready Interrupt Disable"] + #[inline(always)] + pub fn resrdy(&self) -> RESRDY_R { + RESRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Overrun Interrupt Disable"] + #[inline(always)] + pub fn overrun(&self) -> OVERRUN_R { + OVERRUN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Window Monitor Interrupt Disable"] + #[inline(always)] + pub fn winmon(&self) -> WINMON_R { + WINMON_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Result Ready Interrupt Disable"] + #[inline(always)] + pub fn resrdy(&mut self) -> RESRDY_W { + RESRDY_W { w: self } + } + #[doc = "Bit 1 - Overrun Interrupt Disable"] + #[inline(always)] + pub fn overrun(&mut self) -> OVERRUN_W { + OVERRUN_W { w: self } + } + #[doc = "Bit 2 - Window Monitor Interrupt Disable"] + #[inline(always)] + pub fn winmon(&mut self) -> WINMON_W { + WINMON_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/adc0/intenset.rs b/pac/atsamc20e/src/adc0/intenset.rs new file mode 100644 index 000000000000..5ca93b05b859 --- /dev/null +++ b/pac/atsamc20e/src/adc0/intenset.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RESRDY` reader - Result Ready Interrupt Enable"] +pub struct RESRDY_R(crate::FieldReader); +impl RESRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESRDY` writer - Result Ready Interrupt Enable"] +pub struct RESRDY_W<'a> { + w: &'a mut W, +} +impl<'a> RESRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `OVERRUN` reader - Overrun Interrupt Enable"] +pub struct OVERRUN_R(crate::FieldReader); +impl OVERRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVERRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVERRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVERRUN` writer - Overrun Interrupt Enable"] +pub struct OVERRUN_W<'a> { + w: &'a mut W, +} +impl<'a> OVERRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WINMON` reader - Window Monitor Interrupt Enable"] +pub struct WINMON_R(crate::FieldReader); +impl WINMON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINMON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINMON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMON` writer - Window Monitor Interrupt Enable"] +pub struct WINMON_W<'a> { + w: &'a mut W, +} +impl<'a> WINMON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Result Ready Interrupt Enable"] + #[inline(always)] + pub fn resrdy(&self) -> RESRDY_R { + RESRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Overrun Interrupt Enable"] + #[inline(always)] + pub fn overrun(&self) -> OVERRUN_R { + OVERRUN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Window Monitor Interrupt Enable"] + #[inline(always)] + pub fn winmon(&self) -> WINMON_R { + WINMON_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Result Ready Interrupt Enable"] + #[inline(always)] + pub fn resrdy(&mut self) -> RESRDY_W { + RESRDY_W { w: self } + } + #[doc = "Bit 1 - Overrun Interrupt Enable"] + #[inline(always)] + pub fn overrun(&mut self) -> OVERRUN_W { + OVERRUN_W { w: self } + } + #[doc = "Bit 2 - Window Monitor Interrupt Enable"] + #[inline(always)] + pub fn winmon(&mut self) -> WINMON_W { + WINMON_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/adc0/intflag.rs b/pac/atsamc20e/src/adc0/intflag.rs new file mode 100644 index 000000000000..3cd74788b226 --- /dev/null +++ b/pac/atsamc20e/src/adc0/intflag.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RESRDY` reader - Result Ready Interrupt Flag"] +pub struct RESRDY_R(crate::FieldReader); +impl RESRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESRDY` writer - Result Ready Interrupt Flag"] +pub struct RESRDY_W<'a> { + w: &'a mut W, +} +impl<'a> RESRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `OVERRUN` reader - Overrun Interrupt Flag"] +pub struct OVERRUN_R(crate::FieldReader); +impl OVERRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVERRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVERRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVERRUN` writer - Overrun Interrupt Flag"] +pub struct OVERRUN_W<'a> { + w: &'a mut W, +} +impl<'a> OVERRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WINMON` reader - Window Monitor Interrupt Flag"] +pub struct WINMON_R(crate::FieldReader); +impl WINMON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINMON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINMON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMON` writer - Window Monitor Interrupt Flag"] +pub struct WINMON_W<'a> { + w: &'a mut W, +} +impl<'a> WINMON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Result Ready Interrupt Flag"] + #[inline(always)] + pub fn resrdy(&self) -> RESRDY_R { + RESRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Overrun Interrupt Flag"] + #[inline(always)] + pub fn overrun(&self) -> OVERRUN_R { + OVERRUN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Window Monitor Interrupt Flag"] + #[inline(always)] + pub fn winmon(&self) -> WINMON_R { + WINMON_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Result Ready Interrupt Flag"] + #[inline(always)] + pub fn resrdy(&mut self) -> RESRDY_W { + RESRDY_W { w: self } + } + #[doc = "Bit 1 - Overrun Interrupt Flag"] + #[inline(always)] + pub fn overrun(&mut self) -> OVERRUN_W { + OVERRUN_W { w: self } + } + #[doc = "Bit 2 - Window Monitor Interrupt Flag"] + #[inline(always)] + pub fn winmon(&mut self) -> WINMON_W { + WINMON_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/adc0/offsetcorr.rs b/pac/atsamc20e/src/adc0/offsetcorr.rs new file mode 100644 index 000000000000..24a97427c64e --- /dev/null +++ b/pac/atsamc20e/src/adc0/offsetcorr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `OFFSETCORR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OFFSETCORR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OFFSETCORR` reader - Offset Correction Value"] +pub struct OFFSETCORR_R(crate::FieldReader); +impl OFFSETCORR_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + OFFSETCORR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OFFSETCORR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OFFSETCORR` writer - Offset Correction Value"] +pub struct OFFSETCORR_W<'a> { + w: &'a mut W, +} +impl<'a> OFFSETCORR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0fff) | (value as u16 & 0x0fff); + self.w + } +} +impl R { + #[doc = "Bits 0:11 - Offset Correction Value"] + #[inline(always)] + pub fn offsetcorr(&self) -> OFFSETCORR_R { + OFFSETCORR_R::new((self.bits & 0x0fff) as u16) + } +} +impl W { + #[doc = "Bits 0:11 - Offset Correction Value"] + #[inline(always)] + pub fn offsetcorr(&mut self) -> OFFSETCORR_W { + OFFSETCORR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Offset Correction\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [offsetcorr](index.html) module"] +pub struct OFFSETCORR_SPEC; +impl crate::RegisterSpec for OFFSETCORR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [offsetcorr::R](R) reader structure"] +impl crate::Readable for OFFSETCORR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [offsetcorr::W](W) writer structure"] +impl crate::Writable for OFFSETCORR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OFFSETCORR to value 0"] +impl crate::Resettable for OFFSETCORR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/adc0/refctrl.rs b/pac/atsamc20e/src/adc0/refctrl.rs new file mode 100644 index 000000000000..c21b6532936f --- /dev/null +++ b/pac/atsamc20e/src/adc0/refctrl.rs @@ -0,0 +1,238 @@ +#[doc = "Register `REFCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `REFCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Reference Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum REFSEL_A { + #[doc = "0: Internal Bandgap Reference"] + INTREF = 0, + #[doc = "1: 1/1.6 VDDANA"] + INTVCC0 = 1, + #[doc = "2: 1/2 VDDANA"] + INTVCC1 = 2, + #[doc = "3: External Reference"] + AREFA = 3, + #[doc = "5: VDDANA"] + INTVCC2 = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: REFSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `REFSEL` reader - Reference Selection"] +pub struct REFSEL_R(crate::FieldReader); +impl REFSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REFSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(REFSEL_A::INTREF), + 1 => Some(REFSEL_A::INTVCC0), + 2 => Some(REFSEL_A::INTVCC1), + 3 => Some(REFSEL_A::AREFA), + 5 => Some(REFSEL_A::INTVCC2), + _ => None, + } + } + #[doc = "Checks if the value of the field is `INTREF`"] + #[inline(always)] + pub fn is_intref(&self) -> bool { + **self == REFSEL_A::INTREF + } + #[doc = "Checks if the value of the field is `INTVCC0`"] + #[inline(always)] + pub fn is_intvcc0(&self) -> bool { + **self == REFSEL_A::INTVCC0 + } + #[doc = "Checks if the value of the field is `INTVCC1`"] + #[inline(always)] + pub fn is_intvcc1(&self) -> bool { + **self == REFSEL_A::INTVCC1 + } + #[doc = "Checks if the value of the field is `AREFA`"] + #[inline(always)] + pub fn is_arefa(&self) -> bool { + **self == REFSEL_A::AREFA + } + #[doc = "Checks if the value of the field is `INTVCC2`"] + #[inline(always)] + pub fn is_intvcc2(&self) -> bool { + **self == REFSEL_A::INTVCC2 + } +} +impl core::ops::Deref for REFSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REFSEL` writer - Reference Selection"] +pub struct REFSEL_W<'a> { + w: &'a mut W, +} +impl<'a> REFSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: REFSEL_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Internal Bandgap Reference"] + #[inline(always)] + pub fn intref(self) -> &'a mut W { + self.variant(REFSEL_A::INTREF) + } + #[doc = "1/1.6 VDDANA"] + #[inline(always)] + pub fn intvcc0(self) -> &'a mut W { + self.variant(REFSEL_A::INTVCC0) + } + #[doc = "1/2 VDDANA"] + #[inline(always)] + pub fn intvcc1(self) -> &'a mut W { + self.variant(REFSEL_A::INTVCC1) + } + #[doc = "External Reference"] + #[inline(always)] + pub fn arefa(self) -> &'a mut W { + self.variant(REFSEL_A::AREFA) + } + #[doc = "VDDANA"] + #[inline(always)] + pub fn intvcc2(self) -> &'a mut W { + self.variant(REFSEL_A::INTVCC2) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +#[doc = "Field `REFCOMP` reader - Reference Buffer Offset Compensation Enable"] +pub struct REFCOMP_R(crate::FieldReader); +impl REFCOMP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + REFCOMP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REFCOMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REFCOMP` writer - Reference Buffer Offset Compensation Enable"] +pub struct REFCOMP_W<'a> { + w: &'a mut W, +} +impl<'a> REFCOMP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Reference Selection"] + #[inline(always)] + pub fn refsel(&self) -> REFSEL_R { + REFSEL_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 7 - Reference Buffer Offset Compensation Enable"] + #[inline(always)] + pub fn refcomp(&self) -> REFCOMP_R { + REFCOMP_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Reference Selection"] + #[inline(always)] + pub fn refsel(&mut self) -> REFSEL_W { + REFSEL_W { w: self } + } + #[doc = "Bit 7 - Reference Buffer Offset Compensation Enable"] + #[inline(always)] + pub fn refcomp(&mut self) -> REFCOMP_W { + REFCOMP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Reference Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [refctrl](index.html) module"] +pub struct REFCTRL_SPEC; +impl crate::RegisterSpec for REFCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [refctrl::R](R) reader structure"] +impl crate::Readable for REFCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [refctrl::W](W) writer structure"] +impl crate::Writable for REFCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets REFCTRL to value 0"] +impl crate::Resettable for REFCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/adc0/result.rs b/pac/atsamc20e/src/adc0/result.rs new file mode 100644 index 000000000000..b63b08cc72b9 --- /dev/null +++ b/pac/atsamc20e/src/adc0/result.rs @@ -0,0 +1,53 @@ +#[doc = "Register `RESULT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `RESULT` reader - Result Value"] +pub struct RESULT_R(crate::FieldReader); +impl RESULT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + RESULT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESULT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:15 - Result Value"] + #[inline(always)] + pub fn result(&self) -> RESULT_R { + RESULT_R::new(self.bits as u16) + } +} +#[doc = "Result\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [result](index.html) module"] +pub struct RESULT_SPEC; +impl crate::RegisterSpec for RESULT_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [result::R](R) reader structure"] +impl crate::Readable for RESULT_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets RESULT to value 0"] +impl crate::Resettable for RESULT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/adc0/sampctrl.rs b/pac/atsamc20e/src/adc0/sampctrl.rs new file mode 100644 index 000000000000..be4b77a80410 --- /dev/null +++ b/pac/atsamc20e/src/adc0/sampctrl.rs @@ -0,0 +1,150 @@ +#[doc = "Register `SAMPCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SAMPCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SAMPLEN` reader - Sampling Time Length"] +pub struct SAMPLEN_R(crate::FieldReader); +impl SAMPLEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SAMPLEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SAMPLEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SAMPLEN` writer - Sampling Time Length"] +pub struct SAMPLEN_W<'a> { + w: &'a mut W, +} +impl<'a> SAMPLEN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u8 & 0x3f); + self.w + } +} +#[doc = "Field `OFFCOMP` reader - Comparator Offset Compensation Enable"] +pub struct OFFCOMP_R(crate::FieldReader); +impl OFFCOMP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OFFCOMP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OFFCOMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OFFCOMP` writer - Comparator Offset Compensation Enable"] +pub struct OFFCOMP_W<'a> { + w: &'a mut W, +} +impl<'a> OFFCOMP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Sampling Time Length"] + #[inline(always)] + pub fn samplen(&self) -> SAMPLEN_R { + SAMPLEN_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 7 - Comparator Offset Compensation Enable"] + #[inline(always)] + pub fn offcomp(&self) -> OFFCOMP_R { + OFFCOMP_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:5 - Sampling Time Length"] + #[inline(always)] + pub fn samplen(&mut self) -> SAMPLEN_W { + SAMPLEN_W { w: self } + } + #[doc = "Bit 7 - Comparator Offset Compensation Enable"] + #[inline(always)] + pub fn offcomp(&mut self) -> OFFCOMP_W { + OFFCOMP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Sample Time Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sampctrl](index.html) module"] +pub struct SAMPCTRL_SPEC; +impl crate::RegisterSpec for SAMPCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [sampctrl::R](R) reader structure"] +impl crate::Readable for SAMPCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [sampctrl::W](W) writer structure"] +impl crate::Writable for SAMPCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SAMPCTRL to value 0"] +impl crate::Resettable for SAMPCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/adc0/seqctrl.rs b/pac/atsamc20e/src/adc0/seqctrl.rs new file mode 100644 index 000000000000..c8388c9a393f --- /dev/null +++ b/pac/atsamc20e/src/adc0/seqctrl.rs @@ -0,0 +1,103 @@ +#[doc = "Register `SEQCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SEQCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SEQEN` reader - Enable Positive Input in the Sequence"] +pub struct SEQEN_R(crate::FieldReader); +impl SEQEN_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + SEQEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEQEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEQEN` writer - Enable Positive Input in the Sequence"] +pub struct SEQEN_W<'a> { + w: &'a mut W, +} +impl<'a> SEQEN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Enable Positive Input in the Sequence"] + #[inline(always)] + pub fn seqen(&self) -> SEQEN_R { + SEQEN_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Enable Positive Input in the Sequence"] + #[inline(always)] + pub fn seqen(&mut self) -> SEQEN_W { + SEQEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Sequence Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [seqctrl](index.html) module"] +pub struct SEQCTRL_SPEC; +impl crate::RegisterSpec for SEQCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [seqctrl::R](R) reader structure"] +impl crate::Readable for SEQCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [seqctrl::W](W) writer structure"] +impl crate::Writable for SEQCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SEQCTRL to value 0"] +impl crate::Resettable for SEQCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/adc0/seqstatus.rs b/pac/atsamc20e/src/adc0/seqstatus.rs new file mode 100644 index 000000000000..42c820892e9a --- /dev/null +++ b/pac/atsamc20e/src/adc0/seqstatus.rs @@ -0,0 +1,73 @@ +#[doc = "Register `SEQSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SEQSTATE` reader - Sequence State"] +pub struct SEQSTATE_R(crate::FieldReader); +impl SEQSTATE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SEQSTATE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEQSTATE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEQBUSY` reader - Sequence Busy"] +pub struct SEQBUSY_R(crate::FieldReader); +impl SEQBUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SEQBUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEQBUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:4 - Sequence State"] + #[inline(always)] + pub fn seqstate(&self) -> SEQSTATE_R { + SEQSTATE_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bit 7 - Sequence Busy"] + #[inline(always)] + pub fn seqbusy(&self) -> SEQBUSY_R { + SEQBUSY_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +#[doc = "Sequence Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [seqstatus](index.html) module"] +pub struct SEQSTATUS_SPEC; +impl crate::RegisterSpec for SEQSTATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [seqstatus::R](R) reader structure"] +impl crate::Readable for SEQSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SEQSTATUS to value 0"] +impl crate::Resettable for SEQSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/adc0/swtrig.rs b/pac/atsamc20e/src/adc0/swtrig.rs new file mode 100644 index 000000000000..5e23ed7865ed --- /dev/null +++ b/pac/atsamc20e/src/adc0/swtrig.rs @@ -0,0 +1,160 @@ +#[doc = "Register `SWTRIG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SWTRIG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FLUSH` reader - ADC Flush"] +pub struct FLUSH_R(crate::FieldReader); +impl FLUSH_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FLUSH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FLUSH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLUSH` writer - ADC Flush"] +pub struct FLUSH_W<'a> { + w: &'a mut W, +} +impl<'a> FLUSH_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `START` reader - Start ADC Conversion"] +pub struct START_R(crate::FieldReader); +impl START_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + START_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for START_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `START` writer - Start ADC Conversion"] +pub struct START_W<'a> { + w: &'a mut W, +} +impl<'a> START_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - ADC Flush"] + #[inline(always)] + pub fn flush(&self) -> FLUSH_R { + FLUSH_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Start ADC Conversion"] + #[inline(always)] + pub fn start(&self) -> START_R { + START_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - ADC Flush"] + #[inline(always)] + pub fn flush(&mut self) -> FLUSH_W { + FLUSH_W { w: self } + } + #[doc = "Bit 1 - Start ADC Conversion"] + #[inline(always)] + pub fn start(&mut self) -> START_W { + START_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Software Trigger\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [swtrig](index.html) module"] +pub struct SWTRIG_SPEC; +impl crate::RegisterSpec for SWTRIG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [swtrig::R](R) reader structure"] +impl crate::Readable for SWTRIG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [swtrig::W](W) writer structure"] +impl crate::Writable for SWTRIG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SWTRIG to value 0"] +impl crate::Resettable for SWTRIG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/adc0/syncbusy.rs b/pac/atsamc20e/src/adc0/syncbusy.rs new file mode 100644 index 000000000000..9c92da8a7c74 --- /dev/null +++ b/pac/atsamc20e/src/adc0/syncbusy.rs @@ -0,0 +1,253 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - SWRST Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - ENABLE Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INPUTCTRL` reader - INPUTCTRL Synchronization Busy"] +pub struct INPUTCTRL_R(crate::FieldReader); +impl INPUTCTRL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INPUTCTRL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INPUTCTRL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLC` reader - CTRLC Synchronization Busy"] +pub struct CTRLC_R(crate::FieldReader); +impl CTRLC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AVGCTRL` reader - AVGCTRL Synchronization Busy"] +pub struct AVGCTRL_R(crate::FieldReader); +impl AVGCTRL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AVGCTRL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AVGCTRL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SAMPCTRL` reader - SAMPCTRL Synchronization Busy"] +pub struct SAMPCTRL_R(crate::FieldReader); +impl SAMPCTRL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SAMPCTRL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SAMPCTRL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINLT` reader - WINLT Synchronization Busy"] +pub struct WINLT_R(crate::FieldReader); +impl WINLT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINLT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINLT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINUT` reader - WINUT Synchronization Busy"] +pub struct WINUT_R(crate::FieldReader); +impl WINUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GAINCORR` reader - GAINCORR Synchronization Busy"] +pub struct GAINCORR_R(crate::FieldReader); +impl GAINCORR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GAINCORR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GAINCORR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OFFSETCORR` reader - OFFSETCTRL Synchronization Busy"] +pub struct OFFSETCORR_R(crate::FieldReader); +impl OFFSETCORR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OFFSETCORR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OFFSETCORR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG` reader - SWTRG Synchronization Busy"] +pub struct SWTRIG_R(crate::FieldReader); +impl SWTRIG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - SWRST Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ENABLE Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - INPUTCTRL Synchronization Busy"] + #[inline(always)] + pub fn inputctrl(&self) -> INPUTCTRL_R { + INPUTCTRL_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - CTRLC Synchronization Busy"] + #[inline(always)] + pub fn ctrlc(&self) -> CTRLC_R { + CTRLC_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - AVGCTRL Synchronization Busy"] + #[inline(always)] + pub fn avgctrl(&self) -> AVGCTRL_R { + AVGCTRL_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - SAMPCTRL Synchronization Busy"] + #[inline(always)] + pub fn sampctrl(&self) -> SAMPCTRL_R { + SAMPCTRL_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - WINLT Synchronization Busy"] + #[inline(always)] + pub fn winlt(&self) -> WINLT_R { + WINLT_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - WINUT Synchronization Busy"] + #[inline(always)] + pub fn winut(&self) -> WINUT_R { + WINUT_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - GAINCORR Synchronization Busy"] + #[inline(always)] + pub fn gaincorr(&self) -> GAINCORR_R { + GAINCORR_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - OFFSETCTRL Synchronization Busy"] + #[inline(always)] + pub fn offsetcorr(&self) -> OFFSETCORR_R { + OFFSETCORR_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - SWTRG Synchronization Busy"] + #[inline(always)] + pub fn swtrig(&self) -> SWTRIG_R { + SWTRIG_R::new(((self.bits >> 10) & 0x01) != 0) + } +} +#[doc = "Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/adc0/winlt.rs b/pac/atsamc20e/src/adc0/winlt.rs new file mode 100644 index 000000000000..2a3397684767 --- /dev/null +++ b/pac/atsamc20e/src/adc0/winlt.rs @@ -0,0 +1,103 @@ +#[doc = "Register `WINLT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WINLT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WINLT` reader - Window Lower Threshold"] +pub struct WINLT_R(crate::FieldReader); +impl WINLT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + WINLT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINLT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINLT` writer - Window Lower Threshold"] +pub struct WINLT_W<'a> { + w: &'a mut W, +} +impl<'a> WINLT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Window Lower Threshold"] + #[inline(always)] + pub fn winlt(&self) -> WINLT_R { + WINLT_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Window Lower Threshold"] + #[inline(always)] + pub fn winlt(&mut self) -> WINLT_W { + WINLT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Window Monitor Lower Threshold\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [winlt](index.html) module"] +pub struct WINLT_SPEC; +impl crate::RegisterSpec for WINLT_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [winlt::R](R) reader structure"] +impl crate::Readable for WINLT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [winlt::W](W) writer structure"] +impl crate::Writable for WINLT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WINLT to value 0"] +impl crate::Resettable for WINLT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/adc0/winut.rs b/pac/atsamc20e/src/adc0/winut.rs new file mode 100644 index 000000000000..0ea123174937 --- /dev/null +++ b/pac/atsamc20e/src/adc0/winut.rs @@ -0,0 +1,103 @@ +#[doc = "Register `WINUT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WINUT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WINUT` reader - Window Upper Threshold"] +pub struct WINUT_R(crate::FieldReader); +impl WINUT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + WINUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINUT` writer - Window Upper Threshold"] +pub struct WINUT_W<'a> { + w: &'a mut W, +} +impl<'a> WINUT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Window Upper Threshold"] + #[inline(always)] + pub fn winut(&self) -> WINUT_R { + WINUT_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Window Upper Threshold"] + #[inline(always)] + pub fn winut(&mut self) -> WINUT_W { + WINUT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Window Monitor Upper Threshold\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [winut](index.html) module"] +pub struct WINUT_SPEC; +impl crate::RegisterSpec for WINUT_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [winut::R](R) reader structure"] +impl crate::Readable for WINUT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [winut::W](W) writer structure"] +impl crate::Writable for WINUT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WINUT to value 0"] +impl crate::Resettable for WINUT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/ccl.rs b/pac/atsamc20e/src/ccl.rs new file mode 100644 index 000000000000..30b1f41639c1 --- /dev/null +++ b/pac/atsamc20e/src/ccl.rs @@ -0,0 +1,24 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrl: crate::Reg, + _reserved1: [u8; 0x03], + #[doc = "0x04 - SEQ Control x"] + pub seqctrl: [crate::Reg; 2], + _reserved2: [u8; 0x02], + #[doc = "0x08..0x18 - LUT Control x"] + pub lutctrl: [crate::Reg; 4], +} +#[doc = "CTRL register accessor: an alias for `Reg`"] +pub type CTRL = crate::Reg; +#[doc = "Control"] +pub mod ctrl; +#[doc = "SEQCTRL register accessor: an alias for `Reg`"] +pub type SEQCTRL = crate::Reg; +#[doc = "SEQ Control x"] +pub mod seqctrl; +#[doc = "LUTCTRL register accessor: an alias for `Reg`"] +pub type LUTCTRL = crate::Reg; +#[doc = "LUT Control x"] +pub mod lutctrl; diff --git a/pac/atsamc20e/src/ccl/ctrl.rs b/pac/atsamc20e/src/ccl/ctrl.rs new file mode 100644 index 000000000000..5e515fe037ca --- /dev/null +++ b/pac/atsamc20e/src/ccl/ctrl.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"] +pub struct CTRL_SPEC; +impl crate::RegisterSpec for CTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrl::R](R) reader structure"] +impl crate::Readable for CTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"] +impl crate::Writable for CTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/ccl/lutctrl.rs b/pac/atsamc20e/src/ccl/lutctrl.rs new file mode 100644 index 000000000000..530ed34f7c81 --- /dev/null +++ b/pac/atsamc20e/src/ccl/lutctrl.rs @@ -0,0 +1,702 @@ +#[doc = "Register `LUTCTRL[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `LUTCTRL[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - LUT Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - LUT Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Filter Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FILTSEL_A { + #[doc = "0: Filter disabled"] + DISABLE = 0, + #[doc = "1: Synchronizer enabled"] + SYNCH = 1, + #[doc = "2: Filter enabled"] + FILTER = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FILTSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `FILTSEL` reader - Filter Selection"] +pub struct FILTSEL_R(crate::FieldReader); +impl FILTSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FILTSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(FILTSEL_A::DISABLE), + 1 => Some(FILTSEL_A::SYNCH), + 2 => Some(FILTSEL_A::FILTER), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == FILTSEL_A::DISABLE + } + #[doc = "Checks if the value of the field is `SYNCH`"] + #[inline(always)] + pub fn is_synch(&self) -> bool { + **self == FILTSEL_A::SYNCH + } + #[doc = "Checks if the value of the field is `FILTER`"] + #[inline(always)] + pub fn is_filter(&self) -> bool { + **self == FILTSEL_A::FILTER + } +} +impl core::ops::Deref for FILTSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTSEL` writer - Filter Selection"] +pub struct FILTSEL_W<'a> { + w: &'a mut W, +} +impl<'a> FILTSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FILTSEL_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Filter disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(FILTSEL_A::DISABLE) + } + #[doc = "Synchronizer enabled"] + #[inline(always)] + pub fn synch(self) -> &'a mut W { + self.variant(FILTSEL_A::SYNCH) + } + #[doc = "Filter enabled"] + #[inline(always)] + pub fn filter(self) -> &'a mut W { + self.variant(FILTSEL_A::FILTER) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u32 & 0x03) << 4); + self.w + } +} +#[doc = "Field `EDGESEL` reader - Edge Selection"] +pub struct EDGESEL_R(crate::FieldReader); +impl EDGESEL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EDGESEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EDGESEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EDGESEL` writer - Edge Selection"] +pub struct EDGESEL_W<'a> { + w: &'a mut W, +} +impl<'a> EDGESEL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Input Selection 0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum INSEL0_A { + #[doc = "0: Masked input"] + MASK = 0, + #[doc = "1: Feedback input source"] + FEEDBACK = 1, + #[doc = "2: Linked LUT input source"] + LINK = 2, + #[doc = "3: Event in put source"] + EVENT = 3, + #[doc = "4: I/O pin input source"] + IO = 4, + #[doc = "5: AC input source"] + AC = 5, + #[doc = "6: TC input source"] + TC = 6, + #[doc = "7: Alternate TC input source"] + ALTTC = 7, + #[doc = "8: TCC input source"] + TCC = 8, + #[doc = "9: SERCOM inout source"] + SERCOM = 9, +} +impl From for u8 { + #[inline(always)] + fn from(variant: INSEL0_A) -> Self { + variant as _ + } +} +#[doc = "Field `INSEL0` reader - Input Selection 0"] +pub struct INSEL0_R(crate::FieldReader); +impl INSEL0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + INSEL0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(INSEL0_A::MASK), + 1 => Some(INSEL0_A::FEEDBACK), + 2 => Some(INSEL0_A::LINK), + 3 => Some(INSEL0_A::EVENT), + 4 => Some(INSEL0_A::IO), + 5 => Some(INSEL0_A::AC), + 6 => Some(INSEL0_A::TC), + 7 => Some(INSEL0_A::ALTTC), + 8 => Some(INSEL0_A::TCC), + 9 => Some(INSEL0_A::SERCOM), + _ => None, + } + } + #[doc = "Checks if the value of the field is `MASK`"] + #[inline(always)] + pub fn is_mask(&self) -> bool { + **self == INSEL0_A::MASK + } + #[doc = "Checks if the value of the field is `FEEDBACK`"] + #[inline(always)] + pub fn is_feedback(&self) -> bool { + **self == INSEL0_A::FEEDBACK + } + #[doc = "Checks if the value of the field is `LINK`"] + #[inline(always)] + pub fn is_link(&self) -> bool { + **self == INSEL0_A::LINK + } + #[doc = "Checks if the value of the field is `EVENT`"] + #[inline(always)] + pub fn is_event(&self) -> bool { + **self == INSEL0_A::EVENT + } + #[doc = "Checks if the value of the field is `IO`"] + #[inline(always)] + pub fn is_io(&self) -> bool { + **self == INSEL0_A::IO + } + #[doc = "Checks if the value of the field is `AC`"] + #[inline(always)] + pub fn is_ac(&self) -> bool { + **self == INSEL0_A::AC + } + #[doc = "Checks if the value of the field is `TC`"] + #[inline(always)] + pub fn is_tc(&self) -> bool { + **self == INSEL0_A::TC + } + #[doc = "Checks if the value of the field is `ALTTC`"] + #[inline(always)] + pub fn is_alttc(&self) -> bool { + **self == INSEL0_A::ALTTC + } + #[doc = "Checks if the value of the field is `TCC`"] + #[inline(always)] + pub fn is_tcc(&self) -> bool { + **self == INSEL0_A::TCC + } + #[doc = "Checks if the value of the field is `SERCOM`"] + #[inline(always)] + pub fn is_sercom(&self) -> bool { + **self == INSEL0_A::SERCOM + } +} +impl core::ops::Deref for INSEL0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INSEL0` writer - Input Selection 0"] +pub struct INSEL0_W<'a> { + w: &'a mut W, +} +impl<'a> INSEL0_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: INSEL0_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Masked input"] + #[inline(always)] + pub fn mask(self) -> &'a mut W { + self.variant(INSEL0_A::MASK) + } + #[doc = "Feedback input source"] + #[inline(always)] + pub fn feedback(self) -> &'a mut W { + self.variant(INSEL0_A::FEEDBACK) + } + #[doc = "Linked LUT input source"] + #[inline(always)] + pub fn link(self) -> &'a mut W { + self.variant(INSEL0_A::LINK) + } + #[doc = "Event in put source"] + #[inline(always)] + pub fn event(self) -> &'a mut W { + self.variant(INSEL0_A::EVENT) + } + #[doc = "I/O pin input source"] + #[inline(always)] + pub fn io(self) -> &'a mut W { + self.variant(INSEL0_A::IO) + } + #[doc = "AC input source"] + #[inline(always)] + pub fn ac(self) -> &'a mut W { + self.variant(INSEL0_A::AC) + } + #[doc = "TC input source"] + #[inline(always)] + pub fn tc(self) -> &'a mut W { + self.variant(INSEL0_A::TC) + } + #[doc = "Alternate TC input source"] + #[inline(always)] + pub fn alttc(self) -> &'a mut W { + self.variant(INSEL0_A::ALTTC) + } + #[doc = "TCC input source"] + #[inline(always)] + pub fn tcc(self) -> &'a mut W { + self.variant(INSEL0_A::TCC) + } + #[doc = "SERCOM inout source"] + #[inline(always)] + pub fn sercom(self) -> &'a mut W { + self.variant(INSEL0_A::SERCOM) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 8)) | ((value as u32 & 0x0f) << 8); + self.w + } +} +#[doc = "Field `INSEL1` reader - Input Selection 1"] +pub struct INSEL1_R(crate::FieldReader); +impl INSEL1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + INSEL1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INSEL1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INSEL1` writer - Input Selection 1"] +pub struct INSEL1_W<'a> { + w: &'a mut W, +} +impl<'a> INSEL1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 12)) | ((value as u32 & 0x0f) << 12); + self.w + } +} +#[doc = "Field `INSEL2` reader - Input Selection 2"] +pub struct INSEL2_R(crate::FieldReader); +impl INSEL2_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + INSEL2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INSEL2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INSEL2` writer - Input Selection 2"] +pub struct INSEL2_W<'a> { + w: &'a mut W, +} +impl<'a> INSEL2_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 16)) | ((value as u32 & 0x0f) << 16); + self.w + } +} +#[doc = "Field `INVEI` reader - Input Event Invert"] +pub struct INVEI_R(crate::FieldReader); +impl INVEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEI` writer - Input Event Invert"] +pub struct INVEI_W<'a> { + w: &'a mut W, +} +impl<'a> INVEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `LUTEI` reader - Event Input Enable"] +pub struct LUTEI_R(crate::FieldReader); +impl LUTEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LUTEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LUTEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LUTEI` writer - Event Input Enable"] +pub struct LUTEI_W<'a> { + w: &'a mut W, +} +impl<'a> LUTEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `LUTEO` reader - Event Output Enable"] +pub struct LUTEO_R(crate::FieldReader); +impl LUTEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LUTEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LUTEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LUTEO` writer - Event Output Enable"] +pub struct LUTEO_W<'a> { + w: &'a mut W, +} +impl<'a> LUTEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `TRUTH` reader - Truth Value"] +pub struct TRUTH_R(crate::FieldReader); +impl TRUTH_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TRUTH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRUTH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRUTH` writer - Truth Value"] +pub struct TRUTH_W<'a> { + w: &'a mut W, +} +impl<'a> TRUTH_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 24)) | ((value as u32 & 0xff) << 24); + self.w + } +} +impl R { + #[doc = "Bit 1 - LUT Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 4:5 - Filter Selection"] + #[inline(always)] + pub fn filtsel(&self) -> FILTSEL_R { + FILTSEL_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bit 7 - Edge Selection"] + #[inline(always)] + pub fn edgesel(&self) -> EDGESEL_R { + EDGESEL_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:11 - Input Selection 0"] + #[inline(always)] + pub fn insel0(&self) -> INSEL0_R { + INSEL0_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - Input Selection 1"] + #[inline(always)] + pub fn insel1(&self) -> INSEL1_R { + INSEL1_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:19 - Input Selection 2"] + #[inline(always)] + pub fn insel2(&self) -> INSEL2_R { + INSEL2_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Input Event Invert"] + #[inline(always)] + pub fn invei(&self) -> INVEI_R { + INVEI_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Event Input Enable"] + #[inline(always)] + pub fn lutei(&self) -> LUTEI_R { + LUTEI_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Event Output Enable"] + #[inline(always)] + pub fn luteo(&self) -> LUTEO_R { + LUTEO_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bits 24:31 - Truth Value"] + #[inline(always)] + pub fn truth(&self) -> TRUTH_R { + TRUTH_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bit 1 - LUT Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 4:5 - Filter Selection"] + #[inline(always)] + pub fn filtsel(&mut self) -> FILTSEL_W { + FILTSEL_W { w: self } + } + #[doc = "Bit 7 - Edge Selection"] + #[inline(always)] + pub fn edgesel(&mut self) -> EDGESEL_W { + EDGESEL_W { w: self } + } + #[doc = "Bits 8:11 - Input Selection 0"] + #[inline(always)] + pub fn insel0(&mut self) -> INSEL0_W { + INSEL0_W { w: self } + } + #[doc = "Bits 12:15 - Input Selection 1"] + #[inline(always)] + pub fn insel1(&mut self) -> INSEL1_W { + INSEL1_W { w: self } + } + #[doc = "Bits 16:19 - Input Selection 2"] + #[inline(always)] + pub fn insel2(&mut self) -> INSEL2_W { + INSEL2_W { w: self } + } + #[doc = "Bit 20 - Input Event Invert"] + #[inline(always)] + pub fn invei(&mut self) -> INVEI_W { + INVEI_W { w: self } + } + #[doc = "Bit 21 - Event Input Enable"] + #[inline(always)] + pub fn lutei(&mut self) -> LUTEI_W { + LUTEI_W { w: self } + } + #[doc = "Bit 22 - Event Output Enable"] + #[inline(always)] + pub fn luteo(&mut self) -> LUTEO_W { + LUTEO_W { w: self } + } + #[doc = "Bits 24:31 - Truth Value"] + #[inline(always)] + pub fn truth(&mut self) -> TRUTH_W { + TRUTH_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "LUT Control x\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lutctrl](index.html) module"] +pub struct LUTCTRL_SPEC; +impl crate::RegisterSpec for LUTCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [lutctrl::R](R) reader structure"] +impl crate::Readable for LUTCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [lutctrl::W](W) writer structure"] +impl crate::Writable for LUTCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets LUTCTRL[%s] +to value 0"] +impl crate::Resettable for LUTCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/ccl/seqctrl.rs b/pac/atsamc20e/src/ccl/seqctrl.rs new file mode 100644 index 000000000000..e2597a1042f3 --- /dev/null +++ b/pac/atsamc20e/src/ccl/seqctrl.rs @@ -0,0 +1,192 @@ +#[doc = "Register `SEQCTRL[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SEQCTRL[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Sequential Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SEQSEL_A { + #[doc = "0: Sequential logic is disabled"] + DISABLE = 0, + #[doc = "1: D flip flop"] + DFF = 1, + #[doc = "2: JK flip flop"] + JK = 2, + #[doc = "3: D latch"] + LATCH = 3, + #[doc = "4: RS latch"] + RS = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEQSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `SEQSEL` reader - Sequential Selection"] +pub struct SEQSEL_R(crate::FieldReader); +impl SEQSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SEQSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEQSEL_A::DISABLE), + 1 => Some(SEQSEL_A::DFF), + 2 => Some(SEQSEL_A::JK), + 3 => Some(SEQSEL_A::LATCH), + 4 => Some(SEQSEL_A::RS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == SEQSEL_A::DISABLE + } + #[doc = "Checks if the value of the field is `DFF`"] + #[inline(always)] + pub fn is_dff(&self) -> bool { + **self == SEQSEL_A::DFF + } + #[doc = "Checks if the value of the field is `JK`"] + #[inline(always)] + pub fn is_jk(&self) -> bool { + **self == SEQSEL_A::JK + } + #[doc = "Checks if the value of the field is `LATCH`"] + #[inline(always)] + pub fn is_latch(&self) -> bool { + **self == SEQSEL_A::LATCH + } + #[doc = "Checks if the value of the field is `RS`"] + #[inline(always)] + pub fn is_rs(&self) -> bool { + **self == SEQSEL_A::RS + } +} +impl core::ops::Deref for SEQSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEQSEL` writer - Sequential Selection"] +pub struct SEQSEL_W<'a> { + w: &'a mut W, +} +impl<'a> SEQSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SEQSEL_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Sequential logic is disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(SEQSEL_A::DISABLE) + } + #[doc = "D flip flop"] + #[inline(always)] + pub fn dff(self) -> &'a mut W { + self.variant(SEQSEL_A::DFF) + } + #[doc = "JK flip flop"] + #[inline(always)] + pub fn jk(self) -> &'a mut W { + self.variant(SEQSEL_A::JK) + } + #[doc = "D latch"] + #[inline(always)] + pub fn latch(self) -> &'a mut W { + self.variant(SEQSEL_A::LATCH) + } + #[doc = "RS latch"] + #[inline(always)] + pub fn rs(self) -> &'a mut W { + self.variant(SEQSEL_A::RS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Sequential Selection"] + #[inline(always)] + pub fn seqsel(&self) -> SEQSEL_R { + SEQSEL_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Sequential Selection"] + #[inline(always)] + pub fn seqsel(&mut self) -> SEQSEL_W { + SEQSEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SEQ Control x\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [seqctrl](index.html) module"] +pub struct SEQCTRL_SPEC; +impl crate::RegisterSpec for SEQCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [seqctrl::R](R) reader structure"] +impl crate::Readable for SEQCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [seqctrl::W](W) writer structure"] +impl crate::Writable for SEQCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SEQCTRL[%s] +to value 0"] +impl crate::Resettable for SEQCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/divas.rs b/pac/atsamc20e/src/divas.rs new file mode 100644 index 000000000000..dbc2f5f226da --- /dev/null +++ b/pac/atsamc20e/src/divas.rs @@ -0,0 +1,48 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrla: crate::Reg, + _reserved1: [u8; 0x03], + #[doc = "0x04 - Status"] + pub status: crate::Reg, + _reserved2: [u8; 0x03], + #[doc = "0x08 - Dividend"] + pub dividend: crate::Reg, + #[doc = "0x0c - Divisor"] + pub divisor: crate::Reg, + #[doc = "0x10 - Result"] + pub result: crate::Reg, + #[doc = "0x14 - Remainder"] + pub rem: crate::Reg, + #[doc = "0x18 - Square Root Input"] + pub sqrnum: crate::Reg, +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control"] +pub mod ctrla; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "DIVIDEND register accessor: an alias for `Reg`"] +pub type DIVIDEND = crate::Reg; +#[doc = "Dividend"] +pub mod dividend; +#[doc = "DIVISOR register accessor: an alias for `Reg`"] +pub type DIVISOR = crate::Reg; +#[doc = "Divisor"] +pub mod divisor; +#[doc = "RESULT register accessor: an alias for `Reg`"] +pub type RESULT = crate::Reg; +#[doc = "Result"] +pub mod result; +#[doc = "REM register accessor: an alias for `Reg`"] +pub type REM = crate::Reg; +#[doc = "Remainder"] +pub mod rem; +#[doc = "SQRNUM register accessor: an alias for `Reg`"] +pub type SQRNUM = crate::Reg; +#[doc = "Square Root Input"] +pub mod sqrnum; diff --git a/pac/atsamc20e/src/divas/ctrla.rs b/pac/atsamc20e/src/divas/ctrla.rs new file mode 100644 index 000000000000..7f79349da05c --- /dev/null +++ b/pac/atsamc20e/src/divas/ctrla.rs @@ -0,0 +1,160 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SIGNED` reader - Signed"] +pub struct SIGNED_R(crate::FieldReader); +impl SIGNED_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SIGNED_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SIGNED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SIGNED` writer - Signed"] +pub struct SIGNED_W<'a> { + w: &'a mut W, +} +impl<'a> SIGNED_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `DLZ` reader - Disable Leading Zero Optimization"] +pub struct DLZ_R(crate::FieldReader); +impl DLZ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DLZ_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DLZ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DLZ` writer - Disable Leading Zero Optimization"] +pub struct DLZ_W<'a> { + w: &'a mut W, +} +impl<'a> DLZ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - Signed"] + #[inline(always)] + pub fn signed(&self) -> SIGNED_R { + SIGNED_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Disable Leading Zero Optimization"] + #[inline(always)] + pub fn dlz(&self) -> DLZ_R { + DLZ_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Signed"] + #[inline(always)] + pub fn signed(&mut self) -> SIGNED_W { + SIGNED_W { w: self } + } + #[doc = "Bit 1 - Disable Leading Zero Optimization"] + #[inline(always)] + pub fn dlz(&mut self) -> DLZ_W { + DLZ_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/divas/dividend.rs b/pac/atsamc20e/src/divas/dividend.rs new file mode 100644 index 000000000000..215f44261a6c --- /dev/null +++ b/pac/atsamc20e/src/divas/dividend.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DIVIDEND` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIVIDEND` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIVIDEND` reader - DIVIDEND"] +pub struct DIVIDEND_R(crate::FieldReader); +impl DIVIDEND_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + DIVIDEND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIVIDEND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIVIDEND` writer - DIVIDEND"] +pub struct DIVIDEND_W<'a> { + w: &'a mut W, +} +impl<'a> DIVIDEND_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - DIVIDEND"] + #[inline(always)] + pub fn dividend(&self) -> DIVIDEND_R { + DIVIDEND_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - DIVIDEND"] + #[inline(always)] + pub fn dividend(&mut self) -> DIVIDEND_W { + DIVIDEND_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Dividend\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dividend](index.html) module"] +pub struct DIVIDEND_SPEC; +impl crate::RegisterSpec for DIVIDEND_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dividend::R](R) reader structure"] +impl crate::Readable for DIVIDEND_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dividend::W](W) writer structure"] +impl crate::Writable for DIVIDEND_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DIVIDEND to value 0"] +impl crate::Resettable for DIVIDEND_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/divas/divisor.rs b/pac/atsamc20e/src/divas/divisor.rs new file mode 100644 index 000000000000..b711870a5cd6 --- /dev/null +++ b/pac/atsamc20e/src/divas/divisor.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DIVISOR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIVISOR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIVISOR` reader - DIVISOR"] +pub struct DIVISOR_R(crate::FieldReader); +impl DIVISOR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + DIVISOR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIVISOR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIVISOR` writer - DIVISOR"] +pub struct DIVISOR_W<'a> { + w: &'a mut W, +} +impl<'a> DIVISOR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - DIVISOR"] + #[inline(always)] + pub fn divisor(&self) -> DIVISOR_R { + DIVISOR_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - DIVISOR"] + #[inline(always)] + pub fn divisor(&mut self) -> DIVISOR_W { + DIVISOR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Divisor\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [divisor](index.html) module"] +pub struct DIVISOR_SPEC; +impl crate::RegisterSpec for DIVISOR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [divisor::R](R) reader structure"] +impl crate::Readable for DIVISOR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [divisor::W](W) writer structure"] +impl crate::Writable for DIVISOR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DIVISOR to value 0"] +impl crate::Resettable for DIVISOR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/divas/rem.rs b/pac/atsamc20e/src/divas/rem.rs new file mode 100644 index 000000000000..76f3a90878ed --- /dev/null +++ b/pac/atsamc20e/src/divas/rem.rs @@ -0,0 +1,53 @@ +#[doc = "Register `REM` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `REM` reader - REM"] +pub struct REM_R(crate::FieldReader); +impl REM_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + REM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - REM"] + #[inline(always)] + pub fn rem(&self) -> REM_R { + REM_R::new(self.bits as u32) + } +} +#[doc = "Remainder\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rem](index.html) module"] +pub struct REM_SPEC; +impl crate::RegisterSpec for REM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rem::R](R) reader structure"] +impl crate::Readable for REM_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets REM to value 0"] +impl crate::Resettable for REM_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/divas/result.rs b/pac/atsamc20e/src/divas/result.rs new file mode 100644 index 000000000000..85fc1a025f9e --- /dev/null +++ b/pac/atsamc20e/src/divas/result.rs @@ -0,0 +1,53 @@ +#[doc = "Register `RESULT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `RESULT` reader - RESULT"] +pub struct RESULT_R(crate::FieldReader); +impl RESULT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + RESULT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESULT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - RESULT"] + #[inline(always)] + pub fn result(&self) -> RESULT_R { + RESULT_R::new(self.bits as u32) + } +} +#[doc = "Result\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [result](index.html) module"] +pub struct RESULT_SPEC; +impl crate::RegisterSpec for RESULT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [result::R](R) reader structure"] +impl crate::Readable for RESULT_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets RESULT to value 0"] +impl crate::Resettable for RESULT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/divas/sqrnum.rs b/pac/atsamc20e/src/divas/sqrnum.rs new file mode 100644 index 000000000000..cc0ce6806beb --- /dev/null +++ b/pac/atsamc20e/src/divas/sqrnum.rs @@ -0,0 +1,103 @@ +#[doc = "Register `SQRNUM` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SQRNUM` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SQRNUM` reader - Square Root Input"] +pub struct SQRNUM_R(crate::FieldReader); +impl SQRNUM_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + SQRNUM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SQRNUM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SQRNUM` writer - Square Root Input"] +pub struct SQRNUM_W<'a> { + w: &'a mut W, +} +impl<'a> SQRNUM_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Square Root Input"] + #[inline(always)] + pub fn sqrnum(&self) -> SQRNUM_R { + SQRNUM_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Square Root Input"] + #[inline(always)] + pub fn sqrnum(&mut self) -> SQRNUM_W { + SQRNUM_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Square Root Input\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sqrnum](index.html) module"] +pub struct SQRNUM_SPEC; +impl crate::RegisterSpec for SQRNUM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [sqrnum::R](R) reader structure"] +impl crate::Readable for SQRNUM_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [sqrnum::W](W) writer structure"] +impl crate::Writable for SQRNUM_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SQRNUM to value 0"] +impl crate::Resettable for SQRNUM_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/divas/status.rs b/pac/atsamc20e/src/divas/status.rs new file mode 100644 index 000000000000..feffbccec659 --- /dev/null +++ b/pac/atsamc20e/src/divas/status.rs @@ -0,0 +1,160 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BUSY` reader - DIVAS Accelerator Busy"] +pub struct BUSY_R(crate::FieldReader); +impl BUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSY` writer - DIVAS Accelerator Busy"] +pub struct BUSY_W<'a> { + w: &'a mut W, +} +impl<'a> BUSY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `DBZ` reader - Writing a one to this bit clears DBZ to zero"] +pub struct DBZ_R(crate::FieldReader); +impl DBZ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBZ_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBZ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBZ` writer - Writing a one to this bit clears DBZ to zero"] +pub struct DBZ_W<'a> { + w: &'a mut W, +} +impl<'a> DBZ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - DIVAS Accelerator Busy"] + #[inline(always)] + pub fn busy(&self) -> BUSY_R { + BUSY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Writing a one to this bit clears DBZ to zero"] + #[inline(always)] + pub fn dbz(&self) -> DBZ_R { + DBZ_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - DIVAS Accelerator Busy"] + #[inline(always)] + pub fn busy(&mut self) -> BUSY_W { + BUSY_W { w: self } + } + #[doc = "Bit 1 - Writing a one to this bit clears DBZ to zero"] + #[inline(always)] + pub fn dbz(&mut self) -> DBZ_W { + DBZ_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/dmac.rs b/pac/atsamc20e/src/dmac.rs new file mode 100644 index 000000000000..c23d36697550 --- /dev/null +++ b/pac/atsamc20e/src/dmac.rs @@ -0,0 +1,148 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrl: crate::Reg, + #[doc = "0x02 - CRC Control"] + pub crcctrl: crate::Reg, + #[doc = "0x04 - CRC Data Input"] + pub crcdatain: crate::Reg, + #[doc = "0x08 - CRC Checksum"] + pub crcchksum: crate::Reg, + #[doc = "0x0c - CRC Status"] + pub crcstatus: crate::Reg, + #[doc = "0x0d - Debug Control"] + pub dbgctrl: crate::Reg, + #[doc = "0x0e - QOS Control"] + pub qosctrl: crate::Reg, + _reserved7: [u8; 0x01], + #[doc = "0x10 - Software Trigger Control"] + pub swtrigctrl: crate::Reg, + #[doc = "0x14 - Priority Control 0"] + pub prictrl0: crate::Reg, + _reserved9: [u8; 0x08], + #[doc = "0x20 - Interrupt Pending"] + pub intpend: crate::Reg, + _reserved10: [u8; 0x02], + #[doc = "0x24 - Interrupt Status"] + pub intstatus: crate::Reg, + #[doc = "0x28 - Busy Channels"] + pub busych: crate::Reg, + #[doc = "0x2c - Pending Channels"] + pub pendch: crate::Reg, + #[doc = "0x30 - Active Channel and Levels"] + pub active: crate::Reg, + #[doc = "0x34 - Descriptor Memory Section Base Address"] + pub baseaddr: crate::Reg, + #[doc = "0x38 - Write-Back Memory Section Base Address"] + pub wrbaddr: crate::Reg, + _reserved16: [u8; 0x03], + #[doc = "0x3f - Channel ID"] + pub chid: crate::Reg, + #[doc = "0x40 - Channel Control A"] + pub chctrla: crate::Reg, + _reserved18: [u8; 0x03], + #[doc = "0x44 - Channel Control B"] + pub chctrlb: crate::Reg, + _reserved19: [u8; 0x04], + #[doc = "0x4c - Channel Interrupt Enable Clear"] + pub chintenclr: crate::Reg, + #[doc = "0x4d - Channel Interrupt Enable Set"] + pub chintenset: crate::Reg, + #[doc = "0x4e - Channel Interrupt Flag Status and Clear"] + pub chintflag: crate::Reg, + #[doc = "0x4f - Channel Status"] + pub chstatus: crate::Reg, +} +#[doc = "CTRL register accessor: an alias for `Reg`"] +pub type CTRL = crate::Reg; +#[doc = "Control"] +pub mod ctrl; +#[doc = "CRCCTRL register accessor: an alias for `Reg`"] +pub type CRCCTRL = crate::Reg; +#[doc = "CRC Control"] +pub mod crcctrl; +#[doc = "CRCDATAIN register accessor: an alias for `Reg`"] +pub type CRCDATAIN = crate::Reg; +#[doc = "CRC Data Input"] +pub mod crcdatain; +#[doc = "CRCCHKSUM register accessor: an alias for `Reg`"] +pub type CRCCHKSUM = crate::Reg; +#[doc = "CRC Checksum"] +pub mod crcchksum; +#[doc = "CRCSTATUS register accessor: an alias for `Reg`"] +pub type CRCSTATUS = crate::Reg; +#[doc = "CRC Status"] +pub mod crcstatus; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "QOSCTRL register accessor: an alias for `Reg`"] +pub type QOSCTRL = crate::Reg; +#[doc = "QOS Control"] +pub mod qosctrl; +#[doc = "SWTRIGCTRL register accessor: an alias for `Reg`"] +pub type SWTRIGCTRL = crate::Reg; +#[doc = "Software Trigger Control"] +pub mod swtrigctrl; +#[doc = "PRICTRL0 register accessor: an alias for `Reg`"] +pub type PRICTRL0 = crate::Reg; +#[doc = "Priority Control 0"] +pub mod prictrl0; +#[doc = "INTPEND register accessor: an alias for `Reg`"] +pub type INTPEND = crate::Reg; +#[doc = "Interrupt Pending"] +pub mod intpend; +#[doc = "INTSTATUS register accessor: an alias for `Reg`"] +pub type INTSTATUS = crate::Reg; +#[doc = "Interrupt Status"] +pub mod intstatus; +#[doc = "BUSYCH register accessor: an alias for `Reg`"] +pub type BUSYCH = crate::Reg; +#[doc = "Busy Channels"] +pub mod busych; +#[doc = "PENDCH register accessor: an alias for `Reg`"] +pub type PENDCH = crate::Reg; +#[doc = "Pending Channels"] +pub mod pendch; +#[doc = "ACTIVE register accessor: an alias for `Reg`"] +pub type ACTIVE = crate::Reg; +#[doc = "Active Channel and Levels"] +pub mod active; +#[doc = "BASEADDR register accessor: an alias for `Reg`"] +pub type BASEADDR = crate::Reg; +#[doc = "Descriptor Memory Section Base Address"] +pub mod baseaddr; +#[doc = "WRBADDR register accessor: an alias for `Reg`"] +pub type WRBADDR = crate::Reg; +#[doc = "Write-Back Memory Section Base Address"] +pub mod wrbaddr; +#[doc = "CHID register accessor: an alias for `Reg`"] +pub type CHID = crate::Reg; +#[doc = "Channel ID"] +pub mod chid; +#[doc = "CHCTRLA register accessor: an alias for `Reg`"] +pub type CHCTRLA = crate::Reg; +#[doc = "Channel Control A"] +pub mod chctrla; +#[doc = "CHCTRLB register accessor: an alias for `Reg`"] +pub type CHCTRLB = crate::Reg; +#[doc = "Channel Control B"] +pub mod chctrlb; +#[doc = "CHINTENCLR register accessor: an alias for `Reg`"] +pub type CHINTENCLR = crate::Reg; +#[doc = "Channel Interrupt Enable Clear"] +pub mod chintenclr; +#[doc = "CHINTENSET register accessor: an alias for `Reg`"] +pub type CHINTENSET = crate::Reg; +#[doc = "Channel Interrupt Enable Set"] +pub mod chintenset; +#[doc = "CHINTFLAG register accessor: an alias for `Reg`"] +pub type CHINTFLAG = crate::Reg; +#[doc = "Channel Interrupt Flag Status and Clear"] +pub mod chintflag; +#[doc = "CHSTATUS register accessor: an alias for `Reg`"] +pub type CHSTATUS = crate::Reg; +#[doc = "Channel Status"] +pub mod chstatus; diff --git a/pac/atsamc20e/src/dmac/active.rs b/pac/atsamc20e/src/dmac/active.rs new file mode 100644 index 000000000000..c3cc5a0420bc --- /dev/null +++ b/pac/atsamc20e/src/dmac/active.rs @@ -0,0 +1,173 @@ +#[doc = "Register `ACTIVE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `LVLEX0` reader - Level 0 Channel Trigger Request Executing"] +pub struct LVLEX0_R(crate::FieldReader); +impl LVLEX0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LVLEX0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEX0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLEX1` reader - Level 1 Channel Trigger Request Executing"] +pub struct LVLEX1_R(crate::FieldReader); +impl LVLEX1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LVLEX1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEX1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLEX2` reader - Level 2 Channel Trigger Request Executing"] +pub struct LVLEX2_R(crate::FieldReader); +impl LVLEX2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LVLEX2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEX2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLEX3` reader - Level 3 Channel Trigger Request Executing"] +pub struct LVLEX3_R(crate::FieldReader); +impl LVLEX3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LVLEX3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEX3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ID` reader - Active Channel ID"] +pub struct ID_R(crate::FieldReader); +impl ID_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ID_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ID_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ABUSY` reader - Active Channel Busy"] +pub struct ABUSY_R(crate::FieldReader); +impl ABUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ABUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ABUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BTCNT` reader - Active Channel Block Transfer Count"] +pub struct BTCNT_R(crate::FieldReader); +impl BTCNT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BTCNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BTCNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Level 0 Channel Trigger Request Executing"] + #[inline(always)] + pub fn lvlex0(&self) -> LVLEX0_R { + LVLEX0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Level 1 Channel Trigger Request Executing"] + #[inline(always)] + pub fn lvlex1(&self) -> LVLEX1_R { + LVLEX1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Level 2 Channel Trigger Request Executing"] + #[inline(always)] + pub fn lvlex2(&self) -> LVLEX2_R { + LVLEX2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Level 3 Channel Trigger Request Executing"] + #[inline(always)] + pub fn lvlex3(&self) -> LVLEX3_R { + LVLEX3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bits 8:12 - Active Channel ID"] + #[inline(always)] + pub fn id(&self) -> ID_R { + ID_R::new(((self.bits >> 8) & 0x1f) as u8) + } + #[doc = "Bit 15 - Active Channel Busy"] + #[inline(always)] + pub fn abusy(&self) -> ABUSY_R { + ABUSY_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:31 - Active Channel Block Transfer Count"] + #[inline(always)] + pub fn btcnt(&self) -> BTCNT_R { + BTCNT_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[doc = "Active Channel and Levels\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [active](index.html) module"] +pub struct ACTIVE_SPEC; +impl crate::RegisterSpec for ACTIVE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [active::R](R) reader structure"] +impl crate::Readable for ACTIVE_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets ACTIVE to value 0"] +impl crate::Resettable for ACTIVE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/dmac/baseaddr.rs b/pac/atsamc20e/src/dmac/baseaddr.rs new file mode 100644 index 000000000000..cec8c8cf0777 --- /dev/null +++ b/pac/atsamc20e/src/dmac/baseaddr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `BASEADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BASEADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BASEADDR` reader - Descriptor Memory Base Address"] +pub struct BASEADDR_R(crate::FieldReader); +impl BASEADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + BASEADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BASEADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BASEADDR` writer - Descriptor Memory Base Address"] +pub struct BASEADDR_W<'a> { + w: &'a mut W, +} +impl<'a> BASEADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Descriptor Memory Base Address"] + #[inline(always)] + pub fn baseaddr(&self) -> BASEADDR_R { + BASEADDR_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Descriptor Memory Base Address"] + #[inline(always)] + pub fn baseaddr(&mut self) -> BASEADDR_W { + BASEADDR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Descriptor Memory Section Base Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baseaddr](index.html) module"] +pub struct BASEADDR_SPEC; +impl crate::RegisterSpec for BASEADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [baseaddr::R](R) reader structure"] +impl crate::Readable for BASEADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baseaddr::W](W) writer structure"] +impl crate::Writable for BASEADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BASEADDR to value 0"] +impl crate::Resettable for BASEADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/dmac/busych.rs b/pac/atsamc20e/src/dmac/busych.rs new file mode 100644 index 000000000000..68fdc5e3788b --- /dev/null +++ b/pac/atsamc20e/src/dmac/busych.rs @@ -0,0 +1,153 @@ +#[doc = "Register `BUSYCH` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `BUSYCH0` reader - Busy Channel 0"] +pub struct BUSYCH0_R(crate::FieldReader); +impl BUSYCH0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH1` reader - Busy Channel 1"] +pub struct BUSYCH1_R(crate::FieldReader); +impl BUSYCH1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH2` reader - Busy Channel 2"] +pub struct BUSYCH2_R(crate::FieldReader); +impl BUSYCH2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH3` reader - Busy Channel 3"] +pub struct BUSYCH3_R(crate::FieldReader); +impl BUSYCH3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH4` reader - Busy Channel 4"] +pub struct BUSYCH4_R(crate::FieldReader); +impl BUSYCH4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH5` reader - Busy Channel 5"] +pub struct BUSYCH5_R(crate::FieldReader); +impl BUSYCH5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Busy Channel 0"] + #[inline(always)] + pub fn busych0(&self) -> BUSYCH0_R { + BUSYCH0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Busy Channel 1"] + #[inline(always)] + pub fn busych1(&self) -> BUSYCH1_R { + BUSYCH1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Busy Channel 2"] + #[inline(always)] + pub fn busych2(&self) -> BUSYCH2_R { + BUSYCH2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Busy Channel 3"] + #[inline(always)] + pub fn busych3(&self) -> BUSYCH3_R { + BUSYCH3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Busy Channel 4"] + #[inline(always)] + pub fn busych4(&self) -> BUSYCH4_R { + BUSYCH4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Busy Channel 5"] + #[inline(always)] + pub fn busych5(&self) -> BUSYCH5_R { + BUSYCH5_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +#[doc = "Busy Channels\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [busych](index.html) module"] +pub struct BUSYCH_SPEC; +impl crate::RegisterSpec for BUSYCH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [busych::R](R) reader structure"] +impl crate::Readable for BUSYCH_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets BUSYCH to value 0"] +impl crate::Resettable for BUSYCH_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/dmac/chctrla.rs b/pac/atsamc20e/src/dmac/chctrla.rs new file mode 100644 index 000000000000..22e8d456e05c --- /dev/null +++ b/pac/atsamc20e/src/dmac/chctrla.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CHCTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHCTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Channel Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Channel Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Channel Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Channel Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Channel run in standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Channel run in standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - Channel Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 6 - Channel run in standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Channel Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 6 - Channel run in standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chctrla](index.html) module"] +pub struct CHCTRLA_SPEC; +impl crate::RegisterSpec for CHCTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [chctrla::R](R) reader structure"] +impl crate::Readable for CHCTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chctrla::W](W) writer structure"] +impl crate::Writable for CHCTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHCTRLA to value 0"] +impl crate::Resettable for CHCTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/dmac/chctrlb.rs b/pac/atsamc20e/src/dmac/chctrlb.rs new file mode 100644 index 000000000000..5dcbc1da26f1 --- /dev/null +++ b/pac/atsamc20e/src/dmac/chctrlb.rs @@ -0,0 +1,1188 @@ +#[doc = "Register `CHCTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHCTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Event Input Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EVACT_A { + #[doc = "0: No action"] + NOACT = 0, + #[doc = "1: Transfer and periodic transfer trigger"] + TRIG = 1, + #[doc = "2: Conditional transfer trigger"] + CTRIG = 2, + #[doc = "3: Conditional block transfer"] + CBLOCK = 3, + #[doc = "4: Channel suspend operation"] + SUSPEND = 4, + #[doc = "5: Channel resume operation"] + RESUME = 5, + #[doc = "6: Skip next block suspend action"] + SSKIP = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EVACT_A) -> Self { + variant as _ + } +} +#[doc = "Field `EVACT` reader - Event Input Action"] +pub struct EVACT_R(crate::FieldReader); +impl EVACT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(EVACT_A::NOACT), + 1 => Some(EVACT_A::TRIG), + 2 => Some(EVACT_A::CTRIG), + 3 => Some(EVACT_A::CBLOCK), + 4 => Some(EVACT_A::SUSPEND), + 5 => Some(EVACT_A::RESUME), + 6 => Some(EVACT_A::SSKIP), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NOACT`"] + #[inline(always)] + pub fn is_noact(&self) -> bool { + **self == EVACT_A::NOACT + } + #[doc = "Checks if the value of the field is `TRIG`"] + #[inline(always)] + pub fn is_trig(&self) -> bool { + **self == EVACT_A::TRIG + } + #[doc = "Checks if the value of the field is `CTRIG`"] + #[inline(always)] + pub fn is_ctrig(&self) -> bool { + **self == EVACT_A::CTRIG + } + #[doc = "Checks if the value of the field is `CBLOCK`"] + #[inline(always)] + pub fn is_cblock(&self) -> bool { + **self == EVACT_A::CBLOCK + } + #[doc = "Checks if the value of the field is `SUSPEND`"] + #[inline(always)] + pub fn is_suspend(&self) -> bool { + **self == EVACT_A::SUSPEND + } + #[doc = "Checks if the value of the field is `RESUME`"] + #[inline(always)] + pub fn is_resume(&self) -> bool { + **self == EVACT_A::RESUME + } + #[doc = "Checks if the value of the field is `SSKIP`"] + #[inline(always)] + pub fn is_sskip(&self) -> bool { + **self == EVACT_A::SSKIP + } +} +impl core::ops::Deref for EVACT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT` writer - Event Input Action"] +pub struct EVACT_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EVACT_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn noact(self) -> &'a mut W { + self.variant(EVACT_A::NOACT) + } + #[doc = "Transfer and periodic transfer trigger"] + #[inline(always)] + pub fn trig(self) -> &'a mut W { + self.variant(EVACT_A::TRIG) + } + #[doc = "Conditional transfer trigger"] + #[inline(always)] + pub fn ctrig(self) -> &'a mut W { + self.variant(EVACT_A::CTRIG) + } + #[doc = "Conditional block transfer"] + #[inline(always)] + pub fn cblock(self) -> &'a mut W { + self.variant(EVACT_A::CBLOCK) + } + #[doc = "Channel suspend operation"] + #[inline(always)] + pub fn suspend(self) -> &'a mut W { + self.variant(EVACT_A::SUSPEND) + } + #[doc = "Channel resume operation"] + #[inline(always)] + pub fn resume(self) -> &'a mut W { + self.variant(EVACT_A::RESUME) + } + #[doc = "Skip next block suspend action"] + #[inline(always)] + pub fn sskip(self) -> &'a mut W { + self.variant(EVACT_A::SSKIP) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Field `EVIE` reader - Channel Event Input Enable"] +pub struct EVIE_R(crate::FieldReader); +impl EVIE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVIE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVIE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVIE` writer - Channel Event Input Enable"] +pub struct EVIE_W<'a> { + w: &'a mut W, +} +impl<'a> EVIE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `EVOE` reader - Channel Event Output Enable"] +pub struct EVOE_R(crate::FieldReader); +impl EVOE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVOE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVOE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVOE` writer - Channel Event Output Enable"] +pub struct EVOE_W<'a> { + w: &'a mut W, +} +impl<'a> EVOE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Channel Arbitration Level\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum LVL_A { + #[doc = "0: Channel Priority Level 0"] + LVL0 = 0, + #[doc = "1: Channel Priority Level 1"] + LVL1 = 1, + #[doc = "2: Channel Priority Level 2"] + LVL2 = 2, + #[doc = "3: Channel Priority Level 3"] + LVL3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LVL_A) -> Self { + variant as _ + } +} +#[doc = "Field `LVL` reader - Channel Arbitration Level"] +pub struct LVL_R(crate::FieldReader); +impl LVL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LVL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> LVL_A { + match self.bits { + 0 => LVL_A::LVL0, + 1 => LVL_A::LVL1, + 2 => LVL_A::LVL2, + 3 => LVL_A::LVL3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `LVL0`"] + #[inline(always)] + pub fn is_lvl0(&self) -> bool { + **self == LVL_A::LVL0 + } + #[doc = "Checks if the value of the field is `LVL1`"] + #[inline(always)] + pub fn is_lvl1(&self) -> bool { + **self == LVL_A::LVL1 + } + #[doc = "Checks if the value of the field is `LVL2`"] + #[inline(always)] + pub fn is_lvl2(&self) -> bool { + **self == LVL_A::LVL2 + } + #[doc = "Checks if the value of the field is `LVL3`"] + #[inline(always)] + pub fn is_lvl3(&self) -> bool { + **self == LVL_A::LVL3 + } +} +impl core::ops::Deref for LVL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVL` writer - Channel Arbitration Level"] +pub struct LVL_W<'a> { + w: &'a mut W, +} +impl<'a> LVL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: LVL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Channel Priority Level 0"] + #[inline(always)] + pub fn lvl0(self) -> &'a mut W { + self.variant(LVL_A::LVL0) + } + #[doc = "Channel Priority Level 1"] + #[inline(always)] + pub fn lvl1(self) -> &'a mut W { + self.variant(LVL_A::LVL1) + } + #[doc = "Channel Priority Level 2"] + #[inline(always)] + pub fn lvl2(self) -> &'a mut W { + self.variant(LVL_A::LVL2) + } + #[doc = "Channel Priority Level 3"] + #[inline(always)] + pub fn lvl3(self) -> &'a mut W { + self.variant(LVL_A::LVL3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 5)) | ((value as u32 & 0x03) << 5); + self.w + } +} +#[doc = "Trigger Source\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum TRIGSRC_A { + #[doc = "0: Only software/event triggers"] + DISABLE = 0, + #[doc = "2: SERCOM0 RX Trigger"] + SERCOM0_RX = 2, + #[doc = "3: SERCOM0 TX Trigger"] + SERCOM0_TX = 3, + #[doc = "4: SERCOM1 RX Trigger"] + SERCOM1_RX = 4, + #[doc = "5: SERCOM1 TX Trigger"] + SERCOM1_TX = 5, + #[doc = "6: SERCOM2 RX Trigger"] + SERCOM2_RX = 6, + #[doc = "7: SERCOM2 TX Trigger"] + SERCOM2_TX = 7, + #[doc = "8: SERCOM3 RX Trigger"] + SERCOM3_RX = 8, + #[doc = "9: SERCOM3 TX Trigger"] + SERCOM3_TX = 9, + #[doc = "16: TCC0 Overflow Trigger"] + TCC0_OVF = 16, + #[doc = "17: TCC0 Match/Compare 0 Trigger"] + TCC0_MC0 = 17, + #[doc = "18: TCC0 Match/Compare 1 Trigger"] + TCC0_MC1 = 18, + #[doc = "19: TCC0 Match/Compare 2 Trigger"] + TCC0_MC2 = 19, + #[doc = "20: TCC0 Match/Compare 3 Trigger"] + TCC0_MC3 = 20, + #[doc = "21: TCC1 Overflow Trigger"] + TCC1_OVF = 21, + #[doc = "22: TCC1 Match/Compare 0 Trigger"] + TCC1_MC0 = 22, + #[doc = "23: TCC1 Match/Compare 1 Trigger"] + TCC1_MC1 = 23, + #[doc = "24: TCC2 Overflow Trigger"] + TCC2_OVF = 24, + #[doc = "25: TCC2 Match/Compare 0 Trigger"] + TCC2_MC0 = 25, + #[doc = "26: TCC2 Match/Compare 1 Trigger"] + TCC2_MC1 = 26, + #[doc = "27: TC0 Overflow Trigger"] + TC0_OVF = 27, + #[doc = "28: TC0 Match/Compare 0 Trigger"] + TC0_MC0 = 28, + #[doc = "29: TC0 Match/Compare 1 Trigger"] + TC0_MC1 = 29, + #[doc = "30: TC1 Overflow Trigger"] + TC1_OVF = 30, + #[doc = "31: TC1 Match/Compare 0 Trigger"] + TC1_MC0 = 31, + #[doc = "32: TC1 Match/Compare 1 Trigger"] + TC1_MC1 = 32, + #[doc = "33: TC2 Overflow Trigger"] + TC2_OVF = 33, + #[doc = "34: TC2 Match/Compare 0 Trigger"] + TC2_MC0 = 34, + #[doc = "35: TC2 Match/Compare 1 Trigger"] + TC2_MC1 = 35, + #[doc = "36: TC3 Overflow Trigger"] + TC3_OVF = 36, + #[doc = "37: TC3 Match/Compare 0 Trigger"] + TC3_MC0 = 37, + #[doc = "38: TC3 Match/Compare 1 Trigger"] + TC3_MC1 = 38, + #[doc = "39: TC4 Overflow Trigger"] + TC4_OVF = 39, + #[doc = "40: TC4 Match/Compare 0 Trigger"] + TC4_MC0 = 40, + #[doc = "41: TC4 Match/Compare 1 Trigger"] + TC4_MC1 = 41, + #[doc = "42: ADC0 Result Ready Trigger"] + ADC0_RESRDY = 42, + #[doc = "46: PTC End of Conversion Trigger"] + PTC_EOC = 46, + #[doc = "47: PTC Window Compare Trigger"] + PTC_WCOMP = 47, + #[doc = "48: PTC Sequence Trigger"] + PTC_SEQ = 48, +} +impl From for u8 { + #[inline(always)] + fn from(variant: TRIGSRC_A) -> Self { + variant as _ + } +} +#[doc = "Field `TRIGSRC` reader - Trigger Source"] +pub struct TRIGSRC_R(crate::FieldReader); +impl TRIGSRC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TRIGSRC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(TRIGSRC_A::DISABLE), + 2 => Some(TRIGSRC_A::SERCOM0_RX), + 3 => Some(TRIGSRC_A::SERCOM0_TX), + 4 => Some(TRIGSRC_A::SERCOM1_RX), + 5 => Some(TRIGSRC_A::SERCOM1_TX), + 6 => Some(TRIGSRC_A::SERCOM2_RX), + 7 => Some(TRIGSRC_A::SERCOM2_TX), + 8 => Some(TRIGSRC_A::SERCOM3_RX), + 9 => Some(TRIGSRC_A::SERCOM3_TX), + 16 => Some(TRIGSRC_A::TCC0_OVF), + 17 => Some(TRIGSRC_A::TCC0_MC0), + 18 => Some(TRIGSRC_A::TCC0_MC1), + 19 => Some(TRIGSRC_A::TCC0_MC2), + 20 => Some(TRIGSRC_A::TCC0_MC3), + 21 => Some(TRIGSRC_A::TCC1_OVF), + 22 => Some(TRIGSRC_A::TCC1_MC0), + 23 => Some(TRIGSRC_A::TCC1_MC1), + 24 => Some(TRIGSRC_A::TCC2_OVF), + 25 => Some(TRIGSRC_A::TCC2_MC0), + 26 => Some(TRIGSRC_A::TCC2_MC1), + 27 => Some(TRIGSRC_A::TC0_OVF), + 28 => Some(TRIGSRC_A::TC0_MC0), + 29 => Some(TRIGSRC_A::TC0_MC1), + 30 => Some(TRIGSRC_A::TC1_OVF), + 31 => Some(TRIGSRC_A::TC1_MC0), + 32 => Some(TRIGSRC_A::TC1_MC1), + 33 => Some(TRIGSRC_A::TC2_OVF), + 34 => Some(TRIGSRC_A::TC2_MC0), + 35 => Some(TRIGSRC_A::TC2_MC1), + 36 => Some(TRIGSRC_A::TC3_OVF), + 37 => Some(TRIGSRC_A::TC3_MC0), + 38 => Some(TRIGSRC_A::TC3_MC1), + 39 => Some(TRIGSRC_A::TC4_OVF), + 40 => Some(TRIGSRC_A::TC4_MC0), + 41 => Some(TRIGSRC_A::TC4_MC1), + 42 => Some(TRIGSRC_A::ADC0_RESRDY), + 46 => Some(TRIGSRC_A::PTC_EOC), + 47 => Some(TRIGSRC_A::PTC_WCOMP), + 48 => Some(TRIGSRC_A::PTC_SEQ), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == TRIGSRC_A::DISABLE + } + #[doc = "Checks if the value of the field is `SERCOM0_RX`"] + #[inline(always)] + pub fn is_sercom0_rx(&self) -> bool { + **self == TRIGSRC_A::SERCOM0_RX + } + #[doc = "Checks if the value of the field is `SERCOM0_TX`"] + #[inline(always)] + pub fn is_sercom0_tx(&self) -> bool { + **self == TRIGSRC_A::SERCOM0_TX + } + #[doc = "Checks if the value of the field is `SERCOM1_RX`"] + #[inline(always)] + pub fn is_sercom1_rx(&self) -> bool { + **self == TRIGSRC_A::SERCOM1_RX + } + #[doc = "Checks if the value of the field is `SERCOM1_TX`"] + #[inline(always)] + pub fn is_sercom1_tx(&self) -> bool { + **self == TRIGSRC_A::SERCOM1_TX + } + #[doc = "Checks if the value of the field is `SERCOM2_RX`"] + #[inline(always)] + pub fn is_sercom2_rx(&self) -> bool { + **self == TRIGSRC_A::SERCOM2_RX + } + #[doc = "Checks if the value of the field is `SERCOM2_TX`"] + #[inline(always)] + pub fn is_sercom2_tx(&self) -> bool { + **self == TRIGSRC_A::SERCOM2_TX + } + #[doc = "Checks if the value of the field is `SERCOM3_RX`"] + #[inline(always)] + pub fn is_sercom3_rx(&self) -> bool { + **self == TRIGSRC_A::SERCOM3_RX + } + #[doc = "Checks if the value of the field is `SERCOM3_TX`"] + #[inline(always)] + pub fn is_sercom3_tx(&self) -> bool { + **self == TRIGSRC_A::SERCOM3_TX + } + #[doc = "Checks if the value of the field is `TCC0_OVF`"] + #[inline(always)] + pub fn is_tcc0_ovf(&self) -> bool { + **self == TRIGSRC_A::TCC0_OVF + } + #[doc = "Checks if the value of the field is `TCC0_MC0`"] + #[inline(always)] + pub fn is_tcc0_mc0(&self) -> bool { + **self == TRIGSRC_A::TCC0_MC0 + } + #[doc = "Checks if the value of the field is `TCC0_MC1`"] + #[inline(always)] + pub fn is_tcc0_mc1(&self) -> bool { + **self == TRIGSRC_A::TCC0_MC1 + } + #[doc = "Checks if the value of the field is `TCC0_MC2`"] + #[inline(always)] + pub fn is_tcc0_mc2(&self) -> bool { + **self == TRIGSRC_A::TCC0_MC2 + } + #[doc = "Checks if the value of the field is `TCC0_MC3`"] + #[inline(always)] + pub fn is_tcc0_mc3(&self) -> bool { + **self == TRIGSRC_A::TCC0_MC3 + } + #[doc = "Checks if the value of the field is `TCC1_OVF`"] + #[inline(always)] + pub fn is_tcc1_ovf(&self) -> bool { + **self == TRIGSRC_A::TCC1_OVF + } + #[doc = "Checks if the value of the field is `TCC1_MC0`"] + #[inline(always)] + pub fn is_tcc1_mc0(&self) -> bool { + **self == TRIGSRC_A::TCC1_MC0 + } + #[doc = "Checks if the value of the field is `TCC1_MC1`"] + #[inline(always)] + pub fn is_tcc1_mc1(&self) -> bool { + **self == TRIGSRC_A::TCC1_MC1 + } + #[doc = "Checks if the value of the field is `TCC2_OVF`"] + #[inline(always)] + pub fn is_tcc2_ovf(&self) -> bool { + **self == TRIGSRC_A::TCC2_OVF + } + #[doc = "Checks if the value of the field is `TCC2_MC0`"] + #[inline(always)] + pub fn is_tcc2_mc0(&self) -> bool { + **self == TRIGSRC_A::TCC2_MC0 + } + #[doc = "Checks if the value of the field is `TCC2_MC1`"] + #[inline(always)] + pub fn is_tcc2_mc1(&self) -> bool { + **self == TRIGSRC_A::TCC2_MC1 + } + #[doc = "Checks if the value of the field is `TC0_OVF`"] + #[inline(always)] + pub fn is_tc0_ovf(&self) -> bool { + **self == TRIGSRC_A::TC0_OVF + } + #[doc = "Checks if the value of the field is `TC0_MC0`"] + #[inline(always)] + pub fn is_tc0_mc0(&self) -> bool { + **self == TRIGSRC_A::TC0_MC0 + } + #[doc = "Checks if the value of the field is `TC0_MC1`"] + #[inline(always)] + pub fn is_tc0_mc1(&self) -> bool { + **self == TRIGSRC_A::TC0_MC1 + } + #[doc = "Checks if the value of the field is `TC1_OVF`"] + #[inline(always)] + pub fn is_tc1_ovf(&self) -> bool { + **self == TRIGSRC_A::TC1_OVF + } + #[doc = "Checks if the value of the field is `TC1_MC0`"] + #[inline(always)] + pub fn is_tc1_mc0(&self) -> bool { + **self == TRIGSRC_A::TC1_MC0 + } + #[doc = "Checks if the value of the field is `TC1_MC1`"] + #[inline(always)] + pub fn is_tc1_mc1(&self) -> bool { + **self == TRIGSRC_A::TC1_MC1 + } + #[doc = "Checks if the value of the field is `TC2_OVF`"] + #[inline(always)] + pub fn is_tc2_ovf(&self) -> bool { + **self == TRIGSRC_A::TC2_OVF + } + #[doc = "Checks if the value of the field is `TC2_MC0`"] + #[inline(always)] + pub fn is_tc2_mc0(&self) -> bool { + **self == TRIGSRC_A::TC2_MC0 + } + #[doc = "Checks if the value of the field is `TC2_MC1`"] + #[inline(always)] + pub fn is_tc2_mc1(&self) -> bool { + **self == TRIGSRC_A::TC2_MC1 + } + #[doc = "Checks if the value of the field is `TC3_OVF`"] + #[inline(always)] + pub fn is_tc3_ovf(&self) -> bool { + **self == TRIGSRC_A::TC3_OVF + } + #[doc = "Checks if the value of the field is `TC3_MC0`"] + #[inline(always)] + pub fn is_tc3_mc0(&self) -> bool { + **self == TRIGSRC_A::TC3_MC0 + } + #[doc = "Checks if the value of the field is `TC3_MC1`"] + #[inline(always)] + pub fn is_tc3_mc1(&self) -> bool { + **self == TRIGSRC_A::TC3_MC1 + } + #[doc = "Checks if the value of the field is `TC4_OVF`"] + #[inline(always)] + pub fn is_tc4_ovf(&self) -> bool { + **self == TRIGSRC_A::TC4_OVF + } + #[doc = "Checks if the value of the field is `TC4_MC0`"] + #[inline(always)] + pub fn is_tc4_mc0(&self) -> bool { + **self == TRIGSRC_A::TC4_MC0 + } + #[doc = "Checks if the value of the field is `TC4_MC1`"] + #[inline(always)] + pub fn is_tc4_mc1(&self) -> bool { + **self == TRIGSRC_A::TC4_MC1 + } + #[doc = "Checks if the value of the field is `ADC0_RESRDY`"] + #[inline(always)] + pub fn is_adc0_resrdy(&self) -> bool { + **self == TRIGSRC_A::ADC0_RESRDY + } + #[doc = "Checks if the value of the field is `PTC_EOC`"] + #[inline(always)] + pub fn is_ptc_eoc(&self) -> bool { + **self == TRIGSRC_A::PTC_EOC + } + #[doc = "Checks if the value of the field is `PTC_WCOMP`"] + #[inline(always)] + pub fn is_ptc_wcomp(&self) -> bool { + **self == TRIGSRC_A::PTC_WCOMP + } + #[doc = "Checks if the value of the field is `PTC_SEQ`"] + #[inline(always)] + pub fn is_ptc_seq(&self) -> bool { + **self == TRIGSRC_A::PTC_SEQ + } +} +impl core::ops::Deref for TRIGSRC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRIGSRC` writer - Trigger Source"] +pub struct TRIGSRC_W<'a> { + w: &'a mut W, +} +impl<'a> TRIGSRC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TRIGSRC_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Only software/event triggers"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(TRIGSRC_A::DISABLE) + } + #[doc = "SERCOM0 RX Trigger"] + #[inline(always)] + pub fn sercom0_rx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM0_RX) + } + #[doc = "SERCOM0 TX Trigger"] + #[inline(always)] + pub fn sercom0_tx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM0_TX) + } + #[doc = "SERCOM1 RX Trigger"] + #[inline(always)] + pub fn sercom1_rx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM1_RX) + } + #[doc = "SERCOM1 TX Trigger"] + #[inline(always)] + pub fn sercom1_tx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM1_TX) + } + #[doc = "SERCOM2 RX Trigger"] + #[inline(always)] + pub fn sercom2_rx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM2_RX) + } + #[doc = "SERCOM2 TX Trigger"] + #[inline(always)] + pub fn sercom2_tx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM2_TX) + } + #[doc = "SERCOM3 RX Trigger"] + #[inline(always)] + pub fn sercom3_rx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM3_RX) + } + #[doc = "SERCOM3 TX Trigger"] + #[inline(always)] + pub fn sercom3_tx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM3_TX) + } + #[doc = "TCC0 Overflow Trigger"] + #[inline(always)] + pub fn tcc0_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC0_OVF) + } + #[doc = "TCC0 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tcc0_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC0_MC0) + } + #[doc = "TCC0 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tcc0_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC0_MC1) + } + #[doc = "TCC0 Match/Compare 2 Trigger"] + #[inline(always)] + pub fn tcc0_mc2(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC0_MC2) + } + #[doc = "TCC0 Match/Compare 3 Trigger"] + #[inline(always)] + pub fn tcc0_mc3(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC0_MC3) + } + #[doc = "TCC1 Overflow Trigger"] + #[inline(always)] + pub fn tcc1_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC1_OVF) + } + #[doc = "TCC1 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tcc1_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC1_MC0) + } + #[doc = "TCC1 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tcc1_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC1_MC1) + } + #[doc = "TCC2 Overflow Trigger"] + #[inline(always)] + pub fn tcc2_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC2_OVF) + } + #[doc = "TCC2 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tcc2_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC2_MC0) + } + #[doc = "TCC2 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tcc2_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC2_MC1) + } + #[doc = "TC0 Overflow Trigger"] + #[inline(always)] + pub fn tc0_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC0_OVF) + } + #[doc = "TC0 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tc0_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC0_MC0) + } + #[doc = "TC0 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tc0_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC0_MC1) + } + #[doc = "TC1 Overflow Trigger"] + #[inline(always)] + pub fn tc1_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC1_OVF) + } + #[doc = "TC1 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tc1_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC1_MC0) + } + #[doc = "TC1 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tc1_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC1_MC1) + } + #[doc = "TC2 Overflow Trigger"] + #[inline(always)] + pub fn tc2_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC2_OVF) + } + #[doc = "TC2 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tc2_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC2_MC0) + } + #[doc = "TC2 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tc2_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC2_MC1) + } + #[doc = "TC3 Overflow Trigger"] + #[inline(always)] + pub fn tc3_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC3_OVF) + } + #[doc = "TC3 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tc3_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC3_MC0) + } + #[doc = "TC3 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tc3_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC3_MC1) + } + #[doc = "TC4 Overflow Trigger"] + #[inline(always)] + pub fn tc4_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC4_OVF) + } + #[doc = "TC4 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tc4_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC4_MC0) + } + #[doc = "TC4 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tc4_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC4_MC1) + } + #[doc = "ADC0 Result Ready Trigger"] + #[inline(always)] + pub fn adc0_resrdy(self) -> &'a mut W { + self.variant(TRIGSRC_A::ADC0_RESRDY) + } + #[doc = "PTC End of Conversion Trigger"] + #[inline(always)] + pub fn ptc_eoc(self) -> &'a mut W { + self.variant(TRIGSRC_A::PTC_EOC) + } + #[doc = "PTC Window Compare Trigger"] + #[inline(always)] + pub fn ptc_wcomp(self) -> &'a mut W { + self.variant(TRIGSRC_A::PTC_WCOMP) + } + #[doc = "PTC Sequence Trigger"] + #[inline(always)] + pub fn ptc_seq(self) -> &'a mut W { + self.variant(TRIGSRC_A::PTC_SEQ) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 8)) | ((value as u32 & 0x3f) << 8); + self.w + } +} +#[doc = "Trigger Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum TRIGACT_A { + #[doc = "0: One trigger required for each block transfer"] + BLOCK = 0, + #[doc = "2: One trigger required for each beat transfer"] + BEAT = 2, + #[doc = "3: One trigger required for each transaction"] + TRANSACTION = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: TRIGACT_A) -> Self { + variant as _ + } +} +#[doc = "Field `TRIGACT` reader - Trigger Action"] +pub struct TRIGACT_R(crate::FieldReader); +impl TRIGACT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TRIGACT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(TRIGACT_A::BLOCK), + 2 => Some(TRIGACT_A::BEAT), + 3 => Some(TRIGACT_A::TRANSACTION), + _ => None, + } + } + #[doc = "Checks if the value of the field is `BLOCK`"] + #[inline(always)] + pub fn is_block(&self) -> bool { + **self == TRIGACT_A::BLOCK + } + #[doc = "Checks if the value of the field is `BEAT`"] + #[inline(always)] + pub fn is_beat(&self) -> bool { + **self == TRIGACT_A::BEAT + } + #[doc = "Checks if the value of the field is `TRANSACTION`"] + #[inline(always)] + pub fn is_transaction(&self) -> bool { + **self == TRIGACT_A::TRANSACTION + } +} +impl core::ops::Deref for TRIGACT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRIGACT` writer - Trigger Action"] +pub struct TRIGACT_W<'a> { + w: &'a mut W, +} +impl<'a> TRIGACT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TRIGACT_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "One trigger required for each block transfer"] + #[inline(always)] + pub fn block(self) -> &'a mut W { + self.variant(TRIGACT_A::BLOCK) + } + #[doc = "One trigger required for each beat transfer"] + #[inline(always)] + pub fn beat(self) -> &'a mut W { + self.variant(TRIGACT_A::BEAT) + } + #[doc = "One trigger required for each transaction"] + #[inline(always)] + pub fn transaction(self) -> &'a mut W { + self.variant(TRIGACT_A::TRANSACTION) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 22)) | ((value as u32 & 0x03) << 22); + self.w + } +} +#[doc = "Software Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NOACT = 0, + #[doc = "1: Channel suspend operation"] + SUSPEND = 1, + #[doc = "2: Channel resume operation"] + RESUME = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Software Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NOACT), + 1 => Some(CMD_A::SUSPEND), + 2 => Some(CMD_A::RESUME), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NOACT`"] + #[inline(always)] + pub fn is_noact(&self) -> bool { + **self == CMD_A::NOACT + } + #[doc = "Checks if the value of the field is `SUSPEND`"] + #[inline(always)] + pub fn is_suspend(&self) -> bool { + **self == CMD_A::SUSPEND + } + #[doc = "Checks if the value of the field is `RESUME`"] + #[inline(always)] + pub fn is_resume(&self) -> bool { + **self == CMD_A::RESUME + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Software Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn noact(self) -> &'a mut W { + self.variant(CMD_A::NOACT) + } + #[doc = "Channel suspend operation"] + #[inline(always)] + pub fn suspend(self) -> &'a mut W { + self.variant(CMD_A::SUSPEND) + } + #[doc = "Channel resume operation"] + #[inline(always)] + pub fn resume(self) -> &'a mut W { + self.variant(CMD_A::RESUME) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 24)) | ((value as u32 & 0x03) << 24); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Event Input Action"] + #[inline(always)] + pub fn evact(&self) -> EVACT_R { + EVACT_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 3 - Channel Event Input Enable"] + #[inline(always)] + pub fn evie(&self) -> EVIE_R { + EVIE_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Channel Event Output Enable"] + #[inline(always)] + pub fn evoe(&self) -> EVOE_R { + EVOE_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bits 5:6 - Channel Arbitration Level"] + #[inline(always)] + pub fn lvl(&self) -> LVL_R { + LVL_R::new(((self.bits >> 5) & 0x03) as u8) + } + #[doc = "Bits 8:13 - Trigger Source"] + #[inline(always)] + pub fn trigsrc(&self) -> TRIGSRC_R { + TRIGSRC_R::new(((self.bits >> 8) & 0x3f) as u8) + } + #[doc = "Bits 22:23 - Trigger Action"] + #[inline(always)] + pub fn trigact(&self) -> TRIGACT_R { + TRIGACT_R::new(((self.bits >> 22) & 0x03) as u8) + } + #[doc = "Bits 24:25 - Software Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 24) & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Event Input Action"] + #[inline(always)] + pub fn evact(&mut self) -> EVACT_W { + EVACT_W { w: self } + } + #[doc = "Bit 3 - Channel Event Input Enable"] + #[inline(always)] + pub fn evie(&mut self) -> EVIE_W { + EVIE_W { w: self } + } + #[doc = "Bit 4 - Channel Event Output Enable"] + #[inline(always)] + pub fn evoe(&mut self) -> EVOE_W { + EVOE_W { w: self } + } + #[doc = "Bits 5:6 - Channel Arbitration Level"] + #[inline(always)] + pub fn lvl(&mut self) -> LVL_W { + LVL_W { w: self } + } + #[doc = "Bits 8:13 - Trigger Source"] + #[inline(always)] + pub fn trigsrc(&mut self) -> TRIGSRC_W { + TRIGSRC_W { w: self } + } + #[doc = "Bits 22:23 - Trigger Action"] + #[inline(always)] + pub fn trigact(&mut self) -> TRIGACT_W { + TRIGACT_W { w: self } + } + #[doc = "Bits 24:25 - Software Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chctrlb](index.html) module"] +pub struct CHCTRLB_SPEC; +impl crate::RegisterSpec for CHCTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [chctrlb::R](R) reader structure"] +impl crate::Readable for CHCTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chctrlb::W](W) writer structure"] +impl crate::Writable for CHCTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHCTRLB to value 0"] +impl crate::Resettable for CHCTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/dmac/chid.rs b/pac/atsamc20e/src/dmac/chid.rs new file mode 100644 index 000000000000..1f778a7fc6f0 --- /dev/null +++ b/pac/atsamc20e/src/dmac/chid.rs @@ -0,0 +1,103 @@ +#[doc = "Register `CHID` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHID` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ID` reader - Channel ID"] +pub struct ID_R(crate::FieldReader); +impl ID_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ID_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ID_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ID` writer - Channel ID"] +pub struct ID_W<'a> { + w: &'a mut W, +} +impl<'a> ID_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Channel ID"] + #[inline(always)] + pub fn id(&self) -> ID_R { + ID_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Channel ID"] + #[inline(always)] + pub fn id(&mut self) -> ID_W { + ID_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel ID\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chid](index.html) module"] +pub struct CHID_SPEC; +impl crate::RegisterSpec for CHID_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [chid::R](R) reader structure"] +impl crate::Readable for CHID_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chid::W](W) writer structure"] +impl crate::Writable for CHID_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHID to value 0"] +impl crate::Resettable for CHID_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/dmac/chintenclr.rs b/pac/atsamc20e/src/dmac/chintenclr.rs new file mode 100644 index 000000000000..5ae3096f9ab8 --- /dev/null +++ b/pac/atsamc20e/src/dmac/chintenclr.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CHINTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHINTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TERR` reader - Channel Transfer Error Interrupt Enable"] +pub struct TERR_R(crate::FieldReader); +impl TERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TERR` writer - Channel Transfer Error Interrupt Enable"] +pub struct TERR_W<'a> { + w: &'a mut W, +} +impl<'a> TERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TCMPL` reader - Channel Transfer Complete Interrupt Enable"] +pub struct TCMPL_R(crate::FieldReader); +impl TCMPL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCMPL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCMPL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCMPL` writer - Channel Transfer Complete Interrupt Enable"] +pub struct TCMPL_W<'a> { + w: &'a mut W, +} +impl<'a> TCMPL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SUSP` reader - Channel Suspend Interrupt Enable"] +pub struct SUSP_R(crate::FieldReader); +impl SUSP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SUSP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SUSP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SUSP` writer - Channel Suspend Interrupt Enable"] +pub struct SUSP_W<'a> { + w: &'a mut W, +} +impl<'a> SUSP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Channel Transfer Error Interrupt Enable"] + #[inline(always)] + pub fn terr(&self) -> TERR_R { + TERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel Transfer Complete Interrupt Enable"] + #[inline(always)] + pub fn tcmpl(&self) -> TCMPL_R { + TCMPL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel Suspend Interrupt Enable"] + #[inline(always)] + pub fn susp(&self) -> SUSP_R { + SUSP_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel Transfer Error Interrupt Enable"] + #[inline(always)] + pub fn terr(&mut self) -> TERR_W { + TERR_W { w: self } + } + #[doc = "Bit 1 - Channel Transfer Complete Interrupt Enable"] + #[inline(always)] + pub fn tcmpl(&mut self) -> TCMPL_W { + TCMPL_W { w: self } + } + #[doc = "Bit 2 - Channel Suspend Interrupt Enable"] + #[inline(always)] + pub fn susp(&mut self) -> SUSP_W { + SUSP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chintenclr](index.html) module"] +pub struct CHINTENCLR_SPEC; +impl crate::RegisterSpec for CHINTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [chintenclr::R](R) reader structure"] +impl crate::Readable for CHINTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chintenclr::W](W) writer structure"] +impl crate::Writable for CHINTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHINTENCLR to value 0"] +impl crate::Resettable for CHINTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/dmac/chintenset.rs b/pac/atsamc20e/src/dmac/chintenset.rs new file mode 100644 index 000000000000..2e7daef20a6f --- /dev/null +++ b/pac/atsamc20e/src/dmac/chintenset.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CHINTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHINTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TERR` reader - Channel Transfer Error Interrupt Enable"] +pub struct TERR_R(crate::FieldReader); +impl TERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TERR` writer - Channel Transfer Error Interrupt Enable"] +pub struct TERR_W<'a> { + w: &'a mut W, +} +impl<'a> TERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TCMPL` reader - Channel Transfer Complete Interrupt Enable"] +pub struct TCMPL_R(crate::FieldReader); +impl TCMPL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCMPL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCMPL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCMPL` writer - Channel Transfer Complete Interrupt Enable"] +pub struct TCMPL_W<'a> { + w: &'a mut W, +} +impl<'a> TCMPL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SUSP` reader - Channel Suspend Interrupt Enable"] +pub struct SUSP_R(crate::FieldReader); +impl SUSP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SUSP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SUSP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SUSP` writer - Channel Suspend Interrupt Enable"] +pub struct SUSP_W<'a> { + w: &'a mut W, +} +impl<'a> SUSP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Channel Transfer Error Interrupt Enable"] + #[inline(always)] + pub fn terr(&self) -> TERR_R { + TERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel Transfer Complete Interrupt Enable"] + #[inline(always)] + pub fn tcmpl(&self) -> TCMPL_R { + TCMPL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel Suspend Interrupt Enable"] + #[inline(always)] + pub fn susp(&self) -> SUSP_R { + SUSP_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel Transfer Error Interrupt Enable"] + #[inline(always)] + pub fn terr(&mut self) -> TERR_W { + TERR_W { w: self } + } + #[doc = "Bit 1 - Channel Transfer Complete Interrupt Enable"] + #[inline(always)] + pub fn tcmpl(&mut self) -> TCMPL_W { + TCMPL_W { w: self } + } + #[doc = "Bit 2 - Channel Suspend Interrupt Enable"] + #[inline(always)] + pub fn susp(&mut self) -> SUSP_W { + SUSP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chintenset](index.html) module"] +pub struct CHINTENSET_SPEC; +impl crate::RegisterSpec for CHINTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [chintenset::R](R) reader structure"] +impl crate::Readable for CHINTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chintenset::W](W) writer structure"] +impl crate::Writable for CHINTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHINTENSET to value 0"] +impl crate::Resettable for CHINTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/dmac/chintflag.rs b/pac/atsamc20e/src/dmac/chintflag.rs new file mode 100644 index 000000000000..4e61d6510c30 --- /dev/null +++ b/pac/atsamc20e/src/dmac/chintflag.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CHINTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHINTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TERR` reader - Channel Transfer Error"] +pub struct TERR_R(crate::FieldReader); +impl TERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TERR` writer - Channel Transfer Error"] +pub struct TERR_W<'a> { + w: &'a mut W, +} +impl<'a> TERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TCMPL` reader - Channel Transfer Complete"] +pub struct TCMPL_R(crate::FieldReader); +impl TCMPL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCMPL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCMPL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCMPL` writer - Channel Transfer Complete"] +pub struct TCMPL_W<'a> { + w: &'a mut W, +} +impl<'a> TCMPL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SUSP` reader - Channel Suspend"] +pub struct SUSP_R(crate::FieldReader); +impl SUSP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SUSP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SUSP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SUSP` writer - Channel Suspend"] +pub struct SUSP_W<'a> { + w: &'a mut W, +} +impl<'a> SUSP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Channel Transfer Error"] + #[inline(always)] + pub fn terr(&self) -> TERR_R { + TERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel Transfer Complete"] + #[inline(always)] + pub fn tcmpl(&self) -> TCMPL_R { + TCMPL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel Suspend"] + #[inline(always)] + pub fn susp(&self) -> SUSP_R { + SUSP_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel Transfer Error"] + #[inline(always)] + pub fn terr(&mut self) -> TERR_W { + TERR_W { w: self } + } + #[doc = "Bit 1 - Channel Transfer Complete"] + #[inline(always)] + pub fn tcmpl(&mut self) -> TCMPL_W { + TCMPL_W { w: self } + } + #[doc = "Bit 2 - Channel Suspend"] + #[inline(always)] + pub fn susp(&mut self) -> SUSP_W { + SUSP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chintflag](index.html) module"] +pub struct CHINTFLAG_SPEC; +impl crate::RegisterSpec for CHINTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [chintflag::R](R) reader structure"] +impl crate::Readable for CHINTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chintflag::W](W) writer structure"] +impl crate::Writable for CHINTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHINTFLAG to value 0"] +impl crate::Resettable for CHINTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/dmac/chstatus.rs b/pac/atsamc20e/src/dmac/chstatus.rs new file mode 100644 index 000000000000..98a84345d4f7 --- /dev/null +++ b/pac/atsamc20e/src/dmac/chstatus.rs @@ -0,0 +1,93 @@ +#[doc = "Register `CHSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PEND` reader - Channel Pending"] +pub struct PEND_R(crate::FieldReader); +impl PEND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSY` reader - Channel Busy"] +pub struct BUSY_R(crate::FieldReader); +impl BUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FERR` reader - Channel Fetch Error"] +pub struct FERR_R(crate::FieldReader); +impl FERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Channel Pending"] + #[inline(always)] + pub fn pend(&self) -> PEND_R { + PEND_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel Busy"] + #[inline(always)] + pub fn busy(&self) -> BUSY_R { + BUSY_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel Fetch Error"] + #[inline(always)] + pub fn ferr(&self) -> FERR_R { + FERR_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +#[doc = "Channel Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chstatus](index.html) module"] +pub struct CHSTATUS_SPEC; +impl crate::RegisterSpec for CHSTATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [chstatus::R](R) reader structure"] +impl crate::Readable for CHSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CHSTATUS to value 0"] +impl crate::Resettable for CHSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/dmac/crcchksum.rs b/pac/atsamc20e/src/dmac/crcchksum.rs new file mode 100644 index 000000000000..89eb5b38a093 --- /dev/null +++ b/pac/atsamc20e/src/dmac/crcchksum.rs @@ -0,0 +1,103 @@ +#[doc = "Register `CRCCHKSUM` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CRCCHKSUM` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CRCCHKSUM` reader - CRC Checksum"] +pub struct CRCCHKSUM_R(crate::FieldReader); +impl CRCCHKSUM_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CRCCHKSUM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CRCCHKSUM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCCHKSUM` writer - CRC Checksum"] +pub struct CRCCHKSUM_W<'a> { + w: &'a mut W, +} +impl<'a> CRCCHKSUM_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - CRC Checksum"] + #[inline(always)] + pub fn crcchksum(&self) -> CRCCHKSUM_R { + CRCCHKSUM_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - CRC Checksum"] + #[inline(always)] + pub fn crcchksum(&mut self) -> CRCCHKSUM_W { + CRCCHKSUM_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CRC Checksum\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [crcchksum](index.html) module"] +pub struct CRCCHKSUM_SPEC; +impl crate::RegisterSpec for CRCCHKSUM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [crcchksum::R](R) reader structure"] +impl crate::Readable for CRCCHKSUM_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [crcchksum::W](W) writer structure"] +impl crate::Writable for CRCCHKSUM_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CRCCHKSUM to value 0"] +impl crate::Resettable for CRCCHKSUM_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/dmac/crcctrl.rs b/pac/atsamc20e/src/dmac/crcctrl.rs new file mode 100644 index 000000000000..b8daf7b8259d --- /dev/null +++ b/pac/atsamc20e/src/dmac/crcctrl.rs @@ -0,0 +1,337 @@ +#[doc = "Register `CRCCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CRCCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "CRC Beat Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CRCBEATSIZE_A { + #[doc = "0: 8-bit bus transfer"] + BYTE = 0, + #[doc = "1: 16-bit bus transfer"] + HWORD = 1, + #[doc = "2: 32-bit bus transfer"] + WORD = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CRCBEATSIZE_A) -> Self { + variant as _ + } +} +#[doc = "Field `CRCBEATSIZE` reader - CRC Beat Size"] +pub struct CRCBEATSIZE_R(crate::FieldReader); +impl CRCBEATSIZE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CRCBEATSIZE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CRCBEATSIZE_A::BYTE), + 1 => Some(CRCBEATSIZE_A::HWORD), + 2 => Some(CRCBEATSIZE_A::WORD), + _ => None, + } + } + #[doc = "Checks if the value of the field is `BYTE`"] + #[inline(always)] + pub fn is_byte(&self) -> bool { + **self == CRCBEATSIZE_A::BYTE + } + #[doc = "Checks if the value of the field is `HWORD`"] + #[inline(always)] + pub fn is_hword(&self) -> bool { + **self == CRCBEATSIZE_A::HWORD + } + #[doc = "Checks if the value of the field is `WORD`"] + #[inline(always)] + pub fn is_word(&self) -> bool { + **self == CRCBEATSIZE_A::WORD + } +} +impl core::ops::Deref for CRCBEATSIZE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCBEATSIZE` writer - CRC Beat Size"] +pub struct CRCBEATSIZE_W<'a> { + w: &'a mut W, +} +impl<'a> CRCBEATSIZE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CRCBEATSIZE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8-bit bus transfer"] + #[inline(always)] + pub fn byte(self) -> &'a mut W { + self.variant(CRCBEATSIZE_A::BYTE) + } + #[doc = "16-bit bus transfer"] + #[inline(always)] + pub fn hword(self) -> &'a mut W { + self.variant(CRCBEATSIZE_A::HWORD) + } + #[doc = "32-bit bus transfer"] + #[inline(always)] + pub fn word(self) -> &'a mut W { + self.variant(CRCBEATSIZE_A::WORD) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u16 & 0x03); + self.w + } +} +#[doc = "CRC Polynomial Type\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CRCPOLY_A { + #[doc = "0: CRC-16 (CRC-CCITT)"] + CRC16 = 0, + #[doc = "1: CRC32 (IEEE 802.3)"] + CRC32 = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CRCPOLY_A) -> Self { + variant as _ + } +} +#[doc = "Field `CRCPOLY` reader - CRC Polynomial Type"] +pub struct CRCPOLY_R(crate::FieldReader); +impl CRCPOLY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CRCPOLY_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CRCPOLY_A::CRC16), + 1 => Some(CRCPOLY_A::CRC32), + _ => None, + } + } + #[doc = "Checks if the value of the field is `CRC16`"] + #[inline(always)] + pub fn is_crc16(&self) -> bool { + **self == CRCPOLY_A::CRC16 + } + #[doc = "Checks if the value of the field is `CRC32`"] + #[inline(always)] + pub fn is_crc32(&self) -> bool { + **self == CRCPOLY_A::CRC32 + } +} +impl core::ops::Deref for CRCPOLY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCPOLY` writer - CRC Polynomial Type"] +pub struct CRCPOLY_W<'a> { + w: &'a mut W, +} +impl<'a> CRCPOLY_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CRCPOLY_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "CRC-16 (CRC-CCITT)"] + #[inline(always)] + pub fn crc16(self) -> &'a mut W { + self.variant(CRCPOLY_A::CRC16) + } + #[doc = "CRC32 (IEEE 802.3)"] + #[inline(always)] + pub fn crc32(self) -> &'a mut W { + self.variant(CRCPOLY_A::CRC32) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u16 & 0x03) << 2); + self.w + } +} +#[doc = "CRC Input Source\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CRCSRC_A { + #[doc = "0: No action"] + NOACT = 0, + #[doc = "1: I/O interface"] + IO = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CRCSRC_A) -> Self { + variant as _ + } +} +#[doc = "Field `CRCSRC` reader - CRC Input Source"] +pub struct CRCSRC_R(crate::FieldReader); +impl CRCSRC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CRCSRC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CRCSRC_A::NOACT), + 1 => Some(CRCSRC_A::IO), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NOACT`"] + #[inline(always)] + pub fn is_noact(&self) -> bool { + **self == CRCSRC_A::NOACT + } + #[doc = "Checks if the value of the field is `IO`"] + #[inline(always)] + pub fn is_io(&self) -> bool { + **self == CRCSRC_A::IO + } +} +impl core::ops::Deref for CRCSRC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCSRC` writer - CRC Input Source"] +pub struct CRCSRC_W<'a> { + w: &'a mut W, +} +impl<'a> CRCSRC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CRCSRC_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn noact(self) -> &'a mut W { + self.variant(CRCSRC_A::NOACT) + } + #[doc = "I/O interface"] + #[inline(always)] + pub fn io(self) -> &'a mut W { + self.variant(CRCSRC_A::IO) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 8)) | ((value as u16 & 0x3f) << 8); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - CRC Beat Size"] + #[inline(always)] + pub fn crcbeatsize(&self) -> CRCBEATSIZE_R { + CRCBEATSIZE_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bits 2:3 - CRC Polynomial Type"] + #[inline(always)] + pub fn crcpoly(&self) -> CRCPOLY_R { + CRCPOLY_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bits 8:13 - CRC Input Source"] + #[inline(always)] + pub fn crcsrc(&self) -> CRCSRC_R { + CRCSRC_R::new(((self.bits >> 8) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - CRC Beat Size"] + #[inline(always)] + pub fn crcbeatsize(&mut self) -> CRCBEATSIZE_W { + CRCBEATSIZE_W { w: self } + } + #[doc = "Bits 2:3 - CRC Polynomial Type"] + #[inline(always)] + pub fn crcpoly(&mut self) -> CRCPOLY_W { + CRCPOLY_W { w: self } + } + #[doc = "Bits 8:13 - CRC Input Source"] + #[inline(always)] + pub fn crcsrc(&mut self) -> CRCSRC_W { + CRCSRC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CRC Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [crcctrl](index.html) module"] +pub struct CRCCTRL_SPEC; +impl crate::RegisterSpec for CRCCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [crcctrl::R](R) reader structure"] +impl crate::Readable for CRCCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [crcctrl::W](W) writer structure"] +impl crate::Writable for CRCCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CRCCTRL to value 0"] +impl crate::Resettable for CRCCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/dmac/crcdatain.rs b/pac/atsamc20e/src/dmac/crcdatain.rs new file mode 100644 index 000000000000..ca0879a12136 --- /dev/null +++ b/pac/atsamc20e/src/dmac/crcdatain.rs @@ -0,0 +1,103 @@ +#[doc = "Register `CRCDATAIN` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CRCDATAIN` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CRCDATAIN` reader - CRC Data Input"] +pub struct CRCDATAIN_R(crate::FieldReader); +impl CRCDATAIN_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CRCDATAIN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CRCDATAIN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCDATAIN` writer - CRC Data Input"] +pub struct CRCDATAIN_W<'a> { + w: &'a mut W, +} +impl<'a> CRCDATAIN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - CRC Data Input"] + #[inline(always)] + pub fn crcdatain(&self) -> CRCDATAIN_R { + CRCDATAIN_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - CRC Data Input"] + #[inline(always)] + pub fn crcdatain(&mut self) -> CRCDATAIN_W { + CRCDATAIN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CRC Data Input\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [crcdatain](index.html) module"] +pub struct CRCDATAIN_SPEC; +impl crate::RegisterSpec for CRCDATAIN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [crcdatain::R](R) reader structure"] +impl crate::Readable for CRCDATAIN_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [crcdatain::W](W) writer structure"] +impl crate::Writable for CRCDATAIN_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CRCDATAIN to value 0"] +impl crate::Resettable for CRCDATAIN_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/dmac/crcstatus.rs b/pac/atsamc20e/src/dmac/crcstatus.rs new file mode 100644 index 000000000000..a132e9d5cd03 --- /dev/null +++ b/pac/atsamc20e/src/dmac/crcstatus.rs @@ -0,0 +1,160 @@ +#[doc = "Register `CRCSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CRCSTATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CRCBUSY` reader - CRC Module Busy"] +pub struct CRCBUSY_R(crate::FieldReader); +impl CRCBUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CRCBUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CRCBUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCBUSY` writer - CRC Module Busy"] +pub struct CRCBUSY_W<'a> { + w: &'a mut W, +} +impl<'a> CRCBUSY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `CRCZERO` reader - CRC Zero"] +pub struct CRCZERO_R(crate::FieldReader); +impl CRCZERO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CRCZERO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CRCZERO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCZERO` writer - CRC Zero"] +pub struct CRCZERO_W<'a> { + w: &'a mut W, +} +impl<'a> CRCZERO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - CRC Module Busy"] + #[inline(always)] + pub fn crcbusy(&self) -> CRCBUSY_R { + CRCBUSY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - CRC Zero"] + #[inline(always)] + pub fn crczero(&self) -> CRCZERO_R { + CRCZERO_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - CRC Module Busy"] + #[inline(always)] + pub fn crcbusy(&mut self) -> CRCBUSY_W { + CRCBUSY_W { w: self } + } + #[doc = "Bit 1 - CRC Zero"] + #[inline(always)] + pub fn crczero(&mut self) -> CRCZERO_W { + CRCZERO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CRC Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [crcstatus](index.html) module"] +pub struct CRCSTATUS_SPEC; +impl crate::RegisterSpec for CRCSTATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [crcstatus::R](R) reader structure"] +impl crate::Readable for CRCSTATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [crcstatus::W](W) writer structure"] +impl crate::Writable for CRCSTATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CRCSTATUS to value 0"] +impl crate::Resettable for CRCSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/dmac/ctrl.rs b/pac/atsamc20e/src/dmac/ctrl.rs new file mode 100644 index 000000000000..fabae9d82a6c --- /dev/null +++ b/pac/atsamc20e/src/dmac/ctrl.rs @@ -0,0 +1,395 @@ +#[doc = "Register `CTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `DMAENABLE` reader - DMA Enable"] +pub struct DMAENABLE_R(crate::FieldReader); +impl DMAENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DMAENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DMAENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DMAENABLE` writer - DMA Enable"] +pub struct DMAENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> DMAENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CRCENABLE` reader - CRC Enable"] +pub struct CRCENABLE_R(crate::FieldReader); +impl CRCENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CRCENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CRCENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCENABLE` writer - CRC Enable"] +pub struct CRCENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> CRCENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `LVLEN0` reader - Priority Level 0 Enable"] +pub struct LVLEN0_R(crate::FieldReader); +impl LVLEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LVLEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLEN0` writer - Priority Level 0 Enable"] +pub struct LVLEN0_W<'a> { + w: &'a mut W, +} +impl<'a> LVLEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `LVLEN1` reader - Priority Level 1 Enable"] +pub struct LVLEN1_R(crate::FieldReader); +impl LVLEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LVLEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLEN1` writer - Priority Level 1 Enable"] +pub struct LVLEN1_W<'a> { + w: &'a mut W, +} +impl<'a> LVLEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `LVLEN2` reader - Priority Level 2 Enable"] +pub struct LVLEN2_R(crate::FieldReader); +impl LVLEN2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LVLEN2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEN2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLEN2` writer - Priority Level 2 Enable"] +pub struct LVLEN2_W<'a> { + w: &'a mut W, +} +impl<'a> LVLEN2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u16 & 0x01) << 10); + self.w + } +} +#[doc = "Field `LVLEN3` reader - Priority Level 3 Enable"] +pub struct LVLEN3_R(crate::FieldReader); +impl LVLEN3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LVLEN3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEN3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLEN3` writer - Priority Level 3 Enable"] +pub struct LVLEN3_W<'a> { + w: &'a mut W, +} +impl<'a> LVLEN3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u16 & 0x01) << 11); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - DMA Enable"] + #[inline(always)] + pub fn dmaenable(&self) -> DMAENABLE_R { + DMAENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - CRC Enable"] + #[inline(always)] + pub fn crcenable(&self) -> CRCENABLE_R { + CRCENABLE_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 8 - Priority Level 0 Enable"] + #[inline(always)] + pub fn lvlen0(&self) -> LVLEN0_R { + LVLEN0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Priority Level 1 Enable"] + #[inline(always)] + pub fn lvlen1(&self) -> LVLEN1_R { + LVLEN1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Priority Level 2 Enable"] + #[inline(always)] + pub fn lvlen2(&self) -> LVLEN2_R { + LVLEN2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Priority Level 3 Enable"] + #[inline(always)] + pub fn lvlen3(&self) -> LVLEN3_R { + LVLEN3_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - DMA Enable"] + #[inline(always)] + pub fn dmaenable(&mut self) -> DMAENABLE_W { + DMAENABLE_W { w: self } + } + #[doc = "Bit 2 - CRC Enable"] + #[inline(always)] + pub fn crcenable(&mut self) -> CRCENABLE_W { + CRCENABLE_W { w: self } + } + #[doc = "Bit 8 - Priority Level 0 Enable"] + #[inline(always)] + pub fn lvlen0(&mut self) -> LVLEN0_W { + LVLEN0_W { w: self } + } + #[doc = "Bit 9 - Priority Level 1 Enable"] + #[inline(always)] + pub fn lvlen1(&mut self) -> LVLEN1_W { + LVLEN1_W { w: self } + } + #[doc = "Bit 10 - Priority Level 2 Enable"] + #[inline(always)] + pub fn lvlen2(&mut self) -> LVLEN2_W { + LVLEN2_W { w: self } + } + #[doc = "Bit 11 - Priority Level 3 Enable"] + #[inline(always)] + pub fn lvlen3(&mut self) -> LVLEN3_W { + LVLEN3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"] +pub struct CTRL_SPEC; +impl crate::RegisterSpec for CTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrl::R](R) reader structure"] +impl crate::Readable for CTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"] +impl crate::Writable for CTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/dmac/dbgctrl.rs b/pac/atsamc20e/src/dmac/dbgctrl.rs new file mode 100644 index 000000000000..53636eb2b339 --- /dev/null +++ b/pac/atsamc20e/src/dmac/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Debug Run"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Debug Run"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/dmac/intpend.rs b/pac/atsamc20e/src/dmac/intpend.rs new file mode 100644 index 000000000000..1988b30a190b --- /dev/null +++ b/pac/atsamc20e/src/dmac/intpend.rs @@ -0,0 +1,385 @@ +#[doc = "Register `INTPEND` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTPEND` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ID` reader - Channel ID"] +pub struct ID_R(crate::FieldReader); +impl ID_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ID_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ID_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ID` writer - Channel ID"] +pub struct ID_W<'a> { + w: &'a mut W, +} +impl<'a> ID_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u16 & 0x07); + self.w + } +} +#[doc = "Field `TERR` reader - Transfer Error"] +pub struct TERR_R(crate::FieldReader); +impl TERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TERR` writer - Transfer Error"] +pub struct TERR_W<'a> { + w: &'a mut W, +} +impl<'a> TERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `TCMPL` reader - Transfer Complete"] +pub struct TCMPL_R(crate::FieldReader); +impl TCMPL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCMPL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCMPL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCMPL` writer - Transfer Complete"] +pub struct TCMPL_W<'a> { + w: &'a mut W, +} +impl<'a> TCMPL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `SUSP` reader - Channel Suspend"] +pub struct SUSP_R(crate::FieldReader); +impl SUSP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SUSP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SUSP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SUSP` writer - Channel Suspend"] +pub struct SUSP_W<'a> { + w: &'a mut W, +} +impl<'a> SUSP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u16 & 0x01) << 10); + self.w + } +} +#[doc = "Field `FERR` reader - Fetch Error"] +pub struct FERR_R(crate::FieldReader); +impl FERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FERR` writer - Fetch Error"] +pub struct FERR_W<'a> { + w: &'a mut W, +} +impl<'a> FERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u16 & 0x01) << 13); + self.w + } +} +#[doc = "Field `BUSY` reader - Busy"] +pub struct BUSY_R(crate::FieldReader); +impl BUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSY` writer - Busy"] +pub struct BUSY_W<'a> { + w: &'a mut W, +} +impl<'a> BUSY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u16 & 0x01) << 14); + self.w + } +} +#[doc = "Field `PEND` reader - Pending"] +pub struct PEND_R(crate::FieldReader); +impl PEND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEND` writer - Pending"] +pub struct PEND_W<'a> { + w: &'a mut W, +} +impl<'a> PEND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Channel ID"] + #[inline(always)] + pub fn id(&self) -> ID_R { + ID_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 8 - Transfer Error"] + #[inline(always)] + pub fn terr(&self) -> TERR_R { + TERR_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Transfer Complete"] + #[inline(always)] + pub fn tcmpl(&self) -> TCMPL_R { + TCMPL_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Channel Suspend"] + #[inline(always)] + pub fn susp(&self) -> SUSP_R { + SUSP_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 13 - Fetch Error"] + #[inline(always)] + pub fn ferr(&self) -> FERR_R { + FERR_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Busy"] + #[inline(always)] + pub fn busy(&self) -> BUSY_R { + BUSY_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Pending"] + #[inline(always)] + pub fn pend(&self) -> PEND_R { + PEND_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Channel ID"] + #[inline(always)] + pub fn id(&mut self) -> ID_W { + ID_W { w: self } + } + #[doc = "Bit 8 - Transfer Error"] + #[inline(always)] + pub fn terr(&mut self) -> TERR_W { + TERR_W { w: self } + } + #[doc = "Bit 9 - Transfer Complete"] + #[inline(always)] + pub fn tcmpl(&mut self) -> TCMPL_W { + TCMPL_W { w: self } + } + #[doc = "Bit 10 - Channel Suspend"] + #[inline(always)] + pub fn susp(&mut self) -> SUSP_W { + SUSP_W { w: self } + } + #[doc = "Bit 13 - Fetch Error"] + #[inline(always)] + pub fn ferr(&mut self) -> FERR_W { + FERR_W { w: self } + } + #[doc = "Bit 14 - Busy"] + #[inline(always)] + pub fn busy(&mut self) -> BUSY_W { + BUSY_W { w: self } + } + #[doc = "Bit 15 - Pending"] + #[inline(always)] + pub fn pend(&mut self) -> PEND_W { + PEND_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Pending\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intpend](index.html) module"] +pub struct INTPEND_SPEC; +impl crate::RegisterSpec for INTPEND_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intpend::R](R) reader structure"] +impl crate::Readable for INTPEND_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intpend::W](W) writer structure"] +impl crate::Writable for INTPEND_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTPEND to value 0"] +impl crate::Resettable for INTPEND_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/dmac/intstatus.rs b/pac/atsamc20e/src/dmac/intstatus.rs new file mode 100644 index 000000000000..4e6617d96bef --- /dev/null +++ b/pac/atsamc20e/src/dmac/intstatus.rs @@ -0,0 +1,153 @@ +#[doc = "Register `INTSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `CHINT0` reader - Channel 0 Pending Interrupt"] +pub struct CHINT0_R(crate::FieldReader); +impl CHINT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT1` reader - Channel 1 Pending Interrupt"] +pub struct CHINT1_R(crate::FieldReader); +impl CHINT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT2` reader - Channel 2 Pending Interrupt"] +pub struct CHINT2_R(crate::FieldReader); +impl CHINT2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT3` reader - Channel 3 Pending Interrupt"] +pub struct CHINT3_R(crate::FieldReader); +impl CHINT3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT4` reader - Channel 4 Pending Interrupt"] +pub struct CHINT4_R(crate::FieldReader); +impl CHINT4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT5` reader - Channel 5 Pending Interrupt"] +pub struct CHINT5_R(crate::FieldReader); +impl CHINT5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Channel 0 Pending Interrupt"] + #[inline(always)] + pub fn chint0(&self) -> CHINT0_R { + CHINT0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel 1 Pending Interrupt"] + #[inline(always)] + pub fn chint1(&self) -> CHINT1_R { + CHINT1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel 2 Pending Interrupt"] + #[inline(always)] + pub fn chint2(&self) -> CHINT2_R { + CHINT2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Channel 3 Pending Interrupt"] + #[inline(always)] + pub fn chint3(&self) -> CHINT3_R { + CHINT3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Channel 4 Pending Interrupt"] + #[inline(always)] + pub fn chint4(&self) -> CHINT4_R { + CHINT4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Channel 5 Pending Interrupt"] + #[inline(always)] + pub fn chint5(&self) -> CHINT5_R { + CHINT5_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +#[doc = "Interrupt Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intstatus](index.html) module"] +pub struct INTSTATUS_SPEC; +impl crate::RegisterSpec for INTSTATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intstatus::R](R) reader structure"] +impl crate::Readable for INTSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets INTSTATUS to value 0"] +impl crate::Resettable for INTSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/dmac/pendch.rs b/pac/atsamc20e/src/dmac/pendch.rs new file mode 100644 index 000000000000..1ffc2ca607b1 --- /dev/null +++ b/pac/atsamc20e/src/dmac/pendch.rs @@ -0,0 +1,153 @@ +#[doc = "Register `PENDCH` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PENDCH0` reader - Pending Channel 0"] +pub struct PENDCH0_R(crate::FieldReader); +impl PENDCH0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH1` reader - Pending Channel 1"] +pub struct PENDCH1_R(crate::FieldReader); +impl PENDCH1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH2` reader - Pending Channel 2"] +pub struct PENDCH2_R(crate::FieldReader); +impl PENDCH2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH3` reader - Pending Channel 3"] +pub struct PENDCH3_R(crate::FieldReader); +impl PENDCH3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH4` reader - Pending Channel 4"] +pub struct PENDCH4_R(crate::FieldReader); +impl PENDCH4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH5` reader - Pending Channel 5"] +pub struct PENDCH5_R(crate::FieldReader); +impl PENDCH5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Pending Channel 0"] + #[inline(always)] + pub fn pendch0(&self) -> PENDCH0_R { + PENDCH0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Pending Channel 1"] + #[inline(always)] + pub fn pendch1(&self) -> PENDCH1_R { + PENDCH1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Pending Channel 2"] + #[inline(always)] + pub fn pendch2(&self) -> PENDCH2_R { + PENDCH2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Pending Channel 3"] + #[inline(always)] + pub fn pendch3(&self) -> PENDCH3_R { + PENDCH3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Pending Channel 4"] + #[inline(always)] + pub fn pendch4(&self) -> PENDCH4_R { + PENDCH4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Pending Channel 5"] + #[inline(always)] + pub fn pendch5(&self) -> PENDCH5_R { + PENDCH5_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +#[doc = "Pending Channels\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pendch](index.html) module"] +pub struct PENDCH_SPEC; +impl crate::RegisterSpec for PENDCH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pendch::R](R) reader structure"] +impl crate::Readable for PENDCH_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PENDCH to value 0"] +impl crate::Resettable for PENDCH_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/dmac/prictrl0.rs b/pac/atsamc20e/src/dmac/prictrl0.rs new file mode 100644 index 000000000000..64324f7f2493 --- /dev/null +++ b/pac/atsamc20e/src/dmac/prictrl0.rs @@ -0,0 +1,449 @@ +#[doc = "Register `PRICTRL0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PRICTRL0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `LVLPRI0` reader - Level 0 Channel Priority Number"] +pub struct LVLPRI0_R(crate::FieldReader); +impl LVLPRI0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LVLPRI0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLPRI0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLPRI0` writer - Level 0 Channel Priority Number"] +pub struct LVLPRI0_W<'a> { + w: &'a mut W, +} +impl<'a> LVLPRI0_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Level 0 Round-Robin Scheduling Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RRLVLEN0_A { + #[doc = "0: Static arbitration scheme for channels with level 3 priority"] + STATIC_LVL = 0, + #[doc = "1: Round-robin arbitration scheme for channels with level 3 priority"] + ROUND_ROBIN_LVL = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RRLVLEN0_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RRLVLEN0` reader - Level 0 Round-Robin Scheduling Enable"] +pub struct RRLVLEN0_R(crate::FieldReader); +impl RRLVLEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RRLVLEN0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RRLVLEN0_A { + match self.bits { + false => RRLVLEN0_A::STATIC_LVL, + true => RRLVLEN0_A::ROUND_ROBIN_LVL, + } + } + #[doc = "Checks if the value of the field is `STATIC_LVL`"] + #[inline(always)] + pub fn is_static_lvl(&self) -> bool { + **self == RRLVLEN0_A::STATIC_LVL + } + #[doc = "Checks if the value of the field is `ROUND_ROBIN_LVL`"] + #[inline(always)] + pub fn is_round_robin_lvl(&self) -> bool { + **self == RRLVLEN0_A::ROUND_ROBIN_LVL + } +} +impl core::ops::Deref for RRLVLEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RRLVLEN0` writer - Level 0 Round-Robin Scheduling Enable"] +pub struct RRLVLEN0_W<'a> { + w: &'a mut W, +} +impl<'a> RRLVLEN0_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RRLVLEN0_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Static arbitration scheme for channels with level 3 priority"] + #[inline(always)] + pub fn static_lvl(self) -> &'a mut W { + self.variant(RRLVLEN0_A::STATIC_LVL) + } + #[doc = "Round-robin arbitration scheme for channels with level 3 priority"] + #[inline(always)] + pub fn round_robin_lvl(self) -> &'a mut W { + self.variant(RRLVLEN0_A::ROUND_ROBIN_LVL) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `LVLPRI1` reader - Level 1 Channel Priority Number"] +pub struct LVLPRI1_R(crate::FieldReader); +impl LVLPRI1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LVLPRI1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLPRI1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLPRI1` writer - Level 1 Channel Priority Number"] +pub struct LVLPRI1_W<'a> { + w: &'a mut W, +} +impl<'a> LVLPRI1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +#[doc = "Field `RRLVLEN1` reader - Level 1 Round-Robin Scheduling Enable"] +pub struct RRLVLEN1_R(crate::FieldReader); +impl RRLVLEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RRLVLEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RRLVLEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RRLVLEN1` writer - Level 1 Round-Robin Scheduling Enable"] +pub struct RRLVLEN1_W<'a> { + w: &'a mut W, +} +impl<'a> RRLVLEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `LVLPRI2` reader - Level 2 Channel Priority Number"] +pub struct LVLPRI2_R(crate::FieldReader); +impl LVLPRI2_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LVLPRI2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLPRI2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLPRI2` writer - Level 2 Channel Priority Number"] +pub struct LVLPRI2_W<'a> { + w: &'a mut W, +} +impl<'a> LVLPRI2_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 16)) | ((value as u32 & 0x07) << 16); + self.w + } +} +#[doc = "Field `RRLVLEN2` reader - Level 2 Round-Robin Scheduling Enable"] +pub struct RRLVLEN2_R(crate::FieldReader); +impl RRLVLEN2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RRLVLEN2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RRLVLEN2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RRLVLEN2` writer - Level 2 Round-Robin Scheduling Enable"] +pub struct RRLVLEN2_W<'a> { + w: &'a mut W, +} +impl<'a> RRLVLEN2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `LVLPRI3` reader - Level 3 Channel Priority Number"] +pub struct LVLPRI3_R(crate::FieldReader); +impl LVLPRI3_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LVLPRI3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLPRI3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLPRI3` writer - Level 3 Channel Priority Number"] +pub struct LVLPRI3_W<'a> { + w: &'a mut W, +} +impl<'a> LVLPRI3_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 24)) | ((value as u32 & 0x07) << 24); + self.w + } +} +#[doc = "Field `RRLVLEN3` reader - Level 3 Round-Robin Scheduling Enable"] +pub struct RRLVLEN3_R(crate::FieldReader); +impl RRLVLEN3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RRLVLEN3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RRLVLEN3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RRLVLEN3` writer - Level 3 Round-Robin Scheduling Enable"] +pub struct RRLVLEN3_W<'a> { + w: &'a mut W, +} +impl<'a> RRLVLEN3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Level 0 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri0(&self) -> LVLPRI0_R { + LVLPRI0_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 7 - Level 0 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen0(&self) -> RRLVLEN0_R { + RRLVLEN0_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Level 1 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri1(&self) -> LVLPRI1_R { + LVLPRI1_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 15 - Level 1 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen1(&self) -> RRLVLEN1_R { + RRLVLEN1_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:18 - Level 2 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri2(&self) -> LVLPRI2_R { + LVLPRI2_R::new(((self.bits >> 16) & 0x07) as u8) + } + #[doc = "Bit 23 - Level 2 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen2(&self) -> RRLVLEN2_R { + RRLVLEN2_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bits 24:26 - Level 3 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri3(&self) -> LVLPRI3_R { + LVLPRI3_R::new(((self.bits >> 24) & 0x07) as u8) + } + #[doc = "Bit 31 - Level 3 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen3(&self) -> RRLVLEN3_R { + RRLVLEN3_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Level 0 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri0(&mut self) -> LVLPRI0_W { + LVLPRI0_W { w: self } + } + #[doc = "Bit 7 - Level 0 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen0(&mut self) -> RRLVLEN0_W { + RRLVLEN0_W { w: self } + } + #[doc = "Bits 8:10 - Level 1 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri1(&mut self) -> LVLPRI1_W { + LVLPRI1_W { w: self } + } + #[doc = "Bit 15 - Level 1 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen1(&mut self) -> RRLVLEN1_W { + RRLVLEN1_W { w: self } + } + #[doc = "Bits 16:18 - Level 2 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri2(&mut self) -> LVLPRI2_W { + LVLPRI2_W { w: self } + } + #[doc = "Bit 23 - Level 2 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen2(&mut self) -> RRLVLEN2_W { + RRLVLEN2_W { w: self } + } + #[doc = "Bits 24:26 - Level 3 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri3(&mut self) -> LVLPRI3_W { + LVLPRI3_W { w: self } + } + #[doc = "Bit 31 - Level 3 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen3(&mut self) -> RRLVLEN3_W { + RRLVLEN3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Priority Control 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [prictrl0](index.html) module"] +pub struct PRICTRL0_SPEC; +impl crate::RegisterSpec for PRICTRL0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [prictrl0::R](R) reader structure"] +impl crate::Readable for PRICTRL0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [prictrl0::W](W) writer structure"] +impl crate::Writable for PRICTRL0_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PRICTRL0 to value 0"] +impl crate::Resettable for PRICTRL0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/dmac/qosctrl.rs b/pac/atsamc20e/src/dmac/qosctrl.rs new file mode 100644 index 000000000000..016fcaa221ef --- /dev/null +++ b/pac/atsamc20e/src/dmac/qosctrl.rs @@ -0,0 +1,402 @@ +#[doc = "Register `QOSCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `QOSCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Write-Back Quality of Service\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WRBQOS_A { + #[doc = "0: Background (no sensitive operation)"] + DISABLE = 0, + #[doc = "1: Sensitive Bandwidth"] + LOW = 1, + #[doc = "2: Sensitive Latency"] + MEDIUM = 2, + #[doc = "3: Critical Latency"] + HIGH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WRBQOS_A) -> Self { + variant as _ + } +} +#[doc = "Field `WRBQOS` reader - Write-Back Quality of Service"] +pub struct WRBQOS_R(crate::FieldReader); +impl WRBQOS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WRBQOS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> WRBQOS_A { + match self.bits { + 0 => WRBQOS_A::DISABLE, + 1 => WRBQOS_A::LOW, + 2 => WRBQOS_A::MEDIUM, + 3 => WRBQOS_A::HIGH, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == WRBQOS_A::DISABLE + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == WRBQOS_A::LOW + } + #[doc = "Checks if the value of the field is `MEDIUM`"] + #[inline(always)] + pub fn is_medium(&self) -> bool { + **self == WRBQOS_A::MEDIUM + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == WRBQOS_A::HIGH + } +} +impl core::ops::Deref for WRBQOS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WRBQOS` writer - Write-Back Quality of Service"] +pub struct WRBQOS_W<'a> { + w: &'a mut W, +} +impl<'a> WRBQOS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WRBQOS_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Background (no sensitive operation)"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(WRBQOS_A::DISABLE) + } + #[doc = "Sensitive Bandwidth"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(WRBQOS_A::LOW) + } + #[doc = "Sensitive Latency"] + #[inline(always)] + pub fn medium(self) -> &'a mut W { + self.variant(WRBQOS_A::MEDIUM) + } + #[doc = "Critical Latency"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(WRBQOS_A::HIGH) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u8 & 0x03); + self.w + } +} +#[doc = "Fetch Quality of Service\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FQOS_A { + #[doc = "0: Background (no sensitive operation)"] + DISABLE = 0, + #[doc = "1: Sensitive Bandwidth"] + LOW = 1, + #[doc = "2: Sensitive Latency"] + MEDIUM = 2, + #[doc = "3: Critical Latency"] + HIGH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FQOS_A) -> Self { + variant as _ + } +} +#[doc = "Field `FQOS` reader - Fetch Quality of Service"] +pub struct FQOS_R(crate::FieldReader); +impl FQOS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FQOS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FQOS_A { + match self.bits { + 0 => FQOS_A::DISABLE, + 1 => FQOS_A::LOW, + 2 => FQOS_A::MEDIUM, + 3 => FQOS_A::HIGH, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == FQOS_A::DISABLE + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == FQOS_A::LOW + } + #[doc = "Checks if the value of the field is `MEDIUM`"] + #[inline(always)] + pub fn is_medium(&self) -> bool { + **self == FQOS_A::MEDIUM + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == FQOS_A::HIGH + } +} +impl core::ops::Deref for FQOS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FQOS` writer - Fetch Quality of Service"] +pub struct FQOS_W<'a> { + w: &'a mut W, +} +impl<'a> FQOS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FQOS_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Background (no sensitive operation)"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(FQOS_A::DISABLE) + } + #[doc = "Sensitive Bandwidth"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(FQOS_A::LOW) + } + #[doc = "Sensitive Latency"] + #[inline(always)] + pub fn medium(self) -> &'a mut W { + self.variant(FQOS_A::MEDIUM) + } + #[doc = "Critical Latency"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(FQOS_A::HIGH) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u8 & 0x03) << 2); + self.w + } +} +#[doc = "Data Transfer Quality of Service\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DQOS_A { + #[doc = "0: Background (no sensitive operation)"] + DISABLE = 0, + #[doc = "1: Sensitive Bandwidth"] + LOW = 1, + #[doc = "2: Sensitive Latency"] + MEDIUM = 2, + #[doc = "3: Critical Latency"] + HIGH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DQOS_A) -> Self { + variant as _ + } +} +#[doc = "Field `DQOS` reader - Data Transfer Quality of Service"] +pub struct DQOS_R(crate::FieldReader); +impl DQOS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DQOS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DQOS_A { + match self.bits { + 0 => DQOS_A::DISABLE, + 1 => DQOS_A::LOW, + 2 => DQOS_A::MEDIUM, + 3 => DQOS_A::HIGH, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == DQOS_A::DISABLE + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == DQOS_A::LOW + } + #[doc = "Checks if the value of the field is `MEDIUM`"] + #[inline(always)] + pub fn is_medium(&self) -> bool { + **self == DQOS_A::MEDIUM + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == DQOS_A::HIGH + } +} +impl core::ops::Deref for DQOS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DQOS` writer - Data Transfer Quality of Service"] +pub struct DQOS_W<'a> { + w: &'a mut W, +} +impl<'a> DQOS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DQOS_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Background (no sensitive operation)"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(DQOS_A::DISABLE) + } + #[doc = "Sensitive Bandwidth"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(DQOS_A::LOW) + } + #[doc = "Sensitive Latency"] + #[inline(always)] + pub fn medium(self) -> &'a mut W { + self.variant(DQOS_A::MEDIUM) + } + #[doc = "Critical Latency"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(DQOS_A::HIGH) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u8 & 0x03) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Write-Back Quality of Service"] + #[inline(always)] + pub fn wrbqos(&self) -> WRBQOS_R { + WRBQOS_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bits 2:3 - Fetch Quality of Service"] + #[inline(always)] + pub fn fqos(&self) -> FQOS_R { + FQOS_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bits 4:5 - Data Transfer Quality of Service"] + #[inline(always)] + pub fn dqos(&self) -> DQOS_R { + DQOS_R::new(((self.bits >> 4) & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Write-Back Quality of Service"] + #[inline(always)] + pub fn wrbqos(&mut self) -> WRBQOS_W { + WRBQOS_W { w: self } + } + #[doc = "Bits 2:3 - Fetch Quality of Service"] + #[inline(always)] + pub fn fqos(&mut self) -> FQOS_W { + FQOS_W { w: self } + } + #[doc = "Bits 4:5 - Data Transfer Quality of Service"] + #[inline(always)] + pub fn dqos(&mut self) -> DQOS_W { + DQOS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "QOS Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [qosctrl](index.html) module"] +pub struct QOSCTRL_SPEC; +impl crate::RegisterSpec for QOSCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [qosctrl::R](R) reader structure"] +impl crate::Readable for QOSCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [qosctrl::W](W) writer structure"] +impl crate::Writable for QOSCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets QOSCTRL to value 0x2a"] +impl crate::Resettable for QOSCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x2a + } +} diff --git a/pac/atsamc20e/src/dmac/swtrigctrl.rs b/pac/atsamc20e/src/dmac/swtrigctrl.rs new file mode 100644 index 000000000000..ada7d633a376 --- /dev/null +++ b/pac/atsamc20e/src/dmac/swtrigctrl.rs @@ -0,0 +1,348 @@ +#[doc = "Register `SWTRIGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SWTRIGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWTRIG0` reader - Channel 0 Software Trigger"] +pub struct SWTRIG0_R(crate::FieldReader); +impl SWTRIG0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG0` writer - Channel 0 Software Trigger"] +pub struct SWTRIG0_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `SWTRIG1` reader - Channel 1 Software Trigger"] +pub struct SWTRIG1_R(crate::FieldReader); +impl SWTRIG1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG1` writer - Channel 1 Software Trigger"] +pub struct SWTRIG1_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SWTRIG2` reader - Channel 2 Software Trigger"] +pub struct SWTRIG2_R(crate::FieldReader); +impl SWTRIG2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG2` writer - Channel 2 Software Trigger"] +pub struct SWTRIG2_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SWTRIG3` reader - Channel 3 Software Trigger"] +pub struct SWTRIG3_R(crate::FieldReader); +impl SWTRIG3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG3` writer - Channel 3 Software Trigger"] +pub struct SWTRIG3_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `SWTRIG4` reader - Channel 4 Software Trigger"] +pub struct SWTRIG4_R(crate::FieldReader); +impl SWTRIG4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG4` writer - Channel 4 Software Trigger"] +pub struct SWTRIG4_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `SWTRIG5` reader - Channel 5 Software Trigger"] +pub struct SWTRIG5_R(crate::FieldReader); +impl SWTRIG5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG5` writer - Channel 5 Software Trigger"] +pub struct SWTRIG5_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Channel 0 Software Trigger"] + #[inline(always)] + pub fn swtrig0(&self) -> SWTRIG0_R { + SWTRIG0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel 1 Software Trigger"] + #[inline(always)] + pub fn swtrig1(&self) -> SWTRIG1_R { + SWTRIG1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel 2 Software Trigger"] + #[inline(always)] + pub fn swtrig2(&self) -> SWTRIG2_R { + SWTRIG2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Channel 3 Software Trigger"] + #[inline(always)] + pub fn swtrig3(&self) -> SWTRIG3_R { + SWTRIG3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Channel 4 Software Trigger"] + #[inline(always)] + pub fn swtrig4(&self) -> SWTRIG4_R { + SWTRIG4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Channel 5 Software Trigger"] + #[inline(always)] + pub fn swtrig5(&self) -> SWTRIG5_R { + SWTRIG5_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel 0 Software Trigger"] + #[inline(always)] + pub fn swtrig0(&mut self) -> SWTRIG0_W { + SWTRIG0_W { w: self } + } + #[doc = "Bit 1 - Channel 1 Software Trigger"] + #[inline(always)] + pub fn swtrig1(&mut self) -> SWTRIG1_W { + SWTRIG1_W { w: self } + } + #[doc = "Bit 2 - Channel 2 Software Trigger"] + #[inline(always)] + pub fn swtrig2(&mut self) -> SWTRIG2_W { + SWTRIG2_W { w: self } + } + #[doc = "Bit 3 - Channel 3 Software Trigger"] + #[inline(always)] + pub fn swtrig3(&mut self) -> SWTRIG3_W { + SWTRIG3_W { w: self } + } + #[doc = "Bit 4 - Channel 4 Software Trigger"] + #[inline(always)] + pub fn swtrig4(&mut self) -> SWTRIG4_W { + SWTRIG4_W { w: self } + } + #[doc = "Bit 5 - Channel 5 Software Trigger"] + #[inline(always)] + pub fn swtrig5(&mut self) -> SWTRIG5_W { + SWTRIG5_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Software Trigger Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [swtrigctrl](index.html) module"] +pub struct SWTRIGCTRL_SPEC; +impl crate::RegisterSpec for SWTRIGCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [swtrigctrl::R](R) reader structure"] +impl crate::Readable for SWTRIGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [swtrigctrl::W](W) writer structure"] +impl crate::Writable for SWTRIGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SWTRIGCTRL to value 0"] +impl crate::Resettable for SWTRIGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/dmac/wrbaddr.rs b/pac/atsamc20e/src/dmac/wrbaddr.rs new file mode 100644 index 000000000000..ccf2a376b853 --- /dev/null +++ b/pac/atsamc20e/src/dmac/wrbaddr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `WRBADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WRBADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WRBADDR` reader - Write-Back Memory Base Address"] +pub struct WRBADDR_R(crate::FieldReader); +impl WRBADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + WRBADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WRBADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WRBADDR` writer - Write-Back Memory Base Address"] +pub struct WRBADDR_W<'a> { + w: &'a mut W, +} +impl<'a> WRBADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Write-Back Memory Base Address"] + #[inline(always)] + pub fn wrbaddr(&self) -> WRBADDR_R { + WRBADDR_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Write-Back Memory Base Address"] + #[inline(always)] + pub fn wrbaddr(&mut self) -> WRBADDR_W { + WRBADDR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Write-Back Memory Section Base Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wrbaddr](index.html) module"] +pub struct WRBADDR_SPEC; +impl crate::RegisterSpec for WRBADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [wrbaddr::R](R) reader structure"] +impl crate::Readable for WRBADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wrbaddr::W](W) writer structure"] +impl crate::Writable for WRBADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WRBADDR to value 0"] +impl crate::Resettable for WRBADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/dsu.rs b/pac/atsamc20e/src/dsu.rs new file mode 100644 index 000000000000..88324f764961 --- /dev/null +++ b/pac/atsamc20e/src/dsu.rs @@ -0,0 +1,163 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrl: crate::Reg, + #[doc = "0x01 - Status A"] + pub statusa: crate::Reg, + #[doc = "0x02 - Status B"] + pub statusb: crate::Reg, + #[doc = "0x03 - Status C"] + pub statusc: crate::Reg, + #[doc = "0x04 - Address"] + pub addr: crate::Reg, + #[doc = "0x08 - Length"] + pub length: crate::Reg, + #[doc = "0x0c - Data"] + pub data: crate::Reg, + #[doc = "0x10..0x18 - Debug Communication Channel n"] + pub dcc: [crate::Reg; 2], + #[doc = "0x18 - Device Identification"] + pub did: crate::Reg, + _reserved9: [u8; 0xd4], + #[doc = "0xf0..0xf8 - Device Configuration"] + pub dcfg: [crate::Reg; 2], + _reserved10: [u8; 0x0f08], + #[doc = "0x1000 - CoreSight ROM Table Entry 0"] + pub entry0: crate::Reg, + #[doc = "0x1004 - CoreSight ROM Table Entry 1"] + pub entry1: crate::Reg, + #[doc = "0x1008 - CoreSight ROM Table End"] + pub end: crate::Reg, + _reserved13: [u8; 0x0fc0], + #[doc = "0x1fcc - CoreSight ROM Table Memory Type"] + pub memtype: crate::Reg, + #[doc = "0x1fd0 - Peripheral Identification 4"] + pub pid4: crate::Reg, + #[doc = "0x1fd4 - Peripheral Identification 5"] + pub pid5: crate::Reg, + #[doc = "0x1fd8 - Peripheral Identification 6"] + pub pid6: crate::Reg, + #[doc = "0x1fdc - Peripheral Identification 7"] + pub pid7: crate::Reg, + #[doc = "0x1fe0 - Peripheral Identification 0"] + pub pid0: crate::Reg, + #[doc = "0x1fe4 - Peripheral Identification 1"] + pub pid1: crate::Reg, + #[doc = "0x1fe8 - Peripheral Identification 2"] + pub pid2: crate::Reg, + #[doc = "0x1fec - Peripheral Identification 3"] + pub pid3: crate::Reg, + #[doc = "0x1ff0 - Component Identification 0"] + pub cid0: crate::Reg, + #[doc = "0x1ff4 - Component Identification 1"] + pub cid1: crate::Reg, + #[doc = "0x1ff8 - Component Identification 2"] + pub cid2: crate::Reg, + #[doc = "0x1ffc - Component Identification 3"] + pub cid3: crate::Reg, +} +#[doc = "CTRL register accessor: an alias for `Reg`"] +pub type CTRL = crate::Reg; +#[doc = "Control"] +pub mod ctrl; +#[doc = "STATUSA register accessor: an alias for `Reg`"] +pub type STATUSA = crate::Reg; +#[doc = "Status A"] +pub mod statusa; +#[doc = "STATUSB register accessor: an alias for `Reg`"] +pub type STATUSB = crate::Reg; +#[doc = "Status B"] +pub mod statusb; +#[doc = "STATUSC register accessor: an alias for `Reg`"] +pub type STATUSC = crate::Reg; +#[doc = "Status C"] +pub mod statusc; +#[doc = "ADDR register accessor: an alias for `Reg`"] +pub type ADDR = crate::Reg; +#[doc = "Address"] +pub mod addr; +#[doc = "LENGTH register accessor: an alias for `Reg`"] +pub type LENGTH = crate::Reg; +#[doc = "Length"] +pub mod length; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "Data"] +pub mod data; +#[doc = "DCC register accessor: an alias for `Reg`"] +pub type DCC = crate::Reg; +#[doc = "Debug Communication Channel n"] +pub mod dcc; +#[doc = "DID register accessor: an alias for `Reg`"] +pub type DID = crate::Reg; +#[doc = "Device Identification"] +pub mod did; +#[doc = "DCFG register accessor: an alias for `Reg`"] +pub type DCFG = crate::Reg; +#[doc = "Device Configuration"] +pub mod dcfg; +#[doc = "ENTRY0 register accessor: an alias for `Reg`"] +pub type ENTRY0 = crate::Reg; +#[doc = "CoreSight ROM Table Entry 0"] +pub mod entry0; +#[doc = "ENTRY1 register accessor: an alias for `Reg`"] +pub type ENTRY1 = crate::Reg; +#[doc = "CoreSight ROM Table Entry 1"] +pub mod entry1; +#[doc = "END register accessor: an alias for `Reg`"] +pub type END = crate::Reg; +#[doc = "CoreSight ROM Table End"] +pub mod end; +#[doc = "MEMTYPE register accessor: an alias for `Reg`"] +pub type MEMTYPE = crate::Reg; +#[doc = "CoreSight ROM Table Memory Type"] +pub mod memtype; +#[doc = "PID4 register accessor: an alias for `Reg`"] +pub type PID4 = crate::Reg; +#[doc = "Peripheral Identification 4"] +pub mod pid4; +#[doc = "PID5 register accessor: an alias for `Reg`"] +pub type PID5 = crate::Reg; +#[doc = "Peripheral Identification 5"] +pub mod pid5; +#[doc = "PID6 register accessor: an alias for `Reg`"] +pub type PID6 = crate::Reg; +#[doc = "Peripheral Identification 6"] +pub mod pid6; +#[doc = "PID7 register accessor: an alias for `Reg`"] +pub type PID7 = crate::Reg; +#[doc = "Peripheral Identification 7"] +pub mod pid7; +#[doc = "PID0 register accessor: an alias for `Reg`"] +pub type PID0 = crate::Reg; +#[doc = "Peripheral Identification 0"] +pub mod pid0; +#[doc = "PID1 register accessor: an alias for `Reg`"] +pub type PID1 = crate::Reg; +#[doc = "Peripheral Identification 1"] +pub mod pid1; +#[doc = "PID2 register accessor: an alias for `Reg`"] +pub type PID2 = crate::Reg; +#[doc = "Peripheral Identification 2"] +pub mod pid2; +#[doc = "PID3 register accessor: an alias for `Reg`"] +pub type PID3 = crate::Reg; +#[doc = "Peripheral Identification 3"] +pub mod pid3; +#[doc = "CID0 register accessor: an alias for `Reg`"] +pub type CID0 = crate::Reg; +#[doc = "Component Identification 0"] +pub mod cid0; +#[doc = "CID1 register accessor: an alias for `Reg`"] +pub type CID1 = crate::Reg; +#[doc = "Component Identification 1"] +pub mod cid1; +#[doc = "CID2 register accessor: an alias for `Reg`"] +pub type CID2 = crate::Reg; +#[doc = "Component Identification 2"] +pub mod cid2; +#[doc = "CID3 register accessor: an alias for `Reg`"] +pub type CID3 = crate::Reg; +#[doc = "Component Identification 3"] +pub mod cid3; diff --git a/pac/atsamc20e/src/dsu/addr.rs b/pac/atsamc20e/src/dsu/addr.rs new file mode 100644 index 000000000000..412f874d6b15 --- /dev/null +++ b/pac/atsamc20e/src/dsu/addr.rs @@ -0,0 +1,140 @@ +#[doc = "Register `ADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `AMOD` reader - Access Mode"] +pub struct AMOD_R(crate::FieldReader); +impl AMOD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + AMOD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AMOD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AMOD` writer - Access Mode"] +pub struct AMOD_W<'a> { + w: &'a mut W, +} +impl<'a> AMOD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u32 & 0x03); + self.w + } +} +#[doc = "Field `ADDR` reader - Address"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - Address"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3fff_ffff << 2)) | ((value as u32 & 0x3fff_ffff) << 2); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Access Mode"] + #[inline(always)] + pub fn amod(&self) -> AMOD_R { + AMOD_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bits 2:31 - Address"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new(((self.bits >> 2) & 0x3fff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:1 - Access Mode"] + #[inline(always)] + pub fn amod(&mut self) -> AMOD_W { + AMOD_W { w: self } + } + #[doc = "Bits 2:31 - Address"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [addr](index.html) module"] +pub struct ADDR_SPEC; +impl crate::RegisterSpec for ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [addr::R](R) reader structure"] +impl crate::Readable for ADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [addr::W](W) writer structure"] +impl crate::Writable for ADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ADDR to value 0"] +impl crate::Resettable for ADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/dsu/cid0.rs b/pac/atsamc20e/src/dsu/cid0.rs new file mode 100644 index 000000000000..b3c2373dfc99 --- /dev/null +++ b/pac/atsamc20e/src/dsu/cid0.rs @@ -0,0 +1,53 @@ +#[doc = "Register `CID0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PREAMBLEB0` reader - Preamble Byte 0"] +pub struct PREAMBLEB0_R(crate::FieldReader); +impl PREAMBLEB0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PREAMBLEB0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PREAMBLEB0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:7 - Preamble Byte 0"] + #[inline(always)] + pub fn preambleb0(&self) -> PREAMBLEB0_R { + PREAMBLEB0_R::new((self.bits & 0xff) as u8) + } +} +#[doc = "Component Identification 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid0](index.html) module"] +pub struct CID0_SPEC; +impl crate::RegisterSpec for CID0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid0::R](R) reader structure"] +impl crate::Readable for CID0_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID0 to value 0x0d"] +impl crate::Resettable for CID0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0d + } +} diff --git a/pac/atsamc20e/src/dsu/cid1.rs b/pac/atsamc20e/src/dsu/cid1.rs new file mode 100644 index 000000000000..3628ceac64a7 --- /dev/null +++ b/pac/atsamc20e/src/dsu/cid1.rs @@ -0,0 +1,73 @@ +#[doc = "Register `CID1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PREAMBLE` reader - Preamble"] +pub struct PREAMBLE_R(crate::FieldReader); +impl PREAMBLE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PREAMBLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PREAMBLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCLASS` reader - Component Class"] +pub struct CCLASS_R(crate::FieldReader); +impl CCLASS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CCLASS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCLASS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:3 - Preamble"] + #[inline(always)] + pub fn preamble(&self) -> PREAMBLE_R { + PREAMBLE_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Component Class"] + #[inline(always)] + pub fn cclass(&self) -> CCLASS_R { + CCLASS_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +#[doc = "Component Identification 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid1](index.html) module"] +pub struct CID1_SPEC; +impl crate::RegisterSpec for CID1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid1::R](R) reader structure"] +impl crate::Readable for CID1_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID1 to value 0x10"] +impl crate::Resettable for CID1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x10 + } +} diff --git a/pac/atsamc20e/src/dsu/cid2.rs b/pac/atsamc20e/src/dsu/cid2.rs new file mode 100644 index 000000000000..714078d5c430 --- /dev/null +++ b/pac/atsamc20e/src/dsu/cid2.rs @@ -0,0 +1,53 @@ +#[doc = "Register `CID2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PREAMBLEB2` reader - Preamble Byte 2"] +pub struct PREAMBLEB2_R(crate::FieldReader); +impl PREAMBLEB2_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PREAMBLEB2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PREAMBLEB2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:7 - Preamble Byte 2"] + #[inline(always)] + pub fn preambleb2(&self) -> PREAMBLEB2_R { + PREAMBLEB2_R::new((self.bits & 0xff) as u8) + } +} +#[doc = "Component Identification 2\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid2](index.html) module"] +pub struct CID2_SPEC; +impl crate::RegisterSpec for CID2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid2::R](R) reader structure"] +impl crate::Readable for CID2_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID2 to value 0x05"] +impl crate::Resettable for CID2_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x05 + } +} diff --git a/pac/atsamc20e/src/dsu/cid3.rs b/pac/atsamc20e/src/dsu/cid3.rs new file mode 100644 index 000000000000..a345af7b5166 --- /dev/null +++ b/pac/atsamc20e/src/dsu/cid3.rs @@ -0,0 +1,53 @@ +#[doc = "Register `CID3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PREAMBLEB3` reader - Preamble Byte 3"] +pub struct PREAMBLEB3_R(crate::FieldReader); +impl PREAMBLEB3_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PREAMBLEB3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PREAMBLEB3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:7 - Preamble Byte 3"] + #[inline(always)] + pub fn preambleb3(&self) -> PREAMBLEB3_R { + PREAMBLEB3_R::new((self.bits & 0xff) as u8) + } +} +#[doc = "Component Identification 3\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid3](index.html) module"] +pub struct CID3_SPEC; +impl crate::RegisterSpec for CID3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid3::R](R) reader structure"] +impl crate::Readable for CID3_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID3 to value 0xb1"] +impl crate::Resettable for CID3_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xb1 + } +} diff --git a/pac/atsamc20e/src/dsu/ctrl.rs b/pac/atsamc20e/src/dsu/ctrl.rs new file mode 100644 index 000000000000..0a19db5a5239 --- /dev/null +++ b/pac/atsamc20e/src/dsu/ctrl.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `CRC` writer - 32-bit Cyclic Redundancy Code"] +pub struct CRC_W<'a> { + w: &'a mut W, +} +impl<'a> CRC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `MBIST` writer - Memory built-in self-test"] +pub struct MBIST_W<'a> { + w: &'a mut W, +} +impl<'a> MBIST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CE` writer - Chip-Erase"] +pub struct CE_W<'a> { + w: &'a mut W, +} +impl<'a> CE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `ARR` writer - Auxiliary Row Read"] +pub struct ARR_W<'a> { + w: &'a mut W, +} +impl<'a> ARR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +#[doc = "Field `SMSA` writer - Start Memory Stream Access"] +pub struct SMSA_W<'a> { + w: &'a mut W, +} +impl<'a> SMSA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 2 - 32-bit Cyclic Redundancy Code"] + #[inline(always)] + pub fn crc(&mut self) -> CRC_W { + CRC_W { w: self } + } + #[doc = "Bit 3 - Memory built-in self-test"] + #[inline(always)] + pub fn mbist(&mut self) -> MBIST_W { + MBIST_W { w: self } + } + #[doc = "Bit 4 - Chip-Erase"] + #[inline(always)] + pub fn ce(&mut self) -> CE_W { + CE_W { w: self } + } + #[doc = "Bit 6 - Auxiliary Row Read"] + #[inline(always)] + pub fn arr(&mut self) -> ARR_W { + ARR_W { w: self } + } + #[doc = "Bit 7 - Start Memory Stream Access"] + #[inline(always)] + pub fn smsa(&mut self) -> SMSA_W { + SMSA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"] +pub struct CTRL_SPEC; +impl crate::RegisterSpec for CTRL_SPEC { + type Ux = u8; +} +#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"] +impl crate::Writable for CTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/dsu/data.rs b/pac/atsamc20e/src/dsu/data.rs new file mode 100644 index 000000000000..193cc49a07fd --- /dev/null +++ b/pac/atsamc20e/src/dsu/data.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Data"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Data"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/dsu/dcc.rs b/pac/atsamc20e/src/dsu/dcc.rs new file mode 100644 index 000000000000..354323a499ef --- /dev/null +++ b/pac/atsamc20e/src/dsu/dcc.rs @@ -0,0 +1,104 @@ +#[doc = "Register `DCC[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DCC[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Data"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Data"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Communication Channel n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dcc](index.html) module"] +pub struct DCC_SPEC; +impl crate::RegisterSpec for DCC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dcc::R](R) reader structure"] +impl crate::Readable for DCC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dcc::W](W) writer structure"] +impl crate::Writable for DCC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DCC[%s] +to value 0"] +impl crate::Resettable for DCC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/dsu/dcfg.rs b/pac/atsamc20e/src/dsu/dcfg.rs new file mode 100644 index 000000000000..c6d61d0b496e --- /dev/null +++ b/pac/atsamc20e/src/dsu/dcfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `DCFG[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DCFG[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DCFG` reader - Device Configuration"] +pub struct DCFG_R(crate::FieldReader); +impl DCFG_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + DCFG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DCFG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DCFG` writer - Device Configuration"] +pub struct DCFG_W<'a> { + w: &'a mut W, +} +impl<'a> DCFG_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Device Configuration"] + #[inline(always)] + pub fn dcfg(&self) -> DCFG_R { + DCFG_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Device Configuration"] + #[inline(always)] + pub fn dcfg(&mut self) -> DCFG_W { + DCFG_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Device Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dcfg](index.html) module"] +pub struct DCFG_SPEC; +impl crate::RegisterSpec for DCFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dcfg::R](R) reader structure"] +impl crate::Readable for DCFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dcfg::W](W) writer structure"] +impl crate::Writable for DCFG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DCFG[%s] +to value 0"] +impl crate::Resettable for DCFG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/dsu/did.rs b/pac/atsamc20e/src/dsu/did.rs new file mode 100644 index 000000000000..de80bad50358 --- /dev/null +++ b/pac/atsamc20e/src/dsu/did.rs @@ -0,0 +1,279 @@ +#[doc = "Register `DID` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `DEVSEL` reader - Device Select"] +pub struct DEVSEL_R(crate::FieldReader); +impl DEVSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DEVSEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DEVSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REVISION` reader - Revision Number"] +pub struct REVISION_R(crate::FieldReader); +impl REVISION_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REVISION_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REVISION_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIE` reader - Die Number"] +pub struct DIE_R(crate::FieldReader); +impl DIE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DIE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Series\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SERIES_A { + #[doc = "0: Cortex-M0+ processor, basic feature set"] + _0 = 0, + #[doc = "1: Cortex-M0+ processor, CAN"] + _1 = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SERIES_A) -> Self { + variant as _ + } +} +#[doc = "Field `SERIES` reader - Series"] +pub struct SERIES_R(crate::FieldReader); +impl SERIES_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SERIES_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SERIES_A::_0), + 1 => Some(SERIES_A::_1), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_0`"] + #[inline(always)] + pub fn is_0(&self) -> bool { + **self == SERIES_A::_0 + } + #[doc = "Checks if the value of the field is `_1`"] + #[inline(always)] + pub fn is_1(&self) -> bool { + **self == SERIES_A::_1 + } +} +impl core::ops::Deref for SERIES_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Family\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FAMILY_A { + #[doc = "0: General purpose microcontroller"] + _0 = 0, + #[doc = "1: PicoPower"] + _1 = 1, + #[doc = "2: 5V Industrial"] + _2 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FAMILY_A) -> Self { + variant as _ + } +} +#[doc = "Field `FAMILY` reader - Family"] +pub struct FAMILY_R(crate::FieldReader); +impl FAMILY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FAMILY_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(FAMILY_A::_0), + 1 => Some(FAMILY_A::_1), + 2 => Some(FAMILY_A::_2), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_0`"] + #[inline(always)] + pub fn is_0(&self) -> bool { + **self == FAMILY_A::_0 + } + #[doc = "Checks if the value of the field is `_1`"] + #[inline(always)] + pub fn is_1(&self) -> bool { + **self == FAMILY_A::_1 + } + #[doc = "Checks if the value of the field is `_2`"] + #[inline(always)] + pub fn is_2(&self) -> bool { + **self == FAMILY_A::_2 + } +} +impl core::ops::Deref for FAMILY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Processor\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PROCESSOR_A { + #[doc = "0: Cortex-M0"] + _0 = 0, + #[doc = "1: Cortex-M0+"] + _1 = 1, + #[doc = "2: Cortex-M3"] + _2 = 2, + #[doc = "3: Cortex-M4"] + _3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PROCESSOR_A) -> Self { + variant as _ + } +} +#[doc = "Field `PROCESSOR` reader - Processor"] +pub struct PROCESSOR_R(crate::FieldReader); +impl PROCESSOR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PROCESSOR_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PROCESSOR_A::_0), + 1 => Some(PROCESSOR_A::_1), + 2 => Some(PROCESSOR_A::_2), + 3 => Some(PROCESSOR_A::_3), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_0`"] + #[inline(always)] + pub fn is_0(&self) -> bool { + **self == PROCESSOR_A::_0 + } + #[doc = "Checks if the value of the field is `_1`"] + #[inline(always)] + pub fn is_1(&self) -> bool { + **self == PROCESSOR_A::_1 + } + #[doc = "Checks if the value of the field is `_2`"] + #[inline(always)] + pub fn is_2(&self) -> bool { + **self == PROCESSOR_A::_2 + } + #[doc = "Checks if the value of the field is `_3`"] + #[inline(always)] + pub fn is_3(&self) -> bool { + **self == PROCESSOR_A::_3 + } +} +impl core::ops::Deref for PROCESSOR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:7 - Device Select"] + #[inline(always)] + pub fn devsel(&self) -> DEVSEL_R { + DEVSEL_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:11 - Revision Number"] + #[inline(always)] + pub fn revision(&self) -> REVISION_R { + REVISION_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - Die Number"] + #[inline(always)] + pub fn die(&self) -> DIE_R { + DIE_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:21 - Series"] + #[inline(always)] + pub fn series(&self) -> SERIES_R { + SERIES_R::new(((self.bits >> 16) & 0x3f) as u8) + } + #[doc = "Bits 23:27 - Family"] + #[inline(always)] + pub fn family(&self) -> FAMILY_R { + FAMILY_R::new(((self.bits >> 23) & 0x1f) as u8) + } + #[doc = "Bits 28:31 - Processor"] + #[inline(always)] + pub fn processor(&self) -> PROCESSOR_R { + PROCESSOR_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +#[doc = "Device Identification\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [did](index.html) module"] +pub struct DID_SPEC; +impl crate::RegisterSpec for DID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [did::R](R) reader structure"] +impl crate::Readable for DID_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DID to value 0x1100_050a"] +impl crate::Resettable for DID_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x1100_050a + } +} diff --git a/pac/atsamc20e/src/dsu/end.rs b/pac/atsamc20e/src/dsu/end.rs new file mode 100644 index 000000000000..cce2edea2bce --- /dev/null +++ b/pac/atsamc20e/src/dsu/end.rs @@ -0,0 +1,53 @@ +#[doc = "Register `END` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `END` reader - End Marker"] +pub struct END_R(crate::FieldReader); +impl END_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + END_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for END_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - End Marker"] + #[inline(always)] + pub fn end(&self) -> END_R { + END_R::new(self.bits as u32) + } +} +#[doc = "CoreSight ROM Table End\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [end](index.html) module"] +pub struct END_SPEC; +impl crate::RegisterSpec for END_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [end::R](R) reader structure"] +impl crate::Readable for END_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets END to value 0"] +impl crate::Resettable for END_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/dsu/entry0.rs b/pac/atsamc20e/src/dsu/entry0.rs new file mode 100644 index 000000000000..d8563990e827 --- /dev/null +++ b/pac/atsamc20e/src/dsu/entry0.rs @@ -0,0 +1,93 @@ +#[doc = "Register `ENTRY0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `EPRES` reader - Entry Present"] +pub struct EPRES_R(crate::FieldReader); +impl EPRES_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EPRES_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EPRES_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FMT` reader - Format"] +pub struct FMT_R(crate::FieldReader); +impl FMT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FMT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FMT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDOFF` reader - Address Offset"] +pub struct ADDOFF_R(crate::FieldReader); +impl ADDOFF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + ADDOFF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDOFF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Entry Present"] + #[inline(always)] + pub fn epres(&self) -> EPRES_R { + EPRES_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Format"] + #[inline(always)] + pub fn fmt(&self) -> FMT_R { + FMT_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 12:31 - Address Offset"] + #[inline(always)] + pub fn addoff(&self) -> ADDOFF_R { + ADDOFF_R::new(((self.bits >> 12) & 0x000f_ffff) as u32) + } +} +#[doc = "CoreSight ROM Table Entry 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [entry0](index.html) module"] +pub struct ENTRY0_SPEC; +impl crate::RegisterSpec for ENTRY0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [entry0::R](R) reader structure"] +impl crate::Readable for ENTRY0_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets ENTRY0 to value 0x9f0f_c002"] +impl crate::Resettable for ENTRY0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x9f0f_c002 + } +} diff --git a/pac/atsamc20e/src/dsu/entry1.rs b/pac/atsamc20e/src/dsu/entry1.rs new file mode 100644 index 000000000000..cec8fa367705 --- /dev/null +++ b/pac/atsamc20e/src/dsu/entry1.rs @@ -0,0 +1,31 @@ +#[doc = "Register `ENTRY1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "CoreSight ROM Table Entry 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [entry1](index.html) module"] +pub struct ENTRY1_SPEC; +impl crate::RegisterSpec for ENTRY1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [entry1::R](R) reader structure"] +impl crate::Readable for ENTRY1_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets ENTRY1 to value 0x5002"] +impl crate::Resettable for ENTRY1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x5002 + } +} diff --git a/pac/atsamc20e/src/dsu/length.rs b/pac/atsamc20e/src/dsu/length.rs new file mode 100644 index 000000000000..2dc771f74dfd --- /dev/null +++ b/pac/atsamc20e/src/dsu/length.rs @@ -0,0 +1,103 @@ +#[doc = "Register `LENGTH` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `LENGTH` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `LENGTH` reader - Length"] +pub struct LENGTH_R(crate::FieldReader); +impl LENGTH_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + LENGTH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LENGTH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LENGTH` writer - Length"] +pub struct LENGTH_W<'a> { + w: &'a mut W, +} +impl<'a> LENGTH_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3fff_ffff << 2)) | ((value as u32 & 0x3fff_ffff) << 2); + self.w + } +} +impl R { + #[doc = "Bits 2:31 - Length"] + #[inline(always)] + pub fn length(&self) -> LENGTH_R { + LENGTH_R::new(((self.bits >> 2) & 0x3fff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 2:31 - Length"] + #[inline(always)] + pub fn length(&mut self) -> LENGTH_W { + LENGTH_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Length\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [length](index.html) module"] +pub struct LENGTH_SPEC; +impl crate::RegisterSpec for LENGTH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [length::R](R) reader structure"] +impl crate::Readable for LENGTH_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [length::W](W) writer structure"] +impl crate::Writable for LENGTH_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets LENGTH to value 0"] +impl crate::Resettable for LENGTH_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/dsu/memtype.rs b/pac/atsamc20e/src/dsu/memtype.rs new file mode 100644 index 000000000000..3cc841e2ba78 --- /dev/null +++ b/pac/atsamc20e/src/dsu/memtype.rs @@ -0,0 +1,53 @@ +#[doc = "Register `MEMTYPE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SMEMP` reader - System Memory Present"] +pub struct SMEMP_R(crate::FieldReader); +impl SMEMP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SMEMP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SMEMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - System Memory Present"] + #[inline(always)] + pub fn smemp(&self) -> SMEMP_R { + SMEMP_R::new((self.bits & 0x01) != 0) + } +} +#[doc = "CoreSight ROM Table Memory Type\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [memtype](index.html) module"] +pub struct MEMTYPE_SPEC; +impl crate::RegisterSpec for MEMTYPE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [memtype::R](R) reader structure"] +impl crate::Readable for MEMTYPE_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets MEMTYPE to value 0"] +impl crate::Resettable for MEMTYPE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/dsu/pid0.rs b/pac/atsamc20e/src/dsu/pid0.rs new file mode 100644 index 000000000000..98028ea62838 --- /dev/null +++ b/pac/atsamc20e/src/dsu/pid0.rs @@ -0,0 +1,53 @@ +#[doc = "Register `PID0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PARTNBL` reader - Part Number Low"] +pub struct PARTNBL_R(crate::FieldReader); +impl PARTNBL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PARTNBL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PARTNBL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:7 - Part Number Low"] + #[inline(always)] + pub fn partnbl(&self) -> PARTNBL_R { + PARTNBL_R::new((self.bits & 0xff) as u8) + } +} +#[doc = "Peripheral Identification 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid0](index.html) module"] +pub struct PID0_SPEC; +impl crate::RegisterSpec for PID0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid0::R](R) reader structure"] +impl crate::Readable for PID0_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID0 to value 0xd0"] +impl crate::Resettable for PID0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xd0 + } +} diff --git a/pac/atsamc20e/src/dsu/pid1.rs b/pac/atsamc20e/src/dsu/pid1.rs new file mode 100644 index 000000000000..4f94b853507c --- /dev/null +++ b/pac/atsamc20e/src/dsu/pid1.rs @@ -0,0 +1,73 @@ +#[doc = "Register `PID1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PARTNBH` reader - Part Number High"] +pub struct PARTNBH_R(crate::FieldReader); +impl PARTNBH_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PARTNBH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PARTNBH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `JEPIDCL` reader - Low part of the JEP-106 Identity Code"] +pub struct JEPIDCL_R(crate::FieldReader); +impl JEPIDCL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + JEPIDCL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for JEPIDCL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:3 - Part Number High"] + #[inline(always)] + pub fn partnbh(&self) -> PARTNBH_R { + PARTNBH_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Low part of the JEP-106 Identity Code"] + #[inline(always)] + pub fn jepidcl(&self) -> JEPIDCL_R { + JEPIDCL_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +#[doc = "Peripheral Identification 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid1](index.html) module"] +pub struct PID1_SPEC; +impl crate::RegisterSpec for PID1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid1::R](R) reader structure"] +impl crate::Readable for PID1_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID1 to value 0xfc"] +impl crate::Resettable for PID1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xfc + } +} diff --git a/pac/atsamc20e/src/dsu/pid2.rs b/pac/atsamc20e/src/dsu/pid2.rs new file mode 100644 index 000000000000..d8f8ed10192e --- /dev/null +++ b/pac/atsamc20e/src/dsu/pid2.rs @@ -0,0 +1,93 @@ +#[doc = "Register `PID2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `JEPIDCH` reader - JEP-106 Identity Code High"] +pub struct JEPIDCH_R(crate::FieldReader); +impl JEPIDCH_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + JEPIDCH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for JEPIDCH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `JEPU` reader - JEP-106 Identity Code is used"] +pub struct JEPU_R(crate::FieldReader); +impl JEPU_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + JEPU_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for JEPU_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REVISION` reader - Revision Number"] +pub struct REVISION_R(crate::FieldReader); +impl REVISION_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REVISION_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REVISION_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:2 - JEP-106 Identity Code High"] + #[inline(always)] + pub fn jepidch(&self) -> JEPIDCH_R { + JEPIDCH_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 3 - JEP-106 Identity Code is used"] + #[inline(always)] + pub fn jepu(&self) -> JEPU_R { + JEPU_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bits 4:7 - Revision Number"] + #[inline(always)] + pub fn revision(&self) -> REVISION_R { + REVISION_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +#[doc = "Peripheral Identification 2\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid2](index.html) module"] +pub struct PID2_SPEC; +impl crate::RegisterSpec for PID2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid2::R](R) reader structure"] +impl crate::Readable for PID2_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID2 to value 0x09"] +impl crate::Resettable for PID2_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x09 + } +} diff --git a/pac/atsamc20e/src/dsu/pid3.rs b/pac/atsamc20e/src/dsu/pid3.rs new file mode 100644 index 000000000000..c0a8fb2d7f92 --- /dev/null +++ b/pac/atsamc20e/src/dsu/pid3.rs @@ -0,0 +1,73 @@ +#[doc = "Register `PID3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `CUSMOD` reader - ARM CUSMOD"] +pub struct CUSMOD_R(crate::FieldReader); +impl CUSMOD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CUSMOD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CUSMOD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REVAND` reader - Revision Number"] +pub struct REVAND_R(crate::FieldReader); +impl REVAND_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REVAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REVAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:3 - ARM CUSMOD"] + #[inline(always)] + pub fn cusmod(&self) -> CUSMOD_R { + CUSMOD_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Revision Number"] + #[inline(always)] + pub fn revand(&self) -> REVAND_R { + REVAND_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +#[doc = "Peripheral Identification 3\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid3](index.html) module"] +pub struct PID3_SPEC; +impl crate::RegisterSpec for PID3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid3::R](R) reader structure"] +impl crate::Readable for PID3_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID3 to value 0"] +impl crate::Resettable for PID3_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/dsu/pid4.rs b/pac/atsamc20e/src/dsu/pid4.rs new file mode 100644 index 000000000000..d3a1bd120f0b --- /dev/null +++ b/pac/atsamc20e/src/dsu/pid4.rs @@ -0,0 +1,73 @@ +#[doc = "Register `PID4` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `JEPCC` reader - JEP-106 Continuation Code"] +pub struct JEPCC_R(crate::FieldReader); +impl JEPCC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + JEPCC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for JEPCC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FKBC` reader - 4KB count"] +pub struct FKBC_R(crate::FieldReader); +impl FKBC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FKBC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FKBC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:3 - JEP-106 Continuation Code"] + #[inline(always)] + pub fn jepcc(&self) -> JEPCC_R { + JEPCC_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - 4KB count"] + #[inline(always)] + pub fn fkbc(&self) -> FKBC_R { + FKBC_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +#[doc = "Peripheral Identification 4\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid4](index.html) module"] +pub struct PID4_SPEC; +impl crate::RegisterSpec for PID4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid4::R](R) reader structure"] +impl crate::Readable for PID4_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID4 to value 0"] +impl crate::Resettable for PID4_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/dsu/pid5.rs b/pac/atsamc20e/src/dsu/pid5.rs new file mode 100644 index 000000000000..d343d4800b95 --- /dev/null +++ b/pac/atsamc20e/src/dsu/pid5.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID5` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 5\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid5](index.html) module"] +pub struct PID5_SPEC; +impl crate::RegisterSpec for PID5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid5::R](R) reader structure"] +impl crate::Readable for PID5_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID5 to value 0"] +impl crate::Resettable for PID5_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/dsu/pid6.rs b/pac/atsamc20e/src/dsu/pid6.rs new file mode 100644 index 000000000000..55cc2b8b5861 --- /dev/null +++ b/pac/atsamc20e/src/dsu/pid6.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID6` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 6\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid6](index.html) module"] +pub struct PID6_SPEC; +impl crate::RegisterSpec for PID6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid6::R](R) reader structure"] +impl crate::Readable for PID6_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID6 to value 0"] +impl crate::Resettable for PID6_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/dsu/pid7.rs b/pac/atsamc20e/src/dsu/pid7.rs new file mode 100644 index 000000000000..77664d4f2f95 --- /dev/null +++ b/pac/atsamc20e/src/dsu/pid7.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID7` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 7\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid7](index.html) module"] +pub struct PID7_SPEC; +impl crate::RegisterSpec for PID7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid7::R](R) reader structure"] +impl crate::Readable for PID7_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID7 to value 0"] +impl crate::Resettable for PID7_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/dsu/statusa.rs b/pac/atsamc20e/src/dsu/statusa.rs new file mode 100644 index 000000000000..c7b90a13e491 --- /dev/null +++ b/pac/atsamc20e/src/dsu/statusa.rs @@ -0,0 +1,301 @@ +#[doc = "Register `STATUSA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUSA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DONE` reader - Done"] +pub struct DONE_R(crate::FieldReader); +impl DONE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DONE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DONE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DONE` writer - Done"] +pub struct DONE_W<'a> { + w: &'a mut W, +} +impl<'a> DONE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `CRSTEXT` reader - CPU Reset Phase Extension"] +pub struct CRSTEXT_R(crate::FieldReader); +impl CRSTEXT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CRSTEXT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CRSTEXT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRSTEXT` writer - CPU Reset Phase Extension"] +pub struct CRSTEXT_W<'a> { + w: &'a mut W, +} +impl<'a> CRSTEXT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `BERR` reader - Bus Error"] +pub struct BERR_R(crate::FieldReader); +impl BERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BERR` writer - Bus Error"] +pub struct BERR_W<'a> { + w: &'a mut W, +} +impl<'a> BERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `FAIL` reader - Failure"] +pub struct FAIL_R(crate::FieldReader); +impl FAIL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAIL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAIL` writer - Failure"] +pub struct FAIL_W<'a> { + w: &'a mut W, +} +impl<'a> FAIL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PERR` reader - Protection Error"] +pub struct PERR_R(crate::FieldReader); +impl PERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERR` writer - Protection Error"] +pub struct PERR_W<'a> { + w: &'a mut W, +} +impl<'a> PERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +impl R { + #[doc = "Bit 0 - Done"] + #[inline(always)] + pub fn done(&self) -> DONE_R { + DONE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - CPU Reset Phase Extension"] + #[inline(always)] + pub fn crstext(&self) -> CRSTEXT_R { + CRSTEXT_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Bus Error"] + #[inline(always)] + pub fn berr(&self) -> BERR_R { + BERR_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Failure"] + #[inline(always)] + pub fn fail(&self) -> FAIL_R { + FAIL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Protection Error"] + #[inline(always)] + pub fn perr(&self) -> PERR_R { + PERR_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Done"] + #[inline(always)] + pub fn done(&mut self) -> DONE_W { + DONE_W { w: self } + } + #[doc = "Bit 1 - CPU Reset Phase Extension"] + #[inline(always)] + pub fn crstext(&mut self) -> CRSTEXT_W { + CRSTEXT_W { w: self } + } + #[doc = "Bit 2 - Bus Error"] + #[inline(always)] + pub fn berr(&mut self) -> BERR_W { + BERR_W { w: self } + } + #[doc = "Bit 3 - Failure"] + #[inline(always)] + pub fn fail(&mut self) -> FAIL_W { + FAIL_W { w: self } + } + #[doc = "Bit 4 - Protection Error"] + #[inline(always)] + pub fn perr(&mut self) -> PERR_W { + PERR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [statusa](index.html) module"] +pub struct STATUSA_SPEC; +impl crate::RegisterSpec for STATUSA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [statusa::R](R) reader structure"] +impl crate::Readable for STATUSA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [statusa::W](W) writer structure"] +impl crate::Writable for STATUSA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUSA to value 0"] +impl crate::Resettable for STATUSA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/dsu/statusb.rs b/pac/atsamc20e/src/dsu/statusb.rs new file mode 100644 index 000000000000..1e9374f8deae --- /dev/null +++ b/pac/atsamc20e/src/dsu/statusb.rs @@ -0,0 +1,133 @@ +#[doc = "Register `STATUSB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PROT` reader - Protected"] +pub struct PROT_R(crate::FieldReader); +impl PROT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PROT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PROT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGPRES` reader - Debugger Present"] +pub struct DBGPRES_R(crate::FieldReader); +impl DBGPRES_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGPRES_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGPRES_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DCCD0` reader - Debug Communication Channel 0 Dirty"] +pub struct DCCD0_R(crate::FieldReader); +impl DCCD0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DCCD0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DCCD0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DCCD1` reader - Debug Communication Channel 1 Dirty"] +pub struct DCCD1_R(crate::FieldReader); +impl DCCD1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DCCD1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DCCD1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HPE` reader - Hot-Plugging Enable"] +pub struct HPE_R(crate::FieldReader); +impl HPE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HPE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HPE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Protected"] + #[inline(always)] + pub fn prot(&self) -> PROT_R { + PROT_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Debugger Present"] + #[inline(always)] + pub fn dbgpres(&self) -> DBGPRES_R { + DBGPRES_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Debug Communication Channel 0 Dirty"] + #[inline(always)] + pub fn dccd0(&self) -> DCCD0_R { + DCCD0_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Debug Communication Channel 1 Dirty"] + #[inline(always)] + pub fn dccd1(&self) -> DCCD1_R { + DCCD1_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Hot-Plugging Enable"] + #[inline(always)] + pub fn hpe(&self) -> HPE_R { + HPE_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +#[doc = "Status B\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [statusb](index.html) module"] +pub struct STATUSB_SPEC; +impl crate::RegisterSpec for STATUSB_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [statusb::R](R) reader structure"] +impl crate::Readable for STATUSB_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUSB to value 0"] +impl crate::Resettable for STATUSB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/dsu/statusc.rs b/pac/atsamc20e/src/dsu/statusc.rs new file mode 100644 index 000000000000..14b3f7b1c7e3 --- /dev/null +++ b/pac/atsamc20e/src/dsu/statusc.rs @@ -0,0 +1,53 @@ +#[doc = "Register `STATUSC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `STATE` reader - State"] +pub struct STATE_R(crate::FieldReader); +impl STATE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + STATE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STATE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:2 - State"] + #[inline(always)] + pub fn state(&self) -> STATE_R { + STATE_R::new((self.bits & 0x07) as u8) + } +} +#[doc = "Status C\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [statusc](index.html) module"] +pub struct STATUSC_SPEC; +impl crate::RegisterSpec for STATUSC_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [statusc::R](R) reader structure"] +impl crate::Readable for STATUSC_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUSC to value 0"] +impl crate::Resettable for STATUSC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/eic.rs b/pac/atsamc20e/src/eic.rs new file mode 100644 index 000000000000..606231233f4b --- /dev/null +++ b/pac/atsamc20e/src/eic.rs @@ -0,0 +1,64 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrla: crate::Reg, + #[doc = "0x01 - NMI Control"] + pub nmictrl: crate::Reg, + #[doc = "0x02 - NMI Interrupt Flag"] + pub nmiflag: crate::Reg, + #[doc = "0x04 - Syncbusy register"] + pub syncbusy: crate::Reg, + #[doc = "0x08 - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x0c - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x10 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x14 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x18 - EIC Asynchronous edge Detection Enable"] + pub asynch: crate::Reg, + #[doc = "0x1c..0x24 - Configuration n"] + pub config: [crate::Reg; 2], +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control"] +pub mod ctrla; +#[doc = "NMICTRL register accessor: an alias for `Reg`"] +pub type NMICTRL = crate::Reg; +#[doc = "NMI Control"] +pub mod nmictrl; +#[doc = "NMIFLAG register accessor: an alias for `Reg`"] +pub type NMIFLAG = crate::Reg; +#[doc = "NMI Interrupt Flag"] +pub mod nmiflag; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Syncbusy register"] +pub mod syncbusy; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "ASYNCH register accessor: an alias for `Reg`"] +pub type ASYNCH = crate::Reg; +#[doc = "EIC Asynchronous edge Detection Enable"] +pub mod asynch; +#[doc = "CONFIG register accessor: an alias for `Reg`"] +pub type CONFIG = crate::Reg; +#[doc = "Configuration n"] +pub mod config; diff --git a/pac/atsamc20e/src/eic/asynch.rs b/pac/atsamc20e/src/eic/asynch.rs new file mode 100644 index 000000000000..78a9b5c5f054 --- /dev/null +++ b/pac/atsamc20e/src/eic/asynch.rs @@ -0,0 +1,152 @@ +#[doc = "Register `ASYNCH` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ASYNCH` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "EIC Asynchronous edge Detection Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u16)] +pub enum ASYNCH_A { + #[doc = "0: Edge detection is clock synchronously operated"] + SYNC = 0, + #[doc = "1: Edge detection is clock asynchronously operated"] + ASYNC = 1, +} +impl From for u16 { + #[inline(always)] + fn from(variant: ASYNCH_A) -> Self { + variant as _ + } +} +#[doc = "Field `ASYNCH` reader - EIC Asynchronous edge Detection Enable"] +pub struct ASYNCH_R(crate::FieldReader); +impl ASYNCH_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + ASYNCH_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(ASYNCH_A::SYNC), + 1 => Some(ASYNCH_A::ASYNC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `SYNC`"] + #[inline(always)] + pub fn is_sync(&self) -> bool { + **self == ASYNCH_A::SYNC + } + #[doc = "Checks if the value of the field is `ASYNC`"] + #[inline(always)] + pub fn is_async(&self) -> bool { + **self == ASYNCH_A::ASYNC + } +} +impl core::ops::Deref for ASYNCH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ASYNCH` writer - EIC Asynchronous edge Detection Enable"] +pub struct ASYNCH_W<'a> { + w: &'a mut W, +} +impl<'a> ASYNCH_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: ASYNCH_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Edge detection is clock synchronously operated"] + #[inline(always)] + pub fn sync(self) -> &'a mut W { + self.variant(ASYNCH_A::SYNC) + } + #[doc = "Edge detection is clock asynchronously operated"] + #[inline(always)] + pub fn async_(self) -> &'a mut W { + self.variant(ASYNCH_A::ASYNC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - EIC Asynchronous edge Detection Enable"] + #[inline(always)] + pub fn asynch(&self) -> ASYNCH_R { + ASYNCH_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - EIC Asynchronous edge Detection Enable"] + #[inline(always)] + pub fn asynch(&mut self) -> ASYNCH_W { + ASYNCH_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "EIC Asynchronous edge Detection Enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [asynch](index.html) module"] +pub struct ASYNCH_SPEC; +impl crate::RegisterSpec for ASYNCH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [asynch::R](R) reader structure"] +impl crate::Readable for ASYNCH_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [asynch::W](W) writer structure"] +impl crate::Writable for ASYNCH_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ASYNCH to value 0"] +impl crate::Resettable for ASYNCH_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/eic/config.rs b/pac/atsamc20e/src/eic/config.rs new file mode 100644 index 000000000000..ab2c30950417 --- /dev/null +++ b/pac/atsamc20e/src/eic/config.rs @@ -0,0 +1,1547 @@ +#[doc = "Register `CONFIG[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CONFIG[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Input Sense Configuration 0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE0_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE0_A) -> Self { + variant as _ + } +} +#[doc = "Field `SENSE0` reader - Input Sense Configuration 0"] +pub struct SENSE0_R(crate::FieldReader); +impl SENSE0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SENSE0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE0_A::NONE), + 1 => Some(SENSE0_A::RISE), + 2 => Some(SENSE0_A::FALL), + 3 => Some(SENSE0_A::BOTH), + 4 => Some(SENSE0_A::HIGH), + 5 => Some(SENSE0_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == SENSE0_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == SENSE0_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == SENSE0_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == SENSE0_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SENSE0_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SENSE0_A::LOW + } +} +impl core::ops::Deref for SENSE0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SENSE0` writer - Input Sense Configuration 0"] +pub struct SENSE0_W<'a> { + w: &'a mut W, +} +impl<'a> SENSE0_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SENSE0_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE0_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE0_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE0_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE0_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE0_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE0_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Field `FILTEN0` reader - Filter Enable 0"] +pub struct FILTEN0_R(crate::FieldReader); +impl FILTEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FILTEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTEN0` writer - Filter Enable 0"] +pub struct FILTEN0_W<'a> { + w: &'a mut W, +} +impl<'a> FILTEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Input Sense Configuration 1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE1_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE1_A) -> Self { + variant as _ + } +} +#[doc = "Field `SENSE1` reader - Input Sense Configuration 1"] +pub struct SENSE1_R(crate::FieldReader); +impl SENSE1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SENSE1_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE1_A::NONE), + 1 => Some(SENSE1_A::RISE), + 2 => Some(SENSE1_A::FALL), + 3 => Some(SENSE1_A::BOTH), + 4 => Some(SENSE1_A::HIGH), + 5 => Some(SENSE1_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == SENSE1_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == SENSE1_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == SENSE1_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == SENSE1_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SENSE1_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SENSE1_A::LOW + } +} +impl core::ops::Deref for SENSE1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SENSE1` writer - Input Sense Configuration 1"] +pub struct SENSE1_W<'a> { + w: &'a mut W, +} +impl<'a> SENSE1_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SENSE1_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE1_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE1_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE1_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE1_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE1_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE1_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 4)) | ((value as u32 & 0x07) << 4); + self.w + } +} +#[doc = "Field `FILTEN1` reader - Filter Enable 1"] +pub struct FILTEN1_R(crate::FieldReader); +impl FILTEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FILTEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTEN1` writer - Filter Enable 1"] +pub struct FILTEN1_W<'a> { + w: &'a mut W, +} +impl<'a> FILTEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Input Sense Configuration 2\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE2_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE2_A) -> Self { + variant as _ + } +} +#[doc = "Field `SENSE2` reader - Input Sense Configuration 2"] +pub struct SENSE2_R(crate::FieldReader); +impl SENSE2_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SENSE2_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE2_A::NONE), + 1 => Some(SENSE2_A::RISE), + 2 => Some(SENSE2_A::FALL), + 3 => Some(SENSE2_A::BOTH), + 4 => Some(SENSE2_A::HIGH), + 5 => Some(SENSE2_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == SENSE2_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == SENSE2_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == SENSE2_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == SENSE2_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SENSE2_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SENSE2_A::LOW + } +} +impl core::ops::Deref for SENSE2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SENSE2` writer - Input Sense Configuration 2"] +pub struct SENSE2_W<'a> { + w: &'a mut W, +} +impl<'a> SENSE2_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SENSE2_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE2_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE2_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE2_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE2_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE2_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE2_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +#[doc = "Field `FILTEN2` reader - Filter Enable 2"] +pub struct FILTEN2_R(crate::FieldReader); +impl FILTEN2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FILTEN2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTEN2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTEN2` writer - Filter Enable 2"] +pub struct FILTEN2_W<'a> { + w: &'a mut W, +} +impl<'a> FILTEN2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Input Sense Configuration 3\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE3_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE3_A) -> Self { + variant as _ + } +} +#[doc = "Field `SENSE3` reader - Input Sense Configuration 3"] +pub struct SENSE3_R(crate::FieldReader); +impl SENSE3_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SENSE3_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE3_A::NONE), + 1 => Some(SENSE3_A::RISE), + 2 => Some(SENSE3_A::FALL), + 3 => Some(SENSE3_A::BOTH), + 4 => Some(SENSE3_A::HIGH), + 5 => Some(SENSE3_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == SENSE3_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == SENSE3_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == SENSE3_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == SENSE3_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SENSE3_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SENSE3_A::LOW + } +} +impl core::ops::Deref for SENSE3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SENSE3` writer - Input Sense Configuration 3"] +pub struct SENSE3_W<'a> { + w: &'a mut W, +} +impl<'a> SENSE3_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SENSE3_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE3_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE3_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE3_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE3_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE3_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE3_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 12)) | ((value as u32 & 0x07) << 12); + self.w + } +} +#[doc = "Field `FILTEN3` reader - Filter Enable 3"] +pub struct FILTEN3_R(crate::FieldReader); +impl FILTEN3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FILTEN3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTEN3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTEN3` writer - Filter Enable 3"] +pub struct FILTEN3_W<'a> { + w: &'a mut W, +} +impl<'a> FILTEN3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Input Sense Configuration 4\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE4_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE4_A) -> Self { + variant as _ + } +} +#[doc = "Field `SENSE4` reader - Input Sense Configuration 4"] +pub struct SENSE4_R(crate::FieldReader); +impl SENSE4_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SENSE4_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE4_A::NONE), + 1 => Some(SENSE4_A::RISE), + 2 => Some(SENSE4_A::FALL), + 3 => Some(SENSE4_A::BOTH), + 4 => Some(SENSE4_A::HIGH), + 5 => Some(SENSE4_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == SENSE4_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == SENSE4_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == SENSE4_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == SENSE4_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SENSE4_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SENSE4_A::LOW + } +} +impl core::ops::Deref for SENSE4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SENSE4` writer - Input Sense Configuration 4"] +pub struct SENSE4_W<'a> { + w: &'a mut W, +} +impl<'a> SENSE4_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SENSE4_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE4_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE4_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE4_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE4_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE4_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE4_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 16)) | ((value as u32 & 0x07) << 16); + self.w + } +} +#[doc = "Field `FILTEN4` reader - Filter Enable 4"] +pub struct FILTEN4_R(crate::FieldReader); +impl FILTEN4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FILTEN4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTEN4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTEN4` writer - Filter Enable 4"] +pub struct FILTEN4_W<'a> { + w: &'a mut W, +} +impl<'a> FILTEN4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Input Sense Configuration 5\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE5_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE5_A) -> Self { + variant as _ + } +} +#[doc = "Field `SENSE5` reader - Input Sense Configuration 5"] +pub struct SENSE5_R(crate::FieldReader); +impl SENSE5_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SENSE5_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE5_A::NONE), + 1 => Some(SENSE5_A::RISE), + 2 => Some(SENSE5_A::FALL), + 3 => Some(SENSE5_A::BOTH), + 4 => Some(SENSE5_A::HIGH), + 5 => Some(SENSE5_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == SENSE5_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == SENSE5_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == SENSE5_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == SENSE5_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SENSE5_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SENSE5_A::LOW + } +} +impl core::ops::Deref for SENSE5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SENSE5` writer - Input Sense Configuration 5"] +pub struct SENSE5_W<'a> { + w: &'a mut W, +} +impl<'a> SENSE5_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SENSE5_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE5_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE5_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE5_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE5_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE5_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE5_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 20)) | ((value as u32 & 0x07) << 20); + self.w + } +} +#[doc = "Field `FILTEN5` reader - Filter Enable 5"] +pub struct FILTEN5_R(crate::FieldReader); +impl FILTEN5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FILTEN5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTEN5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTEN5` writer - Filter Enable 5"] +pub struct FILTEN5_W<'a> { + w: &'a mut W, +} +impl<'a> FILTEN5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Input Sense Configuration 6\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE6_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE6_A) -> Self { + variant as _ + } +} +#[doc = "Field `SENSE6` reader - Input Sense Configuration 6"] +pub struct SENSE6_R(crate::FieldReader); +impl SENSE6_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SENSE6_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE6_A::NONE), + 1 => Some(SENSE6_A::RISE), + 2 => Some(SENSE6_A::FALL), + 3 => Some(SENSE6_A::BOTH), + 4 => Some(SENSE6_A::HIGH), + 5 => Some(SENSE6_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == SENSE6_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == SENSE6_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == SENSE6_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == SENSE6_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SENSE6_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SENSE6_A::LOW + } +} +impl core::ops::Deref for SENSE6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SENSE6` writer - Input Sense Configuration 6"] +pub struct SENSE6_W<'a> { + w: &'a mut W, +} +impl<'a> SENSE6_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SENSE6_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE6_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE6_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE6_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE6_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE6_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE6_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 24)) | ((value as u32 & 0x07) << 24); + self.w + } +} +#[doc = "Field `FILTEN6` reader - Filter Enable 6"] +pub struct FILTEN6_R(crate::FieldReader); +impl FILTEN6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FILTEN6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTEN6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTEN6` writer - Filter Enable 6"] +pub struct FILTEN6_W<'a> { + w: &'a mut W, +} +impl<'a> FILTEN6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +#[doc = "Input Sense Configuration 7\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE7_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE7_A) -> Self { + variant as _ + } +} +#[doc = "Field `SENSE7` reader - Input Sense Configuration 7"] +pub struct SENSE7_R(crate::FieldReader); +impl SENSE7_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SENSE7_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE7_A::NONE), + 1 => Some(SENSE7_A::RISE), + 2 => Some(SENSE7_A::FALL), + 3 => Some(SENSE7_A::BOTH), + 4 => Some(SENSE7_A::HIGH), + 5 => Some(SENSE7_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == SENSE7_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == SENSE7_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == SENSE7_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == SENSE7_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SENSE7_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SENSE7_A::LOW + } +} +impl core::ops::Deref for SENSE7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SENSE7` writer - Input Sense Configuration 7"] +pub struct SENSE7_W<'a> { + w: &'a mut W, +} +impl<'a> SENSE7_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SENSE7_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE7_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE7_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE7_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE7_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE7_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE7_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 28)) | ((value as u32 & 0x07) << 28); + self.w + } +} +#[doc = "Field `FILTEN7` reader - Filter Enable 7"] +pub struct FILTEN7_R(crate::FieldReader); +impl FILTEN7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FILTEN7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTEN7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTEN7` writer - Filter Enable 7"] +pub struct FILTEN7_W<'a> { + w: &'a mut W, +} +impl<'a> FILTEN7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Input Sense Configuration 0"] + #[inline(always)] + pub fn sense0(&self) -> SENSE0_R { + SENSE0_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 3 - Filter Enable 0"] + #[inline(always)] + pub fn filten0(&self) -> FILTEN0_R { + FILTEN0_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bits 4:6 - Input Sense Configuration 1"] + #[inline(always)] + pub fn sense1(&self) -> SENSE1_R { + SENSE1_R::new(((self.bits >> 4) & 0x07) as u8) + } + #[doc = "Bit 7 - Filter Enable 1"] + #[inline(always)] + pub fn filten1(&self) -> FILTEN1_R { + FILTEN1_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Input Sense Configuration 2"] + #[inline(always)] + pub fn sense2(&self) -> SENSE2_R { + SENSE2_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 11 - Filter Enable 2"] + #[inline(always)] + pub fn filten2(&self) -> FILTEN2_R { + FILTEN2_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bits 12:14 - Input Sense Configuration 3"] + #[inline(always)] + pub fn sense3(&self) -> SENSE3_R { + SENSE3_R::new(((self.bits >> 12) & 0x07) as u8) + } + #[doc = "Bit 15 - Filter Enable 3"] + #[inline(always)] + pub fn filten3(&self) -> FILTEN3_R { + FILTEN3_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:18 - Input Sense Configuration 4"] + #[inline(always)] + pub fn sense4(&self) -> SENSE4_R { + SENSE4_R::new(((self.bits >> 16) & 0x07) as u8) + } + #[doc = "Bit 19 - Filter Enable 4"] + #[inline(always)] + pub fn filten4(&self) -> FILTEN4_R { + FILTEN4_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bits 20:22 - Input Sense Configuration 5"] + #[inline(always)] + pub fn sense5(&self) -> SENSE5_R { + SENSE5_R::new(((self.bits >> 20) & 0x07) as u8) + } + #[doc = "Bit 23 - Filter Enable 5"] + #[inline(always)] + pub fn filten5(&self) -> FILTEN5_R { + FILTEN5_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bits 24:26 - Input Sense Configuration 6"] + #[inline(always)] + pub fn sense6(&self) -> SENSE6_R { + SENSE6_R::new(((self.bits >> 24) & 0x07) as u8) + } + #[doc = "Bit 27 - Filter Enable 6"] + #[inline(always)] + pub fn filten6(&self) -> FILTEN6_R { + FILTEN6_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bits 28:30 - Input Sense Configuration 7"] + #[inline(always)] + pub fn sense7(&self) -> SENSE7_R { + SENSE7_R::new(((self.bits >> 28) & 0x07) as u8) + } + #[doc = "Bit 31 - Filter Enable 7"] + #[inline(always)] + pub fn filten7(&self) -> FILTEN7_R { + FILTEN7_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Input Sense Configuration 0"] + #[inline(always)] + pub fn sense0(&mut self) -> SENSE0_W { + SENSE0_W { w: self } + } + #[doc = "Bit 3 - Filter Enable 0"] + #[inline(always)] + pub fn filten0(&mut self) -> FILTEN0_W { + FILTEN0_W { w: self } + } + #[doc = "Bits 4:6 - Input Sense Configuration 1"] + #[inline(always)] + pub fn sense1(&mut self) -> SENSE1_W { + SENSE1_W { w: self } + } + #[doc = "Bit 7 - Filter Enable 1"] + #[inline(always)] + pub fn filten1(&mut self) -> FILTEN1_W { + FILTEN1_W { w: self } + } + #[doc = "Bits 8:10 - Input Sense Configuration 2"] + #[inline(always)] + pub fn sense2(&mut self) -> SENSE2_W { + SENSE2_W { w: self } + } + #[doc = "Bit 11 - Filter Enable 2"] + #[inline(always)] + pub fn filten2(&mut self) -> FILTEN2_W { + FILTEN2_W { w: self } + } + #[doc = "Bits 12:14 - Input Sense Configuration 3"] + #[inline(always)] + pub fn sense3(&mut self) -> SENSE3_W { + SENSE3_W { w: self } + } + #[doc = "Bit 15 - Filter Enable 3"] + #[inline(always)] + pub fn filten3(&mut self) -> FILTEN3_W { + FILTEN3_W { w: self } + } + #[doc = "Bits 16:18 - Input Sense Configuration 4"] + #[inline(always)] + pub fn sense4(&mut self) -> SENSE4_W { + SENSE4_W { w: self } + } + #[doc = "Bit 19 - Filter Enable 4"] + #[inline(always)] + pub fn filten4(&mut self) -> FILTEN4_W { + FILTEN4_W { w: self } + } + #[doc = "Bits 20:22 - Input Sense Configuration 5"] + #[inline(always)] + pub fn sense5(&mut self) -> SENSE5_W { + SENSE5_W { w: self } + } + #[doc = "Bit 23 - Filter Enable 5"] + #[inline(always)] + pub fn filten5(&mut self) -> FILTEN5_W { + FILTEN5_W { w: self } + } + #[doc = "Bits 24:26 - Input Sense Configuration 6"] + #[inline(always)] + pub fn sense6(&mut self) -> SENSE6_W { + SENSE6_W { w: self } + } + #[doc = "Bit 27 - Filter Enable 6"] + #[inline(always)] + pub fn filten6(&mut self) -> FILTEN6_W { + FILTEN6_W { w: self } + } + #[doc = "Bits 28:30 - Input Sense Configuration 7"] + #[inline(always)] + pub fn sense7(&mut self) -> SENSE7_W { + SENSE7_W { w: self } + } + #[doc = "Bit 31 - Filter Enable 7"] + #[inline(always)] + pub fn filten7(&mut self) -> FILTEN7_W { + FILTEN7_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Configuration n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [config](index.html) module"] +pub struct CONFIG_SPEC; +impl crate::RegisterSpec for CONFIG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [config::R](R) reader structure"] +impl crate::Readable for CONFIG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [config::W](W) writer structure"] +impl crate::Writable for CONFIG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CONFIG[%s] +to value 0"] +impl crate::Resettable for CONFIG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/eic/ctrla.rs b/pac/atsamc20e/src/eic/ctrla.rs new file mode 100644 index 000000000000..25e701dd3db2 --- /dev/null +++ b/pac/atsamc20e/src/eic/ctrla.rs @@ -0,0 +1,254 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Clock Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CKSEL_A { + #[doc = "0: Clocked by GCLK"] + CLK_GCLK = 0, + #[doc = "1: Clocked by ULP32K"] + CLK_ULP32K = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CKSEL_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CKSEL` reader - Clock Selection"] +pub struct CKSEL_R(crate::FieldReader); +impl CKSEL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CKSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CKSEL_A { + match self.bits { + false => CKSEL_A::CLK_GCLK, + true => CKSEL_A::CLK_ULP32K, + } + } + #[doc = "Checks if the value of the field is `CLK_GCLK`"] + #[inline(always)] + pub fn is_clk_gclk(&self) -> bool { + **self == CKSEL_A::CLK_GCLK + } + #[doc = "Checks if the value of the field is `CLK_ULP32K`"] + #[inline(always)] + pub fn is_clk_ulp32k(&self) -> bool { + **self == CKSEL_A::CLK_ULP32K + } +} +impl core::ops::Deref for CKSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CKSEL` writer - Clock Selection"] +pub struct CKSEL_W<'a> { + w: &'a mut W, +} +impl<'a> CKSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CKSEL_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Clocked by GCLK"] + #[inline(always)] + pub fn clk_gclk(self) -> &'a mut W { + self.variant(CKSEL_A::CLK_GCLK) + } + #[doc = "Clocked by ULP32K"] + #[inline(always)] + pub fn clk_ulp32k(self) -> &'a mut W { + self.variant(CKSEL_A::CLK_ULP32K) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - Clock Selection"] + #[inline(always)] + pub fn cksel(&self) -> CKSEL_R { + CKSEL_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 4 - Clock Selection"] + #[inline(always)] + pub fn cksel(&mut self) -> CKSEL_W { + CKSEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/eic/evctrl.rs b/pac/atsamc20e/src/eic/evctrl.rs new file mode 100644 index 000000000000..25adccf3558e --- /dev/null +++ b/pac/atsamc20e/src/eic/evctrl.rs @@ -0,0 +1,103 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EXTINTEO` reader - External Interrupt Event Output Enable"] +pub struct EXTINTEO_R(crate::FieldReader); +impl EXTINTEO_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + EXTINTEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINTEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINTEO` writer - External Interrupt Event Output Enable"] +pub struct EXTINTEO_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINTEO_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - External Interrupt Event Output Enable"] + #[inline(always)] + pub fn extinteo(&self) -> EXTINTEO_R { + EXTINTEO_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - External Interrupt Event Output Enable"] + #[inline(always)] + pub fn extinteo(&mut self) -> EXTINTEO_W { + EXTINTEO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/eic/intenclr.rs b/pac/atsamc20e/src/eic/intenclr.rs new file mode 100644 index 000000000000..198c3aac9eb1 --- /dev/null +++ b/pac/atsamc20e/src/eic/intenclr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EXTINT` reader - External Interrupt Disable"] +pub struct EXTINT_R(crate::FieldReader); +impl EXTINT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + EXTINT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT` writer - External Interrupt Disable"] +pub struct EXTINT_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - External Interrupt Disable"] + #[inline(always)] + pub fn extint(&self) -> EXTINT_R { + EXTINT_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - External Interrupt Disable"] + #[inline(always)] + pub fn extint(&mut self) -> EXTINT_W { + EXTINT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/eic/intenset.rs b/pac/atsamc20e/src/eic/intenset.rs new file mode 100644 index 000000000000..e2ff6729d71f --- /dev/null +++ b/pac/atsamc20e/src/eic/intenset.rs @@ -0,0 +1,103 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EXTINT` reader - External Interrupt Enable"] +pub struct EXTINT_R(crate::FieldReader); +impl EXTINT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + EXTINT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT` writer - External Interrupt Enable"] +pub struct EXTINT_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - External Interrupt Enable"] + #[inline(always)] + pub fn extint(&self) -> EXTINT_R { + EXTINT_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - External Interrupt Enable"] + #[inline(always)] + pub fn extint(&mut self) -> EXTINT_W { + EXTINT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/eic/intflag.rs b/pac/atsamc20e/src/eic/intflag.rs new file mode 100644 index 000000000000..df2f15490feb --- /dev/null +++ b/pac/atsamc20e/src/eic/intflag.rs @@ -0,0 +1,103 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EXTINT` reader - External Interrupt Flag"] +pub struct EXTINT_R(crate::FieldReader); +impl EXTINT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + EXTINT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT` writer - External Interrupt Flag"] +pub struct EXTINT_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - External Interrupt Flag"] + #[inline(always)] + pub fn extint(&self) -> EXTINT_R { + EXTINT_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - External Interrupt Flag"] + #[inline(always)] + pub fn extint(&mut self) -> EXTINT_W { + EXTINT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/eic/nmictrl.rs b/pac/atsamc20e/src/eic/nmictrl.rs new file mode 100644 index 000000000000..c9b276ea2a29 --- /dev/null +++ b/pac/atsamc20e/src/eic/nmictrl.rs @@ -0,0 +1,345 @@ +#[doc = "Register `NMICTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `NMICTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "NMI Input Sense Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum NMISENSE_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising-edge detection"] + RISE = 1, + #[doc = "2: Falling-edge detection"] + FALL = 2, + #[doc = "3: Both-edges detection"] + BOTH = 3, + #[doc = "4: High-level detection"] + HIGH = 4, + #[doc = "5: Low-level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: NMISENSE_A) -> Self { + variant as _ + } +} +#[doc = "Field `NMISENSE` reader - NMI Input Sense Configuration"] +pub struct NMISENSE_R(crate::FieldReader); +impl NMISENSE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + NMISENSE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(NMISENSE_A::NONE), + 1 => Some(NMISENSE_A::RISE), + 2 => Some(NMISENSE_A::FALL), + 3 => Some(NMISENSE_A::BOTH), + 4 => Some(NMISENSE_A::HIGH), + 5 => Some(NMISENSE_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == NMISENSE_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == NMISENSE_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == NMISENSE_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == NMISENSE_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == NMISENSE_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == NMISENSE_A::LOW + } +} +impl core::ops::Deref for NMISENSE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NMISENSE` writer - NMI Input Sense Configuration"] +pub struct NMISENSE_W<'a> { + w: &'a mut W, +} +impl<'a> NMISENSE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: NMISENSE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(NMISENSE_A::NONE) + } + #[doc = "Rising-edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(NMISENSE_A::RISE) + } + #[doc = "Falling-edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(NMISENSE_A::FALL) + } + #[doc = "Both-edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(NMISENSE_A::BOTH) + } + #[doc = "High-level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(NMISENSE_A::HIGH) + } + #[doc = "Low-level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(NMISENSE_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +#[doc = "Field `NMIFILTEN` reader - NMI Filter Enable"] +pub struct NMIFILTEN_R(crate::FieldReader); +impl NMIFILTEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NMIFILTEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NMIFILTEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NMIFILTEN` writer - NMI Filter Enable"] +pub struct NMIFILTEN_W<'a> { + w: &'a mut W, +} +impl<'a> NMIFILTEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "NMI Asynchronous edge Detection Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum NMIASYNCH_A { + #[doc = "0: Edge detection is clock synchronously operated"] + SYNC = 0, + #[doc = "1: Edge detection is clock asynchronously operated"] + ASYNC = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NMIASYNCH_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NMIASYNCH` reader - NMI Asynchronous edge Detection Enable"] +pub struct NMIASYNCH_R(crate::FieldReader); +impl NMIASYNCH_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NMIASYNCH_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> NMIASYNCH_A { + match self.bits { + false => NMIASYNCH_A::SYNC, + true => NMIASYNCH_A::ASYNC, + } + } + #[doc = "Checks if the value of the field is `SYNC`"] + #[inline(always)] + pub fn is_sync(&self) -> bool { + **self == NMIASYNCH_A::SYNC + } + #[doc = "Checks if the value of the field is `ASYNC`"] + #[inline(always)] + pub fn is_async(&self) -> bool { + **self == NMIASYNCH_A::ASYNC + } +} +impl core::ops::Deref for NMIASYNCH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NMIASYNCH` writer - NMI Asynchronous edge Detection Enable"] +pub struct NMIASYNCH_W<'a> { + w: &'a mut W, +} +impl<'a> NMIASYNCH_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: NMIASYNCH_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Edge detection is clock synchronously operated"] + #[inline(always)] + pub fn sync(self) -> &'a mut W { + self.variant(NMIASYNCH_A::SYNC) + } + #[doc = "Edge detection is clock asynchronously operated"] + #[inline(always)] + pub fn async_(self) -> &'a mut W { + self.variant(NMIASYNCH_A::ASYNC) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - NMI Input Sense Configuration"] + #[inline(always)] + pub fn nmisense(&self) -> NMISENSE_R { + NMISENSE_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 3 - NMI Filter Enable"] + #[inline(always)] + pub fn nmifilten(&self) -> NMIFILTEN_R { + NMIFILTEN_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - NMI Asynchronous edge Detection Enable"] + #[inline(always)] + pub fn nmiasynch(&self) -> NMIASYNCH_R { + NMIASYNCH_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - NMI Input Sense Configuration"] + #[inline(always)] + pub fn nmisense(&mut self) -> NMISENSE_W { + NMISENSE_W { w: self } + } + #[doc = "Bit 3 - NMI Filter Enable"] + #[inline(always)] + pub fn nmifilten(&mut self) -> NMIFILTEN_W { + NMIFILTEN_W { w: self } + } + #[doc = "Bit 4 - NMI Asynchronous edge Detection Enable"] + #[inline(always)] + pub fn nmiasynch(&mut self) -> NMIASYNCH_W { + NMIASYNCH_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "NMI Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [nmictrl](index.html) module"] +pub struct NMICTRL_SPEC; +impl crate::RegisterSpec for NMICTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [nmictrl::R](R) reader structure"] +impl crate::Readable for NMICTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [nmictrl::W](W) writer structure"] +impl crate::Writable for NMICTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets NMICTRL to value 0"] +impl crate::Resettable for NMICTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/eic/nmiflag.rs b/pac/atsamc20e/src/eic/nmiflag.rs new file mode 100644 index 000000000000..97934b501c12 --- /dev/null +++ b/pac/atsamc20e/src/eic/nmiflag.rs @@ -0,0 +1,113 @@ +#[doc = "Register `NMIFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `NMIFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `NMI` reader - NMI Interrupt Flag"] +pub struct NMI_R(crate::FieldReader); +impl NMI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NMI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NMI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NMI` writer - NMI Interrupt Flag"] +pub struct NMI_W<'a> { + w: &'a mut W, +} +impl<'a> NMI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - NMI Interrupt Flag"] + #[inline(always)] + pub fn nmi(&self) -> NMI_R { + NMI_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - NMI Interrupt Flag"] + #[inline(always)] + pub fn nmi(&mut self) -> NMI_W { + NMI_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "NMI Interrupt Flag\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [nmiflag](index.html) module"] +pub struct NMIFLAG_SPEC; +impl crate::RegisterSpec for NMIFLAG_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [nmiflag::R](R) reader structure"] +impl crate::Readable for NMIFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [nmiflag::W](W) writer structure"] +impl crate::Writable for NMIFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets NMIFLAG to value 0"] +impl crate::Resettable for NMIFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/eic/syncbusy.rs b/pac/atsamc20e/src/eic/syncbusy.rs new file mode 100644 index 000000000000..84d125d0acf1 --- /dev/null +++ b/pac/atsamc20e/src/eic/syncbusy.rs @@ -0,0 +1,73 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software reset synchronisation"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - Enable synchronisation"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software reset synchronisation"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable synchronisation"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +#[doc = "Syncbusy register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/evsys.rs b/pac/atsamc20e/src/evsys.rs new file mode 100644 index 000000000000..20d569fd3b90 --- /dev/null +++ b/pac/atsamc20e/src/evsys.rs @@ -0,0 +1,54 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrla: crate::Reg, + _reserved1: [u8; 0x0b], + #[doc = "0x0c - Channel Status"] + pub chstatus: crate::Reg, + #[doc = "0x10 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x14 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x18 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x1c - Software Event"] + pub swevt: crate::Reg, + #[doc = "0x20..0x38 - Channel n"] + pub channel: [crate::Reg; 6], + _reserved7: [u8; 0x48], + #[doc = "0x80..0x13c - User Multiplexer n"] + pub user: [crate::Reg; 47], +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control"] +pub mod ctrla; +#[doc = "CHSTATUS register accessor: an alias for `Reg`"] +pub type CHSTATUS = crate::Reg; +#[doc = "Channel Status"] +pub mod chstatus; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "SWEVT register accessor: an alias for `Reg`"] +pub type SWEVT = crate::Reg; +#[doc = "Software Event"] +pub mod swevt; +#[doc = "CHANNEL register accessor: an alias for `Reg`"] +pub type CHANNEL = crate::Reg; +#[doc = "Channel n"] +pub mod channel; +#[doc = "USER register accessor: an alias for `Reg`"] +pub type USER = crate::Reg; +#[doc = "User Multiplexer n"] +pub mod user; diff --git a/pac/atsamc20e/src/evsys/channel.rs b/pac/atsamc20e/src/evsys/channel.rs new file mode 100644 index 000000000000..20e3857da922 --- /dev/null +++ b/pac/atsamc20e/src/evsys/channel.rs @@ -0,0 +1,409 @@ +#[doc = "Register `CHANNEL[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHANNEL[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVGEN` reader - Event Generator Selection"] +pub struct EVGEN_R(crate::FieldReader); +impl EVGEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVGEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVGEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVGEN` writer - Event Generator Selection"] +pub struct EVGEN_W<'a> { + w: &'a mut W, +} +impl<'a> EVGEN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x7f) | (value as u32 & 0x7f); + self.w + } +} +#[doc = "Path Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PATH_A { + #[doc = "0: Synchronous path"] + SYNCHRONOUS = 0, + #[doc = "1: Resynchronized path"] + RESYNCHRONIZED = 1, + #[doc = "2: Asynchronous path"] + ASYNCHRONOUS = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PATH_A) -> Self { + variant as _ + } +} +#[doc = "Field `PATH` reader - Path Selection"] +pub struct PATH_R(crate::FieldReader); +impl PATH_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PATH_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PATH_A::SYNCHRONOUS), + 1 => Some(PATH_A::RESYNCHRONIZED), + 2 => Some(PATH_A::ASYNCHRONOUS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `SYNCHRONOUS`"] + #[inline(always)] + pub fn is_synchronous(&self) -> bool { + **self == PATH_A::SYNCHRONOUS + } + #[doc = "Checks if the value of the field is `RESYNCHRONIZED`"] + #[inline(always)] + pub fn is_resynchronized(&self) -> bool { + **self == PATH_A::RESYNCHRONIZED + } + #[doc = "Checks if the value of the field is `ASYNCHRONOUS`"] + #[inline(always)] + pub fn is_asynchronous(&self) -> bool { + **self == PATH_A::ASYNCHRONOUS + } +} +impl core::ops::Deref for PATH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PATH` writer - Path Selection"] +pub struct PATH_W<'a> { + w: &'a mut W, +} +impl<'a> PATH_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PATH_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Synchronous path"] + #[inline(always)] + pub fn synchronous(self) -> &'a mut W { + self.variant(PATH_A::SYNCHRONOUS) + } + #[doc = "Resynchronized path"] + #[inline(always)] + pub fn resynchronized(self) -> &'a mut W { + self.variant(PATH_A::RESYNCHRONIZED) + } + #[doc = "Asynchronous path"] + #[inline(always)] + pub fn asynchronous(self) -> &'a mut W { + self.variant(PATH_A::ASYNCHRONOUS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 8)) | ((value as u32 & 0x03) << 8); + self.w + } +} +#[doc = "Edge Detection Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EDGSEL_A { + #[doc = "0: No event output when using the resynchronized or synchronous path"] + NO_EVT_OUTPUT = 0, + #[doc = "1: Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path"] + RISING_EDGE = 1, + #[doc = "2: Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path"] + FALLING_EDGE = 2, + #[doc = "3: Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path"] + BOTH_EDGES = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EDGSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `EDGSEL` reader - Edge Detection Selection"] +pub struct EDGSEL_R(crate::FieldReader); +impl EDGSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EDGSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EDGSEL_A { + match self.bits { + 0 => EDGSEL_A::NO_EVT_OUTPUT, + 1 => EDGSEL_A::RISING_EDGE, + 2 => EDGSEL_A::FALLING_EDGE, + 3 => EDGSEL_A::BOTH_EDGES, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NO_EVT_OUTPUT`"] + #[inline(always)] + pub fn is_no_evt_output(&self) -> bool { + **self == EDGSEL_A::NO_EVT_OUTPUT + } + #[doc = "Checks if the value of the field is `RISING_EDGE`"] + #[inline(always)] + pub fn is_rising_edge(&self) -> bool { + **self == EDGSEL_A::RISING_EDGE + } + #[doc = "Checks if the value of the field is `FALLING_EDGE`"] + #[inline(always)] + pub fn is_falling_edge(&self) -> bool { + **self == EDGSEL_A::FALLING_EDGE + } + #[doc = "Checks if the value of the field is `BOTH_EDGES`"] + #[inline(always)] + pub fn is_both_edges(&self) -> bool { + **self == EDGSEL_A::BOTH_EDGES + } +} +impl core::ops::Deref for EDGSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EDGSEL` writer - Edge Detection Selection"] +pub struct EDGSEL_W<'a> { + w: &'a mut W, +} +impl<'a> EDGSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EDGSEL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "No event output when using the resynchronized or synchronous path"] + #[inline(always)] + pub fn no_evt_output(self) -> &'a mut W { + self.variant(EDGSEL_A::NO_EVT_OUTPUT) + } + #[doc = "Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path"] + #[inline(always)] + pub fn rising_edge(self) -> &'a mut W { + self.variant(EDGSEL_A::RISING_EDGE) + } + #[doc = "Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path"] + #[inline(always)] + pub fn falling_edge(self) -> &'a mut W { + self.variant(EDGSEL_A::FALLING_EDGE) + } + #[doc = "Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path"] + #[inline(always)] + pub fn both_edges(self) -> &'a mut W { + self.variant(EDGSEL_A::BOTH_EDGES) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 10)) | ((value as u32 & 0x03) << 10); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - Generic Clock On Demand"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - Generic Clock On Demand"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bits 0:6 - Event Generator Selection"] + #[inline(always)] + pub fn evgen(&self) -> EVGEN_R { + EVGEN_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bits 8:9 - Path Selection"] + #[inline(always)] + pub fn path(&self) -> PATH_R { + PATH_R::new(((self.bits >> 8) & 0x03) as u8) + } + #[doc = "Bits 10:11 - Edge Detection Selection"] + #[inline(always)] + pub fn edgsel(&self) -> EDGSEL_R { + EDGSEL_R::new(((self.bits >> 10) & 0x03) as u8) + } + #[doc = "Bit 14 - Run in standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Generic Clock On Demand"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:6 - Event Generator Selection"] + #[inline(always)] + pub fn evgen(&mut self) -> EVGEN_W { + EVGEN_W { w: self } + } + #[doc = "Bits 8:9 - Path Selection"] + #[inline(always)] + pub fn path(&mut self) -> PATH_W { + PATH_W { w: self } + } + #[doc = "Bits 10:11 - Edge Detection Selection"] + #[inline(always)] + pub fn edgsel(&mut self) -> EDGSEL_W { + EDGSEL_W { w: self } + } + #[doc = "Bit 14 - Run in standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 15 - Generic Clock On Demand"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [channel](index.html) module"] +pub struct CHANNEL_SPEC; +impl crate::RegisterSpec for CHANNEL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [channel::R](R) reader structure"] +impl crate::Readable for CHANNEL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [channel::W](W) writer structure"] +impl crate::Writable for CHANNEL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHANNEL[%s] +to value 0x8000"] +impl crate::Resettable for CHANNEL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x8000 + } +} diff --git a/pac/atsamc20e/src/evsys/chstatus.rs b/pac/atsamc20e/src/evsys/chstatus.rs new file mode 100644 index 000000000000..43004730356d --- /dev/null +++ b/pac/atsamc20e/src/evsys/chstatus.rs @@ -0,0 +1,273 @@ +#[doc = "Register `CHSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `USRRDY0` reader - Channel 0 User Ready"] +pub struct USRRDY0_R(crate::FieldReader); +impl USRRDY0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY1` reader - Channel 1 User Ready"] +pub struct USRRDY1_R(crate::FieldReader); +impl USRRDY1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY2` reader - Channel 2 User Ready"] +pub struct USRRDY2_R(crate::FieldReader); +impl USRRDY2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY3` reader - Channel 3 User Ready"] +pub struct USRRDY3_R(crate::FieldReader); +impl USRRDY3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY4` reader - Channel 4 User Ready"] +pub struct USRRDY4_R(crate::FieldReader); +impl USRRDY4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY5` reader - Channel 5 User Ready"] +pub struct USRRDY5_R(crate::FieldReader); +impl USRRDY5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY0` reader - Channel 0 Busy"] +pub struct CHBUSY0_R(crate::FieldReader); +impl CHBUSY0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY1` reader - Channel 1 Busy"] +pub struct CHBUSY1_R(crate::FieldReader); +impl CHBUSY1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY2` reader - Channel 2 Busy"] +pub struct CHBUSY2_R(crate::FieldReader); +impl CHBUSY2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY3` reader - Channel 3 Busy"] +pub struct CHBUSY3_R(crate::FieldReader); +impl CHBUSY3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY4` reader - Channel 4 Busy"] +pub struct CHBUSY4_R(crate::FieldReader); +impl CHBUSY4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY5` reader - Channel 5 Busy"] +pub struct CHBUSY5_R(crate::FieldReader); +impl CHBUSY5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Channel 0 User Ready"] + #[inline(always)] + pub fn usrrdy0(&self) -> USRRDY0_R { + USRRDY0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel 1 User Ready"] + #[inline(always)] + pub fn usrrdy1(&self) -> USRRDY1_R { + USRRDY1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel 2 User Ready"] + #[inline(always)] + pub fn usrrdy2(&self) -> USRRDY2_R { + USRRDY2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Channel 3 User Ready"] + #[inline(always)] + pub fn usrrdy3(&self) -> USRRDY3_R { + USRRDY3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Channel 4 User Ready"] + #[inline(always)] + pub fn usrrdy4(&self) -> USRRDY4_R { + USRRDY4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Channel 5 User Ready"] + #[inline(always)] + pub fn usrrdy5(&self) -> USRRDY5_R { + USRRDY5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 16 - Channel 0 Busy"] + #[inline(always)] + pub fn chbusy0(&self) -> CHBUSY0_R { + CHBUSY0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Channel 1 Busy"] + #[inline(always)] + pub fn chbusy1(&self) -> CHBUSY1_R { + CHBUSY1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Channel 2 Busy"] + #[inline(always)] + pub fn chbusy2(&self) -> CHBUSY2_R { + CHBUSY2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Channel 3 Busy"] + #[inline(always)] + pub fn chbusy3(&self) -> CHBUSY3_R { + CHBUSY3_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Channel 4 Busy"] + #[inline(always)] + pub fn chbusy4(&self) -> CHBUSY4_R { + CHBUSY4_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Channel 5 Busy"] + #[inline(always)] + pub fn chbusy5(&self) -> CHBUSY5_R { + CHBUSY5_R::new(((self.bits >> 21) & 0x01) != 0) + } +} +#[doc = "Channel Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chstatus](index.html) module"] +pub struct CHSTATUS_SPEC; +impl crate::RegisterSpec for CHSTATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [chstatus::R](R) reader structure"] +impl crate::Readable for CHSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CHSTATUS to value 0"] +impl crate::Resettable for CHSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/evsys/ctrla.rs b/pac/atsamc20e/src/evsys/ctrla.rs new file mode 100644 index 000000000000..1c24704395ad --- /dev/null +++ b/pac/atsamc20e/src/evsys/ctrla.rs @@ -0,0 +1,113 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/evsys/intenclr.rs b/pac/atsamc20e/src/evsys/intenclr.rs new file mode 100644 index 000000000000..60271a5e2e70 --- /dev/null +++ b/pac/atsamc20e/src/evsys/intenclr.rs @@ -0,0 +1,630 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVR0` reader - Channel 0 Overrun Interrupt Enable"] +pub struct OVR0_R(crate::FieldReader); +impl OVR0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR0` writer - Channel 0 Overrun Interrupt Enable"] +pub struct OVR0_W<'a> { + w: &'a mut W, +} +impl<'a> OVR0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `OVR1` reader - Channel 1 Overrun Interrupt Enable"] +pub struct OVR1_R(crate::FieldReader); +impl OVR1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR1` writer - Channel 1 Overrun Interrupt Enable"] +pub struct OVR1_W<'a> { + w: &'a mut W, +} +impl<'a> OVR1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `OVR2` reader - Channel 2 Overrun Interrupt Enable"] +pub struct OVR2_R(crate::FieldReader); +impl OVR2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR2` writer - Channel 2 Overrun Interrupt Enable"] +pub struct OVR2_W<'a> { + w: &'a mut W, +} +impl<'a> OVR2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `OVR3` reader - Channel 3 Overrun Interrupt Enable"] +pub struct OVR3_R(crate::FieldReader); +impl OVR3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR3` writer - Channel 3 Overrun Interrupt Enable"] +pub struct OVR3_W<'a> { + w: &'a mut W, +} +impl<'a> OVR3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `OVR4` reader - Channel 4 Overrun Interrupt Enable"] +pub struct OVR4_R(crate::FieldReader); +impl OVR4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR4` writer - Channel 4 Overrun Interrupt Enable"] +pub struct OVR4_W<'a> { + w: &'a mut W, +} +impl<'a> OVR4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `OVR5` reader - Channel 5 Overrun Interrupt Enable"] +pub struct OVR5_R(crate::FieldReader); +impl OVR5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR5` writer - Channel 5 Overrun Interrupt Enable"] +pub struct OVR5_W<'a> { + w: &'a mut W, +} +impl<'a> OVR5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `EVD0` reader - Channel 0 Event Detection Interrupt Enable"] +pub struct EVD0_R(crate::FieldReader); +impl EVD0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD0` writer - Channel 0 Event Detection Interrupt Enable"] +pub struct EVD0_W<'a> { + w: &'a mut W, +} +impl<'a> EVD0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `EVD1` reader - Channel 1 Event Detection Interrupt Enable"] +pub struct EVD1_R(crate::FieldReader); +impl EVD1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD1` writer - Channel 1 Event Detection Interrupt Enable"] +pub struct EVD1_W<'a> { + w: &'a mut W, +} +impl<'a> EVD1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `EVD2` reader - Channel 2 Event Detection Interrupt Enable"] +pub struct EVD2_R(crate::FieldReader); +impl EVD2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD2` writer - Channel 2 Event Detection Interrupt Enable"] +pub struct EVD2_W<'a> { + w: &'a mut W, +} +impl<'a> EVD2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `EVD3` reader - Channel 3 Event Detection Interrupt Enable"] +pub struct EVD3_R(crate::FieldReader); +impl EVD3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD3` writer - Channel 3 Event Detection Interrupt Enable"] +pub struct EVD3_W<'a> { + w: &'a mut W, +} +impl<'a> EVD3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `EVD4` reader - Channel 4 Event Detection Interrupt Enable"] +pub struct EVD4_R(crate::FieldReader); +impl EVD4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD4` writer - Channel 4 Event Detection Interrupt Enable"] +pub struct EVD4_W<'a> { + w: &'a mut W, +} +impl<'a> EVD4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `EVD5` reader - Channel 5 Event Detection Interrupt Enable"] +pub struct EVD5_R(crate::FieldReader); +impl EVD5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD5` writer - Channel 5 Event Detection Interrupt Enable"] +pub struct EVD5_W<'a> { + w: &'a mut W, +} +impl<'a> EVD5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +impl R { + #[doc = "Bit 0 - Channel 0 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr0(&self) -> OVR0_R { + OVR0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel 1 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr1(&self) -> OVR1_R { + OVR1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel 2 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr2(&self) -> OVR2_R { + OVR2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Channel 3 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr3(&self) -> OVR3_R { + OVR3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Channel 4 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr4(&self) -> OVR4_R { + OVR4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Channel 5 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr5(&self) -> OVR5_R { + OVR5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 16 - Channel 0 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd0(&self) -> EVD0_R { + EVD0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Channel 1 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd1(&self) -> EVD1_R { + EVD1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Channel 2 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd2(&self) -> EVD2_R { + EVD2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Channel 3 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd3(&self) -> EVD3_R { + EVD3_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Channel 4 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd4(&self) -> EVD4_R { + EVD4_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Channel 5 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd5(&self) -> EVD5_R { + EVD5_R::new(((self.bits >> 21) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel 0 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr0(&mut self) -> OVR0_W { + OVR0_W { w: self } + } + #[doc = "Bit 1 - Channel 1 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr1(&mut self) -> OVR1_W { + OVR1_W { w: self } + } + #[doc = "Bit 2 - Channel 2 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr2(&mut self) -> OVR2_W { + OVR2_W { w: self } + } + #[doc = "Bit 3 - Channel 3 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr3(&mut self) -> OVR3_W { + OVR3_W { w: self } + } + #[doc = "Bit 4 - Channel 4 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr4(&mut self) -> OVR4_W { + OVR4_W { w: self } + } + #[doc = "Bit 5 - Channel 5 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr5(&mut self) -> OVR5_W { + OVR5_W { w: self } + } + #[doc = "Bit 16 - Channel 0 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd0(&mut self) -> EVD0_W { + EVD0_W { w: self } + } + #[doc = "Bit 17 - Channel 1 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd1(&mut self) -> EVD1_W { + EVD1_W { w: self } + } + #[doc = "Bit 18 - Channel 2 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd2(&mut self) -> EVD2_W { + EVD2_W { w: self } + } + #[doc = "Bit 19 - Channel 3 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd3(&mut self) -> EVD3_W { + EVD3_W { w: self } + } + #[doc = "Bit 20 - Channel 4 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd4(&mut self) -> EVD4_W { + EVD4_W { w: self } + } + #[doc = "Bit 21 - Channel 5 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd5(&mut self) -> EVD5_W { + EVD5_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/evsys/intenset.rs b/pac/atsamc20e/src/evsys/intenset.rs new file mode 100644 index 000000000000..974030ec7350 --- /dev/null +++ b/pac/atsamc20e/src/evsys/intenset.rs @@ -0,0 +1,630 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVR0` reader - Channel 0 Overrun Interrupt Enable"] +pub struct OVR0_R(crate::FieldReader); +impl OVR0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR0` writer - Channel 0 Overrun Interrupt Enable"] +pub struct OVR0_W<'a> { + w: &'a mut W, +} +impl<'a> OVR0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `OVR1` reader - Channel 1 Overrun Interrupt Enable"] +pub struct OVR1_R(crate::FieldReader); +impl OVR1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR1` writer - Channel 1 Overrun Interrupt Enable"] +pub struct OVR1_W<'a> { + w: &'a mut W, +} +impl<'a> OVR1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `OVR2` reader - Channel 2 Overrun Interrupt Enable"] +pub struct OVR2_R(crate::FieldReader); +impl OVR2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR2` writer - Channel 2 Overrun Interrupt Enable"] +pub struct OVR2_W<'a> { + w: &'a mut W, +} +impl<'a> OVR2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `OVR3` reader - Channel 3 Overrun Interrupt Enable"] +pub struct OVR3_R(crate::FieldReader); +impl OVR3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR3` writer - Channel 3 Overrun Interrupt Enable"] +pub struct OVR3_W<'a> { + w: &'a mut W, +} +impl<'a> OVR3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `OVR4` reader - Channel 4 Overrun Interrupt Enable"] +pub struct OVR4_R(crate::FieldReader); +impl OVR4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR4` writer - Channel 4 Overrun Interrupt Enable"] +pub struct OVR4_W<'a> { + w: &'a mut W, +} +impl<'a> OVR4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `OVR5` reader - Channel 5 Overrun Interrupt Enable"] +pub struct OVR5_R(crate::FieldReader); +impl OVR5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR5` writer - Channel 5 Overrun Interrupt Enable"] +pub struct OVR5_W<'a> { + w: &'a mut W, +} +impl<'a> OVR5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `EVD0` reader - Channel 0 Event Detection Interrupt Enable"] +pub struct EVD0_R(crate::FieldReader); +impl EVD0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD0` writer - Channel 0 Event Detection Interrupt Enable"] +pub struct EVD0_W<'a> { + w: &'a mut W, +} +impl<'a> EVD0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `EVD1` reader - Channel 1 Event Detection Interrupt Enable"] +pub struct EVD1_R(crate::FieldReader); +impl EVD1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD1` writer - Channel 1 Event Detection Interrupt Enable"] +pub struct EVD1_W<'a> { + w: &'a mut W, +} +impl<'a> EVD1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `EVD2` reader - Channel 2 Event Detection Interrupt Enable"] +pub struct EVD2_R(crate::FieldReader); +impl EVD2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD2` writer - Channel 2 Event Detection Interrupt Enable"] +pub struct EVD2_W<'a> { + w: &'a mut W, +} +impl<'a> EVD2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `EVD3` reader - Channel 3 Event Detection Interrupt Enable"] +pub struct EVD3_R(crate::FieldReader); +impl EVD3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD3` writer - Channel 3 Event Detection Interrupt Enable"] +pub struct EVD3_W<'a> { + w: &'a mut W, +} +impl<'a> EVD3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `EVD4` reader - Channel 4 Event Detection Interrupt Enable"] +pub struct EVD4_R(crate::FieldReader); +impl EVD4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD4` writer - Channel 4 Event Detection Interrupt Enable"] +pub struct EVD4_W<'a> { + w: &'a mut W, +} +impl<'a> EVD4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `EVD5` reader - Channel 5 Event Detection Interrupt Enable"] +pub struct EVD5_R(crate::FieldReader); +impl EVD5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD5` writer - Channel 5 Event Detection Interrupt Enable"] +pub struct EVD5_W<'a> { + w: &'a mut W, +} +impl<'a> EVD5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +impl R { + #[doc = "Bit 0 - Channel 0 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr0(&self) -> OVR0_R { + OVR0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel 1 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr1(&self) -> OVR1_R { + OVR1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel 2 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr2(&self) -> OVR2_R { + OVR2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Channel 3 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr3(&self) -> OVR3_R { + OVR3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Channel 4 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr4(&self) -> OVR4_R { + OVR4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Channel 5 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr5(&self) -> OVR5_R { + OVR5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 16 - Channel 0 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd0(&self) -> EVD0_R { + EVD0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Channel 1 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd1(&self) -> EVD1_R { + EVD1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Channel 2 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd2(&self) -> EVD2_R { + EVD2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Channel 3 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd3(&self) -> EVD3_R { + EVD3_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Channel 4 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd4(&self) -> EVD4_R { + EVD4_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Channel 5 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd5(&self) -> EVD5_R { + EVD5_R::new(((self.bits >> 21) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel 0 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr0(&mut self) -> OVR0_W { + OVR0_W { w: self } + } + #[doc = "Bit 1 - Channel 1 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr1(&mut self) -> OVR1_W { + OVR1_W { w: self } + } + #[doc = "Bit 2 - Channel 2 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr2(&mut self) -> OVR2_W { + OVR2_W { w: self } + } + #[doc = "Bit 3 - Channel 3 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr3(&mut self) -> OVR3_W { + OVR3_W { w: self } + } + #[doc = "Bit 4 - Channel 4 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr4(&mut self) -> OVR4_W { + OVR4_W { w: self } + } + #[doc = "Bit 5 - Channel 5 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr5(&mut self) -> OVR5_W { + OVR5_W { w: self } + } + #[doc = "Bit 16 - Channel 0 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd0(&mut self) -> EVD0_W { + EVD0_W { w: self } + } + #[doc = "Bit 17 - Channel 1 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd1(&mut self) -> EVD1_W { + EVD1_W { w: self } + } + #[doc = "Bit 18 - Channel 2 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd2(&mut self) -> EVD2_W { + EVD2_W { w: self } + } + #[doc = "Bit 19 - Channel 3 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd3(&mut self) -> EVD3_W { + EVD3_W { w: self } + } + #[doc = "Bit 20 - Channel 4 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd4(&mut self) -> EVD4_W { + EVD4_W { w: self } + } + #[doc = "Bit 21 - Channel 5 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd5(&mut self) -> EVD5_W { + EVD5_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/evsys/intflag.rs b/pac/atsamc20e/src/evsys/intflag.rs new file mode 100644 index 000000000000..fa72ee78a84f --- /dev/null +++ b/pac/atsamc20e/src/evsys/intflag.rs @@ -0,0 +1,630 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVR0` reader - Channel 0 Overrun"] +pub struct OVR0_R(crate::FieldReader); +impl OVR0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR0` writer - Channel 0 Overrun"] +pub struct OVR0_W<'a> { + w: &'a mut W, +} +impl<'a> OVR0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `OVR1` reader - Channel 1 Overrun"] +pub struct OVR1_R(crate::FieldReader); +impl OVR1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR1` writer - Channel 1 Overrun"] +pub struct OVR1_W<'a> { + w: &'a mut W, +} +impl<'a> OVR1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `OVR2` reader - Channel 2 Overrun"] +pub struct OVR2_R(crate::FieldReader); +impl OVR2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR2` writer - Channel 2 Overrun"] +pub struct OVR2_W<'a> { + w: &'a mut W, +} +impl<'a> OVR2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `OVR3` reader - Channel 3 Overrun"] +pub struct OVR3_R(crate::FieldReader); +impl OVR3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR3` writer - Channel 3 Overrun"] +pub struct OVR3_W<'a> { + w: &'a mut W, +} +impl<'a> OVR3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `OVR4` reader - Channel 4 Overrun"] +pub struct OVR4_R(crate::FieldReader); +impl OVR4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR4` writer - Channel 4 Overrun"] +pub struct OVR4_W<'a> { + w: &'a mut W, +} +impl<'a> OVR4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `OVR5` reader - Channel 5 Overrun"] +pub struct OVR5_R(crate::FieldReader); +impl OVR5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR5` writer - Channel 5 Overrun"] +pub struct OVR5_W<'a> { + w: &'a mut W, +} +impl<'a> OVR5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `EVD0` reader - Channel 0 Event Detection"] +pub struct EVD0_R(crate::FieldReader); +impl EVD0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD0` writer - Channel 0 Event Detection"] +pub struct EVD0_W<'a> { + w: &'a mut W, +} +impl<'a> EVD0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `EVD1` reader - Channel 1 Event Detection"] +pub struct EVD1_R(crate::FieldReader); +impl EVD1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD1` writer - Channel 1 Event Detection"] +pub struct EVD1_W<'a> { + w: &'a mut W, +} +impl<'a> EVD1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `EVD2` reader - Channel 2 Event Detection"] +pub struct EVD2_R(crate::FieldReader); +impl EVD2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD2` writer - Channel 2 Event Detection"] +pub struct EVD2_W<'a> { + w: &'a mut W, +} +impl<'a> EVD2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `EVD3` reader - Channel 3 Event Detection"] +pub struct EVD3_R(crate::FieldReader); +impl EVD3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD3` writer - Channel 3 Event Detection"] +pub struct EVD3_W<'a> { + w: &'a mut W, +} +impl<'a> EVD3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `EVD4` reader - Channel 4 Event Detection"] +pub struct EVD4_R(crate::FieldReader); +impl EVD4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD4` writer - Channel 4 Event Detection"] +pub struct EVD4_W<'a> { + w: &'a mut W, +} +impl<'a> EVD4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `EVD5` reader - Channel 5 Event Detection"] +pub struct EVD5_R(crate::FieldReader); +impl EVD5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD5` writer - Channel 5 Event Detection"] +pub struct EVD5_W<'a> { + w: &'a mut W, +} +impl<'a> EVD5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +impl R { + #[doc = "Bit 0 - Channel 0 Overrun"] + #[inline(always)] + pub fn ovr0(&self) -> OVR0_R { + OVR0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel 1 Overrun"] + #[inline(always)] + pub fn ovr1(&self) -> OVR1_R { + OVR1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel 2 Overrun"] + #[inline(always)] + pub fn ovr2(&self) -> OVR2_R { + OVR2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Channel 3 Overrun"] + #[inline(always)] + pub fn ovr3(&self) -> OVR3_R { + OVR3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Channel 4 Overrun"] + #[inline(always)] + pub fn ovr4(&self) -> OVR4_R { + OVR4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Channel 5 Overrun"] + #[inline(always)] + pub fn ovr5(&self) -> OVR5_R { + OVR5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 16 - Channel 0 Event Detection"] + #[inline(always)] + pub fn evd0(&self) -> EVD0_R { + EVD0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Channel 1 Event Detection"] + #[inline(always)] + pub fn evd1(&self) -> EVD1_R { + EVD1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Channel 2 Event Detection"] + #[inline(always)] + pub fn evd2(&self) -> EVD2_R { + EVD2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Channel 3 Event Detection"] + #[inline(always)] + pub fn evd3(&self) -> EVD3_R { + EVD3_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Channel 4 Event Detection"] + #[inline(always)] + pub fn evd4(&self) -> EVD4_R { + EVD4_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Channel 5 Event Detection"] + #[inline(always)] + pub fn evd5(&self) -> EVD5_R { + EVD5_R::new(((self.bits >> 21) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel 0 Overrun"] + #[inline(always)] + pub fn ovr0(&mut self) -> OVR0_W { + OVR0_W { w: self } + } + #[doc = "Bit 1 - Channel 1 Overrun"] + #[inline(always)] + pub fn ovr1(&mut self) -> OVR1_W { + OVR1_W { w: self } + } + #[doc = "Bit 2 - Channel 2 Overrun"] + #[inline(always)] + pub fn ovr2(&mut self) -> OVR2_W { + OVR2_W { w: self } + } + #[doc = "Bit 3 - Channel 3 Overrun"] + #[inline(always)] + pub fn ovr3(&mut self) -> OVR3_W { + OVR3_W { w: self } + } + #[doc = "Bit 4 - Channel 4 Overrun"] + #[inline(always)] + pub fn ovr4(&mut self) -> OVR4_W { + OVR4_W { w: self } + } + #[doc = "Bit 5 - Channel 5 Overrun"] + #[inline(always)] + pub fn ovr5(&mut self) -> OVR5_W { + OVR5_W { w: self } + } + #[doc = "Bit 16 - Channel 0 Event Detection"] + #[inline(always)] + pub fn evd0(&mut self) -> EVD0_W { + EVD0_W { w: self } + } + #[doc = "Bit 17 - Channel 1 Event Detection"] + #[inline(always)] + pub fn evd1(&mut self) -> EVD1_W { + EVD1_W { w: self } + } + #[doc = "Bit 18 - Channel 2 Event Detection"] + #[inline(always)] + pub fn evd2(&mut self) -> EVD2_W { + EVD2_W { w: self } + } + #[doc = "Bit 19 - Channel 3 Event Detection"] + #[inline(always)] + pub fn evd3(&mut self) -> EVD3_W { + EVD3_W { w: self } + } + #[doc = "Bit 20 - Channel 4 Event Detection"] + #[inline(always)] + pub fn evd4(&mut self) -> EVD4_W { + EVD4_W { w: self } + } + #[doc = "Bit 21 - Channel 5 Event Detection"] + #[inline(always)] + pub fn evd5(&mut self) -> EVD5_W { + EVD5_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/evsys/swevt.rs b/pac/atsamc20e/src/evsys/swevt.rs new file mode 100644 index 000000000000..ba358dc12664 --- /dev/null +++ b/pac/atsamc20e/src/evsys/swevt.rs @@ -0,0 +1,207 @@ +#[doc = "Register `SWEVT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHANNEL0` writer - Channel 0 Software Selection"] +pub struct CHANNEL0_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `CHANNEL1` writer - Channel 1 Software Selection"] +pub struct CHANNEL1_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CHANNEL2` writer - Channel 2 Software Selection"] +pub struct CHANNEL2_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CHANNEL3` writer - Channel 3 Software Selection"] +pub struct CHANNEL3_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CHANNEL4` writer - Channel 4 Software Selection"] +pub struct CHANNEL4_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `CHANNEL5` writer - Channel 5 Software Selection"] +pub struct CHANNEL5_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +impl W { + #[doc = "Bit 0 - Channel 0 Software Selection"] + #[inline(always)] + pub fn channel0(&mut self) -> CHANNEL0_W { + CHANNEL0_W { w: self } + } + #[doc = "Bit 1 - Channel 1 Software Selection"] + #[inline(always)] + pub fn channel1(&mut self) -> CHANNEL1_W { + CHANNEL1_W { w: self } + } + #[doc = "Bit 2 - Channel 2 Software Selection"] + #[inline(always)] + pub fn channel2(&mut self) -> CHANNEL2_W { + CHANNEL2_W { w: self } + } + #[doc = "Bit 3 - Channel 3 Software Selection"] + #[inline(always)] + pub fn channel3(&mut self) -> CHANNEL3_W { + CHANNEL3_W { w: self } + } + #[doc = "Bit 4 - Channel 4 Software Selection"] + #[inline(always)] + pub fn channel4(&mut self) -> CHANNEL4_W { + CHANNEL4_W { w: self } + } + #[doc = "Bit 5 - Channel 5 Software Selection"] + #[inline(always)] + pub fn channel5(&mut self) -> CHANNEL5_W { + CHANNEL5_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Software Event\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [swevt](index.html) module"] +pub struct SWEVT_SPEC; +impl crate::RegisterSpec for SWEVT_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [swevt::W](W) writer structure"] +impl crate::Writable for SWEVT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SWEVT to value 0"] +impl crate::Resettable for SWEVT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/evsys/user.rs b/pac/atsamc20e/src/evsys/user.rs new file mode 100644 index 000000000000..efc20862bfe8 --- /dev/null +++ b/pac/atsamc20e/src/evsys/user.rs @@ -0,0 +1,104 @@ +#[doc = "Register `USER[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `USER[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHANNEL` reader - Channel Event Selection"] +pub struct CHANNEL_R(crate::FieldReader); +impl CHANNEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CHANNEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHANNEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHANNEL` writer - Channel Event Selection"] +pub struct CHANNEL_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Channel Event Selection"] + #[inline(always)] + pub fn channel(&self) -> CHANNEL_R { + CHANNEL_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Channel Event Selection"] + #[inline(always)] + pub fn channel(&mut self) -> CHANNEL_W { + CHANNEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "User Multiplexer n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [user](index.html) module"] +pub struct USER_SPEC; +impl crate::RegisterSpec for USER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [user::R](R) reader structure"] +impl crate::Readable for USER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [user::W](W) writer structure"] +impl crate::Writable for USER_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets USER[%s] +to value 0"] +impl crate::Resettable for USER_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/freqm.rs b/pac/atsamc20e/src/freqm.rs new file mode 100644 index 000000000000..f0fc6fda975e --- /dev/null +++ b/pac/atsamc20e/src/freqm.rs @@ -0,0 +1,59 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control A Register"] + pub ctrla: crate::Reg, + #[doc = "0x01 - Control B Register"] + pub ctrlb: crate::Reg, + #[doc = "0x02 - Config A register"] + pub cfga: crate::Reg, + _reserved3: [u8; 0x04], + #[doc = "0x08 - Interrupt Enable Clear Register"] + pub intenclr: crate::Reg, + #[doc = "0x09 - Interrupt Enable Set Register"] + pub intenset: crate::Reg, + #[doc = "0x0a - Interrupt Flag Register"] + pub intflag: crate::Reg, + #[doc = "0x0b - Status Register"] + pub status: crate::Reg, + #[doc = "0x0c - Synchronization Busy Register"] + pub syncbusy: crate::Reg, + #[doc = "0x10 - Count Value Register"] + pub value: crate::Reg, +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A Register"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "Control B Register"] +pub mod ctrlb; +#[doc = "CFGA register accessor: an alias for `Reg`"] +pub type CFGA = crate::Reg; +#[doc = "Config A register"] +pub mod cfga; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear Register"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set Register"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Register"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status Register"] +pub mod status; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Busy Register"] +pub mod syncbusy; +#[doc = "VALUE register accessor: an alias for `Reg`"] +pub type VALUE = crate::Reg; +#[doc = "Count Value Register"] +pub mod value; diff --git a/pac/atsamc20e/src/freqm/cfga.rs b/pac/atsamc20e/src/freqm/cfga.rs new file mode 100644 index 000000000000..573c62964185 --- /dev/null +++ b/pac/atsamc20e/src/freqm/cfga.rs @@ -0,0 +1,103 @@ +#[doc = "Register `CFGA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CFGA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `REFNUM` reader - Number of Reference Clock Cycles"] +pub struct REFNUM_R(crate::FieldReader); +impl REFNUM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REFNUM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REFNUM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REFNUM` writer - Number of Reference Clock Cycles"] +pub struct REFNUM_W<'a> { + w: &'a mut W, +} +impl<'a> REFNUM_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u16 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Number of Reference Clock Cycles"] + #[inline(always)] + pub fn refnum(&self) -> REFNUM_R { + REFNUM_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Number of Reference Clock Cycles"] + #[inline(always)] + pub fn refnum(&mut self) -> REFNUM_W { + REFNUM_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Config A register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cfga](index.html) module"] +pub struct CFGA_SPEC; +impl crate::RegisterSpec for CFGA_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [cfga::R](R) reader structure"] +impl crate::Readable for CFGA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cfga::W](W) writer structure"] +impl crate::Writable for CFGA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CFGA to value 0"] +impl crate::Resettable for CFGA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/freqm/ctrla.rs b/pac/atsamc20e/src/freqm/ctrla.rs new file mode 100644 index 000000000000..b2cefdd45770 --- /dev/null +++ b/pac/atsamc20e/src/freqm/ctrla.rs @@ -0,0 +1,160 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/freqm/ctrlb.rs b/pac/atsamc20e/src/freqm/ctrlb.rs new file mode 100644 index 000000000000..7d350e71fbf3 --- /dev/null +++ b/pac/atsamc20e/src/freqm/ctrlb.rs @@ -0,0 +1,72 @@ +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `START` writer - Start Measurement"] +pub struct START_W<'a> { + w: &'a mut W, +} +impl<'a> START_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0 - Start Measurement"] + #[inline(always)] + pub fn start(&mut self) -> START_W { + START_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u8; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/freqm/intenclr.rs b/pac/atsamc20e/src/freqm/intenclr.rs new file mode 100644 index 000000000000..a224aa5500f6 --- /dev/null +++ b/pac/atsamc20e/src/freqm/intenclr.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DONE` reader - Measurement Done Interrupt Enable"] +pub struct DONE_R(crate::FieldReader); +impl DONE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DONE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DONE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DONE` writer - Measurement Done Interrupt Enable"] +pub struct DONE_W<'a> { + w: &'a mut W, +} +impl<'a> DONE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Measurement Done Interrupt Enable"] + #[inline(always)] + pub fn done(&self) -> DONE_R { + DONE_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Measurement Done Interrupt Enable"] + #[inline(always)] + pub fn done(&mut self) -> DONE_W { + DONE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/freqm/intenset.rs b/pac/atsamc20e/src/freqm/intenset.rs new file mode 100644 index 000000000000..53b3d0bef7c0 --- /dev/null +++ b/pac/atsamc20e/src/freqm/intenset.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DONE` reader - Measurement Done Interrupt Enable"] +pub struct DONE_R(crate::FieldReader); +impl DONE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DONE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DONE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DONE` writer - Measurement Done Interrupt Enable"] +pub struct DONE_W<'a> { + w: &'a mut W, +} +impl<'a> DONE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Measurement Done Interrupt Enable"] + #[inline(always)] + pub fn done(&self) -> DONE_R { + DONE_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Measurement Done Interrupt Enable"] + #[inline(always)] + pub fn done(&mut self) -> DONE_W { + DONE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/freqm/intflag.rs b/pac/atsamc20e/src/freqm/intflag.rs new file mode 100644 index 000000000000..3b8fdab47703 --- /dev/null +++ b/pac/atsamc20e/src/freqm/intflag.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DONE` reader - Measurement Done"] +pub struct DONE_R(crate::FieldReader); +impl DONE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DONE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DONE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DONE` writer - Measurement Done"] +pub struct DONE_W<'a> { + w: &'a mut W, +} +impl<'a> DONE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Measurement Done"] + #[inline(always)] + pub fn done(&self) -> DONE_R { + DONE_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Measurement Done"] + #[inline(always)] + pub fn done(&mut self) -> DONE_W { + DONE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/freqm/status.rs b/pac/atsamc20e/src/freqm/status.rs new file mode 100644 index 000000000000..8a81662f51b0 --- /dev/null +++ b/pac/atsamc20e/src/freqm/status.rs @@ -0,0 +1,160 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BUSY` reader - FREQM Status"] +pub struct BUSY_R(crate::FieldReader); +impl BUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSY` writer - FREQM Status"] +pub struct BUSY_W<'a> { + w: &'a mut W, +} +impl<'a> BUSY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `OVF` reader - Sticky Count Value Overflow"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Sticky Count Value Overflow"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - FREQM Status"] + #[inline(always)] + pub fn busy(&self) -> BUSY_R { + BUSY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Sticky Count Value Overflow"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - FREQM Status"] + #[inline(always)] + pub fn busy(&mut self) -> BUSY_W { + BUSY_W { w: self } + } + #[doc = "Bit 1 - Sticky Count Value Overflow"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/freqm/syncbusy.rs b/pac/atsamc20e/src/freqm/syncbusy.rs new file mode 100644 index 000000000000..54396368e817 --- /dev/null +++ b/pac/atsamc20e/src/freqm/syncbusy.rs @@ -0,0 +1,73 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +#[doc = "Synchronization Busy Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/freqm/value.rs b/pac/atsamc20e/src/freqm/value.rs new file mode 100644 index 000000000000..5b0f5dfd9b67 --- /dev/null +++ b/pac/atsamc20e/src/freqm/value.rs @@ -0,0 +1,53 @@ +#[doc = "Register `VALUE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `VALUE` reader - Measurement Value"] +pub struct VALUE_R(crate::FieldReader); +impl VALUE_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + VALUE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VALUE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:23 - Measurement Value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +#[doc = "Count Value Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [value](index.html) module"] +pub struct VALUE_SPEC; +impl crate::RegisterSpec for VALUE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [value::R](R) reader structure"] +impl crate::Readable for VALUE_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets VALUE to value 0"] +impl crate::Resettable for VALUE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/gclk.rs b/pac/atsamc20e/src/gclk.rs new file mode 100644 index 000000000000..2a37bdedcab3 --- /dev/null +++ b/pac/atsamc20e/src/gclk.rs @@ -0,0 +1,31 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrla: crate::Reg, + _reserved1: [u8; 0x03], + #[doc = "0x04 - Synchronization Busy"] + pub syncbusy: crate::Reg, + _reserved2: [u8; 0x18], + #[doc = "0x20..0x44 - Generic Clock Generator Control"] + pub genctrl: [crate::Reg; 9], + _reserved3: [u8; 0x3c], + #[doc = "0x80..0x124 - Peripheral Clock Control"] + pub pchctrl: [crate::Reg; 41], +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control"] +pub mod ctrla; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Busy"] +pub mod syncbusy; +#[doc = "GENCTRL register accessor: an alias for `Reg`"] +pub type GENCTRL = crate::Reg; +#[doc = "Generic Clock Generator Control"] +pub mod genctrl; +#[doc = "PCHCTRL register accessor: an alias for `Reg`"] +pub type PCHCTRL = crate::Reg; +#[doc = "Peripheral Clock Control"] +pub mod pchctrl; diff --git a/pac/atsamc20e/src/gclk/ctrla.rs b/pac/atsamc20e/src/gclk/ctrla.rs new file mode 100644 index 000000000000..1c24704395ad --- /dev/null +++ b/pac/atsamc20e/src/gclk/ctrla.rs @@ -0,0 +1,113 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/gclk/genctrl.rs b/pac/atsamc20e/src/gclk/genctrl.rs new file mode 100644 index 000000000000..052b2915ca7f --- /dev/null +++ b/pac/atsamc20e/src/gclk/genctrl.rs @@ -0,0 +1,597 @@ +#[doc = "Register `GENCTRL[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GENCTRL[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Source Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SRC_A { + #[doc = "0: XOSC oscillator output"] + XOSC = 0, + #[doc = "1: Generator input pad"] + GCLKIN = 1, + #[doc = "2: Generic clock generator 1 output"] + GCLKGEN1 = 2, + #[doc = "3: OSCULP32K oscillator output"] + OSCULP32K = 3, + #[doc = "4: OSC32K oscillator output"] + OSC32K = 4, + #[doc = "5: XOSC32K oscillator output"] + XOSC32K = 5, + #[doc = "6: OSC48M oscillator output"] + OSC48M = 6, + #[doc = "7: DPLL96M output"] + DPLL96M = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SRC_A) -> Self { + variant as _ + } +} +#[doc = "Field `SRC` reader - Source Select"] +pub struct SRC_R(crate::FieldReader); +impl SRC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SRC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SRC_A { + match self.bits { + 0 => SRC_A::XOSC, + 1 => SRC_A::GCLKIN, + 2 => SRC_A::GCLKGEN1, + 3 => SRC_A::OSCULP32K, + 4 => SRC_A::OSC32K, + 5 => SRC_A::XOSC32K, + 6 => SRC_A::OSC48M, + 7 => SRC_A::DPLL96M, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `XOSC`"] + #[inline(always)] + pub fn is_xosc(&self) -> bool { + **self == SRC_A::XOSC + } + #[doc = "Checks if the value of the field is `GCLKIN`"] + #[inline(always)] + pub fn is_gclkin(&self) -> bool { + **self == SRC_A::GCLKIN + } + #[doc = "Checks if the value of the field is `GCLKGEN1`"] + #[inline(always)] + pub fn is_gclkgen1(&self) -> bool { + **self == SRC_A::GCLKGEN1 + } + #[doc = "Checks if the value of the field is `OSCULP32K`"] + #[inline(always)] + pub fn is_osculp32k(&self) -> bool { + **self == SRC_A::OSCULP32K + } + #[doc = "Checks if the value of the field is `OSC32K`"] + #[inline(always)] + pub fn is_osc32k(&self) -> bool { + **self == SRC_A::OSC32K + } + #[doc = "Checks if the value of the field is `XOSC32K`"] + #[inline(always)] + pub fn is_xosc32k(&self) -> bool { + **self == SRC_A::XOSC32K + } + #[doc = "Checks if the value of the field is `OSC48M`"] + #[inline(always)] + pub fn is_osc48m(&self) -> bool { + **self == SRC_A::OSC48M + } + #[doc = "Checks if the value of the field is `DPLL96M`"] + #[inline(always)] + pub fn is_dpll96m(&self) -> bool { + **self == SRC_A::DPLL96M + } +} +impl core::ops::Deref for SRC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SRC` writer - Source Select"] +pub struct SRC_W<'a> { + w: &'a mut W, +} +impl<'a> SRC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SRC_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "XOSC oscillator output"] + #[inline(always)] + pub fn xosc(self) -> &'a mut W { + self.variant(SRC_A::XOSC) + } + #[doc = "Generator input pad"] + #[inline(always)] + pub fn gclkin(self) -> &'a mut W { + self.variant(SRC_A::GCLKIN) + } + #[doc = "Generic clock generator 1 output"] + #[inline(always)] + pub fn gclkgen1(self) -> &'a mut W { + self.variant(SRC_A::GCLKGEN1) + } + #[doc = "OSCULP32K oscillator output"] + #[inline(always)] + pub fn osculp32k(self) -> &'a mut W { + self.variant(SRC_A::OSCULP32K) + } + #[doc = "OSC32K oscillator output"] + #[inline(always)] + pub fn osc32k(self) -> &'a mut W { + self.variant(SRC_A::OSC32K) + } + #[doc = "XOSC32K oscillator output"] + #[inline(always)] + pub fn xosc32k(self) -> &'a mut W { + self.variant(SRC_A::XOSC32K) + } + #[doc = "OSC48M oscillator output"] + #[inline(always)] + pub fn osc48m(self) -> &'a mut W { + self.variant(SRC_A::OSC48M) + } + #[doc = "DPLL96M output"] + #[inline(always)] + pub fn dpll96m(self) -> &'a mut W { + self.variant(SRC_A::DPLL96M) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Field `GENEN` reader - Generic Clock Generator Enable"] +pub struct GENEN_R(crate::FieldReader); +impl GENEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENEN` writer - Generic Clock Generator Enable"] +pub struct GENEN_W<'a> { + w: &'a mut W, +} +impl<'a> GENEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `IDC` reader - Improve Duty Cycle"] +pub struct IDC_R(crate::FieldReader); +impl IDC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IDC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IDC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IDC` writer - Improve Duty Cycle"] +pub struct IDC_W<'a> { + w: &'a mut W, +} +impl<'a> IDC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `OOV` reader - Output Off Value"] +pub struct OOV_R(crate::FieldReader); +impl OOV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OOV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OOV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OOV` writer - Output Off Value"] +pub struct OOV_W<'a> { + w: &'a mut W, +} +impl<'a> OOV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `OE` reader - Output Enable"] +pub struct OE_R(crate::FieldReader); +impl OE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OE` writer - Output Enable"] +pub struct OE_W<'a> { + w: &'a mut W, +} +impl<'a> OE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Divide Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum DIVSEL_A { + #[doc = "0: Divide input directly by divider factor"] + DIV1 = 0, + #[doc = "1: Divide input by 2^(divider factor+ 1)"] + DIV2 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DIVSEL_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DIVSEL` reader - Divide Selection"] +pub struct DIVSEL_R(crate::FieldReader); +impl DIVSEL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIVSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DIVSEL_A { + match self.bits { + false => DIVSEL_A::DIV1, + true => DIVSEL_A::DIV2, + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == DIVSEL_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == DIVSEL_A::DIV2 + } +} +impl core::ops::Deref for DIVSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIVSEL` writer - Divide Selection"] +pub struct DIVSEL_W<'a> { + w: &'a mut W, +} +impl<'a> DIVSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DIVSEL_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Divide input directly by divider factor"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(DIVSEL_A::DIV1) + } + #[doc = "Divide input by 2^(divider factor+ 1)"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(DIVSEL_A::DIV2) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `DIV` reader - Division Factor"] +pub struct DIV_R(crate::FieldReader); +impl DIV_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + DIV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIV` writer - Division Factor"] +pub struct DIV_W<'a> { + w: &'a mut W, +} +impl<'a> DIV_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xffff << 16)) | ((value as u32 & 0xffff) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Source Select"] + #[inline(always)] + pub fn src(&self) -> SRC_R { + SRC_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 8 - Generic Clock Generator Enable"] + #[inline(always)] + pub fn genen(&self) -> GENEN_R { + GENEN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Improve Duty Cycle"] + #[inline(always)] + pub fn idc(&self) -> IDC_R { + IDC_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Output Off Value"] + #[inline(always)] + pub fn oov(&self) -> OOV_R { + OOV_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Output Enable"] + #[inline(always)] + pub fn oe(&self) -> OE_R { + OE_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Divide Selection"] + #[inline(always)] + pub fn divsel(&self) -> DIVSEL_R { + DIVSEL_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bits 16:31 - Division Factor"] + #[inline(always)] + pub fn div(&self) -> DIV_R { + DIV_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:2 - Source Select"] + #[inline(always)] + pub fn src(&mut self) -> SRC_W { + SRC_W { w: self } + } + #[doc = "Bit 8 - Generic Clock Generator Enable"] + #[inline(always)] + pub fn genen(&mut self) -> GENEN_W { + GENEN_W { w: self } + } + #[doc = "Bit 9 - Improve Duty Cycle"] + #[inline(always)] + pub fn idc(&mut self) -> IDC_W { + IDC_W { w: self } + } + #[doc = "Bit 10 - Output Off Value"] + #[inline(always)] + pub fn oov(&mut self) -> OOV_W { + OOV_W { w: self } + } + #[doc = "Bit 11 - Output Enable"] + #[inline(always)] + pub fn oe(&mut self) -> OE_W { + OE_W { w: self } + } + #[doc = "Bit 12 - Divide Selection"] + #[inline(always)] + pub fn divsel(&mut self) -> DIVSEL_W { + DIVSEL_W { w: self } + } + #[doc = "Bit 13 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bits 16:31 - Division Factor"] + #[inline(always)] + pub fn div(&mut self) -> DIV_W { + DIV_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Generic Clock Generator Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [genctrl](index.html) module"] +pub struct GENCTRL_SPEC; +impl crate::RegisterSpec for GENCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [genctrl::R](R) reader structure"] +impl crate::Readable for GENCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [genctrl::W](W) writer structure"] +impl crate::Writable for GENCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets GENCTRL[%s] +to value 0"] +impl crate::Resettable for GENCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/gclk/pchctrl.rs b/pac/atsamc20e/src/gclk/pchctrl.rs new file mode 100644 index 000000000000..8001ffeaa1ee --- /dev/null +++ b/pac/atsamc20e/src/gclk/pchctrl.rs @@ -0,0 +1,338 @@ +#[doc = "Register `PCHCTRL[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PCHCTRL[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Generic Clock Generator\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum GEN_A { + #[doc = "0: Generic clock generator 0"] + GCLK0 = 0, + #[doc = "1: Generic clock generator 1"] + GCLK1 = 1, + #[doc = "2: Generic clock generator 2"] + GCLK2 = 2, + #[doc = "3: Generic clock generator 3"] + GCLK3 = 3, + #[doc = "4: Generic clock generator 4"] + GCLK4 = 4, + #[doc = "5: Generic clock generator 5"] + GCLK5 = 5, + #[doc = "6: Generic clock generator 6"] + GCLK6 = 6, + #[doc = "7: Generic clock generator 7"] + GCLK7 = 7, + #[doc = "8: Generic clock generator 8"] + GCLK8 = 8, +} +impl From for u8 { + #[inline(always)] + fn from(variant: GEN_A) -> Self { + variant as _ + } +} +#[doc = "Field `GEN` reader - Generic Clock Generator"] +pub struct GEN_R(crate::FieldReader); +impl GEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + GEN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(GEN_A::GCLK0), + 1 => Some(GEN_A::GCLK1), + 2 => Some(GEN_A::GCLK2), + 3 => Some(GEN_A::GCLK3), + 4 => Some(GEN_A::GCLK4), + 5 => Some(GEN_A::GCLK5), + 6 => Some(GEN_A::GCLK6), + 7 => Some(GEN_A::GCLK7), + 8 => Some(GEN_A::GCLK8), + _ => None, + } + } + #[doc = "Checks if the value of the field is `GCLK0`"] + #[inline(always)] + pub fn is_gclk0(&self) -> bool { + **self == GEN_A::GCLK0 + } + #[doc = "Checks if the value of the field is `GCLK1`"] + #[inline(always)] + pub fn is_gclk1(&self) -> bool { + **self == GEN_A::GCLK1 + } + #[doc = "Checks if the value of the field is `GCLK2`"] + #[inline(always)] + pub fn is_gclk2(&self) -> bool { + **self == GEN_A::GCLK2 + } + #[doc = "Checks if the value of the field is `GCLK3`"] + #[inline(always)] + pub fn is_gclk3(&self) -> bool { + **self == GEN_A::GCLK3 + } + #[doc = "Checks if the value of the field is `GCLK4`"] + #[inline(always)] + pub fn is_gclk4(&self) -> bool { + **self == GEN_A::GCLK4 + } + #[doc = "Checks if the value of the field is `GCLK5`"] + #[inline(always)] + pub fn is_gclk5(&self) -> bool { + **self == GEN_A::GCLK5 + } + #[doc = "Checks if the value of the field is `GCLK6`"] + #[inline(always)] + pub fn is_gclk6(&self) -> bool { + **self == GEN_A::GCLK6 + } + #[doc = "Checks if the value of the field is `GCLK7`"] + #[inline(always)] + pub fn is_gclk7(&self) -> bool { + **self == GEN_A::GCLK7 + } + #[doc = "Checks if the value of the field is `GCLK8`"] + #[inline(always)] + pub fn is_gclk8(&self) -> bool { + **self == GEN_A::GCLK8 + } +} +impl core::ops::Deref for GEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GEN` writer - Generic Clock Generator"] +pub struct GEN_W<'a> { + w: &'a mut W, +} +impl<'a> GEN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: GEN_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Generic clock generator 0"] + #[inline(always)] + pub fn gclk0(self) -> &'a mut W { + self.variant(GEN_A::GCLK0) + } + #[doc = "Generic clock generator 1"] + #[inline(always)] + pub fn gclk1(self) -> &'a mut W { + self.variant(GEN_A::GCLK1) + } + #[doc = "Generic clock generator 2"] + #[inline(always)] + pub fn gclk2(self) -> &'a mut W { + self.variant(GEN_A::GCLK2) + } + #[doc = "Generic clock generator 3"] + #[inline(always)] + pub fn gclk3(self) -> &'a mut W { + self.variant(GEN_A::GCLK3) + } + #[doc = "Generic clock generator 4"] + #[inline(always)] + pub fn gclk4(self) -> &'a mut W { + self.variant(GEN_A::GCLK4) + } + #[doc = "Generic clock generator 5"] + #[inline(always)] + pub fn gclk5(self) -> &'a mut W { + self.variant(GEN_A::GCLK5) + } + #[doc = "Generic clock generator 6"] + #[inline(always)] + pub fn gclk6(self) -> &'a mut W { + self.variant(GEN_A::GCLK6) + } + #[doc = "Generic clock generator 7"] + #[inline(always)] + pub fn gclk7(self) -> &'a mut W { + self.variant(GEN_A::GCLK7) + } + #[doc = "Generic clock generator 8"] + #[inline(always)] + pub fn gclk8(self) -> &'a mut W { + self.variant(GEN_A::GCLK8) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Field `CHEN` reader - Channel Enable"] +pub struct CHEN_R(crate::FieldReader); +impl CHEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHEN` writer - Channel Enable"] +pub struct CHEN_W<'a> { + w: &'a mut W, +} +impl<'a> CHEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `WRTLOCK` reader - Write Lock"] +pub struct WRTLOCK_R(crate::FieldReader); +impl WRTLOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WRTLOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WRTLOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WRTLOCK` writer - Write Lock"] +pub struct WRTLOCK_W<'a> { + w: &'a mut W, +} +impl<'a> WRTLOCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Generic Clock Generator"] + #[inline(always)] + pub fn gen(&self) -> GEN_R { + GEN_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 6 - Channel Enable"] + #[inline(always)] + pub fn chen(&self) -> CHEN_R { + CHEN_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&self) -> WRTLOCK_R { + WRTLOCK_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Generic Clock Generator"] + #[inline(always)] + pub fn gen(&mut self) -> GEN_W { + GEN_W { w: self } + } + #[doc = "Bit 6 - Channel Enable"] + #[inline(always)] + pub fn chen(&mut self) -> CHEN_W { + CHEN_W { w: self } + } + #[doc = "Bit 7 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&mut self) -> WRTLOCK_W { + WRTLOCK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Peripheral Clock Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pchctrl](index.html) module"] +pub struct PCHCTRL_SPEC; +impl crate::RegisterSpec for PCHCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pchctrl::R](R) reader structure"] +impl crate::Readable for PCHCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [pchctrl::W](W) writer structure"] +impl crate::Writable for PCHCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PCHCTRL[%s] +to value 0"] +impl crate::Resettable for PCHCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/gclk/syncbusy.rs b/pac/atsamc20e/src/gclk/syncbusy.rs new file mode 100644 index 000000000000..f21640440354 --- /dev/null +++ b/pac/atsamc20e/src/gclk/syncbusy.rs @@ -0,0 +1,233 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchroniation Busy bit"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENCTRL0` reader - Generic Clock Generator Control 0 Synchronization Busy bits"] +pub struct GENCTRL0_R(crate::FieldReader); +impl GENCTRL0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENCTRL0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENCTRL0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENCTRL1` reader - Generic Clock Generator Control 1 Synchronization Busy bits"] +pub struct GENCTRL1_R(crate::FieldReader); +impl GENCTRL1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENCTRL1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENCTRL1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENCTRL2` reader - Generic Clock Generator Control 2 Synchronization Busy bits"] +pub struct GENCTRL2_R(crate::FieldReader); +impl GENCTRL2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENCTRL2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENCTRL2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENCTRL3` reader - Generic Clock Generator Control 3 Synchronization Busy bits"] +pub struct GENCTRL3_R(crate::FieldReader); +impl GENCTRL3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENCTRL3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENCTRL3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENCTRL4` reader - Generic Clock Generator Control 4 Synchronization Busy bits"] +pub struct GENCTRL4_R(crate::FieldReader); +impl GENCTRL4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENCTRL4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENCTRL4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENCTRL5` reader - Generic Clock Generator Control 5 Synchronization Busy bits"] +pub struct GENCTRL5_R(crate::FieldReader); +impl GENCTRL5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENCTRL5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENCTRL5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENCTRL6` reader - Generic Clock Generator Control 6 Synchronization Busy bits"] +pub struct GENCTRL6_R(crate::FieldReader); +impl GENCTRL6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENCTRL6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENCTRL6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENCTRL7` reader - Generic Clock Generator Control 7 Synchronization Busy bits"] +pub struct GENCTRL7_R(crate::FieldReader); +impl GENCTRL7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENCTRL7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENCTRL7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENCTRL8` reader - Generic Clock Generator Control 8 Synchronization Busy bits"] +pub struct GENCTRL8_R(crate::FieldReader); +impl GENCTRL8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENCTRL8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENCTRL8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchroniation Busy bit"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 2 - Generic Clock Generator Control 0 Synchronization Busy bits"] + #[inline(always)] + pub fn genctrl0(&self) -> GENCTRL0_R { + GENCTRL0_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Generic Clock Generator Control 1 Synchronization Busy bits"] + #[inline(always)] + pub fn genctrl1(&self) -> GENCTRL1_R { + GENCTRL1_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Generic Clock Generator Control 2 Synchronization Busy bits"] + #[inline(always)] + pub fn genctrl2(&self) -> GENCTRL2_R { + GENCTRL2_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Generic Clock Generator Control 3 Synchronization Busy bits"] + #[inline(always)] + pub fn genctrl3(&self) -> GENCTRL3_R { + GENCTRL3_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Generic Clock Generator Control 4 Synchronization Busy bits"] + #[inline(always)] + pub fn genctrl4(&self) -> GENCTRL4_R { + GENCTRL4_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Generic Clock Generator Control 5 Synchronization Busy bits"] + #[inline(always)] + pub fn genctrl5(&self) -> GENCTRL5_R { + GENCTRL5_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Generic Clock Generator Control 6 Synchronization Busy bits"] + #[inline(always)] + pub fn genctrl6(&self) -> GENCTRL6_R { + GENCTRL6_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Generic Clock Generator Control 7 Synchronization Busy bits"] + #[inline(always)] + pub fn genctrl7(&self) -> GENCTRL7_R { + GENCTRL7_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Generic Clock Generator Control 8 Synchronization Busy bits"] + #[inline(always)] + pub fn genctrl8(&self) -> GENCTRL8_R { + GENCTRL8_R::new(((self.bits >> 10) & 0x01) != 0) + } +} +#[doc = "Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/generic.rs b/pac/atsamc20e/src/generic.rs new file mode 100644 index 000000000000..76159643acfa --- /dev/null +++ b/pac/atsamc20e/src/generic.rs @@ -0,0 +1,260 @@ +use core::marker; +#[doc = " Raw register type"] +pub trait RegisterSpec { + #[doc = " Raw register type (`u8`, `u16`, `u32`, ...)."] + type Ux: Copy; +} +#[doc = " Trait implemented by readable registers to enable the `read` method."] +#[doc = ""] +#[doc = " Registers marked with `Writable` can be also `modify`'ed."] +pub trait Readable: RegisterSpec { + #[doc = " Result from a call to `read` and argument to `modify`."] + type Reader: From> + core::ops::Deref>; +} +#[doc = " Trait implemented by writeable registers."] +#[doc = ""] +#[doc = " This enables the `write`, `write_with_zero` and `reset` methods."] +#[doc = ""] +#[doc = " Registers marked with `Readable` can be also `modify`'ed."] +pub trait Writable: RegisterSpec { + #[doc = " Writer type argument to `write`, et al."] + type Writer: From> + core::ops::DerefMut>; +} +#[doc = " Reset value of the register."] +#[doc = ""] +#[doc = " This value is the initial value for the `write` method. It can also be directly written to the"] +#[doc = " register by using the `reset` method."] +pub trait Resettable: RegisterSpec { + #[doc = " Reset value of the register."] + fn reset_value() -> Self::Ux; +} +#[doc = " This structure provides volatile access to registers."] +#[repr(transparent)] +pub struct Reg { + register: vcell::VolatileCell, + _marker: marker::PhantomData, +} +unsafe impl Send for Reg where REG::Ux: Send {} +impl Reg { + #[doc = " Returns the underlying memory address of register."] + #[doc = ""] + #[doc = " ```ignore"] + #[doc = " let reg_ptr = periph.reg.as_ptr();"] + #[doc = " ```"] + #[inline(always)] + pub fn as_ptr(&self) -> *mut REG::Ux { + self.register.as_ptr() + } +} +impl Reg { + #[doc = " Reads the contents of a `Readable` register."] + #[doc = ""] + #[doc = " You can read the raw contents of a register by using `bits`:"] + #[doc = " ```ignore"] + #[doc = " let bits = periph.reg.read().bits();"] + #[doc = " ```"] + #[doc = " or get the content of a particular field of a register:"] + #[doc = " ```ignore"] + #[doc = " let reader = periph.reg.read();"] + #[doc = " let bits = reader.field1().bits();"] + #[doc = " let flag = reader.field2().bit_is_set();"] + #[doc = " ```"] + #[inline(always)] + pub fn read(&self) -> REG::Reader { + REG::Reader::from(R { + bits: self.register.get(), + _reg: marker::PhantomData, + }) + } +} +impl Reg { + #[doc = " Writes the reset value to `Writable` register."] + #[doc = ""] + #[doc = " Resets the register to its initial state."] + #[inline(always)] + pub fn reset(&self) { + self.register.set(REG::reset_value()) + } + #[doc = " Writes bits to a `Writable` register."] + #[doc = ""] + #[doc = " You can write raw bits into a register:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.write(|w| unsafe { w.bits(rawbits) });"] + #[doc = " ```"] + #[doc = " or write only the fields you need:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.write(|w| w"] + #[doc = " .field1().bits(newfield1bits)"] + #[doc = " .field2().set_bit()"] + #[doc = " .field3().variant(VARIANT)"] + #[doc = " );"] + #[doc = " ```"] + #[doc = " In the latter case, other fields will be set to their reset value."] + #[inline(always)] + pub fn write(&self, f: F) + where + F: FnOnce(&mut REG::Writer) -> &mut W, + { + self.register.set( + f(&mut REG::Writer::from(W { + bits: REG::reset_value(), + _reg: marker::PhantomData, + })) + .bits, + ); + } +} +impl Reg +where + REG::Ux: Default, +{ + #[doc = " Writes 0 to a `Writable` register."] + #[doc = ""] + #[doc = " Similar to `write`, but unused bits will contain 0."] + #[inline(always)] + pub unsafe fn write_with_zero(&self, f: F) + where + F: FnOnce(&mut REG::Writer) -> &mut W, + { + self.register.set( + (*f(&mut REG::Writer::from(W { + bits: REG::Ux::default(), + _reg: marker::PhantomData, + }))) + .bits, + ); + } +} +impl Reg { + #[doc = " Modifies the contents of the register by reading and then writing it."] + #[doc = ""] + #[doc = " E.g. to do a read-modify-write sequence to change parts of a register:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.modify(|r, w| unsafe { w.bits("] + #[doc = " r.bits() | 3"] + #[doc = " ) });"] + #[doc = " ```"] + #[doc = " or"] + #[doc = " ```ignore"] + #[doc = " periph.reg.modify(|_, w| w"] + #[doc = " .field1().bits(newfield1bits)"] + #[doc = " .field2().set_bit()"] + #[doc = " .field3().variant(VARIANT)"] + #[doc = " );"] + #[doc = " ```"] + #[doc = " Other fields will have the value they had before the call to `modify`."] + #[inline(always)] + pub fn modify(&self, f: F) + where + for<'w> F: FnOnce(®::Reader, &'w mut REG::Writer) -> &'w mut W, + { + let bits = self.register.get(); + self.register.set( + f( + ®::Reader::from(R { + bits, + _reg: marker::PhantomData, + }), + &mut REG::Writer::from(W { + bits, + _reg: marker::PhantomData, + }), + ) + .bits, + ); + } +} +#[doc = " Register reader."] +#[doc = ""] +#[doc = " Result of the `read` methods of registers. Also used as a closure argument in the `modify`"] +#[doc = " method."] +pub struct R { + pub(crate) bits: REG::Ux, + _reg: marker::PhantomData, +} +impl R { + #[doc = " Reads raw bits from register."] + #[inline(always)] + pub fn bits(&self) -> REG::Ux { + self.bits + } +} +impl PartialEq for R +where + REG::Ux: PartialEq, + FI: Copy + Into, +{ + #[inline(always)] + fn eq(&self, other: &FI) -> bool { + self.bits.eq(&(*other).into()) + } +} +#[doc = " Register writer."] +#[doc = ""] +#[doc = " Used as an argument to the closures in the `write` and `modify` methods of the register."] +pub struct W { + #[doc = "Writable bits"] + pub(crate) bits: REG::Ux, + _reg: marker::PhantomData, +} +impl W { + #[doc = " Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = " Field reader."] +#[doc = ""] +#[doc = " Result of the `read` methods of fields."] +pub struct FieldReader { + pub(crate) bits: U, + _reg: marker::PhantomData, +} +impl FieldReader +where + U: Copy, +{ + #[doc = " Creates a new instance of the reader."] + #[allow(unused)] + #[inline(always)] + pub(crate) fn new(bits: U) -> Self { + Self { + bits, + _reg: marker::PhantomData, + } + } + #[doc = " Reads raw bits from field."] + #[inline(always)] + pub fn bits(&self) -> U { + self.bits + } +} +impl PartialEq for FieldReader +where + U: PartialEq, + FI: Copy + Into, +{ + #[inline(always)] + fn eq(&self, other: &FI) -> bool { + self.bits.eq(&(*other).into()) + } +} +impl FieldReader { + #[doc = " Value of the field as raw bits."] + #[inline(always)] + pub fn bit(&self) -> bool { + self.bits + } + #[doc = " Returns `true` if the bit is clear (0)."] + #[inline(always)] + pub fn bit_is_clear(&self) -> bool { + !self.bit() + } + #[doc = " Returns `true` if the bit is set (1)."] + #[inline(always)] + pub fn bit_is_set(&self) -> bool { + self.bit() + } +} diff --git a/pac/atsamc20e/src/hmatrixhs.rs b/pac/atsamc20e/src/hmatrixhs.rs new file mode 100644 index 000000000000..c8129ac89b6f --- /dev/null +++ b/pac/atsamc20e/src/hmatrixhs.rs @@ -0,0 +1,43 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00..0x40 - Master Configuration"] + pub mcfg: [crate::Reg; 16], + #[doc = "0x40..0x80 - Slave Configuration"] + pub scfg: [crate::Reg; 16], + #[doc = "0x80..0xa0 - PRS\\[%s\\]"] + pub prs: [PRS; 4], + _reserved3: [u8; 0x60], + #[doc = "0x100 - Master Remap Control"] + pub mrcr: crate::Reg, + _reserved4: [u8; 0x0c], + #[doc = "0x110..0x150 - Special Function"] + pub sfr: [crate::Reg; 16], +} +#[doc = r"Register block"] +#[repr(C)] +pub struct PRS { + #[doc = "0x00 - Priority A for Slave"] + pub pras: crate::Reg, + #[doc = "0x04 - Priority B for Slave"] + pub prbs: crate::Reg, +} +#[doc = r"Register block"] +#[doc = "PRS\\[%s\\]"] +pub mod prs; +#[doc = "MCFG register accessor: an alias for `Reg`"] +pub type MCFG = crate::Reg; +#[doc = "Master Configuration"] +pub mod mcfg; +#[doc = "SCFG register accessor: an alias for `Reg`"] +pub type SCFG = crate::Reg; +#[doc = "Slave Configuration"] +pub mod scfg; +#[doc = "MRCR register accessor: an alias for `Reg`"] +pub type MRCR = crate::Reg; +#[doc = "Master Remap Control"] +pub mod mrcr; +#[doc = "SFR register accessor: an alias for `Reg`"] +pub type SFR = crate::Reg; +#[doc = "Special Function"] +pub mod sfr; diff --git a/pac/atsamc20e/src/hmatrixhs/mcfg.rs b/pac/atsamc20e/src/hmatrixhs/mcfg.rs new file mode 100644 index 000000000000..454a39fabe13 --- /dev/null +++ b/pac/atsamc20e/src/hmatrixhs/mcfg.rs @@ -0,0 +1,192 @@ +#[doc = "Register `MCFG[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MCFG[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Undefined Length Burst Type\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum ULBT_A { + #[doc = "0: Infinite Length"] + INFINITE = 0, + #[doc = "1: Single Access"] + SINGLE = 1, + #[doc = "2: Four Beat Burst"] + FOUR_BEAT = 2, + #[doc = "3: Eight Beat Burst"] + EIGHT_BEAT = 3, + #[doc = "4: Sixteen Beat Burst"] + SIXTEEN_BEAT = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: ULBT_A) -> Self { + variant as _ + } +} +#[doc = "Field `ULBT` reader - Undefined Length Burst Type"] +pub struct ULBT_R(crate::FieldReader); +impl ULBT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ULBT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(ULBT_A::INFINITE), + 1 => Some(ULBT_A::SINGLE), + 2 => Some(ULBT_A::FOUR_BEAT), + 3 => Some(ULBT_A::EIGHT_BEAT), + 4 => Some(ULBT_A::SIXTEEN_BEAT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `INFINITE`"] + #[inline(always)] + pub fn is_infinite(&self) -> bool { + **self == ULBT_A::INFINITE + } + #[doc = "Checks if the value of the field is `SINGLE`"] + #[inline(always)] + pub fn is_single(&self) -> bool { + **self == ULBT_A::SINGLE + } + #[doc = "Checks if the value of the field is `FOUR_BEAT`"] + #[inline(always)] + pub fn is_four_beat(&self) -> bool { + **self == ULBT_A::FOUR_BEAT + } + #[doc = "Checks if the value of the field is `EIGHT_BEAT`"] + #[inline(always)] + pub fn is_eight_beat(&self) -> bool { + **self == ULBT_A::EIGHT_BEAT + } + #[doc = "Checks if the value of the field is `SIXTEEN_BEAT`"] + #[inline(always)] + pub fn is_sixteen_beat(&self) -> bool { + **self == ULBT_A::SIXTEEN_BEAT + } +} +impl core::ops::Deref for ULBT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ULBT` writer - Undefined Length Burst Type"] +pub struct ULBT_W<'a> { + w: &'a mut W, +} +impl<'a> ULBT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: ULBT_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Infinite Length"] + #[inline(always)] + pub fn infinite(self) -> &'a mut W { + self.variant(ULBT_A::INFINITE) + } + #[doc = "Single Access"] + #[inline(always)] + pub fn single(self) -> &'a mut W { + self.variant(ULBT_A::SINGLE) + } + #[doc = "Four Beat Burst"] + #[inline(always)] + pub fn four_beat(self) -> &'a mut W { + self.variant(ULBT_A::FOUR_BEAT) + } + #[doc = "Eight Beat Burst"] + #[inline(always)] + pub fn eight_beat(self) -> &'a mut W { + self.variant(ULBT_A::EIGHT_BEAT) + } + #[doc = "Sixteen Beat Burst"] + #[inline(always)] + pub fn sixteen_beat(self) -> &'a mut W { + self.variant(ULBT_A::SIXTEEN_BEAT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Undefined Length Burst Type"] + #[inline(always)] + pub fn ulbt(&self) -> ULBT_R { + ULBT_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Undefined Length Burst Type"] + #[inline(always)] + pub fn ulbt(&mut self) -> ULBT_W { + ULBT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Master Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mcfg](index.html) module"] +pub struct MCFG_SPEC; +impl crate::RegisterSpec for MCFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [mcfg::R](R) reader structure"] +impl crate::Readable for MCFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [mcfg::W](W) writer structure"] +impl crate::Writable for MCFG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets MCFG[%s] +to value 0x02"] +impl crate::Resettable for MCFG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x02 + } +} diff --git a/pac/atsamc20e/src/hmatrixhs/mrcr.rs b/pac/atsamc20e/src/hmatrixhs/mrcr.rs new file mode 100644 index 000000000000..0cf2a1fb01be --- /dev/null +++ b/pac/atsamc20e/src/hmatrixhs/mrcr.rs @@ -0,0 +1,1570 @@ +#[doc = "Register `MRCR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MRCR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Remap Command Bit for Master 0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB0_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB0_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB0` reader - Remap Command Bit for Master 0"] +pub struct RCB0_R(crate::FieldReader); +impl RCB0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB0_A { + match self.bits { + false => RCB0_A::DIS, + true => RCB0_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB0_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB0_A::ENA + } +} +impl core::ops::Deref for RCB0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB0` writer - Remap Command Bit for Master 0"] +pub struct RCB0_W<'a> { + w: &'a mut W, +} +impl<'a> RCB0_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB0_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB0_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB0_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Remap Command Bit for Master 1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB1_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB1_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB1` reader - Remap Command Bit for Master 1"] +pub struct RCB1_R(crate::FieldReader); +impl RCB1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB1_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB1_A { + match self.bits { + false => RCB1_A::DIS, + true => RCB1_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB1_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB1_A::ENA + } +} +impl core::ops::Deref for RCB1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB1` writer - Remap Command Bit for Master 1"] +pub struct RCB1_W<'a> { + w: &'a mut W, +} +impl<'a> RCB1_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB1_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB1_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB1_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Remap Command Bit for Master 2\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB2_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB2_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB2` reader - Remap Command Bit for Master 2"] +pub struct RCB2_R(crate::FieldReader); +impl RCB2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB2_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB2_A { + match self.bits { + false => RCB2_A::DIS, + true => RCB2_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB2_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB2_A::ENA + } +} +impl core::ops::Deref for RCB2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB2` writer - Remap Command Bit for Master 2"] +pub struct RCB2_W<'a> { + w: &'a mut W, +} +impl<'a> RCB2_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB2_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB2_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB2_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Remap Command Bit for Master 3\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB3_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB3_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB3` reader - Remap Command Bit for Master 3"] +pub struct RCB3_R(crate::FieldReader); +impl RCB3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB3_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB3_A { + match self.bits { + false => RCB3_A::DIS, + true => RCB3_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB3_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB3_A::ENA + } +} +impl core::ops::Deref for RCB3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB3` writer - Remap Command Bit for Master 3"] +pub struct RCB3_W<'a> { + w: &'a mut W, +} +impl<'a> RCB3_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB3_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB3_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB3_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Remap Command Bit for Master 4\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB4_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB4_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB4` reader - Remap Command Bit for Master 4"] +pub struct RCB4_R(crate::FieldReader); +impl RCB4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB4_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB4_A { + match self.bits { + false => RCB4_A::DIS, + true => RCB4_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB4_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB4_A::ENA + } +} +impl core::ops::Deref for RCB4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB4` writer - Remap Command Bit for Master 4"] +pub struct RCB4_W<'a> { + w: &'a mut W, +} +impl<'a> RCB4_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB4_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB4_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB4_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Remap Command Bit for Master 5\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB5_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB5_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB5` reader - Remap Command Bit for Master 5"] +pub struct RCB5_R(crate::FieldReader); +impl RCB5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB5_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB5_A { + match self.bits { + false => RCB5_A::DIS, + true => RCB5_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB5_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB5_A::ENA + } +} +impl core::ops::Deref for RCB5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB5` writer - Remap Command Bit for Master 5"] +pub struct RCB5_W<'a> { + w: &'a mut W, +} +impl<'a> RCB5_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB5_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB5_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB5_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Remap Command Bit for Master 6\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB6_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB6_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB6` reader - Remap Command Bit for Master 6"] +pub struct RCB6_R(crate::FieldReader); +impl RCB6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB6_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB6_A { + match self.bits { + false => RCB6_A::DIS, + true => RCB6_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB6_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB6_A::ENA + } +} +impl core::ops::Deref for RCB6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB6` writer - Remap Command Bit for Master 6"] +pub struct RCB6_W<'a> { + w: &'a mut W, +} +impl<'a> RCB6_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB6_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB6_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB6_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Remap Command Bit for Master 7\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB7_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB7_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB7` reader - Remap Command Bit for Master 7"] +pub struct RCB7_R(crate::FieldReader); +impl RCB7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB7_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB7_A { + match self.bits { + false => RCB7_A::DIS, + true => RCB7_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB7_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB7_A::ENA + } +} +impl core::ops::Deref for RCB7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB7` writer - Remap Command Bit for Master 7"] +pub struct RCB7_W<'a> { + w: &'a mut W, +} +impl<'a> RCB7_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB7_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB7_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB7_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Remap Command Bit for Master 8\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB8_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB8_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB8` reader - Remap Command Bit for Master 8"] +pub struct RCB8_R(crate::FieldReader); +impl RCB8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB8_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB8_A { + match self.bits { + false => RCB8_A::DIS, + true => RCB8_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB8_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB8_A::ENA + } +} +impl core::ops::Deref for RCB8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB8` writer - Remap Command Bit for Master 8"] +pub struct RCB8_W<'a> { + w: &'a mut W, +} +impl<'a> RCB8_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB8_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB8_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB8_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Remap Command Bit for Master 9\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB9_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB9_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB9` reader - Remap Command Bit for Master 9"] +pub struct RCB9_R(crate::FieldReader); +impl RCB9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB9_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB9_A { + match self.bits { + false => RCB9_A::DIS, + true => RCB9_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB9_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB9_A::ENA + } +} +impl core::ops::Deref for RCB9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB9` writer - Remap Command Bit for Master 9"] +pub struct RCB9_W<'a> { + w: &'a mut W, +} +impl<'a> RCB9_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB9_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB9_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB9_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Remap Command Bit for Master 10\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB10_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB10_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB10` reader - Remap Command Bit for Master 10"] +pub struct RCB10_R(crate::FieldReader); +impl RCB10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB10_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB10_A { + match self.bits { + false => RCB10_A::DIS, + true => RCB10_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB10_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB10_A::ENA + } +} +impl core::ops::Deref for RCB10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB10` writer - Remap Command Bit for Master 10"] +pub struct RCB10_W<'a> { + w: &'a mut W, +} +impl<'a> RCB10_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB10_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB10_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB10_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Remap Command Bit for Master 11\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB11_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB11_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB11` reader - Remap Command Bit for Master 11"] +pub struct RCB11_R(crate::FieldReader); +impl RCB11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB11_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB11_A { + match self.bits { + false => RCB11_A::DIS, + true => RCB11_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB11_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB11_A::ENA + } +} +impl core::ops::Deref for RCB11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB11` writer - Remap Command Bit for Master 11"] +pub struct RCB11_W<'a> { + w: &'a mut W, +} +impl<'a> RCB11_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB11_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB11_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB11_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Remap Command Bit for Master 12\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB12_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB12_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB12` reader - Remap Command Bit for Master 12"] +pub struct RCB12_R(crate::FieldReader); +impl RCB12_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB12_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB12_A { + match self.bits { + false => RCB12_A::DIS, + true => RCB12_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB12_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB12_A::ENA + } +} +impl core::ops::Deref for RCB12_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB12` writer - Remap Command Bit for Master 12"] +pub struct RCB12_W<'a> { + w: &'a mut W, +} +impl<'a> RCB12_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB12_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB12_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB12_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Remap Command Bit for Master 13\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB13_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB13_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB13` reader - Remap Command Bit for Master 13"] +pub struct RCB13_R(crate::FieldReader); +impl RCB13_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB13_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB13_A { + match self.bits { + false => RCB13_A::DIS, + true => RCB13_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB13_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB13_A::ENA + } +} +impl core::ops::Deref for RCB13_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB13` writer - Remap Command Bit for Master 13"] +pub struct RCB13_W<'a> { + w: &'a mut W, +} +impl<'a> RCB13_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB13_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB13_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB13_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Remap Command Bit for Master 14\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB14_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB14_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB14` reader - Remap Command Bit for Master 14"] +pub struct RCB14_R(crate::FieldReader); +impl RCB14_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB14_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB14_A { + match self.bits { + false => RCB14_A::DIS, + true => RCB14_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB14_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB14_A::ENA + } +} +impl core::ops::Deref for RCB14_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB14` writer - Remap Command Bit for Master 14"] +pub struct RCB14_W<'a> { + w: &'a mut W, +} +impl<'a> RCB14_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB14_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB14_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB14_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Remap Command Bit for Master 15\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB15_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB15_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB15` reader - Remap Command Bit for Master 15"] +pub struct RCB15_R(crate::FieldReader); +impl RCB15_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB15_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB15_A { + match self.bits { + false => RCB15_A::DIS, + true => RCB15_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB15_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB15_A::ENA + } +} +impl core::ops::Deref for RCB15_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB15` writer - Remap Command Bit for Master 15"] +pub struct RCB15_W<'a> { + w: &'a mut W, +} +impl<'a> RCB15_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB15_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB15_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB15_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Remap Command Bit for Master 0"] + #[inline(always)] + pub fn rcb0(&self) -> RCB0_R { + RCB0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Remap Command Bit for Master 1"] + #[inline(always)] + pub fn rcb1(&self) -> RCB1_R { + RCB1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Remap Command Bit for Master 2"] + #[inline(always)] + pub fn rcb2(&self) -> RCB2_R { + RCB2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Remap Command Bit for Master 3"] + #[inline(always)] + pub fn rcb3(&self) -> RCB3_R { + RCB3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Remap Command Bit for Master 4"] + #[inline(always)] + pub fn rcb4(&self) -> RCB4_R { + RCB4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Remap Command Bit for Master 5"] + #[inline(always)] + pub fn rcb5(&self) -> RCB5_R { + RCB5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Remap Command Bit for Master 6"] + #[inline(always)] + pub fn rcb6(&self) -> RCB6_R { + RCB6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Remap Command Bit for Master 7"] + #[inline(always)] + pub fn rcb7(&self) -> RCB7_R { + RCB7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Remap Command Bit for Master 8"] + #[inline(always)] + pub fn rcb8(&self) -> RCB8_R { + RCB8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Remap Command Bit for Master 9"] + #[inline(always)] + pub fn rcb9(&self) -> RCB9_R { + RCB9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Remap Command Bit for Master 10"] + #[inline(always)] + pub fn rcb10(&self) -> RCB10_R { + RCB10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Remap Command Bit for Master 11"] + #[inline(always)] + pub fn rcb11(&self) -> RCB11_R { + RCB11_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Remap Command Bit for Master 12"] + #[inline(always)] + pub fn rcb12(&self) -> RCB12_R { + RCB12_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Remap Command Bit for Master 13"] + #[inline(always)] + pub fn rcb13(&self) -> RCB13_R { + RCB13_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Remap Command Bit for Master 14"] + #[inline(always)] + pub fn rcb14(&self) -> RCB14_R { + RCB14_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Remap Command Bit for Master 15"] + #[inline(always)] + pub fn rcb15(&self) -> RCB15_R { + RCB15_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Remap Command Bit for Master 0"] + #[inline(always)] + pub fn rcb0(&mut self) -> RCB0_W { + RCB0_W { w: self } + } + #[doc = "Bit 1 - Remap Command Bit for Master 1"] + #[inline(always)] + pub fn rcb1(&mut self) -> RCB1_W { + RCB1_W { w: self } + } + #[doc = "Bit 2 - Remap Command Bit for Master 2"] + #[inline(always)] + pub fn rcb2(&mut self) -> RCB2_W { + RCB2_W { w: self } + } + #[doc = "Bit 3 - Remap Command Bit for Master 3"] + #[inline(always)] + pub fn rcb3(&mut self) -> RCB3_W { + RCB3_W { w: self } + } + #[doc = "Bit 4 - Remap Command Bit for Master 4"] + #[inline(always)] + pub fn rcb4(&mut self) -> RCB4_W { + RCB4_W { w: self } + } + #[doc = "Bit 5 - Remap Command Bit for Master 5"] + #[inline(always)] + pub fn rcb5(&mut self) -> RCB5_W { + RCB5_W { w: self } + } + #[doc = "Bit 6 - Remap Command Bit for Master 6"] + #[inline(always)] + pub fn rcb6(&mut self) -> RCB6_W { + RCB6_W { w: self } + } + #[doc = "Bit 7 - Remap Command Bit for Master 7"] + #[inline(always)] + pub fn rcb7(&mut self) -> RCB7_W { + RCB7_W { w: self } + } + #[doc = "Bit 8 - Remap Command Bit for Master 8"] + #[inline(always)] + pub fn rcb8(&mut self) -> RCB8_W { + RCB8_W { w: self } + } + #[doc = "Bit 9 - Remap Command Bit for Master 9"] + #[inline(always)] + pub fn rcb9(&mut self) -> RCB9_W { + RCB9_W { w: self } + } + #[doc = "Bit 10 - Remap Command Bit for Master 10"] + #[inline(always)] + pub fn rcb10(&mut self) -> RCB10_W { + RCB10_W { w: self } + } + #[doc = "Bit 11 - Remap Command Bit for Master 11"] + #[inline(always)] + pub fn rcb11(&mut self) -> RCB11_W { + RCB11_W { w: self } + } + #[doc = "Bit 12 - Remap Command Bit for Master 12"] + #[inline(always)] + pub fn rcb12(&mut self) -> RCB12_W { + RCB12_W { w: self } + } + #[doc = "Bit 13 - Remap Command Bit for Master 13"] + #[inline(always)] + pub fn rcb13(&mut self) -> RCB13_W { + RCB13_W { w: self } + } + #[doc = "Bit 14 - Remap Command Bit for Master 14"] + #[inline(always)] + pub fn rcb14(&mut self) -> RCB14_W { + RCB14_W { w: self } + } + #[doc = "Bit 15 - Remap Command Bit for Master 15"] + #[inline(always)] + pub fn rcb15(&mut self) -> RCB15_W { + RCB15_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Master Remap Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mrcr](index.html) module"] +pub struct MRCR_SPEC; +impl crate::RegisterSpec for MRCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [mrcr::R](R) reader structure"] +impl crate::Readable for MRCR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [mrcr::W](W) writer structure"] +impl crate::Writable for MRCR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets MRCR to value 0"] +impl crate::Resettable for MRCR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/hmatrixhs/prs.rs b/pac/atsamc20e/src/hmatrixhs/prs.rs new file mode 100644 index 000000000000..0313f3c4fc20 --- /dev/null +++ b/pac/atsamc20e/src/hmatrixhs/prs.rs @@ -0,0 +1,8 @@ +#[doc = "PRAS register accessor: an alias for `Reg`"] +pub type PRAS = crate::Reg; +#[doc = "Priority A for Slave"] +pub mod pras; +#[doc = "PRBS register accessor: an alias for `Reg`"] +pub type PRBS = crate::Reg; +#[doc = "Priority B for Slave"] +pub mod prbs; diff --git a/pac/atsamc20e/src/hmatrixhs/prs/pras.rs b/pac/atsamc20e/src/hmatrixhs/prs/pras.rs new file mode 100644 index 000000000000..ac4744a9e2a0 --- /dev/null +++ b/pac/atsamc20e/src/hmatrixhs/prs/pras.rs @@ -0,0 +1,362 @@ +#[doc = "Register `PRAS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PRAS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `M0PR` reader - Master 0 Priority"] +pub struct M0PR_R(crate::FieldReader); +impl M0PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M0PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M0PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M0PR` writer - Master 0 Priority"] +pub struct M0PR_W<'a> { + w: &'a mut W, +} +impl<'a> M0PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Field `M1PR` reader - Master 1 Priority"] +pub struct M1PR_R(crate::FieldReader); +impl M1PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M1PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M1PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M1PR` writer - Master 1 Priority"] +pub struct M1PR_W<'a> { + w: &'a mut W, +} +impl<'a> M1PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 4)) | ((value as u32 & 0x0f) << 4); + self.w + } +} +#[doc = "Field `M2PR` reader - Master 2 Priority"] +pub struct M2PR_R(crate::FieldReader); +impl M2PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M2PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M2PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M2PR` writer - Master 2 Priority"] +pub struct M2PR_W<'a> { + w: &'a mut W, +} +impl<'a> M2PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 8)) | ((value as u32 & 0x0f) << 8); + self.w + } +} +#[doc = "Field `M3PR` reader - Master 3 Priority"] +pub struct M3PR_R(crate::FieldReader); +impl M3PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M3PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M3PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M3PR` writer - Master 3 Priority"] +pub struct M3PR_W<'a> { + w: &'a mut W, +} +impl<'a> M3PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 12)) | ((value as u32 & 0x0f) << 12); + self.w + } +} +#[doc = "Field `M4PR` reader - Master 4 Priority"] +pub struct M4PR_R(crate::FieldReader); +impl M4PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M4PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M4PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M4PR` writer - Master 4 Priority"] +pub struct M4PR_W<'a> { + w: &'a mut W, +} +impl<'a> M4PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 16)) | ((value as u32 & 0x0f) << 16); + self.w + } +} +#[doc = "Field `M5PR` reader - Master 5 Priority"] +pub struct M5PR_R(crate::FieldReader); +impl M5PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M5PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M5PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M5PR` writer - Master 5 Priority"] +pub struct M5PR_W<'a> { + w: &'a mut W, +} +impl<'a> M5PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 20)) | ((value as u32 & 0x0f) << 20); + self.w + } +} +#[doc = "Field `M6PR` reader - Master 6 Priority"] +pub struct M6PR_R(crate::FieldReader); +impl M6PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M6PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M6PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M6PR` writer - Master 6 Priority"] +pub struct M6PR_W<'a> { + w: &'a mut W, +} +impl<'a> M6PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Field `M7PR` reader - Master 7 Priority"] +pub struct M7PR_R(crate::FieldReader); +impl M7PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M7PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M7PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M7PR` writer - Master 7 Priority"] +pub struct M7PR_W<'a> { + w: &'a mut W, +} +impl<'a> M7PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 28)) | ((value as u32 & 0x0f) << 28); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Master 0 Priority"] + #[inline(always)] + pub fn m0pr(&self) -> M0PR_R { + M0PR_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Master 1 Priority"] + #[inline(always)] + pub fn m1pr(&self) -> M1PR_R { + M1PR_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 8:11 - Master 2 Priority"] + #[inline(always)] + pub fn m2pr(&self) -> M2PR_R { + M2PR_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - Master 3 Priority"] + #[inline(always)] + pub fn m3pr(&self) -> M3PR_R { + M3PR_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:19 - Master 4 Priority"] + #[inline(always)] + pub fn m4pr(&self) -> M4PR_R { + M4PR_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bits 20:23 - Master 5 Priority"] + #[inline(always)] + pub fn m5pr(&self) -> M5PR_R { + M5PR_R::new(((self.bits >> 20) & 0x0f) as u8) + } + #[doc = "Bits 24:27 - Master 6 Priority"] + #[inline(always)] + pub fn m6pr(&self) -> M6PR_R { + M6PR_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bits 28:31 - Master 7 Priority"] + #[inline(always)] + pub fn m7pr(&self) -> M7PR_R { + M7PR_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Master 0 Priority"] + #[inline(always)] + pub fn m0pr(&mut self) -> M0PR_W { + M0PR_W { w: self } + } + #[doc = "Bits 4:7 - Master 1 Priority"] + #[inline(always)] + pub fn m1pr(&mut self) -> M1PR_W { + M1PR_W { w: self } + } + #[doc = "Bits 8:11 - Master 2 Priority"] + #[inline(always)] + pub fn m2pr(&mut self) -> M2PR_W { + M2PR_W { w: self } + } + #[doc = "Bits 12:15 - Master 3 Priority"] + #[inline(always)] + pub fn m3pr(&mut self) -> M3PR_W { + M3PR_W { w: self } + } + #[doc = "Bits 16:19 - Master 4 Priority"] + #[inline(always)] + pub fn m4pr(&mut self) -> M4PR_W { + M4PR_W { w: self } + } + #[doc = "Bits 20:23 - Master 5 Priority"] + #[inline(always)] + pub fn m5pr(&mut self) -> M5PR_W { + M5PR_W { w: self } + } + #[doc = "Bits 24:27 - Master 6 Priority"] + #[inline(always)] + pub fn m6pr(&mut self) -> M6PR_W { + M6PR_W { w: self } + } + #[doc = "Bits 28:31 - Master 7 Priority"] + #[inline(always)] + pub fn m7pr(&mut self) -> M7PR_W { + M7PR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Priority A for Slave\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pras](index.html) module"] +pub struct PRAS_SPEC; +impl crate::RegisterSpec for PRAS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pras::R](R) reader structure"] +impl crate::Readable for PRAS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [pras::W](W) writer structure"] +impl crate::Writable for PRAS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PRAS to value 0"] +impl crate::Resettable for PRAS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/hmatrixhs/prs/prbs.rs b/pac/atsamc20e/src/hmatrixhs/prs/prbs.rs new file mode 100644 index 000000000000..a2cc6bb9f6b0 --- /dev/null +++ b/pac/atsamc20e/src/hmatrixhs/prs/prbs.rs @@ -0,0 +1,362 @@ +#[doc = "Register `PRBS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PRBS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `M8PR` reader - Master 8 Priority"] +pub struct M8PR_R(crate::FieldReader); +impl M8PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M8PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M8PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M8PR` writer - Master 8 Priority"] +pub struct M8PR_W<'a> { + w: &'a mut W, +} +impl<'a> M8PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Field `M9PR` reader - Master 9 Priority"] +pub struct M9PR_R(crate::FieldReader); +impl M9PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M9PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M9PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M9PR` writer - Master 9 Priority"] +pub struct M9PR_W<'a> { + w: &'a mut W, +} +impl<'a> M9PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 4)) | ((value as u32 & 0x0f) << 4); + self.w + } +} +#[doc = "Field `M10PR` reader - Master 10 Priority"] +pub struct M10PR_R(crate::FieldReader); +impl M10PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M10PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M10PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M10PR` writer - Master 10 Priority"] +pub struct M10PR_W<'a> { + w: &'a mut W, +} +impl<'a> M10PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 8)) | ((value as u32 & 0x0f) << 8); + self.w + } +} +#[doc = "Field `M11PR` reader - Master 11 Priority"] +pub struct M11PR_R(crate::FieldReader); +impl M11PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M11PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M11PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M11PR` writer - Master 11 Priority"] +pub struct M11PR_W<'a> { + w: &'a mut W, +} +impl<'a> M11PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 12)) | ((value as u32 & 0x0f) << 12); + self.w + } +} +#[doc = "Field `M12PR` reader - Master 12 Priority"] +pub struct M12PR_R(crate::FieldReader); +impl M12PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M12PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M12PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M12PR` writer - Master 12 Priority"] +pub struct M12PR_W<'a> { + w: &'a mut W, +} +impl<'a> M12PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 16)) | ((value as u32 & 0x0f) << 16); + self.w + } +} +#[doc = "Field `M13PR` reader - Master 13 Priority"] +pub struct M13PR_R(crate::FieldReader); +impl M13PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M13PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M13PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M13PR` writer - Master 13 Priority"] +pub struct M13PR_W<'a> { + w: &'a mut W, +} +impl<'a> M13PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 20)) | ((value as u32 & 0x0f) << 20); + self.w + } +} +#[doc = "Field `M14PR` reader - Master 14 Priority"] +pub struct M14PR_R(crate::FieldReader); +impl M14PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M14PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M14PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M14PR` writer - Master 14 Priority"] +pub struct M14PR_W<'a> { + w: &'a mut W, +} +impl<'a> M14PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Field `M15PR` reader - Master 15 Priority"] +pub struct M15PR_R(crate::FieldReader); +impl M15PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M15PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M15PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M15PR` writer - Master 15 Priority"] +pub struct M15PR_W<'a> { + w: &'a mut W, +} +impl<'a> M15PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 28)) | ((value as u32 & 0x0f) << 28); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Master 8 Priority"] + #[inline(always)] + pub fn m8pr(&self) -> M8PR_R { + M8PR_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Master 9 Priority"] + #[inline(always)] + pub fn m9pr(&self) -> M9PR_R { + M9PR_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 8:11 - Master 10 Priority"] + #[inline(always)] + pub fn m10pr(&self) -> M10PR_R { + M10PR_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - Master 11 Priority"] + #[inline(always)] + pub fn m11pr(&self) -> M11PR_R { + M11PR_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:19 - Master 12 Priority"] + #[inline(always)] + pub fn m12pr(&self) -> M12PR_R { + M12PR_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bits 20:23 - Master 13 Priority"] + #[inline(always)] + pub fn m13pr(&self) -> M13PR_R { + M13PR_R::new(((self.bits >> 20) & 0x0f) as u8) + } + #[doc = "Bits 24:27 - Master 14 Priority"] + #[inline(always)] + pub fn m14pr(&self) -> M14PR_R { + M14PR_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bits 28:31 - Master 15 Priority"] + #[inline(always)] + pub fn m15pr(&self) -> M15PR_R { + M15PR_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Master 8 Priority"] + #[inline(always)] + pub fn m8pr(&mut self) -> M8PR_W { + M8PR_W { w: self } + } + #[doc = "Bits 4:7 - Master 9 Priority"] + #[inline(always)] + pub fn m9pr(&mut self) -> M9PR_W { + M9PR_W { w: self } + } + #[doc = "Bits 8:11 - Master 10 Priority"] + #[inline(always)] + pub fn m10pr(&mut self) -> M10PR_W { + M10PR_W { w: self } + } + #[doc = "Bits 12:15 - Master 11 Priority"] + #[inline(always)] + pub fn m11pr(&mut self) -> M11PR_W { + M11PR_W { w: self } + } + #[doc = "Bits 16:19 - Master 12 Priority"] + #[inline(always)] + pub fn m12pr(&mut self) -> M12PR_W { + M12PR_W { w: self } + } + #[doc = "Bits 20:23 - Master 13 Priority"] + #[inline(always)] + pub fn m13pr(&mut self) -> M13PR_W { + M13PR_W { w: self } + } + #[doc = "Bits 24:27 - Master 14 Priority"] + #[inline(always)] + pub fn m14pr(&mut self) -> M14PR_W { + M14PR_W { w: self } + } + #[doc = "Bits 28:31 - Master 15 Priority"] + #[inline(always)] + pub fn m15pr(&mut self) -> M15PR_W { + M15PR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Priority B for Slave\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [prbs](index.html) module"] +pub struct PRBS_SPEC; +impl crate::RegisterSpec for PRBS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [prbs::R](R) reader structure"] +impl crate::Readable for PRBS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [prbs::W](W) writer structure"] +impl crate::Writable for PRBS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PRBS to value 0"] +impl crate::Resettable for PRBS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/hmatrixhs/scfg.rs b/pac/atsamc20e/src/hmatrixhs/scfg.rs new file mode 100644 index 000000000000..7180c043195a --- /dev/null +++ b/pac/atsamc20e/src/hmatrixhs/scfg.rs @@ -0,0 +1,334 @@ +#[doc = "Register `SCFG[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SCFG[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SLOT_CYCLE` reader - Maximum Number of Allowed Cycles for a Burst"] +pub struct SLOT_CYCLE_R(crate::FieldReader); +impl SLOT_CYCLE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SLOT_CYCLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SLOT_CYCLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLOT_CYCLE` writer - Maximum Number of Allowed Cycles for a Burst"] +pub struct SLOT_CYCLE_W<'a> { + w: &'a mut W, +} +impl<'a> SLOT_CYCLE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +#[doc = "Default Master Type\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DEFMSTR_TYPE_A { + #[doc = "0: No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst."] + NO_DEFAULT = 0, + #[doc = "1: Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave."] + LAST_DEFAULT = 1, + #[doc = "2: Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave."] + FIXED_DEFAULT = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DEFMSTR_TYPE_A) -> Self { + variant as _ + } +} +#[doc = "Field `DEFMSTR_TYPE` reader - Default Master Type"] +pub struct DEFMSTR_TYPE_R(crate::FieldReader); +impl DEFMSTR_TYPE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DEFMSTR_TYPE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(DEFMSTR_TYPE_A::NO_DEFAULT), + 1 => Some(DEFMSTR_TYPE_A::LAST_DEFAULT), + 2 => Some(DEFMSTR_TYPE_A::FIXED_DEFAULT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NO_DEFAULT`"] + #[inline(always)] + pub fn is_no_default(&self) -> bool { + **self == DEFMSTR_TYPE_A::NO_DEFAULT + } + #[doc = "Checks if the value of the field is `LAST_DEFAULT`"] + #[inline(always)] + pub fn is_last_default(&self) -> bool { + **self == DEFMSTR_TYPE_A::LAST_DEFAULT + } + #[doc = "Checks if the value of the field is `FIXED_DEFAULT`"] + #[inline(always)] + pub fn is_fixed_default(&self) -> bool { + **self == DEFMSTR_TYPE_A::FIXED_DEFAULT + } +} +impl core::ops::Deref for DEFMSTR_TYPE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DEFMSTR_TYPE` writer - Default Master Type"] +pub struct DEFMSTR_TYPE_W<'a> { + w: &'a mut W, +} +impl<'a> DEFMSTR_TYPE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DEFMSTR_TYPE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst."] + #[inline(always)] + pub fn no_default(self) -> &'a mut W { + self.variant(DEFMSTR_TYPE_A::NO_DEFAULT) + } + #[doc = "Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave."] + #[inline(always)] + pub fn last_default(self) -> &'a mut W { + self.variant(DEFMSTR_TYPE_A::LAST_DEFAULT) + } + #[doc = "Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave."] + #[inline(always)] + pub fn fixed_default(self) -> &'a mut W { + self.variant(DEFMSTR_TYPE_A::FIXED_DEFAULT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Field `FIXED_DEFMSTR` reader - Fixed Index of Default Master"] +pub struct FIXED_DEFMSTR_R(crate::FieldReader); +impl FIXED_DEFMSTR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FIXED_DEFMSTR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FIXED_DEFMSTR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FIXED_DEFMSTR` writer - Fixed Index of Default Master"] +pub struct FIXED_DEFMSTR_W<'a> { + w: &'a mut W, +} +impl<'a> FIXED_DEFMSTR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 18)) | ((value as u32 & 0x0f) << 18); + self.w + } +} +#[doc = "Arbitration Type\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ARBT_A { + #[doc = "0: Round-Robin Arbitration"] + ROUND_ROBIN = 0, + #[doc = "1: Fixed Priority Arbitration"] + FIXED_PRIORITY = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ARBT_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ARBT` reader - Arbitration Type"] +pub struct ARBT_R(crate::FieldReader); +impl ARBT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ARBT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ARBT_A { + match self.bits { + false => ARBT_A::ROUND_ROBIN, + true => ARBT_A::FIXED_PRIORITY, + } + } + #[doc = "Checks if the value of the field is `ROUND_ROBIN`"] + #[inline(always)] + pub fn is_round_robin(&self) -> bool { + **self == ARBT_A::ROUND_ROBIN + } + #[doc = "Checks if the value of the field is `FIXED_PRIORITY`"] + #[inline(always)] + pub fn is_fixed_priority(&self) -> bool { + **self == ARBT_A::FIXED_PRIORITY + } +} +impl core::ops::Deref for ARBT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ARBT` writer - Arbitration Type"] +pub struct ARBT_W<'a> { + w: &'a mut W, +} +impl<'a> ARBT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: ARBT_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Round-Robin Arbitration"] + #[inline(always)] + pub fn round_robin(self) -> &'a mut W { + self.variant(ARBT_A::ROUND_ROBIN) + } + #[doc = "Fixed Priority Arbitration"] + #[inline(always)] + pub fn fixed_priority(self) -> &'a mut W { + self.variant(ARBT_A::FIXED_PRIORITY) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Maximum Number of Allowed Cycles for a Burst"] + #[inline(always)] + pub fn slot_cycle(&self) -> SLOT_CYCLE_R { + SLOT_CYCLE_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 16:17 - Default Master Type"] + #[inline(always)] + pub fn defmstr_type(&self) -> DEFMSTR_TYPE_R { + DEFMSTR_TYPE_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bits 18:21 - Fixed Index of Default Master"] + #[inline(always)] + pub fn fixed_defmstr(&self) -> FIXED_DEFMSTR_R { + FIXED_DEFMSTR_R::new(((self.bits >> 18) & 0x0f) as u8) + } + #[doc = "Bit 24 - Arbitration Type"] + #[inline(always)] + pub fn arbt(&self) -> ARBT_R { + ARBT_R::new(((self.bits >> 24) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - Maximum Number of Allowed Cycles for a Burst"] + #[inline(always)] + pub fn slot_cycle(&mut self) -> SLOT_CYCLE_W { + SLOT_CYCLE_W { w: self } + } + #[doc = "Bits 16:17 - Default Master Type"] + #[inline(always)] + pub fn defmstr_type(&mut self) -> DEFMSTR_TYPE_W { + DEFMSTR_TYPE_W { w: self } + } + #[doc = "Bits 18:21 - Fixed Index of Default Master"] + #[inline(always)] + pub fn fixed_defmstr(&mut self) -> FIXED_DEFMSTR_W { + FIXED_DEFMSTR_W { w: self } + } + #[doc = "Bit 24 - Arbitration Type"] + #[inline(always)] + pub fn arbt(&mut self) -> ARBT_W { + ARBT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Slave Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [scfg](index.html) module"] +pub struct SCFG_SPEC; +impl crate::RegisterSpec for SCFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [scfg::R](R) reader structure"] +impl crate::Readable for SCFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [scfg::W](W) writer structure"] +impl crate::Writable for SCFG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SCFG[%s] +to value 0x10"] +impl crate::Resettable for SCFG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x10 + } +} diff --git a/pac/atsamc20e/src/hmatrixhs/sfr.rs b/pac/atsamc20e/src/hmatrixhs/sfr.rs new file mode 100644 index 000000000000..0a7e024f73c8 --- /dev/null +++ b/pac/atsamc20e/src/hmatrixhs/sfr.rs @@ -0,0 +1,104 @@ +#[doc = "Register `SFR[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SFR[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SFR` reader - Special Function Register"] +pub struct SFR_R(crate::FieldReader); +impl SFR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + SFR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SFR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SFR` writer - Special Function Register"] +pub struct SFR_W<'a> { + w: &'a mut W, +} +impl<'a> SFR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Special Function Register"] + #[inline(always)] + pub fn sfr(&self) -> SFR_R { + SFR_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Special Function Register"] + #[inline(always)] + pub fn sfr(&mut self) -> SFR_W { + SFR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Special Function\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sfr](index.html) module"] +pub struct SFR_SPEC; +impl crate::RegisterSpec for SFR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [sfr::R](R) reader structure"] +impl crate::Readable for SFR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [sfr::W](W) writer structure"] +impl crate::Writable for SFR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SFR[%s] +to value 0"] +impl crate::Resettable for SFR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/lib.rs b/pac/atsamc20e/src/lib.rs new file mode 100644 index 000000000000..5deef8efbc97 --- /dev/null +++ b/pac/atsamc20e/src/lib.rs @@ -0,0 +1,1437 @@ +#![doc = "Peripheral access API for ATSAMC20E microcontrollers (generated using svd2rust v0.20.0 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] +svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.20.0/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"] +#![deny(const_err)] +#![deny(dead_code)] +#![deny(improper_ctypes)] +#![deny(missing_docs)] +#![deny(no_mangle_generic_items)] +#![deny(non_shorthand_field_patterns)] +#![deny(overflowing_literals)] +#![deny(path_statements)] +#![deny(patterns_in_fns_without_body)] +#![deny(private_in_public)] +#![deny(unconditional_recursion)] +#![deny(unused_allocation)] +#![deny(unused_comparisons)] +#![deny(unused_parens)] +#![deny(while_true)] +#![allow(non_camel_case_types)] +#![allow(non_snake_case)] +#![allow(clippy::all)] +#![no_std] +use core::marker::PhantomData; +use core::ops::Deref; +#[doc = r"Number available in the NVIC for configuring priority"] +pub const NVIC_PRIO_BITS: u8 = 2; +#[cfg(feature = "rt")] +pub use self::Interrupt as interrupt; +pub use cortex_m::peripheral::Peripherals as CorePeripherals; +pub use cortex_m::peripheral::{CBP, CPUID, DCB, DWT, FPB, ITM, MPU, NVIC, SCB, SYST, TPIU}; +#[cfg(feature = "rt")] +pub use cortex_m_rt::interrupt; +#[allow(unused_imports)] +use generic::*; +#[doc = r"Common register and bit access and modify traits"] +pub mod generic; +#[cfg(feature = "rt")] +extern "C" { + fn WDT(); + fn RTC(); + fn EIC(); + fn FREQM(); + fn NVMCTRL(); + fn DMAC(); + fn EVSYS(); + fn SERCOM0(); + fn SERCOM1(); + fn SERCOM2(); + fn SERCOM3(); + fn TCC0(); + fn TCC1(); + fn TCC2(); + fn TC0(); + fn TC1(); + fn TC2(); + fn TC3(); + fn TC4(); + fn ADC0(); + fn AC(); + fn PTC(); +} +#[doc(hidden)] +pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, +} +#[cfg(feature = "rt")] +#[doc(hidden)] +#[link_section = ".vector_table.interrupts"] +#[no_mangle] +pub static __INTERRUPTS: [Vector; 31] = [ + Vector { _reserved: 0 }, + Vector { _handler: WDT }, + Vector { _handler: RTC }, + Vector { _handler: EIC }, + Vector { _handler: FREQM }, + Vector { _reserved: 0 }, + Vector { _handler: NVMCTRL }, + Vector { _handler: DMAC }, + Vector { _handler: EVSYS }, + Vector { _handler: SERCOM0 }, + Vector { _handler: SERCOM1 }, + Vector { _handler: SERCOM2 }, + Vector { _handler: SERCOM3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TCC0 }, + Vector { _handler: TCC1 }, + Vector { _handler: TCC2 }, + Vector { _handler: TC0 }, + Vector { _handler: TC1 }, + Vector { _handler: TC2 }, + Vector { _handler: TC3 }, + Vector { _handler: TC4 }, + Vector { _handler: ADC0 }, + Vector { _reserved: 0 }, + Vector { _handler: AC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: PTC }, +]; +#[doc = r"Enumeration of all the interrupts."] +#[derive(Copy, Clone, Debug, PartialEq, Eq)] +#[repr(u16)] +pub enum Interrupt { + #[doc = "1 - WDT"] + WDT = 1, + #[doc = "2 - RTC"] + RTC = 2, + #[doc = "3 - EIC"] + EIC = 3, + #[doc = "4 - FREQM"] + FREQM = 4, + #[doc = "6 - NVMCTRL"] + NVMCTRL = 6, + #[doc = "7 - DMAC"] + DMAC = 7, + #[doc = "8 - EVSYS"] + EVSYS = 8, + #[doc = "9 - SERCOM0"] + SERCOM0 = 9, + #[doc = "10 - SERCOM1"] + SERCOM1 = 10, + #[doc = "11 - SERCOM2"] + SERCOM2 = 11, + #[doc = "12 - SERCOM3"] + SERCOM3 = 12, + #[doc = "17 - TCC0"] + TCC0 = 17, + #[doc = "18 - TCC1"] + TCC1 = 18, + #[doc = "19 - TCC2"] + TCC2 = 19, + #[doc = "20 - TC0"] + TC0 = 20, + #[doc = "21 - TC1"] + TC1 = 21, + #[doc = "22 - TC2"] + TC2 = 22, + #[doc = "23 - TC3"] + TC3 = 23, + #[doc = "24 - TC4"] + TC4 = 24, + #[doc = "25 - ADC0"] + ADC0 = 25, + #[doc = "27 - AC"] + AC = 27, + #[doc = "30 - PTC"] + PTC = 30, +} +unsafe impl cortex_m::interrupt::InterruptNumber for Interrupt { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } +} +#[doc = "Analog Comparators"] +pub struct AC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for AC {} +impl AC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const ac::RegisterBlock = 0x4200_5000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const ac::RegisterBlock { + Self::PTR + } +} +impl Deref for AC { + type Target = ac::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for AC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AC").finish() + } +} +#[doc = "Analog Comparators"] +pub mod ac; +#[doc = "Analog Digital Converter"] +pub struct ADC0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for ADC0 {} +impl ADC0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const adc0::RegisterBlock = 0x4200_4400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const adc0::RegisterBlock { + Self::PTR + } +} +impl Deref for ADC0 { + type Target = adc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for ADC0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ADC0").finish() + } +} +#[doc = "Analog Digital Converter"] +pub mod adc0; +#[doc = "Configurable Custom Logic"] +pub struct CCL { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for CCL {} +impl CCL { + #[doc = r"Pointer to the register block"] + pub const PTR: *const ccl::RegisterBlock = 0x4200_5c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const ccl::RegisterBlock { + Self::PTR + } +} +impl Deref for CCL { + type Target = ccl::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for CCL { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CCL").finish() + } +} +#[doc = "Configurable Custom Logic"] +pub mod ccl; +#[doc = "Divide and Square Root Accelerator"] +pub struct DIVAS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for DIVAS {} +impl DIVAS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const divas::RegisterBlock = 0x4800_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const divas::RegisterBlock { + Self::PTR + } +} +impl Deref for DIVAS { + type Target = divas::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for DIVAS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DIVAS").finish() + } +} +#[doc = "Divide and Square Root Accelerator"] +pub mod divas; +#[doc = "Direct Memory Access Controller"] +pub struct DMAC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for DMAC {} +impl DMAC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const dmac::RegisterBlock = 0x4100_6000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const dmac::RegisterBlock { + Self::PTR + } +} +impl Deref for DMAC { + type Target = dmac::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for DMAC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DMAC").finish() + } +} +#[doc = "Direct Memory Access Controller"] +pub mod dmac; +#[doc = "Device Service Unit"] +pub struct DSU { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for DSU {} +impl DSU { + #[doc = r"Pointer to the register block"] + pub const PTR: *const dsu::RegisterBlock = 0x4100_2000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const dsu::RegisterBlock { + Self::PTR + } +} +impl Deref for DSU { + type Target = dsu::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for DSU { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DSU").finish() + } +} +#[doc = "Device Service Unit"] +pub mod dsu; +#[doc = "External Interrupt Controller"] +pub struct EIC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for EIC {} +impl EIC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const eic::RegisterBlock = 0x4000_2800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const eic::RegisterBlock { + Self::PTR + } +} +impl Deref for EIC { + type Target = eic::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for EIC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EIC").finish() + } +} +#[doc = "External Interrupt Controller"] +pub mod eic; +#[doc = "Event System Interface"] +pub struct EVSYS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for EVSYS {} +impl EVSYS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const evsys::RegisterBlock = 0x4200_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const evsys::RegisterBlock { + Self::PTR + } +} +impl Deref for EVSYS { + type Target = evsys::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for EVSYS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EVSYS").finish() + } +} +#[doc = "Event System Interface"] +pub mod evsys; +#[doc = "Frequency Meter"] +pub struct FREQM { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for FREQM {} +impl FREQM { + #[doc = r"Pointer to the register block"] + pub const PTR: *const freqm::RegisterBlock = 0x4000_2c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const freqm::RegisterBlock { + Self::PTR + } +} +impl Deref for FREQM { + type Target = freqm::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for FREQM { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FREQM").finish() + } +} +#[doc = "Frequency Meter"] +pub mod freqm; +#[doc = "Generic Clock Generator"] +pub struct GCLK { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for GCLK {} +impl GCLK { + #[doc = r"Pointer to the register block"] + pub const PTR: *const gclk::RegisterBlock = 0x4000_1c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const gclk::RegisterBlock { + Self::PTR + } +} +impl Deref for GCLK { + type Target = gclk::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for GCLK { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GCLK").finish() + } +} +#[doc = "Generic Clock Generator"] +pub mod gclk; +#[doc = "HSB Matrix"] +pub struct HMATRIXHS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for HMATRIXHS {} +impl HMATRIXHS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const hmatrixhs::RegisterBlock = 0x4100_a000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const hmatrixhs::RegisterBlock { + Self::PTR + } +} +impl Deref for HMATRIXHS { + type Target = hmatrixhs::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for HMATRIXHS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HMATRIXHS").finish() + } +} +#[doc = "HSB Matrix"] +pub mod hmatrixhs; +#[doc = "Main Clock"] +pub struct MCLK { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for MCLK {} +impl MCLK { + #[doc = r"Pointer to the register block"] + pub const PTR: *const mclk::RegisterBlock = 0x4000_0800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const mclk::RegisterBlock { + Self::PTR + } +} +impl Deref for MCLK { + type Target = mclk::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for MCLK { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MCLK").finish() + } +} +#[doc = "Main Clock"] +pub mod mclk; +#[doc = "Cortex-M0+ Micro-Trace Buffer"] +pub struct MTB { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for MTB {} +impl MTB { + #[doc = r"Pointer to the register block"] + pub const PTR: *const mtb::RegisterBlock = 0x4100_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const mtb::RegisterBlock { + Self::PTR + } +} +impl Deref for MTB { + type Target = mtb::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for MTB { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MTB").finish() + } +} +#[doc = "Cortex-M0+ Micro-Trace Buffer"] +pub mod mtb; +#[doc = "Non-Volatile Memory Controller"] +pub struct NVMCTRL { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for NVMCTRL {} +impl NVMCTRL { + #[doc = r"Pointer to the register block"] + pub const PTR: *const nvmctrl::RegisterBlock = 0x4100_4000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const nvmctrl::RegisterBlock { + Self::PTR + } +} +impl Deref for NVMCTRL { + type Target = nvmctrl::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for NVMCTRL { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("NVMCTRL").finish() + } +} +#[doc = "Non-Volatile Memory Controller"] +pub mod nvmctrl; +#[doc = "Oscillators Control"] +pub struct OSCCTRL { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for OSCCTRL {} +impl OSCCTRL { + #[doc = r"Pointer to the register block"] + pub const PTR: *const oscctrl::RegisterBlock = 0x4000_1000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const oscctrl::RegisterBlock { + Self::PTR + } +} +impl Deref for OSCCTRL { + type Target = oscctrl::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for OSCCTRL { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OSCCTRL").finish() + } +} +#[doc = "Oscillators Control"] +pub mod oscctrl; +#[doc = "32k Oscillators Control"] +pub struct OSC32KCTRL { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for OSC32KCTRL {} +impl OSC32KCTRL { + #[doc = r"Pointer to the register block"] + pub const PTR: *const osc32kctrl::RegisterBlock = 0x4000_1400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const osc32kctrl::RegisterBlock { + Self::PTR + } +} +impl Deref for OSC32KCTRL { + type Target = osc32kctrl::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for OSC32KCTRL { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OSC32KCTRL").finish() + } +} +#[doc = "32k Oscillators Control"] +pub mod osc32kctrl; +#[doc = "Peripheral Access Controller"] +pub struct PAC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PAC {} +impl PAC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const pac::RegisterBlock = 0x4000_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const pac::RegisterBlock { + Self::PTR + } +} +impl Deref for PAC { + type Target = pac::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PAC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PAC").finish() + } +} +#[doc = "Peripheral Access Controller"] +pub mod pac; +#[doc = "Power Manager"] +pub struct PM { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PM {} +impl PM { + #[doc = r"Pointer to the register block"] + pub const PTR: *const pm::RegisterBlock = 0x4000_0400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const pm::RegisterBlock { + Self::PTR + } +} +impl Deref for PM { + type Target = pm::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PM { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PM").finish() + } +} +#[doc = "Power Manager"] +pub mod pm; +#[doc = "Port Module"] +pub struct PORT { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PORT {} +impl PORT { + #[doc = r"Pointer to the register block"] + pub const PTR: *const port::RegisterBlock = 0x4100_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const port::RegisterBlock { + Self::PTR + } +} +impl Deref for PORT { + type Target = port::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PORT { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PORT").finish() + } +} +#[doc = "Port Module"] +pub mod port; +#[doc = "Port Module"] +pub struct PORT_IOBUS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PORT_IOBUS {} +impl PORT_IOBUS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const port::RegisterBlock = 0x6000_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const port::RegisterBlock { + Self::PTR + } +} +impl Deref for PORT_IOBUS { + type Target = port::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PORT_IOBUS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PORT_IOBUS").finish() + } +} +#[doc = "Port Module"] +pub use port as port_iobus; +#[doc = "Reset Controller"] +pub struct RSTC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for RSTC {} +impl RSTC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const rstc::RegisterBlock = 0x4000_0c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const rstc::RegisterBlock { + Self::PTR + } +} +impl Deref for RSTC { + type Target = rstc::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for RSTC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RSTC").finish() + } +} +#[doc = "Reset Controller"] +pub mod rstc; +#[doc = "Real-Time Counter"] +pub struct RTC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for RTC {} +impl RTC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const rtc::RegisterBlock = 0x4000_2400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const rtc::RegisterBlock { + Self::PTR + } +} +impl Deref for RTC { + type Target = rtc::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for RTC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RTC").finish() + } +} +#[doc = "Real-Time Counter"] +pub mod rtc; +#[doc = "Serial Communication Interface"] +pub struct SERCOM0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SERCOM0 {} +impl SERCOM0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sercom0::RegisterBlock = 0x4200_0400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sercom0::RegisterBlock { + Self::PTR + } +} +impl Deref for SERCOM0 { + type Target = sercom0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SERCOM0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SERCOM0").finish() + } +} +#[doc = "Serial Communication Interface"] +pub mod sercom0; +#[doc = "Serial Communication Interface"] +pub struct SERCOM1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SERCOM1 {} +impl SERCOM1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sercom0::RegisterBlock = 0x4200_0800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sercom0::RegisterBlock { + Self::PTR + } +} +impl Deref for SERCOM1 { + type Target = sercom0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SERCOM1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SERCOM1").finish() + } +} +#[doc = "Serial Communication Interface"] +pub use sercom0 as sercom1; +#[doc = "Serial Communication Interface"] +pub struct SERCOM2 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SERCOM2 {} +impl SERCOM2 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sercom0::RegisterBlock = 0x4200_0c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sercom0::RegisterBlock { + Self::PTR + } +} +impl Deref for SERCOM2 { + type Target = sercom0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SERCOM2 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SERCOM2").finish() + } +} +#[doc = "Serial Communication Interface"] +pub use sercom0 as sercom2; +#[doc = "Serial Communication Interface"] +pub struct SERCOM3 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SERCOM3 {} +impl SERCOM3 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sercom0::RegisterBlock = 0x4200_1000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sercom0::RegisterBlock { + Self::PTR + } +} +impl Deref for SERCOM3 { + type Target = sercom0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SERCOM3 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SERCOM3").finish() + } +} +#[doc = "Serial Communication Interface"] +pub use sercom0 as sercom3; +#[doc = "Supply Controller"] +pub struct SUPC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SUPC {} +impl SUPC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const supc::RegisterBlock = 0x4000_1800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const supc::RegisterBlock { + Self::PTR + } +} +impl Deref for SUPC { + type Target = supc::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SUPC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SUPC").finish() + } +} +#[doc = "Supply Controller"] +pub mod supc; +#[doc = "Basic Timer Counter"] +pub struct TC0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TC0 {} +impl TC0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tc0::RegisterBlock = 0x4200_3000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tc0::RegisterBlock { + Self::PTR + } +} +impl Deref for TC0 { + type Target = tc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TC0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TC0").finish() + } +} +#[doc = "Basic Timer Counter"] +pub mod tc0; +#[doc = "Basic Timer Counter"] +pub struct TC1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TC1 {} +impl TC1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tc0::RegisterBlock = 0x4200_3400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tc0::RegisterBlock { + Self::PTR + } +} +impl Deref for TC1 { + type Target = tc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TC1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TC1").finish() + } +} +#[doc = "Basic Timer Counter"] +pub use tc0 as tc1; +#[doc = "Basic Timer Counter"] +pub struct TC2 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TC2 {} +impl TC2 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tc0::RegisterBlock = 0x4200_3800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tc0::RegisterBlock { + Self::PTR + } +} +impl Deref for TC2 { + type Target = tc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TC2 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TC2").finish() + } +} +#[doc = "Basic Timer Counter"] +pub use tc0 as tc2; +#[doc = "Basic Timer Counter"] +pub struct TC3 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TC3 {} +impl TC3 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tc0::RegisterBlock = 0x4200_3c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tc0::RegisterBlock { + Self::PTR + } +} +impl Deref for TC3 { + type Target = tc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TC3 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TC3").finish() + } +} +#[doc = "Basic Timer Counter"] +pub use tc0 as tc3; +#[doc = "Basic Timer Counter"] +pub struct TC4 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TC4 {} +impl TC4 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tc0::RegisterBlock = 0x4200_4000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tc0::RegisterBlock { + Self::PTR + } +} +impl Deref for TC4 { + type Target = tc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TC4 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TC4").finish() + } +} +#[doc = "Basic Timer Counter"] +pub use tc0 as tc4; +#[doc = "Timer Counter Control"] +pub struct TCC0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TCC0 {} +impl TCC0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tcc0::RegisterBlock = 0x4200_2400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tcc0::RegisterBlock { + Self::PTR + } +} +impl Deref for TCC0 { + type Target = tcc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TCC0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TCC0").finish() + } +} +#[doc = "Timer Counter Control"] +pub mod tcc0; +#[doc = "Timer Counter Control"] +pub struct TCC1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TCC1 {} +impl TCC1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tcc0::RegisterBlock = 0x4200_2800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tcc0::RegisterBlock { + Self::PTR + } +} +impl Deref for TCC1 { + type Target = tcc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TCC1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TCC1").finish() + } +} +#[doc = "Timer Counter Control"] +pub use tcc0 as tcc1; +#[doc = "Timer Counter Control"] +pub struct TCC2 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TCC2 {} +impl TCC2 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tcc0::RegisterBlock = 0x4200_2c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tcc0::RegisterBlock { + Self::PTR + } +} +impl Deref for TCC2 { + type Target = tcc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TCC2 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TCC2").finish() + } +} +#[doc = "Timer Counter Control"] +pub use tcc0 as tcc2; +#[doc = "Watchdog Timer"] +pub struct WDT { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for WDT {} +impl WDT { + #[doc = r"Pointer to the register block"] + pub const PTR: *const wdt::RegisterBlock = 0x4000_2000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const wdt::RegisterBlock { + Self::PTR + } +} +impl Deref for WDT { + type Target = wdt::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for WDT { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("WDT").finish() + } +} +#[doc = "Watchdog Timer"] +pub mod wdt; +#[doc = "System timer"] +pub struct SYSTICK { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SYSTICK {} +impl SYSTICK { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sys_tick::RegisterBlock = 0xe000_e010 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sys_tick::RegisterBlock { + Self::PTR + } +} +impl Deref for SYSTICK { + type Target = sys_tick::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SYSTICK { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SYSTICK").finish() + } +} +#[doc = "System timer"] +pub mod sys_tick; +#[doc = "System Control Registers"] +pub struct SYSTEMCONTROL { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SYSTEMCONTROL {} +impl SYSTEMCONTROL { + #[doc = r"Pointer to the register block"] + pub const PTR: *const system_control::RegisterBlock = 0xe000_e000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const system_control::RegisterBlock { + Self::PTR + } +} +impl Deref for SYSTEMCONTROL { + type Target = system_control::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SYSTEMCONTROL { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SYSTEMCONTROL").finish() + } +} +#[doc = "System Control Registers"] +pub mod system_control; +#[no_mangle] +static mut DEVICE_PERIPHERALS: bool = false; +#[doc = r"All the peripherals"] +#[allow(non_snake_case)] +pub struct Peripherals { + #[doc = "AC"] + pub AC: AC, + #[doc = "ADC0"] + pub ADC0: ADC0, + #[doc = "CCL"] + pub CCL: CCL, + #[doc = "DIVAS"] + pub DIVAS: DIVAS, + #[doc = "DMAC"] + pub DMAC: DMAC, + #[doc = "DSU"] + pub DSU: DSU, + #[doc = "EIC"] + pub EIC: EIC, + #[doc = "EVSYS"] + pub EVSYS: EVSYS, + #[doc = "FREQM"] + pub FREQM: FREQM, + #[doc = "GCLK"] + pub GCLK: GCLK, + #[doc = "HMATRIXHS"] + pub HMATRIXHS: HMATRIXHS, + #[doc = "MCLK"] + pub MCLK: MCLK, + #[doc = "MTB"] + pub MTB: MTB, + #[doc = "NVMCTRL"] + pub NVMCTRL: NVMCTRL, + #[doc = "OSCCTRL"] + pub OSCCTRL: OSCCTRL, + #[doc = "OSC32KCTRL"] + pub OSC32KCTRL: OSC32KCTRL, + #[doc = "PAC"] + pub PAC: PAC, + #[doc = "PM"] + pub PM: PM, + #[doc = "PORT"] + pub PORT: PORT, + #[doc = "PORT_IOBUS"] + pub PORT_IOBUS: PORT_IOBUS, + #[doc = "RSTC"] + pub RSTC: RSTC, + #[doc = "RTC"] + pub RTC: RTC, + #[doc = "SERCOM0"] + pub SERCOM0: SERCOM0, + #[doc = "SERCOM1"] + pub SERCOM1: SERCOM1, + #[doc = "SERCOM2"] + pub SERCOM2: SERCOM2, + #[doc = "SERCOM3"] + pub SERCOM3: SERCOM3, + #[doc = "SUPC"] + pub SUPC: SUPC, + #[doc = "TC0"] + pub TC0: TC0, + #[doc = "TC1"] + pub TC1: TC1, + #[doc = "TC2"] + pub TC2: TC2, + #[doc = "TC3"] + pub TC3: TC3, + #[doc = "TC4"] + pub TC4: TC4, + #[doc = "TCC0"] + pub TCC0: TCC0, + #[doc = "TCC1"] + pub TCC1: TCC1, + #[doc = "TCC2"] + pub TCC2: TCC2, + #[doc = "WDT"] + pub WDT: WDT, + #[doc = "SYSTICK"] + pub SYSTICK: SYSTICK, + #[doc = "SYSTEMCONTROL"] + pub SYSTEMCONTROL: SYSTEMCONTROL, +} +impl Peripherals { + #[doc = r"Returns all the peripherals *once*"] + #[inline] + pub fn take() -> Option { + cortex_m::interrupt::free(|_| { + if unsafe { DEVICE_PERIPHERALS } { + None + } else { + Some(unsafe { Peripherals::steal() }) + } + }) + } + #[doc = r"Unchecked version of `Peripherals::take`"] + #[inline] + pub unsafe fn steal() -> Self { + DEVICE_PERIPHERALS = true; + Peripherals { + AC: AC { + _marker: PhantomData, + }, + ADC0: ADC0 { + _marker: PhantomData, + }, + CCL: CCL { + _marker: PhantomData, + }, + DIVAS: DIVAS { + _marker: PhantomData, + }, + DMAC: DMAC { + _marker: PhantomData, + }, + DSU: DSU { + _marker: PhantomData, + }, + EIC: EIC { + _marker: PhantomData, + }, + EVSYS: EVSYS { + _marker: PhantomData, + }, + FREQM: FREQM { + _marker: PhantomData, + }, + GCLK: GCLK { + _marker: PhantomData, + }, + HMATRIXHS: HMATRIXHS { + _marker: PhantomData, + }, + MCLK: MCLK { + _marker: PhantomData, + }, + MTB: MTB { + _marker: PhantomData, + }, + NVMCTRL: NVMCTRL { + _marker: PhantomData, + }, + OSCCTRL: OSCCTRL { + _marker: PhantomData, + }, + OSC32KCTRL: OSC32KCTRL { + _marker: PhantomData, + }, + PAC: PAC { + _marker: PhantomData, + }, + PM: PM { + _marker: PhantomData, + }, + PORT: PORT { + _marker: PhantomData, + }, + PORT_IOBUS: PORT_IOBUS { + _marker: PhantomData, + }, + RSTC: RSTC { + _marker: PhantomData, + }, + RTC: RTC { + _marker: PhantomData, + }, + SERCOM0: SERCOM0 { + _marker: PhantomData, + }, + SERCOM1: SERCOM1 { + _marker: PhantomData, + }, + SERCOM2: SERCOM2 { + _marker: PhantomData, + }, + SERCOM3: SERCOM3 { + _marker: PhantomData, + }, + SUPC: SUPC { + _marker: PhantomData, + }, + TC0: TC0 { + _marker: PhantomData, + }, + TC1: TC1 { + _marker: PhantomData, + }, + TC2: TC2 { + _marker: PhantomData, + }, + TC3: TC3 { + _marker: PhantomData, + }, + TC4: TC4 { + _marker: PhantomData, + }, + TCC0: TCC0 { + _marker: PhantomData, + }, + TCC1: TCC1 { + _marker: PhantomData, + }, + TCC2: TCC2 { + _marker: PhantomData, + }, + WDT: WDT { + _marker: PhantomData, + }, + SYSTICK: SYSTICK { + _marker: PhantomData, + }, + SYSTEMCONTROL: SYSTEMCONTROL { + _marker: PhantomData, + }, + } + } +} diff --git a/pac/atsamc20e/src/mclk.rs b/pac/atsamc20e/src/mclk.rs new file mode 100644 index 000000000000..fc7efe3a584e --- /dev/null +++ b/pac/atsamc20e/src/mclk.rs @@ -0,0 +1,54 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved0: [u8; 0x01], + #[doc = "0x01 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x02 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x03 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x04 - CPU Clock Division"] + pub cpudiv: crate::Reg, + _reserved4: [u8; 0x0b], + #[doc = "0x10 - AHB Mask"] + pub ahbmask: crate::Reg, + #[doc = "0x14 - APBA Mask"] + pub apbamask: crate::Reg, + #[doc = "0x18 - APBB Mask"] + pub apbbmask: crate::Reg, + #[doc = "0x1c - APBC Mask"] + pub apbcmask: crate::Reg, +} +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "CPUDIV register accessor: an alias for `Reg`"] +pub type CPUDIV = crate::Reg; +#[doc = "CPU Clock Division"] +pub mod cpudiv; +#[doc = "AHBMASK register accessor: an alias for `Reg`"] +pub type AHBMASK = crate::Reg; +#[doc = "AHB Mask"] +pub mod ahbmask; +#[doc = "APBAMASK register accessor: an alias for `Reg`"] +pub type APBAMASK = crate::Reg; +#[doc = "APBA Mask"] +pub mod apbamask; +#[doc = "APBBMASK register accessor: an alias for `Reg`"] +pub type APBBMASK = crate::Reg; +#[doc = "APBB Mask"] +pub mod apbbmask; +#[doc = "APBCMASK register accessor: an alias for `Reg`"] +pub type APBCMASK = crate::Reg; +#[doc = "APBC Mask"] +pub mod apbcmask; diff --git a/pac/atsamc20e/src/mclk/ahbmask.rs b/pac/atsamc20e/src/mclk/ahbmask.rs new file mode 100644 index 000000000000..9366eb778bfa --- /dev/null +++ b/pac/atsamc20e/src/mclk/ahbmask.rs @@ -0,0 +1,583 @@ +#[doc = "Register `AHBMASK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `AHBMASK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `HPB0_` reader - HPB0 AHB Clock Mask"] +pub struct HPB0__R(crate::FieldReader); +impl HPB0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HPB0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HPB0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HPB0_` writer - HPB0 AHB Clock Mask"] +pub struct HPB0__W<'a> { + w: &'a mut W, +} +impl<'a> HPB0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `HPB1_` reader - HPB1 AHB Clock Mask"] +pub struct HPB1__R(crate::FieldReader); +impl HPB1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HPB1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HPB1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HPB1_` writer - HPB1 AHB Clock Mask"] +pub struct HPB1__W<'a> { + w: &'a mut W, +} +impl<'a> HPB1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `HPB2_` reader - HPB2 AHB Clock Mask"] +pub struct HPB2__R(crate::FieldReader); +impl HPB2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HPB2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HPB2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HPB2_` writer - HPB2 AHB Clock Mask"] +pub struct HPB2__W<'a> { + w: &'a mut W, +} +impl<'a> HPB2__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `DSU_` reader - DSU AHB Clock Mask"] +pub struct DSU__R(crate::FieldReader); +impl DSU__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DSU__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DSU__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DSU_` writer - DSU AHB Clock Mask"] +pub struct DSU__W<'a> { + w: &'a mut W, +} +impl<'a> DSU__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `HMATRIXHS_` reader - HMATRIXHS AHB Clock Mask"] +pub struct HMATRIXHS__R(crate::FieldReader); +impl HMATRIXHS__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HMATRIXHS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HMATRIXHS__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HMATRIXHS_` writer - HMATRIXHS AHB Clock Mask"] +pub struct HMATRIXHS__W<'a> { + w: &'a mut W, +} +impl<'a> HMATRIXHS__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `NVMCTRL_` reader - NVMCTRL AHB Clock Mask"] +pub struct NVMCTRL__R(crate::FieldReader); +impl NVMCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NVMCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NVMCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NVMCTRL_` writer - NVMCTRL AHB Clock Mask"] +pub struct NVMCTRL__W<'a> { + w: &'a mut W, +} +impl<'a> NVMCTRL__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `HSRAM_` reader - HSRAM AHB Clock Mask"] +pub struct HSRAM__R(crate::FieldReader); +impl HSRAM__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HSRAM__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HSRAM__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HSRAM_` writer - HSRAM AHB Clock Mask"] +pub struct HSRAM__W<'a> { + w: &'a mut W, +} +impl<'a> HSRAM__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `DMAC_` reader - DMAC AHB Clock Mask"] +pub struct DMAC__R(crate::FieldReader); +impl DMAC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DMAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DMAC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DMAC_` writer - DMAC AHB Clock Mask"] +pub struct DMAC__W<'a> { + w: &'a mut W, +} +impl<'a> DMAC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `PAC_` reader - PAC AHB Clock Mask"] +pub struct PAC__R(crate::FieldReader); +impl PAC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PAC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PAC_` writer - PAC AHB Clock Mask"] +pub struct PAC__W<'a> { + w: &'a mut W, +} +impl<'a> PAC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `NVMCTRL_PICACHU_` reader - NVMCTRL_PICACHU AHB Clock Mask"] +pub struct NVMCTRL_PICACHU__R(crate::FieldReader); +impl NVMCTRL_PICACHU__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NVMCTRL_PICACHU__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NVMCTRL_PICACHU__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NVMCTRL_PICACHU_` writer - NVMCTRL_PICACHU AHB Clock Mask"] +pub struct NVMCTRL_PICACHU__W<'a> { + w: &'a mut W, +} +impl<'a> NVMCTRL_PICACHU__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `DIVAS_` reader - DIVAS AHB Clock Mask"] +pub struct DIVAS__R(crate::FieldReader); +impl DIVAS__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIVAS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIVAS__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIVAS_` writer - DIVAS AHB Clock Mask"] +pub struct DIVAS__W<'a> { + w: &'a mut W, +} +impl<'a> DIVAS__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +impl R { + #[doc = "Bit 0 - HPB0 AHB Clock Mask"] + #[inline(always)] + pub fn hpb0_(&self) -> HPB0__R { + HPB0__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - HPB1 AHB Clock Mask"] + #[inline(always)] + pub fn hpb1_(&self) -> HPB1__R { + HPB1__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - HPB2 AHB Clock Mask"] + #[inline(always)] + pub fn hpb2_(&self) -> HPB2__R { + HPB2__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - DSU AHB Clock Mask"] + #[inline(always)] + pub fn dsu_(&self) -> DSU__R { + DSU__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - HMATRIXHS AHB Clock Mask"] + #[inline(always)] + pub fn hmatrixhs_(&self) -> HMATRIXHS__R { + HMATRIXHS__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - NVMCTRL AHB Clock Mask"] + #[inline(always)] + pub fn nvmctrl_(&self) -> NVMCTRL__R { + NVMCTRL__R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - HSRAM AHB Clock Mask"] + #[inline(always)] + pub fn hsram_(&self) -> HSRAM__R { + HSRAM__R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - DMAC AHB Clock Mask"] + #[inline(always)] + pub fn dmac_(&self) -> DMAC__R { + DMAC__R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 10 - PAC AHB Clock Mask"] + #[inline(always)] + pub fn pac_(&self) -> PAC__R { + PAC__R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - NVMCTRL_PICACHU AHB Clock Mask"] + #[inline(always)] + pub fn nvmctrl_picachu_(&self) -> NVMCTRL_PICACHU__R { + NVMCTRL_PICACHU__R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - DIVAS AHB Clock Mask"] + #[inline(always)] + pub fn divas_(&self) -> DIVAS__R { + DIVAS__R::new(((self.bits >> 12) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - HPB0 AHB Clock Mask"] + #[inline(always)] + pub fn hpb0_(&mut self) -> HPB0__W { + HPB0__W { w: self } + } + #[doc = "Bit 1 - HPB1 AHB Clock Mask"] + #[inline(always)] + pub fn hpb1_(&mut self) -> HPB1__W { + HPB1__W { w: self } + } + #[doc = "Bit 2 - HPB2 AHB Clock Mask"] + #[inline(always)] + pub fn hpb2_(&mut self) -> HPB2__W { + HPB2__W { w: self } + } + #[doc = "Bit 3 - DSU AHB Clock Mask"] + #[inline(always)] + pub fn dsu_(&mut self) -> DSU__W { + DSU__W { w: self } + } + #[doc = "Bit 4 - HMATRIXHS AHB Clock Mask"] + #[inline(always)] + pub fn hmatrixhs_(&mut self) -> HMATRIXHS__W { + HMATRIXHS__W { w: self } + } + #[doc = "Bit 5 - NVMCTRL AHB Clock Mask"] + #[inline(always)] + pub fn nvmctrl_(&mut self) -> NVMCTRL__W { + NVMCTRL__W { w: self } + } + #[doc = "Bit 6 - HSRAM AHB Clock Mask"] + #[inline(always)] + pub fn hsram_(&mut self) -> HSRAM__W { + HSRAM__W { w: self } + } + #[doc = "Bit 7 - DMAC AHB Clock Mask"] + #[inline(always)] + pub fn dmac_(&mut self) -> DMAC__W { + DMAC__W { w: self } + } + #[doc = "Bit 10 - PAC AHB Clock Mask"] + #[inline(always)] + pub fn pac_(&mut self) -> PAC__W { + PAC__W { w: self } + } + #[doc = "Bit 11 - NVMCTRL_PICACHU AHB Clock Mask"] + #[inline(always)] + pub fn nvmctrl_picachu_(&mut self) -> NVMCTRL_PICACHU__W { + NVMCTRL_PICACHU__W { w: self } + } + #[doc = "Bit 12 - DIVAS AHB Clock Mask"] + #[inline(always)] + pub fn divas_(&mut self) -> DIVAS__W { + DIVAS__W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "AHB Mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ahbmask](index.html) module"] +pub struct AHBMASK_SPEC; +impl crate::RegisterSpec for AHBMASK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ahbmask::R](R) reader structure"] +impl crate::Readable for AHBMASK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ahbmask::W](W) writer structure"] +impl crate::Writable for AHBMASK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets AHBMASK to value 0x1cff"] +impl crate::Resettable for AHBMASK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x1cff + } +} diff --git a/pac/atsamc20e/src/mclk/apbamask.rs b/pac/atsamc20e/src/mclk/apbamask.rs new file mode 100644 index 000000000000..3e095e73a158 --- /dev/null +++ b/pac/atsamc20e/src/mclk/apbamask.rs @@ -0,0 +1,630 @@ +#[doc = "Register `APBAMASK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `APBAMASK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PAC_` reader - PAC APB Clock Enable"] +pub struct PAC__R(crate::FieldReader); +impl PAC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PAC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PAC_` writer - PAC APB Clock Enable"] +pub struct PAC__W<'a> { + w: &'a mut W, +} +impl<'a> PAC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `PM_` reader - PM APB Clock Enable"] +pub struct PM__R(crate::FieldReader); +impl PM__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PM__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PM__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PM_` writer - PM APB Clock Enable"] +pub struct PM__W<'a> { + w: &'a mut W, +} +impl<'a> PM__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MCLK_` reader - MCLK APB Clock Enable"] +pub struct MCLK__R(crate::FieldReader); +impl MCLK__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCLK__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCLK__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCLK_` writer - MCLK APB Clock Enable"] +pub struct MCLK__W<'a> { + w: &'a mut W, +} +impl<'a> MCLK__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RSTC_` reader - RSTC APB Clock Enable"] +pub struct RSTC__R(crate::FieldReader); +impl RSTC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RSTC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RSTC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RSTC_` writer - RSTC APB Clock Enable"] +pub struct RSTC__W<'a> { + w: &'a mut W, +} +impl<'a> RSTC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `OSCCTRL_` reader - OSCCTRL APB Clock Enable"] +pub struct OSCCTRL__R(crate::FieldReader); +impl OSCCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSCCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSCCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSCCTRL_` writer - OSCCTRL APB Clock Enable"] +pub struct OSCCTRL__W<'a> { + w: &'a mut W, +} +impl<'a> OSCCTRL__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `OSC32KCTRL_` reader - OSC32KCTRL APB Clock Enable"] +pub struct OSC32KCTRL__R(crate::FieldReader); +impl OSC32KCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC32KCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC32KCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC32KCTRL_` writer - OSC32KCTRL APB Clock Enable"] +pub struct OSC32KCTRL__W<'a> { + w: &'a mut W, +} +impl<'a> OSC32KCTRL__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `SUPC_` reader - SUPC APB Clock Enable"] +pub struct SUPC__R(crate::FieldReader); +impl SUPC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SUPC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SUPC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SUPC_` writer - SUPC APB Clock Enable"] +pub struct SUPC__W<'a> { + w: &'a mut W, +} +impl<'a> SUPC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `GCLK_` reader - GCLK APB Clock Enable"] +pub struct GCLK__R(crate::FieldReader); +impl GCLK__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GCLK__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GCLK__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GCLK_` writer - GCLK APB Clock Enable"] +pub struct GCLK__W<'a> { + w: &'a mut W, +} +impl<'a> GCLK__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `WDT_` reader - WDT APB Clock Enable"] +pub struct WDT__R(crate::FieldReader); +impl WDT__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WDT__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WDT__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WDT_` writer - WDT APB Clock Enable"] +pub struct WDT__W<'a> { + w: &'a mut W, +} +impl<'a> WDT__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `RTC_` reader - RTC APB Clock Enable"] +pub struct RTC__R(crate::FieldReader); +impl RTC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RTC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RTC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RTC_` writer - RTC APB Clock Enable"] +pub struct RTC__W<'a> { + w: &'a mut W, +} +impl<'a> RTC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `EIC_` reader - EIC APB Clock Enable"] +pub struct EIC__R(crate::FieldReader); +impl EIC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EIC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EIC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EIC_` writer - EIC APB Clock Enable"] +pub struct EIC__W<'a> { + w: &'a mut W, +} +impl<'a> EIC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `FREQM_` reader - FREQM APB Clock Enable"] +pub struct FREQM__R(crate::FieldReader); +impl FREQM__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FREQM__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FREQM__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FREQM_` writer - FREQM APB Clock Enable"] +pub struct FREQM__W<'a> { + w: &'a mut W, +} +impl<'a> FREQM__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +impl R { + #[doc = "Bit 0 - PAC APB Clock Enable"] + #[inline(always)] + pub fn pac_(&self) -> PAC__R { + PAC__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - PM APB Clock Enable"] + #[inline(always)] + pub fn pm_(&self) -> PM__R { + PM__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - MCLK APB Clock Enable"] + #[inline(always)] + pub fn mclk_(&self) -> MCLK__R { + MCLK__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - RSTC APB Clock Enable"] + #[inline(always)] + pub fn rstc_(&self) -> RSTC__R { + RSTC__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - OSCCTRL APB Clock Enable"] + #[inline(always)] + pub fn oscctrl_(&self) -> OSCCTRL__R { + OSCCTRL__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - OSC32KCTRL APB Clock Enable"] + #[inline(always)] + pub fn osc32kctrl_(&self) -> OSC32KCTRL__R { + OSC32KCTRL__R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - SUPC APB Clock Enable"] + #[inline(always)] + pub fn supc_(&self) -> SUPC__R { + SUPC__R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - GCLK APB Clock Enable"] + #[inline(always)] + pub fn gclk_(&self) -> GCLK__R { + GCLK__R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - WDT APB Clock Enable"] + #[inline(always)] + pub fn wdt_(&self) -> WDT__R { + WDT__R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - RTC APB Clock Enable"] + #[inline(always)] + pub fn rtc_(&self) -> RTC__R { + RTC__R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - EIC APB Clock Enable"] + #[inline(always)] + pub fn eic_(&self) -> EIC__R { + EIC__R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - FREQM APB Clock Enable"] + #[inline(always)] + pub fn freqm_(&self) -> FREQM__R { + FREQM__R::new(((self.bits >> 11) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - PAC APB Clock Enable"] + #[inline(always)] + pub fn pac_(&mut self) -> PAC__W { + PAC__W { w: self } + } + #[doc = "Bit 1 - PM APB Clock Enable"] + #[inline(always)] + pub fn pm_(&mut self) -> PM__W { + PM__W { w: self } + } + #[doc = "Bit 2 - MCLK APB Clock Enable"] + #[inline(always)] + pub fn mclk_(&mut self) -> MCLK__W { + MCLK__W { w: self } + } + #[doc = "Bit 3 - RSTC APB Clock Enable"] + #[inline(always)] + pub fn rstc_(&mut self) -> RSTC__W { + RSTC__W { w: self } + } + #[doc = "Bit 4 - OSCCTRL APB Clock Enable"] + #[inline(always)] + pub fn oscctrl_(&mut self) -> OSCCTRL__W { + OSCCTRL__W { w: self } + } + #[doc = "Bit 5 - OSC32KCTRL APB Clock Enable"] + #[inline(always)] + pub fn osc32kctrl_(&mut self) -> OSC32KCTRL__W { + OSC32KCTRL__W { w: self } + } + #[doc = "Bit 6 - SUPC APB Clock Enable"] + #[inline(always)] + pub fn supc_(&mut self) -> SUPC__W { + SUPC__W { w: self } + } + #[doc = "Bit 7 - GCLK APB Clock Enable"] + #[inline(always)] + pub fn gclk_(&mut self) -> GCLK__W { + GCLK__W { w: self } + } + #[doc = "Bit 8 - WDT APB Clock Enable"] + #[inline(always)] + pub fn wdt_(&mut self) -> WDT__W { + WDT__W { w: self } + } + #[doc = "Bit 9 - RTC APB Clock Enable"] + #[inline(always)] + pub fn rtc_(&mut self) -> RTC__W { + RTC__W { w: self } + } + #[doc = "Bit 10 - EIC APB Clock Enable"] + #[inline(always)] + pub fn eic_(&mut self) -> EIC__W { + EIC__W { w: self } + } + #[doc = "Bit 11 - FREQM APB Clock Enable"] + #[inline(always)] + pub fn freqm_(&mut self) -> FREQM__W { + FREQM__W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "APBA Mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [apbamask](index.html) module"] +pub struct APBAMASK_SPEC; +impl crate::RegisterSpec for APBAMASK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [apbamask::R](R) reader structure"] +impl crate::Readable for APBAMASK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [apbamask::W](W) writer structure"] +impl crate::Writable for APBAMASK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets APBAMASK to value 0x0fff"] +impl crate::Resettable for APBAMASK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0fff + } +} diff --git a/pac/atsamc20e/src/mclk/apbbmask.rs b/pac/atsamc20e/src/mclk/apbbmask.rs new file mode 100644 index 000000000000..e1ec6b1f2323 --- /dev/null +++ b/pac/atsamc20e/src/mclk/apbbmask.rs @@ -0,0 +1,254 @@ +#[doc = "Register `APBBMASK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `APBBMASK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PORT_` reader - PORT APB Clock Enable"] +pub struct PORT__R(crate::FieldReader); +impl PORT__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PORT__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PORT__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PORT_` writer - PORT APB Clock Enable"] +pub struct PORT__W<'a> { + w: &'a mut W, +} +impl<'a> PORT__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `DSU_` reader - DSU APB Clock Enable"] +pub struct DSU__R(crate::FieldReader); +impl DSU__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DSU__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DSU__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DSU_` writer - DSU APB Clock Enable"] +pub struct DSU__W<'a> { + w: &'a mut W, +} +impl<'a> DSU__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `NVMCTRL_` reader - NVMCTRL APB Clock Enable"] +pub struct NVMCTRL__R(crate::FieldReader); +impl NVMCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NVMCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NVMCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NVMCTRL_` writer - NVMCTRL APB Clock Enable"] +pub struct NVMCTRL__W<'a> { + w: &'a mut W, +} +impl<'a> NVMCTRL__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `HMATRIXHS_` reader - HMATRIXHS APB Clock Enable"] +pub struct HMATRIXHS__R(crate::FieldReader); +impl HMATRIXHS__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HMATRIXHS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HMATRIXHS__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HMATRIXHS_` writer - HMATRIXHS APB Clock Enable"] +pub struct HMATRIXHS__W<'a> { + w: &'a mut W, +} +impl<'a> HMATRIXHS__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - PORT APB Clock Enable"] + #[inline(always)] + pub fn port_(&self) -> PORT__R { + PORT__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - DSU APB Clock Enable"] + #[inline(always)] + pub fn dsu_(&self) -> DSU__R { + DSU__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - NVMCTRL APB Clock Enable"] + #[inline(always)] + pub fn nvmctrl_(&self) -> NVMCTRL__R { + NVMCTRL__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 5 - HMATRIXHS APB Clock Enable"] + #[inline(always)] + pub fn hmatrixhs_(&self) -> HMATRIXHS__R { + HMATRIXHS__R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - PORT APB Clock Enable"] + #[inline(always)] + pub fn port_(&mut self) -> PORT__W { + PORT__W { w: self } + } + #[doc = "Bit 1 - DSU APB Clock Enable"] + #[inline(always)] + pub fn dsu_(&mut self) -> DSU__W { + DSU__W { w: self } + } + #[doc = "Bit 2 - NVMCTRL APB Clock Enable"] + #[inline(always)] + pub fn nvmctrl_(&mut self) -> NVMCTRL__W { + NVMCTRL__W { w: self } + } + #[doc = "Bit 5 - HMATRIXHS APB Clock Enable"] + #[inline(always)] + pub fn hmatrixhs_(&mut self) -> HMATRIXHS__W { + HMATRIXHS__W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "APBB Mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [apbbmask](index.html) module"] +pub struct APBBMASK_SPEC; +impl crate::RegisterSpec for APBBMASK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [apbbmask::R](R) reader structure"] +impl crate::Readable for APBBMASK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [apbbmask::W](W) writer structure"] +impl crate::Writable for APBBMASK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets APBBMASK to value 0x07"] +impl crate::Resettable for APBBMASK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x07 + } +} diff --git a/pac/atsamc20e/src/mclk/apbcmask.rs b/pac/atsamc20e/src/mclk/apbcmask.rs new file mode 100644 index 000000000000..64b4ce91fe5d --- /dev/null +++ b/pac/atsamc20e/src/mclk/apbcmask.rs @@ -0,0 +1,865 @@ +#[doc = "Register `APBCMASK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `APBCMASK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVSYS_` reader - EVSYS APB Clock Enable"] +pub struct EVSYS__R(crate::FieldReader); +impl EVSYS__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVSYS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVSYS__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVSYS_` writer - EVSYS APB Clock Enable"] +pub struct EVSYS__W<'a> { + w: &'a mut W, +} +impl<'a> EVSYS__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `SERCOM0_` reader - SERCOM0 APB Clock Enable"] +pub struct SERCOM0__R(crate::FieldReader); +impl SERCOM0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM0_` writer - SERCOM0 APB Clock Enable"] +pub struct SERCOM0__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SERCOM1_` reader - SERCOM1 APB Clock Enable"] +pub struct SERCOM1__R(crate::FieldReader); +impl SERCOM1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM1_` writer - SERCOM1 APB Clock Enable"] +pub struct SERCOM1__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SERCOM2_` reader - SERCOM2 APB Clock Enable"] +pub struct SERCOM2__R(crate::FieldReader); +impl SERCOM2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM2_` writer - SERCOM2 APB Clock Enable"] +pub struct SERCOM2__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM2__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `SERCOM3_` reader - SERCOM3 APB Clock Enable"] +pub struct SERCOM3__R(crate::FieldReader); +impl SERCOM3__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM3__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM3__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM3_` writer - SERCOM3 APB Clock Enable"] +pub struct SERCOM3__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM3__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `TCC0_` reader - TCC0 APB Clock Enable"] +pub struct TCC0__R(crate::FieldReader); +impl TCC0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCC0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCC0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCC0_` writer - TCC0 APB Clock Enable"] +pub struct TCC0__W<'a> { + w: &'a mut W, +} +impl<'a> TCC0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `TCC1_` reader - TCC1 APB Clock Enable"] +pub struct TCC1__R(crate::FieldReader); +impl TCC1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCC1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCC1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCC1_` writer - TCC1 APB Clock Enable"] +pub struct TCC1__W<'a> { + w: &'a mut W, +} +impl<'a> TCC1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `TCC2_` reader - TCC2 APB Clock Enable"] +pub struct TCC2__R(crate::FieldReader); +impl TCC2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCC2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCC2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCC2_` writer - TCC2 APB Clock Enable"] +pub struct TCC2__W<'a> { + w: &'a mut W, +} +impl<'a> TCC2__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `TC0_` reader - TC0 APB Clock Enable"] +pub struct TC0__R(crate::FieldReader); +impl TC0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC0_` writer - TC0 APB Clock Enable"] +pub struct TC0__W<'a> { + w: &'a mut W, +} +impl<'a> TC0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `TC1_` reader - TC1 APB Clock Enable"] +pub struct TC1__R(crate::FieldReader); +impl TC1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC1_` writer - TC1 APB Clock Enable"] +pub struct TC1__W<'a> { + w: &'a mut W, +} +impl<'a> TC1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `TC2_` reader - TC2 APB Clock Enable"] +pub struct TC2__R(crate::FieldReader); +impl TC2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC2_` writer - TC2 APB Clock Enable"] +pub struct TC2__W<'a> { + w: &'a mut W, +} +impl<'a> TC2__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `TC3_` reader - TC3 APB Clock Enable"] +pub struct TC3__R(crate::FieldReader); +impl TC3__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC3__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC3__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC3_` writer - TC3 APB Clock Enable"] +pub struct TC3__W<'a> { + w: &'a mut W, +} +impl<'a> TC3__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `TC4_` reader - TC4 APB Clock Enable"] +pub struct TC4__R(crate::FieldReader); +impl TC4__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC4__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC4__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC4_` writer - TC4 APB Clock Enable"] +pub struct TC4__W<'a> { + w: &'a mut W, +} +impl<'a> TC4__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `ADC0_` reader - ADC0 APB Clock Enable"] +pub struct ADC0__R(crate::FieldReader); +impl ADC0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ADC0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADC0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADC0_` writer - ADC0 APB Clock Enable"] +pub struct ADC0__W<'a> { + w: &'a mut W, +} +impl<'a> ADC0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `AC_` reader - AC APB Clock Enable"] +pub struct AC__R(crate::FieldReader); +impl AC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AC_` writer - AC APB Clock Enable"] +pub struct AC__W<'a> { + w: &'a mut W, +} +impl<'a> AC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `PTC_` reader - PTC APB Clock Enable"] +pub struct PTC__R(crate::FieldReader); +impl PTC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PTC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PTC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PTC_` writer - PTC APB Clock Enable"] +pub struct PTC__W<'a> { + w: &'a mut W, +} +impl<'a> PTC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `CCL_` reader - CCL APB Clock Enable"] +pub struct CCL__R(crate::FieldReader); +impl CCL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCL_` writer - CCL APB Clock Enable"] +pub struct CCL__W<'a> { + w: &'a mut W, +} +impl<'a> CCL__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +impl R { + #[doc = "Bit 0 - EVSYS APB Clock Enable"] + #[inline(always)] + pub fn evsys_(&self) -> EVSYS__R { + EVSYS__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM0 APB Clock Enable"] + #[inline(always)] + pub fn sercom0_(&self) -> SERCOM0__R { + SERCOM0__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - SERCOM1 APB Clock Enable"] + #[inline(always)] + pub fn sercom1_(&self) -> SERCOM1__R { + SERCOM1__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - SERCOM2 APB Clock Enable"] + #[inline(always)] + pub fn sercom2_(&self) -> SERCOM2__R { + SERCOM2__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - SERCOM3 APB Clock Enable"] + #[inline(always)] + pub fn sercom3_(&self) -> SERCOM3__R { + SERCOM3__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 9 - TCC0 APB Clock Enable"] + #[inline(always)] + pub fn tcc0_(&self) -> TCC0__R { + TCC0__R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - TCC1 APB Clock Enable"] + #[inline(always)] + pub fn tcc1_(&self) -> TCC1__R { + TCC1__R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - TCC2 APB Clock Enable"] + #[inline(always)] + pub fn tcc2_(&self) -> TCC2__R { + TCC2__R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - TC0 APB Clock Enable"] + #[inline(always)] + pub fn tc0_(&self) -> TC0__R { + TC0__R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - TC1 APB Clock Enable"] + #[inline(always)] + pub fn tc1_(&self) -> TC1__R { + TC1__R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - TC2 APB Clock Enable"] + #[inline(always)] + pub fn tc2_(&self) -> TC2__R { + TC2__R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - TC3 APB Clock Enable"] + #[inline(always)] + pub fn tc3_(&self) -> TC3__R { + TC3__R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - TC4 APB Clock Enable"] + #[inline(always)] + pub fn tc4_(&self) -> TC4__R { + TC4__R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - ADC0 APB Clock Enable"] + #[inline(always)] + pub fn adc0_(&self) -> ADC0__R { + ADC0__R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 20 - AC APB Clock Enable"] + #[inline(always)] + pub fn ac_(&self) -> AC__R { + AC__R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 22 - PTC APB Clock Enable"] + #[inline(always)] + pub fn ptc_(&self) -> PTC__R { + PTC__R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - CCL APB Clock Enable"] + #[inline(always)] + pub fn ccl_(&self) -> CCL__R { + CCL__R::new(((self.bits >> 23) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - EVSYS APB Clock Enable"] + #[inline(always)] + pub fn evsys_(&mut self) -> EVSYS__W { + EVSYS__W { w: self } + } + #[doc = "Bit 1 - SERCOM0 APB Clock Enable"] + #[inline(always)] + pub fn sercom0_(&mut self) -> SERCOM0__W { + SERCOM0__W { w: self } + } + #[doc = "Bit 2 - SERCOM1 APB Clock Enable"] + #[inline(always)] + pub fn sercom1_(&mut self) -> SERCOM1__W { + SERCOM1__W { w: self } + } + #[doc = "Bit 3 - SERCOM2 APB Clock Enable"] + #[inline(always)] + pub fn sercom2_(&mut self) -> SERCOM2__W { + SERCOM2__W { w: self } + } + #[doc = "Bit 4 - SERCOM3 APB Clock Enable"] + #[inline(always)] + pub fn sercom3_(&mut self) -> SERCOM3__W { + SERCOM3__W { w: self } + } + #[doc = "Bit 9 - TCC0 APB Clock Enable"] + #[inline(always)] + pub fn tcc0_(&mut self) -> TCC0__W { + TCC0__W { w: self } + } + #[doc = "Bit 10 - TCC1 APB Clock Enable"] + #[inline(always)] + pub fn tcc1_(&mut self) -> TCC1__W { + TCC1__W { w: self } + } + #[doc = "Bit 11 - TCC2 APB Clock Enable"] + #[inline(always)] + pub fn tcc2_(&mut self) -> TCC2__W { + TCC2__W { w: self } + } + #[doc = "Bit 12 - TC0 APB Clock Enable"] + #[inline(always)] + pub fn tc0_(&mut self) -> TC0__W { + TC0__W { w: self } + } + #[doc = "Bit 13 - TC1 APB Clock Enable"] + #[inline(always)] + pub fn tc1_(&mut self) -> TC1__W { + TC1__W { w: self } + } + #[doc = "Bit 14 - TC2 APB Clock Enable"] + #[inline(always)] + pub fn tc2_(&mut self) -> TC2__W { + TC2__W { w: self } + } + #[doc = "Bit 15 - TC3 APB Clock Enable"] + #[inline(always)] + pub fn tc3_(&mut self) -> TC3__W { + TC3__W { w: self } + } + #[doc = "Bit 16 - TC4 APB Clock Enable"] + #[inline(always)] + pub fn tc4_(&mut self) -> TC4__W { + TC4__W { w: self } + } + #[doc = "Bit 17 - ADC0 APB Clock Enable"] + #[inline(always)] + pub fn adc0_(&mut self) -> ADC0__W { + ADC0__W { w: self } + } + #[doc = "Bit 20 - AC APB Clock Enable"] + #[inline(always)] + pub fn ac_(&mut self) -> AC__W { + AC__W { w: self } + } + #[doc = "Bit 22 - PTC APB Clock Enable"] + #[inline(always)] + pub fn ptc_(&mut self) -> PTC__W { + PTC__W { w: self } + } + #[doc = "Bit 23 - CCL APB Clock Enable"] + #[inline(always)] + pub fn ccl_(&mut self) -> CCL__W { + CCL__W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "APBC Mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [apbcmask](index.html) module"] +pub struct APBCMASK_SPEC; +impl crate::RegisterSpec for APBCMASK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [apbcmask::R](R) reader structure"] +impl crate::Readable for APBCMASK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [apbcmask::W](W) writer structure"] +impl crate::Writable for APBCMASK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets APBCMASK to value 0"] +impl crate::Resettable for APBCMASK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/mclk/cpudiv.rs b/pac/atsamc20e/src/mclk/cpudiv.rs new file mode 100644 index 000000000000..a21fdae21357 --- /dev/null +++ b/pac/atsamc20e/src/mclk/cpudiv.rs @@ -0,0 +1,230 @@ +#[doc = "Register `CPUDIV` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CPUDIV` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "CPU Clock Division Factor\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CPUDIV_A { + #[doc = "1: Divide by 1"] + DIV1 = 1, + #[doc = "2: Divide by 2"] + DIV2 = 2, + #[doc = "4: Divide by 4"] + DIV4 = 4, + #[doc = "8: Divide by 8"] + DIV8 = 8, + #[doc = "16: Divide by 16"] + DIV16 = 16, + #[doc = "32: Divide by 32"] + DIV32 = 32, + #[doc = "64: Divide by 64"] + DIV64 = 64, + #[doc = "128: Divide by 128"] + DIV128 = 128, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CPUDIV_A) -> Self { + variant as _ + } +} +#[doc = "Field `CPUDIV` reader - CPU Clock Division Factor"] +pub struct CPUDIV_R(crate::FieldReader); +impl CPUDIV_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CPUDIV_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 1 => Some(CPUDIV_A::DIV1), + 2 => Some(CPUDIV_A::DIV2), + 4 => Some(CPUDIV_A::DIV4), + 8 => Some(CPUDIV_A::DIV8), + 16 => Some(CPUDIV_A::DIV16), + 32 => Some(CPUDIV_A::DIV32), + 64 => Some(CPUDIV_A::DIV64), + 128 => Some(CPUDIV_A::DIV128), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == CPUDIV_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == CPUDIV_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == CPUDIV_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == CPUDIV_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == CPUDIV_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == CPUDIV_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == CPUDIV_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == CPUDIV_A::DIV128 + } +} +impl core::ops::Deref for CPUDIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPUDIV` writer - CPU Clock Division Factor"] +pub struct CPUDIV_W<'a> { + w: &'a mut W, +} +impl<'a> CPUDIV_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CPUDIV_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Divide by 1"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV1) + } + #[doc = "Divide by 2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV2) + } + #[doc = "Divide by 4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV4) + } + #[doc = "Divide by 8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV8) + } + #[doc = "Divide by 16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV16) + } + #[doc = "Divide by 32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV32) + } + #[doc = "Divide by 64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV64) + } + #[doc = "Divide by 128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV128) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - CPU Clock Division Factor"] + #[inline(always)] + pub fn cpudiv(&self) -> CPUDIV_R { + CPUDIV_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - CPU Clock Division Factor"] + #[inline(always)] + pub fn cpudiv(&mut self) -> CPUDIV_W { + CPUDIV_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CPU Clock Division\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cpudiv](index.html) module"] +pub struct CPUDIV_SPEC; +impl crate::RegisterSpec for CPUDIV_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [cpudiv::R](R) reader structure"] +impl crate::Readable for CPUDIV_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cpudiv::W](W) writer structure"] +impl crate::Writable for CPUDIV_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CPUDIV to value 0x01"] +impl crate::Resettable for CPUDIV_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pac/atsamc20e/src/mclk/intenclr.rs b/pac/atsamc20e/src/mclk/intenclr.rs new file mode 100644 index 000000000000..14feb632dbb7 --- /dev/null +++ b/pac/atsamc20e/src/mclk/intenclr.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CKRDY` reader - Clock Ready Interrupt Enable"] +pub struct CKRDY_R(crate::FieldReader); +impl CKRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CKRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CKRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CKRDY` writer - Clock Ready Interrupt Enable"] +pub struct CKRDY_W<'a> { + w: &'a mut W, +} +impl<'a> CKRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Clock Ready Interrupt Enable"] + #[inline(always)] + pub fn ckrdy(&self) -> CKRDY_R { + CKRDY_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Clock Ready Interrupt Enable"] + #[inline(always)] + pub fn ckrdy(&mut self) -> CKRDY_W { + CKRDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/mclk/intenset.rs b/pac/atsamc20e/src/mclk/intenset.rs new file mode 100644 index 000000000000..f01fcc316d93 --- /dev/null +++ b/pac/atsamc20e/src/mclk/intenset.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CKRDY` reader - Clock Ready Interrupt Enable"] +pub struct CKRDY_R(crate::FieldReader); +impl CKRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CKRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CKRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CKRDY` writer - Clock Ready Interrupt Enable"] +pub struct CKRDY_W<'a> { + w: &'a mut W, +} +impl<'a> CKRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Clock Ready Interrupt Enable"] + #[inline(always)] + pub fn ckrdy(&self) -> CKRDY_R { + CKRDY_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Clock Ready Interrupt Enable"] + #[inline(always)] + pub fn ckrdy(&mut self) -> CKRDY_W { + CKRDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/mclk/intflag.rs b/pac/atsamc20e/src/mclk/intflag.rs new file mode 100644 index 000000000000..cf421d4ac61a --- /dev/null +++ b/pac/atsamc20e/src/mclk/intflag.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CKRDY` reader - Clock Ready"] +pub struct CKRDY_R(crate::FieldReader); +impl CKRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CKRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CKRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CKRDY` writer - Clock Ready"] +pub struct CKRDY_W<'a> { + w: &'a mut W, +} +impl<'a> CKRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Clock Ready"] + #[inline(always)] + pub fn ckrdy(&self) -> CKRDY_R { + CKRDY_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Clock Ready"] + #[inline(always)] + pub fn ckrdy(&mut self) -> CKRDY_W { + CKRDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0x01"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pac/atsamc20e/src/mtb.rs b/pac/atsamc20e/src/mtb.rs new file mode 100644 index 000000000000..01be005c0fb9 --- /dev/null +++ b/pac/atsamc20e/src/mtb.rs @@ -0,0 +1,158 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - MTB Position"] + pub position: crate::Reg, + #[doc = "0x04 - MTB Master"] + pub master: crate::Reg, + #[doc = "0x08 - MTB Flow"] + pub flow: crate::Reg, + #[doc = "0x0c - MTB Base"] + pub base: crate::Reg, + _reserved4: [u8; 0x0ef0], + #[doc = "0xf00 - MTB Integration Mode Control"] + pub itctrl: crate::Reg, + _reserved5: [u8; 0x9c], + #[doc = "0xfa0 - MTB Claim Set"] + pub claimset: crate::Reg, + #[doc = "0xfa4 - MTB Claim Clear"] + pub claimclr: crate::Reg, + _reserved7: [u8; 0x08], + #[doc = "0xfb0 - MTB Lock Access"] + pub lockaccess: crate::Reg, + #[doc = "0xfb4 - MTB Lock Status"] + pub lockstatus: crate::Reg, + #[doc = "0xfb8 - MTB Authentication Status"] + pub authstatus: crate::Reg, + #[doc = "0xfbc - MTB Device Architecture"] + pub devarch: crate::Reg, + _reserved11: [u8; 0x08], + #[doc = "0xfc8 - MTB Device Configuration"] + pub devid: crate::Reg, + #[doc = "0xfcc - MTB Device Type"] + pub devtype: crate::Reg, + #[doc = "0xfd0 - Peripheral Identification 4"] + pub pid4: crate::Reg, + #[doc = "0xfd4 - Peripheral Identification 5"] + pub pid5: crate::Reg, + #[doc = "0xfd8 - Peripheral Identification 6"] + pub pid6: crate::Reg, + #[doc = "0xfdc - Peripheral Identification 7"] + pub pid7: crate::Reg, + #[doc = "0xfe0 - Peripheral Identification 0"] + pub pid0: crate::Reg, + #[doc = "0xfe4 - Peripheral Identification 1"] + pub pid1: crate::Reg, + #[doc = "0xfe8 - Peripheral Identification 2"] + pub pid2: crate::Reg, + #[doc = "0xfec - Peripheral Identification 3"] + pub pid3: crate::Reg, + #[doc = "0xff0 - Component Identification 0"] + pub cid0: crate::Reg, + #[doc = "0xff4 - Component Identification 1"] + pub cid1: crate::Reg, + #[doc = "0xff8 - Component Identification 2"] + pub cid2: crate::Reg, + #[doc = "0xffc - Component Identification 3"] + pub cid3: crate::Reg, +} +#[doc = "POSITION register accessor: an alias for `Reg`"] +pub type POSITION = crate::Reg; +#[doc = "MTB Position"] +pub mod position; +#[doc = "MASTER register accessor: an alias for `Reg`"] +pub type MASTER = crate::Reg; +#[doc = "MTB Master"] +pub mod master; +#[doc = "FLOW register accessor: an alias for `Reg`"] +pub type FLOW = crate::Reg; +#[doc = "MTB Flow"] +pub mod flow; +#[doc = "BASE register accessor: an alias for `Reg`"] +pub type BASE = crate::Reg; +#[doc = "MTB Base"] +pub mod base; +#[doc = "ITCTRL register accessor: an alias for `Reg`"] +pub type ITCTRL = crate::Reg; +#[doc = "MTB Integration Mode Control"] +pub mod itctrl; +#[doc = "CLAIMSET register accessor: an alias for `Reg`"] +pub type CLAIMSET = crate::Reg; +#[doc = "MTB Claim Set"] +pub mod claimset; +#[doc = "CLAIMCLR register accessor: an alias for `Reg`"] +pub type CLAIMCLR = crate::Reg; +#[doc = "MTB Claim Clear"] +pub mod claimclr; +#[doc = "LOCKACCESS register accessor: an alias for `Reg`"] +pub type LOCKACCESS = crate::Reg; +#[doc = "MTB Lock Access"] +pub mod lockaccess; +#[doc = "LOCKSTATUS register accessor: an alias for `Reg`"] +pub type LOCKSTATUS = crate::Reg; +#[doc = "MTB Lock Status"] +pub mod lockstatus; +#[doc = "AUTHSTATUS register accessor: an alias for `Reg`"] +pub type AUTHSTATUS = crate::Reg; +#[doc = "MTB Authentication Status"] +pub mod authstatus; +#[doc = "DEVARCH register accessor: an alias for `Reg`"] +pub type DEVARCH = crate::Reg; +#[doc = "MTB Device Architecture"] +pub mod devarch; +#[doc = "DEVID register accessor: an alias for `Reg`"] +pub type DEVID = crate::Reg; +#[doc = "MTB Device Configuration"] +pub mod devid; +#[doc = "DEVTYPE register accessor: an alias for `Reg`"] +pub type DEVTYPE = crate::Reg; +#[doc = "MTB Device Type"] +pub mod devtype; +#[doc = "PID4 register accessor: an alias for `Reg`"] +pub type PID4 = crate::Reg; +#[doc = "Peripheral Identification 4"] +pub mod pid4; +#[doc = "PID5 register accessor: an alias for `Reg`"] +pub type PID5 = crate::Reg; +#[doc = "Peripheral Identification 5"] +pub mod pid5; +#[doc = "PID6 register accessor: an alias for `Reg`"] +pub type PID6 = crate::Reg; +#[doc = "Peripheral Identification 6"] +pub mod pid6; +#[doc = "PID7 register accessor: an alias for `Reg`"] +pub type PID7 = crate::Reg; +#[doc = "Peripheral Identification 7"] +pub mod pid7; +#[doc = "PID0 register accessor: an alias for `Reg`"] +pub type PID0 = crate::Reg; +#[doc = "Peripheral Identification 0"] +pub mod pid0; +#[doc = "PID1 register accessor: an alias for `Reg`"] +pub type PID1 = crate::Reg; +#[doc = "Peripheral Identification 1"] +pub mod pid1; +#[doc = "PID2 register accessor: an alias for `Reg`"] +pub type PID2 = crate::Reg; +#[doc = "Peripheral Identification 2"] +pub mod pid2; +#[doc = "PID3 register accessor: an alias for `Reg`"] +pub type PID3 = crate::Reg; +#[doc = "Peripheral Identification 3"] +pub mod pid3; +#[doc = "CID0 register accessor: an alias for `Reg`"] +pub type CID0 = crate::Reg; +#[doc = "Component Identification 0"] +pub mod cid0; +#[doc = "CID1 register accessor: an alias for `Reg`"] +pub type CID1 = crate::Reg; +#[doc = "Component Identification 1"] +pub mod cid1; +#[doc = "CID2 register accessor: an alias for `Reg`"] +pub type CID2 = crate::Reg; +#[doc = "Component Identification 2"] +pub mod cid2; +#[doc = "CID3 register accessor: an alias for `Reg`"] +pub type CID3 = crate::Reg; +#[doc = "Component Identification 3"] +pub mod cid3; diff --git a/pac/atsamc20e/src/mtb/authstatus.rs b/pac/atsamc20e/src/mtb/authstatus.rs new file mode 100644 index 000000000000..6fe441e0554d --- /dev/null +++ b/pac/atsamc20e/src/mtb/authstatus.rs @@ -0,0 +1,31 @@ +#[doc = "Register `AUTHSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "MTB Authentication Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [authstatus](index.html) module"] +pub struct AUTHSTATUS_SPEC; +impl crate::RegisterSpec for AUTHSTATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [authstatus::R](R) reader structure"] +impl crate::Readable for AUTHSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets AUTHSTATUS to value 0"] +impl crate::Resettable for AUTHSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/mtb/base.rs b/pac/atsamc20e/src/mtb/base.rs new file mode 100644 index 000000000000..f59b5a97a398 --- /dev/null +++ b/pac/atsamc20e/src/mtb/base.rs @@ -0,0 +1,31 @@ +#[doc = "Register `BASE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "MTB Base\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [base](index.html) module"] +pub struct BASE_SPEC; +impl crate::RegisterSpec for BASE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [base::R](R) reader structure"] +impl crate::Readable for BASE_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets BASE to value 0"] +impl crate::Resettable for BASE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/mtb/cid0.rs b/pac/atsamc20e/src/mtb/cid0.rs new file mode 100644 index 000000000000..e03bd35fa470 --- /dev/null +++ b/pac/atsamc20e/src/mtb/cid0.rs @@ -0,0 +1,31 @@ +#[doc = "Register `CID0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Component Identification 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid0](index.html) module"] +pub struct CID0_SPEC; +impl crate::RegisterSpec for CID0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid0::R](R) reader structure"] +impl crate::Readable for CID0_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID0 to value 0"] +impl crate::Resettable for CID0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/mtb/cid1.rs b/pac/atsamc20e/src/mtb/cid1.rs new file mode 100644 index 000000000000..1cafc8e0fb9a --- /dev/null +++ b/pac/atsamc20e/src/mtb/cid1.rs @@ -0,0 +1,31 @@ +#[doc = "Register `CID1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Component Identification 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid1](index.html) module"] +pub struct CID1_SPEC; +impl crate::RegisterSpec for CID1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid1::R](R) reader structure"] +impl crate::Readable for CID1_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID1 to value 0"] +impl crate::Resettable for CID1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/mtb/cid2.rs b/pac/atsamc20e/src/mtb/cid2.rs new file mode 100644 index 000000000000..6a91e4e23206 --- /dev/null +++ b/pac/atsamc20e/src/mtb/cid2.rs @@ -0,0 +1,31 @@ +#[doc = "Register `CID2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Component Identification 2\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid2](index.html) module"] +pub struct CID2_SPEC; +impl crate::RegisterSpec for CID2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid2::R](R) reader structure"] +impl crate::Readable for CID2_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID2 to value 0"] +impl crate::Resettable for CID2_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/mtb/cid3.rs b/pac/atsamc20e/src/mtb/cid3.rs new file mode 100644 index 000000000000..726290f4ffed --- /dev/null +++ b/pac/atsamc20e/src/mtb/cid3.rs @@ -0,0 +1,31 @@ +#[doc = "Register `CID3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Component Identification 3\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid3](index.html) module"] +pub struct CID3_SPEC; +impl crate::RegisterSpec for CID3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid3::R](R) reader structure"] +impl crate::Readable for CID3_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID3 to value 0"] +impl crate::Resettable for CID3_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/mtb/claimclr.rs b/pac/atsamc20e/src/mtb/claimclr.rs new file mode 100644 index 000000000000..7d0fa5d487b2 --- /dev/null +++ b/pac/atsamc20e/src/mtb/claimclr.rs @@ -0,0 +1,64 @@ +#[doc = "Register `CLAIMCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CLAIMCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MTB Claim Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [claimclr](index.html) module"] +pub struct CLAIMCLR_SPEC; +impl crate::RegisterSpec for CLAIMCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [claimclr::R](R) reader structure"] +impl crate::Readable for CLAIMCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [claimclr::W](W) writer structure"] +impl crate::Writable for CLAIMCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CLAIMCLR to value 0"] +impl crate::Resettable for CLAIMCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/mtb/claimset.rs b/pac/atsamc20e/src/mtb/claimset.rs new file mode 100644 index 000000000000..d5e8ffaa4846 --- /dev/null +++ b/pac/atsamc20e/src/mtb/claimset.rs @@ -0,0 +1,64 @@ +#[doc = "Register `CLAIMSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CLAIMSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MTB Claim Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [claimset](index.html) module"] +pub struct CLAIMSET_SPEC; +impl crate::RegisterSpec for CLAIMSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [claimset::R](R) reader structure"] +impl crate::Readable for CLAIMSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [claimset::W](W) writer structure"] +impl crate::Writable for CLAIMSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CLAIMSET to value 0"] +impl crate::Resettable for CLAIMSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/mtb/devarch.rs b/pac/atsamc20e/src/mtb/devarch.rs new file mode 100644 index 000000000000..b79480753d5e --- /dev/null +++ b/pac/atsamc20e/src/mtb/devarch.rs @@ -0,0 +1,31 @@ +#[doc = "Register `DEVARCH` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "MTB Device Architecture\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [devarch](index.html) module"] +pub struct DEVARCH_SPEC; +impl crate::RegisterSpec for DEVARCH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [devarch::R](R) reader structure"] +impl crate::Readable for DEVARCH_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DEVARCH to value 0"] +impl crate::Resettable for DEVARCH_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/mtb/devid.rs b/pac/atsamc20e/src/mtb/devid.rs new file mode 100644 index 000000000000..21c15d952032 --- /dev/null +++ b/pac/atsamc20e/src/mtb/devid.rs @@ -0,0 +1,31 @@ +#[doc = "Register `DEVID` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "MTB Device Configuration\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [devid](index.html) module"] +pub struct DEVID_SPEC; +impl crate::RegisterSpec for DEVID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [devid::R](R) reader structure"] +impl crate::Readable for DEVID_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DEVID to value 0"] +impl crate::Resettable for DEVID_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/mtb/devtype.rs b/pac/atsamc20e/src/mtb/devtype.rs new file mode 100644 index 000000000000..c00d66b98a2f --- /dev/null +++ b/pac/atsamc20e/src/mtb/devtype.rs @@ -0,0 +1,31 @@ +#[doc = "Register `DEVTYPE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "MTB Device Type\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [devtype](index.html) module"] +pub struct DEVTYPE_SPEC; +impl crate::RegisterSpec for DEVTYPE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [devtype::R](R) reader structure"] +impl crate::Readable for DEVTYPE_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DEVTYPE to value 0"] +impl crate::Resettable for DEVTYPE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/mtb/flow.rs b/pac/atsamc20e/src/mtb/flow.rs new file mode 100644 index 000000000000..1b94efdb89b8 --- /dev/null +++ b/pac/atsamc20e/src/mtb/flow.rs @@ -0,0 +1,197 @@ +#[doc = "Register `FLOW` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FLOW` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `AUTOSTOP` reader - Auto Stop Tracing"] +pub struct AUTOSTOP_R(crate::FieldReader); +impl AUTOSTOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AUTOSTOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AUTOSTOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AUTOSTOP` writer - Auto Stop Tracing"] +pub struct AUTOSTOP_W<'a> { + w: &'a mut W, +} +impl<'a> AUTOSTOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `AUTOHALT` reader - Auto Halt Request"] +pub struct AUTOHALT_R(crate::FieldReader); +impl AUTOHALT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AUTOHALT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AUTOHALT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AUTOHALT` writer - Auto Halt Request"] +pub struct AUTOHALT_W<'a> { + w: &'a mut W, +} +impl<'a> AUTOHALT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WATERMARK` reader - Watermark value"] +pub struct WATERMARK_R(crate::FieldReader); +impl WATERMARK_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + WATERMARK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WATERMARK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WATERMARK` writer - Watermark value"] +pub struct WATERMARK_W<'a> { + w: &'a mut W, +} +impl<'a> WATERMARK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1fff_ffff << 3)) | ((value as u32 & 0x1fff_ffff) << 3); + self.w + } +} +impl R { + #[doc = "Bit 0 - Auto Stop Tracing"] + #[inline(always)] + pub fn autostop(&self) -> AUTOSTOP_R { + AUTOSTOP_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Auto Halt Request"] + #[inline(always)] + pub fn autohalt(&self) -> AUTOHALT_R { + AUTOHALT_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 3:31 - Watermark value"] + #[inline(always)] + pub fn watermark(&self) -> WATERMARK_R { + WATERMARK_R::new(((self.bits >> 3) & 0x1fff_ffff) as u32) + } +} +impl W { + #[doc = "Bit 0 - Auto Stop Tracing"] + #[inline(always)] + pub fn autostop(&mut self) -> AUTOSTOP_W { + AUTOSTOP_W { w: self } + } + #[doc = "Bit 1 - Auto Halt Request"] + #[inline(always)] + pub fn autohalt(&mut self) -> AUTOHALT_W { + AUTOHALT_W { w: self } + } + #[doc = "Bits 3:31 - Watermark value"] + #[inline(always)] + pub fn watermark(&mut self) -> WATERMARK_W { + WATERMARK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MTB Flow\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [flow](index.html) module"] +pub struct FLOW_SPEC; +impl crate::RegisterSpec for FLOW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [flow::R](R) reader structure"] +impl crate::Readable for FLOW_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [flow::W](W) writer structure"] +impl crate::Writable for FLOW_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets FLOW to value 0"] +impl crate::Resettable for FLOW_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/mtb/itctrl.rs b/pac/atsamc20e/src/mtb/itctrl.rs new file mode 100644 index 000000000000..a48364e0b062 --- /dev/null +++ b/pac/atsamc20e/src/mtb/itctrl.rs @@ -0,0 +1,64 @@ +#[doc = "Register `ITCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ITCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MTB Integration Mode Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [itctrl](index.html) module"] +pub struct ITCTRL_SPEC; +impl crate::RegisterSpec for ITCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [itctrl::R](R) reader structure"] +impl crate::Readable for ITCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [itctrl::W](W) writer structure"] +impl crate::Writable for ITCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ITCTRL to value 0"] +impl crate::Resettable for ITCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/mtb/lockaccess.rs b/pac/atsamc20e/src/mtb/lockaccess.rs new file mode 100644 index 000000000000..0400690beade --- /dev/null +++ b/pac/atsamc20e/src/mtb/lockaccess.rs @@ -0,0 +1,64 @@ +#[doc = "Register `LOCKACCESS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `LOCKACCESS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MTB Lock Access\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lockaccess](index.html) module"] +pub struct LOCKACCESS_SPEC; +impl crate::RegisterSpec for LOCKACCESS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [lockaccess::R](R) reader structure"] +impl crate::Readable for LOCKACCESS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [lockaccess::W](W) writer structure"] +impl crate::Writable for LOCKACCESS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets LOCKACCESS to value 0"] +impl crate::Resettable for LOCKACCESS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/mtb/lockstatus.rs b/pac/atsamc20e/src/mtb/lockstatus.rs new file mode 100644 index 000000000000..0c68410c6944 --- /dev/null +++ b/pac/atsamc20e/src/mtb/lockstatus.rs @@ -0,0 +1,31 @@ +#[doc = "Register `LOCKSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "MTB Lock Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lockstatus](index.html) module"] +pub struct LOCKSTATUS_SPEC; +impl crate::RegisterSpec for LOCKSTATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [lockstatus::R](R) reader structure"] +impl crate::Readable for LOCKSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets LOCKSTATUS to value 0"] +impl crate::Resettable for LOCKSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/mtb/master.rs b/pac/atsamc20e/src/mtb/master.rs new file mode 100644 index 000000000000..0190ca1ce909 --- /dev/null +++ b/pac/atsamc20e/src/mtb/master.rs @@ -0,0 +1,385 @@ +#[doc = "Register `MASTER` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MASTER` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MASK` reader - Maximum Value of the Trace Buffer in SRAM"] +pub struct MASK_R(crate::FieldReader); +impl MASK_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MASK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MASK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MASK` writer - Maximum Value of the Trace Buffer in SRAM"] +pub struct MASK_W<'a> { + w: &'a mut W, +} +impl<'a> MASK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f); + self.w + } +} +#[doc = "Field `TSTARTEN` reader - Trace Start Input Enable"] +pub struct TSTARTEN_R(crate::FieldReader); +impl TSTARTEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSTARTEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSTARTEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSTARTEN` writer - Trace Start Input Enable"] +pub struct TSTARTEN_W<'a> { + w: &'a mut W, +} +impl<'a> TSTARTEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `TSTOPEN` reader - Trace Stop Input Enable"] +pub struct TSTOPEN_R(crate::FieldReader); +impl TSTOPEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSTOPEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSTOPEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSTOPEN` writer - Trace Stop Input Enable"] +pub struct TSTOPEN_W<'a> { + w: &'a mut W, +} +impl<'a> TSTOPEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `SFRWPRIV` reader - Special Function Register Write Privilege"] +pub struct SFRWPRIV_R(crate::FieldReader); +impl SFRWPRIV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SFRWPRIV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SFRWPRIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SFRWPRIV` writer - Special Function Register Write Privilege"] +pub struct SFRWPRIV_W<'a> { + w: &'a mut W, +} +impl<'a> SFRWPRIV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `RAMPRIV` reader - SRAM Privilege"] +pub struct RAMPRIV_R(crate::FieldReader); +impl RAMPRIV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RAMPRIV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RAMPRIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RAMPRIV` writer - SRAM Privilege"] +pub struct RAMPRIV_W<'a> { + w: &'a mut W, +} +impl<'a> RAMPRIV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `HALTREQ` reader - Halt Request"] +pub struct HALTREQ_R(crate::FieldReader); +impl HALTREQ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HALTREQ_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HALTREQ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HALTREQ` writer - Halt Request"] +pub struct HALTREQ_W<'a> { + w: &'a mut W, +} +impl<'a> HALTREQ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `EN` reader - Main Trace Enable"] +pub struct EN_R(crate::FieldReader); +impl EN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EN` writer - Main Trace Enable"] +pub struct EN_W<'a> { + w: &'a mut W, +} +impl<'a> EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Maximum Value of the Trace Buffer in SRAM"] + #[inline(always)] + pub fn mask(&self) -> MASK_R { + MASK_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bit 5 - Trace Start Input Enable"] + #[inline(always)] + pub fn tstarten(&self) -> TSTARTEN_R { + TSTARTEN_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Trace Stop Input Enable"] + #[inline(always)] + pub fn tstopen(&self) -> TSTOPEN_R { + TSTOPEN_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Special Function Register Write Privilege"] + #[inline(always)] + pub fn sfrwpriv(&self) -> SFRWPRIV_R { + SFRWPRIV_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - SRAM Privilege"] + #[inline(always)] + pub fn rampriv(&self) -> RAMPRIV_R { + RAMPRIV_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Halt Request"] + #[inline(always)] + pub fn haltreq(&self) -> HALTREQ_R { + HALTREQ_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 31 - Main Trace Enable"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Maximum Value of the Trace Buffer in SRAM"] + #[inline(always)] + pub fn mask(&mut self) -> MASK_W { + MASK_W { w: self } + } + #[doc = "Bit 5 - Trace Start Input Enable"] + #[inline(always)] + pub fn tstarten(&mut self) -> TSTARTEN_W { + TSTARTEN_W { w: self } + } + #[doc = "Bit 6 - Trace Stop Input Enable"] + #[inline(always)] + pub fn tstopen(&mut self) -> TSTOPEN_W { + TSTOPEN_W { w: self } + } + #[doc = "Bit 7 - Special Function Register Write Privilege"] + #[inline(always)] + pub fn sfrwpriv(&mut self) -> SFRWPRIV_W { + SFRWPRIV_W { w: self } + } + #[doc = "Bit 8 - SRAM Privilege"] + #[inline(always)] + pub fn rampriv(&mut self) -> RAMPRIV_W { + RAMPRIV_W { w: self } + } + #[doc = "Bit 9 - Halt Request"] + #[inline(always)] + pub fn haltreq(&mut self) -> HALTREQ_W { + HALTREQ_W { w: self } + } + #[doc = "Bit 31 - Main Trace Enable"] + #[inline(always)] + pub fn en(&mut self) -> EN_W { + EN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MTB Master\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [master](index.html) module"] +pub struct MASTER_SPEC; +impl crate::RegisterSpec for MASTER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [master::R](R) reader structure"] +impl crate::Readable for MASTER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [master::W](W) writer structure"] +impl crate::Writable for MASTER_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets MASTER to value 0"] +impl crate::Resettable for MASTER_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/mtb/pid0.rs b/pac/atsamc20e/src/mtb/pid0.rs new file mode 100644 index 000000000000..0a7183189fe5 --- /dev/null +++ b/pac/atsamc20e/src/mtb/pid0.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid0](index.html) module"] +pub struct PID0_SPEC; +impl crate::RegisterSpec for PID0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid0::R](R) reader structure"] +impl crate::Readable for PID0_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID0 to value 0"] +impl crate::Resettable for PID0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/mtb/pid1.rs b/pac/atsamc20e/src/mtb/pid1.rs new file mode 100644 index 000000000000..7d6381917f5d --- /dev/null +++ b/pac/atsamc20e/src/mtb/pid1.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid1](index.html) module"] +pub struct PID1_SPEC; +impl crate::RegisterSpec for PID1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid1::R](R) reader structure"] +impl crate::Readable for PID1_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID1 to value 0"] +impl crate::Resettable for PID1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/mtb/pid2.rs b/pac/atsamc20e/src/mtb/pid2.rs new file mode 100644 index 000000000000..74c230346b4c --- /dev/null +++ b/pac/atsamc20e/src/mtb/pid2.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 2\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid2](index.html) module"] +pub struct PID2_SPEC; +impl crate::RegisterSpec for PID2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid2::R](R) reader structure"] +impl crate::Readable for PID2_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID2 to value 0"] +impl crate::Resettable for PID2_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/mtb/pid3.rs b/pac/atsamc20e/src/mtb/pid3.rs new file mode 100644 index 000000000000..e9e922aa2f21 --- /dev/null +++ b/pac/atsamc20e/src/mtb/pid3.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 3\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid3](index.html) module"] +pub struct PID3_SPEC; +impl crate::RegisterSpec for PID3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid3::R](R) reader structure"] +impl crate::Readable for PID3_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID3 to value 0"] +impl crate::Resettable for PID3_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/mtb/pid4.rs b/pac/atsamc20e/src/mtb/pid4.rs new file mode 100644 index 000000000000..89074d3c2692 --- /dev/null +++ b/pac/atsamc20e/src/mtb/pid4.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID4` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 4\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid4](index.html) module"] +pub struct PID4_SPEC; +impl crate::RegisterSpec for PID4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid4::R](R) reader structure"] +impl crate::Readable for PID4_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID4 to value 0"] +impl crate::Resettable for PID4_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/mtb/pid5.rs b/pac/atsamc20e/src/mtb/pid5.rs new file mode 100644 index 000000000000..d343d4800b95 --- /dev/null +++ b/pac/atsamc20e/src/mtb/pid5.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID5` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 5\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid5](index.html) module"] +pub struct PID5_SPEC; +impl crate::RegisterSpec for PID5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid5::R](R) reader structure"] +impl crate::Readable for PID5_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID5 to value 0"] +impl crate::Resettable for PID5_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/mtb/pid6.rs b/pac/atsamc20e/src/mtb/pid6.rs new file mode 100644 index 000000000000..55cc2b8b5861 --- /dev/null +++ b/pac/atsamc20e/src/mtb/pid6.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID6` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 6\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid6](index.html) module"] +pub struct PID6_SPEC; +impl crate::RegisterSpec for PID6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid6::R](R) reader structure"] +impl crate::Readable for PID6_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID6 to value 0"] +impl crate::Resettable for PID6_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/mtb/pid7.rs b/pac/atsamc20e/src/mtb/pid7.rs new file mode 100644 index 000000000000..77664d4f2f95 --- /dev/null +++ b/pac/atsamc20e/src/mtb/pid7.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID7` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 7\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid7](index.html) module"] +pub struct PID7_SPEC; +impl crate::RegisterSpec for PID7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid7::R](R) reader structure"] +impl crate::Readable for PID7_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID7 to value 0"] +impl crate::Resettable for PID7_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/mtb/position.rs b/pac/atsamc20e/src/mtb/position.rs new file mode 100644 index 000000000000..4bab0425b142 --- /dev/null +++ b/pac/atsamc20e/src/mtb/position.rs @@ -0,0 +1,150 @@ +#[doc = "Register `POSITION` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `POSITION` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WRAP` reader - Pointer Value Wraps"] +pub struct WRAP_R(crate::FieldReader); +impl WRAP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WRAP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WRAP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WRAP` writer - Pointer Value Wraps"] +pub struct WRAP_W<'a> { + w: &'a mut W, +} +impl<'a> WRAP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `POINTER` reader - Trace Packet Location Pointer"] +pub struct POINTER_R(crate::FieldReader); +impl POINTER_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + POINTER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for POINTER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `POINTER` writer - Trace Packet Location Pointer"] +pub struct POINTER_W<'a> { + w: &'a mut W, +} +impl<'a> POINTER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1fff_ffff << 3)) | ((value as u32 & 0x1fff_ffff) << 3); + self.w + } +} +impl R { + #[doc = "Bit 2 - Pointer Value Wraps"] + #[inline(always)] + pub fn wrap(&self) -> WRAP_R { + WRAP_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 3:31 - Trace Packet Location Pointer"] + #[inline(always)] + pub fn pointer(&self) -> POINTER_R { + POINTER_R::new(((self.bits >> 3) & 0x1fff_ffff) as u32) + } +} +impl W { + #[doc = "Bit 2 - Pointer Value Wraps"] + #[inline(always)] + pub fn wrap(&mut self) -> WRAP_W { + WRAP_W { w: self } + } + #[doc = "Bits 3:31 - Trace Packet Location Pointer"] + #[inline(always)] + pub fn pointer(&mut self) -> POINTER_W { + POINTER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MTB Position\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [position](index.html) module"] +pub struct POSITION_SPEC; +impl crate::RegisterSpec for POSITION_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [position::R](R) reader structure"] +impl crate::Readable for POSITION_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [position::W](W) writer structure"] +impl crate::Writable for POSITION_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets POSITION to value 0"] +impl crate::Resettable for POSITION_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/nvmctrl.rs b/pac/atsamc20e/src/nvmctrl.rs new file mode 100644 index 000000000000..2c017caaef9c --- /dev/null +++ b/pac/atsamc20e/src/nvmctrl.rs @@ -0,0 +1,76 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + _reserved1: [u8; 0x02], + #[doc = "0x04 - Control B"] + pub ctrlb: crate::Reg, + #[doc = "0x08 - NVM Parameter"] + pub param: crate::Reg, + #[doc = "0x0c - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + _reserved4: [u8; 0x03], + #[doc = "0x10 - Interrupt Enable Set"] + pub intenset: crate::Reg, + _reserved5: [u8; 0x03], + #[doc = "0x14 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved6: [u8; 0x03], + #[doc = "0x18 - Status"] + pub status: crate::Reg, + _reserved7: [u8; 0x02], + #[doc = "0x1c - Address"] + pub addr: crate::Reg, + #[doc = "0x20 - Lock Section"] + pub lock: crate::Reg, + _reserved9: [u8; 0x06], + #[doc = "0x28 - Page Buffer Load Data 0"] + pub pbldata0: crate::Reg, + #[doc = "0x2c - Page Buffer Load Data 1"] + pub pbldata1: crate::Reg, +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "Control B"] +pub mod ctrlb; +#[doc = "PARAM register accessor: an alias for `Reg`"] +pub type PARAM = crate::Reg; +#[doc = "NVM Parameter"] +pub mod param; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "ADDR register accessor: an alias for `Reg`"] +pub type ADDR = crate::Reg; +#[doc = "Address"] +pub mod addr; +#[doc = "LOCK register accessor: an alias for `Reg`"] +pub type LOCK = crate::Reg; +#[doc = "Lock Section"] +pub mod lock; +#[doc = "PBLDATA0 register accessor: an alias for `Reg`"] +pub type PBLDATA0 = crate::Reg; +#[doc = "Page Buffer Load Data 0"] +pub mod pbldata0; +#[doc = "PBLDATA1 register accessor: an alias for `Reg`"] +pub type PBLDATA1 = crate::Reg; +#[doc = "Page Buffer Load Data 1"] +pub mod pbldata1; diff --git a/pac/atsamc20e/src/nvmctrl/addr.rs b/pac/atsamc20e/src/nvmctrl/addr.rs new file mode 100644 index 000000000000..74ed27736dac --- /dev/null +++ b/pac/atsamc20e/src/nvmctrl/addr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `ADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ADDR` reader - NVM Address"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - NVM Address"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x003f_ffff) | (value as u32 & 0x003f_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:21 - NVM Address"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new((self.bits & 0x003f_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:21 - NVM Address"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [addr](index.html) module"] +pub struct ADDR_SPEC; +impl crate::RegisterSpec for ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [addr::R](R) reader structure"] +impl crate::Readable for ADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [addr::W](W) writer structure"] +impl crate::Writable for ADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ADDR to value 0"] +impl crate::Resettable for ADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/nvmctrl/ctrla.rs b/pac/atsamc20e/src/nvmctrl/ctrla.rs new file mode 100644 index 000000000000..89f175771e4d --- /dev/null +++ b/pac/atsamc20e/src/nvmctrl/ctrla.rs @@ -0,0 +1,394 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "2: Erase Row - Erases the row addressed by the ADDR register."] + ER = 2, + #[doc = "4: Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register."] + WP = 4, + #[doc = "5: Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row."] + EAR = 5, + #[doc = "6: Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row."] + WAP = 6, + #[doc = "10: Security Flow Command"] + SF = 10, + #[doc = "15: Write lockbits"] + WL = 15, + #[doc = "26: RWW EEPROM area Erase Row - Erases the row addressed by the ADDR register."] + RWWEEER = 26, + #[doc = "28: RWW EEPROM Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register."] + RWWEEWP = 28, + #[doc = "64: Lock Region - Locks the region containing the address location in the ADDR register."] + LR = 64, + #[doc = "65: Unlock Region - Unlocks the region containing the address location in the ADDR register."] + UR = 65, + #[doc = "66: Sets the power reduction mode."] + SPRM = 66, + #[doc = "67: Clears the power reduction mode."] + CPRM = 67, + #[doc = "68: Page Buffer Clear - Clears the page buffer."] + PBC = 68, + #[doc = "69: Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row."] + SSB = 69, + #[doc = "70: Invalidate all cache lines."] + INVALL = 70, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 2 => Some(CMD_A::ER), + 4 => Some(CMD_A::WP), + 5 => Some(CMD_A::EAR), + 6 => Some(CMD_A::WAP), + 10 => Some(CMD_A::SF), + 15 => Some(CMD_A::WL), + 26 => Some(CMD_A::RWWEEER), + 28 => Some(CMD_A::RWWEEWP), + 64 => Some(CMD_A::LR), + 65 => Some(CMD_A::UR), + 66 => Some(CMD_A::SPRM), + 67 => Some(CMD_A::CPRM), + 68 => Some(CMD_A::PBC), + 69 => Some(CMD_A::SSB), + 70 => Some(CMD_A::INVALL), + _ => None, + } + } + #[doc = "Checks if the value of the field is `ER`"] + #[inline(always)] + pub fn is_er(&self) -> bool { + **self == CMD_A::ER + } + #[doc = "Checks if the value of the field is `WP`"] + #[inline(always)] + pub fn is_wp(&self) -> bool { + **self == CMD_A::WP + } + #[doc = "Checks if the value of the field is `EAR`"] + #[inline(always)] + pub fn is_ear(&self) -> bool { + **self == CMD_A::EAR + } + #[doc = "Checks if the value of the field is `WAP`"] + #[inline(always)] + pub fn is_wap(&self) -> bool { + **self == CMD_A::WAP + } + #[doc = "Checks if the value of the field is `SF`"] + #[inline(always)] + pub fn is_sf(&self) -> bool { + **self == CMD_A::SF + } + #[doc = "Checks if the value of the field is `WL`"] + #[inline(always)] + pub fn is_wl(&self) -> bool { + **self == CMD_A::WL + } + #[doc = "Checks if the value of the field is `RWWEEER`"] + #[inline(always)] + pub fn is_rwweeer(&self) -> bool { + **self == CMD_A::RWWEEER + } + #[doc = "Checks if the value of the field is `RWWEEWP`"] + #[inline(always)] + pub fn is_rwweewp(&self) -> bool { + **self == CMD_A::RWWEEWP + } + #[doc = "Checks if the value of the field is `LR`"] + #[inline(always)] + pub fn is_lr(&self) -> bool { + **self == CMD_A::LR + } + #[doc = "Checks if the value of the field is `UR`"] + #[inline(always)] + pub fn is_ur(&self) -> bool { + **self == CMD_A::UR + } + #[doc = "Checks if the value of the field is `SPRM`"] + #[inline(always)] + pub fn is_sprm(&self) -> bool { + **self == CMD_A::SPRM + } + #[doc = "Checks if the value of the field is `CPRM`"] + #[inline(always)] + pub fn is_cprm(&self) -> bool { + **self == CMD_A::CPRM + } + #[doc = "Checks if the value of the field is `PBC`"] + #[inline(always)] + pub fn is_pbc(&self) -> bool { + **self == CMD_A::PBC + } + #[doc = "Checks if the value of the field is `SSB`"] + #[inline(always)] + pub fn is_ssb(&self) -> bool { + **self == CMD_A::SSB + } + #[doc = "Checks if the value of the field is `INVALL`"] + #[inline(always)] + pub fn is_invall(&self) -> bool { + **self == CMD_A::INVALL + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Erase Row - Erases the row addressed by the ADDR register."] + #[inline(always)] + pub fn er(self) -> &'a mut W { + self.variant(CMD_A::ER) + } + #[doc = "Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register."] + #[inline(always)] + pub fn wp(self) -> &'a mut W { + self.variant(CMD_A::WP) + } + #[doc = "Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row."] + #[inline(always)] + pub fn ear(self) -> &'a mut W { + self.variant(CMD_A::EAR) + } + #[doc = "Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row."] + #[inline(always)] + pub fn wap(self) -> &'a mut W { + self.variant(CMD_A::WAP) + } + #[doc = "Security Flow Command"] + #[inline(always)] + pub fn sf(self) -> &'a mut W { + self.variant(CMD_A::SF) + } + #[doc = "Write lockbits"] + #[inline(always)] + pub fn wl(self) -> &'a mut W { + self.variant(CMD_A::WL) + } + #[doc = "RWW EEPROM area Erase Row - Erases the row addressed by the ADDR register."] + #[inline(always)] + pub fn rwweeer(self) -> &'a mut W { + self.variant(CMD_A::RWWEEER) + } + #[doc = "RWW EEPROM Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register."] + #[inline(always)] + pub fn rwweewp(self) -> &'a mut W { + self.variant(CMD_A::RWWEEWP) + } + #[doc = "Lock Region - Locks the region containing the address location in the ADDR register."] + #[inline(always)] + pub fn lr(self) -> &'a mut W { + self.variant(CMD_A::LR) + } + #[doc = "Unlock Region - Unlocks the region containing the address location in the ADDR register."] + #[inline(always)] + pub fn ur(self) -> &'a mut W { + self.variant(CMD_A::UR) + } + #[doc = "Sets the power reduction mode."] + #[inline(always)] + pub fn sprm(self) -> &'a mut W { + self.variant(CMD_A::SPRM) + } + #[doc = "Clears the power reduction mode."] + #[inline(always)] + pub fn cprm(self) -> &'a mut W { + self.variant(CMD_A::CPRM) + } + #[doc = "Page Buffer Clear - Clears the page buffer."] + #[inline(always)] + pub fn pbc(self) -> &'a mut W { + self.variant(CMD_A::PBC) + } + #[doc = "Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row."] + #[inline(always)] + pub fn ssb(self) -> &'a mut W { + self.variant(CMD_A::SSB) + } + #[doc = "Invalidate all cache lines."] + #[inline(always)] + pub fn invall(self) -> &'a mut W { + self.variant(CMD_A::INVALL) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x7f) | (value as u16 & 0x7f); + self.w + } +} +#[doc = "Command Execution\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMDEX_A { + #[doc = "165: Execution Key"] + KEY = 165, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMDEX_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMDEX` reader - Command Execution"] +pub struct CMDEX_R(crate::FieldReader); +impl CMDEX_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMDEX_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 165 => Some(CMDEX_A::KEY), + _ => None, + } + } + #[doc = "Checks if the value of the field is `KEY`"] + #[inline(always)] + pub fn is_key(&self) -> bool { + **self == CMDEX_A::KEY + } +} +impl core::ops::Deref for CMDEX_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMDEX` writer - Command Execution"] +pub struct CMDEX_W<'a> { + w: &'a mut W, +} +impl<'a> CMDEX_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMDEX_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Execution Key"] + #[inline(always)] + pub fn key(self) -> &'a mut W { + self.variant(CMDEX_A::KEY) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u16 & 0xff) << 8); + self.w + } +} +impl R { + #[doc = "Bits 0:6 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bits 8:15 - Command Execution"] + #[inline(always)] + pub fn cmdex(&self) -> CMDEX_R { + CMDEX_R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:6 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Bits 8:15 - Command Execution"] + #[inline(always)] + pub fn cmdex(&mut self) -> CMDEX_W { + CMDEX_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/nvmctrl/ctrlb.rs b/pac/atsamc20e/src/nvmctrl/ctrlb.rs new file mode 100644 index 000000000000..6162d0d4ade0 --- /dev/null +++ b/pac/atsamc20e/src/nvmctrl/ctrlb.rs @@ -0,0 +1,447 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "NVM Read Wait States\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum RWS_A { + #[doc = "0: Single Auto Wait State"] + SINGLE = 0, + #[doc = "1: Half Auto Wait State"] + HALF = 1, + #[doc = "2: Dual Auto Wait State"] + DUAL = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RWS_A) -> Self { + variant as _ + } +} +#[doc = "Field `RWS` reader - NVM Read Wait States"] +pub struct RWS_R(crate::FieldReader); +impl RWS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RWS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(RWS_A::SINGLE), + 1 => Some(RWS_A::HALF), + 2 => Some(RWS_A::DUAL), + _ => None, + } + } + #[doc = "Checks if the value of the field is `SINGLE`"] + #[inline(always)] + pub fn is_single(&self) -> bool { + **self == RWS_A::SINGLE + } + #[doc = "Checks if the value of the field is `HALF`"] + #[inline(always)] + pub fn is_half(&self) -> bool { + **self == RWS_A::HALF + } + #[doc = "Checks if the value of the field is `DUAL`"] + #[inline(always)] + pub fn is_dual(&self) -> bool { + **self == RWS_A::DUAL + } +} +impl core::ops::Deref for RWS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RWS` writer - NVM Read Wait States"] +pub struct RWS_W<'a> { + w: &'a mut W, +} +impl<'a> RWS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RWS_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Single Auto Wait State"] + #[inline(always)] + pub fn single(self) -> &'a mut W { + self.variant(RWS_A::SINGLE) + } + #[doc = "Half Auto Wait State"] + #[inline(always)] + pub fn half(self) -> &'a mut W { + self.variant(RWS_A::HALF) + } + #[doc = "Dual Auto Wait State"] + #[inline(always)] + pub fn dual(self) -> &'a mut W { + self.variant(RWS_A::DUAL) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 1)) | ((value as u32 & 0x0f) << 1); + self.w + } +} +#[doc = "Field `MANW` reader - Manual Write"] +pub struct MANW_R(crate::FieldReader); +impl MANW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MANW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MANW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MANW` writer - Manual Write"] +pub struct MANW_W<'a> { + w: &'a mut W, +} +impl<'a> MANW_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Power Reduction Mode during Sleep\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SLEEPPRM_A { + #[doc = "0: NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access."] + WAKEONACCESS = 0, + #[doc = "1: NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep."] + WAKEUPINSTANT = 1, + #[doc = "3: Auto power reduction disabled."] + DISABLED = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SLEEPPRM_A) -> Self { + variant as _ + } +} +#[doc = "Field `SLEEPPRM` reader - Power Reduction Mode during Sleep"] +pub struct SLEEPPRM_R(crate::FieldReader); +impl SLEEPPRM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SLEEPPRM_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SLEEPPRM_A::WAKEONACCESS), + 1 => Some(SLEEPPRM_A::WAKEUPINSTANT), + 3 => Some(SLEEPPRM_A::DISABLED), + _ => None, + } + } + #[doc = "Checks if the value of the field is `WAKEONACCESS`"] + #[inline(always)] + pub fn is_wakeonaccess(&self) -> bool { + **self == SLEEPPRM_A::WAKEONACCESS + } + #[doc = "Checks if the value of the field is `WAKEUPINSTANT`"] + #[inline(always)] + pub fn is_wakeupinstant(&self) -> bool { + **self == SLEEPPRM_A::WAKEUPINSTANT + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + **self == SLEEPPRM_A::DISABLED + } +} +impl core::ops::Deref for SLEEPPRM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLEEPPRM` writer - Power Reduction Mode during Sleep"] +pub struct SLEEPPRM_W<'a> { + w: &'a mut W, +} +impl<'a> SLEEPPRM_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SLEEPPRM_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access."] + #[inline(always)] + pub fn wakeonaccess(self) -> &'a mut W { + self.variant(SLEEPPRM_A::WAKEONACCESS) + } + #[doc = "NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep."] + #[inline(always)] + pub fn wakeupinstant(self) -> &'a mut W { + self.variant(SLEEPPRM_A::WAKEUPINSTANT) + } + #[doc = "Auto power reduction disabled."] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(SLEEPPRM_A::DISABLED) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 8)) | ((value as u32 & 0x03) << 8); + self.w + } +} +#[doc = "NVMCTRL Read Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum READMODE_A { + #[doc = "0: The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance."] + NO_MISS_PENALTY = 0, + #[doc = "1: Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time."] + LOW_POWER = 1, + #[doc = "2: The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings."] + DETERMINISTIC = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: READMODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `READMODE` reader - NVMCTRL Read Mode"] +pub struct READMODE_R(crate::FieldReader); +impl READMODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + READMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(READMODE_A::NO_MISS_PENALTY), + 1 => Some(READMODE_A::LOW_POWER), + 2 => Some(READMODE_A::DETERMINISTIC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NO_MISS_PENALTY`"] + #[inline(always)] + pub fn is_no_miss_penalty(&self) -> bool { + **self == READMODE_A::NO_MISS_PENALTY + } + #[doc = "Checks if the value of the field is `LOW_POWER`"] + #[inline(always)] + pub fn is_low_power(&self) -> bool { + **self == READMODE_A::LOW_POWER + } + #[doc = "Checks if the value of the field is `DETERMINISTIC`"] + #[inline(always)] + pub fn is_deterministic(&self) -> bool { + **self == READMODE_A::DETERMINISTIC + } +} +impl core::ops::Deref for READMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `READMODE` writer - NVMCTRL Read Mode"] +pub struct READMODE_W<'a> { + w: &'a mut W, +} +impl<'a> READMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: READMODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance."] + #[inline(always)] + pub fn no_miss_penalty(self) -> &'a mut W { + self.variant(READMODE_A::NO_MISS_PENALTY) + } + #[doc = "Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time."] + #[inline(always)] + pub fn low_power(self) -> &'a mut W { + self.variant(READMODE_A::LOW_POWER) + } + #[doc = "The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings."] + #[inline(always)] + pub fn deterministic(self) -> &'a mut W { + self.variant(READMODE_A::DETERMINISTIC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Field `CACHEDIS` reader - Cache Disable"] +pub struct CACHEDIS_R(crate::FieldReader); +impl CACHEDIS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CACHEDIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CACHEDIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CACHEDIS` writer - Cache Disable"] +pub struct CACHEDIS_W<'a> { + w: &'a mut W, +} +impl<'a> CACHEDIS_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 18)) | ((value as u32 & 0x03) << 18); + self.w + } +} +impl R { + #[doc = "Bits 1:4 - NVM Read Wait States"] + #[inline(always)] + pub fn rws(&self) -> RWS_R { + RWS_R::new(((self.bits >> 1) & 0x0f) as u8) + } + #[doc = "Bit 7 - Manual Write"] + #[inline(always)] + pub fn manw(&self) -> MANW_R { + MANW_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:9 - Power Reduction Mode during Sleep"] + #[inline(always)] + pub fn sleepprm(&self) -> SLEEPPRM_R { + SLEEPPRM_R::new(((self.bits >> 8) & 0x03) as u8) + } + #[doc = "Bits 16:17 - NVMCTRL Read Mode"] + #[inline(always)] + pub fn readmode(&self) -> READMODE_R { + READMODE_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bits 18:19 - Cache Disable"] + #[inline(always)] + pub fn cachedis(&self) -> CACHEDIS_R { + CACHEDIS_R::new(((self.bits >> 18) & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 1:4 - NVM Read Wait States"] + #[inline(always)] + pub fn rws(&mut self) -> RWS_W { + RWS_W { w: self } + } + #[doc = "Bit 7 - Manual Write"] + #[inline(always)] + pub fn manw(&mut self) -> MANW_W { + MANW_W { w: self } + } + #[doc = "Bits 8:9 - Power Reduction Mode during Sleep"] + #[inline(always)] + pub fn sleepprm(&mut self) -> SLEEPPRM_W { + SLEEPPRM_W { w: self } + } + #[doc = "Bits 16:17 - NVMCTRL Read Mode"] + #[inline(always)] + pub fn readmode(&mut self) -> READMODE_W { + READMODE_W { w: self } + } + #[doc = "Bits 18:19 - Cache Disable"] + #[inline(always)] + pub fn cachedis(&mut self) -> CACHEDIS_W { + CACHEDIS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0x80"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x80 + } +} diff --git a/pac/atsamc20e/src/nvmctrl/intenclr.rs b/pac/atsamc20e/src/nvmctrl/intenclr.rs new file mode 100644 index 000000000000..6e7db4b52c9d --- /dev/null +++ b/pac/atsamc20e/src/nvmctrl/intenclr.rs @@ -0,0 +1,160 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `READY` reader - NVM Ready Interrupt Enable"] +pub struct READY_R(crate::FieldReader); +impl READY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + READY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for READY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `READY` writer - NVM Ready Interrupt Enable"] +pub struct READY_W<'a> { + w: &'a mut W, +} +impl<'a> READY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERROR` reader - Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - NVM Ready Interrupt Enable"] + #[inline(always)] + pub fn ready(&self) -> READY_R { + READY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - NVM Ready Interrupt Enable"] + #[inline(always)] + pub fn ready(&mut self) -> READY_W { + READY_W { w: self } + } + #[doc = "Bit 1 - Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/nvmctrl/intenset.rs b/pac/atsamc20e/src/nvmctrl/intenset.rs new file mode 100644 index 000000000000..ba8698e86c3e --- /dev/null +++ b/pac/atsamc20e/src/nvmctrl/intenset.rs @@ -0,0 +1,160 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `READY` reader - NVM Ready Interrupt Enable"] +pub struct READY_R(crate::FieldReader); +impl READY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + READY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for READY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `READY` writer - NVM Ready Interrupt Enable"] +pub struct READY_W<'a> { + w: &'a mut W, +} +impl<'a> READY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERROR` reader - Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - NVM Ready Interrupt Enable"] + #[inline(always)] + pub fn ready(&self) -> READY_R { + READY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - NVM Ready Interrupt Enable"] + #[inline(always)] + pub fn ready(&mut self) -> READY_W { + READY_W { w: self } + } + #[doc = "Bit 1 - Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/nvmctrl/intflag.rs b/pac/atsamc20e/src/nvmctrl/intflag.rs new file mode 100644 index 000000000000..1b30cdddf25d --- /dev/null +++ b/pac/atsamc20e/src/nvmctrl/intflag.rs @@ -0,0 +1,160 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `READY` reader - NVM Ready"] +pub struct READY_R(crate::FieldReader); +impl READY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + READY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for READY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `READY` writer - NVM Ready"] +pub struct READY_W<'a> { + w: &'a mut W, +} +impl<'a> READY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERROR` reader - Error"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Error"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - NVM Ready"] + #[inline(always)] + pub fn ready(&self) -> READY_R { + READY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Error"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - NVM Ready"] + #[inline(always)] + pub fn ready(&mut self) -> READY_W { + READY_W { w: self } + } + #[doc = "Bit 1 - Error"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/nvmctrl/lock.rs b/pac/atsamc20e/src/nvmctrl/lock.rs new file mode 100644 index 000000000000..dbcf37a8107f --- /dev/null +++ b/pac/atsamc20e/src/nvmctrl/lock.rs @@ -0,0 +1,103 @@ +#[doc = "Register `LOCK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `LOCK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `LOCK` reader - Region Lock Bits"] +pub struct LOCK_R(crate::FieldReader); +impl LOCK_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + LOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LOCK` writer - Region Lock Bits"] +pub struct LOCK_W<'a> { + w: &'a mut W, +} +impl<'a> LOCK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Region Lock Bits"] + #[inline(always)] + pub fn lock(&self) -> LOCK_R { + LOCK_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Region Lock Bits"] + #[inline(always)] + pub fn lock(&mut self) -> LOCK_W { + LOCK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Lock Section\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lock](index.html) module"] +pub struct LOCK_SPEC; +impl crate::RegisterSpec for LOCK_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [lock::R](R) reader structure"] +impl crate::Readable for LOCK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [lock::W](W) writer structure"] +impl crate::Writable for LOCK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets LOCK to value 0"] +impl crate::Resettable for LOCK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/nvmctrl/param.rs b/pac/atsamc20e/src/nvmctrl/param.rs new file mode 100644 index 000000000000..d9197cf16de4 --- /dev/null +++ b/pac/atsamc20e/src/nvmctrl/param.rs @@ -0,0 +1,304 @@ +#[doc = "Register `PARAM` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PARAM` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `NVMP` reader - NVM Pages"] +pub struct NVMP_R(crate::FieldReader); +impl NVMP_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + NVMP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NVMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NVMP` writer - NVM Pages"] +pub struct NVMP_W<'a> { + w: &'a mut W, +} +impl<'a> NVMP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +#[doc = "Page Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PSZ_A { + #[doc = "0: 8 bytes"] + _8 = 0, + #[doc = "1: 16 bytes"] + _16 = 1, + #[doc = "2: 32 bytes"] + _32 = 2, + #[doc = "3: 64 bytes"] + _64 = 3, + #[doc = "4: 128 bytes"] + _128 = 4, + #[doc = "5: 256 bytes"] + _256 = 5, + #[doc = "6: 512 bytes"] + _512 = 6, + #[doc = "7: 1024 bytes"] + _1024 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PSZ_A) -> Self { + variant as _ + } +} +#[doc = "Field `PSZ` reader - Page Size"] +pub struct PSZ_R(crate::FieldReader); +impl PSZ_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PSZ_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PSZ_A { + match self.bits { + 0 => PSZ_A::_8, + 1 => PSZ_A::_16, + 2 => PSZ_A::_32, + 3 => PSZ_A::_64, + 4 => PSZ_A::_128, + 5 => PSZ_A::_256, + 6 => PSZ_A::_512, + 7 => PSZ_A::_1024, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `_8`"] + #[inline(always)] + pub fn is_8(&self) -> bool { + **self == PSZ_A::_8 + } + #[doc = "Checks if the value of the field is `_16`"] + #[inline(always)] + pub fn is_16(&self) -> bool { + **self == PSZ_A::_16 + } + #[doc = "Checks if the value of the field is `_32`"] + #[inline(always)] + pub fn is_32(&self) -> bool { + **self == PSZ_A::_32 + } + #[doc = "Checks if the value of the field is `_64`"] + #[inline(always)] + pub fn is_64(&self) -> bool { + **self == PSZ_A::_64 + } + #[doc = "Checks if the value of the field is `_128`"] + #[inline(always)] + pub fn is_128(&self) -> bool { + **self == PSZ_A::_128 + } + #[doc = "Checks if the value of the field is `_256`"] + #[inline(always)] + pub fn is_256(&self) -> bool { + **self == PSZ_A::_256 + } + #[doc = "Checks if the value of the field is `_512`"] + #[inline(always)] + pub fn is_512(&self) -> bool { + **self == PSZ_A::_512 + } + #[doc = "Checks if the value of the field is `_1024`"] + #[inline(always)] + pub fn is_1024(&self) -> bool { + **self == PSZ_A::_1024 + } +} +impl core::ops::Deref for PSZ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PSZ` writer - Page Size"] +pub struct PSZ_W<'a> { + w: &'a mut W, +} +impl<'a> PSZ_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PSZ_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "8 bytes"] + #[inline(always)] + pub fn _8(self) -> &'a mut W { + self.variant(PSZ_A::_8) + } + #[doc = "16 bytes"] + #[inline(always)] + pub fn _16(self) -> &'a mut W { + self.variant(PSZ_A::_16) + } + #[doc = "32 bytes"] + #[inline(always)] + pub fn _32(self) -> &'a mut W { + self.variant(PSZ_A::_32) + } + #[doc = "64 bytes"] + #[inline(always)] + pub fn _64(self) -> &'a mut W { + self.variant(PSZ_A::_64) + } + #[doc = "128 bytes"] + #[inline(always)] + pub fn _128(self) -> &'a mut W { + self.variant(PSZ_A::_128) + } + #[doc = "256 bytes"] + #[inline(always)] + pub fn _256(self) -> &'a mut W { + self.variant(PSZ_A::_256) + } + #[doc = "512 bytes"] + #[inline(always)] + pub fn _512(self) -> &'a mut W { + self.variant(PSZ_A::_512) + } + #[doc = "1024 bytes"] + #[inline(always)] + pub fn _1024(self) -> &'a mut W { + self.variant(PSZ_A::_1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 16)) | ((value as u32 & 0x07) << 16); + self.w + } +} +#[doc = "Field `RWWEEP` reader - RWW EEPROM Pages"] +pub struct RWWEEP_R(crate::FieldReader); +impl RWWEEP_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + RWWEEP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RWWEEP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RWWEEP` writer - RWW EEPROM Pages"] +pub struct RWWEEP_W<'a> { + w: &'a mut W, +} +impl<'a> RWWEEP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0fff << 20)) | ((value as u32 & 0x0fff) << 20); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - NVM Pages"] + #[inline(always)] + pub fn nvmp(&self) -> NVMP_R { + NVMP_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:18 - Page Size"] + #[inline(always)] + pub fn psz(&self) -> PSZ_R { + PSZ_R::new(((self.bits >> 16) & 0x07) as u8) + } + #[doc = "Bits 20:31 - RWW EEPROM Pages"] + #[inline(always)] + pub fn rwweep(&self) -> RWWEEP_R { + RWWEEP_R::new(((self.bits >> 20) & 0x0fff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - NVM Pages"] + #[inline(always)] + pub fn nvmp(&mut self) -> NVMP_W { + NVMP_W { w: self } + } + #[doc = "Bits 16:18 - Page Size"] + #[inline(always)] + pub fn psz(&mut self) -> PSZ_W { + PSZ_W { w: self } + } + #[doc = "Bits 20:31 - RWW EEPROM Pages"] + #[inline(always)] + pub fn rwweep(&mut self) -> RWWEEP_W { + RWWEEP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "NVM Parameter\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [param](index.html) module"] +pub struct PARAM_SPEC; +impl crate::RegisterSpec for PARAM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [param::R](R) reader structure"] +impl crate::Readable for PARAM_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [param::W](W) writer structure"] +impl crate::Writable for PARAM_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PARAM to value 0"] +impl crate::Resettable for PARAM_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/nvmctrl/pbldata0.rs b/pac/atsamc20e/src/nvmctrl/pbldata0.rs new file mode 100644 index 000000000000..ff2effaf4d89 --- /dev/null +++ b/pac/atsamc20e/src/nvmctrl/pbldata0.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PBLDATA0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Page Buffer Load Data 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pbldata0](index.html) module"] +pub struct PBLDATA0_SPEC; +impl crate::RegisterSpec for PBLDATA0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pbldata0::R](R) reader structure"] +impl crate::Readable for PBLDATA0_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PBLDATA0 to value 0"] +impl crate::Resettable for PBLDATA0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/nvmctrl/pbldata1.rs b/pac/atsamc20e/src/nvmctrl/pbldata1.rs new file mode 100644 index 000000000000..9fc6404691c5 --- /dev/null +++ b/pac/atsamc20e/src/nvmctrl/pbldata1.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PBLDATA1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Page Buffer Load Data 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pbldata1](index.html) module"] +pub struct PBLDATA1_SPEC; +impl crate::RegisterSpec for PBLDATA1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pbldata1::R](R) reader structure"] +impl crate::Readable for PBLDATA1_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PBLDATA1 to value 0"] +impl crate::Resettable for PBLDATA1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/nvmctrl/status.rs b/pac/atsamc20e/src/nvmctrl/status.rs new file mode 100644 index 000000000000..ce849015560e --- /dev/null +++ b/pac/atsamc20e/src/nvmctrl/status.rs @@ -0,0 +1,348 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PRM` reader - Power Reduction Mode"] +pub struct PRM_R(crate::FieldReader); +impl PRM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PRM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PRM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRM` writer - Power Reduction Mode"] +pub struct PRM_W<'a> { + w: &'a mut W, +} +impl<'a> PRM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `LOAD` reader - NVM Page Buffer Active Loading"] +pub struct LOAD_R(crate::FieldReader); +impl LOAD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LOAD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOAD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LOAD` writer - NVM Page Buffer Active Loading"] +pub struct LOAD_W<'a> { + w: &'a mut W, +} +impl<'a> LOAD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PROGE` reader - Programming Error Status"] +pub struct PROGE_R(crate::FieldReader); +impl PROGE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PROGE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PROGE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PROGE` writer - Programming Error Status"] +pub struct PROGE_W<'a> { + w: &'a mut W, +} +impl<'a> PROGE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `LOCKE` reader - Lock Error Status"] +pub struct LOCKE_R(crate::FieldReader); +impl LOCKE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LOCKE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOCKE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LOCKE` writer - Lock Error Status"] +pub struct LOCKE_W<'a> { + w: &'a mut W, +} +impl<'a> LOCKE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `NVME` reader - NVM Error"] +pub struct NVME_R(crate::FieldReader); +impl NVME_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NVME_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NVME_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NVME` writer - NVM Error"] +pub struct NVME_W<'a> { + w: &'a mut W, +} +impl<'a> NVME_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `SB` reader - Security Bit Status"] +pub struct SB_R(crate::FieldReader); +impl SB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SB` writer - Security Bit Status"] +pub struct SB_W<'a> { + w: &'a mut W, +} +impl<'a> SB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +impl R { + #[doc = "Bit 0 - Power Reduction Mode"] + #[inline(always)] + pub fn prm(&self) -> PRM_R { + PRM_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - NVM Page Buffer Active Loading"] + #[inline(always)] + pub fn load(&self) -> LOAD_R { + LOAD_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Programming Error Status"] + #[inline(always)] + pub fn proge(&self) -> PROGE_R { + PROGE_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Lock Error Status"] + #[inline(always)] + pub fn locke(&self) -> LOCKE_R { + LOCKE_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - NVM Error"] + #[inline(always)] + pub fn nvme(&self) -> NVME_R { + NVME_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 8 - Security Bit Status"] + #[inline(always)] + pub fn sb(&self) -> SB_R { + SB_R::new(((self.bits >> 8) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Power Reduction Mode"] + #[inline(always)] + pub fn prm(&mut self) -> PRM_W { + PRM_W { w: self } + } + #[doc = "Bit 1 - NVM Page Buffer Active Loading"] + #[inline(always)] + pub fn load(&mut self) -> LOAD_W { + LOAD_W { w: self } + } + #[doc = "Bit 2 - Programming Error Status"] + #[inline(always)] + pub fn proge(&mut self) -> PROGE_W { + PROGE_W { w: self } + } + #[doc = "Bit 3 - Lock Error Status"] + #[inline(always)] + pub fn locke(&mut self) -> LOCKE_W { + LOCKE_W { w: self } + } + #[doc = "Bit 4 - NVM Error"] + #[inline(always)] + pub fn nvme(&mut self) -> NVME_W { + NVME_W { w: self } + } + #[doc = "Bit 8 - Security Bit Status"] + #[inline(always)] + pub fn sb(&mut self) -> SB_W { + SB_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/osc32kctrl.rs b/pac/atsamc20e/src/osc32kctrl.rs new file mode 100644 index 000000000000..263cd2f61d59 --- /dev/null +++ b/pac/atsamc20e/src/osc32kctrl.rs @@ -0,0 +1,64 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x04 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x08 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x0c - Power and Clocks Status"] + pub status: crate::Reg, + #[doc = "0x10 - Clock selection"] + pub rtcctrl: crate::Reg, + #[doc = "0x14 - 32kHz External Crystal Oscillator (XOSC32K) Control"] + pub xosc32k: crate::Reg, + #[doc = "0x16 - Clock Failure Detector Control"] + pub cfdctrl: crate::Reg, + #[doc = "0x17 - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x18 - 32kHz Internal Oscillator (OSC32K) Control"] + pub osc32k: crate::Reg, + #[doc = "0x1c - 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control"] + pub osculp32k: crate::Reg, +} +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Power and Clocks Status"] +pub mod status; +#[doc = "RTCCTRL register accessor: an alias for `Reg`"] +pub type RTCCTRL = crate::Reg; +#[doc = "Clock selection"] +pub mod rtcctrl; +#[doc = "XOSC32K register accessor: an alias for `Reg`"] +pub type XOSC32K = crate::Reg; +#[doc = "32kHz External Crystal Oscillator (XOSC32K) Control"] +pub mod xosc32k; +#[doc = "CFDCTRL register accessor: an alias for `Reg`"] +pub type CFDCTRL = crate::Reg; +#[doc = "Clock Failure Detector Control"] +pub mod cfdctrl; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "OSC32K register accessor: an alias for `Reg`"] +pub type OSC32K = crate::Reg; +#[doc = "32kHz Internal Oscillator (OSC32K) Control"] +pub mod osc32k; +#[doc = "OSCULP32K register accessor: an alias for `Reg`"] +pub type OSCULP32K = crate::Reg; +#[doc = "32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control"] +pub mod osculp32k; diff --git a/pac/atsamc20e/src/osc32kctrl/cfdctrl.rs b/pac/atsamc20e/src/osc32kctrl/cfdctrl.rs new file mode 100644 index 000000000000..492a86e1a5a7 --- /dev/null +++ b/pac/atsamc20e/src/osc32kctrl/cfdctrl.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CFDCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CFDCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CFDEN` reader - Clock Failure Detector Enable"] +pub struct CFDEN_R(crate::FieldReader); +impl CFDEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFDEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFDEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFDEN` writer - Clock Failure Detector Enable"] +pub struct CFDEN_W<'a> { + w: &'a mut W, +} +impl<'a> CFDEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SWBACK` reader - Clock Switch Back"] +pub struct SWBACK_R(crate::FieldReader); +impl SWBACK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWBACK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWBACK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWBACK` writer - Clock Switch Back"] +pub struct SWBACK_W<'a> { + w: &'a mut W, +} +impl<'a> SWBACK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CFDPRESC` reader - Clock Failure Detector Prescaler"] +pub struct CFDPRESC_R(crate::FieldReader); +impl CFDPRESC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFDPRESC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFDPRESC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFDPRESC` writer - Clock Failure Detector Prescaler"] +pub struct CFDPRESC_W<'a> { + w: &'a mut W, +} +impl<'a> CFDPRESC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Clock Failure Detector Enable"] + #[inline(always)] + pub fn cfden(&self) -> CFDEN_R { + CFDEN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Clock Switch Back"] + #[inline(always)] + pub fn swback(&self) -> SWBACK_R { + SWBACK_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Clock Failure Detector Prescaler"] + #[inline(always)] + pub fn cfdpresc(&self) -> CFDPRESC_R { + CFDPRESC_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Clock Failure Detector Enable"] + #[inline(always)] + pub fn cfden(&mut self) -> CFDEN_W { + CFDEN_W { w: self } + } + #[doc = "Bit 1 - Clock Switch Back"] + #[inline(always)] + pub fn swback(&mut self) -> SWBACK_W { + SWBACK_W { w: self } + } + #[doc = "Bit 2 - Clock Failure Detector Prescaler"] + #[inline(always)] + pub fn cfdpresc(&mut self) -> CFDPRESC_W { + CFDPRESC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Clock Failure Detector Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cfdctrl](index.html) module"] +pub struct CFDCTRL_SPEC; +impl crate::RegisterSpec for CFDCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [cfdctrl::R](R) reader structure"] +impl crate::Readable for CFDCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cfdctrl::W](W) writer structure"] +impl crate::Writable for CFDCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CFDCTRL to value 0"] +impl crate::Resettable for CFDCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/osc32kctrl/evctrl.rs b/pac/atsamc20e/src/osc32kctrl/evctrl.rs new file mode 100644 index 000000000000..e22ba62f0fe2 --- /dev/null +++ b/pac/atsamc20e/src/osc32kctrl/evctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CFDEO` reader - Clock Failure Detector Event Output Enable"] +pub struct CFDEO_R(crate::FieldReader); +impl CFDEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFDEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFDEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFDEO` writer - Clock Failure Detector Event Output Enable"] +pub struct CFDEO_W<'a> { + w: &'a mut W, +} +impl<'a> CFDEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Clock Failure Detector Event Output Enable"] + #[inline(always)] + pub fn cfdeo(&self) -> CFDEO_R { + CFDEO_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Clock Failure Detector Event Output Enable"] + #[inline(always)] + pub fn cfdeo(&mut self) -> CFDEO_W { + CFDEO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/osc32kctrl/intenclr.rs b/pac/atsamc20e/src/osc32kctrl/intenclr.rs new file mode 100644 index 000000000000..7e330c8de495 --- /dev/null +++ b/pac/atsamc20e/src/osc32kctrl/intenclr.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XOSC32KRDY` reader - XOSC32K Ready Interrupt Enable"] +pub struct XOSC32KRDY_R(crate::FieldReader); +impl XOSC32KRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSC32KRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSC32KRDY` writer - XOSC32K Ready Interrupt Enable"] +pub struct XOSC32KRDY_W<'a> { + w: &'a mut W, +} +impl<'a> XOSC32KRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `OSC32KRDY` reader - OSC32K Ready Interrupt Enable"] +pub struct OSC32KRDY_R(crate::FieldReader); +impl OSC32KRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC32KRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC32KRDY` writer - OSC32K Ready Interrupt Enable"] +pub struct OSC32KRDY_W<'a> { + w: &'a mut W, +} +impl<'a> OSC32KRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CLKFAIL` reader - XOSC32K Clock Failure Detector Interrupt Enable"] +pub struct CLKFAIL_R(crate::FieldReader); +impl CLKFAIL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKFAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKFAIL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKFAIL` writer - XOSC32K Clock Failure Detector Interrupt Enable"] +pub struct CLKFAIL_W<'a> { + w: &'a mut W, +} +impl<'a> CLKFAIL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - XOSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn xosc32krdy(&self) -> XOSC32KRDY_R { + XOSC32KRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - OSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn osc32krdy(&self) -> OSC32KRDY_R { + OSC32KRDY_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - XOSC32K Clock Failure Detector Interrupt Enable"] + #[inline(always)] + pub fn clkfail(&self) -> CLKFAIL_R { + CLKFAIL_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - XOSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn xosc32krdy(&mut self) -> XOSC32KRDY_W { + XOSC32KRDY_W { w: self } + } + #[doc = "Bit 1 - OSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn osc32krdy(&mut self) -> OSC32KRDY_W { + OSC32KRDY_W { w: self } + } + #[doc = "Bit 2 - XOSC32K Clock Failure Detector Interrupt Enable"] + #[inline(always)] + pub fn clkfail(&mut self) -> CLKFAIL_W { + CLKFAIL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/osc32kctrl/intenset.rs b/pac/atsamc20e/src/osc32kctrl/intenset.rs new file mode 100644 index 000000000000..e853d40049f2 --- /dev/null +++ b/pac/atsamc20e/src/osc32kctrl/intenset.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XOSC32KRDY` reader - XOSC32K Ready Interrupt Enable"] +pub struct XOSC32KRDY_R(crate::FieldReader); +impl XOSC32KRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSC32KRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSC32KRDY` writer - XOSC32K Ready Interrupt Enable"] +pub struct XOSC32KRDY_W<'a> { + w: &'a mut W, +} +impl<'a> XOSC32KRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `OSC32KRDY` reader - OSC32K Ready Interrupt Enable"] +pub struct OSC32KRDY_R(crate::FieldReader); +impl OSC32KRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC32KRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC32KRDY` writer - OSC32K Ready Interrupt Enable"] +pub struct OSC32KRDY_W<'a> { + w: &'a mut W, +} +impl<'a> OSC32KRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CLKFAIL` reader - XOSC32K Clock Failure Detector Interrupt Enable"] +pub struct CLKFAIL_R(crate::FieldReader); +impl CLKFAIL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKFAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKFAIL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKFAIL` writer - XOSC32K Clock Failure Detector Interrupt Enable"] +pub struct CLKFAIL_W<'a> { + w: &'a mut W, +} +impl<'a> CLKFAIL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - XOSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn xosc32krdy(&self) -> XOSC32KRDY_R { + XOSC32KRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - OSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn osc32krdy(&self) -> OSC32KRDY_R { + OSC32KRDY_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - XOSC32K Clock Failure Detector Interrupt Enable"] + #[inline(always)] + pub fn clkfail(&self) -> CLKFAIL_R { + CLKFAIL_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - XOSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn xosc32krdy(&mut self) -> XOSC32KRDY_W { + XOSC32KRDY_W { w: self } + } + #[doc = "Bit 1 - OSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn osc32krdy(&mut self) -> OSC32KRDY_W { + OSC32KRDY_W { w: self } + } + #[doc = "Bit 2 - XOSC32K Clock Failure Detector Interrupt Enable"] + #[inline(always)] + pub fn clkfail(&mut self) -> CLKFAIL_W { + CLKFAIL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/osc32kctrl/intflag.rs b/pac/atsamc20e/src/osc32kctrl/intflag.rs new file mode 100644 index 000000000000..9ca42439429d --- /dev/null +++ b/pac/atsamc20e/src/osc32kctrl/intflag.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XOSC32KRDY` reader - XOSC32K Ready"] +pub struct XOSC32KRDY_R(crate::FieldReader); +impl XOSC32KRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSC32KRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSC32KRDY` writer - XOSC32K Ready"] +pub struct XOSC32KRDY_W<'a> { + w: &'a mut W, +} +impl<'a> XOSC32KRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `OSC32KRDY` reader - OSC32K Ready"] +pub struct OSC32KRDY_R(crate::FieldReader); +impl OSC32KRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC32KRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC32KRDY` writer - OSC32K Ready"] +pub struct OSC32KRDY_W<'a> { + w: &'a mut W, +} +impl<'a> OSC32KRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CLKFAIL` reader - XOSC32K Clock Failure Detector"] +pub struct CLKFAIL_R(crate::FieldReader); +impl CLKFAIL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKFAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKFAIL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKFAIL` writer - XOSC32K Clock Failure Detector"] +pub struct CLKFAIL_W<'a> { + w: &'a mut W, +} +impl<'a> CLKFAIL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - XOSC32K Ready"] + #[inline(always)] + pub fn xosc32krdy(&self) -> XOSC32KRDY_R { + XOSC32KRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - OSC32K Ready"] + #[inline(always)] + pub fn osc32krdy(&self) -> OSC32KRDY_R { + OSC32KRDY_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - XOSC32K Clock Failure Detector"] + #[inline(always)] + pub fn clkfail(&self) -> CLKFAIL_R { + CLKFAIL_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - XOSC32K Ready"] + #[inline(always)] + pub fn xosc32krdy(&mut self) -> XOSC32KRDY_W { + XOSC32KRDY_W { w: self } + } + #[doc = "Bit 1 - OSC32K Ready"] + #[inline(always)] + pub fn osc32krdy(&mut self) -> OSC32KRDY_W { + OSC32KRDY_W { w: self } + } + #[doc = "Bit 2 - XOSC32K Clock Failure Detector"] + #[inline(always)] + pub fn clkfail(&mut self) -> CLKFAIL_W { + CLKFAIL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/osc32kctrl/osc32k.rs b/pac/atsamc20e/src/osc32kctrl/osc32k.rs new file mode 100644 index 000000000000..aa32cb287aa7 --- /dev/null +++ b/pac/atsamc20e/src/osc32kctrl/osc32k.rs @@ -0,0 +1,549 @@ +#[doc = "Register `OSC32K` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OSC32K` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Oscillator Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Oscillator Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `EN32K` reader - 32kHz Output Enable"] +pub struct EN32K_R(crate::FieldReader); +impl EN32K_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EN32K_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EN32K_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EN32K` writer - 32kHz Output Enable"] +pub struct EN32K_W<'a> { + w: &'a mut W, +} +impl<'a> EN32K_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `EN1K` reader - 1kHz Output Enable"] +pub struct EN1K_R(crate::FieldReader); +impl EN1K_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EN1K_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EN1K_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EN1K` writer - 1kHz Output Enable"] +pub struct EN1K_W<'a> { + w: &'a mut W, +} +impl<'a> EN1K_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - On Demand Control"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - On Demand Control"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Oscillator Start-Up Time\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum STARTUP_A { + #[doc = "0: 0.092 ms"] + CYCLE3 = 0, + #[doc = "1: 0.122 ms"] + CYCLE4 = 1, + #[doc = "2: 0.183 ms"] + CYCLE6 = 2, + #[doc = "3: 0.305 ms"] + CYCLE10 = 3, + #[doc = "4: 0.549 ms"] + CYCLE18 = 4, + #[doc = "5: 1.038 ms"] + CYCLE34 = 5, + #[doc = "6: 2.014 ms"] + CYCLE66 = 6, + #[doc = "7: 3.967 ms"] + CYCLE130 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: STARTUP_A) -> Self { + variant as _ + } +} +#[doc = "Field `STARTUP` reader - Oscillator Start-Up Time"] +pub struct STARTUP_R(crate::FieldReader); +impl STARTUP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + STARTUP_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STARTUP_A { + match self.bits { + 0 => STARTUP_A::CYCLE3, + 1 => STARTUP_A::CYCLE4, + 2 => STARTUP_A::CYCLE6, + 3 => STARTUP_A::CYCLE10, + 4 => STARTUP_A::CYCLE18, + 5 => STARTUP_A::CYCLE34, + 6 => STARTUP_A::CYCLE66, + 7 => STARTUP_A::CYCLE130, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `CYCLE3`"] + #[inline(always)] + pub fn is_cycle3(&self) -> bool { + **self == STARTUP_A::CYCLE3 + } + #[doc = "Checks if the value of the field is `CYCLE4`"] + #[inline(always)] + pub fn is_cycle4(&self) -> bool { + **self == STARTUP_A::CYCLE4 + } + #[doc = "Checks if the value of the field is `CYCLE6`"] + #[inline(always)] + pub fn is_cycle6(&self) -> bool { + **self == STARTUP_A::CYCLE6 + } + #[doc = "Checks if the value of the field is `CYCLE10`"] + #[inline(always)] + pub fn is_cycle10(&self) -> bool { + **self == STARTUP_A::CYCLE10 + } + #[doc = "Checks if the value of the field is `CYCLE18`"] + #[inline(always)] + pub fn is_cycle18(&self) -> bool { + **self == STARTUP_A::CYCLE18 + } + #[doc = "Checks if the value of the field is `CYCLE34`"] + #[inline(always)] + pub fn is_cycle34(&self) -> bool { + **self == STARTUP_A::CYCLE34 + } + #[doc = "Checks if the value of the field is `CYCLE66`"] + #[inline(always)] + pub fn is_cycle66(&self) -> bool { + **self == STARTUP_A::CYCLE66 + } + #[doc = "Checks if the value of the field is `CYCLE130`"] + #[inline(always)] + pub fn is_cycle130(&self) -> bool { + **self == STARTUP_A::CYCLE130 + } +} +impl core::ops::Deref for STARTUP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STARTUP` writer - Oscillator Start-Up Time"] +pub struct STARTUP_W<'a> { + w: &'a mut W, +} +impl<'a> STARTUP_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: STARTUP_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "0.092 ms"] + #[inline(always)] + pub fn cycle3(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE3) + } + #[doc = "0.122 ms"] + #[inline(always)] + pub fn cycle4(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE4) + } + #[doc = "0.183 ms"] + #[inline(always)] + pub fn cycle6(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE6) + } + #[doc = "0.305 ms"] + #[inline(always)] + pub fn cycle10(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE10) + } + #[doc = "0.549 ms"] + #[inline(always)] + pub fn cycle18(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE18) + } + #[doc = "1.038 ms"] + #[inline(always)] + pub fn cycle34(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE34) + } + #[doc = "2.014 ms"] + #[inline(always)] + pub fn cycle66(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE66) + } + #[doc = "3.967 ms"] + #[inline(always)] + pub fn cycle130(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE130) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +#[doc = "Field `WRTLOCK` reader - Write Lock"] +pub struct WRTLOCK_R(crate::FieldReader); +impl WRTLOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WRTLOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WRTLOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WRTLOCK` writer - Write Lock"] +pub struct WRTLOCK_W<'a> { + w: &'a mut W, +} +impl<'a> WRTLOCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `CALIB` reader - Oscillator Calibration"] +pub struct CALIB_R(crate::FieldReader); +impl CALIB_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CALIB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CALIB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CALIB` writer - Oscillator Calibration"] +pub struct CALIB_W<'a> { + w: &'a mut W, +} +impl<'a> CALIB_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x7f << 16)) | ((value as u32 & 0x7f) << 16); + self.w + } +} +impl R { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - 32kHz Output Enable"] + #[inline(always)] + pub fn en32k(&self) -> EN32K_R { + EN32K_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - 1kHz Output Enable"] + #[inline(always)] + pub fn en1k(&self) -> EN1K_R { + EN1K_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Oscillator Start-Up Time"] + #[inline(always)] + pub fn startup(&self) -> STARTUP_R { + STARTUP_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 12 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&self) -> WRTLOCK_R { + WRTLOCK_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bits 16:22 - Oscillator Calibration"] + #[inline(always)] + pub fn calib(&self) -> CALIB_R { + CALIB_R::new(((self.bits >> 16) & 0x7f) as u8) + } +} +impl W { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - 32kHz Output Enable"] + #[inline(always)] + pub fn en32k(&mut self) -> EN32K_W { + EN32K_W { w: self } + } + #[doc = "Bit 3 - 1kHz Output Enable"] + #[inline(always)] + pub fn en1k(&mut self) -> EN1K_W { + EN1K_W { w: self } + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Bits 8:10 - Oscillator Start-Up Time"] + #[inline(always)] + pub fn startup(&mut self) -> STARTUP_W { + STARTUP_W { w: self } + } + #[doc = "Bit 12 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&mut self) -> WRTLOCK_W { + WRTLOCK_W { w: self } + } + #[doc = "Bits 16:22 - Oscillator Calibration"] + #[inline(always)] + pub fn calib(&mut self) -> CALIB_W { + CALIB_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "32kHz Internal Oscillator (OSC32K) Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [osc32k](index.html) module"] +pub struct OSC32K_SPEC; +impl crate::RegisterSpec for OSC32K_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [osc32k::R](R) reader structure"] +impl crate::Readable for OSC32K_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [osc32k::W](W) writer structure"] +impl crate::Writable for OSC32K_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OSC32K to value 0x003f_0080"] +impl crate::Resettable for OSC32K_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x003f_0080 + } +} diff --git a/pac/atsamc20e/src/osc32kctrl/osculp32k.rs b/pac/atsamc20e/src/osc32kctrl/osculp32k.rs new file mode 100644 index 000000000000..1c351c406e59 --- /dev/null +++ b/pac/atsamc20e/src/osc32kctrl/osculp32k.rs @@ -0,0 +1,150 @@ +#[doc = "Register `OSCULP32K` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OSCULP32K` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CALIB` reader - Oscillator Calibration"] +pub struct CALIB_R(crate::FieldReader); +impl CALIB_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CALIB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CALIB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CALIB` writer - Oscillator Calibration"] +pub struct CALIB_W<'a> { + w: &'a mut W, +} +impl<'a> CALIB_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 8)) | ((value as u32 & 0x1f) << 8); + self.w + } +} +#[doc = "Field `WRTLOCK` reader - Write Lock"] +pub struct WRTLOCK_R(crate::FieldReader); +impl WRTLOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WRTLOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WRTLOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WRTLOCK` writer - Write Lock"] +pub struct WRTLOCK_W<'a> { + w: &'a mut W, +} +impl<'a> WRTLOCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bits 8:12 - Oscillator Calibration"] + #[inline(always)] + pub fn calib(&self) -> CALIB_R { + CALIB_R::new(((self.bits >> 8) & 0x1f) as u8) + } + #[doc = "Bit 15 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&self) -> WRTLOCK_R { + WRTLOCK_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 8:12 - Oscillator Calibration"] + #[inline(always)] + pub fn calib(&mut self) -> CALIB_W { + CALIB_W { w: self } + } + #[doc = "Bit 15 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&mut self) -> WRTLOCK_W { + WRTLOCK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [osculp32k](index.html) module"] +pub struct OSCULP32K_SPEC; +impl crate::RegisterSpec for OSCULP32K_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [osculp32k::R](R) reader structure"] +impl crate::Readable for OSCULP32K_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [osculp32k::W](W) writer structure"] +impl crate::Writable for OSCULP32K_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OSCULP32K to value 0"] +impl crate::Resettable for OSCULP32K_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/osc32kctrl/rtcctrl.rs b/pac/atsamc20e/src/osc32kctrl/rtcctrl.rs new file mode 100644 index 000000000000..1248024a03b9 --- /dev/null +++ b/pac/atsamc20e/src/osc32kctrl/rtcctrl.rs @@ -0,0 +1,204 @@ +#[doc = "Register `RTCCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RTCCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "RTC Clock Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum RTCSEL_A { + #[doc = "0: 1.024kHz from 32kHz internal ULP oscillator"] + ULP1K = 0, + #[doc = "1: 32.768kHz from 32kHz internal ULP oscillator"] + ULP32K = 1, + #[doc = "2: 1.024kHz from 32.768kHz internal oscillator"] + OSC1K = 2, + #[doc = "3: 32.768kHz from 32.768kHz internal oscillator"] + OSC32K = 3, + #[doc = "4: 1.024kHz from 32.768kHz internal oscillator"] + XOSC1K = 4, + #[doc = "5: 32.768kHz from 32.768kHz external crystal oscillator"] + XOSC32K = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RTCSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `RTCSEL` reader - RTC Clock Selection"] +pub struct RTCSEL_R(crate::FieldReader); +impl RTCSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RTCSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(RTCSEL_A::ULP1K), + 1 => Some(RTCSEL_A::ULP32K), + 2 => Some(RTCSEL_A::OSC1K), + 3 => Some(RTCSEL_A::OSC32K), + 4 => Some(RTCSEL_A::XOSC1K), + 5 => Some(RTCSEL_A::XOSC32K), + _ => None, + } + } + #[doc = "Checks if the value of the field is `ULP1K`"] + #[inline(always)] + pub fn is_ulp1k(&self) -> bool { + **self == RTCSEL_A::ULP1K + } + #[doc = "Checks if the value of the field is `ULP32K`"] + #[inline(always)] + pub fn is_ulp32k(&self) -> bool { + **self == RTCSEL_A::ULP32K + } + #[doc = "Checks if the value of the field is `OSC1K`"] + #[inline(always)] + pub fn is_osc1k(&self) -> bool { + **self == RTCSEL_A::OSC1K + } + #[doc = "Checks if the value of the field is `OSC32K`"] + #[inline(always)] + pub fn is_osc32k(&self) -> bool { + **self == RTCSEL_A::OSC32K + } + #[doc = "Checks if the value of the field is `XOSC1K`"] + #[inline(always)] + pub fn is_xosc1k(&self) -> bool { + **self == RTCSEL_A::XOSC1K + } + #[doc = "Checks if the value of the field is `XOSC32K`"] + #[inline(always)] + pub fn is_xosc32k(&self) -> bool { + **self == RTCSEL_A::XOSC32K + } +} +impl core::ops::Deref for RTCSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RTCSEL` writer - RTC Clock Selection"] +pub struct RTCSEL_W<'a> { + w: &'a mut W, +} +impl<'a> RTCSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RTCSEL_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "1.024kHz from 32kHz internal ULP oscillator"] + #[inline(always)] + pub fn ulp1k(self) -> &'a mut W { + self.variant(RTCSEL_A::ULP1K) + } + #[doc = "32.768kHz from 32kHz internal ULP oscillator"] + #[inline(always)] + pub fn ulp32k(self) -> &'a mut W { + self.variant(RTCSEL_A::ULP32K) + } + #[doc = "1.024kHz from 32.768kHz internal oscillator"] + #[inline(always)] + pub fn osc1k(self) -> &'a mut W { + self.variant(RTCSEL_A::OSC1K) + } + #[doc = "32.768kHz from 32.768kHz internal oscillator"] + #[inline(always)] + pub fn osc32k(self) -> &'a mut W { + self.variant(RTCSEL_A::OSC32K) + } + #[doc = "1.024kHz from 32.768kHz internal oscillator"] + #[inline(always)] + pub fn xosc1k(self) -> &'a mut W { + self.variant(RTCSEL_A::XOSC1K) + } + #[doc = "32.768kHz from 32.768kHz external crystal oscillator"] + #[inline(always)] + pub fn xosc32k(self) -> &'a mut W { + self.variant(RTCSEL_A::XOSC32K) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - RTC Clock Selection"] + #[inline(always)] + pub fn rtcsel(&self) -> RTCSEL_R { + RTCSEL_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - RTC Clock Selection"] + #[inline(always)] + pub fn rtcsel(&mut self) -> RTCSEL_W { + RTCSEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Clock selection\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rtcctrl](index.html) module"] +pub struct RTCCTRL_SPEC; +impl crate::RegisterSpec for RTCCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rtcctrl::R](R) reader structure"] +impl crate::Readable for RTCCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rtcctrl::W](W) writer structure"] +impl crate::Writable for RTCCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RTCCTRL to value 0"] +impl crate::Resettable for RTCCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/osc32kctrl/status.rs b/pac/atsamc20e/src/osc32kctrl/status.rs new file mode 100644 index 000000000000..f1f1483ac4e8 --- /dev/null +++ b/pac/atsamc20e/src/osc32kctrl/status.rs @@ -0,0 +1,113 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `XOSC32KRDY` reader - XOSC32K Ready"] +pub struct XOSC32KRDY_R(crate::FieldReader); +impl XOSC32KRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSC32KRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC32KRDY` reader - OSC32K Ready"] +pub struct OSC32KRDY_R(crate::FieldReader); +impl OSC32KRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC32KRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKFAIL` reader - XOSC32K Clock Failure Detector"] +pub struct CLKFAIL_R(crate::FieldReader); +impl CLKFAIL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKFAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKFAIL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKSW` reader - XOSC32K Clock switch"] +pub struct CLKSW_R(crate::FieldReader); +impl CLKSW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKSW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKSW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - XOSC32K Ready"] + #[inline(always)] + pub fn xosc32krdy(&self) -> XOSC32KRDY_R { + XOSC32KRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - OSC32K Ready"] + #[inline(always)] + pub fn osc32krdy(&self) -> OSC32KRDY_R { + OSC32KRDY_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - XOSC32K Clock Failure Detector"] + #[inline(always)] + pub fn clkfail(&self) -> CLKFAIL_R { + CLKFAIL_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - XOSC32K Clock switch"] + #[inline(always)] + pub fn clksw(&self) -> CLKSW_R { + CLKSW_R::new(((self.bits >> 3) & 0x01) != 0) + } +} +#[doc = "Power and Clocks Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/osc32kctrl/xosc32k.rs b/pac/atsamc20e/src/osc32kctrl/xosc32k.rs new file mode 100644 index 000000000000..93e42bba3c0e --- /dev/null +++ b/pac/atsamc20e/src/osc32kctrl/xosc32k.rs @@ -0,0 +1,559 @@ +#[doc = "Register `XOSC32K` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `XOSC32K` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Oscillator Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Oscillator Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `XTALEN` reader - Crystal Oscillator Enable"] +pub struct XTALEN_R(crate::FieldReader); +impl XTALEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XTALEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XTALEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XTALEN` writer - Crystal Oscillator Enable"] +pub struct XTALEN_W<'a> { + w: &'a mut W, +} +impl<'a> XTALEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `EN32K` reader - 32kHz Output Enable"] +pub struct EN32K_R(crate::FieldReader); +impl EN32K_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EN32K_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EN32K_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EN32K` writer - 32kHz Output Enable"] +pub struct EN32K_W<'a> { + w: &'a mut W, +} +impl<'a> EN32K_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `EN1K` reader - 1kHz Output Enable"] +pub struct EN1K_R(crate::FieldReader); +impl EN1K_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EN1K_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EN1K_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EN1K` writer - 1kHz Output Enable"] +pub struct EN1K_W<'a> { + w: &'a mut W, +} +impl<'a> EN1K_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - On Demand Control"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - On Demand Control"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Oscillator Start-Up Time\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum STARTUP_A { + #[doc = "0: 0.122 ms"] + CYCLE1 = 0, + #[doc = "1: 1.068 ms"] + CYCLE32 = 1, + #[doc = "2: 62.6 ms"] + CYCLE2048 = 2, + #[doc = "3: 125 ms"] + CYCLE4096 = 3, + #[doc = "4: 500 ms"] + CYCLE16384 = 4, + #[doc = "5: 1000 ms"] + CYCLE32768 = 5, + #[doc = "6: 2000 ms"] + CYCLE65536 = 6, + #[doc = "7: 4000 ms"] + CYCLE131072 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: STARTUP_A) -> Self { + variant as _ + } +} +#[doc = "Field `STARTUP` reader - Oscillator Start-Up Time"] +pub struct STARTUP_R(crate::FieldReader); +impl STARTUP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + STARTUP_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STARTUP_A { + match self.bits { + 0 => STARTUP_A::CYCLE1, + 1 => STARTUP_A::CYCLE32, + 2 => STARTUP_A::CYCLE2048, + 3 => STARTUP_A::CYCLE4096, + 4 => STARTUP_A::CYCLE16384, + 5 => STARTUP_A::CYCLE32768, + 6 => STARTUP_A::CYCLE65536, + 7 => STARTUP_A::CYCLE131072, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `CYCLE1`"] + #[inline(always)] + pub fn is_cycle1(&self) -> bool { + **self == STARTUP_A::CYCLE1 + } + #[doc = "Checks if the value of the field is `CYCLE32`"] + #[inline(always)] + pub fn is_cycle32(&self) -> bool { + **self == STARTUP_A::CYCLE32 + } + #[doc = "Checks if the value of the field is `CYCLE2048`"] + #[inline(always)] + pub fn is_cycle2048(&self) -> bool { + **self == STARTUP_A::CYCLE2048 + } + #[doc = "Checks if the value of the field is `CYCLE4096`"] + #[inline(always)] + pub fn is_cycle4096(&self) -> bool { + **self == STARTUP_A::CYCLE4096 + } + #[doc = "Checks if the value of the field is `CYCLE16384`"] + #[inline(always)] + pub fn is_cycle16384(&self) -> bool { + **self == STARTUP_A::CYCLE16384 + } + #[doc = "Checks if the value of the field is `CYCLE32768`"] + #[inline(always)] + pub fn is_cycle32768(&self) -> bool { + **self == STARTUP_A::CYCLE32768 + } + #[doc = "Checks if the value of the field is `CYCLE65536`"] + #[inline(always)] + pub fn is_cycle65536(&self) -> bool { + **self == STARTUP_A::CYCLE65536 + } + #[doc = "Checks if the value of the field is `CYCLE131072`"] + #[inline(always)] + pub fn is_cycle131072(&self) -> bool { + **self == STARTUP_A::CYCLE131072 + } +} +impl core::ops::Deref for STARTUP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STARTUP` writer - Oscillator Start-Up Time"] +pub struct STARTUP_W<'a> { + w: &'a mut W, +} +impl<'a> STARTUP_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: STARTUP_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "0.122 ms"] + #[inline(always)] + pub fn cycle1(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE1) + } + #[doc = "1.068 ms"] + #[inline(always)] + pub fn cycle32(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE32) + } + #[doc = "62.6 ms"] + #[inline(always)] + pub fn cycle2048(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE2048) + } + #[doc = "125 ms"] + #[inline(always)] + pub fn cycle4096(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE4096) + } + #[doc = "500 ms"] + #[inline(always)] + pub fn cycle16384(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE16384) + } + #[doc = "1000 ms"] + #[inline(always)] + pub fn cycle32768(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE32768) + } + #[doc = "2000 ms"] + #[inline(always)] + pub fn cycle65536(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE65536) + } + #[doc = "4000 ms"] + #[inline(always)] + pub fn cycle131072(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE131072) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u16 & 0x07) << 8); + self.w + } +} +#[doc = "Field `WRTLOCK` reader - Write Lock"] +pub struct WRTLOCK_R(crate::FieldReader); +impl WRTLOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WRTLOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WRTLOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WRTLOCK` writer - Write Lock"] +pub struct WRTLOCK_W<'a> { + w: &'a mut W, +} +impl<'a> WRTLOCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u16 & 0x01) << 12); + self.w + } +} +impl R { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Crystal Oscillator Enable"] + #[inline(always)] + pub fn xtalen(&self) -> XTALEN_R { + XTALEN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - 32kHz Output Enable"] + #[inline(always)] + pub fn en32k(&self) -> EN32K_R { + EN32K_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - 1kHz Output Enable"] + #[inline(always)] + pub fn en1k(&self) -> EN1K_R { + EN1K_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Oscillator Start-Up Time"] + #[inline(always)] + pub fn startup(&self) -> STARTUP_R { + STARTUP_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 12 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&self) -> WRTLOCK_R { + WRTLOCK_R::new(((self.bits >> 12) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - Crystal Oscillator Enable"] + #[inline(always)] + pub fn xtalen(&mut self) -> XTALEN_W { + XTALEN_W { w: self } + } + #[doc = "Bit 3 - 32kHz Output Enable"] + #[inline(always)] + pub fn en32k(&mut self) -> EN32K_W { + EN32K_W { w: self } + } + #[doc = "Bit 4 - 1kHz Output Enable"] + #[inline(always)] + pub fn en1k(&mut self) -> EN1K_W { + EN1K_W { w: self } + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Bits 8:10 - Oscillator Start-Up Time"] + #[inline(always)] + pub fn startup(&mut self) -> STARTUP_W { + STARTUP_W { w: self } + } + #[doc = "Bit 12 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&mut self) -> WRTLOCK_W { + WRTLOCK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "32kHz External Crystal Oscillator (XOSC32K) Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [xosc32k](index.html) module"] +pub struct XOSC32K_SPEC; +impl crate::RegisterSpec for XOSC32K_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [xosc32k::R](R) reader structure"] +impl crate::Readable for XOSC32K_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [xosc32k::W](W) writer structure"] +impl crate::Writable for XOSC32K_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets XOSC32K to value 0x80"] +impl crate::Resettable for XOSC32K_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x80 + } +} diff --git a/pac/atsamc20e/src/oscctrl.rs b/pac/atsamc20e/src/oscctrl.rs new file mode 100644 index 000000000000..e6dd0929927c --- /dev/null +++ b/pac/atsamc20e/src/oscctrl.rs @@ -0,0 +1,117 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x04 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x08 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x0c - Power and Clocks Status"] + pub status: crate::Reg, + #[doc = "0x10 - External Multipurpose Crystal Oscillator (XOSC) Control"] + pub xoscctrl: crate::Reg, + #[doc = "0x12 - Clock Failure Detector Prescaler"] + pub cfdpresc: crate::Reg, + #[doc = "0x13 - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x14 - 48MHz Internal Oscillator (OSC48M) Control"] + pub osc48mctrl: crate::Reg, + #[doc = "0x15 - OSC48M Divider"] + pub osc48mdiv: crate::Reg, + #[doc = "0x16 - OSC48M Startup Time"] + pub osc48mstup: crate::Reg, + _reserved10: [u8; 0x01], + #[doc = "0x18 - OSC48M Synchronization Busy"] + pub osc48msyncbusy: crate::Reg, + #[doc = "0x1c - DPLL Control"] + pub dpllctrla: crate::Reg, + _reserved12: [u8; 0x03], + #[doc = "0x20 - DPLL Ratio Control"] + pub dpllratio: crate::Reg, + #[doc = "0x24 - Digital Core Configuration"] + pub dpllctrlb: crate::Reg, + #[doc = "0x28 - DPLL Prescaler"] + pub dpllpresc: crate::Reg, + _reserved15: [u8; 0x03], + #[doc = "0x2c - DPLL Synchronization Busy"] + pub dpllsyncbusy: crate::Reg, + _reserved16: [u8; 0x03], + #[doc = "0x30 - DPLL Status"] + pub dpllstatus: crate::Reg, + _reserved17: [u8; 0x07], + #[doc = "0x38 - 48MHz Oscillator Calibration"] + pub cal48m: crate::Reg, +} +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Power and Clocks Status"] +pub mod status; +#[doc = "XOSCCTRL register accessor: an alias for `Reg`"] +pub type XOSCCTRL = crate::Reg; +#[doc = "External Multipurpose Crystal Oscillator (XOSC) Control"] +pub mod xoscctrl; +#[doc = "CFDPRESC register accessor: an alias for `Reg`"] +pub type CFDPRESC = crate::Reg; +#[doc = "Clock Failure Detector Prescaler"] +pub mod cfdpresc; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "OSC48MCTRL register accessor: an alias for `Reg`"] +pub type OSC48MCTRL = crate::Reg; +#[doc = "48MHz Internal Oscillator (OSC48M) Control"] +pub mod osc48mctrl; +#[doc = "OSC48MDIV register accessor: an alias for `Reg`"] +pub type OSC48MDIV = crate::Reg; +#[doc = "OSC48M Divider"] +pub mod osc48mdiv; +#[doc = "OSC48MSTUP register accessor: an alias for `Reg`"] +pub type OSC48MSTUP = crate::Reg; +#[doc = "OSC48M Startup Time"] +pub mod osc48mstup; +#[doc = "OSC48MSYNCBUSY register accessor: an alias for `Reg`"] +pub type OSC48MSYNCBUSY = crate::Reg; +#[doc = "OSC48M Synchronization Busy"] +pub mod osc48msyncbusy; +#[doc = "DPLLCTRLA register accessor: an alias for `Reg`"] +pub type DPLLCTRLA = crate::Reg; +#[doc = "DPLL Control"] +pub mod dpllctrla; +#[doc = "DPLLRATIO register accessor: an alias for `Reg`"] +pub type DPLLRATIO = crate::Reg; +#[doc = "DPLL Ratio Control"] +pub mod dpllratio; +#[doc = "DPLLCTRLB register accessor: an alias for `Reg`"] +pub type DPLLCTRLB = crate::Reg; +#[doc = "Digital Core Configuration"] +pub mod dpllctrlb; +#[doc = "DPLLPRESC register accessor: an alias for `Reg`"] +pub type DPLLPRESC = crate::Reg; +#[doc = "DPLL Prescaler"] +pub mod dpllpresc; +#[doc = "DPLLSYNCBUSY register accessor: an alias for `Reg`"] +pub type DPLLSYNCBUSY = crate::Reg; +#[doc = "DPLL Synchronization Busy"] +pub mod dpllsyncbusy; +#[doc = "DPLLSTATUS register accessor: an alias for `Reg`"] +pub type DPLLSTATUS = crate::Reg; +#[doc = "DPLL Status"] +pub mod dpllstatus; +#[doc = "CAL48M register accessor: an alias for `Reg`"] +pub type CAL48M = crate::Reg; +#[doc = "48MHz Oscillator Calibration"] +pub mod cal48m; diff --git a/pac/atsamc20e/src/oscctrl/cal48m.rs b/pac/atsamc20e/src/oscctrl/cal48m.rs new file mode 100644 index 000000000000..05d5cd2bbc92 --- /dev/null +++ b/pac/atsamc20e/src/oscctrl/cal48m.rs @@ -0,0 +1,177 @@ +#[doc = "Register `CAL48M` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CAL48M` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FCAL` reader - Frequency Calibration (48MHz)"] +pub struct FCAL_R(crate::FieldReader); +impl FCAL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FCAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FCAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FCAL` writer - Frequency Calibration (48MHz)"] +pub struct FCAL_W<'a> { + w: &'a mut W, +} +impl<'a> FCAL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +#[doc = "Field `FRANGE` reader - Frequency Range (48MHz)"] +pub struct FRANGE_R(crate::FieldReader); +impl FRANGE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FRANGE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FRANGE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FRANGE` writer - Frequency Range (48MHz)"] +pub struct FRANGE_W<'a> { + w: &'a mut W, +} +impl<'a> FRANGE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 8)) | ((value as u32 & 0x03) << 8); + self.w + } +} +#[doc = "Field `TCAL` reader - Temperature Calibration (48MHz)"] +pub struct TCAL_R(crate::FieldReader); +impl TCAL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TCAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCAL` writer - Temperature Calibration (48MHz)"] +pub struct TCAL_W<'a> { + w: &'a mut W, +} +impl<'a> TCAL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 16)) | ((value as u32 & 0x3f) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Frequency Calibration (48MHz)"] + #[inline(always)] + pub fn fcal(&self) -> FCAL_R { + FCAL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 8:9 - Frequency Range (48MHz)"] + #[inline(always)] + pub fn frange(&self) -> FRANGE_R { + FRANGE_R::new(((self.bits >> 8) & 0x03) as u8) + } + #[doc = "Bits 16:21 - Temperature Calibration (48MHz)"] + #[inline(always)] + pub fn tcal(&self) -> TCAL_R { + TCAL_R::new(((self.bits >> 16) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - Frequency Calibration (48MHz)"] + #[inline(always)] + pub fn fcal(&mut self) -> FCAL_W { + FCAL_W { w: self } + } + #[doc = "Bits 8:9 - Frequency Range (48MHz)"] + #[inline(always)] + pub fn frange(&mut self) -> FRANGE_W { + FRANGE_W { w: self } + } + #[doc = "Bits 16:21 - Temperature Calibration (48MHz)"] + #[inline(always)] + pub fn tcal(&mut self) -> TCAL_W { + TCAL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "48MHz Oscillator Calibration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cal48m](index.html) module"] +pub struct CAL48M_SPEC; +impl crate::RegisterSpec for CAL48M_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cal48m::R](R) reader structure"] +impl crate::Readable for CAL48M_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cal48m::W](W) writer structure"] +impl crate::Writable for CAL48M_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CAL48M to value 0"] +impl crate::Resettable for CAL48M_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/oscctrl/cfdpresc.rs b/pac/atsamc20e/src/oscctrl/cfdpresc.rs new file mode 100644 index 000000000000..029ae541eec5 --- /dev/null +++ b/pac/atsamc20e/src/oscctrl/cfdpresc.rs @@ -0,0 +1,230 @@ +#[doc = "Register `CFDPRESC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CFDPRESC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Clock Failure Detector Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CFDPRESC_A { + #[doc = "0: 48 MHz"] + DIV1 = 0, + #[doc = "1: 24 MHz"] + DIV2 = 1, + #[doc = "2: 12 MHz"] + DIV4 = 2, + #[doc = "3: 6 MHz"] + DIV8 = 3, + #[doc = "4: 3 MHz"] + DIV16 = 4, + #[doc = "5: 1.5 MHz"] + DIV32 = 5, + #[doc = "6: 0.75 MHz"] + DIV64 = 6, + #[doc = "7: 0.3125 MHz"] + DIV128 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CFDPRESC_A) -> Self { + variant as _ + } +} +#[doc = "Field `CFDPRESC` reader - Clock Failure Detector Prescaler"] +pub struct CFDPRESC_R(crate::FieldReader); +impl CFDPRESC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CFDPRESC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CFDPRESC_A { + match self.bits { + 0 => CFDPRESC_A::DIV1, + 1 => CFDPRESC_A::DIV2, + 2 => CFDPRESC_A::DIV4, + 3 => CFDPRESC_A::DIV8, + 4 => CFDPRESC_A::DIV16, + 5 => CFDPRESC_A::DIV32, + 6 => CFDPRESC_A::DIV64, + 7 => CFDPRESC_A::DIV128, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == CFDPRESC_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == CFDPRESC_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == CFDPRESC_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == CFDPRESC_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == CFDPRESC_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == CFDPRESC_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == CFDPRESC_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == CFDPRESC_A::DIV128 + } +} +impl core::ops::Deref for CFDPRESC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFDPRESC` writer - Clock Failure Detector Prescaler"] +pub struct CFDPRESC_W<'a> { + w: &'a mut W, +} +impl<'a> CFDPRESC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CFDPRESC_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "48 MHz"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(CFDPRESC_A::DIV1) + } + #[doc = "24 MHz"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(CFDPRESC_A::DIV2) + } + #[doc = "12 MHz"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(CFDPRESC_A::DIV4) + } + #[doc = "6 MHz"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(CFDPRESC_A::DIV8) + } + #[doc = "3 MHz"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(CFDPRESC_A::DIV16) + } + #[doc = "1.5 MHz"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(CFDPRESC_A::DIV32) + } + #[doc = "0.75 MHz"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(CFDPRESC_A::DIV64) + } + #[doc = "0.3125 MHz"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(CFDPRESC_A::DIV128) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Clock Failure Detector Prescaler"] + #[inline(always)] + pub fn cfdpresc(&self) -> CFDPRESC_R { + CFDPRESC_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Clock Failure Detector Prescaler"] + #[inline(always)] + pub fn cfdpresc(&mut self) -> CFDPRESC_W { + CFDPRESC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Clock Failure Detector Prescaler\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cfdpresc](index.html) module"] +pub struct CFDPRESC_SPEC; +impl crate::RegisterSpec for CFDPRESC_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [cfdpresc::R](R) reader structure"] +impl crate::Readable for CFDPRESC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cfdpresc::W](W) writer structure"] +impl crate::Writable for CFDPRESC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CFDPRESC to value 0"] +impl crate::Resettable for CFDPRESC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/oscctrl/dpllctrla.rs b/pac/atsamc20e/src/oscctrl/dpllctrla.rs new file mode 100644 index 000000000000..5a60a5087002 --- /dev/null +++ b/pac/atsamc20e/src/oscctrl/dpllctrla.rs @@ -0,0 +1,207 @@ +#[doc = "Register `DPLLCTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DPLLCTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - On Demand"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - On Demand"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - On Demand"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - On Demand"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DPLL Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dpllctrla](index.html) module"] +pub struct DPLLCTRLA_SPEC; +impl crate::RegisterSpec for DPLLCTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dpllctrla::R](R) reader structure"] +impl crate::Readable for DPLLCTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dpllctrla::W](W) writer structure"] +impl crate::Writable for DPLLCTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DPLLCTRLA to value 0x80"] +impl crate::Resettable for DPLLCTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x80 + } +} diff --git a/pac/atsamc20e/src/oscctrl/dpllctrlb.rs b/pac/atsamc20e/src/oscctrl/dpllctrlb.rs new file mode 100644 index 000000000000..8400b0572dd0 --- /dev/null +++ b/pac/atsamc20e/src/oscctrl/dpllctrlb.rs @@ -0,0 +1,580 @@ +#[doc = "Register `DPLLCTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DPLLCTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Proportional Integral Filter Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FILTER_A { + #[doc = "0: Default filter mode"] + DEFAULT = 0, + #[doc = "1: Low bandwidth filter"] + LBFILT = 1, + #[doc = "2: High bandwidth filter"] + HBFILT = 2, + #[doc = "3: High damping filter"] + HDFILT = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FILTER_A) -> Self { + variant as _ + } +} +#[doc = "Field `FILTER` reader - Proportional Integral Filter Selection"] +pub struct FILTER_R(crate::FieldReader); +impl FILTER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FILTER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FILTER_A { + match self.bits { + 0 => FILTER_A::DEFAULT, + 1 => FILTER_A::LBFILT, + 2 => FILTER_A::HBFILT, + 3 => FILTER_A::HDFILT, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DEFAULT`"] + #[inline(always)] + pub fn is_default(&self) -> bool { + **self == FILTER_A::DEFAULT + } + #[doc = "Checks if the value of the field is `LBFILT`"] + #[inline(always)] + pub fn is_lbfilt(&self) -> bool { + **self == FILTER_A::LBFILT + } + #[doc = "Checks if the value of the field is `HBFILT`"] + #[inline(always)] + pub fn is_hbfilt(&self) -> bool { + **self == FILTER_A::HBFILT + } + #[doc = "Checks if the value of the field is `HDFILT`"] + #[inline(always)] + pub fn is_hdfilt(&self) -> bool { + **self == FILTER_A::HDFILT + } +} +impl core::ops::Deref for FILTER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTER` writer - Proportional Integral Filter Selection"] +pub struct FILTER_W<'a> { + w: &'a mut W, +} +impl<'a> FILTER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FILTER_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Default filter mode"] + #[inline(always)] + pub fn default(self) -> &'a mut W { + self.variant(FILTER_A::DEFAULT) + } + #[doc = "Low bandwidth filter"] + #[inline(always)] + pub fn lbfilt(self) -> &'a mut W { + self.variant(FILTER_A::LBFILT) + } + #[doc = "High bandwidth filter"] + #[inline(always)] + pub fn hbfilt(self) -> &'a mut W { + self.variant(FILTER_A::HBFILT) + } + #[doc = "High damping filter"] + #[inline(always)] + pub fn hdfilt(self) -> &'a mut W { + self.variant(FILTER_A::HDFILT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u32 & 0x03); + self.w + } +} +#[doc = "Field `LPEN` reader - Low-Power Enable"] +pub struct LPEN_R(crate::FieldReader); +impl LPEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LPEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LPEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LPEN` writer - Low-Power Enable"] +pub struct LPEN_W<'a> { + w: &'a mut W, +} +impl<'a> LPEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `WUF` reader - Wake Up Fast"] +pub struct WUF_R(crate::FieldReader); +impl WUF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WUF` writer - Wake Up Fast"] +pub struct WUF_W<'a> { + w: &'a mut W, +} +impl<'a> WUF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Reference Clock Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum REFCLK_A { + #[doc = "0: XOSC32K clock reference"] + XOSC32K = 0, + #[doc = "1: XOSC clock reference"] + XOSC = 1, + #[doc = "2: GCLK clock reference"] + GCLK = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: REFCLK_A) -> Self { + variant as _ + } +} +#[doc = "Field `REFCLK` reader - Reference Clock Selection"] +pub struct REFCLK_R(crate::FieldReader); +impl REFCLK_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REFCLK_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(REFCLK_A::XOSC32K), + 1 => Some(REFCLK_A::XOSC), + 2 => Some(REFCLK_A::GCLK), + _ => None, + } + } + #[doc = "Checks if the value of the field is `XOSC32K`"] + #[inline(always)] + pub fn is_xosc32k(&self) -> bool { + **self == REFCLK_A::XOSC32K + } + #[doc = "Checks if the value of the field is `XOSC`"] + #[inline(always)] + pub fn is_xosc(&self) -> bool { + **self == REFCLK_A::XOSC + } + #[doc = "Checks if the value of the field is `GCLK`"] + #[inline(always)] + pub fn is_gclk(&self) -> bool { + **self == REFCLK_A::GCLK + } +} +impl core::ops::Deref for REFCLK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REFCLK` writer - Reference Clock Selection"] +pub struct REFCLK_W<'a> { + w: &'a mut W, +} +impl<'a> REFCLK_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: REFCLK_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "XOSC32K clock reference"] + #[inline(always)] + pub fn xosc32k(self) -> &'a mut W { + self.variant(REFCLK_A::XOSC32K) + } + #[doc = "XOSC clock reference"] + #[inline(always)] + pub fn xosc(self) -> &'a mut W { + self.variant(REFCLK_A::XOSC) + } + #[doc = "GCLK clock reference"] + #[inline(always)] + pub fn gclk(self) -> &'a mut W { + self.variant(REFCLK_A::GCLK) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u32 & 0x03) << 4); + self.w + } +} +#[doc = "Lock Time\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum LTIME_A { + #[doc = "0: No time-out. Automatic lock."] + DEFAULT = 0, + #[doc = "4: Time-out if no lock within 8ms"] + _8MS = 4, + #[doc = "5: Time-out if no lock within 9ms"] + _9MS = 5, + #[doc = "6: Time-out if no lock within 10ms"] + _10MS = 6, + #[doc = "7: Time-out if no lock within 11ms"] + _11MS = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LTIME_A) -> Self { + variant as _ + } +} +#[doc = "Field `LTIME` reader - Lock Time"] +pub struct LTIME_R(crate::FieldReader); +impl LTIME_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LTIME_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(LTIME_A::DEFAULT), + 4 => Some(LTIME_A::_8MS), + 5 => Some(LTIME_A::_9MS), + 6 => Some(LTIME_A::_10MS), + 7 => Some(LTIME_A::_11MS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DEFAULT`"] + #[inline(always)] + pub fn is_default(&self) -> bool { + **self == LTIME_A::DEFAULT + } + #[doc = "Checks if the value of the field is `_8MS`"] + #[inline(always)] + pub fn is_8ms(&self) -> bool { + **self == LTIME_A::_8MS + } + #[doc = "Checks if the value of the field is `_9MS`"] + #[inline(always)] + pub fn is_9ms(&self) -> bool { + **self == LTIME_A::_9MS + } + #[doc = "Checks if the value of the field is `_10MS`"] + #[inline(always)] + pub fn is_10ms(&self) -> bool { + **self == LTIME_A::_10MS + } + #[doc = "Checks if the value of the field is `_11MS`"] + #[inline(always)] + pub fn is_11ms(&self) -> bool { + **self == LTIME_A::_11MS + } +} +impl core::ops::Deref for LTIME_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LTIME` writer - Lock Time"] +pub struct LTIME_W<'a> { + w: &'a mut W, +} +impl<'a> LTIME_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: LTIME_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No time-out. Automatic lock."] + #[inline(always)] + pub fn default(self) -> &'a mut W { + self.variant(LTIME_A::DEFAULT) + } + #[doc = "Time-out if no lock within 8ms"] + #[inline(always)] + pub fn _8ms(self) -> &'a mut W { + self.variant(LTIME_A::_8MS) + } + #[doc = "Time-out if no lock within 9ms"] + #[inline(always)] + pub fn _9ms(self) -> &'a mut W { + self.variant(LTIME_A::_9MS) + } + #[doc = "Time-out if no lock within 10ms"] + #[inline(always)] + pub fn _10ms(self) -> &'a mut W { + self.variant(LTIME_A::_10MS) + } + #[doc = "Time-out if no lock within 11ms"] + #[inline(always)] + pub fn _11ms(self) -> &'a mut W { + self.variant(LTIME_A::_11MS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +#[doc = "Field `LBYPASS` reader - Lock Bypass"] +pub struct LBYPASS_R(crate::FieldReader); +impl LBYPASS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LBYPASS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LBYPASS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LBYPASS` writer - Lock Bypass"] +pub struct LBYPASS_W<'a> { + w: &'a mut W, +} +impl<'a> LBYPASS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `DIV` reader - Clock Divider"] +pub struct DIV_R(crate::FieldReader); +impl DIV_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + DIV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIV` writer - Clock Divider"] +pub struct DIV_W<'a> { + w: &'a mut W, +} +impl<'a> DIV_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07ff << 16)) | ((value as u32 & 0x07ff) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Proportional Integral Filter Selection"] + #[inline(always)] + pub fn filter(&self) -> FILTER_R { + FILTER_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bit 2 - Low-Power Enable"] + #[inline(always)] + pub fn lpen(&self) -> LPEN_R { + LPEN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Wake Up Fast"] + #[inline(always)] + pub fn wuf(&self) -> WUF_R { + WUF_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bits 4:5 - Reference Clock Selection"] + #[inline(always)] + pub fn refclk(&self) -> REFCLK_R { + REFCLK_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bits 8:10 - Lock Time"] + #[inline(always)] + pub fn ltime(&self) -> LTIME_R { + LTIME_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 12 - Lock Bypass"] + #[inline(always)] + pub fn lbypass(&self) -> LBYPASS_R { + LBYPASS_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bits 16:26 - Clock Divider"] + #[inline(always)] + pub fn div(&self) -> DIV_R { + DIV_R::new(((self.bits >> 16) & 0x07ff) as u16) + } +} +impl W { + #[doc = "Bits 0:1 - Proportional Integral Filter Selection"] + #[inline(always)] + pub fn filter(&mut self) -> FILTER_W { + FILTER_W { w: self } + } + #[doc = "Bit 2 - Low-Power Enable"] + #[inline(always)] + pub fn lpen(&mut self) -> LPEN_W { + LPEN_W { w: self } + } + #[doc = "Bit 3 - Wake Up Fast"] + #[inline(always)] + pub fn wuf(&mut self) -> WUF_W { + WUF_W { w: self } + } + #[doc = "Bits 4:5 - Reference Clock Selection"] + #[inline(always)] + pub fn refclk(&mut self) -> REFCLK_W { + REFCLK_W { w: self } + } + #[doc = "Bits 8:10 - Lock Time"] + #[inline(always)] + pub fn ltime(&mut self) -> LTIME_W { + LTIME_W { w: self } + } + #[doc = "Bit 12 - Lock Bypass"] + #[inline(always)] + pub fn lbypass(&mut self) -> LBYPASS_W { + LBYPASS_W { w: self } + } + #[doc = "Bits 16:26 - Clock Divider"] + #[inline(always)] + pub fn div(&mut self) -> DIV_W { + DIV_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Digital Core Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dpllctrlb](index.html) module"] +pub struct DPLLCTRLB_SPEC; +impl crate::RegisterSpec for DPLLCTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dpllctrlb::R](R) reader structure"] +impl crate::Readable for DPLLCTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dpllctrlb::W](W) writer structure"] +impl crate::Writable for DPLLCTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DPLLCTRLB to value 0"] +impl crate::Resettable for DPLLCTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/oscctrl/dpllpresc.rs b/pac/atsamc20e/src/oscctrl/dpllpresc.rs new file mode 100644 index 000000000000..9de662161f99 --- /dev/null +++ b/pac/atsamc20e/src/oscctrl/dpllpresc.rs @@ -0,0 +1,165 @@ +#[doc = "Register `DPLLPRESC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DPLLPRESC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Output Clock Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESC_A { + #[doc = "0: DPLL output is divided by 1"] + DIV1 = 0, + #[doc = "1: DPLL output is divided by 2"] + DIV2 = 1, + #[doc = "2: DPLL output is divided by 4"] + DIV4 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESC_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESC` reader - Output Clock Prescaler"] +pub struct PRESC_R(crate::FieldReader); +impl PRESC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESC_A::DIV1), + 1 => Some(PRESC_A::DIV2), + 2 => Some(PRESC_A::DIV4), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == PRESC_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESC_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESC_A::DIV4 + } +} +impl core::ops::Deref for PRESC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESC` writer - Output Clock Prescaler"] +pub struct PRESC_W<'a> { + w: &'a mut W, +} +impl<'a> PRESC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESC_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "DPLL output is divided by 1"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESC_A::DIV1) + } + #[doc = "DPLL output is divided by 2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESC_A::DIV2) + } + #[doc = "DPLL output is divided by 4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESC_A::DIV4) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u8 & 0x03); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Output Clock Prescaler"] + #[inline(always)] + pub fn presc(&self) -> PRESC_R { + PRESC_R::new((self.bits & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Output Clock Prescaler"] + #[inline(always)] + pub fn presc(&mut self) -> PRESC_W { + PRESC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DPLL Prescaler\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dpllpresc](index.html) module"] +pub struct DPLLPRESC_SPEC; +impl crate::RegisterSpec for DPLLPRESC_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dpllpresc::R](R) reader structure"] +impl crate::Readable for DPLLPRESC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dpllpresc::W](W) writer structure"] +impl crate::Writable for DPLLPRESC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DPLLPRESC to value 0"] +impl crate::Resettable for DPLLPRESC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/oscctrl/dpllratio.rs b/pac/atsamc20e/src/oscctrl/dpllratio.rs new file mode 100644 index 000000000000..93b39e30f1a5 --- /dev/null +++ b/pac/atsamc20e/src/oscctrl/dpllratio.rs @@ -0,0 +1,140 @@ +#[doc = "Register `DPLLRATIO` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DPLLRATIO` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `LDR` reader - Loop Divider Ratio"] +pub struct LDR_R(crate::FieldReader); +impl LDR_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + LDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LDR` writer - Loop Divider Ratio"] +pub struct LDR_W<'a> { + w: &'a mut W, +} +impl<'a> LDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0fff) | (value as u32 & 0x0fff); + self.w + } +} +#[doc = "Field `LDRFRAC` reader - Loop Divider Ratio Fractional Part"] +pub struct LDRFRAC_R(crate::FieldReader); +impl LDRFRAC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LDRFRAC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LDRFRAC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LDRFRAC` writer - Loop Divider Ratio Fractional Part"] +pub struct LDRFRAC_W<'a> { + w: &'a mut W, +} +impl<'a> LDRFRAC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 16)) | ((value as u32 & 0x0f) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:11 - Loop Divider Ratio"] + #[inline(always)] + pub fn ldr(&self) -> LDR_R { + LDR_R::new((self.bits & 0x0fff) as u16) + } + #[doc = "Bits 16:19 - Loop Divider Ratio Fractional Part"] + #[inline(always)] + pub fn ldrfrac(&self) -> LDRFRAC_R { + LDRFRAC_R::new(((self.bits >> 16) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:11 - Loop Divider Ratio"] + #[inline(always)] + pub fn ldr(&mut self) -> LDR_W { + LDR_W { w: self } + } + #[doc = "Bits 16:19 - Loop Divider Ratio Fractional Part"] + #[inline(always)] + pub fn ldrfrac(&mut self) -> LDRFRAC_W { + LDRFRAC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DPLL Ratio Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dpllratio](index.html) module"] +pub struct DPLLRATIO_SPEC; +impl crate::RegisterSpec for DPLLRATIO_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dpllratio::R](R) reader structure"] +impl crate::Readable for DPLLRATIO_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dpllratio::W](W) writer structure"] +impl crate::Writable for DPLLRATIO_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DPLLRATIO to value 0"] +impl crate::Resettable for DPLLRATIO_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/oscctrl/dpllstatus.rs b/pac/atsamc20e/src/oscctrl/dpllstatus.rs new file mode 100644 index 000000000000..931900212816 --- /dev/null +++ b/pac/atsamc20e/src/oscctrl/dpllstatus.rs @@ -0,0 +1,73 @@ +#[doc = "Register `DPLLSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `LOCK` reader - DPLL Lock Status"] +pub struct LOCK_R(crate::FieldReader); +impl LOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKRDY` reader - DPLL Clock Ready"] +pub struct CLKRDY_R(crate::FieldReader); +impl CLKRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - DPLL Lock Status"] + #[inline(always)] + pub fn lock(&self) -> LOCK_R { + LOCK_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - DPLL Clock Ready"] + #[inline(always)] + pub fn clkrdy(&self) -> CLKRDY_R { + CLKRDY_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +#[doc = "DPLL Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dpllstatus](index.html) module"] +pub struct DPLLSTATUS_SPEC; +impl crate::RegisterSpec for DPLLSTATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dpllstatus::R](R) reader structure"] +impl crate::Readable for DPLLSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DPLLSTATUS to value 0"] +impl crate::Resettable for DPLLSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/oscctrl/dpllsyncbusy.rs b/pac/atsamc20e/src/oscctrl/dpllsyncbusy.rs new file mode 100644 index 000000000000..f9fb880a5a59 --- /dev/null +++ b/pac/atsamc20e/src/oscctrl/dpllsyncbusy.rs @@ -0,0 +1,93 @@ +#[doc = "Register `DPLLSYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `ENABLE` reader - DPLL Enable Synchronization Status"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLRATIO` reader - DPLL Ratio Synchronization Status"] +pub struct DPLLRATIO_R(crate::FieldReader); +impl DPLLRATIO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLRATIO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLRATIO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLPRESC` reader - DPLL Prescaler Synchronization Status"] +pub struct DPLLPRESC_R(crate::FieldReader); +impl DPLLPRESC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLPRESC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLPRESC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 1 - DPLL Enable Synchronization Status"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - DPLL Ratio Synchronization Status"] + #[inline(always)] + pub fn dpllratio(&self) -> DPLLRATIO_R { + DPLLRATIO_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - DPLL Prescaler Synchronization Status"] + #[inline(always)] + pub fn dpllpresc(&self) -> DPLLPRESC_R { + DPLLPRESC_R::new(((self.bits >> 3) & 0x01) != 0) + } +} +#[doc = "DPLL Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dpllsyncbusy](index.html) module"] +pub struct DPLLSYNCBUSY_SPEC; +impl crate::RegisterSpec for DPLLSYNCBUSY_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dpllsyncbusy::R](R) reader structure"] +impl crate::Readable for DPLLSYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DPLLSYNCBUSY to value 0"] +impl crate::Resettable for DPLLSYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/oscctrl/evctrl.rs b/pac/atsamc20e/src/oscctrl/evctrl.rs new file mode 100644 index 000000000000..e22ba62f0fe2 --- /dev/null +++ b/pac/atsamc20e/src/oscctrl/evctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CFDEO` reader - Clock Failure Detector Event Output Enable"] +pub struct CFDEO_R(crate::FieldReader); +impl CFDEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFDEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFDEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFDEO` writer - Clock Failure Detector Event Output Enable"] +pub struct CFDEO_W<'a> { + w: &'a mut W, +} +impl<'a> CFDEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Clock Failure Detector Event Output Enable"] + #[inline(always)] + pub fn cfdeo(&self) -> CFDEO_R { + CFDEO_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Clock Failure Detector Event Output Enable"] + #[inline(always)] + pub fn cfdeo(&mut self) -> CFDEO_W { + CFDEO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/oscctrl/intenclr.rs b/pac/atsamc20e/src/oscctrl/intenclr.rs new file mode 100644 index 000000000000..0ea0034a0c02 --- /dev/null +++ b/pac/atsamc20e/src/oscctrl/intenclr.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XOSCRDY` reader - XOSC Ready Interrupt Enable"] +pub struct XOSCRDY_R(crate::FieldReader); +impl XOSCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSCRDY` writer - XOSC Ready Interrupt Enable"] +pub struct XOSCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> XOSCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `XOSCFAIL` reader - XOSC Clock Failure Detector Interrupt Enable"] +pub struct XOSCFAIL_R(crate::FieldReader); +impl XOSCFAIL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSCFAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCFAIL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSCFAIL` writer - XOSC Clock Failure Detector Interrupt Enable"] +pub struct XOSCFAIL_W<'a> { + w: &'a mut W, +} +impl<'a> XOSCFAIL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `OSC48MRDY` reader - OSC48M Ready Interrupt Enable"] +pub struct OSC48MRDY_R(crate::FieldReader); +impl OSC48MRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC48MRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC48MRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC48MRDY` writer - OSC48M Ready Interrupt Enable"] +pub struct OSC48MRDY_W<'a> { + w: &'a mut W, +} +impl<'a> OSC48MRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `DPLLLCKR` reader - DPLL Lock Rise Interrupt Enable"] +pub struct DPLLLCKR_R(crate::FieldReader); +impl DPLLLCKR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKR` writer - DPLL Lock Rise Interrupt Enable"] +pub struct DPLLLCKR_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLCKR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `DPLLLCKF` reader - DPLL Lock Fall Interrupt Enable"] +pub struct DPLLLCKF_R(crate::FieldReader); +impl DPLLLCKF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKF` writer - DPLL Lock Fall Interrupt Enable"] +pub struct DPLLLCKF_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLCKF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `DPLLLTO` reader - DPLL Time Out Interrupt Enable"] +pub struct DPLLLTO_R(crate::FieldReader); +impl DPLLLTO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLTO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLTO` writer - DPLL Time Out Interrupt Enable"] +pub struct DPLLLTO_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLTO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `DPLLLDRTO` reader - DPLL Ratio Ready Interrupt Enable"] +pub struct DPLLLDRTO_R(crate::FieldReader); +impl DPLLLDRTO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLDRTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLDRTO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLDRTO` writer - DPLL Ratio Ready Interrupt Enable"] +pub struct DPLLLDRTO_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLDRTO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +impl R { + #[doc = "Bit 0 - XOSC Ready Interrupt Enable"] + #[inline(always)] + pub fn xoscrdy(&self) -> XOSCRDY_R { + XOSCRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - XOSC Clock Failure Detector Interrupt Enable"] + #[inline(always)] + pub fn xoscfail(&self) -> XOSCFAIL_R { + XOSCFAIL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - OSC48M Ready Interrupt Enable"] + #[inline(always)] + pub fn osc48mrdy(&self) -> OSC48MRDY_R { + OSC48MRDY_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 8 - DPLL Lock Rise Interrupt Enable"] + #[inline(always)] + pub fn dplllckr(&self) -> DPLLLCKR_R { + DPLLLCKR_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - DPLL Lock Fall Interrupt Enable"] + #[inline(always)] + pub fn dplllckf(&self) -> DPLLLCKF_R { + DPLLLCKF_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - DPLL Time Out Interrupt Enable"] + #[inline(always)] + pub fn dplllto(&self) -> DPLLLTO_R { + DPLLLTO_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - DPLL Ratio Ready Interrupt Enable"] + #[inline(always)] + pub fn dpllldrto(&self) -> DPLLLDRTO_R { + DPLLLDRTO_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - XOSC Ready Interrupt Enable"] + #[inline(always)] + pub fn xoscrdy(&mut self) -> XOSCRDY_W { + XOSCRDY_W { w: self } + } + #[doc = "Bit 1 - XOSC Clock Failure Detector Interrupt Enable"] + #[inline(always)] + pub fn xoscfail(&mut self) -> XOSCFAIL_W { + XOSCFAIL_W { w: self } + } + #[doc = "Bit 4 - OSC48M Ready Interrupt Enable"] + #[inline(always)] + pub fn osc48mrdy(&mut self) -> OSC48MRDY_W { + OSC48MRDY_W { w: self } + } + #[doc = "Bit 8 - DPLL Lock Rise Interrupt Enable"] + #[inline(always)] + pub fn dplllckr(&mut self) -> DPLLLCKR_W { + DPLLLCKR_W { w: self } + } + #[doc = "Bit 9 - DPLL Lock Fall Interrupt Enable"] + #[inline(always)] + pub fn dplllckf(&mut self) -> DPLLLCKF_W { + DPLLLCKF_W { w: self } + } + #[doc = "Bit 10 - DPLL Time Out Interrupt Enable"] + #[inline(always)] + pub fn dplllto(&mut self) -> DPLLLTO_W { + DPLLLTO_W { w: self } + } + #[doc = "Bit 11 - DPLL Ratio Ready Interrupt Enable"] + #[inline(always)] + pub fn dpllldrto(&mut self) -> DPLLLDRTO_W { + DPLLLDRTO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/oscctrl/intenset.rs b/pac/atsamc20e/src/oscctrl/intenset.rs new file mode 100644 index 000000000000..2890541e4414 --- /dev/null +++ b/pac/atsamc20e/src/oscctrl/intenset.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XOSCRDY` reader - XOSC Ready Interrupt Enable"] +pub struct XOSCRDY_R(crate::FieldReader); +impl XOSCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSCRDY` writer - XOSC Ready Interrupt Enable"] +pub struct XOSCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> XOSCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `XOSCFAIL` reader - XOSC Clock Failure Detector Interrupt Enable"] +pub struct XOSCFAIL_R(crate::FieldReader); +impl XOSCFAIL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSCFAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCFAIL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSCFAIL` writer - XOSC Clock Failure Detector Interrupt Enable"] +pub struct XOSCFAIL_W<'a> { + w: &'a mut W, +} +impl<'a> XOSCFAIL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `OSC48MRDY` reader - OSC48M Ready Interrupt Enable"] +pub struct OSC48MRDY_R(crate::FieldReader); +impl OSC48MRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC48MRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC48MRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC48MRDY` writer - OSC48M Ready Interrupt Enable"] +pub struct OSC48MRDY_W<'a> { + w: &'a mut W, +} +impl<'a> OSC48MRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `DPLLLCKR` reader - DPLL Lock Rise Interrupt Enable"] +pub struct DPLLLCKR_R(crate::FieldReader); +impl DPLLLCKR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKR` writer - DPLL Lock Rise Interrupt Enable"] +pub struct DPLLLCKR_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLCKR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `DPLLLCKF` reader - DPLL Lock Fall Interrupt Enable"] +pub struct DPLLLCKF_R(crate::FieldReader); +impl DPLLLCKF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKF` writer - DPLL Lock Fall Interrupt Enable"] +pub struct DPLLLCKF_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLCKF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `DPLLLTO` reader - DPLL Time Out Interrupt Enable"] +pub struct DPLLLTO_R(crate::FieldReader); +impl DPLLLTO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLTO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLTO` writer - DPLL Time Out Interrupt Enable"] +pub struct DPLLLTO_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLTO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `DPLLLDRTO` reader - DPLL Ratio Ready Interrupt Enable"] +pub struct DPLLLDRTO_R(crate::FieldReader); +impl DPLLLDRTO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLDRTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLDRTO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLDRTO` writer - DPLL Ratio Ready Interrupt Enable"] +pub struct DPLLLDRTO_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLDRTO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +impl R { + #[doc = "Bit 0 - XOSC Ready Interrupt Enable"] + #[inline(always)] + pub fn xoscrdy(&self) -> XOSCRDY_R { + XOSCRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - XOSC Clock Failure Detector Interrupt Enable"] + #[inline(always)] + pub fn xoscfail(&self) -> XOSCFAIL_R { + XOSCFAIL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - OSC48M Ready Interrupt Enable"] + #[inline(always)] + pub fn osc48mrdy(&self) -> OSC48MRDY_R { + OSC48MRDY_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 8 - DPLL Lock Rise Interrupt Enable"] + #[inline(always)] + pub fn dplllckr(&self) -> DPLLLCKR_R { + DPLLLCKR_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - DPLL Lock Fall Interrupt Enable"] + #[inline(always)] + pub fn dplllckf(&self) -> DPLLLCKF_R { + DPLLLCKF_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - DPLL Time Out Interrupt Enable"] + #[inline(always)] + pub fn dplllto(&self) -> DPLLLTO_R { + DPLLLTO_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - DPLL Ratio Ready Interrupt Enable"] + #[inline(always)] + pub fn dpllldrto(&self) -> DPLLLDRTO_R { + DPLLLDRTO_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - XOSC Ready Interrupt Enable"] + #[inline(always)] + pub fn xoscrdy(&mut self) -> XOSCRDY_W { + XOSCRDY_W { w: self } + } + #[doc = "Bit 1 - XOSC Clock Failure Detector Interrupt Enable"] + #[inline(always)] + pub fn xoscfail(&mut self) -> XOSCFAIL_W { + XOSCFAIL_W { w: self } + } + #[doc = "Bit 4 - OSC48M Ready Interrupt Enable"] + #[inline(always)] + pub fn osc48mrdy(&mut self) -> OSC48MRDY_W { + OSC48MRDY_W { w: self } + } + #[doc = "Bit 8 - DPLL Lock Rise Interrupt Enable"] + #[inline(always)] + pub fn dplllckr(&mut self) -> DPLLLCKR_W { + DPLLLCKR_W { w: self } + } + #[doc = "Bit 9 - DPLL Lock Fall Interrupt Enable"] + #[inline(always)] + pub fn dplllckf(&mut self) -> DPLLLCKF_W { + DPLLLCKF_W { w: self } + } + #[doc = "Bit 10 - DPLL Time Out Interrupt Enable"] + #[inline(always)] + pub fn dplllto(&mut self) -> DPLLLTO_W { + DPLLLTO_W { w: self } + } + #[doc = "Bit 11 - DPLL Ratio Ready Interrupt Enable"] + #[inline(always)] + pub fn dpllldrto(&mut self) -> DPLLLDRTO_W { + DPLLLDRTO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/oscctrl/intflag.rs b/pac/atsamc20e/src/oscctrl/intflag.rs new file mode 100644 index 000000000000..71e452a1b571 --- /dev/null +++ b/pac/atsamc20e/src/oscctrl/intflag.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XOSCRDY` reader - XOSC Ready"] +pub struct XOSCRDY_R(crate::FieldReader); +impl XOSCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSCRDY` writer - XOSC Ready"] +pub struct XOSCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> XOSCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `XOSCFAIL` reader - XOSC Clock Failure Detector"] +pub struct XOSCFAIL_R(crate::FieldReader); +impl XOSCFAIL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSCFAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCFAIL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSCFAIL` writer - XOSC Clock Failure Detector"] +pub struct XOSCFAIL_W<'a> { + w: &'a mut W, +} +impl<'a> XOSCFAIL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `OSC48MRDY` reader - OSC48M Ready"] +pub struct OSC48MRDY_R(crate::FieldReader); +impl OSC48MRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC48MRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC48MRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC48MRDY` writer - OSC48M Ready"] +pub struct OSC48MRDY_W<'a> { + w: &'a mut W, +} +impl<'a> OSC48MRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `DPLLLCKR` reader - DPLL Lock Rise"] +pub struct DPLLLCKR_R(crate::FieldReader); +impl DPLLLCKR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKR` writer - DPLL Lock Rise"] +pub struct DPLLLCKR_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLCKR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `DPLLLCKF` reader - DPLL Lock Fall"] +pub struct DPLLLCKF_R(crate::FieldReader); +impl DPLLLCKF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKF` writer - DPLL Lock Fall"] +pub struct DPLLLCKF_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLCKF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `DPLLLTO` reader - DPLL Timeout"] +pub struct DPLLLTO_R(crate::FieldReader); +impl DPLLLTO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLTO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLTO` writer - DPLL Timeout"] +pub struct DPLLLTO_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLTO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `DPLLLDRTO` reader - DPLL Ratio Ready"] +pub struct DPLLLDRTO_R(crate::FieldReader); +impl DPLLLDRTO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLDRTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLDRTO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLDRTO` writer - DPLL Ratio Ready"] +pub struct DPLLLDRTO_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLDRTO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +impl R { + #[doc = "Bit 0 - XOSC Ready"] + #[inline(always)] + pub fn xoscrdy(&self) -> XOSCRDY_R { + XOSCRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - XOSC Clock Failure Detector"] + #[inline(always)] + pub fn xoscfail(&self) -> XOSCFAIL_R { + XOSCFAIL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - OSC48M Ready"] + #[inline(always)] + pub fn osc48mrdy(&self) -> OSC48MRDY_R { + OSC48MRDY_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 8 - DPLL Lock Rise"] + #[inline(always)] + pub fn dplllckr(&self) -> DPLLLCKR_R { + DPLLLCKR_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - DPLL Lock Fall"] + #[inline(always)] + pub fn dplllckf(&self) -> DPLLLCKF_R { + DPLLLCKF_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - DPLL Timeout"] + #[inline(always)] + pub fn dplllto(&self) -> DPLLLTO_R { + DPLLLTO_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - DPLL Ratio Ready"] + #[inline(always)] + pub fn dpllldrto(&self) -> DPLLLDRTO_R { + DPLLLDRTO_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - XOSC Ready"] + #[inline(always)] + pub fn xoscrdy(&mut self) -> XOSCRDY_W { + XOSCRDY_W { w: self } + } + #[doc = "Bit 1 - XOSC Clock Failure Detector"] + #[inline(always)] + pub fn xoscfail(&mut self) -> XOSCFAIL_W { + XOSCFAIL_W { w: self } + } + #[doc = "Bit 4 - OSC48M Ready"] + #[inline(always)] + pub fn osc48mrdy(&mut self) -> OSC48MRDY_W { + OSC48MRDY_W { w: self } + } + #[doc = "Bit 8 - DPLL Lock Rise"] + #[inline(always)] + pub fn dplllckr(&mut self) -> DPLLLCKR_W { + DPLLLCKR_W { w: self } + } + #[doc = "Bit 9 - DPLL Lock Fall"] + #[inline(always)] + pub fn dplllckf(&mut self) -> DPLLLCKF_W { + DPLLLCKF_W { w: self } + } + #[doc = "Bit 10 - DPLL Timeout"] + #[inline(always)] + pub fn dplllto(&mut self) -> DPLLLTO_W { + DPLLLTO_W { w: self } + } + #[doc = "Bit 11 - DPLL Ratio Ready"] + #[inline(always)] + pub fn dpllldrto(&mut self) -> DPLLLDRTO_W { + DPLLLDRTO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/oscctrl/osc48mctrl.rs b/pac/atsamc20e/src/oscctrl/osc48mctrl.rs new file mode 100644 index 000000000000..8314e21e5775 --- /dev/null +++ b/pac/atsamc20e/src/oscctrl/osc48mctrl.rs @@ -0,0 +1,207 @@ +#[doc = "Register `OSC48MCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OSC48MCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Oscillator Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Oscillator Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - On Demand Control"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - On Demand Control"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "48MHz Internal Oscillator (OSC48M) Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [osc48mctrl](index.html) module"] +pub struct OSC48MCTRL_SPEC; +impl crate::RegisterSpec for OSC48MCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [osc48mctrl::R](R) reader structure"] +impl crate::Readable for OSC48MCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [osc48mctrl::W](W) writer structure"] +impl crate::Writable for OSC48MCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OSC48MCTRL to value 0x82"] +impl crate::Resettable for OSC48MCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x82 + } +} diff --git a/pac/atsamc20e/src/oscctrl/osc48mdiv.rs b/pac/atsamc20e/src/oscctrl/osc48mdiv.rs new file mode 100644 index 000000000000..4ed854b09284 --- /dev/null +++ b/pac/atsamc20e/src/oscctrl/osc48mdiv.rs @@ -0,0 +1,334 @@ +#[doc = "Register `OSC48MDIV` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OSC48MDIV` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "OSC48M Division Factor\n\nValue on reset: 11"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DIV_A { + #[doc = "0: 48 MHz"] + DIV1 = 0, + #[doc = "1: 24 MHz"] + DIV2 = 1, + #[doc = "2: 16 MHz"] + DIV3 = 2, + #[doc = "3: 12 MHz"] + DIV4 = 3, + #[doc = "4: 9.6 MHz"] + DIV5 = 4, + #[doc = "5: 8 MHz"] + DIV6 = 5, + #[doc = "6: 6.86 MHz"] + DIV7 = 6, + #[doc = "7: 6 MHz"] + DIV8 = 7, + #[doc = "8: 5.33 MHz"] + DIV9 = 8, + #[doc = "9: 4.8 MHz"] + DIV10 = 9, + #[doc = "10: 4.36 MHz"] + DIV11 = 10, + #[doc = "11: 4 MHz"] + DIV12 = 11, + #[doc = "12: 3.69 MHz"] + DIV13 = 12, + #[doc = "13: 3.43 MHz"] + DIV14 = 13, + #[doc = "14: 3.2 MHz"] + DIV15 = 14, + #[doc = "15: 3 MHz"] + DIV16 = 15, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DIV_A) -> Self { + variant as _ + } +} +#[doc = "Field `DIV` reader - OSC48M Division Factor"] +pub struct DIV_R(crate::FieldReader); +impl DIV_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DIV_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DIV_A { + match self.bits { + 0 => DIV_A::DIV1, + 1 => DIV_A::DIV2, + 2 => DIV_A::DIV3, + 3 => DIV_A::DIV4, + 4 => DIV_A::DIV5, + 5 => DIV_A::DIV6, + 6 => DIV_A::DIV7, + 7 => DIV_A::DIV8, + 8 => DIV_A::DIV9, + 9 => DIV_A::DIV10, + 10 => DIV_A::DIV11, + 11 => DIV_A::DIV12, + 12 => DIV_A::DIV13, + 13 => DIV_A::DIV14, + 14 => DIV_A::DIV15, + 15 => DIV_A::DIV16, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == DIV_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == DIV_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV3`"] + #[inline(always)] + pub fn is_div3(&self) -> bool { + **self == DIV_A::DIV3 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == DIV_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV5`"] + #[inline(always)] + pub fn is_div5(&self) -> bool { + **self == DIV_A::DIV5 + } + #[doc = "Checks if the value of the field is `DIV6`"] + #[inline(always)] + pub fn is_div6(&self) -> bool { + **self == DIV_A::DIV6 + } + #[doc = "Checks if the value of the field is `DIV7`"] + #[inline(always)] + pub fn is_div7(&self) -> bool { + **self == DIV_A::DIV7 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == DIV_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV9`"] + #[inline(always)] + pub fn is_div9(&self) -> bool { + **self == DIV_A::DIV9 + } + #[doc = "Checks if the value of the field is `DIV10`"] + #[inline(always)] + pub fn is_div10(&self) -> bool { + **self == DIV_A::DIV10 + } + #[doc = "Checks if the value of the field is `DIV11`"] + #[inline(always)] + pub fn is_div11(&self) -> bool { + **self == DIV_A::DIV11 + } + #[doc = "Checks if the value of the field is `DIV12`"] + #[inline(always)] + pub fn is_div12(&self) -> bool { + **self == DIV_A::DIV12 + } + #[doc = "Checks if the value of the field is `DIV13`"] + #[inline(always)] + pub fn is_div13(&self) -> bool { + **self == DIV_A::DIV13 + } + #[doc = "Checks if the value of the field is `DIV14`"] + #[inline(always)] + pub fn is_div14(&self) -> bool { + **self == DIV_A::DIV14 + } + #[doc = "Checks if the value of the field is `DIV15`"] + #[inline(always)] + pub fn is_div15(&self) -> bool { + **self == DIV_A::DIV15 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == DIV_A::DIV16 + } +} +impl core::ops::Deref for DIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIV` writer - OSC48M Division Factor"] +pub struct DIV_W<'a> { + w: &'a mut W, +} +impl<'a> DIV_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DIV_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "48 MHz"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(DIV_A::DIV1) + } + #[doc = "24 MHz"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(DIV_A::DIV2) + } + #[doc = "16 MHz"] + #[inline(always)] + pub fn div3(self) -> &'a mut W { + self.variant(DIV_A::DIV3) + } + #[doc = "12 MHz"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(DIV_A::DIV4) + } + #[doc = "9.6 MHz"] + #[inline(always)] + pub fn div5(self) -> &'a mut W { + self.variant(DIV_A::DIV5) + } + #[doc = "8 MHz"] + #[inline(always)] + pub fn div6(self) -> &'a mut W { + self.variant(DIV_A::DIV6) + } + #[doc = "6.86 MHz"] + #[inline(always)] + pub fn div7(self) -> &'a mut W { + self.variant(DIV_A::DIV7) + } + #[doc = "6 MHz"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(DIV_A::DIV8) + } + #[doc = "5.33 MHz"] + #[inline(always)] + pub fn div9(self) -> &'a mut W { + self.variant(DIV_A::DIV9) + } + #[doc = "4.8 MHz"] + #[inline(always)] + pub fn div10(self) -> &'a mut W { + self.variant(DIV_A::DIV10) + } + #[doc = "4.36 MHz"] + #[inline(always)] + pub fn div11(self) -> &'a mut W { + self.variant(DIV_A::DIV11) + } + #[doc = "4 MHz"] + #[inline(always)] + pub fn div12(self) -> &'a mut W { + self.variant(DIV_A::DIV12) + } + #[doc = "3.69 MHz"] + #[inline(always)] + pub fn div13(self) -> &'a mut W { + self.variant(DIV_A::DIV13) + } + #[doc = "3.43 MHz"] + #[inline(always)] + pub fn div14(self) -> &'a mut W { + self.variant(DIV_A::DIV14) + } + #[doc = "3.2 MHz"] + #[inline(always)] + pub fn div15(self) -> &'a mut W { + self.variant(DIV_A::DIV15) + } + #[doc = "3 MHz"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(DIV_A::DIV16) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - OSC48M Division Factor"] + #[inline(always)] + pub fn div(&self) -> DIV_R { + DIV_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - OSC48M Division Factor"] + #[inline(always)] + pub fn div(&mut self) -> DIV_W { + DIV_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OSC48M Divider\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [osc48mdiv](index.html) module"] +pub struct OSC48MDIV_SPEC; +impl crate::RegisterSpec for OSC48MDIV_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [osc48mdiv::R](R) reader structure"] +impl crate::Readable for OSC48MDIV_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [osc48mdiv::W](W) writer structure"] +impl crate::Writable for OSC48MDIV_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OSC48MDIV to value 0x0b"] +impl crate::Resettable for OSC48MDIV_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0b + } +} diff --git a/pac/atsamc20e/src/oscctrl/osc48mstup.rs b/pac/atsamc20e/src/oscctrl/osc48mstup.rs new file mode 100644 index 000000000000..34da6bb7ef11 --- /dev/null +++ b/pac/atsamc20e/src/oscctrl/osc48mstup.rs @@ -0,0 +1,230 @@ +#[doc = "Register `OSC48MSTUP` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OSC48MSTUP` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Startup Time\n\nValue on reset: 7"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum STARTUP_A { + #[doc = "0: 166 ns"] + CYCLE8 = 0, + #[doc = "1: 333 ns"] + CYCLE16 = 1, + #[doc = "2: 667 ns"] + CYCLE32 = 2, + #[doc = "3: 1.333 us"] + CYCLE64 = 3, + #[doc = "4: 2.667 us"] + CYCLE128 = 4, + #[doc = "5: 5.333 us"] + CYCLE256 = 5, + #[doc = "6: 10.667 us"] + CYCLE512 = 6, + #[doc = "7: 21.333 us"] + CYCLE1024 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: STARTUP_A) -> Self { + variant as _ + } +} +#[doc = "Field `STARTUP` reader - Startup Time"] +pub struct STARTUP_R(crate::FieldReader); +impl STARTUP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + STARTUP_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STARTUP_A { + match self.bits { + 0 => STARTUP_A::CYCLE8, + 1 => STARTUP_A::CYCLE16, + 2 => STARTUP_A::CYCLE32, + 3 => STARTUP_A::CYCLE64, + 4 => STARTUP_A::CYCLE128, + 5 => STARTUP_A::CYCLE256, + 6 => STARTUP_A::CYCLE512, + 7 => STARTUP_A::CYCLE1024, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `CYCLE8`"] + #[inline(always)] + pub fn is_cycle8(&self) -> bool { + **self == STARTUP_A::CYCLE8 + } + #[doc = "Checks if the value of the field is `CYCLE16`"] + #[inline(always)] + pub fn is_cycle16(&self) -> bool { + **self == STARTUP_A::CYCLE16 + } + #[doc = "Checks if the value of the field is `CYCLE32`"] + #[inline(always)] + pub fn is_cycle32(&self) -> bool { + **self == STARTUP_A::CYCLE32 + } + #[doc = "Checks if the value of the field is `CYCLE64`"] + #[inline(always)] + pub fn is_cycle64(&self) -> bool { + **self == STARTUP_A::CYCLE64 + } + #[doc = "Checks if the value of the field is `CYCLE128`"] + #[inline(always)] + pub fn is_cycle128(&self) -> bool { + **self == STARTUP_A::CYCLE128 + } + #[doc = "Checks if the value of the field is `CYCLE256`"] + #[inline(always)] + pub fn is_cycle256(&self) -> bool { + **self == STARTUP_A::CYCLE256 + } + #[doc = "Checks if the value of the field is `CYCLE512`"] + #[inline(always)] + pub fn is_cycle512(&self) -> bool { + **self == STARTUP_A::CYCLE512 + } + #[doc = "Checks if the value of the field is `CYCLE1024`"] + #[inline(always)] + pub fn is_cycle1024(&self) -> bool { + **self == STARTUP_A::CYCLE1024 + } +} +impl core::ops::Deref for STARTUP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STARTUP` writer - Startup Time"] +pub struct STARTUP_W<'a> { + w: &'a mut W, +} +impl<'a> STARTUP_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: STARTUP_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "166 ns"] + #[inline(always)] + pub fn cycle8(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE8) + } + #[doc = "333 ns"] + #[inline(always)] + pub fn cycle16(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE16) + } + #[doc = "667 ns"] + #[inline(always)] + pub fn cycle32(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE32) + } + #[doc = "1.333 us"] + #[inline(always)] + pub fn cycle64(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE64) + } + #[doc = "2.667 us"] + #[inline(always)] + pub fn cycle128(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE128) + } + #[doc = "5.333 us"] + #[inline(always)] + pub fn cycle256(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE256) + } + #[doc = "10.667 us"] + #[inline(always)] + pub fn cycle512(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE512) + } + #[doc = "21.333 us"] + #[inline(always)] + pub fn cycle1024(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Startup Time"] + #[inline(always)] + pub fn startup(&self) -> STARTUP_R { + STARTUP_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Startup Time"] + #[inline(always)] + pub fn startup(&mut self) -> STARTUP_W { + STARTUP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OSC48M Startup Time\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [osc48mstup](index.html) module"] +pub struct OSC48MSTUP_SPEC; +impl crate::RegisterSpec for OSC48MSTUP_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [osc48mstup::R](R) reader structure"] +impl crate::Readable for OSC48MSTUP_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [osc48mstup::W](W) writer structure"] +impl crate::Writable for OSC48MSTUP_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OSC48MSTUP to value 0x07"] +impl crate::Resettable for OSC48MSTUP_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x07 + } +} diff --git a/pac/atsamc20e/src/oscctrl/osc48msyncbusy.rs b/pac/atsamc20e/src/oscctrl/osc48msyncbusy.rs new file mode 100644 index 000000000000..8d4410ae630a --- /dev/null +++ b/pac/atsamc20e/src/oscctrl/osc48msyncbusy.rs @@ -0,0 +1,53 @@ +#[doc = "Register `OSC48MSYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `OSC48MDIV` reader - OSC48MDIV Synchronization Status"] +pub struct OSC48MDIV_R(crate::FieldReader); +impl OSC48MDIV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC48MDIV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC48MDIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 2 - OSC48MDIV Synchronization Status"] + #[inline(always)] + pub fn osc48mdiv(&self) -> OSC48MDIV_R { + OSC48MDIV_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +#[doc = "OSC48M Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [osc48msyncbusy](index.html) module"] +pub struct OSC48MSYNCBUSY_SPEC; +impl crate::RegisterSpec for OSC48MSYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [osc48msyncbusy::R](R) reader structure"] +impl crate::Readable for OSC48MSYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets OSC48MSYNCBUSY to value 0"] +impl crate::Resettable for OSC48MSYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/oscctrl/status.rs b/pac/atsamc20e/src/oscctrl/status.rs new file mode 100644 index 000000000000..3025966192a3 --- /dev/null +++ b/pac/atsamc20e/src/oscctrl/status.rs @@ -0,0 +1,193 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `XOSCRDY` reader - XOSC Ready"] +pub struct XOSCRDY_R(crate::FieldReader); +impl XOSCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSCFAIL` reader - XOSC Clock Failure Detector"] +pub struct XOSCFAIL_R(crate::FieldReader); +impl XOSCFAIL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSCFAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCFAIL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSCCKSW` reader - XOSC Clock Switch"] +pub struct XOSCCKSW_R(crate::FieldReader); +impl XOSCCKSW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSCCKSW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCCKSW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC48MRDY` reader - OSC48M Ready"] +pub struct OSC48MRDY_R(crate::FieldReader); +impl OSC48MRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC48MRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC48MRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKR` reader - DPLL Lock Rise"] +pub struct DPLLLCKR_R(crate::FieldReader); +impl DPLLLCKR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKF` reader - DPLL Lock Fall"] +pub struct DPLLLCKF_R(crate::FieldReader); +impl DPLLLCKF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLTO` reader - DPLL Timeout"] +pub struct DPLLTO_R(crate::FieldReader); +impl DPLLTO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLTO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLDRTO` reader - DPLL Ratio Ready"] +pub struct DPLLLDRTO_R(crate::FieldReader); +impl DPLLLDRTO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLDRTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLDRTO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - XOSC Ready"] + #[inline(always)] + pub fn xoscrdy(&self) -> XOSCRDY_R { + XOSCRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - XOSC Clock Failure Detector"] + #[inline(always)] + pub fn xoscfail(&self) -> XOSCFAIL_R { + XOSCFAIL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - XOSC Clock Switch"] + #[inline(always)] + pub fn xosccksw(&self) -> XOSCCKSW_R { + XOSCCKSW_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 4 - OSC48M Ready"] + #[inline(always)] + pub fn osc48mrdy(&self) -> OSC48MRDY_R { + OSC48MRDY_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 8 - DPLL Lock Rise"] + #[inline(always)] + pub fn dplllckr(&self) -> DPLLLCKR_R { + DPLLLCKR_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - DPLL Lock Fall"] + #[inline(always)] + pub fn dplllckf(&self) -> DPLLLCKF_R { + DPLLLCKF_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - DPLL Timeout"] + #[inline(always)] + pub fn dpllto(&self) -> DPLLTO_R { + DPLLTO_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - DPLL Ratio Ready"] + #[inline(always)] + pub fn dpllldrto(&self) -> DPLLLDRTO_R { + DPLLLDRTO_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +#[doc = "Power and Clocks Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/oscctrl/xoscctrl.rs b/pac/atsamc20e/src/oscctrl/xoscctrl.rs new file mode 100644 index 000000000000..3a5319565c10 --- /dev/null +++ b/pac/atsamc20e/src/oscctrl/xoscctrl.rs @@ -0,0 +1,788 @@ +#[doc = "Register `XOSCCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `XOSCCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Oscillator Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Oscillator Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `XTALEN` reader - Crystal Oscillator Enable"] +pub struct XTALEN_R(crate::FieldReader); +impl XTALEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XTALEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XTALEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XTALEN` writer - Crystal Oscillator Enable"] +pub struct XTALEN_W<'a> { + w: &'a mut W, +} +impl<'a> XTALEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CFDEN` reader - Xosc Clock Failure Detector Enable"] +pub struct CFDEN_R(crate::FieldReader); +impl CFDEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFDEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFDEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFDEN` writer - Xosc Clock Failure Detector Enable"] +pub struct CFDEN_W<'a> { + w: &'a mut W, +} +impl<'a> CFDEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `SWBEN` reader - Xosc Clock Switch Enable"] +pub struct SWBEN_R(crate::FieldReader); +impl SWBEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWBEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWBEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWBEN` writer - Xosc Clock Switch Enable"] +pub struct SWBEN_W<'a> { + w: &'a mut W, +} +impl<'a> SWBEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - On Demand Control"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - On Demand Control"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Oscillator Gain\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum GAIN_A { + #[doc = "0: 2 MHz"] + GAIN2 = 0, + #[doc = "1: 4 MHz"] + GAIN4 = 1, + #[doc = "2: 8 MHz"] + GAIN8 = 2, + #[doc = "3: 16 MHz"] + GAIN16 = 3, + #[doc = "4: 30 MHz"] + GAIN30 = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: GAIN_A) -> Self { + variant as _ + } +} +#[doc = "Field `GAIN` reader - Oscillator Gain"] +pub struct GAIN_R(crate::FieldReader); +impl GAIN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + GAIN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(GAIN_A::GAIN2), + 1 => Some(GAIN_A::GAIN4), + 2 => Some(GAIN_A::GAIN8), + 3 => Some(GAIN_A::GAIN16), + 4 => Some(GAIN_A::GAIN30), + _ => None, + } + } + #[doc = "Checks if the value of the field is `GAIN2`"] + #[inline(always)] + pub fn is_gain2(&self) -> bool { + **self == GAIN_A::GAIN2 + } + #[doc = "Checks if the value of the field is `GAIN4`"] + #[inline(always)] + pub fn is_gain4(&self) -> bool { + **self == GAIN_A::GAIN4 + } + #[doc = "Checks if the value of the field is `GAIN8`"] + #[inline(always)] + pub fn is_gain8(&self) -> bool { + **self == GAIN_A::GAIN8 + } + #[doc = "Checks if the value of the field is `GAIN16`"] + #[inline(always)] + pub fn is_gain16(&self) -> bool { + **self == GAIN_A::GAIN16 + } + #[doc = "Checks if the value of the field is `GAIN30`"] + #[inline(always)] + pub fn is_gain30(&self) -> bool { + **self == GAIN_A::GAIN30 + } +} +impl core::ops::Deref for GAIN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GAIN` writer - Oscillator Gain"] +pub struct GAIN_W<'a> { + w: &'a mut W, +} +impl<'a> GAIN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: GAIN_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "2 MHz"] + #[inline(always)] + pub fn gain2(self) -> &'a mut W { + self.variant(GAIN_A::GAIN2) + } + #[doc = "4 MHz"] + #[inline(always)] + pub fn gain4(self) -> &'a mut W { + self.variant(GAIN_A::GAIN4) + } + #[doc = "8 MHz"] + #[inline(always)] + pub fn gain8(self) -> &'a mut W { + self.variant(GAIN_A::GAIN8) + } + #[doc = "16 MHz"] + #[inline(always)] + pub fn gain16(self) -> &'a mut W { + self.variant(GAIN_A::GAIN16) + } + #[doc = "30 MHz"] + #[inline(always)] + pub fn gain30(self) -> &'a mut W { + self.variant(GAIN_A::GAIN30) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u16 & 0x07) << 8); + self.w + } +} +#[doc = "Field `AMPGC` reader - Automatic Amplitude Gain Control"] +pub struct AMPGC_R(crate::FieldReader); +impl AMPGC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AMPGC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AMPGC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AMPGC` writer - Automatic Amplitude Gain Control"] +pub struct AMPGC_W<'a> { + w: &'a mut W, +} +impl<'a> AMPGC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u16 & 0x01) << 11); + self.w + } +} +#[doc = "Start-Up Time\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum STARTUP_A { + #[doc = "0: 31 us"] + CYCLE1 = 0, + #[doc = "1: 61 us"] + CYCLE2 = 1, + #[doc = "2: 122 us"] + CYCLE4 = 2, + #[doc = "3: 244 us"] + CYCLE8 = 3, + #[doc = "4: 488 us"] + CYCLE16 = 4, + #[doc = "5: 977 us"] + CYCLE32 = 5, + #[doc = "6: 1953 us"] + CYCLE64 = 6, + #[doc = "7: 3906 us"] + CYCLE128 = 7, + #[doc = "8: 7813 us"] + CYCLE256 = 8, + #[doc = "9: 15625 us"] + CYCLE512 = 9, + #[doc = "10: 31250 us"] + CYCLE1024 = 10, + #[doc = "11: 62500 us"] + CYCLE2048 = 11, + #[doc = "12: 125000 us"] + CYCLE4096 = 12, + #[doc = "13: 250000 us"] + CYCLE8192 = 13, + #[doc = "14: 500000 us"] + CYCLE16384 = 14, + #[doc = "15: 1000000 us"] + CYCLE32768 = 15, +} +impl From for u8 { + #[inline(always)] + fn from(variant: STARTUP_A) -> Self { + variant as _ + } +} +#[doc = "Field `STARTUP` reader - Start-Up Time"] +pub struct STARTUP_R(crate::FieldReader); +impl STARTUP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + STARTUP_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STARTUP_A { + match self.bits { + 0 => STARTUP_A::CYCLE1, + 1 => STARTUP_A::CYCLE2, + 2 => STARTUP_A::CYCLE4, + 3 => STARTUP_A::CYCLE8, + 4 => STARTUP_A::CYCLE16, + 5 => STARTUP_A::CYCLE32, + 6 => STARTUP_A::CYCLE64, + 7 => STARTUP_A::CYCLE128, + 8 => STARTUP_A::CYCLE256, + 9 => STARTUP_A::CYCLE512, + 10 => STARTUP_A::CYCLE1024, + 11 => STARTUP_A::CYCLE2048, + 12 => STARTUP_A::CYCLE4096, + 13 => STARTUP_A::CYCLE8192, + 14 => STARTUP_A::CYCLE16384, + 15 => STARTUP_A::CYCLE32768, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `CYCLE1`"] + #[inline(always)] + pub fn is_cycle1(&self) -> bool { + **self == STARTUP_A::CYCLE1 + } + #[doc = "Checks if the value of the field is `CYCLE2`"] + #[inline(always)] + pub fn is_cycle2(&self) -> bool { + **self == STARTUP_A::CYCLE2 + } + #[doc = "Checks if the value of the field is `CYCLE4`"] + #[inline(always)] + pub fn is_cycle4(&self) -> bool { + **self == STARTUP_A::CYCLE4 + } + #[doc = "Checks if the value of the field is `CYCLE8`"] + #[inline(always)] + pub fn is_cycle8(&self) -> bool { + **self == STARTUP_A::CYCLE8 + } + #[doc = "Checks if the value of the field is `CYCLE16`"] + #[inline(always)] + pub fn is_cycle16(&self) -> bool { + **self == STARTUP_A::CYCLE16 + } + #[doc = "Checks if the value of the field is `CYCLE32`"] + #[inline(always)] + pub fn is_cycle32(&self) -> bool { + **self == STARTUP_A::CYCLE32 + } + #[doc = "Checks if the value of the field is `CYCLE64`"] + #[inline(always)] + pub fn is_cycle64(&self) -> bool { + **self == STARTUP_A::CYCLE64 + } + #[doc = "Checks if the value of the field is `CYCLE128`"] + #[inline(always)] + pub fn is_cycle128(&self) -> bool { + **self == STARTUP_A::CYCLE128 + } + #[doc = "Checks if the value of the field is `CYCLE256`"] + #[inline(always)] + pub fn is_cycle256(&self) -> bool { + **self == STARTUP_A::CYCLE256 + } + #[doc = "Checks if the value of the field is `CYCLE512`"] + #[inline(always)] + pub fn is_cycle512(&self) -> bool { + **self == STARTUP_A::CYCLE512 + } + #[doc = "Checks if the value of the field is `CYCLE1024`"] + #[inline(always)] + pub fn is_cycle1024(&self) -> bool { + **self == STARTUP_A::CYCLE1024 + } + #[doc = "Checks if the value of the field is `CYCLE2048`"] + #[inline(always)] + pub fn is_cycle2048(&self) -> bool { + **self == STARTUP_A::CYCLE2048 + } + #[doc = "Checks if the value of the field is `CYCLE4096`"] + #[inline(always)] + pub fn is_cycle4096(&self) -> bool { + **self == STARTUP_A::CYCLE4096 + } + #[doc = "Checks if the value of the field is `CYCLE8192`"] + #[inline(always)] + pub fn is_cycle8192(&self) -> bool { + **self == STARTUP_A::CYCLE8192 + } + #[doc = "Checks if the value of the field is `CYCLE16384`"] + #[inline(always)] + pub fn is_cycle16384(&self) -> bool { + **self == STARTUP_A::CYCLE16384 + } + #[doc = "Checks if the value of the field is `CYCLE32768`"] + #[inline(always)] + pub fn is_cycle32768(&self) -> bool { + **self == STARTUP_A::CYCLE32768 + } +} +impl core::ops::Deref for STARTUP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STARTUP` writer - Start-Up Time"] +pub struct STARTUP_W<'a> { + w: &'a mut W, +} +impl<'a> STARTUP_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: STARTUP_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "31 us"] + #[inline(always)] + pub fn cycle1(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE1) + } + #[doc = "61 us"] + #[inline(always)] + pub fn cycle2(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE2) + } + #[doc = "122 us"] + #[inline(always)] + pub fn cycle4(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE4) + } + #[doc = "244 us"] + #[inline(always)] + pub fn cycle8(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE8) + } + #[doc = "488 us"] + #[inline(always)] + pub fn cycle16(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE16) + } + #[doc = "977 us"] + #[inline(always)] + pub fn cycle32(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE32) + } + #[doc = "1953 us"] + #[inline(always)] + pub fn cycle64(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE64) + } + #[doc = "3906 us"] + #[inline(always)] + pub fn cycle128(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE128) + } + #[doc = "7813 us"] + #[inline(always)] + pub fn cycle256(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE256) + } + #[doc = "15625 us"] + #[inline(always)] + pub fn cycle512(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE512) + } + #[doc = "31250 us"] + #[inline(always)] + pub fn cycle1024(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE1024) + } + #[doc = "62500 us"] + #[inline(always)] + pub fn cycle2048(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE2048) + } + #[doc = "125000 us"] + #[inline(always)] + pub fn cycle4096(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE4096) + } + #[doc = "250000 us"] + #[inline(always)] + pub fn cycle8192(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE8192) + } + #[doc = "500000 us"] + #[inline(always)] + pub fn cycle16384(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE16384) + } + #[doc = "1000000 us"] + #[inline(always)] + pub fn cycle32768(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE32768) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 12)) | ((value as u16 & 0x0f) << 12); + self.w + } +} +impl R { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Crystal Oscillator Enable"] + #[inline(always)] + pub fn xtalen(&self) -> XTALEN_R { + XTALEN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Xosc Clock Failure Detector Enable"] + #[inline(always)] + pub fn cfden(&self) -> CFDEN_R { + CFDEN_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Xosc Clock Switch Enable"] + #[inline(always)] + pub fn swben(&self) -> SWBEN_R { + SWBEN_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Oscillator Gain"] + #[inline(always)] + pub fn gain(&self) -> GAIN_R { + GAIN_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 11 - Automatic Amplitude Gain Control"] + #[inline(always)] + pub fn ampgc(&self) -> AMPGC_R { + AMPGC_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bits 12:15 - Start-Up Time"] + #[inline(always)] + pub fn startup(&self) -> STARTUP_R { + STARTUP_R::new(((self.bits >> 12) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - Crystal Oscillator Enable"] + #[inline(always)] + pub fn xtalen(&mut self) -> XTALEN_W { + XTALEN_W { w: self } + } + #[doc = "Bit 3 - Xosc Clock Failure Detector Enable"] + #[inline(always)] + pub fn cfden(&mut self) -> CFDEN_W { + CFDEN_W { w: self } + } + #[doc = "Bit 4 - Xosc Clock Switch Enable"] + #[inline(always)] + pub fn swben(&mut self) -> SWBEN_W { + SWBEN_W { w: self } + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Bits 8:10 - Oscillator Gain"] + #[inline(always)] + pub fn gain(&mut self) -> GAIN_W { + GAIN_W { w: self } + } + #[doc = "Bit 11 - Automatic Amplitude Gain Control"] + #[inline(always)] + pub fn ampgc(&mut self) -> AMPGC_W { + AMPGC_W { w: self } + } + #[doc = "Bits 12:15 - Start-Up Time"] + #[inline(always)] + pub fn startup(&mut self) -> STARTUP_W { + STARTUP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "External Multipurpose Crystal Oscillator (XOSC) Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [xoscctrl](index.html) module"] +pub struct XOSCCTRL_SPEC; +impl crate::RegisterSpec for XOSCCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [xoscctrl::R](R) reader structure"] +impl crate::Readable for XOSCCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [xoscctrl::W](W) writer structure"] +impl crate::Writable for XOSCCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets XOSCCTRL to value 0x80"] +impl crate::Resettable for XOSCCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x80 + } +} diff --git a/pac/atsamc20e/src/pac.rs b/pac/atsamc20e/src/pac.rs new file mode 100644 index 000000000000..3e365e081945 --- /dev/null +++ b/pac/atsamc20e/src/pac.rs @@ -0,0 +1,73 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Write control"] + pub wrctrl: crate::Reg, + #[doc = "0x04 - Event control"] + pub evctrl: crate::Reg, + _reserved2: [u8; 0x03], + #[doc = "0x08 - Interrupt enable clear"] + pub intenclr: crate::Reg, + #[doc = "0x09 - Interrupt enable set"] + pub intenset: crate::Reg, + _reserved4: [u8; 0x06], + #[doc = "0x10 - Bridge interrupt flag status"] + pub intflagahb: crate::Reg, + #[doc = "0x14 - Peripheral interrupt flag status - Bridge A"] + pub intflaga: crate::Reg, + #[doc = "0x18 - Peripheral interrupt flag status - Bridge B"] + pub intflagb: crate::Reg, + #[doc = "0x1c - Peripheral interrupt flag status - Bridge C"] + pub intflagc: crate::Reg, + _reserved8: [u8; 0x14], + #[doc = "0x34 - Peripheral write protection status - Bridge A"] + pub statusa: crate::Reg, + #[doc = "0x38 - Peripheral write protection status - Bridge B"] + pub statusb: crate::Reg, + #[doc = "0x3c - Peripheral write protection status - Bridge C"] + pub statusc: crate::Reg, +} +#[doc = "WRCTRL register accessor: an alias for `Reg`"] +pub type WRCTRL = crate::Reg; +#[doc = "Write control"] +pub mod wrctrl; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt enable clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt enable set"] +pub mod intenset; +#[doc = "INTFLAGAHB register accessor: an alias for `Reg`"] +pub type INTFLAGAHB = crate::Reg; +#[doc = "Bridge interrupt flag status"] +pub mod intflagahb; +#[doc = "INTFLAGA register accessor: an alias for `Reg`"] +pub type INTFLAGA = crate::Reg; +#[doc = "Peripheral interrupt flag status - Bridge A"] +pub mod intflaga; +#[doc = "INTFLAGB register accessor: an alias for `Reg`"] +pub type INTFLAGB = crate::Reg; +#[doc = "Peripheral interrupt flag status - Bridge B"] +pub mod intflagb; +#[doc = "INTFLAGC register accessor: an alias for `Reg`"] +pub type INTFLAGC = crate::Reg; +#[doc = "Peripheral interrupt flag status - Bridge C"] +pub mod intflagc; +#[doc = "STATUSA register accessor: an alias for `Reg`"] +pub type STATUSA = crate::Reg; +#[doc = "Peripheral write protection status - Bridge A"] +pub mod statusa; +#[doc = "STATUSB register accessor: an alias for `Reg`"] +pub type STATUSB = crate::Reg; +#[doc = "Peripheral write protection status - Bridge B"] +pub mod statusb; +#[doc = "STATUSC register accessor: an alias for `Reg`"] +pub type STATUSC = crate::Reg; +#[doc = "Peripheral write protection status - Bridge C"] +pub mod statusc; diff --git a/pac/atsamc20e/src/pac/evctrl.rs b/pac/atsamc20e/src/pac/evctrl.rs new file mode 100644 index 000000000000..630581b98c85 --- /dev/null +++ b/pac/atsamc20e/src/pac/evctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ERREO` reader - Peripheral acess error event output"] +pub struct ERREO_R(crate::FieldReader); +impl ERREO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERREO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERREO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERREO` writer - Peripheral acess error event output"] +pub struct ERREO_W<'a> { + w: &'a mut W, +} +impl<'a> ERREO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Peripheral acess error event output"] + #[inline(always)] + pub fn erreo(&self) -> ERREO_R { + ERREO_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Peripheral acess error event output"] + #[inline(always)] + pub fn erreo(&mut self) -> ERREO_W { + ERREO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/pac/intenclr.rs b/pac/atsamc20e/src/pac/intenclr.rs new file mode 100644 index 000000000000..609fe0fcf628 --- /dev/null +++ b/pac/atsamc20e/src/pac/intenclr.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ERR` reader - Peripheral access error interrupt disable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - Peripheral access error interrupt disable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Peripheral access error interrupt disable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Peripheral access error interrupt disable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt enable clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/pac/intenset.rs b/pac/atsamc20e/src/pac/intenset.rs new file mode 100644 index 000000000000..390545b588de --- /dev/null +++ b/pac/atsamc20e/src/pac/intenset.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ERR` reader - Peripheral access error interrupt enable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - Peripheral access error interrupt enable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Peripheral access error interrupt enable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Peripheral access error interrupt enable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt enable set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/pac/intflaga.rs b/pac/atsamc20e/src/pac/intflaga.rs new file mode 100644 index 000000000000..df4c8554d9ab --- /dev/null +++ b/pac/atsamc20e/src/pac/intflaga.rs @@ -0,0 +1,630 @@ +#[doc = "Register `INTFLAGA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAGA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PAC_` reader - PAC"] +pub struct PAC__R(crate::FieldReader); +impl PAC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PAC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PAC_` writer - PAC"] +pub struct PAC__W<'a> { + w: &'a mut W, +} +impl<'a> PAC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `PM_` reader - PM"] +pub struct PM__R(crate::FieldReader); +impl PM__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PM__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PM__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PM_` writer - PM"] +pub struct PM__W<'a> { + w: &'a mut W, +} +impl<'a> PM__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MCLK_` reader - MCLK"] +pub struct MCLK__R(crate::FieldReader); +impl MCLK__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCLK__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCLK__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCLK_` writer - MCLK"] +pub struct MCLK__W<'a> { + w: &'a mut W, +} +impl<'a> MCLK__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RSTC_` reader - RSTC"] +pub struct RSTC__R(crate::FieldReader); +impl RSTC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RSTC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RSTC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RSTC_` writer - RSTC"] +pub struct RSTC__W<'a> { + w: &'a mut W, +} +impl<'a> RSTC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `OSCCTRL_` reader - OSCCTRL"] +pub struct OSCCTRL__R(crate::FieldReader); +impl OSCCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSCCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSCCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSCCTRL_` writer - OSCCTRL"] +pub struct OSCCTRL__W<'a> { + w: &'a mut W, +} +impl<'a> OSCCTRL__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `OSC32KCTRL_` reader - OSC32KCTRL"] +pub struct OSC32KCTRL__R(crate::FieldReader); +impl OSC32KCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC32KCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC32KCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC32KCTRL_` writer - OSC32KCTRL"] +pub struct OSC32KCTRL__W<'a> { + w: &'a mut W, +} +impl<'a> OSC32KCTRL__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `SUPC_` reader - SUPC"] +pub struct SUPC__R(crate::FieldReader); +impl SUPC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SUPC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SUPC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SUPC_` writer - SUPC"] +pub struct SUPC__W<'a> { + w: &'a mut W, +} +impl<'a> SUPC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `GCLK_` reader - GCLK"] +pub struct GCLK__R(crate::FieldReader); +impl GCLK__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GCLK__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GCLK__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GCLK_` writer - GCLK"] +pub struct GCLK__W<'a> { + w: &'a mut W, +} +impl<'a> GCLK__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `WDT_` reader - WDT"] +pub struct WDT__R(crate::FieldReader); +impl WDT__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WDT__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WDT__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WDT_` writer - WDT"] +pub struct WDT__W<'a> { + w: &'a mut W, +} +impl<'a> WDT__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `RTC_` reader - RTC"] +pub struct RTC__R(crate::FieldReader); +impl RTC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RTC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RTC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RTC_` writer - RTC"] +pub struct RTC__W<'a> { + w: &'a mut W, +} +impl<'a> RTC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `EIC_` reader - EIC"] +pub struct EIC__R(crate::FieldReader); +impl EIC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EIC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EIC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EIC_` writer - EIC"] +pub struct EIC__W<'a> { + w: &'a mut W, +} +impl<'a> EIC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `FREQM_` reader - FREQM"] +pub struct FREQM__R(crate::FieldReader); +impl FREQM__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FREQM__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FREQM__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FREQM_` writer - FREQM"] +pub struct FREQM__W<'a> { + w: &'a mut W, +} +impl<'a> FREQM__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +impl R { + #[doc = "Bit 0 - PAC"] + #[inline(always)] + pub fn pac_(&self) -> PAC__R { + PAC__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - PM"] + #[inline(always)] + pub fn pm_(&self) -> PM__R { + PM__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - MCLK"] + #[inline(always)] + pub fn mclk_(&self) -> MCLK__R { + MCLK__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - RSTC"] + #[inline(always)] + pub fn rstc_(&self) -> RSTC__R { + RSTC__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - OSCCTRL"] + #[inline(always)] + pub fn oscctrl_(&self) -> OSCCTRL__R { + OSCCTRL__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - OSC32KCTRL"] + #[inline(always)] + pub fn osc32kctrl_(&self) -> OSC32KCTRL__R { + OSC32KCTRL__R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - SUPC"] + #[inline(always)] + pub fn supc_(&self) -> SUPC__R { + SUPC__R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - GCLK"] + #[inline(always)] + pub fn gclk_(&self) -> GCLK__R { + GCLK__R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - WDT"] + #[inline(always)] + pub fn wdt_(&self) -> WDT__R { + WDT__R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - RTC"] + #[inline(always)] + pub fn rtc_(&self) -> RTC__R { + RTC__R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - EIC"] + #[inline(always)] + pub fn eic_(&self) -> EIC__R { + EIC__R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - FREQM"] + #[inline(always)] + pub fn freqm_(&self) -> FREQM__R { + FREQM__R::new(((self.bits >> 11) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - PAC"] + #[inline(always)] + pub fn pac_(&mut self) -> PAC__W { + PAC__W { w: self } + } + #[doc = "Bit 1 - PM"] + #[inline(always)] + pub fn pm_(&mut self) -> PM__W { + PM__W { w: self } + } + #[doc = "Bit 2 - MCLK"] + #[inline(always)] + pub fn mclk_(&mut self) -> MCLK__W { + MCLK__W { w: self } + } + #[doc = "Bit 3 - RSTC"] + #[inline(always)] + pub fn rstc_(&mut self) -> RSTC__W { + RSTC__W { w: self } + } + #[doc = "Bit 4 - OSCCTRL"] + #[inline(always)] + pub fn oscctrl_(&mut self) -> OSCCTRL__W { + OSCCTRL__W { w: self } + } + #[doc = "Bit 5 - OSC32KCTRL"] + #[inline(always)] + pub fn osc32kctrl_(&mut self) -> OSC32KCTRL__W { + OSC32KCTRL__W { w: self } + } + #[doc = "Bit 6 - SUPC"] + #[inline(always)] + pub fn supc_(&mut self) -> SUPC__W { + SUPC__W { w: self } + } + #[doc = "Bit 7 - GCLK"] + #[inline(always)] + pub fn gclk_(&mut self) -> GCLK__W { + GCLK__W { w: self } + } + #[doc = "Bit 8 - WDT"] + #[inline(always)] + pub fn wdt_(&mut self) -> WDT__W { + WDT__W { w: self } + } + #[doc = "Bit 9 - RTC"] + #[inline(always)] + pub fn rtc_(&mut self) -> RTC__W { + RTC__W { w: self } + } + #[doc = "Bit 10 - EIC"] + #[inline(always)] + pub fn eic_(&mut self) -> EIC__W { + EIC__W { w: self } + } + #[doc = "Bit 11 - FREQM"] + #[inline(always)] + pub fn freqm_(&mut self) -> FREQM__W { + FREQM__W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Peripheral interrupt flag status - Bridge A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflaga](index.html) module"] +pub struct INTFLAGA_SPEC; +impl crate::RegisterSpec for INTFLAGA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflaga::R](R) reader structure"] +impl crate::Readable for INTFLAGA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflaga::W](W) writer structure"] +impl crate::Writable for INTFLAGA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAGA to value 0"] +impl crate::Resettable for INTFLAGA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/pac/intflagahb.rs b/pac/atsamc20e/src/pac/intflagahb.rs new file mode 100644 index 000000000000..4b7f7377e25e --- /dev/null +++ b/pac/atsamc20e/src/pac/intflagahb.rs @@ -0,0 +1,442 @@ +#[doc = "Register `INTFLAGAHB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAGAHB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FLASH_` reader - FLASH"] +pub struct FLASH__R(crate::FieldReader); +impl FLASH__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FLASH__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FLASH__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLASH_` writer - FLASH"] +pub struct FLASH__W<'a> { + w: &'a mut W, +} +impl<'a> FLASH__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `HSRAMCM0P_` reader - HSRAMCM0P"] +pub struct HSRAMCM0P__R(crate::FieldReader); +impl HSRAMCM0P__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HSRAMCM0P__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HSRAMCM0P__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HSRAMCM0P_` writer - HSRAMCM0P"] +pub struct HSRAMCM0P__W<'a> { + w: &'a mut W, +} +impl<'a> HSRAMCM0P__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `HSRAMDSU_` reader - HSRAMDSU"] +pub struct HSRAMDSU__R(crate::FieldReader); +impl HSRAMDSU__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HSRAMDSU__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HSRAMDSU__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HSRAMDSU_` writer - HSRAMDSU"] +pub struct HSRAMDSU__W<'a> { + w: &'a mut W, +} +impl<'a> HSRAMDSU__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `HPB1_` reader - HPB1"] +pub struct HPB1__R(crate::FieldReader); +impl HPB1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HPB1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HPB1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HPB1_` writer - HPB1"] +pub struct HPB1__W<'a> { + w: &'a mut W, +} +impl<'a> HPB1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `HPB0_` reader - HPB0"] +pub struct HPB0__R(crate::FieldReader); +impl HPB0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HPB0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HPB0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HPB0_` writer - HPB0"] +pub struct HPB0__W<'a> { + w: &'a mut W, +} +impl<'a> HPB0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `HPB2_` reader - HPB2"] +pub struct HPB2__R(crate::FieldReader); +impl HPB2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HPB2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HPB2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HPB2_` writer - HPB2"] +pub struct HPB2__W<'a> { + w: &'a mut W, +} +impl<'a> HPB2__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `LPRAMDMAC_` reader - LPRAMDMAC"] +pub struct LPRAMDMAC__R(crate::FieldReader); +impl LPRAMDMAC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LPRAMDMAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LPRAMDMAC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LPRAMDMAC_` writer - LPRAMDMAC"] +pub struct LPRAMDMAC__W<'a> { + w: &'a mut W, +} +impl<'a> LPRAMDMAC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `DIVAS_` reader - DIVAS"] +pub struct DIVAS__R(crate::FieldReader); +impl DIVAS__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIVAS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIVAS__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIVAS_` writer - DIVAS"] +pub struct DIVAS__W<'a> { + w: &'a mut W, +} +impl<'a> DIVAS__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - FLASH"] + #[inline(always)] + pub fn flash_(&self) -> FLASH__R { + FLASH__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - HSRAMCM0P"] + #[inline(always)] + pub fn hsramcm0p_(&self) -> HSRAMCM0P__R { + HSRAMCM0P__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - HSRAMDSU"] + #[inline(always)] + pub fn hsramdsu_(&self) -> HSRAMDSU__R { + HSRAMDSU__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - HPB1"] + #[inline(always)] + pub fn hpb1_(&self) -> HPB1__R { + HPB1__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - HPB0"] + #[inline(always)] + pub fn hpb0_(&self) -> HPB0__R { + HPB0__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - HPB2"] + #[inline(always)] + pub fn hpb2_(&self) -> HPB2__R { + HPB2__R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - LPRAMDMAC"] + #[inline(always)] + pub fn lpramdmac_(&self) -> LPRAMDMAC__R { + LPRAMDMAC__R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - DIVAS"] + #[inline(always)] + pub fn divas_(&self) -> DIVAS__R { + DIVAS__R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - FLASH"] + #[inline(always)] + pub fn flash_(&mut self) -> FLASH__W { + FLASH__W { w: self } + } + #[doc = "Bit 1 - HSRAMCM0P"] + #[inline(always)] + pub fn hsramcm0p_(&mut self) -> HSRAMCM0P__W { + HSRAMCM0P__W { w: self } + } + #[doc = "Bit 2 - HSRAMDSU"] + #[inline(always)] + pub fn hsramdsu_(&mut self) -> HSRAMDSU__W { + HSRAMDSU__W { w: self } + } + #[doc = "Bit 3 - HPB1"] + #[inline(always)] + pub fn hpb1_(&mut self) -> HPB1__W { + HPB1__W { w: self } + } + #[doc = "Bit 4 - HPB0"] + #[inline(always)] + pub fn hpb0_(&mut self) -> HPB0__W { + HPB0__W { w: self } + } + #[doc = "Bit 5 - HPB2"] + #[inline(always)] + pub fn hpb2_(&mut self) -> HPB2__W { + HPB2__W { w: self } + } + #[doc = "Bit 6 - LPRAMDMAC"] + #[inline(always)] + pub fn lpramdmac_(&mut self) -> LPRAMDMAC__W { + LPRAMDMAC__W { w: self } + } + #[doc = "Bit 7 - DIVAS"] + #[inline(always)] + pub fn divas_(&mut self) -> DIVAS__W { + DIVAS__W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Bridge interrupt flag status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflagahb](index.html) module"] +pub struct INTFLAGAHB_SPEC; +impl crate::RegisterSpec for INTFLAGAHB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflagahb::R](R) reader structure"] +impl crate::Readable for INTFLAGAHB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflagahb::W](W) writer structure"] +impl crate::Writable for INTFLAGAHB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAGAHB to value 0"] +impl crate::Resettable for INTFLAGAHB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/pac/intflagb.rs b/pac/atsamc20e/src/pac/intflagb.rs new file mode 100644 index 000000000000..8359f7e11f30 --- /dev/null +++ b/pac/atsamc20e/src/pac/intflagb.rs @@ -0,0 +1,348 @@ +#[doc = "Register `INTFLAGB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAGB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PORT_` reader - PORT"] +pub struct PORT__R(crate::FieldReader); +impl PORT__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PORT__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PORT__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PORT_` writer - PORT"] +pub struct PORT__W<'a> { + w: &'a mut W, +} +impl<'a> PORT__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `DSU_` reader - DSU"] +pub struct DSU__R(crate::FieldReader); +impl DSU__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DSU__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DSU__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DSU_` writer - DSU"] +pub struct DSU__W<'a> { + w: &'a mut W, +} +impl<'a> DSU__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `NVMCTRL_` reader - NVMCTRL"] +pub struct NVMCTRL__R(crate::FieldReader); +impl NVMCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NVMCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NVMCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NVMCTRL_` writer - NVMCTRL"] +pub struct NVMCTRL__W<'a> { + w: &'a mut W, +} +impl<'a> NVMCTRL__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `DMAC_` reader - DMAC"] +pub struct DMAC__R(crate::FieldReader); +impl DMAC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DMAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DMAC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DMAC_` writer - DMAC"] +pub struct DMAC__W<'a> { + w: &'a mut W, +} +impl<'a> DMAC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `MTB_` reader - MTB"] +pub struct MTB__R(crate::FieldReader); +impl MTB__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MTB__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MTB__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MTB_` writer - MTB"] +pub struct MTB__W<'a> { + w: &'a mut W, +} +impl<'a> MTB__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `HMATRIXHS_` reader - HMATRIXHS"] +pub struct HMATRIXHS__R(crate::FieldReader); +impl HMATRIXHS__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HMATRIXHS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HMATRIXHS__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HMATRIXHS_` writer - HMATRIXHS"] +pub struct HMATRIXHS__W<'a> { + w: &'a mut W, +} +impl<'a> HMATRIXHS__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - PORT"] + #[inline(always)] + pub fn port_(&self) -> PORT__R { + PORT__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - DSU"] + #[inline(always)] + pub fn dsu_(&self) -> DSU__R { + DSU__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - NVMCTRL"] + #[inline(always)] + pub fn nvmctrl_(&self) -> NVMCTRL__R { + NVMCTRL__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - DMAC"] + #[inline(always)] + pub fn dmac_(&self) -> DMAC__R { + DMAC__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - MTB"] + #[inline(always)] + pub fn mtb_(&self) -> MTB__R { + MTB__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - HMATRIXHS"] + #[inline(always)] + pub fn hmatrixhs_(&self) -> HMATRIXHS__R { + HMATRIXHS__R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - PORT"] + #[inline(always)] + pub fn port_(&mut self) -> PORT__W { + PORT__W { w: self } + } + #[doc = "Bit 1 - DSU"] + #[inline(always)] + pub fn dsu_(&mut self) -> DSU__W { + DSU__W { w: self } + } + #[doc = "Bit 2 - NVMCTRL"] + #[inline(always)] + pub fn nvmctrl_(&mut self) -> NVMCTRL__W { + NVMCTRL__W { w: self } + } + #[doc = "Bit 3 - DMAC"] + #[inline(always)] + pub fn dmac_(&mut self) -> DMAC__W { + DMAC__W { w: self } + } + #[doc = "Bit 4 - MTB"] + #[inline(always)] + pub fn mtb_(&mut self) -> MTB__W { + MTB__W { w: self } + } + #[doc = "Bit 5 - HMATRIXHS"] + #[inline(always)] + pub fn hmatrixhs_(&mut self) -> HMATRIXHS__W { + HMATRIXHS__W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Peripheral interrupt flag status - Bridge B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflagb](index.html) module"] +pub struct INTFLAGB_SPEC; +impl crate::RegisterSpec for INTFLAGB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflagb::R](R) reader structure"] +impl crate::Readable for INTFLAGB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflagb::W](W) writer structure"] +impl crate::Writable for INTFLAGB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAGB to value 0"] +impl crate::Resettable for INTFLAGB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/pac/intflagc.rs b/pac/atsamc20e/src/pac/intflagc.rs new file mode 100644 index 000000000000..25a236fa631a --- /dev/null +++ b/pac/atsamc20e/src/pac/intflagc.rs @@ -0,0 +1,865 @@ +#[doc = "Register `INTFLAGC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAGC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVSYS_` reader - EVSYS"] +pub struct EVSYS__R(crate::FieldReader); +impl EVSYS__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVSYS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVSYS__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVSYS_` writer - EVSYS"] +pub struct EVSYS__W<'a> { + w: &'a mut W, +} +impl<'a> EVSYS__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `SERCOM0_` reader - SERCOM0"] +pub struct SERCOM0__R(crate::FieldReader); +impl SERCOM0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM0_` writer - SERCOM0"] +pub struct SERCOM0__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SERCOM1_` reader - SERCOM1"] +pub struct SERCOM1__R(crate::FieldReader); +impl SERCOM1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM1_` writer - SERCOM1"] +pub struct SERCOM1__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SERCOM2_` reader - SERCOM2"] +pub struct SERCOM2__R(crate::FieldReader); +impl SERCOM2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM2_` writer - SERCOM2"] +pub struct SERCOM2__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM2__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `SERCOM3_` reader - SERCOM3"] +pub struct SERCOM3__R(crate::FieldReader); +impl SERCOM3__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM3__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM3__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM3_` writer - SERCOM3"] +pub struct SERCOM3__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM3__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `TCC0_` reader - TCC0"] +pub struct TCC0__R(crate::FieldReader); +impl TCC0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCC0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCC0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCC0_` writer - TCC0"] +pub struct TCC0__W<'a> { + w: &'a mut W, +} +impl<'a> TCC0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `TCC1_` reader - TCC1"] +pub struct TCC1__R(crate::FieldReader); +impl TCC1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCC1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCC1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCC1_` writer - TCC1"] +pub struct TCC1__W<'a> { + w: &'a mut W, +} +impl<'a> TCC1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `TCC2_` reader - TCC2"] +pub struct TCC2__R(crate::FieldReader); +impl TCC2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCC2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCC2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCC2_` writer - TCC2"] +pub struct TCC2__W<'a> { + w: &'a mut W, +} +impl<'a> TCC2__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `TC0_` reader - TC0"] +pub struct TC0__R(crate::FieldReader); +impl TC0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC0_` writer - TC0"] +pub struct TC0__W<'a> { + w: &'a mut W, +} +impl<'a> TC0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `TC1_` reader - TC1"] +pub struct TC1__R(crate::FieldReader); +impl TC1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC1_` writer - TC1"] +pub struct TC1__W<'a> { + w: &'a mut W, +} +impl<'a> TC1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `TC2_` reader - TC2"] +pub struct TC2__R(crate::FieldReader); +impl TC2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC2_` writer - TC2"] +pub struct TC2__W<'a> { + w: &'a mut W, +} +impl<'a> TC2__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `TC3_` reader - TC3"] +pub struct TC3__R(crate::FieldReader); +impl TC3__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC3__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC3__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC3_` writer - TC3"] +pub struct TC3__W<'a> { + w: &'a mut W, +} +impl<'a> TC3__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `TC4_` reader - TC4"] +pub struct TC4__R(crate::FieldReader); +impl TC4__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC4__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC4__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC4_` writer - TC4"] +pub struct TC4__W<'a> { + w: &'a mut W, +} +impl<'a> TC4__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `ADC0_` reader - ADC0"] +pub struct ADC0__R(crate::FieldReader); +impl ADC0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ADC0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADC0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADC0_` writer - ADC0"] +pub struct ADC0__W<'a> { + w: &'a mut W, +} +impl<'a> ADC0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `AC_` reader - AC"] +pub struct AC__R(crate::FieldReader); +impl AC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AC_` writer - AC"] +pub struct AC__W<'a> { + w: &'a mut W, +} +impl<'a> AC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `PTC_` reader - PTC"] +pub struct PTC__R(crate::FieldReader); +impl PTC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PTC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PTC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PTC_` writer - PTC"] +pub struct PTC__W<'a> { + w: &'a mut W, +} +impl<'a> PTC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `CCL_` reader - CCL"] +pub struct CCL__R(crate::FieldReader); +impl CCL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCL_` writer - CCL"] +pub struct CCL__W<'a> { + w: &'a mut W, +} +impl<'a> CCL__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +impl R { + #[doc = "Bit 0 - EVSYS"] + #[inline(always)] + pub fn evsys_(&self) -> EVSYS__R { + EVSYS__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM0"] + #[inline(always)] + pub fn sercom0_(&self) -> SERCOM0__R { + SERCOM0__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - SERCOM1"] + #[inline(always)] + pub fn sercom1_(&self) -> SERCOM1__R { + SERCOM1__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - SERCOM2"] + #[inline(always)] + pub fn sercom2_(&self) -> SERCOM2__R { + SERCOM2__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - SERCOM3"] + #[inline(always)] + pub fn sercom3_(&self) -> SERCOM3__R { + SERCOM3__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 9 - TCC0"] + #[inline(always)] + pub fn tcc0_(&self) -> TCC0__R { + TCC0__R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - TCC1"] + #[inline(always)] + pub fn tcc1_(&self) -> TCC1__R { + TCC1__R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - TCC2"] + #[inline(always)] + pub fn tcc2_(&self) -> TCC2__R { + TCC2__R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - TC0"] + #[inline(always)] + pub fn tc0_(&self) -> TC0__R { + TC0__R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - TC1"] + #[inline(always)] + pub fn tc1_(&self) -> TC1__R { + TC1__R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - TC2"] + #[inline(always)] + pub fn tc2_(&self) -> TC2__R { + TC2__R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - TC3"] + #[inline(always)] + pub fn tc3_(&self) -> TC3__R { + TC3__R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - TC4"] + #[inline(always)] + pub fn tc4_(&self) -> TC4__R { + TC4__R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - ADC0"] + #[inline(always)] + pub fn adc0_(&self) -> ADC0__R { + ADC0__R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 20 - AC"] + #[inline(always)] + pub fn ac_(&self) -> AC__R { + AC__R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 22 - PTC"] + #[inline(always)] + pub fn ptc_(&self) -> PTC__R { + PTC__R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - CCL"] + #[inline(always)] + pub fn ccl_(&self) -> CCL__R { + CCL__R::new(((self.bits >> 23) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - EVSYS"] + #[inline(always)] + pub fn evsys_(&mut self) -> EVSYS__W { + EVSYS__W { w: self } + } + #[doc = "Bit 1 - SERCOM0"] + #[inline(always)] + pub fn sercom0_(&mut self) -> SERCOM0__W { + SERCOM0__W { w: self } + } + #[doc = "Bit 2 - SERCOM1"] + #[inline(always)] + pub fn sercom1_(&mut self) -> SERCOM1__W { + SERCOM1__W { w: self } + } + #[doc = "Bit 3 - SERCOM2"] + #[inline(always)] + pub fn sercom2_(&mut self) -> SERCOM2__W { + SERCOM2__W { w: self } + } + #[doc = "Bit 4 - SERCOM3"] + #[inline(always)] + pub fn sercom3_(&mut self) -> SERCOM3__W { + SERCOM3__W { w: self } + } + #[doc = "Bit 9 - TCC0"] + #[inline(always)] + pub fn tcc0_(&mut self) -> TCC0__W { + TCC0__W { w: self } + } + #[doc = "Bit 10 - TCC1"] + #[inline(always)] + pub fn tcc1_(&mut self) -> TCC1__W { + TCC1__W { w: self } + } + #[doc = "Bit 11 - TCC2"] + #[inline(always)] + pub fn tcc2_(&mut self) -> TCC2__W { + TCC2__W { w: self } + } + #[doc = "Bit 12 - TC0"] + #[inline(always)] + pub fn tc0_(&mut self) -> TC0__W { + TC0__W { w: self } + } + #[doc = "Bit 13 - TC1"] + #[inline(always)] + pub fn tc1_(&mut self) -> TC1__W { + TC1__W { w: self } + } + #[doc = "Bit 14 - TC2"] + #[inline(always)] + pub fn tc2_(&mut self) -> TC2__W { + TC2__W { w: self } + } + #[doc = "Bit 15 - TC3"] + #[inline(always)] + pub fn tc3_(&mut self) -> TC3__W { + TC3__W { w: self } + } + #[doc = "Bit 16 - TC4"] + #[inline(always)] + pub fn tc4_(&mut self) -> TC4__W { + TC4__W { w: self } + } + #[doc = "Bit 17 - ADC0"] + #[inline(always)] + pub fn adc0_(&mut self) -> ADC0__W { + ADC0__W { w: self } + } + #[doc = "Bit 20 - AC"] + #[inline(always)] + pub fn ac_(&mut self) -> AC__W { + AC__W { w: self } + } + #[doc = "Bit 22 - PTC"] + #[inline(always)] + pub fn ptc_(&mut self) -> PTC__W { + PTC__W { w: self } + } + #[doc = "Bit 23 - CCL"] + #[inline(always)] + pub fn ccl_(&mut self) -> CCL__W { + CCL__W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Peripheral interrupt flag status - Bridge C\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflagc](index.html) module"] +pub struct INTFLAGC_SPEC; +impl crate::RegisterSpec for INTFLAGC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflagc::R](R) reader structure"] +impl crate::Readable for INTFLAGC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflagc::W](W) writer structure"] +impl crate::Writable for INTFLAGC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAGC to value 0"] +impl crate::Resettable for INTFLAGC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/pac/statusa.rs b/pac/atsamc20e/src/pac/statusa.rs new file mode 100644 index 000000000000..32974f65e5d5 --- /dev/null +++ b/pac/atsamc20e/src/pac/statusa.rs @@ -0,0 +1,273 @@ +#[doc = "Register `STATUSA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PAC_` reader - PAC APB Protect Enable"] +pub struct PAC__R(crate::FieldReader); +impl PAC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PAC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PM_` reader - PM APB Protect Enable"] +pub struct PM__R(crate::FieldReader); +impl PM__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PM__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PM__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCLK_` reader - MCLK APB Protect Enable"] +pub struct MCLK__R(crate::FieldReader); +impl MCLK__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCLK__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCLK__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RSTC_` reader - RSTC APB Protect Enable"] +pub struct RSTC__R(crate::FieldReader); +impl RSTC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RSTC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RSTC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSCCTRL_` reader - OSCCTRL APB Protect Enable"] +pub struct OSCCTRL__R(crate::FieldReader); +impl OSCCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSCCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSCCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC32KCTRL_` reader - OSC32KCTRL APB Protect Enable"] +pub struct OSC32KCTRL__R(crate::FieldReader); +impl OSC32KCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC32KCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC32KCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SUPC_` reader - SUPC APB Protect Enable"] +pub struct SUPC__R(crate::FieldReader); +impl SUPC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SUPC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SUPC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GCLK_` reader - GCLK APB Protect Enable"] +pub struct GCLK__R(crate::FieldReader); +impl GCLK__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GCLK__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GCLK__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WDT_` reader - WDT APB Protect Enable"] +pub struct WDT__R(crate::FieldReader); +impl WDT__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WDT__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WDT__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RTC_` reader - RTC APB Protect Enable"] +pub struct RTC__R(crate::FieldReader); +impl RTC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RTC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RTC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EIC_` reader - EIC APB Protect Enable"] +pub struct EIC__R(crate::FieldReader); +impl EIC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EIC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EIC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FREQM_` reader - FREQM APB Protect Enable"] +pub struct FREQM__R(crate::FieldReader); +impl FREQM__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FREQM__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FREQM__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - PAC APB Protect Enable"] + #[inline(always)] + pub fn pac_(&self) -> PAC__R { + PAC__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - PM APB Protect Enable"] + #[inline(always)] + pub fn pm_(&self) -> PM__R { + PM__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - MCLK APB Protect Enable"] + #[inline(always)] + pub fn mclk_(&self) -> MCLK__R { + MCLK__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - RSTC APB Protect Enable"] + #[inline(always)] + pub fn rstc_(&self) -> RSTC__R { + RSTC__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - OSCCTRL APB Protect Enable"] + #[inline(always)] + pub fn oscctrl_(&self) -> OSCCTRL__R { + OSCCTRL__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - OSC32KCTRL APB Protect Enable"] + #[inline(always)] + pub fn osc32kctrl_(&self) -> OSC32KCTRL__R { + OSC32KCTRL__R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - SUPC APB Protect Enable"] + #[inline(always)] + pub fn supc_(&self) -> SUPC__R { + SUPC__R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - GCLK APB Protect Enable"] + #[inline(always)] + pub fn gclk_(&self) -> GCLK__R { + GCLK__R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - WDT APB Protect Enable"] + #[inline(always)] + pub fn wdt_(&self) -> WDT__R { + WDT__R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - RTC APB Protect Enable"] + #[inline(always)] + pub fn rtc_(&self) -> RTC__R { + RTC__R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - EIC APB Protect Enable"] + #[inline(always)] + pub fn eic_(&self) -> EIC__R { + EIC__R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - FREQM APB Protect Enable"] + #[inline(always)] + pub fn freqm_(&self) -> FREQM__R { + FREQM__R::new(((self.bits >> 11) & 0x01) != 0) + } +} +#[doc = "Peripheral write protection status - Bridge A\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [statusa](index.html) module"] +pub struct STATUSA_SPEC; +impl crate::RegisterSpec for STATUSA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [statusa::R](R) reader structure"] +impl crate::Readable for STATUSA_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUSA to value 0"] +impl crate::Resettable for STATUSA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/pac/statusb.rs b/pac/atsamc20e/src/pac/statusb.rs new file mode 100644 index 000000000000..a022cc2f1d54 --- /dev/null +++ b/pac/atsamc20e/src/pac/statusb.rs @@ -0,0 +1,153 @@ +#[doc = "Register `STATUSB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PORT_` reader - PORT APB Protect Enable"] +pub struct PORT__R(crate::FieldReader); +impl PORT__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PORT__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PORT__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DSU_` reader - DSU APB Protect Enable"] +pub struct DSU__R(crate::FieldReader); +impl DSU__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DSU__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DSU__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NVMCTRL_` reader - NVMCTRL APB Protect Enable"] +pub struct NVMCTRL__R(crate::FieldReader); +impl NVMCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NVMCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NVMCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DMAC_` reader - DMAC APB Protect Enable"] +pub struct DMAC__R(crate::FieldReader); +impl DMAC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DMAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DMAC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MTB_` reader - MTB APB Protect Enable"] +pub struct MTB__R(crate::FieldReader); +impl MTB__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MTB__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MTB__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HMATRIXHS_` reader - HMATRIXHS APB Protect Enable"] +pub struct HMATRIXHS__R(crate::FieldReader); +impl HMATRIXHS__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HMATRIXHS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HMATRIXHS__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - PORT APB Protect Enable"] + #[inline(always)] + pub fn port_(&self) -> PORT__R { + PORT__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - DSU APB Protect Enable"] + #[inline(always)] + pub fn dsu_(&self) -> DSU__R { + DSU__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - NVMCTRL APB Protect Enable"] + #[inline(always)] + pub fn nvmctrl_(&self) -> NVMCTRL__R { + NVMCTRL__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - DMAC APB Protect Enable"] + #[inline(always)] + pub fn dmac_(&self) -> DMAC__R { + DMAC__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - MTB APB Protect Enable"] + #[inline(always)] + pub fn mtb_(&self) -> MTB__R { + MTB__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - HMATRIXHS APB Protect Enable"] + #[inline(always)] + pub fn hmatrixhs_(&self) -> HMATRIXHS__R { + HMATRIXHS__R::new(((self.bits >> 5) & 0x01) != 0) + } +} +#[doc = "Peripheral write protection status - Bridge B\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [statusb](index.html) module"] +pub struct STATUSB_SPEC; +impl crate::RegisterSpec for STATUSB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [statusb::R](R) reader structure"] +impl crate::Readable for STATUSB_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUSB to value 0x02"] +impl crate::Resettable for STATUSB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x02 + } +} diff --git a/pac/atsamc20e/src/pac/statusc.rs b/pac/atsamc20e/src/pac/statusc.rs new file mode 100644 index 000000000000..744a02d7454f --- /dev/null +++ b/pac/atsamc20e/src/pac/statusc.rs @@ -0,0 +1,373 @@ +#[doc = "Register `STATUSC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `EVSYS_` reader - EVSYS APB Protect Enable"] +pub struct EVSYS__R(crate::FieldReader); +impl EVSYS__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVSYS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVSYS__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM0_` reader - SERCOM0 APB Protect Enable"] +pub struct SERCOM0__R(crate::FieldReader); +impl SERCOM0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM1_` reader - SERCOM1 APB Protect Enable"] +pub struct SERCOM1__R(crate::FieldReader); +impl SERCOM1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM2_` reader - SERCOM2 APB Protect Enable"] +pub struct SERCOM2__R(crate::FieldReader); +impl SERCOM2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM3_` reader - SERCOM3 APB Protect Enable"] +pub struct SERCOM3__R(crate::FieldReader); +impl SERCOM3__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM3__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM3__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCC0_` reader - TCC0 APB Protect Enable"] +pub struct TCC0__R(crate::FieldReader); +impl TCC0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCC0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCC0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCC1_` reader - TCC1 APB Protect Enable"] +pub struct TCC1__R(crate::FieldReader); +impl TCC1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCC1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCC1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCC2_` reader - TCC2 APB Protect Enable"] +pub struct TCC2__R(crate::FieldReader); +impl TCC2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCC2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCC2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC0_` reader - TC0 APB Protect Enable"] +pub struct TC0__R(crate::FieldReader); +impl TC0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC1_` reader - TC1 APB Protect Enable"] +pub struct TC1__R(crate::FieldReader); +impl TC1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC2_` reader - TC2 APB Protect Enable"] +pub struct TC2__R(crate::FieldReader); +impl TC2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC3_` reader - TC3 APB Protect Enable"] +pub struct TC3__R(crate::FieldReader); +impl TC3__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC3__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC3__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC4_` reader - TC4 APB Protect Enable"] +pub struct TC4__R(crate::FieldReader); +impl TC4__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC4__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC4__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADC0_` reader - ADC0 APB Protect Enable"] +pub struct ADC0__R(crate::FieldReader); +impl ADC0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ADC0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADC0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AC_` reader - AC APB Protect Enable"] +pub struct AC__R(crate::FieldReader); +impl AC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PTC_` reader - PTC APB Protect Enable"] +pub struct PTC__R(crate::FieldReader); +impl PTC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PTC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PTC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCL_` reader - CCL APB Protect Enable"] +pub struct CCL__R(crate::FieldReader); +impl CCL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - EVSYS APB Protect Enable"] + #[inline(always)] + pub fn evsys_(&self) -> EVSYS__R { + EVSYS__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM0 APB Protect Enable"] + #[inline(always)] + pub fn sercom0_(&self) -> SERCOM0__R { + SERCOM0__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - SERCOM1 APB Protect Enable"] + #[inline(always)] + pub fn sercom1_(&self) -> SERCOM1__R { + SERCOM1__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - SERCOM2 APB Protect Enable"] + #[inline(always)] + pub fn sercom2_(&self) -> SERCOM2__R { + SERCOM2__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - SERCOM3 APB Protect Enable"] + #[inline(always)] + pub fn sercom3_(&self) -> SERCOM3__R { + SERCOM3__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 9 - TCC0 APB Protect Enable"] + #[inline(always)] + pub fn tcc0_(&self) -> TCC0__R { + TCC0__R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - TCC1 APB Protect Enable"] + #[inline(always)] + pub fn tcc1_(&self) -> TCC1__R { + TCC1__R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - TCC2 APB Protect Enable"] + #[inline(always)] + pub fn tcc2_(&self) -> TCC2__R { + TCC2__R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - TC0 APB Protect Enable"] + #[inline(always)] + pub fn tc0_(&self) -> TC0__R { + TC0__R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - TC1 APB Protect Enable"] + #[inline(always)] + pub fn tc1_(&self) -> TC1__R { + TC1__R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - TC2 APB Protect Enable"] + #[inline(always)] + pub fn tc2_(&self) -> TC2__R { + TC2__R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - TC3 APB Protect Enable"] + #[inline(always)] + pub fn tc3_(&self) -> TC3__R { + TC3__R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - TC4 APB Protect Enable"] + #[inline(always)] + pub fn tc4_(&self) -> TC4__R { + TC4__R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - ADC0 APB Protect Enable"] + #[inline(always)] + pub fn adc0_(&self) -> ADC0__R { + ADC0__R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 20 - AC APB Protect Enable"] + #[inline(always)] + pub fn ac_(&self) -> AC__R { + AC__R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 22 - PTC APB Protect Enable"] + #[inline(always)] + pub fn ptc_(&self) -> PTC__R { + PTC__R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - CCL APB Protect Enable"] + #[inline(always)] + pub fn ccl_(&self) -> CCL__R { + CCL__R::new(((self.bits >> 23) & 0x01) != 0) + } +} +#[doc = "Peripheral write protection status - Bridge C\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [statusc](index.html) module"] +pub struct STATUSC_SPEC; +impl crate::RegisterSpec for STATUSC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [statusc::R](R) reader structure"] +impl crate::Readable for STATUSC_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUSC to value 0x0200_0000"] +impl crate::Resettable for STATUSC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0200_0000 + } +} diff --git a/pac/atsamc20e/src/pac/wrctrl.rs b/pac/atsamc20e/src/pac/wrctrl.rs new file mode 100644 index 000000000000..65773ea08d64 --- /dev/null +++ b/pac/atsamc20e/src/pac/wrctrl.rs @@ -0,0 +1,215 @@ +#[doc = "Register `WRCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WRCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PERID` reader - Peripheral identifier"] +pub struct PERID_R(crate::FieldReader); +impl PERID_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + PERID_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERID_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERID` writer - Peripheral identifier"] +pub struct PERID_W<'a> { + w: &'a mut W, +} +impl<'a> PERID_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +#[doc = "Peripheral access control key\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum KEY_A { + #[doc = "0: No action"] + OFF = 0, + #[doc = "1: Clear protection"] + CLR = 1, + #[doc = "2: Set protection"] + SET = 2, + #[doc = "3: Set and lock protection"] + SETLCK = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: KEY_A) -> Self { + variant as _ + } +} +#[doc = "Field `KEY` reader - Peripheral access control key"] +pub struct KEY_R(crate::FieldReader); +impl KEY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + KEY_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(KEY_A::OFF), + 1 => Some(KEY_A::CLR), + 2 => Some(KEY_A::SET), + 3 => Some(KEY_A::SETLCK), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == KEY_A::OFF + } + #[doc = "Checks if the value of the field is `CLR`"] + #[inline(always)] + pub fn is_clr(&self) -> bool { + **self == KEY_A::CLR + } + #[doc = "Checks if the value of the field is `SET`"] + #[inline(always)] + pub fn is_set(&self) -> bool { + **self == KEY_A::SET + } + #[doc = "Checks if the value of the field is `SETLCK`"] + #[inline(always)] + pub fn is_setlck(&self) -> bool { + **self == KEY_A::SETLCK + } +} +impl core::ops::Deref for KEY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `KEY` writer - Peripheral access control key"] +pub struct KEY_W<'a> { + w: &'a mut W, +} +impl<'a> KEY_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: KEY_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(KEY_A::OFF) + } + #[doc = "Clear protection"] + #[inline(always)] + pub fn clr(self) -> &'a mut W { + self.variant(KEY_A::CLR) + } + #[doc = "Set protection"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(KEY_A::SET) + } + #[doc = "Set and lock protection"] + #[inline(always)] + pub fn setlck(self) -> &'a mut W { + self.variant(KEY_A::SETLCK) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Peripheral identifier"] + #[inline(always)] + pub fn perid(&self) -> PERID_R { + PERID_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:23 - Peripheral access control key"] + #[inline(always)] + pub fn key(&self) -> KEY_R { + KEY_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:15 - Peripheral identifier"] + #[inline(always)] + pub fn perid(&mut self) -> PERID_W { + PERID_W { w: self } + } + #[doc = "Bits 16:23 - Peripheral access control key"] + #[inline(always)] + pub fn key(&mut self) -> KEY_W { + KEY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Write control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wrctrl](index.html) module"] +pub struct WRCTRL_SPEC; +impl crate::RegisterSpec for WRCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [wrctrl::R](R) reader structure"] +impl crate::Readable for WRCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wrctrl::W](W) writer structure"] +impl crate::Writable for WRCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WRCTRL to value 0"] +impl crate::Resettable for WRCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/pm.rs b/pac/atsamc20e/src/pm.rs new file mode 100644 index 000000000000..9da2b0e13288 --- /dev/null +++ b/pac/atsamc20e/src/pm.rs @@ -0,0 +1,18 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved0: [u8; 0x01], + #[doc = "0x01 - Sleep Configuration"] + pub sleepcfg: crate::Reg, + _reserved1: [u8; 0x06], + #[doc = "0x08 - Standby Configuration"] + pub stdbycfg: crate::Reg, +} +#[doc = "SLEEPCFG register accessor: an alias for `Reg`"] +pub type SLEEPCFG = crate::Reg; +#[doc = "Sleep Configuration"] +pub mod sleepcfg; +#[doc = "STDBYCFG register accessor: an alias for `Reg`"] +pub type STDBYCFG = crate::Reg; +#[doc = "Standby Configuration"] +pub mod stdbycfg; diff --git a/pac/atsamc20e/src/pm/sleepcfg.rs b/pac/atsamc20e/src/pm/sleepcfg.rs new file mode 100644 index 000000000000..ef643311a059 --- /dev/null +++ b/pac/atsamc20e/src/pm/sleepcfg.rs @@ -0,0 +1,178 @@ +#[doc = "Register `SLEEPCFG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SLEEPCFG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Sleep Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SLEEPMODE_A { + #[doc = "0: CPU clock is OFF"] + IDLE0 = 0, + #[doc = "1: AHB clock is OFF"] + IDLE1 = 1, + #[doc = "2: APB clock are OFF"] + IDLE2 = 2, + #[doc = "4: All Clocks are OFF"] + STANDBY = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SLEEPMODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `SLEEPMODE` reader - Sleep Mode"] +pub struct SLEEPMODE_R(crate::FieldReader); +impl SLEEPMODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SLEEPMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SLEEPMODE_A::IDLE0), + 1 => Some(SLEEPMODE_A::IDLE1), + 2 => Some(SLEEPMODE_A::IDLE2), + 4 => Some(SLEEPMODE_A::STANDBY), + _ => None, + } + } + #[doc = "Checks if the value of the field is `IDLE0`"] + #[inline(always)] + pub fn is_idle0(&self) -> bool { + **self == SLEEPMODE_A::IDLE0 + } + #[doc = "Checks if the value of the field is `IDLE1`"] + #[inline(always)] + pub fn is_idle1(&self) -> bool { + **self == SLEEPMODE_A::IDLE1 + } + #[doc = "Checks if the value of the field is `IDLE2`"] + #[inline(always)] + pub fn is_idle2(&self) -> bool { + **self == SLEEPMODE_A::IDLE2 + } + #[doc = "Checks if the value of the field is `STANDBY`"] + #[inline(always)] + pub fn is_standby(&self) -> bool { + **self == SLEEPMODE_A::STANDBY + } +} +impl core::ops::Deref for SLEEPMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLEEPMODE` writer - Sleep Mode"] +pub struct SLEEPMODE_W<'a> { + w: &'a mut W, +} +impl<'a> SLEEPMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SLEEPMODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "CPU clock is OFF"] + #[inline(always)] + pub fn idle0(self) -> &'a mut W { + self.variant(SLEEPMODE_A::IDLE0) + } + #[doc = "AHB clock is OFF"] + #[inline(always)] + pub fn idle1(self) -> &'a mut W { + self.variant(SLEEPMODE_A::IDLE1) + } + #[doc = "APB clock are OFF"] + #[inline(always)] + pub fn idle2(self) -> &'a mut W { + self.variant(SLEEPMODE_A::IDLE2) + } + #[doc = "All Clocks are OFF"] + #[inline(always)] + pub fn standby(self) -> &'a mut W { + self.variant(SLEEPMODE_A::STANDBY) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Sleep Mode"] + #[inline(always)] + pub fn sleepmode(&self) -> SLEEPMODE_R { + SLEEPMODE_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Sleep Mode"] + #[inline(always)] + pub fn sleepmode(&mut self) -> SLEEPMODE_W { + SLEEPMODE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Sleep Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sleepcfg](index.html) module"] +pub struct SLEEPCFG_SPEC; +impl crate::RegisterSpec for SLEEPCFG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [sleepcfg::R](R) reader structure"] +impl crate::Readable for SLEEPCFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [sleepcfg::W](W) writer structure"] +impl crate::Writable for SLEEPCFG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SLEEPCFG to value 0"] +impl crate::Resettable for SLEEPCFG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/pm/stdbycfg.rs b/pac/atsamc20e/src/pm/stdbycfg.rs new file mode 100644 index 000000000000..9780f2b001f5 --- /dev/null +++ b/pac/atsamc20e/src/pm/stdbycfg.rs @@ -0,0 +1,212 @@ +#[doc = "Register `STDBYCFG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STDBYCFG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Voltage Regulator Standby mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum VREGSMOD_A { + #[doc = "0: Automatic mode"] + AUTO = 0, + #[doc = "1: Performance oriented"] + PERFORMANCE = 1, + #[doc = "2: Low Power oriented"] + LP = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: VREGSMOD_A) -> Self { + variant as _ + } +} +#[doc = "Field `VREGSMOD` reader - Voltage Regulator Standby mode"] +pub struct VREGSMOD_R(crate::FieldReader); +impl VREGSMOD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + VREGSMOD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(VREGSMOD_A::AUTO), + 1 => Some(VREGSMOD_A::PERFORMANCE), + 2 => Some(VREGSMOD_A::LP), + _ => None, + } + } + #[doc = "Checks if the value of the field is `AUTO`"] + #[inline(always)] + pub fn is_auto(&self) -> bool { + **self == VREGSMOD_A::AUTO + } + #[doc = "Checks if the value of the field is `PERFORMANCE`"] + #[inline(always)] + pub fn is_performance(&self) -> bool { + **self == VREGSMOD_A::PERFORMANCE + } + #[doc = "Checks if the value of the field is `LP`"] + #[inline(always)] + pub fn is_lp(&self) -> bool { + **self == VREGSMOD_A::LP + } +} +impl core::ops::Deref for VREGSMOD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VREGSMOD` writer - Voltage Regulator Standby mode"] +pub struct VREGSMOD_W<'a> { + w: &'a mut W, +} +impl<'a> VREGSMOD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: VREGSMOD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Automatic mode"] + #[inline(always)] + pub fn auto(self) -> &'a mut W { + self.variant(VREGSMOD_A::AUTO) + } + #[doc = "Performance oriented"] + #[inline(always)] + pub fn performance(self) -> &'a mut W { + self.variant(VREGSMOD_A::PERFORMANCE) + } + #[doc = "Low Power oriented"] + #[inline(always)] + pub fn lp(self) -> &'a mut W { + self.variant(VREGSMOD_A::LP) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 6)) | ((value as u16 & 0x03) << 6); + self.w + } +} +#[doc = "Field `BBIASHS` reader - Back Bias for HMCRAMCHS"] +pub struct BBIASHS_R(crate::FieldReader); +impl BBIASHS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BBIASHS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BBIASHS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BBIASHS` writer - Back Bias for HMCRAMCHS"] +pub struct BBIASHS_W<'a> { + w: &'a mut W, +} +impl<'a> BBIASHS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u16 & 0x01) << 10); + self.w + } +} +impl R { + #[doc = "Bits 6:7 - Voltage Regulator Standby mode"] + #[inline(always)] + pub fn vregsmod(&self) -> VREGSMOD_R { + VREGSMOD_R::new(((self.bits >> 6) & 0x03) as u8) + } + #[doc = "Bit 10 - Back Bias for HMCRAMCHS"] + #[inline(always)] + pub fn bbiashs(&self) -> BBIASHS_R { + BBIASHS_R::new(((self.bits >> 10) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 6:7 - Voltage Regulator Standby mode"] + #[inline(always)] + pub fn vregsmod(&mut self) -> VREGSMOD_W { + VREGSMOD_W { w: self } + } + #[doc = "Bit 10 - Back Bias for HMCRAMCHS"] + #[inline(always)] + pub fn bbiashs(&mut self) -> BBIASHS_W { + BBIASHS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Standby Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [stdbycfg](index.html) module"] +pub struct STDBYCFG_SPEC; +impl crate::RegisterSpec for STDBYCFG_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [stdbycfg::R](R) reader structure"] +impl crate::Readable for STDBYCFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [stdbycfg::W](W) writer structure"] +impl crate::Writable for STDBYCFG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STDBYCFG to value 0x0400"] +impl crate::Resettable for STDBYCFG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0400 + } +} diff --git a/pac/atsamc20e/src/port.rs b/pac/atsamc20e/src/port.rs new file mode 100644 index 000000000000..0ca09e672d24 --- /dev/null +++ b/pac/atsamc20e/src/port.rs @@ -0,0 +1,41 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00..0x60 - GROUP\\[%s\\]"] + pub group0: GROUP, +} +#[doc = r"Register block"] +#[repr(C)] +pub struct GROUP { + #[doc = "0x00 - Data Direction"] + pub dir: crate::Reg, + #[doc = "0x04 - Data Direction Clear"] + pub dirclr: crate::Reg, + #[doc = "0x08 - Data Direction Set"] + pub dirset: crate::Reg, + #[doc = "0x0c - Data Direction Toggle"] + pub dirtgl: crate::Reg, + #[doc = "0x10 - Data Output Value"] + pub out: crate::Reg, + #[doc = "0x14 - Data Output Value Clear"] + pub outclr: crate::Reg, + #[doc = "0x18 - Data Output Value Set"] + pub outset: crate::Reg, + #[doc = "0x1c - Data Output Value Toggle"] + pub outtgl: crate::Reg, + #[doc = "0x20 - Data Input Value"] + pub in_: crate::Reg, + #[doc = "0x24 - Control"] + pub ctrl: crate::Reg, + #[doc = "0x28 - Write Configuration"] + pub wrconfig: crate::Reg, + #[doc = "0x2c - Event Input Control"] + pub evctrl: crate::Reg, + #[doc = "0x30..0x40 - Peripheral Multiplexing n"] + pub pmux: [crate::Reg; 16], + #[doc = "0x40..0x60 - Pin Configuration n"] + pub pincfg: [crate::Reg; 32], +} +#[doc = r"Register block"] +#[doc = "GROUP\\[%s\\]"] +pub mod group; diff --git a/pac/atsamc20e/src/port/group.rs b/pac/atsamc20e/src/port/group.rs new file mode 100644 index 000000000000..d1aabcd73380 --- /dev/null +++ b/pac/atsamc20e/src/port/group.rs @@ -0,0 +1,56 @@ +#[doc = "DIR register accessor: an alias for `Reg`"] +pub type DIR = crate::Reg; +#[doc = "Data Direction"] +pub mod dir; +#[doc = "DIRCLR register accessor: an alias for `Reg`"] +pub type DIRCLR = crate::Reg; +#[doc = "Data Direction Clear"] +pub mod dirclr; +#[doc = "DIRSET register accessor: an alias for `Reg`"] +pub type DIRSET = crate::Reg; +#[doc = "Data Direction Set"] +pub mod dirset; +#[doc = "DIRTGL register accessor: an alias for `Reg`"] +pub type DIRTGL = crate::Reg; +#[doc = "Data Direction Toggle"] +pub mod dirtgl; +#[doc = "OUT register accessor: an alias for `Reg`"] +pub type OUT = crate::Reg; +#[doc = "Data Output Value"] +pub mod out; +#[doc = "OUTCLR register accessor: an alias for `Reg`"] +pub type OUTCLR = crate::Reg; +#[doc = "Data Output Value Clear"] +pub mod outclr; +#[doc = "OUTSET register accessor: an alias for `Reg`"] +pub type OUTSET = crate::Reg; +#[doc = "Data Output Value Set"] +pub mod outset; +#[doc = "OUTTGL register accessor: an alias for `Reg`"] +pub type OUTTGL = crate::Reg; +#[doc = "Data Output Value Toggle"] +pub mod outtgl; +#[doc = "IN register accessor: an alias for `Reg`"] +pub type IN = crate::Reg; +#[doc = "Data Input Value"] +pub mod in_; +#[doc = "CTRL register accessor: an alias for `Reg`"] +pub type CTRL = crate::Reg; +#[doc = "Control"] +pub mod ctrl; +#[doc = "WRCONFIG register accessor: an alias for `Reg`"] +pub type WRCONFIG = crate::Reg; +#[doc = "Write Configuration"] +pub mod wrconfig; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Input Control"] +pub mod evctrl; +#[doc = "PMUX register accessor: an alias for `Reg`"] +pub type PMUX = crate::Reg; +#[doc = "Peripheral Multiplexing n"] +pub mod pmux; +#[doc = "PINCFG register accessor: an alias for `Reg`"] +pub type PINCFG = crate::Reg; +#[doc = "Pin Configuration n"] +pub mod pincfg; diff --git a/pac/atsamc20e/src/port/group/ctrl.rs b/pac/atsamc20e/src/port/group/ctrl.rs new file mode 100644 index 000000000000..4b57cd6fcd2b --- /dev/null +++ b/pac/atsamc20e/src/port/group/ctrl.rs @@ -0,0 +1,103 @@ +#[doc = "Register `CTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SAMPLING` reader - Input Sampling Mode"] +pub struct SAMPLING_R(crate::FieldReader); +impl SAMPLING_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + SAMPLING_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SAMPLING_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SAMPLING` writer - Input Sampling Mode"] +pub struct SAMPLING_W<'a> { + w: &'a mut W, +} +impl<'a> SAMPLING_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Input Sampling Mode"] + #[inline(always)] + pub fn sampling(&self) -> SAMPLING_R { + SAMPLING_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Input Sampling Mode"] + #[inline(always)] + pub fn sampling(&mut self) -> SAMPLING_W { + SAMPLING_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"] +pub struct CTRL_SPEC; +impl crate::RegisterSpec for CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrl::R](R) reader structure"] +impl crate::Readable for CTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"] +impl crate::Writable for CTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/port/group/dir.rs b/pac/atsamc20e/src/port/group/dir.rs new file mode 100644 index 000000000000..e04452fb5d35 --- /dev/null +++ b/pac/atsamc20e/src/port/group/dir.rs @@ -0,0 +1,64 @@ +#[doc = "Register `DIR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Direction\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dir](index.html) module"] +pub struct DIR_SPEC; +impl crate::RegisterSpec for DIR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dir::R](R) reader structure"] +impl crate::Readable for DIR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dir::W](W) writer structure"] +impl crate::Writable for DIR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DIR to value 0"] +impl crate::Resettable for DIR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/port/group/dirclr.rs b/pac/atsamc20e/src/port/group/dirclr.rs new file mode 100644 index 000000000000..5e6d73d032b2 --- /dev/null +++ b/pac/atsamc20e/src/port/group/dirclr.rs @@ -0,0 +1,64 @@ +#[doc = "Register `DIRCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIRCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Direction Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dirclr](index.html) module"] +pub struct DIRCLR_SPEC; +impl crate::RegisterSpec for DIRCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dirclr::R](R) reader structure"] +impl crate::Readable for DIRCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dirclr::W](W) writer structure"] +impl crate::Writable for DIRCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DIRCLR to value 0"] +impl crate::Resettable for DIRCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/port/group/dirset.rs b/pac/atsamc20e/src/port/group/dirset.rs new file mode 100644 index 000000000000..eaa86e14f15d --- /dev/null +++ b/pac/atsamc20e/src/port/group/dirset.rs @@ -0,0 +1,64 @@ +#[doc = "Register `DIRSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIRSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Direction Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dirset](index.html) module"] +pub struct DIRSET_SPEC; +impl crate::RegisterSpec for DIRSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dirset::R](R) reader structure"] +impl crate::Readable for DIRSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dirset::W](W) writer structure"] +impl crate::Writable for DIRSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DIRSET to value 0"] +impl crate::Resettable for DIRSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/port/group/dirtgl.rs b/pac/atsamc20e/src/port/group/dirtgl.rs new file mode 100644 index 000000000000..fbd021438b1b --- /dev/null +++ b/pac/atsamc20e/src/port/group/dirtgl.rs @@ -0,0 +1,64 @@ +#[doc = "Register `DIRTGL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIRTGL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Direction Toggle\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dirtgl](index.html) module"] +pub struct DIRTGL_SPEC; +impl crate::RegisterSpec for DIRTGL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dirtgl::R](R) reader structure"] +impl crate::Readable for DIRTGL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dirtgl::W](W) writer structure"] +impl crate::Writable for DIRTGL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DIRTGL to value 0"] +impl crate::Resettable for DIRTGL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/port/group/evctrl.rs b/pac/atsamc20e/src/port/group/evctrl.rs new file mode 100644 index 000000000000..ef0a35987f3d --- /dev/null +++ b/pac/atsamc20e/src/port/group/evctrl.rs @@ -0,0 +1,625 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PID0` reader - Port Event Pin Identifier 0"] +pub struct PID0_R(crate::FieldReader); +impl PID0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PID0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PID0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PID0` writer - Port Event Pin Identifier 0"] +pub struct PID0_W<'a> { + w: &'a mut W, +} +impl<'a> PID0_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f); + self.w + } +} +#[doc = "Port Event Action 0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EVACT0_A { + #[doc = "0: Event output to pin"] + OUT = 0, + #[doc = "1: Set output register of pin on event"] + SET = 1, + #[doc = "2: Clear output register of pin on event"] + CLR = 2, + #[doc = "3: Toggle output register of pin on event"] + TGL = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EVACT0_A) -> Self { + variant as _ + } +} +#[doc = "Field `EVACT0` reader - Port Event Action 0"] +pub struct EVACT0_R(crate::FieldReader); +impl EVACT0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVACT0_A { + match self.bits { + 0 => EVACT0_A::OUT, + 1 => EVACT0_A::SET, + 2 => EVACT0_A::CLR, + 3 => EVACT0_A::TGL, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `OUT`"] + #[inline(always)] + pub fn is_out(&self) -> bool { + **self == EVACT0_A::OUT + } + #[doc = "Checks if the value of the field is `SET`"] + #[inline(always)] + pub fn is_set(&self) -> bool { + **self == EVACT0_A::SET + } + #[doc = "Checks if the value of the field is `CLR`"] + #[inline(always)] + pub fn is_clr(&self) -> bool { + **self == EVACT0_A::CLR + } + #[doc = "Checks if the value of the field is `TGL`"] + #[inline(always)] + pub fn is_tgl(&self) -> bool { + **self == EVACT0_A::TGL + } +} +impl core::ops::Deref for EVACT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT0` writer - Port Event Action 0"] +pub struct EVACT0_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT0_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EVACT0_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Event output to pin"] + #[inline(always)] + pub fn out(self) -> &'a mut W { + self.variant(EVACT0_A::OUT) + } + #[doc = "Set output register of pin on event"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(EVACT0_A::SET) + } + #[doc = "Clear output register of pin on event"] + #[inline(always)] + pub fn clr(self) -> &'a mut W { + self.variant(EVACT0_A::CLR) + } + #[doc = "Toggle output register of pin on event"] + #[inline(always)] + pub fn tgl(self) -> &'a mut W { + self.variant(EVACT0_A::TGL) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 5)) | ((value as u32 & 0x03) << 5); + self.w + } +} +#[doc = "Field `PORTEI0` reader - Port Event Enable Input 0"] +pub struct PORTEI0_R(crate::FieldReader); +impl PORTEI0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PORTEI0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PORTEI0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PORTEI0` writer - Port Event Enable Input 0"] +pub struct PORTEI0_W<'a> { + w: &'a mut W, +} +impl<'a> PORTEI0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `PID1` reader - Port Event Pin Identifier 1"] +pub struct PID1_R(crate::FieldReader); +impl PID1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PID1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PID1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PID1` writer - Port Event Pin Identifier 1"] +pub struct PID1_W<'a> { + w: &'a mut W, +} +impl<'a> PID1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 8)) | ((value as u32 & 0x1f) << 8); + self.w + } +} +#[doc = "Field `EVACT1` reader - Port Event Action 1"] +pub struct EVACT1_R(crate::FieldReader); +impl EVACT1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVACT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT1` writer - Port Event Action 1"] +pub struct EVACT1_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 13)) | ((value as u32 & 0x03) << 13); + self.w + } +} +#[doc = "Field `PORTEI1` reader - Port Event Enable Input 1"] +pub struct PORTEI1_R(crate::FieldReader); +impl PORTEI1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PORTEI1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PORTEI1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PORTEI1` writer - Port Event Enable Input 1"] +pub struct PORTEI1_W<'a> { + w: &'a mut W, +} +impl<'a> PORTEI1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `PID2` reader - Port Event Pin Identifier 2"] +pub struct PID2_R(crate::FieldReader); +impl PID2_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PID2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PID2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PID2` writer - Port Event Pin Identifier 2"] +pub struct PID2_W<'a> { + w: &'a mut W, +} +impl<'a> PID2_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 16)) | ((value as u32 & 0x1f) << 16); + self.w + } +} +#[doc = "Field `EVACT2` reader - Port Event Action 2"] +pub struct EVACT2_R(crate::FieldReader); +impl EVACT2_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVACT2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT2` writer - Port Event Action 2"] +pub struct EVACT2_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT2_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 21)) | ((value as u32 & 0x03) << 21); + self.w + } +} +#[doc = "Field `PORTEI2` reader - Port Event Enable Input 2"] +pub struct PORTEI2_R(crate::FieldReader); +impl PORTEI2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PORTEI2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PORTEI2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PORTEI2` writer - Port Event Enable Input 2"] +pub struct PORTEI2_W<'a> { + w: &'a mut W, +} +impl<'a> PORTEI2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `PID3` reader - Port Event Pin Identifier 3"] +pub struct PID3_R(crate::FieldReader); +impl PID3_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PID3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PID3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PID3` writer - Port Event Pin Identifier 3"] +pub struct PID3_W<'a> { + w: &'a mut W, +} +impl<'a> PID3_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 24)) | ((value as u32 & 0x1f) << 24); + self.w + } +} +#[doc = "Field `EVACT3` reader - Port Event Action 3"] +pub struct EVACT3_R(crate::FieldReader); +impl EVACT3_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVACT3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT3` writer - Port Event Action 3"] +pub struct EVACT3_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT3_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 29)) | ((value as u32 & 0x03) << 29); + self.w + } +} +#[doc = "Field `PORTEI3` reader - Port Event Enable Input 3"] +pub struct PORTEI3_R(crate::FieldReader); +impl PORTEI3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PORTEI3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PORTEI3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PORTEI3` writer - Port Event Enable Input 3"] +pub struct PORTEI3_W<'a> { + w: &'a mut W, +} +impl<'a> PORTEI3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Port Event Pin Identifier 0"] + #[inline(always)] + pub fn pid0(&self) -> PID0_R { + PID0_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:6 - Port Event Action 0"] + #[inline(always)] + pub fn evact0(&self) -> EVACT0_R { + EVACT0_R::new(((self.bits >> 5) & 0x03) as u8) + } + #[doc = "Bit 7 - Port Event Enable Input 0"] + #[inline(always)] + pub fn portei0(&self) -> PORTEI0_R { + PORTEI0_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:12 - Port Event Pin Identifier 1"] + #[inline(always)] + pub fn pid1(&self) -> PID1_R { + PID1_R::new(((self.bits >> 8) & 0x1f) as u8) + } + #[doc = "Bits 13:14 - Port Event Action 1"] + #[inline(always)] + pub fn evact1(&self) -> EVACT1_R { + EVACT1_R::new(((self.bits >> 13) & 0x03) as u8) + } + #[doc = "Bit 15 - Port Event Enable Input 1"] + #[inline(always)] + pub fn portei1(&self) -> PORTEI1_R { + PORTEI1_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:20 - Port Event Pin Identifier 2"] + #[inline(always)] + pub fn pid2(&self) -> PID2_R { + PID2_R::new(((self.bits >> 16) & 0x1f) as u8) + } + #[doc = "Bits 21:22 - Port Event Action 2"] + #[inline(always)] + pub fn evact2(&self) -> EVACT2_R { + EVACT2_R::new(((self.bits >> 21) & 0x03) as u8) + } + #[doc = "Bit 23 - Port Event Enable Input 2"] + #[inline(always)] + pub fn portei2(&self) -> PORTEI2_R { + PORTEI2_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bits 24:28 - Port Event Pin Identifier 3"] + #[inline(always)] + pub fn pid3(&self) -> PID3_R { + PID3_R::new(((self.bits >> 24) & 0x1f) as u8) + } + #[doc = "Bits 29:30 - Port Event Action 3"] + #[inline(always)] + pub fn evact3(&self) -> EVACT3_R { + EVACT3_R::new(((self.bits >> 29) & 0x03) as u8) + } + #[doc = "Bit 31 - Port Event Enable Input 3"] + #[inline(always)] + pub fn portei3(&self) -> PORTEI3_R { + PORTEI3_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Port Event Pin Identifier 0"] + #[inline(always)] + pub fn pid0(&mut self) -> PID0_W { + PID0_W { w: self } + } + #[doc = "Bits 5:6 - Port Event Action 0"] + #[inline(always)] + pub fn evact0(&mut self) -> EVACT0_W { + EVACT0_W { w: self } + } + #[doc = "Bit 7 - Port Event Enable Input 0"] + #[inline(always)] + pub fn portei0(&mut self) -> PORTEI0_W { + PORTEI0_W { w: self } + } + #[doc = "Bits 8:12 - Port Event Pin Identifier 1"] + #[inline(always)] + pub fn pid1(&mut self) -> PID1_W { + PID1_W { w: self } + } + #[doc = "Bits 13:14 - Port Event Action 1"] + #[inline(always)] + pub fn evact1(&mut self) -> EVACT1_W { + EVACT1_W { w: self } + } + #[doc = "Bit 15 - Port Event Enable Input 1"] + #[inline(always)] + pub fn portei1(&mut self) -> PORTEI1_W { + PORTEI1_W { w: self } + } + #[doc = "Bits 16:20 - Port Event Pin Identifier 2"] + #[inline(always)] + pub fn pid2(&mut self) -> PID2_W { + PID2_W { w: self } + } + #[doc = "Bits 21:22 - Port Event Action 2"] + #[inline(always)] + pub fn evact2(&mut self) -> EVACT2_W { + EVACT2_W { w: self } + } + #[doc = "Bit 23 - Port Event Enable Input 2"] + #[inline(always)] + pub fn portei2(&mut self) -> PORTEI2_W { + PORTEI2_W { w: self } + } + #[doc = "Bits 24:28 - Port Event Pin Identifier 3"] + #[inline(always)] + pub fn pid3(&mut self) -> PID3_W { + PID3_W { w: self } + } + #[doc = "Bits 29:30 - Port Event Action 3"] + #[inline(always)] + pub fn evact3(&mut self) -> EVACT3_W { + EVACT3_W { w: self } + } + #[doc = "Bit 31 - Port Event Enable Input 3"] + #[inline(always)] + pub fn portei3(&mut self) -> PORTEI3_W { + PORTEI3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Input Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/port/group/in_.rs b/pac/atsamc20e/src/port/group/in_.rs new file mode 100644 index 000000000000..1c8e7396a83e --- /dev/null +++ b/pac/atsamc20e/src/port/group/in_.rs @@ -0,0 +1,31 @@ +#[doc = "Register `IN` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Data Input Value\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [in_](index.html) module"] +pub struct IN_SPEC; +impl crate::RegisterSpec for IN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [in_::R](R) reader structure"] +impl crate::Readable for IN_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets IN to value 0"] +impl crate::Resettable for IN_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/port/group/out.rs b/pac/atsamc20e/src/port/group/out.rs new file mode 100644 index 000000000000..092e8dbd8023 --- /dev/null +++ b/pac/atsamc20e/src/port/group/out.rs @@ -0,0 +1,64 @@ +#[doc = "Register `OUT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OUT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Output Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [out](index.html) module"] +pub struct OUT_SPEC; +impl crate::RegisterSpec for OUT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [out::R](R) reader structure"] +impl crate::Readable for OUT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [out::W](W) writer structure"] +impl crate::Writable for OUT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OUT to value 0"] +impl crate::Resettable for OUT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/port/group/outclr.rs b/pac/atsamc20e/src/port/group/outclr.rs new file mode 100644 index 000000000000..6e734396601f --- /dev/null +++ b/pac/atsamc20e/src/port/group/outclr.rs @@ -0,0 +1,64 @@ +#[doc = "Register `OUTCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OUTCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Output Value Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [outclr](index.html) module"] +pub struct OUTCLR_SPEC; +impl crate::RegisterSpec for OUTCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [outclr::R](R) reader structure"] +impl crate::Readable for OUTCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [outclr::W](W) writer structure"] +impl crate::Writable for OUTCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OUTCLR to value 0"] +impl crate::Resettable for OUTCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/port/group/outset.rs b/pac/atsamc20e/src/port/group/outset.rs new file mode 100644 index 000000000000..6d39122deb4b --- /dev/null +++ b/pac/atsamc20e/src/port/group/outset.rs @@ -0,0 +1,64 @@ +#[doc = "Register `OUTSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OUTSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Output Value Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [outset](index.html) module"] +pub struct OUTSET_SPEC; +impl crate::RegisterSpec for OUTSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [outset::R](R) reader structure"] +impl crate::Readable for OUTSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [outset::W](W) writer structure"] +impl crate::Writable for OUTSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OUTSET to value 0"] +impl crate::Resettable for OUTSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/port/group/outtgl.rs b/pac/atsamc20e/src/port/group/outtgl.rs new file mode 100644 index 000000000000..0f3d87d6476d --- /dev/null +++ b/pac/atsamc20e/src/port/group/outtgl.rs @@ -0,0 +1,64 @@ +#[doc = "Register `OUTTGL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OUTTGL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Output Value Toggle\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [outtgl](index.html) module"] +pub struct OUTTGL_SPEC; +impl crate::RegisterSpec for OUTTGL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [outtgl::R](R) reader structure"] +impl crate::Readable for OUTTGL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [outtgl::W](W) writer structure"] +impl crate::Writable for OUTTGL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OUTTGL to value 0"] +impl crate::Resettable for OUTTGL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/port/group/pincfg.rs b/pac/atsamc20e/src/port/group/pincfg.rs new file mode 100644 index 000000000000..920af6550361 --- /dev/null +++ b/pac/atsamc20e/src/port/group/pincfg.rs @@ -0,0 +1,255 @@ +#[doc = "Register `PINCFG[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PINCFG[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PMUXEN` reader - Select Peripheral Multiplexer"] +pub struct PMUXEN_R(crate::FieldReader); +impl PMUXEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PMUXEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PMUXEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PMUXEN` writer - Select Peripheral Multiplexer"] +pub struct PMUXEN_W<'a> { + w: &'a mut W, +} +impl<'a> PMUXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `INEN` reader - Input Enable"] +pub struct INEN_R(crate::FieldReader); +impl INEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INEN` writer - Input Enable"] +pub struct INEN_W<'a> { + w: &'a mut W, +} +impl<'a> INEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PULLEN` reader - Pull Enable"] +pub struct PULLEN_R(crate::FieldReader); +impl PULLEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PULLEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PULLEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PULLEN` writer - Pull Enable"] +pub struct PULLEN_W<'a> { + w: &'a mut W, +} +impl<'a> PULLEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `DRVSTR` reader - Output Driver Strength Selection"] +pub struct DRVSTR_R(crate::FieldReader); +impl DRVSTR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRVSTR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRVSTR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRVSTR` writer - Output Driver Strength Selection"] +pub struct DRVSTR_W<'a> { + w: &'a mut W, +} +impl<'a> DRVSTR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - Select Peripheral Multiplexer"] + #[inline(always)] + pub fn pmuxen(&self) -> PMUXEN_R { + PMUXEN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Input Enable"] + #[inline(always)] + pub fn inen(&self) -> INEN_R { + INEN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Pull Enable"] + #[inline(always)] + pub fn pullen(&self) -> PULLEN_R { + PULLEN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 6 - Output Driver Strength Selection"] + #[inline(always)] + pub fn drvstr(&self) -> DRVSTR_R { + DRVSTR_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Select Peripheral Multiplexer"] + #[inline(always)] + pub fn pmuxen(&mut self) -> PMUXEN_W { + PMUXEN_W { w: self } + } + #[doc = "Bit 1 - Input Enable"] + #[inline(always)] + pub fn inen(&mut self) -> INEN_W { + INEN_W { w: self } + } + #[doc = "Bit 2 - Pull Enable"] + #[inline(always)] + pub fn pullen(&mut self) -> PULLEN_W { + PULLEN_W { w: self } + } + #[doc = "Bit 6 - Output Driver Strength Selection"] + #[inline(always)] + pub fn drvstr(&mut self) -> DRVSTR_W { + DRVSTR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Pin Configuration n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pincfg](index.html) module"] +pub struct PINCFG_SPEC; +impl crate::RegisterSpec for PINCFG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [pincfg::R](R) reader structure"] +impl crate::Readable for PINCFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [pincfg::W](W) writer structure"] +impl crate::Writable for PINCFG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PINCFG[%s] +to value 0"] +impl crate::Resettable for PINCFG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/port/group/pmux.rs b/pac/atsamc20e/src/port/group/pmux.rs new file mode 100644 index 000000000000..79c991a99daf --- /dev/null +++ b/pac/atsamc20e/src/port/group/pmux.rs @@ -0,0 +1,141 @@ +#[doc = "Register `PMUX[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PMUX[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PMUXE` reader - Peripheral Multiplexing for Even-Numbered Pin"] +pub struct PMUXE_R(crate::FieldReader); +impl PMUXE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PMUXE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PMUXE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PMUXE` writer - Peripheral Multiplexing for Even-Numbered Pin"] +pub struct PMUXE_W<'a> { + w: &'a mut W, +} +impl<'a> PMUXE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +#[doc = "Field `PMUXO` reader - Peripheral Multiplexing for Odd-Numbered Pin"] +pub struct PMUXO_R(crate::FieldReader); +impl PMUXO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PMUXO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PMUXO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PMUXO` writer - Peripheral Multiplexing for Odd-Numbered Pin"] +pub struct PMUXO_W<'a> { + w: &'a mut W, +} +impl<'a> PMUXO_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 4)) | ((value as u8 & 0x0f) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Peripheral Multiplexing for Even-Numbered Pin"] + #[inline(always)] + pub fn pmuxe(&self) -> PMUXE_R { + PMUXE_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Peripheral Multiplexing for Odd-Numbered Pin"] + #[inline(always)] + pub fn pmuxo(&self) -> PMUXO_R { + PMUXO_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Peripheral Multiplexing for Even-Numbered Pin"] + #[inline(always)] + pub fn pmuxe(&mut self) -> PMUXE_W { + PMUXE_W { w: self } + } + #[doc = "Bits 4:7 - Peripheral Multiplexing for Odd-Numbered Pin"] + #[inline(always)] + pub fn pmuxo(&mut self) -> PMUXO_W { + PMUXO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Peripheral Multiplexing n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pmux](index.html) module"] +pub struct PMUX_SPEC; +impl crate::RegisterSpec for PMUX_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [pmux::R](R) reader structure"] +impl crate::Readable for PMUX_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [pmux::W](W) writer structure"] +impl crate::Writable for PMUX_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PMUX[%s] +to value 0"] +impl crate::Resettable for PMUX_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/port/group/wrconfig.rs b/pac/atsamc20e/src/port/group/wrconfig.rs new file mode 100644 index 000000000000..c87e4f174728 --- /dev/null +++ b/pac/atsamc20e/src/port/group/wrconfig.rs @@ -0,0 +1,268 @@ +#[doc = "Register `WRCONFIG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PINMASK` writer - Pin Mask for Multiple Pin Configuration"] +pub struct PINMASK_W<'a> { + w: &'a mut W, +} +impl<'a> PINMASK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +#[doc = "Field `PMUXEN` writer - Select Peripheral Multiplexer"] +pub struct PMUXEN_W<'a> { + w: &'a mut W, +} +impl<'a> PMUXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `INEN` writer - Input Enable"] +pub struct INEN_W<'a> { + w: &'a mut W, +} +impl<'a> INEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `PULLEN` writer - Pull Enable"] +pub struct PULLEN_W<'a> { + w: &'a mut W, +} +impl<'a> PULLEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `DRVSTR` writer - Output Driver Strength Selection"] +pub struct DRVSTR_W<'a> { + w: &'a mut W, +} +impl<'a> DRVSTR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `PMUX` writer - Peripheral Multiplexing Template"] +pub struct PMUX_W<'a> { + w: &'a mut W, +} +impl<'a> PMUX_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Field `WRPMUX` writer - Write PMUX Registers"] +pub struct WRPMUX_W<'a> { + w: &'a mut W, +} +impl<'a> WRPMUX_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Field `WRPINCFG` writer - Write PINCFG Registers"] +pub struct WRPINCFG_W<'a> { + w: &'a mut W, +} +impl<'a> WRPINCFG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +#[doc = "Field `HWSEL` writer - Half-Word Select"] +pub struct HWSEL_W<'a> { + w: &'a mut W, +} +impl<'a> HWSEL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl W { + #[doc = "Bits 0:15 - Pin Mask for Multiple Pin Configuration"] + #[inline(always)] + pub fn pinmask(&mut self) -> PINMASK_W { + PINMASK_W { w: self } + } + #[doc = "Bit 16 - Select Peripheral Multiplexer"] + #[inline(always)] + pub fn pmuxen(&mut self) -> PMUXEN_W { + PMUXEN_W { w: self } + } + #[doc = "Bit 17 - Input Enable"] + #[inline(always)] + pub fn inen(&mut self) -> INEN_W { + INEN_W { w: self } + } + #[doc = "Bit 18 - Pull Enable"] + #[inline(always)] + pub fn pullen(&mut self) -> PULLEN_W { + PULLEN_W { w: self } + } + #[doc = "Bit 22 - Output Driver Strength Selection"] + #[inline(always)] + pub fn drvstr(&mut self) -> DRVSTR_W { + DRVSTR_W { w: self } + } + #[doc = "Bits 24:27 - Peripheral Multiplexing Template"] + #[inline(always)] + pub fn pmux(&mut self) -> PMUX_W { + PMUX_W { w: self } + } + #[doc = "Bit 28 - Write PMUX Registers"] + #[inline(always)] + pub fn wrpmux(&mut self) -> WRPMUX_W { + WRPMUX_W { w: self } + } + #[doc = "Bit 30 - Write PINCFG Registers"] + #[inline(always)] + pub fn wrpincfg(&mut self) -> WRPINCFG_W { + WRPINCFG_W { w: self } + } + #[doc = "Bit 31 - Half-Word Select"] + #[inline(always)] + pub fn hwsel(&mut self) -> HWSEL_W { + HWSEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Write Configuration\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wrconfig](index.html) module"] +pub struct WRCONFIG_SPEC; +impl crate::RegisterSpec for WRCONFIG_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [wrconfig::W](W) writer structure"] +impl crate::Writable for WRCONFIG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WRCONFIG to value 0"] +impl crate::Resettable for WRCONFIG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/rstc.rs b/pac/atsamc20e/src/rstc.rs new file mode 100644 index 000000000000..327b511df28a --- /dev/null +++ b/pac/atsamc20e/src/rstc.rs @@ -0,0 +1,10 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Reset Cause"] + pub rcause: crate::Reg, +} +#[doc = "RCAUSE register accessor: an alias for `Reg`"] +pub type RCAUSE = crate::Reg; +#[doc = "Reset Cause"] +pub mod rcause; diff --git a/pac/atsamc20e/src/rstc/rcause.rs b/pac/atsamc20e/src/rstc/rcause.rs new file mode 100644 index 000000000000..3dc13496e74b --- /dev/null +++ b/pac/atsamc20e/src/rstc/rcause.rs @@ -0,0 +1,153 @@ +#[doc = "Register `RCAUSE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `POR` reader - Power On Reset"] +pub struct POR_R(crate::FieldReader); +impl POR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + POR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for POR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODCORE` reader - Brown Out CORE Detector Reset"] +pub struct BODCORE_R(crate::FieldReader); +impl BODCORE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODCORE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODCORE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODVDD` reader - Brown Out VDD Detector Reset"] +pub struct BODVDD_R(crate::FieldReader); +impl BODVDD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODVDD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODVDD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXT` reader - External Reset"] +pub struct EXT_R(crate::FieldReader); +impl EXT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WDT` reader - Watchdog Reset"] +pub struct WDT_R(crate::FieldReader); +impl WDT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WDT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WDT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYST` reader - System Reset Request"] +pub struct SYST_R(crate::FieldReader); +impl SYST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Power On Reset"] + #[inline(always)] + pub fn por(&self) -> POR_R { + POR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Brown Out CORE Detector Reset"] + #[inline(always)] + pub fn bodcore(&self) -> BODCORE_R { + BODCORE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Brown Out VDD Detector Reset"] + #[inline(always)] + pub fn bodvdd(&self) -> BODVDD_R { + BODVDD_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 4 - External Reset"] + #[inline(always)] + pub fn ext(&self) -> EXT_R { + EXT_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Watchdog Reset"] + #[inline(always)] + pub fn wdt(&self) -> WDT_R { + WDT_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - System Reset Request"] + #[inline(always)] + pub fn syst(&self) -> SYST_R { + SYST_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +#[doc = "Reset Cause\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rcause](index.html) module"] +pub struct RCAUSE_SPEC; +impl crate::RegisterSpec for RCAUSE_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [rcause::R](R) reader structure"] +impl crate::Readable for RCAUSE_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets RCAUSE to value 0"] +impl crate::Resettable for RCAUSE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/rtc.rs b/pac/atsamc20e/src/rtc.rs new file mode 100644 index 000000000000..62f424cb1a8e --- /dev/null +++ b/pac/atsamc20e/src/rtc.rs @@ -0,0 +1,120 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved_0_mode0: [u8; 0x25], +} +impl RegisterBlock { + #[doc = "0x00..0x25 - Clock/Calendar with Alarm"] + #[inline(always)] + pub fn mode2(&self) -> &MODE2 { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const MODE2) } + } + #[doc = "0x00..0x24 - 16-bit Counter with Two 16-bit Compares"] + #[inline(always)] + pub fn mode1(&self) -> &MODE1 { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const MODE1) } + } + #[doc = "0x00..0x24 - 32-bit Counter with Single 32-bit Compare"] + #[inline(always)] + pub fn mode0(&self) -> &MODE0 { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const MODE0) } + } +} +#[doc = r"Register block"] +#[repr(C)] +pub struct MODE0 { + #[doc = "0x00 - MODE0 Control A"] + pub ctrla: crate::Reg, + _reserved1: [u8; 0x02], + #[doc = "0x04 - MODE0 Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x08 - MODE0 Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x0a - MODE0 Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x0c - MODE0 Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x0e - Debug Control"] + pub dbgctrl: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x10 - MODE0 Synchronization Busy Status"] + pub syncbusy: crate::Reg, + #[doc = "0x14 - Frequency Correction"] + pub freqcorr: crate::Reg, + _reserved8: [u8; 0x03], + #[doc = "0x18 - MODE0 Counter Value"] + pub count: crate::Reg, + _reserved9: [u8; 0x04], + #[doc = "0x20 - MODE0 Compare n Value"] + pub comp: crate::Reg, +} +#[doc = r"Register block"] +#[doc = "32-bit Counter with Single 32-bit Compare"] +pub mod mode0; +#[doc = r"Register block"] +#[repr(C)] +pub struct MODE1 { + #[doc = "0x00 - MODE1 Control A"] + pub ctrla: crate::Reg, + _reserved1: [u8; 0x02], + #[doc = "0x04 - MODE1 Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x08 - MODE1 Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x0a - MODE1 Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x0c - MODE1 Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x0e - Debug Control"] + pub dbgctrl: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x10 - MODE1 Synchronization Busy Status"] + pub syncbusy: crate::Reg, + #[doc = "0x14 - Frequency Correction"] + pub freqcorr: crate::Reg, + _reserved8: [u8; 0x03], + #[doc = "0x18 - MODE1 Counter Value"] + pub count: crate::Reg, + _reserved9: [u8; 0x02], + #[doc = "0x1c - MODE1 Counter Period"] + pub per: crate::Reg, + _reserved10: [u8; 0x02], + #[doc = "0x20 - MODE1 Compare n Value"] + pub comp: [crate::Reg; 2], +} +#[doc = r"Register block"] +#[doc = "16-bit Counter with Two 16-bit Compares"] +pub mod mode1; +#[doc = r"Register block"] +#[repr(C)] +pub struct MODE2 { + #[doc = "0x00 - MODE2 Control A"] + pub ctrla: crate::Reg, + _reserved1: [u8; 0x02], + #[doc = "0x04 - MODE2 Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x08 - MODE2 Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x0a - MODE2 Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x0c - MODE2 Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x0e - Debug Control"] + pub dbgctrl: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x10 - MODE2 Synchronization Busy Status"] + pub syncbusy: crate::Reg, + #[doc = "0x14 - Frequency Correction"] + pub freqcorr: crate::Reg, + _reserved8: [u8; 0x03], + #[doc = "0x18 - MODE2 Clock Value"] + pub clock: crate::Reg, + _reserved9: [u8; 0x04], + #[doc = "0x20 - MODE2_ALARM Alarm n Value"] + pub alarm: crate::Reg, + #[doc = "0x24 - MODE2_ALARM Alarm n Mask"] + pub mask: crate::Reg, +} +#[doc = r"Register block"] +#[doc = "Clock/Calendar with Alarm"] +pub mod mode2; diff --git a/pac/atsamc20e/src/rtc/mode0.rs b/pac/atsamc20e/src/rtc/mode0.rs new file mode 100644 index 000000000000..9ce5c3808169 --- /dev/null +++ b/pac/atsamc20e/src/rtc/mode0.rs @@ -0,0 +1,40 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "MODE0 Control A"] +pub mod ctrla; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "MODE0 Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "MODE0 Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "MODE0 Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "MODE0 Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "MODE0 Synchronization Busy Status"] +pub mod syncbusy; +#[doc = "FREQCORR register accessor: an alias for `Reg`"] +pub type FREQCORR = crate::Reg; +#[doc = "Frequency Correction"] +pub mod freqcorr; +#[doc = "COUNT register accessor: an alias for `Reg`"] +pub type COUNT = crate::Reg; +#[doc = "MODE0 Counter Value"] +pub mod count; +#[doc = "COMP register accessor: an alias for `Reg`"] +pub type COMP = crate::Reg; +#[doc = "MODE0 Compare n Value"] +pub mod comp; diff --git a/pac/atsamc20e/src/rtc/mode0/comp.rs b/pac/atsamc20e/src/rtc/mode0/comp.rs new file mode 100644 index 000000000000..a909d3cea2d3 --- /dev/null +++ b/pac/atsamc20e/src/rtc/mode0/comp.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COMP` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COMP` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COMP` reader - Compare Value"] +pub struct COMP_R(crate::FieldReader); +impl COMP_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COMP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP` writer - Compare Value"] +pub struct COMP_W<'a> { + w: &'a mut W, +} +impl<'a> COMP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Compare Value"] + #[inline(always)] + pub fn comp(&self) -> COMP_R { + COMP_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Compare Value"] + #[inline(always)] + pub fn comp(&mut self) -> COMP_W { + COMP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE0 Compare n Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [comp](index.html) module"] +pub struct COMP_SPEC; +impl crate::RegisterSpec for COMP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [comp::R](R) reader structure"] +impl crate::Readable for COMP_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [comp::W](W) writer structure"] +impl crate::Writable for COMP_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COMP to value 0"] +impl crate::Resettable for COMP_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/rtc/mode0/count.rs b/pac/atsamc20e/src/rtc/mode0/count.rs new file mode 100644 index 000000000000..cf880b5e77a6 --- /dev/null +++ b/pac/atsamc20e/src/rtc/mode0/count.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE0 Counter Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count](index.html) module"] +pub struct COUNT_SPEC; +impl crate::RegisterSpec for COUNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [count::R](R) reader structure"] +impl crate::Readable for COUNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count::W](W) writer structure"] +impl crate::Writable for COUNT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT to value 0"] +impl crate::Resettable for COUNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/rtc/mode0/ctrla.rs b/pac/atsamc20e/src/rtc/mode0/ctrla.rs new file mode 100644 index 000000000000..423877bd087d --- /dev/null +++ b/pac/atsamc20e/src/rtc/mode0/ctrla.rs @@ -0,0 +1,569 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: Mode 0: 32-bit Counter"] + COUNT32 = 0, + #[doc = "1: Mode 1: 16-bit Counter"] + COUNT16 = 1, + #[doc = "2: Mode 2: Clock/Calendar"] + CLOCK = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::COUNT32), + 1 => Some(MODE_A::COUNT16), + 2 => Some(MODE_A::CLOCK), + _ => None, + } + } + #[doc = "Checks if the value of the field is `COUNT32`"] + #[inline(always)] + pub fn is_count32(&self) -> bool { + **self == MODE_A::COUNT32 + } + #[doc = "Checks if the value of the field is `COUNT16`"] + #[inline(always)] + pub fn is_count16(&self) -> bool { + **self == MODE_A::COUNT16 + } + #[doc = "Checks if the value of the field is `CLOCK`"] + #[inline(always)] + pub fn is_clock(&self) -> bool { + **self == MODE_A::CLOCK + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Mode 0: 32-bit Counter"] + #[inline(always)] + pub fn count32(self) -> &'a mut W { + self.variant(MODE_A::COUNT32) + } + #[doc = "Mode 1: 16-bit Counter"] + #[inline(always)] + pub fn count16(self) -> &'a mut W { + self.variant(MODE_A::COUNT16) + } + #[doc = "Mode 2: Clock/Calendar"] + #[inline(always)] + pub fn clock(self) -> &'a mut W { + self.variant(MODE_A::CLOCK) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u16 & 0x03) << 2); + self.w + } +} +#[doc = "Field `MATCHCLR` reader - Clear on Match"] +pub struct MATCHCLR_R(crate::FieldReader); +impl MATCHCLR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MATCHCLR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MATCHCLR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MATCHCLR` writer - Clear on Match"] +pub struct MATCHCLR_W<'a> { + w: &'a mut W, +} +impl<'a> MATCHCLR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: CLK_RTC_CNT = GCLK_RTC/1"] + OFF = 0, + #[doc = "1: CLK_RTC_CNT = GCLK_RTC/1"] + DIV1 = 1, + #[doc = "2: CLK_RTC_CNT = GCLK_RTC/2"] + DIV2 = 2, + #[doc = "3: CLK_RTC_CNT = GCLK_RTC/4"] + DIV4 = 3, + #[doc = "4: CLK_RTC_CNT = GCLK_RTC/8"] + DIV8 = 4, + #[doc = "5: CLK_RTC_CNT = GCLK_RTC/16"] + DIV16 = 5, + #[doc = "6: CLK_RTC_CNT = GCLK_RTC/32"] + DIV32 = 6, + #[doc = "7: CLK_RTC_CNT = GCLK_RTC/64"] + DIV64 = 7, + #[doc = "8: CLK_RTC_CNT = GCLK_RTC/128"] + DIV128 = 8, + #[doc = "9: CLK_RTC_CNT = GCLK_RTC/256"] + DIV256 = 9, + #[doc = "10: CLK_RTC_CNT = GCLK_RTC/512"] + DIV512 = 10, + #[doc = "11: CLK_RTC_CNT = GCLK_RTC/1024"] + DIV1024 = 11, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCALER_A::OFF), + 1 => Some(PRESCALER_A::DIV1), + 2 => Some(PRESCALER_A::DIV2), + 3 => Some(PRESCALER_A::DIV4), + 4 => Some(PRESCALER_A::DIV8), + 5 => Some(PRESCALER_A::DIV16), + 6 => Some(PRESCALER_A::DIV32), + 7 => Some(PRESCALER_A::DIV64), + 8 => Some(PRESCALER_A::DIV128), + 9 => Some(PRESCALER_A::DIV256), + 10 => Some(PRESCALER_A::DIV512), + 11 => Some(PRESCALER_A::DIV1024), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == PRESCALER_A::OFF + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == PRESCALER_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == PRESCALER_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == PRESCALER_A::DIV128 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV512`"] + #[inline(always)] + pub fn is_div512(&self) -> bool { + **self == PRESCALER_A::DIV512 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PRESCALER_A::DIV1024 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(PRESCALER_A::OFF) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV32) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV128) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/512"] + #[inline(always)] + pub fn div512(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV512) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 8)) | ((value as u16 & 0x0f) << 8); + self.w + } +} +#[doc = "Field `COUNTSYNC` reader - Count Read Synchronization Enable"] +pub struct COUNTSYNC_R(crate::FieldReader); +impl COUNTSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNTSYNC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNTSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNTSYNC` writer - Count Read Synchronization Enable"] +pub struct COUNTSYNC_W<'a> { + w: &'a mut W, +} +impl<'a> COUNTSYNC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:3 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bit 7 - Clear on Match"] + #[inline(always)] + pub fn matchclr(&self) -> MATCHCLR_R { + MATCHCLR_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:11 - Prescaler"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 15 - Count Read Synchronization Enable"] + #[inline(always)] + pub fn countsync(&self) -> COUNTSYNC_R { + COUNTSYNC_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:3 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 7 - Clear on Match"] + #[inline(always)] + pub fn matchclr(&mut self) -> MATCHCLR_W { + MATCHCLR_W { w: self } + } + #[doc = "Bits 8:11 - Prescaler"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Bit 15 - Count Read Synchronization Enable"] + #[inline(always)] + pub fn countsync(&mut self) -> COUNTSYNC_W { + COUNTSYNC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE0 Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/rtc/mode0/dbgctrl.rs b/pac/atsamc20e/src/rtc/mode0/dbgctrl.rs new file mode 100644 index 000000000000..0383e70d0429 --- /dev/null +++ b/pac/atsamc20e/src/rtc/mode0/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Run During Debug"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Run During Debug"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/rtc/mode0/evctrl.rs b/pac/atsamc20e/src/rtc/mode0/evctrl.rs new file mode 100644 index 000000000000..c73647759dbe --- /dev/null +++ b/pac/atsamc20e/src/rtc/mode0/evctrl.rs @@ -0,0 +1,536 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PEREO0` reader - Periodic Interval 0 Event Output Enable"] +pub struct PEREO0_R(crate::FieldReader); +impl PEREO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO0` writer - Periodic Interval 0 Event Output Enable"] +pub struct PEREO0_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `PEREO1` reader - Periodic Interval 1 Event Output Enable"] +pub struct PEREO1_R(crate::FieldReader); +impl PEREO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO1` writer - Periodic Interval 1 Event Output Enable"] +pub struct PEREO1_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PEREO2` reader - Periodic Interval 2 Event Output Enable"] +pub struct PEREO2_R(crate::FieldReader); +impl PEREO2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO2` writer - Periodic Interval 2 Event Output Enable"] +pub struct PEREO2_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PEREO3` reader - Periodic Interval 3 Event Output Enable"] +pub struct PEREO3_R(crate::FieldReader); +impl PEREO3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO3` writer - Periodic Interval 3 Event Output Enable"] +pub struct PEREO3_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PEREO4` reader - Periodic Interval 4 Event Output Enable"] +pub struct PEREO4_R(crate::FieldReader); +impl PEREO4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO4` writer - Periodic Interval 4 Event Output Enable"] +pub struct PEREO4_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PEREO5` reader - Periodic Interval 5 Event Output Enable"] +pub struct PEREO5_R(crate::FieldReader); +impl PEREO5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO5` writer - Periodic Interval 5 Event Output Enable"] +pub struct PEREO5_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PEREO6` reader - Periodic Interval 6 Event Output Enable"] +pub struct PEREO6_R(crate::FieldReader); +impl PEREO6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO6` writer - Periodic Interval 6 Event Output Enable"] +pub struct PEREO6_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PEREO7` reader - Periodic Interval 7 Event Output Enable"] +pub struct PEREO7_R(crate::FieldReader); +impl PEREO7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO7` writer - Periodic Interval 7 Event Output Enable"] +pub struct PEREO7_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CMPEO0` reader - Compare 0 Event Output Enable"] +pub struct CMPEO0_R(crate::FieldReader); +impl CMPEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMPEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMPEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMPEO0` writer - Compare 0 Event Output Enable"] +pub struct CMPEO0_W<'a> { + w: &'a mut W, +} +impl<'a> CMPEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `OVFEO` reader - Overflow Event Output Enable"] +pub struct OVFEO_R(crate::FieldReader); +impl OVFEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVFEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVFEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVFEO` writer - Overflow Event Output Enable"] +pub struct OVFEO_W<'a> { + w: &'a mut W, +} +impl<'a> OVFEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Event Output Enable"] + #[inline(always)] + pub fn pereo0(&self) -> PEREO0_R { + PEREO0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Event Output Enable"] + #[inline(always)] + pub fn pereo1(&self) -> PEREO1_R { + PEREO1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Event Output Enable"] + #[inline(always)] + pub fn pereo2(&self) -> PEREO2_R { + PEREO2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Event Output Enable"] + #[inline(always)] + pub fn pereo3(&self) -> PEREO3_R { + PEREO3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Event Output Enable"] + #[inline(always)] + pub fn pereo4(&self) -> PEREO4_R { + PEREO4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Event Output Enable"] + #[inline(always)] + pub fn pereo5(&self) -> PEREO5_R { + PEREO5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Event Output Enable"] + #[inline(always)] + pub fn pereo6(&self) -> PEREO6_R { + PEREO6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Event Output Enable"] + #[inline(always)] + pub fn pereo7(&self) -> PEREO7_R { + PEREO7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Compare 0 Event Output Enable"] + #[inline(always)] + pub fn cmpeo0(&self) -> CMPEO0_R { + CMPEO0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&self) -> OVFEO_R { + OVFEO_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Event Output Enable"] + #[inline(always)] + pub fn pereo0(&mut self) -> PEREO0_W { + PEREO0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1 Event Output Enable"] + #[inline(always)] + pub fn pereo1(&mut self) -> PEREO1_W { + PEREO1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2 Event Output Enable"] + #[inline(always)] + pub fn pereo2(&mut self) -> PEREO2_W { + PEREO2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3 Event Output Enable"] + #[inline(always)] + pub fn pereo3(&mut self) -> PEREO3_W { + PEREO3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4 Event Output Enable"] + #[inline(always)] + pub fn pereo4(&mut self) -> PEREO4_W { + PEREO4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5 Event Output Enable"] + #[inline(always)] + pub fn pereo5(&mut self) -> PEREO5_W { + PEREO5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6 Event Output Enable"] + #[inline(always)] + pub fn pereo6(&mut self) -> PEREO6_W { + PEREO6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7 Event Output Enable"] + #[inline(always)] + pub fn pereo7(&mut self) -> PEREO7_W { + PEREO7_W { w: self } + } + #[doc = "Bit 8 - Compare 0 Event Output Enable"] + #[inline(always)] + pub fn cmpeo0(&mut self) -> CMPEO0_W { + CMPEO0_W { w: self } + } + #[doc = "Bit 15 - Overflow Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&mut self) -> OVFEO_W { + OVFEO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE0 Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/rtc/mode0/freqcorr.rs b/pac/atsamc20e/src/rtc/mode0/freqcorr.rs new file mode 100644 index 000000000000..043ba6f88eb2 --- /dev/null +++ b/pac/atsamc20e/src/rtc/mode0/freqcorr.rs @@ -0,0 +1,150 @@ +#[doc = "Register `FREQCORR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FREQCORR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `VALUE` reader - Correction Value"] +pub struct VALUE_R(crate::FieldReader); +impl VALUE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + VALUE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VALUE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VALUE` writer - Correction Value"] +pub struct VALUE_W<'a> { + w: &'a mut W, +} +impl<'a> VALUE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x7f) | (value as u8 & 0x7f); + self.w + } +} +#[doc = "Field `SIGN` reader - Correction Sign"] +pub struct SIGN_R(crate::FieldReader); +impl SIGN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SIGN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SIGN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SIGN` writer - Correction Sign"] +pub struct SIGN_W<'a> { + w: &'a mut W, +} +impl<'a> SIGN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bits 0:6 - Correction Value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bit 7 - Correction Sign"] + #[inline(always)] + pub fn sign(&self) -> SIGN_R { + SIGN_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:6 - Correction Value"] + #[inline(always)] + pub fn value(&mut self) -> VALUE_W { + VALUE_W { w: self } + } + #[doc = "Bit 7 - Correction Sign"] + #[inline(always)] + pub fn sign(&mut self) -> SIGN_W { + SIGN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Frequency Correction\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [freqcorr](index.html) module"] +pub struct FREQCORR_SPEC; +impl crate::RegisterSpec for FREQCORR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [freqcorr::R](R) reader structure"] +impl crate::Readable for FREQCORR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [freqcorr::W](W) writer structure"] +impl crate::Writable for FREQCORR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets FREQCORR to value 0"] +impl crate::Resettable for FREQCORR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/rtc/mode0/intenclr.rs b/pac/atsamc20e/src/rtc/mode0/intenclr.rs new file mode 100644 index 000000000000..8be5e2c3920b --- /dev/null +++ b/pac/atsamc20e/src/rtc/mode0/intenclr.rs @@ -0,0 +1,536 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER0` reader - Periodic Interval 0 Interrupt Enable"] +pub struct PER0_R(crate::FieldReader); +impl PER0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER0` writer - Periodic Interval 0 Interrupt Enable"] +pub struct PER0_W<'a> { + w: &'a mut W, +} +impl<'a> PER0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PER1` reader - Periodic Interval 1 Interrupt Enable"] +pub struct PER1_R(crate::FieldReader); +impl PER1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER1` writer - Periodic Interval 1 Interrupt Enable"] +pub struct PER1_W<'a> { + w: &'a mut W, +} +impl<'a> PER1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PER2` reader - Periodic Interval 2 Interrupt Enable"] +pub struct PER2_R(crate::FieldReader); +impl PER2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER2` writer - Periodic Interval 2 Interrupt Enable"] +pub struct PER2_W<'a> { + w: &'a mut W, +} +impl<'a> PER2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PER3` reader - Periodic Interval 3 Interrupt Enable"] +pub struct PER3_R(crate::FieldReader); +impl PER3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER3` writer - Periodic Interval 3 Interrupt Enable"] +pub struct PER3_W<'a> { + w: &'a mut W, +} +impl<'a> PER3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PER4` reader - Periodic Interval 4 Interrupt Enable"] +pub struct PER4_R(crate::FieldReader); +impl PER4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER4` writer - Periodic Interval 4 Interrupt Enable"] +pub struct PER4_W<'a> { + w: &'a mut W, +} +impl<'a> PER4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PER5` reader - Periodic Interval 5 Interrupt Enable"] +pub struct PER5_R(crate::FieldReader); +impl PER5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER5` writer - Periodic Interval 5 Interrupt Enable"] +pub struct PER5_W<'a> { + w: &'a mut W, +} +impl<'a> PER5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PER6` reader - Periodic Interval 6 Interrupt Enable"] +pub struct PER6_R(crate::FieldReader); +impl PER6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER6` writer - Periodic Interval 6 Interrupt Enable"] +pub struct PER6_W<'a> { + w: &'a mut W, +} +impl<'a> PER6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PER7` reader - Periodic Interval 7 Interrupt Enable"] +pub struct PER7_R(crate::FieldReader); +impl PER7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER7` writer - Periodic Interval 7 Interrupt Enable"] +pub struct PER7_W<'a> { + w: &'a mut W, +} +impl<'a> PER7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CMP0` reader - Compare 0 Interrupt Enable"] +pub struct CMP0_R(crate::FieldReader); +impl CMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP0` writer - Compare 0 Interrupt Enable"] +pub struct CMP0_W<'a> { + w: &'a mut W, +} +impl<'a> CMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + pub fn per0(&self) -> PER0_R { + PER0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + pub fn per1(&self) -> PER1_R { + PER1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + pub fn per2(&self) -> PER2_R { + PER2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + pub fn per3(&self) -> PER3_R { + PER3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + pub fn per4(&self) -> PER4_R { + PER4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + pub fn per5(&self) -> PER5_R { + PER5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + pub fn per6(&self) -> PER6_R { + PER6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + pub fn per7(&self) -> PER7_R { + PER7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&self) -> CMP0_R { + CMP0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + pub fn per0(&mut self) -> PER0_W { + PER0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + pub fn per1(&mut self) -> PER1_W { + PER1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + pub fn per2(&mut self) -> PER2_W { + PER2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + pub fn per3(&mut self) -> PER3_W { + PER3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + pub fn per4(&mut self) -> PER4_W { + PER4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + pub fn per5(&mut self) -> PER5_W { + PER5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + pub fn per6(&mut self) -> PER6_W { + PER6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + pub fn per7(&mut self) -> PER7_W { + PER7_W { w: self } + } + #[doc = "Bit 8 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&mut self) -> CMP0_W { + CMP0_W { w: self } + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE0 Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/rtc/mode0/intenset.rs b/pac/atsamc20e/src/rtc/mode0/intenset.rs new file mode 100644 index 000000000000..7228f5d486f5 --- /dev/null +++ b/pac/atsamc20e/src/rtc/mode0/intenset.rs @@ -0,0 +1,536 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER0` reader - Periodic Interval 0 Interrupt Enable"] +pub struct PER0_R(crate::FieldReader); +impl PER0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER0` writer - Periodic Interval 0 Interrupt Enable"] +pub struct PER0_W<'a> { + w: &'a mut W, +} +impl<'a> PER0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PER1` reader - Periodic Interval 1 Interrupt Enable"] +pub struct PER1_R(crate::FieldReader); +impl PER1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER1` writer - Periodic Interval 1 Interrupt Enable"] +pub struct PER1_W<'a> { + w: &'a mut W, +} +impl<'a> PER1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PER2` reader - Periodic Interval 2 Interrupt Enable"] +pub struct PER2_R(crate::FieldReader); +impl PER2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER2` writer - Periodic Interval 2 Interrupt Enable"] +pub struct PER2_W<'a> { + w: &'a mut W, +} +impl<'a> PER2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PER3` reader - Periodic Interval 3 Interrupt Enable"] +pub struct PER3_R(crate::FieldReader); +impl PER3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER3` writer - Periodic Interval 3 Interrupt Enable"] +pub struct PER3_W<'a> { + w: &'a mut W, +} +impl<'a> PER3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PER4` reader - Periodic Interval 4 Interrupt Enable"] +pub struct PER4_R(crate::FieldReader); +impl PER4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER4` writer - Periodic Interval 4 Interrupt Enable"] +pub struct PER4_W<'a> { + w: &'a mut W, +} +impl<'a> PER4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PER5` reader - Periodic Interval 5 Interrupt Enable"] +pub struct PER5_R(crate::FieldReader); +impl PER5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER5` writer - Periodic Interval 5 Interrupt Enable"] +pub struct PER5_W<'a> { + w: &'a mut W, +} +impl<'a> PER5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PER6` reader - Periodic Interval 6 Interrupt Enable"] +pub struct PER6_R(crate::FieldReader); +impl PER6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER6` writer - Periodic Interval 6 Interrupt Enable"] +pub struct PER6_W<'a> { + w: &'a mut W, +} +impl<'a> PER6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PER7` reader - Periodic Interval 7 Interrupt Enable"] +pub struct PER7_R(crate::FieldReader); +impl PER7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER7` writer - Periodic Interval 7 Interrupt Enable"] +pub struct PER7_W<'a> { + w: &'a mut W, +} +impl<'a> PER7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CMP0` reader - Compare 0 Interrupt Enable"] +pub struct CMP0_R(crate::FieldReader); +impl CMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP0` writer - Compare 0 Interrupt Enable"] +pub struct CMP0_W<'a> { + w: &'a mut W, +} +impl<'a> CMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + pub fn per0(&self) -> PER0_R { + PER0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + pub fn per1(&self) -> PER1_R { + PER1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + pub fn per2(&self) -> PER2_R { + PER2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + pub fn per3(&self) -> PER3_R { + PER3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + pub fn per4(&self) -> PER4_R { + PER4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + pub fn per5(&self) -> PER5_R { + PER5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + pub fn per6(&self) -> PER6_R { + PER6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + pub fn per7(&self) -> PER7_R { + PER7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&self) -> CMP0_R { + CMP0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + pub fn per0(&mut self) -> PER0_W { + PER0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + pub fn per1(&mut self) -> PER1_W { + PER1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + pub fn per2(&mut self) -> PER2_W { + PER2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + pub fn per3(&mut self) -> PER3_W { + PER3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + pub fn per4(&mut self) -> PER4_W { + PER4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + pub fn per5(&mut self) -> PER5_W { + PER5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + pub fn per6(&mut self) -> PER6_W { + PER6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + pub fn per7(&mut self) -> PER7_W { + PER7_W { w: self } + } + #[doc = "Bit 8 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&mut self) -> CMP0_W { + CMP0_W { w: self } + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE0 Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/rtc/mode0/intflag.rs b/pac/atsamc20e/src/rtc/mode0/intflag.rs new file mode 100644 index 000000000000..f2dccdb04aa4 --- /dev/null +++ b/pac/atsamc20e/src/rtc/mode0/intflag.rs @@ -0,0 +1,536 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER0` reader - Periodic Interval 0"] +pub struct PER0_R(crate::FieldReader); +impl PER0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER0` writer - Periodic Interval 0"] +pub struct PER0_W<'a> { + w: &'a mut W, +} +impl<'a> PER0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PER1` reader - Periodic Interval 1"] +pub struct PER1_R(crate::FieldReader); +impl PER1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER1` writer - Periodic Interval 1"] +pub struct PER1_W<'a> { + w: &'a mut W, +} +impl<'a> PER1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PER2` reader - Periodic Interval 2"] +pub struct PER2_R(crate::FieldReader); +impl PER2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER2` writer - Periodic Interval 2"] +pub struct PER2_W<'a> { + w: &'a mut W, +} +impl<'a> PER2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PER3` reader - Periodic Interval 3"] +pub struct PER3_R(crate::FieldReader); +impl PER3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER3` writer - Periodic Interval 3"] +pub struct PER3_W<'a> { + w: &'a mut W, +} +impl<'a> PER3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PER4` reader - Periodic Interval 4"] +pub struct PER4_R(crate::FieldReader); +impl PER4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER4` writer - Periodic Interval 4"] +pub struct PER4_W<'a> { + w: &'a mut W, +} +impl<'a> PER4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PER5` reader - Periodic Interval 5"] +pub struct PER5_R(crate::FieldReader); +impl PER5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER5` writer - Periodic Interval 5"] +pub struct PER5_W<'a> { + w: &'a mut W, +} +impl<'a> PER5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PER6` reader - Periodic Interval 6"] +pub struct PER6_R(crate::FieldReader); +impl PER6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER6` writer - Periodic Interval 6"] +pub struct PER6_W<'a> { + w: &'a mut W, +} +impl<'a> PER6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PER7` reader - Periodic Interval 7"] +pub struct PER7_R(crate::FieldReader); +impl PER7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER7` writer - Periodic Interval 7"] +pub struct PER7_W<'a> { + w: &'a mut W, +} +impl<'a> PER7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CMP0` reader - Compare 0"] +pub struct CMP0_R(crate::FieldReader); +impl CMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP0` writer - Compare 0"] +pub struct CMP0_W<'a> { + w: &'a mut W, +} +impl<'a> CMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0"] + #[inline(always)] + pub fn per0(&self) -> PER0_R { + PER0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1"] + #[inline(always)] + pub fn per1(&self) -> PER1_R { + PER1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2"] + #[inline(always)] + pub fn per2(&self) -> PER2_R { + PER2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3"] + #[inline(always)] + pub fn per3(&self) -> PER3_R { + PER3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4"] + #[inline(always)] + pub fn per4(&self) -> PER4_R { + PER4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5"] + #[inline(always)] + pub fn per5(&self) -> PER5_R { + PER5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6"] + #[inline(always)] + pub fn per6(&self) -> PER6_R { + PER6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7"] + #[inline(always)] + pub fn per7(&self) -> PER7_R { + PER7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Compare 0"] + #[inline(always)] + pub fn cmp0(&self) -> CMP0_R { + CMP0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0"] + #[inline(always)] + pub fn per0(&mut self) -> PER0_W { + PER0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1"] + #[inline(always)] + pub fn per1(&mut self) -> PER1_W { + PER1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2"] + #[inline(always)] + pub fn per2(&mut self) -> PER2_W { + PER2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3"] + #[inline(always)] + pub fn per3(&mut self) -> PER3_W { + PER3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4"] + #[inline(always)] + pub fn per4(&mut self) -> PER4_W { + PER4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5"] + #[inline(always)] + pub fn per5(&mut self) -> PER5_W { + PER5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6"] + #[inline(always)] + pub fn per6(&mut self) -> PER6_W { + PER6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7"] + #[inline(always)] + pub fn per7(&mut self) -> PER7_W { + PER7_W { w: self } + } + #[doc = "Bit 8 - Compare 0"] + #[inline(always)] + pub fn cmp0(&mut self) -> CMP0_W { + CMP0_W { w: self } + } + #[doc = "Bit 15 - Overflow"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE0 Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/rtc/mode0/syncbusy.rs b/pac/atsamc20e/src/rtc/mode0/syncbusy.rs new file mode 100644 index 000000000000..518dea115a18 --- /dev/null +++ b/pac/atsamc20e/src/rtc/mode0/syncbusy.rs @@ -0,0 +1,153 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - Enable Bit Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FREQCORR` reader - FREQCORR Register Busy"] +pub struct FREQCORR_R(crate::FieldReader); +impl FREQCORR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FREQCORR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FREQCORR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` reader - COUNT Register Busy"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP0` reader - COMP 0 Register Busy"] +pub struct COMP0_R(crate::FieldReader); +impl COMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNTSYNC` reader - Count Read Synchronization Enable Bit Busy"] +pub struct COUNTSYNC_R(crate::FieldReader); +impl COUNTSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNTSYNC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNTSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable Bit Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - FREQCORR Register Busy"] + #[inline(always)] + pub fn freqcorr(&self) -> FREQCORR_R { + FREQCORR_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - COUNT Register Busy"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 5 - COMP 0 Register Busy"] + #[inline(always)] + pub fn comp0(&self) -> COMP0_R { + COMP0_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 15 - Count Read Synchronization Enable Bit Busy"] + #[inline(always)] + pub fn countsync(&self) -> COUNTSYNC_R { + COUNTSYNC_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +#[doc = "MODE0 Synchronization Busy Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/rtc/mode1.rs b/pac/atsamc20e/src/rtc/mode1.rs new file mode 100644 index 000000000000..9ea1bc17497c --- /dev/null +++ b/pac/atsamc20e/src/rtc/mode1.rs @@ -0,0 +1,44 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "MODE1 Control A"] +pub mod ctrla; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "MODE1 Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "MODE1 Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "MODE1 Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "MODE1 Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "MODE1 Synchronization Busy Status"] +pub mod syncbusy; +#[doc = "FREQCORR register accessor: an alias for `Reg`"] +pub type FREQCORR = crate::Reg; +#[doc = "Frequency Correction"] +pub mod freqcorr; +#[doc = "COUNT register accessor: an alias for `Reg`"] +pub type COUNT = crate::Reg; +#[doc = "MODE1 Counter Value"] +pub mod count; +#[doc = "PER register accessor: an alias for `Reg`"] +pub type PER = crate::Reg; +#[doc = "MODE1 Counter Period"] +pub mod per; +#[doc = "COMP register accessor: an alias for `Reg`"] +pub type COMP = crate::Reg; +#[doc = "MODE1 Compare n Value"] +pub mod comp; diff --git a/pac/atsamc20e/src/rtc/mode1/comp.rs b/pac/atsamc20e/src/rtc/mode1/comp.rs new file mode 100644 index 000000000000..6935385840f1 --- /dev/null +++ b/pac/atsamc20e/src/rtc/mode1/comp.rs @@ -0,0 +1,104 @@ +#[doc = "Register `COMP[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COMP[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COMP` reader - Compare Value"] +pub struct COMP_R(crate::FieldReader); +impl COMP_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + COMP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP` writer - Compare Value"] +pub struct COMP_W<'a> { + w: &'a mut W, +} +impl<'a> COMP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Compare Value"] + #[inline(always)] + pub fn comp(&self) -> COMP_R { + COMP_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Compare Value"] + #[inline(always)] + pub fn comp(&mut self) -> COMP_W { + COMP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Compare n Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [comp](index.html) module"] +pub struct COMP_SPEC; +impl crate::RegisterSpec for COMP_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [comp::R](R) reader structure"] +impl crate::Readable for COMP_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [comp::W](W) writer structure"] +impl crate::Writable for COMP_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COMP[%s] +to value 0"] +impl crate::Resettable for COMP_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/rtc/mode1/count.rs b/pac/atsamc20e/src/rtc/mode1/count.rs new file mode 100644 index 000000000000..2c41937b189c --- /dev/null +++ b/pac/atsamc20e/src/rtc/mode1/count.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Counter Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count](index.html) module"] +pub struct COUNT_SPEC; +impl crate::RegisterSpec for COUNT_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [count::R](R) reader structure"] +impl crate::Readable for COUNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count::W](W) writer structure"] +impl crate::Writable for COUNT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT to value 0"] +impl crate::Resettable for COUNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/rtc/mode1/ctrla.rs b/pac/atsamc20e/src/rtc/mode1/ctrla.rs new file mode 100644 index 000000000000..6e3e2042a9c4 --- /dev/null +++ b/pac/atsamc20e/src/rtc/mode1/ctrla.rs @@ -0,0 +1,522 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: Mode 0: 32-bit Counter"] + COUNT32 = 0, + #[doc = "1: Mode 1: 16-bit Counter"] + COUNT16 = 1, + #[doc = "2: Mode 2: Clock/Calendar"] + CLOCK = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::COUNT32), + 1 => Some(MODE_A::COUNT16), + 2 => Some(MODE_A::CLOCK), + _ => None, + } + } + #[doc = "Checks if the value of the field is `COUNT32`"] + #[inline(always)] + pub fn is_count32(&self) -> bool { + **self == MODE_A::COUNT32 + } + #[doc = "Checks if the value of the field is `COUNT16`"] + #[inline(always)] + pub fn is_count16(&self) -> bool { + **self == MODE_A::COUNT16 + } + #[doc = "Checks if the value of the field is `CLOCK`"] + #[inline(always)] + pub fn is_clock(&self) -> bool { + **self == MODE_A::CLOCK + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Mode 0: 32-bit Counter"] + #[inline(always)] + pub fn count32(self) -> &'a mut W { + self.variant(MODE_A::COUNT32) + } + #[doc = "Mode 1: 16-bit Counter"] + #[inline(always)] + pub fn count16(self) -> &'a mut W { + self.variant(MODE_A::COUNT16) + } + #[doc = "Mode 2: Clock/Calendar"] + #[inline(always)] + pub fn clock(self) -> &'a mut W { + self.variant(MODE_A::CLOCK) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u16 & 0x03) << 2); + self.w + } +} +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: CLK_RTC_CNT = GCLK_RTC/1"] + OFF = 0, + #[doc = "1: CLK_RTC_CNT = GCLK_RTC/1"] + DIV1 = 1, + #[doc = "2: CLK_RTC_CNT = GCLK_RTC/2"] + DIV2 = 2, + #[doc = "3: CLK_RTC_CNT = GCLK_RTC/4"] + DIV4 = 3, + #[doc = "4: CLK_RTC_CNT = GCLK_RTC/8"] + DIV8 = 4, + #[doc = "5: CLK_RTC_CNT = GCLK_RTC/16"] + DIV16 = 5, + #[doc = "6: CLK_RTC_CNT = GCLK_RTC/32"] + DIV32 = 6, + #[doc = "7: CLK_RTC_CNT = GCLK_RTC/64"] + DIV64 = 7, + #[doc = "8: CLK_RTC_CNT = GCLK_RTC/128"] + DIV128 = 8, + #[doc = "9: CLK_RTC_CNT = GCLK_RTC/256"] + DIV256 = 9, + #[doc = "10: CLK_RTC_CNT = GCLK_RTC/512"] + DIV512 = 10, + #[doc = "11: CLK_RTC_CNT = GCLK_RTC/1024"] + DIV1024 = 11, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCALER_A::OFF), + 1 => Some(PRESCALER_A::DIV1), + 2 => Some(PRESCALER_A::DIV2), + 3 => Some(PRESCALER_A::DIV4), + 4 => Some(PRESCALER_A::DIV8), + 5 => Some(PRESCALER_A::DIV16), + 6 => Some(PRESCALER_A::DIV32), + 7 => Some(PRESCALER_A::DIV64), + 8 => Some(PRESCALER_A::DIV128), + 9 => Some(PRESCALER_A::DIV256), + 10 => Some(PRESCALER_A::DIV512), + 11 => Some(PRESCALER_A::DIV1024), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == PRESCALER_A::OFF + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == PRESCALER_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == PRESCALER_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == PRESCALER_A::DIV128 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV512`"] + #[inline(always)] + pub fn is_div512(&self) -> bool { + **self == PRESCALER_A::DIV512 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PRESCALER_A::DIV1024 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(PRESCALER_A::OFF) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV32) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV128) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/512"] + #[inline(always)] + pub fn div512(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV512) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 8)) | ((value as u16 & 0x0f) << 8); + self.w + } +} +#[doc = "Field `COUNTSYNC` reader - Count Read Synchronization Enable"] +pub struct COUNTSYNC_R(crate::FieldReader); +impl COUNTSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNTSYNC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNTSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNTSYNC` writer - Count Read Synchronization Enable"] +pub struct COUNTSYNC_W<'a> { + w: &'a mut W, +} +impl<'a> COUNTSYNC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:3 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bits 8:11 - Prescaler"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 15 - Count Read Synchronization Enable"] + #[inline(always)] + pub fn countsync(&self) -> COUNTSYNC_R { + COUNTSYNC_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:3 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bits 8:11 - Prescaler"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Bit 15 - Count Read Synchronization Enable"] + #[inline(always)] + pub fn countsync(&mut self) -> COUNTSYNC_W { + COUNTSYNC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/rtc/mode1/dbgctrl.rs b/pac/atsamc20e/src/rtc/mode1/dbgctrl.rs new file mode 100644 index 000000000000..0383e70d0429 --- /dev/null +++ b/pac/atsamc20e/src/rtc/mode1/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Run During Debug"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Run During Debug"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/rtc/mode1/evctrl.rs b/pac/atsamc20e/src/rtc/mode1/evctrl.rs new file mode 100644 index 000000000000..e15624f828c7 --- /dev/null +++ b/pac/atsamc20e/src/rtc/mode1/evctrl.rs @@ -0,0 +1,583 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PEREO0` reader - Periodic Interval 0 Event Output Enable"] +pub struct PEREO0_R(crate::FieldReader); +impl PEREO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO0` writer - Periodic Interval 0 Event Output Enable"] +pub struct PEREO0_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `PEREO1` reader - Periodic Interval 1 Event Output Enable"] +pub struct PEREO1_R(crate::FieldReader); +impl PEREO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO1` writer - Periodic Interval 1 Event Output Enable"] +pub struct PEREO1_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PEREO2` reader - Periodic Interval 2 Event Output Enable"] +pub struct PEREO2_R(crate::FieldReader); +impl PEREO2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO2` writer - Periodic Interval 2 Event Output Enable"] +pub struct PEREO2_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PEREO3` reader - Periodic Interval 3 Event Output Enable"] +pub struct PEREO3_R(crate::FieldReader); +impl PEREO3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO3` writer - Periodic Interval 3 Event Output Enable"] +pub struct PEREO3_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PEREO4` reader - Periodic Interval 4 Event Output Enable"] +pub struct PEREO4_R(crate::FieldReader); +impl PEREO4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO4` writer - Periodic Interval 4 Event Output Enable"] +pub struct PEREO4_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PEREO5` reader - Periodic Interval 5 Event Output Enable"] +pub struct PEREO5_R(crate::FieldReader); +impl PEREO5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO5` writer - Periodic Interval 5 Event Output Enable"] +pub struct PEREO5_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PEREO6` reader - Periodic Interval 6 Event Output Enable"] +pub struct PEREO6_R(crate::FieldReader); +impl PEREO6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO6` writer - Periodic Interval 6 Event Output Enable"] +pub struct PEREO6_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PEREO7` reader - Periodic Interval 7 Event Output Enable"] +pub struct PEREO7_R(crate::FieldReader); +impl PEREO7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO7` writer - Periodic Interval 7 Event Output Enable"] +pub struct PEREO7_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CMPEO0` reader - Compare 0 Event Output Enable"] +pub struct CMPEO0_R(crate::FieldReader); +impl CMPEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMPEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMPEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMPEO0` writer - Compare 0 Event Output Enable"] +pub struct CMPEO0_W<'a> { + w: &'a mut W, +} +impl<'a> CMPEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `CMPEO1` reader - Compare 1 Event Output Enable"] +pub struct CMPEO1_R(crate::FieldReader); +impl CMPEO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMPEO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMPEO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMPEO1` writer - Compare 1 Event Output Enable"] +pub struct CMPEO1_W<'a> { + w: &'a mut W, +} +impl<'a> CMPEO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `OVFEO` reader - Overflow Event Output Enable"] +pub struct OVFEO_R(crate::FieldReader); +impl OVFEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVFEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVFEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVFEO` writer - Overflow Event Output Enable"] +pub struct OVFEO_W<'a> { + w: &'a mut W, +} +impl<'a> OVFEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Event Output Enable"] + #[inline(always)] + pub fn pereo0(&self) -> PEREO0_R { + PEREO0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Event Output Enable"] + #[inline(always)] + pub fn pereo1(&self) -> PEREO1_R { + PEREO1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Event Output Enable"] + #[inline(always)] + pub fn pereo2(&self) -> PEREO2_R { + PEREO2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Event Output Enable"] + #[inline(always)] + pub fn pereo3(&self) -> PEREO3_R { + PEREO3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Event Output Enable"] + #[inline(always)] + pub fn pereo4(&self) -> PEREO4_R { + PEREO4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Event Output Enable"] + #[inline(always)] + pub fn pereo5(&self) -> PEREO5_R { + PEREO5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Event Output Enable"] + #[inline(always)] + pub fn pereo6(&self) -> PEREO6_R { + PEREO6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Event Output Enable"] + #[inline(always)] + pub fn pereo7(&self) -> PEREO7_R { + PEREO7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Compare 0 Event Output Enable"] + #[inline(always)] + pub fn cmpeo0(&self) -> CMPEO0_R { + CMPEO0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Compare 1 Event Output Enable"] + #[inline(always)] + pub fn cmpeo1(&self) -> CMPEO1_R { + CMPEO1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&self) -> OVFEO_R { + OVFEO_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Event Output Enable"] + #[inline(always)] + pub fn pereo0(&mut self) -> PEREO0_W { + PEREO0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1 Event Output Enable"] + #[inline(always)] + pub fn pereo1(&mut self) -> PEREO1_W { + PEREO1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2 Event Output Enable"] + #[inline(always)] + pub fn pereo2(&mut self) -> PEREO2_W { + PEREO2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3 Event Output Enable"] + #[inline(always)] + pub fn pereo3(&mut self) -> PEREO3_W { + PEREO3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4 Event Output Enable"] + #[inline(always)] + pub fn pereo4(&mut self) -> PEREO4_W { + PEREO4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5 Event Output Enable"] + #[inline(always)] + pub fn pereo5(&mut self) -> PEREO5_W { + PEREO5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6 Event Output Enable"] + #[inline(always)] + pub fn pereo6(&mut self) -> PEREO6_W { + PEREO6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7 Event Output Enable"] + #[inline(always)] + pub fn pereo7(&mut self) -> PEREO7_W { + PEREO7_W { w: self } + } + #[doc = "Bit 8 - Compare 0 Event Output Enable"] + #[inline(always)] + pub fn cmpeo0(&mut self) -> CMPEO0_W { + CMPEO0_W { w: self } + } + #[doc = "Bit 9 - Compare 1 Event Output Enable"] + #[inline(always)] + pub fn cmpeo1(&mut self) -> CMPEO1_W { + CMPEO1_W { w: self } + } + #[doc = "Bit 15 - Overflow Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&mut self) -> OVFEO_W { + OVFEO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/rtc/mode1/freqcorr.rs b/pac/atsamc20e/src/rtc/mode1/freqcorr.rs new file mode 100644 index 000000000000..043ba6f88eb2 --- /dev/null +++ b/pac/atsamc20e/src/rtc/mode1/freqcorr.rs @@ -0,0 +1,150 @@ +#[doc = "Register `FREQCORR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FREQCORR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `VALUE` reader - Correction Value"] +pub struct VALUE_R(crate::FieldReader); +impl VALUE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + VALUE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VALUE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VALUE` writer - Correction Value"] +pub struct VALUE_W<'a> { + w: &'a mut W, +} +impl<'a> VALUE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x7f) | (value as u8 & 0x7f); + self.w + } +} +#[doc = "Field `SIGN` reader - Correction Sign"] +pub struct SIGN_R(crate::FieldReader); +impl SIGN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SIGN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SIGN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SIGN` writer - Correction Sign"] +pub struct SIGN_W<'a> { + w: &'a mut W, +} +impl<'a> SIGN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bits 0:6 - Correction Value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bit 7 - Correction Sign"] + #[inline(always)] + pub fn sign(&self) -> SIGN_R { + SIGN_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:6 - Correction Value"] + #[inline(always)] + pub fn value(&mut self) -> VALUE_W { + VALUE_W { w: self } + } + #[doc = "Bit 7 - Correction Sign"] + #[inline(always)] + pub fn sign(&mut self) -> SIGN_W { + SIGN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Frequency Correction\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [freqcorr](index.html) module"] +pub struct FREQCORR_SPEC; +impl crate::RegisterSpec for FREQCORR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [freqcorr::R](R) reader structure"] +impl crate::Readable for FREQCORR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [freqcorr::W](W) writer structure"] +impl crate::Writable for FREQCORR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets FREQCORR to value 0"] +impl crate::Resettable for FREQCORR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/rtc/mode1/intenclr.rs b/pac/atsamc20e/src/rtc/mode1/intenclr.rs new file mode 100644 index 000000000000..d3fc5b3df34b --- /dev/null +++ b/pac/atsamc20e/src/rtc/mode1/intenclr.rs @@ -0,0 +1,583 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER0` reader - Periodic Interval 0 Interrupt Enable"] +pub struct PER0_R(crate::FieldReader); +impl PER0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER0` writer - Periodic Interval 0 Interrupt Enable"] +pub struct PER0_W<'a> { + w: &'a mut W, +} +impl<'a> PER0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PER1` reader - Periodic Interval 1 Interrupt Enable"] +pub struct PER1_R(crate::FieldReader); +impl PER1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER1` writer - Periodic Interval 1 Interrupt Enable"] +pub struct PER1_W<'a> { + w: &'a mut W, +} +impl<'a> PER1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PER2` reader - Periodic Interval 2 Interrupt Enable"] +pub struct PER2_R(crate::FieldReader); +impl PER2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER2` writer - Periodic Interval 2 Interrupt Enable"] +pub struct PER2_W<'a> { + w: &'a mut W, +} +impl<'a> PER2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PER3` reader - Periodic Interval 3 Interrupt Enable"] +pub struct PER3_R(crate::FieldReader); +impl PER3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER3` writer - Periodic Interval 3 Interrupt Enable"] +pub struct PER3_W<'a> { + w: &'a mut W, +} +impl<'a> PER3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PER4` reader - Periodic Interval 4 Interrupt Enable"] +pub struct PER4_R(crate::FieldReader); +impl PER4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER4` writer - Periodic Interval 4 Interrupt Enable"] +pub struct PER4_W<'a> { + w: &'a mut W, +} +impl<'a> PER4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PER5` reader - Periodic Interval 5 Interrupt Enable"] +pub struct PER5_R(crate::FieldReader); +impl PER5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER5` writer - Periodic Interval 5 Interrupt Enable"] +pub struct PER5_W<'a> { + w: &'a mut W, +} +impl<'a> PER5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PER6` reader - Periodic Interval 6 Interrupt Enable"] +pub struct PER6_R(crate::FieldReader); +impl PER6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER6` writer - Periodic Interval 6 Interrupt Enable"] +pub struct PER6_W<'a> { + w: &'a mut W, +} +impl<'a> PER6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PER7` reader - Periodic Interval 7 Interrupt Enable"] +pub struct PER7_R(crate::FieldReader); +impl PER7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER7` writer - Periodic Interval 7 Interrupt Enable"] +pub struct PER7_W<'a> { + w: &'a mut W, +} +impl<'a> PER7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CMP0` reader - Compare 0 Interrupt Enable"] +pub struct CMP0_R(crate::FieldReader); +impl CMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP0` writer - Compare 0 Interrupt Enable"] +pub struct CMP0_W<'a> { + w: &'a mut W, +} +impl<'a> CMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `CMP1` reader - Compare 1 Interrupt Enable"] +pub struct CMP1_R(crate::FieldReader); +impl CMP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP1` writer - Compare 1 Interrupt Enable"] +pub struct CMP1_W<'a> { + w: &'a mut W, +} +impl<'a> CMP1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + pub fn per0(&self) -> PER0_R { + PER0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + pub fn per1(&self) -> PER1_R { + PER1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + pub fn per2(&self) -> PER2_R { + PER2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + pub fn per3(&self) -> PER3_R { + PER3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + pub fn per4(&self) -> PER4_R { + PER4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + pub fn per5(&self) -> PER5_R { + PER5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + pub fn per6(&self) -> PER6_R { + PER6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + pub fn per7(&self) -> PER7_R { + PER7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&self) -> CMP0_R { + CMP0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Compare 1 Interrupt Enable"] + #[inline(always)] + pub fn cmp1(&self) -> CMP1_R { + CMP1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + pub fn per0(&mut self) -> PER0_W { + PER0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + pub fn per1(&mut self) -> PER1_W { + PER1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + pub fn per2(&mut self) -> PER2_W { + PER2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + pub fn per3(&mut self) -> PER3_W { + PER3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + pub fn per4(&mut self) -> PER4_W { + PER4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + pub fn per5(&mut self) -> PER5_W { + PER5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + pub fn per6(&mut self) -> PER6_W { + PER6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + pub fn per7(&mut self) -> PER7_W { + PER7_W { w: self } + } + #[doc = "Bit 8 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&mut self) -> CMP0_W { + CMP0_W { w: self } + } + #[doc = "Bit 9 - Compare 1 Interrupt Enable"] + #[inline(always)] + pub fn cmp1(&mut self) -> CMP1_W { + CMP1_W { w: self } + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/rtc/mode1/intenset.rs b/pac/atsamc20e/src/rtc/mode1/intenset.rs new file mode 100644 index 000000000000..074cb377926a --- /dev/null +++ b/pac/atsamc20e/src/rtc/mode1/intenset.rs @@ -0,0 +1,583 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER0` reader - Periodic Interval 0 Interrupt Enable"] +pub struct PER0_R(crate::FieldReader); +impl PER0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER0` writer - Periodic Interval 0 Interrupt Enable"] +pub struct PER0_W<'a> { + w: &'a mut W, +} +impl<'a> PER0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PER1` reader - Periodic Interval 1 Interrupt Enable"] +pub struct PER1_R(crate::FieldReader); +impl PER1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER1` writer - Periodic Interval 1 Interrupt Enable"] +pub struct PER1_W<'a> { + w: &'a mut W, +} +impl<'a> PER1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PER2` reader - Periodic Interval 2 Interrupt Enable"] +pub struct PER2_R(crate::FieldReader); +impl PER2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER2` writer - Periodic Interval 2 Interrupt Enable"] +pub struct PER2_W<'a> { + w: &'a mut W, +} +impl<'a> PER2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PER3` reader - Periodic Interval 3 Interrupt Enable"] +pub struct PER3_R(crate::FieldReader); +impl PER3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER3` writer - Periodic Interval 3 Interrupt Enable"] +pub struct PER3_W<'a> { + w: &'a mut W, +} +impl<'a> PER3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PER4` reader - Periodic Interval 4 Interrupt Enable"] +pub struct PER4_R(crate::FieldReader); +impl PER4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER4` writer - Periodic Interval 4 Interrupt Enable"] +pub struct PER4_W<'a> { + w: &'a mut W, +} +impl<'a> PER4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PER5` reader - Periodic Interval 5 Interrupt Enable"] +pub struct PER5_R(crate::FieldReader); +impl PER5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER5` writer - Periodic Interval 5 Interrupt Enable"] +pub struct PER5_W<'a> { + w: &'a mut W, +} +impl<'a> PER5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PER6` reader - Periodic Interval 6 Interrupt Enable"] +pub struct PER6_R(crate::FieldReader); +impl PER6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER6` writer - Periodic Interval 6 Interrupt Enable"] +pub struct PER6_W<'a> { + w: &'a mut W, +} +impl<'a> PER6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PER7` reader - Periodic Interval 7 Interrupt Enable"] +pub struct PER7_R(crate::FieldReader); +impl PER7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER7` writer - Periodic Interval 7 Interrupt Enable"] +pub struct PER7_W<'a> { + w: &'a mut W, +} +impl<'a> PER7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CMP0` reader - Compare 0 Interrupt Enable"] +pub struct CMP0_R(crate::FieldReader); +impl CMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP0` writer - Compare 0 Interrupt Enable"] +pub struct CMP0_W<'a> { + w: &'a mut W, +} +impl<'a> CMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `CMP1` reader - Compare 1 Interrupt Enable"] +pub struct CMP1_R(crate::FieldReader); +impl CMP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP1` writer - Compare 1 Interrupt Enable"] +pub struct CMP1_W<'a> { + w: &'a mut W, +} +impl<'a> CMP1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + pub fn per0(&self) -> PER0_R { + PER0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + pub fn per1(&self) -> PER1_R { + PER1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + pub fn per2(&self) -> PER2_R { + PER2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + pub fn per3(&self) -> PER3_R { + PER3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + pub fn per4(&self) -> PER4_R { + PER4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + pub fn per5(&self) -> PER5_R { + PER5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + pub fn per6(&self) -> PER6_R { + PER6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + pub fn per7(&self) -> PER7_R { + PER7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&self) -> CMP0_R { + CMP0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Compare 1 Interrupt Enable"] + #[inline(always)] + pub fn cmp1(&self) -> CMP1_R { + CMP1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + pub fn per0(&mut self) -> PER0_W { + PER0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + pub fn per1(&mut self) -> PER1_W { + PER1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + pub fn per2(&mut self) -> PER2_W { + PER2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + pub fn per3(&mut self) -> PER3_W { + PER3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + pub fn per4(&mut self) -> PER4_W { + PER4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + pub fn per5(&mut self) -> PER5_W { + PER5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + pub fn per6(&mut self) -> PER6_W { + PER6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + pub fn per7(&mut self) -> PER7_W { + PER7_W { w: self } + } + #[doc = "Bit 8 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&mut self) -> CMP0_W { + CMP0_W { w: self } + } + #[doc = "Bit 9 - Compare 1 Interrupt Enable"] + #[inline(always)] + pub fn cmp1(&mut self) -> CMP1_W { + CMP1_W { w: self } + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/rtc/mode1/intflag.rs b/pac/atsamc20e/src/rtc/mode1/intflag.rs new file mode 100644 index 000000000000..25bce956f46b --- /dev/null +++ b/pac/atsamc20e/src/rtc/mode1/intflag.rs @@ -0,0 +1,583 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER0` reader - Periodic Interval 0"] +pub struct PER0_R(crate::FieldReader); +impl PER0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER0` writer - Periodic Interval 0"] +pub struct PER0_W<'a> { + w: &'a mut W, +} +impl<'a> PER0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PER1` reader - Periodic Interval 1"] +pub struct PER1_R(crate::FieldReader); +impl PER1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER1` writer - Periodic Interval 1"] +pub struct PER1_W<'a> { + w: &'a mut W, +} +impl<'a> PER1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PER2` reader - Periodic Interval 2"] +pub struct PER2_R(crate::FieldReader); +impl PER2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER2` writer - Periodic Interval 2"] +pub struct PER2_W<'a> { + w: &'a mut W, +} +impl<'a> PER2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PER3` reader - Periodic Interval 3"] +pub struct PER3_R(crate::FieldReader); +impl PER3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER3` writer - Periodic Interval 3"] +pub struct PER3_W<'a> { + w: &'a mut W, +} +impl<'a> PER3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PER4` reader - Periodic Interval 4"] +pub struct PER4_R(crate::FieldReader); +impl PER4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER4` writer - Periodic Interval 4"] +pub struct PER4_W<'a> { + w: &'a mut W, +} +impl<'a> PER4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PER5` reader - Periodic Interval 5"] +pub struct PER5_R(crate::FieldReader); +impl PER5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER5` writer - Periodic Interval 5"] +pub struct PER5_W<'a> { + w: &'a mut W, +} +impl<'a> PER5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PER6` reader - Periodic Interval 6"] +pub struct PER6_R(crate::FieldReader); +impl PER6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER6` writer - Periodic Interval 6"] +pub struct PER6_W<'a> { + w: &'a mut W, +} +impl<'a> PER6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PER7` reader - Periodic Interval 7"] +pub struct PER7_R(crate::FieldReader); +impl PER7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER7` writer - Periodic Interval 7"] +pub struct PER7_W<'a> { + w: &'a mut W, +} +impl<'a> PER7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CMP0` reader - Compare 0"] +pub struct CMP0_R(crate::FieldReader); +impl CMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP0` writer - Compare 0"] +pub struct CMP0_W<'a> { + w: &'a mut W, +} +impl<'a> CMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `CMP1` reader - Compare 1"] +pub struct CMP1_R(crate::FieldReader); +impl CMP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP1` writer - Compare 1"] +pub struct CMP1_W<'a> { + w: &'a mut W, +} +impl<'a> CMP1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0"] + #[inline(always)] + pub fn per0(&self) -> PER0_R { + PER0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1"] + #[inline(always)] + pub fn per1(&self) -> PER1_R { + PER1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2"] + #[inline(always)] + pub fn per2(&self) -> PER2_R { + PER2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3"] + #[inline(always)] + pub fn per3(&self) -> PER3_R { + PER3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4"] + #[inline(always)] + pub fn per4(&self) -> PER4_R { + PER4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5"] + #[inline(always)] + pub fn per5(&self) -> PER5_R { + PER5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6"] + #[inline(always)] + pub fn per6(&self) -> PER6_R { + PER6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7"] + #[inline(always)] + pub fn per7(&self) -> PER7_R { + PER7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Compare 0"] + #[inline(always)] + pub fn cmp0(&self) -> CMP0_R { + CMP0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Compare 1"] + #[inline(always)] + pub fn cmp1(&self) -> CMP1_R { + CMP1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0"] + #[inline(always)] + pub fn per0(&mut self) -> PER0_W { + PER0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1"] + #[inline(always)] + pub fn per1(&mut self) -> PER1_W { + PER1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2"] + #[inline(always)] + pub fn per2(&mut self) -> PER2_W { + PER2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3"] + #[inline(always)] + pub fn per3(&mut self) -> PER3_W { + PER3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4"] + #[inline(always)] + pub fn per4(&mut self) -> PER4_W { + PER4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5"] + #[inline(always)] + pub fn per5(&mut self) -> PER5_W { + PER5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6"] + #[inline(always)] + pub fn per6(&mut self) -> PER6_W { + PER6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7"] + #[inline(always)] + pub fn per7(&mut self) -> PER7_W { + PER7_W { w: self } + } + #[doc = "Bit 8 - Compare 0"] + #[inline(always)] + pub fn cmp0(&mut self) -> CMP0_W { + CMP0_W { w: self } + } + #[doc = "Bit 9 - Compare 1"] + #[inline(always)] + pub fn cmp1(&mut self) -> CMP1_W { + CMP1_W { w: self } + } + #[doc = "Bit 15 - Overflow"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/rtc/mode1/per.rs b/pac/atsamc20e/src/rtc/mode1/per.rs new file mode 100644 index 000000000000..c09b31fa30dd --- /dev/null +++ b/pac/atsamc20e/src/rtc/mode1/per.rs @@ -0,0 +1,103 @@ +#[doc = "Register `PER` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PER` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER` reader - Counter Period"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` writer - Counter Period"] +pub struct PER_W<'a> { + w: &'a mut W, +} +impl<'a> PER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Counter Period"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Counter Period"] + #[inline(always)] + pub fn per(&mut self) -> PER_W { + PER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Counter Period\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [per](index.html) module"] +pub struct PER_SPEC; +impl crate::RegisterSpec for PER_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [per::R](R) reader structure"] +impl crate::Readable for PER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [per::W](W) writer structure"] +impl crate::Writable for PER_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PER to value 0"] +impl crate::Resettable for PER_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/rtc/mode1/syncbusy.rs b/pac/atsamc20e/src/rtc/mode1/syncbusy.rs new file mode 100644 index 000000000000..b64c973bafff --- /dev/null +++ b/pac/atsamc20e/src/rtc/mode1/syncbusy.rs @@ -0,0 +1,193 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Bit Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - Enable Bit Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FREQCORR` reader - FREQCORR Register Busy"] +pub struct FREQCORR_R(crate::FieldReader); +impl FREQCORR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FREQCORR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FREQCORR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` reader - COUNT Register Busy"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` reader - PER Register Busy"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP0` reader - COMP 0 Register Busy"] +pub struct COMP0_R(crate::FieldReader); +impl COMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP1` reader - COMP 1 Register Busy"] +pub struct COMP1_R(crate::FieldReader); +impl COMP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNTSYNC` reader - Count Read Synchronization Enable Bit Busy"] +pub struct COUNTSYNC_R(crate::FieldReader); +impl COUNTSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNTSYNC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNTSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Bit Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable Bit Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - FREQCORR Register Busy"] + #[inline(always)] + pub fn freqcorr(&self) -> FREQCORR_R { + FREQCORR_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - COUNT Register Busy"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - PER Register Busy"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - COMP 0 Register Busy"] + #[inline(always)] + pub fn comp0(&self) -> COMP0_R { + COMP0_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - COMP 1 Register Busy"] + #[inline(always)] + pub fn comp1(&self) -> COMP1_R { + COMP1_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 15 - Count Read Synchronization Enable Bit Busy"] + #[inline(always)] + pub fn countsync(&self) -> COUNTSYNC_R { + COUNTSYNC_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +#[doc = "MODE1 Synchronization Busy Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/rtc/mode2.rs b/pac/atsamc20e/src/rtc/mode2.rs new file mode 100644 index 000000000000..b0bc13e81dbc --- /dev/null +++ b/pac/atsamc20e/src/rtc/mode2.rs @@ -0,0 +1,44 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "MODE2 Control A"] +pub mod ctrla; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "MODE2 Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "MODE2 Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "MODE2 Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "MODE2 Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "MODE2 Synchronization Busy Status"] +pub mod syncbusy; +#[doc = "FREQCORR register accessor: an alias for `Reg`"] +pub type FREQCORR = crate::Reg; +#[doc = "Frequency Correction"] +pub mod freqcorr; +#[doc = "CLOCK register accessor: an alias for `Reg`"] +pub type CLOCK = crate::Reg; +#[doc = "MODE2 Clock Value"] +pub mod clock; +#[doc = "ALARM register accessor: an alias for `Reg`"] +pub type ALARM = crate::Reg; +#[doc = "MODE2_ALARM Alarm n Value"] +pub mod alarm; +#[doc = "MASK register accessor: an alias for `Reg`"] +pub type MASK = crate::Reg; +#[doc = "MODE2_ALARM Alarm n Mask"] +pub mod mask; diff --git a/pac/atsamc20e/src/rtc/mode2/alarm.rs b/pac/atsamc20e/src/rtc/mode2/alarm.rs new file mode 100644 index 000000000000..1242477ea69f --- /dev/null +++ b/pac/atsamc20e/src/rtc/mode2/alarm.rs @@ -0,0 +1,337 @@ +#[doc = "Register `ALARM` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ALARM` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SECOND` reader - Second"] +pub struct SECOND_R(crate::FieldReader); +impl SECOND_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SECOND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SECOND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SECOND` writer - Second"] +pub struct SECOND_W<'a> { + w: &'a mut W, +} +impl<'a> SECOND_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +#[doc = "Field `MINUTE` reader - Minute"] +pub struct MINUTE_R(crate::FieldReader); +impl MINUTE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MINUTE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MINUTE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MINUTE` writer - Minute"] +pub struct MINUTE_W<'a> { + w: &'a mut W, +} +impl<'a> MINUTE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 6)) | ((value as u32 & 0x3f) << 6); + self.w + } +} +#[doc = "Hour\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum HOUR_A { + #[doc = "0: Morning hour"] + AM = 0, + #[doc = "16: Afternoon hour"] + PM = 16, +} +impl From for u8 { + #[inline(always)] + fn from(variant: HOUR_A) -> Self { + variant as _ + } +} +#[doc = "Field `HOUR` reader - Hour"] +pub struct HOUR_R(crate::FieldReader); +impl HOUR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + HOUR_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(HOUR_A::AM), + 16 => Some(HOUR_A::PM), + _ => None, + } + } + #[doc = "Checks if the value of the field is `AM`"] + #[inline(always)] + pub fn is_am(&self) -> bool { + **self == HOUR_A::AM + } + #[doc = "Checks if the value of the field is `PM`"] + #[inline(always)] + pub fn is_pm(&self) -> bool { + **self == HOUR_A::PM + } +} +impl core::ops::Deref for HOUR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HOUR` writer - Hour"] +pub struct HOUR_W<'a> { + w: &'a mut W, +} +impl<'a> HOUR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: HOUR_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Morning hour"] + #[inline(always)] + pub fn am(self) -> &'a mut W { + self.variant(HOUR_A::AM) + } + #[doc = "Afternoon hour"] + #[inline(always)] + pub fn pm(self) -> &'a mut W { + self.variant(HOUR_A::PM) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 12)) | ((value as u32 & 0x1f) << 12); + self.w + } +} +#[doc = "Field `DAY` reader - Day"] +pub struct DAY_R(crate::FieldReader); +impl DAY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DAY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DAY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DAY` writer - Day"] +pub struct DAY_W<'a> { + w: &'a mut W, +} +impl<'a> DAY_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 17)) | ((value as u32 & 0x1f) << 17); + self.w + } +} +#[doc = "Field `MONTH` reader - Month"] +pub struct MONTH_R(crate::FieldReader); +impl MONTH_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MONTH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MONTH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MONTH` writer - Month"] +pub struct MONTH_W<'a> { + w: &'a mut W, +} +impl<'a> MONTH_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 22)) | ((value as u32 & 0x0f) << 22); + self.w + } +} +#[doc = "Field `YEAR` reader - Year"] +pub struct YEAR_R(crate::FieldReader); +impl YEAR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + YEAR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for YEAR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `YEAR` writer - Year"] +pub struct YEAR_W<'a> { + w: &'a mut W, +} +impl<'a> YEAR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 26)) | ((value as u32 & 0x3f) << 26); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Second"] + #[inline(always)] + pub fn second(&self) -> SECOND_R { + SECOND_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:11 - Minute"] + #[inline(always)] + pub fn minute(&self) -> MINUTE_R { + MINUTE_R::new(((self.bits >> 6) & 0x3f) as u8) + } + #[doc = "Bits 12:16 - Hour"] + #[inline(always)] + pub fn hour(&self) -> HOUR_R { + HOUR_R::new(((self.bits >> 12) & 0x1f) as u8) + } + #[doc = "Bits 17:21 - Day"] + #[inline(always)] + pub fn day(&self) -> DAY_R { + DAY_R::new(((self.bits >> 17) & 0x1f) as u8) + } + #[doc = "Bits 22:25 - Month"] + #[inline(always)] + pub fn month(&self) -> MONTH_R { + MONTH_R::new(((self.bits >> 22) & 0x0f) as u8) + } + #[doc = "Bits 26:31 - Year"] + #[inline(always)] + pub fn year(&self) -> YEAR_R { + YEAR_R::new(((self.bits >> 26) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - Second"] + #[inline(always)] + pub fn second(&mut self) -> SECOND_W { + SECOND_W { w: self } + } + #[doc = "Bits 6:11 - Minute"] + #[inline(always)] + pub fn minute(&mut self) -> MINUTE_W { + MINUTE_W { w: self } + } + #[doc = "Bits 12:16 - Hour"] + #[inline(always)] + pub fn hour(&mut self) -> HOUR_W { + HOUR_W { w: self } + } + #[doc = "Bits 17:21 - Day"] + #[inline(always)] + pub fn day(&mut self) -> DAY_W { + DAY_W { w: self } + } + #[doc = "Bits 22:25 - Month"] + #[inline(always)] + pub fn month(&mut self) -> MONTH_W { + MONTH_W { w: self } + } + #[doc = "Bits 26:31 - Year"] + #[inline(always)] + pub fn year(&mut self) -> YEAR_W { + YEAR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2_ALARM Alarm n Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [alarm](index.html) module"] +pub struct ALARM_SPEC; +impl crate::RegisterSpec for ALARM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [alarm::R](R) reader structure"] +impl crate::Readable for ALARM_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [alarm::W](W) writer structure"] +impl crate::Writable for ALARM_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ALARM to value 0"] +impl crate::Resettable for ALARM_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/rtc/mode2/clock.rs b/pac/atsamc20e/src/rtc/mode2/clock.rs new file mode 100644 index 000000000000..3f364ff8e57b --- /dev/null +++ b/pac/atsamc20e/src/rtc/mode2/clock.rs @@ -0,0 +1,337 @@ +#[doc = "Register `CLOCK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CLOCK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SECOND` reader - Second"] +pub struct SECOND_R(crate::FieldReader); +impl SECOND_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SECOND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SECOND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SECOND` writer - Second"] +pub struct SECOND_W<'a> { + w: &'a mut W, +} +impl<'a> SECOND_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +#[doc = "Field `MINUTE` reader - Minute"] +pub struct MINUTE_R(crate::FieldReader); +impl MINUTE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MINUTE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MINUTE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MINUTE` writer - Minute"] +pub struct MINUTE_W<'a> { + w: &'a mut W, +} +impl<'a> MINUTE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 6)) | ((value as u32 & 0x3f) << 6); + self.w + } +} +#[doc = "Hour\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum HOUR_A { + #[doc = "0: AM when CLKREP in 12-hour"] + AM = 0, + #[doc = "16: PM when CLKREP in 12-hour"] + PM = 16, +} +impl From for u8 { + #[inline(always)] + fn from(variant: HOUR_A) -> Self { + variant as _ + } +} +#[doc = "Field `HOUR` reader - Hour"] +pub struct HOUR_R(crate::FieldReader); +impl HOUR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + HOUR_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(HOUR_A::AM), + 16 => Some(HOUR_A::PM), + _ => None, + } + } + #[doc = "Checks if the value of the field is `AM`"] + #[inline(always)] + pub fn is_am(&self) -> bool { + **self == HOUR_A::AM + } + #[doc = "Checks if the value of the field is `PM`"] + #[inline(always)] + pub fn is_pm(&self) -> bool { + **self == HOUR_A::PM + } +} +impl core::ops::Deref for HOUR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HOUR` writer - Hour"] +pub struct HOUR_W<'a> { + w: &'a mut W, +} +impl<'a> HOUR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: HOUR_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "AM when CLKREP in 12-hour"] + #[inline(always)] + pub fn am(self) -> &'a mut W { + self.variant(HOUR_A::AM) + } + #[doc = "PM when CLKREP in 12-hour"] + #[inline(always)] + pub fn pm(self) -> &'a mut W { + self.variant(HOUR_A::PM) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 12)) | ((value as u32 & 0x1f) << 12); + self.w + } +} +#[doc = "Field `DAY` reader - Day"] +pub struct DAY_R(crate::FieldReader); +impl DAY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DAY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DAY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DAY` writer - Day"] +pub struct DAY_W<'a> { + w: &'a mut W, +} +impl<'a> DAY_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 17)) | ((value as u32 & 0x1f) << 17); + self.w + } +} +#[doc = "Field `MONTH` reader - Month"] +pub struct MONTH_R(crate::FieldReader); +impl MONTH_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MONTH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MONTH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MONTH` writer - Month"] +pub struct MONTH_W<'a> { + w: &'a mut W, +} +impl<'a> MONTH_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 22)) | ((value as u32 & 0x0f) << 22); + self.w + } +} +#[doc = "Field `YEAR` reader - Year"] +pub struct YEAR_R(crate::FieldReader); +impl YEAR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + YEAR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for YEAR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `YEAR` writer - Year"] +pub struct YEAR_W<'a> { + w: &'a mut W, +} +impl<'a> YEAR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 26)) | ((value as u32 & 0x3f) << 26); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Second"] + #[inline(always)] + pub fn second(&self) -> SECOND_R { + SECOND_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:11 - Minute"] + #[inline(always)] + pub fn minute(&self) -> MINUTE_R { + MINUTE_R::new(((self.bits >> 6) & 0x3f) as u8) + } + #[doc = "Bits 12:16 - Hour"] + #[inline(always)] + pub fn hour(&self) -> HOUR_R { + HOUR_R::new(((self.bits >> 12) & 0x1f) as u8) + } + #[doc = "Bits 17:21 - Day"] + #[inline(always)] + pub fn day(&self) -> DAY_R { + DAY_R::new(((self.bits >> 17) & 0x1f) as u8) + } + #[doc = "Bits 22:25 - Month"] + #[inline(always)] + pub fn month(&self) -> MONTH_R { + MONTH_R::new(((self.bits >> 22) & 0x0f) as u8) + } + #[doc = "Bits 26:31 - Year"] + #[inline(always)] + pub fn year(&self) -> YEAR_R { + YEAR_R::new(((self.bits >> 26) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - Second"] + #[inline(always)] + pub fn second(&mut self) -> SECOND_W { + SECOND_W { w: self } + } + #[doc = "Bits 6:11 - Minute"] + #[inline(always)] + pub fn minute(&mut self) -> MINUTE_W { + MINUTE_W { w: self } + } + #[doc = "Bits 12:16 - Hour"] + #[inline(always)] + pub fn hour(&mut self) -> HOUR_W { + HOUR_W { w: self } + } + #[doc = "Bits 17:21 - Day"] + #[inline(always)] + pub fn day(&mut self) -> DAY_W { + DAY_W { w: self } + } + #[doc = "Bits 22:25 - Month"] + #[inline(always)] + pub fn month(&mut self) -> MONTH_W { + MONTH_W { w: self } + } + #[doc = "Bits 26:31 - Year"] + #[inline(always)] + pub fn year(&mut self) -> YEAR_W { + YEAR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2 Clock Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clock](index.html) module"] +pub struct CLOCK_SPEC; +impl crate::RegisterSpec for CLOCK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [clock::R](R) reader structure"] +impl crate::Readable for CLOCK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [clock::W](W) writer structure"] +impl crate::Writable for CLOCK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CLOCK to value 0"] +impl crate::Resettable for CLOCK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/rtc/mode2/ctrla.rs b/pac/atsamc20e/src/rtc/mode2/ctrla.rs new file mode 100644 index 000000000000..fc4bfda16bd8 --- /dev/null +++ b/pac/atsamc20e/src/rtc/mode2/ctrla.rs @@ -0,0 +1,616 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: Mode 0: 32-bit Counter"] + COUNT32 = 0, + #[doc = "1: Mode 1: 16-bit Counter"] + COUNT16 = 1, + #[doc = "2: Mode 2: Clock/Calendar"] + CLOCK = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::COUNT32), + 1 => Some(MODE_A::COUNT16), + 2 => Some(MODE_A::CLOCK), + _ => None, + } + } + #[doc = "Checks if the value of the field is `COUNT32`"] + #[inline(always)] + pub fn is_count32(&self) -> bool { + **self == MODE_A::COUNT32 + } + #[doc = "Checks if the value of the field is `COUNT16`"] + #[inline(always)] + pub fn is_count16(&self) -> bool { + **self == MODE_A::COUNT16 + } + #[doc = "Checks if the value of the field is `CLOCK`"] + #[inline(always)] + pub fn is_clock(&self) -> bool { + **self == MODE_A::CLOCK + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Mode 0: 32-bit Counter"] + #[inline(always)] + pub fn count32(self) -> &'a mut W { + self.variant(MODE_A::COUNT32) + } + #[doc = "Mode 1: 16-bit Counter"] + #[inline(always)] + pub fn count16(self) -> &'a mut W { + self.variant(MODE_A::COUNT16) + } + #[doc = "Mode 2: Clock/Calendar"] + #[inline(always)] + pub fn clock(self) -> &'a mut W { + self.variant(MODE_A::CLOCK) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u16 & 0x03) << 2); + self.w + } +} +#[doc = "Field `CLKREP` reader - Clock Representation"] +pub struct CLKREP_R(crate::FieldReader); +impl CLKREP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKREP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKREP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKREP` writer - Clock Representation"] +pub struct CLKREP_W<'a> { + w: &'a mut W, +} +impl<'a> CLKREP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `MATCHCLR` reader - Clear on Match"] +pub struct MATCHCLR_R(crate::FieldReader); +impl MATCHCLR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MATCHCLR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MATCHCLR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MATCHCLR` writer - Clear on Match"] +pub struct MATCHCLR_W<'a> { + w: &'a mut W, +} +impl<'a> MATCHCLR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: CLK_RTC_CNT = GCLK_RTC/1"] + OFF = 0, + #[doc = "1: CLK_RTC_CNT = GCLK_RTC/1"] + DIV1 = 1, + #[doc = "2: CLK_RTC_CNT = GCLK_RTC/2"] + DIV2 = 2, + #[doc = "3: CLK_RTC_CNT = GCLK_RTC/4"] + DIV4 = 3, + #[doc = "4: CLK_RTC_CNT = GCLK_RTC/8"] + DIV8 = 4, + #[doc = "5: CLK_RTC_CNT = GCLK_RTC/16"] + DIV16 = 5, + #[doc = "6: CLK_RTC_CNT = GCLK_RTC/32"] + DIV32 = 6, + #[doc = "7: CLK_RTC_CNT = GCLK_RTC/64"] + DIV64 = 7, + #[doc = "8: CLK_RTC_CNT = GCLK_RTC/128"] + DIV128 = 8, + #[doc = "9: CLK_RTC_CNT = GCLK_RTC/256"] + DIV256 = 9, + #[doc = "10: CLK_RTC_CNT = GCLK_RTC/512"] + DIV512 = 10, + #[doc = "11: CLK_RTC_CNT = GCLK_RTC/1024"] + DIV1024 = 11, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCALER_A::OFF), + 1 => Some(PRESCALER_A::DIV1), + 2 => Some(PRESCALER_A::DIV2), + 3 => Some(PRESCALER_A::DIV4), + 4 => Some(PRESCALER_A::DIV8), + 5 => Some(PRESCALER_A::DIV16), + 6 => Some(PRESCALER_A::DIV32), + 7 => Some(PRESCALER_A::DIV64), + 8 => Some(PRESCALER_A::DIV128), + 9 => Some(PRESCALER_A::DIV256), + 10 => Some(PRESCALER_A::DIV512), + 11 => Some(PRESCALER_A::DIV1024), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == PRESCALER_A::OFF + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == PRESCALER_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == PRESCALER_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == PRESCALER_A::DIV128 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV512`"] + #[inline(always)] + pub fn is_div512(&self) -> bool { + **self == PRESCALER_A::DIV512 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PRESCALER_A::DIV1024 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(PRESCALER_A::OFF) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV32) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV128) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/512"] + #[inline(always)] + pub fn div512(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV512) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 8)) | ((value as u16 & 0x0f) << 8); + self.w + } +} +#[doc = "Field `CLOCKSYNC` reader - Clock Read Synchronization Enable"] +pub struct CLOCKSYNC_R(crate::FieldReader); +impl CLOCKSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLOCKSYNC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLOCKSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLOCKSYNC` writer - Clock Read Synchronization Enable"] +pub struct CLOCKSYNC_W<'a> { + w: &'a mut W, +} +impl<'a> CLOCKSYNC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:3 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bit 6 - Clock Representation"] + #[inline(always)] + pub fn clkrep(&self) -> CLKREP_R { + CLKREP_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Clear on Match"] + #[inline(always)] + pub fn matchclr(&self) -> MATCHCLR_R { + MATCHCLR_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:11 - Prescaler"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 15 - Clock Read Synchronization Enable"] + #[inline(always)] + pub fn clocksync(&self) -> CLOCKSYNC_R { + CLOCKSYNC_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:3 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 6 - Clock Representation"] + #[inline(always)] + pub fn clkrep(&mut self) -> CLKREP_W { + CLKREP_W { w: self } + } + #[doc = "Bit 7 - Clear on Match"] + #[inline(always)] + pub fn matchclr(&mut self) -> MATCHCLR_W { + MATCHCLR_W { w: self } + } + #[doc = "Bits 8:11 - Prescaler"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Bit 15 - Clock Read Synchronization Enable"] + #[inline(always)] + pub fn clocksync(&mut self) -> CLOCKSYNC_W { + CLOCKSYNC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2 Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/rtc/mode2/dbgctrl.rs b/pac/atsamc20e/src/rtc/mode2/dbgctrl.rs new file mode 100644 index 000000000000..0383e70d0429 --- /dev/null +++ b/pac/atsamc20e/src/rtc/mode2/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Run During Debug"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Run During Debug"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/rtc/mode2/evctrl.rs b/pac/atsamc20e/src/rtc/mode2/evctrl.rs new file mode 100644 index 000000000000..17bc3da4a79e --- /dev/null +++ b/pac/atsamc20e/src/rtc/mode2/evctrl.rs @@ -0,0 +1,536 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PEREO0` reader - Periodic Interval 0 Event Output Enable"] +pub struct PEREO0_R(crate::FieldReader); +impl PEREO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO0` writer - Periodic Interval 0 Event Output Enable"] +pub struct PEREO0_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `PEREO1` reader - Periodic Interval 1 Event Output Enable"] +pub struct PEREO1_R(crate::FieldReader); +impl PEREO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO1` writer - Periodic Interval 1 Event Output Enable"] +pub struct PEREO1_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PEREO2` reader - Periodic Interval 2 Event Output Enable"] +pub struct PEREO2_R(crate::FieldReader); +impl PEREO2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO2` writer - Periodic Interval 2 Event Output Enable"] +pub struct PEREO2_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PEREO3` reader - Periodic Interval 3 Event Output Enable"] +pub struct PEREO3_R(crate::FieldReader); +impl PEREO3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO3` writer - Periodic Interval 3 Event Output Enable"] +pub struct PEREO3_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PEREO4` reader - Periodic Interval 4 Event Output Enable"] +pub struct PEREO4_R(crate::FieldReader); +impl PEREO4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO4` writer - Periodic Interval 4 Event Output Enable"] +pub struct PEREO4_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PEREO5` reader - Periodic Interval 5 Event Output Enable"] +pub struct PEREO5_R(crate::FieldReader); +impl PEREO5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO5` writer - Periodic Interval 5 Event Output Enable"] +pub struct PEREO5_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PEREO6` reader - Periodic Interval 6 Event Output Enable"] +pub struct PEREO6_R(crate::FieldReader); +impl PEREO6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO6` writer - Periodic Interval 6 Event Output Enable"] +pub struct PEREO6_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PEREO7` reader - Periodic Interval 7 Event Output Enable"] +pub struct PEREO7_R(crate::FieldReader); +impl PEREO7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO7` writer - Periodic Interval 7 Event Output Enable"] +pub struct PEREO7_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `ALARMEO0` reader - Alarm 0 Event Output Enable"] +pub struct ALARMEO0_R(crate::FieldReader); +impl ALARMEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALARMEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALARMEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALARMEO0` writer - Alarm 0 Event Output Enable"] +pub struct ALARMEO0_W<'a> { + w: &'a mut W, +} +impl<'a> ALARMEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `OVFEO` reader - Overflow Event Output Enable"] +pub struct OVFEO_R(crate::FieldReader); +impl OVFEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVFEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVFEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVFEO` writer - Overflow Event Output Enable"] +pub struct OVFEO_W<'a> { + w: &'a mut W, +} +impl<'a> OVFEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Event Output Enable"] + #[inline(always)] + pub fn pereo0(&self) -> PEREO0_R { + PEREO0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Event Output Enable"] + #[inline(always)] + pub fn pereo1(&self) -> PEREO1_R { + PEREO1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Event Output Enable"] + #[inline(always)] + pub fn pereo2(&self) -> PEREO2_R { + PEREO2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Event Output Enable"] + #[inline(always)] + pub fn pereo3(&self) -> PEREO3_R { + PEREO3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Event Output Enable"] + #[inline(always)] + pub fn pereo4(&self) -> PEREO4_R { + PEREO4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Event Output Enable"] + #[inline(always)] + pub fn pereo5(&self) -> PEREO5_R { + PEREO5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Event Output Enable"] + #[inline(always)] + pub fn pereo6(&self) -> PEREO6_R { + PEREO6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Event Output Enable"] + #[inline(always)] + pub fn pereo7(&self) -> PEREO7_R { + PEREO7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Alarm 0 Event Output Enable"] + #[inline(always)] + pub fn alarmeo0(&self) -> ALARMEO0_R { + ALARMEO0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&self) -> OVFEO_R { + OVFEO_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Event Output Enable"] + #[inline(always)] + pub fn pereo0(&mut self) -> PEREO0_W { + PEREO0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1 Event Output Enable"] + #[inline(always)] + pub fn pereo1(&mut self) -> PEREO1_W { + PEREO1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2 Event Output Enable"] + #[inline(always)] + pub fn pereo2(&mut self) -> PEREO2_W { + PEREO2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3 Event Output Enable"] + #[inline(always)] + pub fn pereo3(&mut self) -> PEREO3_W { + PEREO3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4 Event Output Enable"] + #[inline(always)] + pub fn pereo4(&mut self) -> PEREO4_W { + PEREO4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5 Event Output Enable"] + #[inline(always)] + pub fn pereo5(&mut self) -> PEREO5_W { + PEREO5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6 Event Output Enable"] + #[inline(always)] + pub fn pereo6(&mut self) -> PEREO6_W { + PEREO6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7 Event Output Enable"] + #[inline(always)] + pub fn pereo7(&mut self) -> PEREO7_W { + PEREO7_W { w: self } + } + #[doc = "Bit 8 - Alarm 0 Event Output Enable"] + #[inline(always)] + pub fn alarmeo0(&mut self) -> ALARMEO0_W { + ALARMEO0_W { w: self } + } + #[doc = "Bit 15 - Overflow Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&mut self) -> OVFEO_W { + OVFEO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2 Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/rtc/mode2/freqcorr.rs b/pac/atsamc20e/src/rtc/mode2/freqcorr.rs new file mode 100644 index 000000000000..043ba6f88eb2 --- /dev/null +++ b/pac/atsamc20e/src/rtc/mode2/freqcorr.rs @@ -0,0 +1,150 @@ +#[doc = "Register `FREQCORR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FREQCORR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `VALUE` reader - Correction Value"] +pub struct VALUE_R(crate::FieldReader); +impl VALUE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + VALUE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VALUE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VALUE` writer - Correction Value"] +pub struct VALUE_W<'a> { + w: &'a mut W, +} +impl<'a> VALUE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x7f) | (value as u8 & 0x7f); + self.w + } +} +#[doc = "Field `SIGN` reader - Correction Sign"] +pub struct SIGN_R(crate::FieldReader); +impl SIGN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SIGN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SIGN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SIGN` writer - Correction Sign"] +pub struct SIGN_W<'a> { + w: &'a mut W, +} +impl<'a> SIGN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bits 0:6 - Correction Value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bit 7 - Correction Sign"] + #[inline(always)] + pub fn sign(&self) -> SIGN_R { + SIGN_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:6 - Correction Value"] + #[inline(always)] + pub fn value(&mut self) -> VALUE_W { + VALUE_W { w: self } + } + #[doc = "Bit 7 - Correction Sign"] + #[inline(always)] + pub fn sign(&mut self) -> SIGN_W { + SIGN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Frequency Correction\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [freqcorr](index.html) module"] +pub struct FREQCORR_SPEC; +impl crate::RegisterSpec for FREQCORR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [freqcorr::R](R) reader structure"] +impl crate::Readable for FREQCORR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [freqcorr::W](W) writer structure"] +impl crate::Writable for FREQCORR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets FREQCORR to value 0"] +impl crate::Resettable for FREQCORR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/rtc/mode2/intenclr.rs b/pac/atsamc20e/src/rtc/mode2/intenclr.rs new file mode 100644 index 000000000000..84aa17f78a0e --- /dev/null +++ b/pac/atsamc20e/src/rtc/mode2/intenclr.rs @@ -0,0 +1,536 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER0` reader - Periodic Interval 0 Interrupt Enable"] +pub struct PER0_R(crate::FieldReader); +impl PER0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER0` writer - Periodic Interval 0 Interrupt Enable"] +pub struct PER0_W<'a> { + w: &'a mut W, +} +impl<'a> PER0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PER1` reader - Periodic Interval 1 Interrupt Enable"] +pub struct PER1_R(crate::FieldReader); +impl PER1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER1` writer - Periodic Interval 1 Interrupt Enable"] +pub struct PER1_W<'a> { + w: &'a mut W, +} +impl<'a> PER1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PER2` reader - Periodic Interval 2 Interrupt Enable"] +pub struct PER2_R(crate::FieldReader); +impl PER2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER2` writer - Periodic Interval 2 Interrupt Enable"] +pub struct PER2_W<'a> { + w: &'a mut W, +} +impl<'a> PER2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PER3` reader - Periodic Interval 3 Interrupt Enable"] +pub struct PER3_R(crate::FieldReader); +impl PER3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER3` writer - Periodic Interval 3 Interrupt Enable"] +pub struct PER3_W<'a> { + w: &'a mut W, +} +impl<'a> PER3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PER4` reader - Periodic Interval 4 Interrupt Enable"] +pub struct PER4_R(crate::FieldReader); +impl PER4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER4` writer - Periodic Interval 4 Interrupt Enable"] +pub struct PER4_W<'a> { + w: &'a mut W, +} +impl<'a> PER4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PER5` reader - Periodic Interval 5 Interrupt Enable"] +pub struct PER5_R(crate::FieldReader); +impl PER5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER5` writer - Periodic Interval 5 Interrupt Enable"] +pub struct PER5_W<'a> { + w: &'a mut W, +} +impl<'a> PER5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PER6` reader - Periodic Interval 6 Interrupt Enable"] +pub struct PER6_R(crate::FieldReader); +impl PER6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER6` writer - Periodic Interval 6 Interrupt Enable"] +pub struct PER6_W<'a> { + w: &'a mut W, +} +impl<'a> PER6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PER7` reader - Periodic Interval 7 Interrupt Enable"] +pub struct PER7_R(crate::FieldReader); +impl PER7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER7` writer - Periodic Interval 7 Interrupt Enable"] +pub struct PER7_W<'a> { + w: &'a mut W, +} +impl<'a> PER7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `ALARM0` reader - Alarm 0 Interrupt Enable"] +pub struct ALARM0_R(crate::FieldReader); +impl ALARM0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALARM0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALARM0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALARM0` writer - Alarm 0 Interrupt Enable"] +pub struct ALARM0_W<'a> { + w: &'a mut W, +} +impl<'a> ALARM0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + pub fn per0(&self) -> PER0_R { + PER0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + pub fn per1(&self) -> PER1_R { + PER1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + pub fn per2(&self) -> PER2_R { + PER2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + pub fn per3(&self) -> PER3_R { + PER3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + pub fn per4(&self) -> PER4_R { + PER4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + pub fn per5(&self) -> PER5_R { + PER5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + pub fn per6(&self) -> PER6_R { + PER6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + pub fn per7(&self) -> PER7_R { + PER7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Alarm 0 Interrupt Enable"] + #[inline(always)] + pub fn alarm0(&self) -> ALARM0_R { + ALARM0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + pub fn per0(&mut self) -> PER0_W { + PER0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + pub fn per1(&mut self) -> PER1_W { + PER1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + pub fn per2(&mut self) -> PER2_W { + PER2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + pub fn per3(&mut self) -> PER3_W { + PER3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + pub fn per4(&mut self) -> PER4_W { + PER4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + pub fn per5(&mut self) -> PER5_W { + PER5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + pub fn per6(&mut self) -> PER6_W { + PER6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + pub fn per7(&mut self) -> PER7_W { + PER7_W { w: self } + } + #[doc = "Bit 8 - Alarm 0 Interrupt Enable"] + #[inline(always)] + pub fn alarm0(&mut self) -> ALARM0_W { + ALARM0_W { w: self } + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2 Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/rtc/mode2/intenset.rs b/pac/atsamc20e/src/rtc/mode2/intenset.rs new file mode 100644 index 000000000000..a41687fa1ee5 --- /dev/null +++ b/pac/atsamc20e/src/rtc/mode2/intenset.rs @@ -0,0 +1,536 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER0` reader - Periodic Interval 0 Enable"] +pub struct PER0_R(crate::FieldReader); +impl PER0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER0` writer - Periodic Interval 0 Enable"] +pub struct PER0_W<'a> { + w: &'a mut W, +} +impl<'a> PER0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PER1` reader - Periodic Interval 1 Enable"] +pub struct PER1_R(crate::FieldReader); +impl PER1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER1` writer - Periodic Interval 1 Enable"] +pub struct PER1_W<'a> { + w: &'a mut W, +} +impl<'a> PER1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PER2` reader - Periodic Interval 2 Enable"] +pub struct PER2_R(crate::FieldReader); +impl PER2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER2` writer - Periodic Interval 2 Enable"] +pub struct PER2_W<'a> { + w: &'a mut W, +} +impl<'a> PER2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PER3` reader - Periodic Interval 3 Enable"] +pub struct PER3_R(crate::FieldReader); +impl PER3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER3` writer - Periodic Interval 3 Enable"] +pub struct PER3_W<'a> { + w: &'a mut W, +} +impl<'a> PER3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PER4` reader - Periodic Interval 4 Enable"] +pub struct PER4_R(crate::FieldReader); +impl PER4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER4` writer - Periodic Interval 4 Enable"] +pub struct PER4_W<'a> { + w: &'a mut W, +} +impl<'a> PER4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PER5` reader - Periodic Interval 5 Enable"] +pub struct PER5_R(crate::FieldReader); +impl PER5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER5` writer - Periodic Interval 5 Enable"] +pub struct PER5_W<'a> { + w: &'a mut W, +} +impl<'a> PER5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PER6` reader - Periodic Interval 6 Enable"] +pub struct PER6_R(crate::FieldReader); +impl PER6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER6` writer - Periodic Interval 6 Enable"] +pub struct PER6_W<'a> { + w: &'a mut W, +} +impl<'a> PER6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PER7` reader - Periodic Interval 7 Enable"] +pub struct PER7_R(crate::FieldReader); +impl PER7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER7` writer - Periodic Interval 7 Enable"] +pub struct PER7_W<'a> { + w: &'a mut W, +} +impl<'a> PER7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `ALARM0` reader - Alarm 0 Interrupt Enable"] +pub struct ALARM0_R(crate::FieldReader); +impl ALARM0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALARM0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALARM0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALARM0` writer - Alarm 0 Interrupt Enable"] +pub struct ALARM0_W<'a> { + w: &'a mut W, +} +impl<'a> ALARM0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Enable"] + #[inline(always)] + pub fn per0(&self) -> PER0_R { + PER0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Enable"] + #[inline(always)] + pub fn per1(&self) -> PER1_R { + PER1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Enable"] + #[inline(always)] + pub fn per2(&self) -> PER2_R { + PER2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Enable"] + #[inline(always)] + pub fn per3(&self) -> PER3_R { + PER3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Enable"] + #[inline(always)] + pub fn per4(&self) -> PER4_R { + PER4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Enable"] + #[inline(always)] + pub fn per5(&self) -> PER5_R { + PER5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Enable"] + #[inline(always)] + pub fn per6(&self) -> PER6_R { + PER6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Enable"] + #[inline(always)] + pub fn per7(&self) -> PER7_R { + PER7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Alarm 0 Interrupt Enable"] + #[inline(always)] + pub fn alarm0(&self) -> ALARM0_R { + ALARM0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Enable"] + #[inline(always)] + pub fn per0(&mut self) -> PER0_W { + PER0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1 Enable"] + #[inline(always)] + pub fn per1(&mut self) -> PER1_W { + PER1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2 Enable"] + #[inline(always)] + pub fn per2(&mut self) -> PER2_W { + PER2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3 Enable"] + #[inline(always)] + pub fn per3(&mut self) -> PER3_W { + PER3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4 Enable"] + #[inline(always)] + pub fn per4(&mut self) -> PER4_W { + PER4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5 Enable"] + #[inline(always)] + pub fn per5(&mut self) -> PER5_W { + PER5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6 Enable"] + #[inline(always)] + pub fn per6(&mut self) -> PER6_W { + PER6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7 Enable"] + #[inline(always)] + pub fn per7(&mut self) -> PER7_W { + PER7_W { w: self } + } + #[doc = "Bit 8 - Alarm 0 Interrupt Enable"] + #[inline(always)] + pub fn alarm0(&mut self) -> ALARM0_W { + ALARM0_W { w: self } + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2 Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/rtc/mode2/intflag.rs b/pac/atsamc20e/src/rtc/mode2/intflag.rs new file mode 100644 index 000000000000..8de0f3efd1d0 --- /dev/null +++ b/pac/atsamc20e/src/rtc/mode2/intflag.rs @@ -0,0 +1,536 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER0` reader - Periodic Interval 0"] +pub struct PER0_R(crate::FieldReader); +impl PER0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER0` writer - Periodic Interval 0"] +pub struct PER0_W<'a> { + w: &'a mut W, +} +impl<'a> PER0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PER1` reader - Periodic Interval 1"] +pub struct PER1_R(crate::FieldReader); +impl PER1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER1` writer - Periodic Interval 1"] +pub struct PER1_W<'a> { + w: &'a mut W, +} +impl<'a> PER1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PER2` reader - Periodic Interval 2"] +pub struct PER2_R(crate::FieldReader); +impl PER2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER2` writer - Periodic Interval 2"] +pub struct PER2_W<'a> { + w: &'a mut W, +} +impl<'a> PER2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PER3` reader - Periodic Interval 3"] +pub struct PER3_R(crate::FieldReader); +impl PER3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER3` writer - Periodic Interval 3"] +pub struct PER3_W<'a> { + w: &'a mut W, +} +impl<'a> PER3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PER4` reader - Periodic Interval 4"] +pub struct PER4_R(crate::FieldReader); +impl PER4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER4` writer - Periodic Interval 4"] +pub struct PER4_W<'a> { + w: &'a mut W, +} +impl<'a> PER4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PER5` reader - Periodic Interval 5"] +pub struct PER5_R(crate::FieldReader); +impl PER5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER5` writer - Periodic Interval 5"] +pub struct PER5_W<'a> { + w: &'a mut W, +} +impl<'a> PER5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PER6` reader - Periodic Interval 6"] +pub struct PER6_R(crate::FieldReader); +impl PER6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER6` writer - Periodic Interval 6"] +pub struct PER6_W<'a> { + w: &'a mut W, +} +impl<'a> PER6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PER7` reader - Periodic Interval 7"] +pub struct PER7_R(crate::FieldReader); +impl PER7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER7` writer - Periodic Interval 7"] +pub struct PER7_W<'a> { + w: &'a mut W, +} +impl<'a> PER7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `ALARM0` reader - Alarm 0"] +pub struct ALARM0_R(crate::FieldReader); +impl ALARM0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALARM0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALARM0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALARM0` writer - Alarm 0"] +pub struct ALARM0_W<'a> { + w: &'a mut W, +} +impl<'a> ALARM0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0"] + #[inline(always)] + pub fn per0(&self) -> PER0_R { + PER0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1"] + #[inline(always)] + pub fn per1(&self) -> PER1_R { + PER1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2"] + #[inline(always)] + pub fn per2(&self) -> PER2_R { + PER2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3"] + #[inline(always)] + pub fn per3(&self) -> PER3_R { + PER3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4"] + #[inline(always)] + pub fn per4(&self) -> PER4_R { + PER4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5"] + #[inline(always)] + pub fn per5(&self) -> PER5_R { + PER5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6"] + #[inline(always)] + pub fn per6(&self) -> PER6_R { + PER6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7"] + #[inline(always)] + pub fn per7(&self) -> PER7_R { + PER7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Alarm 0"] + #[inline(always)] + pub fn alarm0(&self) -> ALARM0_R { + ALARM0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0"] + #[inline(always)] + pub fn per0(&mut self) -> PER0_W { + PER0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1"] + #[inline(always)] + pub fn per1(&mut self) -> PER1_W { + PER1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2"] + #[inline(always)] + pub fn per2(&mut self) -> PER2_W { + PER2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3"] + #[inline(always)] + pub fn per3(&mut self) -> PER3_W { + PER3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4"] + #[inline(always)] + pub fn per4(&mut self) -> PER4_W { + PER4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5"] + #[inline(always)] + pub fn per5(&mut self) -> PER5_W { + PER5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6"] + #[inline(always)] + pub fn per6(&mut self) -> PER6_W { + PER6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7"] + #[inline(always)] + pub fn per7(&mut self) -> PER7_W { + PER7_W { w: self } + } + #[doc = "Bit 8 - Alarm 0"] + #[inline(always)] + pub fn alarm0(&mut self) -> ALARM0_W { + ALARM0_W { w: self } + } + #[doc = "Bit 15 - Overflow"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2 Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/rtc/mode2/mask.rs b/pac/atsamc20e/src/rtc/mode2/mask.rs new file mode 100644 index 000000000000..53e0bb491a62 --- /dev/null +++ b/pac/atsamc20e/src/rtc/mode2/mask.rs @@ -0,0 +1,217 @@ +#[doc = "Register `MASK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MASK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Alarm Mask Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SEL_A { + #[doc = "0: Alarm Disabled"] + OFF = 0, + #[doc = "1: Match seconds only"] + SS = 1, + #[doc = "2: Match seconds and minutes only"] + MMSS = 2, + #[doc = "3: Match seconds, minutes, and hours only"] + HHMMSS = 3, + #[doc = "4: Match seconds, minutes, hours, and days only"] + DDHHMMSS = 4, + #[doc = "5: Match seconds, minutes, hours, days, and months only"] + MMDDHHMMSS = 5, + #[doc = "6: Match seconds, minutes, hours, days, months, and years"] + YYMMDDHHMMSS = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `SEL` reader - Alarm Mask Selection"] +pub struct SEL_R(crate::FieldReader); +impl SEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEL_A::OFF), + 1 => Some(SEL_A::SS), + 2 => Some(SEL_A::MMSS), + 3 => Some(SEL_A::HHMMSS), + 4 => Some(SEL_A::DDHHMMSS), + 5 => Some(SEL_A::MMDDHHMMSS), + 6 => Some(SEL_A::YYMMDDHHMMSS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == SEL_A::OFF + } + #[doc = "Checks if the value of the field is `SS`"] + #[inline(always)] + pub fn is_ss(&self) -> bool { + **self == SEL_A::SS + } + #[doc = "Checks if the value of the field is `MMSS`"] + #[inline(always)] + pub fn is_mmss(&self) -> bool { + **self == SEL_A::MMSS + } + #[doc = "Checks if the value of the field is `HHMMSS`"] + #[inline(always)] + pub fn is_hhmmss(&self) -> bool { + **self == SEL_A::HHMMSS + } + #[doc = "Checks if the value of the field is `DDHHMMSS`"] + #[inline(always)] + pub fn is_ddhhmmss(&self) -> bool { + **self == SEL_A::DDHHMMSS + } + #[doc = "Checks if the value of the field is `MMDDHHMMSS`"] + #[inline(always)] + pub fn is_mmddhhmmss(&self) -> bool { + **self == SEL_A::MMDDHHMMSS + } + #[doc = "Checks if the value of the field is `YYMMDDHHMMSS`"] + #[inline(always)] + pub fn is_yymmddhhmmss(&self) -> bool { + **self == SEL_A::YYMMDDHHMMSS + } +} +impl core::ops::Deref for SEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEL` writer - Alarm Mask Selection"] +pub struct SEL_W<'a> { + w: &'a mut W, +} +impl<'a> SEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SEL_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Alarm Disabled"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(SEL_A::OFF) + } + #[doc = "Match seconds only"] + #[inline(always)] + pub fn ss(self) -> &'a mut W { + self.variant(SEL_A::SS) + } + #[doc = "Match seconds and minutes only"] + #[inline(always)] + pub fn mmss(self) -> &'a mut W { + self.variant(SEL_A::MMSS) + } + #[doc = "Match seconds, minutes, and hours only"] + #[inline(always)] + pub fn hhmmss(self) -> &'a mut W { + self.variant(SEL_A::HHMMSS) + } + #[doc = "Match seconds, minutes, hours, and days only"] + #[inline(always)] + pub fn ddhhmmss(self) -> &'a mut W { + self.variant(SEL_A::DDHHMMSS) + } + #[doc = "Match seconds, minutes, hours, days, and months only"] + #[inline(always)] + pub fn mmddhhmmss(self) -> &'a mut W { + self.variant(SEL_A::MMDDHHMMSS) + } + #[doc = "Match seconds, minutes, hours, days, months, and years"] + #[inline(always)] + pub fn yymmddhhmmss(self) -> &'a mut W { + self.variant(SEL_A::YYMMDDHHMMSS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Alarm Mask Selection"] + #[inline(always)] + pub fn sel(&self) -> SEL_R { + SEL_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Alarm Mask Selection"] + #[inline(always)] + pub fn sel(&mut self) -> SEL_W { + SEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2_ALARM Alarm n Mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mask](index.html) module"] +pub struct MASK_SPEC; +impl crate::RegisterSpec for MASK_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [mask::R](R) reader structure"] +impl crate::Readable for MASK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [mask::W](W) writer structure"] +impl crate::Writable for MASK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets MASK to value 0"] +impl crate::Resettable for MASK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/rtc/mode2/syncbusy.rs b/pac/atsamc20e/src/rtc/mode2/syncbusy.rs new file mode 100644 index 000000000000..b517ee5ae8b2 --- /dev/null +++ b/pac/atsamc20e/src/rtc/mode2/syncbusy.rs @@ -0,0 +1,173 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Bit Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - Enable Bit Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FREQCORR` reader - FREQCORR Register Busy"] +pub struct FREQCORR_R(crate::FieldReader); +impl FREQCORR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FREQCORR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FREQCORR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLOCK` reader - CLOCK Register Busy"] +pub struct CLOCK_R(crate::FieldReader); +impl CLOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALARM0` reader - ALARM 0 Register Busy"] +pub struct ALARM0_R(crate::FieldReader); +impl ALARM0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALARM0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALARM0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MASK0` reader - MASK 0 Register Busy"] +pub struct MASK0_R(crate::FieldReader); +impl MASK0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MASK0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MASK0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLOCKSYNC` reader - Clock Read Synchronization Enable Bit Busy"] +pub struct CLOCKSYNC_R(crate::FieldReader); +impl CLOCKSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLOCKSYNC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLOCKSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Bit Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable Bit Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - FREQCORR Register Busy"] + #[inline(always)] + pub fn freqcorr(&self) -> FREQCORR_R { + FREQCORR_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - CLOCK Register Busy"] + #[inline(always)] + pub fn clock(&self) -> CLOCK_R { + CLOCK_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 5 - ALARM 0 Register Busy"] + #[inline(always)] + pub fn alarm0(&self) -> ALARM0_R { + ALARM0_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 11 - MASK 0 Register Busy"] + #[inline(always)] + pub fn mask0(&self) -> MASK0_R { + MASK0_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 15 - Clock Read Synchronization Enable Bit Busy"] + #[inline(always)] + pub fn clocksync(&self) -> CLOCKSYNC_R { + CLOCKSYNC_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +#[doc = "MODE2 Synchronization Busy Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/sercom0.rs b/pac/atsamc20e/src/sercom0.rs new file mode 100644 index 000000000000..da7b62f750c6 --- /dev/null +++ b/pac/atsamc20e/src/sercom0.rs @@ -0,0 +1,327 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved_0_i2cm: [u8; 0x31], +} +impl RegisterBlock { + #[doc = "0x00..0x31 - USART INTERNAL CLOCK Mode"] + #[inline(always)] + pub fn usart_int(&self) -> &USART_INT { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const USART_INT) } + } + #[doc = "0x00..0x31 - USART EXTERNAL CLOCK Mode"] + #[inline(always)] + pub fn usart_ext(&self) -> &USART_EXT { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const USART_EXT) } + } + #[doc = "0x00..0x31 - SPI Master Mode"] + #[inline(always)] + pub fn spim(&self) -> &SPIM { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const SPIM) } + } + #[doc = "0x00..0x31 - SPI Slave Mode"] + #[inline(always)] + pub fn spis(&self) -> &SPIS { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const SPIS) } + } + #[doc = "0x00..0x29 - I2C Slave Mode"] + #[inline(always)] + pub fn i2cs(&self) -> &I2CS { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const I2CS) } + } + #[doc = "0x00..0x31 - I2C Master Mode"] + #[inline(always)] + pub fn i2cm(&self) -> &I2CM { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const I2CM) } + } +} +#[doc = r"Register block"] +#[repr(C)] +pub struct I2CM { + #[doc = "0x00 - I2CM Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - I2CM Control B"] + pub ctrlb: crate::Reg, + _reserved2: [u8; 0x04], + #[doc = "0x0c - I2CM Baud Rate"] + pub baud: crate::Reg, + _reserved3: [u8; 0x04], + #[doc = "0x14 - I2CM Interrupt Enable Clear"] + pub intenclr: crate::Reg, + _reserved4: [u8; 0x01], + #[doc = "0x16 - I2CM Interrupt Enable Set"] + pub intenset: crate::Reg, + _reserved5: [u8; 0x01], + #[doc = "0x18 - I2CM Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x1a - I2CM Status"] + pub status: crate::Reg, + #[doc = "0x1c - I2CM Synchronization Busy"] + pub syncbusy: crate::Reg, + _reserved8: [u8; 0x04], + #[doc = "0x24 - I2CM Address"] + pub addr: crate::Reg, + #[doc = "0x28 - I2CM Data"] + pub data: crate::Reg, + _reserved10: [u8; 0x07], + #[doc = "0x30 - I2CM Debug Control"] + pub dbgctrl: crate::Reg, +} +#[doc = r"Register block"] +#[doc = "I2C Master Mode"] +pub mod i2cm; +#[doc = r"Register block"] +#[repr(C)] +pub struct I2CS { + #[doc = "0x00 - I2CS Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - I2CS Control B"] + pub ctrlb: crate::Reg, + _reserved2: [u8; 0x0c], + #[doc = "0x14 - I2CS Interrupt Enable Clear"] + pub intenclr: crate::Reg, + _reserved3: [u8; 0x01], + #[doc = "0x16 - I2CS Interrupt Enable Set"] + pub intenset: crate::Reg, + _reserved4: [u8; 0x01], + #[doc = "0x18 - I2CS Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved5: [u8; 0x01], + #[doc = "0x1a - I2CS Status"] + pub status: crate::Reg, + #[doc = "0x1c - I2CS Synchronization Busy"] + pub syncbusy: crate::Reg, + _reserved7: [u8; 0x04], + #[doc = "0x24 - I2CS Address"] + pub addr: crate::Reg, + #[doc = "0x28 - I2CS Data"] + pub data: crate::Reg, +} +#[doc = r"Register block"] +#[doc = "I2C Slave Mode"] +pub mod i2cs; +#[doc = r"Register block"] +#[repr(C)] +pub struct SPIS { + #[doc = "0x00 - SPIS Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - SPIS Control B"] + pub ctrlb: crate::Reg, + _reserved2: [u8; 0x04], + #[doc = "0x0c - SPIS Baud Rate"] + pub baud: crate::Reg, + _reserved3: [u8; 0x07], + #[doc = "0x14 - SPIS Interrupt Enable Clear"] + pub intenclr: crate::Reg, + _reserved4: [u8; 0x01], + #[doc = "0x16 - SPIS Interrupt Enable Set"] + pub intenset: crate::Reg, + _reserved5: [u8; 0x01], + #[doc = "0x18 - SPIS Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x1a - SPIS Status"] + pub status: crate::Reg, + #[doc = "0x1c - SPIS Synchronization Busy"] + pub syncbusy: crate::Reg, + _reserved8: [u8; 0x04], + #[doc = "0x24 - SPIS Address"] + pub addr: crate::Reg, + #[doc = "0x28 - SPIS Data"] + pub data: crate::Reg, + _reserved10: [u8; 0x04], + #[doc = "0x30 - SPIS Debug Control"] + pub dbgctrl: crate::Reg, +} +#[doc = r"Register block"] +#[doc = "SPI Slave Mode"] +pub mod spis; +#[doc = r"Register block"] +#[repr(C)] +pub struct SPIM { + #[doc = "0x00 - SPIM Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - SPIM Control B"] + pub ctrlb: crate::Reg, + _reserved2: [u8; 0x04], + #[doc = "0x0c - SPIM Baud Rate"] + pub baud: crate::Reg, + _reserved3: [u8; 0x07], + #[doc = "0x14 - SPIM Interrupt Enable Clear"] + pub intenclr: crate::Reg, + _reserved4: [u8; 0x01], + #[doc = "0x16 - SPIM Interrupt Enable Set"] + pub intenset: crate::Reg, + _reserved5: [u8; 0x01], + #[doc = "0x18 - SPIM Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x1a - SPIM Status"] + pub status: crate::Reg, + #[doc = "0x1c - SPIM Synchronization Busy"] + pub syncbusy: crate::Reg, + _reserved8: [u8; 0x04], + #[doc = "0x24 - SPIM Address"] + pub addr: crate::Reg, + #[doc = "0x28 - SPIM Data"] + pub data: crate::Reg, + _reserved10: [u8; 0x04], + #[doc = "0x30 - SPIM Debug Control"] + pub dbgctrl: crate::Reg, +} +#[doc = r"Register block"] +#[doc = "SPI Master Mode"] +pub mod spim; +#[doc = r"Register block"] +#[repr(C)] +pub struct USART_EXT { + #[doc = "0x00 - USART_EXT Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - USART_EXT Control B"] + pub ctrlb: crate::Reg, + #[doc = "0x08 - USART_EXT Control C"] + pub ctrlc: crate::Reg, + _reserved_3_baud: [u8; 0x02], + #[doc = "0x0e - USART_EXT Receive Pulse Length"] + pub rxpl: crate::Reg, + _reserved5: [u8; 0x05], + #[doc = "0x14 - USART_EXT Interrupt Enable Clear"] + pub intenclr: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x16 - USART_EXT Interrupt Enable Set"] + pub intenset: crate::Reg, + _reserved7: [u8; 0x01], + #[doc = "0x18 - USART_EXT Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved8: [u8; 0x01], + #[doc = "0x1a - USART_EXT Status"] + pub status: crate::Reg, + #[doc = "0x1c - USART_EXT Synchronization Busy"] + pub syncbusy: crate::Reg, + _reserved10: [u8; 0x08], + #[doc = "0x28 - USART_EXT Data"] + pub data: crate::Reg, + _reserved11: [u8; 0x06], + #[doc = "0x30 - USART_EXT Debug Control"] + pub dbgctrl: crate::Reg, +} +impl USART_EXT { + #[doc = "0x0c - USART_EXT Baud Rate"] + #[inline(always)] + pub fn baud_usartfp_mode( + &self, + ) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } + #[doc = "0x0c - USART_EXT Baud Rate"] + #[inline(always)] + pub fn baud_fracfp_mode( + &self, + ) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } + #[doc = "0x0c - USART_EXT Baud Rate"] + #[inline(always)] + pub fn baud_frac_mode( + &self, + ) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } + #[doc = "0x0c - USART_EXT Baud Rate"] + #[inline(always)] + pub fn baud(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } +} +#[doc = r"Register block"] +#[doc = "USART EXTERNAL CLOCK Mode"] +pub mod usart_ext; +#[doc = r"Register block"] +#[repr(C)] +pub struct USART_INT { + #[doc = "0x00 - USART_INT Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - USART_INT Control B"] + pub ctrlb: crate::Reg, + #[doc = "0x08 - USART_INT Control C"] + pub ctrlc: crate::Reg, + _reserved_3_baud: [u8; 0x02], + #[doc = "0x0e - USART_INT Receive Pulse Length"] + pub rxpl: crate::Reg, + _reserved5: [u8; 0x05], + #[doc = "0x14 - USART_INT Interrupt Enable Clear"] + pub intenclr: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x16 - USART_INT Interrupt Enable Set"] + pub intenset: crate::Reg, + _reserved7: [u8; 0x01], + #[doc = "0x18 - USART_INT Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved8: [u8; 0x01], + #[doc = "0x1a - USART_INT Status"] + pub status: crate::Reg, + #[doc = "0x1c - USART_INT Synchronization Busy"] + pub syncbusy: crate::Reg, + _reserved10: [u8; 0x08], + #[doc = "0x28 - USART_INT Data"] + pub data: crate::Reg, + _reserved11: [u8; 0x06], + #[doc = "0x30 - USART_INT Debug Control"] + pub dbgctrl: crate::Reg, +} +impl USART_INT { + #[doc = "0x0c - USART_INT Baud Rate"] + #[inline(always)] + pub fn baud_usartfp_mode( + &self, + ) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } + #[doc = "0x0c - USART_INT Baud Rate"] + #[inline(always)] + pub fn baud_fracfp_mode( + &self, + ) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } + #[doc = "0x0c - USART_INT Baud Rate"] + #[inline(always)] + pub fn baud_frac_mode( + &self, + ) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } + #[doc = "0x0c - USART_INT Baud Rate"] + #[inline(always)] + pub fn baud(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } +} +#[doc = r"Register block"] +#[doc = "USART INTERNAL CLOCK Mode"] +pub mod usart_int; diff --git a/pac/atsamc20e/src/sercom0/i2cm.rs b/pac/atsamc20e/src/sercom0/i2cm.rs new file mode 100644 index 000000000000..8aa217da8b18 --- /dev/null +++ b/pac/atsamc20e/src/sercom0/i2cm.rs @@ -0,0 +1,44 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "I2CM Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "I2CM Control B"] +pub mod ctrlb; +#[doc = "BAUD register accessor: an alias for `Reg`"] +pub type BAUD = crate::Reg; +#[doc = "I2CM Baud Rate"] +pub mod baud; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "I2CM Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "I2CM Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "I2CM Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "I2CM Status"] +pub mod status; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "I2CM Synchronization Busy"] +pub mod syncbusy; +#[doc = "ADDR register accessor: an alias for `Reg`"] +pub type ADDR = crate::Reg; +#[doc = "I2CM Address"] +pub mod addr; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "I2CM Data"] +pub mod data; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "I2CM Debug Control"] +pub mod dbgctrl; diff --git a/pac/atsamc20e/src/sercom0/i2cm/addr.rs b/pac/atsamc20e/src/sercom0/i2cm/addr.rs new file mode 100644 index 000000000000..4efd19e824c6 --- /dev/null +++ b/pac/atsamc20e/src/sercom0/i2cm/addr.rs @@ -0,0 +1,281 @@ +#[doc = "Register `ADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ADDR` reader - Address Value"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - Address Value"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07ff) | (value as u32 & 0x07ff); + self.w + } +} +#[doc = "Field `LENEN` reader - Length Enable"] +pub struct LENEN_R(crate::FieldReader); +impl LENEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LENEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LENEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LENEN` writer - Length Enable"] +pub struct LENEN_W<'a> { + w: &'a mut W, +} +impl<'a> LENEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `HS` reader - High Speed Mode"] +pub struct HS_R(crate::FieldReader); +impl HS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HS` writer - High Speed Mode"] +pub struct HS_W<'a> { + w: &'a mut W, +} +impl<'a> HS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `TENBITEN` reader - Ten Bit Addressing Enable"] +pub struct TENBITEN_R(crate::FieldReader); +impl TENBITEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TENBITEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TENBITEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TENBITEN` writer - Ten Bit Addressing Enable"] +pub struct TENBITEN_W<'a> { + w: &'a mut W, +} +impl<'a> TENBITEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `LEN` reader - Length"] +pub struct LEN_R(crate::FieldReader); +impl LEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LEN` writer - Length"] +pub struct LEN_W<'a> { + w: &'a mut W, +} +impl<'a> LEN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:10 - Address Value"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new((self.bits & 0x07ff) as u16) + } + #[doc = "Bit 13 - Length Enable"] + #[inline(always)] + pub fn lenen(&self) -> LENEN_R { + LENEN_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - High Speed Mode"] + #[inline(always)] + pub fn hs(&self) -> HS_R { + HS_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Ten Bit Addressing Enable"] + #[inline(always)] + pub fn tenbiten(&self) -> TENBITEN_R { + TENBITEN_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:23 - Length"] + #[inline(always)] + pub fn len(&self) -> LEN_R { + LEN_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:10 - Address Value"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Bit 13 - Length Enable"] + #[inline(always)] + pub fn lenen(&mut self) -> LENEN_W { + LENEN_W { w: self } + } + #[doc = "Bit 14 - High Speed Mode"] + #[inline(always)] + pub fn hs(&mut self) -> HS_W { + HS_W { w: self } + } + #[doc = "Bit 15 - Ten Bit Addressing Enable"] + #[inline(always)] + pub fn tenbiten(&mut self) -> TENBITEN_W { + TENBITEN_W { w: self } + } + #[doc = "Bits 16:23 - Length"] + #[inline(always)] + pub fn len(&mut self) -> LEN_W { + LEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [addr](index.html) module"] +pub struct ADDR_SPEC; +impl crate::RegisterSpec for ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [addr::R](R) reader structure"] +impl crate::Readable for ADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [addr::W](W) writer structure"] +impl crate::Writable for ADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ADDR to value 0"] +impl crate::Resettable for ADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/sercom0/i2cm/baud.rs b/pac/atsamc20e/src/sercom0/i2cm/baud.rs new file mode 100644 index 000000000000..7c98d3b5b0de --- /dev/null +++ b/pac/atsamc20e/src/sercom0/i2cm/baud.rs @@ -0,0 +1,214 @@ +#[doc = "Register `BAUD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +#[doc = "Field `BAUDLOW` reader - Baud Rate Value Low"] +pub struct BAUDLOW_R(crate::FieldReader); +impl BAUDLOW_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BAUDLOW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUDLOW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUDLOW` writer - Baud Rate Value Low"] +pub struct BAUDLOW_W<'a> { + w: &'a mut W, +} +impl<'a> BAUDLOW_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +#[doc = "Field `HSBAUD` reader - High Speed Baud Rate Value"] +pub struct HSBAUD_R(crate::FieldReader); +impl HSBAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + HSBAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HSBAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HSBAUD` writer - High Speed Baud Rate Value"] +pub struct HSBAUD_W<'a> { + w: &'a mut W, +} +impl<'a> HSBAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +#[doc = "Field `HSBAUDLOW` reader - High Speed Baud Rate Value Low"] +pub struct HSBAUDLOW_R(crate::FieldReader); +impl HSBAUDLOW_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + HSBAUDLOW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HSBAUDLOW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HSBAUDLOW` writer - High Speed Baud Rate Value Low"] +pub struct HSBAUDLOW_W<'a> { + w: &'a mut W, +} +impl<'a> HSBAUDLOW_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 24)) | ((value as u32 & 0xff) << 24); + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Baud Rate Value Low"] + #[inline(always)] + pub fn baudlow(&self) -> BAUDLOW_R { + BAUDLOW_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - High Speed Baud Rate Value"] + #[inline(always)] + pub fn hsbaud(&self) -> HSBAUD_R { + HSBAUD_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - High Speed Baud Rate Value Low"] + #[inline(always)] + pub fn hsbaudlow(&self) -> HSBAUDLOW_R { + HSBAUDLOW_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Bits 8:15 - Baud Rate Value Low"] + #[inline(always)] + pub fn baudlow(&mut self) -> BAUDLOW_W { + BAUDLOW_W { w: self } + } + #[doc = "Bits 16:23 - High Speed Baud Rate Value"] + #[inline(always)] + pub fn hsbaud(&mut self) -> HSBAUD_W { + HSBAUD_W { w: self } + } + #[doc = "Bits 24:31 - High Speed Baud Rate Value Low"] + #[inline(always)] + pub fn hsbaudlow(&mut self) -> HSBAUDLOW_W { + HSBAUDLOW_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud](index.html) module"] +pub struct BAUD_SPEC; +impl crate::RegisterSpec for BAUD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [baud::R](R) reader structure"] +impl crate::Readable for BAUD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud::W](W) writer structure"] +impl crate::Writable for BAUD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD to value 0"] +impl crate::Resettable for BAUD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/sercom0/i2cm/ctrla.rs b/pac/atsamc20e/src/sercom0/i2cm/ctrla.rs new file mode 100644 index 000000000000..34fa668b7967 --- /dev/null +++ b/pac/atsamc20e/src/sercom0/i2cm/ctrla.rs @@ -0,0 +1,903 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: USART with external clock"] + USART_EXT_CLK = 0, + #[doc = "1: USART with internal clock"] + USART_INT_CLK = 1, + #[doc = "2: SPI in slave operation"] + SPI_SLAVE = 2, + #[doc = "3: SPI in master operation"] + SPI_MASTER = 3, + #[doc = "4: I2C slave operation"] + I2C_SLAVE = 4, + #[doc = "5: I2C master operation"] + I2C_MASTER = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::USART_EXT_CLK), + 1 => Some(MODE_A::USART_INT_CLK), + 2 => Some(MODE_A::SPI_SLAVE), + 3 => Some(MODE_A::SPI_MASTER), + 4 => Some(MODE_A::I2C_SLAVE), + 5 => Some(MODE_A::I2C_MASTER), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_EXT_CLK`"] + #[inline(always)] + pub fn is_usart_ext_clk(&self) -> bool { + **self == MODE_A::USART_EXT_CLK + } + #[doc = "Checks if the value of the field is `USART_INT_CLK`"] + #[inline(always)] + pub fn is_usart_int_clk(&self) -> bool { + **self == MODE_A::USART_INT_CLK + } + #[doc = "Checks if the value of the field is `SPI_SLAVE`"] + #[inline(always)] + pub fn is_spi_slave(&self) -> bool { + **self == MODE_A::SPI_SLAVE + } + #[doc = "Checks if the value of the field is `SPI_MASTER`"] + #[inline(always)] + pub fn is_spi_master(&self) -> bool { + **self == MODE_A::SPI_MASTER + } + #[doc = "Checks if the value of the field is `I2C_SLAVE`"] + #[inline(always)] + pub fn is_i2c_slave(&self) -> bool { + **self == MODE_A::I2C_SLAVE + } + #[doc = "Checks if the value of the field is `I2C_MASTER`"] + #[inline(always)] + pub fn is_i2c_master(&self) -> bool { + **self == MODE_A::I2C_MASTER + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART with external clock"] + #[inline(always)] + pub fn usart_ext_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_EXT_CLK) + } + #[doc = "USART with internal clock"] + #[inline(always)] + pub fn usart_int_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_INT_CLK) + } + #[doc = "SPI in slave operation"] + #[inline(always)] + pub fn spi_slave(self) -> &'a mut W { + self.variant(MODE_A::SPI_SLAVE) + } + #[doc = "SPI in master operation"] + #[inline(always)] + pub fn spi_master(self) -> &'a mut W { + self.variant(MODE_A::SPI_MASTER) + } + #[doc = "I2C slave operation"] + #[inline(always)] + pub fn i2c_slave(self) -> &'a mut W { + self.variant(MODE_A::I2C_SLAVE) + } + #[doc = "I2C master operation"] + #[inline(always)] + pub fn i2c_master(self) -> &'a mut W { + self.variant(MODE_A::I2C_MASTER) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 2)) | ((value as u32 & 0x07) << 2); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `PINOUT` reader - Pin Usage"] +pub struct PINOUT_R(crate::FieldReader); +impl PINOUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PINOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PINOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PINOUT` writer - Pin Usage"] +pub struct PINOUT_W<'a> { + w: &'a mut W, +} +impl<'a> PINOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "SDA Hold Time\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SDAHOLD_A { + #[doc = "0: Disabled"] + DISABLE = 0, + #[doc = "1: 50-100ns hold time"] + _75NS = 1, + #[doc = "2: 300-600ns hold time"] + _450NS = 2, + #[doc = "3: 400-800ns hold time"] + _600NS = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SDAHOLD_A) -> Self { + variant as _ + } +} +#[doc = "Field `SDAHOLD` reader - SDA Hold Time"] +pub struct SDAHOLD_R(crate::FieldReader); +impl SDAHOLD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SDAHOLD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SDAHOLD_A { + match self.bits { + 0 => SDAHOLD_A::DISABLE, + 1 => SDAHOLD_A::_75NS, + 2 => SDAHOLD_A::_450NS, + 3 => SDAHOLD_A::_600NS, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == SDAHOLD_A::DISABLE + } + #[doc = "Checks if the value of the field is `_75NS`"] + #[inline(always)] + pub fn is_75ns(&self) -> bool { + **self == SDAHOLD_A::_75NS + } + #[doc = "Checks if the value of the field is `_450NS`"] + #[inline(always)] + pub fn is_450ns(&self) -> bool { + **self == SDAHOLD_A::_450NS + } + #[doc = "Checks if the value of the field is `_600NS`"] + #[inline(always)] + pub fn is_600ns(&self) -> bool { + **self == SDAHOLD_A::_600NS + } +} +impl core::ops::Deref for SDAHOLD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SDAHOLD` writer - SDA Hold Time"] +pub struct SDAHOLD_W<'a> { + w: &'a mut W, +} +impl<'a> SDAHOLD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SDAHOLD_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(SDAHOLD_A::DISABLE) + } + #[doc = "50-100ns hold time"] + #[inline(always)] + pub fn _75ns(self) -> &'a mut W { + self.variant(SDAHOLD_A::_75NS) + } + #[doc = "300-600ns hold time"] + #[inline(always)] + pub fn _450ns(self) -> &'a mut W { + self.variant(SDAHOLD_A::_450NS) + } + #[doc = "400-800ns hold time"] + #[inline(always)] + pub fn _600ns(self) -> &'a mut W { + self.variant(SDAHOLD_A::_600NS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 20)) | ((value as u32 & 0x03) << 20); + self.w + } +} +#[doc = "Field `MEXTTOEN` reader - Master SCL Low Extend Timeout"] +pub struct MEXTTOEN_R(crate::FieldReader); +impl MEXTTOEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MEXTTOEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MEXTTOEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MEXTTOEN` writer - Master SCL Low Extend Timeout"] +pub struct MEXTTOEN_W<'a> { + w: &'a mut W, +} +impl<'a> MEXTTOEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `SEXTTOEN` reader - Slave SCL Low Extend Timeout"] +pub struct SEXTTOEN_R(crate::FieldReader); +impl SEXTTOEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SEXTTOEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEXTTOEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEXTTOEN` writer - Slave SCL Low Extend Timeout"] +pub struct SEXTTOEN_W<'a> { + w: &'a mut W, +} +impl<'a> SEXTTOEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Transfer Speed\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SPEED_A { + #[doc = "0: Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz"] + STANDARD_AND_FAST_MODE = 0, + #[doc = "1: Fast-mode Plus Upto 1MHz"] + FASTPLUS_MODE = 1, + #[doc = "2: High-speed mode Upto 3.4MHz"] + HIGH_SPEED_MODE = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SPEED_A) -> Self { + variant as _ + } +} +#[doc = "Field `SPEED` reader - Transfer Speed"] +pub struct SPEED_R(crate::FieldReader); +impl SPEED_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SPEED_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SPEED_A::STANDARD_AND_FAST_MODE), + 1 => Some(SPEED_A::FASTPLUS_MODE), + 2 => Some(SPEED_A::HIGH_SPEED_MODE), + _ => None, + } + } + #[doc = "Checks if the value of the field is `STANDARD_AND_FAST_MODE`"] + #[inline(always)] + pub fn is_standard_and_fast_mode(&self) -> bool { + **self == SPEED_A::STANDARD_AND_FAST_MODE + } + #[doc = "Checks if the value of the field is `FASTPLUS_MODE`"] + #[inline(always)] + pub fn is_fastplus_mode(&self) -> bool { + **self == SPEED_A::FASTPLUS_MODE + } + #[doc = "Checks if the value of the field is `HIGH_SPEED_MODE`"] + #[inline(always)] + pub fn is_high_speed_mode(&self) -> bool { + **self == SPEED_A::HIGH_SPEED_MODE + } +} +impl core::ops::Deref for SPEED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SPEED` writer - Transfer Speed"] +pub struct SPEED_W<'a> { + w: &'a mut W, +} +impl<'a> SPEED_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SPEED_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz"] + #[inline(always)] + pub fn standard_and_fast_mode(self) -> &'a mut W { + self.variant(SPEED_A::STANDARD_AND_FAST_MODE) + } + #[doc = "Fast-mode Plus Upto 1MHz"] + #[inline(always)] + pub fn fastplus_mode(self) -> &'a mut W { + self.variant(SPEED_A::FASTPLUS_MODE) + } + #[doc = "High-speed mode Upto 3.4MHz"] + #[inline(always)] + pub fn high_speed_mode(self) -> &'a mut W { + self.variant(SPEED_A::HIGH_SPEED_MODE) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 24)) | ((value as u32 & 0x03) << 24); + self.w + } +} +#[doc = "Field `SCLSM` reader - SCL Clock Stretch Mode"] +pub struct SCLSM_R(crate::FieldReader); +impl SCLSM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SCLSM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SCLSM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SCLSM` writer - SCL Clock Stretch Mode"] +pub struct SCLSM_W<'a> { + w: &'a mut W, +} +impl<'a> SCLSM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +#[doc = "Inactive Time-Out\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum INACTOUT_A { + #[doc = "0: Disabled"] + DISABLE = 0, + #[doc = "1: 5-6 SCL Time-Out(50-60us)"] + _55US = 1, + #[doc = "2: 10-11 SCL Time-Out(100-110us)"] + _105US = 2, + #[doc = "3: 20-21 SCL Time-Out(200-210us)"] + _205US = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: INACTOUT_A) -> Self { + variant as _ + } +} +#[doc = "Field `INACTOUT` reader - Inactive Time-Out"] +pub struct INACTOUT_R(crate::FieldReader); +impl INACTOUT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + INACTOUT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INACTOUT_A { + match self.bits { + 0 => INACTOUT_A::DISABLE, + 1 => INACTOUT_A::_55US, + 2 => INACTOUT_A::_105US, + 3 => INACTOUT_A::_205US, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == INACTOUT_A::DISABLE + } + #[doc = "Checks if the value of the field is `_55US`"] + #[inline(always)] + pub fn is_55us(&self) -> bool { + **self == INACTOUT_A::_55US + } + #[doc = "Checks if the value of the field is `_105US`"] + #[inline(always)] + pub fn is_105us(&self) -> bool { + **self == INACTOUT_A::_105US + } + #[doc = "Checks if the value of the field is `_205US`"] + #[inline(always)] + pub fn is_205us(&self) -> bool { + **self == INACTOUT_A::_205US + } +} +impl core::ops::Deref for INACTOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INACTOUT` writer - Inactive Time-Out"] +pub struct INACTOUT_W<'a> { + w: &'a mut W, +} +impl<'a> INACTOUT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: INACTOUT_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(INACTOUT_A::DISABLE) + } + #[doc = "5-6 SCL Time-Out(50-60us)"] + #[inline(always)] + pub fn _55us(self) -> &'a mut W { + self.variant(INACTOUT_A::_55US) + } + #[doc = "10-11 SCL Time-Out(100-110us)"] + #[inline(always)] + pub fn _105us(self) -> &'a mut W { + self.variant(INACTOUT_A::_105US) + } + #[doc = "20-21 SCL Time-Out(200-210us)"] + #[inline(always)] + pub fn _205us(self) -> &'a mut W { + self.variant(INACTOUT_A::_205US) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 28)) | ((value as u32 & 0x03) << 28); + self.w + } +} +#[doc = "Field `LOWTOUTEN` reader - SCL Low Timeout Enable"] +pub struct LOWTOUTEN_R(crate::FieldReader); +impl LOWTOUTEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LOWTOUTEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOWTOUTEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LOWTOUTEN` writer - SCL Low Timeout Enable"] +pub struct LOWTOUTEN_W<'a> { + w: &'a mut W, +} +impl<'a> LOWTOUTEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x07) as u8) + } + #[doc = "Bit 7 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 16 - Pin Usage"] + #[inline(always)] + pub fn pinout(&self) -> PINOUT_R { + PINOUT_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bits 20:21 - SDA Hold Time"] + #[inline(always)] + pub fn sdahold(&self) -> SDAHOLD_R { + SDAHOLD_R::new(((self.bits >> 20) & 0x03) as u8) + } + #[doc = "Bit 22 - Master SCL Low Extend Timeout"] + #[inline(always)] + pub fn mexttoen(&self) -> MEXTTOEN_R { + MEXTTOEN_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttoen(&self) -> SEXTTOEN_R { + SEXTTOEN_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bits 24:25 - Transfer Speed"] + #[inline(always)] + pub fn speed(&self) -> SPEED_R { + SPEED_R::new(((self.bits >> 24) & 0x03) as u8) + } + #[doc = "Bit 27 - SCL Clock Stretch Mode"] + #[inline(always)] + pub fn sclsm(&self) -> SCLSM_R { + SCLSM_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bits 28:29 - Inactive Time-Out"] + #[inline(always)] + pub fn inactout(&self) -> INACTOUT_R { + INACTOUT_R::new(((self.bits >> 28) & 0x03) as u8) + } + #[doc = "Bit 30 - SCL Low Timeout Enable"] + #[inline(always)] + pub fn lowtouten(&self) -> LOWTOUTEN_R { + LOWTOUTEN_R::new(((self.bits >> 30) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 7 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 16 - Pin Usage"] + #[inline(always)] + pub fn pinout(&mut self) -> PINOUT_W { + PINOUT_W { w: self } + } + #[doc = "Bits 20:21 - SDA Hold Time"] + #[inline(always)] + pub fn sdahold(&mut self) -> SDAHOLD_W { + SDAHOLD_W { w: self } + } + #[doc = "Bit 22 - Master SCL Low Extend Timeout"] + #[inline(always)] + pub fn mexttoen(&mut self) -> MEXTTOEN_W { + MEXTTOEN_W { w: self } + } + #[doc = "Bit 23 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttoen(&mut self) -> SEXTTOEN_W { + SEXTTOEN_W { w: self } + } + #[doc = "Bits 24:25 - Transfer Speed"] + #[inline(always)] + pub fn speed(&mut self) -> SPEED_W { + SPEED_W { w: self } + } + #[doc = "Bit 27 - SCL Clock Stretch Mode"] + #[inline(always)] + pub fn sclsm(&mut self) -> SCLSM_W { + SCLSM_W { w: self } + } + #[doc = "Bits 28:29 - Inactive Time-Out"] + #[inline(always)] + pub fn inactout(&mut self) -> INACTOUT_W { + INACTOUT_W { w: self } + } + #[doc = "Bit 30 - SCL Low Timeout Enable"] + #[inline(always)] + pub fn lowtouten(&mut self) -> LOWTOUTEN_W { + LOWTOUTEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/sercom0/i2cm/ctrlb.rs b/pac/atsamc20e/src/sercom0/i2cm/ctrlb.rs new file mode 100644 index 000000000000..ce534463c0da --- /dev/null +++ b/pac/atsamc20e/src/sercom0/i2cm/ctrlb.rs @@ -0,0 +1,244 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SMEN` reader - Smart Mode Enable"] +pub struct SMEN_R(crate::FieldReader); +impl SMEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SMEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SMEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SMEN` writer - Smart Mode Enable"] +pub struct SMEN_W<'a> { + w: &'a mut W, +} +impl<'a> SMEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `QCEN` reader - Quick Command Enable"] +pub struct QCEN_R(crate::FieldReader); +impl QCEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + QCEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for QCEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `QCEN` writer - Quick Command Enable"] +pub struct QCEN_W<'a> { + w: &'a mut W, +} +impl<'a> QCEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Field `ACKACT` reader - Acknowledge Action"] +pub struct ACKACT_R(crate::FieldReader); +impl ACKACT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ACKACT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ACKACT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ACKACT` writer - Acknowledge Action"] +pub struct ACKACT_W<'a> { + w: &'a mut W, +} +impl<'a> ACKACT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +impl R { + #[doc = "Bit 8 - Smart Mode Enable"] + #[inline(always)] + pub fn smen(&self) -> SMEN_R { + SMEN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Quick Command Enable"] + #[inline(always)] + pub fn qcen(&self) -> QCEN_R { + QCEN_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bits 16:17 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bit 18 - Acknowledge Action"] + #[inline(always)] + pub fn ackact(&self) -> ACKACT_R { + ACKACT_R::new(((self.bits >> 18) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 8 - Smart Mode Enable"] + #[inline(always)] + pub fn smen(&mut self) -> SMEN_W { + SMEN_W { w: self } + } + #[doc = "Bit 9 - Quick Command Enable"] + #[inline(always)] + pub fn qcen(&mut self) -> QCEN_W { + QCEN_W { w: self } + } + #[doc = "Bits 16:17 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Bit 18 - Acknowledge Action"] + #[inline(always)] + pub fn ackact(&mut self) -> ACKACT_W { + ACKACT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/sercom0/i2cm/data.rs b/pac/atsamc20e/src/sercom0/i2cm/data.rs new file mode 100644 index 000000000000..cf204596d3a6 --- /dev/null +++ b/pac/atsamc20e/src/sercom0/i2cm/data.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data Value"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data Value"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Data Value"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Value"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/sercom0/i2cm/dbgctrl.rs b/pac/atsamc20e/src/sercom0/i2cm/dbgctrl.rs new file mode 100644 index 000000000000..0fffdb4c6e39 --- /dev/null +++ b/pac/atsamc20e/src/sercom0/i2cm/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGSTOP` reader - Debug Mode"] +pub struct DBGSTOP_R(crate::FieldReader); +impl DBGSTOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGSTOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGSTOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGSTOP` writer - Debug Mode"] +pub struct DBGSTOP_W<'a> { + w: &'a mut W, +} +impl<'a> DBGSTOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&self) -> DBGSTOP_R { + DBGSTOP_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&mut self) -> DBGSTOP_W { + DBGSTOP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/sercom0/i2cm/intenclr.rs b/pac/atsamc20e/src/sercom0/i2cm/intenclr.rs new file mode 100644 index 000000000000..17f067a55656 --- /dev/null +++ b/pac/atsamc20e/src/sercom0/i2cm/intenclr.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MB` reader - Master On Bus Interrupt Disable"] +pub struct MB_R(crate::FieldReader); +impl MB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MB` writer - Master On Bus Interrupt Disable"] +pub struct MB_W<'a> { + w: &'a mut W, +} +impl<'a> MB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SB` reader - Slave On Bus Interrupt Disable"] +pub struct SB_R(crate::FieldReader); +impl SB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SB` writer - Slave On Bus Interrupt Disable"] +pub struct SB_W<'a> { + w: &'a mut W, +} +impl<'a> SB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Disable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Disable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Master On Bus Interrupt Disable"] + #[inline(always)] + pub fn mb(&self) -> MB_R { + MB_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Slave On Bus Interrupt Disable"] + #[inline(always)] + pub fn sb(&self) -> SB_R { + SB_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Master On Bus Interrupt Disable"] + #[inline(always)] + pub fn mb(&mut self) -> MB_W { + MB_W { w: self } + } + #[doc = "Bit 1 - Slave On Bus Interrupt Disable"] + #[inline(always)] + pub fn sb(&mut self) -> SB_W { + SB_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/sercom0/i2cm/intenset.rs b/pac/atsamc20e/src/sercom0/i2cm/intenset.rs new file mode 100644 index 000000000000..a0cbf96b3aa0 --- /dev/null +++ b/pac/atsamc20e/src/sercom0/i2cm/intenset.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MB` reader - Master On Bus Interrupt Enable"] +pub struct MB_R(crate::FieldReader); +impl MB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MB` writer - Master On Bus Interrupt Enable"] +pub struct MB_W<'a> { + w: &'a mut W, +} +impl<'a> MB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SB` reader - Slave On Bus Interrupt Enable"] +pub struct SB_R(crate::FieldReader); +impl SB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SB` writer - Slave On Bus Interrupt Enable"] +pub struct SB_W<'a> { + w: &'a mut W, +} +impl<'a> SB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Master On Bus Interrupt Enable"] + #[inline(always)] + pub fn mb(&self) -> MB_R { + MB_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Slave On Bus Interrupt Enable"] + #[inline(always)] + pub fn sb(&self) -> SB_R { + SB_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Master On Bus Interrupt Enable"] + #[inline(always)] + pub fn mb(&mut self) -> MB_W { + MB_W { w: self } + } + #[doc = "Bit 1 - Slave On Bus Interrupt Enable"] + #[inline(always)] + pub fn sb(&mut self) -> SB_W { + SB_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/sercom0/i2cm/intflag.rs b/pac/atsamc20e/src/sercom0/i2cm/intflag.rs new file mode 100644 index 000000000000..0fb0d2b9060c --- /dev/null +++ b/pac/atsamc20e/src/sercom0/i2cm/intflag.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MB` reader - Master On Bus Interrupt"] +pub struct MB_R(crate::FieldReader); +impl MB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MB` writer - Master On Bus Interrupt"] +pub struct MB_W<'a> { + w: &'a mut W, +} +impl<'a> MB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SB` reader - Slave On Bus Interrupt"] +pub struct SB_R(crate::FieldReader); +impl SB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SB` writer - Slave On Bus Interrupt"] +pub struct SB_W<'a> { + w: &'a mut W, +} +impl<'a> SB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Master On Bus Interrupt"] + #[inline(always)] + pub fn mb(&self) -> MB_R { + MB_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Slave On Bus Interrupt"] + #[inline(always)] + pub fn sb(&self) -> SB_R { + SB_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Master On Bus Interrupt"] + #[inline(always)] + pub fn mb(&mut self) -> MB_W { + MB_W { w: self } + } + #[doc = "Bit 1 - Slave On Bus Interrupt"] + #[inline(always)] + pub fn sb(&mut self) -> SB_W { + SB_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/sercom0/i2cm/status.rs b/pac/atsamc20e/src/sercom0/i2cm/status.rs new file mode 100644 index 000000000000..95af23673ec4 --- /dev/null +++ b/pac/atsamc20e/src/sercom0/i2cm/status.rs @@ -0,0 +1,479 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BUSERR` reader - Bus Error"] +pub struct BUSERR_R(crate::FieldReader); +impl BUSERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSERR` writer - Bus Error"] +pub struct BUSERR_W<'a> { + w: &'a mut W, +} +impl<'a> BUSERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `ARBLOST` reader - Arbitration Lost"] +pub struct ARBLOST_R(crate::FieldReader); +impl ARBLOST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ARBLOST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ARBLOST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ARBLOST` writer - Arbitration Lost"] +pub struct ARBLOST_W<'a> { + w: &'a mut W, +} +impl<'a> ARBLOST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXNACK` reader - Received Not Acknowledge"] +pub struct RXNACK_R(crate::FieldReader); +impl RXNACK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXNACK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXNACK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXNACK` writer - Received Not Acknowledge"] +pub struct RXNACK_W<'a> { + w: &'a mut W, +} +impl<'a> RXNACK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `BUSSTATE` reader - Bus State"] +pub struct BUSSTATE_R(crate::FieldReader); +impl BUSSTATE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BUSSTATE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSSTATE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSSTATE` writer - Bus State"] +pub struct BUSSTATE_W<'a> { + w: &'a mut W, +} +impl<'a> BUSSTATE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u16 & 0x03) << 4); + self.w + } +} +#[doc = "Field `LOWTOUT` reader - SCL Low Timeout"] +pub struct LOWTOUT_R(crate::FieldReader); +impl LOWTOUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LOWTOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOWTOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LOWTOUT` writer - SCL Low Timeout"] +pub struct LOWTOUT_W<'a> { + w: &'a mut W, +} +impl<'a> LOWTOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `CLKHOLD` reader - Clock Hold"] +pub struct CLKHOLD_R(crate::FieldReader); +impl CLKHOLD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKHOLD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKHOLD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKHOLD` writer - Clock Hold"] +pub struct CLKHOLD_W<'a> { + w: &'a mut W, +} +impl<'a> CLKHOLD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `MEXTTOUT` reader - Master SCL Low Extend Timeout"] +pub struct MEXTTOUT_R(crate::FieldReader); +impl MEXTTOUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MEXTTOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MEXTTOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MEXTTOUT` writer - Master SCL Low Extend Timeout"] +pub struct MEXTTOUT_W<'a> { + w: &'a mut W, +} +impl<'a> MEXTTOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `SEXTTOUT` reader - Slave SCL Low Extend Timeout"] +pub struct SEXTTOUT_R(crate::FieldReader); +impl SEXTTOUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SEXTTOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEXTTOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEXTTOUT` writer - Slave SCL Low Extend Timeout"] +pub struct SEXTTOUT_W<'a> { + w: &'a mut W, +} +impl<'a> SEXTTOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `LENERR` reader - Length Error"] +pub struct LENERR_R(crate::FieldReader); +impl LENERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LENERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LENERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LENERR` writer - Length Error"] +pub struct LENERR_W<'a> { + w: &'a mut W, +} +impl<'a> LENERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u16 & 0x01) << 10); + self.w + } +} +impl R { + #[doc = "Bit 0 - Bus Error"] + #[inline(always)] + pub fn buserr(&self) -> BUSERR_R { + BUSERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Arbitration Lost"] + #[inline(always)] + pub fn arblost(&self) -> ARBLOST_R { + ARBLOST_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Received Not Acknowledge"] + #[inline(always)] + pub fn rxnack(&self) -> RXNACK_R { + RXNACK_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 4:5 - Bus State"] + #[inline(always)] + pub fn busstate(&self) -> BUSSTATE_R { + BUSSTATE_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bit 6 - SCL Low Timeout"] + #[inline(always)] + pub fn lowtout(&self) -> LOWTOUT_R { + LOWTOUT_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Clock Hold"] + #[inline(always)] + pub fn clkhold(&self) -> CLKHOLD_R { + CLKHOLD_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Master SCL Low Extend Timeout"] + #[inline(always)] + pub fn mexttout(&self) -> MEXTTOUT_R { + MEXTTOUT_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttout(&self) -> SEXTTOUT_R { + SEXTTOUT_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Length Error"] + #[inline(always)] + pub fn lenerr(&self) -> LENERR_R { + LENERR_R::new(((self.bits >> 10) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Bus Error"] + #[inline(always)] + pub fn buserr(&mut self) -> BUSERR_W { + BUSERR_W { w: self } + } + #[doc = "Bit 1 - Arbitration Lost"] + #[inline(always)] + pub fn arblost(&mut self) -> ARBLOST_W { + ARBLOST_W { w: self } + } + #[doc = "Bit 2 - Received Not Acknowledge"] + #[inline(always)] + pub fn rxnack(&mut self) -> RXNACK_W { + RXNACK_W { w: self } + } + #[doc = "Bits 4:5 - Bus State"] + #[inline(always)] + pub fn busstate(&mut self) -> BUSSTATE_W { + BUSSTATE_W { w: self } + } + #[doc = "Bit 6 - SCL Low Timeout"] + #[inline(always)] + pub fn lowtout(&mut self) -> LOWTOUT_W { + LOWTOUT_W { w: self } + } + #[doc = "Bit 7 - Clock Hold"] + #[inline(always)] + pub fn clkhold(&mut self) -> CLKHOLD_W { + CLKHOLD_W { w: self } + } + #[doc = "Bit 8 - Master SCL Low Extend Timeout"] + #[inline(always)] + pub fn mexttout(&mut self) -> MEXTTOUT_W { + MEXTTOUT_W { w: self } + } + #[doc = "Bit 9 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttout(&mut self) -> SEXTTOUT_W { + SEXTTOUT_W { w: self } + } + #[doc = "Bit 10 - Length Error"] + #[inline(always)] + pub fn lenerr(&mut self) -> LENERR_W { + LENERR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/sercom0/i2cm/syncbusy.rs b/pac/atsamc20e/src/sercom0/i2cm/syncbusy.rs new file mode 100644 index 000000000000..87dd418d1cd3 --- /dev/null +++ b/pac/atsamc20e/src/sercom0/i2cm/syncbusy.rs @@ -0,0 +1,93 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - SERCOM Enable Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYSOP` reader - System Operation Synchronization Busy"] +pub struct SYSOP_R(crate::FieldReader); +impl SYSOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYSOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYSOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM Enable Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - System Operation Synchronization Busy"] + #[inline(always)] + pub fn sysop(&self) -> SYSOP_R { + SYSOP_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +#[doc = "I2CM Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/sercom0/i2cs.rs b/pac/atsamc20e/src/sercom0/i2cs.rs new file mode 100644 index 000000000000..baf9513c6cc1 --- /dev/null +++ b/pac/atsamc20e/src/sercom0/i2cs.rs @@ -0,0 +1,36 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "I2CS Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "I2CS Control B"] +pub mod ctrlb; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "I2CS Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "I2CS Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "I2CS Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "I2CS Status"] +pub mod status; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "I2CS Synchronization Busy"] +pub mod syncbusy; +#[doc = "ADDR register accessor: an alias for `Reg`"] +pub type ADDR = crate::Reg; +#[doc = "I2CS Address"] +pub mod addr; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "I2CS Data"] +pub mod data; diff --git a/pac/atsamc20e/src/sercom0/i2cs/addr.rs b/pac/atsamc20e/src/sercom0/i2cs/addr.rs new file mode 100644 index 000000000000..c1b69ee22891 --- /dev/null +++ b/pac/atsamc20e/src/sercom0/i2cs/addr.rs @@ -0,0 +1,234 @@ +#[doc = "Register `ADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `GENCEN` reader - General Call Address Enable"] +pub struct GENCEN_R(crate::FieldReader); +impl GENCEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENCEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENCEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENCEN` writer - General Call Address Enable"] +pub struct GENCEN_W<'a> { + w: &'a mut W, +} +impl<'a> GENCEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ADDR` reader - Address Value"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - Address Value"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03ff << 1)) | ((value as u32 & 0x03ff) << 1); + self.w + } +} +#[doc = "Field `TENBITEN` reader - Ten Bit Addressing Enable"] +pub struct TENBITEN_R(crate::FieldReader); +impl TENBITEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TENBITEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TENBITEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TENBITEN` writer - Ten Bit Addressing Enable"] +pub struct TENBITEN_W<'a> { + w: &'a mut W, +} +impl<'a> TENBITEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `ADDRMASK` reader - Address Mask"] +pub struct ADDRMASK_R(crate::FieldReader); +impl ADDRMASK_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + ADDRMASK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDRMASK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDRMASK` writer - Address Mask"] +pub struct ADDRMASK_W<'a> { + w: &'a mut W, +} +impl<'a> ADDRMASK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03ff << 17)) | ((value as u32 & 0x03ff) << 17); + self.w + } +} +impl R { + #[doc = "Bit 0 - General Call Address Enable"] + #[inline(always)] + pub fn gencen(&self) -> GENCEN_R { + GENCEN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bits 1:10 - Address Value"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new(((self.bits >> 1) & 0x03ff) as u16) + } + #[doc = "Bit 15 - Ten Bit Addressing Enable"] + #[inline(always)] + pub fn tenbiten(&self) -> TENBITEN_R { + TENBITEN_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 17:26 - Address Mask"] + #[inline(always)] + pub fn addrmask(&self) -> ADDRMASK_R { + ADDRMASK_R::new(((self.bits >> 17) & 0x03ff) as u16) + } +} +impl W { + #[doc = "Bit 0 - General Call Address Enable"] + #[inline(always)] + pub fn gencen(&mut self) -> GENCEN_W { + GENCEN_W { w: self } + } + #[doc = "Bits 1:10 - Address Value"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Bit 15 - Ten Bit Addressing Enable"] + #[inline(always)] + pub fn tenbiten(&mut self) -> TENBITEN_W { + TENBITEN_W { w: self } + } + #[doc = "Bits 17:26 - Address Mask"] + #[inline(always)] + pub fn addrmask(&mut self) -> ADDRMASK_W { + ADDRMASK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [addr](index.html) module"] +pub struct ADDR_SPEC; +impl crate::RegisterSpec for ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [addr::R](R) reader structure"] +impl crate::Readable for ADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [addr::W](W) writer structure"] +impl crate::Writable for ADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ADDR to value 0"] +impl crate::Resettable for ADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/sercom0/i2cs/ctrla.rs b/pac/atsamc20e/src/sercom0/i2cs/ctrla.rs new file mode 100644 index 000000000000..ec93812b004f --- /dev/null +++ b/pac/atsamc20e/src/sercom0/i2cs/ctrla.rs @@ -0,0 +1,744 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: USART with external clock"] + USART_EXT_CLK = 0, + #[doc = "1: USART with internal clock"] + USART_INT_CLK = 1, + #[doc = "2: SPI in slave operation"] + SPI_SLAVE = 2, + #[doc = "3: SPI in master operation"] + SPI_MASTER = 3, + #[doc = "4: I2C slave operation"] + I2C_SLAVE = 4, + #[doc = "5: I2C master operation"] + I2C_MASTER = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::USART_EXT_CLK), + 1 => Some(MODE_A::USART_INT_CLK), + 2 => Some(MODE_A::SPI_SLAVE), + 3 => Some(MODE_A::SPI_MASTER), + 4 => Some(MODE_A::I2C_SLAVE), + 5 => Some(MODE_A::I2C_MASTER), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_EXT_CLK`"] + #[inline(always)] + pub fn is_usart_ext_clk(&self) -> bool { + **self == MODE_A::USART_EXT_CLK + } + #[doc = "Checks if the value of the field is `USART_INT_CLK`"] + #[inline(always)] + pub fn is_usart_int_clk(&self) -> bool { + **self == MODE_A::USART_INT_CLK + } + #[doc = "Checks if the value of the field is `SPI_SLAVE`"] + #[inline(always)] + pub fn is_spi_slave(&self) -> bool { + **self == MODE_A::SPI_SLAVE + } + #[doc = "Checks if the value of the field is `SPI_MASTER`"] + #[inline(always)] + pub fn is_spi_master(&self) -> bool { + **self == MODE_A::SPI_MASTER + } + #[doc = "Checks if the value of the field is `I2C_SLAVE`"] + #[inline(always)] + pub fn is_i2c_slave(&self) -> bool { + **self == MODE_A::I2C_SLAVE + } + #[doc = "Checks if the value of the field is `I2C_MASTER`"] + #[inline(always)] + pub fn is_i2c_master(&self) -> bool { + **self == MODE_A::I2C_MASTER + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART with external clock"] + #[inline(always)] + pub fn usart_ext_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_EXT_CLK) + } + #[doc = "USART with internal clock"] + #[inline(always)] + pub fn usart_int_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_INT_CLK) + } + #[doc = "SPI in slave operation"] + #[inline(always)] + pub fn spi_slave(self) -> &'a mut W { + self.variant(MODE_A::SPI_SLAVE) + } + #[doc = "SPI in master operation"] + #[inline(always)] + pub fn spi_master(self) -> &'a mut W { + self.variant(MODE_A::SPI_MASTER) + } + #[doc = "I2C slave operation"] + #[inline(always)] + pub fn i2c_slave(self) -> &'a mut W { + self.variant(MODE_A::I2C_SLAVE) + } + #[doc = "I2C master operation"] + #[inline(always)] + pub fn i2c_master(self) -> &'a mut W { + self.variant(MODE_A::I2C_MASTER) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 2)) | ((value as u32 & 0x07) << 2); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `PINOUT` reader - Pin Usage"] +pub struct PINOUT_R(crate::FieldReader); +impl PINOUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PINOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PINOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PINOUT` writer - Pin Usage"] +pub struct PINOUT_W<'a> { + w: &'a mut W, +} +impl<'a> PINOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "SDA Hold Time\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SDAHOLD_A { + #[doc = "0: Disabled"] + DISABLE = 0, + #[doc = "1: 50-100ns hold time"] + _75NS = 1, + #[doc = "2: 300-600ns hold time"] + _450NS = 2, + #[doc = "3: 400-800ns hold time"] + _600NS = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SDAHOLD_A) -> Self { + variant as _ + } +} +#[doc = "Field `SDAHOLD` reader - SDA Hold Time"] +pub struct SDAHOLD_R(crate::FieldReader); +impl SDAHOLD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SDAHOLD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SDAHOLD_A { + match self.bits { + 0 => SDAHOLD_A::DISABLE, + 1 => SDAHOLD_A::_75NS, + 2 => SDAHOLD_A::_450NS, + 3 => SDAHOLD_A::_600NS, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == SDAHOLD_A::DISABLE + } + #[doc = "Checks if the value of the field is `_75NS`"] + #[inline(always)] + pub fn is_75ns(&self) -> bool { + **self == SDAHOLD_A::_75NS + } + #[doc = "Checks if the value of the field is `_450NS`"] + #[inline(always)] + pub fn is_450ns(&self) -> bool { + **self == SDAHOLD_A::_450NS + } + #[doc = "Checks if the value of the field is `_600NS`"] + #[inline(always)] + pub fn is_600ns(&self) -> bool { + **self == SDAHOLD_A::_600NS + } +} +impl core::ops::Deref for SDAHOLD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SDAHOLD` writer - SDA Hold Time"] +pub struct SDAHOLD_W<'a> { + w: &'a mut W, +} +impl<'a> SDAHOLD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SDAHOLD_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(SDAHOLD_A::DISABLE) + } + #[doc = "50-100ns hold time"] + #[inline(always)] + pub fn _75ns(self) -> &'a mut W { + self.variant(SDAHOLD_A::_75NS) + } + #[doc = "300-600ns hold time"] + #[inline(always)] + pub fn _450ns(self) -> &'a mut W { + self.variant(SDAHOLD_A::_450NS) + } + #[doc = "400-800ns hold time"] + #[inline(always)] + pub fn _600ns(self) -> &'a mut W { + self.variant(SDAHOLD_A::_600NS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 20)) | ((value as u32 & 0x03) << 20); + self.w + } +} +#[doc = "Field `SEXTTOEN` reader - Slave SCL Low Extend Timeout"] +pub struct SEXTTOEN_R(crate::FieldReader); +impl SEXTTOEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SEXTTOEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEXTTOEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEXTTOEN` writer - Slave SCL Low Extend Timeout"] +pub struct SEXTTOEN_W<'a> { + w: &'a mut W, +} +impl<'a> SEXTTOEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Transfer Speed\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SPEED_A { + #[doc = "0: Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz"] + STANDARD_AND_FAST_MODE = 0, + #[doc = "1: Fast-mode Plus Upto 1MHz"] + FASTPLUS_MODE = 1, + #[doc = "2: High-speed mode Upto 3.4MHz"] + HIGH_SPEED_MODE = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SPEED_A) -> Self { + variant as _ + } +} +#[doc = "Field `SPEED` reader - Transfer Speed"] +pub struct SPEED_R(crate::FieldReader); +impl SPEED_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SPEED_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SPEED_A::STANDARD_AND_FAST_MODE), + 1 => Some(SPEED_A::FASTPLUS_MODE), + 2 => Some(SPEED_A::HIGH_SPEED_MODE), + _ => None, + } + } + #[doc = "Checks if the value of the field is `STANDARD_AND_FAST_MODE`"] + #[inline(always)] + pub fn is_standard_and_fast_mode(&self) -> bool { + **self == SPEED_A::STANDARD_AND_FAST_MODE + } + #[doc = "Checks if the value of the field is `FASTPLUS_MODE`"] + #[inline(always)] + pub fn is_fastplus_mode(&self) -> bool { + **self == SPEED_A::FASTPLUS_MODE + } + #[doc = "Checks if the value of the field is `HIGH_SPEED_MODE`"] + #[inline(always)] + pub fn is_high_speed_mode(&self) -> bool { + **self == SPEED_A::HIGH_SPEED_MODE + } +} +impl core::ops::Deref for SPEED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SPEED` writer - Transfer Speed"] +pub struct SPEED_W<'a> { + w: &'a mut W, +} +impl<'a> SPEED_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SPEED_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz"] + #[inline(always)] + pub fn standard_and_fast_mode(self) -> &'a mut W { + self.variant(SPEED_A::STANDARD_AND_FAST_MODE) + } + #[doc = "Fast-mode Plus Upto 1MHz"] + #[inline(always)] + pub fn fastplus_mode(self) -> &'a mut W { + self.variant(SPEED_A::FASTPLUS_MODE) + } + #[doc = "High-speed mode Upto 3.4MHz"] + #[inline(always)] + pub fn high_speed_mode(self) -> &'a mut W { + self.variant(SPEED_A::HIGH_SPEED_MODE) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 24)) | ((value as u32 & 0x03) << 24); + self.w + } +} +#[doc = "Field `SCLSM` reader - SCL Clock Stretch Mode"] +pub struct SCLSM_R(crate::FieldReader); +impl SCLSM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SCLSM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SCLSM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SCLSM` writer - SCL Clock Stretch Mode"] +pub struct SCLSM_W<'a> { + w: &'a mut W, +} +impl<'a> SCLSM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +#[doc = "Field `LOWTOUTEN` reader - SCL Low Timeout Enable"] +pub struct LOWTOUTEN_R(crate::FieldReader); +impl LOWTOUTEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LOWTOUTEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOWTOUTEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LOWTOUTEN` writer - SCL Low Timeout Enable"] +pub struct LOWTOUTEN_W<'a> { + w: &'a mut W, +} +impl<'a> LOWTOUTEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x07) as u8) + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 16 - Pin Usage"] + #[inline(always)] + pub fn pinout(&self) -> PINOUT_R { + PINOUT_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bits 20:21 - SDA Hold Time"] + #[inline(always)] + pub fn sdahold(&self) -> SDAHOLD_R { + SDAHOLD_R::new(((self.bits >> 20) & 0x03) as u8) + } + #[doc = "Bit 23 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttoen(&self) -> SEXTTOEN_R { + SEXTTOEN_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bits 24:25 - Transfer Speed"] + #[inline(always)] + pub fn speed(&self) -> SPEED_R { + SPEED_R::new(((self.bits >> 24) & 0x03) as u8) + } + #[doc = "Bit 27 - SCL Clock Stretch Mode"] + #[inline(always)] + pub fn sclsm(&self) -> SCLSM_R { + SCLSM_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 30 - SCL Low Timeout Enable"] + #[inline(always)] + pub fn lowtouten(&self) -> LOWTOUTEN_R { + LOWTOUTEN_R::new(((self.bits >> 30) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 16 - Pin Usage"] + #[inline(always)] + pub fn pinout(&mut self) -> PINOUT_W { + PINOUT_W { w: self } + } + #[doc = "Bits 20:21 - SDA Hold Time"] + #[inline(always)] + pub fn sdahold(&mut self) -> SDAHOLD_W { + SDAHOLD_W { w: self } + } + #[doc = "Bit 23 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttoen(&mut self) -> SEXTTOEN_W { + SEXTTOEN_W { w: self } + } + #[doc = "Bits 24:25 - Transfer Speed"] + #[inline(always)] + pub fn speed(&mut self) -> SPEED_W { + SPEED_W { w: self } + } + #[doc = "Bit 27 - SCL Clock Stretch Mode"] + #[inline(always)] + pub fn sclsm(&mut self) -> SCLSM_W { + SCLSM_W { w: self } + } + #[doc = "Bit 30 - SCL Low Timeout Enable"] + #[inline(always)] + pub fn lowtouten(&mut self) -> LOWTOUTEN_W { + LOWTOUTEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/sercom0/i2cs/ctrlb.rs b/pac/atsamc20e/src/sercom0/i2cs/ctrlb.rs new file mode 100644 index 000000000000..b20f48581ed5 --- /dev/null +++ b/pac/atsamc20e/src/sercom0/i2cs/ctrlb.rs @@ -0,0 +1,328 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SMEN` reader - Smart Mode Enable"] +pub struct SMEN_R(crate::FieldReader); +impl SMEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SMEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SMEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SMEN` writer - Smart Mode Enable"] +pub struct SMEN_W<'a> { + w: &'a mut W, +} +impl<'a> SMEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `GCMD` reader - PMBus Group Command"] +pub struct GCMD_R(crate::FieldReader); +impl GCMD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GCMD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GCMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GCMD` writer - PMBus Group Command"] +pub struct GCMD_W<'a> { + w: &'a mut W, +} +impl<'a> GCMD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `AACKEN` reader - Automatic Address Acknowledge"] +pub struct AACKEN_R(crate::FieldReader); +impl AACKEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AACKEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AACKEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AACKEN` writer - Automatic Address Acknowledge"] +pub struct AACKEN_W<'a> { + w: &'a mut W, +} +impl<'a> AACKEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `AMODE` reader - Address Mode"] +pub struct AMODE_R(crate::FieldReader); +impl AMODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + AMODE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AMODE` writer - Address Mode"] +pub struct AMODE_W<'a> { + w: &'a mut W, +} +impl<'a> AMODE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 14)) | ((value as u32 & 0x03) << 14); + self.w + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Field `ACKACT` reader - Acknowledge Action"] +pub struct ACKACT_R(crate::FieldReader); +impl ACKACT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ACKACT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ACKACT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ACKACT` writer - Acknowledge Action"] +pub struct ACKACT_W<'a> { + w: &'a mut W, +} +impl<'a> ACKACT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +impl R { + #[doc = "Bit 8 - Smart Mode Enable"] + #[inline(always)] + pub fn smen(&self) -> SMEN_R { + SMEN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - PMBus Group Command"] + #[inline(always)] + pub fn gcmd(&self) -> GCMD_R { + GCMD_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Automatic Address Acknowledge"] + #[inline(always)] + pub fn aacken(&self) -> AACKEN_R { + AACKEN_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bits 14:15 - Address Mode"] + #[inline(always)] + pub fn amode(&self) -> AMODE_R { + AMODE_R::new(((self.bits >> 14) & 0x03) as u8) + } + #[doc = "Bits 16:17 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bit 18 - Acknowledge Action"] + #[inline(always)] + pub fn ackact(&self) -> ACKACT_R { + ACKACT_R::new(((self.bits >> 18) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 8 - Smart Mode Enable"] + #[inline(always)] + pub fn smen(&mut self) -> SMEN_W { + SMEN_W { w: self } + } + #[doc = "Bit 9 - PMBus Group Command"] + #[inline(always)] + pub fn gcmd(&mut self) -> GCMD_W { + GCMD_W { w: self } + } + #[doc = "Bit 10 - Automatic Address Acknowledge"] + #[inline(always)] + pub fn aacken(&mut self) -> AACKEN_W { + AACKEN_W { w: self } + } + #[doc = "Bits 14:15 - Address Mode"] + #[inline(always)] + pub fn amode(&mut self) -> AMODE_W { + AMODE_W { w: self } + } + #[doc = "Bits 16:17 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Bit 18 - Acknowledge Action"] + #[inline(always)] + pub fn ackact(&mut self) -> ACKACT_W { + ACKACT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/sercom0/i2cs/data.rs b/pac/atsamc20e/src/sercom0/i2cs/data.rs new file mode 100644 index 000000000000..d8bfe070431a --- /dev/null +++ b/pac/atsamc20e/src/sercom0/i2cs/data.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data Value"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data Value"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Data Value"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Value"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/sercom0/i2cs/intenclr.rs b/pac/atsamc20e/src/sercom0/i2cs/intenclr.rs new file mode 100644 index 000000000000..49f5191c8d63 --- /dev/null +++ b/pac/atsamc20e/src/sercom0/i2cs/intenclr.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PREC` reader - Stop Received Interrupt Disable"] +pub struct PREC_R(crate::FieldReader); +impl PREC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PREC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PREC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PREC` writer - Stop Received Interrupt Disable"] +pub struct PREC_W<'a> { + w: &'a mut W, +} +impl<'a> PREC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `AMATCH` reader - Address Match Interrupt Disable"] +pub struct AMATCH_R(crate::FieldReader); +impl AMATCH_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AMATCH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AMATCH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AMATCH` writer - Address Match Interrupt Disable"] +pub struct AMATCH_W<'a> { + w: &'a mut W, +} +impl<'a> AMATCH_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `DRDY` reader - Data Interrupt Disable"] +pub struct DRDY_R(crate::FieldReader); +impl DRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRDY` writer - Data Interrupt Disable"] +pub struct DRDY_W<'a> { + w: &'a mut W, +} +impl<'a> DRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Disable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Disable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Stop Received Interrupt Disable"] + #[inline(always)] + pub fn prec(&self) -> PREC_R { + PREC_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Address Match Interrupt Disable"] + #[inline(always)] + pub fn amatch(&self) -> AMATCH_R { + AMATCH_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Data Interrupt Disable"] + #[inline(always)] + pub fn drdy(&self) -> DRDY_R { + DRDY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Stop Received Interrupt Disable"] + #[inline(always)] + pub fn prec(&mut self) -> PREC_W { + PREC_W { w: self } + } + #[doc = "Bit 1 - Address Match Interrupt Disable"] + #[inline(always)] + pub fn amatch(&mut self) -> AMATCH_W { + AMATCH_W { w: self } + } + #[doc = "Bit 2 - Data Interrupt Disable"] + #[inline(always)] + pub fn drdy(&mut self) -> DRDY_W { + DRDY_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/sercom0/i2cs/intenset.rs b/pac/atsamc20e/src/sercom0/i2cs/intenset.rs new file mode 100644 index 000000000000..97ea784d7476 --- /dev/null +++ b/pac/atsamc20e/src/sercom0/i2cs/intenset.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PREC` reader - Stop Received Interrupt Enable"] +pub struct PREC_R(crate::FieldReader); +impl PREC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PREC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PREC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PREC` writer - Stop Received Interrupt Enable"] +pub struct PREC_W<'a> { + w: &'a mut W, +} +impl<'a> PREC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `AMATCH` reader - Address Match Interrupt Enable"] +pub struct AMATCH_R(crate::FieldReader); +impl AMATCH_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AMATCH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AMATCH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AMATCH` writer - Address Match Interrupt Enable"] +pub struct AMATCH_W<'a> { + w: &'a mut W, +} +impl<'a> AMATCH_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `DRDY` reader - Data Interrupt Enable"] +pub struct DRDY_R(crate::FieldReader); +impl DRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRDY` writer - Data Interrupt Enable"] +pub struct DRDY_W<'a> { + w: &'a mut W, +} +impl<'a> DRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Stop Received Interrupt Enable"] + #[inline(always)] + pub fn prec(&self) -> PREC_R { + PREC_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Address Match Interrupt Enable"] + #[inline(always)] + pub fn amatch(&self) -> AMATCH_R { + AMATCH_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Data Interrupt Enable"] + #[inline(always)] + pub fn drdy(&self) -> DRDY_R { + DRDY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Stop Received Interrupt Enable"] + #[inline(always)] + pub fn prec(&mut self) -> PREC_W { + PREC_W { w: self } + } + #[doc = "Bit 1 - Address Match Interrupt Enable"] + #[inline(always)] + pub fn amatch(&mut self) -> AMATCH_W { + AMATCH_W { w: self } + } + #[doc = "Bit 2 - Data Interrupt Enable"] + #[inline(always)] + pub fn drdy(&mut self) -> DRDY_W { + DRDY_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/sercom0/i2cs/intflag.rs b/pac/atsamc20e/src/sercom0/i2cs/intflag.rs new file mode 100644 index 000000000000..2eee333e4e59 --- /dev/null +++ b/pac/atsamc20e/src/sercom0/i2cs/intflag.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PREC` reader - Stop Received Interrupt"] +pub struct PREC_R(crate::FieldReader); +impl PREC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PREC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PREC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PREC` writer - Stop Received Interrupt"] +pub struct PREC_W<'a> { + w: &'a mut W, +} +impl<'a> PREC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `AMATCH` reader - Address Match Interrupt"] +pub struct AMATCH_R(crate::FieldReader); +impl AMATCH_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AMATCH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AMATCH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AMATCH` writer - Address Match Interrupt"] +pub struct AMATCH_W<'a> { + w: &'a mut W, +} +impl<'a> AMATCH_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `DRDY` reader - Data Interrupt"] +pub struct DRDY_R(crate::FieldReader); +impl DRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRDY` writer - Data Interrupt"] +pub struct DRDY_W<'a> { + w: &'a mut W, +} +impl<'a> DRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Stop Received Interrupt"] + #[inline(always)] + pub fn prec(&self) -> PREC_R { + PREC_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Address Match Interrupt"] + #[inline(always)] + pub fn amatch(&self) -> AMATCH_R { + AMATCH_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Data Interrupt"] + #[inline(always)] + pub fn drdy(&self) -> DRDY_R { + DRDY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Stop Received Interrupt"] + #[inline(always)] + pub fn prec(&mut self) -> PREC_W { + PREC_W { w: self } + } + #[doc = "Bit 1 - Address Match Interrupt"] + #[inline(always)] + pub fn amatch(&mut self) -> AMATCH_W { + AMATCH_W { w: self } + } + #[doc = "Bit 2 - Data Interrupt"] + #[inline(always)] + pub fn drdy(&mut self) -> DRDY_W { + DRDY_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/sercom0/i2cs/status.rs b/pac/atsamc20e/src/sercom0/i2cs/status.rs new file mode 100644 index 000000000000..b3f6d218fa66 --- /dev/null +++ b/pac/atsamc20e/src/sercom0/i2cs/status.rs @@ -0,0 +1,489 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BUSERR` reader - Bus Error"] +pub struct BUSERR_R(crate::FieldReader); +impl BUSERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSERR` writer - Bus Error"] +pub struct BUSERR_W<'a> { + w: &'a mut W, +} +impl<'a> BUSERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `COLL` reader - Transmit Collision"] +pub struct COLL_R(crate::FieldReader); +impl COLL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COLL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COLL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COLL` writer - Transmit Collision"] +pub struct COLL_W<'a> { + w: &'a mut W, +} +impl<'a> COLL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXNACK` reader - Received Not Acknowledge"] +pub struct RXNACK_R(crate::FieldReader); +impl RXNACK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXNACK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXNACK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXNACK` writer - Received Not Acknowledge"] +pub struct RXNACK_W<'a> { + w: &'a mut W, +} +impl<'a> RXNACK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `DIR` reader - Read/Write Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Read/Write Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `SR` reader - Repeated Start"] +pub struct SR_R(crate::FieldReader); +impl SR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SR` writer - Repeated Start"] +pub struct SR_W<'a> { + w: &'a mut W, +} +impl<'a> SR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `LOWTOUT` reader - SCL Low Timeout"] +pub struct LOWTOUT_R(crate::FieldReader); +impl LOWTOUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LOWTOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOWTOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LOWTOUT` writer - SCL Low Timeout"] +pub struct LOWTOUT_W<'a> { + w: &'a mut W, +} +impl<'a> LOWTOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `CLKHOLD` reader - Clock Hold"] +pub struct CLKHOLD_R(crate::FieldReader); +impl CLKHOLD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKHOLD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKHOLD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKHOLD` writer - Clock Hold"] +pub struct CLKHOLD_W<'a> { + w: &'a mut W, +} +impl<'a> CLKHOLD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `SEXTTOUT` reader - Slave SCL Low Extend Timeout"] +pub struct SEXTTOUT_R(crate::FieldReader); +impl SEXTTOUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SEXTTOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEXTTOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEXTTOUT` writer - Slave SCL Low Extend Timeout"] +pub struct SEXTTOUT_W<'a> { + w: &'a mut W, +} +impl<'a> SEXTTOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `HS` reader - High Speed"] +pub struct HS_R(crate::FieldReader); +impl HS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HS` writer - High Speed"] +pub struct HS_W<'a> { + w: &'a mut W, +} +impl<'a> HS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u16 & 0x01) << 10); + self.w + } +} +impl R { + #[doc = "Bit 0 - Bus Error"] + #[inline(always)] + pub fn buserr(&self) -> BUSERR_R { + BUSERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Collision"] + #[inline(always)] + pub fn coll(&self) -> COLL_R { + COLL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Received Not Acknowledge"] + #[inline(always)] + pub fn rxnack(&self) -> RXNACK_R { + RXNACK_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Read/Write Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Repeated Start"] + #[inline(always)] + pub fn sr(&self) -> SR_R { + SR_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 6 - SCL Low Timeout"] + #[inline(always)] + pub fn lowtout(&self) -> LOWTOUT_R { + LOWTOUT_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Clock Hold"] + #[inline(always)] + pub fn clkhold(&self) -> CLKHOLD_R { + CLKHOLD_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 9 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttout(&self) -> SEXTTOUT_R { + SEXTTOUT_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - High Speed"] + #[inline(always)] + pub fn hs(&self) -> HS_R { + HS_R::new(((self.bits >> 10) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Bus Error"] + #[inline(always)] + pub fn buserr(&mut self) -> BUSERR_W { + BUSERR_W { w: self } + } + #[doc = "Bit 1 - Transmit Collision"] + #[inline(always)] + pub fn coll(&mut self) -> COLL_W { + COLL_W { w: self } + } + #[doc = "Bit 2 - Received Not Acknowledge"] + #[inline(always)] + pub fn rxnack(&mut self) -> RXNACK_W { + RXNACK_W { w: self } + } + #[doc = "Bit 3 - Read/Write Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 4 - Repeated Start"] + #[inline(always)] + pub fn sr(&mut self) -> SR_W { + SR_W { w: self } + } + #[doc = "Bit 6 - SCL Low Timeout"] + #[inline(always)] + pub fn lowtout(&mut self) -> LOWTOUT_W { + LOWTOUT_W { w: self } + } + #[doc = "Bit 7 - Clock Hold"] + #[inline(always)] + pub fn clkhold(&mut self) -> CLKHOLD_W { + CLKHOLD_W { w: self } + } + #[doc = "Bit 9 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttout(&mut self) -> SEXTTOUT_W { + SEXTTOUT_W { w: self } + } + #[doc = "Bit 10 - High Speed"] + #[inline(always)] + pub fn hs(&mut self) -> HS_W { + HS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/sercom0/i2cs/syncbusy.rs b/pac/atsamc20e/src/sercom0/i2cs/syncbusy.rs new file mode 100644 index 000000000000..38e2509d9666 --- /dev/null +++ b/pac/atsamc20e/src/sercom0/i2cs/syncbusy.rs @@ -0,0 +1,73 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - SERCOM Enable Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM Enable Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +#[doc = "I2CS Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/sercom0/spim.rs b/pac/atsamc20e/src/sercom0/spim.rs new file mode 100644 index 000000000000..528e38e1b811 --- /dev/null +++ b/pac/atsamc20e/src/sercom0/spim.rs @@ -0,0 +1,44 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "SPIM Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "SPIM Control B"] +pub mod ctrlb; +#[doc = "BAUD register accessor: an alias for `Reg`"] +pub type BAUD = crate::Reg; +#[doc = "SPIM Baud Rate"] +pub mod baud; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "SPIM Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "SPIM Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "SPIM Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "SPIM Status"] +pub mod status; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "SPIM Synchronization Busy"] +pub mod syncbusy; +#[doc = "ADDR register accessor: an alias for `Reg`"] +pub type ADDR = crate::Reg; +#[doc = "SPIM Address"] +pub mod addr; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "SPIM Data"] +pub mod data; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "SPIM Debug Control"] +pub mod dbgctrl; diff --git a/pac/atsamc20e/src/sercom0/spim/addr.rs b/pac/atsamc20e/src/sercom0/spim/addr.rs new file mode 100644 index 000000000000..7c25cd522ea2 --- /dev/null +++ b/pac/atsamc20e/src/sercom0/spim/addr.rs @@ -0,0 +1,140 @@ +#[doc = "Register `ADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ADDR` reader - Address Value"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - Address Value"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +#[doc = "Field `ADDRMASK` reader - Address Mask"] +pub struct ADDRMASK_R(crate::FieldReader); +impl ADDRMASK_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ADDRMASK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDRMASK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDRMASK` writer - Address Mask"] +pub struct ADDRMASK_W<'a> { + w: &'a mut W, +} +impl<'a> ADDRMASK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Address Value"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 16:23 - Address Mask"] + #[inline(always)] + pub fn addrmask(&self) -> ADDRMASK_R { + ADDRMASK_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Address Value"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Bits 16:23 - Address Mask"] + #[inline(always)] + pub fn addrmask(&mut self) -> ADDRMASK_W { + ADDRMASK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [addr](index.html) module"] +pub struct ADDR_SPEC; +impl crate::RegisterSpec for ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [addr::R](R) reader structure"] +impl crate::Readable for ADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [addr::W](W) writer structure"] +impl crate::Writable for ADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ADDR to value 0"] +impl crate::Resettable for ADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/sercom0/spim/baud.rs b/pac/atsamc20e/src/sercom0/spim/baud.rs new file mode 100644 index 000000000000..6bec9ca74355 --- /dev/null +++ b/pac/atsamc20e/src/sercom0/spim/baud.rs @@ -0,0 +1,103 @@ +#[doc = "Register `BAUD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud](index.html) module"] +pub struct BAUD_SPEC; +impl crate::RegisterSpec for BAUD_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [baud::R](R) reader structure"] +impl crate::Readable for BAUD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud::W](W) writer structure"] +impl crate::Writable for BAUD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD to value 0"] +impl crate::Resettable for BAUD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/sercom0/spim/ctrla.rs b/pac/atsamc20e/src/sercom0/spim/ctrla.rs new file mode 100644 index 000000000000..44028f8cbdd7 --- /dev/null +++ b/pac/atsamc20e/src/sercom0/spim/ctrla.rs @@ -0,0 +1,992 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: USART with external clock"] + USART_EXT_CLK = 0, + #[doc = "1: USART with internal clock"] + USART_INT_CLK = 1, + #[doc = "2: SPI in slave operation"] + SPI_SLAVE = 2, + #[doc = "3: SPI in master operation"] + SPI_MASTER = 3, + #[doc = "4: I2C slave operation"] + I2C_SLAVE = 4, + #[doc = "5: I2C master operation"] + I2C_MASTER = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::USART_EXT_CLK), + 1 => Some(MODE_A::USART_INT_CLK), + 2 => Some(MODE_A::SPI_SLAVE), + 3 => Some(MODE_A::SPI_MASTER), + 4 => Some(MODE_A::I2C_SLAVE), + 5 => Some(MODE_A::I2C_MASTER), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_EXT_CLK`"] + #[inline(always)] + pub fn is_usart_ext_clk(&self) -> bool { + **self == MODE_A::USART_EXT_CLK + } + #[doc = "Checks if the value of the field is `USART_INT_CLK`"] + #[inline(always)] + pub fn is_usart_int_clk(&self) -> bool { + **self == MODE_A::USART_INT_CLK + } + #[doc = "Checks if the value of the field is `SPI_SLAVE`"] + #[inline(always)] + pub fn is_spi_slave(&self) -> bool { + **self == MODE_A::SPI_SLAVE + } + #[doc = "Checks if the value of the field is `SPI_MASTER`"] + #[inline(always)] + pub fn is_spi_master(&self) -> bool { + **self == MODE_A::SPI_MASTER + } + #[doc = "Checks if the value of the field is `I2C_SLAVE`"] + #[inline(always)] + pub fn is_i2c_slave(&self) -> bool { + **self == MODE_A::I2C_SLAVE + } + #[doc = "Checks if the value of the field is `I2C_MASTER`"] + #[inline(always)] + pub fn is_i2c_master(&self) -> bool { + **self == MODE_A::I2C_MASTER + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART with external clock"] + #[inline(always)] + pub fn usart_ext_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_EXT_CLK) + } + #[doc = "USART with internal clock"] + #[inline(always)] + pub fn usart_int_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_INT_CLK) + } + #[doc = "SPI in slave operation"] + #[inline(always)] + pub fn spi_slave(self) -> &'a mut W { + self.variant(MODE_A::SPI_SLAVE) + } + #[doc = "SPI in master operation"] + #[inline(always)] + pub fn spi_master(self) -> &'a mut W { + self.variant(MODE_A::SPI_MASTER) + } + #[doc = "I2C slave operation"] + #[inline(always)] + pub fn i2c_slave(self) -> &'a mut W { + self.variant(MODE_A::I2C_SLAVE) + } + #[doc = "I2C master operation"] + #[inline(always)] + pub fn i2c_master(self) -> &'a mut W { + self.variant(MODE_A::I2C_MASTER) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 2)) | ((value as u32 & 0x07) << 2); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `IBON` reader - Immediate Buffer Overflow Notification"] +pub struct IBON_R(crate::FieldReader); +impl IBON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IBON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IBON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IBON` writer - Immediate Buffer Overflow Notification"] +pub struct IBON_W<'a> { + w: &'a mut W, +} +impl<'a> IBON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Data Out Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DOPO_A { + #[doc = "0: DO on PAD\\[0\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + PAD0 = 0, + #[doc = "1: DO on PAD\\[2\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + PAD1 = 1, + #[doc = "2: DO on PAD\\[3\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + PAD2 = 2, + #[doc = "3: DO on PAD\\[0\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + PAD3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DOPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `DOPO` reader - Data Out Pinout"] +pub struct DOPO_R(crate::FieldReader); +impl DOPO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DOPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DOPO_A { + match self.bits { + 0 => DOPO_A::PAD0, + 1 => DOPO_A::PAD1, + 2 => DOPO_A::PAD2, + 3 => DOPO_A::PAD3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == DOPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD1`"] + #[inline(always)] + pub fn is_pad1(&self) -> bool { + **self == DOPO_A::PAD1 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == DOPO_A::PAD2 + } + #[doc = "Checks if the value of the field is `PAD3`"] + #[inline(always)] + pub fn is_pad3(&self) -> bool { + **self == DOPO_A::PAD3 + } +} +impl core::ops::Deref for DOPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DOPO` writer - Data Out Pinout"] +pub struct DOPO_W<'a> { + w: &'a mut W, +} +impl<'a> DOPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DOPO_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "DO on PAD\\[0\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(DOPO_A::PAD0) + } + #[doc = "DO on PAD\\[2\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + #[inline(always)] + pub fn pad1(self) -> &'a mut W { + self.variant(DOPO_A::PAD1) + } + #[doc = "DO on PAD\\[3\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(DOPO_A::PAD2) + } + #[doc = "DO on PAD\\[0\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + #[inline(always)] + pub fn pad3(self) -> &'a mut W { + self.variant(DOPO_A::PAD3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Data In Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DIPO_A { + #[doc = "0: SERCOM PAD\\[0\\]"] + PAD0 = 0, + #[doc = "1: SERCOM PAD\\[1\\]"] + PAD1 = 1, + #[doc = "2: SERCOM PAD\\[2\\]"] + PAD2 = 2, + #[doc = "3: SERCOM PAD\\[3\\]"] + PAD3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DIPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `DIPO` reader - Data In Pinout"] +pub struct DIPO_R(crate::FieldReader); +impl DIPO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DIPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DIPO_A { + match self.bits { + 0 => DIPO_A::PAD0, + 1 => DIPO_A::PAD1, + 2 => DIPO_A::PAD2, + 3 => DIPO_A::PAD3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == DIPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD1`"] + #[inline(always)] + pub fn is_pad1(&self) -> bool { + **self == DIPO_A::PAD1 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == DIPO_A::PAD2 + } + #[doc = "Checks if the value of the field is `PAD3`"] + #[inline(always)] + pub fn is_pad3(&self) -> bool { + **self == DIPO_A::PAD3 + } +} +impl core::ops::Deref for DIPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIPO` writer - Data In Pinout"] +pub struct DIPO_W<'a> { + w: &'a mut W, +} +impl<'a> DIPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DIPO_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "SERCOM PAD\\[0\\]"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(DIPO_A::PAD0) + } + #[doc = "SERCOM PAD\\[1\\]"] + #[inline(always)] + pub fn pad1(self) -> &'a mut W { + self.variant(DIPO_A::PAD1) + } + #[doc = "SERCOM PAD\\[2\\]"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(DIPO_A::PAD2) + } + #[doc = "SERCOM PAD\\[3\\]"] + #[inline(always)] + pub fn pad3(self) -> &'a mut W { + self.variant(DIPO_A::PAD3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 20)) | ((value as u32 & 0x03) << 20); + self.w + } +} +#[doc = "Frame Format\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FORM_A { + #[doc = "0: SPI Frame"] + SPI_FRAME = 0, + #[doc = "2: SPI Frame with Addr"] + SPI_FRAME_WITH_ADDR = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FORM_A) -> Self { + variant as _ + } +} +#[doc = "Field `FORM` reader - Frame Format"] +pub struct FORM_R(crate::FieldReader); +impl FORM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FORM_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(FORM_A::SPI_FRAME), + 2 => Some(FORM_A::SPI_FRAME_WITH_ADDR), + _ => None, + } + } + #[doc = "Checks if the value of the field is `SPI_FRAME`"] + #[inline(always)] + pub fn is_spi_frame(&self) -> bool { + **self == FORM_A::SPI_FRAME + } + #[doc = "Checks if the value of the field is `SPI_FRAME_WITH_ADDR`"] + #[inline(always)] + pub fn is_spi_frame_with_addr(&self) -> bool { + **self == FORM_A::SPI_FRAME_WITH_ADDR + } +} +impl core::ops::Deref for FORM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FORM` writer - Frame Format"] +pub struct FORM_W<'a> { + w: &'a mut W, +} +impl<'a> FORM_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FORM_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "SPI Frame"] + #[inline(always)] + pub fn spi_frame(self) -> &'a mut W { + self.variant(FORM_A::SPI_FRAME) + } + #[doc = "SPI Frame with Addr"] + #[inline(always)] + pub fn spi_frame_with_addr(self) -> &'a mut W { + self.variant(FORM_A::SPI_FRAME_WITH_ADDR) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Clock Phase\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CPHA_A { + #[doc = "0: The data is sampled on a leading SCK edge and changed on a trailing SCK edge"] + LEADING_EDGE = 0, + #[doc = "1: The data is sampled on a trailing SCK edge and changed on a leading SCK edge"] + TRAILING_EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CPHA_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CPHA` reader - Clock Phase"] +pub struct CPHA_R(crate::FieldReader); +impl CPHA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPHA_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CPHA_A { + match self.bits { + false => CPHA_A::LEADING_EDGE, + true => CPHA_A::TRAILING_EDGE, + } + } + #[doc = "Checks if the value of the field is `LEADING_EDGE`"] + #[inline(always)] + pub fn is_leading_edge(&self) -> bool { + **self == CPHA_A::LEADING_EDGE + } + #[doc = "Checks if the value of the field is `TRAILING_EDGE`"] + #[inline(always)] + pub fn is_trailing_edge(&self) -> bool { + **self == CPHA_A::TRAILING_EDGE + } +} +impl core::ops::Deref for CPHA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPHA` writer - Clock Phase"] +pub struct CPHA_W<'a> { + w: &'a mut W, +} +impl<'a> CPHA_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CPHA_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "The data is sampled on a leading SCK edge and changed on a trailing SCK edge"] + #[inline(always)] + pub fn leading_edge(self) -> &'a mut W { + self.variant(CPHA_A::LEADING_EDGE) + } + #[doc = "The data is sampled on a trailing SCK edge and changed on a leading SCK edge"] + #[inline(always)] + pub fn trailing_edge(self) -> &'a mut W { + self.variant(CPHA_A::TRAILING_EDGE) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Clock Polarity\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CPOL_A { + #[doc = "0: SCK is low when idle"] + IDLE_LOW = 0, + #[doc = "1: SCK is high when idle"] + IDLE_HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CPOL_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CPOL` reader - Clock Polarity"] +pub struct CPOL_R(crate::FieldReader); +impl CPOL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPOL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CPOL_A { + match self.bits { + false => CPOL_A::IDLE_LOW, + true => CPOL_A::IDLE_HIGH, + } + } + #[doc = "Checks if the value of the field is `IDLE_LOW`"] + #[inline(always)] + pub fn is_idle_low(&self) -> bool { + **self == CPOL_A::IDLE_LOW + } + #[doc = "Checks if the value of the field is `IDLE_HIGH`"] + #[inline(always)] + pub fn is_idle_high(&self) -> bool { + **self == CPOL_A::IDLE_HIGH + } +} +impl core::ops::Deref for CPOL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPOL` writer - Clock Polarity"] +pub struct CPOL_W<'a> { + w: &'a mut W, +} +impl<'a> CPOL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CPOL_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "SCK is low when idle"] + #[inline(always)] + pub fn idle_low(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_LOW) + } + #[doc = "SCK is high when idle"] + #[inline(always)] + pub fn idle_high(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_HIGH) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29); + self.w + } +} +#[doc = "Data Order\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum DORD_A { + #[doc = "0: MSB is transferred first"] + MSB = 0, + #[doc = "1: LSB is transferred first"] + LSB = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DORD_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DORD` reader - Data Order"] +pub struct DORD_R(crate::FieldReader); +impl DORD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DORD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DORD_A { + match self.bits { + false => DORD_A::MSB, + true => DORD_A::LSB, + } + } + #[doc = "Checks if the value of the field is `MSB`"] + #[inline(always)] + pub fn is_msb(&self) -> bool { + **self == DORD_A::MSB + } + #[doc = "Checks if the value of the field is `LSB`"] + #[inline(always)] + pub fn is_lsb(&self) -> bool { + **self == DORD_A::LSB + } +} +impl core::ops::Deref for DORD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DORD` writer - Data Order"] +pub struct DORD_W<'a> { + w: &'a mut W, +} +impl<'a> DORD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DORD_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "MSB is transferred first"] + #[inline(always)] + pub fn msb(self) -> &'a mut W { + self.variant(DORD_A::MSB) + } + #[doc = "LSB is transferred first"] + #[inline(always)] + pub fn lsb(self) -> &'a mut W { + self.variant(DORD_A::LSB) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x07) as u8) + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&self) -> IBON_R { + IBON_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bits 16:17 - Data Out Pinout"] + #[inline(always)] + pub fn dopo(&self) -> DOPO_R { + DOPO_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bits 20:21 - Data In Pinout"] + #[inline(always)] + pub fn dipo(&self) -> DIPO_R { + DIPO_R::new(((self.bits >> 20) & 0x03) as u8) + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&self) -> FORM_R { + FORM_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 28 - Clock Phase"] + #[inline(always)] + pub fn cpha(&self) -> CPHA_R { + CPHA_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&self) -> CPOL_R { + CPOL_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&self) -> DORD_R { + DORD_R::new(((self.bits >> 30) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&mut self) -> IBON_W { + IBON_W { w: self } + } + #[doc = "Bits 16:17 - Data Out Pinout"] + #[inline(always)] + pub fn dopo(&mut self) -> DOPO_W { + DOPO_W { w: self } + } + #[doc = "Bits 20:21 - Data In Pinout"] + #[inline(always)] + pub fn dipo(&mut self) -> DIPO_W { + DIPO_W { w: self } + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&mut self) -> FORM_W { + FORM_W { w: self } + } + #[doc = "Bit 28 - Clock Phase"] + #[inline(always)] + pub fn cpha(&mut self) -> CPHA_W { + CPHA_W { w: self } + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&mut self) -> CPOL_W { + CPOL_W { w: self } + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&mut self) -> DORD_W { + DORD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/sercom0/spim/ctrlb.rs b/pac/atsamc20e/src/sercom0/spim/ctrlb.rs new file mode 100644 index 000000000000..3d94f824ce83 --- /dev/null +++ b/pac/atsamc20e/src/sercom0/spim/ctrlb.rs @@ -0,0 +1,439 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Character Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CHSIZE_A { + #[doc = "0: 8 bits"] + _8_BIT = 0, + #[doc = "1: 9 bits"] + _9_BIT = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CHSIZE_A) -> Self { + variant as _ + } +} +#[doc = "Field `CHSIZE` reader - Character Size"] +pub struct CHSIZE_R(crate::FieldReader); +impl CHSIZE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CHSIZE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CHSIZE_A::_8_BIT), + 1 => Some(CHSIZE_A::_9_BIT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_8_BIT`"] + #[inline(always)] + pub fn is_8_bit(&self) -> bool { + **self == CHSIZE_A::_8_BIT + } + #[doc = "Checks if the value of the field is `_9_BIT`"] + #[inline(always)] + pub fn is_9_bit(&self) -> bool { + **self == CHSIZE_A::_9_BIT + } +} +impl core::ops::Deref for CHSIZE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHSIZE` writer - Character Size"] +pub struct CHSIZE_W<'a> { + w: &'a mut W, +} +impl<'a> CHSIZE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CHSIZE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8 bits"] + #[inline(always)] + pub fn _8_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_8_BIT) + } + #[doc = "9 bits"] + #[inline(always)] + pub fn _9_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_9_BIT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Field `PLOADEN` reader - Data Preload Enable"] +pub struct PLOADEN_R(crate::FieldReader); +impl PLOADEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PLOADEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PLOADEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PLOADEN` writer - Data Preload Enable"] +pub struct PLOADEN_W<'a> { + w: &'a mut W, +} +impl<'a> PLOADEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `SSDE` reader - Slave Select Low Detect Enable"] +pub struct SSDE_R(crate::FieldReader); +impl SSDE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SSDE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSDE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSDE` writer - Slave Select Low Detect Enable"] +pub struct SSDE_W<'a> { + w: &'a mut W, +} +impl<'a> SSDE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `MSSEN` reader - Master Slave Select Enable"] +pub struct MSSEN_R(crate::FieldReader); +impl MSSEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MSSEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MSSEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MSSEN` writer - Master Slave Select Enable"] +pub struct MSSEN_W<'a> { + w: &'a mut W, +} +impl<'a> MSSEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Address Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum AMODE_A { + #[doc = "0: SPI Address mask"] + MASK = 0, + #[doc = "1: Two unique Addressess"] + _2_ADDRESSES = 1, + #[doc = "2: Address Range"] + RANGE = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: AMODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `AMODE` reader - Address Mode"] +pub struct AMODE_R(crate::FieldReader); +impl AMODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + AMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(AMODE_A::MASK), + 1 => Some(AMODE_A::_2_ADDRESSES), + 2 => Some(AMODE_A::RANGE), + _ => None, + } + } + #[doc = "Checks if the value of the field is `MASK`"] + #[inline(always)] + pub fn is_mask(&self) -> bool { + **self == AMODE_A::MASK + } + #[doc = "Checks if the value of the field is `_2_ADDRESSES`"] + #[inline(always)] + pub fn is_2_addresses(&self) -> bool { + **self == AMODE_A::_2_ADDRESSES + } + #[doc = "Checks if the value of the field is `RANGE`"] + #[inline(always)] + pub fn is_range(&self) -> bool { + **self == AMODE_A::RANGE + } +} +impl core::ops::Deref for AMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AMODE` writer - Address Mode"] +pub struct AMODE_W<'a> { + w: &'a mut W, +} +impl<'a> AMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: AMODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "SPI Address mask"] + #[inline(always)] + pub fn mask(self) -> &'a mut W { + self.variant(AMODE_A::MASK) + } + #[doc = "Two unique Addressess"] + #[inline(always)] + pub fn _2_addresses(self) -> &'a mut W { + self.variant(AMODE_A::_2_ADDRESSES) + } + #[doc = "Address Range"] + #[inline(always)] + pub fn range(self) -> &'a mut W { + self.variant(AMODE_A::RANGE) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 14)) | ((value as u32 & 0x03) << 14); + self.w + } +} +#[doc = "Field `RXEN` reader - Receiver Enable"] +pub struct RXEN_R(crate::FieldReader); +impl RXEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXEN` writer - Receiver Enable"] +pub struct RXEN_W<'a> { + w: &'a mut W, +} +impl<'a> RXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&self) -> CHSIZE_R { + CHSIZE_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 6 - Data Preload Enable"] + #[inline(always)] + pub fn ploaden(&self) -> PLOADEN_R { + PLOADEN_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 9 - Slave Select Low Detect Enable"] + #[inline(always)] + pub fn ssde(&self) -> SSDE_R { + SSDE_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 13 - Master Slave Select Enable"] + #[inline(always)] + pub fn mssen(&self) -> MSSEN_R { + MSSEN_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bits 14:15 - Address Mode"] + #[inline(always)] + pub fn amode(&self) -> AMODE_R { + AMODE_R::new(((self.bits >> 14) & 0x03) as u8) + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&self) -> RXEN_R { + RXEN_R::new(((self.bits >> 17) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&mut self) -> CHSIZE_W { + CHSIZE_W { w: self } + } + #[doc = "Bit 6 - Data Preload Enable"] + #[inline(always)] + pub fn ploaden(&mut self) -> PLOADEN_W { + PLOADEN_W { w: self } + } + #[doc = "Bit 9 - Slave Select Low Detect Enable"] + #[inline(always)] + pub fn ssde(&mut self) -> SSDE_W { + SSDE_W { w: self } + } + #[doc = "Bit 13 - Master Slave Select Enable"] + #[inline(always)] + pub fn mssen(&mut self) -> MSSEN_W { + MSSEN_W { w: self } + } + #[doc = "Bits 14:15 - Address Mode"] + #[inline(always)] + pub fn amode(&mut self) -> AMODE_W { + AMODE_W { w: self } + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&mut self) -> RXEN_W { + RXEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/sercom0/spim/data.rs b/pac/atsamc20e/src/sercom0/spim/data.rs new file mode 100644 index 000000000000..dc9cd020d2a5 --- /dev/null +++ b/pac/atsamc20e/src/sercom0/spim/data.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data Value"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data Value"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01ff) | (value as u32 & 0x01ff); + self.w + } +} +impl R { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new((self.bits & 0x01ff) as u16) + } +} +impl W { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/sercom0/spim/dbgctrl.rs b/pac/atsamc20e/src/sercom0/spim/dbgctrl.rs new file mode 100644 index 000000000000..d9aa7495940c --- /dev/null +++ b/pac/atsamc20e/src/sercom0/spim/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGSTOP` reader - Debug Mode"] +pub struct DBGSTOP_R(crate::FieldReader); +impl DBGSTOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGSTOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGSTOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGSTOP` writer - Debug Mode"] +pub struct DBGSTOP_W<'a> { + w: &'a mut W, +} +impl<'a> DBGSTOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&self) -> DBGSTOP_R { + DBGSTOP_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&mut self) -> DBGSTOP_W { + DBGSTOP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/sercom0/spim/intenclr.rs b/pac/atsamc20e/src/sercom0/spim/intenclr.rs new file mode 100644 index 000000000000..ccab3de4348d --- /dev/null +++ b/pac/atsamc20e/src/sercom0/spim/intenclr.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Disable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Disable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Disable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Disable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Disable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Disable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SSL` reader - Slave Select Low Interrupt Disable"] +pub struct SSL_R(crate::FieldReader); +impl SSL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SSL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSL` writer - Slave Select Low Interrupt Disable"] +pub struct SSL_W<'a> { + w: &'a mut W, +} +impl<'a> SSL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Disable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Disable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Slave Select Low Interrupt Disable"] + #[inline(always)] + pub fn ssl(&self) -> SSL_R { + SSL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Slave Select Low Interrupt Disable"] + #[inline(always)] + pub fn ssl(&mut self) -> SSL_W { + SSL_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/sercom0/spim/intenset.rs b/pac/atsamc20e/src/sercom0/spim/intenset.rs new file mode 100644 index 000000000000..d9779cf897c2 --- /dev/null +++ b/pac/atsamc20e/src/sercom0/spim/intenset.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Enable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Enable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Enable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Enable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Enable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Enable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SSL` reader - Slave Select Low Interrupt Enable"] +pub struct SSL_R(crate::FieldReader); +impl SSL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SSL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSL` writer - Slave Select Low Interrupt Enable"] +pub struct SSL_W<'a> { + w: &'a mut W, +} +impl<'a> SSL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Slave Select Low Interrupt Enable"] + #[inline(always)] + pub fn ssl(&self) -> SSL_R { + SSL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Slave Select Low Interrupt Enable"] + #[inline(always)] + pub fn ssl(&mut self) -> SSL_W { + SSL_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/sercom0/spim/intflag.rs b/pac/atsamc20e/src/sercom0/spim/intflag.rs new file mode 100644 index 000000000000..e9bc10c271b8 --- /dev/null +++ b/pac/atsamc20e/src/sercom0/spim/intflag.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SSL` reader - Slave Select Low Interrupt Flag"] +pub struct SSL_R(crate::FieldReader); +impl SSL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SSL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSL` writer - Slave Select Low Interrupt Flag"] +pub struct SSL_W<'a> { + w: &'a mut W, +} +impl<'a> SSL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Slave Select Low Interrupt Flag"] + #[inline(always)] + pub fn ssl(&self) -> SSL_R { + SSL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Slave Select Low Interrupt Flag"] + #[inline(always)] + pub fn ssl(&mut self) -> SSL_W { + SSL_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/sercom0/spim/status.rs b/pac/atsamc20e/src/sercom0/spim/status.rs new file mode 100644 index 000000000000..9919460bf0e2 --- /dev/null +++ b/pac/atsamc20e/src/sercom0/spim/status.rs @@ -0,0 +1,113 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BUFOVF` reader - Buffer Overflow"] +pub struct BUFOVF_R(crate::FieldReader); +impl BUFOVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUFOVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUFOVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUFOVF` writer - Buffer Overflow"] +pub struct BUFOVF_W<'a> { + w: &'a mut W, +} +impl<'a> BUFOVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&self) -> BUFOVF_R { + BUFOVF_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&mut self) -> BUFOVF_W { + BUFOVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/sercom0/spim/syncbusy.rs b/pac/atsamc20e/src/sercom0/spim/syncbusy.rs new file mode 100644 index 000000000000..bee13adf7084 --- /dev/null +++ b/pac/atsamc20e/src/sercom0/spim/syncbusy.rs @@ -0,0 +1,93 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - SERCOM Enable Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLB` reader - CTRLB Synchronization Busy"] +pub struct CTRLB_R(crate::FieldReader); +impl CTRLB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM Enable Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - CTRLB Synchronization Busy"] + #[inline(always)] + pub fn ctrlb(&self) -> CTRLB_R { + CTRLB_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +#[doc = "SPIM Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/sercom0/spis.rs b/pac/atsamc20e/src/sercom0/spis.rs new file mode 100644 index 000000000000..eed10c90c460 --- /dev/null +++ b/pac/atsamc20e/src/sercom0/spis.rs @@ -0,0 +1,44 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "SPIS Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "SPIS Control B"] +pub mod ctrlb; +#[doc = "BAUD register accessor: an alias for `Reg`"] +pub type BAUD = crate::Reg; +#[doc = "SPIS Baud Rate"] +pub mod baud; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "SPIS Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "SPIS Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "SPIS Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "SPIS Status"] +pub mod status; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "SPIS Synchronization Busy"] +pub mod syncbusy; +#[doc = "ADDR register accessor: an alias for `Reg`"] +pub type ADDR = crate::Reg; +#[doc = "SPIS Address"] +pub mod addr; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "SPIS Data"] +pub mod data; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "SPIS Debug Control"] +pub mod dbgctrl; diff --git a/pac/atsamc20e/src/sercom0/spis/addr.rs b/pac/atsamc20e/src/sercom0/spis/addr.rs new file mode 100644 index 000000000000..5fca0a698bfe --- /dev/null +++ b/pac/atsamc20e/src/sercom0/spis/addr.rs @@ -0,0 +1,140 @@ +#[doc = "Register `ADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ADDR` reader - Address Value"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - Address Value"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +#[doc = "Field `ADDRMASK` reader - Address Mask"] +pub struct ADDRMASK_R(crate::FieldReader); +impl ADDRMASK_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ADDRMASK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDRMASK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDRMASK` writer - Address Mask"] +pub struct ADDRMASK_W<'a> { + w: &'a mut W, +} +impl<'a> ADDRMASK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Address Value"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 16:23 - Address Mask"] + #[inline(always)] + pub fn addrmask(&self) -> ADDRMASK_R { + ADDRMASK_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Address Value"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Bits 16:23 - Address Mask"] + #[inline(always)] + pub fn addrmask(&mut self) -> ADDRMASK_W { + ADDRMASK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [addr](index.html) module"] +pub struct ADDR_SPEC; +impl crate::RegisterSpec for ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [addr::R](R) reader structure"] +impl crate::Readable for ADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [addr::W](W) writer structure"] +impl crate::Writable for ADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ADDR to value 0"] +impl crate::Resettable for ADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/sercom0/spis/baud.rs b/pac/atsamc20e/src/sercom0/spis/baud.rs new file mode 100644 index 000000000000..eeee4cf633e5 --- /dev/null +++ b/pac/atsamc20e/src/sercom0/spis/baud.rs @@ -0,0 +1,103 @@ +#[doc = "Register `BAUD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud](index.html) module"] +pub struct BAUD_SPEC; +impl crate::RegisterSpec for BAUD_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [baud::R](R) reader structure"] +impl crate::Readable for BAUD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud::W](W) writer structure"] +impl crate::Writable for BAUD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD to value 0"] +impl crate::Resettable for BAUD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/sercom0/spis/ctrla.rs b/pac/atsamc20e/src/sercom0/spis/ctrla.rs new file mode 100644 index 000000000000..6151433a8529 --- /dev/null +++ b/pac/atsamc20e/src/sercom0/spis/ctrla.rs @@ -0,0 +1,992 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: USART with external clock"] + USART_EXT_CLK = 0, + #[doc = "1: USART with internal clock"] + USART_INT_CLK = 1, + #[doc = "2: SPI in slave operation"] + SPI_SLAVE = 2, + #[doc = "3: SPI in master operation"] + SPI_MASTER = 3, + #[doc = "4: I2C slave operation"] + I2C_SLAVE = 4, + #[doc = "5: I2C master operation"] + I2C_MASTER = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::USART_EXT_CLK), + 1 => Some(MODE_A::USART_INT_CLK), + 2 => Some(MODE_A::SPI_SLAVE), + 3 => Some(MODE_A::SPI_MASTER), + 4 => Some(MODE_A::I2C_SLAVE), + 5 => Some(MODE_A::I2C_MASTER), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_EXT_CLK`"] + #[inline(always)] + pub fn is_usart_ext_clk(&self) -> bool { + **self == MODE_A::USART_EXT_CLK + } + #[doc = "Checks if the value of the field is `USART_INT_CLK`"] + #[inline(always)] + pub fn is_usart_int_clk(&self) -> bool { + **self == MODE_A::USART_INT_CLK + } + #[doc = "Checks if the value of the field is `SPI_SLAVE`"] + #[inline(always)] + pub fn is_spi_slave(&self) -> bool { + **self == MODE_A::SPI_SLAVE + } + #[doc = "Checks if the value of the field is `SPI_MASTER`"] + #[inline(always)] + pub fn is_spi_master(&self) -> bool { + **self == MODE_A::SPI_MASTER + } + #[doc = "Checks if the value of the field is `I2C_SLAVE`"] + #[inline(always)] + pub fn is_i2c_slave(&self) -> bool { + **self == MODE_A::I2C_SLAVE + } + #[doc = "Checks if the value of the field is `I2C_MASTER`"] + #[inline(always)] + pub fn is_i2c_master(&self) -> bool { + **self == MODE_A::I2C_MASTER + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART with external clock"] + #[inline(always)] + pub fn usart_ext_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_EXT_CLK) + } + #[doc = "USART with internal clock"] + #[inline(always)] + pub fn usart_int_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_INT_CLK) + } + #[doc = "SPI in slave operation"] + #[inline(always)] + pub fn spi_slave(self) -> &'a mut W { + self.variant(MODE_A::SPI_SLAVE) + } + #[doc = "SPI in master operation"] + #[inline(always)] + pub fn spi_master(self) -> &'a mut W { + self.variant(MODE_A::SPI_MASTER) + } + #[doc = "I2C slave operation"] + #[inline(always)] + pub fn i2c_slave(self) -> &'a mut W { + self.variant(MODE_A::I2C_SLAVE) + } + #[doc = "I2C master operation"] + #[inline(always)] + pub fn i2c_master(self) -> &'a mut W { + self.variant(MODE_A::I2C_MASTER) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 2)) | ((value as u32 & 0x07) << 2); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `IBON` reader - Immediate Buffer Overflow Notification"] +pub struct IBON_R(crate::FieldReader); +impl IBON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IBON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IBON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IBON` writer - Immediate Buffer Overflow Notification"] +pub struct IBON_W<'a> { + w: &'a mut W, +} +impl<'a> IBON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Data Out Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DOPO_A { + #[doc = "0: DO on PAD\\[0\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + PAD0 = 0, + #[doc = "1: DO on PAD\\[2\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + PAD1 = 1, + #[doc = "2: DO on PAD\\[3\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + PAD2 = 2, + #[doc = "3: DO on PAD\\[0\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + PAD3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DOPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `DOPO` reader - Data Out Pinout"] +pub struct DOPO_R(crate::FieldReader); +impl DOPO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DOPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DOPO_A { + match self.bits { + 0 => DOPO_A::PAD0, + 1 => DOPO_A::PAD1, + 2 => DOPO_A::PAD2, + 3 => DOPO_A::PAD3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == DOPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD1`"] + #[inline(always)] + pub fn is_pad1(&self) -> bool { + **self == DOPO_A::PAD1 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == DOPO_A::PAD2 + } + #[doc = "Checks if the value of the field is `PAD3`"] + #[inline(always)] + pub fn is_pad3(&self) -> bool { + **self == DOPO_A::PAD3 + } +} +impl core::ops::Deref for DOPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DOPO` writer - Data Out Pinout"] +pub struct DOPO_W<'a> { + w: &'a mut W, +} +impl<'a> DOPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DOPO_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "DO on PAD\\[0\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(DOPO_A::PAD0) + } + #[doc = "DO on PAD\\[2\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + #[inline(always)] + pub fn pad1(self) -> &'a mut W { + self.variant(DOPO_A::PAD1) + } + #[doc = "DO on PAD\\[3\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(DOPO_A::PAD2) + } + #[doc = "DO on PAD\\[0\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + #[inline(always)] + pub fn pad3(self) -> &'a mut W { + self.variant(DOPO_A::PAD3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Data In Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DIPO_A { + #[doc = "0: SERCOM PAD\\[0\\]"] + PAD0 = 0, + #[doc = "1: SERCOM PAD\\[1\\]"] + PAD1 = 1, + #[doc = "2: SERCOM PAD\\[2\\]"] + PAD2 = 2, + #[doc = "3: SERCOM PAD\\[3\\]"] + PAD3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DIPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `DIPO` reader - Data In Pinout"] +pub struct DIPO_R(crate::FieldReader); +impl DIPO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DIPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DIPO_A { + match self.bits { + 0 => DIPO_A::PAD0, + 1 => DIPO_A::PAD1, + 2 => DIPO_A::PAD2, + 3 => DIPO_A::PAD3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == DIPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD1`"] + #[inline(always)] + pub fn is_pad1(&self) -> bool { + **self == DIPO_A::PAD1 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == DIPO_A::PAD2 + } + #[doc = "Checks if the value of the field is `PAD3`"] + #[inline(always)] + pub fn is_pad3(&self) -> bool { + **self == DIPO_A::PAD3 + } +} +impl core::ops::Deref for DIPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIPO` writer - Data In Pinout"] +pub struct DIPO_W<'a> { + w: &'a mut W, +} +impl<'a> DIPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DIPO_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "SERCOM PAD\\[0\\]"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(DIPO_A::PAD0) + } + #[doc = "SERCOM PAD\\[1\\]"] + #[inline(always)] + pub fn pad1(self) -> &'a mut W { + self.variant(DIPO_A::PAD1) + } + #[doc = "SERCOM PAD\\[2\\]"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(DIPO_A::PAD2) + } + #[doc = "SERCOM PAD\\[3\\]"] + #[inline(always)] + pub fn pad3(self) -> &'a mut W { + self.variant(DIPO_A::PAD3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 20)) | ((value as u32 & 0x03) << 20); + self.w + } +} +#[doc = "Frame Format\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FORM_A { + #[doc = "0: SPI Frame"] + SPI_FRAME = 0, + #[doc = "2: SPI Frame with Addr"] + SPI_FRAME_WITH_ADDR = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FORM_A) -> Self { + variant as _ + } +} +#[doc = "Field `FORM` reader - Frame Format"] +pub struct FORM_R(crate::FieldReader); +impl FORM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FORM_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(FORM_A::SPI_FRAME), + 2 => Some(FORM_A::SPI_FRAME_WITH_ADDR), + _ => None, + } + } + #[doc = "Checks if the value of the field is `SPI_FRAME`"] + #[inline(always)] + pub fn is_spi_frame(&self) -> bool { + **self == FORM_A::SPI_FRAME + } + #[doc = "Checks if the value of the field is `SPI_FRAME_WITH_ADDR`"] + #[inline(always)] + pub fn is_spi_frame_with_addr(&self) -> bool { + **self == FORM_A::SPI_FRAME_WITH_ADDR + } +} +impl core::ops::Deref for FORM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FORM` writer - Frame Format"] +pub struct FORM_W<'a> { + w: &'a mut W, +} +impl<'a> FORM_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FORM_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "SPI Frame"] + #[inline(always)] + pub fn spi_frame(self) -> &'a mut W { + self.variant(FORM_A::SPI_FRAME) + } + #[doc = "SPI Frame with Addr"] + #[inline(always)] + pub fn spi_frame_with_addr(self) -> &'a mut W { + self.variant(FORM_A::SPI_FRAME_WITH_ADDR) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Clock Phase\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CPHA_A { + #[doc = "0: The data is sampled on a leading SCK edge and changed on a trailing SCK edge"] + LEADING_EDGE = 0, + #[doc = "1: The data is sampled on a trailing SCK edge and changed on a leading SCK edge"] + TRAILING_EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CPHA_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CPHA` reader - Clock Phase"] +pub struct CPHA_R(crate::FieldReader); +impl CPHA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPHA_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CPHA_A { + match self.bits { + false => CPHA_A::LEADING_EDGE, + true => CPHA_A::TRAILING_EDGE, + } + } + #[doc = "Checks if the value of the field is `LEADING_EDGE`"] + #[inline(always)] + pub fn is_leading_edge(&self) -> bool { + **self == CPHA_A::LEADING_EDGE + } + #[doc = "Checks if the value of the field is `TRAILING_EDGE`"] + #[inline(always)] + pub fn is_trailing_edge(&self) -> bool { + **self == CPHA_A::TRAILING_EDGE + } +} +impl core::ops::Deref for CPHA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPHA` writer - Clock Phase"] +pub struct CPHA_W<'a> { + w: &'a mut W, +} +impl<'a> CPHA_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CPHA_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "The data is sampled on a leading SCK edge and changed on a trailing SCK edge"] + #[inline(always)] + pub fn leading_edge(self) -> &'a mut W { + self.variant(CPHA_A::LEADING_EDGE) + } + #[doc = "The data is sampled on a trailing SCK edge and changed on a leading SCK edge"] + #[inline(always)] + pub fn trailing_edge(self) -> &'a mut W { + self.variant(CPHA_A::TRAILING_EDGE) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Clock Polarity\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CPOL_A { + #[doc = "0: SCK is low when idle"] + IDLE_LOW = 0, + #[doc = "1: SCK is high when idle"] + IDLE_HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CPOL_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CPOL` reader - Clock Polarity"] +pub struct CPOL_R(crate::FieldReader); +impl CPOL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPOL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CPOL_A { + match self.bits { + false => CPOL_A::IDLE_LOW, + true => CPOL_A::IDLE_HIGH, + } + } + #[doc = "Checks if the value of the field is `IDLE_LOW`"] + #[inline(always)] + pub fn is_idle_low(&self) -> bool { + **self == CPOL_A::IDLE_LOW + } + #[doc = "Checks if the value of the field is `IDLE_HIGH`"] + #[inline(always)] + pub fn is_idle_high(&self) -> bool { + **self == CPOL_A::IDLE_HIGH + } +} +impl core::ops::Deref for CPOL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPOL` writer - Clock Polarity"] +pub struct CPOL_W<'a> { + w: &'a mut W, +} +impl<'a> CPOL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CPOL_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "SCK is low when idle"] + #[inline(always)] + pub fn idle_low(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_LOW) + } + #[doc = "SCK is high when idle"] + #[inline(always)] + pub fn idle_high(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_HIGH) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29); + self.w + } +} +#[doc = "Data Order\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum DORD_A { + #[doc = "0: MSB is transferred first"] + MSB = 0, + #[doc = "1: LSB is transferred first"] + LSB = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DORD_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DORD` reader - Data Order"] +pub struct DORD_R(crate::FieldReader); +impl DORD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DORD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DORD_A { + match self.bits { + false => DORD_A::MSB, + true => DORD_A::LSB, + } + } + #[doc = "Checks if the value of the field is `MSB`"] + #[inline(always)] + pub fn is_msb(&self) -> bool { + **self == DORD_A::MSB + } + #[doc = "Checks if the value of the field is `LSB`"] + #[inline(always)] + pub fn is_lsb(&self) -> bool { + **self == DORD_A::LSB + } +} +impl core::ops::Deref for DORD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DORD` writer - Data Order"] +pub struct DORD_W<'a> { + w: &'a mut W, +} +impl<'a> DORD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DORD_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "MSB is transferred first"] + #[inline(always)] + pub fn msb(self) -> &'a mut W { + self.variant(DORD_A::MSB) + } + #[doc = "LSB is transferred first"] + #[inline(always)] + pub fn lsb(self) -> &'a mut W { + self.variant(DORD_A::LSB) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x07) as u8) + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&self) -> IBON_R { + IBON_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bits 16:17 - Data Out Pinout"] + #[inline(always)] + pub fn dopo(&self) -> DOPO_R { + DOPO_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bits 20:21 - Data In Pinout"] + #[inline(always)] + pub fn dipo(&self) -> DIPO_R { + DIPO_R::new(((self.bits >> 20) & 0x03) as u8) + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&self) -> FORM_R { + FORM_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 28 - Clock Phase"] + #[inline(always)] + pub fn cpha(&self) -> CPHA_R { + CPHA_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&self) -> CPOL_R { + CPOL_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&self) -> DORD_R { + DORD_R::new(((self.bits >> 30) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&mut self) -> IBON_W { + IBON_W { w: self } + } + #[doc = "Bits 16:17 - Data Out Pinout"] + #[inline(always)] + pub fn dopo(&mut self) -> DOPO_W { + DOPO_W { w: self } + } + #[doc = "Bits 20:21 - Data In Pinout"] + #[inline(always)] + pub fn dipo(&mut self) -> DIPO_W { + DIPO_W { w: self } + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&mut self) -> FORM_W { + FORM_W { w: self } + } + #[doc = "Bit 28 - Clock Phase"] + #[inline(always)] + pub fn cpha(&mut self) -> CPHA_W { + CPHA_W { w: self } + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&mut self) -> CPOL_W { + CPOL_W { w: self } + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&mut self) -> DORD_W { + DORD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/sercom0/spis/ctrlb.rs b/pac/atsamc20e/src/sercom0/spis/ctrlb.rs new file mode 100644 index 000000000000..ccb70582cf34 --- /dev/null +++ b/pac/atsamc20e/src/sercom0/spis/ctrlb.rs @@ -0,0 +1,439 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Character Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CHSIZE_A { + #[doc = "0: 8 bits"] + _8_BIT = 0, + #[doc = "1: 9 bits"] + _9_BIT = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CHSIZE_A) -> Self { + variant as _ + } +} +#[doc = "Field `CHSIZE` reader - Character Size"] +pub struct CHSIZE_R(crate::FieldReader); +impl CHSIZE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CHSIZE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CHSIZE_A::_8_BIT), + 1 => Some(CHSIZE_A::_9_BIT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_8_BIT`"] + #[inline(always)] + pub fn is_8_bit(&self) -> bool { + **self == CHSIZE_A::_8_BIT + } + #[doc = "Checks if the value of the field is `_9_BIT`"] + #[inline(always)] + pub fn is_9_bit(&self) -> bool { + **self == CHSIZE_A::_9_BIT + } +} +impl core::ops::Deref for CHSIZE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHSIZE` writer - Character Size"] +pub struct CHSIZE_W<'a> { + w: &'a mut W, +} +impl<'a> CHSIZE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CHSIZE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8 bits"] + #[inline(always)] + pub fn _8_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_8_BIT) + } + #[doc = "9 bits"] + #[inline(always)] + pub fn _9_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_9_BIT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Field `PLOADEN` reader - Data Preload Enable"] +pub struct PLOADEN_R(crate::FieldReader); +impl PLOADEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PLOADEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PLOADEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PLOADEN` writer - Data Preload Enable"] +pub struct PLOADEN_W<'a> { + w: &'a mut W, +} +impl<'a> PLOADEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `SSDE` reader - Slave Select Low Detect Enable"] +pub struct SSDE_R(crate::FieldReader); +impl SSDE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SSDE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSDE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSDE` writer - Slave Select Low Detect Enable"] +pub struct SSDE_W<'a> { + w: &'a mut W, +} +impl<'a> SSDE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `MSSEN` reader - Master Slave Select Enable"] +pub struct MSSEN_R(crate::FieldReader); +impl MSSEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MSSEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MSSEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MSSEN` writer - Master Slave Select Enable"] +pub struct MSSEN_W<'a> { + w: &'a mut W, +} +impl<'a> MSSEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Address Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum AMODE_A { + #[doc = "0: SPI Address mask"] + MASK = 0, + #[doc = "1: Two unique Addressess"] + _2_ADDRESSES = 1, + #[doc = "2: Address Range"] + RANGE = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: AMODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `AMODE` reader - Address Mode"] +pub struct AMODE_R(crate::FieldReader); +impl AMODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + AMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(AMODE_A::MASK), + 1 => Some(AMODE_A::_2_ADDRESSES), + 2 => Some(AMODE_A::RANGE), + _ => None, + } + } + #[doc = "Checks if the value of the field is `MASK`"] + #[inline(always)] + pub fn is_mask(&self) -> bool { + **self == AMODE_A::MASK + } + #[doc = "Checks if the value of the field is `_2_ADDRESSES`"] + #[inline(always)] + pub fn is_2_addresses(&self) -> bool { + **self == AMODE_A::_2_ADDRESSES + } + #[doc = "Checks if the value of the field is `RANGE`"] + #[inline(always)] + pub fn is_range(&self) -> bool { + **self == AMODE_A::RANGE + } +} +impl core::ops::Deref for AMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AMODE` writer - Address Mode"] +pub struct AMODE_W<'a> { + w: &'a mut W, +} +impl<'a> AMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: AMODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "SPI Address mask"] + #[inline(always)] + pub fn mask(self) -> &'a mut W { + self.variant(AMODE_A::MASK) + } + #[doc = "Two unique Addressess"] + #[inline(always)] + pub fn _2_addresses(self) -> &'a mut W { + self.variant(AMODE_A::_2_ADDRESSES) + } + #[doc = "Address Range"] + #[inline(always)] + pub fn range(self) -> &'a mut W { + self.variant(AMODE_A::RANGE) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 14)) | ((value as u32 & 0x03) << 14); + self.w + } +} +#[doc = "Field `RXEN` reader - Receiver Enable"] +pub struct RXEN_R(crate::FieldReader); +impl RXEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXEN` writer - Receiver Enable"] +pub struct RXEN_W<'a> { + w: &'a mut W, +} +impl<'a> RXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&self) -> CHSIZE_R { + CHSIZE_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 6 - Data Preload Enable"] + #[inline(always)] + pub fn ploaden(&self) -> PLOADEN_R { + PLOADEN_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 9 - Slave Select Low Detect Enable"] + #[inline(always)] + pub fn ssde(&self) -> SSDE_R { + SSDE_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 13 - Master Slave Select Enable"] + #[inline(always)] + pub fn mssen(&self) -> MSSEN_R { + MSSEN_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bits 14:15 - Address Mode"] + #[inline(always)] + pub fn amode(&self) -> AMODE_R { + AMODE_R::new(((self.bits >> 14) & 0x03) as u8) + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&self) -> RXEN_R { + RXEN_R::new(((self.bits >> 17) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&mut self) -> CHSIZE_W { + CHSIZE_W { w: self } + } + #[doc = "Bit 6 - Data Preload Enable"] + #[inline(always)] + pub fn ploaden(&mut self) -> PLOADEN_W { + PLOADEN_W { w: self } + } + #[doc = "Bit 9 - Slave Select Low Detect Enable"] + #[inline(always)] + pub fn ssde(&mut self) -> SSDE_W { + SSDE_W { w: self } + } + #[doc = "Bit 13 - Master Slave Select Enable"] + #[inline(always)] + pub fn mssen(&mut self) -> MSSEN_W { + MSSEN_W { w: self } + } + #[doc = "Bits 14:15 - Address Mode"] + #[inline(always)] + pub fn amode(&mut self) -> AMODE_W { + AMODE_W { w: self } + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&mut self) -> RXEN_W { + RXEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/sercom0/spis/data.rs b/pac/atsamc20e/src/sercom0/spis/data.rs new file mode 100644 index 000000000000..4edf8089b29f --- /dev/null +++ b/pac/atsamc20e/src/sercom0/spis/data.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data Value"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data Value"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01ff) | (value as u32 & 0x01ff); + self.w + } +} +impl R { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new((self.bits & 0x01ff) as u16) + } +} +impl W { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/sercom0/spis/dbgctrl.rs b/pac/atsamc20e/src/sercom0/spis/dbgctrl.rs new file mode 100644 index 000000000000..ec36bbd26057 --- /dev/null +++ b/pac/atsamc20e/src/sercom0/spis/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGSTOP` reader - Debug Mode"] +pub struct DBGSTOP_R(crate::FieldReader); +impl DBGSTOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGSTOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGSTOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGSTOP` writer - Debug Mode"] +pub struct DBGSTOP_W<'a> { + w: &'a mut W, +} +impl<'a> DBGSTOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&self) -> DBGSTOP_R { + DBGSTOP_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&mut self) -> DBGSTOP_W { + DBGSTOP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/sercom0/spis/intenclr.rs b/pac/atsamc20e/src/sercom0/spis/intenclr.rs new file mode 100644 index 000000000000..e4c9ee0d506d --- /dev/null +++ b/pac/atsamc20e/src/sercom0/spis/intenclr.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Disable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Disable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Disable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Disable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Disable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Disable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SSL` reader - Slave Select Low Interrupt Disable"] +pub struct SSL_R(crate::FieldReader); +impl SSL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SSL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSL` writer - Slave Select Low Interrupt Disable"] +pub struct SSL_W<'a> { + w: &'a mut W, +} +impl<'a> SSL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Disable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Disable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Slave Select Low Interrupt Disable"] + #[inline(always)] + pub fn ssl(&self) -> SSL_R { + SSL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Slave Select Low Interrupt Disable"] + #[inline(always)] + pub fn ssl(&mut self) -> SSL_W { + SSL_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/sercom0/spis/intenset.rs b/pac/atsamc20e/src/sercom0/spis/intenset.rs new file mode 100644 index 000000000000..99582a624ebc --- /dev/null +++ b/pac/atsamc20e/src/sercom0/spis/intenset.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Enable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Enable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Enable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Enable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Enable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Enable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SSL` reader - Slave Select Low Interrupt Enable"] +pub struct SSL_R(crate::FieldReader); +impl SSL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SSL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSL` writer - Slave Select Low Interrupt Enable"] +pub struct SSL_W<'a> { + w: &'a mut W, +} +impl<'a> SSL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Slave Select Low Interrupt Enable"] + #[inline(always)] + pub fn ssl(&self) -> SSL_R { + SSL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Slave Select Low Interrupt Enable"] + #[inline(always)] + pub fn ssl(&mut self) -> SSL_W { + SSL_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/sercom0/spis/intflag.rs b/pac/atsamc20e/src/sercom0/spis/intflag.rs new file mode 100644 index 000000000000..589e73c2329f --- /dev/null +++ b/pac/atsamc20e/src/sercom0/spis/intflag.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SSL` reader - Slave Select Low Interrupt Flag"] +pub struct SSL_R(crate::FieldReader); +impl SSL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SSL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSL` writer - Slave Select Low Interrupt Flag"] +pub struct SSL_W<'a> { + w: &'a mut W, +} +impl<'a> SSL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Slave Select Low Interrupt Flag"] + #[inline(always)] + pub fn ssl(&self) -> SSL_R { + SSL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Slave Select Low Interrupt Flag"] + #[inline(always)] + pub fn ssl(&mut self) -> SSL_W { + SSL_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/sercom0/spis/status.rs b/pac/atsamc20e/src/sercom0/spis/status.rs new file mode 100644 index 000000000000..55c39c1a709f --- /dev/null +++ b/pac/atsamc20e/src/sercom0/spis/status.rs @@ -0,0 +1,113 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BUFOVF` reader - Buffer Overflow"] +pub struct BUFOVF_R(crate::FieldReader); +impl BUFOVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUFOVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUFOVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUFOVF` writer - Buffer Overflow"] +pub struct BUFOVF_W<'a> { + w: &'a mut W, +} +impl<'a> BUFOVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&self) -> BUFOVF_R { + BUFOVF_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&mut self) -> BUFOVF_W { + BUFOVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/sercom0/spis/syncbusy.rs b/pac/atsamc20e/src/sercom0/spis/syncbusy.rs new file mode 100644 index 000000000000..ac2f2e2c27ec --- /dev/null +++ b/pac/atsamc20e/src/sercom0/spis/syncbusy.rs @@ -0,0 +1,93 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - SERCOM Enable Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLB` reader - CTRLB Synchronization Busy"] +pub struct CTRLB_R(crate::FieldReader); +impl CTRLB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM Enable Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - CTRLB Synchronization Busy"] + #[inline(always)] + pub fn ctrlb(&self) -> CTRLB_R { + CTRLB_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +#[doc = "SPIS Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/sercom0/usart_ext.rs b/pac/atsamc20e/src/sercom0/usart_ext.rs new file mode 100644 index 000000000000..8c08b9efc1d5 --- /dev/null +++ b/pac/atsamc20e/src/sercom0/usart_ext.rs @@ -0,0 +1,60 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "USART_EXT Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "USART_EXT Control B"] +pub mod ctrlb; +#[doc = "CTRLC register accessor: an alias for `Reg`"] +pub type CTRLC = crate::Reg; +#[doc = "USART_EXT Control C"] +pub mod ctrlc; +#[doc = "BAUD register accessor: an alias for `Reg`"] +pub type BAUD = crate::Reg; +#[doc = "USART_EXT Baud Rate"] +pub mod baud; +#[doc = "BAUD_FRAC_MODE register accessor: an alias for `Reg`"] +pub type BAUD_FRAC_MODE = crate::Reg; +#[doc = "USART_EXT Baud Rate"] +pub mod baud_frac_mode; +#[doc = "BAUD_FRACFP_MODE register accessor: an alias for `Reg`"] +pub type BAUD_FRACFP_MODE = crate::Reg; +#[doc = "USART_EXT Baud Rate"] +pub mod baud_fracfp_mode; +#[doc = "BAUD_USARTFP_MODE register accessor: an alias for `Reg`"] +pub type BAUD_USARTFP_MODE = crate::Reg; +#[doc = "USART_EXT Baud Rate"] +pub mod baud_usartfp_mode; +#[doc = "RXPL register accessor: an alias for `Reg`"] +pub type RXPL = crate::Reg; +#[doc = "USART_EXT Receive Pulse Length"] +pub mod rxpl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "USART_EXT Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "USART_EXT Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "USART_EXT Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "USART_EXT Status"] +pub mod status; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "USART_EXT Synchronization Busy"] +pub mod syncbusy; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "USART_EXT Data"] +pub mod data; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "USART_EXT Debug Control"] +pub mod dbgctrl; diff --git a/pac/atsamc20e/src/sercom0/usart_ext/baud.rs b/pac/atsamc20e/src/sercom0/usart_ext/baud.rs new file mode 100644 index 000000000000..9558a8e1a52d --- /dev/null +++ b/pac/atsamc20e/src/sercom0/usart_ext/baud.rs @@ -0,0 +1,103 @@ +#[doc = "Register `BAUD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud](index.html) module"] +pub struct BAUD_SPEC; +impl crate::RegisterSpec for BAUD_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud::R](R) reader structure"] +impl crate::Readable for BAUD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud::W](W) writer structure"] +impl crate::Writable for BAUD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD to value 0"] +impl crate::Resettable for BAUD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/sercom0/usart_ext/baud_frac_mode.rs b/pac/atsamc20e/src/sercom0/usart_ext/baud_frac_mode.rs new file mode 100644 index 000000000000..d7cdd4570e26 --- /dev/null +++ b/pac/atsamc20e/src/sercom0/usart_ext/baud_frac_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `BAUD_FRAC_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD_FRAC_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1fff) | (value as u16 & 0x1fff); + self.w + } +} +#[doc = "Field `FP` reader - Fractional Part"] +pub struct FP_R(crate::FieldReader); +impl FP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FP` writer - Fractional Part"] +pub struct FP_W<'a> { + w: &'a mut W, +} +impl<'a> FP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 13)) | ((value as u16 & 0x07) << 13); + self.w + } +} +impl R { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new((self.bits & 0x1fff) as u16) + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&self) -> FP_R { + FP_R::new(((self.bits >> 13) & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&mut self) -> FP_W { + FP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud_frac_mode](index.html) module"] +pub struct BAUD_FRAC_MODE_SPEC; +impl crate::RegisterSpec for BAUD_FRAC_MODE_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud_frac_mode::R](R) reader structure"] +impl crate::Readable for BAUD_FRAC_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud_frac_mode::W](W) writer structure"] +impl crate::Writable for BAUD_FRAC_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD_FRAC_MODE to value 0"] +impl crate::Resettable for BAUD_FRAC_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/sercom0/usart_ext/baud_fracfp_mode.rs b/pac/atsamc20e/src/sercom0/usart_ext/baud_fracfp_mode.rs new file mode 100644 index 000000000000..c1dc50807677 --- /dev/null +++ b/pac/atsamc20e/src/sercom0/usart_ext/baud_fracfp_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `BAUD_FRACFP_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD_FRACFP_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1fff) | (value as u16 & 0x1fff); + self.w + } +} +#[doc = "Field `FP` reader - Fractional Part"] +pub struct FP_R(crate::FieldReader); +impl FP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FP` writer - Fractional Part"] +pub struct FP_W<'a> { + w: &'a mut W, +} +impl<'a> FP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 13)) | ((value as u16 & 0x07) << 13); + self.w + } +} +impl R { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new((self.bits & 0x1fff) as u16) + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&self) -> FP_R { + FP_R::new(((self.bits >> 13) & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&mut self) -> FP_W { + FP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud_fracfp_mode](index.html) module"] +pub struct BAUD_FRACFP_MODE_SPEC; +impl crate::RegisterSpec for BAUD_FRACFP_MODE_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud_fracfp_mode::R](R) reader structure"] +impl crate::Readable for BAUD_FRACFP_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud_fracfp_mode::W](W) writer structure"] +impl crate::Writable for BAUD_FRACFP_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD_FRACFP_MODE to value 0"] +impl crate::Resettable for BAUD_FRACFP_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/sercom0/usart_ext/baud_usartfp_mode.rs b/pac/atsamc20e/src/sercom0/usart_ext/baud_usartfp_mode.rs new file mode 100644 index 000000000000..8d4db16e0245 --- /dev/null +++ b/pac/atsamc20e/src/sercom0/usart_ext/baud_usartfp_mode.rs @@ -0,0 +1,103 @@ +#[doc = "Register `BAUD_USARTFP_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD_USARTFP_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud_usartfp_mode](index.html) module"] +pub struct BAUD_USARTFP_MODE_SPEC; +impl crate::RegisterSpec for BAUD_USARTFP_MODE_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud_usartfp_mode::R](R) reader structure"] +impl crate::Readable for BAUD_USARTFP_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud_usartfp_mode::W](W) writer structure"] +impl crate::Writable for BAUD_USARTFP_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD_USARTFP_MODE to value 0"] +impl crate::Resettable for BAUD_USARTFP_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/sercom0/usart_ext/ctrla.rs b/pac/atsamc20e/src/sercom0/usart_ext/ctrla.rs new file mode 100644 index 000000000000..535875ac8b25 --- /dev/null +++ b/pac/atsamc20e/src/sercom0/usart_ext/ctrla.rs @@ -0,0 +1,1171 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: USART with external clock"] + USART_EXT_CLK = 0, + #[doc = "1: USART with internal clock"] + USART_INT_CLK = 1, + #[doc = "2: SPI in slave operation"] + SPI_SLAVE = 2, + #[doc = "3: SPI in master operation"] + SPI_MASTER = 3, + #[doc = "4: I2C slave operation"] + I2C_SLAVE = 4, + #[doc = "5: I2C master operation"] + I2C_MASTER = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::USART_EXT_CLK), + 1 => Some(MODE_A::USART_INT_CLK), + 2 => Some(MODE_A::SPI_SLAVE), + 3 => Some(MODE_A::SPI_MASTER), + 4 => Some(MODE_A::I2C_SLAVE), + 5 => Some(MODE_A::I2C_MASTER), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_EXT_CLK`"] + #[inline(always)] + pub fn is_usart_ext_clk(&self) -> bool { + **self == MODE_A::USART_EXT_CLK + } + #[doc = "Checks if the value of the field is `USART_INT_CLK`"] + #[inline(always)] + pub fn is_usart_int_clk(&self) -> bool { + **self == MODE_A::USART_INT_CLK + } + #[doc = "Checks if the value of the field is `SPI_SLAVE`"] + #[inline(always)] + pub fn is_spi_slave(&self) -> bool { + **self == MODE_A::SPI_SLAVE + } + #[doc = "Checks if the value of the field is `SPI_MASTER`"] + #[inline(always)] + pub fn is_spi_master(&self) -> bool { + **self == MODE_A::SPI_MASTER + } + #[doc = "Checks if the value of the field is `I2C_SLAVE`"] + #[inline(always)] + pub fn is_i2c_slave(&self) -> bool { + **self == MODE_A::I2C_SLAVE + } + #[doc = "Checks if the value of the field is `I2C_MASTER`"] + #[inline(always)] + pub fn is_i2c_master(&self) -> bool { + **self == MODE_A::I2C_MASTER + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART with external clock"] + #[inline(always)] + pub fn usart_ext_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_EXT_CLK) + } + #[doc = "USART with internal clock"] + #[inline(always)] + pub fn usart_int_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_INT_CLK) + } + #[doc = "SPI in slave operation"] + #[inline(always)] + pub fn spi_slave(self) -> &'a mut W { + self.variant(MODE_A::SPI_SLAVE) + } + #[doc = "SPI in master operation"] + #[inline(always)] + pub fn spi_master(self) -> &'a mut W { + self.variant(MODE_A::SPI_MASTER) + } + #[doc = "I2C slave operation"] + #[inline(always)] + pub fn i2c_slave(self) -> &'a mut W { + self.variant(MODE_A::I2C_SLAVE) + } + #[doc = "I2C master operation"] + #[inline(always)] + pub fn i2c_master(self) -> &'a mut W { + self.variant(MODE_A::I2C_MASTER) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 2)) | ((value as u32 & 0x07) << 2); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `IBON` reader - Immediate Buffer Overflow Notification"] +pub struct IBON_R(crate::FieldReader); +impl IBON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IBON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IBON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IBON` writer - Immediate Buffer Overflow Notification"] +pub struct IBON_W<'a> { + w: &'a mut W, +} +impl<'a> IBON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Sample\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SAMPR_A { + #[doc = "0: 16x over-sampling using arithmetic baudrate generation"] + _16X_ARITHMETIC = 0, + #[doc = "1: 16x over-sampling using fractional baudrate generation"] + _16X_FRACTIONAL = 1, + #[doc = "2: 8x over-sampling using arithmetic baudrate generation"] + _8X_ARITHMETIC = 2, + #[doc = "3: 8x over-sampling using fractional baudrate generation"] + _8X_FRACTIONAL = 3, + #[doc = "4: 3x over-sampling using arithmetic baudrate generation"] + _3X_ARITHMETIC = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SAMPR_A) -> Self { + variant as _ + } +} +#[doc = "Field `SAMPR` reader - Sample"] +pub struct SAMPR_R(crate::FieldReader); +impl SAMPR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SAMPR_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SAMPR_A::_16X_ARITHMETIC), + 1 => Some(SAMPR_A::_16X_FRACTIONAL), + 2 => Some(SAMPR_A::_8X_ARITHMETIC), + 3 => Some(SAMPR_A::_8X_FRACTIONAL), + 4 => Some(SAMPR_A::_3X_ARITHMETIC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_16X_ARITHMETIC`"] + #[inline(always)] + pub fn is_16x_arithmetic(&self) -> bool { + **self == SAMPR_A::_16X_ARITHMETIC + } + #[doc = "Checks if the value of the field is `_16X_FRACTIONAL`"] + #[inline(always)] + pub fn is_16x_fractional(&self) -> bool { + **self == SAMPR_A::_16X_FRACTIONAL + } + #[doc = "Checks if the value of the field is `_8X_ARITHMETIC`"] + #[inline(always)] + pub fn is_8x_arithmetic(&self) -> bool { + **self == SAMPR_A::_8X_ARITHMETIC + } + #[doc = "Checks if the value of the field is `_8X_FRACTIONAL`"] + #[inline(always)] + pub fn is_8x_fractional(&self) -> bool { + **self == SAMPR_A::_8X_FRACTIONAL + } + #[doc = "Checks if the value of the field is `_3X_ARITHMETIC`"] + #[inline(always)] + pub fn is_3x_arithmetic(&self) -> bool { + **self == SAMPR_A::_3X_ARITHMETIC + } +} +impl core::ops::Deref for SAMPR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SAMPR` writer - Sample"] +pub struct SAMPR_W<'a> { + w: &'a mut W, +} +impl<'a> SAMPR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SAMPR_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "16x over-sampling using arithmetic baudrate generation"] + #[inline(always)] + pub fn _16x_arithmetic(self) -> &'a mut W { + self.variant(SAMPR_A::_16X_ARITHMETIC) + } + #[doc = "16x over-sampling using fractional baudrate generation"] + #[inline(always)] + pub fn _16x_fractional(self) -> &'a mut W { + self.variant(SAMPR_A::_16X_FRACTIONAL) + } + #[doc = "8x over-sampling using arithmetic baudrate generation"] + #[inline(always)] + pub fn _8x_arithmetic(self) -> &'a mut W { + self.variant(SAMPR_A::_8X_ARITHMETIC) + } + #[doc = "8x over-sampling using fractional baudrate generation"] + #[inline(always)] + pub fn _8x_fractional(self) -> &'a mut W { + self.variant(SAMPR_A::_8X_FRACTIONAL) + } + #[doc = "3x over-sampling using arithmetic baudrate generation"] + #[inline(always)] + pub fn _3x_arithmetic(self) -> &'a mut W { + self.variant(SAMPR_A::_3X_ARITHMETIC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 13)) | ((value as u32 & 0x07) << 13); + self.w + } +} +#[doc = "Transmit Data Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum TXPO_A { + #[doc = "0: SERCOM PAD\\[0\\] +is used for data transmission"] + PAD0 = 0, + #[doc = "1: SERCOM PAD\\[2\\] +is used for data transmission"] + PAD2 = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: TXPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `TXPO` reader - Transmit Data Pinout"] +pub struct TXPO_R(crate::FieldReader); +impl TXPO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TXPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(TXPO_A::PAD0), + 1 => Some(TXPO_A::PAD2), + _ => None, + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == TXPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == TXPO_A::PAD2 + } +} +impl core::ops::Deref for TXPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXPO` writer - Transmit Data Pinout"] +pub struct TXPO_W<'a> { + w: &'a mut W, +} +impl<'a> TXPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TXPO_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "SERCOM PAD\\[0\\] +is used for data transmission"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(TXPO_A::PAD0) + } + #[doc = "SERCOM PAD\\[2\\] +is used for data transmission"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(TXPO_A::PAD2) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Receive Data Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum RXPO_A { + #[doc = "0: SERCOM PAD\\[0\\] +is used for data reception"] + PAD0 = 0, + #[doc = "1: SERCOM PAD\\[1\\] +is used for data reception"] + PAD1 = 1, + #[doc = "2: SERCOM PAD\\[2\\] +is used for data reception"] + PAD2 = 2, + #[doc = "3: SERCOM PAD\\[3\\] +is used for data reception"] + PAD3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RXPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `RXPO` reader - Receive Data Pinout"] +pub struct RXPO_R(crate::FieldReader); +impl RXPO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RXPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RXPO_A { + match self.bits { + 0 => RXPO_A::PAD0, + 1 => RXPO_A::PAD1, + 2 => RXPO_A::PAD2, + 3 => RXPO_A::PAD3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == RXPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD1`"] + #[inline(always)] + pub fn is_pad1(&self) -> bool { + **self == RXPO_A::PAD1 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == RXPO_A::PAD2 + } + #[doc = "Checks if the value of the field is `PAD3`"] + #[inline(always)] + pub fn is_pad3(&self) -> bool { + **self == RXPO_A::PAD3 + } +} +impl core::ops::Deref for RXPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXPO` writer - Receive Data Pinout"] +pub struct RXPO_W<'a> { + w: &'a mut W, +} +impl<'a> RXPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RXPO_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "SERCOM PAD\\[0\\] +is used for data reception"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(RXPO_A::PAD0) + } + #[doc = "SERCOM PAD\\[1\\] +is used for data reception"] + #[inline(always)] + pub fn pad1(self) -> &'a mut W { + self.variant(RXPO_A::PAD1) + } + #[doc = "SERCOM PAD\\[2\\] +is used for data reception"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(RXPO_A::PAD2) + } + #[doc = "SERCOM PAD\\[3\\] +is used for data reception"] + #[inline(always)] + pub fn pad3(self) -> &'a mut W { + self.variant(RXPO_A::PAD3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 20)) | ((value as u32 & 0x03) << 20); + self.w + } +} +#[doc = "Field `SAMPA` reader - Sample Adjustment"] +pub struct SAMPA_R(crate::FieldReader); +impl SAMPA_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SAMPA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SAMPA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SAMPA` writer - Sample Adjustment"] +pub struct SAMPA_W<'a> { + w: &'a mut W, +} +impl<'a> SAMPA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 22)) | ((value as u32 & 0x03) << 22); + self.w + } +} +#[doc = "Frame Format\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FORM_A { + #[doc = "0: USART frame"] + USART_FRAME_NO_PARITY = 0, + #[doc = "1: USART frame with parity"] + USART_FRAME_WITH_PARITY = 1, + #[doc = "2: LIN Master - Break and sync generation"] + USART_FRAME_LIN_MASTER_MODE = 2, + #[doc = "4: Auto-baud - break detection and auto-baud"] + USART_FRAME_AUTO_BAUD_NO_PARITY = 4, + #[doc = "5: Auto-baud - break detection and auto-baud with parity"] + USART_FRAME_AUTO_BAUD_WITH_PARITY = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FORM_A) -> Self { + variant as _ + } +} +#[doc = "Field `FORM` reader - Frame Format"] +pub struct FORM_R(crate::FieldReader); +impl FORM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FORM_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(FORM_A::USART_FRAME_NO_PARITY), + 1 => Some(FORM_A::USART_FRAME_WITH_PARITY), + 2 => Some(FORM_A::USART_FRAME_LIN_MASTER_MODE), + 4 => Some(FORM_A::USART_FRAME_AUTO_BAUD_NO_PARITY), + 5 => Some(FORM_A::USART_FRAME_AUTO_BAUD_WITH_PARITY), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_FRAME_NO_PARITY`"] + #[inline(always)] + pub fn is_usart_frame_no_parity(&self) -> bool { + **self == FORM_A::USART_FRAME_NO_PARITY + } + #[doc = "Checks if the value of the field is `USART_FRAME_WITH_PARITY`"] + #[inline(always)] + pub fn is_usart_frame_with_parity(&self) -> bool { + **self == FORM_A::USART_FRAME_WITH_PARITY + } + #[doc = "Checks if the value of the field is `USART_FRAME_LIN_MASTER_MODE`"] + #[inline(always)] + pub fn is_usart_frame_lin_master_mode(&self) -> bool { + **self == FORM_A::USART_FRAME_LIN_MASTER_MODE + } + #[doc = "Checks if the value of the field is `USART_FRAME_AUTO_BAUD_NO_PARITY`"] + #[inline(always)] + pub fn is_usart_frame_auto_baud_no_parity(&self) -> bool { + **self == FORM_A::USART_FRAME_AUTO_BAUD_NO_PARITY + } + #[doc = "Checks if the value of the field is `USART_FRAME_AUTO_BAUD_WITH_PARITY`"] + #[inline(always)] + pub fn is_usart_frame_auto_baud_with_parity(&self) -> bool { + **self == FORM_A::USART_FRAME_AUTO_BAUD_WITH_PARITY + } +} +impl core::ops::Deref for FORM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FORM` writer - Frame Format"] +pub struct FORM_W<'a> { + w: &'a mut W, +} +impl<'a> FORM_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FORM_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART frame"] + #[inline(always)] + pub fn usart_frame_no_parity(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_NO_PARITY) + } + #[doc = "USART frame with parity"] + #[inline(always)] + pub fn usart_frame_with_parity(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_WITH_PARITY) + } + #[doc = "LIN Master - Break and sync generation"] + #[inline(always)] + pub fn usart_frame_lin_master_mode(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_LIN_MASTER_MODE) + } + #[doc = "Auto-baud - break detection and auto-baud"] + #[inline(always)] + pub fn usart_frame_auto_baud_no_parity(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_AUTO_BAUD_NO_PARITY) + } + #[doc = "Auto-baud - break detection and auto-baud with parity"] + #[inline(always)] + pub fn usart_frame_auto_baud_with_parity(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_AUTO_BAUD_WITH_PARITY) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Communication Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CMODE_A { + #[doc = "0: Asynchronous Communication"] + ASYNC = 0, + #[doc = "1: Synchronous Communication"] + SYNC = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CMODE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CMODE` reader - Communication Mode"] +pub struct CMODE_R(crate::FieldReader); +impl CMODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CMODE_A { + match self.bits { + false => CMODE_A::ASYNC, + true => CMODE_A::SYNC, + } + } + #[doc = "Checks if the value of the field is `ASYNC`"] + #[inline(always)] + pub fn is_async(&self) -> bool { + **self == CMODE_A::ASYNC + } + #[doc = "Checks if the value of the field is `SYNC`"] + #[inline(always)] + pub fn is_sync(&self) -> bool { + **self == CMODE_A::SYNC + } +} +impl core::ops::Deref for CMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMODE` writer - Communication Mode"] +pub struct CMODE_W<'a> { + w: &'a mut W, +} +impl<'a> CMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMODE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Asynchronous Communication"] + #[inline(always)] + pub fn async_(self) -> &'a mut W { + self.variant(CMODE_A::ASYNC) + } + #[doc = "Synchronous Communication"] + #[inline(always)] + pub fn sync(self) -> &'a mut W { + self.variant(CMODE_A::SYNC) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Clock Polarity\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CPOL_A { + #[doc = "0: TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge"] + IDLE_LOW = 0, + #[doc = "1: TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge"] + IDLE_HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CPOL_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CPOL` reader - Clock Polarity"] +pub struct CPOL_R(crate::FieldReader); +impl CPOL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPOL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CPOL_A { + match self.bits { + false => CPOL_A::IDLE_LOW, + true => CPOL_A::IDLE_HIGH, + } + } + #[doc = "Checks if the value of the field is `IDLE_LOW`"] + #[inline(always)] + pub fn is_idle_low(&self) -> bool { + **self == CPOL_A::IDLE_LOW + } + #[doc = "Checks if the value of the field is `IDLE_HIGH`"] + #[inline(always)] + pub fn is_idle_high(&self) -> bool { + **self == CPOL_A::IDLE_HIGH + } +} +impl core::ops::Deref for CPOL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPOL` writer - Clock Polarity"] +pub struct CPOL_W<'a> { + w: &'a mut W, +} +impl<'a> CPOL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CPOL_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge"] + #[inline(always)] + pub fn idle_low(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_LOW) + } + #[doc = "TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge"] + #[inline(always)] + pub fn idle_high(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_HIGH) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29); + self.w + } +} +#[doc = "Data Order\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum DORD_A { + #[doc = "0: MSB is transmitted first"] + MSB = 0, + #[doc = "1: LSB is transmitted first"] + LSB = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DORD_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DORD` reader - Data Order"] +pub struct DORD_R(crate::FieldReader); +impl DORD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DORD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DORD_A { + match self.bits { + false => DORD_A::MSB, + true => DORD_A::LSB, + } + } + #[doc = "Checks if the value of the field is `MSB`"] + #[inline(always)] + pub fn is_msb(&self) -> bool { + **self == DORD_A::MSB + } + #[doc = "Checks if the value of the field is `LSB`"] + #[inline(always)] + pub fn is_lsb(&self) -> bool { + **self == DORD_A::LSB + } +} +impl core::ops::Deref for DORD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DORD` writer - Data Order"] +pub struct DORD_W<'a> { + w: &'a mut W, +} +impl<'a> DORD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DORD_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "MSB is transmitted first"] + #[inline(always)] + pub fn msb(self) -> &'a mut W { + self.variant(DORD_A::MSB) + } + #[doc = "LSB is transmitted first"] + #[inline(always)] + pub fn lsb(self) -> &'a mut W { + self.variant(DORD_A::LSB) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x07) as u8) + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&self) -> IBON_R { + IBON_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bits 13:15 - Sample"] + #[inline(always)] + pub fn sampr(&self) -> SAMPR_R { + SAMPR_R::new(((self.bits >> 13) & 0x07) as u8) + } + #[doc = "Bits 16:17 - Transmit Data Pinout"] + #[inline(always)] + pub fn txpo(&self) -> TXPO_R { + TXPO_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bits 20:21 - Receive Data Pinout"] + #[inline(always)] + pub fn rxpo(&self) -> RXPO_R { + RXPO_R::new(((self.bits >> 20) & 0x03) as u8) + } + #[doc = "Bits 22:23 - Sample Adjustment"] + #[inline(always)] + pub fn sampa(&self) -> SAMPA_R { + SAMPA_R::new(((self.bits >> 22) & 0x03) as u8) + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&self) -> FORM_R { + FORM_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 28 - Communication Mode"] + #[inline(always)] + pub fn cmode(&self) -> CMODE_R { + CMODE_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&self) -> CPOL_R { + CPOL_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&self) -> DORD_R { + DORD_R::new(((self.bits >> 30) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&mut self) -> IBON_W { + IBON_W { w: self } + } + #[doc = "Bits 13:15 - Sample"] + #[inline(always)] + pub fn sampr(&mut self) -> SAMPR_W { + SAMPR_W { w: self } + } + #[doc = "Bits 16:17 - Transmit Data Pinout"] + #[inline(always)] + pub fn txpo(&mut self) -> TXPO_W { + TXPO_W { w: self } + } + #[doc = "Bits 20:21 - Receive Data Pinout"] + #[inline(always)] + pub fn rxpo(&mut self) -> RXPO_W { + RXPO_W { w: self } + } + #[doc = "Bits 22:23 - Sample Adjustment"] + #[inline(always)] + pub fn sampa(&mut self) -> SAMPA_W { + SAMPA_W { w: self } + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&mut self) -> FORM_W { + FORM_W { w: self } + } + #[doc = "Bit 28 - Communication Mode"] + #[inline(always)] + pub fn cmode(&mut self) -> CMODE_W { + CMODE_W { w: self } + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&mut self) -> CPOL_W { + CPOL_W { w: self } + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&mut self) -> DORD_W { + DORD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/sercom0/usart_ext/ctrlb.rs b/pac/atsamc20e/src/sercom0/usart_ext/ctrlb.rs new file mode 100644 index 000000000000..37567555e842 --- /dev/null +++ b/pac/atsamc20e/src/sercom0/usart_ext/ctrlb.rs @@ -0,0 +1,651 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Character Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CHSIZE_A { + #[doc = "0: 8 Bits"] + _8_BIT = 0, + #[doc = "1: 9 Bits"] + _9_BIT = 1, + #[doc = "5: 5 Bits"] + _5_BIT = 5, + #[doc = "6: 6 Bits"] + _6_BIT = 6, + #[doc = "7: 7 Bits"] + _7_BIT = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CHSIZE_A) -> Self { + variant as _ + } +} +#[doc = "Field `CHSIZE` reader - Character Size"] +pub struct CHSIZE_R(crate::FieldReader); +impl CHSIZE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CHSIZE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CHSIZE_A::_8_BIT), + 1 => Some(CHSIZE_A::_9_BIT), + 5 => Some(CHSIZE_A::_5_BIT), + 6 => Some(CHSIZE_A::_6_BIT), + 7 => Some(CHSIZE_A::_7_BIT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_8_BIT`"] + #[inline(always)] + pub fn is_8_bit(&self) -> bool { + **self == CHSIZE_A::_8_BIT + } + #[doc = "Checks if the value of the field is `_9_BIT`"] + #[inline(always)] + pub fn is_9_bit(&self) -> bool { + **self == CHSIZE_A::_9_BIT + } + #[doc = "Checks if the value of the field is `_5_BIT`"] + #[inline(always)] + pub fn is_5_bit(&self) -> bool { + **self == CHSIZE_A::_5_BIT + } + #[doc = "Checks if the value of the field is `_6_BIT`"] + #[inline(always)] + pub fn is_6_bit(&self) -> bool { + **self == CHSIZE_A::_6_BIT + } + #[doc = "Checks if the value of the field is `_7_BIT`"] + #[inline(always)] + pub fn is_7_bit(&self) -> bool { + **self == CHSIZE_A::_7_BIT + } +} +impl core::ops::Deref for CHSIZE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHSIZE` writer - Character Size"] +pub struct CHSIZE_W<'a> { + w: &'a mut W, +} +impl<'a> CHSIZE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CHSIZE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8 Bits"] + #[inline(always)] + pub fn _8_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_8_BIT) + } + #[doc = "9 Bits"] + #[inline(always)] + pub fn _9_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_9_BIT) + } + #[doc = "5 Bits"] + #[inline(always)] + pub fn _5_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_5_BIT) + } + #[doc = "6 Bits"] + #[inline(always)] + pub fn _6_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_6_BIT) + } + #[doc = "7 Bits"] + #[inline(always)] + pub fn _7_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_7_BIT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Stop Bit Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SBMODE_A { + #[doc = "0: One Stop Bit"] + _1_BIT = 0, + #[doc = "1: Two Stop Bits"] + _2_BIT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SBMODE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SBMODE` reader - Stop Bit Mode"] +pub struct SBMODE_R(crate::FieldReader); +impl SBMODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SBMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SBMODE_A { + match self.bits { + false => SBMODE_A::_1_BIT, + true => SBMODE_A::_2_BIT, + } + } + #[doc = "Checks if the value of the field is `_1_BIT`"] + #[inline(always)] + pub fn is_1_bit(&self) -> bool { + **self == SBMODE_A::_1_BIT + } + #[doc = "Checks if the value of the field is `_2_BIT`"] + #[inline(always)] + pub fn is_2_bit(&self) -> bool { + **self == SBMODE_A::_2_BIT + } +} +impl core::ops::Deref for SBMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SBMODE` writer - Stop Bit Mode"] +pub struct SBMODE_W<'a> { + w: &'a mut W, +} +impl<'a> SBMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SBMODE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "One Stop Bit"] + #[inline(always)] + pub fn _1_bit(self) -> &'a mut W { + self.variant(SBMODE_A::_1_BIT) + } + #[doc = "Two Stop Bits"] + #[inline(always)] + pub fn _2_bit(self) -> &'a mut W { + self.variant(SBMODE_A::_2_BIT) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `COLDEN` reader - Collision Detection Enable"] +pub struct COLDEN_R(crate::FieldReader); +impl COLDEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COLDEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COLDEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COLDEN` writer - Collision Detection Enable"] +pub struct COLDEN_W<'a> { + w: &'a mut W, +} +impl<'a> COLDEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `SFDE` reader - Start of Frame Detection Enable"] +pub struct SFDE_R(crate::FieldReader); +impl SFDE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SFDE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SFDE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SFDE` writer - Start of Frame Detection Enable"] +pub struct SFDE_W<'a> { + w: &'a mut W, +} +impl<'a> SFDE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `ENC` reader - Encoding Format"] +pub struct ENC_R(crate::FieldReader); +impl ENC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENC` writer - Encoding Format"] +pub struct ENC_W<'a> { + w: &'a mut W, +} +impl<'a> ENC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Parity Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PMODE_A { + #[doc = "0: Even Parity"] + EVEN = 0, + #[doc = "1: Odd Parity"] + ODD = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PMODE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PMODE` reader - Parity Mode"] +pub struct PMODE_R(crate::FieldReader); +impl PMODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PMODE_A { + match self.bits { + false => PMODE_A::EVEN, + true => PMODE_A::ODD, + } + } + #[doc = "Checks if the value of the field is `EVEN`"] + #[inline(always)] + pub fn is_even(&self) -> bool { + **self == PMODE_A::EVEN + } + #[doc = "Checks if the value of the field is `ODD`"] + #[inline(always)] + pub fn is_odd(&self) -> bool { + **self == PMODE_A::ODD + } +} +impl core::ops::Deref for PMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PMODE` writer - Parity Mode"] +pub struct PMODE_W<'a> { + w: &'a mut W, +} +impl<'a> PMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PMODE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Even Parity"] + #[inline(always)] + pub fn even(self) -> &'a mut W { + self.variant(PMODE_A::EVEN) + } + #[doc = "Odd Parity"] + #[inline(always)] + pub fn odd(self) -> &'a mut W { + self.variant(PMODE_A::ODD) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `TXEN` reader - Transmitter Enable"] +pub struct TXEN_R(crate::FieldReader); +impl TXEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXEN` writer - Transmitter Enable"] +pub struct TXEN_W<'a> { + w: &'a mut W, +} +impl<'a> TXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `RXEN` reader - Receiver Enable"] +pub struct RXEN_R(crate::FieldReader); +impl RXEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXEN` writer - Receiver Enable"] +pub struct RXEN_W<'a> { + w: &'a mut W, +} +impl<'a> RXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `LINCMD` reader - LIN Command"] +pub struct LINCMD_R(crate::FieldReader); +impl LINCMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LINCMD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LINCMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LINCMD` writer - LIN Command"] +pub struct LINCMD_W<'a> { + w: &'a mut W, +} +impl<'a> LINCMD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 24)) | ((value as u32 & 0x03) << 24); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&self) -> CHSIZE_R { + CHSIZE_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 6 - Stop Bit Mode"] + #[inline(always)] + pub fn sbmode(&self) -> SBMODE_R { + SBMODE_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 8 - Collision Detection Enable"] + #[inline(always)] + pub fn colden(&self) -> COLDEN_R { + COLDEN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Start of Frame Detection Enable"] + #[inline(always)] + pub fn sfde(&self) -> SFDE_R { + SFDE_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Encoding Format"] + #[inline(always)] + pub fn enc(&self) -> ENC_R { + ENC_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 13 - Parity Mode"] + #[inline(always)] + pub fn pmode(&self) -> PMODE_R { + PMODE_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 16 - Transmitter Enable"] + #[inline(always)] + pub fn txen(&self) -> TXEN_R { + TXEN_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&self) -> RXEN_R { + RXEN_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bits 24:25 - LIN Command"] + #[inline(always)] + pub fn lincmd(&self) -> LINCMD_R { + LINCMD_R::new(((self.bits >> 24) & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&mut self) -> CHSIZE_W { + CHSIZE_W { w: self } + } + #[doc = "Bit 6 - Stop Bit Mode"] + #[inline(always)] + pub fn sbmode(&mut self) -> SBMODE_W { + SBMODE_W { w: self } + } + #[doc = "Bit 8 - Collision Detection Enable"] + #[inline(always)] + pub fn colden(&mut self) -> COLDEN_W { + COLDEN_W { w: self } + } + #[doc = "Bit 9 - Start of Frame Detection Enable"] + #[inline(always)] + pub fn sfde(&mut self) -> SFDE_W { + SFDE_W { w: self } + } + #[doc = "Bit 10 - Encoding Format"] + #[inline(always)] + pub fn enc(&mut self) -> ENC_W { + ENC_W { w: self } + } + #[doc = "Bit 13 - Parity Mode"] + #[inline(always)] + pub fn pmode(&mut self) -> PMODE_W { + PMODE_W { w: self } + } + #[doc = "Bit 16 - Transmitter Enable"] + #[inline(always)] + pub fn txen(&mut self) -> TXEN_W { + TXEN_W { w: self } + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&mut self) -> RXEN_W { + RXEN_W { w: self } + } + #[doc = "Bits 24:25 - LIN Command"] + #[inline(always)] + pub fn lincmd(&mut self) -> LINCMD_W { + LINCMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/sercom0/usart_ext/ctrlc.rs b/pac/atsamc20e/src/sercom0/usart_ext/ctrlc.rs new file mode 100644 index 000000000000..5840d5c3bd06 --- /dev/null +++ b/pac/atsamc20e/src/sercom0/usart_ext/ctrlc.rs @@ -0,0 +1,177 @@ +#[doc = "Register `CTRLC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `GTIME` reader - RS485 Guard Time"] +pub struct GTIME_R(crate::FieldReader); +impl GTIME_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + GTIME_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GTIME_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GTIME` writer - RS485 Guard Time"] +pub struct GTIME_W<'a> { + w: &'a mut W, +} +impl<'a> GTIME_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Field `BRKLEN` reader - LIN Master Break Length"] +pub struct BRKLEN_R(crate::FieldReader); +impl BRKLEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BRKLEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BRKLEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BRKLEN` writer - LIN Master Break Length"] +pub struct BRKLEN_W<'a> { + w: &'a mut W, +} +impl<'a> BRKLEN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 8)) | ((value as u32 & 0x03) << 8); + self.w + } +} +#[doc = "Field `HDRDLY` reader - LIN Master Header Delay"] +pub struct HDRDLY_R(crate::FieldReader); +impl HDRDLY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + HDRDLY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HDRDLY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HDRDLY` writer - LIN Master Header Delay"] +pub struct HDRDLY_W<'a> { + w: &'a mut W, +} +impl<'a> HDRDLY_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 10)) | ((value as u32 & 0x03) << 10); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - RS485 Guard Time"] + #[inline(always)] + pub fn gtime(&self) -> GTIME_R { + GTIME_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bits 8:9 - LIN Master Break Length"] + #[inline(always)] + pub fn brklen(&self) -> BRKLEN_R { + BRKLEN_R::new(((self.bits >> 8) & 0x03) as u8) + } + #[doc = "Bits 10:11 - LIN Master Header Delay"] + #[inline(always)] + pub fn hdrdly(&self) -> HDRDLY_R { + HDRDLY_R::new(((self.bits >> 10) & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - RS485 Guard Time"] + #[inline(always)] + pub fn gtime(&mut self) -> GTIME_W { + GTIME_W { w: self } + } + #[doc = "Bits 8:9 - LIN Master Break Length"] + #[inline(always)] + pub fn brklen(&mut self) -> BRKLEN_W { + BRKLEN_W { w: self } + } + #[doc = "Bits 10:11 - LIN Master Header Delay"] + #[inline(always)] + pub fn hdrdly(&mut self) -> HDRDLY_W { + HDRDLY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Control C\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlc](index.html) module"] +pub struct CTRLC_SPEC; +impl crate::RegisterSpec for CTRLC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlc::R](R) reader structure"] +impl crate::Readable for CTRLC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlc::W](W) writer structure"] +impl crate::Writable for CTRLC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLC to value 0"] +impl crate::Resettable for CTRLC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/sercom0/usart_ext/data.rs b/pac/atsamc20e/src/sercom0/usart_ext/data.rs new file mode 100644 index 000000000000..a54152c9571a --- /dev/null +++ b/pac/atsamc20e/src/sercom0/usart_ext/data.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data Value"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data Value"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01ff) | (value as u16 & 0x01ff); + self.w + } +} +impl R { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new((self.bits & 0x01ff) as u16) + } +} +impl W { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/sercom0/usart_ext/dbgctrl.rs b/pac/atsamc20e/src/sercom0/usart_ext/dbgctrl.rs new file mode 100644 index 000000000000..6c844f3fe40d --- /dev/null +++ b/pac/atsamc20e/src/sercom0/usart_ext/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGSTOP` reader - Debug Mode"] +pub struct DBGSTOP_R(crate::FieldReader); +impl DBGSTOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGSTOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGSTOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGSTOP` writer - Debug Mode"] +pub struct DBGSTOP_W<'a> { + w: &'a mut W, +} +impl<'a> DBGSTOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&self) -> DBGSTOP_R { + DBGSTOP_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&mut self) -> DBGSTOP_W { + DBGSTOP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/sercom0/usart_ext/intenclr.rs b/pac/atsamc20e/src/sercom0/usart_ext/intenclr.rs new file mode 100644 index 000000000000..a815553ce666 --- /dev/null +++ b/pac/atsamc20e/src/sercom0/usart_ext/intenclr.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Disable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Disable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Disable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Disable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Disable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Disable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RXS` reader - Receive Start Interrupt Disable"] +pub struct RXS_R(crate::FieldReader); +impl RXS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXS` writer - Receive Start Interrupt Disable"] +pub struct RXS_W<'a> { + w: &'a mut W, +} +impl<'a> RXS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CTSIC` reader - Clear To Send Input Change Interrupt Disable"] +pub struct CTSIC_R(crate::FieldReader); +impl CTSIC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTSIC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTSIC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTSIC` writer - Clear To Send Input Change Interrupt Disable"] +pub struct CTSIC_W<'a> { + w: &'a mut W, +} +impl<'a> CTSIC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RXBRK` reader - Break Received Interrupt Disable"] +pub struct RXBRK_R(crate::FieldReader); +impl RXBRK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXBRK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXBRK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXBRK` writer - Break Received Interrupt Disable"] +pub struct RXBRK_W<'a> { + w: &'a mut W, +} +impl<'a> RXBRK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Disable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Disable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Receive Start Interrupt Disable"] + #[inline(always)] + pub fn rxs(&self) -> RXS_R { + RXS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Disable"] + #[inline(always)] + pub fn ctsic(&self) -> CTSIC_R { + CTSIC_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Break Received Interrupt Disable"] + #[inline(always)] + pub fn rxbrk(&self) -> RXBRK_R { + RXBRK_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Receive Start Interrupt Disable"] + #[inline(always)] + pub fn rxs(&mut self) -> RXS_W { + RXS_W { w: self } + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Disable"] + #[inline(always)] + pub fn ctsic(&mut self) -> CTSIC_W { + CTSIC_W { w: self } + } + #[doc = "Bit 5 - Break Received Interrupt Disable"] + #[inline(always)] + pub fn rxbrk(&mut self) -> RXBRK_W { + RXBRK_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/sercom0/usart_ext/intenset.rs b/pac/atsamc20e/src/sercom0/usart_ext/intenset.rs new file mode 100644 index 000000000000..e800681cf423 --- /dev/null +++ b/pac/atsamc20e/src/sercom0/usart_ext/intenset.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Enable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Enable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Enable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Enable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Enable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Enable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RXS` reader - Receive Start Interrupt Enable"] +pub struct RXS_R(crate::FieldReader); +impl RXS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXS` writer - Receive Start Interrupt Enable"] +pub struct RXS_W<'a> { + w: &'a mut W, +} +impl<'a> RXS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CTSIC` reader - Clear To Send Input Change Interrupt Enable"] +pub struct CTSIC_R(crate::FieldReader); +impl CTSIC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTSIC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTSIC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTSIC` writer - Clear To Send Input Change Interrupt Enable"] +pub struct CTSIC_W<'a> { + w: &'a mut W, +} +impl<'a> CTSIC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RXBRK` reader - Break Received Interrupt Enable"] +pub struct RXBRK_R(crate::FieldReader); +impl RXBRK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXBRK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXBRK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXBRK` writer - Break Received Interrupt Enable"] +pub struct RXBRK_W<'a> { + w: &'a mut W, +} +impl<'a> RXBRK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Receive Start Interrupt Enable"] + #[inline(always)] + pub fn rxs(&self) -> RXS_R { + RXS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Enable"] + #[inline(always)] + pub fn ctsic(&self) -> CTSIC_R { + CTSIC_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Break Received Interrupt Enable"] + #[inline(always)] + pub fn rxbrk(&self) -> RXBRK_R { + RXBRK_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Receive Start Interrupt Enable"] + #[inline(always)] + pub fn rxs(&mut self) -> RXS_W { + RXS_W { w: self } + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Enable"] + #[inline(always)] + pub fn ctsic(&mut self) -> CTSIC_W { + CTSIC_W { w: self } + } + #[doc = "Bit 5 - Break Received Interrupt Enable"] + #[inline(always)] + pub fn rxbrk(&mut self) -> RXBRK_W { + RXBRK_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/sercom0/usart_ext/intflag.rs b/pac/atsamc20e/src/sercom0/usart_ext/intflag.rs new file mode 100644 index 000000000000..4b0be279a9ae --- /dev/null +++ b/pac/atsamc20e/src/sercom0/usart_ext/intflag.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RXS` reader - Receive Start Interrupt"] +pub struct RXS_R(crate::FieldReader); +impl RXS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXS` writer - Receive Start Interrupt"] +pub struct RXS_W<'a> { + w: &'a mut W, +} +impl<'a> RXS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CTSIC` reader - Clear To Send Input Change Interrupt"] +pub struct CTSIC_R(crate::FieldReader); +impl CTSIC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTSIC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTSIC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTSIC` writer - Clear To Send Input Change Interrupt"] +pub struct CTSIC_W<'a> { + w: &'a mut W, +} +impl<'a> CTSIC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RXBRK` reader - Break Received Interrupt"] +pub struct RXBRK_R(crate::FieldReader); +impl RXBRK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXBRK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXBRK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXBRK` writer - Break Received Interrupt"] +pub struct RXBRK_W<'a> { + w: &'a mut W, +} +impl<'a> RXBRK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Receive Start Interrupt"] + #[inline(always)] + pub fn rxs(&self) -> RXS_R { + RXS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt"] + #[inline(always)] + pub fn ctsic(&self) -> CTSIC_R { + CTSIC_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Break Received Interrupt"] + #[inline(always)] + pub fn rxbrk(&self) -> RXBRK_R { + RXBRK_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Receive Start Interrupt"] + #[inline(always)] + pub fn rxs(&mut self) -> RXS_W { + RXS_W { w: self } + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt"] + #[inline(always)] + pub fn ctsic(&mut self) -> CTSIC_W { + CTSIC_W { w: self } + } + #[doc = "Bit 5 - Break Received Interrupt"] + #[inline(always)] + pub fn rxbrk(&mut self) -> RXBRK_W { + RXBRK_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/sercom0/usart_ext/rxpl.rs b/pac/atsamc20e/src/sercom0/usart_ext/rxpl.rs new file mode 100644 index 000000000000..174464dc16b5 --- /dev/null +++ b/pac/atsamc20e/src/sercom0/usart_ext/rxpl.rs @@ -0,0 +1,103 @@ +#[doc = "Register `RXPL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RXPL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RXPL` reader - Receive Pulse Length"] +pub struct RXPL_R(crate::FieldReader); +impl RXPL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RXPL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXPL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXPL` writer - Receive Pulse Length"] +pub struct RXPL_W<'a> { + w: &'a mut W, +} +impl<'a> RXPL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Receive Pulse Length"] + #[inline(always)] + pub fn rxpl(&self) -> RXPL_R { + RXPL_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Receive Pulse Length"] + #[inline(always)] + pub fn rxpl(&mut self) -> RXPL_W { + RXPL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Receive Pulse Length\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxpl](index.html) module"] +pub struct RXPL_SPEC; +impl crate::RegisterSpec for RXPL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [rxpl::R](R) reader structure"] +impl crate::Readable for RXPL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rxpl::W](W) writer structure"] +impl crate::Writable for RXPL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RXPL to value 0"] +impl crate::Resettable for RXPL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/sercom0/usart_ext/status.rs b/pac/atsamc20e/src/sercom0/usart_ext/status.rs new file mode 100644 index 000000000000..a0c50c1bc2cf --- /dev/null +++ b/pac/atsamc20e/src/sercom0/usart_ext/status.rs @@ -0,0 +1,395 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PERR` reader - Parity Error"] +pub struct PERR_R(crate::FieldReader); +impl PERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERR` writer - Parity Error"] +pub struct PERR_W<'a> { + w: &'a mut W, +} +impl<'a> PERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `FERR` reader - Frame Error"] +pub struct FERR_R(crate::FieldReader); +impl FERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FERR` writer - Frame Error"] +pub struct FERR_W<'a> { + w: &'a mut W, +} +impl<'a> FERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `BUFOVF` reader - Buffer Overflow"] +pub struct BUFOVF_R(crate::FieldReader); +impl BUFOVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUFOVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUFOVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUFOVF` writer - Buffer Overflow"] +pub struct BUFOVF_W<'a> { + w: &'a mut W, +} +impl<'a> BUFOVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CTS` reader - Clear To Send"] +pub struct CTS_R(crate::FieldReader); +impl CTS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTS` writer - Clear To Send"] +pub struct CTS_W<'a> { + w: &'a mut W, +} +impl<'a> CTS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ISF` reader - Inconsistent Sync Field"] +pub struct ISF_R(crate::FieldReader); +impl ISF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ISF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ISF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ISF` writer - Inconsistent Sync Field"] +pub struct ISF_W<'a> { + w: &'a mut W, +} +impl<'a> ISF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `COLL` reader - Collision Detected"] +pub struct COLL_R(crate::FieldReader); +impl COLL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COLL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COLL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COLL` writer - Collision Detected"] +pub struct COLL_W<'a> { + w: &'a mut W, +} +impl<'a> COLL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `TXE` reader - Transmitter Empty"] +pub struct TXE_R(crate::FieldReader); +impl TXE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXE` writer - Transmitter Empty"] +pub struct TXE_W<'a> { + w: &'a mut W, +} +impl<'a> TXE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - Parity Error"] + #[inline(always)] + pub fn perr(&self) -> PERR_R { + PERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Frame Error"] + #[inline(always)] + pub fn ferr(&self) -> FERR_R { + FERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&self) -> BUFOVF_R { + BUFOVF_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Clear To Send"] + #[inline(always)] + pub fn cts(&self) -> CTS_R { + CTS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Inconsistent Sync Field"] + #[inline(always)] + pub fn isf(&self) -> ISF_R { + ISF_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Collision Detected"] + #[inline(always)] + pub fn coll(&self) -> COLL_R { + COLL_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Transmitter Empty"] + #[inline(always)] + pub fn txe(&self) -> TXE_R { + TXE_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Parity Error"] + #[inline(always)] + pub fn perr(&mut self) -> PERR_W { + PERR_W { w: self } + } + #[doc = "Bit 1 - Frame Error"] + #[inline(always)] + pub fn ferr(&mut self) -> FERR_W { + FERR_W { w: self } + } + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&mut self) -> BUFOVF_W { + BUFOVF_W { w: self } + } + #[doc = "Bit 3 - Clear To Send"] + #[inline(always)] + pub fn cts(&mut self) -> CTS_W { + CTS_W { w: self } + } + #[doc = "Bit 4 - Inconsistent Sync Field"] + #[inline(always)] + pub fn isf(&mut self) -> ISF_W { + ISF_W { w: self } + } + #[doc = "Bit 5 - Collision Detected"] + #[inline(always)] + pub fn coll(&mut self) -> COLL_W { + COLL_W { w: self } + } + #[doc = "Bit 6 - Transmitter Empty"] + #[inline(always)] + pub fn txe(&mut self) -> TXE_W { + TXE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/sercom0/usart_ext/syncbusy.rs b/pac/atsamc20e/src/sercom0/usart_ext/syncbusy.rs new file mode 100644 index 000000000000..7c3b817bbb04 --- /dev/null +++ b/pac/atsamc20e/src/sercom0/usart_ext/syncbusy.rs @@ -0,0 +1,93 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - SERCOM Enable Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLB` reader - CTRLB Synchronization Busy"] +pub struct CTRLB_R(crate::FieldReader); +impl CTRLB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM Enable Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - CTRLB Synchronization Busy"] + #[inline(always)] + pub fn ctrlb(&self) -> CTRLB_R { + CTRLB_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +#[doc = "USART_EXT Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/sercom0/usart_int.rs b/pac/atsamc20e/src/sercom0/usart_int.rs new file mode 100644 index 000000000000..157c8c4b4fdc --- /dev/null +++ b/pac/atsamc20e/src/sercom0/usart_int.rs @@ -0,0 +1,60 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "USART_INT Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "USART_INT Control B"] +pub mod ctrlb; +#[doc = "CTRLC register accessor: an alias for `Reg`"] +pub type CTRLC = crate::Reg; +#[doc = "USART_INT Control C"] +pub mod ctrlc; +#[doc = "BAUD register accessor: an alias for `Reg`"] +pub type BAUD = crate::Reg; +#[doc = "USART_INT Baud Rate"] +pub mod baud; +#[doc = "BAUD_FRAC_MODE register accessor: an alias for `Reg`"] +pub type BAUD_FRAC_MODE = crate::Reg; +#[doc = "USART_INT Baud Rate"] +pub mod baud_frac_mode; +#[doc = "BAUD_FRACFP_MODE register accessor: an alias for `Reg`"] +pub type BAUD_FRACFP_MODE = crate::Reg; +#[doc = "USART_INT Baud Rate"] +pub mod baud_fracfp_mode; +#[doc = "BAUD_USARTFP_MODE register accessor: an alias for `Reg`"] +pub type BAUD_USARTFP_MODE = crate::Reg; +#[doc = "USART_INT Baud Rate"] +pub mod baud_usartfp_mode; +#[doc = "RXPL register accessor: an alias for `Reg`"] +pub type RXPL = crate::Reg; +#[doc = "USART_INT Receive Pulse Length"] +pub mod rxpl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "USART_INT Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "USART_INT Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "USART_INT Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "USART_INT Status"] +pub mod status; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "USART_INT Synchronization Busy"] +pub mod syncbusy; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "USART_INT Data"] +pub mod data; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "USART_INT Debug Control"] +pub mod dbgctrl; diff --git a/pac/atsamc20e/src/sercom0/usart_int/baud.rs b/pac/atsamc20e/src/sercom0/usart_int/baud.rs new file mode 100644 index 000000000000..a82df20712b3 --- /dev/null +++ b/pac/atsamc20e/src/sercom0/usart_int/baud.rs @@ -0,0 +1,103 @@ +#[doc = "Register `BAUD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud](index.html) module"] +pub struct BAUD_SPEC; +impl crate::RegisterSpec for BAUD_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud::R](R) reader structure"] +impl crate::Readable for BAUD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud::W](W) writer structure"] +impl crate::Writable for BAUD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD to value 0"] +impl crate::Resettable for BAUD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/sercom0/usart_int/baud_frac_mode.rs b/pac/atsamc20e/src/sercom0/usart_int/baud_frac_mode.rs new file mode 100644 index 000000000000..b9c7fa4c4b2a --- /dev/null +++ b/pac/atsamc20e/src/sercom0/usart_int/baud_frac_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `BAUD_FRAC_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD_FRAC_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1fff) | (value as u16 & 0x1fff); + self.w + } +} +#[doc = "Field `FP` reader - Fractional Part"] +pub struct FP_R(crate::FieldReader); +impl FP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FP` writer - Fractional Part"] +pub struct FP_W<'a> { + w: &'a mut W, +} +impl<'a> FP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 13)) | ((value as u16 & 0x07) << 13); + self.w + } +} +impl R { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new((self.bits & 0x1fff) as u16) + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&self) -> FP_R { + FP_R::new(((self.bits >> 13) & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&mut self) -> FP_W { + FP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud_frac_mode](index.html) module"] +pub struct BAUD_FRAC_MODE_SPEC; +impl crate::RegisterSpec for BAUD_FRAC_MODE_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud_frac_mode::R](R) reader structure"] +impl crate::Readable for BAUD_FRAC_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud_frac_mode::W](W) writer structure"] +impl crate::Writable for BAUD_FRAC_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD_FRAC_MODE to value 0"] +impl crate::Resettable for BAUD_FRAC_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/sercom0/usart_int/baud_fracfp_mode.rs b/pac/atsamc20e/src/sercom0/usart_int/baud_fracfp_mode.rs new file mode 100644 index 000000000000..0671db99cc9d --- /dev/null +++ b/pac/atsamc20e/src/sercom0/usart_int/baud_fracfp_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `BAUD_FRACFP_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD_FRACFP_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1fff) | (value as u16 & 0x1fff); + self.w + } +} +#[doc = "Field `FP` reader - Fractional Part"] +pub struct FP_R(crate::FieldReader); +impl FP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FP` writer - Fractional Part"] +pub struct FP_W<'a> { + w: &'a mut W, +} +impl<'a> FP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 13)) | ((value as u16 & 0x07) << 13); + self.w + } +} +impl R { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new((self.bits & 0x1fff) as u16) + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&self) -> FP_R { + FP_R::new(((self.bits >> 13) & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&mut self) -> FP_W { + FP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud_fracfp_mode](index.html) module"] +pub struct BAUD_FRACFP_MODE_SPEC; +impl crate::RegisterSpec for BAUD_FRACFP_MODE_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud_fracfp_mode::R](R) reader structure"] +impl crate::Readable for BAUD_FRACFP_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud_fracfp_mode::W](W) writer structure"] +impl crate::Writable for BAUD_FRACFP_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD_FRACFP_MODE to value 0"] +impl crate::Resettable for BAUD_FRACFP_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/sercom0/usart_int/baud_usartfp_mode.rs b/pac/atsamc20e/src/sercom0/usart_int/baud_usartfp_mode.rs new file mode 100644 index 000000000000..b49a7ef5b84c --- /dev/null +++ b/pac/atsamc20e/src/sercom0/usart_int/baud_usartfp_mode.rs @@ -0,0 +1,103 @@ +#[doc = "Register `BAUD_USARTFP_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD_USARTFP_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud_usartfp_mode](index.html) module"] +pub struct BAUD_USARTFP_MODE_SPEC; +impl crate::RegisterSpec for BAUD_USARTFP_MODE_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud_usartfp_mode::R](R) reader structure"] +impl crate::Readable for BAUD_USARTFP_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud_usartfp_mode::W](W) writer structure"] +impl crate::Writable for BAUD_USARTFP_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD_USARTFP_MODE to value 0"] +impl crate::Resettable for BAUD_USARTFP_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/sercom0/usart_int/ctrla.rs b/pac/atsamc20e/src/sercom0/usart_int/ctrla.rs new file mode 100644 index 000000000000..19d10ecf8e8f --- /dev/null +++ b/pac/atsamc20e/src/sercom0/usart_int/ctrla.rs @@ -0,0 +1,1171 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: USART with external clock"] + USART_EXT_CLK = 0, + #[doc = "1: USART with internal clock"] + USART_INT_CLK = 1, + #[doc = "2: SPI in slave operation"] + SPI_SLAVE = 2, + #[doc = "3: SPI in master operation"] + SPI_MASTER = 3, + #[doc = "4: I2C slave operation"] + I2C_SLAVE = 4, + #[doc = "5: I2C master operation"] + I2C_MASTER = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::USART_EXT_CLK), + 1 => Some(MODE_A::USART_INT_CLK), + 2 => Some(MODE_A::SPI_SLAVE), + 3 => Some(MODE_A::SPI_MASTER), + 4 => Some(MODE_A::I2C_SLAVE), + 5 => Some(MODE_A::I2C_MASTER), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_EXT_CLK`"] + #[inline(always)] + pub fn is_usart_ext_clk(&self) -> bool { + **self == MODE_A::USART_EXT_CLK + } + #[doc = "Checks if the value of the field is `USART_INT_CLK`"] + #[inline(always)] + pub fn is_usart_int_clk(&self) -> bool { + **self == MODE_A::USART_INT_CLK + } + #[doc = "Checks if the value of the field is `SPI_SLAVE`"] + #[inline(always)] + pub fn is_spi_slave(&self) -> bool { + **self == MODE_A::SPI_SLAVE + } + #[doc = "Checks if the value of the field is `SPI_MASTER`"] + #[inline(always)] + pub fn is_spi_master(&self) -> bool { + **self == MODE_A::SPI_MASTER + } + #[doc = "Checks if the value of the field is `I2C_SLAVE`"] + #[inline(always)] + pub fn is_i2c_slave(&self) -> bool { + **self == MODE_A::I2C_SLAVE + } + #[doc = "Checks if the value of the field is `I2C_MASTER`"] + #[inline(always)] + pub fn is_i2c_master(&self) -> bool { + **self == MODE_A::I2C_MASTER + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART with external clock"] + #[inline(always)] + pub fn usart_ext_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_EXT_CLK) + } + #[doc = "USART with internal clock"] + #[inline(always)] + pub fn usart_int_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_INT_CLK) + } + #[doc = "SPI in slave operation"] + #[inline(always)] + pub fn spi_slave(self) -> &'a mut W { + self.variant(MODE_A::SPI_SLAVE) + } + #[doc = "SPI in master operation"] + #[inline(always)] + pub fn spi_master(self) -> &'a mut W { + self.variant(MODE_A::SPI_MASTER) + } + #[doc = "I2C slave operation"] + #[inline(always)] + pub fn i2c_slave(self) -> &'a mut W { + self.variant(MODE_A::I2C_SLAVE) + } + #[doc = "I2C master operation"] + #[inline(always)] + pub fn i2c_master(self) -> &'a mut W { + self.variant(MODE_A::I2C_MASTER) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 2)) | ((value as u32 & 0x07) << 2); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `IBON` reader - Immediate Buffer Overflow Notification"] +pub struct IBON_R(crate::FieldReader); +impl IBON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IBON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IBON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IBON` writer - Immediate Buffer Overflow Notification"] +pub struct IBON_W<'a> { + w: &'a mut W, +} +impl<'a> IBON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Sample\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SAMPR_A { + #[doc = "0: 16x over-sampling using arithmetic baudrate generation"] + _16X_ARITHMETIC = 0, + #[doc = "1: 16x over-sampling using fractional baudrate generation"] + _16X_FRACTIONAL = 1, + #[doc = "2: 8x over-sampling using arithmetic baudrate generation"] + _8X_ARITHMETIC = 2, + #[doc = "3: 8x over-sampling using fractional baudrate generation"] + _8X_FRACTIONAL = 3, + #[doc = "4: 3x over-sampling using arithmetic baudrate generation"] + _3X_ARITHMETIC = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SAMPR_A) -> Self { + variant as _ + } +} +#[doc = "Field `SAMPR` reader - Sample"] +pub struct SAMPR_R(crate::FieldReader); +impl SAMPR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SAMPR_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SAMPR_A::_16X_ARITHMETIC), + 1 => Some(SAMPR_A::_16X_FRACTIONAL), + 2 => Some(SAMPR_A::_8X_ARITHMETIC), + 3 => Some(SAMPR_A::_8X_FRACTIONAL), + 4 => Some(SAMPR_A::_3X_ARITHMETIC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_16X_ARITHMETIC`"] + #[inline(always)] + pub fn is_16x_arithmetic(&self) -> bool { + **self == SAMPR_A::_16X_ARITHMETIC + } + #[doc = "Checks if the value of the field is `_16X_FRACTIONAL`"] + #[inline(always)] + pub fn is_16x_fractional(&self) -> bool { + **self == SAMPR_A::_16X_FRACTIONAL + } + #[doc = "Checks if the value of the field is `_8X_ARITHMETIC`"] + #[inline(always)] + pub fn is_8x_arithmetic(&self) -> bool { + **self == SAMPR_A::_8X_ARITHMETIC + } + #[doc = "Checks if the value of the field is `_8X_FRACTIONAL`"] + #[inline(always)] + pub fn is_8x_fractional(&self) -> bool { + **self == SAMPR_A::_8X_FRACTIONAL + } + #[doc = "Checks if the value of the field is `_3X_ARITHMETIC`"] + #[inline(always)] + pub fn is_3x_arithmetic(&self) -> bool { + **self == SAMPR_A::_3X_ARITHMETIC + } +} +impl core::ops::Deref for SAMPR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SAMPR` writer - Sample"] +pub struct SAMPR_W<'a> { + w: &'a mut W, +} +impl<'a> SAMPR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SAMPR_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "16x over-sampling using arithmetic baudrate generation"] + #[inline(always)] + pub fn _16x_arithmetic(self) -> &'a mut W { + self.variant(SAMPR_A::_16X_ARITHMETIC) + } + #[doc = "16x over-sampling using fractional baudrate generation"] + #[inline(always)] + pub fn _16x_fractional(self) -> &'a mut W { + self.variant(SAMPR_A::_16X_FRACTIONAL) + } + #[doc = "8x over-sampling using arithmetic baudrate generation"] + #[inline(always)] + pub fn _8x_arithmetic(self) -> &'a mut W { + self.variant(SAMPR_A::_8X_ARITHMETIC) + } + #[doc = "8x over-sampling using fractional baudrate generation"] + #[inline(always)] + pub fn _8x_fractional(self) -> &'a mut W { + self.variant(SAMPR_A::_8X_FRACTIONAL) + } + #[doc = "3x over-sampling using arithmetic baudrate generation"] + #[inline(always)] + pub fn _3x_arithmetic(self) -> &'a mut W { + self.variant(SAMPR_A::_3X_ARITHMETIC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 13)) | ((value as u32 & 0x07) << 13); + self.w + } +} +#[doc = "Transmit Data Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum TXPO_A { + #[doc = "0: SERCOM PAD\\[0\\] +is used for data transmission"] + PAD0 = 0, + #[doc = "1: SERCOM PAD\\[2\\] +is used for data transmission"] + PAD2 = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: TXPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `TXPO` reader - Transmit Data Pinout"] +pub struct TXPO_R(crate::FieldReader); +impl TXPO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TXPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(TXPO_A::PAD0), + 1 => Some(TXPO_A::PAD2), + _ => None, + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == TXPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == TXPO_A::PAD2 + } +} +impl core::ops::Deref for TXPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXPO` writer - Transmit Data Pinout"] +pub struct TXPO_W<'a> { + w: &'a mut W, +} +impl<'a> TXPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TXPO_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "SERCOM PAD\\[0\\] +is used for data transmission"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(TXPO_A::PAD0) + } + #[doc = "SERCOM PAD\\[2\\] +is used for data transmission"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(TXPO_A::PAD2) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Receive Data Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum RXPO_A { + #[doc = "0: SERCOM PAD\\[0\\] +is used for data reception"] + PAD0 = 0, + #[doc = "1: SERCOM PAD\\[1\\] +is used for data reception"] + PAD1 = 1, + #[doc = "2: SERCOM PAD\\[2\\] +is used for data reception"] + PAD2 = 2, + #[doc = "3: SERCOM PAD\\[3\\] +is used for data reception"] + PAD3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RXPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `RXPO` reader - Receive Data Pinout"] +pub struct RXPO_R(crate::FieldReader); +impl RXPO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RXPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RXPO_A { + match self.bits { + 0 => RXPO_A::PAD0, + 1 => RXPO_A::PAD1, + 2 => RXPO_A::PAD2, + 3 => RXPO_A::PAD3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == RXPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD1`"] + #[inline(always)] + pub fn is_pad1(&self) -> bool { + **self == RXPO_A::PAD1 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == RXPO_A::PAD2 + } + #[doc = "Checks if the value of the field is `PAD3`"] + #[inline(always)] + pub fn is_pad3(&self) -> bool { + **self == RXPO_A::PAD3 + } +} +impl core::ops::Deref for RXPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXPO` writer - Receive Data Pinout"] +pub struct RXPO_W<'a> { + w: &'a mut W, +} +impl<'a> RXPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RXPO_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "SERCOM PAD\\[0\\] +is used for data reception"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(RXPO_A::PAD0) + } + #[doc = "SERCOM PAD\\[1\\] +is used for data reception"] + #[inline(always)] + pub fn pad1(self) -> &'a mut W { + self.variant(RXPO_A::PAD1) + } + #[doc = "SERCOM PAD\\[2\\] +is used for data reception"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(RXPO_A::PAD2) + } + #[doc = "SERCOM PAD\\[3\\] +is used for data reception"] + #[inline(always)] + pub fn pad3(self) -> &'a mut W { + self.variant(RXPO_A::PAD3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 20)) | ((value as u32 & 0x03) << 20); + self.w + } +} +#[doc = "Field `SAMPA` reader - Sample Adjustment"] +pub struct SAMPA_R(crate::FieldReader); +impl SAMPA_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SAMPA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SAMPA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SAMPA` writer - Sample Adjustment"] +pub struct SAMPA_W<'a> { + w: &'a mut W, +} +impl<'a> SAMPA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 22)) | ((value as u32 & 0x03) << 22); + self.w + } +} +#[doc = "Frame Format\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FORM_A { + #[doc = "0: USART frame"] + USART_FRAME_NO_PARITY = 0, + #[doc = "1: USART frame with parity"] + USART_FRAME_WITH_PARITY = 1, + #[doc = "2: LIN Master - Break and sync generation"] + USART_FRAME_LIN_MASTER_MODE = 2, + #[doc = "4: Auto-baud - break detection and auto-baud"] + USART_FRAME_AUTO_BAUD_NO_PARITY = 4, + #[doc = "5: Auto-baud - break detection and auto-baud with parity"] + USART_FRAME_AUTO_BAUD_WITH_PARITY = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FORM_A) -> Self { + variant as _ + } +} +#[doc = "Field `FORM` reader - Frame Format"] +pub struct FORM_R(crate::FieldReader); +impl FORM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FORM_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(FORM_A::USART_FRAME_NO_PARITY), + 1 => Some(FORM_A::USART_FRAME_WITH_PARITY), + 2 => Some(FORM_A::USART_FRAME_LIN_MASTER_MODE), + 4 => Some(FORM_A::USART_FRAME_AUTO_BAUD_NO_PARITY), + 5 => Some(FORM_A::USART_FRAME_AUTO_BAUD_WITH_PARITY), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_FRAME_NO_PARITY`"] + #[inline(always)] + pub fn is_usart_frame_no_parity(&self) -> bool { + **self == FORM_A::USART_FRAME_NO_PARITY + } + #[doc = "Checks if the value of the field is `USART_FRAME_WITH_PARITY`"] + #[inline(always)] + pub fn is_usart_frame_with_parity(&self) -> bool { + **self == FORM_A::USART_FRAME_WITH_PARITY + } + #[doc = "Checks if the value of the field is `USART_FRAME_LIN_MASTER_MODE`"] + #[inline(always)] + pub fn is_usart_frame_lin_master_mode(&self) -> bool { + **self == FORM_A::USART_FRAME_LIN_MASTER_MODE + } + #[doc = "Checks if the value of the field is `USART_FRAME_AUTO_BAUD_NO_PARITY`"] + #[inline(always)] + pub fn is_usart_frame_auto_baud_no_parity(&self) -> bool { + **self == FORM_A::USART_FRAME_AUTO_BAUD_NO_PARITY + } + #[doc = "Checks if the value of the field is `USART_FRAME_AUTO_BAUD_WITH_PARITY`"] + #[inline(always)] + pub fn is_usart_frame_auto_baud_with_parity(&self) -> bool { + **self == FORM_A::USART_FRAME_AUTO_BAUD_WITH_PARITY + } +} +impl core::ops::Deref for FORM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FORM` writer - Frame Format"] +pub struct FORM_W<'a> { + w: &'a mut W, +} +impl<'a> FORM_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FORM_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART frame"] + #[inline(always)] + pub fn usart_frame_no_parity(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_NO_PARITY) + } + #[doc = "USART frame with parity"] + #[inline(always)] + pub fn usart_frame_with_parity(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_WITH_PARITY) + } + #[doc = "LIN Master - Break and sync generation"] + #[inline(always)] + pub fn usart_frame_lin_master_mode(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_LIN_MASTER_MODE) + } + #[doc = "Auto-baud - break detection and auto-baud"] + #[inline(always)] + pub fn usart_frame_auto_baud_no_parity(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_AUTO_BAUD_NO_PARITY) + } + #[doc = "Auto-baud - break detection and auto-baud with parity"] + #[inline(always)] + pub fn usart_frame_auto_baud_with_parity(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_AUTO_BAUD_WITH_PARITY) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Communication Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CMODE_A { + #[doc = "0: Asynchronous Communication"] + ASYNC = 0, + #[doc = "1: Synchronous Communication"] + SYNC = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CMODE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CMODE` reader - Communication Mode"] +pub struct CMODE_R(crate::FieldReader); +impl CMODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CMODE_A { + match self.bits { + false => CMODE_A::ASYNC, + true => CMODE_A::SYNC, + } + } + #[doc = "Checks if the value of the field is `ASYNC`"] + #[inline(always)] + pub fn is_async(&self) -> bool { + **self == CMODE_A::ASYNC + } + #[doc = "Checks if the value of the field is `SYNC`"] + #[inline(always)] + pub fn is_sync(&self) -> bool { + **self == CMODE_A::SYNC + } +} +impl core::ops::Deref for CMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMODE` writer - Communication Mode"] +pub struct CMODE_W<'a> { + w: &'a mut W, +} +impl<'a> CMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMODE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Asynchronous Communication"] + #[inline(always)] + pub fn async_(self) -> &'a mut W { + self.variant(CMODE_A::ASYNC) + } + #[doc = "Synchronous Communication"] + #[inline(always)] + pub fn sync(self) -> &'a mut W { + self.variant(CMODE_A::SYNC) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Clock Polarity\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CPOL_A { + #[doc = "0: TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge"] + IDLE_LOW = 0, + #[doc = "1: TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge"] + IDLE_HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CPOL_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CPOL` reader - Clock Polarity"] +pub struct CPOL_R(crate::FieldReader); +impl CPOL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPOL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CPOL_A { + match self.bits { + false => CPOL_A::IDLE_LOW, + true => CPOL_A::IDLE_HIGH, + } + } + #[doc = "Checks if the value of the field is `IDLE_LOW`"] + #[inline(always)] + pub fn is_idle_low(&self) -> bool { + **self == CPOL_A::IDLE_LOW + } + #[doc = "Checks if the value of the field is `IDLE_HIGH`"] + #[inline(always)] + pub fn is_idle_high(&self) -> bool { + **self == CPOL_A::IDLE_HIGH + } +} +impl core::ops::Deref for CPOL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPOL` writer - Clock Polarity"] +pub struct CPOL_W<'a> { + w: &'a mut W, +} +impl<'a> CPOL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CPOL_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge"] + #[inline(always)] + pub fn idle_low(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_LOW) + } + #[doc = "TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge"] + #[inline(always)] + pub fn idle_high(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_HIGH) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29); + self.w + } +} +#[doc = "Data Order\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum DORD_A { + #[doc = "0: MSB is transmitted first"] + MSB = 0, + #[doc = "1: LSB is transmitted first"] + LSB = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DORD_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DORD` reader - Data Order"] +pub struct DORD_R(crate::FieldReader); +impl DORD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DORD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DORD_A { + match self.bits { + false => DORD_A::MSB, + true => DORD_A::LSB, + } + } + #[doc = "Checks if the value of the field is `MSB`"] + #[inline(always)] + pub fn is_msb(&self) -> bool { + **self == DORD_A::MSB + } + #[doc = "Checks if the value of the field is `LSB`"] + #[inline(always)] + pub fn is_lsb(&self) -> bool { + **self == DORD_A::LSB + } +} +impl core::ops::Deref for DORD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DORD` writer - Data Order"] +pub struct DORD_W<'a> { + w: &'a mut W, +} +impl<'a> DORD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DORD_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "MSB is transmitted first"] + #[inline(always)] + pub fn msb(self) -> &'a mut W { + self.variant(DORD_A::MSB) + } + #[doc = "LSB is transmitted first"] + #[inline(always)] + pub fn lsb(self) -> &'a mut W { + self.variant(DORD_A::LSB) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x07) as u8) + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&self) -> IBON_R { + IBON_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bits 13:15 - Sample"] + #[inline(always)] + pub fn sampr(&self) -> SAMPR_R { + SAMPR_R::new(((self.bits >> 13) & 0x07) as u8) + } + #[doc = "Bits 16:17 - Transmit Data Pinout"] + #[inline(always)] + pub fn txpo(&self) -> TXPO_R { + TXPO_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bits 20:21 - Receive Data Pinout"] + #[inline(always)] + pub fn rxpo(&self) -> RXPO_R { + RXPO_R::new(((self.bits >> 20) & 0x03) as u8) + } + #[doc = "Bits 22:23 - Sample Adjustment"] + #[inline(always)] + pub fn sampa(&self) -> SAMPA_R { + SAMPA_R::new(((self.bits >> 22) & 0x03) as u8) + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&self) -> FORM_R { + FORM_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 28 - Communication Mode"] + #[inline(always)] + pub fn cmode(&self) -> CMODE_R { + CMODE_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&self) -> CPOL_R { + CPOL_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&self) -> DORD_R { + DORD_R::new(((self.bits >> 30) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&mut self) -> IBON_W { + IBON_W { w: self } + } + #[doc = "Bits 13:15 - Sample"] + #[inline(always)] + pub fn sampr(&mut self) -> SAMPR_W { + SAMPR_W { w: self } + } + #[doc = "Bits 16:17 - Transmit Data Pinout"] + #[inline(always)] + pub fn txpo(&mut self) -> TXPO_W { + TXPO_W { w: self } + } + #[doc = "Bits 20:21 - Receive Data Pinout"] + #[inline(always)] + pub fn rxpo(&mut self) -> RXPO_W { + RXPO_W { w: self } + } + #[doc = "Bits 22:23 - Sample Adjustment"] + #[inline(always)] + pub fn sampa(&mut self) -> SAMPA_W { + SAMPA_W { w: self } + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&mut self) -> FORM_W { + FORM_W { w: self } + } + #[doc = "Bit 28 - Communication Mode"] + #[inline(always)] + pub fn cmode(&mut self) -> CMODE_W { + CMODE_W { w: self } + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&mut self) -> CPOL_W { + CPOL_W { w: self } + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&mut self) -> DORD_W { + DORD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/sercom0/usart_int/ctrlb.rs b/pac/atsamc20e/src/sercom0/usart_int/ctrlb.rs new file mode 100644 index 000000000000..d556e0c3cfc2 --- /dev/null +++ b/pac/atsamc20e/src/sercom0/usart_int/ctrlb.rs @@ -0,0 +1,651 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Character Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CHSIZE_A { + #[doc = "0: 8 Bits"] + _8_BIT = 0, + #[doc = "1: 9 Bits"] + _9_BIT = 1, + #[doc = "5: 5 Bits"] + _5_BIT = 5, + #[doc = "6: 6 Bits"] + _6_BIT = 6, + #[doc = "7: 7 Bits"] + _7_BIT = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CHSIZE_A) -> Self { + variant as _ + } +} +#[doc = "Field `CHSIZE` reader - Character Size"] +pub struct CHSIZE_R(crate::FieldReader); +impl CHSIZE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CHSIZE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CHSIZE_A::_8_BIT), + 1 => Some(CHSIZE_A::_9_BIT), + 5 => Some(CHSIZE_A::_5_BIT), + 6 => Some(CHSIZE_A::_6_BIT), + 7 => Some(CHSIZE_A::_7_BIT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_8_BIT`"] + #[inline(always)] + pub fn is_8_bit(&self) -> bool { + **self == CHSIZE_A::_8_BIT + } + #[doc = "Checks if the value of the field is `_9_BIT`"] + #[inline(always)] + pub fn is_9_bit(&self) -> bool { + **self == CHSIZE_A::_9_BIT + } + #[doc = "Checks if the value of the field is `_5_BIT`"] + #[inline(always)] + pub fn is_5_bit(&self) -> bool { + **self == CHSIZE_A::_5_BIT + } + #[doc = "Checks if the value of the field is `_6_BIT`"] + #[inline(always)] + pub fn is_6_bit(&self) -> bool { + **self == CHSIZE_A::_6_BIT + } + #[doc = "Checks if the value of the field is `_7_BIT`"] + #[inline(always)] + pub fn is_7_bit(&self) -> bool { + **self == CHSIZE_A::_7_BIT + } +} +impl core::ops::Deref for CHSIZE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHSIZE` writer - Character Size"] +pub struct CHSIZE_W<'a> { + w: &'a mut W, +} +impl<'a> CHSIZE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CHSIZE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8 Bits"] + #[inline(always)] + pub fn _8_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_8_BIT) + } + #[doc = "9 Bits"] + #[inline(always)] + pub fn _9_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_9_BIT) + } + #[doc = "5 Bits"] + #[inline(always)] + pub fn _5_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_5_BIT) + } + #[doc = "6 Bits"] + #[inline(always)] + pub fn _6_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_6_BIT) + } + #[doc = "7 Bits"] + #[inline(always)] + pub fn _7_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_7_BIT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Stop Bit Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SBMODE_A { + #[doc = "0: One Stop Bit"] + _1_BIT = 0, + #[doc = "1: Two Stop Bits"] + _2_BIT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SBMODE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SBMODE` reader - Stop Bit Mode"] +pub struct SBMODE_R(crate::FieldReader); +impl SBMODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SBMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SBMODE_A { + match self.bits { + false => SBMODE_A::_1_BIT, + true => SBMODE_A::_2_BIT, + } + } + #[doc = "Checks if the value of the field is `_1_BIT`"] + #[inline(always)] + pub fn is_1_bit(&self) -> bool { + **self == SBMODE_A::_1_BIT + } + #[doc = "Checks if the value of the field is `_2_BIT`"] + #[inline(always)] + pub fn is_2_bit(&self) -> bool { + **self == SBMODE_A::_2_BIT + } +} +impl core::ops::Deref for SBMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SBMODE` writer - Stop Bit Mode"] +pub struct SBMODE_W<'a> { + w: &'a mut W, +} +impl<'a> SBMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SBMODE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "One Stop Bit"] + #[inline(always)] + pub fn _1_bit(self) -> &'a mut W { + self.variant(SBMODE_A::_1_BIT) + } + #[doc = "Two Stop Bits"] + #[inline(always)] + pub fn _2_bit(self) -> &'a mut W { + self.variant(SBMODE_A::_2_BIT) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `COLDEN` reader - Collision Detection Enable"] +pub struct COLDEN_R(crate::FieldReader); +impl COLDEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COLDEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COLDEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COLDEN` writer - Collision Detection Enable"] +pub struct COLDEN_W<'a> { + w: &'a mut W, +} +impl<'a> COLDEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `SFDE` reader - Start of Frame Detection Enable"] +pub struct SFDE_R(crate::FieldReader); +impl SFDE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SFDE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SFDE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SFDE` writer - Start of Frame Detection Enable"] +pub struct SFDE_W<'a> { + w: &'a mut W, +} +impl<'a> SFDE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `ENC` reader - Encoding Format"] +pub struct ENC_R(crate::FieldReader); +impl ENC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENC` writer - Encoding Format"] +pub struct ENC_W<'a> { + w: &'a mut W, +} +impl<'a> ENC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Parity Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PMODE_A { + #[doc = "0: Even Parity"] + EVEN = 0, + #[doc = "1: Odd Parity"] + ODD = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PMODE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PMODE` reader - Parity Mode"] +pub struct PMODE_R(crate::FieldReader); +impl PMODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PMODE_A { + match self.bits { + false => PMODE_A::EVEN, + true => PMODE_A::ODD, + } + } + #[doc = "Checks if the value of the field is `EVEN`"] + #[inline(always)] + pub fn is_even(&self) -> bool { + **self == PMODE_A::EVEN + } + #[doc = "Checks if the value of the field is `ODD`"] + #[inline(always)] + pub fn is_odd(&self) -> bool { + **self == PMODE_A::ODD + } +} +impl core::ops::Deref for PMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PMODE` writer - Parity Mode"] +pub struct PMODE_W<'a> { + w: &'a mut W, +} +impl<'a> PMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PMODE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Even Parity"] + #[inline(always)] + pub fn even(self) -> &'a mut W { + self.variant(PMODE_A::EVEN) + } + #[doc = "Odd Parity"] + #[inline(always)] + pub fn odd(self) -> &'a mut W { + self.variant(PMODE_A::ODD) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `TXEN` reader - Transmitter Enable"] +pub struct TXEN_R(crate::FieldReader); +impl TXEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXEN` writer - Transmitter Enable"] +pub struct TXEN_W<'a> { + w: &'a mut W, +} +impl<'a> TXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `RXEN` reader - Receiver Enable"] +pub struct RXEN_R(crate::FieldReader); +impl RXEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXEN` writer - Receiver Enable"] +pub struct RXEN_W<'a> { + w: &'a mut W, +} +impl<'a> RXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `LINCMD` reader - LIN Command"] +pub struct LINCMD_R(crate::FieldReader); +impl LINCMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LINCMD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LINCMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LINCMD` writer - LIN Command"] +pub struct LINCMD_W<'a> { + w: &'a mut W, +} +impl<'a> LINCMD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 24)) | ((value as u32 & 0x03) << 24); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&self) -> CHSIZE_R { + CHSIZE_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 6 - Stop Bit Mode"] + #[inline(always)] + pub fn sbmode(&self) -> SBMODE_R { + SBMODE_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 8 - Collision Detection Enable"] + #[inline(always)] + pub fn colden(&self) -> COLDEN_R { + COLDEN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Start of Frame Detection Enable"] + #[inline(always)] + pub fn sfde(&self) -> SFDE_R { + SFDE_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Encoding Format"] + #[inline(always)] + pub fn enc(&self) -> ENC_R { + ENC_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 13 - Parity Mode"] + #[inline(always)] + pub fn pmode(&self) -> PMODE_R { + PMODE_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 16 - Transmitter Enable"] + #[inline(always)] + pub fn txen(&self) -> TXEN_R { + TXEN_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&self) -> RXEN_R { + RXEN_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bits 24:25 - LIN Command"] + #[inline(always)] + pub fn lincmd(&self) -> LINCMD_R { + LINCMD_R::new(((self.bits >> 24) & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&mut self) -> CHSIZE_W { + CHSIZE_W { w: self } + } + #[doc = "Bit 6 - Stop Bit Mode"] + #[inline(always)] + pub fn sbmode(&mut self) -> SBMODE_W { + SBMODE_W { w: self } + } + #[doc = "Bit 8 - Collision Detection Enable"] + #[inline(always)] + pub fn colden(&mut self) -> COLDEN_W { + COLDEN_W { w: self } + } + #[doc = "Bit 9 - Start of Frame Detection Enable"] + #[inline(always)] + pub fn sfde(&mut self) -> SFDE_W { + SFDE_W { w: self } + } + #[doc = "Bit 10 - Encoding Format"] + #[inline(always)] + pub fn enc(&mut self) -> ENC_W { + ENC_W { w: self } + } + #[doc = "Bit 13 - Parity Mode"] + #[inline(always)] + pub fn pmode(&mut self) -> PMODE_W { + PMODE_W { w: self } + } + #[doc = "Bit 16 - Transmitter Enable"] + #[inline(always)] + pub fn txen(&mut self) -> TXEN_W { + TXEN_W { w: self } + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&mut self) -> RXEN_W { + RXEN_W { w: self } + } + #[doc = "Bits 24:25 - LIN Command"] + #[inline(always)] + pub fn lincmd(&mut self) -> LINCMD_W { + LINCMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/sercom0/usart_int/ctrlc.rs b/pac/atsamc20e/src/sercom0/usart_int/ctrlc.rs new file mode 100644 index 000000000000..e2182cc7f768 --- /dev/null +++ b/pac/atsamc20e/src/sercom0/usart_int/ctrlc.rs @@ -0,0 +1,177 @@ +#[doc = "Register `CTRLC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `GTIME` reader - RS485 Guard Time"] +pub struct GTIME_R(crate::FieldReader); +impl GTIME_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + GTIME_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GTIME_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GTIME` writer - RS485 Guard Time"] +pub struct GTIME_W<'a> { + w: &'a mut W, +} +impl<'a> GTIME_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Field `BRKLEN` reader - LIN Master Break Length"] +pub struct BRKLEN_R(crate::FieldReader); +impl BRKLEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BRKLEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BRKLEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BRKLEN` writer - LIN Master Break Length"] +pub struct BRKLEN_W<'a> { + w: &'a mut W, +} +impl<'a> BRKLEN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 8)) | ((value as u32 & 0x03) << 8); + self.w + } +} +#[doc = "Field `HDRDLY` reader - LIN Master Header Delay"] +pub struct HDRDLY_R(crate::FieldReader); +impl HDRDLY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + HDRDLY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HDRDLY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HDRDLY` writer - LIN Master Header Delay"] +pub struct HDRDLY_W<'a> { + w: &'a mut W, +} +impl<'a> HDRDLY_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 10)) | ((value as u32 & 0x03) << 10); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - RS485 Guard Time"] + #[inline(always)] + pub fn gtime(&self) -> GTIME_R { + GTIME_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bits 8:9 - LIN Master Break Length"] + #[inline(always)] + pub fn brklen(&self) -> BRKLEN_R { + BRKLEN_R::new(((self.bits >> 8) & 0x03) as u8) + } + #[doc = "Bits 10:11 - LIN Master Header Delay"] + #[inline(always)] + pub fn hdrdly(&self) -> HDRDLY_R { + HDRDLY_R::new(((self.bits >> 10) & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - RS485 Guard Time"] + #[inline(always)] + pub fn gtime(&mut self) -> GTIME_W { + GTIME_W { w: self } + } + #[doc = "Bits 8:9 - LIN Master Break Length"] + #[inline(always)] + pub fn brklen(&mut self) -> BRKLEN_W { + BRKLEN_W { w: self } + } + #[doc = "Bits 10:11 - LIN Master Header Delay"] + #[inline(always)] + pub fn hdrdly(&mut self) -> HDRDLY_W { + HDRDLY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Control C\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlc](index.html) module"] +pub struct CTRLC_SPEC; +impl crate::RegisterSpec for CTRLC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlc::R](R) reader structure"] +impl crate::Readable for CTRLC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlc::W](W) writer structure"] +impl crate::Writable for CTRLC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLC to value 0"] +impl crate::Resettable for CTRLC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/sercom0/usart_int/data.rs b/pac/atsamc20e/src/sercom0/usart_int/data.rs new file mode 100644 index 000000000000..19d74c337d44 --- /dev/null +++ b/pac/atsamc20e/src/sercom0/usart_int/data.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data Value"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data Value"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01ff) | (value as u16 & 0x01ff); + self.w + } +} +impl R { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new((self.bits & 0x01ff) as u16) + } +} +impl W { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/sercom0/usart_int/dbgctrl.rs b/pac/atsamc20e/src/sercom0/usart_int/dbgctrl.rs new file mode 100644 index 000000000000..0ac5b9c7b902 --- /dev/null +++ b/pac/atsamc20e/src/sercom0/usart_int/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGSTOP` reader - Debug Mode"] +pub struct DBGSTOP_R(crate::FieldReader); +impl DBGSTOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGSTOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGSTOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGSTOP` writer - Debug Mode"] +pub struct DBGSTOP_W<'a> { + w: &'a mut W, +} +impl<'a> DBGSTOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&self) -> DBGSTOP_R { + DBGSTOP_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&mut self) -> DBGSTOP_W { + DBGSTOP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/sercom0/usart_int/intenclr.rs b/pac/atsamc20e/src/sercom0/usart_int/intenclr.rs new file mode 100644 index 000000000000..5ad23ad15636 --- /dev/null +++ b/pac/atsamc20e/src/sercom0/usart_int/intenclr.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Disable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Disable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Disable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Disable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Disable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Disable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RXS` reader - Receive Start Interrupt Disable"] +pub struct RXS_R(crate::FieldReader); +impl RXS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXS` writer - Receive Start Interrupt Disable"] +pub struct RXS_W<'a> { + w: &'a mut W, +} +impl<'a> RXS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CTSIC` reader - Clear To Send Input Change Interrupt Disable"] +pub struct CTSIC_R(crate::FieldReader); +impl CTSIC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTSIC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTSIC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTSIC` writer - Clear To Send Input Change Interrupt Disable"] +pub struct CTSIC_W<'a> { + w: &'a mut W, +} +impl<'a> CTSIC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RXBRK` reader - Break Received Interrupt Disable"] +pub struct RXBRK_R(crate::FieldReader); +impl RXBRK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXBRK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXBRK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXBRK` writer - Break Received Interrupt Disable"] +pub struct RXBRK_W<'a> { + w: &'a mut W, +} +impl<'a> RXBRK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Disable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Disable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Receive Start Interrupt Disable"] + #[inline(always)] + pub fn rxs(&self) -> RXS_R { + RXS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Disable"] + #[inline(always)] + pub fn ctsic(&self) -> CTSIC_R { + CTSIC_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Break Received Interrupt Disable"] + #[inline(always)] + pub fn rxbrk(&self) -> RXBRK_R { + RXBRK_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Receive Start Interrupt Disable"] + #[inline(always)] + pub fn rxs(&mut self) -> RXS_W { + RXS_W { w: self } + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Disable"] + #[inline(always)] + pub fn ctsic(&mut self) -> CTSIC_W { + CTSIC_W { w: self } + } + #[doc = "Bit 5 - Break Received Interrupt Disable"] + #[inline(always)] + pub fn rxbrk(&mut self) -> RXBRK_W { + RXBRK_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/sercom0/usart_int/intenset.rs b/pac/atsamc20e/src/sercom0/usart_int/intenset.rs new file mode 100644 index 000000000000..457f440e13e9 --- /dev/null +++ b/pac/atsamc20e/src/sercom0/usart_int/intenset.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Enable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Enable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Enable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Enable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Enable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Enable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RXS` reader - Receive Start Interrupt Enable"] +pub struct RXS_R(crate::FieldReader); +impl RXS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXS` writer - Receive Start Interrupt Enable"] +pub struct RXS_W<'a> { + w: &'a mut W, +} +impl<'a> RXS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CTSIC` reader - Clear To Send Input Change Interrupt Enable"] +pub struct CTSIC_R(crate::FieldReader); +impl CTSIC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTSIC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTSIC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTSIC` writer - Clear To Send Input Change Interrupt Enable"] +pub struct CTSIC_W<'a> { + w: &'a mut W, +} +impl<'a> CTSIC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RXBRK` reader - Break Received Interrupt Enable"] +pub struct RXBRK_R(crate::FieldReader); +impl RXBRK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXBRK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXBRK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXBRK` writer - Break Received Interrupt Enable"] +pub struct RXBRK_W<'a> { + w: &'a mut W, +} +impl<'a> RXBRK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Receive Start Interrupt Enable"] + #[inline(always)] + pub fn rxs(&self) -> RXS_R { + RXS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Enable"] + #[inline(always)] + pub fn ctsic(&self) -> CTSIC_R { + CTSIC_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Break Received Interrupt Enable"] + #[inline(always)] + pub fn rxbrk(&self) -> RXBRK_R { + RXBRK_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Receive Start Interrupt Enable"] + #[inline(always)] + pub fn rxs(&mut self) -> RXS_W { + RXS_W { w: self } + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Enable"] + #[inline(always)] + pub fn ctsic(&mut self) -> CTSIC_W { + CTSIC_W { w: self } + } + #[doc = "Bit 5 - Break Received Interrupt Enable"] + #[inline(always)] + pub fn rxbrk(&mut self) -> RXBRK_W { + RXBRK_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/sercom0/usart_int/intflag.rs b/pac/atsamc20e/src/sercom0/usart_int/intflag.rs new file mode 100644 index 000000000000..a6a26321b8c4 --- /dev/null +++ b/pac/atsamc20e/src/sercom0/usart_int/intflag.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RXS` reader - Receive Start Interrupt"] +pub struct RXS_R(crate::FieldReader); +impl RXS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXS` writer - Receive Start Interrupt"] +pub struct RXS_W<'a> { + w: &'a mut W, +} +impl<'a> RXS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CTSIC` reader - Clear To Send Input Change Interrupt"] +pub struct CTSIC_R(crate::FieldReader); +impl CTSIC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTSIC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTSIC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTSIC` writer - Clear To Send Input Change Interrupt"] +pub struct CTSIC_W<'a> { + w: &'a mut W, +} +impl<'a> CTSIC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RXBRK` reader - Break Received Interrupt"] +pub struct RXBRK_R(crate::FieldReader); +impl RXBRK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXBRK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXBRK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXBRK` writer - Break Received Interrupt"] +pub struct RXBRK_W<'a> { + w: &'a mut W, +} +impl<'a> RXBRK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Receive Start Interrupt"] + #[inline(always)] + pub fn rxs(&self) -> RXS_R { + RXS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt"] + #[inline(always)] + pub fn ctsic(&self) -> CTSIC_R { + CTSIC_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Break Received Interrupt"] + #[inline(always)] + pub fn rxbrk(&self) -> RXBRK_R { + RXBRK_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Receive Start Interrupt"] + #[inline(always)] + pub fn rxs(&mut self) -> RXS_W { + RXS_W { w: self } + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt"] + #[inline(always)] + pub fn ctsic(&mut self) -> CTSIC_W { + CTSIC_W { w: self } + } + #[doc = "Bit 5 - Break Received Interrupt"] + #[inline(always)] + pub fn rxbrk(&mut self) -> RXBRK_W { + RXBRK_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/sercom0/usart_int/rxpl.rs b/pac/atsamc20e/src/sercom0/usart_int/rxpl.rs new file mode 100644 index 000000000000..324cbac371c1 --- /dev/null +++ b/pac/atsamc20e/src/sercom0/usart_int/rxpl.rs @@ -0,0 +1,103 @@ +#[doc = "Register `RXPL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RXPL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RXPL` reader - Receive Pulse Length"] +pub struct RXPL_R(crate::FieldReader); +impl RXPL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RXPL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXPL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXPL` writer - Receive Pulse Length"] +pub struct RXPL_W<'a> { + w: &'a mut W, +} +impl<'a> RXPL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Receive Pulse Length"] + #[inline(always)] + pub fn rxpl(&self) -> RXPL_R { + RXPL_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Receive Pulse Length"] + #[inline(always)] + pub fn rxpl(&mut self) -> RXPL_W { + RXPL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Receive Pulse Length\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxpl](index.html) module"] +pub struct RXPL_SPEC; +impl crate::RegisterSpec for RXPL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [rxpl::R](R) reader structure"] +impl crate::Readable for RXPL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rxpl::W](W) writer structure"] +impl crate::Writable for RXPL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RXPL to value 0"] +impl crate::Resettable for RXPL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/sercom0/usart_int/status.rs b/pac/atsamc20e/src/sercom0/usart_int/status.rs new file mode 100644 index 000000000000..1a92018a359b --- /dev/null +++ b/pac/atsamc20e/src/sercom0/usart_int/status.rs @@ -0,0 +1,395 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PERR` reader - Parity Error"] +pub struct PERR_R(crate::FieldReader); +impl PERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERR` writer - Parity Error"] +pub struct PERR_W<'a> { + w: &'a mut W, +} +impl<'a> PERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `FERR` reader - Frame Error"] +pub struct FERR_R(crate::FieldReader); +impl FERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FERR` writer - Frame Error"] +pub struct FERR_W<'a> { + w: &'a mut W, +} +impl<'a> FERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `BUFOVF` reader - Buffer Overflow"] +pub struct BUFOVF_R(crate::FieldReader); +impl BUFOVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUFOVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUFOVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUFOVF` writer - Buffer Overflow"] +pub struct BUFOVF_W<'a> { + w: &'a mut W, +} +impl<'a> BUFOVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CTS` reader - Clear To Send"] +pub struct CTS_R(crate::FieldReader); +impl CTS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTS` writer - Clear To Send"] +pub struct CTS_W<'a> { + w: &'a mut W, +} +impl<'a> CTS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ISF` reader - Inconsistent Sync Field"] +pub struct ISF_R(crate::FieldReader); +impl ISF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ISF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ISF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ISF` writer - Inconsistent Sync Field"] +pub struct ISF_W<'a> { + w: &'a mut W, +} +impl<'a> ISF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `COLL` reader - Collision Detected"] +pub struct COLL_R(crate::FieldReader); +impl COLL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COLL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COLL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COLL` writer - Collision Detected"] +pub struct COLL_W<'a> { + w: &'a mut W, +} +impl<'a> COLL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `TXE` reader - Transmitter Empty"] +pub struct TXE_R(crate::FieldReader); +impl TXE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXE` writer - Transmitter Empty"] +pub struct TXE_W<'a> { + w: &'a mut W, +} +impl<'a> TXE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - Parity Error"] + #[inline(always)] + pub fn perr(&self) -> PERR_R { + PERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Frame Error"] + #[inline(always)] + pub fn ferr(&self) -> FERR_R { + FERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&self) -> BUFOVF_R { + BUFOVF_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Clear To Send"] + #[inline(always)] + pub fn cts(&self) -> CTS_R { + CTS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Inconsistent Sync Field"] + #[inline(always)] + pub fn isf(&self) -> ISF_R { + ISF_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Collision Detected"] + #[inline(always)] + pub fn coll(&self) -> COLL_R { + COLL_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Transmitter Empty"] + #[inline(always)] + pub fn txe(&self) -> TXE_R { + TXE_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Parity Error"] + #[inline(always)] + pub fn perr(&mut self) -> PERR_W { + PERR_W { w: self } + } + #[doc = "Bit 1 - Frame Error"] + #[inline(always)] + pub fn ferr(&mut self) -> FERR_W { + FERR_W { w: self } + } + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&mut self) -> BUFOVF_W { + BUFOVF_W { w: self } + } + #[doc = "Bit 3 - Clear To Send"] + #[inline(always)] + pub fn cts(&mut self) -> CTS_W { + CTS_W { w: self } + } + #[doc = "Bit 4 - Inconsistent Sync Field"] + #[inline(always)] + pub fn isf(&mut self) -> ISF_W { + ISF_W { w: self } + } + #[doc = "Bit 5 - Collision Detected"] + #[inline(always)] + pub fn coll(&mut self) -> COLL_W { + COLL_W { w: self } + } + #[doc = "Bit 6 - Transmitter Empty"] + #[inline(always)] + pub fn txe(&mut self) -> TXE_W { + TXE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/sercom0/usart_int/syncbusy.rs b/pac/atsamc20e/src/sercom0/usart_int/syncbusy.rs new file mode 100644 index 000000000000..5dea9a5a7bab --- /dev/null +++ b/pac/atsamc20e/src/sercom0/usart_int/syncbusy.rs @@ -0,0 +1,93 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - SERCOM Enable Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLB` reader - CTRLB Synchronization Busy"] +pub struct CTRLB_R(crate::FieldReader); +impl CTRLB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM Enable Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - CTRLB Synchronization Busy"] + #[inline(always)] + pub fn ctrlb(&self) -> CTRLB_R { + CTRLB_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +#[doc = "USART_INT Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/supc.rs b/pac/atsamc20e/src/supc.rs new file mode 100644 index 000000000000..452d8f3f9613 --- /dev/null +++ b/pac/atsamc20e/src/supc.rs @@ -0,0 +1,52 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x04 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x08 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x0c - Power and Clocks Status"] + pub status: crate::Reg, + #[doc = "0x10 - BODVDD Control"] + pub bodvdd: crate::Reg, + #[doc = "0x14 - BODCORE Control"] + pub bodcore: crate::Reg, + #[doc = "0x18 - VREG Control"] + pub vreg: crate::Reg, + #[doc = "0x1c - VREF Control"] + pub vref: crate::Reg, +} +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Power and Clocks Status"] +pub mod status; +#[doc = "BODVDD register accessor: an alias for `Reg`"] +pub type BODVDD = crate::Reg; +#[doc = "BODVDD Control"] +pub mod bodvdd; +#[doc = "BODCORE register accessor: an alias for `Reg`"] +pub type BODCORE = crate::Reg; +#[doc = "BODCORE Control"] +pub mod bodcore; +#[doc = "VREG register accessor: an alias for `Reg`"] +pub type VREG = crate::Reg; +#[doc = "VREG Control"] +pub mod vreg; +#[doc = "VREF register accessor: an alias for `Reg`"] +pub type VREF = crate::Reg; +#[doc = "VREF Control"] +pub mod vref; diff --git a/pac/atsamc20e/src/supc/bodcore.rs b/pac/atsamc20e/src/supc/bodcore.rs new file mode 100644 index 000000000000..670dec8e048c --- /dev/null +++ b/pac/atsamc20e/src/supc/bodcore.rs @@ -0,0 +1,705 @@ +#[doc = "Register `BODCORE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BODCORE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `HYST` reader - Hysteresis Enable"] +pub struct HYST_R(crate::FieldReader); +impl HYST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HYST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HYST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HYST` writer - Hysteresis Enable"] +pub struct HYST_W<'a> { + w: &'a mut W, +} +impl<'a> HYST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Action when Threshold Crossed\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum ACTION_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: The BODCORE generates a reset"] + RESET = 1, + #[doc = "2: The BODCORE generates an interrupt"] + INT = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: ACTION_A) -> Self { + variant as _ + } +} +#[doc = "Field `ACTION` reader - Action when Threshold Crossed"] +pub struct ACTION_R(crate::FieldReader); +impl ACTION_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ACTION_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(ACTION_A::NONE), + 1 => Some(ACTION_A::RESET), + 2 => Some(ACTION_A::INT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == ACTION_A::NONE + } + #[doc = "Checks if the value of the field is `RESET`"] + #[inline(always)] + pub fn is_reset(&self) -> bool { + **self == ACTION_A::RESET + } + #[doc = "Checks if the value of the field is `INT`"] + #[inline(always)] + pub fn is_int(&self) -> bool { + **self == ACTION_A::INT + } +} +impl core::ops::Deref for ACTION_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ACTION` writer - Action when Threshold Crossed"] +pub struct ACTION_W<'a> { + w: &'a mut W, +} +impl<'a> ACTION_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: ACTION_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(ACTION_A::NONE) + } + #[doc = "The BODCORE generates a reset"] + #[inline(always)] + pub fn reset(self) -> &'a mut W { + self.variant(ACTION_A::RESET) + } + #[doc = "The BODCORE generates an interrupt"] + #[inline(always)] + pub fn int(self) -> &'a mut W { + self.variant(ACTION_A::INT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 3)) | ((value as u32 & 0x03) << 3); + self.w + } +} +#[doc = "Field `STDBYCFG` reader - Configuration in Standby mode"] +pub struct STDBYCFG_R(crate::FieldReader); +impl STDBYCFG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STDBYCFG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STDBYCFG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STDBYCFG` writer - Configuration in Standby mode"] +pub struct STDBYCFG_W<'a> { + w: &'a mut W, +} +impl<'a> STDBYCFG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ACTCFG` reader - Configuration in Active mode"] +pub struct ACTCFG_R(crate::FieldReader); +impl ACTCFG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ACTCFG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ACTCFG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ACTCFG` writer - Configuration in Active mode"] +pub struct ACTCFG_W<'a> { + w: &'a mut W, +} +impl<'a> ACTCFG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Prescaler Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PSEL_A { + #[doc = "0: Divide clock by 2"] + DIV2 = 0, + #[doc = "1: Divide clock by 4"] + DIV4 = 1, + #[doc = "2: Divide clock by 8"] + DIV8 = 2, + #[doc = "3: Divide clock by 16"] + DIV16 = 3, + #[doc = "4: Divide clock by 32"] + DIV32 = 4, + #[doc = "5: Divide clock by 64"] + DIV64 = 5, + #[doc = "6: Divide clock by 128"] + DIV128 = 6, + #[doc = "7: Divide clock by 256"] + DIV256 = 7, + #[doc = "8: Divide clock by 512"] + DIV512 = 8, + #[doc = "9: Divide clock by 1024"] + DIV1024 = 9, + #[doc = "10: Divide clock by 2048"] + DIV2048 = 10, + #[doc = "11: Divide clock by 4096"] + DIV4096 = 11, + #[doc = "12: Divide clock by 8192"] + DIV8192 = 12, + #[doc = "13: Divide clock by 16384"] + DIV16384 = 13, + #[doc = "14: Divide clock by 32768"] + DIV32768 = 14, + #[doc = "15: Divide clock by 65536"] + DIV65536 = 15, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `PSEL` reader - Prescaler Select"] +pub struct PSEL_R(crate::FieldReader); +impl PSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PSEL_A { + match self.bits { + 0 => PSEL_A::DIV2, + 1 => PSEL_A::DIV4, + 2 => PSEL_A::DIV8, + 3 => PSEL_A::DIV16, + 4 => PSEL_A::DIV32, + 5 => PSEL_A::DIV64, + 6 => PSEL_A::DIV128, + 7 => PSEL_A::DIV256, + 8 => PSEL_A::DIV512, + 9 => PSEL_A::DIV1024, + 10 => PSEL_A::DIV2048, + 11 => PSEL_A::DIV4096, + 12 => PSEL_A::DIV8192, + 13 => PSEL_A::DIV16384, + 14 => PSEL_A::DIV32768, + 15 => PSEL_A::DIV65536, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PSEL_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PSEL_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PSEL_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PSEL_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == PSEL_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PSEL_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == PSEL_A::DIV128 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PSEL_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV512`"] + #[inline(always)] + pub fn is_div512(&self) -> bool { + **self == PSEL_A::DIV512 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PSEL_A::DIV1024 + } + #[doc = "Checks if the value of the field is `DIV2048`"] + #[inline(always)] + pub fn is_div2048(&self) -> bool { + **self == PSEL_A::DIV2048 + } + #[doc = "Checks if the value of the field is `DIV4096`"] + #[inline(always)] + pub fn is_div4096(&self) -> bool { + **self == PSEL_A::DIV4096 + } + #[doc = "Checks if the value of the field is `DIV8192`"] + #[inline(always)] + pub fn is_div8192(&self) -> bool { + **self == PSEL_A::DIV8192 + } + #[doc = "Checks if the value of the field is `DIV16384`"] + #[inline(always)] + pub fn is_div16384(&self) -> bool { + **self == PSEL_A::DIV16384 + } + #[doc = "Checks if the value of the field is `DIV32768`"] + #[inline(always)] + pub fn is_div32768(&self) -> bool { + **self == PSEL_A::DIV32768 + } + #[doc = "Checks if the value of the field is `DIV65536`"] + #[inline(always)] + pub fn is_div65536(&self) -> bool { + **self == PSEL_A::DIV65536 + } +} +impl core::ops::Deref for PSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PSEL` writer - Prescaler Select"] +pub struct PSEL_W<'a> { + w: &'a mut W, +} +impl<'a> PSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PSEL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Divide clock by 2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PSEL_A::DIV2) + } + #[doc = "Divide clock by 4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PSEL_A::DIV4) + } + #[doc = "Divide clock by 8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PSEL_A::DIV8) + } + #[doc = "Divide clock by 16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PSEL_A::DIV16) + } + #[doc = "Divide clock by 32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(PSEL_A::DIV32) + } + #[doc = "Divide clock by 64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PSEL_A::DIV64) + } + #[doc = "Divide clock by 128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(PSEL_A::DIV128) + } + #[doc = "Divide clock by 256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PSEL_A::DIV256) + } + #[doc = "Divide clock by 512"] + #[inline(always)] + pub fn div512(self) -> &'a mut W { + self.variant(PSEL_A::DIV512) + } + #[doc = "Divide clock by 1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PSEL_A::DIV1024) + } + #[doc = "Divide clock by 2048"] + #[inline(always)] + pub fn div2048(self) -> &'a mut W { + self.variant(PSEL_A::DIV2048) + } + #[doc = "Divide clock by 4096"] + #[inline(always)] + pub fn div4096(self) -> &'a mut W { + self.variant(PSEL_A::DIV4096) + } + #[doc = "Divide clock by 8192"] + #[inline(always)] + pub fn div8192(self) -> &'a mut W { + self.variant(PSEL_A::DIV8192) + } + #[doc = "Divide clock by 16384"] + #[inline(always)] + pub fn div16384(self) -> &'a mut W { + self.variant(PSEL_A::DIV16384) + } + #[doc = "Divide clock by 32768"] + #[inline(always)] + pub fn div32768(self) -> &'a mut W { + self.variant(PSEL_A::DIV32768) + } + #[doc = "Divide clock by 65536"] + #[inline(always)] + pub fn div65536(self) -> &'a mut W { + self.variant(PSEL_A::DIV65536) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 12)) | ((value as u32 & 0x0f) << 12); + self.w + } +} +#[doc = "Field `LEVEL` reader - Threshold Level"] +pub struct LEVEL_R(crate::FieldReader); +impl LEVEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LEVEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LEVEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LEVEL` writer - Threshold Level"] +pub struct LEVEL_W<'a> { + w: &'a mut W, +} +impl<'a> LEVEL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 16)) | ((value as u32 & 0x3f) << 16); + self.w + } +} +impl R { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Hysteresis Enable"] + #[inline(always)] + pub fn hyst(&self) -> HYST_R { + HYST_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 3:4 - Action when Threshold Crossed"] + #[inline(always)] + pub fn action(&self) -> ACTION_R { + ACTION_R::new(((self.bits >> 3) & 0x03) as u8) + } + #[doc = "Bit 5 - Configuration in Standby mode"] + #[inline(always)] + pub fn stdbycfg(&self) -> STDBYCFG_R { + STDBYCFG_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 8 - Configuration in Active mode"] + #[inline(always)] + pub fn actcfg(&self) -> ACTCFG_R { + ACTCFG_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bits 12:15 - Prescaler Select"] + #[inline(always)] + pub fn psel(&self) -> PSEL_R { + PSEL_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:21 - Threshold Level"] + #[inline(always)] + pub fn level(&self) -> LEVEL_R { + LEVEL_R::new(((self.bits >> 16) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - Hysteresis Enable"] + #[inline(always)] + pub fn hyst(&mut self) -> HYST_W { + HYST_W { w: self } + } + #[doc = "Bits 3:4 - Action when Threshold Crossed"] + #[inline(always)] + pub fn action(&mut self) -> ACTION_W { + ACTION_W { w: self } + } + #[doc = "Bit 5 - Configuration in Standby mode"] + #[inline(always)] + pub fn stdbycfg(&mut self) -> STDBYCFG_W { + STDBYCFG_W { w: self } + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 8 - Configuration in Active mode"] + #[inline(always)] + pub fn actcfg(&mut self) -> ACTCFG_W { + ACTCFG_W { w: self } + } + #[doc = "Bits 12:15 - Prescaler Select"] + #[inline(always)] + pub fn psel(&mut self) -> PSEL_W { + PSEL_W { w: self } + } + #[doc = "Bits 16:21 - Threshold Level"] + #[inline(always)] + pub fn level(&mut self) -> LEVEL_W { + LEVEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "BODCORE Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [bodcore](index.html) module"] +pub struct BODCORE_SPEC; +impl crate::RegisterSpec for BODCORE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [bodcore::R](R) reader structure"] +impl crate::Readable for BODCORE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [bodcore::W](W) writer structure"] +impl crate::Writable for BODCORE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BODCORE to value 0"] +impl crate::Resettable for BODCORE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/supc/bodvdd.rs b/pac/atsamc20e/src/supc/bodvdd.rs new file mode 100644 index 000000000000..f5cbfffb6453 --- /dev/null +++ b/pac/atsamc20e/src/supc/bodvdd.rs @@ -0,0 +1,705 @@ +#[doc = "Register `BODVDD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BODVDD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `HYST` reader - Hysteresis Enable"] +pub struct HYST_R(crate::FieldReader); +impl HYST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HYST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HYST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HYST` writer - Hysteresis Enable"] +pub struct HYST_W<'a> { + w: &'a mut W, +} +impl<'a> HYST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Action when Threshold Crossed\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum ACTION_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: The BODVDD generates a reset"] + RESET = 1, + #[doc = "2: The BODVDD generates an interrupt"] + INT = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: ACTION_A) -> Self { + variant as _ + } +} +#[doc = "Field `ACTION` reader - Action when Threshold Crossed"] +pub struct ACTION_R(crate::FieldReader); +impl ACTION_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ACTION_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(ACTION_A::NONE), + 1 => Some(ACTION_A::RESET), + 2 => Some(ACTION_A::INT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == ACTION_A::NONE + } + #[doc = "Checks if the value of the field is `RESET`"] + #[inline(always)] + pub fn is_reset(&self) -> bool { + **self == ACTION_A::RESET + } + #[doc = "Checks if the value of the field is `INT`"] + #[inline(always)] + pub fn is_int(&self) -> bool { + **self == ACTION_A::INT + } +} +impl core::ops::Deref for ACTION_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ACTION` writer - Action when Threshold Crossed"] +pub struct ACTION_W<'a> { + w: &'a mut W, +} +impl<'a> ACTION_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: ACTION_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(ACTION_A::NONE) + } + #[doc = "The BODVDD generates a reset"] + #[inline(always)] + pub fn reset(self) -> &'a mut W { + self.variant(ACTION_A::RESET) + } + #[doc = "The BODVDD generates an interrupt"] + #[inline(always)] + pub fn int(self) -> &'a mut W { + self.variant(ACTION_A::INT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 3)) | ((value as u32 & 0x03) << 3); + self.w + } +} +#[doc = "Field `STDBYCFG` reader - Configuration in Standby mode"] +pub struct STDBYCFG_R(crate::FieldReader); +impl STDBYCFG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STDBYCFG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STDBYCFG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STDBYCFG` writer - Configuration in Standby mode"] +pub struct STDBYCFG_W<'a> { + w: &'a mut W, +} +impl<'a> STDBYCFG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ACTCFG` reader - Configuration in Active mode"] +pub struct ACTCFG_R(crate::FieldReader); +impl ACTCFG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ACTCFG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ACTCFG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ACTCFG` writer - Configuration in Active mode"] +pub struct ACTCFG_W<'a> { + w: &'a mut W, +} +impl<'a> ACTCFG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Prescaler Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PSEL_A { + #[doc = "0: Divide clock by 2"] + DIV2 = 0, + #[doc = "1: Divide clock by 4"] + DIV4 = 1, + #[doc = "2: Divide clock by 8"] + DIV8 = 2, + #[doc = "3: Divide clock by 16"] + DIV16 = 3, + #[doc = "4: Divide clock by 32"] + DIV32 = 4, + #[doc = "5: Divide clock by 64"] + DIV64 = 5, + #[doc = "6: Divide clock by 128"] + DIV128 = 6, + #[doc = "7: Divide clock by 256"] + DIV256 = 7, + #[doc = "8: Divide clock by 512"] + DIV512 = 8, + #[doc = "9: Divide clock by 1024"] + DIV1024 = 9, + #[doc = "10: Divide clock by 2048"] + DIV2048 = 10, + #[doc = "11: Divide clock by 4096"] + DIV4096 = 11, + #[doc = "12: Divide clock by 8192"] + DIV8192 = 12, + #[doc = "13: Divide clock by 16384"] + DIV16384 = 13, + #[doc = "14: Divide clock by 32768"] + DIV32768 = 14, + #[doc = "15: Divide clock by 65536"] + DIV65536 = 15, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `PSEL` reader - Prescaler Select"] +pub struct PSEL_R(crate::FieldReader); +impl PSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PSEL_A { + match self.bits { + 0 => PSEL_A::DIV2, + 1 => PSEL_A::DIV4, + 2 => PSEL_A::DIV8, + 3 => PSEL_A::DIV16, + 4 => PSEL_A::DIV32, + 5 => PSEL_A::DIV64, + 6 => PSEL_A::DIV128, + 7 => PSEL_A::DIV256, + 8 => PSEL_A::DIV512, + 9 => PSEL_A::DIV1024, + 10 => PSEL_A::DIV2048, + 11 => PSEL_A::DIV4096, + 12 => PSEL_A::DIV8192, + 13 => PSEL_A::DIV16384, + 14 => PSEL_A::DIV32768, + 15 => PSEL_A::DIV65536, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PSEL_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PSEL_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PSEL_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PSEL_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == PSEL_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PSEL_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == PSEL_A::DIV128 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PSEL_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV512`"] + #[inline(always)] + pub fn is_div512(&self) -> bool { + **self == PSEL_A::DIV512 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PSEL_A::DIV1024 + } + #[doc = "Checks if the value of the field is `DIV2048`"] + #[inline(always)] + pub fn is_div2048(&self) -> bool { + **self == PSEL_A::DIV2048 + } + #[doc = "Checks if the value of the field is `DIV4096`"] + #[inline(always)] + pub fn is_div4096(&self) -> bool { + **self == PSEL_A::DIV4096 + } + #[doc = "Checks if the value of the field is `DIV8192`"] + #[inline(always)] + pub fn is_div8192(&self) -> bool { + **self == PSEL_A::DIV8192 + } + #[doc = "Checks if the value of the field is `DIV16384`"] + #[inline(always)] + pub fn is_div16384(&self) -> bool { + **self == PSEL_A::DIV16384 + } + #[doc = "Checks if the value of the field is `DIV32768`"] + #[inline(always)] + pub fn is_div32768(&self) -> bool { + **self == PSEL_A::DIV32768 + } + #[doc = "Checks if the value of the field is `DIV65536`"] + #[inline(always)] + pub fn is_div65536(&self) -> bool { + **self == PSEL_A::DIV65536 + } +} +impl core::ops::Deref for PSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PSEL` writer - Prescaler Select"] +pub struct PSEL_W<'a> { + w: &'a mut W, +} +impl<'a> PSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PSEL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Divide clock by 2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PSEL_A::DIV2) + } + #[doc = "Divide clock by 4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PSEL_A::DIV4) + } + #[doc = "Divide clock by 8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PSEL_A::DIV8) + } + #[doc = "Divide clock by 16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PSEL_A::DIV16) + } + #[doc = "Divide clock by 32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(PSEL_A::DIV32) + } + #[doc = "Divide clock by 64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PSEL_A::DIV64) + } + #[doc = "Divide clock by 128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(PSEL_A::DIV128) + } + #[doc = "Divide clock by 256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PSEL_A::DIV256) + } + #[doc = "Divide clock by 512"] + #[inline(always)] + pub fn div512(self) -> &'a mut W { + self.variant(PSEL_A::DIV512) + } + #[doc = "Divide clock by 1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PSEL_A::DIV1024) + } + #[doc = "Divide clock by 2048"] + #[inline(always)] + pub fn div2048(self) -> &'a mut W { + self.variant(PSEL_A::DIV2048) + } + #[doc = "Divide clock by 4096"] + #[inline(always)] + pub fn div4096(self) -> &'a mut W { + self.variant(PSEL_A::DIV4096) + } + #[doc = "Divide clock by 8192"] + #[inline(always)] + pub fn div8192(self) -> &'a mut W { + self.variant(PSEL_A::DIV8192) + } + #[doc = "Divide clock by 16384"] + #[inline(always)] + pub fn div16384(self) -> &'a mut W { + self.variant(PSEL_A::DIV16384) + } + #[doc = "Divide clock by 32768"] + #[inline(always)] + pub fn div32768(self) -> &'a mut W { + self.variant(PSEL_A::DIV32768) + } + #[doc = "Divide clock by 65536"] + #[inline(always)] + pub fn div65536(self) -> &'a mut W { + self.variant(PSEL_A::DIV65536) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 12)) | ((value as u32 & 0x0f) << 12); + self.w + } +} +#[doc = "Field `LEVEL` reader - Threshold Level for VDD"] +pub struct LEVEL_R(crate::FieldReader); +impl LEVEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LEVEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LEVEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LEVEL` writer - Threshold Level for VDD"] +pub struct LEVEL_W<'a> { + w: &'a mut W, +} +impl<'a> LEVEL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 16)) | ((value as u32 & 0x3f) << 16); + self.w + } +} +impl R { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Hysteresis Enable"] + #[inline(always)] + pub fn hyst(&self) -> HYST_R { + HYST_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 3:4 - Action when Threshold Crossed"] + #[inline(always)] + pub fn action(&self) -> ACTION_R { + ACTION_R::new(((self.bits >> 3) & 0x03) as u8) + } + #[doc = "Bit 5 - Configuration in Standby mode"] + #[inline(always)] + pub fn stdbycfg(&self) -> STDBYCFG_R { + STDBYCFG_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 8 - Configuration in Active mode"] + #[inline(always)] + pub fn actcfg(&self) -> ACTCFG_R { + ACTCFG_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bits 12:15 - Prescaler Select"] + #[inline(always)] + pub fn psel(&self) -> PSEL_R { + PSEL_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:21 - Threshold Level for VDD"] + #[inline(always)] + pub fn level(&self) -> LEVEL_R { + LEVEL_R::new(((self.bits >> 16) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - Hysteresis Enable"] + #[inline(always)] + pub fn hyst(&mut self) -> HYST_W { + HYST_W { w: self } + } + #[doc = "Bits 3:4 - Action when Threshold Crossed"] + #[inline(always)] + pub fn action(&mut self) -> ACTION_W { + ACTION_W { w: self } + } + #[doc = "Bit 5 - Configuration in Standby mode"] + #[inline(always)] + pub fn stdbycfg(&mut self) -> STDBYCFG_W { + STDBYCFG_W { w: self } + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 8 - Configuration in Active mode"] + #[inline(always)] + pub fn actcfg(&mut self) -> ACTCFG_W { + ACTCFG_W { w: self } + } + #[doc = "Bits 12:15 - Prescaler Select"] + #[inline(always)] + pub fn psel(&mut self) -> PSEL_W { + PSEL_W { w: self } + } + #[doc = "Bits 16:21 - Threshold Level for VDD"] + #[inline(always)] + pub fn level(&mut self) -> LEVEL_W { + LEVEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "BODVDD Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [bodvdd](index.html) module"] +pub struct BODVDD_SPEC; +impl crate::RegisterSpec for BODVDD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [bodvdd::R](R) reader structure"] +impl crate::Readable for BODVDD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [bodvdd::W](W) writer structure"] +impl crate::Writable for BODVDD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BODVDD to value 0"] +impl crate::Resettable for BODVDD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/supc/intenclr.rs b/pac/atsamc20e/src/supc/intenclr.rs new file mode 100644 index 000000000000..7b399544fafd --- /dev/null +++ b/pac/atsamc20e/src/supc/intenclr.rs @@ -0,0 +1,348 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BODVDDRDY` reader - BODVDD Ready"] +pub struct BODVDDRDY_R(crate::FieldReader); +impl BODVDDRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODVDDRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODVDDRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODVDDRDY` writer - BODVDD Ready"] +pub struct BODVDDRDY_W<'a> { + w: &'a mut W, +} +impl<'a> BODVDDRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `BODVDDDET` reader - BODVDD Detection"] +pub struct BODVDDDET_R(crate::FieldReader); +impl BODVDDDET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODVDDDET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODVDDDET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODVDDDET` writer - BODVDD Detection"] +pub struct BODVDDDET_W<'a> { + w: &'a mut W, +} +impl<'a> BODVDDDET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `BVDDSRDY` reader - BODVDD Synchronization Ready"] +pub struct BVDDSRDY_R(crate::FieldReader); +impl BVDDSRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BVDDSRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BVDDSRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BVDDSRDY` writer - BODVDD Synchronization Ready"] +pub struct BVDDSRDY_W<'a> { + w: &'a mut W, +} +impl<'a> BVDDSRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `BODCORERDY` reader - BODCORE Ready"] +pub struct BODCORERDY_R(crate::FieldReader); +impl BODCORERDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODCORERDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODCORERDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODCORERDY` writer - BODCORE Ready"] +pub struct BODCORERDY_W<'a> { + w: &'a mut W, +} +impl<'a> BODCORERDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `BODCOREDET` reader - BODCORE Detection"] +pub struct BODCOREDET_R(crate::FieldReader); +impl BODCOREDET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODCOREDET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODCOREDET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODCOREDET` writer - BODCORE Detection"] +pub struct BODCOREDET_W<'a> { + w: &'a mut W, +} +impl<'a> BODCOREDET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `BCORESRDY` reader - BODCORE Synchronization Ready"] +pub struct BCORESRDY_R(crate::FieldReader); +impl BCORESRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BCORESRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BCORESRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BCORESRDY` writer - BODCORE Synchronization Ready"] +pub struct BCORESRDY_W<'a> { + w: &'a mut W, +} +impl<'a> BCORESRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - BODVDD Ready"] + #[inline(always)] + pub fn bodvddrdy(&self) -> BODVDDRDY_R { + BODVDDRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - BODVDD Detection"] + #[inline(always)] + pub fn bodvdddet(&self) -> BODVDDDET_R { + BODVDDDET_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - BODVDD Synchronization Ready"] + #[inline(always)] + pub fn bvddsrdy(&self) -> BVDDSRDY_R { + BVDDSRDY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - BODCORE Ready"] + #[inline(always)] + pub fn bodcorerdy(&self) -> BODCORERDY_R { + BODCORERDY_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - BODCORE Detection"] + #[inline(always)] + pub fn bodcoredet(&self) -> BODCOREDET_R { + BODCOREDET_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - BODCORE Synchronization Ready"] + #[inline(always)] + pub fn bcoresrdy(&self) -> BCORESRDY_R { + BCORESRDY_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - BODVDD Ready"] + #[inline(always)] + pub fn bodvddrdy(&mut self) -> BODVDDRDY_W { + BODVDDRDY_W { w: self } + } + #[doc = "Bit 1 - BODVDD Detection"] + #[inline(always)] + pub fn bodvdddet(&mut self) -> BODVDDDET_W { + BODVDDDET_W { w: self } + } + #[doc = "Bit 2 - BODVDD Synchronization Ready"] + #[inline(always)] + pub fn bvddsrdy(&mut self) -> BVDDSRDY_W { + BVDDSRDY_W { w: self } + } + #[doc = "Bit 3 - BODCORE Ready"] + #[inline(always)] + pub fn bodcorerdy(&mut self) -> BODCORERDY_W { + BODCORERDY_W { w: self } + } + #[doc = "Bit 4 - BODCORE Detection"] + #[inline(always)] + pub fn bodcoredet(&mut self) -> BODCOREDET_W { + BODCOREDET_W { w: self } + } + #[doc = "Bit 5 - BODCORE Synchronization Ready"] + #[inline(always)] + pub fn bcoresrdy(&mut self) -> BCORESRDY_W { + BCORESRDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/supc/intenset.rs b/pac/atsamc20e/src/supc/intenset.rs new file mode 100644 index 000000000000..9e86a6e5b772 --- /dev/null +++ b/pac/atsamc20e/src/supc/intenset.rs @@ -0,0 +1,348 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BODVDDRDY` reader - BODVDD Ready"] +pub struct BODVDDRDY_R(crate::FieldReader); +impl BODVDDRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODVDDRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODVDDRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODVDDRDY` writer - BODVDD Ready"] +pub struct BODVDDRDY_W<'a> { + w: &'a mut W, +} +impl<'a> BODVDDRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `BODVDDDET` reader - BODVDD Detection"] +pub struct BODVDDDET_R(crate::FieldReader); +impl BODVDDDET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODVDDDET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODVDDDET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODVDDDET` writer - BODVDD Detection"] +pub struct BODVDDDET_W<'a> { + w: &'a mut W, +} +impl<'a> BODVDDDET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `BVDDSRDY` reader - BODVDD Synchronization Ready"] +pub struct BVDDSRDY_R(crate::FieldReader); +impl BVDDSRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BVDDSRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BVDDSRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BVDDSRDY` writer - BODVDD Synchronization Ready"] +pub struct BVDDSRDY_W<'a> { + w: &'a mut W, +} +impl<'a> BVDDSRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `BODCORERDY` reader - BODCORE Ready"] +pub struct BODCORERDY_R(crate::FieldReader); +impl BODCORERDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODCORERDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODCORERDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODCORERDY` writer - BODCORE Ready"] +pub struct BODCORERDY_W<'a> { + w: &'a mut W, +} +impl<'a> BODCORERDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `BODCOREDET` reader - BODCORE Detection"] +pub struct BODCOREDET_R(crate::FieldReader); +impl BODCOREDET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODCOREDET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODCOREDET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODCOREDET` writer - BODCORE Detection"] +pub struct BODCOREDET_W<'a> { + w: &'a mut W, +} +impl<'a> BODCOREDET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `BCORESRDY` reader - BODCORE Synchronization Ready"] +pub struct BCORESRDY_R(crate::FieldReader); +impl BCORESRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BCORESRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BCORESRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BCORESRDY` writer - BODCORE Synchronization Ready"] +pub struct BCORESRDY_W<'a> { + w: &'a mut W, +} +impl<'a> BCORESRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - BODVDD Ready"] + #[inline(always)] + pub fn bodvddrdy(&self) -> BODVDDRDY_R { + BODVDDRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - BODVDD Detection"] + #[inline(always)] + pub fn bodvdddet(&self) -> BODVDDDET_R { + BODVDDDET_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - BODVDD Synchronization Ready"] + #[inline(always)] + pub fn bvddsrdy(&self) -> BVDDSRDY_R { + BVDDSRDY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - BODCORE Ready"] + #[inline(always)] + pub fn bodcorerdy(&self) -> BODCORERDY_R { + BODCORERDY_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - BODCORE Detection"] + #[inline(always)] + pub fn bodcoredet(&self) -> BODCOREDET_R { + BODCOREDET_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - BODCORE Synchronization Ready"] + #[inline(always)] + pub fn bcoresrdy(&self) -> BCORESRDY_R { + BCORESRDY_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - BODVDD Ready"] + #[inline(always)] + pub fn bodvddrdy(&mut self) -> BODVDDRDY_W { + BODVDDRDY_W { w: self } + } + #[doc = "Bit 1 - BODVDD Detection"] + #[inline(always)] + pub fn bodvdddet(&mut self) -> BODVDDDET_W { + BODVDDDET_W { w: self } + } + #[doc = "Bit 2 - BODVDD Synchronization Ready"] + #[inline(always)] + pub fn bvddsrdy(&mut self) -> BVDDSRDY_W { + BVDDSRDY_W { w: self } + } + #[doc = "Bit 3 - BODCORE Ready"] + #[inline(always)] + pub fn bodcorerdy(&mut self) -> BODCORERDY_W { + BODCORERDY_W { w: self } + } + #[doc = "Bit 4 - BODCORE Detection"] + #[inline(always)] + pub fn bodcoredet(&mut self) -> BODCOREDET_W { + BODCOREDET_W { w: self } + } + #[doc = "Bit 5 - BODCORE Synchronization Ready"] + #[inline(always)] + pub fn bcoresrdy(&mut self) -> BCORESRDY_W { + BCORESRDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/supc/intflag.rs b/pac/atsamc20e/src/supc/intflag.rs new file mode 100644 index 000000000000..46b4b52add2d --- /dev/null +++ b/pac/atsamc20e/src/supc/intflag.rs @@ -0,0 +1,348 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BODVDDRDY` reader - BODVDD Ready"] +pub struct BODVDDRDY_R(crate::FieldReader); +impl BODVDDRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODVDDRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODVDDRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODVDDRDY` writer - BODVDD Ready"] +pub struct BODVDDRDY_W<'a> { + w: &'a mut W, +} +impl<'a> BODVDDRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `BODVDDDET` reader - BODVDD Detection"] +pub struct BODVDDDET_R(crate::FieldReader); +impl BODVDDDET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODVDDDET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODVDDDET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODVDDDET` writer - BODVDD Detection"] +pub struct BODVDDDET_W<'a> { + w: &'a mut W, +} +impl<'a> BODVDDDET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `BVDDSRDY` reader - BODVDD Synchronization Ready"] +pub struct BVDDSRDY_R(crate::FieldReader); +impl BVDDSRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BVDDSRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BVDDSRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BVDDSRDY` writer - BODVDD Synchronization Ready"] +pub struct BVDDSRDY_W<'a> { + w: &'a mut W, +} +impl<'a> BVDDSRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `BODCORERDY` reader - BODCORE Ready"] +pub struct BODCORERDY_R(crate::FieldReader); +impl BODCORERDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODCORERDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODCORERDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODCORERDY` writer - BODCORE Ready"] +pub struct BODCORERDY_W<'a> { + w: &'a mut W, +} +impl<'a> BODCORERDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `BODCOREDET` reader - BODCORE Detection"] +pub struct BODCOREDET_R(crate::FieldReader); +impl BODCOREDET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODCOREDET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODCOREDET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODCOREDET` writer - BODCORE Detection"] +pub struct BODCOREDET_W<'a> { + w: &'a mut W, +} +impl<'a> BODCOREDET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `BCORESRDY` reader - BODCORE Synchronization Ready"] +pub struct BCORESRDY_R(crate::FieldReader); +impl BCORESRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BCORESRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BCORESRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BCORESRDY` writer - BODCORE Synchronization Ready"] +pub struct BCORESRDY_W<'a> { + w: &'a mut W, +} +impl<'a> BCORESRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - BODVDD Ready"] + #[inline(always)] + pub fn bodvddrdy(&self) -> BODVDDRDY_R { + BODVDDRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - BODVDD Detection"] + #[inline(always)] + pub fn bodvdddet(&self) -> BODVDDDET_R { + BODVDDDET_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - BODVDD Synchronization Ready"] + #[inline(always)] + pub fn bvddsrdy(&self) -> BVDDSRDY_R { + BVDDSRDY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - BODCORE Ready"] + #[inline(always)] + pub fn bodcorerdy(&self) -> BODCORERDY_R { + BODCORERDY_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - BODCORE Detection"] + #[inline(always)] + pub fn bodcoredet(&self) -> BODCOREDET_R { + BODCOREDET_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - BODCORE Synchronization Ready"] + #[inline(always)] + pub fn bcoresrdy(&self) -> BCORESRDY_R { + BCORESRDY_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - BODVDD Ready"] + #[inline(always)] + pub fn bodvddrdy(&mut self) -> BODVDDRDY_W { + BODVDDRDY_W { w: self } + } + #[doc = "Bit 1 - BODVDD Detection"] + #[inline(always)] + pub fn bodvdddet(&mut self) -> BODVDDDET_W { + BODVDDDET_W { w: self } + } + #[doc = "Bit 2 - BODVDD Synchronization Ready"] + #[inline(always)] + pub fn bvddsrdy(&mut self) -> BVDDSRDY_W { + BVDDSRDY_W { w: self } + } + #[doc = "Bit 3 - BODCORE Ready"] + #[inline(always)] + pub fn bodcorerdy(&mut self) -> BODCORERDY_W { + BODCORERDY_W { w: self } + } + #[doc = "Bit 4 - BODCORE Detection"] + #[inline(always)] + pub fn bodcoredet(&mut self) -> BODCOREDET_W { + BODCOREDET_W { w: self } + } + #[doc = "Bit 5 - BODCORE Synchronization Ready"] + #[inline(always)] + pub fn bcoresrdy(&mut self) -> BCORESRDY_W { + BCORESRDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/supc/status.rs b/pac/atsamc20e/src/supc/status.rs new file mode 100644 index 000000000000..0fc1de3635b5 --- /dev/null +++ b/pac/atsamc20e/src/supc/status.rs @@ -0,0 +1,153 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `BODVDDRDY` reader - BODVDD Ready"] +pub struct BODVDDRDY_R(crate::FieldReader); +impl BODVDDRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODVDDRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODVDDRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODVDDDET` reader - BODVDD Detection"] +pub struct BODVDDDET_R(crate::FieldReader); +impl BODVDDDET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODVDDDET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODVDDDET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BVDDSRDY` reader - BODVDD Synchronization Ready"] +pub struct BVDDSRDY_R(crate::FieldReader); +impl BVDDSRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BVDDSRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BVDDSRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODCORERDY` reader - BODCORE Ready"] +pub struct BODCORERDY_R(crate::FieldReader); +impl BODCORERDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODCORERDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODCORERDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODCOREDET` reader - BODCORE Detection"] +pub struct BODCOREDET_R(crate::FieldReader); +impl BODCOREDET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODCOREDET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODCOREDET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BCORESRDY` reader - BODCORE Synchronization Ready"] +pub struct BCORESRDY_R(crate::FieldReader); +impl BCORESRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BCORESRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BCORESRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - BODVDD Ready"] + #[inline(always)] + pub fn bodvddrdy(&self) -> BODVDDRDY_R { + BODVDDRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - BODVDD Detection"] + #[inline(always)] + pub fn bodvdddet(&self) -> BODVDDDET_R { + BODVDDDET_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - BODVDD Synchronization Ready"] + #[inline(always)] + pub fn bvddsrdy(&self) -> BVDDSRDY_R { + BVDDSRDY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - BODCORE Ready"] + #[inline(always)] + pub fn bodcorerdy(&self) -> BODCORERDY_R { + BODCORERDY_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - BODCORE Detection"] + #[inline(always)] + pub fn bodcoredet(&self) -> BODCOREDET_R { + BODCOREDET_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - BODCORE Synchronization Ready"] + #[inline(always)] + pub fn bcoresrdy(&self) -> BCORESRDY_R { + BCORESRDY_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +#[doc = "Power and Clocks Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/supc/vref.rs b/pac/atsamc20e/src/supc/vref.rs new file mode 100644 index 000000000000..2d5b1381885e --- /dev/null +++ b/pac/atsamc20e/src/supc/vref.rs @@ -0,0 +1,353 @@ +#[doc = "Register `VREF` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `VREF` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TSEN` reader - Temperature Sensor Output Enable"] +pub struct TSEN_R(crate::FieldReader); +impl TSEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSEN` writer - Temperature Sensor Output Enable"] +pub struct TSEN_W<'a> { + w: &'a mut W, +} +impl<'a> TSEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `VREFOE` reader - Voltage Reference Output Enable"] +pub struct VREFOE_R(crate::FieldReader); +impl VREFOE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + VREFOE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VREFOE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VREFOE` writer - Voltage Reference Output Enable"] +pub struct VREFOE_W<'a> { + w: &'a mut W, +} +impl<'a> VREFOE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - On Demand Contrl"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - On Demand Contrl"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Voltage Reference Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SEL_A { + #[doc = "0: 1.024V voltage reference typical value"] + _1V024 = 0, + #[doc = "2: 2.048V voltage reference typical value"] + _2V048 = 2, + #[doc = "3: 4.096V voltage reference typical value"] + _4V096 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `SEL` reader - Voltage Reference Selection"] +pub struct SEL_R(crate::FieldReader); +impl SEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEL_A::_1V024), + 2 => Some(SEL_A::_2V048), + 3 => Some(SEL_A::_4V096), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_1V024`"] + #[inline(always)] + pub fn is_1v024(&self) -> bool { + **self == SEL_A::_1V024 + } + #[doc = "Checks if the value of the field is `_2V048`"] + #[inline(always)] + pub fn is_2v048(&self) -> bool { + **self == SEL_A::_2V048 + } + #[doc = "Checks if the value of the field is `_4V096`"] + #[inline(always)] + pub fn is_4v096(&self) -> bool { + **self == SEL_A::_4V096 + } +} +impl core::ops::Deref for SEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEL` writer - Voltage Reference Selection"] +pub struct SEL_W<'a> { + w: &'a mut W, +} +impl<'a> SEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SEL_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "1.024V voltage reference typical value"] + #[inline(always)] + pub fn _1v024(self) -> &'a mut W { + self.variant(SEL_A::_1V024) + } + #[doc = "2.048V voltage reference typical value"] + #[inline(always)] + pub fn _2v048(self) -> &'a mut W { + self.variant(SEL_A::_2V048) + } + #[doc = "4.096V voltage reference typical value"] + #[inline(always)] + pub fn _4v096(self) -> &'a mut W { + self.variant(SEL_A::_4V096) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 16)) | ((value as u32 & 0x0f) << 16); + self.w + } +} +impl R { + #[doc = "Bit 1 - Temperature Sensor Output Enable"] + #[inline(always)] + pub fn tsen(&self) -> TSEN_R { + TSEN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Voltage Reference Output Enable"] + #[inline(always)] + pub fn vrefoe(&self) -> VREFOE_R { + VREFOE_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - On Demand Contrl"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 16:19 - Voltage Reference Selection"] + #[inline(always)] + pub fn sel(&self) -> SEL_R { + SEL_R::new(((self.bits >> 16) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bit 1 - Temperature Sensor Output Enable"] + #[inline(always)] + pub fn tsen(&mut self) -> TSEN_W { + TSEN_W { w: self } + } + #[doc = "Bit 2 - Voltage Reference Output Enable"] + #[inline(always)] + pub fn vrefoe(&mut self) -> VREFOE_W { + VREFOE_W { w: self } + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - On Demand Contrl"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Bits 16:19 - Voltage Reference Selection"] + #[inline(always)] + pub fn sel(&mut self) -> SEL_W { + SEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "VREF Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [vref](index.html) module"] +pub struct VREF_SPEC; +impl crate::RegisterSpec for VREF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [vref::R](R) reader structure"] +impl crate::Readable for VREF_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [vref::W](W) writer structure"] +impl crate::Writable for VREF_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets VREF to value 0"] +impl crate::Resettable for VREF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/supc/vreg.rs b/pac/atsamc20e/src/supc/vreg.rs new file mode 100644 index 000000000000..fb5b12a185cf --- /dev/null +++ b/pac/atsamc20e/src/supc/vreg.rs @@ -0,0 +1,160 @@ +#[doc = "Register `VREG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `VREG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "VREG Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [vreg](index.html) module"] +pub struct VREG_SPEC; +impl crate::RegisterSpec for VREG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [vreg::R](R) reader structure"] +impl crate::Readable for VREG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [vreg::W](W) writer structure"] +impl crate::Writable for VREG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets VREG to value 0"] +impl crate::Resettable for VREG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/sys_tick.rs b/pac/atsamc20e/src/sys_tick.rs new file mode 100644 index 000000000000..b0fe7a59e5ed --- /dev/null +++ b/pac/atsamc20e/src/sys_tick.rs @@ -0,0 +1,28 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - SysTick Control and Status Register"] + pub csr: crate::Reg, + #[doc = "0x04 - SysTick Reload Value Register"] + pub rvr: crate::Reg, + #[doc = "0x08 - SysTick Current Value Register"] + pub cvr: crate::Reg, + #[doc = "0x0c - SysTick Calibration Value Register"] + pub calib: crate::Reg, +} +#[doc = "CSR register accessor: an alias for `Reg`"] +pub type CSR = crate::Reg; +#[doc = "SysTick Control and Status Register"] +pub mod csr; +#[doc = "RVR register accessor: an alias for `Reg`"] +pub type RVR = crate::Reg; +#[doc = "SysTick Reload Value Register"] +pub mod rvr; +#[doc = "CVR register accessor: an alias for `Reg`"] +pub type CVR = crate::Reg; +#[doc = "SysTick Current Value Register"] +pub mod cvr; +#[doc = "CALIB register accessor: an alias for `Reg`"] +pub type CALIB = crate::Reg; +#[doc = "SysTick Calibration Value Register"] +pub mod calib; diff --git a/pac/atsamc20e/src/sys_tick/calib.rs b/pac/atsamc20e/src/sys_tick/calib.rs new file mode 100644 index 000000000000..df7fd80f773a --- /dev/null +++ b/pac/atsamc20e/src/sys_tick/calib.rs @@ -0,0 +1,157 @@ +#[doc = "Register `CALIB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `TENMS` reader - Reload value to use for 10ms timing"] +pub struct TENMS_R(crate::FieldReader); +impl TENMS_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + TENMS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TENMS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "TENMS is rounded from non-integer ratio\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SKEW_A { + #[doc = "0: 10ms calibration value is exact"] + VALUE_0 = 0, + #[doc = "1: 10ms calibration value is inexact, because of the clock frequency"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SKEW_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SKEW` reader - TENMS is rounded from non-integer ratio"] +pub struct SKEW_R(crate::FieldReader); +impl SKEW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SKEW_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SKEW_A { + match self.bits { + false => SKEW_A::VALUE_0, + true => SKEW_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == SKEW_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == SKEW_A::VALUE_1 + } +} +impl core::ops::Deref for SKEW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "No Separate Reference Clock\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum NOREF_A { + #[doc = "0: The reference clock is provided"] + VALUE_0 = 0, + #[doc = "1: The reference clock is not provided"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NOREF_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NOREF` reader - No Separate Reference Clock"] +pub struct NOREF_R(crate::FieldReader); +impl NOREF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NOREF_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> NOREF_A { + match self.bits { + false => NOREF_A::VALUE_0, + true => NOREF_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == NOREF_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == NOREF_A::VALUE_1 + } +} +impl core::ops::Deref for NOREF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:23 - Reload value to use for 10ms timing"] + #[inline(always)] + pub fn tenms(&self) -> TENMS_R { + TENMS_R::new((self.bits & 0x00ff_ffff) as u32) + } + #[doc = "Bit 30 - TENMS is rounded from non-integer ratio"] + #[inline(always)] + pub fn skew(&self) -> SKEW_R { + SKEW_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 31 - No Separate Reference Clock"] + #[inline(always)] + pub fn noref(&self) -> NOREF_R { + NOREF_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +#[doc = "SysTick Calibration Value Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [calib](index.html) module"] +pub struct CALIB_SPEC; +impl crate::RegisterSpec for CALIB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [calib::R](R) reader structure"] +impl crate::Readable for CALIB_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CALIB to value 0"] +impl crate::Resettable for CALIB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/sys_tick/csr.rs b/pac/atsamc20e/src/sys_tick/csr.rs new file mode 100644 index 000000000000..872d637f5a86 --- /dev/null +++ b/pac/atsamc20e/src/sys_tick/csr.rs @@ -0,0 +1,395 @@ +#[doc = "Register `CSR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CSR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "SysTick Counter Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ENABLE_A { + #[doc = "0: Counter disabled"] + VALUE_0 = 0, + #[doc = "1: Counter enabled"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ENABLE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ENABLE` reader - SysTick Counter Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ENABLE_A { + match self.bits { + false => ENABLE_A::VALUE_0, + true => ENABLE_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == ENABLE_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == ENABLE_A::VALUE_1 + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - SysTick Counter Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: ENABLE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Counter disabled"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(ENABLE_A::VALUE_0) + } + #[doc = "Counter enabled"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(ENABLE_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "SysTick Exception Request Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TICKINT_A { + #[doc = "0: Counting down to 0 does not assert the SysTick exception request"] + VALUE_0 = 0, + #[doc = "1: Counting down to 0 asserts the SysTick exception request"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TICKINT_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TICKINT` reader - SysTick Exception Request Enable"] +pub struct TICKINT_R(crate::FieldReader); +impl TICKINT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TICKINT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TICKINT_A { + match self.bits { + false => TICKINT_A::VALUE_0, + true => TICKINT_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == TICKINT_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == TICKINT_A::VALUE_1 + } +} +impl core::ops::Deref for TICKINT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TICKINT` writer - SysTick Exception Request Enable"] +pub struct TICKINT_W<'a> { + w: &'a mut W, +} +impl<'a> TICKINT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TICKINT_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Counting down to 0 does not assert the SysTick exception request"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(TICKINT_A::VALUE_0) + } + #[doc = "Counting down to 0 asserts the SysTick exception request"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(TICKINT_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Clock Source 0=external, 1=processor\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CLKSOURCE_A { + #[doc = "0: External clock"] + VALUE_0 = 0, + #[doc = "1: Processor clock"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CLKSOURCE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CLKSOURCE` reader - Clock Source 0=external, 1=processor"] +pub struct CLKSOURCE_R(crate::FieldReader); +impl CLKSOURCE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKSOURCE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CLKSOURCE_A { + match self.bits { + false => CLKSOURCE_A::VALUE_0, + true => CLKSOURCE_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == CLKSOURCE_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == CLKSOURCE_A::VALUE_1 + } +} +impl core::ops::Deref for CLKSOURCE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKSOURCE` writer - Clock Source 0=external, 1=processor"] +pub struct CLKSOURCE_W<'a> { + w: &'a mut W, +} +impl<'a> CLKSOURCE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CLKSOURCE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "External clock"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(CLKSOURCE_A::VALUE_0) + } + #[doc = "Processor clock"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(CLKSOURCE_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `COUNTFLAG` reader - Timer counted to 0 since last read of register"] +pub struct COUNTFLAG_R(crate::FieldReader); +impl COUNTFLAG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNTFLAG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNTFLAG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNTFLAG` writer - Timer counted to 0 since last read of register"] +pub struct COUNTFLAG_W<'a> { + w: &'a mut W, +} +impl<'a> COUNTFLAG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +impl R { + #[doc = "Bit 0 - SysTick Counter Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SysTick Exception Request Enable"] + #[inline(always)] + pub fn tickint(&self) -> TICKINT_R { + TICKINT_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Clock Source 0=external, 1=processor"] + #[inline(always)] + pub fn clksource(&self) -> CLKSOURCE_R { + CLKSOURCE_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 16 - Timer counted to 0 since last read of register"] + #[inline(always)] + pub fn countflag(&self) -> COUNTFLAG_R { + COUNTFLAG_R::new(((self.bits >> 16) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - SysTick Counter Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 1 - SysTick Exception Request Enable"] + #[inline(always)] + pub fn tickint(&mut self) -> TICKINT_W { + TICKINT_W { w: self } + } + #[doc = "Bit 2 - Clock Source 0=external, 1=processor"] + #[inline(always)] + pub fn clksource(&mut self) -> CLKSOURCE_W { + CLKSOURCE_W { w: self } + } + #[doc = "Bit 16 - Timer counted to 0 since last read of register"] + #[inline(always)] + pub fn countflag(&mut self) -> COUNTFLAG_W { + COUNTFLAG_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SysTick Control and Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [csr](index.html) module"] +pub struct CSR_SPEC; +impl crate::RegisterSpec for CSR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [csr::R](R) reader structure"] +impl crate::Readable for CSR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [csr::W](W) writer structure"] +impl crate::Writable for CSR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CSR to value 0x04"] +impl crate::Resettable for CSR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x04 + } +} diff --git a/pac/atsamc20e/src/sys_tick/cvr.rs b/pac/atsamc20e/src/sys_tick/cvr.rs new file mode 100644 index 000000000000..8a40b5f43b3a --- /dev/null +++ b/pac/atsamc20e/src/sys_tick/cvr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `CVR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CVR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CURRENT` reader - Current value at the time the register is accessed"] +pub struct CURRENT_R(crate::FieldReader); +impl CURRENT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CURRENT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CURRENT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CURRENT` writer - Current value at the time the register is accessed"] +pub struct CURRENT_W<'a> { + w: &'a mut W, +} +impl<'a> CURRENT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Current value at the time the register is accessed"] + #[inline(always)] + pub fn current(&self) -> CURRENT_R { + CURRENT_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Current value at the time the register is accessed"] + #[inline(always)] + pub fn current(&mut self) -> CURRENT_W { + CURRENT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SysTick Current Value Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cvr](index.html) module"] +pub struct CVR_SPEC; +impl crate::RegisterSpec for CVR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cvr::R](R) reader structure"] +impl crate::Readable for CVR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cvr::W](W) writer structure"] +impl crate::Writable for CVR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CVR to value 0"] +impl crate::Resettable for CVR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/sys_tick/rvr.rs b/pac/atsamc20e/src/sys_tick/rvr.rs new file mode 100644 index 000000000000..ac023ff75f36 --- /dev/null +++ b/pac/atsamc20e/src/sys_tick/rvr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `RVR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RVR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RELOAD` reader - Value to load into the SysTick Current Value Register when the counter reaches 0"] +pub struct RELOAD_R(crate::FieldReader); +impl RELOAD_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + RELOAD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RELOAD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RELOAD` writer - Value to load into the SysTick Current Value Register when the counter reaches 0"] +pub struct RELOAD_W<'a> { + w: &'a mut W, +} +impl<'a> RELOAD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Value to load into the SysTick Current Value Register when the counter reaches 0"] + #[inline(always)] + pub fn reload(&self) -> RELOAD_R { + RELOAD_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Value to load into the SysTick Current Value Register when the counter reaches 0"] + #[inline(always)] + pub fn reload(&mut self) -> RELOAD_W { + RELOAD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SysTick Reload Value Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rvr](index.html) module"] +pub struct RVR_SPEC; +impl crate::RegisterSpec for RVR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rvr::R](R) reader structure"] +impl crate::Readable for RVR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rvr::W](W) writer structure"] +impl crate::Writable for RVR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RVR to value 0"] +impl crate::Resettable for RVR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/system_control.rs b/pac/atsamc20e/src/system_control.rs new file mode 100644 index 000000000000..4894b22b258f --- /dev/null +++ b/pac/atsamc20e/src/system_control.rs @@ -0,0 +1,67 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved0: [u8; 0x0d00], + #[doc = "0xd00 - CPUID Base Register"] + pub cpuid: crate::Reg, + #[doc = "0xd04 - Interrupt Control and State Register"] + pub icsr: crate::Reg, + #[doc = "0xd08 - Vector Table Offset Register"] + pub vtor: crate::Reg, + #[doc = "0xd0c - Application Interrupt and Reset Control Register"] + pub aircr: crate::Reg, + #[doc = "0xd10 - System Control Register"] + pub scr: crate::Reg, + #[doc = "0xd14 - Configuration and Control Register"] + pub ccr: crate::Reg, + _reserved6: [u8; 0x04], + #[doc = "0xd1c - System Handler Priority Register 2"] + pub shpr2: crate::Reg, + #[doc = "0xd20 - System Handler Priority Register 3"] + pub shpr3: crate::Reg, + #[doc = "0xd24 - System Handler Control and State Register"] + pub shcsr: crate::Reg, + _reserved9: [u8; 0x08], + #[doc = "0xd30 - Debug Fault Status Register"] + pub dfsr: crate::Reg, +} +#[doc = "CPUID register accessor: an alias for `Reg`"] +pub type CPUID = crate::Reg; +#[doc = "CPUID Base Register"] +pub mod cpuid; +#[doc = "ICSR register accessor: an alias for `Reg`"] +pub type ICSR = crate::Reg; +#[doc = "Interrupt Control and State Register"] +pub mod icsr; +#[doc = "VTOR register accessor: an alias for `Reg`"] +pub type VTOR = crate::Reg; +#[doc = "Vector Table Offset Register"] +pub mod vtor; +#[doc = "AIRCR register accessor: an alias for `Reg`"] +pub type AIRCR = crate::Reg; +#[doc = "Application Interrupt and Reset Control Register"] +pub mod aircr; +#[doc = "SCR register accessor: an alias for `Reg`"] +pub type SCR = crate::Reg; +#[doc = "System Control Register"] +pub mod scr; +#[doc = "CCR register accessor: an alias for `Reg`"] +pub type CCR = crate::Reg; +#[doc = "Configuration and Control Register"] +pub mod ccr; +#[doc = "SHPR2 register accessor: an alias for `Reg`"] +pub type SHPR2 = crate::Reg; +#[doc = "System Handler Priority Register 2"] +pub mod shpr2; +#[doc = "SHPR3 register accessor: an alias for `Reg`"] +pub type SHPR3 = crate::Reg; +#[doc = "System Handler Priority Register 3"] +pub mod shpr3; +#[doc = "SHCSR register accessor: an alias for `Reg`"] +pub type SHCSR = crate::Reg; +#[doc = "System Handler Control and State Register"] +pub mod shcsr; +#[doc = "DFSR register accessor: an alias for `Reg`"] +pub type DFSR = crate::Reg; +#[doc = "Debug Fault Status Register"] +pub mod dfsr; diff --git a/pac/atsamc20e/src/system_control/aircr.rs b/pac/atsamc20e/src/system_control/aircr.rs new file mode 100644 index 000000000000..9453cc6f30bc --- /dev/null +++ b/pac/atsamc20e/src/system_control/aircr.rs @@ -0,0 +1,338 @@ +#[doc = "Register `AIRCR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `AIRCR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `VECTCLRACTIVE` reader - Debug: Clear state information"] +pub struct VECTCLRACTIVE_R(crate::FieldReader); +impl VECTCLRACTIVE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + VECTCLRACTIVE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VECTCLRACTIVE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VECTCLRACTIVE` writer - Debug: Clear state information"] +pub struct VECTCLRACTIVE_W<'a> { + w: &'a mut W, +} +impl<'a> VECTCLRACTIVE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "System Reset Request\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SYSRESETREQ_A { + #[doc = "0: No system reset request"] + VALUE_0 = 0, + #[doc = "1: Asserts a signal to the outer system that requests a reset"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SYSRESETREQ_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SYSRESETREQ` reader - System Reset Request"] +pub struct SYSRESETREQ_R(crate::FieldReader); +impl SYSRESETREQ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYSRESETREQ_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SYSRESETREQ_A { + match self.bits { + false => SYSRESETREQ_A::VALUE_0, + true => SYSRESETREQ_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == SYSRESETREQ_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == SYSRESETREQ_A::VALUE_1 + } +} +impl core::ops::Deref for SYSRESETREQ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYSRESETREQ` writer - System Reset Request"] +pub struct SYSRESETREQ_W<'a> { + w: &'a mut W, +} +impl<'a> SYSRESETREQ_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SYSRESETREQ_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "No system reset request"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(SYSRESETREQ_A::VALUE_0) + } + #[doc = "Asserts a signal to the outer system that requests a reset"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(SYSRESETREQ_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Data Endianness, 0=little, 1=big\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ENDIANNESS_A { + #[doc = "0: Little-endian"] + VALUE_0 = 0, + #[doc = "1: Big-endian"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ENDIANNESS_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ENDIANNESS` reader - Data Endianness, 0=little, 1=big"] +pub struct ENDIANNESS_R(crate::FieldReader); +impl ENDIANNESS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENDIANNESS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ENDIANNESS_A { + match self.bits { + false => ENDIANNESS_A::VALUE_0, + true => ENDIANNESS_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == ENDIANNESS_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == ENDIANNESS_A::VALUE_1 + } +} +impl core::ops::Deref for ENDIANNESS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENDIANNESS` writer - Data Endianness, 0=little, 1=big"] +pub struct ENDIANNESS_W<'a> { + w: &'a mut W, +} +impl<'a> ENDIANNESS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: ENDIANNESS_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Little-endian"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(ENDIANNESS_A::VALUE_0) + } + #[doc = "Big-endian"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(ENDIANNESS_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `VECTKEY` reader - Register key (0x05FA)"] +pub struct VECTKEY_R(crate::FieldReader); +impl VECTKEY_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + VECTKEY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VECTKEY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VECTKEY` writer - Register key (0x05FA)"] +pub struct VECTKEY_W<'a> { + w: &'a mut W, +} +impl<'a> VECTKEY_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xffff << 16)) | ((value as u32 & 0xffff) << 16); + self.w + } +} +impl R { + #[doc = "Bit 1 - Debug: Clear state information"] + #[inline(always)] + pub fn vectclractive(&self) -> VECTCLRACTIVE_R { + VECTCLRACTIVE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - System Reset Request"] + #[inline(always)] + pub fn sysresetreq(&self) -> SYSRESETREQ_R { + SYSRESETREQ_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 15 - Data Endianness, 0=little, 1=big"] + #[inline(always)] + pub fn endianness(&self) -> ENDIANNESS_R { + ENDIANNESS_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:31 - Register key (0x05FA)"] + #[inline(always)] + pub fn vectkey(&self) -> VECTKEY_R { + VECTKEY_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bit 1 - Debug: Clear state information"] + #[inline(always)] + pub fn vectclractive(&mut self) -> VECTCLRACTIVE_W { + VECTCLRACTIVE_W { w: self } + } + #[doc = "Bit 2 - System Reset Request"] + #[inline(always)] + pub fn sysresetreq(&mut self) -> SYSRESETREQ_W { + SYSRESETREQ_W { w: self } + } + #[doc = "Bit 15 - Data Endianness, 0=little, 1=big"] + #[inline(always)] + pub fn endianness(&mut self) -> ENDIANNESS_W { + ENDIANNESS_W { w: self } + } + #[doc = "Bits 16:31 - Register key (0x05FA)"] + #[inline(always)] + pub fn vectkey(&mut self) -> VECTKEY_W { + VECTKEY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Application Interrupt and Reset Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [aircr](index.html) module"] +pub struct AIRCR_SPEC; +impl crate::RegisterSpec for AIRCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [aircr::R](R) reader structure"] +impl crate::Readable for AIRCR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [aircr::W](W) writer structure"] +impl crate::Writable for AIRCR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets AIRCR to value 0"] +impl crate::Resettable for AIRCR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/system_control/ccr.rs b/pac/atsamc20e/src/system_control/ccr.rs new file mode 100644 index 000000000000..62516a7b60c8 --- /dev/null +++ b/pac/atsamc20e/src/system_control/ccr.rs @@ -0,0 +1,137 @@ +#[doc = "Register `CCR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Unaligned accesses generates a Hard Fault\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum UNALIGN_TRP_A { + #[doc = "0: Do not trap unaligned halfword and word accesses"] + VALUE_0 = 0, + #[doc = "1: Trap unaligned halfword and word accesses"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: UNALIGN_TRP_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `UNALIGN_TRP` reader - Unaligned accesses generates a Hard Fault"] +pub struct UNALIGN_TRP_R(crate::FieldReader); +impl UNALIGN_TRP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UNALIGN_TRP_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> UNALIGN_TRP_A { + match self.bits { + false => UNALIGN_TRP_A::VALUE_0, + true => UNALIGN_TRP_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == UNALIGN_TRP_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == UNALIGN_TRP_A::VALUE_1 + } +} +impl core::ops::Deref for UNALIGN_TRP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Stack 8-byte aligned on exception entry\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum STKALIGN_A { + #[doc = "0: 4-byte aligned"] + VALUE_0 = 0, + #[doc = "1: 8-byte aligned"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: STKALIGN_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STKALIGN` reader - Stack 8-byte aligned on exception entry"] +pub struct STKALIGN_R(crate::FieldReader); +impl STKALIGN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STKALIGN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STKALIGN_A { + match self.bits { + false => STKALIGN_A::VALUE_0, + true => STKALIGN_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == STKALIGN_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == STKALIGN_A::VALUE_1 + } +} +impl core::ops::Deref for STKALIGN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 3 - Unaligned accesses generates a Hard Fault"] + #[inline(always)] + pub fn unalign_trp(&self) -> UNALIGN_TRP_R { + UNALIGN_TRP_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 9 - Stack 8-byte aligned on exception entry"] + #[inline(always)] + pub fn stkalign(&self) -> STKALIGN_R { + STKALIGN_R::new(((self.bits >> 9) & 0x01) != 0) + } +} +#[doc = "Configuration and Control Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccr](index.html) module"] +pub struct CCR_SPEC; +impl crate::RegisterSpec for CCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ccr::R](R) reader structure"] +impl crate::Readable for CCR_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CCR to value 0x0204"] +impl crate::Resettable for CCR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0204 + } +} diff --git a/pac/atsamc20e/src/system_control/cpuid.rs b/pac/atsamc20e/src/system_control/cpuid.rs new file mode 100644 index 000000000000..4157d7a94e97 --- /dev/null +++ b/pac/atsamc20e/src/system_control/cpuid.rs @@ -0,0 +1,133 @@ +#[doc = "Register `CPUID` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `REVISION` reader - Minor revision number"] +pub struct REVISION_R(crate::FieldReader); +impl REVISION_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REVISION_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REVISION_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PARTNO` reader - Processor Part Number, 0xC60=Cortex-M0+"] +pub struct PARTNO_R(crate::FieldReader); +impl PARTNO_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + PARTNO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PARTNO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ARCHITECTURE` reader - Processor Architecture, 0xC=ARMv6-M"] +pub struct ARCHITECTURE_R(crate::FieldReader); +impl ARCHITECTURE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ARCHITECTURE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ARCHITECTURE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VARIANT` reader - Major revision number"] +pub struct VARIANT_R(crate::FieldReader); +impl VARIANT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + VARIANT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VARIANT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IMPLEMENTER` reader - Implementer code, ARM=0x41"] +pub struct IMPLEMENTER_R(crate::FieldReader); +impl IMPLEMENTER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + IMPLEMENTER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IMPLEMENTER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:3 - Minor revision number"] + #[inline(always)] + pub fn revision(&self) -> REVISION_R { + REVISION_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:15 - Processor Part Number, 0xC60=Cortex-M0+"] + #[inline(always)] + pub fn partno(&self) -> PARTNO_R { + PARTNO_R::new(((self.bits >> 4) & 0x0fff) as u16) + } + #[doc = "Bits 16:19 - Processor Architecture, 0xC=ARMv6-M"] + #[inline(always)] + pub fn architecture(&self) -> ARCHITECTURE_R { + ARCHITECTURE_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bits 20:23 - Major revision number"] + #[inline(always)] + pub fn variant(&self) -> VARIANT_R { + VARIANT_R::new(((self.bits >> 20) & 0x0f) as u8) + } + #[doc = "Bits 24:31 - Implementer code, ARM=0x41"] + #[inline(always)] + pub fn implementer(&self) -> IMPLEMENTER_R { + IMPLEMENTER_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[doc = "CPUID Base Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cpuid](index.html) module"] +pub struct CPUID_SPEC; +impl crate::RegisterSpec for CPUID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cpuid::R](R) reader structure"] +impl crate::Readable for CPUID_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CPUID to value 0x410c_c601"] +impl crate::Resettable for CPUID_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x410c_c601 + } +} diff --git a/pac/atsamc20e/src/system_control/dfsr.rs b/pac/atsamc20e/src/system_control/dfsr.rs new file mode 100644 index 000000000000..948899af0905 --- /dev/null +++ b/pac/atsamc20e/src/system_control/dfsr.rs @@ -0,0 +1,301 @@ +#[doc = "Register `DFSR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DFSR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `HALTED` reader - Halt request debug event active"] +pub struct HALTED_R(crate::FieldReader); +impl HALTED_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HALTED_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HALTED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HALTED` writer - Halt request debug event active"] +pub struct HALTED_W<'a> { + w: &'a mut W, +} +impl<'a> HALTED_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `BKPT` reader - Breakpoint debug event"] +pub struct BKPT_R(crate::FieldReader); +impl BKPT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BKPT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BKPT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BKPT` writer - Breakpoint debug event"] +pub struct BKPT_W<'a> { + w: &'a mut W, +} +impl<'a> BKPT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `DWTTRAP` reader - DWT debug event"] +pub struct DWTTRAP_R(crate::FieldReader); +impl DWTTRAP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DWTTRAP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DWTTRAP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DWTTRAP` writer - DWT debug event"] +pub struct DWTTRAP_W<'a> { + w: &'a mut W, +} +impl<'a> DWTTRAP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `VCATCH` reader - Vector catch debug event"] +pub struct VCATCH_R(crate::FieldReader); +impl VCATCH_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + VCATCH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VCATCH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VCATCH` writer - Vector catch debug event"] +pub struct VCATCH_W<'a> { + w: &'a mut W, +} +impl<'a> VCATCH_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `EXTERNAL` reader - EDBGRQ debug event"] +pub struct EXTERNAL_R(crate::FieldReader); +impl EXTERNAL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTERNAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTERNAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTERNAL` writer - EDBGRQ debug event"] +pub struct EXTERNAL_W<'a> { + w: &'a mut W, +} +impl<'a> EXTERNAL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +impl R { + #[doc = "Bit 0 - Halt request debug event active"] + #[inline(always)] + pub fn halted(&self) -> HALTED_R { + HALTED_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Breakpoint debug event"] + #[inline(always)] + pub fn bkpt(&self) -> BKPT_R { + BKPT_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - DWT debug event"] + #[inline(always)] + pub fn dwttrap(&self) -> DWTTRAP_R { + DWTTRAP_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Vector catch debug event"] + #[inline(always)] + pub fn vcatch(&self) -> VCATCH_R { + VCATCH_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - EDBGRQ debug event"] + #[inline(always)] + pub fn external(&self) -> EXTERNAL_R { + EXTERNAL_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Halt request debug event active"] + #[inline(always)] + pub fn halted(&mut self) -> HALTED_W { + HALTED_W { w: self } + } + #[doc = "Bit 1 - Breakpoint debug event"] + #[inline(always)] + pub fn bkpt(&mut self) -> BKPT_W { + BKPT_W { w: self } + } + #[doc = "Bit 2 - DWT debug event"] + #[inline(always)] + pub fn dwttrap(&mut self) -> DWTTRAP_W { + DWTTRAP_W { w: self } + } + #[doc = "Bit 3 - Vector catch debug event"] + #[inline(always)] + pub fn vcatch(&mut self) -> VCATCH_W { + VCATCH_W { w: self } + } + #[doc = "Bit 4 - EDBGRQ debug event"] + #[inline(always)] + pub fn external(&mut self) -> EXTERNAL_W { + EXTERNAL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Fault Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dfsr](index.html) module"] +pub struct DFSR_SPEC; +impl crate::RegisterSpec for DFSR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dfsr::R](R) reader structure"] +impl crate::Readable for DFSR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dfsr::W](W) writer structure"] +impl crate::Writable for DFSR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DFSR to value 0"] +impl crate::Resettable for DFSR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/system_control/icsr.rs b/pac/atsamc20e/src/system_control/icsr.rs new file mode 100644 index 000000000000..7fe5fd412116 --- /dev/null +++ b/pac/atsamc20e/src/system_control/icsr.rs @@ -0,0 +1,704 @@ +#[doc = "Register `ICSR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ICSR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `VECTACTIVE` reader - Debug: Exception number of currently executing exception, or 0 if thread mode"] +pub struct VECTACTIVE_R(crate::FieldReader); +impl VECTACTIVE_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + VECTACTIVE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VECTACTIVE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VECTACTIVE` writer - Debug: Exception number of currently executing exception, or 0 if thread mode"] +pub struct VECTACTIVE_W<'a> { + w: &'a mut W, +} +impl<'a> VECTACTIVE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01ff) | (value as u32 & 0x01ff); + self.w + } +} +#[doc = "Field `VECTPENDING` reader - Exception number of the highest priority pending enabled exception"] +pub struct VECTPENDING_R(crate::FieldReader); +impl VECTPENDING_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + VECTPENDING_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VECTPENDING_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VECTPENDING` writer - Exception number of the highest priority pending enabled exception"] +pub struct VECTPENDING_W<'a> { + w: &'a mut W, +} +impl<'a> VECTPENDING_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01ff << 12)) | ((value as u32 & 0x01ff) << 12); + self.w + } +} +#[doc = "Field `ISRPENDING` reader - Debug: NVIC interrupt pending"] +pub struct ISRPENDING_R(crate::FieldReader); +impl ISRPENDING_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ISRPENDING_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ISRPENDING_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ISRPENDING` writer - Debug: NVIC interrupt pending"] +pub struct ISRPENDING_W<'a> { + w: &'a mut W, +} +impl<'a> ISRPENDING_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `ISRPREEMPT` reader - Debug: Pending exception serviced on exit from debug halt"] +pub struct ISRPREEMPT_R(crate::FieldReader); +impl ISRPREEMPT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ISRPREEMPT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ISRPREEMPT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ISRPREEMPT` writer - Debug: Pending exception serviced on exit from debug halt"] +pub struct ISRPREEMPT_W<'a> { + w: &'a mut W, +} +impl<'a> ISRPREEMPT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "SysTick exception clear-pending bit\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PENDSTCLR_A { + #[doc = "0: No effect"] + VALUE_0 = 0, + #[doc = "1: Removes the pending state from the SysTick exception"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PENDSTCLR_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PENDSTCLR` reader - SysTick exception clear-pending bit"] +pub struct PENDSTCLR_R(crate::FieldReader); +impl PENDSTCLR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDSTCLR_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PENDSTCLR_A { + match self.bits { + false => PENDSTCLR_A::VALUE_0, + true => PENDSTCLR_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == PENDSTCLR_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == PENDSTCLR_A::VALUE_1 + } +} +impl core::ops::Deref for PENDSTCLR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDSTCLR` writer - SysTick exception clear-pending bit"] +pub struct PENDSTCLR_W<'a> { + w: &'a mut W, +} +impl<'a> PENDSTCLR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PENDSTCLR_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "No effect"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(PENDSTCLR_A::VALUE_0) + } + #[doc = "Removes the pending state from the SysTick exception"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(PENDSTCLR_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "SysTick exception set-pending bit\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PENDSTSET_A { + #[doc = "0: Write: no effect; read: SysTick exception is not pending"] + VALUE_0 = 0, + #[doc = "1: Write: changes SysTick exception state to pending; read: SysTick exception is pending"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PENDSTSET_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PENDSTSET` reader - SysTick exception set-pending bit"] +pub struct PENDSTSET_R(crate::FieldReader); +impl PENDSTSET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDSTSET_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PENDSTSET_A { + match self.bits { + false => PENDSTSET_A::VALUE_0, + true => PENDSTSET_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == PENDSTSET_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == PENDSTSET_A::VALUE_1 + } +} +impl core::ops::Deref for PENDSTSET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDSTSET` writer - SysTick exception set-pending bit"] +pub struct PENDSTSET_W<'a> { + w: &'a mut W, +} +impl<'a> PENDSTSET_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PENDSTSET_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Write: no effect; read: SysTick exception is not pending"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(PENDSTSET_A::VALUE_0) + } + #[doc = "Write: changes SysTick exception state to pending; read: SysTick exception is pending"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(PENDSTSET_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "PendSV clear-pending bit\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PENDSVCLR_A { + #[doc = "0: No effect"] + VALUE_0 = 0, + #[doc = "1: Removes the pending state from the PendSV exception"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PENDSVCLR_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PENDSVCLR` reader - PendSV clear-pending bit"] +pub struct PENDSVCLR_R(crate::FieldReader); +impl PENDSVCLR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDSVCLR_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PENDSVCLR_A { + match self.bits { + false => PENDSVCLR_A::VALUE_0, + true => PENDSVCLR_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == PENDSVCLR_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == PENDSVCLR_A::VALUE_1 + } +} +impl core::ops::Deref for PENDSVCLR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDSVCLR` writer - PendSV clear-pending bit"] +pub struct PENDSVCLR_W<'a> { + w: &'a mut W, +} +impl<'a> PENDSVCLR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PENDSVCLR_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "No effect"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(PENDSVCLR_A::VALUE_0) + } + #[doc = "Removes the pending state from the PendSV exception"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(PENDSVCLR_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +#[doc = "PendSV set-pending bit\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PENDSVSET_A { + #[doc = "0: Write: no effect; read: PendSV exception is not pending"] + VALUE_0 = 0, + #[doc = "1: Write: changes PendSV exception state to pending; read: PendSV exception is pending"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PENDSVSET_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PENDSVSET` reader - PendSV set-pending bit"] +pub struct PENDSVSET_R(crate::FieldReader); +impl PENDSVSET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDSVSET_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PENDSVSET_A { + match self.bits { + false => PENDSVSET_A::VALUE_0, + true => PENDSVSET_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == PENDSVSET_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == PENDSVSET_A::VALUE_1 + } +} +impl core::ops::Deref for PENDSVSET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDSVSET` writer - PendSV set-pending bit"] +pub struct PENDSVSET_W<'a> { + w: &'a mut W, +} +impl<'a> PENDSVSET_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PENDSVSET_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Write: no effect; read: PendSV exception is not pending"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(PENDSVSET_A::VALUE_0) + } + #[doc = "Write: changes PendSV exception state to pending; read: PendSV exception is pending"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(PENDSVSET_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "NMI set-pending bit\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum NMIPENDSET_A { + #[doc = "0: Write: no effect; read: NMI exception is not pending"] + VALUE_0 = 0, + #[doc = "1: Write: changes NMI exception state to pending; read: NMI exception is pending"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NMIPENDSET_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NMIPENDSET` reader - NMI set-pending bit"] +pub struct NMIPENDSET_R(crate::FieldReader); +impl NMIPENDSET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NMIPENDSET_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> NMIPENDSET_A { + match self.bits { + false => NMIPENDSET_A::VALUE_0, + true => NMIPENDSET_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == NMIPENDSET_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == NMIPENDSET_A::VALUE_1 + } +} +impl core::ops::Deref for NMIPENDSET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NMIPENDSET` writer - NMI set-pending bit"] +pub struct NMIPENDSET_W<'a> { + w: &'a mut W, +} +impl<'a> NMIPENDSET_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: NMIPENDSET_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Write: no effect; read: NMI exception is not pending"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(NMIPENDSET_A::VALUE_0) + } + #[doc = "Write: changes NMI exception state to pending; read: NMI exception is pending"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(NMIPENDSET_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bits 0:8 - Debug: Exception number of currently executing exception, or 0 if thread mode"] + #[inline(always)] + pub fn vectactive(&self) -> VECTACTIVE_R { + VECTACTIVE_R::new((self.bits & 0x01ff) as u16) + } + #[doc = "Bits 12:20 - Exception number of the highest priority pending enabled exception"] + #[inline(always)] + pub fn vectpending(&self) -> VECTPENDING_R { + VECTPENDING_R::new(((self.bits >> 12) & 0x01ff) as u16) + } + #[doc = "Bit 22 - Debug: NVIC interrupt pending"] + #[inline(always)] + pub fn isrpending(&self) -> ISRPENDING_R { + ISRPENDING_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Debug: Pending exception serviced on exit from debug halt"] + #[inline(always)] + pub fn isrpreempt(&self) -> ISRPREEMPT_R { + ISRPREEMPT_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 25 - SysTick exception clear-pending bit"] + #[inline(always)] + pub fn pendstclr(&self) -> PENDSTCLR_R { + PENDSTCLR_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - SysTick exception set-pending bit"] + #[inline(always)] + pub fn pendstset(&self) -> PENDSTSET_R { + PENDSTSET_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - PendSV clear-pending bit"] + #[inline(always)] + pub fn pendsvclr(&self) -> PENDSVCLR_R { + PENDSVCLR_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28 - PendSV set-pending bit"] + #[inline(always)] + pub fn pendsvset(&self) -> PENDSVSET_R { + PENDSVSET_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 31 - NMI set-pending bit"] + #[inline(always)] + pub fn nmipendset(&self) -> NMIPENDSET_R { + NMIPENDSET_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:8 - Debug: Exception number of currently executing exception, or 0 if thread mode"] + #[inline(always)] + pub fn vectactive(&mut self) -> VECTACTIVE_W { + VECTACTIVE_W { w: self } + } + #[doc = "Bits 12:20 - Exception number of the highest priority pending enabled exception"] + #[inline(always)] + pub fn vectpending(&mut self) -> VECTPENDING_W { + VECTPENDING_W { w: self } + } + #[doc = "Bit 22 - Debug: NVIC interrupt pending"] + #[inline(always)] + pub fn isrpending(&mut self) -> ISRPENDING_W { + ISRPENDING_W { w: self } + } + #[doc = "Bit 23 - Debug: Pending exception serviced on exit from debug halt"] + #[inline(always)] + pub fn isrpreempt(&mut self) -> ISRPREEMPT_W { + ISRPREEMPT_W { w: self } + } + #[doc = "Bit 25 - SysTick exception clear-pending bit"] + #[inline(always)] + pub fn pendstclr(&mut self) -> PENDSTCLR_W { + PENDSTCLR_W { w: self } + } + #[doc = "Bit 26 - SysTick exception set-pending bit"] + #[inline(always)] + pub fn pendstset(&mut self) -> PENDSTSET_W { + PENDSTSET_W { w: self } + } + #[doc = "Bit 27 - PendSV clear-pending bit"] + #[inline(always)] + pub fn pendsvclr(&mut self) -> PENDSVCLR_W { + PENDSVCLR_W { w: self } + } + #[doc = "Bit 28 - PendSV set-pending bit"] + #[inline(always)] + pub fn pendsvset(&mut self) -> PENDSVSET_W { + PENDSVSET_W { w: self } + } + #[doc = "Bit 31 - NMI set-pending bit"] + #[inline(always)] + pub fn nmipendset(&mut self) -> NMIPENDSET_W { + NMIPENDSET_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Control and State Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [icsr](index.html) module"] +pub struct ICSR_SPEC; +impl crate::RegisterSpec for ICSR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [icsr::R](R) reader structure"] +impl crate::Readable for ICSR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [icsr::W](W) writer structure"] +impl crate::Writable for ICSR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ICSR to value 0"] +impl crate::Resettable for ICSR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/system_control/scr.rs b/pac/atsamc20e/src/system_control/scr.rs new file mode 100644 index 000000000000..db9c54fe6f6f --- /dev/null +++ b/pac/atsamc20e/src/system_control/scr.rs @@ -0,0 +1,348 @@ +#[doc = "Register `SCR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SCR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Sleep-On-Exit when exiting Handler mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SLEEPONEXIT_A { + #[doc = "0: O not sleep when returning to Thread mode"] + VALUE_0 = 0, + #[doc = "1: Enter sleep, or deep sleep, on return from an ISR"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SLEEPONEXIT_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SLEEPONEXIT` reader - Sleep-On-Exit when exiting Handler mode"] +pub struct SLEEPONEXIT_R(crate::FieldReader); +impl SLEEPONEXIT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLEEPONEXIT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SLEEPONEXIT_A { + match self.bits { + false => SLEEPONEXIT_A::VALUE_0, + true => SLEEPONEXIT_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == SLEEPONEXIT_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == SLEEPONEXIT_A::VALUE_1 + } +} +impl core::ops::Deref for SLEEPONEXIT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLEEPONEXIT` writer - Sleep-On-Exit when exiting Handler mode"] +pub struct SLEEPONEXIT_W<'a> { + w: &'a mut W, +} +impl<'a> SLEEPONEXIT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SLEEPONEXIT_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "O not sleep when returning to Thread mode"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(SLEEPONEXIT_A::VALUE_0) + } + #[doc = "Enter sleep, or deep sleep, on return from an ISR"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(SLEEPONEXIT_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Uses Deep Sleep as low power mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SLEEPDEEP_A { + #[doc = "0: Sleep"] + VALUE_0 = 0, + #[doc = "1: Deep sleep"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SLEEPDEEP_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SLEEPDEEP` reader - Uses Deep Sleep as low power mode"] +pub struct SLEEPDEEP_R(crate::FieldReader); +impl SLEEPDEEP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLEEPDEEP_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SLEEPDEEP_A { + match self.bits { + false => SLEEPDEEP_A::VALUE_0, + true => SLEEPDEEP_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == SLEEPDEEP_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == SLEEPDEEP_A::VALUE_1 + } +} +impl core::ops::Deref for SLEEPDEEP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLEEPDEEP` writer - Uses Deep Sleep as low power mode"] +pub struct SLEEPDEEP_W<'a> { + w: &'a mut W, +} +impl<'a> SLEEPDEEP_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SLEEPDEEP_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Sleep"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(SLEEPDEEP_A::VALUE_0) + } + #[doc = "Deep sleep"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(SLEEPDEEP_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Send Event on Pending bit\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SEVONPEND_A { + #[doc = "0: Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded"] + VALUE_0 = 0, + #[doc = "1: Enabled events and all interrupts, including disabled interrupts, can wakeup the processor"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SEVONPEND_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SEVONPEND` reader - Send Event on Pending bit"] +pub struct SEVONPEND_R(crate::FieldReader); +impl SEVONPEND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SEVONPEND_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SEVONPEND_A { + match self.bits { + false => SEVONPEND_A::VALUE_0, + true => SEVONPEND_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == SEVONPEND_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == SEVONPEND_A::VALUE_1 + } +} +impl core::ops::Deref for SEVONPEND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEVONPEND` writer - Send Event on Pending bit"] +pub struct SEVONPEND_W<'a> { + w: &'a mut W, +} +impl<'a> SEVONPEND_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SEVONPEND_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(SEVONPEND_A::VALUE_0) + } + #[doc = "Enabled events and all interrupts, including disabled interrupts, can wakeup the processor"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(SEVONPEND_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +impl R { + #[doc = "Bit 1 - Sleep-On-Exit when exiting Handler mode"] + #[inline(always)] + pub fn sleeponexit(&self) -> SLEEPONEXIT_R { + SLEEPONEXIT_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Uses Deep Sleep as low power mode"] + #[inline(always)] + pub fn sleepdeep(&self) -> SLEEPDEEP_R { + SLEEPDEEP_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 4 - Send Event on Pending bit"] + #[inline(always)] + pub fn sevonpend(&self) -> SEVONPEND_R { + SEVONPEND_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 1 - Sleep-On-Exit when exiting Handler mode"] + #[inline(always)] + pub fn sleeponexit(&mut self) -> SLEEPONEXIT_W { + SLEEPONEXIT_W { w: self } + } + #[doc = "Bit 2 - Uses Deep Sleep as low power mode"] + #[inline(always)] + pub fn sleepdeep(&mut self) -> SLEEPDEEP_W { + SLEEPDEEP_W { w: self } + } + #[doc = "Bit 4 - Send Event on Pending bit"] + #[inline(always)] + pub fn sevonpend(&mut self) -> SEVONPEND_W { + SEVONPEND_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "System Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [scr](index.html) module"] +pub struct SCR_SPEC; +impl crate::RegisterSpec for SCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [scr::R](R) reader structure"] +impl crate::Readable for SCR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [scr::W](W) writer structure"] +impl crate::Writable for SCR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SCR to value 0"] +impl crate::Resettable for SCR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/system_control/shcsr.rs b/pac/atsamc20e/src/system_control/shcsr.rs new file mode 100644 index 000000000000..bfba26ac06ad --- /dev/null +++ b/pac/atsamc20e/src/system_control/shcsr.rs @@ -0,0 +1,113 @@ +#[doc = "Register `SHCSR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SHCSR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SVCALLPENDED` reader - "] +pub struct SVCALLPENDED_R(crate::FieldReader); +impl SVCALLPENDED_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SVCALLPENDED_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SVCALLPENDED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SVCALLPENDED` writer - "] +pub struct SVCALLPENDED_W<'a> { + w: &'a mut W, +} +impl<'a> SVCALLPENDED_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 15"] + #[inline(always)] + pub fn svcallpended(&self) -> SVCALLPENDED_R { + SVCALLPENDED_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 15"] + #[inline(always)] + pub fn svcallpended(&mut self) -> SVCALLPENDED_W { + SVCALLPENDED_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "System Handler Control and State Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [shcsr](index.html) module"] +pub struct SHCSR_SPEC; +impl crate::RegisterSpec for SHCSR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [shcsr::R](R) reader structure"] +impl crate::Readable for SHCSR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [shcsr::W](W) writer structure"] +impl crate::Writable for SHCSR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SHCSR to value 0"] +impl crate::Resettable for SHCSR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/system_control/shpr2.rs b/pac/atsamc20e/src/system_control/shpr2.rs new file mode 100644 index 000000000000..5665d6a5e8a9 --- /dev/null +++ b/pac/atsamc20e/src/system_control/shpr2.rs @@ -0,0 +1,103 @@ +#[doc = "Register `SHPR2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SHPR2` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PRI_11` reader - Priority of system handler 11, SVCall"] +pub struct PRI_11_R(crate::FieldReader); +impl PRI_11_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRI_11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PRI_11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRI_11` writer - Priority of system handler 11, SVCall"] +pub struct PRI_11_W<'a> { + w: &'a mut W, +} +impl<'a> PRI_11_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 24)) | ((value as u32 & 0xff) << 24); + self.w + } +} +impl R { + #[doc = "Bits 24:31 - Priority of system handler 11, SVCall"] + #[inline(always)] + pub fn pri_11(&self) -> PRI_11_R { + PRI_11_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 24:31 - Priority of system handler 11, SVCall"] + #[inline(always)] + pub fn pri_11(&mut self) -> PRI_11_W { + PRI_11_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "System Handler Priority Register 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [shpr2](index.html) module"] +pub struct SHPR2_SPEC; +impl crate::RegisterSpec for SHPR2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [shpr2::R](R) reader structure"] +impl crate::Readable for SHPR2_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [shpr2::W](W) writer structure"] +impl crate::Writable for SHPR2_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SHPR2 to value 0"] +impl crate::Resettable for SHPR2_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/system_control/shpr3.rs b/pac/atsamc20e/src/system_control/shpr3.rs new file mode 100644 index 000000000000..cb5a92c53503 --- /dev/null +++ b/pac/atsamc20e/src/system_control/shpr3.rs @@ -0,0 +1,140 @@ +#[doc = "Register `SHPR3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SHPR3` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PRI_14` reader - Priority of system handler 14, PendSV"] +pub struct PRI_14_R(crate::FieldReader); +impl PRI_14_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRI_14_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PRI_14_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRI_14` writer - Priority of system handler 14, PendSV"] +pub struct PRI_14_W<'a> { + w: &'a mut W, +} +impl<'a> PRI_14_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +#[doc = "Field `PRI_15` reader - Priority of system handler 15, SysTick exception"] +pub struct PRI_15_R(crate::FieldReader); +impl PRI_15_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRI_15_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PRI_15_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRI_15` writer - Priority of system handler 15, SysTick exception"] +pub struct PRI_15_W<'a> { + w: &'a mut W, +} +impl<'a> PRI_15_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 24)) | ((value as u32 & 0xff) << 24); + self.w + } +} +impl R { + #[doc = "Bits 16:23 - Priority of system handler 14, PendSV"] + #[inline(always)] + pub fn pri_14(&self) -> PRI_14_R { + PRI_14_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Priority of system handler 15, SysTick exception"] + #[inline(always)] + pub fn pri_15(&self) -> PRI_15_R { + PRI_15_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 16:23 - Priority of system handler 14, PendSV"] + #[inline(always)] + pub fn pri_14(&mut self) -> PRI_14_W { + PRI_14_W { w: self } + } + #[doc = "Bits 24:31 - Priority of system handler 15, SysTick exception"] + #[inline(always)] + pub fn pri_15(&mut self) -> PRI_15_W { + PRI_15_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "System Handler Priority Register 3\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [shpr3](index.html) module"] +pub struct SHPR3_SPEC; +impl crate::RegisterSpec for SHPR3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [shpr3::R](R) reader structure"] +impl crate::Readable for SHPR3_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [shpr3::W](W) writer structure"] +impl crate::Writable for SHPR3_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SHPR3 to value 0"] +impl crate::Resettable for SHPR3_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/system_control/vtor.rs b/pac/atsamc20e/src/system_control/vtor.rs new file mode 100644 index 000000000000..0ee4c7817817 --- /dev/null +++ b/pac/atsamc20e/src/system_control/vtor.rs @@ -0,0 +1,103 @@ +#[doc = "Register `VTOR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `VTOR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TBLOFF` reader - Vector table base offset"] +pub struct TBLOFF_R(crate::FieldReader); +impl TBLOFF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + TBLOFF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TBLOFF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TBLOFF` writer - Vector table base offset"] +pub struct TBLOFF_W<'a> { + w: &'a mut W, +} +impl<'a> TBLOFF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01ff_ffff << 7)) | ((value as u32 & 0x01ff_ffff) << 7); + self.w + } +} +impl R { + #[doc = "Bits 7:31 - Vector table base offset"] + #[inline(always)] + pub fn tbloff(&self) -> TBLOFF_R { + TBLOFF_R::new(((self.bits >> 7) & 0x01ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 7:31 - Vector table base offset"] + #[inline(always)] + pub fn tbloff(&mut self) -> TBLOFF_W { + TBLOFF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Vector Table Offset Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [vtor](index.html) module"] +pub struct VTOR_SPEC; +impl crate::RegisterSpec for VTOR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [vtor::R](R) reader structure"] +impl crate::Readable for VTOR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [vtor::W](W) writer structure"] +impl crate::Writable for VTOR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets VTOR to value 0"] +impl crate::Resettable for VTOR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/tc0.rs b/pac/atsamc20e/src/tc0.rs new file mode 100644 index 000000000000..86e973b276e7 --- /dev/null +++ b/pac/atsamc20e/src/tc0.rs @@ -0,0 +1,146 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved_0_count8: [u8; 0x38], +} +impl RegisterBlock { + #[doc = "0x00..0x38 - 32-bit Counter Mode"] + #[inline(always)] + pub fn count32(&self) -> &COUNT32 { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const COUNT32) } + } + #[doc = "0x00..0x34 - 16-bit Counter Mode"] + #[inline(always)] + pub fn count16(&self) -> &COUNT16 { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const COUNT16) } + } + #[doc = "0x00..0x32 - 8-bit Counter Mode"] + #[inline(always)] + pub fn count8(&self) -> &COUNT8 { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const COUNT8) } + } +} +#[doc = r"Register block"] +#[repr(C)] +pub struct COUNT8 { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - Control B Clear"] + pub ctrlbclr: crate::Reg, + #[doc = "0x05 - Control B Set"] + pub ctrlbset: crate::Reg, + #[doc = "0x06 - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x08 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x09 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x0a - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x0b - Status"] + pub status: crate::Reg, + #[doc = "0x0c - Waveform Generation Control"] + pub wave: crate::Reg, + #[doc = "0x0d - Control C"] + pub drvctrl: crate::Reg, + _reserved10: [u8; 0x01], + #[doc = "0x0f - Debug Control"] + pub dbgctrl: crate::Reg, + #[doc = "0x10 - Synchronization Status"] + pub syncbusy: crate::Reg, + #[doc = "0x14 - COUNT8 Count"] + pub count: crate::Reg, + _reserved13: [u8; 0x06], + #[doc = "0x1b - COUNT8 Period"] + pub per: crate::Reg, + #[doc = "0x1c - COUNT8 Compare and Capture"] + pub cc: [crate::Reg; 2], + _reserved15: [u8; 0x11], + #[doc = "0x2f - COUNT8 Period Buffer"] + pub perbuf: crate::Reg, + #[doc = "0x30 - COUNT8 Compare and Capture Buffer"] + pub ccbuf: [crate::Reg; 2], +} +#[doc = r"Register block"] +#[doc = "8-bit Counter Mode"] +pub mod count8; +#[doc = r"Register block"] +#[repr(C)] +pub struct COUNT16 { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - Control B Clear"] + pub ctrlbclr: crate::Reg, + #[doc = "0x05 - Control B Set"] + pub ctrlbset: crate::Reg, + #[doc = "0x06 - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x08 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x09 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x0a - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x0b - Status"] + pub status: crate::Reg, + #[doc = "0x0c - Waveform Generation Control"] + pub wave: crate::Reg, + #[doc = "0x0d - Control C"] + pub drvctrl: crate::Reg, + _reserved10: [u8; 0x01], + #[doc = "0x0f - Debug Control"] + pub dbgctrl: crate::Reg, + #[doc = "0x10 - Synchronization Status"] + pub syncbusy: crate::Reg, + #[doc = "0x14 - COUNT16 Count"] + pub count: crate::Reg, + _reserved13: [u8; 0x06], + #[doc = "0x1c - COUNT16 Compare and Capture"] + pub cc: [crate::Reg; 2], + _reserved14: [u8; 0x10], + #[doc = "0x30 - COUNT16 Compare and Capture Buffer"] + pub ccbuf: [crate::Reg; 2], +} +#[doc = r"Register block"] +#[doc = "16-bit Counter Mode"] +pub mod count16; +#[doc = r"Register block"] +#[repr(C)] +pub struct COUNT32 { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - Control B Clear"] + pub ctrlbclr: crate::Reg, + #[doc = "0x05 - Control B Set"] + pub ctrlbset: crate::Reg, + #[doc = "0x06 - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x08 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x09 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x0a - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x0b - Status"] + pub status: crate::Reg, + #[doc = "0x0c - Waveform Generation Control"] + pub wave: crate::Reg, + #[doc = "0x0d - Control C"] + pub drvctrl: crate::Reg, + _reserved10: [u8; 0x01], + #[doc = "0x0f - Debug Control"] + pub dbgctrl: crate::Reg, + #[doc = "0x10 - Synchronization Status"] + pub syncbusy: crate::Reg, + #[doc = "0x14 - COUNT32 Count"] + pub count: crate::Reg, + _reserved13: [u8; 0x04], + #[doc = "0x1c..0x24 - COUNT32 Compare and Capture"] + pub cc: [crate::Reg; 2], + _reserved14: [u8; 0x0c], + #[doc = "0x30..0x38 - COUNT32 Compare and Capture Buffer"] + pub ccbuf: [crate::Reg; 2], +} +#[doc = r"Register block"] +#[doc = "32-bit Counter Mode"] +pub mod count32; diff --git a/pac/atsamc20e/src/tc0/count16.rs b/pac/atsamc20e/src/tc0/count16.rs new file mode 100644 index 000000000000..5bd1e88c7efb --- /dev/null +++ b/pac/atsamc20e/src/tc0/count16.rs @@ -0,0 +1,60 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "CTRLBCLR register accessor: an alias for `Reg`"] +pub type CTRLBCLR = crate::Reg; +#[doc = "Control B Clear"] +pub mod ctrlbclr; +#[doc = "CTRLBSET register accessor: an alias for `Reg`"] +pub type CTRLBSET = crate::Reg; +#[doc = "Control B Set"] +pub mod ctrlbset; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "WAVE register accessor: an alias for `Reg`"] +pub type WAVE = crate::Reg; +#[doc = "Waveform Generation Control"] +pub mod wave; +#[doc = "DRVCTRL register accessor: an alias for `Reg`"] +pub type DRVCTRL = crate::Reg; +#[doc = "Control C"] +pub mod drvctrl; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Status"] +pub mod syncbusy; +#[doc = "COUNT register accessor: an alias for `Reg`"] +pub type COUNT = crate::Reg; +#[doc = "COUNT16 Count"] +pub mod count; +#[doc = "CC register accessor: an alias for `Reg`"] +pub type CC = crate::Reg; +#[doc = "COUNT16 Compare and Capture"] +pub mod cc; +#[doc = "CCBUF register accessor: an alias for `Reg`"] +pub type CCBUF = crate::Reg; +#[doc = "COUNT16 Compare and Capture Buffer"] +pub mod ccbuf; diff --git a/pac/atsamc20e/src/tc0/count16/cc.rs b/pac/atsamc20e/src/tc0/count16/cc.rs new file mode 100644 index 000000000000..b6f975905e31 --- /dev/null +++ b/pac/atsamc20e/src/tc0/count16/cc.rs @@ -0,0 +1,104 @@ +#[doc = "Register `CC[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CC[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CC` reader - Counter/Compare Value"] +pub struct CC_R(crate::FieldReader); +impl CC_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + CC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC` writer - Counter/Compare Value"] +pub struct CC_W<'a> { + w: &'a mut W, +} +impl<'a> CC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Counter/Compare Value"] + #[inline(always)] + pub fn cc(&self) -> CC_R { + CC_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Counter/Compare Value"] + #[inline(always)] + pub fn cc(&mut self) -> CC_W { + CC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT16 Compare and Capture\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc](index.html) module"] +pub struct CC_SPEC; +impl crate::RegisterSpec for CC_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [cc::R](R) reader structure"] +impl crate::Readable for CC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cc::W](W) writer structure"] +impl crate::Writable for CC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CC[%s] +to value 0"] +impl crate::Resettable for CC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/tc0/count16/ccbuf.rs b/pac/atsamc20e/src/tc0/count16/ccbuf.rs new file mode 100644 index 000000000000..2f922bba8d31 --- /dev/null +++ b/pac/atsamc20e/src/tc0/count16/ccbuf.rs @@ -0,0 +1,104 @@ +#[doc = "Register `CCBUF[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CCBUF[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CCBUF` reader - Counter/Compare Buffer Value"] +pub struct CCBUF_R(crate::FieldReader); +impl CCBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + CCBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUF` writer - Counter/Compare Buffer Value"] +pub struct CCBUF_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Counter/Compare Buffer Value"] + #[inline(always)] + pub fn ccbuf(&self) -> CCBUF_R { + CCBUF_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Counter/Compare Buffer Value"] + #[inline(always)] + pub fn ccbuf(&mut self) -> CCBUF_W { + CCBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT16 Compare and Capture Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccbuf](index.html) module"] +pub struct CCBUF_SPEC; +impl crate::RegisterSpec for CCBUF_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ccbuf::R](R) reader structure"] +impl crate::Readable for CCBUF_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ccbuf::W](W) writer structure"] +impl crate::Writable for CCBUF_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CCBUF[%s] +to value 0"] +impl crate::Resettable for CCBUF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/tc0/count16/count.rs b/pac/atsamc20e/src/tc0/count16/count.rs new file mode 100644 index 000000000000..5d26b509abb1 --- /dev/null +++ b/pac/atsamc20e/src/tc0/count16/count.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT16 Count\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count](index.html) module"] +pub struct COUNT_SPEC; +impl crate::RegisterSpec for COUNT_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [count::R](R) reader structure"] +impl crate::Readable for COUNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count::W](W) writer structure"] +impl crate::Writable for COUNT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT to value 0"] +impl crate::Resettable for COUNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/tc0/count16/ctrla.rs b/pac/atsamc20e/src/tc0/count16/ctrla.rs new file mode 100644 index 000000000000..cadcddaaead8 --- /dev/null +++ b/pac/atsamc20e/src/tc0/count16/ctrla.rs @@ -0,0 +1,851 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Timer Counter Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: Counter in 16-bit mode"] + COUNT16 = 0, + #[doc = "1: Counter in 8-bit mode"] + COUNT8 = 1, + #[doc = "2: Counter in 32-bit mode"] + COUNT32 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Timer Counter Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::COUNT16), + 1 => Some(MODE_A::COUNT8), + 2 => Some(MODE_A::COUNT32), + _ => None, + } + } + #[doc = "Checks if the value of the field is `COUNT16`"] + #[inline(always)] + pub fn is_count16(&self) -> bool { + **self == MODE_A::COUNT16 + } + #[doc = "Checks if the value of the field is `COUNT8`"] + #[inline(always)] + pub fn is_count8(&self) -> bool { + **self == MODE_A::COUNT8 + } + #[doc = "Checks if the value of the field is `COUNT32`"] + #[inline(always)] + pub fn is_count32(&self) -> bool { + **self == MODE_A::COUNT32 + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Timer Counter Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Counter in 16-bit mode"] + #[inline(always)] + pub fn count16(self) -> &'a mut W { + self.variant(MODE_A::COUNT16) + } + #[doc = "Counter in 8-bit mode"] + #[inline(always)] + pub fn count8(self) -> &'a mut W { + self.variant(MODE_A::COUNT8) + } + #[doc = "Counter in 32-bit mode"] + #[inline(always)] + pub fn count32(self) -> &'a mut W { + self.variant(MODE_A::COUNT32) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u32 & 0x03) << 2); + self.w + } +} +#[doc = "Prescaler and Counter Synchronization\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCSYNC_A { + #[doc = "0: Reload or reset the counter on next generic clock"] + GCLK = 0, + #[doc = "1: Reload or reset the counter on next prescaler clock"] + PRESC = 1, + #[doc = "2: Reload or reset the counter on next generic clock and reset the prescaler counter"] + RESYNC = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCSYNC_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCSYNC` reader - Prescaler and Counter Synchronization"] +pub struct PRESCSYNC_R(crate::FieldReader); +impl PRESCSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCSYNC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCSYNC_A::GCLK), + 1 => Some(PRESCSYNC_A::PRESC), + 2 => Some(PRESCSYNC_A::RESYNC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `GCLK`"] + #[inline(always)] + pub fn is_gclk(&self) -> bool { + **self == PRESCSYNC_A::GCLK + } + #[doc = "Checks if the value of the field is `PRESC`"] + #[inline(always)] + pub fn is_presc(&self) -> bool { + **self == PRESCSYNC_A::PRESC + } + #[doc = "Checks if the value of the field is `RESYNC`"] + #[inline(always)] + pub fn is_resync(&self) -> bool { + **self == PRESCSYNC_A::RESYNC + } +} +impl core::ops::Deref for PRESCSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCSYNC` writer - Prescaler and Counter Synchronization"] +pub struct PRESCSYNC_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCSYNC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCSYNC_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Reload or reset the counter on next generic clock"] + #[inline(always)] + pub fn gclk(self) -> &'a mut W { + self.variant(PRESCSYNC_A::GCLK) + } + #[doc = "Reload or reset the counter on next prescaler clock"] + #[inline(always)] + pub fn presc(self) -> &'a mut W { + self.variant(PRESCSYNC_A::PRESC) + } + #[doc = "Reload or reset the counter on next generic clock and reset the prescaler counter"] + #[inline(always)] + pub fn resync(self) -> &'a mut W { + self.variant(PRESCSYNC_A::RESYNC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u32 & 0x03) << 4); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - Clock On Demand"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - Clock On Demand"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: Prescaler: GCLK_TC"] + DIV1 = 0, + #[doc = "1: Prescaler: GCLK_TC/2"] + DIV2 = 1, + #[doc = "2: Prescaler: GCLK_TC/4"] + DIV4 = 2, + #[doc = "3: Prescaler: GCLK_TC/8"] + DIV8 = 3, + #[doc = "4: Prescaler: GCLK_TC/16"] + DIV16 = 4, + #[doc = "5: Prescaler: GCLK_TC/64"] + DIV64 = 5, + #[doc = "6: Prescaler: GCLK_TC/256"] + DIV256 = 6, + #[doc = "7: Prescaler: GCLK_TC/1024"] + DIV1024 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PRESCALER_A { + match self.bits { + 0 => PRESCALER_A::DIV1, + 1 => PRESCALER_A::DIV2, + 2 => PRESCALER_A::DIV4, + 3 => PRESCALER_A::DIV8, + 4 => PRESCALER_A::DIV16, + 5 => PRESCALER_A::DIV64, + 6 => PRESCALER_A::DIV256, + 7 => PRESCALER_A::DIV1024, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == PRESCALER_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PRESCALER_A::DIV1024 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Prescaler: GCLK_TC"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1) + } + #[doc = "Prescaler: GCLK_TC/2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "Prescaler: GCLK_TC/4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "Prescaler: GCLK_TC/8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "Prescaler: GCLK_TC/16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "Prescaler: GCLK_TC/64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "Prescaler: GCLK_TC/256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = "Prescaler: GCLK_TC/1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +#[doc = "Field `ALOCK` reader - Auto Lock"] +pub struct ALOCK_R(crate::FieldReader); +impl ALOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALOCK` writer - Auto Lock"] +pub struct ALOCK_W<'a> { + w: &'a mut W, +} +impl<'a> ALOCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `CAPTEN0` reader - Capture Channel 0 Enable"] +pub struct CAPTEN0_R(crate::FieldReader); +impl CAPTEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CAPTEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CAPTEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAPTEN0` writer - Capture Channel 0 Enable"] +pub struct CAPTEN0_W<'a> { + w: &'a mut W, +} +impl<'a> CAPTEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `CAPTEN1` reader - Capture Channel 1 Enable"] +pub struct CAPTEN1_R(crate::FieldReader); +impl CAPTEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CAPTEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CAPTEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAPTEN1` writer - Capture Channel 1 Enable"] +pub struct CAPTEN1_W<'a> { + w: &'a mut W, +} +impl<'a> CAPTEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `COPEN0` reader - Capture On Pin 0 Enable"] +pub struct COPEN0_R(crate::FieldReader); +impl COPEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COPEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COPEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COPEN0` writer - Capture On Pin 0 Enable"] +pub struct COPEN0_W<'a> { + w: &'a mut W, +} +impl<'a> COPEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `COPEN1` reader - Capture On Pin 1 Enable"] +pub struct COPEN1_R(crate::FieldReader); +impl COPEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COPEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COPEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COPEN1` writer - Capture On Pin 1 Enable"] +pub struct COPEN1_W<'a> { + w: &'a mut W, +} +impl<'a> COPEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:3 - Timer Counter Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bits 4:5 - Prescaler and Counter Synchronization"] + #[inline(always)] + pub fn prescsync(&self) -> PRESCSYNC_R { + PRESCSYNC_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Clock On Demand"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 11 - Auto Lock"] + #[inline(always)] + pub fn alock(&self) -> ALOCK_R { + ALOCK_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 16 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn capten0(&self) -> CAPTEN0_R { + CAPTEN0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn capten1(&self) -> CAPTEN1_R { + CAPTEN1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 20 - Capture On Pin 0 Enable"] + #[inline(always)] + pub fn copen0(&self) -> COPEN0_R { + COPEN0_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Capture On Pin 1 Enable"] + #[inline(always)] + pub fn copen1(&self) -> COPEN1_R { + COPEN1_R::new(((self.bits >> 21) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:3 - Timer Counter Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bits 4:5 - Prescaler and Counter Synchronization"] + #[inline(always)] + pub fn prescsync(&mut self) -> PRESCSYNC_W { + PRESCSYNC_W { w: self } + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - Clock On Demand"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Bit 11 - Auto Lock"] + #[inline(always)] + pub fn alock(&mut self) -> ALOCK_W { + ALOCK_W { w: self } + } + #[doc = "Bit 16 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn capten0(&mut self) -> CAPTEN0_W { + CAPTEN0_W { w: self } + } + #[doc = "Bit 17 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn capten1(&mut self) -> CAPTEN1_W { + CAPTEN1_W { w: self } + } + #[doc = "Bit 20 - Capture On Pin 0 Enable"] + #[inline(always)] + pub fn copen0(&mut self) -> COPEN0_W { + COPEN0_W { w: self } + } + #[doc = "Bit 21 - Capture On Pin 1 Enable"] + #[inline(always)] + pub fn copen1(&mut self) -> COPEN1_W { + COPEN1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/tc0/count16/ctrlbclr.rs b/pac/atsamc20e/src/tc0/count16/ctrlbclr.rs new file mode 100644 index 000000000000..76265674036a --- /dev/null +++ b/pac/atsamc20e/src/tc0/count16/ctrlbclr.rs @@ -0,0 +1,345 @@ +#[doc = "Register `CTRLBCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Counter Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `LUPD` reader - Lock Update"] +pub struct LUPD_R(crate::FieldReader); +impl LUPD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LUPD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LUPD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LUPD` writer - Lock Update"] +pub struct LUPD_W<'a> { + w: &'a mut W, +} +impl<'a> LUPD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ONESHOT` reader - One-Shot on Counter"] +pub struct ONESHOT_R(crate::FieldReader); +impl ONESHOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONESHOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONESHOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONESHOT` writer - One-Shot on Counter"] +pub struct ONESHOT_W<'a> { + w: &'a mut W, +} +impl<'a> ONESHOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Force a start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force a stop"] + STOP = 2, + #[doc = "3: Force update of double-buffered register"] + UPDATE = 3, + #[doc = "4: Force a read synchronization of COUNT"] + READSYNC = 4, + #[doc = "5: One-shot DMA trigger"] + DMAOS = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NONE), + 1 => Some(CMD_A::RETRIGGER), + 2 => Some(CMD_A::STOP), + 3 => Some(CMD_A::UPDATE), + 4 => Some(CMD_A::READSYNC), + 5 => Some(CMD_A::DMAOS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == CMD_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == CMD_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == CMD_A::STOP + } + #[doc = "Checks if the value of the field is `UPDATE`"] + #[inline(always)] + pub fn is_update(&self) -> bool { + **self == CMD_A::UPDATE + } + #[doc = "Checks if the value of the field is `READSYNC`"] + #[inline(always)] + pub fn is_readsync(&self) -> bool { + **self == CMD_A::READSYNC + } + #[doc = "Checks if the value of the field is `DMAOS`"] + #[inline(always)] + pub fn is_dmaos(&self) -> bool { + **self == CMD_A::DMAOS + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMD_A::NONE) + } + #[doc = "Force a start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMD_A::RETRIGGER) + } + #[doc = "Force a stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMD_A::STOP) + } + #[doc = "Force update of double-buffered register"] + #[inline(always)] + pub fn update(self) -> &'a mut W { + self.variant(CMD_A::UPDATE) + } + #[doc = "Force a read synchronization of COUNT"] + #[inline(always)] + pub fn readsync(self) -> &'a mut W { + self.variant(CMD_A::READSYNC) + } + #[doc = "One-shot DMA trigger"] + #[inline(always)] + pub fn dmaos(self) -> &'a mut W { + self.variant(CMD_A::DMAOS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 5)) | ((value as u8 & 0x07) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&self) -> LUPD_R { + LUPD_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 5) & 0x07) as u8) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&mut self) -> LUPD_W { + LUPD_W { w: self } + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&mut self) -> ONESHOT_W { + ONESHOT_W { w: self } + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbclr](index.html) module"] +pub struct CTRLBCLR_SPEC; +impl crate::RegisterSpec for CTRLBCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbclr::R](R) reader structure"] +impl crate::Readable for CTRLBCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbclr::W](W) writer structure"] +impl crate::Writable for CTRLBCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLBCLR to value 0"] +impl crate::Resettable for CTRLBCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/tc0/count16/ctrlbset.rs b/pac/atsamc20e/src/tc0/count16/ctrlbset.rs new file mode 100644 index 000000000000..610914c9c7c8 --- /dev/null +++ b/pac/atsamc20e/src/tc0/count16/ctrlbset.rs @@ -0,0 +1,345 @@ +#[doc = "Register `CTRLBSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Counter Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `LUPD` reader - Lock Update"] +pub struct LUPD_R(crate::FieldReader); +impl LUPD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LUPD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LUPD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LUPD` writer - Lock Update"] +pub struct LUPD_W<'a> { + w: &'a mut W, +} +impl<'a> LUPD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ONESHOT` reader - One-Shot on Counter"] +pub struct ONESHOT_R(crate::FieldReader); +impl ONESHOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONESHOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONESHOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONESHOT` writer - One-Shot on Counter"] +pub struct ONESHOT_W<'a> { + w: &'a mut W, +} +impl<'a> ONESHOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Force a start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force a stop"] + STOP = 2, + #[doc = "3: Force update of double-buffered register"] + UPDATE = 3, + #[doc = "4: Force a read synchronization of COUNT"] + READSYNC = 4, + #[doc = "5: One-shot DMA trigger"] + DMAOS = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NONE), + 1 => Some(CMD_A::RETRIGGER), + 2 => Some(CMD_A::STOP), + 3 => Some(CMD_A::UPDATE), + 4 => Some(CMD_A::READSYNC), + 5 => Some(CMD_A::DMAOS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == CMD_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == CMD_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == CMD_A::STOP + } + #[doc = "Checks if the value of the field is `UPDATE`"] + #[inline(always)] + pub fn is_update(&self) -> bool { + **self == CMD_A::UPDATE + } + #[doc = "Checks if the value of the field is `READSYNC`"] + #[inline(always)] + pub fn is_readsync(&self) -> bool { + **self == CMD_A::READSYNC + } + #[doc = "Checks if the value of the field is `DMAOS`"] + #[inline(always)] + pub fn is_dmaos(&self) -> bool { + **self == CMD_A::DMAOS + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMD_A::NONE) + } + #[doc = "Force a start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMD_A::RETRIGGER) + } + #[doc = "Force a stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMD_A::STOP) + } + #[doc = "Force update of double-buffered register"] + #[inline(always)] + pub fn update(self) -> &'a mut W { + self.variant(CMD_A::UPDATE) + } + #[doc = "Force a read synchronization of COUNT"] + #[inline(always)] + pub fn readsync(self) -> &'a mut W { + self.variant(CMD_A::READSYNC) + } + #[doc = "One-shot DMA trigger"] + #[inline(always)] + pub fn dmaos(self) -> &'a mut W { + self.variant(CMD_A::DMAOS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 5)) | ((value as u8 & 0x07) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&self) -> LUPD_R { + LUPD_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 5) & 0x07) as u8) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&mut self) -> LUPD_W { + LUPD_W { w: self } + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&mut self) -> ONESHOT_W { + ONESHOT_W { w: self } + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbset](index.html) module"] +pub struct CTRLBSET_SPEC; +impl crate::RegisterSpec for CTRLBSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbset::R](R) reader structure"] +impl crate::Readable for CTRLBSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbset::W](W) writer structure"] +impl crate::Writable for CTRLBSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLBSET to value 0"] +impl crate::Resettable for CTRLBSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/tc0/count16/dbgctrl.rs b/pac/atsamc20e/src/tc0/count16/dbgctrl.rs new file mode 100644 index 000000000000..0383e70d0429 --- /dev/null +++ b/pac/atsamc20e/src/tc0/count16/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Run During Debug"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Run During Debug"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/tc0/count16/drvctrl.rs b/pac/atsamc20e/src/tc0/count16/drvctrl.rs new file mode 100644 index 000000000000..323926b4b22d --- /dev/null +++ b/pac/atsamc20e/src/tc0/count16/drvctrl.rs @@ -0,0 +1,160 @@ +#[doc = "Register `DRVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DRVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INVEN0` reader - Output Waveform Invert Enable 0"] +pub struct INVEN0_R(crate::FieldReader); +impl INVEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN0` writer - Output Waveform Invert Enable 0"] +pub struct INVEN0_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `INVEN1` reader - Output Waveform Invert Enable 1"] +pub struct INVEN1_R(crate::FieldReader); +impl INVEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN1` writer - Output Waveform Invert Enable 1"] +pub struct INVEN1_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - Output Waveform Invert Enable 0"] + #[inline(always)] + pub fn inven0(&self) -> INVEN0_R { + INVEN0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Output Waveform Invert Enable 1"] + #[inline(always)] + pub fn inven1(&self) -> INVEN1_R { + INVEN1_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Output Waveform Invert Enable 0"] + #[inline(always)] + pub fn inven0(&mut self) -> INVEN0_W { + INVEN0_W { w: self } + } + #[doc = "Bit 1 - Output Waveform Invert Enable 1"] + #[inline(always)] + pub fn inven1(&mut self) -> INVEN1_W { + INVEN1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control C\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [drvctrl](index.html) module"] +pub struct DRVCTRL_SPEC; +impl crate::RegisterSpec for DRVCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [drvctrl::R](R) reader structure"] +impl crate::Readable for DRVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [drvctrl::W](W) writer structure"] +impl crate::Writable for DRVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DRVCTRL to value 0"] +impl crate::Resettable for DRVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/tc0/count16/evctrl.rs b/pac/atsamc20e/src/tc0/count16/evctrl.rs new file mode 100644 index 000000000000..7d4c38d486c1 --- /dev/null +++ b/pac/atsamc20e/src/tc0/count16/evctrl.rs @@ -0,0 +1,465 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Event Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EVACT_A { + #[doc = "0: Event action disabled"] + OFF = 0, + #[doc = "1: Start, restart or retrigger TC on event"] + RETRIGGER = 1, + #[doc = "2: Count on event"] + COUNT = 2, + #[doc = "3: Start TC on event"] + START = 3, + #[doc = "4: Time stamp capture"] + STAMP = 4, + #[doc = "5: Period catured in CC0, pulse width in CC1"] + PPW = 5, + #[doc = "6: Period catured in CC1, pulse width in CC0"] + PWP = 6, + #[doc = "7: Pulse width capture"] + PW = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EVACT_A) -> Self { + variant as _ + } +} +#[doc = "Field `EVACT` reader - Event Action"] +pub struct EVACT_R(crate::FieldReader); +impl EVACT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVACT_A { + match self.bits { + 0 => EVACT_A::OFF, + 1 => EVACT_A::RETRIGGER, + 2 => EVACT_A::COUNT, + 3 => EVACT_A::START, + 4 => EVACT_A::STAMP, + 5 => EVACT_A::PPW, + 6 => EVACT_A::PWP, + 7 => EVACT_A::PW, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == EVACT_A::OFF + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == EVACT_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `COUNT`"] + #[inline(always)] + pub fn is_count(&self) -> bool { + **self == EVACT_A::COUNT + } + #[doc = "Checks if the value of the field is `START`"] + #[inline(always)] + pub fn is_start(&self) -> bool { + **self == EVACT_A::START + } + #[doc = "Checks if the value of the field is `STAMP`"] + #[inline(always)] + pub fn is_stamp(&self) -> bool { + **self == EVACT_A::STAMP + } + #[doc = "Checks if the value of the field is `PPW`"] + #[inline(always)] + pub fn is_ppw(&self) -> bool { + **self == EVACT_A::PPW + } + #[doc = "Checks if the value of the field is `PWP`"] + #[inline(always)] + pub fn is_pwp(&self) -> bool { + **self == EVACT_A::PWP + } + #[doc = "Checks if the value of the field is `PW`"] + #[inline(always)] + pub fn is_pw(&self) -> bool { + **self == EVACT_A::PW + } +} +impl core::ops::Deref for EVACT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT` writer - Event Action"] +pub struct EVACT_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EVACT_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Event action disabled"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(EVACT_A::OFF) + } + #[doc = "Start, restart or retrigger TC on event"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(EVACT_A::RETRIGGER) + } + #[doc = "Count on event"] + #[inline(always)] + pub fn count(self) -> &'a mut W { + self.variant(EVACT_A::COUNT) + } + #[doc = "Start TC on event"] + #[inline(always)] + pub fn start(self) -> &'a mut W { + self.variant(EVACT_A::START) + } + #[doc = "Time stamp capture"] + #[inline(always)] + pub fn stamp(self) -> &'a mut W { + self.variant(EVACT_A::STAMP) + } + #[doc = "Period catured in CC0, pulse width in CC1"] + #[inline(always)] + pub fn ppw(self) -> &'a mut W { + self.variant(EVACT_A::PPW) + } + #[doc = "Period catured in CC1, pulse width in CC0"] + #[inline(always)] + pub fn pwp(self) -> &'a mut W { + self.variant(EVACT_A::PWP) + } + #[doc = "Pulse width capture"] + #[inline(always)] + pub fn pw(self) -> &'a mut W { + self.variant(EVACT_A::PW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u16 & 0x07); + self.w + } +} +#[doc = "Field `TCINV` reader - TC Event Input Polarity"] +pub struct TCINV_R(crate::FieldReader); +impl TCINV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCINV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCINV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCINV` writer - TC Event Input Polarity"] +pub struct TCINV_W<'a> { + w: &'a mut W, +} +impl<'a> TCINV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `TCEI` reader - TC Event Enable"] +pub struct TCEI_R(crate::FieldReader); +impl TCEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCEI` writer - TC Event Enable"] +pub struct TCEI_W<'a> { + w: &'a mut W, +} +impl<'a> TCEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `OVFEO` reader - Event Output Enable"] +pub struct OVFEO_R(crate::FieldReader); +impl OVFEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVFEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVFEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVFEO` writer - Event Output Enable"] +pub struct OVFEO_W<'a> { + w: &'a mut W, +} +impl<'a> OVFEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `MCEO0` reader - MC Event Output Enable 0"] +pub struct MCEO0_R(crate::FieldReader); +impl MCEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO0` writer - MC Event Output Enable 0"] +pub struct MCEO0_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u16 & 0x01) << 12); + self.w + } +} +#[doc = "Field `MCEO1` reader - MC Event Output Enable 1"] +pub struct MCEO1_R(crate::FieldReader); +impl MCEO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO1` writer - MC Event Output Enable 1"] +pub struct MCEO1_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u16 & 0x01) << 13); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Event Action"] + #[inline(always)] + pub fn evact(&self) -> EVACT_R { + EVACT_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 4 - TC Event Input Polarity"] + #[inline(always)] + pub fn tcinv(&self) -> TCINV_R { + TCINV_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - TC Event Enable"] + #[inline(always)] + pub fn tcei(&self) -> TCEI_R { + TCEI_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 8 - Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&self) -> OVFEO_R { + OVFEO_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 12 - MC Event Output Enable 0"] + #[inline(always)] + pub fn mceo0(&self) -> MCEO0_R { + MCEO0_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - MC Event Output Enable 1"] + #[inline(always)] + pub fn mceo1(&self) -> MCEO1_R { + MCEO1_R::new(((self.bits >> 13) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Event Action"] + #[inline(always)] + pub fn evact(&mut self) -> EVACT_W { + EVACT_W { w: self } + } + #[doc = "Bit 4 - TC Event Input Polarity"] + #[inline(always)] + pub fn tcinv(&mut self) -> TCINV_W { + TCINV_W { w: self } + } + #[doc = "Bit 5 - TC Event Enable"] + #[inline(always)] + pub fn tcei(&mut self) -> TCEI_W { + TCEI_W { w: self } + } + #[doc = "Bit 8 - Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&mut self) -> OVFEO_W { + OVFEO_W { w: self } + } + #[doc = "Bit 12 - MC Event Output Enable 0"] + #[inline(always)] + pub fn mceo0(&mut self) -> MCEO0_W { + MCEO0_W { w: self } + } + #[doc = "Bit 13 - MC Event Output Enable 1"] + #[inline(always)] + pub fn mceo1(&mut self) -> MCEO1_W { + MCEO1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/tc0/count16/intenclr.rs b/pac/atsamc20e/src/tc0/count16/intenclr.rs new file mode 100644 index 000000000000..af01ef5b7dca --- /dev/null +++ b/pac/atsamc20e/src/tc0/count16/intenclr.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - OVF Interrupt Disable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - OVF Interrupt Disable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - ERR Interrupt Disable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - ERR Interrupt Disable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MC0` reader - MC Interrupt Disable 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - MC Interrupt Disable 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - MC Interrupt Disable 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - MC Interrupt Disable 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - OVF Interrupt Disable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ERR Interrupt Disable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - MC Interrupt Disable 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - MC Interrupt Disable 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - OVF Interrupt Disable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - ERR Interrupt Disable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 4 - MC Interrupt Disable 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - MC Interrupt Disable 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/tc0/count16/intenset.rs b/pac/atsamc20e/src/tc0/count16/intenset.rs new file mode 100644 index 000000000000..0e1883a2f20a --- /dev/null +++ b/pac/atsamc20e/src/tc0/count16/intenset.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - OVF Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - OVF Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - ERR Interrupt Enable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - ERR Interrupt Enable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MC0` reader - MC Interrupt Enable 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - MC Interrupt Enable 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - MC Interrupt Enable 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - MC Interrupt Enable 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - OVF Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ERR Interrupt Enable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - MC Interrupt Enable 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - MC Interrupt Enable 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - OVF Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - ERR Interrupt Enable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 4 - MC Interrupt Enable 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - MC Interrupt Enable 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/tc0/count16/intflag.rs b/pac/atsamc20e/src/tc0/count16/intflag.rs new file mode 100644 index 000000000000..1dddffaf8e7f --- /dev/null +++ b/pac/atsamc20e/src/tc0/count16/intflag.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - OVF Interrupt Flag"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - OVF Interrupt Flag"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - ERR Interrupt Flag"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - ERR Interrupt Flag"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MC0` reader - MC Interrupt Flag 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - MC Interrupt Flag 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - MC Interrupt Flag 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - MC Interrupt Flag 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - OVF Interrupt Flag"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ERR Interrupt Flag"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - MC Interrupt Flag 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - MC Interrupt Flag 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - OVF Interrupt Flag"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - ERR Interrupt Flag"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 4 - MC Interrupt Flag 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - MC Interrupt Flag 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/tc0/count16/status.rs b/pac/atsamc20e/src/tc0/count16/status.rs new file mode 100644 index 000000000000..5088af446830 --- /dev/null +++ b/pac/atsamc20e/src/tc0/count16/status.rs @@ -0,0 +1,301 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `STOP` reader - Stop Status Flag"] +pub struct STOP_R(crate::FieldReader); +impl STOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STOP` writer - Stop Status Flag"] +pub struct STOP_W<'a> { + w: &'a mut W, +} +impl<'a> STOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SLAVE` reader - Slave Status Flag"] +pub struct SLAVE_R(crate::FieldReader); +impl SLAVE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLAVE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SLAVE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLAVE` writer - Slave Status Flag"] +pub struct SLAVE_W<'a> { + w: &'a mut W, +} +impl<'a> SLAVE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PERBUFV` reader - Synchronization Busy Status"] +pub struct PERBUFV_R(crate::FieldReader); +impl PERBUFV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PERBUFV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERBUFV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERBUFV` writer - Synchronization Busy Status"] +pub struct PERBUFV_W<'a> { + w: &'a mut W, +} +impl<'a> PERBUFV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CCBUFV0` reader - Compare channel buffer 0 valid"] +pub struct CCBUFV0_R(crate::FieldReader); +impl CCBUFV0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBUFV0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUFV0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUFV0` writer - Compare channel buffer 0 valid"] +pub struct CCBUFV0_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUFV0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `CCBUFV1` reader - Compare channel buffer 1 valid"] +pub struct CCBUFV1_R(crate::FieldReader); +impl CCBUFV1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBUFV1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUFV1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUFV1` writer - Compare channel buffer 1 valid"] +pub struct CCBUFV1_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUFV1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Stop Status Flag"] + #[inline(always)] + pub fn stop(&self) -> STOP_R { + STOP_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Slave Status Flag"] + #[inline(always)] + pub fn slave(&self) -> SLAVE_R { + SLAVE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 3 - Synchronization Busy Status"] + #[inline(always)] + pub fn perbufv(&self) -> PERBUFV_R { + PERBUFV_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Compare channel buffer 0 valid"] + #[inline(always)] + pub fn ccbufv0(&self) -> CCBUFV0_R { + CCBUFV0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Compare channel buffer 1 valid"] + #[inline(always)] + pub fn ccbufv1(&self) -> CCBUFV1_R { + CCBUFV1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Stop Status Flag"] + #[inline(always)] + pub fn stop(&mut self) -> STOP_W { + STOP_W { w: self } + } + #[doc = "Bit 1 - Slave Status Flag"] + #[inline(always)] + pub fn slave(&mut self) -> SLAVE_W { + SLAVE_W { w: self } + } + #[doc = "Bit 3 - Synchronization Busy Status"] + #[inline(always)] + pub fn perbufv(&mut self) -> PERBUFV_W { + PERBUFV_W { w: self } + } + #[doc = "Bit 4 - Compare channel buffer 0 valid"] + #[inline(always)] + pub fn ccbufv0(&mut self) -> CCBUFV0_W { + CCBUFV0_W { w: self } + } + #[doc = "Bit 5 - Compare channel buffer 1 valid"] + #[inline(always)] + pub fn ccbufv1(&mut self) -> CCBUFV1_W { + CCBUFV1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0x01"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pac/atsamc20e/src/tc0/count16/syncbusy.rs b/pac/atsamc20e/src/tc0/count16/syncbusy.rs new file mode 100644 index 000000000000..7ad8d91a84de --- /dev/null +++ b/pac/atsamc20e/src/tc0/count16/syncbusy.rs @@ -0,0 +1,193 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - swrst"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLB` reader - CTRLB"] +pub struct CTRLB_R(crate::FieldReader); +impl CTRLB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STATUS` reader - STATUS"] +pub struct STATUS_R(crate::FieldReader); +impl STATUS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STATUS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STATUS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` reader - Counter"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` reader - Period"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC0` reader - Compare Channel 0"] +pub struct CC0_R(crate::FieldReader); +impl CC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC1` reader - Compare Channel 1"] +pub struct CC1_R(crate::FieldReader); +impl CC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - swrst"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - CTRLB"] + #[inline(always)] + pub fn ctrlb(&self) -> CTRLB_R { + CTRLB_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - STATUS"] + #[inline(always)] + pub fn status(&self) -> STATUS_R { + STATUS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Counter"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Period"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Compare Channel 0"] + #[inline(always)] + pub fn cc0(&self) -> CC0_R { + CC0_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Compare Channel 1"] + #[inline(always)] + pub fn cc1(&self) -> CC1_R { + CC1_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +#[doc = "Synchronization Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/tc0/count16/wave.rs b/pac/atsamc20e/src/tc0/count16/wave.rs new file mode 100644 index 000000000000..46061b24b75d --- /dev/null +++ b/pac/atsamc20e/src/tc0/count16/wave.rs @@ -0,0 +1,178 @@ +#[doc = "Register `WAVE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WAVE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Waveform Generation Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WAVEGEN_A { + #[doc = "0: Normal frequency"] + NFRQ = 0, + #[doc = "1: Match frequency"] + MFRQ = 1, + #[doc = "2: Normal PWM"] + NPWM = 2, + #[doc = "3: Match PWM"] + MPWM = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WAVEGEN_A) -> Self { + variant as _ + } +} +#[doc = "Field `WAVEGEN` reader - Waveform Generation Mode"] +pub struct WAVEGEN_R(crate::FieldReader); +impl WAVEGEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WAVEGEN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> WAVEGEN_A { + match self.bits { + 0 => WAVEGEN_A::NFRQ, + 1 => WAVEGEN_A::MFRQ, + 2 => WAVEGEN_A::NPWM, + 3 => WAVEGEN_A::MPWM, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NFRQ`"] + #[inline(always)] + pub fn is_nfrq(&self) -> bool { + **self == WAVEGEN_A::NFRQ + } + #[doc = "Checks if the value of the field is `MFRQ`"] + #[inline(always)] + pub fn is_mfrq(&self) -> bool { + **self == WAVEGEN_A::MFRQ + } + #[doc = "Checks if the value of the field is `NPWM`"] + #[inline(always)] + pub fn is_npwm(&self) -> bool { + **self == WAVEGEN_A::NPWM + } + #[doc = "Checks if the value of the field is `MPWM`"] + #[inline(always)] + pub fn is_mpwm(&self) -> bool { + **self == WAVEGEN_A::MPWM + } +} +impl core::ops::Deref for WAVEGEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAVEGEN` writer - Waveform Generation Mode"] +pub struct WAVEGEN_W<'a> { + w: &'a mut W, +} +impl<'a> WAVEGEN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WAVEGEN_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Normal frequency"] + #[inline(always)] + pub fn nfrq(self) -> &'a mut W { + self.variant(WAVEGEN_A::NFRQ) + } + #[doc = "Match frequency"] + #[inline(always)] + pub fn mfrq(self) -> &'a mut W { + self.variant(WAVEGEN_A::MFRQ) + } + #[doc = "Normal PWM"] + #[inline(always)] + pub fn npwm(self) -> &'a mut W { + self.variant(WAVEGEN_A::NPWM) + } + #[doc = "Match PWM"] + #[inline(always)] + pub fn mpwm(self) -> &'a mut W { + self.variant(WAVEGEN_A::MPWM) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u8 & 0x03); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Waveform Generation Mode"] + #[inline(always)] + pub fn wavegen(&self) -> WAVEGEN_R { + WAVEGEN_R::new((self.bits & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Waveform Generation Mode"] + #[inline(always)] + pub fn wavegen(&mut self) -> WAVEGEN_W { + WAVEGEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Waveform Generation Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wave](index.html) module"] +pub struct WAVE_SPEC; +impl crate::RegisterSpec for WAVE_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [wave::R](R) reader structure"] +impl crate::Readable for WAVE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wave::W](W) writer structure"] +impl crate::Writable for WAVE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WAVE to value 0"] +impl crate::Resettable for WAVE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/tc0/count32.rs b/pac/atsamc20e/src/tc0/count32.rs new file mode 100644 index 000000000000..9062acfbbd7f --- /dev/null +++ b/pac/atsamc20e/src/tc0/count32.rs @@ -0,0 +1,60 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "CTRLBCLR register accessor: an alias for `Reg`"] +pub type CTRLBCLR = crate::Reg; +#[doc = "Control B Clear"] +pub mod ctrlbclr; +#[doc = "CTRLBSET register accessor: an alias for `Reg`"] +pub type CTRLBSET = crate::Reg; +#[doc = "Control B Set"] +pub mod ctrlbset; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "WAVE register accessor: an alias for `Reg`"] +pub type WAVE = crate::Reg; +#[doc = "Waveform Generation Control"] +pub mod wave; +#[doc = "DRVCTRL register accessor: an alias for `Reg`"] +pub type DRVCTRL = crate::Reg; +#[doc = "Control C"] +pub mod drvctrl; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Status"] +pub mod syncbusy; +#[doc = "COUNT register accessor: an alias for `Reg`"] +pub type COUNT = crate::Reg; +#[doc = "COUNT32 Count"] +pub mod count; +#[doc = "CC register accessor: an alias for `Reg`"] +pub type CC = crate::Reg; +#[doc = "COUNT32 Compare and Capture"] +pub mod cc; +#[doc = "CCBUF register accessor: an alias for `Reg`"] +pub type CCBUF = crate::Reg; +#[doc = "COUNT32 Compare and Capture Buffer"] +pub mod ccbuf; diff --git a/pac/atsamc20e/src/tc0/count32/cc.rs b/pac/atsamc20e/src/tc0/count32/cc.rs new file mode 100644 index 000000000000..512a1e01ffd4 --- /dev/null +++ b/pac/atsamc20e/src/tc0/count32/cc.rs @@ -0,0 +1,104 @@ +#[doc = "Register `CC[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CC[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CC` reader - Counter/Compare Value"] +pub struct CC_R(crate::FieldReader); +impl CC_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC` writer - Counter/Compare Value"] +pub struct CC_W<'a> { + w: &'a mut W, +} +impl<'a> CC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Counter/Compare Value"] + #[inline(always)] + pub fn cc(&self) -> CC_R { + CC_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Counter/Compare Value"] + #[inline(always)] + pub fn cc(&mut self) -> CC_W { + CC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT32 Compare and Capture\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc](index.html) module"] +pub struct CC_SPEC; +impl crate::RegisterSpec for CC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cc::R](R) reader structure"] +impl crate::Readable for CC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cc::W](W) writer structure"] +impl crate::Writable for CC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CC[%s] +to value 0"] +impl crate::Resettable for CC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/tc0/count32/ccbuf.rs b/pac/atsamc20e/src/tc0/count32/ccbuf.rs new file mode 100644 index 000000000000..9fb2d9f8f66c --- /dev/null +++ b/pac/atsamc20e/src/tc0/count32/ccbuf.rs @@ -0,0 +1,104 @@ +#[doc = "Register `CCBUF[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CCBUF[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CCBUF` reader - Counter/Compare Buffer Value"] +pub struct CCBUF_R(crate::FieldReader); +impl CCBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CCBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUF` writer - Counter/Compare Buffer Value"] +pub struct CCBUF_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Counter/Compare Buffer Value"] + #[inline(always)] + pub fn ccbuf(&self) -> CCBUF_R { + CCBUF_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Counter/Compare Buffer Value"] + #[inline(always)] + pub fn ccbuf(&mut self) -> CCBUF_W { + CCBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT32 Compare and Capture Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccbuf](index.html) module"] +pub struct CCBUF_SPEC; +impl crate::RegisterSpec for CCBUF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ccbuf::R](R) reader structure"] +impl crate::Readable for CCBUF_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ccbuf::W](W) writer structure"] +impl crate::Writable for CCBUF_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CCBUF[%s] +to value 0"] +impl crate::Resettable for CCBUF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/tc0/count32/count.rs b/pac/atsamc20e/src/tc0/count32/count.rs new file mode 100644 index 000000000000..9aea527a8b3c --- /dev/null +++ b/pac/atsamc20e/src/tc0/count32/count.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT32 Count\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count](index.html) module"] +pub struct COUNT_SPEC; +impl crate::RegisterSpec for COUNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [count::R](R) reader structure"] +impl crate::Readable for COUNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count::W](W) writer structure"] +impl crate::Writable for COUNT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT to value 0"] +impl crate::Resettable for COUNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/tc0/count32/ctrla.rs b/pac/atsamc20e/src/tc0/count32/ctrla.rs new file mode 100644 index 000000000000..cadcddaaead8 --- /dev/null +++ b/pac/atsamc20e/src/tc0/count32/ctrla.rs @@ -0,0 +1,851 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Timer Counter Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: Counter in 16-bit mode"] + COUNT16 = 0, + #[doc = "1: Counter in 8-bit mode"] + COUNT8 = 1, + #[doc = "2: Counter in 32-bit mode"] + COUNT32 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Timer Counter Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::COUNT16), + 1 => Some(MODE_A::COUNT8), + 2 => Some(MODE_A::COUNT32), + _ => None, + } + } + #[doc = "Checks if the value of the field is `COUNT16`"] + #[inline(always)] + pub fn is_count16(&self) -> bool { + **self == MODE_A::COUNT16 + } + #[doc = "Checks if the value of the field is `COUNT8`"] + #[inline(always)] + pub fn is_count8(&self) -> bool { + **self == MODE_A::COUNT8 + } + #[doc = "Checks if the value of the field is `COUNT32`"] + #[inline(always)] + pub fn is_count32(&self) -> bool { + **self == MODE_A::COUNT32 + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Timer Counter Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Counter in 16-bit mode"] + #[inline(always)] + pub fn count16(self) -> &'a mut W { + self.variant(MODE_A::COUNT16) + } + #[doc = "Counter in 8-bit mode"] + #[inline(always)] + pub fn count8(self) -> &'a mut W { + self.variant(MODE_A::COUNT8) + } + #[doc = "Counter in 32-bit mode"] + #[inline(always)] + pub fn count32(self) -> &'a mut W { + self.variant(MODE_A::COUNT32) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u32 & 0x03) << 2); + self.w + } +} +#[doc = "Prescaler and Counter Synchronization\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCSYNC_A { + #[doc = "0: Reload or reset the counter on next generic clock"] + GCLK = 0, + #[doc = "1: Reload or reset the counter on next prescaler clock"] + PRESC = 1, + #[doc = "2: Reload or reset the counter on next generic clock and reset the prescaler counter"] + RESYNC = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCSYNC_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCSYNC` reader - Prescaler and Counter Synchronization"] +pub struct PRESCSYNC_R(crate::FieldReader); +impl PRESCSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCSYNC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCSYNC_A::GCLK), + 1 => Some(PRESCSYNC_A::PRESC), + 2 => Some(PRESCSYNC_A::RESYNC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `GCLK`"] + #[inline(always)] + pub fn is_gclk(&self) -> bool { + **self == PRESCSYNC_A::GCLK + } + #[doc = "Checks if the value of the field is `PRESC`"] + #[inline(always)] + pub fn is_presc(&self) -> bool { + **self == PRESCSYNC_A::PRESC + } + #[doc = "Checks if the value of the field is `RESYNC`"] + #[inline(always)] + pub fn is_resync(&self) -> bool { + **self == PRESCSYNC_A::RESYNC + } +} +impl core::ops::Deref for PRESCSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCSYNC` writer - Prescaler and Counter Synchronization"] +pub struct PRESCSYNC_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCSYNC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCSYNC_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Reload or reset the counter on next generic clock"] + #[inline(always)] + pub fn gclk(self) -> &'a mut W { + self.variant(PRESCSYNC_A::GCLK) + } + #[doc = "Reload or reset the counter on next prescaler clock"] + #[inline(always)] + pub fn presc(self) -> &'a mut W { + self.variant(PRESCSYNC_A::PRESC) + } + #[doc = "Reload or reset the counter on next generic clock and reset the prescaler counter"] + #[inline(always)] + pub fn resync(self) -> &'a mut W { + self.variant(PRESCSYNC_A::RESYNC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u32 & 0x03) << 4); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - Clock On Demand"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - Clock On Demand"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: Prescaler: GCLK_TC"] + DIV1 = 0, + #[doc = "1: Prescaler: GCLK_TC/2"] + DIV2 = 1, + #[doc = "2: Prescaler: GCLK_TC/4"] + DIV4 = 2, + #[doc = "3: Prescaler: GCLK_TC/8"] + DIV8 = 3, + #[doc = "4: Prescaler: GCLK_TC/16"] + DIV16 = 4, + #[doc = "5: Prescaler: GCLK_TC/64"] + DIV64 = 5, + #[doc = "6: Prescaler: GCLK_TC/256"] + DIV256 = 6, + #[doc = "7: Prescaler: GCLK_TC/1024"] + DIV1024 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PRESCALER_A { + match self.bits { + 0 => PRESCALER_A::DIV1, + 1 => PRESCALER_A::DIV2, + 2 => PRESCALER_A::DIV4, + 3 => PRESCALER_A::DIV8, + 4 => PRESCALER_A::DIV16, + 5 => PRESCALER_A::DIV64, + 6 => PRESCALER_A::DIV256, + 7 => PRESCALER_A::DIV1024, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == PRESCALER_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PRESCALER_A::DIV1024 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Prescaler: GCLK_TC"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1) + } + #[doc = "Prescaler: GCLK_TC/2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "Prescaler: GCLK_TC/4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "Prescaler: GCLK_TC/8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "Prescaler: GCLK_TC/16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "Prescaler: GCLK_TC/64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "Prescaler: GCLK_TC/256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = "Prescaler: GCLK_TC/1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +#[doc = "Field `ALOCK` reader - Auto Lock"] +pub struct ALOCK_R(crate::FieldReader); +impl ALOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALOCK` writer - Auto Lock"] +pub struct ALOCK_W<'a> { + w: &'a mut W, +} +impl<'a> ALOCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `CAPTEN0` reader - Capture Channel 0 Enable"] +pub struct CAPTEN0_R(crate::FieldReader); +impl CAPTEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CAPTEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CAPTEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAPTEN0` writer - Capture Channel 0 Enable"] +pub struct CAPTEN0_W<'a> { + w: &'a mut W, +} +impl<'a> CAPTEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `CAPTEN1` reader - Capture Channel 1 Enable"] +pub struct CAPTEN1_R(crate::FieldReader); +impl CAPTEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CAPTEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CAPTEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAPTEN1` writer - Capture Channel 1 Enable"] +pub struct CAPTEN1_W<'a> { + w: &'a mut W, +} +impl<'a> CAPTEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `COPEN0` reader - Capture On Pin 0 Enable"] +pub struct COPEN0_R(crate::FieldReader); +impl COPEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COPEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COPEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COPEN0` writer - Capture On Pin 0 Enable"] +pub struct COPEN0_W<'a> { + w: &'a mut W, +} +impl<'a> COPEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `COPEN1` reader - Capture On Pin 1 Enable"] +pub struct COPEN1_R(crate::FieldReader); +impl COPEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COPEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COPEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COPEN1` writer - Capture On Pin 1 Enable"] +pub struct COPEN1_W<'a> { + w: &'a mut W, +} +impl<'a> COPEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:3 - Timer Counter Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bits 4:5 - Prescaler and Counter Synchronization"] + #[inline(always)] + pub fn prescsync(&self) -> PRESCSYNC_R { + PRESCSYNC_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Clock On Demand"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 11 - Auto Lock"] + #[inline(always)] + pub fn alock(&self) -> ALOCK_R { + ALOCK_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 16 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn capten0(&self) -> CAPTEN0_R { + CAPTEN0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn capten1(&self) -> CAPTEN1_R { + CAPTEN1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 20 - Capture On Pin 0 Enable"] + #[inline(always)] + pub fn copen0(&self) -> COPEN0_R { + COPEN0_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Capture On Pin 1 Enable"] + #[inline(always)] + pub fn copen1(&self) -> COPEN1_R { + COPEN1_R::new(((self.bits >> 21) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:3 - Timer Counter Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bits 4:5 - Prescaler and Counter Synchronization"] + #[inline(always)] + pub fn prescsync(&mut self) -> PRESCSYNC_W { + PRESCSYNC_W { w: self } + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - Clock On Demand"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Bit 11 - Auto Lock"] + #[inline(always)] + pub fn alock(&mut self) -> ALOCK_W { + ALOCK_W { w: self } + } + #[doc = "Bit 16 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn capten0(&mut self) -> CAPTEN0_W { + CAPTEN0_W { w: self } + } + #[doc = "Bit 17 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn capten1(&mut self) -> CAPTEN1_W { + CAPTEN1_W { w: self } + } + #[doc = "Bit 20 - Capture On Pin 0 Enable"] + #[inline(always)] + pub fn copen0(&mut self) -> COPEN0_W { + COPEN0_W { w: self } + } + #[doc = "Bit 21 - Capture On Pin 1 Enable"] + #[inline(always)] + pub fn copen1(&mut self) -> COPEN1_W { + COPEN1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/tc0/count32/ctrlbclr.rs b/pac/atsamc20e/src/tc0/count32/ctrlbclr.rs new file mode 100644 index 000000000000..76265674036a --- /dev/null +++ b/pac/atsamc20e/src/tc0/count32/ctrlbclr.rs @@ -0,0 +1,345 @@ +#[doc = "Register `CTRLBCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Counter Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `LUPD` reader - Lock Update"] +pub struct LUPD_R(crate::FieldReader); +impl LUPD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LUPD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LUPD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LUPD` writer - Lock Update"] +pub struct LUPD_W<'a> { + w: &'a mut W, +} +impl<'a> LUPD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ONESHOT` reader - One-Shot on Counter"] +pub struct ONESHOT_R(crate::FieldReader); +impl ONESHOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONESHOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONESHOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONESHOT` writer - One-Shot on Counter"] +pub struct ONESHOT_W<'a> { + w: &'a mut W, +} +impl<'a> ONESHOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Force a start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force a stop"] + STOP = 2, + #[doc = "3: Force update of double-buffered register"] + UPDATE = 3, + #[doc = "4: Force a read synchronization of COUNT"] + READSYNC = 4, + #[doc = "5: One-shot DMA trigger"] + DMAOS = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NONE), + 1 => Some(CMD_A::RETRIGGER), + 2 => Some(CMD_A::STOP), + 3 => Some(CMD_A::UPDATE), + 4 => Some(CMD_A::READSYNC), + 5 => Some(CMD_A::DMAOS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == CMD_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == CMD_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == CMD_A::STOP + } + #[doc = "Checks if the value of the field is `UPDATE`"] + #[inline(always)] + pub fn is_update(&self) -> bool { + **self == CMD_A::UPDATE + } + #[doc = "Checks if the value of the field is `READSYNC`"] + #[inline(always)] + pub fn is_readsync(&self) -> bool { + **self == CMD_A::READSYNC + } + #[doc = "Checks if the value of the field is `DMAOS`"] + #[inline(always)] + pub fn is_dmaos(&self) -> bool { + **self == CMD_A::DMAOS + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMD_A::NONE) + } + #[doc = "Force a start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMD_A::RETRIGGER) + } + #[doc = "Force a stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMD_A::STOP) + } + #[doc = "Force update of double-buffered register"] + #[inline(always)] + pub fn update(self) -> &'a mut W { + self.variant(CMD_A::UPDATE) + } + #[doc = "Force a read synchronization of COUNT"] + #[inline(always)] + pub fn readsync(self) -> &'a mut W { + self.variant(CMD_A::READSYNC) + } + #[doc = "One-shot DMA trigger"] + #[inline(always)] + pub fn dmaos(self) -> &'a mut W { + self.variant(CMD_A::DMAOS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 5)) | ((value as u8 & 0x07) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&self) -> LUPD_R { + LUPD_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 5) & 0x07) as u8) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&mut self) -> LUPD_W { + LUPD_W { w: self } + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&mut self) -> ONESHOT_W { + ONESHOT_W { w: self } + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbclr](index.html) module"] +pub struct CTRLBCLR_SPEC; +impl crate::RegisterSpec for CTRLBCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbclr::R](R) reader structure"] +impl crate::Readable for CTRLBCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbclr::W](W) writer structure"] +impl crate::Writable for CTRLBCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLBCLR to value 0"] +impl crate::Resettable for CTRLBCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/tc0/count32/ctrlbset.rs b/pac/atsamc20e/src/tc0/count32/ctrlbset.rs new file mode 100644 index 000000000000..610914c9c7c8 --- /dev/null +++ b/pac/atsamc20e/src/tc0/count32/ctrlbset.rs @@ -0,0 +1,345 @@ +#[doc = "Register `CTRLBSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Counter Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `LUPD` reader - Lock Update"] +pub struct LUPD_R(crate::FieldReader); +impl LUPD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LUPD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LUPD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LUPD` writer - Lock Update"] +pub struct LUPD_W<'a> { + w: &'a mut W, +} +impl<'a> LUPD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ONESHOT` reader - One-Shot on Counter"] +pub struct ONESHOT_R(crate::FieldReader); +impl ONESHOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONESHOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONESHOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONESHOT` writer - One-Shot on Counter"] +pub struct ONESHOT_W<'a> { + w: &'a mut W, +} +impl<'a> ONESHOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Force a start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force a stop"] + STOP = 2, + #[doc = "3: Force update of double-buffered register"] + UPDATE = 3, + #[doc = "4: Force a read synchronization of COUNT"] + READSYNC = 4, + #[doc = "5: One-shot DMA trigger"] + DMAOS = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NONE), + 1 => Some(CMD_A::RETRIGGER), + 2 => Some(CMD_A::STOP), + 3 => Some(CMD_A::UPDATE), + 4 => Some(CMD_A::READSYNC), + 5 => Some(CMD_A::DMAOS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == CMD_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == CMD_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == CMD_A::STOP + } + #[doc = "Checks if the value of the field is `UPDATE`"] + #[inline(always)] + pub fn is_update(&self) -> bool { + **self == CMD_A::UPDATE + } + #[doc = "Checks if the value of the field is `READSYNC`"] + #[inline(always)] + pub fn is_readsync(&self) -> bool { + **self == CMD_A::READSYNC + } + #[doc = "Checks if the value of the field is `DMAOS`"] + #[inline(always)] + pub fn is_dmaos(&self) -> bool { + **self == CMD_A::DMAOS + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMD_A::NONE) + } + #[doc = "Force a start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMD_A::RETRIGGER) + } + #[doc = "Force a stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMD_A::STOP) + } + #[doc = "Force update of double-buffered register"] + #[inline(always)] + pub fn update(self) -> &'a mut W { + self.variant(CMD_A::UPDATE) + } + #[doc = "Force a read synchronization of COUNT"] + #[inline(always)] + pub fn readsync(self) -> &'a mut W { + self.variant(CMD_A::READSYNC) + } + #[doc = "One-shot DMA trigger"] + #[inline(always)] + pub fn dmaos(self) -> &'a mut W { + self.variant(CMD_A::DMAOS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 5)) | ((value as u8 & 0x07) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&self) -> LUPD_R { + LUPD_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 5) & 0x07) as u8) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&mut self) -> LUPD_W { + LUPD_W { w: self } + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&mut self) -> ONESHOT_W { + ONESHOT_W { w: self } + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbset](index.html) module"] +pub struct CTRLBSET_SPEC; +impl crate::RegisterSpec for CTRLBSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbset::R](R) reader structure"] +impl crate::Readable for CTRLBSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbset::W](W) writer structure"] +impl crate::Writable for CTRLBSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLBSET to value 0"] +impl crate::Resettable for CTRLBSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/tc0/count32/dbgctrl.rs b/pac/atsamc20e/src/tc0/count32/dbgctrl.rs new file mode 100644 index 000000000000..0383e70d0429 --- /dev/null +++ b/pac/atsamc20e/src/tc0/count32/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Run During Debug"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Run During Debug"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/tc0/count32/drvctrl.rs b/pac/atsamc20e/src/tc0/count32/drvctrl.rs new file mode 100644 index 000000000000..323926b4b22d --- /dev/null +++ b/pac/atsamc20e/src/tc0/count32/drvctrl.rs @@ -0,0 +1,160 @@ +#[doc = "Register `DRVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DRVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INVEN0` reader - Output Waveform Invert Enable 0"] +pub struct INVEN0_R(crate::FieldReader); +impl INVEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN0` writer - Output Waveform Invert Enable 0"] +pub struct INVEN0_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `INVEN1` reader - Output Waveform Invert Enable 1"] +pub struct INVEN1_R(crate::FieldReader); +impl INVEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN1` writer - Output Waveform Invert Enable 1"] +pub struct INVEN1_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - Output Waveform Invert Enable 0"] + #[inline(always)] + pub fn inven0(&self) -> INVEN0_R { + INVEN0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Output Waveform Invert Enable 1"] + #[inline(always)] + pub fn inven1(&self) -> INVEN1_R { + INVEN1_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Output Waveform Invert Enable 0"] + #[inline(always)] + pub fn inven0(&mut self) -> INVEN0_W { + INVEN0_W { w: self } + } + #[doc = "Bit 1 - Output Waveform Invert Enable 1"] + #[inline(always)] + pub fn inven1(&mut self) -> INVEN1_W { + INVEN1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control C\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [drvctrl](index.html) module"] +pub struct DRVCTRL_SPEC; +impl crate::RegisterSpec for DRVCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [drvctrl::R](R) reader structure"] +impl crate::Readable for DRVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [drvctrl::W](W) writer structure"] +impl crate::Writable for DRVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DRVCTRL to value 0"] +impl crate::Resettable for DRVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/tc0/count32/evctrl.rs b/pac/atsamc20e/src/tc0/count32/evctrl.rs new file mode 100644 index 000000000000..7d4c38d486c1 --- /dev/null +++ b/pac/atsamc20e/src/tc0/count32/evctrl.rs @@ -0,0 +1,465 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Event Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EVACT_A { + #[doc = "0: Event action disabled"] + OFF = 0, + #[doc = "1: Start, restart or retrigger TC on event"] + RETRIGGER = 1, + #[doc = "2: Count on event"] + COUNT = 2, + #[doc = "3: Start TC on event"] + START = 3, + #[doc = "4: Time stamp capture"] + STAMP = 4, + #[doc = "5: Period catured in CC0, pulse width in CC1"] + PPW = 5, + #[doc = "6: Period catured in CC1, pulse width in CC0"] + PWP = 6, + #[doc = "7: Pulse width capture"] + PW = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EVACT_A) -> Self { + variant as _ + } +} +#[doc = "Field `EVACT` reader - Event Action"] +pub struct EVACT_R(crate::FieldReader); +impl EVACT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVACT_A { + match self.bits { + 0 => EVACT_A::OFF, + 1 => EVACT_A::RETRIGGER, + 2 => EVACT_A::COUNT, + 3 => EVACT_A::START, + 4 => EVACT_A::STAMP, + 5 => EVACT_A::PPW, + 6 => EVACT_A::PWP, + 7 => EVACT_A::PW, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == EVACT_A::OFF + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == EVACT_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `COUNT`"] + #[inline(always)] + pub fn is_count(&self) -> bool { + **self == EVACT_A::COUNT + } + #[doc = "Checks if the value of the field is `START`"] + #[inline(always)] + pub fn is_start(&self) -> bool { + **self == EVACT_A::START + } + #[doc = "Checks if the value of the field is `STAMP`"] + #[inline(always)] + pub fn is_stamp(&self) -> bool { + **self == EVACT_A::STAMP + } + #[doc = "Checks if the value of the field is `PPW`"] + #[inline(always)] + pub fn is_ppw(&self) -> bool { + **self == EVACT_A::PPW + } + #[doc = "Checks if the value of the field is `PWP`"] + #[inline(always)] + pub fn is_pwp(&self) -> bool { + **self == EVACT_A::PWP + } + #[doc = "Checks if the value of the field is `PW`"] + #[inline(always)] + pub fn is_pw(&self) -> bool { + **self == EVACT_A::PW + } +} +impl core::ops::Deref for EVACT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT` writer - Event Action"] +pub struct EVACT_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EVACT_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Event action disabled"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(EVACT_A::OFF) + } + #[doc = "Start, restart or retrigger TC on event"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(EVACT_A::RETRIGGER) + } + #[doc = "Count on event"] + #[inline(always)] + pub fn count(self) -> &'a mut W { + self.variant(EVACT_A::COUNT) + } + #[doc = "Start TC on event"] + #[inline(always)] + pub fn start(self) -> &'a mut W { + self.variant(EVACT_A::START) + } + #[doc = "Time stamp capture"] + #[inline(always)] + pub fn stamp(self) -> &'a mut W { + self.variant(EVACT_A::STAMP) + } + #[doc = "Period catured in CC0, pulse width in CC1"] + #[inline(always)] + pub fn ppw(self) -> &'a mut W { + self.variant(EVACT_A::PPW) + } + #[doc = "Period catured in CC1, pulse width in CC0"] + #[inline(always)] + pub fn pwp(self) -> &'a mut W { + self.variant(EVACT_A::PWP) + } + #[doc = "Pulse width capture"] + #[inline(always)] + pub fn pw(self) -> &'a mut W { + self.variant(EVACT_A::PW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u16 & 0x07); + self.w + } +} +#[doc = "Field `TCINV` reader - TC Event Input Polarity"] +pub struct TCINV_R(crate::FieldReader); +impl TCINV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCINV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCINV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCINV` writer - TC Event Input Polarity"] +pub struct TCINV_W<'a> { + w: &'a mut W, +} +impl<'a> TCINV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `TCEI` reader - TC Event Enable"] +pub struct TCEI_R(crate::FieldReader); +impl TCEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCEI` writer - TC Event Enable"] +pub struct TCEI_W<'a> { + w: &'a mut W, +} +impl<'a> TCEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `OVFEO` reader - Event Output Enable"] +pub struct OVFEO_R(crate::FieldReader); +impl OVFEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVFEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVFEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVFEO` writer - Event Output Enable"] +pub struct OVFEO_W<'a> { + w: &'a mut W, +} +impl<'a> OVFEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `MCEO0` reader - MC Event Output Enable 0"] +pub struct MCEO0_R(crate::FieldReader); +impl MCEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO0` writer - MC Event Output Enable 0"] +pub struct MCEO0_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u16 & 0x01) << 12); + self.w + } +} +#[doc = "Field `MCEO1` reader - MC Event Output Enable 1"] +pub struct MCEO1_R(crate::FieldReader); +impl MCEO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO1` writer - MC Event Output Enable 1"] +pub struct MCEO1_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u16 & 0x01) << 13); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Event Action"] + #[inline(always)] + pub fn evact(&self) -> EVACT_R { + EVACT_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 4 - TC Event Input Polarity"] + #[inline(always)] + pub fn tcinv(&self) -> TCINV_R { + TCINV_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - TC Event Enable"] + #[inline(always)] + pub fn tcei(&self) -> TCEI_R { + TCEI_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 8 - Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&self) -> OVFEO_R { + OVFEO_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 12 - MC Event Output Enable 0"] + #[inline(always)] + pub fn mceo0(&self) -> MCEO0_R { + MCEO0_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - MC Event Output Enable 1"] + #[inline(always)] + pub fn mceo1(&self) -> MCEO1_R { + MCEO1_R::new(((self.bits >> 13) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Event Action"] + #[inline(always)] + pub fn evact(&mut self) -> EVACT_W { + EVACT_W { w: self } + } + #[doc = "Bit 4 - TC Event Input Polarity"] + #[inline(always)] + pub fn tcinv(&mut self) -> TCINV_W { + TCINV_W { w: self } + } + #[doc = "Bit 5 - TC Event Enable"] + #[inline(always)] + pub fn tcei(&mut self) -> TCEI_W { + TCEI_W { w: self } + } + #[doc = "Bit 8 - Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&mut self) -> OVFEO_W { + OVFEO_W { w: self } + } + #[doc = "Bit 12 - MC Event Output Enable 0"] + #[inline(always)] + pub fn mceo0(&mut self) -> MCEO0_W { + MCEO0_W { w: self } + } + #[doc = "Bit 13 - MC Event Output Enable 1"] + #[inline(always)] + pub fn mceo1(&mut self) -> MCEO1_W { + MCEO1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/tc0/count32/intenclr.rs b/pac/atsamc20e/src/tc0/count32/intenclr.rs new file mode 100644 index 000000000000..af01ef5b7dca --- /dev/null +++ b/pac/atsamc20e/src/tc0/count32/intenclr.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - OVF Interrupt Disable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - OVF Interrupt Disable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - ERR Interrupt Disable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - ERR Interrupt Disable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MC0` reader - MC Interrupt Disable 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - MC Interrupt Disable 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - MC Interrupt Disable 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - MC Interrupt Disable 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - OVF Interrupt Disable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ERR Interrupt Disable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - MC Interrupt Disable 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - MC Interrupt Disable 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - OVF Interrupt Disable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - ERR Interrupt Disable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 4 - MC Interrupt Disable 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - MC Interrupt Disable 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/tc0/count32/intenset.rs b/pac/atsamc20e/src/tc0/count32/intenset.rs new file mode 100644 index 000000000000..0e1883a2f20a --- /dev/null +++ b/pac/atsamc20e/src/tc0/count32/intenset.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - OVF Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - OVF Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - ERR Interrupt Enable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - ERR Interrupt Enable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MC0` reader - MC Interrupt Enable 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - MC Interrupt Enable 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - MC Interrupt Enable 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - MC Interrupt Enable 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - OVF Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ERR Interrupt Enable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - MC Interrupt Enable 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - MC Interrupt Enable 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - OVF Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - ERR Interrupt Enable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 4 - MC Interrupt Enable 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - MC Interrupt Enable 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/tc0/count32/intflag.rs b/pac/atsamc20e/src/tc0/count32/intflag.rs new file mode 100644 index 000000000000..1dddffaf8e7f --- /dev/null +++ b/pac/atsamc20e/src/tc0/count32/intflag.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - OVF Interrupt Flag"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - OVF Interrupt Flag"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - ERR Interrupt Flag"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - ERR Interrupt Flag"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MC0` reader - MC Interrupt Flag 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - MC Interrupt Flag 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - MC Interrupt Flag 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - MC Interrupt Flag 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - OVF Interrupt Flag"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ERR Interrupt Flag"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - MC Interrupt Flag 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - MC Interrupt Flag 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - OVF Interrupt Flag"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - ERR Interrupt Flag"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 4 - MC Interrupt Flag 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - MC Interrupt Flag 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/tc0/count32/status.rs b/pac/atsamc20e/src/tc0/count32/status.rs new file mode 100644 index 000000000000..5088af446830 --- /dev/null +++ b/pac/atsamc20e/src/tc0/count32/status.rs @@ -0,0 +1,301 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `STOP` reader - Stop Status Flag"] +pub struct STOP_R(crate::FieldReader); +impl STOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STOP` writer - Stop Status Flag"] +pub struct STOP_W<'a> { + w: &'a mut W, +} +impl<'a> STOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SLAVE` reader - Slave Status Flag"] +pub struct SLAVE_R(crate::FieldReader); +impl SLAVE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLAVE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SLAVE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLAVE` writer - Slave Status Flag"] +pub struct SLAVE_W<'a> { + w: &'a mut W, +} +impl<'a> SLAVE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PERBUFV` reader - Synchronization Busy Status"] +pub struct PERBUFV_R(crate::FieldReader); +impl PERBUFV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PERBUFV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERBUFV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERBUFV` writer - Synchronization Busy Status"] +pub struct PERBUFV_W<'a> { + w: &'a mut W, +} +impl<'a> PERBUFV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CCBUFV0` reader - Compare channel buffer 0 valid"] +pub struct CCBUFV0_R(crate::FieldReader); +impl CCBUFV0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBUFV0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUFV0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUFV0` writer - Compare channel buffer 0 valid"] +pub struct CCBUFV0_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUFV0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `CCBUFV1` reader - Compare channel buffer 1 valid"] +pub struct CCBUFV1_R(crate::FieldReader); +impl CCBUFV1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBUFV1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUFV1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUFV1` writer - Compare channel buffer 1 valid"] +pub struct CCBUFV1_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUFV1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Stop Status Flag"] + #[inline(always)] + pub fn stop(&self) -> STOP_R { + STOP_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Slave Status Flag"] + #[inline(always)] + pub fn slave(&self) -> SLAVE_R { + SLAVE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 3 - Synchronization Busy Status"] + #[inline(always)] + pub fn perbufv(&self) -> PERBUFV_R { + PERBUFV_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Compare channel buffer 0 valid"] + #[inline(always)] + pub fn ccbufv0(&self) -> CCBUFV0_R { + CCBUFV0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Compare channel buffer 1 valid"] + #[inline(always)] + pub fn ccbufv1(&self) -> CCBUFV1_R { + CCBUFV1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Stop Status Flag"] + #[inline(always)] + pub fn stop(&mut self) -> STOP_W { + STOP_W { w: self } + } + #[doc = "Bit 1 - Slave Status Flag"] + #[inline(always)] + pub fn slave(&mut self) -> SLAVE_W { + SLAVE_W { w: self } + } + #[doc = "Bit 3 - Synchronization Busy Status"] + #[inline(always)] + pub fn perbufv(&mut self) -> PERBUFV_W { + PERBUFV_W { w: self } + } + #[doc = "Bit 4 - Compare channel buffer 0 valid"] + #[inline(always)] + pub fn ccbufv0(&mut self) -> CCBUFV0_W { + CCBUFV0_W { w: self } + } + #[doc = "Bit 5 - Compare channel buffer 1 valid"] + #[inline(always)] + pub fn ccbufv1(&mut self) -> CCBUFV1_W { + CCBUFV1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0x01"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pac/atsamc20e/src/tc0/count32/syncbusy.rs b/pac/atsamc20e/src/tc0/count32/syncbusy.rs new file mode 100644 index 000000000000..7ad8d91a84de --- /dev/null +++ b/pac/atsamc20e/src/tc0/count32/syncbusy.rs @@ -0,0 +1,193 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - swrst"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLB` reader - CTRLB"] +pub struct CTRLB_R(crate::FieldReader); +impl CTRLB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STATUS` reader - STATUS"] +pub struct STATUS_R(crate::FieldReader); +impl STATUS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STATUS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STATUS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` reader - Counter"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` reader - Period"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC0` reader - Compare Channel 0"] +pub struct CC0_R(crate::FieldReader); +impl CC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC1` reader - Compare Channel 1"] +pub struct CC1_R(crate::FieldReader); +impl CC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - swrst"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - CTRLB"] + #[inline(always)] + pub fn ctrlb(&self) -> CTRLB_R { + CTRLB_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - STATUS"] + #[inline(always)] + pub fn status(&self) -> STATUS_R { + STATUS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Counter"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Period"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Compare Channel 0"] + #[inline(always)] + pub fn cc0(&self) -> CC0_R { + CC0_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Compare Channel 1"] + #[inline(always)] + pub fn cc1(&self) -> CC1_R { + CC1_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +#[doc = "Synchronization Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/tc0/count32/wave.rs b/pac/atsamc20e/src/tc0/count32/wave.rs new file mode 100644 index 000000000000..46061b24b75d --- /dev/null +++ b/pac/atsamc20e/src/tc0/count32/wave.rs @@ -0,0 +1,178 @@ +#[doc = "Register `WAVE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WAVE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Waveform Generation Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WAVEGEN_A { + #[doc = "0: Normal frequency"] + NFRQ = 0, + #[doc = "1: Match frequency"] + MFRQ = 1, + #[doc = "2: Normal PWM"] + NPWM = 2, + #[doc = "3: Match PWM"] + MPWM = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WAVEGEN_A) -> Self { + variant as _ + } +} +#[doc = "Field `WAVEGEN` reader - Waveform Generation Mode"] +pub struct WAVEGEN_R(crate::FieldReader); +impl WAVEGEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WAVEGEN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> WAVEGEN_A { + match self.bits { + 0 => WAVEGEN_A::NFRQ, + 1 => WAVEGEN_A::MFRQ, + 2 => WAVEGEN_A::NPWM, + 3 => WAVEGEN_A::MPWM, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NFRQ`"] + #[inline(always)] + pub fn is_nfrq(&self) -> bool { + **self == WAVEGEN_A::NFRQ + } + #[doc = "Checks if the value of the field is `MFRQ`"] + #[inline(always)] + pub fn is_mfrq(&self) -> bool { + **self == WAVEGEN_A::MFRQ + } + #[doc = "Checks if the value of the field is `NPWM`"] + #[inline(always)] + pub fn is_npwm(&self) -> bool { + **self == WAVEGEN_A::NPWM + } + #[doc = "Checks if the value of the field is `MPWM`"] + #[inline(always)] + pub fn is_mpwm(&self) -> bool { + **self == WAVEGEN_A::MPWM + } +} +impl core::ops::Deref for WAVEGEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAVEGEN` writer - Waveform Generation Mode"] +pub struct WAVEGEN_W<'a> { + w: &'a mut W, +} +impl<'a> WAVEGEN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WAVEGEN_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Normal frequency"] + #[inline(always)] + pub fn nfrq(self) -> &'a mut W { + self.variant(WAVEGEN_A::NFRQ) + } + #[doc = "Match frequency"] + #[inline(always)] + pub fn mfrq(self) -> &'a mut W { + self.variant(WAVEGEN_A::MFRQ) + } + #[doc = "Normal PWM"] + #[inline(always)] + pub fn npwm(self) -> &'a mut W { + self.variant(WAVEGEN_A::NPWM) + } + #[doc = "Match PWM"] + #[inline(always)] + pub fn mpwm(self) -> &'a mut W { + self.variant(WAVEGEN_A::MPWM) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u8 & 0x03); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Waveform Generation Mode"] + #[inline(always)] + pub fn wavegen(&self) -> WAVEGEN_R { + WAVEGEN_R::new((self.bits & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Waveform Generation Mode"] + #[inline(always)] + pub fn wavegen(&mut self) -> WAVEGEN_W { + WAVEGEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Waveform Generation Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wave](index.html) module"] +pub struct WAVE_SPEC; +impl crate::RegisterSpec for WAVE_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [wave::R](R) reader structure"] +impl crate::Readable for WAVE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wave::W](W) writer structure"] +impl crate::Writable for WAVE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WAVE to value 0"] +impl crate::Resettable for WAVE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/tc0/count8.rs b/pac/atsamc20e/src/tc0/count8.rs new file mode 100644 index 000000000000..777da5744358 --- /dev/null +++ b/pac/atsamc20e/src/tc0/count8.rs @@ -0,0 +1,68 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "CTRLBCLR register accessor: an alias for `Reg`"] +pub type CTRLBCLR = crate::Reg; +#[doc = "Control B Clear"] +pub mod ctrlbclr; +#[doc = "CTRLBSET register accessor: an alias for `Reg`"] +pub type CTRLBSET = crate::Reg; +#[doc = "Control B Set"] +pub mod ctrlbset; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "WAVE register accessor: an alias for `Reg`"] +pub type WAVE = crate::Reg; +#[doc = "Waveform Generation Control"] +pub mod wave; +#[doc = "DRVCTRL register accessor: an alias for `Reg`"] +pub type DRVCTRL = crate::Reg; +#[doc = "Control C"] +pub mod drvctrl; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Status"] +pub mod syncbusy; +#[doc = "COUNT register accessor: an alias for `Reg`"] +pub type COUNT = crate::Reg; +#[doc = "COUNT8 Count"] +pub mod count; +#[doc = "PER register accessor: an alias for `Reg`"] +pub type PER = crate::Reg; +#[doc = "COUNT8 Period"] +pub mod per; +#[doc = "CC register accessor: an alias for `Reg`"] +pub type CC = crate::Reg; +#[doc = "COUNT8 Compare and Capture"] +pub mod cc; +#[doc = "PERBUF register accessor: an alias for `Reg`"] +pub type PERBUF = crate::Reg; +#[doc = "COUNT8 Period Buffer"] +pub mod perbuf; +#[doc = "CCBUF register accessor: an alias for `Reg`"] +pub type CCBUF = crate::Reg; +#[doc = "COUNT8 Compare and Capture Buffer"] +pub mod ccbuf; diff --git a/pac/atsamc20e/src/tc0/count8/cc.rs b/pac/atsamc20e/src/tc0/count8/cc.rs new file mode 100644 index 000000000000..45f5c29c89af --- /dev/null +++ b/pac/atsamc20e/src/tc0/count8/cc.rs @@ -0,0 +1,104 @@ +#[doc = "Register `CC[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CC[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CC` reader - Counter/Compare Value"] +pub struct CC_R(crate::FieldReader); +impl CC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC` writer - Counter/Compare Value"] +pub struct CC_W<'a> { + w: &'a mut W, +} +impl<'a> CC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Counter/Compare Value"] + #[inline(always)] + pub fn cc(&self) -> CC_R { + CC_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Counter/Compare Value"] + #[inline(always)] + pub fn cc(&mut self) -> CC_W { + CC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT8 Compare and Capture\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc](index.html) module"] +pub struct CC_SPEC; +impl crate::RegisterSpec for CC_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [cc::R](R) reader structure"] +impl crate::Readable for CC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cc::W](W) writer structure"] +impl crate::Writable for CC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CC[%s] +to value 0"] +impl crate::Resettable for CC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/tc0/count8/ccbuf.rs b/pac/atsamc20e/src/tc0/count8/ccbuf.rs new file mode 100644 index 000000000000..cd81b1219860 --- /dev/null +++ b/pac/atsamc20e/src/tc0/count8/ccbuf.rs @@ -0,0 +1,104 @@ +#[doc = "Register `CCBUF[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CCBUF[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CCBUF` reader - Counter/Compare Buffer Value"] +pub struct CCBUF_R(crate::FieldReader); +impl CCBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CCBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUF` writer - Counter/Compare Buffer Value"] +pub struct CCBUF_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Counter/Compare Buffer Value"] + #[inline(always)] + pub fn ccbuf(&self) -> CCBUF_R { + CCBUF_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Counter/Compare Buffer Value"] + #[inline(always)] + pub fn ccbuf(&mut self) -> CCBUF_W { + CCBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT8 Compare and Capture Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccbuf](index.html) module"] +pub struct CCBUF_SPEC; +impl crate::RegisterSpec for CCBUF_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ccbuf::R](R) reader structure"] +impl crate::Readable for CCBUF_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ccbuf::W](W) writer structure"] +impl crate::Writable for CCBUF_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CCBUF[%s] +to value 0"] +impl crate::Resettable for CCBUF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/tc0/count8/count.rs b/pac/atsamc20e/src/tc0/count8/count.rs new file mode 100644 index 000000000000..0edbb0f17bb7 --- /dev/null +++ b/pac/atsamc20e/src/tc0/count8/count.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT8 Count\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count](index.html) module"] +pub struct COUNT_SPEC; +impl crate::RegisterSpec for COUNT_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [count::R](R) reader structure"] +impl crate::Readable for COUNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count::W](W) writer structure"] +impl crate::Writable for COUNT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT to value 0"] +impl crate::Resettable for COUNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/tc0/count8/ctrla.rs b/pac/atsamc20e/src/tc0/count8/ctrla.rs new file mode 100644 index 000000000000..cadcddaaead8 --- /dev/null +++ b/pac/atsamc20e/src/tc0/count8/ctrla.rs @@ -0,0 +1,851 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Timer Counter Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: Counter in 16-bit mode"] + COUNT16 = 0, + #[doc = "1: Counter in 8-bit mode"] + COUNT8 = 1, + #[doc = "2: Counter in 32-bit mode"] + COUNT32 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Timer Counter Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::COUNT16), + 1 => Some(MODE_A::COUNT8), + 2 => Some(MODE_A::COUNT32), + _ => None, + } + } + #[doc = "Checks if the value of the field is `COUNT16`"] + #[inline(always)] + pub fn is_count16(&self) -> bool { + **self == MODE_A::COUNT16 + } + #[doc = "Checks if the value of the field is `COUNT8`"] + #[inline(always)] + pub fn is_count8(&self) -> bool { + **self == MODE_A::COUNT8 + } + #[doc = "Checks if the value of the field is `COUNT32`"] + #[inline(always)] + pub fn is_count32(&self) -> bool { + **self == MODE_A::COUNT32 + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Timer Counter Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Counter in 16-bit mode"] + #[inline(always)] + pub fn count16(self) -> &'a mut W { + self.variant(MODE_A::COUNT16) + } + #[doc = "Counter in 8-bit mode"] + #[inline(always)] + pub fn count8(self) -> &'a mut W { + self.variant(MODE_A::COUNT8) + } + #[doc = "Counter in 32-bit mode"] + #[inline(always)] + pub fn count32(self) -> &'a mut W { + self.variant(MODE_A::COUNT32) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u32 & 0x03) << 2); + self.w + } +} +#[doc = "Prescaler and Counter Synchronization\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCSYNC_A { + #[doc = "0: Reload or reset the counter on next generic clock"] + GCLK = 0, + #[doc = "1: Reload or reset the counter on next prescaler clock"] + PRESC = 1, + #[doc = "2: Reload or reset the counter on next generic clock and reset the prescaler counter"] + RESYNC = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCSYNC_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCSYNC` reader - Prescaler and Counter Synchronization"] +pub struct PRESCSYNC_R(crate::FieldReader); +impl PRESCSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCSYNC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCSYNC_A::GCLK), + 1 => Some(PRESCSYNC_A::PRESC), + 2 => Some(PRESCSYNC_A::RESYNC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `GCLK`"] + #[inline(always)] + pub fn is_gclk(&self) -> bool { + **self == PRESCSYNC_A::GCLK + } + #[doc = "Checks if the value of the field is `PRESC`"] + #[inline(always)] + pub fn is_presc(&self) -> bool { + **self == PRESCSYNC_A::PRESC + } + #[doc = "Checks if the value of the field is `RESYNC`"] + #[inline(always)] + pub fn is_resync(&self) -> bool { + **self == PRESCSYNC_A::RESYNC + } +} +impl core::ops::Deref for PRESCSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCSYNC` writer - Prescaler and Counter Synchronization"] +pub struct PRESCSYNC_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCSYNC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCSYNC_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Reload or reset the counter on next generic clock"] + #[inline(always)] + pub fn gclk(self) -> &'a mut W { + self.variant(PRESCSYNC_A::GCLK) + } + #[doc = "Reload or reset the counter on next prescaler clock"] + #[inline(always)] + pub fn presc(self) -> &'a mut W { + self.variant(PRESCSYNC_A::PRESC) + } + #[doc = "Reload or reset the counter on next generic clock and reset the prescaler counter"] + #[inline(always)] + pub fn resync(self) -> &'a mut W { + self.variant(PRESCSYNC_A::RESYNC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u32 & 0x03) << 4); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - Clock On Demand"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - Clock On Demand"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: Prescaler: GCLK_TC"] + DIV1 = 0, + #[doc = "1: Prescaler: GCLK_TC/2"] + DIV2 = 1, + #[doc = "2: Prescaler: GCLK_TC/4"] + DIV4 = 2, + #[doc = "3: Prescaler: GCLK_TC/8"] + DIV8 = 3, + #[doc = "4: Prescaler: GCLK_TC/16"] + DIV16 = 4, + #[doc = "5: Prescaler: GCLK_TC/64"] + DIV64 = 5, + #[doc = "6: Prescaler: GCLK_TC/256"] + DIV256 = 6, + #[doc = "7: Prescaler: GCLK_TC/1024"] + DIV1024 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PRESCALER_A { + match self.bits { + 0 => PRESCALER_A::DIV1, + 1 => PRESCALER_A::DIV2, + 2 => PRESCALER_A::DIV4, + 3 => PRESCALER_A::DIV8, + 4 => PRESCALER_A::DIV16, + 5 => PRESCALER_A::DIV64, + 6 => PRESCALER_A::DIV256, + 7 => PRESCALER_A::DIV1024, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == PRESCALER_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PRESCALER_A::DIV1024 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Prescaler: GCLK_TC"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1) + } + #[doc = "Prescaler: GCLK_TC/2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "Prescaler: GCLK_TC/4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "Prescaler: GCLK_TC/8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "Prescaler: GCLK_TC/16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "Prescaler: GCLK_TC/64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "Prescaler: GCLK_TC/256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = "Prescaler: GCLK_TC/1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +#[doc = "Field `ALOCK` reader - Auto Lock"] +pub struct ALOCK_R(crate::FieldReader); +impl ALOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALOCK` writer - Auto Lock"] +pub struct ALOCK_W<'a> { + w: &'a mut W, +} +impl<'a> ALOCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `CAPTEN0` reader - Capture Channel 0 Enable"] +pub struct CAPTEN0_R(crate::FieldReader); +impl CAPTEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CAPTEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CAPTEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAPTEN0` writer - Capture Channel 0 Enable"] +pub struct CAPTEN0_W<'a> { + w: &'a mut W, +} +impl<'a> CAPTEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `CAPTEN1` reader - Capture Channel 1 Enable"] +pub struct CAPTEN1_R(crate::FieldReader); +impl CAPTEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CAPTEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CAPTEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAPTEN1` writer - Capture Channel 1 Enable"] +pub struct CAPTEN1_W<'a> { + w: &'a mut W, +} +impl<'a> CAPTEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `COPEN0` reader - Capture On Pin 0 Enable"] +pub struct COPEN0_R(crate::FieldReader); +impl COPEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COPEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COPEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COPEN0` writer - Capture On Pin 0 Enable"] +pub struct COPEN0_W<'a> { + w: &'a mut W, +} +impl<'a> COPEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `COPEN1` reader - Capture On Pin 1 Enable"] +pub struct COPEN1_R(crate::FieldReader); +impl COPEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COPEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COPEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COPEN1` writer - Capture On Pin 1 Enable"] +pub struct COPEN1_W<'a> { + w: &'a mut W, +} +impl<'a> COPEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:3 - Timer Counter Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bits 4:5 - Prescaler and Counter Synchronization"] + #[inline(always)] + pub fn prescsync(&self) -> PRESCSYNC_R { + PRESCSYNC_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Clock On Demand"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 11 - Auto Lock"] + #[inline(always)] + pub fn alock(&self) -> ALOCK_R { + ALOCK_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 16 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn capten0(&self) -> CAPTEN0_R { + CAPTEN0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn capten1(&self) -> CAPTEN1_R { + CAPTEN1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 20 - Capture On Pin 0 Enable"] + #[inline(always)] + pub fn copen0(&self) -> COPEN0_R { + COPEN0_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Capture On Pin 1 Enable"] + #[inline(always)] + pub fn copen1(&self) -> COPEN1_R { + COPEN1_R::new(((self.bits >> 21) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:3 - Timer Counter Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bits 4:5 - Prescaler and Counter Synchronization"] + #[inline(always)] + pub fn prescsync(&mut self) -> PRESCSYNC_W { + PRESCSYNC_W { w: self } + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - Clock On Demand"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Bit 11 - Auto Lock"] + #[inline(always)] + pub fn alock(&mut self) -> ALOCK_W { + ALOCK_W { w: self } + } + #[doc = "Bit 16 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn capten0(&mut self) -> CAPTEN0_W { + CAPTEN0_W { w: self } + } + #[doc = "Bit 17 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn capten1(&mut self) -> CAPTEN1_W { + CAPTEN1_W { w: self } + } + #[doc = "Bit 20 - Capture On Pin 0 Enable"] + #[inline(always)] + pub fn copen0(&mut self) -> COPEN0_W { + COPEN0_W { w: self } + } + #[doc = "Bit 21 - Capture On Pin 1 Enable"] + #[inline(always)] + pub fn copen1(&mut self) -> COPEN1_W { + COPEN1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/tc0/count8/ctrlbclr.rs b/pac/atsamc20e/src/tc0/count8/ctrlbclr.rs new file mode 100644 index 000000000000..76265674036a --- /dev/null +++ b/pac/atsamc20e/src/tc0/count8/ctrlbclr.rs @@ -0,0 +1,345 @@ +#[doc = "Register `CTRLBCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Counter Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `LUPD` reader - Lock Update"] +pub struct LUPD_R(crate::FieldReader); +impl LUPD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LUPD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LUPD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LUPD` writer - Lock Update"] +pub struct LUPD_W<'a> { + w: &'a mut W, +} +impl<'a> LUPD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ONESHOT` reader - One-Shot on Counter"] +pub struct ONESHOT_R(crate::FieldReader); +impl ONESHOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONESHOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONESHOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONESHOT` writer - One-Shot on Counter"] +pub struct ONESHOT_W<'a> { + w: &'a mut W, +} +impl<'a> ONESHOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Force a start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force a stop"] + STOP = 2, + #[doc = "3: Force update of double-buffered register"] + UPDATE = 3, + #[doc = "4: Force a read synchronization of COUNT"] + READSYNC = 4, + #[doc = "5: One-shot DMA trigger"] + DMAOS = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NONE), + 1 => Some(CMD_A::RETRIGGER), + 2 => Some(CMD_A::STOP), + 3 => Some(CMD_A::UPDATE), + 4 => Some(CMD_A::READSYNC), + 5 => Some(CMD_A::DMAOS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == CMD_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == CMD_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == CMD_A::STOP + } + #[doc = "Checks if the value of the field is `UPDATE`"] + #[inline(always)] + pub fn is_update(&self) -> bool { + **self == CMD_A::UPDATE + } + #[doc = "Checks if the value of the field is `READSYNC`"] + #[inline(always)] + pub fn is_readsync(&self) -> bool { + **self == CMD_A::READSYNC + } + #[doc = "Checks if the value of the field is `DMAOS`"] + #[inline(always)] + pub fn is_dmaos(&self) -> bool { + **self == CMD_A::DMAOS + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMD_A::NONE) + } + #[doc = "Force a start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMD_A::RETRIGGER) + } + #[doc = "Force a stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMD_A::STOP) + } + #[doc = "Force update of double-buffered register"] + #[inline(always)] + pub fn update(self) -> &'a mut W { + self.variant(CMD_A::UPDATE) + } + #[doc = "Force a read synchronization of COUNT"] + #[inline(always)] + pub fn readsync(self) -> &'a mut W { + self.variant(CMD_A::READSYNC) + } + #[doc = "One-shot DMA trigger"] + #[inline(always)] + pub fn dmaos(self) -> &'a mut W { + self.variant(CMD_A::DMAOS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 5)) | ((value as u8 & 0x07) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&self) -> LUPD_R { + LUPD_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 5) & 0x07) as u8) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&mut self) -> LUPD_W { + LUPD_W { w: self } + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&mut self) -> ONESHOT_W { + ONESHOT_W { w: self } + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbclr](index.html) module"] +pub struct CTRLBCLR_SPEC; +impl crate::RegisterSpec for CTRLBCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbclr::R](R) reader structure"] +impl crate::Readable for CTRLBCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbclr::W](W) writer structure"] +impl crate::Writable for CTRLBCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLBCLR to value 0"] +impl crate::Resettable for CTRLBCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/tc0/count8/ctrlbset.rs b/pac/atsamc20e/src/tc0/count8/ctrlbset.rs new file mode 100644 index 000000000000..610914c9c7c8 --- /dev/null +++ b/pac/atsamc20e/src/tc0/count8/ctrlbset.rs @@ -0,0 +1,345 @@ +#[doc = "Register `CTRLBSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Counter Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `LUPD` reader - Lock Update"] +pub struct LUPD_R(crate::FieldReader); +impl LUPD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LUPD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LUPD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LUPD` writer - Lock Update"] +pub struct LUPD_W<'a> { + w: &'a mut W, +} +impl<'a> LUPD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ONESHOT` reader - One-Shot on Counter"] +pub struct ONESHOT_R(crate::FieldReader); +impl ONESHOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONESHOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONESHOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONESHOT` writer - One-Shot on Counter"] +pub struct ONESHOT_W<'a> { + w: &'a mut W, +} +impl<'a> ONESHOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Force a start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force a stop"] + STOP = 2, + #[doc = "3: Force update of double-buffered register"] + UPDATE = 3, + #[doc = "4: Force a read synchronization of COUNT"] + READSYNC = 4, + #[doc = "5: One-shot DMA trigger"] + DMAOS = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NONE), + 1 => Some(CMD_A::RETRIGGER), + 2 => Some(CMD_A::STOP), + 3 => Some(CMD_A::UPDATE), + 4 => Some(CMD_A::READSYNC), + 5 => Some(CMD_A::DMAOS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == CMD_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == CMD_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == CMD_A::STOP + } + #[doc = "Checks if the value of the field is `UPDATE`"] + #[inline(always)] + pub fn is_update(&self) -> bool { + **self == CMD_A::UPDATE + } + #[doc = "Checks if the value of the field is `READSYNC`"] + #[inline(always)] + pub fn is_readsync(&self) -> bool { + **self == CMD_A::READSYNC + } + #[doc = "Checks if the value of the field is `DMAOS`"] + #[inline(always)] + pub fn is_dmaos(&self) -> bool { + **self == CMD_A::DMAOS + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMD_A::NONE) + } + #[doc = "Force a start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMD_A::RETRIGGER) + } + #[doc = "Force a stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMD_A::STOP) + } + #[doc = "Force update of double-buffered register"] + #[inline(always)] + pub fn update(self) -> &'a mut W { + self.variant(CMD_A::UPDATE) + } + #[doc = "Force a read synchronization of COUNT"] + #[inline(always)] + pub fn readsync(self) -> &'a mut W { + self.variant(CMD_A::READSYNC) + } + #[doc = "One-shot DMA trigger"] + #[inline(always)] + pub fn dmaos(self) -> &'a mut W { + self.variant(CMD_A::DMAOS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 5)) | ((value as u8 & 0x07) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&self) -> LUPD_R { + LUPD_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 5) & 0x07) as u8) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&mut self) -> LUPD_W { + LUPD_W { w: self } + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&mut self) -> ONESHOT_W { + ONESHOT_W { w: self } + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbset](index.html) module"] +pub struct CTRLBSET_SPEC; +impl crate::RegisterSpec for CTRLBSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbset::R](R) reader structure"] +impl crate::Readable for CTRLBSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbset::W](W) writer structure"] +impl crate::Writable for CTRLBSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLBSET to value 0"] +impl crate::Resettable for CTRLBSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/tc0/count8/dbgctrl.rs b/pac/atsamc20e/src/tc0/count8/dbgctrl.rs new file mode 100644 index 000000000000..0383e70d0429 --- /dev/null +++ b/pac/atsamc20e/src/tc0/count8/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Run During Debug"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Run During Debug"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/tc0/count8/drvctrl.rs b/pac/atsamc20e/src/tc0/count8/drvctrl.rs new file mode 100644 index 000000000000..323926b4b22d --- /dev/null +++ b/pac/atsamc20e/src/tc0/count8/drvctrl.rs @@ -0,0 +1,160 @@ +#[doc = "Register `DRVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DRVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INVEN0` reader - Output Waveform Invert Enable 0"] +pub struct INVEN0_R(crate::FieldReader); +impl INVEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN0` writer - Output Waveform Invert Enable 0"] +pub struct INVEN0_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `INVEN1` reader - Output Waveform Invert Enable 1"] +pub struct INVEN1_R(crate::FieldReader); +impl INVEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN1` writer - Output Waveform Invert Enable 1"] +pub struct INVEN1_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - Output Waveform Invert Enable 0"] + #[inline(always)] + pub fn inven0(&self) -> INVEN0_R { + INVEN0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Output Waveform Invert Enable 1"] + #[inline(always)] + pub fn inven1(&self) -> INVEN1_R { + INVEN1_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Output Waveform Invert Enable 0"] + #[inline(always)] + pub fn inven0(&mut self) -> INVEN0_W { + INVEN0_W { w: self } + } + #[doc = "Bit 1 - Output Waveform Invert Enable 1"] + #[inline(always)] + pub fn inven1(&mut self) -> INVEN1_W { + INVEN1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control C\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [drvctrl](index.html) module"] +pub struct DRVCTRL_SPEC; +impl crate::RegisterSpec for DRVCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [drvctrl::R](R) reader structure"] +impl crate::Readable for DRVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [drvctrl::W](W) writer structure"] +impl crate::Writable for DRVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DRVCTRL to value 0"] +impl crate::Resettable for DRVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/tc0/count8/evctrl.rs b/pac/atsamc20e/src/tc0/count8/evctrl.rs new file mode 100644 index 000000000000..7d4c38d486c1 --- /dev/null +++ b/pac/atsamc20e/src/tc0/count8/evctrl.rs @@ -0,0 +1,465 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Event Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EVACT_A { + #[doc = "0: Event action disabled"] + OFF = 0, + #[doc = "1: Start, restart or retrigger TC on event"] + RETRIGGER = 1, + #[doc = "2: Count on event"] + COUNT = 2, + #[doc = "3: Start TC on event"] + START = 3, + #[doc = "4: Time stamp capture"] + STAMP = 4, + #[doc = "5: Period catured in CC0, pulse width in CC1"] + PPW = 5, + #[doc = "6: Period catured in CC1, pulse width in CC0"] + PWP = 6, + #[doc = "7: Pulse width capture"] + PW = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EVACT_A) -> Self { + variant as _ + } +} +#[doc = "Field `EVACT` reader - Event Action"] +pub struct EVACT_R(crate::FieldReader); +impl EVACT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVACT_A { + match self.bits { + 0 => EVACT_A::OFF, + 1 => EVACT_A::RETRIGGER, + 2 => EVACT_A::COUNT, + 3 => EVACT_A::START, + 4 => EVACT_A::STAMP, + 5 => EVACT_A::PPW, + 6 => EVACT_A::PWP, + 7 => EVACT_A::PW, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == EVACT_A::OFF + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == EVACT_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `COUNT`"] + #[inline(always)] + pub fn is_count(&self) -> bool { + **self == EVACT_A::COUNT + } + #[doc = "Checks if the value of the field is `START`"] + #[inline(always)] + pub fn is_start(&self) -> bool { + **self == EVACT_A::START + } + #[doc = "Checks if the value of the field is `STAMP`"] + #[inline(always)] + pub fn is_stamp(&self) -> bool { + **self == EVACT_A::STAMP + } + #[doc = "Checks if the value of the field is `PPW`"] + #[inline(always)] + pub fn is_ppw(&self) -> bool { + **self == EVACT_A::PPW + } + #[doc = "Checks if the value of the field is `PWP`"] + #[inline(always)] + pub fn is_pwp(&self) -> bool { + **self == EVACT_A::PWP + } + #[doc = "Checks if the value of the field is `PW`"] + #[inline(always)] + pub fn is_pw(&self) -> bool { + **self == EVACT_A::PW + } +} +impl core::ops::Deref for EVACT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT` writer - Event Action"] +pub struct EVACT_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EVACT_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Event action disabled"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(EVACT_A::OFF) + } + #[doc = "Start, restart or retrigger TC on event"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(EVACT_A::RETRIGGER) + } + #[doc = "Count on event"] + #[inline(always)] + pub fn count(self) -> &'a mut W { + self.variant(EVACT_A::COUNT) + } + #[doc = "Start TC on event"] + #[inline(always)] + pub fn start(self) -> &'a mut W { + self.variant(EVACT_A::START) + } + #[doc = "Time stamp capture"] + #[inline(always)] + pub fn stamp(self) -> &'a mut W { + self.variant(EVACT_A::STAMP) + } + #[doc = "Period catured in CC0, pulse width in CC1"] + #[inline(always)] + pub fn ppw(self) -> &'a mut W { + self.variant(EVACT_A::PPW) + } + #[doc = "Period catured in CC1, pulse width in CC0"] + #[inline(always)] + pub fn pwp(self) -> &'a mut W { + self.variant(EVACT_A::PWP) + } + #[doc = "Pulse width capture"] + #[inline(always)] + pub fn pw(self) -> &'a mut W { + self.variant(EVACT_A::PW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u16 & 0x07); + self.w + } +} +#[doc = "Field `TCINV` reader - TC Event Input Polarity"] +pub struct TCINV_R(crate::FieldReader); +impl TCINV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCINV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCINV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCINV` writer - TC Event Input Polarity"] +pub struct TCINV_W<'a> { + w: &'a mut W, +} +impl<'a> TCINV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `TCEI` reader - TC Event Enable"] +pub struct TCEI_R(crate::FieldReader); +impl TCEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCEI` writer - TC Event Enable"] +pub struct TCEI_W<'a> { + w: &'a mut W, +} +impl<'a> TCEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `OVFEO` reader - Event Output Enable"] +pub struct OVFEO_R(crate::FieldReader); +impl OVFEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVFEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVFEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVFEO` writer - Event Output Enable"] +pub struct OVFEO_W<'a> { + w: &'a mut W, +} +impl<'a> OVFEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `MCEO0` reader - MC Event Output Enable 0"] +pub struct MCEO0_R(crate::FieldReader); +impl MCEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO0` writer - MC Event Output Enable 0"] +pub struct MCEO0_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u16 & 0x01) << 12); + self.w + } +} +#[doc = "Field `MCEO1` reader - MC Event Output Enable 1"] +pub struct MCEO1_R(crate::FieldReader); +impl MCEO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO1` writer - MC Event Output Enable 1"] +pub struct MCEO1_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u16 & 0x01) << 13); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Event Action"] + #[inline(always)] + pub fn evact(&self) -> EVACT_R { + EVACT_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 4 - TC Event Input Polarity"] + #[inline(always)] + pub fn tcinv(&self) -> TCINV_R { + TCINV_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - TC Event Enable"] + #[inline(always)] + pub fn tcei(&self) -> TCEI_R { + TCEI_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 8 - Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&self) -> OVFEO_R { + OVFEO_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 12 - MC Event Output Enable 0"] + #[inline(always)] + pub fn mceo0(&self) -> MCEO0_R { + MCEO0_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - MC Event Output Enable 1"] + #[inline(always)] + pub fn mceo1(&self) -> MCEO1_R { + MCEO1_R::new(((self.bits >> 13) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Event Action"] + #[inline(always)] + pub fn evact(&mut self) -> EVACT_W { + EVACT_W { w: self } + } + #[doc = "Bit 4 - TC Event Input Polarity"] + #[inline(always)] + pub fn tcinv(&mut self) -> TCINV_W { + TCINV_W { w: self } + } + #[doc = "Bit 5 - TC Event Enable"] + #[inline(always)] + pub fn tcei(&mut self) -> TCEI_W { + TCEI_W { w: self } + } + #[doc = "Bit 8 - Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&mut self) -> OVFEO_W { + OVFEO_W { w: self } + } + #[doc = "Bit 12 - MC Event Output Enable 0"] + #[inline(always)] + pub fn mceo0(&mut self) -> MCEO0_W { + MCEO0_W { w: self } + } + #[doc = "Bit 13 - MC Event Output Enable 1"] + #[inline(always)] + pub fn mceo1(&mut self) -> MCEO1_W { + MCEO1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/tc0/count8/intenclr.rs b/pac/atsamc20e/src/tc0/count8/intenclr.rs new file mode 100644 index 000000000000..af01ef5b7dca --- /dev/null +++ b/pac/atsamc20e/src/tc0/count8/intenclr.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - OVF Interrupt Disable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - OVF Interrupt Disable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - ERR Interrupt Disable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - ERR Interrupt Disable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MC0` reader - MC Interrupt Disable 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - MC Interrupt Disable 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - MC Interrupt Disable 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - MC Interrupt Disable 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - OVF Interrupt Disable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ERR Interrupt Disable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - MC Interrupt Disable 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - MC Interrupt Disable 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - OVF Interrupt Disable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - ERR Interrupt Disable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 4 - MC Interrupt Disable 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - MC Interrupt Disable 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/tc0/count8/intenset.rs b/pac/atsamc20e/src/tc0/count8/intenset.rs new file mode 100644 index 000000000000..0e1883a2f20a --- /dev/null +++ b/pac/atsamc20e/src/tc0/count8/intenset.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - OVF Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - OVF Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - ERR Interrupt Enable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - ERR Interrupt Enable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MC0` reader - MC Interrupt Enable 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - MC Interrupt Enable 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - MC Interrupt Enable 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - MC Interrupt Enable 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - OVF Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ERR Interrupt Enable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - MC Interrupt Enable 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - MC Interrupt Enable 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - OVF Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - ERR Interrupt Enable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 4 - MC Interrupt Enable 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - MC Interrupt Enable 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/tc0/count8/intflag.rs b/pac/atsamc20e/src/tc0/count8/intflag.rs new file mode 100644 index 000000000000..1dddffaf8e7f --- /dev/null +++ b/pac/atsamc20e/src/tc0/count8/intflag.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - OVF Interrupt Flag"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - OVF Interrupt Flag"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - ERR Interrupt Flag"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - ERR Interrupt Flag"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MC0` reader - MC Interrupt Flag 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - MC Interrupt Flag 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - MC Interrupt Flag 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - MC Interrupt Flag 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - OVF Interrupt Flag"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ERR Interrupt Flag"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - MC Interrupt Flag 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - MC Interrupt Flag 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - OVF Interrupt Flag"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - ERR Interrupt Flag"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 4 - MC Interrupt Flag 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - MC Interrupt Flag 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/tc0/count8/per.rs b/pac/atsamc20e/src/tc0/count8/per.rs new file mode 100644 index 000000000000..c9ab52e247d8 --- /dev/null +++ b/pac/atsamc20e/src/tc0/count8/per.rs @@ -0,0 +1,103 @@ +#[doc = "Register `PER` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PER` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER` reader - Period Value"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` writer - Period Value"] +pub struct PER_W<'a> { + w: &'a mut W, +} +impl<'a> PER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Period Value"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Period Value"] + #[inline(always)] + pub fn per(&mut self) -> PER_W { + PER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT8 Period\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [per](index.html) module"] +pub struct PER_SPEC; +impl crate::RegisterSpec for PER_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [per::R](R) reader structure"] +impl crate::Readable for PER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [per::W](W) writer structure"] +impl crate::Writable for PER_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PER to value 0xff"] +impl crate::Resettable for PER_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xff + } +} diff --git a/pac/atsamc20e/src/tc0/count8/perbuf.rs b/pac/atsamc20e/src/tc0/count8/perbuf.rs new file mode 100644 index 000000000000..cbd500e2bbe1 --- /dev/null +++ b/pac/atsamc20e/src/tc0/count8/perbuf.rs @@ -0,0 +1,103 @@ +#[doc = "Register `PERBUF` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PERBUF` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PERBUF` reader - Period Buffer Value"] +pub struct PERBUF_R(crate::FieldReader); +impl PERBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PERBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERBUF` writer - Period Buffer Value"] +pub struct PERBUF_W<'a> { + w: &'a mut W, +} +impl<'a> PERBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Period Buffer Value"] + #[inline(always)] + pub fn perbuf(&self) -> PERBUF_R { + PERBUF_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Period Buffer Value"] + #[inline(always)] + pub fn perbuf(&mut self) -> PERBUF_W { + PERBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT8 Period Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [perbuf](index.html) module"] +pub struct PERBUF_SPEC; +impl crate::RegisterSpec for PERBUF_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [perbuf::R](R) reader structure"] +impl crate::Readable for PERBUF_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [perbuf::W](W) writer structure"] +impl crate::Writable for PERBUF_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PERBUF to value 0xff"] +impl crate::Resettable for PERBUF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xff + } +} diff --git a/pac/atsamc20e/src/tc0/count8/status.rs b/pac/atsamc20e/src/tc0/count8/status.rs new file mode 100644 index 000000000000..5088af446830 --- /dev/null +++ b/pac/atsamc20e/src/tc0/count8/status.rs @@ -0,0 +1,301 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `STOP` reader - Stop Status Flag"] +pub struct STOP_R(crate::FieldReader); +impl STOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STOP` writer - Stop Status Flag"] +pub struct STOP_W<'a> { + w: &'a mut W, +} +impl<'a> STOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SLAVE` reader - Slave Status Flag"] +pub struct SLAVE_R(crate::FieldReader); +impl SLAVE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLAVE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SLAVE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLAVE` writer - Slave Status Flag"] +pub struct SLAVE_W<'a> { + w: &'a mut W, +} +impl<'a> SLAVE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PERBUFV` reader - Synchronization Busy Status"] +pub struct PERBUFV_R(crate::FieldReader); +impl PERBUFV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PERBUFV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERBUFV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERBUFV` writer - Synchronization Busy Status"] +pub struct PERBUFV_W<'a> { + w: &'a mut W, +} +impl<'a> PERBUFV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CCBUFV0` reader - Compare channel buffer 0 valid"] +pub struct CCBUFV0_R(crate::FieldReader); +impl CCBUFV0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBUFV0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUFV0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUFV0` writer - Compare channel buffer 0 valid"] +pub struct CCBUFV0_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUFV0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `CCBUFV1` reader - Compare channel buffer 1 valid"] +pub struct CCBUFV1_R(crate::FieldReader); +impl CCBUFV1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBUFV1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUFV1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUFV1` writer - Compare channel buffer 1 valid"] +pub struct CCBUFV1_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUFV1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Stop Status Flag"] + #[inline(always)] + pub fn stop(&self) -> STOP_R { + STOP_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Slave Status Flag"] + #[inline(always)] + pub fn slave(&self) -> SLAVE_R { + SLAVE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 3 - Synchronization Busy Status"] + #[inline(always)] + pub fn perbufv(&self) -> PERBUFV_R { + PERBUFV_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Compare channel buffer 0 valid"] + #[inline(always)] + pub fn ccbufv0(&self) -> CCBUFV0_R { + CCBUFV0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Compare channel buffer 1 valid"] + #[inline(always)] + pub fn ccbufv1(&self) -> CCBUFV1_R { + CCBUFV1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Stop Status Flag"] + #[inline(always)] + pub fn stop(&mut self) -> STOP_W { + STOP_W { w: self } + } + #[doc = "Bit 1 - Slave Status Flag"] + #[inline(always)] + pub fn slave(&mut self) -> SLAVE_W { + SLAVE_W { w: self } + } + #[doc = "Bit 3 - Synchronization Busy Status"] + #[inline(always)] + pub fn perbufv(&mut self) -> PERBUFV_W { + PERBUFV_W { w: self } + } + #[doc = "Bit 4 - Compare channel buffer 0 valid"] + #[inline(always)] + pub fn ccbufv0(&mut self) -> CCBUFV0_W { + CCBUFV0_W { w: self } + } + #[doc = "Bit 5 - Compare channel buffer 1 valid"] + #[inline(always)] + pub fn ccbufv1(&mut self) -> CCBUFV1_W { + CCBUFV1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0x01"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pac/atsamc20e/src/tc0/count8/syncbusy.rs b/pac/atsamc20e/src/tc0/count8/syncbusy.rs new file mode 100644 index 000000000000..7ad8d91a84de --- /dev/null +++ b/pac/atsamc20e/src/tc0/count8/syncbusy.rs @@ -0,0 +1,193 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - swrst"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLB` reader - CTRLB"] +pub struct CTRLB_R(crate::FieldReader); +impl CTRLB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STATUS` reader - STATUS"] +pub struct STATUS_R(crate::FieldReader); +impl STATUS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STATUS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STATUS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` reader - Counter"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` reader - Period"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC0` reader - Compare Channel 0"] +pub struct CC0_R(crate::FieldReader); +impl CC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC1` reader - Compare Channel 1"] +pub struct CC1_R(crate::FieldReader); +impl CC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - swrst"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - CTRLB"] + #[inline(always)] + pub fn ctrlb(&self) -> CTRLB_R { + CTRLB_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - STATUS"] + #[inline(always)] + pub fn status(&self) -> STATUS_R { + STATUS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Counter"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Period"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Compare Channel 0"] + #[inline(always)] + pub fn cc0(&self) -> CC0_R { + CC0_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Compare Channel 1"] + #[inline(always)] + pub fn cc1(&self) -> CC1_R { + CC1_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +#[doc = "Synchronization Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/tc0/count8/wave.rs b/pac/atsamc20e/src/tc0/count8/wave.rs new file mode 100644 index 000000000000..46061b24b75d --- /dev/null +++ b/pac/atsamc20e/src/tc0/count8/wave.rs @@ -0,0 +1,178 @@ +#[doc = "Register `WAVE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WAVE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Waveform Generation Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WAVEGEN_A { + #[doc = "0: Normal frequency"] + NFRQ = 0, + #[doc = "1: Match frequency"] + MFRQ = 1, + #[doc = "2: Normal PWM"] + NPWM = 2, + #[doc = "3: Match PWM"] + MPWM = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WAVEGEN_A) -> Self { + variant as _ + } +} +#[doc = "Field `WAVEGEN` reader - Waveform Generation Mode"] +pub struct WAVEGEN_R(crate::FieldReader); +impl WAVEGEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WAVEGEN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> WAVEGEN_A { + match self.bits { + 0 => WAVEGEN_A::NFRQ, + 1 => WAVEGEN_A::MFRQ, + 2 => WAVEGEN_A::NPWM, + 3 => WAVEGEN_A::MPWM, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NFRQ`"] + #[inline(always)] + pub fn is_nfrq(&self) -> bool { + **self == WAVEGEN_A::NFRQ + } + #[doc = "Checks if the value of the field is `MFRQ`"] + #[inline(always)] + pub fn is_mfrq(&self) -> bool { + **self == WAVEGEN_A::MFRQ + } + #[doc = "Checks if the value of the field is `NPWM`"] + #[inline(always)] + pub fn is_npwm(&self) -> bool { + **self == WAVEGEN_A::NPWM + } + #[doc = "Checks if the value of the field is `MPWM`"] + #[inline(always)] + pub fn is_mpwm(&self) -> bool { + **self == WAVEGEN_A::MPWM + } +} +impl core::ops::Deref for WAVEGEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAVEGEN` writer - Waveform Generation Mode"] +pub struct WAVEGEN_W<'a> { + w: &'a mut W, +} +impl<'a> WAVEGEN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WAVEGEN_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Normal frequency"] + #[inline(always)] + pub fn nfrq(self) -> &'a mut W { + self.variant(WAVEGEN_A::NFRQ) + } + #[doc = "Match frequency"] + #[inline(always)] + pub fn mfrq(self) -> &'a mut W { + self.variant(WAVEGEN_A::MFRQ) + } + #[doc = "Normal PWM"] + #[inline(always)] + pub fn npwm(self) -> &'a mut W { + self.variant(WAVEGEN_A::NPWM) + } + #[doc = "Match PWM"] + #[inline(always)] + pub fn mpwm(self) -> &'a mut W { + self.variant(WAVEGEN_A::MPWM) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u8 & 0x03); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Waveform Generation Mode"] + #[inline(always)] + pub fn wavegen(&self) -> WAVEGEN_R { + WAVEGEN_R::new((self.bits & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Waveform Generation Mode"] + #[inline(always)] + pub fn wavegen(&mut self) -> WAVEGEN_W { + WAVEGEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Waveform Generation Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wave](index.html) module"] +pub struct WAVE_SPEC; +impl crate::RegisterSpec for WAVE_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [wave::R](R) reader structure"] +impl crate::Readable for WAVE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wave::W](W) writer structure"] +impl crate::Writable for WAVE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WAVE to value 0"] +impl crate::Resettable for WAVE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/tcc0.rs b/pac/atsamc20e/src/tcc0.rs new file mode 100644 index 000000000000..6ce813a9e3d5 --- /dev/null +++ b/pac/atsamc20e/src/tcc0.rs @@ -0,0 +1,359 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - Control B Clear"] + pub ctrlbclr: crate::Reg, + #[doc = "0x05 - Control B Set"] + pub ctrlbset: crate::Reg, + _reserved3: [u8; 0x02], + #[doc = "0x08 - Synchronization Busy"] + pub syncbusy: crate::Reg, + #[doc = "0x0c - Recoverable Fault A Configuration"] + pub fctrla: crate::Reg, + #[doc = "0x10 - Recoverable Fault B Configuration"] + pub fctrlb: crate::Reg, + #[doc = "0x14 - Waveform Extension Configuration"] + pub wexctrl: crate::Reg, + #[doc = "0x18 - Driver Control"] + pub drvctrl: crate::Reg, + _reserved8: [u8; 0x02], + #[doc = "0x1e - Debug Control"] + pub dbgctrl: crate::Reg, + _reserved9: [u8; 0x01], + #[doc = "0x20 - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x24 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x28 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x2c - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x30 - Status"] + pub status: crate::Reg, + _reserved_14_count: [u8; 0x04], + #[doc = "0x38 - Pattern"] + pub patt: crate::Reg, + _reserved16: [u8; 0x02], + #[doc = "0x3c - Waveform Control"] + pub wave: crate::Reg, + _reserved_17_per: [u8; 0x04], + _reserved_18_cc: [u8; 0x10], + _reserved19: [u8; 0x10], + #[doc = "0x64 - Pattern Buffer"] + pub pattbuf: crate::Reg, + _reserved20: [u8; 0x06], + _reserved_20_perbuf: [u8; 0x04], + _reserved_21_ccbuf: [u8; 0x10], +} +impl RegisterBlock { + #[doc = "0x34 - Count"] + #[inline(always)] + pub fn count_dith6_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(52usize) + as *const crate::Reg) + } + } + #[doc = "0x34 - Count"] + #[inline(always)] + pub fn count_dith5_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(52usize) + as *const crate::Reg) + } + } + #[doc = "0x34 - Count"] + #[inline(always)] + pub fn count_dith4_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(52usize) + as *const crate::Reg) + } + } + #[doc = "0x34 - Count"] + #[inline(always)] + pub fn count(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(52usize) + as *const crate::Reg) + } + } + #[doc = "0x40 - Period"] + #[inline(always)] + pub fn per_dith6_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(64usize) + as *const crate::Reg) + } + } + #[doc = "0x40 - Period"] + #[inline(always)] + pub fn per_dith5_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(64usize) + as *const crate::Reg) + } + } + #[doc = "0x40 - Period"] + #[inline(always)] + pub fn per_dith4_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(64usize) + as *const crate::Reg) + } + } + #[doc = "0x40 - Period"] + #[inline(always)] + pub fn per(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(64usize) + as *const crate::Reg) + } + } + #[doc = "0x44..0x54 - Compare and Capture"] + #[inline(always)] + pub fn cc_dith6_mode(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(68usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x44..0x54 - Compare and Capture"] + #[inline(always)] + pub fn cc_dith5_mode(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(68usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x44..0x54 - Compare and Capture"] + #[inline(always)] + pub fn cc_dith4_mode(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(68usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x44..0x54 - Compare and Capture"] + #[inline(always)] + pub fn cc(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(68usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x6c - Period Buffer"] + #[inline(always)] + pub fn perbuf_dith6_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(108usize) + as *const crate::Reg) + } + } + #[doc = "0x6c - Period Buffer"] + #[inline(always)] + pub fn perbuf_dith5_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(108usize) + as *const crate::Reg) + } + } + #[doc = "0x6c - Period Buffer"] + #[inline(always)] + pub fn perbuf_dith4_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(108usize) + as *const crate::Reg) + } + } + #[doc = "0x6c - Period Buffer"] + #[inline(always)] + pub fn perbuf(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(108usize) + as *const crate::Reg) + } + } + #[doc = "0x70..0x80 - Compare and Capture Buffer"] + #[inline(always)] + pub fn ccbuf_dith6_mode(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(112usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x70..0x80 - Compare and Capture Buffer"] + #[inline(always)] + pub fn ccbuf_dith5_mode(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(112usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x70..0x80 - Compare and Capture Buffer"] + #[inline(always)] + pub fn ccbuf_dith4_mode(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(112usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x70..0x80 - Compare and Capture Buffer"] + #[inline(always)] + pub fn ccbuf(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(112usize) + as *const [crate::Reg; 4]) + } + } +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "CTRLBCLR register accessor: an alias for `Reg`"] +pub type CTRLBCLR = crate::Reg; +#[doc = "Control B Clear"] +pub mod ctrlbclr; +#[doc = "CTRLBSET register accessor: an alias for `Reg`"] +pub type CTRLBSET = crate::Reg; +#[doc = "Control B Set"] +pub mod ctrlbset; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Busy"] +pub mod syncbusy; +#[doc = "FCTRLA register accessor: an alias for `Reg`"] +pub type FCTRLA = crate::Reg; +#[doc = "Recoverable Fault A Configuration"] +pub mod fctrla; +#[doc = "FCTRLB register accessor: an alias for `Reg`"] +pub type FCTRLB = crate::Reg; +#[doc = "Recoverable Fault B Configuration"] +pub mod fctrlb; +#[doc = "WEXCTRL register accessor: an alias for `Reg`"] +pub type WEXCTRL = crate::Reg; +#[doc = "Waveform Extension Configuration"] +pub mod wexctrl; +#[doc = "DRVCTRL register accessor: an alias for `Reg`"] +pub type DRVCTRL = crate::Reg; +#[doc = "Driver Control"] +pub mod drvctrl; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "COUNT register accessor: an alias for `Reg`"] +pub type COUNT = crate::Reg; +#[doc = "Count"] +pub mod count; +#[doc = "COUNT_DITH4_MODE register accessor: an alias for `Reg`"] +pub type COUNT_DITH4_MODE = crate::Reg; +#[doc = "Count"] +pub mod count_dith4_mode; +#[doc = "COUNT_DITH5_MODE register accessor: an alias for `Reg`"] +pub type COUNT_DITH5_MODE = crate::Reg; +#[doc = "Count"] +pub mod count_dith5_mode; +#[doc = "COUNT_DITH6_MODE register accessor: an alias for `Reg`"] +pub type COUNT_DITH6_MODE = crate::Reg; +#[doc = "Count"] +pub mod count_dith6_mode; +#[doc = "PATT register accessor: an alias for `Reg`"] +pub type PATT = crate::Reg; +#[doc = "Pattern"] +pub mod patt; +#[doc = "WAVE register accessor: an alias for `Reg`"] +pub type WAVE = crate::Reg; +#[doc = "Waveform Control"] +pub mod wave; +#[doc = "PER register accessor: an alias for `Reg`"] +pub type PER = crate::Reg; +#[doc = "Period"] +pub mod per; +#[doc = "PER_DITH4_MODE register accessor: an alias for `Reg`"] +pub type PER_DITH4_MODE = crate::Reg; +#[doc = "Period"] +pub mod per_dith4_mode; +#[doc = "PER_DITH5_MODE register accessor: an alias for `Reg`"] +pub type PER_DITH5_MODE = crate::Reg; +#[doc = "Period"] +pub mod per_dith5_mode; +#[doc = "PER_DITH6_MODE register accessor: an alias for `Reg`"] +pub type PER_DITH6_MODE = crate::Reg; +#[doc = "Period"] +pub mod per_dith6_mode; +#[doc = "CC register accessor: an alias for `Reg`"] +pub type CC = crate::Reg; +#[doc = "Compare and Capture"] +pub mod cc; +#[doc = "CC_DITH4_MODE register accessor: an alias for `Reg`"] +pub type CC_DITH4_MODE = crate::Reg; +#[doc = "Compare and Capture"] +pub mod cc_dith4_mode; +#[doc = "CC_DITH5_MODE register accessor: an alias for `Reg`"] +pub type CC_DITH5_MODE = crate::Reg; +#[doc = "Compare and Capture"] +pub mod cc_dith5_mode; +#[doc = "CC_DITH6_MODE register accessor: an alias for `Reg`"] +pub type CC_DITH6_MODE = crate::Reg; +#[doc = "Compare and Capture"] +pub mod cc_dith6_mode; +#[doc = "PATTBUF register accessor: an alias for `Reg`"] +pub type PATTBUF = crate::Reg; +#[doc = "Pattern Buffer"] +pub mod pattbuf; +#[doc = "PERBUF register accessor: an alias for `Reg`"] +pub type PERBUF = crate::Reg; +#[doc = "Period Buffer"] +pub mod perbuf; +#[doc = "PERBUF_DITH4_MODE register accessor: an alias for `Reg`"] +pub type PERBUF_DITH4_MODE = crate::Reg; +#[doc = "Period Buffer"] +pub mod perbuf_dith4_mode; +#[doc = "PERBUF_DITH5_MODE register accessor: an alias for `Reg`"] +pub type PERBUF_DITH5_MODE = crate::Reg; +#[doc = "Period Buffer"] +pub mod perbuf_dith5_mode; +#[doc = "PERBUF_DITH6_MODE register accessor: an alias for `Reg`"] +pub type PERBUF_DITH6_MODE = crate::Reg; +#[doc = "Period Buffer"] +pub mod perbuf_dith6_mode; +#[doc = "CCBUF register accessor: an alias for `Reg`"] +pub type CCBUF = crate::Reg; +#[doc = "Compare and Capture Buffer"] +pub mod ccbuf; +#[doc = "CCBUF_DITH4_MODE register accessor: an alias for `Reg`"] +pub type CCBUF_DITH4_MODE = crate::Reg; +#[doc = "Compare and Capture Buffer"] +pub mod ccbuf_dith4_mode; +#[doc = "CCBUF_DITH5_MODE register accessor: an alias for `Reg`"] +pub type CCBUF_DITH5_MODE = crate::Reg; +#[doc = "Compare and Capture Buffer"] +pub mod ccbuf_dith5_mode; +#[doc = "CCBUF_DITH6_MODE register accessor: an alias for `Reg`"] +pub type CCBUF_DITH6_MODE = crate::Reg; +#[doc = "Compare and Capture Buffer"] +pub mod ccbuf_dith6_mode; diff --git a/pac/atsamc20e/src/tcc0/cc.rs b/pac/atsamc20e/src/tcc0/cc.rs new file mode 100644 index 000000000000..c4d6df7a9a20 --- /dev/null +++ b/pac/atsamc20e/src/tcc0/cc.rs @@ -0,0 +1,104 @@ +#[doc = "Register `CC[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CC[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CC` reader - Channel Compare/Capture Value"] +pub struct CC_R(crate::FieldReader); +impl CC_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC` writer - Channel Compare/Capture Value"] +pub struct CC_W<'a> { + w: &'a mut W, +} +impl<'a> CC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&self) -> CC_R { + CC_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&mut self) -> CC_W { + CC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc](index.html) module"] +pub struct CC_SPEC; +impl crate::RegisterSpec for CC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cc::R](R) reader structure"] +impl crate::Readable for CC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cc::W](W) writer structure"] +impl crate::Writable for CC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CC[%s] +to value 0"] +impl crate::Resettable for CC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/tcc0/cc_dith4_mode.rs b/pac/atsamc20e/src/tcc0/cc_dith4_mode.rs new file mode 100644 index 000000000000..c45d8b6bac41 --- /dev/null +++ b/pac/atsamc20e/src/tcc0/cc_dith4_mode.rs @@ -0,0 +1,141 @@ +#[doc = "Register `CC_DITH4_MODE[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CC_DITH4_MODE[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHER` reader - Dithering Cycle Number"] +pub struct DITHER_R(crate::FieldReader); +impl DITHER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHER` writer - Dithering Cycle Number"] +pub struct DITHER_W<'a> { + w: &'a mut W, +} +impl<'a> DITHER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Field `CC` reader - Channel Compare/Capture Value"] +pub struct CC_R(crate::FieldReader); +impl CC_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC` writer - Channel Compare/Capture Value"] +pub struct CC_W<'a> { + w: &'a mut W, +} +impl<'a> CC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x000f_ffff << 4)) | ((value as u32 & 0x000f_ffff) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&self) -> DITHER_R { + DITHER_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&self) -> CC_R { + CC_R::new(((self.bits >> 4) & 0x000f_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:3 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&mut self) -> DITHER_W { + DITHER_W { w: self } + } + #[doc = "Bits 4:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&mut self) -> CC_W { + CC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc_dith4_mode](index.html) module"] +pub struct CC_DITH4_MODE_SPEC; +impl crate::RegisterSpec for CC_DITH4_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cc_dith4_mode::R](R) reader structure"] +impl crate::Readable for CC_DITH4_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cc_dith4_mode::W](W) writer structure"] +impl crate::Writable for CC_DITH4_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CC_DITH4_MODE[%s] +to value 0"] +impl crate::Resettable for CC_DITH4_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/tcc0/cc_dith5_mode.rs b/pac/atsamc20e/src/tcc0/cc_dith5_mode.rs new file mode 100644 index 000000000000..0592b923051a --- /dev/null +++ b/pac/atsamc20e/src/tcc0/cc_dith5_mode.rs @@ -0,0 +1,141 @@ +#[doc = "Register `CC_DITH5_MODE[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CC_DITH5_MODE[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHER` reader - Dithering Cycle Number"] +pub struct DITHER_R(crate::FieldReader); +impl DITHER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHER` writer - Dithering Cycle Number"] +pub struct DITHER_W<'a> { + w: &'a mut W, +} +impl<'a> DITHER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f); + self.w + } +} +#[doc = "Field `CC` reader - Channel Compare/Capture Value"] +pub struct CC_R(crate::FieldReader); +impl CC_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC` writer - Channel Compare/Capture Value"] +pub struct CC_W<'a> { + w: &'a mut W, +} +impl<'a> CC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0007_ffff << 5)) | ((value as u32 & 0x0007_ffff) << 5); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&self) -> DITHER_R { + DITHER_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&self) -> CC_R { + CC_R::new(((self.bits >> 5) & 0x0007_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:4 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&mut self) -> DITHER_W { + DITHER_W { w: self } + } + #[doc = "Bits 5:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&mut self) -> CC_W { + CC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc_dith5_mode](index.html) module"] +pub struct CC_DITH5_MODE_SPEC; +impl crate::RegisterSpec for CC_DITH5_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cc_dith5_mode::R](R) reader structure"] +impl crate::Readable for CC_DITH5_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cc_dith5_mode::W](W) writer structure"] +impl crate::Writable for CC_DITH5_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CC_DITH5_MODE[%s] +to value 0"] +impl crate::Resettable for CC_DITH5_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/tcc0/cc_dith6_mode.rs b/pac/atsamc20e/src/tcc0/cc_dith6_mode.rs new file mode 100644 index 000000000000..62a82a872426 --- /dev/null +++ b/pac/atsamc20e/src/tcc0/cc_dith6_mode.rs @@ -0,0 +1,141 @@ +#[doc = "Register `CC_DITH6_MODE[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CC_DITH6_MODE[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHER` reader - Dithering Cycle Number"] +pub struct DITHER_R(crate::FieldReader); +impl DITHER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHER` writer - Dithering Cycle Number"] +pub struct DITHER_W<'a> { + w: &'a mut W, +} +impl<'a> DITHER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +#[doc = "Field `CC` reader - Channel Compare/Capture Value"] +pub struct CC_R(crate::FieldReader); +impl CC_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC` writer - Channel Compare/Capture Value"] +pub struct CC_W<'a> { + w: &'a mut W, +} +impl<'a> CC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0003_ffff << 6)) | ((value as u32 & 0x0003_ffff) << 6); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&self) -> DITHER_R { + DITHER_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&self) -> CC_R { + CC_R::new(((self.bits >> 6) & 0x0003_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:5 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&mut self) -> DITHER_W { + DITHER_W { w: self } + } + #[doc = "Bits 6:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&mut self) -> CC_W { + CC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc_dith6_mode](index.html) module"] +pub struct CC_DITH6_MODE_SPEC; +impl crate::RegisterSpec for CC_DITH6_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cc_dith6_mode::R](R) reader structure"] +impl crate::Readable for CC_DITH6_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cc_dith6_mode::W](W) writer structure"] +impl crate::Writable for CC_DITH6_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CC_DITH6_MODE[%s] +to value 0"] +impl crate::Resettable for CC_DITH6_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/tcc0/ccbuf.rs b/pac/atsamc20e/src/tcc0/ccbuf.rs new file mode 100644 index 000000000000..a4db1135f095 --- /dev/null +++ b/pac/atsamc20e/src/tcc0/ccbuf.rs @@ -0,0 +1,104 @@ +#[doc = "Register `CCBUF[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CCBUF[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CCBUF` reader - Channel Compare/Capture Buffer Value"] +pub struct CCBUF_R(crate::FieldReader); +impl CCBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CCBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUF` writer - Channel Compare/Capture Buffer Value"] +pub struct CCBUF_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccbuf(&self) -> CCBUF_R { + CCBUF_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccbuf(&mut self) -> CCBUF_W { + CCBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccbuf](index.html) module"] +pub struct CCBUF_SPEC; +impl crate::RegisterSpec for CCBUF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ccbuf::R](R) reader structure"] +impl crate::Readable for CCBUF_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ccbuf::W](W) writer structure"] +impl crate::Writable for CCBUF_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CCBUF[%s] +to value 0"] +impl crate::Resettable for CCBUF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/tcc0/ccbuf_dith4_mode.rs b/pac/atsamc20e/src/tcc0/ccbuf_dith4_mode.rs new file mode 100644 index 000000000000..dfa16e936175 --- /dev/null +++ b/pac/atsamc20e/src/tcc0/ccbuf_dith4_mode.rs @@ -0,0 +1,141 @@ +#[doc = "Register `CCBUF_DITH4_MODE[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CCBUF_DITH4_MODE[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CCBUF` reader - Channel Compare/Capture Buffer Value"] +pub struct CCBUF_R(crate::FieldReader); +impl CCBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CCBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUF` writer - Channel Compare/Capture Buffer Value"] +pub struct CCBUF_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Field `DITHERBUF` reader - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_R(crate::FieldReader); +impl DITHERBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + DITHERBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHERBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHERBUF` writer - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_W<'a> { + w: &'a mut W, +} +impl<'a> DITHERBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x000f_ffff << 4)) | ((value as u32 & 0x000f_ffff) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccbuf(&self) -> CCBUF_R { + CCBUF_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:23 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&self) -> DITHERBUF_R { + DITHERBUF_R::new(((self.bits >> 4) & 0x000f_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:3 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccbuf(&mut self) -> CCBUF_W { + CCBUF_W { w: self } + } + #[doc = "Bits 4:23 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&mut self) -> DITHERBUF_W { + DITHERBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccbuf_dith4_mode](index.html) module"] +pub struct CCBUF_DITH4_MODE_SPEC; +impl crate::RegisterSpec for CCBUF_DITH4_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ccbuf_dith4_mode::R](R) reader structure"] +impl crate::Readable for CCBUF_DITH4_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ccbuf_dith4_mode::W](W) writer structure"] +impl crate::Writable for CCBUF_DITH4_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CCBUF_DITH4_MODE[%s] +to value 0"] +impl crate::Resettable for CCBUF_DITH4_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/tcc0/ccbuf_dith5_mode.rs b/pac/atsamc20e/src/tcc0/ccbuf_dith5_mode.rs new file mode 100644 index 000000000000..0c78ba3303c0 --- /dev/null +++ b/pac/atsamc20e/src/tcc0/ccbuf_dith5_mode.rs @@ -0,0 +1,141 @@ +#[doc = "Register `CCBUF_DITH5_MODE[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CCBUF_DITH5_MODE[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHERBUF` reader - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_R(crate::FieldReader); +impl DITHERBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHERBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHERBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHERBUF` writer - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_W<'a> { + w: &'a mut W, +} +impl<'a> DITHERBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f); + self.w + } +} +#[doc = "Field `CCBUF` reader - Channel Compare/Capture Buffer Value"] +pub struct CCBUF_R(crate::FieldReader); +impl CCBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CCBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUF` writer - Channel Compare/Capture Buffer Value"] +pub struct CCBUF_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0007_ffff << 5)) | ((value as u32 & 0x0007_ffff) << 5); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&self) -> DITHERBUF_R { + DITHERBUF_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:23 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccbuf(&self) -> CCBUF_R { + CCBUF_R::new(((self.bits >> 5) & 0x0007_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:4 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&mut self) -> DITHERBUF_W { + DITHERBUF_W { w: self } + } + #[doc = "Bits 5:23 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccbuf(&mut self) -> CCBUF_W { + CCBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccbuf_dith5_mode](index.html) module"] +pub struct CCBUF_DITH5_MODE_SPEC; +impl crate::RegisterSpec for CCBUF_DITH5_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ccbuf_dith5_mode::R](R) reader structure"] +impl crate::Readable for CCBUF_DITH5_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ccbuf_dith5_mode::W](W) writer structure"] +impl crate::Writable for CCBUF_DITH5_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CCBUF_DITH5_MODE[%s] +to value 0"] +impl crate::Resettable for CCBUF_DITH5_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/tcc0/ccbuf_dith6_mode.rs b/pac/atsamc20e/src/tcc0/ccbuf_dith6_mode.rs new file mode 100644 index 000000000000..8d19b8a9e595 --- /dev/null +++ b/pac/atsamc20e/src/tcc0/ccbuf_dith6_mode.rs @@ -0,0 +1,141 @@ +#[doc = "Register `CCBUF_DITH6_MODE[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CCBUF_DITH6_MODE[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHERBUF` reader - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_R(crate::FieldReader); +impl DITHERBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHERBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHERBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHERBUF` writer - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_W<'a> { + w: &'a mut W, +} +impl<'a> DITHERBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +#[doc = "Field `CCBUF` reader - Channel Compare/Capture Buffer Value"] +pub struct CCBUF_R(crate::FieldReader); +impl CCBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CCBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUF` writer - Channel Compare/Capture Buffer Value"] +pub struct CCBUF_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0003_ffff << 6)) | ((value as u32 & 0x0003_ffff) << 6); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&self) -> DITHERBUF_R { + DITHERBUF_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:23 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccbuf(&self) -> CCBUF_R { + CCBUF_R::new(((self.bits >> 6) & 0x0003_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:5 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&mut self) -> DITHERBUF_W { + DITHERBUF_W { w: self } + } + #[doc = "Bits 6:23 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccbuf(&mut self) -> CCBUF_W { + CCBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccbuf_dith6_mode](index.html) module"] +pub struct CCBUF_DITH6_MODE_SPEC; +impl crate::RegisterSpec for CCBUF_DITH6_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ccbuf_dith6_mode::R](R) reader structure"] +impl crate::Readable for CCBUF_DITH6_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ccbuf_dith6_mode::W](W) writer structure"] +impl crate::Writable for CCBUF_DITH6_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CCBUF_DITH6_MODE[%s] +to value 0"] +impl crate::Resettable for CCBUF_DITH6_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/tcc0/count.rs b/pac/atsamc20e/src/tcc0/count.rs new file mode 100644 index 000000000000..7628f2c0d5e1 --- /dev/null +++ b/pac/atsamc20e/src/tcc0/count.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Count\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count](index.html) module"] +pub struct COUNT_SPEC; +impl crate::RegisterSpec for COUNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [count::R](R) reader structure"] +impl crate::Readable for COUNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count::W](W) writer structure"] +impl crate::Writable for COUNT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT to value 0"] +impl crate::Resettable for COUNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/tcc0/count_dith4_mode.rs b/pac/atsamc20e/src/tcc0/count_dith4_mode.rs new file mode 100644 index 000000000000..fc058ae5efd5 --- /dev/null +++ b/pac/atsamc20e/src/tcc0/count_dith4_mode.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT_DITH4_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT_DITH4_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x000f_ffff << 4)) | ((value as u32 & 0x000f_ffff) << 4); + self.w + } +} +impl R { + #[doc = "Bits 4:23 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 4) & 0x000f_ffff) as u32) + } +} +impl W { + #[doc = "Bits 4:23 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Count\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count_dith4_mode](index.html) module"] +pub struct COUNT_DITH4_MODE_SPEC; +impl crate::RegisterSpec for COUNT_DITH4_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [count_dith4_mode::R](R) reader structure"] +impl crate::Readable for COUNT_DITH4_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count_dith4_mode::W](W) writer structure"] +impl crate::Writable for COUNT_DITH4_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT_DITH4_MODE to value 0"] +impl crate::Resettable for COUNT_DITH4_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/tcc0/count_dith5_mode.rs b/pac/atsamc20e/src/tcc0/count_dith5_mode.rs new file mode 100644 index 000000000000..e66e20310726 --- /dev/null +++ b/pac/atsamc20e/src/tcc0/count_dith5_mode.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT_DITH5_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT_DITH5_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0007_ffff << 5)) | ((value as u32 & 0x0007_ffff) << 5); + self.w + } +} +impl R { + #[doc = "Bits 5:23 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 5) & 0x0007_ffff) as u32) + } +} +impl W { + #[doc = "Bits 5:23 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Count\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count_dith5_mode](index.html) module"] +pub struct COUNT_DITH5_MODE_SPEC; +impl crate::RegisterSpec for COUNT_DITH5_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [count_dith5_mode::R](R) reader structure"] +impl crate::Readable for COUNT_DITH5_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count_dith5_mode::W](W) writer structure"] +impl crate::Writable for COUNT_DITH5_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT_DITH5_MODE to value 0"] +impl crate::Resettable for COUNT_DITH5_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/tcc0/count_dith6_mode.rs b/pac/atsamc20e/src/tcc0/count_dith6_mode.rs new file mode 100644 index 000000000000..5410fc6c9459 --- /dev/null +++ b/pac/atsamc20e/src/tcc0/count_dith6_mode.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT_DITH6_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT_DITH6_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0003_ffff << 6)) | ((value as u32 & 0x0003_ffff) << 6); + self.w + } +} +impl R { + #[doc = "Bits 6:23 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 6) & 0x0003_ffff) as u32) + } +} +impl W { + #[doc = "Bits 6:23 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Count\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count_dith6_mode](index.html) module"] +pub struct COUNT_DITH6_MODE_SPEC; +impl crate::RegisterSpec for COUNT_DITH6_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [count_dith6_mode::R](R) reader structure"] +impl crate::Readable for COUNT_DITH6_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count_dith6_mode::W](W) writer structure"] +impl crate::Writable for COUNT_DITH6_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT_DITH6_MODE to value 0"] +impl crate::Resettable for COUNT_DITH6_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/tcc0/ctrla.rs b/pac/atsamc20e/src/tcc0/ctrla.rs new file mode 100644 index 000000000000..b717d1ac6ae0 --- /dev/null +++ b/pac/atsamc20e/src/tcc0/ctrla.rs @@ -0,0 +1,911 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Enhanced Resolution\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum RESOLUTION_A { + #[doc = "0: Dithering is disabled"] + NONE = 0, + #[doc = "1: Dithering is done every 16 PWM frames"] + DITH4 = 1, + #[doc = "2: Dithering is done every 32 PWM frames"] + DITH5 = 2, + #[doc = "3: Dithering is done every 64 PWM frames"] + DITH6 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RESOLUTION_A) -> Self { + variant as _ + } +} +#[doc = "Field `RESOLUTION` reader - Enhanced Resolution"] +pub struct RESOLUTION_R(crate::FieldReader); +impl RESOLUTION_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RESOLUTION_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RESOLUTION_A { + match self.bits { + 0 => RESOLUTION_A::NONE, + 1 => RESOLUTION_A::DITH4, + 2 => RESOLUTION_A::DITH5, + 3 => RESOLUTION_A::DITH6, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == RESOLUTION_A::NONE + } + #[doc = "Checks if the value of the field is `DITH4`"] + #[inline(always)] + pub fn is_dith4(&self) -> bool { + **self == RESOLUTION_A::DITH4 + } + #[doc = "Checks if the value of the field is `DITH5`"] + #[inline(always)] + pub fn is_dith5(&self) -> bool { + **self == RESOLUTION_A::DITH5 + } + #[doc = "Checks if the value of the field is `DITH6`"] + #[inline(always)] + pub fn is_dith6(&self) -> bool { + **self == RESOLUTION_A::DITH6 + } +} +impl core::ops::Deref for RESOLUTION_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESOLUTION` writer - Enhanced Resolution"] +pub struct RESOLUTION_W<'a> { + w: &'a mut W, +} +impl<'a> RESOLUTION_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RESOLUTION_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Dithering is disabled"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(RESOLUTION_A::NONE) + } + #[doc = "Dithering is done every 16 PWM frames"] + #[inline(always)] + pub fn dith4(self) -> &'a mut W { + self.variant(RESOLUTION_A::DITH4) + } + #[doc = "Dithering is done every 32 PWM frames"] + #[inline(always)] + pub fn dith5(self) -> &'a mut W { + self.variant(RESOLUTION_A::DITH5) + } + #[doc = "Dithering is done every 64 PWM frames"] + #[inline(always)] + pub fn dith6(self) -> &'a mut W { + self.variant(RESOLUTION_A::DITH6) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 5)) | ((value as u32 & 0x03) << 5); + self.w + } +} +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: No division"] + DIV1 = 0, + #[doc = "1: Divide by 2"] + DIV2 = 1, + #[doc = "2: Divide by 4"] + DIV4 = 2, + #[doc = "3: Divide by 8"] + DIV8 = 3, + #[doc = "4: Divide by 16"] + DIV16 = 4, + #[doc = "5: Divide by 64"] + DIV64 = 5, + #[doc = "6: Divide by 256"] + DIV256 = 6, + #[doc = "7: Divide by 1024"] + DIV1024 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PRESCALER_A { + match self.bits { + 0 => PRESCALER_A::DIV1, + 1 => PRESCALER_A::DIV2, + 2 => PRESCALER_A::DIV4, + 3 => PRESCALER_A::DIV8, + 4 => PRESCALER_A::DIV16, + 5 => PRESCALER_A::DIV64, + 6 => PRESCALER_A::DIV256, + 7 => PRESCALER_A::DIV1024, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == PRESCALER_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PRESCALER_A::DIV1024 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "No division"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1) + } + #[doc = "Divide by 2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "Divide by 4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "Divide by 8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "Divide by 16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "Divide by 64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "Divide by 256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = "Divide by 1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Prescaler and Counter Synchronization Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCSYNC_A { + #[doc = "0: Reload or reset counter on next GCLK"] + GCLK = 0, + #[doc = "1: Reload or reset counter on next prescaler clock"] + PRESC = 1, + #[doc = "2: Reload or reset counter on next GCLK and reset prescaler counter"] + RESYNC = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCSYNC_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCSYNC` reader - Prescaler and Counter Synchronization Selection"] +pub struct PRESCSYNC_R(crate::FieldReader); +impl PRESCSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCSYNC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCSYNC_A::GCLK), + 1 => Some(PRESCSYNC_A::PRESC), + 2 => Some(PRESCSYNC_A::RESYNC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `GCLK`"] + #[inline(always)] + pub fn is_gclk(&self) -> bool { + **self == PRESCSYNC_A::GCLK + } + #[doc = "Checks if the value of the field is `PRESC`"] + #[inline(always)] + pub fn is_presc(&self) -> bool { + **self == PRESCSYNC_A::PRESC + } + #[doc = "Checks if the value of the field is `RESYNC`"] + #[inline(always)] + pub fn is_resync(&self) -> bool { + **self == PRESCSYNC_A::RESYNC + } +} +impl core::ops::Deref for PRESCSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCSYNC` writer - Prescaler and Counter Synchronization Selection"] +pub struct PRESCSYNC_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCSYNC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCSYNC_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Reload or reset counter on next GCLK"] + #[inline(always)] + pub fn gclk(self) -> &'a mut W { + self.variant(PRESCSYNC_A::GCLK) + } + #[doc = "Reload or reset counter on next prescaler clock"] + #[inline(always)] + pub fn presc(self) -> &'a mut W { + self.variant(PRESCSYNC_A::PRESC) + } + #[doc = "Reload or reset counter on next GCLK and reset prescaler counter"] + #[inline(always)] + pub fn resync(self) -> &'a mut W { + self.variant(PRESCSYNC_A::RESYNC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 12)) | ((value as u32 & 0x03) << 12); + self.w + } +} +#[doc = "Field `ALOCK` reader - Auto Lock"] +pub struct ALOCK_R(crate::FieldReader); +impl ALOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALOCK` writer - Auto Lock"] +pub struct ALOCK_W<'a> { + w: &'a mut W, +} +impl<'a> ALOCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `MSYNC` reader - Master Synchronization (only for TCC Slave Instance)"] +pub struct MSYNC_R(crate::FieldReader); +impl MSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MSYNC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MSYNC` writer - Master Synchronization (only for TCC Slave Instance)"] +pub struct MSYNC_W<'a> { + w: &'a mut W, +} +impl<'a> MSYNC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `DMAOS` reader - DMA One-shot Trigger Mode"] +pub struct DMAOS_R(crate::FieldReader); +impl DMAOS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DMAOS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DMAOS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DMAOS` writer - DMA One-shot Trigger Mode"] +pub struct DMAOS_W<'a> { + w: &'a mut W, +} +impl<'a> DMAOS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `CPTEN0` reader - Capture Channel 0 Enable"] +pub struct CPTEN0_R(crate::FieldReader); +impl CPTEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPTEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CPTEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPTEN0` writer - Capture Channel 0 Enable"] +pub struct CPTEN0_W<'a> { + w: &'a mut W, +} +impl<'a> CPTEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `CPTEN1` reader - Capture Channel 1 Enable"] +pub struct CPTEN1_R(crate::FieldReader); +impl CPTEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPTEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CPTEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPTEN1` writer - Capture Channel 1 Enable"] +pub struct CPTEN1_W<'a> { + w: &'a mut W, +} +impl<'a> CPTEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `CPTEN2` reader - Capture Channel 2 Enable"] +pub struct CPTEN2_R(crate::FieldReader); +impl CPTEN2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPTEN2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CPTEN2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPTEN2` writer - Capture Channel 2 Enable"] +pub struct CPTEN2_W<'a> { + w: &'a mut W, +} +impl<'a> CPTEN2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `CPTEN3` reader - Capture Channel 3 Enable"] +pub struct CPTEN3_R(crate::FieldReader); +impl CPTEN3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPTEN3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CPTEN3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPTEN3` writer - Capture Channel 3 Enable"] +pub struct CPTEN3_W<'a> { + w: &'a mut W, +} +impl<'a> CPTEN3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 5:6 - Enhanced Resolution"] + #[inline(always)] + pub fn resolution(&self) -> RESOLUTION_R { + RESOLUTION_R::new(((self.bits >> 5) & 0x03) as u8) + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 11 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bits 12:13 - Prescaler and Counter Synchronization Selection"] + #[inline(always)] + pub fn prescsync(&self) -> PRESCSYNC_R { + PRESCSYNC_R::new(((self.bits >> 12) & 0x03) as u8) + } + #[doc = "Bit 14 - Auto Lock"] + #[inline(always)] + pub fn alock(&self) -> ALOCK_R { + ALOCK_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Master Synchronization (only for TCC Slave Instance)"] + #[inline(always)] + pub fn msync(&self) -> MSYNC_R { + MSYNC_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 23 - DMA One-shot Trigger Mode"] + #[inline(always)] + pub fn dmaos(&self) -> DMAOS_R { + DMAOS_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn cpten0(&self) -> CPTEN0_R { + CPTEN0_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn cpten1(&self) -> CPTEN1_R { + CPTEN1_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Capture Channel 2 Enable"] + #[inline(always)] + pub fn cpten2(&self) -> CPTEN2_R { + CPTEN2_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Capture Channel 3 Enable"] + #[inline(always)] + pub fn cpten3(&self) -> CPTEN3_R { + CPTEN3_R::new(((self.bits >> 27) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 5:6 - Enhanced Resolution"] + #[inline(always)] + pub fn resolution(&mut self) -> RESOLUTION_W { + RESOLUTION_W { w: self } + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Bit 11 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bits 12:13 - Prescaler and Counter Synchronization Selection"] + #[inline(always)] + pub fn prescsync(&mut self) -> PRESCSYNC_W { + PRESCSYNC_W { w: self } + } + #[doc = "Bit 14 - Auto Lock"] + #[inline(always)] + pub fn alock(&mut self) -> ALOCK_W { + ALOCK_W { w: self } + } + #[doc = "Bit 15 - Master Synchronization (only for TCC Slave Instance)"] + #[inline(always)] + pub fn msync(&mut self) -> MSYNC_W { + MSYNC_W { w: self } + } + #[doc = "Bit 23 - DMA One-shot Trigger Mode"] + #[inline(always)] + pub fn dmaos(&mut self) -> DMAOS_W { + DMAOS_W { w: self } + } + #[doc = "Bit 24 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn cpten0(&mut self) -> CPTEN0_W { + CPTEN0_W { w: self } + } + #[doc = "Bit 25 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn cpten1(&mut self) -> CPTEN1_W { + CPTEN1_W { w: self } + } + #[doc = "Bit 26 - Capture Channel 2 Enable"] + #[inline(always)] + pub fn cpten2(&mut self) -> CPTEN2_W { + CPTEN2_W { w: self } + } + #[doc = "Bit 27 - Capture Channel 3 Enable"] + #[inline(always)] + pub fn cpten3(&mut self) -> CPTEN3_W { + CPTEN3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/tcc0/ctrlbclr.rs b/pac/atsamc20e/src/tcc0/ctrlbclr.rs new file mode 100644 index 000000000000..f96ce81ffde3 --- /dev/null +++ b/pac/atsamc20e/src/tcc0/ctrlbclr.rs @@ -0,0 +1,457 @@ +#[doc = "Register `CTRLBCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Counter Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `LUPD` reader - Lock Update"] +pub struct LUPD_R(crate::FieldReader); +impl LUPD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LUPD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LUPD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LUPD` writer - Lock Update"] +pub struct LUPD_W<'a> { + w: &'a mut W, +} +impl<'a> LUPD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ONESHOT` reader - One-Shot"] +pub struct ONESHOT_R(crate::FieldReader); +impl ONESHOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONESHOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONESHOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONESHOT` writer - One-Shot"] +pub struct ONESHOT_W<'a> { + w: &'a mut W, +} +impl<'a> ONESHOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Ramp Index Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum IDXCMD_A { + #[doc = "0: Command disabled: Index toggles between cycles A and B"] + DISABLE = 0, + #[doc = "1: Set index: cycle B will be forced in the next cycle"] + SET = 1, + #[doc = "2: Clear index: cycle A will be forced in the next cycle"] + CLEAR = 2, + #[doc = "3: Hold index: the next cycle will be the same as the current cycle"] + HOLD = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: IDXCMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `IDXCMD` reader - Ramp Index Command"] +pub struct IDXCMD_R(crate::FieldReader); +impl IDXCMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + IDXCMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> IDXCMD_A { + match self.bits { + 0 => IDXCMD_A::DISABLE, + 1 => IDXCMD_A::SET, + 2 => IDXCMD_A::CLEAR, + 3 => IDXCMD_A::HOLD, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == IDXCMD_A::DISABLE + } + #[doc = "Checks if the value of the field is `SET`"] + #[inline(always)] + pub fn is_set(&self) -> bool { + **self == IDXCMD_A::SET + } + #[doc = "Checks if the value of the field is `CLEAR`"] + #[inline(always)] + pub fn is_clear(&self) -> bool { + **self == IDXCMD_A::CLEAR + } + #[doc = "Checks if the value of the field is `HOLD`"] + #[inline(always)] + pub fn is_hold(&self) -> bool { + **self == IDXCMD_A::HOLD + } +} +impl core::ops::Deref for IDXCMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IDXCMD` writer - Ramp Index Command"] +pub struct IDXCMD_W<'a> { + w: &'a mut W, +} +impl<'a> IDXCMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: IDXCMD_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Command disabled: Index toggles between cycles A and B"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(IDXCMD_A::DISABLE) + } + #[doc = "Set index: cycle B will be forced in the next cycle"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(IDXCMD_A::SET) + } + #[doc = "Clear index: cycle A will be forced in the next cycle"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(IDXCMD_A::CLEAR) + } + #[doc = "Hold index: the next cycle will be the same as the current cycle"] + #[inline(always)] + pub fn hold(self) -> &'a mut W { + self.variant(IDXCMD_A::HOLD) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 3)) | ((value as u8 & 0x03) << 3); + self.w + } +} +#[doc = "TCC Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Clear start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force stop"] + STOP = 2, + #[doc = "3: Force update or double buffered registers"] + UPDATE = 3, + #[doc = "4: Force COUNT read synchronization"] + READSYNC = 4, + #[doc = "5: One-shot DMA trigger"] + DMAOS = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - TCC Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NONE), + 1 => Some(CMD_A::RETRIGGER), + 2 => Some(CMD_A::STOP), + 3 => Some(CMD_A::UPDATE), + 4 => Some(CMD_A::READSYNC), + 5 => Some(CMD_A::DMAOS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == CMD_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == CMD_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == CMD_A::STOP + } + #[doc = "Checks if the value of the field is `UPDATE`"] + #[inline(always)] + pub fn is_update(&self) -> bool { + **self == CMD_A::UPDATE + } + #[doc = "Checks if the value of the field is `READSYNC`"] + #[inline(always)] + pub fn is_readsync(&self) -> bool { + **self == CMD_A::READSYNC + } + #[doc = "Checks if the value of the field is `DMAOS`"] + #[inline(always)] + pub fn is_dmaos(&self) -> bool { + **self == CMD_A::DMAOS + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - TCC Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMD_A::NONE) + } + #[doc = "Clear start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMD_A::RETRIGGER) + } + #[doc = "Force stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMD_A::STOP) + } + #[doc = "Force update or double buffered registers"] + #[inline(always)] + pub fn update(self) -> &'a mut W { + self.variant(CMD_A::UPDATE) + } + #[doc = "Force COUNT read synchronization"] + #[inline(always)] + pub fn readsync(self) -> &'a mut W { + self.variant(CMD_A::READSYNC) + } + #[doc = "One-shot DMA trigger"] + #[inline(always)] + pub fn dmaos(self) -> &'a mut W { + self.variant(CMD_A::DMAOS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 5)) | ((value as u8 & 0x07) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&self) -> LUPD_R { + LUPD_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - One-Shot"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 3:4 - Ramp Index Command"] + #[inline(always)] + pub fn idxcmd(&self) -> IDXCMD_R { + IDXCMD_R::new(((self.bits >> 3) & 0x03) as u8) + } + #[doc = "Bits 5:7 - TCC Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 5) & 0x07) as u8) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&mut self) -> LUPD_W { + LUPD_W { w: self } + } + #[doc = "Bit 2 - One-Shot"] + #[inline(always)] + pub fn oneshot(&mut self) -> ONESHOT_W { + ONESHOT_W { w: self } + } + #[doc = "Bits 3:4 - Ramp Index Command"] + #[inline(always)] + pub fn idxcmd(&mut self) -> IDXCMD_W { + IDXCMD_W { w: self } + } + #[doc = "Bits 5:7 - TCC Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbclr](index.html) module"] +pub struct CTRLBCLR_SPEC; +impl crate::RegisterSpec for CTRLBCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbclr::R](R) reader structure"] +impl crate::Readable for CTRLBCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbclr::W](W) writer structure"] +impl crate::Writable for CTRLBCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLBCLR to value 0"] +impl crate::Resettable for CTRLBCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/tcc0/ctrlbset.rs b/pac/atsamc20e/src/tcc0/ctrlbset.rs new file mode 100644 index 000000000000..7002dd71efe7 --- /dev/null +++ b/pac/atsamc20e/src/tcc0/ctrlbset.rs @@ -0,0 +1,457 @@ +#[doc = "Register `CTRLBSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Counter Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `LUPD` reader - Lock Update"] +pub struct LUPD_R(crate::FieldReader); +impl LUPD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LUPD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LUPD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LUPD` writer - Lock Update"] +pub struct LUPD_W<'a> { + w: &'a mut W, +} +impl<'a> LUPD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ONESHOT` reader - One-Shot"] +pub struct ONESHOT_R(crate::FieldReader); +impl ONESHOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONESHOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONESHOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONESHOT` writer - One-Shot"] +pub struct ONESHOT_W<'a> { + w: &'a mut W, +} +impl<'a> ONESHOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Ramp Index Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum IDXCMD_A { + #[doc = "0: Command disabled: Index toggles between cycles A and B"] + DISABLE = 0, + #[doc = "1: Set index: cycle B will be forced in the next cycle"] + SET = 1, + #[doc = "2: Clear index: cycle A will be forced in the next cycle"] + CLEAR = 2, + #[doc = "3: Hold index: the next cycle will be the same as the current cycle"] + HOLD = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: IDXCMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `IDXCMD` reader - Ramp Index Command"] +pub struct IDXCMD_R(crate::FieldReader); +impl IDXCMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + IDXCMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> IDXCMD_A { + match self.bits { + 0 => IDXCMD_A::DISABLE, + 1 => IDXCMD_A::SET, + 2 => IDXCMD_A::CLEAR, + 3 => IDXCMD_A::HOLD, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == IDXCMD_A::DISABLE + } + #[doc = "Checks if the value of the field is `SET`"] + #[inline(always)] + pub fn is_set(&self) -> bool { + **self == IDXCMD_A::SET + } + #[doc = "Checks if the value of the field is `CLEAR`"] + #[inline(always)] + pub fn is_clear(&self) -> bool { + **self == IDXCMD_A::CLEAR + } + #[doc = "Checks if the value of the field is `HOLD`"] + #[inline(always)] + pub fn is_hold(&self) -> bool { + **self == IDXCMD_A::HOLD + } +} +impl core::ops::Deref for IDXCMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IDXCMD` writer - Ramp Index Command"] +pub struct IDXCMD_W<'a> { + w: &'a mut W, +} +impl<'a> IDXCMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: IDXCMD_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Command disabled: Index toggles between cycles A and B"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(IDXCMD_A::DISABLE) + } + #[doc = "Set index: cycle B will be forced in the next cycle"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(IDXCMD_A::SET) + } + #[doc = "Clear index: cycle A will be forced in the next cycle"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(IDXCMD_A::CLEAR) + } + #[doc = "Hold index: the next cycle will be the same as the current cycle"] + #[inline(always)] + pub fn hold(self) -> &'a mut W { + self.variant(IDXCMD_A::HOLD) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 3)) | ((value as u8 & 0x03) << 3); + self.w + } +} +#[doc = "TCC Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Clear start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force stop"] + STOP = 2, + #[doc = "3: Force update or double buffered registers"] + UPDATE = 3, + #[doc = "4: Force COUNT read synchronization"] + READSYNC = 4, + #[doc = "5: One-shot DMA trigger"] + DMAOS = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - TCC Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NONE), + 1 => Some(CMD_A::RETRIGGER), + 2 => Some(CMD_A::STOP), + 3 => Some(CMD_A::UPDATE), + 4 => Some(CMD_A::READSYNC), + 5 => Some(CMD_A::DMAOS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == CMD_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == CMD_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == CMD_A::STOP + } + #[doc = "Checks if the value of the field is `UPDATE`"] + #[inline(always)] + pub fn is_update(&self) -> bool { + **self == CMD_A::UPDATE + } + #[doc = "Checks if the value of the field is `READSYNC`"] + #[inline(always)] + pub fn is_readsync(&self) -> bool { + **self == CMD_A::READSYNC + } + #[doc = "Checks if the value of the field is `DMAOS`"] + #[inline(always)] + pub fn is_dmaos(&self) -> bool { + **self == CMD_A::DMAOS + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - TCC Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMD_A::NONE) + } + #[doc = "Clear start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMD_A::RETRIGGER) + } + #[doc = "Force stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMD_A::STOP) + } + #[doc = "Force update or double buffered registers"] + #[inline(always)] + pub fn update(self) -> &'a mut W { + self.variant(CMD_A::UPDATE) + } + #[doc = "Force COUNT read synchronization"] + #[inline(always)] + pub fn readsync(self) -> &'a mut W { + self.variant(CMD_A::READSYNC) + } + #[doc = "One-shot DMA trigger"] + #[inline(always)] + pub fn dmaos(self) -> &'a mut W { + self.variant(CMD_A::DMAOS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 5)) | ((value as u8 & 0x07) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&self) -> LUPD_R { + LUPD_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - One-Shot"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 3:4 - Ramp Index Command"] + #[inline(always)] + pub fn idxcmd(&self) -> IDXCMD_R { + IDXCMD_R::new(((self.bits >> 3) & 0x03) as u8) + } + #[doc = "Bits 5:7 - TCC Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 5) & 0x07) as u8) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&mut self) -> LUPD_W { + LUPD_W { w: self } + } + #[doc = "Bit 2 - One-Shot"] + #[inline(always)] + pub fn oneshot(&mut self) -> ONESHOT_W { + ONESHOT_W { w: self } + } + #[doc = "Bits 3:4 - Ramp Index Command"] + #[inline(always)] + pub fn idxcmd(&mut self) -> IDXCMD_W { + IDXCMD_W { w: self } + } + #[doc = "Bits 5:7 - TCC Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbset](index.html) module"] +pub struct CTRLBSET_SPEC; +impl crate::RegisterSpec for CTRLBSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbset::R](R) reader structure"] +impl crate::Readable for CTRLBSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbset::W](W) writer structure"] +impl crate::Writable for CTRLBSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLBSET to value 0"] +impl crate::Resettable for CTRLBSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/tcc0/dbgctrl.rs b/pac/atsamc20e/src/tcc0/dbgctrl.rs new file mode 100644 index 000000000000..313ebe3f5c18 --- /dev/null +++ b/pac/atsamc20e/src/tcc0/dbgctrl.rs @@ -0,0 +1,160 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Debug Running Mode"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Debug Running Mode"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `FDDBD` reader - Fault Detection on Debug Break Detection"] +pub struct FDDBD_R(crate::FieldReader); +impl FDDBD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FDDBD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FDDBD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FDDBD` writer - Fault Detection on Debug Break Detection"] +pub struct FDDBD_W<'a> { + w: &'a mut W, +} +impl<'a> FDDBD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Running Mode"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 2 - Fault Detection on Debug Break Detection"] + #[inline(always)] + pub fn fddbd(&self) -> FDDBD_R { + FDDBD_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Running Mode"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Bit 2 - Fault Detection on Debug Break Detection"] + #[inline(always)] + pub fn fddbd(&mut self) -> FDDBD_W { + FDDBD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/tcc0/drvctrl.rs b/pac/atsamc20e/src/tcc0/drvctrl.rs new file mode 100644 index 000000000000..316041e1e3be --- /dev/null +++ b/pac/atsamc20e/src/tcc0/drvctrl.rs @@ -0,0 +1,1268 @@ +#[doc = "Register `DRVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DRVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `NRE0` reader - Non-Recoverable State 0 Output Enable"] +pub struct NRE0_R(crate::FieldReader); +impl NRE0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRE0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRE0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRE0` writer - Non-Recoverable State 0 Output Enable"] +pub struct NRE0_W<'a> { + w: &'a mut W, +} +impl<'a> NRE0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `NRE1` reader - Non-Recoverable State 1 Output Enable"] +pub struct NRE1_R(crate::FieldReader); +impl NRE1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRE1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRE1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRE1` writer - Non-Recoverable State 1 Output Enable"] +pub struct NRE1_W<'a> { + w: &'a mut W, +} +impl<'a> NRE1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `NRE2` reader - Non-Recoverable State 2 Output Enable"] +pub struct NRE2_R(crate::FieldReader); +impl NRE2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRE2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRE2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRE2` writer - Non-Recoverable State 2 Output Enable"] +pub struct NRE2_W<'a> { + w: &'a mut W, +} +impl<'a> NRE2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `NRE3` reader - Non-Recoverable State 3 Output Enable"] +pub struct NRE3_R(crate::FieldReader); +impl NRE3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRE3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRE3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRE3` writer - Non-Recoverable State 3 Output Enable"] +pub struct NRE3_W<'a> { + w: &'a mut W, +} +impl<'a> NRE3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `NRE4` reader - Non-Recoverable State 4 Output Enable"] +pub struct NRE4_R(crate::FieldReader); +impl NRE4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRE4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRE4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRE4` writer - Non-Recoverable State 4 Output Enable"] +pub struct NRE4_W<'a> { + w: &'a mut W, +} +impl<'a> NRE4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `NRE5` reader - Non-Recoverable State 5 Output Enable"] +pub struct NRE5_R(crate::FieldReader); +impl NRE5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRE5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRE5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRE5` writer - Non-Recoverable State 5 Output Enable"] +pub struct NRE5_W<'a> { + w: &'a mut W, +} +impl<'a> NRE5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `NRE6` reader - Non-Recoverable State 6 Output Enable"] +pub struct NRE6_R(crate::FieldReader); +impl NRE6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRE6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRE6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRE6` writer - Non-Recoverable State 6 Output Enable"] +pub struct NRE6_W<'a> { + w: &'a mut W, +} +impl<'a> NRE6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `NRE7` reader - Non-Recoverable State 7 Output Enable"] +pub struct NRE7_R(crate::FieldReader); +impl NRE7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRE7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRE7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRE7` writer - Non-Recoverable State 7 Output Enable"] +pub struct NRE7_W<'a> { + w: &'a mut W, +} +impl<'a> NRE7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `NRV0` reader - Non-Recoverable State 0 Output Value"] +pub struct NRV0_R(crate::FieldReader); +impl NRV0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRV0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRV0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRV0` writer - Non-Recoverable State 0 Output Value"] +pub struct NRV0_W<'a> { + w: &'a mut W, +} +impl<'a> NRV0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `NRV1` reader - Non-Recoverable State 1 Output Value"] +pub struct NRV1_R(crate::FieldReader); +impl NRV1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRV1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRV1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRV1` writer - Non-Recoverable State 1 Output Value"] +pub struct NRV1_W<'a> { + w: &'a mut W, +} +impl<'a> NRV1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `NRV2` reader - Non-Recoverable State 2 Output Value"] +pub struct NRV2_R(crate::FieldReader); +impl NRV2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRV2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRV2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRV2` writer - Non-Recoverable State 2 Output Value"] +pub struct NRV2_W<'a> { + w: &'a mut W, +} +impl<'a> NRV2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `NRV3` reader - Non-Recoverable State 3 Output Value"] +pub struct NRV3_R(crate::FieldReader); +impl NRV3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRV3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRV3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRV3` writer - Non-Recoverable State 3 Output Value"] +pub struct NRV3_W<'a> { + w: &'a mut W, +} +impl<'a> NRV3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `NRV4` reader - Non-Recoverable State 4 Output Value"] +pub struct NRV4_R(crate::FieldReader); +impl NRV4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRV4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRV4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRV4` writer - Non-Recoverable State 4 Output Value"] +pub struct NRV4_W<'a> { + w: &'a mut W, +} +impl<'a> NRV4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `NRV5` reader - Non-Recoverable State 5 Output Value"] +pub struct NRV5_R(crate::FieldReader); +impl NRV5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRV5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRV5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRV5` writer - Non-Recoverable State 5 Output Value"] +pub struct NRV5_W<'a> { + w: &'a mut W, +} +impl<'a> NRV5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `NRV6` reader - Non-Recoverable State 6 Output Value"] +pub struct NRV6_R(crate::FieldReader); +impl NRV6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRV6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRV6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRV6` writer - Non-Recoverable State 6 Output Value"] +pub struct NRV6_W<'a> { + w: &'a mut W, +} +impl<'a> NRV6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `NRV7` reader - Non-Recoverable State 7 Output Value"] +pub struct NRV7_R(crate::FieldReader); +impl NRV7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRV7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRV7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRV7` writer - Non-Recoverable State 7 Output Value"] +pub struct NRV7_W<'a> { + w: &'a mut W, +} +impl<'a> NRV7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `INVEN0` reader - Output Waveform 0 Inversion"] +pub struct INVEN0_R(crate::FieldReader); +impl INVEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN0` writer - Output Waveform 0 Inversion"] +pub struct INVEN0_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `INVEN1` reader - Output Waveform 1 Inversion"] +pub struct INVEN1_R(crate::FieldReader); +impl INVEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN1` writer - Output Waveform 1 Inversion"] +pub struct INVEN1_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `INVEN2` reader - Output Waveform 2 Inversion"] +pub struct INVEN2_R(crate::FieldReader); +impl INVEN2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN2` writer - Output Waveform 2 Inversion"] +pub struct INVEN2_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `INVEN3` reader - Output Waveform 3 Inversion"] +pub struct INVEN3_R(crate::FieldReader); +impl INVEN3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN3` writer - Output Waveform 3 Inversion"] +pub struct INVEN3_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `INVEN4` reader - Output Waveform 4 Inversion"] +pub struct INVEN4_R(crate::FieldReader); +impl INVEN4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN4` writer - Output Waveform 4 Inversion"] +pub struct INVEN4_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `INVEN5` reader - Output Waveform 5 Inversion"] +pub struct INVEN5_R(crate::FieldReader); +impl INVEN5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN5` writer - Output Waveform 5 Inversion"] +pub struct INVEN5_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `INVEN6` reader - Output Waveform 6 Inversion"] +pub struct INVEN6_R(crate::FieldReader); +impl INVEN6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN6` writer - Output Waveform 6 Inversion"] +pub struct INVEN6_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `INVEN7` reader - Output Waveform 7 Inversion"] +pub struct INVEN7_R(crate::FieldReader); +impl INVEN7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN7` writer - Output Waveform 7 Inversion"] +pub struct INVEN7_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `FILTERVAL0` reader - Non-Recoverable Fault Input 0 Filter Value"] +pub struct FILTERVAL0_R(crate::FieldReader); +impl FILTERVAL0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FILTERVAL0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTERVAL0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTERVAL0` writer - Non-Recoverable Fault Input 0 Filter Value"] +pub struct FILTERVAL0_W<'a> { + w: &'a mut W, +} +impl<'a> FILTERVAL0_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Field `FILTERVAL1` reader - Non-Recoverable Fault Input 1 Filter Value"] +pub struct FILTERVAL1_R(crate::FieldReader); +impl FILTERVAL1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FILTERVAL1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTERVAL1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTERVAL1` writer - Non-Recoverable Fault Input 1 Filter Value"] +pub struct FILTERVAL1_W<'a> { + w: &'a mut W, +} +impl<'a> FILTERVAL1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 28)) | ((value as u32 & 0x0f) << 28); + self.w + } +} +impl R { + #[doc = "Bit 0 - Non-Recoverable State 0 Output Enable"] + #[inline(always)] + pub fn nre0(&self) -> NRE0_R { + NRE0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Non-Recoverable State 1 Output Enable"] + #[inline(always)] + pub fn nre1(&self) -> NRE1_R { + NRE1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Non-Recoverable State 2 Output Enable"] + #[inline(always)] + pub fn nre2(&self) -> NRE2_R { + NRE2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Non-Recoverable State 3 Output Enable"] + #[inline(always)] + pub fn nre3(&self) -> NRE3_R { + NRE3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Non-Recoverable State 4 Output Enable"] + #[inline(always)] + pub fn nre4(&self) -> NRE4_R { + NRE4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Non-Recoverable State 5 Output Enable"] + #[inline(always)] + pub fn nre5(&self) -> NRE5_R { + NRE5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Non-Recoverable State 6 Output Enable"] + #[inline(always)] + pub fn nre6(&self) -> NRE6_R { + NRE6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Non-Recoverable State 7 Output Enable"] + #[inline(always)] + pub fn nre7(&self) -> NRE7_R { + NRE7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Non-Recoverable State 0 Output Value"] + #[inline(always)] + pub fn nrv0(&self) -> NRV0_R { + NRV0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Non-Recoverable State 1 Output Value"] + #[inline(always)] + pub fn nrv1(&self) -> NRV1_R { + NRV1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Non-Recoverable State 2 Output Value"] + #[inline(always)] + pub fn nrv2(&self) -> NRV2_R { + NRV2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Non-Recoverable State 3 Output Value"] + #[inline(always)] + pub fn nrv3(&self) -> NRV3_R { + NRV3_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Non-Recoverable State 4 Output Value"] + #[inline(always)] + pub fn nrv4(&self) -> NRV4_R { + NRV4_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Non-Recoverable State 5 Output Value"] + #[inline(always)] + pub fn nrv5(&self) -> NRV5_R { + NRV5_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Non-Recoverable State 6 Output Value"] + #[inline(always)] + pub fn nrv6(&self) -> NRV6_R { + NRV6_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Non-Recoverable State 7 Output Value"] + #[inline(always)] + pub fn nrv7(&self) -> NRV7_R { + NRV7_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Output Waveform 0 Inversion"] + #[inline(always)] + pub fn inven0(&self) -> INVEN0_R { + INVEN0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Output Waveform 1 Inversion"] + #[inline(always)] + pub fn inven1(&self) -> INVEN1_R { + INVEN1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Output Waveform 2 Inversion"] + #[inline(always)] + pub fn inven2(&self) -> INVEN2_R { + INVEN2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Output Waveform 3 Inversion"] + #[inline(always)] + pub fn inven3(&self) -> INVEN3_R { + INVEN3_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Output Waveform 4 Inversion"] + #[inline(always)] + pub fn inven4(&self) -> INVEN4_R { + INVEN4_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Output Waveform 5 Inversion"] + #[inline(always)] + pub fn inven5(&self) -> INVEN5_R { + INVEN5_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Output Waveform 6 Inversion"] + #[inline(always)] + pub fn inven6(&self) -> INVEN6_R { + INVEN6_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Output Waveform 7 Inversion"] + #[inline(always)] + pub fn inven7(&self) -> INVEN7_R { + INVEN7_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bits 24:27 - Non-Recoverable Fault Input 0 Filter Value"] + #[inline(always)] + pub fn filterval0(&self) -> FILTERVAL0_R { + FILTERVAL0_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bits 28:31 - Non-Recoverable Fault Input 1 Filter Value"] + #[inline(always)] + pub fn filterval1(&self) -> FILTERVAL1_R { + FILTERVAL1_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bit 0 - Non-Recoverable State 0 Output Enable"] + #[inline(always)] + pub fn nre0(&mut self) -> NRE0_W { + NRE0_W { w: self } + } + #[doc = "Bit 1 - Non-Recoverable State 1 Output Enable"] + #[inline(always)] + pub fn nre1(&mut self) -> NRE1_W { + NRE1_W { w: self } + } + #[doc = "Bit 2 - Non-Recoverable State 2 Output Enable"] + #[inline(always)] + pub fn nre2(&mut self) -> NRE2_W { + NRE2_W { w: self } + } + #[doc = "Bit 3 - Non-Recoverable State 3 Output Enable"] + #[inline(always)] + pub fn nre3(&mut self) -> NRE3_W { + NRE3_W { w: self } + } + #[doc = "Bit 4 - Non-Recoverable State 4 Output Enable"] + #[inline(always)] + pub fn nre4(&mut self) -> NRE4_W { + NRE4_W { w: self } + } + #[doc = "Bit 5 - Non-Recoverable State 5 Output Enable"] + #[inline(always)] + pub fn nre5(&mut self) -> NRE5_W { + NRE5_W { w: self } + } + #[doc = "Bit 6 - Non-Recoverable State 6 Output Enable"] + #[inline(always)] + pub fn nre6(&mut self) -> NRE6_W { + NRE6_W { w: self } + } + #[doc = "Bit 7 - Non-Recoverable State 7 Output Enable"] + #[inline(always)] + pub fn nre7(&mut self) -> NRE7_W { + NRE7_W { w: self } + } + #[doc = "Bit 8 - Non-Recoverable State 0 Output Value"] + #[inline(always)] + pub fn nrv0(&mut self) -> NRV0_W { + NRV0_W { w: self } + } + #[doc = "Bit 9 - Non-Recoverable State 1 Output Value"] + #[inline(always)] + pub fn nrv1(&mut self) -> NRV1_W { + NRV1_W { w: self } + } + #[doc = "Bit 10 - Non-Recoverable State 2 Output Value"] + #[inline(always)] + pub fn nrv2(&mut self) -> NRV2_W { + NRV2_W { w: self } + } + #[doc = "Bit 11 - Non-Recoverable State 3 Output Value"] + #[inline(always)] + pub fn nrv3(&mut self) -> NRV3_W { + NRV3_W { w: self } + } + #[doc = "Bit 12 - Non-Recoverable State 4 Output Value"] + #[inline(always)] + pub fn nrv4(&mut self) -> NRV4_W { + NRV4_W { w: self } + } + #[doc = "Bit 13 - Non-Recoverable State 5 Output Value"] + #[inline(always)] + pub fn nrv5(&mut self) -> NRV5_W { + NRV5_W { w: self } + } + #[doc = "Bit 14 - Non-Recoverable State 6 Output Value"] + #[inline(always)] + pub fn nrv6(&mut self) -> NRV6_W { + NRV6_W { w: self } + } + #[doc = "Bit 15 - Non-Recoverable State 7 Output Value"] + #[inline(always)] + pub fn nrv7(&mut self) -> NRV7_W { + NRV7_W { w: self } + } + #[doc = "Bit 16 - Output Waveform 0 Inversion"] + #[inline(always)] + pub fn inven0(&mut self) -> INVEN0_W { + INVEN0_W { w: self } + } + #[doc = "Bit 17 - Output Waveform 1 Inversion"] + #[inline(always)] + pub fn inven1(&mut self) -> INVEN1_W { + INVEN1_W { w: self } + } + #[doc = "Bit 18 - Output Waveform 2 Inversion"] + #[inline(always)] + pub fn inven2(&mut self) -> INVEN2_W { + INVEN2_W { w: self } + } + #[doc = "Bit 19 - Output Waveform 3 Inversion"] + #[inline(always)] + pub fn inven3(&mut self) -> INVEN3_W { + INVEN3_W { w: self } + } + #[doc = "Bit 20 - Output Waveform 4 Inversion"] + #[inline(always)] + pub fn inven4(&mut self) -> INVEN4_W { + INVEN4_W { w: self } + } + #[doc = "Bit 21 - Output Waveform 5 Inversion"] + #[inline(always)] + pub fn inven5(&mut self) -> INVEN5_W { + INVEN5_W { w: self } + } + #[doc = "Bit 22 - Output Waveform 6 Inversion"] + #[inline(always)] + pub fn inven6(&mut self) -> INVEN6_W { + INVEN6_W { w: self } + } + #[doc = "Bit 23 - Output Waveform 7 Inversion"] + #[inline(always)] + pub fn inven7(&mut self) -> INVEN7_W { + INVEN7_W { w: self } + } + #[doc = "Bits 24:27 - Non-Recoverable Fault Input 0 Filter Value"] + #[inline(always)] + pub fn filterval0(&mut self) -> FILTERVAL0_W { + FILTERVAL0_W { w: self } + } + #[doc = "Bits 28:31 - Non-Recoverable Fault Input 1 Filter Value"] + #[inline(always)] + pub fn filterval1(&mut self) -> FILTERVAL1_W { + FILTERVAL1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Driver Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [drvctrl](index.html) module"] +pub struct DRVCTRL_SPEC; +impl crate::RegisterSpec for DRVCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [drvctrl::R](R) reader structure"] +impl crate::Readable for DRVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [drvctrl::W](W) writer structure"] +impl crate::Writable for DRVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DRVCTRL to value 0"] +impl crate::Resettable for DRVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/tcc0/evctrl.rs b/pac/atsamc20e/src/tcc0/evctrl.rs new file mode 100644 index 000000000000..334a53924d61 --- /dev/null +++ b/pac/atsamc20e/src/tcc0/evctrl.rs @@ -0,0 +1,1211 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Timer/counter Input Event0 Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EVACT0_A { + #[doc = "0: Event action disabled"] + OFF = 0, + #[doc = "1: Start, restart or re-trigger counter on event"] + RETRIGGER = 1, + #[doc = "2: Count on event"] + COUNTEV = 2, + #[doc = "3: Start counter on event"] + START = 3, + #[doc = "4: Increment counter on event"] + INC = 4, + #[doc = "5: Count on active state of asynchronous event"] + COUNT = 5, + #[doc = "6: Stamp capture"] + STAMP = 6, + #[doc = "7: Non-recoverable fault"] + FAULT = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EVACT0_A) -> Self { + variant as _ + } +} +#[doc = "Field `EVACT0` reader - Timer/counter Input Event0 Action"] +pub struct EVACT0_R(crate::FieldReader); +impl EVACT0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVACT0_A { + match self.bits { + 0 => EVACT0_A::OFF, + 1 => EVACT0_A::RETRIGGER, + 2 => EVACT0_A::COUNTEV, + 3 => EVACT0_A::START, + 4 => EVACT0_A::INC, + 5 => EVACT0_A::COUNT, + 6 => EVACT0_A::STAMP, + 7 => EVACT0_A::FAULT, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == EVACT0_A::OFF + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == EVACT0_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `COUNTEV`"] + #[inline(always)] + pub fn is_countev(&self) -> bool { + **self == EVACT0_A::COUNTEV + } + #[doc = "Checks if the value of the field is `START`"] + #[inline(always)] + pub fn is_start(&self) -> bool { + **self == EVACT0_A::START + } + #[doc = "Checks if the value of the field is `INC`"] + #[inline(always)] + pub fn is_inc(&self) -> bool { + **self == EVACT0_A::INC + } + #[doc = "Checks if the value of the field is `COUNT`"] + #[inline(always)] + pub fn is_count(&self) -> bool { + **self == EVACT0_A::COUNT + } + #[doc = "Checks if the value of the field is `STAMP`"] + #[inline(always)] + pub fn is_stamp(&self) -> bool { + **self == EVACT0_A::STAMP + } + #[doc = "Checks if the value of the field is `FAULT`"] + #[inline(always)] + pub fn is_fault(&self) -> bool { + **self == EVACT0_A::FAULT + } +} +impl core::ops::Deref for EVACT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT0` writer - Timer/counter Input Event0 Action"] +pub struct EVACT0_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT0_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EVACT0_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Event action disabled"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(EVACT0_A::OFF) + } + #[doc = "Start, restart or re-trigger counter on event"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(EVACT0_A::RETRIGGER) + } + #[doc = "Count on event"] + #[inline(always)] + pub fn countev(self) -> &'a mut W { + self.variant(EVACT0_A::COUNTEV) + } + #[doc = "Start counter on event"] + #[inline(always)] + pub fn start(self) -> &'a mut W { + self.variant(EVACT0_A::START) + } + #[doc = "Increment counter on event"] + #[inline(always)] + pub fn inc(self) -> &'a mut W { + self.variant(EVACT0_A::INC) + } + #[doc = "Count on active state of asynchronous event"] + #[inline(always)] + pub fn count(self) -> &'a mut W { + self.variant(EVACT0_A::COUNT) + } + #[doc = "Stamp capture"] + #[inline(always)] + pub fn stamp(self) -> &'a mut W { + self.variant(EVACT0_A::STAMP) + } + #[doc = "Non-recoverable fault"] + #[inline(always)] + pub fn fault(self) -> &'a mut W { + self.variant(EVACT0_A::FAULT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Timer/counter Input Event1 Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EVACT1_A { + #[doc = "0: Event action disabled"] + OFF = 0, + #[doc = "1: Re-trigger counter on event"] + RETRIGGER = 1, + #[doc = "2: Direction control"] + DIR = 2, + #[doc = "3: Stop counter on event"] + STOP = 3, + #[doc = "4: Decrement counter on event"] + DEC = 4, + #[doc = "5: Period capture value in CC0 register, pulse width capture value in CC1 register"] + PPW = 5, + #[doc = "6: Period capture value in CC1 register, pulse width capture value in CC0 register"] + PWP = 6, + #[doc = "7: Non-recoverable fault"] + FAULT = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EVACT1_A) -> Self { + variant as _ + } +} +#[doc = "Field `EVACT1` reader - Timer/counter Input Event1 Action"] +pub struct EVACT1_R(crate::FieldReader); +impl EVACT1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT1_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVACT1_A { + match self.bits { + 0 => EVACT1_A::OFF, + 1 => EVACT1_A::RETRIGGER, + 2 => EVACT1_A::DIR, + 3 => EVACT1_A::STOP, + 4 => EVACT1_A::DEC, + 5 => EVACT1_A::PPW, + 6 => EVACT1_A::PWP, + 7 => EVACT1_A::FAULT, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == EVACT1_A::OFF + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == EVACT1_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `DIR`"] + #[inline(always)] + pub fn is_dir(&self) -> bool { + **self == EVACT1_A::DIR + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == EVACT1_A::STOP + } + #[doc = "Checks if the value of the field is `DEC`"] + #[inline(always)] + pub fn is_dec(&self) -> bool { + **self == EVACT1_A::DEC + } + #[doc = "Checks if the value of the field is `PPW`"] + #[inline(always)] + pub fn is_ppw(&self) -> bool { + **self == EVACT1_A::PPW + } + #[doc = "Checks if the value of the field is `PWP`"] + #[inline(always)] + pub fn is_pwp(&self) -> bool { + **self == EVACT1_A::PWP + } + #[doc = "Checks if the value of the field is `FAULT`"] + #[inline(always)] + pub fn is_fault(&self) -> bool { + **self == EVACT1_A::FAULT + } +} +impl core::ops::Deref for EVACT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT1` writer - Timer/counter Input Event1 Action"] +pub struct EVACT1_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT1_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EVACT1_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Event action disabled"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(EVACT1_A::OFF) + } + #[doc = "Re-trigger counter on event"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(EVACT1_A::RETRIGGER) + } + #[doc = "Direction control"] + #[inline(always)] + pub fn dir(self) -> &'a mut W { + self.variant(EVACT1_A::DIR) + } + #[doc = "Stop counter on event"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(EVACT1_A::STOP) + } + #[doc = "Decrement counter on event"] + #[inline(always)] + pub fn dec(self) -> &'a mut W { + self.variant(EVACT1_A::DEC) + } + #[doc = "Period capture value in CC0 register, pulse width capture value in CC1 register"] + #[inline(always)] + pub fn ppw(self) -> &'a mut W { + self.variant(EVACT1_A::PPW) + } + #[doc = "Period capture value in CC1 register, pulse width capture value in CC0 register"] + #[inline(always)] + pub fn pwp(self) -> &'a mut W { + self.variant(EVACT1_A::PWP) + } + #[doc = "Non-recoverable fault"] + #[inline(always)] + pub fn fault(self) -> &'a mut W { + self.variant(EVACT1_A::FAULT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 3)) | ((value as u32 & 0x07) << 3); + self.w + } +} +#[doc = "Timer/counter Output Event Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CNTSEL_A { + #[doc = "0: An interrupt/event is generated when a new counter cycle starts"] + START = 0, + #[doc = "1: An interrupt/event is generated when a counter cycle ends"] + END = 1, + #[doc = "2: An interrupt/event is generated when a counter cycle ends, except for the first and last cycles"] + BETWEEN = 2, + #[doc = "3: An interrupt/event is generated when a new counter cycle starts or a counter cycle ends"] + BOUNDARY = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CNTSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `CNTSEL` reader - Timer/counter Output Event Mode"] +pub struct CNTSEL_R(crate::FieldReader); +impl CNTSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CNTSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CNTSEL_A { + match self.bits { + 0 => CNTSEL_A::START, + 1 => CNTSEL_A::END, + 2 => CNTSEL_A::BETWEEN, + 3 => CNTSEL_A::BOUNDARY, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `START`"] + #[inline(always)] + pub fn is_start(&self) -> bool { + **self == CNTSEL_A::START + } + #[doc = "Checks if the value of the field is `END`"] + #[inline(always)] + pub fn is_end(&self) -> bool { + **self == CNTSEL_A::END + } + #[doc = "Checks if the value of the field is `BETWEEN`"] + #[inline(always)] + pub fn is_between(&self) -> bool { + **self == CNTSEL_A::BETWEEN + } + #[doc = "Checks if the value of the field is `BOUNDARY`"] + #[inline(always)] + pub fn is_boundary(&self) -> bool { + **self == CNTSEL_A::BOUNDARY + } +} +impl core::ops::Deref for CNTSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CNTSEL` writer - Timer/counter Output Event Mode"] +pub struct CNTSEL_W<'a> { + w: &'a mut W, +} +impl<'a> CNTSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CNTSEL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "An interrupt/event is generated when a new counter cycle starts"] + #[inline(always)] + pub fn start(self) -> &'a mut W { + self.variant(CNTSEL_A::START) + } + #[doc = "An interrupt/event is generated when a counter cycle ends"] + #[inline(always)] + pub fn end(self) -> &'a mut W { + self.variant(CNTSEL_A::END) + } + #[doc = "An interrupt/event is generated when a counter cycle ends, except for the first and last cycles"] + #[inline(always)] + pub fn between(self) -> &'a mut W { + self.variant(CNTSEL_A::BETWEEN) + } + #[doc = "An interrupt/event is generated when a new counter cycle starts or a counter cycle ends"] + #[inline(always)] + pub fn boundary(self) -> &'a mut W { + self.variant(CNTSEL_A::BOUNDARY) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 6)) | ((value as u32 & 0x03) << 6); + self.w + } +} +#[doc = "Field `OVFEO` reader - Overflow/Underflow Output Event Enable"] +pub struct OVFEO_R(crate::FieldReader); +impl OVFEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVFEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVFEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVFEO` writer - Overflow/Underflow Output Event Enable"] +pub struct OVFEO_W<'a> { + w: &'a mut W, +} +impl<'a> OVFEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `TRGEO` reader - Retrigger Output Event Enable"] +pub struct TRGEO_R(crate::FieldReader); +impl TRGEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRGEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRGEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRGEO` writer - Retrigger Output Event Enable"] +pub struct TRGEO_W<'a> { + w: &'a mut W, +} +impl<'a> TRGEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `CNTEO` reader - Timer/counter Output Event Enable"] +pub struct CNTEO_R(crate::FieldReader); +impl CNTEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CNTEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CNTEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CNTEO` writer - Timer/counter Output Event Enable"] +pub struct CNTEO_W<'a> { + w: &'a mut W, +} +impl<'a> CNTEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `TCINV0` reader - Inverted Event 0 Input Enable"] +pub struct TCINV0_R(crate::FieldReader); +impl TCINV0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCINV0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCINV0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCINV0` writer - Inverted Event 0 Input Enable"] +pub struct TCINV0_W<'a> { + w: &'a mut W, +} +impl<'a> TCINV0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `TCINV1` reader - Inverted Event 1 Input Enable"] +pub struct TCINV1_R(crate::FieldReader); +impl TCINV1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCINV1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCINV1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCINV1` writer - Inverted Event 1 Input Enable"] +pub struct TCINV1_W<'a> { + w: &'a mut W, +} +impl<'a> TCINV1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `TCEI0` reader - Timer/counter Event 0 Input Enable"] +pub struct TCEI0_R(crate::FieldReader); +impl TCEI0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCEI0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCEI0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCEI0` writer - Timer/counter Event 0 Input Enable"] +pub struct TCEI0_W<'a> { + w: &'a mut W, +} +impl<'a> TCEI0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `TCEI1` reader - Timer/counter Event 1 Input Enable"] +pub struct TCEI1_R(crate::FieldReader); +impl TCEI1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCEI1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCEI1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCEI1` writer - Timer/counter Event 1 Input Enable"] +pub struct TCEI1_W<'a> { + w: &'a mut W, +} +impl<'a> TCEI1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `MCEI0` reader - Match or Capture Channel 0 Event Input Enable"] +pub struct MCEI0_R(crate::FieldReader); +impl MCEI0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEI0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEI0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEI0` writer - Match or Capture Channel 0 Event Input Enable"] +pub struct MCEI0_W<'a> { + w: &'a mut W, +} +impl<'a> MCEI0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `MCEI1` reader - Match or Capture Channel 1 Event Input Enable"] +pub struct MCEI1_R(crate::FieldReader); +impl MCEI1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEI1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEI1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEI1` writer - Match or Capture Channel 1 Event Input Enable"] +pub struct MCEI1_W<'a> { + w: &'a mut W, +} +impl<'a> MCEI1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `MCEI2` reader - Match or Capture Channel 2 Event Input Enable"] +pub struct MCEI2_R(crate::FieldReader); +impl MCEI2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEI2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEI2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEI2` writer - Match or Capture Channel 2 Event Input Enable"] +pub struct MCEI2_W<'a> { + w: &'a mut W, +} +impl<'a> MCEI2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `MCEI3` reader - Match or Capture Channel 3 Event Input Enable"] +pub struct MCEI3_R(crate::FieldReader); +impl MCEI3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEI3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEI3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEI3` writer - Match or Capture Channel 3 Event Input Enable"] +pub struct MCEI3_W<'a> { + w: &'a mut W, +} +impl<'a> MCEI3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `MCEO0` reader - Match or Capture Channel 0 Event Output Enable"] +pub struct MCEO0_R(crate::FieldReader); +impl MCEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO0` writer - Match or Capture Channel 0 Event Output Enable"] +pub struct MCEO0_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `MCEO1` reader - Match or Capture Channel 1 Event Output Enable"] +pub struct MCEO1_R(crate::FieldReader); +impl MCEO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO1` writer - Match or Capture Channel 1 Event Output Enable"] +pub struct MCEO1_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `MCEO2` reader - Match or Capture Channel 2 Event Output Enable"] +pub struct MCEO2_R(crate::FieldReader); +impl MCEO2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO2` writer - Match or Capture Channel 2 Event Output Enable"] +pub struct MCEO2_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `MCEO3` reader - Match or Capture Channel 3 Event Output Enable"] +pub struct MCEO3_R(crate::FieldReader); +impl MCEO3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO3` writer - Match or Capture Channel 3 Event Output Enable"] +pub struct MCEO3_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Timer/counter Input Event0 Action"] + #[inline(always)] + pub fn evact0(&self) -> EVACT0_R { + EVACT0_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bits 3:5 - Timer/counter Input Event1 Action"] + #[inline(always)] + pub fn evact1(&self) -> EVACT1_R { + EVACT1_R::new(((self.bits >> 3) & 0x07) as u8) + } + #[doc = "Bits 6:7 - Timer/counter Output Event Mode"] + #[inline(always)] + pub fn cntsel(&self) -> CNTSEL_R { + CNTSEL_R::new(((self.bits >> 6) & 0x03) as u8) + } + #[doc = "Bit 8 - Overflow/Underflow Output Event Enable"] + #[inline(always)] + pub fn ovfeo(&self) -> OVFEO_R { + OVFEO_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Retrigger Output Event Enable"] + #[inline(always)] + pub fn trgeo(&self) -> TRGEO_R { + TRGEO_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Timer/counter Output Event Enable"] + #[inline(always)] + pub fn cnteo(&self) -> CNTEO_R { + CNTEO_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 12 - Inverted Event 0 Input Enable"] + #[inline(always)] + pub fn tcinv0(&self) -> TCINV0_R { + TCINV0_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Inverted Event 1 Input Enable"] + #[inline(always)] + pub fn tcinv1(&self) -> TCINV1_R { + TCINV1_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Timer/counter Event 0 Input Enable"] + #[inline(always)] + pub fn tcei0(&self) -> TCEI0_R { + TCEI0_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Timer/counter Event 1 Input Enable"] + #[inline(always)] + pub fn tcei1(&self) -> TCEI1_R { + TCEI1_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Match or Capture Channel 0 Event Input Enable"] + #[inline(always)] + pub fn mcei0(&self) -> MCEI0_R { + MCEI0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Match or Capture Channel 1 Event Input Enable"] + #[inline(always)] + pub fn mcei1(&self) -> MCEI1_R { + MCEI1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Match or Capture Channel 2 Event Input Enable"] + #[inline(always)] + pub fn mcei2(&self) -> MCEI2_R { + MCEI2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Match or Capture Channel 3 Event Input Enable"] + #[inline(always)] + pub fn mcei3(&self) -> MCEI3_R { + MCEI3_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 24 - Match or Capture Channel 0 Event Output Enable"] + #[inline(always)] + pub fn mceo0(&self) -> MCEO0_R { + MCEO0_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Match or Capture Channel 1 Event Output Enable"] + #[inline(always)] + pub fn mceo1(&self) -> MCEO1_R { + MCEO1_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Match or Capture Channel 2 Event Output Enable"] + #[inline(always)] + pub fn mceo2(&self) -> MCEO2_R { + MCEO2_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Match or Capture Channel 3 Event Output Enable"] + #[inline(always)] + pub fn mceo3(&self) -> MCEO3_R { + MCEO3_R::new(((self.bits >> 27) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Timer/counter Input Event0 Action"] + #[inline(always)] + pub fn evact0(&mut self) -> EVACT0_W { + EVACT0_W { w: self } + } + #[doc = "Bits 3:5 - Timer/counter Input Event1 Action"] + #[inline(always)] + pub fn evact1(&mut self) -> EVACT1_W { + EVACT1_W { w: self } + } + #[doc = "Bits 6:7 - Timer/counter Output Event Mode"] + #[inline(always)] + pub fn cntsel(&mut self) -> CNTSEL_W { + CNTSEL_W { w: self } + } + #[doc = "Bit 8 - Overflow/Underflow Output Event Enable"] + #[inline(always)] + pub fn ovfeo(&mut self) -> OVFEO_W { + OVFEO_W { w: self } + } + #[doc = "Bit 9 - Retrigger Output Event Enable"] + #[inline(always)] + pub fn trgeo(&mut self) -> TRGEO_W { + TRGEO_W { w: self } + } + #[doc = "Bit 10 - Timer/counter Output Event Enable"] + #[inline(always)] + pub fn cnteo(&mut self) -> CNTEO_W { + CNTEO_W { w: self } + } + #[doc = "Bit 12 - Inverted Event 0 Input Enable"] + #[inline(always)] + pub fn tcinv0(&mut self) -> TCINV0_W { + TCINV0_W { w: self } + } + #[doc = "Bit 13 - Inverted Event 1 Input Enable"] + #[inline(always)] + pub fn tcinv1(&mut self) -> TCINV1_W { + TCINV1_W { w: self } + } + #[doc = "Bit 14 - Timer/counter Event 0 Input Enable"] + #[inline(always)] + pub fn tcei0(&mut self) -> TCEI0_W { + TCEI0_W { w: self } + } + #[doc = "Bit 15 - Timer/counter Event 1 Input Enable"] + #[inline(always)] + pub fn tcei1(&mut self) -> TCEI1_W { + TCEI1_W { w: self } + } + #[doc = "Bit 16 - Match or Capture Channel 0 Event Input Enable"] + #[inline(always)] + pub fn mcei0(&mut self) -> MCEI0_W { + MCEI0_W { w: self } + } + #[doc = "Bit 17 - Match or Capture Channel 1 Event Input Enable"] + #[inline(always)] + pub fn mcei1(&mut self) -> MCEI1_W { + MCEI1_W { w: self } + } + #[doc = "Bit 18 - Match or Capture Channel 2 Event Input Enable"] + #[inline(always)] + pub fn mcei2(&mut self) -> MCEI2_W { + MCEI2_W { w: self } + } + #[doc = "Bit 19 - Match or Capture Channel 3 Event Input Enable"] + #[inline(always)] + pub fn mcei3(&mut self) -> MCEI3_W { + MCEI3_W { w: self } + } + #[doc = "Bit 24 - Match or Capture Channel 0 Event Output Enable"] + #[inline(always)] + pub fn mceo0(&mut self) -> MCEO0_W { + MCEO0_W { w: self } + } + #[doc = "Bit 25 - Match or Capture Channel 1 Event Output Enable"] + #[inline(always)] + pub fn mceo1(&mut self) -> MCEO1_W { + MCEO1_W { w: self } + } + #[doc = "Bit 26 - Match or Capture Channel 2 Event Output Enable"] + #[inline(always)] + pub fn mceo2(&mut self) -> MCEO2_W { + MCEO2_W { w: self } + } + #[doc = "Bit 27 - Match or Capture Channel 3 Event Output Enable"] + #[inline(always)] + pub fn mceo3(&mut self) -> MCEO3_W { + MCEO3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/tcc0/fctrla.rs b/pac/atsamc20e/src/tcc0/fctrla.rs new file mode 100644 index 000000000000..77c7276fee23 --- /dev/null +++ b/pac/atsamc20e/src/tcc0/fctrla.rs @@ -0,0 +1,940 @@ +#[doc = "Register `FCTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FCTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Fault A Source\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SRC_A { + #[doc = "0: Fault input disabled"] + DISABLE = 0, + #[doc = "1: MCEx (x=0,1) event input"] + ENABLE = 1, + #[doc = "2: Inverted MCEx (x=0,1) event input"] + INVERT = 2, + #[doc = "3: Alternate fault (A or B) state at the end of the previous period"] + ALTFAULT = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SRC_A) -> Self { + variant as _ + } +} +#[doc = "Field `SRC` reader - Fault A Source"] +pub struct SRC_R(crate::FieldReader); +impl SRC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SRC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SRC_A { + match self.bits { + 0 => SRC_A::DISABLE, + 1 => SRC_A::ENABLE, + 2 => SRC_A::INVERT, + 3 => SRC_A::ALTFAULT, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == SRC_A::DISABLE + } + #[doc = "Checks if the value of the field is `ENABLE`"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + **self == SRC_A::ENABLE + } + #[doc = "Checks if the value of the field is `INVERT`"] + #[inline(always)] + pub fn is_invert(&self) -> bool { + **self == SRC_A::INVERT + } + #[doc = "Checks if the value of the field is `ALTFAULT`"] + #[inline(always)] + pub fn is_altfault(&self) -> bool { + **self == SRC_A::ALTFAULT + } +} +impl core::ops::Deref for SRC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SRC` writer - Fault A Source"] +pub struct SRC_W<'a> { + w: &'a mut W, +} +impl<'a> SRC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SRC_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Fault input disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(SRC_A::DISABLE) + } + #[doc = "MCEx (x=0,1) event input"] + #[inline(always)] + pub fn enable(self) -> &'a mut W { + self.variant(SRC_A::ENABLE) + } + #[doc = "Inverted MCEx (x=0,1) event input"] + #[inline(always)] + pub fn invert(self) -> &'a mut W { + self.variant(SRC_A::INVERT) + } + #[doc = "Alternate fault (A or B) state at the end of the previous period"] + #[inline(always)] + pub fn altfault(self) -> &'a mut W { + self.variant(SRC_A::ALTFAULT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u32 & 0x03); + self.w + } +} +#[doc = "Field `KEEP` reader - Fault A Keeper"] +pub struct KEEP_R(crate::FieldReader); +impl KEEP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + KEEP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for KEEP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `KEEP` writer - Fault A Keeper"] +pub struct KEEP_W<'a> { + w: &'a mut W, +} +impl<'a> KEEP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `QUAL` reader - Fault A Qualification"] +pub struct QUAL_R(crate::FieldReader); +impl QUAL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + QUAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for QUAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `QUAL` writer - Fault A Qualification"] +pub struct QUAL_W<'a> { + w: &'a mut W, +} +impl<'a> QUAL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Fault A Blanking Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum BLANK_A { + #[doc = "0: Blanking applied from start of the ramp"] + START = 0, + #[doc = "1: Blanking applied from rising edge of the output waveform"] + RISE = 1, + #[doc = "2: Blanking applied from falling edge of the output waveform"] + FALL = 2, + #[doc = "3: Blanking applied from each toggle of the output waveform"] + BOTH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: BLANK_A) -> Self { + variant as _ + } +} +#[doc = "Field `BLANK` reader - Fault A Blanking Mode"] +pub struct BLANK_R(crate::FieldReader); +impl BLANK_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BLANK_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> BLANK_A { + match self.bits { + 0 => BLANK_A::START, + 1 => BLANK_A::RISE, + 2 => BLANK_A::FALL, + 3 => BLANK_A::BOTH, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `START`"] + #[inline(always)] + pub fn is_start(&self) -> bool { + **self == BLANK_A::START + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == BLANK_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == BLANK_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == BLANK_A::BOTH + } +} +impl core::ops::Deref for BLANK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BLANK` writer - Fault A Blanking Mode"] +pub struct BLANK_W<'a> { + w: &'a mut W, +} +impl<'a> BLANK_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: BLANK_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Blanking applied from start of the ramp"] + #[inline(always)] + pub fn start(self) -> &'a mut W { + self.variant(BLANK_A::START) + } + #[doc = "Blanking applied from rising edge of the output waveform"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(BLANK_A::RISE) + } + #[doc = "Blanking applied from falling edge of the output waveform"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(BLANK_A::FALL) + } + #[doc = "Blanking applied from each toggle of the output waveform"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(BLANK_A::BOTH) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 5)) | ((value as u32 & 0x03) << 5); + self.w + } +} +#[doc = "Field `RESTART` reader - Fault A Restart"] +pub struct RESTART_R(crate::FieldReader); +impl RESTART_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESTART_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESTART_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESTART` writer - Fault A Restart"] +pub struct RESTART_W<'a> { + w: &'a mut W, +} +impl<'a> RESTART_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Fault A Halt Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum HALT_A { + #[doc = "0: Halt action disabled"] + DISABLE = 0, + #[doc = "1: Hardware halt action"] + HW = 1, + #[doc = "2: Software halt action"] + SW = 2, + #[doc = "3: Non-recoverable fault"] + NR = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: HALT_A) -> Self { + variant as _ + } +} +#[doc = "Field `HALT` reader - Fault A Halt Mode"] +pub struct HALT_R(crate::FieldReader); +impl HALT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + HALT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> HALT_A { + match self.bits { + 0 => HALT_A::DISABLE, + 1 => HALT_A::HW, + 2 => HALT_A::SW, + 3 => HALT_A::NR, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == HALT_A::DISABLE + } + #[doc = "Checks if the value of the field is `HW`"] + #[inline(always)] + pub fn is_hw(&self) -> bool { + **self == HALT_A::HW + } + #[doc = "Checks if the value of the field is `SW`"] + #[inline(always)] + pub fn is_sw(&self) -> bool { + **self == HALT_A::SW + } + #[doc = "Checks if the value of the field is `NR`"] + #[inline(always)] + pub fn is_nr(&self) -> bool { + **self == HALT_A::NR + } +} +impl core::ops::Deref for HALT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HALT` writer - Fault A Halt Mode"] +pub struct HALT_W<'a> { + w: &'a mut W, +} +impl<'a> HALT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: HALT_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Halt action disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(HALT_A::DISABLE) + } + #[doc = "Hardware halt action"] + #[inline(always)] + pub fn hw(self) -> &'a mut W { + self.variant(HALT_A::HW) + } + #[doc = "Software halt action"] + #[inline(always)] + pub fn sw(self) -> &'a mut W { + self.variant(HALT_A::SW) + } + #[doc = "Non-recoverable fault"] + #[inline(always)] + pub fn nr(self) -> &'a mut W { + self.variant(HALT_A::NR) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 8)) | ((value as u32 & 0x03) << 8); + self.w + } +} +#[doc = "Fault A Capture Channel\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CHSEL_A { + #[doc = "0: Capture value stored in channel 0"] + CC0 = 0, + #[doc = "1: Capture value stored in channel 1"] + CC1 = 1, + #[doc = "2: Capture value stored in channel 2"] + CC2 = 2, + #[doc = "3: Capture value stored in channel 3"] + CC3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CHSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `CHSEL` reader - Fault A Capture Channel"] +pub struct CHSEL_R(crate::FieldReader); +impl CHSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CHSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CHSEL_A { + match self.bits { + 0 => CHSEL_A::CC0, + 1 => CHSEL_A::CC1, + 2 => CHSEL_A::CC2, + 3 => CHSEL_A::CC3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `CC0`"] + #[inline(always)] + pub fn is_cc0(&self) -> bool { + **self == CHSEL_A::CC0 + } + #[doc = "Checks if the value of the field is `CC1`"] + #[inline(always)] + pub fn is_cc1(&self) -> bool { + **self == CHSEL_A::CC1 + } + #[doc = "Checks if the value of the field is `CC2`"] + #[inline(always)] + pub fn is_cc2(&self) -> bool { + **self == CHSEL_A::CC2 + } + #[doc = "Checks if the value of the field is `CC3`"] + #[inline(always)] + pub fn is_cc3(&self) -> bool { + **self == CHSEL_A::CC3 + } +} +impl core::ops::Deref for CHSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHSEL` writer - Fault A Capture Channel"] +pub struct CHSEL_W<'a> { + w: &'a mut W, +} +impl<'a> CHSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CHSEL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Capture value stored in channel 0"] + #[inline(always)] + pub fn cc0(self) -> &'a mut W { + self.variant(CHSEL_A::CC0) + } + #[doc = "Capture value stored in channel 1"] + #[inline(always)] + pub fn cc1(self) -> &'a mut W { + self.variant(CHSEL_A::CC1) + } + #[doc = "Capture value stored in channel 2"] + #[inline(always)] + pub fn cc2(self) -> &'a mut W { + self.variant(CHSEL_A::CC2) + } + #[doc = "Capture value stored in channel 3"] + #[inline(always)] + pub fn cc3(self) -> &'a mut W { + self.variant(CHSEL_A::CC3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 10)) | ((value as u32 & 0x03) << 10); + self.w + } +} +#[doc = "Fault A Capture Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CAPTURE_A { + #[doc = "0: No capture"] + DISABLE = 0, + #[doc = "1: Capture on fault"] + CAPT = 1, + #[doc = "2: Minimum capture"] + CAPTMIN = 2, + #[doc = "3: Maximum capture"] + CAPTMAX = 3, + #[doc = "4: Minimum local detection"] + LOCMIN = 4, + #[doc = "5: Maximum local detection"] + LOCMAX = 5, + #[doc = "6: Minimum and maximum local detection"] + DERIV0 = 6, + #[doc = "7: Capture with ramp index as MSB value"] + CAPTMARK = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CAPTURE_A) -> Self { + variant as _ + } +} +#[doc = "Field `CAPTURE` reader - Fault A Capture Action"] +pub struct CAPTURE_R(crate::FieldReader); +impl CAPTURE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CAPTURE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CAPTURE_A { + match self.bits { + 0 => CAPTURE_A::DISABLE, + 1 => CAPTURE_A::CAPT, + 2 => CAPTURE_A::CAPTMIN, + 3 => CAPTURE_A::CAPTMAX, + 4 => CAPTURE_A::LOCMIN, + 5 => CAPTURE_A::LOCMAX, + 6 => CAPTURE_A::DERIV0, + 7 => CAPTURE_A::CAPTMARK, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == CAPTURE_A::DISABLE + } + #[doc = "Checks if the value of the field is `CAPT`"] + #[inline(always)] + pub fn is_capt(&self) -> bool { + **self == CAPTURE_A::CAPT + } + #[doc = "Checks if the value of the field is `CAPTMIN`"] + #[inline(always)] + pub fn is_captmin(&self) -> bool { + **self == CAPTURE_A::CAPTMIN + } + #[doc = "Checks if the value of the field is `CAPTMAX`"] + #[inline(always)] + pub fn is_captmax(&self) -> bool { + **self == CAPTURE_A::CAPTMAX + } + #[doc = "Checks if the value of the field is `LOCMIN`"] + #[inline(always)] + pub fn is_locmin(&self) -> bool { + **self == CAPTURE_A::LOCMIN + } + #[doc = "Checks if the value of the field is `LOCMAX`"] + #[inline(always)] + pub fn is_locmax(&self) -> bool { + **self == CAPTURE_A::LOCMAX + } + #[doc = "Checks if the value of the field is `DERIV0`"] + #[inline(always)] + pub fn is_deriv0(&self) -> bool { + **self == CAPTURE_A::DERIV0 + } + #[doc = "Checks if the value of the field is `CAPTMARK`"] + #[inline(always)] + pub fn is_captmark(&self) -> bool { + **self == CAPTURE_A::CAPTMARK + } +} +impl core::ops::Deref for CAPTURE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAPTURE` writer - Fault A Capture Action"] +pub struct CAPTURE_W<'a> { + w: &'a mut W, +} +impl<'a> CAPTURE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CAPTURE_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "No capture"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(CAPTURE_A::DISABLE) + } + #[doc = "Capture on fault"] + #[inline(always)] + pub fn capt(self) -> &'a mut W { + self.variant(CAPTURE_A::CAPT) + } + #[doc = "Minimum capture"] + #[inline(always)] + pub fn captmin(self) -> &'a mut W { + self.variant(CAPTURE_A::CAPTMIN) + } + #[doc = "Maximum capture"] + #[inline(always)] + pub fn captmax(self) -> &'a mut W { + self.variant(CAPTURE_A::CAPTMAX) + } + #[doc = "Minimum local detection"] + #[inline(always)] + pub fn locmin(self) -> &'a mut W { + self.variant(CAPTURE_A::LOCMIN) + } + #[doc = "Maximum local detection"] + #[inline(always)] + pub fn locmax(self) -> &'a mut W { + self.variant(CAPTURE_A::LOCMAX) + } + #[doc = "Minimum and maximum local detection"] + #[inline(always)] + pub fn deriv0(self) -> &'a mut W { + self.variant(CAPTURE_A::DERIV0) + } + #[doc = "Capture with ramp index as MSB value"] + #[inline(always)] + pub fn captmark(self) -> &'a mut W { + self.variant(CAPTURE_A::CAPTMARK) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 12)) | ((value as u32 & 0x07) << 12); + self.w + } +} +#[doc = "Field `BLANKPRESC` reader - Fault A Blanking Prescaler"] +pub struct BLANKPRESC_R(crate::FieldReader); +impl BLANKPRESC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BLANKPRESC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BLANKPRESC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BLANKPRESC` writer - Fault A Blanking Prescaler"] +pub struct BLANKPRESC_W<'a> { + w: &'a mut W, +} +impl<'a> BLANKPRESC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `BLANKVAL` reader - Fault A Blanking Time"] +pub struct BLANKVAL_R(crate::FieldReader); +impl BLANKVAL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BLANKVAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BLANKVAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BLANKVAL` writer - Fault A Blanking Time"] +pub struct BLANKVAL_W<'a> { + w: &'a mut W, +} +impl<'a> BLANKVAL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +#[doc = "Field `FILTERVAL` reader - Fault A Filter Value"] +pub struct FILTERVAL_R(crate::FieldReader); +impl FILTERVAL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FILTERVAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTERVAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTERVAL` writer - Fault A Filter Value"] +pub struct FILTERVAL_W<'a> { + w: &'a mut W, +} +impl<'a> FILTERVAL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Fault A Source"] + #[inline(always)] + pub fn src(&self) -> SRC_R { + SRC_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bit 3 - Fault A Keeper"] + #[inline(always)] + pub fn keep(&self) -> KEEP_R { + KEEP_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Fault A Qualification"] + #[inline(always)] + pub fn qual(&self) -> QUAL_R { + QUAL_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bits 5:6 - Fault A Blanking Mode"] + #[inline(always)] + pub fn blank(&self) -> BLANK_R { + BLANK_R::new(((self.bits >> 5) & 0x03) as u8) + } + #[doc = "Bit 7 - Fault A Restart"] + #[inline(always)] + pub fn restart(&self) -> RESTART_R { + RESTART_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:9 - Fault A Halt Mode"] + #[inline(always)] + pub fn halt(&self) -> HALT_R { + HALT_R::new(((self.bits >> 8) & 0x03) as u8) + } + #[doc = "Bits 10:11 - Fault A Capture Channel"] + #[inline(always)] + pub fn chsel(&self) -> CHSEL_R { + CHSEL_R::new(((self.bits >> 10) & 0x03) as u8) + } + #[doc = "Bits 12:14 - Fault A Capture Action"] + #[inline(always)] + pub fn capture(&self) -> CAPTURE_R { + CAPTURE_R::new(((self.bits >> 12) & 0x07) as u8) + } + #[doc = "Bit 15 - Fault A Blanking Prescaler"] + #[inline(always)] + pub fn blankpresc(&self) -> BLANKPRESC_R { + BLANKPRESC_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:23 - Fault A Blanking Time"] + #[inline(always)] + pub fn blankval(&self) -> BLANKVAL_R { + BLANKVAL_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:27 - Fault A Filter Value"] + #[inline(always)] + pub fn filterval(&self) -> FILTERVAL_R { + FILTERVAL_R::new(((self.bits >> 24) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Fault A Source"] + #[inline(always)] + pub fn src(&mut self) -> SRC_W { + SRC_W { w: self } + } + #[doc = "Bit 3 - Fault A Keeper"] + #[inline(always)] + pub fn keep(&mut self) -> KEEP_W { + KEEP_W { w: self } + } + #[doc = "Bit 4 - Fault A Qualification"] + #[inline(always)] + pub fn qual(&mut self) -> QUAL_W { + QUAL_W { w: self } + } + #[doc = "Bits 5:6 - Fault A Blanking Mode"] + #[inline(always)] + pub fn blank(&mut self) -> BLANK_W { + BLANK_W { w: self } + } + #[doc = "Bit 7 - Fault A Restart"] + #[inline(always)] + pub fn restart(&mut self) -> RESTART_W { + RESTART_W { w: self } + } + #[doc = "Bits 8:9 - Fault A Halt Mode"] + #[inline(always)] + pub fn halt(&mut self) -> HALT_W { + HALT_W { w: self } + } + #[doc = "Bits 10:11 - Fault A Capture Channel"] + #[inline(always)] + pub fn chsel(&mut self) -> CHSEL_W { + CHSEL_W { w: self } + } + #[doc = "Bits 12:14 - Fault A Capture Action"] + #[inline(always)] + pub fn capture(&mut self) -> CAPTURE_W { + CAPTURE_W { w: self } + } + #[doc = "Bit 15 - Fault A Blanking Prescaler"] + #[inline(always)] + pub fn blankpresc(&mut self) -> BLANKPRESC_W { + BLANKPRESC_W { w: self } + } + #[doc = "Bits 16:23 - Fault A Blanking Time"] + #[inline(always)] + pub fn blankval(&mut self) -> BLANKVAL_W { + BLANKVAL_W { w: self } + } + #[doc = "Bits 24:27 - Fault A Filter Value"] + #[inline(always)] + pub fn filterval(&mut self) -> FILTERVAL_W { + FILTERVAL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Recoverable Fault A Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fctrla](index.html) module"] +pub struct FCTRLA_SPEC; +impl crate::RegisterSpec for FCTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [fctrla::R](R) reader structure"] +impl crate::Readable for FCTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [fctrla::W](W) writer structure"] +impl crate::Writable for FCTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets FCTRLA to value 0"] +impl crate::Resettable for FCTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/tcc0/fctrlb.rs b/pac/atsamc20e/src/tcc0/fctrlb.rs new file mode 100644 index 000000000000..4c1dfd1af93d --- /dev/null +++ b/pac/atsamc20e/src/tcc0/fctrlb.rs @@ -0,0 +1,940 @@ +#[doc = "Register `FCTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FCTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Fault B Source\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SRC_A { + #[doc = "0: Fault input disabled"] + DISABLE = 0, + #[doc = "1: MCEx (x=0,1) event input"] + ENABLE = 1, + #[doc = "2: Inverted MCEx (x=0,1) event input"] + INVERT = 2, + #[doc = "3: Alternate fault (A or B) state at the end of the previous period"] + ALTFAULT = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SRC_A) -> Self { + variant as _ + } +} +#[doc = "Field `SRC` reader - Fault B Source"] +pub struct SRC_R(crate::FieldReader); +impl SRC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SRC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SRC_A { + match self.bits { + 0 => SRC_A::DISABLE, + 1 => SRC_A::ENABLE, + 2 => SRC_A::INVERT, + 3 => SRC_A::ALTFAULT, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == SRC_A::DISABLE + } + #[doc = "Checks if the value of the field is `ENABLE`"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + **self == SRC_A::ENABLE + } + #[doc = "Checks if the value of the field is `INVERT`"] + #[inline(always)] + pub fn is_invert(&self) -> bool { + **self == SRC_A::INVERT + } + #[doc = "Checks if the value of the field is `ALTFAULT`"] + #[inline(always)] + pub fn is_altfault(&self) -> bool { + **self == SRC_A::ALTFAULT + } +} +impl core::ops::Deref for SRC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SRC` writer - Fault B Source"] +pub struct SRC_W<'a> { + w: &'a mut W, +} +impl<'a> SRC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SRC_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Fault input disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(SRC_A::DISABLE) + } + #[doc = "MCEx (x=0,1) event input"] + #[inline(always)] + pub fn enable(self) -> &'a mut W { + self.variant(SRC_A::ENABLE) + } + #[doc = "Inverted MCEx (x=0,1) event input"] + #[inline(always)] + pub fn invert(self) -> &'a mut W { + self.variant(SRC_A::INVERT) + } + #[doc = "Alternate fault (A or B) state at the end of the previous period"] + #[inline(always)] + pub fn altfault(self) -> &'a mut W { + self.variant(SRC_A::ALTFAULT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u32 & 0x03); + self.w + } +} +#[doc = "Field `KEEP` reader - Fault B Keeper"] +pub struct KEEP_R(crate::FieldReader); +impl KEEP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + KEEP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for KEEP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `KEEP` writer - Fault B Keeper"] +pub struct KEEP_W<'a> { + w: &'a mut W, +} +impl<'a> KEEP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `QUAL` reader - Fault B Qualification"] +pub struct QUAL_R(crate::FieldReader); +impl QUAL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + QUAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for QUAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `QUAL` writer - Fault B Qualification"] +pub struct QUAL_W<'a> { + w: &'a mut W, +} +impl<'a> QUAL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Fault B Blanking Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum BLANK_A { + #[doc = "0: Blanking applied from start of the ramp"] + START = 0, + #[doc = "1: Blanking applied from rising edge of the output waveform"] + RISE = 1, + #[doc = "2: Blanking applied from falling edge of the output waveform"] + FALL = 2, + #[doc = "3: Blanking applied from each toggle of the output waveform"] + BOTH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: BLANK_A) -> Self { + variant as _ + } +} +#[doc = "Field `BLANK` reader - Fault B Blanking Mode"] +pub struct BLANK_R(crate::FieldReader); +impl BLANK_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BLANK_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> BLANK_A { + match self.bits { + 0 => BLANK_A::START, + 1 => BLANK_A::RISE, + 2 => BLANK_A::FALL, + 3 => BLANK_A::BOTH, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `START`"] + #[inline(always)] + pub fn is_start(&self) -> bool { + **self == BLANK_A::START + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == BLANK_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == BLANK_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == BLANK_A::BOTH + } +} +impl core::ops::Deref for BLANK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BLANK` writer - Fault B Blanking Mode"] +pub struct BLANK_W<'a> { + w: &'a mut W, +} +impl<'a> BLANK_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: BLANK_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Blanking applied from start of the ramp"] + #[inline(always)] + pub fn start(self) -> &'a mut W { + self.variant(BLANK_A::START) + } + #[doc = "Blanking applied from rising edge of the output waveform"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(BLANK_A::RISE) + } + #[doc = "Blanking applied from falling edge of the output waveform"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(BLANK_A::FALL) + } + #[doc = "Blanking applied from each toggle of the output waveform"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(BLANK_A::BOTH) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 5)) | ((value as u32 & 0x03) << 5); + self.w + } +} +#[doc = "Field `RESTART` reader - Fault B Restart"] +pub struct RESTART_R(crate::FieldReader); +impl RESTART_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESTART_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESTART_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESTART` writer - Fault B Restart"] +pub struct RESTART_W<'a> { + w: &'a mut W, +} +impl<'a> RESTART_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Fault B Halt Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum HALT_A { + #[doc = "0: Halt action disabled"] + DISABLE = 0, + #[doc = "1: Hardware halt action"] + HW = 1, + #[doc = "2: Software halt action"] + SW = 2, + #[doc = "3: Non-recoverable fault"] + NR = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: HALT_A) -> Self { + variant as _ + } +} +#[doc = "Field `HALT` reader - Fault B Halt Mode"] +pub struct HALT_R(crate::FieldReader); +impl HALT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + HALT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> HALT_A { + match self.bits { + 0 => HALT_A::DISABLE, + 1 => HALT_A::HW, + 2 => HALT_A::SW, + 3 => HALT_A::NR, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == HALT_A::DISABLE + } + #[doc = "Checks if the value of the field is `HW`"] + #[inline(always)] + pub fn is_hw(&self) -> bool { + **self == HALT_A::HW + } + #[doc = "Checks if the value of the field is `SW`"] + #[inline(always)] + pub fn is_sw(&self) -> bool { + **self == HALT_A::SW + } + #[doc = "Checks if the value of the field is `NR`"] + #[inline(always)] + pub fn is_nr(&self) -> bool { + **self == HALT_A::NR + } +} +impl core::ops::Deref for HALT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HALT` writer - Fault B Halt Mode"] +pub struct HALT_W<'a> { + w: &'a mut W, +} +impl<'a> HALT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: HALT_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Halt action disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(HALT_A::DISABLE) + } + #[doc = "Hardware halt action"] + #[inline(always)] + pub fn hw(self) -> &'a mut W { + self.variant(HALT_A::HW) + } + #[doc = "Software halt action"] + #[inline(always)] + pub fn sw(self) -> &'a mut W { + self.variant(HALT_A::SW) + } + #[doc = "Non-recoverable fault"] + #[inline(always)] + pub fn nr(self) -> &'a mut W { + self.variant(HALT_A::NR) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 8)) | ((value as u32 & 0x03) << 8); + self.w + } +} +#[doc = "Fault B Capture Channel\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CHSEL_A { + #[doc = "0: Capture value stored in channel 0"] + CC0 = 0, + #[doc = "1: Capture value stored in channel 1"] + CC1 = 1, + #[doc = "2: Capture value stored in channel 2"] + CC2 = 2, + #[doc = "3: Capture value stored in channel 3"] + CC3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CHSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `CHSEL` reader - Fault B Capture Channel"] +pub struct CHSEL_R(crate::FieldReader); +impl CHSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CHSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CHSEL_A { + match self.bits { + 0 => CHSEL_A::CC0, + 1 => CHSEL_A::CC1, + 2 => CHSEL_A::CC2, + 3 => CHSEL_A::CC3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `CC0`"] + #[inline(always)] + pub fn is_cc0(&self) -> bool { + **self == CHSEL_A::CC0 + } + #[doc = "Checks if the value of the field is `CC1`"] + #[inline(always)] + pub fn is_cc1(&self) -> bool { + **self == CHSEL_A::CC1 + } + #[doc = "Checks if the value of the field is `CC2`"] + #[inline(always)] + pub fn is_cc2(&self) -> bool { + **self == CHSEL_A::CC2 + } + #[doc = "Checks if the value of the field is `CC3`"] + #[inline(always)] + pub fn is_cc3(&self) -> bool { + **self == CHSEL_A::CC3 + } +} +impl core::ops::Deref for CHSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHSEL` writer - Fault B Capture Channel"] +pub struct CHSEL_W<'a> { + w: &'a mut W, +} +impl<'a> CHSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CHSEL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Capture value stored in channel 0"] + #[inline(always)] + pub fn cc0(self) -> &'a mut W { + self.variant(CHSEL_A::CC0) + } + #[doc = "Capture value stored in channel 1"] + #[inline(always)] + pub fn cc1(self) -> &'a mut W { + self.variant(CHSEL_A::CC1) + } + #[doc = "Capture value stored in channel 2"] + #[inline(always)] + pub fn cc2(self) -> &'a mut W { + self.variant(CHSEL_A::CC2) + } + #[doc = "Capture value stored in channel 3"] + #[inline(always)] + pub fn cc3(self) -> &'a mut W { + self.variant(CHSEL_A::CC3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 10)) | ((value as u32 & 0x03) << 10); + self.w + } +} +#[doc = "Fault B Capture Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CAPTURE_A { + #[doc = "0: No capture"] + DISABLE = 0, + #[doc = "1: Capture on fault"] + CAPT = 1, + #[doc = "2: Minimum capture"] + CAPTMIN = 2, + #[doc = "3: Maximum capture"] + CAPTMAX = 3, + #[doc = "4: Minimum local detection"] + LOCMIN = 4, + #[doc = "5: Maximum local detection"] + LOCMAX = 5, + #[doc = "6: Minimum and maximum local detection"] + DERIV0 = 6, + #[doc = "7: Capture with ramp index as MSB value"] + CAPTMARK = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CAPTURE_A) -> Self { + variant as _ + } +} +#[doc = "Field `CAPTURE` reader - Fault B Capture Action"] +pub struct CAPTURE_R(crate::FieldReader); +impl CAPTURE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CAPTURE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CAPTURE_A { + match self.bits { + 0 => CAPTURE_A::DISABLE, + 1 => CAPTURE_A::CAPT, + 2 => CAPTURE_A::CAPTMIN, + 3 => CAPTURE_A::CAPTMAX, + 4 => CAPTURE_A::LOCMIN, + 5 => CAPTURE_A::LOCMAX, + 6 => CAPTURE_A::DERIV0, + 7 => CAPTURE_A::CAPTMARK, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == CAPTURE_A::DISABLE + } + #[doc = "Checks if the value of the field is `CAPT`"] + #[inline(always)] + pub fn is_capt(&self) -> bool { + **self == CAPTURE_A::CAPT + } + #[doc = "Checks if the value of the field is `CAPTMIN`"] + #[inline(always)] + pub fn is_captmin(&self) -> bool { + **self == CAPTURE_A::CAPTMIN + } + #[doc = "Checks if the value of the field is `CAPTMAX`"] + #[inline(always)] + pub fn is_captmax(&self) -> bool { + **self == CAPTURE_A::CAPTMAX + } + #[doc = "Checks if the value of the field is `LOCMIN`"] + #[inline(always)] + pub fn is_locmin(&self) -> bool { + **self == CAPTURE_A::LOCMIN + } + #[doc = "Checks if the value of the field is `LOCMAX`"] + #[inline(always)] + pub fn is_locmax(&self) -> bool { + **self == CAPTURE_A::LOCMAX + } + #[doc = "Checks if the value of the field is `DERIV0`"] + #[inline(always)] + pub fn is_deriv0(&self) -> bool { + **self == CAPTURE_A::DERIV0 + } + #[doc = "Checks if the value of the field is `CAPTMARK`"] + #[inline(always)] + pub fn is_captmark(&self) -> bool { + **self == CAPTURE_A::CAPTMARK + } +} +impl core::ops::Deref for CAPTURE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAPTURE` writer - Fault B Capture Action"] +pub struct CAPTURE_W<'a> { + w: &'a mut W, +} +impl<'a> CAPTURE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CAPTURE_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "No capture"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(CAPTURE_A::DISABLE) + } + #[doc = "Capture on fault"] + #[inline(always)] + pub fn capt(self) -> &'a mut W { + self.variant(CAPTURE_A::CAPT) + } + #[doc = "Minimum capture"] + #[inline(always)] + pub fn captmin(self) -> &'a mut W { + self.variant(CAPTURE_A::CAPTMIN) + } + #[doc = "Maximum capture"] + #[inline(always)] + pub fn captmax(self) -> &'a mut W { + self.variant(CAPTURE_A::CAPTMAX) + } + #[doc = "Minimum local detection"] + #[inline(always)] + pub fn locmin(self) -> &'a mut W { + self.variant(CAPTURE_A::LOCMIN) + } + #[doc = "Maximum local detection"] + #[inline(always)] + pub fn locmax(self) -> &'a mut W { + self.variant(CAPTURE_A::LOCMAX) + } + #[doc = "Minimum and maximum local detection"] + #[inline(always)] + pub fn deriv0(self) -> &'a mut W { + self.variant(CAPTURE_A::DERIV0) + } + #[doc = "Capture with ramp index as MSB value"] + #[inline(always)] + pub fn captmark(self) -> &'a mut W { + self.variant(CAPTURE_A::CAPTMARK) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 12)) | ((value as u32 & 0x07) << 12); + self.w + } +} +#[doc = "Field `BLANKPRESC` reader - Fault B Blanking Prescaler"] +pub struct BLANKPRESC_R(crate::FieldReader); +impl BLANKPRESC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BLANKPRESC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BLANKPRESC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BLANKPRESC` writer - Fault B Blanking Prescaler"] +pub struct BLANKPRESC_W<'a> { + w: &'a mut W, +} +impl<'a> BLANKPRESC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `BLANKVAL` reader - Fault B Blanking Time"] +pub struct BLANKVAL_R(crate::FieldReader); +impl BLANKVAL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BLANKVAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BLANKVAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BLANKVAL` writer - Fault B Blanking Time"] +pub struct BLANKVAL_W<'a> { + w: &'a mut W, +} +impl<'a> BLANKVAL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +#[doc = "Field `FILTERVAL` reader - Fault B Filter Value"] +pub struct FILTERVAL_R(crate::FieldReader); +impl FILTERVAL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FILTERVAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTERVAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTERVAL` writer - Fault B Filter Value"] +pub struct FILTERVAL_W<'a> { + w: &'a mut W, +} +impl<'a> FILTERVAL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Fault B Source"] + #[inline(always)] + pub fn src(&self) -> SRC_R { + SRC_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bit 3 - Fault B Keeper"] + #[inline(always)] + pub fn keep(&self) -> KEEP_R { + KEEP_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Fault B Qualification"] + #[inline(always)] + pub fn qual(&self) -> QUAL_R { + QUAL_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bits 5:6 - Fault B Blanking Mode"] + #[inline(always)] + pub fn blank(&self) -> BLANK_R { + BLANK_R::new(((self.bits >> 5) & 0x03) as u8) + } + #[doc = "Bit 7 - Fault B Restart"] + #[inline(always)] + pub fn restart(&self) -> RESTART_R { + RESTART_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:9 - Fault B Halt Mode"] + #[inline(always)] + pub fn halt(&self) -> HALT_R { + HALT_R::new(((self.bits >> 8) & 0x03) as u8) + } + #[doc = "Bits 10:11 - Fault B Capture Channel"] + #[inline(always)] + pub fn chsel(&self) -> CHSEL_R { + CHSEL_R::new(((self.bits >> 10) & 0x03) as u8) + } + #[doc = "Bits 12:14 - Fault B Capture Action"] + #[inline(always)] + pub fn capture(&self) -> CAPTURE_R { + CAPTURE_R::new(((self.bits >> 12) & 0x07) as u8) + } + #[doc = "Bit 15 - Fault B Blanking Prescaler"] + #[inline(always)] + pub fn blankpresc(&self) -> BLANKPRESC_R { + BLANKPRESC_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:23 - Fault B Blanking Time"] + #[inline(always)] + pub fn blankval(&self) -> BLANKVAL_R { + BLANKVAL_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:27 - Fault B Filter Value"] + #[inline(always)] + pub fn filterval(&self) -> FILTERVAL_R { + FILTERVAL_R::new(((self.bits >> 24) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Fault B Source"] + #[inline(always)] + pub fn src(&mut self) -> SRC_W { + SRC_W { w: self } + } + #[doc = "Bit 3 - Fault B Keeper"] + #[inline(always)] + pub fn keep(&mut self) -> KEEP_W { + KEEP_W { w: self } + } + #[doc = "Bit 4 - Fault B Qualification"] + #[inline(always)] + pub fn qual(&mut self) -> QUAL_W { + QUAL_W { w: self } + } + #[doc = "Bits 5:6 - Fault B Blanking Mode"] + #[inline(always)] + pub fn blank(&mut self) -> BLANK_W { + BLANK_W { w: self } + } + #[doc = "Bit 7 - Fault B Restart"] + #[inline(always)] + pub fn restart(&mut self) -> RESTART_W { + RESTART_W { w: self } + } + #[doc = "Bits 8:9 - Fault B Halt Mode"] + #[inline(always)] + pub fn halt(&mut self) -> HALT_W { + HALT_W { w: self } + } + #[doc = "Bits 10:11 - Fault B Capture Channel"] + #[inline(always)] + pub fn chsel(&mut self) -> CHSEL_W { + CHSEL_W { w: self } + } + #[doc = "Bits 12:14 - Fault B Capture Action"] + #[inline(always)] + pub fn capture(&mut self) -> CAPTURE_W { + CAPTURE_W { w: self } + } + #[doc = "Bit 15 - Fault B Blanking Prescaler"] + #[inline(always)] + pub fn blankpresc(&mut self) -> BLANKPRESC_W { + BLANKPRESC_W { w: self } + } + #[doc = "Bits 16:23 - Fault B Blanking Time"] + #[inline(always)] + pub fn blankval(&mut self) -> BLANKVAL_W { + BLANKVAL_W { w: self } + } + #[doc = "Bits 24:27 - Fault B Filter Value"] + #[inline(always)] + pub fn filterval(&mut self) -> FILTERVAL_W { + FILTERVAL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Recoverable Fault B Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fctrlb](index.html) module"] +pub struct FCTRLB_SPEC; +impl crate::RegisterSpec for FCTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [fctrlb::R](R) reader structure"] +impl crate::Readable for FCTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [fctrlb::W](W) writer structure"] +impl crate::Writable for FCTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets FCTRLB to value 0"] +impl crate::Resettable for FCTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/tcc0/intenclr.rs b/pac/atsamc20e/src/tcc0/intenclr.rs new file mode 100644 index 000000000000..a227a8405a3c --- /dev/null +++ b/pac/atsamc20e/src/tcc0/intenclr.rs @@ -0,0 +1,724 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `TRG` reader - Retrigger Interrupt Enable"] +pub struct TRG_R(crate::FieldReader); +impl TRG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRG` writer - Retrigger Interrupt Enable"] +pub struct TRG_W<'a> { + w: &'a mut W, +} +impl<'a> TRG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CNT` reader - Counter Interrupt Enable"] +pub struct CNT_R(crate::FieldReader); +impl CNT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CNT` writer - Counter Interrupt Enable"] +pub struct CNT_W<'a> { + w: &'a mut W, +} +impl<'a> CNT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `ERR` reader - Error Interrupt Enable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - Error Interrupt Enable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `UFS` reader - Non-Recoverable Update Fault Interrupt Enable"] +pub struct UFS_R(crate::FieldReader); +impl UFS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UFS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for UFS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `UFS` writer - Non-Recoverable Update Fault Interrupt Enable"] +pub struct UFS_W<'a> { + w: &'a mut W, +} +impl<'a> UFS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `DFS` reader - Non-Recoverable Debug Fault Interrupt Enable"] +pub struct DFS_R(crate::FieldReader); +impl DFS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFS` writer - Non-Recoverable Debug Fault Interrupt Enable"] +pub struct DFS_W<'a> { + w: &'a mut W, +} +impl<'a> DFS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `FAULTA` reader - Recoverable Fault A Interrupt Enable"] +pub struct FAULTA_R(crate::FieldReader); +impl FAULTA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTA` writer - Recoverable Fault A Interrupt Enable"] +pub struct FAULTA_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `FAULTB` reader - Recoverable Fault B Interrupt Enable"] +pub struct FAULTB_R(crate::FieldReader); +impl FAULTB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTB` writer - Recoverable Fault B Interrupt Enable"] +pub struct FAULTB_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `FAULT0` reader - Non-Recoverable Fault 0 Interrupt Enable"] +pub struct FAULT0_R(crate::FieldReader); +impl FAULT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT0` writer - Non-Recoverable Fault 0 Interrupt Enable"] +pub struct FAULT0_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `FAULT1` reader - Non-Recoverable Fault 1 Interrupt Enable"] +pub struct FAULT1_R(crate::FieldReader); +impl FAULT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT1` writer - Non-Recoverable Fault 1 Interrupt Enable"] +pub struct FAULT1_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `MC0` reader - Match or Capture Channel 0 Interrupt Enable"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - Match or Capture Channel 0 Interrupt Enable"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `MC1` reader - Match or Capture Channel 1 Interrupt Enable"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - Match or Capture Channel 1 Interrupt Enable"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `MC2` reader - Match or Capture Channel 2 Interrupt Enable"] +pub struct MC2_R(crate::FieldReader); +impl MC2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC2` writer - Match or Capture Channel 2 Interrupt Enable"] +pub struct MC2_W<'a> { + w: &'a mut W, +} +impl<'a> MC2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `MC3` reader - Match or Capture Channel 3 Interrupt Enable"] +pub struct MC3_R(crate::FieldReader); +impl MC3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC3` writer - Match or Capture Channel 3 Interrupt Enable"] +pub struct MC3_W<'a> { + w: &'a mut W, +} +impl<'a> MC3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +impl R { + #[doc = "Bit 0 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Retrigger Interrupt Enable"] + #[inline(always)] + pub fn trg(&self) -> TRG_R { + TRG_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Counter Interrupt Enable"] + #[inline(always)] + pub fn cnt(&self) -> CNT_R { + CNT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Error Interrupt Enable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 10 - Non-Recoverable Update Fault Interrupt Enable"] + #[inline(always)] + pub fn ufs(&self) -> UFS_R { + UFS_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Non-Recoverable Debug Fault Interrupt Enable"] + #[inline(always)] + pub fn dfs(&self) -> DFS_R { + DFS_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Recoverable Fault A Interrupt Enable"] + #[inline(always)] + pub fn faulta(&self) -> FAULTA_R { + FAULTA_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Recoverable Fault B Interrupt Enable"] + #[inline(always)] + pub fn faultb(&self) -> FAULTB_R { + FAULTB_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Non-Recoverable Fault 0 Interrupt Enable"] + #[inline(always)] + pub fn fault0(&self) -> FAULT0_R { + FAULT0_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Non-Recoverable Fault 1 Interrupt Enable"] + #[inline(always)] + pub fn fault1(&self) -> FAULT1_R { + FAULT1_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Match or Capture Channel 0 Interrupt Enable"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Match or Capture Channel 1 Interrupt Enable"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Match or Capture Channel 2 Interrupt Enable"] + #[inline(always)] + pub fn mc2(&self) -> MC2_R { + MC2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Match or Capture Channel 3 Interrupt Enable"] + #[inline(always)] + pub fn mc3(&self) -> MC3_R { + MC3_R::new(((self.bits >> 19) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - Retrigger Interrupt Enable"] + #[inline(always)] + pub fn trg(&mut self) -> TRG_W { + TRG_W { w: self } + } + #[doc = "Bit 2 - Counter Interrupt Enable"] + #[inline(always)] + pub fn cnt(&mut self) -> CNT_W { + CNT_W { w: self } + } + #[doc = "Bit 3 - Error Interrupt Enable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 10 - Non-Recoverable Update Fault Interrupt Enable"] + #[inline(always)] + pub fn ufs(&mut self) -> UFS_W { + UFS_W { w: self } + } + #[doc = "Bit 11 - Non-Recoverable Debug Fault Interrupt Enable"] + #[inline(always)] + pub fn dfs(&mut self) -> DFS_W { + DFS_W { w: self } + } + #[doc = "Bit 12 - Recoverable Fault A Interrupt Enable"] + #[inline(always)] + pub fn faulta(&mut self) -> FAULTA_W { + FAULTA_W { w: self } + } + #[doc = "Bit 13 - Recoverable Fault B Interrupt Enable"] + #[inline(always)] + pub fn faultb(&mut self) -> FAULTB_W { + FAULTB_W { w: self } + } + #[doc = "Bit 14 - Non-Recoverable Fault 0 Interrupt Enable"] + #[inline(always)] + pub fn fault0(&mut self) -> FAULT0_W { + FAULT0_W { w: self } + } + #[doc = "Bit 15 - Non-Recoverable Fault 1 Interrupt Enable"] + #[inline(always)] + pub fn fault1(&mut self) -> FAULT1_W { + FAULT1_W { w: self } + } + #[doc = "Bit 16 - Match or Capture Channel 0 Interrupt Enable"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 17 - Match or Capture Channel 1 Interrupt Enable"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Bit 18 - Match or Capture Channel 2 Interrupt Enable"] + #[inline(always)] + pub fn mc2(&mut self) -> MC2_W { + MC2_W { w: self } + } + #[doc = "Bit 19 - Match or Capture Channel 3 Interrupt Enable"] + #[inline(always)] + pub fn mc3(&mut self) -> MC3_W { + MC3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/tcc0/intenset.rs b/pac/atsamc20e/src/tcc0/intenset.rs new file mode 100644 index 000000000000..0125a220bd02 --- /dev/null +++ b/pac/atsamc20e/src/tcc0/intenset.rs @@ -0,0 +1,724 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `TRG` reader - Retrigger Interrupt Enable"] +pub struct TRG_R(crate::FieldReader); +impl TRG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRG` writer - Retrigger Interrupt Enable"] +pub struct TRG_W<'a> { + w: &'a mut W, +} +impl<'a> TRG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CNT` reader - Counter Interrupt Enable"] +pub struct CNT_R(crate::FieldReader); +impl CNT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CNT` writer - Counter Interrupt Enable"] +pub struct CNT_W<'a> { + w: &'a mut W, +} +impl<'a> CNT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `ERR` reader - Error Interrupt Enable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - Error Interrupt Enable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `UFS` reader - Non-Recoverable Update Fault Interrupt Enable"] +pub struct UFS_R(crate::FieldReader); +impl UFS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UFS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for UFS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `UFS` writer - Non-Recoverable Update Fault Interrupt Enable"] +pub struct UFS_W<'a> { + w: &'a mut W, +} +impl<'a> UFS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `DFS` reader - Non-Recoverable Debug Fault Interrupt Enable"] +pub struct DFS_R(crate::FieldReader); +impl DFS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFS` writer - Non-Recoverable Debug Fault Interrupt Enable"] +pub struct DFS_W<'a> { + w: &'a mut W, +} +impl<'a> DFS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `FAULTA` reader - Recoverable Fault A Interrupt Enable"] +pub struct FAULTA_R(crate::FieldReader); +impl FAULTA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTA` writer - Recoverable Fault A Interrupt Enable"] +pub struct FAULTA_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `FAULTB` reader - Recoverable Fault B Interrupt Enable"] +pub struct FAULTB_R(crate::FieldReader); +impl FAULTB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTB` writer - Recoverable Fault B Interrupt Enable"] +pub struct FAULTB_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `FAULT0` reader - Non-Recoverable Fault 0 Interrupt Enable"] +pub struct FAULT0_R(crate::FieldReader); +impl FAULT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT0` writer - Non-Recoverable Fault 0 Interrupt Enable"] +pub struct FAULT0_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `FAULT1` reader - Non-Recoverable Fault 1 Interrupt Enable"] +pub struct FAULT1_R(crate::FieldReader); +impl FAULT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT1` writer - Non-Recoverable Fault 1 Interrupt Enable"] +pub struct FAULT1_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `MC0` reader - Match or Capture Channel 0 Interrupt Enable"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - Match or Capture Channel 0 Interrupt Enable"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `MC1` reader - Match or Capture Channel 1 Interrupt Enable"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - Match or Capture Channel 1 Interrupt Enable"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `MC2` reader - Match or Capture Channel 2 Interrupt Enable"] +pub struct MC2_R(crate::FieldReader); +impl MC2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC2` writer - Match or Capture Channel 2 Interrupt Enable"] +pub struct MC2_W<'a> { + w: &'a mut W, +} +impl<'a> MC2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `MC3` reader - Match or Capture Channel 3 Interrupt Enable"] +pub struct MC3_R(crate::FieldReader); +impl MC3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC3` writer - Match or Capture Channel 3 Interrupt Enable"] +pub struct MC3_W<'a> { + w: &'a mut W, +} +impl<'a> MC3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +impl R { + #[doc = "Bit 0 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Retrigger Interrupt Enable"] + #[inline(always)] + pub fn trg(&self) -> TRG_R { + TRG_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Counter Interrupt Enable"] + #[inline(always)] + pub fn cnt(&self) -> CNT_R { + CNT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Error Interrupt Enable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 10 - Non-Recoverable Update Fault Interrupt Enable"] + #[inline(always)] + pub fn ufs(&self) -> UFS_R { + UFS_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Non-Recoverable Debug Fault Interrupt Enable"] + #[inline(always)] + pub fn dfs(&self) -> DFS_R { + DFS_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Recoverable Fault A Interrupt Enable"] + #[inline(always)] + pub fn faulta(&self) -> FAULTA_R { + FAULTA_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Recoverable Fault B Interrupt Enable"] + #[inline(always)] + pub fn faultb(&self) -> FAULTB_R { + FAULTB_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Non-Recoverable Fault 0 Interrupt Enable"] + #[inline(always)] + pub fn fault0(&self) -> FAULT0_R { + FAULT0_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Non-Recoverable Fault 1 Interrupt Enable"] + #[inline(always)] + pub fn fault1(&self) -> FAULT1_R { + FAULT1_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Match or Capture Channel 0 Interrupt Enable"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Match or Capture Channel 1 Interrupt Enable"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Match or Capture Channel 2 Interrupt Enable"] + #[inline(always)] + pub fn mc2(&self) -> MC2_R { + MC2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Match or Capture Channel 3 Interrupt Enable"] + #[inline(always)] + pub fn mc3(&self) -> MC3_R { + MC3_R::new(((self.bits >> 19) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - Retrigger Interrupt Enable"] + #[inline(always)] + pub fn trg(&mut self) -> TRG_W { + TRG_W { w: self } + } + #[doc = "Bit 2 - Counter Interrupt Enable"] + #[inline(always)] + pub fn cnt(&mut self) -> CNT_W { + CNT_W { w: self } + } + #[doc = "Bit 3 - Error Interrupt Enable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 10 - Non-Recoverable Update Fault Interrupt Enable"] + #[inline(always)] + pub fn ufs(&mut self) -> UFS_W { + UFS_W { w: self } + } + #[doc = "Bit 11 - Non-Recoverable Debug Fault Interrupt Enable"] + #[inline(always)] + pub fn dfs(&mut self) -> DFS_W { + DFS_W { w: self } + } + #[doc = "Bit 12 - Recoverable Fault A Interrupt Enable"] + #[inline(always)] + pub fn faulta(&mut self) -> FAULTA_W { + FAULTA_W { w: self } + } + #[doc = "Bit 13 - Recoverable Fault B Interrupt Enable"] + #[inline(always)] + pub fn faultb(&mut self) -> FAULTB_W { + FAULTB_W { w: self } + } + #[doc = "Bit 14 - Non-Recoverable Fault 0 Interrupt Enable"] + #[inline(always)] + pub fn fault0(&mut self) -> FAULT0_W { + FAULT0_W { w: self } + } + #[doc = "Bit 15 - Non-Recoverable Fault 1 Interrupt Enable"] + #[inline(always)] + pub fn fault1(&mut self) -> FAULT1_W { + FAULT1_W { w: self } + } + #[doc = "Bit 16 - Match or Capture Channel 0 Interrupt Enable"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 17 - Match or Capture Channel 1 Interrupt Enable"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Bit 18 - Match or Capture Channel 2 Interrupt Enable"] + #[inline(always)] + pub fn mc2(&mut self) -> MC2_W { + MC2_W { w: self } + } + #[doc = "Bit 19 - Match or Capture Channel 3 Interrupt Enable"] + #[inline(always)] + pub fn mc3(&mut self) -> MC3_W { + MC3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/tcc0/intflag.rs b/pac/atsamc20e/src/tcc0/intflag.rs new file mode 100644 index 000000000000..b2d5088f4087 --- /dev/null +++ b/pac/atsamc20e/src/tcc0/intflag.rs @@ -0,0 +1,724 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - Overflow"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `TRG` reader - Retrigger"] +pub struct TRG_R(crate::FieldReader); +impl TRG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRG` writer - Retrigger"] +pub struct TRG_W<'a> { + w: &'a mut W, +} +impl<'a> TRG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CNT` reader - Counter"] +pub struct CNT_R(crate::FieldReader); +impl CNT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CNT` writer - Counter"] +pub struct CNT_W<'a> { + w: &'a mut W, +} +impl<'a> CNT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `ERR` reader - Error"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - Error"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `UFS` reader - Non-Recoverable Update Fault"] +pub struct UFS_R(crate::FieldReader); +impl UFS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UFS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for UFS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `UFS` writer - Non-Recoverable Update Fault"] +pub struct UFS_W<'a> { + w: &'a mut W, +} +impl<'a> UFS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `DFS` reader - Non-Recoverable Debug Fault"] +pub struct DFS_R(crate::FieldReader); +impl DFS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFS` writer - Non-Recoverable Debug Fault"] +pub struct DFS_W<'a> { + w: &'a mut W, +} +impl<'a> DFS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `FAULTA` reader - Recoverable Fault A"] +pub struct FAULTA_R(crate::FieldReader); +impl FAULTA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTA` writer - Recoverable Fault A"] +pub struct FAULTA_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `FAULTB` reader - Recoverable Fault B"] +pub struct FAULTB_R(crate::FieldReader); +impl FAULTB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTB` writer - Recoverable Fault B"] +pub struct FAULTB_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `FAULT0` reader - Non-Recoverable Fault 0"] +pub struct FAULT0_R(crate::FieldReader); +impl FAULT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT0` writer - Non-Recoverable Fault 0"] +pub struct FAULT0_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `FAULT1` reader - Non-Recoverable Fault 1"] +pub struct FAULT1_R(crate::FieldReader); +impl FAULT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT1` writer - Non-Recoverable Fault 1"] +pub struct FAULT1_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `MC0` reader - Match or Capture 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - Match or Capture 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `MC1` reader - Match or Capture 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - Match or Capture 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `MC2` reader - Match or Capture 2"] +pub struct MC2_R(crate::FieldReader); +impl MC2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC2` writer - Match or Capture 2"] +pub struct MC2_W<'a> { + w: &'a mut W, +} +impl<'a> MC2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `MC3` reader - Match or Capture 3"] +pub struct MC3_R(crate::FieldReader); +impl MC3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC3` writer - Match or Capture 3"] +pub struct MC3_W<'a> { + w: &'a mut W, +} +impl<'a> MC3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +impl R { + #[doc = "Bit 0 - Overflow"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Retrigger"] + #[inline(always)] + pub fn trg(&self) -> TRG_R { + TRG_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Counter"] + #[inline(always)] + pub fn cnt(&self) -> CNT_R { + CNT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Error"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 10 - Non-Recoverable Update Fault"] + #[inline(always)] + pub fn ufs(&self) -> UFS_R { + UFS_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Non-Recoverable Debug Fault"] + #[inline(always)] + pub fn dfs(&self) -> DFS_R { + DFS_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Recoverable Fault A"] + #[inline(always)] + pub fn faulta(&self) -> FAULTA_R { + FAULTA_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Recoverable Fault B"] + #[inline(always)] + pub fn faultb(&self) -> FAULTB_R { + FAULTB_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Non-Recoverable Fault 0"] + #[inline(always)] + pub fn fault0(&self) -> FAULT0_R { + FAULT0_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Non-Recoverable Fault 1"] + #[inline(always)] + pub fn fault1(&self) -> FAULT1_R { + FAULT1_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Match or Capture 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Match or Capture 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Match or Capture 2"] + #[inline(always)] + pub fn mc2(&self) -> MC2_R { + MC2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Match or Capture 3"] + #[inline(always)] + pub fn mc3(&self) -> MC3_R { + MC3_R::new(((self.bits >> 19) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Overflow"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - Retrigger"] + #[inline(always)] + pub fn trg(&mut self) -> TRG_W { + TRG_W { w: self } + } + #[doc = "Bit 2 - Counter"] + #[inline(always)] + pub fn cnt(&mut self) -> CNT_W { + CNT_W { w: self } + } + #[doc = "Bit 3 - Error"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 10 - Non-Recoverable Update Fault"] + #[inline(always)] + pub fn ufs(&mut self) -> UFS_W { + UFS_W { w: self } + } + #[doc = "Bit 11 - Non-Recoverable Debug Fault"] + #[inline(always)] + pub fn dfs(&mut self) -> DFS_W { + DFS_W { w: self } + } + #[doc = "Bit 12 - Recoverable Fault A"] + #[inline(always)] + pub fn faulta(&mut self) -> FAULTA_W { + FAULTA_W { w: self } + } + #[doc = "Bit 13 - Recoverable Fault B"] + #[inline(always)] + pub fn faultb(&mut self) -> FAULTB_W { + FAULTB_W { w: self } + } + #[doc = "Bit 14 - Non-Recoverable Fault 0"] + #[inline(always)] + pub fn fault0(&mut self) -> FAULT0_W { + FAULT0_W { w: self } + } + #[doc = "Bit 15 - Non-Recoverable Fault 1"] + #[inline(always)] + pub fn fault1(&mut self) -> FAULT1_W { + FAULT1_W { w: self } + } + #[doc = "Bit 16 - Match or Capture 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 17 - Match or Capture 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Bit 18 - Match or Capture 2"] + #[inline(always)] + pub fn mc2(&mut self) -> MC2_W { + MC2_W { w: self } + } + #[doc = "Bit 19 - Match or Capture 3"] + #[inline(always)] + pub fn mc3(&mut self) -> MC3_W { + MC3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/tcc0/patt.rs b/pac/atsamc20e/src/tcc0/patt.rs new file mode 100644 index 000000000000..ea458642b182 --- /dev/null +++ b/pac/atsamc20e/src/tcc0/patt.rs @@ -0,0 +1,818 @@ +#[doc = "Register `PATT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PATT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PGE0` reader - Pattern Generator 0 Output Enable"] +pub struct PGE0_R(crate::FieldReader); +impl PGE0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGE0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGE0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGE0` writer - Pattern Generator 0 Output Enable"] +pub struct PGE0_W<'a> { + w: &'a mut W, +} +impl<'a> PGE0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PGE1` reader - Pattern Generator 1 Output Enable"] +pub struct PGE1_R(crate::FieldReader); +impl PGE1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGE1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGE1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGE1` writer - Pattern Generator 1 Output Enable"] +pub struct PGE1_W<'a> { + w: &'a mut W, +} +impl<'a> PGE1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PGE2` reader - Pattern Generator 2 Output Enable"] +pub struct PGE2_R(crate::FieldReader); +impl PGE2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGE2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGE2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGE2` writer - Pattern Generator 2 Output Enable"] +pub struct PGE2_W<'a> { + w: &'a mut W, +} +impl<'a> PGE2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PGE3` reader - Pattern Generator 3 Output Enable"] +pub struct PGE3_R(crate::FieldReader); +impl PGE3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGE3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGE3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGE3` writer - Pattern Generator 3 Output Enable"] +pub struct PGE3_W<'a> { + w: &'a mut W, +} +impl<'a> PGE3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PGE4` reader - Pattern Generator 4 Output Enable"] +pub struct PGE4_R(crate::FieldReader); +impl PGE4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGE4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGE4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGE4` writer - Pattern Generator 4 Output Enable"] +pub struct PGE4_W<'a> { + w: &'a mut W, +} +impl<'a> PGE4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PGE5` reader - Pattern Generator 5 Output Enable"] +pub struct PGE5_R(crate::FieldReader); +impl PGE5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGE5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGE5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGE5` writer - Pattern Generator 5 Output Enable"] +pub struct PGE5_W<'a> { + w: &'a mut W, +} +impl<'a> PGE5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PGE6` reader - Pattern Generator 6 Output Enable"] +pub struct PGE6_R(crate::FieldReader); +impl PGE6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGE6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGE6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGE6` writer - Pattern Generator 6 Output Enable"] +pub struct PGE6_W<'a> { + w: &'a mut W, +} +impl<'a> PGE6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PGE7` reader - Pattern Generator 7 Output Enable"] +pub struct PGE7_R(crate::FieldReader); +impl PGE7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGE7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGE7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGE7` writer - Pattern Generator 7 Output Enable"] +pub struct PGE7_W<'a> { + w: &'a mut W, +} +impl<'a> PGE7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `PGV0` reader - Pattern Generator 0 Output Value"] +pub struct PGV0_R(crate::FieldReader); +impl PGV0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGV0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGV0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGV0` writer - Pattern Generator 0 Output Value"] +pub struct PGV0_W<'a> { + w: &'a mut W, +} +impl<'a> PGV0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `PGV1` reader - Pattern Generator 1 Output Value"] +pub struct PGV1_R(crate::FieldReader); +impl PGV1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGV1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGV1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGV1` writer - Pattern Generator 1 Output Value"] +pub struct PGV1_W<'a> { + w: &'a mut W, +} +impl<'a> PGV1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `PGV2` reader - Pattern Generator 2 Output Value"] +pub struct PGV2_R(crate::FieldReader); +impl PGV2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGV2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGV2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGV2` writer - Pattern Generator 2 Output Value"] +pub struct PGV2_W<'a> { + w: &'a mut W, +} +impl<'a> PGV2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u16 & 0x01) << 10); + self.w + } +} +#[doc = "Field `PGV3` reader - Pattern Generator 3 Output Value"] +pub struct PGV3_R(crate::FieldReader); +impl PGV3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGV3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGV3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGV3` writer - Pattern Generator 3 Output Value"] +pub struct PGV3_W<'a> { + w: &'a mut W, +} +impl<'a> PGV3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u16 & 0x01) << 11); + self.w + } +} +#[doc = "Field `PGV4` reader - Pattern Generator 4 Output Value"] +pub struct PGV4_R(crate::FieldReader); +impl PGV4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGV4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGV4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGV4` writer - Pattern Generator 4 Output Value"] +pub struct PGV4_W<'a> { + w: &'a mut W, +} +impl<'a> PGV4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u16 & 0x01) << 12); + self.w + } +} +#[doc = "Field `PGV5` reader - Pattern Generator 5 Output Value"] +pub struct PGV5_R(crate::FieldReader); +impl PGV5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGV5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGV5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGV5` writer - Pattern Generator 5 Output Value"] +pub struct PGV5_W<'a> { + w: &'a mut W, +} +impl<'a> PGV5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u16 & 0x01) << 13); + self.w + } +} +#[doc = "Field `PGV6` reader - Pattern Generator 6 Output Value"] +pub struct PGV6_R(crate::FieldReader); +impl PGV6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGV6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGV6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGV6` writer - Pattern Generator 6 Output Value"] +pub struct PGV6_W<'a> { + w: &'a mut W, +} +impl<'a> PGV6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u16 & 0x01) << 14); + self.w + } +} +#[doc = "Field `PGV7` reader - Pattern Generator 7 Output Value"] +pub struct PGV7_R(crate::FieldReader); +impl PGV7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGV7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGV7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGV7` writer - Pattern Generator 7 Output Value"] +pub struct PGV7_W<'a> { + w: &'a mut W, +} +impl<'a> PGV7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Pattern Generator 0 Output Enable"] + #[inline(always)] + pub fn pge0(&self) -> PGE0_R { + PGE0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Pattern Generator 1 Output Enable"] + #[inline(always)] + pub fn pge1(&self) -> PGE1_R { + PGE1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Pattern Generator 2 Output Enable"] + #[inline(always)] + pub fn pge2(&self) -> PGE2_R { + PGE2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Pattern Generator 3 Output Enable"] + #[inline(always)] + pub fn pge3(&self) -> PGE3_R { + PGE3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Pattern Generator 4 Output Enable"] + #[inline(always)] + pub fn pge4(&self) -> PGE4_R { + PGE4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Pattern Generator 5 Output Enable"] + #[inline(always)] + pub fn pge5(&self) -> PGE5_R { + PGE5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Pattern Generator 6 Output Enable"] + #[inline(always)] + pub fn pge6(&self) -> PGE6_R { + PGE6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Pattern Generator 7 Output Enable"] + #[inline(always)] + pub fn pge7(&self) -> PGE7_R { + PGE7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Pattern Generator 0 Output Value"] + #[inline(always)] + pub fn pgv0(&self) -> PGV0_R { + PGV0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Pattern Generator 1 Output Value"] + #[inline(always)] + pub fn pgv1(&self) -> PGV1_R { + PGV1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Pattern Generator 2 Output Value"] + #[inline(always)] + pub fn pgv2(&self) -> PGV2_R { + PGV2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Pattern Generator 3 Output Value"] + #[inline(always)] + pub fn pgv3(&self) -> PGV3_R { + PGV3_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Pattern Generator 4 Output Value"] + #[inline(always)] + pub fn pgv4(&self) -> PGV4_R { + PGV4_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Pattern Generator 5 Output Value"] + #[inline(always)] + pub fn pgv5(&self) -> PGV5_R { + PGV5_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Pattern Generator 6 Output Value"] + #[inline(always)] + pub fn pgv6(&self) -> PGV6_R { + PGV6_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Pattern Generator 7 Output Value"] + #[inline(always)] + pub fn pgv7(&self) -> PGV7_R { + PGV7_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pattern Generator 0 Output Enable"] + #[inline(always)] + pub fn pge0(&mut self) -> PGE0_W { + PGE0_W { w: self } + } + #[doc = "Bit 1 - Pattern Generator 1 Output Enable"] + #[inline(always)] + pub fn pge1(&mut self) -> PGE1_W { + PGE1_W { w: self } + } + #[doc = "Bit 2 - Pattern Generator 2 Output Enable"] + #[inline(always)] + pub fn pge2(&mut self) -> PGE2_W { + PGE2_W { w: self } + } + #[doc = "Bit 3 - Pattern Generator 3 Output Enable"] + #[inline(always)] + pub fn pge3(&mut self) -> PGE3_W { + PGE3_W { w: self } + } + #[doc = "Bit 4 - Pattern Generator 4 Output Enable"] + #[inline(always)] + pub fn pge4(&mut self) -> PGE4_W { + PGE4_W { w: self } + } + #[doc = "Bit 5 - Pattern Generator 5 Output Enable"] + #[inline(always)] + pub fn pge5(&mut self) -> PGE5_W { + PGE5_W { w: self } + } + #[doc = "Bit 6 - Pattern Generator 6 Output Enable"] + #[inline(always)] + pub fn pge6(&mut self) -> PGE6_W { + PGE6_W { w: self } + } + #[doc = "Bit 7 - Pattern Generator 7 Output Enable"] + #[inline(always)] + pub fn pge7(&mut self) -> PGE7_W { + PGE7_W { w: self } + } + #[doc = "Bit 8 - Pattern Generator 0 Output Value"] + #[inline(always)] + pub fn pgv0(&mut self) -> PGV0_W { + PGV0_W { w: self } + } + #[doc = "Bit 9 - Pattern Generator 1 Output Value"] + #[inline(always)] + pub fn pgv1(&mut self) -> PGV1_W { + PGV1_W { w: self } + } + #[doc = "Bit 10 - Pattern Generator 2 Output Value"] + #[inline(always)] + pub fn pgv2(&mut self) -> PGV2_W { + PGV2_W { w: self } + } + #[doc = "Bit 11 - Pattern Generator 3 Output Value"] + #[inline(always)] + pub fn pgv3(&mut self) -> PGV3_W { + PGV3_W { w: self } + } + #[doc = "Bit 12 - Pattern Generator 4 Output Value"] + #[inline(always)] + pub fn pgv4(&mut self) -> PGV4_W { + PGV4_W { w: self } + } + #[doc = "Bit 13 - Pattern Generator 5 Output Value"] + #[inline(always)] + pub fn pgv5(&mut self) -> PGV5_W { + PGV5_W { w: self } + } + #[doc = "Bit 14 - Pattern Generator 6 Output Value"] + #[inline(always)] + pub fn pgv6(&mut self) -> PGV6_W { + PGV6_W { w: self } + } + #[doc = "Bit 15 - Pattern Generator 7 Output Value"] + #[inline(always)] + pub fn pgv7(&mut self) -> PGV7_W { + PGV7_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Pattern\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [patt](index.html) module"] +pub struct PATT_SPEC; +impl crate::RegisterSpec for PATT_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [patt::R](R) reader structure"] +impl crate::Readable for PATT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [patt::W](W) writer structure"] +impl crate::Writable for PATT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PATT to value 0"] +impl crate::Resettable for PATT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/tcc0/pattbuf.rs b/pac/atsamc20e/src/tcc0/pattbuf.rs new file mode 100644 index 000000000000..c9375e27645c --- /dev/null +++ b/pac/atsamc20e/src/tcc0/pattbuf.rs @@ -0,0 +1,818 @@ +#[doc = "Register `PATTBUF` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PATTBUF` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PGEB0` reader - Pattern Generator 0 Output Enable Buffer"] +pub struct PGEB0_R(crate::FieldReader); +impl PGEB0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGEB0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGEB0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGEB0` writer - Pattern Generator 0 Output Enable Buffer"] +pub struct PGEB0_W<'a> { + w: &'a mut W, +} +impl<'a> PGEB0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PGEB1` reader - Pattern Generator 1 Output Enable Buffer"] +pub struct PGEB1_R(crate::FieldReader); +impl PGEB1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGEB1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGEB1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGEB1` writer - Pattern Generator 1 Output Enable Buffer"] +pub struct PGEB1_W<'a> { + w: &'a mut W, +} +impl<'a> PGEB1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PGEB2` reader - Pattern Generator 2 Output Enable Buffer"] +pub struct PGEB2_R(crate::FieldReader); +impl PGEB2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGEB2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGEB2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGEB2` writer - Pattern Generator 2 Output Enable Buffer"] +pub struct PGEB2_W<'a> { + w: &'a mut W, +} +impl<'a> PGEB2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PGEB3` reader - Pattern Generator 3 Output Enable Buffer"] +pub struct PGEB3_R(crate::FieldReader); +impl PGEB3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGEB3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGEB3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGEB3` writer - Pattern Generator 3 Output Enable Buffer"] +pub struct PGEB3_W<'a> { + w: &'a mut W, +} +impl<'a> PGEB3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PGEB4` reader - Pattern Generator 4 Output Enable Buffer"] +pub struct PGEB4_R(crate::FieldReader); +impl PGEB4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGEB4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGEB4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGEB4` writer - Pattern Generator 4 Output Enable Buffer"] +pub struct PGEB4_W<'a> { + w: &'a mut W, +} +impl<'a> PGEB4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PGEB5` reader - Pattern Generator 5 Output Enable Buffer"] +pub struct PGEB5_R(crate::FieldReader); +impl PGEB5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGEB5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGEB5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGEB5` writer - Pattern Generator 5 Output Enable Buffer"] +pub struct PGEB5_W<'a> { + w: &'a mut W, +} +impl<'a> PGEB5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PGEB6` reader - Pattern Generator 6 Output Enable Buffer"] +pub struct PGEB6_R(crate::FieldReader); +impl PGEB6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGEB6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGEB6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGEB6` writer - Pattern Generator 6 Output Enable Buffer"] +pub struct PGEB6_W<'a> { + w: &'a mut W, +} +impl<'a> PGEB6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PGEB7` reader - Pattern Generator 7 Output Enable Buffer"] +pub struct PGEB7_R(crate::FieldReader); +impl PGEB7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGEB7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGEB7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGEB7` writer - Pattern Generator 7 Output Enable Buffer"] +pub struct PGEB7_W<'a> { + w: &'a mut W, +} +impl<'a> PGEB7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `PGVB0` reader - Pattern Generator 0 Output Enable"] +pub struct PGVB0_R(crate::FieldReader); +impl PGVB0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGVB0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGVB0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGVB0` writer - Pattern Generator 0 Output Enable"] +pub struct PGVB0_W<'a> { + w: &'a mut W, +} +impl<'a> PGVB0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `PGVB1` reader - Pattern Generator 1 Output Enable"] +pub struct PGVB1_R(crate::FieldReader); +impl PGVB1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGVB1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGVB1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGVB1` writer - Pattern Generator 1 Output Enable"] +pub struct PGVB1_W<'a> { + w: &'a mut W, +} +impl<'a> PGVB1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `PGVB2` reader - Pattern Generator 2 Output Enable"] +pub struct PGVB2_R(crate::FieldReader); +impl PGVB2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGVB2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGVB2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGVB2` writer - Pattern Generator 2 Output Enable"] +pub struct PGVB2_W<'a> { + w: &'a mut W, +} +impl<'a> PGVB2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u16 & 0x01) << 10); + self.w + } +} +#[doc = "Field `PGVB3` reader - Pattern Generator 3 Output Enable"] +pub struct PGVB3_R(crate::FieldReader); +impl PGVB3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGVB3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGVB3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGVB3` writer - Pattern Generator 3 Output Enable"] +pub struct PGVB3_W<'a> { + w: &'a mut W, +} +impl<'a> PGVB3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u16 & 0x01) << 11); + self.w + } +} +#[doc = "Field `PGVB4` reader - Pattern Generator 4 Output Enable"] +pub struct PGVB4_R(crate::FieldReader); +impl PGVB4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGVB4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGVB4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGVB4` writer - Pattern Generator 4 Output Enable"] +pub struct PGVB4_W<'a> { + w: &'a mut W, +} +impl<'a> PGVB4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u16 & 0x01) << 12); + self.w + } +} +#[doc = "Field `PGVB5` reader - Pattern Generator 5 Output Enable"] +pub struct PGVB5_R(crate::FieldReader); +impl PGVB5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGVB5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGVB5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGVB5` writer - Pattern Generator 5 Output Enable"] +pub struct PGVB5_W<'a> { + w: &'a mut W, +} +impl<'a> PGVB5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u16 & 0x01) << 13); + self.w + } +} +#[doc = "Field `PGVB6` reader - Pattern Generator 6 Output Enable"] +pub struct PGVB6_R(crate::FieldReader); +impl PGVB6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGVB6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGVB6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGVB6` writer - Pattern Generator 6 Output Enable"] +pub struct PGVB6_W<'a> { + w: &'a mut W, +} +impl<'a> PGVB6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u16 & 0x01) << 14); + self.w + } +} +#[doc = "Field `PGVB7` reader - Pattern Generator 7 Output Enable"] +pub struct PGVB7_R(crate::FieldReader); +impl PGVB7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGVB7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGVB7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGVB7` writer - Pattern Generator 7 Output Enable"] +pub struct PGVB7_W<'a> { + w: &'a mut W, +} +impl<'a> PGVB7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Pattern Generator 0 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb0(&self) -> PGEB0_R { + PGEB0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Pattern Generator 1 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb1(&self) -> PGEB1_R { + PGEB1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Pattern Generator 2 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb2(&self) -> PGEB2_R { + PGEB2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Pattern Generator 3 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb3(&self) -> PGEB3_R { + PGEB3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Pattern Generator 4 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb4(&self) -> PGEB4_R { + PGEB4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Pattern Generator 5 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb5(&self) -> PGEB5_R { + PGEB5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Pattern Generator 6 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb6(&self) -> PGEB6_R { + PGEB6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Pattern Generator 7 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb7(&self) -> PGEB7_R { + PGEB7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Pattern Generator 0 Output Enable"] + #[inline(always)] + pub fn pgvb0(&self) -> PGVB0_R { + PGVB0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Pattern Generator 1 Output Enable"] + #[inline(always)] + pub fn pgvb1(&self) -> PGVB1_R { + PGVB1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Pattern Generator 2 Output Enable"] + #[inline(always)] + pub fn pgvb2(&self) -> PGVB2_R { + PGVB2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Pattern Generator 3 Output Enable"] + #[inline(always)] + pub fn pgvb3(&self) -> PGVB3_R { + PGVB3_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Pattern Generator 4 Output Enable"] + #[inline(always)] + pub fn pgvb4(&self) -> PGVB4_R { + PGVB4_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Pattern Generator 5 Output Enable"] + #[inline(always)] + pub fn pgvb5(&self) -> PGVB5_R { + PGVB5_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Pattern Generator 6 Output Enable"] + #[inline(always)] + pub fn pgvb6(&self) -> PGVB6_R { + PGVB6_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Pattern Generator 7 Output Enable"] + #[inline(always)] + pub fn pgvb7(&self) -> PGVB7_R { + PGVB7_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pattern Generator 0 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb0(&mut self) -> PGEB0_W { + PGEB0_W { w: self } + } + #[doc = "Bit 1 - Pattern Generator 1 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb1(&mut self) -> PGEB1_W { + PGEB1_W { w: self } + } + #[doc = "Bit 2 - Pattern Generator 2 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb2(&mut self) -> PGEB2_W { + PGEB2_W { w: self } + } + #[doc = "Bit 3 - Pattern Generator 3 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb3(&mut self) -> PGEB3_W { + PGEB3_W { w: self } + } + #[doc = "Bit 4 - Pattern Generator 4 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb4(&mut self) -> PGEB4_W { + PGEB4_W { w: self } + } + #[doc = "Bit 5 - Pattern Generator 5 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb5(&mut self) -> PGEB5_W { + PGEB5_W { w: self } + } + #[doc = "Bit 6 - Pattern Generator 6 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb6(&mut self) -> PGEB6_W { + PGEB6_W { w: self } + } + #[doc = "Bit 7 - Pattern Generator 7 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb7(&mut self) -> PGEB7_W { + PGEB7_W { w: self } + } + #[doc = "Bit 8 - Pattern Generator 0 Output Enable"] + #[inline(always)] + pub fn pgvb0(&mut self) -> PGVB0_W { + PGVB0_W { w: self } + } + #[doc = "Bit 9 - Pattern Generator 1 Output Enable"] + #[inline(always)] + pub fn pgvb1(&mut self) -> PGVB1_W { + PGVB1_W { w: self } + } + #[doc = "Bit 10 - Pattern Generator 2 Output Enable"] + #[inline(always)] + pub fn pgvb2(&mut self) -> PGVB2_W { + PGVB2_W { w: self } + } + #[doc = "Bit 11 - Pattern Generator 3 Output Enable"] + #[inline(always)] + pub fn pgvb3(&mut self) -> PGVB3_W { + PGVB3_W { w: self } + } + #[doc = "Bit 12 - Pattern Generator 4 Output Enable"] + #[inline(always)] + pub fn pgvb4(&mut self) -> PGVB4_W { + PGVB4_W { w: self } + } + #[doc = "Bit 13 - Pattern Generator 5 Output Enable"] + #[inline(always)] + pub fn pgvb5(&mut self) -> PGVB5_W { + PGVB5_W { w: self } + } + #[doc = "Bit 14 - Pattern Generator 6 Output Enable"] + #[inline(always)] + pub fn pgvb6(&mut self) -> PGVB6_W { + PGVB6_W { w: self } + } + #[doc = "Bit 15 - Pattern Generator 7 Output Enable"] + #[inline(always)] + pub fn pgvb7(&mut self) -> PGVB7_W { + PGVB7_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Pattern Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pattbuf](index.html) module"] +pub struct PATTBUF_SPEC; +impl crate::RegisterSpec for PATTBUF_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [pattbuf::R](R) reader structure"] +impl crate::Readable for PATTBUF_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [pattbuf::W](W) writer structure"] +impl crate::Writable for PATTBUF_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PATTBUF to value 0"] +impl crate::Resettable for PATTBUF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/tcc0/per.rs b/pac/atsamc20e/src/tcc0/per.rs new file mode 100644 index 000000000000..9d8618631650 --- /dev/null +++ b/pac/atsamc20e/src/tcc0/per.rs @@ -0,0 +1,103 @@ +#[doc = "Register `PER` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PER` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER` reader - Period Value"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` writer - Period Value"] +pub struct PER_W<'a> { + w: &'a mut W, +} +impl<'a> PER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Period Value"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Period Value"] + #[inline(always)] + pub fn per(&mut self) -> PER_W { + PER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [per](index.html) module"] +pub struct PER_SPEC; +impl crate::RegisterSpec for PER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [per::R](R) reader structure"] +impl crate::Readable for PER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [per::W](W) writer structure"] +impl crate::Writable for PER_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PER to value 0xffff_ffff"] +impl crate::Resettable for PER_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pac/atsamc20e/src/tcc0/per_dith4_mode.rs b/pac/atsamc20e/src/tcc0/per_dith4_mode.rs new file mode 100644 index 000000000000..2f600552db84 --- /dev/null +++ b/pac/atsamc20e/src/tcc0/per_dith4_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PER_DITH4_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PER_DITH4_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHER` reader - Dithering Cycle Number"] +pub struct DITHER_R(crate::FieldReader); +impl DITHER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHER` writer - Dithering Cycle Number"] +pub struct DITHER_W<'a> { + w: &'a mut W, +} +impl<'a> DITHER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Field `PER` reader - Period Value"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` writer - Period Value"] +pub struct PER_W<'a> { + w: &'a mut W, +} +impl<'a> PER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x000f_ffff << 4)) | ((value as u32 & 0x000f_ffff) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&self) -> DITHER_R { + DITHER_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:23 - Period Value"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(((self.bits >> 4) & 0x000f_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:3 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&mut self) -> DITHER_W { + DITHER_W { w: self } + } + #[doc = "Bits 4:23 - Period Value"] + #[inline(always)] + pub fn per(&mut self) -> PER_W { + PER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [per_dith4_mode](index.html) module"] +pub struct PER_DITH4_MODE_SPEC; +impl crate::RegisterSpec for PER_DITH4_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [per_dith4_mode::R](R) reader structure"] +impl crate::Readable for PER_DITH4_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [per_dith4_mode::W](W) writer structure"] +impl crate::Writable for PER_DITH4_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PER_DITH4_MODE to value 0xffff_ffff"] +impl crate::Resettable for PER_DITH4_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pac/atsamc20e/src/tcc0/per_dith5_mode.rs b/pac/atsamc20e/src/tcc0/per_dith5_mode.rs new file mode 100644 index 000000000000..1906582e4c95 --- /dev/null +++ b/pac/atsamc20e/src/tcc0/per_dith5_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PER_DITH5_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PER_DITH5_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHER` reader - Dithering Cycle Number"] +pub struct DITHER_R(crate::FieldReader); +impl DITHER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHER` writer - Dithering Cycle Number"] +pub struct DITHER_W<'a> { + w: &'a mut W, +} +impl<'a> DITHER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f); + self.w + } +} +#[doc = "Field `PER` reader - Period Value"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` writer - Period Value"] +pub struct PER_W<'a> { + w: &'a mut W, +} +impl<'a> PER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0007_ffff << 5)) | ((value as u32 & 0x0007_ffff) << 5); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&self) -> DITHER_R { + DITHER_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:23 - Period Value"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(((self.bits >> 5) & 0x0007_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:4 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&mut self) -> DITHER_W { + DITHER_W { w: self } + } + #[doc = "Bits 5:23 - Period Value"] + #[inline(always)] + pub fn per(&mut self) -> PER_W { + PER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [per_dith5_mode](index.html) module"] +pub struct PER_DITH5_MODE_SPEC; +impl crate::RegisterSpec for PER_DITH5_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [per_dith5_mode::R](R) reader structure"] +impl crate::Readable for PER_DITH5_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [per_dith5_mode::W](W) writer structure"] +impl crate::Writable for PER_DITH5_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PER_DITH5_MODE to value 0xffff_ffff"] +impl crate::Resettable for PER_DITH5_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pac/atsamc20e/src/tcc0/per_dith6_mode.rs b/pac/atsamc20e/src/tcc0/per_dith6_mode.rs new file mode 100644 index 000000000000..67880e220a9c --- /dev/null +++ b/pac/atsamc20e/src/tcc0/per_dith6_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PER_DITH6_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PER_DITH6_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHER` reader - Dithering Cycle Number"] +pub struct DITHER_R(crate::FieldReader); +impl DITHER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHER` writer - Dithering Cycle Number"] +pub struct DITHER_W<'a> { + w: &'a mut W, +} +impl<'a> DITHER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +#[doc = "Field `PER` reader - Period Value"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` writer - Period Value"] +pub struct PER_W<'a> { + w: &'a mut W, +} +impl<'a> PER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0003_ffff << 6)) | ((value as u32 & 0x0003_ffff) << 6); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&self) -> DITHER_R { + DITHER_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:23 - Period Value"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(((self.bits >> 6) & 0x0003_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:5 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&mut self) -> DITHER_W { + DITHER_W { w: self } + } + #[doc = "Bits 6:23 - Period Value"] + #[inline(always)] + pub fn per(&mut self) -> PER_W { + PER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [per_dith6_mode](index.html) module"] +pub struct PER_DITH6_MODE_SPEC; +impl crate::RegisterSpec for PER_DITH6_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [per_dith6_mode::R](R) reader structure"] +impl crate::Readable for PER_DITH6_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [per_dith6_mode::W](W) writer structure"] +impl crate::Writable for PER_DITH6_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PER_DITH6_MODE to value 0xffff_ffff"] +impl crate::Resettable for PER_DITH6_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pac/atsamc20e/src/tcc0/perbuf.rs b/pac/atsamc20e/src/tcc0/perbuf.rs new file mode 100644 index 000000000000..169f17479616 --- /dev/null +++ b/pac/atsamc20e/src/tcc0/perbuf.rs @@ -0,0 +1,103 @@ +#[doc = "Register `PERBUF` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PERBUF` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PERBUF` reader - Period Buffer Value"] +pub struct PERBUF_R(crate::FieldReader); +impl PERBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + PERBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERBUF` writer - Period Buffer Value"] +pub struct PERBUF_W<'a> { + w: &'a mut W, +} +impl<'a> PERBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Period Buffer Value"] + #[inline(always)] + pub fn perbuf(&self) -> PERBUF_R { + PERBUF_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Period Buffer Value"] + #[inline(always)] + pub fn perbuf(&mut self) -> PERBUF_W { + PERBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [perbuf](index.html) module"] +pub struct PERBUF_SPEC; +impl crate::RegisterSpec for PERBUF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [perbuf::R](R) reader structure"] +impl crate::Readable for PERBUF_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [perbuf::W](W) writer structure"] +impl crate::Writable for PERBUF_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PERBUF to value 0xffff_ffff"] +impl crate::Resettable for PERBUF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pac/atsamc20e/src/tcc0/perbuf_dith4_mode.rs b/pac/atsamc20e/src/tcc0/perbuf_dith4_mode.rs new file mode 100644 index 000000000000..ccf96ecef185 --- /dev/null +++ b/pac/atsamc20e/src/tcc0/perbuf_dith4_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PERBUF_DITH4_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PERBUF_DITH4_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHERBUF` reader - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_R(crate::FieldReader); +impl DITHERBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHERBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHERBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHERBUF` writer - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_W<'a> { + w: &'a mut W, +} +impl<'a> DITHERBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Field `PERBUF` reader - Period Buffer Value"] +pub struct PERBUF_R(crate::FieldReader); +impl PERBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + PERBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERBUF` writer - Period Buffer Value"] +pub struct PERBUF_W<'a> { + w: &'a mut W, +} +impl<'a> PERBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x000f_ffff << 4)) | ((value as u32 & 0x000f_ffff) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&self) -> DITHERBUF_R { + DITHERBUF_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:23 - Period Buffer Value"] + #[inline(always)] + pub fn perbuf(&self) -> PERBUF_R { + PERBUF_R::new(((self.bits >> 4) & 0x000f_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:3 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&mut self) -> DITHERBUF_W { + DITHERBUF_W { w: self } + } + #[doc = "Bits 4:23 - Period Buffer Value"] + #[inline(always)] + pub fn perbuf(&mut self) -> PERBUF_W { + PERBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [perbuf_dith4_mode](index.html) module"] +pub struct PERBUF_DITH4_MODE_SPEC; +impl crate::RegisterSpec for PERBUF_DITH4_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [perbuf_dith4_mode::R](R) reader structure"] +impl crate::Readable for PERBUF_DITH4_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [perbuf_dith4_mode::W](W) writer structure"] +impl crate::Writable for PERBUF_DITH4_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PERBUF_DITH4_MODE to value 0xffff_ffff"] +impl crate::Resettable for PERBUF_DITH4_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pac/atsamc20e/src/tcc0/perbuf_dith5_mode.rs b/pac/atsamc20e/src/tcc0/perbuf_dith5_mode.rs new file mode 100644 index 000000000000..d55f6d52c5ba --- /dev/null +++ b/pac/atsamc20e/src/tcc0/perbuf_dith5_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PERBUF_DITH5_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PERBUF_DITH5_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHERBUF` reader - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_R(crate::FieldReader); +impl DITHERBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHERBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHERBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHERBUF` writer - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_W<'a> { + w: &'a mut W, +} +impl<'a> DITHERBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f); + self.w + } +} +#[doc = "Field `PERBUF` reader - Period Buffer Value"] +pub struct PERBUF_R(crate::FieldReader); +impl PERBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + PERBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERBUF` writer - Period Buffer Value"] +pub struct PERBUF_W<'a> { + w: &'a mut W, +} +impl<'a> PERBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0007_ffff << 5)) | ((value as u32 & 0x0007_ffff) << 5); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&self) -> DITHERBUF_R { + DITHERBUF_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:23 - Period Buffer Value"] + #[inline(always)] + pub fn perbuf(&self) -> PERBUF_R { + PERBUF_R::new(((self.bits >> 5) & 0x0007_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:4 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&mut self) -> DITHERBUF_W { + DITHERBUF_W { w: self } + } + #[doc = "Bits 5:23 - Period Buffer Value"] + #[inline(always)] + pub fn perbuf(&mut self) -> PERBUF_W { + PERBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [perbuf_dith5_mode](index.html) module"] +pub struct PERBUF_DITH5_MODE_SPEC; +impl crate::RegisterSpec for PERBUF_DITH5_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [perbuf_dith5_mode::R](R) reader structure"] +impl crate::Readable for PERBUF_DITH5_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [perbuf_dith5_mode::W](W) writer structure"] +impl crate::Writable for PERBUF_DITH5_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PERBUF_DITH5_MODE to value 0xffff_ffff"] +impl crate::Resettable for PERBUF_DITH5_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pac/atsamc20e/src/tcc0/perbuf_dith6_mode.rs b/pac/atsamc20e/src/tcc0/perbuf_dith6_mode.rs new file mode 100644 index 000000000000..983c849f9073 --- /dev/null +++ b/pac/atsamc20e/src/tcc0/perbuf_dith6_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PERBUF_DITH6_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PERBUF_DITH6_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHERBUF` reader - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_R(crate::FieldReader); +impl DITHERBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHERBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHERBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHERBUF` writer - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_W<'a> { + w: &'a mut W, +} +impl<'a> DITHERBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +#[doc = "Field `PERBUF` reader - Period Buffer Value"] +pub struct PERBUF_R(crate::FieldReader); +impl PERBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + PERBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERBUF` writer - Period Buffer Value"] +pub struct PERBUF_W<'a> { + w: &'a mut W, +} +impl<'a> PERBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0003_ffff << 6)) | ((value as u32 & 0x0003_ffff) << 6); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&self) -> DITHERBUF_R { + DITHERBUF_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:23 - Period Buffer Value"] + #[inline(always)] + pub fn perbuf(&self) -> PERBUF_R { + PERBUF_R::new(((self.bits >> 6) & 0x0003_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:5 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&mut self) -> DITHERBUF_W { + DITHERBUF_W { w: self } + } + #[doc = "Bits 6:23 - Period Buffer Value"] + #[inline(always)] + pub fn perbuf(&mut self) -> PERBUF_W { + PERBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [perbuf_dith6_mode](index.html) module"] +pub struct PERBUF_DITH6_MODE_SPEC; +impl crate::RegisterSpec for PERBUF_DITH6_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [perbuf_dith6_mode::R](R) reader structure"] +impl crate::Readable for PERBUF_DITH6_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [perbuf_dith6_mode::W](W) writer structure"] +impl crate::Writable for PERBUF_DITH6_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PERBUF_DITH6_MODE to value 0xffff_ffff"] +impl crate::Resettable for PERBUF_DITH6_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pac/atsamc20e/src/tcc0/status.rs b/pac/atsamc20e/src/tcc0/status.rs new file mode 100644 index 000000000000..eecd909e6093 --- /dev/null +++ b/pac/atsamc20e/src/tcc0/status.rs @@ -0,0 +1,1147 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `STOP` reader - Stop"] +pub struct STOP_R(crate::FieldReader); +impl STOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STOP` writer - Stop"] +pub struct STOP_W<'a> { + w: &'a mut W, +} +impl<'a> STOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `IDX` reader - Ramp"] +pub struct IDX_R(crate::FieldReader); +impl IDX_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IDX_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IDX_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IDX` writer - Ramp"] +pub struct IDX_W<'a> { + w: &'a mut W, +} +impl<'a> IDX_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `UFS` reader - Non-recoverable Update Fault State"] +pub struct UFS_R(crate::FieldReader); +impl UFS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UFS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for UFS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `UFS` writer - Non-recoverable Update Fault State"] +pub struct UFS_W<'a> { + w: &'a mut W, +} +impl<'a> UFS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `DFS` reader - Non-Recoverable Debug Fault State"] +pub struct DFS_R(crate::FieldReader); +impl DFS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFS` writer - Non-Recoverable Debug Fault State"] +pub struct DFS_W<'a> { + w: &'a mut W, +} +impl<'a> DFS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `SLAVE` reader - Slave"] +pub struct SLAVE_R(crate::FieldReader); +impl SLAVE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLAVE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SLAVE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLAVE` writer - Slave"] +pub struct SLAVE_W<'a> { + w: &'a mut W, +} +impl<'a> SLAVE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PATTBUFV` reader - Pattern Buffer Valid"] +pub struct PATTBUFV_R(crate::FieldReader); +impl PATTBUFV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PATTBUFV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PATTBUFV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PATTBUFV` writer - Pattern Buffer Valid"] +pub struct PATTBUFV_W<'a> { + w: &'a mut W, +} +impl<'a> PATTBUFV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PERBUFV` reader - Period Buffer Valid"] +pub struct PERBUFV_R(crate::FieldReader); +impl PERBUFV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PERBUFV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERBUFV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERBUFV` writer - Period Buffer Valid"] +pub struct PERBUFV_W<'a> { + w: &'a mut W, +} +impl<'a> PERBUFV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `FAULTAIN` reader - Recoverable Fault A Input"] +pub struct FAULTAIN_R(crate::FieldReader); +impl FAULTAIN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTAIN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTAIN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTAIN` writer - Recoverable Fault A Input"] +pub struct FAULTAIN_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTAIN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `FAULTBIN` reader - Recoverable Fault B Input"] +pub struct FAULTBIN_R(crate::FieldReader); +impl FAULTBIN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTBIN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTBIN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTBIN` writer - Recoverable Fault B Input"] +pub struct FAULTBIN_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTBIN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `FAULT0IN` reader - Non-Recoverable Fault0 Input"] +pub struct FAULT0IN_R(crate::FieldReader); +impl FAULT0IN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT0IN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT0IN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT0IN` writer - Non-Recoverable Fault0 Input"] +pub struct FAULT0IN_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT0IN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `FAULT1IN` reader - Non-Recoverable Fault1 Input"] +pub struct FAULT1IN_R(crate::FieldReader); +impl FAULT1IN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT1IN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT1IN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT1IN` writer - Non-Recoverable Fault1 Input"] +pub struct FAULT1IN_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT1IN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `FAULTA` reader - Recoverable Fault A State"] +pub struct FAULTA_R(crate::FieldReader); +impl FAULTA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTA` writer - Recoverable Fault A State"] +pub struct FAULTA_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `FAULTB` reader - Recoverable Fault B State"] +pub struct FAULTB_R(crate::FieldReader); +impl FAULTB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTB` writer - Recoverable Fault B State"] +pub struct FAULTB_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `FAULT0` reader - Non-Recoverable Fault 0 State"] +pub struct FAULT0_R(crate::FieldReader); +impl FAULT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT0` writer - Non-Recoverable Fault 0 State"] +pub struct FAULT0_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `FAULT1` reader - Non-Recoverable Fault 1 State"] +pub struct FAULT1_R(crate::FieldReader); +impl FAULT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT1` writer - Non-Recoverable Fault 1 State"] +pub struct FAULT1_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `CCBUFV0` reader - Compare Channel 0 Buffer Valid"] +pub struct CCBUFV0_R(crate::FieldReader); +impl CCBUFV0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBUFV0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUFV0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUFV0` writer - Compare Channel 0 Buffer Valid"] +pub struct CCBUFV0_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUFV0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `CCBUFV1` reader - Compare Channel 1 Buffer Valid"] +pub struct CCBUFV1_R(crate::FieldReader); +impl CCBUFV1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBUFV1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUFV1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUFV1` writer - Compare Channel 1 Buffer Valid"] +pub struct CCBUFV1_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUFV1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `CCBUFV2` reader - Compare Channel 2 Buffer Valid"] +pub struct CCBUFV2_R(crate::FieldReader); +impl CCBUFV2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBUFV2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUFV2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUFV2` writer - Compare Channel 2 Buffer Valid"] +pub struct CCBUFV2_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUFV2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `CCBUFV3` reader - Compare Channel 3 Buffer Valid"] +pub struct CCBUFV3_R(crate::FieldReader); +impl CCBUFV3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBUFV3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUFV3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUFV3` writer - Compare Channel 3 Buffer Valid"] +pub struct CCBUFV3_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUFV3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `CMP0` reader - Compare Channel 0 Value"] +pub struct CMP0_R(crate::FieldReader); +impl CMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP0` writer - Compare Channel 0 Value"] +pub struct CMP0_W<'a> { + w: &'a mut W, +} +impl<'a> CMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `CMP1` reader - Compare Channel 1 Value"] +pub struct CMP1_R(crate::FieldReader); +impl CMP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP1` writer - Compare Channel 1 Value"] +pub struct CMP1_W<'a> { + w: &'a mut W, +} +impl<'a> CMP1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `CMP2` reader - Compare Channel 2 Value"] +pub struct CMP2_R(crate::FieldReader); +impl CMP2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP2` writer - Compare Channel 2 Value"] +pub struct CMP2_W<'a> { + w: &'a mut W, +} +impl<'a> CMP2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `CMP3` reader - Compare Channel 3 Value"] +pub struct CMP3_R(crate::FieldReader); +impl CMP3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP3` writer - Compare Channel 3 Value"] +pub struct CMP3_W<'a> { + w: &'a mut W, +} +impl<'a> CMP3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +impl R { + #[doc = "Bit 0 - Stop"] + #[inline(always)] + pub fn stop(&self) -> STOP_R { + STOP_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Ramp"] + #[inline(always)] + pub fn idx(&self) -> IDX_R { + IDX_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Non-recoverable Update Fault State"] + #[inline(always)] + pub fn ufs(&self) -> UFS_R { + UFS_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Non-Recoverable Debug Fault State"] + #[inline(always)] + pub fn dfs(&self) -> DFS_R { + DFS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Slave"] + #[inline(always)] + pub fn slave(&self) -> SLAVE_R { + SLAVE_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Pattern Buffer Valid"] + #[inline(always)] + pub fn pattbufv(&self) -> PATTBUFV_R { + PATTBUFV_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 7 - Period Buffer Valid"] + #[inline(always)] + pub fn perbufv(&self) -> PERBUFV_R { + PERBUFV_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Recoverable Fault A Input"] + #[inline(always)] + pub fn faultain(&self) -> FAULTAIN_R { + FAULTAIN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Recoverable Fault B Input"] + #[inline(always)] + pub fn faultbin(&self) -> FAULTBIN_R { + FAULTBIN_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Non-Recoverable Fault0 Input"] + #[inline(always)] + pub fn fault0in(&self) -> FAULT0IN_R { + FAULT0IN_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Non-Recoverable Fault1 Input"] + #[inline(always)] + pub fn fault1in(&self) -> FAULT1IN_R { + FAULT1IN_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Recoverable Fault A State"] + #[inline(always)] + pub fn faulta(&self) -> FAULTA_R { + FAULTA_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Recoverable Fault B State"] + #[inline(always)] + pub fn faultb(&self) -> FAULTB_R { + FAULTB_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Non-Recoverable Fault 0 State"] + #[inline(always)] + pub fn fault0(&self) -> FAULT0_R { + FAULT0_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Non-Recoverable Fault 1 State"] + #[inline(always)] + pub fn fault1(&self) -> FAULT1_R { + FAULT1_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Compare Channel 0 Buffer Valid"] + #[inline(always)] + pub fn ccbufv0(&self) -> CCBUFV0_R { + CCBUFV0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Compare Channel 1 Buffer Valid"] + #[inline(always)] + pub fn ccbufv1(&self) -> CCBUFV1_R { + CCBUFV1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Compare Channel 2 Buffer Valid"] + #[inline(always)] + pub fn ccbufv2(&self) -> CCBUFV2_R { + CCBUFV2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Compare Channel 3 Buffer Valid"] + #[inline(always)] + pub fn ccbufv3(&self) -> CCBUFV3_R { + CCBUFV3_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 24 - Compare Channel 0 Value"] + #[inline(always)] + pub fn cmp0(&self) -> CMP0_R { + CMP0_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Compare Channel 1 Value"] + #[inline(always)] + pub fn cmp1(&self) -> CMP1_R { + CMP1_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Compare Channel 2 Value"] + #[inline(always)] + pub fn cmp2(&self) -> CMP2_R { + CMP2_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Compare Channel 3 Value"] + #[inline(always)] + pub fn cmp3(&self) -> CMP3_R { + CMP3_R::new(((self.bits >> 27) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Stop"] + #[inline(always)] + pub fn stop(&mut self) -> STOP_W { + STOP_W { w: self } + } + #[doc = "Bit 1 - Ramp"] + #[inline(always)] + pub fn idx(&mut self) -> IDX_W { + IDX_W { w: self } + } + #[doc = "Bit 2 - Non-recoverable Update Fault State"] + #[inline(always)] + pub fn ufs(&mut self) -> UFS_W { + UFS_W { w: self } + } + #[doc = "Bit 3 - Non-Recoverable Debug Fault State"] + #[inline(always)] + pub fn dfs(&mut self) -> DFS_W { + DFS_W { w: self } + } + #[doc = "Bit 4 - Slave"] + #[inline(always)] + pub fn slave(&mut self) -> SLAVE_W { + SLAVE_W { w: self } + } + #[doc = "Bit 5 - Pattern Buffer Valid"] + #[inline(always)] + pub fn pattbufv(&mut self) -> PATTBUFV_W { + PATTBUFV_W { w: self } + } + #[doc = "Bit 7 - Period Buffer Valid"] + #[inline(always)] + pub fn perbufv(&mut self) -> PERBUFV_W { + PERBUFV_W { w: self } + } + #[doc = "Bit 8 - Recoverable Fault A Input"] + #[inline(always)] + pub fn faultain(&mut self) -> FAULTAIN_W { + FAULTAIN_W { w: self } + } + #[doc = "Bit 9 - Recoverable Fault B Input"] + #[inline(always)] + pub fn faultbin(&mut self) -> FAULTBIN_W { + FAULTBIN_W { w: self } + } + #[doc = "Bit 10 - Non-Recoverable Fault0 Input"] + #[inline(always)] + pub fn fault0in(&mut self) -> FAULT0IN_W { + FAULT0IN_W { w: self } + } + #[doc = "Bit 11 - Non-Recoverable Fault1 Input"] + #[inline(always)] + pub fn fault1in(&mut self) -> FAULT1IN_W { + FAULT1IN_W { w: self } + } + #[doc = "Bit 12 - Recoverable Fault A State"] + #[inline(always)] + pub fn faulta(&mut self) -> FAULTA_W { + FAULTA_W { w: self } + } + #[doc = "Bit 13 - Recoverable Fault B State"] + #[inline(always)] + pub fn faultb(&mut self) -> FAULTB_W { + FAULTB_W { w: self } + } + #[doc = "Bit 14 - Non-Recoverable Fault 0 State"] + #[inline(always)] + pub fn fault0(&mut self) -> FAULT0_W { + FAULT0_W { w: self } + } + #[doc = "Bit 15 - Non-Recoverable Fault 1 State"] + #[inline(always)] + pub fn fault1(&mut self) -> FAULT1_W { + FAULT1_W { w: self } + } + #[doc = "Bit 16 - Compare Channel 0 Buffer Valid"] + #[inline(always)] + pub fn ccbufv0(&mut self) -> CCBUFV0_W { + CCBUFV0_W { w: self } + } + #[doc = "Bit 17 - Compare Channel 1 Buffer Valid"] + #[inline(always)] + pub fn ccbufv1(&mut self) -> CCBUFV1_W { + CCBUFV1_W { w: self } + } + #[doc = "Bit 18 - Compare Channel 2 Buffer Valid"] + #[inline(always)] + pub fn ccbufv2(&mut self) -> CCBUFV2_W { + CCBUFV2_W { w: self } + } + #[doc = "Bit 19 - Compare Channel 3 Buffer Valid"] + #[inline(always)] + pub fn ccbufv3(&mut self) -> CCBUFV3_W { + CCBUFV3_W { w: self } + } + #[doc = "Bit 24 - Compare Channel 0 Value"] + #[inline(always)] + pub fn cmp0(&mut self) -> CMP0_W { + CMP0_W { w: self } + } + #[doc = "Bit 25 - Compare Channel 1 Value"] + #[inline(always)] + pub fn cmp1(&mut self) -> CMP1_W { + CMP1_W { w: self } + } + #[doc = "Bit 26 - Compare Channel 2 Value"] + #[inline(always)] + pub fn cmp2(&mut self) -> CMP2_W { + CMP2_W { w: self } + } + #[doc = "Bit 27 - Compare Channel 3 Value"] + #[inline(always)] + pub fn cmp3(&mut self) -> CMP3_W { + CMP3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0x01"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pac/atsamc20e/src/tcc0/syncbusy.rs b/pac/atsamc20e/src/tcc0/syncbusy.rs new file mode 100644 index 000000000000..db0788c3f206 --- /dev/null +++ b/pac/atsamc20e/src/tcc0/syncbusy.rs @@ -0,0 +1,273 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Swrst Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - Enable Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLB` reader - Ctrlb Busy"] +pub struct CTRLB_R(crate::FieldReader); +impl CTRLB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STATUS` reader - Status Busy"] +pub struct STATUS_R(crate::FieldReader); +impl STATUS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STATUS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STATUS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` reader - Count Busy"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PATT` reader - Pattern Busy"] +pub struct PATT_R(crate::FieldReader); +impl PATT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PATT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PATT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAVE` reader - Wave Busy"] +pub struct WAVE_R(crate::FieldReader); +impl WAVE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAVE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAVE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` reader - Period Busy"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC0` reader - Compare Channel 0 Busy"] +pub struct CC0_R(crate::FieldReader); +impl CC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC1` reader - Compare Channel 1 Busy"] +pub struct CC1_R(crate::FieldReader); +impl CC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC2` reader - Compare Channel 2 Busy"] +pub struct CC2_R(crate::FieldReader); +impl CC2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC3` reader - Compare Channel 3 Busy"] +pub struct CC3_R(crate::FieldReader); +impl CC3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Swrst Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Ctrlb Busy"] + #[inline(always)] + pub fn ctrlb(&self) -> CTRLB_R { + CTRLB_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Status Busy"] + #[inline(always)] + pub fn status(&self) -> STATUS_R { + STATUS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Count Busy"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Pattern Busy"] + #[inline(always)] + pub fn patt(&self) -> PATT_R { + PATT_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Wave Busy"] + #[inline(always)] + pub fn wave(&self) -> WAVE_R { + WAVE_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Period Busy"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Compare Channel 0 Busy"] + #[inline(always)] + pub fn cc0(&self) -> CC0_R { + CC0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Compare Channel 1 Busy"] + #[inline(always)] + pub fn cc1(&self) -> CC1_R { + CC1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Compare Channel 2 Busy"] + #[inline(always)] + pub fn cc2(&self) -> CC2_R { + CC2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Compare Channel 3 Busy"] + #[inline(always)] + pub fn cc3(&self) -> CC3_R { + CC3_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +#[doc = "Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/tcc0/wave.rs b/pac/atsamc20e/src/tcc0/wave.rs new file mode 100644 index 000000000000..8d092d429a91 --- /dev/null +++ b/pac/atsamc20e/src/tcc0/wave.rs @@ -0,0 +1,940 @@ +#[doc = "Register `WAVE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WAVE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Waveform Generation\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WAVEGEN_A { + #[doc = "0: Normal frequency"] + NFRQ = 0, + #[doc = "1: Match frequency"] + MFRQ = 1, + #[doc = "2: Normal PWM"] + NPWM = 2, + #[doc = "4: Dual-slope critical"] + DSCRITICAL = 4, + #[doc = "5: Dual-slope with interrupt/event condition when COUNT reaches ZERO"] + DSBOTTOM = 5, + #[doc = "6: Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP"] + DSBOTH = 6, + #[doc = "7: Dual-slope with interrupt/event condition when COUNT reaches TOP"] + DSTOP = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WAVEGEN_A) -> Self { + variant as _ + } +} +#[doc = "Field `WAVEGEN` reader - Waveform Generation"] +pub struct WAVEGEN_R(crate::FieldReader); +impl WAVEGEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WAVEGEN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(WAVEGEN_A::NFRQ), + 1 => Some(WAVEGEN_A::MFRQ), + 2 => Some(WAVEGEN_A::NPWM), + 4 => Some(WAVEGEN_A::DSCRITICAL), + 5 => Some(WAVEGEN_A::DSBOTTOM), + 6 => Some(WAVEGEN_A::DSBOTH), + 7 => Some(WAVEGEN_A::DSTOP), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NFRQ`"] + #[inline(always)] + pub fn is_nfrq(&self) -> bool { + **self == WAVEGEN_A::NFRQ + } + #[doc = "Checks if the value of the field is `MFRQ`"] + #[inline(always)] + pub fn is_mfrq(&self) -> bool { + **self == WAVEGEN_A::MFRQ + } + #[doc = "Checks if the value of the field is `NPWM`"] + #[inline(always)] + pub fn is_npwm(&self) -> bool { + **self == WAVEGEN_A::NPWM + } + #[doc = "Checks if the value of the field is `DSCRITICAL`"] + #[inline(always)] + pub fn is_dscritical(&self) -> bool { + **self == WAVEGEN_A::DSCRITICAL + } + #[doc = "Checks if the value of the field is `DSBOTTOM`"] + #[inline(always)] + pub fn is_dsbottom(&self) -> bool { + **self == WAVEGEN_A::DSBOTTOM + } + #[doc = "Checks if the value of the field is `DSBOTH`"] + #[inline(always)] + pub fn is_dsboth(&self) -> bool { + **self == WAVEGEN_A::DSBOTH + } + #[doc = "Checks if the value of the field is `DSTOP`"] + #[inline(always)] + pub fn is_dstop(&self) -> bool { + **self == WAVEGEN_A::DSTOP + } +} +impl core::ops::Deref for WAVEGEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAVEGEN` writer - Waveform Generation"] +pub struct WAVEGEN_W<'a> { + w: &'a mut W, +} +impl<'a> WAVEGEN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WAVEGEN_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Normal frequency"] + #[inline(always)] + pub fn nfrq(self) -> &'a mut W { + self.variant(WAVEGEN_A::NFRQ) + } + #[doc = "Match frequency"] + #[inline(always)] + pub fn mfrq(self) -> &'a mut W { + self.variant(WAVEGEN_A::MFRQ) + } + #[doc = "Normal PWM"] + #[inline(always)] + pub fn npwm(self) -> &'a mut W { + self.variant(WAVEGEN_A::NPWM) + } + #[doc = "Dual-slope critical"] + #[inline(always)] + pub fn dscritical(self) -> &'a mut W { + self.variant(WAVEGEN_A::DSCRITICAL) + } + #[doc = "Dual-slope with interrupt/event condition when COUNT reaches ZERO"] + #[inline(always)] + pub fn dsbottom(self) -> &'a mut W { + self.variant(WAVEGEN_A::DSBOTTOM) + } + #[doc = "Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP"] + #[inline(always)] + pub fn dsboth(self) -> &'a mut W { + self.variant(WAVEGEN_A::DSBOTH) + } + #[doc = "Dual-slope with interrupt/event condition when COUNT reaches TOP"] + #[inline(always)] + pub fn dstop(self) -> &'a mut W { + self.variant(WAVEGEN_A::DSTOP) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Ramp Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum RAMP_A { + #[doc = "0: RAMP1 operation"] + RAMP1 = 0, + #[doc = "1: Alternative RAMP2 operation"] + RAMP2A = 1, + #[doc = "2: RAMP2 operation"] + RAMP2 = 2, + #[doc = "3: Critical RAMP2 operation"] + RAMP2C = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RAMP_A) -> Self { + variant as _ + } +} +#[doc = "Field `RAMP` reader - Ramp Mode"] +pub struct RAMP_R(crate::FieldReader); +impl RAMP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RAMP_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RAMP_A { + match self.bits { + 0 => RAMP_A::RAMP1, + 1 => RAMP_A::RAMP2A, + 2 => RAMP_A::RAMP2, + 3 => RAMP_A::RAMP2C, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `RAMP1`"] + #[inline(always)] + pub fn is_ramp1(&self) -> bool { + **self == RAMP_A::RAMP1 + } + #[doc = "Checks if the value of the field is `RAMP2A`"] + #[inline(always)] + pub fn is_ramp2a(&self) -> bool { + **self == RAMP_A::RAMP2A + } + #[doc = "Checks if the value of the field is `RAMP2`"] + #[inline(always)] + pub fn is_ramp2(&self) -> bool { + **self == RAMP_A::RAMP2 + } + #[doc = "Checks if the value of the field is `RAMP2C`"] + #[inline(always)] + pub fn is_ramp2c(&self) -> bool { + **self == RAMP_A::RAMP2C + } +} +impl core::ops::Deref for RAMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RAMP` writer - Ramp Mode"] +pub struct RAMP_W<'a> { + w: &'a mut W, +} +impl<'a> RAMP_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RAMP_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "RAMP1 operation"] + #[inline(always)] + pub fn ramp1(self) -> &'a mut W { + self.variant(RAMP_A::RAMP1) + } + #[doc = "Alternative RAMP2 operation"] + #[inline(always)] + pub fn ramp2a(self) -> &'a mut W { + self.variant(RAMP_A::RAMP2A) + } + #[doc = "RAMP2 operation"] + #[inline(always)] + pub fn ramp2(self) -> &'a mut W { + self.variant(RAMP_A::RAMP2) + } + #[doc = "Critical RAMP2 operation"] + #[inline(always)] + pub fn ramp2c(self) -> &'a mut W { + self.variant(RAMP_A::RAMP2C) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u32 & 0x03) << 4); + self.w + } +} +#[doc = "Field `CIPEREN` reader - Circular period Enable"] +pub struct CIPEREN_R(crate::FieldReader); +impl CIPEREN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CIPEREN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CIPEREN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CIPEREN` writer - Circular period Enable"] +pub struct CIPEREN_W<'a> { + w: &'a mut W, +} +impl<'a> CIPEREN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CICCEN0` reader - Circular Channel 0 Enable"] +pub struct CICCEN0_R(crate::FieldReader); +impl CICCEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CICCEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CICCEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CICCEN0` writer - Circular Channel 0 Enable"] +pub struct CICCEN0_W<'a> { + w: &'a mut W, +} +impl<'a> CICCEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `CICCEN1` reader - Circular Channel 1 Enable"] +pub struct CICCEN1_R(crate::FieldReader); +impl CICCEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CICCEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CICCEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CICCEN1` writer - Circular Channel 1 Enable"] +pub struct CICCEN1_W<'a> { + w: &'a mut W, +} +impl<'a> CICCEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `CICCEN2` reader - Circular Channel 2 Enable"] +pub struct CICCEN2_R(crate::FieldReader); +impl CICCEN2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CICCEN2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CICCEN2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CICCEN2` writer - Circular Channel 2 Enable"] +pub struct CICCEN2_W<'a> { + w: &'a mut W, +} +impl<'a> CICCEN2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `CICCEN3` reader - Circular Channel 3 Enable"] +pub struct CICCEN3_R(crate::FieldReader); +impl CICCEN3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CICCEN3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CICCEN3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CICCEN3` writer - Circular Channel 3 Enable"] +pub struct CICCEN3_W<'a> { + w: &'a mut W, +} +impl<'a> CICCEN3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `POL0` reader - Channel 0 Polarity"] +pub struct POL0_R(crate::FieldReader); +impl POL0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + POL0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for POL0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `POL0` writer - Channel 0 Polarity"] +pub struct POL0_W<'a> { + w: &'a mut W, +} +impl<'a> POL0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `POL1` reader - Channel 1 Polarity"] +pub struct POL1_R(crate::FieldReader); +impl POL1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + POL1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for POL1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `POL1` writer - Channel 1 Polarity"] +pub struct POL1_W<'a> { + w: &'a mut W, +} +impl<'a> POL1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `POL2` reader - Channel 2 Polarity"] +pub struct POL2_R(crate::FieldReader); +impl POL2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + POL2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for POL2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `POL2` writer - Channel 2 Polarity"] +pub struct POL2_W<'a> { + w: &'a mut W, +} +impl<'a> POL2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `POL3` reader - Channel 3 Polarity"] +pub struct POL3_R(crate::FieldReader); +impl POL3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + POL3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for POL3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `POL3` writer - Channel 3 Polarity"] +pub struct POL3_W<'a> { + w: &'a mut W, +} +impl<'a> POL3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `SWAP0` reader - Swap DTI Output Pair 0"] +pub struct SWAP0_R(crate::FieldReader); +impl SWAP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWAP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWAP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWAP0` writer - Swap DTI Output Pair 0"] +pub struct SWAP0_W<'a> { + w: &'a mut W, +} +impl<'a> SWAP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `SWAP1` reader - Swap DTI Output Pair 1"] +pub struct SWAP1_R(crate::FieldReader); +impl SWAP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWAP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWAP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWAP1` writer - Swap DTI Output Pair 1"] +pub struct SWAP1_W<'a> { + w: &'a mut W, +} +impl<'a> SWAP1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `SWAP2` reader - Swap DTI Output Pair 2"] +pub struct SWAP2_R(crate::FieldReader); +impl SWAP2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWAP2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWAP2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWAP2` writer - Swap DTI Output Pair 2"] +pub struct SWAP2_W<'a> { + w: &'a mut W, +} +impl<'a> SWAP2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `SWAP3` reader - Swap DTI Output Pair 3"] +pub struct SWAP3_R(crate::FieldReader); +impl SWAP3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWAP3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWAP3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWAP3` writer - Swap DTI Output Pair 3"] +pub struct SWAP3_W<'a> { + w: &'a mut W, +} +impl<'a> SWAP3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Waveform Generation"] + #[inline(always)] + pub fn wavegen(&self) -> WAVEGEN_R { + WAVEGEN_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bits 4:5 - Ramp Mode"] + #[inline(always)] + pub fn ramp(&self) -> RAMP_R { + RAMP_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bit 7 - Circular period Enable"] + #[inline(always)] + pub fn ciperen(&self) -> CIPEREN_R { + CIPEREN_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Circular Channel 0 Enable"] + #[inline(always)] + pub fn ciccen0(&self) -> CICCEN0_R { + CICCEN0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Circular Channel 1 Enable"] + #[inline(always)] + pub fn ciccen1(&self) -> CICCEN1_R { + CICCEN1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Circular Channel 2 Enable"] + #[inline(always)] + pub fn ciccen2(&self) -> CICCEN2_R { + CICCEN2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Circular Channel 3 Enable"] + #[inline(always)] + pub fn ciccen3(&self) -> CICCEN3_R { + CICCEN3_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 16 - Channel 0 Polarity"] + #[inline(always)] + pub fn pol0(&self) -> POL0_R { + POL0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Channel 1 Polarity"] + #[inline(always)] + pub fn pol1(&self) -> POL1_R { + POL1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Channel 2 Polarity"] + #[inline(always)] + pub fn pol2(&self) -> POL2_R { + POL2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Channel 3 Polarity"] + #[inline(always)] + pub fn pol3(&self) -> POL3_R { + POL3_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 24 - Swap DTI Output Pair 0"] + #[inline(always)] + pub fn swap0(&self) -> SWAP0_R { + SWAP0_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Swap DTI Output Pair 1"] + #[inline(always)] + pub fn swap1(&self) -> SWAP1_R { + SWAP1_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Swap DTI Output Pair 2"] + #[inline(always)] + pub fn swap2(&self) -> SWAP2_R { + SWAP2_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Swap DTI Output Pair 3"] + #[inline(always)] + pub fn swap3(&self) -> SWAP3_R { + SWAP3_R::new(((self.bits >> 27) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Waveform Generation"] + #[inline(always)] + pub fn wavegen(&mut self) -> WAVEGEN_W { + WAVEGEN_W { w: self } + } + #[doc = "Bits 4:5 - Ramp Mode"] + #[inline(always)] + pub fn ramp(&mut self) -> RAMP_W { + RAMP_W { w: self } + } + #[doc = "Bit 7 - Circular period Enable"] + #[inline(always)] + pub fn ciperen(&mut self) -> CIPEREN_W { + CIPEREN_W { w: self } + } + #[doc = "Bit 8 - Circular Channel 0 Enable"] + #[inline(always)] + pub fn ciccen0(&mut self) -> CICCEN0_W { + CICCEN0_W { w: self } + } + #[doc = "Bit 9 - Circular Channel 1 Enable"] + #[inline(always)] + pub fn ciccen1(&mut self) -> CICCEN1_W { + CICCEN1_W { w: self } + } + #[doc = "Bit 10 - Circular Channel 2 Enable"] + #[inline(always)] + pub fn ciccen2(&mut self) -> CICCEN2_W { + CICCEN2_W { w: self } + } + #[doc = "Bit 11 - Circular Channel 3 Enable"] + #[inline(always)] + pub fn ciccen3(&mut self) -> CICCEN3_W { + CICCEN3_W { w: self } + } + #[doc = "Bit 16 - Channel 0 Polarity"] + #[inline(always)] + pub fn pol0(&mut self) -> POL0_W { + POL0_W { w: self } + } + #[doc = "Bit 17 - Channel 1 Polarity"] + #[inline(always)] + pub fn pol1(&mut self) -> POL1_W { + POL1_W { w: self } + } + #[doc = "Bit 18 - Channel 2 Polarity"] + #[inline(always)] + pub fn pol2(&mut self) -> POL2_W { + POL2_W { w: self } + } + #[doc = "Bit 19 - Channel 3 Polarity"] + #[inline(always)] + pub fn pol3(&mut self) -> POL3_W { + POL3_W { w: self } + } + #[doc = "Bit 24 - Swap DTI Output Pair 0"] + #[inline(always)] + pub fn swap0(&mut self) -> SWAP0_W { + SWAP0_W { w: self } + } + #[doc = "Bit 25 - Swap DTI Output Pair 1"] + #[inline(always)] + pub fn swap1(&mut self) -> SWAP1_W { + SWAP1_W { w: self } + } + #[doc = "Bit 26 - Swap DTI Output Pair 2"] + #[inline(always)] + pub fn swap2(&mut self) -> SWAP2_W { + SWAP2_W { w: self } + } + #[doc = "Bit 27 - Swap DTI Output Pair 3"] + #[inline(always)] + pub fn swap3(&mut self) -> SWAP3_W { + SWAP3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Waveform Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wave](index.html) module"] +pub struct WAVE_SPEC; +impl crate::RegisterSpec for WAVE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [wave::R](R) reader structure"] +impl crate::Readable for WAVE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wave::W](W) writer structure"] +impl crate::Writable for WAVE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WAVE to value 0"] +impl crate::Resettable for WAVE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/tcc0/wexctrl.rs b/pac/atsamc20e/src/tcc0/wexctrl.rs new file mode 100644 index 000000000000..8eb0d29cbee5 --- /dev/null +++ b/pac/atsamc20e/src/tcc0/wexctrl.rs @@ -0,0 +1,365 @@ +#[doc = "Register `WEXCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WEXCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OTMX` reader - Output Matrix"] +pub struct OTMX_R(crate::FieldReader); +impl OTMX_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + OTMX_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OTMX_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OTMX` writer - Output Matrix"] +pub struct OTMX_W<'a> { + w: &'a mut W, +} +impl<'a> OTMX_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u32 & 0x03); + self.w + } +} +#[doc = "Field `DTIEN0` reader - Dead-time Insertion Generator 0 Enable"] +pub struct DTIEN0_R(crate::FieldReader); +impl DTIEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DTIEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DTIEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DTIEN0` writer - Dead-time Insertion Generator 0 Enable"] +pub struct DTIEN0_W<'a> { + w: &'a mut W, +} +impl<'a> DTIEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `DTIEN1` reader - Dead-time Insertion Generator 1 Enable"] +pub struct DTIEN1_R(crate::FieldReader); +impl DTIEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DTIEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DTIEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DTIEN1` writer - Dead-time Insertion Generator 1 Enable"] +pub struct DTIEN1_W<'a> { + w: &'a mut W, +} +impl<'a> DTIEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `DTIEN2` reader - Dead-time Insertion Generator 2 Enable"] +pub struct DTIEN2_R(crate::FieldReader); +impl DTIEN2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DTIEN2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DTIEN2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DTIEN2` writer - Dead-time Insertion Generator 2 Enable"] +pub struct DTIEN2_W<'a> { + w: &'a mut W, +} +impl<'a> DTIEN2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `DTIEN3` reader - Dead-time Insertion Generator 3 Enable"] +pub struct DTIEN3_R(crate::FieldReader); +impl DTIEN3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DTIEN3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DTIEN3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DTIEN3` writer - Dead-time Insertion Generator 3 Enable"] +pub struct DTIEN3_W<'a> { + w: &'a mut W, +} +impl<'a> DTIEN3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `DTLS` reader - Dead-time Low Side Outputs Value"] +pub struct DTLS_R(crate::FieldReader); +impl DTLS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DTLS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DTLS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DTLS` writer - Dead-time Low Side Outputs Value"] +pub struct DTLS_W<'a> { + w: &'a mut W, +} +impl<'a> DTLS_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +#[doc = "Field `DTHS` reader - Dead-time High Side Outputs Value"] +pub struct DTHS_R(crate::FieldReader); +impl DTHS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DTHS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DTHS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DTHS` writer - Dead-time High Side Outputs Value"] +pub struct DTHS_W<'a> { + w: &'a mut W, +} +impl<'a> DTHS_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 24)) | ((value as u32 & 0xff) << 24); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Output Matrix"] + #[inline(always)] + pub fn otmx(&self) -> OTMX_R { + OTMX_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bit 8 - Dead-time Insertion Generator 0 Enable"] + #[inline(always)] + pub fn dtien0(&self) -> DTIEN0_R { + DTIEN0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Dead-time Insertion Generator 1 Enable"] + #[inline(always)] + pub fn dtien1(&self) -> DTIEN1_R { + DTIEN1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Dead-time Insertion Generator 2 Enable"] + #[inline(always)] + pub fn dtien2(&self) -> DTIEN2_R { + DTIEN2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Dead-time Insertion Generator 3 Enable"] + #[inline(always)] + pub fn dtien3(&self) -> DTIEN3_R { + DTIEN3_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bits 16:23 - Dead-time Low Side Outputs Value"] + #[inline(always)] + pub fn dtls(&self) -> DTLS_R { + DTLS_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Dead-time High Side Outputs Value"] + #[inline(always)] + pub fn dths(&self) -> DTHS_R { + DTHS_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Output Matrix"] + #[inline(always)] + pub fn otmx(&mut self) -> OTMX_W { + OTMX_W { w: self } + } + #[doc = "Bit 8 - Dead-time Insertion Generator 0 Enable"] + #[inline(always)] + pub fn dtien0(&mut self) -> DTIEN0_W { + DTIEN0_W { w: self } + } + #[doc = "Bit 9 - Dead-time Insertion Generator 1 Enable"] + #[inline(always)] + pub fn dtien1(&mut self) -> DTIEN1_W { + DTIEN1_W { w: self } + } + #[doc = "Bit 10 - Dead-time Insertion Generator 2 Enable"] + #[inline(always)] + pub fn dtien2(&mut self) -> DTIEN2_W { + DTIEN2_W { w: self } + } + #[doc = "Bit 11 - Dead-time Insertion Generator 3 Enable"] + #[inline(always)] + pub fn dtien3(&mut self) -> DTIEN3_W { + DTIEN3_W { w: self } + } + #[doc = "Bits 16:23 - Dead-time Low Side Outputs Value"] + #[inline(always)] + pub fn dtls(&mut self) -> DTLS_W { + DTLS_W { w: self } + } + #[doc = "Bits 24:31 - Dead-time High Side Outputs Value"] + #[inline(always)] + pub fn dths(&mut self) -> DTHS_W { + DTHS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Waveform Extension Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wexctrl](index.html) module"] +pub struct WEXCTRL_SPEC; +impl crate::RegisterSpec for WEXCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [wexctrl::R](R) reader structure"] +impl crate::Readable for WEXCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wexctrl::W](W) writer structure"] +impl crate::Writable for WEXCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WEXCTRL to value 0"] +impl crate::Resettable for WEXCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/wdt.rs b/pac/atsamc20e/src/wdt.rs new file mode 100644 index 000000000000..22b5c2bb706f --- /dev/null +++ b/pac/atsamc20e/src/wdt.rs @@ -0,0 +1,54 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrla: crate::Reg, + #[doc = "0x01 - Configuration"] + pub config: crate::Reg, + #[doc = "0x02 - Early Warning Interrupt Control"] + pub ewctrl: crate::Reg, + _reserved3: [u8; 0x01], + #[doc = "0x04 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x05 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x06 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x08 - Synchronization Busy"] + pub syncbusy: crate::Reg, + #[doc = "0x0c - Clear"] + pub clear: crate::Reg, +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control"] +pub mod ctrla; +#[doc = "CONFIG register accessor: an alias for `Reg`"] +pub type CONFIG = crate::Reg; +#[doc = "Configuration"] +pub mod config; +#[doc = "EWCTRL register accessor: an alias for `Reg`"] +pub type EWCTRL = crate::Reg; +#[doc = "Early Warning Interrupt Control"] +pub mod ewctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Busy"] +pub mod syncbusy; +#[doc = "CLEAR register accessor: an alias for `Reg`"] +pub type CLEAR = crate::Reg; +#[doc = "Clear"] +pub mod clear; diff --git a/pac/atsamc20e/src/wdt/clear.rs b/pac/atsamc20e/src/wdt/clear.rs new file mode 100644 index 000000000000..61ee21f3246a --- /dev/null +++ b/pac/atsamc20e/src/wdt/clear.rs @@ -0,0 +1,85 @@ +#[doc = "Register `CLEAR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Watchdog Clear\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CLEAR_AW { + #[doc = "165: Clear Key"] + KEY = 165, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CLEAR_AW) -> Self { + variant as _ + } +} +#[doc = "Field `CLEAR` writer - Watchdog Clear"] +pub struct CLEAR_W<'a> { + w: &'a mut W, +} +impl<'a> CLEAR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CLEAR_AW) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Clear Key"] + #[inline(always)] + pub fn key(self) -> &'a mut W { + self.variant(CLEAR_AW::KEY) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl W { + #[doc = "Bits 0:7 - Watchdog Clear"] + #[inline(always)] + pub fn clear(&mut self) -> CLEAR_W { + CLEAR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Clear\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clear](index.html) module"] +pub struct CLEAR_SPEC; +impl crate::RegisterSpec for CLEAR_SPEC { + type Ux = u8; +} +#[doc = "`write(|w| ..)` method takes [clear::W](W) writer structure"] +impl crate::Writable for CLEAR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CLEAR to value 0"] +impl crate::Resettable for CLEAR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/wdt/config.rs b/pac/atsamc20e/src/wdt/config.rs new file mode 100644 index 000000000000..c90f062b01f0 --- /dev/null +++ b/pac/atsamc20e/src/wdt/config.rs @@ -0,0 +1,498 @@ +#[doc = "Register `CONFIG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CONFIG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Time-Out Period\n\nValue on reset: 11"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PER_A { + #[doc = "0: 8 clock cycles"] + CYC8 = 0, + #[doc = "1: 16 clock cycles"] + CYC16 = 1, + #[doc = "2: 32 clock cycles"] + CYC32 = 2, + #[doc = "3: 64 clock cycles"] + CYC64 = 3, + #[doc = "4: 128 clock cycles"] + CYC128 = 4, + #[doc = "5: 256 clock cycles"] + CYC256 = 5, + #[doc = "6: 512 clock cycles"] + CYC512 = 6, + #[doc = "7: 1024 clock cycles"] + CYC1024 = 7, + #[doc = "8: 2048 clock cycles"] + CYC2048 = 8, + #[doc = "9: 4096 clock cycles"] + CYC4096 = 9, + #[doc = "10: 8192 clock cycles"] + CYC8192 = 10, + #[doc = "11: 16384 clock cycles"] + CYC16384 = 11, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PER` reader - Time-Out Period"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PER_A::CYC8), + 1 => Some(PER_A::CYC16), + 2 => Some(PER_A::CYC32), + 3 => Some(PER_A::CYC64), + 4 => Some(PER_A::CYC128), + 5 => Some(PER_A::CYC256), + 6 => Some(PER_A::CYC512), + 7 => Some(PER_A::CYC1024), + 8 => Some(PER_A::CYC2048), + 9 => Some(PER_A::CYC4096), + 10 => Some(PER_A::CYC8192), + 11 => Some(PER_A::CYC16384), + _ => None, + } + } + #[doc = "Checks if the value of the field is `CYC8`"] + #[inline(always)] + pub fn is_cyc8(&self) -> bool { + **self == PER_A::CYC8 + } + #[doc = "Checks if the value of the field is `CYC16`"] + #[inline(always)] + pub fn is_cyc16(&self) -> bool { + **self == PER_A::CYC16 + } + #[doc = "Checks if the value of the field is `CYC32`"] + #[inline(always)] + pub fn is_cyc32(&self) -> bool { + **self == PER_A::CYC32 + } + #[doc = "Checks if the value of the field is `CYC64`"] + #[inline(always)] + pub fn is_cyc64(&self) -> bool { + **self == PER_A::CYC64 + } + #[doc = "Checks if the value of the field is `CYC128`"] + #[inline(always)] + pub fn is_cyc128(&self) -> bool { + **self == PER_A::CYC128 + } + #[doc = "Checks if the value of the field is `CYC256`"] + #[inline(always)] + pub fn is_cyc256(&self) -> bool { + **self == PER_A::CYC256 + } + #[doc = "Checks if the value of the field is `CYC512`"] + #[inline(always)] + pub fn is_cyc512(&self) -> bool { + **self == PER_A::CYC512 + } + #[doc = "Checks if the value of the field is `CYC1024`"] + #[inline(always)] + pub fn is_cyc1024(&self) -> bool { + **self == PER_A::CYC1024 + } + #[doc = "Checks if the value of the field is `CYC2048`"] + #[inline(always)] + pub fn is_cyc2048(&self) -> bool { + **self == PER_A::CYC2048 + } + #[doc = "Checks if the value of the field is `CYC4096`"] + #[inline(always)] + pub fn is_cyc4096(&self) -> bool { + **self == PER_A::CYC4096 + } + #[doc = "Checks if the value of the field is `CYC8192`"] + #[inline(always)] + pub fn is_cyc8192(&self) -> bool { + **self == PER_A::CYC8192 + } + #[doc = "Checks if the value of the field is `CYC16384`"] + #[inline(always)] + pub fn is_cyc16384(&self) -> bool { + **self == PER_A::CYC16384 + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` writer - Time-Out Period"] +pub struct PER_W<'a> { + w: &'a mut W, +} +impl<'a> PER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PER_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8 clock cycles"] + #[inline(always)] + pub fn cyc8(self) -> &'a mut W { + self.variant(PER_A::CYC8) + } + #[doc = "16 clock cycles"] + #[inline(always)] + pub fn cyc16(self) -> &'a mut W { + self.variant(PER_A::CYC16) + } + #[doc = "32 clock cycles"] + #[inline(always)] + pub fn cyc32(self) -> &'a mut W { + self.variant(PER_A::CYC32) + } + #[doc = "64 clock cycles"] + #[inline(always)] + pub fn cyc64(self) -> &'a mut W { + self.variant(PER_A::CYC64) + } + #[doc = "128 clock cycles"] + #[inline(always)] + pub fn cyc128(self) -> &'a mut W { + self.variant(PER_A::CYC128) + } + #[doc = "256 clock cycles"] + #[inline(always)] + pub fn cyc256(self) -> &'a mut W { + self.variant(PER_A::CYC256) + } + #[doc = "512 clock cycles"] + #[inline(always)] + pub fn cyc512(self) -> &'a mut W { + self.variant(PER_A::CYC512) + } + #[doc = "1024 clock cycles"] + #[inline(always)] + pub fn cyc1024(self) -> &'a mut W { + self.variant(PER_A::CYC1024) + } + #[doc = "2048 clock cycles"] + #[inline(always)] + pub fn cyc2048(self) -> &'a mut W { + self.variant(PER_A::CYC2048) + } + #[doc = "4096 clock cycles"] + #[inline(always)] + pub fn cyc4096(self) -> &'a mut W { + self.variant(PER_A::CYC4096) + } + #[doc = "8192 clock cycles"] + #[inline(always)] + pub fn cyc8192(self) -> &'a mut W { + self.variant(PER_A::CYC8192) + } + #[doc = "16384 clock cycles"] + #[inline(always)] + pub fn cyc16384(self) -> &'a mut W { + self.variant(PER_A::CYC16384) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +#[doc = "Window Mode Time-Out Period\n\nValue on reset: 11"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WINDOW_A { + #[doc = "0: 8 clock cycles"] + CYC8 = 0, + #[doc = "1: 16 clock cycles"] + CYC16 = 1, + #[doc = "2: 32 clock cycles"] + CYC32 = 2, + #[doc = "3: 64 clock cycles"] + CYC64 = 3, + #[doc = "4: 128 clock cycles"] + CYC128 = 4, + #[doc = "5: 256 clock cycles"] + CYC256 = 5, + #[doc = "6: 512 clock cycles"] + CYC512 = 6, + #[doc = "7: 1024 clock cycles"] + CYC1024 = 7, + #[doc = "8: 2048 clock cycles"] + CYC2048 = 8, + #[doc = "9: 4096 clock cycles"] + CYC4096 = 9, + #[doc = "10: 8192 clock cycles"] + CYC8192 = 10, + #[doc = "11: 16384 clock cycles"] + CYC16384 = 11, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WINDOW_A) -> Self { + variant as _ + } +} +#[doc = "Field `WINDOW` reader - Window Mode Time-Out Period"] +pub struct WINDOW_R(crate::FieldReader); +impl WINDOW_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WINDOW_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(WINDOW_A::CYC8), + 1 => Some(WINDOW_A::CYC16), + 2 => Some(WINDOW_A::CYC32), + 3 => Some(WINDOW_A::CYC64), + 4 => Some(WINDOW_A::CYC128), + 5 => Some(WINDOW_A::CYC256), + 6 => Some(WINDOW_A::CYC512), + 7 => Some(WINDOW_A::CYC1024), + 8 => Some(WINDOW_A::CYC2048), + 9 => Some(WINDOW_A::CYC4096), + 10 => Some(WINDOW_A::CYC8192), + 11 => Some(WINDOW_A::CYC16384), + _ => None, + } + } + #[doc = "Checks if the value of the field is `CYC8`"] + #[inline(always)] + pub fn is_cyc8(&self) -> bool { + **self == WINDOW_A::CYC8 + } + #[doc = "Checks if the value of the field is `CYC16`"] + #[inline(always)] + pub fn is_cyc16(&self) -> bool { + **self == WINDOW_A::CYC16 + } + #[doc = "Checks if the value of the field is `CYC32`"] + #[inline(always)] + pub fn is_cyc32(&self) -> bool { + **self == WINDOW_A::CYC32 + } + #[doc = "Checks if the value of the field is `CYC64`"] + #[inline(always)] + pub fn is_cyc64(&self) -> bool { + **self == WINDOW_A::CYC64 + } + #[doc = "Checks if the value of the field is `CYC128`"] + #[inline(always)] + pub fn is_cyc128(&self) -> bool { + **self == WINDOW_A::CYC128 + } + #[doc = "Checks if the value of the field is `CYC256`"] + #[inline(always)] + pub fn is_cyc256(&self) -> bool { + **self == WINDOW_A::CYC256 + } + #[doc = "Checks if the value of the field is `CYC512`"] + #[inline(always)] + pub fn is_cyc512(&self) -> bool { + **self == WINDOW_A::CYC512 + } + #[doc = "Checks if the value of the field is `CYC1024`"] + #[inline(always)] + pub fn is_cyc1024(&self) -> bool { + **self == WINDOW_A::CYC1024 + } + #[doc = "Checks if the value of the field is `CYC2048`"] + #[inline(always)] + pub fn is_cyc2048(&self) -> bool { + **self == WINDOW_A::CYC2048 + } + #[doc = "Checks if the value of the field is `CYC4096`"] + #[inline(always)] + pub fn is_cyc4096(&self) -> bool { + **self == WINDOW_A::CYC4096 + } + #[doc = "Checks if the value of the field is `CYC8192`"] + #[inline(always)] + pub fn is_cyc8192(&self) -> bool { + **self == WINDOW_A::CYC8192 + } + #[doc = "Checks if the value of the field is `CYC16384`"] + #[inline(always)] + pub fn is_cyc16384(&self) -> bool { + **self == WINDOW_A::CYC16384 + } +} +impl core::ops::Deref for WINDOW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINDOW` writer - Window Mode Time-Out Period"] +pub struct WINDOW_W<'a> { + w: &'a mut W, +} +impl<'a> WINDOW_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WINDOW_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8 clock cycles"] + #[inline(always)] + pub fn cyc8(self) -> &'a mut W { + self.variant(WINDOW_A::CYC8) + } + #[doc = "16 clock cycles"] + #[inline(always)] + pub fn cyc16(self) -> &'a mut W { + self.variant(WINDOW_A::CYC16) + } + #[doc = "32 clock cycles"] + #[inline(always)] + pub fn cyc32(self) -> &'a mut W { + self.variant(WINDOW_A::CYC32) + } + #[doc = "64 clock cycles"] + #[inline(always)] + pub fn cyc64(self) -> &'a mut W { + self.variant(WINDOW_A::CYC64) + } + #[doc = "128 clock cycles"] + #[inline(always)] + pub fn cyc128(self) -> &'a mut W { + self.variant(WINDOW_A::CYC128) + } + #[doc = "256 clock cycles"] + #[inline(always)] + pub fn cyc256(self) -> &'a mut W { + self.variant(WINDOW_A::CYC256) + } + #[doc = "512 clock cycles"] + #[inline(always)] + pub fn cyc512(self) -> &'a mut W { + self.variant(WINDOW_A::CYC512) + } + #[doc = "1024 clock cycles"] + #[inline(always)] + pub fn cyc1024(self) -> &'a mut W { + self.variant(WINDOW_A::CYC1024) + } + #[doc = "2048 clock cycles"] + #[inline(always)] + pub fn cyc2048(self) -> &'a mut W { + self.variant(WINDOW_A::CYC2048) + } + #[doc = "4096 clock cycles"] + #[inline(always)] + pub fn cyc4096(self) -> &'a mut W { + self.variant(WINDOW_A::CYC4096) + } + #[doc = "8192 clock cycles"] + #[inline(always)] + pub fn cyc8192(self) -> &'a mut W { + self.variant(WINDOW_A::CYC8192) + } + #[doc = "16384 clock cycles"] + #[inline(always)] + pub fn cyc16384(self) -> &'a mut W { + self.variant(WINDOW_A::CYC16384) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 4)) | ((value as u8 & 0x0f) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Time-Out Period"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Window Mode Time-Out Period"] + #[inline(always)] + pub fn window(&self) -> WINDOW_R { + WINDOW_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Time-Out Period"] + #[inline(always)] + pub fn per(&mut self) -> PER_W { + PER_W { w: self } + } + #[doc = "Bits 4:7 - Window Mode Time-Out Period"] + #[inline(always)] + pub fn window(&mut self) -> WINDOW_W { + WINDOW_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [config](index.html) module"] +pub struct CONFIG_SPEC; +impl crate::RegisterSpec for CONFIG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [config::R](R) reader structure"] +impl crate::Readable for CONFIG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [config::W](W) writer structure"] +impl crate::Writable for CONFIG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CONFIG to value 0xbb"] +impl crate::Resettable for CONFIG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xbb + } +} diff --git a/pac/atsamc20e/src/wdt/ctrla.rs b/pac/atsamc20e/src/wdt/ctrla.rs new file mode 100644 index 000000000000..895169d36aeb --- /dev/null +++ b/pac/atsamc20e/src/wdt/ctrla.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WEN` reader - Watchdog Timer Window Mode Enable"] +pub struct WEN_R(crate::FieldReader); +impl WEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WEN` writer - Watchdog Timer Window Mode Enable"] +pub struct WEN_W<'a> { + w: &'a mut W, +} +impl<'a> WEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `ALWAYSON` reader - Always-On"] +pub struct ALWAYSON_R(crate::FieldReader); +impl ALWAYSON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALWAYSON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALWAYSON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALWAYSON` writer - Always-On"] +pub struct ALWAYSON_W<'a> { + w: &'a mut W, +} +impl<'a> ALWAYSON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Watchdog Timer Window Mode Enable"] + #[inline(always)] + pub fn wen(&self) -> WEN_R { + WEN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 7 - Always-On"] + #[inline(always)] + pub fn alwayson(&self) -> ALWAYSON_R { + ALWAYSON_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - Watchdog Timer Window Mode Enable"] + #[inline(always)] + pub fn wen(&mut self) -> WEN_W { + WEN_W { w: self } + } + #[doc = "Bit 7 - Always-On"] + #[inline(always)] + pub fn alwayson(&mut self) -> ALWAYSON_W { + ALWAYSON_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/wdt/ewctrl.rs b/pac/atsamc20e/src/wdt/ewctrl.rs new file mode 100644 index 000000000000..94542e9897a9 --- /dev/null +++ b/pac/atsamc20e/src/wdt/ewctrl.rs @@ -0,0 +1,282 @@ +#[doc = "Register `EWCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EWCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Early Warning Interrupt Time Offset\n\nValue on reset: 11"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EWOFFSET_A { + #[doc = "0: 8 clock cycles"] + CYC8 = 0, + #[doc = "1: 16 clock cycles"] + CYC16 = 1, + #[doc = "2: 32 clock cycles"] + CYC32 = 2, + #[doc = "3: 64 clock cycles"] + CYC64 = 3, + #[doc = "4: 128 clock cycles"] + CYC128 = 4, + #[doc = "5: 256 clock cycles"] + CYC256 = 5, + #[doc = "6: 512 clock cycles"] + CYC512 = 6, + #[doc = "7: 1024 clock cycles"] + CYC1024 = 7, + #[doc = "8: 2048 clock cycles"] + CYC2048 = 8, + #[doc = "9: 4096 clock cycles"] + CYC4096 = 9, + #[doc = "10: 8192 clock cycles"] + CYC8192 = 10, + #[doc = "11: 16384 clock cycles"] + CYC16384 = 11, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EWOFFSET_A) -> Self { + variant as _ + } +} +#[doc = "Field `EWOFFSET` reader - Early Warning Interrupt Time Offset"] +pub struct EWOFFSET_R(crate::FieldReader); +impl EWOFFSET_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EWOFFSET_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(EWOFFSET_A::CYC8), + 1 => Some(EWOFFSET_A::CYC16), + 2 => Some(EWOFFSET_A::CYC32), + 3 => Some(EWOFFSET_A::CYC64), + 4 => Some(EWOFFSET_A::CYC128), + 5 => Some(EWOFFSET_A::CYC256), + 6 => Some(EWOFFSET_A::CYC512), + 7 => Some(EWOFFSET_A::CYC1024), + 8 => Some(EWOFFSET_A::CYC2048), + 9 => Some(EWOFFSET_A::CYC4096), + 10 => Some(EWOFFSET_A::CYC8192), + 11 => Some(EWOFFSET_A::CYC16384), + _ => None, + } + } + #[doc = "Checks if the value of the field is `CYC8`"] + #[inline(always)] + pub fn is_cyc8(&self) -> bool { + **self == EWOFFSET_A::CYC8 + } + #[doc = "Checks if the value of the field is `CYC16`"] + #[inline(always)] + pub fn is_cyc16(&self) -> bool { + **self == EWOFFSET_A::CYC16 + } + #[doc = "Checks if the value of the field is `CYC32`"] + #[inline(always)] + pub fn is_cyc32(&self) -> bool { + **self == EWOFFSET_A::CYC32 + } + #[doc = "Checks if the value of the field is `CYC64`"] + #[inline(always)] + pub fn is_cyc64(&self) -> bool { + **self == EWOFFSET_A::CYC64 + } + #[doc = "Checks if the value of the field is `CYC128`"] + #[inline(always)] + pub fn is_cyc128(&self) -> bool { + **self == EWOFFSET_A::CYC128 + } + #[doc = "Checks if the value of the field is `CYC256`"] + #[inline(always)] + pub fn is_cyc256(&self) -> bool { + **self == EWOFFSET_A::CYC256 + } + #[doc = "Checks if the value of the field is `CYC512`"] + #[inline(always)] + pub fn is_cyc512(&self) -> bool { + **self == EWOFFSET_A::CYC512 + } + #[doc = "Checks if the value of the field is `CYC1024`"] + #[inline(always)] + pub fn is_cyc1024(&self) -> bool { + **self == EWOFFSET_A::CYC1024 + } + #[doc = "Checks if the value of the field is `CYC2048`"] + #[inline(always)] + pub fn is_cyc2048(&self) -> bool { + **self == EWOFFSET_A::CYC2048 + } + #[doc = "Checks if the value of the field is `CYC4096`"] + #[inline(always)] + pub fn is_cyc4096(&self) -> bool { + **self == EWOFFSET_A::CYC4096 + } + #[doc = "Checks if the value of the field is `CYC8192`"] + #[inline(always)] + pub fn is_cyc8192(&self) -> bool { + **self == EWOFFSET_A::CYC8192 + } + #[doc = "Checks if the value of the field is `CYC16384`"] + #[inline(always)] + pub fn is_cyc16384(&self) -> bool { + **self == EWOFFSET_A::CYC16384 + } +} +impl core::ops::Deref for EWOFFSET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EWOFFSET` writer - Early Warning Interrupt Time Offset"] +pub struct EWOFFSET_W<'a> { + w: &'a mut W, +} +impl<'a> EWOFFSET_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EWOFFSET_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8 clock cycles"] + #[inline(always)] + pub fn cyc8(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC8) + } + #[doc = "16 clock cycles"] + #[inline(always)] + pub fn cyc16(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC16) + } + #[doc = "32 clock cycles"] + #[inline(always)] + pub fn cyc32(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC32) + } + #[doc = "64 clock cycles"] + #[inline(always)] + pub fn cyc64(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC64) + } + #[doc = "128 clock cycles"] + #[inline(always)] + pub fn cyc128(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC128) + } + #[doc = "256 clock cycles"] + #[inline(always)] + pub fn cyc256(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC256) + } + #[doc = "512 clock cycles"] + #[inline(always)] + pub fn cyc512(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC512) + } + #[doc = "1024 clock cycles"] + #[inline(always)] + pub fn cyc1024(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC1024) + } + #[doc = "2048 clock cycles"] + #[inline(always)] + pub fn cyc2048(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC2048) + } + #[doc = "4096 clock cycles"] + #[inline(always)] + pub fn cyc4096(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC4096) + } + #[doc = "8192 clock cycles"] + #[inline(always)] + pub fn cyc8192(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC8192) + } + #[doc = "16384 clock cycles"] + #[inline(always)] + pub fn cyc16384(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC16384) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Early Warning Interrupt Time Offset"] + #[inline(always)] + pub fn ewoffset(&self) -> EWOFFSET_R { + EWOFFSET_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Early Warning Interrupt Time Offset"] + #[inline(always)] + pub fn ewoffset(&mut self) -> EWOFFSET_W { + EWOFFSET_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Early Warning Interrupt Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ewctrl](index.html) module"] +pub struct EWCTRL_SPEC; +impl crate::RegisterSpec for EWCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ewctrl::R](R) reader structure"] +impl crate::Readable for EWCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ewctrl::W](W) writer structure"] +impl crate::Writable for EWCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EWCTRL to value 0x0b"] +impl crate::Resettable for EWCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0b + } +} diff --git a/pac/atsamc20e/src/wdt/intenclr.rs b/pac/atsamc20e/src/wdt/intenclr.rs new file mode 100644 index 000000000000..ed4021f96cce --- /dev/null +++ b/pac/atsamc20e/src/wdt/intenclr.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EW` reader - Early Warning Interrupt Enable"] +pub struct EW_R(crate::FieldReader); +impl EW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EW` writer - Early Warning Interrupt Enable"] +pub struct EW_W<'a> { + w: &'a mut W, +} +impl<'a> EW_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Early Warning Interrupt Enable"] + #[inline(always)] + pub fn ew(&self) -> EW_R { + EW_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Early Warning Interrupt Enable"] + #[inline(always)] + pub fn ew(&mut self) -> EW_W { + EW_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/wdt/intenset.rs b/pac/atsamc20e/src/wdt/intenset.rs new file mode 100644 index 000000000000..5a0928ff0532 --- /dev/null +++ b/pac/atsamc20e/src/wdt/intenset.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EW` reader - Early Warning Interrupt Enable"] +pub struct EW_R(crate::FieldReader); +impl EW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EW` writer - Early Warning Interrupt Enable"] +pub struct EW_W<'a> { + w: &'a mut W, +} +impl<'a> EW_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Early Warning Interrupt Enable"] + #[inline(always)] + pub fn ew(&self) -> EW_R { + EW_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Early Warning Interrupt Enable"] + #[inline(always)] + pub fn ew(&mut self) -> EW_W { + EW_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/wdt/intflag.rs b/pac/atsamc20e/src/wdt/intflag.rs new file mode 100644 index 000000000000..f2c9b858a199 --- /dev/null +++ b/pac/atsamc20e/src/wdt/intflag.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EW` reader - Early Warning"] +pub struct EW_R(crate::FieldReader); +impl EW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EW` writer - Early Warning"] +pub struct EW_W<'a> { + w: &'a mut W, +} +impl<'a> EW_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Early Warning"] + #[inline(always)] + pub fn ew(&self) -> EW_R { + EW_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Early Warning"] + #[inline(always)] + pub fn ew(&mut self) -> EW_W { + EW_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20e/src/wdt/syncbusy.rs b/pac/atsamc20e/src/wdt/syncbusy.rs new file mode 100644 index 000000000000..a3ecf7fbdb8a --- /dev/null +++ b/pac/atsamc20e/src/wdt/syncbusy.rs @@ -0,0 +1,113 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `ENABLE` reader - Enable Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WEN` reader - Window Enable Busy"] +pub struct WEN_R(crate::FieldReader); +impl WEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALWAYSON` reader - Always-On Busy"] +pub struct ALWAYSON_R(crate::FieldReader); +impl ALWAYSON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALWAYSON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALWAYSON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLEAR` reader - Clear Busy"] +pub struct CLEAR_R(crate::FieldReader); +impl CLEAR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLEAR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLEAR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 1 - Enable Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Window Enable Busy"] + #[inline(always)] + pub fn wen(&self) -> WEN_R { + WEN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Always-On Busy"] + #[inline(always)] + pub fn alwayson(&self) -> ALWAYSON_R { + ALWAYSON_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Clear Busy"] + #[inline(always)] + pub fn clear(&self) -> CLEAR_R { + CLEAR_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +#[doc = "Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/CHANGELOG.md b/pac/atsamc20g/CHANGELOG.md new file mode 100644 index 000000000000..e28d85f63b31 --- /dev/null +++ b/pac/atsamc20g/CHANGELOG.md @@ -0,0 +1,6 @@ +# Unreleased + +- Initial version +--- + +Changelog tracking started at v0.0.1 diff --git a/pac/atsamc20g/Cargo.toml b/pac/atsamc20g/Cargo.toml new file mode 100644 index 000000000000..837adf7339e8 --- /dev/null +++ b/pac/atsamc20g/Cargo.toml @@ -0,0 +1,22 @@ +[package] +name = "atsamc20g" +description = "Peripheral access API for ATSAMC20G microcontrollers (generated using svd2rust)" +version = "0.0.1" +authors = ["Jeremy Boynes "] +keywords = ["no-std", "arm", "cortex-m"] +categories = ["embedded", "hardware-support", "no-std"] +license = "MIT OR Apache-2.0" +repository = "https://github.com/atsamd-rs/atsamd" +readme = "README.md" +edition = "2021" + +[dependencies] +cortex-m = "0.7" +vcell = "0.1" + +[dependencies.cortex-m-rt] +version = "0.7" +optional = true + +[features] +rt = ["cortex-m-rt/device"] diff --git a/pac/atsamc20g/README.md b/pac/atsamc20g/README.md new file mode 100644 index 000000000000..7402e6198af1 --- /dev/null +++ b/pac/atsamc20g/README.md @@ -0,0 +1,26 @@ +# ATSAMC20G + +A peripheral access crate for the ATSAMC20E chip from Microchip (née Atmel) for Rust Embedded projects. + +[![Build Status](https://travis-ci.org/atsamd-rs/atsamd.svg?branch=master)](https://travis-ci.org/atsamd-rs/atsamd) +[![Crates.io](https://img.shields.io/crates/v/atsamc20g.svg)](https://crates.io/crates/atsamc20g) + +## [Documentation](https://docs.rs/atsamc20g) + +This source was automatically generated using `svd2rust`, split into smaller pieces using `form` and formatted via `rustfmt`. + +## License + +Licensed under either of: + +- Apache License, Version 2.0 ([LICENSE-APACHE](https://github.com/atsamd-rs/atsamd/blob/master/LICENSE-APACHE) or + http://www.apache.org/licenses/LICENSE-2.0) +- MIT license ([LICENSE-MIT](https://github.com/atsamd-rs/atsamd/blob/master/LICENSE-MIT) or http://opensource.org/licenses/MIT) + +at your option. + +### Contribution + +Unless you explicitly state otherwise, any contribution intentionally submitted +for inclusion in the work by you, as defined in the Apache-2.0 license, shall +be dual licensed as above, without any additional terms or conditions. diff --git a/pac/atsamc20g/build.rs b/pac/atsamc20g/build.rs new file mode 100644 index 000000000000..597923f50892 --- /dev/null +++ b/pac/atsamc20g/build.rs @@ -0,0 +1,16 @@ +use std::env; +use std::fs::File; +use std::io::Write; +use std::path::PathBuf; +fn main() { + if env::var_os("CARGO_FEATURE_RT").is_some() { + let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap()); + File::create(out.join("device.x")) + .unwrap() + .write_all(include_bytes!("device.x")) + .unwrap(); + println!("cargo:rustc-link-search={}", out.display()); + println!("cargo:rerun-if-changed=device.x"); + } + println!("cargo:rerun-if-changed=build.rs"); +} diff --git a/pac/atsamc20g/device.x b/pac/atsamc20g/device.x new file mode 100644 index 000000000000..c9ef51bf7250 --- /dev/null +++ b/pac/atsamc20g/device.x @@ -0,0 +1,23 @@ +PROVIDE(WDT = DefaultHandler); +PROVIDE(RTC = DefaultHandler); +PROVIDE(EIC = DefaultHandler); +PROVIDE(FREQM = DefaultHandler); +PROVIDE(NVMCTRL = DefaultHandler); +PROVIDE(DMAC = DefaultHandler); +PROVIDE(EVSYS = DefaultHandler); +PROVIDE(SERCOM0 = DefaultHandler); +PROVIDE(SERCOM1 = DefaultHandler); +PROVIDE(SERCOM2 = DefaultHandler); +PROVIDE(SERCOM3 = DefaultHandler); +PROVIDE(TCC0 = DefaultHandler); +PROVIDE(TCC1 = DefaultHandler); +PROVIDE(TCC2 = DefaultHandler); +PROVIDE(TC0 = DefaultHandler); +PROVIDE(TC1 = DefaultHandler); +PROVIDE(TC2 = DefaultHandler); +PROVIDE(TC3 = DefaultHandler); +PROVIDE(TC4 = DefaultHandler); +PROVIDE(ADC0 = DefaultHandler); +PROVIDE(AC = DefaultHandler); +PROVIDE(PTC = DefaultHandler); + diff --git a/pac/atsamc20g/src/ac.rs b/pac/atsamc20g/src/ac.rs new file mode 100644 index 000000000000..b66620475572 --- /dev/null +++ b/pac/atsamc20g/src/ac.rs @@ -0,0 +1,83 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + #[doc = "0x01 - Control B"] + pub ctrlb: crate::Reg, + #[doc = "0x02 - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x04 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x05 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x06 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x07 - Status A"] + pub statusa: crate::Reg, + #[doc = "0x08 - Status B"] + pub statusb: crate::Reg, + #[doc = "0x09 - Debug Control"] + pub dbgctrl: crate::Reg, + #[doc = "0x0a - Window Control"] + pub winctrl: crate::Reg, + _reserved10: [u8; 0x01], + #[doc = "0x0c - Scaler n"] + pub scaler: [crate::Reg; 4], + #[doc = "0x10..0x20 - Comparator Control n"] + pub compctrl: [crate::Reg; 4], + #[doc = "0x20 - Synchronization Busy"] + pub syncbusy: crate::Reg, +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "Control B"] +pub mod ctrlb; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUSA register accessor: an alias for `Reg`"] +pub type STATUSA = crate::Reg; +#[doc = "Status A"] +pub mod statusa; +#[doc = "STATUSB register accessor: an alias for `Reg`"] +pub type STATUSB = crate::Reg; +#[doc = "Status B"] +pub mod statusb; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "WINCTRL register accessor: an alias for `Reg`"] +pub type WINCTRL = crate::Reg; +#[doc = "Window Control"] +pub mod winctrl; +#[doc = "SCALER register accessor: an alias for `Reg`"] +pub type SCALER = crate::Reg; +#[doc = "Scaler n"] +pub mod scaler; +#[doc = "COMPCTRL register accessor: an alias for `Reg`"] +pub type COMPCTRL = crate::Reg; +#[doc = "Comparator Control n"] +pub mod compctrl; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Busy"] +pub mod syncbusy; diff --git a/pac/atsamc20g/src/ac/compctrl.rs b/pac/atsamc20g/src/ac/compctrl.rs new file mode 100644 index 000000000000..c52cb53fe56f --- /dev/null +++ b/pac/atsamc20g/src/ac/compctrl.rs @@ -0,0 +1,974 @@ +#[doc = "Register `COMPCTRL[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COMPCTRL[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SINGLE` reader - Single-Shot Mode"] +pub struct SINGLE_R(crate::FieldReader); +impl SINGLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SINGLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SINGLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SINGLE` writer - Single-Shot Mode"] +pub struct SINGLE_W<'a> { + w: &'a mut W, +} +impl<'a> SINGLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Interrupt Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum INTSEL_A { + #[doc = "0: Interrupt on comparator output toggle"] + TOGGLE = 0, + #[doc = "1: Interrupt on comparator output rising"] + RISING = 1, + #[doc = "2: Interrupt on comparator output falling"] + FALLING = 2, + #[doc = "3: Interrupt on end of comparison (single-shot mode only)"] + EOC = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: INTSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `INTSEL` reader - Interrupt Selection"] +pub struct INTSEL_R(crate::FieldReader); +impl INTSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + INTSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INTSEL_A { + match self.bits { + 0 => INTSEL_A::TOGGLE, + 1 => INTSEL_A::RISING, + 2 => INTSEL_A::FALLING, + 3 => INTSEL_A::EOC, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `TOGGLE`"] + #[inline(always)] + pub fn is_toggle(&self) -> bool { + **self == INTSEL_A::TOGGLE + } + #[doc = "Checks if the value of the field is `RISING`"] + #[inline(always)] + pub fn is_rising(&self) -> bool { + **self == INTSEL_A::RISING + } + #[doc = "Checks if the value of the field is `FALLING`"] + #[inline(always)] + pub fn is_falling(&self) -> bool { + **self == INTSEL_A::FALLING + } + #[doc = "Checks if the value of the field is `EOC`"] + #[inline(always)] + pub fn is_eoc(&self) -> bool { + **self == INTSEL_A::EOC + } +} +impl core::ops::Deref for INTSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INTSEL` writer - Interrupt Selection"] +pub struct INTSEL_W<'a> { + w: &'a mut W, +} +impl<'a> INTSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: INTSEL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Interrupt on comparator output toggle"] + #[inline(always)] + pub fn toggle(self) -> &'a mut W { + self.variant(INTSEL_A::TOGGLE) + } + #[doc = "Interrupt on comparator output rising"] + #[inline(always)] + pub fn rising(self) -> &'a mut W { + self.variant(INTSEL_A::RISING) + } + #[doc = "Interrupt on comparator output falling"] + #[inline(always)] + pub fn falling(self) -> &'a mut W { + self.variant(INTSEL_A::FALLING) + } + #[doc = "Interrupt on end of comparison (single-shot mode only)"] + #[inline(always)] + pub fn eoc(self) -> &'a mut W { + self.variant(INTSEL_A::EOC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 3)) | ((value as u32 & 0x03) << 3); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Negative Input Mux Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MUXNEG_A { + #[doc = "0: I/O pin 0"] + PIN0 = 0, + #[doc = "1: I/O pin 1"] + PIN1 = 1, + #[doc = "2: I/O pin 2"] + PIN2 = 2, + #[doc = "3: I/O pin 3"] + PIN3 = 3, + #[doc = "4: Ground"] + GND = 4, + #[doc = "5: VDD scaler"] + VSCALE = 5, + #[doc = "6: Internal bandgap voltage"] + BANDGAP = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MUXNEG_A) -> Self { + variant as _ + } +} +#[doc = "Field `MUXNEG` reader - Negative Input Mux Selection"] +pub struct MUXNEG_R(crate::FieldReader); +impl MUXNEG_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MUXNEG_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MUXNEG_A::PIN0), + 1 => Some(MUXNEG_A::PIN1), + 2 => Some(MUXNEG_A::PIN2), + 3 => Some(MUXNEG_A::PIN3), + 4 => Some(MUXNEG_A::GND), + 5 => Some(MUXNEG_A::VSCALE), + 6 => Some(MUXNEG_A::BANDGAP), + _ => None, + } + } + #[doc = "Checks if the value of the field is `PIN0`"] + #[inline(always)] + pub fn is_pin0(&self) -> bool { + **self == MUXNEG_A::PIN0 + } + #[doc = "Checks if the value of the field is `PIN1`"] + #[inline(always)] + pub fn is_pin1(&self) -> bool { + **self == MUXNEG_A::PIN1 + } + #[doc = "Checks if the value of the field is `PIN2`"] + #[inline(always)] + pub fn is_pin2(&self) -> bool { + **self == MUXNEG_A::PIN2 + } + #[doc = "Checks if the value of the field is `PIN3`"] + #[inline(always)] + pub fn is_pin3(&self) -> bool { + **self == MUXNEG_A::PIN3 + } + #[doc = "Checks if the value of the field is `GND`"] + #[inline(always)] + pub fn is_gnd(&self) -> bool { + **self == MUXNEG_A::GND + } + #[doc = "Checks if the value of the field is `VSCALE`"] + #[inline(always)] + pub fn is_vscale(&self) -> bool { + **self == MUXNEG_A::VSCALE + } + #[doc = "Checks if the value of the field is `BANDGAP`"] + #[inline(always)] + pub fn is_bandgap(&self) -> bool { + **self == MUXNEG_A::BANDGAP + } +} +impl core::ops::Deref for MUXNEG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MUXNEG` writer - Negative Input Mux Selection"] +pub struct MUXNEG_W<'a> { + w: &'a mut W, +} +impl<'a> MUXNEG_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MUXNEG_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "I/O pin 0"] + #[inline(always)] + pub fn pin0(self) -> &'a mut W { + self.variant(MUXNEG_A::PIN0) + } + #[doc = "I/O pin 1"] + #[inline(always)] + pub fn pin1(self) -> &'a mut W { + self.variant(MUXNEG_A::PIN1) + } + #[doc = "I/O pin 2"] + #[inline(always)] + pub fn pin2(self) -> &'a mut W { + self.variant(MUXNEG_A::PIN2) + } + #[doc = "I/O pin 3"] + #[inline(always)] + pub fn pin3(self) -> &'a mut W { + self.variant(MUXNEG_A::PIN3) + } + #[doc = "Ground"] + #[inline(always)] + pub fn gnd(self) -> &'a mut W { + self.variant(MUXNEG_A::GND) + } + #[doc = "VDD scaler"] + #[inline(always)] + pub fn vscale(self) -> &'a mut W { + self.variant(MUXNEG_A::VSCALE) + } + #[doc = "Internal bandgap voltage"] + #[inline(always)] + pub fn bandgap(self) -> &'a mut W { + self.variant(MUXNEG_A::BANDGAP) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +#[doc = "Positive Input Mux Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MUXPOS_A { + #[doc = "0: I/O pin 0"] + PIN0 = 0, + #[doc = "1: I/O pin 1"] + PIN1 = 1, + #[doc = "2: I/O pin 2"] + PIN2 = 2, + #[doc = "3: I/O pin 3"] + PIN3 = 3, + #[doc = "4: VDD Scaler"] + VSCALE = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MUXPOS_A) -> Self { + variant as _ + } +} +#[doc = "Field `MUXPOS` reader - Positive Input Mux Selection"] +pub struct MUXPOS_R(crate::FieldReader); +impl MUXPOS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MUXPOS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MUXPOS_A::PIN0), + 1 => Some(MUXPOS_A::PIN1), + 2 => Some(MUXPOS_A::PIN2), + 3 => Some(MUXPOS_A::PIN3), + 4 => Some(MUXPOS_A::VSCALE), + _ => None, + } + } + #[doc = "Checks if the value of the field is `PIN0`"] + #[inline(always)] + pub fn is_pin0(&self) -> bool { + **self == MUXPOS_A::PIN0 + } + #[doc = "Checks if the value of the field is `PIN1`"] + #[inline(always)] + pub fn is_pin1(&self) -> bool { + **self == MUXPOS_A::PIN1 + } + #[doc = "Checks if the value of the field is `PIN2`"] + #[inline(always)] + pub fn is_pin2(&self) -> bool { + **self == MUXPOS_A::PIN2 + } + #[doc = "Checks if the value of the field is `PIN3`"] + #[inline(always)] + pub fn is_pin3(&self) -> bool { + **self == MUXPOS_A::PIN3 + } + #[doc = "Checks if the value of the field is `VSCALE`"] + #[inline(always)] + pub fn is_vscale(&self) -> bool { + **self == MUXPOS_A::VSCALE + } +} +impl core::ops::Deref for MUXPOS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MUXPOS` writer - Positive Input Mux Selection"] +pub struct MUXPOS_W<'a> { + w: &'a mut W, +} +impl<'a> MUXPOS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MUXPOS_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "I/O pin 0"] + #[inline(always)] + pub fn pin0(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN0) + } + #[doc = "I/O pin 1"] + #[inline(always)] + pub fn pin1(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN1) + } + #[doc = "I/O pin 2"] + #[inline(always)] + pub fn pin2(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN2) + } + #[doc = "I/O pin 3"] + #[inline(always)] + pub fn pin3(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN3) + } + #[doc = "VDD Scaler"] + #[inline(always)] + pub fn vscale(self) -> &'a mut W { + self.variant(MUXPOS_A::VSCALE) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 12)) | ((value as u32 & 0x07) << 12); + self.w + } +} +#[doc = "Field `SWAP` reader - Swap Inputs and Invert"] +pub struct SWAP_R(crate::FieldReader); +impl SWAP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWAP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWAP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWAP` writer - Swap Inputs and Invert"] +pub struct SWAP_W<'a> { + w: &'a mut W, +} +impl<'a> SWAP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Speed Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SPEED_A { + #[doc = "0: Low speed"] + LOW = 0, + #[doc = "3: High speed"] + HIGH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SPEED_A) -> Self { + variant as _ + } +} +#[doc = "Field `SPEED` reader - Speed Selection"] +pub struct SPEED_R(crate::FieldReader); +impl SPEED_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SPEED_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SPEED_A::LOW), + 3 => Some(SPEED_A::HIGH), + _ => None, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SPEED_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SPEED_A::HIGH + } +} +impl core::ops::Deref for SPEED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SPEED` writer - Speed Selection"] +pub struct SPEED_W<'a> { + w: &'a mut W, +} +impl<'a> SPEED_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SPEED_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Low speed"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SPEED_A::LOW) + } + #[doc = "High speed"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SPEED_A::HIGH) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Field `HYSTEN` reader - Hysteresis Enable"] +pub struct HYSTEN_R(crate::FieldReader); +impl HYSTEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HYSTEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HYSTEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HYSTEN` writer - Hysteresis Enable"] +pub struct HYSTEN_W<'a> { + w: &'a mut W, +} +impl<'a> HYSTEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Filter Length\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FLEN_A { + #[doc = "0: No filtering"] + OFF = 0, + #[doc = "1: 3-bit majority function (2 of 3)"] + MAJ3 = 1, + #[doc = "2: 5-bit majority function (3 of 5)"] + MAJ5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FLEN_A) -> Self { + variant as _ + } +} +#[doc = "Field `FLEN` reader - Filter Length"] +pub struct FLEN_R(crate::FieldReader); +impl FLEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FLEN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(FLEN_A::OFF), + 1 => Some(FLEN_A::MAJ3), + 2 => Some(FLEN_A::MAJ5), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == FLEN_A::OFF + } + #[doc = "Checks if the value of the field is `MAJ3`"] + #[inline(always)] + pub fn is_maj3(&self) -> bool { + **self == FLEN_A::MAJ3 + } + #[doc = "Checks if the value of the field is `MAJ5`"] + #[inline(always)] + pub fn is_maj5(&self) -> bool { + **self == FLEN_A::MAJ5 + } +} +impl core::ops::Deref for FLEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLEN` writer - Filter Length"] +pub struct FLEN_W<'a> { + w: &'a mut W, +} +impl<'a> FLEN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FLEN_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No filtering"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(FLEN_A::OFF) + } + #[doc = "3-bit majority function (2 of 3)"] + #[inline(always)] + pub fn maj3(self) -> &'a mut W { + self.variant(FLEN_A::MAJ3) + } + #[doc = "5-bit majority function (3 of 5)"] + #[inline(always)] + pub fn maj5(self) -> &'a mut W { + self.variant(FLEN_A::MAJ5) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 24)) | ((value as u32 & 0x07) << 24); + self.w + } +} +#[doc = "Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum OUT_A { + #[doc = "0: The output of COMPn is not routed to the COMPn I/O port"] + OFF = 0, + #[doc = "1: The asynchronous output of COMPn is routed to the COMPn I/O port"] + ASYNC = 1, + #[doc = "2: The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port"] + SYNC = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: OUT_A) -> Self { + variant as _ + } +} +#[doc = "Field `OUT` reader - Output"] +pub struct OUT_R(crate::FieldReader); +impl OUT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + OUT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(OUT_A::OFF), + 1 => Some(OUT_A::ASYNC), + 2 => Some(OUT_A::SYNC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == OUT_A::OFF + } + #[doc = "Checks if the value of the field is `ASYNC`"] + #[inline(always)] + pub fn is_async(&self) -> bool { + **self == OUT_A::ASYNC + } + #[doc = "Checks if the value of the field is `SYNC`"] + #[inline(always)] + pub fn is_sync(&self) -> bool { + **self == OUT_A::SYNC + } +} +impl core::ops::Deref for OUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OUT` writer - Output"] +pub struct OUT_W<'a> { + w: &'a mut W, +} +impl<'a> OUT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: OUT_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "The output of COMPn is not routed to the COMPn I/O port"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(OUT_A::OFF) + } + #[doc = "The asynchronous output of COMPn is routed to the COMPn I/O port"] + #[inline(always)] + pub fn async_(self) -> &'a mut W { + self.variant(OUT_A::ASYNC) + } + #[doc = "The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port"] + #[inline(always)] + pub fn sync(self) -> &'a mut W { + self.variant(OUT_A::SYNC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 28)) | ((value as u32 & 0x03) << 28); + self.w + } +} +impl R { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Single-Shot Mode"] + #[inline(always)] + pub fn single(&self) -> SINGLE_R { + SINGLE_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 3:4 - Interrupt Selection"] + #[inline(always)] + pub fn intsel(&self) -> INTSEL_R { + INTSEL_R::new(((self.bits >> 3) & 0x03) as u8) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Negative Input Mux Selection"] + #[inline(always)] + pub fn muxneg(&self) -> MUXNEG_R { + MUXNEG_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bits 12:14 - Positive Input Mux Selection"] + #[inline(always)] + pub fn muxpos(&self) -> MUXPOS_R { + MUXPOS_R::new(((self.bits >> 12) & 0x07) as u8) + } + #[doc = "Bit 15 - Swap Inputs and Invert"] + #[inline(always)] + pub fn swap(&self) -> SWAP_R { + SWAP_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:17 - Speed Selection"] + #[inline(always)] + pub fn speed(&self) -> SPEED_R { + SPEED_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bit 19 - Hysteresis Enable"] + #[inline(always)] + pub fn hysten(&self) -> HYSTEN_R { + HYSTEN_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bits 24:26 - Filter Length"] + #[inline(always)] + pub fn flen(&self) -> FLEN_R { + FLEN_R::new(((self.bits >> 24) & 0x07) as u8) + } + #[doc = "Bits 28:29 - Output"] + #[inline(always)] + pub fn out(&self) -> OUT_R { + OUT_R::new(((self.bits >> 28) & 0x03) as u8) + } +} +impl W { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - Single-Shot Mode"] + #[inline(always)] + pub fn single(&mut self) -> SINGLE_W { + SINGLE_W { w: self } + } + #[doc = "Bits 3:4 - Interrupt Selection"] + #[inline(always)] + pub fn intsel(&mut self) -> INTSEL_W { + INTSEL_W { w: self } + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bits 8:10 - Negative Input Mux Selection"] + #[inline(always)] + pub fn muxneg(&mut self) -> MUXNEG_W { + MUXNEG_W { w: self } + } + #[doc = "Bits 12:14 - Positive Input Mux Selection"] + #[inline(always)] + pub fn muxpos(&mut self) -> MUXPOS_W { + MUXPOS_W { w: self } + } + #[doc = "Bit 15 - Swap Inputs and Invert"] + #[inline(always)] + pub fn swap(&mut self) -> SWAP_W { + SWAP_W { w: self } + } + #[doc = "Bits 16:17 - Speed Selection"] + #[inline(always)] + pub fn speed(&mut self) -> SPEED_W { + SPEED_W { w: self } + } + #[doc = "Bit 19 - Hysteresis Enable"] + #[inline(always)] + pub fn hysten(&mut self) -> HYSTEN_W { + HYSTEN_W { w: self } + } + #[doc = "Bits 24:26 - Filter Length"] + #[inline(always)] + pub fn flen(&mut self) -> FLEN_W { + FLEN_W { w: self } + } + #[doc = "Bits 28:29 - Output"] + #[inline(always)] + pub fn out(&mut self) -> OUT_W { + OUT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Comparator Control n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [compctrl](index.html) module"] +pub struct COMPCTRL_SPEC; +impl crate::RegisterSpec for COMPCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [compctrl::R](R) reader structure"] +impl crate::Readable for COMPCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [compctrl::W](W) writer structure"] +impl crate::Writable for COMPCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COMPCTRL[%s] +to value 0"] +impl crate::Resettable for COMPCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/ac/ctrla.rs b/pac/atsamc20g/src/ac/ctrla.rs new file mode 100644 index 000000000000..5f2c406226f4 --- /dev/null +++ b/pac/atsamc20g/src/ac/ctrla.rs @@ -0,0 +1,160 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/ac/ctrlb.rs b/pac/atsamc20g/src/ac/ctrlb.rs new file mode 100644 index 000000000000..68aa8d2a20ba --- /dev/null +++ b/pac/atsamc20g/src/ac/ctrlb.rs @@ -0,0 +1,99 @@ +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `START0` writer - Comparator 0 Start Comparison"] +pub struct START0_W<'a> { + w: &'a mut W, +} +impl<'a> START0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `START1` writer - Comparator 1 Start Comparison"] +pub struct START1_W<'a> { + w: &'a mut W, +} +impl<'a> START1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl W { + #[doc = "Bit 0 - Comparator 0 Start Comparison"] + #[inline(always)] + pub fn start0(&mut self) -> START0_W { + START0_W { w: self } + } + #[doc = "Bit 1 - Comparator 1 Start Comparison"] + #[inline(always)] + pub fn start1(&mut self) -> START1_W { + START1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u8; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/ac/dbgctrl.rs b/pac/atsamc20g/src/ac/dbgctrl.rs new file mode 100644 index 000000000000..53636eb2b339 --- /dev/null +++ b/pac/atsamc20g/src/ac/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Debug Run"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Debug Run"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/ac/evctrl.rs b/pac/atsamc20g/src/ac/evctrl.rs new file mode 100644 index 000000000000..5e5e650d6de9 --- /dev/null +++ b/pac/atsamc20g/src/ac/evctrl.rs @@ -0,0 +1,395 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COMPEO0` reader - Comparator 0 Event Output Enable"] +pub struct COMPEO0_R(crate::FieldReader); +impl COMPEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPEO0` writer - Comparator 0 Event Output Enable"] +pub struct COMPEO0_W<'a> { + w: &'a mut W, +} +impl<'a> COMPEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `COMPEO1` reader - Comparator 1 Event Output Enable"] +pub struct COMPEO1_R(crate::FieldReader); +impl COMPEO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPEO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPEO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPEO1` writer - Comparator 1 Event Output Enable"] +pub struct COMPEO1_W<'a> { + w: &'a mut W, +} +impl<'a> COMPEO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WINEO0` reader - Window 0 Event Output Enable"] +pub struct WINEO0_R(crate::FieldReader); +impl WINEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINEO0` writer - Window 0 Event Output Enable"] +pub struct WINEO0_W<'a> { + w: &'a mut W, +} +impl<'a> WINEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `COMPEI0` reader - Comparator 0 Event Input Enable"] +pub struct COMPEI0_R(crate::FieldReader); +impl COMPEI0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPEI0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPEI0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPEI0` writer - Comparator 0 Event Input Enable"] +pub struct COMPEI0_W<'a> { + w: &'a mut W, +} +impl<'a> COMPEI0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `COMPEI1` reader - Comparator 1 Event Input Enable"] +pub struct COMPEI1_R(crate::FieldReader); +impl COMPEI1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPEI1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPEI1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPEI1` writer - Comparator 1 Event Input Enable"] +pub struct COMPEI1_W<'a> { + w: &'a mut W, +} +impl<'a> COMPEI1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `INVEI0` reader - Comparator 0 Input Event Invert Enable"] +pub struct INVEI0_R(crate::FieldReader); +impl INVEI0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEI0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEI0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEI0` writer - Comparator 0 Input Event Invert Enable"] +pub struct INVEI0_W<'a> { + w: &'a mut W, +} +impl<'a> INVEI0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u16 & 0x01) << 12); + self.w + } +} +#[doc = "Field `INVEI1` reader - Comparator 1 Input Event Invert Enable"] +pub struct INVEI1_R(crate::FieldReader); +impl INVEI1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEI1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEI1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEI1` writer - Comparator 1 Input Event Invert Enable"] +pub struct INVEI1_W<'a> { + w: &'a mut W, +} +impl<'a> INVEI1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u16 & 0x01) << 13); + self.w + } +} +impl R { + #[doc = "Bit 0 - Comparator 0 Event Output Enable"] + #[inline(always)] + pub fn compeo0(&self) -> COMPEO0_R { + COMPEO0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Comparator 1 Event Output Enable"] + #[inline(always)] + pub fn compeo1(&self) -> COMPEO1_R { + COMPEO1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - Window 0 Event Output Enable"] + #[inline(always)] + pub fn wineo0(&self) -> WINEO0_R { + WINEO0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 8 - Comparator 0 Event Input Enable"] + #[inline(always)] + pub fn compei0(&self) -> COMPEI0_R { + COMPEI0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Comparator 1 Event Input Enable"] + #[inline(always)] + pub fn compei1(&self) -> COMPEI1_R { + COMPEI1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 12 - Comparator 0 Input Event Invert Enable"] + #[inline(always)] + pub fn invei0(&self) -> INVEI0_R { + INVEI0_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Comparator 1 Input Event Invert Enable"] + #[inline(always)] + pub fn invei1(&self) -> INVEI1_R { + INVEI1_R::new(((self.bits >> 13) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Comparator 0 Event Output Enable"] + #[inline(always)] + pub fn compeo0(&mut self) -> COMPEO0_W { + COMPEO0_W { w: self } + } + #[doc = "Bit 1 - Comparator 1 Event Output Enable"] + #[inline(always)] + pub fn compeo1(&mut self) -> COMPEO1_W { + COMPEO1_W { w: self } + } + #[doc = "Bit 4 - Window 0 Event Output Enable"] + #[inline(always)] + pub fn wineo0(&mut self) -> WINEO0_W { + WINEO0_W { w: self } + } + #[doc = "Bit 8 - Comparator 0 Event Input Enable"] + #[inline(always)] + pub fn compei0(&mut self) -> COMPEI0_W { + COMPEI0_W { w: self } + } + #[doc = "Bit 9 - Comparator 1 Event Input Enable"] + #[inline(always)] + pub fn compei1(&mut self) -> COMPEI1_W { + COMPEI1_W { w: self } + } + #[doc = "Bit 12 - Comparator 0 Input Event Invert Enable"] + #[inline(always)] + pub fn invei0(&mut self) -> INVEI0_W { + INVEI0_W { w: self } + } + #[doc = "Bit 13 - Comparator 1 Input Event Invert Enable"] + #[inline(always)] + pub fn invei1(&mut self) -> INVEI1_W { + INVEI1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/ac/intenclr.rs b/pac/atsamc20g/src/ac/intenclr.rs new file mode 100644 index 000000000000..45e3320d293e --- /dev/null +++ b/pac/atsamc20g/src/ac/intenclr.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COMP0` reader - Comparator 0 Interrupt Enable"] +pub struct COMP0_R(crate::FieldReader); +impl COMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP0` writer - Comparator 0 Interrupt Enable"] +pub struct COMP0_W<'a> { + w: &'a mut W, +} +impl<'a> COMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `COMP1` reader - Comparator 1 Interrupt Enable"] +pub struct COMP1_R(crate::FieldReader); +impl COMP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP1` writer - Comparator 1 Interrupt Enable"] +pub struct COMP1_W<'a> { + w: &'a mut W, +} +impl<'a> COMP1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WIN0` reader - Window 0 Interrupt Enable"] +pub struct WIN0_R(crate::FieldReader); +impl WIN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WIN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WIN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WIN0` writer - Window 0 Interrupt Enable"] +pub struct WIN0_W<'a> { + w: &'a mut W, +} +impl<'a> WIN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +impl R { + #[doc = "Bit 0 - Comparator 0 Interrupt Enable"] + #[inline(always)] + pub fn comp0(&self) -> COMP0_R { + COMP0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Comparator 1 Interrupt Enable"] + #[inline(always)] + pub fn comp1(&self) -> COMP1_R { + COMP1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - Window 0 Interrupt Enable"] + #[inline(always)] + pub fn win0(&self) -> WIN0_R { + WIN0_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Comparator 0 Interrupt Enable"] + #[inline(always)] + pub fn comp0(&mut self) -> COMP0_W { + COMP0_W { w: self } + } + #[doc = "Bit 1 - Comparator 1 Interrupt Enable"] + #[inline(always)] + pub fn comp1(&mut self) -> COMP1_W { + COMP1_W { w: self } + } + #[doc = "Bit 4 - Window 0 Interrupt Enable"] + #[inline(always)] + pub fn win0(&mut self) -> WIN0_W { + WIN0_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/ac/intenset.rs b/pac/atsamc20g/src/ac/intenset.rs new file mode 100644 index 000000000000..5354a4d111d0 --- /dev/null +++ b/pac/atsamc20g/src/ac/intenset.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COMP0` reader - Comparator 0 Interrupt Enable"] +pub struct COMP0_R(crate::FieldReader); +impl COMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP0` writer - Comparator 0 Interrupt Enable"] +pub struct COMP0_W<'a> { + w: &'a mut W, +} +impl<'a> COMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `COMP1` reader - Comparator 1 Interrupt Enable"] +pub struct COMP1_R(crate::FieldReader); +impl COMP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP1` writer - Comparator 1 Interrupt Enable"] +pub struct COMP1_W<'a> { + w: &'a mut W, +} +impl<'a> COMP1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WIN0` reader - Window 0 Interrupt Enable"] +pub struct WIN0_R(crate::FieldReader); +impl WIN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WIN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WIN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WIN0` writer - Window 0 Interrupt Enable"] +pub struct WIN0_W<'a> { + w: &'a mut W, +} +impl<'a> WIN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +impl R { + #[doc = "Bit 0 - Comparator 0 Interrupt Enable"] + #[inline(always)] + pub fn comp0(&self) -> COMP0_R { + COMP0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Comparator 1 Interrupt Enable"] + #[inline(always)] + pub fn comp1(&self) -> COMP1_R { + COMP1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - Window 0 Interrupt Enable"] + #[inline(always)] + pub fn win0(&self) -> WIN0_R { + WIN0_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Comparator 0 Interrupt Enable"] + #[inline(always)] + pub fn comp0(&mut self) -> COMP0_W { + COMP0_W { w: self } + } + #[doc = "Bit 1 - Comparator 1 Interrupt Enable"] + #[inline(always)] + pub fn comp1(&mut self) -> COMP1_W { + COMP1_W { w: self } + } + #[doc = "Bit 4 - Window 0 Interrupt Enable"] + #[inline(always)] + pub fn win0(&mut self) -> WIN0_W { + WIN0_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/ac/intflag.rs b/pac/atsamc20g/src/ac/intflag.rs new file mode 100644 index 000000000000..7da0fea7569f --- /dev/null +++ b/pac/atsamc20g/src/ac/intflag.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COMP0` reader - Comparator 0"] +pub struct COMP0_R(crate::FieldReader); +impl COMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP0` writer - Comparator 0"] +pub struct COMP0_W<'a> { + w: &'a mut W, +} +impl<'a> COMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `COMP1` reader - Comparator 1"] +pub struct COMP1_R(crate::FieldReader); +impl COMP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP1` writer - Comparator 1"] +pub struct COMP1_W<'a> { + w: &'a mut W, +} +impl<'a> COMP1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WIN0` reader - Window 0"] +pub struct WIN0_R(crate::FieldReader); +impl WIN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WIN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WIN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WIN0` writer - Window 0"] +pub struct WIN0_W<'a> { + w: &'a mut W, +} +impl<'a> WIN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +impl R { + #[doc = "Bit 0 - Comparator 0"] + #[inline(always)] + pub fn comp0(&self) -> COMP0_R { + COMP0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Comparator 1"] + #[inline(always)] + pub fn comp1(&self) -> COMP1_R { + COMP1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - Window 0"] + #[inline(always)] + pub fn win0(&self) -> WIN0_R { + WIN0_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Comparator 0"] + #[inline(always)] + pub fn comp0(&mut self) -> COMP0_W { + COMP0_W { w: self } + } + #[doc = "Bit 1 - Comparator 1"] + #[inline(always)] + pub fn comp1(&mut self) -> COMP1_W { + COMP1_W { w: self } + } + #[doc = "Bit 4 - Window 0"] + #[inline(always)] + pub fn win0(&mut self) -> WIN0_W { + WIN0_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/ac/scaler.rs b/pac/atsamc20g/src/ac/scaler.rs new file mode 100644 index 000000000000..091cacfaeb4b --- /dev/null +++ b/pac/atsamc20g/src/ac/scaler.rs @@ -0,0 +1,104 @@ +#[doc = "Register `SCALER[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SCALER[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `VALUE` reader - Scaler Value"] +pub struct VALUE_R(crate::FieldReader); +impl VALUE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + VALUE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VALUE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VALUE` writer - Scaler Value"] +pub struct VALUE_W<'a> { + w: &'a mut W, +} +impl<'a> VALUE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u8 & 0x3f); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Scaler Value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - Scaler Value"] + #[inline(always)] + pub fn value(&mut self) -> VALUE_W { + VALUE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Scaler n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [scaler](index.html) module"] +pub struct SCALER_SPEC; +impl crate::RegisterSpec for SCALER_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [scaler::R](R) reader structure"] +impl crate::Readable for SCALER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [scaler::W](W) writer structure"] +impl crate::Writable for SCALER_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SCALER[%s] +to value 0"] +impl crate::Resettable for SCALER_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/ac/statusa.rs b/pac/atsamc20g/src/ac/statusa.rs new file mode 100644 index 000000000000..7b98c567e8a6 --- /dev/null +++ b/pac/atsamc20g/src/ac/statusa.rs @@ -0,0 +1,135 @@ +#[doc = "Register `STATUSA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `STATE0` reader - Comparator 0 Current State"] +pub struct STATE0_R(crate::FieldReader); +impl STATE0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STATE0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STATE0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STATE1` reader - Comparator 1 Current State"] +pub struct STATE1_R(crate::FieldReader); +impl STATE1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STATE1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STATE1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Window 0 Current State\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WSTATE0_A { + #[doc = "0: Signal is above window"] + ABOVE = 0, + #[doc = "1: Signal is inside window"] + INSIDE = 1, + #[doc = "2: Signal is below window"] + BELOW = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WSTATE0_A) -> Self { + variant as _ + } +} +#[doc = "Field `WSTATE0` reader - Window 0 Current State"] +pub struct WSTATE0_R(crate::FieldReader); +impl WSTATE0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WSTATE0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(WSTATE0_A::ABOVE), + 1 => Some(WSTATE0_A::INSIDE), + 2 => Some(WSTATE0_A::BELOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `ABOVE`"] + #[inline(always)] + pub fn is_above(&self) -> bool { + **self == WSTATE0_A::ABOVE + } + #[doc = "Checks if the value of the field is `INSIDE`"] + #[inline(always)] + pub fn is_inside(&self) -> bool { + **self == WSTATE0_A::INSIDE + } + #[doc = "Checks if the value of the field is `BELOW`"] + #[inline(always)] + pub fn is_below(&self) -> bool { + **self == WSTATE0_A::BELOW + } +} +impl core::ops::Deref for WSTATE0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Comparator 0 Current State"] + #[inline(always)] + pub fn state0(&self) -> STATE0_R { + STATE0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Comparator 1 Current State"] + #[inline(always)] + pub fn state1(&self) -> STATE1_R { + STATE1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 4:5 - Window 0 Current State"] + #[inline(always)] + pub fn wstate0(&self) -> WSTATE0_R { + WSTATE0_R::new(((self.bits >> 4) & 0x03) as u8) + } +} +#[doc = "Status A\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [statusa](index.html) module"] +pub struct STATUSA_SPEC; +impl crate::RegisterSpec for STATUSA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [statusa::R](R) reader structure"] +impl crate::Readable for STATUSA_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUSA to value 0"] +impl crate::Resettable for STATUSA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/ac/statusb.rs b/pac/atsamc20g/src/ac/statusb.rs new file mode 100644 index 000000000000..dd27eb62fd27 --- /dev/null +++ b/pac/atsamc20g/src/ac/statusb.rs @@ -0,0 +1,73 @@ +#[doc = "Register `STATUSB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `READY0` reader - Comparator 0 Ready"] +pub struct READY0_R(crate::FieldReader); +impl READY0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + READY0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for READY0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `READY1` reader - Comparator 1 Ready"] +pub struct READY1_R(crate::FieldReader); +impl READY1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + READY1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for READY1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Comparator 0 Ready"] + #[inline(always)] + pub fn ready0(&self) -> READY0_R { + READY0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Comparator 1 Ready"] + #[inline(always)] + pub fn ready1(&self) -> READY1_R { + READY1_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +#[doc = "Status B\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [statusb](index.html) module"] +pub struct STATUSB_SPEC; +impl crate::RegisterSpec for STATUSB_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [statusb::R](R) reader structure"] +impl crate::Readable for STATUSB_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUSB to value 0"] +impl crate::Resettable for STATUSB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/ac/syncbusy.rs b/pac/atsamc20g/src/ac/syncbusy.rs new file mode 100644 index 000000000000..f3f2b1f4f1a6 --- /dev/null +++ b/pac/atsamc20g/src/ac/syncbusy.rs @@ -0,0 +1,133 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - Enable Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINCTRL` reader - WINCTRL Synchronization Busy"] +pub struct WINCTRL_R(crate::FieldReader); +impl WINCTRL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINCTRL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINCTRL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPCTRL0` reader - COMPCTRL 0 Synchronization Busy"] +pub struct COMPCTRL0_R(crate::FieldReader); +impl COMPCTRL0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPCTRL0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPCTRL0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPCTRL1` reader - COMPCTRL 1 Synchronization Busy"] +pub struct COMPCTRL1_R(crate::FieldReader); +impl COMPCTRL1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPCTRL1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPCTRL1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - WINCTRL Synchronization Busy"] + #[inline(always)] + pub fn winctrl(&self) -> WINCTRL_R { + WINCTRL_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - COMPCTRL 0 Synchronization Busy"] + #[inline(always)] + pub fn compctrl0(&self) -> COMPCTRL0_R { + COMPCTRL0_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - COMPCTRL 1 Synchronization Busy"] + #[inline(always)] + pub fn compctrl1(&self) -> COMPCTRL1_R { + COMPCTRL1_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +#[doc = "Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/ac/winctrl.rs b/pac/atsamc20g/src/ac/winctrl.rs new file mode 100644 index 000000000000..3259570489e0 --- /dev/null +++ b/pac/atsamc20g/src/ac/winctrl.rs @@ -0,0 +1,225 @@ +#[doc = "Register `WINCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WINCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WEN0` reader - Window 0 Mode Enable"] +pub struct WEN0_R(crate::FieldReader); +impl WEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WEN0` writer - Window 0 Mode Enable"] +pub struct WEN0_W<'a> { + w: &'a mut W, +} +impl<'a> WEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Window 0 Interrupt Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WINTSEL0_A { + #[doc = "0: Interrupt on signal above window"] + ABOVE = 0, + #[doc = "1: Interrupt on signal inside window"] + INSIDE = 1, + #[doc = "2: Interrupt on signal below window"] + BELOW = 2, + #[doc = "3: Interrupt on signal outside window"] + OUTSIDE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WINTSEL0_A) -> Self { + variant as _ + } +} +#[doc = "Field `WINTSEL0` reader - Window 0 Interrupt Selection"] +pub struct WINTSEL0_R(crate::FieldReader); +impl WINTSEL0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WINTSEL0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> WINTSEL0_A { + match self.bits { + 0 => WINTSEL0_A::ABOVE, + 1 => WINTSEL0_A::INSIDE, + 2 => WINTSEL0_A::BELOW, + 3 => WINTSEL0_A::OUTSIDE, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `ABOVE`"] + #[inline(always)] + pub fn is_above(&self) -> bool { + **self == WINTSEL0_A::ABOVE + } + #[doc = "Checks if the value of the field is `INSIDE`"] + #[inline(always)] + pub fn is_inside(&self) -> bool { + **self == WINTSEL0_A::INSIDE + } + #[doc = "Checks if the value of the field is `BELOW`"] + #[inline(always)] + pub fn is_below(&self) -> bool { + **self == WINTSEL0_A::BELOW + } + #[doc = "Checks if the value of the field is `OUTSIDE`"] + #[inline(always)] + pub fn is_outside(&self) -> bool { + **self == WINTSEL0_A::OUTSIDE + } +} +impl core::ops::Deref for WINTSEL0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINTSEL0` writer - Window 0 Interrupt Selection"] +pub struct WINTSEL0_W<'a> { + w: &'a mut W, +} +impl<'a> WINTSEL0_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WINTSEL0_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Interrupt on signal above window"] + #[inline(always)] + pub fn above(self) -> &'a mut W { + self.variant(WINTSEL0_A::ABOVE) + } + #[doc = "Interrupt on signal inside window"] + #[inline(always)] + pub fn inside(self) -> &'a mut W { + self.variant(WINTSEL0_A::INSIDE) + } + #[doc = "Interrupt on signal below window"] + #[inline(always)] + pub fn below(self) -> &'a mut W { + self.variant(WINTSEL0_A::BELOW) + } + #[doc = "Interrupt on signal outside window"] + #[inline(always)] + pub fn outside(self) -> &'a mut W { + self.variant(WINTSEL0_A::OUTSIDE) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 1)) | ((value as u8 & 0x03) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - Window 0 Mode Enable"] + #[inline(always)] + pub fn wen0(&self) -> WEN0_R { + WEN0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bits 1:2 - Window 0 Interrupt Selection"] + #[inline(always)] + pub fn wintsel0(&self) -> WINTSEL0_R { + WINTSEL0_R::new(((self.bits >> 1) & 0x03) as u8) + } +} +impl W { + #[doc = "Bit 0 - Window 0 Mode Enable"] + #[inline(always)] + pub fn wen0(&mut self) -> WEN0_W { + WEN0_W { w: self } + } + #[doc = "Bits 1:2 - Window 0 Interrupt Selection"] + #[inline(always)] + pub fn wintsel0(&mut self) -> WINTSEL0_W { + WINTSEL0_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Window Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [winctrl](index.html) module"] +pub struct WINCTRL_SPEC; +impl crate::RegisterSpec for WINCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [winctrl::R](R) reader structure"] +impl crate::Readable for WINCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [winctrl::W](W) writer structure"] +impl crate::Writable for WINCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WINCTRL to value 0"] +impl crate::Resettable for WINCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/adc0.rs b/pac/atsamc20g/src/adc0.rs new file mode 100644 index 000000000000..453f56ed28c8 --- /dev/null +++ b/pac/atsamc20g/src/adc0.rs @@ -0,0 +1,141 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + #[doc = "0x01 - Control B"] + pub ctrlb: crate::Reg, + #[doc = "0x02 - Reference Control"] + pub refctrl: crate::Reg, + #[doc = "0x03 - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x04 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x05 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x06 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x07 - Sequence Status"] + pub seqstatus: crate::Reg, + #[doc = "0x08 - Input Control"] + pub inputctrl: crate::Reg, + #[doc = "0x0a - Control C"] + pub ctrlc: crate::Reg, + #[doc = "0x0c - Average Control"] + pub avgctrl: crate::Reg, + #[doc = "0x0d - Sample Time Control"] + pub sampctrl: crate::Reg, + #[doc = "0x0e - Window Monitor Lower Threshold"] + pub winlt: crate::Reg, + #[doc = "0x10 - Window Monitor Upper Threshold"] + pub winut: crate::Reg, + #[doc = "0x12 - Gain Correction"] + pub gaincorr: crate::Reg, + #[doc = "0x14 - Offset Correction"] + pub offsetcorr: crate::Reg, + _reserved16: [u8; 0x02], + #[doc = "0x18 - Software Trigger"] + pub swtrig: crate::Reg, + _reserved17: [u8; 0x03], + #[doc = "0x1c - Debug Control"] + pub dbgctrl: crate::Reg, + _reserved18: [u8; 0x03], + #[doc = "0x20 - Synchronization Busy"] + pub syncbusy: crate::Reg, + _reserved19: [u8; 0x02], + #[doc = "0x24 - Result"] + pub result: crate::Reg, + _reserved20: [u8; 0x02], + #[doc = "0x28 - Sequence Control"] + pub seqctrl: crate::Reg, + #[doc = "0x2c - Calibration"] + pub calib: crate::Reg, +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "Control B"] +pub mod ctrlb; +#[doc = "REFCTRL register accessor: an alias for `Reg`"] +pub type REFCTRL = crate::Reg; +#[doc = "Reference Control"] +pub mod refctrl; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "SEQSTATUS register accessor: an alias for `Reg`"] +pub type SEQSTATUS = crate::Reg; +#[doc = "Sequence Status"] +pub mod seqstatus; +#[doc = "INPUTCTRL register accessor: an alias for `Reg`"] +pub type INPUTCTRL = crate::Reg; +#[doc = "Input Control"] +pub mod inputctrl; +#[doc = "CTRLC register accessor: an alias for `Reg`"] +pub type CTRLC = crate::Reg; +#[doc = "Control C"] +pub mod ctrlc; +#[doc = "AVGCTRL register accessor: an alias for `Reg`"] +pub type AVGCTRL = crate::Reg; +#[doc = "Average Control"] +pub mod avgctrl; +#[doc = "SAMPCTRL register accessor: an alias for `Reg`"] +pub type SAMPCTRL = crate::Reg; +#[doc = "Sample Time Control"] +pub mod sampctrl; +#[doc = "WINLT register accessor: an alias for `Reg`"] +pub type WINLT = crate::Reg; +#[doc = "Window Monitor Lower Threshold"] +pub mod winlt; +#[doc = "WINUT register accessor: an alias for `Reg`"] +pub type WINUT = crate::Reg; +#[doc = "Window Monitor Upper Threshold"] +pub mod winut; +#[doc = "GAINCORR register accessor: an alias for `Reg`"] +pub type GAINCORR = crate::Reg; +#[doc = "Gain Correction"] +pub mod gaincorr; +#[doc = "OFFSETCORR register accessor: an alias for `Reg`"] +pub type OFFSETCORR = crate::Reg; +#[doc = "Offset Correction"] +pub mod offsetcorr; +#[doc = "SWTRIG register accessor: an alias for `Reg`"] +pub type SWTRIG = crate::Reg; +#[doc = "Software Trigger"] +pub mod swtrig; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Busy"] +pub mod syncbusy; +#[doc = "RESULT register accessor: an alias for `Reg`"] +pub type RESULT = crate::Reg; +#[doc = "Result"] +pub mod result; +#[doc = "SEQCTRL register accessor: an alias for `Reg`"] +pub type SEQCTRL = crate::Reg; +#[doc = "Sequence Control"] +pub mod seqctrl; +#[doc = "CALIB register accessor: an alias for `Reg`"] +pub type CALIB = crate::Reg; +#[doc = "Calibration"] +pub mod calib; diff --git a/pac/atsamc20g/src/adc0/avgctrl.rs b/pac/atsamc20g/src/adc0/avgctrl.rs new file mode 100644 index 000000000000..ddb735715c98 --- /dev/null +++ b/pac/atsamc20g/src/adc0/avgctrl.rs @@ -0,0 +1,306 @@ +#[doc = "Register `AVGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `AVGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Number of Samples to be Collected\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SAMPLENUM_A { + #[doc = "0: 1 sample"] + _1 = 0, + #[doc = "1: 2 samples"] + _2 = 1, + #[doc = "2: 4 samples"] + _4 = 2, + #[doc = "3: 8 samples"] + _8 = 3, + #[doc = "4: 16 samples"] + _16 = 4, + #[doc = "5: 32 samples"] + _32 = 5, + #[doc = "6: 64 samples"] + _64 = 6, + #[doc = "7: 128 samples"] + _128 = 7, + #[doc = "8: 256 samples"] + _256 = 8, + #[doc = "9: 512 samples"] + _512 = 9, + #[doc = "10: 1024 samples"] + _1024 = 10, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SAMPLENUM_A) -> Self { + variant as _ + } +} +#[doc = "Field `SAMPLENUM` reader - Number of Samples to be Collected"] +pub struct SAMPLENUM_R(crate::FieldReader); +impl SAMPLENUM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SAMPLENUM_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SAMPLENUM_A::_1), + 1 => Some(SAMPLENUM_A::_2), + 2 => Some(SAMPLENUM_A::_4), + 3 => Some(SAMPLENUM_A::_8), + 4 => Some(SAMPLENUM_A::_16), + 5 => Some(SAMPLENUM_A::_32), + 6 => Some(SAMPLENUM_A::_64), + 7 => Some(SAMPLENUM_A::_128), + 8 => Some(SAMPLENUM_A::_256), + 9 => Some(SAMPLENUM_A::_512), + 10 => Some(SAMPLENUM_A::_1024), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_1`"] + #[inline(always)] + pub fn is_1(&self) -> bool { + **self == SAMPLENUM_A::_1 + } + #[doc = "Checks if the value of the field is `_2`"] + #[inline(always)] + pub fn is_2(&self) -> bool { + **self == SAMPLENUM_A::_2 + } + #[doc = "Checks if the value of the field is `_4`"] + #[inline(always)] + pub fn is_4(&self) -> bool { + **self == SAMPLENUM_A::_4 + } + #[doc = "Checks if the value of the field is `_8`"] + #[inline(always)] + pub fn is_8(&self) -> bool { + **self == SAMPLENUM_A::_8 + } + #[doc = "Checks if the value of the field is `_16`"] + #[inline(always)] + pub fn is_16(&self) -> bool { + **self == SAMPLENUM_A::_16 + } + #[doc = "Checks if the value of the field is `_32`"] + #[inline(always)] + pub fn is_32(&self) -> bool { + **self == SAMPLENUM_A::_32 + } + #[doc = "Checks if the value of the field is `_64`"] + #[inline(always)] + pub fn is_64(&self) -> bool { + **self == SAMPLENUM_A::_64 + } + #[doc = "Checks if the value of the field is `_128`"] + #[inline(always)] + pub fn is_128(&self) -> bool { + **self == SAMPLENUM_A::_128 + } + #[doc = "Checks if the value of the field is `_256`"] + #[inline(always)] + pub fn is_256(&self) -> bool { + **self == SAMPLENUM_A::_256 + } + #[doc = "Checks if the value of the field is `_512`"] + #[inline(always)] + pub fn is_512(&self) -> bool { + **self == SAMPLENUM_A::_512 + } + #[doc = "Checks if the value of the field is `_1024`"] + #[inline(always)] + pub fn is_1024(&self) -> bool { + **self == SAMPLENUM_A::_1024 + } +} +impl core::ops::Deref for SAMPLENUM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SAMPLENUM` writer - Number of Samples to be Collected"] +pub struct SAMPLENUM_W<'a> { + w: &'a mut W, +} +impl<'a> SAMPLENUM_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SAMPLENUM_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "1 sample"] + #[inline(always)] + pub fn _1(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_1) + } + #[doc = "2 samples"] + #[inline(always)] + pub fn _2(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_2) + } + #[doc = "4 samples"] + #[inline(always)] + pub fn _4(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_4) + } + #[doc = "8 samples"] + #[inline(always)] + pub fn _8(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_8) + } + #[doc = "16 samples"] + #[inline(always)] + pub fn _16(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_16) + } + #[doc = "32 samples"] + #[inline(always)] + pub fn _32(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_32) + } + #[doc = "64 samples"] + #[inline(always)] + pub fn _64(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_64) + } + #[doc = "128 samples"] + #[inline(always)] + pub fn _128(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_128) + } + #[doc = "256 samples"] + #[inline(always)] + pub fn _256(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_256) + } + #[doc = "512 samples"] + #[inline(always)] + pub fn _512(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_512) + } + #[doc = "1024 samples"] + #[inline(always)] + pub fn _1024(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +#[doc = "Field `ADJRES` reader - Adjusting Result / Division Coefficient"] +pub struct ADJRES_R(crate::FieldReader); +impl ADJRES_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ADJRES_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADJRES_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADJRES` writer - Adjusting Result / Division Coefficient"] +pub struct ADJRES_W<'a> { + w: &'a mut W, +} +impl<'a> ADJRES_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 4)) | ((value as u8 & 0x07) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Number of Samples to be Collected"] + #[inline(always)] + pub fn samplenum(&self) -> SAMPLENUM_R { + SAMPLENUM_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:6 - Adjusting Result / Division Coefficient"] + #[inline(always)] + pub fn adjres(&self) -> ADJRES_R { + ADJRES_R::new(((self.bits >> 4) & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Number of Samples to be Collected"] + #[inline(always)] + pub fn samplenum(&mut self) -> SAMPLENUM_W { + SAMPLENUM_W { w: self } + } + #[doc = "Bits 4:6 - Adjusting Result / Division Coefficient"] + #[inline(always)] + pub fn adjres(&mut self) -> ADJRES_W { + ADJRES_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Average Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [avgctrl](index.html) module"] +pub struct AVGCTRL_SPEC; +impl crate::RegisterSpec for AVGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [avgctrl::R](R) reader structure"] +impl crate::Readable for AVGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [avgctrl::W](W) writer structure"] +impl crate::Writable for AVGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets AVGCTRL to value 0"] +impl crate::Resettable for AVGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/adc0/calib.rs b/pac/atsamc20g/src/adc0/calib.rs new file mode 100644 index 000000000000..8a1a99b8c47d --- /dev/null +++ b/pac/atsamc20g/src/adc0/calib.rs @@ -0,0 +1,140 @@ +#[doc = "Register `CALIB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CALIB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BIASCOMP` reader - Bias Comparator Scaling"] +pub struct BIASCOMP_R(crate::FieldReader); +impl BIASCOMP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BIASCOMP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BIASCOMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BIASCOMP` writer - Bias Comparator Scaling"] +pub struct BIASCOMP_W<'a> { + w: &'a mut W, +} +impl<'a> BIASCOMP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u16 & 0x07); + self.w + } +} +#[doc = "Field `BIASREFBUF` reader - Bias Reference Buffer Scaling"] +pub struct BIASREFBUF_R(crate::FieldReader); +impl BIASREFBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BIASREFBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BIASREFBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BIASREFBUF` writer - Bias Reference Buffer Scaling"] +pub struct BIASREFBUF_W<'a> { + w: &'a mut W, +} +impl<'a> BIASREFBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u16 & 0x07) << 8); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Bias Comparator Scaling"] + #[inline(always)] + pub fn biascomp(&self) -> BIASCOMP_R { + BIASCOMP_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bits 8:10 - Bias Reference Buffer Scaling"] + #[inline(always)] + pub fn biasrefbuf(&self) -> BIASREFBUF_R { + BIASREFBUF_R::new(((self.bits >> 8) & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Bias Comparator Scaling"] + #[inline(always)] + pub fn biascomp(&mut self) -> BIASCOMP_W { + BIASCOMP_W { w: self } + } + #[doc = "Bits 8:10 - Bias Reference Buffer Scaling"] + #[inline(always)] + pub fn biasrefbuf(&mut self) -> BIASREFBUF_W { + BIASREFBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Calibration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [calib](index.html) module"] +pub struct CALIB_SPEC; +impl crate::RegisterSpec for CALIB_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [calib::R](R) reader structure"] +impl crate::Readable for CALIB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [calib::W](W) writer structure"] +impl crate::Writable for CALIB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CALIB to value 0"] +impl crate::Resettable for CALIB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/adc0/ctrla.rs b/pac/atsamc20g/src/adc0/ctrla.rs new file mode 100644 index 000000000000..47c681045f95 --- /dev/null +++ b/pac/atsamc20g/src/adc0/ctrla.rs @@ -0,0 +1,301 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SLAVEEN` reader - Slave Enable"] +pub struct SLAVEEN_R(crate::FieldReader); +impl SLAVEEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLAVEEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SLAVEEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLAVEEN` writer - Slave Enable"] +pub struct SLAVEEN_W<'a> { + w: &'a mut W, +} +impl<'a> SLAVEEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run During Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run During Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - On Demand Control"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - On Demand Control"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 5 - Slave Enable"] + #[inline(always)] + pub fn slaveen(&self) -> SLAVEEN_R { + SLAVEEN_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Run During Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 5 - Slave Enable"] + #[inline(always)] + pub fn slaveen(&mut self) -> SLAVEEN_W { + SLAVEEN_W { w: self } + } + #[doc = "Bit 6 - Run During Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/adc0/ctrlb.rs b/pac/atsamc20g/src/adc0/ctrlb.rs new file mode 100644 index 000000000000..4d39688fc975 --- /dev/null +++ b/pac/atsamc20g/src/adc0/ctrlb.rs @@ -0,0 +1,230 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Prescaler Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: Peripheral clock / 2"] + DIV2 = 0, + #[doc = "1: Peripheral clock / 4"] + DIV4 = 1, + #[doc = "2: Peripheral clock / 8"] + DIV8 = 2, + #[doc = "3: Peripheral clock / 16"] + DIV16 = 3, + #[doc = "4: Peripheral clock / 32"] + DIV32 = 4, + #[doc = "5: Peripheral clock / 64"] + DIV64 = 5, + #[doc = "6: Peripheral clock / 128"] + DIV128 = 6, + #[doc = "7: Peripheral clock / 256"] + DIV256 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler Configuration"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PRESCALER_A { + match self.bits { + 0 => PRESCALER_A::DIV2, + 1 => PRESCALER_A::DIV4, + 2 => PRESCALER_A::DIV8, + 3 => PRESCALER_A::DIV16, + 4 => PRESCALER_A::DIV32, + 5 => PRESCALER_A::DIV64, + 6 => PRESCALER_A::DIV128, + 7 => PRESCALER_A::DIV256, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == PRESCALER_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == PRESCALER_A::DIV128 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler Configuration"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Peripheral clock / 2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "Peripheral clock / 4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "Peripheral clock / 8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "Peripheral clock / 16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "Peripheral clock / 32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV32) + } + #[doc = "Peripheral clock / 64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "Peripheral clock / 128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV128) + } + #[doc = "Peripheral clock / 256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Prescaler Configuration"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Prescaler Configuration"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/adc0/ctrlc.rs b/pac/atsamc20g/src/adc0/ctrlc.rs new file mode 100644 index 000000000000..fa45a771545a --- /dev/null +++ b/pac/atsamc20g/src/adc0/ctrlc.rs @@ -0,0 +1,538 @@ +#[doc = "Register `CTRLC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIFFMODE` reader - Differential Mode"] +pub struct DIFFMODE_R(crate::FieldReader); +impl DIFFMODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIFFMODE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIFFMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIFFMODE` writer - Differential Mode"] +pub struct DIFFMODE_W<'a> { + w: &'a mut W, +} +impl<'a> DIFFMODE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `LEFTADJ` reader - Left-Adjusted Result"] +pub struct LEFTADJ_R(crate::FieldReader); +impl LEFTADJ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LEFTADJ_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LEFTADJ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LEFTADJ` writer - Left-Adjusted Result"] +pub struct LEFTADJ_W<'a> { + w: &'a mut W, +} +impl<'a> LEFTADJ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `FREERUN` reader - Free Running Mode"] +pub struct FREERUN_R(crate::FieldReader); +impl FREERUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FREERUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FREERUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FREERUN` writer - Free Running Mode"] +pub struct FREERUN_W<'a> { + w: &'a mut W, +} +impl<'a> FREERUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CORREN` reader - Digital Correction Logic Enable"] +pub struct CORREN_R(crate::FieldReader); +impl CORREN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CORREN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CORREN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CORREN` writer - Digital Correction Logic Enable"] +pub struct CORREN_W<'a> { + w: &'a mut W, +} +impl<'a> CORREN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Conversion Result Resolution\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum RESSEL_A { + #[doc = "0: 12-bit"] + _12BIT = 0, + #[doc = "1: 16-bit averaging mode"] + _16BIT = 1, + #[doc = "2: 10-bit"] + _10BIT = 2, + #[doc = "3: 8-bit"] + _8BIT = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RESSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `RESSEL` reader - Conversion Result Resolution"] +pub struct RESSEL_R(crate::FieldReader); +impl RESSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RESSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RESSEL_A { + match self.bits { + 0 => RESSEL_A::_12BIT, + 1 => RESSEL_A::_16BIT, + 2 => RESSEL_A::_10BIT, + 3 => RESSEL_A::_8BIT, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `_12BIT`"] + #[inline(always)] + pub fn is_12bit(&self) -> bool { + **self == RESSEL_A::_12BIT + } + #[doc = "Checks if the value of the field is `_16BIT`"] + #[inline(always)] + pub fn is_16bit(&self) -> bool { + **self == RESSEL_A::_16BIT + } + #[doc = "Checks if the value of the field is `_10BIT`"] + #[inline(always)] + pub fn is_10bit(&self) -> bool { + **self == RESSEL_A::_10BIT + } + #[doc = "Checks if the value of the field is `_8BIT`"] + #[inline(always)] + pub fn is_8bit(&self) -> bool { + **self == RESSEL_A::_8BIT + } +} +impl core::ops::Deref for RESSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESSEL` writer - Conversion Result Resolution"] +pub struct RESSEL_W<'a> { + w: &'a mut W, +} +impl<'a> RESSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RESSEL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "12-bit"] + #[inline(always)] + pub fn _12bit(self) -> &'a mut W { + self.variant(RESSEL_A::_12BIT) + } + #[doc = "16-bit averaging mode"] + #[inline(always)] + pub fn _16bit(self) -> &'a mut W { + self.variant(RESSEL_A::_16BIT) + } + #[doc = "10-bit"] + #[inline(always)] + pub fn _10bit(self) -> &'a mut W { + self.variant(RESSEL_A::_10BIT) + } + #[doc = "8-bit"] + #[inline(always)] + pub fn _8bit(self) -> &'a mut W { + self.variant(RESSEL_A::_8BIT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u16 & 0x03) << 4); + self.w + } +} +#[doc = "Field `R2R` reader - Rail-to-Rail mode enable"] +pub struct R2R_R(crate::FieldReader); +impl R2R_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + R2R_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for R2R_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `R2R` writer - Rail-to-Rail mode enable"] +pub struct R2R_W<'a> { + w: &'a mut W, +} +impl<'a> R2R_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Window Monitor Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WINMODE_A { + #[doc = "0: No window mode (default)"] + DISABLE = 0, + #[doc = "1: RESULT > WINLT"] + MODE1 = 1, + #[doc = "2: RESULT < WINUT"] + MODE2 = 2, + #[doc = "3: WINLT < RESULT < WINUT"] + MODE3 = 3, + #[doc = "4: !(WINLT < RESULT < WINUT)"] + MODE4 = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WINMODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `WINMODE` reader - Window Monitor Mode"] +pub struct WINMODE_R(crate::FieldReader); +impl WINMODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WINMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(WINMODE_A::DISABLE), + 1 => Some(WINMODE_A::MODE1), + 2 => Some(WINMODE_A::MODE2), + 3 => Some(WINMODE_A::MODE3), + 4 => Some(WINMODE_A::MODE4), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == WINMODE_A::DISABLE + } + #[doc = "Checks if the value of the field is `MODE1`"] + #[inline(always)] + pub fn is_mode1(&self) -> bool { + **self == WINMODE_A::MODE1 + } + #[doc = "Checks if the value of the field is `MODE2`"] + #[inline(always)] + pub fn is_mode2(&self) -> bool { + **self == WINMODE_A::MODE2 + } + #[doc = "Checks if the value of the field is `MODE3`"] + #[inline(always)] + pub fn is_mode3(&self) -> bool { + **self == WINMODE_A::MODE3 + } + #[doc = "Checks if the value of the field is `MODE4`"] + #[inline(always)] + pub fn is_mode4(&self) -> bool { + **self == WINMODE_A::MODE4 + } +} +impl core::ops::Deref for WINMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMODE` writer - Window Monitor Mode"] +pub struct WINMODE_W<'a> { + w: &'a mut W, +} +impl<'a> WINMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WINMODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No window mode (default)"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(WINMODE_A::DISABLE) + } + #[doc = "RESULT > WINLT"] + #[inline(always)] + pub fn mode1(self) -> &'a mut W { + self.variant(WINMODE_A::MODE1) + } + #[doc = "RESULT < WINUT"] + #[inline(always)] + pub fn mode2(self) -> &'a mut W { + self.variant(WINMODE_A::MODE2) + } + #[doc = "WINLT < RESULT < WINUT"] + #[inline(always)] + pub fn mode3(self) -> &'a mut W { + self.variant(WINMODE_A::MODE3) + } + #[doc = "!(WINLT < RESULT < WINUT)"] + #[inline(always)] + pub fn mode4(self) -> &'a mut W { + self.variant(WINMODE_A::MODE4) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u16 & 0x07) << 8); + self.w + } +} +impl R { + #[doc = "Bit 0 - Differential Mode"] + #[inline(always)] + pub fn diffmode(&self) -> DIFFMODE_R { + DIFFMODE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Left-Adjusted Result"] + #[inline(always)] + pub fn leftadj(&self) -> LEFTADJ_R { + LEFTADJ_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Free Running Mode"] + #[inline(always)] + pub fn freerun(&self) -> FREERUN_R { + FREERUN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Digital Correction Logic Enable"] + #[inline(always)] + pub fn corren(&self) -> CORREN_R { + CORREN_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bits 4:5 - Conversion Result Resolution"] + #[inline(always)] + pub fn ressel(&self) -> RESSEL_R { + RESSEL_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bit 7 - Rail-to-Rail mode enable"] + #[inline(always)] + pub fn r2r(&self) -> R2R_R { + R2R_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Window Monitor Mode"] + #[inline(always)] + pub fn winmode(&self) -> WINMODE_R { + WINMODE_R::new(((self.bits >> 8) & 0x07) as u8) + } +} +impl W { + #[doc = "Bit 0 - Differential Mode"] + #[inline(always)] + pub fn diffmode(&mut self) -> DIFFMODE_W { + DIFFMODE_W { w: self } + } + #[doc = "Bit 1 - Left-Adjusted Result"] + #[inline(always)] + pub fn leftadj(&mut self) -> LEFTADJ_W { + LEFTADJ_W { w: self } + } + #[doc = "Bit 2 - Free Running Mode"] + #[inline(always)] + pub fn freerun(&mut self) -> FREERUN_W { + FREERUN_W { w: self } + } + #[doc = "Bit 3 - Digital Correction Logic Enable"] + #[inline(always)] + pub fn corren(&mut self) -> CORREN_W { + CORREN_W { w: self } + } + #[doc = "Bits 4:5 - Conversion Result Resolution"] + #[inline(always)] + pub fn ressel(&mut self) -> RESSEL_W { + RESSEL_W { w: self } + } + #[doc = "Bit 7 - Rail-to-Rail mode enable"] + #[inline(always)] + pub fn r2r(&mut self) -> R2R_W { + R2R_W { w: self } + } + #[doc = "Bits 8:10 - Window Monitor Mode"] + #[inline(always)] + pub fn winmode(&mut self) -> WINMODE_W { + WINMODE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control C\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlc](index.html) module"] +pub struct CTRLC_SPEC; +impl crate::RegisterSpec for CTRLC_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrlc::R](R) reader structure"] +impl crate::Readable for CTRLC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlc::W](W) writer structure"] +impl crate::Writable for CTRLC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLC to value 0"] +impl crate::Resettable for CTRLC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/adc0/dbgctrl.rs b/pac/atsamc20g/src/adc0/dbgctrl.rs new file mode 100644 index 000000000000..53636eb2b339 --- /dev/null +++ b/pac/atsamc20g/src/adc0/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Debug Run"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Debug Run"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/adc0/evctrl.rs b/pac/atsamc20g/src/adc0/evctrl.rs new file mode 100644 index 000000000000..295508f82de3 --- /dev/null +++ b/pac/atsamc20g/src/adc0/evctrl.rs @@ -0,0 +1,348 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FLUSHEI` reader - Flush Event Input Enable"] +pub struct FLUSHEI_R(crate::FieldReader); +impl FLUSHEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FLUSHEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FLUSHEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLUSHEI` writer - Flush Event Input Enable"] +pub struct FLUSHEI_W<'a> { + w: &'a mut W, +} +impl<'a> FLUSHEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `STARTEI` reader - Start Conversion Event Input Enable"] +pub struct STARTEI_R(crate::FieldReader); +impl STARTEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STARTEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STARTEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STARTEI` writer - Start Conversion Event Input Enable"] +pub struct STARTEI_W<'a> { + w: &'a mut W, +} +impl<'a> STARTEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `FLUSHINV` reader - Flush Event Invert Enable"] +pub struct FLUSHINV_R(crate::FieldReader); +impl FLUSHINV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FLUSHINV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FLUSHINV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLUSHINV` writer - Flush Event Invert Enable"] +pub struct FLUSHINV_W<'a> { + w: &'a mut W, +} +impl<'a> FLUSHINV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `STARTINV` reader - Start Event Invert Enable"] +pub struct STARTINV_R(crate::FieldReader); +impl STARTINV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STARTINV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STARTINV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STARTINV` writer - Start Event Invert Enable"] +pub struct STARTINV_W<'a> { + w: &'a mut W, +} +impl<'a> STARTINV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `RESRDYEO` reader - Result Ready Event Out"] +pub struct RESRDYEO_R(crate::FieldReader); +impl RESRDYEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESRDYEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESRDYEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESRDYEO` writer - Result Ready Event Out"] +pub struct RESRDYEO_W<'a> { + w: &'a mut W, +} +impl<'a> RESRDYEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `WINMONEO` reader - Window Monitor Event Out"] +pub struct WINMONEO_R(crate::FieldReader); +impl WINMONEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINMONEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINMONEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMONEO` writer - Window Monitor Event Out"] +pub struct WINMONEO_W<'a> { + w: &'a mut W, +} +impl<'a> WINMONEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Flush Event Input Enable"] + #[inline(always)] + pub fn flushei(&self) -> FLUSHEI_R { + FLUSHEI_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Start Conversion Event Input Enable"] + #[inline(always)] + pub fn startei(&self) -> STARTEI_R { + STARTEI_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Flush Event Invert Enable"] + #[inline(always)] + pub fn flushinv(&self) -> FLUSHINV_R { + FLUSHINV_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Start Event Invert Enable"] + #[inline(always)] + pub fn startinv(&self) -> STARTINV_R { + STARTINV_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Result Ready Event Out"] + #[inline(always)] + pub fn resrdyeo(&self) -> RESRDYEO_R { + RESRDYEO_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Window Monitor Event Out"] + #[inline(always)] + pub fn winmoneo(&self) -> WINMONEO_R { + WINMONEO_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Flush Event Input Enable"] + #[inline(always)] + pub fn flushei(&mut self) -> FLUSHEI_W { + FLUSHEI_W { w: self } + } + #[doc = "Bit 1 - Start Conversion Event Input Enable"] + #[inline(always)] + pub fn startei(&mut self) -> STARTEI_W { + STARTEI_W { w: self } + } + #[doc = "Bit 2 - Flush Event Invert Enable"] + #[inline(always)] + pub fn flushinv(&mut self) -> FLUSHINV_W { + FLUSHINV_W { w: self } + } + #[doc = "Bit 3 - Start Event Invert Enable"] + #[inline(always)] + pub fn startinv(&mut self) -> STARTINV_W { + STARTINV_W { w: self } + } + #[doc = "Bit 4 - Result Ready Event Out"] + #[inline(always)] + pub fn resrdyeo(&mut self) -> RESRDYEO_W { + RESRDYEO_W { w: self } + } + #[doc = "Bit 5 - Window Monitor Event Out"] + #[inline(always)] + pub fn winmoneo(&mut self) -> WINMONEO_W { + WINMONEO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/adc0/gaincorr.rs b/pac/atsamc20g/src/adc0/gaincorr.rs new file mode 100644 index 000000000000..496cb8c6021c --- /dev/null +++ b/pac/atsamc20g/src/adc0/gaincorr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `GAINCORR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GAINCORR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `GAINCORR` reader - Gain Correction Value"] +pub struct GAINCORR_R(crate::FieldReader); +impl GAINCORR_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + GAINCORR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GAINCORR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GAINCORR` writer - Gain Correction Value"] +pub struct GAINCORR_W<'a> { + w: &'a mut W, +} +impl<'a> GAINCORR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0fff) | (value as u16 & 0x0fff); + self.w + } +} +impl R { + #[doc = "Bits 0:11 - Gain Correction Value"] + #[inline(always)] + pub fn gaincorr(&self) -> GAINCORR_R { + GAINCORR_R::new((self.bits & 0x0fff) as u16) + } +} +impl W { + #[doc = "Bits 0:11 - Gain Correction Value"] + #[inline(always)] + pub fn gaincorr(&mut self) -> GAINCORR_W { + GAINCORR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Gain Correction\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gaincorr](index.html) module"] +pub struct GAINCORR_SPEC; +impl crate::RegisterSpec for GAINCORR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [gaincorr::R](R) reader structure"] +impl crate::Readable for GAINCORR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gaincorr::W](W) writer structure"] +impl crate::Writable for GAINCORR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets GAINCORR to value 0"] +impl crate::Resettable for GAINCORR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/adc0/inputctrl.rs b/pac/atsamc20g/src/adc0/inputctrl.rs new file mode 100644 index 000000000000..e0bd7489b5a5 --- /dev/null +++ b/pac/atsamc20g/src/adc0/inputctrl.rs @@ -0,0 +1,472 @@ +#[doc = "Register `INPUTCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INPUTCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Positive Mux Input Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MUXPOS_A { + #[doc = "0: ADC AIN0 Pin"] + AIN0 = 0, + #[doc = "1: ADC AIN1 Pin"] + AIN1 = 1, + #[doc = "2: ADC AIN2 Pin"] + AIN2 = 2, + #[doc = "3: ADC AIN3 Pin"] + AIN3 = 3, + #[doc = "4: ADC AIN4 Pin"] + AIN4 = 4, + #[doc = "5: ADC AIN5 Pin"] + AIN5 = 5, + #[doc = "6: ADC AIN6 Pin"] + AIN6 = 6, + #[doc = "7: ADC AIN7 Pin"] + AIN7 = 7, + #[doc = "8: ADC AIN8 Pin"] + AIN8 = 8, + #[doc = "9: ADC AIN9 Pin"] + AIN9 = 9, + #[doc = "10: ADC AIN10 Pin"] + AIN10 = 10, + #[doc = "11: ADC AIN11 Pin"] + AIN11 = 11, + #[doc = "25: Bandgap Voltage"] + BANDGAP = 25, + #[doc = "26: 1/4 Scaled Core Supply"] + SCALEDCOREVCC = 26, + #[doc = "27: 1/4 Scaled I/O Supply"] + SCALEDIOVCC = 27, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MUXPOS_A) -> Self { + variant as _ + } +} +#[doc = "Field `MUXPOS` reader - Positive Mux Input Selection"] +pub struct MUXPOS_R(crate::FieldReader); +impl MUXPOS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MUXPOS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MUXPOS_A::AIN0), + 1 => Some(MUXPOS_A::AIN1), + 2 => Some(MUXPOS_A::AIN2), + 3 => Some(MUXPOS_A::AIN3), + 4 => Some(MUXPOS_A::AIN4), + 5 => Some(MUXPOS_A::AIN5), + 6 => Some(MUXPOS_A::AIN6), + 7 => Some(MUXPOS_A::AIN7), + 8 => Some(MUXPOS_A::AIN8), + 9 => Some(MUXPOS_A::AIN9), + 10 => Some(MUXPOS_A::AIN10), + 11 => Some(MUXPOS_A::AIN11), + 25 => Some(MUXPOS_A::BANDGAP), + 26 => Some(MUXPOS_A::SCALEDCOREVCC), + 27 => Some(MUXPOS_A::SCALEDIOVCC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `AIN0`"] + #[inline(always)] + pub fn is_ain0(&self) -> bool { + **self == MUXPOS_A::AIN0 + } + #[doc = "Checks if the value of the field is `AIN1`"] + #[inline(always)] + pub fn is_ain1(&self) -> bool { + **self == MUXPOS_A::AIN1 + } + #[doc = "Checks if the value of the field is `AIN2`"] + #[inline(always)] + pub fn is_ain2(&self) -> bool { + **self == MUXPOS_A::AIN2 + } + #[doc = "Checks if the value of the field is `AIN3`"] + #[inline(always)] + pub fn is_ain3(&self) -> bool { + **self == MUXPOS_A::AIN3 + } + #[doc = "Checks if the value of the field is `AIN4`"] + #[inline(always)] + pub fn is_ain4(&self) -> bool { + **self == MUXPOS_A::AIN4 + } + #[doc = "Checks if the value of the field is `AIN5`"] + #[inline(always)] + pub fn is_ain5(&self) -> bool { + **self == MUXPOS_A::AIN5 + } + #[doc = "Checks if the value of the field is `AIN6`"] + #[inline(always)] + pub fn is_ain6(&self) -> bool { + **self == MUXPOS_A::AIN6 + } + #[doc = "Checks if the value of the field is `AIN7`"] + #[inline(always)] + pub fn is_ain7(&self) -> bool { + **self == MUXPOS_A::AIN7 + } + #[doc = "Checks if the value of the field is `AIN8`"] + #[inline(always)] + pub fn is_ain8(&self) -> bool { + **self == MUXPOS_A::AIN8 + } + #[doc = "Checks if the value of the field is `AIN9`"] + #[inline(always)] + pub fn is_ain9(&self) -> bool { + **self == MUXPOS_A::AIN9 + } + #[doc = "Checks if the value of the field is `AIN10`"] + #[inline(always)] + pub fn is_ain10(&self) -> bool { + **self == MUXPOS_A::AIN10 + } + #[doc = "Checks if the value of the field is `AIN11`"] + #[inline(always)] + pub fn is_ain11(&self) -> bool { + **self == MUXPOS_A::AIN11 + } + #[doc = "Checks if the value of the field is `BANDGAP`"] + #[inline(always)] + pub fn is_bandgap(&self) -> bool { + **self == MUXPOS_A::BANDGAP + } + #[doc = "Checks if the value of the field is `SCALEDCOREVCC`"] + #[inline(always)] + pub fn is_scaledcorevcc(&self) -> bool { + **self == MUXPOS_A::SCALEDCOREVCC + } + #[doc = "Checks if the value of the field is `SCALEDIOVCC`"] + #[inline(always)] + pub fn is_scalediovcc(&self) -> bool { + **self == MUXPOS_A::SCALEDIOVCC + } +} +impl core::ops::Deref for MUXPOS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MUXPOS` writer - Positive Mux Input Selection"] +pub struct MUXPOS_W<'a> { + w: &'a mut W, +} +impl<'a> MUXPOS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MUXPOS_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "ADC AIN0 Pin"] + #[inline(always)] + pub fn ain0(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN0) + } + #[doc = "ADC AIN1 Pin"] + #[inline(always)] + pub fn ain1(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN1) + } + #[doc = "ADC AIN2 Pin"] + #[inline(always)] + pub fn ain2(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN2) + } + #[doc = "ADC AIN3 Pin"] + #[inline(always)] + pub fn ain3(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN3) + } + #[doc = "ADC AIN4 Pin"] + #[inline(always)] + pub fn ain4(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN4) + } + #[doc = "ADC AIN5 Pin"] + #[inline(always)] + pub fn ain5(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN5) + } + #[doc = "ADC AIN6 Pin"] + #[inline(always)] + pub fn ain6(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN6) + } + #[doc = "ADC AIN7 Pin"] + #[inline(always)] + pub fn ain7(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN7) + } + #[doc = "ADC AIN8 Pin"] + #[inline(always)] + pub fn ain8(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN8) + } + #[doc = "ADC AIN9 Pin"] + #[inline(always)] + pub fn ain9(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN9) + } + #[doc = "ADC AIN10 Pin"] + #[inline(always)] + pub fn ain10(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN10) + } + #[doc = "ADC AIN11 Pin"] + #[inline(always)] + pub fn ain11(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN11) + } + #[doc = "Bandgap Voltage"] + #[inline(always)] + pub fn bandgap(self) -> &'a mut W { + self.variant(MUXPOS_A::BANDGAP) + } + #[doc = "1/4 Scaled Core Supply"] + #[inline(always)] + pub fn scaledcorevcc(self) -> &'a mut W { + self.variant(MUXPOS_A::SCALEDCOREVCC) + } + #[doc = "1/4 Scaled I/O Supply"] + #[inline(always)] + pub fn scalediovcc(self) -> &'a mut W { + self.variant(MUXPOS_A::SCALEDIOVCC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u16 & 0x1f); + self.w + } +} +#[doc = "Negative Mux Input Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MUXNEG_A { + #[doc = "0: ADC AIN0 Pin"] + AIN0 = 0, + #[doc = "1: ADC AIN1 Pin"] + AIN1 = 1, + #[doc = "2: ADC AIN2 Pin"] + AIN2 = 2, + #[doc = "3: ADC AIN3 Pin"] + AIN3 = 3, + #[doc = "4: ADC AIN4 Pin"] + AIN4 = 4, + #[doc = "5: ADC AIN5 Pin"] + AIN5 = 5, + #[doc = "24: Internal Ground"] + GND = 24, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MUXNEG_A) -> Self { + variant as _ + } +} +#[doc = "Field `MUXNEG` reader - Negative Mux Input Selection"] +pub struct MUXNEG_R(crate::FieldReader); +impl MUXNEG_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MUXNEG_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MUXNEG_A::AIN0), + 1 => Some(MUXNEG_A::AIN1), + 2 => Some(MUXNEG_A::AIN2), + 3 => Some(MUXNEG_A::AIN3), + 4 => Some(MUXNEG_A::AIN4), + 5 => Some(MUXNEG_A::AIN5), + 24 => Some(MUXNEG_A::GND), + _ => None, + } + } + #[doc = "Checks if the value of the field is `AIN0`"] + #[inline(always)] + pub fn is_ain0(&self) -> bool { + **self == MUXNEG_A::AIN0 + } + #[doc = "Checks if the value of the field is `AIN1`"] + #[inline(always)] + pub fn is_ain1(&self) -> bool { + **self == MUXNEG_A::AIN1 + } + #[doc = "Checks if the value of the field is `AIN2`"] + #[inline(always)] + pub fn is_ain2(&self) -> bool { + **self == MUXNEG_A::AIN2 + } + #[doc = "Checks if the value of the field is `AIN3`"] + #[inline(always)] + pub fn is_ain3(&self) -> bool { + **self == MUXNEG_A::AIN3 + } + #[doc = "Checks if the value of the field is `AIN4`"] + #[inline(always)] + pub fn is_ain4(&self) -> bool { + **self == MUXNEG_A::AIN4 + } + #[doc = "Checks if the value of the field is `AIN5`"] + #[inline(always)] + pub fn is_ain5(&self) -> bool { + **self == MUXNEG_A::AIN5 + } + #[doc = "Checks if the value of the field is `GND`"] + #[inline(always)] + pub fn is_gnd(&self) -> bool { + **self == MUXNEG_A::GND + } +} +impl core::ops::Deref for MUXNEG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MUXNEG` writer - Negative Mux Input Selection"] +pub struct MUXNEG_W<'a> { + w: &'a mut W, +} +impl<'a> MUXNEG_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MUXNEG_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "ADC AIN0 Pin"] + #[inline(always)] + pub fn ain0(self) -> &'a mut W { + self.variant(MUXNEG_A::AIN0) + } + #[doc = "ADC AIN1 Pin"] + #[inline(always)] + pub fn ain1(self) -> &'a mut W { + self.variant(MUXNEG_A::AIN1) + } + #[doc = "ADC AIN2 Pin"] + #[inline(always)] + pub fn ain2(self) -> &'a mut W { + self.variant(MUXNEG_A::AIN2) + } + #[doc = "ADC AIN3 Pin"] + #[inline(always)] + pub fn ain3(self) -> &'a mut W { + self.variant(MUXNEG_A::AIN3) + } + #[doc = "ADC AIN4 Pin"] + #[inline(always)] + pub fn ain4(self) -> &'a mut W { + self.variant(MUXNEG_A::AIN4) + } + #[doc = "ADC AIN5 Pin"] + #[inline(always)] + pub fn ain5(self) -> &'a mut W { + self.variant(MUXNEG_A::AIN5) + } + #[doc = "Internal Ground"] + #[inline(always)] + pub fn gnd(self) -> &'a mut W { + self.variant(MUXNEG_A::GND) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 8)) | ((value as u16 & 0x1f) << 8); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Positive Mux Input Selection"] + #[inline(always)] + pub fn muxpos(&self) -> MUXPOS_R { + MUXPOS_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 8:12 - Negative Mux Input Selection"] + #[inline(always)] + pub fn muxneg(&self) -> MUXNEG_R { + MUXNEG_R::new(((self.bits >> 8) & 0x1f) as u8) + } +} +impl W { + #[doc = "Bits 0:4 - Positive Mux Input Selection"] + #[inline(always)] + pub fn muxpos(&mut self) -> MUXPOS_W { + MUXPOS_W { w: self } + } + #[doc = "Bits 8:12 - Negative Mux Input Selection"] + #[inline(always)] + pub fn muxneg(&mut self) -> MUXNEG_W { + MUXNEG_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Input Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [inputctrl](index.html) module"] +pub struct INPUTCTRL_SPEC; +impl crate::RegisterSpec for INPUTCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [inputctrl::R](R) reader structure"] +impl crate::Readable for INPUTCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [inputctrl::W](W) writer structure"] +impl crate::Writable for INPUTCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INPUTCTRL to value 0"] +impl crate::Resettable for INPUTCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/adc0/intenclr.rs b/pac/atsamc20g/src/adc0/intenclr.rs new file mode 100644 index 000000000000..b10f428d30b1 --- /dev/null +++ b/pac/atsamc20g/src/adc0/intenclr.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RESRDY` reader - Result Ready Interrupt Disable"] +pub struct RESRDY_R(crate::FieldReader); +impl RESRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESRDY` writer - Result Ready Interrupt Disable"] +pub struct RESRDY_W<'a> { + w: &'a mut W, +} +impl<'a> RESRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `OVERRUN` reader - Overrun Interrupt Disable"] +pub struct OVERRUN_R(crate::FieldReader); +impl OVERRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVERRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVERRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVERRUN` writer - Overrun Interrupt Disable"] +pub struct OVERRUN_W<'a> { + w: &'a mut W, +} +impl<'a> OVERRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WINMON` reader - Window Monitor Interrupt Disable"] +pub struct WINMON_R(crate::FieldReader); +impl WINMON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINMON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINMON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMON` writer - Window Monitor Interrupt Disable"] +pub struct WINMON_W<'a> { + w: &'a mut W, +} +impl<'a> WINMON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Result Ready Interrupt Disable"] + #[inline(always)] + pub fn resrdy(&self) -> RESRDY_R { + RESRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Overrun Interrupt Disable"] + #[inline(always)] + pub fn overrun(&self) -> OVERRUN_R { + OVERRUN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Window Monitor Interrupt Disable"] + #[inline(always)] + pub fn winmon(&self) -> WINMON_R { + WINMON_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Result Ready Interrupt Disable"] + #[inline(always)] + pub fn resrdy(&mut self) -> RESRDY_W { + RESRDY_W { w: self } + } + #[doc = "Bit 1 - Overrun Interrupt Disable"] + #[inline(always)] + pub fn overrun(&mut self) -> OVERRUN_W { + OVERRUN_W { w: self } + } + #[doc = "Bit 2 - Window Monitor Interrupt Disable"] + #[inline(always)] + pub fn winmon(&mut self) -> WINMON_W { + WINMON_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/adc0/intenset.rs b/pac/atsamc20g/src/adc0/intenset.rs new file mode 100644 index 000000000000..5ca93b05b859 --- /dev/null +++ b/pac/atsamc20g/src/adc0/intenset.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RESRDY` reader - Result Ready Interrupt Enable"] +pub struct RESRDY_R(crate::FieldReader); +impl RESRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESRDY` writer - Result Ready Interrupt Enable"] +pub struct RESRDY_W<'a> { + w: &'a mut W, +} +impl<'a> RESRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `OVERRUN` reader - Overrun Interrupt Enable"] +pub struct OVERRUN_R(crate::FieldReader); +impl OVERRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVERRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVERRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVERRUN` writer - Overrun Interrupt Enable"] +pub struct OVERRUN_W<'a> { + w: &'a mut W, +} +impl<'a> OVERRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WINMON` reader - Window Monitor Interrupt Enable"] +pub struct WINMON_R(crate::FieldReader); +impl WINMON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINMON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINMON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMON` writer - Window Monitor Interrupt Enable"] +pub struct WINMON_W<'a> { + w: &'a mut W, +} +impl<'a> WINMON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Result Ready Interrupt Enable"] + #[inline(always)] + pub fn resrdy(&self) -> RESRDY_R { + RESRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Overrun Interrupt Enable"] + #[inline(always)] + pub fn overrun(&self) -> OVERRUN_R { + OVERRUN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Window Monitor Interrupt Enable"] + #[inline(always)] + pub fn winmon(&self) -> WINMON_R { + WINMON_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Result Ready Interrupt Enable"] + #[inline(always)] + pub fn resrdy(&mut self) -> RESRDY_W { + RESRDY_W { w: self } + } + #[doc = "Bit 1 - Overrun Interrupt Enable"] + #[inline(always)] + pub fn overrun(&mut self) -> OVERRUN_W { + OVERRUN_W { w: self } + } + #[doc = "Bit 2 - Window Monitor Interrupt Enable"] + #[inline(always)] + pub fn winmon(&mut self) -> WINMON_W { + WINMON_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/adc0/intflag.rs b/pac/atsamc20g/src/adc0/intflag.rs new file mode 100644 index 000000000000..3cd74788b226 --- /dev/null +++ b/pac/atsamc20g/src/adc0/intflag.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RESRDY` reader - Result Ready Interrupt Flag"] +pub struct RESRDY_R(crate::FieldReader); +impl RESRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESRDY` writer - Result Ready Interrupt Flag"] +pub struct RESRDY_W<'a> { + w: &'a mut W, +} +impl<'a> RESRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `OVERRUN` reader - Overrun Interrupt Flag"] +pub struct OVERRUN_R(crate::FieldReader); +impl OVERRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVERRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVERRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVERRUN` writer - Overrun Interrupt Flag"] +pub struct OVERRUN_W<'a> { + w: &'a mut W, +} +impl<'a> OVERRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WINMON` reader - Window Monitor Interrupt Flag"] +pub struct WINMON_R(crate::FieldReader); +impl WINMON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINMON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINMON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMON` writer - Window Monitor Interrupt Flag"] +pub struct WINMON_W<'a> { + w: &'a mut W, +} +impl<'a> WINMON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Result Ready Interrupt Flag"] + #[inline(always)] + pub fn resrdy(&self) -> RESRDY_R { + RESRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Overrun Interrupt Flag"] + #[inline(always)] + pub fn overrun(&self) -> OVERRUN_R { + OVERRUN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Window Monitor Interrupt Flag"] + #[inline(always)] + pub fn winmon(&self) -> WINMON_R { + WINMON_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Result Ready Interrupt Flag"] + #[inline(always)] + pub fn resrdy(&mut self) -> RESRDY_W { + RESRDY_W { w: self } + } + #[doc = "Bit 1 - Overrun Interrupt Flag"] + #[inline(always)] + pub fn overrun(&mut self) -> OVERRUN_W { + OVERRUN_W { w: self } + } + #[doc = "Bit 2 - Window Monitor Interrupt Flag"] + #[inline(always)] + pub fn winmon(&mut self) -> WINMON_W { + WINMON_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/adc0/offsetcorr.rs b/pac/atsamc20g/src/adc0/offsetcorr.rs new file mode 100644 index 000000000000..24a97427c64e --- /dev/null +++ b/pac/atsamc20g/src/adc0/offsetcorr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `OFFSETCORR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OFFSETCORR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OFFSETCORR` reader - Offset Correction Value"] +pub struct OFFSETCORR_R(crate::FieldReader); +impl OFFSETCORR_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + OFFSETCORR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OFFSETCORR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OFFSETCORR` writer - Offset Correction Value"] +pub struct OFFSETCORR_W<'a> { + w: &'a mut W, +} +impl<'a> OFFSETCORR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0fff) | (value as u16 & 0x0fff); + self.w + } +} +impl R { + #[doc = "Bits 0:11 - Offset Correction Value"] + #[inline(always)] + pub fn offsetcorr(&self) -> OFFSETCORR_R { + OFFSETCORR_R::new((self.bits & 0x0fff) as u16) + } +} +impl W { + #[doc = "Bits 0:11 - Offset Correction Value"] + #[inline(always)] + pub fn offsetcorr(&mut self) -> OFFSETCORR_W { + OFFSETCORR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Offset Correction\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [offsetcorr](index.html) module"] +pub struct OFFSETCORR_SPEC; +impl crate::RegisterSpec for OFFSETCORR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [offsetcorr::R](R) reader structure"] +impl crate::Readable for OFFSETCORR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [offsetcorr::W](W) writer structure"] +impl crate::Writable for OFFSETCORR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OFFSETCORR to value 0"] +impl crate::Resettable for OFFSETCORR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/adc0/refctrl.rs b/pac/atsamc20g/src/adc0/refctrl.rs new file mode 100644 index 000000000000..c21b6532936f --- /dev/null +++ b/pac/atsamc20g/src/adc0/refctrl.rs @@ -0,0 +1,238 @@ +#[doc = "Register `REFCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `REFCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Reference Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum REFSEL_A { + #[doc = "0: Internal Bandgap Reference"] + INTREF = 0, + #[doc = "1: 1/1.6 VDDANA"] + INTVCC0 = 1, + #[doc = "2: 1/2 VDDANA"] + INTVCC1 = 2, + #[doc = "3: External Reference"] + AREFA = 3, + #[doc = "5: VDDANA"] + INTVCC2 = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: REFSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `REFSEL` reader - Reference Selection"] +pub struct REFSEL_R(crate::FieldReader); +impl REFSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REFSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(REFSEL_A::INTREF), + 1 => Some(REFSEL_A::INTVCC0), + 2 => Some(REFSEL_A::INTVCC1), + 3 => Some(REFSEL_A::AREFA), + 5 => Some(REFSEL_A::INTVCC2), + _ => None, + } + } + #[doc = "Checks if the value of the field is `INTREF`"] + #[inline(always)] + pub fn is_intref(&self) -> bool { + **self == REFSEL_A::INTREF + } + #[doc = "Checks if the value of the field is `INTVCC0`"] + #[inline(always)] + pub fn is_intvcc0(&self) -> bool { + **self == REFSEL_A::INTVCC0 + } + #[doc = "Checks if the value of the field is `INTVCC1`"] + #[inline(always)] + pub fn is_intvcc1(&self) -> bool { + **self == REFSEL_A::INTVCC1 + } + #[doc = "Checks if the value of the field is `AREFA`"] + #[inline(always)] + pub fn is_arefa(&self) -> bool { + **self == REFSEL_A::AREFA + } + #[doc = "Checks if the value of the field is `INTVCC2`"] + #[inline(always)] + pub fn is_intvcc2(&self) -> bool { + **self == REFSEL_A::INTVCC2 + } +} +impl core::ops::Deref for REFSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REFSEL` writer - Reference Selection"] +pub struct REFSEL_W<'a> { + w: &'a mut W, +} +impl<'a> REFSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: REFSEL_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Internal Bandgap Reference"] + #[inline(always)] + pub fn intref(self) -> &'a mut W { + self.variant(REFSEL_A::INTREF) + } + #[doc = "1/1.6 VDDANA"] + #[inline(always)] + pub fn intvcc0(self) -> &'a mut W { + self.variant(REFSEL_A::INTVCC0) + } + #[doc = "1/2 VDDANA"] + #[inline(always)] + pub fn intvcc1(self) -> &'a mut W { + self.variant(REFSEL_A::INTVCC1) + } + #[doc = "External Reference"] + #[inline(always)] + pub fn arefa(self) -> &'a mut W { + self.variant(REFSEL_A::AREFA) + } + #[doc = "VDDANA"] + #[inline(always)] + pub fn intvcc2(self) -> &'a mut W { + self.variant(REFSEL_A::INTVCC2) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +#[doc = "Field `REFCOMP` reader - Reference Buffer Offset Compensation Enable"] +pub struct REFCOMP_R(crate::FieldReader); +impl REFCOMP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + REFCOMP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REFCOMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REFCOMP` writer - Reference Buffer Offset Compensation Enable"] +pub struct REFCOMP_W<'a> { + w: &'a mut W, +} +impl<'a> REFCOMP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Reference Selection"] + #[inline(always)] + pub fn refsel(&self) -> REFSEL_R { + REFSEL_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 7 - Reference Buffer Offset Compensation Enable"] + #[inline(always)] + pub fn refcomp(&self) -> REFCOMP_R { + REFCOMP_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Reference Selection"] + #[inline(always)] + pub fn refsel(&mut self) -> REFSEL_W { + REFSEL_W { w: self } + } + #[doc = "Bit 7 - Reference Buffer Offset Compensation Enable"] + #[inline(always)] + pub fn refcomp(&mut self) -> REFCOMP_W { + REFCOMP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Reference Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [refctrl](index.html) module"] +pub struct REFCTRL_SPEC; +impl crate::RegisterSpec for REFCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [refctrl::R](R) reader structure"] +impl crate::Readable for REFCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [refctrl::W](W) writer structure"] +impl crate::Writable for REFCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets REFCTRL to value 0"] +impl crate::Resettable for REFCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/adc0/result.rs b/pac/atsamc20g/src/adc0/result.rs new file mode 100644 index 000000000000..b63b08cc72b9 --- /dev/null +++ b/pac/atsamc20g/src/adc0/result.rs @@ -0,0 +1,53 @@ +#[doc = "Register `RESULT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `RESULT` reader - Result Value"] +pub struct RESULT_R(crate::FieldReader); +impl RESULT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + RESULT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESULT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:15 - Result Value"] + #[inline(always)] + pub fn result(&self) -> RESULT_R { + RESULT_R::new(self.bits as u16) + } +} +#[doc = "Result\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [result](index.html) module"] +pub struct RESULT_SPEC; +impl crate::RegisterSpec for RESULT_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [result::R](R) reader structure"] +impl crate::Readable for RESULT_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets RESULT to value 0"] +impl crate::Resettable for RESULT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/adc0/sampctrl.rs b/pac/atsamc20g/src/adc0/sampctrl.rs new file mode 100644 index 000000000000..be4b77a80410 --- /dev/null +++ b/pac/atsamc20g/src/adc0/sampctrl.rs @@ -0,0 +1,150 @@ +#[doc = "Register `SAMPCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SAMPCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SAMPLEN` reader - Sampling Time Length"] +pub struct SAMPLEN_R(crate::FieldReader); +impl SAMPLEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SAMPLEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SAMPLEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SAMPLEN` writer - Sampling Time Length"] +pub struct SAMPLEN_W<'a> { + w: &'a mut W, +} +impl<'a> SAMPLEN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u8 & 0x3f); + self.w + } +} +#[doc = "Field `OFFCOMP` reader - Comparator Offset Compensation Enable"] +pub struct OFFCOMP_R(crate::FieldReader); +impl OFFCOMP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OFFCOMP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OFFCOMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OFFCOMP` writer - Comparator Offset Compensation Enable"] +pub struct OFFCOMP_W<'a> { + w: &'a mut W, +} +impl<'a> OFFCOMP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Sampling Time Length"] + #[inline(always)] + pub fn samplen(&self) -> SAMPLEN_R { + SAMPLEN_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 7 - Comparator Offset Compensation Enable"] + #[inline(always)] + pub fn offcomp(&self) -> OFFCOMP_R { + OFFCOMP_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:5 - Sampling Time Length"] + #[inline(always)] + pub fn samplen(&mut self) -> SAMPLEN_W { + SAMPLEN_W { w: self } + } + #[doc = "Bit 7 - Comparator Offset Compensation Enable"] + #[inline(always)] + pub fn offcomp(&mut self) -> OFFCOMP_W { + OFFCOMP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Sample Time Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sampctrl](index.html) module"] +pub struct SAMPCTRL_SPEC; +impl crate::RegisterSpec for SAMPCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [sampctrl::R](R) reader structure"] +impl crate::Readable for SAMPCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [sampctrl::W](W) writer structure"] +impl crate::Writable for SAMPCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SAMPCTRL to value 0"] +impl crate::Resettable for SAMPCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/adc0/seqctrl.rs b/pac/atsamc20g/src/adc0/seqctrl.rs new file mode 100644 index 000000000000..c8388c9a393f --- /dev/null +++ b/pac/atsamc20g/src/adc0/seqctrl.rs @@ -0,0 +1,103 @@ +#[doc = "Register `SEQCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SEQCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SEQEN` reader - Enable Positive Input in the Sequence"] +pub struct SEQEN_R(crate::FieldReader); +impl SEQEN_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + SEQEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEQEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEQEN` writer - Enable Positive Input in the Sequence"] +pub struct SEQEN_W<'a> { + w: &'a mut W, +} +impl<'a> SEQEN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Enable Positive Input in the Sequence"] + #[inline(always)] + pub fn seqen(&self) -> SEQEN_R { + SEQEN_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Enable Positive Input in the Sequence"] + #[inline(always)] + pub fn seqen(&mut self) -> SEQEN_W { + SEQEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Sequence Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [seqctrl](index.html) module"] +pub struct SEQCTRL_SPEC; +impl crate::RegisterSpec for SEQCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [seqctrl::R](R) reader structure"] +impl crate::Readable for SEQCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [seqctrl::W](W) writer structure"] +impl crate::Writable for SEQCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SEQCTRL to value 0"] +impl crate::Resettable for SEQCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/adc0/seqstatus.rs b/pac/atsamc20g/src/adc0/seqstatus.rs new file mode 100644 index 000000000000..42c820892e9a --- /dev/null +++ b/pac/atsamc20g/src/adc0/seqstatus.rs @@ -0,0 +1,73 @@ +#[doc = "Register `SEQSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SEQSTATE` reader - Sequence State"] +pub struct SEQSTATE_R(crate::FieldReader); +impl SEQSTATE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SEQSTATE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEQSTATE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEQBUSY` reader - Sequence Busy"] +pub struct SEQBUSY_R(crate::FieldReader); +impl SEQBUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SEQBUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEQBUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:4 - Sequence State"] + #[inline(always)] + pub fn seqstate(&self) -> SEQSTATE_R { + SEQSTATE_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bit 7 - Sequence Busy"] + #[inline(always)] + pub fn seqbusy(&self) -> SEQBUSY_R { + SEQBUSY_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +#[doc = "Sequence Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [seqstatus](index.html) module"] +pub struct SEQSTATUS_SPEC; +impl crate::RegisterSpec for SEQSTATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [seqstatus::R](R) reader structure"] +impl crate::Readable for SEQSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SEQSTATUS to value 0"] +impl crate::Resettable for SEQSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/adc0/swtrig.rs b/pac/atsamc20g/src/adc0/swtrig.rs new file mode 100644 index 000000000000..5e23ed7865ed --- /dev/null +++ b/pac/atsamc20g/src/adc0/swtrig.rs @@ -0,0 +1,160 @@ +#[doc = "Register `SWTRIG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SWTRIG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FLUSH` reader - ADC Flush"] +pub struct FLUSH_R(crate::FieldReader); +impl FLUSH_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FLUSH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FLUSH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLUSH` writer - ADC Flush"] +pub struct FLUSH_W<'a> { + w: &'a mut W, +} +impl<'a> FLUSH_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `START` reader - Start ADC Conversion"] +pub struct START_R(crate::FieldReader); +impl START_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + START_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for START_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `START` writer - Start ADC Conversion"] +pub struct START_W<'a> { + w: &'a mut W, +} +impl<'a> START_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - ADC Flush"] + #[inline(always)] + pub fn flush(&self) -> FLUSH_R { + FLUSH_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Start ADC Conversion"] + #[inline(always)] + pub fn start(&self) -> START_R { + START_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - ADC Flush"] + #[inline(always)] + pub fn flush(&mut self) -> FLUSH_W { + FLUSH_W { w: self } + } + #[doc = "Bit 1 - Start ADC Conversion"] + #[inline(always)] + pub fn start(&mut self) -> START_W { + START_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Software Trigger\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [swtrig](index.html) module"] +pub struct SWTRIG_SPEC; +impl crate::RegisterSpec for SWTRIG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [swtrig::R](R) reader structure"] +impl crate::Readable for SWTRIG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [swtrig::W](W) writer structure"] +impl crate::Writable for SWTRIG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SWTRIG to value 0"] +impl crate::Resettable for SWTRIG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/adc0/syncbusy.rs b/pac/atsamc20g/src/adc0/syncbusy.rs new file mode 100644 index 000000000000..9c92da8a7c74 --- /dev/null +++ b/pac/atsamc20g/src/adc0/syncbusy.rs @@ -0,0 +1,253 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - SWRST Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - ENABLE Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INPUTCTRL` reader - INPUTCTRL Synchronization Busy"] +pub struct INPUTCTRL_R(crate::FieldReader); +impl INPUTCTRL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INPUTCTRL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INPUTCTRL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLC` reader - CTRLC Synchronization Busy"] +pub struct CTRLC_R(crate::FieldReader); +impl CTRLC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AVGCTRL` reader - AVGCTRL Synchronization Busy"] +pub struct AVGCTRL_R(crate::FieldReader); +impl AVGCTRL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AVGCTRL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AVGCTRL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SAMPCTRL` reader - SAMPCTRL Synchronization Busy"] +pub struct SAMPCTRL_R(crate::FieldReader); +impl SAMPCTRL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SAMPCTRL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SAMPCTRL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINLT` reader - WINLT Synchronization Busy"] +pub struct WINLT_R(crate::FieldReader); +impl WINLT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINLT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINLT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINUT` reader - WINUT Synchronization Busy"] +pub struct WINUT_R(crate::FieldReader); +impl WINUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GAINCORR` reader - GAINCORR Synchronization Busy"] +pub struct GAINCORR_R(crate::FieldReader); +impl GAINCORR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GAINCORR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GAINCORR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OFFSETCORR` reader - OFFSETCTRL Synchronization Busy"] +pub struct OFFSETCORR_R(crate::FieldReader); +impl OFFSETCORR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OFFSETCORR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OFFSETCORR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG` reader - SWTRG Synchronization Busy"] +pub struct SWTRIG_R(crate::FieldReader); +impl SWTRIG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - SWRST Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ENABLE Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - INPUTCTRL Synchronization Busy"] + #[inline(always)] + pub fn inputctrl(&self) -> INPUTCTRL_R { + INPUTCTRL_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - CTRLC Synchronization Busy"] + #[inline(always)] + pub fn ctrlc(&self) -> CTRLC_R { + CTRLC_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - AVGCTRL Synchronization Busy"] + #[inline(always)] + pub fn avgctrl(&self) -> AVGCTRL_R { + AVGCTRL_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - SAMPCTRL Synchronization Busy"] + #[inline(always)] + pub fn sampctrl(&self) -> SAMPCTRL_R { + SAMPCTRL_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - WINLT Synchronization Busy"] + #[inline(always)] + pub fn winlt(&self) -> WINLT_R { + WINLT_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - WINUT Synchronization Busy"] + #[inline(always)] + pub fn winut(&self) -> WINUT_R { + WINUT_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - GAINCORR Synchronization Busy"] + #[inline(always)] + pub fn gaincorr(&self) -> GAINCORR_R { + GAINCORR_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - OFFSETCTRL Synchronization Busy"] + #[inline(always)] + pub fn offsetcorr(&self) -> OFFSETCORR_R { + OFFSETCORR_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - SWTRG Synchronization Busy"] + #[inline(always)] + pub fn swtrig(&self) -> SWTRIG_R { + SWTRIG_R::new(((self.bits >> 10) & 0x01) != 0) + } +} +#[doc = "Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/adc0/winlt.rs b/pac/atsamc20g/src/adc0/winlt.rs new file mode 100644 index 000000000000..2a3397684767 --- /dev/null +++ b/pac/atsamc20g/src/adc0/winlt.rs @@ -0,0 +1,103 @@ +#[doc = "Register `WINLT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WINLT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WINLT` reader - Window Lower Threshold"] +pub struct WINLT_R(crate::FieldReader); +impl WINLT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + WINLT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINLT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINLT` writer - Window Lower Threshold"] +pub struct WINLT_W<'a> { + w: &'a mut W, +} +impl<'a> WINLT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Window Lower Threshold"] + #[inline(always)] + pub fn winlt(&self) -> WINLT_R { + WINLT_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Window Lower Threshold"] + #[inline(always)] + pub fn winlt(&mut self) -> WINLT_W { + WINLT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Window Monitor Lower Threshold\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [winlt](index.html) module"] +pub struct WINLT_SPEC; +impl crate::RegisterSpec for WINLT_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [winlt::R](R) reader structure"] +impl crate::Readable for WINLT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [winlt::W](W) writer structure"] +impl crate::Writable for WINLT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WINLT to value 0"] +impl crate::Resettable for WINLT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/adc0/winut.rs b/pac/atsamc20g/src/adc0/winut.rs new file mode 100644 index 000000000000..0ea123174937 --- /dev/null +++ b/pac/atsamc20g/src/adc0/winut.rs @@ -0,0 +1,103 @@ +#[doc = "Register `WINUT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WINUT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WINUT` reader - Window Upper Threshold"] +pub struct WINUT_R(crate::FieldReader); +impl WINUT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + WINUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINUT` writer - Window Upper Threshold"] +pub struct WINUT_W<'a> { + w: &'a mut W, +} +impl<'a> WINUT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Window Upper Threshold"] + #[inline(always)] + pub fn winut(&self) -> WINUT_R { + WINUT_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Window Upper Threshold"] + #[inline(always)] + pub fn winut(&mut self) -> WINUT_W { + WINUT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Window Monitor Upper Threshold\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [winut](index.html) module"] +pub struct WINUT_SPEC; +impl crate::RegisterSpec for WINUT_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [winut::R](R) reader structure"] +impl crate::Readable for WINUT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [winut::W](W) writer structure"] +impl crate::Writable for WINUT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WINUT to value 0"] +impl crate::Resettable for WINUT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/ccl.rs b/pac/atsamc20g/src/ccl.rs new file mode 100644 index 000000000000..30b1f41639c1 --- /dev/null +++ b/pac/atsamc20g/src/ccl.rs @@ -0,0 +1,24 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrl: crate::Reg, + _reserved1: [u8; 0x03], + #[doc = "0x04 - SEQ Control x"] + pub seqctrl: [crate::Reg; 2], + _reserved2: [u8; 0x02], + #[doc = "0x08..0x18 - LUT Control x"] + pub lutctrl: [crate::Reg; 4], +} +#[doc = "CTRL register accessor: an alias for `Reg`"] +pub type CTRL = crate::Reg; +#[doc = "Control"] +pub mod ctrl; +#[doc = "SEQCTRL register accessor: an alias for `Reg`"] +pub type SEQCTRL = crate::Reg; +#[doc = "SEQ Control x"] +pub mod seqctrl; +#[doc = "LUTCTRL register accessor: an alias for `Reg`"] +pub type LUTCTRL = crate::Reg; +#[doc = "LUT Control x"] +pub mod lutctrl; diff --git a/pac/atsamc20g/src/ccl/ctrl.rs b/pac/atsamc20g/src/ccl/ctrl.rs new file mode 100644 index 000000000000..5e515fe037ca --- /dev/null +++ b/pac/atsamc20g/src/ccl/ctrl.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"] +pub struct CTRL_SPEC; +impl crate::RegisterSpec for CTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrl::R](R) reader structure"] +impl crate::Readable for CTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"] +impl crate::Writable for CTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/ccl/lutctrl.rs b/pac/atsamc20g/src/ccl/lutctrl.rs new file mode 100644 index 000000000000..530ed34f7c81 --- /dev/null +++ b/pac/atsamc20g/src/ccl/lutctrl.rs @@ -0,0 +1,702 @@ +#[doc = "Register `LUTCTRL[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `LUTCTRL[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - LUT Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - LUT Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Filter Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FILTSEL_A { + #[doc = "0: Filter disabled"] + DISABLE = 0, + #[doc = "1: Synchronizer enabled"] + SYNCH = 1, + #[doc = "2: Filter enabled"] + FILTER = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FILTSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `FILTSEL` reader - Filter Selection"] +pub struct FILTSEL_R(crate::FieldReader); +impl FILTSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FILTSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(FILTSEL_A::DISABLE), + 1 => Some(FILTSEL_A::SYNCH), + 2 => Some(FILTSEL_A::FILTER), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == FILTSEL_A::DISABLE + } + #[doc = "Checks if the value of the field is `SYNCH`"] + #[inline(always)] + pub fn is_synch(&self) -> bool { + **self == FILTSEL_A::SYNCH + } + #[doc = "Checks if the value of the field is `FILTER`"] + #[inline(always)] + pub fn is_filter(&self) -> bool { + **self == FILTSEL_A::FILTER + } +} +impl core::ops::Deref for FILTSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTSEL` writer - Filter Selection"] +pub struct FILTSEL_W<'a> { + w: &'a mut W, +} +impl<'a> FILTSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FILTSEL_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Filter disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(FILTSEL_A::DISABLE) + } + #[doc = "Synchronizer enabled"] + #[inline(always)] + pub fn synch(self) -> &'a mut W { + self.variant(FILTSEL_A::SYNCH) + } + #[doc = "Filter enabled"] + #[inline(always)] + pub fn filter(self) -> &'a mut W { + self.variant(FILTSEL_A::FILTER) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u32 & 0x03) << 4); + self.w + } +} +#[doc = "Field `EDGESEL` reader - Edge Selection"] +pub struct EDGESEL_R(crate::FieldReader); +impl EDGESEL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EDGESEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EDGESEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EDGESEL` writer - Edge Selection"] +pub struct EDGESEL_W<'a> { + w: &'a mut W, +} +impl<'a> EDGESEL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Input Selection 0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum INSEL0_A { + #[doc = "0: Masked input"] + MASK = 0, + #[doc = "1: Feedback input source"] + FEEDBACK = 1, + #[doc = "2: Linked LUT input source"] + LINK = 2, + #[doc = "3: Event in put source"] + EVENT = 3, + #[doc = "4: I/O pin input source"] + IO = 4, + #[doc = "5: AC input source"] + AC = 5, + #[doc = "6: TC input source"] + TC = 6, + #[doc = "7: Alternate TC input source"] + ALTTC = 7, + #[doc = "8: TCC input source"] + TCC = 8, + #[doc = "9: SERCOM inout source"] + SERCOM = 9, +} +impl From for u8 { + #[inline(always)] + fn from(variant: INSEL0_A) -> Self { + variant as _ + } +} +#[doc = "Field `INSEL0` reader - Input Selection 0"] +pub struct INSEL0_R(crate::FieldReader); +impl INSEL0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + INSEL0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(INSEL0_A::MASK), + 1 => Some(INSEL0_A::FEEDBACK), + 2 => Some(INSEL0_A::LINK), + 3 => Some(INSEL0_A::EVENT), + 4 => Some(INSEL0_A::IO), + 5 => Some(INSEL0_A::AC), + 6 => Some(INSEL0_A::TC), + 7 => Some(INSEL0_A::ALTTC), + 8 => Some(INSEL0_A::TCC), + 9 => Some(INSEL0_A::SERCOM), + _ => None, + } + } + #[doc = "Checks if the value of the field is `MASK`"] + #[inline(always)] + pub fn is_mask(&self) -> bool { + **self == INSEL0_A::MASK + } + #[doc = "Checks if the value of the field is `FEEDBACK`"] + #[inline(always)] + pub fn is_feedback(&self) -> bool { + **self == INSEL0_A::FEEDBACK + } + #[doc = "Checks if the value of the field is `LINK`"] + #[inline(always)] + pub fn is_link(&self) -> bool { + **self == INSEL0_A::LINK + } + #[doc = "Checks if the value of the field is `EVENT`"] + #[inline(always)] + pub fn is_event(&self) -> bool { + **self == INSEL0_A::EVENT + } + #[doc = "Checks if the value of the field is `IO`"] + #[inline(always)] + pub fn is_io(&self) -> bool { + **self == INSEL0_A::IO + } + #[doc = "Checks if the value of the field is `AC`"] + #[inline(always)] + pub fn is_ac(&self) -> bool { + **self == INSEL0_A::AC + } + #[doc = "Checks if the value of the field is `TC`"] + #[inline(always)] + pub fn is_tc(&self) -> bool { + **self == INSEL0_A::TC + } + #[doc = "Checks if the value of the field is `ALTTC`"] + #[inline(always)] + pub fn is_alttc(&self) -> bool { + **self == INSEL0_A::ALTTC + } + #[doc = "Checks if the value of the field is `TCC`"] + #[inline(always)] + pub fn is_tcc(&self) -> bool { + **self == INSEL0_A::TCC + } + #[doc = "Checks if the value of the field is `SERCOM`"] + #[inline(always)] + pub fn is_sercom(&self) -> bool { + **self == INSEL0_A::SERCOM + } +} +impl core::ops::Deref for INSEL0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INSEL0` writer - Input Selection 0"] +pub struct INSEL0_W<'a> { + w: &'a mut W, +} +impl<'a> INSEL0_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: INSEL0_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Masked input"] + #[inline(always)] + pub fn mask(self) -> &'a mut W { + self.variant(INSEL0_A::MASK) + } + #[doc = "Feedback input source"] + #[inline(always)] + pub fn feedback(self) -> &'a mut W { + self.variant(INSEL0_A::FEEDBACK) + } + #[doc = "Linked LUT input source"] + #[inline(always)] + pub fn link(self) -> &'a mut W { + self.variant(INSEL0_A::LINK) + } + #[doc = "Event in put source"] + #[inline(always)] + pub fn event(self) -> &'a mut W { + self.variant(INSEL0_A::EVENT) + } + #[doc = "I/O pin input source"] + #[inline(always)] + pub fn io(self) -> &'a mut W { + self.variant(INSEL0_A::IO) + } + #[doc = "AC input source"] + #[inline(always)] + pub fn ac(self) -> &'a mut W { + self.variant(INSEL0_A::AC) + } + #[doc = "TC input source"] + #[inline(always)] + pub fn tc(self) -> &'a mut W { + self.variant(INSEL0_A::TC) + } + #[doc = "Alternate TC input source"] + #[inline(always)] + pub fn alttc(self) -> &'a mut W { + self.variant(INSEL0_A::ALTTC) + } + #[doc = "TCC input source"] + #[inline(always)] + pub fn tcc(self) -> &'a mut W { + self.variant(INSEL0_A::TCC) + } + #[doc = "SERCOM inout source"] + #[inline(always)] + pub fn sercom(self) -> &'a mut W { + self.variant(INSEL0_A::SERCOM) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 8)) | ((value as u32 & 0x0f) << 8); + self.w + } +} +#[doc = "Field `INSEL1` reader - Input Selection 1"] +pub struct INSEL1_R(crate::FieldReader); +impl INSEL1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + INSEL1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INSEL1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INSEL1` writer - Input Selection 1"] +pub struct INSEL1_W<'a> { + w: &'a mut W, +} +impl<'a> INSEL1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 12)) | ((value as u32 & 0x0f) << 12); + self.w + } +} +#[doc = "Field `INSEL2` reader - Input Selection 2"] +pub struct INSEL2_R(crate::FieldReader); +impl INSEL2_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + INSEL2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INSEL2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INSEL2` writer - Input Selection 2"] +pub struct INSEL2_W<'a> { + w: &'a mut W, +} +impl<'a> INSEL2_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 16)) | ((value as u32 & 0x0f) << 16); + self.w + } +} +#[doc = "Field `INVEI` reader - Input Event Invert"] +pub struct INVEI_R(crate::FieldReader); +impl INVEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEI` writer - Input Event Invert"] +pub struct INVEI_W<'a> { + w: &'a mut W, +} +impl<'a> INVEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `LUTEI` reader - Event Input Enable"] +pub struct LUTEI_R(crate::FieldReader); +impl LUTEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LUTEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LUTEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LUTEI` writer - Event Input Enable"] +pub struct LUTEI_W<'a> { + w: &'a mut W, +} +impl<'a> LUTEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `LUTEO` reader - Event Output Enable"] +pub struct LUTEO_R(crate::FieldReader); +impl LUTEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LUTEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LUTEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LUTEO` writer - Event Output Enable"] +pub struct LUTEO_W<'a> { + w: &'a mut W, +} +impl<'a> LUTEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `TRUTH` reader - Truth Value"] +pub struct TRUTH_R(crate::FieldReader); +impl TRUTH_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TRUTH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRUTH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRUTH` writer - Truth Value"] +pub struct TRUTH_W<'a> { + w: &'a mut W, +} +impl<'a> TRUTH_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 24)) | ((value as u32 & 0xff) << 24); + self.w + } +} +impl R { + #[doc = "Bit 1 - LUT Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 4:5 - Filter Selection"] + #[inline(always)] + pub fn filtsel(&self) -> FILTSEL_R { + FILTSEL_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bit 7 - Edge Selection"] + #[inline(always)] + pub fn edgesel(&self) -> EDGESEL_R { + EDGESEL_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:11 - Input Selection 0"] + #[inline(always)] + pub fn insel0(&self) -> INSEL0_R { + INSEL0_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - Input Selection 1"] + #[inline(always)] + pub fn insel1(&self) -> INSEL1_R { + INSEL1_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:19 - Input Selection 2"] + #[inline(always)] + pub fn insel2(&self) -> INSEL2_R { + INSEL2_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Input Event Invert"] + #[inline(always)] + pub fn invei(&self) -> INVEI_R { + INVEI_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Event Input Enable"] + #[inline(always)] + pub fn lutei(&self) -> LUTEI_R { + LUTEI_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Event Output Enable"] + #[inline(always)] + pub fn luteo(&self) -> LUTEO_R { + LUTEO_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bits 24:31 - Truth Value"] + #[inline(always)] + pub fn truth(&self) -> TRUTH_R { + TRUTH_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bit 1 - LUT Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 4:5 - Filter Selection"] + #[inline(always)] + pub fn filtsel(&mut self) -> FILTSEL_W { + FILTSEL_W { w: self } + } + #[doc = "Bit 7 - Edge Selection"] + #[inline(always)] + pub fn edgesel(&mut self) -> EDGESEL_W { + EDGESEL_W { w: self } + } + #[doc = "Bits 8:11 - Input Selection 0"] + #[inline(always)] + pub fn insel0(&mut self) -> INSEL0_W { + INSEL0_W { w: self } + } + #[doc = "Bits 12:15 - Input Selection 1"] + #[inline(always)] + pub fn insel1(&mut self) -> INSEL1_W { + INSEL1_W { w: self } + } + #[doc = "Bits 16:19 - Input Selection 2"] + #[inline(always)] + pub fn insel2(&mut self) -> INSEL2_W { + INSEL2_W { w: self } + } + #[doc = "Bit 20 - Input Event Invert"] + #[inline(always)] + pub fn invei(&mut self) -> INVEI_W { + INVEI_W { w: self } + } + #[doc = "Bit 21 - Event Input Enable"] + #[inline(always)] + pub fn lutei(&mut self) -> LUTEI_W { + LUTEI_W { w: self } + } + #[doc = "Bit 22 - Event Output Enable"] + #[inline(always)] + pub fn luteo(&mut self) -> LUTEO_W { + LUTEO_W { w: self } + } + #[doc = "Bits 24:31 - Truth Value"] + #[inline(always)] + pub fn truth(&mut self) -> TRUTH_W { + TRUTH_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "LUT Control x\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lutctrl](index.html) module"] +pub struct LUTCTRL_SPEC; +impl crate::RegisterSpec for LUTCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [lutctrl::R](R) reader structure"] +impl crate::Readable for LUTCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [lutctrl::W](W) writer structure"] +impl crate::Writable for LUTCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets LUTCTRL[%s] +to value 0"] +impl crate::Resettable for LUTCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/ccl/seqctrl.rs b/pac/atsamc20g/src/ccl/seqctrl.rs new file mode 100644 index 000000000000..e2597a1042f3 --- /dev/null +++ b/pac/atsamc20g/src/ccl/seqctrl.rs @@ -0,0 +1,192 @@ +#[doc = "Register `SEQCTRL[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SEQCTRL[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Sequential Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SEQSEL_A { + #[doc = "0: Sequential logic is disabled"] + DISABLE = 0, + #[doc = "1: D flip flop"] + DFF = 1, + #[doc = "2: JK flip flop"] + JK = 2, + #[doc = "3: D latch"] + LATCH = 3, + #[doc = "4: RS latch"] + RS = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEQSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `SEQSEL` reader - Sequential Selection"] +pub struct SEQSEL_R(crate::FieldReader); +impl SEQSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SEQSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEQSEL_A::DISABLE), + 1 => Some(SEQSEL_A::DFF), + 2 => Some(SEQSEL_A::JK), + 3 => Some(SEQSEL_A::LATCH), + 4 => Some(SEQSEL_A::RS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == SEQSEL_A::DISABLE + } + #[doc = "Checks if the value of the field is `DFF`"] + #[inline(always)] + pub fn is_dff(&self) -> bool { + **self == SEQSEL_A::DFF + } + #[doc = "Checks if the value of the field is `JK`"] + #[inline(always)] + pub fn is_jk(&self) -> bool { + **self == SEQSEL_A::JK + } + #[doc = "Checks if the value of the field is `LATCH`"] + #[inline(always)] + pub fn is_latch(&self) -> bool { + **self == SEQSEL_A::LATCH + } + #[doc = "Checks if the value of the field is `RS`"] + #[inline(always)] + pub fn is_rs(&self) -> bool { + **self == SEQSEL_A::RS + } +} +impl core::ops::Deref for SEQSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEQSEL` writer - Sequential Selection"] +pub struct SEQSEL_W<'a> { + w: &'a mut W, +} +impl<'a> SEQSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SEQSEL_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Sequential logic is disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(SEQSEL_A::DISABLE) + } + #[doc = "D flip flop"] + #[inline(always)] + pub fn dff(self) -> &'a mut W { + self.variant(SEQSEL_A::DFF) + } + #[doc = "JK flip flop"] + #[inline(always)] + pub fn jk(self) -> &'a mut W { + self.variant(SEQSEL_A::JK) + } + #[doc = "D latch"] + #[inline(always)] + pub fn latch(self) -> &'a mut W { + self.variant(SEQSEL_A::LATCH) + } + #[doc = "RS latch"] + #[inline(always)] + pub fn rs(self) -> &'a mut W { + self.variant(SEQSEL_A::RS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Sequential Selection"] + #[inline(always)] + pub fn seqsel(&self) -> SEQSEL_R { + SEQSEL_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Sequential Selection"] + #[inline(always)] + pub fn seqsel(&mut self) -> SEQSEL_W { + SEQSEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SEQ Control x\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [seqctrl](index.html) module"] +pub struct SEQCTRL_SPEC; +impl crate::RegisterSpec for SEQCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [seqctrl::R](R) reader structure"] +impl crate::Readable for SEQCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [seqctrl::W](W) writer structure"] +impl crate::Writable for SEQCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SEQCTRL[%s] +to value 0"] +impl crate::Resettable for SEQCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/divas.rs b/pac/atsamc20g/src/divas.rs new file mode 100644 index 000000000000..dbc2f5f226da --- /dev/null +++ b/pac/atsamc20g/src/divas.rs @@ -0,0 +1,48 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrla: crate::Reg, + _reserved1: [u8; 0x03], + #[doc = "0x04 - Status"] + pub status: crate::Reg, + _reserved2: [u8; 0x03], + #[doc = "0x08 - Dividend"] + pub dividend: crate::Reg, + #[doc = "0x0c - Divisor"] + pub divisor: crate::Reg, + #[doc = "0x10 - Result"] + pub result: crate::Reg, + #[doc = "0x14 - Remainder"] + pub rem: crate::Reg, + #[doc = "0x18 - Square Root Input"] + pub sqrnum: crate::Reg, +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control"] +pub mod ctrla; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "DIVIDEND register accessor: an alias for `Reg`"] +pub type DIVIDEND = crate::Reg; +#[doc = "Dividend"] +pub mod dividend; +#[doc = "DIVISOR register accessor: an alias for `Reg`"] +pub type DIVISOR = crate::Reg; +#[doc = "Divisor"] +pub mod divisor; +#[doc = "RESULT register accessor: an alias for `Reg`"] +pub type RESULT = crate::Reg; +#[doc = "Result"] +pub mod result; +#[doc = "REM register accessor: an alias for `Reg`"] +pub type REM = crate::Reg; +#[doc = "Remainder"] +pub mod rem; +#[doc = "SQRNUM register accessor: an alias for `Reg`"] +pub type SQRNUM = crate::Reg; +#[doc = "Square Root Input"] +pub mod sqrnum; diff --git a/pac/atsamc20g/src/divas/ctrla.rs b/pac/atsamc20g/src/divas/ctrla.rs new file mode 100644 index 000000000000..7f79349da05c --- /dev/null +++ b/pac/atsamc20g/src/divas/ctrla.rs @@ -0,0 +1,160 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SIGNED` reader - Signed"] +pub struct SIGNED_R(crate::FieldReader); +impl SIGNED_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SIGNED_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SIGNED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SIGNED` writer - Signed"] +pub struct SIGNED_W<'a> { + w: &'a mut W, +} +impl<'a> SIGNED_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `DLZ` reader - Disable Leading Zero Optimization"] +pub struct DLZ_R(crate::FieldReader); +impl DLZ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DLZ_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DLZ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DLZ` writer - Disable Leading Zero Optimization"] +pub struct DLZ_W<'a> { + w: &'a mut W, +} +impl<'a> DLZ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - Signed"] + #[inline(always)] + pub fn signed(&self) -> SIGNED_R { + SIGNED_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Disable Leading Zero Optimization"] + #[inline(always)] + pub fn dlz(&self) -> DLZ_R { + DLZ_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Signed"] + #[inline(always)] + pub fn signed(&mut self) -> SIGNED_W { + SIGNED_W { w: self } + } + #[doc = "Bit 1 - Disable Leading Zero Optimization"] + #[inline(always)] + pub fn dlz(&mut self) -> DLZ_W { + DLZ_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/divas/dividend.rs b/pac/atsamc20g/src/divas/dividend.rs new file mode 100644 index 000000000000..215f44261a6c --- /dev/null +++ b/pac/atsamc20g/src/divas/dividend.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DIVIDEND` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIVIDEND` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIVIDEND` reader - DIVIDEND"] +pub struct DIVIDEND_R(crate::FieldReader); +impl DIVIDEND_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + DIVIDEND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIVIDEND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIVIDEND` writer - DIVIDEND"] +pub struct DIVIDEND_W<'a> { + w: &'a mut W, +} +impl<'a> DIVIDEND_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - DIVIDEND"] + #[inline(always)] + pub fn dividend(&self) -> DIVIDEND_R { + DIVIDEND_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - DIVIDEND"] + #[inline(always)] + pub fn dividend(&mut self) -> DIVIDEND_W { + DIVIDEND_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Dividend\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dividend](index.html) module"] +pub struct DIVIDEND_SPEC; +impl crate::RegisterSpec for DIVIDEND_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dividend::R](R) reader structure"] +impl crate::Readable for DIVIDEND_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dividend::W](W) writer structure"] +impl crate::Writable for DIVIDEND_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DIVIDEND to value 0"] +impl crate::Resettable for DIVIDEND_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/divas/divisor.rs b/pac/atsamc20g/src/divas/divisor.rs new file mode 100644 index 000000000000..b711870a5cd6 --- /dev/null +++ b/pac/atsamc20g/src/divas/divisor.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DIVISOR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIVISOR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIVISOR` reader - DIVISOR"] +pub struct DIVISOR_R(crate::FieldReader); +impl DIVISOR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + DIVISOR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIVISOR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIVISOR` writer - DIVISOR"] +pub struct DIVISOR_W<'a> { + w: &'a mut W, +} +impl<'a> DIVISOR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - DIVISOR"] + #[inline(always)] + pub fn divisor(&self) -> DIVISOR_R { + DIVISOR_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - DIVISOR"] + #[inline(always)] + pub fn divisor(&mut self) -> DIVISOR_W { + DIVISOR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Divisor\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [divisor](index.html) module"] +pub struct DIVISOR_SPEC; +impl crate::RegisterSpec for DIVISOR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [divisor::R](R) reader structure"] +impl crate::Readable for DIVISOR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [divisor::W](W) writer structure"] +impl crate::Writable for DIVISOR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DIVISOR to value 0"] +impl crate::Resettable for DIVISOR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/divas/rem.rs b/pac/atsamc20g/src/divas/rem.rs new file mode 100644 index 000000000000..76f3a90878ed --- /dev/null +++ b/pac/atsamc20g/src/divas/rem.rs @@ -0,0 +1,53 @@ +#[doc = "Register `REM` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `REM` reader - REM"] +pub struct REM_R(crate::FieldReader); +impl REM_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + REM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - REM"] + #[inline(always)] + pub fn rem(&self) -> REM_R { + REM_R::new(self.bits as u32) + } +} +#[doc = "Remainder\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rem](index.html) module"] +pub struct REM_SPEC; +impl crate::RegisterSpec for REM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rem::R](R) reader structure"] +impl crate::Readable for REM_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets REM to value 0"] +impl crate::Resettable for REM_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/divas/result.rs b/pac/atsamc20g/src/divas/result.rs new file mode 100644 index 000000000000..85fc1a025f9e --- /dev/null +++ b/pac/atsamc20g/src/divas/result.rs @@ -0,0 +1,53 @@ +#[doc = "Register `RESULT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `RESULT` reader - RESULT"] +pub struct RESULT_R(crate::FieldReader); +impl RESULT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + RESULT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESULT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - RESULT"] + #[inline(always)] + pub fn result(&self) -> RESULT_R { + RESULT_R::new(self.bits as u32) + } +} +#[doc = "Result\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [result](index.html) module"] +pub struct RESULT_SPEC; +impl crate::RegisterSpec for RESULT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [result::R](R) reader structure"] +impl crate::Readable for RESULT_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets RESULT to value 0"] +impl crate::Resettable for RESULT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/divas/sqrnum.rs b/pac/atsamc20g/src/divas/sqrnum.rs new file mode 100644 index 000000000000..cc0ce6806beb --- /dev/null +++ b/pac/atsamc20g/src/divas/sqrnum.rs @@ -0,0 +1,103 @@ +#[doc = "Register `SQRNUM` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SQRNUM` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SQRNUM` reader - Square Root Input"] +pub struct SQRNUM_R(crate::FieldReader); +impl SQRNUM_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + SQRNUM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SQRNUM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SQRNUM` writer - Square Root Input"] +pub struct SQRNUM_W<'a> { + w: &'a mut W, +} +impl<'a> SQRNUM_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Square Root Input"] + #[inline(always)] + pub fn sqrnum(&self) -> SQRNUM_R { + SQRNUM_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Square Root Input"] + #[inline(always)] + pub fn sqrnum(&mut self) -> SQRNUM_W { + SQRNUM_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Square Root Input\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sqrnum](index.html) module"] +pub struct SQRNUM_SPEC; +impl crate::RegisterSpec for SQRNUM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [sqrnum::R](R) reader structure"] +impl crate::Readable for SQRNUM_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [sqrnum::W](W) writer structure"] +impl crate::Writable for SQRNUM_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SQRNUM to value 0"] +impl crate::Resettable for SQRNUM_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/divas/status.rs b/pac/atsamc20g/src/divas/status.rs new file mode 100644 index 000000000000..feffbccec659 --- /dev/null +++ b/pac/atsamc20g/src/divas/status.rs @@ -0,0 +1,160 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BUSY` reader - DIVAS Accelerator Busy"] +pub struct BUSY_R(crate::FieldReader); +impl BUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSY` writer - DIVAS Accelerator Busy"] +pub struct BUSY_W<'a> { + w: &'a mut W, +} +impl<'a> BUSY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `DBZ` reader - Writing a one to this bit clears DBZ to zero"] +pub struct DBZ_R(crate::FieldReader); +impl DBZ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBZ_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBZ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBZ` writer - Writing a one to this bit clears DBZ to zero"] +pub struct DBZ_W<'a> { + w: &'a mut W, +} +impl<'a> DBZ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - DIVAS Accelerator Busy"] + #[inline(always)] + pub fn busy(&self) -> BUSY_R { + BUSY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Writing a one to this bit clears DBZ to zero"] + #[inline(always)] + pub fn dbz(&self) -> DBZ_R { + DBZ_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - DIVAS Accelerator Busy"] + #[inline(always)] + pub fn busy(&mut self) -> BUSY_W { + BUSY_W { w: self } + } + #[doc = "Bit 1 - Writing a one to this bit clears DBZ to zero"] + #[inline(always)] + pub fn dbz(&mut self) -> DBZ_W { + DBZ_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/dmac.rs b/pac/atsamc20g/src/dmac.rs new file mode 100644 index 000000000000..c23d36697550 --- /dev/null +++ b/pac/atsamc20g/src/dmac.rs @@ -0,0 +1,148 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrl: crate::Reg, + #[doc = "0x02 - CRC Control"] + pub crcctrl: crate::Reg, + #[doc = "0x04 - CRC Data Input"] + pub crcdatain: crate::Reg, + #[doc = "0x08 - CRC Checksum"] + pub crcchksum: crate::Reg, + #[doc = "0x0c - CRC Status"] + pub crcstatus: crate::Reg, + #[doc = "0x0d - Debug Control"] + pub dbgctrl: crate::Reg, + #[doc = "0x0e - QOS Control"] + pub qosctrl: crate::Reg, + _reserved7: [u8; 0x01], + #[doc = "0x10 - Software Trigger Control"] + pub swtrigctrl: crate::Reg, + #[doc = "0x14 - Priority Control 0"] + pub prictrl0: crate::Reg, + _reserved9: [u8; 0x08], + #[doc = "0x20 - Interrupt Pending"] + pub intpend: crate::Reg, + _reserved10: [u8; 0x02], + #[doc = "0x24 - Interrupt Status"] + pub intstatus: crate::Reg, + #[doc = "0x28 - Busy Channels"] + pub busych: crate::Reg, + #[doc = "0x2c - Pending Channels"] + pub pendch: crate::Reg, + #[doc = "0x30 - Active Channel and Levels"] + pub active: crate::Reg, + #[doc = "0x34 - Descriptor Memory Section Base Address"] + pub baseaddr: crate::Reg, + #[doc = "0x38 - Write-Back Memory Section Base Address"] + pub wrbaddr: crate::Reg, + _reserved16: [u8; 0x03], + #[doc = "0x3f - Channel ID"] + pub chid: crate::Reg, + #[doc = "0x40 - Channel Control A"] + pub chctrla: crate::Reg, + _reserved18: [u8; 0x03], + #[doc = "0x44 - Channel Control B"] + pub chctrlb: crate::Reg, + _reserved19: [u8; 0x04], + #[doc = "0x4c - Channel Interrupt Enable Clear"] + pub chintenclr: crate::Reg, + #[doc = "0x4d - Channel Interrupt Enable Set"] + pub chintenset: crate::Reg, + #[doc = "0x4e - Channel Interrupt Flag Status and Clear"] + pub chintflag: crate::Reg, + #[doc = "0x4f - Channel Status"] + pub chstatus: crate::Reg, +} +#[doc = "CTRL register accessor: an alias for `Reg`"] +pub type CTRL = crate::Reg; +#[doc = "Control"] +pub mod ctrl; +#[doc = "CRCCTRL register accessor: an alias for `Reg`"] +pub type CRCCTRL = crate::Reg; +#[doc = "CRC Control"] +pub mod crcctrl; +#[doc = "CRCDATAIN register accessor: an alias for `Reg`"] +pub type CRCDATAIN = crate::Reg; +#[doc = "CRC Data Input"] +pub mod crcdatain; +#[doc = "CRCCHKSUM register accessor: an alias for `Reg`"] +pub type CRCCHKSUM = crate::Reg; +#[doc = "CRC Checksum"] +pub mod crcchksum; +#[doc = "CRCSTATUS register accessor: an alias for `Reg`"] +pub type CRCSTATUS = crate::Reg; +#[doc = "CRC Status"] +pub mod crcstatus; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "QOSCTRL register accessor: an alias for `Reg`"] +pub type QOSCTRL = crate::Reg; +#[doc = "QOS Control"] +pub mod qosctrl; +#[doc = "SWTRIGCTRL register accessor: an alias for `Reg`"] +pub type SWTRIGCTRL = crate::Reg; +#[doc = "Software Trigger Control"] +pub mod swtrigctrl; +#[doc = "PRICTRL0 register accessor: an alias for `Reg`"] +pub type PRICTRL0 = crate::Reg; +#[doc = "Priority Control 0"] +pub mod prictrl0; +#[doc = "INTPEND register accessor: an alias for `Reg`"] +pub type INTPEND = crate::Reg; +#[doc = "Interrupt Pending"] +pub mod intpend; +#[doc = "INTSTATUS register accessor: an alias for `Reg`"] +pub type INTSTATUS = crate::Reg; +#[doc = "Interrupt Status"] +pub mod intstatus; +#[doc = "BUSYCH register accessor: an alias for `Reg`"] +pub type BUSYCH = crate::Reg; +#[doc = "Busy Channels"] +pub mod busych; +#[doc = "PENDCH register accessor: an alias for `Reg`"] +pub type PENDCH = crate::Reg; +#[doc = "Pending Channels"] +pub mod pendch; +#[doc = "ACTIVE register accessor: an alias for `Reg`"] +pub type ACTIVE = crate::Reg; +#[doc = "Active Channel and Levels"] +pub mod active; +#[doc = "BASEADDR register accessor: an alias for `Reg`"] +pub type BASEADDR = crate::Reg; +#[doc = "Descriptor Memory Section Base Address"] +pub mod baseaddr; +#[doc = "WRBADDR register accessor: an alias for `Reg`"] +pub type WRBADDR = crate::Reg; +#[doc = "Write-Back Memory Section Base Address"] +pub mod wrbaddr; +#[doc = "CHID register accessor: an alias for `Reg`"] +pub type CHID = crate::Reg; +#[doc = "Channel ID"] +pub mod chid; +#[doc = "CHCTRLA register accessor: an alias for `Reg`"] +pub type CHCTRLA = crate::Reg; +#[doc = "Channel Control A"] +pub mod chctrla; +#[doc = "CHCTRLB register accessor: an alias for `Reg`"] +pub type CHCTRLB = crate::Reg; +#[doc = "Channel Control B"] +pub mod chctrlb; +#[doc = "CHINTENCLR register accessor: an alias for `Reg`"] +pub type CHINTENCLR = crate::Reg; +#[doc = "Channel Interrupt Enable Clear"] +pub mod chintenclr; +#[doc = "CHINTENSET register accessor: an alias for `Reg`"] +pub type CHINTENSET = crate::Reg; +#[doc = "Channel Interrupt Enable Set"] +pub mod chintenset; +#[doc = "CHINTFLAG register accessor: an alias for `Reg`"] +pub type CHINTFLAG = crate::Reg; +#[doc = "Channel Interrupt Flag Status and Clear"] +pub mod chintflag; +#[doc = "CHSTATUS register accessor: an alias for `Reg`"] +pub type CHSTATUS = crate::Reg; +#[doc = "Channel Status"] +pub mod chstatus; diff --git a/pac/atsamc20g/src/dmac/active.rs b/pac/atsamc20g/src/dmac/active.rs new file mode 100644 index 000000000000..c3cc5a0420bc --- /dev/null +++ b/pac/atsamc20g/src/dmac/active.rs @@ -0,0 +1,173 @@ +#[doc = "Register `ACTIVE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `LVLEX0` reader - Level 0 Channel Trigger Request Executing"] +pub struct LVLEX0_R(crate::FieldReader); +impl LVLEX0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LVLEX0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEX0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLEX1` reader - Level 1 Channel Trigger Request Executing"] +pub struct LVLEX1_R(crate::FieldReader); +impl LVLEX1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LVLEX1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEX1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLEX2` reader - Level 2 Channel Trigger Request Executing"] +pub struct LVLEX2_R(crate::FieldReader); +impl LVLEX2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LVLEX2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEX2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLEX3` reader - Level 3 Channel Trigger Request Executing"] +pub struct LVLEX3_R(crate::FieldReader); +impl LVLEX3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LVLEX3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEX3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ID` reader - Active Channel ID"] +pub struct ID_R(crate::FieldReader); +impl ID_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ID_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ID_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ABUSY` reader - Active Channel Busy"] +pub struct ABUSY_R(crate::FieldReader); +impl ABUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ABUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ABUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BTCNT` reader - Active Channel Block Transfer Count"] +pub struct BTCNT_R(crate::FieldReader); +impl BTCNT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BTCNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BTCNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Level 0 Channel Trigger Request Executing"] + #[inline(always)] + pub fn lvlex0(&self) -> LVLEX0_R { + LVLEX0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Level 1 Channel Trigger Request Executing"] + #[inline(always)] + pub fn lvlex1(&self) -> LVLEX1_R { + LVLEX1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Level 2 Channel Trigger Request Executing"] + #[inline(always)] + pub fn lvlex2(&self) -> LVLEX2_R { + LVLEX2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Level 3 Channel Trigger Request Executing"] + #[inline(always)] + pub fn lvlex3(&self) -> LVLEX3_R { + LVLEX3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bits 8:12 - Active Channel ID"] + #[inline(always)] + pub fn id(&self) -> ID_R { + ID_R::new(((self.bits >> 8) & 0x1f) as u8) + } + #[doc = "Bit 15 - Active Channel Busy"] + #[inline(always)] + pub fn abusy(&self) -> ABUSY_R { + ABUSY_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:31 - Active Channel Block Transfer Count"] + #[inline(always)] + pub fn btcnt(&self) -> BTCNT_R { + BTCNT_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[doc = "Active Channel and Levels\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [active](index.html) module"] +pub struct ACTIVE_SPEC; +impl crate::RegisterSpec for ACTIVE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [active::R](R) reader structure"] +impl crate::Readable for ACTIVE_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets ACTIVE to value 0"] +impl crate::Resettable for ACTIVE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/dmac/baseaddr.rs b/pac/atsamc20g/src/dmac/baseaddr.rs new file mode 100644 index 000000000000..cec8c8cf0777 --- /dev/null +++ b/pac/atsamc20g/src/dmac/baseaddr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `BASEADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BASEADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BASEADDR` reader - Descriptor Memory Base Address"] +pub struct BASEADDR_R(crate::FieldReader); +impl BASEADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + BASEADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BASEADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BASEADDR` writer - Descriptor Memory Base Address"] +pub struct BASEADDR_W<'a> { + w: &'a mut W, +} +impl<'a> BASEADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Descriptor Memory Base Address"] + #[inline(always)] + pub fn baseaddr(&self) -> BASEADDR_R { + BASEADDR_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Descriptor Memory Base Address"] + #[inline(always)] + pub fn baseaddr(&mut self) -> BASEADDR_W { + BASEADDR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Descriptor Memory Section Base Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baseaddr](index.html) module"] +pub struct BASEADDR_SPEC; +impl crate::RegisterSpec for BASEADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [baseaddr::R](R) reader structure"] +impl crate::Readable for BASEADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baseaddr::W](W) writer structure"] +impl crate::Writable for BASEADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BASEADDR to value 0"] +impl crate::Resettable for BASEADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/dmac/busych.rs b/pac/atsamc20g/src/dmac/busych.rs new file mode 100644 index 000000000000..68fdc5e3788b --- /dev/null +++ b/pac/atsamc20g/src/dmac/busych.rs @@ -0,0 +1,153 @@ +#[doc = "Register `BUSYCH` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `BUSYCH0` reader - Busy Channel 0"] +pub struct BUSYCH0_R(crate::FieldReader); +impl BUSYCH0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH1` reader - Busy Channel 1"] +pub struct BUSYCH1_R(crate::FieldReader); +impl BUSYCH1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH2` reader - Busy Channel 2"] +pub struct BUSYCH2_R(crate::FieldReader); +impl BUSYCH2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH3` reader - Busy Channel 3"] +pub struct BUSYCH3_R(crate::FieldReader); +impl BUSYCH3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH4` reader - Busy Channel 4"] +pub struct BUSYCH4_R(crate::FieldReader); +impl BUSYCH4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH5` reader - Busy Channel 5"] +pub struct BUSYCH5_R(crate::FieldReader); +impl BUSYCH5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Busy Channel 0"] + #[inline(always)] + pub fn busych0(&self) -> BUSYCH0_R { + BUSYCH0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Busy Channel 1"] + #[inline(always)] + pub fn busych1(&self) -> BUSYCH1_R { + BUSYCH1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Busy Channel 2"] + #[inline(always)] + pub fn busych2(&self) -> BUSYCH2_R { + BUSYCH2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Busy Channel 3"] + #[inline(always)] + pub fn busych3(&self) -> BUSYCH3_R { + BUSYCH3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Busy Channel 4"] + #[inline(always)] + pub fn busych4(&self) -> BUSYCH4_R { + BUSYCH4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Busy Channel 5"] + #[inline(always)] + pub fn busych5(&self) -> BUSYCH5_R { + BUSYCH5_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +#[doc = "Busy Channels\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [busych](index.html) module"] +pub struct BUSYCH_SPEC; +impl crate::RegisterSpec for BUSYCH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [busych::R](R) reader structure"] +impl crate::Readable for BUSYCH_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets BUSYCH to value 0"] +impl crate::Resettable for BUSYCH_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/dmac/chctrla.rs b/pac/atsamc20g/src/dmac/chctrla.rs new file mode 100644 index 000000000000..22e8d456e05c --- /dev/null +++ b/pac/atsamc20g/src/dmac/chctrla.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CHCTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHCTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Channel Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Channel Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Channel Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Channel Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Channel run in standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Channel run in standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - Channel Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 6 - Channel run in standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Channel Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 6 - Channel run in standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chctrla](index.html) module"] +pub struct CHCTRLA_SPEC; +impl crate::RegisterSpec for CHCTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [chctrla::R](R) reader structure"] +impl crate::Readable for CHCTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chctrla::W](W) writer structure"] +impl crate::Writable for CHCTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHCTRLA to value 0"] +impl crate::Resettable for CHCTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/dmac/chctrlb.rs b/pac/atsamc20g/src/dmac/chctrlb.rs new file mode 100644 index 000000000000..5dcbc1da26f1 --- /dev/null +++ b/pac/atsamc20g/src/dmac/chctrlb.rs @@ -0,0 +1,1188 @@ +#[doc = "Register `CHCTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHCTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Event Input Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EVACT_A { + #[doc = "0: No action"] + NOACT = 0, + #[doc = "1: Transfer and periodic transfer trigger"] + TRIG = 1, + #[doc = "2: Conditional transfer trigger"] + CTRIG = 2, + #[doc = "3: Conditional block transfer"] + CBLOCK = 3, + #[doc = "4: Channel suspend operation"] + SUSPEND = 4, + #[doc = "5: Channel resume operation"] + RESUME = 5, + #[doc = "6: Skip next block suspend action"] + SSKIP = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EVACT_A) -> Self { + variant as _ + } +} +#[doc = "Field `EVACT` reader - Event Input Action"] +pub struct EVACT_R(crate::FieldReader); +impl EVACT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(EVACT_A::NOACT), + 1 => Some(EVACT_A::TRIG), + 2 => Some(EVACT_A::CTRIG), + 3 => Some(EVACT_A::CBLOCK), + 4 => Some(EVACT_A::SUSPEND), + 5 => Some(EVACT_A::RESUME), + 6 => Some(EVACT_A::SSKIP), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NOACT`"] + #[inline(always)] + pub fn is_noact(&self) -> bool { + **self == EVACT_A::NOACT + } + #[doc = "Checks if the value of the field is `TRIG`"] + #[inline(always)] + pub fn is_trig(&self) -> bool { + **self == EVACT_A::TRIG + } + #[doc = "Checks if the value of the field is `CTRIG`"] + #[inline(always)] + pub fn is_ctrig(&self) -> bool { + **self == EVACT_A::CTRIG + } + #[doc = "Checks if the value of the field is `CBLOCK`"] + #[inline(always)] + pub fn is_cblock(&self) -> bool { + **self == EVACT_A::CBLOCK + } + #[doc = "Checks if the value of the field is `SUSPEND`"] + #[inline(always)] + pub fn is_suspend(&self) -> bool { + **self == EVACT_A::SUSPEND + } + #[doc = "Checks if the value of the field is `RESUME`"] + #[inline(always)] + pub fn is_resume(&self) -> bool { + **self == EVACT_A::RESUME + } + #[doc = "Checks if the value of the field is `SSKIP`"] + #[inline(always)] + pub fn is_sskip(&self) -> bool { + **self == EVACT_A::SSKIP + } +} +impl core::ops::Deref for EVACT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT` writer - Event Input Action"] +pub struct EVACT_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EVACT_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn noact(self) -> &'a mut W { + self.variant(EVACT_A::NOACT) + } + #[doc = "Transfer and periodic transfer trigger"] + #[inline(always)] + pub fn trig(self) -> &'a mut W { + self.variant(EVACT_A::TRIG) + } + #[doc = "Conditional transfer trigger"] + #[inline(always)] + pub fn ctrig(self) -> &'a mut W { + self.variant(EVACT_A::CTRIG) + } + #[doc = "Conditional block transfer"] + #[inline(always)] + pub fn cblock(self) -> &'a mut W { + self.variant(EVACT_A::CBLOCK) + } + #[doc = "Channel suspend operation"] + #[inline(always)] + pub fn suspend(self) -> &'a mut W { + self.variant(EVACT_A::SUSPEND) + } + #[doc = "Channel resume operation"] + #[inline(always)] + pub fn resume(self) -> &'a mut W { + self.variant(EVACT_A::RESUME) + } + #[doc = "Skip next block suspend action"] + #[inline(always)] + pub fn sskip(self) -> &'a mut W { + self.variant(EVACT_A::SSKIP) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Field `EVIE` reader - Channel Event Input Enable"] +pub struct EVIE_R(crate::FieldReader); +impl EVIE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVIE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVIE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVIE` writer - Channel Event Input Enable"] +pub struct EVIE_W<'a> { + w: &'a mut W, +} +impl<'a> EVIE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `EVOE` reader - Channel Event Output Enable"] +pub struct EVOE_R(crate::FieldReader); +impl EVOE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVOE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVOE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVOE` writer - Channel Event Output Enable"] +pub struct EVOE_W<'a> { + w: &'a mut W, +} +impl<'a> EVOE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Channel Arbitration Level\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum LVL_A { + #[doc = "0: Channel Priority Level 0"] + LVL0 = 0, + #[doc = "1: Channel Priority Level 1"] + LVL1 = 1, + #[doc = "2: Channel Priority Level 2"] + LVL2 = 2, + #[doc = "3: Channel Priority Level 3"] + LVL3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LVL_A) -> Self { + variant as _ + } +} +#[doc = "Field `LVL` reader - Channel Arbitration Level"] +pub struct LVL_R(crate::FieldReader); +impl LVL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LVL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> LVL_A { + match self.bits { + 0 => LVL_A::LVL0, + 1 => LVL_A::LVL1, + 2 => LVL_A::LVL2, + 3 => LVL_A::LVL3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `LVL0`"] + #[inline(always)] + pub fn is_lvl0(&self) -> bool { + **self == LVL_A::LVL0 + } + #[doc = "Checks if the value of the field is `LVL1`"] + #[inline(always)] + pub fn is_lvl1(&self) -> bool { + **self == LVL_A::LVL1 + } + #[doc = "Checks if the value of the field is `LVL2`"] + #[inline(always)] + pub fn is_lvl2(&self) -> bool { + **self == LVL_A::LVL2 + } + #[doc = "Checks if the value of the field is `LVL3`"] + #[inline(always)] + pub fn is_lvl3(&self) -> bool { + **self == LVL_A::LVL3 + } +} +impl core::ops::Deref for LVL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVL` writer - Channel Arbitration Level"] +pub struct LVL_W<'a> { + w: &'a mut W, +} +impl<'a> LVL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: LVL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Channel Priority Level 0"] + #[inline(always)] + pub fn lvl0(self) -> &'a mut W { + self.variant(LVL_A::LVL0) + } + #[doc = "Channel Priority Level 1"] + #[inline(always)] + pub fn lvl1(self) -> &'a mut W { + self.variant(LVL_A::LVL1) + } + #[doc = "Channel Priority Level 2"] + #[inline(always)] + pub fn lvl2(self) -> &'a mut W { + self.variant(LVL_A::LVL2) + } + #[doc = "Channel Priority Level 3"] + #[inline(always)] + pub fn lvl3(self) -> &'a mut W { + self.variant(LVL_A::LVL3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 5)) | ((value as u32 & 0x03) << 5); + self.w + } +} +#[doc = "Trigger Source\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum TRIGSRC_A { + #[doc = "0: Only software/event triggers"] + DISABLE = 0, + #[doc = "2: SERCOM0 RX Trigger"] + SERCOM0_RX = 2, + #[doc = "3: SERCOM0 TX Trigger"] + SERCOM0_TX = 3, + #[doc = "4: SERCOM1 RX Trigger"] + SERCOM1_RX = 4, + #[doc = "5: SERCOM1 TX Trigger"] + SERCOM1_TX = 5, + #[doc = "6: SERCOM2 RX Trigger"] + SERCOM2_RX = 6, + #[doc = "7: SERCOM2 TX Trigger"] + SERCOM2_TX = 7, + #[doc = "8: SERCOM3 RX Trigger"] + SERCOM3_RX = 8, + #[doc = "9: SERCOM3 TX Trigger"] + SERCOM3_TX = 9, + #[doc = "16: TCC0 Overflow Trigger"] + TCC0_OVF = 16, + #[doc = "17: TCC0 Match/Compare 0 Trigger"] + TCC0_MC0 = 17, + #[doc = "18: TCC0 Match/Compare 1 Trigger"] + TCC0_MC1 = 18, + #[doc = "19: TCC0 Match/Compare 2 Trigger"] + TCC0_MC2 = 19, + #[doc = "20: TCC0 Match/Compare 3 Trigger"] + TCC0_MC3 = 20, + #[doc = "21: TCC1 Overflow Trigger"] + TCC1_OVF = 21, + #[doc = "22: TCC1 Match/Compare 0 Trigger"] + TCC1_MC0 = 22, + #[doc = "23: TCC1 Match/Compare 1 Trigger"] + TCC1_MC1 = 23, + #[doc = "24: TCC2 Overflow Trigger"] + TCC2_OVF = 24, + #[doc = "25: TCC2 Match/Compare 0 Trigger"] + TCC2_MC0 = 25, + #[doc = "26: TCC2 Match/Compare 1 Trigger"] + TCC2_MC1 = 26, + #[doc = "27: TC0 Overflow Trigger"] + TC0_OVF = 27, + #[doc = "28: TC0 Match/Compare 0 Trigger"] + TC0_MC0 = 28, + #[doc = "29: TC0 Match/Compare 1 Trigger"] + TC0_MC1 = 29, + #[doc = "30: TC1 Overflow Trigger"] + TC1_OVF = 30, + #[doc = "31: TC1 Match/Compare 0 Trigger"] + TC1_MC0 = 31, + #[doc = "32: TC1 Match/Compare 1 Trigger"] + TC1_MC1 = 32, + #[doc = "33: TC2 Overflow Trigger"] + TC2_OVF = 33, + #[doc = "34: TC2 Match/Compare 0 Trigger"] + TC2_MC0 = 34, + #[doc = "35: TC2 Match/Compare 1 Trigger"] + TC2_MC1 = 35, + #[doc = "36: TC3 Overflow Trigger"] + TC3_OVF = 36, + #[doc = "37: TC3 Match/Compare 0 Trigger"] + TC3_MC0 = 37, + #[doc = "38: TC3 Match/Compare 1 Trigger"] + TC3_MC1 = 38, + #[doc = "39: TC4 Overflow Trigger"] + TC4_OVF = 39, + #[doc = "40: TC4 Match/Compare 0 Trigger"] + TC4_MC0 = 40, + #[doc = "41: TC4 Match/Compare 1 Trigger"] + TC4_MC1 = 41, + #[doc = "42: ADC0 Result Ready Trigger"] + ADC0_RESRDY = 42, + #[doc = "46: PTC End of Conversion Trigger"] + PTC_EOC = 46, + #[doc = "47: PTC Window Compare Trigger"] + PTC_WCOMP = 47, + #[doc = "48: PTC Sequence Trigger"] + PTC_SEQ = 48, +} +impl From for u8 { + #[inline(always)] + fn from(variant: TRIGSRC_A) -> Self { + variant as _ + } +} +#[doc = "Field `TRIGSRC` reader - Trigger Source"] +pub struct TRIGSRC_R(crate::FieldReader); +impl TRIGSRC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TRIGSRC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(TRIGSRC_A::DISABLE), + 2 => Some(TRIGSRC_A::SERCOM0_RX), + 3 => Some(TRIGSRC_A::SERCOM0_TX), + 4 => Some(TRIGSRC_A::SERCOM1_RX), + 5 => Some(TRIGSRC_A::SERCOM1_TX), + 6 => Some(TRIGSRC_A::SERCOM2_RX), + 7 => Some(TRIGSRC_A::SERCOM2_TX), + 8 => Some(TRIGSRC_A::SERCOM3_RX), + 9 => Some(TRIGSRC_A::SERCOM3_TX), + 16 => Some(TRIGSRC_A::TCC0_OVF), + 17 => Some(TRIGSRC_A::TCC0_MC0), + 18 => Some(TRIGSRC_A::TCC0_MC1), + 19 => Some(TRIGSRC_A::TCC0_MC2), + 20 => Some(TRIGSRC_A::TCC0_MC3), + 21 => Some(TRIGSRC_A::TCC1_OVF), + 22 => Some(TRIGSRC_A::TCC1_MC0), + 23 => Some(TRIGSRC_A::TCC1_MC1), + 24 => Some(TRIGSRC_A::TCC2_OVF), + 25 => Some(TRIGSRC_A::TCC2_MC0), + 26 => Some(TRIGSRC_A::TCC2_MC1), + 27 => Some(TRIGSRC_A::TC0_OVF), + 28 => Some(TRIGSRC_A::TC0_MC0), + 29 => Some(TRIGSRC_A::TC0_MC1), + 30 => Some(TRIGSRC_A::TC1_OVF), + 31 => Some(TRIGSRC_A::TC1_MC0), + 32 => Some(TRIGSRC_A::TC1_MC1), + 33 => Some(TRIGSRC_A::TC2_OVF), + 34 => Some(TRIGSRC_A::TC2_MC0), + 35 => Some(TRIGSRC_A::TC2_MC1), + 36 => Some(TRIGSRC_A::TC3_OVF), + 37 => Some(TRIGSRC_A::TC3_MC0), + 38 => Some(TRIGSRC_A::TC3_MC1), + 39 => Some(TRIGSRC_A::TC4_OVF), + 40 => Some(TRIGSRC_A::TC4_MC0), + 41 => Some(TRIGSRC_A::TC4_MC1), + 42 => Some(TRIGSRC_A::ADC0_RESRDY), + 46 => Some(TRIGSRC_A::PTC_EOC), + 47 => Some(TRIGSRC_A::PTC_WCOMP), + 48 => Some(TRIGSRC_A::PTC_SEQ), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == TRIGSRC_A::DISABLE + } + #[doc = "Checks if the value of the field is `SERCOM0_RX`"] + #[inline(always)] + pub fn is_sercom0_rx(&self) -> bool { + **self == TRIGSRC_A::SERCOM0_RX + } + #[doc = "Checks if the value of the field is `SERCOM0_TX`"] + #[inline(always)] + pub fn is_sercom0_tx(&self) -> bool { + **self == TRIGSRC_A::SERCOM0_TX + } + #[doc = "Checks if the value of the field is `SERCOM1_RX`"] + #[inline(always)] + pub fn is_sercom1_rx(&self) -> bool { + **self == TRIGSRC_A::SERCOM1_RX + } + #[doc = "Checks if the value of the field is `SERCOM1_TX`"] + #[inline(always)] + pub fn is_sercom1_tx(&self) -> bool { + **self == TRIGSRC_A::SERCOM1_TX + } + #[doc = "Checks if the value of the field is `SERCOM2_RX`"] + #[inline(always)] + pub fn is_sercom2_rx(&self) -> bool { + **self == TRIGSRC_A::SERCOM2_RX + } + #[doc = "Checks if the value of the field is `SERCOM2_TX`"] + #[inline(always)] + pub fn is_sercom2_tx(&self) -> bool { + **self == TRIGSRC_A::SERCOM2_TX + } + #[doc = "Checks if the value of the field is `SERCOM3_RX`"] + #[inline(always)] + pub fn is_sercom3_rx(&self) -> bool { + **self == TRIGSRC_A::SERCOM3_RX + } + #[doc = "Checks if the value of the field is `SERCOM3_TX`"] + #[inline(always)] + pub fn is_sercom3_tx(&self) -> bool { + **self == TRIGSRC_A::SERCOM3_TX + } + #[doc = "Checks if the value of the field is `TCC0_OVF`"] + #[inline(always)] + pub fn is_tcc0_ovf(&self) -> bool { + **self == TRIGSRC_A::TCC0_OVF + } + #[doc = "Checks if the value of the field is `TCC0_MC0`"] + #[inline(always)] + pub fn is_tcc0_mc0(&self) -> bool { + **self == TRIGSRC_A::TCC0_MC0 + } + #[doc = "Checks if the value of the field is `TCC0_MC1`"] + #[inline(always)] + pub fn is_tcc0_mc1(&self) -> bool { + **self == TRIGSRC_A::TCC0_MC1 + } + #[doc = "Checks if the value of the field is `TCC0_MC2`"] + #[inline(always)] + pub fn is_tcc0_mc2(&self) -> bool { + **self == TRIGSRC_A::TCC0_MC2 + } + #[doc = "Checks if the value of the field is `TCC0_MC3`"] + #[inline(always)] + pub fn is_tcc0_mc3(&self) -> bool { + **self == TRIGSRC_A::TCC0_MC3 + } + #[doc = "Checks if the value of the field is `TCC1_OVF`"] + #[inline(always)] + pub fn is_tcc1_ovf(&self) -> bool { + **self == TRIGSRC_A::TCC1_OVF + } + #[doc = "Checks if the value of the field is `TCC1_MC0`"] + #[inline(always)] + pub fn is_tcc1_mc0(&self) -> bool { + **self == TRIGSRC_A::TCC1_MC0 + } + #[doc = "Checks if the value of the field is `TCC1_MC1`"] + #[inline(always)] + pub fn is_tcc1_mc1(&self) -> bool { + **self == TRIGSRC_A::TCC1_MC1 + } + #[doc = "Checks if the value of the field is `TCC2_OVF`"] + #[inline(always)] + pub fn is_tcc2_ovf(&self) -> bool { + **self == TRIGSRC_A::TCC2_OVF + } + #[doc = "Checks if the value of the field is `TCC2_MC0`"] + #[inline(always)] + pub fn is_tcc2_mc0(&self) -> bool { + **self == TRIGSRC_A::TCC2_MC0 + } + #[doc = "Checks if the value of the field is `TCC2_MC1`"] + #[inline(always)] + pub fn is_tcc2_mc1(&self) -> bool { + **self == TRIGSRC_A::TCC2_MC1 + } + #[doc = "Checks if the value of the field is `TC0_OVF`"] + #[inline(always)] + pub fn is_tc0_ovf(&self) -> bool { + **self == TRIGSRC_A::TC0_OVF + } + #[doc = "Checks if the value of the field is `TC0_MC0`"] + #[inline(always)] + pub fn is_tc0_mc0(&self) -> bool { + **self == TRIGSRC_A::TC0_MC0 + } + #[doc = "Checks if the value of the field is `TC0_MC1`"] + #[inline(always)] + pub fn is_tc0_mc1(&self) -> bool { + **self == TRIGSRC_A::TC0_MC1 + } + #[doc = "Checks if the value of the field is `TC1_OVF`"] + #[inline(always)] + pub fn is_tc1_ovf(&self) -> bool { + **self == TRIGSRC_A::TC1_OVF + } + #[doc = "Checks if the value of the field is `TC1_MC0`"] + #[inline(always)] + pub fn is_tc1_mc0(&self) -> bool { + **self == TRIGSRC_A::TC1_MC0 + } + #[doc = "Checks if the value of the field is `TC1_MC1`"] + #[inline(always)] + pub fn is_tc1_mc1(&self) -> bool { + **self == TRIGSRC_A::TC1_MC1 + } + #[doc = "Checks if the value of the field is `TC2_OVF`"] + #[inline(always)] + pub fn is_tc2_ovf(&self) -> bool { + **self == TRIGSRC_A::TC2_OVF + } + #[doc = "Checks if the value of the field is `TC2_MC0`"] + #[inline(always)] + pub fn is_tc2_mc0(&self) -> bool { + **self == TRIGSRC_A::TC2_MC0 + } + #[doc = "Checks if the value of the field is `TC2_MC1`"] + #[inline(always)] + pub fn is_tc2_mc1(&self) -> bool { + **self == TRIGSRC_A::TC2_MC1 + } + #[doc = "Checks if the value of the field is `TC3_OVF`"] + #[inline(always)] + pub fn is_tc3_ovf(&self) -> bool { + **self == TRIGSRC_A::TC3_OVF + } + #[doc = "Checks if the value of the field is `TC3_MC0`"] + #[inline(always)] + pub fn is_tc3_mc0(&self) -> bool { + **self == TRIGSRC_A::TC3_MC0 + } + #[doc = "Checks if the value of the field is `TC3_MC1`"] + #[inline(always)] + pub fn is_tc3_mc1(&self) -> bool { + **self == TRIGSRC_A::TC3_MC1 + } + #[doc = "Checks if the value of the field is `TC4_OVF`"] + #[inline(always)] + pub fn is_tc4_ovf(&self) -> bool { + **self == TRIGSRC_A::TC4_OVF + } + #[doc = "Checks if the value of the field is `TC4_MC0`"] + #[inline(always)] + pub fn is_tc4_mc0(&self) -> bool { + **self == TRIGSRC_A::TC4_MC0 + } + #[doc = "Checks if the value of the field is `TC4_MC1`"] + #[inline(always)] + pub fn is_tc4_mc1(&self) -> bool { + **self == TRIGSRC_A::TC4_MC1 + } + #[doc = "Checks if the value of the field is `ADC0_RESRDY`"] + #[inline(always)] + pub fn is_adc0_resrdy(&self) -> bool { + **self == TRIGSRC_A::ADC0_RESRDY + } + #[doc = "Checks if the value of the field is `PTC_EOC`"] + #[inline(always)] + pub fn is_ptc_eoc(&self) -> bool { + **self == TRIGSRC_A::PTC_EOC + } + #[doc = "Checks if the value of the field is `PTC_WCOMP`"] + #[inline(always)] + pub fn is_ptc_wcomp(&self) -> bool { + **self == TRIGSRC_A::PTC_WCOMP + } + #[doc = "Checks if the value of the field is `PTC_SEQ`"] + #[inline(always)] + pub fn is_ptc_seq(&self) -> bool { + **self == TRIGSRC_A::PTC_SEQ + } +} +impl core::ops::Deref for TRIGSRC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRIGSRC` writer - Trigger Source"] +pub struct TRIGSRC_W<'a> { + w: &'a mut W, +} +impl<'a> TRIGSRC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TRIGSRC_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Only software/event triggers"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(TRIGSRC_A::DISABLE) + } + #[doc = "SERCOM0 RX Trigger"] + #[inline(always)] + pub fn sercom0_rx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM0_RX) + } + #[doc = "SERCOM0 TX Trigger"] + #[inline(always)] + pub fn sercom0_tx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM0_TX) + } + #[doc = "SERCOM1 RX Trigger"] + #[inline(always)] + pub fn sercom1_rx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM1_RX) + } + #[doc = "SERCOM1 TX Trigger"] + #[inline(always)] + pub fn sercom1_tx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM1_TX) + } + #[doc = "SERCOM2 RX Trigger"] + #[inline(always)] + pub fn sercom2_rx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM2_RX) + } + #[doc = "SERCOM2 TX Trigger"] + #[inline(always)] + pub fn sercom2_tx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM2_TX) + } + #[doc = "SERCOM3 RX Trigger"] + #[inline(always)] + pub fn sercom3_rx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM3_RX) + } + #[doc = "SERCOM3 TX Trigger"] + #[inline(always)] + pub fn sercom3_tx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM3_TX) + } + #[doc = "TCC0 Overflow Trigger"] + #[inline(always)] + pub fn tcc0_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC0_OVF) + } + #[doc = "TCC0 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tcc0_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC0_MC0) + } + #[doc = "TCC0 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tcc0_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC0_MC1) + } + #[doc = "TCC0 Match/Compare 2 Trigger"] + #[inline(always)] + pub fn tcc0_mc2(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC0_MC2) + } + #[doc = "TCC0 Match/Compare 3 Trigger"] + #[inline(always)] + pub fn tcc0_mc3(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC0_MC3) + } + #[doc = "TCC1 Overflow Trigger"] + #[inline(always)] + pub fn tcc1_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC1_OVF) + } + #[doc = "TCC1 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tcc1_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC1_MC0) + } + #[doc = "TCC1 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tcc1_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC1_MC1) + } + #[doc = "TCC2 Overflow Trigger"] + #[inline(always)] + pub fn tcc2_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC2_OVF) + } + #[doc = "TCC2 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tcc2_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC2_MC0) + } + #[doc = "TCC2 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tcc2_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC2_MC1) + } + #[doc = "TC0 Overflow Trigger"] + #[inline(always)] + pub fn tc0_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC0_OVF) + } + #[doc = "TC0 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tc0_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC0_MC0) + } + #[doc = "TC0 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tc0_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC0_MC1) + } + #[doc = "TC1 Overflow Trigger"] + #[inline(always)] + pub fn tc1_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC1_OVF) + } + #[doc = "TC1 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tc1_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC1_MC0) + } + #[doc = "TC1 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tc1_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC1_MC1) + } + #[doc = "TC2 Overflow Trigger"] + #[inline(always)] + pub fn tc2_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC2_OVF) + } + #[doc = "TC2 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tc2_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC2_MC0) + } + #[doc = "TC2 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tc2_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC2_MC1) + } + #[doc = "TC3 Overflow Trigger"] + #[inline(always)] + pub fn tc3_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC3_OVF) + } + #[doc = "TC3 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tc3_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC3_MC0) + } + #[doc = "TC3 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tc3_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC3_MC1) + } + #[doc = "TC4 Overflow Trigger"] + #[inline(always)] + pub fn tc4_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC4_OVF) + } + #[doc = "TC4 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tc4_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC4_MC0) + } + #[doc = "TC4 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tc4_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC4_MC1) + } + #[doc = "ADC0 Result Ready Trigger"] + #[inline(always)] + pub fn adc0_resrdy(self) -> &'a mut W { + self.variant(TRIGSRC_A::ADC0_RESRDY) + } + #[doc = "PTC End of Conversion Trigger"] + #[inline(always)] + pub fn ptc_eoc(self) -> &'a mut W { + self.variant(TRIGSRC_A::PTC_EOC) + } + #[doc = "PTC Window Compare Trigger"] + #[inline(always)] + pub fn ptc_wcomp(self) -> &'a mut W { + self.variant(TRIGSRC_A::PTC_WCOMP) + } + #[doc = "PTC Sequence Trigger"] + #[inline(always)] + pub fn ptc_seq(self) -> &'a mut W { + self.variant(TRIGSRC_A::PTC_SEQ) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 8)) | ((value as u32 & 0x3f) << 8); + self.w + } +} +#[doc = "Trigger Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum TRIGACT_A { + #[doc = "0: One trigger required for each block transfer"] + BLOCK = 0, + #[doc = "2: One trigger required for each beat transfer"] + BEAT = 2, + #[doc = "3: One trigger required for each transaction"] + TRANSACTION = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: TRIGACT_A) -> Self { + variant as _ + } +} +#[doc = "Field `TRIGACT` reader - Trigger Action"] +pub struct TRIGACT_R(crate::FieldReader); +impl TRIGACT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TRIGACT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(TRIGACT_A::BLOCK), + 2 => Some(TRIGACT_A::BEAT), + 3 => Some(TRIGACT_A::TRANSACTION), + _ => None, + } + } + #[doc = "Checks if the value of the field is `BLOCK`"] + #[inline(always)] + pub fn is_block(&self) -> bool { + **self == TRIGACT_A::BLOCK + } + #[doc = "Checks if the value of the field is `BEAT`"] + #[inline(always)] + pub fn is_beat(&self) -> bool { + **self == TRIGACT_A::BEAT + } + #[doc = "Checks if the value of the field is `TRANSACTION`"] + #[inline(always)] + pub fn is_transaction(&self) -> bool { + **self == TRIGACT_A::TRANSACTION + } +} +impl core::ops::Deref for TRIGACT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRIGACT` writer - Trigger Action"] +pub struct TRIGACT_W<'a> { + w: &'a mut W, +} +impl<'a> TRIGACT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TRIGACT_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "One trigger required for each block transfer"] + #[inline(always)] + pub fn block(self) -> &'a mut W { + self.variant(TRIGACT_A::BLOCK) + } + #[doc = "One trigger required for each beat transfer"] + #[inline(always)] + pub fn beat(self) -> &'a mut W { + self.variant(TRIGACT_A::BEAT) + } + #[doc = "One trigger required for each transaction"] + #[inline(always)] + pub fn transaction(self) -> &'a mut W { + self.variant(TRIGACT_A::TRANSACTION) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 22)) | ((value as u32 & 0x03) << 22); + self.w + } +} +#[doc = "Software Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NOACT = 0, + #[doc = "1: Channel suspend operation"] + SUSPEND = 1, + #[doc = "2: Channel resume operation"] + RESUME = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Software Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NOACT), + 1 => Some(CMD_A::SUSPEND), + 2 => Some(CMD_A::RESUME), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NOACT`"] + #[inline(always)] + pub fn is_noact(&self) -> bool { + **self == CMD_A::NOACT + } + #[doc = "Checks if the value of the field is `SUSPEND`"] + #[inline(always)] + pub fn is_suspend(&self) -> bool { + **self == CMD_A::SUSPEND + } + #[doc = "Checks if the value of the field is `RESUME`"] + #[inline(always)] + pub fn is_resume(&self) -> bool { + **self == CMD_A::RESUME + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Software Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn noact(self) -> &'a mut W { + self.variant(CMD_A::NOACT) + } + #[doc = "Channel suspend operation"] + #[inline(always)] + pub fn suspend(self) -> &'a mut W { + self.variant(CMD_A::SUSPEND) + } + #[doc = "Channel resume operation"] + #[inline(always)] + pub fn resume(self) -> &'a mut W { + self.variant(CMD_A::RESUME) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 24)) | ((value as u32 & 0x03) << 24); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Event Input Action"] + #[inline(always)] + pub fn evact(&self) -> EVACT_R { + EVACT_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 3 - Channel Event Input Enable"] + #[inline(always)] + pub fn evie(&self) -> EVIE_R { + EVIE_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Channel Event Output Enable"] + #[inline(always)] + pub fn evoe(&self) -> EVOE_R { + EVOE_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bits 5:6 - Channel Arbitration Level"] + #[inline(always)] + pub fn lvl(&self) -> LVL_R { + LVL_R::new(((self.bits >> 5) & 0x03) as u8) + } + #[doc = "Bits 8:13 - Trigger Source"] + #[inline(always)] + pub fn trigsrc(&self) -> TRIGSRC_R { + TRIGSRC_R::new(((self.bits >> 8) & 0x3f) as u8) + } + #[doc = "Bits 22:23 - Trigger Action"] + #[inline(always)] + pub fn trigact(&self) -> TRIGACT_R { + TRIGACT_R::new(((self.bits >> 22) & 0x03) as u8) + } + #[doc = "Bits 24:25 - Software Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 24) & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Event Input Action"] + #[inline(always)] + pub fn evact(&mut self) -> EVACT_W { + EVACT_W { w: self } + } + #[doc = "Bit 3 - Channel Event Input Enable"] + #[inline(always)] + pub fn evie(&mut self) -> EVIE_W { + EVIE_W { w: self } + } + #[doc = "Bit 4 - Channel Event Output Enable"] + #[inline(always)] + pub fn evoe(&mut self) -> EVOE_W { + EVOE_W { w: self } + } + #[doc = "Bits 5:6 - Channel Arbitration Level"] + #[inline(always)] + pub fn lvl(&mut self) -> LVL_W { + LVL_W { w: self } + } + #[doc = "Bits 8:13 - Trigger Source"] + #[inline(always)] + pub fn trigsrc(&mut self) -> TRIGSRC_W { + TRIGSRC_W { w: self } + } + #[doc = "Bits 22:23 - Trigger Action"] + #[inline(always)] + pub fn trigact(&mut self) -> TRIGACT_W { + TRIGACT_W { w: self } + } + #[doc = "Bits 24:25 - Software Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chctrlb](index.html) module"] +pub struct CHCTRLB_SPEC; +impl crate::RegisterSpec for CHCTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [chctrlb::R](R) reader structure"] +impl crate::Readable for CHCTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chctrlb::W](W) writer structure"] +impl crate::Writable for CHCTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHCTRLB to value 0"] +impl crate::Resettable for CHCTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/dmac/chid.rs b/pac/atsamc20g/src/dmac/chid.rs new file mode 100644 index 000000000000..1f778a7fc6f0 --- /dev/null +++ b/pac/atsamc20g/src/dmac/chid.rs @@ -0,0 +1,103 @@ +#[doc = "Register `CHID` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHID` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ID` reader - Channel ID"] +pub struct ID_R(crate::FieldReader); +impl ID_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ID_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ID_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ID` writer - Channel ID"] +pub struct ID_W<'a> { + w: &'a mut W, +} +impl<'a> ID_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Channel ID"] + #[inline(always)] + pub fn id(&self) -> ID_R { + ID_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Channel ID"] + #[inline(always)] + pub fn id(&mut self) -> ID_W { + ID_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel ID\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chid](index.html) module"] +pub struct CHID_SPEC; +impl crate::RegisterSpec for CHID_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [chid::R](R) reader structure"] +impl crate::Readable for CHID_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chid::W](W) writer structure"] +impl crate::Writable for CHID_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHID to value 0"] +impl crate::Resettable for CHID_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/dmac/chintenclr.rs b/pac/atsamc20g/src/dmac/chintenclr.rs new file mode 100644 index 000000000000..5ae3096f9ab8 --- /dev/null +++ b/pac/atsamc20g/src/dmac/chintenclr.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CHINTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHINTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TERR` reader - Channel Transfer Error Interrupt Enable"] +pub struct TERR_R(crate::FieldReader); +impl TERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TERR` writer - Channel Transfer Error Interrupt Enable"] +pub struct TERR_W<'a> { + w: &'a mut W, +} +impl<'a> TERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TCMPL` reader - Channel Transfer Complete Interrupt Enable"] +pub struct TCMPL_R(crate::FieldReader); +impl TCMPL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCMPL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCMPL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCMPL` writer - Channel Transfer Complete Interrupt Enable"] +pub struct TCMPL_W<'a> { + w: &'a mut W, +} +impl<'a> TCMPL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SUSP` reader - Channel Suspend Interrupt Enable"] +pub struct SUSP_R(crate::FieldReader); +impl SUSP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SUSP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SUSP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SUSP` writer - Channel Suspend Interrupt Enable"] +pub struct SUSP_W<'a> { + w: &'a mut W, +} +impl<'a> SUSP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Channel Transfer Error Interrupt Enable"] + #[inline(always)] + pub fn terr(&self) -> TERR_R { + TERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel Transfer Complete Interrupt Enable"] + #[inline(always)] + pub fn tcmpl(&self) -> TCMPL_R { + TCMPL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel Suspend Interrupt Enable"] + #[inline(always)] + pub fn susp(&self) -> SUSP_R { + SUSP_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel Transfer Error Interrupt Enable"] + #[inline(always)] + pub fn terr(&mut self) -> TERR_W { + TERR_W { w: self } + } + #[doc = "Bit 1 - Channel Transfer Complete Interrupt Enable"] + #[inline(always)] + pub fn tcmpl(&mut self) -> TCMPL_W { + TCMPL_W { w: self } + } + #[doc = "Bit 2 - Channel Suspend Interrupt Enable"] + #[inline(always)] + pub fn susp(&mut self) -> SUSP_W { + SUSP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chintenclr](index.html) module"] +pub struct CHINTENCLR_SPEC; +impl crate::RegisterSpec for CHINTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [chintenclr::R](R) reader structure"] +impl crate::Readable for CHINTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chintenclr::W](W) writer structure"] +impl crate::Writable for CHINTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHINTENCLR to value 0"] +impl crate::Resettable for CHINTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/dmac/chintenset.rs b/pac/atsamc20g/src/dmac/chintenset.rs new file mode 100644 index 000000000000..2e7daef20a6f --- /dev/null +++ b/pac/atsamc20g/src/dmac/chintenset.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CHINTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHINTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TERR` reader - Channel Transfer Error Interrupt Enable"] +pub struct TERR_R(crate::FieldReader); +impl TERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TERR` writer - Channel Transfer Error Interrupt Enable"] +pub struct TERR_W<'a> { + w: &'a mut W, +} +impl<'a> TERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TCMPL` reader - Channel Transfer Complete Interrupt Enable"] +pub struct TCMPL_R(crate::FieldReader); +impl TCMPL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCMPL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCMPL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCMPL` writer - Channel Transfer Complete Interrupt Enable"] +pub struct TCMPL_W<'a> { + w: &'a mut W, +} +impl<'a> TCMPL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SUSP` reader - Channel Suspend Interrupt Enable"] +pub struct SUSP_R(crate::FieldReader); +impl SUSP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SUSP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SUSP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SUSP` writer - Channel Suspend Interrupt Enable"] +pub struct SUSP_W<'a> { + w: &'a mut W, +} +impl<'a> SUSP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Channel Transfer Error Interrupt Enable"] + #[inline(always)] + pub fn terr(&self) -> TERR_R { + TERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel Transfer Complete Interrupt Enable"] + #[inline(always)] + pub fn tcmpl(&self) -> TCMPL_R { + TCMPL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel Suspend Interrupt Enable"] + #[inline(always)] + pub fn susp(&self) -> SUSP_R { + SUSP_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel Transfer Error Interrupt Enable"] + #[inline(always)] + pub fn terr(&mut self) -> TERR_W { + TERR_W { w: self } + } + #[doc = "Bit 1 - Channel Transfer Complete Interrupt Enable"] + #[inline(always)] + pub fn tcmpl(&mut self) -> TCMPL_W { + TCMPL_W { w: self } + } + #[doc = "Bit 2 - Channel Suspend Interrupt Enable"] + #[inline(always)] + pub fn susp(&mut self) -> SUSP_W { + SUSP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chintenset](index.html) module"] +pub struct CHINTENSET_SPEC; +impl crate::RegisterSpec for CHINTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [chintenset::R](R) reader structure"] +impl crate::Readable for CHINTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chintenset::W](W) writer structure"] +impl crate::Writable for CHINTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHINTENSET to value 0"] +impl crate::Resettable for CHINTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/dmac/chintflag.rs b/pac/atsamc20g/src/dmac/chintflag.rs new file mode 100644 index 000000000000..4e61d6510c30 --- /dev/null +++ b/pac/atsamc20g/src/dmac/chintflag.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CHINTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHINTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TERR` reader - Channel Transfer Error"] +pub struct TERR_R(crate::FieldReader); +impl TERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TERR` writer - Channel Transfer Error"] +pub struct TERR_W<'a> { + w: &'a mut W, +} +impl<'a> TERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TCMPL` reader - Channel Transfer Complete"] +pub struct TCMPL_R(crate::FieldReader); +impl TCMPL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCMPL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCMPL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCMPL` writer - Channel Transfer Complete"] +pub struct TCMPL_W<'a> { + w: &'a mut W, +} +impl<'a> TCMPL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SUSP` reader - Channel Suspend"] +pub struct SUSP_R(crate::FieldReader); +impl SUSP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SUSP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SUSP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SUSP` writer - Channel Suspend"] +pub struct SUSP_W<'a> { + w: &'a mut W, +} +impl<'a> SUSP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Channel Transfer Error"] + #[inline(always)] + pub fn terr(&self) -> TERR_R { + TERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel Transfer Complete"] + #[inline(always)] + pub fn tcmpl(&self) -> TCMPL_R { + TCMPL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel Suspend"] + #[inline(always)] + pub fn susp(&self) -> SUSP_R { + SUSP_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel Transfer Error"] + #[inline(always)] + pub fn terr(&mut self) -> TERR_W { + TERR_W { w: self } + } + #[doc = "Bit 1 - Channel Transfer Complete"] + #[inline(always)] + pub fn tcmpl(&mut self) -> TCMPL_W { + TCMPL_W { w: self } + } + #[doc = "Bit 2 - Channel Suspend"] + #[inline(always)] + pub fn susp(&mut self) -> SUSP_W { + SUSP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chintflag](index.html) module"] +pub struct CHINTFLAG_SPEC; +impl crate::RegisterSpec for CHINTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [chintflag::R](R) reader structure"] +impl crate::Readable for CHINTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chintflag::W](W) writer structure"] +impl crate::Writable for CHINTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHINTFLAG to value 0"] +impl crate::Resettable for CHINTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/dmac/chstatus.rs b/pac/atsamc20g/src/dmac/chstatus.rs new file mode 100644 index 000000000000..98a84345d4f7 --- /dev/null +++ b/pac/atsamc20g/src/dmac/chstatus.rs @@ -0,0 +1,93 @@ +#[doc = "Register `CHSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PEND` reader - Channel Pending"] +pub struct PEND_R(crate::FieldReader); +impl PEND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSY` reader - Channel Busy"] +pub struct BUSY_R(crate::FieldReader); +impl BUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FERR` reader - Channel Fetch Error"] +pub struct FERR_R(crate::FieldReader); +impl FERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Channel Pending"] + #[inline(always)] + pub fn pend(&self) -> PEND_R { + PEND_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel Busy"] + #[inline(always)] + pub fn busy(&self) -> BUSY_R { + BUSY_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel Fetch Error"] + #[inline(always)] + pub fn ferr(&self) -> FERR_R { + FERR_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +#[doc = "Channel Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chstatus](index.html) module"] +pub struct CHSTATUS_SPEC; +impl crate::RegisterSpec for CHSTATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [chstatus::R](R) reader structure"] +impl crate::Readable for CHSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CHSTATUS to value 0"] +impl crate::Resettable for CHSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/dmac/crcchksum.rs b/pac/atsamc20g/src/dmac/crcchksum.rs new file mode 100644 index 000000000000..89eb5b38a093 --- /dev/null +++ b/pac/atsamc20g/src/dmac/crcchksum.rs @@ -0,0 +1,103 @@ +#[doc = "Register `CRCCHKSUM` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CRCCHKSUM` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CRCCHKSUM` reader - CRC Checksum"] +pub struct CRCCHKSUM_R(crate::FieldReader); +impl CRCCHKSUM_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CRCCHKSUM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CRCCHKSUM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCCHKSUM` writer - CRC Checksum"] +pub struct CRCCHKSUM_W<'a> { + w: &'a mut W, +} +impl<'a> CRCCHKSUM_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - CRC Checksum"] + #[inline(always)] + pub fn crcchksum(&self) -> CRCCHKSUM_R { + CRCCHKSUM_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - CRC Checksum"] + #[inline(always)] + pub fn crcchksum(&mut self) -> CRCCHKSUM_W { + CRCCHKSUM_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CRC Checksum\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [crcchksum](index.html) module"] +pub struct CRCCHKSUM_SPEC; +impl crate::RegisterSpec for CRCCHKSUM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [crcchksum::R](R) reader structure"] +impl crate::Readable for CRCCHKSUM_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [crcchksum::W](W) writer structure"] +impl crate::Writable for CRCCHKSUM_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CRCCHKSUM to value 0"] +impl crate::Resettable for CRCCHKSUM_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/dmac/crcctrl.rs b/pac/atsamc20g/src/dmac/crcctrl.rs new file mode 100644 index 000000000000..b8daf7b8259d --- /dev/null +++ b/pac/atsamc20g/src/dmac/crcctrl.rs @@ -0,0 +1,337 @@ +#[doc = "Register `CRCCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CRCCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "CRC Beat Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CRCBEATSIZE_A { + #[doc = "0: 8-bit bus transfer"] + BYTE = 0, + #[doc = "1: 16-bit bus transfer"] + HWORD = 1, + #[doc = "2: 32-bit bus transfer"] + WORD = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CRCBEATSIZE_A) -> Self { + variant as _ + } +} +#[doc = "Field `CRCBEATSIZE` reader - CRC Beat Size"] +pub struct CRCBEATSIZE_R(crate::FieldReader); +impl CRCBEATSIZE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CRCBEATSIZE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CRCBEATSIZE_A::BYTE), + 1 => Some(CRCBEATSIZE_A::HWORD), + 2 => Some(CRCBEATSIZE_A::WORD), + _ => None, + } + } + #[doc = "Checks if the value of the field is `BYTE`"] + #[inline(always)] + pub fn is_byte(&self) -> bool { + **self == CRCBEATSIZE_A::BYTE + } + #[doc = "Checks if the value of the field is `HWORD`"] + #[inline(always)] + pub fn is_hword(&self) -> bool { + **self == CRCBEATSIZE_A::HWORD + } + #[doc = "Checks if the value of the field is `WORD`"] + #[inline(always)] + pub fn is_word(&self) -> bool { + **self == CRCBEATSIZE_A::WORD + } +} +impl core::ops::Deref for CRCBEATSIZE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCBEATSIZE` writer - CRC Beat Size"] +pub struct CRCBEATSIZE_W<'a> { + w: &'a mut W, +} +impl<'a> CRCBEATSIZE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CRCBEATSIZE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8-bit bus transfer"] + #[inline(always)] + pub fn byte(self) -> &'a mut W { + self.variant(CRCBEATSIZE_A::BYTE) + } + #[doc = "16-bit bus transfer"] + #[inline(always)] + pub fn hword(self) -> &'a mut W { + self.variant(CRCBEATSIZE_A::HWORD) + } + #[doc = "32-bit bus transfer"] + #[inline(always)] + pub fn word(self) -> &'a mut W { + self.variant(CRCBEATSIZE_A::WORD) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u16 & 0x03); + self.w + } +} +#[doc = "CRC Polynomial Type\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CRCPOLY_A { + #[doc = "0: CRC-16 (CRC-CCITT)"] + CRC16 = 0, + #[doc = "1: CRC32 (IEEE 802.3)"] + CRC32 = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CRCPOLY_A) -> Self { + variant as _ + } +} +#[doc = "Field `CRCPOLY` reader - CRC Polynomial Type"] +pub struct CRCPOLY_R(crate::FieldReader); +impl CRCPOLY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CRCPOLY_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CRCPOLY_A::CRC16), + 1 => Some(CRCPOLY_A::CRC32), + _ => None, + } + } + #[doc = "Checks if the value of the field is `CRC16`"] + #[inline(always)] + pub fn is_crc16(&self) -> bool { + **self == CRCPOLY_A::CRC16 + } + #[doc = "Checks if the value of the field is `CRC32`"] + #[inline(always)] + pub fn is_crc32(&self) -> bool { + **self == CRCPOLY_A::CRC32 + } +} +impl core::ops::Deref for CRCPOLY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCPOLY` writer - CRC Polynomial Type"] +pub struct CRCPOLY_W<'a> { + w: &'a mut W, +} +impl<'a> CRCPOLY_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CRCPOLY_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "CRC-16 (CRC-CCITT)"] + #[inline(always)] + pub fn crc16(self) -> &'a mut W { + self.variant(CRCPOLY_A::CRC16) + } + #[doc = "CRC32 (IEEE 802.3)"] + #[inline(always)] + pub fn crc32(self) -> &'a mut W { + self.variant(CRCPOLY_A::CRC32) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u16 & 0x03) << 2); + self.w + } +} +#[doc = "CRC Input Source\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CRCSRC_A { + #[doc = "0: No action"] + NOACT = 0, + #[doc = "1: I/O interface"] + IO = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CRCSRC_A) -> Self { + variant as _ + } +} +#[doc = "Field `CRCSRC` reader - CRC Input Source"] +pub struct CRCSRC_R(crate::FieldReader); +impl CRCSRC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CRCSRC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CRCSRC_A::NOACT), + 1 => Some(CRCSRC_A::IO), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NOACT`"] + #[inline(always)] + pub fn is_noact(&self) -> bool { + **self == CRCSRC_A::NOACT + } + #[doc = "Checks if the value of the field is `IO`"] + #[inline(always)] + pub fn is_io(&self) -> bool { + **self == CRCSRC_A::IO + } +} +impl core::ops::Deref for CRCSRC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCSRC` writer - CRC Input Source"] +pub struct CRCSRC_W<'a> { + w: &'a mut W, +} +impl<'a> CRCSRC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CRCSRC_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn noact(self) -> &'a mut W { + self.variant(CRCSRC_A::NOACT) + } + #[doc = "I/O interface"] + #[inline(always)] + pub fn io(self) -> &'a mut W { + self.variant(CRCSRC_A::IO) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 8)) | ((value as u16 & 0x3f) << 8); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - CRC Beat Size"] + #[inline(always)] + pub fn crcbeatsize(&self) -> CRCBEATSIZE_R { + CRCBEATSIZE_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bits 2:3 - CRC Polynomial Type"] + #[inline(always)] + pub fn crcpoly(&self) -> CRCPOLY_R { + CRCPOLY_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bits 8:13 - CRC Input Source"] + #[inline(always)] + pub fn crcsrc(&self) -> CRCSRC_R { + CRCSRC_R::new(((self.bits >> 8) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - CRC Beat Size"] + #[inline(always)] + pub fn crcbeatsize(&mut self) -> CRCBEATSIZE_W { + CRCBEATSIZE_W { w: self } + } + #[doc = "Bits 2:3 - CRC Polynomial Type"] + #[inline(always)] + pub fn crcpoly(&mut self) -> CRCPOLY_W { + CRCPOLY_W { w: self } + } + #[doc = "Bits 8:13 - CRC Input Source"] + #[inline(always)] + pub fn crcsrc(&mut self) -> CRCSRC_W { + CRCSRC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CRC Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [crcctrl](index.html) module"] +pub struct CRCCTRL_SPEC; +impl crate::RegisterSpec for CRCCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [crcctrl::R](R) reader structure"] +impl crate::Readable for CRCCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [crcctrl::W](W) writer structure"] +impl crate::Writable for CRCCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CRCCTRL to value 0"] +impl crate::Resettable for CRCCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/dmac/crcdatain.rs b/pac/atsamc20g/src/dmac/crcdatain.rs new file mode 100644 index 000000000000..ca0879a12136 --- /dev/null +++ b/pac/atsamc20g/src/dmac/crcdatain.rs @@ -0,0 +1,103 @@ +#[doc = "Register `CRCDATAIN` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CRCDATAIN` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CRCDATAIN` reader - CRC Data Input"] +pub struct CRCDATAIN_R(crate::FieldReader); +impl CRCDATAIN_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CRCDATAIN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CRCDATAIN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCDATAIN` writer - CRC Data Input"] +pub struct CRCDATAIN_W<'a> { + w: &'a mut W, +} +impl<'a> CRCDATAIN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - CRC Data Input"] + #[inline(always)] + pub fn crcdatain(&self) -> CRCDATAIN_R { + CRCDATAIN_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - CRC Data Input"] + #[inline(always)] + pub fn crcdatain(&mut self) -> CRCDATAIN_W { + CRCDATAIN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CRC Data Input\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [crcdatain](index.html) module"] +pub struct CRCDATAIN_SPEC; +impl crate::RegisterSpec for CRCDATAIN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [crcdatain::R](R) reader structure"] +impl crate::Readable for CRCDATAIN_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [crcdatain::W](W) writer structure"] +impl crate::Writable for CRCDATAIN_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CRCDATAIN to value 0"] +impl crate::Resettable for CRCDATAIN_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/dmac/crcstatus.rs b/pac/atsamc20g/src/dmac/crcstatus.rs new file mode 100644 index 000000000000..a132e9d5cd03 --- /dev/null +++ b/pac/atsamc20g/src/dmac/crcstatus.rs @@ -0,0 +1,160 @@ +#[doc = "Register `CRCSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CRCSTATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CRCBUSY` reader - CRC Module Busy"] +pub struct CRCBUSY_R(crate::FieldReader); +impl CRCBUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CRCBUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CRCBUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCBUSY` writer - CRC Module Busy"] +pub struct CRCBUSY_W<'a> { + w: &'a mut W, +} +impl<'a> CRCBUSY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `CRCZERO` reader - CRC Zero"] +pub struct CRCZERO_R(crate::FieldReader); +impl CRCZERO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CRCZERO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CRCZERO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCZERO` writer - CRC Zero"] +pub struct CRCZERO_W<'a> { + w: &'a mut W, +} +impl<'a> CRCZERO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - CRC Module Busy"] + #[inline(always)] + pub fn crcbusy(&self) -> CRCBUSY_R { + CRCBUSY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - CRC Zero"] + #[inline(always)] + pub fn crczero(&self) -> CRCZERO_R { + CRCZERO_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - CRC Module Busy"] + #[inline(always)] + pub fn crcbusy(&mut self) -> CRCBUSY_W { + CRCBUSY_W { w: self } + } + #[doc = "Bit 1 - CRC Zero"] + #[inline(always)] + pub fn crczero(&mut self) -> CRCZERO_W { + CRCZERO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CRC Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [crcstatus](index.html) module"] +pub struct CRCSTATUS_SPEC; +impl crate::RegisterSpec for CRCSTATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [crcstatus::R](R) reader structure"] +impl crate::Readable for CRCSTATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [crcstatus::W](W) writer structure"] +impl crate::Writable for CRCSTATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CRCSTATUS to value 0"] +impl crate::Resettable for CRCSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/dmac/ctrl.rs b/pac/atsamc20g/src/dmac/ctrl.rs new file mode 100644 index 000000000000..fabae9d82a6c --- /dev/null +++ b/pac/atsamc20g/src/dmac/ctrl.rs @@ -0,0 +1,395 @@ +#[doc = "Register `CTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `DMAENABLE` reader - DMA Enable"] +pub struct DMAENABLE_R(crate::FieldReader); +impl DMAENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DMAENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DMAENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DMAENABLE` writer - DMA Enable"] +pub struct DMAENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> DMAENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CRCENABLE` reader - CRC Enable"] +pub struct CRCENABLE_R(crate::FieldReader); +impl CRCENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CRCENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CRCENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCENABLE` writer - CRC Enable"] +pub struct CRCENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> CRCENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `LVLEN0` reader - Priority Level 0 Enable"] +pub struct LVLEN0_R(crate::FieldReader); +impl LVLEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LVLEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLEN0` writer - Priority Level 0 Enable"] +pub struct LVLEN0_W<'a> { + w: &'a mut W, +} +impl<'a> LVLEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `LVLEN1` reader - Priority Level 1 Enable"] +pub struct LVLEN1_R(crate::FieldReader); +impl LVLEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LVLEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLEN1` writer - Priority Level 1 Enable"] +pub struct LVLEN1_W<'a> { + w: &'a mut W, +} +impl<'a> LVLEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `LVLEN2` reader - Priority Level 2 Enable"] +pub struct LVLEN2_R(crate::FieldReader); +impl LVLEN2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LVLEN2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEN2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLEN2` writer - Priority Level 2 Enable"] +pub struct LVLEN2_W<'a> { + w: &'a mut W, +} +impl<'a> LVLEN2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u16 & 0x01) << 10); + self.w + } +} +#[doc = "Field `LVLEN3` reader - Priority Level 3 Enable"] +pub struct LVLEN3_R(crate::FieldReader); +impl LVLEN3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LVLEN3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEN3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLEN3` writer - Priority Level 3 Enable"] +pub struct LVLEN3_W<'a> { + w: &'a mut W, +} +impl<'a> LVLEN3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u16 & 0x01) << 11); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - DMA Enable"] + #[inline(always)] + pub fn dmaenable(&self) -> DMAENABLE_R { + DMAENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - CRC Enable"] + #[inline(always)] + pub fn crcenable(&self) -> CRCENABLE_R { + CRCENABLE_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 8 - Priority Level 0 Enable"] + #[inline(always)] + pub fn lvlen0(&self) -> LVLEN0_R { + LVLEN0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Priority Level 1 Enable"] + #[inline(always)] + pub fn lvlen1(&self) -> LVLEN1_R { + LVLEN1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Priority Level 2 Enable"] + #[inline(always)] + pub fn lvlen2(&self) -> LVLEN2_R { + LVLEN2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Priority Level 3 Enable"] + #[inline(always)] + pub fn lvlen3(&self) -> LVLEN3_R { + LVLEN3_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - DMA Enable"] + #[inline(always)] + pub fn dmaenable(&mut self) -> DMAENABLE_W { + DMAENABLE_W { w: self } + } + #[doc = "Bit 2 - CRC Enable"] + #[inline(always)] + pub fn crcenable(&mut self) -> CRCENABLE_W { + CRCENABLE_W { w: self } + } + #[doc = "Bit 8 - Priority Level 0 Enable"] + #[inline(always)] + pub fn lvlen0(&mut self) -> LVLEN0_W { + LVLEN0_W { w: self } + } + #[doc = "Bit 9 - Priority Level 1 Enable"] + #[inline(always)] + pub fn lvlen1(&mut self) -> LVLEN1_W { + LVLEN1_W { w: self } + } + #[doc = "Bit 10 - Priority Level 2 Enable"] + #[inline(always)] + pub fn lvlen2(&mut self) -> LVLEN2_W { + LVLEN2_W { w: self } + } + #[doc = "Bit 11 - Priority Level 3 Enable"] + #[inline(always)] + pub fn lvlen3(&mut self) -> LVLEN3_W { + LVLEN3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"] +pub struct CTRL_SPEC; +impl crate::RegisterSpec for CTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrl::R](R) reader structure"] +impl crate::Readable for CTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"] +impl crate::Writable for CTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/dmac/dbgctrl.rs b/pac/atsamc20g/src/dmac/dbgctrl.rs new file mode 100644 index 000000000000..53636eb2b339 --- /dev/null +++ b/pac/atsamc20g/src/dmac/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Debug Run"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Debug Run"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/dmac/intpend.rs b/pac/atsamc20g/src/dmac/intpend.rs new file mode 100644 index 000000000000..1988b30a190b --- /dev/null +++ b/pac/atsamc20g/src/dmac/intpend.rs @@ -0,0 +1,385 @@ +#[doc = "Register `INTPEND` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTPEND` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ID` reader - Channel ID"] +pub struct ID_R(crate::FieldReader); +impl ID_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ID_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ID_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ID` writer - Channel ID"] +pub struct ID_W<'a> { + w: &'a mut W, +} +impl<'a> ID_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u16 & 0x07); + self.w + } +} +#[doc = "Field `TERR` reader - Transfer Error"] +pub struct TERR_R(crate::FieldReader); +impl TERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TERR` writer - Transfer Error"] +pub struct TERR_W<'a> { + w: &'a mut W, +} +impl<'a> TERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `TCMPL` reader - Transfer Complete"] +pub struct TCMPL_R(crate::FieldReader); +impl TCMPL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCMPL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCMPL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCMPL` writer - Transfer Complete"] +pub struct TCMPL_W<'a> { + w: &'a mut W, +} +impl<'a> TCMPL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `SUSP` reader - Channel Suspend"] +pub struct SUSP_R(crate::FieldReader); +impl SUSP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SUSP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SUSP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SUSP` writer - Channel Suspend"] +pub struct SUSP_W<'a> { + w: &'a mut W, +} +impl<'a> SUSP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u16 & 0x01) << 10); + self.w + } +} +#[doc = "Field `FERR` reader - Fetch Error"] +pub struct FERR_R(crate::FieldReader); +impl FERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FERR` writer - Fetch Error"] +pub struct FERR_W<'a> { + w: &'a mut W, +} +impl<'a> FERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u16 & 0x01) << 13); + self.w + } +} +#[doc = "Field `BUSY` reader - Busy"] +pub struct BUSY_R(crate::FieldReader); +impl BUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSY` writer - Busy"] +pub struct BUSY_W<'a> { + w: &'a mut W, +} +impl<'a> BUSY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u16 & 0x01) << 14); + self.w + } +} +#[doc = "Field `PEND` reader - Pending"] +pub struct PEND_R(crate::FieldReader); +impl PEND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEND` writer - Pending"] +pub struct PEND_W<'a> { + w: &'a mut W, +} +impl<'a> PEND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Channel ID"] + #[inline(always)] + pub fn id(&self) -> ID_R { + ID_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 8 - Transfer Error"] + #[inline(always)] + pub fn terr(&self) -> TERR_R { + TERR_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Transfer Complete"] + #[inline(always)] + pub fn tcmpl(&self) -> TCMPL_R { + TCMPL_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Channel Suspend"] + #[inline(always)] + pub fn susp(&self) -> SUSP_R { + SUSP_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 13 - Fetch Error"] + #[inline(always)] + pub fn ferr(&self) -> FERR_R { + FERR_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Busy"] + #[inline(always)] + pub fn busy(&self) -> BUSY_R { + BUSY_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Pending"] + #[inline(always)] + pub fn pend(&self) -> PEND_R { + PEND_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Channel ID"] + #[inline(always)] + pub fn id(&mut self) -> ID_W { + ID_W { w: self } + } + #[doc = "Bit 8 - Transfer Error"] + #[inline(always)] + pub fn terr(&mut self) -> TERR_W { + TERR_W { w: self } + } + #[doc = "Bit 9 - Transfer Complete"] + #[inline(always)] + pub fn tcmpl(&mut self) -> TCMPL_W { + TCMPL_W { w: self } + } + #[doc = "Bit 10 - Channel Suspend"] + #[inline(always)] + pub fn susp(&mut self) -> SUSP_W { + SUSP_W { w: self } + } + #[doc = "Bit 13 - Fetch Error"] + #[inline(always)] + pub fn ferr(&mut self) -> FERR_W { + FERR_W { w: self } + } + #[doc = "Bit 14 - Busy"] + #[inline(always)] + pub fn busy(&mut self) -> BUSY_W { + BUSY_W { w: self } + } + #[doc = "Bit 15 - Pending"] + #[inline(always)] + pub fn pend(&mut self) -> PEND_W { + PEND_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Pending\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intpend](index.html) module"] +pub struct INTPEND_SPEC; +impl crate::RegisterSpec for INTPEND_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intpend::R](R) reader structure"] +impl crate::Readable for INTPEND_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intpend::W](W) writer structure"] +impl crate::Writable for INTPEND_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTPEND to value 0"] +impl crate::Resettable for INTPEND_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/dmac/intstatus.rs b/pac/atsamc20g/src/dmac/intstatus.rs new file mode 100644 index 000000000000..4e6617d96bef --- /dev/null +++ b/pac/atsamc20g/src/dmac/intstatus.rs @@ -0,0 +1,153 @@ +#[doc = "Register `INTSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `CHINT0` reader - Channel 0 Pending Interrupt"] +pub struct CHINT0_R(crate::FieldReader); +impl CHINT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT1` reader - Channel 1 Pending Interrupt"] +pub struct CHINT1_R(crate::FieldReader); +impl CHINT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT2` reader - Channel 2 Pending Interrupt"] +pub struct CHINT2_R(crate::FieldReader); +impl CHINT2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT3` reader - Channel 3 Pending Interrupt"] +pub struct CHINT3_R(crate::FieldReader); +impl CHINT3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT4` reader - Channel 4 Pending Interrupt"] +pub struct CHINT4_R(crate::FieldReader); +impl CHINT4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT5` reader - Channel 5 Pending Interrupt"] +pub struct CHINT5_R(crate::FieldReader); +impl CHINT5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Channel 0 Pending Interrupt"] + #[inline(always)] + pub fn chint0(&self) -> CHINT0_R { + CHINT0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel 1 Pending Interrupt"] + #[inline(always)] + pub fn chint1(&self) -> CHINT1_R { + CHINT1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel 2 Pending Interrupt"] + #[inline(always)] + pub fn chint2(&self) -> CHINT2_R { + CHINT2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Channel 3 Pending Interrupt"] + #[inline(always)] + pub fn chint3(&self) -> CHINT3_R { + CHINT3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Channel 4 Pending Interrupt"] + #[inline(always)] + pub fn chint4(&self) -> CHINT4_R { + CHINT4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Channel 5 Pending Interrupt"] + #[inline(always)] + pub fn chint5(&self) -> CHINT5_R { + CHINT5_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +#[doc = "Interrupt Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intstatus](index.html) module"] +pub struct INTSTATUS_SPEC; +impl crate::RegisterSpec for INTSTATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intstatus::R](R) reader structure"] +impl crate::Readable for INTSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets INTSTATUS to value 0"] +impl crate::Resettable for INTSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/dmac/pendch.rs b/pac/atsamc20g/src/dmac/pendch.rs new file mode 100644 index 000000000000..1ffc2ca607b1 --- /dev/null +++ b/pac/atsamc20g/src/dmac/pendch.rs @@ -0,0 +1,153 @@ +#[doc = "Register `PENDCH` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PENDCH0` reader - Pending Channel 0"] +pub struct PENDCH0_R(crate::FieldReader); +impl PENDCH0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH1` reader - Pending Channel 1"] +pub struct PENDCH1_R(crate::FieldReader); +impl PENDCH1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH2` reader - Pending Channel 2"] +pub struct PENDCH2_R(crate::FieldReader); +impl PENDCH2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH3` reader - Pending Channel 3"] +pub struct PENDCH3_R(crate::FieldReader); +impl PENDCH3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH4` reader - Pending Channel 4"] +pub struct PENDCH4_R(crate::FieldReader); +impl PENDCH4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH5` reader - Pending Channel 5"] +pub struct PENDCH5_R(crate::FieldReader); +impl PENDCH5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Pending Channel 0"] + #[inline(always)] + pub fn pendch0(&self) -> PENDCH0_R { + PENDCH0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Pending Channel 1"] + #[inline(always)] + pub fn pendch1(&self) -> PENDCH1_R { + PENDCH1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Pending Channel 2"] + #[inline(always)] + pub fn pendch2(&self) -> PENDCH2_R { + PENDCH2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Pending Channel 3"] + #[inline(always)] + pub fn pendch3(&self) -> PENDCH3_R { + PENDCH3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Pending Channel 4"] + #[inline(always)] + pub fn pendch4(&self) -> PENDCH4_R { + PENDCH4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Pending Channel 5"] + #[inline(always)] + pub fn pendch5(&self) -> PENDCH5_R { + PENDCH5_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +#[doc = "Pending Channels\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pendch](index.html) module"] +pub struct PENDCH_SPEC; +impl crate::RegisterSpec for PENDCH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pendch::R](R) reader structure"] +impl crate::Readable for PENDCH_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PENDCH to value 0"] +impl crate::Resettable for PENDCH_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/dmac/prictrl0.rs b/pac/atsamc20g/src/dmac/prictrl0.rs new file mode 100644 index 000000000000..64324f7f2493 --- /dev/null +++ b/pac/atsamc20g/src/dmac/prictrl0.rs @@ -0,0 +1,449 @@ +#[doc = "Register `PRICTRL0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PRICTRL0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `LVLPRI0` reader - Level 0 Channel Priority Number"] +pub struct LVLPRI0_R(crate::FieldReader); +impl LVLPRI0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LVLPRI0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLPRI0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLPRI0` writer - Level 0 Channel Priority Number"] +pub struct LVLPRI0_W<'a> { + w: &'a mut W, +} +impl<'a> LVLPRI0_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Level 0 Round-Robin Scheduling Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RRLVLEN0_A { + #[doc = "0: Static arbitration scheme for channels with level 3 priority"] + STATIC_LVL = 0, + #[doc = "1: Round-robin arbitration scheme for channels with level 3 priority"] + ROUND_ROBIN_LVL = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RRLVLEN0_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RRLVLEN0` reader - Level 0 Round-Robin Scheduling Enable"] +pub struct RRLVLEN0_R(crate::FieldReader); +impl RRLVLEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RRLVLEN0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RRLVLEN0_A { + match self.bits { + false => RRLVLEN0_A::STATIC_LVL, + true => RRLVLEN0_A::ROUND_ROBIN_LVL, + } + } + #[doc = "Checks if the value of the field is `STATIC_LVL`"] + #[inline(always)] + pub fn is_static_lvl(&self) -> bool { + **self == RRLVLEN0_A::STATIC_LVL + } + #[doc = "Checks if the value of the field is `ROUND_ROBIN_LVL`"] + #[inline(always)] + pub fn is_round_robin_lvl(&self) -> bool { + **self == RRLVLEN0_A::ROUND_ROBIN_LVL + } +} +impl core::ops::Deref for RRLVLEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RRLVLEN0` writer - Level 0 Round-Robin Scheduling Enable"] +pub struct RRLVLEN0_W<'a> { + w: &'a mut W, +} +impl<'a> RRLVLEN0_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RRLVLEN0_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Static arbitration scheme for channels with level 3 priority"] + #[inline(always)] + pub fn static_lvl(self) -> &'a mut W { + self.variant(RRLVLEN0_A::STATIC_LVL) + } + #[doc = "Round-robin arbitration scheme for channels with level 3 priority"] + #[inline(always)] + pub fn round_robin_lvl(self) -> &'a mut W { + self.variant(RRLVLEN0_A::ROUND_ROBIN_LVL) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `LVLPRI1` reader - Level 1 Channel Priority Number"] +pub struct LVLPRI1_R(crate::FieldReader); +impl LVLPRI1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LVLPRI1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLPRI1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLPRI1` writer - Level 1 Channel Priority Number"] +pub struct LVLPRI1_W<'a> { + w: &'a mut W, +} +impl<'a> LVLPRI1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +#[doc = "Field `RRLVLEN1` reader - Level 1 Round-Robin Scheduling Enable"] +pub struct RRLVLEN1_R(crate::FieldReader); +impl RRLVLEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RRLVLEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RRLVLEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RRLVLEN1` writer - Level 1 Round-Robin Scheduling Enable"] +pub struct RRLVLEN1_W<'a> { + w: &'a mut W, +} +impl<'a> RRLVLEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `LVLPRI2` reader - Level 2 Channel Priority Number"] +pub struct LVLPRI2_R(crate::FieldReader); +impl LVLPRI2_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LVLPRI2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLPRI2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLPRI2` writer - Level 2 Channel Priority Number"] +pub struct LVLPRI2_W<'a> { + w: &'a mut W, +} +impl<'a> LVLPRI2_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 16)) | ((value as u32 & 0x07) << 16); + self.w + } +} +#[doc = "Field `RRLVLEN2` reader - Level 2 Round-Robin Scheduling Enable"] +pub struct RRLVLEN2_R(crate::FieldReader); +impl RRLVLEN2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RRLVLEN2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RRLVLEN2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RRLVLEN2` writer - Level 2 Round-Robin Scheduling Enable"] +pub struct RRLVLEN2_W<'a> { + w: &'a mut W, +} +impl<'a> RRLVLEN2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `LVLPRI3` reader - Level 3 Channel Priority Number"] +pub struct LVLPRI3_R(crate::FieldReader); +impl LVLPRI3_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LVLPRI3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLPRI3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLPRI3` writer - Level 3 Channel Priority Number"] +pub struct LVLPRI3_W<'a> { + w: &'a mut W, +} +impl<'a> LVLPRI3_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 24)) | ((value as u32 & 0x07) << 24); + self.w + } +} +#[doc = "Field `RRLVLEN3` reader - Level 3 Round-Robin Scheduling Enable"] +pub struct RRLVLEN3_R(crate::FieldReader); +impl RRLVLEN3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RRLVLEN3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RRLVLEN3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RRLVLEN3` writer - Level 3 Round-Robin Scheduling Enable"] +pub struct RRLVLEN3_W<'a> { + w: &'a mut W, +} +impl<'a> RRLVLEN3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Level 0 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri0(&self) -> LVLPRI0_R { + LVLPRI0_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 7 - Level 0 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen0(&self) -> RRLVLEN0_R { + RRLVLEN0_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Level 1 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri1(&self) -> LVLPRI1_R { + LVLPRI1_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 15 - Level 1 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen1(&self) -> RRLVLEN1_R { + RRLVLEN1_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:18 - Level 2 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri2(&self) -> LVLPRI2_R { + LVLPRI2_R::new(((self.bits >> 16) & 0x07) as u8) + } + #[doc = "Bit 23 - Level 2 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen2(&self) -> RRLVLEN2_R { + RRLVLEN2_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bits 24:26 - Level 3 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri3(&self) -> LVLPRI3_R { + LVLPRI3_R::new(((self.bits >> 24) & 0x07) as u8) + } + #[doc = "Bit 31 - Level 3 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen3(&self) -> RRLVLEN3_R { + RRLVLEN3_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Level 0 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri0(&mut self) -> LVLPRI0_W { + LVLPRI0_W { w: self } + } + #[doc = "Bit 7 - Level 0 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen0(&mut self) -> RRLVLEN0_W { + RRLVLEN0_W { w: self } + } + #[doc = "Bits 8:10 - Level 1 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri1(&mut self) -> LVLPRI1_W { + LVLPRI1_W { w: self } + } + #[doc = "Bit 15 - Level 1 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen1(&mut self) -> RRLVLEN1_W { + RRLVLEN1_W { w: self } + } + #[doc = "Bits 16:18 - Level 2 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri2(&mut self) -> LVLPRI2_W { + LVLPRI2_W { w: self } + } + #[doc = "Bit 23 - Level 2 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen2(&mut self) -> RRLVLEN2_W { + RRLVLEN2_W { w: self } + } + #[doc = "Bits 24:26 - Level 3 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri3(&mut self) -> LVLPRI3_W { + LVLPRI3_W { w: self } + } + #[doc = "Bit 31 - Level 3 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen3(&mut self) -> RRLVLEN3_W { + RRLVLEN3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Priority Control 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [prictrl0](index.html) module"] +pub struct PRICTRL0_SPEC; +impl crate::RegisterSpec for PRICTRL0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [prictrl0::R](R) reader structure"] +impl crate::Readable for PRICTRL0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [prictrl0::W](W) writer structure"] +impl crate::Writable for PRICTRL0_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PRICTRL0 to value 0"] +impl crate::Resettable for PRICTRL0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/dmac/qosctrl.rs b/pac/atsamc20g/src/dmac/qosctrl.rs new file mode 100644 index 000000000000..016fcaa221ef --- /dev/null +++ b/pac/atsamc20g/src/dmac/qosctrl.rs @@ -0,0 +1,402 @@ +#[doc = "Register `QOSCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `QOSCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Write-Back Quality of Service\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WRBQOS_A { + #[doc = "0: Background (no sensitive operation)"] + DISABLE = 0, + #[doc = "1: Sensitive Bandwidth"] + LOW = 1, + #[doc = "2: Sensitive Latency"] + MEDIUM = 2, + #[doc = "3: Critical Latency"] + HIGH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WRBQOS_A) -> Self { + variant as _ + } +} +#[doc = "Field `WRBQOS` reader - Write-Back Quality of Service"] +pub struct WRBQOS_R(crate::FieldReader); +impl WRBQOS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WRBQOS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> WRBQOS_A { + match self.bits { + 0 => WRBQOS_A::DISABLE, + 1 => WRBQOS_A::LOW, + 2 => WRBQOS_A::MEDIUM, + 3 => WRBQOS_A::HIGH, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == WRBQOS_A::DISABLE + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == WRBQOS_A::LOW + } + #[doc = "Checks if the value of the field is `MEDIUM`"] + #[inline(always)] + pub fn is_medium(&self) -> bool { + **self == WRBQOS_A::MEDIUM + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == WRBQOS_A::HIGH + } +} +impl core::ops::Deref for WRBQOS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WRBQOS` writer - Write-Back Quality of Service"] +pub struct WRBQOS_W<'a> { + w: &'a mut W, +} +impl<'a> WRBQOS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WRBQOS_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Background (no sensitive operation)"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(WRBQOS_A::DISABLE) + } + #[doc = "Sensitive Bandwidth"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(WRBQOS_A::LOW) + } + #[doc = "Sensitive Latency"] + #[inline(always)] + pub fn medium(self) -> &'a mut W { + self.variant(WRBQOS_A::MEDIUM) + } + #[doc = "Critical Latency"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(WRBQOS_A::HIGH) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u8 & 0x03); + self.w + } +} +#[doc = "Fetch Quality of Service\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FQOS_A { + #[doc = "0: Background (no sensitive operation)"] + DISABLE = 0, + #[doc = "1: Sensitive Bandwidth"] + LOW = 1, + #[doc = "2: Sensitive Latency"] + MEDIUM = 2, + #[doc = "3: Critical Latency"] + HIGH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FQOS_A) -> Self { + variant as _ + } +} +#[doc = "Field `FQOS` reader - Fetch Quality of Service"] +pub struct FQOS_R(crate::FieldReader); +impl FQOS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FQOS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FQOS_A { + match self.bits { + 0 => FQOS_A::DISABLE, + 1 => FQOS_A::LOW, + 2 => FQOS_A::MEDIUM, + 3 => FQOS_A::HIGH, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == FQOS_A::DISABLE + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == FQOS_A::LOW + } + #[doc = "Checks if the value of the field is `MEDIUM`"] + #[inline(always)] + pub fn is_medium(&self) -> bool { + **self == FQOS_A::MEDIUM + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == FQOS_A::HIGH + } +} +impl core::ops::Deref for FQOS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FQOS` writer - Fetch Quality of Service"] +pub struct FQOS_W<'a> { + w: &'a mut W, +} +impl<'a> FQOS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FQOS_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Background (no sensitive operation)"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(FQOS_A::DISABLE) + } + #[doc = "Sensitive Bandwidth"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(FQOS_A::LOW) + } + #[doc = "Sensitive Latency"] + #[inline(always)] + pub fn medium(self) -> &'a mut W { + self.variant(FQOS_A::MEDIUM) + } + #[doc = "Critical Latency"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(FQOS_A::HIGH) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u8 & 0x03) << 2); + self.w + } +} +#[doc = "Data Transfer Quality of Service\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DQOS_A { + #[doc = "0: Background (no sensitive operation)"] + DISABLE = 0, + #[doc = "1: Sensitive Bandwidth"] + LOW = 1, + #[doc = "2: Sensitive Latency"] + MEDIUM = 2, + #[doc = "3: Critical Latency"] + HIGH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DQOS_A) -> Self { + variant as _ + } +} +#[doc = "Field `DQOS` reader - Data Transfer Quality of Service"] +pub struct DQOS_R(crate::FieldReader); +impl DQOS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DQOS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DQOS_A { + match self.bits { + 0 => DQOS_A::DISABLE, + 1 => DQOS_A::LOW, + 2 => DQOS_A::MEDIUM, + 3 => DQOS_A::HIGH, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == DQOS_A::DISABLE + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == DQOS_A::LOW + } + #[doc = "Checks if the value of the field is `MEDIUM`"] + #[inline(always)] + pub fn is_medium(&self) -> bool { + **self == DQOS_A::MEDIUM + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == DQOS_A::HIGH + } +} +impl core::ops::Deref for DQOS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DQOS` writer - Data Transfer Quality of Service"] +pub struct DQOS_W<'a> { + w: &'a mut W, +} +impl<'a> DQOS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DQOS_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Background (no sensitive operation)"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(DQOS_A::DISABLE) + } + #[doc = "Sensitive Bandwidth"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(DQOS_A::LOW) + } + #[doc = "Sensitive Latency"] + #[inline(always)] + pub fn medium(self) -> &'a mut W { + self.variant(DQOS_A::MEDIUM) + } + #[doc = "Critical Latency"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(DQOS_A::HIGH) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u8 & 0x03) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Write-Back Quality of Service"] + #[inline(always)] + pub fn wrbqos(&self) -> WRBQOS_R { + WRBQOS_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bits 2:3 - Fetch Quality of Service"] + #[inline(always)] + pub fn fqos(&self) -> FQOS_R { + FQOS_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bits 4:5 - Data Transfer Quality of Service"] + #[inline(always)] + pub fn dqos(&self) -> DQOS_R { + DQOS_R::new(((self.bits >> 4) & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Write-Back Quality of Service"] + #[inline(always)] + pub fn wrbqos(&mut self) -> WRBQOS_W { + WRBQOS_W { w: self } + } + #[doc = "Bits 2:3 - Fetch Quality of Service"] + #[inline(always)] + pub fn fqos(&mut self) -> FQOS_W { + FQOS_W { w: self } + } + #[doc = "Bits 4:5 - Data Transfer Quality of Service"] + #[inline(always)] + pub fn dqos(&mut self) -> DQOS_W { + DQOS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "QOS Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [qosctrl](index.html) module"] +pub struct QOSCTRL_SPEC; +impl crate::RegisterSpec for QOSCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [qosctrl::R](R) reader structure"] +impl crate::Readable for QOSCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [qosctrl::W](W) writer structure"] +impl crate::Writable for QOSCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets QOSCTRL to value 0x2a"] +impl crate::Resettable for QOSCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x2a + } +} diff --git a/pac/atsamc20g/src/dmac/swtrigctrl.rs b/pac/atsamc20g/src/dmac/swtrigctrl.rs new file mode 100644 index 000000000000..ada7d633a376 --- /dev/null +++ b/pac/atsamc20g/src/dmac/swtrigctrl.rs @@ -0,0 +1,348 @@ +#[doc = "Register `SWTRIGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SWTRIGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWTRIG0` reader - Channel 0 Software Trigger"] +pub struct SWTRIG0_R(crate::FieldReader); +impl SWTRIG0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG0` writer - Channel 0 Software Trigger"] +pub struct SWTRIG0_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `SWTRIG1` reader - Channel 1 Software Trigger"] +pub struct SWTRIG1_R(crate::FieldReader); +impl SWTRIG1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG1` writer - Channel 1 Software Trigger"] +pub struct SWTRIG1_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SWTRIG2` reader - Channel 2 Software Trigger"] +pub struct SWTRIG2_R(crate::FieldReader); +impl SWTRIG2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG2` writer - Channel 2 Software Trigger"] +pub struct SWTRIG2_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SWTRIG3` reader - Channel 3 Software Trigger"] +pub struct SWTRIG3_R(crate::FieldReader); +impl SWTRIG3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG3` writer - Channel 3 Software Trigger"] +pub struct SWTRIG3_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `SWTRIG4` reader - Channel 4 Software Trigger"] +pub struct SWTRIG4_R(crate::FieldReader); +impl SWTRIG4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG4` writer - Channel 4 Software Trigger"] +pub struct SWTRIG4_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `SWTRIG5` reader - Channel 5 Software Trigger"] +pub struct SWTRIG5_R(crate::FieldReader); +impl SWTRIG5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG5` writer - Channel 5 Software Trigger"] +pub struct SWTRIG5_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Channel 0 Software Trigger"] + #[inline(always)] + pub fn swtrig0(&self) -> SWTRIG0_R { + SWTRIG0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel 1 Software Trigger"] + #[inline(always)] + pub fn swtrig1(&self) -> SWTRIG1_R { + SWTRIG1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel 2 Software Trigger"] + #[inline(always)] + pub fn swtrig2(&self) -> SWTRIG2_R { + SWTRIG2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Channel 3 Software Trigger"] + #[inline(always)] + pub fn swtrig3(&self) -> SWTRIG3_R { + SWTRIG3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Channel 4 Software Trigger"] + #[inline(always)] + pub fn swtrig4(&self) -> SWTRIG4_R { + SWTRIG4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Channel 5 Software Trigger"] + #[inline(always)] + pub fn swtrig5(&self) -> SWTRIG5_R { + SWTRIG5_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel 0 Software Trigger"] + #[inline(always)] + pub fn swtrig0(&mut self) -> SWTRIG0_W { + SWTRIG0_W { w: self } + } + #[doc = "Bit 1 - Channel 1 Software Trigger"] + #[inline(always)] + pub fn swtrig1(&mut self) -> SWTRIG1_W { + SWTRIG1_W { w: self } + } + #[doc = "Bit 2 - Channel 2 Software Trigger"] + #[inline(always)] + pub fn swtrig2(&mut self) -> SWTRIG2_W { + SWTRIG2_W { w: self } + } + #[doc = "Bit 3 - Channel 3 Software Trigger"] + #[inline(always)] + pub fn swtrig3(&mut self) -> SWTRIG3_W { + SWTRIG3_W { w: self } + } + #[doc = "Bit 4 - Channel 4 Software Trigger"] + #[inline(always)] + pub fn swtrig4(&mut self) -> SWTRIG4_W { + SWTRIG4_W { w: self } + } + #[doc = "Bit 5 - Channel 5 Software Trigger"] + #[inline(always)] + pub fn swtrig5(&mut self) -> SWTRIG5_W { + SWTRIG5_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Software Trigger Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [swtrigctrl](index.html) module"] +pub struct SWTRIGCTRL_SPEC; +impl crate::RegisterSpec for SWTRIGCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [swtrigctrl::R](R) reader structure"] +impl crate::Readable for SWTRIGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [swtrigctrl::W](W) writer structure"] +impl crate::Writable for SWTRIGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SWTRIGCTRL to value 0"] +impl crate::Resettable for SWTRIGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/dmac/wrbaddr.rs b/pac/atsamc20g/src/dmac/wrbaddr.rs new file mode 100644 index 000000000000..ccf2a376b853 --- /dev/null +++ b/pac/atsamc20g/src/dmac/wrbaddr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `WRBADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WRBADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WRBADDR` reader - Write-Back Memory Base Address"] +pub struct WRBADDR_R(crate::FieldReader); +impl WRBADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + WRBADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WRBADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WRBADDR` writer - Write-Back Memory Base Address"] +pub struct WRBADDR_W<'a> { + w: &'a mut W, +} +impl<'a> WRBADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Write-Back Memory Base Address"] + #[inline(always)] + pub fn wrbaddr(&self) -> WRBADDR_R { + WRBADDR_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Write-Back Memory Base Address"] + #[inline(always)] + pub fn wrbaddr(&mut self) -> WRBADDR_W { + WRBADDR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Write-Back Memory Section Base Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wrbaddr](index.html) module"] +pub struct WRBADDR_SPEC; +impl crate::RegisterSpec for WRBADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [wrbaddr::R](R) reader structure"] +impl crate::Readable for WRBADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wrbaddr::W](W) writer structure"] +impl crate::Writable for WRBADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WRBADDR to value 0"] +impl crate::Resettable for WRBADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/dsu.rs b/pac/atsamc20g/src/dsu.rs new file mode 100644 index 000000000000..88324f764961 --- /dev/null +++ b/pac/atsamc20g/src/dsu.rs @@ -0,0 +1,163 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrl: crate::Reg, + #[doc = "0x01 - Status A"] + pub statusa: crate::Reg, + #[doc = "0x02 - Status B"] + pub statusb: crate::Reg, + #[doc = "0x03 - Status C"] + pub statusc: crate::Reg, + #[doc = "0x04 - Address"] + pub addr: crate::Reg, + #[doc = "0x08 - Length"] + pub length: crate::Reg, + #[doc = "0x0c - Data"] + pub data: crate::Reg, + #[doc = "0x10..0x18 - Debug Communication Channel n"] + pub dcc: [crate::Reg; 2], + #[doc = "0x18 - Device Identification"] + pub did: crate::Reg, + _reserved9: [u8; 0xd4], + #[doc = "0xf0..0xf8 - Device Configuration"] + pub dcfg: [crate::Reg; 2], + _reserved10: [u8; 0x0f08], + #[doc = "0x1000 - CoreSight ROM Table Entry 0"] + pub entry0: crate::Reg, + #[doc = "0x1004 - CoreSight ROM Table Entry 1"] + pub entry1: crate::Reg, + #[doc = "0x1008 - CoreSight ROM Table End"] + pub end: crate::Reg, + _reserved13: [u8; 0x0fc0], + #[doc = "0x1fcc - CoreSight ROM Table Memory Type"] + pub memtype: crate::Reg, + #[doc = "0x1fd0 - Peripheral Identification 4"] + pub pid4: crate::Reg, + #[doc = "0x1fd4 - Peripheral Identification 5"] + pub pid5: crate::Reg, + #[doc = "0x1fd8 - Peripheral Identification 6"] + pub pid6: crate::Reg, + #[doc = "0x1fdc - Peripheral Identification 7"] + pub pid7: crate::Reg, + #[doc = "0x1fe0 - Peripheral Identification 0"] + pub pid0: crate::Reg, + #[doc = "0x1fe4 - Peripheral Identification 1"] + pub pid1: crate::Reg, + #[doc = "0x1fe8 - Peripheral Identification 2"] + pub pid2: crate::Reg, + #[doc = "0x1fec - Peripheral Identification 3"] + pub pid3: crate::Reg, + #[doc = "0x1ff0 - Component Identification 0"] + pub cid0: crate::Reg, + #[doc = "0x1ff4 - Component Identification 1"] + pub cid1: crate::Reg, + #[doc = "0x1ff8 - Component Identification 2"] + pub cid2: crate::Reg, + #[doc = "0x1ffc - Component Identification 3"] + pub cid3: crate::Reg, +} +#[doc = "CTRL register accessor: an alias for `Reg`"] +pub type CTRL = crate::Reg; +#[doc = "Control"] +pub mod ctrl; +#[doc = "STATUSA register accessor: an alias for `Reg`"] +pub type STATUSA = crate::Reg; +#[doc = "Status A"] +pub mod statusa; +#[doc = "STATUSB register accessor: an alias for `Reg`"] +pub type STATUSB = crate::Reg; +#[doc = "Status B"] +pub mod statusb; +#[doc = "STATUSC register accessor: an alias for `Reg`"] +pub type STATUSC = crate::Reg; +#[doc = "Status C"] +pub mod statusc; +#[doc = "ADDR register accessor: an alias for `Reg`"] +pub type ADDR = crate::Reg; +#[doc = "Address"] +pub mod addr; +#[doc = "LENGTH register accessor: an alias for `Reg`"] +pub type LENGTH = crate::Reg; +#[doc = "Length"] +pub mod length; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "Data"] +pub mod data; +#[doc = "DCC register accessor: an alias for `Reg`"] +pub type DCC = crate::Reg; +#[doc = "Debug Communication Channel n"] +pub mod dcc; +#[doc = "DID register accessor: an alias for `Reg`"] +pub type DID = crate::Reg; +#[doc = "Device Identification"] +pub mod did; +#[doc = "DCFG register accessor: an alias for `Reg`"] +pub type DCFG = crate::Reg; +#[doc = "Device Configuration"] +pub mod dcfg; +#[doc = "ENTRY0 register accessor: an alias for `Reg`"] +pub type ENTRY0 = crate::Reg; +#[doc = "CoreSight ROM Table Entry 0"] +pub mod entry0; +#[doc = "ENTRY1 register accessor: an alias for `Reg`"] +pub type ENTRY1 = crate::Reg; +#[doc = "CoreSight ROM Table Entry 1"] +pub mod entry1; +#[doc = "END register accessor: an alias for `Reg`"] +pub type END = crate::Reg; +#[doc = "CoreSight ROM Table End"] +pub mod end; +#[doc = "MEMTYPE register accessor: an alias for `Reg`"] +pub type MEMTYPE = crate::Reg; +#[doc = "CoreSight ROM Table Memory Type"] +pub mod memtype; +#[doc = "PID4 register accessor: an alias for `Reg`"] +pub type PID4 = crate::Reg; +#[doc = "Peripheral Identification 4"] +pub mod pid4; +#[doc = "PID5 register accessor: an alias for `Reg`"] +pub type PID5 = crate::Reg; +#[doc = "Peripheral Identification 5"] +pub mod pid5; +#[doc = "PID6 register accessor: an alias for `Reg`"] +pub type PID6 = crate::Reg; +#[doc = "Peripheral Identification 6"] +pub mod pid6; +#[doc = "PID7 register accessor: an alias for `Reg`"] +pub type PID7 = crate::Reg; +#[doc = "Peripheral Identification 7"] +pub mod pid7; +#[doc = "PID0 register accessor: an alias for `Reg`"] +pub type PID0 = crate::Reg; +#[doc = "Peripheral Identification 0"] +pub mod pid0; +#[doc = "PID1 register accessor: an alias for `Reg`"] +pub type PID1 = crate::Reg; +#[doc = "Peripheral Identification 1"] +pub mod pid1; +#[doc = "PID2 register accessor: an alias for `Reg`"] +pub type PID2 = crate::Reg; +#[doc = "Peripheral Identification 2"] +pub mod pid2; +#[doc = "PID3 register accessor: an alias for `Reg`"] +pub type PID3 = crate::Reg; +#[doc = "Peripheral Identification 3"] +pub mod pid3; +#[doc = "CID0 register accessor: an alias for `Reg`"] +pub type CID0 = crate::Reg; +#[doc = "Component Identification 0"] +pub mod cid0; +#[doc = "CID1 register accessor: an alias for `Reg`"] +pub type CID1 = crate::Reg; +#[doc = "Component Identification 1"] +pub mod cid1; +#[doc = "CID2 register accessor: an alias for `Reg`"] +pub type CID2 = crate::Reg; +#[doc = "Component Identification 2"] +pub mod cid2; +#[doc = "CID3 register accessor: an alias for `Reg`"] +pub type CID3 = crate::Reg; +#[doc = "Component Identification 3"] +pub mod cid3; diff --git a/pac/atsamc20g/src/dsu/addr.rs b/pac/atsamc20g/src/dsu/addr.rs new file mode 100644 index 000000000000..412f874d6b15 --- /dev/null +++ b/pac/atsamc20g/src/dsu/addr.rs @@ -0,0 +1,140 @@ +#[doc = "Register `ADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `AMOD` reader - Access Mode"] +pub struct AMOD_R(crate::FieldReader); +impl AMOD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + AMOD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AMOD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AMOD` writer - Access Mode"] +pub struct AMOD_W<'a> { + w: &'a mut W, +} +impl<'a> AMOD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u32 & 0x03); + self.w + } +} +#[doc = "Field `ADDR` reader - Address"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - Address"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3fff_ffff << 2)) | ((value as u32 & 0x3fff_ffff) << 2); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Access Mode"] + #[inline(always)] + pub fn amod(&self) -> AMOD_R { + AMOD_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bits 2:31 - Address"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new(((self.bits >> 2) & 0x3fff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:1 - Access Mode"] + #[inline(always)] + pub fn amod(&mut self) -> AMOD_W { + AMOD_W { w: self } + } + #[doc = "Bits 2:31 - Address"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [addr](index.html) module"] +pub struct ADDR_SPEC; +impl crate::RegisterSpec for ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [addr::R](R) reader structure"] +impl crate::Readable for ADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [addr::W](W) writer structure"] +impl crate::Writable for ADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ADDR to value 0"] +impl crate::Resettable for ADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/dsu/cid0.rs b/pac/atsamc20g/src/dsu/cid0.rs new file mode 100644 index 000000000000..b3c2373dfc99 --- /dev/null +++ b/pac/atsamc20g/src/dsu/cid0.rs @@ -0,0 +1,53 @@ +#[doc = "Register `CID0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PREAMBLEB0` reader - Preamble Byte 0"] +pub struct PREAMBLEB0_R(crate::FieldReader); +impl PREAMBLEB0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PREAMBLEB0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PREAMBLEB0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:7 - Preamble Byte 0"] + #[inline(always)] + pub fn preambleb0(&self) -> PREAMBLEB0_R { + PREAMBLEB0_R::new((self.bits & 0xff) as u8) + } +} +#[doc = "Component Identification 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid0](index.html) module"] +pub struct CID0_SPEC; +impl crate::RegisterSpec for CID0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid0::R](R) reader structure"] +impl crate::Readable for CID0_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID0 to value 0x0d"] +impl crate::Resettable for CID0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0d + } +} diff --git a/pac/atsamc20g/src/dsu/cid1.rs b/pac/atsamc20g/src/dsu/cid1.rs new file mode 100644 index 000000000000..3628ceac64a7 --- /dev/null +++ b/pac/atsamc20g/src/dsu/cid1.rs @@ -0,0 +1,73 @@ +#[doc = "Register `CID1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PREAMBLE` reader - Preamble"] +pub struct PREAMBLE_R(crate::FieldReader); +impl PREAMBLE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PREAMBLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PREAMBLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCLASS` reader - Component Class"] +pub struct CCLASS_R(crate::FieldReader); +impl CCLASS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CCLASS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCLASS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:3 - Preamble"] + #[inline(always)] + pub fn preamble(&self) -> PREAMBLE_R { + PREAMBLE_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Component Class"] + #[inline(always)] + pub fn cclass(&self) -> CCLASS_R { + CCLASS_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +#[doc = "Component Identification 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid1](index.html) module"] +pub struct CID1_SPEC; +impl crate::RegisterSpec for CID1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid1::R](R) reader structure"] +impl crate::Readable for CID1_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID1 to value 0x10"] +impl crate::Resettable for CID1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x10 + } +} diff --git a/pac/atsamc20g/src/dsu/cid2.rs b/pac/atsamc20g/src/dsu/cid2.rs new file mode 100644 index 000000000000..714078d5c430 --- /dev/null +++ b/pac/atsamc20g/src/dsu/cid2.rs @@ -0,0 +1,53 @@ +#[doc = "Register `CID2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PREAMBLEB2` reader - Preamble Byte 2"] +pub struct PREAMBLEB2_R(crate::FieldReader); +impl PREAMBLEB2_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PREAMBLEB2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PREAMBLEB2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:7 - Preamble Byte 2"] + #[inline(always)] + pub fn preambleb2(&self) -> PREAMBLEB2_R { + PREAMBLEB2_R::new((self.bits & 0xff) as u8) + } +} +#[doc = "Component Identification 2\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid2](index.html) module"] +pub struct CID2_SPEC; +impl crate::RegisterSpec for CID2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid2::R](R) reader structure"] +impl crate::Readable for CID2_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID2 to value 0x05"] +impl crate::Resettable for CID2_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x05 + } +} diff --git a/pac/atsamc20g/src/dsu/cid3.rs b/pac/atsamc20g/src/dsu/cid3.rs new file mode 100644 index 000000000000..a345af7b5166 --- /dev/null +++ b/pac/atsamc20g/src/dsu/cid3.rs @@ -0,0 +1,53 @@ +#[doc = "Register `CID3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PREAMBLEB3` reader - Preamble Byte 3"] +pub struct PREAMBLEB3_R(crate::FieldReader); +impl PREAMBLEB3_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PREAMBLEB3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PREAMBLEB3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:7 - Preamble Byte 3"] + #[inline(always)] + pub fn preambleb3(&self) -> PREAMBLEB3_R { + PREAMBLEB3_R::new((self.bits & 0xff) as u8) + } +} +#[doc = "Component Identification 3\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid3](index.html) module"] +pub struct CID3_SPEC; +impl crate::RegisterSpec for CID3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid3::R](R) reader structure"] +impl crate::Readable for CID3_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID3 to value 0xb1"] +impl crate::Resettable for CID3_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xb1 + } +} diff --git a/pac/atsamc20g/src/dsu/ctrl.rs b/pac/atsamc20g/src/dsu/ctrl.rs new file mode 100644 index 000000000000..0a19db5a5239 --- /dev/null +++ b/pac/atsamc20g/src/dsu/ctrl.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `CRC` writer - 32-bit Cyclic Redundancy Code"] +pub struct CRC_W<'a> { + w: &'a mut W, +} +impl<'a> CRC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `MBIST` writer - Memory built-in self-test"] +pub struct MBIST_W<'a> { + w: &'a mut W, +} +impl<'a> MBIST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CE` writer - Chip-Erase"] +pub struct CE_W<'a> { + w: &'a mut W, +} +impl<'a> CE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `ARR` writer - Auxiliary Row Read"] +pub struct ARR_W<'a> { + w: &'a mut W, +} +impl<'a> ARR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +#[doc = "Field `SMSA` writer - Start Memory Stream Access"] +pub struct SMSA_W<'a> { + w: &'a mut W, +} +impl<'a> SMSA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 2 - 32-bit Cyclic Redundancy Code"] + #[inline(always)] + pub fn crc(&mut self) -> CRC_W { + CRC_W { w: self } + } + #[doc = "Bit 3 - Memory built-in self-test"] + #[inline(always)] + pub fn mbist(&mut self) -> MBIST_W { + MBIST_W { w: self } + } + #[doc = "Bit 4 - Chip-Erase"] + #[inline(always)] + pub fn ce(&mut self) -> CE_W { + CE_W { w: self } + } + #[doc = "Bit 6 - Auxiliary Row Read"] + #[inline(always)] + pub fn arr(&mut self) -> ARR_W { + ARR_W { w: self } + } + #[doc = "Bit 7 - Start Memory Stream Access"] + #[inline(always)] + pub fn smsa(&mut self) -> SMSA_W { + SMSA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"] +pub struct CTRL_SPEC; +impl crate::RegisterSpec for CTRL_SPEC { + type Ux = u8; +} +#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"] +impl crate::Writable for CTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/dsu/data.rs b/pac/atsamc20g/src/dsu/data.rs new file mode 100644 index 000000000000..193cc49a07fd --- /dev/null +++ b/pac/atsamc20g/src/dsu/data.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Data"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Data"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/dsu/dcc.rs b/pac/atsamc20g/src/dsu/dcc.rs new file mode 100644 index 000000000000..354323a499ef --- /dev/null +++ b/pac/atsamc20g/src/dsu/dcc.rs @@ -0,0 +1,104 @@ +#[doc = "Register `DCC[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DCC[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Data"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Data"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Communication Channel n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dcc](index.html) module"] +pub struct DCC_SPEC; +impl crate::RegisterSpec for DCC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dcc::R](R) reader structure"] +impl crate::Readable for DCC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dcc::W](W) writer structure"] +impl crate::Writable for DCC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DCC[%s] +to value 0"] +impl crate::Resettable for DCC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/dsu/dcfg.rs b/pac/atsamc20g/src/dsu/dcfg.rs new file mode 100644 index 000000000000..c6d61d0b496e --- /dev/null +++ b/pac/atsamc20g/src/dsu/dcfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `DCFG[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DCFG[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DCFG` reader - Device Configuration"] +pub struct DCFG_R(crate::FieldReader); +impl DCFG_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + DCFG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DCFG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DCFG` writer - Device Configuration"] +pub struct DCFG_W<'a> { + w: &'a mut W, +} +impl<'a> DCFG_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Device Configuration"] + #[inline(always)] + pub fn dcfg(&self) -> DCFG_R { + DCFG_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Device Configuration"] + #[inline(always)] + pub fn dcfg(&mut self) -> DCFG_W { + DCFG_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Device Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dcfg](index.html) module"] +pub struct DCFG_SPEC; +impl crate::RegisterSpec for DCFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dcfg::R](R) reader structure"] +impl crate::Readable for DCFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dcfg::W](W) writer structure"] +impl crate::Writable for DCFG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DCFG[%s] +to value 0"] +impl crate::Resettable for DCFG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/dsu/did.rs b/pac/atsamc20g/src/dsu/did.rs new file mode 100644 index 000000000000..16117820e39f --- /dev/null +++ b/pac/atsamc20g/src/dsu/did.rs @@ -0,0 +1,279 @@ +#[doc = "Register `DID` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `DEVSEL` reader - Device Select"] +pub struct DEVSEL_R(crate::FieldReader); +impl DEVSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DEVSEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DEVSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REVISION` reader - Revision Number"] +pub struct REVISION_R(crate::FieldReader); +impl REVISION_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REVISION_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REVISION_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIE` reader - Die Number"] +pub struct DIE_R(crate::FieldReader); +impl DIE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DIE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Series\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SERIES_A { + #[doc = "0: Cortex-M0+ processor, basic feature set"] + _0 = 0, + #[doc = "1: Cortex-M0+ processor, CAN"] + _1 = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SERIES_A) -> Self { + variant as _ + } +} +#[doc = "Field `SERIES` reader - Series"] +pub struct SERIES_R(crate::FieldReader); +impl SERIES_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SERIES_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SERIES_A::_0), + 1 => Some(SERIES_A::_1), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_0`"] + #[inline(always)] + pub fn is_0(&self) -> bool { + **self == SERIES_A::_0 + } + #[doc = "Checks if the value of the field is `_1`"] + #[inline(always)] + pub fn is_1(&self) -> bool { + **self == SERIES_A::_1 + } +} +impl core::ops::Deref for SERIES_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Family\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FAMILY_A { + #[doc = "0: General purpose microcontroller"] + _0 = 0, + #[doc = "1: PicoPower"] + _1 = 1, + #[doc = "2: 5V Industrial"] + _2 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FAMILY_A) -> Self { + variant as _ + } +} +#[doc = "Field `FAMILY` reader - Family"] +pub struct FAMILY_R(crate::FieldReader); +impl FAMILY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FAMILY_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(FAMILY_A::_0), + 1 => Some(FAMILY_A::_1), + 2 => Some(FAMILY_A::_2), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_0`"] + #[inline(always)] + pub fn is_0(&self) -> bool { + **self == FAMILY_A::_0 + } + #[doc = "Checks if the value of the field is `_1`"] + #[inline(always)] + pub fn is_1(&self) -> bool { + **self == FAMILY_A::_1 + } + #[doc = "Checks if the value of the field is `_2`"] + #[inline(always)] + pub fn is_2(&self) -> bool { + **self == FAMILY_A::_2 + } +} +impl core::ops::Deref for FAMILY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Processor\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PROCESSOR_A { + #[doc = "0: Cortex-M0"] + _0 = 0, + #[doc = "1: Cortex-M0+"] + _1 = 1, + #[doc = "2: Cortex-M3"] + _2 = 2, + #[doc = "3: Cortex-M4"] + _3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PROCESSOR_A) -> Self { + variant as _ + } +} +#[doc = "Field `PROCESSOR` reader - Processor"] +pub struct PROCESSOR_R(crate::FieldReader); +impl PROCESSOR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PROCESSOR_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PROCESSOR_A::_0), + 1 => Some(PROCESSOR_A::_1), + 2 => Some(PROCESSOR_A::_2), + 3 => Some(PROCESSOR_A::_3), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_0`"] + #[inline(always)] + pub fn is_0(&self) -> bool { + **self == PROCESSOR_A::_0 + } + #[doc = "Checks if the value of the field is `_1`"] + #[inline(always)] + pub fn is_1(&self) -> bool { + **self == PROCESSOR_A::_1 + } + #[doc = "Checks if the value of the field is `_2`"] + #[inline(always)] + pub fn is_2(&self) -> bool { + **self == PROCESSOR_A::_2 + } + #[doc = "Checks if the value of the field is `_3`"] + #[inline(always)] + pub fn is_3(&self) -> bool { + **self == PROCESSOR_A::_3 + } +} +impl core::ops::Deref for PROCESSOR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:7 - Device Select"] + #[inline(always)] + pub fn devsel(&self) -> DEVSEL_R { + DEVSEL_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:11 - Revision Number"] + #[inline(always)] + pub fn revision(&self) -> REVISION_R { + REVISION_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - Die Number"] + #[inline(always)] + pub fn die(&self) -> DIE_R { + DIE_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:21 - Series"] + #[inline(always)] + pub fn series(&self) -> SERIES_R { + SERIES_R::new(((self.bits >> 16) & 0x3f) as u8) + } + #[doc = "Bits 23:27 - Family"] + #[inline(always)] + pub fn family(&self) -> FAMILY_R { + FAMILY_R::new(((self.bits >> 23) & 0x1f) as u8) + } + #[doc = "Bits 28:31 - Processor"] + #[inline(always)] + pub fn processor(&self) -> PROCESSOR_R { + PROCESSOR_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +#[doc = "Device Identification\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [did](index.html) module"] +pub struct DID_SPEC; +impl crate::RegisterSpec for DID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [did::R](R) reader structure"] +impl crate::Readable for DID_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DID to value 0x1100_0505"] +impl crate::Resettable for DID_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x1100_0505 + } +} diff --git a/pac/atsamc20g/src/dsu/end.rs b/pac/atsamc20g/src/dsu/end.rs new file mode 100644 index 000000000000..cce2edea2bce --- /dev/null +++ b/pac/atsamc20g/src/dsu/end.rs @@ -0,0 +1,53 @@ +#[doc = "Register `END` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `END` reader - End Marker"] +pub struct END_R(crate::FieldReader); +impl END_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + END_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for END_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - End Marker"] + #[inline(always)] + pub fn end(&self) -> END_R { + END_R::new(self.bits as u32) + } +} +#[doc = "CoreSight ROM Table End\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [end](index.html) module"] +pub struct END_SPEC; +impl crate::RegisterSpec for END_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [end::R](R) reader structure"] +impl crate::Readable for END_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets END to value 0"] +impl crate::Resettable for END_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/dsu/entry0.rs b/pac/atsamc20g/src/dsu/entry0.rs new file mode 100644 index 000000000000..d8563990e827 --- /dev/null +++ b/pac/atsamc20g/src/dsu/entry0.rs @@ -0,0 +1,93 @@ +#[doc = "Register `ENTRY0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `EPRES` reader - Entry Present"] +pub struct EPRES_R(crate::FieldReader); +impl EPRES_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EPRES_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EPRES_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FMT` reader - Format"] +pub struct FMT_R(crate::FieldReader); +impl FMT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FMT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FMT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDOFF` reader - Address Offset"] +pub struct ADDOFF_R(crate::FieldReader); +impl ADDOFF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + ADDOFF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDOFF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Entry Present"] + #[inline(always)] + pub fn epres(&self) -> EPRES_R { + EPRES_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Format"] + #[inline(always)] + pub fn fmt(&self) -> FMT_R { + FMT_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 12:31 - Address Offset"] + #[inline(always)] + pub fn addoff(&self) -> ADDOFF_R { + ADDOFF_R::new(((self.bits >> 12) & 0x000f_ffff) as u32) + } +} +#[doc = "CoreSight ROM Table Entry 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [entry0](index.html) module"] +pub struct ENTRY0_SPEC; +impl crate::RegisterSpec for ENTRY0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [entry0::R](R) reader structure"] +impl crate::Readable for ENTRY0_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets ENTRY0 to value 0x9f0f_c002"] +impl crate::Resettable for ENTRY0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x9f0f_c002 + } +} diff --git a/pac/atsamc20g/src/dsu/entry1.rs b/pac/atsamc20g/src/dsu/entry1.rs new file mode 100644 index 000000000000..cec8fa367705 --- /dev/null +++ b/pac/atsamc20g/src/dsu/entry1.rs @@ -0,0 +1,31 @@ +#[doc = "Register `ENTRY1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "CoreSight ROM Table Entry 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [entry1](index.html) module"] +pub struct ENTRY1_SPEC; +impl crate::RegisterSpec for ENTRY1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [entry1::R](R) reader structure"] +impl crate::Readable for ENTRY1_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets ENTRY1 to value 0x5002"] +impl crate::Resettable for ENTRY1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x5002 + } +} diff --git a/pac/atsamc20g/src/dsu/length.rs b/pac/atsamc20g/src/dsu/length.rs new file mode 100644 index 000000000000..2dc771f74dfd --- /dev/null +++ b/pac/atsamc20g/src/dsu/length.rs @@ -0,0 +1,103 @@ +#[doc = "Register `LENGTH` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `LENGTH` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `LENGTH` reader - Length"] +pub struct LENGTH_R(crate::FieldReader); +impl LENGTH_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + LENGTH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LENGTH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LENGTH` writer - Length"] +pub struct LENGTH_W<'a> { + w: &'a mut W, +} +impl<'a> LENGTH_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3fff_ffff << 2)) | ((value as u32 & 0x3fff_ffff) << 2); + self.w + } +} +impl R { + #[doc = "Bits 2:31 - Length"] + #[inline(always)] + pub fn length(&self) -> LENGTH_R { + LENGTH_R::new(((self.bits >> 2) & 0x3fff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 2:31 - Length"] + #[inline(always)] + pub fn length(&mut self) -> LENGTH_W { + LENGTH_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Length\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [length](index.html) module"] +pub struct LENGTH_SPEC; +impl crate::RegisterSpec for LENGTH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [length::R](R) reader structure"] +impl crate::Readable for LENGTH_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [length::W](W) writer structure"] +impl crate::Writable for LENGTH_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets LENGTH to value 0"] +impl crate::Resettable for LENGTH_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/dsu/memtype.rs b/pac/atsamc20g/src/dsu/memtype.rs new file mode 100644 index 000000000000..3cc841e2ba78 --- /dev/null +++ b/pac/atsamc20g/src/dsu/memtype.rs @@ -0,0 +1,53 @@ +#[doc = "Register `MEMTYPE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SMEMP` reader - System Memory Present"] +pub struct SMEMP_R(crate::FieldReader); +impl SMEMP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SMEMP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SMEMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - System Memory Present"] + #[inline(always)] + pub fn smemp(&self) -> SMEMP_R { + SMEMP_R::new((self.bits & 0x01) != 0) + } +} +#[doc = "CoreSight ROM Table Memory Type\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [memtype](index.html) module"] +pub struct MEMTYPE_SPEC; +impl crate::RegisterSpec for MEMTYPE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [memtype::R](R) reader structure"] +impl crate::Readable for MEMTYPE_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets MEMTYPE to value 0"] +impl crate::Resettable for MEMTYPE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/dsu/pid0.rs b/pac/atsamc20g/src/dsu/pid0.rs new file mode 100644 index 000000000000..98028ea62838 --- /dev/null +++ b/pac/atsamc20g/src/dsu/pid0.rs @@ -0,0 +1,53 @@ +#[doc = "Register `PID0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PARTNBL` reader - Part Number Low"] +pub struct PARTNBL_R(crate::FieldReader); +impl PARTNBL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PARTNBL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PARTNBL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:7 - Part Number Low"] + #[inline(always)] + pub fn partnbl(&self) -> PARTNBL_R { + PARTNBL_R::new((self.bits & 0xff) as u8) + } +} +#[doc = "Peripheral Identification 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid0](index.html) module"] +pub struct PID0_SPEC; +impl crate::RegisterSpec for PID0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid0::R](R) reader structure"] +impl crate::Readable for PID0_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID0 to value 0xd0"] +impl crate::Resettable for PID0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xd0 + } +} diff --git a/pac/atsamc20g/src/dsu/pid1.rs b/pac/atsamc20g/src/dsu/pid1.rs new file mode 100644 index 000000000000..4f94b853507c --- /dev/null +++ b/pac/atsamc20g/src/dsu/pid1.rs @@ -0,0 +1,73 @@ +#[doc = "Register `PID1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PARTNBH` reader - Part Number High"] +pub struct PARTNBH_R(crate::FieldReader); +impl PARTNBH_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PARTNBH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PARTNBH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `JEPIDCL` reader - Low part of the JEP-106 Identity Code"] +pub struct JEPIDCL_R(crate::FieldReader); +impl JEPIDCL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + JEPIDCL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for JEPIDCL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:3 - Part Number High"] + #[inline(always)] + pub fn partnbh(&self) -> PARTNBH_R { + PARTNBH_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Low part of the JEP-106 Identity Code"] + #[inline(always)] + pub fn jepidcl(&self) -> JEPIDCL_R { + JEPIDCL_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +#[doc = "Peripheral Identification 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid1](index.html) module"] +pub struct PID1_SPEC; +impl crate::RegisterSpec for PID1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid1::R](R) reader structure"] +impl crate::Readable for PID1_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID1 to value 0xfc"] +impl crate::Resettable for PID1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xfc + } +} diff --git a/pac/atsamc20g/src/dsu/pid2.rs b/pac/atsamc20g/src/dsu/pid2.rs new file mode 100644 index 000000000000..d8f8ed10192e --- /dev/null +++ b/pac/atsamc20g/src/dsu/pid2.rs @@ -0,0 +1,93 @@ +#[doc = "Register `PID2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `JEPIDCH` reader - JEP-106 Identity Code High"] +pub struct JEPIDCH_R(crate::FieldReader); +impl JEPIDCH_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + JEPIDCH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for JEPIDCH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `JEPU` reader - JEP-106 Identity Code is used"] +pub struct JEPU_R(crate::FieldReader); +impl JEPU_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + JEPU_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for JEPU_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REVISION` reader - Revision Number"] +pub struct REVISION_R(crate::FieldReader); +impl REVISION_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REVISION_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REVISION_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:2 - JEP-106 Identity Code High"] + #[inline(always)] + pub fn jepidch(&self) -> JEPIDCH_R { + JEPIDCH_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 3 - JEP-106 Identity Code is used"] + #[inline(always)] + pub fn jepu(&self) -> JEPU_R { + JEPU_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bits 4:7 - Revision Number"] + #[inline(always)] + pub fn revision(&self) -> REVISION_R { + REVISION_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +#[doc = "Peripheral Identification 2\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid2](index.html) module"] +pub struct PID2_SPEC; +impl crate::RegisterSpec for PID2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid2::R](R) reader structure"] +impl crate::Readable for PID2_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID2 to value 0x09"] +impl crate::Resettable for PID2_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x09 + } +} diff --git a/pac/atsamc20g/src/dsu/pid3.rs b/pac/atsamc20g/src/dsu/pid3.rs new file mode 100644 index 000000000000..c0a8fb2d7f92 --- /dev/null +++ b/pac/atsamc20g/src/dsu/pid3.rs @@ -0,0 +1,73 @@ +#[doc = "Register `PID3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `CUSMOD` reader - ARM CUSMOD"] +pub struct CUSMOD_R(crate::FieldReader); +impl CUSMOD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CUSMOD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CUSMOD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REVAND` reader - Revision Number"] +pub struct REVAND_R(crate::FieldReader); +impl REVAND_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REVAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REVAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:3 - ARM CUSMOD"] + #[inline(always)] + pub fn cusmod(&self) -> CUSMOD_R { + CUSMOD_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Revision Number"] + #[inline(always)] + pub fn revand(&self) -> REVAND_R { + REVAND_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +#[doc = "Peripheral Identification 3\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid3](index.html) module"] +pub struct PID3_SPEC; +impl crate::RegisterSpec for PID3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid3::R](R) reader structure"] +impl crate::Readable for PID3_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID3 to value 0"] +impl crate::Resettable for PID3_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/dsu/pid4.rs b/pac/atsamc20g/src/dsu/pid4.rs new file mode 100644 index 000000000000..d3a1bd120f0b --- /dev/null +++ b/pac/atsamc20g/src/dsu/pid4.rs @@ -0,0 +1,73 @@ +#[doc = "Register `PID4` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `JEPCC` reader - JEP-106 Continuation Code"] +pub struct JEPCC_R(crate::FieldReader); +impl JEPCC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + JEPCC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for JEPCC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FKBC` reader - 4KB count"] +pub struct FKBC_R(crate::FieldReader); +impl FKBC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FKBC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FKBC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:3 - JEP-106 Continuation Code"] + #[inline(always)] + pub fn jepcc(&self) -> JEPCC_R { + JEPCC_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - 4KB count"] + #[inline(always)] + pub fn fkbc(&self) -> FKBC_R { + FKBC_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +#[doc = "Peripheral Identification 4\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid4](index.html) module"] +pub struct PID4_SPEC; +impl crate::RegisterSpec for PID4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid4::R](R) reader structure"] +impl crate::Readable for PID4_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID4 to value 0"] +impl crate::Resettable for PID4_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/dsu/pid5.rs b/pac/atsamc20g/src/dsu/pid5.rs new file mode 100644 index 000000000000..d343d4800b95 --- /dev/null +++ b/pac/atsamc20g/src/dsu/pid5.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID5` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 5\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid5](index.html) module"] +pub struct PID5_SPEC; +impl crate::RegisterSpec for PID5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid5::R](R) reader structure"] +impl crate::Readable for PID5_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID5 to value 0"] +impl crate::Resettable for PID5_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/dsu/pid6.rs b/pac/atsamc20g/src/dsu/pid6.rs new file mode 100644 index 000000000000..55cc2b8b5861 --- /dev/null +++ b/pac/atsamc20g/src/dsu/pid6.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID6` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 6\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid6](index.html) module"] +pub struct PID6_SPEC; +impl crate::RegisterSpec for PID6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid6::R](R) reader structure"] +impl crate::Readable for PID6_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID6 to value 0"] +impl crate::Resettable for PID6_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/dsu/pid7.rs b/pac/atsamc20g/src/dsu/pid7.rs new file mode 100644 index 000000000000..77664d4f2f95 --- /dev/null +++ b/pac/atsamc20g/src/dsu/pid7.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID7` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 7\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid7](index.html) module"] +pub struct PID7_SPEC; +impl crate::RegisterSpec for PID7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid7::R](R) reader structure"] +impl crate::Readable for PID7_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID7 to value 0"] +impl crate::Resettable for PID7_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/dsu/statusa.rs b/pac/atsamc20g/src/dsu/statusa.rs new file mode 100644 index 000000000000..c7b90a13e491 --- /dev/null +++ b/pac/atsamc20g/src/dsu/statusa.rs @@ -0,0 +1,301 @@ +#[doc = "Register `STATUSA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUSA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DONE` reader - Done"] +pub struct DONE_R(crate::FieldReader); +impl DONE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DONE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DONE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DONE` writer - Done"] +pub struct DONE_W<'a> { + w: &'a mut W, +} +impl<'a> DONE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `CRSTEXT` reader - CPU Reset Phase Extension"] +pub struct CRSTEXT_R(crate::FieldReader); +impl CRSTEXT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CRSTEXT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CRSTEXT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRSTEXT` writer - CPU Reset Phase Extension"] +pub struct CRSTEXT_W<'a> { + w: &'a mut W, +} +impl<'a> CRSTEXT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `BERR` reader - Bus Error"] +pub struct BERR_R(crate::FieldReader); +impl BERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BERR` writer - Bus Error"] +pub struct BERR_W<'a> { + w: &'a mut W, +} +impl<'a> BERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `FAIL` reader - Failure"] +pub struct FAIL_R(crate::FieldReader); +impl FAIL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAIL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAIL` writer - Failure"] +pub struct FAIL_W<'a> { + w: &'a mut W, +} +impl<'a> FAIL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PERR` reader - Protection Error"] +pub struct PERR_R(crate::FieldReader); +impl PERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERR` writer - Protection Error"] +pub struct PERR_W<'a> { + w: &'a mut W, +} +impl<'a> PERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +impl R { + #[doc = "Bit 0 - Done"] + #[inline(always)] + pub fn done(&self) -> DONE_R { + DONE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - CPU Reset Phase Extension"] + #[inline(always)] + pub fn crstext(&self) -> CRSTEXT_R { + CRSTEXT_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Bus Error"] + #[inline(always)] + pub fn berr(&self) -> BERR_R { + BERR_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Failure"] + #[inline(always)] + pub fn fail(&self) -> FAIL_R { + FAIL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Protection Error"] + #[inline(always)] + pub fn perr(&self) -> PERR_R { + PERR_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Done"] + #[inline(always)] + pub fn done(&mut self) -> DONE_W { + DONE_W { w: self } + } + #[doc = "Bit 1 - CPU Reset Phase Extension"] + #[inline(always)] + pub fn crstext(&mut self) -> CRSTEXT_W { + CRSTEXT_W { w: self } + } + #[doc = "Bit 2 - Bus Error"] + #[inline(always)] + pub fn berr(&mut self) -> BERR_W { + BERR_W { w: self } + } + #[doc = "Bit 3 - Failure"] + #[inline(always)] + pub fn fail(&mut self) -> FAIL_W { + FAIL_W { w: self } + } + #[doc = "Bit 4 - Protection Error"] + #[inline(always)] + pub fn perr(&mut self) -> PERR_W { + PERR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [statusa](index.html) module"] +pub struct STATUSA_SPEC; +impl crate::RegisterSpec for STATUSA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [statusa::R](R) reader structure"] +impl crate::Readable for STATUSA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [statusa::W](W) writer structure"] +impl crate::Writable for STATUSA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUSA to value 0"] +impl crate::Resettable for STATUSA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/dsu/statusb.rs b/pac/atsamc20g/src/dsu/statusb.rs new file mode 100644 index 000000000000..1e9374f8deae --- /dev/null +++ b/pac/atsamc20g/src/dsu/statusb.rs @@ -0,0 +1,133 @@ +#[doc = "Register `STATUSB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PROT` reader - Protected"] +pub struct PROT_R(crate::FieldReader); +impl PROT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PROT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PROT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGPRES` reader - Debugger Present"] +pub struct DBGPRES_R(crate::FieldReader); +impl DBGPRES_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGPRES_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGPRES_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DCCD0` reader - Debug Communication Channel 0 Dirty"] +pub struct DCCD0_R(crate::FieldReader); +impl DCCD0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DCCD0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DCCD0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DCCD1` reader - Debug Communication Channel 1 Dirty"] +pub struct DCCD1_R(crate::FieldReader); +impl DCCD1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DCCD1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DCCD1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HPE` reader - Hot-Plugging Enable"] +pub struct HPE_R(crate::FieldReader); +impl HPE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HPE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HPE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Protected"] + #[inline(always)] + pub fn prot(&self) -> PROT_R { + PROT_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Debugger Present"] + #[inline(always)] + pub fn dbgpres(&self) -> DBGPRES_R { + DBGPRES_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Debug Communication Channel 0 Dirty"] + #[inline(always)] + pub fn dccd0(&self) -> DCCD0_R { + DCCD0_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Debug Communication Channel 1 Dirty"] + #[inline(always)] + pub fn dccd1(&self) -> DCCD1_R { + DCCD1_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Hot-Plugging Enable"] + #[inline(always)] + pub fn hpe(&self) -> HPE_R { + HPE_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +#[doc = "Status B\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [statusb](index.html) module"] +pub struct STATUSB_SPEC; +impl crate::RegisterSpec for STATUSB_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [statusb::R](R) reader structure"] +impl crate::Readable for STATUSB_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUSB to value 0"] +impl crate::Resettable for STATUSB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/dsu/statusc.rs b/pac/atsamc20g/src/dsu/statusc.rs new file mode 100644 index 000000000000..14b3f7b1c7e3 --- /dev/null +++ b/pac/atsamc20g/src/dsu/statusc.rs @@ -0,0 +1,53 @@ +#[doc = "Register `STATUSC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `STATE` reader - State"] +pub struct STATE_R(crate::FieldReader); +impl STATE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + STATE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STATE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:2 - State"] + #[inline(always)] + pub fn state(&self) -> STATE_R { + STATE_R::new((self.bits & 0x07) as u8) + } +} +#[doc = "Status C\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [statusc](index.html) module"] +pub struct STATUSC_SPEC; +impl crate::RegisterSpec for STATUSC_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [statusc::R](R) reader structure"] +impl crate::Readable for STATUSC_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUSC to value 0"] +impl crate::Resettable for STATUSC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/eic.rs b/pac/atsamc20g/src/eic.rs new file mode 100644 index 000000000000..606231233f4b --- /dev/null +++ b/pac/atsamc20g/src/eic.rs @@ -0,0 +1,64 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrla: crate::Reg, + #[doc = "0x01 - NMI Control"] + pub nmictrl: crate::Reg, + #[doc = "0x02 - NMI Interrupt Flag"] + pub nmiflag: crate::Reg, + #[doc = "0x04 - Syncbusy register"] + pub syncbusy: crate::Reg, + #[doc = "0x08 - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x0c - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x10 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x14 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x18 - EIC Asynchronous edge Detection Enable"] + pub asynch: crate::Reg, + #[doc = "0x1c..0x24 - Configuration n"] + pub config: [crate::Reg; 2], +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control"] +pub mod ctrla; +#[doc = "NMICTRL register accessor: an alias for `Reg`"] +pub type NMICTRL = crate::Reg; +#[doc = "NMI Control"] +pub mod nmictrl; +#[doc = "NMIFLAG register accessor: an alias for `Reg`"] +pub type NMIFLAG = crate::Reg; +#[doc = "NMI Interrupt Flag"] +pub mod nmiflag; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Syncbusy register"] +pub mod syncbusy; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "ASYNCH register accessor: an alias for `Reg`"] +pub type ASYNCH = crate::Reg; +#[doc = "EIC Asynchronous edge Detection Enable"] +pub mod asynch; +#[doc = "CONFIG register accessor: an alias for `Reg`"] +pub type CONFIG = crate::Reg; +#[doc = "Configuration n"] +pub mod config; diff --git a/pac/atsamc20g/src/eic/asynch.rs b/pac/atsamc20g/src/eic/asynch.rs new file mode 100644 index 000000000000..78a9b5c5f054 --- /dev/null +++ b/pac/atsamc20g/src/eic/asynch.rs @@ -0,0 +1,152 @@ +#[doc = "Register `ASYNCH` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ASYNCH` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "EIC Asynchronous edge Detection Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u16)] +pub enum ASYNCH_A { + #[doc = "0: Edge detection is clock synchronously operated"] + SYNC = 0, + #[doc = "1: Edge detection is clock asynchronously operated"] + ASYNC = 1, +} +impl From for u16 { + #[inline(always)] + fn from(variant: ASYNCH_A) -> Self { + variant as _ + } +} +#[doc = "Field `ASYNCH` reader - EIC Asynchronous edge Detection Enable"] +pub struct ASYNCH_R(crate::FieldReader); +impl ASYNCH_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + ASYNCH_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(ASYNCH_A::SYNC), + 1 => Some(ASYNCH_A::ASYNC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `SYNC`"] + #[inline(always)] + pub fn is_sync(&self) -> bool { + **self == ASYNCH_A::SYNC + } + #[doc = "Checks if the value of the field is `ASYNC`"] + #[inline(always)] + pub fn is_async(&self) -> bool { + **self == ASYNCH_A::ASYNC + } +} +impl core::ops::Deref for ASYNCH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ASYNCH` writer - EIC Asynchronous edge Detection Enable"] +pub struct ASYNCH_W<'a> { + w: &'a mut W, +} +impl<'a> ASYNCH_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: ASYNCH_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Edge detection is clock synchronously operated"] + #[inline(always)] + pub fn sync(self) -> &'a mut W { + self.variant(ASYNCH_A::SYNC) + } + #[doc = "Edge detection is clock asynchronously operated"] + #[inline(always)] + pub fn async_(self) -> &'a mut W { + self.variant(ASYNCH_A::ASYNC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - EIC Asynchronous edge Detection Enable"] + #[inline(always)] + pub fn asynch(&self) -> ASYNCH_R { + ASYNCH_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - EIC Asynchronous edge Detection Enable"] + #[inline(always)] + pub fn asynch(&mut self) -> ASYNCH_W { + ASYNCH_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "EIC Asynchronous edge Detection Enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [asynch](index.html) module"] +pub struct ASYNCH_SPEC; +impl crate::RegisterSpec for ASYNCH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [asynch::R](R) reader structure"] +impl crate::Readable for ASYNCH_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [asynch::W](W) writer structure"] +impl crate::Writable for ASYNCH_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ASYNCH to value 0"] +impl crate::Resettable for ASYNCH_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/eic/config.rs b/pac/atsamc20g/src/eic/config.rs new file mode 100644 index 000000000000..ab2c30950417 --- /dev/null +++ b/pac/atsamc20g/src/eic/config.rs @@ -0,0 +1,1547 @@ +#[doc = "Register `CONFIG[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CONFIG[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Input Sense Configuration 0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE0_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE0_A) -> Self { + variant as _ + } +} +#[doc = "Field `SENSE0` reader - Input Sense Configuration 0"] +pub struct SENSE0_R(crate::FieldReader); +impl SENSE0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SENSE0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE0_A::NONE), + 1 => Some(SENSE0_A::RISE), + 2 => Some(SENSE0_A::FALL), + 3 => Some(SENSE0_A::BOTH), + 4 => Some(SENSE0_A::HIGH), + 5 => Some(SENSE0_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == SENSE0_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == SENSE0_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == SENSE0_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == SENSE0_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SENSE0_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SENSE0_A::LOW + } +} +impl core::ops::Deref for SENSE0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SENSE0` writer - Input Sense Configuration 0"] +pub struct SENSE0_W<'a> { + w: &'a mut W, +} +impl<'a> SENSE0_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SENSE0_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE0_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE0_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE0_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE0_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE0_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE0_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Field `FILTEN0` reader - Filter Enable 0"] +pub struct FILTEN0_R(crate::FieldReader); +impl FILTEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FILTEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTEN0` writer - Filter Enable 0"] +pub struct FILTEN0_W<'a> { + w: &'a mut W, +} +impl<'a> FILTEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Input Sense Configuration 1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE1_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE1_A) -> Self { + variant as _ + } +} +#[doc = "Field `SENSE1` reader - Input Sense Configuration 1"] +pub struct SENSE1_R(crate::FieldReader); +impl SENSE1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SENSE1_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE1_A::NONE), + 1 => Some(SENSE1_A::RISE), + 2 => Some(SENSE1_A::FALL), + 3 => Some(SENSE1_A::BOTH), + 4 => Some(SENSE1_A::HIGH), + 5 => Some(SENSE1_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == SENSE1_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == SENSE1_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == SENSE1_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == SENSE1_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SENSE1_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SENSE1_A::LOW + } +} +impl core::ops::Deref for SENSE1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SENSE1` writer - Input Sense Configuration 1"] +pub struct SENSE1_W<'a> { + w: &'a mut W, +} +impl<'a> SENSE1_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SENSE1_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE1_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE1_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE1_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE1_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE1_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE1_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 4)) | ((value as u32 & 0x07) << 4); + self.w + } +} +#[doc = "Field `FILTEN1` reader - Filter Enable 1"] +pub struct FILTEN1_R(crate::FieldReader); +impl FILTEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FILTEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTEN1` writer - Filter Enable 1"] +pub struct FILTEN1_W<'a> { + w: &'a mut W, +} +impl<'a> FILTEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Input Sense Configuration 2\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE2_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE2_A) -> Self { + variant as _ + } +} +#[doc = "Field `SENSE2` reader - Input Sense Configuration 2"] +pub struct SENSE2_R(crate::FieldReader); +impl SENSE2_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SENSE2_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE2_A::NONE), + 1 => Some(SENSE2_A::RISE), + 2 => Some(SENSE2_A::FALL), + 3 => Some(SENSE2_A::BOTH), + 4 => Some(SENSE2_A::HIGH), + 5 => Some(SENSE2_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == SENSE2_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == SENSE2_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == SENSE2_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == SENSE2_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SENSE2_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SENSE2_A::LOW + } +} +impl core::ops::Deref for SENSE2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SENSE2` writer - Input Sense Configuration 2"] +pub struct SENSE2_W<'a> { + w: &'a mut W, +} +impl<'a> SENSE2_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SENSE2_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE2_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE2_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE2_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE2_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE2_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE2_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +#[doc = "Field `FILTEN2` reader - Filter Enable 2"] +pub struct FILTEN2_R(crate::FieldReader); +impl FILTEN2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FILTEN2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTEN2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTEN2` writer - Filter Enable 2"] +pub struct FILTEN2_W<'a> { + w: &'a mut W, +} +impl<'a> FILTEN2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Input Sense Configuration 3\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE3_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE3_A) -> Self { + variant as _ + } +} +#[doc = "Field `SENSE3` reader - Input Sense Configuration 3"] +pub struct SENSE3_R(crate::FieldReader); +impl SENSE3_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SENSE3_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE3_A::NONE), + 1 => Some(SENSE3_A::RISE), + 2 => Some(SENSE3_A::FALL), + 3 => Some(SENSE3_A::BOTH), + 4 => Some(SENSE3_A::HIGH), + 5 => Some(SENSE3_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == SENSE3_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == SENSE3_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == SENSE3_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == SENSE3_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SENSE3_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SENSE3_A::LOW + } +} +impl core::ops::Deref for SENSE3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SENSE3` writer - Input Sense Configuration 3"] +pub struct SENSE3_W<'a> { + w: &'a mut W, +} +impl<'a> SENSE3_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SENSE3_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE3_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE3_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE3_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE3_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE3_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE3_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 12)) | ((value as u32 & 0x07) << 12); + self.w + } +} +#[doc = "Field `FILTEN3` reader - Filter Enable 3"] +pub struct FILTEN3_R(crate::FieldReader); +impl FILTEN3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FILTEN3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTEN3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTEN3` writer - Filter Enable 3"] +pub struct FILTEN3_W<'a> { + w: &'a mut W, +} +impl<'a> FILTEN3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Input Sense Configuration 4\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE4_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE4_A) -> Self { + variant as _ + } +} +#[doc = "Field `SENSE4` reader - Input Sense Configuration 4"] +pub struct SENSE4_R(crate::FieldReader); +impl SENSE4_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SENSE4_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE4_A::NONE), + 1 => Some(SENSE4_A::RISE), + 2 => Some(SENSE4_A::FALL), + 3 => Some(SENSE4_A::BOTH), + 4 => Some(SENSE4_A::HIGH), + 5 => Some(SENSE4_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == SENSE4_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == SENSE4_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == SENSE4_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == SENSE4_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SENSE4_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SENSE4_A::LOW + } +} +impl core::ops::Deref for SENSE4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SENSE4` writer - Input Sense Configuration 4"] +pub struct SENSE4_W<'a> { + w: &'a mut W, +} +impl<'a> SENSE4_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SENSE4_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE4_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE4_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE4_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE4_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE4_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE4_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 16)) | ((value as u32 & 0x07) << 16); + self.w + } +} +#[doc = "Field `FILTEN4` reader - Filter Enable 4"] +pub struct FILTEN4_R(crate::FieldReader); +impl FILTEN4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FILTEN4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTEN4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTEN4` writer - Filter Enable 4"] +pub struct FILTEN4_W<'a> { + w: &'a mut W, +} +impl<'a> FILTEN4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Input Sense Configuration 5\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE5_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE5_A) -> Self { + variant as _ + } +} +#[doc = "Field `SENSE5` reader - Input Sense Configuration 5"] +pub struct SENSE5_R(crate::FieldReader); +impl SENSE5_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SENSE5_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE5_A::NONE), + 1 => Some(SENSE5_A::RISE), + 2 => Some(SENSE5_A::FALL), + 3 => Some(SENSE5_A::BOTH), + 4 => Some(SENSE5_A::HIGH), + 5 => Some(SENSE5_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == SENSE5_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == SENSE5_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == SENSE5_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == SENSE5_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SENSE5_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SENSE5_A::LOW + } +} +impl core::ops::Deref for SENSE5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SENSE5` writer - Input Sense Configuration 5"] +pub struct SENSE5_W<'a> { + w: &'a mut W, +} +impl<'a> SENSE5_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SENSE5_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE5_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE5_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE5_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE5_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE5_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE5_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 20)) | ((value as u32 & 0x07) << 20); + self.w + } +} +#[doc = "Field `FILTEN5` reader - Filter Enable 5"] +pub struct FILTEN5_R(crate::FieldReader); +impl FILTEN5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FILTEN5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTEN5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTEN5` writer - Filter Enable 5"] +pub struct FILTEN5_W<'a> { + w: &'a mut W, +} +impl<'a> FILTEN5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Input Sense Configuration 6\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE6_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE6_A) -> Self { + variant as _ + } +} +#[doc = "Field `SENSE6` reader - Input Sense Configuration 6"] +pub struct SENSE6_R(crate::FieldReader); +impl SENSE6_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SENSE6_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE6_A::NONE), + 1 => Some(SENSE6_A::RISE), + 2 => Some(SENSE6_A::FALL), + 3 => Some(SENSE6_A::BOTH), + 4 => Some(SENSE6_A::HIGH), + 5 => Some(SENSE6_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == SENSE6_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == SENSE6_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == SENSE6_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == SENSE6_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SENSE6_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SENSE6_A::LOW + } +} +impl core::ops::Deref for SENSE6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SENSE6` writer - Input Sense Configuration 6"] +pub struct SENSE6_W<'a> { + w: &'a mut W, +} +impl<'a> SENSE6_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SENSE6_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE6_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE6_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE6_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE6_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE6_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE6_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 24)) | ((value as u32 & 0x07) << 24); + self.w + } +} +#[doc = "Field `FILTEN6` reader - Filter Enable 6"] +pub struct FILTEN6_R(crate::FieldReader); +impl FILTEN6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FILTEN6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTEN6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTEN6` writer - Filter Enable 6"] +pub struct FILTEN6_W<'a> { + w: &'a mut W, +} +impl<'a> FILTEN6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +#[doc = "Input Sense Configuration 7\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE7_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE7_A) -> Self { + variant as _ + } +} +#[doc = "Field `SENSE7` reader - Input Sense Configuration 7"] +pub struct SENSE7_R(crate::FieldReader); +impl SENSE7_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SENSE7_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE7_A::NONE), + 1 => Some(SENSE7_A::RISE), + 2 => Some(SENSE7_A::FALL), + 3 => Some(SENSE7_A::BOTH), + 4 => Some(SENSE7_A::HIGH), + 5 => Some(SENSE7_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == SENSE7_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == SENSE7_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == SENSE7_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == SENSE7_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SENSE7_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SENSE7_A::LOW + } +} +impl core::ops::Deref for SENSE7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SENSE7` writer - Input Sense Configuration 7"] +pub struct SENSE7_W<'a> { + w: &'a mut W, +} +impl<'a> SENSE7_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SENSE7_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE7_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE7_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE7_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE7_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE7_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE7_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 28)) | ((value as u32 & 0x07) << 28); + self.w + } +} +#[doc = "Field `FILTEN7` reader - Filter Enable 7"] +pub struct FILTEN7_R(crate::FieldReader); +impl FILTEN7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FILTEN7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTEN7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTEN7` writer - Filter Enable 7"] +pub struct FILTEN7_W<'a> { + w: &'a mut W, +} +impl<'a> FILTEN7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Input Sense Configuration 0"] + #[inline(always)] + pub fn sense0(&self) -> SENSE0_R { + SENSE0_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 3 - Filter Enable 0"] + #[inline(always)] + pub fn filten0(&self) -> FILTEN0_R { + FILTEN0_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bits 4:6 - Input Sense Configuration 1"] + #[inline(always)] + pub fn sense1(&self) -> SENSE1_R { + SENSE1_R::new(((self.bits >> 4) & 0x07) as u8) + } + #[doc = "Bit 7 - Filter Enable 1"] + #[inline(always)] + pub fn filten1(&self) -> FILTEN1_R { + FILTEN1_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Input Sense Configuration 2"] + #[inline(always)] + pub fn sense2(&self) -> SENSE2_R { + SENSE2_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 11 - Filter Enable 2"] + #[inline(always)] + pub fn filten2(&self) -> FILTEN2_R { + FILTEN2_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bits 12:14 - Input Sense Configuration 3"] + #[inline(always)] + pub fn sense3(&self) -> SENSE3_R { + SENSE3_R::new(((self.bits >> 12) & 0x07) as u8) + } + #[doc = "Bit 15 - Filter Enable 3"] + #[inline(always)] + pub fn filten3(&self) -> FILTEN3_R { + FILTEN3_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:18 - Input Sense Configuration 4"] + #[inline(always)] + pub fn sense4(&self) -> SENSE4_R { + SENSE4_R::new(((self.bits >> 16) & 0x07) as u8) + } + #[doc = "Bit 19 - Filter Enable 4"] + #[inline(always)] + pub fn filten4(&self) -> FILTEN4_R { + FILTEN4_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bits 20:22 - Input Sense Configuration 5"] + #[inline(always)] + pub fn sense5(&self) -> SENSE5_R { + SENSE5_R::new(((self.bits >> 20) & 0x07) as u8) + } + #[doc = "Bit 23 - Filter Enable 5"] + #[inline(always)] + pub fn filten5(&self) -> FILTEN5_R { + FILTEN5_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bits 24:26 - Input Sense Configuration 6"] + #[inline(always)] + pub fn sense6(&self) -> SENSE6_R { + SENSE6_R::new(((self.bits >> 24) & 0x07) as u8) + } + #[doc = "Bit 27 - Filter Enable 6"] + #[inline(always)] + pub fn filten6(&self) -> FILTEN6_R { + FILTEN6_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bits 28:30 - Input Sense Configuration 7"] + #[inline(always)] + pub fn sense7(&self) -> SENSE7_R { + SENSE7_R::new(((self.bits >> 28) & 0x07) as u8) + } + #[doc = "Bit 31 - Filter Enable 7"] + #[inline(always)] + pub fn filten7(&self) -> FILTEN7_R { + FILTEN7_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Input Sense Configuration 0"] + #[inline(always)] + pub fn sense0(&mut self) -> SENSE0_W { + SENSE0_W { w: self } + } + #[doc = "Bit 3 - Filter Enable 0"] + #[inline(always)] + pub fn filten0(&mut self) -> FILTEN0_W { + FILTEN0_W { w: self } + } + #[doc = "Bits 4:6 - Input Sense Configuration 1"] + #[inline(always)] + pub fn sense1(&mut self) -> SENSE1_W { + SENSE1_W { w: self } + } + #[doc = "Bit 7 - Filter Enable 1"] + #[inline(always)] + pub fn filten1(&mut self) -> FILTEN1_W { + FILTEN1_W { w: self } + } + #[doc = "Bits 8:10 - Input Sense Configuration 2"] + #[inline(always)] + pub fn sense2(&mut self) -> SENSE2_W { + SENSE2_W { w: self } + } + #[doc = "Bit 11 - Filter Enable 2"] + #[inline(always)] + pub fn filten2(&mut self) -> FILTEN2_W { + FILTEN2_W { w: self } + } + #[doc = "Bits 12:14 - Input Sense Configuration 3"] + #[inline(always)] + pub fn sense3(&mut self) -> SENSE3_W { + SENSE3_W { w: self } + } + #[doc = "Bit 15 - Filter Enable 3"] + #[inline(always)] + pub fn filten3(&mut self) -> FILTEN3_W { + FILTEN3_W { w: self } + } + #[doc = "Bits 16:18 - Input Sense Configuration 4"] + #[inline(always)] + pub fn sense4(&mut self) -> SENSE4_W { + SENSE4_W { w: self } + } + #[doc = "Bit 19 - Filter Enable 4"] + #[inline(always)] + pub fn filten4(&mut self) -> FILTEN4_W { + FILTEN4_W { w: self } + } + #[doc = "Bits 20:22 - Input Sense Configuration 5"] + #[inline(always)] + pub fn sense5(&mut self) -> SENSE5_W { + SENSE5_W { w: self } + } + #[doc = "Bit 23 - Filter Enable 5"] + #[inline(always)] + pub fn filten5(&mut self) -> FILTEN5_W { + FILTEN5_W { w: self } + } + #[doc = "Bits 24:26 - Input Sense Configuration 6"] + #[inline(always)] + pub fn sense6(&mut self) -> SENSE6_W { + SENSE6_W { w: self } + } + #[doc = "Bit 27 - Filter Enable 6"] + #[inline(always)] + pub fn filten6(&mut self) -> FILTEN6_W { + FILTEN6_W { w: self } + } + #[doc = "Bits 28:30 - Input Sense Configuration 7"] + #[inline(always)] + pub fn sense7(&mut self) -> SENSE7_W { + SENSE7_W { w: self } + } + #[doc = "Bit 31 - Filter Enable 7"] + #[inline(always)] + pub fn filten7(&mut self) -> FILTEN7_W { + FILTEN7_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Configuration n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [config](index.html) module"] +pub struct CONFIG_SPEC; +impl crate::RegisterSpec for CONFIG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [config::R](R) reader structure"] +impl crate::Readable for CONFIG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [config::W](W) writer structure"] +impl crate::Writable for CONFIG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CONFIG[%s] +to value 0"] +impl crate::Resettable for CONFIG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/eic/ctrla.rs b/pac/atsamc20g/src/eic/ctrla.rs new file mode 100644 index 000000000000..25e701dd3db2 --- /dev/null +++ b/pac/atsamc20g/src/eic/ctrla.rs @@ -0,0 +1,254 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Clock Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CKSEL_A { + #[doc = "0: Clocked by GCLK"] + CLK_GCLK = 0, + #[doc = "1: Clocked by ULP32K"] + CLK_ULP32K = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CKSEL_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CKSEL` reader - Clock Selection"] +pub struct CKSEL_R(crate::FieldReader); +impl CKSEL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CKSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CKSEL_A { + match self.bits { + false => CKSEL_A::CLK_GCLK, + true => CKSEL_A::CLK_ULP32K, + } + } + #[doc = "Checks if the value of the field is `CLK_GCLK`"] + #[inline(always)] + pub fn is_clk_gclk(&self) -> bool { + **self == CKSEL_A::CLK_GCLK + } + #[doc = "Checks if the value of the field is `CLK_ULP32K`"] + #[inline(always)] + pub fn is_clk_ulp32k(&self) -> bool { + **self == CKSEL_A::CLK_ULP32K + } +} +impl core::ops::Deref for CKSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CKSEL` writer - Clock Selection"] +pub struct CKSEL_W<'a> { + w: &'a mut W, +} +impl<'a> CKSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CKSEL_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Clocked by GCLK"] + #[inline(always)] + pub fn clk_gclk(self) -> &'a mut W { + self.variant(CKSEL_A::CLK_GCLK) + } + #[doc = "Clocked by ULP32K"] + #[inline(always)] + pub fn clk_ulp32k(self) -> &'a mut W { + self.variant(CKSEL_A::CLK_ULP32K) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - Clock Selection"] + #[inline(always)] + pub fn cksel(&self) -> CKSEL_R { + CKSEL_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 4 - Clock Selection"] + #[inline(always)] + pub fn cksel(&mut self) -> CKSEL_W { + CKSEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/eic/evctrl.rs b/pac/atsamc20g/src/eic/evctrl.rs new file mode 100644 index 000000000000..25adccf3558e --- /dev/null +++ b/pac/atsamc20g/src/eic/evctrl.rs @@ -0,0 +1,103 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EXTINTEO` reader - External Interrupt Event Output Enable"] +pub struct EXTINTEO_R(crate::FieldReader); +impl EXTINTEO_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + EXTINTEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINTEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINTEO` writer - External Interrupt Event Output Enable"] +pub struct EXTINTEO_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINTEO_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - External Interrupt Event Output Enable"] + #[inline(always)] + pub fn extinteo(&self) -> EXTINTEO_R { + EXTINTEO_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - External Interrupt Event Output Enable"] + #[inline(always)] + pub fn extinteo(&mut self) -> EXTINTEO_W { + EXTINTEO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/eic/intenclr.rs b/pac/atsamc20g/src/eic/intenclr.rs new file mode 100644 index 000000000000..198c3aac9eb1 --- /dev/null +++ b/pac/atsamc20g/src/eic/intenclr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EXTINT` reader - External Interrupt Disable"] +pub struct EXTINT_R(crate::FieldReader); +impl EXTINT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + EXTINT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT` writer - External Interrupt Disable"] +pub struct EXTINT_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - External Interrupt Disable"] + #[inline(always)] + pub fn extint(&self) -> EXTINT_R { + EXTINT_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - External Interrupt Disable"] + #[inline(always)] + pub fn extint(&mut self) -> EXTINT_W { + EXTINT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/eic/intenset.rs b/pac/atsamc20g/src/eic/intenset.rs new file mode 100644 index 000000000000..e2ff6729d71f --- /dev/null +++ b/pac/atsamc20g/src/eic/intenset.rs @@ -0,0 +1,103 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EXTINT` reader - External Interrupt Enable"] +pub struct EXTINT_R(crate::FieldReader); +impl EXTINT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + EXTINT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT` writer - External Interrupt Enable"] +pub struct EXTINT_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - External Interrupt Enable"] + #[inline(always)] + pub fn extint(&self) -> EXTINT_R { + EXTINT_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - External Interrupt Enable"] + #[inline(always)] + pub fn extint(&mut self) -> EXTINT_W { + EXTINT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/eic/intflag.rs b/pac/atsamc20g/src/eic/intflag.rs new file mode 100644 index 000000000000..df2f15490feb --- /dev/null +++ b/pac/atsamc20g/src/eic/intflag.rs @@ -0,0 +1,103 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EXTINT` reader - External Interrupt Flag"] +pub struct EXTINT_R(crate::FieldReader); +impl EXTINT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + EXTINT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT` writer - External Interrupt Flag"] +pub struct EXTINT_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - External Interrupt Flag"] + #[inline(always)] + pub fn extint(&self) -> EXTINT_R { + EXTINT_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - External Interrupt Flag"] + #[inline(always)] + pub fn extint(&mut self) -> EXTINT_W { + EXTINT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/eic/nmictrl.rs b/pac/atsamc20g/src/eic/nmictrl.rs new file mode 100644 index 000000000000..c9b276ea2a29 --- /dev/null +++ b/pac/atsamc20g/src/eic/nmictrl.rs @@ -0,0 +1,345 @@ +#[doc = "Register `NMICTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `NMICTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "NMI Input Sense Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum NMISENSE_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising-edge detection"] + RISE = 1, + #[doc = "2: Falling-edge detection"] + FALL = 2, + #[doc = "3: Both-edges detection"] + BOTH = 3, + #[doc = "4: High-level detection"] + HIGH = 4, + #[doc = "5: Low-level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: NMISENSE_A) -> Self { + variant as _ + } +} +#[doc = "Field `NMISENSE` reader - NMI Input Sense Configuration"] +pub struct NMISENSE_R(crate::FieldReader); +impl NMISENSE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + NMISENSE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(NMISENSE_A::NONE), + 1 => Some(NMISENSE_A::RISE), + 2 => Some(NMISENSE_A::FALL), + 3 => Some(NMISENSE_A::BOTH), + 4 => Some(NMISENSE_A::HIGH), + 5 => Some(NMISENSE_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == NMISENSE_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == NMISENSE_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == NMISENSE_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == NMISENSE_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == NMISENSE_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == NMISENSE_A::LOW + } +} +impl core::ops::Deref for NMISENSE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NMISENSE` writer - NMI Input Sense Configuration"] +pub struct NMISENSE_W<'a> { + w: &'a mut W, +} +impl<'a> NMISENSE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: NMISENSE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(NMISENSE_A::NONE) + } + #[doc = "Rising-edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(NMISENSE_A::RISE) + } + #[doc = "Falling-edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(NMISENSE_A::FALL) + } + #[doc = "Both-edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(NMISENSE_A::BOTH) + } + #[doc = "High-level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(NMISENSE_A::HIGH) + } + #[doc = "Low-level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(NMISENSE_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +#[doc = "Field `NMIFILTEN` reader - NMI Filter Enable"] +pub struct NMIFILTEN_R(crate::FieldReader); +impl NMIFILTEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NMIFILTEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NMIFILTEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NMIFILTEN` writer - NMI Filter Enable"] +pub struct NMIFILTEN_W<'a> { + w: &'a mut W, +} +impl<'a> NMIFILTEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "NMI Asynchronous edge Detection Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum NMIASYNCH_A { + #[doc = "0: Edge detection is clock synchronously operated"] + SYNC = 0, + #[doc = "1: Edge detection is clock asynchronously operated"] + ASYNC = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NMIASYNCH_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NMIASYNCH` reader - NMI Asynchronous edge Detection Enable"] +pub struct NMIASYNCH_R(crate::FieldReader); +impl NMIASYNCH_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NMIASYNCH_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> NMIASYNCH_A { + match self.bits { + false => NMIASYNCH_A::SYNC, + true => NMIASYNCH_A::ASYNC, + } + } + #[doc = "Checks if the value of the field is `SYNC`"] + #[inline(always)] + pub fn is_sync(&self) -> bool { + **self == NMIASYNCH_A::SYNC + } + #[doc = "Checks if the value of the field is `ASYNC`"] + #[inline(always)] + pub fn is_async(&self) -> bool { + **self == NMIASYNCH_A::ASYNC + } +} +impl core::ops::Deref for NMIASYNCH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NMIASYNCH` writer - NMI Asynchronous edge Detection Enable"] +pub struct NMIASYNCH_W<'a> { + w: &'a mut W, +} +impl<'a> NMIASYNCH_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: NMIASYNCH_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Edge detection is clock synchronously operated"] + #[inline(always)] + pub fn sync(self) -> &'a mut W { + self.variant(NMIASYNCH_A::SYNC) + } + #[doc = "Edge detection is clock asynchronously operated"] + #[inline(always)] + pub fn async_(self) -> &'a mut W { + self.variant(NMIASYNCH_A::ASYNC) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - NMI Input Sense Configuration"] + #[inline(always)] + pub fn nmisense(&self) -> NMISENSE_R { + NMISENSE_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 3 - NMI Filter Enable"] + #[inline(always)] + pub fn nmifilten(&self) -> NMIFILTEN_R { + NMIFILTEN_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - NMI Asynchronous edge Detection Enable"] + #[inline(always)] + pub fn nmiasynch(&self) -> NMIASYNCH_R { + NMIASYNCH_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - NMI Input Sense Configuration"] + #[inline(always)] + pub fn nmisense(&mut self) -> NMISENSE_W { + NMISENSE_W { w: self } + } + #[doc = "Bit 3 - NMI Filter Enable"] + #[inline(always)] + pub fn nmifilten(&mut self) -> NMIFILTEN_W { + NMIFILTEN_W { w: self } + } + #[doc = "Bit 4 - NMI Asynchronous edge Detection Enable"] + #[inline(always)] + pub fn nmiasynch(&mut self) -> NMIASYNCH_W { + NMIASYNCH_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "NMI Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [nmictrl](index.html) module"] +pub struct NMICTRL_SPEC; +impl crate::RegisterSpec for NMICTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [nmictrl::R](R) reader structure"] +impl crate::Readable for NMICTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [nmictrl::W](W) writer structure"] +impl crate::Writable for NMICTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets NMICTRL to value 0"] +impl crate::Resettable for NMICTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/eic/nmiflag.rs b/pac/atsamc20g/src/eic/nmiflag.rs new file mode 100644 index 000000000000..97934b501c12 --- /dev/null +++ b/pac/atsamc20g/src/eic/nmiflag.rs @@ -0,0 +1,113 @@ +#[doc = "Register `NMIFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `NMIFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `NMI` reader - NMI Interrupt Flag"] +pub struct NMI_R(crate::FieldReader); +impl NMI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NMI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NMI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NMI` writer - NMI Interrupt Flag"] +pub struct NMI_W<'a> { + w: &'a mut W, +} +impl<'a> NMI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - NMI Interrupt Flag"] + #[inline(always)] + pub fn nmi(&self) -> NMI_R { + NMI_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - NMI Interrupt Flag"] + #[inline(always)] + pub fn nmi(&mut self) -> NMI_W { + NMI_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "NMI Interrupt Flag\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [nmiflag](index.html) module"] +pub struct NMIFLAG_SPEC; +impl crate::RegisterSpec for NMIFLAG_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [nmiflag::R](R) reader structure"] +impl crate::Readable for NMIFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [nmiflag::W](W) writer structure"] +impl crate::Writable for NMIFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets NMIFLAG to value 0"] +impl crate::Resettable for NMIFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/eic/syncbusy.rs b/pac/atsamc20g/src/eic/syncbusy.rs new file mode 100644 index 000000000000..84d125d0acf1 --- /dev/null +++ b/pac/atsamc20g/src/eic/syncbusy.rs @@ -0,0 +1,73 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software reset synchronisation"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - Enable synchronisation"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software reset synchronisation"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable synchronisation"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +#[doc = "Syncbusy register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/evsys.rs b/pac/atsamc20g/src/evsys.rs new file mode 100644 index 000000000000..20d569fd3b90 --- /dev/null +++ b/pac/atsamc20g/src/evsys.rs @@ -0,0 +1,54 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrla: crate::Reg, + _reserved1: [u8; 0x0b], + #[doc = "0x0c - Channel Status"] + pub chstatus: crate::Reg, + #[doc = "0x10 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x14 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x18 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x1c - Software Event"] + pub swevt: crate::Reg, + #[doc = "0x20..0x38 - Channel n"] + pub channel: [crate::Reg; 6], + _reserved7: [u8; 0x48], + #[doc = "0x80..0x13c - User Multiplexer n"] + pub user: [crate::Reg; 47], +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control"] +pub mod ctrla; +#[doc = "CHSTATUS register accessor: an alias for `Reg`"] +pub type CHSTATUS = crate::Reg; +#[doc = "Channel Status"] +pub mod chstatus; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "SWEVT register accessor: an alias for `Reg`"] +pub type SWEVT = crate::Reg; +#[doc = "Software Event"] +pub mod swevt; +#[doc = "CHANNEL register accessor: an alias for `Reg`"] +pub type CHANNEL = crate::Reg; +#[doc = "Channel n"] +pub mod channel; +#[doc = "USER register accessor: an alias for `Reg`"] +pub type USER = crate::Reg; +#[doc = "User Multiplexer n"] +pub mod user; diff --git a/pac/atsamc20g/src/evsys/channel.rs b/pac/atsamc20g/src/evsys/channel.rs new file mode 100644 index 000000000000..20e3857da922 --- /dev/null +++ b/pac/atsamc20g/src/evsys/channel.rs @@ -0,0 +1,409 @@ +#[doc = "Register `CHANNEL[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHANNEL[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVGEN` reader - Event Generator Selection"] +pub struct EVGEN_R(crate::FieldReader); +impl EVGEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVGEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVGEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVGEN` writer - Event Generator Selection"] +pub struct EVGEN_W<'a> { + w: &'a mut W, +} +impl<'a> EVGEN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x7f) | (value as u32 & 0x7f); + self.w + } +} +#[doc = "Path Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PATH_A { + #[doc = "0: Synchronous path"] + SYNCHRONOUS = 0, + #[doc = "1: Resynchronized path"] + RESYNCHRONIZED = 1, + #[doc = "2: Asynchronous path"] + ASYNCHRONOUS = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PATH_A) -> Self { + variant as _ + } +} +#[doc = "Field `PATH` reader - Path Selection"] +pub struct PATH_R(crate::FieldReader); +impl PATH_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PATH_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PATH_A::SYNCHRONOUS), + 1 => Some(PATH_A::RESYNCHRONIZED), + 2 => Some(PATH_A::ASYNCHRONOUS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `SYNCHRONOUS`"] + #[inline(always)] + pub fn is_synchronous(&self) -> bool { + **self == PATH_A::SYNCHRONOUS + } + #[doc = "Checks if the value of the field is `RESYNCHRONIZED`"] + #[inline(always)] + pub fn is_resynchronized(&self) -> bool { + **self == PATH_A::RESYNCHRONIZED + } + #[doc = "Checks if the value of the field is `ASYNCHRONOUS`"] + #[inline(always)] + pub fn is_asynchronous(&self) -> bool { + **self == PATH_A::ASYNCHRONOUS + } +} +impl core::ops::Deref for PATH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PATH` writer - Path Selection"] +pub struct PATH_W<'a> { + w: &'a mut W, +} +impl<'a> PATH_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PATH_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Synchronous path"] + #[inline(always)] + pub fn synchronous(self) -> &'a mut W { + self.variant(PATH_A::SYNCHRONOUS) + } + #[doc = "Resynchronized path"] + #[inline(always)] + pub fn resynchronized(self) -> &'a mut W { + self.variant(PATH_A::RESYNCHRONIZED) + } + #[doc = "Asynchronous path"] + #[inline(always)] + pub fn asynchronous(self) -> &'a mut W { + self.variant(PATH_A::ASYNCHRONOUS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 8)) | ((value as u32 & 0x03) << 8); + self.w + } +} +#[doc = "Edge Detection Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EDGSEL_A { + #[doc = "0: No event output when using the resynchronized or synchronous path"] + NO_EVT_OUTPUT = 0, + #[doc = "1: Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path"] + RISING_EDGE = 1, + #[doc = "2: Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path"] + FALLING_EDGE = 2, + #[doc = "3: Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path"] + BOTH_EDGES = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EDGSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `EDGSEL` reader - Edge Detection Selection"] +pub struct EDGSEL_R(crate::FieldReader); +impl EDGSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EDGSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EDGSEL_A { + match self.bits { + 0 => EDGSEL_A::NO_EVT_OUTPUT, + 1 => EDGSEL_A::RISING_EDGE, + 2 => EDGSEL_A::FALLING_EDGE, + 3 => EDGSEL_A::BOTH_EDGES, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NO_EVT_OUTPUT`"] + #[inline(always)] + pub fn is_no_evt_output(&self) -> bool { + **self == EDGSEL_A::NO_EVT_OUTPUT + } + #[doc = "Checks if the value of the field is `RISING_EDGE`"] + #[inline(always)] + pub fn is_rising_edge(&self) -> bool { + **self == EDGSEL_A::RISING_EDGE + } + #[doc = "Checks if the value of the field is `FALLING_EDGE`"] + #[inline(always)] + pub fn is_falling_edge(&self) -> bool { + **self == EDGSEL_A::FALLING_EDGE + } + #[doc = "Checks if the value of the field is `BOTH_EDGES`"] + #[inline(always)] + pub fn is_both_edges(&self) -> bool { + **self == EDGSEL_A::BOTH_EDGES + } +} +impl core::ops::Deref for EDGSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EDGSEL` writer - Edge Detection Selection"] +pub struct EDGSEL_W<'a> { + w: &'a mut W, +} +impl<'a> EDGSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EDGSEL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "No event output when using the resynchronized or synchronous path"] + #[inline(always)] + pub fn no_evt_output(self) -> &'a mut W { + self.variant(EDGSEL_A::NO_EVT_OUTPUT) + } + #[doc = "Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path"] + #[inline(always)] + pub fn rising_edge(self) -> &'a mut W { + self.variant(EDGSEL_A::RISING_EDGE) + } + #[doc = "Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path"] + #[inline(always)] + pub fn falling_edge(self) -> &'a mut W { + self.variant(EDGSEL_A::FALLING_EDGE) + } + #[doc = "Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path"] + #[inline(always)] + pub fn both_edges(self) -> &'a mut W { + self.variant(EDGSEL_A::BOTH_EDGES) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 10)) | ((value as u32 & 0x03) << 10); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - Generic Clock On Demand"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - Generic Clock On Demand"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bits 0:6 - Event Generator Selection"] + #[inline(always)] + pub fn evgen(&self) -> EVGEN_R { + EVGEN_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bits 8:9 - Path Selection"] + #[inline(always)] + pub fn path(&self) -> PATH_R { + PATH_R::new(((self.bits >> 8) & 0x03) as u8) + } + #[doc = "Bits 10:11 - Edge Detection Selection"] + #[inline(always)] + pub fn edgsel(&self) -> EDGSEL_R { + EDGSEL_R::new(((self.bits >> 10) & 0x03) as u8) + } + #[doc = "Bit 14 - Run in standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Generic Clock On Demand"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:6 - Event Generator Selection"] + #[inline(always)] + pub fn evgen(&mut self) -> EVGEN_W { + EVGEN_W { w: self } + } + #[doc = "Bits 8:9 - Path Selection"] + #[inline(always)] + pub fn path(&mut self) -> PATH_W { + PATH_W { w: self } + } + #[doc = "Bits 10:11 - Edge Detection Selection"] + #[inline(always)] + pub fn edgsel(&mut self) -> EDGSEL_W { + EDGSEL_W { w: self } + } + #[doc = "Bit 14 - Run in standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 15 - Generic Clock On Demand"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [channel](index.html) module"] +pub struct CHANNEL_SPEC; +impl crate::RegisterSpec for CHANNEL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [channel::R](R) reader structure"] +impl crate::Readable for CHANNEL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [channel::W](W) writer structure"] +impl crate::Writable for CHANNEL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHANNEL[%s] +to value 0x8000"] +impl crate::Resettable for CHANNEL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x8000 + } +} diff --git a/pac/atsamc20g/src/evsys/chstatus.rs b/pac/atsamc20g/src/evsys/chstatus.rs new file mode 100644 index 000000000000..43004730356d --- /dev/null +++ b/pac/atsamc20g/src/evsys/chstatus.rs @@ -0,0 +1,273 @@ +#[doc = "Register `CHSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `USRRDY0` reader - Channel 0 User Ready"] +pub struct USRRDY0_R(crate::FieldReader); +impl USRRDY0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY1` reader - Channel 1 User Ready"] +pub struct USRRDY1_R(crate::FieldReader); +impl USRRDY1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY2` reader - Channel 2 User Ready"] +pub struct USRRDY2_R(crate::FieldReader); +impl USRRDY2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY3` reader - Channel 3 User Ready"] +pub struct USRRDY3_R(crate::FieldReader); +impl USRRDY3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY4` reader - Channel 4 User Ready"] +pub struct USRRDY4_R(crate::FieldReader); +impl USRRDY4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY5` reader - Channel 5 User Ready"] +pub struct USRRDY5_R(crate::FieldReader); +impl USRRDY5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY0` reader - Channel 0 Busy"] +pub struct CHBUSY0_R(crate::FieldReader); +impl CHBUSY0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY1` reader - Channel 1 Busy"] +pub struct CHBUSY1_R(crate::FieldReader); +impl CHBUSY1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY2` reader - Channel 2 Busy"] +pub struct CHBUSY2_R(crate::FieldReader); +impl CHBUSY2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY3` reader - Channel 3 Busy"] +pub struct CHBUSY3_R(crate::FieldReader); +impl CHBUSY3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY4` reader - Channel 4 Busy"] +pub struct CHBUSY4_R(crate::FieldReader); +impl CHBUSY4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY5` reader - Channel 5 Busy"] +pub struct CHBUSY5_R(crate::FieldReader); +impl CHBUSY5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Channel 0 User Ready"] + #[inline(always)] + pub fn usrrdy0(&self) -> USRRDY0_R { + USRRDY0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel 1 User Ready"] + #[inline(always)] + pub fn usrrdy1(&self) -> USRRDY1_R { + USRRDY1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel 2 User Ready"] + #[inline(always)] + pub fn usrrdy2(&self) -> USRRDY2_R { + USRRDY2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Channel 3 User Ready"] + #[inline(always)] + pub fn usrrdy3(&self) -> USRRDY3_R { + USRRDY3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Channel 4 User Ready"] + #[inline(always)] + pub fn usrrdy4(&self) -> USRRDY4_R { + USRRDY4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Channel 5 User Ready"] + #[inline(always)] + pub fn usrrdy5(&self) -> USRRDY5_R { + USRRDY5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 16 - Channel 0 Busy"] + #[inline(always)] + pub fn chbusy0(&self) -> CHBUSY0_R { + CHBUSY0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Channel 1 Busy"] + #[inline(always)] + pub fn chbusy1(&self) -> CHBUSY1_R { + CHBUSY1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Channel 2 Busy"] + #[inline(always)] + pub fn chbusy2(&self) -> CHBUSY2_R { + CHBUSY2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Channel 3 Busy"] + #[inline(always)] + pub fn chbusy3(&self) -> CHBUSY3_R { + CHBUSY3_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Channel 4 Busy"] + #[inline(always)] + pub fn chbusy4(&self) -> CHBUSY4_R { + CHBUSY4_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Channel 5 Busy"] + #[inline(always)] + pub fn chbusy5(&self) -> CHBUSY5_R { + CHBUSY5_R::new(((self.bits >> 21) & 0x01) != 0) + } +} +#[doc = "Channel Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chstatus](index.html) module"] +pub struct CHSTATUS_SPEC; +impl crate::RegisterSpec for CHSTATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [chstatus::R](R) reader structure"] +impl crate::Readable for CHSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CHSTATUS to value 0"] +impl crate::Resettable for CHSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/evsys/ctrla.rs b/pac/atsamc20g/src/evsys/ctrla.rs new file mode 100644 index 000000000000..1c24704395ad --- /dev/null +++ b/pac/atsamc20g/src/evsys/ctrla.rs @@ -0,0 +1,113 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/evsys/intenclr.rs b/pac/atsamc20g/src/evsys/intenclr.rs new file mode 100644 index 000000000000..60271a5e2e70 --- /dev/null +++ b/pac/atsamc20g/src/evsys/intenclr.rs @@ -0,0 +1,630 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVR0` reader - Channel 0 Overrun Interrupt Enable"] +pub struct OVR0_R(crate::FieldReader); +impl OVR0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR0` writer - Channel 0 Overrun Interrupt Enable"] +pub struct OVR0_W<'a> { + w: &'a mut W, +} +impl<'a> OVR0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `OVR1` reader - Channel 1 Overrun Interrupt Enable"] +pub struct OVR1_R(crate::FieldReader); +impl OVR1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR1` writer - Channel 1 Overrun Interrupt Enable"] +pub struct OVR1_W<'a> { + w: &'a mut W, +} +impl<'a> OVR1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `OVR2` reader - Channel 2 Overrun Interrupt Enable"] +pub struct OVR2_R(crate::FieldReader); +impl OVR2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR2` writer - Channel 2 Overrun Interrupt Enable"] +pub struct OVR2_W<'a> { + w: &'a mut W, +} +impl<'a> OVR2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `OVR3` reader - Channel 3 Overrun Interrupt Enable"] +pub struct OVR3_R(crate::FieldReader); +impl OVR3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR3` writer - Channel 3 Overrun Interrupt Enable"] +pub struct OVR3_W<'a> { + w: &'a mut W, +} +impl<'a> OVR3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `OVR4` reader - Channel 4 Overrun Interrupt Enable"] +pub struct OVR4_R(crate::FieldReader); +impl OVR4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR4` writer - Channel 4 Overrun Interrupt Enable"] +pub struct OVR4_W<'a> { + w: &'a mut W, +} +impl<'a> OVR4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `OVR5` reader - Channel 5 Overrun Interrupt Enable"] +pub struct OVR5_R(crate::FieldReader); +impl OVR5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR5` writer - Channel 5 Overrun Interrupt Enable"] +pub struct OVR5_W<'a> { + w: &'a mut W, +} +impl<'a> OVR5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `EVD0` reader - Channel 0 Event Detection Interrupt Enable"] +pub struct EVD0_R(crate::FieldReader); +impl EVD0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD0` writer - Channel 0 Event Detection Interrupt Enable"] +pub struct EVD0_W<'a> { + w: &'a mut W, +} +impl<'a> EVD0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `EVD1` reader - Channel 1 Event Detection Interrupt Enable"] +pub struct EVD1_R(crate::FieldReader); +impl EVD1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD1` writer - Channel 1 Event Detection Interrupt Enable"] +pub struct EVD1_W<'a> { + w: &'a mut W, +} +impl<'a> EVD1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `EVD2` reader - Channel 2 Event Detection Interrupt Enable"] +pub struct EVD2_R(crate::FieldReader); +impl EVD2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD2` writer - Channel 2 Event Detection Interrupt Enable"] +pub struct EVD2_W<'a> { + w: &'a mut W, +} +impl<'a> EVD2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `EVD3` reader - Channel 3 Event Detection Interrupt Enable"] +pub struct EVD3_R(crate::FieldReader); +impl EVD3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD3` writer - Channel 3 Event Detection Interrupt Enable"] +pub struct EVD3_W<'a> { + w: &'a mut W, +} +impl<'a> EVD3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `EVD4` reader - Channel 4 Event Detection Interrupt Enable"] +pub struct EVD4_R(crate::FieldReader); +impl EVD4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD4` writer - Channel 4 Event Detection Interrupt Enable"] +pub struct EVD4_W<'a> { + w: &'a mut W, +} +impl<'a> EVD4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `EVD5` reader - Channel 5 Event Detection Interrupt Enable"] +pub struct EVD5_R(crate::FieldReader); +impl EVD5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD5` writer - Channel 5 Event Detection Interrupt Enable"] +pub struct EVD5_W<'a> { + w: &'a mut W, +} +impl<'a> EVD5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +impl R { + #[doc = "Bit 0 - Channel 0 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr0(&self) -> OVR0_R { + OVR0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel 1 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr1(&self) -> OVR1_R { + OVR1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel 2 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr2(&self) -> OVR2_R { + OVR2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Channel 3 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr3(&self) -> OVR3_R { + OVR3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Channel 4 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr4(&self) -> OVR4_R { + OVR4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Channel 5 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr5(&self) -> OVR5_R { + OVR5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 16 - Channel 0 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd0(&self) -> EVD0_R { + EVD0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Channel 1 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd1(&self) -> EVD1_R { + EVD1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Channel 2 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd2(&self) -> EVD2_R { + EVD2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Channel 3 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd3(&self) -> EVD3_R { + EVD3_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Channel 4 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd4(&self) -> EVD4_R { + EVD4_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Channel 5 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd5(&self) -> EVD5_R { + EVD5_R::new(((self.bits >> 21) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel 0 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr0(&mut self) -> OVR0_W { + OVR0_W { w: self } + } + #[doc = "Bit 1 - Channel 1 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr1(&mut self) -> OVR1_W { + OVR1_W { w: self } + } + #[doc = "Bit 2 - Channel 2 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr2(&mut self) -> OVR2_W { + OVR2_W { w: self } + } + #[doc = "Bit 3 - Channel 3 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr3(&mut self) -> OVR3_W { + OVR3_W { w: self } + } + #[doc = "Bit 4 - Channel 4 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr4(&mut self) -> OVR4_W { + OVR4_W { w: self } + } + #[doc = "Bit 5 - Channel 5 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr5(&mut self) -> OVR5_W { + OVR5_W { w: self } + } + #[doc = "Bit 16 - Channel 0 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd0(&mut self) -> EVD0_W { + EVD0_W { w: self } + } + #[doc = "Bit 17 - Channel 1 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd1(&mut self) -> EVD1_W { + EVD1_W { w: self } + } + #[doc = "Bit 18 - Channel 2 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd2(&mut self) -> EVD2_W { + EVD2_W { w: self } + } + #[doc = "Bit 19 - Channel 3 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd3(&mut self) -> EVD3_W { + EVD3_W { w: self } + } + #[doc = "Bit 20 - Channel 4 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd4(&mut self) -> EVD4_W { + EVD4_W { w: self } + } + #[doc = "Bit 21 - Channel 5 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd5(&mut self) -> EVD5_W { + EVD5_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/evsys/intenset.rs b/pac/atsamc20g/src/evsys/intenset.rs new file mode 100644 index 000000000000..974030ec7350 --- /dev/null +++ b/pac/atsamc20g/src/evsys/intenset.rs @@ -0,0 +1,630 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVR0` reader - Channel 0 Overrun Interrupt Enable"] +pub struct OVR0_R(crate::FieldReader); +impl OVR0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR0` writer - Channel 0 Overrun Interrupt Enable"] +pub struct OVR0_W<'a> { + w: &'a mut W, +} +impl<'a> OVR0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `OVR1` reader - Channel 1 Overrun Interrupt Enable"] +pub struct OVR1_R(crate::FieldReader); +impl OVR1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR1` writer - Channel 1 Overrun Interrupt Enable"] +pub struct OVR1_W<'a> { + w: &'a mut W, +} +impl<'a> OVR1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `OVR2` reader - Channel 2 Overrun Interrupt Enable"] +pub struct OVR2_R(crate::FieldReader); +impl OVR2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR2` writer - Channel 2 Overrun Interrupt Enable"] +pub struct OVR2_W<'a> { + w: &'a mut W, +} +impl<'a> OVR2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `OVR3` reader - Channel 3 Overrun Interrupt Enable"] +pub struct OVR3_R(crate::FieldReader); +impl OVR3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR3` writer - Channel 3 Overrun Interrupt Enable"] +pub struct OVR3_W<'a> { + w: &'a mut W, +} +impl<'a> OVR3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `OVR4` reader - Channel 4 Overrun Interrupt Enable"] +pub struct OVR4_R(crate::FieldReader); +impl OVR4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR4` writer - Channel 4 Overrun Interrupt Enable"] +pub struct OVR4_W<'a> { + w: &'a mut W, +} +impl<'a> OVR4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `OVR5` reader - Channel 5 Overrun Interrupt Enable"] +pub struct OVR5_R(crate::FieldReader); +impl OVR5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR5` writer - Channel 5 Overrun Interrupt Enable"] +pub struct OVR5_W<'a> { + w: &'a mut W, +} +impl<'a> OVR5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `EVD0` reader - Channel 0 Event Detection Interrupt Enable"] +pub struct EVD0_R(crate::FieldReader); +impl EVD0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD0` writer - Channel 0 Event Detection Interrupt Enable"] +pub struct EVD0_W<'a> { + w: &'a mut W, +} +impl<'a> EVD0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `EVD1` reader - Channel 1 Event Detection Interrupt Enable"] +pub struct EVD1_R(crate::FieldReader); +impl EVD1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD1` writer - Channel 1 Event Detection Interrupt Enable"] +pub struct EVD1_W<'a> { + w: &'a mut W, +} +impl<'a> EVD1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `EVD2` reader - Channel 2 Event Detection Interrupt Enable"] +pub struct EVD2_R(crate::FieldReader); +impl EVD2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD2` writer - Channel 2 Event Detection Interrupt Enable"] +pub struct EVD2_W<'a> { + w: &'a mut W, +} +impl<'a> EVD2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `EVD3` reader - Channel 3 Event Detection Interrupt Enable"] +pub struct EVD3_R(crate::FieldReader); +impl EVD3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD3` writer - Channel 3 Event Detection Interrupt Enable"] +pub struct EVD3_W<'a> { + w: &'a mut W, +} +impl<'a> EVD3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `EVD4` reader - Channel 4 Event Detection Interrupt Enable"] +pub struct EVD4_R(crate::FieldReader); +impl EVD4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD4` writer - Channel 4 Event Detection Interrupt Enable"] +pub struct EVD4_W<'a> { + w: &'a mut W, +} +impl<'a> EVD4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `EVD5` reader - Channel 5 Event Detection Interrupt Enable"] +pub struct EVD5_R(crate::FieldReader); +impl EVD5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD5` writer - Channel 5 Event Detection Interrupt Enable"] +pub struct EVD5_W<'a> { + w: &'a mut W, +} +impl<'a> EVD5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +impl R { + #[doc = "Bit 0 - Channel 0 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr0(&self) -> OVR0_R { + OVR0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel 1 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr1(&self) -> OVR1_R { + OVR1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel 2 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr2(&self) -> OVR2_R { + OVR2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Channel 3 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr3(&self) -> OVR3_R { + OVR3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Channel 4 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr4(&self) -> OVR4_R { + OVR4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Channel 5 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr5(&self) -> OVR5_R { + OVR5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 16 - Channel 0 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd0(&self) -> EVD0_R { + EVD0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Channel 1 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd1(&self) -> EVD1_R { + EVD1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Channel 2 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd2(&self) -> EVD2_R { + EVD2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Channel 3 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd3(&self) -> EVD3_R { + EVD3_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Channel 4 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd4(&self) -> EVD4_R { + EVD4_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Channel 5 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd5(&self) -> EVD5_R { + EVD5_R::new(((self.bits >> 21) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel 0 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr0(&mut self) -> OVR0_W { + OVR0_W { w: self } + } + #[doc = "Bit 1 - Channel 1 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr1(&mut self) -> OVR1_W { + OVR1_W { w: self } + } + #[doc = "Bit 2 - Channel 2 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr2(&mut self) -> OVR2_W { + OVR2_W { w: self } + } + #[doc = "Bit 3 - Channel 3 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr3(&mut self) -> OVR3_W { + OVR3_W { w: self } + } + #[doc = "Bit 4 - Channel 4 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr4(&mut self) -> OVR4_W { + OVR4_W { w: self } + } + #[doc = "Bit 5 - Channel 5 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr5(&mut self) -> OVR5_W { + OVR5_W { w: self } + } + #[doc = "Bit 16 - Channel 0 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd0(&mut self) -> EVD0_W { + EVD0_W { w: self } + } + #[doc = "Bit 17 - Channel 1 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd1(&mut self) -> EVD1_W { + EVD1_W { w: self } + } + #[doc = "Bit 18 - Channel 2 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd2(&mut self) -> EVD2_W { + EVD2_W { w: self } + } + #[doc = "Bit 19 - Channel 3 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd3(&mut self) -> EVD3_W { + EVD3_W { w: self } + } + #[doc = "Bit 20 - Channel 4 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd4(&mut self) -> EVD4_W { + EVD4_W { w: self } + } + #[doc = "Bit 21 - Channel 5 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd5(&mut self) -> EVD5_W { + EVD5_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/evsys/intflag.rs b/pac/atsamc20g/src/evsys/intflag.rs new file mode 100644 index 000000000000..fa72ee78a84f --- /dev/null +++ b/pac/atsamc20g/src/evsys/intflag.rs @@ -0,0 +1,630 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVR0` reader - Channel 0 Overrun"] +pub struct OVR0_R(crate::FieldReader); +impl OVR0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR0` writer - Channel 0 Overrun"] +pub struct OVR0_W<'a> { + w: &'a mut W, +} +impl<'a> OVR0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `OVR1` reader - Channel 1 Overrun"] +pub struct OVR1_R(crate::FieldReader); +impl OVR1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR1` writer - Channel 1 Overrun"] +pub struct OVR1_W<'a> { + w: &'a mut W, +} +impl<'a> OVR1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `OVR2` reader - Channel 2 Overrun"] +pub struct OVR2_R(crate::FieldReader); +impl OVR2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR2` writer - Channel 2 Overrun"] +pub struct OVR2_W<'a> { + w: &'a mut W, +} +impl<'a> OVR2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `OVR3` reader - Channel 3 Overrun"] +pub struct OVR3_R(crate::FieldReader); +impl OVR3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR3` writer - Channel 3 Overrun"] +pub struct OVR3_W<'a> { + w: &'a mut W, +} +impl<'a> OVR3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `OVR4` reader - Channel 4 Overrun"] +pub struct OVR4_R(crate::FieldReader); +impl OVR4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR4` writer - Channel 4 Overrun"] +pub struct OVR4_W<'a> { + w: &'a mut W, +} +impl<'a> OVR4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `OVR5` reader - Channel 5 Overrun"] +pub struct OVR5_R(crate::FieldReader); +impl OVR5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR5` writer - Channel 5 Overrun"] +pub struct OVR5_W<'a> { + w: &'a mut W, +} +impl<'a> OVR5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `EVD0` reader - Channel 0 Event Detection"] +pub struct EVD0_R(crate::FieldReader); +impl EVD0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD0` writer - Channel 0 Event Detection"] +pub struct EVD0_W<'a> { + w: &'a mut W, +} +impl<'a> EVD0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `EVD1` reader - Channel 1 Event Detection"] +pub struct EVD1_R(crate::FieldReader); +impl EVD1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD1` writer - Channel 1 Event Detection"] +pub struct EVD1_W<'a> { + w: &'a mut W, +} +impl<'a> EVD1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `EVD2` reader - Channel 2 Event Detection"] +pub struct EVD2_R(crate::FieldReader); +impl EVD2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD2` writer - Channel 2 Event Detection"] +pub struct EVD2_W<'a> { + w: &'a mut W, +} +impl<'a> EVD2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `EVD3` reader - Channel 3 Event Detection"] +pub struct EVD3_R(crate::FieldReader); +impl EVD3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD3` writer - Channel 3 Event Detection"] +pub struct EVD3_W<'a> { + w: &'a mut W, +} +impl<'a> EVD3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `EVD4` reader - Channel 4 Event Detection"] +pub struct EVD4_R(crate::FieldReader); +impl EVD4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD4` writer - Channel 4 Event Detection"] +pub struct EVD4_W<'a> { + w: &'a mut W, +} +impl<'a> EVD4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `EVD5` reader - Channel 5 Event Detection"] +pub struct EVD5_R(crate::FieldReader); +impl EVD5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD5` writer - Channel 5 Event Detection"] +pub struct EVD5_W<'a> { + w: &'a mut W, +} +impl<'a> EVD5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +impl R { + #[doc = "Bit 0 - Channel 0 Overrun"] + #[inline(always)] + pub fn ovr0(&self) -> OVR0_R { + OVR0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel 1 Overrun"] + #[inline(always)] + pub fn ovr1(&self) -> OVR1_R { + OVR1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel 2 Overrun"] + #[inline(always)] + pub fn ovr2(&self) -> OVR2_R { + OVR2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Channel 3 Overrun"] + #[inline(always)] + pub fn ovr3(&self) -> OVR3_R { + OVR3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Channel 4 Overrun"] + #[inline(always)] + pub fn ovr4(&self) -> OVR4_R { + OVR4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Channel 5 Overrun"] + #[inline(always)] + pub fn ovr5(&self) -> OVR5_R { + OVR5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 16 - Channel 0 Event Detection"] + #[inline(always)] + pub fn evd0(&self) -> EVD0_R { + EVD0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Channel 1 Event Detection"] + #[inline(always)] + pub fn evd1(&self) -> EVD1_R { + EVD1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Channel 2 Event Detection"] + #[inline(always)] + pub fn evd2(&self) -> EVD2_R { + EVD2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Channel 3 Event Detection"] + #[inline(always)] + pub fn evd3(&self) -> EVD3_R { + EVD3_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Channel 4 Event Detection"] + #[inline(always)] + pub fn evd4(&self) -> EVD4_R { + EVD4_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Channel 5 Event Detection"] + #[inline(always)] + pub fn evd5(&self) -> EVD5_R { + EVD5_R::new(((self.bits >> 21) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel 0 Overrun"] + #[inline(always)] + pub fn ovr0(&mut self) -> OVR0_W { + OVR0_W { w: self } + } + #[doc = "Bit 1 - Channel 1 Overrun"] + #[inline(always)] + pub fn ovr1(&mut self) -> OVR1_W { + OVR1_W { w: self } + } + #[doc = "Bit 2 - Channel 2 Overrun"] + #[inline(always)] + pub fn ovr2(&mut self) -> OVR2_W { + OVR2_W { w: self } + } + #[doc = "Bit 3 - Channel 3 Overrun"] + #[inline(always)] + pub fn ovr3(&mut self) -> OVR3_W { + OVR3_W { w: self } + } + #[doc = "Bit 4 - Channel 4 Overrun"] + #[inline(always)] + pub fn ovr4(&mut self) -> OVR4_W { + OVR4_W { w: self } + } + #[doc = "Bit 5 - Channel 5 Overrun"] + #[inline(always)] + pub fn ovr5(&mut self) -> OVR5_W { + OVR5_W { w: self } + } + #[doc = "Bit 16 - Channel 0 Event Detection"] + #[inline(always)] + pub fn evd0(&mut self) -> EVD0_W { + EVD0_W { w: self } + } + #[doc = "Bit 17 - Channel 1 Event Detection"] + #[inline(always)] + pub fn evd1(&mut self) -> EVD1_W { + EVD1_W { w: self } + } + #[doc = "Bit 18 - Channel 2 Event Detection"] + #[inline(always)] + pub fn evd2(&mut self) -> EVD2_W { + EVD2_W { w: self } + } + #[doc = "Bit 19 - Channel 3 Event Detection"] + #[inline(always)] + pub fn evd3(&mut self) -> EVD3_W { + EVD3_W { w: self } + } + #[doc = "Bit 20 - Channel 4 Event Detection"] + #[inline(always)] + pub fn evd4(&mut self) -> EVD4_W { + EVD4_W { w: self } + } + #[doc = "Bit 21 - Channel 5 Event Detection"] + #[inline(always)] + pub fn evd5(&mut self) -> EVD5_W { + EVD5_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/evsys/swevt.rs b/pac/atsamc20g/src/evsys/swevt.rs new file mode 100644 index 000000000000..ba358dc12664 --- /dev/null +++ b/pac/atsamc20g/src/evsys/swevt.rs @@ -0,0 +1,207 @@ +#[doc = "Register `SWEVT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHANNEL0` writer - Channel 0 Software Selection"] +pub struct CHANNEL0_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `CHANNEL1` writer - Channel 1 Software Selection"] +pub struct CHANNEL1_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CHANNEL2` writer - Channel 2 Software Selection"] +pub struct CHANNEL2_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CHANNEL3` writer - Channel 3 Software Selection"] +pub struct CHANNEL3_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CHANNEL4` writer - Channel 4 Software Selection"] +pub struct CHANNEL4_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `CHANNEL5` writer - Channel 5 Software Selection"] +pub struct CHANNEL5_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +impl W { + #[doc = "Bit 0 - Channel 0 Software Selection"] + #[inline(always)] + pub fn channel0(&mut self) -> CHANNEL0_W { + CHANNEL0_W { w: self } + } + #[doc = "Bit 1 - Channel 1 Software Selection"] + #[inline(always)] + pub fn channel1(&mut self) -> CHANNEL1_W { + CHANNEL1_W { w: self } + } + #[doc = "Bit 2 - Channel 2 Software Selection"] + #[inline(always)] + pub fn channel2(&mut self) -> CHANNEL2_W { + CHANNEL2_W { w: self } + } + #[doc = "Bit 3 - Channel 3 Software Selection"] + #[inline(always)] + pub fn channel3(&mut self) -> CHANNEL3_W { + CHANNEL3_W { w: self } + } + #[doc = "Bit 4 - Channel 4 Software Selection"] + #[inline(always)] + pub fn channel4(&mut self) -> CHANNEL4_W { + CHANNEL4_W { w: self } + } + #[doc = "Bit 5 - Channel 5 Software Selection"] + #[inline(always)] + pub fn channel5(&mut self) -> CHANNEL5_W { + CHANNEL5_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Software Event\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [swevt](index.html) module"] +pub struct SWEVT_SPEC; +impl crate::RegisterSpec for SWEVT_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [swevt::W](W) writer structure"] +impl crate::Writable for SWEVT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SWEVT to value 0"] +impl crate::Resettable for SWEVT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/evsys/user.rs b/pac/atsamc20g/src/evsys/user.rs new file mode 100644 index 000000000000..efc20862bfe8 --- /dev/null +++ b/pac/atsamc20g/src/evsys/user.rs @@ -0,0 +1,104 @@ +#[doc = "Register `USER[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `USER[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHANNEL` reader - Channel Event Selection"] +pub struct CHANNEL_R(crate::FieldReader); +impl CHANNEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CHANNEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHANNEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHANNEL` writer - Channel Event Selection"] +pub struct CHANNEL_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Channel Event Selection"] + #[inline(always)] + pub fn channel(&self) -> CHANNEL_R { + CHANNEL_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Channel Event Selection"] + #[inline(always)] + pub fn channel(&mut self) -> CHANNEL_W { + CHANNEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "User Multiplexer n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [user](index.html) module"] +pub struct USER_SPEC; +impl crate::RegisterSpec for USER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [user::R](R) reader structure"] +impl crate::Readable for USER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [user::W](W) writer structure"] +impl crate::Writable for USER_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets USER[%s] +to value 0"] +impl crate::Resettable for USER_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/freqm.rs b/pac/atsamc20g/src/freqm.rs new file mode 100644 index 000000000000..f0fc6fda975e --- /dev/null +++ b/pac/atsamc20g/src/freqm.rs @@ -0,0 +1,59 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control A Register"] + pub ctrla: crate::Reg, + #[doc = "0x01 - Control B Register"] + pub ctrlb: crate::Reg, + #[doc = "0x02 - Config A register"] + pub cfga: crate::Reg, + _reserved3: [u8; 0x04], + #[doc = "0x08 - Interrupt Enable Clear Register"] + pub intenclr: crate::Reg, + #[doc = "0x09 - Interrupt Enable Set Register"] + pub intenset: crate::Reg, + #[doc = "0x0a - Interrupt Flag Register"] + pub intflag: crate::Reg, + #[doc = "0x0b - Status Register"] + pub status: crate::Reg, + #[doc = "0x0c - Synchronization Busy Register"] + pub syncbusy: crate::Reg, + #[doc = "0x10 - Count Value Register"] + pub value: crate::Reg, +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A Register"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "Control B Register"] +pub mod ctrlb; +#[doc = "CFGA register accessor: an alias for `Reg`"] +pub type CFGA = crate::Reg; +#[doc = "Config A register"] +pub mod cfga; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear Register"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set Register"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Register"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status Register"] +pub mod status; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Busy Register"] +pub mod syncbusy; +#[doc = "VALUE register accessor: an alias for `Reg`"] +pub type VALUE = crate::Reg; +#[doc = "Count Value Register"] +pub mod value; diff --git a/pac/atsamc20g/src/freqm/cfga.rs b/pac/atsamc20g/src/freqm/cfga.rs new file mode 100644 index 000000000000..573c62964185 --- /dev/null +++ b/pac/atsamc20g/src/freqm/cfga.rs @@ -0,0 +1,103 @@ +#[doc = "Register `CFGA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CFGA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `REFNUM` reader - Number of Reference Clock Cycles"] +pub struct REFNUM_R(crate::FieldReader); +impl REFNUM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REFNUM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REFNUM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REFNUM` writer - Number of Reference Clock Cycles"] +pub struct REFNUM_W<'a> { + w: &'a mut W, +} +impl<'a> REFNUM_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u16 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Number of Reference Clock Cycles"] + #[inline(always)] + pub fn refnum(&self) -> REFNUM_R { + REFNUM_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Number of Reference Clock Cycles"] + #[inline(always)] + pub fn refnum(&mut self) -> REFNUM_W { + REFNUM_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Config A register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cfga](index.html) module"] +pub struct CFGA_SPEC; +impl crate::RegisterSpec for CFGA_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [cfga::R](R) reader structure"] +impl crate::Readable for CFGA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cfga::W](W) writer structure"] +impl crate::Writable for CFGA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CFGA to value 0"] +impl crate::Resettable for CFGA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/freqm/ctrla.rs b/pac/atsamc20g/src/freqm/ctrla.rs new file mode 100644 index 000000000000..b2cefdd45770 --- /dev/null +++ b/pac/atsamc20g/src/freqm/ctrla.rs @@ -0,0 +1,160 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/freqm/ctrlb.rs b/pac/atsamc20g/src/freqm/ctrlb.rs new file mode 100644 index 000000000000..7d350e71fbf3 --- /dev/null +++ b/pac/atsamc20g/src/freqm/ctrlb.rs @@ -0,0 +1,72 @@ +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `START` writer - Start Measurement"] +pub struct START_W<'a> { + w: &'a mut W, +} +impl<'a> START_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0 - Start Measurement"] + #[inline(always)] + pub fn start(&mut self) -> START_W { + START_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u8; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/freqm/intenclr.rs b/pac/atsamc20g/src/freqm/intenclr.rs new file mode 100644 index 000000000000..a224aa5500f6 --- /dev/null +++ b/pac/atsamc20g/src/freqm/intenclr.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DONE` reader - Measurement Done Interrupt Enable"] +pub struct DONE_R(crate::FieldReader); +impl DONE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DONE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DONE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DONE` writer - Measurement Done Interrupt Enable"] +pub struct DONE_W<'a> { + w: &'a mut W, +} +impl<'a> DONE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Measurement Done Interrupt Enable"] + #[inline(always)] + pub fn done(&self) -> DONE_R { + DONE_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Measurement Done Interrupt Enable"] + #[inline(always)] + pub fn done(&mut self) -> DONE_W { + DONE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/freqm/intenset.rs b/pac/atsamc20g/src/freqm/intenset.rs new file mode 100644 index 000000000000..53b3d0bef7c0 --- /dev/null +++ b/pac/atsamc20g/src/freqm/intenset.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DONE` reader - Measurement Done Interrupt Enable"] +pub struct DONE_R(crate::FieldReader); +impl DONE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DONE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DONE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DONE` writer - Measurement Done Interrupt Enable"] +pub struct DONE_W<'a> { + w: &'a mut W, +} +impl<'a> DONE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Measurement Done Interrupt Enable"] + #[inline(always)] + pub fn done(&self) -> DONE_R { + DONE_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Measurement Done Interrupt Enable"] + #[inline(always)] + pub fn done(&mut self) -> DONE_W { + DONE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/freqm/intflag.rs b/pac/atsamc20g/src/freqm/intflag.rs new file mode 100644 index 000000000000..3b8fdab47703 --- /dev/null +++ b/pac/atsamc20g/src/freqm/intflag.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DONE` reader - Measurement Done"] +pub struct DONE_R(crate::FieldReader); +impl DONE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DONE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DONE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DONE` writer - Measurement Done"] +pub struct DONE_W<'a> { + w: &'a mut W, +} +impl<'a> DONE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Measurement Done"] + #[inline(always)] + pub fn done(&self) -> DONE_R { + DONE_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Measurement Done"] + #[inline(always)] + pub fn done(&mut self) -> DONE_W { + DONE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/freqm/status.rs b/pac/atsamc20g/src/freqm/status.rs new file mode 100644 index 000000000000..8a81662f51b0 --- /dev/null +++ b/pac/atsamc20g/src/freqm/status.rs @@ -0,0 +1,160 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BUSY` reader - FREQM Status"] +pub struct BUSY_R(crate::FieldReader); +impl BUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSY` writer - FREQM Status"] +pub struct BUSY_W<'a> { + w: &'a mut W, +} +impl<'a> BUSY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `OVF` reader - Sticky Count Value Overflow"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Sticky Count Value Overflow"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - FREQM Status"] + #[inline(always)] + pub fn busy(&self) -> BUSY_R { + BUSY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Sticky Count Value Overflow"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - FREQM Status"] + #[inline(always)] + pub fn busy(&mut self) -> BUSY_W { + BUSY_W { w: self } + } + #[doc = "Bit 1 - Sticky Count Value Overflow"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/freqm/syncbusy.rs b/pac/atsamc20g/src/freqm/syncbusy.rs new file mode 100644 index 000000000000..54396368e817 --- /dev/null +++ b/pac/atsamc20g/src/freqm/syncbusy.rs @@ -0,0 +1,73 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +#[doc = "Synchronization Busy Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/freqm/value.rs b/pac/atsamc20g/src/freqm/value.rs new file mode 100644 index 000000000000..5b0f5dfd9b67 --- /dev/null +++ b/pac/atsamc20g/src/freqm/value.rs @@ -0,0 +1,53 @@ +#[doc = "Register `VALUE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `VALUE` reader - Measurement Value"] +pub struct VALUE_R(crate::FieldReader); +impl VALUE_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + VALUE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VALUE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:23 - Measurement Value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +#[doc = "Count Value Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [value](index.html) module"] +pub struct VALUE_SPEC; +impl crate::RegisterSpec for VALUE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [value::R](R) reader structure"] +impl crate::Readable for VALUE_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets VALUE to value 0"] +impl crate::Resettable for VALUE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/gclk.rs b/pac/atsamc20g/src/gclk.rs new file mode 100644 index 000000000000..2a37bdedcab3 --- /dev/null +++ b/pac/atsamc20g/src/gclk.rs @@ -0,0 +1,31 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrla: crate::Reg, + _reserved1: [u8; 0x03], + #[doc = "0x04 - Synchronization Busy"] + pub syncbusy: crate::Reg, + _reserved2: [u8; 0x18], + #[doc = "0x20..0x44 - Generic Clock Generator Control"] + pub genctrl: [crate::Reg; 9], + _reserved3: [u8; 0x3c], + #[doc = "0x80..0x124 - Peripheral Clock Control"] + pub pchctrl: [crate::Reg; 41], +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control"] +pub mod ctrla; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Busy"] +pub mod syncbusy; +#[doc = "GENCTRL register accessor: an alias for `Reg`"] +pub type GENCTRL = crate::Reg; +#[doc = "Generic Clock Generator Control"] +pub mod genctrl; +#[doc = "PCHCTRL register accessor: an alias for `Reg`"] +pub type PCHCTRL = crate::Reg; +#[doc = "Peripheral Clock Control"] +pub mod pchctrl; diff --git a/pac/atsamc20g/src/gclk/ctrla.rs b/pac/atsamc20g/src/gclk/ctrla.rs new file mode 100644 index 000000000000..1c24704395ad --- /dev/null +++ b/pac/atsamc20g/src/gclk/ctrla.rs @@ -0,0 +1,113 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/gclk/genctrl.rs b/pac/atsamc20g/src/gclk/genctrl.rs new file mode 100644 index 000000000000..052b2915ca7f --- /dev/null +++ b/pac/atsamc20g/src/gclk/genctrl.rs @@ -0,0 +1,597 @@ +#[doc = "Register `GENCTRL[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GENCTRL[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Source Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SRC_A { + #[doc = "0: XOSC oscillator output"] + XOSC = 0, + #[doc = "1: Generator input pad"] + GCLKIN = 1, + #[doc = "2: Generic clock generator 1 output"] + GCLKGEN1 = 2, + #[doc = "3: OSCULP32K oscillator output"] + OSCULP32K = 3, + #[doc = "4: OSC32K oscillator output"] + OSC32K = 4, + #[doc = "5: XOSC32K oscillator output"] + XOSC32K = 5, + #[doc = "6: OSC48M oscillator output"] + OSC48M = 6, + #[doc = "7: DPLL96M output"] + DPLL96M = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SRC_A) -> Self { + variant as _ + } +} +#[doc = "Field `SRC` reader - Source Select"] +pub struct SRC_R(crate::FieldReader); +impl SRC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SRC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SRC_A { + match self.bits { + 0 => SRC_A::XOSC, + 1 => SRC_A::GCLKIN, + 2 => SRC_A::GCLKGEN1, + 3 => SRC_A::OSCULP32K, + 4 => SRC_A::OSC32K, + 5 => SRC_A::XOSC32K, + 6 => SRC_A::OSC48M, + 7 => SRC_A::DPLL96M, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `XOSC`"] + #[inline(always)] + pub fn is_xosc(&self) -> bool { + **self == SRC_A::XOSC + } + #[doc = "Checks if the value of the field is `GCLKIN`"] + #[inline(always)] + pub fn is_gclkin(&self) -> bool { + **self == SRC_A::GCLKIN + } + #[doc = "Checks if the value of the field is `GCLKGEN1`"] + #[inline(always)] + pub fn is_gclkgen1(&self) -> bool { + **self == SRC_A::GCLKGEN1 + } + #[doc = "Checks if the value of the field is `OSCULP32K`"] + #[inline(always)] + pub fn is_osculp32k(&self) -> bool { + **self == SRC_A::OSCULP32K + } + #[doc = "Checks if the value of the field is `OSC32K`"] + #[inline(always)] + pub fn is_osc32k(&self) -> bool { + **self == SRC_A::OSC32K + } + #[doc = "Checks if the value of the field is `XOSC32K`"] + #[inline(always)] + pub fn is_xosc32k(&self) -> bool { + **self == SRC_A::XOSC32K + } + #[doc = "Checks if the value of the field is `OSC48M`"] + #[inline(always)] + pub fn is_osc48m(&self) -> bool { + **self == SRC_A::OSC48M + } + #[doc = "Checks if the value of the field is `DPLL96M`"] + #[inline(always)] + pub fn is_dpll96m(&self) -> bool { + **self == SRC_A::DPLL96M + } +} +impl core::ops::Deref for SRC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SRC` writer - Source Select"] +pub struct SRC_W<'a> { + w: &'a mut W, +} +impl<'a> SRC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SRC_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "XOSC oscillator output"] + #[inline(always)] + pub fn xosc(self) -> &'a mut W { + self.variant(SRC_A::XOSC) + } + #[doc = "Generator input pad"] + #[inline(always)] + pub fn gclkin(self) -> &'a mut W { + self.variant(SRC_A::GCLKIN) + } + #[doc = "Generic clock generator 1 output"] + #[inline(always)] + pub fn gclkgen1(self) -> &'a mut W { + self.variant(SRC_A::GCLKGEN1) + } + #[doc = "OSCULP32K oscillator output"] + #[inline(always)] + pub fn osculp32k(self) -> &'a mut W { + self.variant(SRC_A::OSCULP32K) + } + #[doc = "OSC32K oscillator output"] + #[inline(always)] + pub fn osc32k(self) -> &'a mut W { + self.variant(SRC_A::OSC32K) + } + #[doc = "XOSC32K oscillator output"] + #[inline(always)] + pub fn xosc32k(self) -> &'a mut W { + self.variant(SRC_A::XOSC32K) + } + #[doc = "OSC48M oscillator output"] + #[inline(always)] + pub fn osc48m(self) -> &'a mut W { + self.variant(SRC_A::OSC48M) + } + #[doc = "DPLL96M output"] + #[inline(always)] + pub fn dpll96m(self) -> &'a mut W { + self.variant(SRC_A::DPLL96M) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Field `GENEN` reader - Generic Clock Generator Enable"] +pub struct GENEN_R(crate::FieldReader); +impl GENEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENEN` writer - Generic Clock Generator Enable"] +pub struct GENEN_W<'a> { + w: &'a mut W, +} +impl<'a> GENEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `IDC` reader - Improve Duty Cycle"] +pub struct IDC_R(crate::FieldReader); +impl IDC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IDC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IDC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IDC` writer - Improve Duty Cycle"] +pub struct IDC_W<'a> { + w: &'a mut W, +} +impl<'a> IDC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `OOV` reader - Output Off Value"] +pub struct OOV_R(crate::FieldReader); +impl OOV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OOV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OOV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OOV` writer - Output Off Value"] +pub struct OOV_W<'a> { + w: &'a mut W, +} +impl<'a> OOV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `OE` reader - Output Enable"] +pub struct OE_R(crate::FieldReader); +impl OE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OE` writer - Output Enable"] +pub struct OE_W<'a> { + w: &'a mut W, +} +impl<'a> OE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Divide Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum DIVSEL_A { + #[doc = "0: Divide input directly by divider factor"] + DIV1 = 0, + #[doc = "1: Divide input by 2^(divider factor+ 1)"] + DIV2 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DIVSEL_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DIVSEL` reader - Divide Selection"] +pub struct DIVSEL_R(crate::FieldReader); +impl DIVSEL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIVSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DIVSEL_A { + match self.bits { + false => DIVSEL_A::DIV1, + true => DIVSEL_A::DIV2, + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == DIVSEL_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == DIVSEL_A::DIV2 + } +} +impl core::ops::Deref for DIVSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIVSEL` writer - Divide Selection"] +pub struct DIVSEL_W<'a> { + w: &'a mut W, +} +impl<'a> DIVSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DIVSEL_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Divide input directly by divider factor"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(DIVSEL_A::DIV1) + } + #[doc = "Divide input by 2^(divider factor+ 1)"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(DIVSEL_A::DIV2) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `DIV` reader - Division Factor"] +pub struct DIV_R(crate::FieldReader); +impl DIV_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + DIV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIV` writer - Division Factor"] +pub struct DIV_W<'a> { + w: &'a mut W, +} +impl<'a> DIV_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xffff << 16)) | ((value as u32 & 0xffff) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Source Select"] + #[inline(always)] + pub fn src(&self) -> SRC_R { + SRC_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 8 - Generic Clock Generator Enable"] + #[inline(always)] + pub fn genen(&self) -> GENEN_R { + GENEN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Improve Duty Cycle"] + #[inline(always)] + pub fn idc(&self) -> IDC_R { + IDC_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Output Off Value"] + #[inline(always)] + pub fn oov(&self) -> OOV_R { + OOV_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Output Enable"] + #[inline(always)] + pub fn oe(&self) -> OE_R { + OE_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Divide Selection"] + #[inline(always)] + pub fn divsel(&self) -> DIVSEL_R { + DIVSEL_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bits 16:31 - Division Factor"] + #[inline(always)] + pub fn div(&self) -> DIV_R { + DIV_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:2 - Source Select"] + #[inline(always)] + pub fn src(&mut self) -> SRC_W { + SRC_W { w: self } + } + #[doc = "Bit 8 - Generic Clock Generator Enable"] + #[inline(always)] + pub fn genen(&mut self) -> GENEN_W { + GENEN_W { w: self } + } + #[doc = "Bit 9 - Improve Duty Cycle"] + #[inline(always)] + pub fn idc(&mut self) -> IDC_W { + IDC_W { w: self } + } + #[doc = "Bit 10 - Output Off Value"] + #[inline(always)] + pub fn oov(&mut self) -> OOV_W { + OOV_W { w: self } + } + #[doc = "Bit 11 - Output Enable"] + #[inline(always)] + pub fn oe(&mut self) -> OE_W { + OE_W { w: self } + } + #[doc = "Bit 12 - Divide Selection"] + #[inline(always)] + pub fn divsel(&mut self) -> DIVSEL_W { + DIVSEL_W { w: self } + } + #[doc = "Bit 13 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bits 16:31 - Division Factor"] + #[inline(always)] + pub fn div(&mut self) -> DIV_W { + DIV_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Generic Clock Generator Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [genctrl](index.html) module"] +pub struct GENCTRL_SPEC; +impl crate::RegisterSpec for GENCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [genctrl::R](R) reader structure"] +impl crate::Readable for GENCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [genctrl::W](W) writer structure"] +impl crate::Writable for GENCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets GENCTRL[%s] +to value 0"] +impl crate::Resettable for GENCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/gclk/pchctrl.rs b/pac/atsamc20g/src/gclk/pchctrl.rs new file mode 100644 index 000000000000..8001ffeaa1ee --- /dev/null +++ b/pac/atsamc20g/src/gclk/pchctrl.rs @@ -0,0 +1,338 @@ +#[doc = "Register `PCHCTRL[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PCHCTRL[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Generic Clock Generator\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum GEN_A { + #[doc = "0: Generic clock generator 0"] + GCLK0 = 0, + #[doc = "1: Generic clock generator 1"] + GCLK1 = 1, + #[doc = "2: Generic clock generator 2"] + GCLK2 = 2, + #[doc = "3: Generic clock generator 3"] + GCLK3 = 3, + #[doc = "4: Generic clock generator 4"] + GCLK4 = 4, + #[doc = "5: Generic clock generator 5"] + GCLK5 = 5, + #[doc = "6: Generic clock generator 6"] + GCLK6 = 6, + #[doc = "7: Generic clock generator 7"] + GCLK7 = 7, + #[doc = "8: Generic clock generator 8"] + GCLK8 = 8, +} +impl From for u8 { + #[inline(always)] + fn from(variant: GEN_A) -> Self { + variant as _ + } +} +#[doc = "Field `GEN` reader - Generic Clock Generator"] +pub struct GEN_R(crate::FieldReader); +impl GEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + GEN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(GEN_A::GCLK0), + 1 => Some(GEN_A::GCLK1), + 2 => Some(GEN_A::GCLK2), + 3 => Some(GEN_A::GCLK3), + 4 => Some(GEN_A::GCLK4), + 5 => Some(GEN_A::GCLK5), + 6 => Some(GEN_A::GCLK6), + 7 => Some(GEN_A::GCLK7), + 8 => Some(GEN_A::GCLK8), + _ => None, + } + } + #[doc = "Checks if the value of the field is `GCLK0`"] + #[inline(always)] + pub fn is_gclk0(&self) -> bool { + **self == GEN_A::GCLK0 + } + #[doc = "Checks if the value of the field is `GCLK1`"] + #[inline(always)] + pub fn is_gclk1(&self) -> bool { + **self == GEN_A::GCLK1 + } + #[doc = "Checks if the value of the field is `GCLK2`"] + #[inline(always)] + pub fn is_gclk2(&self) -> bool { + **self == GEN_A::GCLK2 + } + #[doc = "Checks if the value of the field is `GCLK3`"] + #[inline(always)] + pub fn is_gclk3(&self) -> bool { + **self == GEN_A::GCLK3 + } + #[doc = "Checks if the value of the field is `GCLK4`"] + #[inline(always)] + pub fn is_gclk4(&self) -> bool { + **self == GEN_A::GCLK4 + } + #[doc = "Checks if the value of the field is `GCLK5`"] + #[inline(always)] + pub fn is_gclk5(&self) -> bool { + **self == GEN_A::GCLK5 + } + #[doc = "Checks if the value of the field is `GCLK6`"] + #[inline(always)] + pub fn is_gclk6(&self) -> bool { + **self == GEN_A::GCLK6 + } + #[doc = "Checks if the value of the field is `GCLK7`"] + #[inline(always)] + pub fn is_gclk7(&self) -> bool { + **self == GEN_A::GCLK7 + } + #[doc = "Checks if the value of the field is `GCLK8`"] + #[inline(always)] + pub fn is_gclk8(&self) -> bool { + **self == GEN_A::GCLK8 + } +} +impl core::ops::Deref for GEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GEN` writer - Generic Clock Generator"] +pub struct GEN_W<'a> { + w: &'a mut W, +} +impl<'a> GEN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: GEN_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Generic clock generator 0"] + #[inline(always)] + pub fn gclk0(self) -> &'a mut W { + self.variant(GEN_A::GCLK0) + } + #[doc = "Generic clock generator 1"] + #[inline(always)] + pub fn gclk1(self) -> &'a mut W { + self.variant(GEN_A::GCLK1) + } + #[doc = "Generic clock generator 2"] + #[inline(always)] + pub fn gclk2(self) -> &'a mut W { + self.variant(GEN_A::GCLK2) + } + #[doc = "Generic clock generator 3"] + #[inline(always)] + pub fn gclk3(self) -> &'a mut W { + self.variant(GEN_A::GCLK3) + } + #[doc = "Generic clock generator 4"] + #[inline(always)] + pub fn gclk4(self) -> &'a mut W { + self.variant(GEN_A::GCLK4) + } + #[doc = "Generic clock generator 5"] + #[inline(always)] + pub fn gclk5(self) -> &'a mut W { + self.variant(GEN_A::GCLK5) + } + #[doc = "Generic clock generator 6"] + #[inline(always)] + pub fn gclk6(self) -> &'a mut W { + self.variant(GEN_A::GCLK6) + } + #[doc = "Generic clock generator 7"] + #[inline(always)] + pub fn gclk7(self) -> &'a mut W { + self.variant(GEN_A::GCLK7) + } + #[doc = "Generic clock generator 8"] + #[inline(always)] + pub fn gclk8(self) -> &'a mut W { + self.variant(GEN_A::GCLK8) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Field `CHEN` reader - Channel Enable"] +pub struct CHEN_R(crate::FieldReader); +impl CHEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHEN` writer - Channel Enable"] +pub struct CHEN_W<'a> { + w: &'a mut W, +} +impl<'a> CHEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `WRTLOCK` reader - Write Lock"] +pub struct WRTLOCK_R(crate::FieldReader); +impl WRTLOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WRTLOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WRTLOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WRTLOCK` writer - Write Lock"] +pub struct WRTLOCK_W<'a> { + w: &'a mut W, +} +impl<'a> WRTLOCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Generic Clock Generator"] + #[inline(always)] + pub fn gen(&self) -> GEN_R { + GEN_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 6 - Channel Enable"] + #[inline(always)] + pub fn chen(&self) -> CHEN_R { + CHEN_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&self) -> WRTLOCK_R { + WRTLOCK_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Generic Clock Generator"] + #[inline(always)] + pub fn gen(&mut self) -> GEN_W { + GEN_W { w: self } + } + #[doc = "Bit 6 - Channel Enable"] + #[inline(always)] + pub fn chen(&mut self) -> CHEN_W { + CHEN_W { w: self } + } + #[doc = "Bit 7 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&mut self) -> WRTLOCK_W { + WRTLOCK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Peripheral Clock Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pchctrl](index.html) module"] +pub struct PCHCTRL_SPEC; +impl crate::RegisterSpec for PCHCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pchctrl::R](R) reader structure"] +impl crate::Readable for PCHCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [pchctrl::W](W) writer structure"] +impl crate::Writable for PCHCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PCHCTRL[%s] +to value 0"] +impl crate::Resettable for PCHCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/gclk/syncbusy.rs b/pac/atsamc20g/src/gclk/syncbusy.rs new file mode 100644 index 000000000000..f21640440354 --- /dev/null +++ b/pac/atsamc20g/src/gclk/syncbusy.rs @@ -0,0 +1,233 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchroniation Busy bit"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENCTRL0` reader - Generic Clock Generator Control 0 Synchronization Busy bits"] +pub struct GENCTRL0_R(crate::FieldReader); +impl GENCTRL0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENCTRL0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENCTRL0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENCTRL1` reader - Generic Clock Generator Control 1 Synchronization Busy bits"] +pub struct GENCTRL1_R(crate::FieldReader); +impl GENCTRL1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENCTRL1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENCTRL1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENCTRL2` reader - Generic Clock Generator Control 2 Synchronization Busy bits"] +pub struct GENCTRL2_R(crate::FieldReader); +impl GENCTRL2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENCTRL2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENCTRL2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENCTRL3` reader - Generic Clock Generator Control 3 Synchronization Busy bits"] +pub struct GENCTRL3_R(crate::FieldReader); +impl GENCTRL3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENCTRL3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENCTRL3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENCTRL4` reader - Generic Clock Generator Control 4 Synchronization Busy bits"] +pub struct GENCTRL4_R(crate::FieldReader); +impl GENCTRL4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENCTRL4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENCTRL4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENCTRL5` reader - Generic Clock Generator Control 5 Synchronization Busy bits"] +pub struct GENCTRL5_R(crate::FieldReader); +impl GENCTRL5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENCTRL5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENCTRL5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENCTRL6` reader - Generic Clock Generator Control 6 Synchronization Busy bits"] +pub struct GENCTRL6_R(crate::FieldReader); +impl GENCTRL6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENCTRL6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENCTRL6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENCTRL7` reader - Generic Clock Generator Control 7 Synchronization Busy bits"] +pub struct GENCTRL7_R(crate::FieldReader); +impl GENCTRL7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENCTRL7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENCTRL7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENCTRL8` reader - Generic Clock Generator Control 8 Synchronization Busy bits"] +pub struct GENCTRL8_R(crate::FieldReader); +impl GENCTRL8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENCTRL8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENCTRL8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchroniation Busy bit"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 2 - Generic Clock Generator Control 0 Synchronization Busy bits"] + #[inline(always)] + pub fn genctrl0(&self) -> GENCTRL0_R { + GENCTRL0_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Generic Clock Generator Control 1 Synchronization Busy bits"] + #[inline(always)] + pub fn genctrl1(&self) -> GENCTRL1_R { + GENCTRL1_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Generic Clock Generator Control 2 Synchronization Busy bits"] + #[inline(always)] + pub fn genctrl2(&self) -> GENCTRL2_R { + GENCTRL2_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Generic Clock Generator Control 3 Synchronization Busy bits"] + #[inline(always)] + pub fn genctrl3(&self) -> GENCTRL3_R { + GENCTRL3_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Generic Clock Generator Control 4 Synchronization Busy bits"] + #[inline(always)] + pub fn genctrl4(&self) -> GENCTRL4_R { + GENCTRL4_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Generic Clock Generator Control 5 Synchronization Busy bits"] + #[inline(always)] + pub fn genctrl5(&self) -> GENCTRL5_R { + GENCTRL5_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Generic Clock Generator Control 6 Synchronization Busy bits"] + #[inline(always)] + pub fn genctrl6(&self) -> GENCTRL6_R { + GENCTRL6_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Generic Clock Generator Control 7 Synchronization Busy bits"] + #[inline(always)] + pub fn genctrl7(&self) -> GENCTRL7_R { + GENCTRL7_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Generic Clock Generator Control 8 Synchronization Busy bits"] + #[inline(always)] + pub fn genctrl8(&self) -> GENCTRL8_R { + GENCTRL8_R::new(((self.bits >> 10) & 0x01) != 0) + } +} +#[doc = "Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/generic.rs b/pac/atsamc20g/src/generic.rs new file mode 100644 index 000000000000..76159643acfa --- /dev/null +++ b/pac/atsamc20g/src/generic.rs @@ -0,0 +1,260 @@ +use core::marker; +#[doc = " Raw register type"] +pub trait RegisterSpec { + #[doc = " Raw register type (`u8`, `u16`, `u32`, ...)."] + type Ux: Copy; +} +#[doc = " Trait implemented by readable registers to enable the `read` method."] +#[doc = ""] +#[doc = " Registers marked with `Writable` can be also `modify`'ed."] +pub trait Readable: RegisterSpec { + #[doc = " Result from a call to `read` and argument to `modify`."] + type Reader: From> + core::ops::Deref>; +} +#[doc = " Trait implemented by writeable registers."] +#[doc = ""] +#[doc = " This enables the `write`, `write_with_zero` and `reset` methods."] +#[doc = ""] +#[doc = " Registers marked with `Readable` can be also `modify`'ed."] +pub trait Writable: RegisterSpec { + #[doc = " Writer type argument to `write`, et al."] + type Writer: From> + core::ops::DerefMut>; +} +#[doc = " Reset value of the register."] +#[doc = ""] +#[doc = " This value is the initial value for the `write` method. It can also be directly written to the"] +#[doc = " register by using the `reset` method."] +pub trait Resettable: RegisterSpec { + #[doc = " Reset value of the register."] + fn reset_value() -> Self::Ux; +} +#[doc = " This structure provides volatile access to registers."] +#[repr(transparent)] +pub struct Reg { + register: vcell::VolatileCell, + _marker: marker::PhantomData, +} +unsafe impl Send for Reg where REG::Ux: Send {} +impl Reg { + #[doc = " Returns the underlying memory address of register."] + #[doc = ""] + #[doc = " ```ignore"] + #[doc = " let reg_ptr = periph.reg.as_ptr();"] + #[doc = " ```"] + #[inline(always)] + pub fn as_ptr(&self) -> *mut REG::Ux { + self.register.as_ptr() + } +} +impl Reg { + #[doc = " Reads the contents of a `Readable` register."] + #[doc = ""] + #[doc = " You can read the raw contents of a register by using `bits`:"] + #[doc = " ```ignore"] + #[doc = " let bits = periph.reg.read().bits();"] + #[doc = " ```"] + #[doc = " or get the content of a particular field of a register:"] + #[doc = " ```ignore"] + #[doc = " let reader = periph.reg.read();"] + #[doc = " let bits = reader.field1().bits();"] + #[doc = " let flag = reader.field2().bit_is_set();"] + #[doc = " ```"] + #[inline(always)] + pub fn read(&self) -> REG::Reader { + REG::Reader::from(R { + bits: self.register.get(), + _reg: marker::PhantomData, + }) + } +} +impl Reg { + #[doc = " Writes the reset value to `Writable` register."] + #[doc = ""] + #[doc = " Resets the register to its initial state."] + #[inline(always)] + pub fn reset(&self) { + self.register.set(REG::reset_value()) + } + #[doc = " Writes bits to a `Writable` register."] + #[doc = ""] + #[doc = " You can write raw bits into a register:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.write(|w| unsafe { w.bits(rawbits) });"] + #[doc = " ```"] + #[doc = " or write only the fields you need:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.write(|w| w"] + #[doc = " .field1().bits(newfield1bits)"] + #[doc = " .field2().set_bit()"] + #[doc = " .field3().variant(VARIANT)"] + #[doc = " );"] + #[doc = " ```"] + #[doc = " In the latter case, other fields will be set to their reset value."] + #[inline(always)] + pub fn write(&self, f: F) + where + F: FnOnce(&mut REG::Writer) -> &mut W, + { + self.register.set( + f(&mut REG::Writer::from(W { + bits: REG::reset_value(), + _reg: marker::PhantomData, + })) + .bits, + ); + } +} +impl Reg +where + REG::Ux: Default, +{ + #[doc = " Writes 0 to a `Writable` register."] + #[doc = ""] + #[doc = " Similar to `write`, but unused bits will contain 0."] + #[inline(always)] + pub unsafe fn write_with_zero(&self, f: F) + where + F: FnOnce(&mut REG::Writer) -> &mut W, + { + self.register.set( + (*f(&mut REG::Writer::from(W { + bits: REG::Ux::default(), + _reg: marker::PhantomData, + }))) + .bits, + ); + } +} +impl Reg { + #[doc = " Modifies the contents of the register by reading and then writing it."] + #[doc = ""] + #[doc = " E.g. to do a read-modify-write sequence to change parts of a register:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.modify(|r, w| unsafe { w.bits("] + #[doc = " r.bits() | 3"] + #[doc = " ) });"] + #[doc = " ```"] + #[doc = " or"] + #[doc = " ```ignore"] + #[doc = " periph.reg.modify(|_, w| w"] + #[doc = " .field1().bits(newfield1bits)"] + #[doc = " .field2().set_bit()"] + #[doc = " .field3().variant(VARIANT)"] + #[doc = " );"] + #[doc = " ```"] + #[doc = " Other fields will have the value they had before the call to `modify`."] + #[inline(always)] + pub fn modify(&self, f: F) + where + for<'w> F: FnOnce(®::Reader, &'w mut REG::Writer) -> &'w mut W, + { + let bits = self.register.get(); + self.register.set( + f( + ®::Reader::from(R { + bits, + _reg: marker::PhantomData, + }), + &mut REG::Writer::from(W { + bits, + _reg: marker::PhantomData, + }), + ) + .bits, + ); + } +} +#[doc = " Register reader."] +#[doc = ""] +#[doc = " Result of the `read` methods of registers. Also used as a closure argument in the `modify`"] +#[doc = " method."] +pub struct R { + pub(crate) bits: REG::Ux, + _reg: marker::PhantomData, +} +impl R { + #[doc = " Reads raw bits from register."] + #[inline(always)] + pub fn bits(&self) -> REG::Ux { + self.bits + } +} +impl PartialEq for R +where + REG::Ux: PartialEq, + FI: Copy + Into, +{ + #[inline(always)] + fn eq(&self, other: &FI) -> bool { + self.bits.eq(&(*other).into()) + } +} +#[doc = " Register writer."] +#[doc = ""] +#[doc = " Used as an argument to the closures in the `write` and `modify` methods of the register."] +pub struct W { + #[doc = "Writable bits"] + pub(crate) bits: REG::Ux, + _reg: marker::PhantomData, +} +impl W { + #[doc = " Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = " Field reader."] +#[doc = ""] +#[doc = " Result of the `read` methods of fields."] +pub struct FieldReader { + pub(crate) bits: U, + _reg: marker::PhantomData, +} +impl FieldReader +where + U: Copy, +{ + #[doc = " Creates a new instance of the reader."] + #[allow(unused)] + #[inline(always)] + pub(crate) fn new(bits: U) -> Self { + Self { + bits, + _reg: marker::PhantomData, + } + } + #[doc = " Reads raw bits from field."] + #[inline(always)] + pub fn bits(&self) -> U { + self.bits + } +} +impl PartialEq for FieldReader +where + U: PartialEq, + FI: Copy + Into, +{ + #[inline(always)] + fn eq(&self, other: &FI) -> bool { + self.bits.eq(&(*other).into()) + } +} +impl FieldReader { + #[doc = " Value of the field as raw bits."] + #[inline(always)] + pub fn bit(&self) -> bool { + self.bits + } + #[doc = " Returns `true` if the bit is clear (0)."] + #[inline(always)] + pub fn bit_is_clear(&self) -> bool { + !self.bit() + } + #[doc = " Returns `true` if the bit is set (1)."] + #[inline(always)] + pub fn bit_is_set(&self) -> bool { + self.bit() + } +} diff --git a/pac/atsamc20g/src/hmatrixhs.rs b/pac/atsamc20g/src/hmatrixhs.rs new file mode 100644 index 000000000000..c8129ac89b6f --- /dev/null +++ b/pac/atsamc20g/src/hmatrixhs.rs @@ -0,0 +1,43 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00..0x40 - Master Configuration"] + pub mcfg: [crate::Reg; 16], + #[doc = "0x40..0x80 - Slave Configuration"] + pub scfg: [crate::Reg; 16], + #[doc = "0x80..0xa0 - PRS\\[%s\\]"] + pub prs: [PRS; 4], + _reserved3: [u8; 0x60], + #[doc = "0x100 - Master Remap Control"] + pub mrcr: crate::Reg, + _reserved4: [u8; 0x0c], + #[doc = "0x110..0x150 - Special Function"] + pub sfr: [crate::Reg; 16], +} +#[doc = r"Register block"] +#[repr(C)] +pub struct PRS { + #[doc = "0x00 - Priority A for Slave"] + pub pras: crate::Reg, + #[doc = "0x04 - Priority B for Slave"] + pub prbs: crate::Reg, +} +#[doc = r"Register block"] +#[doc = "PRS\\[%s\\]"] +pub mod prs; +#[doc = "MCFG register accessor: an alias for `Reg`"] +pub type MCFG = crate::Reg; +#[doc = "Master Configuration"] +pub mod mcfg; +#[doc = "SCFG register accessor: an alias for `Reg`"] +pub type SCFG = crate::Reg; +#[doc = "Slave Configuration"] +pub mod scfg; +#[doc = "MRCR register accessor: an alias for `Reg`"] +pub type MRCR = crate::Reg; +#[doc = "Master Remap Control"] +pub mod mrcr; +#[doc = "SFR register accessor: an alias for `Reg`"] +pub type SFR = crate::Reg; +#[doc = "Special Function"] +pub mod sfr; diff --git a/pac/atsamc20g/src/hmatrixhs/mcfg.rs b/pac/atsamc20g/src/hmatrixhs/mcfg.rs new file mode 100644 index 000000000000..454a39fabe13 --- /dev/null +++ b/pac/atsamc20g/src/hmatrixhs/mcfg.rs @@ -0,0 +1,192 @@ +#[doc = "Register `MCFG[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MCFG[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Undefined Length Burst Type\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum ULBT_A { + #[doc = "0: Infinite Length"] + INFINITE = 0, + #[doc = "1: Single Access"] + SINGLE = 1, + #[doc = "2: Four Beat Burst"] + FOUR_BEAT = 2, + #[doc = "3: Eight Beat Burst"] + EIGHT_BEAT = 3, + #[doc = "4: Sixteen Beat Burst"] + SIXTEEN_BEAT = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: ULBT_A) -> Self { + variant as _ + } +} +#[doc = "Field `ULBT` reader - Undefined Length Burst Type"] +pub struct ULBT_R(crate::FieldReader); +impl ULBT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ULBT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(ULBT_A::INFINITE), + 1 => Some(ULBT_A::SINGLE), + 2 => Some(ULBT_A::FOUR_BEAT), + 3 => Some(ULBT_A::EIGHT_BEAT), + 4 => Some(ULBT_A::SIXTEEN_BEAT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `INFINITE`"] + #[inline(always)] + pub fn is_infinite(&self) -> bool { + **self == ULBT_A::INFINITE + } + #[doc = "Checks if the value of the field is `SINGLE`"] + #[inline(always)] + pub fn is_single(&self) -> bool { + **self == ULBT_A::SINGLE + } + #[doc = "Checks if the value of the field is `FOUR_BEAT`"] + #[inline(always)] + pub fn is_four_beat(&self) -> bool { + **self == ULBT_A::FOUR_BEAT + } + #[doc = "Checks if the value of the field is `EIGHT_BEAT`"] + #[inline(always)] + pub fn is_eight_beat(&self) -> bool { + **self == ULBT_A::EIGHT_BEAT + } + #[doc = "Checks if the value of the field is `SIXTEEN_BEAT`"] + #[inline(always)] + pub fn is_sixteen_beat(&self) -> bool { + **self == ULBT_A::SIXTEEN_BEAT + } +} +impl core::ops::Deref for ULBT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ULBT` writer - Undefined Length Burst Type"] +pub struct ULBT_W<'a> { + w: &'a mut W, +} +impl<'a> ULBT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: ULBT_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Infinite Length"] + #[inline(always)] + pub fn infinite(self) -> &'a mut W { + self.variant(ULBT_A::INFINITE) + } + #[doc = "Single Access"] + #[inline(always)] + pub fn single(self) -> &'a mut W { + self.variant(ULBT_A::SINGLE) + } + #[doc = "Four Beat Burst"] + #[inline(always)] + pub fn four_beat(self) -> &'a mut W { + self.variant(ULBT_A::FOUR_BEAT) + } + #[doc = "Eight Beat Burst"] + #[inline(always)] + pub fn eight_beat(self) -> &'a mut W { + self.variant(ULBT_A::EIGHT_BEAT) + } + #[doc = "Sixteen Beat Burst"] + #[inline(always)] + pub fn sixteen_beat(self) -> &'a mut W { + self.variant(ULBT_A::SIXTEEN_BEAT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Undefined Length Burst Type"] + #[inline(always)] + pub fn ulbt(&self) -> ULBT_R { + ULBT_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Undefined Length Burst Type"] + #[inline(always)] + pub fn ulbt(&mut self) -> ULBT_W { + ULBT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Master Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mcfg](index.html) module"] +pub struct MCFG_SPEC; +impl crate::RegisterSpec for MCFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [mcfg::R](R) reader structure"] +impl crate::Readable for MCFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [mcfg::W](W) writer structure"] +impl crate::Writable for MCFG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets MCFG[%s] +to value 0x02"] +impl crate::Resettable for MCFG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x02 + } +} diff --git a/pac/atsamc20g/src/hmatrixhs/mrcr.rs b/pac/atsamc20g/src/hmatrixhs/mrcr.rs new file mode 100644 index 000000000000..0cf2a1fb01be --- /dev/null +++ b/pac/atsamc20g/src/hmatrixhs/mrcr.rs @@ -0,0 +1,1570 @@ +#[doc = "Register `MRCR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MRCR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Remap Command Bit for Master 0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB0_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB0_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB0` reader - Remap Command Bit for Master 0"] +pub struct RCB0_R(crate::FieldReader); +impl RCB0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB0_A { + match self.bits { + false => RCB0_A::DIS, + true => RCB0_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB0_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB0_A::ENA + } +} +impl core::ops::Deref for RCB0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB0` writer - Remap Command Bit for Master 0"] +pub struct RCB0_W<'a> { + w: &'a mut W, +} +impl<'a> RCB0_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB0_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB0_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB0_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Remap Command Bit for Master 1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB1_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB1_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB1` reader - Remap Command Bit for Master 1"] +pub struct RCB1_R(crate::FieldReader); +impl RCB1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB1_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB1_A { + match self.bits { + false => RCB1_A::DIS, + true => RCB1_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB1_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB1_A::ENA + } +} +impl core::ops::Deref for RCB1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB1` writer - Remap Command Bit for Master 1"] +pub struct RCB1_W<'a> { + w: &'a mut W, +} +impl<'a> RCB1_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB1_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB1_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB1_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Remap Command Bit for Master 2\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB2_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB2_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB2` reader - Remap Command Bit for Master 2"] +pub struct RCB2_R(crate::FieldReader); +impl RCB2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB2_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB2_A { + match self.bits { + false => RCB2_A::DIS, + true => RCB2_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB2_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB2_A::ENA + } +} +impl core::ops::Deref for RCB2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB2` writer - Remap Command Bit for Master 2"] +pub struct RCB2_W<'a> { + w: &'a mut W, +} +impl<'a> RCB2_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB2_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB2_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB2_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Remap Command Bit for Master 3\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB3_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB3_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB3` reader - Remap Command Bit for Master 3"] +pub struct RCB3_R(crate::FieldReader); +impl RCB3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB3_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB3_A { + match self.bits { + false => RCB3_A::DIS, + true => RCB3_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB3_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB3_A::ENA + } +} +impl core::ops::Deref for RCB3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB3` writer - Remap Command Bit for Master 3"] +pub struct RCB3_W<'a> { + w: &'a mut W, +} +impl<'a> RCB3_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB3_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB3_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB3_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Remap Command Bit for Master 4\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB4_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB4_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB4` reader - Remap Command Bit for Master 4"] +pub struct RCB4_R(crate::FieldReader); +impl RCB4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB4_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB4_A { + match self.bits { + false => RCB4_A::DIS, + true => RCB4_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB4_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB4_A::ENA + } +} +impl core::ops::Deref for RCB4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB4` writer - Remap Command Bit for Master 4"] +pub struct RCB4_W<'a> { + w: &'a mut W, +} +impl<'a> RCB4_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB4_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB4_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB4_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Remap Command Bit for Master 5\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB5_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB5_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB5` reader - Remap Command Bit for Master 5"] +pub struct RCB5_R(crate::FieldReader); +impl RCB5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB5_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB5_A { + match self.bits { + false => RCB5_A::DIS, + true => RCB5_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB5_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB5_A::ENA + } +} +impl core::ops::Deref for RCB5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB5` writer - Remap Command Bit for Master 5"] +pub struct RCB5_W<'a> { + w: &'a mut W, +} +impl<'a> RCB5_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB5_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB5_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB5_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Remap Command Bit for Master 6\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB6_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB6_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB6` reader - Remap Command Bit for Master 6"] +pub struct RCB6_R(crate::FieldReader); +impl RCB6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB6_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB6_A { + match self.bits { + false => RCB6_A::DIS, + true => RCB6_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB6_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB6_A::ENA + } +} +impl core::ops::Deref for RCB6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB6` writer - Remap Command Bit for Master 6"] +pub struct RCB6_W<'a> { + w: &'a mut W, +} +impl<'a> RCB6_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB6_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB6_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB6_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Remap Command Bit for Master 7\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB7_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB7_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB7` reader - Remap Command Bit for Master 7"] +pub struct RCB7_R(crate::FieldReader); +impl RCB7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB7_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB7_A { + match self.bits { + false => RCB7_A::DIS, + true => RCB7_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB7_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB7_A::ENA + } +} +impl core::ops::Deref for RCB7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB7` writer - Remap Command Bit for Master 7"] +pub struct RCB7_W<'a> { + w: &'a mut W, +} +impl<'a> RCB7_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB7_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB7_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB7_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Remap Command Bit for Master 8\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB8_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB8_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB8` reader - Remap Command Bit for Master 8"] +pub struct RCB8_R(crate::FieldReader); +impl RCB8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB8_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB8_A { + match self.bits { + false => RCB8_A::DIS, + true => RCB8_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB8_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB8_A::ENA + } +} +impl core::ops::Deref for RCB8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB8` writer - Remap Command Bit for Master 8"] +pub struct RCB8_W<'a> { + w: &'a mut W, +} +impl<'a> RCB8_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB8_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB8_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB8_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Remap Command Bit for Master 9\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB9_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB9_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB9` reader - Remap Command Bit for Master 9"] +pub struct RCB9_R(crate::FieldReader); +impl RCB9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB9_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB9_A { + match self.bits { + false => RCB9_A::DIS, + true => RCB9_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB9_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB9_A::ENA + } +} +impl core::ops::Deref for RCB9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB9` writer - Remap Command Bit for Master 9"] +pub struct RCB9_W<'a> { + w: &'a mut W, +} +impl<'a> RCB9_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB9_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB9_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB9_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Remap Command Bit for Master 10\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB10_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB10_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB10` reader - Remap Command Bit for Master 10"] +pub struct RCB10_R(crate::FieldReader); +impl RCB10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB10_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB10_A { + match self.bits { + false => RCB10_A::DIS, + true => RCB10_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB10_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB10_A::ENA + } +} +impl core::ops::Deref for RCB10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB10` writer - Remap Command Bit for Master 10"] +pub struct RCB10_W<'a> { + w: &'a mut W, +} +impl<'a> RCB10_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB10_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB10_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB10_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Remap Command Bit for Master 11\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB11_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB11_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB11` reader - Remap Command Bit for Master 11"] +pub struct RCB11_R(crate::FieldReader); +impl RCB11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB11_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB11_A { + match self.bits { + false => RCB11_A::DIS, + true => RCB11_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB11_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB11_A::ENA + } +} +impl core::ops::Deref for RCB11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB11` writer - Remap Command Bit for Master 11"] +pub struct RCB11_W<'a> { + w: &'a mut W, +} +impl<'a> RCB11_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB11_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB11_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB11_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Remap Command Bit for Master 12\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB12_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB12_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB12` reader - Remap Command Bit for Master 12"] +pub struct RCB12_R(crate::FieldReader); +impl RCB12_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB12_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB12_A { + match self.bits { + false => RCB12_A::DIS, + true => RCB12_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB12_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB12_A::ENA + } +} +impl core::ops::Deref for RCB12_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB12` writer - Remap Command Bit for Master 12"] +pub struct RCB12_W<'a> { + w: &'a mut W, +} +impl<'a> RCB12_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB12_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB12_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB12_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Remap Command Bit for Master 13\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB13_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB13_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB13` reader - Remap Command Bit for Master 13"] +pub struct RCB13_R(crate::FieldReader); +impl RCB13_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB13_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB13_A { + match self.bits { + false => RCB13_A::DIS, + true => RCB13_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB13_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB13_A::ENA + } +} +impl core::ops::Deref for RCB13_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB13` writer - Remap Command Bit for Master 13"] +pub struct RCB13_W<'a> { + w: &'a mut W, +} +impl<'a> RCB13_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB13_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB13_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB13_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Remap Command Bit for Master 14\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB14_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB14_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB14` reader - Remap Command Bit for Master 14"] +pub struct RCB14_R(crate::FieldReader); +impl RCB14_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB14_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB14_A { + match self.bits { + false => RCB14_A::DIS, + true => RCB14_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB14_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB14_A::ENA + } +} +impl core::ops::Deref for RCB14_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB14` writer - Remap Command Bit for Master 14"] +pub struct RCB14_W<'a> { + w: &'a mut W, +} +impl<'a> RCB14_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB14_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB14_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB14_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Remap Command Bit for Master 15\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB15_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB15_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB15` reader - Remap Command Bit for Master 15"] +pub struct RCB15_R(crate::FieldReader); +impl RCB15_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB15_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB15_A { + match self.bits { + false => RCB15_A::DIS, + true => RCB15_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB15_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB15_A::ENA + } +} +impl core::ops::Deref for RCB15_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB15` writer - Remap Command Bit for Master 15"] +pub struct RCB15_W<'a> { + w: &'a mut W, +} +impl<'a> RCB15_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB15_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB15_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB15_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Remap Command Bit for Master 0"] + #[inline(always)] + pub fn rcb0(&self) -> RCB0_R { + RCB0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Remap Command Bit for Master 1"] + #[inline(always)] + pub fn rcb1(&self) -> RCB1_R { + RCB1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Remap Command Bit for Master 2"] + #[inline(always)] + pub fn rcb2(&self) -> RCB2_R { + RCB2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Remap Command Bit for Master 3"] + #[inline(always)] + pub fn rcb3(&self) -> RCB3_R { + RCB3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Remap Command Bit for Master 4"] + #[inline(always)] + pub fn rcb4(&self) -> RCB4_R { + RCB4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Remap Command Bit for Master 5"] + #[inline(always)] + pub fn rcb5(&self) -> RCB5_R { + RCB5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Remap Command Bit for Master 6"] + #[inline(always)] + pub fn rcb6(&self) -> RCB6_R { + RCB6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Remap Command Bit for Master 7"] + #[inline(always)] + pub fn rcb7(&self) -> RCB7_R { + RCB7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Remap Command Bit for Master 8"] + #[inline(always)] + pub fn rcb8(&self) -> RCB8_R { + RCB8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Remap Command Bit for Master 9"] + #[inline(always)] + pub fn rcb9(&self) -> RCB9_R { + RCB9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Remap Command Bit for Master 10"] + #[inline(always)] + pub fn rcb10(&self) -> RCB10_R { + RCB10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Remap Command Bit for Master 11"] + #[inline(always)] + pub fn rcb11(&self) -> RCB11_R { + RCB11_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Remap Command Bit for Master 12"] + #[inline(always)] + pub fn rcb12(&self) -> RCB12_R { + RCB12_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Remap Command Bit for Master 13"] + #[inline(always)] + pub fn rcb13(&self) -> RCB13_R { + RCB13_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Remap Command Bit for Master 14"] + #[inline(always)] + pub fn rcb14(&self) -> RCB14_R { + RCB14_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Remap Command Bit for Master 15"] + #[inline(always)] + pub fn rcb15(&self) -> RCB15_R { + RCB15_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Remap Command Bit for Master 0"] + #[inline(always)] + pub fn rcb0(&mut self) -> RCB0_W { + RCB0_W { w: self } + } + #[doc = "Bit 1 - Remap Command Bit for Master 1"] + #[inline(always)] + pub fn rcb1(&mut self) -> RCB1_W { + RCB1_W { w: self } + } + #[doc = "Bit 2 - Remap Command Bit for Master 2"] + #[inline(always)] + pub fn rcb2(&mut self) -> RCB2_W { + RCB2_W { w: self } + } + #[doc = "Bit 3 - Remap Command Bit for Master 3"] + #[inline(always)] + pub fn rcb3(&mut self) -> RCB3_W { + RCB3_W { w: self } + } + #[doc = "Bit 4 - Remap Command Bit for Master 4"] + #[inline(always)] + pub fn rcb4(&mut self) -> RCB4_W { + RCB4_W { w: self } + } + #[doc = "Bit 5 - Remap Command Bit for Master 5"] + #[inline(always)] + pub fn rcb5(&mut self) -> RCB5_W { + RCB5_W { w: self } + } + #[doc = "Bit 6 - Remap Command Bit for Master 6"] + #[inline(always)] + pub fn rcb6(&mut self) -> RCB6_W { + RCB6_W { w: self } + } + #[doc = "Bit 7 - Remap Command Bit for Master 7"] + #[inline(always)] + pub fn rcb7(&mut self) -> RCB7_W { + RCB7_W { w: self } + } + #[doc = "Bit 8 - Remap Command Bit for Master 8"] + #[inline(always)] + pub fn rcb8(&mut self) -> RCB8_W { + RCB8_W { w: self } + } + #[doc = "Bit 9 - Remap Command Bit for Master 9"] + #[inline(always)] + pub fn rcb9(&mut self) -> RCB9_W { + RCB9_W { w: self } + } + #[doc = "Bit 10 - Remap Command Bit for Master 10"] + #[inline(always)] + pub fn rcb10(&mut self) -> RCB10_W { + RCB10_W { w: self } + } + #[doc = "Bit 11 - Remap Command Bit for Master 11"] + #[inline(always)] + pub fn rcb11(&mut self) -> RCB11_W { + RCB11_W { w: self } + } + #[doc = "Bit 12 - Remap Command Bit for Master 12"] + #[inline(always)] + pub fn rcb12(&mut self) -> RCB12_W { + RCB12_W { w: self } + } + #[doc = "Bit 13 - Remap Command Bit for Master 13"] + #[inline(always)] + pub fn rcb13(&mut self) -> RCB13_W { + RCB13_W { w: self } + } + #[doc = "Bit 14 - Remap Command Bit for Master 14"] + #[inline(always)] + pub fn rcb14(&mut self) -> RCB14_W { + RCB14_W { w: self } + } + #[doc = "Bit 15 - Remap Command Bit for Master 15"] + #[inline(always)] + pub fn rcb15(&mut self) -> RCB15_W { + RCB15_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Master Remap Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mrcr](index.html) module"] +pub struct MRCR_SPEC; +impl crate::RegisterSpec for MRCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [mrcr::R](R) reader structure"] +impl crate::Readable for MRCR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [mrcr::W](W) writer structure"] +impl crate::Writable for MRCR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets MRCR to value 0"] +impl crate::Resettable for MRCR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/hmatrixhs/prs.rs b/pac/atsamc20g/src/hmatrixhs/prs.rs new file mode 100644 index 000000000000..0313f3c4fc20 --- /dev/null +++ b/pac/atsamc20g/src/hmatrixhs/prs.rs @@ -0,0 +1,8 @@ +#[doc = "PRAS register accessor: an alias for `Reg`"] +pub type PRAS = crate::Reg; +#[doc = "Priority A for Slave"] +pub mod pras; +#[doc = "PRBS register accessor: an alias for `Reg`"] +pub type PRBS = crate::Reg; +#[doc = "Priority B for Slave"] +pub mod prbs; diff --git a/pac/atsamc20g/src/hmatrixhs/prs/pras.rs b/pac/atsamc20g/src/hmatrixhs/prs/pras.rs new file mode 100644 index 000000000000..ac4744a9e2a0 --- /dev/null +++ b/pac/atsamc20g/src/hmatrixhs/prs/pras.rs @@ -0,0 +1,362 @@ +#[doc = "Register `PRAS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PRAS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `M0PR` reader - Master 0 Priority"] +pub struct M0PR_R(crate::FieldReader); +impl M0PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M0PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M0PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M0PR` writer - Master 0 Priority"] +pub struct M0PR_W<'a> { + w: &'a mut W, +} +impl<'a> M0PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Field `M1PR` reader - Master 1 Priority"] +pub struct M1PR_R(crate::FieldReader); +impl M1PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M1PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M1PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M1PR` writer - Master 1 Priority"] +pub struct M1PR_W<'a> { + w: &'a mut W, +} +impl<'a> M1PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 4)) | ((value as u32 & 0x0f) << 4); + self.w + } +} +#[doc = "Field `M2PR` reader - Master 2 Priority"] +pub struct M2PR_R(crate::FieldReader); +impl M2PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M2PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M2PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M2PR` writer - Master 2 Priority"] +pub struct M2PR_W<'a> { + w: &'a mut W, +} +impl<'a> M2PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 8)) | ((value as u32 & 0x0f) << 8); + self.w + } +} +#[doc = "Field `M3PR` reader - Master 3 Priority"] +pub struct M3PR_R(crate::FieldReader); +impl M3PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M3PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M3PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M3PR` writer - Master 3 Priority"] +pub struct M3PR_W<'a> { + w: &'a mut W, +} +impl<'a> M3PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 12)) | ((value as u32 & 0x0f) << 12); + self.w + } +} +#[doc = "Field `M4PR` reader - Master 4 Priority"] +pub struct M4PR_R(crate::FieldReader); +impl M4PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M4PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M4PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M4PR` writer - Master 4 Priority"] +pub struct M4PR_W<'a> { + w: &'a mut W, +} +impl<'a> M4PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 16)) | ((value as u32 & 0x0f) << 16); + self.w + } +} +#[doc = "Field `M5PR` reader - Master 5 Priority"] +pub struct M5PR_R(crate::FieldReader); +impl M5PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M5PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M5PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M5PR` writer - Master 5 Priority"] +pub struct M5PR_W<'a> { + w: &'a mut W, +} +impl<'a> M5PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 20)) | ((value as u32 & 0x0f) << 20); + self.w + } +} +#[doc = "Field `M6PR` reader - Master 6 Priority"] +pub struct M6PR_R(crate::FieldReader); +impl M6PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M6PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M6PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M6PR` writer - Master 6 Priority"] +pub struct M6PR_W<'a> { + w: &'a mut W, +} +impl<'a> M6PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Field `M7PR` reader - Master 7 Priority"] +pub struct M7PR_R(crate::FieldReader); +impl M7PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M7PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M7PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M7PR` writer - Master 7 Priority"] +pub struct M7PR_W<'a> { + w: &'a mut W, +} +impl<'a> M7PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 28)) | ((value as u32 & 0x0f) << 28); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Master 0 Priority"] + #[inline(always)] + pub fn m0pr(&self) -> M0PR_R { + M0PR_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Master 1 Priority"] + #[inline(always)] + pub fn m1pr(&self) -> M1PR_R { + M1PR_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 8:11 - Master 2 Priority"] + #[inline(always)] + pub fn m2pr(&self) -> M2PR_R { + M2PR_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - Master 3 Priority"] + #[inline(always)] + pub fn m3pr(&self) -> M3PR_R { + M3PR_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:19 - Master 4 Priority"] + #[inline(always)] + pub fn m4pr(&self) -> M4PR_R { + M4PR_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bits 20:23 - Master 5 Priority"] + #[inline(always)] + pub fn m5pr(&self) -> M5PR_R { + M5PR_R::new(((self.bits >> 20) & 0x0f) as u8) + } + #[doc = "Bits 24:27 - Master 6 Priority"] + #[inline(always)] + pub fn m6pr(&self) -> M6PR_R { + M6PR_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bits 28:31 - Master 7 Priority"] + #[inline(always)] + pub fn m7pr(&self) -> M7PR_R { + M7PR_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Master 0 Priority"] + #[inline(always)] + pub fn m0pr(&mut self) -> M0PR_W { + M0PR_W { w: self } + } + #[doc = "Bits 4:7 - Master 1 Priority"] + #[inline(always)] + pub fn m1pr(&mut self) -> M1PR_W { + M1PR_W { w: self } + } + #[doc = "Bits 8:11 - Master 2 Priority"] + #[inline(always)] + pub fn m2pr(&mut self) -> M2PR_W { + M2PR_W { w: self } + } + #[doc = "Bits 12:15 - Master 3 Priority"] + #[inline(always)] + pub fn m3pr(&mut self) -> M3PR_W { + M3PR_W { w: self } + } + #[doc = "Bits 16:19 - Master 4 Priority"] + #[inline(always)] + pub fn m4pr(&mut self) -> M4PR_W { + M4PR_W { w: self } + } + #[doc = "Bits 20:23 - Master 5 Priority"] + #[inline(always)] + pub fn m5pr(&mut self) -> M5PR_W { + M5PR_W { w: self } + } + #[doc = "Bits 24:27 - Master 6 Priority"] + #[inline(always)] + pub fn m6pr(&mut self) -> M6PR_W { + M6PR_W { w: self } + } + #[doc = "Bits 28:31 - Master 7 Priority"] + #[inline(always)] + pub fn m7pr(&mut self) -> M7PR_W { + M7PR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Priority A for Slave\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pras](index.html) module"] +pub struct PRAS_SPEC; +impl crate::RegisterSpec for PRAS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pras::R](R) reader structure"] +impl crate::Readable for PRAS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [pras::W](W) writer structure"] +impl crate::Writable for PRAS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PRAS to value 0"] +impl crate::Resettable for PRAS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/hmatrixhs/prs/prbs.rs b/pac/atsamc20g/src/hmatrixhs/prs/prbs.rs new file mode 100644 index 000000000000..a2cc6bb9f6b0 --- /dev/null +++ b/pac/atsamc20g/src/hmatrixhs/prs/prbs.rs @@ -0,0 +1,362 @@ +#[doc = "Register `PRBS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PRBS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `M8PR` reader - Master 8 Priority"] +pub struct M8PR_R(crate::FieldReader); +impl M8PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M8PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M8PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M8PR` writer - Master 8 Priority"] +pub struct M8PR_W<'a> { + w: &'a mut W, +} +impl<'a> M8PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Field `M9PR` reader - Master 9 Priority"] +pub struct M9PR_R(crate::FieldReader); +impl M9PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M9PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M9PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M9PR` writer - Master 9 Priority"] +pub struct M9PR_W<'a> { + w: &'a mut W, +} +impl<'a> M9PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 4)) | ((value as u32 & 0x0f) << 4); + self.w + } +} +#[doc = "Field `M10PR` reader - Master 10 Priority"] +pub struct M10PR_R(crate::FieldReader); +impl M10PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M10PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M10PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M10PR` writer - Master 10 Priority"] +pub struct M10PR_W<'a> { + w: &'a mut W, +} +impl<'a> M10PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 8)) | ((value as u32 & 0x0f) << 8); + self.w + } +} +#[doc = "Field `M11PR` reader - Master 11 Priority"] +pub struct M11PR_R(crate::FieldReader); +impl M11PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M11PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M11PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M11PR` writer - Master 11 Priority"] +pub struct M11PR_W<'a> { + w: &'a mut W, +} +impl<'a> M11PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 12)) | ((value as u32 & 0x0f) << 12); + self.w + } +} +#[doc = "Field `M12PR` reader - Master 12 Priority"] +pub struct M12PR_R(crate::FieldReader); +impl M12PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M12PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M12PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M12PR` writer - Master 12 Priority"] +pub struct M12PR_W<'a> { + w: &'a mut W, +} +impl<'a> M12PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 16)) | ((value as u32 & 0x0f) << 16); + self.w + } +} +#[doc = "Field `M13PR` reader - Master 13 Priority"] +pub struct M13PR_R(crate::FieldReader); +impl M13PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M13PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M13PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M13PR` writer - Master 13 Priority"] +pub struct M13PR_W<'a> { + w: &'a mut W, +} +impl<'a> M13PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 20)) | ((value as u32 & 0x0f) << 20); + self.w + } +} +#[doc = "Field `M14PR` reader - Master 14 Priority"] +pub struct M14PR_R(crate::FieldReader); +impl M14PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M14PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M14PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M14PR` writer - Master 14 Priority"] +pub struct M14PR_W<'a> { + w: &'a mut W, +} +impl<'a> M14PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Field `M15PR` reader - Master 15 Priority"] +pub struct M15PR_R(crate::FieldReader); +impl M15PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M15PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M15PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M15PR` writer - Master 15 Priority"] +pub struct M15PR_W<'a> { + w: &'a mut W, +} +impl<'a> M15PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 28)) | ((value as u32 & 0x0f) << 28); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Master 8 Priority"] + #[inline(always)] + pub fn m8pr(&self) -> M8PR_R { + M8PR_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Master 9 Priority"] + #[inline(always)] + pub fn m9pr(&self) -> M9PR_R { + M9PR_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 8:11 - Master 10 Priority"] + #[inline(always)] + pub fn m10pr(&self) -> M10PR_R { + M10PR_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - Master 11 Priority"] + #[inline(always)] + pub fn m11pr(&self) -> M11PR_R { + M11PR_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:19 - Master 12 Priority"] + #[inline(always)] + pub fn m12pr(&self) -> M12PR_R { + M12PR_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bits 20:23 - Master 13 Priority"] + #[inline(always)] + pub fn m13pr(&self) -> M13PR_R { + M13PR_R::new(((self.bits >> 20) & 0x0f) as u8) + } + #[doc = "Bits 24:27 - Master 14 Priority"] + #[inline(always)] + pub fn m14pr(&self) -> M14PR_R { + M14PR_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bits 28:31 - Master 15 Priority"] + #[inline(always)] + pub fn m15pr(&self) -> M15PR_R { + M15PR_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Master 8 Priority"] + #[inline(always)] + pub fn m8pr(&mut self) -> M8PR_W { + M8PR_W { w: self } + } + #[doc = "Bits 4:7 - Master 9 Priority"] + #[inline(always)] + pub fn m9pr(&mut self) -> M9PR_W { + M9PR_W { w: self } + } + #[doc = "Bits 8:11 - Master 10 Priority"] + #[inline(always)] + pub fn m10pr(&mut self) -> M10PR_W { + M10PR_W { w: self } + } + #[doc = "Bits 12:15 - Master 11 Priority"] + #[inline(always)] + pub fn m11pr(&mut self) -> M11PR_W { + M11PR_W { w: self } + } + #[doc = "Bits 16:19 - Master 12 Priority"] + #[inline(always)] + pub fn m12pr(&mut self) -> M12PR_W { + M12PR_W { w: self } + } + #[doc = "Bits 20:23 - Master 13 Priority"] + #[inline(always)] + pub fn m13pr(&mut self) -> M13PR_W { + M13PR_W { w: self } + } + #[doc = "Bits 24:27 - Master 14 Priority"] + #[inline(always)] + pub fn m14pr(&mut self) -> M14PR_W { + M14PR_W { w: self } + } + #[doc = "Bits 28:31 - Master 15 Priority"] + #[inline(always)] + pub fn m15pr(&mut self) -> M15PR_W { + M15PR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Priority B for Slave\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [prbs](index.html) module"] +pub struct PRBS_SPEC; +impl crate::RegisterSpec for PRBS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [prbs::R](R) reader structure"] +impl crate::Readable for PRBS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [prbs::W](W) writer structure"] +impl crate::Writable for PRBS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PRBS to value 0"] +impl crate::Resettable for PRBS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/hmatrixhs/scfg.rs b/pac/atsamc20g/src/hmatrixhs/scfg.rs new file mode 100644 index 000000000000..7180c043195a --- /dev/null +++ b/pac/atsamc20g/src/hmatrixhs/scfg.rs @@ -0,0 +1,334 @@ +#[doc = "Register `SCFG[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SCFG[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SLOT_CYCLE` reader - Maximum Number of Allowed Cycles for a Burst"] +pub struct SLOT_CYCLE_R(crate::FieldReader); +impl SLOT_CYCLE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SLOT_CYCLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SLOT_CYCLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLOT_CYCLE` writer - Maximum Number of Allowed Cycles for a Burst"] +pub struct SLOT_CYCLE_W<'a> { + w: &'a mut W, +} +impl<'a> SLOT_CYCLE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +#[doc = "Default Master Type\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DEFMSTR_TYPE_A { + #[doc = "0: No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst."] + NO_DEFAULT = 0, + #[doc = "1: Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave."] + LAST_DEFAULT = 1, + #[doc = "2: Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave."] + FIXED_DEFAULT = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DEFMSTR_TYPE_A) -> Self { + variant as _ + } +} +#[doc = "Field `DEFMSTR_TYPE` reader - Default Master Type"] +pub struct DEFMSTR_TYPE_R(crate::FieldReader); +impl DEFMSTR_TYPE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DEFMSTR_TYPE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(DEFMSTR_TYPE_A::NO_DEFAULT), + 1 => Some(DEFMSTR_TYPE_A::LAST_DEFAULT), + 2 => Some(DEFMSTR_TYPE_A::FIXED_DEFAULT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NO_DEFAULT`"] + #[inline(always)] + pub fn is_no_default(&self) -> bool { + **self == DEFMSTR_TYPE_A::NO_DEFAULT + } + #[doc = "Checks if the value of the field is `LAST_DEFAULT`"] + #[inline(always)] + pub fn is_last_default(&self) -> bool { + **self == DEFMSTR_TYPE_A::LAST_DEFAULT + } + #[doc = "Checks if the value of the field is `FIXED_DEFAULT`"] + #[inline(always)] + pub fn is_fixed_default(&self) -> bool { + **self == DEFMSTR_TYPE_A::FIXED_DEFAULT + } +} +impl core::ops::Deref for DEFMSTR_TYPE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DEFMSTR_TYPE` writer - Default Master Type"] +pub struct DEFMSTR_TYPE_W<'a> { + w: &'a mut W, +} +impl<'a> DEFMSTR_TYPE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DEFMSTR_TYPE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst."] + #[inline(always)] + pub fn no_default(self) -> &'a mut W { + self.variant(DEFMSTR_TYPE_A::NO_DEFAULT) + } + #[doc = "Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave."] + #[inline(always)] + pub fn last_default(self) -> &'a mut W { + self.variant(DEFMSTR_TYPE_A::LAST_DEFAULT) + } + #[doc = "Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave."] + #[inline(always)] + pub fn fixed_default(self) -> &'a mut W { + self.variant(DEFMSTR_TYPE_A::FIXED_DEFAULT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Field `FIXED_DEFMSTR` reader - Fixed Index of Default Master"] +pub struct FIXED_DEFMSTR_R(crate::FieldReader); +impl FIXED_DEFMSTR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FIXED_DEFMSTR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FIXED_DEFMSTR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FIXED_DEFMSTR` writer - Fixed Index of Default Master"] +pub struct FIXED_DEFMSTR_W<'a> { + w: &'a mut W, +} +impl<'a> FIXED_DEFMSTR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 18)) | ((value as u32 & 0x0f) << 18); + self.w + } +} +#[doc = "Arbitration Type\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ARBT_A { + #[doc = "0: Round-Robin Arbitration"] + ROUND_ROBIN = 0, + #[doc = "1: Fixed Priority Arbitration"] + FIXED_PRIORITY = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ARBT_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ARBT` reader - Arbitration Type"] +pub struct ARBT_R(crate::FieldReader); +impl ARBT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ARBT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ARBT_A { + match self.bits { + false => ARBT_A::ROUND_ROBIN, + true => ARBT_A::FIXED_PRIORITY, + } + } + #[doc = "Checks if the value of the field is `ROUND_ROBIN`"] + #[inline(always)] + pub fn is_round_robin(&self) -> bool { + **self == ARBT_A::ROUND_ROBIN + } + #[doc = "Checks if the value of the field is `FIXED_PRIORITY`"] + #[inline(always)] + pub fn is_fixed_priority(&self) -> bool { + **self == ARBT_A::FIXED_PRIORITY + } +} +impl core::ops::Deref for ARBT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ARBT` writer - Arbitration Type"] +pub struct ARBT_W<'a> { + w: &'a mut W, +} +impl<'a> ARBT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: ARBT_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Round-Robin Arbitration"] + #[inline(always)] + pub fn round_robin(self) -> &'a mut W { + self.variant(ARBT_A::ROUND_ROBIN) + } + #[doc = "Fixed Priority Arbitration"] + #[inline(always)] + pub fn fixed_priority(self) -> &'a mut W { + self.variant(ARBT_A::FIXED_PRIORITY) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Maximum Number of Allowed Cycles for a Burst"] + #[inline(always)] + pub fn slot_cycle(&self) -> SLOT_CYCLE_R { + SLOT_CYCLE_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 16:17 - Default Master Type"] + #[inline(always)] + pub fn defmstr_type(&self) -> DEFMSTR_TYPE_R { + DEFMSTR_TYPE_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bits 18:21 - Fixed Index of Default Master"] + #[inline(always)] + pub fn fixed_defmstr(&self) -> FIXED_DEFMSTR_R { + FIXED_DEFMSTR_R::new(((self.bits >> 18) & 0x0f) as u8) + } + #[doc = "Bit 24 - Arbitration Type"] + #[inline(always)] + pub fn arbt(&self) -> ARBT_R { + ARBT_R::new(((self.bits >> 24) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - Maximum Number of Allowed Cycles for a Burst"] + #[inline(always)] + pub fn slot_cycle(&mut self) -> SLOT_CYCLE_W { + SLOT_CYCLE_W { w: self } + } + #[doc = "Bits 16:17 - Default Master Type"] + #[inline(always)] + pub fn defmstr_type(&mut self) -> DEFMSTR_TYPE_W { + DEFMSTR_TYPE_W { w: self } + } + #[doc = "Bits 18:21 - Fixed Index of Default Master"] + #[inline(always)] + pub fn fixed_defmstr(&mut self) -> FIXED_DEFMSTR_W { + FIXED_DEFMSTR_W { w: self } + } + #[doc = "Bit 24 - Arbitration Type"] + #[inline(always)] + pub fn arbt(&mut self) -> ARBT_W { + ARBT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Slave Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [scfg](index.html) module"] +pub struct SCFG_SPEC; +impl crate::RegisterSpec for SCFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [scfg::R](R) reader structure"] +impl crate::Readable for SCFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [scfg::W](W) writer structure"] +impl crate::Writable for SCFG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SCFG[%s] +to value 0x10"] +impl crate::Resettable for SCFG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x10 + } +} diff --git a/pac/atsamc20g/src/hmatrixhs/sfr.rs b/pac/atsamc20g/src/hmatrixhs/sfr.rs new file mode 100644 index 000000000000..0a7e024f73c8 --- /dev/null +++ b/pac/atsamc20g/src/hmatrixhs/sfr.rs @@ -0,0 +1,104 @@ +#[doc = "Register `SFR[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SFR[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SFR` reader - Special Function Register"] +pub struct SFR_R(crate::FieldReader); +impl SFR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + SFR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SFR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SFR` writer - Special Function Register"] +pub struct SFR_W<'a> { + w: &'a mut W, +} +impl<'a> SFR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Special Function Register"] + #[inline(always)] + pub fn sfr(&self) -> SFR_R { + SFR_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Special Function Register"] + #[inline(always)] + pub fn sfr(&mut self) -> SFR_W { + SFR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Special Function\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sfr](index.html) module"] +pub struct SFR_SPEC; +impl crate::RegisterSpec for SFR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [sfr::R](R) reader structure"] +impl crate::Readable for SFR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [sfr::W](W) writer structure"] +impl crate::Writable for SFR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SFR[%s] +to value 0"] +impl crate::Resettable for SFR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/lib.rs b/pac/atsamc20g/src/lib.rs new file mode 100644 index 000000000000..465de37602e7 --- /dev/null +++ b/pac/atsamc20g/src/lib.rs @@ -0,0 +1,1437 @@ +#![doc = "Peripheral access API for ATSAMC20G microcontrollers (generated using svd2rust v0.20.0 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] +svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.20.0/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"] +#![deny(const_err)] +#![deny(dead_code)] +#![deny(improper_ctypes)] +#![deny(missing_docs)] +#![deny(no_mangle_generic_items)] +#![deny(non_shorthand_field_patterns)] +#![deny(overflowing_literals)] +#![deny(path_statements)] +#![deny(patterns_in_fns_without_body)] +#![deny(private_in_public)] +#![deny(unconditional_recursion)] +#![deny(unused_allocation)] +#![deny(unused_comparisons)] +#![deny(unused_parens)] +#![deny(while_true)] +#![allow(non_camel_case_types)] +#![allow(non_snake_case)] +#![allow(clippy::all)] +#![no_std] +use core::marker::PhantomData; +use core::ops::Deref; +#[doc = r"Number available in the NVIC for configuring priority"] +pub const NVIC_PRIO_BITS: u8 = 2; +#[cfg(feature = "rt")] +pub use self::Interrupt as interrupt; +pub use cortex_m::peripheral::Peripherals as CorePeripherals; +pub use cortex_m::peripheral::{CBP, CPUID, DCB, DWT, FPB, ITM, MPU, NVIC, SCB, SYST, TPIU}; +#[cfg(feature = "rt")] +pub use cortex_m_rt::interrupt; +#[allow(unused_imports)] +use generic::*; +#[doc = r"Common register and bit access and modify traits"] +pub mod generic; +#[cfg(feature = "rt")] +extern "C" { + fn WDT(); + fn RTC(); + fn EIC(); + fn FREQM(); + fn NVMCTRL(); + fn DMAC(); + fn EVSYS(); + fn SERCOM0(); + fn SERCOM1(); + fn SERCOM2(); + fn SERCOM3(); + fn TCC0(); + fn TCC1(); + fn TCC2(); + fn TC0(); + fn TC1(); + fn TC2(); + fn TC3(); + fn TC4(); + fn ADC0(); + fn AC(); + fn PTC(); +} +#[doc(hidden)] +pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, +} +#[cfg(feature = "rt")] +#[doc(hidden)] +#[link_section = ".vector_table.interrupts"] +#[no_mangle] +pub static __INTERRUPTS: [Vector; 31] = [ + Vector { _reserved: 0 }, + Vector { _handler: WDT }, + Vector { _handler: RTC }, + Vector { _handler: EIC }, + Vector { _handler: FREQM }, + Vector { _reserved: 0 }, + Vector { _handler: NVMCTRL }, + Vector { _handler: DMAC }, + Vector { _handler: EVSYS }, + Vector { _handler: SERCOM0 }, + Vector { _handler: SERCOM1 }, + Vector { _handler: SERCOM2 }, + Vector { _handler: SERCOM3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TCC0 }, + Vector { _handler: TCC1 }, + Vector { _handler: TCC2 }, + Vector { _handler: TC0 }, + Vector { _handler: TC1 }, + Vector { _handler: TC2 }, + Vector { _handler: TC3 }, + Vector { _handler: TC4 }, + Vector { _handler: ADC0 }, + Vector { _reserved: 0 }, + Vector { _handler: AC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: PTC }, +]; +#[doc = r"Enumeration of all the interrupts."] +#[derive(Copy, Clone, Debug, PartialEq, Eq)] +#[repr(u16)] +pub enum Interrupt { + #[doc = "1 - WDT"] + WDT = 1, + #[doc = "2 - RTC"] + RTC = 2, + #[doc = "3 - EIC"] + EIC = 3, + #[doc = "4 - FREQM"] + FREQM = 4, + #[doc = "6 - NVMCTRL"] + NVMCTRL = 6, + #[doc = "7 - DMAC"] + DMAC = 7, + #[doc = "8 - EVSYS"] + EVSYS = 8, + #[doc = "9 - SERCOM0"] + SERCOM0 = 9, + #[doc = "10 - SERCOM1"] + SERCOM1 = 10, + #[doc = "11 - SERCOM2"] + SERCOM2 = 11, + #[doc = "12 - SERCOM3"] + SERCOM3 = 12, + #[doc = "17 - TCC0"] + TCC0 = 17, + #[doc = "18 - TCC1"] + TCC1 = 18, + #[doc = "19 - TCC2"] + TCC2 = 19, + #[doc = "20 - TC0"] + TC0 = 20, + #[doc = "21 - TC1"] + TC1 = 21, + #[doc = "22 - TC2"] + TC2 = 22, + #[doc = "23 - TC3"] + TC3 = 23, + #[doc = "24 - TC4"] + TC4 = 24, + #[doc = "25 - ADC0"] + ADC0 = 25, + #[doc = "27 - AC"] + AC = 27, + #[doc = "30 - PTC"] + PTC = 30, +} +unsafe impl cortex_m::interrupt::InterruptNumber for Interrupt { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } +} +#[doc = "Analog Comparators"] +pub struct AC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for AC {} +impl AC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const ac::RegisterBlock = 0x4200_5000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const ac::RegisterBlock { + Self::PTR + } +} +impl Deref for AC { + type Target = ac::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for AC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AC").finish() + } +} +#[doc = "Analog Comparators"] +pub mod ac; +#[doc = "Analog Digital Converter"] +pub struct ADC0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for ADC0 {} +impl ADC0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const adc0::RegisterBlock = 0x4200_4400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const adc0::RegisterBlock { + Self::PTR + } +} +impl Deref for ADC0 { + type Target = adc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for ADC0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ADC0").finish() + } +} +#[doc = "Analog Digital Converter"] +pub mod adc0; +#[doc = "Configurable Custom Logic"] +pub struct CCL { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for CCL {} +impl CCL { + #[doc = r"Pointer to the register block"] + pub const PTR: *const ccl::RegisterBlock = 0x4200_5c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const ccl::RegisterBlock { + Self::PTR + } +} +impl Deref for CCL { + type Target = ccl::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for CCL { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CCL").finish() + } +} +#[doc = "Configurable Custom Logic"] +pub mod ccl; +#[doc = "Divide and Square Root Accelerator"] +pub struct DIVAS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for DIVAS {} +impl DIVAS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const divas::RegisterBlock = 0x4800_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const divas::RegisterBlock { + Self::PTR + } +} +impl Deref for DIVAS { + type Target = divas::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for DIVAS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DIVAS").finish() + } +} +#[doc = "Divide and Square Root Accelerator"] +pub mod divas; +#[doc = "Direct Memory Access Controller"] +pub struct DMAC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for DMAC {} +impl DMAC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const dmac::RegisterBlock = 0x4100_6000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const dmac::RegisterBlock { + Self::PTR + } +} +impl Deref for DMAC { + type Target = dmac::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for DMAC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DMAC").finish() + } +} +#[doc = "Direct Memory Access Controller"] +pub mod dmac; +#[doc = "Device Service Unit"] +pub struct DSU { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for DSU {} +impl DSU { + #[doc = r"Pointer to the register block"] + pub const PTR: *const dsu::RegisterBlock = 0x4100_2000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const dsu::RegisterBlock { + Self::PTR + } +} +impl Deref for DSU { + type Target = dsu::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for DSU { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DSU").finish() + } +} +#[doc = "Device Service Unit"] +pub mod dsu; +#[doc = "External Interrupt Controller"] +pub struct EIC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for EIC {} +impl EIC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const eic::RegisterBlock = 0x4000_2800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const eic::RegisterBlock { + Self::PTR + } +} +impl Deref for EIC { + type Target = eic::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for EIC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EIC").finish() + } +} +#[doc = "External Interrupt Controller"] +pub mod eic; +#[doc = "Event System Interface"] +pub struct EVSYS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for EVSYS {} +impl EVSYS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const evsys::RegisterBlock = 0x4200_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const evsys::RegisterBlock { + Self::PTR + } +} +impl Deref for EVSYS { + type Target = evsys::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for EVSYS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EVSYS").finish() + } +} +#[doc = "Event System Interface"] +pub mod evsys; +#[doc = "Frequency Meter"] +pub struct FREQM { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for FREQM {} +impl FREQM { + #[doc = r"Pointer to the register block"] + pub const PTR: *const freqm::RegisterBlock = 0x4000_2c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const freqm::RegisterBlock { + Self::PTR + } +} +impl Deref for FREQM { + type Target = freqm::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for FREQM { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FREQM").finish() + } +} +#[doc = "Frequency Meter"] +pub mod freqm; +#[doc = "Generic Clock Generator"] +pub struct GCLK { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for GCLK {} +impl GCLK { + #[doc = r"Pointer to the register block"] + pub const PTR: *const gclk::RegisterBlock = 0x4000_1c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const gclk::RegisterBlock { + Self::PTR + } +} +impl Deref for GCLK { + type Target = gclk::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for GCLK { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GCLK").finish() + } +} +#[doc = "Generic Clock Generator"] +pub mod gclk; +#[doc = "HSB Matrix"] +pub struct HMATRIXHS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for HMATRIXHS {} +impl HMATRIXHS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const hmatrixhs::RegisterBlock = 0x4100_a000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const hmatrixhs::RegisterBlock { + Self::PTR + } +} +impl Deref for HMATRIXHS { + type Target = hmatrixhs::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for HMATRIXHS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HMATRIXHS").finish() + } +} +#[doc = "HSB Matrix"] +pub mod hmatrixhs; +#[doc = "Main Clock"] +pub struct MCLK { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for MCLK {} +impl MCLK { + #[doc = r"Pointer to the register block"] + pub const PTR: *const mclk::RegisterBlock = 0x4000_0800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const mclk::RegisterBlock { + Self::PTR + } +} +impl Deref for MCLK { + type Target = mclk::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for MCLK { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MCLK").finish() + } +} +#[doc = "Main Clock"] +pub mod mclk; +#[doc = "Cortex-M0+ Micro-Trace Buffer"] +pub struct MTB { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for MTB {} +impl MTB { + #[doc = r"Pointer to the register block"] + pub const PTR: *const mtb::RegisterBlock = 0x4100_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const mtb::RegisterBlock { + Self::PTR + } +} +impl Deref for MTB { + type Target = mtb::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for MTB { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MTB").finish() + } +} +#[doc = "Cortex-M0+ Micro-Trace Buffer"] +pub mod mtb; +#[doc = "Non-Volatile Memory Controller"] +pub struct NVMCTRL { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for NVMCTRL {} +impl NVMCTRL { + #[doc = r"Pointer to the register block"] + pub const PTR: *const nvmctrl::RegisterBlock = 0x4100_4000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const nvmctrl::RegisterBlock { + Self::PTR + } +} +impl Deref for NVMCTRL { + type Target = nvmctrl::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for NVMCTRL { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("NVMCTRL").finish() + } +} +#[doc = "Non-Volatile Memory Controller"] +pub mod nvmctrl; +#[doc = "Oscillators Control"] +pub struct OSCCTRL { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for OSCCTRL {} +impl OSCCTRL { + #[doc = r"Pointer to the register block"] + pub const PTR: *const oscctrl::RegisterBlock = 0x4000_1000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const oscctrl::RegisterBlock { + Self::PTR + } +} +impl Deref for OSCCTRL { + type Target = oscctrl::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for OSCCTRL { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OSCCTRL").finish() + } +} +#[doc = "Oscillators Control"] +pub mod oscctrl; +#[doc = "32k Oscillators Control"] +pub struct OSC32KCTRL { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for OSC32KCTRL {} +impl OSC32KCTRL { + #[doc = r"Pointer to the register block"] + pub const PTR: *const osc32kctrl::RegisterBlock = 0x4000_1400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const osc32kctrl::RegisterBlock { + Self::PTR + } +} +impl Deref for OSC32KCTRL { + type Target = osc32kctrl::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for OSC32KCTRL { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OSC32KCTRL").finish() + } +} +#[doc = "32k Oscillators Control"] +pub mod osc32kctrl; +#[doc = "Peripheral Access Controller"] +pub struct PAC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PAC {} +impl PAC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const pac::RegisterBlock = 0x4000_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const pac::RegisterBlock { + Self::PTR + } +} +impl Deref for PAC { + type Target = pac::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PAC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PAC").finish() + } +} +#[doc = "Peripheral Access Controller"] +pub mod pac; +#[doc = "Power Manager"] +pub struct PM { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PM {} +impl PM { + #[doc = r"Pointer to the register block"] + pub const PTR: *const pm::RegisterBlock = 0x4000_0400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const pm::RegisterBlock { + Self::PTR + } +} +impl Deref for PM { + type Target = pm::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PM { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PM").finish() + } +} +#[doc = "Power Manager"] +pub mod pm; +#[doc = "Port Module"] +pub struct PORT { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PORT {} +impl PORT { + #[doc = r"Pointer to the register block"] + pub const PTR: *const port::RegisterBlock = 0x4100_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const port::RegisterBlock { + Self::PTR + } +} +impl Deref for PORT { + type Target = port::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PORT { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PORT").finish() + } +} +#[doc = "Port Module"] +pub mod port; +#[doc = "Port Module"] +pub struct PORT_IOBUS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PORT_IOBUS {} +impl PORT_IOBUS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const port::RegisterBlock = 0x6000_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const port::RegisterBlock { + Self::PTR + } +} +impl Deref for PORT_IOBUS { + type Target = port::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PORT_IOBUS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PORT_IOBUS").finish() + } +} +#[doc = "Port Module"] +pub use port as port_iobus; +#[doc = "Reset Controller"] +pub struct RSTC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for RSTC {} +impl RSTC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const rstc::RegisterBlock = 0x4000_0c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const rstc::RegisterBlock { + Self::PTR + } +} +impl Deref for RSTC { + type Target = rstc::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for RSTC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RSTC").finish() + } +} +#[doc = "Reset Controller"] +pub mod rstc; +#[doc = "Real-Time Counter"] +pub struct RTC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for RTC {} +impl RTC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const rtc::RegisterBlock = 0x4000_2400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const rtc::RegisterBlock { + Self::PTR + } +} +impl Deref for RTC { + type Target = rtc::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for RTC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RTC").finish() + } +} +#[doc = "Real-Time Counter"] +pub mod rtc; +#[doc = "Serial Communication Interface"] +pub struct SERCOM0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SERCOM0 {} +impl SERCOM0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sercom0::RegisterBlock = 0x4200_0400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sercom0::RegisterBlock { + Self::PTR + } +} +impl Deref for SERCOM0 { + type Target = sercom0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SERCOM0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SERCOM0").finish() + } +} +#[doc = "Serial Communication Interface"] +pub mod sercom0; +#[doc = "Serial Communication Interface"] +pub struct SERCOM1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SERCOM1 {} +impl SERCOM1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sercom0::RegisterBlock = 0x4200_0800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sercom0::RegisterBlock { + Self::PTR + } +} +impl Deref for SERCOM1 { + type Target = sercom0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SERCOM1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SERCOM1").finish() + } +} +#[doc = "Serial Communication Interface"] +pub use sercom0 as sercom1; +#[doc = "Serial Communication Interface"] +pub struct SERCOM2 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SERCOM2 {} +impl SERCOM2 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sercom0::RegisterBlock = 0x4200_0c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sercom0::RegisterBlock { + Self::PTR + } +} +impl Deref for SERCOM2 { + type Target = sercom0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SERCOM2 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SERCOM2").finish() + } +} +#[doc = "Serial Communication Interface"] +pub use sercom0 as sercom2; +#[doc = "Serial Communication Interface"] +pub struct SERCOM3 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SERCOM3 {} +impl SERCOM3 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sercom0::RegisterBlock = 0x4200_1000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sercom0::RegisterBlock { + Self::PTR + } +} +impl Deref for SERCOM3 { + type Target = sercom0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SERCOM3 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SERCOM3").finish() + } +} +#[doc = "Serial Communication Interface"] +pub use sercom0 as sercom3; +#[doc = "Supply Controller"] +pub struct SUPC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SUPC {} +impl SUPC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const supc::RegisterBlock = 0x4000_1800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const supc::RegisterBlock { + Self::PTR + } +} +impl Deref for SUPC { + type Target = supc::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SUPC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SUPC").finish() + } +} +#[doc = "Supply Controller"] +pub mod supc; +#[doc = "Basic Timer Counter"] +pub struct TC0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TC0 {} +impl TC0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tc0::RegisterBlock = 0x4200_3000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tc0::RegisterBlock { + Self::PTR + } +} +impl Deref for TC0 { + type Target = tc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TC0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TC0").finish() + } +} +#[doc = "Basic Timer Counter"] +pub mod tc0; +#[doc = "Basic Timer Counter"] +pub struct TC1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TC1 {} +impl TC1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tc0::RegisterBlock = 0x4200_3400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tc0::RegisterBlock { + Self::PTR + } +} +impl Deref for TC1 { + type Target = tc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TC1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TC1").finish() + } +} +#[doc = "Basic Timer Counter"] +pub use tc0 as tc1; +#[doc = "Basic Timer Counter"] +pub struct TC2 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TC2 {} +impl TC2 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tc0::RegisterBlock = 0x4200_3800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tc0::RegisterBlock { + Self::PTR + } +} +impl Deref for TC2 { + type Target = tc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TC2 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TC2").finish() + } +} +#[doc = "Basic Timer Counter"] +pub use tc0 as tc2; +#[doc = "Basic Timer Counter"] +pub struct TC3 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TC3 {} +impl TC3 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tc0::RegisterBlock = 0x4200_3c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tc0::RegisterBlock { + Self::PTR + } +} +impl Deref for TC3 { + type Target = tc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TC3 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TC3").finish() + } +} +#[doc = "Basic Timer Counter"] +pub use tc0 as tc3; +#[doc = "Basic Timer Counter"] +pub struct TC4 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TC4 {} +impl TC4 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tc0::RegisterBlock = 0x4200_4000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tc0::RegisterBlock { + Self::PTR + } +} +impl Deref for TC4 { + type Target = tc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TC4 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TC4").finish() + } +} +#[doc = "Basic Timer Counter"] +pub use tc0 as tc4; +#[doc = "Timer Counter Control"] +pub struct TCC0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TCC0 {} +impl TCC0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tcc0::RegisterBlock = 0x4200_2400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tcc0::RegisterBlock { + Self::PTR + } +} +impl Deref for TCC0 { + type Target = tcc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TCC0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TCC0").finish() + } +} +#[doc = "Timer Counter Control"] +pub mod tcc0; +#[doc = "Timer Counter Control"] +pub struct TCC1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TCC1 {} +impl TCC1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tcc0::RegisterBlock = 0x4200_2800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tcc0::RegisterBlock { + Self::PTR + } +} +impl Deref for TCC1 { + type Target = tcc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TCC1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TCC1").finish() + } +} +#[doc = "Timer Counter Control"] +pub use tcc0 as tcc1; +#[doc = "Timer Counter Control"] +pub struct TCC2 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TCC2 {} +impl TCC2 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tcc0::RegisterBlock = 0x4200_2c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tcc0::RegisterBlock { + Self::PTR + } +} +impl Deref for TCC2 { + type Target = tcc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TCC2 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TCC2").finish() + } +} +#[doc = "Timer Counter Control"] +pub use tcc0 as tcc2; +#[doc = "Watchdog Timer"] +pub struct WDT { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for WDT {} +impl WDT { + #[doc = r"Pointer to the register block"] + pub const PTR: *const wdt::RegisterBlock = 0x4000_2000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const wdt::RegisterBlock { + Self::PTR + } +} +impl Deref for WDT { + type Target = wdt::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for WDT { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("WDT").finish() + } +} +#[doc = "Watchdog Timer"] +pub mod wdt; +#[doc = "System timer"] +pub struct SYSTICK { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SYSTICK {} +impl SYSTICK { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sys_tick::RegisterBlock = 0xe000_e010 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sys_tick::RegisterBlock { + Self::PTR + } +} +impl Deref for SYSTICK { + type Target = sys_tick::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SYSTICK { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SYSTICK").finish() + } +} +#[doc = "System timer"] +pub mod sys_tick; +#[doc = "System Control Registers"] +pub struct SYSTEMCONTROL { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SYSTEMCONTROL {} +impl SYSTEMCONTROL { + #[doc = r"Pointer to the register block"] + pub const PTR: *const system_control::RegisterBlock = 0xe000_e000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const system_control::RegisterBlock { + Self::PTR + } +} +impl Deref for SYSTEMCONTROL { + type Target = system_control::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SYSTEMCONTROL { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SYSTEMCONTROL").finish() + } +} +#[doc = "System Control Registers"] +pub mod system_control; +#[no_mangle] +static mut DEVICE_PERIPHERALS: bool = false; +#[doc = r"All the peripherals"] +#[allow(non_snake_case)] +pub struct Peripherals { + #[doc = "AC"] + pub AC: AC, + #[doc = "ADC0"] + pub ADC0: ADC0, + #[doc = "CCL"] + pub CCL: CCL, + #[doc = "DIVAS"] + pub DIVAS: DIVAS, + #[doc = "DMAC"] + pub DMAC: DMAC, + #[doc = "DSU"] + pub DSU: DSU, + #[doc = "EIC"] + pub EIC: EIC, + #[doc = "EVSYS"] + pub EVSYS: EVSYS, + #[doc = "FREQM"] + pub FREQM: FREQM, + #[doc = "GCLK"] + pub GCLK: GCLK, + #[doc = "HMATRIXHS"] + pub HMATRIXHS: HMATRIXHS, + #[doc = "MCLK"] + pub MCLK: MCLK, + #[doc = "MTB"] + pub MTB: MTB, + #[doc = "NVMCTRL"] + pub NVMCTRL: NVMCTRL, + #[doc = "OSCCTRL"] + pub OSCCTRL: OSCCTRL, + #[doc = "OSC32KCTRL"] + pub OSC32KCTRL: OSC32KCTRL, + #[doc = "PAC"] + pub PAC: PAC, + #[doc = "PM"] + pub PM: PM, + #[doc = "PORT"] + pub PORT: PORT, + #[doc = "PORT_IOBUS"] + pub PORT_IOBUS: PORT_IOBUS, + #[doc = "RSTC"] + pub RSTC: RSTC, + #[doc = "RTC"] + pub RTC: RTC, + #[doc = "SERCOM0"] + pub SERCOM0: SERCOM0, + #[doc = "SERCOM1"] + pub SERCOM1: SERCOM1, + #[doc = "SERCOM2"] + pub SERCOM2: SERCOM2, + #[doc = "SERCOM3"] + pub SERCOM3: SERCOM3, + #[doc = "SUPC"] + pub SUPC: SUPC, + #[doc = "TC0"] + pub TC0: TC0, + #[doc = "TC1"] + pub TC1: TC1, + #[doc = "TC2"] + pub TC2: TC2, + #[doc = "TC3"] + pub TC3: TC3, + #[doc = "TC4"] + pub TC4: TC4, + #[doc = "TCC0"] + pub TCC0: TCC0, + #[doc = "TCC1"] + pub TCC1: TCC1, + #[doc = "TCC2"] + pub TCC2: TCC2, + #[doc = "WDT"] + pub WDT: WDT, + #[doc = "SYSTICK"] + pub SYSTICK: SYSTICK, + #[doc = "SYSTEMCONTROL"] + pub SYSTEMCONTROL: SYSTEMCONTROL, +} +impl Peripherals { + #[doc = r"Returns all the peripherals *once*"] + #[inline] + pub fn take() -> Option { + cortex_m::interrupt::free(|_| { + if unsafe { DEVICE_PERIPHERALS } { + None + } else { + Some(unsafe { Peripherals::steal() }) + } + }) + } + #[doc = r"Unchecked version of `Peripherals::take`"] + #[inline] + pub unsafe fn steal() -> Self { + DEVICE_PERIPHERALS = true; + Peripherals { + AC: AC { + _marker: PhantomData, + }, + ADC0: ADC0 { + _marker: PhantomData, + }, + CCL: CCL { + _marker: PhantomData, + }, + DIVAS: DIVAS { + _marker: PhantomData, + }, + DMAC: DMAC { + _marker: PhantomData, + }, + DSU: DSU { + _marker: PhantomData, + }, + EIC: EIC { + _marker: PhantomData, + }, + EVSYS: EVSYS { + _marker: PhantomData, + }, + FREQM: FREQM { + _marker: PhantomData, + }, + GCLK: GCLK { + _marker: PhantomData, + }, + HMATRIXHS: HMATRIXHS { + _marker: PhantomData, + }, + MCLK: MCLK { + _marker: PhantomData, + }, + MTB: MTB { + _marker: PhantomData, + }, + NVMCTRL: NVMCTRL { + _marker: PhantomData, + }, + OSCCTRL: OSCCTRL { + _marker: PhantomData, + }, + OSC32KCTRL: OSC32KCTRL { + _marker: PhantomData, + }, + PAC: PAC { + _marker: PhantomData, + }, + PM: PM { + _marker: PhantomData, + }, + PORT: PORT { + _marker: PhantomData, + }, + PORT_IOBUS: PORT_IOBUS { + _marker: PhantomData, + }, + RSTC: RSTC { + _marker: PhantomData, + }, + RTC: RTC { + _marker: PhantomData, + }, + SERCOM0: SERCOM0 { + _marker: PhantomData, + }, + SERCOM1: SERCOM1 { + _marker: PhantomData, + }, + SERCOM2: SERCOM2 { + _marker: PhantomData, + }, + SERCOM3: SERCOM3 { + _marker: PhantomData, + }, + SUPC: SUPC { + _marker: PhantomData, + }, + TC0: TC0 { + _marker: PhantomData, + }, + TC1: TC1 { + _marker: PhantomData, + }, + TC2: TC2 { + _marker: PhantomData, + }, + TC3: TC3 { + _marker: PhantomData, + }, + TC4: TC4 { + _marker: PhantomData, + }, + TCC0: TCC0 { + _marker: PhantomData, + }, + TCC1: TCC1 { + _marker: PhantomData, + }, + TCC2: TCC2 { + _marker: PhantomData, + }, + WDT: WDT { + _marker: PhantomData, + }, + SYSTICK: SYSTICK { + _marker: PhantomData, + }, + SYSTEMCONTROL: SYSTEMCONTROL { + _marker: PhantomData, + }, + } + } +} diff --git a/pac/atsamc20g/src/mclk.rs b/pac/atsamc20g/src/mclk.rs new file mode 100644 index 000000000000..fc7efe3a584e --- /dev/null +++ b/pac/atsamc20g/src/mclk.rs @@ -0,0 +1,54 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved0: [u8; 0x01], + #[doc = "0x01 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x02 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x03 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x04 - CPU Clock Division"] + pub cpudiv: crate::Reg, + _reserved4: [u8; 0x0b], + #[doc = "0x10 - AHB Mask"] + pub ahbmask: crate::Reg, + #[doc = "0x14 - APBA Mask"] + pub apbamask: crate::Reg, + #[doc = "0x18 - APBB Mask"] + pub apbbmask: crate::Reg, + #[doc = "0x1c - APBC Mask"] + pub apbcmask: crate::Reg, +} +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "CPUDIV register accessor: an alias for `Reg`"] +pub type CPUDIV = crate::Reg; +#[doc = "CPU Clock Division"] +pub mod cpudiv; +#[doc = "AHBMASK register accessor: an alias for `Reg`"] +pub type AHBMASK = crate::Reg; +#[doc = "AHB Mask"] +pub mod ahbmask; +#[doc = "APBAMASK register accessor: an alias for `Reg`"] +pub type APBAMASK = crate::Reg; +#[doc = "APBA Mask"] +pub mod apbamask; +#[doc = "APBBMASK register accessor: an alias for `Reg`"] +pub type APBBMASK = crate::Reg; +#[doc = "APBB Mask"] +pub mod apbbmask; +#[doc = "APBCMASK register accessor: an alias for `Reg`"] +pub type APBCMASK = crate::Reg; +#[doc = "APBC Mask"] +pub mod apbcmask; diff --git a/pac/atsamc20g/src/mclk/ahbmask.rs b/pac/atsamc20g/src/mclk/ahbmask.rs new file mode 100644 index 000000000000..9366eb778bfa --- /dev/null +++ b/pac/atsamc20g/src/mclk/ahbmask.rs @@ -0,0 +1,583 @@ +#[doc = "Register `AHBMASK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `AHBMASK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `HPB0_` reader - HPB0 AHB Clock Mask"] +pub struct HPB0__R(crate::FieldReader); +impl HPB0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HPB0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HPB0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HPB0_` writer - HPB0 AHB Clock Mask"] +pub struct HPB0__W<'a> { + w: &'a mut W, +} +impl<'a> HPB0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `HPB1_` reader - HPB1 AHB Clock Mask"] +pub struct HPB1__R(crate::FieldReader); +impl HPB1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HPB1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HPB1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HPB1_` writer - HPB1 AHB Clock Mask"] +pub struct HPB1__W<'a> { + w: &'a mut W, +} +impl<'a> HPB1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `HPB2_` reader - HPB2 AHB Clock Mask"] +pub struct HPB2__R(crate::FieldReader); +impl HPB2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HPB2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HPB2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HPB2_` writer - HPB2 AHB Clock Mask"] +pub struct HPB2__W<'a> { + w: &'a mut W, +} +impl<'a> HPB2__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `DSU_` reader - DSU AHB Clock Mask"] +pub struct DSU__R(crate::FieldReader); +impl DSU__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DSU__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DSU__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DSU_` writer - DSU AHB Clock Mask"] +pub struct DSU__W<'a> { + w: &'a mut W, +} +impl<'a> DSU__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `HMATRIXHS_` reader - HMATRIXHS AHB Clock Mask"] +pub struct HMATRIXHS__R(crate::FieldReader); +impl HMATRIXHS__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HMATRIXHS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HMATRIXHS__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HMATRIXHS_` writer - HMATRIXHS AHB Clock Mask"] +pub struct HMATRIXHS__W<'a> { + w: &'a mut W, +} +impl<'a> HMATRIXHS__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `NVMCTRL_` reader - NVMCTRL AHB Clock Mask"] +pub struct NVMCTRL__R(crate::FieldReader); +impl NVMCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NVMCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NVMCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NVMCTRL_` writer - NVMCTRL AHB Clock Mask"] +pub struct NVMCTRL__W<'a> { + w: &'a mut W, +} +impl<'a> NVMCTRL__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `HSRAM_` reader - HSRAM AHB Clock Mask"] +pub struct HSRAM__R(crate::FieldReader); +impl HSRAM__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HSRAM__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HSRAM__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HSRAM_` writer - HSRAM AHB Clock Mask"] +pub struct HSRAM__W<'a> { + w: &'a mut W, +} +impl<'a> HSRAM__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `DMAC_` reader - DMAC AHB Clock Mask"] +pub struct DMAC__R(crate::FieldReader); +impl DMAC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DMAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DMAC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DMAC_` writer - DMAC AHB Clock Mask"] +pub struct DMAC__W<'a> { + w: &'a mut W, +} +impl<'a> DMAC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `PAC_` reader - PAC AHB Clock Mask"] +pub struct PAC__R(crate::FieldReader); +impl PAC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PAC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PAC_` writer - PAC AHB Clock Mask"] +pub struct PAC__W<'a> { + w: &'a mut W, +} +impl<'a> PAC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `NVMCTRL_PICACHU_` reader - NVMCTRL_PICACHU AHB Clock Mask"] +pub struct NVMCTRL_PICACHU__R(crate::FieldReader); +impl NVMCTRL_PICACHU__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NVMCTRL_PICACHU__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NVMCTRL_PICACHU__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NVMCTRL_PICACHU_` writer - NVMCTRL_PICACHU AHB Clock Mask"] +pub struct NVMCTRL_PICACHU__W<'a> { + w: &'a mut W, +} +impl<'a> NVMCTRL_PICACHU__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `DIVAS_` reader - DIVAS AHB Clock Mask"] +pub struct DIVAS__R(crate::FieldReader); +impl DIVAS__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIVAS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIVAS__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIVAS_` writer - DIVAS AHB Clock Mask"] +pub struct DIVAS__W<'a> { + w: &'a mut W, +} +impl<'a> DIVAS__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +impl R { + #[doc = "Bit 0 - HPB0 AHB Clock Mask"] + #[inline(always)] + pub fn hpb0_(&self) -> HPB0__R { + HPB0__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - HPB1 AHB Clock Mask"] + #[inline(always)] + pub fn hpb1_(&self) -> HPB1__R { + HPB1__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - HPB2 AHB Clock Mask"] + #[inline(always)] + pub fn hpb2_(&self) -> HPB2__R { + HPB2__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - DSU AHB Clock Mask"] + #[inline(always)] + pub fn dsu_(&self) -> DSU__R { + DSU__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - HMATRIXHS AHB Clock Mask"] + #[inline(always)] + pub fn hmatrixhs_(&self) -> HMATRIXHS__R { + HMATRIXHS__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - NVMCTRL AHB Clock Mask"] + #[inline(always)] + pub fn nvmctrl_(&self) -> NVMCTRL__R { + NVMCTRL__R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - HSRAM AHB Clock Mask"] + #[inline(always)] + pub fn hsram_(&self) -> HSRAM__R { + HSRAM__R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - DMAC AHB Clock Mask"] + #[inline(always)] + pub fn dmac_(&self) -> DMAC__R { + DMAC__R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 10 - PAC AHB Clock Mask"] + #[inline(always)] + pub fn pac_(&self) -> PAC__R { + PAC__R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - NVMCTRL_PICACHU AHB Clock Mask"] + #[inline(always)] + pub fn nvmctrl_picachu_(&self) -> NVMCTRL_PICACHU__R { + NVMCTRL_PICACHU__R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - DIVAS AHB Clock Mask"] + #[inline(always)] + pub fn divas_(&self) -> DIVAS__R { + DIVAS__R::new(((self.bits >> 12) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - HPB0 AHB Clock Mask"] + #[inline(always)] + pub fn hpb0_(&mut self) -> HPB0__W { + HPB0__W { w: self } + } + #[doc = "Bit 1 - HPB1 AHB Clock Mask"] + #[inline(always)] + pub fn hpb1_(&mut self) -> HPB1__W { + HPB1__W { w: self } + } + #[doc = "Bit 2 - HPB2 AHB Clock Mask"] + #[inline(always)] + pub fn hpb2_(&mut self) -> HPB2__W { + HPB2__W { w: self } + } + #[doc = "Bit 3 - DSU AHB Clock Mask"] + #[inline(always)] + pub fn dsu_(&mut self) -> DSU__W { + DSU__W { w: self } + } + #[doc = "Bit 4 - HMATRIXHS AHB Clock Mask"] + #[inline(always)] + pub fn hmatrixhs_(&mut self) -> HMATRIXHS__W { + HMATRIXHS__W { w: self } + } + #[doc = "Bit 5 - NVMCTRL AHB Clock Mask"] + #[inline(always)] + pub fn nvmctrl_(&mut self) -> NVMCTRL__W { + NVMCTRL__W { w: self } + } + #[doc = "Bit 6 - HSRAM AHB Clock Mask"] + #[inline(always)] + pub fn hsram_(&mut self) -> HSRAM__W { + HSRAM__W { w: self } + } + #[doc = "Bit 7 - DMAC AHB Clock Mask"] + #[inline(always)] + pub fn dmac_(&mut self) -> DMAC__W { + DMAC__W { w: self } + } + #[doc = "Bit 10 - PAC AHB Clock Mask"] + #[inline(always)] + pub fn pac_(&mut self) -> PAC__W { + PAC__W { w: self } + } + #[doc = "Bit 11 - NVMCTRL_PICACHU AHB Clock Mask"] + #[inline(always)] + pub fn nvmctrl_picachu_(&mut self) -> NVMCTRL_PICACHU__W { + NVMCTRL_PICACHU__W { w: self } + } + #[doc = "Bit 12 - DIVAS AHB Clock Mask"] + #[inline(always)] + pub fn divas_(&mut self) -> DIVAS__W { + DIVAS__W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "AHB Mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ahbmask](index.html) module"] +pub struct AHBMASK_SPEC; +impl crate::RegisterSpec for AHBMASK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ahbmask::R](R) reader structure"] +impl crate::Readable for AHBMASK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ahbmask::W](W) writer structure"] +impl crate::Writable for AHBMASK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets AHBMASK to value 0x1cff"] +impl crate::Resettable for AHBMASK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x1cff + } +} diff --git a/pac/atsamc20g/src/mclk/apbamask.rs b/pac/atsamc20g/src/mclk/apbamask.rs new file mode 100644 index 000000000000..3e095e73a158 --- /dev/null +++ b/pac/atsamc20g/src/mclk/apbamask.rs @@ -0,0 +1,630 @@ +#[doc = "Register `APBAMASK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `APBAMASK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PAC_` reader - PAC APB Clock Enable"] +pub struct PAC__R(crate::FieldReader); +impl PAC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PAC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PAC_` writer - PAC APB Clock Enable"] +pub struct PAC__W<'a> { + w: &'a mut W, +} +impl<'a> PAC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `PM_` reader - PM APB Clock Enable"] +pub struct PM__R(crate::FieldReader); +impl PM__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PM__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PM__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PM_` writer - PM APB Clock Enable"] +pub struct PM__W<'a> { + w: &'a mut W, +} +impl<'a> PM__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MCLK_` reader - MCLK APB Clock Enable"] +pub struct MCLK__R(crate::FieldReader); +impl MCLK__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCLK__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCLK__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCLK_` writer - MCLK APB Clock Enable"] +pub struct MCLK__W<'a> { + w: &'a mut W, +} +impl<'a> MCLK__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RSTC_` reader - RSTC APB Clock Enable"] +pub struct RSTC__R(crate::FieldReader); +impl RSTC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RSTC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RSTC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RSTC_` writer - RSTC APB Clock Enable"] +pub struct RSTC__W<'a> { + w: &'a mut W, +} +impl<'a> RSTC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `OSCCTRL_` reader - OSCCTRL APB Clock Enable"] +pub struct OSCCTRL__R(crate::FieldReader); +impl OSCCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSCCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSCCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSCCTRL_` writer - OSCCTRL APB Clock Enable"] +pub struct OSCCTRL__W<'a> { + w: &'a mut W, +} +impl<'a> OSCCTRL__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `OSC32KCTRL_` reader - OSC32KCTRL APB Clock Enable"] +pub struct OSC32KCTRL__R(crate::FieldReader); +impl OSC32KCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC32KCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC32KCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC32KCTRL_` writer - OSC32KCTRL APB Clock Enable"] +pub struct OSC32KCTRL__W<'a> { + w: &'a mut W, +} +impl<'a> OSC32KCTRL__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `SUPC_` reader - SUPC APB Clock Enable"] +pub struct SUPC__R(crate::FieldReader); +impl SUPC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SUPC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SUPC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SUPC_` writer - SUPC APB Clock Enable"] +pub struct SUPC__W<'a> { + w: &'a mut W, +} +impl<'a> SUPC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `GCLK_` reader - GCLK APB Clock Enable"] +pub struct GCLK__R(crate::FieldReader); +impl GCLK__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GCLK__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GCLK__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GCLK_` writer - GCLK APB Clock Enable"] +pub struct GCLK__W<'a> { + w: &'a mut W, +} +impl<'a> GCLK__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `WDT_` reader - WDT APB Clock Enable"] +pub struct WDT__R(crate::FieldReader); +impl WDT__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WDT__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WDT__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WDT_` writer - WDT APB Clock Enable"] +pub struct WDT__W<'a> { + w: &'a mut W, +} +impl<'a> WDT__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `RTC_` reader - RTC APB Clock Enable"] +pub struct RTC__R(crate::FieldReader); +impl RTC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RTC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RTC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RTC_` writer - RTC APB Clock Enable"] +pub struct RTC__W<'a> { + w: &'a mut W, +} +impl<'a> RTC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `EIC_` reader - EIC APB Clock Enable"] +pub struct EIC__R(crate::FieldReader); +impl EIC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EIC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EIC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EIC_` writer - EIC APB Clock Enable"] +pub struct EIC__W<'a> { + w: &'a mut W, +} +impl<'a> EIC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `FREQM_` reader - FREQM APB Clock Enable"] +pub struct FREQM__R(crate::FieldReader); +impl FREQM__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FREQM__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FREQM__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FREQM_` writer - FREQM APB Clock Enable"] +pub struct FREQM__W<'a> { + w: &'a mut W, +} +impl<'a> FREQM__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +impl R { + #[doc = "Bit 0 - PAC APB Clock Enable"] + #[inline(always)] + pub fn pac_(&self) -> PAC__R { + PAC__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - PM APB Clock Enable"] + #[inline(always)] + pub fn pm_(&self) -> PM__R { + PM__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - MCLK APB Clock Enable"] + #[inline(always)] + pub fn mclk_(&self) -> MCLK__R { + MCLK__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - RSTC APB Clock Enable"] + #[inline(always)] + pub fn rstc_(&self) -> RSTC__R { + RSTC__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - OSCCTRL APB Clock Enable"] + #[inline(always)] + pub fn oscctrl_(&self) -> OSCCTRL__R { + OSCCTRL__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - OSC32KCTRL APB Clock Enable"] + #[inline(always)] + pub fn osc32kctrl_(&self) -> OSC32KCTRL__R { + OSC32KCTRL__R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - SUPC APB Clock Enable"] + #[inline(always)] + pub fn supc_(&self) -> SUPC__R { + SUPC__R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - GCLK APB Clock Enable"] + #[inline(always)] + pub fn gclk_(&self) -> GCLK__R { + GCLK__R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - WDT APB Clock Enable"] + #[inline(always)] + pub fn wdt_(&self) -> WDT__R { + WDT__R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - RTC APB Clock Enable"] + #[inline(always)] + pub fn rtc_(&self) -> RTC__R { + RTC__R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - EIC APB Clock Enable"] + #[inline(always)] + pub fn eic_(&self) -> EIC__R { + EIC__R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - FREQM APB Clock Enable"] + #[inline(always)] + pub fn freqm_(&self) -> FREQM__R { + FREQM__R::new(((self.bits >> 11) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - PAC APB Clock Enable"] + #[inline(always)] + pub fn pac_(&mut self) -> PAC__W { + PAC__W { w: self } + } + #[doc = "Bit 1 - PM APB Clock Enable"] + #[inline(always)] + pub fn pm_(&mut self) -> PM__W { + PM__W { w: self } + } + #[doc = "Bit 2 - MCLK APB Clock Enable"] + #[inline(always)] + pub fn mclk_(&mut self) -> MCLK__W { + MCLK__W { w: self } + } + #[doc = "Bit 3 - RSTC APB Clock Enable"] + #[inline(always)] + pub fn rstc_(&mut self) -> RSTC__W { + RSTC__W { w: self } + } + #[doc = "Bit 4 - OSCCTRL APB Clock Enable"] + #[inline(always)] + pub fn oscctrl_(&mut self) -> OSCCTRL__W { + OSCCTRL__W { w: self } + } + #[doc = "Bit 5 - OSC32KCTRL APB Clock Enable"] + #[inline(always)] + pub fn osc32kctrl_(&mut self) -> OSC32KCTRL__W { + OSC32KCTRL__W { w: self } + } + #[doc = "Bit 6 - SUPC APB Clock Enable"] + #[inline(always)] + pub fn supc_(&mut self) -> SUPC__W { + SUPC__W { w: self } + } + #[doc = "Bit 7 - GCLK APB Clock Enable"] + #[inline(always)] + pub fn gclk_(&mut self) -> GCLK__W { + GCLK__W { w: self } + } + #[doc = "Bit 8 - WDT APB Clock Enable"] + #[inline(always)] + pub fn wdt_(&mut self) -> WDT__W { + WDT__W { w: self } + } + #[doc = "Bit 9 - RTC APB Clock Enable"] + #[inline(always)] + pub fn rtc_(&mut self) -> RTC__W { + RTC__W { w: self } + } + #[doc = "Bit 10 - EIC APB Clock Enable"] + #[inline(always)] + pub fn eic_(&mut self) -> EIC__W { + EIC__W { w: self } + } + #[doc = "Bit 11 - FREQM APB Clock Enable"] + #[inline(always)] + pub fn freqm_(&mut self) -> FREQM__W { + FREQM__W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "APBA Mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [apbamask](index.html) module"] +pub struct APBAMASK_SPEC; +impl crate::RegisterSpec for APBAMASK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [apbamask::R](R) reader structure"] +impl crate::Readable for APBAMASK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [apbamask::W](W) writer structure"] +impl crate::Writable for APBAMASK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets APBAMASK to value 0x0fff"] +impl crate::Resettable for APBAMASK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0fff + } +} diff --git a/pac/atsamc20g/src/mclk/apbbmask.rs b/pac/atsamc20g/src/mclk/apbbmask.rs new file mode 100644 index 000000000000..e1ec6b1f2323 --- /dev/null +++ b/pac/atsamc20g/src/mclk/apbbmask.rs @@ -0,0 +1,254 @@ +#[doc = "Register `APBBMASK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `APBBMASK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PORT_` reader - PORT APB Clock Enable"] +pub struct PORT__R(crate::FieldReader); +impl PORT__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PORT__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PORT__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PORT_` writer - PORT APB Clock Enable"] +pub struct PORT__W<'a> { + w: &'a mut W, +} +impl<'a> PORT__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `DSU_` reader - DSU APB Clock Enable"] +pub struct DSU__R(crate::FieldReader); +impl DSU__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DSU__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DSU__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DSU_` writer - DSU APB Clock Enable"] +pub struct DSU__W<'a> { + w: &'a mut W, +} +impl<'a> DSU__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `NVMCTRL_` reader - NVMCTRL APB Clock Enable"] +pub struct NVMCTRL__R(crate::FieldReader); +impl NVMCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NVMCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NVMCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NVMCTRL_` writer - NVMCTRL APB Clock Enable"] +pub struct NVMCTRL__W<'a> { + w: &'a mut W, +} +impl<'a> NVMCTRL__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `HMATRIXHS_` reader - HMATRIXHS APB Clock Enable"] +pub struct HMATRIXHS__R(crate::FieldReader); +impl HMATRIXHS__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HMATRIXHS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HMATRIXHS__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HMATRIXHS_` writer - HMATRIXHS APB Clock Enable"] +pub struct HMATRIXHS__W<'a> { + w: &'a mut W, +} +impl<'a> HMATRIXHS__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - PORT APB Clock Enable"] + #[inline(always)] + pub fn port_(&self) -> PORT__R { + PORT__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - DSU APB Clock Enable"] + #[inline(always)] + pub fn dsu_(&self) -> DSU__R { + DSU__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - NVMCTRL APB Clock Enable"] + #[inline(always)] + pub fn nvmctrl_(&self) -> NVMCTRL__R { + NVMCTRL__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 5 - HMATRIXHS APB Clock Enable"] + #[inline(always)] + pub fn hmatrixhs_(&self) -> HMATRIXHS__R { + HMATRIXHS__R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - PORT APB Clock Enable"] + #[inline(always)] + pub fn port_(&mut self) -> PORT__W { + PORT__W { w: self } + } + #[doc = "Bit 1 - DSU APB Clock Enable"] + #[inline(always)] + pub fn dsu_(&mut self) -> DSU__W { + DSU__W { w: self } + } + #[doc = "Bit 2 - NVMCTRL APB Clock Enable"] + #[inline(always)] + pub fn nvmctrl_(&mut self) -> NVMCTRL__W { + NVMCTRL__W { w: self } + } + #[doc = "Bit 5 - HMATRIXHS APB Clock Enable"] + #[inline(always)] + pub fn hmatrixhs_(&mut self) -> HMATRIXHS__W { + HMATRIXHS__W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "APBB Mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [apbbmask](index.html) module"] +pub struct APBBMASK_SPEC; +impl crate::RegisterSpec for APBBMASK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [apbbmask::R](R) reader structure"] +impl crate::Readable for APBBMASK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [apbbmask::W](W) writer structure"] +impl crate::Writable for APBBMASK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets APBBMASK to value 0x07"] +impl crate::Resettable for APBBMASK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x07 + } +} diff --git a/pac/atsamc20g/src/mclk/apbcmask.rs b/pac/atsamc20g/src/mclk/apbcmask.rs new file mode 100644 index 000000000000..64b4ce91fe5d --- /dev/null +++ b/pac/atsamc20g/src/mclk/apbcmask.rs @@ -0,0 +1,865 @@ +#[doc = "Register `APBCMASK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `APBCMASK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVSYS_` reader - EVSYS APB Clock Enable"] +pub struct EVSYS__R(crate::FieldReader); +impl EVSYS__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVSYS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVSYS__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVSYS_` writer - EVSYS APB Clock Enable"] +pub struct EVSYS__W<'a> { + w: &'a mut W, +} +impl<'a> EVSYS__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `SERCOM0_` reader - SERCOM0 APB Clock Enable"] +pub struct SERCOM0__R(crate::FieldReader); +impl SERCOM0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM0_` writer - SERCOM0 APB Clock Enable"] +pub struct SERCOM0__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SERCOM1_` reader - SERCOM1 APB Clock Enable"] +pub struct SERCOM1__R(crate::FieldReader); +impl SERCOM1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM1_` writer - SERCOM1 APB Clock Enable"] +pub struct SERCOM1__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SERCOM2_` reader - SERCOM2 APB Clock Enable"] +pub struct SERCOM2__R(crate::FieldReader); +impl SERCOM2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM2_` writer - SERCOM2 APB Clock Enable"] +pub struct SERCOM2__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM2__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `SERCOM3_` reader - SERCOM3 APB Clock Enable"] +pub struct SERCOM3__R(crate::FieldReader); +impl SERCOM3__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM3__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM3__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM3_` writer - SERCOM3 APB Clock Enable"] +pub struct SERCOM3__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM3__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `TCC0_` reader - TCC0 APB Clock Enable"] +pub struct TCC0__R(crate::FieldReader); +impl TCC0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCC0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCC0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCC0_` writer - TCC0 APB Clock Enable"] +pub struct TCC0__W<'a> { + w: &'a mut W, +} +impl<'a> TCC0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `TCC1_` reader - TCC1 APB Clock Enable"] +pub struct TCC1__R(crate::FieldReader); +impl TCC1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCC1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCC1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCC1_` writer - TCC1 APB Clock Enable"] +pub struct TCC1__W<'a> { + w: &'a mut W, +} +impl<'a> TCC1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `TCC2_` reader - TCC2 APB Clock Enable"] +pub struct TCC2__R(crate::FieldReader); +impl TCC2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCC2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCC2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCC2_` writer - TCC2 APB Clock Enable"] +pub struct TCC2__W<'a> { + w: &'a mut W, +} +impl<'a> TCC2__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `TC0_` reader - TC0 APB Clock Enable"] +pub struct TC0__R(crate::FieldReader); +impl TC0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC0_` writer - TC0 APB Clock Enable"] +pub struct TC0__W<'a> { + w: &'a mut W, +} +impl<'a> TC0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `TC1_` reader - TC1 APB Clock Enable"] +pub struct TC1__R(crate::FieldReader); +impl TC1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC1_` writer - TC1 APB Clock Enable"] +pub struct TC1__W<'a> { + w: &'a mut W, +} +impl<'a> TC1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `TC2_` reader - TC2 APB Clock Enable"] +pub struct TC2__R(crate::FieldReader); +impl TC2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC2_` writer - TC2 APB Clock Enable"] +pub struct TC2__W<'a> { + w: &'a mut W, +} +impl<'a> TC2__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `TC3_` reader - TC3 APB Clock Enable"] +pub struct TC3__R(crate::FieldReader); +impl TC3__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC3__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC3__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC3_` writer - TC3 APB Clock Enable"] +pub struct TC3__W<'a> { + w: &'a mut W, +} +impl<'a> TC3__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `TC4_` reader - TC4 APB Clock Enable"] +pub struct TC4__R(crate::FieldReader); +impl TC4__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC4__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC4__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC4_` writer - TC4 APB Clock Enable"] +pub struct TC4__W<'a> { + w: &'a mut W, +} +impl<'a> TC4__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `ADC0_` reader - ADC0 APB Clock Enable"] +pub struct ADC0__R(crate::FieldReader); +impl ADC0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ADC0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADC0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADC0_` writer - ADC0 APB Clock Enable"] +pub struct ADC0__W<'a> { + w: &'a mut W, +} +impl<'a> ADC0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `AC_` reader - AC APB Clock Enable"] +pub struct AC__R(crate::FieldReader); +impl AC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AC_` writer - AC APB Clock Enable"] +pub struct AC__W<'a> { + w: &'a mut W, +} +impl<'a> AC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `PTC_` reader - PTC APB Clock Enable"] +pub struct PTC__R(crate::FieldReader); +impl PTC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PTC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PTC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PTC_` writer - PTC APB Clock Enable"] +pub struct PTC__W<'a> { + w: &'a mut W, +} +impl<'a> PTC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `CCL_` reader - CCL APB Clock Enable"] +pub struct CCL__R(crate::FieldReader); +impl CCL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCL_` writer - CCL APB Clock Enable"] +pub struct CCL__W<'a> { + w: &'a mut W, +} +impl<'a> CCL__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +impl R { + #[doc = "Bit 0 - EVSYS APB Clock Enable"] + #[inline(always)] + pub fn evsys_(&self) -> EVSYS__R { + EVSYS__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM0 APB Clock Enable"] + #[inline(always)] + pub fn sercom0_(&self) -> SERCOM0__R { + SERCOM0__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - SERCOM1 APB Clock Enable"] + #[inline(always)] + pub fn sercom1_(&self) -> SERCOM1__R { + SERCOM1__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - SERCOM2 APB Clock Enable"] + #[inline(always)] + pub fn sercom2_(&self) -> SERCOM2__R { + SERCOM2__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - SERCOM3 APB Clock Enable"] + #[inline(always)] + pub fn sercom3_(&self) -> SERCOM3__R { + SERCOM3__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 9 - TCC0 APB Clock Enable"] + #[inline(always)] + pub fn tcc0_(&self) -> TCC0__R { + TCC0__R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - TCC1 APB Clock Enable"] + #[inline(always)] + pub fn tcc1_(&self) -> TCC1__R { + TCC1__R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - TCC2 APB Clock Enable"] + #[inline(always)] + pub fn tcc2_(&self) -> TCC2__R { + TCC2__R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - TC0 APB Clock Enable"] + #[inline(always)] + pub fn tc0_(&self) -> TC0__R { + TC0__R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - TC1 APB Clock Enable"] + #[inline(always)] + pub fn tc1_(&self) -> TC1__R { + TC1__R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - TC2 APB Clock Enable"] + #[inline(always)] + pub fn tc2_(&self) -> TC2__R { + TC2__R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - TC3 APB Clock Enable"] + #[inline(always)] + pub fn tc3_(&self) -> TC3__R { + TC3__R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - TC4 APB Clock Enable"] + #[inline(always)] + pub fn tc4_(&self) -> TC4__R { + TC4__R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - ADC0 APB Clock Enable"] + #[inline(always)] + pub fn adc0_(&self) -> ADC0__R { + ADC0__R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 20 - AC APB Clock Enable"] + #[inline(always)] + pub fn ac_(&self) -> AC__R { + AC__R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 22 - PTC APB Clock Enable"] + #[inline(always)] + pub fn ptc_(&self) -> PTC__R { + PTC__R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - CCL APB Clock Enable"] + #[inline(always)] + pub fn ccl_(&self) -> CCL__R { + CCL__R::new(((self.bits >> 23) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - EVSYS APB Clock Enable"] + #[inline(always)] + pub fn evsys_(&mut self) -> EVSYS__W { + EVSYS__W { w: self } + } + #[doc = "Bit 1 - SERCOM0 APB Clock Enable"] + #[inline(always)] + pub fn sercom0_(&mut self) -> SERCOM0__W { + SERCOM0__W { w: self } + } + #[doc = "Bit 2 - SERCOM1 APB Clock Enable"] + #[inline(always)] + pub fn sercom1_(&mut self) -> SERCOM1__W { + SERCOM1__W { w: self } + } + #[doc = "Bit 3 - SERCOM2 APB Clock Enable"] + #[inline(always)] + pub fn sercom2_(&mut self) -> SERCOM2__W { + SERCOM2__W { w: self } + } + #[doc = "Bit 4 - SERCOM3 APB Clock Enable"] + #[inline(always)] + pub fn sercom3_(&mut self) -> SERCOM3__W { + SERCOM3__W { w: self } + } + #[doc = "Bit 9 - TCC0 APB Clock Enable"] + #[inline(always)] + pub fn tcc0_(&mut self) -> TCC0__W { + TCC0__W { w: self } + } + #[doc = "Bit 10 - TCC1 APB Clock Enable"] + #[inline(always)] + pub fn tcc1_(&mut self) -> TCC1__W { + TCC1__W { w: self } + } + #[doc = "Bit 11 - TCC2 APB Clock Enable"] + #[inline(always)] + pub fn tcc2_(&mut self) -> TCC2__W { + TCC2__W { w: self } + } + #[doc = "Bit 12 - TC0 APB Clock Enable"] + #[inline(always)] + pub fn tc0_(&mut self) -> TC0__W { + TC0__W { w: self } + } + #[doc = "Bit 13 - TC1 APB Clock Enable"] + #[inline(always)] + pub fn tc1_(&mut self) -> TC1__W { + TC1__W { w: self } + } + #[doc = "Bit 14 - TC2 APB Clock Enable"] + #[inline(always)] + pub fn tc2_(&mut self) -> TC2__W { + TC2__W { w: self } + } + #[doc = "Bit 15 - TC3 APB Clock Enable"] + #[inline(always)] + pub fn tc3_(&mut self) -> TC3__W { + TC3__W { w: self } + } + #[doc = "Bit 16 - TC4 APB Clock Enable"] + #[inline(always)] + pub fn tc4_(&mut self) -> TC4__W { + TC4__W { w: self } + } + #[doc = "Bit 17 - ADC0 APB Clock Enable"] + #[inline(always)] + pub fn adc0_(&mut self) -> ADC0__W { + ADC0__W { w: self } + } + #[doc = "Bit 20 - AC APB Clock Enable"] + #[inline(always)] + pub fn ac_(&mut self) -> AC__W { + AC__W { w: self } + } + #[doc = "Bit 22 - PTC APB Clock Enable"] + #[inline(always)] + pub fn ptc_(&mut self) -> PTC__W { + PTC__W { w: self } + } + #[doc = "Bit 23 - CCL APB Clock Enable"] + #[inline(always)] + pub fn ccl_(&mut self) -> CCL__W { + CCL__W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "APBC Mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [apbcmask](index.html) module"] +pub struct APBCMASK_SPEC; +impl crate::RegisterSpec for APBCMASK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [apbcmask::R](R) reader structure"] +impl crate::Readable for APBCMASK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [apbcmask::W](W) writer structure"] +impl crate::Writable for APBCMASK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets APBCMASK to value 0"] +impl crate::Resettable for APBCMASK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/mclk/cpudiv.rs b/pac/atsamc20g/src/mclk/cpudiv.rs new file mode 100644 index 000000000000..a21fdae21357 --- /dev/null +++ b/pac/atsamc20g/src/mclk/cpudiv.rs @@ -0,0 +1,230 @@ +#[doc = "Register `CPUDIV` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CPUDIV` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "CPU Clock Division Factor\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CPUDIV_A { + #[doc = "1: Divide by 1"] + DIV1 = 1, + #[doc = "2: Divide by 2"] + DIV2 = 2, + #[doc = "4: Divide by 4"] + DIV4 = 4, + #[doc = "8: Divide by 8"] + DIV8 = 8, + #[doc = "16: Divide by 16"] + DIV16 = 16, + #[doc = "32: Divide by 32"] + DIV32 = 32, + #[doc = "64: Divide by 64"] + DIV64 = 64, + #[doc = "128: Divide by 128"] + DIV128 = 128, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CPUDIV_A) -> Self { + variant as _ + } +} +#[doc = "Field `CPUDIV` reader - CPU Clock Division Factor"] +pub struct CPUDIV_R(crate::FieldReader); +impl CPUDIV_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CPUDIV_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 1 => Some(CPUDIV_A::DIV1), + 2 => Some(CPUDIV_A::DIV2), + 4 => Some(CPUDIV_A::DIV4), + 8 => Some(CPUDIV_A::DIV8), + 16 => Some(CPUDIV_A::DIV16), + 32 => Some(CPUDIV_A::DIV32), + 64 => Some(CPUDIV_A::DIV64), + 128 => Some(CPUDIV_A::DIV128), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == CPUDIV_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == CPUDIV_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == CPUDIV_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == CPUDIV_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == CPUDIV_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == CPUDIV_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == CPUDIV_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == CPUDIV_A::DIV128 + } +} +impl core::ops::Deref for CPUDIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPUDIV` writer - CPU Clock Division Factor"] +pub struct CPUDIV_W<'a> { + w: &'a mut W, +} +impl<'a> CPUDIV_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CPUDIV_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Divide by 1"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV1) + } + #[doc = "Divide by 2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV2) + } + #[doc = "Divide by 4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV4) + } + #[doc = "Divide by 8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV8) + } + #[doc = "Divide by 16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV16) + } + #[doc = "Divide by 32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV32) + } + #[doc = "Divide by 64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV64) + } + #[doc = "Divide by 128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV128) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - CPU Clock Division Factor"] + #[inline(always)] + pub fn cpudiv(&self) -> CPUDIV_R { + CPUDIV_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - CPU Clock Division Factor"] + #[inline(always)] + pub fn cpudiv(&mut self) -> CPUDIV_W { + CPUDIV_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CPU Clock Division\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cpudiv](index.html) module"] +pub struct CPUDIV_SPEC; +impl crate::RegisterSpec for CPUDIV_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [cpudiv::R](R) reader structure"] +impl crate::Readable for CPUDIV_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cpudiv::W](W) writer structure"] +impl crate::Writable for CPUDIV_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CPUDIV to value 0x01"] +impl crate::Resettable for CPUDIV_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pac/atsamc20g/src/mclk/intenclr.rs b/pac/atsamc20g/src/mclk/intenclr.rs new file mode 100644 index 000000000000..14feb632dbb7 --- /dev/null +++ b/pac/atsamc20g/src/mclk/intenclr.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CKRDY` reader - Clock Ready Interrupt Enable"] +pub struct CKRDY_R(crate::FieldReader); +impl CKRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CKRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CKRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CKRDY` writer - Clock Ready Interrupt Enable"] +pub struct CKRDY_W<'a> { + w: &'a mut W, +} +impl<'a> CKRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Clock Ready Interrupt Enable"] + #[inline(always)] + pub fn ckrdy(&self) -> CKRDY_R { + CKRDY_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Clock Ready Interrupt Enable"] + #[inline(always)] + pub fn ckrdy(&mut self) -> CKRDY_W { + CKRDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/mclk/intenset.rs b/pac/atsamc20g/src/mclk/intenset.rs new file mode 100644 index 000000000000..f01fcc316d93 --- /dev/null +++ b/pac/atsamc20g/src/mclk/intenset.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CKRDY` reader - Clock Ready Interrupt Enable"] +pub struct CKRDY_R(crate::FieldReader); +impl CKRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CKRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CKRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CKRDY` writer - Clock Ready Interrupt Enable"] +pub struct CKRDY_W<'a> { + w: &'a mut W, +} +impl<'a> CKRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Clock Ready Interrupt Enable"] + #[inline(always)] + pub fn ckrdy(&self) -> CKRDY_R { + CKRDY_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Clock Ready Interrupt Enable"] + #[inline(always)] + pub fn ckrdy(&mut self) -> CKRDY_W { + CKRDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/mclk/intflag.rs b/pac/atsamc20g/src/mclk/intflag.rs new file mode 100644 index 000000000000..cf421d4ac61a --- /dev/null +++ b/pac/atsamc20g/src/mclk/intflag.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CKRDY` reader - Clock Ready"] +pub struct CKRDY_R(crate::FieldReader); +impl CKRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CKRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CKRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CKRDY` writer - Clock Ready"] +pub struct CKRDY_W<'a> { + w: &'a mut W, +} +impl<'a> CKRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Clock Ready"] + #[inline(always)] + pub fn ckrdy(&self) -> CKRDY_R { + CKRDY_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Clock Ready"] + #[inline(always)] + pub fn ckrdy(&mut self) -> CKRDY_W { + CKRDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0x01"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pac/atsamc20g/src/mtb.rs b/pac/atsamc20g/src/mtb.rs new file mode 100644 index 000000000000..01be005c0fb9 --- /dev/null +++ b/pac/atsamc20g/src/mtb.rs @@ -0,0 +1,158 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - MTB Position"] + pub position: crate::Reg, + #[doc = "0x04 - MTB Master"] + pub master: crate::Reg, + #[doc = "0x08 - MTB Flow"] + pub flow: crate::Reg, + #[doc = "0x0c - MTB Base"] + pub base: crate::Reg, + _reserved4: [u8; 0x0ef0], + #[doc = "0xf00 - MTB Integration Mode Control"] + pub itctrl: crate::Reg, + _reserved5: [u8; 0x9c], + #[doc = "0xfa0 - MTB Claim Set"] + pub claimset: crate::Reg, + #[doc = "0xfa4 - MTB Claim Clear"] + pub claimclr: crate::Reg, + _reserved7: [u8; 0x08], + #[doc = "0xfb0 - MTB Lock Access"] + pub lockaccess: crate::Reg, + #[doc = "0xfb4 - MTB Lock Status"] + pub lockstatus: crate::Reg, + #[doc = "0xfb8 - MTB Authentication Status"] + pub authstatus: crate::Reg, + #[doc = "0xfbc - MTB Device Architecture"] + pub devarch: crate::Reg, + _reserved11: [u8; 0x08], + #[doc = "0xfc8 - MTB Device Configuration"] + pub devid: crate::Reg, + #[doc = "0xfcc - MTB Device Type"] + pub devtype: crate::Reg, + #[doc = "0xfd0 - Peripheral Identification 4"] + pub pid4: crate::Reg, + #[doc = "0xfd4 - Peripheral Identification 5"] + pub pid5: crate::Reg, + #[doc = "0xfd8 - Peripheral Identification 6"] + pub pid6: crate::Reg, + #[doc = "0xfdc - Peripheral Identification 7"] + pub pid7: crate::Reg, + #[doc = "0xfe0 - Peripheral Identification 0"] + pub pid0: crate::Reg, + #[doc = "0xfe4 - Peripheral Identification 1"] + pub pid1: crate::Reg, + #[doc = "0xfe8 - Peripheral Identification 2"] + pub pid2: crate::Reg, + #[doc = "0xfec - Peripheral Identification 3"] + pub pid3: crate::Reg, + #[doc = "0xff0 - Component Identification 0"] + pub cid0: crate::Reg, + #[doc = "0xff4 - Component Identification 1"] + pub cid1: crate::Reg, + #[doc = "0xff8 - Component Identification 2"] + pub cid2: crate::Reg, + #[doc = "0xffc - Component Identification 3"] + pub cid3: crate::Reg, +} +#[doc = "POSITION register accessor: an alias for `Reg`"] +pub type POSITION = crate::Reg; +#[doc = "MTB Position"] +pub mod position; +#[doc = "MASTER register accessor: an alias for `Reg`"] +pub type MASTER = crate::Reg; +#[doc = "MTB Master"] +pub mod master; +#[doc = "FLOW register accessor: an alias for `Reg`"] +pub type FLOW = crate::Reg; +#[doc = "MTB Flow"] +pub mod flow; +#[doc = "BASE register accessor: an alias for `Reg`"] +pub type BASE = crate::Reg; +#[doc = "MTB Base"] +pub mod base; +#[doc = "ITCTRL register accessor: an alias for `Reg`"] +pub type ITCTRL = crate::Reg; +#[doc = "MTB Integration Mode Control"] +pub mod itctrl; +#[doc = "CLAIMSET register accessor: an alias for `Reg`"] +pub type CLAIMSET = crate::Reg; +#[doc = "MTB Claim Set"] +pub mod claimset; +#[doc = "CLAIMCLR register accessor: an alias for `Reg`"] +pub type CLAIMCLR = crate::Reg; +#[doc = "MTB Claim Clear"] +pub mod claimclr; +#[doc = "LOCKACCESS register accessor: an alias for `Reg`"] +pub type LOCKACCESS = crate::Reg; +#[doc = "MTB Lock Access"] +pub mod lockaccess; +#[doc = "LOCKSTATUS register accessor: an alias for `Reg`"] +pub type LOCKSTATUS = crate::Reg; +#[doc = "MTB Lock Status"] +pub mod lockstatus; +#[doc = "AUTHSTATUS register accessor: an alias for `Reg`"] +pub type AUTHSTATUS = crate::Reg; +#[doc = "MTB Authentication Status"] +pub mod authstatus; +#[doc = "DEVARCH register accessor: an alias for `Reg`"] +pub type DEVARCH = crate::Reg; +#[doc = "MTB Device Architecture"] +pub mod devarch; +#[doc = "DEVID register accessor: an alias for `Reg`"] +pub type DEVID = crate::Reg; +#[doc = "MTB Device Configuration"] +pub mod devid; +#[doc = "DEVTYPE register accessor: an alias for `Reg`"] +pub type DEVTYPE = crate::Reg; +#[doc = "MTB Device Type"] +pub mod devtype; +#[doc = "PID4 register accessor: an alias for `Reg`"] +pub type PID4 = crate::Reg; +#[doc = "Peripheral Identification 4"] +pub mod pid4; +#[doc = "PID5 register accessor: an alias for `Reg`"] +pub type PID5 = crate::Reg; +#[doc = "Peripheral Identification 5"] +pub mod pid5; +#[doc = "PID6 register accessor: an alias for `Reg`"] +pub type PID6 = crate::Reg; +#[doc = "Peripheral Identification 6"] +pub mod pid6; +#[doc = "PID7 register accessor: an alias for `Reg`"] +pub type PID7 = crate::Reg; +#[doc = "Peripheral Identification 7"] +pub mod pid7; +#[doc = "PID0 register accessor: an alias for `Reg`"] +pub type PID0 = crate::Reg; +#[doc = "Peripheral Identification 0"] +pub mod pid0; +#[doc = "PID1 register accessor: an alias for `Reg`"] +pub type PID1 = crate::Reg; +#[doc = "Peripheral Identification 1"] +pub mod pid1; +#[doc = "PID2 register accessor: an alias for `Reg`"] +pub type PID2 = crate::Reg; +#[doc = "Peripheral Identification 2"] +pub mod pid2; +#[doc = "PID3 register accessor: an alias for `Reg`"] +pub type PID3 = crate::Reg; +#[doc = "Peripheral Identification 3"] +pub mod pid3; +#[doc = "CID0 register accessor: an alias for `Reg`"] +pub type CID0 = crate::Reg; +#[doc = "Component Identification 0"] +pub mod cid0; +#[doc = "CID1 register accessor: an alias for `Reg`"] +pub type CID1 = crate::Reg; +#[doc = "Component Identification 1"] +pub mod cid1; +#[doc = "CID2 register accessor: an alias for `Reg`"] +pub type CID2 = crate::Reg; +#[doc = "Component Identification 2"] +pub mod cid2; +#[doc = "CID3 register accessor: an alias for `Reg`"] +pub type CID3 = crate::Reg; +#[doc = "Component Identification 3"] +pub mod cid3; diff --git a/pac/atsamc20g/src/mtb/authstatus.rs b/pac/atsamc20g/src/mtb/authstatus.rs new file mode 100644 index 000000000000..6fe441e0554d --- /dev/null +++ b/pac/atsamc20g/src/mtb/authstatus.rs @@ -0,0 +1,31 @@ +#[doc = "Register `AUTHSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "MTB Authentication Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [authstatus](index.html) module"] +pub struct AUTHSTATUS_SPEC; +impl crate::RegisterSpec for AUTHSTATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [authstatus::R](R) reader structure"] +impl crate::Readable for AUTHSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets AUTHSTATUS to value 0"] +impl crate::Resettable for AUTHSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/mtb/base.rs b/pac/atsamc20g/src/mtb/base.rs new file mode 100644 index 000000000000..f59b5a97a398 --- /dev/null +++ b/pac/atsamc20g/src/mtb/base.rs @@ -0,0 +1,31 @@ +#[doc = "Register `BASE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "MTB Base\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [base](index.html) module"] +pub struct BASE_SPEC; +impl crate::RegisterSpec for BASE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [base::R](R) reader structure"] +impl crate::Readable for BASE_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets BASE to value 0"] +impl crate::Resettable for BASE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/mtb/cid0.rs b/pac/atsamc20g/src/mtb/cid0.rs new file mode 100644 index 000000000000..e03bd35fa470 --- /dev/null +++ b/pac/atsamc20g/src/mtb/cid0.rs @@ -0,0 +1,31 @@ +#[doc = "Register `CID0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Component Identification 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid0](index.html) module"] +pub struct CID0_SPEC; +impl crate::RegisterSpec for CID0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid0::R](R) reader structure"] +impl crate::Readable for CID0_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID0 to value 0"] +impl crate::Resettable for CID0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/mtb/cid1.rs b/pac/atsamc20g/src/mtb/cid1.rs new file mode 100644 index 000000000000..1cafc8e0fb9a --- /dev/null +++ b/pac/atsamc20g/src/mtb/cid1.rs @@ -0,0 +1,31 @@ +#[doc = "Register `CID1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Component Identification 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid1](index.html) module"] +pub struct CID1_SPEC; +impl crate::RegisterSpec for CID1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid1::R](R) reader structure"] +impl crate::Readable for CID1_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID1 to value 0"] +impl crate::Resettable for CID1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/mtb/cid2.rs b/pac/atsamc20g/src/mtb/cid2.rs new file mode 100644 index 000000000000..6a91e4e23206 --- /dev/null +++ b/pac/atsamc20g/src/mtb/cid2.rs @@ -0,0 +1,31 @@ +#[doc = "Register `CID2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Component Identification 2\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid2](index.html) module"] +pub struct CID2_SPEC; +impl crate::RegisterSpec for CID2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid2::R](R) reader structure"] +impl crate::Readable for CID2_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID2 to value 0"] +impl crate::Resettable for CID2_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/mtb/cid3.rs b/pac/atsamc20g/src/mtb/cid3.rs new file mode 100644 index 000000000000..726290f4ffed --- /dev/null +++ b/pac/atsamc20g/src/mtb/cid3.rs @@ -0,0 +1,31 @@ +#[doc = "Register `CID3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Component Identification 3\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid3](index.html) module"] +pub struct CID3_SPEC; +impl crate::RegisterSpec for CID3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid3::R](R) reader structure"] +impl crate::Readable for CID3_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID3 to value 0"] +impl crate::Resettable for CID3_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/mtb/claimclr.rs b/pac/atsamc20g/src/mtb/claimclr.rs new file mode 100644 index 000000000000..7d0fa5d487b2 --- /dev/null +++ b/pac/atsamc20g/src/mtb/claimclr.rs @@ -0,0 +1,64 @@ +#[doc = "Register `CLAIMCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CLAIMCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MTB Claim Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [claimclr](index.html) module"] +pub struct CLAIMCLR_SPEC; +impl crate::RegisterSpec for CLAIMCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [claimclr::R](R) reader structure"] +impl crate::Readable for CLAIMCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [claimclr::W](W) writer structure"] +impl crate::Writable for CLAIMCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CLAIMCLR to value 0"] +impl crate::Resettable for CLAIMCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/mtb/claimset.rs b/pac/atsamc20g/src/mtb/claimset.rs new file mode 100644 index 000000000000..d5e8ffaa4846 --- /dev/null +++ b/pac/atsamc20g/src/mtb/claimset.rs @@ -0,0 +1,64 @@ +#[doc = "Register `CLAIMSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CLAIMSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MTB Claim Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [claimset](index.html) module"] +pub struct CLAIMSET_SPEC; +impl crate::RegisterSpec for CLAIMSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [claimset::R](R) reader structure"] +impl crate::Readable for CLAIMSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [claimset::W](W) writer structure"] +impl crate::Writable for CLAIMSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CLAIMSET to value 0"] +impl crate::Resettable for CLAIMSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/mtb/devarch.rs b/pac/atsamc20g/src/mtb/devarch.rs new file mode 100644 index 000000000000..b79480753d5e --- /dev/null +++ b/pac/atsamc20g/src/mtb/devarch.rs @@ -0,0 +1,31 @@ +#[doc = "Register `DEVARCH` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "MTB Device Architecture\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [devarch](index.html) module"] +pub struct DEVARCH_SPEC; +impl crate::RegisterSpec for DEVARCH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [devarch::R](R) reader structure"] +impl crate::Readable for DEVARCH_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DEVARCH to value 0"] +impl crate::Resettable for DEVARCH_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/mtb/devid.rs b/pac/atsamc20g/src/mtb/devid.rs new file mode 100644 index 000000000000..21c15d952032 --- /dev/null +++ b/pac/atsamc20g/src/mtb/devid.rs @@ -0,0 +1,31 @@ +#[doc = "Register `DEVID` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "MTB Device Configuration\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [devid](index.html) module"] +pub struct DEVID_SPEC; +impl crate::RegisterSpec for DEVID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [devid::R](R) reader structure"] +impl crate::Readable for DEVID_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DEVID to value 0"] +impl crate::Resettable for DEVID_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/mtb/devtype.rs b/pac/atsamc20g/src/mtb/devtype.rs new file mode 100644 index 000000000000..c00d66b98a2f --- /dev/null +++ b/pac/atsamc20g/src/mtb/devtype.rs @@ -0,0 +1,31 @@ +#[doc = "Register `DEVTYPE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "MTB Device Type\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [devtype](index.html) module"] +pub struct DEVTYPE_SPEC; +impl crate::RegisterSpec for DEVTYPE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [devtype::R](R) reader structure"] +impl crate::Readable for DEVTYPE_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DEVTYPE to value 0"] +impl crate::Resettable for DEVTYPE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/mtb/flow.rs b/pac/atsamc20g/src/mtb/flow.rs new file mode 100644 index 000000000000..1b94efdb89b8 --- /dev/null +++ b/pac/atsamc20g/src/mtb/flow.rs @@ -0,0 +1,197 @@ +#[doc = "Register `FLOW` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FLOW` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `AUTOSTOP` reader - Auto Stop Tracing"] +pub struct AUTOSTOP_R(crate::FieldReader); +impl AUTOSTOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AUTOSTOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AUTOSTOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AUTOSTOP` writer - Auto Stop Tracing"] +pub struct AUTOSTOP_W<'a> { + w: &'a mut W, +} +impl<'a> AUTOSTOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `AUTOHALT` reader - Auto Halt Request"] +pub struct AUTOHALT_R(crate::FieldReader); +impl AUTOHALT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AUTOHALT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AUTOHALT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AUTOHALT` writer - Auto Halt Request"] +pub struct AUTOHALT_W<'a> { + w: &'a mut W, +} +impl<'a> AUTOHALT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WATERMARK` reader - Watermark value"] +pub struct WATERMARK_R(crate::FieldReader); +impl WATERMARK_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + WATERMARK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WATERMARK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WATERMARK` writer - Watermark value"] +pub struct WATERMARK_W<'a> { + w: &'a mut W, +} +impl<'a> WATERMARK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1fff_ffff << 3)) | ((value as u32 & 0x1fff_ffff) << 3); + self.w + } +} +impl R { + #[doc = "Bit 0 - Auto Stop Tracing"] + #[inline(always)] + pub fn autostop(&self) -> AUTOSTOP_R { + AUTOSTOP_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Auto Halt Request"] + #[inline(always)] + pub fn autohalt(&self) -> AUTOHALT_R { + AUTOHALT_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 3:31 - Watermark value"] + #[inline(always)] + pub fn watermark(&self) -> WATERMARK_R { + WATERMARK_R::new(((self.bits >> 3) & 0x1fff_ffff) as u32) + } +} +impl W { + #[doc = "Bit 0 - Auto Stop Tracing"] + #[inline(always)] + pub fn autostop(&mut self) -> AUTOSTOP_W { + AUTOSTOP_W { w: self } + } + #[doc = "Bit 1 - Auto Halt Request"] + #[inline(always)] + pub fn autohalt(&mut self) -> AUTOHALT_W { + AUTOHALT_W { w: self } + } + #[doc = "Bits 3:31 - Watermark value"] + #[inline(always)] + pub fn watermark(&mut self) -> WATERMARK_W { + WATERMARK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MTB Flow\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [flow](index.html) module"] +pub struct FLOW_SPEC; +impl crate::RegisterSpec for FLOW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [flow::R](R) reader structure"] +impl crate::Readable for FLOW_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [flow::W](W) writer structure"] +impl crate::Writable for FLOW_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets FLOW to value 0"] +impl crate::Resettable for FLOW_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/mtb/itctrl.rs b/pac/atsamc20g/src/mtb/itctrl.rs new file mode 100644 index 000000000000..a48364e0b062 --- /dev/null +++ b/pac/atsamc20g/src/mtb/itctrl.rs @@ -0,0 +1,64 @@ +#[doc = "Register `ITCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ITCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MTB Integration Mode Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [itctrl](index.html) module"] +pub struct ITCTRL_SPEC; +impl crate::RegisterSpec for ITCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [itctrl::R](R) reader structure"] +impl crate::Readable for ITCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [itctrl::W](W) writer structure"] +impl crate::Writable for ITCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ITCTRL to value 0"] +impl crate::Resettable for ITCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/mtb/lockaccess.rs b/pac/atsamc20g/src/mtb/lockaccess.rs new file mode 100644 index 000000000000..0400690beade --- /dev/null +++ b/pac/atsamc20g/src/mtb/lockaccess.rs @@ -0,0 +1,64 @@ +#[doc = "Register `LOCKACCESS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `LOCKACCESS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MTB Lock Access\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lockaccess](index.html) module"] +pub struct LOCKACCESS_SPEC; +impl crate::RegisterSpec for LOCKACCESS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [lockaccess::R](R) reader structure"] +impl crate::Readable for LOCKACCESS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [lockaccess::W](W) writer structure"] +impl crate::Writable for LOCKACCESS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets LOCKACCESS to value 0"] +impl crate::Resettable for LOCKACCESS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/mtb/lockstatus.rs b/pac/atsamc20g/src/mtb/lockstatus.rs new file mode 100644 index 000000000000..0c68410c6944 --- /dev/null +++ b/pac/atsamc20g/src/mtb/lockstatus.rs @@ -0,0 +1,31 @@ +#[doc = "Register `LOCKSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "MTB Lock Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lockstatus](index.html) module"] +pub struct LOCKSTATUS_SPEC; +impl crate::RegisterSpec for LOCKSTATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [lockstatus::R](R) reader structure"] +impl crate::Readable for LOCKSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets LOCKSTATUS to value 0"] +impl crate::Resettable for LOCKSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/mtb/master.rs b/pac/atsamc20g/src/mtb/master.rs new file mode 100644 index 000000000000..0190ca1ce909 --- /dev/null +++ b/pac/atsamc20g/src/mtb/master.rs @@ -0,0 +1,385 @@ +#[doc = "Register `MASTER` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MASTER` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MASK` reader - Maximum Value of the Trace Buffer in SRAM"] +pub struct MASK_R(crate::FieldReader); +impl MASK_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MASK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MASK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MASK` writer - Maximum Value of the Trace Buffer in SRAM"] +pub struct MASK_W<'a> { + w: &'a mut W, +} +impl<'a> MASK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f); + self.w + } +} +#[doc = "Field `TSTARTEN` reader - Trace Start Input Enable"] +pub struct TSTARTEN_R(crate::FieldReader); +impl TSTARTEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSTARTEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSTARTEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSTARTEN` writer - Trace Start Input Enable"] +pub struct TSTARTEN_W<'a> { + w: &'a mut W, +} +impl<'a> TSTARTEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `TSTOPEN` reader - Trace Stop Input Enable"] +pub struct TSTOPEN_R(crate::FieldReader); +impl TSTOPEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSTOPEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSTOPEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSTOPEN` writer - Trace Stop Input Enable"] +pub struct TSTOPEN_W<'a> { + w: &'a mut W, +} +impl<'a> TSTOPEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `SFRWPRIV` reader - Special Function Register Write Privilege"] +pub struct SFRWPRIV_R(crate::FieldReader); +impl SFRWPRIV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SFRWPRIV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SFRWPRIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SFRWPRIV` writer - Special Function Register Write Privilege"] +pub struct SFRWPRIV_W<'a> { + w: &'a mut W, +} +impl<'a> SFRWPRIV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `RAMPRIV` reader - SRAM Privilege"] +pub struct RAMPRIV_R(crate::FieldReader); +impl RAMPRIV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RAMPRIV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RAMPRIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RAMPRIV` writer - SRAM Privilege"] +pub struct RAMPRIV_W<'a> { + w: &'a mut W, +} +impl<'a> RAMPRIV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `HALTREQ` reader - Halt Request"] +pub struct HALTREQ_R(crate::FieldReader); +impl HALTREQ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HALTREQ_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HALTREQ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HALTREQ` writer - Halt Request"] +pub struct HALTREQ_W<'a> { + w: &'a mut W, +} +impl<'a> HALTREQ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `EN` reader - Main Trace Enable"] +pub struct EN_R(crate::FieldReader); +impl EN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EN` writer - Main Trace Enable"] +pub struct EN_W<'a> { + w: &'a mut W, +} +impl<'a> EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Maximum Value of the Trace Buffer in SRAM"] + #[inline(always)] + pub fn mask(&self) -> MASK_R { + MASK_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bit 5 - Trace Start Input Enable"] + #[inline(always)] + pub fn tstarten(&self) -> TSTARTEN_R { + TSTARTEN_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Trace Stop Input Enable"] + #[inline(always)] + pub fn tstopen(&self) -> TSTOPEN_R { + TSTOPEN_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Special Function Register Write Privilege"] + #[inline(always)] + pub fn sfrwpriv(&self) -> SFRWPRIV_R { + SFRWPRIV_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - SRAM Privilege"] + #[inline(always)] + pub fn rampriv(&self) -> RAMPRIV_R { + RAMPRIV_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Halt Request"] + #[inline(always)] + pub fn haltreq(&self) -> HALTREQ_R { + HALTREQ_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 31 - Main Trace Enable"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Maximum Value of the Trace Buffer in SRAM"] + #[inline(always)] + pub fn mask(&mut self) -> MASK_W { + MASK_W { w: self } + } + #[doc = "Bit 5 - Trace Start Input Enable"] + #[inline(always)] + pub fn tstarten(&mut self) -> TSTARTEN_W { + TSTARTEN_W { w: self } + } + #[doc = "Bit 6 - Trace Stop Input Enable"] + #[inline(always)] + pub fn tstopen(&mut self) -> TSTOPEN_W { + TSTOPEN_W { w: self } + } + #[doc = "Bit 7 - Special Function Register Write Privilege"] + #[inline(always)] + pub fn sfrwpriv(&mut self) -> SFRWPRIV_W { + SFRWPRIV_W { w: self } + } + #[doc = "Bit 8 - SRAM Privilege"] + #[inline(always)] + pub fn rampriv(&mut self) -> RAMPRIV_W { + RAMPRIV_W { w: self } + } + #[doc = "Bit 9 - Halt Request"] + #[inline(always)] + pub fn haltreq(&mut self) -> HALTREQ_W { + HALTREQ_W { w: self } + } + #[doc = "Bit 31 - Main Trace Enable"] + #[inline(always)] + pub fn en(&mut self) -> EN_W { + EN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MTB Master\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [master](index.html) module"] +pub struct MASTER_SPEC; +impl crate::RegisterSpec for MASTER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [master::R](R) reader structure"] +impl crate::Readable for MASTER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [master::W](W) writer structure"] +impl crate::Writable for MASTER_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets MASTER to value 0"] +impl crate::Resettable for MASTER_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/mtb/pid0.rs b/pac/atsamc20g/src/mtb/pid0.rs new file mode 100644 index 000000000000..0a7183189fe5 --- /dev/null +++ b/pac/atsamc20g/src/mtb/pid0.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid0](index.html) module"] +pub struct PID0_SPEC; +impl crate::RegisterSpec for PID0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid0::R](R) reader structure"] +impl crate::Readable for PID0_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID0 to value 0"] +impl crate::Resettable for PID0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/mtb/pid1.rs b/pac/atsamc20g/src/mtb/pid1.rs new file mode 100644 index 000000000000..7d6381917f5d --- /dev/null +++ b/pac/atsamc20g/src/mtb/pid1.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid1](index.html) module"] +pub struct PID1_SPEC; +impl crate::RegisterSpec for PID1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid1::R](R) reader structure"] +impl crate::Readable for PID1_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID1 to value 0"] +impl crate::Resettable for PID1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/mtb/pid2.rs b/pac/atsamc20g/src/mtb/pid2.rs new file mode 100644 index 000000000000..74c230346b4c --- /dev/null +++ b/pac/atsamc20g/src/mtb/pid2.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 2\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid2](index.html) module"] +pub struct PID2_SPEC; +impl crate::RegisterSpec for PID2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid2::R](R) reader structure"] +impl crate::Readable for PID2_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID2 to value 0"] +impl crate::Resettable for PID2_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/mtb/pid3.rs b/pac/atsamc20g/src/mtb/pid3.rs new file mode 100644 index 000000000000..e9e922aa2f21 --- /dev/null +++ b/pac/atsamc20g/src/mtb/pid3.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 3\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid3](index.html) module"] +pub struct PID3_SPEC; +impl crate::RegisterSpec for PID3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid3::R](R) reader structure"] +impl crate::Readable for PID3_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID3 to value 0"] +impl crate::Resettable for PID3_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/mtb/pid4.rs b/pac/atsamc20g/src/mtb/pid4.rs new file mode 100644 index 000000000000..89074d3c2692 --- /dev/null +++ b/pac/atsamc20g/src/mtb/pid4.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID4` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 4\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid4](index.html) module"] +pub struct PID4_SPEC; +impl crate::RegisterSpec for PID4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid4::R](R) reader structure"] +impl crate::Readable for PID4_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID4 to value 0"] +impl crate::Resettable for PID4_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/mtb/pid5.rs b/pac/atsamc20g/src/mtb/pid5.rs new file mode 100644 index 000000000000..d343d4800b95 --- /dev/null +++ b/pac/atsamc20g/src/mtb/pid5.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID5` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 5\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid5](index.html) module"] +pub struct PID5_SPEC; +impl crate::RegisterSpec for PID5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid5::R](R) reader structure"] +impl crate::Readable for PID5_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID5 to value 0"] +impl crate::Resettable for PID5_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/mtb/pid6.rs b/pac/atsamc20g/src/mtb/pid6.rs new file mode 100644 index 000000000000..55cc2b8b5861 --- /dev/null +++ b/pac/atsamc20g/src/mtb/pid6.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID6` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 6\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid6](index.html) module"] +pub struct PID6_SPEC; +impl crate::RegisterSpec for PID6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid6::R](R) reader structure"] +impl crate::Readable for PID6_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID6 to value 0"] +impl crate::Resettable for PID6_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/mtb/pid7.rs b/pac/atsamc20g/src/mtb/pid7.rs new file mode 100644 index 000000000000..77664d4f2f95 --- /dev/null +++ b/pac/atsamc20g/src/mtb/pid7.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID7` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 7\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid7](index.html) module"] +pub struct PID7_SPEC; +impl crate::RegisterSpec for PID7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid7::R](R) reader structure"] +impl crate::Readable for PID7_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID7 to value 0"] +impl crate::Resettable for PID7_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/mtb/position.rs b/pac/atsamc20g/src/mtb/position.rs new file mode 100644 index 000000000000..4bab0425b142 --- /dev/null +++ b/pac/atsamc20g/src/mtb/position.rs @@ -0,0 +1,150 @@ +#[doc = "Register `POSITION` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `POSITION` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WRAP` reader - Pointer Value Wraps"] +pub struct WRAP_R(crate::FieldReader); +impl WRAP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WRAP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WRAP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WRAP` writer - Pointer Value Wraps"] +pub struct WRAP_W<'a> { + w: &'a mut W, +} +impl<'a> WRAP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `POINTER` reader - Trace Packet Location Pointer"] +pub struct POINTER_R(crate::FieldReader); +impl POINTER_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + POINTER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for POINTER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `POINTER` writer - Trace Packet Location Pointer"] +pub struct POINTER_W<'a> { + w: &'a mut W, +} +impl<'a> POINTER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1fff_ffff << 3)) | ((value as u32 & 0x1fff_ffff) << 3); + self.w + } +} +impl R { + #[doc = "Bit 2 - Pointer Value Wraps"] + #[inline(always)] + pub fn wrap(&self) -> WRAP_R { + WRAP_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 3:31 - Trace Packet Location Pointer"] + #[inline(always)] + pub fn pointer(&self) -> POINTER_R { + POINTER_R::new(((self.bits >> 3) & 0x1fff_ffff) as u32) + } +} +impl W { + #[doc = "Bit 2 - Pointer Value Wraps"] + #[inline(always)] + pub fn wrap(&mut self) -> WRAP_W { + WRAP_W { w: self } + } + #[doc = "Bits 3:31 - Trace Packet Location Pointer"] + #[inline(always)] + pub fn pointer(&mut self) -> POINTER_W { + POINTER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MTB Position\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [position](index.html) module"] +pub struct POSITION_SPEC; +impl crate::RegisterSpec for POSITION_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [position::R](R) reader structure"] +impl crate::Readable for POSITION_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [position::W](W) writer structure"] +impl crate::Writable for POSITION_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets POSITION to value 0"] +impl crate::Resettable for POSITION_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/nvmctrl.rs b/pac/atsamc20g/src/nvmctrl.rs new file mode 100644 index 000000000000..2c017caaef9c --- /dev/null +++ b/pac/atsamc20g/src/nvmctrl.rs @@ -0,0 +1,76 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + _reserved1: [u8; 0x02], + #[doc = "0x04 - Control B"] + pub ctrlb: crate::Reg, + #[doc = "0x08 - NVM Parameter"] + pub param: crate::Reg, + #[doc = "0x0c - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + _reserved4: [u8; 0x03], + #[doc = "0x10 - Interrupt Enable Set"] + pub intenset: crate::Reg, + _reserved5: [u8; 0x03], + #[doc = "0x14 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved6: [u8; 0x03], + #[doc = "0x18 - Status"] + pub status: crate::Reg, + _reserved7: [u8; 0x02], + #[doc = "0x1c - Address"] + pub addr: crate::Reg, + #[doc = "0x20 - Lock Section"] + pub lock: crate::Reg, + _reserved9: [u8; 0x06], + #[doc = "0x28 - Page Buffer Load Data 0"] + pub pbldata0: crate::Reg, + #[doc = "0x2c - Page Buffer Load Data 1"] + pub pbldata1: crate::Reg, +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "Control B"] +pub mod ctrlb; +#[doc = "PARAM register accessor: an alias for `Reg`"] +pub type PARAM = crate::Reg; +#[doc = "NVM Parameter"] +pub mod param; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "ADDR register accessor: an alias for `Reg`"] +pub type ADDR = crate::Reg; +#[doc = "Address"] +pub mod addr; +#[doc = "LOCK register accessor: an alias for `Reg`"] +pub type LOCK = crate::Reg; +#[doc = "Lock Section"] +pub mod lock; +#[doc = "PBLDATA0 register accessor: an alias for `Reg`"] +pub type PBLDATA0 = crate::Reg; +#[doc = "Page Buffer Load Data 0"] +pub mod pbldata0; +#[doc = "PBLDATA1 register accessor: an alias for `Reg`"] +pub type PBLDATA1 = crate::Reg; +#[doc = "Page Buffer Load Data 1"] +pub mod pbldata1; diff --git a/pac/atsamc20g/src/nvmctrl/addr.rs b/pac/atsamc20g/src/nvmctrl/addr.rs new file mode 100644 index 000000000000..74ed27736dac --- /dev/null +++ b/pac/atsamc20g/src/nvmctrl/addr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `ADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ADDR` reader - NVM Address"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - NVM Address"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x003f_ffff) | (value as u32 & 0x003f_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:21 - NVM Address"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new((self.bits & 0x003f_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:21 - NVM Address"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [addr](index.html) module"] +pub struct ADDR_SPEC; +impl crate::RegisterSpec for ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [addr::R](R) reader structure"] +impl crate::Readable for ADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [addr::W](W) writer structure"] +impl crate::Writable for ADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ADDR to value 0"] +impl crate::Resettable for ADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/nvmctrl/ctrla.rs b/pac/atsamc20g/src/nvmctrl/ctrla.rs new file mode 100644 index 000000000000..89f175771e4d --- /dev/null +++ b/pac/atsamc20g/src/nvmctrl/ctrla.rs @@ -0,0 +1,394 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "2: Erase Row - Erases the row addressed by the ADDR register."] + ER = 2, + #[doc = "4: Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register."] + WP = 4, + #[doc = "5: Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row."] + EAR = 5, + #[doc = "6: Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row."] + WAP = 6, + #[doc = "10: Security Flow Command"] + SF = 10, + #[doc = "15: Write lockbits"] + WL = 15, + #[doc = "26: RWW EEPROM area Erase Row - Erases the row addressed by the ADDR register."] + RWWEEER = 26, + #[doc = "28: RWW EEPROM Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register."] + RWWEEWP = 28, + #[doc = "64: Lock Region - Locks the region containing the address location in the ADDR register."] + LR = 64, + #[doc = "65: Unlock Region - Unlocks the region containing the address location in the ADDR register."] + UR = 65, + #[doc = "66: Sets the power reduction mode."] + SPRM = 66, + #[doc = "67: Clears the power reduction mode."] + CPRM = 67, + #[doc = "68: Page Buffer Clear - Clears the page buffer."] + PBC = 68, + #[doc = "69: Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row."] + SSB = 69, + #[doc = "70: Invalidate all cache lines."] + INVALL = 70, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 2 => Some(CMD_A::ER), + 4 => Some(CMD_A::WP), + 5 => Some(CMD_A::EAR), + 6 => Some(CMD_A::WAP), + 10 => Some(CMD_A::SF), + 15 => Some(CMD_A::WL), + 26 => Some(CMD_A::RWWEEER), + 28 => Some(CMD_A::RWWEEWP), + 64 => Some(CMD_A::LR), + 65 => Some(CMD_A::UR), + 66 => Some(CMD_A::SPRM), + 67 => Some(CMD_A::CPRM), + 68 => Some(CMD_A::PBC), + 69 => Some(CMD_A::SSB), + 70 => Some(CMD_A::INVALL), + _ => None, + } + } + #[doc = "Checks if the value of the field is `ER`"] + #[inline(always)] + pub fn is_er(&self) -> bool { + **self == CMD_A::ER + } + #[doc = "Checks if the value of the field is `WP`"] + #[inline(always)] + pub fn is_wp(&self) -> bool { + **self == CMD_A::WP + } + #[doc = "Checks if the value of the field is `EAR`"] + #[inline(always)] + pub fn is_ear(&self) -> bool { + **self == CMD_A::EAR + } + #[doc = "Checks if the value of the field is `WAP`"] + #[inline(always)] + pub fn is_wap(&self) -> bool { + **self == CMD_A::WAP + } + #[doc = "Checks if the value of the field is `SF`"] + #[inline(always)] + pub fn is_sf(&self) -> bool { + **self == CMD_A::SF + } + #[doc = "Checks if the value of the field is `WL`"] + #[inline(always)] + pub fn is_wl(&self) -> bool { + **self == CMD_A::WL + } + #[doc = "Checks if the value of the field is `RWWEEER`"] + #[inline(always)] + pub fn is_rwweeer(&self) -> bool { + **self == CMD_A::RWWEEER + } + #[doc = "Checks if the value of the field is `RWWEEWP`"] + #[inline(always)] + pub fn is_rwweewp(&self) -> bool { + **self == CMD_A::RWWEEWP + } + #[doc = "Checks if the value of the field is `LR`"] + #[inline(always)] + pub fn is_lr(&self) -> bool { + **self == CMD_A::LR + } + #[doc = "Checks if the value of the field is `UR`"] + #[inline(always)] + pub fn is_ur(&self) -> bool { + **self == CMD_A::UR + } + #[doc = "Checks if the value of the field is `SPRM`"] + #[inline(always)] + pub fn is_sprm(&self) -> bool { + **self == CMD_A::SPRM + } + #[doc = "Checks if the value of the field is `CPRM`"] + #[inline(always)] + pub fn is_cprm(&self) -> bool { + **self == CMD_A::CPRM + } + #[doc = "Checks if the value of the field is `PBC`"] + #[inline(always)] + pub fn is_pbc(&self) -> bool { + **self == CMD_A::PBC + } + #[doc = "Checks if the value of the field is `SSB`"] + #[inline(always)] + pub fn is_ssb(&self) -> bool { + **self == CMD_A::SSB + } + #[doc = "Checks if the value of the field is `INVALL`"] + #[inline(always)] + pub fn is_invall(&self) -> bool { + **self == CMD_A::INVALL + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Erase Row - Erases the row addressed by the ADDR register."] + #[inline(always)] + pub fn er(self) -> &'a mut W { + self.variant(CMD_A::ER) + } + #[doc = "Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register."] + #[inline(always)] + pub fn wp(self) -> &'a mut W { + self.variant(CMD_A::WP) + } + #[doc = "Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row."] + #[inline(always)] + pub fn ear(self) -> &'a mut W { + self.variant(CMD_A::EAR) + } + #[doc = "Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row."] + #[inline(always)] + pub fn wap(self) -> &'a mut W { + self.variant(CMD_A::WAP) + } + #[doc = "Security Flow Command"] + #[inline(always)] + pub fn sf(self) -> &'a mut W { + self.variant(CMD_A::SF) + } + #[doc = "Write lockbits"] + #[inline(always)] + pub fn wl(self) -> &'a mut W { + self.variant(CMD_A::WL) + } + #[doc = "RWW EEPROM area Erase Row - Erases the row addressed by the ADDR register."] + #[inline(always)] + pub fn rwweeer(self) -> &'a mut W { + self.variant(CMD_A::RWWEEER) + } + #[doc = "RWW EEPROM Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register."] + #[inline(always)] + pub fn rwweewp(self) -> &'a mut W { + self.variant(CMD_A::RWWEEWP) + } + #[doc = "Lock Region - Locks the region containing the address location in the ADDR register."] + #[inline(always)] + pub fn lr(self) -> &'a mut W { + self.variant(CMD_A::LR) + } + #[doc = "Unlock Region - Unlocks the region containing the address location in the ADDR register."] + #[inline(always)] + pub fn ur(self) -> &'a mut W { + self.variant(CMD_A::UR) + } + #[doc = "Sets the power reduction mode."] + #[inline(always)] + pub fn sprm(self) -> &'a mut W { + self.variant(CMD_A::SPRM) + } + #[doc = "Clears the power reduction mode."] + #[inline(always)] + pub fn cprm(self) -> &'a mut W { + self.variant(CMD_A::CPRM) + } + #[doc = "Page Buffer Clear - Clears the page buffer."] + #[inline(always)] + pub fn pbc(self) -> &'a mut W { + self.variant(CMD_A::PBC) + } + #[doc = "Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row."] + #[inline(always)] + pub fn ssb(self) -> &'a mut W { + self.variant(CMD_A::SSB) + } + #[doc = "Invalidate all cache lines."] + #[inline(always)] + pub fn invall(self) -> &'a mut W { + self.variant(CMD_A::INVALL) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x7f) | (value as u16 & 0x7f); + self.w + } +} +#[doc = "Command Execution\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMDEX_A { + #[doc = "165: Execution Key"] + KEY = 165, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMDEX_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMDEX` reader - Command Execution"] +pub struct CMDEX_R(crate::FieldReader); +impl CMDEX_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMDEX_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 165 => Some(CMDEX_A::KEY), + _ => None, + } + } + #[doc = "Checks if the value of the field is `KEY`"] + #[inline(always)] + pub fn is_key(&self) -> bool { + **self == CMDEX_A::KEY + } +} +impl core::ops::Deref for CMDEX_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMDEX` writer - Command Execution"] +pub struct CMDEX_W<'a> { + w: &'a mut W, +} +impl<'a> CMDEX_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMDEX_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Execution Key"] + #[inline(always)] + pub fn key(self) -> &'a mut W { + self.variant(CMDEX_A::KEY) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u16 & 0xff) << 8); + self.w + } +} +impl R { + #[doc = "Bits 0:6 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bits 8:15 - Command Execution"] + #[inline(always)] + pub fn cmdex(&self) -> CMDEX_R { + CMDEX_R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:6 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Bits 8:15 - Command Execution"] + #[inline(always)] + pub fn cmdex(&mut self) -> CMDEX_W { + CMDEX_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/nvmctrl/ctrlb.rs b/pac/atsamc20g/src/nvmctrl/ctrlb.rs new file mode 100644 index 000000000000..6162d0d4ade0 --- /dev/null +++ b/pac/atsamc20g/src/nvmctrl/ctrlb.rs @@ -0,0 +1,447 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "NVM Read Wait States\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum RWS_A { + #[doc = "0: Single Auto Wait State"] + SINGLE = 0, + #[doc = "1: Half Auto Wait State"] + HALF = 1, + #[doc = "2: Dual Auto Wait State"] + DUAL = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RWS_A) -> Self { + variant as _ + } +} +#[doc = "Field `RWS` reader - NVM Read Wait States"] +pub struct RWS_R(crate::FieldReader); +impl RWS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RWS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(RWS_A::SINGLE), + 1 => Some(RWS_A::HALF), + 2 => Some(RWS_A::DUAL), + _ => None, + } + } + #[doc = "Checks if the value of the field is `SINGLE`"] + #[inline(always)] + pub fn is_single(&self) -> bool { + **self == RWS_A::SINGLE + } + #[doc = "Checks if the value of the field is `HALF`"] + #[inline(always)] + pub fn is_half(&self) -> bool { + **self == RWS_A::HALF + } + #[doc = "Checks if the value of the field is `DUAL`"] + #[inline(always)] + pub fn is_dual(&self) -> bool { + **self == RWS_A::DUAL + } +} +impl core::ops::Deref for RWS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RWS` writer - NVM Read Wait States"] +pub struct RWS_W<'a> { + w: &'a mut W, +} +impl<'a> RWS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RWS_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Single Auto Wait State"] + #[inline(always)] + pub fn single(self) -> &'a mut W { + self.variant(RWS_A::SINGLE) + } + #[doc = "Half Auto Wait State"] + #[inline(always)] + pub fn half(self) -> &'a mut W { + self.variant(RWS_A::HALF) + } + #[doc = "Dual Auto Wait State"] + #[inline(always)] + pub fn dual(self) -> &'a mut W { + self.variant(RWS_A::DUAL) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 1)) | ((value as u32 & 0x0f) << 1); + self.w + } +} +#[doc = "Field `MANW` reader - Manual Write"] +pub struct MANW_R(crate::FieldReader); +impl MANW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MANW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MANW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MANW` writer - Manual Write"] +pub struct MANW_W<'a> { + w: &'a mut W, +} +impl<'a> MANW_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Power Reduction Mode during Sleep\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SLEEPPRM_A { + #[doc = "0: NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access."] + WAKEONACCESS = 0, + #[doc = "1: NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep."] + WAKEUPINSTANT = 1, + #[doc = "3: Auto power reduction disabled."] + DISABLED = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SLEEPPRM_A) -> Self { + variant as _ + } +} +#[doc = "Field `SLEEPPRM` reader - Power Reduction Mode during Sleep"] +pub struct SLEEPPRM_R(crate::FieldReader); +impl SLEEPPRM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SLEEPPRM_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SLEEPPRM_A::WAKEONACCESS), + 1 => Some(SLEEPPRM_A::WAKEUPINSTANT), + 3 => Some(SLEEPPRM_A::DISABLED), + _ => None, + } + } + #[doc = "Checks if the value of the field is `WAKEONACCESS`"] + #[inline(always)] + pub fn is_wakeonaccess(&self) -> bool { + **self == SLEEPPRM_A::WAKEONACCESS + } + #[doc = "Checks if the value of the field is `WAKEUPINSTANT`"] + #[inline(always)] + pub fn is_wakeupinstant(&self) -> bool { + **self == SLEEPPRM_A::WAKEUPINSTANT + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + **self == SLEEPPRM_A::DISABLED + } +} +impl core::ops::Deref for SLEEPPRM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLEEPPRM` writer - Power Reduction Mode during Sleep"] +pub struct SLEEPPRM_W<'a> { + w: &'a mut W, +} +impl<'a> SLEEPPRM_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SLEEPPRM_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access."] + #[inline(always)] + pub fn wakeonaccess(self) -> &'a mut W { + self.variant(SLEEPPRM_A::WAKEONACCESS) + } + #[doc = "NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep."] + #[inline(always)] + pub fn wakeupinstant(self) -> &'a mut W { + self.variant(SLEEPPRM_A::WAKEUPINSTANT) + } + #[doc = "Auto power reduction disabled."] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(SLEEPPRM_A::DISABLED) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 8)) | ((value as u32 & 0x03) << 8); + self.w + } +} +#[doc = "NVMCTRL Read Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum READMODE_A { + #[doc = "0: The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance."] + NO_MISS_PENALTY = 0, + #[doc = "1: Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time."] + LOW_POWER = 1, + #[doc = "2: The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings."] + DETERMINISTIC = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: READMODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `READMODE` reader - NVMCTRL Read Mode"] +pub struct READMODE_R(crate::FieldReader); +impl READMODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + READMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(READMODE_A::NO_MISS_PENALTY), + 1 => Some(READMODE_A::LOW_POWER), + 2 => Some(READMODE_A::DETERMINISTIC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NO_MISS_PENALTY`"] + #[inline(always)] + pub fn is_no_miss_penalty(&self) -> bool { + **self == READMODE_A::NO_MISS_PENALTY + } + #[doc = "Checks if the value of the field is `LOW_POWER`"] + #[inline(always)] + pub fn is_low_power(&self) -> bool { + **self == READMODE_A::LOW_POWER + } + #[doc = "Checks if the value of the field is `DETERMINISTIC`"] + #[inline(always)] + pub fn is_deterministic(&self) -> bool { + **self == READMODE_A::DETERMINISTIC + } +} +impl core::ops::Deref for READMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `READMODE` writer - NVMCTRL Read Mode"] +pub struct READMODE_W<'a> { + w: &'a mut W, +} +impl<'a> READMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: READMODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance."] + #[inline(always)] + pub fn no_miss_penalty(self) -> &'a mut W { + self.variant(READMODE_A::NO_MISS_PENALTY) + } + #[doc = "Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time."] + #[inline(always)] + pub fn low_power(self) -> &'a mut W { + self.variant(READMODE_A::LOW_POWER) + } + #[doc = "The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings."] + #[inline(always)] + pub fn deterministic(self) -> &'a mut W { + self.variant(READMODE_A::DETERMINISTIC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Field `CACHEDIS` reader - Cache Disable"] +pub struct CACHEDIS_R(crate::FieldReader); +impl CACHEDIS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CACHEDIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CACHEDIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CACHEDIS` writer - Cache Disable"] +pub struct CACHEDIS_W<'a> { + w: &'a mut W, +} +impl<'a> CACHEDIS_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 18)) | ((value as u32 & 0x03) << 18); + self.w + } +} +impl R { + #[doc = "Bits 1:4 - NVM Read Wait States"] + #[inline(always)] + pub fn rws(&self) -> RWS_R { + RWS_R::new(((self.bits >> 1) & 0x0f) as u8) + } + #[doc = "Bit 7 - Manual Write"] + #[inline(always)] + pub fn manw(&self) -> MANW_R { + MANW_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:9 - Power Reduction Mode during Sleep"] + #[inline(always)] + pub fn sleepprm(&self) -> SLEEPPRM_R { + SLEEPPRM_R::new(((self.bits >> 8) & 0x03) as u8) + } + #[doc = "Bits 16:17 - NVMCTRL Read Mode"] + #[inline(always)] + pub fn readmode(&self) -> READMODE_R { + READMODE_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bits 18:19 - Cache Disable"] + #[inline(always)] + pub fn cachedis(&self) -> CACHEDIS_R { + CACHEDIS_R::new(((self.bits >> 18) & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 1:4 - NVM Read Wait States"] + #[inline(always)] + pub fn rws(&mut self) -> RWS_W { + RWS_W { w: self } + } + #[doc = "Bit 7 - Manual Write"] + #[inline(always)] + pub fn manw(&mut self) -> MANW_W { + MANW_W { w: self } + } + #[doc = "Bits 8:9 - Power Reduction Mode during Sleep"] + #[inline(always)] + pub fn sleepprm(&mut self) -> SLEEPPRM_W { + SLEEPPRM_W { w: self } + } + #[doc = "Bits 16:17 - NVMCTRL Read Mode"] + #[inline(always)] + pub fn readmode(&mut self) -> READMODE_W { + READMODE_W { w: self } + } + #[doc = "Bits 18:19 - Cache Disable"] + #[inline(always)] + pub fn cachedis(&mut self) -> CACHEDIS_W { + CACHEDIS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0x80"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x80 + } +} diff --git a/pac/atsamc20g/src/nvmctrl/intenclr.rs b/pac/atsamc20g/src/nvmctrl/intenclr.rs new file mode 100644 index 000000000000..6e7db4b52c9d --- /dev/null +++ b/pac/atsamc20g/src/nvmctrl/intenclr.rs @@ -0,0 +1,160 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `READY` reader - NVM Ready Interrupt Enable"] +pub struct READY_R(crate::FieldReader); +impl READY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + READY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for READY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `READY` writer - NVM Ready Interrupt Enable"] +pub struct READY_W<'a> { + w: &'a mut W, +} +impl<'a> READY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERROR` reader - Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - NVM Ready Interrupt Enable"] + #[inline(always)] + pub fn ready(&self) -> READY_R { + READY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - NVM Ready Interrupt Enable"] + #[inline(always)] + pub fn ready(&mut self) -> READY_W { + READY_W { w: self } + } + #[doc = "Bit 1 - Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/nvmctrl/intenset.rs b/pac/atsamc20g/src/nvmctrl/intenset.rs new file mode 100644 index 000000000000..ba8698e86c3e --- /dev/null +++ b/pac/atsamc20g/src/nvmctrl/intenset.rs @@ -0,0 +1,160 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `READY` reader - NVM Ready Interrupt Enable"] +pub struct READY_R(crate::FieldReader); +impl READY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + READY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for READY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `READY` writer - NVM Ready Interrupt Enable"] +pub struct READY_W<'a> { + w: &'a mut W, +} +impl<'a> READY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERROR` reader - Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - NVM Ready Interrupt Enable"] + #[inline(always)] + pub fn ready(&self) -> READY_R { + READY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - NVM Ready Interrupt Enable"] + #[inline(always)] + pub fn ready(&mut self) -> READY_W { + READY_W { w: self } + } + #[doc = "Bit 1 - Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/nvmctrl/intflag.rs b/pac/atsamc20g/src/nvmctrl/intflag.rs new file mode 100644 index 000000000000..1b30cdddf25d --- /dev/null +++ b/pac/atsamc20g/src/nvmctrl/intflag.rs @@ -0,0 +1,160 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `READY` reader - NVM Ready"] +pub struct READY_R(crate::FieldReader); +impl READY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + READY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for READY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `READY` writer - NVM Ready"] +pub struct READY_W<'a> { + w: &'a mut W, +} +impl<'a> READY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERROR` reader - Error"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Error"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - NVM Ready"] + #[inline(always)] + pub fn ready(&self) -> READY_R { + READY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Error"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - NVM Ready"] + #[inline(always)] + pub fn ready(&mut self) -> READY_W { + READY_W { w: self } + } + #[doc = "Bit 1 - Error"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/nvmctrl/lock.rs b/pac/atsamc20g/src/nvmctrl/lock.rs new file mode 100644 index 000000000000..dbcf37a8107f --- /dev/null +++ b/pac/atsamc20g/src/nvmctrl/lock.rs @@ -0,0 +1,103 @@ +#[doc = "Register `LOCK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `LOCK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `LOCK` reader - Region Lock Bits"] +pub struct LOCK_R(crate::FieldReader); +impl LOCK_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + LOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LOCK` writer - Region Lock Bits"] +pub struct LOCK_W<'a> { + w: &'a mut W, +} +impl<'a> LOCK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Region Lock Bits"] + #[inline(always)] + pub fn lock(&self) -> LOCK_R { + LOCK_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Region Lock Bits"] + #[inline(always)] + pub fn lock(&mut self) -> LOCK_W { + LOCK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Lock Section\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lock](index.html) module"] +pub struct LOCK_SPEC; +impl crate::RegisterSpec for LOCK_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [lock::R](R) reader structure"] +impl crate::Readable for LOCK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [lock::W](W) writer structure"] +impl crate::Writable for LOCK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets LOCK to value 0"] +impl crate::Resettable for LOCK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/nvmctrl/param.rs b/pac/atsamc20g/src/nvmctrl/param.rs new file mode 100644 index 000000000000..d9197cf16de4 --- /dev/null +++ b/pac/atsamc20g/src/nvmctrl/param.rs @@ -0,0 +1,304 @@ +#[doc = "Register `PARAM` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PARAM` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `NVMP` reader - NVM Pages"] +pub struct NVMP_R(crate::FieldReader); +impl NVMP_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + NVMP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NVMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NVMP` writer - NVM Pages"] +pub struct NVMP_W<'a> { + w: &'a mut W, +} +impl<'a> NVMP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +#[doc = "Page Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PSZ_A { + #[doc = "0: 8 bytes"] + _8 = 0, + #[doc = "1: 16 bytes"] + _16 = 1, + #[doc = "2: 32 bytes"] + _32 = 2, + #[doc = "3: 64 bytes"] + _64 = 3, + #[doc = "4: 128 bytes"] + _128 = 4, + #[doc = "5: 256 bytes"] + _256 = 5, + #[doc = "6: 512 bytes"] + _512 = 6, + #[doc = "7: 1024 bytes"] + _1024 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PSZ_A) -> Self { + variant as _ + } +} +#[doc = "Field `PSZ` reader - Page Size"] +pub struct PSZ_R(crate::FieldReader); +impl PSZ_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PSZ_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PSZ_A { + match self.bits { + 0 => PSZ_A::_8, + 1 => PSZ_A::_16, + 2 => PSZ_A::_32, + 3 => PSZ_A::_64, + 4 => PSZ_A::_128, + 5 => PSZ_A::_256, + 6 => PSZ_A::_512, + 7 => PSZ_A::_1024, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `_8`"] + #[inline(always)] + pub fn is_8(&self) -> bool { + **self == PSZ_A::_8 + } + #[doc = "Checks if the value of the field is `_16`"] + #[inline(always)] + pub fn is_16(&self) -> bool { + **self == PSZ_A::_16 + } + #[doc = "Checks if the value of the field is `_32`"] + #[inline(always)] + pub fn is_32(&self) -> bool { + **self == PSZ_A::_32 + } + #[doc = "Checks if the value of the field is `_64`"] + #[inline(always)] + pub fn is_64(&self) -> bool { + **self == PSZ_A::_64 + } + #[doc = "Checks if the value of the field is `_128`"] + #[inline(always)] + pub fn is_128(&self) -> bool { + **self == PSZ_A::_128 + } + #[doc = "Checks if the value of the field is `_256`"] + #[inline(always)] + pub fn is_256(&self) -> bool { + **self == PSZ_A::_256 + } + #[doc = "Checks if the value of the field is `_512`"] + #[inline(always)] + pub fn is_512(&self) -> bool { + **self == PSZ_A::_512 + } + #[doc = "Checks if the value of the field is `_1024`"] + #[inline(always)] + pub fn is_1024(&self) -> bool { + **self == PSZ_A::_1024 + } +} +impl core::ops::Deref for PSZ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PSZ` writer - Page Size"] +pub struct PSZ_W<'a> { + w: &'a mut W, +} +impl<'a> PSZ_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PSZ_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "8 bytes"] + #[inline(always)] + pub fn _8(self) -> &'a mut W { + self.variant(PSZ_A::_8) + } + #[doc = "16 bytes"] + #[inline(always)] + pub fn _16(self) -> &'a mut W { + self.variant(PSZ_A::_16) + } + #[doc = "32 bytes"] + #[inline(always)] + pub fn _32(self) -> &'a mut W { + self.variant(PSZ_A::_32) + } + #[doc = "64 bytes"] + #[inline(always)] + pub fn _64(self) -> &'a mut W { + self.variant(PSZ_A::_64) + } + #[doc = "128 bytes"] + #[inline(always)] + pub fn _128(self) -> &'a mut W { + self.variant(PSZ_A::_128) + } + #[doc = "256 bytes"] + #[inline(always)] + pub fn _256(self) -> &'a mut W { + self.variant(PSZ_A::_256) + } + #[doc = "512 bytes"] + #[inline(always)] + pub fn _512(self) -> &'a mut W { + self.variant(PSZ_A::_512) + } + #[doc = "1024 bytes"] + #[inline(always)] + pub fn _1024(self) -> &'a mut W { + self.variant(PSZ_A::_1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 16)) | ((value as u32 & 0x07) << 16); + self.w + } +} +#[doc = "Field `RWWEEP` reader - RWW EEPROM Pages"] +pub struct RWWEEP_R(crate::FieldReader); +impl RWWEEP_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + RWWEEP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RWWEEP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RWWEEP` writer - RWW EEPROM Pages"] +pub struct RWWEEP_W<'a> { + w: &'a mut W, +} +impl<'a> RWWEEP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0fff << 20)) | ((value as u32 & 0x0fff) << 20); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - NVM Pages"] + #[inline(always)] + pub fn nvmp(&self) -> NVMP_R { + NVMP_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:18 - Page Size"] + #[inline(always)] + pub fn psz(&self) -> PSZ_R { + PSZ_R::new(((self.bits >> 16) & 0x07) as u8) + } + #[doc = "Bits 20:31 - RWW EEPROM Pages"] + #[inline(always)] + pub fn rwweep(&self) -> RWWEEP_R { + RWWEEP_R::new(((self.bits >> 20) & 0x0fff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - NVM Pages"] + #[inline(always)] + pub fn nvmp(&mut self) -> NVMP_W { + NVMP_W { w: self } + } + #[doc = "Bits 16:18 - Page Size"] + #[inline(always)] + pub fn psz(&mut self) -> PSZ_W { + PSZ_W { w: self } + } + #[doc = "Bits 20:31 - RWW EEPROM Pages"] + #[inline(always)] + pub fn rwweep(&mut self) -> RWWEEP_W { + RWWEEP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "NVM Parameter\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [param](index.html) module"] +pub struct PARAM_SPEC; +impl crate::RegisterSpec for PARAM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [param::R](R) reader structure"] +impl crate::Readable for PARAM_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [param::W](W) writer structure"] +impl crate::Writable for PARAM_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PARAM to value 0"] +impl crate::Resettable for PARAM_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/nvmctrl/pbldata0.rs b/pac/atsamc20g/src/nvmctrl/pbldata0.rs new file mode 100644 index 000000000000..ff2effaf4d89 --- /dev/null +++ b/pac/atsamc20g/src/nvmctrl/pbldata0.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PBLDATA0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Page Buffer Load Data 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pbldata0](index.html) module"] +pub struct PBLDATA0_SPEC; +impl crate::RegisterSpec for PBLDATA0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pbldata0::R](R) reader structure"] +impl crate::Readable for PBLDATA0_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PBLDATA0 to value 0"] +impl crate::Resettable for PBLDATA0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/nvmctrl/pbldata1.rs b/pac/atsamc20g/src/nvmctrl/pbldata1.rs new file mode 100644 index 000000000000..9fc6404691c5 --- /dev/null +++ b/pac/atsamc20g/src/nvmctrl/pbldata1.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PBLDATA1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Page Buffer Load Data 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pbldata1](index.html) module"] +pub struct PBLDATA1_SPEC; +impl crate::RegisterSpec for PBLDATA1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pbldata1::R](R) reader structure"] +impl crate::Readable for PBLDATA1_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PBLDATA1 to value 0"] +impl crate::Resettable for PBLDATA1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/nvmctrl/status.rs b/pac/atsamc20g/src/nvmctrl/status.rs new file mode 100644 index 000000000000..ce849015560e --- /dev/null +++ b/pac/atsamc20g/src/nvmctrl/status.rs @@ -0,0 +1,348 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PRM` reader - Power Reduction Mode"] +pub struct PRM_R(crate::FieldReader); +impl PRM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PRM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PRM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRM` writer - Power Reduction Mode"] +pub struct PRM_W<'a> { + w: &'a mut W, +} +impl<'a> PRM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `LOAD` reader - NVM Page Buffer Active Loading"] +pub struct LOAD_R(crate::FieldReader); +impl LOAD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LOAD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOAD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LOAD` writer - NVM Page Buffer Active Loading"] +pub struct LOAD_W<'a> { + w: &'a mut W, +} +impl<'a> LOAD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PROGE` reader - Programming Error Status"] +pub struct PROGE_R(crate::FieldReader); +impl PROGE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PROGE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PROGE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PROGE` writer - Programming Error Status"] +pub struct PROGE_W<'a> { + w: &'a mut W, +} +impl<'a> PROGE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `LOCKE` reader - Lock Error Status"] +pub struct LOCKE_R(crate::FieldReader); +impl LOCKE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LOCKE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOCKE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LOCKE` writer - Lock Error Status"] +pub struct LOCKE_W<'a> { + w: &'a mut W, +} +impl<'a> LOCKE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `NVME` reader - NVM Error"] +pub struct NVME_R(crate::FieldReader); +impl NVME_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NVME_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NVME_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NVME` writer - NVM Error"] +pub struct NVME_W<'a> { + w: &'a mut W, +} +impl<'a> NVME_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `SB` reader - Security Bit Status"] +pub struct SB_R(crate::FieldReader); +impl SB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SB` writer - Security Bit Status"] +pub struct SB_W<'a> { + w: &'a mut W, +} +impl<'a> SB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +impl R { + #[doc = "Bit 0 - Power Reduction Mode"] + #[inline(always)] + pub fn prm(&self) -> PRM_R { + PRM_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - NVM Page Buffer Active Loading"] + #[inline(always)] + pub fn load(&self) -> LOAD_R { + LOAD_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Programming Error Status"] + #[inline(always)] + pub fn proge(&self) -> PROGE_R { + PROGE_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Lock Error Status"] + #[inline(always)] + pub fn locke(&self) -> LOCKE_R { + LOCKE_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - NVM Error"] + #[inline(always)] + pub fn nvme(&self) -> NVME_R { + NVME_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 8 - Security Bit Status"] + #[inline(always)] + pub fn sb(&self) -> SB_R { + SB_R::new(((self.bits >> 8) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Power Reduction Mode"] + #[inline(always)] + pub fn prm(&mut self) -> PRM_W { + PRM_W { w: self } + } + #[doc = "Bit 1 - NVM Page Buffer Active Loading"] + #[inline(always)] + pub fn load(&mut self) -> LOAD_W { + LOAD_W { w: self } + } + #[doc = "Bit 2 - Programming Error Status"] + #[inline(always)] + pub fn proge(&mut self) -> PROGE_W { + PROGE_W { w: self } + } + #[doc = "Bit 3 - Lock Error Status"] + #[inline(always)] + pub fn locke(&mut self) -> LOCKE_W { + LOCKE_W { w: self } + } + #[doc = "Bit 4 - NVM Error"] + #[inline(always)] + pub fn nvme(&mut self) -> NVME_W { + NVME_W { w: self } + } + #[doc = "Bit 8 - Security Bit Status"] + #[inline(always)] + pub fn sb(&mut self) -> SB_W { + SB_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/osc32kctrl.rs b/pac/atsamc20g/src/osc32kctrl.rs new file mode 100644 index 000000000000..263cd2f61d59 --- /dev/null +++ b/pac/atsamc20g/src/osc32kctrl.rs @@ -0,0 +1,64 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x04 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x08 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x0c - Power and Clocks Status"] + pub status: crate::Reg, + #[doc = "0x10 - Clock selection"] + pub rtcctrl: crate::Reg, + #[doc = "0x14 - 32kHz External Crystal Oscillator (XOSC32K) Control"] + pub xosc32k: crate::Reg, + #[doc = "0x16 - Clock Failure Detector Control"] + pub cfdctrl: crate::Reg, + #[doc = "0x17 - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x18 - 32kHz Internal Oscillator (OSC32K) Control"] + pub osc32k: crate::Reg, + #[doc = "0x1c - 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control"] + pub osculp32k: crate::Reg, +} +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Power and Clocks Status"] +pub mod status; +#[doc = "RTCCTRL register accessor: an alias for `Reg`"] +pub type RTCCTRL = crate::Reg; +#[doc = "Clock selection"] +pub mod rtcctrl; +#[doc = "XOSC32K register accessor: an alias for `Reg`"] +pub type XOSC32K = crate::Reg; +#[doc = "32kHz External Crystal Oscillator (XOSC32K) Control"] +pub mod xosc32k; +#[doc = "CFDCTRL register accessor: an alias for `Reg`"] +pub type CFDCTRL = crate::Reg; +#[doc = "Clock Failure Detector Control"] +pub mod cfdctrl; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "OSC32K register accessor: an alias for `Reg`"] +pub type OSC32K = crate::Reg; +#[doc = "32kHz Internal Oscillator (OSC32K) Control"] +pub mod osc32k; +#[doc = "OSCULP32K register accessor: an alias for `Reg`"] +pub type OSCULP32K = crate::Reg; +#[doc = "32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control"] +pub mod osculp32k; diff --git a/pac/atsamc20g/src/osc32kctrl/cfdctrl.rs b/pac/atsamc20g/src/osc32kctrl/cfdctrl.rs new file mode 100644 index 000000000000..492a86e1a5a7 --- /dev/null +++ b/pac/atsamc20g/src/osc32kctrl/cfdctrl.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CFDCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CFDCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CFDEN` reader - Clock Failure Detector Enable"] +pub struct CFDEN_R(crate::FieldReader); +impl CFDEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFDEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFDEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFDEN` writer - Clock Failure Detector Enable"] +pub struct CFDEN_W<'a> { + w: &'a mut W, +} +impl<'a> CFDEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SWBACK` reader - Clock Switch Back"] +pub struct SWBACK_R(crate::FieldReader); +impl SWBACK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWBACK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWBACK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWBACK` writer - Clock Switch Back"] +pub struct SWBACK_W<'a> { + w: &'a mut W, +} +impl<'a> SWBACK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CFDPRESC` reader - Clock Failure Detector Prescaler"] +pub struct CFDPRESC_R(crate::FieldReader); +impl CFDPRESC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFDPRESC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFDPRESC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFDPRESC` writer - Clock Failure Detector Prescaler"] +pub struct CFDPRESC_W<'a> { + w: &'a mut W, +} +impl<'a> CFDPRESC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Clock Failure Detector Enable"] + #[inline(always)] + pub fn cfden(&self) -> CFDEN_R { + CFDEN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Clock Switch Back"] + #[inline(always)] + pub fn swback(&self) -> SWBACK_R { + SWBACK_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Clock Failure Detector Prescaler"] + #[inline(always)] + pub fn cfdpresc(&self) -> CFDPRESC_R { + CFDPRESC_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Clock Failure Detector Enable"] + #[inline(always)] + pub fn cfden(&mut self) -> CFDEN_W { + CFDEN_W { w: self } + } + #[doc = "Bit 1 - Clock Switch Back"] + #[inline(always)] + pub fn swback(&mut self) -> SWBACK_W { + SWBACK_W { w: self } + } + #[doc = "Bit 2 - Clock Failure Detector Prescaler"] + #[inline(always)] + pub fn cfdpresc(&mut self) -> CFDPRESC_W { + CFDPRESC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Clock Failure Detector Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cfdctrl](index.html) module"] +pub struct CFDCTRL_SPEC; +impl crate::RegisterSpec for CFDCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [cfdctrl::R](R) reader structure"] +impl crate::Readable for CFDCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cfdctrl::W](W) writer structure"] +impl crate::Writable for CFDCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CFDCTRL to value 0"] +impl crate::Resettable for CFDCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/osc32kctrl/evctrl.rs b/pac/atsamc20g/src/osc32kctrl/evctrl.rs new file mode 100644 index 000000000000..e22ba62f0fe2 --- /dev/null +++ b/pac/atsamc20g/src/osc32kctrl/evctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CFDEO` reader - Clock Failure Detector Event Output Enable"] +pub struct CFDEO_R(crate::FieldReader); +impl CFDEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFDEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFDEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFDEO` writer - Clock Failure Detector Event Output Enable"] +pub struct CFDEO_W<'a> { + w: &'a mut W, +} +impl<'a> CFDEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Clock Failure Detector Event Output Enable"] + #[inline(always)] + pub fn cfdeo(&self) -> CFDEO_R { + CFDEO_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Clock Failure Detector Event Output Enable"] + #[inline(always)] + pub fn cfdeo(&mut self) -> CFDEO_W { + CFDEO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/osc32kctrl/intenclr.rs b/pac/atsamc20g/src/osc32kctrl/intenclr.rs new file mode 100644 index 000000000000..7e330c8de495 --- /dev/null +++ b/pac/atsamc20g/src/osc32kctrl/intenclr.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XOSC32KRDY` reader - XOSC32K Ready Interrupt Enable"] +pub struct XOSC32KRDY_R(crate::FieldReader); +impl XOSC32KRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSC32KRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSC32KRDY` writer - XOSC32K Ready Interrupt Enable"] +pub struct XOSC32KRDY_W<'a> { + w: &'a mut W, +} +impl<'a> XOSC32KRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `OSC32KRDY` reader - OSC32K Ready Interrupt Enable"] +pub struct OSC32KRDY_R(crate::FieldReader); +impl OSC32KRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC32KRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC32KRDY` writer - OSC32K Ready Interrupt Enable"] +pub struct OSC32KRDY_W<'a> { + w: &'a mut W, +} +impl<'a> OSC32KRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CLKFAIL` reader - XOSC32K Clock Failure Detector Interrupt Enable"] +pub struct CLKFAIL_R(crate::FieldReader); +impl CLKFAIL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKFAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKFAIL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKFAIL` writer - XOSC32K Clock Failure Detector Interrupt Enable"] +pub struct CLKFAIL_W<'a> { + w: &'a mut W, +} +impl<'a> CLKFAIL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - XOSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn xosc32krdy(&self) -> XOSC32KRDY_R { + XOSC32KRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - OSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn osc32krdy(&self) -> OSC32KRDY_R { + OSC32KRDY_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - XOSC32K Clock Failure Detector Interrupt Enable"] + #[inline(always)] + pub fn clkfail(&self) -> CLKFAIL_R { + CLKFAIL_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - XOSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn xosc32krdy(&mut self) -> XOSC32KRDY_W { + XOSC32KRDY_W { w: self } + } + #[doc = "Bit 1 - OSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn osc32krdy(&mut self) -> OSC32KRDY_W { + OSC32KRDY_W { w: self } + } + #[doc = "Bit 2 - XOSC32K Clock Failure Detector Interrupt Enable"] + #[inline(always)] + pub fn clkfail(&mut self) -> CLKFAIL_W { + CLKFAIL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/osc32kctrl/intenset.rs b/pac/atsamc20g/src/osc32kctrl/intenset.rs new file mode 100644 index 000000000000..e853d40049f2 --- /dev/null +++ b/pac/atsamc20g/src/osc32kctrl/intenset.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XOSC32KRDY` reader - XOSC32K Ready Interrupt Enable"] +pub struct XOSC32KRDY_R(crate::FieldReader); +impl XOSC32KRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSC32KRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSC32KRDY` writer - XOSC32K Ready Interrupt Enable"] +pub struct XOSC32KRDY_W<'a> { + w: &'a mut W, +} +impl<'a> XOSC32KRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `OSC32KRDY` reader - OSC32K Ready Interrupt Enable"] +pub struct OSC32KRDY_R(crate::FieldReader); +impl OSC32KRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC32KRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC32KRDY` writer - OSC32K Ready Interrupt Enable"] +pub struct OSC32KRDY_W<'a> { + w: &'a mut W, +} +impl<'a> OSC32KRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CLKFAIL` reader - XOSC32K Clock Failure Detector Interrupt Enable"] +pub struct CLKFAIL_R(crate::FieldReader); +impl CLKFAIL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKFAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKFAIL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKFAIL` writer - XOSC32K Clock Failure Detector Interrupt Enable"] +pub struct CLKFAIL_W<'a> { + w: &'a mut W, +} +impl<'a> CLKFAIL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - XOSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn xosc32krdy(&self) -> XOSC32KRDY_R { + XOSC32KRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - OSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn osc32krdy(&self) -> OSC32KRDY_R { + OSC32KRDY_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - XOSC32K Clock Failure Detector Interrupt Enable"] + #[inline(always)] + pub fn clkfail(&self) -> CLKFAIL_R { + CLKFAIL_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - XOSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn xosc32krdy(&mut self) -> XOSC32KRDY_W { + XOSC32KRDY_W { w: self } + } + #[doc = "Bit 1 - OSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn osc32krdy(&mut self) -> OSC32KRDY_W { + OSC32KRDY_W { w: self } + } + #[doc = "Bit 2 - XOSC32K Clock Failure Detector Interrupt Enable"] + #[inline(always)] + pub fn clkfail(&mut self) -> CLKFAIL_W { + CLKFAIL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/osc32kctrl/intflag.rs b/pac/atsamc20g/src/osc32kctrl/intflag.rs new file mode 100644 index 000000000000..9ca42439429d --- /dev/null +++ b/pac/atsamc20g/src/osc32kctrl/intflag.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XOSC32KRDY` reader - XOSC32K Ready"] +pub struct XOSC32KRDY_R(crate::FieldReader); +impl XOSC32KRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSC32KRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSC32KRDY` writer - XOSC32K Ready"] +pub struct XOSC32KRDY_W<'a> { + w: &'a mut W, +} +impl<'a> XOSC32KRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `OSC32KRDY` reader - OSC32K Ready"] +pub struct OSC32KRDY_R(crate::FieldReader); +impl OSC32KRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC32KRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC32KRDY` writer - OSC32K Ready"] +pub struct OSC32KRDY_W<'a> { + w: &'a mut W, +} +impl<'a> OSC32KRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CLKFAIL` reader - XOSC32K Clock Failure Detector"] +pub struct CLKFAIL_R(crate::FieldReader); +impl CLKFAIL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKFAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKFAIL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKFAIL` writer - XOSC32K Clock Failure Detector"] +pub struct CLKFAIL_W<'a> { + w: &'a mut W, +} +impl<'a> CLKFAIL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - XOSC32K Ready"] + #[inline(always)] + pub fn xosc32krdy(&self) -> XOSC32KRDY_R { + XOSC32KRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - OSC32K Ready"] + #[inline(always)] + pub fn osc32krdy(&self) -> OSC32KRDY_R { + OSC32KRDY_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - XOSC32K Clock Failure Detector"] + #[inline(always)] + pub fn clkfail(&self) -> CLKFAIL_R { + CLKFAIL_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - XOSC32K Ready"] + #[inline(always)] + pub fn xosc32krdy(&mut self) -> XOSC32KRDY_W { + XOSC32KRDY_W { w: self } + } + #[doc = "Bit 1 - OSC32K Ready"] + #[inline(always)] + pub fn osc32krdy(&mut self) -> OSC32KRDY_W { + OSC32KRDY_W { w: self } + } + #[doc = "Bit 2 - XOSC32K Clock Failure Detector"] + #[inline(always)] + pub fn clkfail(&mut self) -> CLKFAIL_W { + CLKFAIL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/osc32kctrl/osc32k.rs b/pac/atsamc20g/src/osc32kctrl/osc32k.rs new file mode 100644 index 000000000000..aa32cb287aa7 --- /dev/null +++ b/pac/atsamc20g/src/osc32kctrl/osc32k.rs @@ -0,0 +1,549 @@ +#[doc = "Register `OSC32K` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OSC32K` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Oscillator Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Oscillator Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `EN32K` reader - 32kHz Output Enable"] +pub struct EN32K_R(crate::FieldReader); +impl EN32K_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EN32K_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EN32K_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EN32K` writer - 32kHz Output Enable"] +pub struct EN32K_W<'a> { + w: &'a mut W, +} +impl<'a> EN32K_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `EN1K` reader - 1kHz Output Enable"] +pub struct EN1K_R(crate::FieldReader); +impl EN1K_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EN1K_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EN1K_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EN1K` writer - 1kHz Output Enable"] +pub struct EN1K_W<'a> { + w: &'a mut W, +} +impl<'a> EN1K_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - On Demand Control"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - On Demand Control"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Oscillator Start-Up Time\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum STARTUP_A { + #[doc = "0: 0.092 ms"] + CYCLE3 = 0, + #[doc = "1: 0.122 ms"] + CYCLE4 = 1, + #[doc = "2: 0.183 ms"] + CYCLE6 = 2, + #[doc = "3: 0.305 ms"] + CYCLE10 = 3, + #[doc = "4: 0.549 ms"] + CYCLE18 = 4, + #[doc = "5: 1.038 ms"] + CYCLE34 = 5, + #[doc = "6: 2.014 ms"] + CYCLE66 = 6, + #[doc = "7: 3.967 ms"] + CYCLE130 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: STARTUP_A) -> Self { + variant as _ + } +} +#[doc = "Field `STARTUP` reader - Oscillator Start-Up Time"] +pub struct STARTUP_R(crate::FieldReader); +impl STARTUP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + STARTUP_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STARTUP_A { + match self.bits { + 0 => STARTUP_A::CYCLE3, + 1 => STARTUP_A::CYCLE4, + 2 => STARTUP_A::CYCLE6, + 3 => STARTUP_A::CYCLE10, + 4 => STARTUP_A::CYCLE18, + 5 => STARTUP_A::CYCLE34, + 6 => STARTUP_A::CYCLE66, + 7 => STARTUP_A::CYCLE130, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `CYCLE3`"] + #[inline(always)] + pub fn is_cycle3(&self) -> bool { + **self == STARTUP_A::CYCLE3 + } + #[doc = "Checks if the value of the field is `CYCLE4`"] + #[inline(always)] + pub fn is_cycle4(&self) -> bool { + **self == STARTUP_A::CYCLE4 + } + #[doc = "Checks if the value of the field is `CYCLE6`"] + #[inline(always)] + pub fn is_cycle6(&self) -> bool { + **self == STARTUP_A::CYCLE6 + } + #[doc = "Checks if the value of the field is `CYCLE10`"] + #[inline(always)] + pub fn is_cycle10(&self) -> bool { + **self == STARTUP_A::CYCLE10 + } + #[doc = "Checks if the value of the field is `CYCLE18`"] + #[inline(always)] + pub fn is_cycle18(&self) -> bool { + **self == STARTUP_A::CYCLE18 + } + #[doc = "Checks if the value of the field is `CYCLE34`"] + #[inline(always)] + pub fn is_cycle34(&self) -> bool { + **self == STARTUP_A::CYCLE34 + } + #[doc = "Checks if the value of the field is `CYCLE66`"] + #[inline(always)] + pub fn is_cycle66(&self) -> bool { + **self == STARTUP_A::CYCLE66 + } + #[doc = "Checks if the value of the field is `CYCLE130`"] + #[inline(always)] + pub fn is_cycle130(&self) -> bool { + **self == STARTUP_A::CYCLE130 + } +} +impl core::ops::Deref for STARTUP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STARTUP` writer - Oscillator Start-Up Time"] +pub struct STARTUP_W<'a> { + w: &'a mut W, +} +impl<'a> STARTUP_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: STARTUP_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "0.092 ms"] + #[inline(always)] + pub fn cycle3(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE3) + } + #[doc = "0.122 ms"] + #[inline(always)] + pub fn cycle4(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE4) + } + #[doc = "0.183 ms"] + #[inline(always)] + pub fn cycle6(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE6) + } + #[doc = "0.305 ms"] + #[inline(always)] + pub fn cycle10(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE10) + } + #[doc = "0.549 ms"] + #[inline(always)] + pub fn cycle18(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE18) + } + #[doc = "1.038 ms"] + #[inline(always)] + pub fn cycle34(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE34) + } + #[doc = "2.014 ms"] + #[inline(always)] + pub fn cycle66(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE66) + } + #[doc = "3.967 ms"] + #[inline(always)] + pub fn cycle130(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE130) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +#[doc = "Field `WRTLOCK` reader - Write Lock"] +pub struct WRTLOCK_R(crate::FieldReader); +impl WRTLOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WRTLOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WRTLOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WRTLOCK` writer - Write Lock"] +pub struct WRTLOCK_W<'a> { + w: &'a mut W, +} +impl<'a> WRTLOCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `CALIB` reader - Oscillator Calibration"] +pub struct CALIB_R(crate::FieldReader); +impl CALIB_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CALIB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CALIB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CALIB` writer - Oscillator Calibration"] +pub struct CALIB_W<'a> { + w: &'a mut W, +} +impl<'a> CALIB_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x7f << 16)) | ((value as u32 & 0x7f) << 16); + self.w + } +} +impl R { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - 32kHz Output Enable"] + #[inline(always)] + pub fn en32k(&self) -> EN32K_R { + EN32K_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - 1kHz Output Enable"] + #[inline(always)] + pub fn en1k(&self) -> EN1K_R { + EN1K_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Oscillator Start-Up Time"] + #[inline(always)] + pub fn startup(&self) -> STARTUP_R { + STARTUP_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 12 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&self) -> WRTLOCK_R { + WRTLOCK_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bits 16:22 - Oscillator Calibration"] + #[inline(always)] + pub fn calib(&self) -> CALIB_R { + CALIB_R::new(((self.bits >> 16) & 0x7f) as u8) + } +} +impl W { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - 32kHz Output Enable"] + #[inline(always)] + pub fn en32k(&mut self) -> EN32K_W { + EN32K_W { w: self } + } + #[doc = "Bit 3 - 1kHz Output Enable"] + #[inline(always)] + pub fn en1k(&mut self) -> EN1K_W { + EN1K_W { w: self } + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Bits 8:10 - Oscillator Start-Up Time"] + #[inline(always)] + pub fn startup(&mut self) -> STARTUP_W { + STARTUP_W { w: self } + } + #[doc = "Bit 12 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&mut self) -> WRTLOCK_W { + WRTLOCK_W { w: self } + } + #[doc = "Bits 16:22 - Oscillator Calibration"] + #[inline(always)] + pub fn calib(&mut self) -> CALIB_W { + CALIB_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "32kHz Internal Oscillator (OSC32K) Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [osc32k](index.html) module"] +pub struct OSC32K_SPEC; +impl crate::RegisterSpec for OSC32K_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [osc32k::R](R) reader structure"] +impl crate::Readable for OSC32K_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [osc32k::W](W) writer structure"] +impl crate::Writable for OSC32K_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OSC32K to value 0x003f_0080"] +impl crate::Resettable for OSC32K_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x003f_0080 + } +} diff --git a/pac/atsamc20g/src/osc32kctrl/osculp32k.rs b/pac/atsamc20g/src/osc32kctrl/osculp32k.rs new file mode 100644 index 000000000000..1c351c406e59 --- /dev/null +++ b/pac/atsamc20g/src/osc32kctrl/osculp32k.rs @@ -0,0 +1,150 @@ +#[doc = "Register `OSCULP32K` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OSCULP32K` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CALIB` reader - Oscillator Calibration"] +pub struct CALIB_R(crate::FieldReader); +impl CALIB_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CALIB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CALIB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CALIB` writer - Oscillator Calibration"] +pub struct CALIB_W<'a> { + w: &'a mut W, +} +impl<'a> CALIB_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 8)) | ((value as u32 & 0x1f) << 8); + self.w + } +} +#[doc = "Field `WRTLOCK` reader - Write Lock"] +pub struct WRTLOCK_R(crate::FieldReader); +impl WRTLOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WRTLOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WRTLOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WRTLOCK` writer - Write Lock"] +pub struct WRTLOCK_W<'a> { + w: &'a mut W, +} +impl<'a> WRTLOCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bits 8:12 - Oscillator Calibration"] + #[inline(always)] + pub fn calib(&self) -> CALIB_R { + CALIB_R::new(((self.bits >> 8) & 0x1f) as u8) + } + #[doc = "Bit 15 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&self) -> WRTLOCK_R { + WRTLOCK_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 8:12 - Oscillator Calibration"] + #[inline(always)] + pub fn calib(&mut self) -> CALIB_W { + CALIB_W { w: self } + } + #[doc = "Bit 15 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&mut self) -> WRTLOCK_W { + WRTLOCK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [osculp32k](index.html) module"] +pub struct OSCULP32K_SPEC; +impl crate::RegisterSpec for OSCULP32K_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [osculp32k::R](R) reader structure"] +impl crate::Readable for OSCULP32K_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [osculp32k::W](W) writer structure"] +impl crate::Writable for OSCULP32K_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OSCULP32K to value 0"] +impl crate::Resettable for OSCULP32K_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/osc32kctrl/rtcctrl.rs b/pac/atsamc20g/src/osc32kctrl/rtcctrl.rs new file mode 100644 index 000000000000..1248024a03b9 --- /dev/null +++ b/pac/atsamc20g/src/osc32kctrl/rtcctrl.rs @@ -0,0 +1,204 @@ +#[doc = "Register `RTCCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RTCCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "RTC Clock Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum RTCSEL_A { + #[doc = "0: 1.024kHz from 32kHz internal ULP oscillator"] + ULP1K = 0, + #[doc = "1: 32.768kHz from 32kHz internal ULP oscillator"] + ULP32K = 1, + #[doc = "2: 1.024kHz from 32.768kHz internal oscillator"] + OSC1K = 2, + #[doc = "3: 32.768kHz from 32.768kHz internal oscillator"] + OSC32K = 3, + #[doc = "4: 1.024kHz from 32.768kHz internal oscillator"] + XOSC1K = 4, + #[doc = "5: 32.768kHz from 32.768kHz external crystal oscillator"] + XOSC32K = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RTCSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `RTCSEL` reader - RTC Clock Selection"] +pub struct RTCSEL_R(crate::FieldReader); +impl RTCSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RTCSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(RTCSEL_A::ULP1K), + 1 => Some(RTCSEL_A::ULP32K), + 2 => Some(RTCSEL_A::OSC1K), + 3 => Some(RTCSEL_A::OSC32K), + 4 => Some(RTCSEL_A::XOSC1K), + 5 => Some(RTCSEL_A::XOSC32K), + _ => None, + } + } + #[doc = "Checks if the value of the field is `ULP1K`"] + #[inline(always)] + pub fn is_ulp1k(&self) -> bool { + **self == RTCSEL_A::ULP1K + } + #[doc = "Checks if the value of the field is `ULP32K`"] + #[inline(always)] + pub fn is_ulp32k(&self) -> bool { + **self == RTCSEL_A::ULP32K + } + #[doc = "Checks if the value of the field is `OSC1K`"] + #[inline(always)] + pub fn is_osc1k(&self) -> bool { + **self == RTCSEL_A::OSC1K + } + #[doc = "Checks if the value of the field is `OSC32K`"] + #[inline(always)] + pub fn is_osc32k(&self) -> bool { + **self == RTCSEL_A::OSC32K + } + #[doc = "Checks if the value of the field is `XOSC1K`"] + #[inline(always)] + pub fn is_xosc1k(&self) -> bool { + **self == RTCSEL_A::XOSC1K + } + #[doc = "Checks if the value of the field is `XOSC32K`"] + #[inline(always)] + pub fn is_xosc32k(&self) -> bool { + **self == RTCSEL_A::XOSC32K + } +} +impl core::ops::Deref for RTCSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RTCSEL` writer - RTC Clock Selection"] +pub struct RTCSEL_W<'a> { + w: &'a mut W, +} +impl<'a> RTCSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RTCSEL_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "1.024kHz from 32kHz internal ULP oscillator"] + #[inline(always)] + pub fn ulp1k(self) -> &'a mut W { + self.variant(RTCSEL_A::ULP1K) + } + #[doc = "32.768kHz from 32kHz internal ULP oscillator"] + #[inline(always)] + pub fn ulp32k(self) -> &'a mut W { + self.variant(RTCSEL_A::ULP32K) + } + #[doc = "1.024kHz from 32.768kHz internal oscillator"] + #[inline(always)] + pub fn osc1k(self) -> &'a mut W { + self.variant(RTCSEL_A::OSC1K) + } + #[doc = "32.768kHz from 32.768kHz internal oscillator"] + #[inline(always)] + pub fn osc32k(self) -> &'a mut W { + self.variant(RTCSEL_A::OSC32K) + } + #[doc = "1.024kHz from 32.768kHz internal oscillator"] + #[inline(always)] + pub fn xosc1k(self) -> &'a mut W { + self.variant(RTCSEL_A::XOSC1K) + } + #[doc = "32.768kHz from 32.768kHz external crystal oscillator"] + #[inline(always)] + pub fn xosc32k(self) -> &'a mut W { + self.variant(RTCSEL_A::XOSC32K) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - RTC Clock Selection"] + #[inline(always)] + pub fn rtcsel(&self) -> RTCSEL_R { + RTCSEL_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - RTC Clock Selection"] + #[inline(always)] + pub fn rtcsel(&mut self) -> RTCSEL_W { + RTCSEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Clock selection\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rtcctrl](index.html) module"] +pub struct RTCCTRL_SPEC; +impl crate::RegisterSpec for RTCCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rtcctrl::R](R) reader structure"] +impl crate::Readable for RTCCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rtcctrl::W](W) writer structure"] +impl crate::Writable for RTCCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RTCCTRL to value 0"] +impl crate::Resettable for RTCCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/osc32kctrl/status.rs b/pac/atsamc20g/src/osc32kctrl/status.rs new file mode 100644 index 000000000000..f1f1483ac4e8 --- /dev/null +++ b/pac/atsamc20g/src/osc32kctrl/status.rs @@ -0,0 +1,113 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `XOSC32KRDY` reader - XOSC32K Ready"] +pub struct XOSC32KRDY_R(crate::FieldReader); +impl XOSC32KRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSC32KRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC32KRDY` reader - OSC32K Ready"] +pub struct OSC32KRDY_R(crate::FieldReader); +impl OSC32KRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC32KRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKFAIL` reader - XOSC32K Clock Failure Detector"] +pub struct CLKFAIL_R(crate::FieldReader); +impl CLKFAIL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKFAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKFAIL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKSW` reader - XOSC32K Clock switch"] +pub struct CLKSW_R(crate::FieldReader); +impl CLKSW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKSW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKSW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - XOSC32K Ready"] + #[inline(always)] + pub fn xosc32krdy(&self) -> XOSC32KRDY_R { + XOSC32KRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - OSC32K Ready"] + #[inline(always)] + pub fn osc32krdy(&self) -> OSC32KRDY_R { + OSC32KRDY_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - XOSC32K Clock Failure Detector"] + #[inline(always)] + pub fn clkfail(&self) -> CLKFAIL_R { + CLKFAIL_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - XOSC32K Clock switch"] + #[inline(always)] + pub fn clksw(&self) -> CLKSW_R { + CLKSW_R::new(((self.bits >> 3) & 0x01) != 0) + } +} +#[doc = "Power and Clocks Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/osc32kctrl/xosc32k.rs b/pac/atsamc20g/src/osc32kctrl/xosc32k.rs new file mode 100644 index 000000000000..93e42bba3c0e --- /dev/null +++ b/pac/atsamc20g/src/osc32kctrl/xosc32k.rs @@ -0,0 +1,559 @@ +#[doc = "Register `XOSC32K` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `XOSC32K` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Oscillator Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Oscillator Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `XTALEN` reader - Crystal Oscillator Enable"] +pub struct XTALEN_R(crate::FieldReader); +impl XTALEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XTALEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XTALEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XTALEN` writer - Crystal Oscillator Enable"] +pub struct XTALEN_W<'a> { + w: &'a mut W, +} +impl<'a> XTALEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `EN32K` reader - 32kHz Output Enable"] +pub struct EN32K_R(crate::FieldReader); +impl EN32K_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EN32K_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EN32K_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EN32K` writer - 32kHz Output Enable"] +pub struct EN32K_W<'a> { + w: &'a mut W, +} +impl<'a> EN32K_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `EN1K` reader - 1kHz Output Enable"] +pub struct EN1K_R(crate::FieldReader); +impl EN1K_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EN1K_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EN1K_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EN1K` writer - 1kHz Output Enable"] +pub struct EN1K_W<'a> { + w: &'a mut W, +} +impl<'a> EN1K_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - On Demand Control"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - On Demand Control"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Oscillator Start-Up Time\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum STARTUP_A { + #[doc = "0: 0.122 ms"] + CYCLE1 = 0, + #[doc = "1: 1.068 ms"] + CYCLE32 = 1, + #[doc = "2: 62.6 ms"] + CYCLE2048 = 2, + #[doc = "3: 125 ms"] + CYCLE4096 = 3, + #[doc = "4: 500 ms"] + CYCLE16384 = 4, + #[doc = "5: 1000 ms"] + CYCLE32768 = 5, + #[doc = "6: 2000 ms"] + CYCLE65536 = 6, + #[doc = "7: 4000 ms"] + CYCLE131072 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: STARTUP_A) -> Self { + variant as _ + } +} +#[doc = "Field `STARTUP` reader - Oscillator Start-Up Time"] +pub struct STARTUP_R(crate::FieldReader); +impl STARTUP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + STARTUP_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STARTUP_A { + match self.bits { + 0 => STARTUP_A::CYCLE1, + 1 => STARTUP_A::CYCLE32, + 2 => STARTUP_A::CYCLE2048, + 3 => STARTUP_A::CYCLE4096, + 4 => STARTUP_A::CYCLE16384, + 5 => STARTUP_A::CYCLE32768, + 6 => STARTUP_A::CYCLE65536, + 7 => STARTUP_A::CYCLE131072, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `CYCLE1`"] + #[inline(always)] + pub fn is_cycle1(&self) -> bool { + **self == STARTUP_A::CYCLE1 + } + #[doc = "Checks if the value of the field is `CYCLE32`"] + #[inline(always)] + pub fn is_cycle32(&self) -> bool { + **self == STARTUP_A::CYCLE32 + } + #[doc = "Checks if the value of the field is `CYCLE2048`"] + #[inline(always)] + pub fn is_cycle2048(&self) -> bool { + **self == STARTUP_A::CYCLE2048 + } + #[doc = "Checks if the value of the field is `CYCLE4096`"] + #[inline(always)] + pub fn is_cycle4096(&self) -> bool { + **self == STARTUP_A::CYCLE4096 + } + #[doc = "Checks if the value of the field is `CYCLE16384`"] + #[inline(always)] + pub fn is_cycle16384(&self) -> bool { + **self == STARTUP_A::CYCLE16384 + } + #[doc = "Checks if the value of the field is `CYCLE32768`"] + #[inline(always)] + pub fn is_cycle32768(&self) -> bool { + **self == STARTUP_A::CYCLE32768 + } + #[doc = "Checks if the value of the field is `CYCLE65536`"] + #[inline(always)] + pub fn is_cycle65536(&self) -> bool { + **self == STARTUP_A::CYCLE65536 + } + #[doc = "Checks if the value of the field is `CYCLE131072`"] + #[inline(always)] + pub fn is_cycle131072(&self) -> bool { + **self == STARTUP_A::CYCLE131072 + } +} +impl core::ops::Deref for STARTUP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STARTUP` writer - Oscillator Start-Up Time"] +pub struct STARTUP_W<'a> { + w: &'a mut W, +} +impl<'a> STARTUP_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: STARTUP_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "0.122 ms"] + #[inline(always)] + pub fn cycle1(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE1) + } + #[doc = "1.068 ms"] + #[inline(always)] + pub fn cycle32(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE32) + } + #[doc = "62.6 ms"] + #[inline(always)] + pub fn cycle2048(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE2048) + } + #[doc = "125 ms"] + #[inline(always)] + pub fn cycle4096(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE4096) + } + #[doc = "500 ms"] + #[inline(always)] + pub fn cycle16384(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE16384) + } + #[doc = "1000 ms"] + #[inline(always)] + pub fn cycle32768(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE32768) + } + #[doc = "2000 ms"] + #[inline(always)] + pub fn cycle65536(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE65536) + } + #[doc = "4000 ms"] + #[inline(always)] + pub fn cycle131072(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE131072) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u16 & 0x07) << 8); + self.w + } +} +#[doc = "Field `WRTLOCK` reader - Write Lock"] +pub struct WRTLOCK_R(crate::FieldReader); +impl WRTLOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WRTLOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WRTLOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WRTLOCK` writer - Write Lock"] +pub struct WRTLOCK_W<'a> { + w: &'a mut W, +} +impl<'a> WRTLOCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u16 & 0x01) << 12); + self.w + } +} +impl R { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Crystal Oscillator Enable"] + #[inline(always)] + pub fn xtalen(&self) -> XTALEN_R { + XTALEN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - 32kHz Output Enable"] + #[inline(always)] + pub fn en32k(&self) -> EN32K_R { + EN32K_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - 1kHz Output Enable"] + #[inline(always)] + pub fn en1k(&self) -> EN1K_R { + EN1K_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Oscillator Start-Up Time"] + #[inline(always)] + pub fn startup(&self) -> STARTUP_R { + STARTUP_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 12 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&self) -> WRTLOCK_R { + WRTLOCK_R::new(((self.bits >> 12) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - Crystal Oscillator Enable"] + #[inline(always)] + pub fn xtalen(&mut self) -> XTALEN_W { + XTALEN_W { w: self } + } + #[doc = "Bit 3 - 32kHz Output Enable"] + #[inline(always)] + pub fn en32k(&mut self) -> EN32K_W { + EN32K_W { w: self } + } + #[doc = "Bit 4 - 1kHz Output Enable"] + #[inline(always)] + pub fn en1k(&mut self) -> EN1K_W { + EN1K_W { w: self } + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Bits 8:10 - Oscillator Start-Up Time"] + #[inline(always)] + pub fn startup(&mut self) -> STARTUP_W { + STARTUP_W { w: self } + } + #[doc = "Bit 12 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&mut self) -> WRTLOCK_W { + WRTLOCK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "32kHz External Crystal Oscillator (XOSC32K) Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [xosc32k](index.html) module"] +pub struct XOSC32K_SPEC; +impl crate::RegisterSpec for XOSC32K_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [xosc32k::R](R) reader structure"] +impl crate::Readable for XOSC32K_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [xosc32k::W](W) writer structure"] +impl crate::Writable for XOSC32K_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets XOSC32K to value 0x80"] +impl crate::Resettable for XOSC32K_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x80 + } +} diff --git a/pac/atsamc20g/src/oscctrl.rs b/pac/atsamc20g/src/oscctrl.rs new file mode 100644 index 000000000000..e6dd0929927c --- /dev/null +++ b/pac/atsamc20g/src/oscctrl.rs @@ -0,0 +1,117 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x04 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x08 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x0c - Power and Clocks Status"] + pub status: crate::Reg, + #[doc = "0x10 - External Multipurpose Crystal Oscillator (XOSC) Control"] + pub xoscctrl: crate::Reg, + #[doc = "0x12 - Clock Failure Detector Prescaler"] + pub cfdpresc: crate::Reg, + #[doc = "0x13 - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x14 - 48MHz Internal Oscillator (OSC48M) Control"] + pub osc48mctrl: crate::Reg, + #[doc = "0x15 - OSC48M Divider"] + pub osc48mdiv: crate::Reg, + #[doc = "0x16 - OSC48M Startup Time"] + pub osc48mstup: crate::Reg, + _reserved10: [u8; 0x01], + #[doc = "0x18 - OSC48M Synchronization Busy"] + pub osc48msyncbusy: crate::Reg, + #[doc = "0x1c - DPLL Control"] + pub dpllctrla: crate::Reg, + _reserved12: [u8; 0x03], + #[doc = "0x20 - DPLL Ratio Control"] + pub dpllratio: crate::Reg, + #[doc = "0x24 - Digital Core Configuration"] + pub dpllctrlb: crate::Reg, + #[doc = "0x28 - DPLL Prescaler"] + pub dpllpresc: crate::Reg, + _reserved15: [u8; 0x03], + #[doc = "0x2c - DPLL Synchronization Busy"] + pub dpllsyncbusy: crate::Reg, + _reserved16: [u8; 0x03], + #[doc = "0x30 - DPLL Status"] + pub dpllstatus: crate::Reg, + _reserved17: [u8; 0x07], + #[doc = "0x38 - 48MHz Oscillator Calibration"] + pub cal48m: crate::Reg, +} +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Power and Clocks Status"] +pub mod status; +#[doc = "XOSCCTRL register accessor: an alias for `Reg`"] +pub type XOSCCTRL = crate::Reg; +#[doc = "External Multipurpose Crystal Oscillator (XOSC) Control"] +pub mod xoscctrl; +#[doc = "CFDPRESC register accessor: an alias for `Reg`"] +pub type CFDPRESC = crate::Reg; +#[doc = "Clock Failure Detector Prescaler"] +pub mod cfdpresc; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "OSC48MCTRL register accessor: an alias for `Reg`"] +pub type OSC48MCTRL = crate::Reg; +#[doc = "48MHz Internal Oscillator (OSC48M) Control"] +pub mod osc48mctrl; +#[doc = "OSC48MDIV register accessor: an alias for `Reg`"] +pub type OSC48MDIV = crate::Reg; +#[doc = "OSC48M Divider"] +pub mod osc48mdiv; +#[doc = "OSC48MSTUP register accessor: an alias for `Reg`"] +pub type OSC48MSTUP = crate::Reg; +#[doc = "OSC48M Startup Time"] +pub mod osc48mstup; +#[doc = "OSC48MSYNCBUSY register accessor: an alias for `Reg`"] +pub type OSC48MSYNCBUSY = crate::Reg; +#[doc = "OSC48M Synchronization Busy"] +pub mod osc48msyncbusy; +#[doc = "DPLLCTRLA register accessor: an alias for `Reg`"] +pub type DPLLCTRLA = crate::Reg; +#[doc = "DPLL Control"] +pub mod dpllctrla; +#[doc = "DPLLRATIO register accessor: an alias for `Reg`"] +pub type DPLLRATIO = crate::Reg; +#[doc = "DPLL Ratio Control"] +pub mod dpllratio; +#[doc = "DPLLCTRLB register accessor: an alias for `Reg`"] +pub type DPLLCTRLB = crate::Reg; +#[doc = "Digital Core Configuration"] +pub mod dpllctrlb; +#[doc = "DPLLPRESC register accessor: an alias for `Reg`"] +pub type DPLLPRESC = crate::Reg; +#[doc = "DPLL Prescaler"] +pub mod dpllpresc; +#[doc = "DPLLSYNCBUSY register accessor: an alias for `Reg`"] +pub type DPLLSYNCBUSY = crate::Reg; +#[doc = "DPLL Synchronization Busy"] +pub mod dpllsyncbusy; +#[doc = "DPLLSTATUS register accessor: an alias for `Reg`"] +pub type DPLLSTATUS = crate::Reg; +#[doc = "DPLL Status"] +pub mod dpllstatus; +#[doc = "CAL48M register accessor: an alias for `Reg`"] +pub type CAL48M = crate::Reg; +#[doc = "48MHz Oscillator Calibration"] +pub mod cal48m; diff --git a/pac/atsamc20g/src/oscctrl/cal48m.rs b/pac/atsamc20g/src/oscctrl/cal48m.rs new file mode 100644 index 000000000000..05d5cd2bbc92 --- /dev/null +++ b/pac/atsamc20g/src/oscctrl/cal48m.rs @@ -0,0 +1,177 @@ +#[doc = "Register `CAL48M` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CAL48M` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FCAL` reader - Frequency Calibration (48MHz)"] +pub struct FCAL_R(crate::FieldReader); +impl FCAL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FCAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FCAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FCAL` writer - Frequency Calibration (48MHz)"] +pub struct FCAL_W<'a> { + w: &'a mut W, +} +impl<'a> FCAL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +#[doc = "Field `FRANGE` reader - Frequency Range (48MHz)"] +pub struct FRANGE_R(crate::FieldReader); +impl FRANGE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FRANGE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FRANGE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FRANGE` writer - Frequency Range (48MHz)"] +pub struct FRANGE_W<'a> { + w: &'a mut W, +} +impl<'a> FRANGE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 8)) | ((value as u32 & 0x03) << 8); + self.w + } +} +#[doc = "Field `TCAL` reader - Temperature Calibration (48MHz)"] +pub struct TCAL_R(crate::FieldReader); +impl TCAL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TCAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCAL` writer - Temperature Calibration (48MHz)"] +pub struct TCAL_W<'a> { + w: &'a mut W, +} +impl<'a> TCAL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 16)) | ((value as u32 & 0x3f) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Frequency Calibration (48MHz)"] + #[inline(always)] + pub fn fcal(&self) -> FCAL_R { + FCAL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 8:9 - Frequency Range (48MHz)"] + #[inline(always)] + pub fn frange(&self) -> FRANGE_R { + FRANGE_R::new(((self.bits >> 8) & 0x03) as u8) + } + #[doc = "Bits 16:21 - Temperature Calibration (48MHz)"] + #[inline(always)] + pub fn tcal(&self) -> TCAL_R { + TCAL_R::new(((self.bits >> 16) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - Frequency Calibration (48MHz)"] + #[inline(always)] + pub fn fcal(&mut self) -> FCAL_W { + FCAL_W { w: self } + } + #[doc = "Bits 8:9 - Frequency Range (48MHz)"] + #[inline(always)] + pub fn frange(&mut self) -> FRANGE_W { + FRANGE_W { w: self } + } + #[doc = "Bits 16:21 - Temperature Calibration (48MHz)"] + #[inline(always)] + pub fn tcal(&mut self) -> TCAL_W { + TCAL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "48MHz Oscillator Calibration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cal48m](index.html) module"] +pub struct CAL48M_SPEC; +impl crate::RegisterSpec for CAL48M_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cal48m::R](R) reader structure"] +impl crate::Readable for CAL48M_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cal48m::W](W) writer structure"] +impl crate::Writable for CAL48M_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CAL48M to value 0"] +impl crate::Resettable for CAL48M_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/oscctrl/cfdpresc.rs b/pac/atsamc20g/src/oscctrl/cfdpresc.rs new file mode 100644 index 000000000000..029ae541eec5 --- /dev/null +++ b/pac/atsamc20g/src/oscctrl/cfdpresc.rs @@ -0,0 +1,230 @@ +#[doc = "Register `CFDPRESC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CFDPRESC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Clock Failure Detector Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CFDPRESC_A { + #[doc = "0: 48 MHz"] + DIV1 = 0, + #[doc = "1: 24 MHz"] + DIV2 = 1, + #[doc = "2: 12 MHz"] + DIV4 = 2, + #[doc = "3: 6 MHz"] + DIV8 = 3, + #[doc = "4: 3 MHz"] + DIV16 = 4, + #[doc = "5: 1.5 MHz"] + DIV32 = 5, + #[doc = "6: 0.75 MHz"] + DIV64 = 6, + #[doc = "7: 0.3125 MHz"] + DIV128 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CFDPRESC_A) -> Self { + variant as _ + } +} +#[doc = "Field `CFDPRESC` reader - Clock Failure Detector Prescaler"] +pub struct CFDPRESC_R(crate::FieldReader); +impl CFDPRESC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CFDPRESC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CFDPRESC_A { + match self.bits { + 0 => CFDPRESC_A::DIV1, + 1 => CFDPRESC_A::DIV2, + 2 => CFDPRESC_A::DIV4, + 3 => CFDPRESC_A::DIV8, + 4 => CFDPRESC_A::DIV16, + 5 => CFDPRESC_A::DIV32, + 6 => CFDPRESC_A::DIV64, + 7 => CFDPRESC_A::DIV128, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == CFDPRESC_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == CFDPRESC_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == CFDPRESC_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == CFDPRESC_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == CFDPRESC_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == CFDPRESC_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == CFDPRESC_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == CFDPRESC_A::DIV128 + } +} +impl core::ops::Deref for CFDPRESC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFDPRESC` writer - Clock Failure Detector Prescaler"] +pub struct CFDPRESC_W<'a> { + w: &'a mut W, +} +impl<'a> CFDPRESC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CFDPRESC_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "48 MHz"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(CFDPRESC_A::DIV1) + } + #[doc = "24 MHz"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(CFDPRESC_A::DIV2) + } + #[doc = "12 MHz"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(CFDPRESC_A::DIV4) + } + #[doc = "6 MHz"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(CFDPRESC_A::DIV8) + } + #[doc = "3 MHz"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(CFDPRESC_A::DIV16) + } + #[doc = "1.5 MHz"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(CFDPRESC_A::DIV32) + } + #[doc = "0.75 MHz"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(CFDPRESC_A::DIV64) + } + #[doc = "0.3125 MHz"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(CFDPRESC_A::DIV128) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Clock Failure Detector Prescaler"] + #[inline(always)] + pub fn cfdpresc(&self) -> CFDPRESC_R { + CFDPRESC_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Clock Failure Detector Prescaler"] + #[inline(always)] + pub fn cfdpresc(&mut self) -> CFDPRESC_W { + CFDPRESC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Clock Failure Detector Prescaler\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cfdpresc](index.html) module"] +pub struct CFDPRESC_SPEC; +impl crate::RegisterSpec for CFDPRESC_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [cfdpresc::R](R) reader structure"] +impl crate::Readable for CFDPRESC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cfdpresc::W](W) writer structure"] +impl crate::Writable for CFDPRESC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CFDPRESC to value 0"] +impl crate::Resettable for CFDPRESC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/oscctrl/dpllctrla.rs b/pac/atsamc20g/src/oscctrl/dpllctrla.rs new file mode 100644 index 000000000000..5a60a5087002 --- /dev/null +++ b/pac/atsamc20g/src/oscctrl/dpllctrla.rs @@ -0,0 +1,207 @@ +#[doc = "Register `DPLLCTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DPLLCTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - On Demand"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - On Demand"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - On Demand"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - On Demand"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DPLL Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dpllctrla](index.html) module"] +pub struct DPLLCTRLA_SPEC; +impl crate::RegisterSpec for DPLLCTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dpllctrla::R](R) reader structure"] +impl crate::Readable for DPLLCTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dpllctrla::W](W) writer structure"] +impl crate::Writable for DPLLCTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DPLLCTRLA to value 0x80"] +impl crate::Resettable for DPLLCTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x80 + } +} diff --git a/pac/atsamc20g/src/oscctrl/dpllctrlb.rs b/pac/atsamc20g/src/oscctrl/dpllctrlb.rs new file mode 100644 index 000000000000..8400b0572dd0 --- /dev/null +++ b/pac/atsamc20g/src/oscctrl/dpllctrlb.rs @@ -0,0 +1,580 @@ +#[doc = "Register `DPLLCTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DPLLCTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Proportional Integral Filter Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FILTER_A { + #[doc = "0: Default filter mode"] + DEFAULT = 0, + #[doc = "1: Low bandwidth filter"] + LBFILT = 1, + #[doc = "2: High bandwidth filter"] + HBFILT = 2, + #[doc = "3: High damping filter"] + HDFILT = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FILTER_A) -> Self { + variant as _ + } +} +#[doc = "Field `FILTER` reader - Proportional Integral Filter Selection"] +pub struct FILTER_R(crate::FieldReader); +impl FILTER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FILTER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FILTER_A { + match self.bits { + 0 => FILTER_A::DEFAULT, + 1 => FILTER_A::LBFILT, + 2 => FILTER_A::HBFILT, + 3 => FILTER_A::HDFILT, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DEFAULT`"] + #[inline(always)] + pub fn is_default(&self) -> bool { + **self == FILTER_A::DEFAULT + } + #[doc = "Checks if the value of the field is `LBFILT`"] + #[inline(always)] + pub fn is_lbfilt(&self) -> bool { + **self == FILTER_A::LBFILT + } + #[doc = "Checks if the value of the field is `HBFILT`"] + #[inline(always)] + pub fn is_hbfilt(&self) -> bool { + **self == FILTER_A::HBFILT + } + #[doc = "Checks if the value of the field is `HDFILT`"] + #[inline(always)] + pub fn is_hdfilt(&self) -> bool { + **self == FILTER_A::HDFILT + } +} +impl core::ops::Deref for FILTER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTER` writer - Proportional Integral Filter Selection"] +pub struct FILTER_W<'a> { + w: &'a mut W, +} +impl<'a> FILTER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FILTER_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Default filter mode"] + #[inline(always)] + pub fn default(self) -> &'a mut W { + self.variant(FILTER_A::DEFAULT) + } + #[doc = "Low bandwidth filter"] + #[inline(always)] + pub fn lbfilt(self) -> &'a mut W { + self.variant(FILTER_A::LBFILT) + } + #[doc = "High bandwidth filter"] + #[inline(always)] + pub fn hbfilt(self) -> &'a mut W { + self.variant(FILTER_A::HBFILT) + } + #[doc = "High damping filter"] + #[inline(always)] + pub fn hdfilt(self) -> &'a mut W { + self.variant(FILTER_A::HDFILT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u32 & 0x03); + self.w + } +} +#[doc = "Field `LPEN` reader - Low-Power Enable"] +pub struct LPEN_R(crate::FieldReader); +impl LPEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LPEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LPEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LPEN` writer - Low-Power Enable"] +pub struct LPEN_W<'a> { + w: &'a mut W, +} +impl<'a> LPEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `WUF` reader - Wake Up Fast"] +pub struct WUF_R(crate::FieldReader); +impl WUF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WUF` writer - Wake Up Fast"] +pub struct WUF_W<'a> { + w: &'a mut W, +} +impl<'a> WUF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Reference Clock Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum REFCLK_A { + #[doc = "0: XOSC32K clock reference"] + XOSC32K = 0, + #[doc = "1: XOSC clock reference"] + XOSC = 1, + #[doc = "2: GCLK clock reference"] + GCLK = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: REFCLK_A) -> Self { + variant as _ + } +} +#[doc = "Field `REFCLK` reader - Reference Clock Selection"] +pub struct REFCLK_R(crate::FieldReader); +impl REFCLK_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REFCLK_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(REFCLK_A::XOSC32K), + 1 => Some(REFCLK_A::XOSC), + 2 => Some(REFCLK_A::GCLK), + _ => None, + } + } + #[doc = "Checks if the value of the field is `XOSC32K`"] + #[inline(always)] + pub fn is_xosc32k(&self) -> bool { + **self == REFCLK_A::XOSC32K + } + #[doc = "Checks if the value of the field is `XOSC`"] + #[inline(always)] + pub fn is_xosc(&self) -> bool { + **self == REFCLK_A::XOSC + } + #[doc = "Checks if the value of the field is `GCLK`"] + #[inline(always)] + pub fn is_gclk(&self) -> bool { + **self == REFCLK_A::GCLK + } +} +impl core::ops::Deref for REFCLK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REFCLK` writer - Reference Clock Selection"] +pub struct REFCLK_W<'a> { + w: &'a mut W, +} +impl<'a> REFCLK_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: REFCLK_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "XOSC32K clock reference"] + #[inline(always)] + pub fn xosc32k(self) -> &'a mut W { + self.variant(REFCLK_A::XOSC32K) + } + #[doc = "XOSC clock reference"] + #[inline(always)] + pub fn xosc(self) -> &'a mut W { + self.variant(REFCLK_A::XOSC) + } + #[doc = "GCLK clock reference"] + #[inline(always)] + pub fn gclk(self) -> &'a mut W { + self.variant(REFCLK_A::GCLK) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u32 & 0x03) << 4); + self.w + } +} +#[doc = "Lock Time\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum LTIME_A { + #[doc = "0: No time-out. Automatic lock."] + DEFAULT = 0, + #[doc = "4: Time-out if no lock within 8ms"] + _8MS = 4, + #[doc = "5: Time-out if no lock within 9ms"] + _9MS = 5, + #[doc = "6: Time-out if no lock within 10ms"] + _10MS = 6, + #[doc = "7: Time-out if no lock within 11ms"] + _11MS = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LTIME_A) -> Self { + variant as _ + } +} +#[doc = "Field `LTIME` reader - Lock Time"] +pub struct LTIME_R(crate::FieldReader); +impl LTIME_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LTIME_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(LTIME_A::DEFAULT), + 4 => Some(LTIME_A::_8MS), + 5 => Some(LTIME_A::_9MS), + 6 => Some(LTIME_A::_10MS), + 7 => Some(LTIME_A::_11MS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DEFAULT`"] + #[inline(always)] + pub fn is_default(&self) -> bool { + **self == LTIME_A::DEFAULT + } + #[doc = "Checks if the value of the field is `_8MS`"] + #[inline(always)] + pub fn is_8ms(&self) -> bool { + **self == LTIME_A::_8MS + } + #[doc = "Checks if the value of the field is `_9MS`"] + #[inline(always)] + pub fn is_9ms(&self) -> bool { + **self == LTIME_A::_9MS + } + #[doc = "Checks if the value of the field is `_10MS`"] + #[inline(always)] + pub fn is_10ms(&self) -> bool { + **self == LTIME_A::_10MS + } + #[doc = "Checks if the value of the field is `_11MS`"] + #[inline(always)] + pub fn is_11ms(&self) -> bool { + **self == LTIME_A::_11MS + } +} +impl core::ops::Deref for LTIME_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LTIME` writer - Lock Time"] +pub struct LTIME_W<'a> { + w: &'a mut W, +} +impl<'a> LTIME_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: LTIME_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No time-out. Automatic lock."] + #[inline(always)] + pub fn default(self) -> &'a mut W { + self.variant(LTIME_A::DEFAULT) + } + #[doc = "Time-out if no lock within 8ms"] + #[inline(always)] + pub fn _8ms(self) -> &'a mut W { + self.variant(LTIME_A::_8MS) + } + #[doc = "Time-out if no lock within 9ms"] + #[inline(always)] + pub fn _9ms(self) -> &'a mut W { + self.variant(LTIME_A::_9MS) + } + #[doc = "Time-out if no lock within 10ms"] + #[inline(always)] + pub fn _10ms(self) -> &'a mut W { + self.variant(LTIME_A::_10MS) + } + #[doc = "Time-out if no lock within 11ms"] + #[inline(always)] + pub fn _11ms(self) -> &'a mut W { + self.variant(LTIME_A::_11MS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +#[doc = "Field `LBYPASS` reader - Lock Bypass"] +pub struct LBYPASS_R(crate::FieldReader); +impl LBYPASS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LBYPASS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LBYPASS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LBYPASS` writer - Lock Bypass"] +pub struct LBYPASS_W<'a> { + w: &'a mut W, +} +impl<'a> LBYPASS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `DIV` reader - Clock Divider"] +pub struct DIV_R(crate::FieldReader); +impl DIV_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + DIV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIV` writer - Clock Divider"] +pub struct DIV_W<'a> { + w: &'a mut W, +} +impl<'a> DIV_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07ff << 16)) | ((value as u32 & 0x07ff) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Proportional Integral Filter Selection"] + #[inline(always)] + pub fn filter(&self) -> FILTER_R { + FILTER_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bit 2 - Low-Power Enable"] + #[inline(always)] + pub fn lpen(&self) -> LPEN_R { + LPEN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Wake Up Fast"] + #[inline(always)] + pub fn wuf(&self) -> WUF_R { + WUF_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bits 4:5 - Reference Clock Selection"] + #[inline(always)] + pub fn refclk(&self) -> REFCLK_R { + REFCLK_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bits 8:10 - Lock Time"] + #[inline(always)] + pub fn ltime(&self) -> LTIME_R { + LTIME_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 12 - Lock Bypass"] + #[inline(always)] + pub fn lbypass(&self) -> LBYPASS_R { + LBYPASS_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bits 16:26 - Clock Divider"] + #[inline(always)] + pub fn div(&self) -> DIV_R { + DIV_R::new(((self.bits >> 16) & 0x07ff) as u16) + } +} +impl W { + #[doc = "Bits 0:1 - Proportional Integral Filter Selection"] + #[inline(always)] + pub fn filter(&mut self) -> FILTER_W { + FILTER_W { w: self } + } + #[doc = "Bit 2 - Low-Power Enable"] + #[inline(always)] + pub fn lpen(&mut self) -> LPEN_W { + LPEN_W { w: self } + } + #[doc = "Bit 3 - Wake Up Fast"] + #[inline(always)] + pub fn wuf(&mut self) -> WUF_W { + WUF_W { w: self } + } + #[doc = "Bits 4:5 - Reference Clock Selection"] + #[inline(always)] + pub fn refclk(&mut self) -> REFCLK_W { + REFCLK_W { w: self } + } + #[doc = "Bits 8:10 - Lock Time"] + #[inline(always)] + pub fn ltime(&mut self) -> LTIME_W { + LTIME_W { w: self } + } + #[doc = "Bit 12 - Lock Bypass"] + #[inline(always)] + pub fn lbypass(&mut self) -> LBYPASS_W { + LBYPASS_W { w: self } + } + #[doc = "Bits 16:26 - Clock Divider"] + #[inline(always)] + pub fn div(&mut self) -> DIV_W { + DIV_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Digital Core Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dpllctrlb](index.html) module"] +pub struct DPLLCTRLB_SPEC; +impl crate::RegisterSpec for DPLLCTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dpllctrlb::R](R) reader structure"] +impl crate::Readable for DPLLCTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dpllctrlb::W](W) writer structure"] +impl crate::Writable for DPLLCTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DPLLCTRLB to value 0"] +impl crate::Resettable for DPLLCTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/oscctrl/dpllpresc.rs b/pac/atsamc20g/src/oscctrl/dpllpresc.rs new file mode 100644 index 000000000000..9de662161f99 --- /dev/null +++ b/pac/atsamc20g/src/oscctrl/dpllpresc.rs @@ -0,0 +1,165 @@ +#[doc = "Register `DPLLPRESC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DPLLPRESC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Output Clock Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESC_A { + #[doc = "0: DPLL output is divided by 1"] + DIV1 = 0, + #[doc = "1: DPLL output is divided by 2"] + DIV2 = 1, + #[doc = "2: DPLL output is divided by 4"] + DIV4 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESC_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESC` reader - Output Clock Prescaler"] +pub struct PRESC_R(crate::FieldReader); +impl PRESC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESC_A::DIV1), + 1 => Some(PRESC_A::DIV2), + 2 => Some(PRESC_A::DIV4), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == PRESC_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESC_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESC_A::DIV4 + } +} +impl core::ops::Deref for PRESC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESC` writer - Output Clock Prescaler"] +pub struct PRESC_W<'a> { + w: &'a mut W, +} +impl<'a> PRESC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESC_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "DPLL output is divided by 1"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESC_A::DIV1) + } + #[doc = "DPLL output is divided by 2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESC_A::DIV2) + } + #[doc = "DPLL output is divided by 4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESC_A::DIV4) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u8 & 0x03); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Output Clock Prescaler"] + #[inline(always)] + pub fn presc(&self) -> PRESC_R { + PRESC_R::new((self.bits & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Output Clock Prescaler"] + #[inline(always)] + pub fn presc(&mut self) -> PRESC_W { + PRESC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DPLL Prescaler\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dpllpresc](index.html) module"] +pub struct DPLLPRESC_SPEC; +impl crate::RegisterSpec for DPLLPRESC_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dpllpresc::R](R) reader structure"] +impl crate::Readable for DPLLPRESC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dpllpresc::W](W) writer structure"] +impl crate::Writable for DPLLPRESC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DPLLPRESC to value 0"] +impl crate::Resettable for DPLLPRESC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/oscctrl/dpllratio.rs b/pac/atsamc20g/src/oscctrl/dpllratio.rs new file mode 100644 index 000000000000..93b39e30f1a5 --- /dev/null +++ b/pac/atsamc20g/src/oscctrl/dpllratio.rs @@ -0,0 +1,140 @@ +#[doc = "Register `DPLLRATIO` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DPLLRATIO` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `LDR` reader - Loop Divider Ratio"] +pub struct LDR_R(crate::FieldReader); +impl LDR_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + LDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LDR` writer - Loop Divider Ratio"] +pub struct LDR_W<'a> { + w: &'a mut W, +} +impl<'a> LDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0fff) | (value as u32 & 0x0fff); + self.w + } +} +#[doc = "Field `LDRFRAC` reader - Loop Divider Ratio Fractional Part"] +pub struct LDRFRAC_R(crate::FieldReader); +impl LDRFRAC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LDRFRAC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LDRFRAC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LDRFRAC` writer - Loop Divider Ratio Fractional Part"] +pub struct LDRFRAC_W<'a> { + w: &'a mut W, +} +impl<'a> LDRFRAC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 16)) | ((value as u32 & 0x0f) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:11 - Loop Divider Ratio"] + #[inline(always)] + pub fn ldr(&self) -> LDR_R { + LDR_R::new((self.bits & 0x0fff) as u16) + } + #[doc = "Bits 16:19 - Loop Divider Ratio Fractional Part"] + #[inline(always)] + pub fn ldrfrac(&self) -> LDRFRAC_R { + LDRFRAC_R::new(((self.bits >> 16) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:11 - Loop Divider Ratio"] + #[inline(always)] + pub fn ldr(&mut self) -> LDR_W { + LDR_W { w: self } + } + #[doc = "Bits 16:19 - Loop Divider Ratio Fractional Part"] + #[inline(always)] + pub fn ldrfrac(&mut self) -> LDRFRAC_W { + LDRFRAC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DPLL Ratio Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dpllratio](index.html) module"] +pub struct DPLLRATIO_SPEC; +impl crate::RegisterSpec for DPLLRATIO_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dpllratio::R](R) reader structure"] +impl crate::Readable for DPLLRATIO_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dpllratio::W](W) writer structure"] +impl crate::Writable for DPLLRATIO_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DPLLRATIO to value 0"] +impl crate::Resettable for DPLLRATIO_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/oscctrl/dpllstatus.rs b/pac/atsamc20g/src/oscctrl/dpllstatus.rs new file mode 100644 index 000000000000..931900212816 --- /dev/null +++ b/pac/atsamc20g/src/oscctrl/dpllstatus.rs @@ -0,0 +1,73 @@ +#[doc = "Register `DPLLSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `LOCK` reader - DPLL Lock Status"] +pub struct LOCK_R(crate::FieldReader); +impl LOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKRDY` reader - DPLL Clock Ready"] +pub struct CLKRDY_R(crate::FieldReader); +impl CLKRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - DPLL Lock Status"] + #[inline(always)] + pub fn lock(&self) -> LOCK_R { + LOCK_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - DPLL Clock Ready"] + #[inline(always)] + pub fn clkrdy(&self) -> CLKRDY_R { + CLKRDY_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +#[doc = "DPLL Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dpllstatus](index.html) module"] +pub struct DPLLSTATUS_SPEC; +impl crate::RegisterSpec for DPLLSTATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dpllstatus::R](R) reader structure"] +impl crate::Readable for DPLLSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DPLLSTATUS to value 0"] +impl crate::Resettable for DPLLSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/oscctrl/dpllsyncbusy.rs b/pac/atsamc20g/src/oscctrl/dpllsyncbusy.rs new file mode 100644 index 000000000000..f9fb880a5a59 --- /dev/null +++ b/pac/atsamc20g/src/oscctrl/dpllsyncbusy.rs @@ -0,0 +1,93 @@ +#[doc = "Register `DPLLSYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `ENABLE` reader - DPLL Enable Synchronization Status"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLRATIO` reader - DPLL Ratio Synchronization Status"] +pub struct DPLLRATIO_R(crate::FieldReader); +impl DPLLRATIO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLRATIO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLRATIO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLPRESC` reader - DPLL Prescaler Synchronization Status"] +pub struct DPLLPRESC_R(crate::FieldReader); +impl DPLLPRESC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLPRESC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLPRESC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 1 - DPLL Enable Synchronization Status"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - DPLL Ratio Synchronization Status"] + #[inline(always)] + pub fn dpllratio(&self) -> DPLLRATIO_R { + DPLLRATIO_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - DPLL Prescaler Synchronization Status"] + #[inline(always)] + pub fn dpllpresc(&self) -> DPLLPRESC_R { + DPLLPRESC_R::new(((self.bits >> 3) & 0x01) != 0) + } +} +#[doc = "DPLL Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dpllsyncbusy](index.html) module"] +pub struct DPLLSYNCBUSY_SPEC; +impl crate::RegisterSpec for DPLLSYNCBUSY_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dpllsyncbusy::R](R) reader structure"] +impl crate::Readable for DPLLSYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DPLLSYNCBUSY to value 0"] +impl crate::Resettable for DPLLSYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/oscctrl/evctrl.rs b/pac/atsamc20g/src/oscctrl/evctrl.rs new file mode 100644 index 000000000000..e22ba62f0fe2 --- /dev/null +++ b/pac/atsamc20g/src/oscctrl/evctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CFDEO` reader - Clock Failure Detector Event Output Enable"] +pub struct CFDEO_R(crate::FieldReader); +impl CFDEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFDEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFDEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFDEO` writer - Clock Failure Detector Event Output Enable"] +pub struct CFDEO_W<'a> { + w: &'a mut W, +} +impl<'a> CFDEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Clock Failure Detector Event Output Enable"] + #[inline(always)] + pub fn cfdeo(&self) -> CFDEO_R { + CFDEO_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Clock Failure Detector Event Output Enable"] + #[inline(always)] + pub fn cfdeo(&mut self) -> CFDEO_W { + CFDEO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/oscctrl/intenclr.rs b/pac/atsamc20g/src/oscctrl/intenclr.rs new file mode 100644 index 000000000000..0ea0034a0c02 --- /dev/null +++ b/pac/atsamc20g/src/oscctrl/intenclr.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XOSCRDY` reader - XOSC Ready Interrupt Enable"] +pub struct XOSCRDY_R(crate::FieldReader); +impl XOSCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSCRDY` writer - XOSC Ready Interrupt Enable"] +pub struct XOSCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> XOSCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `XOSCFAIL` reader - XOSC Clock Failure Detector Interrupt Enable"] +pub struct XOSCFAIL_R(crate::FieldReader); +impl XOSCFAIL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSCFAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCFAIL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSCFAIL` writer - XOSC Clock Failure Detector Interrupt Enable"] +pub struct XOSCFAIL_W<'a> { + w: &'a mut W, +} +impl<'a> XOSCFAIL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `OSC48MRDY` reader - OSC48M Ready Interrupt Enable"] +pub struct OSC48MRDY_R(crate::FieldReader); +impl OSC48MRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC48MRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC48MRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC48MRDY` writer - OSC48M Ready Interrupt Enable"] +pub struct OSC48MRDY_W<'a> { + w: &'a mut W, +} +impl<'a> OSC48MRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `DPLLLCKR` reader - DPLL Lock Rise Interrupt Enable"] +pub struct DPLLLCKR_R(crate::FieldReader); +impl DPLLLCKR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKR` writer - DPLL Lock Rise Interrupt Enable"] +pub struct DPLLLCKR_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLCKR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `DPLLLCKF` reader - DPLL Lock Fall Interrupt Enable"] +pub struct DPLLLCKF_R(crate::FieldReader); +impl DPLLLCKF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKF` writer - DPLL Lock Fall Interrupt Enable"] +pub struct DPLLLCKF_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLCKF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `DPLLLTO` reader - DPLL Time Out Interrupt Enable"] +pub struct DPLLLTO_R(crate::FieldReader); +impl DPLLLTO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLTO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLTO` writer - DPLL Time Out Interrupt Enable"] +pub struct DPLLLTO_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLTO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `DPLLLDRTO` reader - DPLL Ratio Ready Interrupt Enable"] +pub struct DPLLLDRTO_R(crate::FieldReader); +impl DPLLLDRTO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLDRTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLDRTO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLDRTO` writer - DPLL Ratio Ready Interrupt Enable"] +pub struct DPLLLDRTO_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLDRTO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +impl R { + #[doc = "Bit 0 - XOSC Ready Interrupt Enable"] + #[inline(always)] + pub fn xoscrdy(&self) -> XOSCRDY_R { + XOSCRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - XOSC Clock Failure Detector Interrupt Enable"] + #[inline(always)] + pub fn xoscfail(&self) -> XOSCFAIL_R { + XOSCFAIL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - OSC48M Ready Interrupt Enable"] + #[inline(always)] + pub fn osc48mrdy(&self) -> OSC48MRDY_R { + OSC48MRDY_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 8 - DPLL Lock Rise Interrupt Enable"] + #[inline(always)] + pub fn dplllckr(&self) -> DPLLLCKR_R { + DPLLLCKR_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - DPLL Lock Fall Interrupt Enable"] + #[inline(always)] + pub fn dplllckf(&self) -> DPLLLCKF_R { + DPLLLCKF_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - DPLL Time Out Interrupt Enable"] + #[inline(always)] + pub fn dplllto(&self) -> DPLLLTO_R { + DPLLLTO_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - DPLL Ratio Ready Interrupt Enable"] + #[inline(always)] + pub fn dpllldrto(&self) -> DPLLLDRTO_R { + DPLLLDRTO_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - XOSC Ready Interrupt Enable"] + #[inline(always)] + pub fn xoscrdy(&mut self) -> XOSCRDY_W { + XOSCRDY_W { w: self } + } + #[doc = "Bit 1 - XOSC Clock Failure Detector Interrupt Enable"] + #[inline(always)] + pub fn xoscfail(&mut self) -> XOSCFAIL_W { + XOSCFAIL_W { w: self } + } + #[doc = "Bit 4 - OSC48M Ready Interrupt Enable"] + #[inline(always)] + pub fn osc48mrdy(&mut self) -> OSC48MRDY_W { + OSC48MRDY_W { w: self } + } + #[doc = "Bit 8 - DPLL Lock Rise Interrupt Enable"] + #[inline(always)] + pub fn dplllckr(&mut self) -> DPLLLCKR_W { + DPLLLCKR_W { w: self } + } + #[doc = "Bit 9 - DPLL Lock Fall Interrupt Enable"] + #[inline(always)] + pub fn dplllckf(&mut self) -> DPLLLCKF_W { + DPLLLCKF_W { w: self } + } + #[doc = "Bit 10 - DPLL Time Out Interrupt Enable"] + #[inline(always)] + pub fn dplllto(&mut self) -> DPLLLTO_W { + DPLLLTO_W { w: self } + } + #[doc = "Bit 11 - DPLL Ratio Ready Interrupt Enable"] + #[inline(always)] + pub fn dpllldrto(&mut self) -> DPLLLDRTO_W { + DPLLLDRTO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/oscctrl/intenset.rs b/pac/atsamc20g/src/oscctrl/intenset.rs new file mode 100644 index 000000000000..2890541e4414 --- /dev/null +++ b/pac/atsamc20g/src/oscctrl/intenset.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XOSCRDY` reader - XOSC Ready Interrupt Enable"] +pub struct XOSCRDY_R(crate::FieldReader); +impl XOSCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSCRDY` writer - XOSC Ready Interrupt Enable"] +pub struct XOSCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> XOSCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `XOSCFAIL` reader - XOSC Clock Failure Detector Interrupt Enable"] +pub struct XOSCFAIL_R(crate::FieldReader); +impl XOSCFAIL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSCFAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCFAIL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSCFAIL` writer - XOSC Clock Failure Detector Interrupt Enable"] +pub struct XOSCFAIL_W<'a> { + w: &'a mut W, +} +impl<'a> XOSCFAIL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `OSC48MRDY` reader - OSC48M Ready Interrupt Enable"] +pub struct OSC48MRDY_R(crate::FieldReader); +impl OSC48MRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC48MRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC48MRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC48MRDY` writer - OSC48M Ready Interrupt Enable"] +pub struct OSC48MRDY_W<'a> { + w: &'a mut W, +} +impl<'a> OSC48MRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `DPLLLCKR` reader - DPLL Lock Rise Interrupt Enable"] +pub struct DPLLLCKR_R(crate::FieldReader); +impl DPLLLCKR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKR` writer - DPLL Lock Rise Interrupt Enable"] +pub struct DPLLLCKR_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLCKR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `DPLLLCKF` reader - DPLL Lock Fall Interrupt Enable"] +pub struct DPLLLCKF_R(crate::FieldReader); +impl DPLLLCKF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKF` writer - DPLL Lock Fall Interrupt Enable"] +pub struct DPLLLCKF_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLCKF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `DPLLLTO` reader - DPLL Time Out Interrupt Enable"] +pub struct DPLLLTO_R(crate::FieldReader); +impl DPLLLTO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLTO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLTO` writer - DPLL Time Out Interrupt Enable"] +pub struct DPLLLTO_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLTO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `DPLLLDRTO` reader - DPLL Ratio Ready Interrupt Enable"] +pub struct DPLLLDRTO_R(crate::FieldReader); +impl DPLLLDRTO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLDRTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLDRTO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLDRTO` writer - DPLL Ratio Ready Interrupt Enable"] +pub struct DPLLLDRTO_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLDRTO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +impl R { + #[doc = "Bit 0 - XOSC Ready Interrupt Enable"] + #[inline(always)] + pub fn xoscrdy(&self) -> XOSCRDY_R { + XOSCRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - XOSC Clock Failure Detector Interrupt Enable"] + #[inline(always)] + pub fn xoscfail(&self) -> XOSCFAIL_R { + XOSCFAIL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - OSC48M Ready Interrupt Enable"] + #[inline(always)] + pub fn osc48mrdy(&self) -> OSC48MRDY_R { + OSC48MRDY_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 8 - DPLL Lock Rise Interrupt Enable"] + #[inline(always)] + pub fn dplllckr(&self) -> DPLLLCKR_R { + DPLLLCKR_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - DPLL Lock Fall Interrupt Enable"] + #[inline(always)] + pub fn dplllckf(&self) -> DPLLLCKF_R { + DPLLLCKF_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - DPLL Time Out Interrupt Enable"] + #[inline(always)] + pub fn dplllto(&self) -> DPLLLTO_R { + DPLLLTO_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - DPLL Ratio Ready Interrupt Enable"] + #[inline(always)] + pub fn dpllldrto(&self) -> DPLLLDRTO_R { + DPLLLDRTO_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - XOSC Ready Interrupt Enable"] + #[inline(always)] + pub fn xoscrdy(&mut self) -> XOSCRDY_W { + XOSCRDY_W { w: self } + } + #[doc = "Bit 1 - XOSC Clock Failure Detector Interrupt Enable"] + #[inline(always)] + pub fn xoscfail(&mut self) -> XOSCFAIL_W { + XOSCFAIL_W { w: self } + } + #[doc = "Bit 4 - OSC48M Ready Interrupt Enable"] + #[inline(always)] + pub fn osc48mrdy(&mut self) -> OSC48MRDY_W { + OSC48MRDY_W { w: self } + } + #[doc = "Bit 8 - DPLL Lock Rise Interrupt Enable"] + #[inline(always)] + pub fn dplllckr(&mut self) -> DPLLLCKR_W { + DPLLLCKR_W { w: self } + } + #[doc = "Bit 9 - DPLL Lock Fall Interrupt Enable"] + #[inline(always)] + pub fn dplllckf(&mut self) -> DPLLLCKF_W { + DPLLLCKF_W { w: self } + } + #[doc = "Bit 10 - DPLL Time Out Interrupt Enable"] + #[inline(always)] + pub fn dplllto(&mut self) -> DPLLLTO_W { + DPLLLTO_W { w: self } + } + #[doc = "Bit 11 - DPLL Ratio Ready Interrupt Enable"] + #[inline(always)] + pub fn dpllldrto(&mut self) -> DPLLLDRTO_W { + DPLLLDRTO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/oscctrl/intflag.rs b/pac/atsamc20g/src/oscctrl/intflag.rs new file mode 100644 index 000000000000..71e452a1b571 --- /dev/null +++ b/pac/atsamc20g/src/oscctrl/intflag.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XOSCRDY` reader - XOSC Ready"] +pub struct XOSCRDY_R(crate::FieldReader); +impl XOSCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSCRDY` writer - XOSC Ready"] +pub struct XOSCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> XOSCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `XOSCFAIL` reader - XOSC Clock Failure Detector"] +pub struct XOSCFAIL_R(crate::FieldReader); +impl XOSCFAIL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSCFAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCFAIL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSCFAIL` writer - XOSC Clock Failure Detector"] +pub struct XOSCFAIL_W<'a> { + w: &'a mut W, +} +impl<'a> XOSCFAIL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `OSC48MRDY` reader - OSC48M Ready"] +pub struct OSC48MRDY_R(crate::FieldReader); +impl OSC48MRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC48MRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC48MRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC48MRDY` writer - OSC48M Ready"] +pub struct OSC48MRDY_W<'a> { + w: &'a mut W, +} +impl<'a> OSC48MRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `DPLLLCKR` reader - DPLL Lock Rise"] +pub struct DPLLLCKR_R(crate::FieldReader); +impl DPLLLCKR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKR` writer - DPLL Lock Rise"] +pub struct DPLLLCKR_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLCKR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `DPLLLCKF` reader - DPLL Lock Fall"] +pub struct DPLLLCKF_R(crate::FieldReader); +impl DPLLLCKF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKF` writer - DPLL Lock Fall"] +pub struct DPLLLCKF_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLCKF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `DPLLLTO` reader - DPLL Timeout"] +pub struct DPLLLTO_R(crate::FieldReader); +impl DPLLLTO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLTO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLTO` writer - DPLL Timeout"] +pub struct DPLLLTO_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLTO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `DPLLLDRTO` reader - DPLL Ratio Ready"] +pub struct DPLLLDRTO_R(crate::FieldReader); +impl DPLLLDRTO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLDRTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLDRTO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLDRTO` writer - DPLL Ratio Ready"] +pub struct DPLLLDRTO_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLDRTO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +impl R { + #[doc = "Bit 0 - XOSC Ready"] + #[inline(always)] + pub fn xoscrdy(&self) -> XOSCRDY_R { + XOSCRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - XOSC Clock Failure Detector"] + #[inline(always)] + pub fn xoscfail(&self) -> XOSCFAIL_R { + XOSCFAIL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - OSC48M Ready"] + #[inline(always)] + pub fn osc48mrdy(&self) -> OSC48MRDY_R { + OSC48MRDY_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 8 - DPLL Lock Rise"] + #[inline(always)] + pub fn dplllckr(&self) -> DPLLLCKR_R { + DPLLLCKR_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - DPLL Lock Fall"] + #[inline(always)] + pub fn dplllckf(&self) -> DPLLLCKF_R { + DPLLLCKF_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - DPLL Timeout"] + #[inline(always)] + pub fn dplllto(&self) -> DPLLLTO_R { + DPLLLTO_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - DPLL Ratio Ready"] + #[inline(always)] + pub fn dpllldrto(&self) -> DPLLLDRTO_R { + DPLLLDRTO_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - XOSC Ready"] + #[inline(always)] + pub fn xoscrdy(&mut self) -> XOSCRDY_W { + XOSCRDY_W { w: self } + } + #[doc = "Bit 1 - XOSC Clock Failure Detector"] + #[inline(always)] + pub fn xoscfail(&mut self) -> XOSCFAIL_W { + XOSCFAIL_W { w: self } + } + #[doc = "Bit 4 - OSC48M Ready"] + #[inline(always)] + pub fn osc48mrdy(&mut self) -> OSC48MRDY_W { + OSC48MRDY_W { w: self } + } + #[doc = "Bit 8 - DPLL Lock Rise"] + #[inline(always)] + pub fn dplllckr(&mut self) -> DPLLLCKR_W { + DPLLLCKR_W { w: self } + } + #[doc = "Bit 9 - DPLL Lock Fall"] + #[inline(always)] + pub fn dplllckf(&mut self) -> DPLLLCKF_W { + DPLLLCKF_W { w: self } + } + #[doc = "Bit 10 - DPLL Timeout"] + #[inline(always)] + pub fn dplllto(&mut self) -> DPLLLTO_W { + DPLLLTO_W { w: self } + } + #[doc = "Bit 11 - DPLL Ratio Ready"] + #[inline(always)] + pub fn dpllldrto(&mut self) -> DPLLLDRTO_W { + DPLLLDRTO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/oscctrl/osc48mctrl.rs b/pac/atsamc20g/src/oscctrl/osc48mctrl.rs new file mode 100644 index 000000000000..8314e21e5775 --- /dev/null +++ b/pac/atsamc20g/src/oscctrl/osc48mctrl.rs @@ -0,0 +1,207 @@ +#[doc = "Register `OSC48MCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OSC48MCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Oscillator Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Oscillator Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - On Demand Control"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - On Demand Control"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "48MHz Internal Oscillator (OSC48M) Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [osc48mctrl](index.html) module"] +pub struct OSC48MCTRL_SPEC; +impl crate::RegisterSpec for OSC48MCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [osc48mctrl::R](R) reader structure"] +impl crate::Readable for OSC48MCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [osc48mctrl::W](W) writer structure"] +impl crate::Writable for OSC48MCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OSC48MCTRL to value 0x82"] +impl crate::Resettable for OSC48MCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x82 + } +} diff --git a/pac/atsamc20g/src/oscctrl/osc48mdiv.rs b/pac/atsamc20g/src/oscctrl/osc48mdiv.rs new file mode 100644 index 000000000000..4ed854b09284 --- /dev/null +++ b/pac/atsamc20g/src/oscctrl/osc48mdiv.rs @@ -0,0 +1,334 @@ +#[doc = "Register `OSC48MDIV` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OSC48MDIV` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "OSC48M Division Factor\n\nValue on reset: 11"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DIV_A { + #[doc = "0: 48 MHz"] + DIV1 = 0, + #[doc = "1: 24 MHz"] + DIV2 = 1, + #[doc = "2: 16 MHz"] + DIV3 = 2, + #[doc = "3: 12 MHz"] + DIV4 = 3, + #[doc = "4: 9.6 MHz"] + DIV5 = 4, + #[doc = "5: 8 MHz"] + DIV6 = 5, + #[doc = "6: 6.86 MHz"] + DIV7 = 6, + #[doc = "7: 6 MHz"] + DIV8 = 7, + #[doc = "8: 5.33 MHz"] + DIV9 = 8, + #[doc = "9: 4.8 MHz"] + DIV10 = 9, + #[doc = "10: 4.36 MHz"] + DIV11 = 10, + #[doc = "11: 4 MHz"] + DIV12 = 11, + #[doc = "12: 3.69 MHz"] + DIV13 = 12, + #[doc = "13: 3.43 MHz"] + DIV14 = 13, + #[doc = "14: 3.2 MHz"] + DIV15 = 14, + #[doc = "15: 3 MHz"] + DIV16 = 15, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DIV_A) -> Self { + variant as _ + } +} +#[doc = "Field `DIV` reader - OSC48M Division Factor"] +pub struct DIV_R(crate::FieldReader); +impl DIV_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DIV_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DIV_A { + match self.bits { + 0 => DIV_A::DIV1, + 1 => DIV_A::DIV2, + 2 => DIV_A::DIV3, + 3 => DIV_A::DIV4, + 4 => DIV_A::DIV5, + 5 => DIV_A::DIV6, + 6 => DIV_A::DIV7, + 7 => DIV_A::DIV8, + 8 => DIV_A::DIV9, + 9 => DIV_A::DIV10, + 10 => DIV_A::DIV11, + 11 => DIV_A::DIV12, + 12 => DIV_A::DIV13, + 13 => DIV_A::DIV14, + 14 => DIV_A::DIV15, + 15 => DIV_A::DIV16, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == DIV_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == DIV_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV3`"] + #[inline(always)] + pub fn is_div3(&self) -> bool { + **self == DIV_A::DIV3 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == DIV_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV5`"] + #[inline(always)] + pub fn is_div5(&self) -> bool { + **self == DIV_A::DIV5 + } + #[doc = "Checks if the value of the field is `DIV6`"] + #[inline(always)] + pub fn is_div6(&self) -> bool { + **self == DIV_A::DIV6 + } + #[doc = "Checks if the value of the field is `DIV7`"] + #[inline(always)] + pub fn is_div7(&self) -> bool { + **self == DIV_A::DIV7 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == DIV_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV9`"] + #[inline(always)] + pub fn is_div9(&self) -> bool { + **self == DIV_A::DIV9 + } + #[doc = "Checks if the value of the field is `DIV10`"] + #[inline(always)] + pub fn is_div10(&self) -> bool { + **self == DIV_A::DIV10 + } + #[doc = "Checks if the value of the field is `DIV11`"] + #[inline(always)] + pub fn is_div11(&self) -> bool { + **self == DIV_A::DIV11 + } + #[doc = "Checks if the value of the field is `DIV12`"] + #[inline(always)] + pub fn is_div12(&self) -> bool { + **self == DIV_A::DIV12 + } + #[doc = "Checks if the value of the field is `DIV13`"] + #[inline(always)] + pub fn is_div13(&self) -> bool { + **self == DIV_A::DIV13 + } + #[doc = "Checks if the value of the field is `DIV14`"] + #[inline(always)] + pub fn is_div14(&self) -> bool { + **self == DIV_A::DIV14 + } + #[doc = "Checks if the value of the field is `DIV15`"] + #[inline(always)] + pub fn is_div15(&self) -> bool { + **self == DIV_A::DIV15 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == DIV_A::DIV16 + } +} +impl core::ops::Deref for DIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIV` writer - OSC48M Division Factor"] +pub struct DIV_W<'a> { + w: &'a mut W, +} +impl<'a> DIV_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DIV_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "48 MHz"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(DIV_A::DIV1) + } + #[doc = "24 MHz"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(DIV_A::DIV2) + } + #[doc = "16 MHz"] + #[inline(always)] + pub fn div3(self) -> &'a mut W { + self.variant(DIV_A::DIV3) + } + #[doc = "12 MHz"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(DIV_A::DIV4) + } + #[doc = "9.6 MHz"] + #[inline(always)] + pub fn div5(self) -> &'a mut W { + self.variant(DIV_A::DIV5) + } + #[doc = "8 MHz"] + #[inline(always)] + pub fn div6(self) -> &'a mut W { + self.variant(DIV_A::DIV6) + } + #[doc = "6.86 MHz"] + #[inline(always)] + pub fn div7(self) -> &'a mut W { + self.variant(DIV_A::DIV7) + } + #[doc = "6 MHz"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(DIV_A::DIV8) + } + #[doc = "5.33 MHz"] + #[inline(always)] + pub fn div9(self) -> &'a mut W { + self.variant(DIV_A::DIV9) + } + #[doc = "4.8 MHz"] + #[inline(always)] + pub fn div10(self) -> &'a mut W { + self.variant(DIV_A::DIV10) + } + #[doc = "4.36 MHz"] + #[inline(always)] + pub fn div11(self) -> &'a mut W { + self.variant(DIV_A::DIV11) + } + #[doc = "4 MHz"] + #[inline(always)] + pub fn div12(self) -> &'a mut W { + self.variant(DIV_A::DIV12) + } + #[doc = "3.69 MHz"] + #[inline(always)] + pub fn div13(self) -> &'a mut W { + self.variant(DIV_A::DIV13) + } + #[doc = "3.43 MHz"] + #[inline(always)] + pub fn div14(self) -> &'a mut W { + self.variant(DIV_A::DIV14) + } + #[doc = "3.2 MHz"] + #[inline(always)] + pub fn div15(self) -> &'a mut W { + self.variant(DIV_A::DIV15) + } + #[doc = "3 MHz"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(DIV_A::DIV16) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - OSC48M Division Factor"] + #[inline(always)] + pub fn div(&self) -> DIV_R { + DIV_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - OSC48M Division Factor"] + #[inline(always)] + pub fn div(&mut self) -> DIV_W { + DIV_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OSC48M Divider\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [osc48mdiv](index.html) module"] +pub struct OSC48MDIV_SPEC; +impl crate::RegisterSpec for OSC48MDIV_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [osc48mdiv::R](R) reader structure"] +impl crate::Readable for OSC48MDIV_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [osc48mdiv::W](W) writer structure"] +impl crate::Writable for OSC48MDIV_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OSC48MDIV to value 0x0b"] +impl crate::Resettable for OSC48MDIV_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0b + } +} diff --git a/pac/atsamc20g/src/oscctrl/osc48mstup.rs b/pac/atsamc20g/src/oscctrl/osc48mstup.rs new file mode 100644 index 000000000000..34da6bb7ef11 --- /dev/null +++ b/pac/atsamc20g/src/oscctrl/osc48mstup.rs @@ -0,0 +1,230 @@ +#[doc = "Register `OSC48MSTUP` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OSC48MSTUP` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Startup Time\n\nValue on reset: 7"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum STARTUP_A { + #[doc = "0: 166 ns"] + CYCLE8 = 0, + #[doc = "1: 333 ns"] + CYCLE16 = 1, + #[doc = "2: 667 ns"] + CYCLE32 = 2, + #[doc = "3: 1.333 us"] + CYCLE64 = 3, + #[doc = "4: 2.667 us"] + CYCLE128 = 4, + #[doc = "5: 5.333 us"] + CYCLE256 = 5, + #[doc = "6: 10.667 us"] + CYCLE512 = 6, + #[doc = "7: 21.333 us"] + CYCLE1024 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: STARTUP_A) -> Self { + variant as _ + } +} +#[doc = "Field `STARTUP` reader - Startup Time"] +pub struct STARTUP_R(crate::FieldReader); +impl STARTUP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + STARTUP_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STARTUP_A { + match self.bits { + 0 => STARTUP_A::CYCLE8, + 1 => STARTUP_A::CYCLE16, + 2 => STARTUP_A::CYCLE32, + 3 => STARTUP_A::CYCLE64, + 4 => STARTUP_A::CYCLE128, + 5 => STARTUP_A::CYCLE256, + 6 => STARTUP_A::CYCLE512, + 7 => STARTUP_A::CYCLE1024, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `CYCLE8`"] + #[inline(always)] + pub fn is_cycle8(&self) -> bool { + **self == STARTUP_A::CYCLE8 + } + #[doc = "Checks if the value of the field is `CYCLE16`"] + #[inline(always)] + pub fn is_cycle16(&self) -> bool { + **self == STARTUP_A::CYCLE16 + } + #[doc = "Checks if the value of the field is `CYCLE32`"] + #[inline(always)] + pub fn is_cycle32(&self) -> bool { + **self == STARTUP_A::CYCLE32 + } + #[doc = "Checks if the value of the field is `CYCLE64`"] + #[inline(always)] + pub fn is_cycle64(&self) -> bool { + **self == STARTUP_A::CYCLE64 + } + #[doc = "Checks if the value of the field is `CYCLE128`"] + #[inline(always)] + pub fn is_cycle128(&self) -> bool { + **self == STARTUP_A::CYCLE128 + } + #[doc = "Checks if the value of the field is `CYCLE256`"] + #[inline(always)] + pub fn is_cycle256(&self) -> bool { + **self == STARTUP_A::CYCLE256 + } + #[doc = "Checks if the value of the field is `CYCLE512`"] + #[inline(always)] + pub fn is_cycle512(&self) -> bool { + **self == STARTUP_A::CYCLE512 + } + #[doc = "Checks if the value of the field is `CYCLE1024`"] + #[inline(always)] + pub fn is_cycle1024(&self) -> bool { + **self == STARTUP_A::CYCLE1024 + } +} +impl core::ops::Deref for STARTUP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STARTUP` writer - Startup Time"] +pub struct STARTUP_W<'a> { + w: &'a mut W, +} +impl<'a> STARTUP_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: STARTUP_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "166 ns"] + #[inline(always)] + pub fn cycle8(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE8) + } + #[doc = "333 ns"] + #[inline(always)] + pub fn cycle16(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE16) + } + #[doc = "667 ns"] + #[inline(always)] + pub fn cycle32(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE32) + } + #[doc = "1.333 us"] + #[inline(always)] + pub fn cycle64(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE64) + } + #[doc = "2.667 us"] + #[inline(always)] + pub fn cycle128(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE128) + } + #[doc = "5.333 us"] + #[inline(always)] + pub fn cycle256(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE256) + } + #[doc = "10.667 us"] + #[inline(always)] + pub fn cycle512(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE512) + } + #[doc = "21.333 us"] + #[inline(always)] + pub fn cycle1024(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Startup Time"] + #[inline(always)] + pub fn startup(&self) -> STARTUP_R { + STARTUP_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Startup Time"] + #[inline(always)] + pub fn startup(&mut self) -> STARTUP_W { + STARTUP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OSC48M Startup Time\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [osc48mstup](index.html) module"] +pub struct OSC48MSTUP_SPEC; +impl crate::RegisterSpec for OSC48MSTUP_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [osc48mstup::R](R) reader structure"] +impl crate::Readable for OSC48MSTUP_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [osc48mstup::W](W) writer structure"] +impl crate::Writable for OSC48MSTUP_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OSC48MSTUP to value 0x07"] +impl crate::Resettable for OSC48MSTUP_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x07 + } +} diff --git a/pac/atsamc20g/src/oscctrl/osc48msyncbusy.rs b/pac/atsamc20g/src/oscctrl/osc48msyncbusy.rs new file mode 100644 index 000000000000..8d4410ae630a --- /dev/null +++ b/pac/atsamc20g/src/oscctrl/osc48msyncbusy.rs @@ -0,0 +1,53 @@ +#[doc = "Register `OSC48MSYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `OSC48MDIV` reader - OSC48MDIV Synchronization Status"] +pub struct OSC48MDIV_R(crate::FieldReader); +impl OSC48MDIV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC48MDIV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC48MDIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 2 - OSC48MDIV Synchronization Status"] + #[inline(always)] + pub fn osc48mdiv(&self) -> OSC48MDIV_R { + OSC48MDIV_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +#[doc = "OSC48M Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [osc48msyncbusy](index.html) module"] +pub struct OSC48MSYNCBUSY_SPEC; +impl crate::RegisterSpec for OSC48MSYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [osc48msyncbusy::R](R) reader structure"] +impl crate::Readable for OSC48MSYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets OSC48MSYNCBUSY to value 0"] +impl crate::Resettable for OSC48MSYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/oscctrl/status.rs b/pac/atsamc20g/src/oscctrl/status.rs new file mode 100644 index 000000000000..3025966192a3 --- /dev/null +++ b/pac/atsamc20g/src/oscctrl/status.rs @@ -0,0 +1,193 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `XOSCRDY` reader - XOSC Ready"] +pub struct XOSCRDY_R(crate::FieldReader); +impl XOSCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSCFAIL` reader - XOSC Clock Failure Detector"] +pub struct XOSCFAIL_R(crate::FieldReader); +impl XOSCFAIL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSCFAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCFAIL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSCCKSW` reader - XOSC Clock Switch"] +pub struct XOSCCKSW_R(crate::FieldReader); +impl XOSCCKSW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSCCKSW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCCKSW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC48MRDY` reader - OSC48M Ready"] +pub struct OSC48MRDY_R(crate::FieldReader); +impl OSC48MRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC48MRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC48MRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKR` reader - DPLL Lock Rise"] +pub struct DPLLLCKR_R(crate::FieldReader); +impl DPLLLCKR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKF` reader - DPLL Lock Fall"] +pub struct DPLLLCKF_R(crate::FieldReader); +impl DPLLLCKF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLTO` reader - DPLL Timeout"] +pub struct DPLLTO_R(crate::FieldReader); +impl DPLLTO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLTO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLDRTO` reader - DPLL Ratio Ready"] +pub struct DPLLLDRTO_R(crate::FieldReader); +impl DPLLLDRTO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLDRTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLDRTO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - XOSC Ready"] + #[inline(always)] + pub fn xoscrdy(&self) -> XOSCRDY_R { + XOSCRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - XOSC Clock Failure Detector"] + #[inline(always)] + pub fn xoscfail(&self) -> XOSCFAIL_R { + XOSCFAIL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - XOSC Clock Switch"] + #[inline(always)] + pub fn xosccksw(&self) -> XOSCCKSW_R { + XOSCCKSW_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 4 - OSC48M Ready"] + #[inline(always)] + pub fn osc48mrdy(&self) -> OSC48MRDY_R { + OSC48MRDY_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 8 - DPLL Lock Rise"] + #[inline(always)] + pub fn dplllckr(&self) -> DPLLLCKR_R { + DPLLLCKR_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - DPLL Lock Fall"] + #[inline(always)] + pub fn dplllckf(&self) -> DPLLLCKF_R { + DPLLLCKF_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - DPLL Timeout"] + #[inline(always)] + pub fn dpllto(&self) -> DPLLTO_R { + DPLLTO_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - DPLL Ratio Ready"] + #[inline(always)] + pub fn dpllldrto(&self) -> DPLLLDRTO_R { + DPLLLDRTO_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +#[doc = "Power and Clocks Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/oscctrl/xoscctrl.rs b/pac/atsamc20g/src/oscctrl/xoscctrl.rs new file mode 100644 index 000000000000..3a5319565c10 --- /dev/null +++ b/pac/atsamc20g/src/oscctrl/xoscctrl.rs @@ -0,0 +1,788 @@ +#[doc = "Register `XOSCCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `XOSCCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Oscillator Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Oscillator Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `XTALEN` reader - Crystal Oscillator Enable"] +pub struct XTALEN_R(crate::FieldReader); +impl XTALEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XTALEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XTALEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XTALEN` writer - Crystal Oscillator Enable"] +pub struct XTALEN_W<'a> { + w: &'a mut W, +} +impl<'a> XTALEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CFDEN` reader - Xosc Clock Failure Detector Enable"] +pub struct CFDEN_R(crate::FieldReader); +impl CFDEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFDEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFDEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFDEN` writer - Xosc Clock Failure Detector Enable"] +pub struct CFDEN_W<'a> { + w: &'a mut W, +} +impl<'a> CFDEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `SWBEN` reader - Xosc Clock Switch Enable"] +pub struct SWBEN_R(crate::FieldReader); +impl SWBEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWBEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWBEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWBEN` writer - Xosc Clock Switch Enable"] +pub struct SWBEN_W<'a> { + w: &'a mut W, +} +impl<'a> SWBEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - On Demand Control"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - On Demand Control"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Oscillator Gain\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum GAIN_A { + #[doc = "0: 2 MHz"] + GAIN2 = 0, + #[doc = "1: 4 MHz"] + GAIN4 = 1, + #[doc = "2: 8 MHz"] + GAIN8 = 2, + #[doc = "3: 16 MHz"] + GAIN16 = 3, + #[doc = "4: 30 MHz"] + GAIN30 = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: GAIN_A) -> Self { + variant as _ + } +} +#[doc = "Field `GAIN` reader - Oscillator Gain"] +pub struct GAIN_R(crate::FieldReader); +impl GAIN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + GAIN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(GAIN_A::GAIN2), + 1 => Some(GAIN_A::GAIN4), + 2 => Some(GAIN_A::GAIN8), + 3 => Some(GAIN_A::GAIN16), + 4 => Some(GAIN_A::GAIN30), + _ => None, + } + } + #[doc = "Checks if the value of the field is `GAIN2`"] + #[inline(always)] + pub fn is_gain2(&self) -> bool { + **self == GAIN_A::GAIN2 + } + #[doc = "Checks if the value of the field is `GAIN4`"] + #[inline(always)] + pub fn is_gain4(&self) -> bool { + **self == GAIN_A::GAIN4 + } + #[doc = "Checks if the value of the field is `GAIN8`"] + #[inline(always)] + pub fn is_gain8(&self) -> bool { + **self == GAIN_A::GAIN8 + } + #[doc = "Checks if the value of the field is `GAIN16`"] + #[inline(always)] + pub fn is_gain16(&self) -> bool { + **self == GAIN_A::GAIN16 + } + #[doc = "Checks if the value of the field is `GAIN30`"] + #[inline(always)] + pub fn is_gain30(&self) -> bool { + **self == GAIN_A::GAIN30 + } +} +impl core::ops::Deref for GAIN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GAIN` writer - Oscillator Gain"] +pub struct GAIN_W<'a> { + w: &'a mut W, +} +impl<'a> GAIN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: GAIN_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "2 MHz"] + #[inline(always)] + pub fn gain2(self) -> &'a mut W { + self.variant(GAIN_A::GAIN2) + } + #[doc = "4 MHz"] + #[inline(always)] + pub fn gain4(self) -> &'a mut W { + self.variant(GAIN_A::GAIN4) + } + #[doc = "8 MHz"] + #[inline(always)] + pub fn gain8(self) -> &'a mut W { + self.variant(GAIN_A::GAIN8) + } + #[doc = "16 MHz"] + #[inline(always)] + pub fn gain16(self) -> &'a mut W { + self.variant(GAIN_A::GAIN16) + } + #[doc = "30 MHz"] + #[inline(always)] + pub fn gain30(self) -> &'a mut W { + self.variant(GAIN_A::GAIN30) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u16 & 0x07) << 8); + self.w + } +} +#[doc = "Field `AMPGC` reader - Automatic Amplitude Gain Control"] +pub struct AMPGC_R(crate::FieldReader); +impl AMPGC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AMPGC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AMPGC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AMPGC` writer - Automatic Amplitude Gain Control"] +pub struct AMPGC_W<'a> { + w: &'a mut W, +} +impl<'a> AMPGC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u16 & 0x01) << 11); + self.w + } +} +#[doc = "Start-Up Time\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum STARTUP_A { + #[doc = "0: 31 us"] + CYCLE1 = 0, + #[doc = "1: 61 us"] + CYCLE2 = 1, + #[doc = "2: 122 us"] + CYCLE4 = 2, + #[doc = "3: 244 us"] + CYCLE8 = 3, + #[doc = "4: 488 us"] + CYCLE16 = 4, + #[doc = "5: 977 us"] + CYCLE32 = 5, + #[doc = "6: 1953 us"] + CYCLE64 = 6, + #[doc = "7: 3906 us"] + CYCLE128 = 7, + #[doc = "8: 7813 us"] + CYCLE256 = 8, + #[doc = "9: 15625 us"] + CYCLE512 = 9, + #[doc = "10: 31250 us"] + CYCLE1024 = 10, + #[doc = "11: 62500 us"] + CYCLE2048 = 11, + #[doc = "12: 125000 us"] + CYCLE4096 = 12, + #[doc = "13: 250000 us"] + CYCLE8192 = 13, + #[doc = "14: 500000 us"] + CYCLE16384 = 14, + #[doc = "15: 1000000 us"] + CYCLE32768 = 15, +} +impl From for u8 { + #[inline(always)] + fn from(variant: STARTUP_A) -> Self { + variant as _ + } +} +#[doc = "Field `STARTUP` reader - Start-Up Time"] +pub struct STARTUP_R(crate::FieldReader); +impl STARTUP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + STARTUP_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STARTUP_A { + match self.bits { + 0 => STARTUP_A::CYCLE1, + 1 => STARTUP_A::CYCLE2, + 2 => STARTUP_A::CYCLE4, + 3 => STARTUP_A::CYCLE8, + 4 => STARTUP_A::CYCLE16, + 5 => STARTUP_A::CYCLE32, + 6 => STARTUP_A::CYCLE64, + 7 => STARTUP_A::CYCLE128, + 8 => STARTUP_A::CYCLE256, + 9 => STARTUP_A::CYCLE512, + 10 => STARTUP_A::CYCLE1024, + 11 => STARTUP_A::CYCLE2048, + 12 => STARTUP_A::CYCLE4096, + 13 => STARTUP_A::CYCLE8192, + 14 => STARTUP_A::CYCLE16384, + 15 => STARTUP_A::CYCLE32768, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `CYCLE1`"] + #[inline(always)] + pub fn is_cycle1(&self) -> bool { + **self == STARTUP_A::CYCLE1 + } + #[doc = "Checks if the value of the field is `CYCLE2`"] + #[inline(always)] + pub fn is_cycle2(&self) -> bool { + **self == STARTUP_A::CYCLE2 + } + #[doc = "Checks if the value of the field is `CYCLE4`"] + #[inline(always)] + pub fn is_cycle4(&self) -> bool { + **self == STARTUP_A::CYCLE4 + } + #[doc = "Checks if the value of the field is `CYCLE8`"] + #[inline(always)] + pub fn is_cycle8(&self) -> bool { + **self == STARTUP_A::CYCLE8 + } + #[doc = "Checks if the value of the field is `CYCLE16`"] + #[inline(always)] + pub fn is_cycle16(&self) -> bool { + **self == STARTUP_A::CYCLE16 + } + #[doc = "Checks if the value of the field is `CYCLE32`"] + #[inline(always)] + pub fn is_cycle32(&self) -> bool { + **self == STARTUP_A::CYCLE32 + } + #[doc = "Checks if the value of the field is `CYCLE64`"] + #[inline(always)] + pub fn is_cycle64(&self) -> bool { + **self == STARTUP_A::CYCLE64 + } + #[doc = "Checks if the value of the field is `CYCLE128`"] + #[inline(always)] + pub fn is_cycle128(&self) -> bool { + **self == STARTUP_A::CYCLE128 + } + #[doc = "Checks if the value of the field is `CYCLE256`"] + #[inline(always)] + pub fn is_cycle256(&self) -> bool { + **self == STARTUP_A::CYCLE256 + } + #[doc = "Checks if the value of the field is `CYCLE512`"] + #[inline(always)] + pub fn is_cycle512(&self) -> bool { + **self == STARTUP_A::CYCLE512 + } + #[doc = "Checks if the value of the field is `CYCLE1024`"] + #[inline(always)] + pub fn is_cycle1024(&self) -> bool { + **self == STARTUP_A::CYCLE1024 + } + #[doc = "Checks if the value of the field is `CYCLE2048`"] + #[inline(always)] + pub fn is_cycle2048(&self) -> bool { + **self == STARTUP_A::CYCLE2048 + } + #[doc = "Checks if the value of the field is `CYCLE4096`"] + #[inline(always)] + pub fn is_cycle4096(&self) -> bool { + **self == STARTUP_A::CYCLE4096 + } + #[doc = "Checks if the value of the field is `CYCLE8192`"] + #[inline(always)] + pub fn is_cycle8192(&self) -> bool { + **self == STARTUP_A::CYCLE8192 + } + #[doc = "Checks if the value of the field is `CYCLE16384`"] + #[inline(always)] + pub fn is_cycle16384(&self) -> bool { + **self == STARTUP_A::CYCLE16384 + } + #[doc = "Checks if the value of the field is `CYCLE32768`"] + #[inline(always)] + pub fn is_cycle32768(&self) -> bool { + **self == STARTUP_A::CYCLE32768 + } +} +impl core::ops::Deref for STARTUP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STARTUP` writer - Start-Up Time"] +pub struct STARTUP_W<'a> { + w: &'a mut W, +} +impl<'a> STARTUP_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: STARTUP_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "31 us"] + #[inline(always)] + pub fn cycle1(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE1) + } + #[doc = "61 us"] + #[inline(always)] + pub fn cycle2(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE2) + } + #[doc = "122 us"] + #[inline(always)] + pub fn cycle4(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE4) + } + #[doc = "244 us"] + #[inline(always)] + pub fn cycle8(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE8) + } + #[doc = "488 us"] + #[inline(always)] + pub fn cycle16(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE16) + } + #[doc = "977 us"] + #[inline(always)] + pub fn cycle32(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE32) + } + #[doc = "1953 us"] + #[inline(always)] + pub fn cycle64(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE64) + } + #[doc = "3906 us"] + #[inline(always)] + pub fn cycle128(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE128) + } + #[doc = "7813 us"] + #[inline(always)] + pub fn cycle256(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE256) + } + #[doc = "15625 us"] + #[inline(always)] + pub fn cycle512(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE512) + } + #[doc = "31250 us"] + #[inline(always)] + pub fn cycle1024(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE1024) + } + #[doc = "62500 us"] + #[inline(always)] + pub fn cycle2048(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE2048) + } + #[doc = "125000 us"] + #[inline(always)] + pub fn cycle4096(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE4096) + } + #[doc = "250000 us"] + #[inline(always)] + pub fn cycle8192(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE8192) + } + #[doc = "500000 us"] + #[inline(always)] + pub fn cycle16384(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE16384) + } + #[doc = "1000000 us"] + #[inline(always)] + pub fn cycle32768(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE32768) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 12)) | ((value as u16 & 0x0f) << 12); + self.w + } +} +impl R { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Crystal Oscillator Enable"] + #[inline(always)] + pub fn xtalen(&self) -> XTALEN_R { + XTALEN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Xosc Clock Failure Detector Enable"] + #[inline(always)] + pub fn cfden(&self) -> CFDEN_R { + CFDEN_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Xosc Clock Switch Enable"] + #[inline(always)] + pub fn swben(&self) -> SWBEN_R { + SWBEN_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Oscillator Gain"] + #[inline(always)] + pub fn gain(&self) -> GAIN_R { + GAIN_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 11 - Automatic Amplitude Gain Control"] + #[inline(always)] + pub fn ampgc(&self) -> AMPGC_R { + AMPGC_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bits 12:15 - Start-Up Time"] + #[inline(always)] + pub fn startup(&self) -> STARTUP_R { + STARTUP_R::new(((self.bits >> 12) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - Crystal Oscillator Enable"] + #[inline(always)] + pub fn xtalen(&mut self) -> XTALEN_W { + XTALEN_W { w: self } + } + #[doc = "Bit 3 - Xosc Clock Failure Detector Enable"] + #[inline(always)] + pub fn cfden(&mut self) -> CFDEN_W { + CFDEN_W { w: self } + } + #[doc = "Bit 4 - Xosc Clock Switch Enable"] + #[inline(always)] + pub fn swben(&mut self) -> SWBEN_W { + SWBEN_W { w: self } + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Bits 8:10 - Oscillator Gain"] + #[inline(always)] + pub fn gain(&mut self) -> GAIN_W { + GAIN_W { w: self } + } + #[doc = "Bit 11 - Automatic Amplitude Gain Control"] + #[inline(always)] + pub fn ampgc(&mut self) -> AMPGC_W { + AMPGC_W { w: self } + } + #[doc = "Bits 12:15 - Start-Up Time"] + #[inline(always)] + pub fn startup(&mut self) -> STARTUP_W { + STARTUP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "External Multipurpose Crystal Oscillator (XOSC) Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [xoscctrl](index.html) module"] +pub struct XOSCCTRL_SPEC; +impl crate::RegisterSpec for XOSCCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [xoscctrl::R](R) reader structure"] +impl crate::Readable for XOSCCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [xoscctrl::W](W) writer structure"] +impl crate::Writable for XOSCCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets XOSCCTRL to value 0x80"] +impl crate::Resettable for XOSCCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x80 + } +} diff --git a/pac/atsamc20g/src/pac.rs b/pac/atsamc20g/src/pac.rs new file mode 100644 index 000000000000..3e365e081945 --- /dev/null +++ b/pac/atsamc20g/src/pac.rs @@ -0,0 +1,73 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Write control"] + pub wrctrl: crate::Reg, + #[doc = "0x04 - Event control"] + pub evctrl: crate::Reg, + _reserved2: [u8; 0x03], + #[doc = "0x08 - Interrupt enable clear"] + pub intenclr: crate::Reg, + #[doc = "0x09 - Interrupt enable set"] + pub intenset: crate::Reg, + _reserved4: [u8; 0x06], + #[doc = "0x10 - Bridge interrupt flag status"] + pub intflagahb: crate::Reg, + #[doc = "0x14 - Peripheral interrupt flag status - Bridge A"] + pub intflaga: crate::Reg, + #[doc = "0x18 - Peripheral interrupt flag status - Bridge B"] + pub intflagb: crate::Reg, + #[doc = "0x1c - Peripheral interrupt flag status - Bridge C"] + pub intflagc: crate::Reg, + _reserved8: [u8; 0x14], + #[doc = "0x34 - Peripheral write protection status - Bridge A"] + pub statusa: crate::Reg, + #[doc = "0x38 - Peripheral write protection status - Bridge B"] + pub statusb: crate::Reg, + #[doc = "0x3c - Peripheral write protection status - Bridge C"] + pub statusc: crate::Reg, +} +#[doc = "WRCTRL register accessor: an alias for `Reg`"] +pub type WRCTRL = crate::Reg; +#[doc = "Write control"] +pub mod wrctrl; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt enable clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt enable set"] +pub mod intenset; +#[doc = "INTFLAGAHB register accessor: an alias for `Reg`"] +pub type INTFLAGAHB = crate::Reg; +#[doc = "Bridge interrupt flag status"] +pub mod intflagahb; +#[doc = "INTFLAGA register accessor: an alias for `Reg`"] +pub type INTFLAGA = crate::Reg; +#[doc = "Peripheral interrupt flag status - Bridge A"] +pub mod intflaga; +#[doc = "INTFLAGB register accessor: an alias for `Reg`"] +pub type INTFLAGB = crate::Reg; +#[doc = "Peripheral interrupt flag status - Bridge B"] +pub mod intflagb; +#[doc = "INTFLAGC register accessor: an alias for `Reg`"] +pub type INTFLAGC = crate::Reg; +#[doc = "Peripheral interrupt flag status - Bridge C"] +pub mod intflagc; +#[doc = "STATUSA register accessor: an alias for `Reg`"] +pub type STATUSA = crate::Reg; +#[doc = "Peripheral write protection status - Bridge A"] +pub mod statusa; +#[doc = "STATUSB register accessor: an alias for `Reg`"] +pub type STATUSB = crate::Reg; +#[doc = "Peripheral write protection status - Bridge B"] +pub mod statusb; +#[doc = "STATUSC register accessor: an alias for `Reg`"] +pub type STATUSC = crate::Reg; +#[doc = "Peripheral write protection status - Bridge C"] +pub mod statusc; diff --git a/pac/atsamc20g/src/pac/evctrl.rs b/pac/atsamc20g/src/pac/evctrl.rs new file mode 100644 index 000000000000..630581b98c85 --- /dev/null +++ b/pac/atsamc20g/src/pac/evctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ERREO` reader - Peripheral acess error event output"] +pub struct ERREO_R(crate::FieldReader); +impl ERREO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERREO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERREO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERREO` writer - Peripheral acess error event output"] +pub struct ERREO_W<'a> { + w: &'a mut W, +} +impl<'a> ERREO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Peripheral acess error event output"] + #[inline(always)] + pub fn erreo(&self) -> ERREO_R { + ERREO_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Peripheral acess error event output"] + #[inline(always)] + pub fn erreo(&mut self) -> ERREO_W { + ERREO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/pac/intenclr.rs b/pac/atsamc20g/src/pac/intenclr.rs new file mode 100644 index 000000000000..609fe0fcf628 --- /dev/null +++ b/pac/atsamc20g/src/pac/intenclr.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ERR` reader - Peripheral access error interrupt disable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - Peripheral access error interrupt disable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Peripheral access error interrupt disable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Peripheral access error interrupt disable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt enable clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/pac/intenset.rs b/pac/atsamc20g/src/pac/intenset.rs new file mode 100644 index 000000000000..390545b588de --- /dev/null +++ b/pac/atsamc20g/src/pac/intenset.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ERR` reader - Peripheral access error interrupt enable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - Peripheral access error interrupt enable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Peripheral access error interrupt enable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Peripheral access error interrupt enable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt enable set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/pac/intflaga.rs b/pac/atsamc20g/src/pac/intflaga.rs new file mode 100644 index 000000000000..df4c8554d9ab --- /dev/null +++ b/pac/atsamc20g/src/pac/intflaga.rs @@ -0,0 +1,630 @@ +#[doc = "Register `INTFLAGA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAGA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PAC_` reader - PAC"] +pub struct PAC__R(crate::FieldReader); +impl PAC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PAC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PAC_` writer - PAC"] +pub struct PAC__W<'a> { + w: &'a mut W, +} +impl<'a> PAC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `PM_` reader - PM"] +pub struct PM__R(crate::FieldReader); +impl PM__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PM__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PM__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PM_` writer - PM"] +pub struct PM__W<'a> { + w: &'a mut W, +} +impl<'a> PM__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MCLK_` reader - MCLK"] +pub struct MCLK__R(crate::FieldReader); +impl MCLK__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCLK__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCLK__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCLK_` writer - MCLK"] +pub struct MCLK__W<'a> { + w: &'a mut W, +} +impl<'a> MCLK__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RSTC_` reader - RSTC"] +pub struct RSTC__R(crate::FieldReader); +impl RSTC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RSTC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RSTC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RSTC_` writer - RSTC"] +pub struct RSTC__W<'a> { + w: &'a mut W, +} +impl<'a> RSTC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `OSCCTRL_` reader - OSCCTRL"] +pub struct OSCCTRL__R(crate::FieldReader); +impl OSCCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSCCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSCCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSCCTRL_` writer - OSCCTRL"] +pub struct OSCCTRL__W<'a> { + w: &'a mut W, +} +impl<'a> OSCCTRL__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `OSC32KCTRL_` reader - OSC32KCTRL"] +pub struct OSC32KCTRL__R(crate::FieldReader); +impl OSC32KCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC32KCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC32KCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC32KCTRL_` writer - OSC32KCTRL"] +pub struct OSC32KCTRL__W<'a> { + w: &'a mut W, +} +impl<'a> OSC32KCTRL__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `SUPC_` reader - SUPC"] +pub struct SUPC__R(crate::FieldReader); +impl SUPC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SUPC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SUPC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SUPC_` writer - SUPC"] +pub struct SUPC__W<'a> { + w: &'a mut W, +} +impl<'a> SUPC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `GCLK_` reader - GCLK"] +pub struct GCLK__R(crate::FieldReader); +impl GCLK__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GCLK__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GCLK__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GCLK_` writer - GCLK"] +pub struct GCLK__W<'a> { + w: &'a mut W, +} +impl<'a> GCLK__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `WDT_` reader - WDT"] +pub struct WDT__R(crate::FieldReader); +impl WDT__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WDT__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WDT__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WDT_` writer - WDT"] +pub struct WDT__W<'a> { + w: &'a mut W, +} +impl<'a> WDT__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `RTC_` reader - RTC"] +pub struct RTC__R(crate::FieldReader); +impl RTC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RTC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RTC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RTC_` writer - RTC"] +pub struct RTC__W<'a> { + w: &'a mut W, +} +impl<'a> RTC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `EIC_` reader - EIC"] +pub struct EIC__R(crate::FieldReader); +impl EIC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EIC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EIC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EIC_` writer - EIC"] +pub struct EIC__W<'a> { + w: &'a mut W, +} +impl<'a> EIC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `FREQM_` reader - FREQM"] +pub struct FREQM__R(crate::FieldReader); +impl FREQM__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FREQM__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FREQM__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FREQM_` writer - FREQM"] +pub struct FREQM__W<'a> { + w: &'a mut W, +} +impl<'a> FREQM__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +impl R { + #[doc = "Bit 0 - PAC"] + #[inline(always)] + pub fn pac_(&self) -> PAC__R { + PAC__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - PM"] + #[inline(always)] + pub fn pm_(&self) -> PM__R { + PM__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - MCLK"] + #[inline(always)] + pub fn mclk_(&self) -> MCLK__R { + MCLK__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - RSTC"] + #[inline(always)] + pub fn rstc_(&self) -> RSTC__R { + RSTC__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - OSCCTRL"] + #[inline(always)] + pub fn oscctrl_(&self) -> OSCCTRL__R { + OSCCTRL__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - OSC32KCTRL"] + #[inline(always)] + pub fn osc32kctrl_(&self) -> OSC32KCTRL__R { + OSC32KCTRL__R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - SUPC"] + #[inline(always)] + pub fn supc_(&self) -> SUPC__R { + SUPC__R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - GCLK"] + #[inline(always)] + pub fn gclk_(&self) -> GCLK__R { + GCLK__R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - WDT"] + #[inline(always)] + pub fn wdt_(&self) -> WDT__R { + WDT__R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - RTC"] + #[inline(always)] + pub fn rtc_(&self) -> RTC__R { + RTC__R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - EIC"] + #[inline(always)] + pub fn eic_(&self) -> EIC__R { + EIC__R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - FREQM"] + #[inline(always)] + pub fn freqm_(&self) -> FREQM__R { + FREQM__R::new(((self.bits >> 11) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - PAC"] + #[inline(always)] + pub fn pac_(&mut self) -> PAC__W { + PAC__W { w: self } + } + #[doc = "Bit 1 - PM"] + #[inline(always)] + pub fn pm_(&mut self) -> PM__W { + PM__W { w: self } + } + #[doc = "Bit 2 - MCLK"] + #[inline(always)] + pub fn mclk_(&mut self) -> MCLK__W { + MCLK__W { w: self } + } + #[doc = "Bit 3 - RSTC"] + #[inline(always)] + pub fn rstc_(&mut self) -> RSTC__W { + RSTC__W { w: self } + } + #[doc = "Bit 4 - OSCCTRL"] + #[inline(always)] + pub fn oscctrl_(&mut self) -> OSCCTRL__W { + OSCCTRL__W { w: self } + } + #[doc = "Bit 5 - OSC32KCTRL"] + #[inline(always)] + pub fn osc32kctrl_(&mut self) -> OSC32KCTRL__W { + OSC32KCTRL__W { w: self } + } + #[doc = "Bit 6 - SUPC"] + #[inline(always)] + pub fn supc_(&mut self) -> SUPC__W { + SUPC__W { w: self } + } + #[doc = "Bit 7 - GCLK"] + #[inline(always)] + pub fn gclk_(&mut self) -> GCLK__W { + GCLK__W { w: self } + } + #[doc = "Bit 8 - WDT"] + #[inline(always)] + pub fn wdt_(&mut self) -> WDT__W { + WDT__W { w: self } + } + #[doc = "Bit 9 - RTC"] + #[inline(always)] + pub fn rtc_(&mut self) -> RTC__W { + RTC__W { w: self } + } + #[doc = "Bit 10 - EIC"] + #[inline(always)] + pub fn eic_(&mut self) -> EIC__W { + EIC__W { w: self } + } + #[doc = "Bit 11 - FREQM"] + #[inline(always)] + pub fn freqm_(&mut self) -> FREQM__W { + FREQM__W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Peripheral interrupt flag status - Bridge A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflaga](index.html) module"] +pub struct INTFLAGA_SPEC; +impl crate::RegisterSpec for INTFLAGA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflaga::R](R) reader structure"] +impl crate::Readable for INTFLAGA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflaga::W](W) writer structure"] +impl crate::Writable for INTFLAGA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAGA to value 0"] +impl crate::Resettable for INTFLAGA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/pac/intflagahb.rs b/pac/atsamc20g/src/pac/intflagahb.rs new file mode 100644 index 000000000000..4b7f7377e25e --- /dev/null +++ b/pac/atsamc20g/src/pac/intflagahb.rs @@ -0,0 +1,442 @@ +#[doc = "Register `INTFLAGAHB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAGAHB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FLASH_` reader - FLASH"] +pub struct FLASH__R(crate::FieldReader); +impl FLASH__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FLASH__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FLASH__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLASH_` writer - FLASH"] +pub struct FLASH__W<'a> { + w: &'a mut W, +} +impl<'a> FLASH__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `HSRAMCM0P_` reader - HSRAMCM0P"] +pub struct HSRAMCM0P__R(crate::FieldReader); +impl HSRAMCM0P__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HSRAMCM0P__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HSRAMCM0P__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HSRAMCM0P_` writer - HSRAMCM0P"] +pub struct HSRAMCM0P__W<'a> { + w: &'a mut W, +} +impl<'a> HSRAMCM0P__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `HSRAMDSU_` reader - HSRAMDSU"] +pub struct HSRAMDSU__R(crate::FieldReader); +impl HSRAMDSU__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HSRAMDSU__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HSRAMDSU__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HSRAMDSU_` writer - HSRAMDSU"] +pub struct HSRAMDSU__W<'a> { + w: &'a mut W, +} +impl<'a> HSRAMDSU__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `HPB1_` reader - HPB1"] +pub struct HPB1__R(crate::FieldReader); +impl HPB1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HPB1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HPB1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HPB1_` writer - HPB1"] +pub struct HPB1__W<'a> { + w: &'a mut W, +} +impl<'a> HPB1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `HPB0_` reader - HPB0"] +pub struct HPB0__R(crate::FieldReader); +impl HPB0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HPB0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HPB0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HPB0_` writer - HPB0"] +pub struct HPB0__W<'a> { + w: &'a mut W, +} +impl<'a> HPB0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `HPB2_` reader - HPB2"] +pub struct HPB2__R(crate::FieldReader); +impl HPB2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HPB2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HPB2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HPB2_` writer - HPB2"] +pub struct HPB2__W<'a> { + w: &'a mut W, +} +impl<'a> HPB2__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `LPRAMDMAC_` reader - LPRAMDMAC"] +pub struct LPRAMDMAC__R(crate::FieldReader); +impl LPRAMDMAC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LPRAMDMAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LPRAMDMAC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LPRAMDMAC_` writer - LPRAMDMAC"] +pub struct LPRAMDMAC__W<'a> { + w: &'a mut W, +} +impl<'a> LPRAMDMAC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `DIVAS_` reader - DIVAS"] +pub struct DIVAS__R(crate::FieldReader); +impl DIVAS__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIVAS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIVAS__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIVAS_` writer - DIVAS"] +pub struct DIVAS__W<'a> { + w: &'a mut W, +} +impl<'a> DIVAS__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - FLASH"] + #[inline(always)] + pub fn flash_(&self) -> FLASH__R { + FLASH__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - HSRAMCM0P"] + #[inline(always)] + pub fn hsramcm0p_(&self) -> HSRAMCM0P__R { + HSRAMCM0P__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - HSRAMDSU"] + #[inline(always)] + pub fn hsramdsu_(&self) -> HSRAMDSU__R { + HSRAMDSU__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - HPB1"] + #[inline(always)] + pub fn hpb1_(&self) -> HPB1__R { + HPB1__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - HPB0"] + #[inline(always)] + pub fn hpb0_(&self) -> HPB0__R { + HPB0__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - HPB2"] + #[inline(always)] + pub fn hpb2_(&self) -> HPB2__R { + HPB2__R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - LPRAMDMAC"] + #[inline(always)] + pub fn lpramdmac_(&self) -> LPRAMDMAC__R { + LPRAMDMAC__R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - DIVAS"] + #[inline(always)] + pub fn divas_(&self) -> DIVAS__R { + DIVAS__R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - FLASH"] + #[inline(always)] + pub fn flash_(&mut self) -> FLASH__W { + FLASH__W { w: self } + } + #[doc = "Bit 1 - HSRAMCM0P"] + #[inline(always)] + pub fn hsramcm0p_(&mut self) -> HSRAMCM0P__W { + HSRAMCM0P__W { w: self } + } + #[doc = "Bit 2 - HSRAMDSU"] + #[inline(always)] + pub fn hsramdsu_(&mut self) -> HSRAMDSU__W { + HSRAMDSU__W { w: self } + } + #[doc = "Bit 3 - HPB1"] + #[inline(always)] + pub fn hpb1_(&mut self) -> HPB1__W { + HPB1__W { w: self } + } + #[doc = "Bit 4 - HPB0"] + #[inline(always)] + pub fn hpb0_(&mut self) -> HPB0__W { + HPB0__W { w: self } + } + #[doc = "Bit 5 - HPB2"] + #[inline(always)] + pub fn hpb2_(&mut self) -> HPB2__W { + HPB2__W { w: self } + } + #[doc = "Bit 6 - LPRAMDMAC"] + #[inline(always)] + pub fn lpramdmac_(&mut self) -> LPRAMDMAC__W { + LPRAMDMAC__W { w: self } + } + #[doc = "Bit 7 - DIVAS"] + #[inline(always)] + pub fn divas_(&mut self) -> DIVAS__W { + DIVAS__W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Bridge interrupt flag status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflagahb](index.html) module"] +pub struct INTFLAGAHB_SPEC; +impl crate::RegisterSpec for INTFLAGAHB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflagahb::R](R) reader structure"] +impl crate::Readable for INTFLAGAHB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflagahb::W](W) writer structure"] +impl crate::Writable for INTFLAGAHB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAGAHB to value 0"] +impl crate::Resettable for INTFLAGAHB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/pac/intflagb.rs b/pac/atsamc20g/src/pac/intflagb.rs new file mode 100644 index 000000000000..8359f7e11f30 --- /dev/null +++ b/pac/atsamc20g/src/pac/intflagb.rs @@ -0,0 +1,348 @@ +#[doc = "Register `INTFLAGB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAGB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PORT_` reader - PORT"] +pub struct PORT__R(crate::FieldReader); +impl PORT__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PORT__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PORT__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PORT_` writer - PORT"] +pub struct PORT__W<'a> { + w: &'a mut W, +} +impl<'a> PORT__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `DSU_` reader - DSU"] +pub struct DSU__R(crate::FieldReader); +impl DSU__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DSU__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DSU__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DSU_` writer - DSU"] +pub struct DSU__W<'a> { + w: &'a mut W, +} +impl<'a> DSU__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `NVMCTRL_` reader - NVMCTRL"] +pub struct NVMCTRL__R(crate::FieldReader); +impl NVMCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NVMCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NVMCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NVMCTRL_` writer - NVMCTRL"] +pub struct NVMCTRL__W<'a> { + w: &'a mut W, +} +impl<'a> NVMCTRL__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `DMAC_` reader - DMAC"] +pub struct DMAC__R(crate::FieldReader); +impl DMAC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DMAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DMAC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DMAC_` writer - DMAC"] +pub struct DMAC__W<'a> { + w: &'a mut W, +} +impl<'a> DMAC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `MTB_` reader - MTB"] +pub struct MTB__R(crate::FieldReader); +impl MTB__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MTB__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MTB__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MTB_` writer - MTB"] +pub struct MTB__W<'a> { + w: &'a mut W, +} +impl<'a> MTB__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `HMATRIXHS_` reader - HMATRIXHS"] +pub struct HMATRIXHS__R(crate::FieldReader); +impl HMATRIXHS__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HMATRIXHS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HMATRIXHS__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HMATRIXHS_` writer - HMATRIXHS"] +pub struct HMATRIXHS__W<'a> { + w: &'a mut W, +} +impl<'a> HMATRIXHS__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - PORT"] + #[inline(always)] + pub fn port_(&self) -> PORT__R { + PORT__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - DSU"] + #[inline(always)] + pub fn dsu_(&self) -> DSU__R { + DSU__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - NVMCTRL"] + #[inline(always)] + pub fn nvmctrl_(&self) -> NVMCTRL__R { + NVMCTRL__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - DMAC"] + #[inline(always)] + pub fn dmac_(&self) -> DMAC__R { + DMAC__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - MTB"] + #[inline(always)] + pub fn mtb_(&self) -> MTB__R { + MTB__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - HMATRIXHS"] + #[inline(always)] + pub fn hmatrixhs_(&self) -> HMATRIXHS__R { + HMATRIXHS__R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - PORT"] + #[inline(always)] + pub fn port_(&mut self) -> PORT__W { + PORT__W { w: self } + } + #[doc = "Bit 1 - DSU"] + #[inline(always)] + pub fn dsu_(&mut self) -> DSU__W { + DSU__W { w: self } + } + #[doc = "Bit 2 - NVMCTRL"] + #[inline(always)] + pub fn nvmctrl_(&mut self) -> NVMCTRL__W { + NVMCTRL__W { w: self } + } + #[doc = "Bit 3 - DMAC"] + #[inline(always)] + pub fn dmac_(&mut self) -> DMAC__W { + DMAC__W { w: self } + } + #[doc = "Bit 4 - MTB"] + #[inline(always)] + pub fn mtb_(&mut self) -> MTB__W { + MTB__W { w: self } + } + #[doc = "Bit 5 - HMATRIXHS"] + #[inline(always)] + pub fn hmatrixhs_(&mut self) -> HMATRIXHS__W { + HMATRIXHS__W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Peripheral interrupt flag status - Bridge B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflagb](index.html) module"] +pub struct INTFLAGB_SPEC; +impl crate::RegisterSpec for INTFLAGB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflagb::R](R) reader structure"] +impl crate::Readable for INTFLAGB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflagb::W](W) writer structure"] +impl crate::Writable for INTFLAGB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAGB to value 0"] +impl crate::Resettable for INTFLAGB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/pac/intflagc.rs b/pac/atsamc20g/src/pac/intflagc.rs new file mode 100644 index 000000000000..25a236fa631a --- /dev/null +++ b/pac/atsamc20g/src/pac/intflagc.rs @@ -0,0 +1,865 @@ +#[doc = "Register `INTFLAGC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAGC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVSYS_` reader - EVSYS"] +pub struct EVSYS__R(crate::FieldReader); +impl EVSYS__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVSYS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVSYS__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVSYS_` writer - EVSYS"] +pub struct EVSYS__W<'a> { + w: &'a mut W, +} +impl<'a> EVSYS__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `SERCOM0_` reader - SERCOM0"] +pub struct SERCOM0__R(crate::FieldReader); +impl SERCOM0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM0_` writer - SERCOM0"] +pub struct SERCOM0__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SERCOM1_` reader - SERCOM1"] +pub struct SERCOM1__R(crate::FieldReader); +impl SERCOM1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM1_` writer - SERCOM1"] +pub struct SERCOM1__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SERCOM2_` reader - SERCOM2"] +pub struct SERCOM2__R(crate::FieldReader); +impl SERCOM2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM2_` writer - SERCOM2"] +pub struct SERCOM2__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM2__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `SERCOM3_` reader - SERCOM3"] +pub struct SERCOM3__R(crate::FieldReader); +impl SERCOM3__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM3__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM3__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM3_` writer - SERCOM3"] +pub struct SERCOM3__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM3__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `TCC0_` reader - TCC0"] +pub struct TCC0__R(crate::FieldReader); +impl TCC0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCC0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCC0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCC0_` writer - TCC0"] +pub struct TCC0__W<'a> { + w: &'a mut W, +} +impl<'a> TCC0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `TCC1_` reader - TCC1"] +pub struct TCC1__R(crate::FieldReader); +impl TCC1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCC1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCC1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCC1_` writer - TCC1"] +pub struct TCC1__W<'a> { + w: &'a mut W, +} +impl<'a> TCC1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `TCC2_` reader - TCC2"] +pub struct TCC2__R(crate::FieldReader); +impl TCC2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCC2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCC2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCC2_` writer - TCC2"] +pub struct TCC2__W<'a> { + w: &'a mut W, +} +impl<'a> TCC2__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `TC0_` reader - TC0"] +pub struct TC0__R(crate::FieldReader); +impl TC0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC0_` writer - TC0"] +pub struct TC0__W<'a> { + w: &'a mut W, +} +impl<'a> TC0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `TC1_` reader - TC1"] +pub struct TC1__R(crate::FieldReader); +impl TC1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC1_` writer - TC1"] +pub struct TC1__W<'a> { + w: &'a mut W, +} +impl<'a> TC1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `TC2_` reader - TC2"] +pub struct TC2__R(crate::FieldReader); +impl TC2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC2_` writer - TC2"] +pub struct TC2__W<'a> { + w: &'a mut W, +} +impl<'a> TC2__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `TC3_` reader - TC3"] +pub struct TC3__R(crate::FieldReader); +impl TC3__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC3__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC3__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC3_` writer - TC3"] +pub struct TC3__W<'a> { + w: &'a mut W, +} +impl<'a> TC3__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `TC4_` reader - TC4"] +pub struct TC4__R(crate::FieldReader); +impl TC4__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC4__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC4__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC4_` writer - TC4"] +pub struct TC4__W<'a> { + w: &'a mut W, +} +impl<'a> TC4__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `ADC0_` reader - ADC0"] +pub struct ADC0__R(crate::FieldReader); +impl ADC0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ADC0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADC0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADC0_` writer - ADC0"] +pub struct ADC0__W<'a> { + w: &'a mut W, +} +impl<'a> ADC0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `AC_` reader - AC"] +pub struct AC__R(crate::FieldReader); +impl AC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AC_` writer - AC"] +pub struct AC__W<'a> { + w: &'a mut W, +} +impl<'a> AC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `PTC_` reader - PTC"] +pub struct PTC__R(crate::FieldReader); +impl PTC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PTC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PTC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PTC_` writer - PTC"] +pub struct PTC__W<'a> { + w: &'a mut W, +} +impl<'a> PTC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `CCL_` reader - CCL"] +pub struct CCL__R(crate::FieldReader); +impl CCL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCL_` writer - CCL"] +pub struct CCL__W<'a> { + w: &'a mut W, +} +impl<'a> CCL__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +impl R { + #[doc = "Bit 0 - EVSYS"] + #[inline(always)] + pub fn evsys_(&self) -> EVSYS__R { + EVSYS__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM0"] + #[inline(always)] + pub fn sercom0_(&self) -> SERCOM0__R { + SERCOM0__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - SERCOM1"] + #[inline(always)] + pub fn sercom1_(&self) -> SERCOM1__R { + SERCOM1__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - SERCOM2"] + #[inline(always)] + pub fn sercom2_(&self) -> SERCOM2__R { + SERCOM2__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - SERCOM3"] + #[inline(always)] + pub fn sercom3_(&self) -> SERCOM3__R { + SERCOM3__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 9 - TCC0"] + #[inline(always)] + pub fn tcc0_(&self) -> TCC0__R { + TCC0__R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - TCC1"] + #[inline(always)] + pub fn tcc1_(&self) -> TCC1__R { + TCC1__R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - TCC2"] + #[inline(always)] + pub fn tcc2_(&self) -> TCC2__R { + TCC2__R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - TC0"] + #[inline(always)] + pub fn tc0_(&self) -> TC0__R { + TC0__R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - TC1"] + #[inline(always)] + pub fn tc1_(&self) -> TC1__R { + TC1__R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - TC2"] + #[inline(always)] + pub fn tc2_(&self) -> TC2__R { + TC2__R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - TC3"] + #[inline(always)] + pub fn tc3_(&self) -> TC3__R { + TC3__R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - TC4"] + #[inline(always)] + pub fn tc4_(&self) -> TC4__R { + TC4__R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - ADC0"] + #[inline(always)] + pub fn adc0_(&self) -> ADC0__R { + ADC0__R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 20 - AC"] + #[inline(always)] + pub fn ac_(&self) -> AC__R { + AC__R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 22 - PTC"] + #[inline(always)] + pub fn ptc_(&self) -> PTC__R { + PTC__R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - CCL"] + #[inline(always)] + pub fn ccl_(&self) -> CCL__R { + CCL__R::new(((self.bits >> 23) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - EVSYS"] + #[inline(always)] + pub fn evsys_(&mut self) -> EVSYS__W { + EVSYS__W { w: self } + } + #[doc = "Bit 1 - SERCOM0"] + #[inline(always)] + pub fn sercom0_(&mut self) -> SERCOM0__W { + SERCOM0__W { w: self } + } + #[doc = "Bit 2 - SERCOM1"] + #[inline(always)] + pub fn sercom1_(&mut self) -> SERCOM1__W { + SERCOM1__W { w: self } + } + #[doc = "Bit 3 - SERCOM2"] + #[inline(always)] + pub fn sercom2_(&mut self) -> SERCOM2__W { + SERCOM2__W { w: self } + } + #[doc = "Bit 4 - SERCOM3"] + #[inline(always)] + pub fn sercom3_(&mut self) -> SERCOM3__W { + SERCOM3__W { w: self } + } + #[doc = "Bit 9 - TCC0"] + #[inline(always)] + pub fn tcc0_(&mut self) -> TCC0__W { + TCC0__W { w: self } + } + #[doc = "Bit 10 - TCC1"] + #[inline(always)] + pub fn tcc1_(&mut self) -> TCC1__W { + TCC1__W { w: self } + } + #[doc = "Bit 11 - TCC2"] + #[inline(always)] + pub fn tcc2_(&mut self) -> TCC2__W { + TCC2__W { w: self } + } + #[doc = "Bit 12 - TC0"] + #[inline(always)] + pub fn tc0_(&mut self) -> TC0__W { + TC0__W { w: self } + } + #[doc = "Bit 13 - TC1"] + #[inline(always)] + pub fn tc1_(&mut self) -> TC1__W { + TC1__W { w: self } + } + #[doc = "Bit 14 - TC2"] + #[inline(always)] + pub fn tc2_(&mut self) -> TC2__W { + TC2__W { w: self } + } + #[doc = "Bit 15 - TC3"] + #[inline(always)] + pub fn tc3_(&mut self) -> TC3__W { + TC3__W { w: self } + } + #[doc = "Bit 16 - TC4"] + #[inline(always)] + pub fn tc4_(&mut self) -> TC4__W { + TC4__W { w: self } + } + #[doc = "Bit 17 - ADC0"] + #[inline(always)] + pub fn adc0_(&mut self) -> ADC0__W { + ADC0__W { w: self } + } + #[doc = "Bit 20 - AC"] + #[inline(always)] + pub fn ac_(&mut self) -> AC__W { + AC__W { w: self } + } + #[doc = "Bit 22 - PTC"] + #[inline(always)] + pub fn ptc_(&mut self) -> PTC__W { + PTC__W { w: self } + } + #[doc = "Bit 23 - CCL"] + #[inline(always)] + pub fn ccl_(&mut self) -> CCL__W { + CCL__W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Peripheral interrupt flag status - Bridge C\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflagc](index.html) module"] +pub struct INTFLAGC_SPEC; +impl crate::RegisterSpec for INTFLAGC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflagc::R](R) reader structure"] +impl crate::Readable for INTFLAGC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflagc::W](W) writer structure"] +impl crate::Writable for INTFLAGC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAGC to value 0"] +impl crate::Resettable for INTFLAGC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/pac/statusa.rs b/pac/atsamc20g/src/pac/statusa.rs new file mode 100644 index 000000000000..32974f65e5d5 --- /dev/null +++ b/pac/atsamc20g/src/pac/statusa.rs @@ -0,0 +1,273 @@ +#[doc = "Register `STATUSA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PAC_` reader - PAC APB Protect Enable"] +pub struct PAC__R(crate::FieldReader); +impl PAC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PAC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PM_` reader - PM APB Protect Enable"] +pub struct PM__R(crate::FieldReader); +impl PM__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PM__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PM__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCLK_` reader - MCLK APB Protect Enable"] +pub struct MCLK__R(crate::FieldReader); +impl MCLK__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCLK__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCLK__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RSTC_` reader - RSTC APB Protect Enable"] +pub struct RSTC__R(crate::FieldReader); +impl RSTC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RSTC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RSTC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSCCTRL_` reader - OSCCTRL APB Protect Enable"] +pub struct OSCCTRL__R(crate::FieldReader); +impl OSCCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSCCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSCCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC32KCTRL_` reader - OSC32KCTRL APB Protect Enable"] +pub struct OSC32KCTRL__R(crate::FieldReader); +impl OSC32KCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC32KCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC32KCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SUPC_` reader - SUPC APB Protect Enable"] +pub struct SUPC__R(crate::FieldReader); +impl SUPC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SUPC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SUPC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GCLK_` reader - GCLK APB Protect Enable"] +pub struct GCLK__R(crate::FieldReader); +impl GCLK__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GCLK__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GCLK__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WDT_` reader - WDT APB Protect Enable"] +pub struct WDT__R(crate::FieldReader); +impl WDT__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WDT__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WDT__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RTC_` reader - RTC APB Protect Enable"] +pub struct RTC__R(crate::FieldReader); +impl RTC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RTC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RTC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EIC_` reader - EIC APB Protect Enable"] +pub struct EIC__R(crate::FieldReader); +impl EIC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EIC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EIC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FREQM_` reader - FREQM APB Protect Enable"] +pub struct FREQM__R(crate::FieldReader); +impl FREQM__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FREQM__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FREQM__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - PAC APB Protect Enable"] + #[inline(always)] + pub fn pac_(&self) -> PAC__R { + PAC__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - PM APB Protect Enable"] + #[inline(always)] + pub fn pm_(&self) -> PM__R { + PM__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - MCLK APB Protect Enable"] + #[inline(always)] + pub fn mclk_(&self) -> MCLK__R { + MCLK__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - RSTC APB Protect Enable"] + #[inline(always)] + pub fn rstc_(&self) -> RSTC__R { + RSTC__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - OSCCTRL APB Protect Enable"] + #[inline(always)] + pub fn oscctrl_(&self) -> OSCCTRL__R { + OSCCTRL__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - OSC32KCTRL APB Protect Enable"] + #[inline(always)] + pub fn osc32kctrl_(&self) -> OSC32KCTRL__R { + OSC32KCTRL__R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - SUPC APB Protect Enable"] + #[inline(always)] + pub fn supc_(&self) -> SUPC__R { + SUPC__R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - GCLK APB Protect Enable"] + #[inline(always)] + pub fn gclk_(&self) -> GCLK__R { + GCLK__R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - WDT APB Protect Enable"] + #[inline(always)] + pub fn wdt_(&self) -> WDT__R { + WDT__R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - RTC APB Protect Enable"] + #[inline(always)] + pub fn rtc_(&self) -> RTC__R { + RTC__R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - EIC APB Protect Enable"] + #[inline(always)] + pub fn eic_(&self) -> EIC__R { + EIC__R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - FREQM APB Protect Enable"] + #[inline(always)] + pub fn freqm_(&self) -> FREQM__R { + FREQM__R::new(((self.bits >> 11) & 0x01) != 0) + } +} +#[doc = "Peripheral write protection status - Bridge A\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [statusa](index.html) module"] +pub struct STATUSA_SPEC; +impl crate::RegisterSpec for STATUSA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [statusa::R](R) reader structure"] +impl crate::Readable for STATUSA_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUSA to value 0"] +impl crate::Resettable for STATUSA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/pac/statusb.rs b/pac/atsamc20g/src/pac/statusb.rs new file mode 100644 index 000000000000..a022cc2f1d54 --- /dev/null +++ b/pac/atsamc20g/src/pac/statusb.rs @@ -0,0 +1,153 @@ +#[doc = "Register `STATUSB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PORT_` reader - PORT APB Protect Enable"] +pub struct PORT__R(crate::FieldReader); +impl PORT__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PORT__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PORT__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DSU_` reader - DSU APB Protect Enable"] +pub struct DSU__R(crate::FieldReader); +impl DSU__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DSU__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DSU__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NVMCTRL_` reader - NVMCTRL APB Protect Enable"] +pub struct NVMCTRL__R(crate::FieldReader); +impl NVMCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NVMCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NVMCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DMAC_` reader - DMAC APB Protect Enable"] +pub struct DMAC__R(crate::FieldReader); +impl DMAC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DMAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DMAC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MTB_` reader - MTB APB Protect Enable"] +pub struct MTB__R(crate::FieldReader); +impl MTB__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MTB__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MTB__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HMATRIXHS_` reader - HMATRIXHS APB Protect Enable"] +pub struct HMATRIXHS__R(crate::FieldReader); +impl HMATRIXHS__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HMATRIXHS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HMATRIXHS__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - PORT APB Protect Enable"] + #[inline(always)] + pub fn port_(&self) -> PORT__R { + PORT__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - DSU APB Protect Enable"] + #[inline(always)] + pub fn dsu_(&self) -> DSU__R { + DSU__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - NVMCTRL APB Protect Enable"] + #[inline(always)] + pub fn nvmctrl_(&self) -> NVMCTRL__R { + NVMCTRL__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - DMAC APB Protect Enable"] + #[inline(always)] + pub fn dmac_(&self) -> DMAC__R { + DMAC__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - MTB APB Protect Enable"] + #[inline(always)] + pub fn mtb_(&self) -> MTB__R { + MTB__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - HMATRIXHS APB Protect Enable"] + #[inline(always)] + pub fn hmatrixhs_(&self) -> HMATRIXHS__R { + HMATRIXHS__R::new(((self.bits >> 5) & 0x01) != 0) + } +} +#[doc = "Peripheral write protection status - Bridge B\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [statusb](index.html) module"] +pub struct STATUSB_SPEC; +impl crate::RegisterSpec for STATUSB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [statusb::R](R) reader structure"] +impl crate::Readable for STATUSB_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUSB to value 0x02"] +impl crate::Resettable for STATUSB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x02 + } +} diff --git a/pac/atsamc20g/src/pac/statusc.rs b/pac/atsamc20g/src/pac/statusc.rs new file mode 100644 index 000000000000..744a02d7454f --- /dev/null +++ b/pac/atsamc20g/src/pac/statusc.rs @@ -0,0 +1,373 @@ +#[doc = "Register `STATUSC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `EVSYS_` reader - EVSYS APB Protect Enable"] +pub struct EVSYS__R(crate::FieldReader); +impl EVSYS__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVSYS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVSYS__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM0_` reader - SERCOM0 APB Protect Enable"] +pub struct SERCOM0__R(crate::FieldReader); +impl SERCOM0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM1_` reader - SERCOM1 APB Protect Enable"] +pub struct SERCOM1__R(crate::FieldReader); +impl SERCOM1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM2_` reader - SERCOM2 APB Protect Enable"] +pub struct SERCOM2__R(crate::FieldReader); +impl SERCOM2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM3_` reader - SERCOM3 APB Protect Enable"] +pub struct SERCOM3__R(crate::FieldReader); +impl SERCOM3__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM3__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM3__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCC0_` reader - TCC0 APB Protect Enable"] +pub struct TCC0__R(crate::FieldReader); +impl TCC0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCC0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCC0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCC1_` reader - TCC1 APB Protect Enable"] +pub struct TCC1__R(crate::FieldReader); +impl TCC1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCC1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCC1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCC2_` reader - TCC2 APB Protect Enable"] +pub struct TCC2__R(crate::FieldReader); +impl TCC2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCC2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCC2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC0_` reader - TC0 APB Protect Enable"] +pub struct TC0__R(crate::FieldReader); +impl TC0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC1_` reader - TC1 APB Protect Enable"] +pub struct TC1__R(crate::FieldReader); +impl TC1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC2_` reader - TC2 APB Protect Enable"] +pub struct TC2__R(crate::FieldReader); +impl TC2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC3_` reader - TC3 APB Protect Enable"] +pub struct TC3__R(crate::FieldReader); +impl TC3__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC3__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC3__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC4_` reader - TC4 APB Protect Enable"] +pub struct TC4__R(crate::FieldReader); +impl TC4__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC4__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC4__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADC0_` reader - ADC0 APB Protect Enable"] +pub struct ADC0__R(crate::FieldReader); +impl ADC0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ADC0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADC0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AC_` reader - AC APB Protect Enable"] +pub struct AC__R(crate::FieldReader); +impl AC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PTC_` reader - PTC APB Protect Enable"] +pub struct PTC__R(crate::FieldReader); +impl PTC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PTC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PTC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCL_` reader - CCL APB Protect Enable"] +pub struct CCL__R(crate::FieldReader); +impl CCL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - EVSYS APB Protect Enable"] + #[inline(always)] + pub fn evsys_(&self) -> EVSYS__R { + EVSYS__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM0 APB Protect Enable"] + #[inline(always)] + pub fn sercom0_(&self) -> SERCOM0__R { + SERCOM0__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - SERCOM1 APB Protect Enable"] + #[inline(always)] + pub fn sercom1_(&self) -> SERCOM1__R { + SERCOM1__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - SERCOM2 APB Protect Enable"] + #[inline(always)] + pub fn sercom2_(&self) -> SERCOM2__R { + SERCOM2__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - SERCOM3 APB Protect Enable"] + #[inline(always)] + pub fn sercom3_(&self) -> SERCOM3__R { + SERCOM3__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 9 - TCC0 APB Protect Enable"] + #[inline(always)] + pub fn tcc0_(&self) -> TCC0__R { + TCC0__R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - TCC1 APB Protect Enable"] + #[inline(always)] + pub fn tcc1_(&self) -> TCC1__R { + TCC1__R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - TCC2 APB Protect Enable"] + #[inline(always)] + pub fn tcc2_(&self) -> TCC2__R { + TCC2__R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - TC0 APB Protect Enable"] + #[inline(always)] + pub fn tc0_(&self) -> TC0__R { + TC0__R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - TC1 APB Protect Enable"] + #[inline(always)] + pub fn tc1_(&self) -> TC1__R { + TC1__R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - TC2 APB Protect Enable"] + #[inline(always)] + pub fn tc2_(&self) -> TC2__R { + TC2__R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - TC3 APB Protect Enable"] + #[inline(always)] + pub fn tc3_(&self) -> TC3__R { + TC3__R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - TC4 APB Protect Enable"] + #[inline(always)] + pub fn tc4_(&self) -> TC4__R { + TC4__R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - ADC0 APB Protect Enable"] + #[inline(always)] + pub fn adc0_(&self) -> ADC0__R { + ADC0__R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 20 - AC APB Protect Enable"] + #[inline(always)] + pub fn ac_(&self) -> AC__R { + AC__R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 22 - PTC APB Protect Enable"] + #[inline(always)] + pub fn ptc_(&self) -> PTC__R { + PTC__R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - CCL APB Protect Enable"] + #[inline(always)] + pub fn ccl_(&self) -> CCL__R { + CCL__R::new(((self.bits >> 23) & 0x01) != 0) + } +} +#[doc = "Peripheral write protection status - Bridge C\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [statusc](index.html) module"] +pub struct STATUSC_SPEC; +impl crate::RegisterSpec for STATUSC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [statusc::R](R) reader structure"] +impl crate::Readable for STATUSC_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUSC to value 0x0200_0000"] +impl crate::Resettable for STATUSC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0200_0000 + } +} diff --git a/pac/atsamc20g/src/pac/wrctrl.rs b/pac/atsamc20g/src/pac/wrctrl.rs new file mode 100644 index 000000000000..65773ea08d64 --- /dev/null +++ b/pac/atsamc20g/src/pac/wrctrl.rs @@ -0,0 +1,215 @@ +#[doc = "Register `WRCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WRCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PERID` reader - Peripheral identifier"] +pub struct PERID_R(crate::FieldReader); +impl PERID_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + PERID_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERID_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERID` writer - Peripheral identifier"] +pub struct PERID_W<'a> { + w: &'a mut W, +} +impl<'a> PERID_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +#[doc = "Peripheral access control key\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum KEY_A { + #[doc = "0: No action"] + OFF = 0, + #[doc = "1: Clear protection"] + CLR = 1, + #[doc = "2: Set protection"] + SET = 2, + #[doc = "3: Set and lock protection"] + SETLCK = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: KEY_A) -> Self { + variant as _ + } +} +#[doc = "Field `KEY` reader - Peripheral access control key"] +pub struct KEY_R(crate::FieldReader); +impl KEY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + KEY_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(KEY_A::OFF), + 1 => Some(KEY_A::CLR), + 2 => Some(KEY_A::SET), + 3 => Some(KEY_A::SETLCK), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == KEY_A::OFF + } + #[doc = "Checks if the value of the field is `CLR`"] + #[inline(always)] + pub fn is_clr(&self) -> bool { + **self == KEY_A::CLR + } + #[doc = "Checks if the value of the field is `SET`"] + #[inline(always)] + pub fn is_set(&self) -> bool { + **self == KEY_A::SET + } + #[doc = "Checks if the value of the field is `SETLCK`"] + #[inline(always)] + pub fn is_setlck(&self) -> bool { + **self == KEY_A::SETLCK + } +} +impl core::ops::Deref for KEY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `KEY` writer - Peripheral access control key"] +pub struct KEY_W<'a> { + w: &'a mut W, +} +impl<'a> KEY_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: KEY_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(KEY_A::OFF) + } + #[doc = "Clear protection"] + #[inline(always)] + pub fn clr(self) -> &'a mut W { + self.variant(KEY_A::CLR) + } + #[doc = "Set protection"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(KEY_A::SET) + } + #[doc = "Set and lock protection"] + #[inline(always)] + pub fn setlck(self) -> &'a mut W { + self.variant(KEY_A::SETLCK) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Peripheral identifier"] + #[inline(always)] + pub fn perid(&self) -> PERID_R { + PERID_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:23 - Peripheral access control key"] + #[inline(always)] + pub fn key(&self) -> KEY_R { + KEY_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:15 - Peripheral identifier"] + #[inline(always)] + pub fn perid(&mut self) -> PERID_W { + PERID_W { w: self } + } + #[doc = "Bits 16:23 - Peripheral access control key"] + #[inline(always)] + pub fn key(&mut self) -> KEY_W { + KEY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Write control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wrctrl](index.html) module"] +pub struct WRCTRL_SPEC; +impl crate::RegisterSpec for WRCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [wrctrl::R](R) reader structure"] +impl crate::Readable for WRCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wrctrl::W](W) writer structure"] +impl crate::Writable for WRCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WRCTRL to value 0"] +impl crate::Resettable for WRCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/pm.rs b/pac/atsamc20g/src/pm.rs new file mode 100644 index 000000000000..9da2b0e13288 --- /dev/null +++ b/pac/atsamc20g/src/pm.rs @@ -0,0 +1,18 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved0: [u8; 0x01], + #[doc = "0x01 - Sleep Configuration"] + pub sleepcfg: crate::Reg, + _reserved1: [u8; 0x06], + #[doc = "0x08 - Standby Configuration"] + pub stdbycfg: crate::Reg, +} +#[doc = "SLEEPCFG register accessor: an alias for `Reg`"] +pub type SLEEPCFG = crate::Reg; +#[doc = "Sleep Configuration"] +pub mod sleepcfg; +#[doc = "STDBYCFG register accessor: an alias for `Reg`"] +pub type STDBYCFG = crate::Reg; +#[doc = "Standby Configuration"] +pub mod stdbycfg; diff --git a/pac/atsamc20g/src/pm/sleepcfg.rs b/pac/atsamc20g/src/pm/sleepcfg.rs new file mode 100644 index 000000000000..ef643311a059 --- /dev/null +++ b/pac/atsamc20g/src/pm/sleepcfg.rs @@ -0,0 +1,178 @@ +#[doc = "Register `SLEEPCFG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SLEEPCFG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Sleep Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SLEEPMODE_A { + #[doc = "0: CPU clock is OFF"] + IDLE0 = 0, + #[doc = "1: AHB clock is OFF"] + IDLE1 = 1, + #[doc = "2: APB clock are OFF"] + IDLE2 = 2, + #[doc = "4: All Clocks are OFF"] + STANDBY = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SLEEPMODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `SLEEPMODE` reader - Sleep Mode"] +pub struct SLEEPMODE_R(crate::FieldReader); +impl SLEEPMODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SLEEPMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SLEEPMODE_A::IDLE0), + 1 => Some(SLEEPMODE_A::IDLE1), + 2 => Some(SLEEPMODE_A::IDLE2), + 4 => Some(SLEEPMODE_A::STANDBY), + _ => None, + } + } + #[doc = "Checks if the value of the field is `IDLE0`"] + #[inline(always)] + pub fn is_idle0(&self) -> bool { + **self == SLEEPMODE_A::IDLE0 + } + #[doc = "Checks if the value of the field is `IDLE1`"] + #[inline(always)] + pub fn is_idle1(&self) -> bool { + **self == SLEEPMODE_A::IDLE1 + } + #[doc = "Checks if the value of the field is `IDLE2`"] + #[inline(always)] + pub fn is_idle2(&self) -> bool { + **self == SLEEPMODE_A::IDLE2 + } + #[doc = "Checks if the value of the field is `STANDBY`"] + #[inline(always)] + pub fn is_standby(&self) -> bool { + **self == SLEEPMODE_A::STANDBY + } +} +impl core::ops::Deref for SLEEPMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLEEPMODE` writer - Sleep Mode"] +pub struct SLEEPMODE_W<'a> { + w: &'a mut W, +} +impl<'a> SLEEPMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SLEEPMODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "CPU clock is OFF"] + #[inline(always)] + pub fn idle0(self) -> &'a mut W { + self.variant(SLEEPMODE_A::IDLE0) + } + #[doc = "AHB clock is OFF"] + #[inline(always)] + pub fn idle1(self) -> &'a mut W { + self.variant(SLEEPMODE_A::IDLE1) + } + #[doc = "APB clock are OFF"] + #[inline(always)] + pub fn idle2(self) -> &'a mut W { + self.variant(SLEEPMODE_A::IDLE2) + } + #[doc = "All Clocks are OFF"] + #[inline(always)] + pub fn standby(self) -> &'a mut W { + self.variant(SLEEPMODE_A::STANDBY) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Sleep Mode"] + #[inline(always)] + pub fn sleepmode(&self) -> SLEEPMODE_R { + SLEEPMODE_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Sleep Mode"] + #[inline(always)] + pub fn sleepmode(&mut self) -> SLEEPMODE_W { + SLEEPMODE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Sleep Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sleepcfg](index.html) module"] +pub struct SLEEPCFG_SPEC; +impl crate::RegisterSpec for SLEEPCFG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [sleepcfg::R](R) reader structure"] +impl crate::Readable for SLEEPCFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [sleepcfg::W](W) writer structure"] +impl crate::Writable for SLEEPCFG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SLEEPCFG to value 0"] +impl crate::Resettable for SLEEPCFG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/pm/stdbycfg.rs b/pac/atsamc20g/src/pm/stdbycfg.rs new file mode 100644 index 000000000000..9780f2b001f5 --- /dev/null +++ b/pac/atsamc20g/src/pm/stdbycfg.rs @@ -0,0 +1,212 @@ +#[doc = "Register `STDBYCFG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STDBYCFG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Voltage Regulator Standby mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum VREGSMOD_A { + #[doc = "0: Automatic mode"] + AUTO = 0, + #[doc = "1: Performance oriented"] + PERFORMANCE = 1, + #[doc = "2: Low Power oriented"] + LP = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: VREGSMOD_A) -> Self { + variant as _ + } +} +#[doc = "Field `VREGSMOD` reader - Voltage Regulator Standby mode"] +pub struct VREGSMOD_R(crate::FieldReader); +impl VREGSMOD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + VREGSMOD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(VREGSMOD_A::AUTO), + 1 => Some(VREGSMOD_A::PERFORMANCE), + 2 => Some(VREGSMOD_A::LP), + _ => None, + } + } + #[doc = "Checks if the value of the field is `AUTO`"] + #[inline(always)] + pub fn is_auto(&self) -> bool { + **self == VREGSMOD_A::AUTO + } + #[doc = "Checks if the value of the field is `PERFORMANCE`"] + #[inline(always)] + pub fn is_performance(&self) -> bool { + **self == VREGSMOD_A::PERFORMANCE + } + #[doc = "Checks if the value of the field is `LP`"] + #[inline(always)] + pub fn is_lp(&self) -> bool { + **self == VREGSMOD_A::LP + } +} +impl core::ops::Deref for VREGSMOD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VREGSMOD` writer - Voltage Regulator Standby mode"] +pub struct VREGSMOD_W<'a> { + w: &'a mut W, +} +impl<'a> VREGSMOD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: VREGSMOD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Automatic mode"] + #[inline(always)] + pub fn auto(self) -> &'a mut W { + self.variant(VREGSMOD_A::AUTO) + } + #[doc = "Performance oriented"] + #[inline(always)] + pub fn performance(self) -> &'a mut W { + self.variant(VREGSMOD_A::PERFORMANCE) + } + #[doc = "Low Power oriented"] + #[inline(always)] + pub fn lp(self) -> &'a mut W { + self.variant(VREGSMOD_A::LP) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 6)) | ((value as u16 & 0x03) << 6); + self.w + } +} +#[doc = "Field `BBIASHS` reader - Back Bias for HMCRAMCHS"] +pub struct BBIASHS_R(crate::FieldReader); +impl BBIASHS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BBIASHS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BBIASHS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BBIASHS` writer - Back Bias for HMCRAMCHS"] +pub struct BBIASHS_W<'a> { + w: &'a mut W, +} +impl<'a> BBIASHS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u16 & 0x01) << 10); + self.w + } +} +impl R { + #[doc = "Bits 6:7 - Voltage Regulator Standby mode"] + #[inline(always)] + pub fn vregsmod(&self) -> VREGSMOD_R { + VREGSMOD_R::new(((self.bits >> 6) & 0x03) as u8) + } + #[doc = "Bit 10 - Back Bias for HMCRAMCHS"] + #[inline(always)] + pub fn bbiashs(&self) -> BBIASHS_R { + BBIASHS_R::new(((self.bits >> 10) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 6:7 - Voltage Regulator Standby mode"] + #[inline(always)] + pub fn vregsmod(&mut self) -> VREGSMOD_W { + VREGSMOD_W { w: self } + } + #[doc = "Bit 10 - Back Bias for HMCRAMCHS"] + #[inline(always)] + pub fn bbiashs(&mut self) -> BBIASHS_W { + BBIASHS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Standby Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [stdbycfg](index.html) module"] +pub struct STDBYCFG_SPEC; +impl crate::RegisterSpec for STDBYCFG_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [stdbycfg::R](R) reader structure"] +impl crate::Readable for STDBYCFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [stdbycfg::W](W) writer structure"] +impl crate::Writable for STDBYCFG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STDBYCFG to value 0x0400"] +impl crate::Resettable for STDBYCFG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0400 + } +} diff --git a/pac/atsamc20g/src/port.rs b/pac/atsamc20g/src/port.rs new file mode 100644 index 000000000000..08c16491ba07 --- /dev/null +++ b/pac/atsamc20g/src/port.rs @@ -0,0 +1,44 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00..0x60 - GROUP\\[%s\\]"] + pub group0: GROUP, + _reserved1: [u8; 0x20], + #[doc = "0x80..0xe0 - GROUP\\[%s\\]"] + pub group1: GROUP, +} +#[doc = r"Register block"] +#[repr(C)] +pub struct GROUP { + #[doc = "0x00 - Data Direction"] + pub dir: crate::Reg, + #[doc = "0x04 - Data Direction Clear"] + pub dirclr: crate::Reg, + #[doc = "0x08 - Data Direction Set"] + pub dirset: crate::Reg, + #[doc = "0x0c - Data Direction Toggle"] + pub dirtgl: crate::Reg, + #[doc = "0x10 - Data Output Value"] + pub out: crate::Reg, + #[doc = "0x14 - Data Output Value Clear"] + pub outclr: crate::Reg, + #[doc = "0x18 - Data Output Value Set"] + pub outset: crate::Reg, + #[doc = "0x1c - Data Output Value Toggle"] + pub outtgl: crate::Reg, + #[doc = "0x20 - Data Input Value"] + pub in_: crate::Reg, + #[doc = "0x24 - Control"] + pub ctrl: crate::Reg, + #[doc = "0x28 - Write Configuration"] + pub wrconfig: crate::Reg, + #[doc = "0x2c - Event Input Control"] + pub evctrl: crate::Reg, + #[doc = "0x30..0x40 - Peripheral Multiplexing n"] + pub pmux: [crate::Reg; 16], + #[doc = "0x40..0x60 - Pin Configuration n"] + pub pincfg: [crate::Reg; 32], +} +#[doc = r"Register block"] +#[doc = "GROUP\\[%s\\]"] +pub mod group; diff --git a/pac/atsamc20g/src/port/group.rs b/pac/atsamc20g/src/port/group.rs new file mode 100644 index 000000000000..d1aabcd73380 --- /dev/null +++ b/pac/atsamc20g/src/port/group.rs @@ -0,0 +1,56 @@ +#[doc = "DIR register accessor: an alias for `Reg`"] +pub type DIR = crate::Reg; +#[doc = "Data Direction"] +pub mod dir; +#[doc = "DIRCLR register accessor: an alias for `Reg`"] +pub type DIRCLR = crate::Reg; +#[doc = "Data Direction Clear"] +pub mod dirclr; +#[doc = "DIRSET register accessor: an alias for `Reg`"] +pub type DIRSET = crate::Reg; +#[doc = "Data Direction Set"] +pub mod dirset; +#[doc = "DIRTGL register accessor: an alias for `Reg`"] +pub type DIRTGL = crate::Reg; +#[doc = "Data Direction Toggle"] +pub mod dirtgl; +#[doc = "OUT register accessor: an alias for `Reg`"] +pub type OUT = crate::Reg; +#[doc = "Data Output Value"] +pub mod out; +#[doc = "OUTCLR register accessor: an alias for `Reg`"] +pub type OUTCLR = crate::Reg; +#[doc = "Data Output Value Clear"] +pub mod outclr; +#[doc = "OUTSET register accessor: an alias for `Reg`"] +pub type OUTSET = crate::Reg; +#[doc = "Data Output Value Set"] +pub mod outset; +#[doc = "OUTTGL register accessor: an alias for `Reg`"] +pub type OUTTGL = crate::Reg; +#[doc = "Data Output Value Toggle"] +pub mod outtgl; +#[doc = "IN register accessor: an alias for `Reg`"] +pub type IN = crate::Reg; +#[doc = "Data Input Value"] +pub mod in_; +#[doc = "CTRL register accessor: an alias for `Reg`"] +pub type CTRL = crate::Reg; +#[doc = "Control"] +pub mod ctrl; +#[doc = "WRCONFIG register accessor: an alias for `Reg`"] +pub type WRCONFIG = crate::Reg; +#[doc = "Write Configuration"] +pub mod wrconfig; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Input Control"] +pub mod evctrl; +#[doc = "PMUX register accessor: an alias for `Reg`"] +pub type PMUX = crate::Reg; +#[doc = "Peripheral Multiplexing n"] +pub mod pmux; +#[doc = "PINCFG register accessor: an alias for `Reg`"] +pub type PINCFG = crate::Reg; +#[doc = "Pin Configuration n"] +pub mod pincfg; diff --git a/pac/atsamc20g/src/port/group/ctrl.rs b/pac/atsamc20g/src/port/group/ctrl.rs new file mode 100644 index 000000000000..4b57cd6fcd2b --- /dev/null +++ b/pac/atsamc20g/src/port/group/ctrl.rs @@ -0,0 +1,103 @@ +#[doc = "Register `CTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SAMPLING` reader - Input Sampling Mode"] +pub struct SAMPLING_R(crate::FieldReader); +impl SAMPLING_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + SAMPLING_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SAMPLING_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SAMPLING` writer - Input Sampling Mode"] +pub struct SAMPLING_W<'a> { + w: &'a mut W, +} +impl<'a> SAMPLING_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Input Sampling Mode"] + #[inline(always)] + pub fn sampling(&self) -> SAMPLING_R { + SAMPLING_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Input Sampling Mode"] + #[inline(always)] + pub fn sampling(&mut self) -> SAMPLING_W { + SAMPLING_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"] +pub struct CTRL_SPEC; +impl crate::RegisterSpec for CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrl::R](R) reader structure"] +impl crate::Readable for CTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"] +impl crate::Writable for CTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/port/group/dir.rs b/pac/atsamc20g/src/port/group/dir.rs new file mode 100644 index 000000000000..e04452fb5d35 --- /dev/null +++ b/pac/atsamc20g/src/port/group/dir.rs @@ -0,0 +1,64 @@ +#[doc = "Register `DIR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Direction\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dir](index.html) module"] +pub struct DIR_SPEC; +impl crate::RegisterSpec for DIR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dir::R](R) reader structure"] +impl crate::Readable for DIR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dir::W](W) writer structure"] +impl crate::Writable for DIR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DIR to value 0"] +impl crate::Resettable for DIR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/port/group/dirclr.rs b/pac/atsamc20g/src/port/group/dirclr.rs new file mode 100644 index 000000000000..5e6d73d032b2 --- /dev/null +++ b/pac/atsamc20g/src/port/group/dirclr.rs @@ -0,0 +1,64 @@ +#[doc = "Register `DIRCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIRCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Direction Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dirclr](index.html) module"] +pub struct DIRCLR_SPEC; +impl crate::RegisterSpec for DIRCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dirclr::R](R) reader structure"] +impl crate::Readable for DIRCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dirclr::W](W) writer structure"] +impl crate::Writable for DIRCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DIRCLR to value 0"] +impl crate::Resettable for DIRCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/port/group/dirset.rs b/pac/atsamc20g/src/port/group/dirset.rs new file mode 100644 index 000000000000..eaa86e14f15d --- /dev/null +++ b/pac/atsamc20g/src/port/group/dirset.rs @@ -0,0 +1,64 @@ +#[doc = "Register `DIRSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIRSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Direction Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dirset](index.html) module"] +pub struct DIRSET_SPEC; +impl crate::RegisterSpec for DIRSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dirset::R](R) reader structure"] +impl crate::Readable for DIRSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dirset::W](W) writer structure"] +impl crate::Writable for DIRSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DIRSET to value 0"] +impl crate::Resettable for DIRSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/port/group/dirtgl.rs b/pac/atsamc20g/src/port/group/dirtgl.rs new file mode 100644 index 000000000000..fbd021438b1b --- /dev/null +++ b/pac/atsamc20g/src/port/group/dirtgl.rs @@ -0,0 +1,64 @@ +#[doc = "Register `DIRTGL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIRTGL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Direction Toggle\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dirtgl](index.html) module"] +pub struct DIRTGL_SPEC; +impl crate::RegisterSpec for DIRTGL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dirtgl::R](R) reader structure"] +impl crate::Readable for DIRTGL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dirtgl::W](W) writer structure"] +impl crate::Writable for DIRTGL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DIRTGL to value 0"] +impl crate::Resettable for DIRTGL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/port/group/evctrl.rs b/pac/atsamc20g/src/port/group/evctrl.rs new file mode 100644 index 000000000000..ef0a35987f3d --- /dev/null +++ b/pac/atsamc20g/src/port/group/evctrl.rs @@ -0,0 +1,625 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PID0` reader - Port Event Pin Identifier 0"] +pub struct PID0_R(crate::FieldReader); +impl PID0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PID0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PID0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PID0` writer - Port Event Pin Identifier 0"] +pub struct PID0_W<'a> { + w: &'a mut W, +} +impl<'a> PID0_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f); + self.w + } +} +#[doc = "Port Event Action 0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EVACT0_A { + #[doc = "0: Event output to pin"] + OUT = 0, + #[doc = "1: Set output register of pin on event"] + SET = 1, + #[doc = "2: Clear output register of pin on event"] + CLR = 2, + #[doc = "3: Toggle output register of pin on event"] + TGL = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EVACT0_A) -> Self { + variant as _ + } +} +#[doc = "Field `EVACT0` reader - Port Event Action 0"] +pub struct EVACT0_R(crate::FieldReader); +impl EVACT0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVACT0_A { + match self.bits { + 0 => EVACT0_A::OUT, + 1 => EVACT0_A::SET, + 2 => EVACT0_A::CLR, + 3 => EVACT0_A::TGL, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `OUT`"] + #[inline(always)] + pub fn is_out(&self) -> bool { + **self == EVACT0_A::OUT + } + #[doc = "Checks if the value of the field is `SET`"] + #[inline(always)] + pub fn is_set(&self) -> bool { + **self == EVACT0_A::SET + } + #[doc = "Checks if the value of the field is `CLR`"] + #[inline(always)] + pub fn is_clr(&self) -> bool { + **self == EVACT0_A::CLR + } + #[doc = "Checks if the value of the field is `TGL`"] + #[inline(always)] + pub fn is_tgl(&self) -> bool { + **self == EVACT0_A::TGL + } +} +impl core::ops::Deref for EVACT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT0` writer - Port Event Action 0"] +pub struct EVACT0_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT0_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EVACT0_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Event output to pin"] + #[inline(always)] + pub fn out(self) -> &'a mut W { + self.variant(EVACT0_A::OUT) + } + #[doc = "Set output register of pin on event"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(EVACT0_A::SET) + } + #[doc = "Clear output register of pin on event"] + #[inline(always)] + pub fn clr(self) -> &'a mut W { + self.variant(EVACT0_A::CLR) + } + #[doc = "Toggle output register of pin on event"] + #[inline(always)] + pub fn tgl(self) -> &'a mut W { + self.variant(EVACT0_A::TGL) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 5)) | ((value as u32 & 0x03) << 5); + self.w + } +} +#[doc = "Field `PORTEI0` reader - Port Event Enable Input 0"] +pub struct PORTEI0_R(crate::FieldReader); +impl PORTEI0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PORTEI0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PORTEI0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PORTEI0` writer - Port Event Enable Input 0"] +pub struct PORTEI0_W<'a> { + w: &'a mut W, +} +impl<'a> PORTEI0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `PID1` reader - Port Event Pin Identifier 1"] +pub struct PID1_R(crate::FieldReader); +impl PID1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PID1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PID1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PID1` writer - Port Event Pin Identifier 1"] +pub struct PID1_W<'a> { + w: &'a mut W, +} +impl<'a> PID1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 8)) | ((value as u32 & 0x1f) << 8); + self.w + } +} +#[doc = "Field `EVACT1` reader - Port Event Action 1"] +pub struct EVACT1_R(crate::FieldReader); +impl EVACT1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVACT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT1` writer - Port Event Action 1"] +pub struct EVACT1_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 13)) | ((value as u32 & 0x03) << 13); + self.w + } +} +#[doc = "Field `PORTEI1` reader - Port Event Enable Input 1"] +pub struct PORTEI1_R(crate::FieldReader); +impl PORTEI1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PORTEI1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PORTEI1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PORTEI1` writer - Port Event Enable Input 1"] +pub struct PORTEI1_W<'a> { + w: &'a mut W, +} +impl<'a> PORTEI1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `PID2` reader - Port Event Pin Identifier 2"] +pub struct PID2_R(crate::FieldReader); +impl PID2_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PID2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PID2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PID2` writer - Port Event Pin Identifier 2"] +pub struct PID2_W<'a> { + w: &'a mut W, +} +impl<'a> PID2_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 16)) | ((value as u32 & 0x1f) << 16); + self.w + } +} +#[doc = "Field `EVACT2` reader - Port Event Action 2"] +pub struct EVACT2_R(crate::FieldReader); +impl EVACT2_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVACT2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT2` writer - Port Event Action 2"] +pub struct EVACT2_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT2_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 21)) | ((value as u32 & 0x03) << 21); + self.w + } +} +#[doc = "Field `PORTEI2` reader - Port Event Enable Input 2"] +pub struct PORTEI2_R(crate::FieldReader); +impl PORTEI2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PORTEI2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PORTEI2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PORTEI2` writer - Port Event Enable Input 2"] +pub struct PORTEI2_W<'a> { + w: &'a mut W, +} +impl<'a> PORTEI2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `PID3` reader - Port Event Pin Identifier 3"] +pub struct PID3_R(crate::FieldReader); +impl PID3_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PID3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PID3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PID3` writer - Port Event Pin Identifier 3"] +pub struct PID3_W<'a> { + w: &'a mut W, +} +impl<'a> PID3_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 24)) | ((value as u32 & 0x1f) << 24); + self.w + } +} +#[doc = "Field `EVACT3` reader - Port Event Action 3"] +pub struct EVACT3_R(crate::FieldReader); +impl EVACT3_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVACT3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT3` writer - Port Event Action 3"] +pub struct EVACT3_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT3_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 29)) | ((value as u32 & 0x03) << 29); + self.w + } +} +#[doc = "Field `PORTEI3` reader - Port Event Enable Input 3"] +pub struct PORTEI3_R(crate::FieldReader); +impl PORTEI3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PORTEI3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PORTEI3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PORTEI3` writer - Port Event Enable Input 3"] +pub struct PORTEI3_W<'a> { + w: &'a mut W, +} +impl<'a> PORTEI3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Port Event Pin Identifier 0"] + #[inline(always)] + pub fn pid0(&self) -> PID0_R { + PID0_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:6 - Port Event Action 0"] + #[inline(always)] + pub fn evact0(&self) -> EVACT0_R { + EVACT0_R::new(((self.bits >> 5) & 0x03) as u8) + } + #[doc = "Bit 7 - Port Event Enable Input 0"] + #[inline(always)] + pub fn portei0(&self) -> PORTEI0_R { + PORTEI0_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:12 - Port Event Pin Identifier 1"] + #[inline(always)] + pub fn pid1(&self) -> PID1_R { + PID1_R::new(((self.bits >> 8) & 0x1f) as u8) + } + #[doc = "Bits 13:14 - Port Event Action 1"] + #[inline(always)] + pub fn evact1(&self) -> EVACT1_R { + EVACT1_R::new(((self.bits >> 13) & 0x03) as u8) + } + #[doc = "Bit 15 - Port Event Enable Input 1"] + #[inline(always)] + pub fn portei1(&self) -> PORTEI1_R { + PORTEI1_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:20 - Port Event Pin Identifier 2"] + #[inline(always)] + pub fn pid2(&self) -> PID2_R { + PID2_R::new(((self.bits >> 16) & 0x1f) as u8) + } + #[doc = "Bits 21:22 - Port Event Action 2"] + #[inline(always)] + pub fn evact2(&self) -> EVACT2_R { + EVACT2_R::new(((self.bits >> 21) & 0x03) as u8) + } + #[doc = "Bit 23 - Port Event Enable Input 2"] + #[inline(always)] + pub fn portei2(&self) -> PORTEI2_R { + PORTEI2_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bits 24:28 - Port Event Pin Identifier 3"] + #[inline(always)] + pub fn pid3(&self) -> PID3_R { + PID3_R::new(((self.bits >> 24) & 0x1f) as u8) + } + #[doc = "Bits 29:30 - Port Event Action 3"] + #[inline(always)] + pub fn evact3(&self) -> EVACT3_R { + EVACT3_R::new(((self.bits >> 29) & 0x03) as u8) + } + #[doc = "Bit 31 - Port Event Enable Input 3"] + #[inline(always)] + pub fn portei3(&self) -> PORTEI3_R { + PORTEI3_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Port Event Pin Identifier 0"] + #[inline(always)] + pub fn pid0(&mut self) -> PID0_W { + PID0_W { w: self } + } + #[doc = "Bits 5:6 - Port Event Action 0"] + #[inline(always)] + pub fn evact0(&mut self) -> EVACT0_W { + EVACT0_W { w: self } + } + #[doc = "Bit 7 - Port Event Enable Input 0"] + #[inline(always)] + pub fn portei0(&mut self) -> PORTEI0_W { + PORTEI0_W { w: self } + } + #[doc = "Bits 8:12 - Port Event Pin Identifier 1"] + #[inline(always)] + pub fn pid1(&mut self) -> PID1_W { + PID1_W { w: self } + } + #[doc = "Bits 13:14 - Port Event Action 1"] + #[inline(always)] + pub fn evact1(&mut self) -> EVACT1_W { + EVACT1_W { w: self } + } + #[doc = "Bit 15 - Port Event Enable Input 1"] + #[inline(always)] + pub fn portei1(&mut self) -> PORTEI1_W { + PORTEI1_W { w: self } + } + #[doc = "Bits 16:20 - Port Event Pin Identifier 2"] + #[inline(always)] + pub fn pid2(&mut self) -> PID2_W { + PID2_W { w: self } + } + #[doc = "Bits 21:22 - Port Event Action 2"] + #[inline(always)] + pub fn evact2(&mut self) -> EVACT2_W { + EVACT2_W { w: self } + } + #[doc = "Bit 23 - Port Event Enable Input 2"] + #[inline(always)] + pub fn portei2(&mut self) -> PORTEI2_W { + PORTEI2_W { w: self } + } + #[doc = "Bits 24:28 - Port Event Pin Identifier 3"] + #[inline(always)] + pub fn pid3(&mut self) -> PID3_W { + PID3_W { w: self } + } + #[doc = "Bits 29:30 - Port Event Action 3"] + #[inline(always)] + pub fn evact3(&mut self) -> EVACT3_W { + EVACT3_W { w: self } + } + #[doc = "Bit 31 - Port Event Enable Input 3"] + #[inline(always)] + pub fn portei3(&mut self) -> PORTEI3_W { + PORTEI3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Input Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/port/group/in_.rs b/pac/atsamc20g/src/port/group/in_.rs new file mode 100644 index 000000000000..1c8e7396a83e --- /dev/null +++ b/pac/atsamc20g/src/port/group/in_.rs @@ -0,0 +1,31 @@ +#[doc = "Register `IN` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Data Input Value\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [in_](index.html) module"] +pub struct IN_SPEC; +impl crate::RegisterSpec for IN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [in_::R](R) reader structure"] +impl crate::Readable for IN_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets IN to value 0"] +impl crate::Resettable for IN_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/port/group/out.rs b/pac/atsamc20g/src/port/group/out.rs new file mode 100644 index 000000000000..092e8dbd8023 --- /dev/null +++ b/pac/atsamc20g/src/port/group/out.rs @@ -0,0 +1,64 @@ +#[doc = "Register `OUT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OUT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Output Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [out](index.html) module"] +pub struct OUT_SPEC; +impl crate::RegisterSpec for OUT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [out::R](R) reader structure"] +impl crate::Readable for OUT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [out::W](W) writer structure"] +impl crate::Writable for OUT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OUT to value 0"] +impl crate::Resettable for OUT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/port/group/outclr.rs b/pac/atsamc20g/src/port/group/outclr.rs new file mode 100644 index 000000000000..6e734396601f --- /dev/null +++ b/pac/atsamc20g/src/port/group/outclr.rs @@ -0,0 +1,64 @@ +#[doc = "Register `OUTCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OUTCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Output Value Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [outclr](index.html) module"] +pub struct OUTCLR_SPEC; +impl crate::RegisterSpec for OUTCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [outclr::R](R) reader structure"] +impl crate::Readable for OUTCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [outclr::W](W) writer structure"] +impl crate::Writable for OUTCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OUTCLR to value 0"] +impl crate::Resettable for OUTCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/port/group/outset.rs b/pac/atsamc20g/src/port/group/outset.rs new file mode 100644 index 000000000000..6d39122deb4b --- /dev/null +++ b/pac/atsamc20g/src/port/group/outset.rs @@ -0,0 +1,64 @@ +#[doc = "Register `OUTSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OUTSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Output Value Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [outset](index.html) module"] +pub struct OUTSET_SPEC; +impl crate::RegisterSpec for OUTSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [outset::R](R) reader structure"] +impl crate::Readable for OUTSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [outset::W](W) writer structure"] +impl crate::Writable for OUTSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OUTSET to value 0"] +impl crate::Resettable for OUTSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/port/group/outtgl.rs b/pac/atsamc20g/src/port/group/outtgl.rs new file mode 100644 index 000000000000..0f3d87d6476d --- /dev/null +++ b/pac/atsamc20g/src/port/group/outtgl.rs @@ -0,0 +1,64 @@ +#[doc = "Register `OUTTGL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OUTTGL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Output Value Toggle\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [outtgl](index.html) module"] +pub struct OUTTGL_SPEC; +impl crate::RegisterSpec for OUTTGL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [outtgl::R](R) reader structure"] +impl crate::Readable for OUTTGL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [outtgl::W](W) writer structure"] +impl crate::Writable for OUTTGL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OUTTGL to value 0"] +impl crate::Resettable for OUTTGL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/port/group/pincfg.rs b/pac/atsamc20g/src/port/group/pincfg.rs new file mode 100644 index 000000000000..920af6550361 --- /dev/null +++ b/pac/atsamc20g/src/port/group/pincfg.rs @@ -0,0 +1,255 @@ +#[doc = "Register `PINCFG[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PINCFG[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PMUXEN` reader - Select Peripheral Multiplexer"] +pub struct PMUXEN_R(crate::FieldReader); +impl PMUXEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PMUXEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PMUXEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PMUXEN` writer - Select Peripheral Multiplexer"] +pub struct PMUXEN_W<'a> { + w: &'a mut W, +} +impl<'a> PMUXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `INEN` reader - Input Enable"] +pub struct INEN_R(crate::FieldReader); +impl INEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INEN` writer - Input Enable"] +pub struct INEN_W<'a> { + w: &'a mut W, +} +impl<'a> INEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PULLEN` reader - Pull Enable"] +pub struct PULLEN_R(crate::FieldReader); +impl PULLEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PULLEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PULLEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PULLEN` writer - Pull Enable"] +pub struct PULLEN_W<'a> { + w: &'a mut W, +} +impl<'a> PULLEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `DRVSTR` reader - Output Driver Strength Selection"] +pub struct DRVSTR_R(crate::FieldReader); +impl DRVSTR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRVSTR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRVSTR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRVSTR` writer - Output Driver Strength Selection"] +pub struct DRVSTR_W<'a> { + w: &'a mut W, +} +impl<'a> DRVSTR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - Select Peripheral Multiplexer"] + #[inline(always)] + pub fn pmuxen(&self) -> PMUXEN_R { + PMUXEN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Input Enable"] + #[inline(always)] + pub fn inen(&self) -> INEN_R { + INEN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Pull Enable"] + #[inline(always)] + pub fn pullen(&self) -> PULLEN_R { + PULLEN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 6 - Output Driver Strength Selection"] + #[inline(always)] + pub fn drvstr(&self) -> DRVSTR_R { + DRVSTR_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Select Peripheral Multiplexer"] + #[inline(always)] + pub fn pmuxen(&mut self) -> PMUXEN_W { + PMUXEN_W { w: self } + } + #[doc = "Bit 1 - Input Enable"] + #[inline(always)] + pub fn inen(&mut self) -> INEN_W { + INEN_W { w: self } + } + #[doc = "Bit 2 - Pull Enable"] + #[inline(always)] + pub fn pullen(&mut self) -> PULLEN_W { + PULLEN_W { w: self } + } + #[doc = "Bit 6 - Output Driver Strength Selection"] + #[inline(always)] + pub fn drvstr(&mut self) -> DRVSTR_W { + DRVSTR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Pin Configuration n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pincfg](index.html) module"] +pub struct PINCFG_SPEC; +impl crate::RegisterSpec for PINCFG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [pincfg::R](R) reader structure"] +impl crate::Readable for PINCFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [pincfg::W](W) writer structure"] +impl crate::Writable for PINCFG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PINCFG[%s] +to value 0"] +impl crate::Resettable for PINCFG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/port/group/pmux.rs b/pac/atsamc20g/src/port/group/pmux.rs new file mode 100644 index 000000000000..79c991a99daf --- /dev/null +++ b/pac/atsamc20g/src/port/group/pmux.rs @@ -0,0 +1,141 @@ +#[doc = "Register `PMUX[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PMUX[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PMUXE` reader - Peripheral Multiplexing for Even-Numbered Pin"] +pub struct PMUXE_R(crate::FieldReader); +impl PMUXE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PMUXE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PMUXE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PMUXE` writer - Peripheral Multiplexing for Even-Numbered Pin"] +pub struct PMUXE_W<'a> { + w: &'a mut W, +} +impl<'a> PMUXE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +#[doc = "Field `PMUXO` reader - Peripheral Multiplexing for Odd-Numbered Pin"] +pub struct PMUXO_R(crate::FieldReader); +impl PMUXO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PMUXO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PMUXO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PMUXO` writer - Peripheral Multiplexing for Odd-Numbered Pin"] +pub struct PMUXO_W<'a> { + w: &'a mut W, +} +impl<'a> PMUXO_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 4)) | ((value as u8 & 0x0f) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Peripheral Multiplexing for Even-Numbered Pin"] + #[inline(always)] + pub fn pmuxe(&self) -> PMUXE_R { + PMUXE_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Peripheral Multiplexing for Odd-Numbered Pin"] + #[inline(always)] + pub fn pmuxo(&self) -> PMUXO_R { + PMUXO_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Peripheral Multiplexing for Even-Numbered Pin"] + #[inline(always)] + pub fn pmuxe(&mut self) -> PMUXE_W { + PMUXE_W { w: self } + } + #[doc = "Bits 4:7 - Peripheral Multiplexing for Odd-Numbered Pin"] + #[inline(always)] + pub fn pmuxo(&mut self) -> PMUXO_W { + PMUXO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Peripheral Multiplexing n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pmux](index.html) module"] +pub struct PMUX_SPEC; +impl crate::RegisterSpec for PMUX_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [pmux::R](R) reader structure"] +impl crate::Readable for PMUX_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [pmux::W](W) writer structure"] +impl crate::Writable for PMUX_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PMUX[%s] +to value 0"] +impl crate::Resettable for PMUX_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/port/group/wrconfig.rs b/pac/atsamc20g/src/port/group/wrconfig.rs new file mode 100644 index 000000000000..c87e4f174728 --- /dev/null +++ b/pac/atsamc20g/src/port/group/wrconfig.rs @@ -0,0 +1,268 @@ +#[doc = "Register `WRCONFIG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PINMASK` writer - Pin Mask for Multiple Pin Configuration"] +pub struct PINMASK_W<'a> { + w: &'a mut W, +} +impl<'a> PINMASK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +#[doc = "Field `PMUXEN` writer - Select Peripheral Multiplexer"] +pub struct PMUXEN_W<'a> { + w: &'a mut W, +} +impl<'a> PMUXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `INEN` writer - Input Enable"] +pub struct INEN_W<'a> { + w: &'a mut W, +} +impl<'a> INEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `PULLEN` writer - Pull Enable"] +pub struct PULLEN_W<'a> { + w: &'a mut W, +} +impl<'a> PULLEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `DRVSTR` writer - Output Driver Strength Selection"] +pub struct DRVSTR_W<'a> { + w: &'a mut W, +} +impl<'a> DRVSTR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `PMUX` writer - Peripheral Multiplexing Template"] +pub struct PMUX_W<'a> { + w: &'a mut W, +} +impl<'a> PMUX_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Field `WRPMUX` writer - Write PMUX Registers"] +pub struct WRPMUX_W<'a> { + w: &'a mut W, +} +impl<'a> WRPMUX_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Field `WRPINCFG` writer - Write PINCFG Registers"] +pub struct WRPINCFG_W<'a> { + w: &'a mut W, +} +impl<'a> WRPINCFG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +#[doc = "Field `HWSEL` writer - Half-Word Select"] +pub struct HWSEL_W<'a> { + w: &'a mut W, +} +impl<'a> HWSEL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl W { + #[doc = "Bits 0:15 - Pin Mask for Multiple Pin Configuration"] + #[inline(always)] + pub fn pinmask(&mut self) -> PINMASK_W { + PINMASK_W { w: self } + } + #[doc = "Bit 16 - Select Peripheral Multiplexer"] + #[inline(always)] + pub fn pmuxen(&mut self) -> PMUXEN_W { + PMUXEN_W { w: self } + } + #[doc = "Bit 17 - Input Enable"] + #[inline(always)] + pub fn inen(&mut self) -> INEN_W { + INEN_W { w: self } + } + #[doc = "Bit 18 - Pull Enable"] + #[inline(always)] + pub fn pullen(&mut self) -> PULLEN_W { + PULLEN_W { w: self } + } + #[doc = "Bit 22 - Output Driver Strength Selection"] + #[inline(always)] + pub fn drvstr(&mut self) -> DRVSTR_W { + DRVSTR_W { w: self } + } + #[doc = "Bits 24:27 - Peripheral Multiplexing Template"] + #[inline(always)] + pub fn pmux(&mut self) -> PMUX_W { + PMUX_W { w: self } + } + #[doc = "Bit 28 - Write PMUX Registers"] + #[inline(always)] + pub fn wrpmux(&mut self) -> WRPMUX_W { + WRPMUX_W { w: self } + } + #[doc = "Bit 30 - Write PINCFG Registers"] + #[inline(always)] + pub fn wrpincfg(&mut self) -> WRPINCFG_W { + WRPINCFG_W { w: self } + } + #[doc = "Bit 31 - Half-Word Select"] + #[inline(always)] + pub fn hwsel(&mut self) -> HWSEL_W { + HWSEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Write Configuration\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wrconfig](index.html) module"] +pub struct WRCONFIG_SPEC; +impl crate::RegisterSpec for WRCONFIG_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [wrconfig::W](W) writer structure"] +impl crate::Writable for WRCONFIG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WRCONFIG to value 0"] +impl crate::Resettable for WRCONFIG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/rstc.rs b/pac/atsamc20g/src/rstc.rs new file mode 100644 index 000000000000..327b511df28a --- /dev/null +++ b/pac/atsamc20g/src/rstc.rs @@ -0,0 +1,10 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Reset Cause"] + pub rcause: crate::Reg, +} +#[doc = "RCAUSE register accessor: an alias for `Reg`"] +pub type RCAUSE = crate::Reg; +#[doc = "Reset Cause"] +pub mod rcause; diff --git a/pac/atsamc20g/src/rstc/rcause.rs b/pac/atsamc20g/src/rstc/rcause.rs new file mode 100644 index 000000000000..3dc13496e74b --- /dev/null +++ b/pac/atsamc20g/src/rstc/rcause.rs @@ -0,0 +1,153 @@ +#[doc = "Register `RCAUSE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `POR` reader - Power On Reset"] +pub struct POR_R(crate::FieldReader); +impl POR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + POR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for POR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODCORE` reader - Brown Out CORE Detector Reset"] +pub struct BODCORE_R(crate::FieldReader); +impl BODCORE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODCORE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODCORE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODVDD` reader - Brown Out VDD Detector Reset"] +pub struct BODVDD_R(crate::FieldReader); +impl BODVDD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODVDD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODVDD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXT` reader - External Reset"] +pub struct EXT_R(crate::FieldReader); +impl EXT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WDT` reader - Watchdog Reset"] +pub struct WDT_R(crate::FieldReader); +impl WDT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WDT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WDT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYST` reader - System Reset Request"] +pub struct SYST_R(crate::FieldReader); +impl SYST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Power On Reset"] + #[inline(always)] + pub fn por(&self) -> POR_R { + POR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Brown Out CORE Detector Reset"] + #[inline(always)] + pub fn bodcore(&self) -> BODCORE_R { + BODCORE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Brown Out VDD Detector Reset"] + #[inline(always)] + pub fn bodvdd(&self) -> BODVDD_R { + BODVDD_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 4 - External Reset"] + #[inline(always)] + pub fn ext(&self) -> EXT_R { + EXT_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Watchdog Reset"] + #[inline(always)] + pub fn wdt(&self) -> WDT_R { + WDT_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - System Reset Request"] + #[inline(always)] + pub fn syst(&self) -> SYST_R { + SYST_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +#[doc = "Reset Cause\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rcause](index.html) module"] +pub struct RCAUSE_SPEC; +impl crate::RegisterSpec for RCAUSE_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [rcause::R](R) reader structure"] +impl crate::Readable for RCAUSE_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets RCAUSE to value 0"] +impl crate::Resettable for RCAUSE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/rtc.rs b/pac/atsamc20g/src/rtc.rs new file mode 100644 index 000000000000..62f424cb1a8e --- /dev/null +++ b/pac/atsamc20g/src/rtc.rs @@ -0,0 +1,120 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved_0_mode0: [u8; 0x25], +} +impl RegisterBlock { + #[doc = "0x00..0x25 - Clock/Calendar with Alarm"] + #[inline(always)] + pub fn mode2(&self) -> &MODE2 { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const MODE2) } + } + #[doc = "0x00..0x24 - 16-bit Counter with Two 16-bit Compares"] + #[inline(always)] + pub fn mode1(&self) -> &MODE1 { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const MODE1) } + } + #[doc = "0x00..0x24 - 32-bit Counter with Single 32-bit Compare"] + #[inline(always)] + pub fn mode0(&self) -> &MODE0 { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const MODE0) } + } +} +#[doc = r"Register block"] +#[repr(C)] +pub struct MODE0 { + #[doc = "0x00 - MODE0 Control A"] + pub ctrla: crate::Reg, + _reserved1: [u8; 0x02], + #[doc = "0x04 - MODE0 Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x08 - MODE0 Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x0a - MODE0 Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x0c - MODE0 Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x0e - Debug Control"] + pub dbgctrl: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x10 - MODE0 Synchronization Busy Status"] + pub syncbusy: crate::Reg, + #[doc = "0x14 - Frequency Correction"] + pub freqcorr: crate::Reg, + _reserved8: [u8; 0x03], + #[doc = "0x18 - MODE0 Counter Value"] + pub count: crate::Reg, + _reserved9: [u8; 0x04], + #[doc = "0x20 - MODE0 Compare n Value"] + pub comp: crate::Reg, +} +#[doc = r"Register block"] +#[doc = "32-bit Counter with Single 32-bit Compare"] +pub mod mode0; +#[doc = r"Register block"] +#[repr(C)] +pub struct MODE1 { + #[doc = "0x00 - MODE1 Control A"] + pub ctrla: crate::Reg, + _reserved1: [u8; 0x02], + #[doc = "0x04 - MODE1 Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x08 - MODE1 Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x0a - MODE1 Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x0c - MODE1 Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x0e - Debug Control"] + pub dbgctrl: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x10 - MODE1 Synchronization Busy Status"] + pub syncbusy: crate::Reg, + #[doc = "0x14 - Frequency Correction"] + pub freqcorr: crate::Reg, + _reserved8: [u8; 0x03], + #[doc = "0x18 - MODE1 Counter Value"] + pub count: crate::Reg, + _reserved9: [u8; 0x02], + #[doc = "0x1c - MODE1 Counter Period"] + pub per: crate::Reg, + _reserved10: [u8; 0x02], + #[doc = "0x20 - MODE1 Compare n Value"] + pub comp: [crate::Reg; 2], +} +#[doc = r"Register block"] +#[doc = "16-bit Counter with Two 16-bit Compares"] +pub mod mode1; +#[doc = r"Register block"] +#[repr(C)] +pub struct MODE2 { + #[doc = "0x00 - MODE2 Control A"] + pub ctrla: crate::Reg, + _reserved1: [u8; 0x02], + #[doc = "0x04 - MODE2 Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x08 - MODE2 Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x0a - MODE2 Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x0c - MODE2 Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x0e - Debug Control"] + pub dbgctrl: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x10 - MODE2 Synchronization Busy Status"] + pub syncbusy: crate::Reg, + #[doc = "0x14 - Frequency Correction"] + pub freqcorr: crate::Reg, + _reserved8: [u8; 0x03], + #[doc = "0x18 - MODE2 Clock Value"] + pub clock: crate::Reg, + _reserved9: [u8; 0x04], + #[doc = "0x20 - MODE2_ALARM Alarm n Value"] + pub alarm: crate::Reg, + #[doc = "0x24 - MODE2_ALARM Alarm n Mask"] + pub mask: crate::Reg, +} +#[doc = r"Register block"] +#[doc = "Clock/Calendar with Alarm"] +pub mod mode2; diff --git a/pac/atsamc20g/src/rtc/mode0.rs b/pac/atsamc20g/src/rtc/mode0.rs new file mode 100644 index 000000000000..9ce5c3808169 --- /dev/null +++ b/pac/atsamc20g/src/rtc/mode0.rs @@ -0,0 +1,40 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "MODE0 Control A"] +pub mod ctrla; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "MODE0 Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "MODE0 Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "MODE0 Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "MODE0 Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "MODE0 Synchronization Busy Status"] +pub mod syncbusy; +#[doc = "FREQCORR register accessor: an alias for `Reg`"] +pub type FREQCORR = crate::Reg; +#[doc = "Frequency Correction"] +pub mod freqcorr; +#[doc = "COUNT register accessor: an alias for `Reg`"] +pub type COUNT = crate::Reg; +#[doc = "MODE0 Counter Value"] +pub mod count; +#[doc = "COMP register accessor: an alias for `Reg`"] +pub type COMP = crate::Reg; +#[doc = "MODE0 Compare n Value"] +pub mod comp; diff --git a/pac/atsamc20g/src/rtc/mode0/comp.rs b/pac/atsamc20g/src/rtc/mode0/comp.rs new file mode 100644 index 000000000000..a909d3cea2d3 --- /dev/null +++ b/pac/atsamc20g/src/rtc/mode0/comp.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COMP` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COMP` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COMP` reader - Compare Value"] +pub struct COMP_R(crate::FieldReader); +impl COMP_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COMP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP` writer - Compare Value"] +pub struct COMP_W<'a> { + w: &'a mut W, +} +impl<'a> COMP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Compare Value"] + #[inline(always)] + pub fn comp(&self) -> COMP_R { + COMP_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Compare Value"] + #[inline(always)] + pub fn comp(&mut self) -> COMP_W { + COMP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE0 Compare n Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [comp](index.html) module"] +pub struct COMP_SPEC; +impl crate::RegisterSpec for COMP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [comp::R](R) reader structure"] +impl crate::Readable for COMP_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [comp::W](W) writer structure"] +impl crate::Writable for COMP_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COMP to value 0"] +impl crate::Resettable for COMP_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/rtc/mode0/count.rs b/pac/atsamc20g/src/rtc/mode0/count.rs new file mode 100644 index 000000000000..cf880b5e77a6 --- /dev/null +++ b/pac/atsamc20g/src/rtc/mode0/count.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE0 Counter Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count](index.html) module"] +pub struct COUNT_SPEC; +impl crate::RegisterSpec for COUNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [count::R](R) reader structure"] +impl crate::Readable for COUNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count::W](W) writer structure"] +impl crate::Writable for COUNT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT to value 0"] +impl crate::Resettable for COUNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/rtc/mode0/ctrla.rs b/pac/atsamc20g/src/rtc/mode0/ctrla.rs new file mode 100644 index 000000000000..423877bd087d --- /dev/null +++ b/pac/atsamc20g/src/rtc/mode0/ctrla.rs @@ -0,0 +1,569 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: Mode 0: 32-bit Counter"] + COUNT32 = 0, + #[doc = "1: Mode 1: 16-bit Counter"] + COUNT16 = 1, + #[doc = "2: Mode 2: Clock/Calendar"] + CLOCK = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::COUNT32), + 1 => Some(MODE_A::COUNT16), + 2 => Some(MODE_A::CLOCK), + _ => None, + } + } + #[doc = "Checks if the value of the field is `COUNT32`"] + #[inline(always)] + pub fn is_count32(&self) -> bool { + **self == MODE_A::COUNT32 + } + #[doc = "Checks if the value of the field is `COUNT16`"] + #[inline(always)] + pub fn is_count16(&self) -> bool { + **self == MODE_A::COUNT16 + } + #[doc = "Checks if the value of the field is `CLOCK`"] + #[inline(always)] + pub fn is_clock(&self) -> bool { + **self == MODE_A::CLOCK + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Mode 0: 32-bit Counter"] + #[inline(always)] + pub fn count32(self) -> &'a mut W { + self.variant(MODE_A::COUNT32) + } + #[doc = "Mode 1: 16-bit Counter"] + #[inline(always)] + pub fn count16(self) -> &'a mut W { + self.variant(MODE_A::COUNT16) + } + #[doc = "Mode 2: Clock/Calendar"] + #[inline(always)] + pub fn clock(self) -> &'a mut W { + self.variant(MODE_A::CLOCK) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u16 & 0x03) << 2); + self.w + } +} +#[doc = "Field `MATCHCLR` reader - Clear on Match"] +pub struct MATCHCLR_R(crate::FieldReader); +impl MATCHCLR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MATCHCLR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MATCHCLR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MATCHCLR` writer - Clear on Match"] +pub struct MATCHCLR_W<'a> { + w: &'a mut W, +} +impl<'a> MATCHCLR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: CLK_RTC_CNT = GCLK_RTC/1"] + OFF = 0, + #[doc = "1: CLK_RTC_CNT = GCLK_RTC/1"] + DIV1 = 1, + #[doc = "2: CLK_RTC_CNT = GCLK_RTC/2"] + DIV2 = 2, + #[doc = "3: CLK_RTC_CNT = GCLK_RTC/4"] + DIV4 = 3, + #[doc = "4: CLK_RTC_CNT = GCLK_RTC/8"] + DIV8 = 4, + #[doc = "5: CLK_RTC_CNT = GCLK_RTC/16"] + DIV16 = 5, + #[doc = "6: CLK_RTC_CNT = GCLK_RTC/32"] + DIV32 = 6, + #[doc = "7: CLK_RTC_CNT = GCLK_RTC/64"] + DIV64 = 7, + #[doc = "8: CLK_RTC_CNT = GCLK_RTC/128"] + DIV128 = 8, + #[doc = "9: CLK_RTC_CNT = GCLK_RTC/256"] + DIV256 = 9, + #[doc = "10: CLK_RTC_CNT = GCLK_RTC/512"] + DIV512 = 10, + #[doc = "11: CLK_RTC_CNT = GCLK_RTC/1024"] + DIV1024 = 11, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCALER_A::OFF), + 1 => Some(PRESCALER_A::DIV1), + 2 => Some(PRESCALER_A::DIV2), + 3 => Some(PRESCALER_A::DIV4), + 4 => Some(PRESCALER_A::DIV8), + 5 => Some(PRESCALER_A::DIV16), + 6 => Some(PRESCALER_A::DIV32), + 7 => Some(PRESCALER_A::DIV64), + 8 => Some(PRESCALER_A::DIV128), + 9 => Some(PRESCALER_A::DIV256), + 10 => Some(PRESCALER_A::DIV512), + 11 => Some(PRESCALER_A::DIV1024), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == PRESCALER_A::OFF + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == PRESCALER_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == PRESCALER_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == PRESCALER_A::DIV128 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV512`"] + #[inline(always)] + pub fn is_div512(&self) -> bool { + **self == PRESCALER_A::DIV512 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PRESCALER_A::DIV1024 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(PRESCALER_A::OFF) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV32) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV128) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/512"] + #[inline(always)] + pub fn div512(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV512) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 8)) | ((value as u16 & 0x0f) << 8); + self.w + } +} +#[doc = "Field `COUNTSYNC` reader - Count Read Synchronization Enable"] +pub struct COUNTSYNC_R(crate::FieldReader); +impl COUNTSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNTSYNC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNTSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNTSYNC` writer - Count Read Synchronization Enable"] +pub struct COUNTSYNC_W<'a> { + w: &'a mut W, +} +impl<'a> COUNTSYNC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:3 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bit 7 - Clear on Match"] + #[inline(always)] + pub fn matchclr(&self) -> MATCHCLR_R { + MATCHCLR_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:11 - Prescaler"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 15 - Count Read Synchronization Enable"] + #[inline(always)] + pub fn countsync(&self) -> COUNTSYNC_R { + COUNTSYNC_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:3 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 7 - Clear on Match"] + #[inline(always)] + pub fn matchclr(&mut self) -> MATCHCLR_W { + MATCHCLR_W { w: self } + } + #[doc = "Bits 8:11 - Prescaler"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Bit 15 - Count Read Synchronization Enable"] + #[inline(always)] + pub fn countsync(&mut self) -> COUNTSYNC_W { + COUNTSYNC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE0 Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/rtc/mode0/dbgctrl.rs b/pac/atsamc20g/src/rtc/mode0/dbgctrl.rs new file mode 100644 index 000000000000..0383e70d0429 --- /dev/null +++ b/pac/atsamc20g/src/rtc/mode0/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Run During Debug"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Run During Debug"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/rtc/mode0/evctrl.rs b/pac/atsamc20g/src/rtc/mode0/evctrl.rs new file mode 100644 index 000000000000..c73647759dbe --- /dev/null +++ b/pac/atsamc20g/src/rtc/mode0/evctrl.rs @@ -0,0 +1,536 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PEREO0` reader - Periodic Interval 0 Event Output Enable"] +pub struct PEREO0_R(crate::FieldReader); +impl PEREO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO0` writer - Periodic Interval 0 Event Output Enable"] +pub struct PEREO0_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `PEREO1` reader - Periodic Interval 1 Event Output Enable"] +pub struct PEREO1_R(crate::FieldReader); +impl PEREO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO1` writer - Periodic Interval 1 Event Output Enable"] +pub struct PEREO1_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PEREO2` reader - Periodic Interval 2 Event Output Enable"] +pub struct PEREO2_R(crate::FieldReader); +impl PEREO2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO2` writer - Periodic Interval 2 Event Output Enable"] +pub struct PEREO2_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PEREO3` reader - Periodic Interval 3 Event Output Enable"] +pub struct PEREO3_R(crate::FieldReader); +impl PEREO3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO3` writer - Periodic Interval 3 Event Output Enable"] +pub struct PEREO3_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PEREO4` reader - Periodic Interval 4 Event Output Enable"] +pub struct PEREO4_R(crate::FieldReader); +impl PEREO4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO4` writer - Periodic Interval 4 Event Output Enable"] +pub struct PEREO4_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PEREO5` reader - Periodic Interval 5 Event Output Enable"] +pub struct PEREO5_R(crate::FieldReader); +impl PEREO5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO5` writer - Periodic Interval 5 Event Output Enable"] +pub struct PEREO5_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PEREO6` reader - Periodic Interval 6 Event Output Enable"] +pub struct PEREO6_R(crate::FieldReader); +impl PEREO6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO6` writer - Periodic Interval 6 Event Output Enable"] +pub struct PEREO6_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PEREO7` reader - Periodic Interval 7 Event Output Enable"] +pub struct PEREO7_R(crate::FieldReader); +impl PEREO7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO7` writer - Periodic Interval 7 Event Output Enable"] +pub struct PEREO7_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CMPEO0` reader - Compare 0 Event Output Enable"] +pub struct CMPEO0_R(crate::FieldReader); +impl CMPEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMPEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMPEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMPEO0` writer - Compare 0 Event Output Enable"] +pub struct CMPEO0_W<'a> { + w: &'a mut W, +} +impl<'a> CMPEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `OVFEO` reader - Overflow Event Output Enable"] +pub struct OVFEO_R(crate::FieldReader); +impl OVFEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVFEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVFEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVFEO` writer - Overflow Event Output Enable"] +pub struct OVFEO_W<'a> { + w: &'a mut W, +} +impl<'a> OVFEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Event Output Enable"] + #[inline(always)] + pub fn pereo0(&self) -> PEREO0_R { + PEREO0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Event Output Enable"] + #[inline(always)] + pub fn pereo1(&self) -> PEREO1_R { + PEREO1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Event Output Enable"] + #[inline(always)] + pub fn pereo2(&self) -> PEREO2_R { + PEREO2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Event Output Enable"] + #[inline(always)] + pub fn pereo3(&self) -> PEREO3_R { + PEREO3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Event Output Enable"] + #[inline(always)] + pub fn pereo4(&self) -> PEREO4_R { + PEREO4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Event Output Enable"] + #[inline(always)] + pub fn pereo5(&self) -> PEREO5_R { + PEREO5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Event Output Enable"] + #[inline(always)] + pub fn pereo6(&self) -> PEREO6_R { + PEREO6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Event Output Enable"] + #[inline(always)] + pub fn pereo7(&self) -> PEREO7_R { + PEREO7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Compare 0 Event Output Enable"] + #[inline(always)] + pub fn cmpeo0(&self) -> CMPEO0_R { + CMPEO0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&self) -> OVFEO_R { + OVFEO_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Event Output Enable"] + #[inline(always)] + pub fn pereo0(&mut self) -> PEREO0_W { + PEREO0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1 Event Output Enable"] + #[inline(always)] + pub fn pereo1(&mut self) -> PEREO1_W { + PEREO1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2 Event Output Enable"] + #[inline(always)] + pub fn pereo2(&mut self) -> PEREO2_W { + PEREO2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3 Event Output Enable"] + #[inline(always)] + pub fn pereo3(&mut self) -> PEREO3_W { + PEREO3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4 Event Output Enable"] + #[inline(always)] + pub fn pereo4(&mut self) -> PEREO4_W { + PEREO4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5 Event Output Enable"] + #[inline(always)] + pub fn pereo5(&mut self) -> PEREO5_W { + PEREO5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6 Event Output Enable"] + #[inline(always)] + pub fn pereo6(&mut self) -> PEREO6_W { + PEREO6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7 Event Output Enable"] + #[inline(always)] + pub fn pereo7(&mut self) -> PEREO7_W { + PEREO7_W { w: self } + } + #[doc = "Bit 8 - Compare 0 Event Output Enable"] + #[inline(always)] + pub fn cmpeo0(&mut self) -> CMPEO0_W { + CMPEO0_W { w: self } + } + #[doc = "Bit 15 - Overflow Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&mut self) -> OVFEO_W { + OVFEO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE0 Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/rtc/mode0/freqcorr.rs b/pac/atsamc20g/src/rtc/mode0/freqcorr.rs new file mode 100644 index 000000000000..043ba6f88eb2 --- /dev/null +++ b/pac/atsamc20g/src/rtc/mode0/freqcorr.rs @@ -0,0 +1,150 @@ +#[doc = "Register `FREQCORR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FREQCORR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `VALUE` reader - Correction Value"] +pub struct VALUE_R(crate::FieldReader); +impl VALUE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + VALUE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VALUE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VALUE` writer - Correction Value"] +pub struct VALUE_W<'a> { + w: &'a mut W, +} +impl<'a> VALUE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x7f) | (value as u8 & 0x7f); + self.w + } +} +#[doc = "Field `SIGN` reader - Correction Sign"] +pub struct SIGN_R(crate::FieldReader); +impl SIGN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SIGN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SIGN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SIGN` writer - Correction Sign"] +pub struct SIGN_W<'a> { + w: &'a mut W, +} +impl<'a> SIGN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bits 0:6 - Correction Value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bit 7 - Correction Sign"] + #[inline(always)] + pub fn sign(&self) -> SIGN_R { + SIGN_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:6 - Correction Value"] + #[inline(always)] + pub fn value(&mut self) -> VALUE_W { + VALUE_W { w: self } + } + #[doc = "Bit 7 - Correction Sign"] + #[inline(always)] + pub fn sign(&mut self) -> SIGN_W { + SIGN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Frequency Correction\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [freqcorr](index.html) module"] +pub struct FREQCORR_SPEC; +impl crate::RegisterSpec for FREQCORR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [freqcorr::R](R) reader structure"] +impl crate::Readable for FREQCORR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [freqcorr::W](W) writer structure"] +impl crate::Writable for FREQCORR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets FREQCORR to value 0"] +impl crate::Resettable for FREQCORR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/rtc/mode0/intenclr.rs b/pac/atsamc20g/src/rtc/mode0/intenclr.rs new file mode 100644 index 000000000000..8be5e2c3920b --- /dev/null +++ b/pac/atsamc20g/src/rtc/mode0/intenclr.rs @@ -0,0 +1,536 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER0` reader - Periodic Interval 0 Interrupt Enable"] +pub struct PER0_R(crate::FieldReader); +impl PER0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER0` writer - Periodic Interval 0 Interrupt Enable"] +pub struct PER0_W<'a> { + w: &'a mut W, +} +impl<'a> PER0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PER1` reader - Periodic Interval 1 Interrupt Enable"] +pub struct PER1_R(crate::FieldReader); +impl PER1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER1` writer - Periodic Interval 1 Interrupt Enable"] +pub struct PER1_W<'a> { + w: &'a mut W, +} +impl<'a> PER1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PER2` reader - Periodic Interval 2 Interrupt Enable"] +pub struct PER2_R(crate::FieldReader); +impl PER2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER2` writer - Periodic Interval 2 Interrupt Enable"] +pub struct PER2_W<'a> { + w: &'a mut W, +} +impl<'a> PER2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PER3` reader - Periodic Interval 3 Interrupt Enable"] +pub struct PER3_R(crate::FieldReader); +impl PER3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER3` writer - Periodic Interval 3 Interrupt Enable"] +pub struct PER3_W<'a> { + w: &'a mut W, +} +impl<'a> PER3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PER4` reader - Periodic Interval 4 Interrupt Enable"] +pub struct PER4_R(crate::FieldReader); +impl PER4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER4` writer - Periodic Interval 4 Interrupt Enable"] +pub struct PER4_W<'a> { + w: &'a mut W, +} +impl<'a> PER4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PER5` reader - Periodic Interval 5 Interrupt Enable"] +pub struct PER5_R(crate::FieldReader); +impl PER5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER5` writer - Periodic Interval 5 Interrupt Enable"] +pub struct PER5_W<'a> { + w: &'a mut W, +} +impl<'a> PER5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PER6` reader - Periodic Interval 6 Interrupt Enable"] +pub struct PER6_R(crate::FieldReader); +impl PER6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER6` writer - Periodic Interval 6 Interrupt Enable"] +pub struct PER6_W<'a> { + w: &'a mut W, +} +impl<'a> PER6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PER7` reader - Periodic Interval 7 Interrupt Enable"] +pub struct PER7_R(crate::FieldReader); +impl PER7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER7` writer - Periodic Interval 7 Interrupt Enable"] +pub struct PER7_W<'a> { + w: &'a mut W, +} +impl<'a> PER7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CMP0` reader - Compare 0 Interrupt Enable"] +pub struct CMP0_R(crate::FieldReader); +impl CMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP0` writer - Compare 0 Interrupt Enable"] +pub struct CMP0_W<'a> { + w: &'a mut W, +} +impl<'a> CMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + pub fn per0(&self) -> PER0_R { + PER0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + pub fn per1(&self) -> PER1_R { + PER1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + pub fn per2(&self) -> PER2_R { + PER2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + pub fn per3(&self) -> PER3_R { + PER3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + pub fn per4(&self) -> PER4_R { + PER4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + pub fn per5(&self) -> PER5_R { + PER5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + pub fn per6(&self) -> PER6_R { + PER6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + pub fn per7(&self) -> PER7_R { + PER7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&self) -> CMP0_R { + CMP0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + pub fn per0(&mut self) -> PER0_W { + PER0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + pub fn per1(&mut self) -> PER1_W { + PER1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + pub fn per2(&mut self) -> PER2_W { + PER2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + pub fn per3(&mut self) -> PER3_W { + PER3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + pub fn per4(&mut self) -> PER4_W { + PER4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + pub fn per5(&mut self) -> PER5_W { + PER5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + pub fn per6(&mut self) -> PER6_W { + PER6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + pub fn per7(&mut self) -> PER7_W { + PER7_W { w: self } + } + #[doc = "Bit 8 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&mut self) -> CMP0_W { + CMP0_W { w: self } + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE0 Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/rtc/mode0/intenset.rs b/pac/atsamc20g/src/rtc/mode0/intenset.rs new file mode 100644 index 000000000000..7228f5d486f5 --- /dev/null +++ b/pac/atsamc20g/src/rtc/mode0/intenset.rs @@ -0,0 +1,536 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER0` reader - Periodic Interval 0 Interrupt Enable"] +pub struct PER0_R(crate::FieldReader); +impl PER0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER0` writer - Periodic Interval 0 Interrupt Enable"] +pub struct PER0_W<'a> { + w: &'a mut W, +} +impl<'a> PER0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PER1` reader - Periodic Interval 1 Interrupt Enable"] +pub struct PER1_R(crate::FieldReader); +impl PER1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER1` writer - Periodic Interval 1 Interrupt Enable"] +pub struct PER1_W<'a> { + w: &'a mut W, +} +impl<'a> PER1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PER2` reader - Periodic Interval 2 Interrupt Enable"] +pub struct PER2_R(crate::FieldReader); +impl PER2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER2` writer - Periodic Interval 2 Interrupt Enable"] +pub struct PER2_W<'a> { + w: &'a mut W, +} +impl<'a> PER2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PER3` reader - Periodic Interval 3 Interrupt Enable"] +pub struct PER3_R(crate::FieldReader); +impl PER3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER3` writer - Periodic Interval 3 Interrupt Enable"] +pub struct PER3_W<'a> { + w: &'a mut W, +} +impl<'a> PER3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PER4` reader - Periodic Interval 4 Interrupt Enable"] +pub struct PER4_R(crate::FieldReader); +impl PER4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER4` writer - Periodic Interval 4 Interrupt Enable"] +pub struct PER4_W<'a> { + w: &'a mut W, +} +impl<'a> PER4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PER5` reader - Periodic Interval 5 Interrupt Enable"] +pub struct PER5_R(crate::FieldReader); +impl PER5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER5` writer - Periodic Interval 5 Interrupt Enable"] +pub struct PER5_W<'a> { + w: &'a mut W, +} +impl<'a> PER5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PER6` reader - Periodic Interval 6 Interrupt Enable"] +pub struct PER6_R(crate::FieldReader); +impl PER6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER6` writer - Periodic Interval 6 Interrupt Enable"] +pub struct PER6_W<'a> { + w: &'a mut W, +} +impl<'a> PER6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PER7` reader - Periodic Interval 7 Interrupt Enable"] +pub struct PER7_R(crate::FieldReader); +impl PER7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER7` writer - Periodic Interval 7 Interrupt Enable"] +pub struct PER7_W<'a> { + w: &'a mut W, +} +impl<'a> PER7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CMP0` reader - Compare 0 Interrupt Enable"] +pub struct CMP0_R(crate::FieldReader); +impl CMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP0` writer - Compare 0 Interrupt Enable"] +pub struct CMP0_W<'a> { + w: &'a mut W, +} +impl<'a> CMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + pub fn per0(&self) -> PER0_R { + PER0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + pub fn per1(&self) -> PER1_R { + PER1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + pub fn per2(&self) -> PER2_R { + PER2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + pub fn per3(&self) -> PER3_R { + PER3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + pub fn per4(&self) -> PER4_R { + PER4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + pub fn per5(&self) -> PER5_R { + PER5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + pub fn per6(&self) -> PER6_R { + PER6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + pub fn per7(&self) -> PER7_R { + PER7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&self) -> CMP0_R { + CMP0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + pub fn per0(&mut self) -> PER0_W { + PER0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + pub fn per1(&mut self) -> PER1_W { + PER1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + pub fn per2(&mut self) -> PER2_W { + PER2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + pub fn per3(&mut self) -> PER3_W { + PER3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + pub fn per4(&mut self) -> PER4_W { + PER4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + pub fn per5(&mut self) -> PER5_W { + PER5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + pub fn per6(&mut self) -> PER6_W { + PER6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + pub fn per7(&mut self) -> PER7_W { + PER7_W { w: self } + } + #[doc = "Bit 8 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&mut self) -> CMP0_W { + CMP0_W { w: self } + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE0 Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/rtc/mode0/intflag.rs b/pac/atsamc20g/src/rtc/mode0/intflag.rs new file mode 100644 index 000000000000..f2dccdb04aa4 --- /dev/null +++ b/pac/atsamc20g/src/rtc/mode0/intflag.rs @@ -0,0 +1,536 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER0` reader - Periodic Interval 0"] +pub struct PER0_R(crate::FieldReader); +impl PER0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER0` writer - Periodic Interval 0"] +pub struct PER0_W<'a> { + w: &'a mut W, +} +impl<'a> PER0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PER1` reader - Periodic Interval 1"] +pub struct PER1_R(crate::FieldReader); +impl PER1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER1` writer - Periodic Interval 1"] +pub struct PER1_W<'a> { + w: &'a mut W, +} +impl<'a> PER1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PER2` reader - Periodic Interval 2"] +pub struct PER2_R(crate::FieldReader); +impl PER2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER2` writer - Periodic Interval 2"] +pub struct PER2_W<'a> { + w: &'a mut W, +} +impl<'a> PER2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PER3` reader - Periodic Interval 3"] +pub struct PER3_R(crate::FieldReader); +impl PER3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER3` writer - Periodic Interval 3"] +pub struct PER3_W<'a> { + w: &'a mut W, +} +impl<'a> PER3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PER4` reader - Periodic Interval 4"] +pub struct PER4_R(crate::FieldReader); +impl PER4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER4` writer - Periodic Interval 4"] +pub struct PER4_W<'a> { + w: &'a mut W, +} +impl<'a> PER4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PER5` reader - Periodic Interval 5"] +pub struct PER5_R(crate::FieldReader); +impl PER5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER5` writer - Periodic Interval 5"] +pub struct PER5_W<'a> { + w: &'a mut W, +} +impl<'a> PER5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PER6` reader - Periodic Interval 6"] +pub struct PER6_R(crate::FieldReader); +impl PER6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER6` writer - Periodic Interval 6"] +pub struct PER6_W<'a> { + w: &'a mut W, +} +impl<'a> PER6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PER7` reader - Periodic Interval 7"] +pub struct PER7_R(crate::FieldReader); +impl PER7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER7` writer - Periodic Interval 7"] +pub struct PER7_W<'a> { + w: &'a mut W, +} +impl<'a> PER7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CMP0` reader - Compare 0"] +pub struct CMP0_R(crate::FieldReader); +impl CMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP0` writer - Compare 0"] +pub struct CMP0_W<'a> { + w: &'a mut W, +} +impl<'a> CMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0"] + #[inline(always)] + pub fn per0(&self) -> PER0_R { + PER0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1"] + #[inline(always)] + pub fn per1(&self) -> PER1_R { + PER1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2"] + #[inline(always)] + pub fn per2(&self) -> PER2_R { + PER2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3"] + #[inline(always)] + pub fn per3(&self) -> PER3_R { + PER3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4"] + #[inline(always)] + pub fn per4(&self) -> PER4_R { + PER4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5"] + #[inline(always)] + pub fn per5(&self) -> PER5_R { + PER5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6"] + #[inline(always)] + pub fn per6(&self) -> PER6_R { + PER6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7"] + #[inline(always)] + pub fn per7(&self) -> PER7_R { + PER7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Compare 0"] + #[inline(always)] + pub fn cmp0(&self) -> CMP0_R { + CMP0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0"] + #[inline(always)] + pub fn per0(&mut self) -> PER0_W { + PER0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1"] + #[inline(always)] + pub fn per1(&mut self) -> PER1_W { + PER1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2"] + #[inline(always)] + pub fn per2(&mut self) -> PER2_W { + PER2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3"] + #[inline(always)] + pub fn per3(&mut self) -> PER3_W { + PER3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4"] + #[inline(always)] + pub fn per4(&mut self) -> PER4_W { + PER4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5"] + #[inline(always)] + pub fn per5(&mut self) -> PER5_W { + PER5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6"] + #[inline(always)] + pub fn per6(&mut self) -> PER6_W { + PER6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7"] + #[inline(always)] + pub fn per7(&mut self) -> PER7_W { + PER7_W { w: self } + } + #[doc = "Bit 8 - Compare 0"] + #[inline(always)] + pub fn cmp0(&mut self) -> CMP0_W { + CMP0_W { w: self } + } + #[doc = "Bit 15 - Overflow"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE0 Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/rtc/mode0/syncbusy.rs b/pac/atsamc20g/src/rtc/mode0/syncbusy.rs new file mode 100644 index 000000000000..518dea115a18 --- /dev/null +++ b/pac/atsamc20g/src/rtc/mode0/syncbusy.rs @@ -0,0 +1,153 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - Enable Bit Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FREQCORR` reader - FREQCORR Register Busy"] +pub struct FREQCORR_R(crate::FieldReader); +impl FREQCORR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FREQCORR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FREQCORR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` reader - COUNT Register Busy"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP0` reader - COMP 0 Register Busy"] +pub struct COMP0_R(crate::FieldReader); +impl COMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNTSYNC` reader - Count Read Synchronization Enable Bit Busy"] +pub struct COUNTSYNC_R(crate::FieldReader); +impl COUNTSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNTSYNC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNTSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable Bit Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - FREQCORR Register Busy"] + #[inline(always)] + pub fn freqcorr(&self) -> FREQCORR_R { + FREQCORR_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - COUNT Register Busy"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 5 - COMP 0 Register Busy"] + #[inline(always)] + pub fn comp0(&self) -> COMP0_R { + COMP0_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 15 - Count Read Synchronization Enable Bit Busy"] + #[inline(always)] + pub fn countsync(&self) -> COUNTSYNC_R { + COUNTSYNC_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +#[doc = "MODE0 Synchronization Busy Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/rtc/mode1.rs b/pac/atsamc20g/src/rtc/mode1.rs new file mode 100644 index 000000000000..9ea1bc17497c --- /dev/null +++ b/pac/atsamc20g/src/rtc/mode1.rs @@ -0,0 +1,44 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "MODE1 Control A"] +pub mod ctrla; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "MODE1 Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "MODE1 Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "MODE1 Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "MODE1 Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "MODE1 Synchronization Busy Status"] +pub mod syncbusy; +#[doc = "FREQCORR register accessor: an alias for `Reg`"] +pub type FREQCORR = crate::Reg; +#[doc = "Frequency Correction"] +pub mod freqcorr; +#[doc = "COUNT register accessor: an alias for `Reg`"] +pub type COUNT = crate::Reg; +#[doc = "MODE1 Counter Value"] +pub mod count; +#[doc = "PER register accessor: an alias for `Reg`"] +pub type PER = crate::Reg; +#[doc = "MODE1 Counter Period"] +pub mod per; +#[doc = "COMP register accessor: an alias for `Reg`"] +pub type COMP = crate::Reg; +#[doc = "MODE1 Compare n Value"] +pub mod comp; diff --git a/pac/atsamc20g/src/rtc/mode1/comp.rs b/pac/atsamc20g/src/rtc/mode1/comp.rs new file mode 100644 index 000000000000..6935385840f1 --- /dev/null +++ b/pac/atsamc20g/src/rtc/mode1/comp.rs @@ -0,0 +1,104 @@ +#[doc = "Register `COMP[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COMP[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COMP` reader - Compare Value"] +pub struct COMP_R(crate::FieldReader); +impl COMP_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + COMP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP` writer - Compare Value"] +pub struct COMP_W<'a> { + w: &'a mut W, +} +impl<'a> COMP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Compare Value"] + #[inline(always)] + pub fn comp(&self) -> COMP_R { + COMP_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Compare Value"] + #[inline(always)] + pub fn comp(&mut self) -> COMP_W { + COMP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Compare n Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [comp](index.html) module"] +pub struct COMP_SPEC; +impl crate::RegisterSpec for COMP_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [comp::R](R) reader structure"] +impl crate::Readable for COMP_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [comp::W](W) writer structure"] +impl crate::Writable for COMP_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COMP[%s] +to value 0"] +impl crate::Resettable for COMP_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/rtc/mode1/count.rs b/pac/atsamc20g/src/rtc/mode1/count.rs new file mode 100644 index 000000000000..2c41937b189c --- /dev/null +++ b/pac/atsamc20g/src/rtc/mode1/count.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Counter Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count](index.html) module"] +pub struct COUNT_SPEC; +impl crate::RegisterSpec for COUNT_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [count::R](R) reader structure"] +impl crate::Readable for COUNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count::W](W) writer structure"] +impl crate::Writable for COUNT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT to value 0"] +impl crate::Resettable for COUNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/rtc/mode1/ctrla.rs b/pac/atsamc20g/src/rtc/mode1/ctrla.rs new file mode 100644 index 000000000000..6e3e2042a9c4 --- /dev/null +++ b/pac/atsamc20g/src/rtc/mode1/ctrla.rs @@ -0,0 +1,522 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: Mode 0: 32-bit Counter"] + COUNT32 = 0, + #[doc = "1: Mode 1: 16-bit Counter"] + COUNT16 = 1, + #[doc = "2: Mode 2: Clock/Calendar"] + CLOCK = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::COUNT32), + 1 => Some(MODE_A::COUNT16), + 2 => Some(MODE_A::CLOCK), + _ => None, + } + } + #[doc = "Checks if the value of the field is `COUNT32`"] + #[inline(always)] + pub fn is_count32(&self) -> bool { + **self == MODE_A::COUNT32 + } + #[doc = "Checks if the value of the field is `COUNT16`"] + #[inline(always)] + pub fn is_count16(&self) -> bool { + **self == MODE_A::COUNT16 + } + #[doc = "Checks if the value of the field is `CLOCK`"] + #[inline(always)] + pub fn is_clock(&self) -> bool { + **self == MODE_A::CLOCK + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Mode 0: 32-bit Counter"] + #[inline(always)] + pub fn count32(self) -> &'a mut W { + self.variant(MODE_A::COUNT32) + } + #[doc = "Mode 1: 16-bit Counter"] + #[inline(always)] + pub fn count16(self) -> &'a mut W { + self.variant(MODE_A::COUNT16) + } + #[doc = "Mode 2: Clock/Calendar"] + #[inline(always)] + pub fn clock(self) -> &'a mut W { + self.variant(MODE_A::CLOCK) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u16 & 0x03) << 2); + self.w + } +} +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: CLK_RTC_CNT = GCLK_RTC/1"] + OFF = 0, + #[doc = "1: CLK_RTC_CNT = GCLK_RTC/1"] + DIV1 = 1, + #[doc = "2: CLK_RTC_CNT = GCLK_RTC/2"] + DIV2 = 2, + #[doc = "3: CLK_RTC_CNT = GCLK_RTC/4"] + DIV4 = 3, + #[doc = "4: CLK_RTC_CNT = GCLK_RTC/8"] + DIV8 = 4, + #[doc = "5: CLK_RTC_CNT = GCLK_RTC/16"] + DIV16 = 5, + #[doc = "6: CLK_RTC_CNT = GCLK_RTC/32"] + DIV32 = 6, + #[doc = "7: CLK_RTC_CNT = GCLK_RTC/64"] + DIV64 = 7, + #[doc = "8: CLK_RTC_CNT = GCLK_RTC/128"] + DIV128 = 8, + #[doc = "9: CLK_RTC_CNT = GCLK_RTC/256"] + DIV256 = 9, + #[doc = "10: CLK_RTC_CNT = GCLK_RTC/512"] + DIV512 = 10, + #[doc = "11: CLK_RTC_CNT = GCLK_RTC/1024"] + DIV1024 = 11, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCALER_A::OFF), + 1 => Some(PRESCALER_A::DIV1), + 2 => Some(PRESCALER_A::DIV2), + 3 => Some(PRESCALER_A::DIV4), + 4 => Some(PRESCALER_A::DIV8), + 5 => Some(PRESCALER_A::DIV16), + 6 => Some(PRESCALER_A::DIV32), + 7 => Some(PRESCALER_A::DIV64), + 8 => Some(PRESCALER_A::DIV128), + 9 => Some(PRESCALER_A::DIV256), + 10 => Some(PRESCALER_A::DIV512), + 11 => Some(PRESCALER_A::DIV1024), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == PRESCALER_A::OFF + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == PRESCALER_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == PRESCALER_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == PRESCALER_A::DIV128 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV512`"] + #[inline(always)] + pub fn is_div512(&self) -> bool { + **self == PRESCALER_A::DIV512 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PRESCALER_A::DIV1024 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(PRESCALER_A::OFF) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV32) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV128) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/512"] + #[inline(always)] + pub fn div512(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV512) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 8)) | ((value as u16 & 0x0f) << 8); + self.w + } +} +#[doc = "Field `COUNTSYNC` reader - Count Read Synchronization Enable"] +pub struct COUNTSYNC_R(crate::FieldReader); +impl COUNTSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNTSYNC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNTSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNTSYNC` writer - Count Read Synchronization Enable"] +pub struct COUNTSYNC_W<'a> { + w: &'a mut W, +} +impl<'a> COUNTSYNC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:3 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bits 8:11 - Prescaler"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 15 - Count Read Synchronization Enable"] + #[inline(always)] + pub fn countsync(&self) -> COUNTSYNC_R { + COUNTSYNC_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:3 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bits 8:11 - Prescaler"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Bit 15 - Count Read Synchronization Enable"] + #[inline(always)] + pub fn countsync(&mut self) -> COUNTSYNC_W { + COUNTSYNC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/rtc/mode1/dbgctrl.rs b/pac/atsamc20g/src/rtc/mode1/dbgctrl.rs new file mode 100644 index 000000000000..0383e70d0429 --- /dev/null +++ b/pac/atsamc20g/src/rtc/mode1/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Run During Debug"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Run During Debug"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/rtc/mode1/evctrl.rs b/pac/atsamc20g/src/rtc/mode1/evctrl.rs new file mode 100644 index 000000000000..e15624f828c7 --- /dev/null +++ b/pac/atsamc20g/src/rtc/mode1/evctrl.rs @@ -0,0 +1,583 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PEREO0` reader - Periodic Interval 0 Event Output Enable"] +pub struct PEREO0_R(crate::FieldReader); +impl PEREO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO0` writer - Periodic Interval 0 Event Output Enable"] +pub struct PEREO0_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `PEREO1` reader - Periodic Interval 1 Event Output Enable"] +pub struct PEREO1_R(crate::FieldReader); +impl PEREO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO1` writer - Periodic Interval 1 Event Output Enable"] +pub struct PEREO1_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PEREO2` reader - Periodic Interval 2 Event Output Enable"] +pub struct PEREO2_R(crate::FieldReader); +impl PEREO2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO2` writer - Periodic Interval 2 Event Output Enable"] +pub struct PEREO2_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PEREO3` reader - Periodic Interval 3 Event Output Enable"] +pub struct PEREO3_R(crate::FieldReader); +impl PEREO3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO3` writer - Periodic Interval 3 Event Output Enable"] +pub struct PEREO3_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PEREO4` reader - Periodic Interval 4 Event Output Enable"] +pub struct PEREO4_R(crate::FieldReader); +impl PEREO4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO4` writer - Periodic Interval 4 Event Output Enable"] +pub struct PEREO4_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PEREO5` reader - Periodic Interval 5 Event Output Enable"] +pub struct PEREO5_R(crate::FieldReader); +impl PEREO5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO5` writer - Periodic Interval 5 Event Output Enable"] +pub struct PEREO5_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PEREO6` reader - Periodic Interval 6 Event Output Enable"] +pub struct PEREO6_R(crate::FieldReader); +impl PEREO6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO6` writer - Periodic Interval 6 Event Output Enable"] +pub struct PEREO6_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PEREO7` reader - Periodic Interval 7 Event Output Enable"] +pub struct PEREO7_R(crate::FieldReader); +impl PEREO7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO7` writer - Periodic Interval 7 Event Output Enable"] +pub struct PEREO7_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CMPEO0` reader - Compare 0 Event Output Enable"] +pub struct CMPEO0_R(crate::FieldReader); +impl CMPEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMPEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMPEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMPEO0` writer - Compare 0 Event Output Enable"] +pub struct CMPEO0_W<'a> { + w: &'a mut W, +} +impl<'a> CMPEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `CMPEO1` reader - Compare 1 Event Output Enable"] +pub struct CMPEO1_R(crate::FieldReader); +impl CMPEO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMPEO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMPEO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMPEO1` writer - Compare 1 Event Output Enable"] +pub struct CMPEO1_W<'a> { + w: &'a mut W, +} +impl<'a> CMPEO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `OVFEO` reader - Overflow Event Output Enable"] +pub struct OVFEO_R(crate::FieldReader); +impl OVFEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVFEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVFEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVFEO` writer - Overflow Event Output Enable"] +pub struct OVFEO_W<'a> { + w: &'a mut W, +} +impl<'a> OVFEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Event Output Enable"] + #[inline(always)] + pub fn pereo0(&self) -> PEREO0_R { + PEREO0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Event Output Enable"] + #[inline(always)] + pub fn pereo1(&self) -> PEREO1_R { + PEREO1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Event Output Enable"] + #[inline(always)] + pub fn pereo2(&self) -> PEREO2_R { + PEREO2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Event Output Enable"] + #[inline(always)] + pub fn pereo3(&self) -> PEREO3_R { + PEREO3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Event Output Enable"] + #[inline(always)] + pub fn pereo4(&self) -> PEREO4_R { + PEREO4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Event Output Enable"] + #[inline(always)] + pub fn pereo5(&self) -> PEREO5_R { + PEREO5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Event Output Enable"] + #[inline(always)] + pub fn pereo6(&self) -> PEREO6_R { + PEREO6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Event Output Enable"] + #[inline(always)] + pub fn pereo7(&self) -> PEREO7_R { + PEREO7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Compare 0 Event Output Enable"] + #[inline(always)] + pub fn cmpeo0(&self) -> CMPEO0_R { + CMPEO0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Compare 1 Event Output Enable"] + #[inline(always)] + pub fn cmpeo1(&self) -> CMPEO1_R { + CMPEO1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&self) -> OVFEO_R { + OVFEO_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Event Output Enable"] + #[inline(always)] + pub fn pereo0(&mut self) -> PEREO0_W { + PEREO0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1 Event Output Enable"] + #[inline(always)] + pub fn pereo1(&mut self) -> PEREO1_W { + PEREO1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2 Event Output Enable"] + #[inline(always)] + pub fn pereo2(&mut self) -> PEREO2_W { + PEREO2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3 Event Output Enable"] + #[inline(always)] + pub fn pereo3(&mut self) -> PEREO3_W { + PEREO3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4 Event Output Enable"] + #[inline(always)] + pub fn pereo4(&mut self) -> PEREO4_W { + PEREO4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5 Event Output Enable"] + #[inline(always)] + pub fn pereo5(&mut self) -> PEREO5_W { + PEREO5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6 Event Output Enable"] + #[inline(always)] + pub fn pereo6(&mut self) -> PEREO6_W { + PEREO6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7 Event Output Enable"] + #[inline(always)] + pub fn pereo7(&mut self) -> PEREO7_W { + PEREO7_W { w: self } + } + #[doc = "Bit 8 - Compare 0 Event Output Enable"] + #[inline(always)] + pub fn cmpeo0(&mut self) -> CMPEO0_W { + CMPEO0_W { w: self } + } + #[doc = "Bit 9 - Compare 1 Event Output Enable"] + #[inline(always)] + pub fn cmpeo1(&mut self) -> CMPEO1_W { + CMPEO1_W { w: self } + } + #[doc = "Bit 15 - Overflow Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&mut self) -> OVFEO_W { + OVFEO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/rtc/mode1/freqcorr.rs b/pac/atsamc20g/src/rtc/mode1/freqcorr.rs new file mode 100644 index 000000000000..043ba6f88eb2 --- /dev/null +++ b/pac/atsamc20g/src/rtc/mode1/freqcorr.rs @@ -0,0 +1,150 @@ +#[doc = "Register `FREQCORR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FREQCORR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `VALUE` reader - Correction Value"] +pub struct VALUE_R(crate::FieldReader); +impl VALUE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + VALUE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VALUE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VALUE` writer - Correction Value"] +pub struct VALUE_W<'a> { + w: &'a mut W, +} +impl<'a> VALUE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x7f) | (value as u8 & 0x7f); + self.w + } +} +#[doc = "Field `SIGN` reader - Correction Sign"] +pub struct SIGN_R(crate::FieldReader); +impl SIGN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SIGN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SIGN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SIGN` writer - Correction Sign"] +pub struct SIGN_W<'a> { + w: &'a mut W, +} +impl<'a> SIGN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bits 0:6 - Correction Value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bit 7 - Correction Sign"] + #[inline(always)] + pub fn sign(&self) -> SIGN_R { + SIGN_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:6 - Correction Value"] + #[inline(always)] + pub fn value(&mut self) -> VALUE_W { + VALUE_W { w: self } + } + #[doc = "Bit 7 - Correction Sign"] + #[inline(always)] + pub fn sign(&mut self) -> SIGN_W { + SIGN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Frequency Correction\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [freqcorr](index.html) module"] +pub struct FREQCORR_SPEC; +impl crate::RegisterSpec for FREQCORR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [freqcorr::R](R) reader structure"] +impl crate::Readable for FREQCORR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [freqcorr::W](W) writer structure"] +impl crate::Writable for FREQCORR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets FREQCORR to value 0"] +impl crate::Resettable for FREQCORR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/rtc/mode1/intenclr.rs b/pac/atsamc20g/src/rtc/mode1/intenclr.rs new file mode 100644 index 000000000000..d3fc5b3df34b --- /dev/null +++ b/pac/atsamc20g/src/rtc/mode1/intenclr.rs @@ -0,0 +1,583 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER0` reader - Periodic Interval 0 Interrupt Enable"] +pub struct PER0_R(crate::FieldReader); +impl PER0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER0` writer - Periodic Interval 0 Interrupt Enable"] +pub struct PER0_W<'a> { + w: &'a mut W, +} +impl<'a> PER0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PER1` reader - Periodic Interval 1 Interrupt Enable"] +pub struct PER1_R(crate::FieldReader); +impl PER1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER1` writer - Periodic Interval 1 Interrupt Enable"] +pub struct PER1_W<'a> { + w: &'a mut W, +} +impl<'a> PER1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PER2` reader - Periodic Interval 2 Interrupt Enable"] +pub struct PER2_R(crate::FieldReader); +impl PER2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER2` writer - Periodic Interval 2 Interrupt Enable"] +pub struct PER2_W<'a> { + w: &'a mut W, +} +impl<'a> PER2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PER3` reader - Periodic Interval 3 Interrupt Enable"] +pub struct PER3_R(crate::FieldReader); +impl PER3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER3` writer - Periodic Interval 3 Interrupt Enable"] +pub struct PER3_W<'a> { + w: &'a mut W, +} +impl<'a> PER3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PER4` reader - Periodic Interval 4 Interrupt Enable"] +pub struct PER4_R(crate::FieldReader); +impl PER4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER4` writer - Periodic Interval 4 Interrupt Enable"] +pub struct PER4_W<'a> { + w: &'a mut W, +} +impl<'a> PER4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PER5` reader - Periodic Interval 5 Interrupt Enable"] +pub struct PER5_R(crate::FieldReader); +impl PER5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER5` writer - Periodic Interval 5 Interrupt Enable"] +pub struct PER5_W<'a> { + w: &'a mut W, +} +impl<'a> PER5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PER6` reader - Periodic Interval 6 Interrupt Enable"] +pub struct PER6_R(crate::FieldReader); +impl PER6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER6` writer - Periodic Interval 6 Interrupt Enable"] +pub struct PER6_W<'a> { + w: &'a mut W, +} +impl<'a> PER6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PER7` reader - Periodic Interval 7 Interrupt Enable"] +pub struct PER7_R(crate::FieldReader); +impl PER7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER7` writer - Periodic Interval 7 Interrupt Enable"] +pub struct PER7_W<'a> { + w: &'a mut W, +} +impl<'a> PER7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CMP0` reader - Compare 0 Interrupt Enable"] +pub struct CMP0_R(crate::FieldReader); +impl CMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP0` writer - Compare 0 Interrupt Enable"] +pub struct CMP0_W<'a> { + w: &'a mut W, +} +impl<'a> CMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `CMP1` reader - Compare 1 Interrupt Enable"] +pub struct CMP1_R(crate::FieldReader); +impl CMP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP1` writer - Compare 1 Interrupt Enable"] +pub struct CMP1_W<'a> { + w: &'a mut W, +} +impl<'a> CMP1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + pub fn per0(&self) -> PER0_R { + PER0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + pub fn per1(&self) -> PER1_R { + PER1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + pub fn per2(&self) -> PER2_R { + PER2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + pub fn per3(&self) -> PER3_R { + PER3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + pub fn per4(&self) -> PER4_R { + PER4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + pub fn per5(&self) -> PER5_R { + PER5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + pub fn per6(&self) -> PER6_R { + PER6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + pub fn per7(&self) -> PER7_R { + PER7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&self) -> CMP0_R { + CMP0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Compare 1 Interrupt Enable"] + #[inline(always)] + pub fn cmp1(&self) -> CMP1_R { + CMP1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + pub fn per0(&mut self) -> PER0_W { + PER0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + pub fn per1(&mut self) -> PER1_W { + PER1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + pub fn per2(&mut self) -> PER2_W { + PER2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + pub fn per3(&mut self) -> PER3_W { + PER3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + pub fn per4(&mut self) -> PER4_W { + PER4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + pub fn per5(&mut self) -> PER5_W { + PER5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + pub fn per6(&mut self) -> PER6_W { + PER6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + pub fn per7(&mut self) -> PER7_W { + PER7_W { w: self } + } + #[doc = "Bit 8 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&mut self) -> CMP0_W { + CMP0_W { w: self } + } + #[doc = "Bit 9 - Compare 1 Interrupt Enable"] + #[inline(always)] + pub fn cmp1(&mut self) -> CMP1_W { + CMP1_W { w: self } + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/rtc/mode1/intenset.rs b/pac/atsamc20g/src/rtc/mode1/intenset.rs new file mode 100644 index 000000000000..074cb377926a --- /dev/null +++ b/pac/atsamc20g/src/rtc/mode1/intenset.rs @@ -0,0 +1,583 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER0` reader - Periodic Interval 0 Interrupt Enable"] +pub struct PER0_R(crate::FieldReader); +impl PER0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER0` writer - Periodic Interval 0 Interrupt Enable"] +pub struct PER0_W<'a> { + w: &'a mut W, +} +impl<'a> PER0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PER1` reader - Periodic Interval 1 Interrupt Enable"] +pub struct PER1_R(crate::FieldReader); +impl PER1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER1` writer - Periodic Interval 1 Interrupt Enable"] +pub struct PER1_W<'a> { + w: &'a mut W, +} +impl<'a> PER1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PER2` reader - Periodic Interval 2 Interrupt Enable"] +pub struct PER2_R(crate::FieldReader); +impl PER2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER2` writer - Periodic Interval 2 Interrupt Enable"] +pub struct PER2_W<'a> { + w: &'a mut W, +} +impl<'a> PER2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PER3` reader - Periodic Interval 3 Interrupt Enable"] +pub struct PER3_R(crate::FieldReader); +impl PER3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER3` writer - Periodic Interval 3 Interrupt Enable"] +pub struct PER3_W<'a> { + w: &'a mut W, +} +impl<'a> PER3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PER4` reader - Periodic Interval 4 Interrupt Enable"] +pub struct PER4_R(crate::FieldReader); +impl PER4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER4` writer - Periodic Interval 4 Interrupt Enable"] +pub struct PER4_W<'a> { + w: &'a mut W, +} +impl<'a> PER4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PER5` reader - Periodic Interval 5 Interrupt Enable"] +pub struct PER5_R(crate::FieldReader); +impl PER5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER5` writer - Periodic Interval 5 Interrupt Enable"] +pub struct PER5_W<'a> { + w: &'a mut W, +} +impl<'a> PER5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PER6` reader - Periodic Interval 6 Interrupt Enable"] +pub struct PER6_R(crate::FieldReader); +impl PER6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER6` writer - Periodic Interval 6 Interrupt Enable"] +pub struct PER6_W<'a> { + w: &'a mut W, +} +impl<'a> PER6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PER7` reader - Periodic Interval 7 Interrupt Enable"] +pub struct PER7_R(crate::FieldReader); +impl PER7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER7` writer - Periodic Interval 7 Interrupt Enable"] +pub struct PER7_W<'a> { + w: &'a mut W, +} +impl<'a> PER7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CMP0` reader - Compare 0 Interrupt Enable"] +pub struct CMP0_R(crate::FieldReader); +impl CMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP0` writer - Compare 0 Interrupt Enable"] +pub struct CMP0_W<'a> { + w: &'a mut W, +} +impl<'a> CMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `CMP1` reader - Compare 1 Interrupt Enable"] +pub struct CMP1_R(crate::FieldReader); +impl CMP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP1` writer - Compare 1 Interrupt Enable"] +pub struct CMP1_W<'a> { + w: &'a mut W, +} +impl<'a> CMP1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + pub fn per0(&self) -> PER0_R { + PER0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + pub fn per1(&self) -> PER1_R { + PER1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + pub fn per2(&self) -> PER2_R { + PER2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + pub fn per3(&self) -> PER3_R { + PER3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + pub fn per4(&self) -> PER4_R { + PER4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + pub fn per5(&self) -> PER5_R { + PER5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + pub fn per6(&self) -> PER6_R { + PER6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + pub fn per7(&self) -> PER7_R { + PER7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&self) -> CMP0_R { + CMP0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Compare 1 Interrupt Enable"] + #[inline(always)] + pub fn cmp1(&self) -> CMP1_R { + CMP1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + pub fn per0(&mut self) -> PER0_W { + PER0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + pub fn per1(&mut self) -> PER1_W { + PER1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + pub fn per2(&mut self) -> PER2_W { + PER2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + pub fn per3(&mut self) -> PER3_W { + PER3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + pub fn per4(&mut self) -> PER4_W { + PER4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + pub fn per5(&mut self) -> PER5_W { + PER5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + pub fn per6(&mut self) -> PER6_W { + PER6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + pub fn per7(&mut self) -> PER7_W { + PER7_W { w: self } + } + #[doc = "Bit 8 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&mut self) -> CMP0_W { + CMP0_W { w: self } + } + #[doc = "Bit 9 - Compare 1 Interrupt Enable"] + #[inline(always)] + pub fn cmp1(&mut self) -> CMP1_W { + CMP1_W { w: self } + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/rtc/mode1/intflag.rs b/pac/atsamc20g/src/rtc/mode1/intflag.rs new file mode 100644 index 000000000000..25bce956f46b --- /dev/null +++ b/pac/atsamc20g/src/rtc/mode1/intflag.rs @@ -0,0 +1,583 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER0` reader - Periodic Interval 0"] +pub struct PER0_R(crate::FieldReader); +impl PER0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER0` writer - Periodic Interval 0"] +pub struct PER0_W<'a> { + w: &'a mut W, +} +impl<'a> PER0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PER1` reader - Periodic Interval 1"] +pub struct PER1_R(crate::FieldReader); +impl PER1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER1` writer - Periodic Interval 1"] +pub struct PER1_W<'a> { + w: &'a mut W, +} +impl<'a> PER1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PER2` reader - Periodic Interval 2"] +pub struct PER2_R(crate::FieldReader); +impl PER2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER2` writer - Periodic Interval 2"] +pub struct PER2_W<'a> { + w: &'a mut W, +} +impl<'a> PER2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PER3` reader - Periodic Interval 3"] +pub struct PER3_R(crate::FieldReader); +impl PER3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER3` writer - Periodic Interval 3"] +pub struct PER3_W<'a> { + w: &'a mut W, +} +impl<'a> PER3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PER4` reader - Periodic Interval 4"] +pub struct PER4_R(crate::FieldReader); +impl PER4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER4` writer - Periodic Interval 4"] +pub struct PER4_W<'a> { + w: &'a mut W, +} +impl<'a> PER4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PER5` reader - Periodic Interval 5"] +pub struct PER5_R(crate::FieldReader); +impl PER5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER5` writer - Periodic Interval 5"] +pub struct PER5_W<'a> { + w: &'a mut W, +} +impl<'a> PER5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PER6` reader - Periodic Interval 6"] +pub struct PER6_R(crate::FieldReader); +impl PER6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER6` writer - Periodic Interval 6"] +pub struct PER6_W<'a> { + w: &'a mut W, +} +impl<'a> PER6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PER7` reader - Periodic Interval 7"] +pub struct PER7_R(crate::FieldReader); +impl PER7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER7` writer - Periodic Interval 7"] +pub struct PER7_W<'a> { + w: &'a mut W, +} +impl<'a> PER7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CMP0` reader - Compare 0"] +pub struct CMP0_R(crate::FieldReader); +impl CMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP0` writer - Compare 0"] +pub struct CMP0_W<'a> { + w: &'a mut W, +} +impl<'a> CMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `CMP1` reader - Compare 1"] +pub struct CMP1_R(crate::FieldReader); +impl CMP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP1` writer - Compare 1"] +pub struct CMP1_W<'a> { + w: &'a mut W, +} +impl<'a> CMP1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0"] + #[inline(always)] + pub fn per0(&self) -> PER0_R { + PER0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1"] + #[inline(always)] + pub fn per1(&self) -> PER1_R { + PER1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2"] + #[inline(always)] + pub fn per2(&self) -> PER2_R { + PER2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3"] + #[inline(always)] + pub fn per3(&self) -> PER3_R { + PER3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4"] + #[inline(always)] + pub fn per4(&self) -> PER4_R { + PER4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5"] + #[inline(always)] + pub fn per5(&self) -> PER5_R { + PER5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6"] + #[inline(always)] + pub fn per6(&self) -> PER6_R { + PER6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7"] + #[inline(always)] + pub fn per7(&self) -> PER7_R { + PER7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Compare 0"] + #[inline(always)] + pub fn cmp0(&self) -> CMP0_R { + CMP0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Compare 1"] + #[inline(always)] + pub fn cmp1(&self) -> CMP1_R { + CMP1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0"] + #[inline(always)] + pub fn per0(&mut self) -> PER0_W { + PER0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1"] + #[inline(always)] + pub fn per1(&mut self) -> PER1_W { + PER1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2"] + #[inline(always)] + pub fn per2(&mut self) -> PER2_W { + PER2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3"] + #[inline(always)] + pub fn per3(&mut self) -> PER3_W { + PER3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4"] + #[inline(always)] + pub fn per4(&mut self) -> PER4_W { + PER4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5"] + #[inline(always)] + pub fn per5(&mut self) -> PER5_W { + PER5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6"] + #[inline(always)] + pub fn per6(&mut self) -> PER6_W { + PER6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7"] + #[inline(always)] + pub fn per7(&mut self) -> PER7_W { + PER7_W { w: self } + } + #[doc = "Bit 8 - Compare 0"] + #[inline(always)] + pub fn cmp0(&mut self) -> CMP0_W { + CMP0_W { w: self } + } + #[doc = "Bit 9 - Compare 1"] + #[inline(always)] + pub fn cmp1(&mut self) -> CMP1_W { + CMP1_W { w: self } + } + #[doc = "Bit 15 - Overflow"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/rtc/mode1/per.rs b/pac/atsamc20g/src/rtc/mode1/per.rs new file mode 100644 index 000000000000..c09b31fa30dd --- /dev/null +++ b/pac/atsamc20g/src/rtc/mode1/per.rs @@ -0,0 +1,103 @@ +#[doc = "Register `PER` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PER` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER` reader - Counter Period"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` writer - Counter Period"] +pub struct PER_W<'a> { + w: &'a mut W, +} +impl<'a> PER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Counter Period"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Counter Period"] + #[inline(always)] + pub fn per(&mut self) -> PER_W { + PER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Counter Period\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [per](index.html) module"] +pub struct PER_SPEC; +impl crate::RegisterSpec for PER_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [per::R](R) reader structure"] +impl crate::Readable for PER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [per::W](W) writer structure"] +impl crate::Writable for PER_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PER to value 0"] +impl crate::Resettable for PER_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/rtc/mode1/syncbusy.rs b/pac/atsamc20g/src/rtc/mode1/syncbusy.rs new file mode 100644 index 000000000000..b64c973bafff --- /dev/null +++ b/pac/atsamc20g/src/rtc/mode1/syncbusy.rs @@ -0,0 +1,193 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Bit Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - Enable Bit Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FREQCORR` reader - FREQCORR Register Busy"] +pub struct FREQCORR_R(crate::FieldReader); +impl FREQCORR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FREQCORR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FREQCORR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` reader - COUNT Register Busy"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` reader - PER Register Busy"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP0` reader - COMP 0 Register Busy"] +pub struct COMP0_R(crate::FieldReader); +impl COMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP1` reader - COMP 1 Register Busy"] +pub struct COMP1_R(crate::FieldReader); +impl COMP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNTSYNC` reader - Count Read Synchronization Enable Bit Busy"] +pub struct COUNTSYNC_R(crate::FieldReader); +impl COUNTSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNTSYNC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNTSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Bit Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable Bit Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - FREQCORR Register Busy"] + #[inline(always)] + pub fn freqcorr(&self) -> FREQCORR_R { + FREQCORR_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - COUNT Register Busy"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - PER Register Busy"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - COMP 0 Register Busy"] + #[inline(always)] + pub fn comp0(&self) -> COMP0_R { + COMP0_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - COMP 1 Register Busy"] + #[inline(always)] + pub fn comp1(&self) -> COMP1_R { + COMP1_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 15 - Count Read Synchronization Enable Bit Busy"] + #[inline(always)] + pub fn countsync(&self) -> COUNTSYNC_R { + COUNTSYNC_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +#[doc = "MODE1 Synchronization Busy Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/rtc/mode2.rs b/pac/atsamc20g/src/rtc/mode2.rs new file mode 100644 index 000000000000..b0bc13e81dbc --- /dev/null +++ b/pac/atsamc20g/src/rtc/mode2.rs @@ -0,0 +1,44 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "MODE2 Control A"] +pub mod ctrla; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "MODE2 Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "MODE2 Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "MODE2 Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "MODE2 Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "MODE2 Synchronization Busy Status"] +pub mod syncbusy; +#[doc = "FREQCORR register accessor: an alias for `Reg`"] +pub type FREQCORR = crate::Reg; +#[doc = "Frequency Correction"] +pub mod freqcorr; +#[doc = "CLOCK register accessor: an alias for `Reg`"] +pub type CLOCK = crate::Reg; +#[doc = "MODE2 Clock Value"] +pub mod clock; +#[doc = "ALARM register accessor: an alias for `Reg`"] +pub type ALARM = crate::Reg; +#[doc = "MODE2_ALARM Alarm n Value"] +pub mod alarm; +#[doc = "MASK register accessor: an alias for `Reg`"] +pub type MASK = crate::Reg; +#[doc = "MODE2_ALARM Alarm n Mask"] +pub mod mask; diff --git a/pac/atsamc20g/src/rtc/mode2/alarm.rs b/pac/atsamc20g/src/rtc/mode2/alarm.rs new file mode 100644 index 000000000000..1242477ea69f --- /dev/null +++ b/pac/atsamc20g/src/rtc/mode2/alarm.rs @@ -0,0 +1,337 @@ +#[doc = "Register `ALARM` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ALARM` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SECOND` reader - Second"] +pub struct SECOND_R(crate::FieldReader); +impl SECOND_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SECOND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SECOND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SECOND` writer - Second"] +pub struct SECOND_W<'a> { + w: &'a mut W, +} +impl<'a> SECOND_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +#[doc = "Field `MINUTE` reader - Minute"] +pub struct MINUTE_R(crate::FieldReader); +impl MINUTE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MINUTE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MINUTE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MINUTE` writer - Minute"] +pub struct MINUTE_W<'a> { + w: &'a mut W, +} +impl<'a> MINUTE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 6)) | ((value as u32 & 0x3f) << 6); + self.w + } +} +#[doc = "Hour\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum HOUR_A { + #[doc = "0: Morning hour"] + AM = 0, + #[doc = "16: Afternoon hour"] + PM = 16, +} +impl From for u8 { + #[inline(always)] + fn from(variant: HOUR_A) -> Self { + variant as _ + } +} +#[doc = "Field `HOUR` reader - Hour"] +pub struct HOUR_R(crate::FieldReader); +impl HOUR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + HOUR_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(HOUR_A::AM), + 16 => Some(HOUR_A::PM), + _ => None, + } + } + #[doc = "Checks if the value of the field is `AM`"] + #[inline(always)] + pub fn is_am(&self) -> bool { + **self == HOUR_A::AM + } + #[doc = "Checks if the value of the field is `PM`"] + #[inline(always)] + pub fn is_pm(&self) -> bool { + **self == HOUR_A::PM + } +} +impl core::ops::Deref for HOUR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HOUR` writer - Hour"] +pub struct HOUR_W<'a> { + w: &'a mut W, +} +impl<'a> HOUR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: HOUR_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Morning hour"] + #[inline(always)] + pub fn am(self) -> &'a mut W { + self.variant(HOUR_A::AM) + } + #[doc = "Afternoon hour"] + #[inline(always)] + pub fn pm(self) -> &'a mut W { + self.variant(HOUR_A::PM) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 12)) | ((value as u32 & 0x1f) << 12); + self.w + } +} +#[doc = "Field `DAY` reader - Day"] +pub struct DAY_R(crate::FieldReader); +impl DAY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DAY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DAY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DAY` writer - Day"] +pub struct DAY_W<'a> { + w: &'a mut W, +} +impl<'a> DAY_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 17)) | ((value as u32 & 0x1f) << 17); + self.w + } +} +#[doc = "Field `MONTH` reader - Month"] +pub struct MONTH_R(crate::FieldReader); +impl MONTH_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MONTH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MONTH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MONTH` writer - Month"] +pub struct MONTH_W<'a> { + w: &'a mut W, +} +impl<'a> MONTH_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 22)) | ((value as u32 & 0x0f) << 22); + self.w + } +} +#[doc = "Field `YEAR` reader - Year"] +pub struct YEAR_R(crate::FieldReader); +impl YEAR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + YEAR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for YEAR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `YEAR` writer - Year"] +pub struct YEAR_W<'a> { + w: &'a mut W, +} +impl<'a> YEAR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 26)) | ((value as u32 & 0x3f) << 26); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Second"] + #[inline(always)] + pub fn second(&self) -> SECOND_R { + SECOND_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:11 - Minute"] + #[inline(always)] + pub fn minute(&self) -> MINUTE_R { + MINUTE_R::new(((self.bits >> 6) & 0x3f) as u8) + } + #[doc = "Bits 12:16 - Hour"] + #[inline(always)] + pub fn hour(&self) -> HOUR_R { + HOUR_R::new(((self.bits >> 12) & 0x1f) as u8) + } + #[doc = "Bits 17:21 - Day"] + #[inline(always)] + pub fn day(&self) -> DAY_R { + DAY_R::new(((self.bits >> 17) & 0x1f) as u8) + } + #[doc = "Bits 22:25 - Month"] + #[inline(always)] + pub fn month(&self) -> MONTH_R { + MONTH_R::new(((self.bits >> 22) & 0x0f) as u8) + } + #[doc = "Bits 26:31 - Year"] + #[inline(always)] + pub fn year(&self) -> YEAR_R { + YEAR_R::new(((self.bits >> 26) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - Second"] + #[inline(always)] + pub fn second(&mut self) -> SECOND_W { + SECOND_W { w: self } + } + #[doc = "Bits 6:11 - Minute"] + #[inline(always)] + pub fn minute(&mut self) -> MINUTE_W { + MINUTE_W { w: self } + } + #[doc = "Bits 12:16 - Hour"] + #[inline(always)] + pub fn hour(&mut self) -> HOUR_W { + HOUR_W { w: self } + } + #[doc = "Bits 17:21 - Day"] + #[inline(always)] + pub fn day(&mut self) -> DAY_W { + DAY_W { w: self } + } + #[doc = "Bits 22:25 - Month"] + #[inline(always)] + pub fn month(&mut self) -> MONTH_W { + MONTH_W { w: self } + } + #[doc = "Bits 26:31 - Year"] + #[inline(always)] + pub fn year(&mut self) -> YEAR_W { + YEAR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2_ALARM Alarm n Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [alarm](index.html) module"] +pub struct ALARM_SPEC; +impl crate::RegisterSpec for ALARM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [alarm::R](R) reader structure"] +impl crate::Readable for ALARM_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [alarm::W](W) writer structure"] +impl crate::Writable for ALARM_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ALARM to value 0"] +impl crate::Resettable for ALARM_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/rtc/mode2/clock.rs b/pac/atsamc20g/src/rtc/mode2/clock.rs new file mode 100644 index 000000000000..3f364ff8e57b --- /dev/null +++ b/pac/atsamc20g/src/rtc/mode2/clock.rs @@ -0,0 +1,337 @@ +#[doc = "Register `CLOCK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CLOCK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SECOND` reader - Second"] +pub struct SECOND_R(crate::FieldReader); +impl SECOND_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SECOND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SECOND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SECOND` writer - Second"] +pub struct SECOND_W<'a> { + w: &'a mut W, +} +impl<'a> SECOND_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +#[doc = "Field `MINUTE` reader - Minute"] +pub struct MINUTE_R(crate::FieldReader); +impl MINUTE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MINUTE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MINUTE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MINUTE` writer - Minute"] +pub struct MINUTE_W<'a> { + w: &'a mut W, +} +impl<'a> MINUTE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 6)) | ((value as u32 & 0x3f) << 6); + self.w + } +} +#[doc = "Hour\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum HOUR_A { + #[doc = "0: AM when CLKREP in 12-hour"] + AM = 0, + #[doc = "16: PM when CLKREP in 12-hour"] + PM = 16, +} +impl From for u8 { + #[inline(always)] + fn from(variant: HOUR_A) -> Self { + variant as _ + } +} +#[doc = "Field `HOUR` reader - Hour"] +pub struct HOUR_R(crate::FieldReader); +impl HOUR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + HOUR_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(HOUR_A::AM), + 16 => Some(HOUR_A::PM), + _ => None, + } + } + #[doc = "Checks if the value of the field is `AM`"] + #[inline(always)] + pub fn is_am(&self) -> bool { + **self == HOUR_A::AM + } + #[doc = "Checks if the value of the field is `PM`"] + #[inline(always)] + pub fn is_pm(&self) -> bool { + **self == HOUR_A::PM + } +} +impl core::ops::Deref for HOUR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HOUR` writer - Hour"] +pub struct HOUR_W<'a> { + w: &'a mut W, +} +impl<'a> HOUR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: HOUR_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "AM when CLKREP in 12-hour"] + #[inline(always)] + pub fn am(self) -> &'a mut W { + self.variant(HOUR_A::AM) + } + #[doc = "PM when CLKREP in 12-hour"] + #[inline(always)] + pub fn pm(self) -> &'a mut W { + self.variant(HOUR_A::PM) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 12)) | ((value as u32 & 0x1f) << 12); + self.w + } +} +#[doc = "Field `DAY` reader - Day"] +pub struct DAY_R(crate::FieldReader); +impl DAY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DAY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DAY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DAY` writer - Day"] +pub struct DAY_W<'a> { + w: &'a mut W, +} +impl<'a> DAY_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 17)) | ((value as u32 & 0x1f) << 17); + self.w + } +} +#[doc = "Field `MONTH` reader - Month"] +pub struct MONTH_R(crate::FieldReader); +impl MONTH_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MONTH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MONTH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MONTH` writer - Month"] +pub struct MONTH_W<'a> { + w: &'a mut W, +} +impl<'a> MONTH_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 22)) | ((value as u32 & 0x0f) << 22); + self.w + } +} +#[doc = "Field `YEAR` reader - Year"] +pub struct YEAR_R(crate::FieldReader); +impl YEAR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + YEAR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for YEAR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `YEAR` writer - Year"] +pub struct YEAR_W<'a> { + w: &'a mut W, +} +impl<'a> YEAR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 26)) | ((value as u32 & 0x3f) << 26); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Second"] + #[inline(always)] + pub fn second(&self) -> SECOND_R { + SECOND_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:11 - Minute"] + #[inline(always)] + pub fn minute(&self) -> MINUTE_R { + MINUTE_R::new(((self.bits >> 6) & 0x3f) as u8) + } + #[doc = "Bits 12:16 - Hour"] + #[inline(always)] + pub fn hour(&self) -> HOUR_R { + HOUR_R::new(((self.bits >> 12) & 0x1f) as u8) + } + #[doc = "Bits 17:21 - Day"] + #[inline(always)] + pub fn day(&self) -> DAY_R { + DAY_R::new(((self.bits >> 17) & 0x1f) as u8) + } + #[doc = "Bits 22:25 - Month"] + #[inline(always)] + pub fn month(&self) -> MONTH_R { + MONTH_R::new(((self.bits >> 22) & 0x0f) as u8) + } + #[doc = "Bits 26:31 - Year"] + #[inline(always)] + pub fn year(&self) -> YEAR_R { + YEAR_R::new(((self.bits >> 26) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - Second"] + #[inline(always)] + pub fn second(&mut self) -> SECOND_W { + SECOND_W { w: self } + } + #[doc = "Bits 6:11 - Minute"] + #[inline(always)] + pub fn minute(&mut self) -> MINUTE_W { + MINUTE_W { w: self } + } + #[doc = "Bits 12:16 - Hour"] + #[inline(always)] + pub fn hour(&mut self) -> HOUR_W { + HOUR_W { w: self } + } + #[doc = "Bits 17:21 - Day"] + #[inline(always)] + pub fn day(&mut self) -> DAY_W { + DAY_W { w: self } + } + #[doc = "Bits 22:25 - Month"] + #[inline(always)] + pub fn month(&mut self) -> MONTH_W { + MONTH_W { w: self } + } + #[doc = "Bits 26:31 - Year"] + #[inline(always)] + pub fn year(&mut self) -> YEAR_W { + YEAR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2 Clock Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clock](index.html) module"] +pub struct CLOCK_SPEC; +impl crate::RegisterSpec for CLOCK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [clock::R](R) reader structure"] +impl crate::Readable for CLOCK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [clock::W](W) writer structure"] +impl crate::Writable for CLOCK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CLOCK to value 0"] +impl crate::Resettable for CLOCK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/rtc/mode2/ctrla.rs b/pac/atsamc20g/src/rtc/mode2/ctrla.rs new file mode 100644 index 000000000000..fc4bfda16bd8 --- /dev/null +++ b/pac/atsamc20g/src/rtc/mode2/ctrla.rs @@ -0,0 +1,616 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: Mode 0: 32-bit Counter"] + COUNT32 = 0, + #[doc = "1: Mode 1: 16-bit Counter"] + COUNT16 = 1, + #[doc = "2: Mode 2: Clock/Calendar"] + CLOCK = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::COUNT32), + 1 => Some(MODE_A::COUNT16), + 2 => Some(MODE_A::CLOCK), + _ => None, + } + } + #[doc = "Checks if the value of the field is `COUNT32`"] + #[inline(always)] + pub fn is_count32(&self) -> bool { + **self == MODE_A::COUNT32 + } + #[doc = "Checks if the value of the field is `COUNT16`"] + #[inline(always)] + pub fn is_count16(&self) -> bool { + **self == MODE_A::COUNT16 + } + #[doc = "Checks if the value of the field is `CLOCK`"] + #[inline(always)] + pub fn is_clock(&self) -> bool { + **self == MODE_A::CLOCK + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Mode 0: 32-bit Counter"] + #[inline(always)] + pub fn count32(self) -> &'a mut W { + self.variant(MODE_A::COUNT32) + } + #[doc = "Mode 1: 16-bit Counter"] + #[inline(always)] + pub fn count16(self) -> &'a mut W { + self.variant(MODE_A::COUNT16) + } + #[doc = "Mode 2: Clock/Calendar"] + #[inline(always)] + pub fn clock(self) -> &'a mut W { + self.variant(MODE_A::CLOCK) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u16 & 0x03) << 2); + self.w + } +} +#[doc = "Field `CLKREP` reader - Clock Representation"] +pub struct CLKREP_R(crate::FieldReader); +impl CLKREP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKREP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKREP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKREP` writer - Clock Representation"] +pub struct CLKREP_W<'a> { + w: &'a mut W, +} +impl<'a> CLKREP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `MATCHCLR` reader - Clear on Match"] +pub struct MATCHCLR_R(crate::FieldReader); +impl MATCHCLR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MATCHCLR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MATCHCLR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MATCHCLR` writer - Clear on Match"] +pub struct MATCHCLR_W<'a> { + w: &'a mut W, +} +impl<'a> MATCHCLR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: CLK_RTC_CNT = GCLK_RTC/1"] + OFF = 0, + #[doc = "1: CLK_RTC_CNT = GCLK_RTC/1"] + DIV1 = 1, + #[doc = "2: CLK_RTC_CNT = GCLK_RTC/2"] + DIV2 = 2, + #[doc = "3: CLK_RTC_CNT = GCLK_RTC/4"] + DIV4 = 3, + #[doc = "4: CLK_RTC_CNT = GCLK_RTC/8"] + DIV8 = 4, + #[doc = "5: CLK_RTC_CNT = GCLK_RTC/16"] + DIV16 = 5, + #[doc = "6: CLK_RTC_CNT = GCLK_RTC/32"] + DIV32 = 6, + #[doc = "7: CLK_RTC_CNT = GCLK_RTC/64"] + DIV64 = 7, + #[doc = "8: CLK_RTC_CNT = GCLK_RTC/128"] + DIV128 = 8, + #[doc = "9: CLK_RTC_CNT = GCLK_RTC/256"] + DIV256 = 9, + #[doc = "10: CLK_RTC_CNT = GCLK_RTC/512"] + DIV512 = 10, + #[doc = "11: CLK_RTC_CNT = GCLK_RTC/1024"] + DIV1024 = 11, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCALER_A::OFF), + 1 => Some(PRESCALER_A::DIV1), + 2 => Some(PRESCALER_A::DIV2), + 3 => Some(PRESCALER_A::DIV4), + 4 => Some(PRESCALER_A::DIV8), + 5 => Some(PRESCALER_A::DIV16), + 6 => Some(PRESCALER_A::DIV32), + 7 => Some(PRESCALER_A::DIV64), + 8 => Some(PRESCALER_A::DIV128), + 9 => Some(PRESCALER_A::DIV256), + 10 => Some(PRESCALER_A::DIV512), + 11 => Some(PRESCALER_A::DIV1024), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == PRESCALER_A::OFF + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == PRESCALER_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == PRESCALER_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == PRESCALER_A::DIV128 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV512`"] + #[inline(always)] + pub fn is_div512(&self) -> bool { + **self == PRESCALER_A::DIV512 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PRESCALER_A::DIV1024 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(PRESCALER_A::OFF) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV32) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV128) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/512"] + #[inline(always)] + pub fn div512(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV512) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 8)) | ((value as u16 & 0x0f) << 8); + self.w + } +} +#[doc = "Field `CLOCKSYNC` reader - Clock Read Synchronization Enable"] +pub struct CLOCKSYNC_R(crate::FieldReader); +impl CLOCKSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLOCKSYNC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLOCKSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLOCKSYNC` writer - Clock Read Synchronization Enable"] +pub struct CLOCKSYNC_W<'a> { + w: &'a mut W, +} +impl<'a> CLOCKSYNC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:3 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bit 6 - Clock Representation"] + #[inline(always)] + pub fn clkrep(&self) -> CLKREP_R { + CLKREP_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Clear on Match"] + #[inline(always)] + pub fn matchclr(&self) -> MATCHCLR_R { + MATCHCLR_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:11 - Prescaler"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 15 - Clock Read Synchronization Enable"] + #[inline(always)] + pub fn clocksync(&self) -> CLOCKSYNC_R { + CLOCKSYNC_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:3 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 6 - Clock Representation"] + #[inline(always)] + pub fn clkrep(&mut self) -> CLKREP_W { + CLKREP_W { w: self } + } + #[doc = "Bit 7 - Clear on Match"] + #[inline(always)] + pub fn matchclr(&mut self) -> MATCHCLR_W { + MATCHCLR_W { w: self } + } + #[doc = "Bits 8:11 - Prescaler"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Bit 15 - Clock Read Synchronization Enable"] + #[inline(always)] + pub fn clocksync(&mut self) -> CLOCKSYNC_W { + CLOCKSYNC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2 Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/rtc/mode2/dbgctrl.rs b/pac/atsamc20g/src/rtc/mode2/dbgctrl.rs new file mode 100644 index 000000000000..0383e70d0429 --- /dev/null +++ b/pac/atsamc20g/src/rtc/mode2/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Run During Debug"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Run During Debug"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/rtc/mode2/evctrl.rs b/pac/atsamc20g/src/rtc/mode2/evctrl.rs new file mode 100644 index 000000000000..17bc3da4a79e --- /dev/null +++ b/pac/atsamc20g/src/rtc/mode2/evctrl.rs @@ -0,0 +1,536 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PEREO0` reader - Periodic Interval 0 Event Output Enable"] +pub struct PEREO0_R(crate::FieldReader); +impl PEREO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO0` writer - Periodic Interval 0 Event Output Enable"] +pub struct PEREO0_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `PEREO1` reader - Periodic Interval 1 Event Output Enable"] +pub struct PEREO1_R(crate::FieldReader); +impl PEREO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO1` writer - Periodic Interval 1 Event Output Enable"] +pub struct PEREO1_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PEREO2` reader - Periodic Interval 2 Event Output Enable"] +pub struct PEREO2_R(crate::FieldReader); +impl PEREO2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO2` writer - Periodic Interval 2 Event Output Enable"] +pub struct PEREO2_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PEREO3` reader - Periodic Interval 3 Event Output Enable"] +pub struct PEREO3_R(crate::FieldReader); +impl PEREO3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO3` writer - Periodic Interval 3 Event Output Enable"] +pub struct PEREO3_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PEREO4` reader - Periodic Interval 4 Event Output Enable"] +pub struct PEREO4_R(crate::FieldReader); +impl PEREO4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO4` writer - Periodic Interval 4 Event Output Enable"] +pub struct PEREO4_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PEREO5` reader - Periodic Interval 5 Event Output Enable"] +pub struct PEREO5_R(crate::FieldReader); +impl PEREO5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO5` writer - Periodic Interval 5 Event Output Enable"] +pub struct PEREO5_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PEREO6` reader - Periodic Interval 6 Event Output Enable"] +pub struct PEREO6_R(crate::FieldReader); +impl PEREO6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO6` writer - Periodic Interval 6 Event Output Enable"] +pub struct PEREO6_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PEREO7` reader - Periodic Interval 7 Event Output Enable"] +pub struct PEREO7_R(crate::FieldReader); +impl PEREO7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO7` writer - Periodic Interval 7 Event Output Enable"] +pub struct PEREO7_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `ALARMEO0` reader - Alarm 0 Event Output Enable"] +pub struct ALARMEO0_R(crate::FieldReader); +impl ALARMEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALARMEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALARMEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALARMEO0` writer - Alarm 0 Event Output Enable"] +pub struct ALARMEO0_W<'a> { + w: &'a mut W, +} +impl<'a> ALARMEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `OVFEO` reader - Overflow Event Output Enable"] +pub struct OVFEO_R(crate::FieldReader); +impl OVFEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVFEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVFEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVFEO` writer - Overflow Event Output Enable"] +pub struct OVFEO_W<'a> { + w: &'a mut W, +} +impl<'a> OVFEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Event Output Enable"] + #[inline(always)] + pub fn pereo0(&self) -> PEREO0_R { + PEREO0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Event Output Enable"] + #[inline(always)] + pub fn pereo1(&self) -> PEREO1_R { + PEREO1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Event Output Enable"] + #[inline(always)] + pub fn pereo2(&self) -> PEREO2_R { + PEREO2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Event Output Enable"] + #[inline(always)] + pub fn pereo3(&self) -> PEREO3_R { + PEREO3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Event Output Enable"] + #[inline(always)] + pub fn pereo4(&self) -> PEREO4_R { + PEREO4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Event Output Enable"] + #[inline(always)] + pub fn pereo5(&self) -> PEREO5_R { + PEREO5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Event Output Enable"] + #[inline(always)] + pub fn pereo6(&self) -> PEREO6_R { + PEREO6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Event Output Enable"] + #[inline(always)] + pub fn pereo7(&self) -> PEREO7_R { + PEREO7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Alarm 0 Event Output Enable"] + #[inline(always)] + pub fn alarmeo0(&self) -> ALARMEO0_R { + ALARMEO0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&self) -> OVFEO_R { + OVFEO_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Event Output Enable"] + #[inline(always)] + pub fn pereo0(&mut self) -> PEREO0_W { + PEREO0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1 Event Output Enable"] + #[inline(always)] + pub fn pereo1(&mut self) -> PEREO1_W { + PEREO1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2 Event Output Enable"] + #[inline(always)] + pub fn pereo2(&mut self) -> PEREO2_W { + PEREO2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3 Event Output Enable"] + #[inline(always)] + pub fn pereo3(&mut self) -> PEREO3_W { + PEREO3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4 Event Output Enable"] + #[inline(always)] + pub fn pereo4(&mut self) -> PEREO4_W { + PEREO4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5 Event Output Enable"] + #[inline(always)] + pub fn pereo5(&mut self) -> PEREO5_W { + PEREO5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6 Event Output Enable"] + #[inline(always)] + pub fn pereo6(&mut self) -> PEREO6_W { + PEREO6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7 Event Output Enable"] + #[inline(always)] + pub fn pereo7(&mut self) -> PEREO7_W { + PEREO7_W { w: self } + } + #[doc = "Bit 8 - Alarm 0 Event Output Enable"] + #[inline(always)] + pub fn alarmeo0(&mut self) -> ALARMEO0_W { + ALARMEO0_W { w: self } + } + #[doc = "Bit 15 - Overflow Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&mut self) -> OVFEO_W { + OVFEO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2 Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/rtc/mode2/freqcorr.rs b/pac/atsamc20g/src/rtc/mode2/freqcorr.rs new file mode 100644 index 000000000000..043ba6f88eb2 --- /dev/null +++ b/pac/atsamc20g/src/rtc/mode2/freqcorr.rs @@ -0,0 +1,150 @@ +#[doc = "Register `FREQCORR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FREQCORR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `VALUE` reader - Correction Value"] +pub struct VALUE_R(crate::FieldReader); +impl VALUE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + VALUE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VALUE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VALUE` writer - Correction Value"] +pub struct VALUE_W<'a> { + w: &'a mut W, +} +impl<'a> VALUE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x7f) | (value as u8 & 0x7f); + self.w + } +} +#[doc = "Field `SIGN` reader - Correction Sign"] +pub struct SIGN_R(crate::FieldReader); +impl SIGN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SIGN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SIGN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SIGN` writer - Correction Sign"] +pub struct SIGN_W<'a> { + w: &'a mut W, +} +impl<'a> SIGN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bits 0:6 - Correction Value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bit 7 - Correction Sign"] + #[inline(always)] + pub fn sign(&self) -> SIGN_R { + SIGN_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:6 - Correction Value"] + #[inline(always)] + pub fn value(&mut self) -> VALUE_W { + VALUE_W { w: self } + } + #[doc = "Bit 7 - Correction Sign"] + #[inline(always)] + pub fn sign(&mut self) -> SIGN_W { + SIGN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Frequency Correction\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [freqcorr](index.html) module"] +pub struct FREQCORR_SPEC; +impl crate::RegisterSpec for FREQCORR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [freqcorr::R](R) reader structure"] +impl crate::Readable for FREQCORR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [freqcorr::W](W) writer structure"] +impl crate::Writable for FREQCORR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets FREQCORR to value 0"] +impl crate::Resettable for FREQCORR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/rtc/mode2/intenclr.rs b/pac/atsamc20g/src/rtc/mode2/intenclr.rs new file mode 100644 index 000000000000..84aa17f78a0e --- /dev/null +++ b/pac/atsamc20g/src/rtc/mode2/intenclr.rs @@ -0,0 +1,536 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER0` reader - Periodic Interval 0 Interrupt Enable"] +pub struct PER0_R(crate::FieldReader); +impl PER0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER0` writer - Periodic Interval 0 Interrupt Enable"] +pub struct PER0_W<'a> { + w: &'a mut W, +} +impl<'a> PER0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PER1` reader - Periodic Interval 1 Interrupt Enable"] +pub struct PER1_R(crate::FieldReader); +impl PER1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER1` writer - Periodic Interval 1 Interrupt Enable"] +pub struct PER1_W<'a> { + w: &'a mut W, +} +impl<'a> PER1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PER2` reader - Periodic Interval 2 Interrupt Enable"] +pub struct PER2_R(crate::FieldReader); +impl PER2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER2` writer - Periodic Interval 2 Interrupt Enable"] +pub struct PER2_W<'a> { + w: &'a mut W, +} +impl<'a> PER2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PER3` reader - Periodic Interval 3 Interrupt Enable"] +pub struct PER3_R(crate::FieldReader); +impl PER3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER3` writer - Periodic Interval 3 Interrupt Enable"] +pub struct PER3_W<'a> { + w: &'a mut W, +} +impl<'a> PER3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PER4` reader - Periodic Interval 4 Interrupt Enable"] +pub struct PER4_R(crate::FieldReader); +impl PER4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER4` writer - Periodic Interval 4 Interrupt Enable"] +pub struct PER4_W<'a> { + w: &'a mut W, +} +impl<'a> PER4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PER5` reader - Periodic Interval 5 Interrupt Enable"] +pub struct PER5_R(crate::FieldReader); +impl PER5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER5` writer - Periodic Interval 5 Interrupt Enable"] +pub struct PER5_W<'a> { + w: &'a mut W, +} +impl<'a> PER5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PER6` reader - Periodic Interval 6 Interrupt Enable"] +pub struct PER6_R(crate::FieldReader); +impl PER6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER6` writer - Periodic Interval 6 Interrupt Enable"] +pub struct PER6_W<'a> { + w: &'a mut W, +} +impl<'a> PER6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PER7` reader - Periodic Interval 7 Interrupt Enable"] +pub struct PER7_R(crate::FieldReader); +impl PER7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER7` writer - Periodic Interval 7 Interrupt Enable"] +pub struct PER7_W<'a> { + w: &'a mut W, +} +impl<'a> PER7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `ALARM0` reader - Alarm 0 Interrupt Enable"] +pub struct ALARM0_R(crate::FieldReader); +impl ALARM0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALARM0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALARM0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALARM0` writer - Alarm 0 Interrupt Enable"] +pub struct ALARM0_W<'a> { + w: &'a mut W, +} +impl<'a> ALARM0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + pub fn per0(&self) -> PER0_R { + PER0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + pub fn per1(&self) -> PER1_R { + PER1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + pub fn per2(&self) -> PER2_R { + PER2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + pub fn per3(&self) -> PER3_R { + PER3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + pub fn per4(&self) -> PER4_R { + PER4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + pub fn per5(&self) -> PER5_R { + PER5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + pub fn per6(&self) -> PER6_R { + PER6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + pub fn per7(&self) -> PER7_R { + PER7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Alarm 0 Interrupt Enable"] + #[inline(always)] + pub fn alarm0(&self) -> ALARM0_R { + ALARM0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + pub fn per0(&mut self) -> PER0_W { + PER0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + pub fn per1(&mut self) -> PER1_W { + PER1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + pub fn per2(&mut self) -> PER2_W { + PER2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + pub fn per3(&mut self) -> PER3_W { + PER3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + pub fn per4(&mut self) -> PER4_W { + PER4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + pub fn per5(&mut self) -> PER5_W { + PER5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + pub fn per6(&mut self) -> PER6_W { + PER6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + pub fn per7(&mut self) -> PER7_W { + PER7_W { w: self } + } + #[doc = "Bit 8 - Alarm 0 Interrupt Enable"] + #[inline(always)] + pub fn alarm0(&mut self) -> ALARM0_W { + ALARM0_W { w: self } + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2 Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/rtc/mode2/intenset.rs b/pac/atsamc20g/src/rtc/mode2/intenset.rs new file mode 100644 index 000000000000..a41687fa1ee5 --- /dev/null +++ b/pac/atsamc20g/src/rtc/mode2/intenset.rs @@ -0,0 +1,536 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER0` reader - Periodic Interval 0 Enable"] +pub struct PER0_R(crate::FieldReader); +impl PER0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER0` writer - Periodic Interval 0 Enable"] +pub struct PER0_W<'a> { + w: &'a mut W, +} +impl<'a> PER0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PER1` reader - Periodic Interval 1 Enable"] +pub struct PER1_R(crate::FieldReader); +impl PER1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER1` writer - Periodic Interval 1 Enable"] +pub struct PER1_W<'a> { + w: &'a mut W, +} +impl<'a> PER1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PER2` reader - Periodic Interval 2 Enable"] +pub struct PER2_R(crate::FieldReader); +impl PER2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER2` writer - Periodic Interval 2 Enable"] +pub struct PER2_W<'a> { + w: &'a mut W, +} +impl<'a> PER2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PER3` reader - Periodic Interval 3 Enable"] +pub struct PER3_R(crate::FieldReader); +impl PER3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER3` writer - Periodic Interval 3 Enable"] +pub struct PER3_W<'a> { + w: &'a mut W, +} +impl<'a> PER3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PER4` reader - Periodic Interval 4 Enable"] +pub struct PER4_R(crate::FieldReader); +impl PER4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER4` writer - Periodic Interval 4 Enable"] +pub struct PER4_W<'a> { + w: &'a mut W, +} +impl<'a> PER4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PER5` reader - Periodic Interval 5 Enable"] +pub struct PER5_R(crate::FieldReader); +impl PER5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER5` writer - Periodic Interval 5 Enable"] +pub struct PER5_W<'a> { + w: &'a mut W, +} +impl<'a> PER5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PER6` reader - Periodic Interval 6 Enable"] +pub struct PER6_R(crate::FieldReader); +impl PER6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER6` writer - Periodic Interval 6 Enable"] +pub struct PER6_W<'a> { + w: &'a mut W, +} +impl<'a> PER6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PER7` reader - Periodic Interval 7 Enable"] +pub struct PER7_R(crate::FieldReader); +impl PER7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER7` writer - Periodic Interval 7 Enable"] +pub struct PER7_W<'a> { + w: &'a mut W, +} +impl<'a> PER7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `ALARM0` reader - Alarm 0 Interrupt Enable"] +pub struct ALARM0_R(crate::FieldReader); +impl ALARM0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALARM0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALARM0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALARM0` writer - Alarm 0 Interrupt Enable"] +pub struct ALARM0_W<'a> { + w: &'a mut W, +} +impl<'a> ALARM0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Enable"] + #[inline(always)] + pub fn per0(&self) -> PER0_R { + PER0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Enable"] + #[inline(always)] + pub fn per1(&self) -> PER1_R { + PER1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Enable"] + #[inline(always)] + pub fn per2(&self) -> PER2_R { + PER2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Enable"] + #[inline(always)] + pub fn per3(&self) -> PER3_R { + PER3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Enable"] + #[inline(always)] + pub fn per4(&self) -> PER4_R { + PER4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Enable"] + #[inline(always)] + pub fn per5(&self) -> PER5_R { + PER5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Enable"] + #[inline(always)] + pub fn per6(&self) -> PER6_R { + PER6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Enable"] + #[inline(always)] + pub fn per7(&self) -> PER7_R { + PER7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Alarm 0 Interrupt Enable"] + #[inline(always)] + pub fn alarm0(&self) -> ALARM0_R { + ALARM0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Enable"] + #[inline(always)] + pub fn per0(&mut self) -> PER0_W { + PER0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1 Enable"] + #[inline(always)] + pub fn per1(&mut self) -> PER1_W { + PER1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2 Enable"] + #[inline(always)] + pub fn per2(&mut self) -> PER2_W { + PER2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3 Enable"] + #[inline(always)] + pub fn per3(&mut self) -> PER3_W { + PER3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4 Enable"] + #[inline(always)] + pub fn per4(&mut self) -> PER4_W { + PER4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5 Enable"] + #[inline(always)] + pub fn per5(&mut self) -> PER5_W { + PER5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6 Enable"] + #[inline(always)] + pub fn per6(&mut self) -> PER6_W { + PER6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7 Enable"] + #[inline(always)] + pub fn per7(&mut self) -> PER7_W { + PER7_W { w: self } + } + #[doc = "Bit 8 - Alarm 0 Interrupt Enable"] + #[inline(always)] + pub fn alarm0(&mut self) -> ALARM0_W { + ALARM0_W { w: self } + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2 Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/rtc/mode2/intflag.rs b/pac/atsamc20g/src/rtc/mode2/intflag.rs new file mode 100644 index 000000000000..8de0f3efd1d0 --- /dev/null +++ b/pac/atsamc20g/src/rtc/mode2/intflag.rs @@ -0,0 +1,536 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER0` reader - Periodic Interval 0"] +pub struct PER0_R(crate::FieldReader); +impl PER0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER0` writer - Periodic Interval 0"] +pub struct PER0_W<'a> { + w: &'a mut W, +} +impl<'a> PER0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PER1` reader - Periodic Interval 1"] +pub struct PER1_R(crate::FieldReader); +impl PER1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER1` writer - Periodic Interval 1"] +pub struct PER1_W<'a> { + w: &'a mut W, +} +impl<'a> PER1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PER2` reader - Periodic Interval 2"] +pub struct PER2_R(crate::FieldReader); +impl PER2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER2` writer - Periodic Interval 2"] +pub struct PER2_W<'a> { + w: &'a mut W, +} +impl<'a> PER2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PER3` reader - Periodic Interval 3"] +pub struct PER3_R(crate::FieldReader); +impl PER3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER3` writer - Periodic Interval 3"] +pub struct PER3_W<'a> { + w: &'a mut W, +} +impl<'a> PER3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PER4` reader - Periodic Interval 4"] +pub struct PER4_R(crate::FieldReader); +impl PER4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER4` writer - Periodic Interval 4"] +pub struct PER4_W<'a> { + w: &'a mut W, +} +impl<'a> PER4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PER5` reader - Periodic Interval 5"] +pub struct PER5_R(crate::FieldReader); +impl PER5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER5` writer - Periodic Interval 5"] +pub struct PER5_W<'a> { + w: &'a mut W, +} +impl<'a> PER5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PER6` reader - Periodic Interval 6"] +pub struct PER6_R(crate::FieldReader); +impl PER6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER6` writer - Periodic Interval 6"] +pub struct PER6_W<'a> { + w: &'a mut W, +} +impl<'a> PER6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PER7` reader - Periodic Interval 7"] +pub struct PER7_R(crate::FieldReader); +impl PER7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER7` writer - Periodic Interval 7"] +pub struct PER7_W<'a> { + w: &'a mut W, +} +impl<'a> PER7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `ALARM0` reader - Alarm 0"] +pub struct ALARM0_R(crate::FieldReader); +impl ALARM0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALARM0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALARM0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALARM0` writer - Alarm 0"] +pub struct ALARM0_W<'a> { + w: &'a mut W, +} +impl<'a> ALARM0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0"] + #[inline(always)] + pub fn per0(&self) -> PER0_R { + PER0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1"] + #[inline(always)] + pub fn per1(&self) -> PER1_R { + PER1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2"] + #[inline(always)] + pub fn per2(&self) -> PER2_R { + PER2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3"] + #[inline(always)] + pub fn per3(&self) -> PER3_R { + PER3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4"] + #[inline(always)] + pub fn per4(&self) -> PER4_R { + PER4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5"] + #[inline(always)] + pub fn per5(&self) -> PER5_R { + PER5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6"] + #[inline(always)] + pub fn per6(&self) -> PER6_R { + PER6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7"] + #[inline(always)] + pub fn per7(&self) -> PER7_R { + PER7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Alarm 0"] + #[inline(always)] + pub fn alarm0(&self) -> ALARM0_R { + ALARM0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0"] + #[inline(always)] + pub fn per0(&mut self) -> PER0_W { + PER0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1"] + #[inline(always)] + pub fn per1(&mut self) -> PER1_W { + PER1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2"] + #[inline(always)] + pub fn per2(&mut self) -> PER2_W { + PER2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3"] + #[inline(always)] + pub fn per3(&mut self) -> PER3_W { + PER3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4"] + #[inline(always)] + pub fn per4(&mut self) -> PER4_W { + PER4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5"] + #[inline(always)] + pub fn per5(&mut self) -> PER5_W { + PER5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6"] + #[inline(always)] + pub fn per6(&mut self) -> PER6_W { + PER6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7"] + #[inline(always)] + pub fn per7(&mut self) -> PER7_W { + PER7_W { w: self } + } + #[doc = "Bit 8 - Alarm 0"] + #[inline(always)] + pub fn alarm0(&mut self) -> ALARM0_W { + ALARM0_W { w: self } + } + #[doc = "Bit 15 - Overflow"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2 Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/rtc/mode2/mask.rs b/pac/atsamc20g/src/rtc/mode2/mask.rs new file mode 100644 index 000000000000..53e0bb491a62 --- /dev/null +++ b/pac/atsamc20g/src/rtc/mode2/mask.rs @@ -0,0 +1,217 @@ +#[doc = "Register `MASK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MASK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Alarm Mask Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SEL_A { + #[doc = "0: Alarm Disabled"] + OFF = 0, + #[doc = "1: Match seconds only"] + SS = 1, + #[doc = "2: Match seconds and minutes only"] + MMSS = 2, + #[doc = "3: Match seconds, minutes, and hours only"] + HHMMSS = 3, + #[doc = "4: Match seconds, minutes, hours, and days only"] + DDHHMMSS = 4, + #[doc = "5: Match seconds, minutes, hours, days, and months only"] + MMDDHHMMSS = 5, + #[doc = "6: Match seconds, minutes, hours, days, months, and years"] + YYMMDDHHMMSS = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `SEL` reader - Alarm Mask Selection"] +pub struct SEL_R(crate::FieldReader); +impl SEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEL_A::OFF), + 1 => Some(SEL_A::SS), + 2 => Some(SEL_A::MMSS), + 3 => Some(SEL_A::HHMMSS), + 4 => Some(SEL_A::DDHHMMSS), + 5 => Some(SEL_A::MMDDHHMMSS), + 6 => Some(SEL_A::YYMMDDHHMMSS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == SEL_A::OFF + } + #[doc = "Checks if the value of the field is `SS`"] + #[inline(always)] + pub fn is_ss(&self) -> bool { + **self == SEL_A::SS + } + #[doc = "Checks if the value of the field is `MMSS`"] + #[inline(always)] + pub fn is_mmss(&self) -> bool { + **self == SEL_A::MMSS + } + #[doc = "Checks if the value of the field is `HHMMSS`"] + #[inline(always)] + pub fn is_hhmmss(&self) -> bool { + **self == SEL_A::HHMMSS + } + #[doc = "Checks if the value of the field is `DDHHMMSS`"] + #[inline(always)] + pub fn is_ddhhmmss(&self) -> bool { + **self == SEL_A::DDHHMMSS + } + #[doc = "Checks if the value of the field is `MMDDHHMMSS`"] + #[inline(always)] + pub fn is_mmddhhmmss(&self) -> bool { + **self == SEL_A::MMDDHHMMSS + } + #[doc = "Checks if the value of the field is `YYMMDDHHMMSS`"] + #[inline(always)] + pub fn is_yymmddhhmmss(&self) -> bool { + **self == SEL_A::YYMMDDHHMMSS + } +} +impl core::ops::Deref for SEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEL` writer - Alarm Mask Selection"] +pub struct SEL_W<'a> { + w: &'a mut W, +} +impl<'a> SEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SEL_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Alarm Disabled"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(SEL_A::OFF) + } + #[doc = "Match seconds only"] + #[inline(always)] + pub fn ss(self) -> &'a mut W { + self.variant(SEL_A::SS) + } + #[doc = "Match seconds and minutes only"] + #[inline(always)] + pub fn mmss(self) -> &'a mut W { + self.variant(SEL_A::MMSS) + } + #[doc = "Match seconds, minutes, and hours only"] + #[inline(always)] + pub fn hhmmss(self) -> &'a mut W { + self.variant(SEL_A::HHMMSS) + } + #[doc = "Match seconds, minutes, hours, and days only"] + #[inline(always)] + pub fn ddhhmmss(self) -> &'a mut W { + self.variant(SEL_A::DDHHMMSS) + } + #[doc = "Match seconds, minutes, hours, days, and months only"] + #[inline(always)] + pub fn mmddhhmmss(self) -> &'a mut W { + self.variant(SEL_A::MMDDHHMMSS) + } + #[doc = "Match seconds, minutes, hours, days, months, and years"] + #[inline(always)] + pub fn yymmddhhmmss(self) -> &'a mut W { + self.variant(SEL_A::YYMMDDHHMMSS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Alarm Mask Selection"] + #[inline(always)] + pub fn sel(&self) -> SEL_R { + SEL_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Alarm Mask Selection"] + #[inline(always)] + pub fn sel(&mut self) -> SEL_W { + SEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2_ALARM Alarm n Mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mask](index.html) module"] +pub struct MASK_SPEC; +impl crate::RegisterSpec for MASK_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [mask::R](R) reader structure"] +impl crate::Readable for MASK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [mask::W](W) writer structure"] +impl crate::Writable for MASK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets MASK to value 0"] +impl crate::Resettable for MASK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/rtc/mode2/syncbusy.rs b/pac/atsamc20g/src/rtc/mode2/syncbusy.rs new file mode 100644 index 000000000000..b517ee5ae8b2 --- /dev/null +++ b/pac/atsamc20g/src/rtc/mode2/syncbusy.rs @@ -0,0 +1,173 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Bit Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - Enable Bit Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FREQCORR` reader - FREQCORR Register Busy"] +pub struct FREQCORR_R(crate::FieldReader); +impl FREQCORR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FREQCORR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FREQCORR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLOCK` reader - CLOCK Register Busy"] +pub struct CLOCK_R(crate::FieldReader); +impl CLOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALARM0` reader - ALARM 0 Register Busy"] +pub struct ALARM0_R(crate::FieldReader); +impl ALARM0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALARM0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALARM0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MASK0` reader - MASK 0 Register Busy"] +pub struct MASK0_R(crate::FieldReader); +impl MASK0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MASK0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MASK0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLOCKSYNC` reader - Clock Read Synchronization Enable Bit Busy"] +pub struct CLOCKSYNC_R(crate::FieldReader); +impl CLOCKSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLOCKSYNC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLOCKSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Bit Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable Bit Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - FREQCORR Register Busy"] + #[inline(always)] + pub fn freqcorr(&self) -> FREQCORR_R { + FREQCORR_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - CLOCK Register Busy"] + #[inline(always)] + pub fn clock(&self) -> CLOCK_R { + CLOCK_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 5 - ALARM 0 Register Busy"] + #[inline(always)] + pub fn alarm0(&self) -> ALARM0_R { + ALARM0_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 11 - MASK 0 Register Busy"] + #[inline(always)] + pub fn mask0(&self) -> MASK0_R { + MASK0_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 15 - Clock Read Synchronization Enable Bit Busy"] + #[inline(always)] + pub fn clocksync(&self) -> CLOCKSYNC_R { + CLOCKSYNC_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +#[doc = "MODE2 Synchronization Busy Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/sercom0.rs b/pac/atsamc20g/src/sercom0.rs new file mode 100644 index 000000000000..da7b62f750c6 --- /dev/null +++ b/pac/atsamc20g/src/sercom0.rs @@ -0,0 +1,327 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved_0_i2cm: [u8; 0x31], +} +impl RegisterBlock { + #[doc = "0x00..0x31 - USART INTERNAL CLOCK Mode"] + #[inline(always)] + pub fn usart_int(&self) -> &USART_INT { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const USART_INT) } + } + #[doc = "0x00..0x31 - USART EXTERNAL CLOCK Mode"] + #[inline(always)] + pub fn usart_ext(&self) -> &USART_EXT { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const USART_EXT) } + } + #[doc = "0x00..0x31 - SPI Master Mode"] + #[inline(always)] + pub fn spim(&self) -> &SPIM { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const SPIM) } + } + #[doc = "0x00..0x31 - SPI Slave Mode"] + #[inline(always)] + pub fn spis(&self) -> &SPIS { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const SPIS) } + } + #[doc = "0x00..0x29 - I2C Slave Mode"] + #[inline(always)] + pub fn i2cs(&self) -> &I2CS { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const I2CS) } + } + #[doc = "0x00..0x31 - I2C Master Mode"] + #[inline(always)] + pub fn i2cm(&self) -> &I2CM { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const I2CM) } + } +} +#[doc = r"Register block"] +#[repr(C)] +pub struct I2CM { + #[doc = "0x00 - I2CM Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - I2CM Control B"] + pub ctrlb: crate::Reg, + _reserved2: [u8; 0x04], + #[doc = "0x0c - I2CM Baud Rate"] + pub baud: crate::Reg, + _reserved3: [u8; 0x04], + #[doc = "0x14 - I2CM Interrupt Enable Clear"] + pub intenclr: crate::Reg, + _reserved4: [u8; 0x01], + #[doc = "0x16 - I2CM Interrupt Enable Set"] + pub intenset: crate::Reg, + _reserved5: [u8; 0x01], + #[doc = "0x18 - I2CM Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x1a - I2CM Status"] + pub status: crate::Reg, + #[doc = "0x1c - I2CM Synchronization Busy"] + pub syncbusy: crate::Reg, + _reserved8: [u8; 0x04], + #[doc = "0x24 - I2CM Address"] + pub addr: crate::Reg, + #[doc = "0x28 - I2CM Data"] + pub data: crate::Reg, + _reserved10: [u8; 0x07], + #[doc = "0x30 - I2CM Debug Control"] + pub dbgctrl: crate::Reg, +} +#[doc = r"Register block"] +#[doc = "I2C Master Mode"] +pub mod i2cm; +#[doc = r"Register block"] +#[repr(C)] +pub struct I2CS { + #[doc = "0x00 - I2CS Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - I2CS Control B"] + pub ctrlb: crate::Reg, + _reserved2: [u8; 0x0c], + #[doc = "0x14 - I2CS Interrupt Enable Clear"] + pub intenclr: crate::Reg, + _reserved3: [u8; 0x01], + #[doc = "0x16 - I2CS Interrupt Enable Set"] + pub intenset: crate::Reg, + _reserved4: [u8; 0x01], + #[doc = "0x18 - I2CS Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved5: [u8; 0x01], + #[doc = "0x1a - I2CS Status"] + pub status: crate::Reg, + #[doc = "0x1c - I2CS Synchronization Busy"] + pub syncbusy: crate::Reg, + _reserved7: [u8; 0x04], + #[doc = "0x24 - I2CS Address"] + pub addr: crate::Reg, + #[doc = "0x28 - I2CS Data"] + pub data: crate::Reg, +} +#[doc = r"Register block"] +#[doc = "I2C Slave Mode"] +pub mod i2cs; +#[doc = r"Register block"] +#[repr(C)] +pub struct SPIS { + #[doc = "0x00 - SPIS Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - SPIS Control B"] + pub ctrlb: crate::Reg, + _reserved2: [u8; 0x04], + #[doc = "0x0c - SPIS Baud Rate"] + pub baud: crate::Reg, + _reserved3: [u8; 0x07], + #[doc = "0x14 - SPIS Interrupt Enable Clear"] + pub intenclr: crate::Reg, + _reserved4: [u8; 0x01], + #[doc = "0x16 - SPIS Interrupt Enable Set"] + pub intenset: crate::Reg, + _reserved5: [u8; 0x01], + #[doc = "0x18 - SPIS Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x1a - SPIS Status"] + pub status: crate::Reg, + #[doc = "0x1c - SPIS Synchronization Busy"] + pub syncbusy: crate::Reg, + _reserved8: [u8; 0x04], + #[doc = "0x24 - SPIS Address"] + pub addr: crate::Reg, + #[doc = "0x28 - SPIS Data"] + pub data: crate::Reg, + _reserved10: [u8; 0x04], + #[doc = "0x30 - SPIS Debug Control"] + pub dbgctrl: crate::Reg, +} +#[doc = r"Register block"] +#[doc = "SPI Slave Mode"] +pub mod spis; +#[doc = r"Register block"] +#[repr(C)] +pub struct SPIM { + #[doc = "0x00 - SPIM Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - SPIM Control B"] + pub ctrlb: crate::Reg, + _reserved2: [u8; 0x04], + #[doc = "0x0c - SPIM Baud Rate"] + pub baud: crate::Reg, + _reserved3: [u8; 0x07], + #[doc = "0x14 - SPIM Interrupt Enable Clear"] + pub intenclr: crate::Reg, + _reserved4: [u8; 0x01], + #[doc = "0x16 - SPIM Interrupt Enable Set"] + pub intenset: crate::Reg, + _reserved5: [u8; 0x01], + #[doc = "0x18 - SPIM Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x1a - SPIM Status"] + pub status: crate::Reg, + #[doc = "0x1c - SPIM Synchronization Busy"] + pub syncbusy: crate::Reg, + _reserved8: [u8; 0x04], + #[doc = "0x24 - SPIM Address"] + pub addr: crate::Reg, + #[doc = "0x28 - SPIM Data"] + pub data: crate::Reg, + _reserved10: [u8; 0x04], + #[doc = "0x30 - SPIM Debug Control"] + pub dbgctrl: crate::Reg, +} +#[doc = r"Register block"] +#[doc = "SPI Master Mode"] +pub mod spim; +#[doc = r"Register block"] +#[repr(C)] +pub struct USART_EXT { + #[doc = "0x00 - USART_EXT Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - USART_EXT Control B"] + pub ctrlb: crate::Reg, + #[doc = "0x08 - USART_EXT Control C"] + pub ctrlc: crate::Reg, + _reserved_3_baud: [u8; 0x02], + #[doc = "0x0e - USART_EXT Receive Pulse Length"] + pub rxpl: crate::Reg, + _reserved5: [u8; 0x05], + #[doc = "0x14 - USART_EXT Interrupt Enable Clear"] + pub intenclr: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x16 - USART_EXT Interrupt Enable Set"] + pub intenset: crate::Reg, + _reserved7: [u8; 0x01], + #[doc = "0x18 - USART_EXT Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved8: [u8; 0x01], + #[doc = "0x1a - USART_EXT Status"] + pub status: crate::Reg, + #[doc = "0x1c - USART_EXT Synchronization Busy"] + pub syncbusy: crate::Reg, + _reserved10: [u8; 0x08], + #[doc = "0x28 - USART_EXT Data"] + pub data: crate::Reg, + _reserved11: [u8; 0x06], + #[doc = "0x30 - USART_EXT Debug Control"] + pub dbgctrl: crate::Reg, +} +impl USART_EXT { + #[doc = "0x0c - USART_EXT Baud Rate"] + #[inline(always)] + pub fn baud_usartfp_mode( + &self, + ) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } + #[doc = "0x0c - USART_EXT Baud Rate"] + #[inline(always)] + pub fn baud_fracfp_mode( + &self, + ) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } + #[doc = "0x0c - USART_EXT Baud Rate"] + #[inline(always)] + pub fn baud_frac_mode( + &self, + ) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } + #[doc = "0x0c - USART_EXT Baud Rate"] + #[inline(always)] + pub fn baud(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } +} +#[doc = r"Register block"] +#[doc = "USART EXTERNAL CLOCK Mode"] +pub mod usart_ext; +#[doc = r"Register block"] +#[repr(C)] +pub struct USART_INT { + #[doc = "0x00 - USART_INT Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - USART_INT Control B"] + pub ctrlb: crate::Reg, + #[doc = "0x08 - USART_INT Control C"] + pub ctrlc: crate::Reg, + _reserved_3_baud: [u8; 0x02], + #[doc = "0x0e - USART_INT Receive Pulse Length"] + pub rxpl: crate::Reg, + _reserved5: [u8; 0x05], + #[doc = "0x14 - USART_INT Interrupt Enable Clear"] + pub intenclr: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x16 - USART_INT Interrupt Enable Set"] + pub intenset: crate::Reg, + _reserved7: [u8; 0x01], + #[doc = "0x18 - USART_INT Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved8: [u8; 0x01], + #[doc = "0x1a - USART_INT Status"] + pub status: crate::Reg, + #[doc = "0x1c - USART_INT Synchronization Busy"] + pub syncbusy: crate::Reg, + _reserved10: [u8; 0x08], + #[doc = "0x28 - USART_INT Data"] + pub data: crate::Reg, + _reserved11: [u8; 0x06], + #[doc = "0x30 - USART_INT Debug Control"] + pub dbgctrl: crate::Reg, +} +impl USART_INT { + #[doc = "0x0c - USART_INT Baud Rate"] + #[inline(always)] + pub fn baud_usartfp_mode( + &self, + ) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } + #[doc = "0x0c - USART_INT Baud Rate"] + #[inline(always)] + pub fn baud_fracfp_mode( + &self, + ) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } + #[doc = "0x0c - USART_INT Baud Rate"] + #[inline(always)] + pub fn baud_frac_mode( + &self, + ) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } + #[doc = "0x0c - USART_INT Baud Rate"] + #[inline(always)] + pub fn baud(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } +} +#[doc = r"Register block"] +#[doc = "USART INTERNAL CLOCK Mode"] +pub mod usart_int; diff --git a/pac/atsamc20g/src/sercom0/i2cm.rs b/pac/atsamc20g/src/sercom0/i2cm.rs new file mode 100644 index 000000000000..8aa217da8b18 --- /dev/null +++ b/pac/atsamc20g/src/sercom0/i2cm.rs @@ -0,0 +1,44 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "I2CM Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "I2CM Control B"] +pub mod ctrlb; +#[doc = "BAUD register accessor: an alias for `Reg`"] +pub type BAUD = crate::Reg; +#[doc = "I2CM Baud Rate"] +pub mod baud; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "I2CM Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "I2CM Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "I2CM Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "I2CM Status"] +pub mod status; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "I2CM Synchronization Busy"] +pub mod syncbusy; +#[doc = "ADDR register accessor: an alias for `Reg`"] +pub type ADDR = crate::Reg; +#[doc = "I2CM Address"] +pub mod addr; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "I2CM Data"] +pub mod data; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "I2CM Debug Control"] +pub mod dbgctrl; diff --git a/pac/atsamc20g/src/sercom0/i2cm/addr.rs b/pac/atsamc20g/src/sercom0/i2cm/addr.rs new file mode 100644 index 000000000000..4efd19e824c6 --- /dev/null +++ b/pac/atsamc20g/src/sercom0/i2cm/addr.rs @@ -0,0 +1,281 @@ +#[doc = "Register `ADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ADDR` reader - Address Value"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - Address Value"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07ff) | (value as u32 & 0x07ff); + self.w + } +} +#[doc = "Field `LENEN` reader - Length Enable"] +pub struct LENEN_R(crate::FieldReader); +impl LENEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LENEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LENEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LENEN` writer - Length Enable"] +pub struct LENEN_W<'a> { + w: &'a mut W, +} +impl<'a> LENEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `HS` reader - High Speed Mode"] +pub struct HS_R(crate::FieldReader); +impl HS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HS` writer - High Speed Mode"] +pub struct HS_W<'a> { + w: &'a mut W, +} +impl<'a> HS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `TENBITEN` reader - Ten Bit Addressing Enable"] +pub struct TENBITEN_R(crate::FieldReader); +impl TENBITEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TENBITEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TENBITEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TENBITEN` writer - Ten Bit Addressing Enable"] +pub struct TENBITEN_W<'a> { + w: &'a mut W, +} +impl<'a> TENBITEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `LEN` reader - Length"] +pub struct LEN_R(crate::FieldReader); +impl LEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LEN` writer - Length"] +pub struct LEN_W<'a> { + w: &'a mut W, +} +impl<'a> LEN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:10 - Address Value"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new((self.bits & 0x07ff) as u16) + } + #[doc = "Bit 13 - Length Enable"] + #[inline(always)] + pub fn lenen(&self) -> LENEN_R { + LENEN_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - High Speed Mode"] + #[inline(always)] + pub fn hs(&self) -> HS_R { + HS_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Ten Bit Addressing Enable"] + #[inline(always)] + pub fn tenbiten(&self) -> TENBITEN_R { + TENBITEN_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:23 - Length"] + #[inline(always)] + pub fn len(&self) -> LEN_R { + LEN_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:10 - Address Value"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Bit 13 - Length Enable"] + #[inline(always)] + pub fn lenen(&mut self) -> LENEN_W { + LENEN_W { w: self } + } + #[doc = "Bit 14 - High Speed Mode"] + #[inline(always)] + pub fn hs(&mut self) -> HS_W { + HS_W { w: self } + } + #[doc = "Bit 15 - Ten Bit Addressing Enable"] + #[inline(always)] + pub fn tenbiten(&mut self) -> TENBITEN_W { + TENBITEN_W { w: self } + } + #[doc = "Bits 16:23 - Length"] + #[inline(always)] + pub fn len(&mut self) -> LEN_W { + LEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [addr](index.html) module"] +pub struct ADDR_SPEC; +impl crate::RegisterSpec for ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [addr::R](R) reader structure"] +impl crate::Readable for ADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [addr::W](W) writer structure"] +impl crate::Writable for ADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ADDR to value 0"] +impl crate::Resettable for ADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/sercom0/i2cm/baud.rs b/pac/atsamc20g/src/sercom0/i2cm/baud.rs new file mode 100644 index 000000000000..7c98d3b5b0de --- /dev/null +++ b/pac/atsamc20g/src/sercom0/i2cm/baud.rs @@ -0,0 +1,214 @@ +#[doc = "Register `BAUD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +#[doc = "Field `BAUDLOW` reader - Baud Rate Value Low"] +pub struct BAUDLOW_R(crate::FieldReader); +impl BAUDLOW_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BAUDLOW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUDLOW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUDLOW` writer - Baud Rate Value Low"] +pub struct BAUDLOW_W<'a> { + w: &'a mut W, +} +impl<'a> BAUDLOW_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +#[doc = "Field `HSBAUD` reader - High Speed Baud Rate Value"] +pub struct HSBAUD_R(crate::FieldReader); +impl HSBAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + HSBAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HSBAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HSBAUD` writer - High Speed Baud Rate Value"] +pub struct HSBAUD_W<'a> { + w: &'a mut W, +} +impl<'a> HSBAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +#[doc = "Field `HSBAUDLOW` reader - High Speed Baud Rate Value Low"] +pub struct HSBAUDLOW_R(crate::FieldReader); +impl HSBAUDLOW_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + HSBAUDLOW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HSBAUDLOW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HSBAUDLOW` writer - High Speed Baud Rate Value Low"] +pub struct HSBAUDLOW_W<'a> { + w: &'a mut W, +} +impl<'a> HSBAUDLOW_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 24)) | ((value as u32 & 0xff) << 24); + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Baud Rate Value Low"] + #[inline(always)] + pub fn baudlow(&self) -> BAUDLOW_R { + BAUDLOW_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - High Speed Baud Rate Value"] + #[inline(always)] + pub fn hsbaud(&self) -> HSBAUD_R { + HSBAUD_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - High Speed Baud Rate Value Low"] + #[inline(always)] + pub fn hsbaudlow(&self) -> HSBAUDLOW_R { + HSBAUDLOW_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Bits 8:15 - Baud Rate Value Low"] + #[inline(always)] + pub fn baudlow(&mut self) -> BAUDLOW_W { + BAUDLOW_W { w: self } + } + #[doc = "Bits 16:23 - High Speed Baud Rate Value"] + #[inline(always)] + pub fn hsbaud(&mut self) -> HSBAUD_W { + HSBAUD_W { w: self } + } + #[doc = "Bits 24:31 - High Speed Baud Rate Value Low"] + #[inline(always)] + pub fn hsbaudlow(&mut self) -> HSBAUDLOW_W { + HSBAUDLOW_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud](index.html) module"] +pub struct BAUD_SPEC; +impl crate::RegisterSpec for BAUD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [baud::R](R) reader structure"] +impl crate::Readable for BAUD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud::W](W) writer structure"] +impl crate::Writable for BAUD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD to value 0"] +impl crate::Resettable for BAUD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/sercom0/i2cm/ctrla.rs b/pac/atsamc20g/src/sercom0/i2cm/ctrla.rs new file mode 100644 index 000000000000..34fa668b7967 --- /dev/null +++ b/pac/atsamc20g/src/sercom0/i2cm/ctrla.rs @@ -0,0 +1,903 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: USART with external clock"] + USART_EXT_CLK = 0, + #[doc = "1: USART with internal clock"] + USART_INT_CLK = 1, + #[doc = "2: SPI in slave operation"] + SPI_SLAVE = 2, + #[doc = "3: SPI in master operation"] + SPI_MASTER = 3, + #[doc = "4: I2C slave operation"] + I2C_SLAVE = 4, + #[doc = "5: I2C master operation"] + I2C_MASTER = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::USART_EXT_CLK), + 1 => Some(MODE_A::USART_INT_CLK), + 2 => Some(MODE_A::SPI_SLAVE), + 3 => Some(MODE_A::SPI_MASTER), + 4 => Some(MODE_A::I2C_SLAVE), + 5 => Some(MODE_A::I2C_MASTER), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_EXT_CLK`"] + #[inline(always)] + pub fn is_usart_ext_clk(&self) -> bool { + **self == MODE_A::USART_EXT_CLK + } + #[doc = "Checks if the value of the field is `USART_INT_CLK`"] + #[inline(always)] + pub fn is_usart_int_clk(&self) -> bool { + **self == MODE_A::USART_INT_CLK + } + #[doc = "Checks if the value of the field is `SPI_SLAVE`"] + #[inline(always)] + pub fn is_spi_slave(&self) -> bool { + **self == MODE_A::SPI_SLAVE + } + #[doc = "Checks if the value of the field is `SPI_MASTER`"] + #[inline(always)] + pub fn is_spi_master(&self) -> bool { + **self == MODE_A::SPI_MASTER + } + #[doc = "Checks if the value of the field is `I2C_SLAVE`"] + #[inline(always)] + pub fn is_i2c_slave(&self) -> bool { + **self == MODE_A::I2C_SLAVE + } + #[doc = "Checks if the value of the field is `I2C_MASTER`"] + #[inline(always)] + pub fn is_i2c_master(&self) -> bool { + **self == MODE_A::I2C_MASTER + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART with external clock"] + #[inline(always)] + pub fn usart_ext_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_EXT_CLK) + } + #[doc = "USART with internal clock"] + #[inline(always)] + pub fn usart_int_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_INT_CLK) + } + #[doc = "SPI in slave operation"] + #[inline(always)] + pub fn spi_slave(self) -> &'a mut W { + self.variant(MODE_A::SPI_SLAVE) + } + #[doc = "SPI in master operation"] + #[inline(always)] + pub fn spi_master(self) -> &'a mut W { + self.variant(MODE_A::SPI_MASTER) + } + #[doc = "I2C slave operation"] + #[inline(always)] + pub fn i2c_slave(self) -> &'a mut W { + self.variant(MODE_A::I2C_SLAVE) + } + #[doc = "I2C master operation"] + #[inline(always)] + pub fn i2c_master(self) -> &'a mut W { + self.variant(MODE_A::I2C_MASTER) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 2)) | ((value as u32 & 0x07) << 2); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `PINOUT` reader - Pin Usage"] +pub struct PINOUT_R(crate::FieldReader); +impl PINOUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PINOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PINOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PINOUT` writer - Pin Usage"] +pub struct PINOUT_W<'a> { + w: &'a mut W, +} +impl<'a> PINOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "SDA Hold Time\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SDAHOLD_A { + #[doc = "0: Disabled"] + DISABLE = 0, + #[doc = "1: 50-100ns hold time"] + _75NS = 1, + #[doc = "2: 300-600ns hold time"] + _450NS = 2, + #[doc = "3: 400-800ns hold time"] + _600NS = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SDAHOLD_A) -> Self { + variant as _ + } +} +#[doc = "Field `SDAHOLD` reader - SDA Hold Time"] +pub struct SDAHOLD_R(crate::FieldReader); +impl SDAHOLD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SDAHOLD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SDAHOLD_A { + match self.bits { + 0 => SDAHOLD_A::DISABLE, + 1 => SDAHOLD_A::_75NS, + 2 => SDAHOLD_A::_450NS, + 3 => SDAHOLD_A::_600NS, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == SDAHOLD_A::DISABLE + } + #[doc = "Checks if the value of the field is `_75NS`"] + #[inline(always)] + pub fn is_75ns(&self) -> bool { + **self == SDAHOLD_A::_75NS + } + #[doc = "Checks if the value of the field is `_450NS`"] + #[inline(always)] + pub fn is_450ns(&self) -> bool { + **self == SDAHOLD_A::_450NS + } + #[doc = "Checks if the value of the field is `_600NS`"] + #[inline(always)] + pub fn is_600ns(&self) -> bool { + **self == SDAHOLD_A::_600NS + } +} +impl core::ops::Deref for SDAHOLD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SDAHOLD` writer - SDA Hold Time"] +pub struct SDAHOLD_W<'a> { + w: &'a mut W, +} +impl<'a> SDAHOLD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SDAHOLD_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(SDAHOLD_A::DISABLE) + } + #[doc = "50-100ns hold time"] + #[inline(always)] + pub fn _75ns(self) -> &'a mut W { + self.variant(SDAHOLD_A::_75NS) + } + #[doc = "300-600ns hold time"] + #[inline(always)] + pub fn _450ns(self) -> &'a mut W { + self.variant(SDAHOLD_A::_450NS) + } + #[doc = "400-800ns hold time"] + #[inline(always)] + pub fn _600ns(self) -> &'a mut W { + self.variant(SDAHOLD_A::_600NS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 20)) | ((value as u32 & 0x03) << 20); + self.w + } +} +#[doc = "Field `MEXTTOEN` reader - Master SCL Low Extend Timeout"] +pub struct MEXTTOEN_R(crate::FieldReader); +impl MEXTTOEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MEXTTOEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MEXTTOEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MEXTTOEN` writer - Master SCL Low Extend Timeout"] +pub struct MEXTTOEN_W<'a> { + w: &'a mut W, +} +impl<'a> MEXTTOEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `SEXTTOEN` reader - Slave SCL Low Extend Timeout"] +pub struct SEXTTOEN_R(crate::FieldReader); +impl SEXTTOEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SEXTTOEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEXTTOEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEXTTOEN` writer - Slave SCL Low Extend Timeout"] +pub struct SEXTTOEN_W<'a> { + w: &'a mut W, +} +impl<'a> SEXTTOEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Transfer Speed\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SPEED_A { + #[doc = "0: Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz"] + STANDARD_AND_FAST_MODE = 0, + #[doc = "1: Fast-mode Plus Upto 1MHz"] + FASTPLUS_MODE = 1, + #[doc = "2: High-speed mode Upto 3.4MHz"] + HIGH_SPEED_MODE = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SPEED_A) -> Self { + variant as _ + } +} +#[doc = "Field `SPEED` reader - Transfer Speed"] +pub struct SPEED_R(crate::FieldReader); +impl SPEED_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SPEED_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SPEED_A::STANDARD_AND_FAST_MODE), + 1 => Some(SPEED_A::FASTPLUS_MODE), + 2 => Some(SPEED_A::HIGH_SPEED_MODE), + _ => None, + } + } + #[doc = "Checks if the value of the field is `STANDARD_AND_FAST_MODE`"] + #[inline(always)] + pub fn is_standard_and_fast_mode(&self) -> bool { + **self == SPEED_A::STANDARD_AND_FAST_MODE + } + #[doc = "Checks if the value of the field is `FASTPLUS_MODE`"] + #[inline(always)] + pub fn is_fastplus_mode(&self) -> bool { + **self == SPEED_A::FASTPLUS_MODE + } + #[doc = "Checks if the value of the field is `HIGH_SPEED_MODE`"] + #[inline(always)] + pub fn is_high_speed_mode(&self) -> bool { + **self == SPEED_A::HIGH_SPEED_MODE + } +} +impl core::ops::Deref for SPEED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SPEED` writer - Transfer Speed"] +pub struct SPEED_W<'a> { + w: &'a mut W, +} +impl<'a> SPEED_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SPEED_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz"] + #[inline(always)] + pub fn standard_and_fast_mode(self) -> &'a mut W { + self.variant(SPEED_A::STANDARD_AND_FAST_MODE) + } + #[doc = "Fast-mode Plus Upto 1MHz"] + #[inline(always)] + pub fn fastplus_mode(self) -> &'a mut W { + self.variant(SPEED_A::FASTPLUS_MODE) + } + #[doc = "High-speed mode Upto 3.4MHz"] + #[inline(always)] + pub fn high_speed_mode(self) -> &'a mut W { + self.variant(SPEED_A::HIGH_SPEED_MODE) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 24)) | ((value as u32 & 0x03) << 24); + self.w + } +} +#[doc = "Field `SCLSM` reader - SCL Clock Stretch Mode"] +pub struct SCLSM_R(crate::FieldReader); +impl SCLSM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SCLSM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SCLSM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SCLSM` writer - SCL Clock Stretch Mode"] +pub struct SCLSM_W<'a> { + w: &'a mut W, +} +impl<'a> SCLSM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +#[doc = "Inactive Time-Out\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum INACTOUT_A { + #[doc = "0: Disabled"] + DISABLE = 0, + #[doc = "1: 5-6 SCL Time-Out(50-60us)"] + _55US = 1, + #[doc = "2: 10-11 SCL Time-Out(100-110us)"] + _105US = 2, + #[doc = "3: 20-21 SCL Time-Out(200-210us)"] + _205US = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: INACTOUT_A) -> Self { + variant as _ + } +} +#[doc = "Field `INACTOUT` reader - Inactive Time-Out"] +pub struct INACTOUT_R(crate::FieldReader); +impl INACTOUT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + INACTOUT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INACTOUT_A { + match self.bits { + 0 => INACTOUT_A::DISABLE, + 1 => INACTOUT_A::_55US, + 2 => INACTOUT_A::_105US, + 3 => INACTOUT_A::_205US, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == INACTOUT_A::DISABLE + } + #[doc = "Checks if the value of the field is `_55US`"] + #[inline(always)] + pub fn is_55us(&self) -> bool { + **self == INACTOUT_A::_55US + } + #[doc = "Checks if the value of the field is `_105US`"] + #[inline(always)] + pub fn is_105us(&self) -> bool { + **self == INACTOUT_A::_105US + } + #[doc = "Checks if the value of the field is `_205US`"] + #[inline(always)] + pub fn is_205us(&self) -> bool { + **self == INACTOUT_A::_205US + } +} +impl core::ops::Deref for INACTOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INACTOUT` writer - Inactive Time-Out"] +pub struct INACTOUT_W<'a> { + w: &'a mut W, +} +impl<'a> INACTOUT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: INACTOUT_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(INACTOUT_A::DISABLE) + } + #[doc = "5-6 SCL Time-Out(50-60us)"] + #[inline(always)] + pub fn _55us(self) -> &'a mut W { + self.variant(INACTOUT_A::_55US) + } + #[doc = "10-11 SCL Time-Out(100-110us)"] + #[inline(always)] + pub fn _105us(self) -> &'a mut W { + self.variant(INACTOUT_A::_105US) + } + #[doc = "20-21 SCL Time-Out(200-210us)"] + #[inline(always)] + pub fn _205us(self) -> &'a mut W { + self.variant(INACTOUT_A::_205US) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 28)) | ((value as u32 & 0x03) << 28); + self.w + } +} +#[doc = "Field `LOWTOUTEN` reader - SCL Low Timeout Enable"] +pub struct LOWTOUTEN_R(crate::FieldReader); +impl LOWTOUTEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LOWTOUTEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOWTOUTEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LOWTOUTEN` writer - SCL Low Timeout Enable"] +pub struct LOWTOUTEN_W<'a> { + w: &'a mut W, +} +impl<'a> LOWTOUTEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x07) as u8) + } + #[doc = "Bit 7 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 16 - Pin Usage"] + #[inline(always)] + pub fn pinout(&self) -> PINOUT_R { + PINOUT_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bits 20:21 - SDA Hold Time"] + #[inline(always)] + pub fn sdahold(&self) -> SDAHOLD_R { + SDAHOLD_R::new(((self.bits >> 20) & 0x03) as u8) + } + #[doc = "Bit 22 - Master SCL Low Extend Timeout"] + #[inline(always)] + pub fn mexttoen(&self) -> MEXTTOEN_R { + MEXTTOEN_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttoen(&self) -> SEXTTOEN_R { + SEXTTOEN_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bits 24:25 - Transfer Speed"] + #[inline(always)] + pub fn speed(&self) -> SPEED_R { + SPEED_R::new(((self.bits >> 24) & 0x03) as u8) + } + #[doc = "Bit 27 - SCL Clock Stretch Mode"] + #[inline(always)] + pub fn sclsm(&self) -> SCLSM_R { + SCLSM_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bits 28:29 - Inactive Time-Out"] + #[inline(always)] + pub fn inactout(&self) -> INACTOUT_R { + INACTOUT_R::new(((self.bits >> 28) & 0x03) as u8) + } + #[doc = "Bit 30 - SCL Low Timeout Enable"] + #[inline(always)] + pub fn lowtouten(&self) -> LOWTOUTEN_R { + LOWTOUTEN_R::new(((self.bits >> 30) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 7 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 16 - Pin Usage"] + #[inline(always)] + pub fn pinout(&mut self) -> PINOUT_W { + PINOUT_W { w: self } + } + #[doc = "Bits 20:21 - SDA Hold Time"] + #[inline(always)] + pub fn sdahold(&mut self) -> SDAHOLD_W { + SDAHOLD_W { w: self } + } + #[doc = "Bit 22 - Master SCL Low Extend Timeout"] + #[inline(always)] + pub fn mexttoen(&mut self) -> MEXTTOEN_W { + MEXTTOEN_W { w: self } + } + #[doc = "Bit 23 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttoen(&mut self) -> SEXTTOEN_W { + SEXTTOEN_W { w: self } + } + #[doc = "Bits 24:25 - Transfer Speed"] + #[inline(always)] + pub fn speed(&mut self) -> SPEED_W { + SPEED_W { w: self } + } + #[doc = "Bit 27 - SCL Clock Stretch Mode"] + #[inline(always)] + pub fn sclsm(&mut self) -> SCLSM_W { + SCLSM_W { w: self } + } + #[doc = "Bits 28:29 - Inactive Time-Out"] + #[inline(always)] + pub fn inactout(&mut self) -> INACTOUT_W { + INACTOUT_W { w: self } + } + #[doc = "Bit 30 - SCL Low Timeout Enable"] + #[inline(always)] + pub fn lowtouten(&mut self) -> LOWTOUTEN_W { + LOWTOUTEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/sercom0/i2cm/ctrlb.rs b/pac/atsamc20g/src/sercom0/i2cm/ctrlb.rs new file mode 100644 index 000000000000..ce534463c0da --- /dev/null +++ b/pac/atsamc20g/src/sercom0/i2cm/ctrlb.rs @@ -0,0 +1,244 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SMEN` reader - Smart Mode Enable"] +pub struct SMEN_R(crate::FieldReader); +impl SMEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SMEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SMEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SMEN` writer - Smart Mode Enable"] +pub struct SMEN_W<'a> { + w: &'a mut W, +} +impl<'a> SMEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `QCEN` reader - Quick Command Enable"] +pub struct QCEN_R(crate::FieldReader); +impl QCEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + QCEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for QCEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `QCEN` writer - Quick Command Enable"] +pub struct QCEN_W<'a> { + w: &'a mut W, +} +impl<'a> QCEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Field `ACKACT` reader - Acknowledge Action"] +pub struct ACKACT_R(crate::FieldReader); +impl ACKACT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ACKACT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ACKACT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ACKACT` writer - Acknowledge Action"] +pub struct ACKACT_W<'a> { + w: &'a mut W, +} +impl<'a> ACKACT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +impl R { + #[doc = "Bit 8 - Smart Mode Enable"] + #[inline(always)] + pub fn smen(&self) -> SMEN_R { + SMEN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Quick Command Enable"] + #[inline(always)] + pub fn qcen(&self) -> QCEN_R { + QCEN_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bits 16:17 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bit 18 - Acknowledge Action"] + #[inline(always)] + pub fn ackact(&self) -> ACKACT_R { + ACKACT_R::new(((self.bits >> 18) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 8 - Smart Mode Enable"] + #[inline(always)] + pub fn smen(&mut self) -> SMEN_W { + SMEN_W { w: self } + } + #[doc = "Bit 9 - Quick Command Enable"] + #[inline(always)] + pub fn qcen(&mut self) -> QCEN_W { + QCEN_W { w: self } + } + #[doc = "Bits 16:17 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Bit 18 - Acknowledge Action"] + #[inline(always)] + pub fn ackact(&mut self) -> ACKACT_W { + ACKACT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/sercom0/i2cm/data.rs b/pac/atsamc20g/src/sercom0/i2cm/data.rs new file mode 100644 index 000000000000..cf204596d3a6 --- /dev/null +++ b/pac/atsamc20g/src/sercom0/i2cm/data.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data Value"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data Value"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Data Value"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Value"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/sercom0/i2cm/dbgctrl.rs b/pac/atsamc20g/src/sercom0/i2cm/dbgctrl.rs new file mode 100644 index 000000000000..0fffdb4c6e39 --- /dev/null +++ b/pac/atsamc20g/src/sercom0/i2cm/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGSTOP` reader - Debug Mode"] +pub struct DBGSTOP_R(crate::FieldReader); +impl DBGSTOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGSTOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGSTOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGSTOP` writer - Debug Mode"] +pub struct DBGSTOP_W<'a> { + w: &'a mut W, +} +impl<'a> DBGSTOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&self) -> DBGSTOP_R { + DBGSTOP_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&mut self) -> DBGSTOP_W { + DBGSTOP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/sercom0/i2cm/intenclr.rs b/pac/atsamc20g/src/sercom0/i2cm/intenclr.rs new file mode 100644 index 000000000000..17f067a55656 --- /dev/null +++ b/pac/atsamc20g/src/sercom0/i2cm/intenclr.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MB` reader - Master On Bus Interrupt Disable"] +pub struct MB_R(crate::FieldReader); +impl MB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MB` writer - Master On Bus Interrupt Disable"] +pub struct MB_W<'a> { + w: &'a mut W, +} +impl<'a> MB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SB` reader - Slave On Bus Interrupt Disable"] +pub struct SB_R(crate::FieldReader); +impl SB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SB` writer - Slave On Bus Interrupt Disable"] +pub struct SB_W<'a> { + w: &'a mut W, +} +impl<'a> SB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Disable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Disable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Master On Bus Interrupt Disable"] + #[inline(always)] + pub fn mb(&self) -> MB_R { + MB_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Slave On Bus Interrupt Disable"] + #[inline(always)] + pub fn sb(&self) -> SB_R { + SB_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Master On Bus Interrupt Disable"] + #[inline(always)] + pub fn mb(&mut self) -> MB_W { + MB_W { w: self } + } + #[doc = "Bit 1 - Slave On Bus Interrupt Disable"] + #[inline(always)] + pub fn sb(&mut self) -> SB_W { + SB_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/sercom0/i2cm/intenset.rs b/pac/atsamc20g/src/sercom0/i2cm/intenset.rs new file mode 100644 index 000000000000..a0cbf96b3aa0 --- /dev/null +++ b/pac/atsamc20g/src/sercom0/i2cm/intenset.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MB` reader - Master On Bus Interrupt Enable"] +pub struct MB_R(crate::FieldReader); +impl MB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MB` writer - Master On Bus Interrupt Enable"] +pub struct MB_W<'a> { + w: &'a mut W, +} +impl<'a> MB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SB` reader - Slave On Bus Interrupt Enable"] +pub struct SB_R(crate::FieldReader); +impl SB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SB` writer - Slave On Bus Interrupt Enable"] +pub struct SB_W<'a> { + w: &'a mut W, +} +impl<'a> SB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Master On Bus Interrupt Enable"] + #[inline(always)] + pub fn mb(&self) -> MB_R { + MB_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Slave On Bus Interrupt Enable"] + #[inline(always)] + pub fn sb(&self) -> SB_R { + SB_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Master On Bus Interrupt Enable"] + #[inline(always)] + pub fn mb(&mut self) -> MB_W { + MB_W { w: self } + } + #[doc = "Bit 1 - Slave On Bus Interrupt Enable"] + #[inline(always)] + pub fn sb(&mut self) -> SB_W { + SB_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/sercom0/i2cm/intflag.rs b/pac/atsamc20g/src/sercom0/i2cm/intflag.rs new file mode 100644 index 000000000000..0fb0d2b9060c --- /dev/null +++ b/pac/atsamc20g/src/sercom0/i2cm/intflag.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MB` reader - Master On Bus Interrupt"] +pub struct MB_R(crate::FieldReader); +impl MB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MB` writer - Master On Bus Interrupt"] +pub struct MB_W<'a> { + w: &'a mut W, +} +impl<'a> MB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SB` reader - Slave On Bus Interrupt"] +pub struct SB_R(crate::FieldReader); +impl SB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SB` writer - Slave On Bus Interrupt"] +pub struct SB_W<'a> { + w: &'a mut W, +} +impl<'a> SB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Master On Bus Interrupt"] + #[inline(always)] + pub fn mb(&self) -> MB_R { + MB_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Slave On Bus Interrupt"] + #[inline(always)] + pub fn sb(&self) -> SB_R { + SB_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Master On Bus Interrupt"] + #[inline(always)] + pub fn mb(&mut self) -> MB_W { + MB_W { w: self } + } + #[doc = "Bit 1 - Slave On Bus Interrupt"] + #[inline(always)] + pub fn sb(&mut self) -> SB_W { + SB_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/sercom0/i2cm/status.rs b/pac/atsamc20g/src/sercom0/i2cm/status.rs new file mode 100644 index 000000000000..95af23673ec4 --- /dev/null +++ b/pac/atsamc20g/src/sercom0/i2cm/status.rs @@ -0,0 +1,479 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BUSERR` reader - Bus Error"] +pub struct BUSERR_R(crate::FieldReader); +impl BUSERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSERR` writer - Bus Error"] +pub struct BUSERR_W<'a> { + w: &'a mut W, +} +impl<'a> BUSERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `ARBLOST` reader - Arbitration Lost"] +pub struct ARBLOST_R(crate::FieldReader); +impl ARBLOST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ARBLOST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ARBLOST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ARBLOST` writer - Arbitration Lost"] +pub struct ARBLOST_W<'a> { + w: &'a mut W, +} +impl<'a> ARBLOST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXNACK` reader - Received Not Acknowledge"] +pub struct RXNACK_R(crate::FieldReader); +impl RXNACK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXNACK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXNACK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXNACK` writer - Received Not Acknowledge"] +pub struct RXNACK_W<'a> { + w: &'a mut W, +} +impl<'a> RXNACK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `BUSSTATE` reader - Bus State"] +pub struct BUSSTATE_R(crate::FieldReader); +impl BUSSTATE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BUSSTATE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSSTATE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSSTATE` writer - Bus State"] +pub struct BUSSTATE_W<'a> { + w: &'a mut W, +} +impl<'a> BUSSTATE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u16 & 0x03) << 4); + self.w + } +} +#[doc = "Field `LOWTOUT` reader - SCL Low Timeout"] +pub struct LOWTOUT_R(crate::FieldReader); +impl LOWTOUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LOWTOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOWTOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LOWTOUT` writer - SCL Low Timeout"] +pub struct LOWTOUT_W<'a> { + w: &'a mut W, +} +impl<'a> LOWTOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `CLKHOLD` reader - Clock Hold"] +pub struct CLKHOLD_R(crate::FieldReader); +impl CLKHOLD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKHOLD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKHOLD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKHOLD` writer - Clock Hold"] +pub struct CLKHOLD_W<'a> { + w: &'a mut W, +} +impl<'a> CLKHOLD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `MEXTTOUT` reader - Master SCL Low Extend Timeout"] +pub struct MEXTTOUT_R(crate::FieldReader); +impl MEXTTOUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MEXTTOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MEXTTOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MEXTTOUT` writer - Master SCL Low Extend Timeout"] +pub struct MEXTTOUT_W<'a> { + w: &'a mut W, +} +impl<'a> MEXTTOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `SEXTTOUT` reader - Slave SCL Low Extend Timeout"] +pub struct SEXTTOUT_R(crate::FieldReader); +impl SEXTTOUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SEXTTOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEXTTOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEXTTOUT` writer - Slave SCL Low Extend Timeout"] +pub struct SEXTTOUT_W<'a> { + w: &'a mut W, +} +impl<'a> SEXTTOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `LENERR` reader - Length Error"] +pub struct LENERR_R(crate::FieldReader); +impl LENERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LENERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LENERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LENERR` writer - Length Error"] +pub struct LENERR_W<'a> { + w: &'a mut W, +} +impl<'a> LENERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u16 & 0x01) << 10); + self.w + } +} +impl R { + #[doc = "Bit 0 - Bus Error"] + #[inline(always)] + pub fn buserr(&self) -> BUSERR_R { + BUSERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Arbitration Lost"] + #[inline(always)] + pub fn arblost(&self) -> ARBLOST_R { + ARBLOST_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Received Not Acknowledge"] + #[inline(always)] + pub fn rxnack(&self) -> RXNACK_R { + RXNACK_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 4:5 - Bus State"] + #[inline(always)] + pub fn busstate(&self) -> BUSSTATE_R { + BUSSTATE_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bit 6 - SCL Low Timeout"] + #[inline(always)] + pub fn lowtout(&self) -> LOWTOUT_R { + LOWTOUT_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Clock Hold"] + #[inline(always)] + pub fn clkhold(&self) -> CLKHOLD_R { + CLKHOLD_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Master SCL Low Extend Timeout"] + #[inline(always)] + pub fn mexttout(&self) -> MEXTTOUT_R { + MEXTTOUT_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttout(&self) -> SEXTTOUT_R { + SEXTTOUT_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Length Error"] + #[inline(always)] + pub fn lenerr(&self) -> LENERR_R { + LENERR_R::new(((self.bits >> 10) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Bus Error"] + #[inline(always)] + pub fn buserr(&mut self) -> BUSERR_W { + BUSERR_W { w: self } + } + #[doc = "Bit 1 - Arbitration Lost"] + #[inline(always)] + pub fn arblost(&mut self) -> ARBLOST_W { + ARBLOST_W { w: self } + } + #[doc = "Bit 2 - Received Not Acknowledge"] + #[inline(always)] + pub fn rxnack(&mut self) -> RXNACK_W { + RXNACK_W { w: self } + } + #[doc = "Bits 4:5 - Bus State"] + #[inline(always)] + pub fn busstate(&mut self) -> BUSSTATE_W { + BUSSTATE_W { w: self } + } + #[doc = "Bit 6 - SCL Low Timeout"] + #[inline(always)] + pub fn lowtout(&mut self) -> LOWTOUT_W { + LOWTOUT_W { w: self } + } + #[doc = "Bit 7 - Clock Hold"] + #[inline(always)] + pub fn clkhold(&mut self) -> CLKHOLD_W { + CLKHOLD_W { w: self } + } + #[doc = "Bit 8 - Master SCL Low Extend Timeout"] + #[inline(always)] + pub fn mexttout(&mut self) -> MEXTTOUT_W { + MEXTTOUT_W { w: self } + } + #[doc = "Bit 9 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttout(&mut self) -> SEXTTOUT_W { + SEXTTOUT_W { w: self } + } + #[doc = "Bit 10 - Length Error"] + #[inline(always)] + pub fn lenerr(&mut self) -> LENERR_W { + LENERR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/sercom0/i2cm/syncbusy.rs b/pac/atsamc20g/src/sercom0/i2cm/syncbusy.rs new file mode 100644 index 000000000000..87dd418d1cd3 --- /dev/null +++ b/pac/atsamc20g/src/sercom0/i2cm/syncbusy.rs @@ -0,0 +1,93 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - SERCOM Enable Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYSOP` reader - System Operation Synchronization Busy"] +pub struct SYSOP_R(crate::FieldReader); +impl SYSOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYSOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYSOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM Enable Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - System Operation Synchronization Busy"] + #[inline(always)] + pub fn sysop(&self) -> SYSOP_R { + SYSOP_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +#[doc = "I2CM Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/sercom0/i2cs.rs b/pac/atsamc20g/src/sercom0/i2cs.rs new file mode 100644 index 000000000000..baf9513c6cc1 --- /dev/null +++ b/pac/atsamc20g/src/sercom0/i2cs.rs @@ -0,0 +1,36 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "I2CS Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "I2CS Control B"] +pub mod ctrlb; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "I2CS Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "I2CS Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "I2CS Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "I2CS Status"] +pub mod status; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "I2CS Synchronization Busy"] +pub mod syncbusy; +#[doc = "ADDR register accessor: an alias for `Reg`"] +pub type ADDR = crate::Reg; +#[doc = "I2CS Address"] +pub mod addr; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "I2CS Data"] +pub mod data; diff --git a/pac/atsamc20g/src/sercom0/i2cs/addr.rs b/pac/atsamc20g/src/sercom0/i2cs/addr.rs new file mode 100644 index 000000000000..c1b69ee22891 --- /dev/null +++ b/pac/atsamc20g/src/sercom0/i2cs/addr.rs @@ -0,0 +1,234 @@ +#[doc = "Register `ADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `GENCEN` reader - General Call Address Enable"] +pub struct GENCEN_R(crate::FieldReader); +impl GENCEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENCEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENCEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENCEN` writer - General Call Address Enable"] +pub struct GENCEN_W<'a> { + w: &'a mut W, +} +impl<'a> GENCEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ADDR` reader - Address Value"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - Address Value"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03ff << 1)) | ((value as u32 & 0x03ff) << 1); + self.w + } +} +#[doc = "Field `TENBITEN` reader - Ten Bit Addressing Enable"] +pub struct TENBITEN_R(crate::FieldReader); +impl TENBITEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TENBITEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TENBITEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TENBITEN` writer - Ten Bit Addressing Enable"] +pub struct TENBITEN_W<'a> { + w: &'a mut W, +} +impl<'a> TENBITEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `ADDRMASK` reader - Address Mask"] +pub struct ADDRMASK_R(crate::FieldReader); +impl ADDRMASK_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + ADDRMASK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDRMASK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDRMASK` writer - Address Mask"] +pub struct ADDRMASK_W<'a> { + w: &'a mut W, +} +impl<'a> ADDRMASK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03ff << 17)) | ((value as u32 & 0x03ff) << 17); + self.w + } +} +impl R { + #[doc = "Bit 0 - General Call Address Enable"] + #[inline(always)] + pub fn gencen(&self) -> GENCEN_R { + GENCEN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bits 1:10 - Address Value"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new(((self.bits >> 1) & 0x03ff) as u16) + } + #[doc = "Bit 15 - Ten Bit Addressing Enable"] + #[inline(always)] + pub fn tenbiten(&self) -> TENBITEN_R { + TENBITEN_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 17:26 - Address Mask"] + #[inline(always)] + pub fn addrmask(&self) -> ADDRMASK_R { + ADDRMASK_R::new(((self.bits >> 17) & 0x03ff) as u16) + } +} +impl W { + #[doc = "Bit 0 - General Call Address Enable"] + #[inline(always)] + pub fn gencen(&mut self) -> GENCEN_W { + GENCEN_W { w: self } + } + #[doc = "Bits 1:10 - Address Value"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Bit 15 - Ten Bit Addressing Enable"] + #[inline(always)] + pub fn tenbiten(&mut self) -> TENBITEN_W { + TENBITEN_W { w: self } + } + #[doc = "Bits 17:26 - Address Mask"] + #[inline(always)] + pub fn addrmask(&mut self) -> ADDRMASK_W { + ADDRMASK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [addr](index.html) module"] +pub struct ADDR_SPEC; +impl crate::RegisterSpec for ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [addr::R](R) reader structure"] +impl crate::Readable for ADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [addr::W](W) writer structure"] +impl crate::Writable for ADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ADDR to value 0"] +impl crate::Resettable for ADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/sercom0/i2cs/ctrla.rs b/pac/atsamc20g/src/sercom0/i2cs/ctrla.rs new file mode 100644 index 000000000000..ec93812b004f --- /dev/null +++ b/pac/atsamc20g/src/sercom0/i2cs/ctrla.rs @@ -0,0 +1,744 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: USART with external clock"] + USART_EXT_CLK = 0, + #[doc = "1: USART with internal clock"] + USART_INT_CLK = 1, + #[doc = "2: SPI in slave operation"] + SPI_SLAVE = 2, + #[doc = "3: SPI in master operation"] + SPI_MASTER = 3, + #[doc = "4: I2C slave operation"] + I2C_SLAVE = 4, + #[doc = "5: I2C master operation"] + I2C_MASTER = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::USART_EXT_CLK), + 1 => Some(MODE_A::USART_INT_CLK), + 2 => Some(MODE_A::SPI_SLAVE), + 3 => Some(MODE_A::SPI_MASTER), + 4 => Some(MODE_A::I2C_SLAVE), + 5 => Some(MODE_A::I2C_MASTER), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_EXT_CLK`"] + #[inline(always)] + pub fn is_usart_ext_clk(&self) -> bool { + **self == MODE_A::USART_EXT_CLK + } + #[doc = "Checks if the value of the field is `USART_INT_CLK`"] + #[inline(always)] + pub fn is_usart_int_clk(&self) -> bool { + **self == MODE_A::USART_INT_CLK + } + #[doc = "Checks if the value of the field is `SPI_SLAVE`"] + #[inline(always)] + pub fn is_spi_slave(&self) -> bool { + **self == MODE_A::SPI_SLAVE + } + #[doc = "Checks if the value of the field is `SPI_MASTER`"] + #[inline(always)] + pub fn is_spi_master(&self) -> bool { + **self == MODE_A::SPI_MASTER + } + #[doc = "Checks if the value of the field is `I2C_SLAVE`"] + #[inline(always)] + pub fn is_i2c_slave(&self) -> bool { + **self == MODE_A::I2C_SLAVE + } + #[doc = "Checks if the value of the field is `I2C_MASTER`"] + #[inline(always)] + pub fn is_i2c_master(&self) -> bool { + **self == MODE_A::I2C_MASTER + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART with external clock"] + #[inline(always)] + pub fn usart_ext_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_EXT_CLK) + } + #[doc = "USART with internal clock"] + #[inline(always)] + pub fn usart_int_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_INT_CLK) + } + #[doc = "SPI in slave operation"] + #[inline(always)] + pub fn spi_slave(self) -> &'a mut W { + self.variant(MODE_A::SPI_SLAVE) + } + #[doc = "SPI in master operation"] + #[inline(always)] + pub fn spi_master(self) -> &'a mut W { + self.variant(MODE_A::SPI_MASTER) + } + #[doc = "I2C slave operation"] + #[inline(always)] + pub fn i2c_slave(self) -> &'a mut W { + self.variant(MODE_A::I2C_SLAVE) + } + #[doc = "I2C master operation"] + #[inline(always)] + pub fn i2c_master(self) -> &'a mut W { + self.variant(MODE_A::I2C_MASTER) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 2)) | ((value as u32 & 0x07) << 2); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `PINOUT` reader - Pin Usage"] +pub struct PINOUT_R(crate::FieldReader); +impl PINOUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PINOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PINOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PINOUT` writer - Pin Usage"] +pub struct PINOUT_W<'a> { + w: &'a mut W, +} +impl<'a> PINOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "SDA Hold Time\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SDAHOLD_A { + #[doc = "0: Disabled"] + DISABLE = 0, + #[doc = "1: 50-100ns hold time"] + _75NS = 1, + #[doc = "2: 300-600ns hold time"] + _450NS = 2, + #[doc = "3: 400-800ns hold time"] + _600NS = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SDAHOLD_A) -> Self { + variant as _ + } +} +#[doc = "Field `SDAHOLD` reader - SDA Hold Time"] +pub struct SDAHOLD_R(crate::FieldReader); +impl SDAHOLD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SDAHOLD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SDAHOLD_A { + match self.bits { + 0 => SDAHOLD_A::DISABLE, + 1 => SDAHOLD_A::_75NS, + 2 => SDAHOLD_A::_450NS, + 3 => SDAHOLD_A::_600NS, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == SDAHOLD_A::DISABLE + } + #[doc = "Checks if the value of the field is `_75NS`"] + #[inline(always)] + pub fn is_75ns(&self) -> bool { + **self == SDAHOLD_A::_75NS + } + #[doc = "Checks if the value of the field is `_450NS`"] + #[inline(always)] + pub fn is_450ns(&self) -> bool { + **self == SDAHOLD_A::_450NS + } + #[doc = "Checks if the value of the field is `_600NS`"] + #[inline(always)] + pub fn is_600ns(&self) -> bool { + **self == SDAHOLD_A::_600NS + } +} +impl core::ops::Deref for SDAHOLD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SDAHOLD` writer - SDA Hold Time"] +pub struct SDAHOLD_W<'a> { + w: &'a mut W, +} +impl<'a> SDAHOLD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SDAHOLD_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(SDAHOLD_A::DISABLE) + } + #[doc = "50-100ns hold time"] + #[inline(always)] + pub fn _75ns(self) -> &'a mut W { + self.variant(SDAHOLD_A::_75NS) + } + #[doc = "300-600ns hold time"] + #[inline(always)] + pub fn _450ns(self) -> &'a mut W { + self.variant(SDAHOLD_A::_450NS) + } + #[doc = "400-800ns hold time"] + #[inline(always)] + pub fn _600ns(self) -> &'a mut W { + self.variant(SDAHOLD_A::_600NS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 20)) | ((value as u32 & 0x03) << 20); + self.w + } +} +#[doc = "Field `SEXTTOEN` reader - Slave SCL Low Extend Timeout"] +pub struct SEXTTOEN_R(crate::FieldReader); +impl SEXTTOEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SEXTTOEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEXTTOEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEXTTOEN` writer - Slave SCL Low Extend Timeout"] +pub struct SEXTTOEN_W<'a> { + w: &'a mut W, +} +impl<'a> SEXTTOEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Transfer Speed\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SPEED_A { + #[doc = "0: Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz"] + STANDARD_AND_FAST_MODE = 0, + #[doc = "1: Fast-mode Plus Upto 1MHz"] + FASTPLUS_MODE = 1, + #[doc = "2: High-speed mode Upto 3.4MHz"] + HIGH_SPEED_MODE = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SPEED_A) -> Self { + variant as _ + } +} +#[doc = "Field `SPEED` reader - Transfer Speed"] +pub struct SPEED_R(crate::FieldReader); +impl SPEED_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SPEED_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SPEED_A::STANDARD_AND_FAST_MODE), + 1 => Some(SPEED_A::FASTPLUS_MODE), + 2 => Some(SPEED_A::HIGH_SPEED_MODE), + _ => None, + } + } + #[doc = "Checks if the value of the field is `STANDARD_AND_FAST_MODE`"] + #[inline(always)] + pub fn is_standard_and_fast_mode(&self) -> bool { + **self == SPEED_A::STANDARD_AND_FAST_MODE + } + #[doc = "Checks if the value of the field is `FASTPLUS_MODE`"] + #[inline(always)] + pub fn is_fastplus_mode(&self) -> bool { + **self == SPEED_A::FASTPLUS_MODE + } + #[doc = "Checks if the value of the field is `HIGH_SPEED_MODE`"] + #[inline(always)] + pub fn is_high_speed_mode(&self) -> bool { + **self == SPEED_A::HIGH_SPEED_MODE + } +} +impl core::ops::Deref for SPEED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SPEED` writer - Transfer Speed"] +pub struct SPEED_W<'a> { + w: &'a mut W, +} +impl<'a> SPEED_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SPEED_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz"] + #[inline(always)] + pub fn standard_and_fast_mode(self) -> &'a mut W { + self.variant(SPEED_A::STANDARD_AND_FAST_MODE) + } + #[doc = "Fast-mode Plus Upto 1MHz"] + #[inline(always)] + pub fn fastplus_mode(self) -> &'a mut W { + self.variant(SPEED_A::FASTPLUS_MODE) + } + #[doc = "High-speed mode Upto 3.4MHz"] + #[inline(always)] + pub fn high_speed_mode(self) -> &'a mut W { + self.variant(SPEED_A::HIGH_SPEED_MODE) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 24)) | ((value as u32 & 0x03) << 24); + self.w + } +} +#[doc = "Field `SCLSM` reader - SCL Clock Stretch Mode"] +pub struct SCLSM_R(crate::FieldReader); +impl SCLSM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SCLSM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SCLSM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SCLSM` writer - SCL Clock Stretch Mode"] +pub struct SCLSM_W<'a> { + w: &'a mut W, +} +impl<'a> SCLSM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +#[doc = "Field `LOWTOUTEN` reader - SCL Low Timeout Enable"] +pub struct LOWTOUTEN_R(crate::FieldReader); +impl LOWTOUTEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LOWTOUTEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOWTOUTEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LOWTOUTEN` writer - SCL Low Timeout Enable"] +pub struct LOWTOUTEN_W<'a> { + w: &'a mut W, +} +impl<'a> LOWTOUTEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x07) as u8) + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 16 - Pin Usage"] + #[inline(always)] + pub fn pinout(&self) -> PINOUT_R { + PINOUT_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bits 20:21 - SDA Hold Time"] + #[inline(always)] + pub fn sdahold(&self) -> SDAHOLD_R { + SDAHOLD_R::new(((self.bits >> 20) & 0x03) as u8) + } + #[doc = "Bit 23 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttoen(&self) -> SEXTTOEN_R { + SEXTTOEN_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bits 24:25 - Transfer Speed"] + #[inline(always)] + pub fn speed(&self) -> SPEED_R { + SPEED_R::new(((self.bits >> 24) & 0x03) as u8) + } + #[doc = "Bit 27 - SCL Clock Stretch Mode"] + #[inline(always)] + pub fn sclsm(&self) -> SCLSM_R { + SCLSM_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 30 - SCL Low Timeout Enable"] + #[inline(always)] + pub fn lowtouten(&self) -> LOWTOUTEN_R { + LOWTOUTEN_R::new(((self.bits >> 30) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 16 - Pin Usage"] + #[inline(always)] + pub fn pinout(&mut self) -> PINOUT_W { + PINOUT_W { w: self } + } + #[doc = "Bits 20:21 - SDA Hold Time"] + #[inline(always)] + pub fn sdahold(&mut self) -> SDAHOLD_W { + SDAHOLD_W { w: self } + } + #[doc = "Bit 23 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttoen(&mut self) -> SEXTTOEN_W { + SEXTTOEN_W { w: self } + } + #[doc = "Bits 24:25 - Transfer Speed"] + #[inline(always)] + pub fn speed(&mut self) -> SPEED_W { + SPEED_W { w: self } + } + #[doc = "Bit 27 - SCL Clock Stretch Mode"] + #[inline(always)] + pub fn sclsm(&mut self) -> SCLSM_W { + SCLSM_W { w: self } + } + #[doc = "Bit 30 - SCL Low Timeout Enable"] + #[inline(always)] + pub fn lowtouten(&mut self) -> LOWTOUTEN_W { + LOWTOUTEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/sercom0/i2cs/ctrlb.rs b/pac/atsamc20g/src/sercom0/i2cs/ctrlb.rs new file mode 100644 index 000000000000..b20f48581ed5 --- /dev/null +++ b/pac/atsamc20g/src/sercom0/i2cs/ctrlb.rs @@ -0,0 +1,328 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SMEN` reader - Smart Mode Enable"] +pub struct SMEN_R(crate::FieldReader); +impl SMEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SMEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SMEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SMEN` writer - Smart Mode Enable"] +pub struct SMEN_W<'a> { + w: &'a mut W, +} +impl<'a> SMEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `GCMD` reader - PMBus Group Command"] +pub struct GCMD_R(crate::FieldReader); +impl GCMD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GCMD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GCMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GCMD` writer - PMBus Group Command"] +pub struct GCMD_W<'a> { + w: &'a mut W, +} +impl<'a> GCMD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `AACKEN` reader - Automatic Address Acknowledge"] +pub struct AACKEN_R(crate::FieldReader); +impl AACKEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AACKEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AACKEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AACKEN` writer - Automatic Address Acknowledge"] +pub struct AACKEN_W<'a> { + w: &'a mut W, +} +impl<'a> AACKEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `AMODE` reader - Address Mode"] +pub struct AMODE_R(crate::FieldReader); +impl AMODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + AMODE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AMODE` writer - Address Mode"] +pub struct AMODE_W<'a> { + w: &'a mut W, +} +impl<'a> AMODE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 14)) | ((value as u32 & 0x03) << 14); + self.w + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Field `ACKACT` reader - Acknowledge Action"] +pub struct ACKACT_R(crate::FieldReader); +impl ACKACT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ACKACT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ACKACT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ACKACT` writer - Acknowledge Action"] +pub struct ACKACT_W<'a> { + w: &'a mut W, +} +impl<'a> ACKACT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +impl R { + #[doc = "Bit 8 - Smart Mode Enable"] + #[inline(always)] + pub fn smen(&self) -> SMEN_R { + SMEN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - PMBus Group Command"] + #[inline(always)] + pub fn gcmd(&self) -> GCMD_R { + GCMD_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Automatic Address Acknowledge"] + #[inline(always)] + pub fn aacken(&self) -> AACKEN_R { + AACKEN_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bits 14:15 - Address Mode"] + #[inline(always)] + pub fn amode(&self) -> AMODE_R { + AMODE_R::new(((self.bits >> 14) & 0x03) as u8) + } + #[doc = "Bits 16:17 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bit 18 - Acknowledge Action"] + #[inline(always)] + pub fn ackact(&self) -> ACKACT_R { + ACKACT_R::new(((self.bits >> 18) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 8 - Smart Mode Enable"] + #[inline(always)] + pub fn smen(&mut self) -> SMEN_W { + SMEN_W { w: self } + } + #[doc = "Bit 9 - PMBus Group Command"] + #[inline(always)] + pub fn gcmd(&mut self) -> GCMD_W { + GCMD_W { w: self } + } + #[doc = "Bit 10 - Automatic Address Acknowledge"] + #[inline(always)] + pub fn aacken(&mut self) -> AACKEN_W { + AACKEN_W { w: self } + } + #[doc = "Bits 14:15 - Address Mode"] + #[inline(always)] + pub fn amode(&mut self) -> AMODE_W { + AMODE_W { w: self } + } + #[doc = "Bits 16:17 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Bit 18 - Acknowledge Action"] + #[inline(always)] + pub fn ackact(&mut self) -> ACKACT_W { + ACKACT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/sercom0/i2cs/data.rs b/pac/atsamc20g/src/sercom0/i2cs/data.rs new file mode 100644 index 000000000000..d8bfe070431a --- /dev/null +++ b/pac/atsamc20g/src/sercom0/i2cs/data.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data Value"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data Value"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Data Value"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Value"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/sercom0/i2cs/intenclr.rs b/pac/atsamc20g/src/sercom0/i2cs/intenclr.rs new file mode 100644 index 000000000000..49f5191c8d63 --- /dev/null +++ b/pac/atsamc20g/src/sercom0/i2cs/intenclr.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PREC` reader - Stop Received Interrupt Disable"] +pub struct PREC_R(crate::FieldReader); +impl PREC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PREC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PREC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PREC` writer - Stop Received Interrupt Disable"] +pub struct PREC_W<'a> { + w: &'a mut W, +} +impl<'a> PREC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `AMATCH` reader - Address Match Interrupt Disable"] +pub struct AMATCH_R(crate::FieldReader); +impl AMATCH_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AMATCH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AMATCH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AMATCH` writer - Address Match Interrupt Disable"] +pub struct AMATCH_W<'a> { + w: &'a mut W, +} +impl<'a> AMATCH_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `DRDY` reader - Data Interrupt Disable"] +pub struct DRDY_R(crate::FieldReader); +impl DRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRDY` writer - Data Interrupt Disable"] +pub struct DRDY_W<'a> { + w: &'a mut W, +} +impl<'a> DRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Disable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Disable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Stop Received Interrupt Disable"] + #[inline(always)] + pub fn prec(&self) -> PREC_R { + PREC_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Address Match Interrupt Disable"] + #[inline(always)] + pub fn amatch(&self) -> AMATCH_R { + AMATCH_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Data Interrupt Disable"] + #[inline(always)] + pub fn drdy(&self) -> DRDY_R { + DRDY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Stop Received Interrupt Disable"] + #[inline(always)] + pub fn prec(&mut self) -> PREC_W { + PREC_W { w: self } + } + #[doc = "Bit 1 - Address Match Interrupt Disable"] + #[inline(always)] + pub fn amatch(&mut self) -> AMATCH_W { + AMATCH_W { w: self } + } + #[doc = "Bit 2 - Data Interrupt Disable"] + #[inline(always)] + pub fn drdy(&mut self) -> DRDY_W { + DRDY_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/sercom0/i2cs/intenset.rs b/pac/atsamc20g/src/sercom0/i2cs/intenset.rs new file mode 100644 index 000000000000..97ea784d7476 --- /dev/null +++ b/pac/atsamc20g/src/sercom0/i2cs/intenset.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PREC` reader - Stop Received Interrupt Enable"] +pub struct PREC_R(crate::FieldReader); +impl PREC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PREC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PREC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PREC` writer - Stop Received Interrupt Enable"] +pub struct PREC_W<'a> { + w: &'a mut W, +} +impl<'a> PREC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `AMATCH` reader - Address Match Interrupt Enable"] +pub struct AMATCH_R(crate::FieldReader); +impl AMATCH_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AMATCH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AMATCH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AMATCH` writer - Address Match Interrupt Enable"] +pub struct AMATCH_W<'a> { + w: &'a mut W, +} +impl<'a> AMATCH_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `DRDY` reader - Data Interrupt Enable"] +pub struct DRDY_R(crate::FieldReader); +impl DRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRDY` writer - Data Interrupt Enable"] +pub struct DRDY_W<'a> { + w: &'a mut W, +} +impl<'a> DRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Stop Received Interrupt Enable"] + #[inline(always)] + pub fn prec(&self) -> PREC_R { + PREC_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Address Match Interrupt Enable"] + #[inline(always)] + pub fn amatch(&self) -> AMATCH_R { + AMATCH_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Data Interrupt Enable"] + #[inline(always)] + pub fn drdy(&self) -> DRDY_R { + DRDY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Stop Received Interrupt Enable"] + #[inline(always)] + pub fn prec(&mut self) -> PREC_W { + PREC_W { w: self } + } + #[doc = "Bit 1 - Address Match Interrupt Enable"] + #[inline(always)] + pub fn amatch(&mut self) -> AMATCH_W { + AMATCH_W { w: self } + } + #[doc = "Bit 2 - Data Interrupt Enable"] + #[inline(always)] + pub fn drdy(&mut self) -> DRDY_W { + DRDY_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/sercom0/i2cs/intflag.rs b/pac/atsamc20g/src/sercom0/i2cs/intflag.rs new file mode 100644 index 000000000000..2eee333e4e59 --- /dev/null +++ b/pac/atsamc20g/src/sercom0/i2cs/intflag.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PREC` reader - Stop Received Interrupt"] +pub struct PREC_R(crate::FieldReader); +impl PREC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PREC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PREC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PREC` writer - Stop Received Interrupt"] +pub struct PREC_W<'a> { + w: &'a mut W, +} +impl<'a> PREC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `AMATCH` reader - Address Match Interrupt"] +pub struct AMATCH_R(crate::FieldReader); +impl AMATCH_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AMATCH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AMATCH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AMATCH` writer - Address Match Interrupt"] +pub struct AMATCH_W<'a> { + w: &'a mut W, +} +impl<'a> AMATCH_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `DRDY` reader - Data Interrupt"] +pub struct DRDY_R(crate::FieldReader); +impl DRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRDY` writer - Data Interrupt"] +pub struct DRDY_W<'a> { + w: &'a mut W, +} +impl<'a> DRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Stop Received Interrupt"] + #[inline(always)] + pub fn prec(&self) -> PREC_R { + PREC_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Address Match Interrupt"] + #[inline(always)] + pub fn amatch(&self) -> AMATCH_R { + AMATCH_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Data Interrupt"] + #[inline(always)] + pub fn drdy(&self) -> DRDY_R { + DRDY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Stop Received Interrupt"] + #[inline(always)] + pub fn prec(&mut self) -> PREC_W { + PREC_W { w: self } + } + #[doc = "Bit 1 - Address Match Interrupt"] + #[inline(always)] + pub fn amatch(&mut self) -> AMATCH_W { + AMATCH_W { w: self } + } + #[doc = "Bit 2 - Data Interrupt"] + #[inline(always)] + pub fn drdy(&mut self) -> DRDY_W { + DRDY_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/sercom0/i2cs/status.rs b/pac/atsamc20g/src/sercom0/i2cs/status.rs new file mode 100644 index 000000000000..b3f6d218fa66 --- /dev/null +++ b/pac/atsamc20g/src/sercom0/i2cs/status.rs @@ -0,0 +1,489 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BUSERR` reader - Bus Error"] +pub struct BUSERR_R(crate::FieldReader); +impl BUSERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSERR` writer - Bus Error"] +pub struct BUSERR_W<'a> { + w: &'a mut W, +} +impl<'a> BUSERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `COLL` reader - Transmit Collision"] +pub struct COLL_R(crate::FieldReader); +impl COLL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COLL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COLL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COLL` writer - Transmit Collision"] +pub struct COLL_W<'a> { + w: &'a mut W, +} +impl<'a> COLL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXNACK` reader - Received Not Acknowledge"] +pub struct RXNACK_R(crate::FieldReader); +impl RXNACK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXNACK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXNACK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXNACK` writer - Received Not Acknowledge"] +pub struct RXNACK_W<'a> { + w: &'a mut W, +} +impl<'a> RXNACK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `DIR` reader - Read/Write Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Read/Write Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `SR` reader - Repeated Start"] +pub struct SR_R(crate::FieldReader); +impl SR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SR` writer - Repeated Start"] +pub struct SR_W<'a> { + w: &'a mut W, +} +impl<'a> SR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `LOWTOUT` reader - SCL Low Timeout"] +pub struct LOWTOUT_R(crate::FieldReader); +impl LOWTOUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LOWTOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOWTOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LOWTOUT` writer - SCL Low Timeout"] +pub struct LOWTOUT_W<'a> { + w: &'a mut W, +} +impl<'a> LOWTOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `CLKHOLD` reader - Clock Hold"] +pub struct CLKHOLD_R(crate::FieldReader); +impl CLKHOLD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKHOLD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKHOLD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKHOLD` writer - Clock Hold"] +pub struct CLKHOLD_W<'a> { + w: &'a mut W, +} +impl<'a> CLKHOLD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `SEXTTOUT` reader - Slave SCL Low Extend Timeout"] +pub struct SEXTTOUT_R(crate::FieldReader); +impl SEXTTOUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SEXTTOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEXTTOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEXTTOUT` writer - Slave SCL Low Extend Timeout"] +pub struct SEXTTOUT_W<'a> { + w: &'a mut W, +} +impl<'a> SEXTTOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `HS` reader - High Speed"] +pub struct HS_R(crate::FieldReader); +impl HS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HS` writer - High Speed"] +pub struct HS_W<'a> { + w: &'a mut W, +} +impl<'a> HS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u16 & 0x01) << 10); + self.w + } +} +impl R { + #[doc = "Bit 0 - Bus Error"] + #[inline(always)] + pub fn buserr(&self) -> BUSERR_R { + BUSERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Collision"] + #[inline(always)] + pub fn coll(&self) -> COLL_R { + COLL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Received Not Acknowledge"] + #[inline(always)] + pub fn rxnack(&self) -> RXNACK_R { + RXNACK_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Read/Write Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Repeated Start"] + #[inline(always)] + pub fn sr(&self) -> SR_R { + SR_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 6 - SCL Low Timeout"] + #[inline(always)] + pub fn lowtout(&self) -> LOWTOUT_R { + LOWTOUT_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Clock Hold"] + #[inline(always)] + pub fn clkhold(&self) -> CLKHOLD_R { + CLKHOLD_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 9 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttout(&self) -> SEXTTOUT_R { + SEXTTOUT_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - High Speed"] + #[inline(always)] + pub fn hs(&self) -> HS_R { + HS_R::new(((self.bits >> 10) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Bus Error"] + #[inline(always)] + pub fn buserr(&mut self) -> BUSERR_W { + BUSERR_W { w: self } + } + #[doc = "Bit 1 - Transmit Collision"] + #[inline(always)] + pub fn coll(&mut self) -> COLL_W { + COLL_W { w: self } + } + #[doc = "Bit 2 - Received Not Acknowledge"] + #[inline(always)] + pub fn rxnack(&mut self) -> RXNACK_W { + RXNACK_W { w: self } + } + #[doc = "Bit 3 - Read/Write Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 4 - Repeated Start"] + #[inline(always)] + pub fn sr(&mut self) -> SR_W { + SR_W { w: self } + } + #[doc = "Bit 6 - SCL Low Timeout"] + #[inline(always)] + pub fn lowtout(&mut self) -> LOWTOUT_W { + LOWTOUT_W { w: self } + } + #[doc = "Bit 7 - Clock Hold"] + #[inline(always)] + pub fn clkhold(&mut self) -> CLKHOLD_W { + CLKHOLD_W { w: self } + } + #[doc = "Bit 9 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttout(&mut self) -> SEXTTOUT_W { + SEXTTOUT_W { w: self } + } + #[doc = "Bit 10 - High Speed"] + #[inline(always)] + pub fn hs(&mut self) -> HS_W { + HS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/sercom0/i2cs/syncbusy.rs b/pac/atsamc20g/src/sercom0/i2cs/syncbusy.rs new file mode 100644 index 000000000000..38e2509d9666 --- /dev/null +++ b/pac/atsamc20g/src/sercom0/i2cs/syncbusy.rs @@ -0,0 +1,73 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - SERCOM Enable Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM Enable Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +#[doc = "I2CS Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/sercom0/spim.rs b/pac/atsamc20g/src/sercom0/spim.rs new file mode 100644 index 000000000000..528e38e1b811 --- /dev/null +++ b/pac/atsamc20g/src/sercom0/spim.rs @@ -0,0 +1,44 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "SPIM Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "SPIM Control B"] +pub mod ctrlb; +#[doc = "BAUD register accessor: an alias for `Reg`"] +pub type BAUD = crate::Reg; +#[doc = "SPIM Baud Rate"] +pub mod baud; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "SPIM Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "SPIM Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "SPIM Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "SPIM Status"] +pub mod status; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "SPIM Synchronization Busy"] +pub mod syncbusy; +#[doc = "ADDR register accessor: an alias for `Reg`"] +pub type ADDR = crate::Reg; +#[doc = "SPIM Address"] +pub mod addr; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "SPIM Data"] +pub mod data; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "SPIM Debug Control"] +pub mod dbgctrl; diff --git a/pac/atsamc20g/src/sercom0/spim/addr.rs b/pac/atsamc20g/src/sercom0/spim/addr.rs new file mode 100644 index 000000000000..7c25cd522ea2 --- /dev/null +++ b/pac/atsamc20g/src/sercom0/spim/addr.rs @@ -0,0 +1,140 @@ +#[doc = "Register `ADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ADDR` reader - Address Value"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - Address Value"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +#[doc = "Field `ADDRMASK` reader - Address Mask"] +pub struct ADDRMASK_R(crate::FieldReader); +impl ADDRMASK_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ADDRMASK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDRMASK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDRMASK` writer - Address Mask"] +pub struct ADDRMASK_W<'a> { + w: &'a mut W, +} +impl<'a> ADDRMASK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Address Value"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 16:23 - Address Mask"] + #[inline(always)] + pub fn addrmask(&self) -> ADDRMASK_R { + ADDRMASK_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Address Value"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Bits 16:23 - Address Mask"] + #[inline(always)] + pub fn addrmask(&mut self) -> ADDRMASK_W { + ADDRMASK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [addr](index.html) module"] +pub struct ADDR_SPEC; +impl crate::RegisterSpec for ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [addr::R](R) reader structure"] +impl crate::Readable for ADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [addr::W](W) writer structure"] +impl crate::Writable for ADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ADDR to value 0"] +impl crate::Resettable for ADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/sercom0/spim/baud.rs b/pac/atsamc20g/src/sercom0/spim/baud.rs new file mode 100644 index 000000000000..6bec9ca74355 --- /dev/null +++ b/pac/atsamc20g/src/sercom0/spim/baud.rs @@ -0,0 +1,103 @@ +#[doc = "Register `BAUD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud](index.html) module"] +pub struct BAUD_SPEC; +impl crate::RegisterSpec for BAUD_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [baud::R](R) reader structure"] +impl crate::Readable for BAUD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud::W](W) writer structure"] +impl crate::Writable for BAUD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD to value 0"] +impl crate::Resettable for BAUD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/sercom0/spim/ctrla.rs b/pac/atsamc20g/src/sercom0/spim/ctrla.rs new file mode 100644 index 000000000000..44028f8cbdd7 --- /dev/null +++ b/pac/atsamc20g/src/sercom0/spim/ctrla.rs @@ -0,0 +1,992 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: USART with external clock"] + USART_EXT_CLK = 0, + #[doc = "1: USART with internal clock"] + USART_INT_CLK = 1, + #[doc = "2: SPI in slave operation"] + SPI_SLAVE = 2, + #[doc = "3: SPI in master operation"] + SPI_MASTER = 3, + #[doc = "4: I2C slave operation"] + I2C_SLAVE = 4, + #[doc = "5: I2C master operation"] + I2C_MASTER = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::USART_EXT_CLK), + 1 => Some(MODE_A::USART_INT_CLK), + 2 => Some(MODE_A::SPI_SLAVE), + 3 => Some(MODE_A::SPI_MASTER), + 4 => Some(MODE_A::I2C_SLAVE), + 5 => Some(MODE_A::I2C_MASTER), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_EXT_CLK`"] + #[inline(always)] + pub fn is_usart_ext_clk(&self) -> bool { + **self == MODE_A::USART_EXT_CLK + } + #[doc = "Checks if the value of the field is `USART_INT_CLK`"] + #[inline(always)] + pub fn is_usart_int_clk(&self) -> bool { + **self == MODE_A::USART_INT_CLK + } + #[doc = "Checks if the value of the field is `SPI_SLAVE`"] + #[inline(always)] + pub fn is_spi_slave(&self) -> bool { + **self == MODE_A::SPI_SLAVE + } + #[doc = "Checks if the value of the field is `SPI_MASTER`"] + #[inline(always)] + pub fn is_spi_master(&self) -> bool { + **self == MODE_A::SPI_MASTER + } + #[doc = "Checks if the value of the field is `I2C_SLAVE`"] + #[inline(always)] + pub fn is_i2c_slave(&self) -> bool { + **self == MODE_A::I2C_SLAVE + } + #[doc = "Checks if the value of the field is `I2C_MASTER`"] + #[inline(always)] + pub fn is_i2c_master(&self) -> bool { + **self == MODE_A::I2C_MASTER + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART with external clock"] + #[inline(always)] + pub fn usart_ext_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_EXT_CLK) + } + #[doc = "USART with internal clock"] + #[inline(always)] + pub fn usart_int_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_INT_CLK) + } + #[doc = "SPI in slave operation"] + #[inline(always)] + pub fn spi_slave(self) -> &'a mut W { + self.variant(MODE_A::SPI_SLAVE) + } + #[doc = "SPI in master operation"] + #[inline(always)] + pub fn spi_master(self) -> &'a mut W { + self.variant(MODE_A::SPI_MASTER) + } + #[doc = "I2C slave operation"] + #[inline(always)] + pub fn i2c_slave(self) -> &'a mut W { + self.variant(MODE_A::I2C_SLAVE) + } + #[doc = "I2C master operation"] + #[inline(always)] + pub fn i2c_master(self) -> &'a mut W { + self.variant(MODE_A::I2C_MASTER) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 2)) | ((value as u32 & 0x07) << 2); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `IBON` reader - Immediate Buffer Overflow Notification"] +pub struct IBON_R(crate::FieldReader); +impl IBON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IBON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IBON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IBON` writer - Immediate Buffer Overflow Notification"] +pub struct IBON_W<'a> { + w: &'a mut W, +} +impl<'a> IBON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Data Out Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DOPO_A { + #[doc = "0: DO on PAD\\[0\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + PAD0 = 0, + #[doc = "1: DO on PAD\\[2\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + PAD1 = 1, + #[doc = "2: DO on PAD\\[3\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + PAD2 = 2, + #[doc = "3: DO on PAD\\[0\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + PAD3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DOPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `DOPO` reader - Data Out Pinout"] +pub struct DOPO_R(crate::FieldReader); +impl DOPO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DOPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DOPO_A { + match self.bits { + 0 => DOPO_A::PAD0, + 1 => DOPO_A::PAD1, + 2 => DOPO_A::PAD2, + 3 => DOPO_A::PAD3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == DOPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD1`"] + #[inline(always)] + pub fn is_pad1(&self) -> bool { + **self == DOPO_A::PAD1 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == DOPO_A::PAD2 + } + #[doc = "Checks if the value of the field is `PAD3`"] + #[inline(always)] + pub fn is_pad3(&self) -> bool { + **self == DOPO_A::PAD3 + } +} +impl core::ops::Deref for DOPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DOPO` writer - Data Out Pinout"] +pub struct DOPO_W<'a> { + w: &'a mut W, +} +impl<'a> DOPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DOPO_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "DO on PAD\\[0\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(DOPO_A::PAD0) + } + #[doc = "DO on PAD\\[2\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + #[inline(always)] + pub fn pad1(self) -> &'a mut W { + self.variant(DOPO_A::PAD1) + } + #[doc = "DO on PAD\\[3\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(DOPO_A::PAD2) + } + #[doc = "DO on PAD\\[0\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + #[inline(always)] + pub fn pad3(self) -> &'a mut W { + self.variant(DOPO_A::PAD3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Data In Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DIPO_A { + #[doc = "0: SERCOM PAD\\[0\\]"] + PAD0 = 0, + #[doc = "1: SERCOM PAD\\[1\\]"] + PAD1 = 1, + #[doc = "2: SERCOM PAD\\[2\\]"] + PAD2 = 2, + #[doc = "3: SERCOM PAD\\[3\\]"] + PAD3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DIPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `DIPO` reader - Data In Pinout"] +pub struct DIPO_R(crate::FieldReader); +impl DIPO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DIPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DIPO_A { + match self.bits { + 0 => DIPO_A::PAD0, + 1 => DIPO_A::PAD1, + 2 => DIPO_A::PAD2, + 3 => DIPO_A::PAD3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == DIPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD1`"] + #[inline(always)] + pub fn is_pad1(&self) -> bool { + **self == DIPO_A::PAD1 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == DIPO_A::PAD2 + } + #[doc = "Checks if the value of the field is `PAD3`"] + #[inline(always)] + pub fn is_pad3(&self) -> bool { + **self == DIPO_A::PAD3 + } +} +impl core::ops::Deref for DIPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIPO` writer - Data In Pinout"] +pub struct DIPO_W<'a> { + w: &'a mut W, +} +impl<'a> DIPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DIPO_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "SERCOM PAD\\[0\\]"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(DIPO_A::PAD0) + } + #[doc = "SERCOM PAD\\[1\\]"] + #[inline(always)] + pub fn pad1(self) -> &'a mut W { + self.variant(DIPO_A::PAD1) + } + #[doc = "SERCOM PAD\\[2\\]"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(DIPO_A::PAD2) + } + #[doc = "SERCOM PAD\\[3\\]"] + #[inline(always)] + pub fn pad3(self) -> &'a mut W { + self.variant(DIPO_A::PAD3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 20)) | ((value as u32 & 0x03) << 20); + self.w + } +} +#[doc = "Frame Format\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FORM_A { + #[doc = "0: SPI Frame"] + SPI_FRAME = 0, + #[doc = "2: SPI Frame with Addr"] + SPI_FRAME_WITH_ADDR = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FORM_A) -> Self { + variant as _ + } +} +#[doc = "Field `FORM` reader - Frame Format"] +pub struct FORM_R(crate::FieldReader); +impl FORM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FORM_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(FORM_A::SPI_FRAME), + 2 => Some(FORM_A::SPI_FRAME_WITH_ADDR), + _ => None, + } + } + #[doc = "Checks if the value of the field is `SPI_FRAME`"] + #[inline(always)] + pub fn is_spi_frame(&self) -> bool { + **self == FORM_A::SPI_FRAME + } + #[doc = "Checks if the value of the field is `SPI_FRAME_WITH_ADDR`"] + #[inline(always)] + pub fn is_spi_frame_with_addr(&self) -> bool { + **self == FORM_A::SPI_FRAME_WITH_ADDR + } +} +impl core::ops::Deref for FORM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FORM` writer - Frame Format"] +pub struct FORM_W<'a> { + w: &'a mut W, +} +impl<'a> FORM_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FORM_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "SPI Frame"] + #[inline(always)] + pub fn spi_frame(self) -> &'a mut W { + self.variant(FORM_A::SPI_FRAME) + } + #[doc = "SPI Frame with Addr"] + #[inline(always)] + pub fn spi_frame_with_addr(self) -> &'a mut W { + self.variant(FORM_A::SPI_FRAME_WITH_ADDR) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Clock Phase\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CPHA_A { + #[doc = "0: The data is sampled on a leading SCK edge and changed on a trailing SCK edge"] + LEADING_EDGE = 0, + #[doc = "1: The data is sampled on a trailing SCK edge and changed on a leading SCK edge"] + TRAILING_EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CPHA_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CPHA` reader - Clock Phase"] +pub struct CPHA_R(crate::FieldReader); +impl CPHA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPHA_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CPHA_A { + match self.bits { + false => CPHA_A::LEADING_EDGE, + true => CPHA_A::TRAILING_EDGE, + } + } + #[doc = "Checks if the value of the field is `LEADING_EDGE`"] + #[inline(always)] + pub fn is_leading_edge(&self) -> bool { + **self == CPHA_A::LEADING_EDGE + } + #[doc = "Checks if the value of the field is `TRAILING_EDGE`"] + #[inline(always)] + pub fn is_trailing_edge(&self) -> bool { + **self == CPHA_A::TRAILING_EDGE + } +} +impl core::ops::Deref for CPHA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPHA` writer - Clock Phase"] +pub struct CPHA_W<'a> { + w: &'a mut W, +} +impl<'a> CPHA_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CPHA_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "The data is sampled on a leading SCK edge and changed on a trailing SCK edge"] + #[inline(always)] + pub fn leading_edge(self) -> &'a mut W { + self.variant(CPHA_A::LEADING_EDGE) + } + #[doc = "The data is sampled on a trailing SCK edge and changed on a leading SCK edge"] + #[inline(always)] + pub fn trailing_edge(self) -> &'a mut W { + self.variant(CPHA_A::TRAILING_EDGE) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Clock Polarity\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CPOL_A { + #[doc = "0: SCK is low when idle"] + IDLE_LOW = 0, + #[doc = "1: SCK is high when idle"] + IDLE_HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CPOL_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CPOL` reader - Clock Polarity"] +pub struct CPOL_R(crate::FieldReader); +impl CPOL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPOL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CPOL_A { + match self.bits { + false => CPOL_A::IDLE_LOW, + true => CPOL_A::IDLE_HIGH, + } + } + #[doc = "Checks if the value of the field is `IDLE_LOW`"] + #[inline(always)] + pub fn is_idle_low(&self) -> bool { + **self == CPOL_A::IDLE_LOW + } + #[doc = "Checks if the value of the field is `IDLE_HIGH`"] + #[inline(always)] + pub fn is_idle_high(&self) -> bool { + **self == CPOL_A::IDLE_HIGH + } +} +impl core::ops::Deref for CPOL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPOL` writer - Clock Polarity"] +pub struct CPOL_W<'a> { + w: &'a mut W, +} +impl<'a> CPOL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CPOL_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "SCK is low when idle"] + #[inline(always)] + pub fn idle_low(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_LOW) + } + #[doc = "SCK is high when idle"] + #[inline(always)] + pub fn idle_high(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_HIGH) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29); + self.w + } +} +#[doc = "Data Order\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum DORD_A { + #[doc = "0: MSB is transferred first"] + MSB = 0, + #[doc = "1: LSB is transferred first"] + LSB = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DORD_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DORD` reader - Data Order"] +pub struct DORD_R(crate::FieldReader); +impl DORD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DORD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DORD_A { + match self.bits { + false => DORD_A::MSB, + true => DORD_A::LSB, + } + } + #[doc = "Checks if the value of the field is `MSB`"] + #[inline(always)] + pub fn is_msb(&self) -> bool { + **self == DORD_A::MSB + } + #[doc = "Checks if the value of the field is `LSB`"] + #[inline(always)] + pub fn is_lsb(&self) -> bool { + **self == DORD_A::LSB + } +} +impl core::ops::Deref for DORD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DORD` writer - Data Order"] +pub struct DORD_W<'a> { + w: &'a mut W, +} +impl<'a> DORD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DORD_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "MSB is transferred first"] + #[inline(always)] + pub fn msb(self) -> &'a mut W { + self.variant(DORD_A::MSB) + } + #[doc = "LSB is transferred first"] + #[inline(always)] + pub fn lsb(self) -> &'a mut W { + self.variant(DORD_A::LSB) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x07) as u8) + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&self) -> IBON_R { + IBON_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bits 16:17 - Data Out Pinout"] + #[inline(always)] + pub fn dopo(&self) -> DOPO_R { + DOPO_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bits 20:21 - Data In Pinout"] + #[inline(always)] + pub fn dipo(&self) -> DIPO_R { + DIPO_R::new(((self.bits >> 20) & 0x03) as u8) + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&self) -> FORM_R { + FORM_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 28 - Clock Phase"] + #[inline(always)] + pub fn cpha(&self) -> CPHA_R { + CPHA_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&self) -> CPOL_R { + CPOL_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&self) -> DORD_R { + DORD_R::new(((self.bits >> 30) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&mut self) -> IBON_W { + IBON_W { w: self } + } + #[doc = "Bits 16:17 - Data Out Pinout"] + #[inline(always)] + pub fn dopo(&mut self) -> DOPO_W { + DOPO_W { w: self } + } + #[doc = "Bits 20:21 - Data In Pinout"] + #[inline(always)] + pub fn dipo(&mut self) -> DIPO_W { + DIPO_W { w: self } + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&mut self) -> FORM_W { + FORM_W { w: self } + } + #[doc = "Bit 28 - Clock Phase"] + #[inline(always)] + pub fn cpha(&mut self) -> CPHA_W { + CPHA_W { w: self } + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&mut self) -> CPOL_W { + CPOL_W { w: self } + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&mut self) -> DORD_W { + DORD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/sercom0/spim/ctrlb.rs b/pac/atsamc20g/src/sercom0/spim/ctrlb.rs new file mode 100644 index 000000000000..3d94f824ce83 --- /dev/null +++ b/pac/atsamc20g/src/sercom0/spim/ctrlb.rs @@ -0,0 +1,439 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Character Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CHSIZE_A { + #[doc = "0: 8 bits"] + _8_BIT = 0, + #[doc = "1: 9 bits"] + _9_BIT = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CHSIZE_A) -> Self { + variant as _ + } +} +#[doc = "Field `CHSIZE` reader - Character Size"] +pub struct CHSIZE_R(crate::FieldReader); +impl CHSIZE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CHSIZE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CHSIZE_A::_8_BIT), + 1 => Some(CHSIZE_A::_9_BIT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_8_BIT`"] + #[inline(always)] + pub fn is_8_bit(&self) -> bool { + **self == CHSIZE_A::_8_BIT + } + #[doc = "Checks if the value of the field is `_9_BIT`"] + #[inline(always)] + pub fn is_9_bit(&self) -> bool { + **self == CHSIZE_A::_9_BIT + } +} +impl core::ops::Deref for CHSIZE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHSIZE` writer - Character Size"] +pub struct CHSIZE_W<'a> { + w: &'a mut W, +} +impl<'a> CHSIZE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CHSIZE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8 bits"] + #[inline(always)] + pub fn _8_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_8_BIT) + } + #[doc = "9 bits"] + #[inline(always)] + pub fn _9_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_9_BIT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Field `PLOADEN` reader - Data Preload Enable"] +pub struct PLOADEN_R(crate::FieldReader); +impl PLOADEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PLOADEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PLOADEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PLOADEN` writer - Data Preload Enable"] +pub struct PLOADEN_W<'a> { + w: &'a mut W, +} +impl<'a> PLOADEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `SSDE` reader - Slave Select Low Detect Enable"] +pub struct SSDE_R(crate::FieldReader); +impl SSDE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SSDE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSDE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSDE` writer - Slave Select Low Detect Enable"] +pub struct SSDE_W<'a> { + w: &'a mut W, +} +impl<'a> SSDE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `MSSEN` reader - Master Slave Select Enable"] +pub struct MSSEN_R(crate::FieldReader); +impl MSSEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MSSEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MSSEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MSSEN` writer - Master Slave Select Enable"] +pub struct MSSEN_W<'a> { + w: &'a mut W, +} +impl<'a> MSSEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Address Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum AMODE_A { + #[doc = "0: SPI Address mask"] + MASK = 0, + #[doc = "1: Two unique Addressess"] + _2_ADDRESSES = 1, + #[doc = "2: Address Range"] + RANGE = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: AMODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `AMODE` reader - Address Mode"] +pub struct AMODE_R(crate::FieldReader); +impl AMODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + AMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(AMODE_A::MASK), + 1 => Some(AMODE_A::_2_ADDRESSES), + 2 => Some(AMODE_A::RANGE), + _ => None, + } + } + #[doc = "Checks if the value of the field is `MASK`"] + #[inline(always)] + pub fn is_mask(&self) -> bool { + **self == AMODE_A::MASK + } + #[doc = "Checks if the value of the field is `_2_ADDRESSES`"] + #[inline(always)] + pub fn is_2_addresses(&self) -> bool { + **self == AMODE_A::_2_ADDRESSES + } + #[doc = "Checks if the value of the field is `RANGE`"] + #[inline(always)] + pub fn is_range(&self) -> bool { + **self == AMODE_A::RANGE + } +} +impl core::ops::Deref for AMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AMODE` writer - Address Mode"] +pub struct AMODE_W<'a> { + w: &'a mut W, +} +impl<'a> AMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: AMODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "SPI Address mask"] + #[inline(always)] + pub fn mask(self) -> &'a mut W { + self.variant(AMODE_A::MASK) + } + #[doc = "Two unique Addressess"] + #[inline(always)] + pub fn _2_addresses(self) -> &'a mut W { + self.variant(AMODE_A::_2_ADDRESSES) + } + #[doc = "Address Range"] + #[inline(always)] + pub fn range(self) -> &'a mut W { + self.variant(AMODE_A::RANGE) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 14)) | ((value as u32 & 0x03) << 14); + self.w + } +} +#[doc = "Field `RXEN` reader - Receiver Enable"] +pub struct RXEN_R(crate::FieldReader); +impl RXEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXEN` writer - Receiver Enable"] +pub struct RXEN_W<'a> { + w: &'a mut W, +} +impl<'a> RXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&self) -> CHSIZE_R { + CHSIZE_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 6 - Data Preload Enable"] + #[inline(always)] + pub fn ploaden(&self) -> PLOADEN_R { + PLOADEN_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 9 - Slave Select Low Detect Enable"] + #[inline(always)] + pub fn ssde(&self) -> SSDE_R { + SSDE_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 13 - Master Slave Select Enable"] + #[inline(always)] + pub fn mssen(&self) -> MSSEN_R { + MSSEN_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bits 14:15 - Address Mode"] + #[inline(always)] + pub fn amode(&self) -> AMODE_R { + AMODE_R::new(((self.bits >> 14) & 0x03) as u8) + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&self) -> RXEN_R { + RXEN_R::new(((self.bits >> 17) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&mut self) -> CHSIZE_W { + CHSIZE_W { w: self } + } + #[doc = "Bit 6 - Data Preload Enable"] + #[inline(always)] + pub fn ploaden(&mut self) -> PLOADEN_W { + PLOADEN_W { w: self } + } + #[doc = "Bit 9 - Slave Select Low Detect Enable"] + #[inline(always)] + pub fn ssde(&mut self) -> SSDE_W { + SSDE_W { w: self } + } + #[doc = "Bit 13 - Master Slave Select Enable"] + #[inline(always)] + pub fn mssen(&mut self) -> MSSEN_W { + MSSEN_W { w: self } + } + #[doc = "Bits 14:15 - Address Mode"] + #[inline(always)] + pub fn amode(&mut self) -> AMODE_W { + AMODE_W { w: self } + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&mut self) -> RXEN_W { + RXEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/sercom0/spim/data.rs b/pac/atsamc20g/src/sercom0/spim/data.rs new file mode 100644 index 000000000000..dc9cd020d2a5 --- /dev/null +++ b/pac/atsamc20g/src/sercom0/spim/data.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data Value"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data Value"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01ff) | (value as u32 & 0x01ff); + self.w + } +} +impl R { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new((self.bits & 0x01ff) as u16) + } +} +impl W { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/sercom0/spim/dbgctrl.rs b/pac/atsamc20g/src/sercom0/spim/dbgctrl.rs new file mode 100644 index 000000000000..d9aa7495940c --- /dev/null +++ b/pac/atsamc20g/src/sercom0/spim/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGSTOP` reader - Debug Mode"] +pub struct DBGSTOP_R(crate::FieldReader); +impl DBGSTOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGSTOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGSTOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGSTOP` writer - Debug Mode"] +pub struct DBGSTOP_W<'a> { + w: &'a mut W, +} +impl<'a> DBGSTOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&self) -> DBGSTOP_R { + DBGSTOP_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&mut self) -> DBGSTOP_W { + DBGSTOP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/sercom0/spim/intenclr.rs b/pac/atsamc20g/src/sercom0/spim/intenclr.rs new file mode 100644 index 000000000000..ccab3de4348d --- /dev/null +++ b/pac/atsamc20g/src/sercom0/spim/intenclr.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Disable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Disable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Disable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Disable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Disable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Disable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SSL` reader - Slave Select Low Interrupt Disable"] +pub struct SSL_R(crate::FieldReader); +impl SSL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SSL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSL` writer - Slave Select Low Interrupt Disable"] +pub struct SSL_W<'a> { + w: &'a mut W, +} +impl<'a> SSL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Disable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Disable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Slave Select Low Interrupt Disable"] + #[inline(always)] + pub fn ssl(&self) -> SSL_R { + SSL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Slave Select Low Interrupt Disable"] + #[inline(always)] + pub fn ssl(&mut self) -> SSL_W { + SSL_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/sercom0/spim/intenset.rs b/pac/atsamc20g/src/sercom0/spim/intenset.rs new file mode 100644 index 000000000000..d9779cf897c2 --- /dev/null +++ b/pac/atsamc20g/src/sercom0/spim/intenset.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Enable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Enable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Enable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Enable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Enable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Enable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SSL` reader - Slave Select Low Interrupt Enable"] +pub struct SSL_R(crate::FieldReader); +impl SSL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SSL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSL` writer - Slave Select Low Interrupt Enable"] +pub struct SSL_W<'a> { + w: &'a mut W, +} +impl<'a> SSL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Slave Select Low Interrupt Enable"] + #[inline(always)] + pub fn ssl(&self) -> SSL_R { + SSL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Slave Select Low Interrupt Enable"] + #[inline(always)] + pub fn ssl(&mut self) -> SSL_W { + SSL_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/sercom0/spim/intflag.rs b/pac/atsamc20g/src/sercom0/spim/intflag.rs new file mode 100644 index 000000000000..e9bc10c271b8 --- /dev/null +++ b/pac/atsamc20g/src/sercom0/spim/intflag.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SSL` reader - Slave Select Low Interrupt Flag"] +pub struct SSL_R(crate::FieldReader); +impl SSL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SSL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSL` writer - Slave Select Low Interrupt Flag"] +pub struct SSL_W<'a> { + w: &'a mut W, +} +impl<'a> SSL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Slave Select Low Interrupt Flag"] + #[inline(always)] + pub fn ssl(&self) -> SSL_R { + SSL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Slave Select Low Interrupt Flag"] + #[inline(always)] + pub fn ssl(&mut self) -> SSL_W { + SSL_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/sercom0/spim/status.rs b/pac/atsamc20g/src/sercom0/spim/status.rs new file mode 100644 index 000000000000..9919460bf0e2 --- /dev/null +++ b/pac/atsamc20g/src/sercom0/spim/status.rs @@ -0,0 +1,113 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BUFOVF` reader - Buffer Overflow"] +pub struct BUFOVF_R(crate::FieldReader); +impl BUFOVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUFOVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUFOVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUFOVF` writer - Buffer Overflow"] +pub struct BUFOVF_W<'a> { + w: &'a mut W, +} +impl<'a> BUFOVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&self) -> BUFOVF_R { + BUFOVF_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&mut self) -> BUFOVF_W { + BUFOVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/sercom0/spim/syncbusy.rs b/pac/atsamc20g/src/sercom0/spim/syncbusy.rs new file mode 100644 index 000000000000..bee13adf7084 --- /dev/null +++ b/pac/atsamc20g/src/sercom0/spim/syncbusy.rs @@ -0,0 +1,93 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - SERCOM Enable Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLB` reader - CTRLB Synchronization Busy"] +pub struct CTRLB_R(crate::FieldReader); +impl CTRLB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM Enable Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - CTRLB Synchronization Busy"] + #[inline(always)] + pub fn ctrlb(&self) -> CTRLB_R { + CTRLB_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +#[doc = "SPIM Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/sercom0/spis.rs b/pac/atsamc20g/src/sercom0/spis.rs new file mode 100644 index 000000000000..eed10c90c460 --- /dev/null +++ b/pac/atsamc20g/src/sercom0/spis.rs @@ -0,0 +1,44 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "SPIS Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "SPIS Control B"] +pub mod ctrlb; +#[doc = "BAUD register accessor: an alias for `Reg`"] +pub type BAUD = crate::Reg; +#[doc = "SPIS Baud Rate"] +pub mod baud; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "SPIS Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "SPIS Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "SPIS Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "SPIS Status"] +pub mod status; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "SPIS Synchronization Busy"] +pub mod syncbusy; +#[doc = "ADDR register accessor: an alias for `Reg`"] +pub type ADDR = crate::Reg; +#[doc = "SPIS Address"] +pub mod addr; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "SPIS Data"] +pub mod data; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "SPIS Debug Control"] +pub mod dbgctrl; diff --git a/pac/atsamc20g/src/sercom0/spis/addr.rs b/pac/atsamc20g/src/sercom0/spis/addr.rs new file mode 100644 index 000000000000..5fca0a698bfe --- /dev/null +++ b/pac/atsamc20g/src/sercom0/spis/addr.rs @@ -0,0 +1,140 @@ +#[doc = "Register `ADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ADDR` reader - Address Value"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - Address Value"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +#[doc = "Field `ADDRMASK` reader - Address Mask"] +pub struct ADDRMASK_R(crate::FieldReader); +impl ADDRMASK_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ADDRMASK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDRMASK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDRMASK` writer - Address Mask"] +pub struct ADDRMASK_W<'a> { + w: &'a mut W, +} +impl<'a> ADDRMASK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Address Value"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 16:23 - Address Mask"] + #[inline(always)] + pub fn addrmask(&self) -> ADDRMASK_R { + ADDRMASK_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Address Value"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Bits 16:23 - Address Mask"] + #[inline(always)] + pub fn addrmask(&mut self) -> ADDRMASK_W { + ADDRMASK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [addr](index.html) module"] +pub struct ADDR_SPEC; +impl crate::RegisterSpec for ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [addr::R](R) reader structure"] +impl crate::Readable for ADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [addr::W](W) writer structure"] +impl crate::Writable for ADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ADDR to value 0"] +impl crate::Resettable for ADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/sercom0/spis/baud.rs b/pac/atsamc20g/src/sercom0/spis/baud.rs new file mode 100644 index 000000000000..eeee4cf633e5 --- /dev/null +++ b/pac/atsamc20g/src/sercom0/spis/baud.rs @@ -0,0 +1,103 @@ +#[doc = "Register `BAUD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud](index.html) module"] +pub struct BAUD_SPEC; +impl crate::RegisterSpec for BAUD_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [baud::R](R) reader structure"] +impl crate::Readable for BAUD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud::W](W) writer structure"] +impl crate::Writable for BAUD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD to value 0"] +impl crate::Resettable for BAUD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/sercom0/spis/ctrla.rs b/pac/atsamc20g/src/sercom0/spis/ctrla.rs new file mode 100644 index 000000000000..6151433a8529 --- /dev/null +++ b/pac/atsamc20g/src/sercom0/spis/ctrla.rs @@ -0,0 +1,992 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: USART with external clock"] + USART_EXT_CLK = 0, + #[doc = "1: USART with internal clock"] + USART_INT_CLK = 1, + #[doc = "2: SPI in slave operation"] + SPI_SLAVE = 2, + #[doc = "3: SPI in master operation"] + SPI_MASTER = 3, + #[doc = "4: I2C slave operation"] + I2C_SLAVE = 4, + #[doc = "5: I2C master operation"] + I2C_MASTER = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::USART_EXT_CLK), + 1 => Some(MODE_A::USART_INT_CLK), + 2 => Some(MODE_A::SPI_SLAVE), + 3 => Some(MODE_A::SPI_MASTER), + 4 => Some(MODE_A::I2C_SLAVE), + 5 => Some(MODE_A::I2C_MASTER), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_EXT_CLK`"] + #[inline(always)] + pub fn is_usart_ext_clk(&self) -> bool { + **self == MODE_A::USART_EXT_CLK + } + #[doc = "Checks if the value of the field is `USART_INT_CLK`"] + #[inline(always)] + pub fn is_usart_int_clk(&self) -> bool { + **self == MODE_A::USART_INT_CLK + } + #[doc = "Checks if the value of the field is `SPI_SLAVE`"] + #[inline(always)] + pub fn is_spi_slave(&self) -> bool { + **self == MODE_A::SPI_SLAVE + } + #[doc = "Checks if the value of the field is `SPI_MASTER`"] + #[inline(always)] + pub fn is_spi_master(&self) -> bool { + **self == MODE_A::SPI_MASTER + } + #[doc = "Checks if the value of the field is `I2C_SLAVE`"] + #[inline(always)] + pub fn is_i2c_slave(&self) -> bool { + **self == MODE_A::I2C_SLAVE + } + #[doc = "Checks if the value of the field is `I2C_MASTER`"] + #[inline(always)] + pub fn is_i2c_master(&self) -> bool { + **self == MODE_A::I2C_MASTER + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART with external clock"] + #[inline(always)] + pub fn usart_ext_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_EXT_CLK) + } + #[doc = "USART with internal clock"] + #[inline(always)] + pub fn usart_int_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_INT_CLK) + } + #[doc = "SPI in slave operation"] + #[inline(always)] + pub fn spi_slave(self) -> &'a mut W { + self.variant(MODE_A::SPI_SLAVE) + } + #[doc = "SPI in master operation"] + #[inline(always)] + pub fn spi_master(self) -> &'a mut W { + self.variant(MODE_A::SPI_MASTER) + } + #[doc = "I2C slave operation"] + #[inline(always)] + pub fn i2c_slave(self) -> &'a mut W { + self.variant(MODE_A::I2C_SLAVE) + } + #[doc = "I2C master operation"] + #[inline(always)] + pub fn i2c_master(self) -> &'a mut W { + self.variant(MODE_A::I2C_MASTER) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 2)) | ((value as u32 & 0x07) << 2); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `IBON` reader - Immediate Buffer Overflow Notification"] +pub struct IBON_R(crate::FieldReader); +impl IBON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IBON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IBON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IBON` writer - Immediate Buffer Overflow Notification"] +pub struct IBON_W<'a> { + w: &'a mut W, +} +impl<'a> IBON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Data Out Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DOPO_A { + #[doc = "0: DO on PAD\\[0\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + PAD0 = 0, + #[doc = "1: DO on PAD\\[2\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + PAD1 = 1, + #[doc = "2: DO on PAD\\[3\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + PAD2 = 2, + #[doc = "3: DO on PAD\\[0\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + PAD3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DOPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `DOPO` reader - Data Out Pinout"] +pub struct DOPO_R(crate::FieldReader); +impl DOPO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DOPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DOPO_A { + match self.bits { + 0 => DOPO_A::PAD0, + 1 => DOPO_A::PAD1, + 2 => DOPO_A::PAD2, + 3 => DOPO_A::PAD3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == DOPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD1`"] + #[inline(always)] + pub fn is_pad1(&self) -> bool { + **self == DOPO_A::PAD1 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == DOPO_A::PAD2 + } + #[doc = "Checks if the value of the field is `PAD3`"] + #[inline(always)] + pub fn is_pad3(&self) -> bool { + **self == DOPO_A::PAD3 + } +} +impl core::ops::Deref for DOPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DOPO` writer - Data Out Pinout"] +pub struct DOPO_W<'a> { + w: &'a mut W, +} +impl<'a> DOPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DOPO_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "DO on PAD\\[0\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(DOPO_A::PAD0) + } + #[doc = "DO on PAD\\[2\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + #[inline(always)] + pub fn pad1(self) -> &'a mut W { + self.variant(DOPO_A::PAD1) + } + #[doc = "DO on PAD\\[3\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(DOPO_A::PAD2) + } + #[doc = "DO on PAD\\[0\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + #[inline(always)] + pub fn pad3(self) -> &'a mut W { + self.variant(DOPO_A::PAD3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Data In Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DIPO_A { + #[doc = "0: SERCOM PAD\\[0\\]"] + PAD0 = 0, + #[doc = "1: SERCOM PAD\\[1\\]"] + PAD1 = 1, + #[doc = "2: SERCOM PAD\\[2\\]"] + PAD2 = 2, + #[doc = "3: SERCOM PAD\\[3\\]"] + PAD3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DIPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `DIPO` reader - Data In Pinout"] +pub struct DIPO_R(crate::FieldReader); +impl DIPO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DIPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DIPO_A { + match self.bits { + 0 => DIPO_A::PAD0, + 1 => DIPO_A::PAD1, + 2 => DIPO_A::PAD2, + 3 => DIPO_A::PAD3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == DIPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD1`"] + #[inline(always)] + pub fn is_pad1(&self) -> bool { + **self == DIPO_A::PAD1 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == DIPO_A::PAD2 + } + #[doc = "Checks if the value of the field is `PAD3`"] + #[inline(always)] + pub fn is_pad3(&self) -> bool { + **self == DIPO_A::PAD3 + } +} +impl core::ops::Deref for DIPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIPO` writer - Data In Pinout"] +pub struct DIPO_W<'a> { + w: &'a mut W, +} +impl<'a> DIPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DIPO_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "SERCOM PAD\\[0\\]"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(DIPO_A::PAD0) + } + #[doc = "SERCOM PAD\\[1\\]"] + #[inline(always)] + pub fn pad1(self) -> &'a mut W { + self.variant(DIPO_A::PAD1) + } + #[doc = "SERCOM PAD\\[2\\]"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(DIPO_A::PAD2) + } + #[doc = "SERCOM PAD\\[3\\]"] + #[inline(always)] + pub fn pad3(self) -> &'a mut W { + self.variant(DIPO_A::PAD3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 20)) | ((value as u32 & 0x03) << 20); + self.w + } +} +#[doc = "Frame Format\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FORM_A { + #[doc = "0: SPI Frame"] + SPI_FRAME = 0, + #[doc = "2: SPI Frame with Addr"] + SPI_FRAME_WITH_ADDR = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FORM_A) -> Self { + variant as _ + } +} +#[doc = "Field `FORM` reader - Frame Format"] +pub struct FORM_R(crate::FieldReader); +impl FORM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FORM_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(FORM_A::SPI_FRAME), + 2 => Some(FORM_A::SPI_FRAME_WITH_ADDR), + _ => None, + } + } + #[doc = "Checks if the value of the field is `SPI_FRAME`"] + #[inline(always)] + pub fn is_spi_frame(&self) -> bool { + **self == FORM_A::SPI_FRAME + } + #[doc = "Checks if the value of the field is `SPI_FRAME_WITH_ADDR`"] + #[inline(always)] + pub fn is_spi_frame_with_addr(&self) -> bool { + **self == FORM_A::SPI_FRAME_WITH_ADDR + } +} +impl core::ops::Deref for FORM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FORM` writer - Frame Format"] +pub struct FORM_W<'a> { + w: &'a mut W, +} +impl<'a> FORM_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FORM_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "SPI Frame"] + #[inline(always)] + pub fn spi_frame(self) -> &'a mut W { + self.variant(FORM_A::SPI_FRAME) + } + #[doc = "SPI Frame with Addr"] + #[inline(always)] + pub fn spi_frame_with_addr(self) -> &'a mut W { + self.variant(FORM_A::SPI_FRAME_WITH_ADDR) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Clock Phase\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CPHA_A { + #[doc = "0: The data is sampled on a leading SCK edge and changed on a trailing SCK edge"] + LEADING_EDGE = 0, + #[doc = "1: The data is sampled on a trailing SCK edge and changed on a leading SCK edge"] + TRAILING_EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CPHA_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CPHA` reader - Clock Phase"] +pub struct CPHA_R(crate::FieldReader); +impl CPHA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPHA_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CPHA_A { + match self.bits { + false => CPHA_A::LEADING_EDGE, + true => CPHA_A::TRAILING_EDGE, + } + } + #[doc = "Checks if the value of the field is `LEADING_EDGE`"] + #[inline(always)] + pub fn is_leading_edge(&self) -> bool { + **self == CPHA_A::LEADING_EDGE + } + #[doc = "Checks if the value of the field is `TRAILING_EDGE`"] + #[inline(always)] + pub fn is_trailing_edge(&self) -> bool { + **self == CPHA_A::TRAILING_EDGE + } +} +impl core::ops::Deref for CPHA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPHA` writer - Clock Phase"] +pub struct CPHA_W<'a> { + w: &'a mut W, +} +impl<'a> CPHA_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CPHA_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "The data is sampled on a leading SCK edge and changed on a trailing SCK edge"] + #[inline(always)] + pub fn leading_edge(self) -> &'a mut W { + self.variant(CPHA_A::LEADING_EDGE) + } + #[doc = "The data is sampled on a trailing SCK edge and changed on a leading SCK edge"] + #[inline(always)] + pub fn trailing_edge(self) -> &'a mut W { + self.variant(CPHA_A::TRAILING_EDGE) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Clock Polarity\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CPOL_A { + #[doc = "0: SCK is low when idle"] + IDLE_LOW = 0, + #[doc = "1: SCK is high when idle"] + IDLE_HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CPOL_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CPOL` reader - Clock Polarity"] +pub struct CPOL_R(crate::FieldReader); +impl CPOL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPOL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CPOL_A { + match self.bits { + false => CPOL_A::IDLE_LOW, + true => CPOL_A::IDLE_HIGH, + } + } + #[doc = "Checks if the value of the field is `IDLE_LOW`"] + #[inline(always)] + pub fn is_idle_low(&self) -> bool { + **self == CPOL_A::IDLE_LOW + } + #[doc = "Checks if the value of the field is `IDLE_HIGH`"] + #[inline(always)] + pub fn is_idle_high(&self) -> bool { + **self == CPOL_A::IDLE_HIGH + } +} +impl core::ops::Deref for CPOL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPOL` writer - Clock Polarity"] +pub struct CPOL_W<'a> { + w: &'a mut W, +} +impl<'a> CPOL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CPOL_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "SCK is low when idle"] + #[inline(always)] + pub fn idle_low(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_LOW) + } + #[doc = "SCK is high when idle"] + #[inline(always)] + pub fn idle_high(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_HIGH) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29); + self.w + } +} +#[doc = "Data Order\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum DORD_A { + #[doc = "0: MSB is transferred first"] + MSB = 0, + #[doc = "1: LSB is transferred first"] + LSB = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DORD_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DORD` reader - Data Order"] +pub struct DORD_R(crate::FieldReader); +impl DORD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DORD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DORD_A { + match self.bits { + false => DORD_A::MSB, + true => DORD_A::LSB, + } + } + #[doc = "Checks if the value of the field is `MSB`"] + #[inline(always)] + pub fn is_msb(&self) -> bool { + **self == DORD_A::MSB + } + #[doc = "Checks if the value of the field is `LSB`"] + #[inline(always)] + pub fn is_lsb(&self) -> bool { + **self == DORD_A::LSB + } +} +impl core::ops::Deref for DORD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DORD` writer - Data Order"] +pub struct DORD_W<'a> { + w: &'a mut W, +} +impl<'a> DORD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DORD_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "MSB is transferred first"] + #[inline(always)] + pub fn msb(self) -> &'a mut W { + self.variant(DORD_A::MSB) + } + #[doc = "LSB is transferred first"] + #[inline(always)] + pub fn lsb(self) -> &'a mut W { + self.variant(DORD_A::LSB) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x07) as u8) + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&self) -> IBON_R { + IBON_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bits 16:17 - Data Out Pinout"] + #[inline(always)] + pub fn dopo(&self) -> DOPO_R { + DOPO_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bits 20:21 - Data In Pinout"] + #[inline(always)] + pub fn dipo(&self) -> DIPO_R { + DIPO_R::new(((self.bits >> 20) & 0x03) as u8) + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&self) -> FORM_R { + FORM_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 28 - Clock Phase"] + #[inline(always)] + pub fn cpha(&self) -> CPHA_R { + CPHA_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&self) -> CPOL_R { + CPOL_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&self) -> DORD_R { + DORD_R::new(((self.bits >> 30) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&mut self) -> IBON_W { + IBON_W { w: self } + } + #[doc = "Bits 16:17 - Data Out Pinout"] + #[inline(always)] + pub fn dopo(&mut self) -> DOPO_W { + DOPO_W { w: self } + } + #[doc = "Bits 20:21 - Data In Pinout"] + #[inline(always)] + pub fn dipo(&mut self) -> DIPO_W { + DIPO_W { w: self } + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&mut self) -> FORM_W { + FORM_W { w: self } + } + #[doc = "Bit 28 - Clock Phase"] + #[inline(always)] + pub fn cpha(&mut self) -> CPHA_W { + CPHA_W { w: self } + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&mut self) -> CPOL_W { + CPOL_W { w: self } + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&mut self) -> DORD_W { + DORD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/sercom0/spis/ctrlb.rs b/pac/atsamc20g/src/sercom0/spis/ctrlb.rs new file mode 100644 index 000000000000..ccb70582cf34 --- /dev/null +++ b/pac/atsamc20g/src/sercom0/spis/ctrlb.rs @@ -0,0 +1,439 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Character Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CHSIZE_A { + #[doc = "0: 8 bits"] + _8_BIT = 0, + #[doc = "1: 9 bits"] + _9_BIT = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CHSIZE_A) -> Self { + variant as _ + } +} +#[doc = "Field `CHSIZE` reader - Character Size"] +pub struct CHSIZE_R(crate::FieldReader); +impl CHSIZE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CHSIZE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CHSIZE_A::_8_BIT), + 1 => Some(CHSIZE_A::_9_BIT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_8_BIT`"] + #[inline(always)] + pub fn is_8_bit(&self) -> bool { + **self == CHSIZE_A::_8_BIT + } + #[doc = "Checks if the value of the field is `_9_BIT`"] + #[inline(always)] + pub fn is_9_bit(&self) -> bool { + **self == CHSIZE_A::_9_BIT + } +} +impl core::ops::Deref for CHSIZE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHSIZE` writer - Character Size"] +pub struct CHSIZE_W<'a> { + w: &'a mut W, +} +impl<'a> CHSIZE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CHSIZE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8 bits"] + #[inline(always)] + pub fn _8_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_8_BIT) + } + #[doc = "9 bits"] + #[inline(always)] + pub fn _9_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_9_BIT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Field `PLOADEN` reader - Data Preload Enable"] +pub struct PLOADEN_R(crate::FieldReader); +impl PLOADEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PLOADEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PLOADEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PLOADEN` writer - Data Preload Enable"] +pub struct PLOADEN_W<'a> { + w: &'a mut W, +} +impl<'a> PLOADEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `SSDE` reader - Slave Select Low Detect Enable"] +pub struct SSDE_R(crate::FieldReader); +impl SSDE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SSDE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSDE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSDE` writer - Slave Select Low Detect Enable"] +pub struct SSDE_W<'a> { + w: &'a mut W, +} +impl<'a> SSDE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `MSSEN` reader - Master Slave Select Enable"] +pub struct MSSEN_R(crate::FieldReader); +impl MSSEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MSSEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MSSEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MSSEN` writer - Master Slave Select Enable"] +pub struct MSSEN_W<'a> { + w: &'a mut W, +} +impl<'a> MSSEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Address Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum AMODE_A { + #[doc = "0: SPI Address mask"] + MASK = 0, + #[doc = "1: Two unique Addressess"] + _2_ADDRESSES = 1, + #[doc = "2: Address Range"] + RANGE = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: AMODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `AMODE` reader - Address Mode"] +pub struct AMODE_R(crate::FieldReader); +impl AMODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + AMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(AMODE_A::MASK), + 1 => Some(AMODE_A::_2_ADDRESSES), + 2 => Some(AMODE_A::RANGE), + _ => None, + } + } + #[doc = "Checks if the value of the field is `MASK`"] + #[inline(always)] + pub fn is_mask(&self) -> bool { + **self == AMODE_A::MASK + } + #[doc = "Checks if the value of the field is `_2_ADDRESSES`"] + #[inline(always)] + pub fn is_2_addresses(&self) -> bool { + **self == AMODE_A::_2_ADDRESSES + } + #[doc = "Checks if the value of the field is `RANGE`"] + #[inline(always)] + pub fn is_range(&self) -> bool { + **self == AMODE_A::RANGE + } +} +impl core::ops::Deref for AMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AMODE` writer - Address Mode"] +pub struct AMODE_W<'a> { + w: &'a mut W, +} +impl<'a> AMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: AMODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "SPI Address mask"] + #[inline(always)] + pub fn mask(self) -> &'a mut W { + self.variant(AMODE_A::MASK) + } + #[doc = "Two unique Addressess"] + #[inline(always)] + pub fn _2_addresses(self) -> &'a mut W { + self.variant(AMODE_A::_2_ADDRESSES) + } + #[doc = "Address Range"] + #[inline(always)] + pub fn range(self) -> &'a mut W { + self.variant(AMODE_A::RANGE) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 14)) | ((value as u32 & 0x03) << 14); + self.w + } +} +#[doc = "Field `RXEN` reader - Receiver Enable"] +pub struct RXEN_R(crate::FieldReader); +impl RXEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXEN` writer - Receiver Enable"] +pub struct RXEN_W<'a> { + w: &'a mut W, +} +impl<'a> RXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&self) -> CHSIZE_R { + CHSIZE_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 6 - Data Preload Enable"] + #[inline(always)] + pub fn ploaden(&self) -> PLOADEN_R { + PLOADEN_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 9 - Slave Select Low Detect Enable"] + #[inline(always)] + pub fn ssde(&self) -> SSDE_R { + SSDE_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 13 - Master Slave Select Enable"] + #[inline(always)] + pub fn mssen(&self) -> MSSEN_R { + MSSEN_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bits 14:15 - Address Mode"] + #[inline(always)] + pub fn amode(&self) -> AMODE_R { + AMODE_R::new(((self.bits >> 14) & 0x03) as u8) + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&self) -> RXEN_R { + RXEN_R::new(((self.bits >> 17) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&mut self) -> CHSIZE_W { + CHSIZE_W { w: self } + } + #[doc = "Bit 6 - Data Preload Enable"] + #[inline(always)] + pub fn ploaden(&mut self) -> PLOADEN_W { + PLOADEN_W { w: self } + } + #[doc = "Bit 9 - Slave Select Low Detect Enable"] + #[inline(always)] + pub fn ssde(&mut self) -> SSDE_W { + SSDE_W { w: self } + } + #[doc = "Bit 13 - Master Slave Select Enable"] + #[inline(always)] + pub fn mssen(&mut self) -> MSSEN_W { + MSSEN_W { w: self } + } + #[doc = "Bits 14:15 - Address Mode"] + #[inline(always)] + pub fn amode(&mut self) -> AMODE_W { + AMODE_W { w: self } + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&mut self) -> RXEN_W { + RXEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/sercom0/spis/data.rs b/pac/atsamc20g/src/sercom0/spis/data.rs new file mode 100644 index 000000000000..4edf8089b29f --- /dev/null +++ b/pac/atsamc20g/src/sercom0/spis/data.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data Value"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data Value"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01ff) | (value as u32 & 0x01ff); + self.w + } +} +impl R { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new((self.bits & 0x01ff) as u16) + } +} +impl W { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/sercom0/spis/dbgctrl.rs b/pac/atsamc20g/src/sercom0/spis/dbgctrl.rs new file mode 100644 index 000000000000..ec36bbd26057 --- /dev/null +++ b/pac/atsamc20g/src/sercom0/spis/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGSTOP` reader - Debug Mode"] +pub struct DBGSTOP_R(crate::FieldReader); +impl DBGSTOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGSTOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGSTOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGSTOP` writer - Debug Mode"] +pub struct DBGSTOP_W<'a> { + w: &'a mut W, +} +impl<'a> DBGSTOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&self) -> DBGSTOP_R { + DBGSTOP_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&mut self) -> DBGSTOP_W { + DBGSTOP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/sercom0/spis/intenclr.rs b/pac/atsamc20g/src/sercom0/spis/intenclr.rs new file mode 100644 index 000000000000..e4c9ee0d506d --- /dev/null +++ b/pac/atsamc20g/src/sercom0/spis/intenclr.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Disable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Disable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Disable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Disable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Disable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Disable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SSL` reader - Slave Select Low Interrupt Disable"] +pub struct SSL_R(crate::FieldReader); +impl SSL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SSL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSL` writer - Slave Select Low Interrupt Disable"] +pub struct SSL_W<'a> { + w: &'a mut W, +} +impl<'a> SSL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Disable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Disable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Slave Select Low Interrupt Disable"] + #[inline(always)] + pub fn ssl(&self) -> SSL_R { + SSL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Slave Select Low Interrupt Disable"] + #[inline(always)] + pub fn ssl(&mut self) -> SSL_W { + SSL_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/sercom0/spis/intenset.rs b/pac/atsamc20g/src/sercom0/spis/intenset.rs new file mode 100644 index 000000000000..99582a624ebc --- /dev/null +++ b/pac/atsamc20g/src/sercom0/spis/intenset.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Enable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Enable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Enable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Enable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Enable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Enable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SSL` reader - Slave Select Low Interrupt Enable"] +pub struct SSL_R(crate::FieldReader); +impl SSL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SSL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSL` writer - Slave Select Low Interrupt Enable"] +pub struct SSL_W<'a> { + w: &'a mut W, +} +impl<'a> SSL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Slave Select Low Interrupt Enable"] + #[inline(always)] + pub fn ssl(&self) -> SSL_R { + SSL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Slave Select Low Interrupt Enable"] + #[inline(always)] + pub fn ssl(&mut self) -> SSL_W { + SSL_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/sercom0/spis/intflag.rs b/pac/atsamc20g/src/sercom0/spis/intflag.rs new file mode 100644 index 000000000000..589e73c2329f --- /dev/null +++ b/pac/atsamc20g/src/sercom0/spis/intflag.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SSL` reader - Slave Select Low Interrupt Flag"] +pub struct SSL_R(crate::FieldReader); +impl SSL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SSL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSL` writer - Slave Select Low Interrupt Flag"] +pub struct SSL_W<'a> { + w: &'a mut W, +} +impl<'a> SSL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Slave Select Low Interrupt Flag"] + #[inline(always)] + pub fn ssl(&self) -> SSL_R { + SSL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Slave Select Low Interrupt Flag"] + #[inline(always)] + pub fn ssl(&mut self) -> SSL_W { + SSL_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/sercom0/spis/status.rs b/pac/atsamc20g/src/sercom0/spis/status.rs new file mode 100644 index 000000000000..55c39c1a709f --- /dev/null +++ b/pac/atsamc20g/src/sercom0/spis/status.rs @@ -0,0 +1,113 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BUFOVF` reader - Buffer Overflow"] +pub struct BUFOVF_R(crate::FieldReader); +impl BUFOVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUFOVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUFOVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUFOVF` writer - Buffer Overflow"] +pub struct BUFOVF_W<'a> { + w: &'a mut W, +} +impl<'a> BUFOVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&self) -> BUFOVF_R { + BUFOVF_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&mut self) -> BUFOVF_W { + BUFOVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/sercom0/spis/syncbusy.rs b/pac/atsamc20g/src/sercom0/spis/syncbusy.rs new file mode 100644 index 000000000000..ac2f2e2c27ec --- /dev/null +++ b/pac/atsamc20g/src/sercom0/spis/syncbusy.rs @@ -0,0 +1,93 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - SERCOM Enable Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLB` reader - CTRLB Synchronization Busy"] +pub struct CTRLB_R(crate::FieldReader); +impl CTRLB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM Enable Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - CTRLB Synchronization Busy"] + #[inline(always)] + pub fn ctrlb(&self) -> CTRLB_R { + CTRLB_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +#[doc = "SPIS Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/sercom0/usart_ext.rs b/pac/atsamc20g/src/sercom0/usart_ext.rs new file mode 100644 index 000000000000..8c08b9efc1d5 --- /dev/null +++ b/pac/atsamc20g/src/sercom0/usart_ext.rs @@ -0,0 +1,60 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "USART_EXT Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "USART_EXT Control B"] +pub mod ctrlb; +#[doc = "CTRLC register accessor: an alias for `Reg`"] +pub type CTRLC = crate::Reg; +#[doc = "USART_EXT Control C"] +pub mod ctrlc; +#[doc = "BAUD register accessor: an alias for `Reg`"] +pub type BAUD = crate::Reg; +#[doc = "USART_EXT Baud Rate"] +pub mod baud; +#[doc = "BAUD_FRAC_MODE register accessor: an alias for `Reg`"] +pub type BAUD_FRAC_MODE = crate::Reg; +#[doc = "USART_EXT Baud Rate"] +pub mod baud_frac_mode; +#[doc = "BAUD_FRACFP_MODE register accessor: an alias for `Reg`"] +pub type BAUD_FRACFP_MODE = crate::Reg; +#[doc = "USART_EXT Baud Rate"] +pub mod baud_fracfp_mode; +#[doc = "BAUD_USARTFP_MODE register accessor: an alias for `Reg`"] +pub type BAUD_USARTFP_MODE = crate::Reg; +#[doc = "USART_EXT Baud Rate"] +pub mod baud_usartfp_mode; +#[doc = "RXPL register accessor: an alias for `Reg`"] +pub type RXPL = crate::Reg; +#[doc = "USART_EXT Receive Pulse Length"] +pub mod rxpl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "USART_EXT Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "USART_EXT Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "USART_EXT Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "USART_EXT Status"] +pub mod status; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "USART_EXT Synchronization Busy"] +pub mod syncbusy; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "USART_EXT Data"] +pub mod data; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "USART_EXT Debug Control"] +pub mod dbgctrl; diff --git a/pac/atsamc20g/src/sercom0/usart_ext/baud.rs b/pac/atsamc20g/src/sercom0/usart_ext/baud.rs new file mode 100644 index 000000000000..9558a8e1a52d --- /dev/null +++ b/pac/atsamc20g/src/sercom0/usart_ext/baud.rs @@ -0,0 +1,103 @@ +#[doc = "Register `BAUD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud](index.html) module"] +pub struct BAUD_SPEC; +impl crate::RegisterSpec for BAUD_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud::R](R) reader structure"] +impl crate::Readable for BAUD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud::W](W) writer structure"] +impl crate::Writable for BAUD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD to value 0"] +impl crate::Resettable for BAUD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/sercom0/usart_ext/baud_frac_mode.rs b/pac/atsamc20g/src/sercom0/usart_ext/baud_frac_mode.rs new file mode 100644 index 000000000000..d7cdd4570e26 --- /dev/null +++ b/pac/atsamc20g/src/sercom0/usart_ext/baud_frac_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `BAUD_FRAC_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD_FRAC_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1fff) | (value as u16 & 0x1fff); + self.w + } +} +#[doc = "Field `FP` reader - Fractional Part"] +pub struct FP_R(crate::FieldReader); +impl FP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FP` writer - Fractional Part"] +pub struct FP_W<'a> { + w: &'a mut W, +} +impl<'a> FP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 13)) | ((value as u16 & 0x07) << 13); + self.w + } +} +impl R { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new((self.bits & 0x1fff) as u16) + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&self) -> FP_R { + FP_R::new(((self.bits >> 13) & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&mut self) -> FP_W { + FP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud_frac_mode](index.html) module"] +pub struct BAUD_FRAC_MODE_SPEC; +impl crate::RegisterSpec for BAUD_FRAC_MODE_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud_frac_mode::R](R) reader structure"] +impl crate::Readable for BAUD_FRAC_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud_frac_mode::W](W) writer structure"] +impl crate::Writable for BAUD_FRAC_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD_FRAC_MODE to value 0"] +impl crate::Resettable for BAUD_FRAC_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/sercom0/usart_ext/baud_fracfp_mode.rs b/pac/atsamc20g/src/sercom0/usart_ext/baud_fracfp_mode.rs new file mode 100644 index 000000000000..c1dc50807677 --- /dev/null +++ b/pac/atsamc20g/src/sercom0/usart_ext/baud_fracfp_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `BAUD_FRACFP_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD_FRACFP_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1fff) | (value as u16 & 0x1fff); + self.w + } +} +#[doc = "Field `FP` reader - Fractional Part"] +pub struct FP_R(crate::FieldReader); +impl FP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FP` writer - Fractional Part"] +pub struct FP_W<'a> { + w: &'a mut W, +} +impl<'a> FP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 13)) | ((value as u16 & 0x07) << 13); + self.w + } +} +impl R { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new((self.bits & 0x1fff) as u16) + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&self) -> FP_R { + FP_R::new(((self.bits >> 13) & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&mut self) -> FP_W { + FP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud_fracfp_mode](index.html) module"] +pub struct BAUD_FRACFP_MODE_SPEC; +impl crate::RegisterSpec for BAUD_FRACFP_MODE_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud_fracfp_mode::R](R) reader structure"] +impl crate::Readable for BAUD_FRACFP_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud_fracfp_mode::W](W) writer structure"] +impl crate::Writable for BAUD_FRACFP_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD_FRACFP_MODE to value 0"] +impl crate::Resettable for BAUD_FRACFP_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/sercom0/usart_ext/baud_usartfp_mode.rs b/pac/atsamc20g/src/sercom0/usart_ext/baud_usartfp_mode.rs new file mode 100644 index 000000000000..8d4db16e0245 --- /dev/null +++ b/pac/atsamc20g/src/sercom0/usart_ext/baud_usartfp_mode.rs @@ -0,0 +1,103 @@ +#[doc = "Register `BAUD_USARTFP_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD_USARTFP_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud_usartfp_mode](index.html) module"] +pub struct BAUD_USARTFP_MODE_SPEC; +impl crate::RegisterSpec for BAUD_USARTFP_MODE_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud_usartfp_mode::R](R) reader structure"] +impl crate::Readable for BAUD_USARTFP_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud_usartfp_mode::W](W) writer structure"] +impl crate::Writable for BAUD_USARTFP_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD_USARTFP_MODE to value 0"] +impl crate::Resettable for BAUD_USARTFP_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/sercom0/usart_ext/ctrla.rs b/pac/atsamc20g/src/sercom0/usart_ext/ctrla.rs new file mode 100644 index 000000000000..535875ac8b25 --- /dev/null +++ b/pac/atsamc20g/src/sercom0/usart_ext/ctrla.rs @@ -0,0 +1,1171 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: USART with external clock"] + USART_EXT_CLK = 0, + #[doc = "1: USART with internal clock"] + USART_INT_CLK = 1, + #[doc = "2: SPI in slave operation"] + SPI_SLAVE = 2, + #[doc = "3: SPI in master operation"] + SPI_MASTER = 3, + #[doc = "4: I2C slave operation"] + I2C_SLAVE = 4, + #[doc = "5: I2C master operation"] + I2C_MASTER = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::USART_EXT_CLK), + 1 => Some(MODE_A::USART_INT_CLK), + 2 => Some(MODE_A::SPI_SLAVE), + 3 => Some(MODE_A::SPI_MASTER), + 4 => Some(MODE_A::I2C_SLAVE), + 5 => Some(MODE_A::I2C_MASTER), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_EXT_CLK`"] + #[inline(always)] + pub fn is_usart_ext_clk(&self) -> bool { + **self == MODE_A::USART_EXT_CLK + } + #[doc = "Checks if the value of the field is `USART_INT_CLK`"] + #[inline(always)] + pub fn is_usart_int_clk(&self) -> bool { + **self == MODE_A::USART_INT_CLK + } + #[doc = "Checks if the value of the field is `SPI_SLAVE`"] + #[inline(always)] + pub fn is_spi_slave(&self) -> bool { + **self == MODE_A::SPI_SLAVE + } + #[doc = "Checks if the value of the field is `SPI_MASTER`"] + #[inline(always)] + pub fn is_spi_master(&self) -> bool { + **self == MODE_A::SPI_MASTER + } + #[doc = "Checks if the value of the field is `I2C_SLAVE`"] + #[inline(always)] + pub fn is_i2c_slave(&self) -> bool { + **self == MODE_A::I2C_SLAVE + } + #[doc = "Checks if the value of the field is `I2C_MASTER`"] + #[inline(always)] + pub fn is_i2c_master(&self) -> bool { + **self == MODE_A::I2C_MASTER + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART with external clock"] + #[inline(always)] + pub fn usart_ext_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_EXT_CLK) + } + #[doc = "USART with internal clock"] + #[inline(always)] + pub fn usart_int_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_INT_CLK) + } + #[doc = "SPI in slave operation"] + #[inline(always)] + pub fn spi_slave(self) -> &'a mut W { + self.variant(MODE_A::SPI_SLAVE) + } + #[doc = "SPI in master operation"] + #[inline(always)] + pub fn spi_master(self) -> &'a mut W { + self.variant(MODE_A::SPI_MASTER) + } + #[doc = "I2C slave operation"] + #[inline(always)] + pub fn i2c_slave(self) -> &'a mut W { + self.variant(MODE_A::I2C_SLAVE) + } + #[doc = "I2C master operation"] + #[inline(always)] + pub fn i2c_master(self) -> &'a mut W { + self.variant(MODE_A::I2C_MASTER) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 2)) | ((value as u32 & 0x07) << 2); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `IBON` reader - Immediate Buffer Overflow Notification"] +pub struct IBON_R(crate::FieldReader); +impl IBON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IBON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IBON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IBON` writer - Immediate Buffer Overflow Notification"] +pub struct IBON_W<'a> { + w: &'a mut W, +} +impl<'a> IBON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Sample\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SAMPR_A { + #[doc = "0: 16x over-sampling using arithmetic baudrate generation"] + _16X_ARITHMETIC = 0, + #[doc = "1: 16x over-sampling using fractional baudrate generation"] + _16X_FRACTIONAL = 1, + #[doc = "2: 8x over-sampling using arithmetic baudrate generation"] + _8X_ARITHMETIC = 2, + #[doc = "3: 8x over-sampling using fractional baudrate generation"] + _8X_FRACTIONAL = 3, + #[doc = "4: 3x over-sampling using arithmetic baudrate generation"] + _3X_ARITHMETIC = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SAMPR_A) -> Self { + variant as _ + } +} +#[doc = "Field `SAMPR` reader - Sample"] +pub struct SAMPR_R(crate::FieldReader); +impl SAMPR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SAMPR_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SAMPR_A::_16X_ARITHMETIC), + 1 => Some(SAMPR_A::_16X_FRACTIONAL), + 2 => Some(SAMPR_A::_8X_ARITHMETIC), + 3 => Some(SAMPR_A::_8X_FRACTIONAL), + 4 => Some(SAMPR_A::_3X_ARITHMETIC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_16X_ARITHMETIC`"] + #[inline(always)] + pub fn is_16x_arithmetic(&self) -> bool { + **self == SAMPR_A::_16X_ARITHMETIC + } + #[doc = "Checks if the value of the field is `_16X_FRACTIONAL`"] + #[inline(always)] + pub fn is_16x_fractional(&self) -> bool { + **self == SAMPR_A::_16X_FRACTIONAL + } + #[doc = "Checks if the value of the field is `_8X_ARITHMETIC`"] + #[inline(always)] + pub fn is_8x_arithmetic(&self) -> bool { + **self == SAMPR_A::_8X_ARITHMETIC + } + #[doc = "Checks if the value of the field is `_8X_FRACTIONAL`"] + #[inline(always)] + pub fn is_8x_fractional(&self) -> bool { + **self == SAMPR_A::_8X_FRACTIONAL + } + #[doc = "Checks if the value of the field is `_3X_ARITHMETIC`"] + #[inline(always)] + pub fn is_3x_arithmetic(&self) -> bool { + **self == SAMPR_A::_3X_ARITHMETIC + } +} +impl core::ops::Deref for SAMPR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SAMPR` writer - Sample"] +pub struct SAMPR_W<'a> { + w: &'a mut W, +} +impl<'a> SAMPR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SAMPR_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "16x over-sampling using arithmetic baudrate generation"] + #[inline(always)] + pub fn _16x_arithmetic(self) -> &'a mut W { + self.variant(SAMPR_A::_16X_ARITHMETIC) + } + #[doc = "16x over-sampling using fractional baudrate generation"] + #[inline(always)] + pub fn _16x_fractional(self) -> &'a mut W { + self.variant(SAMPR_A::_16X_FRACTIONAL) + } + #[doc = "8x over-sampling using arithmetic baudrate generation"] + #[inline(always)] + pub fn _8x_arithmetic(self) -> &'a mut W { + self.variant(SAMPR_A::_8X_ARITHMETIC) + } + #[doc = "8x over-sampling using fractional baudrate generation"] + #[inline(always)] + pub fn _8x_fractional(self) -> &'a mut W { + self.variant(SAMPR_A::_8X_FRACTIONAL) + } + #[doc = "3x over-sampling using arithmetic baudrate generation"] + #[inline(always)] + pub fn _3x_arithmetic(self) -> &'a mut W { + self.variant(SAMPR_A::_3X_ARITHMETIC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 13)) | ((value as u32 & 0x07) << 13); + self.w + } +} +#[doc = "Transmit Data Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum TXPO_A { + #[doc = "0: SERCOM PAD\\[0\\] +is used for data transmission"] + PAD0 = 0, + #[doc = "1: SERCOM PAD\\[2\\] +is used for data transmission"] + PAD2 = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: TXPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `TXPO` reader - Transmit Data Pinout"] +pub struct TXPO_R(crate::FieldReader); +impl TXPO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TXPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(TXPO_A::PAD0), + 1 => Some(TXPO_A::PAD2), + _ => None, + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == TXPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == TXPO_A::PAD2 + } +} +impl core::ops::Deref for TXPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXPO` writer - Transmit Data Pinout"] +pub struct TXPO_W<'a> { + w: &'a mut W, +} +impl<'a> TXPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TXPO_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "SERCOM PAD\\[0\\] +is used for data transmission"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(TXPO_A::PAD0) + } + #[doc = "SERCOM PAD\\[2\\] +is used for data transmission"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(TXPO_A::PAD2) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Receive Data Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum RXPO_A { + #[doc = "0: SERCOM PAD\\[0\\] +is used for data reception"] + PAD0 = 0, + #[doc = "1: SERCOM PAD\\[1\\] +is used for data reception"] + PAD1 = 1, + #[doc = "2: SERCOM PAD\\[2\\] +is used for data reception"] + PAD2 = 2, + #[doc = "3: SERCOM PAD\\[3\\] +is used for data reception"] + PAD3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RXPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `RXPO` reader - Receive Data Pinout"] +pub struct RXPO_R(crate::FieldReader); +impl RXPO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RXPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RXPO_A { + match self.bits { + 0 => RXPO_A::PAD0, + 1 => RXPO_A::PAD1, + 2 => RXPO_A::PAD2, + 3 => RXPO_A::PAD3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == RXPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD1`"] + #[inline(always)] + pub fn is_pad1(&self) -> bool { + **self == RXPO_A::PAD1 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == RXPO_A::PAD2 + } + #[doc = "Checks if the value of the field is `PAD3`"] + #[inline(always)] + pub fn is_pad3(&self) -> bool { + **self == RXPO_A::PAD3 + } +} +impl core::ops::Deref for RXPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXPO` writer - Receive Data Pinout"] +pub struct RXPO_W<'a> { + w: &'a mut W, +} +impl<'a> RXPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RXPO_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "SERCOM PAD\\[0\\] +is used for data reception"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(RXPO_A::PAD0) + } + #[doc = "SERCOM PAD\\[1\\] +is used for data reception"] + #[inline(always)] + pub fn pad1(self) -> &'a mut W { + self.variant(RXPO_A::PAD1) + } + #[doc = "SERCOM PAD\\[2\\] +is used for data reception"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(RXPO_A::PAD2) + } + #[doc = "SERCOM PAD\\[3\\] +is used for data reception"] + #[inline(always)] + pub fn pad3(self) -> &'a mut W { + self.variant(RXPO_A::PAD3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 20)) | ((value as u32 & 0x03) << 20); + self.w + } +} +#[doc = "Field `SAMPA` reader - Sample Adjustment"] +pub struct SAMPA_R(crate::FieldReader); +impl SAMPA_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SAMPA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SAMPA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SAMPA` writer - Sample Adjustment"] +pub struct SAMPA_W<'a> { + w: &'a mut W, +} +impl<'a> SAMPA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 22)) | ((value as u32 & 0x03) << 22); + self.w + } +} +#[doc = "Frame Format\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FORM_A { + #[doc = "0: USART frame"] + USART_FRAME_NO_PARITY = 0, + #[doc = "1: USART frame with parity"] + USART_FRAME_WITH_PARITY = 1, + #[doc = "2: LIN Master - Break and sync generation"] + USART_FRAME_LIN_MASTER_MODE = 2, + #[doc = "4: Auto-baud - break detection and auto-baud"] + USART_FRAME_AUTO_BAUD_NO_PARITY = 4, + #[doc = "5: Auto-baud - break detection and auto-baud with parity"] + USART_FRAME_AUTO_BAUD_WITH_PARITY = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FORM_A) -> Self { + variant as _ + } +} +#[doc = "Field `FORM` reader - Frame Format"] +pub struct FORM_R(crate::FieldReader); +impl FORM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FORM_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(FORM_A::USART_FRAME_NO_PARITY), + 1 => Some(FORM_A::USART_FRAME_WITH_PARITY), + 2 => Some(FORM_A::USART_FRAME_LIN_MASTER_MODE), + 4 => Some(FORM_A::USART_FRAME_AUTO_BAUD_NO_PARITY), + 5 => Some(FORM_A::USART_FRAME_AUTO_BAUD_WITH_PARITY), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_FRAME_NO_PARITY`"] + #[inline(always)] + pub fn is_usart_frame_no_parity(&self) -> bool { + **self == FORM_A::USART_FRAME_NO_PARITY + } + #[doc = "Checks if the value of the field is `USART_FRAME_WITH_PARITY`"] + #[inline(always)] + pub fn is_usart_frame_with_parity(&self) -> bool { + **self == FORM_A::USART_FRAME_WITH_PARITY + } + #[doc = "Checks if the value of the field is `USART_FRAME_LIN_MASTER_MODE`"] + #[inline(always)] + pub fn is_usart_frame_lin_master_mode(&self) -> bool { + **self == FORM_A::USART_FRAME_LIN_MASTER_MODE + } + #[doc = "Checks if the value of the field is `USART_FRAME_AUTO_BAUD_NO_PARITY`"] + #[inline(always)] + pub fn is_usart_frame_auto_baud_no_parity(&self) -> bool { + **self == FORM_A::USART_FRAME_AUTO_BAUD_NO_PARITY + } + #[doc = "Checks if the value of the field is `USART_FRAME_AUTO_BAUD_WITH_PARITY`"] + #[inline(always)] + pub fn is_usart_frame_auto_baud_with_parity(&self) -> bool { + **self == FORM_A::USART_FRAME_AUTO_BAUD_WITH_PARITY + } +} +impl core::ops::Deref for FORM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FORM` writer - Frame Format"] +pub struct FORM_W<'a> { + w: &'a mut W, +} +impl<'a> FORM_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FORM_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART frame"] + #[inline(always)] + pub fn usart_frame_no_parity(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_NO_PARITY) + } + #[doc = "USART frame with parity"] + #[inline(always)] + pub fn usart_frame_with_parity(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_WITH_PARITY) + } + #[doc = "LIN Master - Break and sync generation"] + #[inline(always)] + pub fn usart_frame_lin_master_mode(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_LIN_MASTER_MODE) + } + #[doc = "Auto-baud - break detection and auto-baud"] + #[inline(always)] + pub fn usart_frame_auto_baud_no_parity(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_AUTO_BAUD_NO_PARITY) + } + #[doc = "Auto-baud - break detection and auto-baud with parity"] + #[inline(always)] + pub fn usart_frame_auto_baud_with_parity(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_AUTO_BAUD_WITH_PARITY) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Communication Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CMODE_A { + #[doc = "0: Asynchronous Communication"] + ASYNC = 0, + #[doc = "1: Synchronous Communication"] + SYNC = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CMODE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CMODE` reader - Communication Mode"] +pub struct CMODE_R(crate::FieldReader); +impl CMODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CMODE_A { + match self.bits { + false => CMODE_A::ASYNC, + true => CMODE_A::SYNC, + } + } + #[doc = "Checks if the value of the field is `ASYNC`"] + #[inline(always)] + pub fn is_async(&self) -> bool { + **self == CMODE_A::ASYNC + } + #[doc = "Checks if the value of the field is `SYNC`"] + #[inline(always)] + pub fn is_sync(&self) -> bool { + **self == CMODE_A::SYNC + } +} +impl core::ops::Deref for CMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMODE` writer - Communication Mode"] +pub struct CMODE_W<'a> { + w: &'a mut W, +} +impl<'a> CMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMODE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Asynchronous Communication"] + #[inline(always)] + pub fn async_(self) -> &'a mut W { + self.variant(CMODE_A::ASYNC) + } + #[doc = "Synchronous Communication"] + #[inline(always)] + pub fn sync(self) -> &'a mut W { + self.variant(CMODE_A::SYNC) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Clock Polarity\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CPOL_A { + #[doc = "0: TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge"] + IDLE_LOW = 0, + #[doc = "1: TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge"] + IDLE_HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CPOL_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CPOL` reader - Clock Polarity"] +pub struct CPOL_R(crate::FieldReader); +impl CPOL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPOL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CPOL_A { + match self.bits { + false => CPOL_A::IDLE_LOW, + true => CPOL_A::IDLE_HIGH, + } + } + #[doc = "Checks if the value of the field is `IDLE_LOW`"] + #[inline(always)] + pub fn is_idle_low(&self) -> bool { + **self == CPOL_A::IDLE_LOW + } + #[doc = "Checks if the value of the field is `IDLE_HIGH`"] + #[inline(always)] + pub fn is_idle_high(&self) -> bool { + **self == CPOL_A::IDLE_HIGH + } +} +impl core::ops::Deref for CPOL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPOL` writer - Clock Polarity"] +pub struct CPOL_W<'a> { + w: &'a mut W, +} +impl<'a> CPOL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CPOL_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge"] + #[inline(always)] + pub fn idle_low(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_LOW) + } + #[doc = "TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge"] + #[inline(always)] + pub fn idle_high(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_HIGH) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29); + self.w + } +} +#[doc = "Data Order\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum DORD_A { + #[doc = "0: MSB is transmitted first"] + MSB = 0, + #[doc = "1: LSB is transmitted first"] + LSB = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DORD_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DORD` reader - Data Order"] +pub struct DORD_R(crate::FieldReader); +impl DORD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DORD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DORD_A { + match self.bits { + false => DORD_A::MSB, + true => DORD_A::LSB, + } + } + #[doc = "Checks if the value of the field is `MSB`"] + #[inline(always)] + pub fn is_msb(&self) -> bool { + **self == DORD_A::MSB + } + #[doc = "Checks if the value of the field is `LSB`"] + #[inline(always)] + pub fn is_lsb(&self) -> bool { + **self == DORD_A::LSB + } +} +impl core::ops::Deref for DORD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DORD` writer - Data Order"] +pub struct DORD_W<'a> { + w: &'a mut W, +} +impl<'a> DORD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DORD_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "MSB is transmitted first"] + #[inline(always)] + pub fn msb(self) -> &'a mut W { + self.variant(DORD_A::MSB) + } + #[doc = "LSB is transmitted first"] + #[inline(always)] + pub fn lsb(self) -> &'a mut W { + self.variant(DORD_A::LSB) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x07) as u8) + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&self) -> IBON_R { + IBON_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bits 13:15 - Sample"] + #[inline(always)] + pub fn sampr(&self) -> SAMPR_R { + SAMPR_R::new(((self.bits >> 13) & 0x07) as u8) + } + #[doc = "Bits 16:17 - Transmit Data Pinout"] + #[inline(always)] + pub fn txpo(&self) -> TXPO_R { + TXPO_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bits 20:21 - Receive Data Pinout"] + #[inline(always)] + pub fn rxpo(&self) -> RXPO_R { + RXPO_R::new(((self.bits >> 20) & 0x03) as u8) + } + #[doc = "Bits 22:23 - Sample Adjustment"] + #[inline(always)] + pub fn sampa(&self) -> SAMPA_R { + SAMPA_R::new(((self.bits >> 22) & 0x03) as u8) + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&self) -> FORM_R { + FORM_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 28 - Communication Mode"] + #[inline(always)] + pub fn cmode(&self) -> CMODE_R { + CMODE_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&self) -> CPOL_R { + CPOL_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&self) -> DORD_R { + DORD_R::new(((self.bits >> 30) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&mut self) -> IBON_W { + IBON_W { w: self } + } + #[doc = "Bits 13:15 - Sample"] + #[inline(always)] + pub fn sampr(&mut self) -> SAMPR_W { + SAMPR_W { w: self } + } + #[doc = "Bits 16:17 - Transmit Data Pinout"] + #[inline(always)] + pub fn txpo(&mut self) -> TXPO_W { + TXPO_W { w: self } + } + #[doc = "Bits 20:21 - Receive Data Pinout"] + #[inline(always)] + pub fn rxpo(&mut self) -> RXPO_W { + RXPO_W { w: self } + } + #[doc = "Bits 22:23 - Sample Adjustment"] + #[inline(always)] + pub fn sampa(&mut self) -> SAMPA_W { + SAMPA_W { w: self } + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&mut self) -> FORM_W { + FORM_W { w: self } + } + #[doc = "Bit 28 - Communication Mode"] + #[inline(always)] + pub fn cmode(&mut self) -> CMODE_W { + CMODE_W { w: self } + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&mut self) -> CPOL_W { + CPOL_W { w: self } + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&mut self) -> DORD_W { + DORD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/sercom0/usart_ext/ctrlb.rs b/pac/atsamc20g/src/sercom0/usart_ext/ctrlb.rs new file mode 100644 index 000000000000..37567555e842 --- /dev/null +++ b/pac/atsamc20g/src/sercom0/usart_ext/ctrlb.rs @@ -0,0 +1,651 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Character Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CHSIZE_A { + #[doc = "0: 8 Bits"] + _8_BIT = 0, + #[doc = "1: 9 Bits"] + _9_BIT = 1, + #[doc = "5: 5 Bits"] + _5_BIT = 5, + #[doc = "6: 6 Bits"] + _6_BIT = 6, + #[doc = "7: 7 Bits"] + _7_BIT = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CHSIZE_A) -> Self { + variant as _ + } +} +#[doc = "Field `CHSIZE` reader - Character Size"] +pub struct CHSIZE_R(crate::FieldReader); +impl CHSIZE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CHSIZE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CHSIZE_A::_8_BIT), + 1 => Some(CHSIZE_A::_9_BIT), + 5 => Some(CHSIZE_A::_5_BIT), + 6 => Some(CHSIZE_A::_6_BIT), + 7 => Some(CHSIZE_A::_7_BIT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_8_BIT`"] + #[inline(always)] + pub fn is_8_bit(&self) -> bool { + **self == CHSIZE_A::_8_BIT + } + #[doc = "Checks if the value of the field is `_9_BIT`"] + #[inline(always)] + pub fn is_9_bit(&self) -> bool { + **self == CHSIZE_A::_9_BIT + } + #[doc = "Checks if the value of the field is `_5_BIT`"] + #[inline(always)] + pub fn is_5_bit(&self) -> bool { + **self == CHSIZE_A::_5_BIT + } + #[doc = "Checks if the value of the field is `_6_BIT`"] + #[inline(always)] + pub fn is_6_bit(&self) -> bool { + **self == CHSIZE_A::_6_BIT + } + #[doc = "Checks if the value of the field is `_7_BIT`"] + #[inline(always)] + pub fn is_7_bit(&self) -> bool { + **self == CHSIZE_A::_7_BIT + } +} +impl core::ops::Deref for CHSIZE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHSIZE` writer - Character Size"] +pub struct CHSIZE_W<'a> { + w: &'a mut W, +} +impl<'a> CHSIZE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CHSIZE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8 Bits"] + #[inline(always)] + pub fn _8_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_8_BIT) + } + #[doc = "9 Bits"] + #[inline(always)] + pub fn _9_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_9_BIT) + } + #[doc = "5 Bits"] + #[inline(always)] + pub fn _5_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_5_BIT) + } + #[doc = "6 Bits"] + #[inline(always)] + pub fn _6_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_6_BIT) + } + #[doc = "7 Bits"] + #[inline(always)] + pub fn _7_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_7_BIT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Stop Bit Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SBMODE_A { + #[doc = "0: One Stop Bit"] + _1_BIT = 0, + #[doc = "1: Two Stop Bits"] + _2_BIT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SBMODE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SBMODE` reader - Stop Bit Mode"] +pub struct SBMODE_R(crate::FieldReader); +impl SBMODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SBMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SBMODE_A { + match self.bits { + false => SBMODE_A::_1_BIT, + true => SBMODE_A::_2_BIT, + } + } + #[doc = "Checks if the value of the field is `_1_BIT`"] + #[inline(always)] + pub fn is_1_bit(&self) -> bool { + **self == SBMODE_A::_1_BIT + } + #[doc = "Checks if the value of the field is `_2_BIT`"] + #[inline(always)] + pub fn is_2_bit(&self) -> bool { + **self == SBMODE_A::_2_BIT + } +} +impl core::ops::Deref for SBMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SBMODE` writer - Stop Bit Mode"] +pub struct SBMODE_W<'a> { + w: &'a mut W, +} +impl<'a> SBMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SBMODE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "One Stop Bit"] + #[inline(always)] + pub fn _1_bit(self) -> &'a mut W { + self.variant(SBMODE_A::_1_BIT) + } + #[doc = "Two Stop Bits"] + #[inline(always)] + pub fn _2_bit(self) -> &'a mut W { + self.variant(SBMODE_A::_2_BIT) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `COLDEN` reader - Collision Detection Enable"] +pub struct COLDEN_R(crate::FieldReader); +impl COLDEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COLDEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COLDEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COLDEN` writer - Collision Detection Enable"] +pub struct COLDEN_W<'a> { + w: &'a mut W, +} +impl<'a> COLDEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `SFDE` reader - Start of Frame Detection Enable"] +pub struct SFDE_R(crate::FieldReader); +impl SFDE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SFDE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SFDE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SFDE` writer - Start of Frame Detection Enable"] +pub struct SFDE_W<'a> { + w: &'a mut W, +} +impl<'a> SFDE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `ENC` reader - Encoding Format"] +pub struct ENC_R(crate::FieldReader); +impl ENC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENC` writer - Encoding Format"] +pub struct ENC_W<'a> { + w: &'a mut W, +} +impl<'a> ENC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Parity Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PMODE_A { + #[doc = "0: Even Parity"] + EVEN = 0, + #[doc = "1: Odd Parity"] + ODD = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PMODE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PMODE` reader - Parity Mode"] +pub struct PMODE_R(crate::FieldReader); +impl PMODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PMODE_A { + match self.bits { + false => PMODE_A::EVEN, + true => PMODE_A::ODD, + } + } + #[doc = "Checks if the value of the field is `EVEN`"] + #[inline(always)] + pub fn is_even(&self) -> bool { + **self == PMODE_A::EVEN + } + #[doc = "Checks if the value of the field is `ODD`"] + #[inline(always)] + pub fn is_odd(&self) -> bool { + **self == PMODE_A::ODD + } +} +impl core::ops::Deref for PMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PMODE` writer - Parity Mode"] +pub struct PMODE_W<'a> { + w: &'a mut W, +} +impl<'a> PMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PMODE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Even Parity"] + #[inline(always)] + pub fn even(self) -> &'a mut W { + self.variant(PMODE_A::EVEN) + } + #[doc = "Odd Parity"] + #[inline(always)] + pub fn odd(self) -> &'a mut W { + self.variant(PMODE_A::ODD) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `TXEN` reader - Transmitter Enable"] +pub struct TXEN_R(crate::FieldReader); +impl TXEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXEN` writer - Transmitter Enable"] +pub struct TXEN_W<'a> { + w: &'a mut W, +} +impl<'a> TXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `RXEN` reader - Receiver Enable"] +pub struct RXEN_R(crate::FieldReader); +impl RXEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXEN` writer - Receiver Enable"] +pub struct RXEN_W<'a> { + w: &'a mut W, +} +impl<'a> RXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `LINCMD` reader - LIN Command"] +pub struct LINCMD_R(crate::FieldReader); +impl LINCMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LINCMD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LINCMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LINCMD` writer - LIN Command"] +pub struct LINCMD_W<'a> { + w: &'a mut W, +} +impl<'a> LINCMD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 24)) | ((value as u32 & 0x03) << 24); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&self) -> CHSIZE_R { + CHSIZE_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 6 - Stop Bit Mode"] + #[inline(always)] + pub fn sbmode(&self) -> SBMODE_R { + SBMODE_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 8 - Collision Detection Enable"] + #[inline(always)] + pub fn colden(&self) -> COLDEN_R { + COLDEN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Start of Frame Detection Enable"] + #[inline(always)] + pub fn sfde(&self) -> SFDE_R { + SFDE_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Encoding Format"] + #[inline(always)] + pub fn enc(&self) -> ENC_R { + ENC_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 13 - Parity Mode"] + #[inline(always)] + pub fn pmode(&self) -> PMODE_R { + PMODE_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 16 - Transmitter Enable"] + #[inline(always)] + pub fn txen(&self) -> TXEN_R { + TXEN_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&self) -> RXEN_R { + RXEN_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bits 24:25 - LIN Command"] + #[inline(always)] + pub fn lincmd(&self) -> LINCMD_R { + LINCMD_R::new(((self.bits >> 24) & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&mut self) -> CHSIZE_W { + CHSIZE_W { w: self } + } + #[doc = "Bit 6 - Stop Bit Mode"] + #[inline(always)] + pub fn sbmode(&mut self) -> SBMODE_W { + SBMODE_W { w: self } + } + #[doc = "Bit 8 - Collision Detection Enable"] + #[inline(always)] + pub fn colden(&mut self) -> COLDEN_W { + COLDEN_W { w: self } + } + #[doc = "Bit 9 - Start of Frame Detection Enable"] + #[inline(always)] + pub fn sfde(&mut self) -> SFDE_W { + SFDE_W { w: self } + } + #[doc = "Bit 10 - Encoding Format"] + #[inline(always)] + pub fn enc(&mut self) -> ENC_W { + ENC_W { w: self } + } + #[doc = "Bit 13 - Parity Mode"] + #[inline(always)] + pub fn pmode(&mut self) -> PMODE_W { + PMODE_W { w: self } + } + #[doc = "Bit 16 - Transmitter Enable"] + #[inline(always)] + pub fn txen(&mut self) -> TXEN_W { + TXEN_W { w: self } + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&mut self) -> RXEN_W { + RXEN_W { w: self } + } + #[doc = "Bits 24:25 - LIN Command"] + #[inline(always)] + pub fn lincmd(&mut self) -> LINCMD_W { + LINCMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/sercom0/usart_ext/ctrlc.rs b/pac/atsamc20g/src/sercom0/usart_ext/ctrlc.rs new file mode 100644 index 000000000000..5840d5c3bd06 --- /dev/null +++ b/pac/atsamc20g/src/sercom0/usart_ext/ctrlc.rs @@ -0,0 +1,177 @@ +#[doc = "Register `CTRLC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `GTIME` reader - RS485 Guard Time"] +pub struct GTIME_R(crate::FieldReader); +impl GTIME_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + GTIME_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GTIME_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GTIME` writer - RS485 Guard Time"] +pub struct GTIME_W<'a> { + w: &'a mut W, +} +impl<'a> GTIME_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Field `BRKLEN` reader - LIN Master Break Length"] +pub struct BRKLEN_R(crate::FieldReader); +impl BRKLEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BRKLEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BRKLEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BRKLEN` writer - LIN Master Break Length"] +pub struct BRKLEN_W<'a> { + w: &'a mut W, +} +impl<'a> BRKLEN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 8)) | ((value as u32 & 0x03) << 8); + self.w + } +} +#[doc = "Field `HDRDLY` reader - LIN Master Header Delay"] +pub struct HDRDLY_R(crate::FieldReader); +impl HDRDLY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + HDRDLY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HDRDLY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HDRDLY` writer - LIN Master Header Delay"] +pub struct HDRDLY_W<'a> { + w: &'a mut W, +} +impl<'a> HDRDLY_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 10)) | ((value as u32 & 0x03) << 10); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - RS485 Guard Time"] + #[inline(always)] + pub fn gtime(&self) -> GTIME_R { + GTIME_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bits 8:9 - LIN Master Break Length"] + #[inline(always)] + pub fn brklen(&self) -> BRKLEN_R { + BRKLEN_R::new(((self.bits >> 8) & 0x03) as u8) + } + #[doc = "Bits 10:11 - LIN Master Header Delay"] + #[inline(always)] + pub fn hdrdly(&self) -> HDRDLY_R { + HDRDLY_R::new(((self.bits >> 10) & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - RS485 Guard Time"] + #[inline(always)] + pub fn gtime(&mut self) -> GTIME_W { + GTIME_W { w: self } + } + #[doc = "Bits 8:9 - LIN Master Break Length"] + #[inline(always)] + pub fn brklen(&mut self) -> BRKLEN_W { + BRKLEN_W { w: self } + } + #[doc = "Bits 10:11 - LIN Master Header Delay"] + #[inline(always)] + pub fn hdrdly(&mut self) -> HDRDLY_W { + HDRDLY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Control C\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlc](index.html) module"] +pub struct CTRLC_SPEC; +impl crate::RegisterSpec for CTRLC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlc::R](R) reader structure"] +impl crate::Readable for CTRLC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlc::W](W) writer structure"] +impl crate::Writable for CTRLC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLC to value 0"] +impl crate::Resettable for CTRLC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/sercom0/usart_ext/data.rs b/pac/atsamc20g/src/sercom0/usart_ext/data.rs new file mode 100644 index 000000000000..a54152c9571a --- /dev/null +++ b/pac/atsamc20g/src/sercom0/usart_ext/data.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data Value"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data Value"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01ff) | (value as u16 & 0x01ff); + self.w + } +} +impl R { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new((self.bits & 0x01ff) as u16) + } +} +impl W { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/sercom0/usart_ext/dbgctrl.rs b/pac/atsamc20g/src/sercom0/usart_ext/dbgctrl.rs new file mode 100644 index 000000000000..6c844f3fe40d --- /dev/null +++ b/pac/atsamc20g/src/sercom0/usart_ext/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGSTOP` reader - Debug Mode"] +pub struct DBGSTOP_R(crate::FieldReader); +impl DBGSTOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGSTOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGSTOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGSTOP` writer - Debug Mode"] +pub struct DBGSTOP_W<'a> { + w: &'a mut W, +} +impl<'a> DBGSTOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&self) -> DBGSTOP_R { + DBGSTOP_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&mut self) -> DBGSTOP_W { + DBGSTOP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/sercom0/usart_ext/intenclr.rs b/pac/atsamc20g/src/sercom0/usart_ext/intenclr.rs new file mode 100644 index 000000000000..a815553ce666 --- /dev/null +++ b/pac/atsamc20g/src/sercom0/usart_ext/intenclr.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Disable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Disable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Disable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Disable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Disable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Disable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RXS` reader - Receive Start Interrupt Disable"] +pub struct RXS_R(crate::FieldReader); +impl RXS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXS` writer - Receive Start Interrupt Disable"] +pub struct RXS_W<'a> { + w: &'a mut W, +} +impl<'a> RXS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CTSIC` reader - Clear To Send Input Change Interrupt Disable"] +pub struct CTSIC_R(crate::FieldReader); +impl CTSIC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTSIC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTSIC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTSIC` writer - Clear To Send Input Change Interrupt Disable"] +pub struct CTSIC_W<'a> { + w: &'a mut W, +} +impl<'a> CTSIC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RXBRK` reader - Break Received Interrupt Disable"] +pub struct RXBRK_R(crate::FieldReader); +impl RXBRK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXBRK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXBRK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXBRK` writer - Break Received Interrupt Disable"] +pub struct RXBRK_W<'a> { + w: &'a mut W, +} +impl<'a> RXBRK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Disable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Disable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Receive Start Interrupt Disable"] + #[inline(always)] + pub fn rxs(&self) -> RXS_R { + RXS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Disable"] + #[inline(always)] + pub fn ctsic(&self) -> CTSIC_R { + CTSIC_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Break Received Interrupt Disable"] + #[inline(always)] + pub fn rxbrk(&self) -> RXBRK_R { + RXBRK_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Receive Start Interrupt Disable"] + #[inline(always)] + pub fn rxs(&mut self) -> RXS_W { + RXS_W { w: self } + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Disable"] + #[inline(always)] + pub fn ctsic(&mut self) -> CTSIC_W { + CTSIC_W { w: self } + } + #[doc = "Bit 5 - Break Received Interrupt Disable"] + #[inline(always)] + pub fn rxbrk(&mut self) -> RXBRK_W { + RXBRK_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/sercom0/usart_ext/intenset.rs b/pac/atsamc20g/src/sercom0/usart_ext/intenset.rs new file mode 100644 index 000000000000..e800681cf423 --- /dev/null +++ b/pac/atsamc20g/src/sercom0/usart_ext/intenset.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Enable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Enable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Enable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Enable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Enable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Enable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RXS` reader - Receive Start Interrupt Enable"] +pub struct RXS_R(crate::FieldReader); +impl RXS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXS` writer - Receive Start Interrupt Enable"] +pub struct RXS_W<'a> { + w: &'a mut W, +} +impl<'a> RXS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CTSIC` reader - Clear To Send Input Change Interrupt Enable"] +pub struct CTSIC_R(crate::FieldReader); +impl CTSIC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTSIC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTSIC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTSIC` writer - Clear To Send Input Change Interrupt Enable"] +pub struct CTSIC_W<'a> { + w: &'a mut W, +} +impl<'a> CTSIC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RXBRK` reader - Break Received Interrupt Enable"] +pub struct RXBRK_R(crate::FieldReader); +impl RXBRK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXBRK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXBRK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXBRK` writer - Break Received Interrupt Enable"] +pub struct RXBRK_W<'a> { + w: &'a mut W, +} +impl<'a> RXBRK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Receive Start Interrupt Enable"] + #[inline(always)] + pub fn rxs(&self) -> RXS_R { + RXS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Enable"] + #[inline(always)] + pub fn ctsic(&self) -> CTSIC_R { + CTSIC_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Break Received Interrupt Enable"] + #[inline(always)] + pub fn rxbrk(&self) -> RXBRK_R { + RXBRK_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Receive Start Interrupt Enable"] + #[inline(always)] + pub fn rxs(&mut self) -> RXS_W { + RXS_W { w: self } + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Enable"] + #[inline(always)] + pub fn ctsic(&mut self) -> CTSIC_W { + CTSIC_W { w: self } + } + #[doc = "Bit 5 - Break Received Interrupt Enable"] + #[inline(always)] + pub fn rxbrk(&mut self) -> RXBRK_W { + RXBRK_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/sercom0/usart_ext/intflag.rs b/pac/atsamc20g/src/sercom0/usart_ext/intflag.rs new file mode 100644 index 000000000000..4b0be279a9ae --- /dev/null +++ b/pac/atsamc20g/src/sercom0/usart_ext/intflag.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RXS` reader - Receive Start Interrupt"] +pub struct RXS_R(crate::FieldReader); +impl RXS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXS` writer - Receive Start Interrupt"] +pub struct RXS_W<'a> { + w: &'a mut W, +} +impl<'a> RXS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CTSIC` reader - Clear To Send Input Change Interrupt"] +pub struct CTSIC_R(crate::FieldReader); +impl CTSIC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTSIC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTSIC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTSIC` writer - Clear To Send Input Change Interrupt"] +pub struct CTSIC_W<'a> { + w: &'a mut W, +} +impl<'a> CTSIC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RXBRK` reader - Break Received Interrupt"] +pub struct RXBRK_R(crate::FieldReader); +impl RXBRK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXBRK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXBRK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXBRK` writer - Break Received Interrupt"] +pub struct RXBRK_W<'a> { + w: &'a mut W, +} +impl<'a> RXBRK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Receive Start Interrupt"] + #[inline(always)] + pub fn rxs(&self) -> RXS_R { + RXS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt"] + #[inline(always)] + pub fn ctsic(&self) -> CTSIC_R { + CTSIC_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Break Received Interrupt"] + #[inline(always)] + pub fn rxbrk(&self) -> RXBRK_R { + RXBRK_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Receive Start Interrupt"] + #[inline(always)] + pub fn rxs(&mut self) -> RXS_W { + RXS_W { w: self } + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt"] + #[inline(always)] + pub fn ctsic(&mut self) -> CTSIC_W { + CTSIC_W { w: self } + } + #[doc = "Bit 5 - Break Received Interrupt"] + #[inline(always)] + pub fn rxbrk(&mut self) -> RXBRK_W { + RXBRK_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/sercom0/usart_ext/rxpl.rs b/pac/atsamc20g/src/sercom0/usart_ext/rxpl.rs new file mode 100644 index 000000000000..174464dc16b5 --- /dev/null +++ b/pac/atsamc20g/src/sercom0/usart_ext/rxpl.rs @@ -0,0 +1,103 @@ +#[doc = "Register `RXPL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RXPL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RXPL` reader - Receive Pulse Length"] +pub struct RXPL_R(crate::FieldReader); +impl RXPL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RXPL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXPL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXPL` writer - Receive Pulse Length"] +pub struct RXPL_W<'a> { + w: &'a mut W, +} +impl<'a> RXPL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Receive Pulse Length"] + #[inline(always)] + pub fn rxpl(&self) -> RXPL_R { + RXPL_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Receive Pulse Length"] + #[inline(always)] + pub fn rxpl(&mut self) -> RXPL_W { + RXPL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Receive Pulse Length\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxpl](index.html) module"] +pub struct RXPL_SPEC; +impl crate::RegisterSpec for RXPL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [rxpl::R](R) reader structure"] +impl crate::Readable for RXPL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rxpl::W](W) writer structure"] +impl crate::Writable for RXPL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RXPL to value 0"] +impl crate::Resettable for RXPL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/sercom0/usart_ext/status.rs b/pac/atsamc20g/src/sercom0/usart_ext/status.rs new file mode 100644 index 000000000000..a0c50c1bc2cf --- /dev/null +++ b/pac/atsamc20g/src/sercom0/usart_ext/status.rs @@ -0,0 +1,395 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PERR` reader - Parity Error"] +pub struct PERR_R(crate::FieldReader); +impl PERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERR` writer - Parity Error"] +pub struct PERR_W<'a> { + w: &'a mut W, +} +impl<'a> PERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `FERR` reader - Frame Error"] +pub struct FERR_R(crate::FieldReader); +impl FERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FERR` writer - Frame Error"] +pub struct FERR_W<'a> { + w: &'a mut W, +} +impl<'a> FERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `BUFOVF` reader - Buffer Overflow"] +pub struct BUFOVF_R(crate::FieldReader); +impl BUFOVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUFOVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUFOVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUFOVF` writer - Buffer Overflow"] +pub struct BUFOVF_W<'a> { + w: &'a mut W, +} +impl<'a> BUFOVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CTS` reader - Clear To Send"] +pub struct CTS_R(crate::FieldReader); +impl CTS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTS` writer - Clear To Send"] +pub struct CTS_W<'a> { + w: &'a mut W, +} +impl<'a> CTS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ISF` reader - Inconsistent Sync Field"] +pub struct ISF_R(crate::FieldReader); +impl ISF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ISF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ISF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ISF` writer - Inconsistent Sync Field"] +pub struct ISF_W<'a> { + w: &'a mut W, +} +impl<'a> ISF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `COLL` reader - Collision Detected"] +pub struct COLL_R(crate::FieldReader); +impl COLL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COLL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COLL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COLL` writer - Collision Detected"] +pub struct COLL_W<'a> { + w: &'a mut W, +} +impl<'a> COLL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `TXE` reader - Transmitter Empty"] +pub struct TXE_R(crate::FieldReader); +impl TXE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXE` writer - Transmitter Empty"] +pub struct TXE_W<'a> { + w: &'a mut W, +} +impl<'a> TXE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - Parity Error"] + #[inline(always)] + pub fn perr(&self) -> PERR_R { + PERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Frame Error"] + #[inline(always)] + pub fn ferr(&self) -> FERR_R { + FERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&self) -> BUFOVF_R { + BUFOVF_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Clear To Send"] + #[inline(always)] + pub fn cts(&self) -> CTS_R { + CTS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Inconsistent Sync Field"] + #[inline(always)] + pub fn isf(&self) -> ISF_R { + ISF_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Collision Detected"] + #[inline(always)] + pub fn coll(&self) -> COLL_R { + COLL_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Transmitter Empty"] + #[inline(always)] + pub fn txe(&self) -> TXE_R { + TXE_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Parity Error"] + #[inline(always)] + pub fn perr(&mut self) -> PERR_W { + PERR_W { w: self } + } + #[doc = "Bit 1 - Frame Error"] + #[inline(always)] + pub fn ferr(&mut self) -> FERR_W { + FERR_W { w: self } + } + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&mut self) -> BUFOVF_W { + BUFOVF_W { w: self } + } + #[doc = "Bit 3 - Clear To Send"] + #[inline(always)] + pub fn cts(&mut self) -> CTS_W { + CTS_W { w: self } + } + #[doc = "Bit 4 - Inconsistent Sync Field"] + #[inline(always)] + pub fn isf(&mut self) -> ISF_W { + ISF_W { w: self } + } + #[doc = "Bit 5 - Collision Detected"] + #[inline(always)] + pub fn coll(&mut self) -> COLL_W { + COLL_W { w: self } + } + #[doc = "Bit 6 - Transmitter Empty"] + #[inline(always)] + pub fn txe(&mut self) -> TXE_W { + TXE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/sercom0/usart_ext/syncbusy.rs b/pac/atsamc20g/src/sercom0/usart_ext/syncbusy.rs new file mode 100644 index 000000000000..7c3b817bbb04 --- /dev/null +++ b/pac/atsamc20g/src/sercom0/usart_ext/syncbusy.rs @@ -0,0 +1,93 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - SERCOM Enable Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLB` reader - CTRLB Synchronization Busy"] +pub struct CTRLB_R(crate::FieldReader); +impl CTRLB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM Enable Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - CTRLB Synchronization Busy"] + #[inline(always)] + pub fn ctrlb(&self) -> CTRLB_R { + CTRLB_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +#[doc = "USART_EXT Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/sercom0/usart_int.rs b/pac/atsamc20g/src/sercom0/usart_int.rs new file mode 100644 index 000000000000..157c8c4b4fdc --- /dev/null +++ b/pac/atsamc20g/src/sercom0/usart_int.rs @@ -0,0 +1,60 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "USART_INT Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "USART_INT Control B"] +pub mod ctrlb; +#[doc = "CTRLC register accessor: an alias for `Reg`"] +pub type CTRLC = crate::Reg; +#[doc = "USART_INT Control C"] +pub mod ctrlc; +#[doc = "BAUD register accessor: an alias for `Reg`"] +pub type BAUD = crate::Reg; +#[doc = "USART_INT Baud Rate"] +pub mod baud; +#[doc = "BAUD_FRAC_MODE register accessor: an alias for `Reg`"] +pub type BAUD_FRAC_MODE = crate::Reg; +#[doc = "USART_INT Baud Rate"] +pub mod baud_frac_mode; +#[doc = "BAUD_FRACFP_MODE register accessor: an alias for `Reg`"] +pub type BAUD_FRACFP_MODE = crate::Reg; +#[doc = "USART_INT Baud Rate"] +pub mod baud_fracfp_mode; +#[doc = "BAUD_USARTFP_MODE register accessor: an alias for `Reg`"] +pub type BAUD_USARTFP_MODE = crate::Reg; +#[doc = "USART_INT Baud Rate"] +pub mod baud_usartfp_mode; +#[doc = "RXPL register accessor: an alias for `Reg`"] +pub type RXPL = crate::Reg; +#[doc = "USART_INT Receive Pulse Length"] +pub mod rxpl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "USART_INT Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "USART_INT Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "USART_INT Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "USART_INT Status"] +pub mod status; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "USART_INT Synchronization Busy"] +pub mod syncbusy; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "USART_INT Data"] +pub mod data; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "USART_INT Debug Control"] +pub mod dbgctrl; diff --git a/pac/atsamc20g/src/sercom0/usart_int/baud.rs b/pac/atsamc20g/src/sercom0/usart_int/baud.rs new file mode 100644 index 000000000000..a82df20712b3 --- /dev/null +++ b/pac/atsamc20g/src/sercom0/usart_int/baud.rs @@ -0,0 +1,103 @@ +#[doc = "Register `BAUD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud](index.html) module"] +pub struct BAUD_SPEC; +impl crate::RegisterSpec for BAUD_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud::R](R) reader structure"] +impl crate::Readable for BAUD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud::W](W) writer structure"] +impl crate::Writable for BAUD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD to value 0"] +impl crate::Resettable for BAUD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/sercom0/usart_int/baud_frac_mode.rs b/pac/atsamc20g/src/sercom0/usart_int/baud_frac_mode.rs new file mode 100644 index 000000000000..b9c7fa4c4b2a --- /dev/null +++ b/pac/atsamc20g/src/sercom0/usart_int/baud_frac_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `BAUD_FRAC_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD_FRAC_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1fff) | (value as u16 & 0x1fff); + self.w + } +} +#[doc = "Field `FP` reader - Fractional Part"] +pub struct FP_R(crate::FieldReader); +impl FP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FP` writer - Fractional Part"] +pub struct FP_W<'a> { + w: &'a mut W, +} +impl<'a> FP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 13)) | ((value as u16 & 0x07) << 13); + self.w + } +} +impl R { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new((self.bits & 0x1fff) as u16) + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&self) -> FP_R { + FP_R::new(((self.bits >> 13) & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&mut self) -> FP_W { + FP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud_frac_mode](index.html) module"] +pub struct BAUD_FRAC_MODE_SPEC; +impl crate::RegisterSpec for BAUD_FRAC_MODE_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud_frac_mode::R](R) reader structure"] +impl crate::Readable for BAUD_FRAC_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud_frac_mode::W](W) writer structure"] +impl crate::Writable for BAUD_FRAC_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD_FRAC_MODE to value 0"] +impl crate::Resettable for BAUD_FRAC_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/sercom0/usart_int/baud_fracfp_mode.rs b/pac/atsamc20g/src/sercom0/usart_int/baud_fracfp_mode.rs new file mode 100644 index 000000000000..0671db99cc9d --- /dev/null +++ b/pac/atsamc20g/src/sercom0/usart_int/baud_fracfp_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `BAUD_FRACFP_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD_FRACFP_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1fff) | (value as u16 & 0x1fff); + self.w + } +} +#[doc = "Field `FP` reader - Fractional Part"] +pub struct FP_R(crate::FieldReader); +impl FP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FP` writer - Fractional Part"] +pub struct FP_W<'a> { + w: &'a mut W, +} +impl<'a> FP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 13)) | ((value as u16 & 0x07) << 13); + self.w + } +} +impl R { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new((self.bits & 0x1fff) as u16) + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&self) -> FP_R { + FP_R::new(((self.bits >> 13) & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&mut self) -> FP_W { + FP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud_fracfp_mode](index.html) module"] +pub struct BAUD_FRACFP_MODE_SPEC; +impl crate::RegisterSpec for BAUD_FRACFP_MODE_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud_fracfp_mode::R](R) reader structure"] +impl crate::Readable for BAUD_FRACFP_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud_fracfp_mode::W](W) writer structure"] +impl crate::Writable for BAUD_FRACFP_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD_FRACFP_MODE to value 0"] +impl crate::Resettable for BAUD_FRACFP_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/sercom0/usart_int/baud_usartfp_mode.rs b/pac/atsamc20g/src/sercom0/usart_int/baud_usartfp_mode.rs new file mode 100644 index 000000000000..b49a7ef5b84c --- /dev/null +++ b/pac/atsamc20g/src/sercom0/usart_int/baud_usartfp_mode.rs @@ -0,0 +1,103 @@ +#[doc = "Register `BAUD_USARTFP_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD_USARTFP_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud_usartfp_mode](index.html) module"] +pub struct BAUD_USARTFP_MODE_SPEC; +impl crate::RegisterSpec for BAUD_USARTFP_MODE_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud_usartfp_mode::R](R) reader structure"] +impl crate::Readable for BAUD_USARTFP_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud_usartfp_mode::W](W) writer structure"] +impl crate::Writable for BAUD_USARTFP_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD_USARTFP_MODE to value 0"] +impl crate::Resettable for BAUD_USARTFP_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/sercom0/usart_int/ctrla.rs b/pac/atsamc20g/src/sercom0/usart_int/ctrla.rs new file mode 100644 index 000000000000..19d10ecf8e8f --- /dev/null +++ b/pac/atsamc20g/src/sercom0/usart_int/ctrla.rs @@ -0,0 +1,1171 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: USART with external clock"] + USART_EXT_CLK = 0, + #[doc = "1: USART with internal clock"] + USART_INT_CLK = 1, + #[doc = "2: SPI in slave operation"] + SPI_SLAVE = 2, + #[doc = "3: SPI in master operation"] + SPI_MASTER = 3, + #[doc = "4: I2C slave operation"] + I2C_SLAVE = 4, + #[doc = "5: I2C master operation"] + I2C_MASTER = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::USART_EXT_CLK), + 1 => Some(MODE_A::USART_INT_CLK), + 2 => Some(MODE_A::SPI_SLAVE), + 3 => Some(MODE_A::SPI_MASTER), + 4 => Some(MODE_A::I2C_SLAVE), + 5 => Some(MODE_A::I2C_MASTER), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_EXT_CLK`"] + #[inline(always)] + pub fn is_usart_ext_clk(&self) -> bool { + **self == MODE_A::USART_EXT_CLK + } + #[doc = "Checks if the value of the field is `USART_INT_CLK`"] + #[inline(always)] + pub fn is_usart_int_clk(&self) -> bool { + **self == MODE_A::USART_INT_CLK + } + #[doc = "Checks if the value of the field is `SPI_SLAVE`"] + #[inline(always)] + pub fn is_spi_slave(&self) -> bool { + **self == MODE_A::SPI_SLAVE + } + #[doc = "Checks if the value of the field is `SPI_MASTER`"] + #[inline(always)] + pub fn is_spi_master(&self) -> bool { + **self == MODE_A::SPI_MASTER + } + #[doc = "Checks if the value of the field is `I2C_SLAVE`"] + #[inline(always)] + pub fn is_i2c_slave(&self) -> bool { + **self == MODE_A::I2C_SLAVE + } + #[doc = "Checks if the value of the field is `I2C_MASTER`"] + #[inline(always)] + pub fn is_i2c_master(&self) -> bool { + **self == MODE_A::I2C_MASTER + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART with external clock"] + #[inline(always)] + pub fn usart_ext_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_EXT_CLK) + } + #[doc = "USART with internal clock"] + #[inline(always)] + pub fn usart_int_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_INT_CLK) + } + #[doc = "SPI in slave operation"] + #[inline(always)] + pub fn spi_slave(self) -> &'a mut W { + self.variant(MODE_A::SPI_SLAVE) + } + #[doc = "SPI in master operation"] + #[inline(always)] + pub fn spi_master(self) -> &'a mut W { + self.variant(MODE_A::SPI_MASTER) + } + #[doc = "I2C slave operation"] + #[inline(always)] + pub fn i2c_slave(self) -> &'a mut W { + self.variant(MODE_A::I2C_SLAVE) + } + #[doc = "I2C master operation"] + #[inline(always)] + pub fn i2c_master(self) -> &'a mut W { + self.variant(MODE_A::I2C_MASTER) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 2)) | ((value as u32 & 0x07) << 2); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `IBON` reader - Immediate Buffer Overflow Notification"] +pub struct IBON_R(crate::FieldReader); +impl IBON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IBON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IBON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IBON` writer - Immediate Buffer Overflow Notification"] +pub struct IBON_W<'a> { + w: &'a mut W, +} +impl<'a> IBON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Sample\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SAMPR_A { + #[doc = "0: 16x over-sampling using arithmetic baudrate generation"] + _16X_ARITHMETIC = 0, + #[doc = "1: 16x over-sampling using fractional baudrate generation"] + _16X_FRACTIONAL = 1, + #[doc = "2: 8x over-sampling using arithmetic baudrate generation"] + _8X_ARITHMETIC = 2, + #[doc = "3: 8x over-sampling using fractional baudrate generation"] + _8X_FRACTIONAL = 3, + #[doc = "4: 3x over-sampling using arithmetic baudrate generation"] + _3X_ARITHMETIC = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SAMPR_A) -> Self { + variant as _ + } +} +#[doc = "Field `SAMPR` reader - Sample"] +pub struct SAMPR_R(crate::FieldReader); +impl SAMPR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SAMPR_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SAMPR_A::_16X_ARITHMETIC), + 1 => Some(SAMPR_A::_16X_FRACTIONAL), + 2 => Some(SAMPR_A::_8X_ARITHMETIC), + 3 => Some(SAMPR_A::_8X_FRACTIONAL), + 4 => Some(SAMPR_A::_3X_ARITHMETIC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_16X_ARITHMETIC`"] + #[inline(always)] + pub fn is_16x_arithmetic(&self) -> bool { + **self == SAMPR_A::_16X_ARITHMETIC + } + #[doc = "Checks if the value of the field is `_16X_FRACTIONAL`"] + #[inline(always)] + pub fn is_16x_fractional(&self) -> bool { + **self == SAMPR_A::_16X_FRACTIONAL + } + #[doc = "Checks if the value of the field is `_8X_ARITHMETIC`"] + #[inline(always)] + pub fn is_8x_arithmetic(&self) -> bool { + **self == SAMPR_A::_8X_ARITHMETIC + } + #[doc = "Checks if the value of the field is `_8X_FRACTIONAL`"] + #[inline(always)] + pub fn is_8x_fractional(&self) -> bool { + **self == SAMPR_A::_8X_FRACTIONAL + } + #[doc = "Checks if the value of the field is `_3X_ARITHMETIC`"] + #[inline(always)] + pub fn is_3x_arithmetic(&self) -> bool { + **self == SAMPR_A::_3X_ARITHMETIC + } +} +impl core::ops::Deref for SAMPR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SAMPR` writer - Sample"] +pub struct SAMPR_W<'a> { + w: &'a mut W, +} +impl<'a> SAMPR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SAMPR_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "16x over-sampling using arithmetic baudrate generation"] + #[inline(always)] + pub fn _16x_arithmetic(self) -> &'a mut W { + self.variant(SAMPR_A::_16X_ARITHMETIC) + } + #[doc = "16x over-sampling using fractional baudrate generation"] + #[inline(always)] + pub fn _16x_fractional(self) -> &'a mut W { + self.variant(SAMPR_A::_16X_FRACTIONAL) + } + #[doc = "8x over-sampling using arithmetic baudrate generation"] + #[inline(always)] + pub fn _8x_arithmetic(self) -> &'a mut W { + self.variant(SAMPR_A::_8X_ARITHMETIC) + } + #[doc = "8x over-sampling using fractional baudrate generation"] + #[inline(always)] + pub fn _8x_fractional(self) -> &'a mut W { + self.variant(SAMPR_A::_8X_FRACTIONAL) + } + #[doc = "3x over-sampling using arithmetic baudrate generation"] + #[inline(always)] + pub fn _3x_arithmetic(self) -> &'a mut W { + self.variant(SAMPR_A::_3X_ARITHMETIC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 13)) | ((value as u32 & 0x07) << 13); + self.w + } +} +#[doc = "Transmit Data Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum TXPO_A { + #[doc = "0: SERCOM PAD\\[0\\] +is used for data transmission"] + PAD0 = 0, + #[doc = "1: SERCOM PAD\\[2\\] +is used for data transmission"] + PAD2 = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: TXPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `TXPO` reader - Transmit Data Pinout"] +pub struct TXPO_R(crate::FieldReader); +impl TXPO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TXPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(TXPO_A::PAD0), + 1 => Some(TXPO_A::PAD2), + _ => None, + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == TXPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == TXPO_A::PAD2 + } +} +impl core::ops::Deref for TXPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXPO` writer - Transmit Data Pinout"] +pub struct TXPO_W<'a> { + w: &'a mut W, +} +impl<'a> TXPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TXPO_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "SERCOM PAD\\[0\\] +is used for data transmission"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(TXPO_A::PAD0) + } + #[doc = "SERCOM PAD\\[2\\] +is used for data transmission"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(TXPO_A::PAD2) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Receive Data Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum RXPO_A { + #[doc = "0: SERCOM PAD\\[0\\] +is used for data reception"] + PAD0 = 0, + #[doc = "1: SERCOM PAD\\[1\\] +is used for data reception"] + PAD1 = 1, + #[doc = "2: SERCOM PAD\\[2\\] +is used for data reception"] + PAD2 = 2, + #[doc = "3: SERCOM PAD\\[3\\] +is used for data reception"] + PAD3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RXPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `RXPO` reader - Receive Data Pinout"] +pub struct RXPO_R(crate::FieldReader); +impl RXPO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RXPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RXPO_A { + match self.bits { + 0 => RXPO_A::PAD0, + 1 => RXPO_A::PAD1, + 2 => RXPO_A::PAD2, + 3 => RXPO_A::PAD3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == RXPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD1`"] + #[inline(always)] + pub fn is_pad1(&self) -> bool { + **self == RXPO_A::PAD1 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == RXPO_A::PAD2 + } + #[doc = "Checks if the value of the field is `PAD3`"] + #[inline(always)] + pub fn is_pad3(&self) -> bool { + **self == RXPO_A::PAD3 + } +} +impl core::ops::Deref for RXPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXPO` writer - Receive Data Pinout"] +pub struct RXPO_W<'a> { + w: &'a mut W, +} +impl<'a> RXPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RXPO_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "SERCOM PAD\\[0\\] +is used for data reception"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(RXPO_A::PAD0) + } + #[doc = "SERCOM PAD\\[1\\] +is used for data reception"] + #[inline(always)] + pub fn pad1(self) -> &'a mut W { + self.variant(RXPO_A::PAD1) + } + #[doc = "SERCOM PAD\\[2\\] +is used for data reception"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(RXPO_A::PAD2) + } + #[doc = "SERCOM PAD\\[3\\] +is used for data reception"] + #[inline(always)] + pub fn pad3(self) -> &'a mut W { + self.variant(RXPO_A::PAD3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 20)) | ((value as u32 & 0x03) << 20); + self.w + } +} +#[doc = "Field `SAMPA` reader - Sample Adjustment"] +pub struct SAMPA_R(crate::FieldReader); +impl SAMPA_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SAMPA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SAMPA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SAMPA` writer - Sample Adjustment"] +pub struct SAMPA_W<'a> { + w: &'a mut W, +} +impl<'a> SAMPA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 22)) | ((value as u32 & 0x03) << 22); + self.w + } +} +#[doc = "Frame Format\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FORM_A { + #[doc = "0: USART frame"] + USART_FRAME_NO_PARITY = 0, + #[doc = "1: USART frame with parity"] + USART_FRAME_WITH_PARITY = 1, + #[doc = "2: LIN Master - Break and sync generation"] + USART_FRAME_LIN_MASTER_MODE = 2, + #[doc = "4: Auto-baud - break detection and auto-baud"] + USART_FRAME_AUTO_BAUD_NO_PARITY = 4, + #[doc = "5: Auto-baud - break detection and auto-baud with parity"] + USART_FRAME_AUTO_BAUD_WITH_PARITY = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FORM_A) -> Self { + variant as _ + } +} +#[doc = "Field `FORM` reader - Frame Format"] +pub struct FORM_R(crate::FieldReader); +impl FORM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FORM_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(FORM_A::USART_FRAME_NO_PARITY), + 1 => Some(FORM_A::USART_FRAME_WITH_PARITY), + 2 => Some(FORM_A::USART_FRAME_LIN_MASTER_MODE), + 4 => Some(FORM_A::USART_FRAME_AUTO_BAUD_NO_PARITY), + 5 => Some(FORM_A::USART_FRAME_AUTO_BAUD_WITH_PARITY), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_FRAME_NO_PARITY`"] + #[inline(always)] + pub fn is_usart_frame_no_parity(&self) -> bool { + **self == FORM_A::USART_FRAME_NO_PARITY + } + #[doc = "Checks if the value of the field is `USART_FRAME_WITH_PARITY`"] + #[inline(always)] + pub fn is_usart_frame_with_parity(&self) -> bool { + **self == FORM_A::USART_FRAME_WITH_PARITY + } + #[doc = "Checks if the value of the field is `USART_FRAME_LIN_MASTER_MODE`"] + #[inline(always)] + pub fn is_usart_frame_lin_master_mode(&self) -> bool { + **self == FORM_A::USART_FRAME_LIN_MASTER_MODE + } + #[doc = "Checks if the value of the field is `USART_FRAME_AUTO_BAUD_NO_PARITY`"] + #[inline(always)] + pub fn is_usart_frame_auto_baud_no_parity(&self) -> bool { + **self == FORM_A::USART_FRAME_AUTO_BAUD_NO_PARITY + } + #[doc = "Checks if the value of the field is `USART_FRAME_AUTO_BAUD_WITH_PARITY`"] + #[inline(always)] + pub fn is_usart_frame_auto_baud_with_parity(&self) -> bool { + **self == FORM_A::USART_FRAME_AUTO_BAUD_WITH_PARITY + } +} +impl core::ops::Deref for FORM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FORM` writer - Frame Format"] +pub struct FORM_W<'a> { + w: &'a mut W, +} +impl<'a> FORM_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FORM_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART frame"] + #[inline(always)] + pub fn usart_frame_no_parity(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_NO_PARITY) + } + #[doc = "USART frame with parity"] + #[inline(always)] + pub fn usart_frame_with_parity(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_WITH_PARITY) + } + #[doc = "LIN Master - Break and sync generation"] + #[inline(always)] + pub fn usart_frame_lin_master_mode(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_LIN_MASTER_MODE) + } + #[doc = "Auto-baud - break detection and auto-baud"] + #[inline(always)] + pub fn usart_frame_auto_baud_no_parity(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_AUTO_BAUD_NO_PARITY) + } + #[doc = "Auto-baud - break detection and auto-baud with parity"] + #[inline(always)] + pub fn usart_frame_auto_baud_with_parity(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_AUTO_BAUD_WITH_PARITY) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Communication Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CMODE_A { + #[doc = "0: Asynchronous Communication"] + ASYNC = 0, + #[doc = "1: Synchronous Communication"] + SYNC = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CMODE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CMODE` reader - Communication Mode"] +pub struct CMODE_R(crate::FieldReader); +impl CMODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CMODE_A { + match self.bits { + false => CMODE_A::ASYNC, + true => CMODE_A::SYNC, + } + } + #[doc = "Checks if the value of the field is `ASYNC`"] + #[inline(always)] + pub fn is_async(&self) -> bool { + **self == CMODE_A::ASYNC + } + #[doc = "Checks if the value of the field is `SYNC`"] + #[inline(always)] + pub fn is_sync(&self) -> bool { + **self == CMODE_A::SYNC + } +} +impl core::ops::Deref for CMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMODE` writer - Communication Mode"] +pub struct CMODE_W<'a> { + w: &'a mut W, +} +impl<'a> CMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMODE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Asynchronous Communication"] + #[inline(always)] + pub fn async_(self) -> &'a mut W { + self.variant(CMODE_A::ASYNC) + } + #[doc = "Synchronous Communication"] + #[inline(always)] + pub fn sync(self) -> &'a mut W { + self.variant(CMODE_A::SYNC) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Clock Polarity\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CPOL_A { + #[doc = "0: TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge"] + IDLE_LOW = 0, + #[doc = "1: TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge"] + IDLE_HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CPOL_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CPOL` reader - Clock Polarity"] +pub struct CPOL_R(crate::FieldReader); +impl CPOL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPOL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CPOL_A { + match self.bits { + false => CPOL_A::IDLE_LOW, + true => CPOL_A::IDLE_HIGH, + } + } + #[doc = "Checks if the value of the field is `IDLE_LOW`"] + #[inline(always)] + pub fn is_idle_low(&self) -> bool { + **self == CPOL_A::IDLE_LOW + } + #[doc = "Checks if the value of the field is `IDLE_HIGH`"] + #[inline(always)] + pub fn is_idle_high(&self) -> bool { + **self == CPOL_A::IDLE_HIGH + } +} +impl core::ops::Deref for CPOL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPOL` writer - Clock Polarity"] +pub struct CPOL_W<'a> { + w: &'a mut W, +} +impl<'a> CPOL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CPOL_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge"] + #[inline(always)] + pub fn idle_low(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_LOW) + } + #[doc = "TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge"] + #[inline(always)] + pub fn idle_high(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_HIGH) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29); + self.w + } +} +#[doc = "Data Order\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum DORD_A { + #[doc = "0: MSB is transmitted first"] + MSB = 0, + #[doc = "1: LSB is transmitted first"] + LSB = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DORD_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DORD` reader - Data Order"] +pub struct DORD_R(crate::FieldReader); +impl DORD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DORD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DORD_A { + match self.bits { + false => DORD_A::MSB, + true => DORD_A::LSB, + } + } + #[doc = "Checks if the value of the field is `MSB`"] + #[inline(always)] + pub fn is_msb(&self) -> bool { + **self == DORD_A::MSB + } + #[doc = "Checks if the value of the field is `LSB`"] + #[inline(always)] + pub fn is_lsb(&self) -> bool { + **self == DORD_A::LSB + } +} +impl core::ops::Deref for DORD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DORD` writer - Data Order"] +pub struct DORD_W<'a> { + w: &'a mut W, +} +impl<'a> DORD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DORD_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "MSB is transmitted first"] + #[inline(always)] + pub fn msb(self) -> &'a mut W { + self.variant(DORD_A::MSB) + } + #[doc = "LSB is transmitted first"] + #[inline(always)] + pub fn lsb(self) -> &'a mut W { + self.variant(DORD_A::LSB) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x07) as u8) + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&self) -> IBON_R { + IBON_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bits 13:15 - Sample"] + #[inline(always)] + pub fn sampr(&self) -> SAMPR_R { + SAMPR_R::new(((self.bits >> 13) & 0x07) as u8) + } + #[doc = "Bits 16:17 - Transmit Data Pinout"] + #[inline(always)] + pub fn txpo(&self) -> TXPO_R { + TXPO_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bits 20:21 - Receive Data Pinout"] + #[inline(always)] + pub fn rxpo(&self) -> RXPO_R { + RXPO_R::new(((self.bits >> 20) & 0x03) as u8) + } + #[doc = "Bits 22:23 - Sample Adjustment"] + #[inline(always)] + pub fn sampa(&self) -> SAMPA_R { + SAMPA_R::new(((self.bits >> 22) & 0x03) as u8) + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&self) -> FORM_R { + FORM_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 28 - Communication Mode"] + #[inline(always)] + pub fn cmode(&self) -> CMODE_R { + CMODE_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&self) -> CPOL_R { + CPOL_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&self) -> DORD_R { + DORD_R::new(((self.bits >> 30) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&mut self) -> IBON_W { + IBON_W { w: self } + } + #[doc = "Bits 13:15 - Sample"] + #[inline(always)] + pub fn sampr(&mut self) -> SAMPR_W { + SAMPR_W { w: self } + } + #[doc = "Bits 16:17 - Transmit Data Pinout"] + #[inline(always)] + pub fn txpo(&mut self) -> TXPO_W { + TXPO_W { w: self } + } + #[doc = "Bits 20:21 - Receive Data Pinout"] + #[inline(always)] + pub fn rxpo(&mut self) -> RXPO_W { + RXPO_W { w: self } + } + #[doc = "Bits 22:23 - Sample Adjustment"] + #[inline(always)] + pub fn sampa(&mut self) -> SAMPA_W { + SAMPA_W { w: self } + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&mut self) -> FORM_W { + FORM_W { w: self } + } + #[doc = "Bit 28 - Communication Mode"] + #[inline(always)] + pub fn cmode(&mut self) -> CMODE_W { + CMODE_W { w: self } + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&mut self) -> CPOL_W { + CPOL_W { w: self } + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&mut self) -> DORD_W { + DORD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/sercom0/usart_int/ctrlb.rs b/pac/atsamc20g/src/sercom0/usart_int/ctrlb.rs new file mode 100644 index 000000000000..d556e0c3cfc2 --- /dev/null +++ b/pac/atsamc20g/src/sercom0/usart_int/ctrlb.rs @@ -0,0 +1,651 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Character Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CHSIZE_A { + #[doc = "0: 8 Bits"] + _8_BIT = 0, + #[doc = "1: 9 Bits"] + _9_BIT = 1, + #[doc = "5: 5 Bits"] + _5_BIT = 5, + #[doc = "6: 6 Bits"] + _6_BIT = 6, + #[doc = "7: 7 Bits"] + _7_BIT = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CHSIZE_A) -> Self { + variant as _ + } +} +#[doc = "Field `CHSIZE` reader - Character Size"] +pub struct CHSIZE_R(crate::FieldReader); +impl CHSIZE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CHSIZE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CHSIZE_A::_8_BIT), + 1 => Some(CHSIZE_A::_9_BIT), + 5 => Some(CHSIZE_A::_5_BIT), + 6 => Some(CHSIZE_A::_6_BIT), + 7 => Some(CHSIZE_A::_7_BIT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_8_BIT`"] + #[inline(always)] + pub fn is_8_bit(&self) -> bool { + **self == CHSIZE_A::_8_BIT + } + #[doc = "Checks if the value of the field is `_9_BIT`"] + #[inline(always)] + pub fn is_9_bit(&self) -> bool { + **self == CHSIZE_A::_9_BIT + } + #[doc = "Checks if the value of the field is `_5_BIT`"] + #[inline(always)] + pub fn is_5_bit(&self) -> bool { + **self == CHSIZE_A::_5_BIT + } + #[doc = "Checks if the value of the field is `_6_BIT`"] + #[inline(always)] + pub fn is_6_bit(&self) -> bool { + **self == CHSIZE_A::_6_BIT + } + #[doc = "Checks if the value of the field is `_7_BIT`"] + #[inline(always)] + pub fn is_7_bit(&self) -> bool { + **self == CHSIZE_A::_7_BIT + } +} +impl core::ops::Deref for CHSIZE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHSIZE` writer - Character Size"] +pub struct CHSIZE_W<'a> { + w: &'a mut W, +} +impl<'a> CHSIZE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CHSIZE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8 Bits"] + #[inline(always)] + pub fn _8_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_8_BIT) + } + #[doc = "9 Bits"] + #[inline(always)] + pub fn _9_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_9_BIT) + } + #[doc = "5 Bits"] + #[inline(always)] + pub fn _5_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_5_BIT) + } + #[doc = "6 Bits"] + #[inline(always)] + pub fn _6_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_6_BIT) + } + #[doc = "7 Bits"] + #[inline(always)] + pub fn _7_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_7_BIT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Stop Bit Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SBMODE_A { + #[doc = "0: One Stop Bit"] + _1_BIT = 0, + #[doc = "1: Two Stop Bits"] + _2_BIT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SBMODE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SBMODE` reader - Stop Bit Mode"] +pub struct SBMODE_R(crate::FieldReader); +impl SBMODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SBMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SBMODE_A { + match self.bits { + false => SBMODE_A::_1_BIT, + true => SBMODE_A::_2_BIT, + } + } + #[doc = "Checks if the value of the field is `_1_BIT`"] + #[inline(always)] + pub fn is_1_bit(&self) -> bool { + **self == SBMODE_A::_1_BIT + } + #[doc = "Checks if the value of the field is `_2_BIT`"] + #[inline(always)] + pub fn is_2_bit(&self) -> bool { + **self == SBMODE_A::_2_BIT + } +} +impl core::ops::Deref for SBMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SBMODE` writer - Stop Bit Mode"] +pub struct SBMODE_W<'a> { + w: &'a mut W, +} +impl<'a> SBMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SBMODE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "One Stop Bit"] + #[inline(always)] + pub fn _1_bit(self) -> &'a mut W { + self.variant(SBMODE_A::_1_BIT) + } + #[doc = "Two Stop Bits"] + #[inline(always)] + pub fn _2_bit(self) -> &'a mut W { + self.variant(SBMODE_A::_2_BIT) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `COLDEN` reader - Collision Detection Enable"] +pub struct COLDEN_R(crate::FieldReader); +impl COLDEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COLDEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COLDEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COLDEN` writer - Collision Detection Enable"] +pub struct COLDEN_W<'a> { + w: &'a mut W, +} +impl<'a> COLDEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `SFDE` reader - Start of Frame Detection Enable"] +pub struct SFDE_R(crate::FieldReader); +impl SFDE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SFDE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SFDE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SFDE` writer - Start of Frame Detection Enable"] +pub struct SFDE_W<'a> { + w: &'a mut W, +} +impl<'a> SFDE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `ENC` reader - Encoding Format"] +pub struct ENC_R(crate::FieldReader); +impl ENC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENC` writer - Encoding Format"] +pub struct ENC_W<'a> { + w: &'a mut W, +} +impl<'a> ENC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Parity Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PMODE_A { + #[doc = "0: Even Parity"] + EVEN = 0, + #[doc = "1: Odd Parity"] + ODD = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PMODE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PMODE` reader - Parity Mode"] +pub struct PMODE_R(crate::FieldReader); +impl PMODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PMODE_A { + match self.bits { + false => PMODE_A::EVEN, + true => PMODE_A::ODD, + } + } + #[doc = "Checks if the value of the field is `EVEN`"] + #[inline(always)] + pub fn is_even(&self) -> bool { + **self == PMODE_A::EVEN + } + #[doc = "Checks if the value of the field is `ODD`"] + #[inline(always)] + pub fn is_odd(&self) -> bool { + **self == PMODE_A::ODD + } +} +impl core::ops::Deref for PMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PMODE` writer - Parity Mode"] +pub struct PMODE_W<'a> { + w: &'a mut W, +} +impl<'a> PMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PMODE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Even Parity"] + #[inline(always)] + pub fn even(self) -> &'a mut W { + self.variant(PMODE_A::EVEN) + } + #[doc = "Odd Parity"] + #[inline(always)] + pub fn odd(self) -> &'a mut W { + self.variant(PMODE_A::ODD) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `TXEN` reader - Transmitter Enable"] +pub struct TXEN_R(crate::FieldReader); +impl TXEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXEN` writer - Transmitter Enable"] +pub struct TXEN_W<'a> { + w: &'a mut W, +} +impl<'a> TXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `RXEN` reader - Receiver Enable"] +pub struct RXEN_R(crate::FieldReader); +impl RXEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXEN` writer - Receiver Enable"] +pub struct RXEN_W<'a> { + w: &'a mut W, +} +impl<'a> RXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `LINCMD` reader - LIN Command"] +pub struct LINCMD_R(crate::FieldReader); +impl LINCMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LINCMD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LINCMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LINCMD` writer - LIN Command"] +pub struct LINCMD_W<'a> { + w: &'a mut W, +} +impl<'a> LINCMD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 24)) | ((value as u32 & 0x03) << 24); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&self) -> CHSIZE_R { + CHSIZE_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 6 - Stop Bit Mode"] + #[inline(always)] + pub fn sbmode(&self) -> SBMODE_R { + SBMODE_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 8 - Collision Detection Enable"] + #[inline(always)] + pub fn colden(&self) -> COLDEN_R { + COLDEN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Start of Frame Detection Enable"] + #[inline(always)] + pub fn sfde(&self) -> SFDE_R { + SFDE_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Encoding Format"] + #[inline(always)] + pub fn enc(&self) -> ENC_R { + ENC_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 13 - Parity Mode"] + #[inline(always)] + pub fn pmode(&self) -> PMODE_R { + PMODE_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 16 - Transmitter Enable"] + #[inline(always)] + pub fn txen(&self) -> TXEN_R { + TXEN_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&self) -> RXEN_R { + RXEN_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bits 24:25 - LIN Command"] + #[inline(always)] + pub fn lincmd(&self) -> LINCMD_R { + LINCMD_R::new(((self.bits >> 24) & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&mut self) -> CHSIZE_W { + CHSIZE_W { w: self } + } + #[doc = "Bit 6 - Stop Bit Mode"] + #[inline(always)] + pub fn sbmode(&mut self) -> SBMODE_W { + SBMODE_W { w: self } + } + #[doc = "Bit 8 - Collision Detection Enable"] + #[inline(always)] + pub fn colden(&mut self) -> COLDEN_W { + COLDEN_W { w: self } + } + #[doc = "Bit 9 - Start of Frame Detection Enable"] + #[inline(always)] + pub fn sfde(&mut self) -> SFDE_W { + SFDE_W { w: self } + } + #[doc = "Bit 10 - Encoding Format"] + #[inline(always)] + pub fn enc(&mut self) -> ENC_W { + ENC_W { w: self } + } + #[doc = "Bit 13 - Parity Mode"] + #[inline(always)] + pub fn pmode(&mut self) -> PMODE_W { + PMODE_W { w: self } + } + #[doc = "Bit 16 - Transmitter Enable"] + #[inline(always)] + pub fn txen(&mut self) -> TXEN_W { + TXEN_W { w: self } + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&mut self) -> RXEN_W { + RXEN_W { w: self } + } + #[doc = "Bits 24:25 - LIN Command"] + #[inline(always)] + pub fn lincmd(&mut self) -> LINCMD_W { + LINCMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/sercom0/usart_int/ctrlc.rs b/pac/atsamc20g/src/sercom0/usart_int/ctrlc.rs new file mode 100644 index 000000000000..e2182cc7f768 --- /dev/null +++ b/pac/atsamc20g/src/sercom0/usart_int/ctrlc.rs @@ -0,0 +1,177 @@ +#[doc = "Register `CTRLC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `GTIME` reader - RS485 Guard Time"] +pub struct GTIME_R(crate::FieldReader); +impl GTIME_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + GTIME_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GTIME_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GTIME` writer - RS485 Guard Time"] +pub struct GTIME_W<'a> { + w: &'a mut W, +} +impl<'a> GTIME_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Field `BRKLEN` reader - LIN Master Break Length"] +pub struct BRKLEN_R(crate::FieldReader); +impl BRKLEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BRKLEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BRKLEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BRKLEN` writer - LIN Master Break Length"] +pub struct BRKLEN_W<'a> { + w: &'a mut W, +} +impl<'a> BRKLEN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 8)) | ((value as u32 & 0x03) << 8); + self.w + } +} +#[doc = "Field `HDRDLY` reader - LIN Master Header Delay"] +pub struct HDRDLY_R(crate::FieldReader); +impl HDRDLY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + HDRDLY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HDRDLY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HDRDLY` writer - LIN Master Header Delay"] +pub struct HDRDLY_W<'a> { + w: &'a mut W, +} +impl<'a> HDRDLY_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 10)) | ((value as u32 & 0x03) << 10); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - RS485 Guard Time"] + #[inline(always)] + pub fn gtime(&self) -> GTIME_R { + GTIME_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bits 8:9 - LIN Master Break Length"] + #[inline(always)] + pub fn brklen(&self) -> BRKLEN_R { + BRKLEN_R::new(((self.bits >> 8) & 0x03) as u8) + } + #[doc = "Bits 10:11 - LIN Master Header Delay"] + #[inline(always)] + pub fn hdrdly(&self) -> HDRDLY_R { + HDRDLY_R::new(((self.bits >> 10) & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - RS485 Guard Time"] + #[inline(always)] + pub fn gtime(&mut self) -> GTIME_W { + GTIME_W { w: self } + } + #[doc = "Bits 8:9 - LIN Master Break Length"] + #[inline(always)] + pub fn brklen(&mut self) -> BRKLEN_W { + BRKLEN_W { w: self } + } + #[doc = "Bits 10:11 - LIN Master Header Delay"] + #[inline(always)] + pub fn hdrdly(&mut self) -> HDRDLY_W { + HDRDLY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Control C\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlc](index.html) module"] +pub struct CTRLC_SPEC; +impl crate::RegisterSpec for CTRLC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlc::R](R) reader structure"] +impl crate::Readable for CTRLC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlc::W](W) writer structure"] +impl crate::Writable for CTRLC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLC to value 0"] +impl crate::Resettable for CTRLC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/sercom0/usart_int/data.rs b/pac/atsamc20g/src/sercom0/usart_int/data.rs new file mode 100644 index 000000000000..19d74c337d44 --- /dev/null +++ b/pac/atsamc20g/src/sercom0/usart_int/data.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data Value"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data Value"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01ff) | (value as u16 & 0x01ff); + self.w + } +} +impl R { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new((self.bits & 0x01ff) as u16) + } +} +impl W { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/sercom0/usart_int/dbgctrl.rs b/pac/atsamc20g/src/sercom0/usart_int/dbgctrl.rs new file mode 100644 index 000000000000..0ac5b9c7b902 --- /dev/null +++ b/pac/atsamc20g/src/sercom0/usart_int/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGSTOP` reader - Debug Mode"] +pub struct DBGSTOP_R(crate::FieldReader); +impl DBGSTOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGSTOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGSTOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGSTOP` writer - Debug Mode"] +pub struct DBGSTOP_W<'a> { + w: &'a mut W, +} +impl<'a> DBGSTOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&self) -> DBGSTOP_R { + DBGSTOP_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&mut self) -> DBGSTOP_W { + DBGSTOP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/sercom0/usart_int/intenclr.rs b/pac/atsamc20g/src/sercom0/usart_int/intenclr.rs new file mode 100644 index 000000000000..5ad23ad15636 --- /dev/null +++ b/pac/atsamc20g/src/sercom0/usart_int/intenclr.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Disable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Disable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Disable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Disable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Disable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Disable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RXS` reader - Receive Start Interrupt Disable"] +pub struct RXS_R(crate::FieldReader); +impl RXS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXS` writer - Receive Start Interrupt Disable"] +pub struct RXS_W<'a> { + w: &'a mut W, +} +impl<'a> RXS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CTSIC` reader - Clear To Send Input Change Interrupt Disable"] +pub struct CTSIC_R(crate::FieldReader); +impl CTSIC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTSIC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTSIC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTSIC` writer - Clear To Send Input Change Interrupt Disable"] +pub struct CTSIC_W<'a> { + w: &'a mut W, +} +impl<'a> CTSIC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RXBRK` reader - Break Received Interrupt Disable"] +pub struct RXBRK_R(crate::FieldReader); +impl RXBRK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXBRK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXBRK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXBRK` writer - Break Received Interrupt Disable"] +pub struct RXBRK_W<'a> { + w: &'a mut W, +} +impl<'a> RXBRK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Disable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Disable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Receive Start Interrupt Disable"] + #[inline(always)] + pub fn rxs(&self) -> RXS_R { + RXS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Disable"] + #[inline(always)] + pub fn ctsic(&self) -> CTSIC_R { + CTSIC_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Break Received Interrupt Disable"] + #[inline(always)] + pub fn rxbrk(&self) -> RXBRK_R { + RXBRK_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Receive Start Interrupt Disable"] + #[inline(always)] + pub fn rxs(&mut self) -> RXS_W { + RXS_W { w: self } + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Disable"] + #[inline(always)] + pub fn ctsic(&mut self) -> CTSIC_W { + CTSIC_W { w: self } + } + #[doc = "Bit 5 - Break Received Interrupt Disable"] + #[inline(always)] + pub fn rxbrk(&mut self) -> RXBRK_W { + RXBRK_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/sercom0/usart_int/intenset.rs b/pac/atsamc20g/src/sercom0/usart_int/intenset.rs new file mode 100644 index 000000000000..457f440e13e9 --- /dev/null +++ b/pac/atsamc20g/src/sercom0/usart_int/intenset.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Enable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Enable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Enable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Enable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Enable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Enable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RXS` reader - Receive Start Interrupt Enable"] +pub struct RXS_R(crate::FieldReader); +impl RXS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXS` writer - Receive Start Interrupt Enable"] +pub struct RXS_W<'a> { + w: &'a mut W, +} +impl<'a> RXS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CTSIC` reader - Clear To Send Input Change Interrupt Enable"] +pub struct CTSIC_R(crate::FieldReader); +impl CTSIC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTSIC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTSIC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTSIC` writer - Clear To Send Input Change Interrupt Enable"] +pub struct CTSIC_W<'a> { + w: &'a mut W, +} +impl<'a> CTSIC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RXBRK` reader - Break Received Interrupt Enable"] +pub struct RXBRK_R(crate::FieldReader); +impl RXBRK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXBRK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXBRK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXBRK` writer - Break Received Interrupt Enable"] +pub struct RXBRK_W<'a> { + w: &'a mut W, +} +impl<'a> RXBRK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Receive Start Interrupt Enable"] + #[inline(always)] + pub fn rxs(&self) -> RXS_R { + RXS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Enable"] + #[inline(always)] + pub fn ctsic(&self) -> CTSIC_R { + CTSIC_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Break Received Interrupt Enable"] + #[inline(always)] + pub fn rxbrk(&self) -> RXBRK_R { + RXBRK_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Receive Start Interrupt Enable"] + #[inline(always)] + pub fn rxs(&mut self) -> RXS_W { + RXS_W { w: self } + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Enable"] + #[inline(always)] + pub fn ctsic(&mut self) -> CTSIC_W { + CTSIC_W { w: self } + } + #[doc = "Bit 5 - Break Received Interrupt Enable"] + #[inline(always)] + pub fn rxbrk(&mut self) -> RXBRK_W { + RXBRK_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/sercom0/usart_int/intflag.rs b/pac/atsamc20g/src/sercom0/usart_int/intflag.rs new file mode 100644 index 000000000000..a6a26321b8c4 --- /dev/null +++ b/pac/atsamc20g/src/sercom0/usart_int/intflag.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RXS` reader - Receive Start Interrupt"] +pub struct RXS_R(crate::FieldReader); +impl RXS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXS` writer - Receive Start Interrupt"] +pub struct RXS_W<'a> { + w: &'a mut W, +} +impl<'a> RXS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CTSIC` reader - Clear To Send Input Change Interrupt"] +pub struct CTSIC_R(crate::FieldReader); +impl CTSIC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTSIC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTSIC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTSIC` writer - Clear To Send Input Change Interrupt"] +pub struct CTSIC_W<'a> { + w: &'a mut W, +} +impl<'a> CTSIC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RXBRK` reader - Break Received Interrupt"] +pub struct RXBRK_R(crate::FieldReader); +impl RXBRK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXBRK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXBRK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXBRK` writer - Break Received Interrupt"] +pub struct RXBRK_W<'a> { + w: &'a mut W, +} +impl<'a> RXBRK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Receive Start Interrupt"] + #[inline(always)] + pub fn rxs(&self) -> RXS_R { + RXS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt"] + #[inline(always)] + pub fn ctsic(&self) -> CTSIC_R { + CTSIC_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Break Received Interrupt"] + #[inline(always)] + pub fn rxbrk(&self) -> RXBRK_R { + RXBRK_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Receive Start Interrupt"] + #[inline(always)] + pub fn rxs(&mut self) -> RXS_W { + RXS_W { w: self } + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt"] + #[inline(always)] + pub fn ctsic(&mut self) -> CTSIC_W { + CTSIC_W { w: self } + } + #[doc = "Bit 5 - Break Received Interrupt"] + #[inline(always)] + pub fn rxbrk(&mut self) -> RXBRK_W { + RXBRK_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/sercom0/usart_int/rxpl.rs b/pac/atsamc20g/src/sercom0/usart_int/rxpl.rs new file mode 100644 index 000000000000..324cbac371c1 --- /dev/null +++ b/pac/atsamc20g/src/sercom0/usart_int/rxpl.rs @@ -0,0 +1,103 @@ +#[doc = "Register `RXPL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RXPL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RXPL` reader - Receive Pulse Length"] +pub struct RXPL_R(crate::FieldReader); +impl RXPL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RXPL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXPL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXPL` writer - Receive Pulse Length"] +pub struct RXPL_W<'a> { + w: &'a mut W, +} +impl<'a> RXPL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Receive Pulse Length"] + #[inline(always)] + pub fn rxpl(&self) -> RXPL_R { + RXPL_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Receive Pulse Length"] + #[inline(always)] + pub fn rxpl(&mut self) -> RXPL_W { + RXPL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Receive Pulse Length\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxpl](index.html) module"] +pub struct RXPL_SPEC; +impl crate::RegisterSpec for RXPL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [rxpl::R](R) reader structure"] +impl crate::Readable for RXPL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rxpl::W](W) writer structure"] +impl crate::Writable for RXPL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RXPL to value 0"] +impl crate::Resettable for RXPL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/sercom0/usart_int/status.rs b/pac/atsamc20g/src/sercom0/usart_int/status.rs new file mode 100644 index 000000000000..1a92018a359b --- /dev/null +++ b/pac/atsamc20g/src/sercom0/usart_int/status.rs @@ -0,0 +1,395 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PERR` reader - Parity Error"] +pub struct PERR_R(crate::FieldReader); +impl PERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERR` writer - Parity Error"] +pub struct PERR_W<'a> { + w: &'a mut W, +} +impl<'a> PERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `FERR` reader - Frame Error"] +pub struct FERR_R(crate::FieldReader); +impl FERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FERR` writer - Frame Error"] +pub struct FERR_W<'a> { + w: &'a mut W, +} +impl<'a> FERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `BUFOVF` reader - Buffer Overflow"] +pub struct BUFOVF_R(crate::FieldReader); +impl BUFOVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUFOVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUFOVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUFOVF` writer - Buffer Overflow"] +pub struct BUFOVF_W<'a> { + w: &'a mut W, +} +impl<'a> BUFOVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CTS` reader - Clear To Send"] +pub struct CTS_R(crate::FieldReader); +impl CTS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTS` writer - Clear To Send"] +pub struct CTS_W<'a> { + w: &'a mut W, +} +impl<'a> CTS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ISF` reader - Inconsistent Sync Field"] +pub struct ISF_R(crate::FieldReader); +impl ISF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ISF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ISF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ISF` writer - Inconsistent Sync Field"] +pub struct ISF_W<'a> { + w: &'a mut W, +} +impl<'a> ISF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `COLL` reader - Collision Detected"] +pub struct COLL_R(crate::FieldReader); +impl COLL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COLL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COLL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COLL` writer - Collision Detected"] +pub struct COLL_W<'a> { + w: &'a mut W, +} +impl<'a> COLL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `TXE` reader - Transmitter Empty"] +pub struct TXE_R(crate::FieldReader); +impl TXE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXE` writer - Transmitter Empty"] +pub struct TXE_W<'a> { + w: &'a mut W, +} +impl<'a> TXE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - Parity Error"] + #[inline(always)] + pub fn perr(&self) -> PERR_R { + PERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Frame Error"] + #[inline(always)] + pub fn ferr(&self) -> FERR_R { + FERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&self) -> BUFOVF_R { + BUFOVF_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Clear To Send"] + #[inline(always)] + pub fn cts(&self) -> CTS_R { + CTS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Inconsistent Sync Field"] + #[inline(always)] + pub fn isf(&self) -> ISF_R { + ISF_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Collision Detected"] + #[inline(always)] + pub fn coll(&self) -> COLL_R { + COLL_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Transmitter Empty"] + #[inline(always)] + pub fn txe(&self) -> TXE_R { + TXE_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Parity Error"] + #[inline(always)] + pub fn perr(&mut self) -> PERR_W { + PERR_W { w: self } + } + #[doc = "Bit 1 - Frame Error"] + #[inline(always)] + pub fn ferr(&mut self) -> FERR_W { + FERR_W { w: self } + } + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&mut self) -> BUFOVF_W { + BUFOVF_W { w: self } + } + #[doc = "Bit 3 - Clear To Send"] + #[inline(always)] + pub fn cts(&mut self) -> CTS_W { + CTS_W { w: self } + } + #[doc = "Bit 4 - Inconsistent Sync Field"] + #[inline(always)] + pub fn isf(&mut self) -> ISF_W { + ISF_W { w: self } + } + #[doc = "Bit 5 - Collision Detected"] + #[inline(always)] + pub fn coll(&mut self) -> COLL_W { + COLL_W { w: self } + } + #[doc = "Bit 6 - Transmitter Empty"] + #[inline(always)] + pub fn txe(&mut self) -> TXE_W { + TXE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/sercom0/usart_int/syncbusy.rs b/pac/atsamc20g/src/sercom0/usart_int/syncbusy.rs new file mode 100644 index 000000000000..5dea9a5a7bab --- /dev/null +++ b/pac/atsamc20g/src/sercom0/usart_int/syncbusy.rs @@ -0,0 +1,93 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - SERCOM Enable Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLB` reader - CTRLB Synchronization Busy"] +pub struct CTRLB_R(crate::FieldReader); +impl CTRLB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM Enable Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - CTRLB Synchronization Busy"] + #[inline(always)] + pub fn ctrlb(&self) -> CTRLB_R { + CTRLB_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +#[doc = "USART_INT Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/supc.rs b/pac/atsamc20g/src/supc.rs new file mode 100644 index 000000000000..452d8f3f9613 --- /dev/null +++ b/pac/atsamc20g/src/supc.rs @@ -0,0 +1,52 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x04 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x08 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x0c - Power and Clocks Status"] + pub status: crate::Reg, + #[doc = "0x10 - BODVDD Control"] + pub bodvdd: crate::Reg, + #[doc = "0x14 - BODCORE Control"] + pub bodcore: crate::Reg, + #[doc = "0x18 - VREG Control"] + pub vreg: crate::Reg, + #[doc = "0x1c - VREF Control"] + pub vref: crate::Reg, +} +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Power and Clocks Status"] +pub mod status; +#[doc = "BODVDD register accessor: an alias for `Reg`"] +pub type BODVDD = crate::Reg; +#[doc = "BODVDD Control"] +pub mod bodvdd; +#[doc = "BODCORE register accessor: an alias for `Reg`"] +pub type BODCORE = crate::Reg; +#[doc = "BODCORE Control"] +pub mod bodcore; +#[doc = "VREG register accessor: an alias for `Reg`"] +pub type VREG = crate::Reg; +#[doc = "VREG Control"] +pub mod vreg; +#[doc = "VREF register accessor: an alias for `Reg`"] +pub type VREF = crate::Reg; +#[doc = "VREF Control"] +pub mod vref; diff --git a/pac/atsamc20g/src/supc/bodcore.rs b/pac/atsamc20g/src/supc/bodcore.rs new file mode 100644 index 000000000000..670dec8e048c --- /dev/null +++ b/pac/atsamc20g/src/supc/bodcore.rs @@ -0,0 +1,705 @@ +#[doc = "Register `BODCORE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BODCORE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `HYST` reader - Hysteresis Enable"] +pub struct HYST_R(crate::FieldReader); +impl HYST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HYST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HYST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HYST` writer - Hysteresis Enable"] +pub struct HYST_W<'a> { + w: &'a mut W, +} +impl<'a> HYST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Action when Threshold Crossed\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum ACTION_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: The BODCORE generates a reset"] + RESET = 1, + #[doc = "2: The BODCORE generates an interrupt"] + INT = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: ACTION_A) -> Self { + variant as _ + } +} +#[doc = "Field `ACTION` reader - Action when Threshold Crossed"] +pub struct ACTION_R(crate::FieldReader); +impl ACTION_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ACTION_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(ACTION_A::NONE), + 1 => Some(ACTION_A::RESET), + 2 => Some(ACTION_A::INT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == ACTION_A::NONE + } + #[doc = "Checks if the value of the field is `RESET`"] + #[inline(always)] + pub fn is_reset(&self) -> bool { + **self == ACTION_A::RESET + } + #[doc = "Checks if the value of the field is `INT`"] + #[inline(always)] + pub fn is_int(&self) -> bool { + **self == ACTION_A::INT + } +} +impl core::ops::Deref for ACTION_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ACTION` writer - Action when Threshold Crossed"] +pub struct ACTION_W<'a> { + w: &'a mut W, +} +impl<'a> ACTION_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: ACTION_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(ACTION_A::NONE) + } + #[doc = "The BODCORE generates a reset"] + #[inline(always)] + pub fn reset(self) -> &'a mut W { + self.variant(ACTION_A::RESET) + } + #[doc = "The BODCORE generates an interrupt"] + #[inline(always)] + pub fn int(self) -> &'a mut W { + self.variant(ACTION_A::INT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 3)) | ((value as u32 & 0x03) << 3); + self.w + } +} +#[doc = "Field `STDBYCFG` reader - Configuration in Standby mode"] +pub struct STDBYCFG_R(crate::FieldReader); +impl STDBYCFG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STDBYCFG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STDBYCFG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STDBYCFG` writer - Configuration in Standby mode"] +pub struct STDBYCFG_W<'a> { + w: &'a mut W, +} +impl<'a> STDBYCFG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ACTCFG` reader - Configuration in Active mode"] +pub struct ACTCFG_R(crate::FieldReader); +impl ACTCFG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ACTCFG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ACTCFG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ACTCFG` writer - Configuration in Active mode"] +pub struct ACTCFG_W<'a> { + w: &'a mut W, +} +impl<'a> ACTCFG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Prescaler Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PSEL_A { + #[doc = "0: Divide clock by 2"] + DIV2 = 0, + #[doc = "1: Divide clock by 4"] + DIV4 = 1, + #[doc = "2: Divide clock by 8"] + DIV8 = 2, + #[doc = "3: Divide clock by 16"] + DIV16 = 3, + #[doc = "4: Divide clock by 32"] + DIV32 = 4, + #[doc = "5: Divide clock by 64"] + DIV64 = 5, + #[doc = "6: Divide clock by 128"] + DIV128 = 6, + #[doc = "7: Divide clock by 256"] + DIV256 = 7, + #[doc = "8: Divide clock by 512"] + DIV512 = 8, + #[doc = "9: Divide clock by 1024"] + DIV1024 = 9, + #[doc = "10: Divide clock by 2048"] + DIV2048 = 10, + #[doc = "11: Divide clock by 4096"] + DIV4096 = 11, + #[doc = "12: Divide clock by 8192"] + DIV8192 = 12, + #[doc = "13: Divide clock by 16384"] + DIV16384 = 13, + #[doc = "14: Divide clock by 32768"] + DIV32768 = 14, + #[doc = "15: Divide clock by 65536"] + DIV65536 = 15, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `PSEL` reader - Prescaler Select"] +pub struct PSEL_R(crate::FieldReader); +impl PSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PSEL_A { + match self.bits { + 0 => PSEL_A::DIV2, + 1 => PSEL_A::DIV4, + 2 => PSEL_A::DIV8, + 3 => PSEL_A::DIV16, + 4 => PSEL_A::DIV32, + 5 => PSEL_A::DIV64, + 6 => PSEL_A::DIV128, + 7 => PSEL_A::DIV256, + 8 => PSEL_A::DIV512, + 9 => PSEL_A::DIV1024, + 10 => PSEL_A::DIV2048, + 11 => PSEL_A::DIV4096, + 12 => PSEL_A::DIV8192, + 13 => PSEL_A::DIV16384, + 14 => PSEL_A::DIV32768, + 15 => PSEL_A::DIV65536, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PSEL_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PSEL_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PSEL_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PSEL_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == PSEL_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PSEL_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == PSEL_A::DIV128 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PSEL_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV512`"] + #[inline(always)] + pub fn is_div512(&self) -> bool { + **self == PSEL_A::DIV512 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PSEL_A::DIV1024 + } + #[doc = "Checks if the value of the field is `DIV2048`"] + #[inline(always)] + pub fn is_div2048(&self) -> bool { + **self == PSEL_A::DIV2048 + } + #[doc = "Checks if the value of the field is `DIV4096`"] + #[inline(always)] + pub fn is_div4096(&self) -> bool { + **self == PSEL_A::DIV4096 + } + #[doc = "Checks if the value of the field is `DIV8192`"] + #[inline(always)] + pub fn is_div8192(&self) -> bool { + **self == PSEL_A::DIV8192 + } + #[doc = "Checks if the value of the field is `DIV16384`"] + #[inline(always)] + pub fn is_div16384(&self) -> bool { + **self == PSEL_A::DIV16384 + } + #[doc = "Checks if the value of the field is `DIV32768`"] + #[inline(always)] + pub fn is_div32768(&self) -> bool { + **self == PSEL_A::DIV32768 + } + #[doc = "Checks if the value of the field is `DIV65536`"] + #[inline(always)] + pub fn is_div65536(&self) -> bool { + **self == PSEL_A::DIV65536 + } +} +impl core::ops::Deref for PSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PSEL` writer - Prescaler Select"] +pub struct PSEL_W<'a> { + w: &'a mut W, +} +impl<'a> PSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PSEL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Divide clock by 2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PSEL_A::DIV2) + } + #[doc = "Divide clock by 4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PSEL_A::DIV4) + } + #[doc = "Divide clock by 8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PSEL_A::DIV8) + } + #[doc = "Divide clock by 16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PSEL_A::DIV16) + } + #[doc = "Divide clock by 32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(PSEL_A::DIV32) + } + #[doc = "Divide clock by 64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PSEL_A::DIV64) + } + #[doc = "Divide clock by 128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(PSEL_A::DIV128) + } + #[doc = "Divide clock by 256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PSEL_A::DIV256) + } + #[doc = "Divide clock by 512"] + #[inline(always)] + pub fn div512(self) -> &'a mut W { + self.variant(PSEL_A::DIV512) + } + #[doc = "Divide clock by 1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PSEL_A::DIV1024) + } + #[doc = "Divide clock by 2048"] + #[inline(always)] + pub fn div2048(self) -> &'a mut W { + self.variant(PSEL_A::DIV2048) + } + #[doc = "Divide clock by 4096"] + #[inline(always)] + pub fn div4096(self) -> &'a mut W { + self.variant(PSEL_A::DIV4096) + } + #[doc = "Divide clock by 8192"] + #[inline(always)] + pub fn div8192(self) -> &'a mut W { + self.variant(PSEL_A::DIV8192) + } + #[doc = "Divide clock by 16384"] + #[inline(always)] + pub fn div16384(self) -> &'a mut W { + self.variant(PSEL_A::DIV16384) + } + #[doc = "Divide clock by 32768"] + #[inline(always)] + pub fn div32768(self) -> &'a mut W { + self.variant(PSEL_A::DIV32768) + } + #[doc = "Divide clock by 65536"] + #[inline(always)] + pub fn div65536(self) -> &'a mut W { + self.variant(PSEL_A::DIV65536) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 12)) | ((value as u32 & 0x0f) << 12); + self.w + } +} +#[doc = "Field `LEVEL` reader - Threshold Level"] +pub struct LEVEL_R(crate::FieldReader); +impl LEVEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LEVEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LEVEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LEVEL` writer - Threshold Level"] +pub struct LEVEL_W<'a> { + w: &'a mut W, +} +impl<'a> LEVEL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 16)) | ((value as u32 & 0x3f) << 16); + self.w + } +} +impl R { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Hysteresis Enable"] + #[inline(always)] + pub fn hyst(&self) -> HYST_R { + HYST_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 3:4 - Action when Threshold Crossed"] + #[inline(always)] + pub fn action(&self) -> ACTION_R { + ACTION_R::new(((self.bits >> 3) & 0x03) as u8) + } + #[doc = "Bit 5 - Configuration in Standby mode"] + #[inline(always)] + pub fn stdbycfg(&self) -> STDBYCFG_R { + STDBYCFG_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 8 - Configuration in Active mode"] + #[inline(always)] + pub fn actcfg(&self) -> ACTCFG_R { + ACTCFG_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bits 12:15 - Prescaler Select"] + #[inline(always)] + pub fn psel(&self) -> PSEL_R { + PSEL_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:21 - Threshold Level"] + #[inline(always)] + pub fn level(&self) -> LEVEL_R { + LEVEL_R::new(((self.bits >> 16) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - Hysteresis Enable"] + #[inline(always)] + pub fn hyst(&mut self) -> HYST_W { + HYST_W { w: self } + } + #[doc = "Bits 3:4 - Action when Threshold Crossed"] + #[inline(always)] + pub fn action(&mut self) -> ACTION_W { + ACTION_W { w: self } + } + #[doc = "Bit 5 - Configuration in Standby mode"] + #[inline(always)] + pub fn stdbycfg(&mut self) -> STDBYCFG_W { + STDBYCFG_W { w: self } + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 8 - Configuration in Active mode"] + #[inline(always)] + pub fn actcfg(&mut self) -> ACTCFG_W { + ACTCFG_W { w: self } + } + #[doc = "Bits 12:15 - Prescaler Select"] + #[inline(always)] + pub fn psel(&mut self) -> PSEL_W { + PSEL_W { w: self } + } + #[doc = "Bits 16:21 - Threshold Level"] + #[inline(always)] + pub fn level(&mut self) -> LEVEL_W { + LEVEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "BODCORE Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [bodcore](index.html) module"] +pub struct BODCORE_SPEC; +impl crate::RegisterSpec for BODCORE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [bodcore::R](R) reader structure"] +impl crate::Readable for BODCORE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [bodcore::W](W) writer structure"] +impl crate::Writable for BODCORE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BODCORE to value 0"] +impl crate::Resettable for BODCORE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/supc/bodvdd.rs b/pac/atsamc20g/src/supc/bodvdd.rs new file mode 100644 index 000000000000..f5cbfffb6453 --- /dev/null +++ b/pac/atsamc20g/src/supc/bodvdd.rs @@ -0,0 +1,705 @@ +#[doc = "Register `BODVDD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BODVDD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `HYST` reader - Hysteresis Enable"] +pub struct HYST_R(crate::FieldReader); +impl HYST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HYST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HYST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HYST` writer - Hysteresis Enable"] +pub struct HYST_W<'a> { + w: &'a mut W, +} +impl<'a> HYST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Action when Threshold Crossed\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum ACTION_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: The BODVDD generates a reset"] + RESET = 1, + #[doc = "2: The BODVDD generates an interrupt"] + INT = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: ACTION_A) -> Self { + variant as _ + } +} +#[doc = "Field `ACTION` reader - Action when Threshold Crossed"] +pub struct ACTION_R(crate::FieldReader); +impl ACTION_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ACTION_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(ACTION_A::NONE), + 1 => Some(ACTION_A::RESET), + 2 => Some(ACTION_A::INT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == ACTION_A::NONE + } + #[doc = "Checks if the value of the field is `RESET`"] + #[inline(always)] + pub fn is_reset(&self) -> bool { + **self == ACTION_A::RESET + } + #[doc = "Checks if the value of the field is `INT`"] + #[inline(always)] + pub fn is_int(&self) -> bool { + **self == ACTION_A::INT + } +} +impl core::ops::Deref for ACTION_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ACTION` writer - Action when Threshold Crossed"] +pub struct ACTION_W<'a> { + w: &'a mut W, +} +impl<'a> ACTION_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: ACTION_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(ACTION_A::NONE) + } + #[doc = "The BODVDD generates a reset"] + #[inline(always)] + pub fn reset(self) -> &'a mut W { + self.variant(ACTION_A::RESET) + } + #[doc = "The BODVDD generates an interrupt"] + #[inline(always)] + pub fn int(self) -> &'a mut W { + self.variant(ACTION_A::INT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 3)) | ((value as u32 & 0x03) << 3); + self.w + } +} +#[doc = "Field `STDBYCFG` reader - Configuration in Standby mode"] +pub struct STDBYCFG_R(crate::FieldReader); +impl STDBYCFG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STDBYCFG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STDBYCFG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STDBYCFG` writer - Configuration in Standby mode"] +pub struct STDBYCFG_W<'a> { + w: &'a mut W, +} +impl<'a> STDBYCFG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ACTCFG` reader - Configuration in Active mode"] +pub struct ACTCFG_R(crate::FieldReader); +impl ACTCFG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ACTCFG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ACTCFG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ACTCFG` writer - Configuration in Active mode"] +pub struct ACTCFG_W<'a> { + w: &'a mut W, +} +impl<'a> ACTCFG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Prescaler Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PSEL_A { + #[doc = "0: Divide clock by 2"] + DIV2 = 0, + #[doc = "1: Divide clock by 4"] + DIV4 = 1, + #[doc = "2: Divide clock by 8"] + DIV8 = 2, + #[doc = "3: Divide clock by 16"] + DIV16 = 3, + #[doc = "4: Divide clock by 32"] + DIV32 = 4, + #[doc = "5: Divide clock by 64"] + DIV64 = 5, + #[doc = "6: Divide clock by 128"] + DIV128 = 6, + #[doc = "7: Divide clock by 256"] + DIV256 = 7, + #[doc = "8: Divide clock by 512"] + DIV512 = 8, + #[doc = "9: Divide clock by 1024"] + DIV1024 = 9, + #[doc = "10: Divide clock by 2048"] + DIV2048 = 10, + #[doc = "11: Divide clock by 4096"] + DIV4096 = 11, + #[doc = "12: Divide clock by 8192"] + DIV8192 = 12, + #[doc = "13: Divide clock by 16384"] + DIV16384 = 13, + #[doc = "14: Divide clock by 32768"] + DIV32768 = 14, + #[doc = "15: Divide clock by 65536"] + DIV65536 = 15, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `PSEL` reader - Prescaler Select"] +pub struct PSEL_R(crate::FieldReader); +impl PSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PSEL_A { + match self.bits { + 0 => PSEL_A::DIV2, + 1 => PSEL_A::DIV4, + 2 => PSEL_A::DIV8, + 3 => PSEL_A::DIV16, + 4 => PSEL_A::DIV32, + 5 => PSEL_A::DIV64, + 6 => PSEL_A::DIV128, + 7 => PSEL_A::DIV256, + 8 => PSEL_A::DIV512, + 9 => PSEL_A::DIV1024, + 10 => PSEL_A::DIV2048, + 11 => PSEL_A::DIV4096, + 12 => PSEL_A::DIV8192, + 13 => PSEL_A::DIV16384, + 14 => PSEL_A::DIV32768, + 15 => PSEL_A::DIV65536, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PSEL_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PSEL_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PSEL_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PSEL_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == PSEL_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PSEL_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == PSEL_A::DIV128 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PSEL_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV512`"] + #[inline(always)] + pub fn is_div512(&self) -> bool { + **self == PSEL_A::DIV512 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PSEL_A::DIV1024 + } + #[doc = "Checks if the value of the field is `DIV2048`"] + #[inline(always)] + pub fn is_div2048(&self) -> bool { + **self == PSEL_A::DIV2048 + } + #[doc = "Checks if the value of the field is `DIV4096`"] + #[inline(always)] + pub fn is_div4096(&self) -> bool { + **self == PSEL_A::DIV4096 + } + #[doc = "Checks if the value of the field is `DIV8192`"] + #[inline(always)] + pub fn is_div8192(&self) -> bool { + **self == PSEL_A::DIV8192 + } + #[doc = "Checks if the value of the field is `DIV16384`"] + #[inline(always)] + pub fn is_div16384(&self) -> bool { + **self == PSEL_A::DIV16384 + } + #[doc = "Checks if the value of the field is `DIV32768`"] + #[inline(always)] + pub fn is_div32768(&self) -> bool { + **self == PSEL_A::DIV32768 + } + #[doc = "Checks if the value of the field is `DIV65536`"] + #[inline(always)] + pub fn is_div65536(&self) -> bool { + **self == PSEL_A::DIV65536 + } +} +impl core::ops::Deref for PSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PSEL` writer - Prescaler Select"] +pub struct PSEL_W<'a> { + w: &'a mut W, +} +impl<'a> PSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PSEL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Divide clock by 2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PSEL_A::DIV2) + } + #[doc = "Divide clock by 4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PSEL_A::DIV4) + } + #[doc = "Divide clock by 8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PSEL_A::DIV8) + } + #[doc = "Divide clock by 16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PSEL_A::DIV16) + } + #[doc = "Divide clock by 32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(PSEL_A::DIV32) + } + #[doc = "Divide clock by 64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PSEL_A::DIV64) + } + #[doc = "Divide clock by 128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(PSEL_A::DIV128) + } + #[doc = "Divide clock by 256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PSEL_A::DIV256) + } + #[doc = "Divide clock by 512"] + #[inline(always)] + pub fn div512(self) -> &'a mut W { + self.variant(PSEL_A::DIV512) + } + #[doc = "Divide clock by 1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PSEL_A::DIV1024) + } + #[doc = "Divide clock by 2048"] + #[inline(always)] + pub fn div2048(self) -> &'a mut W { + self.variant(PSEL_A::DIV2048) + } + #[doc = "Divide clock by 4096"] + #[inline(always)] + pub fn div4096(self) -> &'a mut W { + self.variant(PSEL_A::DIV4096) + } + #[doc = "Divide clock by 8192"] + #[inline(always)] + pub fn div8192(self) -> &'a mut W { + self.variant(PSEL_A::DIV8192) + } + #[doc = "Divide clock by 16384"] + #[inline(always)] + pub fn div16384(self) -> &'a mut W { + self.variant(PSEL_A::DIV16384) + } + #[doc = "Divide clock by 32768"] + #[inline(always)] + pub fn div32768(self) -> &'a mut W { + self.variant(PSEL_A::DIV32768) + } + #[doc = "Divide clock by 65536"] + #[inline(always)] + pub fn div65536(self) -> &'a mut W { + self.variant(PSEL_A::DIV65536) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 12)) | ((value as u32 & 0x0f) << 12); + self.w + } +} +#[doc = "Field `LEVEL` reader - Threshold Level for VDD"] +pub struct LEVEL_R(crate::FieldReader); +impl LEVEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LEVEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LEVEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LEVEL` writer - Threshold Level for VDD"] +pub struct LEVEL_W<'a> { + w: &'a mut W, +} +impl<'a> LEVEL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 16)) | ((value as u32 & 0x3f) << 16); + self.w + } +} +impl R { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Hysteresis Enable"] + #[inline(always)] + pub fn hyst(&self) -> HYST_R { + HYST_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 3:4 - Action when Threshold Crossed"] + #[inline(always)] + pub fn action(&self) -> ACTION_R { + ACTION_R::new(((self.bits >> 3) & 0x03) as u8) + } + #[doc = "Bit 5 - Configuration in Standby mode"] + #[inline(always)] + pub fn stdbycfg(&self) -> STDBYCFG_R { + STDBYCFG_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 8 - Configuration in Active mode"] + #[inline(always)] + pub fn actcfg(&self) -> ACTCFG_R { + ACTCFG_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bits 12:15 - Prescaler Select"] + #[inline(always)] + pub fn psel(&self) -> PSEL_R { + PSEL_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:21 - Threshold Level for VDD"] + #[inline(always)] + pub fn level(&self) -> LEVEL_R { + LEVEL_R::new(((self.bits >> 16) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - Hysteresis Enable"] + #[inline(always)] + pub fn hyst(&mut self) -> HYST_W { + HYST_W { w: self } + } + #[doc = "Bits 3:4 - Action when Threshold Crossed"] + #[inline(always)] + pub fn action(&mut self) -> ACTION_W { + ACTION_W { w: self } + } + #[doc = "Bit 5 - Configuration in Standby mode"] + #[inline(always)] + pub fn stdbycfg(&mut self) -> STDBYCFG_W { + STDBYCFG_W { w: self } + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 8 - Configuration in Active mode"] + #[inline(always)] + pub fn actcfg(&mut self) -> ACTCFG_W { + ACTCFG_W { w: self } + } + #[doc = "Bits 12:15 - Prescaler Select"] + #[inline(always)] + pub fn psel(&mut self) -> PSEL_W { + PSEL_W { w: self } + } + #[doc = "Bits 16:21 - Threshold Level for VDD"] + #[inline(always)] + pub fn level(&mut self) -> LEVEL_W { + LEVEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "BODVDD Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [bodvdd](index.html) module"] +pub struct BODVDD_SPEC; +impl crate::RegisterSpec for BODVDD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [bodvdd::R](R) reader structure"] +impl crate::Readable for BODVDD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [bodvdd::W](W) writer structure"] +impl crate::Writable for BODVDD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BODVDD to value 0"] +impl crate::Resettable for BODVDD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/supc/intenclr.rs b/pac/atsamc20g/src/supc/intenclr.rs new file mode 100644 index 000000000000..7b399544fafd --- /dev/null +++ b/pac/atsamc20g/src/supc/intenclr.rs @@ -0,0 +1,348 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BODVDDRDY` reader - BODVDD Ready"] +pub struct BODVDDRDY_R(crate::FieldReader); +impl BODVDDRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODVDDRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODVDDRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODVDDRDY` writer - BODVDD Ready"] +pub struct BODVDDRDY_W<'a> { + w: &'a mut W, +} +impl<'a> BODVDDRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `BODVDDDET` reader - BODVDD Detection"] +pub struct BODVDDDET_R(crate::FieldReader); +impl BODVDDDET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODVDDDET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODVDDDET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODVDDDET` writer - BODVDD Detection"] +pub struct BODVDDDET_W<'a> { + w: &'a mut W, +} +impl<'a> BODVDDDET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `BVDDSRDY` reader - BODVDD Synchronization Ready"] +pub struct BVDDSRDY_R(crate::FieldReader); +impl BVDDSRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BVDDSRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BVDDSRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BVDDSRDY` writer - BODVDD Synchronization Ready"] +pub struct BVDDSRDY_W<'a> { + w: &'a mut W, +} +impl<'a> BVDDSRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `BODCORERDY` reader - BODCORE Ready"] +pub struct BODCORERDY_R(crate::FieldReader); +impl BODCORERDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODCORERDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODCORERDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODCORERDY` writer - BODCORE Ready"] +pub struct BODCORERDY_W<'a> { + w: &'a mut W, +} +impl<'a> BODCORERDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `BODCOREDET` reader - BODCORE Detection"] +pub struct BODCOREDET_R(crate::FieldReader); +impl BODCOREDET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODCOREDET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODCOREDET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODCOREDET` writer - BODCORE Detection"] +pub struct BODCOREDET_W<'a> { + w: &'a mut W, +} +impl<'a> BODCOREDET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `BCORESRDY` reader - BODCORE Synchronization Ready"] +pub struct BCORESRDY_R(crate::FieldReader); +impl BCORESRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BCORESRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BCORESRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BCORESRDY` writer - BODCORE Synchronization Ready"] +pub struct BCORESRDY_W<'a> { + w: &'a mut W, +} +impl<'a> BCORESRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - BODVDD Ready"] + #[inline(always)] + pub fn bodvddrdy(&self) -> BODVDDRDY_R { + BODVDDRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - BODVDD Detection"] + #[inline(always)] + pub fn bodvdddet(&self) -> BODVDDDET_R { + BODVDDDET_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - BODVDD Synchronization Ready"] + #[inline(always)] + pub fn bvddsrdy(&self) -> BVDDSRDY_R { + BVDDSRDY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - BODCORE Ready"] + #[inline(always)] + pub fn bodcorerdy(&self) -> BODCORERDY_R { + BODCORERDY_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - BODCORE Detection"] + #[inline(always)] + pub fn bodcoredet(&self) -> BODCOREDET_R { + BODCOREDET_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - BODCORE Synchronization Ready"] + #[inline(always)] + pub fn bcoresrdy(&self) -> BCORESRDY_R { + BCORESRDY_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - BODVDD Ready"] + #[inline(always)] + pub fn bodvddrdy(&mut self) -> BODVDDRDY_W { + BODVDDRDY_W { w: self } + } + #[doc = "Bit 1 - BODVDD Detection"] + #[inline(always)] + pub fn bodvdddet(&mut self) -> BODVDDDET_W { + BODVDDDET_W { w: self } + } + #[doc = "Bit 2 - BODVDD Synchronization Ready"] + #[inline(always)] + pub fn bvddsrdy(&mut self) -> BVDDSRDY_W { + BVDDSRDY_W { w: self } + } + #[doc = "Bit 3 - BODCORE Ready"] + #[inline(always)] + pub fn bodcorerdy(&mut self) -> BODCORERDY_W { + BODCORERDY_W { w: self } + } + #[doc = "Bit 4 - BODCORE Detection"] + #[inline(always)] + pub fn bodcoredet(&mut self) -> BODCOREDET_W { + BODCOREDET_W { w: self } + } + #[doc = "Bit 5 - BODCORE Synchronization Ready"] + #[inline(always)] + pub fn bcoresrdy(&mut self) -> BCORESRDY_W { + BCORESRDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/supc/intenset.rs b/pac/atsamc20g/src/supc/intenset.rs new file mode 100644 index 000000000000..9e86a6e5b772 --- /dev/null +++ b/pac/atsamc20g/src/supc/intenset.rs @@ -0,0 +1,348 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BODVDDRDY` reader - BODVDD Ready"] +pub struct BODVDDRDY_R(crate::FieldReader); +impl BODVDDRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODVDDRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODVDDRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODVDDRDY` writer - BODVDD Ready"] +pub struct BODVDDRDY_W<'a> { + w: &'a mut W, +} +impl<'a> BODVDDRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `BODVDDDET` reader - BODVDD Detection"] +pub struct BODVDDDET_R(crate::FieldReader); +impl BODVDDDET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODVDDDET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODVDDDET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODVDDDET` writer - BODVDD Detection"] +pub struct BODVDDDET_W<'a> { + w: &'a mut W, +} +impl<'a> BODVDDDET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `BVDDSRDY` reader - BODVDD Synchronization Ready"] +pub struct BVDDSRDY_R(crate::FieldReader); +impl BVDDSRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BVDDSRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BVDDSRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BVDDSRDY` writer - BODVDD Synchronization Ready"] +pub struct BVDDSRDY_W<'a> { + w: &'a mut W, +} +impl<'a> BVDDSRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `BODCORERDY` reader - BODCORE Ready"] +pub struct BODCORERDY_R(crate::FieldReader); +impl BODCORERDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODCORERDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODCORERDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODCORERDY` writer - BODCORE Ready"] +pub struct BODCORERDY_W<'a> { + w: &'a mut W, +} +impl<'a> BODCORERDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `BODCOREDET` reader - BODCORE Detection"] +pub struct BODCOREDET_R(crate::FieldReader); +impl BODCOREDET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODCOREDET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODCOREDET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODCOREDET` writer - BODCORE Detection"] +pub struct BODCOREDET_W<'a> { + w: &'a mut W, +} +impl<'a> BODCOREDET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `BCORESRDY` reader - BODCORE Synchronization Ready"] +pub struct BCORESRDY_R(crate::FieldReader); +impl BCORESRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BCORESRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BCORESRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BCORESRDY` writer - BODCORE Synchronization Ready"] +pub struct BCORESRDY_W<'a> { + w: &'a mut W, +} +impl<'a> BCORESRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - BODVDD Ready"] + #[inline(always)] + pub fn bodvddrdy(&self) -> BODVDDRDY_R { + BODVDDRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - BODVDD Detection"] + #[inline(always)] + pub fn bodvdddet(&self) -> BODVDDDET_R { + BODVDDDET_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - BODVDD Synchronization Ready"] + #[inline(always)] + pub fn bvddsrdy(&self) -> BVDDSRDY_R { + BVDDSRDY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - BODCORE Ready"] + #[inline(always)] + pub fn bodcorerdy(&self) -> BODCORERDY_R { + BODCORERDY_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - BODCORE Detection"] + #[inline(always)] + pub fn bodcoredet(&self) -> BODCOREDET_R { + BODCOREDET_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - BODCORE Synchronization Ready"] + #[inline(always)] + pub fn bcoresrdy(&self) -> BCORESRDY_R { + BCORESRDY_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - BODVDD Ready"] + #[inline(always)] + pub fn bodvddrdy(&mut self) -> BODVDDRDY_W { + BODVDDRDY_W { w: self } + } + #[doc = "Bit 1 - BODVDD Detection"] + #[inline(always)] + pub fn bodvdddet(&mut self) -> BODVDDDET_W { + BODVDDDET_W { w: self } + } + #[doc = "Bit 2 - BODVDD Synchronization Ready"] + #[inline(always)] + pub fn bvddsrdy(&mut self) -> BVDDSRDY_W { + BVDDSRDY_W { w: self } + } + #[doc = "Bit 3 - BODCORE Ready"] + #[inline(always)] + pub fn bodcorerdy(&mut self) -> BODCORERDY_W { + BODCORERDY_W { w: self } + } + #[doc = "Bit 4 - BODCORE Detection"] + #[inline(always)] + pub fn bodcoredet(&mut self) -> BODCOREDET_W { + BODCOREDET_W { w: self } + } + #[doc = "Bit 5 - BODCORE Synchronization Ready"] + #[inline(always)] + pub fn bcoresrdy(&mut self) -> BCORESRDY_W { + BCORESRDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/supc/intflag.rs b/pac/atsamc20g/src/supc/intflag.rs new file mode 100644 index 000000000000..46b4b52add2d --- /dev/null +++ b/pac/atsamc20g/src/supc/intflag.rs @@ -0,0 +1,348 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BODVDDRDY` reader - BODVDD Ready"] +pub struct BODVDDRDY_R(crate::FieldReader); +impl BODVDDRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODVDDRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODVDDRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODVDDRDY` writer - BODVDD Ready"] +pub struct BODVDDRDY_W<'a> { + w: &'a mut W, +} +impl<'a> BODVDDRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `BODVDDDET` reader - BODVDD Detection"] +pub struct BODVDDDET_R(crate::FieldReader); +impl BODVDDDET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODVDDDET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODVDDDET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODVDDDET` writer - BODVDD Detection"] +pub struct BODVDDDET_W<'a> { + w: &'a mut W, +} +impl<'a> BODVDDDET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `BVDDSRDY` reader - BODVDD Synchronization Ready"] +pub struct BVDDSRDY_R(crate::FieldReader); +impl BVDDSRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BVDDSRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BVDDSRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BVDDSRDY` writer - BODVDD Synchronization Ready"] +pub struct BVDDSRDY_W<'a> { + w: &'a mut W, +} +impl<'a> BVDDSRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `BODCORERDY` reader - BODCORE Ready"] +pub struct BODCORERDY_R(crate::FieldReader); +impl BODCORERDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODCORERDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODCORERDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODCORERDY` writer - BODCORE Ready"] +pub struct BODCORERDY_W<'a> { + w: &'a mut W, +} +impl<'a> BODCORERDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `BODCOREDET` reader - BODCORE Detection"] +pub struct BODCOREDET_R(crate::FieldReader); +impl BODCOREDET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODCOREDET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODCOREDET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODCOREDET` writer - BODCORE Detection"] +pub struct BODCOREDET_W<'a> { + w: &'a mut W, +} +impl<'a> BODCOREDET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `BCORESRDY` reader - BODCORE Synchronization Ready"] +pub struct BCORESRDY_R(crate::FieldReader); +impl BCORESRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BCORESRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BCORESRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BCORESRDY` writer - BODCORE Synchronization Ready"] +pub struct BCORESRDY_W<'a> { + w: &'a mut W, +} +impl<'a> BCORESRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - BODVDD Ready"] + #[inline(always)] + pub fn bodvddrdy(&self) -> BODVDDRDY_R { + BODVDDRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - BODVDD Detection"] + #[inline(always)] + pub fn bodvdddet(&self) -> BODVDDDET_R { + BODVDDDET_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - BODVDD Synchronization Ready"] + #[inline(always)] + pub fn bvddsrdy(&self) -> BVDDSRDY_R { + BVDDSRDY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - BODCORE Ready"] + #[inline(always)] + pub fn bodcorerdy(&self) -> BODCORERDY_R { + BODCORERDY_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - BODCORE Detection"] + #[inline(always)] + pub fn bodcoredet(&self) -> BODCOREDET_R { + BODCOREDET_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - BODCORE Synchronization Ready"] + #[inline(always)] + pub fn bcoresrdy(&self) -> BCORESRDY_R { + BCORESRDY_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - BODVDD Ready"] + #[inline(always)] + pub fn bodvddrdy(&mut self) -> BODVDDRDY_W { + BODVDDRDY_W { w: self } + } + #[doc = "Bit 1 - BODVDD Detection"] + #[inline(always)] + pub fn bodvdddet(&mut self) -> BODVDDDET_W { + BODVDDDET_W { w: self } + } + #[doc = "Bit 2 - BODVDD Synchronization Ready"] + #[inline(always)] + pub fn bvddsrdy(&mut self) -> BVDDSRDY_W { + BVDDSRDY_W { w: self } + } + #[doc = "Bit 3 - BODCORE Ready"] + #[inline(always)] + pub fn bodcorerdy(&mut self) -> BODCORERDY_W { + BODCORERDY_W { w: self } + } + #[doc = "Bit 4 - BODCORE Detection"] + #[inline(always)] + pub fn bodcoredet(&mut self) -> BODCOREDET_W { + BODCOREDET_W { w: self } + } + #[doc = "Bit 5 - BODCORE Synchronization Ready"] + #[inline(always)] + pub fn bcoresrdy(&mut self) -> BCORESRDY_W { + BCORESRDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/supc/status.rs b/pac/atsamc20g/src/supc/status.rs new file mode 100644 index 000000000000..0fc1de3635b5 --- /dev/null +++ b/pac/atsamc20g/src/supc/status.rs @@ -0,0 +1,153 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `BODVDDRDY` reader - BODVDD Ready"] +pub struct BODVDDRDY_R(crate::FieldReader); +impl BODVDDRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODVDDRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODVDDRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODVDDDET` reader - BODVDD Detection"] +pub struct BODVDDDET_R(crate::FieldReader); +impl BODVDDDET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODVDDDET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODVDDDET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BVDDSRDY` reader - BODVDD Synchronization Ready"] +pub struct BVDDSRDY_R(crate::FieldReader); +impl BVDDSRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BVDDSRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BVDDSRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODCORERDY` reader - BODCORE Ready"] +pub struct BODCORERDY_R(crate::FieldReader); +impl BODCORERDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODCORERDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODCORERDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODCOREDET` reader - BODCORE Detection"] +pub struct BODCOREDET_R(crate::FieldReader); +impl BODCOREDET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODCOREDET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODCOREDET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BCORESRDY` reader - BODCORE Synchronization Ready"] +pub struct BCORESRDY_R(crate::FieldReader); +impl BCORESRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BCORESRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BCORESRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - BODVDD Ready"] + #[inline(always)] + pub fn bodvddrdy(&self) -> BODVDDRDY_R { + BODVDDRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - BODVDD Detection"] + #[inline(always)] + pub fn bodvdddet(&self) -> BODVDDDET_R { + BODVDDDET_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - BODVDD Synchronization Ready"] + #[inline(always)] + pub fn bvddsrdy(&self) -> BVDDSRDY_R { + BVDDSRDY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - BODCORE Ready"] + #[inline(always)] + pub fn bodcorerdy(&self) -> BODCORERDY_R { + BODCORERDY_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - BODCORE Detection"] + #[inline(always)] + pub fn bodcoredet(&self) -> BODCOREDET_R { + BODCOREDET_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - BODCORE Synchronization Ready"] + #[inline(always)] + pub fn bcoresrdy(&self) -> BCORESRDY_R { + BCORESRDY_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +#[doc = "Power and Clocks Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/supc/vref.rs b/pac/atsamc20g/src/supc/vref.rs new file mode 100644 index 000000000000..2d5b1381885e --- /dev/null +++ b/pac/atsamc20g/src/supc/vref.rs @@ -0,0 +1,353 @@ +#[doc = "Register `VREF` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `VREF` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TSEN` reader - Temperature Sensor Output Enable"] +pub struct TSEN_R(crate::FieldReader); +impl TSEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSEN` writer - Temperature Sensor Output Enable"] +pub struct TSEN_W<'a> { + w: &'a mut W, +} +impl<'a> TSEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `VREFOE` reader - Voltage Reference Output Enable"] +pub struct VREFOE_R(crate::FieldReader); +impl VREFOE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + VREFOE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VREFOE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VREFOE` writer - Voltage Reference Output Enable"] +pub struct VREFOE_W<'a> { + w: &'a mut W, +} +impl<'a> VREFOE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - On Demand Contrl"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - On Demand Contrl"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Voltage Reference Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SEL_A { + #[doc = "0: 1.024V voltage reference typical value"] + _1V024 = 0, + #[doc = "2: 2.048V voltage reference typical value"] + _2V048 = 2, + #[doc = "3: 4.096V voltage reference typical value"] + _4V096 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `SEL` reader - Voltage Reference Selection"] +pub struct SEL_R(crate::FieldReader); +impl SEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEL_A::_1V024), + 2 => Some(SEL_A::_2V048), + 3 => Some(SEL_A::_4V096), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_1V024`"] + #[inline(always)] + pub fn is_1v024(&self) -> bool { + **self == SEL_A::_1V024 + } + #[doc = "Checks if the value of the field is `_2V048`"] + #[inline(always)] + pub fn is_2v048(&self) -> bool { + **self == SEL_A::_2V048 + } + #[doc = "Checks if the value of the field is `_4V096`"] + #[inline(always)] + pub fn is_4v096(&self) -> bool { + **self == SEL_A::_4V096 + } +} +impl core::ops::Deref for SEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEL` writer - Voltage Reference Selection"] +pub struct SEL_W<'a> { + w: &'a mut W, +} +impl<'a> SEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SEL_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "1.024V voltage reference typical value"] + #[inline(always)] + pub fn _1v024(self) -> &'a mut W { + self.variant(SEL_A::_1V024) + } + #[doc = "2.048V voltage reference typical value"] + #[inline(always)] + pub fn _2v048(self) -> &'a mut W { + self.variant(SEL_A::_2V048) + } + #[doc = "4.096V voltage reference typical value"] + #[inline(always)] + pub fn _4v096(self) -> &'a mut W { + self.variant(SEL_A::_4V096) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 16)) | ((value as u32 & 0x0f) << 16); + self.w + } +} +impl R { + #[doc = "Bit 1 - Temperature Sensor Output Enable"] + #[inline(always)] + pub fn tsen(&self) -> TSEN_R { + TSEN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Voltage Reference Output Enable"] + #[inline(always)] + pub fn vrefoe(&self) -> VREFOE_R { + VREFOE_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - On Demand Contrl"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 16:19 - Voltage Reference Selection"] + #[inline(always)] + pub fn sel(&self) -> SEL_R { + SEL_R::new(((self.bits >> 16) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bit 1 - Temperature Sensor Output Enable"] + #[inline(always)] + pub fn tsen(&mut self) -> TSEN_W { + TSEN_W { w: self } + } + #[doc = "Bit 2 - Voltage Reference Output Enable"] + #[inline(always)] + pub fn vrefoe(&mut self) -> VREFOE_W { + VREFOE_W { w: self } + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - On Demand Contrl"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Bits 16:19 - Voltage Reference Selection"] + #[inline(always)] + pub fn sel(&mut self) -> SEL_W { + SEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "VREF Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [vref](index.html) module"] +pub struct VREF_SPEC; +impl crate::RegisterSpec for VREF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [vref::R](R) reader structure"] +impl crate::Readable for VREF_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [vref::W](W) writer structure"] +impl crate::Writable for VREF_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets VREF to value 0"] +impl crate::Resettable for VREF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/supc/vreg.rs b/pac/atsamc20g/src/supc/vreg.rs new file mode 100644 index 000000000000..fb5b12a185cf --- /dev/null +++ b/pac/atsamc20g/src/supc/vreg.rs @@ -0,0 +1,160 @@ +#[doc = "Register `VREG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `VREG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "VREG Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [vreg](index.html) module"] +pub struct VREG_SPEC; +impl crate::RegisterSpec for VREG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [vreg::R](R) reader structure"] +impl crate::Readable for VREG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [vreg::W](W) writer structure"] +impl crate::Writable for VREG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets VREG to value 0"] +impl crate::Resettable for VREG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/sys_tick.rs b/pac/atsamc20g/src/sys_tick.rs new file mode 100644 index 000000000000..b0fe7a59e5ed --- /dev/null +++ b/pac/atsamc20g/src/sys_tick.rs @@ -0,0 +1,28 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - SysTick Control and Status Register"] + pub csr: crate::Reg, + #[doc = "0x04 - SysTick Reload Value Register"] + pub rvr: crate::Reg, + #[doc = "0x08 - SysTick Current Value Register"] + pub cvr: crate::Reg, + #[doc = "0x0c - SysTick Calibration Value Register"] + pub calib: crate::Reg, +} +#[doc = "CSR register accessor: an alias for `Reg`"] +pub type CSR = crate::Reg; +#[doc = "SysTick Control and Status Register"] +pub mod csr; +#[doc = "RVR register accessor: an alias for `Reg`"] +pub type RVR = crate::Reg; +#[doc = "SysTick Reload Value Register"] +pub mod rvr; +#[doc = "CVR register accessor: an alias for `Reg`"] +pub type CVR = crate::Reg; +#[doc = "SysTick Current Value Register"] +pub mod cvr; +#[doc = "CALIB register accessor: an alias for `Reg`"] +pub type CALIB = crate::Reg; +#[doc = "SysTick Calibration Value Register"] +pub mod calib; diff --git a/pac/atsamc20g/src/sys_tick/calib.rs b/pac/atsamc20g/src/sys_tick/calib.rs new file mode 100644 index 000000000000..df7fd80f773a --- /dev/null +++ b/pac/atsamc20g/src/sys_tick/calib.rs @@ -0,0 +1,157 @@ +#[doc = "Register `CALIB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `TENMS` reader - Reload value to use for 10ms timing"] +pub struct TENMS_R(crate::FieldReader); +impl TENMS_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + TENMS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TENMS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "TENMS is rounded from non-integer ratio\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SKEW_A { + #[doc = "0: 10ms calibration value is exact"] + VALUE_0 = 0, + #[doc = "1: 10ms calibration value is inexact, because of the clock frequency"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SKEW_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SKEW` reader - TENMS is rounded from non-integer ratio"] +pub struct SKEW_R(crate::FieldReader); +impl SKEW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SKEW_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SKEW_A { + match self.bits { + false => SKEW_A::VALUE_0, + true => SKEW_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == SKEW_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == SKEW_A::VALUE_1 + } +} +impl core::ops::Deref for SKEW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "No Separate Reference Clock\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum NOREF_A { + #[doc = "0: The reference clock is provided"] + VALUE_0 = 0, + #[doc = "1: The reference clock is not provided"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NOREF_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NOREF` reader - No Separate Reference Clock"] +pub struct NOREF_R(crate::FieldReader); +impl NOREF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NOREF_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> NOREF_A { + match self.bits { + false => NOREF_A::VALUE_0, + true => NOREF_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == NOREF_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == NOREF_A::VALUE_1 + } +} +impl core::ops::Deref for NOREF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:23 - Reload value to use for 10ms timing"] + #[inline(always)] + pub fn tenms(&self) -> TENMS_R { + TENMS_R::new((self.bits & 0x00ff_ffff) as u32) + } + #[doc = "Bit 30 - TENMS is rounded from non-integer ratio"] + #[inline(always)] + pub fn skew(&self) -> SKEW_R { + SKEW_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 31 - No Separate Reference Clock"] + #[inline(always)] + pub fn noref(&self) -> NOREF_R { + NOREF_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +#[doc = "SysTick Calibration Value Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [calib](index.html) module"] +pub struct CALIB_SPEC; +impl crate::RegisterSpec for CALIB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [calib::R](R) reader structure"] +impl crate::Readable for CALIB_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CALIB to value 0"] +impl crate::Resettable for CALIB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/sys_tick/csr.rs b/pac/atsamc20g/src/sys_tick/csr.rs new file mode 100644 index 000000000000..872d637f5a86 --- /dev/null +++ b/pac/atsamc20g/src/sys_tick/csr.rs @@ -0,0 +1,395 @@ +#[doc = "Register `CSR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CSR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "SysTick Counter Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ENABLE_A { + #[doc = "0: Counter disabled"] + VALUE_0 = 0, + #[doc = "1: Counter enabled"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ENABLE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ENABLE` reader - SysTick Counter Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ENABLE_A { + match self.bits { + false => ENABLE_A::VALUE_0, + true => ENABLE_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == ENABLE_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == ENABLE_A::VALUE_1 + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - SysTick Counter Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: ENABLE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Counter disabled"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(ENABLE_A::VALUE_0) + } + #[doc = "Counter enabled"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(ENABLE_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "SysTick Exception Request Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TICKINT_A { + #[doc = "0: Counting down to 0 does not assert the SysTick exception request"] + VALUE_0 = 0, + #[doc = "1: Counting down to 0 asserts the SysTick exception request"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TICKINT_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TICKINT` reader - SysTick Exception Request Enable"] +pub struct TICKINT_R(crate::FieldReader); +impl TICKINT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TICKINT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TICKINT_A { + match self.bits { + false => TICKINT_A::VALUE_0, + true => TICKINT_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == TICKINT_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == TICKINT_A::VALUE_1 + } +} +impl core::ops::Deref for TICKINT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TICKINT` writer - SysTick Exception Request Enable"] +pub struct TICKINT_W<'a> { + w: &'a mut W, +} +impl<'a> TICKINT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TICKINT_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Counting down to 0 does not assert the SysTick exception request"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(TICKINT_A::VALUE_0) + } + #[doc = "Counting down to 0 asserts the SysTick exception request"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(TICKINT_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Clock Source 0=external, 1=processor\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CLKSOURCE_A { + #[doc = "0: External clock"] + VALUE_0 = 0, + #[doc = "1: Processor clock"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CLKSOURCE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CLKSOURCE` reader - Clock Source 0=external, 1=processor"] +pub struct CLKSOURCE_R(crate::FieldReader); +impl CLKSOURCE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKSOURCE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CLKSOURCE_A { + match self.bits { + false => CLKSOURCE_A::VALUE_0, + true => CLKSOURCE_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == CLKSOURCE_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == CLKSOURCE_A::VALUE_1 + } +} +impl core::ops::Deref for CLKSOURCE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKSOURCE` writer - Clock Source 0=external, 1=processor"] +pub struct CLKSOURCE_W<'a> { + w: &'a mut W, +} +impl<'a> CLKSOURCE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CLKSOURCE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "External clock"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(CLKSOURCE_A::VALUE_0) + } + #[doc = "Processor clock"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(CLKSOURCE_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `COUNTFLAG` reader - Timer counted to 0 since last read of register"] +pub struct COUNTFLAG_R(crate::FieldReader); +impl COUNTFLAG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNTFLAG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNTFLAG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNTFLAG` writer - Timer counted to 0 since last read of register"] +pub struct COUNTFLAG_W<'a> { + w: &'a mut W, +} +impl<'a> COUNTFLAG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +impl R { + #[doc = "Bit 0 - SysTick Counter Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SysTick Exception Request Enable"] + #[inline(always)] + pub fn tickint(&self) -> TICKINT_R { + TICKINT_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Clock Source 0=external, 1=processor"] + #[inline(always)] + pub fn clksource(&self) -> CLKSOURCE_R { + CLKSOURCE_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 16 - Timer counted to 0 since last read of register"] + #[inline(always)] + pub fn countflag(&self) -> COUNTFLAG_R { + COUNTFLAG_R::new(((self.bits >> 16) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - SysTick Counter Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 1 - SysTick Exception Request Enable"] + #[inline(always)] + pub fn tickint(&mut self) -> TICKINT_W { + TICKINT_W { w: self } + } + #[doc = "Bit 2 - Clock Source 0=external, 1=processor"] + #[inline(always)] + pub fn clksource(&mut self) -> CLKSOURCE_W { + CLKSOURCE_W { w: self } + } + #[doc = "Bit 16 - Timer counted to 0 since last read of register"] + #[inline(always)] + pub fn countflag(&mut self) -> COUNTFLAG_W { + COUNTFLAG_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SysTick Control and Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [csr](index.html) module"] +pub struct CSR_SPEC; +impl crate::RegisterSpec for CSR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [csr::R](R) reader structure"] +impl crate::Readable for CSR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [csr::W](W) writer structure"] +impl crate::Writable for CSR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CSR to value 0x04"] +impl crate::Resettable for CSR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x04 + } +} diff --git a/pac/atsamc20g/src/sys_tick/cvr.rs b/pac/atsamc20g/src/sys_tick/cvr.rs new file mode 100644 index 000000000000..8a40b5f43b3a --- /dev/null +++ b/pac/atsamc20g/src/sys_tick/cvr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `CVR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CVR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CURRENT` reader - Current value at the time the register is accessed"] +pub struct CURRENT_R(crate::FieldReader); +impl CURRENT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CURRENT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CURRENT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CURRENT` writer - Current value at the time the register is accessed"] +pub struct CURRENT_W<'a> { + w: &'a mut W, +} +impl<'a> CURRENT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Current value at the time the register is accessed"] + #[inline(always)] + pub fn current(&self) -> CURRENT_R { + CURRENT_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Current value at the time the register is accessed"] + #[inline(always)] + pub fn current(&mut self) -> CURRENT_W { + CURRENT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SysTick Current Value Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cvr](index.html) module"] +pub struct CVR_SPEC; +impl crate::RegisterSpec for CVR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cvr::R](R) reader structure"] +impl crate::Readable for CVR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cvr::W](W) writer structure"] +impl crate::Writable for CVR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CVR to value 0"] +impl crate::Resettable for CVR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/sys_tick/rvr.rs b/pac/atsamc20g/src/sys_tick/rvr.rs new file mode 100644 index 000000000000..ac023ff75f36 --- /dev/null +++ b/pac/atsamc20g/src/sys_tick/rvr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `RVR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RVR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RELOAD` reader - Value to load into the SysTick Current Value Register when the counter reaches 0"] +pub struct RELOAD_R(crate::FieldReader); +impl RELOAD_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + RELOAD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RELOAD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RELOAD` writer - Value to load into the SysTick Current Value Register when the counter reaches 0"] +pub struct RELOAD_W<'a> { + w: &'a mut W, +} +impl<'a> RELOAD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Value to load into the SysTick Current Value Register when the counter reaches 0"] + #[inline(always)] + pub fn reload(&self) -> RELOAD_R { + RELOAD_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Value to load into the SysTick Current Value Register when the counter reaches 0"] + #[inline(always)] + pub fn reload(&mut self) -> RELOAD_W { + RELOAD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SysTick Reload Value Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rvr](index.html) module"] +pub struct RVR_SPEC; +impl crate::RegisterSpec for RVR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rvr::R](R) reader structure"] +impl crate::Readable for RVR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rvr::W](W) writer structure"] +impl crate::Writable for RVR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RVR to value 0"] +impl crate::Resettable for RVR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/system_control.rs b/pac/atsamc20g/src/system_control.rs new file mode 100644 index 000000000000..4894b22b258f --- /dev/null +++ b/pac/atsamc20g/src/system_control.rs @@ -0,0 +1,67 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved0: [u8; 0x0d00], + #[doc = "0xd00 - CPUID Base Register"] + pub cpuid: crate::Reg, + #[doc = "0xd04 - Interrupt Control and State Register"] + pub icsr: crate::Reg, + #[doc = "0xd08 - Vector Table Offset Register"] + pub vtor: crate::Reg, + #[doc = "0xd0c - Application Interrupt and Reset Control Register"] + pub aircr: crate::Reg, + #[doc = "0xd10 - System Control Register"] + pub scr: crate::Reg, + #[doc = "0xd14 - Configuration and Control Register"] + pub ccr: crate::Reg, + _reserved6: [u8; 0x04], + #[doc = "0xd1c - System Handler Priority Register 2"] + pub shpr2: crate::Reg, + #[doc = "0xd20 - System Handler Priority Register 3"] + pub shpr3: crate::Reg, + #[doc = "0xd24 - System Handler Control and State Register"] + pub shcsr: crate::Reg, + _reserved9: [u8; 0x08], + #[doc = "0xd30 - Debug Fault Status Register"] + pub dfsr: crate::Reg, +} +#[doc = "CPUID register accessor: an alias for `Reg`"] +pub type CPUID = crate::Reg; +#[doc = "CPUID Base Register"] +pub mod cpuid; +#[doc = "ICSR register accessor: an alias for `Reg`"] +pub type ICSR = crate::Reg; +#[doc = "Interrupt Control and State Register"] +pub mod icsr; +#[doc = "VTOR register accessor: an alias for `Reg`"] +pub type VTOR = crate::Reg; +#[doc = "Vector Table Offset Register"] +pub mod vtor; +#[doc = "AIRCR register accessor: an alias for `Reg`"] +pub type AIRCR = crate::Reg; +#[doc = "Application Interrupt and Reset Control Register"] +pub mod aircr; +#[doc = "SCR register accessor: an alias for `Reg`"] +pub type SCR = crate::Reg; +#[doc = "System Control Register"] +pub mod scr; +#[doc = "CCR register accessor: an alias for `Reg`"] +pub type CCR = crate::Reg; +#[doc = "Configuration and Control Register"] +pub mod ccr; +#[doc = "SHPR2 register accessor: an alias for `Reg`"] +pub type SHPR2 = crate::Reg; +#[doc = "System Handler Priority Register 2"] +pub mod shpr2; +#[doc = "SHPR3 register accessor: an alias for `Reg`"] +pub type SHPR3 = crate::Reg; +#[doc = "System Handler Priority Register 3"] +pub mod shpr3; +#[doc = "SHCSR register accessor: an alias for `Reg`"] +pub type SHCSR = crate::Reg; +#[doc = "System Handler Control and State Register"] +pub mod shcsr; +#[doc = "DFSR register accessor: an alias for `Reg`"] +pub type DFSR = crate::Reg; +#[doc = "Debug Fault Status Register"] +pub mod dfsr; diff --git a/pac/atsamc20g/src/system_control/aircr.rs b/pac/atsamc20g/src/system_control/aircr.rs new file mode 100644 index 000000000000..9453cc6f30bc --- /dev/null +++ b/pac/atsamc20g/src/system_control/aircr.rs @@ -0,0 +1,338 @@ +#[doc = "Register `AIRCR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `AIRCR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `VECTCLRACTIVE` reader - Debug: Clear state information"] +pub struct VECTCLRACTIVE_R(crate::FieldReader); +impl VECTCLRACTIVE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + VECTCLRACTIVE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VECTCLRACTIVE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VECTCLRACTIVE` writer - Debug: Clear state information"] +pub struct VECTCLRACTIVE_W<'a> { + w: &'a mut W, +} +impl<'a> VECTCLRACTIVE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "System Reset Request\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SYSRESETREQ_A { + #[doc = "0: No system reset request"] + VALUE_0 = 0, + #[doc = "1: Asserts a signal to the outer system that requests a reset"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SYSRESETREQ_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SYSRESETREQ` reader - System Reset Request"] +pub struct SYSRESETREQ_R(crate::FieldReader); +impl SYSRESETREQ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYSRESETREQ_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SYSRESETREQ_A { + match self.bits { + false => SYSRESETREQ_A::VALUE_0, + true => SYSRESETREQ_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == SYSRESETREQ_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == SYSRESETREQ_A::VALUE_1 + } +} +impl core::ops::Deref for SYSRESETREQ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYSRESETREQ` writer - System Reset Request"] +pub struct SYSRESETREQ_W<'a> { + w: &'a mut W, +} +impl<'a> SYSRESETREQ_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SYSRESETREQ_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "No system reset request"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(SYSRESETREQ_A::VALUE_0) + } + #[doc = "Asserts a signal to the outer system that requests a reset"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(SYSRESETREQ_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Data Endianness, 0=little, 1=big\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ENDIANNESS_A { + #[doc = "0: Little-endian"] + VALUE_0 = 0, + #[doc = "1: Big-endian"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ENDIANNESS_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ENDIANNESS` reader - Data Endianness, 0=little, 1=big"] +pub struct ENDIANNESS_R(crate::FieldReader); +impl ENDIANNESS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENDIANNESS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ENDIANNESS_A { + match self.bits { + false => ENDIANNESS_A::VALUE_0, + true => ENDIANNESS_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == ENDIANNESS_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == ENDIANNESS_A::VALUE_1 + } +} +impl core::ops::Deref for ENDIANNESS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENDIANNESS` writer - Data Endianness, 0=little, 1=big"] +pub struct ENDIANNESS_W<'a> { + w: &'a mut W, +} +impl<'a> ENDIANNESS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: ENDIANNESS_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Little-endian"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(ENDIANNESS_A::VALUE_0) + } + #[doc = "Big-endian"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(ENDIANNESS_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `VECTKEY` reader - Register key (0x05FA)"] +pub struct VECTKEY_R(crate::FieldReader); +impl VECTKEY_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + VECTKEY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VECTKEY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VECTKEY` writer - Register key (0x05FA)"] +pub struct VECTKEY_W<'a> { + w: &'a mut W, +} +impl<'a> VECTKEY_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xffff << 16)) | ((value as u32 & 0xffff) << 16); + self.w + } +} +impl R { + #[doc = "Bit 1 - Debug: Clear state information"] + #[inline(always)] + pub fn vectclractive(&self) -> VECTCLRACTIVE_R { + VECTCLRACTIVE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - System Reset Request"] + #[inline(always)] + pub fn sysresetreq(&self) -> SYSRESETREQ_R { + SYSRESETREQ_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 15 - Data Endianness, 0=little, 1=big"] + #[inline(always)] + pub fn endianness(&self) -> ENDIANNESS_R { + ENDIANNESS_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:31 - Register key (0x05FA)"] + #[inline(always)] + pub fn vectkey(&self) -> VECTKEY_R { + VECTKEY_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bit 1 - Debug: Clear state information"] + #[inline(always)] + pub fn vectclractive(&mut self) -> VECTCLRACTIVE_W { + VECTCLRACTIVE_W { w: self } + } + #[doc = "Bit 2 - System Reset Request"] + #[inline(always)] + pub fn sysresetreq(&mut self) -> SYSRESETREQ_W { + SYSRESETREQ_W { w: self } + } + #[doc = "Bit 15 - Data Endianness, 0=little, 1=big"] + #[inline(always)] + pub fn endianness(&mut self) -> ENDIANNESS_W { + ENDIANNESS_W { w: self } + } + #[doc = "Bits 16:31 - Register key (0x05FA)"] + #[inline(always)] + pub fn vectkey(&mut self) -> VECTKEY_W { + VECTKEY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Application Interrupt and Reset Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [aircr](index.html) module"] +pub struct AIRCR_SPEC; +impl crate::RegisterSpec for AIRCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [aircr::R](R) reader structure"] +impl crate::Readable for AIRCR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [aircr::W](W) writer structure"] +impl crate::Writable for AIRCR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets AIRCR to value 0"] +impl crate::Resettable for AIRCR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/system_control/ccr.rs b/pac/atsamc20g/src/system_control/ccr.rs new file mode 100644 index 000000000000..62516a7b60c8 --- /dev/null +++ b/pac/atsamc20g/src/system_control/ccr.rs @@ -0,0 +1,137 @@ +#[doc = "Register `CCR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Unaligned accesses generates a Hard Fault\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum UNALIGN_TRP_A { + #[doc = "0: Do not trap unaligned halfword and word accesses"] + VALUE_0 = 0, + #[doc = "1: Trap unaligned halfword and word accesses"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: UNALIGN_TRP_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `UNALIGN_TRP` reader - Unaligned accesses generates a Hard Fault"] +pub struct UNALIGN_TRP_R(crate::FieldReader); +impl UNALIGN_TRP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UNALIGN_TRP_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> UNALIGN_TRP_A { + match self.bits { + false => UNALIGN_TRP_A::VALUE_0, + true => UNALIGN_TRP_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == UNALIGN_TRP_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == UNALIGN_TRP_A::VALUE_1 + } +} +impl core::ops::Deref for UNALIGN_TRP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Stack 8-byte aligned on exception entry\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum STKALIGN_A { + #[doc = "0: 4-byte aligned"] + VALUE_0 = 0, + #[doc = "1: 8-byte aligned"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: STKALIGN_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STKALIGN` reader - Stack 8-byte aligned on exception entry"] +pub struct STKALIGN_R(crate::FieldReader); +impl STKALIGN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STKALIGN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STKALIGN_A { + match self.bits { + false => STKALIGN_A::VALUE_0, + true => STKALIGN_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == STKALIGN_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == STKALIGN_A::VALUE_1 + } +} +impl core::ops::Deref for STKALIGN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 3 - Unaligned accesses generates a Hard Fault"] + #[inline(always)] + pub fn unalign_trp(&self) -> UNALIGN_TRP_R { + UNALIGN_TRP_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 9 - Stack 8-byte aligned on exception entry"] + #[inline(always)] + pub fn stkalign(&self) -> STKALIGN_R { + STKALIGN_R::new(((self.bits >> 9) & 0x01) != 0) + } +} +#[doc = "Configuration and Control Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccr](index.html) module"] +pub struct CCR_SPEC; +impl crate::RegisterSpec for CCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ccr::R](R) reader structure"] +impl crate::Readable for CCR_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CCR to value 0x0204"] +impl crate::Resettable for CCR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0204 + } +} diff --git a/pac/atsamc20g/src/system_control/cpuid.rs b/pac/atsamc20g/src/system_control/cpuid.rs new file mode 100644 index 000000000000..4157d7a94e97 --- /dev/null +++ b/pac/atsamc20g/src/system_control/cpuid.rs @@ -0,0 +1,133 @@ +#[doc = "Register `CPUID` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `REVISION` reader - Minor revision number"] +pub struct REVISION_R(crate::FieldReader); +impl REVISION_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REVISION_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REVISION_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PARTNO` reader - Processor Part Number, 0xC60=Cortex-M0+"] +pub struct PARTNO_R(crate::FieldReader); +impl PARTNO_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + PARTNO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PARTNO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ARCHITECTURE` reader - Processor Architecture, 0xC=ARMv6-M"] +pub struct ARCHITECTURE_R(crate::FieldReader); +impl ARCHITECTURE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ARCHITECTURE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ARCHITECTURE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VARIANT` reader - Major revision number"] +pub struct VARIANT_R(crate::FieldReader); +impl VARIANT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + VARIANT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VARIANT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IMPLEMENTER` reader - Implementer code, ARM=0x41"] +pub struct IMPLEMENTER_R(crate::FieldReader); +impl IMPLEMENTER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + IMPLEMENTER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IMPLEMENTER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:3 - Minor revision number"] + #[inline(always)] + pub fn revision(&self) -> REVISION_R { + REVISION_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:15 - Processor Part Number, 0xC60=Cortex-M0+"] + #[inline(always)] + pub fn partno(&self) -> PARTNO_R { + PARTNO_R::new(((self.bits >> 4) & 0x0fff) as u16) + } + #[doc = "Bits 16:19 - Processor Architecture, 0xC=ARMv6-M"] + #[inline(always)] + pub fn architecture(&self) -> ARCHITECTURE_R { + ARCHITECTURE_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bits 20:23 - Major revision number"] + #[inline(always)] + pub fn variant(&self) -> VARIANT_R { + VARIANT_R::new(((self.bits >> 20) & 0x0f) as u8) + } + #[doc = "Bits 24:31 - Implementer code, ARM=0x41"] + #[inline(always)] + pub fn implementer(&self) -> IMPLEMENTER_R { + IMPLEMENTER_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[doc = "CPUID Base Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cpuid](index.html) module"] +pub struct CPUID_SPEC; +impl crate::RegisterSpec for CPUID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cpuid::R](R) reader structure"] +impl crate::Readable for CPUID_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CPUID to value 0x410c_c601"] +impl crate::Resettable for CPUID_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x410c_c601 + } +} diff --git a/pac/atsamc20g/src/system_control/dfsr.rs b/pac/atsamc20g/src/system_control/dfsr.rs new file mode 100644 index 000000000000..948899af0905 --- /dev/null +++ b/pac/atsamc20g/src/system_control/dfsr.rs @@ -0,0 +1,301 @@ +#[doc = "Register `DFSR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DFSR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `HALTED` reader - Halt request debug event active"] +pub struct HALTED_R(crate::FieldReader); +impl HALTED_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HALTED_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HALTED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HALTED` writer - Halt request debug event active"] +pub struct HALTED_W<'a> { + w: &'a mut W, +} +impl<'a> HALTED_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `BKPT` reader - Breakpoint debug event"] +pub struct BKPT_R(crate::FieldReader); +impl BKPT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BKPT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BKPT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BKPT` writer - Breakpoint debug event"] +pub struct BKPT_W<'a> { + w: &'a mut W, +} +impl<'a> BKPT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `DWTTRAP` reader - DWT debug event"] +pub struct DWTTRAP_R(crate::FieldReader); +impl DWTTRAP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DWTTRAP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DWTTRAP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DWTTRAP` writer - DWT debug event"] +pub struct DWTTRAP_W<'a> { + w: &'a mut W, +} +impl<'a> DWTTRAP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `VCATCH` reader - Vector catch debug event"] +pub struct VCATCH_R(crate::FieldReader); +impl VCATCH_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + VCATCH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VCATCH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VCATCH` writer - Vector catch debug event"] +pub struct VCATCH_W<'a> { + w: &'a mut W, +} +impl<'a> VCATCH_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `EXTERNAL` reader - EDBGRQ debug event"] +pub struct EXTERNAL_R(crate::FieldReader); +impl EXTERNAL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTERNAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTERNAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTERNAL` writer - EDBGRQ debug event"] +pub struct EXTERNAL_W<'a> { + w: &'a mut W, +} +impl<'a> EXTERNAL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +impl R { + #[doc = "Bit 0 - Halt request debug event active"] + #[inline(always)] + pub fn halted(&self) -> HALTED_R { + HALTED_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Breakpoint debug event"] + #[inline(always)] + pub fn bkpt(&self) -> BKPT_R { + BKPT_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - DWT debug event"] + #[inline(always)] + pub fn dwttrap(&self) -> DWTTRAP_R { + DWTTRAP_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Vector catch debug event"] + #[inline(always)] + pub fn vcatch(&self) -> VCATCH_R { + VCATCH_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - EDBGRQ debug event"] + #[inline(always)] + pub fn external(&self) -> EXTERNAL_R { + EXTERNAL_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Halt request debug event active"] + #[inline(always)] + pub fn halted(&mut self) -> HALTED_W { + HALTED_W { w: self } + } + #[doc = "Bit 1 - Breakpoint debug event"] + #[inline(always)] + pub fn bkpt(&mut self) -> BKPT_W { + BKPT_W { w: self } + } + #[doc = "Bit 2 - DWT debug event"] + #[inline(always)] + pub fn dwttrap(&mut self) -> DWTTRAP_W { + DWTTRAP_W { w: self } + } + #[doc = "Bit 3 - Vector catch debug event"] + #[inline(always)] + pub fn vcatch(&mut self) -> VCATCH_W { + VCATCH_W { w: self } + } + #[doc = "Bit 4 - EDBGRQ debug event"] + #[inline(always)] + pub fn external(&mut self) -> EXTERNAL_W { + EXTERNAL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Fault Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dfsr](index.html) module"] +pub struct DFSR_SPEC; +impl crate::RegisterSpec for DFSR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dfsr::R](R) reader structure"] +impl crate::Readable for DFSR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dfsr::W](W) writer structure"] +impl crate::Writable for DFSR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DFSR to value 0"] +impl crate::Resettable for DFSR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/system_control/icsr.rs b/pac/atsamc20g/src/system_control/icsr.rs new file mode 100644 index 000000000000..7fe5fd412116 --- /dev/null +++ b/pac/atsamc20g/src/system_control/icsr.rs @@ -0,0 +1,704 @@ +#[doc = "Register `ICSR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ICSR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `VECTACTIVE` reader - Debug: Exception number of currently executing exception, or 0 if thread mode"] +pub struct VECTACTIVE_R(crate::FieldReader); +impl VECTACTIVE_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + VECTACTIVE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VECTACTIVE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VECTACTIVE` writer - Debug: Exception number of currently executing exception, or 0 if thread mode"] +pub struct VECTACTIVE_W<'a> { + w: &'a mut W, +} +impl<'a> VECTACTIVE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01ff) | (value as u32 & 0x01ff); + self.w + } +} +#[doc = "Field `VECTPENDING` reader - Exception number of the highest priority pending enabled exception"] +pub struct VECTPENDING_R(crate::FieldReader); +impl VECTPENDING_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + VECTPENDING_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VECTPENDING_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VECTPENDING` writer - Exception number of the highest priority pending enabled exception"] +pub struct VECTPENDING_W<'a> { + w: &'a mut W, +} +impl<'a> VECTPENDING_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01ff << 12)) | ((value as u32 & 0x01ff) << 12); + self.w + } +} +#[doc = "Field `ISRPENDING` reader - Debug: NVIC interrupt pending"] +pub struct ISRPENDING_R(crate::FieldReader); +impl ISRPENDING_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ISRPENDING_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ISRPENDING_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ISRPENDING` writer - Debug: NVIC interrupt pending"] +pub struct ISRPENDING_W<'a> { + w: &'a mut W, +} +impl<'a> ISRPENDING_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `ISRPREEMPT` reader - Debug: Pending exception serviced on exit from debug halt"] +pub struct ISRPREEMPT_R(crate::FieldReader); +impl ISRPREEMPT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ISRPREEMPT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ISRPREEMPT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ISRPREEMPT` writer - Debug: Pending exception serviced on exit from debug halt"] +pub struct ISRPREEMPT_W<'a> { + w: &'a mut W, +} +impl<'a> ISRPREEMPT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "SysTick exception clear-pending bit\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PENDSTCLR_A { + #[doc = "0: No effect"] + VALUE_0 = 0, + #[doc = "1: Removes the pending state from the SysTick exception"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PENDSTCLR_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PENDSTCLR` reader - SysTick exception clear-pending bit"] +pub struct PENDSTCLR_R(crate::FieldReader); +impl PENDSTCLR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDSTCLR_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PENDSTCLR_A { + match self.bits { + false => PENDSTCLR_A::VALUE_0, + true => PENDSTCLR_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == PENDSTCLR_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == PENDSTCLR_A::VALUE_1 + } +} +impl core::ops::Deref for PENDSTCLR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDSTCLR` writer - SysTick exception clear-pending bit"] +pub struct PENDSTCLR_W<'a> { + w: &'a mut W, +} +impl<'a> PENDSTCLR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PENDSTCLR_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "No effect"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(PENDSTCLR_A::VALUE_0) + } + #[doc = "Removes the pending state from the SysTick exception"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(PENDSTCLR_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "SysTick exception set-pending bit\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PENDSTSET_A { + #[doc = "0: Write: no effect; read: SysTick exception is not pending"] + VALUE_0 = 0, + #[doc = "1: Write: changes SysTick exception state to pending; read: SysTick exception is pending"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PENDSTSET_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PENDSTSET` reader - SysTick exception set-pending bit"] +pub struct PENDSTSET_R(crate::FieldReader); +impl PENDSTSET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDSTSET_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PENDSTSET_A { + match self.bits { + false => PENDSTSET_A::VALUE_0, + true => PENDSTSET_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == PENDSTSET_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == PENDSTSET_A::VALUE_1 + } +} +impl core::ops::Deref for PENDSTSET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDSTSET` writer - SysTick exception set-pending bit"] +pub struct PENDSTSET_W<'a> { + w: &'a mut W, +} +impl<'a> PENDSTSET_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PENDSTSET_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Write: no effect; read: SysTick exception is not pending"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(PENDSTSET_A::VALUE_0) + } + #[doc = "Write: changes SysTick exception state to pending; read: SysTick exception is pending"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(PENDSTSET_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "PendSV clear-pending bit\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PENDSVCLR_A { + #[doc = "0: No effect"] + VALUE_0 = 0, + #[doc = "1: Removes the pending state from the PendSV exception"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PENDSVCLR_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PENDSVCLR` reader - PendSV clear-pending bit"] +pub struct PENDSVCLR_R(crate::FieldReader); +impl PENDSVCLR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDSVCLR_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PENDSVCLR_A { + match self.bits { + false => PENDSVCLR_A::VALUE_0, + true => PENDSVCLR_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == PENDSVCLR_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == PENDSVCLR_A::VALUE_1 + } +} +impl core::ops::Deref for PENDSVCLR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDSVCLR` writer - PendSV clear-pending bit"] +pub struct PENDSVCLR_W<'a> { + w: &'a mut W, +} +impl<'a> PENDSVCLR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PENDSVCLR_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "No effect"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(PENDSVCLR_A::VALUE_0) + } + #[doc = "Removes the pending state from the PendSV exception"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(PENDSVCLR_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +#[doc = "PendSV set-pending bit\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PENDSVSET_A { + #[doc = "0: Write: no effect; read: PendSV exception is not pending"] + VALUE_0 = 0, + #[doc = "1: Write: changes PendSV exception state to pending; read: PendSV exception is pending"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PENDSVSET_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PENDSVSET` reader - PendSV set-pending bit"] +pub struct PENDSVSET_R(crate::FieldReader); +impl PENDSVSET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDSVSET_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PENDSVSET_A { + match self.bits { + false => PENDSVSET_A::VALUE_0, + true => PENDSVSET_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == PENDSVSET_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == PENDSVSET_A::VALUE_1 + } +} +impl core::ops::Deref for PENDSVSET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDSVSET` writer - PendSV set-pending bit"] +pub struct PENDSVSET_W<'a> { + w: &'a mut W, +} +impl<'a> PENDSVSET_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PENDSVSET_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Write: no effect; read: PendSV exception is not pending"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(PENDSVSET_A::VALUE_0) + } + #[doc = "Write: changes PendSV exception state to pending; read: PendSV exception is pending"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(PENDSVSET_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "NMI set-pending bit\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum NMIPENDSET_A { + #[doc = "0: Write: no effect; read: NMI exception is not pending"] + VALUE_0 = 0, + #[doc = "1: Write: changes NMI exception state to pending; read: NMI exception is pending"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NMIPENDSET_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NMIPENDSET` reader - NMI set-pending bit"] +pub struct NMIPENDSET_R(crate::FieldReader); +impl NMIPENDSET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NMIPENDSET_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> NMIPENDSET_A { + match self.bits { + false => NMIPENDSET_A::VALUE_0, + true => NMIPENDSET_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == NMIPENDSET_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == NMIPENDSET_A::VALUE_1 + } +} +impl core::ops::Deref for NMIPENDSET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NMIPENDSET` writer - NMI set-pending bit"] +pub struct NMIPENDSET_W<'a> { + w: &'a mut W, +} +impl<'a> NMIPENDSET_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: NMIPENDSET_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Write: no effect; read: NMI exception is not pending"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(NMIPENDSET_A::VALUE_0) + } + #[doc = "Write: changes NMI exception state to pending; read: NMI exception is pending"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(NMIPENDSET_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bits 0:8 - Debug: Exception number of currently executing exception, or 0 if thread mode"] + #[inline(always)] + pub fn vectactive(&self) -> VECTACTIVE_R { + VECTACTIVE_R::new((self.bits & 0x01ff) as u16) + } + #[doc = "Bits 12:20 - Exception number of the highest priority pending enabled exception"] + #[inline(always)] + pub fn vectpending(&self) -> VECTPENDING_R { + VECTPENDING_R::new(((self.bits >> 12) & 0x01ff) as u16) + } + #[doc = "Bit 22 - Debug: NVIC interrupt pending"] + #[inline(always)] + pub fn isrpending(&self) -> ISRPENDING_R { + ISRPENDING_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Debug: Pending exception serviced on exit from debug halt"] + #[inline(always)] + pub fn isrpreempt(&self) -> ISRPREEMPT_R { + ISRPREEMPT_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 25 - SysTick exception clear-pending bit"] + #[inline(always)] + pub fn pendstclr(&self) -> PENDSTCLR_R { + PENDSTCLR_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - SysTick exception set-pending bit"] + #[inline(always)] + pub fn pendstset(&self) -> PENDSTSET_R { + PENDSTSET_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - PendSV clear-pending bit"] + #[inline(always)] + pub fn pendsvclr(&self) -> PENDSVCLR_R { + PENDSVCLR_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28 - PendSV set-pending bit"] + #[inline(always)] + pub fn pendsvset(&self) -> PENDSVSET_R { + PENDSVSET_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 31 - NMI set-pending bit"] + #[inline(always)] + pub fn nmipendset(&self) -> NMIPENDSET_R { + NMIPENDSET_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:8 - Debug: Exception number of currently executing exception, or 0 if thread mode"] + #[inline(always)] + pub fn vectactive(&mut self) -> VECTACTIVE_W { + VECTACTIVE_W { w: self } + } + #[doc = "Bits 12:20 - Exception number of the highest priority pending enabled exception"] + #[inline(always)] + pub fn vectpending(&mut self) -> VECTPENDING_W { + VECTPENDING_W { w: self } + } + #[doc = "Bit 22 - Debug: NVIC interrupt pending"] + #[inline(always)] + pub fn isrpending(&mut self) -> ISRPENDING_W { + ISRPENDING_W { w: self } + } + #[doc = "Bit 23 - Debug: Pending exception serviced on exit from debug halt"] + #[inline(always)] + pub fn isrpreempt(&mut self) -> ISRPREEMPT_W { + ISRPREEMPT_W { w: self } + } + #[doc = "Bit 25 - SysTick exception clear-pending bit"] + #[inline(always)] + pub fn pendstclr(&mut self) -> PENDSTCLR_W { + PENDSTCLR_W { w: self } + } + #[doc = "Bit 26 - SysTick exception set-pending bit"] + #[inline(always)] + pub fn pendstset(&mut self) -> PENDSTSET_W { + PENDSTSET_W { w: self } + } + #[doc = "Bit 27 - PendSV clear-pending bit"] + #[inline(always)] + pub fn pendsvclr(&mut self) -> PENDSVCLR_W { + PENDSVCLR_W { w: self } + } + #[doc = "Bit 28 - PendSV set-pending bit"] + #[inline(always)] + pub fn pendsvset(&mut self) -> PENDSVSET_W { + PENDSVSET_W { w: self } + } + #[doc = "Bit 31 - NMI set-pending bit"] + #[inline(always)] + pub fn nmipendset(&mut self) -> NMIPENDSET_W { + NMIPENDSET_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Control and State Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [icsr](index.html) module"] +pub struct ICSR_SPEC; +impl crate::RegisterSpec for ICSR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [icsr::R](R) reader structure"] +impl crate::Readable for ICSR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [icsr::W](W) writer structure"] +impl crate::Writable for ICSR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ICSR to value 0"] +impl crate::Resettable for ICSR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/system_control/scr.rs b/pac/atsamc20g/src/system_control/scr.rs new file mode 100644 index 000000000000..db9c54fe6f6f --- /dev/null +++ b/pac/atsamc20g/src/system_control/scr.rs @@ -0,0 +1,348 @@ +#[doc = "Register `SCR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SCR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Sleep-On-Exit when exiting Handler mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SLEEPONEXIT_A { + #[doc = "0: O not sleep when returning to Thread mode"] + VALUE_0 = 0, + #[doc = "1: Enter sleep, or deep sleep, on return from an ISR"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SLEEPONEXIT_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SLEEPONEXIT` reader - Sleep-On-Exit when exiting Handler mode"] +pub struct SLEEPONEXIT_R(crate::FieldReader); +impl SLEEPONEXIT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLEEPONEXIT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SLEEPONEXIT_A { + match self.bits { + false => SLEEPONEXIT_A::VALUE_0, + true => SLEEPONEXIT_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == SLEEPONEXIT_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == SLEEPONEXIT_A::VALUE_1 + } +} +impl core::ops::Deref for SLEEPONEXIT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLEEPONEXIT` writer - Sleep-On-Exit when exiting Handler mode"] +pub struct SLEEPONEXIT_W<'a> { + w: &'a mut W, +} +impl<'a> SLEEPONEXIT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SLEEPONEXIT_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "O not sleep when returning to Thread mode"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(SLEEPONEXIT_A::VALUE_0) + } + #[doc = "Enter sleep, or deep sleep, on return from an ISR"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(SLEEPONEXIT_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Uses Deep Sleep as low power mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SLEEPDEEP_A { + #[doc = "0: Sleep"] + VALUE_0 = 0, + #[doc = "1: Deep sleep"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SLEEPDEEP_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SLEEPDEEP` reader - Uses Deep Sleep as low power mode"] +pub struct SLEEPDEEP_R(crate::FieldReader); +impl SLEEPDEEP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLEEPDEEP_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SLEEPDEEP_A { + match self.bits { + false => SLEEPDEEP_A::VALUE_0, + true => SLEEPDEEP_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == SLEEPDEEP_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == SLEEPDEEP_A::VALUE_1 + } +} +impl core::ops::Deref for SLEEPDEEP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLEEPDEEP` writer - Uses Deep Sleep as low power mode"] +pub struct SLEEPDEEP_W<'a> { + w: &'a mut W, +} +impl<'a> SLEEPDEEP_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SLEEPDEEP_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Sleep"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(SLEEPDEEP_A::VALUE_0) + } + #[doc = "Deep sleep"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(SLEEPDEEP_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Send Event on Pending bit\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SEVONPEND_A { + #[doc = "0: Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded"] + VALUE_0 = 0, + #[doc = "1: Enabled events and all interrupts, including disabled interrupts, can wakeup the processor"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SEVONPEND_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SEVONPEND` reader - Send Event on Pending bit"] +pub struct SEVONPEND_R(crate::FieldReader); +impl SEVONPEND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SEVONPEND_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SEVONPEND_A { + match self.bits { + false => SEVONPEND_A::VALUE_0, + true => SEVONPEND_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == SEVONPEND_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == SEVONPEND_A::VALUE_1 + } +} +impl core::ops::Deref for SEVONPEND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEVONPEND` writer - Send Event on Pending bit"] +pub struct SEVONPEND_W<'a> { + w: &'a mut W, +} +impl<'a> SEVONPEND_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SEVONPEND_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(SEVONPEND_A::VALUE_0) + } + #[doc = "Enabled events and all interrupts, including disabled interrupts, can wakeup the processor"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(SEVONPEND_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +impl R { + #[doc = "Bit 1 - Sleep-On-Exit when exiting Handler mode"] + #[inline(always)] + pub fn sleeponexit(&self) -> SLEEPONEXIT_R { + SLEEPONEXIT_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Uses Deep Sleep as low power mode"] + #[inline(always)] + pub fn sleepdeep(&self) -> SLEEPDEEP_R { + SLEEPDEEP_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 4 - Send Event on Pending bit"] + #[inline(always)] + pub fn sevonpend(&self) -> SEVONPEND_R { + SEVONPEND_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 1 - Sleep-On-Exit when exiting Handler mode"] + #[inline(always)] + pub fn sleeponexit(&mut self) -> SLEEPONEXIT_W { + SLEEPONEXIT_W { w: self } + } + #[doc = "Bit 2 - Uses Deep Sleep as low power mode"] + #[inline(always)] + pub fn sleepdeep(&mut self) -> SLEEPDEEP_W { + SLEEPDEEP_W { w: self } + } + #[doc = "Bit 4 - Send Event on Pending bit"] + #[inline(always)] + pub fn sevonpend(&mut self) -> SEVONPEND_W { + SEVONPEND_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "System Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [scr](index.html) module"] +pub struct SCR_SPEC; +impl crate::RegisterSpec for SCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [scr::R](R) reader structure"] +impl crate::Readable for SCR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [scr::W](W) writer structure"] +impl crate::Writable for SCR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SCR to value 0"] +impl crate::Resettable for SCR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/system_control/shcsr.rs b/pac/atsamc20g/src/system_control/shcsr.rs new file mode 100644 index 000000000000..bfba26ac06ad --- /dev/null +++ b/pac/atsamc20g/src/system_control/shcsr.rs @@ -0,0 +1,113 @@ +#[doc = "Register `SHCSR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SHCSR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SVCALLPENDED` reader - "] +pub struct SVCALLPENDED_R(crate::FieldReader); +impl SVCALLPENDED_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SVCALLPENDED_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SVCALLPENDED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SVCALLPENDED` writer - "] +pub struct SVCALLPENDED_W<'a> { + w: &'a mut W, +} +impl<'a> SVCALLPENDED_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 15"] + #[inline(always)] + pub fn svcallpended(&self) -> SVCALLPENDED_R { + SVCALLPENDED_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 15"] + #[inline(always)] + pub fn svcallpended(&mut self) -> SVCALLPENDED_W { + SVCALLPENDED_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "System Handler Control and State Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [shcsr](index.html) module"] +pub struct SHCSR_SPEC; +impl crate::RegisterSpec for SHCSR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [shcsr::R](R) reader structure"] +impl crate::Readable for SHCSR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [shcsr::W](W) writer structure"] +impl crate::Writable for SHCSR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SHCSR to value 0"] +impl crate::Resettable for SHCSR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/system_control/shpr2.rs b/pac/atsamc20g/src/system_control/shpr2.rs new file mode 100644 index 000000000000..5665d6a5e8a9 --- /dev/null +++ b/pac/atsamc20g/src/system_control/shpr2.rs @@ -0,0 +1,103 @@ +#[doc = "Register `SHPR2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SHPR2` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PRI_11` reader - Priority of system handler 11, SVCall"] +pub struct PRI_11_R(crate::FieldReader); +impl PRI_11_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRI_11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PRI_11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRI_11` writer - Priority of system handler 11, SVCall"] +pub struct PRI_11_W<'a> { + w: &'a mut W, +} +impl<'a> PRI_11_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 24)) | ((value as u32 & 0xff) << 24); + self.w + } +} +impl R { + #[doc = "Bits 24:31 - Priority of system handler 11, SVCall"] + #[inline(always)] + pub fn pri_11(&self) -> PRI_11_R { + PRI_11_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 24:31 - Priority of system handler 11, SVCall"] + #[inline(always)] + pub fn pri_11(&mut self) -> PRI_11_W { + PRI_11_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "System Handler Priority Register 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [shpr2](index.html) module"] +pub struct SHPR2_SPEC; +impl crate::RegisterSpec for SHPR2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [shpr2::R](R) reader structure"] +impl crate::Readable for SHPR2_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [shpr2::W](W) writer structure"] +impl crate::Writable for SHPR2_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SHPR2 to value 0"] +impl crate::Resettable for SHPR2_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/system_control/shpr3.rs b/pac/atsamc20g/src/system_control/shpr3.rs new file mode 100644 index 000000000000..cb5a92c53503 --- /dev/null +++ b/pac/atsamc20g/src/system_control/shpr3.rs @@ -0,0 +1,140 @@ +#[doc = "Register `SHPR3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SHPR3` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PRI_14` reader - Priority of system handler 14, PendSV"] +pub struct PRI_14_R(crate::FieldReader); +impl PRI_14_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRI_14_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PRI_14_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRI_14` writer - Priority of system handler 14, PendSV"] +pub struct PRI_14_W<'a> { + w: &'a mut W, +} +impl<'a> PRI_14_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +#[doc = "Field `PRI_15` reader - Priority of system handler 15, SysTick exception"] +pub struct PRI_15_R(crate::FieldReader); +impl PRI_15_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRI_15_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PRI_15_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRI_15` writer - Priority of system handler 15, SysTick exception"] +pub struct PRI_15_W<'a> { + w: &'a mut W, +} +impl<'a> PRI_15_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 24)) | ((value as u32 & 0xff) << 24); + self.w + } +} +impl R { + #[doc = "Bits 16:23 - Priority of system handler 14, PendSV"] + #[inline(always)] + pub fn pri_14(&self) -> PRI_14_R { + PRI_14_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Priority of system handler 15, SysTick exception"] + #[inline(always)] + pub fn pri_15(&self) -> PRI_15_R { + PRI_15_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 16:23 - Priority of system handler 14, PendSV"] + #[inline(always)] + pub fn pri_14(&mut self) -> PRI_14_W { + PRI_14_W { w: self } + } + #[doc = "Bits 24:31 - Priority of system handler 15, SysTick exception"] + #[inline(always)] + pub fn pri_15(&mut self) -> PRI_15_W { + PRI_15_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "System Handler Priority Register 3\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [shpr3](index.html) module"] +pub struct SHPR3_SPEC; +impl crate::RegisterSpec for SHPR3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [shpr3::R](R) reader structure"] +impl crate::Readable for SHPR3_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [shpr3::W](W) writer structure"] +impl crate::Writable for SHPR3_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SHPR3 to value 0"] +impl crate::Resettable for SHPR3_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/system_control/vtor.rs b/pac/atsamc20g/src/system_control/vtor.rs new file mode 100644 index 000000000000..0ee4c7817817 --- /dev/null +++ b/pac/atsamc20g/src/system_control/vtor.rs @@ -0,0 +1,103 @@ +#[doc = "Register `VTOR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `VTOR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TBLOFF` reader - Vector table base offset"] +pub struct TBLOFF_R(crate::FieldReader); +impl TBLOFF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + TBLOFF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TBLOFF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TBLOFF` writer - Vector table base offset"] +pub struct TBLOFF_W<'a> { + w: &'a mut W, +} +impl<'a> TBLOFF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01ff_ffff << 7)) | ((value as u32 & 0x01ff_ffff) << 7); + self.w + } +} +impl R { + #[doc = "Bits 7:31 - Vector table base offset"] + #[inline(always)] + pub fn tbloff(&self) -> TBLOFF_R { + TBLOFF_R::new(((self.bits >> 7) & 0x01ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 7:31 - Vector table base offset"] + #[inline(always)] + pub fn tbloff(&mut self) -> TBLOFF_W { + TBLOFF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Vector Table Offset Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [vtor](index.html) module"] +pub struct VTOR_SPEC; +impl crate::RegisterSpec for VTOR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [vtor::R](R) reader structure"] +impl crate::Readable for VTOR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [vtor::W](W) writer structure"] +impl crate::Writable for VTOR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets VTOR to value 0"] +impl crate::Resettable for VTOR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/tc0.rs b/pac/atsamc20g/src/tc0.rs new file mode 100644 index 000000000000..86e973b276e7 --- /dev/null +++ b/pac/atsamc20g/src/tc0.rs @@ -0,0 +1,146 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved_0_count8: [u8; 0x38], +} +impl RegisterBlock { + #[doc = "0x00..0x38 - 32-bit Counter Mode"] + #[inline(always)] + pub fn count32(&self) -> &COUNT32 { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const COUNT32) } + } + #[doc = "0x00..0x34 - 16-bit Counter Mode"] + #[inline(always)] + pub fn count16(&self) -> &COUNT16 { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const COUNT16) } + } + #[doc = "0x00..0x32 - 8-bit Counter Mode"] + #[inline(always)] + pub fn count8(&self) -> &COUNT8 { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const COUNT8) } + } +} +#[doc = r"Register block"] +#[repr(C)] +pub struct COUNT8 { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - Control B Clear"] + pub ctrlbclr: crate::Reg, + #[doc = "0x05 - Control B Set"] + pub ctrlbset: crate::Reg, + #[doc = "0x06 - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x08 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x09 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x0a - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x0b - Status"] + pub status: crate::Reg, + #[doc = "0x0c - Waveform Generation Control"] + pub wave: crate::Reg, + #[doc = "0x0d - Control C"] + pub drvctrl: crate::Reg, + _reserved10: [u8; 0x01], + #[doc = "0x0f - Debug Control"] + pub dbgctrl: crate::Reg, + #[doc = "0x10 - Synchronization Status"] + pub syncbusy: crate::Reg, + #[doc = "0x14 - COUNT8 Count"] + pub count: crate::Reg, + _reserved13: [u8; 0x06], + #[doc = "0x1b - COUNT8 Period"] + pub per: crate::Reg, + #[doc = "0x1c - COUNT8 Compare and Capture"] + pub cc: [crate::Reg; 2], + _reserved15: [u8; 0x11], + #[doc = "0x2f - COUNT8 Period Buffer"] + pub perbuf: crate::Reg, + #[doc = "0x30 - COUNT8 Compare and Capture Buffer"] + pub ccbuf: [crate::Reg; 2], +} +#[doc = r"Register block"] +#[doc = "8-bit Counter Mode"] +pub mod count8; +#[doc = r"Register block"] +#[repr(C)] +pub struct COUNT16 { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - Control B Clear"] + pub ctrlbclr: crate::Reg, + #[doc = "0x05 - Control B Set"] + pub ctrlbset: crate::Reg, + #[doc = "0x06 - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x08 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x09 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x0a - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x0b - Status"] + pub status: crate::Reg, + #[doc = "0x0c - Waveform Generation Control"] + pub wave: crate::Reg, + #[doc = "0x0d - Control C"] + pub drvctrl: crate::Reg, + _reserved10: [u8; 0x01], + #[doc = "0x0f - Debug Control"] + pub dbgctrl: crate::Reg, + #[doc = "0x10 - Synchronization Status"] + pub syncbusy: crate::Reg, + #[doc = "0x14 - COUNT16 Count"] + pub count: crate::Reg, + _reserved13: [u8; 0x06], + #[doc = "0x1c - COUNT16 Compare and Capture"] + pub cc: [crate::Reg; 2], + _reserved14: [u8; 0x10], + #[doc = "0x30 - COUNT16 Compare and Capture Buffer"] + pub ccbuf: [crate::Reg; 2], +} +#[doc = r"Register block"] +#[doc = "16-bit Counter Mode"] +pub mod count16; +#[doc = r"Register block"] +#[repr(C)] +pub struct COUNT32 { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - Control B Clear"] + pub ctrlbclr: crate::Reg, + #[doc = "0x05 - Control B Set"] + pub ctrlbset: crate::Reg, + #[doc = "0x06 - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x08 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x09 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x0a - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x0b - Status"] + pub status: crate::Reg, + #[doc = "0x0c - Waveform Generation Control"] + pub wave: crate::Reg, + #[doc = "0x0d - Control C"] + pub drvctrl: crate::Reg, + _reserved10: [u8; 0x01], + #[doc = "0x0f - Debug Control"] + pub dbgctrl: crate::Reg, + #[doc = "0x10 - Synchronization Status"] + pub syncbusy: crate::Reg, + #[doc = "0x14 - COUNT32 Count"] + pub count: crate::Reg, + _reserved13: [u8; 0x04], + #[doc = "0x1c..0x24 - COUNT32 Compare and Capture"] + pub cc: [crate::Reg; 2], + _reserved14: [u8; 0x0c], + #[doc = "0x30..0x38 - COUNT32 Compare and Capture Buffer"] + pub ccbuf: [crate::Reg; 2], +} +#[doc = r"Register block"] +#[doc = "32-bit Counter Mode"] +pub mod count32; diff --git a/pac/atsamc20g/src/tc0/count16.rs b/pac/atsamc20g/src/tc0/count16.rs new file mode 100644 index 000000000000..5bd1e88c7efb --- /dev/null +++ b/pac/atsamc20g/src/tc0/count16.rs @@ -0,0 +1,60 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "CTRLBCLR register accessor: an alias for `Reg`"] +pub type CTRLBCLR = crate::Reg; +#[doc = "Control B Clear"] +pub mod ctrlbclr; +#[doc = "CTRLBSET register accessor: an alias for `Reg`"] +pub type CTRLBSET = crate::Reg; +#[doc = "Control B Set"] +pub mod ctrlbset; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "WAVE register accessor: an alias for `Reg`"] +pub type WAVE = crate::Reg; +#[doc = "Waveform Generation Control"] +pub mod wave; +#[doc = "DRVCTRL register accessor: an alias for `Reg`"] +pub type DRVCTRL = crate::Reg; +#[doc = "Control C"] +pub mod drvctrl; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Status"] +pub mod syncbusy; +#[doc = "COUNT register accessor: an alias for `Reg`"] +pub type COUNT = crate::Reg; +#[doc = "COUNT16 Count"] +pub mod count; +#[doc = "CC register accessor: an alias for `Reg`"] +pub type CC = crate::Reg; +#[doc = "COUNT16 Compare and Capture"] +pub mod cc; +#[doc = "CCBUF register accessor: an alias for `Reg`"] +pub type CCBUF = crate::Reg; +#[doc = "COUNT16 Compare and Capture Buffer"] +pub mod ccbuf; diff --git a/pac/atsamc20g/src/tc0/count16/cc.rs b/pac/atsamc20g/src/tc0/count16/cc.rs new file mode 100644 index 000000000000..b6f975905e31 --- /dev/null +++ b/pac/atsamc20g/src/tc0/count16/cc.rs @@ -0,0 +1,104 @@ +#[doc = "Register `CC[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CC[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CC` reader - Counter/Compare Value"] +pub struct CC_R(crate::FieldReader); +impl CC_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + CC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC` writer - Counter/Compare Value"] +pub struct CC_W<'a> { + w: &'a mut W, +} +impl<'a> CC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Counter/Compare Value"] + #[inline(always)] + pub fn cc(&self) -> CC_R { + CC_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Counter/Compare Value"] + #[inline(always)] + pub fn cc(&mut self) -> CC_W { + CC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT16 Compare and Capture\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc](index.html) module"] +pub struct CC_SPEC; +impl crate::RegisterSpec for CC_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [cc::R](R) reader structure"] +impl crate::Readable for CC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cc::W](W) writer structure"] +impl crate::Writable for CC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CC[%s] +to value 0"] +impl crate::Resettable for CC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/tc0/count16/ccbuf.rs b/pac/atsamc20g/src/tc0/count16/ccbuf.rs new file mode 100644 index 000000000000..2f922bba8d31 --- /dev/null +++ b/pac/atsamc20g/src/tc0/count16/ccbuf.rs @@ -0,0 +1,104 @@ +#[doc = "Register `CCBUF[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CCBUF[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CCBUF` reader - Counter/Compare Buffer Value"] +pub struct CCBUF_R(crate::FieldReader); +impl CCBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + CCBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUF` writer - Counter/Compare Buffer Value"] +pub struct CCBUF_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Counter/Compare Buffer Value"] + #[inline(always)] + pub fn ccbuf(&self) -> CCBUF_R { + CCBUF_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Counter/Compare Buffer Value"] + #[inline(always)] + pub fn ccbuf(&mut self) -> CCBUF_W { + CCBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT16 Compare and Capture Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccbuf](index.html) module"] +pub struct CCBUF_SPEC; +impl crate::RegisterSpec for CCBUF_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ccbuf::R](R) reader structure"] +impl crate::Readable for CCBUF_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ccbuf::W](W) writer structure"] +impl crate::Writable for CCBUF_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CCBUF[%s] +to value 0"] +impl crate::Resettable for CCBUF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/tc0/count16/count.rs b/pac/atsamc20g/src/tc0/count16/count.rs new file mode 100644 index 000000000000..5d26b509abb1 --- /dev/null +++ b/pac/atsamc20g/src/tc0/count16/count.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT16 Count\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count](index.html) module"] +pub struct COUNT_SPEC; +impl crate::RegisterSpec for COUNT_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [count::R](R) reader structure"] +impl crate::Readable for COUNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count::W](W) writer structure"] +impl crate::Writable for COUNT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT to value 0"] +impl crate::Resettable for COUNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/tc0/count16/ctrla.rs b/pac/atsamc20g/src/tc0/count16/ctrla.rs new file mode 100644 index 000000000000..cadcddaaead8 --- /dev/null +++ b/pac/atsamc20g/src/tc0/count16/ctrla.rs @@ -0,0 +1,851 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Timer Counter Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: Counter in 16-bit mode"] + COUNT16 = 0, + #[doc = "1: Counter in 8-bit mode"] + COUNT8 = 1, + #[doc = "2: Counter in 32-bit mode"] + COUNT32 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Timer Counter Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::COUNT16), + 1 => Some(MODE_A::COUNT8), + 2 => Some(MODE_A::COUNT32), + _ => None, + } + } + #[doc = "Checks if the value of the field is `COUNT16`"] + #[inline(always)] + pub fn is_count16(&self) -> bool { + **self == MODE_A::COUNT16 + } + #[doc = "Checks if the value of the field is `COUNT8`"] + #[inline(always)] + pub fn is_count8(&self) -> bool { + **self == MODE_A::COUNT8 + } + #[doc = "Checks if the value of the field is `COUNT32`"] + #[inline(always)] + pub fn is_count32(&self) -> bool { + **self == MODE_A::COUNT32 + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Timer Counter Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Counter in 16-bit mode"] + #[inline(always)] + pub fn count16(self) -> &'a mut W { + self.variant(MODE_A::COUNT16) + } + #[doc = "Counter in 8-bit mode"] + #[inline(always)] + pub fn count8(self) -> &'a mut W { + self.variant(MODE_A::COUNT8) + } + #[doc = "Counter in 32-bit mode"] + #[inline(always)] + pub fn count32(self) -> &'a mut W { + self.variant(MODE_A::COUNT32) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u32 & 0x03) << 2); + self.w + } +} +#[doc = "Prescaler and Counter Synchronization\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCSYNC_A { + #[doc = "0: Reload or reset the counter on next generic clock"] + GCLK = 0, + #[doc = "1: Reload or reset the counter on next prescaler clock"] + PRESC = 1, + #[doc = "2: Reload or reset the counter on next generic clock and reset the prescaler counter"] + RESYNC = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCSYNC_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCSYNC` reader - Prescaler and Counter Synchronization"] +pub struct PRESCSYNC_R(crate::FieldReader); +impl PRESCSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCSYNC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCSYNC_A::GCLK), + 1 => Some(PRESCSYNC_A::PRESC), + 2 => Some(PRESCSYNC_A::RESYNC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `GCLK`"] + #[inline(always)] + pub fn is_gclk(&self) -> bool { + **self == PRESCSYNC_A::GCLK + } + #[doc = "Checks if the value of the field is `PRESC`"] + #[inline(always)] + pub fn is_presc(&self) -> bool { + **self == PRESCSYNC_A::PRESC + } + #[doc = "Checks if the value of the field is `RESYNC`"] + #[inline(always)] + pub fn is_resync(&self) -> bool { + **self == PRESCSYNC_A::RESYNC + } +} +impl core::ops::Deref for PRESCSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCSYNC` writer - Prescaler and Counter Synchronization"] +pub struct PRESCSYNC_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCSYNC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCSYNC_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Reload or reset the counter on next generic clock"] + #[inline(always)] + pub fn gclk(self) -> &'a mut W { + self.variant(PRESCSYNC_A::GCLK) + } + #[doc = "Reload or reset the counter on next prescaler clock"] + #[inline(always)] + pub fn presc(self) -> &'a mut W { + self.variant(PRESCSYNC_A::PRESC) + } + #[doc = "Reload or reset the counter on next generic clock and reset the prescaler counter"] + #[inline(always)] + pub fn resync(self) -> &'a mut W { + self.variant(PRESCSYNC_A::RESYNC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u32 & 0x03) << 4); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - Clock On Demand"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - Clock On Demand"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: Prescaler: GCLK_TC"] + DIV1 = 0, + #[doc = "1: Prescaler: GCLK_TC/2"] + DIV2 = 1, + #[doc = "2: Prescaler: GCLK_TC/4"] + DIV4 = 2, + #[doc = "3: Prescaler: GCLK_TC/8"] + DIV8 = 3, + #[doc = "4: Prescaler: GCLK_TC/16"] + DIV16 = 4, + #[doc = "5: Prescaler: GCLK_TC/64"] + DIV64 = 5, + #[doc = "6: Prescaler: GCLK_TC/256"] + DIV256 = 6, + #[doc = "7: Prescaler: GCLK_TC/1024"] + DIV1024 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PRESCALER_A { + match self.bits { + 0 => PRESCALER_A::DIV1, + 1 => PRESCALER_A::DIV2, + 2 => PRESCALER_A::DIV4, + 3 => PRESCALER_A::DIV8, + 4 => PRESCALER_A::DIV16, + 5 => PRESCALER_A::DIV64, + 6 => PRESCALER_A::DIV256, + 7 => PRESCALER_A::DIV1024, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == PRESCALER_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PRESCALER_A::DIV1024 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Prescaler: GCLK_TC"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1) + } + #[doc = "Prescaler: GCLK_TC/2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "Prescaler: GCLK_TC/4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "Prescaler: GCLK_TC/8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "Prescaler: GCLK_TC/16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "Prescaler: GCLK_TC/64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "Prescaler: GCLK_TC/256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = "Prescaler: GCLK_TC/1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +#[doc = "Field `ALOCK` reader - Auto Lock"] +pub struct ALOCK_R(crate::FieldReader); +impl ALOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALOCK` writer - Auto Lock"] +pub struct ALOCK_W<'a> { + w: &'a mut W, +} +impl<'a> ALOCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `CAPTEN0` reader - Capture Channel 0 Enable"] +pub struct CAPTEN0_R(crate::FieldReader); +impl CAPTEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CAPTEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CAPTEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAPTEN0` writer - Capture Channel 0 Enable"] +pub struct CAPTEN0_W<'a> { + w: &'a mut W, +} +impl<'a> CAPTEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `CAPTEN1` reader - Capture Channel 1 Enable"] +pub struct CAPTEN1_R(crate::FieldReader); +impl CAPTEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CAPTEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CAPTEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAPTEN1` writer - Capture Channel 1 Enable"] +pub struct CAPTEN1_W<'a> { + w: &'a mut W, +} +impl<'a> CAPTEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `COPEN0` reader - Capture On Pin 0 Enable"] +pub struct COPEN0_R(crate::FieldReader); +impl COPEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COPEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COPEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COPEN0` writer - Capture On Pin 0 Enable"] +pub struct COPEN0_W<'a> { + w: &'a mut W, +} +impl<'a> COPEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `COPEN1` reader - Capture On Pin 1 Enable"] +pub struct COPEN1_R(crate::FieldReader); +impl COPEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COPEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COPEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COPEN1` writer - Capture On Pin 1 Enable"] +pub struct COPEN1_W<'a> { + w: &'a mut W, +} +impl<'a> COPEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:3 - Timer Counter Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bits 4:5 - Prescaler and Counter Synchronization"] + #[inline(always)] + pub fn prescsync(&self) -> PRESCSYNC_R { + PRESCSYNC_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Clock On Demand"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 11 - Auto Lock"] + #[inline(always)] + pub fn alock(&self) -> ALOCK_R { + ALOCK_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 16 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn capten0(&self) -> CAPTEN0_R { + CAPTEN0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn capten1(&self) -> CAPTEN1_R { + CAPTEN1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 20 - Capture On Pin 0 Enable"] + #[inline(always)] + pub fn copen0(&self) -> COPEN0_R { + COPEN0_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Capture On Pin 1 Enable"] + #[inline(always)] + pub fn copen1(&self) -> COPEN1_R { + COPEN1_R::new(((self.bits >> 21) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:3 - Timer Counter Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bits 4:5 - Prescaler and Counter Synchronization"] + #[inline(always)] + pub fn prescsync(&mut self) -> PRESCSYNC_W { + PRESCSYNC_W { w: self } + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - Clock On Demand"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Bit 11 - Auto Lock"] + #[inline(always)] + pub fn alock(&mut self) -> ALOCK_W { + ALOCK_W { w: self } + } + #[doc = "Bit 16 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn capten0(&mut self) -> CAPTEN0_W { + CAPTEN0_W { w: self } + } + #[doc = "Bit 17 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn capten1(&mut self) -> CAPTEN1_W { + CAPTEN1_W { w: self } + } + #[doc = "Bit 20 - Capture On Pin 0 Enable"] + #[inline(always)] + pub fn copen0(&mut self) -> COPEN0_W { + COPEN0_W { w: self } + } + #[doc = "Bit 21 - Capture On Pin 1 Enable"] + #[inline(always)] + pub fn copen1(&mut self) -> COPEN1_W { + COPEN1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/tc0/count16/ctrlbclr.rs b/pac/atsamc20g/src/tc0/count16/ctrlbclr.rs new file mode 100644 index 000000000000..76265674036a --- /dev/null +++ b/pac/atsamc20g/src/tc0/count16/ctrlbclr.rs @@ -0,0 +1,345 @@ +#[doc = "Register `CTRLBCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Counter Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `LUPD` reader - Lock Update"] +pub struct LUPD_R(crate::FieldReader); +impl LUPD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LUPD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LUPD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LUPD` writer - Lock Update"] +pub struct LUPD_W<'a> { + w: &'a mut W, +} +impl<'a> LUPD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ONESHOT` reader - One-Shot on Counter"] +pub struct ONESHOT_R(crate::FieldReader); +impl ONESHOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONESHOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONESHOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONESHOT` writer - One-Shot on Counter"] +pub struct ONESHOT_W<'a> { + w: &'a mut W, +} +impl<'a> ONESHOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Force a start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force a stop"] + STOP = 2, + #[doc = "3: Force update of double-buffered register"] + UPDATE = 3, + #[doc = "4: Force a read synchronization of COUNT"] + READSYNC = 4, + #[doc = "5: One-shot DMA trigger"] + DMAOS = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NONE), + 1 => Some(CMD_A::RETRIGGER), + 2 => Some(CMD_A::STOP), + 3 => Some(CMD_A::UPDATE), + 4 => Some(CMD_A::READSYNC), + 5 => Some(CMD_A::DMAOS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == CMD_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == CMD_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == CMD_A::STOP + } + #[doc = "Checks if the value of the field is `UPDATE`"] + #[inline(always)] + pub fn is_update(&self) -> bool { + **self == CMD_A::UPDATE + } + #[doc = "Checks if the value of the field is `READSYNC`"] + #[inline(always)] + pub fn is_readsync(&self) -> bool { + **self == CMD_A::READSYNC + } + #[doc = "Checks if the value of the field is `DMAOS`"] + #[inline(always)] + pub fn is_dmaos(&self) -> bool { + **self == CMD_A::DMAOS + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMD_A::NONE) + } + #[doc = "Force a start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMD_A::RETRIGGER) + } + #[doc = "Force a stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMD_A::STOP) + } + #[doc = "Force update of double-buffered register"] + #[inline(always)] + pub fn update(self) -> &'a mut W { + self.variant(CMD_A::UPDATE) + } + #[doc = "Force a read synchronization of COUNT"] + #[inline(always)] + pub fn readsync(self) -> &'a mut W { + self.variant(CMD_A::READSYNC) + } + #[doc = "One-shot DMA trigger"] + #[inline(always)] + pub fn dmaos(self) -> &'a mut W { + self.variant(CMD_A::DMAOS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 5)) | ((value as u8 & 0x07) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&self) -> LUPD_R { + LUPD_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 5) & 0x07) as u8) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&mut self) -> LUPD_W { + LUPD_W { w: self } + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&mut self) -> ONESHOT_W { + ONESHOT_W { w: self } + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbclr](index.html) module"] +pub struct CTRLBCLR_SPEC; +impl crate::RegisterSpec for CTRLBCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbclr::R](R) reader structure"] +impl crate::Readable for CTRLBCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbclr::W](W) writer structure"] +impl crate::Writable for CTRLBCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLBCLR to value 0"] +impl crate::Resettable for CTRLBCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/tc0/count16/ctrlbset.rs b/pac/atsamc20g/src/tc0/count16/ctrlbset.rs new file mode 100644 index 000000000000..610914c9c7c8 --- /dev/null +++ b/pac/atsamc20g/src/tc0/count16/ctrlbset.rs @@ -0,0 +1,345 @@ +#[doc = "Register `CTRLBSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Counter Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `LUPD` reader - Lock Update"] +pub struct LUPD_R(crate::FieldReader); +impl LUPD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LUPD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LUPD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LUPD` writer - Lock Update"] +pub struct LUPD_W<'a> { + w: &'a mut W, +} +impl<'a> LUPD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ONESHOT` reader - One-Shot on Counter"] +pub struct ONESHOT_R(crate::FieldReader); +impl ONESHOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONESHOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONESHOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONESHOT` writer - One-Shot on Counter"] +pub struct ONESHOT_W<'a> { + w: &'a mut W, +} +impl<'a> ONESHOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Force a start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force a stop"] + STOP = 2, + #[doc = "3: Force update of double-buffered register"] + UPDATE = 3, + #[doc = "4: Force a read synchronization of COUNT"] + READSYNC = 4, + #[doc = "5: One-shot DMA trigger"] + DMAOS = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NONE), + 1 => Some(CMD_A::RETRIGGER), + 2 => Some(CMD_A::STOP), + 3 => Some(CMD_A::UPDATE), + 4 => Some(CMD_A::READSYNC), + 5 => Some(CMD_A::DMAOS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == CMD_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == CMD_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == CMD_A::STOP + } + #[doc = "Checks if the value of the field is `UPDATE`"] + #[inline(always)] + pub fn is_update(&self) -> bool { + **self == CMD_A::UPDATE + } + #[doc = "Checks if the value of the field is `READSYNC`"] + #[inline(always)] + pub fn is_readsync(&self) -> bool { + **self == CMD_A::READSYNC + } + #[doc = "Checks if the value of the field is `DMAOS`"] + #[inline(always)] + pub fn is_dmaos(&self) -> bool { + **self == CMD_A::DMAOS + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMD_A::NONE) + } + #[doc = "Force a start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMD_A::RETRIGGER) + } + #[doc = "Force a stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMD_A::STOP) + } + #[doc = "Force update of double-buffered register"] + #[inline(always)] + pub fn update(self) -> &'a mut W { + self.variant(CMD_A::UPDATE) + } + #[doc = "Force a read synchronization of COUNT"] + #[inline(always)] + pub fn readsync(self) -> &'a mut W { + self.variant(CMD_A::READSYNC) + } + #[doc = "One-shot DMA trigger"] + #[inline(always)] + pub fn dmaos(self) -> &'a mut W { + self.variant(CMD_A::DMAOS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 5)) | ((value as u8 & 0x07) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&self) -> LUPD_R { + LUPD_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 5) & 0x07) as u8) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&mut self) -> LUPD_W { + LUPD_W { w: self } + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&mut self) -> ONESHOT_W { + ONESHOT_W { w: self } + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbset](index.html) module"] +pub struct CTRLBSET_SPEC; +impl crate::RegisterSpec for CTRLBSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbset::R](R) reader structure"] +impl crate::Readable for CTRLBSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbset::W](W) writer structure"] +impl crate::Writable for CTRLBSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLBSET to value 0"] +impl crate::Resettable for CTRLBSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/tc0/count16/dbgctrl.rs b/pac/atsamc20g/src/tc0/count16/dbgctrl.rs new file mode 100644 index 000000000000..0383e70d0429 --- /dev/null +++ b/pac/atsamc20g/src/tc0/count16/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Run During Debug"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Run During Debug"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/tc0/count16/drvctrl.rs b/pac/atsamc20g/src/tc0/count16/drvctrl.rs new file mode 100644 index 000000000000..323926b4b22d --- /dev/null +++ b/pac/atsamc20g/src/tc0/count16/drvctrl.rs @@ -0,0 +1,160 @@ +#[doc = "Register `DRVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DRVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INVEN0` reader - Output Waveform Invert Enable 0"] +pub struct INVEN0_R(crate::FieldReader); +impl INVEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN0` writer - Output Waveform Invert Enable 0"] +pub struct INVEN0_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `INVEN1` reader - Output Waveform Invert Enable 1"] +pub struct INVEN1_R(crate::FieldReader); +impl INVEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN1` writer - Output Waveform Invert Enable 1"] +pub struct INVEN1_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - Output Waveform Invert Enable 0"] + #[inline(always)] + pub fn inven0(&self) -> INVEN0_R { + INVEN0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Output Waveform Invert Enable 1"] + #[inline(always)] + pub fn inven1(&self) -> INVEN1_R { + INVEN1_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Output Waveform Invert Enable 0"] + #[inline(always)] + pub fn inven0(&mut self) -> INVEN0_W { + INVEN0_W { w: self } + } + #[doc = "Bit 1 - Output Waveform Invert Enable 1"] + #[inline(always)] + pub fn inven1(&mut self) -> INVEN1_W { + INVEN1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control C\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [drvctrl](index.html) module"] +pub struct DRVCTRL_SPEC; +impl crate::RegisterSpec for DRVCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [drvctrl::R](R) reader structure"] +impl crate::Readable for DRVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [drvctrl::W](W) writer structure"] +impl crate::Writable for DRVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DRVCTRL to value 0"] +impl crate::Resettable for DRVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/tc0/count16/evctrl.rs b/pac/atsamc20g/src/tc0/count16/evctrl.rs new file mode 100644 index 000000000000..7d4c38d486c1 --- /dev/null +++ b/pac/atsamc20g/src/tc0/count16/evctrl.rs @@ -0,0 +1,465 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Event Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EVACT_A { + #[doc = "0: Event action disabled"] + OFF = 0, + #[doc = "1: Start, restart or retrigger TC on event"] + RETRIGGER = 1, + #[doc = "2: Count on event"] + COUNT = 2, + #[doc = "3: Start TC on event"] + START = 3, + #[doc = "4: Time stamp capture"] + STAMP = 4, + #[doc = "5: Period catured in CC0, pulse width in CC1"] + PPW = 5, + #[doc = "6: Period catured in CC1, pulse width in CC0"] + PWP = 6, + #[doc = "7: Pulse width capture"] + PW = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EVACT_A) -> Self { + variant as _ + } +} +#[doc = "Field `EVACT` reader - Event Action"] +pub struct EVACT_R(crate::FieldReader); +impl EVACT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVACT_A { + match self.bits { + 0 => EVACT_A::OFF, + 1 => EVACT_A::RETRIGGER, + 2 => EVACT_A::COUNT, + 3 => EVACT_A::START, + 4 => EVACT_A::STAMP, + 5 => EVACT_A::PPW, + 6 => EVACT_A::PWP, + 7 => EVACT_A::PW, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == EVACT_A::OFF + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == EVACT_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `COUNT`"] + #[inline(always)] + pub fn is_count(&self) -> bool { + **self == EVACT_A::COUNT + } + #[doc = "Checks if the value of the field is `START`"] + #[inline(always)] + pub fn is_start(&self) -> bool { + **self == EVACT_A::START + } + #[doc = "Checks if the value of the field is `STAMP`"] + #[inline(always)] + pub fn is_stamp(&self) -> bool { + **self == EVACT_A::STAMP + } + #[doc = "Checks if the value of the field is `PPW`"] + #[inline(always)] + pub fn is_ppw(&self) -> bool { + **self == EVACT_A::PPW + } + #[doc = "Checks if the value of the field is `PWP`"] + #[inline(always)] + pub fn is_pwp(&self) -> bool { + **self == EVACT_A::PWP + } + #[doc = "Checks if the value of the field is `PW`"] + #[inline(always)] + pub fn is_pw(&self) -> bool { + **self == EVACT_A::PW + } +} +impl core::ops::Deref for EVACT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT` writer - Event Action"] +pub struct EVACT_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EVACT_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Event action disabled"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(EVACT_A::OFF) + } + #[doc = "Start, restart or retrigger TC on event"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(EVACT_A::RETRIGGER) + } + #[doc = "Count on event"] + #[inline(always)] + pub fn count(self) -> &'a mut W { + self.variant(EVACT_A::COUNT) + } + #[doc = "Start TC on event"] + #[inline(always)] + pub fn start(self) -> &'a mut W { + self.variant(EVACT_A::START) + } + #[doc = "Time stamp capture"] + #[inline(always)] + pub fn stamp(self) -> &'a mut W { + self.variant(EVACT_A::STAMP) + } + #[doc = "Period catured in CC0, pulse width in CC1"] + #[inline(always)] + pub fn ppw(self) -> &'a mut W { + self.variant(EVACT_A::PPW) + } + #[doc = "Period catured in CC1, pulse width in CC0"] + #[inline(always)] + pub fn pwp(self) -> &'a mut W { + self.variant(EVACT_A::PWP) + } + #[doc = "Pulse width capture"] + #[inline(always)] + pub fn pw(self) -> &'a mut W { + self.variant(EVACT_A::PW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u16 & 0x07); + self.w + } +} +#[doc = "Field `TCINV` reader - TC Event Input Polarity"] +pub struct TCINV_R(crate::FieldReader); +impl TCINV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCINV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCINV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCINV` writer - TC Event Input Polarity"] +pub struct TCINV_W<'a> { + w: &'a mut W, +} +impl<'a> TCINV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `TCEI` reader - TC Event Enable"] +pub struct TCEI_R(crate::FieldReader); +impl TCEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCEI` writer - TC Event Enable"] +pub struct TCEI_W<'a> { + w: &'a mut W, +} +impl<'a> TCEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `OVFEO` reader - Event Output Enable"] +pub struct OVFEO_R(crate::FieldReader); +impl OVFEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVFEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVFEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVFEO` writer - Event Output Enable"] +pub struct OVFEO_W<'a> { + w: &'a mut W, +} +impl<'a> OVFEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `MCEO0` reader - MC Event Output Enable 0"] +pub struct MCEO0_R(crate::FieldReader); +impl MCEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO0` writer - MC Event Output Enable 0"] +pub struct MCEO0_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u16 & 0x01) << 12); + self.w + } +} +#[doc = "Field `MCEO1` reader - MC Event Output Enable 1"] +pub struct MCEO1_R(crate::FieldReader); +impl MCEO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO1` writer - MC Event Output Enable 1"] +pub struct MCEO1_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u16 & 0x01) << 13); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Event Action"] + #[inline(always)] + pub fn evact(&self) -> EVACT_R { + EVACT_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 4 - TC Event Input Polarity"] + #[inline(always)] + pub fn tcinv(&self) -> TCINV_R { + TCINV_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - TC Event Enable"] + #[inline(always)] + pub fn tcei(&self) -> TCEI_R { + TCEI_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 8 - Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&self) -> OVFEO_R { + OVFEO_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 12 - MC Event Output Enable 0"] + #[inline(always)] + pub fn mceo0(&self) -> MCEO0_R { + MCEO0_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - MC Event Output Enable 1"] + #[inline(always)] + pub fn mceo1(&self) -> MCEO1_R { + MCEO1_R::new(((self.bits >> 13) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Event Action"] + #[inline(always)] + pub fn evact(&mut self) -> EVACT_W { + EVACT_W { w: self } + } + #[doc = "Bit 4 - TC Event Input Polarity"] + #[inline(always)] + pub fn tcinv(&mut self) -> TCINV_W { + TCINV_W { w: self } + } + #[doc = "Bit 5 - TC Event Enable"] + #[inline(always)] + pub fn tcei(&mut self) -> TCEI_W { + TCEI_W { w: self } + } + #[doc = "Bit 8 - Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&mut self) -> OVFEO_W { + OVFEO_W { w: self } + } + #[doc = "Bit 12 - MC Event Output Enable 0"] + #[inline(always)] + pub fn mceo0(&mut self) -> MCEO0_W { + MCEO0_W { w: self } + } + #[doc = "Bit 13 - MC Event Output Enable 1"] + #[inline(always)] + pub fn mceo1(&mut self) -> MCEO1_W { + MCEO1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/tc0/count16/intenclr.rs b/pac/atsamc20g/src/tc0/count16/intenclr.rs new file mode 100644 index 000000000000..af01ef5b7dca --- /dev/null +++ b/pac/atsamc20g/src/tc0/count16/intenclr.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - OVF Interrupt Disable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - OVF Interrupt Disable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - ERR Interrupt Disable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - ERR Interrupt Disable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MC0` reader - MC Interrupt Disable 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - MC Interrupt Disable 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - MC Interrupt Disable 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - MC Interrupt Disable 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - OVF Interrupt Disable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ERR Interrupt Disable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - MC Interrupt Disable 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - MC Interrupt Disable 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - OVF Interrupt Disable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - ERR Interrupt Disable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 4 - MC Interrupt Disable 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - MC Interrupt Disable 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/tc0/count16/intenset.rs b/pac/atsamc20g/src/tc0/count16/intenset.rs new file mode 100644 index 000000000000..0e1883a2f20a --- /dev/null +++ b/pac/atsamc20g/src/tc0/count16/intenset.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - OVF Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - OVF Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - ERR Interrupt Enable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - ERR Interrupt Enable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MC0` reader - MC Interrupt Enable 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - MC Interrupt Enable 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - MC Interrupt Enable 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - MC Interrupt Enable 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - OVF Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ERR Interrupt Enable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - MC Interrupt Enable 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - MC Interrupt Enable 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - OVF Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - ERR Interrupt Enable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 4 - MC Interrupt Enable 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - MC Interrupt Enable 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/tc0/count16/intflag.rs b/pac/atsamc20g/src/tc0/count16/intflag.rs new file mode 100644 index 000000000000..1dddffaf8e7f --- /dev/null +++ b/pac/atsamc20g/src/tc0/count16/intflag.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - OVF Interrupt Flag"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - OVF Interrupt Flag"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - ERR Interrupt Flag"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - ERR Interrupt Flag"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MC0` reader - MC Interrupt Flag 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - MC Interrupt Flag 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - MC Interrupt Flag 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - MC Interrupt Flag 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - OVF Interrupt Flag"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ERR Interrupt Flag"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - MC Interrupt Flag 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - MC Interrupt Flag 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - OVF Interrupt Flag"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - ERR Interrupt Flag"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 4 - MC Interrupt Flag 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - MC Interrupt Flag 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/tc0/count16/status.rs b/pac/atsamc20g/src/tc0/count16/status.rs new file mode 100644 index 000000000000..5088af446830 --- /dev/null +++ b/pac/atsamc20g/src/tc0/count16/status.rs @@ -0,0 +1,301 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `STOP` reader - Stop Status Flag"] +pub struct STOP_R(crate::FieldReader); +impl STOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STOP` writer - Stop Status Flag"] +pub struct STOP_W<'a> { + w: &'a mut W, +} +impl<'a> STOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SLAVE` reader - Slave Status Flag"] +pub struct SLAVE_R(crate::FieldReader); +impl SLAVE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLAVE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SLAVE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLAVE` writer - Slave Status Flag"] +pub struct SLAVE_W<'a> { + w: &'a mut W, +} +impl<'a> SLAVE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PERBUFV` reader - Synchronization Busy Status"] +pub struct PERBUFV_R(crate::FieldReader); +impl PERBUFV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PERBUFV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERBUFV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERBUFV` writer - Synchronization Busy Status"] +pub struct PERBUFV_W<'a> { + w: &'a mut W, +} +impl<'a> PERBUFV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CCBUFV0` reader - Compare channel buffer 0 valid"] +pub struct CCBUFV0_R(crate::FieldReader); +impl CCBUFV0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBUFV0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUFV0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUFV0` writer - Compare channel buffer 0 valid"] +pub struct CCBUFV0_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUFV0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `CCBUFV1` reader - Compare channel buffer 1 valid"] +pub struct CCBUFV1_R(crate::FieldReader); +impl CCBUFV1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBUFV1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUFV1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUFV1` writer - Compare channel buffer 1 valid"] +pub struct CCBUFV1_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUFV1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Stop Status Flag"] + #[inline(always)] + pub fn stop(&self) -> STOP_R { + STOP_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Slave Status Flag"] + #[inline(always)] + pub fn slave(&self) -> SLAVE_R { + SLAVE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 3 - Synchronization Busy Status"] + #[inline(always)] + pub fn perbufv(&self) -> PERBUFV_R { + PERBUFV_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Compare channel buffer 0 valid"] + #[inline(always)] + pub fn ccbufv0(&self) -> CCBUFV0_R { + CCBUFV0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Compare channel buffer 1 valid"] + #[inline(always)] + pub fn ccbufv1(&self) -> CCBUFV1_R { + CCBUFV1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Stop Status Flag"] + #[inline(always)] + pub fn stop(&mut self) -> STOP_W { + STOP_W { w: self } + } + #[doc = "Bit 1 - Slave Status Flag"] + #[inline(always)] + pub fn slave(&mut self) -> SLAVE_W { + SLAVE_W { w: self } + } + #[doc = "Bit 3 - Synchronization Busy Status"] + #[inline(always)] + pub fn perbufv(&mut self) -> PERBUFV_W { + PERBUFV_W { w: self } + } + #[doc = "Bit 4 - Compare channel buffer 0 valid"] + #[inline(always)] + pub fn ccbufv0(&mut self) -> CCBUFV0_W { + CCBUFV0_W { w: self } + } + #[doc = "Bit 5 - Compare channel buffer 1 valid"] + #[inline(always)] + pub fn ccbufv1(&mut self) -> CCBUFV1_W { + CCBUFV1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0x01"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pac/atsamc20g/src/tc0/count16/syncbusy.rs b/pac/atsamc20g/src/tc0/count16/syncbusy.rs new file mode 100644 index 000000000000..7ad8d91a84de --- /dev/null +++ b/pac/atsamc20g/src/tc0/count16/syncbusy.rs @@ -0,0 +1,193 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - swrst"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLB` reader - CTRLB"] +pub struct CTRLB_R(crate::FieldReader); +impl CTRLB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STATUS` reader - STATUS"] +pub struct STATUS_R(crate::FieldReader); +impl STATUS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STATUS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STATUS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` reader - Counter"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` reader - Period"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC0` reader - Compare Channel 0"] +pub struct CC0_R(crate::FieldReader); +impl CC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC1` reader - Compare Channel 1"] +pub struct CC1_R(crate::FieldReader); +impl CC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - swrst"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - CTRLB"] + #[inline(always)] + pub fn ctrlb(&self) -> CTRLB_R { + CTRLB_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - STATUS"] + #[inline(always)] + pub fn status(&self) -> STATUS_R { + STATUS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Counter"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Period"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Compare Channel 0"] + #[inline(always)] + pub fn cc0(&self) -> CC0_R { + CC0_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Compare Channel 1"] + #[inline(always)] + pub fn cc1(&self) -> CC1_R { + CC1_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +#[doc = "Synchronization Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/tc0/count16/wave.rs b/pac/atsamc20g/src/tc0/count16/wave.rs new file mode 100644 index 000000000000..46061b24b75d --- /dev/null +++ b/pac/atsamc20g/src/tc0/count16/wave.rs @@ -0,0 +1,178 @@ +#[doc = "Register `WAVE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WAVE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Waveform Generation Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WAVEGEN_A { + #[doc = "0: Normal frequency"] + NFRQ = 0, + #[doc = "1: Match frequency"] + MFRQ = 1, + #[doc = "2: Normal PWM"] + NPWM = 2, + #[doc = "3: Match PWM"] + MPWM = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WAVEGEN_A) -> Self { + variant as _ + } +} +#[doc = "Field `WAVEGEN` reader - Waveform Generation Mode"] +pub struct WAVEGEN_R(crate::FieldReader); +impl WAVEGEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WAVEGEN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> WAVEGEN_A { + match self.bits { + 0 => WAVEGEN_A::NFRQ, + 1 => WAVEGEN_A::MFRQ, + 2 => WAVEGEN_A::NPWM, + 3 => WAVEGEN_A::MPWM, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NFRQ`"] + #[inline(always)] + pub fn is_nfrq(&self) -> bool { + **self == WAVEGEN_A::NFRQ + } + #[doc = "Checks if the value of the field is `MFRQ`"] + #[inline(always)] + pub fn is_mfrq(&self) -> bool { + **self == WAVEGEN_A::MFRQ + } + #[doc = "Checks if the value of the field is `NPWM`"] + #[inline(always)] + pub fn is_npwm(&self) -> bool { + **self == WAVEGEN_A::NPWM + } + #[doc = "Checks if the value of the field is `MPWM`"] + #[inline(always)] + pub fn is_mpwm(&self) -> bool { + **self == WAVEGEN_A::MPWM + } +} +impl core::ops::Deref for WAVEGEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAVEGEN` writer - Waveform Generation Mode"] +pub struct WAVEGEN_W<'a> { + w: &'a mut W, +} +impl<'a> WAVEGEN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WAVEGEN_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Normal frequency"] + #[inline(always)] + pub fn nfrq(self) -> &'a mut W { + self.variant(WAVEGEN_A::NFRQ) + } + #[doc = "Match frequency"] + #[inline(always)] + pub fn mfrq(self) -> &'a mut W { + self.variant(WAVEGEN_A::MFRQ) + } + #[doc = "Normal PWM"] + #[inline(always)] + pub fn npwm(self) -> &'a mut W { + self.variant(WAVEGEN_A::NPWM) + } + #[doc = "Match PWM"] + #[inline(always)] + pub fn mpwm(self) -> &'a mut W { + self.variant(WAVEGEN_A::MPWM) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u8 & 0x03); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Waveform Generation Mode"] + #[inline(always)] + pub fn wavegen(&self) -> WAVEGEN_R { + WAVEGEN_R::new((self.bits & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Waveform Generation Mode"] + #[inline(always)] + pub fn wavegen(&mut self) -> WAVEGEN_W { + WAVEGEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Waveform Generation Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wave](index.html) module"] +pub struct WAVE_SPEC; +impl crate::RegisterSpec for WAVE_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [wave::R](R) reader structure"] +impl crate::Readable for WAVE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wave::W](W) writer structure"] +impl crate::Writable for WAVE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WAVE to value 0"] +impl crate::Resettable for WAVE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/tc0/count32.rs b/pac/atsamc20g/src/tc0/count32.rs new file mode 100644 index 000000000000..9062acfbbd7f --- /dev/null +++ b/pac/atsamc20g/src/tc0/count32.rs @@ -0,0 +1,60 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "CTRLBCLR register accessor: an alias for `Reg`"] +pub type CTRLBCLR = crate::Reg; +#[doc = "Control B Clear"] +pub mod ctrlbclr; +#[doc = "CTRLBSET register accessor: an alias for `Reg`"] +pub type CTRLBSET = crate::Reg; +#[doc = "Control B Set"] +pub mod ctrlbset; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "WAVE register accessor: an alias for `Reg`"] +pub type WAVE = crate::Reg; +#[doc = "Waveform Generation Control"] +pub mod wave; +#[doc = "DRVCTRL register accessor: an alias for `Reg`"] +pub type DRVCTRL = crate::Reg; +#[doc = "Control C"] +pub mod drvctrl; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Status"] +pub mod syncbusy; +#[doc = "COUNT register accessor: an alias for `Reg`"] +pub type COUNT = crate::Reg; +#[doc = "COUNT32 Count"] +pub mod count; +#[doc = "CC register accessor: an alias for `Reg`"] +pub type CC = crate::Reg; +#[doc = "COUNT32 Compare and Capture"] +pub mod cc; +#[doc = "CCBUF register accessor: an alias for `Reg`"] +pub type CCBUF = crate::Reg; +#[doc = "COUNT32 Compare and Capture Buffer"] +pub mod ccbuf; diff --git a/pac/atsamc20g/src/tc0/count32/cc.rs b/pac/atsamc20g/src/tc0/count32/cc.rs new file mode 100644 index 000000000000..512a1e01ffd4 --- /dev/null +++ b/pac/atsamc20g/src/tc0/count32/cc.rs @@ -0,0 +1,104 @@ +#[doc = "Register `CC[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CC[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CC` reader - Counter/Compare Value"] +pub struct CC_R(crate::FieldReader); +impl CC_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC` writer - Counter/Compare Value"] +pub struct CC_W<'a> { + w: &'a mut W, +} +impl<'a> CC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Counter/Compare Value"] + #[inline(always)] + pub fn cc(&self) -> CC_R { + CC_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Counter/Compare Value"] + #[inline(always)] + pub fn cc(&mut self) -> CC_W { + CC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT32 Compare and Capture\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc](index.html) module"] +pub struct CC_SPEC; +impl crate::RegisterSpec for CC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cc::R](R) reader structure"] +impl crate::Readable for CC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cc::W](W) writer structure"] +impl crate::Writable for CC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CC[%s] +to value 0"] +impl crate::Resettable for CC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/tc0/count32/ccbuf.rs b/pac/atsamc20g/src/tc0/count32/ccbuf.rs new file mode 100644 index 000000000000..9fb2d9f8f66c --- /dev/null +++ b/pac/atsamc20g/src/tc0/count32/ccbuf.rs @@ -0,0 +1,104 @@ +#[doc = "Register `CCBUF[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CCBUF[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CCBUF` reader - Counter/Compare Buffer Value"] +pub struct CCBUF_R(crate::FieldReader); +impl CCBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CCBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUF` writer - Counter/Compare Buffer Value"] +pub struct CCBUF_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Counter/Compare Buffer Value"] + #[inline(always)] + pub fn ccbuf(&self) -> CCBUF_R { + CCBUF_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Counter/Compare Buffer Value"] + #[inline(always)] + pub fn ccbuf(&mut self) -> CCBUF_W { + CCBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT32 Compare and Capture Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccbuf](index.html) module"] +pub struct CCBUF_SPEC; +impl crate::RegisterSpec for CCBUF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ccbuf::R](R) reader structure"] +impl crate::Readable for CCBUF_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ccbuf::W](W) writer structure"] +impl crate::Writable for CCBUF_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CCBUF[%s] +to value 0"] +impl crate::Resettable for CCBUF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/tc0/count32/count.rs b/pac/atsamc20g/src/tc0/count32/count.rs new file mode 100644 index 000000000000..9aea527a8b3c --- /dev/null +++ b/pac/atsamc20g/src/tc0/count32/count.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT32 Count\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count](index.html) module"] +pub struct COUNT_SPEC; +impl crate::RegisterSpec for COUNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [count::R](R) reader structure"] +impl crate::Readable for COUNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count::W](W) writer structure"] +impl crate::Writable for COUNT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT to value 0"] +impl crate::Resettable for COUNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/tc0/count32/ctrla.rs b/pac/atsamc20g/src/tc0/count32/ctrla.rs new file mode 100644 index 000000000000..cadcddaaead8 --- /dev/null +++ b/pac/atsamc20g/src/tc0/count32/ctrla.rs @@ -0,0 +1,851 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Timer Counter Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: Counter in 16-bit mode"] + COUNT16 = 0, + #[doc = "1: Counter in 8-bit mode"] + COUNT8 = 1, + #[doc = "2: Counter in 32-bit mode"] + COUNT32 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Timer Counter Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::COUNT16), + 1 => Some(MODE_A::COUNT8), + 2 => Some(MODE_A::COUNT32), + _ => None, + } + } + #[doc = "Checks if the value of the field is `COUNT16`"] + #[inline(always)] + pub fn is_count16(&self) -> bool { + **self == MODE_A::COUNT16 + } + #[doc = "Checks if the value of the field is `COUNT8`"] + #[inline(always)] + pub fn is_count8(&self) -> bool { + **self == MODE_A::COUNT8 + } + #[doc = "Checks if the value of the field is `COUNT32`"] + #[inline(always)] + pub fn is_count32(&self) -> bool { + **self == MODE_A::COUNT32 + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Timer Counter Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Counter in 16-bit mode"] + #[inline(always)] + pub fn count16(self) -> &'a mut W { + self.variant(MODE_A::COUNT16) + } + #[doc = "Counter in 8-bit mode"] + #[inline(always)] + pub fn count8(self) -> &'a mut W { + self.variant(MODE_A::COUNT8) + } + #[doc = "Counter in 32-bit mode"] + #[inline(always)] + pub fn count32(self) -> &'a mut W { + self.variant(MODE_A::COUNT32) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u32 & 0x03) << 2); + self.w + } +} +#[doc = "Prescaler and Counter Synchronization\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCSYNC_A { + #[doc = "0: Reload or reset the counter on next generic clock"] + GCLK = 0, + #[doc = "1: Reload or reset the counter on next prescaler clock"] + PRESC = 1, + #[doc = "2: Reload or reset the counter on next generic clock and reset the prescaler counter"] + RESYNC = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCSYNC_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCSYNC` reader - Prescaler and Counter Synchronization"] +pub struct PRESCSYNC_R(crate::FieldReader); +impl PRESCSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCSYNC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCSYNC_A::GCLK), + 1 => Some(PRESCSYNC_A::PRESC), + 2 => Some(PRESCSYNC_A::RESYNC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `GCLK`"] + #[inline(always)] + pub fn is_gclk(&self) -> bool { + **self == PRESCSYNC_A::GCLK + } + #[doc = "Checks if the value of the field is `PRESC`"] + #[inline(always)] + pub fn is_presc(&self) -> bool { + **self == PRESCSYNC_A::PRESC + } + #[doc = "Checks if the value of the field is `RESYNC`"] + #[inline(always)] + pub fn is_resync(&self) -> bool { + **self == PRESCSYNC_A::RESYNC + } +} +impl core::ops::Deref for PRESCSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCSYNC` writer - Prescaler and Counter Synchronization"] +pub struct PRESCSYNC_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCSYNC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCSYNC_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Reload or reset the counter on next generic clock"] + #[inline(always)] + pub fn gclk(self) -> &'a mut W { + self.variant(PRESCSYNC_A::GCLK) + } + #[doc = "Reload or reset the counter on next prescaler clock"] + #[inline(always)] + pub fn presc(self) -> &'a mut W { + self.variant(PRESCSYNC_A::PRESC) + } + #[doc = "Reload or reset the counter on next generic clock and reset the prescaler counter"] + #[inline(always)] + pub fn resync(self) -> &'a mut W { + self.variant(PRESCSYNC_A::RESYNC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u32 & 0x03) << 4); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - Clock On Demand"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - Clock On Demand"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: Prescaler: GCLK_TC"] + DIV1 = 0, + #[doc = "1: Prescaler: GCLK_TC/2"] + DIV2 = 1, + #[doc = "2: Prescaler: GCLK_TC/4"] + DIV4 = 2, + #[doc = "3: Prescaler: GCLK_TC/8"] + DIV8 = 3, + #[doc = "4: Prescaler: GCLK_TC/16"] + DIV16 = 4, + #[doc = "5: Prescaler: GCLK_TC/64"] + DIV64 = 5, + #[doc = "6: Prescaler: GCLK_TC/256"] + DIV256 = 6, + #[doc = "7: Prescaler: GCLK_TC/1024"] + DIV1024 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PRESCALER_A { + match self.bits { + 0 => PRESCALER_A::DIV1, + 1 => PRESCALER_A::DIV2, + 2 => PRESCALER_A::DIV4, + 3 => PRESCALER_A::DIV8, + 4 => PRESCALER_A::DIV16, + 5 => PRESCALER_A::DIV64, + 6 => PRESCALER_A::DIV256, + 7 => PRESCALER_A::DIV1024, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == PRESCALER_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PRESCALER_A::DIV1024 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Prescaler: GCLK_TC"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1) + } + #[doc = "Prescaler: GCLK_TC/2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "Prescaler: GCLK_TC/4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "Prescaler: GCLK_TC/8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "Prescaler: GCLK_TC/16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "Prescaler: GCLK_TC/64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "Prescaler: GCLK_TC/256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = "Prescaler: GCLK_TC/1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +#[doc = "Field `ALOCK` reader - Auto Lock"] +pub struct ALOCK_R(crate::FieldReader); +impl ALOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALOCK` writer - Auto Lock"] +pub struct ALOCK_W<'a> { + w: &'a mut W, +} +impl<'a> ALOCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `CAPTEN0` reader - Capture Channel 0 Enable"] +pub struct CAPTEN0_R(crate::FieldReader); +impl CAPTEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CAPTEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CAPTEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAPTEN0` writer - Capture Channel 0 Enable"] +pub struct CAPTEN0_W<'a> { + w: &'a mut W, +} +impl<'a> CAPTEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `CAPTEN1` reader - Capture Channel 1 Enable"] +pub struct CAPTEN1_R(crate::FieldReader); +impl CAPTEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CAPTEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CAPTEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAPTEN1` writer - Capture Channel 1 Enable"] +pub struct CAPTEN1_W<'a> { + w: &'a mut W, +} +impl<'a> CAPTEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `COPEN0` reader - Capture On Pin 0 Enable"] +pub struct COPEN0_R(crate::FieldReader); +impl COPEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COPEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COPEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COPEN0` writer - Capture On Pin 0 Enable"] +pub struct COPEN0_W<'a> { + w: &'a mut W, +} +impl<'a> COPEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `COPEN1` reader - Capture On Pin 1 Enable"] +pub struct COPEN1_R(crate::FieldReader); +impl COPEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COPEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COPEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COPEN1` writer - Capture On Pin 1 Enable"] +pub struct COPEN1_W<'a> { + w: &'a mut W, +} +impl<'a> COPEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:3 - Timer Counter Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bits 4:5 - Prescaler and Counter Synchronization"] + #[inline(always)] + pub fn prescsync(&self) -> PRESCSYNC_R { + PRESCSYNC_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Clock On Demand"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 11 - Auto Lock"] + #[inline(always)] + pub fn alock(&self) -> ALOCK_R { + ALOCK_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 16 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn capten0(&self) -> CAPTEN0_R { + CAPTEN0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn capten1(&self) -> CAPTEN1_R { + CAPTEN1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 20 - Capture On Pin 0 Enable"] + #[inline(always)] + pub fn copen0(&self) -> COPEN0_R { + COPEN0_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Capture On Pin 1 Enable"] + #[inline(always)] + pub fn copen1(&self) -> COPEN1_R { + COPEN1_R::new(((self.bits >> 21) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:3 - Timer Counter Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bits 4:5 - Prescaler and Counter Synchronization"] + #[inline(always)] + pub fn prescsync(&mut self) -> PRESCSYNC_W { + PRESCSYNC_W { w: self } + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - Clock On Demand"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Bit 11 - Auto Lock"] + #[inline(always)] + pub fn alock(&mut self) -> ALOCK_W { + ALOCK_W { w: self } + } + #[doc = "Bit 16 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn capten0(&mut self) -> CAPTEN0_W { + CAPTEN0_W { w: self } + } + #[doc = "Bit 17 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn capten1(&mut self) -> CAPTEN1_W { + CAPTEN1_W { w: self } + } + #[doc = "Bit 20 - Capture On Pin 0 Enable"] + #[inline(always)] + pub fn copen0(&mut self) -> COPEN0_W { + COPEN0_W { w: self } + } + #[doc = "Bit 21 - Capture On Pin 1 Enable"] + #[inline(always)] + pub fn copen1(&mut self) -> COPEN1_W { + COPEN1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/tc0/count32/ctrlbclr.rs b/pac/atsamc20g/src/tc0/count32/ctrlbclr.rs new file mode 100644 index 000000000000..76265674036a --- /dev/null +++ b/pac/atsamc20g/src/tc0/count32/ctrlbclr.rs @@ -0,0 +1,345 @@ +#[doc = "Register `CTRLBCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Counter Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `LUPD` reader - Lock Update"] +pub struct LUPD_R(crate::FieldReader); +impl LUPD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LUPD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LUPD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LUPD` writer - Lock Update"] +pub struct LUPD_W<'a> { + w: &'a mut W, +} +impl<'a> LUPD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ONESHOT` reader - One-Shot on Counter"] +pub struct ONESHOT_R(crate::FieldReader); +impl ONESHOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONESHOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONESHOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONESHOT` writer - One-Shot on Counter"] +pub struct ONESHOT_W<'a> { + w: &'a mut W, +} +impl<'a> ONESHOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Force a start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force a stop"] + STOP = 2, + #[doc = "3: Force update of double-buffered register"] + UPDATE = 3, + #[doc = "4: Force a read synchronization of COUNT"] + READSYNC = 4, + #[doc = "5: One-shot DMA trigger"] + DMAOS = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NONE), + 1 => Some(CMD_A::RETRIGGER), + 2 => Some(CMD_A::STOP), + 3 => Some(CMD_A::UPDATE), + 4 => Some(CMD_A::READSYNC), + 5 => Some(CMD_A::DMAOS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == CMD_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == CMD_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == CMD_A::STOP + } + #[doc = "Checks if the value of the field is `UPDATE`"] + #[inline(always)] + pub fn is_update(&self) -> bool { + **self == CMD_A::UPDATE + } + #[doc = "Checks if the value of the field is `READSYNC`"] + #[inline(always)] + pub fn is_readsync(&self) -> bool { + **self == CMD_A::READSYNC + } + #[doc = "Checks if the value of the field is `DMAOS`"] + #[inline(always)] + pub fn is_dmaos(&self) -> bool { + **self == CMD_A::DMAOS + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMD_A::NONE) + } + #[doc = "Force a start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMD_A::RETRIGGER) + } + #[doc = "Force a stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMD_A::STOP) + } + #[doc = "Force update of double-buffered register"] + #[inline(always)] + pub fn update(self) -> &'a mut W { + self.variant(CMD_A::UPDATE) + } + #[doc = "Force a read synchronization of COUNT"] + #[inline(always)] + pub fn readsync(self) -> &'a mut W { + self.variant(CMD_A::READSYNC) + } + #[doc = "One-shot DMA trigger"] + #[inline(always)] + pub fn dmaos(self) -> &'a mut W { + self.variant(CMD_A::DMAOS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 5)) | ((value as u8 & 0x07) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&self) -> LUPD_R { + LUPD_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 5) & 0x07) as u8) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&mut self) -> LUPD_W { + LUPD_W { w: self } + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&mut self) -> ONESHOT_W { + ONESHOT_W { w: self } + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbclr](index.html) module"] +pub struct CTRLBCLR_SPEC; +impl crate::RegisterSpec for CTRLBCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbclr::R](R) reader structure"] +impl crate::Readable for CTRLBCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbclr::W](W) writer structure"] +impl crate::Writable for CTRLBCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLBCLR to value 0"] +impl crate::Resettable for CTRLBCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/tc0/count32/ctrlbset.rs b/pac/atsamc20g/src/tc0/count32/ctrlbset.rs new file mode 100644 index 000000000000..610914c9c7c8 --- /dev/null +++ b/pac/atsamc20g/src/tc0/count32/ctrlbset.rs @@ -0,0 +1,345 @@ +#[doc = "Register `CTRLBSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Counter Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `LUPD` reader - Lock Update"] +pub struct LUPD_R(crate::FieldReader); +impl LUPD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LUPD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LUPD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LUPD` writer - Lock Update"] +pub struct LUPD_W<'a> { + w: &'a mut W, +} +impl<'a> LUPD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ONESHOT` reader - One-Shot on Counter"] +pub struct ONESHOT_R(crate::FieldReader); +impl ONESHOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONESHOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONESHOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONESHOT` writer - One-Shot on Counter"] +pub struct ONESHOT_W<'a> { + w: &'a mut W, +} +impl<'a> ONESHOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Force a start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force a stop"] + STOP = 2, + #[doc = "3: Force update of double-buffered register"] + UPDATE = 3, + #[doc = "4: Force a read synchronization of COUNT"] + READSYNC = 4, + #[doc = "5: One-shot DMA trigger"] + DMAOS = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NONE), + 1 => Some(CMD_A::RETRIGGER), + 2 => Some(CMD_A::STOP), + 3 => Some(CMD_A::UPDATE), + 4 => Some(CMD_A::READSYNC), + 5 => Some(CMD_A::DMAOS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == CMD_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == CMD_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == CMD_A::STOP + } + #[doc = "Checks if the value of the field is `UPDATE`"] + #[inline(always)] + pub fn is_update(&self) -> bool { + **self == CMD_A::UPDATE + } + #[doc = "Checks if the value of the field is `READSYNC`"] + #[inline(always)] + pub fn is_readsync(&self) -> bool { + **self == CMD_A::READSYNC + } + #[doc = "Checks if the value of the field is `DMAOS`"] + #[inline(always)] + pub fn is_dmaos(&self) -> bool { + **self == CMD_A::DMAOS + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMD_A::NONE) + } + #[doc = "Force a start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMD_A::RETRIGGER) + } + #[doc = "Force a stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMD_A::STOP) + } + #[doc = "Force update of double-buffered register"] + #[inline(always)] + pub fn update(self) -> &'a mut W { + self.variant(CMD_A::UPDATE) + } + #[doc = "Force a read synchronization of COUNT"] + #[inline(always)] + pub fn readsync(self) -> &'a mut W { + self.variant(CMD_A::READSYNC) + } + #[doc = "One-shot DMA trigger"] + #[inline(always)] + pub fn dmaos(self) -> &'a mut W { + self.variant(CMD_A::DMAOS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 5)) | ((value as u8 & 0x07) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&self) -> LUPD_R { + LUPD_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 5) & 0x07) as u8) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&mut self) -> LUPD_W { + LUPD_W { w: self } + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&mut self) -> ONESHOT_W { + ONESHOT_W { w: self } + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbset](index.html) module"] +pub struct CTRLBSET_SPEC; +impl crate::RegisterSpec for CTRLBSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbset::R](R) reader structure"] +impl crate::Readable for CTRLBSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbset::W](W) writer structure"] +impl crate::Writable for CTRLBSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLBSET to value 0"] +impl crate::Resettable for CTRLBSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/tc0/count32/dbgctrl.rs b/pac/atsamc20g/src/tc0/count32/dbgctrl.rs new file mode 100644 index 000000000000..0383e70d0429 --- /dev/null +++ b/pac/atsamc20g/src/tc0/count32/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Run During Debug"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Run During Debug"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/tc0/count32/drvctrl.rs b/pac/atsamc20g/src/tc0/count32/drvctrl.rs new file mode 100644 index 000000000000..323926b4b22d --- /dev/null +++ b/pac/atsamc20g/src/tc0/count32/drvctrl.rs @@ -0,0 +1,160 @@ +#[doc = "Register `DRVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DRVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INVEN0` reader - Output Waveform Invert Enable 0"] +pub struct INVEN0_R(crate::FieldReader); +impl INVEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN0` writer - Output Waveform Invert Enable 0"] +pub struct INVEN0_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `INVEN1` reader - Output Waveform Invert Enable 1"] +pub struct INVEN1_R(crate::FieldReader); +impl INVEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN1` writer - Output Waveform Invert Enable 1"] +pub struct INVEN1_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - Output Waveform Invert Enable 0"] + #[inline(always)] + pub fn inven0(&self) -> INVEN0_R { + INVEN0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Output Waveform Invert Enable 1"] + #[inline(always)] + pub fn inven1(&self) -> INVEN1_R { + INVEN1_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Output Waveform Invert Enable 0"] + #[inline(always)] + pub fn inven0(&mut self) -> INVEN0_W { + INVEN0_W { w: self } + } + #[doc = "Bit 1 - Output Waveform Invert Enable 1"] + #[inline(always)] + pub fn inven1(&mut self) -> INVEN1_W { + INVEN1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control C\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [drvctrl](index.html) module"] +pub struct DRVCTRL_SPEC; +impl crate::RegisterSpec for DRVCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [drvctrl::R](R) reader structure"] +impl crate::Readable for DRVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [drvctrl::W](W) writer structure"] +impl crate::Writable for DRVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DRVCTRL to value 0"] +impl crate::Resettable for DRVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/tc0/count32/evctrl.rs b/pac/atsamc20g/src/tc0/count32/evctrl.rs new file mode 100644 index 000000000000..7d4c38d486c1 --- /dev/null +++ b/pac/atsamc20g/src/tc0/count32/evctrl.rs @@ -0,0 +1,465 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Event Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EVACT_A { + #[doc = "0: Event action disabled"] + OFF = 0, + #[doc = "1: Start, restart or retrigger TC on event"] + RETRIGGER = 1, + #[doc = "2: Count on event"] + COUNT = 2, + #[doc = "3: Start TC on event"] + START = 3, + #[doc = "4: Time stamp capture"] + STAMP = 4, + #[doc = "5: Period catured in CC0, pulse width in CC1"] + PPW = 5, + #[doc = "6: Period catured in CC1, pulse width in CC0"] + PWP = 6, + #[doc = "7: Pulse width capture"] + PW = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EVACT_A) -> Self { + variant as _ + } +} +#[doc = "Field `EVACT` reader - Event Action"] +pub struct EVACT_R(crate::FieldReader); +impl EVACT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVACT_A { + match self.bits { + 0 => EVACT_A::OFF, + 1 => EVACT_A::RETRIGGER, + 2 => EVACT_A::COUNT, + 3 => EVACT_A::START, + 4 => EVACT_A::STAMP, + 5 => EVACT_A::PPW, + 6 => EVACT_A::PWP, + 7 => EVACT_A::PW, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == EVACT_A::OFF + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == EVACT_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `COUNT`"] + #[inline(always)] + pub fn is_count(&self) -> bool { + **self == EVACT_A::COUNT + } + #[doc = "Checks if the value of the field is `START`"] + #[inline(always)] + pub fn is_start(&self) -> bool { + **self == EVACT_A::START + } + #[doc = "Checks if the value of the field is `STAMP`"] + #[inline(always)] + pub fn is_stamp(&self) -> bool { + **self == EVACT_A::STAMP + } + #[doc = "Checks if the value of the field is `PPW`"] + #[inline(always)] + pub fn is_ppw(&self) -> bool { + **self == EVACT_A::PPW + } + #[doc = "Checks if the value of the field is `PWP`"] + #[inline(always)] + pub fn is_pwp(&self) -> bool { + **self == EVACT_A::PWP + } + #[doc = "Checks if the value of the field is `PW`"] + #[inline(always)] + pub fn is_pw(&self) -> bool { + **self == EVACT_A::PW + } +} +impl core::ops::Deref for EVACT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT` writer - Event Action"] +pub struct EVACT_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EVACT_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Event action disabled"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(EVACT_A::OFF) + } + #[doc = "Start, restart or retrigger TC on event"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(EVACT_A::RETRIGGER) + } + #[doc = "Count on event"] + #[inline(always)] + pub fn count(self) -> &'a mut W { + self.variant(EVACT_A::COUNT) + } + #[doc = "Start TC on event"] + #[inline(always)] + pub fn start(self) -> &'a mut W { + self.variant(EVACT_A::START) + } + #[doc = "Time stamp capture"] + #[inline(always)] + pub fn stamp(self) -> &'a mut W { + self.variant(EVACT_A::STAMP) + } + #[doc = "Period catured in CC0, pulse width in CC1"] + #[inline(always)] + pub fn ppw(self) -> &'a mut W { + self.variant(EVACT_A::PPW) + } + #[doc = "Period catured in CC1, pulse width in CC0"] + #[inline(always)] + pub fn pwp(self) -> &'a mut W { + self.variant(EVACT_A::PWP) + } + #[doc = "Pulse width capture"] + #[inline(always)] + pub fn pw(self) -> &'a mut W { + self.variant(EVACT_A::PW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u16 & 0x07); + self.w + } +} +#[doc = "Field `TCINV` reader - TC Event Input Polarity"] +pub struct TCINV_R(crate::FieldReader); +impl TCINV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCINV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCINV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCINV` writer - TC Event Input Polarity"] +pub struct TCINV_W<'a> { + w: &'a mut W, +} +impl<'a> TCINV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `TCEI` reader - TC Event Enable"] +pub struct TCEI_R(crate::FieldReader); +impl TCEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCEI` writer - TC Event Enable"] +pub struct TCEI_W<'a> { + w: &'a mut W, +} +impl<'a> TCEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `OVFEO` reader - Event Output Enable"] +pub struct OVFEO_R(crate::FieldReader); +impl OVFEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVFEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVFEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVFEO` writer - Event Output Enable"] +pub struct OVFEO_W<'a> { + w: &'a mut W, +} +impl<'a> OVFEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `MCEO0` reader - MC Event Output Enable 0"] +pub struct MCEO0_R(crate::FieldReader); +impl MCEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO0` writer - MC Event Output Enable 0"] +pub struct MCEO0_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u16 & 0x01) << 12); + self.w + } +} +#[doc = "Field `MCEO1` reader - MC Event Output Enable 1"] +pub struct MCEO1_R(crate::FieldReader); +impl MCEO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO1` writer - MC Event Output Enable 1"] +pub struct MCEO1_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u16 & 0x01) << 13); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Event Action"] + #[inline(always)] + pub fn evact(&self) -> EVACT_R { + EVACT_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 4 - TC Event Input Polarity"] + #[inline(always)] + pub fn tcinv(&self) -> TCINV_R { + TCINV_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - TC Event Enable"] + #[inline(always)] + pub fn tcei(&self) -> TCEI_R { + TCEI_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 8 - Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&self) -> OVFEO_R { + OVFEO_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 12 - MC Event Output Enable 0"] + #[inline(always)] + pub fn mceo0(&self) -> MCEO0_R { + MCEO0_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - MC Event Output Enable 1"] + #[inline(always)] + pub fn mceo1(&self) -> MCEO1_R { + MCEO1_R::new(((self.bits >> 13) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Event Action"] + #[inline(always)] + pub fn evact(&mut self) -> EVACT_W { + EVACT_W { w: self } + } + #[doc = "Bit 4 - TC Event Input Polarity"] + #[inline(always)] + pub fn tcinv(&mut self) -> TCINV_W { + TCINV_W { w: self } + } + #[doc = "Bit 5 - TC Event Enable"] + #[inline(always)] + pub fn tcei(&mut self) -> TCEI_W { + TCEI_W { w: self } + } + #[doc = "Bit 8 - Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&mut self) -> OVFEO_W { + OVFEO_W { w: self } + } + #[doc = "Bit 12 - MC Event Output Enable 0"] + #[inline(always)] + pub fn mceo0(&mut self) -> MCEO0_W { + MCEO0_W { w: self } + } + #[doc = "Bit 13 - MC Event Output Enable 1"] + #[inline(always)] + pub fn mceo1(&mut self) -> MCEO1_W { + MCEO1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/tc0/count32/intenclr.rs b/pac/atsamc20g/src/tc0/count32/intenclr.rs new file mode 100644 index 000000000000..af01ef5b7dca --- /dev/null +++ b/pac/atsamc20g/src/tc0/count32/intenclr.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - OVF Interrupt Disable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - OVF Interrupt Disable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - ERR Interrupt Disable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - ERR Interrupt Disable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MC0` reader - MC Interrupt Disable 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - MC Interrupt Disable 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - MC Interrupt Disable 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - MC Interrupt Disable 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - OVF Interrupt Disable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ERR Interrupt Disable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - MC Interrupt Disable 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - MC Interrupt Disable 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - OVF Interrupt Disable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - ERR Interrupt Disable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 4 - MC Interrupt Disable 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - MC Interrupt Disable 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/tc0/count32/intenset.rs b/pac/atsamc20g/src/tc0/count32/intenset.rs new file mode 100644 index 000000000000..0e1883a2f20a --- /dev/null +++ b/pac/atsamc20g/src/tc0/count32/intenset.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - OVF Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - OVF Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - ERR Interrupt Enable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - ERR Interrupt Enable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MC0` reader - MC Interrupt Enable 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - MC Interrupt Enable 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - MC Interrupt Enable 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - MC Interrupt Enable 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - OVF Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ERR Interrupt Enable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - MC Interrupt Enable 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - MC Interrupt Enable 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - OVF Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - ERR Interrupt Enable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 4 - MC Interrupt Enable 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - MC Interrupt Enable 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/tc0/count32/intflag.rs b/pac/atsamc20g/src/tc0/count32/intflag.rs new file mode 100644 index 000000000000..1dddffaf8e7f --- /dev/null +++ b/pac/atsamc20g/src/tc0/count32/intflag.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - OVF Interrupt Flag"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - OVF Interrupt Flag"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - ERR Interrupt Flag"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - ERR Interrupt Flag"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MC0` reader - MC Interrupt Flag 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - MC Interrupt Flag 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - MC Interrupt Flag 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - MC Interrupt Flag 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - OVF Interrupt Flag"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ERR Interrupt Flag"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - MC Interrupt Flag 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - MC Interrupt Flag 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - OVF Interrupt Flag"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - ERR Interrupt Flag"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 4 - MC Interrupt Flag 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - MC Interrupt Flag 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/tc0/count32/status.rs b/pac/atsamc20g/src/tc0/count32/status.rs new file mode 100644 index 000000000000..5088af446830 --- /dev/null +++ b/pac/atsamc20g/src/tc0/count32/status.rs @@ -0,0 +1,301 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `STOP` reader - Stop Status Flag"] +pub struct STOP_R(crate::FieldReader); +impl STOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STOP` writer - Stop Status Flag"] +pub struct STOP_W<'a> { + w: &'a mut W, +} +impl<'a> STOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SLAVE` reader - Slave Status Flag"] +pub struct SLAVE_R(crate::FieldReader); +impl SLAVE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLAVE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SLAVE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLAVE` writer - Slave Status Flag"] +pub struct SLAVE_W<'a> { + w: &'a mut W, +} +impl<'a> SLAVE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PERBUFV` reader - Synchronization Busy Status"] +pub struct PERBUFV_R(crate::FieldReader); +impl PERBUFV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PERBUFV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERBUFV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERBUFV` writer - Synchronization Busy Status"] +pub struct PERBUFV_W<'a> { + w: &'a mut W, +} +impl<'a> PERBUFV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CCBUFV0` reader - Compare channel buffer 0 valid"] +pub struct CCBUFV0_R(crate::FieldReader); +impl CCBUFV0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBUFV0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUFV0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUFV0` writer - Compare channel buffer 0 valid"] +pub struct CCBUFV0_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUFV0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `CCBUFV1` reader - Compare channel buffer 1 valid"] +pub struct CCBUFV1_R(crate::FieldReader); +impl CCBUFV1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBUFV1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUFV1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUFV1` writer - Compare channel buffer 1 valid"] +pub struct CCBUFV1_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUFV1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Stop Status Flag"] + #[inline(always)] + pub fn stop(&self) -> STOP_R { + STOP_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Slave Status Flag"] + #[inline(always)] + pub fn slave(&self) -> SLAVE_R { + SLAVE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 3 - Synchronization Busy Status"] + #[inline(always)] + pub fn perbufv(&self) -> PERBUFV_R { + PERBUFV_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Compare channel buffer 0 valid"] + #[inline(always)] + pub fn ccbufv0(&self) -> CCBUFV0_R { + CCBUFV0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Compare channel buffer 1 valid"] + #[inline(always)] + pub fn ccbufv1(&self) -> CCBUFV1_R { + CCBUFV1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Stop Status Flag"] + #[inline(always)] + pub fn stop(&mut self) -> STOP_W { + STOP_W { w: self } + } + #[doc = "Bit 1 - Slave Status Flag"] + #[inline(always)] + pub fn slave(&mut self) -> SLAVE_W { + SLAVE_W { w: self } + } + #[doc = "Bit 3 - Synchronization Busy Status"] + #[inline(always)] + pub fn perbufv(&mut self) -> PERBUFV_W { + PERBUFV_W { w: self } + } + #[doc = "Bit 4 - Compare channel buffer 0 valid"] + #[inline(always)] + pub fn ccbufv0(&mut self) -> CCBUFV0_W { + CCBUFV0_W { w: self } + } + #[doc = "Bit 5 - Compare channel buffer 1 valid"] + #[inline(always)] + pub fn ccbufv1(&mut self) -> CCBUFV1_W { + CCBUFV1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0x01"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pac/atsamc20g/src/tc0/count32/syncbusy.rs b/pac/atsamc20g/src/tc0/count32/syncbusy.rs new file mode 100644 index 000000000000..7ad8d91a84de --- /dev/null +++ b/pac/atsamc20g/src/tc0/count32/syncbusy.rs @@ -0,0 +1,193 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - swrst"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLB` reader - CTRLB"] +pub struct CTRLB_R(crate::FieldReader); +impl CTRLB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STATUS` reader - STATUS"] +pub struct STATUS_R(crate::FieldReader); +impl STATUS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STATUS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STATUS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` reader - Counter"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` reader - Period"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC0` reader - Compare Channel 0"] +pub struct CC0_R(crate::FieldReader); +impl CC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC1` reader - Compare Channel 1"] +pub struct CC1_R(crate::FieldReader); +impl CC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - swrst"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - CTRLB"] + #[inline(always)] + pub fn ctrlb(&self) -> CTRLB_R { + CTRLB_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - STATUS"] + #[inline(always)] + pub fn status(&self) -> STATUS_R { + STATUS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Counter"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Period"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Compare Channel 0"] + #[inline(always)] + pub fn cc0(&self) -> CC0_R { + CC0_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Compare Channel 1"] + #[inline(always)] + pub fn cc1(&self) -> CC1_R { + CC1_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +#[doc = "Synchronization Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/tc0/count32/wave.rs b/pac/atsamc20g/src/tc0/count32/wave.rs new file mode 100644 index 000000000000..46061b24b75d --- /dev/null +++ b/pac/atsamc20g/src/tc0/count32/wave.rs @@ -0,0 +1,178 @@ +#[doc = "Register `WAVE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WAVE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Waveform Generation Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WAVEGEN_A { + #[doc = "0: Normal frequency"] + NFRQ = 0, + #[doc = "1: Match frequency"] + MFRQ = 1, + #[doc = "2: Normal PWM"] + NPWM = 2, + #[doc = "3: Match PWM"] + MPWM = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WAVEGEN_A) -> Self { + variant as _ + } +} +#[doc = "Field `WAVEGEN` reader - Waveform Generation Mode"] +pub struct WAVEGEN_R(crate::FieldReader); +impl WAVEGEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WAVEGEN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> WAVEGEN_A { + match self.bits { + 0 => WAVEGEN_A::NFRQ, + 1 => WAVEGEN_A::MFRQ, + 2 => WAVEGEN_A::NPWM, + 3 => WAVEGEN_A::MPWM, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NFRQ`"] + #[inline(always)] + pub fn is_nfrq(&self) -> bool { + **self == WAVEGEN_A::NFRQ + } + #[doc = "Checks if the value of the field is `MFRQ`"] + #[inline(always)] + pub fn is_mfrq(&self) -> bool { + **self == WAVEGEN_A::MFRQ + } + #[doc = "Checks if the value of the field is `NPWM`"] + #[inline(always)] + pub fn is_npwm(&self) -> bool { + **self == WAVEGEN_A::NPWM + } + #[doc = "Checks if the value of the field is `MPWM`"] + #[inline(always)] + pub fn is_mpwm(&self) -> bool { + **self == WAVEGEN_A::MPWM + } +} +impl core::ops::Deref for WAVEGEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAVEGEN` writer - Waveform Generation Mode"] +pub struct WAVEGEN_W<'a> { + w: &'a mut W, +} +impl<'a> WAVEGEN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WAVEGEN_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Normal frequency"] + #[inline(always)] + pub fn nfrq(self) -> &'a mut W { + self.variant(WAVEGEN_A::NFRQ) + } + #[doc = "Match frequency"] + #[inline(always)] + pub fn mfrq(self) -> &'a mut W { + self.variant(WAVEGEN_A::MFRQ) + } + #[doc = "Normal PWM"] + #[inline(always)] + pub fn npwm(self) -> &'a mut W { + self.variant(WAVEGEN_A::NPWM) + } + #[doc = "Match PWM"] + #[inline(always)] + pub fn mpwm(self) -> &'a mut W { + self.variant(WAVEGEN_A::MPWM) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u8 & 0x03); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Waveform Generation Mode"] + #[inline(always)] + pub fn wavegen(&self) -> WAVEGEN_R { + WAVEGEN_R::new((self.bits & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Waveform Generation Mode"] + #[inline(always)] + pub fn wavegen(&mut self) -> WAVEGEN_W { + WAVEGEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Waveform Generation Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wave](index.html) module"] +pub struct WAVE_SPEC; +impl crate::RegisterSpec for WAVE_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [wave::R](R) reader structure"] +impl crate::Readable for WAVE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wave::W](W) writer structure"] +impl crate::Writable for WAVE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WAVE to value 0"] +impl crate::Resettable for WAVE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/tc0/count8.rs b/pac/atsamc20g/src/tc0/count8.rs new file mode 100644 index 000000000000..777da5744358 --- /dev/null +++ b/pac/atsamc20g/src/tc0/count8.rs @@ -0,0 +1,68 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "CTRLBCLR register accessor: an alias for `Reg`"] +pub type CTRLBCLR = crate::Reg; +#[doc = "Control B Clear"] +pub mod ctrlbclr; +#[doc = "CTRLBSET register accessor: an alias for `Reg`"] +pub type CTRLBSET = crate::Reg; +#[doc = "Control B Set"] +pub mod ctrlbset; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "WAVE register accessor: an alias for `Reg`"] +pub type WAVE = crate::Reg; +#[doc = "Waveform Generation Control"] +pub mod wave; +#[doc = "DRVCTRL register accessor: an alias for `Reg`"] +pub type DRVCTRL = crate::Reg; +#[doc = "Control C"] +pub mod drvctrl; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Status"] +pub mod syncbusy; +#[doc = "COUNT register accessor: an alias for `Reg`"] +pub type COUNT = crate::Reg; +#[doc = "COUNT8 Count"] +pub mod count; +#[doc = "PER register accessor: an alias for `Reg`"] +pub type PER = crate::Reg; +#[doc = "COUNT8 Period"] +pub mod per; +#[doc = "CC register accessor: an alias for `Reg`"] +pub type CC = crate::Reg; +#[doc = "COUNT8 Compare and Capture"] +pub mod cc; +#[doc = "PERBUF register accessor: an alias for `Reg`"] +pub type PERBUF = crate::Reg; +#[doc = "COUNT8 Period Buffer"] +pub mod perbuf; +#[doc = "CCBUF register accessor: an alias for `Reg`"] +pub type CCBUF = crate::Reg; +#[doc = "COUNT8 Compare and Capture Buffer"] +pub mod ccbuf; diff --git a/pac/atsamc20g/src/tc0/count8/cc.rs b/pac/atsamc20g/src/tc0/count8/cc.rs new file mode 100644 index 000000000000..45f5c29c89af --- /dev/null +++ b/pac/atsamc20g/src/tc0/count8/cc.rs @@ -0,0 +1,104 @@ +#[doc = "Register `CC[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CC[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CC` reader - Counter/Compare Value"] +pub struct CC_R(crate::FieldReader); +impl CC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC` writer - Counter/Compare Value"] +pub struct CC_W<'a> { + w: &'a mut W, +} +impl<'a> CC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Counter/Compare Value"] + #[inline(always)] + pub fn cc(&self) -> CC_R { + CC_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Counter/Compare Value"] + #[inline(always)] + pub fn cc(&mut self) -> CC_W { + CC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT8 Compare and Capture\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc](index.html) module"] +pub struct CC_SPEC; +impl crate::RegisterSpec for CC_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [cc::R](R) reader structure"] +impl crate::Readable for CC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cc::W](W) writer structure"] +impl crate::Writable for CC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CC[%s] +to value 0"] +impl crate::Resettable for CC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/tc0/count8/ccbuf.rs b/pac/atsamc20g/src/tc0/count8/ccbuf.rs new file mode 100644 index 000000000000..cd81b1219860 --- /dev/null +++ b/pac/atsamc20g/src/tc0/count8/ccbuf.rs @@ -0,0 +1,104 @@ +#[doc = "Register `CCBUF[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CCBUF[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CCBUF` reader - Counter/Compare Buffer Value"] +pub struct CCBUF_R(crate::FieldReader); +impl CCBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CCBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUF` writer - Counter/Compare Buffer Value"] +pub struct CCBUF_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Counter/Compare Buffer Value"] + #[inline(always)] + pub fn ccbuf(&self) -> CCBUF_R { + CCBUF_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Counter/Compare Buffer Value"] + #[inline(always)] + pub fn ccbuf(&mut self) -> CCBUF_W { + CCBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT8 Compare and Capture Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccbuf](index.html) module"] +pub struct CCBUF_SPEC; +impl crate::RegisterSpec for CCBUF_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ccbuf::R](R) reader structure"] +impl crate::Readable for CCBUF_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ccbuf::W](W) writer structure"] +impl crate::Writable for CCBUF_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CCBUF[%s] +to value 0"] +impl crate::Resettable for CCBUF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/tc0/count8/count.rs b/pac/atsamc20g/src/tc0/count8/count.rs new file mode 100644 index 000000000000..0edbb0f17bb7 --- /dev/null +++ b/pac/atsamc20g/src/tc0/count8/count.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT8 Count\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count](index.html) module"] +pub struct COUNT_SPEC; +impl crate::RegisterSpec for COUNT_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [count::R](R) reader structure"] +impl crate::Readable for COUNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count::W](W) writer structure"] +impl crate::Writable for COUNT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT to value 0"] +impl crate::Resettable for COUNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/tc0/count8/ctrla.rs b/pac/atsamc20g/src/tc0/count8/ctrla.rs new file mode 100644 index 000000000000..cadcddaaead8 --- /dev/null +++ b/pac/atsamc20g/src/tc0/count8/ctrla.rs @@ -0,0 +1,851 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Timer Counter Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: Counter in 16-bit mode"] + COUNT16 = 0, + #[doc = "1: Counter in 8-bit mode"] + COUNT8 = 1, + #[doc = "2: Counter in 32-bit mode"] + COUNT32 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Timer Counter Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::COUNT16), + 1 => Some(MODE_A::COUNT8), + 2 => Some(MODE_A::COUNT32), + _ => None, + } + } + #[doc = "Checks if the value of the field is `COUNT16`"] + #[inline(always)] + pub fn is_count16(&self) -> bool { + **self == MODE_A::COUNT16 + } + #[doc = "Checks if the value of the field is `COUNT8`"] + #[inline(always)] + pub fn is_count8(&self) -> bool { + **self == MODE_A::COUNT8 + } + #[doc = "Checks if the value of the field is `COUNT32`"] + #[inline(always)] + pub fn is_count32(&self) -> bool { + **self == MODE_A::COUNT32 + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Timer Counter Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Counter in 16-bit mode"] + #[inline(always)] + pub fn count16(self) -> &'a mut W { + self.variant(MODE_A::COUNT16) + } + #[doc = "Counter in 8-bit mode"] + #[inline(always)] + pub fn count8(self) -> &'a mut W { + self.variant(MODE_A::COUNT8) + } + #[doc = "Counter in 32-bit mode"] + #[inline(always)] + pub fn count32(self) -> &'a mut W { + self.variant(MODE_A::COUNT32) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u32 & 0x03) << 2); + self.w + } +} +#[doc = "Prescaler and Counter Synchronization\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCSYNC_A { + #[doc = "0: Reload or reset the counter on next generic clock"] + GCLK = 0, + #[doc = "1: Reload or reset the counter on next prescaler clock"] + PRESC = 1, + #[doc = "2: Reload or reset the counter on next generic clock and reset the prescaler counter"] + RESYNC = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCSYNC_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCSYNC` reader - Prescaler and Counter Synchronization"] +pub struct PRESCSYNC_R(crate::FieldReader); +impl PRESCSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCSYNC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCSYNC_A::GCLK), + 1 => Some(PRESCSYNC_A::PRESC), + 2 => Some(PRESCSYNC_A::RESYNC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `GCLK`"] + #[inline(always)] + pub fn is_gclk(&self) -> bool { + **self == PRESCSYNC_A::GCLK + } + #[doc = "Checks if the value of the field is `PRESC`"] + #[inline(always)] + pub fn is_presc(&self) -> bool { + **self == PRESCSYNC_A::PRESC + } + #[doc = "Checks if the value of the field is `RESYNC`"] + #[inline(always)] + pub fn is_resync(&self) -> bool { + **self == PRESCSYNC_A::RESYNC + } +} +impl core::ops::Deref for PRESCSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCSYNC` writer - Prescaler and Counter Synchronization"] +pub struct PRESCSYNC_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCSYNC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCSYNC_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Reload or reset the counter on next generic clock"] + #[inline(always)] + pub fn gclk(self) -> &'a mut W { + self.variant(PRESCSYNC_A::GCLK) + } + #[doc = "Reload or reset the counter on next prescaler clock"] + #[inline(always)] + pub fn presc(self) -> &'a mut W { + self.variant(PRESCSYNC_A::PRESC) + } + #[doc = "Reload or reset the counter on next generic clock and reset the prescaler counter"] + #[inline(always)] + pub fn resync(self) -> &'a mut W { + self.variant(PRESCSYNC_A::RESYNC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u32 & 0x03) << 4); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - Clock On Demand"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - Clock On Demand"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: Prescaler: GCLK_TC"] + DIV1 = 0, + #[doc = "1: Prescaler: GCLK_TC/2"] + DIV2 = 1, + #[doc = "2: Prescaler: GCLK_TC/4"] + DIV4 = 2, + #[doc = "3: Prescaler: GCLK_TC/8"] + DIV8 = 3, + #[doc = "4: Prescaler: GCLK_TC/16"] + DIV16 = 4, + #[doc = "5: Prescaler: GCLK_TC/64"] + DIV64 = 5, + #[doc = "6: Prescaler: GCLK_TC/256"] + DIV256 = 6, + #[doc = "7: Prescaler: GCLK_TC/1024"] + DIV1024 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PRESCALER_A { + match self.bits { + 0 => PRESCALER_A::DIV1, + 1 => PRESCALER_A::DIV2, + 2 => PRESCALER_A::DIV4, + 3 => PRESCALER_A::DIV8, + 4 => PRESCALER_A::DIV16, + 5 => PRESCALER_A::DIV64, + 6 => PRESCALER_A::DIV256, + 7 => PRESCALER_A::DIV1024, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == PRESCALER_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PRESCALER_A::DIV1024 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Prescaler: GCLK_TC"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1) + } + #[doc = "Prescaler: GCLK_TC/2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "Prescaler: GCLK_TC/4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "Prescaler: GCLK_TC/8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "Prescaler: GCLK_TC/16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "Prescaler: GCLK_TC/64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "Prescaler: GCLK_TC/256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = "Prescaler: GCLK_TC/1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +#[doc = "Field `ALOCK` reader - Auto Lock"] +pub struct ALOCK_R(crate::FieldReader); +impl ALOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALOCK` writer - Auto Lock"] +pub struct ALOCK_W<'a> { + w: &'a mut W, +} +impl<'a> ALOCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `CAPTEN0` reader - Capture Channel 0 Enable"] +pub struct CAPTEN0_R(crate::FieldReader); +impl CAPTEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CAPTEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CAPTEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAPTEN0` writer - Capture Channel 0 Enable"] +pub struct CAPTEN0_W<'a> { + w: &'a mut W, +} +impl<'a> CAPTEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `CAPTEN1` reader - Capture Channel 1 Enable"] +pub struct CAPTEN1_R(crate::FieldReader); +impl CAPTEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CAPTEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CAPTEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAPTEN1` writer - Capture Channel 1 Enable"] +pub struct CAPTEN1_W<'a> { + w: &'a mut W, +} +impl<'a> CAPTEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `COPEN0` reader - Capture On Pin 0 Enable"] +pub struct COPEN0_R(crate::FieldReader); +impl COPEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COPEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COPEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COPEN0` writer - Capture On Pin 0 Enable"] +pub struct COPEN0_W<'a> { + w: &'a mut W, +} +impl<'a> COPEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `COPEN1` reader - Capture On Pin 1 Enable"] +pub struct COPEN1_R(crate::FieldReader); +impl COPEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COPEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COPEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COPEN1` writer - Capture On Pin 1 Enable"] +pub struct COPEN1_W<'a> { + w: &'a mut W, +} +impl<'a> COPEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:3 - Timer Counter Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bits 4:5 - Prescaler and Counter Synchronization"] + #[inline(always)] + pub fn prescsync(&self) -> PRESCSYNC_R { + PRESCSYNC_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Clock On Demand"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 11 - Auto Lock"] + #[inline(always)] + pub fn alock(&self) -> ALOCK_R { + ALOCK_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 16 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn capten0(&self) -> CAPTEN0_R { + CAPTEN0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn capten1(&self) -> CAPTEN1_R { + CAPTEN1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 20 - Capture On Pin 0 Enable"] + #[inline(always)] + pub fn copen0(&self) -> COPEN0_R { + COPEN0_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Capture On Pin 1 Enable"] + #[inline(always)] + pub fn copen1(&self) -> COPEN1_R { + COPEN1_R::new(((self.bits >> 21) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:3 - Timer Counter Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bits 4:5 - Prescaler and Counter Synchronization"] + #[inline(always)] + pub fn prescsync(&mut self) -> PRESCSYNC_W { + PRESCSYNC_W { w: self } + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - Clock On Demand"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Bit 11 - Auto Lock"] + #[inline(always)] + pub fn alock(&mut self) -> ALOCK_W { + ALOCK_W { w: self } + } + #[doc = "Bit 16 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn capten0(&mut self) -> CAPTEN0_W { + CAPTEN0_W { w: self } + } + #[doc = "Bit 17 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn capten1(&mut self) -> CAPTEN1_W { + CAPTEN1_W { w: self } + } + #[doc = "Bit 20 - Capture On Pin 0 Enable"] + #[inline(always)] + pub fn copen0(&mut self) -> COPEN0_W { + COPEN0_W { w: self } + } + #[doc = "Bit 21 - Capture On Pin 1 Enable"] + #[inline(always)] + pub fn copen1(&mut self) -> COPEN1_W { + COPEN1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/tc0/count8/ctrlbclr.rs b/pac/atsamc20g/src/tc0/count8/ctrlbclr.rs new file mode 100644 index 000000000000..76265674036a --- /dev/null +++ b/pac/atsamc20g/src/tc0/count8/ctrlbclr.rs @@ -0,0 +1,345 @@ +#[doc = "Register `CTRLBCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Counter Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `LUPD` reader - Lock Update"] +pub struct LUPD_R(crate::FieldReader); +impl LUPD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LUPD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LUPD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LUPD` writer - Lock Update"] +pub struct LUPD_W<'a> { + w: &'a mut W, +} +impl<'a> LUPD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ONESHOT` reader - One-Shot on Counter"] +pub struct ONESHOT_R(crate::FieldReader); +impl ONESHOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONESHOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONESHOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONESHOT` writer - One-Shot on Counter"] +pub struct ONESHOT_W<'a> { + w: &'a mut W, +} +impl<'a> ONESHOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Force a start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force a stop"] + STOP = 2, + #[doc = "3: Force update of double-buffered register"] + UPDATE = 3, + #[doc = "4: Force a read synchronization of COUNT"] + READSYNC = 4, + #[doc = "5: One-shot DMA trigger"] + DMAOS = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NONE), + 1 => Some(CMD_A::RETRIGGER), + 2 => Some(CMD_A::STOP), + 3 => Some(CMD_A::UPDATE), + 4 => Some(CMD_A::READSYNC), + 5 => Some(CMD_A::DMAOS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == CMD_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == CMD_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == CMD_A::STOP + } + #[doc = "Checks if the value of the field is `UPDATE`"] + #[inline(always)] + pub fn is_update(&self) -> bool { + **self == CMD_A::UPDATE + } + #[doc = "Checks if the value of the field is `READSYNC`"] + #[inline(always)] + pub fn is_readsync(&self) -> bool { + **self == CMD_A::READSYNC + } + #[doc = "Checks if the value of the field is `DMAOS`"] + #[inline(always)] + pub fn is_dmaos(&self) -> bool { + **self == CMD_A::DMAOS + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMD_A::NONE) + } + #[doc = "Force a start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMD_A::RETRIGGER) + } + #[doc = "Force a stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMD_A::STOP) + } + #[doc = "Force update of double-buffered register"] + #[inline(always)] + pub fn update(self) -> &'a mut W { + self.variant(CMD_A::UPDATE) + } + #[doc = "Force a read synchronization of COUNT"] + #[inline(always)] + pub fn readsync(self) -> &'a mut W { + self.variant(CMD_A::READSYNC) + } + #[doc = "One-shot DMA trigger"] + #[inline(always)] + pub fn dmaos(self) -> &'a mut W { + self.variant(CMD_A::DMAOS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 5)) | ((value as u8 & 0x07) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&self) -> LUPD_R { + LUPD_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 5) & 0x07) as u8) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&mut self) -> LUPD_W { + LUPD_W { w: self } + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&mut self) -> ONESHOT_W { + ONESHOT_W { w: self } + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbclr](index.html) module"] +pub struct CTRLBCLR_SPEC; +impl crate::RegisterSpec for CTRLBCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbclr::R](R) reader structure"] +impl crate::Readable for CTRLBCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbclr::W](W) writer structure"] +impl crate::Writable for CTRLBCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLBCLR to value 0"] +impl crate::Resettable for CTRLBCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/tc0/count8/ctrlbset.rs b/pac/atsamc20g/src/tc0/count8/ctrlbset.rs new file mode 100644 index 000000000000..610914c9c7c8 --- /dev/null +++ b/pac/atsamc20g/src/tc0/count8/ctrlbset.rs @@ -0,0 +1,345 @@ +#[doc = "Register `CTRLBSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Counter Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `LUPD` reader - Lock Update"] +pub struct LUPD_R(crate::FieldReader); +impl LUPD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LUPD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LUPD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LUPD` writer - Lock Update"] +pub struct LUPD_W<'a> { + w: &'a mut W, +} +impl<'a> LUPD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ONESHOT` reader - One-Shot on Counter"] +pub struct ONESHOT_R(crate::FieldReader); +impl ONESHOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONESHOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONESHOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONESHOT` writer - One-Shot on Counter"] +pub struct ONESHOT_W<'a> { + w: &'a mut W, +} +impl<'a> ONESHOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Force a start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force a stop"] + STOP = 2, + #[doc = "3: Force update of double-buffered register"] + UPDATE = 3, + #[doc = "4: Force a read synchronization of COUNT"] + READSYNC = 4, + #[doc = "5: One-shot DMA trigger"] + DMAOS = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NONE), + 1 => Some(CMD_A::RETRIGGER), + 2 => Some(CMD_A::STOP), + 3 => Some(CMD_A::UPDATE), + 4 => Some(CMD_A::READSYNC), + 5 => Some(CMD_A::DMAOS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == CMD_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == CMD_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == CMD_A::STOP + } + #[doc = "Checks if the value of the field is `UPDATE`"] + #[inline(always)] + pub fn is_update(&self) -> bool { + **self == CMD_A::UPDATE + } + #[doc = "Checks if the value of the field is `READSYNC`"] + #[inline(always)] + pub fn is_readsync(&self) -> bool { + **self == CMD_A::READSYNC + } + #[doc = "Checks if the value of the field is `DMAOS`"] + #[inline(always)] + pub fn is_dmaos(&self) -> bool { + **self == CMD_A::DMAOS + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMD_A::NONE) + } + #[doc = "Force a start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMD_A::RETRIGGER) + } + #[doc = "Force a stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMD_A::STOP) + } + #[doc = "Force update of double-buffered register"] + #[inline(always)] + pub fn update(self) -> &'a mut W { + self.variant(CMD_A::UPDATE) + } + #[doc = "Force a read synchronization of COUNT"] + #[inline(always)] + pub fn readsync(self) -> &'a mut W { + self.variant(CMD_A::READSYNC) + } + #[doc = "One-shot DMA trigger"] + #[inline(always)] + pub fn dmaos(self) -> &'a mut W { + self.variant(CMD_A::DMAOS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 5)) | ((value as u8 & 0x07) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&self) -> LUPD_R { + LUPD_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 5) & 0x07) as u8) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&mut self) -> LUPD_W { + LUPD_W { w: self } + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&mut self) -> ONESHOT_W { + ONESHOT_W { w: self } + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbset](index.html) module"] +pub struct CTRLBSET_SPEC; +impl crate::RegisterSpec for CTRLBSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbset::R](R) reader structure"] +impl crate::Readable for CTRLBSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbset::W](W) writer structure"] +impl crate::Writable for CTRLBSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLBSET to value 0"] +impl crate::Resettable for CTRLBSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/tc0/count8/dbgctrl.rs b/pac/atsamc20g/src/tc0/count8/dbgctrl.rs new file mode 100644 index 000000000000..0383e70d0429 --- /dev/null +++ b/pac/atsamc20g/src/tc0/count8/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Run During Debug"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Run During Debug"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/tc0/count8/drvctrl.rs b/pac/atsamc20g/src/tc0/count8/drvctrl.rs new file mode 100644 index 000000000000..323926b4b22d --- /dev/null +++ b/pac/atsamc20g/src/tc0/count8/drvctrl.rs @@ -0,0 +1,160 @@ +#[doc = "Register `DRVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DRVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INVEN0` reader - Output Waveform Invert Enable 0"] +pub struct INVEN0_R(crate::FieldReader); +impl INVEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN0` writer - Output Waveform Invert Enable 0"] +pub struct INVEN0_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `INVEN1` reader - Output Waveform Invert Enable 1"] +pub struct INVEN1_R(crate::FieldReader); +impl INVEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN1` writer - Output Waveform Invert Enable 1"] +pub struct INVEN1_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - Output Waveform Invert Enable 0"] + #[inline(always)] + pub fn inven0(&self) -> INVEN0_R { + INVEN0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Output Waveform Invert Enable 1"] + #[inline(always)] + pub fn inven1(&self) -> INVEN1_R { + INVEN1_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Output Waveform Invert Enable 0"] + #[inline(always)] + pub fn inven0(&mut self) -> INVEN0_W { + INVEN0_W { w: self } + } + #[doc = "Bit 1 - Output Waveform Invert Enable 1"] + #[inline(always)] + pub fn inven1(&mut self) -> INVEN1_W { + INVEN1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control C\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [drvctrl](index.html) module"] +pub struct DRVCTRL_SPEC; +impl crate::RegisterSpec for DRVCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [drvctrl::R](R) reader structure"] +impl crate::Readable for DRVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [drvctrl::W](W) writer structure"] +impl crate::Writable for DRVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DRVCTRL to value 0"] +impl crate::Resettable for DRVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/tc0/count8/evctrl.rs b/pac/atsamc20g/src/tc0/count8/evctrl.rs new file mode 100644 index 000000000000..7d4c38d486c1 --- /dev/null +++ b/pac/atsamc20g/src/tc0/count8/evctrl.rs @@ -0,0 +1,465 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Event Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EVACT_A { + #[doc = "0: Event action disabled"] + OFF = 0, + #[doc = "1: Start, restart or retrigger TC on event"] + RETRIGGER = 1, + #[doc = "2: Count on event"] + COUNT = 2, + #[doc = "3: Start TC on event"] + START = 3, + #[doc = "4: Time stamp capture"] + STAMP = 4, + #[doc = "5: Period catured in CC0, pulse width in CC1"] + PPW = 5, + #[doc = "6: Period catured in CC1, pulse width in CC0"] + PWP = 6, + #[doc = "7: Pulse width capture"] + PW = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EVACT_A) -> Self { + variant as _ + } +} +#[doc = "Field `EVACT` reader - Event Action"] +pub struct EVACT_R(crate::FieldReader); +impl EVACT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVACT_A { + match self.bits { + 0 => EVACT_A::OFF, + 1 => EVACT_A::RETRIGGER, + 2 => EVACT_A::COUNT, + 3 => EVACT_A::START, + 4 => EVACT_A::STAMP, + 5 => EVACT_A::PPW, + 6 => EVACT_A::PWP, + 7 => EVACT_A::PW, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == EVACT_A::OFF + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == EVACT_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `COUNT`"] + #[inline(always)] + pub fn is_count(&self) -> bool { + **self == EVACT_A::COUNT + } + #[doc = "Checks if the value of the field is `START`"] + #[inline(always)] + pub fn is_start(&self) -> bool { + **self == EVACT_A::START + } + #[doc = "Checks if the value of the field is `STAMP`"] + #[inline(always)] + pub fn is_stamp(&self) -> bool { + **self == EVACT_A::STAMP + } + #[doc = "Checks if the value of the field is `PPW`"] + #[inline(always)] + pub fn is_ppw(&self) -> bool { + **self == EVACT_A::PPW + } + #[doc = "Checks if the value of the field is `PWP`"] + #[inline(always)] + pub fn is_pwp(&self) -> bool { + **self == EVACT_A::PWP + } + #[doc = "Checks if the value of the field is `PW`"] + #[inline(always)] + pub fn is_pw(&self) -> bool { + **self == EVACT_A::PW + } +} +impl core::ops::Deref for EVACT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT` writer - Event Action"] +pub struct EVACT_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EVACT_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Event action disabled"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(EVACT_A::OFF) + } + #[doc = "Start, restart or retrigger TC on event"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(EVACT_A::RETRIGGER) + } + #[doc = "Count on event"] + #[inline(always)] + pub fn count(self) -> &'a mut W { + self.variant(EVACT_A::COUNT) + } + #[doc = "Start TC on event"] + #[inline(always)] + pub fn start(self) -> &'a mut W { + self.variant(EVACT_A::START) + } + #[doc = "Time stamp capture"] + #[inline(always)] + pub fn stamp(self) -> &'a mut W { + self.variant(EVACT_A::STAMP) + } + #[doc = "Period catured in CC0, pulse width in CC1"] + #[inline(always)] + pub fn ppw(self) -> &'a mut W { + self.variant(EVACT_A::PPW) + } + #[doc = "Period catured in CC1, pulse width in CC0"] + #[inline(always)] + pub fn pwp(self) -> &'a mut W { + self.variant(EVACT_A::PWP) + } + #[doc = "Pulse width capture"] + #[inline(always)] + pub fn pw(self) -> &'a mut W { + self.variant(EVACT_A::PW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u16 & 0x07); + self.w + } +} +#[doc = "Field `TCINV` reader - TC Event Input Polarity"] +pub struct TCINV_R(crate::FieldReader); +impl TCINV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCINV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCINV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCINV` writer - TC Event Input Polarity"] +pub struct TCINV_W<'a> { + w: &'a mut W, +} +impl<'a> TCINV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `TCEI` reader - TC Event Enable"] +pub struct TCEI_R(crate::FieldReader); +impl TCEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCEI` writer - TC Event Enable"] +pub struct TCEI_W<'a> { + w: &'a mut W, +} +impl<'a> TCEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `OVFEO` reader - Event Output Enable"] +pub struct OVFEO_R(crate::FieldReader); +impl OVFEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVFEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVFEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVFEO` writer - Event Output Enable"] +pub struct OVFEO_W<'a> { + w: &'a mut W, +} +impl<'a> OVFEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `MCEO0` reader - MC Event Output Enable 0"] +pub struct MCEO0_R(crate::FieldReader); +impl MCEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO0` writer - MC Event Output Enable 0"] +pub struct MCEO0_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u16 & 0x01) << 12); + self.w + } +} +#[doc = "Field `MCEO1` reader - MC Event Output Enable 1"] +pub struct MCEO1_R(crate::FieldReader); +impl MCEO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO1` writer - MC Event Output Enable 1"] +pub struct MCEO1_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u16 & 0x01) << 13); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Event Action"] + #[inline(always)] + pub fn evact(&self) -> EVACT_R { + EVACT_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 4 - TC Event Input Polarity"] + #[inline(always)] + pub fn tcinv(&self) -> TCINV_R { + TCINV_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - TC Event Enable"] + #[inline(always)] + pub fn tcei(&self) -> TCEI_R { + TCEI_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 8 - Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&self) -> OVFEO_R { + OVFEO_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 12 - MC Event Output Enable 0"] + #[inline(always)] + pub fn mceo0(&self) -> MCEO0_R { + MCEO0_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - MC Event Output Enable 1"] + #[inline(always)] + pub fn mceo1(&self) -> MCEO1_R { + MCEO1_R::new(((self.bits >> 13) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Event Action"] + #[inline(always)] + pub fn evact(&mut self) -> EVACT_W { + EVACT_W { w: self } + } + #[doc = "Bit 4 - TC Event Input Polarity"] + #[inline(always)] + pub fn tcinv(&mut self) -> TCINV_W { + TCINV_W { w: self } + } + #[doc = "Bit 5 - TC Event Enable"] + #[inline(always)] + pub fn tcei(&mut self) -> TCEI_W { + TCEI_W { w: self } + } + #[doc = "Bit 8 - Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&mut self) -> OVFEO_W { + OVFEO_W { w: self } + } + #[doc = "Bit 12 - MC Event Output Enable 0"] + #[inline(always)] + pub fn mceo0(&mut self) -> MCEO0_W { + MCEO0_W { w: self } + } + #[doc = "Bit 13 - MC Event Output Enable 1"] + #[inline(always)] + pub fn mceo1(&mut self) -> MCEO1_W { + MCEO1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/tc0/count8/intenclr.rs b/pac/atsamc20g/src/tc0/count8/intenclr.rs new file mode 100644 index 000000000000..af01ef5b7dca --- /dev/null +++ b/pac/atsamc20g/src/tc0/count8/intenclr.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - OVF Interrupt Disable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - OVF Interrupt Disable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - ERR Interrupt Disable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - ERR Interrupt Disable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MC0` reader - MC Interrupt Disable 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - MC Interrupt Disable 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - MC Interrupt Disable 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - MC Interrupt Disable 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - OVF Interrupt Disable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ERR Interrupt Disable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - MC Interrupt Disable 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - MC Interrupt Disable 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - OVF Interrupt Disable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - ERR Interrupt Disable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 4 - MC Interrupt Disable 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - MC Interrupt Disable 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/tc0/count8/intenset.rs b/pac/atsamc20g/src/tc0/count8/intenset.rs new file mode 100644 index 000000000000..0e1883a2f20a --- /dev/null +++ b/pac/atsamc20g/src/tc0/count8/intenset.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - OVF Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - OVF Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - ERR Interrupt Enable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - ERR Interrupt Enable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MC0` reader - MC Interrupt Enable 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - MC Interrupt Enable 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - MC Interrupt Enable 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - MC Interrupt Enable 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - OVF Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ERR Interrupt Enable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - MC Interrupt Enable 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - MC Interrupt Enable 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - OVF Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - ERR Interrupt Enable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 4 - MC Interrupt Enable 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - MC Interrupt Enable 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/tc0/count8/intflag.rs b/pac/atsamc20g/src/tc0/count8/intflag.rs new file mode 100644 index 000000000000..1dddffaf8e7f --- /dev/null +++ b/pac/atsamc20g/src/tc0/count8/intflag.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - OVF Interrupt Flag"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - OVF Interrupt Flag"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - ERR Interrupt Flag"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - ERR Interrupt Flag"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MC0` reader - MC Interrupt Flag 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - MC Interrupt Flag 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - MC Interrupt Flag 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - MC Interrupt Flag 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - OVF Interrupt Flag"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ERR Interrupt Flag"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - MC Interrupt Flag 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - MC Interrupt Flag 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - OVF Interrupt Flag"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - ERR Interrupt Flag"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 4 - MC Interrupt Flag 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - MC Interrupt Flag 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/tc0/count8/per.rs b/pac/atsamc20g/src/tc0/count8/per.rs new file mode 100644 index 000000000000..c9ab52e247d8 --- /dev/null +++ b/pac/atsamc20g/src/tc0/count8/per.rs @@ -0,0 +1,103 @@ +#[doc = "Register `PER` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PER` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER` reader - Period Value"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` writer - Period Value"] +pub struct PER_W<'a> { + w: &'a mut W, +} +impl<'a> PER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Period Value"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Period Value"] + #[inline(always)] + pub fn per(&mut self) -> PER_W { + PER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT8 Period\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [per](index.html) module"] +pub struct PER_SPEC; +impl crate::RegisterSpec for PER_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [per::R](R) reader structure"] +impl crate::Readable for PER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [per::W](W) writer structure"] +impl crate::Writable for PER_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PER to value 0xff"] +impl crate::Resettable for PER_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xff + } +} diff --git a/pac/atsamc20g/src/tc0/count8/perbuf.rs b/pac/atsamc20g/src/tc0/count8/perbuf.rs new file mode 100644 index 000000000000..cbd500e2bbe1 --- /dev/null +++ b/pac/atsamc20g/src/tc0/count8/perbuf.rs @@ -0,0 +1,103 @@ +#[doc = "Register `PERBUF` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PERBUF` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PERBUF` reader - Period Buffer Value"] +pub struct PERBUF_R(crate::FieldReader); +impl PERBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PERBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERBUF` writer - Period Buffer Value"] +pub struct PERBUF_W<'a> { + w: &'a mut W, +} +impl<'a> PERBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Period Buffer Value"] + #[inline(always)] + pub fn perbuf(&self) -> PERBUF_R { + PERBUF_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Period Buffer Value"] + #[inline(always)] + pub fn perbuf(&mut self) -> PERBUF_W { + PERBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT8 Period Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [perbuf](index.html) module"] +pub struct PERBUF_SPEC; +impl crate::RegisterSpec for PERBUF_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [perbuf::R](R) reader structure"] +impl crate::Readable for PERBUF_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [perbuf::W](W) writer structure"] +impl crate::Writable for PERBUF_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PERBUF to value 0xff"] +impl crate::Resettable for PERBUF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xff + } +} diff --git a/pac/atsamc20g/src/tc0/count8/status.rs b/pac/atsamc20g/src/tc0/count8/status.rs new file mode 100644 index 000000000000..5088af446830 --- /dev/null +++ b/pac/atsamc20g/src/tc0/count8/status.rs @@ -0,0 +1,301 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `STOP` reader - Stop Status Flag"] +pub struct STOP_R(crate::FieldReader); +impl STOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STOP` writer - Stop Status Flag"] +pub struct STOP_W<'a> { + w: &'a mut W, +} +impl<'a> STOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SLAVE` reader - Slave Status Flag"] +pub struct SLAVE_R(crate::FieldReader); +impl SLAVE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLAVE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SLAVE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLAVE` writer - Slave Status Flag"] +pub struct SLAVE_W<'a> { + w: &'a mut W, +} +impl<'a> SLAVE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PERBUFV` reader - Synchronization Busy Status"] +pub struct PERBUFV_R(crate::FieldReader); +impl PERBUFV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PERBUFV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERBUFV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERBUFV` writer - Synchronization Busy Status"] +pub struct PERBUFV_W<'a> { + w: &'a mut W, +} +impl<'a> PERBUFV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CCBUFV0` reader - Compare channel buffer 0 valid"] +pub struct CCBUFV0_R(crate::FieldReader); +impl CCBUFV0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBUFV0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUFV0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUFV0` writer - Compare channel buffer 0 valid"] +pub struct CCBUFV0_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUFV0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `CCBUFV1` reader - Compare channel buffer 1 valid"] +pub struct CCBUFV1_R(crate::FieldReader); +impl CCBUFV1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBUFV1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUFV1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUFV1` writer - Compare channel buffer 1 valid"] +pub struct CCBUFV1_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUFV1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Stop Status Flag"] + #[inline(always)] + pub fn stop(&self) -> STOP_R { + STOP_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Slave Status Flag"] + #[inline(always)] + pub fn slave(&self) -> SLAVE_R { + SLAVE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 3 - Synchronization Busy Status"] + #[inline(always)] + pub fn perbufv(&self) -> PERBUFV_R { + PERBUFV_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Compare channel buffer 0 valid"] + #[inline(always)] + pub fn ccbufv0(&self) -> CCBUFV0_R { + CCBUFV0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Compare channel buffer 1 valid"] + #[inline(always)] + pub fn ccbufv1(&self) -> CCBUFV1_R { + CCBUFV1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Stop Status Flag"] + #[inline(always)] + pub fn stop(&mut self) -> STOP_W { + STOP_W { w: self } + } + #[doc = "Bit 1 - Slave Status Flag"] + #[inline(always)] + pub fn slave(&mut self) -> SLAVE_W { + SLAVE_W { w: self } + } + #[doc = "Bit 3 - Synchronization Busy Status"] + #[inline(always)] + pub fn perbufv(&mut self) -> PERBUFV_W { + PERBUFV_W { w: self } + } + #[doc = "Bit 4 - Compare channel buffer 0 valid"] + #[inline(always)] + pub fn ccbufv0(&mut self) -> CCBUFV0_W { + CCBUFV0_W { w: self } + } + #[doc = "Bit 5 - Compare channel buffer 1 valid"] + #[inline(always)] + pub fn ccbufv1(&mut self) -> CCBUFV1_W { + CCBUFV1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0x01"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pac/atsamc20g/src/tc0/count8/syncbusy.rs b/pac/atsamc20g/src/tc0/count8/syncbusy.rs new file mode 100644 index 000000000000..7ad8d91a84de --- /dev/null +++ b/pac/atsamc20g/src/tc0/count8/syncbusy.rs @@ -0,0 +1,193 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - swrst"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLB` reader - CTRLB"] +pub struct CTRLB_R(crate::FieldReader); +impl CTRLB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STATUS` reader - STATUS"] +pub struct STATUS_R(crate::FieldReader); +impl STATUS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STATUS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STATUS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` reader - Counter"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` reader - Period"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC0` reader - Compare Channel 0"] +pub struct CC0_R(crate::FieldReader); +impl CC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC1` reader - Compare Channel 1"] +pub struct CC1_R(crate::FieldReader); +impl CC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - swrst"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - CTRLB"] + #[inline(always)] + pub fn ctrlb(&self) -> CTRLB_R { + CTRLB_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - STATUS"] + #[inline(always)] + pub fn status(&self) -> STATUS_R { + STATUS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Counter"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Period"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Compare Channel 0"] + #[inline(always)] + pub fn cc0(&self) -> CC0_R { + CC0_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Compare Channel 1"] + #[inline(always)] + pub fn cc1(&self) -> CC1_R { + CC1_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +#[doc = "Synchronization Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/tc0/count8/wave.rs b/pac/atsamc20g/src/tc0/count8/wave.rs new file mode 100644 index 000000000000..46061b24b75d --- /dev/null +++ b/pac/atsamc20g/src/tc0/count8/wave.rs @@ -0,0 +1,178 @@ +#[doc = "Register `WAVE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WAVE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Waveform Generation Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WAVEGEN_A { + #[doc = "0: Normal frequency"] + NFRQ = 0, + #[doc = "1: Match frequency"] + MFRQ = 1, + #[doc = "2: Normal PWM"] + NPWM = 2, + #[doc = "3: Match PWM"] + MPWM = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WAVEGEN_A) -> Self { + variant as _ + } +} +#[doc = "Field `WAVEGEN` reader - Waveform Generation Mode"] +pub struct WAVEGEN_R(crate::FieldReader); +impl WAVEGEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WAVEGEN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> WAVEGEN_A { + match self.bits { + 0 => WAVEGEN_A::NFRQ, + 1 => WAVEGEN_A::MFRQ, + 2 => WAVEGEN_A::NPWM, + 3 => WAVEGEN_A::MPWM, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NFRQ`"] + #[inline(always)] + pub fn is_nfrq(&self) -> bool { + **self == WAVEGEN_A::NFRQ + } + #[doc = "Checks if the value of the field is `MFRQ`"] + #[inline(always)] + pub fn is_mfrq(&self) -> bool { + **self == WAVEGEN_A::MFRQ + } + #[doc = "Checks if the value of the field is `NPWM`"] + #[inline(always)] + pub fn is_npwm(&self) -> bool { + **self == WAVEGEN_A::NPWM + } + #[doc = "Checks if the value of the field is `MPWM`"] + #[inline(always)] + pub fn is_mpwm(&self) -> bool { + **self == WAVEGEN_A::MPWM + } +} +impl core::ops::Deref for WAVEGEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAVEGEN` writer - Waveform Generation Mode"] +pub struct WAVEGEN_W<'a> { + w: &'a mut W, +} +impl<'a> WAVEGEN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WAVEGEN_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Normal frequency"] + #[inline(always)] + pub fn nfrq(self) -> &'a mut W { + self.variant(WAVEGEN_A::NFRQ) + } + #[doc = "Match frequency"] + #[inline(always)] + pub fn mfrq(self) -> &'a mut W { + self.variant(WAVEGEN_A::MFRQ) + } + #[doc = "Normal PWM"] + #[inline(always)] + pub fn npwm(self) -> &'a mut W { + self.variant(WAVEGEN_A::NPWM) + } + #[doc = "Match PWM"] + #[inline(always)] + pub fn mpwm(self) -> &'a mut W { + self.variant(WAVEGEN_A::MPWM) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u8 & 0x03); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Waveform Generation Mode"] + #[inline(always)] + pub fn wavegen(&self) -> WAVEGEN_R { + WAVEGEN_R::new((self.bits & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Waveform Generation Mode"] + #[inline(always)] + pub fn wavegen(&mut self) -> WAVEGEN_W { + WAVEGEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Waveform Generation Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wave](index.html) module"] +pub struct WAVE_SPEC; +impl crate::RegisterSpec for WAVE_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [wave::R](R) reader structure"] +impl crate::Readable for WAVE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wave::W](W) writer structure"] +impl crate::Writable for WAVE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WAVE to value 0"] +impl crate::Resettable for WAVE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/tcc0.rs b/pac/atsamc20g/src/tcc0.rs new file mode 100644 index 000000000000..6ce813a9e3d5 --- /dev/null +++ b/pac/atsamc20g/src/tcc0.rs @@ -0,0 +1,359 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - Control B Clear"] + pub ctrlbclr: crate::Reg, + #[doc = "0x05 - Control B Set"] + pub ctrlbset: crate::Reg, + _reserved3: [u8; 0x02], + #[doc = "0x08 - Synchronization Busy"] + pub syncbusy: crate::Reg, + #[doc = "0x0c - Recoverable Fault A Configuration"] + pub fctrla: crate::Reg, + #[doc = "0x10 - Recoverable Fault B Configuration"] + pub fctrlb: crate::Reg, + #[doc = "0x14 - Waveform Extension Configuration"] + pub wexctrl: crate::Reg, + #[doc = "0x18 - Driver Control"] + pub drvctrl: crate::Reg, + _reserved8: [u8; 0x02], + #[doc = "0x1e - Debug Control"] + pub dbgctrl: crate::Reg, + _reserved9: [u8; 0x01], + #[doc = "0x20 - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x24 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x28 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x2c - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x30 - Status"] + pub status: crate::Reg, + _reserved_14_count: [u8; 0x04], + #[doc = "0x38 - Pattern"] + pub patt: crate::Reg, + _reserved16: [u8; 0x02], + #[doc = "0x3c - Waveform Control"] + pub wave: crate::Reg, + _reserved_17_per: [u8; 0x04], + _reserved_18_cc: [u8; 0x10], + _reserved19: [u8; 0x10], + #[doc = "0x64 - Pattern Buffer"] + pub pattbuf: crate::Reg, + _reserved20: [u8; 0x06], + _reserved_20_perbuf: [u8; 0x04], + _reserved_21_ccbuf: [u8; 0x10], +} +impl RegisterBlock { + #[doc = "0x34 - Count"] + #[inline(always)] + pub fn count_dith6_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(52usize) + as *const crate::Reg) + } + } + #[doc = "0x34 - Count"] + #[inline(always)] + pub fn count_dith5_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(52usize) + as *const crate::Reg) + } + } + #[doc = "0x34 - Count"] + #[inline(always)] + pub fn count_dith4_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(52usize) + as *const crate::Reg) + } + } + #[doc = "0x34 - Count"] + #[inline(always)] + pub fn count(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(52usize) + as *const crate::Reg) + } + } + #[doc = "0x40 - Period"] + #[inline(always)] + pub fn per_dith6_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(64usize) + as *const crate::Reg) + } + } + #[doc = "0x40 - Period"] + #[inline(always)] + pub fn per_dith5_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(64usize) + as *const crate::Reg) + } + } + #[doc = "0x40 - Period"] + #[inline(always)] + pub fn per_dith4_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(64usize) + as *const crate::Reg) + } + } + #[doc = "0x40 - Period"] + #[inline(always)] + pub fn per(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(64usize) + as *const crate::Reg) + } + } + #[doc = "0x44..0x54 - Compare and Capture"] + #[inline(always)] + pub fn cc_dith6_mode(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(68usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x44..0x54 - Compare and Capture"] + #[inline(always)] + pub fn cc_dith5_mode(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(68usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x44..0x54 - Compare and Capture"] + #[inline(always)] + pub fn cc_dith4_mode(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(68usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x44..0x54 - Compare and Capture"] + #[inline(always)] + pub fn cc(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(68usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x6c - Period Buffer"] + #[inline(always)] + pub fn perbuf_dith6_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(108usize) + as *const crate::Reg) + } + } + #[doc = "0x6c - Period Buffer"] + #[inline(always)] + pub fn perbuf_dith5_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(108usize) + as *const crate::Reg) + } + } + #[doc = "0x6c - Period Buffer"] + #[inline(always)] + pub fn perbuf_dith4_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(108usize) + as *const crate::Reg) + } + } + #[doc = "0x6c - Period Buffer"] + #[inline(always)] + pub fn perbuf(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(108usize) + as *const crate::Reg) + } + } + #[doc = "0x70..0x80 - Compare and Capture Buffer"] + #[inline(always)] + pub fn ccbuf_dith6_mode(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(112usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x70..0x80 - Compare and Capture Buffer"] + #[inline(always)] + pub fn ccbuf_dith5_mode(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(112usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x70..0x80 - Compare and Capture Buffer"] + #[inline(always)] + pub fn ccbuf_dith4_mode(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(112usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x70..0x80 - Compare and Capture Buffer"] + #[inline(always)] + pub fn ccbuf(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(112usize) + as *const [crate::Reg; 4]) + } + } +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "CTRLBCLR register accessor: an alias for `Reg`"] +pub type CTRLBCLR = crate::Reg; +#[doc = "Control B Clear"] +pub mod ctrlbclr; +#[doc = "CTRLBSET register accessor: an alias for `Reg`"] +pub type CTRLBSET = crate::Reg; +#[doc = "Control B Set"] +pub mod ctrlbset; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Busy"] +pub mod syncbusy; +#[doc = "FCTRLA register accessor: an alias for `Reg`"] +pub type FCTRLA = crate::Reg; +#[doc = "Recoverable Fault A Configuration"] +pub mod fctrla; +#[doc = "FCTRLB register accessor: an alias for `Reg`"] +pub type FCTRLB = crate::Reg; +#[doc = "Recoverable Fault B Configuration"] +pub mod fctrlb; +#[doc = "WEXCTRL register accessor: an alias for `Reg`"] +pub type WEXCTRL = crate::Reg; +#[doc = "Waveform Extension Configuration"] +pub mod wexctrl; +#[doc = "DRVCTRL register accessor: an alias for `Reg`"] +pub type DRVCTRL = crate::Reg; +#[doc = "Driver Control"] +pub mod drvctrl; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "COUNT register accessor: an alias for `Reg`"] +pub type COUNT = crate::Reg; +#[doc = "Count"] +pub mod count; +#[doc = "COUNT_DITH4_MODE register accessor: an alias for `Reg`"] +pub type COUNT_DITH4_MODE = crate::Reg; +#[doc = "Count"] +pub mod count_dith4_mode; +#[doc = "COUNT_DITH5_MODE register accessor: an alias for `Reg`"] +pub type COUNT_DITH5_MODE = crate::Reg; +#[doc = "Count"] +pub mod count_dith5_mode; +#[doc = "COUNT_DITH6_MODE register accessor: an alias for `Reg`"] +pub type COUNT_DITH6_MODE = crate::Reg; +#[doc = "Count"] +pub mod count_dith6_mode; +#[doc = "PATT register accessor: an alias for `Reg`"] +pub type PATT = crate::Reg; +#[doc = "Pattern"] +pub mod patt; +#[doc = "WAVE register accessor: an alias for `Reg`"] +pub type WAVE = crate::Reg; +#[doc = "Waveform Control"] +pub mod wave; +#[doc = "PER register accessor: an alias for `Reg`"] +pub type PER = crate::Reg; +#[doc = "Period"] +pub mod per; +#[doc = "PER_DITH4_MODE register accessor: an alias for `Reg`"] +pub type PER_DITH4_MODE = crate::Reg; +#[doc = "Period"] +pub mod per_dith4_mode; +#[doc = "PER_DITH5_MODE register accessor: an alias for `Reg`"] +pub type PER_DITH5_MODE = crate::Reg; +#[doc = "Period"] +pub mod per_dith5_mode; +#[doc = "PER_DITH6_MODE register accessor: an alias for `Reg`"] +pub type PER_DITH6_MODE = crate::Reg; +#[doc = "Period"] +pub mod per_dith6_mode; +#[doc = "CC register accessor: an alias for `Reg`"] +pub type CC = crate::Reg; +#[doc = "Compare and Capture"] +pub mod cc; +#[doc = "CC_DITH4_MODE register accessor: an alias for `Reg`"] +pub type CC_DITH4_MODE = crate::Reg; +#[doc = "Compare and Capture"] +pub mod cc_dith4_mode; +#[doc = "CC_DITH5_MODE register accessor: an alias for `Reg`"] +pub type CC_DITH5_MODE = crate::Reg; +#[doc = "Compare and Capture"] +pub mod cc_dith5_mode; +#[doc = "CC_DITH6_MODE register accessor: an alias for `Reg`"] +pub type CC_DITH6_MODE = crate::Reg; +#[doc = "Compare and Capture"] +pub mod cc_dith6_mode; +#[doc = "PATTBUF register accessor: an alias for `Reg`"] +pub type PATTBUF = crate::Reg; +#[doc = "Pattern Buffer"] +pub mod pattbuf; +#[doc = "PERBUF register accessor: an alias for `Reg`"] +pub type PERBUF = crate::Reg; +#[doc = "Period Buffer"] +pub mod perbuf; +#[doc = "PERBUF_DITH4_MODE register accessor: an alias for `Reg`"] +pub type PERBUF_DITH4_MODE = crate::Reg; +#[doc = "Period Buffer"] +pub mod perbuf_dith4_mode; +#[doc = "PERBUF_DITH5_MODE register accessor: an alias for `Reg`"] +pub type PERBUF_DITH5_MODE = crate::Reg; +#[doc = "Period Buffer"] +pub mod perbuf_dith5_mode; +#[doc = "PERBUF_DITH6_MODE register accessor: an alias for `Reg`"] +pub type PERBUF_DITH6_MODE = crate::Reg; +#[doc = "Period Buffer"] +pub mod perbuf_dith6_mode; +#[doc = "CCBUF register accessor: an alias for `Reg`"] +pub type CCBUF = crate::Reg; +#[doc = "Compare and Capture Buffer"] +pub mod ccbuf; +#[doc = "CCBUF_DITH4_MODE register accessor: an alias for `Reg`"] +pub type CCBUF_DITH4_MODE = crate::Reg; +#[doc = "Compare and Capture Buffer"] +pub mod ccbuf_dith4_mode; +#[doc = "CCBUF_DITH5_MODE register accessor: an alias for `Reg`"] +pub type CCBUF_DITH5_MODE = crate::Reg; +#[doc = "Compare and Capture Buffer"] +pub mod ccbuf_dith5_mode; +#[doc = "CCBUF_DITH6_MODE register accessor: an alias for `Reg`"] +pub type CCBUF_DITH6_MODE = crate::Reg; +#[doc = "Compare and Capture Buffer"] +pub mod ccbuf_dith6_mode; diff --git a/pac/atsamc20g/src/tcc0/cc.rs b/pac/atsamc20g/src/tcc0/cc.rs new file mode 100644 index 000000000000..c4d6df7a9a20 --- /dev/null +++ b/pac/atsamc20g/src/tcc0/cc.rs @@ -0,0 +1,104 @@ +#[doc = "Register `CC[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CC[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CC` reader - Channel Compare/Capture Value"] +pub struct CC_R(crate::FieldReader); +impl CC_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC` writer - Channel Compare/Capture Value"] +pub struct CC_W<'a> { + w: &'a mut W, +} +impl<'a> CC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&self) -> CC_R { + CC_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&mut self) -> CC_W { + CC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc](index.html) module"] +pub struct CC_SPEC; +impl crate::RegisterSpec for CC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cc::R](R) reader structure"] +impl crate::Readable for CC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cc::W](W) writer structure"] +impl crate::Writable for CC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CC[%s] +to value 0"] +impl crate::Resettable for CC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/tcc0/cc_dith4_mode.rs b/pac/atsamc20g/src/tcc0/cc_dith4_mode.rs new file mode 100644 index 000000000000..c45d8b6bac41 --- /dev/null +++ b/pac/atsamc20g/src/tcc0/cc_dith4_mode.rs @@ -0,0 +1,141 @@ +#[doc = "Register `CC_DITH4_MODE[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CC_DITH4_MODE[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHER` reader - Dithering Cycle Number"] +pub struct DITHER_R(crate::FieldReader); +impl DITHER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHER` writer - Dithering Cycle Number"] +pub struct DITHER_W<'a> { + w: &'a mut W, +} +impl<'a> DITHER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Field `CC` reader - Channel Compare/Capture Value"] +pub struct CC_R(crate::FieldReader); +impl CC_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC` writer - Channel Compare/Capture Value"] +pub struct CC_W<'a> { + w: &'a mut W, +} +impl<'a> CC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x000f_ffff << 4)) | ((value as u32 & 0x000f_ffff) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&self) -> DITHER_R { + DITHER_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&self) -> CC_R { + CC_R::new(((self.bits >> 4) & 0x000f_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:3 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&mut self) -> DITHER_W { + DITHER_W { w: self } + } + #[doc = "Bits 4:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&mut self) -> CC_W { + CC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc_dith4_mode](index.html) module"] +pub struct CC_DITH4_MODE_SPEC; +impl crate::RegisterSpec for CC_DITH4_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cc_dith4_mode::R](R) reader structure"] +impl crate::Readable for CC_DITH4_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cc_dith4_mode::W](W) writer structure"] +impl crate::Writable for CC_DITH4_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CC_DITH4_MODE[%s] +to value 0"] +impl crate::Resettable for CC_DITH4_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/tcc0/cc_dith5_mode.rs b/pac/atsamc20g/src/tcc0/cc_dith5_mode.rs new file mode 100644 index 000000000000..0592b923051a --- /dev/null +++ b/pac/atsamc20g/src/tcc0/cc_dith5_mode.rs @@ -0,0 +1,141 @@ +#[doc = "Register `CC_DITH5_MODE[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CC_DITH5_MODE[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHER` reader - Dithering Cycle Number"] +pub struct DITHER_R(crate::FieldReader); +impl DITHER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHER` writer - Dithering Cycle Number"] +pub struct DITHER_W<'a> { + w: &'a mut W, +} +impl<'a> DITHER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f); + self.w + } +} +#[doc = "Field `CC` reader - Channel Compare/Capture Value"] +pub struct CC_R(crate::FieldReader); +impl CC_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC` writer - Channel Compare/Capture Value"] +pub struct CC_W<'a> { + w: &'a mut W, +} +impl<'a> CC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0007_ffff << 5)) | ((value as u32 & 0x0007_ffff) << 5); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&self) -> DITHER_R { + DITHER_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&self) -> CC_R { + CC_R::new(((self.bits >> 5) & 0x0007_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:4 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&mut self) -> DITHER_W { + DITHER_W { w: self } + } + #[doc = "Bits 5:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&mut self) -> CC_W { + CC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc_dith5_mode](index.html) module"] +pub struct CC_DITH5_MODE_SPEC; +impl crate::RegisterSpec for CC_DITH5_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cc_dith5_mode::R](R) reader structure"] +impl crate::Readable for CC_DITH5_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cc_dith5_mode::W](W) writer structure"] +impl crate::Writable for CC_DITH5_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CC_DITH5_MODE[%s] +to value 0"] +impl crate::Resettable for CC_DITH5_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/tcc0/cc_dith6_mode.rs b/pac/atsamc20g/src/tcc0/cc_dith6_mode.rs new file mode 100644 index 000000000000..62a82a872426 --- /dev/null +++ b/pac/atsamc20g/src/tcc0/cc_dith6_mode.rs @@ -0,0 +1,141 @@ +#[doc = "Register `CC_DITH6_MODE[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CC_DITH6_MODE[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHER` reader - Dithering Cycle Number"] +pub struct DITHER_R(crate::FieldReader); +impl DITHER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHER` writer - Dithering Cycle Number"] +pub struct DITHER_W<'a> { + w: &'a mut W, +} +impl<'a> DITHER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +#[doc = "Field `CC` reader - Channel Compare/Capture Value"] +pub struct CC_R(crate::FieldReader); +impl CC_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC` writer - Channel Compare/Capture Value"] +pub struct CC_W<'a> { + w: &'a mut W, +} +impl<'a> CC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0003_ffff << 6)) | ((value as u32 & 0x0003_ffff) << 6); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&self) -> DITHER_R { + DITHER_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&self) -> CC_R { + CC_R::new(((self.bits >> 6) & 0x0003_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:5 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&mut self) -> DITHER_W { + DITHER_W { w: self } + } + #[doc = "Bits 6:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&mut self) -> CC_W { + CC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc_dith6_mode](index.html) module"] +pub struct CC_DITH6_MODE_SPEC; +impl crate::RegisterSpec for CC_DITH6_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cc_dith6_mode::R](R) reader structure"] +impl crate::Readable for CC_DITH6_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cc_dith6_mode::W](W) writer structure"] +impl crate::Writable for CC_DITH6_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CC_DITH6_MODE[%s] +to value 0"] +impl crate::Resettable for CC_DITH6_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/tcc0/ccbuf.rs b/pac/atsamc20g/src/tcc0/ccbuf.rs new file mode 100644 index 000000000000..a4db1135f095 --- /dev/null +++ b/pac/atsamc20g/src/tcc0/ccbuf.rs @@ -0,0 +1,104 @@ +#[doc = "Register `CCBUF[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CCBUF[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CCBUF` reader - Channel Compare/Capture Buffer Value"] +pub struct CCBUF_R(crate::FieldReader); +impl CCBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CCBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUF` writer - Channel Compare/Capture Buffer Value"] +pub struct CCBUF_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccbuf(&self) -> CCBUF_R { + CCBUF_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccbuf(&mut self) -> CCBUF_W { + CCBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccbuf](index.html) module"] +pub struct CCBUF_SPEC; +impl crate::RegisterSpec for CCBUF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ccbuf::R](R) reader structure"] +impl crate::Readable for CCBUF_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ccbuf::W](W) writer structure"] +impl crate::Writable for CCBUF_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CCBUF[%s] +to value 0"] +impl crate::Resettable for CCBUF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/tcc0/ccbuf_dith4_mode.rs b/pac/atsamc20g/src/tcc0/ccbuf_dith4_mode.rs new file mode 100644 index 000000000000..dfa16e936175 --- /dev/null +++ b/pac/atsamc20g/src/tcc0/ccbuf_dith4_mode.rs @@ -0,0 +1,141 @@ +#[doc = "Register `CCBUF_DITH4_MODE[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CCBUF_DITH4_MODE[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CCBUF` reader - Channel Compare/Capture Buffer Value"] +pub struct CCBUF_R(crate::FieldReader); +impl CCBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CCBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUF` writer - Channel Compare/Capture Buffer Value"] +pub struct CCBUF_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Field `DITHERBUF` reader - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_R(crate::FieldReader); +impl DITHERBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + DITHERBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHERBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHERBUF` writer - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_W<'a> { + w: &'a mut W, +} +impl<'a> DITHERBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x000f_ffff << 4)) | ((value as u32 & 0x000f_ffff) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccbuf(&self) -> CCBUF_R { + CCBUF_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:23 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&self) -> DITHERBUF_R { + DITHERBUF_R::new(((self.bits >> 4) & 0x000f_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:3 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccbuf(&mut self) -> CCBUF_W { + CCBUF_W { w: self } + } + #[doc = "Bits 4:23 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&mut self) -> DITHERBUF_W { + DITHERBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccbuf_dith4_mode](index.html) module"] +pub struct CCBUF_DITH4_MODE_SPEC; +impl crate::RegisterSpec for CCBUF_DITH4_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ccbuf_dith4_mode::R](R) reader structure"] +impl crate::Readable for CCBUF_DITH4_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ccbuf_dith4_mode::W](W) writer structure"] +impl crate::Writable for CCBUF_DITH4_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CCBUF_DITH4_MODE[%s] +to value 0"] +impl crate::Resettable for CCBUF_DITH4_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/tcc0/ccbuf_dith5_mode.rs b/pac/atsamc20g/src/tcc0/ccbuf_dith5_mode.rs new file mode 100644 index 000000000000..0c78ba3303c0 --- /dev/null +++ b/pac/atsamc20g/src/tcc0/ccbuf_dith5_mode.rs @@ -0,0 +1,141 @@ +#[doc = "Register `CCBUF_DITH5_MODE[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CCBUF_DITH5_MODE[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHERBUF` reader - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_R(crate::FieldReader); +impl DITHERBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHERBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHERBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHERBUF` writer - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_W<'a> { + w: &'a mut W, +} +impl<'a> DITHERBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f); + self.w + } +} +#[doc = "Field `CCBUF` reader - Channel Compare/Capture Buffer Value"] +pub struct CCBUF_R(crate::FieldReader); +impl CCBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CCBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUF` writer - Channel Compare/Capture Buffer Value"] +pub struct CCBUF_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0007_ffff << 5)) | ((value as u32 & 0x0007_ffff) << 5); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&self) -> DITHERBUF_R { + DITHERBUF_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:23 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccbuf(&self) -> CCBUF_R { + CCBUF_R::new(((self.bits >> 5) & 0x0007_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:4 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&mut self) -> DITHERBUF_W { + DITHERBUF_W { w: self } + } + #[doc = "Bits 5:23 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccbuf(&mut self) -> CCBUF_W { + CCBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccbuf_dith5_mode](index.html) module"] +pub struct CCBUF_DITH5_MODE_SPEC; +impl crate::RegisterSpec for CCBUF_DITH5_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ccbuf_dith5_mode::R](R) reader structure"] +impl crate::Readable for CCBUF_DITH5_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ccbuf_dith5_mode::W](W) writer structure"] +impl crate::Writable for CCBUF_DITH5_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CCBUF_DITH5_MODE[%s] +to value 0"] +impl crate::Resettable for CCBUF_DITH5_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/tcc0/ccbuf_dith6_mode.rs b/pac/atsamc20g/src/tcc0/ccbuf_dith6_mode.rs new file mode 100644 index 000000000000..8d19b8a9e595 --- /dev/null +++ b/pac/atsamc20g/src/tcc0/ccbuf_dith6_mode.rs @@ -0,0 +1,141 @@ +#[doc = "Register `CCBUF_DITH6_MODE[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CCBUF_DITH6_MODE[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHERBUF` reader - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_R(crate::FieldReader); +impl DITHERBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHERBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHERBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHERBUF` writer - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_W<'a> { + w: &'a mut W, +} +impl<'a> DITHERBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +#[doc = "Field `CCBUF` reader - Channel Compare/Capture Buffer Value"] +pub struct CCBUF_R(crate::FieldReader); +impl CCBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CCBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUF` writer - Channel Compare/Capture Buffer Value"] +pub struct CCBUF_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0003_ffff << 6)) | ((value as u32 & 0x0003_ffff) << 6); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&self) -> DITHERBUF_R { + DITHERBUF_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:23 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccbuf(&self) -> CCBUF_R { + CCBUF_R::new(((self.bits >> 6) & 0x0003_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:5 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&mut self) -> DITHERBUF_W { + DITHERBUF_W { w: self } + } + #[doc = "Bits 6:23 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccbuf(&mut self) -> CCBUF_W { + CCBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccbuf_dith6_mode](index.html) module"] +pub struct CCBUF_DITH6_MODE_SPEC; +impl crate::RegisterSpec for CCBUF_DITH6_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ccbuf_dith6_mode::R](R) reader structure"] +impl crate::Readable for CCBUF_DITH6_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ccbuf_dith6_mode::W](W) writer structure"] +impl crate::Writable for CCBUF_DITH6_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CCBUF_DITH6_MODE[%s] +to value 0"] +impl crate::Resettable for CCBUF_DITH6_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/tcc0/count.rs b/pac/atsamc20g/src/tcc0/count.rs new file mode 100644 index 000000000000..7628f2c0d5e1 --- /dev/null +++ b/pac/atsamc20g/src/tcc0/count.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Count\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count](index.html) module"] +pub struct COUNT_SPEC; +impl crate::RegisterSpec for COUNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [count::R](R) reader structure"] +impl crate::Readable for COUNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count::W](W) writer structure"] +impl crate::Writable for COUNT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT to value 0"] +impl crate::Resettable for COUNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/tcc0/count_dith4_mode.rs b/pac/atsamc20g/src/tcc0/count_dith4_mode.rs new file mode 100644 index 000000000000..fc058ae5efd5 --- /dev/null +++ b/pac/atsamc20g/src/tcc0/count_dith4_mode.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT_DITH4_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT_DITH4_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x000f_ffff << 4)) | ((value as u32 & 0x000f_ffff) << 4); + self.w + } +} +impl R { + #[doc = "Bits 4:23 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 4) & 0x000f_ffff) as u32) + } +} +impl W { + #[doc = "Bits 4:23 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Count\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count_dith4_mode](index.html) module"] +pub struct COUNT_DITH4_MODE_SPEC; +impl crate::RegisterSpec for COUNT_DITH4_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [count_dith4_mode::R](R) reader structure"] +impl crate::Readable for COUNT_DITH4_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count_dith4_mode::W](W) writer structure"] +impl crate::Writable for COUNT_DITH4_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT_DITH4_MODE to value 0"] +impl crate::Resettable for COUNT_DITH4_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/tcc0/count_dith5_mode.rs b/pac/atsamc20g/src/tcc0/count_dith5_mode.rs new file mode 100644 index 000000000000..e66e20310726 --- /dev/null +++ b/pac/atsamc20g/src/tcc0/count_dith5_mode.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT_DITH5_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT_DITH5_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0007_ffff << 5)) | ((value as u32 & 0x0007_ffff) << 5); + self.w + } +} +impl R { + #[doc = "Bits 5:23 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 5) & 0x0007_ffff) as u32) + } +} +impl W { + #[doc = "Bits 5:23 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Count\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count_dith5_mode](index.html) module"] +pub struct COUNT_DITH5_MODE_SPEC; +impl crate::RegisterSpec for COUNT_DITH5_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [count_dith5_mode::R](R) reader structure"] +impl crate::Readable for COUNT_DITH5_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count_dith5_mode::W](W) writer structure"] +impl crate::Writable for COUNT_DITH5_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT_DITH5_MODE to value 0"] +impl crate::Resettable for COUNT_DITH5_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/tcc0/count_dith6_mode.rs b/pac/atsamc20g/src/tcc0/count_dith6_mode.rs new file mode 100644 index 000000000000..5410fc6c9459 --- /dev/null +++ b/pac/atsamc20g/src/tcc0/count_dith6_mode.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT_DITH6_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT_DITH6_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0003_ffff << 6)) | ((value as u32 & 0x0003_ffff) << 6); + self.w + } +} +impl R { + #[doc = "Bits 6:23 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 6) & 0x0003_ffff) as u32) + } +} +impl W { + #[doc = "Bits 6:23 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Count\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count_dith6_mode](index.html) module"] +pub struct COUNT_DITH6_MODE_SPEC; +impl crate::RegisterSpec for COUNT_DITH6_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [count_dith6_mode::R](R) reader structure"] +impl crate::Readable for COUNT_DITH6_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count_dith6_mode::W](W) writer structure"] +impl crate::Writable for COUNT_DITH6_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT_DITH6_MODE to value 0"] +impl crate::Resettable for COUNT_DITH6_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/tcc0/ctrla.rs b/pac/atsamc20g/src/tcc0/ctrla.rs new file mode 100644 index 000000000000..b717d1ac6ae0 --- /dev/null +++ b/pac/atsamc20g/src/tcc0/ctrla.rs @@ -0,0 +1,911 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Enhanced Resolution\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum RESOLUTION_A { + #[doc = "0: Dithering is disabled"] + NONE = 0, + #[doc = "1: Dithering is done every 16 PWM frames"] + DITH4 = 1, + #[doc = "2: Dithering is done every 32 PWM frames"] + DITH5 = 2, + #[doc = "3: Dithering is done every 64 PWM frames"] + DITH6 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RESOLUTION_A) -> Self { + variant as _ + } +} +#[doc = "Field `RESOLUTION` reader - Enhanced Resolution"] +pub struct RESOLUTION_R(crate::FieldReader); +impl RESOLUTION_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RESOLUTION_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RESOLUTION_A { + match self.bits { + 0 => RESOLUTION_A::NONE, + 1 => RESOLUTION_A::DITH4, + 2 => RESOLUTION_A::DITH5, + 3 => RESOLUTION_A::DITH6, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == RESOLUTION_A::NONE + } + #[doc = "Checks if the value of the field is `DITH4`"] + #[inline(always)] + pub fn is_dith4(&self) -> bool { + **self == RESOLUTION_A::DITH4 + } + #[doc = "Checks if the value of the field is `DITH5`"] + #[inline(always)] + pub fn is_dith5(&self) -> bool { + **self == RESOLUTION_A::DITH5 + } + #[doc = "Checks if the value of the field is `DITH6`"] + #[inline(always)] + pub fn is_dith6(&self) -> bool { + **self == RESOLUTION_A::DITH6 + } +} +impl core::ops::Deref for RESOLUTION_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESOLUTION` writer - Enhanced Resolution"] +pub struct RESOLUTION_W<'a> { + w: &'a mut W, +} +impl<'a> RESOLUTION_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RESOLUTION_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Dithering is disabled"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(RESOLUTION_A::NONE) + } + #[doc = "Dithering is done every 16 PWM frames"] + #[inline(always)] + pub fn dith4(self) -> &'a mut W { + self.variant(RESOLUTION_A::DITH4) + } + #[doc = "Dithering is done every 32 PWM frames"] + #[inline(always)] + pub fn dith5(self) -> &'a mut W { + self.variant(RESOLUTION_A::DITH5) + } + #[doc = "Dithering is done every 64 PWM frames"] + #[inline(always)] + pub fn dith6(self) -> &'a mut W { + self.variant(RESOLUTION_A::DITH6) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 5)) | ((value as u32 & 0x03) << 5); + self.w + } +} +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: No division"] + DIV1 = 0, + #[doc = "1: Divide by 2"] + DIV2 = 1, + #[doc = "2: Divide by 4"] + DIV4 = 2, + #[doc = "3: Divide by 8"] + DIV8 = 3, + #[doc = "4: Divide by 16"] + DIV16 = 4, + #[doc = "5: Divide by 64"] + DIV64 = 5, + #[doc = "6: Divide by 256"] + DIV256 = 6, + #[doc = "7: Divide by 1024"] + DIV1024 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PRESCALER_A { + match self.bits { + 0 => PRESCALER_A::DIV1, + 1 => PRESCALER_A::DIV2, + 2 => PRESCALER_A::DIV4, + 3 => PRESCALER_A::DIV8, + 4 => PRESCALER_A::DIV16, + 5 => PRESCALER_A::DIV64, + 6 => PRESCALER_A::DIV256, + 7 => PRESCALER_A::DIV1024, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == PRESCALER_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PRESCALER_A::DIV1024 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "No division"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1) + } + #[doc = "Divide by 2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "Divide by 4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "Divide by 8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "Divide by 16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "Divide by 64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "Divide by 256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = "Divide by 1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Prescaler and Counter Synchronization Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCSYNC_A { + #[doc = "0: Reload or reset counter on next GCLK"] + GCLK = 0, + #[doc = "1: Reload or reset counter on next prescaler clock"] + PRESC = 1, + #[doc = "2: Reload or reset counter on next GCLK and reset prescaler counter"] + RESYNC = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCSYNC_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCSYNC` reader - Prescaler and Counter Synchronization Selection"] +pub struct PRESCSYNC_R(crate::FieldReader); +impl PRESCSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCSYNC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCSYNC_A::GCLK), + 1 => Some(PRESCSYNC_A::PRESC), + 2 => Some(PRESCSYNC_A::RESYNC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `GCLK`"] + #[inline(always)] + pub fn is_gclk(&self) -> bool { + **self == PRESCSYNC_A::GCLK + } + #[doc = "Checks if the value of the field is `PRESC`"] + #[inline(always)] + pub fn is_presc(&self) -> bool { + **self == PRESCSYNC_A::PRESC + } + #[doc = "Checks if the value of the field is `RESYNC`"] + #[inline(always)] + pub fn is_resync(&self) -> bool { + **self == PRESCSYNC_A::RESYNC + } +} +impl core::ops::Deref for PRESCSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCSYNC` writer - Prescaler and Counter Synchronization Selection"] +pub struct PRESCSYNC_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCSYNC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCSYNC_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Reload or reset counter on next GCLK"] + #[inline(always)] + pub fn gclk(self) -> &'a mut W { + self.variant(PRESCSYNC_A::GCLK) + } + #[doc = "Reload or reset counter on next prescaler clock"] + #[inline(always)] + pub fn presc(self) -> &'a mut W { + self.variant(PRESCSYNC_A::PRESC) + } + #[doc = "Reload or reset counter on next GCLK and reset prescaler counter"] + #[inline(always)] + pub fn resync(self) -> &'a mut W { + self.variant(PRESCSYNC_A::RESYNC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 12)) | ((value as u32 & 0x03) << 12); + self.w + } +} +#[doc = "Field `ALOCK` reader - Auto Lock"] +pub struct ALOCK_R(crate::FieldReader); +impl ALOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALOCK` writer - Auto Lock"] +pub struct ALOCK_W<'a> { + w: &'a mut W, +} +impl<'a> ALOCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `MSYNC` reader - Master Synchronization (only for TCC Slave Instance)"] +pub struct MSYNC_R(crate::FieldReader); +impl MSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MSYNC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MSYNC` writer - Master Synchronization (only for TCC Slave Instance)"] +pub struct MSYNC_W<'a> { + w: &'a mut W, +} +impl<'a> MSYNC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `DMAOS` reader - DMA One-shot Trigger Mode"] +pub struct DMAOS_R(crate::FieldReader); +impl DMAOS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DMAOS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DMAOS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DMAOS` writer - DMA One-shot Trigger Mode"] +pub struct DMAOS_W<'a> { + w: &'a mut W, +} +impl<'a> DMAOS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `CPTEN0` reader - Capture Channel 0 Enable"] +pub struct CPTEN0_R(crate::FieldReader); +impl CPTEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPTEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CPTEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPTEN0` writer - Capture Channel 0 Enable"] +pub struct CPTEN0_W<'a> { + w: &'a mut W, +} +impl<'a> CPTEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `CPTEN1` reader - Capture Channel 1 Enable"] +pub struct CPTEN1_R(crate::FieldReader); +impl CPTEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPTEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CPTEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPTEN1` writer - Capture Channel 1 Enable"] +pub struct CPTEN1_W<'a> { + w: &'a mut W, +} +impl<'a> CPTEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `CPTEN2` reader - Capture Channel 2 Enable"] +pub struct CPTEN2_R(crate::FieldReader); +impl CPTEN2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPTEN2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CPTEN2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPTEN2` writer - Capture Channel 2 Enable"] +pub struct CPTEN2_W<'a> { + w: &'a mut W, +} +impl<'a> CPTEN2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `CPTEN3` reader - Capture Channel 3 Enable"] +pub struct CPTEN3_R(crate::FieldReader); +impl CPTEN3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPTEN3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CPTEN3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPTEN3` writer - Capture Channel 3 Enable"] +pub struct CPTEN3_W<'a> { + w: &'a mut W, +} +impl<'a> CPTEN3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 5:6 - Enhanced Resolution"] + #[inline(always)] + pub fn resolution(&self) -> RESOLUTION_R { + RESOLUTION_R::new(((self.bits >> 5) & 0x03) as u8) + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 11 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bits 12:13 - Prescaler and Counter Synchronization Selection"] + #[inline(always)] + pub fn prescsync(&self) -> PRESCSYNC_R { + PRESCSYNC_R::new(((self.bits >> 12) & 0x03) as u8) + } + #[doc = "Bit 14 - Auto Lock"] + #[inline(always)] + pub fn alock(&self) -> ALOCK_R { + ALOCK_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Master Synchronization (only for TCC Slave Instance)"] + #[inline(always)] + pub fn msync(&self) -> MSYNC_R { + MSYNC_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 23 - DMA One-shot Trigger Mode"] + #[inline(always)] + pub fn dmaos(&self) -> DMAOS_R { + DMAOS_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn cpten0(&self) -> CPTEN0_R { + CPTEN0_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn cpten1(&self) -> CPTEN1_R { + CPTEN1_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Capture Channel 2 Enable"] + #[inline(always)] + pub fn cpten2(&self) -> CPTEN2_R { + CPTEN2_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Capture Channel 3 Enable"] + #[inline(always)] + pub fn cpten3(&self) -> CPTEN3_R { + CPTEN3_R::new(((self.bits >> 27) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 5:6 - Enhanced Resolution"] + #[inline(always)] + pub fn resolution(&mut self) -> RESOLUTION_W { + RESOLUTION_W { w: self } + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Bit 11 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bits 12:13 - Prescaler and Counter Synchronization Selection"] + #[inline(always)] + pub fn prescsync(&mut self) -> PRESCSYNC_W { + PRESCSYNC_W { w: self } + } + #[doc = "Bit 14 - Auto Lock"] + #[inline(always)] + pub fn alock(&mut self) -> ALOCK_W { + ALOCK_W { w: self } + } + #[doc = "Bit 15 - Master Synchronization (only for TCC Slave Instance)"] + #[inline(always)] + pub fn msync(&mut self) -> MSYNC_W { + MSYNC_W { w: self } + } + #[doc = "Bit 23 - DMA One-shot Trigger Mode"] + #[inline(always)] + pub fn dmaos(&mut self) -> DMAOS_W { + DMAOS_W { w: self } + } + #[doc = "Bit 24 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn cpten0(&mut self) -> CPTEN0_W { + CPTEN0_W { w: self } + } + #[doc = "Bit 25 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn cpten1(&mut self) -> CPTEN1_W { + CPTEN1_W { w: self } + } + #[doc = "Bit 26 - Capture Channel 2 Enable"] + #[inline(always)] + pub fn cpten2(&mut self) -> CPTEN2_W { + CPTEN2_W { w: self } + } + #[doc = "Bit 27 - Capture Channel 3 Enable"] + #[inline(always)] + pub fn cpten3(&mut self) -> CPTEN3_W { + CPTEN3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/tcc0/ctrlbclr.rs b/pac/atsamc20g/src/tcc0/ctrlbclr.rs new file mode 100644 index 000000000000..f96ce81ffde3 --- /dev/null +++ b/pac/atsamc20g/src/tcc0/ctrlbclr.rs @@ -0,0 +1,457 @@ +#[doc = "Register `CTRLBCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Counter Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `LUPD` reader - Lock Update"] +pub struct LUPD_R(crate::FieldReader); +impl LUPD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LUPD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LUPD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LUPD` writer - Lock Update"] +pub struct LUPD_W<'a> { + w: &'a mut W, +} +impl<'a> LUPD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ONESHOT` reader - One-Shot"] +pub struct ONESHOT_R(crate::FieldReader); +impl ONESHOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONESHOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONESHOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONESHOT` writer - One-Shot"] +pub struct ONESHOT_W<'a> { + w: &'a mut W, +} +impl<'a> ONESHOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Ramp Index Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum IDXCMD_A { + #[doc = "0: Command disabled: Index toggles between cycles A and B"] + DISABLE = 0, + #[doc = "1: Set index: cycle B will be forced in the next cycle"] + SET = 1, + #[doc = "2: Clear index: cycle A will be forced in the next cycle"] + CLEAR = 2, + #[doc = "3: Hold index: the next cycle will be the same as the current cycle"] + HOLD = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: IDXCMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `IDXCMD` reader - Ramp Index Command"] +pub struct IDXCMD_R(crate::FieldReader); +impl IDXCMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + IDXCMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> IDXCMD_A { + match self.bits { + 0 => IDXCMD_A::DISABLE, + 1 => IDXCMD_A::SET, + 2 => IDXCMD_A::CLEAR, + 3 => IDXCMD_A::HOLD, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == IDXCMD_A::DISABLE + } + #[doc = "Checks if the value of the field is `SET`"] + #[inline(always)] + pub fn is_set(&self) -> bool { + **self == IDXCMD_A::SET + } + #[doc = "Checks if the value of the field is `CLEAR`"] + #[inline(always)] + pub fn is_clear(&self) -> bool { + **self == IDXCMD_A::CLEAR + } + #[doc = "Checks if the value of the field is `HOLD`"] + #[inline(always)] + pub fn is_hold(&self) -> bool { + **self == IDXCMD_A::HOLD + } +} +impl core::ops::Deref for IDXCMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IDXCMD` writer - Ramp Index Command"] +pub struct IDXCMD_W<'a> { + w: &'a mut W, +} +impl<'a> IDXCMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: IDXCMD_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Command disabled: Index toggles between cycles A and B"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(IDXCMD_A::DISABLE) + } + #[doc = "Set index: cycle B will be forced in the next cycle"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(IDXCMD_A::SET) + } + #[doc = "Clear index: cycle A will be forced in the next cycle"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(IDXCMD_A::CLEAR) + } + #[doc = "Hold index: the next cycle will be the same as the current cycle"] + #[inline(always)] + pub fn hold(self) -> &'a mut W { + self.variant(IDXCMD_A::HOLD) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 3)) | ((value as u8 & 0x03) << 3); + self.w + } +} +#[doc = "TCC Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Clear start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force stop"] + STOP = 2, + #[doc = "3: Force update or double buffered registers"] + UPDATE = 3, + #[doc = "4: Force COUNT read synchronization"] + READSYNC = 4, + #[doc = "5: One-shot DMA trigger"] + DMAOS = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - TCC Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NONE), + 1 => Some(CMD_A::RETRIGGER), + 2 => Some(CMD_A::STOP), + 3 => Some(CMD_A::UPDATE), + 4 => Some(CMD_A::READSYNC), + 5 => Some(CMD_A::DMAOS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == CMD_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == CMD_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == CMD_A::STOP + } + #[doc = "Checks if the value of the field is `UPDATE`"] + #[inline(always)] + pub fn is_update(&self) -> bool { + **self == CMD_A::UPDATE + } + #[doc = "Checks if the value of the field is `READSYNC`"] + #[inline(always)] + pub fn is_readsync(&self) -> bool { + **self == CMD_A::READSYNC + } + #[doc = "Checks if the value of the field is `DMAOS`"] + #[inline(always)] + pub fn is_dmaos(&self) -> bool { + **self == CMD_A::DMAOS + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - TCC Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMD_A::NONE) + } + #[doc = "Clear start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMD_A::RETRIGGER) + } + #[doc = "Force stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMD_A::STOP) + } + #[doc = "Force update or double buffered registers"] + #[inline(always)] + pub fn update(self) -> &'a mut W { + self.variant(CMD_A::UPDATE) + } + #[doc = "Force COUNT read synchronization"] + #[inline(always)] + pub fn readsync(self) -> &'a mut W { + self.variant(CMD_A::READSYNC) + } + #[doc = "One-shot DMA trigger"] + #[inline(always)] + pub fn dmaos(self) -> &'a mut W { + self.variant(CMD_A::DMAOS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 5)) | ((value as u8 & 0x07) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&self) -> LUPD_R { + LUPD_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - One-Shot"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 3:4 - Ramp Index Command"] + #[inline(always)] + pub fn idxcmd(&self) -> IDXCMD_R { + IDXCMD_R::new(((self.bits >> 3) & 0x03) as u8) + } + #[doc = "Bits 5:7 - TCC Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 5) & 0x07) as u8) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&mut self) -> LUPD_W { + LUPD_W { w: self } + } + #[doc = "Bit 2 - One-Shot"] + #[inline(always)] + pub fn oneshot(&mut self) -> ONESHOT_W { + ONESHOT_W { w: self } + } + #[doc = "Bits 3:4 - Ramp Index Command"] + #[inline(always)] + pub fn idxcmd(&mut self) -> IDXCMD_W { + IDXCMD_W { w: self } + } + #[doc = "Bits 5:7 - TCC Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbclr](index.html) module"] +pub struct CTRLBCLR_SPEC; +impl crate::RegisterSpec for CTRLBCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbclr::R](R) reader structure"] +impl crate::Readable for CTRLBCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbclr::W](W) writer structure"] +impl crate::Writable for CTRLBCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLBCLR to value 0"] +impl crate::Resettable for CTRLBCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/tcc0/ctrlbset.rs b/pac/atsamc20g/src/tcc0/ctrlbset.rs new file mode 100644 index 000000000000..7002dd71efe7 --- /dev/null +++ b/pac/atsamc20g/src/tcc0/ctrlbset.rs @@ -0,0 +1,457 @@ +#[doc = "Register `CTRLBSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Counter Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `LUPD` reader - Lock Update"] +pub struct LUPD_R(crate::FieldReader); +impl LUPD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LUPD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LUPD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LUPD` writer - Lock Update"] +pub struct LUPD_W<'a> { + w: &'a mut W, +} +impl<'a> LUPD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ONESHOT` reader - One-Shot"] +pub struct ONESHOT_R(crate::FieldReader); +impl ONESHOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONESHOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONESHOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONESHOT` writer - One-Shot"] +pub struct ONESHOT_W<'a> { + w: &'a mut W, +} +impl<'a> ONESHOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Ramp Index Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum IDXCMD_A { + #[doc = "0: Command disabled: Index toggles between cycles A and B"] + DISABLE = 0, + #[doc = "1: Set index: cycle B will be forced in the next cycle"] + SET = 1, + #[doc = "2: Clear index: cycle A will be forced in the next cycle"] + CLEAR = 2, + #[doc = "3: Hold index: the next cycle will be the same as the current cycle"] + HOLD = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: IDXCMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `IDXCMD` reader - Ramp Index Command"] +pub struct IDXCMD_R(crate::FieldReader); +impl IDXCMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + IDXCMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> IDXCMD_A { + match self.bits { + 0 => IDXCMD_A::DISABLE, + 1 => IDXCMD_A::SET, + 2 => IDXCMD_A::CLEAR, + 3 => IDXCMD_A::HOLD, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == IDXCMD_A::DISABLE + } + #[doc = "Checks if the value of the field is `SET`"] + #[inline(always)] + pub fn is_set(&self) -> bool { + **self == IDXCMD_A::SET + } + #[doc = "Checks if the value of the field is `CLEAR`"] + #[inline(always)] + pub fn is_clear(&self) -> bool { + **self == IDXCMD_A::CLEAR + } + #[doc = "Checks if the value of the field is `HOLD`"] + #[inline(always)] + pub fn is_hold(&self) -> bool { + **self == IDXCMD_A::HOLD + } +} +impl core::ops::Deref for IDXCMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IDXCMD` writer - Ramp Index Command"] +pub struct IDXCMD_W<'a> { + w: &'a mut W, +} +impl<'a> IDXCMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: IDXCMD_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Command disabled: Index toggles between cycles A and B"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(IDXCMD_A::DISABLE) + } + #[doc = "Set index: cycle B will be forced in the next cycle"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(IDXCMD_A::SET) + } + #[doc = "Clear index: cycle A will be forced in the next cycle"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(IDXCMD_A::CLEAR) + } + #[doc = "Hold index: the next cycle will be the same as the current cycle"] + #[inline(always)] + pub fn hold(self) -> &'a mut W { + self.variant(IDXCMD_A::HOLD) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 3)) | ((value as u8 & 0x03) << 3); + self.w + } +} +#[doc = "TCC Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Clear start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force stop"] + STOP = 2, + #[doc = "3: Force update or double buffered registers"] + UPDATE = 3, + #[doc = "4: Force COUNT read synchronization"] + READSYNC = 4, + #[doc = "5: One-shot DMA trigger"] + DMAOS = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - TCC Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NONE), + 1 => Some(CMD_A::RETRIGGER), + 2 => Some(CMD_A::STOP), + 3 => Some(CMD_A::UPDATE), + 4 => Some(CMD_A::READSYNC), + 5 => Some(CMD_A::DMAOS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == CMD_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == CMD_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == CMD_A::STOP + } + #[doc = "Checks if the value of the field is `UPDATE`"] + #[inline(always)] + pub fn is_update(&self) -> bool { + **self == CMD_A::UPDATE + } + #[doc = "Checks if the value of the field is `READSYNC`"] + #[inline(always)] + pub fn is_readsync(&self) -> bool { + **self == CMD_A::READSYNC + } + #[doc = "Checks if the value of the field is `DMAOS`"] + #[inline(always)] + pub fn is_dmaos(&self) -> bool { + **self == CMD_A::DMAOS + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - TCC Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMD_A::NONE) + } + #[doc = "Clear start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMD_A::RETRIGGER) + } + #[doc = "Force stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMD_A::STOP) + } + #[doc = "Force update or double buffered registers"] + #[inline(always)] + pub fn update(self) -> &'a mut W { + self.variant(CMD_A::UPDATE) + } + #[doc = "Force COUNT read synchronization"] + #[inline(always)] + pub fn readsync(self) -> &'a mut W { + self.variant(CMD_A::READSYNC) + } + #[doc = "One-shot DMA trigger"] + #[inline(always)] + pub fn dmaos(self) -> &'a mut W { + self.variant(CMD_A::DMAOS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 5)) | ((value as u8 & 0x07) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&self) -> LUPD_R { + LUPD_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - One-Shot"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 3:4 - Ramp Index Command"] + #[inline(always)] + pub fn idxcmd(&self) -> IDXCMD_R { + IDXCMD_R::new(((self.bits >> 3) & 0x03) as u8) + } + #[doc = "Bits 5:7 - TCC Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 5) & 0x07) as u8) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&mut self) -> LUPD_W { + LUPD_W { w: self } + } + #[doc = "Bit 2 - One-Shot"] + #[inline(always)] + pub fn oneshot(&mut self) -> ONESHOT_W { + ONESHOT_W { w: self } + } + #[doc = "Bits 3:4 - Ramp Index Command"] + #[inline(always)] + pub fn idxcmd(&mut self) -> IDXCMD_W { + IDXCMD_W { w: self } + } + #[doc = "Bits 5:7 - TCC Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbset](index.html) module"] +pub struct CTRLBSET_SPEC; +impl crate::RegisterSpec for CTRLBSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbset::R](R) reader structure"] +impl crate::Readable for CTRLBSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbset::W](W) writer structure"] +impl crate::Writable for CTRLBSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLBSET to value 0"] +impl crate::Resettable for CTRLBSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/tcc0/dbgctrl.rs b/pac/atsamc20g/src/tcc0/dbgctrl.rs new file mode 100644 index 000000000000..313ebe3f5c18 --- /dev/null +++ b/pac/atsamc20g/src/tcc0/dbgctrl.rs @@ -0,0 +1,160 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Debug Running Mode"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Debug Running Mode"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `FDDBD` reader - Fault Detection on Debug Break Detection"] +pub struct FDDBD_R(crate::FieldReader); +impl FDDBD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FDDBD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FDDBD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FDDBD` writer - Fault Detection on Debug Break Detection"] +pub struct FDDBD_W<'a> { + w: &'a mut W, +} +impl<'a> FDDBD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Running Mode"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 2 - Fault Detection on Debug Break Detection"] + #[inline(always)] + pub fn fddbd(&self) -> FDDBD_R { + FDDBD_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Running Mode"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Bit 2 - Fault Detection on Debug Break Detection"] + #[inline(always)] + pub fn fddbd(&mut self) -> FDDBD_W { + FDDBD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/tcc0/drvctrl.rs b/pac/atsamc20g/src/tcc0/drvctrl.rs new file mode 100644 index 000000000000..316041e1e3be --- /dev/null +++ b/pac/atsamc20g/src/tcc0/drvctrl.rs @@ -0,0 +1,1268 @@ +#[doc = "Register `DRVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DRVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `NRE0` reader - Non-Recoverable State 0 Output Enable"] +pub struct NRE0_R(crate::FieldReader); +impl NRE0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRE0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRE0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRE0` writer - Non-Recoverable State 0 Output Enable"] +pub struct NRE0_W<'a> { + w: &'a mut W, +} +impl<'a> NRE0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `NRE1` reader - Non-Recoverable State 1 Output Enable"] +pub struct NRE1_R(crate::FieldReader); +impl NRE1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRE1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRE1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRE1` writer - Non-Recoverable State 1 Output Enable"] +pub struct NRE1_W<'a> { + w: &'a mut W, +} +impl<'a> NRE1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `NRE2` reader - Non-Recoverable State 2 Output Enable"] +pub struct NRE2_R(crate::FieldReader); +impl NRE2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRE2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRE2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRE2` writer - Non-Recoverable State 2 Output Enable"] +pub struct NRE2_W<'a> { + w: &'a mut W, +} +impl<'a> NRE2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `NRE3` reader - Non-Recoverable State 3 Output Enable"] +pub struct NRE3_R(crate::FieldReader); +impl NRE3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRE3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRE3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRE3` writer - Non-Recoverable State 3 Output Enable"] +pub struct NRE3_W<'a> { + w: &'a mut W, +} +impl<'a> NRE3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `NRE4` reader - Non-Recoverable State 4 Output Enable"] +pub struct NRE4_R(crate::FieldReader); +impl NRE4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRE4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRE4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRE4` writer - Non-Recoverable State 4 Output Enable"] +pub struct NRE4_W<'a> { + w: &'a mut W, +} +impl<'a> NRE4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `NRE5` reader - Non-Recoverable State 5 Output Enable"] +pub struct NRE5_R(crate::FieldReader); +impl NRE5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRE5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRE5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRE5` writer - Non-Recoverable State 5 Output Enable"] +pub struct NRE5_W<'a> { + w: &'a mut W, +} +impl<'a> NRE5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `NRE6` reader - Non-Recoverable State 6 Output Enable"] +pub struct NRE6_R(crate::FieldReader); +impl NRE6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRE6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRE6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRE6` writer - Non-Recoverable State 6 Output Enable"] +pub struct NRE6_W<'a> { + w: &'a mut W, +} +impl<'a> NRE6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `NRE7` reader - Non-Recoverable State 7 Output Enable"] +pub struct NRE7_R(crate::FieldReader); +impl NRE7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRE7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRE7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRE7` writer - Non-Recoverable State 7 Output Enable"] +pub struct NRE7_W<'a> { + w: &'a mut W, +} +impl<'a> NRE7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `NRV0` reader - Non-Recoverable State 0 Output Value"] +pub struct NRV0_R(crate::FieldReader); +impl NRV0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRV0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRV0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRV0` writer - Non-Recoverable State 0 Output Value"] +pub struct NRV0_W<'a> { + w: &'a mut W, +} +impl<'a> NRV0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `NRV1` reader - Non-Recoverable State 1 Output Value"] +pub struct NRV1_R(crate::FieldReader); +impl NRV1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRV1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRV1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRV1` writer - Non-Recoverable State 1 Output Value"] +pub struct NRV1_W<'a> { + w: &'a mut W, +} +impl<'a> NRV1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `NRV2` reader - Non-Recoverable State 2 Output Value"] +pub struct NRV2_R(crate::FieldReader); +impl NRV2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRV2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRV2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRV2` writer - Non-Recoverable State 2 Output Value"] +pub struct NRV2_W<'a> { + w: &'a mut W, +} +impl<'a> NRV2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `NRV3` reader - Non-Recoverable State 3 Output Value"] +pub struct NRV3_R(crate::FieldReader); +impl NRV3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRV3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRV3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRV3` writer - Non-Recoverable State 3 Output Value"] +pub struct NRV3_W<'a> { + w: &'a mut W, +} +impl<'a> NRV3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `NRV4` reader - Non-Recoverable State 4 Output Value"] +pub struct NRV4_R(crate::FieldReader); +impl NRV4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRV4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRV4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRV4` writer - Non-Recoverable State 4 Output Value"] +pub struct NRV4_W<'a> { + w: &'a mut W, +} +impl<'a> NRV4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `NRV5` reader - Non-Recoverable State 5 Output Value"] +pub struct NRV5_R(crate::FieldReader); +impl NRV5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRV5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRV5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRV5` writer - Non-Recoverable State 5 Output Value"] +pub struct NRV5_W<'a> { + w: &'a mut W, +} +impl<'a> NRV5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `NRV6` reader - Non-Recoverable State 6 Output Value"] +pub struct NRV6_R(crate::FieldReader); +impl NRV6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRV6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRV6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRV6` writer - Non-Recoverable State 6 Output Value"] +pub struct NRV6_W<'a> { + w: &'a mut W, +} +impl<'a> NRV6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `NRV7` reader - Non-Recoverable State 7 Output Value"] +pub struct NRV7_R(crate::FieldReader); +impl NRV7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRV7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRV7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRV7` writer - Non-Recoverable State 7 Output Value"] +pub struct NRV7_W<'a> { + w: &'a mut W, +} +impl<'a> NRV7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `INVEN0` reader - Output Waveform 0 Inversion"] +pub struct INVEN0_R(crate::FieldReader); +impl INVEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN0` writer - Output Waveform 0 Inversion"] +pub struct INVEN0_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `INVEN1` reader - Output Waveform 1 Inversion"] +pub struct INVEN1_R(crate::FieldReader); +impl INVEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN1` writer - Output Waveform 1 Inversion"] +pub struct INVEN1_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `INVEN2` reader - Output Waveform 2 Inversion"] +pub struct INVEN2_R(crate::FieldReader); +impl INVEN2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN2` writer - Output Waveform 2 Inversion"] +pub struct INVEN2_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `INVEN3` reader - Output Waveform 3 Inversion"] +pub struct INVEN3_R(crate::FieldReader); +impl INVEN3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN3` writer - Output Waveform 3 Inversion"] +pub struct INVEN3_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `INVEN4` reader - Output Waveform 4 Inversion"] +pub struct INVEN4_R(crate::FieldReader); +impl INVEN4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN4` writer - Output Waveform 4 Inversion"] +pub struct INVEN4_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `INVEN5` reader - Output Waveform 5 Inversion"] +pub struct INVEN5_R(crate::FieldReader); +impl INVEN5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN5` writer - Output Waveform 5 Inversion"] +pub struct INVEN5_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `INVEN6` reader - Output Waveform 6 Inversion"] +pub struct INVEN6_R(crate::FieldReader); +impl INVEN6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN6` writer - Output Waveform 6 Inversion"] +pub struct INVEN6_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `INVEN7` reader - Output Waveform 7 Inversion"] +pub struct INVEN7_R(crate::FieldReader); +impl INVEN7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN7` writer - Output Waveform 7 Inversion"] +pub struct INVEN7_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `FILTERVAL0` reader - Non-Recoverable Fault Input 0 Filter Value"] +pub struct FILTERVAL0_R(crate::FieldReader); +impl FILTERVAL0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FILTERVAL0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTERVAL0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTERVAL0` writer - Non-Recoverable Fault Input 0 Filter Value"] +pub struct FILTERVAL0_W<'a> { + w: &'a mut W, +} +impl<'a> FILTERVAL0_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Field `FILTERVAL1` reader - Non-Recoverable Fault Input 1 Filter Value"] +pub struct FILTERVAL1_R(crate::FieldReader); +impl FILTERVAL1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FILTERVAL1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTERVAL1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTERVAL1` writer - Non-Recoverable Fault Input 1 Filter Value"] +pub struct FILTERVAL1_W<'a> { + w: &'a mut W, +} +impl<'a> FILTERVAL1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 28)) | ((value as u32 & 0x0f) << 28); + self.w + } +} +impl R { + #[doc = "Bit 0 - Non-Recoverable State 0 Output Enable"] + #[inline(always)] + pub fn nre0(&self) -> NRE0_R { + NRE0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Non-Recoverable State 1 Output Enable"] + #[inline(always)] + pub fn nre1(&self) -> NRE1_R { + NRE1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Non-Recoverable State 2 Output Enable"] + #[inline(always)] + pub fn nre2(&self) -> NRE2_R { + NRE2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Non-Recoverable State 3 Output Enable"] + #[inline(always)] + pub fn nre3(&self) -> NRE3_R { + NRE3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Non-Recoverable State 4 Output Enable"] + #[inline(always)] + pub fn nre4(&self) -> NRE4_R { + NRE4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Non-Recoverable State 5 Output Enable"] + #[inline(always)] + pub fn nre5(&self) -> NRE5_R { + NRE5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Non-Recoverable State 6 Output Enable"] + #[inline(always)] + pub fn nre6(&self) -> NRE6_R { + NRE6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Non-Recoverable State 7 Output Enable"] + #[inline(always)] + pub fn nre7(&self) -> NRE7_R { + NRE7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Non-Recoverable State 0 Output Value"] + #[inline(always)] + pub fn nrv0(&self) -> NRV0_R { + NRV0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Non-Recoverable State 1 Output Value"] + #[inline(always)] + pub fn nrv1(&self) -> NRV1_R { + NRV1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Non-Recoverable State 2 Output Value"] + #[inline(always)] + pub fn nrv2(&self) -> NRV2_R { + NRV2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Non-Recoverable State 3 Output Value"] + #[inline(always)] + pub fn nrv3(&self) -> NRV3_R { + NRV3_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Non-Recoverable State 4 Output Value"] + #[inline(always)] + pub fn nrv4(&self) -> NRV4_R { + NRV4_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Non-Recoverable State 5 Output Value"] + #[inline(always)] + pub fn nrv5(&self) -> NRV5_R { + NRV5_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Non-Recoverable State 6 Output Value"] + #[inline(always)] + pub fn nrv6(&self) -> NRV6_R { + NRV6_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Non-Recoverable State 7 Output Value"] + #[inline(always)] + pub fn nrv7(&self) -> NRV7_R { + NRV7_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Output Waveform 0 Inversion"] + #[inline(always)] + pub fn inven0(&self) -> INVEN0_R { + INVEN0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Output Waveform 1 Inversion"] + #[inline(always)] + pub fn inven1(&self) -> INVEN1_R { + INVEN1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Output Waveform 2 Inversion"] + #[inline(always)] + pub fn inven2(&self) -> INVEN2_R { + INVEN2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Output Waveform 3 Inversion"] + #[inline(always)] + pub fn inven3(&self) -> INVEN3_R { + INVEN3_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Output Waveform 4 Inversion"] + #[inline(always)] + pub fn inven4(&self) -> INVEN4_R { + INVEN4_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Output Waveform 5 Inversion"] + #[inline(always)] + pub fn inven5(&self) -> INVEN5_R { + INVEN5_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Output Waveform 6 Inversion"] + #[inline(always)] + pub fn inven6(&self) -> INVEN6_R { + INVEN6_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Output Waveform 7 Inversion"] + #[inline(always)] + pub fn inven7(&self) -> INVEN7_R { + INVEN7_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bits 24:27 - Non-Recoverable Fault Input 0 Filter Value"] + #[inline(always)] + pub fn filterval0(&self) -> FILTERVAL0_R { + FILTERVAL0_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bits 28:31 - Non-Recoverable Fault Input 1 Filter Value"] + #[inline(always)] + pub fn filterval1(&self) -> FILTERVAL1_R { + FILTERVAL1_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bit 0 - Non-Recoverable State 0 Output Enable"] + #[inline(always)] + pub fn nre0(&mut self) -> NRE0_W { + NRE0_W { w: self } + } + #[doc = "Bit 1 - Non-Recoverable State 1 Output Enable"] + #[inline(always)] + pub fn nre1(&mut self) -> NRE1_W { + NRE1_W { w: self } + } + #[doc = "Bit 2 - Non-Recoverable State 2 Output Enable"] + #[inline(always)] + pub fn nre2(&mut self) -> NRE2_W { + NRE2_W { w: self } + } + #[doc = "Bit 3 - Non-Recoverable State 3 Output Enable"] + #[inline(always)] + pub fn nre3(&mut self) -> NRE3_W { + NRE3_W { w: self } + } + #[doc = "Bit 4 - Non-Recoverable State 4 Output Enable"] + #[inline(always)] + pub fn nre4(&mut self) -> NRE4_W { + NRE4_W { w: self } + } + #[doc = "Bit 5 - Non-Recoverable State 5 Output Enable"] + #[inline(always)] + pub fn nre5(&mut self) -> NRE5_W { + NRE5_W { w: self } + } + #[doc = "Bit 6 - Non-Recoverable State 6 Output Enable"] + #[inline(always)] + pub fn nre6(&mut self) -> NRE6_W { + NRE6_W { w: self } + } + #[doc = "Bit 7 - Non-Recoverable State 7 Output Enable"] + #[inline(always)] + pub fn nre7(&mut self) -> NRE7_W { + NRE7_W { w: self } + } + #[doc = "Bit 8 - Non-Recoverable State 0 Output Value"] + #[inline(always)] + pub fn nrv0(&mut self) -> NRV0_W { + NRV0_W { w: self } + } + #[doc = "Bit 9 - Non-Recoverable State 1 Output Value"] + #[inline(always)] + pub fn nrv1(&mut self) -> NRV1_W { + NRV1_W { w: self } + } + #[doc = "Bit 10 - Non-Recoverable State 2 Output Value"] + #[inline(always)] + pub fn nrv2(&mut self) -> NRV2_W { + NRV2_W { w: self } + } + #[doc = "Bit 11 - Non-Recoverable State 3 Output Value"] + #[inline(always)] + pub fn nrv3(&mut self) -> NRV3_W { + NRV3_W { w: self } + } + #[doc = "Bit 12 - Non-Recoverable State 4 Output Value"] + #[inline(always)] + pub fn nrv4(&mut self) -> NRV4_W { + NRV4_W { w: self } + } + #[doc = "Bit 13 - Non-Recoverable State 5 Output Value"] + #[inline(always)] + pub fn nrv5(&mut self) -> NRV5_W { + NRV5_W { w: self } + } + #[doc = "Bit 14 - Non-Recoverable State 6 Output Value"] + #[inline(always)] + pub fn nrv6(&mut self) -> NRV6_W { + NRV6_W { w: self } + } + #[doc = "Bit 15 - Non-Recoverable State 7 Output Value"] + #[inline(always)] + pub fn nrv7(&mut self) -> NRV7_W { + NRV7_W { w: self } + } + #[doc = "Bit 16 - Output Waveform 0 Inversion"] + #[inline(always)] + pub fn inven0(&mut self) -> INVEN0_W { + INVEN0_W { w: self } + } + #[doc = "Bit 17 - Output Waveform 1 Inversion"] + #[inline(always)] + pub fn inven1(&mut self) -> INVEN1_W { + INVEN1_W { w: self } + } + #[doc = "Bit 18 - Output Waveform 2 Inversion"] + #[inline(always)] + pub fn inven2(&mut self) -> INVEN2_W { + INVEN2_W { w: self } + } + #[doc = "Bit 19 - Output Waveform 3 Inversion"] + #[inline(always)] + pub fn inven3(&mut self) -> INVEN3_W { + INVEN3_W { w: self } + } + #[doc = "Bit 20 - Output Waveform 4 Inversion"] + #[inline(always)] + pub fn inven4(&mut self) -> INVEN4_W { + INVEN4_W { w: self } + } + #[doc = "Bit 21 - Output Waveform 5 Inversion"] + #[inline(always)] + pub fn inven5(&mut self) -> INVEN5_W { + INVEN5_W { w: self } + } + #[doc = "Bit 22 - Output Waveform 6 Inversion"] + #[inline(always)] + pub fn inven6(&mut self) -> INVEN6_W { + INVEN6_W { w: self } + } + #[doc = "Bit 23 - Output Waveform 7 Inversion"] + #[inline(always)] + pub fn inven7(&mut self) -> INVEN7_W { + INVEN7_W { w: self } + } + #[doc = "Bits 24:27 - Non-Recoverable Fault Input 0 Filter Value"] + #[inline(always)] + pub fn filterval0(&mut self) -> FILTERVAL0_W { + FILTERVAL0_W { w: self } + } + #[doc = "Bits 28:31 - Non-Recoverable Fault Input 1 Filter Value"] + #[inline(always)] + pub fn filterval1(&mut self) -> FILTERVAL1_W { + FILTERVAL1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Driver Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [drvctrl](index.html) module"] +pub struct DRVCTRL_SPEC; +impl crate::RegisterSpec for DRVCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [drvctrl::R](R) reader structure"] +impl crate::Readable for DRVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [drvctrl::W](W) writer structure"] +impl crate::Writable for DRVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DRVCTRL to value 0"] +impl crate::Resettable for DRVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/tcc0/evctrl.rs b/pac/atsamc20g/src/tcc0/evctrl.rs new file mode 100644 index 000000000000..334a53924d61 --- /dev/null +++ b/pac/atsamc20g/src/tcc0/evctrl.rs @@ -0,0 +1,1211 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Timer/counter Input Event0 Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EVACT0_A { + #[doc = "0: Event action disabled"] + OFF = 0, + #[doc = "1: Start, restart or re-trigger counter on event"] + RETRIGGER = 1, + #[doc = "2: Count on event"] + COUNTEV = 2, + #[doc = "3: Start counter on event"] + START = 3, + #[doc = "4: Increment counter on event"] + INC = 4, + #[doc = "5: Count on active state of asynchronous event"] + COUNT = 5, + #[doc = "6: Stamp capture"] + STAMP = 6, + #[doc = "7: Non-recoverable fault"] + FAULT = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EVACT0_A) -> Self { + variant as _ + } +} +#[doc = "Field `EVACT0` reader - Timer/counter Input Event0 Action"] +pub struct EVACT0_R(crate::FieldReader); +impl EVACT0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVACT0_A { + match self.bits { + 0 => EVACT0_A::OFF, + 1 => EVACT0_A::RETRIGGER, + 2 => EVACT0_A::COUNTEV, + 3 => EVACT0_A::START, + 4 => EVACT0_A::INC, + 5 => EVACT0_A::COUNT, + 6 => EVACT0_A::STAMP, + 7 => EVACT0_A::FAULT, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == EVACT0_A::OFF + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == EVACT0_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `COUNTEV`"] + #[inline(always)] + pub fn is_countev(&self) -> bool { + **self == EVACT0_A::COUNTEV + } + #[doc = "Checks if the value of the field is `START`"] + #[inline(always)] + pub fn is_start(&self) -> bool { + **self == EVACT0_A::START + } + #[doc = "Checks if the value of the field is `INC`"] + #[inline(always)] + pub fn is_inc(&self) -> bool { + **self == EVACT0_A::INC + } + #[doc = "Checks if the value of the field is `COUNT`"] + #[inline(always)] + pub fn is_count(&self) -> bool { + **self == EVACT0_A::COUNT + } + #[doc = "Checks if the value of the field is `STAMP`"] + #[inline(always)] + pub fn is_stamp(&self) -> bool { + **self == EVACT0_A::STAMP + } + #[doc = "Checks if the value of the field is `FAULT`"] + #[inline(always)] + pub fn is_fault(&self) -> bool { + **self == EVACT0_A::FAULT + } +} +impl core::ops::Deref for EVACT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT0` writer - Timer/counter Input Event0 Action"] +pub struct EVACT0_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT0_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EVACT0_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Event action disabled"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(EVACT0_A::OFF) + } + #[doc = "Start, restart or re-trigger counter on event"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(EVACT0_A::RETRIGGER) + } + #[doc = "Count on event"] + #[inline(always)] + pub fn countev(self) -> &'a mut W { + self.variant(EVACT0_A::COUNTEV) + } + #[doc = "Start counter on event"] + #[inline(always)] + pub fn start(self) -> &'a mut W { + self.variant(EVACT0_A::START) + } + #[doc = "Increment counter on event"] + #[inline(always)] + pub fn inc(self) -> &'a mut W { + self.variant(EVACT0_A::INC) + } + #[doc = "Count on active state of asynchronous event"] + #[inline(always)] + pub fn count(self) -> &'a mut W { + self.variant(EVACT0_A::COUNT) + } + #[doc = "Stamp capture"] + #[inline(always)] + pub fn stamp(self) -> &'a mut W { + self.variant(EVACT0_A::STAMP) + } + #[doc = "Non-recoverable fault"] + #[inline(always)] + pub fn fault(self) -> &'a mut W { + self.variant(EVACT0_A::FAULT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Timer/counter Input Event1 Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EVACT1_A { + #[doc = "0: Event action disabled"] + OFF = 0, + #[doc = "1: Re-trigger counter on event"] + RETRIGGER = 1, + #[doc = "2: Direction control"] + DIR = 2, + #[doc = "3: Stop counter on event"] + STOP = 3, + #[doc = "4: Decrement counter on event"] + DEC = 4, + #[doc = "5: Period capture value in CC0 register, pulse width capture value in CC1 register"] + PPW = 5, + #[doc = "6: Period capture value in CC1 register, pulse width capture value in CC0 register"] + PWP = 6, + #[doc = "7: Non-recoverable fault"] + FAULT = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EVACT1_A) -> Self { + variant as _ + } +} +#[doc = "Field `EVACT1` reader - Timer/counter Input Event1 Action"] +pub struct EVACT1_R(crate::FieldReader); +impl EVACT1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT1_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVACT1_A { + match self.bits { + 0 => EVACT1_A::OFF, + 1 => EVACT1_A::RETRIGGER, + 2 => EVACT1_A::DIR, + 3 => EVACT1_A::STOP, + 4 => EVACT1_A::DEC, + 5 => EVACT1_A::PPW, + 6 => EVACT1_A::PWP, + 7 => EVACT1_A::FAULT, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == EVACT1_A::OFF + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == EVACT1_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `DIR`"] + #[inline(always)] + pub fn is_dir(&self) -> bool { + **self == EVACT1_A::DIR + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == EVACT1_A::STOP + } + #[doc = "Checks if the value of the field is `DEC`"] + #[inline(always)] + pub fn is_dec(&self) -> bool { + **self == EVACT1_A::DEC + } + #[doc = "Checks if the value of the field is `PPW`"] + #[inline(always)] + pub fn is_ppw(&self) -> bool { + **self == EVACT1_A::PPW + } + #[doc = "Checks if the value of the field is `PWP`"] + #[inline(always)] + pub fn is_pwp(&self) -> bool { + **self == EVACT1_A::PWP + } + #[doc = "Checks if the value of the field is `FAULT`"] + #[inline(always)] + pub fn is_fault(&self) -> bool { + **self == EVACT1_A::FAULT + } +} +impl core::ops::Deref for EVACT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT1` writer - Timer/counter Input Event1 Action"] +pub struct EVACT1_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT1_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EVACT1_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Event action disabled"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(EVACT1_A::OFF) + } + #[doc = "Re-trigger counter on event"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(EVACT1_A::RETRIGGER) + } + #[doc = "Direction control"] + #[inline(always)] + pub fn dir(self) -> &'a mut W { + self.variant(EVACT1_A::DIR) + } + #[doc = "Stop counter on event"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(EVACT1_A::STOP) + } + #[doc = "Decrement counter on event"] + #[inline(always)] + pub fn dec(self) -> &'a mut W { + self.variant(EVACT1_A::DEC) + } + #[doc = "Period capture value in CC0 register, pulse width capture value in CC1 register"] + #[inline(always)] + pub fn ppw(self) -> &'a mut W { + self.variant(EVACT1_A::PPW) + } + #[doc = "Period capture value in CC1 register, pulse width capture value in CC0 register"] + #[inline(always)] + pub fn pwp(self) -> &'a mut W { + self.variant(EVACT1_A::PWP) + } + #[doc = "Non-recoverable fault"] + #[inline(always)] + pub fn fault(self) -> &'a mut W { + self.variant(EVACT1_A::FAULT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 3)) | ((value as u32 & 0x07) << 3); + self.w + } +} +#[doc = "Timer/counter Output Event Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CNTSEL_A { + #[doc = "0: An interrupt/event is generated when a new counter cycle starts"] + START = 0, + #[doc = "1: An interrupt/event is generated when a counter cycle ends"] + END = 1, + #[doc = "2: An interrupt/event is generated when a counter cycle ends, except for the first and last cycles"] + BETWEEN = 2, + #[doc = "3: An interrupt/event is generated when a new counter cycle starts or a counter cycle ends"] + BOUNDARY = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CNTSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `CNTSEL` reader - Timer/counter Output Event Mode"] +pub struct CNTSEL_R(crate::FieldReader); +impl CNTSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CNTSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CNTSEL_A { + match self.bits { + 0 => CNTSEL_A::START, + 1 => CNTSEL_A::END, + 2 => CNTSEL_A::BETWEEN, + 3 => CNTSEL_A::BOUNDARY, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `START`"] + #[inline(always)] + pub fn is_start(&self) -> bool { + **self == CNTSEL_A::START + } + #[doc = "Checks if the value of the field is `END`"] + #[inline(always)] + pub fn is_end(&self) -> bool { + **self == CNTSEL_A::END + } + #[doc = "Checks if the value of the field is `BETWEEN`"] + #[inline(always)] + pub fn is_between(&self) -> bool { + **self == CNTSEL_A::BETWEEN + } + #[doc = "Checks if the value of the field is `BOUNDARY`"] + #[inline(always)] + pub fn is_boundary(&self) -> bool { + **self == CNTSEL_A::BOUNDARY + } +} +impl core::ops::Deref for CNTSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CNTSEL` writer - Timer/counter Output Event Mode"] +pub struct CNTSEL_W<'a> { + w: &'a mut W, +} +impl<'a> CNTSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CNTSEL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "An interrupt/event is generated when a new counter cycle starts"] + #[inline(always)] + pub fn start(self) -> &'a mut W { + self.variant(CNTSEL_A::START) + } + #[doc = "An interrupt/event is generated when a counter cycle ends"] + #[inline(always)] + pub fn end(self) -> &'a mut W { + self.variant(CNTSEL_A::END) + } + #[doc = "An interrupt/event is generated when a counter cycle ends, except for the first and last cycles"] + #[inline(always)] + pub fn between(self) -> &'a mut W { + self.variant(CNTSEL_A::BETWEEN) + } + #[doc = "An interrupt/event is generated when a new counter cycle starts or a counter cycle ends"] + #[inline(always)] + pub fn boundary(self) -> &'a mut W { + self.variant(CNTSEL_A::BOUNDARY) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 6)) | ((value as u32 & 0x03) << 6); + self.w + } +} +#[doc = "Field `OVFEO` reader - Overflow/Underflow Output Event Enable"] +pub struct OVFEO_R(crate::FieldReader); +impl OVFEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVFEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVFEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVFEO` writer - Overflow/Underflow Output Event Enable"] +pub struct OVFEO_W<'a> { + w: &'a mut W, +} +impl<'a> OVFEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `TRGEO` reader - Retrigger Output Event Enable"] +pub struct TRGEO_R(crate::FieldReader); +impl TRGEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRGEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRGEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRGEO` writer - Retrigger Output Event Enable"] +pub struct TRGEO_W<'a> { + w: &'a mut W, +} +impl<'a> TRGEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `CNTEO` reader - Timer/counter Output Event Enable"] +pub struct CNTEO_R(crate::FieldReader); +impl CNTEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CNTEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CNTEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CNTEO` writer - Timer/counter Output Event Enable"] +pub struct CNTEO_W<'a> { + w: &'a mut W, +} +impl<'a> CNTEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `TCINV0` reader - Inverted Event 0 Input Enable"] +pub struct TCINV0_R(crate::FieldReader); +impl TCINV0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCINV0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCINV0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCINV0` writer - Inverted Event 0 Input Enable"] +pub struct TCINV0_W<'a> { + w: &'a mut W, +} +impl<'a> TCINV0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `TCINV1` reader - Inverted Event 1 Input Enable"] +pub struct TCINV1_R(crate::FieldReader); +impl TCINV1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCINV1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCINV1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCINV1` writer - Inverted Event 1 Input Enable"] +pub struct TCINV1_W<'a> { + w: &'a mut W, +} +impl<'a> TCINV1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `TCEI0` reader - Timer/counter Event 0 Input Enable"] +pub struct TCEI0_R(crate::FieldReader); +impl TCEI0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCEI0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCEI0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCEI0` writer - Timer/counter Event 0 Input Enable"] +pub struct TCEI0_W<'a> { + w: &'a mut W, +} +impl<'a> TCEI0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `TCEI1` reader - Timer/counter Event 1 Input Enable"] +pub struct TCEI1_R(crate::FieldReader); +impl TCEI1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCEI1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCEI1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCEI1` writer - Timer/counter Event 1 Input Enable"] +pub struct TCEI1_W<'a> { + w: &'a mut W, +} +impl<'a> TCEI1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `MCEI0` reader - Match or Capture Channel 0 Event Input Enable"] +pub struct MCEI0_R(crate::FieldReader); +impl MCEI0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEI0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEI0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEI0` writer - Match or Capture Channel 0 Event Input Enable"] +pub struct MCEI0_W<'a> { + w: &'a mut W, +} +impl<'a> MCEI0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `MCEI1` reader - Match or Capture Channel 1 Event Input Enable"] +pub struct MCEI1_R(crate::FieldReader); +impl MCEI1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEI1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEI1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEI1` writer - Match or Capture Channel 1 Event Input Enable"] +pub struct MCEI1_W<'a> { + w: &'a mut W, +} +impl<'a> MCEI1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `MCEI2` reader - Match or Capture Channel 2 Event Input Enable"] +pub struct MCEI2_R(crate::FieldReader); +impl MCEI2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEI2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEI2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEI2` writer - Match or Capture Channel 2 Event Input Enable"] +pub struct MCEI2_W<'a> { + w: &'a mut W, +} +impl<'a> MCEI2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `MCEI3` reader - Match or Capture Channel 3 Event Input Enable"] +pub struct MCEI3_R(crate::FieldReader); +impl MCEI3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEI3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEI3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEI3` writer - Match or Capture Channel 3 Event Input Enable"] +pub struct MCEI3_W<'a> { + w: &'a mut W, +} +impl<'a> MCEI3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `MCEO0` reader - Match or Capture Channel 0 Event Output Enable"] +pub struct MCEO0_R(crate::FieldReader); +impl MCEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO0` writer - Match or Capture Channel 0 Event Output Enable"] +pub struct MCEO0_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `MCEO1` reader - Match or Capture Channel 1 Event Output Enable"] +pub struct MCEO1_R(crate::FieldReader); +impl MCEO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO1` writer - Match or Capture Channel 1 Event Output Enable"] +pub struct MCEO1_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `MCEO2` reader - Match or Capture Channel 2 Event Output Enable"] +pub struct MCEO2_R(crate::FieldReader); +impl MCEO2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO2` writer - Match or Capture Channel 2 Event Output Enable"] +pub struct MCEO2_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `MCEO3` reader - Match or Capture Channel 3 Event Output Enable"] +pub struct MCEO3_R(crate::FieldReader); +impl MCEO3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO3` writer - Match or Capture Channel 3 Event Output Enable"] +pub struct MCEO3_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Timer/counter Input Event0 Action"] + #[inline(always)] + pub fn evact0(&self) -> EVACT0_R { + EVACT0_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bits 3:5 - Timer/counter Input Event1 Action"] + #[inline(always)] + pub fn evact1(&self) -> EVACT1_R { + EVACT1_R::new(((self.bits >> 3) & 0x07) as u8) + } + #[doc = "Bits 6:7 - Timer/counter Output Event Mode"] + #[inline(always)] + pub fn cntsel(&self) -> CNTSEL_R { + CNTSEL_R::new(((self.bits >> 6) & 0x03) as u8) + } + #[doc = "Bit 8 - Overflow/Underflow Output Event Enable"] + #[inline(always)] + pub fn ovfeo(&self) -> OVFEO_R { + OVFEO_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Retrigger Output Event Enable"] + #[inline(always)] + pub fn trgeo(&self) -> TRGEO_R { + TRGEO_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Timer/counter Output Event Enable"] + #[inline(always)] + pub fn cnteo(&self) -> CNTEO_R { + CNTEO_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 12 - Inverted Event 0 Input Enable"] + #[inline(always)] + pub fn tcinv0(&self) -> TCINV0_R { + TCINV0_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Inverted Event 1 Input Enable"] + #[inline(always)] + pub fn tcinv1(&self) -> TCINV1_R { + TCINV1_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Timer/counter Event 0 Input Enable"] + #[inline(always)] + pub fn tcei0(&self) -> TCEI0_R { + TCEI0_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Timer/counter Event 1 Input Enable"] + #[inline(always)] + pub fn tcei1(&self) -> TCEI1_R { + TCEI1_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Match or Capture Channel 0 Event Input Enable"] + #[inline(always)] + pub fn mcei0(&self) -> MCEI0_R { + MCEI0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Match or Capture Channel 1 Event Input Enable"] + #[inline(always)] + pub fn mcei1(&self) -> MCEI1_R { + MCEI1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Match or Capture Channel 2 Event Input Enable"] + #[inline(always)] + pub fn mcei2(&self) -> MCEI2_R { + MCEI2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Match or Capture Channel 3 Event Input Enable"] + #[inline(always)] + pub fn mcei3(&self) -> MCEI3_R { + MCEI3_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 24 - Match or Capture Channel 0 Event Output Enable"] + #[inline(always)] + pub fn mceo0(&self) -> MCEO0_R { + MCEO0_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Match or Capture Channel 1 Event Output Enable"] + #[inline(always)] + pub fn mceo1(&self) -> MCEO1_R { + MCEO1_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Match or Capture Channel 2 Event Output Enable"] + #[inline(always)] + pub fn mceo2(&self) -> MCEO2_R { + MCEO2_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Match or Capture Channel 3 Event Output Enable"] + #[inline(always)] + pub fn mceo3(&self) -> MCEO3_R { + MCEO3_R::new(((self.bits >> 27) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Timer/counter Input Event0 Action"] + #[inline(always)] + pub fn evact0(&mut self) -> EVACT0_W { + EVACT0_W { w: self } + } + #[doc = "Bits 3:5 - Timer/counter Input Event1 Action"] + #[inline(always)] + pub fn evact1(&mut self) -> EVACT1_W { + EVACT1_W { w: self } + } + #[doc = "Bits 6:7 - Timer/counter Output Event Mode"] + #[inline(always)] + pub fn cntsel(&mut self) -> CNTSEL_W { + CNTSEL_W { w: self } + } + #[doc = "Bit 8 - Overflow/Underflow Output Event Enable"] + #[inline(always)] + pub fn ovfeo(&mut self) -> OVFEO_W { + OVFEO_W { w: self } + } + #[doc = "Bit 9 - Retrigger Output Event Enable"] + #[inline(always)] + pub fn trgeo(&mut self) -> TRGEO_W { + TRGEO_W { w: self } + } + #[doc = "Bit 10 - Timer/counter Output Event Enable"] + #[inline(always)] + pub fn cnteo(&mut self) -> CNTEO_W { + CNTEO_W { w: self } + } + #[doc = "Bit 12 - Inverted Event 0 Input Enable"] + #[inline(always)] + pub fn tcinv0(&mut self) -> TCINV0_W { + TCINV0_W { w: self } + } + #[doc = "Bit 13 - Inverted Event 1 Input Enable"] + #[inline(always)] + pub fn tcinv1(&mut self) -> TCINV1_W { + TCINV1_W { w: self } + } + #[doc = "Bit 14 - Timer/counter Event 0 Input Enable"] + #[inline(always)] + pub fn tcei0(&mut self) -> TCEI0_W { + TCEI0_W { w: self } + } + #[doc = "Bit 15 - Timer/counter Event 1 Input Enable"] + #[inline(always)] + pub fn tcei1(&mut self) -> TCEI1_W { + TCEI1_W { w: self } + } + #[doc = "Bit 16 - Match or Capture Channel 0 Event Input Enable"] + #[inline(always)] + pub fn mcei0(&mut self) -> MCEI0_W { + MCEI0_W { w: self } + } + #[doc = "Bit 17 - Match or Capture Channel 1 Event Input Enable"] + #[inline(always)] + pub fn mcei1(&mut self) -> MCEI1_W { + MCEI1_W { w: self } + } + #[doc = "Bit 18 - Match or Capture Channel 2 Event Input Enable"] + #[inline(always)] + pub fn mcei2(&mut self) -> MCEI2_W { + MCEI2_W { w: self } + } + #[doc = "Bit 19 - Match or Capture Channel 3 Event Input Enable"] + #[inline(always)] + pub fn mcei3(&mut self) -> MCEI3_W { + MCEI3_W { w: self } + } + #[doc = "Bit 24 - Match or Capture Channel 0 Event Output Enable"] + #[inline(always)] + pub fn mceo0(&mut self) -> MCEO0_W { + MCEO0_W { w: self } + } + #[doc = "Bit 25 - Match or Capture Channel 1 Event Output Enable"] + #[inline(always)] + pub fn mceo1(&mut self) -> MCEO1_W { + MCEO1_W { w: self } + } + #[doc = "Bit 26 - Match or Capture Channel 2 Event Output Enable"] + #[inline(always)] + pub fn mceo2(&mut self) -> MCEO2_W { + MCEO2_W { w: self } + } + #[doc = "Bit 27 - Match or Capture Channel 3 Event Output Enable"] + #[inline(always)] + pub fn mceo3(&mut self) -> MCEO3_W { + MCEO3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/tcc0/fctrla.rs b/pac/atsamc20g/src/tcc0/fctrla.rs new file mode 100644 index 000000000000..77c7276fee23 --- /dev/null +++ b/pac/atsamc20g/src/tcc0/fctrla.rs @@ -0,0 +1,940 @@ +#[doc = "Register `FCTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FCTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Fault A Source\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SRC_A { + #[doc = "0: Fault input disabled"] + DISABLE = 0, + #[doc = "1: MCEx (x=0,1) event input"] + ENABLE = 1, + #[doc = "2: Inverted MCEx (x=0,1) event input"] + INVERT = 2, + #[doc = "3: Alternate fault (A or B) state at the end of the previous period"] + ALTFAULT = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SRC_A) -> Self { + variant as _ + } +} +#[doc = "Field `SRC` reader - Fault A Source"] +pub struct SRC_R(crate::FieldReader); +impl SRC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SRC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SRC_A { + match self.bits { + 0 => SRC_A::DISABLE, + 1 => SRC_A::ENABLE, + 2 => SRC_A::INVERT, + 3 => SRC_A::ALTFAULT, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == SRC_A::DISABLE + } + #[doc = "Checks if the value of the field is `ENABLE`"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + **self == SRC_A::ENABLE + } + #[doc = "Checks if the value of the field is `INVERT`"] + #[inline(always)] + pub fn is_invert(&self) -> bool { + **self == SRC_A::INVERT + } + #[doc = "Checks if the value of the field is `ALTFAULT`"] + #[inline(always)] + pub fn is_altfault(&self) -> bool { + **self == SRC_A::ALTFAULT + } +} +impl core::ops::Deref for SRC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SRC` writer - Fault A Source"] +pub struct SRC_W<'a> { + w: &'a mut W, +} +impl<'a> SRC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SRC_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Fault input disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(SRC_A::DISABLE) + } + #[doc = "MCEx (x=0,1) event input"] + #[inline(always)] + pub fn enable(self) -> &'a mut W { + self.variant(SRC_A::ENABLE) + } + #[doc = "Inverted MCEx (x=0,1) event input"] + #[inline(always)] + pub fn invert(self) -> &'a mut W { + self.variant(SRC_A::INVERT) + } + #[doc = "Alternate fault (A or B) state at the end of the previous period"] + #[inline(always)] + pub fn altfault(self) -> &'a mut W { + self.variant(SRC_A::ALTFAULT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u32 & 0x03); + self.w + } +} +#[doc = "Field `KEEP` reader - Fault A Keeper"] +pub struct KEEP_R(crate::FieldReader); +impl KEEP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + KEEP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for KEEP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `KEEP` writer - Fault A Keeper"] +pub struct KEEP_W<'a> { + w: &'a mut W, +} +impl<'a> KEEP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `QUAL` reader - Fault A Qualification"] +pub struct QUAL_R(crate::FieldReader); +impl QUAL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + QUAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for QUAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `QUAL` writer - Fault A Qualification"] +pub struct QUAL_W<'a> { + w: &'a mut W, +} +impl<'a> QUAL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Fault A Blanking Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum BLANK_A { + #[doc = "0: Blanking applied from start of the ramp"] + START = 0, + #[doc = "1: Blanking applied from rising edge of the output waveform"] + RISE = 1, + #[doc = "2: Blanking applied from falling edge of the output waveform"] + FALL = 2, + #[doc = "3: Blanking applied from each toggle of the output waveform"] + BOTH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: BLANK_A) -> Self { + variant as _ + } +} +#[doc = "Field `BLANK` reader - Fault A Blanking Mode"] +pub struct BLANK_R(crate::FieldReader); +impl BLANK_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BLANK_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> BLANK_A { + match self.bits { + 0 => BLANK_A::START, + 1 => BLANK_A::RISE, + 2 => BLANK_A::FALL, + 3 => BLANK_A::BOTH, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `START`"] + #[inline(always)] + pub fn is_start(&self) -> bool { + **self == BLANK_A::START + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == BLANK_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == BLANK_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == BLANK_A::BOTH + } +} +impl core::ops::Deref for BLANK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BLANK` writer - Fault A Blanking Mode"] +pub struct BLANK_W<'a> { + w: &'a mut W, +} +impl<'a> BLANK_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: BLANK_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Blanking applied from start of the ramp"] + #[inline(always)] + pub fn start(self) -> &'a mut W { + self.variant(BLANK_A::START) + } + #[doc = "Blanking applied from rising edge of the output waveform"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(BLANK_A::RISE) + } + #[doc = "Blanking applied from falling edge of the output waveform"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(BLANK_A::FALL) + } + #[doc = "Blanking applied from each toggle of the output waveform"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(BLANK_A::BOTH) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 5)) | ((value as u32 & 0x03) << 5); + self.w + } +} +#[doc = "Field `RESTART` reader - Fault A Restart"] +pub struct RESTART_R(crate::FieldReader); +impl RESTART_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESTART_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESTART_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESTART` writer - Fault A Restart"] +pub struct RESTART_W<'a> { + w: &'a mut W, +} +impl<'a> RESTART_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Fault A Halt Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum HALT_A { + #[doc = "0: Halt action disabled"] + DISABLE = 0, + #[doc = "1: Hardware halt action"] + HW = 1, + #[doc = "2: Software halt action"] + SW = 2, + #[doc = "3: Non-recoverable fault"] + NR = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: HALT_A) -> Self { + variant as _ + } +} +#[doc = "Field `HALT` reader - Fault A Halt Mode"] +pub struct HALT_R(crate::FieldReader); +impl HALT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + HALT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> HALT_A { + match self.bits { + 0 => HALT_A::DISABLE, + 1 => HALT_A::HW, + 2 => HALT_A::SW, + 3 => HALT_A::NR, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == HALT_A::DISABLE + } + #[doc = "Checks if the value of the field is `HW`"] + #[inline(always)] + pub fn is_hw(&self) -> bool { + **self == HALT_A::HW + } + #[doc = "Checks if the value of the field is `SW`"] + #[inline(always)] + pub fn is_sw(&self) -> bool { + **self == HALT_A::SW + } + #[doc = "Checks if the value of the field is `NR`"] + #[inline(always)] + pub fn is_nr(&self) -> bool { + **self == HALT_A::NR + } +} +impl core::ops::Deref for HALT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HALT` writer - Fault A Halt Mode"] +pub struct HALT_W<'a> { + w: &'a mut W, +} +impl<'a> HALT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: HALT_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Halt action disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(HALT_A::DISABLE) + } + #[doc = "Hardware halt action"] + #[inline(always)] + pub fn hw(self) -> &'a mut W { + self.variant(HALT_A::HW) + } + #[doc = "Software halt action"] + #[inline(always)] + pub fn sw(self) -> &'a mut W { + self.variant(HALT_A::SW) + } + #[doc = "Non-recoverable fault"] + #[inline(always)] + pub fn nr(self) -> &'a mut W { + self.variant(HALT_A::NR) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 8)) | ((value as u32 & 0x03) << 8); + self.w + } +} +#[doc = "Fault A Capture Channel\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CHSEL_A { + #[doc = "0: Capture value stored in channel 0"] + CC0 = 0, + #[doc = "1: Capture value stored in channel 1"] + CC1 = 1, + #[doc = "2: Capture value stored in channel 2"] + CC2 = 2, + #[doc = "3: Capture value stored in channel 3"] + CC3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CHSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `CHSEL` reader - Fault A Capture Channel"] +pub struct CHSEL_R(crate::FieldReader); +impl CHSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CHSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CHSEL_A { + match self.bits { + 0 => CHSEL_A::CC0, + 1 => CHSEL_A::CC1, + 2 => CHSEL_A::CC2, + 3 => CHSEL_A::CC3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `CC0`"] + #[inline(always)] + pub fn is_cc0(&self) -> bool { + **self == CHSEL_A::CC0 + } + #[doc = "Checks if the value of the field is `CC1`"] + #[inline(always)] + pub fn is_cc1(&self) -> bool { + **self == CHSEL_A::CC1 + } + #[doc = "Checks if the value of the field is `CC2`"] + #[inline(always)] + pub fn is_cc2(&self) -> bool { + **self == CHSEL_A::CC2 + } + #[doc = "Checks if the value of the field is `CC3`"] + #[inline(always)] + pub fn is_cc3(&self) -> bool { + **self == CHSEL_A::CC3 + } +} +impl core::ops::Deref for CHSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHSEL` writer - Fault A Capture Channel"] +pub struct CHSEL_W<'a> { + w: &'a mut W, +} +impl<'a> CHSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CHSEL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Capture value stored in channel 0"] + #[inline(always)] + pub fn cc0(self) -> &'a mut W { + self.variant(CHSEL_A::CC0) + } + #[doc = "Capture value stored in channel 1"] + #[inline(always)] + pub fn cc1(self) -> &'a mut W { + self.variant(CHSEL_A::CC1) + } + #[doc = "Capture value stored in channel 2"] + #[inline(always)] + pub fn cc2(self) -> &'a mut W { + self.variant(CHSEL_A::CC2) + } + #[doc = "Capture value stored in channel 3"] + #[inline(always)] + pub fn cc3(self) -> &'a mut W { + self.variant(CHSEL_A::CC3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 10)) | ((value as u32 & 0x03) << 10); + self.w + } +} +#[doc = "Fault A Capture Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CAPTURE_A { + #[doc = "0: No capture"] + DISABLE = 0, + #[doc = "1: Capture on fault"] + CAPT = 1, + #[doc = "2: Minimum capture"] + CAPTMIN = 2, + #[doc = "3: Maximum capture"] + CAPTMAX = 3, + #[doc = "4: Minimum local detection"] + LOCMIN = 4, + #[doc = "5: Maximum local detection"] + LOCMAX = 5, + #[doc = "6: Minimum and maximum local detection"] + DERIV0 = 6, + #[doc = "7: Capture with ramp index as MSB value"] + CAPTMARK = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CAPTURE_A) -> Self { + variant as _ + } +} +#[doc = "Field `CAPTURE` reader - Fault A Capture Action"] +pub struct CAPTURE_R(crate::FieldReader); +impl CAPTURE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CAPTURE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CAPTURE_A { + match self.bits { + 0 => CAPTURE_A::DISABLE, + 1 => CAPTURE_A::CAPT, + 2 => CAPTURE_A::CAPTMIN, + 3 => CAPTURE_A::CAPTMAX, + 4 => CAPTURE_A::LOCMIN, + 5 => CAPTURE_A::LOCMAX, + 6 => CAPTURE_A::DERIV0, + 7 => CAPTURE_A::CAPTMARK, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == CAPTURE_A::DISABLE + } + #[doc = "Checks if the value of the field is `CAPT`"] + #[inline(always)] + pub fn is_capt(&self) -> bool { + **self == CAPTURE_A::CAPT + } + #[doc = "Checks if the value of the field is `CAPTMIN`"] + #[inline(always)] + pub fn is_captmin(&self) -> bool { + **self == CAPTURE_A::CAPTMIN + } + #[doc = "Checks if the value of the field is `CAPTMAX`"] + #[inline(always)] + pub fn is_captmax(&self) -> bool { + **self == CAPTURE_A::CAPTMAX + } + #[doc = "Checks if the value of the field is `LOCMIN`"] + #[inline(always)] + pub fn is_locmin(&self) -> bool { + **self == CAPTURE_A::LOCMIN + } + #[doc = "Checks if the value of the field is `LOCMAX`"] + #[inline(always)] + pub fn is_locmax(&self) -> bool { + **self == CAPTURE_A::LOCMAX + } + #[doc = "Checks if the value of the field is `DERIV0`"] + #[inline(always)] + pub fn is_deriv0(&self) -> bool { + **self == CAPTURE_A::DERIV0 + } + #[doc = "Checks if the value of the field is `CAPTMARK`"] + #[inline(always)] + pub fn is_captmark(&self) -> bool { + **self == CAPTURE_A::CAPTMARK + } +} +impl core::ops::Deref for CAPTURE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAPTURE` writer - Fault A Capture Action"] +pub struct CAPTURE_W<'a> { + w: &'a mut W, +} +impl<'a> CAPTURE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CAPTURE_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "No capture"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(CAPTURE_A::DISABLE) + } + #[doc = "Capture on fault"] + #[inline(always)] + pub fn capt(self) -> &'a mut W { + self.variant(CAPTURE_A::CAPT) + } + #[doc = "Minimum capture"] + #[inline(always)] + pub fn captmin(self) -> &'a mut W { + self.variant(CAPTURE_A::CAPTMIN) + } + #[doc = "Maximum capture"] + #[inline(always)] + pub fn captmax(self) -> &'a mut W { + self.variant(CAPTURE_A::CAPTMAX) + } + #[doc = "Minimum local detection"] + #[inline(always)] + pub fn locmin(self) -> &'a mut W { + self.variant(CAPTURE_A::LOCMIN) + } + #[doc = "Maximum local detection"] + #[inline(always)] + pub fn locmax(self) -> &'a mut W { + self.variant(CAPTURE_A::LOCMAX) + } + #[doc = "Minimum and maximum local detection"] + #[inline(always)] + pub fn deriv0(self) -> &'a mut W { + self.variant(CAPTURE_A::DERIV0) + } + #[doc = "Capture with ramp index as MSB value"] + #[inline(always)] + pub fn captmark(self) -> &'a mut W { + self.variant(CAPTURE_A::CAPTMARK) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 12)) | ((value as u32 & 0x07) << 12); + self.w + } +} +#[doc = "Field `BLANKPRESC` reader - Fault A Blanking Prescaler"] +pub struct BLANKPRESC_R(crate::FieldReader); +impl BLANKPRESC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BLANKPRESC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BLANKPRESC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BLANKPRESC` writer - Fault A Blanking Prescaler"] +pub struct BLANKPRESC_W<'a> { + w: &'a mut W, +} +impl<'a> BLANKPRESC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `BLANKVAL` reader - Fault A Blanking Time"] +pub struct BLANKVAL_R(crate::FieldReader); +impl BLANKVAL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BLANKVAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BLANKVAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BLANKVAL` writer - Fault A Blanking Time"] +pub struct BLANKVAL_W<'a> { + w: &'a mut W, +} +impl<'a> BLANKVAL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +#[doc = "Field `FILTERVAL` reader - Fault A Filter Value"] +pub struct FILTERVAL_R(crate::FieldReader); +impl FILTERVAL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FILTERVAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTERVAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTERVAL` writer - Fault A Filter Value"] +pub struct FILTERVAL_W<'a> { + w: &'a mut W, +} +impl<'a> FILTERVAL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Fault A Source"] + #[inline(always)] + pub fn src(&self) -> SRC_R { + SRC_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bit 3 - Fault A Keeper"] + #[inline(always)] + pub fn keep(&self) -> KEEP_R { + KEEP_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Fault A Qualification"] + #[inline(always)] + pub fn qual(&self) -> QUAL_R { + QUAL_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bits 5:6 - Fault A Blanking Mode"] + #[inline(always)] + pub fn blank(&self) -> BLANK_R { + BLANK_R::new(((self.bits >> 5) & 0x03) as u8) + } + #[doc = "Bit 7 - Fault A Restart"] + #[inline(always)] + pub fn restart(&self) -> RESTART_R { + RESTART_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:9 - Fault A Halt Mode"] + #[inline(always)] + pub fn halt(&self) -> HALT_R { + HALT_R::new(((self.bits >> 8) & 0x03) as u8) + } + #[doc = "Bits 10:11 - Fault A Capture Channel"] + #[inline(always)] + pub fn chsel(&self) -> CHSEL_R { + CHSEL_R::new(((self.bits >> 10) & 0x03) as u8) + } + #[doc = "Bits 12:14 - Fault A Capture Action"] + #[inline(always)] + pub fn capture(&self) -> CAPTURE_R { + CAPTURE_R::new(((self.bits >> 12) & 0x07) as u8) + } + #[doc = "Bit 15 - Fault A Blanking Prescaler"] + #[inline(always)] + pub fn blankpresc(&self) -> BLANKPRESC_R { + BLANKPRESC_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:23 - Fault A Blanking Time"] + #[inline(always)] + pub fn blankval(&self) -> BLANKVAL_R { + BLANKVAL_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:27 - Fault A Filter Value"] + #[inline(always)] + pub fn filterval(&self) -> FILTERVAL_R { + FILTERVAL_R::new(((self.bits >> 24) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Fault A Source"] + #[inline(always)] + pub fn src(&mut self) -> SRC_W { + SRC_W { w: self } + } + #[doc = "Bit 3 - Fault A Keeper"] + #[inline(always)] + pub fn keep(&mut self) -> KEEP_W { + KEEP_W { w: self } + } + #[doc = "Bit 4 - Fault A Qualification"] + #[inline(always)] + pub fn qual(&mut self) -> QUAL_W { + QUAL_W { w: self } + } + #[doc = "Bits 5:6 - Fault A Blanking Mode"] + #[inline(always)] + pub fn blank(&mut self) -> BLANK_W { + BLANK_W { w: self } + } + #[doc = "Bit 7 - Fault A Restart"] + #[inline(always)] + pub fn restart(&mut self) -> RESTART_W { + RESTART_W { w: self } + } + #[doc = "Bits 8:9 - Fault A Halt Mode"] + #[inline(always)] + pub fn halt(&mut self) -> HALT_W { + HALT_W { w: self } + } + #[doc = "Bits 10:11 - Fault A Capture Channel"] + #[inline(always)] + pub fn chsel(&mut self) -> CHSEL_W { + CHSEL_W { w: self } + } + #[doc = "Bits 12:14 - Fault A Capture Action"] + #[inline(always)] + pub fn capture(&mut self) -> CAPTURE_W { + CAPTURE_W { w: self } + } + #[doc = "Bit 15 - Fault A Blanking Prescaler"] + #[inline(always)] + pub fn blankpresc(&mut self) -> BLANKPRESC_W { + BLANKPRESC_W { w: self } + } + #[doc = "Bits 16:23 - Fault A Blanking Time"] + #[inline(always)] + pub fn blankval(&mut self) -> BLANKVAL_W { + BLANKVAL_W { w: self } + } + #[doc = "Bits 24:27 - Fault A Filter Value"] + #[inline(always)] + pub fn filterval(&mut self) -> FILTERVAL_W { + FILTERVAL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Recoverable Fault A Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fctrla](index.html) module"] +pub struct FCTRLA_SPEC; +impl crate::RegisterSpec for FCTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [fctrla::R](R) reader structure"] +impl crate::Readable for FCTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [fctrla::W](W) writer structure"] +impl crate::Writable for FCTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets FCTRLA to value 0"] +impl crate::Resettable for FCTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/tcc0/fctrlb.rs b/pac/atsamc20g/src/tcc0/fctrlb.rs new file mode 100644 index 000000000000..4c1dfd1af93d --- /dev/null +++ b/pac/atsamc20g/src/tcc0/fctrlb.rs @@ -0,0 +1,940 @@ +#[doc = "Register `FCTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FCTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Fault B Source\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SRC_A { + #[doc = "0: Fault input disabled"] + DISABLE = 0, + #[doc = "1: MCEx (x=0,1) event input"] + ENABLE = 1, + #[doc = "2: Inverted MCEx (x=0,1) event input"] + INVERT = 2, + #[doc = "3: Alternate fault (A or B) state at the end of the previous period"] + ALTFAULT = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SRC_A) -> Self { + variant as _ + } +} +#[doc = "Field `SRC` reader - Fault B Source"] +pub struct SRC_R(crate::FieldReader); +impl SRC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SRC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SRC_A { + match self.bits { + 0 => SRC_A::DISABLE, + 1 => SRC_A::ENABLE, + 2 => SRC_A::INVERT, + 3 => SRC_A::ALTFAULT, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == SRC_A::DISABLE + } + #[doc = "Checks if the value of the field is `ENABLE`"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + **self == SRC_A::ENABLE + } + #[doc = "Checks if the value of the field is `INVERT`"] + #[inline(always)] + pub fn is_invert(&self) -> bool { + **self == SRC_A::INVERT + } + #[doc = "Checks if the value of the field is `ALTFAULT`"] + #[inline(always)] + pub fn is_altfault(&self) -> bool { + **self == SRC_A::ALTFAULT + } +} +impl core::ops::Deref for SRC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SRC` writer - Fault B Source"] +pub struct SRC_W<'a> { + w: &'a mut W, +} +impl<'a> SRC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SRC_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Fault input disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(SRC_A::DISABLE) + } + #[doc = "MCEx (x=0,1) event input"] + #[inline(always)] + pub fn enable(self) -> &'a mut W { + self.variant(SRC_A::ENABLE) + } + #[doc = "Inverted MCEx (x=0,1) event input"] + #[inline(always)] + pub fn invert(self) -> &'a mut W { + self.variant(SRC_A::INVERT) + } + #[doc = "Alternate fault (A or B) state at the end of the previous period"] + #[inline(always)] + pub fn altfault(self) -> &'a mut W { + self.variant(SRC_A::ALTFAULT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u32 & 0x03); + self.w + } +} +#[doc = "Field `KEEP` reader - Fault B Keeper"] +pub struct KEEP_R(crate::FieldReader); +impl KEEP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + KEEP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for KEEP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `KEEP` writer - Fault B Keeper"] +pub struct KEEP_W<'a> { + w: &'a mut W, +} +impl<'a> KEEP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `QUAL` reader - Fault B Qualification"] +pub struct QUAL_R(crate::FieldReader); +impl QUAL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + QUAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for QUAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `QUAL` writer - Fault B Qualification"] +pub struct QUAL_W<'a> { + w: &'a mut W, +} +impl<'a> QUAL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Fault B Blanking Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum BLANK_A { + #[doc = "0: Blanking applied from start of the ramp"] + START = 0, + #[doc = "1: Blanking applied from rising edge of the output waveform"] + RISE = 1, + #[doc = "2: Blanking applied from falling edge of the output waveform"] + FALL = 2, + #[doc = "3: Blanking applied from each toggle of the output waveform"] + BOTH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: BLANK_A) -> Self { + variant as _ + } +} +#[doc = "Field `BLANK` reader - Fault B Blanking Mode"] +pub struct BLANK_R(crate::FieldReader); +impl BLANK_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BLANK_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> BLANK_A { + match self.bits { + 0 => BLANK_A::START, + 1 => BLANK_A::RISE, + 2 => BLANK_A::FALL, + 3 => BLANK_A::BOTH, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `START`"] + #[inline(always)] + pub fn is_start(&self) -> bool { + **self == BLANK_A::START + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == BLANK_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == BLANK_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == BLANK_A::BOTH + } +} +impl core::ops::Deref for BLANK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BLANK` writer - Fault B Blanking Mode"] +pub struct BLANK_W<'a> { + w: &'a mut W, +} +impl<'a> BLANK_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: BLANK_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Blanking applied from start of the ramp"] + #[inline(always)] + pub fn start(self) -> &'a mut W { + self.variant(BLANK_A::START) + } + #[doc = "Blanking applied from rising edge of the output waveform"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(BLANK_A::RISE) + } + #[doc = "Blanking applied from falling edge of the output waveform"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(BLANK_A::FALL) + } + #[doc = "Blanking applied from each toggle of the output waveform"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(BLANK_A::BOTH) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 5)) | ((value as u32 & 0x03) << 5); + self.w + } +} +#[doc = "Field `RESTART` reader - Fault B Restart"] +pub struct RESTART_R(crate::FieldReader); +impl RESTART_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESTART_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESTART_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESTART` writer - Fault B Restart"] +pub struct RESTART_W<'a> { + w: &'a mut W, +} +impl<'a> RESTART_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Fault B Halt Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum HALT_A { + #[doc = "0: Halt action disabled"] + DISABLE = 0, + #[doc = "1: Hardware halt action"] + HW = 1, + #[doc = "2: Software halt action"] + SW = 2, + #[doc = "3: Non-recoverable fault"] + NR = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: HALT_A) -> Self { + variant as _ + } +} +#[doc = "Field `HALT` reader - Fault B Halt Mode"] +pub struct HALT_R(crate::FieldReader); +impl HALT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + HALT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> HALT_A { + match self.bits { + 0 => HALT_A::DISABLE, + 1 => HALT_A::HW, + 2 => HALT_A::SW, + 3 => HALT_A::NR, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == HALT_A::DISABLE + } + #[doc = "Checks if the value of the field is `HW`"] + #[inline(always)] + pub fn is_hw(&self) -> bool { + **self == HALT_A::HW + } + #[doc = "Checks if the value of the field is `SW`"] + #[inline(always)] + pub fn is_sw(&self) -> bool { + **self == HALT_A::SW + } + #[doc = "Checks if the value of the field is `NR`"] + #[inline(always)] + pub fn is_nr(&self) -> bool { + **self == HALT_A::NR + } +} +impl core::ops::Deref for HALT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HALT` writer - Fault B Halt Mode"] +pub struct HALT_W<'a> { + w: &'a mut W, +} +impl<'a> HALT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: HALT_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Halt action disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(HALT_A::DISABLE) + } + #[doc = "Hardware halt action"] + #[inline(always)] + pub fn hw(self) -> &'a mut W { + self.variant(HALT_A::HW) + } + #[doc = "Software halt action"] + #[inline(always)] + pub fn sw(self) -> &'a mut W { + self.variant(HALT_A::SW) + } + #[doc = "Non-recoverable fault"] + #[inline(always)] + pub fn nr(self) -> &'a mut W { + self.variant(HALT_A::NR) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 8)) | ((value as u32 & 0x03) << 8); + self.w + } +} +#[doc = "Fault B Capture Channel\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CHSEL_A { + #[doc = "0: Capture value stored in channel 0"] + CC0 = 0, + #[doc = "1: Capture value stored in channel 1"] + CC1 = 1, + #[doc = "2: Capture value stored in channel 2"] + CC2 = 2, + #[doc = "3: Capture value stored in channel 3"] + CC3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CHSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `CHSEL` reader - Fault B Capture Channel"] +pub struct CHSEL_R(crate::FieldReader); +impl CHSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CHSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CHSEL_A { + match self.bits { + 0 => CHSEL_A::CC0, + 1 => CHSEL_A::CC1, + 2 => CHSEL_A::CC2, + 3 => CHSEL_A::CC3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `CC0`"] + #[inline(always)] + pub fn is_cc0(&self) -> bool { + **self == CHSEL_A::CC0 + } + #[doc = "Checks if the value of the field is `CC1`"] + #[inline(always)] + pub fn is_cc1(&self) -> bool { + **self == CHSEL_A::CC1 + } + #[doc = "Checks if the value of the field is `CC2`"] + #[inline(always)] + pub fn is_cc2(&self) -> bool { + **self == CHSEL_A::CC2 + } + #[doc = "Checks if the value of the field is `CC3`"] + #[inline(always)] + pub fn is_cc3(&self) -> bool { + **self == CHSEL_A::CC3 + } +} +impl core::ops::Deref for CHSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHSEL` writer - Fault B Capture Channel"] +pub struct CHSEL_W<'a> { + w: &'a mut W, +} +impl<'a> CHSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CHSEL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Capture value stored in channel 0"] + #[inline(always)] + pub fn cc0(self) -> &'a mut W { + self.variant(CHSEL_A::CC0) + } + #[doc = "Capture value stored in channel 1"] + #[inline(always)] + pub fn cc1(self) -> &'a mut W { + self.variant(CHSEL_A::CC1) + } + #[doc = "Capture value stored in channel 2"] + #[inline(always)] + pub fn cc2(self) -> &'a mut W { + self.variant(CHSEL_A::CC2) + } + #[doc = "Capture value stored in channel 3"] + #[inline(always)] + pub fn cc3(self) -> &'a mut W { + self.variant(CHSEL_A::CC3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 10)) | ((value as u32 & 0x03) << 10); + self.w + } +} +#[doc = "Fault B Capture Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CAPTURE_A { + #[doc = "0: No capture"] + DISABLE = 0, + #[doc = "1: Capture on fault"] + CAPT = 1, + #[doc = "2: Minimum capture"] + CAPTMIN = 2, + #[doc = "3: Maximum capture"] + CAPTMAX = 3, + #[doc = "4: Minimum local detection"] + LOCMIN = 4, + #[doc = "5: Maximum local detection"] + LOCMAX = 5, + #[doc = "6: Minimum and maximum local detection"] + DERIV0 = 6, + #[doc = "7: Capture with ramp index as MSB value"] + CAPTMARK = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CAPTURE_A) -> Self { + variant as _ + } +} +#[doc = "Field `CAPTURE` reader - Fault B Capture Action"] +pub struct CAPTURE_R(crate::FieldReader); +impl CAPTURE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CAPTURE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CAPTURE_A { + match self.bits { + 0 => CAPTURE_A::DISABLE, + 1 => CAPTURE_A::CAPT, + 2 => CAPTURE_A::CAPTMIN, + 3 => CAPTURE_A::CAPTMAX, + 4 => CAPTURE_A::LOCMIN, + 5 => CAPTURE_A::LOCMAX, + 6 => CAPTURE_A::DERIV0, + 7 => CAPTURE_A::CAPTMARK, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == CAPTURE_A::DISABLE + } + #[doc = "Checks if the value of the field is `CAPT`"] + #[inline(always)] + pub fn is_capt(&self) -> bool { + **self == CAPTURE_A::CAPT + } + #[doc = "Checks if the value of the field is `CAPTMIN`"] + #[inline(always)] + pub fn is_captmin(&self) -> bool { + **self == CAPTURE_A::CAPTMIN + } + #[doc = "Checks if the value of the field is `CAPTMAX`"] + #[inline(always)] + pub fn is_captmax(&self) -> bool { + **self == CAPTURE_A::CAPTMAX + } + #[doc = "Checks if the value of the field is `LOCMIN`"] + #[inline(always)] + pub fn is_locmin(&self) -> bool { + **self == CAPTURE_A::LOCMIN + } + #[doc = "Checks if the value of the field is `LOCMAX`"] + #[inline(always)] + pub fn is_locmax(&self) -> bool { + **self == CAPTURE_A::LOCMAX + } + #[doc = "Checks if the value of the field is `DERIV0`"] + #[inline(always)] + pub fn is_deriv0(&self) -> bool { + **self == CAPTURE_A::DERIV0 + } + #[doc = "Checks if the value of the field is `CAPTMARK`"] + #[inline(always)] + pub fn is_captmark(&self) -> bool { + **self == CAPTURE_A::CAPTMARK + } +} +impl core::ops::Deref for CAPTURE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAPTURE` writer - Fault B Capture Action"] +pub struct CAPTURE_W<'a> { + w: &'a mut W, +} +impl<'a> CAPTURE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CAPTURE_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "No capture"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(CAPTURE_A::DISABLE) + } + #[doc = "Capture on fault"] + #[inline(always)] + pub fn capt(self) -> &'a mut W { + self.variant(CAPTURE_A::CAPT) + } + #[doc = "Minimum capture"] + #[inline(always)] + pub fn captmin(self) -> &'a mut W { + self.variant(CAPTURE_A::CAPTMIN) + } + #[doc = "Maximum capture"] + #[inline(always)] + pub fn captmax(self) -> &'a mut W { + self.variant(CAPTURE_A::CAPTMAX) + } + #[doc = "Minimum local detection"] + #[inline(always)] + pub fn locmin(self) -> &'a mut W { + self.variant(CAPTURE_A::LOCMIN) + } + #[doc = "Maximum local detection"] + #[inline(always)] + pub fn locmax(self) -> &'a mut W { + self.variant(CAPTURE_A::LOCMAX) + } + #[doc = "Minimum and maximum local detection"] + #[inline(always)] + pub fn deriv0(self) -> &'a mut W { + self.variant(CAPTURE_A::DERIV0) + } + #[doc = "Capture with ramp index as MSB value"] + #[inline(always)] + pub fn captmark(self) -> &'a mut W { + self.variant(CAPTURE_A::CAPTMARK) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 12)) | ((value as u32 & 0x07) << 12); + self.w + } +} +#[doc = "Field `BLANKPRESC` reader - Fault B Blanking Prescaler"] +pub struct BLANKPRESC_R(crate::FieldReader); +impl BLANKPRESC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BLANKPRESC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BLANKPRESC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BLANKPRESC` writer - Fault B Blanking Prescaler"] +pub struct BLANKPRESC_W<'a> { + w: &'a mut W, +} +impl<'a> BLANKPRESC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `BLANKVAL` reader - Fault B Blanking Time"] +pub struct BLANKVAL_R(crate::FieldReader); +impl BLANKVAL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BLANKVAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BLANKVAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BLANKVAL` writer - Fault B Blanking Time"] +pub struct BLANKVAL_W<'a> { + w: &'a mut W, +} +impl<'a> BLANKVAL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +#[doc = "Field `FILTERVAL` reader - Fault B Filter Value"] +pub struct FILTERVAL_R(crate::FieldReader); +impl FILTERVAL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FILTERVAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTERVAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTERVAL` writer - Fault B Filter Value"] +pub struct FILTERVAL_W<'a> { + w: &'a mut W, +} +impl<'a> FILTERVAL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Fault B Source"] + #[inline(always)] + pub fn src(&self) -> SRC_R { + SRC_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bit 3 - Fault B Keeper"] + #[inline(always)] + pub fn keep(&self) -> KEEP_R { + KEEP_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Fault B Qualification"] + #[inline(always)] + pub fn qual(&self) -> QUAL_R { + QUAL_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bits 5:6 - Fault B Blanking Mode"] + #[inline(always)] + pub fn blank(&self) -> BLANK_R { + BLANK_R::new(((self.bits >> 5) & 0x03) as u8) + } + #[doc = "Bit 7 - Fault B Restart"] + #[inline(always)] + pub fn restart(&self) -> RESTART_R { + RESTART_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:9 - Fault B Halt Mode"] + #[inline(always)] + pub fn halt(&self) -> HALT_R { + HALT_R::new(((self.bits >> 8) & 0x03) as u8) + } + #[doc = "Bits 10:11 - Fault B Capture Channel"] + #[inline(always)] + pub fn chsel(&self) -> CHSEL_R { + CHSEL_R::new(((self.bits >> 10) & 0x03) as u8) + } + #[doc = "Bits 12:14 - Fault B Capture Action"] + #[inline(always)] + pub fn capture(&self) -> CAPTURE_R { + CAPTURE_R::new(((self.bits >> 12) & 0x07) as u8) + } + #[doc = "Bit 15 - Fault B Blanking Prescaler"] + #[inline(always)] + pub fn blankpresc(&self) -> BLANKPRESC_R { + BLANKPRESC_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:23 - Fault B Blanking Time"] + #[inline(always)] + pub fn blankval(&self) -> BLANKVAL_R { + BLANKVAL_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:27 - Fault B Filter Value"] + #[inline(always)] + pub fn filterval(&self) -> FILTERVAL_R { + FILTERVAL_R::new(((self.bits >> 24) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Fault B Source"] + #[inline(always)] + pub fn src(&mut self) -> SRC_W { + SRC_W { w: self } + } + #[doc = "Bit 3 - Fault B Keeper"] + #[inline(always)] + pub fn keep(&mut self) -> KEEP_W { + KEEP_W { w: self } + } + #[doc = "Bit 4 - Fault B Qualification"] + #[inline(always)] + pub fn qual(&mut self) -> QUAL_W { + QUAL_W { w: self } + } + #[doc = "Bits 5:6 - Fault B Blanking Mode"] + #[inline(always)] + pub fn blank(&mut self) -> BLANK_W { + BLANK_W { w: self } + } + #[doc = "Bit 7 - Fault B Restart"] + #[inline(always)] + pub fn restart(&mut self) -> RESTART_W { + RESTART_W { w: self } + } + #[doc = "Bits 8:9 - Fault B Halt Mode"] + #[inline(always)] + pub fn halt(&mut self) -> HALT_W { + HALT_W { w: self } + } + #[doc = "Bits 10:11 - Fault B Capture Channel"] + #[inline(always)] + pub fn chsel(&mut self) -> CHSEL_W { + CHSEL_W { w: self } + } + #[doc = "Bits 12:14 - Fault B Capture Action"] + #[inline(always)] + pub fn capture(&mut self) -> CAPTURE_W { + CAPTURE_W { w: self } + } + #[doc = "Bit 15 - Fault B Blanking Prescaler"] + #[inline(always)] + pub fn blankpresc(&mut self) -> BLANKPRESC_W { + BLANKPRESC_W { w: self } + } + #[doc = "Bits 16:23 - Fault B Blanking Time"] + #[inline(always)] + pub fn blankval(&mut self) -> BLANKVAL_W { + BLANKVAL_W { w: self } + } + #[doc = "Bits 24:27 - Fault B Filter Value"] + #[inline(always)] + pub fn filterval(&mut self) -> FILTERVAL_W { + FILTERVAL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Recoverable Fault B Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fctrlb](index.html) module"] +pub struct FCTRLB_SPEC; +impl crate::RegisterSpec for FCTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [fctrlb::R](R) reader structure"] +impl crate::Readable for FCTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [fctrlb::W](W) writer structure"] +impl crate::Writable for FCTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets FCTRLB to value 0"] +impl crate::Resettable for FCTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/tcc0/intenclr.rs b/pac/atsamc20g/src/tcc0/intenclr.rs new file mode 100644 index 000000000000..a227a8405a3c --- /dev/null +++ b/pac/atsamc20g/src/tcc0/intenclr.rs @@ -0,0 +1,724 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `TRG` reader - Retrigger Interrupt Enable"] +pub struct TRG_R(crate::FieldReader); +impl TRG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRG` writer - Retrigger Interrupt Enable"] +pub struct TRG_W<'a> { + w: &'a mut W, +} +impl<'a> TRG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CNT` reader - Counter Interrupt Enable"] +pub struct CNT_R(crate::FieldReader); +impl CNT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CNT` writer - Counter Interrupt Enable"] +pub struct CNT_W<'a> { + w: &'a mut W, +} +impl<'a> CNT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `ERR` reader - Error Interrupt Enable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - Error Interrupt Enable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `UFS` reader - Non-Recoverable Update Fault Interrupt Enable"] +pub struct UFS_R(crate::FieldReader); +impl UFS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UFS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for UFS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `UFS` writer - Non-Recoverable Update Fault Interrupt Enable"] +pub struct UFS_W<'a> { + w: &'a mut W, +} +impl<'a> UFS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `DFS` reader - Non-Recoverable Debug Fault Interrupt Enable"] +pub struct DFS_R(crate::FieldReader); +impl DFS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFS` writer - Non-Recoverable Debug Fault Interrupt Enable"] +pub struct DFS_W<'a> { + w: &'a mut W, +} +impl<'a> DFS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `FAULTA` reader - Recoverable Fault A Interrupt Enable"] +pub struct FAULTA_R(crate::FieldReader); +impl FAULTA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTA` writer - Recoverable Fault A Interrupt Enable"] +pub struct FAULTA_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `FAULTB` reader - Recoverable Fault B Interrupt Enable"] +pub struct FAULTB_R(crate::FieldReader); +impl FAULTB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTB` writer - Recoverable Fault B Interrupt Enable"] +pub struct FAULTB_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `FAULT0` reader - Non-Recoverable Fault 0 Interrupt Enable"] +pub struct FAULT0_R(crate::FieldReader); +impl FAULT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT0` writer - Non-Recoverable Fault 0 Interrupt Enable"] +pub struct FAULT0_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `FAULT1` reader - Non-Recoverable Fault 1 Interrupt Enable"] +pub struct FAULT1_R(crate::FieldReader); +impl FAULT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT1` writer - Non-Recoverable Fault 1 Interrupt Enable"] +pub struct FAULT1_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `MC0` reader - Match or Capture Channel 0 Interrupt Enable"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - Match or Capture Channel 0 Interrupt Enable"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `MC1` reader - Match or Capture Channel 1 Interrupt Enable"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - Match or Capture Channel 1 Interrupt Enable"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `MC2` reader - Match or Capture Channel 2 Interrupt Enable"] +pub struct MC2_R(crate::FieldReader); +impl MC2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC2` writer - Match or Capture Channel 2 Interrupt Enable"] +pub struct MC2_W<'a> { + w: &'a mut W, +} +impl<'a> MC2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `MC3` reader - Match or Capture Channel 3 Interrupt Enable"] +pub struct MC3_R(crate::FieldReader); +impl MC3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC3` writer - Match or Capture Channel 3 Interrupt Enable"] +pub struct MC3_W<'a> { + w: &'a mut W, +} +impl<'a> MC3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +impl R { + #[doc = "Bit 0 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Retrigger Interrupt Enable"] + #[inline(always)] + pub fn trg(&self) -> TRG_R { + TRG_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Counter Interrupt Enable"] + #[inline(always)] + pub fn cnt(&self) -> CNT_R { + CNT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Error Interrupt Enable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 10 - Non-Recoverable Update Fault Interrupt Enable"] + #[inline(always)] + pub fn ufs(&self) -> UFS_R { + UFS_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Non-Recoverable Debug Fault Interrupt Enable"] + #[inline(always)] + pub fn dfs(&self) -> DFS_R { + DFS_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Recoverable Fault A Interrupt Enable"] + #[inline(always)] + pub fn faulta(&self) -> FAULTA_R { + FAULTA_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Recoverable Fault B Interrupt Enable"] + #[inline(always)] + pub fn faultb(&self) -> FAULTB_R { + FAULTB_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Non-Recoverable Fault 0 Interrupt Enable"] + #[inline(always)] + pub fn fault0(&self) -> FAULT0_R { + FAULT0_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Non-Recoverable Fault 1 Interrupt Enable"] + #[inline(always)] + pub fn fault1(&self) -> FAULT1_R { + FAULT1_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Match or Capture Channel 0 Interrupt Enable"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Match or Capture Channel 1 Interrupt Enable"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Match or Capture Channel 2 Interrupt Enable"] + #[inline(always)] + pub fn mc2(&self) -> MC2_R { + MC2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Match or Capture Channel 3 Interrupt Enable"] + #[inline(always)] + pub fn mc3(&self) -> MC3_R { + MC3_R::new(((self.bits >> 19) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - Retrigger Interrupt Enable"] + #[inline(always)] + pub fn trg(&mut self) -> TRG_W { + TRG_W { w: self } + } + #[doc = "Bit 2 - Counter Interrupt Enable"] + #[inline(always)] + pub fn cnt(&mut self) -> CNT_W { + CNT_W { w: self } + } + #[doc = "Bit 3 - Error Interrupt Enable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 10 - Non-Recoverable Update Fault Interrupt Enable"] + #[inline(always)] + pub fn ufs(&mut self) -> UFS_W { + UFS_W { w: self } + } + #[doc = "Bit 11 - Non-Recoverable Debug Fault Interrupt Enable"] + #[inline(always)] + pub fn dfs(&mut self) -> DFS_W { + DFS_W { w: self } + } + #[doc = "Bit 12 - Recoverable Fault A Interrupt Enable"] + #[inline(always)] + pub fn faulta(&mut self) -> FAULTA_W { + FAULTA_W { w: self } + } + #[doc = "Bit 13 - Recoverable Fault B Interrupt Enable"] + #[inline(always)] + pub fn faultb(&mut self) -> FAULTB_W { + FAULTB_W { w: self } + } + #[doc = "Bit 14 - Non-Recoverable Fault 0 Interrupt Enable"] + #[inline(always)] + pub fn fault0(&mut self) -> FAULT0_W { + FAULT0_W { w: self } + } + #[doc = "Bit 15 - Non-Recoverable Fault 1 Interrupt Enable"] + #[inline(always)] + pub fn fault1(&mut self) -> FAULT1_W { + FAULT1_W { w: self } + } + #[doc = "Bit 16 - Match or Capture Channel 0 Interrupt Enable"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 17 - Match or Capture Channel 1 Interrupt Enable"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Bit 18 - Match or Capture Channel 2 Interrupt Enable"] + #[inline(always)] + pub fn mc2(&mut self) -> MC2_W { + MC2_W { w: self } + } + #[doc = "Bit 19 - Match or Capture Channel 3 Interrupt Enable"] + #[inline(always)] + pub fn mc3(&mut self) -> MC3_W { + MC3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/tcc0/intenset.rs b/pac/atsamc20g/src/tcc0/intenset.rs new file mode 100644 index 000000000000..0125a220bd02 --- /dev/null +++ b/pac/atsamc20g/src/tcc0/intenset.rs @@ -0,0 +1,724 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `TRG` reader - Retrigger Interrupt Enable"] +pub struct TRG_R(crate::FieldReader); +impl TRG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRG` writer - Retrigger Interrupt Enable"] +pub struct TRG_W<'a> { + w: &'a mut W, +} +impl<'a> TRG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CNT` reader - Counter Interrupt Enable"] +pub struct CNT_R(crate::FieldReader); +impl CNT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CNT` writer - Counter Interrupt Enable"] +pub struct CNT_W<'a> { + w: &'a mut W, +} +impl<'a> CNT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `ERR` reader - Error Interrupt Enable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - Error Interrupt Enable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `UFS` reader - Non-Recoverable Update Fault Interrupt Enable"] +pub struct UFS_R(crate::FieldReader); +impl UFS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UFS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for UFS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `UFS` writer - Non-Recoverable Update Fault Interrupt Enable"] +pub struct UFS_W<'a> { + w: &'a mut W, +} +impl<'a> UFS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `DFS` reader - Non-Recoverable Debug Fault Interrupt Enable"] +pub struct DFS_R(crate::FieldReader); +impl DFS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFS` writer - Non-Recoverable Debug Fault Interrupt Enable"] +pub struct DFS_W<'a> { + w: &'a mut W, +} +impl<'a> DFS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `FAULTA` reader - Recoverable Fault A Interrupt Enable"] +pub struct FAULTA_R(crate::FieldReader); +impl FAULTA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTA` writer - Recoverable Fault A Interrupt Enable"] +pub struct FAULTA_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `FAULTB` reader - Recoverable Fault B Interrupt Enable"] +pub struct FAULTB_R(crate::FieldReader); +impl FAULTB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTB` writer - Recoverable Fault B Interrupt Enable"] +pub struct FAULTB_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `FAULT0` reader - Non-Recoverable Fault 0 Interrupt Enable"] +pub struct FAULT0_R(crate::FieldReader); +impl FAULT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT0` writer - Non-Recoverable Fault 0 Interrupt Enable"] +pub struct FAULT0_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `FAULT1` reader - Non-Recoverable Fault 1 Interrupt Enable"] +pub struct FAULT1_R(crate::FieldReader); +impl FAULT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT1` writer - Non-Recoverable Fault 1 Interrupt Enable"] +pub struct FAULT1_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `MC0` reader - Match or Capture Channel 0 Interrupt Enable"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - Match or Capture Channel 0 Interrupt Enable"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `MC1` reader - Match or Capture Channel 1 Interrupt Enable"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - Match or Capture Channel 1 Interrupt Enable"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `MC2` reader - Match or Capture Channel 2 Interrupt Enable"] +pub struct MC2_R(crate::FieldReader); +impl MC2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC2` writer - Match or Capture Channel 2 Interrupt Enable"] +pub struct MC2_W<'a> { + w: &'a mut W, +} +impl<'a> MC2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `MC3` reader - Match or Capture Channel 3 Interrupt Enable"] +pub struct MC3_R(crate::FieldReader); +impl MC3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC3` writer - Match or Capture Channel 3 Interrupt Enable"] +pub struct MC3_W<'a> { + w: &'a mut W, +} +impl<'a> MC3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +impl R { + #[doc = "Bit 0 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Retrigger Interrupt Enable"] + #[inline(always)] + pub fn trg(&self) -> TRG_R { + TRG_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Counter Interrupt Enable"] + #[inline(always)] + pub fn cnt(&self) -> CNT_R { + CNT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Error Interrupt Enable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 10 - Non-Recoverable Update Fault Interrupt Enable"] + #[inline(always)] + pub fn ufs(&self) -> UFS_R { + UFS_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Non-Recoverable Debug Fault Interrupt Enable"] + #[inline(always)] + pub fn dfs(&self) -> DFS_R { + DFS_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Recoverable Fault A Interrupt Enable"] + #[inline(always)] + pub fn faulta(&self) -> FAULTA_R { + FAULTA_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Recoverable Fault B Interrupt Enable"] + #[inline(always)] + pub fn faultb(&self) -> FAULTB_R { + FAULTB_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Non-Recoverable Fault 0 Interrupt Enable"] + #[inline(always)] + pub fn fault0(&self) -> FAULT0_R { + FAULT0_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Non-Recoverable Fault 1 Interrupt Enable"] + #[inline(always)] + pub fn fault1(&self) -> FAULT1_R { + FAULT1_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Match or Capture Channel 0 Interrupt Enable"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Match or Capture Channel 1 Interrupt Enable"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Match or Capture Channel 2 Interrupt Enable"] + #[inline(always)] + pub fn mc2(&self) -> MC2_R { + MC2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Match or Capture Channel 3 Interrupt Enable"] + #[inline(always)] + pub fn mc3(&self) -> MC3_R { + MC3_R::new(((self.bits >> 19) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - Retrigger Interrupt Enable"] + #[inline(always)] + pub fn trg(&mut self) -> TRG_W { + TRG_W { w: self } + } + #[doc = "Bit 2 - Counter Interrupt Enable"] + #[inline(always)] + pub fn cnt(&mut self) -> CNT_W { + CNT_W { w: self } + } + #[doc = "Bit 3 - Error Interrupt Enable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 10 - Non-Recoverable Update Fault Interrupt Enable"] + #[inline(always)] + pub fn ufs(&mut self) -> UFS_W { + UFS_W { w: self } + } + #[doc = "Bit 11 - Non-Recoverable Debug Fault Interrupt Enable"] + #[inline(always)] + pub fn dfs(&mut self) -> DFS_W { + DFS_W { w: self } + } + #[doc = "Bit 12 - Recoverable Fault A Interrupt Enable"] + #[inline(always)] + pub fn faulta(&mut self) -> FAULTA_W { + FAULTA_W { w: self } + } + #[doc = "Bit 13 - Recoverable Fault B Interrupt Enable"] + #[inline(always)] + pub fn faultb(&mut self) -> FAULTB_W { + FAULTB_W { w: self } + } + #[doc = "Bit 14 - Non-Recoverable Fault 0 Interrupt Enable"] + #[inline(always)] + pub fn fault0(&mut self) -> FAULT0_W { + FAULT0_W { w: self } + } + #[doc = "Bit 15 - Non-Recoverable Fault 1 Interrupt Enable"] + #[inline(always)] + pub fn fault1(&mut self) -> FAULT1_W { + FAULT1_W { w: self } + } + #[doc = "Bit 16 - Match or Capture Channel 0 Interrupt Enable"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 17 - Match or Capture Channel 1 Interrupt Enable"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Bit 18 - Match or Capture Channel 2 Interrupt Enable"] + #[inline(always)] + pub fn mc2(&mut self) -> MC2_W { + MC2_W { w: self } + } + #[doc = "Bit 19 - Match or Capture Channel 3 Interrupt Enable"] + #[inline(always)] + pub fn mc3(&mut self) -> MC3_W { + MC3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/tcc0/intflag.rs b/pac/atsamc20g/src/tcc0/intflag.rs new file mode 100644 index 000000000000..b2d5088f4087 --- /dev/null +++ b/pac/atsamc20g/src/tcc0/intflag.rs @@ -0,0 +1,724 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - Overflow"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `TRG` reader - Retrigger"] +pub struct TRG_R(crate::FieldReader); +impl TRG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRG` writer - Retrigger"] +pub struct TRG_W<'a> { + w: &'a mut W, +} +impl<'a> TRG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CNT` reader - Counter"] +pub struct CNT_R(crate::FieldReader); +impl CNT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CNT` writer - Counter"] +pub struct CNT_W<'a> { + w: &'a mut W, +} +impl<'a> CNT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `ERR` reader - Error"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - Error"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `UFS` reader - Non-Recoverable Update Fault"] +pub struct UFS_R(crate::FieldReader); +impl UFS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UFS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for UFS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `UFS` writer - Non-Recoverable Update Fault"] +pub struct UFS_W<'a> { + w: &'a mut W, +} +impl<'a> UFS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `DFS` reader - Non-Recoverable Debug Fault"] +pub struct DFS_R(crate::FieldReader); +impl DFS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFS` writer - Non-Recoverable Debug Fault"] +pub struct DFS_W<'a> { + w: &'a mut W, +} +impl<'a> DFS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `FAULTA` reader - Recoverable Fault A"] +pub struct FAULTA_R(crate::FieldReader); +impl FAULTA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTA` writer - Recoverable Fault A"] +pub struct FAULTA_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `FAULTB` reader - Recoverable Fault B"] +pub struct FAULTB_R(crate::FieldReader); +impl FAULTB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTB` writer - Recoverable Fault B"] +pub struct FAULTB_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `FAULT0` reader - Non-Recoverable Fault 0"] +pub struct FAULT0_R(crate::FieldReader); +impl FAULT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT0` writer - Non-Recoverable Fault 0"] +pub struct FAULT0_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `FAULT1` reader - Non-Recoverable Fault 1"] +pub struct FAULT1_R(crate::FieldReader); +impl FAULT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT1` writer - Non-Recoverable Fault 1"] +pub struct FAULT1_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `MC0` reader - Match or Capture 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - Match or Capture 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `MC1` reader - Match or Capture 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - Match or Capture 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `MC2` reader - Match or Capture 2"] +pub struct MC2_R(crate::FieldReader); +impl MC2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC2` writer - Match or Capture 2"] +pub struct MC2_W<'a> { + w: &'a mut W, +} +impl<'a> MC2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `MC3` reader - Match or Capture 3"] +pub struct MC3_R(crate::FieldReader); +impl MC3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC3` writer - Match or Capture 3"] +pub struct MC3_W<'a> { + w: &'a mut W, +} +impl<'a> MC3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +impl R { + #[doc = "Bit 0 - Overflow"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Retrigger"] + #[inline(always)] + pub fn trg(&self) -> TRG_R { + TRG_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Counter"] + #[inline(always)] + pub fn cnt(&self) -> CNT_R { + CNT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Error"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 10 - Non-Recoverable Update Fault"] + #[inline(always)] + pub fn ufs(&self) -> UFS_R { + UFS_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Non-Recoverable Debug Fault"] + #[inline(always)] + pub fn dfs(&self) -> DFS_R { + DFS_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Recoverable Fault A"] + #[inline(always)] + pub fn faulta(&self) -> FAULTA_R { + FAULTA_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Recoverable Fault B"] + #[inline(always)] + pub fn faultb(&self) -> FAULTB_R { + FAULTB_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Non-Recoverable Fault 0"] + #[inline(always)] + pub fn fault0(&self) -> FAULT0_R { + FAULT0_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Non-Recoverable Fault 1"] + #[inline(always)] + pub fn fault1(&self) -> FAULT1_R { + FAULT1_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Match or Capture 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Match or Capture 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Match or Capture 2"] + #[inline(always)] + pub fn mc2(&self) -> MC2_R { + MC2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Match or Capture 3"] + #[inline(always)] + pub fn mc3(&self) -> MC3_R { + MC3_R::new(((self.bits >> 19) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Overflow"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - Retrigger"] + #[inline(always)] + pub fn trg(&mut self) -> TRG_W { + TRG_W { w: self } + } + #[doc = "Bit 2 - Counter"] + #[inline(always)] + pub fn cnt(&mut self) -> CNT_W { + CNT_W { w: self } + } + #[doc = "Bit 3 - Error"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 10 - Non-Recoverable Update Fault"] + #[inline(always)] + pub fn ufs(&mut self) -> UFS_W { + UFS_W { w: self } + } + #[doc = "Bit 11 - Non-Recoverable Debug Fault"] + #[inline(always)] + pub fn dfs(&mut self) -> DFS_W { + DFS_W { w: self } + } + #[doc = "Bit 12 - Recoverable Fault A"] + #[inline(always)] + pub fn faulta(&mut self) -> FAULTA_W { + FAULTA_W { w: self } + } + #[doc = "Bit 13 - Recoverable Fault B"] + #[inline(always)] + pub fn faultb(&mut self) -> FAULTB_W { + FAULTB_W { w: self } + } + #[doc = "Bit 14 - Non-Recoverable Fault 0"] + #[inline(always)] + pub fn fault0(&mut self) -> FAULT0_W { + FAULT0_W { w: self } + } + #[doc = "Bit 15 - Non-Recoverable Fault 1"] + #[inline(always)] + pub fn fault1(&mut self) -> FAULT1_W { + FAULT1_W { w: self } + } + #[doc = "Bit 16 - Match or Capture 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 17 - Match or Capture 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Bit 18 - Match or Capture 2"] + #[inline(always)] + pub fn mc2(&mut self) -> MC2_W { + MC2_W { w: self } + } + #[doc = "Bit 19 - Match or Capture 3"] + #[inline(always)] + pub fn mc3(&mut self) -> MC3_W { + MC3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/tcc0/patt.rs b/pac/atsamc20g/src/tcc0/patt.rs new file mode 100644 index 000000000000..ea458642b182 --- /dev/null +++ b/pac/atsamc20g/src/tcc0/patt.rs @@ -0,0 +1,818 @@ +#[doc = "Register `PATT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PATT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PGE0` reader - Pattern Generator 0 Output Enable"] +pub struct PGE0_R(crate::FieldReader); +impl PGE0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGE0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGE0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGE0` writer - Pattern Generator 0 Output Enable"] +pub struct PGE0_W<'a> { + w: &'a mut W, +} +impl<'a> PGE0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PGE1` reader - Pattern Generator 1 Output Enable"] +pub struct PGE1_R(crate::FieldReader); +impl PGE1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGE1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGE1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGE1` writer - Pattern Generator 1 Output Enable"] +pub struct PGE1_W<'a> { + w: &'a mut W, +} +impl<'a> PGE1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PGE2` reader - Pattern Generator 2 Output Enable"] +pub struct PGE2_R(crate::FieldReader); +impl PGE2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGE2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGE2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGE2` writer - Pattern Generator 2 Output Enable"] +pub struct PGE2_W<'a> { + w: &'a mut W, +} +impl<'a> PGE2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PGE3` reader - Pattern Generator 3 Output Enable"] +pub struct PGE3_R(crate::FieldReader); +impl PGE3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGE3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGE3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGE3` writer - Pattern Generator 3 Output Enable"] +pub struct PGE3_W<'a> { + w: &'a mut W, +} +impl<'a> PGE3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PGE4` reader - Pattern Generator 4 Output Enable"] +pub struct PGE4_R(crate::FieldReader); +impl PGE4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGE4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGE4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGE4` writer - Pattern Generator 4 Output Enable"] +pub struct PGE4_W<'a> { + w: &'a mut W, +} +impl<'a> PGE4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PGE5` reader - Pattern Generator 5 Output Enable"] +pub struct PGE5_R(crate::FieldReader); +impl PGE5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGE5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGE5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGE5` writer - Pattern Generator 5 Output Enable"] +pub struct PGE5_W<'a> { + w: &'a mut W, +} +impl<'a> PGE5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PGE6` reader - Pattern Generator 6 Output Enable"] +pub struct PGE6_R(crate::FieldReader); +impl PGE6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGE6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGE6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGE6` writer - Pattern Generator 6 Output Enable"] +pub struct PGE6_W<'a> { + w: &'a mut W, +} +impl<'a> PGE6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PGE7` reader - Pattern Generator 7 Output Enable"] +pub struct PGE7_R(crate::FieldReader); +impl PGE7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGE7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGE7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGE7` writer - Pattern Generator 7 Output Enable"] +pub struct PGE7_W<'a> { + w: &'a mut W, +} +impl<'a> PGE7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `PGV0` reader - Pattern Generator 0 Output Value"] +pub struct PGV0_R(crate::FieldReader); +impl PGV0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGV0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGV0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGV0` writer - Pattern Generator 0 Output Value"] +pub struct PGV0_W<'a> { + w: &'a mut W, +} +impl<'a> PGV0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `PGV1` reader - Pattern Generator 1 Output Value"] +pub struct PGV1_R(crate::FieldReader); +impl PGV1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGV1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGV1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGV1` writer - Pattern Generator 1 Output Value"] +pub struct PGV1_W<'a> { + w: &'a mut W, +} +impl<'a> PGV1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `PGV2` reader - Pattern Generator 2 Output Value"] +pub struct PGV2_R(crate::FieldReader); +impl PGV2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGV2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGV2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGV2` writer - Pattern Generator 2 Output Value"] +pub struct PGV2_W<'a> { + w: &'a mut W, +} +impl<'a> PGV2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u16 & 0x01) << 10); + self.w + } +} +#[doc = "Field `PGV3` reader - Pattern Generator 3 Output Value"] +pub struct PGV3_R(crate::FieldReader); +impl PGV3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGV3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGV3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGV3` writer - Pattern Generator 3 Output Value"] +pub struct PGV3_W<'a> { + w: &'a mut W, +} +impl<'a> PGV3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u16 & 0x01) << 11); + self.w + } +} +#[doc = "Field `PGV4` reader - Pattern Generator 4 Output Value"] +pub struct PGV4_R(crate::FieldReader); +impl PGV4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGV4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGV4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGV4` writer - Pattern Generator 4 Output Value"] +pub struct PGV4_W<'a> { + w: &'a mut W, +} +impl<'a> PGV4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u16 & 0x01) << 12); + self.w + } +} +#[doc = "Field `PGV5` reader - Pattern Generator 5 Output Value"] +pub struct PGV5_R(crate::FieldReader); +impl PGV5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGV5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGV5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGV5` writer - Pattern Generator 5 Output Value"] +pub struct PGV5_W<'a> { + w: &'a mut W, +} +impl<'a> PGV5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u16 & 0x01) << 13); + self.w + } +} +#[doc = "Field `PGV6` reader - Pattern Generator 6 Output Value"] +pub struct PGV6_R(crate::FieldReader); +impl PGV6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGV6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGV6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGV6` writer - Pattern Generator 6 Output Value"] +pub struct PGV6_W<'a> { + w: &'a mut W, +} +impl<'a> PGV6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u16 & 0x01) << 14); + self.w + } +} +#[doc = "Field `PGV7` reader - Pattern Generator 7 Output Value"] +pub struct PGV7_R(crate::FieldReader); +impl PGV7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGV7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGV7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGV7` writer - Pattern Generator 7 Output Value"] +pub struct PGV7_W<'a> { + w: &'a mut W, +} +impl<'a> PGV7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Pattern Generator 0 Output Enable"] + #[inline(always)] + pub fn pge0(&self) -> PGE0_R { + PGE0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Pattern Generator 1 Output Enable"] + #[inline(always)] + pub fn pge1(&self) -> PGE1_R { + PGE1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Pattern Generator 2 Output Enable"] + #[inline(always)] + pub fn pge2(&self) -> PGE2_R { + PGE2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Pattern Generator 3 Output Enable"] + #[inline(always)] + pub fn pge3(&self) -> PGE3_R { + PGE3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Pattern Generator 4 Output Enable"] + #[inline(always)] + pub fn pge4(&self) -> PGE4_R { + PGE4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Pattern Generator 5 Output Enable"] + #[inline(always)] + pub fn pge5(&self) -> PGE5_R { + PGE5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Pattern Generator 6 Output Enable"] + #[inline(always)] + pub fn pge6(&self) -> PGE6_R { + PGE6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Pattern Generator 7 Output Enable"] + #[inline(always)] + pub fn pge7(&self) -> PGE7_R { + PGE7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Pattern Generator 0 Output Value"] + #[inline(always)] + pub fn pgv0(&self) -> PGV0_R { + PGV0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Pattern Generator 1 Output Value"] + #[inline(always)] + pub fn pgv1(&self) -> PGV1_R { + PGV1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Pattern Generator 2 Output Value"] + #[inline(always)] + pub fn pgv2(&self) -> PGV2_R { + PGV2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Pattern Generator 3 Output Value"] + #[inline(always)] + pub fn pgv3(&self) -> PGV3_R { + PGV3_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Pattern Generator 4 Output Value"] + #[inline(always)] + pub fn pgv4(&self) -> PGV4_R { + PGV4_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Pattern Generator 5 Output Value"] + #[inline(always)] + pub fn pgv5(&self) -> PGV5_R { + PGV5_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Pattern Generator 6 Output Value"] + #[inline(always)] + pub fn pgv6(&self) -> PGV6_R { + PGV6_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Pattern Generator 7 Output Value"] + #[inline(always)] + pub fn pgv7(&self) -> PGV7_R { + PGV7_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pattern Generator 0 Output Enable"] + #[inline(always)] + pub fn pge0(&mut self) -> PGE0_W { + PGE0_W { w: self } + } + #[doc = "Bit 1 - Pattern Generator 1 Output Enable"] + #[inline(always)] + pub fn pge1(&mut self) -> PGE1_W { + PGE1_W { w: self } + } + #[doc = "Bit 2 - Pattern Generator 2 Output Enable"] + #[inline(always)] + pub fn pge2(&mut self) -> PGE2_W { + PGE2_W { w: self } + } + #[doc = "Bit 3 - Pattern Generator 3 Output Enable"] + #[inline(always)] + pub fn pge3(&mut self) -> PGE3_W { + PGE3_W { w: self } + } + #[doc = "Bit 4 - Pattern Generator 4 Output Enable"] + #[inline(always)] + pub fn pge4(&mut self) -> PGE4_W { + PGE4_W { w: self } + } + #[doc = "Bit 5 - Pattern Generator 5 Output Enable"] + #[inline(always)] + pub fn pge5(&mut self) -> PGE5_W { + PGE5_W { w: self } + } + #[doc = "Bit 6 - Pattern Generator 6 Output Enable"] + #[inline(always)] + pub fn pge6(&mut self) -> PGE6_W { + PGE6_W { w: self } + } + #[doc = "Bit 7 - Pattern Generator 7 Output Enable"] + #[inline(always)] + pub fn pge7(&mut self) -> PGE7_W { + PGE7_W { w: self } + } + #[doc = "Bit 8 - Pattern Generator 0 Output Value"] + #[inline(always)] + pub fn pgv0(&mut self) -> PGV0_W { + PGV0_W { w: self } + } + #[doc = "Bit 9 - Pattern Generator 1 Output Value"] + #[inline(always)] + pub fn pgv1(&mut self) -> PGV1_W { + PGV1_W { w: self } + } + #[doc = "Bit 10 - Pattern Generator 2 Output Value"] + #[inline(always)] + pub fn pgv2(&mut self) -> PGV2_W { + PGV2_W { w: self } + } + #[doc = "Bit 11 - Pattern Generator 3 Output Value"] + #[inline(always)] + pub fn pgv3(&mut self) -> PGV3_W { + PGV3_W { w: self } + } + #[doc = "Bit 12 - Pattern Generator 4 Output Value"] + #[inline(always)] + pub fn pgv4(&mut self) -> PGV4_W { + PGV4_W { w: self } + } + #[doc = "Bit 13 - Pattern Generator 5 Output Value"] + #[inline(always)] + pub fn pgv5(&mut self) -> PGV5_W { + PGV5_W { w: self } + } + #[doc = "Bit 14 - Pattern Generator 6 Output Value"] + #[inline(always)] + pub fn pgv6(&mut self) -> PGV6_W { + PGV6_W { w: self } + } + #[doc = "Bit 15 - Pattern Generator 7 Output Value"] + #[inline(always)] + pub fn pgv7(&mut self) -> PGV7_W { + PGV7_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Pattern\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [patt](index.html) module"] +pub struct PATT_SPEC; +impl crate::RegisterSpec for PATT_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [patt::R](R) reader structure"] +impl crate::Readable for PATT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [patt::W](W) writer structure"] +impl crate::Writable for PATT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PATT to value 0"] +impl crate::Resettable for PATT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/tcc0/pattbuf.rs b/pac/atsamc20g/src/tcc0/pattbuf.rs new file mode 100644 index 000000000000..c9375e27645c --- /dev/null +++ b/pac/atsamc20g/src/tcc0/pattbuf.rs @@ -0,0 +1,818 @@ +#[doc = "Register `PATTBUF` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PATTBUF` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PGEB0` reader - Pattern Generator 0 Output Enable Buffer"] +pub struct PGEB0_R(crate::FieldReader); +impl PGEB0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGEB0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGEB0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGEB0` writer - Pattern Generator 0 Output Enable Buffer"] +pub struct PGEB0_W<'a> { + w: &'a mut W, +} +impl<'a> PGEB0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PGEB1` reader - Pattern Generator 1 Output Enable Buffer"] +pub struct PGEB1_R(crate::FieldReader); +impl PGEB1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGEB1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGEB1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGEB1` writer - Pattern Generator 1 Output Enable Buffer"] +pub struct PGEB1_W<'a> { + w: &'a mut W, +} +impl<'a> PGEB1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PGEB2` reader - Pattern Generator 2 Output Enable Buffer"] +pub struct PGEB2_R(crate::FieldReader); +impl PGEB2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGEB2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGEB2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGEB2` writer - Pattern Generator 2 Output Enable Buffer"] +pub struct PGEB2_W<'a> { + w: &'a mut W, +} +impl<'a> PGEB2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PGEB3` reader - Pattern Generator 3 Output Enable Buffer"] +pub struct PGEB3_R(crate::FieldReader); +impl PGEB3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGEB3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGEB3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGEB3` writer - Pattern Generator 3 Output Enable Buffer"] +pub struct PGEB3_W<'a> { + w: &'a mut W, +} +impl<'a> PGEB3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PGEB4` reader - Pattern Generator 4 Output Enable Buffer"] +pub struct PGEB4_R(crate::FieldReader); +impl PGEB4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGEB4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGEB4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGEB4` writer - Pattern Generator 4 Output Enable Buffer"] +pub struct PGEB4_W<'a> { + w: &'a mut W, +} +impl<'a> PGEB4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PGEB5` reader - Pattern Generator 5 Output Enable Buffer"] +pub struct PGEB5_R(crate::FieldReader); +impl PGEB5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGEB5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGEB5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGEB5` writer - Pattern Generator 5 Output Enable Buffer"] +pub struct PGEB5_W<'a> { + w: &'a mut W, +} +impl<'a> PGEB5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PGEB6` reader - Pattern Generator 6 Output Enable Buffer"] +pub struct PGEB6_R(crate::FieldReader); +impl PGEB6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGEB6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGEB6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGEB6` writer - Pattern Generator 6 Output Enable Buffer"] +pub struct PGEB6_W<'a> { + w: &'a mut W, +} +impl<'a> PGEB6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PGEB7` reader - Pattern Generator 7 Output Enable Buffer"] +pub struct PGEB7_R(crate::FieldReader); +impl PGEB7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGEB7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGEB7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGEB7` writer - Pattern Generator 7 Output Enable Buffer"] +pub struct PGEB7_W<'a> { + w: &'a mut W, +} +impl<'a> PGEB7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `PGVB0` reader - Pattern Generator 0 Output Enable"] +pub struct PGVB0_R(crate::FieldReader); +impl PGVB0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGVB0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGVB0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGVB0` writer - Pattern Generator 0 Output Enable"] +pub struct PGVB0_W<'a> { + w: &'a mut W, +} +impl<'a> PGVB0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `PGVB1` reader - Pattern Generator 1 Output Enable"] +pub struct PGVB1_R(crate::FieldReader); +impl PGVB1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGVB1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGVB1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGVB1` writer - Pattern Generator 1 Output Enable"] +pub struct PGVB1_W<'a> { + w: &'a mut W, +} +impl<'a> PGVB1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `PGVB2` reader - Pattern Generator 2 Output Enable"] +pub struct PGVB2_R(crate::FieldReader); +impl PGVB2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGVB2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGVB2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGVB2` writer - Pattern Generator 2 Output Enable"] +pub struct PGVB2_W<'a> { + w: &'a mut W, +} +impl<'a> PGVB2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u16 & 0x01) << 10); + self.w + } +} +#[doc = "Field `PGVB3` reader - Pattern Generator 3 Output Enable"] +pub struct PGVB3_R(crate::FieldReader); +impl PGVB3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGVB3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGVB3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGVB3` writer - Pattern Generator 3 Output Enable"] +pub struct PGVB3_W<'a> { + w: &'a mut W, +} +impl<'a> PGVB3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u16 & 0x01) << 11); + self.w + } +} +#[doc = "Field `PGVB4` reader - Pattern Generator 4 Output Enable"] +pub struct PGVB4_R(crate::FieldReader); +impl PGVB4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGVB4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGVB4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGVB4` writer - Pattern Generator 4 Output Enable"] +pub struct PGVB4_W<'a> { + w: &'a mut W, +} +impl<'a> PGVB4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u16 & 0x01) << 12); + self.w + } +} +#[doc = "Field `PGVB5` reader - Pattern Generator 5 Output Enable"] +pub struct PGVB5_R(crate::FieldReader); +impl PGVB5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGVB5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGVB5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGVB5` writer - Pattern Generator 5 Output Enable"] +pub struct PGVB5_W<'a> { + w: &'a mut W, +} +impl<'a> PGVB5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u16 & 0x01) << 13); + self.w + } +} +#[doc = "Field `PGVB6` reader - Pattern Generator 6 Output Enable"] +pub struct PGVB6_R(crate::FieldReader); +impl PGVB6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGVB6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGVB6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGVB6` writer - Pattern Generator 6 Output Enable"] +pub struct PGVB6_W<'a> { + w: &'a mut W, +} +impl<'a> PGVB6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u16 & 0x01) << 14); + self.w + } +} +#[doc = "Field `PGVB7` reader - Pattern Generator 7 Output Enable"] +pub struct PGVB7_R(crate::FieldReader); +impl PGVB7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGVB7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGVB7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGVB7` writer - Pattern Generator 7 Output Enable"] +pub struct PGVB7_W<'a> { + w: &'a mut W, +} +impl<'a> PGVB7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Pattern Generator 0 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb0(&self) -> PGEB0_R { + PGEB0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Pattern Generator 1 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb1(&self) -> PGEB1_R { + PGEB1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Pattern Generator 2 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb2(&self) -> PGEB2_R { + PGEB2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Pattern Generator 3 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb3(&self) -> PGEB3_R { + PGEB3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Pattern Generator 4 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb4(&self) -> PGEB4_R { + PGEB4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Pattern Generator 5 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb5(&self) -> PGEB5_R { + PGEB5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Pattern Generator 6 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb6(&self) -> PGEB6_R { + PGEB6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Pattern Generator 7 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb7(&self) -> PGEB7_R { + PGEB7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Pattern Generator 0 Output Enable"] + #[inline(always)] + pub fn pgvb0(&self) -> PGVB0_R { + PGVB0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Pattern Generator 1 Output Enable"] + #[inline(always)] + pub fn pgvb1(&self) -> PGVB1_R { + PGVB1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Pattern Generator 2 Output Enable"] + #[inline(always)] + pub fn pgvb2(&self) -> PGVB2_R { + PGVB2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Pattern Generator 3 Output Enable"] + #[inline(always)] + pub fn pgvb3(&self) -> PGVB3_R { + PGVB3_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Pattern Generator 4 Output Enable"] + #[inline(always)] + pub fn pgvb4(&self) -> PGVB4_R { + PGVB4_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Pattern Generator 5 Output Enable"] + #[inline(always)] + pub fn pgvb5(&self) -> PGVB5_R { + PGVB5_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Pattern Generator 6 Output Enable"] + #[inline(always)] + pub fn pgvb6(&self) -> PGVB6_R { + PGVB6_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Pattern Generator 7 Output Enable"] + #[inline(always)] + pub fn pgvb7(&self) -> PGVB7_R { + PGVB7_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pattern Generator 0 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb0(&mut self) -> PGEB0_W { + PGEB0_W { w: self } + } + #[doc = "Bit 1 - Pattern Generator 1 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb1(&mut self) -> PGEB1_W { + PGEB1_W { w: self } + } + #[doc = "Bit 2 - Pattern Generator 2 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb2(&mut self) -> PGEB2_W { + PGEB2_W { w: self } + } + #[doc = "Bit 3 - Pattern Generator 3 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb3(&mut self) -> PGEB3_W { + PGEB3_W { w: self } + } + #[doc = "Bit 4 - Pattern Generator 4 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb4(&mut self) -> PGEB4_W { + PGEB4_W { w: self } + } + #[doc = "Bit 5 - Pattern Generator 5 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb5(&mut self) -> PGEB5_W { + PGEB5_W { w: self } + } + #[doc = "Bit 6 - Pattern Generator 6 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb6(&mut self) -> PGEB6_W { + PGEB6_W { w: self } + } + #[doc = "Bit 7 - Pattern Generator 7 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb7(&mut self) -> PGEB7_W { + PGEB7_W { w: self } + } + #[doc = "Bit 8 - Pattern Generator 0 Output Enable"] + #[inline(always)] + pub fn pgvb0(&mut self) -> PGVB0_W { + PGVB0_W { w: self } + } + #[doc = "Bit 9 - Pattern Generator 1 Output Enable"] + #[inline(always)] + pub fn pgvb1(&mut self) -> PGVB1_W { + PGVB1_W { w: self } + } + #[doc = "Bit 10 - Pattern Generator 2 Output Enable"] + #[inline(always)] + pub fn pgvb2(&mut self) -> PGVB2_W { + PGVB2_W { w: self } + } + #[doc = "Bit 11 - Pattern Generator 3 Output Enable"] + #[inline(always)] + pub fn pgvb3(&mut self) -> PGVB3_W { + PGVB3_W { w: self } + } + #[doc = "Bit 12 - Pattern Generator 4 Output Enable"] + #[inline(always)] + pub fn pgvb4(&mut self) -> PGVB4_W { + PGVB4_W { w: self } + } + #[doc = "Bit 13 - Pattern Generator 5 Output Enable"] + #[inline(always)] + pub fn pgvb5(&mut self) -> PGVB5_W { + PGVB5_W { w: self } + } + #[doc = "Bit 14 - Pattern Generator 6 Output Enable"] + #[inline(always)] + pub fn pgvb6(&mut self) -> PGVB6_W { + PGVB6_W { w: self } + } + #[doc = "Bit 15 - Pattern Generator 7 Output Enable"] + #[inline(always)] + pub fn pgvb7(&mut self) -> PGVB7_W { + PGVB7_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Pattern Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pattbuf](index.html) module"] +pub struct PATTBUF_SPEC; +impl crate::RegisterSpec for PATTBUF_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [pattbuf::R](R) reader structure"] +impl crate::Readable for PATTBUF_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [pattbuf::W](W) writer structure"] +impl crate::Writable for PATTBUF_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PATTBUF to value 0"] +impl crate::Resettable for PATTBUF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/tcc0/per.rs b/pac/atsamc20g/src/tcc0/per.rs new file mode 100644 index 000000000000..9d8618631650 --- /dev/null +++ b/pac/atsamc20g/src/tcc0/per.rs @@ -0,0 +1,103 @@ +#[doc = "Register `PER` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PER` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER` reader - Period Value"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` writer - Period Value"] +pub struct PER_W<'a> { + w: &'a mut W, +} +impl<'a> PER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Period Value"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Period Value"] + #[inline(always)] + pub fn per(&mut self) -> PER_W { + PER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [per](index.html) module"] +pub struct PER_SPEC; +impl crate::RegisterSpec for PER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [per::R](R) reader structure"] +impl crate::Readable for PER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [per::W](W) writer structure"] +impl crate::Writable for PER_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PER to value 0xffff_ffff"] +impl crate::Resettable for PER_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pac/atsamc20g/src/tcc0/per_dith4_mode.rs b/pac/atsamc20g/src/tcc0/per_dith4_mode.rs new file mode 100644 index 000000000000..2f600552db84 --- /dev/null +++ b/pac/atsamc20g/src/tcc0/per_dith4_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PER_DITH4_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PER_DITH4_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHER` reader - Dithering Cycle Number"] +pub struct DITHER_R(crate::FieldReader); +impl DITHER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHER` writer - Dithering Cycle Number"] +pub struct DITHER_W<'a> { + w: &'a mut W, +} +impl<'a> DITHER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Field `PER` reader - Period Value"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` writer - Period Value"] +pub struct PER_W<'a> { + w: &'a mut W, +} +impl<'a> PER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x000f_ffff << 4)) | ((value as u32 & 0x000f_ffff) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&self) -> DITHER_R { + DITHER_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:23 - Period Value"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(((self.bits >> 4) & 0x000f_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:3 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&mut self) -> DITHER_W { + DITHER_W { w: self } + } + #[doc = "Bits 4:23 - Period Value"] + #[inline(always)] + pub fn per(&mut self) -> PER_W { + PER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [per_dith4_mode](index.html) module"] +pub struct PER_DITH4_MODE_SPEC; +impl crate::RegisterSpec for PER_DITH4_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [per_dith4_mode::R](R) reader structure"] +impl crate::Readable for PER_DITH4_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [per_dith4_mode::W](W) writer structure"] +impl crate::Writable for PER_DITH4_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PER_DITH4_MODE to value 0xffff_ffff"] +impl crate::Resettable for PER_DITH4_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pac/atsamc20g/src/tcc0/per_dith5_mode.rs b/pac/atsamc20g/src/tcc0/per_dith5_mode.rs new file mode 100644 index 000000000000..1906582e4c95 --- /dev/null +++ b/pac/atsamc20g/src/tcc0/per_dith5_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PER_DITH5_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PER_DITH5_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHER` reader - Dithering Cycle Number"] +pub struct DITHER_R(crate::FieldReader); +impl DITHER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHER` writer - Dithering Cycle Number"] +pub struct DITHER_W<'a> { + w: &'a mut W, +} +impl<'a> DITHER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f); + self.w + } +} +#[doc = "Field `PER` reader - Period Value"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` writer - Period Value"] +pub struct PER_W<'a> { + w: &'a mut W, +} +impl<'a> PER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0007_ffff << 5)) | ((value as u32 & 0x0007_ffff) << 5); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&self) -> DITHER_R { + DITHER_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:23 - Period Value"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(((self.bits >> 5) & 0x0007_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:4 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&mut self) -> DITHER_W { + DITHER_W { w: self } + } + #[doc = "Bits 5:23 - Period Value"] + #[inline(always)] + pub fn per(&mut self) -> PER_W { + PER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [per_dith5_mode](index.html) module"] +pub struct PER_DITH5_MODE_SPEC; +impl crate::RegisterSpec for PER_DITH5_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [per_dith5_mode::R](R) reader structure"] +impl crate::Readable for PER_DITH5_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [per_dith5_mode::W](W) writer structure"] +impl crate::Writable for PER_DITH5_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PER_DITH5_MODE to value 0xffff_ffff"] +impl crate::Resettable for PER_DITH5_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pac/atsamc20g/src/tcc0/per_dith6_mode.rs b/pac/atsamc20g/src/tcc0/per_dith6_mode.rs new file mode 100644 index 000000000000..67880e220a9c --- /dev/null +++ b/pac/atsamc20g/src/tcc0/per_dith6_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PER_DITH6_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PER_DITH6_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHER` reader - Dithering Cycle Number"] +pub struct DITHER_R(crate::FieldReader); +impl DITHER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHER` writer - Dithering Cycle Number"] +pub struct DITHER_W<'a> { + w: &'a mut W, +} +impl<'a> DITHER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +#[doc = "Field `PER` reader - Period Value"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` writer - Period Value"] +pub struct PER_W<'a> { + w: &'a mut W, +} +impl<'a> PER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0003_ffff << 6)) | ((value as u32 & 0x0003_ffff) << 6); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&self) -> DITHER_R { + DITHER_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:23 - Period Value"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(((self.bits >> 6) & 0x0003_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:5 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&mut self) -> DITHER_W { + DITHER_W { w: self } + } + #[doc = "Bits 6:23 - Period Value"] + #[inline(always)] + pub fn per(&mut self) -> PER_W { + PER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [per_dith6_mode](index.html) module"] +pub struct PER_DITH6_MODE_SPEC; +impl crate::RegisterSpec for PER_DITH6_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [per_dith6_mode::R](R) reader structure"] +impl crate::Readable for PER_DITH6_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [per_dith6_mode::W](W) writer structure"] +impl crate::Writable for PER_DITH6_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PER_DITH6_MODE to value 0xffff_ffff"] +impl crate::Resettable for PER_DITH6_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pac/atsamc20g/src/tcc0/perbuf.rs b/pac/atsamc20g/src/tcc0/perbuf.rs new file mode 100644 index 000000000000..169f17479616 --- /dev/null +++ b/pac/atsamc20g/src/tcc0/perbuf.rs @@ -0,0 +1,103 @@ +#[doc = "Register `PERBUF` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PERBUF` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PERBUF` reader - Period Buffer Value"] +pub struct PERBUF_R(crate::FieldReader); +impl PERBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + PERBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERBUF` writer - Period Buffer Value"] +pub struct PERBUF_W<'a> { + w: &'a mut W, +} +impl<'a> PERBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Period Buffer Value"] + #[inline(always)] + pub fn perbuf(&self) -> PERBUF_R { + PERBUF_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Period Buffer Value"] + #[inline(always)] + pub fn perbuf(&mut self) -> PERBUF_W { + PERBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [perbuf](index.html) module"] +pub struct PERBUF_SPEC; +impl crate::RegisterSpec for PERBUF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [perbuf::R](R) reader structure"] +impl crate::Readable for PERBUF_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [perbuf::W](W) writer structure"] +impl crate::Writable for PERBUF_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PERBUF to value 0xffff_ffff"] +impl crate::Resettable for PERBUF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pac/atsamc20g/src/tcc0/perbuf_dith4_mode.rs b/pac/atsamc20g/src/tcc0/perbuf_dith4_mode.rs new file mode 100644 index 000000000000..ccf96ecef185 --- /dev/null +++ b/pac/atsamc20g/src/tcc0/perbuf_dith4_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PERBUF_DITH4_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PERBUF_DITH4_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHERBUF` reader - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_R(crate::FieldReader); +impl DITHERBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHERBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHERBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHERBUF` writer - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_W<'a> { + w: &'a mut W, +} +impl<'a> DITHERBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Field `PERBUF` reader - Period Buffer Value"] +pub struct PERBUF_R(crate::FieldReader); +impl PERBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + PERBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERBUF` writer - Period Buffer Value"] +pub struct PERBUF_W<'a> { + w: &'a mut W, +} +impl<'a> PERBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x000f_ffff << 4)) | ((value as u32 & 0x000f_ffff) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&self) -> DITHERBUF_R { + DITHERBUF_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:23 - Period Buffer Value"] + #[inline(always)] + pub fn perbuf(&self) -> PERBUF_R { + PERBUF_R::new(((self.bits >> 4) & 0x000f_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:3 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&mut self) -> DITHERBUF_W { + DITHERBUF_W { w: self } + } + #[doc = "Bits 4:23 - Period Buffer Value"] + #[inline(always)] + pub fn perbuf(&mut self) -> PERBUF_W { + PERBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [perbuf_dith4_mode](index.html) module"] +pub struct PERBUF_DITH4_MODE_SPEC; +impl crate::RegisterSpec for PERBUF_DITH4_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [perbuf_dith4_mode::R](R) reader structure"] +impl crate::Readable for PERBUF_DITH4_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [perbuf_dith4_mode::W](W) writer structure"] +impl crate::Writable for PERBUF_DITH4_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PERBUF_DITH4_MODE to value 0xffff_ffff"] +impl crate::Resettable for PERBUF_DITH4_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pac/atsamc20g/src/tcc0/perbuf_dith5_mode.rs b/pac/atsamc20g/src/tcc0/perbuf_dith5_mode.rs new file mode 100644 index 000000000000..d55f6d52c5ba --- /dev/null +++ b/pac/atsamc20g/src/tcc0/perbuf_dith5_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PERBUF_DITH5_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PERBUF_DITH5_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHERBUF` reader - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_R(crate::FieldReader); +impl DITHERBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHERBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHERBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHERBUF` writer - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_W<'a> { + w: &'a mut W, +} +impl<'a> DITHERBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f); + self.w + } +} +#[doc = "Field `PERBUF` reader - Period Buffer Value"] +pub struct PERBUF_R(crate::FieldReader); +impl PERBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + PERBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERBUF` writer - Period Buffer Value"] +pub struct PERBUF_W<'a> { + w: &'a mut W, +} +impl<'a> PERBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0007_ffff << 5)) | ((value as u32 & 0x0007_ffff) << 5); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&self) -> DITHERBUF_R { + DITHERBUF_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:23 - Period Buffer Value"] + #[inline(always)] + pub fn perbuf(&self) -> PERBUF_R { + PERBUF_R::new(((self.bits >> 5) & 0x0007_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:4 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&mut self) -> DITHERBUF_W { + DITHERBUF_W { w: self } + } + #[doc = "Bits 5:23 - Period Buffer Value"] + #[inline(always)] + pub fn perbuf(&mut self) -> PERBUF_W { + PERBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [perbuf_dith5_mode](index.html) module"] +pub struct PERBUF_DITH5_MODE_SPEC; +impl crate::RegisterSpec for PERBUF_DITH5_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [perbuf_dith5_mode::R](R) reader structure"] +impl crate::Readable for PERBUF_DITH5_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [perbuf_dith5_mode::W](W) writer structure"] +impl crate::Writable for PERBUF_DITH5_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PERBUF_DITH5_MODE to value 0xffff_ffff"] +impl crate::Resettable for PERBUF_DITH5_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pac/atsamc20g/src/tcc0/perbuf_dith6_mode.rs b/pac/atsamc20g/src/tcc0/perbuf_dith6_mode.rs new file mode 100644 index 000000000000..983c849f9073 --- /dev/null +++ b/pac/atsamc20g/src/tcc0/perbuf_dith6_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PERBUF_DITH6_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PERBUF_DITH6_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHERBUF` reader - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_R(crate::FieldReader); +impl DITHERBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHERBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHERBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHERBUF` writer - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_W<'a> { + w: &'a mut W, +} +impl<'a> DITHERBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +#[doc = "Field `PERBUF` reader - Period Buffer Value"] +pub struct PERBUF_R(crate::FieldReader); +impl PERBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + PERBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERBUF` writer - Period Buffer Value"] +pub struct PERBUF_W<'a> { + w: &'a mut W, +} +impl<'a> PERBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0003_ffff << 6)) | ((value as u32 & 0x0003_ffff) << 6); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&self) -> DITHERBUF_R { + DITHERBUF_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:23 - Period Buffer Value"] + #[inline(always)] + pub fn perbuf(&self) -> PERBUF_R { + PERBUF_R::new(((self.bits >> 6) & 0x0003_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:5 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&mut self) -> DITHERBUF_W { + DITHERBUF_W { w: self } + } + #[doc = "Bits 6:23 - Period Buffer Value"] + #[inline(always)] + pub fn perbuf(&mut self) -> PERBUF_W { + PERBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [perbuf_dith6_mode](index.html) module"] +pub struct PERBUF_DITH6_MODE_SPEC; +impl crate::RegisterSpec for PERBUF_DITH6_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [perbuf_dith6_mode::R](R) reader structure"] +impl crate::Readable for PERBUF_DITH6_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [perbuf_dith6_mode::W](W) writer structure"] +impl crate::Writable for PERBUF_DITH6_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PERBUF_DITH6_MODE to value 0xffff_ffff"] +impl crate::Resettable for PERBUF_DITH6_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pac/atsamc20g/src/tcc0/status.rs b/pac/atsamc20g/src/tcc0/status.rs new file mode 100644 index 000000000000..eecd909e6093 --- /dev/null +++ b/pac/atsamc20g/src/tcc0/status.rs @@ -0,0 +1,1147 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `STOP` reader - Stop"] +pub struct STOP_R(crate::FieldReader); +impl STOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STOP` writer - Stop"] +pub struct STOP_W<'a> { + w: &'a mut W, +} +impl<'a> STOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `IDX` reader - Ramp"] +pub struct IDX_R(crate::FieldReader); +impl IDX_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IDX_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IDX_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IDX` writer - Ramp"] +pub struct IDX_W<'a> { + w: &'a mut W, +} +impl<'a> IDX_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `UFS` reader - Non-recoverable Update Fault State"] +pub struct UFS_R(crate::FieldReader); +impl UFS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UFS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for UFS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `UFS` writer - Non-recoverable Update Fault State"] +pub struct UFS_W<'a> { + w: &'a mut W, +} +impl<'a> UFS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `DFS` reader - Non-Recoverable Debug Fault State"] +pub struct DFS_R(crate::FieldReader); +impl DFS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFS` writer - Non-Recoverable Debug Fault State"] +pub struct DFS_W<'a> { + w: &'a mut W, +} +impl<'a> DFS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `SLAVE` reader - Slave"] +pub struct SLAVE_R(crate::FieldReader); +impl SLAVE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLAVE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SLAVE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLAVE` writer - Slave"] +pub struct SLAVE_W<'a> { + w: &'a mut W, +} +impl<'a> SLAVE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PATTBUFV` reader - Pattern Buffer Valid"] +pub struct PATTBUFV_R(crate::FieldReader); +impl PATTBUFV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PATTBUFV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PATTBUFV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PATTBUFV` writer - Pattern Buffer Valid"] +pub struct PATTBUFV_W<'a> { + w: &'a mut W, +} +impl<'a> PATTBUFV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PERBUFV` reader - Period Buffer Valid"] +pub struct PERBUFV_R(crate::FieldReader); +impl PERBUFV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PERBUFV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERBUFV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERBUFV` writer - Period Buffer Valid"] +pub struct PERBUFV_W<'a> { + w: &'a mut W, +} +impl<'a> PERBUFV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `FAULTAIN` reader - Recoverable Fault A Input"] +pub struct FAULTAIN_R(crate::FieldReader); +impl FAULTAIN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTAIN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTAIN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTAIN` writer - Recoverable Fault A Input"] +pub struct FAULTAIN_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTAIN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `FAULTBIN` reader - Recoverable Fault B Input"] +pub struct FAULTBIN_R(crate::FieldReader); +impl FAULTBIN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTBIN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTBIN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTBIN` writer - Recoverable Fault B Input"] +pub struct FAULTBIN_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTBIN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `FAULT0IN` reader - Non-Recoverable Fault0 Input"] +pub struct FAULT0IN_R(crate::FieldReader); +impl FAULT0IN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT0IN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT0IN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT0IN` writer - Non-Recoverable Fault0 Input"] +pub struct FAULT0IN_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT0IN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `FAULT1IN` reader - Non-Recoverable Fault1 Input"] +pub struct FAULT1IN_R(crate::FieldReader); +impl FAULT1IN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT1IN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT1IN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT1IN` writer - Non-Recoverable Fault1 Input"] +pub struct FAULT1IN_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT1IN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `FAULTA` reader - Recoverable Fault A State"] +pub struct FAULTA_R(crate::FieldReader); +impl FAULTA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTA` writer - Recoverable Fault A State"] +pub struct FAULTA_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `FAULTB` reader - Recoverable Fault B State"] +pub struct FAULTB_R(crate::FieldReader); +impl FAULTB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTB` writer - Recoverable Fault B State"] +pub struct FAULTB_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `FAULT0` reader - Non-Recoverable Fault 0 State"] +pub struct FAULT0_R(crate::FieldReader); +impl FAULT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT0` writer - Non-Recoverable Fault 0 State"] +pub struct FAULT0_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `FAULT1` reader - Non-Recoverable Fault 1 State"] +pub struct FAULT1_R(crate::FieldReader); +impl FAULT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT1` writer - Non-Recoverable Fault 1 State"] +pub struct FAULT1_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `CCBUFV0` reader - Compare Channel 0 Buffer Valid"] +pub struct CCBUFV0_R(crate::FieldReader); +impl CCBUFV0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBUFV0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUFV0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUFV0` writer - Compare Channel 0 Buffer Valid"] +pub struct CCBUFV0_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUFV0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `CCBUFV1` reader - Compare Channel 1 Buffer Valid"] +pub struct CCBUFV1_R(crate::FieldReader); +impl CCBUFV1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBUFV1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUFV1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUFV1` writer - Compare Channel 1 Buffer Valid"] +pub struct CCBUFV1_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUFV1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `CCBUFV2` reader - Compare Channel 2 Buffer Valid"] +pub struct CCBUFV2_R(crate::FieldReader); +impl CCBUFV2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBUFV2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUFV2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUFV2` writer - Compare Channel 2 Buffer Valid"] +pub struct CCBUFV2_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUFV2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `CCBUFV3` reader - Compare Channel 3 Buffer Valid"] +pub struct CCBUFV3_R(crate::FieldReader); +impl CCBUFV3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBUFV3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUFV3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUFV3` writer - Compare Channel 3 Buffer Valid"] +pub struct CCBUFV3_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUFV3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `CMP0` reader - Compare Channel 0 Value"] +pub struct CMP0_R(crate::FieldReader); +impl CMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP0` writer - Compare Channel 0 Value"] +pub struct CMP0_W<'a> { + w: &'a mut W, +} +impl<'a> CMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `CMP1` reader - Compare Channel 1 Value"] +pub struct CMP1_R(crate::FieldReader); +impl CMP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP1` writer - Compare Channel 1 Value"] +pub struct CMP1_W<'a> { + w: &'a mut W, +} +impl<'a> CMP1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `CMP2` reader - Compare Channel 2 Value"] +pub struct CMP2_R(crate::FieldReader); +impl CMP2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP2` writer - Compare Channel 2 Value"] +pub struct CMP2_W<'a> { + w: &'a mut W, +} +impl<'a> CMP2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `CMP3` reader - Compare Channel 3 Value"] +pub struct CMP3_R(crate::FieldReader); +impl CMP3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP3` writer - Compare Channel 3 Value"] +pub struct CMP3_W<'a> { + w: &'a mut W, +} +impl<'a> CMP3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +impl R { + #[doc = "Bit 0 - Stop"] + #[inline(always)] + pub fn stop(&self) -> STOP_R { + STOP_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Ramp"] + #[inline(always)] + pub fn idx(&self) -> IDX_R { + IDX_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Non-recoverable Update Fault State"] + #[inline(always)] + pub fn ufs(&self) -> UFS_R { + UFS_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Non-Recoverable Debug Fault State"] + #[inline(always)] + pub fn dfs(&self) -> DFS_R { + DFS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Slave"] + #[inline(always)] + pub fn slave(&self) -> SLAVE_R { + SLAVE_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Pattern Buffer Valid"] + #[inline(always)] + pub fn pattbufv(&self) -> PATTBUFV_R { + PATTBUFV_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 7 - Period Buffer Valid"] + #[inline(always)] + pub fn perbufv(&self) -> PERBUFV_R { + PERBUFV_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Recoverable Fault A Input"] + #[inline(always)] + pub fn faultain(&self) -> FAULTAIN_R { + FAULTAIN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Recoverable Fault B Input"] + #[inline(always)] + pub fn faultbin(&self) -> FAULTBIN_R { + FAULTBIN_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Non-Recoverable Fault0 Input"] + #[inline(always)] + pub fn fault0in(&self) -> FAULT0IN_R { + FAULT0IN_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Non-Recoverable Fault1 Input"] + #[inline(always)] + pub fn fault1in(&self) -> FAULT1IN_R { + FAULT1IN_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Recoverable Fault A State"] + #[inline(always)] + pub fn faulta(&self) -> FAULTA_R { + FAULTA_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Recoverable Fault B State"] + #[inline(always)] + pub fn faultb(&self) -> FAULTB_R { + FAULTB_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Non-Recoverable Fault 0 State"] + #[inline(always)] + pub fn fault0(&self) -> FAULT0_R { + FAULT0_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Non-Recoverable Fault 1 State"] + #[inline(always)] + pub fn fault1(&self) -> FAULT1_R { + FAULT1_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Compare Channel 0 Buffer Valid"] + #[inline(always)] + pub fn ccbufv0(&self) -> CCBUFV0_R { + CCBUFV0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Compare Channel 1 Buffer Valid"] + #[inline(always)] + pub fn ccbufv1(&self) -> CCBUFV1_R { + CCBUFV1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Compare Channel 2 Buffer Valid"] + #[inline(always)] + pub fn ccbufv2(&self) -> CCBUFV2_R { + CCBUFV2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Compare Channel 3 Buffer Valid"] + #[inline(always)] + pub fn ccbufv3(&self) -> CCBUFV3_R { + CCBUFV3_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 24 - Compare Channel 0 Value"] + #[inline(always)] + pub fn cmp0(&self) -> CMP0_R { + CMP0_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Compare Channel 1 Value"] + #[inline(always)] + pub fn cmp1(&self) -> CMP1_R { + CMP1_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Compare Channel 2 Value"] + #[inline(always)] + pub fn cmp2(&self) -> CMP2_R { + CMP2_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Compare Channel 3 Value"] + #[inline(always)] + pub fn cmp3(&self) -> CMP3_R { + CMP3_R::new(((self.bits >> 27) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Stop"] + #[inline(always)] + pub fn stop(&mut self) -> STOP_W { + STOP_W { w: self } + } + #[doc = "Bit 1 - Ramp"] + #[inline(always)] + pub fn idx(&mut self) -> IDX_W { + IDX_W { w: self } + } + #[doc = "Bit 2 - Non-recoverable Update Fault State"] + #[inline(always)] + pub fn ufs(&mut self) -> UFS_W { + UFS_W { w: self } + } + #[doc = "Bit 3 - Non-Recoverable Debug Fault State"] + #[inline(always)] + pub fn dfs(&mut self) -> DFS_W { + DFS_W { w: self } + } + #[doc = "Bit 4 - Slave"] + #[inline(always)] + pub fn slave(&mut self) -> SLAVE_W { + SLAVE_W { w: self } + } + #[doc = "Bit 5 - Pattern Buffer Valid"] + #[inline(always)] + pub fn pattbufv(&mut self) -> PATTBUFV_W { + PATTBUFV_W { w: self } + } + #[doc = "Bit 7 - Period Buffer Valid"] + #[inline(always)] + pub fn perbufv(&mut self) -> PERBUFV_W { + PERBUFV_W { w: self } + } + #[doc = "Bit 8 - Recoverable Fault A Input"] + #[inline(always)] + pub fn faultain(&mut self) -> FAULTAIN_W { + FAULTAIN_W { w: self } + } + #[doc = "Bit 9 - Recoverable Fault B Input"] + #[inline(always)] + pub fn faultbin(&mut self) -> FAULTBIN_W { + FAULTBIN_W { w: self } + } + #[doc = "Bit 10 - Non-Recoverable Fault0 Input"] + #[inline(always)] + pub fn fault0in(&mut self) -> FAULT0IN_W { + FAULT0IN_W { w: self } + } + #[doc = "Bit 11 - Non-Recoverable Fault1 Input"] + #[inline(always)] + pub fn fault1in(&mut self) -> FAULT1IN_W { + FAULT1IN_W { w: self } + } + #[doc = "Bit 12 - Recoverable Fault A State"] + #[inline(always)] + pub fn faulta(&mut self) -> FAULTA_W { + FAULTA_W { w: self } + } + #[doc = "Bit 13 - Recoverable Fault B State"] + #[inline(always)] + pub fn faultb(&mut self) -> FAULTB_W { + FAULTB_W { w: self } + } + #[doc = "Bit 14 - Non-Recoverable Fault 0 State"] + #[inline(always)] + pub fn fault0(&mut self) -> FAULT0_W { + FAULT0_W { w: self } + } + #[doc = "Bit 15 - Non-Recoverable Fault 1 State"] + #[inline(always)] + pub fn fault1(&mut self) -> FAULT1_W { + FAULT1_W { w: self } + } + #[doc = "Bit 16 - Compare Channel 0 Buffer Valid"] + #[inline(always)] + pub fn ccbufv0(&mut self) -> CCBUFV0_W { + CCBUFV0_W { w: self } + } + #[doc = "Bit 17 - Compare Channel 1 Buffer Valid"] + #[inline(always)] + pub fn ccbufv1(&mut self) -> CCBUFV1_W { + CCBUFV1_W { w: self } + } + #[doc = "Bit 18 - Compare Channel 2 Buffer Valid"] + #[inline(always)] + pub fn ccbufv2(&mut self) -> CCBUFV2_W { + CCBUFV2_W { w: self } + } + #[doc = "Bit 19 - Compare Channel 3 Buffer Valid"] + #[inline(always)] + pub fn ccbufv3(&mut self) -> CCBUFV3_W { + CCBUFV3_W { w: self } + } + #[doc = "Bit 24 - Compare Channel 0 Value"] + #[inline(always)] + pub fn cmp0(&mut self) -> CMP0_W { + CMP0_W { w: self } + } + #[doc = "Bit 25 - Compare Channel 1 Value"] + #[inline(always)] + pub fn cmp1(&mut self) -> CMP1_W { + CMP1_W { w: self } + } + #[doc = "Bit 26 - Compare Channel 2 Value"] + #[inline(always)] + pub fn cmp2(&mut self) -> CMP2_W { + CMP2_W { w: self } + } + #[doc = "Bit 27 - Compare Channel 3 Value"] + #[inline(always)] + pub fn cmp3(&mut self) -> CMP3_W { + CMP3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0x01"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pac/atsamc20g/src/tcc0/syncbusy.rs b/pac/atsamc20g/src/tcc0/syncbusy.rs new file mode 100644 index 000000000000..db0788c3f206 --- /dev/null +++ b/pac/atsamc20g/src/tcc0/syncbusy.rs @@ -0,0 +1,273 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Swrst Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - Enable Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLB` reader - Ctrlb Busy"] +pub struct CTRLB_R(crate::FieldReader); +impl CTRLB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STATUS` reader - Status Busy"] +pub struct STATUS_R(crate::FieldReader); +impl STATUS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STATUS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STATUS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` reader - Count Busy"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PATT` reader - Pattern Busy"] +pub struct PATT_R(crate::FieldReader); +impl PATT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PATT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PATT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAVE` reader - Wave Busy"] +pub struct WAVE_R(crate::FieldReader); +impl WAVE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAVE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAVE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` reader - Period Busy"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC0` reader - Compare Channel 0 Busy"] +pub struct CC0_R(crate::FieldReader); +impl CC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC1` reader - Compare Channel 1 Busy"] +pub struct CC1_R(crate::FieldReader); +impl CC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC2` reader - Compare Channel 2 Busy"] +pub struct CC2_R(crate::FieldReader); +impl CC2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC3` reader - Compare Channel 3 Busy"] +pub struct CC3_R(crate::FieldReader); +impl CC3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Swrst Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Ctrlb Busy"] + #[inline(always)] + pub fn ctrlb(&self) -> CTRLB_R { + CTRLB_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Status Busy"] + #[inline(always)] + pub fn status(&self) -> STATUS_R { + STATUS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Count Busy"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Pattern Busy"] + #[inline(always)] + pub fn patt(&self) -> PATT_R { + PATT_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Wave Busy"] + #[inline(always)] + pub fn wave(&self) -> WAVE_R { + WAVE_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Period Busy"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Compare Channel 0 Busy"] + #[inline(always)] + pub fn cc0(&self) -> CC0_R { + CC0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Compare Channel 1 Busy"] + #[inline(always)] + pub fn cc1(&self) -> CC1_R { + CC1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Compare Channel 2 Busy"] + #[inline(always)] + pub fn cc2(&self) -> CC2_R { + CC2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Compare Channel 3 Busy"] + #[inline(always)] + pub fn cc3(&self) -> CC3_R { + CC3_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +#[doc = "Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/tcc0/wave.rs b/pac/atsamc20g/src/tcc0/wave.rs new file mode 100644 index 000000000000..8d092d429a91 --- /dev/null +++ b/pac/atsamc20g/src/tcc0/wave.rs @@ -0,0 +1,940 @@ +#[doc = "Register `WAVE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WAVE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Waveform Generation\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WAVEGEN_A { + #[doc = "0: Normal frequency"] + NFRQ = 0, + #[doc = "1: Match frequency"] + MFRQ = 1, + #[doc = "2: Normal PWM"] + NPWM = 2, + #[doc = "4: Dual-slope critical"] + DSCRITICAL = 4, + #[doc = "5: Dual-slope with interrupt/event condition when COUNT reaches ZERO"] + DSBOTTOM = 5, + #[doc = "6: Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP"] + DSBOTH = 6, + #[doc = "7: Dual-slope with interrupt/event condition when COUNT reaches TOP"] + DSTOP = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WAVEGEN_A) -> Self { + variant as _ + } +} +#[doc = "Field `WAVEGEN` reader - Waveform Generation"] +pub struct WAVEGEN_R(crate::FieldReader); +impl WAVEGEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WAVEGEN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(WAVEGEN_A::NFRQ), + 1 => Some(WAVEGEN_A::MFRQ), + 2 => Some(WAVEGEN_A::NPWM), + 4 => Some(WAVEGEN_A::DSCRITICAL), + 5 => Some(WAVEGEN_A::DSBOTTOM), + 6 => Some(WAVEGEN_A::DSBOTH), + 7 => Some(WAVEGEN_A::DSTOP), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NFRQ`"] + #[inline(always)] + pub fn is_nfrq(&self) -> bool { + **self == WAVEGEN_A::NFRQ + } + #[doc = "Checks if the value of the field is `MFRQ`"] + #[inline(always)] + pub fn is_mfrq(&self) -> bool { + **self == WAVEGEN_A::MFRQ + } + #[doc = "Checks if the value of the field is `NPWM`"] + #[inline(always)] + pub fn is_npwm(&self) -> bool { + **self == WAVEGEN_A::NPWM + } + #[doc = "Checks if the value of the field is `DSCRITICAL`"] + #[inline(always)] + pub fn is_dscritical(&self) -> bool { + **self == WAVEGEN_A::DSCRITICAL + } + #[doc = "Checks if the value of the field is `DSBOTTOM`"] + #[inline(always)] + pub fn is_dsbottom(&self) -> bool { + **self == WAVEGEN_A::DSBOTTOM + } + #[doc = "Checks if the value of the field is `DSBOTH`"] + #[inline(always)] + pub fn is_dsboth(&self) -> bool { + **self == WAVEGEN_A::DSBOTH + } + #[doc = "Checks if the value of the field is `DSTOP`"] + #[inline(always)] + pub fn is_dstop(&self) -> bool { + **self == WAVEGEN_A::DSTOP + } +} +impl core::ops::Deref for WAVEGEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAVEGEN` writer - Waveform Generation"] +pub struct WAVEGEN_W<'a> { + w: &'a mut W, +} +impl<'a> WAVEGEN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WAVEGEN_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Normal frequency"] + #[inline(always)] + pub fn nfrq(self) -> &'a mut W { + self.variant(WAVEGEN_A::NFRQ) + } + #[doc = "Match frequency"] + #[inline(always)] + pub fn mfrq(self) -> &'a mut W { + self.variant(WAVEGEN_A::MFRQ) + } + #[doc = "Normal PWM"] + #[inline(always)] + pub fn npwm(self) -> &'a mut W { + self.variant(WAVEGEN_A::NPWM) + } + #[doc = "Dual-slope critical"] + #[inline(always)] + pub fn dscritical(self) -> &'a mut W { + self.variant(WAVEGEN_A::DSCRITICAL) + } + #[doc = "Dual-slope with interrupt/event condition when COUNT reaches ZERO"] + #[inline(always)] + pub fn dsbottom(self) -> &'a mut W { + self.variant(WAVEGEN_A::DSBOTTOM) + } + #[doc = "Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP"] + #[inline(always)] + pub fn dsboth(self) -> &'a mut W { + self.variant(WAVEGEN_A::DSBOTH) + } + #[doc = "Dual-slope with interrupt/event condition when COUNT reaches TOP"] + #[inline(always)] + pub fn dstop(self) -> &'a mut W { + self.variant(WAVEGEN_A::DSTOP) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Ramp Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum RAMP_A { + #[doc = "0: RAMP1 operation"] + RAMP1 = 0, + #[doc = "1: Alternative RAMP2 operation"] + RAMP2A = 1, + #[doc = "2: RAMP2 operation"] + RAMP2 = 2, + #[doc = "3: Critical RAMP2 operation"] + RAMP2C = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RAMP_A) -> Self { + variant as _ + } +} +#[doc = "Field `RAMP` reader - Ramp Mode"] +pub struct RAMP_R(crate::FieldReader); +impl RAMP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RAMP_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RAMP_A { + match self.bits { + 0 => RAMP_A::RAMP1, + 1 => RAMP_A::RAMP2A, + 2 => RAMP_A::RAMP2, + 3 => RAMP_A::RAMP2C, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `RAMP1`"] + #[inline(always)] + pub fn is_ramp1(&self) -> bool { + **self == RAMP_A::RAMP1 + } + #[doc = "Checks if the value of the field is `RAMP2A`"] + #[inline(always)] + pub fn is_ramp2a(&self) -> bool { + **self == RAMP_A::RAMP2A + } + #[doc = "Checks if the value of the field is `RAMP2`"] + #[inline(always)] + pub fn is_ramp2(&self) -> bool { + **self == RAMP_A::RAMP2 + } + #[doc = "Checks if the value of the field is `RAMP2C`"] + #[inline(always)] + pub fn is_ramp2c(&self) -> bool { + **self == RAMP_A::RAMP2C + } +} +impl core::ops::Deref for RAMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RAMP` writer - Ramp Mode"] +pub struct RAMP_W<'a> { + w: &'a mut W, +} +impl<'a> RAMP_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RAMP_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "RAMP1 operation"] + #[inline(always)] + pub fn ramp1(self) -> &'a mut W { + self.variant(RAMP_A::RAMP1) + } + #[doc = "Alternative RAMP2 operation"] + #[inline(always)] + pub fn ramp2a(self) -> &'a mut W { + self.variant(RAMP_A::RAMP2A) + } + #[doc = "RAMP2 operation"] + #[inline(always)] + pub fn ramp2(self) -> &'a mut W { + self.variant(RAMP_A::RAMP2) + } + #[doc = "Critical RAMP2 operation"] + #[inline(always)] + pub fn ramp2c(self) -> &'a mut W { + self.variant(RAMP_A::RAMP2C) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u32 & 0x03) << 4); + self.w + } +} +#[doc = "Field `CIPEREN` reader - Circular period Enable"] +pub struct CIPEREN_R(crate::FieldReader); +impl CIPEREN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CIPEREN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CIPEREN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CIPEREN` writer - Circular period Enable"] +pub struct CIPEREN_W<'a> { + w: &'a mut W, +} +impl<'a> CIPEREN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CICCEN0` reader - Circular Channel 0 Enable"] +pub struct CICCEN0_R(crate::FieldReader); +impl CICCEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CICCEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CICCEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CICCEN0` writer - Circular Channel 0 Enable"] +pub struct CICCEN0_W<'a> { + w: &'a mut W, +} +impl<'a> CICCEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `CICCEN1` reader - Circular Channel 1 Enable"] +pub struct CICCEN1_R(crate::FieldReader); +impl CICCEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CICCEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CICCEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CICCEN1` writer - Circular Channel 1 Enable"] +pub struct CICCEN1_W<'a> { + w: &'a mut W, +} +impl<'a> CICCEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `CICCEN2` reader - Circular Channel 2 Enable"] +pub struct CICCEN2_R(crate::FieldReader); +impl CICCEN2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CICCEN2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CICCEN2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CICCEN2` writer - Circular Channel 2 Enable"] +pub struct CICCEN2_W<'a> { + w: &'a mut W, +} +impl<'a> CICCEN2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `CICCEN3` reader - Circular Channel 3 Enable"] +pub struct CICCEN3_R(crate::FieldReader); +impl CICCEN3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CICCEN3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CICCEN3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CICCEN3` writer - Circular Channel 3 Enable"] +pub struct CICCEN3_W<'a> { + w: &'a mut W, +} +impl<'a> CICCEN3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `POL0` reader - Channel 0 Polarity"] +pub struct POL0_R(crate::FieldReader); +impl POL0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + POL0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for POL0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `POL0` writer - Channel 0 Polarity"] +pub struct POL0_W<'a> { + w: &'a mut W, +} +impl<'a> POL0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `POL1` reader - Channel 1 Polarity"] +pub struct POL1_R(crate::FieldReader); +impl POL1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + POL1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for POL1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `POL1` writer - Channel 1 Polarity"] +pub struct POL1_W<'a> { + w: &'a mut W, +} +impl<'a> POL1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `POL2` reader - Channel 2 Polarity"] +pub struct POL2_R(crate::FieldReader); +impl POL2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + POL2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for POL2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `POL2` writer - Channel 2 Polarity"] +pub struct POL2_W<'a> { + w: &'a mut W, +} +impl<'a> POL2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `POL3` reader - Channel 3 Polarity"] +pub struct POL3_R(crate::FieldReader); +impl POL3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + POL3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for POL3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `POL3` writer - Channel 3 Polarity"] +pub struct POL3_W<'a> { + w: &'a mut W, +} +impl<'a> POL3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `SWAP0` reader - Swap DTI Output Pair 0"] +pub struct SWAP0_R(crate::FieldReader); +impl SWAP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWAP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWAP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWAP0` writer - Swap DTI Output Pair 0"] +pub struct SWAP0_W<'a> { + w: &'a mut W, +} +impl<'a> SWAP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `SWAP1` reader - Swap DTI Output Pair 1"] +pub struct SWAP1_R(crate::FieldReader); +impl SWAP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWAP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWAP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWAP1` writer - Swap DTI Output Pair 1"] +pub struct SWAP1_W<'a> { + w: &'a mut W, +} +impl<'a> SWAP1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `SWAP2` reader - Swap DTI Output Pair 2"] +pub struct SWAP2_R(crate::FieldReader); +impl SWAP2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWAP2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWAP2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWAP2` writer - Swap DTI Output Pair 2"] +pub struct SWAP2_W<'a> { + w: &'a mut W, +} +impl<'a> SWAP2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `SWAP3` reader - Swap DTI Output Pair 3"] +pub struct SWAP3_R(crate::FieldReader); +impl SWAP3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWAP3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWAP3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWAP3` writer - Swap DTI Output Pair 3"] +pub struct SWAP3_W<'a> { + w: &'a mut W, +} +impl<'a> SWAP3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Waveform Generation"] + #[inline(always)] + pub fn wavegen(&self) -> WAVEGEN_R { + WAVEGEN_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bits 4:5 - Ramp Mode"] + #[inline(always)] + pub fn ramp(&self) -> RAMP_R { + RAMP_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bit 7 - Circular period Enable"] + #[inline(always)] + pub fn ciperen(&self) -> CIPEREN_R { + CIPEREN_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Circular Channel 0 Enable"] + #[inline(always)] + pub fn ciccen0(&self) -> CICCEN0_R { + CICCEN0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Circular Channel 1 Enable"] + #[inline(always)] + pub fn ciccen1(&self) -> CICCEN1_R { + CICCEN1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Circular Channel 2 Enable"] + #[inline(always)] + pub fn ciccen2(&self) -> CICCEN2_R { + CICCEN2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Circular Channel 3 Enable"] + #[inline(always)] + pub fn ciccen3(&self) -> CICCEN3_R { + CICCEN3_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 16 - Channel 0 Polarity"] + #[inline(always)] + pub fn pol0(&self) -> POL0_R { + POL0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Channel 1 Polarity"] + #[inline(always)] + pub fn pol1(&self) -> POL1_R { + POL1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Channel 2 Polarity"] + #[inline(always)] + pub fn pol2(&self) -> POL2_R { + POL2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Channel 3 Polarity"] + #[inline(always)] + pub fn pol3(&self) -> POL3_R { + POL3_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 24 - Swap DTI Output Pair 0"] + #[inline(always)] + pub fn swap0(&self) -> SWAP0_R { + SWAP0_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Swap DTI Output Pair 1"] + #[inline(always)] + pub fn swap1(&self) -> SWAP1_R { + SWAP1_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Swap DTI Output Pair 2"] + #[inline(always)] + pub fn swap2(&self) -> SWAP2_R { + SWAP2_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Swap DTI Output Pair 3"] + #[inline(always)] + pub fn swap3(&self) -> SWAP3_R { + SWAP3_R::new(((self.bits >> 27) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Waveform Generation"] + #[inline(always)] + pub fn wavegen(&mut self) -> WAVEGEN_W { + WAVEGEN_W { w: self } + } + #[doc = "Bits 4:5 - Ramp Mode"] + #[inline(always)] + pub fn ramp(&mut self) -> RAMP_W { + RAMP_W { w: self } + } + #[doc = "Bit 7 - Circular period Enable"] + #[inline(always)] + pub fn ciperen(&mut self) -> CIPEREN_W { + CIPEREN_W { w: self } + } + #[doc = "Bit 8 - Circular Channel 0 Enable"] + #[inline(always)] + pub fn ciccen0(&mut self) -> CICCEN0_W { + CICCEN0_W { w: self } + } + #[doc = "Bit 9 - Circular Channel 1 Enable"] + #[inline(always)] + pub fn ciccen1(&mut self) -> CICCEN1_W { + CICCEN1_W { w: self } + } + #[doc = "Bit 10 - Circular Channel 2 Enable"] + #[inline(always)] + pub fn ciccen2(&mut self) -> CICCEN2_W { + CICCEN2_W { w: self } + } + #[doc = "Bit 11 - Circular Channel 3 Enable"] + #[inline(always)] + pub fn ciccen3(&mut self) -> CICCEN3_W { + CICCEN3_W { w: self } + } + #[doc = "Bit 16 - Channel 0 Polarity"] + #[inline(always)] + pub fn pol0(&mut self) -> POL0_W { + POL0_W { w: self } + } + #[doc = "Bit 17 - Channel 1 Polarity"] + #[inline(always)] + pub fn pol1(&mut self) -> POL1_W { + POL1_W { w: self } + } + #[doc = "Bit 18 - Channel 2 Polarity"] + #[inline(always)] + pub fn pol2(&mut self) -> POL2_W { + POL2_W { w: self } + } + #[doc = "Bit 19 - Channel 3 Polarity"] + #[inline(always)] + pub fn pol3(&mut self) -> POL3_W { + POL3_W { w: self } + } + #[doc = "Bit 24 - Swap DTI Output Pair 0"] + #[inline(always)] + pub fn swap0(&mut self) -> SWAP0_W { + SWAP0_W { w: self } + } + #[doc = "Bit 25 - Swap DTI Output Pair 1"] + #[inline(always)] + pub fn swap1(&mut self) -> SWAP1_W { + SWAP1_W { w: self } + } + #[doc = "Bit 26 - Swap DTI Output Pair 2"] + #[inline(always)] + pub fn swap2(&mut self) -> SWAP2_W { + SWAP2_W { w: self } + } + #[doc = "Bit 27 - Swap DTI Output Pair 3"] + #[inline(always)] + pub fn swap3(&mut self) -> SWAP3_W { + SWAP3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Waveform Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wave](index.html) module"] +pub struct WAVE_SPEC; +impl crate::RegisterSpec for WAVE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [wave::R](R) reader structure"] +impl crate::Readable for WAVE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wave::W](W) writer structure"] +impl crate::Writable for WAVE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WAVE to value 0"] +impl crate::Resettable for WAVE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/tcc0/wexctrl.rs b/pac/atsamc20g/src/tcc0/wexctrl.rs new file mode 100644 index 000000000000..8eb0d29cbee5 --- /dev/null +++ b/pac/atsamc20g/src/tcc0/wexctrl.rs @@ -0,0 +1,365 @@ +#[doc = "Register `WEXCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WEXCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OTMX` reader - Output Matrix"] +pub struct OTMX_R(crate::FieldReader); +impl OTMX_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + OTMX_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OTMX_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OTMX` writer - Output Matrix"] +pub struct OTMX_W<'a> { + w: &'a mut W, +} +impl<'a> OTMX_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u32 & 0x03); + self.w + } +} +#[doc = "Field `DTIEN0` reader - Dead-time Insertion Generator 0 Enable"] +pub struct DTIEN0_R(crate::FieldReader); +impl DTIEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DTIEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DTIEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DTIEN0` writer - Dead-time Insertion Generator 0 Enable"] +pub struct DTIEN0_W<'a> { + w: &'a mut W, +} +impl<'a> DTIEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `DTIEN1` reader - Dead-time Insertion Generator 1 Enable"] +pub struct DTIEN1_R(crate::FieldReader); +impl DTIEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DTIEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DTIEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DTIEN1` writer - Dead-time Insertion Generator 1 Enable"] +pub struct DTIEN1_W<'a> { + w: &'a mut W, +} +impl<'a> DTIEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `DTIEN2` reader - Dead-time Insertion Generator 2 Enable"] +pub struct DTIEN2_R(crate::FieldReader); +impl DTIEN2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DTIEN2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DTIEN2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DTIEN2` writer - Dead-time Insertion Generator 2 Enable"] +pub struct DTIEN2_W<'a> { + w: &'a mut W, +} +impl<'a> DTIEN2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `DTIEN3` reader - Dead-time Insertion Generator 3 Enable"] +pub struct DTIEN3_R(crate::FieldReader); +impl DTIEN3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DTIEN3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DTIEN3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DTIEN3` writer - Dead-time Insertion Generator 3 Enable"] +pub struct DTIEN3_W<'a> { + w: &'a mut W, +} +impl<'a> DTIEN3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `DTLS` reader - Dead-time Low Side Outputs Value"] +pub struct DTLS_R(crate::FieldReader); +impl DTLS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DTLS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DTLS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DTLS` writer - Dead-time Low Side Outputs Value"] +pub struct DTLS_W<'a> { + w: &'a mut W, +} +impl<'a> DTLS_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +#[doc = "Field `DTHS` reader - Dead-time High Side Outputs Value"] +pub struct DTHS_R(crate::FieldReader); +impl DTHS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DTHS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DTHS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DTHS` writer - Dead-time High Side Outputs Value"] +pub struct DTHS_W<'a> { + w: &'a mut W, +} +impl<'a> DTHS_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 24)) | ((value as u32 & 0xff) << 24); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Output Matrix"] + #[inline(always)] + pub fn otmx(&self) -> OTMX_R { + OTMX_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bit 8 - Dead-time Insertion Generator 0 Enable"] + #[inline(always)] + pub fn dtien0(&self) -> DTIEN0_R { + DTIEN0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Dead-time Insertion Generator 1 Enable"] + #[inline(always)] + pub fn dtien1(&self) -> DTIEN1_R { + DTIEN1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Dead-time Insertion Generator 2 Enable"] + #[inline(always)] + pub fn dtien2(&self) -> DTIEN2_R { + DTIEN2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Dead-time Insertion Generator 3 Enable"] + #[inline(always)] + pub fn dtien3(&self) -> DTIEN3_R { + DTIEN3_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bits 16:23 - Dead-time Low Side Outputs Value"] + #[inline(always)] + pub fn dtls(&self) -> DTLS_R { + DTLS_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Dead-time High Side Outputs Value"] + #[inline(always)] + pub fn dths(&self) -> DTHS_R { + DTHS_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Output Matrix"] + #[inline(always)] + pub fn otmx(&mut self) -> OTMX_W { + OTMX_W { w: self } + } + #[doc = "Bit 8 - Dead-time Insertion Generator 0 Enable"] + #[inline(always)] + pub fn dtien0(&mut self) -> DTIEN0_W { + DTIEN0_W { w: self } + } + #[doc = "Bit 9 - Dead-time Insertion Generator 1 Enable"] + #[inline(always)] + pub fn dtien1(&mut self) -> DTIEN1_W { + DTIEN1_W { w: self } + } + #[doc = "Bit 10 - Dead-time Insertion Generator 2 Enable"] + #[inline(always)] + pub fn dtien2(&mut self) -> DTIEN2_W { + DTIEN2_W { w: self } + } + #[doc = "Bit 11 - Dead-time Insertion Generator 3 Enable"] + #[inline(always)] + pub fn dtien3(&mut self) -> DTIEN3_W { + DTIEN3_W { w: self } + } + #[doc = "Bits 16:23 - Dead-time Low Side Outputs Value"] + #[inline(always)] + pub fn dtls(&mut self) -> DTLS_W { + DTLS_W { w: self } + } + #[doc = "Bits 24:31 - Dead-time High Side Outputs Value"] + #[inline(always)] + pub fn dths(&mut self) -> DTHS_W { + DTHS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Waveform Extension Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wexctrl](index.html) module"] +pub struct WEXCTRL_SPEC; +impl crate::RegisterSpec for WEXCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [wexctrl::R](R) reader structure"] +impl crate::Readable for WEXCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wexctrl::W](W) writer structure"] +impl crate::Writable for WEXCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WEXCTRL to value 0"] +impl crate::Resettable for WEXCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/wdt.rs b/pac/atsamc20g/src/wdt.rs new file mode 100644 index 000000000000..22b5c2bb706f --- /dev/null +++ b/pac/atsamc20g/src/wdt.rs @@ -0,0 +1,54 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrla: crate::Reg, + #[doc = "0x01 - Configuration"] + pub config: crate::Reg, + #[doc = "0x02 - Early Warning Interrupt Control"] + pub ewctrl: crate::Reg, + _reserved3: [u8; 0x01], + #[doc = "0x04 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x05 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x06 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x08 - Synchronization Busy"] + pub syncbusy: crate::Reg, + #[doc = "0x0c - Clear"] + pub clear: crate::Reg, +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control"] +pub mod ctrla; +#[doc = "CONFIG register accessor: an alias for `Reg`"] +pub type CONFIG = crate::Reg; +#[doc = "Configuration"] +pub mod config; +#[doc = "EWCTRL register accessor: an alias for `Reg`"] +pub type EWCTRL = crate::Reg; +#[doc = "Early Warning Interrupt Control"] +pub mod ewctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Busy"] +pub mod syncbusy; +#[doc = "CLEAR register accessor: an alias for `Reg`"] +pub type CLEAR = crate::Reg; +#[doc = "Clear"] +pub mod clear; diff --git a/pac/atsamc20g/src/wdt/clear.rs b/pac/atsamc20g/src/wdt/clear.rs new file mode 100644 index 000000000000..61ee21f3246a --- /dev/null +++ b/pac/atsamc20g/src/wdt/clear.rs @@ -0,0 +1,85 @@ +#[doc = "Register `CLEAR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Watchdog Clear\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CLEAR_AW { + #[doc = "165: Clear Key"] + KEY = 165, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CLEAR_AW) -> Self { + variant as _ + } +} +#[doc = "Field `CLEAR` writer - Watchdog Clear"] +pub struct CLEAR_W<'a> { + w: &'a mut W, +} +impl<'a> CLEAR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CLEAR_AW) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Clear Key"] + #[inline(always)] + pub fn key(self) -> &'a mut W { + self.variant(CLEAR_AW::KEY) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl W { + #[doc = "Bits 0:7 - Watchdog Clear"] + #[inline(always)] + pub fn clear(&mut self) -> CLEAR_W { + CLEAR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Clear\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clear](index.html) module"] +pub struct CLEAR_SPEC; +impl crate::RegisterSpec for CLEAR_SPEC { + type Ux = u8; +} +#[doc = "`write(|w| ..)` method takes [clear::W](W) writer structure"] +impl crate::Writable for CLEAR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CLEAR to value 0"] +impl crate::Resettable for CLEAR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/wdt/config.rs b/pac/atsamc20g/src/wdt/config.rs new file mode 100644 index 000000000000..c90f062b01f0 --- /dev/null +++ b/pac/atsamc20g/src/wdt/config.rs @@ -0,0 +1,498 @@ +#[doc = "Register `CONFIG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CONFIG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Time-Out Period\n\nValue on reset: 11"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PER_A { + #[doc = "0: 8 clock cycles"] + CYC8 = 0, + #[doc = "1: 16 clock cycles"] + CYC16 = 1, + #[doc = "2: 32 clock cycles"] + CYC32 = 2, + #[doc = "3: 64 clock cycles"] + CYC64 = 3, + #[doc = "4: 128 clock cycles"] + CYC128 = 4, + #[doc = "5: 256 clock cycles"] + CYC256 = 5, + #[doc = "6: 512 clock cycles"] + CYC512 = 6, + #[doc = "7: 1024 clock cycles"] + CYC1024 = 7, + #[doc = "8: 2048 clock cycles"] + CYC2048 = 8, + #[doc = "9: 4096 clock cycles"] + CYC4096 = 9, + #[doc = "10: 8192 clock cycles"] + CYC8192 = 10, + #[doc = "11: 16384 clock cycles"] + CYC16384 = 11, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PER` reader - Time-Out Period"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PER_A::CYC8), + 1 => Some(PER_A::CYC16), + 2 => Some(PER_A::CYC32), + 3 => Some(PER_A::CYC64), + 4 => Some(PER_A::CYC128), + 5 => Some(PER_A::CYC256), + 6 => Some(PER_A::CYC512), + 7 => Some(PER_A::CYC1024), + 8 => Some(PER_A::CYC2048), + 9 => Some(PER_A::CYC4096), + 10 => Some(PER_A::CYC8192), + 11 => Some(PER_A::CYC16384), + _ => None, + } + } + #[doc = "Checks if the value of the field is `CYC8`"] + #[inline(always)] + pub fn is_cyc8(&self) -> bool { + **self == PER_A::CYC8 + } + #[doc = "Checks if the value of the field is `CYC16`"] + #[inline(always)] + pub fn is_cyc16(&self) -> bool { + **self == PER_A::CYC16 + } + #[doc = "Checks if the value of the field is `CYC32`"] + #[inline(always)] + pub fn is_cyc32(&self) -> bool { + **self == PER_A::CYC32 + } + #[doc = "Checks if the value of the field is `CYC64`"] + #[inline(always)] + pub fn is_cyc64(&self) -> bool { + **self == PER_A::CYC64 + } + #[doc = "Checks if the value of the field is `CYC128`"] + #[inline(always)] + pub fn is_cyc128(&self) -> bool { + **self == PER_A::CYC128 + } + #[doc = "Checks if the value of the field is `CYC256`"] + #[inline(always)] + pub fn is_cyc256(&self) -> bool { + **self == PER_A::CYC256 + } + #[doc = "Checks if the value of the field is `CYC512`"] + #[inline(always)] + pub fn is_cyc512(&self) -> bool { + **self == PER_A::CYC512 + } + #[doc = "Checks if the value of the field is `CYC1024`"] + #[inline(always)] + pub fn is_cyc1024(&self) -> bool { + **self == PER_A::CYC1024 + } + #[doc = "Checks if the value of the field is `CYC2048`"] + #[inline(always)] + pub fn is_cyc2048(&self) -> bool { + **self == PER_A::CYC2048 + } + #[doc = "Checks if the value of the field is `CYC4096`"] + #[inline(always)] + pub fn is_cyc4096(&self) -> bool { + **self == PER_A::CYC4096 + } + #[doc = "Checks if the value of the field is `CYC8192`"] + #[inline(always)] + pub fn is_cyc8192(&self) -> bool { + **self == PER_A::CYC8192 + } + #[doc = "Checks if the value of the field is `CYC16384`"] + #[inline(always)] + pub fn is_cyc16384(&self) -> bool { + **self == PER_A::CYC16384 + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` writer - Time-Out Period"] +pub struct PER_W<'a> { + w: &'a mut W, +} +impl<'a> PER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PER_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8 clock cycles"] + #[inline(always)] + pub fn cyc8(self) -> &'a mut W { + self.variant(PER_A::CYC8) + } + #[doc = "16 clock cycles"] + #[inline(always)] + pub fn cyc16(self) -> &'a mut W { + self.variant(PER_A::CYC16) + } + #[doc = "32 clock cycles"] + #[inline(always)] + pub fn cyc32(self) -> &'a mut W { + self.variant(PER_A::CYC32) + } + #[doc = "64 clock cycles"] + #[inline(always)] + pub fn cyc64(self) -> &'a mut W { + self.variant(PER_A::CYC64) + } + #[doc = "128 clock cycles"] + #[inline(always)] + pub fn cyc128(self) -> &'a mut W { + self.variant(PER_A::CYC128) + } + #[doc = "256 clock cycles"] + #[inline(always)] + pub fn cyc256(self) -> &'a mut W { + self.variant(PER_A::CYC256) + } + #[doc = "512 clock cycles"] + #[inline(always)] + pub fn cyc512(self) -> &'a mut W { + self.variant(PER_A::CYC512) + } + #[doc = "1024 clock cycles"] + #[inline(always)] + pub fn cyc1024(self) -> &'a mut W { + self.variant(PER_A::CYC1024) + } + #[doc = "2048 clock cycles"] + #[inline(always)] + pub fn cyc2048(self) -> &'a mut W { + self.variant(PER_A::CYC2048) + } + #[doc = "4096 clock cycles"] + #[inline(always)] + pub fn cyc4096(self) -> &'a mut W { + self.variant(PER_A::CYC4096) + } + #[doc = "8192 clock cycles"] + #[inline(always)] + pub fn cyc8192(self) -> &'a mut W { + self.variant(PER_A::CYC8192) + } + #[doc = "16384 clock cycles"] + #[inline(always)] + pub fn cyc16384(self) -> &'a mut W { + self.variant(PER_A::CYC16384) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +#[doc = "Window Mode Time-Out Period\n\nValue on reset: 11"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WINDOW_A { + #[doc = "0: 8 clock cycles"] + CYC8 = 0, + #[doc = "1: 16 clock cycles"] + CYC16 = 1, + #[doc = "2: 32 clock cycles"] + CYC32 = 2, + #[doc = "3: 64 clock cycles"] + CYC64 = 3, + #[doc = "4: 128 clock cycles"] + CYC128 = 4, + #[doc = "5: 256 clock cycles"] + CYC256 = 5, + #[doc = "6: 512 clock cycles"] + CYC512 = 6, + #[doc = "7: 1024 clock cycles"] + CYC1024 = 7, + #[doc = "8: 2048 clock cycles"] + CYC2048 = 8, + #[doc = "9: 4096 clock cycles"] + CYC4096 = 9, + #[doc = "10: 8192 clock cycles"] + CYC8192 = 10, + #[doc = "11: 16384 clock cycles"] + CYC16384 = 11, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WINDOW_A) -> Self { + variant as _ + } +} +#[doc = "Field `WINDOW` reader - Window Mode Time-Out Period"] +pub struct WINDOW_R(crate::FieldReader); +impl WINDOW_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WINDOW_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(WINDOW_A::CYC8), + 1 => Some(WINDOW_A::CYC16), + 2 => Some(WINDOW_A::CYC32), + 3 => Some(WINDOW_A::CYC64), + 4 => Some(WINDOW_A::CYC128), + 5 => Some(WINDOW_A::CYC256), + 6 => Some(WINDOW_A::CYC512), + 7 => Some(WINDOW_A::CYC1024), + 8 => Some(WINDOW_A::CYC2048), + 9 => Some(WINDOW_A::CYC4096), + 10 => Some(WINDOW_A::CYC8192), + 11 => Some(WINDOW_A::CYC16384), + _ => None, + } + } + #[doc = "Checks if the value of the field is `CYC8`"] + #[inline(always)] + pub fn is_cyc8(&self) -> bool { + **self == WINDOW_A::CYC8 + } + #[doc = "Checks if the value of the field is `CYC16`"] + #[inline(always)] + pub fn is_cyc16(&self) -> bool { + **self == WINDOW_A::CYC16 + } + #[doc = "Checks if the value of the field is `CYC32`"] + #[inline(always)] + pub fn is_cyc32(&self) -> bool { + **self == WINDOW_A::CYC32 + } + #[doc = "Checks if the value of the field is `CYC64`"] + #[inline(always)] + pub fn is_cyc64(&self) -> bool { + **self == WINDOW_A::CYC64 + } + #[doc = "Checks if the value of the field is `CYC128`"] + #[inline(always)] + pub fn is_cyc128(&self) -> bool { + **self == WINDOW_A::CYC128 + } + #[doc = "Checks if the value of the field is `CYC256`"] + #[inline(always)] + pub fn is_cyc256(&self) -> bool { + **self == WINDOW_A::CYC256 + } + #[doc = "Checks if the value of the field is `CYC512`"] + #[inline(always)] + pub fn is_cyc512(&self) -> bool { + **self == WINDOW_A::CYC512 + } + #[doc = "Checks if the value of the field is `CYC1024`"] + #[inline(always)] + pub fn is_cyc1024(&self) -> bool { + **self == WINDOW_A::CYC1024 + } + #[doc = "Checks if the value of the field is `CYC2048`"] + #[inline(always)] + pub fn is_cyc2048(&self) -> bool { + **self == WINDOW_A::CYC2048 + } + #[doc = "Checks if the value of the field is `CYC4096`"] + #[inline(always)] + pub fn is_cyc4096(&self) -> bool { + **self == WINDOW_A::CYC4096 + } + #[doc = "Checks if the value of the field is `CYC8192`"] + #[inline(always)] + pub fn is_cyc8192(&self) -> bool { + **self == WINDOW_A::CYC8192 + } + #[doc = "Checks if the value of the field is `CYC16384`"] + #[inline(always)] + pub fn is_cyc16384(&self) -> bool { + **self == WINDOW_A::CYC16384 + } +} +impl core::ops::Deref for WINDOW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINDOW` writer - Window Mode Time-Out Period"] +pub struct WINDOW_W<'a> { + w: &'a mut W, +} +impl<'a> WINDOW_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WINDOW_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8 clock cycles"] + #[inline(always)] + pub fn cyc8(self) -> &'a mut W { + self.variant(WINDOW_A::CYC8) + } + #[doc = "16 clock cycles"] + #[inline(always)] + pub fn cyc16(self) -> &'a mut W { + self.variant(WINDOW_A::CYC16) + } + #[doc = "32 clock cycles"] + #[inline(always)] + pub fn cyc32(self) -> &'a mut W { + self.variant(WINDOW_A::CYC32) + } + #[doc = "64 clock cycles"] + #[inline(always)] + pub fn cyc64(self) -> &'a mut W { + self.variant(WINDOW_A::CYC64) + } + #[doc = "128 clock cycles"] + #[inline(always)] + pub fn cyc128(self) -> &'a mut W { + self.variant(WINDOW_A::CYC128) + } + #[doc = "256 clock cycles"] + #[inline(always)] + pub fn cyc256(self) -> &'a mut W { + self.variant(WINDOW_A::CYC256) + } + #[doc = "512 clock cycles"] + #[inline(always)] + pub fn cyc512(self) -> &'a mut W { + self.variant(WINDOW_A::CYC512) + } + #[doc = "1024 clock cycles"] + #[inline(always)] + pub fn cyc1024(self) -> &'a mut W { + self.variant(WINDOW_A::CYC1024) + } + #[doc = "2048 clock cycles"] + #[inline(always)] + pub fn cyc2048(self) -> &'a mut W { + self.variant(WINDOW_A::CYC2048) + } + #[doc = "4096 clock cycles"] + #[inline(always)] + pub fn cyc4096(self) -> &'a mut W { + self.variant(WINDOW_A::CYC4096) + } + #[doc = "8192 clock cycles"] + #[inline(always)] + pub fn cyc8192(self) -> &'a mut W { + self.variant(WINDOW_A::CYC8192) + } + #[doc = "16384 clock cycles"] + #[inline(always)] + pub fn cyc16384(self) -> &'a mut W { + self.variant(WINDOW_A::CYC16384) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 4)) | ((value as u8 & 0x0f) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Time-Out Period"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Window Mode Time-Out Period"] + #[inline(always)] + pub fn window(&self) -> WINDOW_R { + WINDOW_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Time-Out Period"] + #[inline(always)] + pub fn per(&mut self) -> PER_W { + PER_W { w: self } + } + #[doc = "Bits 4:7 - Window Mode Time-Out Period"] + #[inline(always)] + pub fn window(&mut self) -> WINDOW_W { + WINDOW_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [config](index.html) module"] +pub struct CONFIG_SPEC; +impl crate::RegisterSpec for CONFIG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [config::R](R) reader structure"] +impl crate::Readable for CONFIG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [config::W](W) writer structure"] +impl crate::Writable for CONFIG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CONFIG to value 0xbb"] +impl crate::Resettable for CONFIG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xbb + } +} diff --git a/pac/atsamc20g/src/wdt/ctrla.rs b/pac/atsamc20g/src/wdt/ctrla.rs new file mode 100644 index 000000000000..895169d36aeb --- /dev/null +++ b/pac/atsamc20g/src/wdt/ctrla.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WEN` reader - Watchdog Timer Window Mode Enable"] +pub struct WEN_R(crate::FieldReader); +impl WEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WEN` writer - Watchdog Timer Window Mode Enable"] +pub struct WEN_W<'a> { + w: &'a mut W, +} +impl<'a> WEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `ALWAYSON` reader - Always-On"] +pub struct ALWAYSON_R(crate::FieldReader); +impl ALWAYSON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALWAYSON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALWAYSON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALWAYSON` writer - Always-On"] +pub struct ALWAYSON_W<'a> { + w: &'a mut W, +} +impl<'a> ALWAYSON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Watchdog Timer Window Mode Enable"] + #[inline(always)] + pub fn wen(&self) -> WEN_R { + WEN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 7 - Always-On"] + #[inline(always)] + pub fn alwayson(&self) -> ALWAYSON_R { + ALWAYSON_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - Watchdog Timer Window Mode Enable"] + #[inline(always)] + pub fn wen(&mut self) -> WEN_W { + WEN_W { w: self } + } + #[doc = "Bit 7 - Always-On"] + #[inline(always)] + pub fn alwayson(&mut self) -> ALWAYSON_W { + ALWAYSON_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/wdt/ewctrl.rs b/pac/atsamc20g/src/wdt/ewctrl.rs new file mode 100644 index 000000000000..94542e9897a9 --- /dev/null +++ b/pac/atsamc20g/src/wdt/ewctrl.rs @@ -0,0 +1,282 @@ +#[doc = "Register `EWCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EWCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Early Warning Interrupt Time Offset\n\nValue on reset: 11"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EWOFFSET_A { + #[doc = "0: 8 clock cycles"] + CYC8 = 0, + #[doc = "1: 16 clock cycles"] + CYC16 = 1, + #[doc = "2: 32 clock cycles"] + CYC32 = 2, + #[doc = "3: 64 clock cycles"] + CYC64 = 3, + #[doc = "4: 128 clock cycles"] + CYC128 = 4, + #[doc = "5: 256 clock cycles"] + CYC256 = 5, + #[doc = "6: 512 clock cycles"] + CYC512 = 6, + #[doc = "7: 1024 clock cycles"] + CYC1024 = 7, + #[doc = "8: 2048 clock cycles"] + CYC2048 = 8, + #[doc = "9: 4096 clock cycles"] + CYC4096 = 9, + #[doc = "10: 8192 clock cycles"] + CYC8192 = 10, + #[doc = "11: 16384 clock cycles"] + CYC16384 = 11, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EWOFFSET_A) -> Self { + variant as _ + } +} +#[doc = "Field `EWOFFSET` reader - Early Warning Interrupt Time Offset"] +pub struct EWOFFSET_R(crate::FieldReader); +impl EWOFFSET_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EWOFFSET_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(EWOFFSET_A::CYC8), + 1 => Some(EWOFFSET_A::CYC16), + 2 => Some(EWOFFSET_A::CYC32), + 3 => Some(EWOFFSET_A::CYC64), + 4 => Some(EWOFFSET_A::CYC128), + 5 => Some(EWOFFSET_A::CYC256), + 6 => Some(EWOFFSET_A::CYC512), + 7 => Some(EWOFFSET_A::CYC1024), + 8 => Some(EWOFFSET_A::CYC2048), + 9 => Some(EWOFFSET_A::CYC4096), + 10 => Some(EWOFFSET_A::CYC8192), + 11 => Some(EWOFFSET_A::CYC16384), + _ => None, + } + } + #[doc = "Checks if the value of the field is `CYC8`"] + #[inline(always)] + pub fn is_cyc8(&self) -> bool { + **self == EWOFFSET_A::CYC8 + } + #[doc = "Checks if the value of the field is `CYC16`"] + #[inline(always)] + pub fn is_cyc16(&self) -> bool { + **self == EWOFFSET_A::CYC16 + } + #[doc = "Checks if the value of the field is `CYC32`"] + #[inline(always)] + pub fn is_cyc32(&self) -> bool { + **self == EWOFFSET_A::CYC32 + } + #[doc = "Checks if the value of the field is `CYC64`"] + #[inline(always)] + pub fn is_cyc64(&self) -> bool { + **self == EWOFFSET_A::CYC64 + } + #[doc = "Checks if the value of the field is `CYC128`"] + #[inline(always)] + pub fn is_cyc128(&self) -> bool { + **self == EWOFFSET_A::CYC128 + } + #[doc = "Checks if the value of the field is `CYC256`"] + #[inline(always)] + pub fn is_cyc256(&self) -> bool { + **self == EWOFFSET_A::CYC256 + } + #[doc = "Checks if the value of the field is `CYC512`"] + #[inline(always)] + pub fn is_cyc512(&self) -> bool { + **self == EWOFFSET_A::CYC512 + } + #[doc = "Checks if the value of the field is `CYC1024`"] + #[inline(always)] + pub fn is_cyc1024(&self) -> bool { + **self == EWOFFSET_A::CYC1024 + } + #[doc = "Checks if the value of the field is `CYC2048`"] + #[inline(always)] + pub fn is_cyc2048(&self) -> bool { + **self == EWOFFSET_A::CYC2048 + } + #[doc = "Checks if the value of the field is `CYC4096`"] + #[inline(always)] + pub fn is_cyc4096(&self) -> bool { + **self == EWOFFSET_A::CYC4096 + } + #[doc = "Checks if the value of the field is `CYC8192`"] + #[inline(always)] + pub fn is_cyc8192(&self) -> bool { + **self == EWOFFSET_A::CYC8192 + } + #[doc = "Checks if the value of the field is `CYC16384`"] + #[inline(always)] + pub fn is_cyc16384(&self) -> bool { + **self == EWOFFSET_A::CYC16384 + } +} +impl core::ops::Deref for EWOFFSET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EWOFFSET` writer - Early Warning Interrupt Time Offset"] +pub struct EWOFFSET_W<'a> { + w: &'a mut W, +} +impl<'a> EWOFFSET_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EWOFFSET_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8 clock cycles"] + #[inline(always)] + pub fn cyc8(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC8) + } + #[doc = "16 clock cycles"] + #[inline(always)] + pub fn cyc16(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC16) + } + #[doc = "32 clock cycles"] + #[inline(always)] + pub fn cyc32(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC32) + } + #[doc = "64 clock cycles"] + #[inline(always)] + pub fn cyc64(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC64) + } + #[doc = "128 clock cycles"] + #[inline(always)] + pub fn cyc128(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC128) + } + #[doc = "256 clock cycles"] + #[inline(always)] + pub fn cyc256(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC256) + } + #[doc = "512 clock cycles"] + #[inline(always)] + pub fn cyc512(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC512) + } + #[doc = "1024 clock cycles"] + #[inline(always)] + pub fn cyc1024(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC1024) + } + #[doc = "2048 clock cycles"] + #[inline(always)] + pub fn cyc2048(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC2048) + } + #[doc = "4096 clock cycles"] + #[inline(always)] + pub fn cyc4096(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC4096) + } + #[doc = "8192 clock cycles"] + #[inline(always)] + pub fn cyc8192(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC8192) + } + #[doc = "16384 clock cycles"] + #[inline(always)] + pub fn cyc16384(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC16384) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Early Warning Interrupt Time Offset"] + #[inline(always)] + pub fn ewoffset(&self) -> EWOFFSET_R { + EWOFFSET_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Early Warning Interrupt Time Offset"] + #[inline(always)] + pub fn ewoffset(&mut self) -> EWOFFSET_W { + EWOFFSET_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Early Warning Interrupt Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ewctrl](index.html) module"] +pub struct EWCTRL_SPEC; +impl crate::RegisterSpec for EWCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ewctrl::R](R) reader structure"] +impl crate::Readable for EWCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ewctrl::W](W) writer structure"] +impl crate::Writable for EWCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EWCTRL to value 0x0b"] +impl crate::Resettable for EWCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0b + } +} diff --git a/pac/atsamc20g/src/wdt/intenclr.rs b/pac/atsamc20g/src/wdt/intenclr.rs new file mode 100644 index 000000000000..ed4021f96cce --- /dev/null +++ b/pac/atsamc20g/src/wdt/intenclr.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EW` reader - Early Warning Interrupt Enable"] +pub struct EW_R(crate::FieldReader); +impl EW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EW` writer - Early Warning Interrupt Enable"] +pub struct EW_W<'a> { + w: &'a mut W, +} +impl<'a> EW_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Early Warning Interrupt Enable"] + #[inline(always)] + pub fn ew(&self) -> EW_R { + EW_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Early Warning Interrupt Enable"] + #[inline(always)] + pub fn ew(&mut self) -> EW_W { + EW_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/wdt/intenset.rs b/pac/atsamc20g/src/wdt/intenset.rs new file mode 100644 index 000000000000..5a0928ff0532 --- /dev/null +++ b/pac/atsamc20g/src/wdt/intenset.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EW` reader - Early Warning Interrupt Enable"] +pub struct EW_R(crate::FieldReader); +impl EW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EW` writer - Early Warning Interrupt Enable"] +pub struct EW_W<'a> { + w: &'a mut W, +} +impl<'a> EW_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Early Warning Interrupt Enable"] + #[inline(always)] + pub fn ew(&self) -> EW_R { + EW_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Early Warning Interrupt Enable"] + #[inline(always)] + pub fn ew(&mut self) -> EW_W { + EW_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/wdt/intflag.rs b/pac/atsamc20g/src/wdt/intflag.rs new file mode 100644 index 000000000000..f2c9b858a199 --- /dev/null +++ b/pac/atsamc20g/src/wdt/intflag.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EW` reader - Early Warning"] +pub struct EW_R(crate::FieldReader); +impl EW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EW` writer - Early Warning"] +pub struct EW_W<'a> { + w: &'a mut W, +} +impl<'a> EW_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Early Warning"] + #[inline(always)] + pub fn ew(&self) -> EW_R { + EW_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Early Warning"] + #[inline(always)] + pub fn ew(&mut self) -> EW_W { + EW_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20g/src/wdt/syncbusy.rs b/pac/atsamc20g/src/wdt/syncbusy.rs new file mode 100644 index 000000000000..a3ecf7fbdb8a --- /dev/null +++ b/pac/atsamc20g/src/wdt/syncbusy.rs @@ -0,0 +1,113 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `ENABLE` reader - Enable Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WEN` reader - Window Enable Busy"] +pub struct WEN_R(crate::FieldReader); +impl WEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALWAYSON` reader - Always-On Busy"] +pub struct ALWAYSON_R(crate::FieldReader); +impl ALWAYSON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALWAYSON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALWAYSON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLEAR` reader - Clear Busy"] +pub struct CLEAR_R(crate::FieldReader); +impl CLEAR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLEAR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLEAR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 1 - Enable Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Window Enable Busy"] + #[inline(always)] + pub fn wen(&self) -> WEN_R { + WEN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Always-On Busy"] + #[inline(always)] + pub fn alwayson(&self) -> ALWAYSON_R { + ALWAYSON_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Clear Busy"] + #[inline(always)] + pub fn clear(&self) -> CLEAR_R { + CLEAR_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +#[doc = "Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/CHANGELOG.md b/pac/atsamc20j/CHANGELOG.md new file mode 100644 index 000000000000..e28d85f63b31 --- /dev/null +++ b/pac/atsamc20j/CHANGELOG.md @@ -0,0 +1,6 @@ +# Unreleased + +- Initial version +--- + +Changelog tracking started at v0.0.1 diff --git a/pac/atsamc20j/Cargo.toml b/pac/atsamc20j/Cargo.toml new file mode 100644 index 000000000000..5e8fda5efe7a --- /dev/null +++ b/pac/atsamc20j/Cargo.toml @@ -0,0 +1,22 @@ +[package] +name = "atsamc20j" +description = "Peripheral access API for ATSAMC20J microcontrollers (generated using svd2rust)" +version = "0.0.1" +authors = ["Jeremy Boynes "] +keywords = ["no-std", "arm", "cortex-m"] +categories = ["embedded", "hardware-support", "no-std"] +license = "MIT OR Apache-2.0" +repository = "https://github.com/atsamd-rs/atsamd" +readme = "README.md" +edition = "2021" + +[dependencies] +cortex-m = "0.7" +vcell = "0.1" + +[dependencies.cortex-m-rt] +version = "0.7" +optional = true + +[features] +rt = ["cortex-m-rt/device"] diff --git a/pac/atsamc20j/README.md b/pac/atsamc20j/README.md new file mode 100644 index 000000000000..1e66f109cf0f --- /dev/null +++ b/pac/atsamc20j/README.md @@ -0,0 +1,26 @@ +# ATSAMC20J + +A peripheral access crate for the ATSAMC20E chip from Microchip (née Atmel) for Rust Embedded projects. + +[![Build Status](https://travis-ci.org/atsamd-rs/atsamd.svg?branch=master)](https://travis-ci.org/atsamd-rs/atsamd) +[![Crates.io](https://img.shields.io/crates/v/atsamc20j.svg)](https://crates.io/crates/atsamc20j) + +## [Documentation](https://docs.rs/atsamc20j) + +This source was automatically generated using `svd2rust`, split into smaller pieces using `form` and formatted via `rustfmt`. + +## License + +Licensed under either of: + +- Apache License, Version 2.0 ([LICENSE-APACHE](https://github.com/atsamd-rs/atsamd/blob/master/LICENSE-APACHE) or + http://www.apache.org/licenses/LICENSE-2.0) +- MIT license ([LICENSE-MIT](https://github.com/atsamd-rs/atsamd/blob/master/LICENSE-MIT) or http://opensource.org/licenses/MIT) + +at your option. + +### Contribution + +Unless you explicitly state otherwise, any contribution intentionally submitted +for inclusion in the work by you, as defined in the Apache-2.0 license, shall +be dual licensed as above, without any additional terms or conditions. diff --git a/pac/atsamc20j/build.rs b/pac/atsamc20j/build.rs new file mode 100644 index 000000000000..597923f50892 --- /dev/null +++ b/pac/atsamc20j/build.rs @@ -0,0 +1,16 @@ +use std::env; +use std::fs::File; +use std::io::Write; +use std::path::PathBuf; +fn main() { + if env::var_os("CARGO_FEATURE_RT").is_some() { + let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap()); + File::create(out.join("device.x")) + .unwrap() + .write_all(include_bytes!("device.x")) + .unwrap(); + println!("cargo:rustc-link-search={}", out.display()); + println!("cargo:rerun-if-changed=device.x"); + } + println!("cargo:rerun-if-changed=build.rs"); +} diff --git a/pac/atsamc20j/device.x b/pac/atsamc20j/device.x new file mode 100644 index 000000000000..c9ef51bf7250 --- /dev/null +++ b/pac/atsamc20j/device.x @@ -0,0 +1,23 @@ +PROVIDE(WDT = DefaultHandler); +PROVIDE(RTC = DefaultHandler); +PROVIDE(EIC = DefaultHandler); +PROVIDE(FREQM = DefaultHandler); +PROVIDE(NVMCTRL = DefaultHandler); +PROVIDE(DMAC = DefaultHandler); +PROVIDE(EVSYS = DefaultHandler); +PROVIDE(SERCOM0 = DefaultHandler); +PROVIDE(SERCOM1 = DefaultHandler); +PROVIDE(SERCOM2 = DefaultHandler); +PROVIDE(SERCOM3 = DefaultHandler); +PROVIDE(TCC0 = DefaultHandler); +PROVIDE(TCC1 = DefaultHandler); +PROVIDE(TCC2 = DefaultHandler); +PROVIDE(TC0 = DefaultHandler); +PROVIDE(TC1 = DefaultHandler); +PROVIDE(TC2 = DefaultHandler); +PROVIDE(TC3 = DefaultHandler); +PROVIDE(TC4 = DefaultHandler); +PROVIDE(ADC0 = DefaultHandler); +PROVIDE(AC = DefaultHandler); +PROVIDE(PTC = DefaultHandler); + diff --git a/pac/atsamc20j/src/ac.rs b/pac/atsamc20j/src/ac.rs new file mode 100644 index 000000000000..b66620475572 --- /dev/null +++ b/pac/atsamc20j/src/ac.rs @@ -0,0 +1,83 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + #[doc = "0x01 - Control B"] + pub ctrlb: crate::Reg, + #[doc = "0x02 - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x04 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x05 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x06 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x07 - Status A"] + pub statusa: crate::Reg, + #[doc = "0x08 - Status B"] + pub statusb: crate::Reg, + #[doc = "0x09 - Debug Control"] + pub dbgctrl: crate::Reg, + #[doc = "0x0a - Window Control"] + pub winctrl: crate::Reg, + _reserved10: [u8; 0x01], + #[doc = "0x0c - Scaler n"] + pub scaler: [crate::Reg; 4], + #[doc = "0x10..0x20 - Comparator Control n"] + pub compctrl: [crate::Reg; 4], + #[doc = "0x20 - Synchronization Busy"] + pub syncbusy: crate::Reg, +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "Control B"] +pub mod ctrlb; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUSA register accessor: an alias for `Reg`"] +pub type STATUSA = crate::Reg; +#[doc = "Status A"] +pub mod statusa; +#[doc = "STATUSB register accessor: an alias for `Reg`"] +pub type STATUSB = crate::Reg; +#[doc = "Status B"] +pub mod statusb; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "WINCTRL register accessor: an alias for `Reg`"] +pub type WINCTRL = crate::Reg; +#[doc = "Window Control"] +pub mod winctrl; +#[doc = "SCALER register accessor: an alias for `Reg`"] +pub type SCALER = crate::Reg; +#[doc = "Scaler n"] +pub mod scaler; +#[doc = "COMPCTRL register accessor: an alias for `Reg`"] +pub type COMPCTRL = crate::Reg; +#[doc = "Comparator Control n"] +pub mod compctrl; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Busy"] +pub mod syncbusy; diff --git a/pac/atsamc20j/src/ac/compctrl.rs b/pac/atsamc20j/src/ac/compctrl.rs new file mode 100644 index 000000000000..c52cb53fe56f --- /dev/null +++ b/pac/atsamc20j/src/ac/compctrl.rs @@ -0,0 +1,974 @@ +#[doc = "Register `COMPCTRL[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COMPCTRL[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SINGLE` reader - Single-Shot Mode"] +pub struct SINGLE_R(crate::FieldReader); +impl SINGLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SINGLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SINGLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SINGLE` writer - Single-Shot Mode"] +pub struct SINGLE_W<'a> { + w: &'a mut W, +} +impl<'a> SINGLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Interrupt Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum INTSEL_A { + #[doc = "0: Interrupt on comparator output toggle"] + TOGGLE = 0, + #[doc = "1: Interrupt on comparator output rising"] + RISING = 1, + #[doc = "2: Interrupt on comparator output falling"] + FALLING = 2, + #[doc = "3: Interrupt on end of comparison (single-shot mode only)"] + EOC = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: INTSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `INTSEL` reader - Interrupt Selection"] +pub struct INTSEL_R(crate::FieldReader); +impl INTSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + INTSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INTSEL_A { + match self.bits { + 0 => INTSEL_A::TOGGLE, + 1 => INTSEL_A::RISING, + 2 => INTSEL_A::FALLING, + 3 => INTSEL_A::EOC, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `TOGGLE`"] + #[inline(always)] + pub fn is_toggle(&self) -> bool { + **self == INTSEL_A::TOGGLE + } + #[doc = "Checks if the value of the field is `RISING`"] + #[inline(always)] + pub fn is_rising(&self) -> bool { + **self == INTSEL_A::RISING + } + #[doc = "Checks if the value of the field is `FALLING`"] + #[inline(always)] + pub fn is_falling(&self) -> bool { + **self == INTSEL_A::FALLING + } + #[doc = "Checks if the value of the field is `EOC`"] + #[inline(always)] + pub fn is_eoc(&self) -> bool { + **self == INTSEL_A::EOC + } +} +impl core::ops::Deref for INTSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INTSEL` writer - Interrupt Selection"] +pub struct INTSEL_W<'a> { + w: &'a mut W, +} +impl<'a> INTSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: INTSEL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Interrupt on comparator output toggle"] + #[inline(always)] + pub fn toggle(self) -> &'a mut W { + self.variant(INTSEL_A::TOGGLE) + } + #[doc = "Interrupt on comparator output rising"] + #[inline(always)] + pub fn rising(self) -> &'a mut W { + self.variant(INTSEL_A::RISING) + } + #[doc = "Interrupt on comparator output falling"] + #[inline(always)] + pub fn falling(self) -> &'a mut W { + self.variant(INTSEL_A::FALLING) + } + #[doc = "Interrupt on end of comparison (single-shot mode only)"] + #[inline(always)] + pub fn eoc(self) -> &'a mut W { + self.variant(INTSEL_A::EOC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 3)) | ((value as u32 & 0x03) << 3); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Negative Input Mux Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MUXNEG_A { + #[doc = "0: I/O pin 0"] + PIN0 = 0, + #[doc = "1: I/O pin 1"] + PIN1 = 1, + #[doc = "2: I/O pin 2"] + PIN2 = 2, + #[doc = "3: I/O pin 3"] + PIN3 = 3, + #[doc = "4: Ground"] + GND = 4, + #[doc = "5: VDD scaler"] + VSCALE = 5, + #[doc = "6: Internal bandgap voltage"] + BANDGAP = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MUXNEG_A) -> Self { + variant as _ + } +} +#[doc = "Field `MUXNEG` reader - Negative Input Mux Selection"] +pub struct MUXNEG_R(crate::FieldReader); +impl MUXNEG_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MUXNEG_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MUXNEG_A::PIN0), + 1 => Some(MUXNEG_A::PIN1), + 2 => Some(MUXNEG_A::PIN2), + 3 => Some(MUXNEG_A::PIN3), + 4 => Some(MUXNEG_A::GND), + 5 => Some(MUXNEG_A::VSCALE), + 6 => Some(MUXNEG_A::BANDGAP), + _ => None, + } + } + #[doc = "Checks if the value of the field is `PIN0`"] + #[inline(always)] + pub fn is_pin0(&self) -> bool { + **self == MUXNEG_A::PIN0 + } + #[doc = "Checks if the value of the field is `PIN1`"] + #[inline(always)] + pub fn is_pin1(&self) -> bool { + **self == MUXNEG_A::PIN1 + } + #[doc = "Checks if the value of the field is `PIN2`"] + #[inline(always)] + pub fn is_pin2(&self) -> bool { + **self == MUXNEG_A::PIN2 + } + #[doc = "Checks if the value of the field is `PIN3`"] + #[inline(always)] + pub fn is_pin3(&self) -> bool { + **self == MUXNEG_A::PIN3 + } + #[doc = "Checks if the value of the field is `GND`"] + #[inline(always)] + pub fn is_gnd(&self) -> bool { + **self == MUXNEG_A::GND + } + #[doc = "Checks if the value of the field is `VSCALE`"] + #[inline(always)] + pub fn is_vscale(&self) -> bool { + **self == MUXNEG_A::VSCALE + } + #[doc = "Checks if the value of the field is `BANDGAP`"] + #[inline(always)] + pub fn is_bandgap(&self) -> bool { + **self == MUXNEG_A::BANDGAP + } +} +impl core::ops::Deref for MUXNEG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MUXNEG` writer - Negative Input Mux Selection"] +pub struct MUXNEG_W<'a> { + w: &'a mut W, +} +impl<'a> MUXNEG_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MUXNEG_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "I/O pin 0"] + #[inline(always)] + pub fn pin0(self) -> &'a mut W { + self.variant(MUXNEG_A::PIN0) + } + #[doc = "I/O pin 1"] + #[inline(always)] + pub fn pin1(self) -> &'a mut W { + self.variant(MUXNEG_A::PIN1) + } + #[doc = "I/O pin 2"] + #[inline(always)] + pub fn pin2(self) -> &'a mut W { + self.variant(MUXNEG_A::PIN2) + } + #[doc = "I/O pin 3"] + #[inline(always)] + pub fn pin3(self) -> &'a mut W { + self.variant(MUXNEG_A::PIN3) + } + #[doc = "Ground"] + #[inline(always)] + pub fn gnd(self) -> &'a mut W { + self.variant(MUXNEG_A::GND) + } + #[doc = "VDD scaler"] + #[inline(always)] + pub fn vscale(self) -> &'a mut W { + self.variant(MUXNEG_A::VSCALE) + } + #[doc = "Internal bandgap voltage"] + #[inline(always)] + pub fn bandgap(self) -> &'a mut W { + self.variant(MUXNEG_A::BANDGAP) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +#[doc = "Positive Input Mux Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MUXPOS_A { + #[doc = "0: I/O pin 0"] + PIN0 = 0, + #[doc = "1: I/O pin 1"] + PIN1 = 1, + #[doc = "2: I/O pin 2"] + PIN2 = 2, + #[doc = "3: I/O pin 3"] + PIN3 = 3, + #[doc = "4: VDD Scaler"] + VSCALE = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MUXPOS_A) -> Self { + variant as _ + } +} +#[doc = "Field `MUXPOS` reader - Positive Input Mux Selection"] +pub struct MUXPOS_R(crate::FieldReader); +impl MUXPOS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MUXPOS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MUXPOS_A::PIN0), + 1 => Some(MUXPOS_A::PIN1), + 2 => Some(MUXPOS_A::PIN2), + 3 => Some(MUXPOS_A::PIN3), + 4 => Some(MUXPOS_A::VSCALE), + _ => None, + } + } + #[doc = "Checks if the value of the field is `PIN0`"] + #[inline(always)] + pub fn is_pin0(&self) -> bool { + **self == MUXPOS_A::PIN0 + } + #[doc = "Checks if the value of the field is `PIN1`"] + #[inline(always)] + pub fn is_pin1(&self) -> bool { + **self == MUXPOS_A::PIN1 + } + #[doc = "Checks if the value of the field is `PIN2`"] + #[inline(always)] + pub fn is_pin2(&self) -> bool { + **self == MUXPOS_A::PIN2 + } + #[doc = "Checks if the value of the field is `PIN3`"] + #[inline(always)] + pub fn is_pin3(&self) -> bool { + **self == MUXPOS_A::PIN3 + } + #[doc = "Checks if the value of the field is `VSCALE`"] + #[inline(always)] + pub fn is_vscale(&self) -> bool { + **self == MUXPOS_A::VSCALE + } +} +impl core::ops::Deref for MUXPOS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MUXPOS` writer - Positive Input Mux Selection"] +pub struct MUXPOS_W<'a> { + w: &'a mut W, +} +impl<'a> MUXPOS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MUXPOS_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "I/O pin 0"] + #[inline(always)] + pub fn pin0(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN0) + } + #[doc = "I/O pin 1"] + #[inline(always)] + pub fn pin1(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN1) + } + #[doc = "I/O pin 2"] + #[inline(always)] + pub fn pin2(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN2) + } + #[doc = "I/O pin 3"] + #[inline(always)] + pub fn pin3(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN3) + } + #[doc = "VDD Scaler"] + #[inline(always)] + pub fn vscale(self) -> &'a mut W { + self.variant(MUXPOS_A::VSCALE) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 12)) | ((value as u32 & 0x07) << 12); + self.w + } +} +#[doc = "Field `SWAP` reader - Swap Inputs and Invert"] +pub struct SWAP_R(crate::FieldReader); +impl SWAP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWAP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWAP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWAP` writer - Swap Inputs and Invert"] +pub struct SWAP_W<'a> { + w: &'a mut W, +} +impl<'a> SWAP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Speed Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SPEED_A { + #[doc = "0: Low speed"] + LOW = 0, + #[doc = "3: High speed"] + HIGH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SPEED_A) -> Self { + variant as _ + } +} +#[doc = "Field `SPEED` reader - Speed Selection"] +pub struct SPEED_R(crate::FieldReader); +impl SPEED_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SPEED_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SPEED_A::LOW), + 3 => Some(SPEED_A::HIGH), + _ => None, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SPEED_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SPEED_A::HIGH + } +} +impl core::ops::Deref for SPEED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SPEED` writer - Speed Selection"] +pub struct SPEED_W<'a> { + w: &'a mut W, +} +impl<'a> SPEED_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SPEED_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Low speed"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SPEED_A::LOW) + } + #[doc = "High speed"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SPEED_A::HIGH) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Field `HYSTEN` reader - Hysteresis Enable"] +pub struct HYSTEN_R(crate::FieldReader); +impl HYSTEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HYSTEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HYSTEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HYSTEN` writer - Hysteresis Enable"] +pub struct HYSTEN_W<'a> { + w: &'a mut W, +} +impl<'a> HYSTEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Filter Length\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FLEN_A { + #[doc = "0: No filtering"] + OFF = 0, + #[doc = "1: 3-bit majority function (2 of 3)"] + MAJ3 = 1, + #[doc = "2: 5-bit majority function (3 of 5)"] + MAJ5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FLEN_A) -> Self { + variant as _ + } +} +#[doc = "Field `FLEN` reader - Filter Length"] +pub struct FLEN_R(crate::FieldReader); +impl FLEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FLEN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(FLEN_A::OFF), + 1 => Some(FLEN_A::MAJ3), + 2 => Some(FLEN_A::MAJ5), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == FLEN_A::OFF + } + #[doc = "Checks if the value of the field is `MAJ3`"] + #[inline(always)] + pub fn is_maj3(&self) -> bool { + **self == FLEN_A::MAJ3 + } + #[doc = "Checks if the value of the field is `MAJ5`"] + #[inline(always)] + pub fn is_maj5(&self) -> bool { + **self == FLEN_A::MAJ5 + } +} +impl core::ops::Deref for FLEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLEN` writer - Filter Length"] +pub struct FLEN_W<'a> { + w: &'a mut W, +} +impl<'a> FLEN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FLEN_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No filtering"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(FLEN_A::OFF) + } + #[doc = "3-bit majority function (2 of 3)"] + #[inline(always)] + pub fn maj3(self) -> &'a mut W { + self.variant(FLEN_A::MAJ3) + } + #[doc = "5-bit majority function (3 of 5)"] + #[inline(always)] + pub fn maj5(self) -> &'a mut W { + self.variant(FLEN_A::MAJ5) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 24)) | ((value as u32 & 0x07) << 24); + self.w + } +} +#[doc = "Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum OUT_A { + #[doc = "0: The output of COMPn is not routed to the COMPn I/O port"] + OFF = 0, + #[doc = "1: The asynchronous output of COMPn is routed to the COMPn I/O port"] + ASYNC = 1, + #[doc = "2: The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port"] + SYNC = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: OUT_A) -> Self { + variant as _ + } +} +#[doc = "Field `OUT` reader - Output"] +pub struct OUT_R(crate::FieldReader); +impl OUT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + OUT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(OUT_A::OFF), + 1 => Some(OUT_A::ASYNC), + 2 => Some(OUT_A::SYNC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == OUT_A::OFF + } + #[doc = "Checks if the value of the field is `ASYNC`"] + #[inline(always)] + pub fn is_async(&self) -> bool { + **self == OUT_A::ASYNC + } + #[doc = "Checks if the value of the field is `SYNC`"] + #[inline(always)] + pub fn is_sync(&self) -> bool { + **self == OUT_A::SYNC + } +} +impl core::ops::Deref for OUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OUT` writer - Output"] +pub struct OUT_W<'a> { + w: &'a mut W, +} +impl<'a> OUT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: OUT_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "The output of COMPn is not routed to the COMPn I/O port"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(OUT_A::OFF) + } + #[doc = "The asynchronous output of COMPn is routed to the COMPn I/O port"] + #[inline(always)] + pub fn async_(self) -> &'a mut W { + self.variant(OUT_A::ASYNC) + } + #[doc = "The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port"] + #[inline(always)] + pub fn sync(self) -> &'a mut W { + self.variant(OUT_A::SYNC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 28)) | ((value as u32 & 0x03) << 28); + self.w + } +} +impl R { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Single-Shot Mode"] + #[inline(always)] + pub fn single(&self) -> SINGLE_R { + SINGLE_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 3:4 - Interrupt Selection"] + #[inline(always)] + pub fn intsel(&self) -> INTSEL_R { + INTSEL_R::new(((self.bits >> 3) & 0x03) as u8) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Negative Input Mux Selection"] + #[inline(always)] + pub fn muxneg(&self) -> MUXNEG_R { + MUXNEG_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bits 12:14 - Positive Input Mux Selection"] + #[inline(always)] + pub fn muxpos(&self) -> MUXPOS_R { + MUXPOS_R::new(((self.bits >> 12) & 0x07) as u8) + } + #[doc = "Bit 15 - Swap Inputs and Invert"] + #[inline(always)] + pub fn swap(&self) -> SWAP_R { + SWAP_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:17 - Speed Selection"] + #[inline(always)] + pub fn speed(&self) -> SPEED_R { + SPEED_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bit 19 - Hysteresis Enable"] + #[inline(always)] + pub fn hysten(&self) -> HYSTEN_R { + HYSTEN_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bits 24:26 - Filter Length"] + #[inline(always)] + pub fn flen(&self) -> FLEN_R { + FLEN_R::new(((self.bits >> 24) & 0x07) as u8) + } + #[doc = "Bits 28:29 - Output"] + #[inline(always)] + pub fn out(&self) -> OUT_R { + OUT_R::new(((self.bits >> 28) & 0x03) as u8) + } +} +impl W { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - Single-Shot Mode"] + #[inline(always)] + pub fn single(&mut self) -> SINGLE_W { + SINGLE_W { w: self } + } + #[doc = "Bits 3:4 - Interrupt Selection"] + #[inline(always)] + pub fn intsel(&mut self) -> INTSEL_W { + INTSEL_W { w: self } + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bits 8:10 - Negative Input Mux Selection"] + #[inline(always)] + pub fn muxneg(&mut self) -> MUXNEG_W { + MUXNEG_W { w: self } + } + #[doc = "Bits 12:14 - Positive Input Mux Selection"] + #[inline(always)] + pub fn muxpos(&mut self) -> MUXPOS_W { + MUXPOS_W { w: self } + } + #[doc = "Bit 15 - Swap Inputs and Invert"] + #[inline(always)] + pub fn swap(&mut self) -> SWAP_W { + SWAP_W { w: self } + } + #[doc = "Bits 16:17 - Speed Selection"] + #[inline(always)] + pub fn speed(&mut self) -> SPEED_W { + SPEED_W { w: self } + } + #[doc = "Bit 19 - Hysteresis Enable"] + #[inline(always)] + pub fn hysten(&mut self) -> HYSTEN_W { + HYSTEN_W { w: self } + } + #[doc = "Bits 24:26 - Filter Length"] + #[inline(always)] + pub fn flen(&mut self) -> FLEN_W { + FLEN_W { w: self } + } + #[doc = "Bits 28:29 - Output"] + #[inline(always)] + pub fn out(&mut self) -> OUT_W { + OUT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Comparator Control n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [compctrl](index.html) module"] +pub struct COMPCTRL_SPEC; +impl crate::RegisterSpec for COMPCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [compctrl::R](R) reader structure"] +impl crate::Readable for COMPCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [compctrl::W](W) writer structure"] +impl crate::Writable for COMPCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COMPCTRL[%s] +to value 0"] +impl crate::Resettable for COMPCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/ac/ctrla.rs b/pac/atsamc20j/src/ac/ctrla.rs new file mode 100644 index 000000000000..5f2c406226f4 --- /dev/null +++ b/pac/atsamc20j/src/ac/ctrla.rs @@ -0,0 +1,160 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/ac/ctrlb.rs b/pac/atsamc20j/src/ac/ctrlb.rs new file mode 100644 index 000000000000..68aa8d2a20ba --- /dev/null +++ b/pac/atsamc20j/src/ac/ctrlb.rs @@ -0,0 +1,99 @@ +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `START0` writer - Comparator 0 Start Comparison"] +pub struct START0_W<'a> { + w: &'a mut W, +} +impl<'a> START0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `START1` writer - Comparator 1 Start Comparison"] +pub struct START1_W<'a> { + w: &'a mut W, +} +impl<'a> START1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl W { + #[doc = "Bit 0 - Comparator 0 Start Comparison"] + #[inline(always)] + pub fn start0(&mut self) -> START0_W { + START0_W { w: self } + } + #[doc = "Bit 1 - Comparator 1 Start Comparison"] + #[inline(always)] + pub fn start1(&mut self) -> START1_W { + START1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u8; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/ac/dbgctrl.rs b/pac/atsamc20j/src/ac/dbgctrl.rs new file mode 100644 index 000000000000..53636eb2b339 --- /dev/null +++ b/pac/atsamc20j/src/ac/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Debug Run"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Debug Run"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/ac/evctrl.rs b/pac/atsamc20j/src/ac/evctrl.rs new file mode 100644 index 000000000000..5e5e650d6de9 --- /dev/null +++ b/pac/atsamc20j/src/ac/evctrl.rs @@ -0,0 +1,395 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COMPEO0` reader - Comparator 0 Event Output Enable"] +pub struct COMPEO0_R(crate::FieldReader); +impl COMPEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPEO0` writer - Comparator 0 Event Output Enable"] +pub struct COMPEO0_W<'a> { + w: &'a mut W, +} +impl<'a> COMPEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `COMPEO1` reader - Comparator 1 Event Output Enable"] +pub struct COMPEO1_R(crate::FieldReader); +impl COMPEO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPEO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPEO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPEO1` writer - Comparator 1 Event Output Enable"] +pub struct COMPEO1_W<'a> { + w: &'a mut W, +} +impl<'a> COMPEO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WINEO0` reader - Window 0 Event Output Enable"] +pub struct WINEO0_R(crate::FieldReader); +impl WINEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINEO0` writer - Window 0 Event Output Enable"] +pub struct WINEO0_W<'a> { + w: &'a mut W, +} +impl<'a> WINEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `COMPEI0` reader - Comparator 0 Event Input Enable"] +pub struct COMPEI0_R(crate::FieldReader); +impl COMPEI0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPEI0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPEI0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPEI0` writer - Comparator 0 Event Input Enable"] +pub struct COMPEI0_W<'a> { + w: &'a mut W, +} +impl<'a> COMPEI0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `COMPEI1` reader - Comparator 1 Event Input Enable"] +pub struct COMPEI1_R(crate::FieldReader); +impl COMPEI1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPEI1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPEI1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPEI1` writer - Comparator 1 Event Input Enable"] +pub struct COMPEI1_W<'a> { + w: &'a mut W, +} +impl<'a> COMPEI1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `INVEI0` reader - Comparator 0 Input Event Invert Enable"] +pub struct INVEI0_R(crate::FieldReader); +impl INVEI0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEI0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEI0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEI0` writer - Comparator 0 Input Event Invert Enable"] +pub struct INVEI0_W<'a> { + w: &'a mut W, +} +impl<'a> INVEI0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u16 & 0x01) << 12); + self.w + } +} +#[doc = "Field `INVEI1` reader - Comparator 1 Input Event Invert Enable"] +pub struct INVEI1_R(crate::FieldReader); +impl INVEI1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEI1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEI1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEI1` writer - Comparator 1 Input Event Invert Enable"] +pub struct INVEI1_W<'a> { + w: &'a mut W, +} +impl<'a> INVEI1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u16 & 0x01) << 13); + self.w + } +} +impl R { + #[doc = "Bit 0 - Comparator 0 Event Output Enable"] + #[inline(always)] + pub fn compeo0(&self) -> COMPEO0_R { + COMPEO0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Comparator 1 Event Output Enable"] + #[inline(always)] + pub fn compeo1(&self) -> COMPEO1_R { + COMPEO1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - Window 0 Event Output Enable"] + #[inline(always)] + pub fn wineo0(&self) -> WINEO0_R { + WINEO0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 8 - Comparator 0 Event Input Enable"] + #[inline(always)] + pub fn compei0(&self) -> COMPEI0_R { + COMPEI0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Comparator 1 Event Input Enable"] + #[inline(always)] + pub fn compei1(&self) -> COMPEI1_R { + COMPEI1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 12 - Comparator 0 Input Event Invert Enable"] + #[inline(always)] + pub fn invei0(&self) -> INVEI0_R { + INVEI0_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Comparator 1 Input Event Invert Enable"] + #[inline(always)] + pub fn invei1(&self) -> INVEI1_R { + INVEI1_R::new(((self.bits >> 13) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Comparator 0 Event Output Enable"] + #[inline(always)] + pub fn compeo0(&mut self) -> COMPEO0_W { + COMPEO0_W { w: self } + } + #[doc = "Bit 1 - Comparator 1 Event Output Enable"] + #[inline(always)] + pub fn compeo1(&mut self) -> COMPEO1_W { + COMPEO1_W { w: self } + } + #[doc = "Bit 4 - Window 0 Event Output Enable"] + #[inline(always)] + pub fn wineo0(&mut self) -> WINEO0_W { + WINEO0_W { w: self } + } + #[doc = "Bit 8 - Comparator 0 Event Input Enable"] + #[inline(always)] + pub fn compei0(&mut self) -> COMPEI0_W { + COMPEI0_W { w: self } + } + #[doc = "Bit 9 - Comparator 1 Event Input Enable"] + #[inline(always)] + pub fn compei1(&mut self) -> COMPEI1_W { + COMPEI1_W { w: self } + } + #[doc = "Bit 12 - Comparator 0 Input Event Invert Enable"] + #[inline(always)] + pub fn invei0(&mut self) -> INVEI0_W { + INVEI0_W { w: self } + } + #[doc = "Bit 13 - Comparator 1 Input Event Invert Enable"] + #[inline(always)] + pub fn invei1(&mut self) -> INVEI1_W { + INVEI1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/ac/intenclr.rs b/pac/atsamc20j/src/ac/intenclr.rs new file mode 100644 index 000000000000..45e3320d293e --- /dev/null +++ b/pac/atsamc20j/src/ac/intenclr.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COMP0` reader - Comparator 0 Interrupt Enable"] +pub struct COMP0_R(crate::FieldReader); +impl COMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP0` writer - Comparator 0 Interrupt Enable"] +pub struct COMP0_W<'a> { + w: &'a mut W, +} +impl<'a> COMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `COMP1` reader - Comparator 1 Interrupt Enable"] +pub struct COMP1_R(crate::FieldReader); +impl COMP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP1` writer - Comparator 1 Interrupt Enable"] +pub struct COMP1_W<'a> { + w: &'a mut W, +} +impl<'a> COMP1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WIN0` reader - Window 0 Interrupt Enable"] +pub struct WIN0_R(crate::FieldReader); +impl WIN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WIN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WIN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WIN0` writer - Window 0 Interrupt Enable"] +pub struct WIN0_W<'a> { + w: &'a mut W, +} +impl<'a> WIN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +impl R { + #[doc = "Bit 0 - Comparator 0 Interrupt Enable"] + #[inline(always)] + pub fn comp0(&self) -> COMP0_R { + COMP0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Comparator 1 Interrupt Enable"] + #[inline(always)] + pub fn comp1(&self) -> COMP1_R { + COMP1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - Window 0 Interrupt Enable"] + #[inline(always)] + pub fn win0(&self) -> WIN0_R { + WIN0_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Comparator 0 Interrupt Enable"] + #[inline(always)] + pub fn comp0(&mut self) -> COMP0_W { + COMP0_W { w: self } + } + #[doc = "Bit 1 - Comparator 1 Interrupt Enable"] + #[inline(always)] + pub fn comp1(&mut self) -> COMP1_W { + COMP1_W { w: self } + } + #[doc = "Bit 4 - Window 0 Interrupt Enable"] + #[inline(always)] + pub fn win0(&mut self) -> WIN0_W { + WIN0_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/ac/intenset.rs b/pac/atsamc20j/src/ac/intenset.rs new file mode 100644 index 000000000000..5354a4d111d0 --- /dev/null +++ b/pac/atsamc20j/src/ac/intenset.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COMP0` reader - Comparator 0 Interrupt Enable"] +pub struct COMP0_R(crate::FieldReader); +impl COMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP0` writer - Comparator 0 Interrupt Enable"] +pub struct COMP0_W<'a> { + w: &'a mut W, +} +impl<'a> COMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `COMP1` reader - Comparator 1 Interrupt Enable"] +pub struct COMP1_R(crate::FieldReader); +impl COMP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP1` writer - Comparator 1 Interrupt Enable"] +pub struct COMP1_W<'a> { + w: &'a mut W, +} +impl<'a> COMP1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WIN0` reader - Window 0 Interrupt Enable"] +pub struct WIN0_R(crate::FieldReader); +impl WIN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WIN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WIN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WIN0` writer - Window 0 Interrupt Enable"] +pub struct WIN0_W<'a> { + w: &'a mut W, +} +impl<'a> WIN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +impl R { + #[doc = "Bit 0 - Comparator 0 Interrupt Enable"] + #[inline(always)] + pub fn comp0(&self) -> COMP0_R { + COMP0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Comparator 1 Interrupt Enable"] + #[inline(always)] + pub fn comp1(&self) -> COMP1_R { + COMP1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - Window 0 Interrupt Enable"] + #[inline(always)] + pub fn win0(&self) -> WIN0_R { + WIN0_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Comparator 0 Interrupt Enable"] + #[inline(always)] + pub fn comp0(&mut self) -> COMP0_W { + COMP0_W { w: self } + } + #[doc = "Bit 1 - Comparator 1 Interrupt Enable"] + #[inline(always)] + pub fn comp1(&mut self) -> COMP1_W { + COMP1_W { w: self } + } + #[doc = "Bit 4 - Window 0 Interrupt Enable"] + #[inline(always)] + pub fn win0(&mut self) -> WIN0_W { + WIN0_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/ac/intflag.rs b/pac/atsamc20j/src/ac/intflag.rs new file mode 100644 index 000000000000..7da0fea7569f --- /dev/null +++ b/pac/atsamc20j/src/ac/intflag.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COMP0` reader - Comparator 0"] +pub struct COMP0_R(crate::FieldReader); +impl COMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP0` writer - Comparator 0"] +pub struct COMP0_W<'a> { + w: &'a mut W, +} +impl<'a> COMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `COMP1` reader - Comparator 1"] +pub struct COMP1_R(crate::FieldReader); +impl COMP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP1` writer - Comparator 1"] +pub struct COMP1_W<'a> { + w: &'a mut W, +} +impl<'a> COMP1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WIN0` reader - Window 0"] +pub struct WIN0_R(crate::FieldReader); +impl WIN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WIN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WIN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WIN0` writer - Window 0"] +pub struct WIN0_W<'a> { + w: &'a mut W, +} +impl<'a> WIN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +impl R { + #[doc = "Bit 0 - Comparator 0"] + #[inline(always)] + pub fn comp0(&self) -> COMP0_R { + COMP0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Comparator 1"] + #[inline(always)] + pub fn comp1(&self) -> COMP1_R { + COMP1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - Window 0"] + #[inline(always)] + pub fn win0(&self) -> WIN0_R { + WIN0_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Comparator 0"] + #[inline(always)] + pub fn comp0(&mut self) -> COMP0_W { + COMP0_W { w: self } + } + #[doc = "Bit 1 - Comparator 1"] + #[inline(always)] + pub fn comp1(&mut self) -> COMP1_W { + COMP1_W { w: self } + } + #[doc = "Bit 4 - Window 0"] + #[inline(always)] + pub fn win0(&mut self) -> WIN0_W { + WIN0_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/ac/scaler.rs b/pac/atsamc20j/src/ac/scaler.rs new file mode 100644 index 000000000000..091cacfaeb4b --- /dev/null +++ b/pac/atsamc20j/src/ac/scaler.rs @@ -0,0 +1,104 @@ +#[doc = "Register `SCALER[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SCALER[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `VALUE` reader - Scaler Value"] +pub struct VALUE_R(crate::FieldReader); +impl VALUE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + VALUE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VALUE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VALUE` writer - Scaler Value"] +pub struct VALUE_W<'a> { + w: &'a mut W, +} +impl<'a> VALUE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u8 & 0x3f); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Scaler Value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - Scaler Value"] + #[inline(always)] + pub fn value(&mut self) -> VALUE_W { + VALUE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Scaler n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [scaler](index.html) module"] +pub struct SCALER_SPEC; +impl crate::RegisterSpec for SCALER_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [scaler::R](R) reader structure"] +impl crate::Readable for SCALER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [scaler::W](W) writer structure"] +impl crate::Writable for SCALER_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SCALER[%s] +to value 0"] +impl crate::Resettable for SCALER_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/ac/statusa.rs b/pac/atsamc20j/src/ac/statusa.rs new file mode 100644 index 000000000000..7b98c567e8a6 --- /dev/null +++ b/pac/atsamc20j/src/ac/statusa.rs @@ -0,0 +1,135 @@ +#[doc = "Register `STATUSA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `STATE0` reader - Comparator 0 Current State"] +pub struct STATE0_R(crate::FieldReader); +impl STATE0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STATE0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STATE0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STATE1` reader - Comparator 1 Current State"] +pub struct STATE1_R(crate::FieldReader); +impl STATE1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STATE1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STATE1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Window 0 Current State\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WSTATE0_A { + #[doc = "0: Signal is above window"] + ABOVE = 0, + #[doc = "1: Signal is inside window"] + INSIDE = 1, + #[doc = "2: Signal is below window"] + BELOW = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WSTATE0_A) -> Self { + variant as _ + } +} +#[doc = "Field `WSTATE0` reader - Window 0 Current State"] +pub struct WSTATE0_R(crate::FieldReader); +impl WSTATE0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WSTATE0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(WSTATE0_A::ABOVE), + 1 => Some(WSTATE0_A::INSIDE), + 2 => Some(WSTATE0_A::BELOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `ABOVE`"] + #[inline(always)] + pub fn is_above(&self) -> bool { + **self == WSTATE0_A::ABOVE + } + #[doc = "Checks if the value of the field is `INSIDE`"] + #[inline(always)] + pub fn is_inside(&self) -> bool { + **self == WSTATE0_A::INSIDE + } + #[doc = "Checks if the value of the field is `BELOW`"] + #[inline(always)] + pub fn is_below(&self) -> bool { + **self == WSTATE0_A::BELOW + } +} +impl core::ops::Deref for WSTATE0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Comparator 0 Current State"] + #[inline(always)] + pub fn state0(&self) -> STATE0_R { + STATE0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Comparator 1 Current State"] + #[inline(always)] + pub fn state1(&self) -> STATE1_R { + STATE1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 4:5 - Window 0 Current State"] + #[inline(always)] + pub fn wstate0(&self) -> WSTATE0_R { + WSTATE0_R::new(((self.bits >> 4) & 0x03) as u8) + } +} +#[doc = "Status A\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [statusa](index.html) module"] +pub struct STATUSA_SPEC; +impl crate::RegisterSpec for STATUSA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [statusa::R](R) reader structure"] +impl crate::Readable for STATUSA_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUSA to value 0"] +impl crate::Resettable for STATUSA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/ac/statusb.rs b/pac/atsamc20j/src/ac/statusb.rs new file mode 100644 index 000000000000..dd27eb62fd27 --- /dev/null +++ b/pac/atsamc20j/src/ac/statusb.rs @@ -0,0 +1,73 @@ +#[doc = "Register `STATUSB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `READY0` reader - Comparator 0 Ready"] +pub struct READY0_R(crate::FieldReader); +impl READY0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + READY0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for READY0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `READY1` reader - Comparator 1 Ready"] +pub struct READY1_R(crate::FieldReader); +impl READY1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + READY1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for READY1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Comparator 0 Ready"] + #[inline(always)] + pub fn ready0(&self) -> READY0_R { + READY0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Comparator 1 Ready"] + #[inline(always)] + pub fn ready1(&self) -> READY1_R { + READY1_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +#[doc = "Status B\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [statusb](index.html) module"] +pub struct STATUSB_SPEC; +impl crate::RegisterSpec for STATUSB_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [statusb::R](R) reader structure"] +impl crate::Readable for STATUSB_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUSB to value 0"] +impl crate::Resettable for STATUSB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/ac/syncbusy.rs b/pac/atsamc20j/src/ac/syncbusy.rs new file mode 100644 index 000000000000..f3f2b1f4f1a6 --- /dev/null +++ b/pac/atsamc20j/src/ac/syncbusy.rs @@ -0,0 +1,133 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - Enable Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINCTRL` reader - WINCTRL Synchronization Busy"] +pub struct WINCTRL_R(crate::FieldReader); +impl WINCTRL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINCTRL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINCTRL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPCTRL0` reader - COMPCTRL 0 Synchronization Busy"] +pub struct COMPCTRL0_R(crate::FieldReader); +impl COMPCTRL0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPCTRL0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPCTRL0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPCTRL1` reader - COMPCTRL 1 Synchronization Busy"] +pub struct COMPCTRL1_R(crate::FieldReader); +impl COMPCTRL1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPCTRL1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPCTRL1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - WINCTRL Synchronization Busy"] + #[inline(always)] + pub fn winctrl(&self) -> WINCTRL_R { + WINCTRL_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - COMPCTRL 0 Synchronization Busy"] + #[inline(always)] + pub fn compctrl0(&self) -> COMPCTRL0_R { + COMPCTRL0_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - COMPCTRL 1 Synchronization Busy"] + #[inline(always)] + pub fn compctrl1(&self) -> COMPCTRL1_R { + COMPCTRL1_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +#[doc = "Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/ac/winctrl.rs b/pac/atsamc20j/src/ac/winctrl.rs new file mode 100644 index 000000000000..3259570489e0 --- /dev/null +++ b/pac/atsamc20j/src/ac/winctrl.rs @@ -0,0 +1,225 @@ +#[doc = "Register `WINCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WINCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WEN0` reader - Window 0 Mode Enable"] +pub struct WEN0_R(crate::FieldReader); +impl WEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WEN0` writer - Window 0 Mode Enable"] +pub struct WEN0_W<'a> { + w: &'a mut W, +} +impl<'a> WEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Window 0 Interrupt Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WINTSEL0_A { + #[doc = "0: Interrupt on signal above window"] + ABOVE = 0, + #[doc = "1: Interrupt on signal inside window"] + INSIDE = 1, + #[doc = "2: Interrupt on signal below window"] + BELOW = 2, + #[doc = "3: Interrupt on signal outside window"] + OUTSIDE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WINTSEL0_A) -> Self { + variant as _ + } +} +#[doc = "Field `WINTSEL0` reader - Window 0 Interrupt Selection"] +pub struct WINTSEL0_R(crate::FieldReader); +impl WINTSEL0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WINTSEL0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> WINTSEL0_A { + match self.bits { + 0 => WINTSEL0_A::ABOVE, + 1 => WINTSEL0_A::INSIDE, + 2 => WINTSEL0_A::BELOW, + 3 => WINTSEL0_A::OUTSIDE, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `ABOVE`"] + #[inline(always)] + pub fn is_above(&self) -> bool { + **self == WINTSEL0_A::ABOVE + } + #[doc = "Checks if the value of the field is `INSIDE`"] + #[inline(always)] + pub fn is_inside(&self) -> bool { + **self == WINTSEL0_A::INSIDE + } + #[doc = "Checks if the value of the field is `BELOW`"] + #[inline(always)] + pub fn is_below(&self) -> bool { + **self == WINTSEL0_A::BELOW + } + #[doc = "Checks if the value of the field is `OUTSIDE`"] + #[inline(always)] + pub fn is_outside(&self) -> bool { + **self == WINTSEL0_A::OUTSIDE + } +} +impl core::ops::Deref for WINTSEL0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINTSEL0` writer - Window 0 Interrupt Selection"] +pub struct WINTSEL0_W<'a> { + w: &'a mut W, +} +impl<'a> WINTSEL0_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WINTSEL0_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Interrupt on signal above window"] + #[inline(always)] + pub fn above(self) -> &'a mut W { + self.variant(WINTSEL0_A::ABOVE) + } + #[doc = "Interrupt on signal inside window"] + #[inline(always)] + pub fn inside(self) -> &'a mut W { + self.variant(WINTSEL0_A::INSIDE) + } + #[doc = "Interrupt on signal below window"] + #[inline(always)] + pub fn below(self) -> &'a mut W { + self.variant(WINTSEL0_A::BELOW) + } + #[doc = "Interrupt on signal outside window"] + #[inline(always)] + pub fn outside(self) -> &'a mut W { + self.variant(WINTSEL0_A::OUTSIDE) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 1)) | ((value as u8 & 0x03) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - Window 0 Mode Enable"] + #[inline(always)] + pub fn wen0(&self) -> WEN0_R { + WEN0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bits 1:2 - Window 0 Interrupt Selection"] + #[inline(always)] + pub fn wintsel0(&self) -> WINTSEL0_R { + WINTSEL0_R::new(((self.bits >> 1) & 0x03) as u8) + } +} +impl W { + #[doc = "Bit 0 - Window 0 Mode Enable"] + #[inline(always)] + pub fn wen0(&mut self) -> WEN0_W { + WEN0_W { w: self } + } + #[doc = "Bits 1:2 - Window 0 Interrupt Selection"] + #[inline(always)] + pub fn wintsel0(&mut self) -> WINTSEL0_W { + WINTSEL0_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Window Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [winctrl](index.html) module"] +pub struct WINCTRL_SPEC; +impl crate::RegisterSpec for WINCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [winctrl::R](R) reader structure"] +impl crate::Readable for WINCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [winctrl::W](W) writer structure"] +impl crate::Writable for WINCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WINCTRL to value 0"] +impl crate::Resettable for WINCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/adc0.rs b/pac/atsamc20j/src/adc0.rs new file mode 100644 index 000000000000..453f56ed28c8 --- /dev/null +++ b/pac/atsamc20j/src/adc0.rs @@ -0,0 +1,141 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + #[doc = "0x01 - Control B"] + pub ctrlb: crate::Reg, + #[doc = "0x02 - Reference Control"] + pub refctrl: crate::Reg, + #[doc = "0x03 - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x04 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x05 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x06 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x07 - Sequence Status"] + pub seqstatus: crate::Reg, + #[doc = "0x08 - Input Control"] + pub inputctrl: crate::Reg, + #[doc = "0x0a - Control C"] + pub ctrlc: crate::Reg, + #[doc = "0x0c - Average Control"] + pub avgctrl: crate::Reg, + #[doc = "0x0d - Sample Time Control"] + pub sampctrl: crate::Reg, + #[doc = "0x0e - Window Monitor Lower Threshold"] + pub winlt: crate::Reg, + #[doc = "0x10 - Window Monitor Upper Threshold"] + pub winut: crate::Reg, + #[doc = "0x12 - Gain Correction"] + pub gaincorr: crate::Reg, + #[doc = "0x14 - Offset Correction"] + pub offsetcorr: crate::Reg, + _reserved16: [u8; 0x02], + #[doc = "0x18 - Software Trigger"] + pub swtrig: crate::Reg, + _reserved17: [u8; 0x03], + #[doc = "0x1c - Debug Control"] + pub dbgctrl: crate::Reg, + _reserved18: [u8; 0x03], + #[doc = "0x20 - Synchronization Busy"] + pub syncbusy: crate::Reg, + _reserved19: [u8; 0x02], + #[doc = "0x24 - Result"] + pub result: crate::Reg, + _reserved20: [u8; 0x02], + #[doc = "0x28 - Sequence Control"] + pub seqctrl: crate::Reg, + #[doc = "0x2c - Calibration"] + pub calib: crate::Reg, +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "Control B"] +pub mod ctrlb; +#[doc = "REFCTRL register accessor: an alias for `Reg`"] +pub type REFCTRL = crate::Reg; +#[doc = "Reference Control"] +pub mod refctrl; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "SEQSTATUS register accessor: an alias for `Reg`"] +pub type SEQSTATUS = crate::Reg; +#[doc = "Sequence Status"] +pub mod seqstatus; +#[doc = "INPUTCTRL register accessor: an alias for `Reg`"] +pub type INPUTCTRL = crate::Reg; +#[doc = "Input Control"] +pub mod inputctrl; +#[doc = "CTRLC register accessor: an alias for `Reg`"] +pub type CTRLC = crate::Reg; +#[doc = "Control C"] +pub mod ctrlc; +#[doc = "AVGCTRL register accessor: an alias for `Reg`"] +pub type AVGCTRL = crate::Reg; +#[doc = "Average Control"] +pub mod avgctrl; +#[doc = "SAMPCTRL register accessor: an alias for `Reg`"] +pub type SAMPCTRL = crate::Reg; +#[doc = "Sample Time Control"] +pub mod sampctrl; +#[doc = "WINLT register accessor: an alias for `Reg`"] +pub type WINLT = crate::Reg; +#[doc = "Window Monitor Lower Threshold"] +pub mod winlt; +#[doc = "WINUT register accessor: an alias for `Reg`"] +pub type WINUT = crate::Reg; +#[doc = "Window Monitor Upper Threshold"] +pub mod winut; +#[doc = "GAINCORR register accessor: an alias for `Reg`"] +pub type GAINCORR = crate::Reg; +#[doc = "Gain Correction"] +pub mod gaincorr; +#[doc = "OFFSETCORR register accessor: an alias for `Reg`"] +pub type OFFSETCORR = crate::Reg; +#[doc = "Offset Correction"] +pub mod offsetcorr; +#[doc = "SWTRIG register accessor: an alias for `Reg`"] +pub type SWTRIG = crate::Reg; +#[doc = "Software Trigger"] +pub mod swtrig; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Busy"] +pub mod syncbusy; +#[doc = "RESULT register accessor: an alias for `Reg`"] +pub type RESULT = crate::Reg; +#[doc = "Result"] +pub mod result; +#[doc = "SEQCTRL register accessor: an alias for `Reg`"] +pub type SEQCTRL = crate::Reg; +#[doc = "Sequence Control"] +pub mod seqctrl; +#[doc = "CALIB register accessor: an alias for `Reg`"] +pub type CALIB = crate::Reg; +#[doc = "Calibration"] +pub mod calib; diff --git a/pac/atsamc20j/src/adc0/avgctrl.rs b/pac/atsamc20j/src/adc0/avgctrl.rs new file mode 100644 index 000000000000..ddb735715c98 --- /dev/null +++ b/pac/atsamc20j/src/adc0/avgctrl.rs @@ -0,0 +1,306 @@ +#[doc = "Register `AVGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `AVGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Number of Samples to be Collected\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SAMPLENUM_A { + #[doc = "0: 1 sample"] + _1 = 0, + #[doc = "1: 2 samples"] + _2 = 1, + #[doc = "2: 4 samples"] + _4 = 2, + #[doc = "3: 8 samples"] + _8 = 3, + #[doc = "4: 16 samples"] + _16 = 4, + #[doc = "5: 32 samples"] + _32 = 5, + #[doc = "6: 64 samples"] + _64 = 6, + #[doc = "7: 128 samples"] + _128 = 7, + #[doc = "8: 256 samples"] + _256 = 8, + #[doc = "9: 512 samples"] + _512 = 9, + #[doc = "10: 1024 samples"] + _1024 = 10, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SAMPLENUM_A) -> Self { + variant as _ + } +} +#[doc = "Field `SAMPLENUM` reader - Number of Samples to be Collected"] +pub struct SAMPLENUM_R(crate::FieldReader); +impl SAMPLENUM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SAMPLENUM_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SAMPLENUM_A::_1), + 1 => Some(SAMPLENUM_A::_2), + 2 => Some(SAMPLENUM_A::_4), + 3 => Some(SAMPLENUM_A::_8), + 4 => Some(SAMPLENUM_A::_16), + 5 => Some(SAMPLENUM_A::_32), + 6 => Some(SAMPLENUM_A::_64), + 7 => Some(SAMPLENUM_A::_128), + 8 => Some(SAMPLENUM_A::_256), + 9 => Some(SAMPLENUM_A::_512), + 10 => Some(SAMPLENUM_A::_1024), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_1`"] + #[inline(always)] + pub fn is_1(&self) -> bool { + **self == SAMPLENUM_A::_1 + } + #[doc = "Checks if the value of the field is `_2`"] + #[inline(always)] + pub fn is_2(&self) -> bool { + **self == SAMPLENUM_A::_2 + } + #[doc = "Checks if the value of the field is `_4`"] + #[inline(always)] + pub fn is_4(&self) -> bool { + **self == SAMPLENUM_A::_4 + } + #[doc = "Checks if the value of the field is `_8`"] + #[inline(always)] + pub fn is_8(&self) -> bool { + **self == SAMPLENUM_A::_8 + } + #[doc = "Checks if the value of the field is `_16`"] + #[inline(always)] + pub fn is_16(&self) -> bool { + **self == SAMPLENUM_A::_16 + } + #[doc = "Checks if the value of the field is `_32`"] + #[inline(always)] + pub fn is_32(&self) -> bool { + **self == SAMPLENUM_A::_32 + } + #[doc = "Checks if the value of the field is `_64`"] + #[inline(always)] + pub fn is_64(&self) -> bool { + **self == SAMPLENUM_A::_64 + } + #[doc = "Checks if the value of the field is `_128`"] + #[inline(always)] + pub fn is_128(&self) -> bool { + **self == SAMPLENUM_A::_128 + } + #[doc = "Checks if the value of the field is `_256`"] + #[inline(always)] + pub fn is_256(&self) -> bool { + **self == SAMPLENUM_A::_256 + } + #[doc = "Checks if the value of the field is `_512`"] + #[inline(always)] + pub fn is_512(&self) -> bool { + **self == SAMPLENUM_A::_512 + } + #[doc = "Checks if the value of the field is `_1024`"] + #[inline(always)] + pub fn is_1024(&self) -> bool { + **self == SAMPLENUM_A::_1024 + } +} +impl core::ops::Deref for SAMPLENUM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SAMPLENUM` writer - Number of Samples to be Collected"] +pub struct SAMPLENUM_W<'a> { + w: &'a mut W, +} +impl<'a> SAMPLENUM_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SAMPLENUM_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "1 sample"] + #[inline(always)] + pub fn _1(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_1) + } + #[doc = "2 samples"] + #[inline(always)] + pub fn _2(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_2) + } + #[doc = "4 samples"] + #[inline(always)] + pub fn _4(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_4) + } + #[doc = "8 samples"] + #[inline(always)] + pub fn _8(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_8) + } + #[doc = "16 samples"] + #[inline(always)] + pub fn _16(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_16) + } + #[doc = "32 samples"] + #[inline(always)] + pub fn _32(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_32) + } + #[doc = "64 samples"] + #[inline(always)] + pub fn _64(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_64) + } + #[doc = "128 samples"] + #[inline(always)] + pub fn _128(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_128) + } + #[doc = "256 samples"] + #[inline(always)] + pub fn _256(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_256) + } + #[doc = "512 samples"] + #[inline(always)] + pub fn _512(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_512) + } + #[doc = "1024 samples"] + #[inline(always)] + pub fn _1024(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +#[doc = "Field `ADJRES` reader - Adjusting Result / Division Coefficient"] +pub struct ADJRES_R(crate::FieldReader); +impl ADJRES_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ADJRES_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADJRES_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADJRES` writer - Adjusting Result / Division Coefficient"] +pub struct ADJRES_W<'a> { + w: &'a mut W, +} +impl<'a> ADJRES_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 4)) | ((value as u8 & 0x07) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Number of Samples to be Collected"] + #[inline(always)] + pub fn samplenum(&self) -> SAMPLENUM_R { + SAMPLENUM_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:6 - Adjusting Result / Division Coefficient"] + #[inline(always)] + pub fn adjres(&self) -> ADJRES_R { + ADJRES_R::new(((self.bits >> 4) & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Number of Samples to be Collected"] + #[inline(always)] + pub fn samplenum(&mut self) -> SAMPLENUM_W { + SAMPLENUM_W { w: self } + } + #[doc = "Bits 4:6 - Adjusting Result / Division Coefficient"] + #[inline(always)] + pub fn adjres(&mut self) -> ADJRES_W { + ADJRES_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Average Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [avgctrl](index.html) module"] +pub struct AVGCTRL_SPEC; +impl crate::RegisterSpec for AVGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [avgctrl::R](R) reader structure"] +impl crate::Readable for AVGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [avgctrl::W](W) writer structure"] +impl crate::Writable for AVGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets AVGCTRL to value 0"] +impl crate::Resettable for AVGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/adc0/calib.rs b/pac/atsamc20j/src/adc0/calib.rs new file mode 100644 index 000000000000..8a1a99b8c47d --- /dev/null +++ b/pac/atsamc20j/src/adc0/calib.rs @@ -0,0 +1,140 @@ +#[doc = "Register `CALIB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CALIB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BIASCOMP` reader - Bias Comparator Scaling"] +pub struct BIASCOMP_R(crate::FieldReader); +impl BIASCOMP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BIASCOMP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BIASCOMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BIASCOMP` writer - Bias Comparator Scaling"] +pub struct BIASCOMP_W<'a> { + w: &'a mut W, +} +impl<'a> BIASCOMP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u16 & 0x07); + self.w + } +} +#[doc = "Field `BIASREFBUF` reader - Bias Reference Buffer Scaling"] +pub struct BIASREFBUF_R(crate::FieldReader); +impl BIASREFBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BIASREFBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BIASREFBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BIASREFBUF` writer - Bias Reference Buffer Scaling"] +pub struct BIASREFBUF_W<'a> { + w: &'a mut W, +} +impl<'a> BIASREFBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u16 & 0x07) << 8); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Bias Comparator Scaling"] + #[inline(always)] + pub fn biascomp(&self) -> BIASCOMP_R { + BIASCOMP_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bits 8:10 - Bias Reference Buffer Scaling"] + #[inline(always)] + pub fn biasrefbuf(&self) -> BIASREFBUF_R { + BIASREFBUF_R::new(((self.bits >> 8) & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Bias Comparator Scaling"] + #[inline(always)] + pub fn biascomp(&mut self) -> BIASCOMP_W { + BIASCOMP_W { w: self } + } + #[doc = "Bits 8:10 - Bias Reference Buffer Scaling"] + #[inline(always)] + pub fn biasrefbuf(&mut self) -> BIASREFBUF_W { + BIASREFBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Calibration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [calib](index.html) module"] +pub struct CALIB_SPEC; +impl crate::RegisterSpec for CALIB_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [calib::R](R) reader structure"] +impl crate::Readable for CALIB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [calib::W](W) writer structure"] +impl crate::Writable for CALIB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CALIB to value 0"] +impl crate::Resettable for CALIB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/adc0/ctrla.rs b/pac/atsamc20j/src/adc0/ctrla.rs new file mode 100644 index 000000000000..47c681045f95 --- /dev/null +++ b/pac/atsamc20j/src/adc0/ctrla.rs @@ -0,0 +1,301 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SLAVEEN` reader - Slave Enable"] +pub struct SLAVEEN_R(crate::FieldReader); +impl SLAVEEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLAVEEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SLAVEEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLAVEEN` writer - Slave Enable"] +pub struct SLAVEEN_W<'a> { + w: &'a mut W, +} +impl<'a> SLAVEEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run During Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run During Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - On Demand Control"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - On Demand Control"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 5 - Slave Enable"] + #[inline(always)] + pub fn slaveen(&self) -> SLAVEEN_R { + SLAVEEN_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Run During Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 5 - Slave Enable"] + #[inline(always)] + pub fn slaveen(&mut self) -> SLAVEEN_W { + SLAVEEN_W { w: self } + } + #[doc = "Bit 6 - Run During Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/adc0/ctrlb.rs b/pac/atsamc20j/src/adc0/ctrlb.rs new file mode 100644 index 000000000000..4d39688fc975 --- /dev/null +++ b/pac/atsamc20j/src/adc0/ctrlb.rs @@ -0,0 +1,230 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Prescaler Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: Peripheral clock / 2"] + DIV2 = 0, + #[doc = "1: Peripheral clock / 4"] + DIV4 = 1, + #[doc = "2: Peripheral clock / 8"] + DIV8 = 2, + #[doc = "3: Peripheral clock / 16"] + DIV16 = 3, + #[doc = "4: Peripheral clock / 32"] + DIV32 = 4, + #[doc = "5: Peripheral clock / 64"] + DIV64 = 5, + #[doc = "6: Peripheral clock / 128"] + DIV128 = 6, + #[doc = "7: Peripheral clock / 256"] + DIV256 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler Configuration"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PRESCALER_A { + match self.bits { + 0 => PRESCALER_A::DIV2, + 1 => PRESCALER_A::DIV4, + 2 => PRESCALER_A::DIV8, + 3 => PRESCALER_A::DIV16, + 4 => PRESCALER_A::DIV32, + 5 => PRESCALER_A::DIV64, + 6 => PRESCALER_A::DIV128, + 7 => PRESCALER_A::DIV256, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == PRESCALER_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == PRESCALER_A::DIV128 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler Configuration"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Peripheral clock / 2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "Peripheral clock / 4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "Peripheral clock / 8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "Peripheral clock / 16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "Peripheral clock / 32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV32) + } + #[doc = "Peripheral clock / 64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "Peripheral clock / 128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV128) + } + #[doc = "Peripheral clock / 256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Prescaler Configuration"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Prescaler Configuration"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/adc0/ctrlc.rs b/pac/atsamc20j/src/adc0/ctrlc.rs new file mode 100644 index 000000000000..fa45a771545a --- /dev/null +++ b/pac/atsamc20j/src/adc0/ctrlc.rs @@ -0,0 +1,538 @@ +#[doc = "Register `CTRLC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIFFMODE` reader - Differential Mode"] +pub struct DIFFMODE_R(crate::FieldReader); +impl DIFFMODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIFFMODE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIFFMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIFFMODE` writer - Differential Mode"] +pub struct DIFFMODE_W<'a> { + w: &'a mut W, +} +impl<'a> DIFFMODE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `LEFTADJ` reader - Left-Adjusted Result"] +pub struct LEFTADJ_R(crate::FieldReader); +impl LEFTADJ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LEFTADJ_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LEFTADJ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LEFTADJ` writer - Left-Adjusted Result"] +pub struct LEFTADJ_W<'a> { + w: &'a mut W, +} +impl<'a> LEFTADJ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `FREERUN` reader - Free Running Mode"] +pub struct FREERUN_R(crate::FieldReader); +impl FREERUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FREERUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FREERUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FREERUN` writer - Free Running Mode"] +pub struct FREERUN_W<'a> { + w: &'a mut W, +} +impl<'a> FREERUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CORREN` reader - Digital Correction Logic Enable"] +pub struct CORREN_R(crate::FieldReader); +impl CORREN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CORREN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CORREN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CORREN` writer - Digital Correction Logic Enable"] +pub struct CORREN_W<'a> { + w: &'a mut W, +} +impl<'a> CORREN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Conversion Result Resolution\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum RESSEL_A { + #[doc = "0: 12-bit"] + _12BIT = 0, + #[doc = "1: 16-bit averaging mode"] + _16BIT = 1, + #[doc = "2: 10-bit"] + _10BIT = 2, + #[doc = "3: 8-bit"] + _8BIT = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RESSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `RESSEL` reader - Conversion Result Resolution"] +pub struct RESSEL_R(crate::FieldReader); +impl RESSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RESSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RESSEL_A { + match self.bits { + 0 => RESSEL_A::_12BIT, + 1 => RESSEL_A::_16BIT, + 2 => RESSEL_A::_10BIT, + 3 => RESSEL_A::_8BIT, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `_12BIT`"] + #[inline(always)] + pub fn is_12bit(&self) -> bool { + **self == RESSEL_A::_12BIT + } + #[doc = "Checks if the value of the field is `_16BIT`"] + #[inline(always)] + pub fn is_16bit(&self) -> bool { + **self == RESSEL_A::_16BIT + } + #[doc = "Checks if the value of the field is `_10BIT`"] + #[inline(always)] + pub fn is_10bit(&self) -> bool { + **self == RESSEL_A::_10BIT + } + #[doc = "Checks if the value of the field is `_8BIT`"] + #[inline(always)] + pub fn is_8bit(&self) -> bool { + **self == RESSEL_A::_8BIT + } +} +impl core::ops::Deref for RESSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESSEL` writer - Conversion Result Resolution"] +pub struct RESSEL_W<'a> { + w: &'a mut W, +} +impl<'a> RESSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RESSEL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "12-bit"] + #[inline(always)] + pub fn _12bit(self) -> &'a mut W { + self.variant(RESSEL_A::_12BIT) + } + #[doc = "16-bit averaging mode"] + #[inline(always)] + pub fn _16bit(self) -> &'a mut W { + self.variant(RESSEL_A::_16BIT) + } + #[doc = "10-bit"] + #[inline(always)] + pub fn _10bit(self) -> &'a mut W { + self.variant(RESSEL_A::_10BIT) + } + #[doc = "8-bit"] + #[inline(always)] + pub fn _8bit(self) -> &'a mut W { + self.variant(RESSEL_A::_8BIT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u16 & 0x03) << 4); + self.w + } +} +#[doc = "Field `R2R` reader - Rail-to-Rail mode enable"] +pub struct R2R_R(crate::FieldReader); +impl R2R_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + R2R_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for R2R_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `R2R` writer - Rail-to-Rail mode enable"] +pub struct R2R_W<'a> { + w: &'a mut W, +} +impl<'a> R2R_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Window Monitor Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WINMODE_A { + #[doc = "0: No window mode (default)"] + DISABLE = 0, + #[doc = "1: RESULT > WINLT"] + MODE1 = 1, + #[doc = "2: RESULT < WINUT"] + MODE2 = 2, + #[doc = "3: WINLT < RESULT < WINUT"] + MODE3 = 3, + #[doc = "4: !(WINLT < RESULT < WINUT)"] + MODE4 = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WINMODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `WINMODE` reader - Window Monitor Mode"] +pub struct WINMODE_R(crate::FieldReader); +impl WINMODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WINMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(WINMODE_A::DISABLE), + 1 => Some(WINMODE_A::MODE1), + 2 => Some(WINMODE_A::MODE2), + 3 => Some(WINMODE_A::MODE3), + 4 => Some(WINMODE_A::MODE4), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == WINMODE_A::DISABLE + } + #[doc = "Checks if the value of the field is `MODE1`"] + #[inline(always)] + pub fn is_mode1(&self) -> bool { + **self == WINMODE_A::MODE1 + } + #[doc = "Checks if the value of the field is `MODE2`"] + #[inline(always)] + pub fn is_mode2(&self) -> bool { + **self == WINMODE_A::MODE2 + } + #[doc = "Checks if the value of the field is `MODE3`"] + #[inline(always)] + pub fn is_mode3(&self) -> bool { + **self == WINMODE_A::MODE3 + } + #[doc = "Checks if the value of the field is `MODE4`"] + #[inline(always)] + pub fn is_mode4(&self) -> bool { + **self == WINMODE_A::MODE4 + } +} +impl core::ops::Deref for WINMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMODE` writer - Window Monitor Mode"] +pub struct WINMODE_W<'a> { + w: &'a mut W, +} +impl<'a> WINMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WINMODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No window mode (default)"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(WINMODE_A::DISABLE) + } + #[doc = "RESULT > WINLT"] + #[inline(always)] + pub fn mode1(self) -> &'a mut W { + self.variant(WINMODE_A::MODE1) + } + #[doc = "RESULT < WINUT"] + #[inline(always)] + pub fn mode2(self) -> &'a mut W { + self.variant(WINMODE_A::MODE2) + } + #[doc = "WINLT < RESULT < WINUT"] + #[inline(always)] + pub fn mode3(self) -> &'a mut W { + self.variant(WINMODE_A::MODE3) + } + #[doc = "!(WINLT < RESULT < WINUT)"] + #[inline(always)] + pub fn mode4(self) -> &'a mut W { + self.variant(WINMODE_A::MODE4) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u16 & 0x07) << 8); + self.w + } +} +impl R { + #[doc = "Bit 0 - Differential Mode"] + #[inline(always)] + pub fn diffmode(&self) -> DIFFMODE_R { + DIFFMODE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Left-Adjusted Result"] + #[inline(always)] + pub fn leftadj(&self) -> LEFTADJ_R { + LEFTADJ_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Free Running Mode"] + #[inline(always)] + pub fn freerun(&self) -> FREERUN_R { + FREERUN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Digital Correction Logic Enable"] + #[inline(always)] + pub fn corren(&self) -> CORREN_R { + CORREN_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bits 4:5 - Conversion Result Resolution"] + #[inline(always)] + pub fn ressel(&self) -> RESSEL_R { + RESSEL_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bit 7 - Rail-to-Rail mode enable"] + #[inline(always)] + pub fn r2r(&self) -> R2R_R { + R2R_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Window Monitor Mode"] + #[inline(always)] + pub fn winmode(&self) -> WINMODE_R { + WINMODE_R::new(((self.bits >> 8) & 0x07) as u8) + } +} +impl W { + #[doc = "Bit 0 - Differential Mode"] + #[inline(always)] + pub fn diffmode(&mut self) -> DIFFMODE_W { + DIFFMODE_W { w: self } + } + #[doc = "Bit 1 - Left-Adjusted Result"] + #[inline(always)] + pub fn leftadj(&mut self) -> LEFTADJ_W { + LEFTADJ_W { w: self } + } + #[doc = "Bit 2 - Free Running Mode"] + #[inline(always)] + pub fn freerun(&mut self) -> FREERUN_W { + FREERUN_W { w: self } + } + #[doc = "Bit 3 - Digital Correction Logic Enable"] + #[inline(always)] + pub fn corren(&mut self) -> CORREN_W { + CORREN_W { w: self } + } + #[doc = "Bits 4:5 - Conversion Result Resolution"] + #[inline(always)] + pub fn ressel(&mut self) -> RESSEL_W { + RESSEL_W { w: self } + } + #[doc = "Bit 7 - Rail-to-Rail mode enable"] + #[inline(always)] + pub fn r2r(&mut self) -> R2R_W { + R2R_W { w: self } + } + #[doc = "Bits 8:10 - Window Monitor Mode"] + #[inline(always)] + pub fn winmode(&mut self) -> WINMODE_W { + WINMODE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control C\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlc](index.html) module"] +pub struct CTRLC_SPEC; +impl crate::RegisterSpec for CTRLC_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrlc::R](R) reader structure"] +impl crate::Readable for CTRLC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlc::W](W) writer structure"] +impl crate::Writable for CTRLC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLC to value 0"] +impl crate::Resettable for CTRLC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/adc0/dbgctrl.rs b/pac/atsamc20j/src/adc0/dbgctrl.rs new file mode 100644 index 000000000000..53636eb2b339 --- /dev/null +++ b/pac/atsamc20j/src/adc0/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Debug Run"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Debug Run"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/adc0/evctrl.rs b/pac/atsamc20j/src/adc0/evctrl.rs new file mode 100644 index 000000000000..295508f82de3 --- /dev/null +++ b/pac/atsamc20j/src/adc0/evctrl.rs @@ -0,0 +1,348 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FLUSHEI` reader - Flush Event Input Enable"] +pub struct FLUSHEI_R(crate::FieldReader); +impl FLUSHEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FLUSHEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FLUSHEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLUSHEI` writer - Flush Event Input Enable"] +pub struct FLUSHEI_W<'a> { + w: &'a mut W, +} +impl<'a> FLUSHEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `STARTEI` reader - Start Conversion Event Input Enable"] +pub struct STARTEI_R(crate::FieldReader); +impl STARTEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STARTEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STARTEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STARTEI` writer - Start Conversion Event Input Enable"] +pub struct STARTEI_W<'a> { + w: &'a mut W, +} +impl<'a> STARTEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `FLUSHINV` reader - Flush Event Invert Enable"] +pub struct FLUSHINV_R(crate::FieldReader); +impl FLUSHINV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FLUSHINV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FLUSHINV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLUSHINV` writer - Flush Event Invert Enable"] +pub struct FLUSHINV_W<'a> { + w: &'a mut W, +} +impl<'a> FLUSHINV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `STARTINV` reader - Start Event Invert Enable"] +pub struct STARTINV_R(crate::FieldReader); +impl STARTINV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STARTINV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STARTINV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STARTINV` writer - Start Event Invert Enable"] +pub struct STARTINV_W<'a> { + w: &'a mut W, +} +impl<'a> STARTINV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `RESRDYEO` reader - Result Ready Event Out"] +pub struct RESRDYEO_R(crate::FieldReader); +impl RESRDYEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESRDYEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESRDYEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESRDYEO` writer - Result Ready Event Out"] +pub struct RESRDYEO_W<'a> { + w: &'a mut W, +} +impl<'a> RESRDYEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `WINMONEO` reader - Window Monitor Event Out"] +pub struct WINMONEO_R(crate::FieldReader); +impl WINMONEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINMONEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINMONEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMONEO` writer - Window Monitor Event Out"] +pub struct WINMONEO_W<'a> { + w: &'a mut W, +} +impl<'a> WINMONEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Flush Event Input Enable"] + #[inline(always)] + pub fn flushei(&self) -> FLUSHEI_R { + FLUSHEI_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Start Conversion Event Input Enable"] + #[inline(always)] + pub fn startei(&self) -> STARTEI_R { + STARTEI_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Flush Event Invert Enable"] + #[inline(always)] + pub fn flushinv(&self) -> FLUSHINV_R { + FLUSHINV_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Start Event Invert Enable"] + #[inline(always)] + pub fn startinv(&self) -> STARTINV_R { + STARTINV_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Result Ready Event Out"] + #[inline(always)] + pub fn resrdyeo(&self) -> RESRDYEO_R { + RESRDYEO_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Window Monitor Event Out"] + #[inline(always)] + pub fn winmoneo(&self) -> WINMONEO_R { + WINMONEO_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Flush Event Input Enable"] + #[inline(always)] + pub fn flushei(&mut self) -> FLUSHEI_W { + FLUSHEI_W { w: self } + } + #[doc = "Bit 1 - Start Conversion Event Input Enable"] + #[inline(always)] + pub fn startei(&mut self) -> STARTEI_W { + STARTEI_W { w: self } + } + #[doc = "Bit 2 - Flush Event Invert Enable"] + #[inline(always)] + pub fn flushinv(&mut self) -> FLUSHINV_W { + FLUSHINV_W { w: self } + } + #[doc = "Bit 3 - Start Event Invert Enable"] + #[inline(always)] + pub fn startinv(&mut self) -> STARTINV_W { + STARTINV_W { w: self } + } + #[doc = "Bit 4 - Result Ready Event Out"] + #[inline(always)] + pub fn resrdyeo(&mut self) -> RESRDYEO_W { + RESRDYEO_W { w: self } + } + #[doc = "Bit 5 - Window Monitor Event Out"] + #[inline(always)] + pub fn winmoneo(&mut self) -> WINMONEO_W { + WINMONEO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/adc0/gaincorr.rs b/pac/atsamc20j/src/adc0/gaincorr.rs new file mode 100644 index 000000000000..496cb8c6021c --- /dev/null +++ b/pac/atsamc20j/src/adc0/gaincorr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `GAINCORR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GAINCORR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `GAINCORR` reader - Gain Correction Value"] +pub struct GAINCORR_R(crate::FieldReader); +impl GAINCORR_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + GAINCORR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GAINCORR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GAINCORR` writer - Gain Correction Value"] +pub struct GAINCORR_W<'a> { + w: &'a mut W, +} +impl<'a> GAINCORR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0fff) | (value as u16 & 0x0fff); + self.w + } +} +impl R { + #[doc = "Bits 0:11 - Gain Correction Value"] + #[inline(always)] + pub fn gaincorr(&self) -> GAINCORR_R { + GAINCORR_R::new((self.bits & 0x0fff) as u16) + } +} +impl W { + #[doc = "Bits 0:11 - Gain Correction Value"] + #[inline(always)] + pub fn gaincorr(&mut self) -> GAINCORR_W { + GAINCORR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Gain Correction\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gaincorr](index.html) module"] +pub struct GAINCORR_SPEC; +impl crate::RegisterSpec for GAINCORR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [gaincorr::R](R) reader structure"] +impl crate::Readable for GAINCORR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gaincorr::W](W) writer structure"] +impl crate::Writable for GAINCORR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets GAINCORR to value 0"] +impl crate::Resettable for GAINCORR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/adc0/inputctrl.rs b/pac/atsamc20j/src/adc0/inputctrl.rs new file mode 100644 index 000000000000..e0bd7489b5a5 --- /dev/null +++ b/pac/atsamc20j/src/adc0/inputctrl.rs @@ -0,0 +1,472 @@ +#[doc = "Register `INPUTCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INPUTCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Positive Mux Input Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MUXPOS_A { + #[doc = "0: ADC AIN0 Pin"] + AIN0 = 0, + #[doc = "1: ADC AIN1 Pin"] + AIN1 = 1, + #[doc = "2: ADC AIN2 Pin"] + AIN2 = 2, + #[doc = "3: ADC AIN3 Pin"] + AIN3 = 3, + #[doc = "4: ADC AIN4 Pin"] + AIN4 = 4, + #[doc = "5: ADC AIN5 Pin"] + AIN5 = 5, + #[doc = "6: ADC AIN6 Pin"] + AIN6 = 6, + #[doc = "7: ADC AIN7 Pin"] + AIN7 = 7, + #[doc = "8: ADC AIN8 Pin"] + AIN8 = 8, + #[doc = "9: ADC AIN9 Pin"] + AIN9 = 9, + #[doc = "10: ADC AIN10 Pin"] + AIN10 = 10, + #[doc = "11: ADC AIN11 Pin"] + AIN11 = 11, + #[doc = "25: Bandgap Voltage"] + BANDGAP = 25, + #[doc = "26: 1/4 Scaled Core Supply"] + SCALEDCOREVCC = 26, + #[doc = "27: 1/4 Scaled I/O Supply"] + SCALEDIOVCC = 27, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MUXPOS_A) -> Self { + variant as _ + } +} +#[doc = "Field `MUXPOS` reader - Positive Mux Input Selection"] +pub struct MUXPOS_R(crate::FieldReader); +impl MUXPOS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MUXPOS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MUXPOS_A::AIN0), + 1 => Some(MUXPOS_A::AIN1), + 2 => Some(MUXPOS_A::AIN2), + 3 => Some(MUXPOS_A::AIN3), + 4 => Some(MUXPOS_A::AIN4), + 5 => Some(MUXPOS_A::AIN5), + 6 => Some(MUXPOS_A::AIN6), + 7 => Some(MUXPOS_A::AIN7), + 8 => Some(MUXPOS_A::AIN8), + 9 => Some(MUXPOS_A::AIN9), + 10 => Some(MUXPOS_A::AIN10), + 11 => Some(MUXPOS_A::AIN11), + 25 => Some(MUXPOS_A::BANDGAP), + 26 => Some(MUXPOS_A::SCALEDCOREVCC), + 27 => Some(MUXPOS_A::SCALEDIOVCC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `AIN0`"] + #[inline(always)] + pub fn is_ain0(&self) -> bool { + **self == MUXPOS_A::AIN0 + } + #[doc = "Checks if the value of the field is `AIN1`"] + #[inline(always)] + pub fn is_ain1(&self) -> bool { + **self == MUXPOS_A::AIN1 + } + #[doc = "Checks if the value of the field is `AIN2`"] + #[inline(always)] + pub fn is_ain2(&self) -> bool { + **self == MUXPOS_A::AIN2 + } + #[doc = "Checks if the value of the field is `AIN3`"] + #[inline(always)] + pub fn is_ain3(&self) -> bool { + **self == MUXPOS_A::AIN3 + } + #[doc = "Checks if the value of the field is `AIN4`"] + #[inline(always)] + pub fn is_ain4(&self) -> bool { + **self == MUXPOS_A::AIN4 + } + #[doc = "Checks if the value of the field is `AIN5`"] + #[inline(always)] + pub fn is_ain5(&self) -> bool { + **self == MUXPOS_A::AIN5 + } + #[doc = "Checks if the value of the field is `AIN6`"] + #[inline(always)] + pub fn is_ain6(&self) -> bool { + **self == MUXPOS_A::AIN6 + } + #[doc = "Checks if the value of the field is `AIN7`"] + #[inline(always)] + pub fn is_ain7(&self) -> bool { + **self == MUXPOS_A::AIN7 + } + #[doc = "Checks if the value of the field is `AIN8`"] + #[inline(always)] + pub fn is_ain8(&self) -> bool { + **self == MUXPOS_A::AIN8 + } + #[doc = "Checks if the value of the field is `AIN9`"] + #[inline(always)] + pub fn is_ain9(&self) -> bool { + **self == MUXPOS_A::AIN9 + } + #[doc = "Checks if the value of the field is `AIN10`"] + #[inline(always)] + pub fn is_ain10(&self) -> bool { + **self == MUXPOS_A::AIN10 + } + #[doc = "Checks if the value of the field is `AIN11`"] + #[inline(always)] + pub fn is_ain11(&self) -> bool { + **self == MUXPOS_A::AIN11 + } + #[doc = "Checks if the value of the field is `BANDGAP`"] + #[inline(always)] + pub fn is_bandgap(&self) -> bool { + **self == MUXPOS_A::BANDGAP + } + #[doc = "Checks if the value of the field is `SCALEDCOREVCC`"] + #[inline(always)] + pub fn is_scaledcorevcc(&self) -> bool { + **self == MUXPOS_A::SCALEDCOREVCC + } + #[doc = "Checks if the value of the field is `SCALEDIOVCC`"] + #[inline(always)] + pub fn is_scalediovcc(&self) -> bool { + **self == MUXPOS_A::SCALEDIOVCC + } +} +impl core::ops::Deref for MUXPOS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MUXPOS` writer - Positive Mux Input Selection"] +pub struct MUXPOS_W<'a> { + w: &'a mut W, +} +impl<'a> MUXPOS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MUXPOS_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "ADC AIN0 Pin"] + #[inline(always)] + pub fn ain0(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN0) + } + #[doc = "ADC AIN1 Pin"] + #[inline(always)] + pub fn ain1(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN1) + } + #[doc = "ADC AIN2 Pin"] + #[inline(always)] + pub fn ain2(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN2) + } + #[doc = "ADC AIN3 Pin"] + #[inline(always)] + pub fn ain3(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN3) + } + #[doc = "ADC AIN4 Pin"] + #[inline(always)] + pub fn ain4(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN4) + } + #[doc = "ADC AIN5 Pin"] + #[inline(always)] + pub fn ain5(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN5) + } + #[doc = "ADC AIN6 Pin"] + #[inline(always)] + pub fn ain6(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN6) + } + #[doc = "ADC AIN7 Pin"] + #[inline(always)] + pub fn ain7(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN7) + } + #[doc = "ADC AIN8 Pin"] + #[inline(always)] + pub fn ain8(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN8) + } + #[doc = "ADC AIN9 Pin"] + #[inline(always)] + pub fn ain9(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN9) + } + #[doc = "ADC AIN10 Pin"] + #[inline(always)] + pub fn ain10(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN10) + } + #[doc = "ADC AIN11 Pin"] + #[inline(always)] + pub fn ain11(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN11) + } + #[doc = "Bandgap Voltage"] + #[inline(always)] + pub fn bandgap(self) -> &'a mut W { + self.variant(MUXPOS_A::BANDGAP) + } + #[doc = "1/4 Scaled Core Supply"] + #[inline(always)] + pub fn scaledcorevcc(self) -> &'a mut W { + self.variant(MUXPOS_A::SCALEDCOREVCC) + } + #[doc = "1/4 Scaled I/O Supply"] + #[inline(always)] + pub fn scalediovcc(self) -> &'a mut W { + self.variant(MUXPOS_A::SCALEDIOVCC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u16 & 0x1f); + self.w + } +} +#[doc = "Negative Mux Input Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MUXNEG_A { + #[doc = "0: ADC AIN0 Pin"] + AIN0 = 0, + #[doc = "1: ADC AIN1 Pin"] + AIN1 = 1, + #[doc = "2: ADC AIN2 Pin"] + AIN2 = 2, + #[doc = "3: ADC AIN3 Pin"] + AIN3 = 3, + #[doc = "4: ADC AIN4 Pin"] + AIN4 = 4, + #[doc = "5: ADC AIN5 Pin"] + AIN5 = 5, + #[doc = "24: Internal Ground"] + GND = 24, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MUXNEG_A) -> Self { + variant as _ + } +} +#[doc = "Field `MUXNEG` reader - Negative Mux Input Selection"] +pub struct MUXNEG_R(crate::FieldReader); +impl MUXNEG_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MUXNEG_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MUXNEG_A::AIN0), + 1 => Some(MUXNEG_A::AIN1), + 2 => Some(MUXNEG_A::AIN2), + 3 => Some(MUXNEG_A::AIN3), + 4 => Some(MUXNEG_A::AIN4), + 5 => Some(MUXNEG_A::AIN5), + 24 => Some(MUXNEG_A::GND), + _ => None, + } + } + #[doc = "Checks if the value of the field is `AIN0`"] + #[inline(always)] + pub fn is_ain0(&self) -> bool { + **self == MUXNEG_A::AIN0 + } + #[doc = "Checks if the value of the field is `AIN1`"] + #[inline(always)] + pub fn is_ain1(&self) -> bool { + **self == MUXNEG_A::AIN1 + } + #[doc = "Checks if the value of the field is `AIN2`"] + #[inline(always)] + pub fn is_ain2(&self) -> bool { + **self == MUXNEG_A::AIN2 + } + #[doc = "Checks if the value of the field is `AIN3`"] + #[inline(always)] + pub fn is_ain3(&self) -> bool { + **self == MUXNEG_A::AIN3 + } + #[doc = "Checks if the value of the field is `AIN4`"] + #[inline(always)] + pub fn is_ain4(&self) -> bool { + **self == MUXNEG_A::AIN4 + } + #[doc = "Checks if the value of the field is `AIN5`"] + #[inline(always)] + pub fn is_ain5(&self) -> bool { + **self == MUXNEG_A::AIN5 + } + #[doc = "Checks if the value of the field is `GND`"] + #[inline(always)] + pub fn is_gnd(&self) -> bool { + **self == MUXNEG_A::GND + } +} +impl core::ops::Deref for MUXNEG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MUXNEG` writer - Negative Mux Input Selection"] +pub struct MUXNEG_W<'a> { + w: &'a mut W, +} +impl<'a> MUXNEG_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MUXNEG_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "ADC AIN0 Pin"] + #[inline(always)] + pub fn ain0(self) -> &'a mut W { + self.variant(MUXNEG_A::AIN0) + } + #[doc = "ADC AIN1 Pin"] + #[inline(always)] + pub fn ain1(self) -> &'a mut W { + self.variant(MUXNEG_A::AIN1) + } + #[doc = "ADC AIN2 Pin"] + #[inline(always)] + pub fn ain2(self) -> &'a mut W { + self.variant(MUXNEG_A::AIN2) + } + #[doc = "ADC AIN3 Pin"] + #[inline(always)] + pub fn ain3(self) -> &'a mut W { + self.variant(MUXNEG_A::AIN3) + } + #[doc = "ADC AIN4 Pin"] + #[inline(always)] + pub fn ain4(self) -> &'a mut W { + self.variant(MUXNEG_A::AIN4) + } + #[doc = "ADC AIN5 Pin"] + #[inline(always)] + pub fn ain5(self) -> &'a mut W { + self.variant(MUXNEG_A::AIN5) + } + #[doc = "Internal Ground"] + #[inline(always)] + pub fn gnd(self) -> &'a mut W { + self.variant(MUXNEG_A::GND) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 8)) | ((value as u16 & 0x1f) << 8); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Positive Mux Input Selection"] + #[inline(always)] + pub fn muxpos(&self) -> MUXPOS_R { + MUXPOS_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 8:12 - Negative Mux Input Selection"] + #[inline(always)] + pub fn muxneg(&self) -> MUXNEG_R { + MUXNEG_R::new(((self.bits >> 8) & 0x1f) as u8) + } +} +impl W { + #[doc = "Bits 0:4 - Positive Mux Input Selection"] + #[inline(always)] + pub fn muxpos(&mut self) -> MUXPOS_W { + MUXPOS_W { w: self } + } + #[doc = "Bits 8:12 - Negative Mux Input Selection"] + #[inline(always)] + pub fn muxneg(&mut self) -> MUXNEG_W { + MUXNEG_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Input Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [inputctrl](index.html) module"] +pub struct INPUTCTRL_SPEC; +impl crate::RegisterSpec for INPUTCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [inputctrl::R](R) reader structure"] +impl crate::Readable for INPUTCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [inputctrl::W](W) writer structure"] +impl crate::Writable for INPUTCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INPUTCTRL to value 0"] +impl crate::Resettable for INPUTCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/adc0/intenclr.rs b/pac/atsamc20j/src/adc0/intenclr.rs new file mode 100644 index 000000000000..b10f428d30b1 --- /dev/null +++ b/pac/atsamc20j/src/adc0/intenclr.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RESRDY` reader - Result Ready Interrupt Disable"] +pub struct RESRDY_R(crate::FieldReader); +impl RESRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESRDY` writer - Result Ready Interrupt Disable"] +pub struct RESRDY_W<'a> { + w: &'a mut W, +} +impl<'a> RESRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `OVERRUN` reader - Overrun Interrupt Disable"] +pub struct OVERRUN_R(crate::FieldReader); +impl OVERRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVERRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVERRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVERRUN` writer - Overrun Interrupt Disable"] +pub struct OVERRUN_W<'a> { + w: &'a mut W, +} +impl<'a> OVERRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WINMON` reader - Window Monitor Interrupt Disable"] +pub struct WINMON_R(crate::FieldReader); +impl WINMON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINMON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINMON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMON` writer - Window Monitor Interrupt Disable"] +pub struct WINMON_W<'a> { + w: &'a mut W, +} +impl<'a> WINMON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Result Ready Interrupt Disable"] + #[inline(always)] + pub fn resrdy(&self) -> RESRDY_R { + RESRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Overrun Interrupt Disable"] + #[inline(always)] + pub fn overrun(&self) -> OVERRUN_R { + OVERRUN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Window Monitor Interrupt Disable"] + #[inline(always)] + pub fn winmon(&self) -> WINMON_R { + WINMON_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Result Ready Interrupt Disable"] + #[inline(always)] + pub fn resrdy(&mut self) -> RESRDY_W { + RESRDY_W { w: self } + } + #[doc = "Bit 1 - Overrun Interrupt Disable"] + #[inline(always)] + pub fn overrun(&mut self) -> OVERRUN_W { + OVERRUN_W { w: self } + } + #[doc = "Bit 2 - Window Monitor Interrupt Disable"] + #[inline(always)] + pub fn winmon(&mut self) -> WINMON_W { + WINMON_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/adc0/intenset.rs b/pac/atsamc20j/src/adc0/intenset.rs new file mode 100644 index 000000000000..5ca93b05b859 --- /dev/null +++ b/pac/atsamc20j/src/adc0/intenset.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RESRDY` reader - Result Ready Interrupt Enable"] +pub struct RESRDY_R(crate::FieldReader); +impl RESRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESRDY` writer - Result Ready Interrupt Enable"] +pub struct RESRDY_W<'a> { + w: &'a mut W, +} +impl<'a> RESRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `OVERRUN` reader - Overrun Interrupt Enable"] +pub struct OVERRUN_R(crate::FieldReader); +impl OVERRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVERRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVERRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVERRUN` writer - Overrun Interrupt Enable"] +pub struct OVERRUN_W<'a> { + w: &'a mut W, +} +impl<'a> OVERRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WINMON` reader - Window Monitor Interrupt Enable"] +pub struct WINMON_R(crate::FieldReader); +impl WINMON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINMON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINMON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMON` writer - Window Monitor Interrupt Enable"] +pub struct WINMON_W<'a> { + w: &'a mut W, +} +impl<'a> WINMON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Result Ready Interrupt Enable"] + #[inline(always)] + pub fn resrdy(&self) -> RESRDY_R { + RESRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Overrun Interrupt Enable"] + #[inline(always)] + pub fn overrun(&self) -> OVERRUN_R { + OVERRUN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Window Monitor Interrupt Enable"] + #[inline(always)] + pub fn winmon(&self) -> WINMON_R { + WINMON_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Result Ready Interrupt Enable"] + #[inline(always)] + pub fn resrdy(&mut self) -> RESRDY_W { + RESRDY_W { w: self } + } + #[doc = "Bit 1 - Overrun Interrupt Enable"] + #[inline(always)] + pub fn overrun(&mut self) -> OVERRUN_W { + OVERRUN_W { w: self } + } + #[doc = "Bit 2 - Window Monitor Interrupt Enable"] + #[inline(always)] + pub fn winmon(&mut self) -> WINMON_W { + WINMON_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/adc0/intflag.rs b/pac/atsamc20j/src/adc0/intflag.rs new file mode 100644 index 000000000000..3cd74788b226 --- /dev/null +++ b/pac/atsamc20j/src/adc0/intflag.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RESRDY` reader - Result Ready Interrupt Flag"] +pub struct RESRDY_R(crate::FieldReader); +impl RESRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESRDY` writer - Result Ready Interrupt Flag"] +pub struct RESRDY_W<'a> { + w: &'a mut W, +} +impl<'a> RESRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `OVERRUN` reader - Overrun Interrupt Flag"] +pub struct OVERRUN_R(crate::FieldReader); +impl OVERRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVERRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVERRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVERRUN` writer - Overrun Interrupt Flag"] +pub struct OVERRUN_W<'a> { + w: &'a mut W, +} +impl<'a> OVERRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WINMON` reader - Window Monitor Interrupt Flag"] +pub struct WINMON_R(crate::FieldReader); +impl WINMON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINMON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINMON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMON` writer - Window Monitor Interrupt Flag"] +pub struct WINMON_W<'a> { + w: &'a mut W, +} +impl<'a> WINMON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Result Ready Interrupt Flag"] + #[inline(always)] + pub fn resrdy(&self) -> RESRDY_R { + RESRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Overrun Interrupt Flag"] + #[inline(always)] + pub fn overrun(&self) -> OVERRUN_R { + OVERRUN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Window Monitor Interrupt Flag"] + #[inline(always)] + pub fn winmon(&self) -> WINMON_R { + WINMON_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Result Ready Interrupt Flag"] + #[inline(always)] + pub fn resrdy(&mut self) -> RESRDY_W { + RESRDY_W { w: self } + } + #[doc = "Bit 1 - Overrun Interrupt Flag"] + #[inline(always)] + pub fn overrun(&mut self) -> OVERRUN_W { + OVERRUN_W { w: self } + } + #[doc = "Bit 2 - Window Monitor Interrupt Flag"] + #[inline(always)] + pub fn winmon(&mut self) -> WINMON_W { + WINMON_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/adc0/offsetcorr.rs b/pac/atsamc20j/src/adc0/offsetcorr.rs new file mode 100644 index 000000000000..24a97427c64e --- /dev/null +++ b/pac/atsamc20j/src/adc0/offsetcorr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `OFFSETCORR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OFFSETCORR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OFFSETCORR` reader - Offset Correction Value"] +pub struct OFFSETCORR_R(crate::FieldReader); +impl OFFSETCORR_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + OFFSETCORR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OFFSETCORR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OFFSETCORR` writer - Offset Correction Value"] +pub struct OFFSETCORR_W<'a> { + w: &'a mut W, +} +impl<'a> OFFSETCORR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0fff) | (value as u16 & 0x0fff); + self.w + } +} +impl R { + #[doc = "Bits 0:11 - Offset Correction Value"] + #[inline(always)] + pub fn offsetcorr(&self) -> OFFSETCORR_R { + OFFSETCORR_R::new((self.bits & 0x0fff) as u16) + } +} +impl W { + #[doc = "Bits 0:11 - Offset Correction Value"] + #[inline(always)] + pub fn offsetcorr(&mut self) -> OFFSETCORR_W { + OFFSETCORR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Offset Correction\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [offsetcorr](index.html) module"] +pub struct OFFSETCORR_SPEC; +impl crate::RegisterSpec for OFFSETCORR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [offsetcorr::R](R) reader structure"] +impl crate::Readable for OFFSETCORR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [offsetcorr::W](W) writer structure"] +impl crate::Writable for OFFSETCORR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OFFSETCORR to value 0"] +impl crate::Resettable for OFFSETCORR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/adc0/refctrl.rs b/pac/atsamc20j/src/adc0/refctrl.rs new file mode 100644 index 000000000000..c21b6532936f --- /dev/null +++ b/pac/atsamc20j/src/adc0/refctrl.rs @@ -0,0 +1,238 @@ +#[doc = "Register `REFCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `REFCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Reference Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum REFSEL_A { + #[doc = "0: Internal Bandgap Reference"] + INTREF = 0, + #[doc = "1: 1/1.6 VDDANA"] + INTVCC0 = 1, + #[doc = "2: 1/2 VDDANA"] + INTVCC1 = 2, + #[doc = "3: External Reference"] + AREFA = 3, + #[doc = "5: VDDANA"] + INTVCC2 = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: REFSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `REFSEL` reader - Reference Selection"] +pub struct REFSEL_R(crate::FieldReader); +impl REFSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REFSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(REFSEL_A::INTREF), + 1 => Some(REFSEL_A::INTVCC0), + 2 => Some(REFSEL_A::INTVCC1), + 3 => Some(REFSEL_A::AREFA), + 5 => Some(REFSEL_A::INTVCC2), + _ => None, + } + } + #[doc = "Checks if the value of the field is `INTREF`"] + #[inline(always)] + pub fn is_intref(&self) -> bool { + **self == REFSEL_A::INTREF + } + #[doc = "Checks if the value of the field is `INTVCC0`"] + #[inline(always)] + pub fn is_intvcc0(&self) -> bool { + **self == REFSEL_A::INTVCC0 + } + #[doc = "Checks if the value of the field is `INTVCC1`"] + #[inline(always)] + pub fn is_intvcc1(&self) -> bool { + **self == REFSEL_A::INTVCC1 + } + #[doc = "Checks if the value of the field is `AREFA`"] + #[inline(always)] + pub fn is_arefa(&self) -> bool { + **self == REFSEL_A::AREFA + } + #[doc = "Checks if the value of the field is `INTVCC2`"] + #[inline(always)] + pub fn is_intvcc2(&self) -> bool { + **self == REFSEL_A::INTVCC2 + } +} +impl core::ops::Deref for REFSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REFSEL` writer - Reference Selection"] +pub struct REFSEL_W<'a> { + w: &'a mut W, +} +impl<'a> REFSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: REFSEL_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Internal Bandgap Reference"] + #[inline(always)] + pub fn intref(self) -> &'a mut W { + self.variant(REFSEL_A::INTREF) + } + #[doc = "1/1.6 VDDANA"] + #[inline(always)] + pub fn intvcc0(self) -> &'a mut W { + self.variant(REFSEL_A::INTVCC0) + } + #[doc = "1/2 VDDANA"] + #[inline(always)] + pub fn intvcc1(self) -> &'a mut W { + self.variant(REFSEL_A::INTVCC1) + } + #[doc = "External Reference"] + #[inline(always)] + pub fn arefa(self) -> &'a mut W { + self.variant(REFSEL_A::AREFA) + } + #[doc = "VDDANA"] + #[inline(always)] + pub fn intvcc2(self) -> &'a mut W { + self.variant(REFSEL_A::INTVCC2) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +#[doc = "Field `REFCOMP` reader - Reference Buffer Offset Compensation Enable"] +pub struct REFCOMP_R(crate::FieldReader); +impl REFCOMP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + REFCOMP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REFCOMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REFCOMP` writer - Reference Buffer Offset Compensation Enable"] +pub struct REFCOMP_W<'a> { + w: &'a mut W, +} +impl<'a> REFCOMP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Reference Selection"] + #[inline(always)] + pub fn refsel(&self) -> REFSEL_R { + REFSEL_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 7 - Reference Buffer Offset Compensation Enable"] + #[inline(always)] + pub fn refcomp(&self) -> REFCOMP_R { + REFCOMP_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Reference Selection"] + #[inline(always)] + pub fn refsel(&mut self) -> REFSEL_W { + REFSEL_W { w: self } + } + #[doc = "Bit 7 - Reference Buffer Offset Compensation Enable"] + #[inline(always)] + pub fn refcomp(&mut self) -> REFCOMP_W { + REFCOMP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Reference Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [refctrl](index.html) module"] +pub struct REFCTRL_SPEC; +impl crate::RegisterSpec for REFCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [refctrl::R](R) reader structure"] +impl crate::Readable for REFCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [refctrl::W](W) writer structure"] +impl crate::Writable for REFCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets REFCTRL to value 0"] +impl crate::Resettable for REFCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/adc0/result.rs b/pac/atsamc20j/src/adc0/result.rs new file mode 100644 index 000000000000..b63b08cc72b9 --- /dev/null +++ b/pac/atsamc20j/src/adc0/result.rs @@ -0,0 +1,53 @@ +#[doc = "Register `RESULT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `RESULT` reader - Result Value"] +pub struct RESULT_R(crate::FieldReader); +impl RESULT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + RESULT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESULT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:15 - Result Value"] + #[inline(always)] + pub fn result(&self) -> RESULT_R { + RESULT_R::new(self.bits as u16) + } +} +#[doc = "Result\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [result](index.html) module"] +pub struct RESULT_SPEC; +impl crate::RegisterSpec for RESULT_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [result::R](R) reader structure"] +impl crate::Readable for RESULT_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets RESULT to value 0"] +impl crate::Resettable for RESULT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/adc0/sampctrl.rs b/pac/atsamc20j/src/adc0/sampctrl.rs new file mode 100644 index 000000000000..be4b77a80410 --- /dev/null +++ b/pac/atsamc20j/src/adc0/sampctrl.rs @@ -0,0 +1,150 @@ +#[doc = "Register `SAMPCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SAMPCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SAMPLEN` reader - Sampling Time Length"] +pub struct SAMPLEN_R(crate::FieldReader); +impl SAMPLEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SAMPLEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SAMPLEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SAMPLEN` writer - Sampling Time Length"] +pub struct SAMPLEN_W<'a> { + w: &'a mut W, +} +impl<'a> SAMPLEN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u8 & 0x3f); + self.w + } +} +#[doc = "Field `OFFCOMP` reader - Comparator Offset Compensation Enable"] +pub struct OFFCOMP_R(crate::FieldReader); +impl OFFCOMP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OFFCOMP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OFFCOMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OFFCOMP` writer - Comparator Offset Compensation Enable"] +pub struct OFFCOMP_W<'a> { + w: &'a mut W, +} +impl<'a> OFFCOMP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Sampling Time Length"] + #[inline(always)] + pub fn samplen(&self) -> SAMPLEN_R { + SAMPLEN_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 7 - Comparator Offset Compensation Enable"] + #[inline(always)] + pub fn offcomp(&self) -> OFFCOMP_R { + OFFCOMP_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:5 - Sampling Time Length"] + #[inline(always)] + pub fn samplen(&mut self) -> SAMPLEN_W { + SAMPLEN_W { w: self } + } + #[doc = "Bit 7 - Comparator Offset Compensation Enable"] + #[inline(always)] + pub fn offcomp(&mut self) -> OFFCOMP_W { + OFFCOMP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Sample Time Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sampctrl](index.html) module"] +pub struct SAMPCTRL_SPEC; +impl crate::RegisterSpec for SAMPCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [sampctrl::R](R) reader structure"] +impl crate::Readable for SAMPCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [sampctrl::W](W) writer structure"] +impl crate::Writable for SAMPCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SAMPCTRL to value 0"] +impl crate::Resettable for SAMPCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/adc0/seqctrl.rs b/pac/atsamc20j/src/adc0/seqctrl.rs new file mode 100644 index 000000000000..c8388c9a393f --- /dev/null +++ b/pac/atsamc20j/src/adc0/seqctrl.rs @@ -0,0 +1,103 @@ +#[doc = "Register `SEQCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SEQCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SEQEN` reader - Enable Positive Input in the Sequence"] +pub struct SEQEN_R(crate::FieldReader); +impl SEQEN_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + SEQEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEQEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEQEN` writer - Enable Positive Input in the Sequence"] +pub struct SEQEN_W<'a> { + w: &'a mut W, +} +impl<'a> SEQEN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Enable Positive Input in the Sequence"] + #[inline(always)] + pub fn seqen(&self) -> SEQEN_R { + SEQEN_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Enable Positive Input in the Sequence"] + #[inline(always)] + pub fn seqen(&mut self) -> SEQEN_W { + SEQEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Sequence Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [seqctrl](index.html) module"] +pub struct SEQCTRL_SPEC; +impl crate::RegisterSpec for SEQCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [seqctrl::R](R) reader structure"] +impl crate::Readable for SEQCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [seqctrl::W](W) writer structure"] +impl crate::Writable for SEQCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SEQCTRL to value 0"] +impl crate::Resettable for SEQCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/adc0/seqstatus.rs b/pac/atsamc20j/src/adc0/seqstatus.rs new file mode 100644 index 000000000000..42c820892e9a --- /dev/null +++ b/pac/atsamc20j/src/adc0/seqstatus.rs @@ -0,0 +1,73 @@ +#[doc = "Register `SEQSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SEQSTATE` reader - Sequence State"] +pub struct SEQSTATE_R(crate::FieldReader); +impl SEQSTATE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SEQSTATE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEQSTATE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEQBUSY` reader - Sequence Busy"] +pub struct SEQBUSY_R(crate::FieldReader); +impl SEQBUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SEQBUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEQBUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:4 - Sequence State"] + #[inline(always)] + pub fn seqstate(&self) -> SEQSTATE_R { + SEQSTATE_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bit 7 - Sequence Busy"] + #[inline(always)] + pub fn seqbusy(&self) -> SEQBUSY_R { + SEQBUSY_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +#[doc = "Sequence Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [seqstatus](index.html) module"] +pub struct SEQSTATUS_SPEC; +impl crate::RegisterSpec for SEQSTATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [seqstatus::R](R) reader structure"] +impl crate::Readable for SEQSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SEQSTATUS to value 0"] +impl crate::Resettable for SEQSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/adc0/swtrig.rs b/pac/atsamc20j/src/adc0/swtrig.rs new file mode 100644 index 000000000000..5e23ed7865ed --- /dev/null +++ b/pac/atsamc20j/src/adc0/swtrig.rs @@ -0,0 +1,160 @@ +#[doc = "Register `SWTRIG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SWTRIG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FLUSH` reader - ADC Flush"] +pub struct FLUSH_R(crate::FieldReader); +impl FLUSH_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FLUSH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FLUSH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLUSH` writer - ADC Flush"] +pub struct FLUSH_W<'a> { + w: &'a mut W, +} +impl<'a> FLUSH_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `START` reader - Start ADC Conversion"] +pub struct START_R(crate::FieldReader); +impl START_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + START_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for START_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `START` writer - Start ADC Conversion"] +pub struct START_W<'a> { + w: &'a mut W, +} +impl<'a> START_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - ADC Flush"] + #[inline(always)] + pub fn flush(&self) -> FLUSH_R { + FLUSH_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Start ADC Conversion"] + #[inline(always)] + pub fn start(&self) -> START_R { + START_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - ADC Flush"] + #[inline(always)] + pub fn flush(&mut self) -> FLUSH_W { + FLUSH_W { w: self } + } + #[doc = "Bit 1 - Start ADC Conversion"] + #[inline(always)] + pub fn start(&mut self) -> START_W { + START_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Software Trigger\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [swtrig](index.html) module"] +pub struct SWTRIG_SPEC; +impl crate::RegisterSpec for SWTRIG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [swtrig::R](R) reader structure"] +impl crate::Readable for SWTRIG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [swtrig::W](W) writer structure"] +impl crate::Writable for SWTRIG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SWTRIG to value 0"] +impl crate::Resettable for SWTRIG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/adc0/syncbusy.rs b/pac/atsamc20j/src/adc0/syncbusy.rs new file mode 100644 index 000000000000..9c92da8a7c74 --- /dev/null +++ b/pac/atsamc20j/src/adc0/syncbusy.rs @@ -0,0 +1,253 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - SWRST Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - ENABLE Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INPUTCTRL` reader - INPUTCTRL Synchronization Busy"] +pub struct INPUTCTRL_R(crate::FieldReader); +impl INPUTCTRL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INPUTCTRL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INPUTCTRL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLC` reader - CTRLC Synchronization Busy"] +pub struct CTRLC_R(crate::FieldReader); +impl CTRLC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AVGCTRL` reader - AVGCTRL Synchronization Busy"] +pub struct AVGCTRL_R(crate::FieldReader); +impl AVGCTRL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AVGCTRL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AVGCTRL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SAMPCTRL` reader - SAMPCTRL Synchronization Busy"] +pub struct SAMPCTRL_R(crate::FieldReader); +impl SAMPCTRL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SAMPCTRL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SAMPCTRL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINLT` reader - WINLT Synchronization Busy"] +pub struct WINLT_R(crate::FieldReader); +impl WINLT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINLT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINLT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINUT` reader - WINUT Synchronization Busy"] +pub struct WINUT_R(crate::FieldReader); +impl WINUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GAINCORR` reader - GAINCORR Synchronization Busy"] +pub struct GAINCORR_R(crate::FieldReader); +impl GAINCORR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GAINCORR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GAINCORR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OFFSETCORR` reader - OFFSETCTRL Synchronization Busy"] +pub struct OFFSETCORR_R(crate::FieldReader); +impl OFFSETCORR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OFFSETCORR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OFFSETCORR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG` reader - SWTRG Synchronization Busy"] +pub struct SWTRIG_R(crate::FieldReader); +impl SWTRIG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - SWRST Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ENABLE Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - INPUTCTRL Synchronization Busy"] + #[inline(always)] + pub fn inputctrl(&self) -> INPUTCTRL_R { + INPUTCTRL_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - CTRLC Synchronization Busy"] + #[inline(always)] + pub fn ctrlc(&self) -> CTRLC_R { + CTRLC_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - AVGCTRL Synchronization Busy"] + #[inline(always)] + pub fn avgctrl(&self) -> AVGCTRL_R { + AVGCTRL_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - SAMPCTRL Synchronization Busy"] + #[inline(always)] + pub fn sampctrl(&self) -> SAMPCTRL_R { + SAMPCTRL_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - WINLT Synchronization Busy"] + #[inline(always)] + pub fn winlt(&self) -> WINLT_R { + WINLT_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - WINUT Synchronization Busy"] + #[inline(always)] + pub fn winut(&self) -> WINUT_R { + WINUT_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - GAINCORR Synchronization Busy"] + #[inline(always)] + pub fn gaincorr(&self) -> GAINCORR_R { + GAINCORR_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - OFFSETCTRL Synchronization Busy"] + #[inline(always)] + pub fn offsetcorr(&self) -> OFFSETCORR_R { + OFFSETCORR_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - SWTRG Synchronization Busy"] + #[inline(always)] + pub fn swtrig(&self) -> SWTRIG_R { + SWTRIG_R::new(((self.bits >> 10) & 0x01) != 0) + } +} +#[doc = "Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/adc0/winlt.rs b/pac/atsamc20j/src/adc0/winlt.rs new file mode 100644 index 000000000000..2a3397684767 --- /dev/null +++ b/pac/atsamc20j/src/adc0/winlt.rs @@ -0,0 +1,103 @@ +#[doc = "Register `WINLT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WINLT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WINLT` reader - Window Lower Threshold"] +pub struct WINLT_R(crate::FieldReader); +impl WINLT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + WINLT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINLT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINLT` writer - Window Lower Threshold"] +pub struct WINLT_W<'a> { + w: &'a mut W, +} +impl<'a> WINLT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Window Lower Threshold"] + #[inline(always)] + pub fn winlt(&self) -> WINLT_R { + WINLT_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Window Lower Threshold"] + #[inline(always)] + pub fn winlt(&mut self) -> WINLT_W { + WINLT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Window Monitor Lower Threshold\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [winlt](index.html) module"] +pub struct WINLT_SPEC; +impl crate::RegisterSpec for WINLT_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [winlt::R](R) reader structure"] +impl crate::Readable for WINLT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [winlt::W](W) writer structure"] +impl crate::Writable for WINLT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WINLT to value 0"] +impl crate::Resettable for WINLT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/adc0/winut.rs b/pac/atsamc20j/src/adc0/winut.rs new file mode 100644 index 000000000000..0ea123174937 --- /dev/null +++ b/pac/atsamc20j/src/adc0/winut.rs @@ -0,0 +1,103 @@ +#[doc = "Register `WINUT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WINUT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WINUT` reader - Window Upper Threshold"] +pub struct WINUT_R(crate::FieldReader); +impl WINUT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + WINUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINUT` writer - Window Upper Threshold"] +pub struct WINUT_W<'a> { + w: &'a mut W, +} +impl<'a> WINUT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Window Upper Threshold"] + #[inline(always)] + pub fn winut(&self) -> WINUT_R { + WINUT_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Window Upper Threshold"] + #[inline(always)] + pub fn winut(&mut self) -> WINUT_W { + WINUT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Window Monitor Upper Threshold\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [winut](index.html) module"] +pub struct WINUT_SPEC; +impl crate::RegisterSpec for WINUT_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [winut::R](R) reader structure"] +impl crate::Readable for WINUT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [winut::W](W) writer structure"] +impl crate::Writable for WINUT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WINUT to value 0"] +impl crate::Resettable for WINUT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/ccl.rs b/pac/atsamc20j/src/ccl.rs new file mode 100644 index 000000000000..30b1f41639c1 --- /dev/null +++ b/pac/atsamc20j/src/ccl.rs @@ -0,0 +1,24 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrl: crate::Reg, + _reserved1: [u8; 0x03], + #[doc = "0x04 - SEQ Control x"] + pub seqctrl: [crate::Reg; 2], + _reserved2: [u8; 0x02], + #[doc = "0x08..0x18 - LUT Control x"] + pub lutctrl: [crate::Reg; 4], +} +#[doc = "CTRL register accessor: an alias for `Reg`"] +pub type CTRL = crate::Reg; +#[doc = "Control"] +pub mod ctrl; +#[doc = "SEQCTRL register accessor: an alias for `Reg`"] +pub type SEQCTRL = crate::Reg; +#[doc = "SEQ Control x"] +pub mod seqctrl; +#[doc = "LUTCTRL register accessor: an alias for `Reg`"] +pub type LUTCTRL = crate::Reg; +#[doc = "LUT Control x"] +pub mod lutctrl; diff --git a/pac/atsamc20j/src/ccl/ctrl.rs b/pac/atsamc20j/src/ccl/ctrl.rs new file mode 100644 index 000000000000..5e515fe037ca --- /dev/null +++ b/pac/atsamc20j/src/ccl/ctrl.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"] +pub struct CTRL_SPEC; +impl crate::RegisterSpec for CTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrl::R](R) reader structure"] +impl crate::Readable for CTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"] +impl crate::Writable for CTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/ccl/lutctrl.rs b/pac/atsamc20j/src/ccl/lutctrl.rs new file mode 100644 index 000000000000..530ed34f7c81 --- /dev/null +++ b/pac/atsamc20j/src/ccl/lutctrl.rs @@ -0,0 +1,702 @@ +#[doc = "Register `LUTCTRL[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `LUTCTRL[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - LUT Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - LUT Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Filter Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FILTSEL_A { + #[doc = "0: Filter disabled"] + DISABLE = 0, + #[doc = "1: Synchronizer enabled"] + SYNCH = 1, + #[doc = "2: Filter enabled"] + FILTER = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FILTSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `FILTSEL` reader - Filter Selection"] +pub struct FILTSEL_R(crate::FieldReader); +impl FILTSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FILTSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(FILTSEL_A::DISABLE), + 1 => Some(FILTSEL_A::SYNCH), + 2 => Some(FILTSEL_A::FILTER), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == FILTSEL_A::DISABLE + } + #[doc = "Checks if the value of the field is `SYNCH`"] + #[inline(always)] + pub fn is_synch(&self) -> bool { + **self == FILTSEL_A::SYNCH + } + #[doc = "Checks if the value of the field is `FILTER`"] + #[inline(always)] + pub fn is_filter(&self) -> bool { + **self == FILTSEL_A::FILTER + } +} +impl core::ops::Deref for FILTSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTSEL` writer - Filter Selection"] +pub struct FILTSEL_W<'a> { + w: &'a mut W, +} +impl<'a> FILTSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FILTSEL_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Filter disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(FILTSEL_A::DISABLE) + } + #[doc = "Synchronizer enabled"] + #[inline(always)] + pub fn synch(self) -> &'a mut W { + self.variant(FILTSEL_A::SYNCH) + } + #[doc = "Filter enabled"] + #[inline(always)] + pub fn filter(self) -> &'a mut W { + self.variant(FILTSEL_A::FILTER) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u32 & 0x03) << 4); + self.w + } +} +#[doc = "Field `EDGESEL` reader - Edge Selection"] +pub struct EDGESEL_R(crate::FieldReader); +impl EDGESEL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EDGESEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EDGESEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EDGESEL` writer - Edge Selection"] +pub struct EDGESEL_W<'a> { + w: &'a mut W, +} +impl<'a> EDGESEL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Input Selection 0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum INSEL0_A { + #[doc = "0: Masked input"] + MASK = 0, + #[doc = "1: Feedback input source"] + FEEDBACK = 1, + #[doc = "2: Linked LUT input source"] + LINK = 2, + #[doc = "3: Event in put source"] + EVENT = 3, + #[doc = "4: I/O pin input source"] + IO = 4, + #[doc = "5: AC input source"] + AC = 5, + #[doc = "6: TC input source"] + TC = 6, + #[doc = "7: Alternate TC input source"] + ALTTC = 7, + #[doc = "8: TCC input source"] + TCC = 8, + #[doc = "9: SERCOM inout source"] + SERCOM = 9, +} +impl From for u8 { + #[inline(always)] + fn from(variant: INSEL0_A) -> Self { + variant as _ + } +} +#[doc = "Field `INSEL0` reader - Input Selection 0"] +pub struct INSEL0_R(crate::FieldReader); +impl INSEL0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + INSEL0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(INSEL0_A::MASK), + 1 => Some(INSEL0_A::FEEDBACK), + 2 => Some(INSEL0_A::LINK), + 3 => Some(INSEL0_A::EVENT), + 4 => Some(INSEL0_A::IO), + 5 => Some(INSEL0_A::AC), + 6 => Some(INSEL0_A::TC), + 7 => Some(INSEL0_A::ALTTC), + 8 => Some(INSEL0_A::TCC), + 9 => Some(INSEL0_A::SERCOM), + _ => None, + } + } + #[doc = "Checks if the value of the field is `MASK`"] + #[inline(always)] + pub fn is_mask(&self) -> bool { + **self == INSEL0_A::MASK + } + #[doc = "Checks if the value of the field is `FEEDBACK`"] + #[inline(always)] + pub fn is_feedback(&self) -> bool { + **self == INSEL0_A::FEEDBACK + } + #[doc = "Checks if the value of the field is `LINK`"] + #[inline(always)] + pub fn is_link(&self) -> bool { + **self == INSEL0_A::LINK + } + #[doc = "Checks if the value of the field is `EVENT`"] + #[inline(always)] + pub fn is_event(&self) -> bool { + **self == INSEL0_A::EVENT + } + #[doc = "Checks if the value of the field is `IO`"] + #[inline(always)] + pub fn is_io(&self) -> bool { + **self == INSEL0_A::IO + } + #[doc = "Checks if the value of the field is `AC`"] + #[inline(always)] + pub fn is_ac(&self) -> bool { + **self == INSEL0_A::AC + } + #[doc = "Checks if the value of the field is `TC`"] + #[inline(always)] + pub fn is_tc(&self) -> bool { + **self == INSEL0_A::TC + } + #[doc = "Checks if the value of the field is `ALTTC`"] + #[inline(always)] + pub fn is_alttc(&self) -> bool { + **self == INSEL0_A::ALTTC + } + #[doc = "Checks if the value of the field is `TCC`"] + #[inline(always)] + pub fn is_tcc(&self) -> bool { + **self == INSEL0_A::TCC + } + #[doc = "Checks if the value of the field is `SERCOM`"] + #[inline(always)] + pub fn is_sercom(&self) -> bool { + **self == INSEL0_A::SERCOM + } +} +impl core::ops::Deref for INSEL0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INSEL0` writer - Input Selection 0"] +pub struct INSEL0_W<'a> { + w: &'a mut W, +} +impl<'a> INSEL0_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: INSEL0_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Masked input"] + #[inline(always)] + pub fn mask(self) -> &'a mut W { + self.variant(INSEL0_A::MASK) + } + #[doc = "Feedback input source"] + #[inline(always)] + pub fn feedback(self) -> &'a mut W { + self.variant(INSEL0_A::FEEDBACK) + } + #[doc = "Linked LUT input source"] + #[inline(always)] + pub fn link(self) -> &'a mut W { + self.variant(INSEL0_A::LINK) + } + #[doc = "Event in put source"] + #[inline(always)] + pub fn event(self) -> &'a mut W { + self.variant(INSEL0_A::EVENT) + } + #[doc = "I/O pin input source"] + #[inline(always)] + pub fn io(self) -> &'a mut W { + self.variant(INSEL0_A::IO) + } + #[doc = "AC input source"] + #[inline(always)] + pub fn ac(self) -> &'a mut W { + self.variant(INSEL0_A::AC) + } + #[doc = "TC input source"] + #[inline(always)] + pub fn tc(self) -> &'a mut W { + self.variant(INSEL0_A::TC) + } + #[doc = "Alternate TC input source"] + #[inline(always)] + pub fn alttc(self) -> &'a mut W { + self.variant(INSEL0_A::ALTTC) + } + #[doc = "TCC input source"] + #[inline(always)] + pub fn tcc(self) -> &'a mut W { + self.variant(INSEL0_A::TCC) + } + #[doc = "SERCOM inout source"] + #[inline(always)] + pub fn sercom(self) -> &'a mut W { + self.variant(INSEL0_A::SERCOM) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 8)) | ((value as u32 & 0x0f) << 8); + self.w + } +} +#[doc = "Field `INSEL1` reader - Input Selection 1"] +pub struct INSEL1_R(crate::FieldReader); +impl INSEL1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + INSEL1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INSEL1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INSEL1` writer - Input Selection 1"] +pub struct INSEL1_W<'a> { + w: &'a mut W, +} +impl<'a> INSEL1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 12)) | ((value as u32 & 0x0f) << 12); + self.w + } +} +#[doc = "Field `INSEL2` reader - Input Selection 2"] +pub struct INSEL2_R(crate::FieldReader); +impl INSEL2_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + INSEL2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INSEL2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INSEL2` writer - Input Selection 2"] +pub struct INSEL2_W<'a> { + w: &'a mut W, +} +impl<'a> INSEL2_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 16)) | ((value as u32 & 0x0f) << 16); + self.w + } +} +#[doc = "Field `INVEI` reader - Input Event Invert"] +pub struct INVEI_R(crate::FieldReader); +impl INVEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEI` writer - Input Event Invert"] +pub struct INVEI_W<'a> { + w: &'a mut W, +} +impl<'a> INVEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `LUTEI` reader - Event Input Enable"] +pub struct LUTEI_R(crate::FieldReader); +impl LUTEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LUTEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LUTEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LUTEI` writer - Event Input Enable"] +pub struct LUTEI_W<'a> { + w: &'a mut W, +} +impl<'a> LUTEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `LUTEO` reader - Event Output Enable"] +pub struct LUTEO_R(crate::FieldReader); +impl LUTEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LUTEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LUTEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LUTEO` writer - Event Output Enable"] +pub struct LUTEO_W<'a> { + w: &'a mut W, +} +impl<'a> LUTEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `TRUTH` reader - Truth Value"] +pub struct TRUTH_R(crate::FieldReader); +impl TRUTH_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TRUTH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRUTH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRUTH` writer - Truth Value"] +pub struct TRUTH_W<'a> { + w: &'a mut W, +} +impl<'a> TRUTH_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 24)) | ((value as u32 & 0xff) << 24); + self.w + } +} +impl R { + #[doc = "Bit 1 - LUT Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 4:5 - Filter Selection"] + #[inline(always)] + pub fn filtsel(&self) -> FILTSEL_R { + FILTSEL_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bit 7 - Edge Selection"] + #[inline(always)] + pub fn edgesel(&self) -> EDGESEL_R { + EDGESEL_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:11 - Input Selection 0"] + #[inline(always)] + pub fn insel0(&self) -> INSEL0_R { + INSEL0_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - Input Selection 1"] + #[inline(always)] + pub fn insel1(&self) -> INSEL1_R { + INSEL1_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:19 - Input Selection 2"] + #[inline(always)] + pub fn insel2(&self) -> INSEL2_R { + INSEL2_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Input Event Invert"] + #[inline(always)] + pub fn invei(&self) -> INVEI_R { + INVEI_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Event Input Enable"] + #[inline(always)] + pub fn lutei(&self) -> LUTEI_R { + LUTEI_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Event Output Enable"] + #[inline(always)] + pub fn luteo(&self) -> LUTEO_R { + LUTEO_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bits 24:31 - Truth Value"] + #[inline(always)] + pub fn truth(&self) -> TRUTH_R { + TRUTH_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bit 1 - LUT Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 4:5 - Filter Selection"] + #[inline(always)] + pub fn filtsel(&mut self) -> FILTSEL_W { + FILTSEL_W { w: self } + } + #[doc = "Bit 7 - Edge Selection"] + #[inline(always)] + pub fn edgesel(&mut self) -> EDGESEL_W { + EDGESEL_W { w: self } + } + #[doc = "Bits 8:11 - Input Selection 0"] + #[inline(always)] + pub fn insel0(&mut self) -> INSEL0_W { + INSEL0_W { w: self } + } + #[doc = "Bits 12:15 - Input Selection 1"] + #[inline(always)] + pub fn insel1(&mut self) -> INSEL1_W { + INSEL1_W { w: self } + } + #[doc = "Bits 16:19 - Input Selection 2"] + #[inline(always)] + pub fn insel2(&mut self) -> INSEL2_W { + INSEL2_W { w: self } + } + #[doc = "Bit 20 - Input Event Invert"] + #[inline(always)] + pub fn invei(&mut self) -> INVEI_W { + INVEI_W { w: self } + } + #[doc = "Bit 21 - Event Input Enable"] + #[inline(always)] + pub fn lutei(&mut self) -> LUTEI_W { + LUTEI_W { w: self } + } + #[doc = "Bit 22 - Event Output Enable"] + #[inline(always)] + pub fn luteo(&mut self) -> LUTEO_W { + LUTEO_W { w: self } + } + #[doc = "Bits 24:31 - Truth Value"] + #[inline(always)] + pub fn truth(&mut self) -> TRUTH_W { + TRUTH_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "LUT Control x\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lutctrl](index.html) module"] +pub struct LUTCTRL_SPEC; +impl crate::RegisterSpec for LUTCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [lutctrl::R](R) reader structure"] +impl crate::Readable for LUTCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [lutctrl::W](W) writer structure"] +impl crate::Writable for LUTCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets LUTCTRL[%s] +to value 0"] +impl crate::Resettable for LUTCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/ccl/seqctrl.rs b/pac/atsamc20j/src/ccl/seqctrl.rs new file mode 100644 index 000000000000..e2597a1042f3 --- /dev/null +++ b/pac/atsamc20j/src/ccl/seqctrl.rs @@ -0,0 +1,192 @@ +#[doc = "Register `SEQCTRL[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SEQCTRL[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Sequential Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SEQSEL_A { + #[doc = "0: Sequential logic is disabled"] + DISABLE = 0, + #[doc = "1: D flip flop"] + DFF = 1, + #[doc = "2: JK flip flop"] + JK = 2, + #[doc = "3: D latch"] + LATCH = 3, + #[doc = "4: RS latch"] + RS = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEQSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `SEQSEL` reader - Sequential Selection"] +pub struct SEQSEL_R(crate::FieldReader); +impl SEQSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SEQSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEQSEL_A::DISABLE), + 1 => Some(SEQSEL_A::DFF), + 2 => Some(SEQSEL_A::JK), + 3 => Some(SEQSEL_A::LATCH), + 4 => Some(SEQSEL_A::RS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == SEQSEL_A::DISABLE + } + #[doc = "Checks if the value of the field is `DFF`"] + #[inline(always)] + pub fn is_dff(&self) -> bool { + **self == SEQSEL_A::DFF + } + #[doc = "Checks if the value of the field is `JK`"] + #[inline(always)] + pub fn is_jk(&self) -> bool { + **self == SEQSEL_A::JK + } + #[doc = "Checks if the value of the field is `LATCH`"] + #[inline(always)] + pub fn is_latch(&self) -> bool { + **self == SEQSEL_A::LATCH + } + #[doc = "Checks if the value of the field is `RS`"] + #[inline(always)] + pub fn is_rs(&self) -> bool { + **self == SEQSEL_A::RS + } +} +impl core::ops::Deref for SEQSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEQSEL` writer - Sequential Selection"] +pub struct SEQSEL_W<'a> { + w: &'a mut W, +} +impl<'a> SEQSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SEQSEL_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Sequential logic is disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(SEQSEL_A::DISABLE) + } + #[doc = "D flip flop"] + #[inline(always)] + pub fn dff(self) -> &'a mut W { + self.variant(SEQSEL_A::DFF) + } + #[doc = "JK flip flop"] + #[inline(always)] + pub fn jk(self) -> &'a mut W { + self.variant(SEQSEL_A::JK) + } + #[doc = "D latch"] + #[inline(always)] + pub fn latch(self) -> &'a mut W { + self.variant(SEQSEL_A::LATCH) + } + #[doc = "RS latch"] + #[inline(always)] + pub fn rs(self) -> &'a mut W { + self.variant(SEQSEL_A::RS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Sequential Selection"] + #[inline(always)] + pub fn seqsel(&self) -> SEQSEL_R { + SEQSEL_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Sequential Selection"] + #[inline(always)] + pub fn seqsel(&mut self) -> SEQSEL_W { + SEQSEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SEQ Control x\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [seqctrl](index.html) module"] +pub struct SEQCTRL_SPEC; +impl crate::RegisterSpec for SEQCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [seqctrl::R](R) reader structure"] +impl crate::Readable for SEQCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [seqctrl::W](W) writer structure"] +impl crate::Writable for SEQCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SEQCTRL[%s] +to value 0"] +impl crate::Resettable for SEQCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/divas.rs b/pac/atsamc20j/src/divas.rs new file mode 100644 index 000000000000..dbc2f5f226da --- /dev/null +++ b/pac/atsamc20j/src/divas.rs @@ -0,0 +1,48 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrla: crate::Reg, + _reserved1: [u8; 0x03], + #[doc = "0x04 - Status"] + pub status: crate::Reg, + _reserved2: [u8; 0x03], + #[doc = "0x08 - Dividend"] + pub dividend: crate::Reg, + #[doc = "0x0c - Divisor"] + pub divisor: crate::Reg, + #[doc = "0x10 - Result"] + pub result: crate::Reg, + #[doc = "0x14 - Remainder"] + pub rem: crate::Reg, + #[doc = "0x18 - Square Root Input"] + pub sqrnum: crate::Reg, +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control"] +pub mod ctrla; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "DIVIDEND register accessor: an alias for `Reg`"] +pub type DIVIDEND = crate::Reg; +#[doc = "Dividend"] +pub mod dividend; +#[doc = "DIVISOR register accessor: an alias for `Reg`"] +pub type DIVISOR = crate::Reg; +#[doc = "Divisor"] +pub mod divisor; +#[doc = "RESULT register accessor: an alias for `Reg`"] +pub type RESULT = crate::Reg; +#[doc = "Result"] +pub mod result; +#[doc = "REM register accessor: an alias for `Reg`"] +pub type REM = crate::Reg; +#[doc = "Remainder"] +pub mod rem; +#[doc = "SQRNUM register accessor: an alias for `Reg`"] +pub type SQRNUM = crate::Reg; +#[doc = "Square Root Input"] +pub mod sqrnum; diff --git a/pac/atsamc20j/src/divas/ctrla.rs b/pac/atsamc20j/src/divas/ctrla.rs new file mode 100644 index 000000000000..7f79349da05c --- /dev/null +++ b/pac/atsamc20j/src/divas/ctrla.rs @@ -0,0 +1,160 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SIGNED` reader - Signed"] +pub struct SIGNED_R(crate::FieldReader); +impl SIGNED_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SIGNED_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SIGNED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SIGNED` writer - Signed"] +pub struct SIGNED_W<'a> { + w: &'a mut W, +} +impl<'a> SIGNED_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `DLZ` reader - Disable Leading Zero Optimization"] +pub struct DLZ_R(crate::FieldReader); +impl DLZ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DLZ_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DLZ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DLZ` writer - Disable Leading Zero Optimization"] +pub struct DLZ_W<'a> { + w: &'a mut W, +} +impl<'a> DLZ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - Signed"] + #[inline(always)] + pub fn signed(&self) -> SIGNED_R { + SIGNED_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Disable Leading Zero Optimization"] + #[inline(always)] + pub fn dlz(&self) -> DLZ_R { + DLZ_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Signed"] + #[inline(always)] + pub fn signed(&mut self) -> SIGNED_W { + SIGNED_W { w: self } + } + #[doc = "Bit 1 - Disable Leading Zero Optimization"] + #[inline(always)] + pub fn dlz(&mut self) -> DLZ_W { + DLZ_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/divas/dividend.rs b/pac/atsamc20j/src/divas/dividend.rs new file mode 100644 index 000000000000..215f44261a6c --- /dev/null +++ b/pac/atsamc20j/src/divas/dividend.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DIVIDEND` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIVIDEND` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIVIDEND` reader - DIVIDEND"] +pub struct DIVIDEND_R(crate::FieldReader); +impl DIVIDEND_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + DIVIDEND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIVIDEND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIVIDEND` writer - DIVIDEND"] +pub struct DIVIDEND_W<'a> { + w: &'a mut W, +} +impl<'a> DIVIDEND_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - DIVIDEND"] + #[inline(always)] + pub fn dividend(&self) -> DIVIDEND_R { + DIVIDEND_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - DIVIDEND"] + #[inline(always)] + pub fn dividend(&mut self) -> DIVIDEND_W { + DIVIDEND_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Dividend\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dividend](index.html) module"] +pub struct DIVIDEND_SPEC; +impl crate::RegisterSpec for DIVIDEND_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dividend::R](R) reader structure"] +impl crate::Readable for DIVIDEND_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dividend::W](W) writer structure"] +impl crate::Writable for DIVIDEND_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DIVIDEND to value 0"] +impl crate::Resettable for DIVIDEND_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/divas/divisor.rs b/pac/atsamc20j/src/divas/divisor.rs new file mode 100644 index 000000000000..b711870a5cd6 --- /dev/null +++ b/pac/atsamc20j/src/divas/divisor.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DIVISOR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIVISOR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIVISOR` reader - DIVISOR"] +pub struct DIVISOR_R(crate::FieldReader); +impl DIVISOR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + DIVISOR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIVISOR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIVISOR` writer - DIVISOR"] +pub struct DIVISOR_W<'a> { + w: &'a mut W, +} +impl<'a> DIVISOR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - DIVISOR"] + #[inline(always)] + pub fn divisor(&self) -> DIVISOR_R { + DIVISOR_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - DIVISOR"] + #[inline(always)] + pub fn divisor(&mut self) -> DIVISOR_W { + DIVISOR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Divisor\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [divisor](index.html) module"] +pub struct DIVISOR_SPEC; +impl crate::RegisterSpec for DIVISOR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [divisor::R](R) reader structure"] +impl crate::Readable for DIVISOR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [divisor::W](W) writer structure"] +impl crate::Writable for DIVISOR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DIVISOR to value 0"] +impl crate::Resettable for DIVISOR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/divas/rem.rs b/pac/atsamc20j/src/divas/rem.rs new file mode 100644 index 000000000000..76f3a90878ed --- /dev/null +++ b/pac/atsamc20j/src/divas/rem.rs @@ -0,0 +1,53 @@ +#[doc = "Register `REM` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `REM` reader - REM"] +pub struct REM_R(crate::FieldReader); +impl REM_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + REM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - REM"] + #[inline(always)] + pub fn rem(&self) -> REM_R { + REM_R::new(self.bits as u32) + } +} +#[doc = "Remainder\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rem](index.html) module"] +pub struct REM_SPEC; +impl crate::RegisterSpec for REM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rem::R](R) reader structure"] +impl crate::Readable for REM_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets REM to value 0"] +impl crate::Resettable for REM_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/divas/result.rs b/pac/atsamc20j/src/divas/result.rs new file mode 100644 index 000000000000..85fc1a025f9e --- /dev/null +++ b/pac/atsamc20j/src/divas/result.rs @@ -0,0 +1,53 @@ +#[doc = "Register `RESULT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `RESULT` reader - RESULT"] +pub struct RESULT_R(crate::FieldReader); +impl RESULT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + RESULT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESULT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - RESULT"] + #[inline(always)] + pub fn result(&self) -> RESULT_R { + RESULT_R::new(self.bits as u32) + } +} +#[doc = "Result\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [result](index.html) module"] +pub struct RESULT_SPEC; +impl crate::RegisterSpec for RESULT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [result::R](R) reader structure"] +impl crate::Readable for RESULT_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets RESULT to value 0"] +impl crate::Resettable for RESULT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/divas/sqrnum.rs b/pac/atsamc20j/src/divas/sqrnum.rs new file mode 100644 index 000000000000..cc0ce6806beb --- /dev/null +++ b/pac/atsamc20j/src/divas/sqrnum.rs @@ -0,0 +1,103 @@ +#[doc = "Register `SQRNUM` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SQRNUM` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SQRNUM` reader - Square Root Input"] +pub struct SQRNUM_R(crate::FieldReader); +impl SQRNUM_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + SQRNUM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SQRNUM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SQRNUM` writer - Square Root Input"] +pub struct SQRNUM_W<'a> { + w: &'a mut W, +} +impl<'a> SQRNUM_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Square Root Input"] + #[inline(always)] + pub fn sqrnum(&self) -> SQRNUM_R { + SQRNUM_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Square Root Input"] + #[inline(always)] + pub fn sqrnum(&mut self) -> SQRNUM_W { + SQRNUM_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Square Root Input\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sqrnum](index.html) module"] +pub struct SQRNUM_SPEC; +impl crate::RegisterSpec for SQRNUM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [sqrnum::R](R) reader structure"] +impl crate::Readable for SQRNUM_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [sqrnum::W](W) writer structure"] +impl crate::Writable for SQRNUM_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SQRNUM to value 0"] +impl crate::Resettable for SQRNUM_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/divas/status.rs b/pac/atsamc20j/src/divas/status.rs new file mode 100644 index 000000000000..feffbccec659 --- /dev/null +++ b/pac/atsamc20j/src/divas/status.rs @@ -0,0 +1,160 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BUSY` reader - DIVAS Accelerator Busy"] +pub struct BUSY_R(crate::FieldReader); +impl BUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSY` writer - DIVAS Accelerator Busy"] +pub struct BUSY_W<'a> { + w: &'a mut W, +} +impl<'a> BUSY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `DBZ` reader - Writing a one to this bit clears DBZ to zero"] +pub struct DBZ_R(crate::FieldReader); +impl DBZ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBZ_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBZ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBZ` writer - Writing a one to this bit clears DBZ to zero"] +pub struct DBZ_W<'a> { + w: &'a mut W, +} +impl<'a> DBZ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - DIVAS Accelerator Busy"] + #[inline(always)] + pub fn busy(&self) -> BUSY_R { + BUSY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Writing a one to this bit clears DBZ to zero"] + #[inline(always)] + pub fn dbz(&self) -> DBZ_R { + DBZ_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - DIVAS Accelerator Busy"] + #[inline(always)] + pub fn busy(&mut self) -> BUSY_W { + BUSY_W { w: self } + } + #[doc = "Bit 1 - Writing a one to this bit clears DBZ to zero"] + #[inline(always)] + pub fn dbz(&mut self) -> DBZ_W { + DBZ_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/dmac.rs b/pac/atsamc20j/src/dmac.rs new file mode 100644 index 000000000000..c23d36697550 --- /dev/null +++ b/pac/atsamc20j/src/dmac.rs @@ -0,0 +1,148 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrl: crate::Reg, + #[doc = "0x02 - CRC Control"] + pub crcctrl: crate::Reg, + #[doc = "0x04 - CRC Data Input"] + pub crcdatain: crate::Reg, + #[doc = "0x08 - CRC Checksum"] + pub crcchksum: crate::Reg, + #[doc = "0x0c - CRC Status"] + pub crcstatus: crate::Reg, + #[doc = "0x0d - Debug Control"] + pub dbgctrl: crate::Reg, + #[doc = "0x0e - QOS Control"] + pub qosctrl: crate::Reg, + _reserved7: [u8; 0x01], + #[doc = "0x10 - Software Trigger Control"] + pub swtrigctrl: crate::Reg, + #[doc = "0x14 - Priority Control 0"] + pub prictrl0: crate::Reg, + _reserved9: [u8; 0x08], + #[doc = "0x20 - Interrupt Pending"] + pub intpend: crate::Reg, + _reserved10: [u8; 0x02], + #[doc = "0x24 - Interrupt Status"] + pub intstatus: crate::Reg, + #[doc = "0x28 - Busy Channels"] + pub busych: crate::Reg, + #[doc = "0x2c - Pending Channels"] + pub pendch: crate::Reg, + #[doc = "0x30 - Active Channel and Levels"] + pub active: crate::Reg, + #[doc = "0x34 - Descriptor Memory Section Base Address"] + pub baseaddr: crate::Reg, + #[doc = "0x38 - Write-Back Memory Section Base Address"] + pub wrbaddr: crate::Reg, + _reserved16: [u8; 0x03], + #[doc = "0x3f - Channel ID"] + pub chid: crate::Reg, + #[doc = "0x40 - Channel Control A"] + pub chctrla: crate::Reg, + _reserved18: [u8; 0x03], + #[doc = "0x44 - Channel Control B"] + pub chctrlb: crate::Reg, + _reserved19: [u8; 0x04], + #[doc = "0x4c - Channel Interrupt Enable Clear"] + pub chintenclr: crate::Reg, + #[doc = "0x4d - Channel Interrupt Enable Set"] + pub chintenset: crate::Reg, + #[doc = "0x4e - Channel Interrupt Flag Status and Clear"] + pub chintflag: crate::Reg, + #[doc = "0x4f - Channel Status"] + pub chstatus: crate::Reg, +} +#[doc = "CTRL register accessor: an alias for `Reg`"] +pub type CTRL = crate::Reg; +#[doc = "Control"] +pub mod ctrl; +#[doc = "CRCCTRL register accessor: an alias for `Reg`"] +pub type CRCCTRL = crate::Reg; +#[doc = "CRC Control"] +pub mod crcctrl; +#[doc = "CRCDATAIN register accessor: an alias for `Reg`"] +pub type CRCDATAIN = crate::Reg; +#[doc = "CRC Data Input"] +pub mod crcdatain; +#[doc = "CRCCHKSUM register accessor: an alias for `Reg`"] +pub type CRCCHKSUM = crate::Reg; +#[doc = "CRC Checksum"] +pub mod crcchksum; +#[doc = "CRCSTATUS register accessor: an alias for `Reg`"] +pub type CRCSTATUS = crate::Reg; +#[doc = "CRC Status"] +pub mod crcstatus; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "QOSCTRL register accessor: an alias for `Reg`"] +pub type QOSCTRL = crate::Reg; +#[doc = "QOS Control"] +pub mod qosctrl; +#[doc = "SWTRIGCTRL register accessor: an alias for `Reg`"] +pub type SWTRIGCTRL = crate::Reg; +#[doc = "Software Trigger Control"] +pub mod swtrigctrl; +#[doc = "PRICTRL0 register accessor: an alias for `Reg`"] +pub type PRICTRL0 = crate::Reg; +#[doc = "Priority Control 0"] +pub mod prictrl0; +#[doc = "INTPEND register accessor: an alias for `Reg`"] +pub type INTPEND = crate::Reg; +#[doc = "Interrupt Pending"] +pub mod intpend; +#[doc = "INTSTATUS register accessor: an alias for `Reg`"] +pub type INTSTATUS = crate::Reg; +#[doc = "Interrupt Status"] +pub mod intstatus; +#[doc = "BUSYCH register accessor: an alias for `Reg`"] +pub type BUSYCH = crate::Reg; +#[doc = "Busy Channels"] +pub mod busych; +#[doc = "PENDCH register accessor: an alias for `Reg`"] +pub type PENDCH = crate::Reg; +#[doc = "Pending Channels"] +pub mod pendch; +#[doc = "ACTIVE register accessor: an alias for `Reg`"] +pub type ACTIVE = crate::Reg; +#[doc = "Active Channel and Levels"] +pub mod active; +#[doc = "BASEADDR register accessor: an alias for `Reg`"] +pub type BASEADDR = crate::Reg; +#[doc = "Descriptor Memory Section Base Address"] +pub mod baseaddr; +#[doc = "WRBADDR register accessor: an alias for `Reg`"] +pub type WRBADDR = crate::Reg; +#[doc = "Write-Back Memory Section Base Address"] +pub mod wrbaddr; +#[doc = "CHID register accessor: an alias for `Reg`"] +pub type CHID = crate::Reg; +#[doc = "Channel ID"] +pub mod chid; +#[doc = "CHCTRLA register accessor: an alias for `Reg`"] +pub type CHCTRLA = crate::Reg; +#[doc = "Channel Control A"] +pub mod chctrla; +#[doc = "CHCTRLB register accessor: an alias for `Reg`"] +pub type CHCTRLB = crate::Reg; +#[doc = "Channel Control B"] +pub mod chctrlb; +#[doc = "CHINTENCLR register accessor: an alias for `Reg`"] +pub type CHINTENCLR = crate::Reg; +#[doc = "Channel Interrupt Enable Clear"] +pub mod chintenclr; +#[doc = "CHINTENSET register accessor: an alias for `Reg`"] +pub type CHINTENSET = crate::Reg; +#[doc = "Channel Interrupt Enable Set"] +pub mod chintenset; +#[doc = "CHINTFLAG register accessor: an alias for `Reg`"] +pub type CHINTFLAG = crate::Reg; +#[doc = "Channel Interrupt Flag Status and Clear"] +pub mod chintflag; +#[doc = "CHSTATUS register accessor: an alias for `Reg`"] +pub type CHSTATUS = crate::Reg; +#[doc = "Channel Status"] +pub mod chstatus; diff --git a/pac/atsamc20j/src/dmac/active.rs b/pac/atsamc20j/src/dmac/active.rs new file mode 100644 index 000000000000..c3cc5a0420bc --- /dev/null +++ b/pac/atsamc20j/src/dmac/active.rs @@ -0,0 +1,173 @@ +#[doc = "Register `ACTIVE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `LVLEX0` reader - Level 0 Channel Trigger Request Executing"] +pub struct LVLEX0_R(crate::FieldReader); +impl LVLEX0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LVLEX0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEX0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLEX1` reader - Level 1 Channel Trigger Request Executing"] +pub struct LVLEX1_R(crate::FieldReader); +impl LVLEX1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LVLEX1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEX1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLEX2` reader - Level 2 Channel Trigger Request Executing"] +pub struct LVLEX2_R(crate::FieldReader); +impl LVLEX2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LVLEX2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEX2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLEX3` reader - Level 3 Channel Trigger Request Executing"] +pub struct LVLEX3_R(crate::FieldReader); +impl LVLEX3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LVLEX3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEX3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ID` reader - Active Channel ID"] +pub struct ID_R(crate::FieldReader); +impl ID_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ID_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ID_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ABUSY` reader - Active Channel Busy"] +pub struct ABUSY_R(crate::FieldReader); +impl ABUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ABUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ABUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BTCNT` reader - Active Channel Block Transfer Count"] +pub struct BTCNT_R(crate::FieldReader); +impl BTCNT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BTCNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BTCNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Level 0 Channel Trigger Request Executing"] + #[inline(always)] + pub fn lvlex0(&self) -> LVLEX0_R { + LVLEX0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Level 1 Channel Trigger Request Executing"] + #[inline(always)] + pub fn lvlex1(&self) -> LVLEX1_R { + LVLEX1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Level 2 Channel Trigger Request Executing"] + #[inline(always)] + pub fn lvlex2(&self) -> LVLEX2_R { + LVLEX2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Level 3 Channel Trigger Request Executing"] + #[inline(always)] + pub fn lvlex3(&self) -> LVLEX3_R { + LVLEX3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bits 8:12 - Active Channel ID"] + #[inline(always)] + pub fn id(&self) -> ID_R { + ID_R::new(((self.bits >> 8) & 0x1f) as u8) + } + #[doc = "Bit 15 - Active Channel Busy"] + #[inline(always)] + pub fn abusy(&self) -> ABUSY_R { + ABUSY_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:31 - Active Channel Block Transfer Count"] + #[inline(always)] + pub fn btcnt(&self) -> BTCNT_R { + BTCNT_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[doc = "Active Channel and Levels\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [active](index.html) module"] +pub struct ACTIVE_SPEC; +impl crate::RegisterSpec for ACTIVE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [active::R](R) reader structure"] +impl crate::Readable for ACTIVE_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets ACTIVE to value 0"] +impl crate::Resettable for ACTIVE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/dmac/baseaddr.rs b/pac/atsamc20j/src/dmac/baseaddr.rs new file mode 100644 index 000000000000..cec8c8cf0777 --- /dev/null +++ b/pac/atsamc20j/src/dmac/baseaddr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `BASEADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BASEADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BASEADDR` reader - Descriptor Memory Base Address"] +pub struct BASEADDR_R(crate::FieldReader); +impl BASEADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + BASEADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BASEADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BASEADDR` writer - Descriptor Memory Base Address"] +pub struct BASEADDR_W<'a> { + w: &'a mut W, +} +impl<'a> BASEADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Descriptor Memory Base Address"] + #[inline(always)] + pub fn baseaddr(&self) -> BASEADDR_R { + BASEADDR_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Descriptor Memory Base Address"] + #[inline(always)] + pub fn baseaddr(&mut self) -> BASEADDR_W { + BASEADDR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Descriptor Memory Section Base Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baseaddr](index.html) module"] +pub struct BASEADDR_SPEC; +impl crate::RegisterSpec for BASEADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [baseaddr::R](R) reader structure"] +impl crate::Readable for BASEADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baseaddr::W](W) writer structure"] +impl crate::Writable for BASEADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BASEADDR to value 0"] +impl crate::Resettable for BASEADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/dmac/busych.rs b/pac/atsamc20j/src/dmac/busych.rs new file mode 100644 index 000000000000..68fdc5e3788b --- /dev/null +++ b/pac/atsamc20j/src/dmac/busych.rs @@ -0,0 +1,153 @@ +#[doc = "Register `BUSYCH` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `BUSYCH0` reader - Busy Channel 0"] +pub struct BUSYCH0_R(crate::FieldReader); +impl BUSYCH0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH1` reader - Busy Channel 1"] +pub struct BUSYCH1_R(crate::FieldReader); +impl BUSYCH1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH2` reader - Busy Channel 2"] +pub struct BUSYCH2_R(crate::FieldReader); +impl BUSYCH2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH3` reader - Busy Channel 3"] +pub struct BUSYCH3_R(crate::FieldReader); +impl BUSYCH3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH4` reader - Busy Channel 4"] +pub struct BUSYCH4_R(crate::FieldReader); +impl BUSYCH4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH5` reader - Busy Channel 5"] +pub struct BUSYCH5_R(crate::FieldReader); +impl BUSYCH5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Busy Channel 0"] + #[inline(always)] + pub fn busych0(&self) -> BUSYCH0_R { + BUSYCH0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Busy Channel 1"] + #[inline(always)] + pub fn busych1(&self) -> BUSYCH1_R { + BUSYCH1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Busy Channel 2"] + #[inline(always)] + pub fn busych2(&self) -> BUSYCH2_R { + BUSYCH2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Busy Channel 3"] + #[inline(always)] + pub fn busych3(&self) -> BUSYCH3_R { + BUSYCH3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Busy Channel 4"] + #[inline(always)] + pub fn busych4(&self) -> BUSYCH4_R { + BUSYCH4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Busy Channel 5"] + #[inline(always)] + pub fn busych5(&self) -> BUSYCH5_R { + BUSYCH5_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +#[doc = "Busy Channels\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [busych](index.html) module"] +pub struct BUSYCH_SPEC; +impl crate::RegisterSpec for BUSYCH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [busych::R](R) reader structure"] +impl crate::Readable for BUSYCH_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets BUSYCH to value 0"] +impl crate::Resettable for BUSYCH_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/dmac/chctrla.rs b/pac/atsamc20j/src/dmac/chctrla.rs new file mode 100644 index 000000000000..22e8d456e05c --- /dev/null +++ b/pac/atsamc20j/src/dmac/chctrla.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CHCTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHCTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Channel Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Channel Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Channel Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Channel Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Channel run in standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Channel run in standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - Channel Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 6 - Channel run in standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Channel Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 6 - Channel run in standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chctrla](index.html) module"] +pub struct CHCTRLA_SPEC; +impl crate::RegisterSpec for CHCTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [chctrla::R](R) reader structure"] +impl crate::Readable for CHCTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chctrla::W](W) writer structure"] +impl crate::Writable for CHCTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHCTRLA to value 0"] +impl crate::Resettable for CHCTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/dmac/chctrlb.rs b/pac/atsamc20j/src/dmac/chctrlb.rs new file mode 100644 index 000000000000..5dcbc1da26f1 --- /dev/null +++ b/pac/atsamc20j/src/dmac/chctrlb.rs @@ -0,0 +1,1188 @@ +#[doc = "Register `CHCTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHCTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Event Input Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EVACT_A { + #[doc = "0: No action"] + NOACT = 0, + #[doc = "1: Transfer and periodic transfer trigger"] + TRIG = 1, + #[doc = "2: Conditional transfer trigger"] + CTRIG = 2, + #[doc = "3: Conditional block transfer"] + CBLOCK = 3, + #[doc = "4: Channel suspend operation"] + SUSPEND = 4, + #[doc = "5: Channel resume operation"] + RESUME = 5, + #[doc = "6: Skip next block suspend action"] + SSKIP = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EVACT_A) -> Self { + variant as _ + } +} +#[doc = "Field `EVACT` reader - Event Input Action"] +pub struct EVACT_R(crate::FieldReader); +impl EVACT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(EVACT_A::NOACT), + 1 => Some(EVACT_A::TRIG), + 2 => Some(EVACT_A::CTRIG), + 3 => Some(EVACT_A::CBLOCK), + 4 => Some(EVACT_A::SUSPEND), + 5 => Some(EVACT_A::RESUME), + 6 => Some(EVACT_A::SSKIP), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NOACT`"] + #[inline(always)] + pub fn is_noact(&self) -> bool { + **self == EVACT_A::NOACT + } + #[doc = "Checks if the value of the field is `TRIG`"] + #[inline(always)] + pub fn is_trig(&self) -> bool { + **self == EVACT_A::TRIG + } + #[doc = "Checks if the value of the field is `CTRIG`"] + #[inline(always)] + pub fn is_ctrig(&self) -> bool { + **self == EVACT_A::CTRIG + } + #[doc = "Checks if the value of the field is `CBLOCK`"] + #[inline(always)] + pub fn is_cblock(&self) -> bool { + **self == EVACT_A::CBLOCK + } + #[doc = "Checks if the value of the field is `SUSPEND`"] + #[inline(always)] + pub fn is_suspend(&self) -> bool { + **self == EVACT_A::SUSPEND + } + #[doc = "Checks if the value of the field is `RESUME`"] + #[inline(always)] + pub fn is_resume(&self) -> bool { + **self == EVACT_A::RESUME + } + #[doc = "Checks if the value of the field is `SSKIP`"] + #[inline(always)] + pub fn is_sskip(&self) -> bool { + **self == EVACT_A::SSKIP + } +} +impl core::ops::Deref for EVACT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT` writer - Event Input Action"] +pub struct EVACT_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EVACT_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn noact(self) -> &'a mut W { + self.variant(EVACT_A::NOACT) + } + #[doc = "Transfer and periodic transfer trigger"] + #[inline(always)] + pub fn trig(self) -> &'a mut W { + self.variant(EVACT_A::TRIG) + } + #[doc = "Conditional transfer trigger"] + #[inline(always)] + pub fn ctrig(self) -> &'a mut W { + self.variant(EVACT_A::CTRIG) + } + #[doc = "Conditional block transfer"] + #[inline(always)] + pub fn cblock(self) -> &'a mut W { + self.variant(EVACT_A::CBLOCK) + } + #[doc = "Channel suspend operation"] + #[inline(always)] + pub fn suspend(self) -> &'a mut W { + self.variant(EVACT_A::SUSPEND) + } + #[doc = "Channel resume operation"] + #[inline(always)] + pub fn resume(self) -> &'a mut W { + self.variant(EVACT_A::RESUME) + } + #[doc = "Skip next block suspend action"] + #[inline(always)] + pub fn sskip(self) -> &'a mut W { + self.variant(EVACT_A::SSKIP) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Field `EVIE` reader - Channel Event Input Enable"] +pub struct EVIE_R(crate::FieldReader); +impl EVIE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVIE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVIE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVIE` writer - Channel Event Input Enable"] +pub struct EVIE_W<'a> { + w: &'a mut W, +} +impl<'a> EVIE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `EVOE` reader - Channel Event Output Enable"] +pub struct EVOE_R(crate::FieldReader); +impl EVOE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVOE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVOE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVOE` writer - Channel Event Output Enable"] +pub struct EVOE_W<'a> { + w: &'a mut W, +} +impl<'a> EVOE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Channel Arbitration Level\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum LVL_A { + #[doc = "0: Channel Priority Level 0"] + LVL0 = 0, + #[doc = "1: Channel Priority Level 1"] + LVL1 = 1, + #[doc = "2: Channel Priority Level 2"] + LVL2 = 2, + #[doc = "3: Channel Priority Level 3"] + LVL3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LVL_A) -> Self { + variant as _ + } +} +#[doc = "Field `LVL` reader - Channel Arbitration Level"] +pub struct LVL_R(crate::FieldReader); +impl LVL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LVL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> LVL_A { + match self.bits { + 0 => LVL_A::LVL0, + 1 => LVL_A::LVL1, + 2 => LVL_A::LVL2, + 3 => LVL_A::LVL3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `LVL0`"] + #[inline(always)] + pub fn is_lvl0(&self) -> bool { + **self == LVL_A::LVL0 + } + #[doc = "Checks if the value of the field is `LVL1`"] + #[inline(always)] + pub fn is_lvl1(&self) -> bool { + **self == LVL_A::LVL1 + } + #[doc = "Checks if the value of the field is `LVL2`"] + #[inline(always)] + pub fn is_lvl2(&self) -> bool { + **self == LVL_A::LVL2 + } + #[doc = "Checks if the value of the field is `LVL3`"] + #[inline(always)] + pub fn is_lvl3(&self) -> bool { + **self == LVL_A::LVL3 + } +} +impl core::ops::Deref for LVL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVL` writer - Channel Arbitration Level"] +pub struct LVL_W<'a> { + w: &'a mut W, +} +impl<'a> LVL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: LVL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Channel Priority Level 0"] + #[inline(always)] + pub fn lvl0(self) -> &'a mut W { + self.variant(LVL_A::LVL0) + } + #[doc = "Channel Priority Level 1"] + #[inline(always)] + pub fn lvl1(self) -> &'a mut W { + self.variant(LVL_A::LVL1) + } + #[doc = "Channel Priority Level 2"] + #[inline(always)] + pub fn lvl2(self) -> &'a mut W { + self.variant(LVL_A::LVL2) + } + #[doc = "Channel Priority Level 3"] + #[inline(always)] + pub fn lvl3(self) -> &'a mut W { + self.variant(LVL_A::LVL3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 5)) | ((value as u32 & 0x03) << 5); + self.w + } +} +#[doc = "Trigger Source\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum TRIGSRC_A { + #[doc = "0: Only software/event triggers"] + DISABLE = 0, + #[doc = "2: SERCOM0 RX Trigger"] + SERCOM0_RX = 2, + #[doc = "3: SERCOM0 TX Trigger"] + SERCOM0_TX = 3, + #[doc = "4: SERCOM1 RX Trigger"] + SERCOM1_RX = 4, + #[doc = "5: SERCOM1 TX Trigger"] + SERCOM1_TX = 5, + #[doc = "6: SERCOM2 RX Trigger"] + SERCOM2_RX = 6, + #[doc = "7: SERCOM2 TX Trigger"] + SERCOM2_TX = 7, + #[doc = "8: SERCOM3 RX Trigger"] + SERCOM3_RX = 8, + #[doc = "9: SERCOM3 TX Trigger"] + SERCOM3_TX = 9, + #[doc = "16: TCC0 Overflow Trigger"] + TCC0_OVF = 16, + #[doc = "17: TCC0 Match/Compare 0 Trigger"] + TCC0_MC0 = 17, + #[doc = "18: TCC0 Match/Compare 1 Trigger"] + TCC0_MC1 = 18, + #[doc = "19: TCC0 Match/Compare 2 Trigger"] + TCC0_MC2 = 19, + #[doc = "20: TCC0 Match/Compare 3 Trigger"] + TCC0_MC3 = 20, + #[doc = "21: TCC1 Overflow Trigger"] + TCC1_OVF = 21, + #[doc = "22: TCC1 Match/Compare 0 Trigger"] + TCC1_MC0 = 22, + #[doc = "23: TCC1 Match/Compare 1 Trigger"] + TCC1_MC1 = 23, + #[doc = "24: TCC2 Overflow Trigger"] + TCC2_OVF = 24, + #[doc = "25: TCC2 Match/Compare 0 Trigger"] + TCC2_MC0 = 25, + #[doc = "26: TCC2 Match/Compare 1 Trigger"] + TCC2_MC1 = 26, + #[doc = "27: TC0 Overflow Trigger"] + TC0_OVF = 27, + #[doc = "28: TC0 Match/Compare 0 Trigger"] + TC0_MC0 = 28, + #[doc = "29: TC0 Match/Compare 1 Trigger"] + TC0_MC1 = 29, + #[doc = "30: TC1 Overflow Trigger"] + TC1_OVF = 30, + #[doc = "31: TC1 Match/Compare 0 Trigger"] + TC1_MC0 = 31, + #[doc = "32: TC1 Match/Compare 1 Trigger"] + TC1_MC1 = 32, + #[doc = "33: TC2 Overflow Trigger"] + TC2_OVF = 33, + #[doc = "34: TC2 Match/Compare 0 Trigger"] + TC2_MC0 = 34, + #[doc = "35: TC2 Match/Compare 1 Trigger"] + TC2_MC1 = 35, + #[doc = "36: TC3 Overflow Trigger"] + TC3_OVF = 36, + #[doc = "37: TC3 Match/Compare 0 Trigger"] + TC3_MC0 = 37, + #[doc = "38: TC3 Match/Compare 1 Trigger"] + TC3_MC1 = 38, + #[doc = "39: TC4 Overflow Trigger"] + TC4_OVF = 39, + #[doc = "40: TC4 Match/Compare 0 Trigger"] + TC4_MC0 = 40, + #[doc = "41: TC4 Match/Compare 1 Trigger"] + TC4_MC1 = 41, + #[doc = "42: ADC0 Result Ready Trigger"] + ADC0_RESRDY = 42, + #[doc = "46: PTC End of Conversion Trigger"] + PTC_EOC = 46, + #[doc = "47: PTC Window Compare Trigger"] + PTC_WCOMP = 47, + #[doc = "48: PTC Sequence Trigger"] + PTC_SEQ = 48, +} +impl From for u8 { + #[inline(always)] + fn from(variant: TRIGSRC_A) -> Self { + variant as _ + } +} +#[doc = "Field `TRIGSRC` reader - Trigger Source"] +pub struct TRIGSRC_R(crate::FieldReader); +impl TRIGSRC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TRIGSRC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(TRIGSRC_A::DISABLE), + 2 => Some(TRIGSRC_A::SERCOM0_RX), + 3 => Some(TRIGSRC_A::SERCOM0_TX), + 4 => Some(TRIGSRC_A::SERCOM1_RX), + 5 => Some(TRIGSRC_A::SERCOM1_TX), + 6 => Some(TRIGSRC_A::SERCOM2_RX), + 7 => Some(TRIGSRC_A::SERCOM2_TX), + 8 => Some(TRIGSRC_A::SERCOM3_RX), + 9 => Some(TRIGSRC_A::SERCOM3_TX), + 16 => Some(TRIGSRC_A::TCC0_OVF), + 17 => Some(TRIGSRC_A::TCC0_MC0), + 18 => Some(TRIGSRC_A::TCC0_MC1), + 19 => Some(TRIGSRC_A::TCC0_MC2), + 20 => Some(TRIGSRC_A::TCC0_MC3), + 21 => Some(TRIGSRC_A::TCC1_OVF), + 22 => Some(TRIGSRC_A::TCC1_MC0), + 23 => Some(TRIGSRC_A::TCC1_MC1), + 24 => Some(TRIGSRC_A::TCC2_OVF), + 25 => Some(TRIGSRC_A::TCC2_MC0), + 26 => Some(TRIGSRC_A::TCC2_MC1), + 27 => Some(TRIGSRC_A::TC0_OVF), + 28 => Some(TRIGSRC_A::TC0_MC0), + 29 => Some(TRIGSRC_A::TC0_MC1), + 30 => Some(TRIGSRC_A::TC1_OVF), + 31 => Some(TRIGSRC_A::TC1_MC0), + 32 => Some(TRIGSRC_A::TC1_MC1), + 33 => Some(TRIGSRC_A::TC2_OVF), + 34 => Some(TRIGSRC_A::TC2_MC0), + 35 => Some(TRIGSRC_A::TC2_MC1), + 36 => Some(TRIGSRC_A::TC3_OVF), + 37 => Some(TRIGSRC_A::TC3_MC0), + 38 => Some(TRIGSRC_A::TC3_MC1), + 39 => Some(TRIGSRC_A::TC4_OVF), + 40 => Some(TRIGSRC_A::TC4_MC0), + 41 => Some(TRIGSRC_A::TC4_MC1), + 42 => Some(TRIGSRC_A::ADC0_RESRDY), + 46 => Some(TRIGSRC_A::PTC_EOC), + 47 => Some(TRIGSRC_A::PTC_WCOMP), + 48 => Some(TRIGSRC_A::PTC_SEQ), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == TRIGSRC_A::DISABLE + } + #[doc = "Checks if the value of the field is `SERCOM0_RX`"] + #[inline(always)] + pub fn is_sercom0_rx(&self) -> bool { + **self == TRIGSRC_A::SERCOM0_RX + } + #[doc = "Checks if the value of the field is `SERCOM0_TX`"] + #[inline(always)] + pub fn is_sercom0_tx(&self) -> bool { + **self == TRIGSRC_A::SERCOM0_TX + } + #[doc = "Checks if the value of the field is `SERCOM1_RX`"] + #[inline(always)] + pub fn is_sercom1_rx(&self) -> bool { + **self == TRIGSRC_A::SERCOM1_RX + } + #[doc = "Checks if the value of the field is `SERCOM1_TX`"] + #[inline(always)] + pub fn is_sercom1_tx(&self) -> bool { + **self == TRIGSRC_A::SERCOM1_TX + } + #[doc = "Checks if the value of the field is `SERCOM2_RX`"] + #[inline(always)] + pub fn is_sercom2_rx(&self) -> bool { + **self == TRIGSRC_A::SERCOM2_RX + } + #[doc = "Checks if the value of the field is `SERCOM2_TX`"] + #[inline(always)] + pub fn is_sercom2_tx(&self) -> bool { + **self == TRIGSRC_A::SERCOM2_TX + } + #[doc = "Checks if the value of the field is `SERCOM3_RX`"] + #[inline(always)] + pub fn is_sercom3_rx(&self) -> bool { + **self == TRIGSRC_A::SERCOM3_RX + } + #[doc = "Checks if the value of the field is `SERCOM3_TX`"] + #[inline(always)] + pub fn is_sercom3_tx(&self) -> bool { + **self == TRIGSRC_A::SERCOM3_TX + } + #[doc = "Checks if the value of the field is `TCC0_OVF`"] + #[inline(always)] + pub fn is_tcc0_ovf(&self) -> bool { + **self == TRIGSRC_A::TCC0_OVF + } + #[doc = "Checks if the value of the field is `TCC0_MC0`"] + #[inline(always)] + pub fn is_tcc0_mc0(&self) -> bool { + **self == TRIGSRC_A::TCC0_MC0 + } + #[doc = "Checks if the value of the field is `TCC0_MC1`"] + #[inline(always)] + pub fn is_tcc0_mc1(&self) -> bool { + **self == TRIGSRC_A::TCC0_MC1 + } + #[doc = "Checks if the value of the field is `TCC0_MC2`"] + #[inline(always)] + pub fn is_tcc0_mc2(&self) -> bool { + **self == TRIGSRC_A::TCC0_MC2 + } + #[doc = "Checks if the value of the field is `TCC0_MC3`"] + #[inline(always)] + pub fn is_tcc0_mc3(&self) -> bool { + **self == TRIGSRC_A::TCC0_MC3 + } + #[doc = "Checks if the value of the field is `TCC1_OVF`"] + #[inline(always)] + pub fn is_tcc1_ovf(&self) -> bool { + **self == TRIGSRC_A::TCC1_OVF + } + #[doc = "Checks if the value of the field is `TCC1_MC0`"] + #[inline(always)] + pub fn is_tcc1_mc0(&self) -> bool { + **self == TRIGSRC_A::TCC1_MC0 + } + #[doc = "Checks if the value of the field is `TCC1_MC1`"] + #[inline(always)] + pub fn is_tcc1_mc1(&self) -> bool { + **self == TRIGSRC_A::TCC1_MC1 + } + #[doc = "Checks if the value of the field is `TCC2_OVF`"] + #[inline(always)] + pub fn is_tcc2_ovf(&self) -> bool { + **self == TRIGSRC_A::TCC2_OVF + } + #[doc = "Checks if the value of the field is `TCC2_MC0`"] + #[inline(always)] + pub fn is_tcc2_mc0(&self) -> bool { + **self == TRIGSRC_A::TCC2_MC0 + } + #[doc = "Checks if the value of the field is `TCC2_MC1`"] + #[inline(always)] + pub fn is_tcc2_mc1(&self) -> bool { + **self == TRIGSRC_A::TCC2_MC1 + } + #[doc = "Checks if the value of the field is `TC0_OVF`"] + #[inline(always)] + pub fn is_tc0_ovf(&self) -> bool { + **self == TRIGSRC_A::TC0_OVF + } + #[doc = "Checks if the value of the field is `TC0_MC0`"] + #[inline(always)] + pub fn is_tc0_mc0(&self) -> bool { + **self == TRIGSRC_A::TC0_MC0 + } + #[doc = "Checks if the value of the field is `TC0_MC1`"] + #[inline(always)] + pub fn is_tc0_mc1(&self) -> bool { + **self == TRIGSRC_A::TC0_MC1 + } + #[doc = "Checks if the value of the field is `TC1_OVF`"] + #[inline(always)] + pub fn is_tc1_ovf(&self) -> bool { + **self == TRIGSRC_A::TC1_OVF + } + #[doc = "Checks if the value of the field is `TC1_MC0`"] + #[inline(always)] + pub fn is_tc1_mc0(&self) -> bool { + **self == TRIGSRC_A::TC1_MC0 + } + #[doc = "Checks if the value of the field is `TC1_MC1`"] + #[inline(always)] + pub fn is_tc1_mc1(&self) -> bool { + **self == TRIGSRC_A::TC1_MC1 + } + #[doc = "Checks if the value of the field is `TC2_OVF`"] + #[inline(always)] + pub fn is_tc2_ovf(&self) -> bool { + **self == TRIGSRC_A::TC2_OVF + } + #[doc = "Checks if the value of the field is `TC2_MC0`"] + #[inline(always)] + pub fn is_tc2_mc0(&self) -> bool { + **self == TRIGSRC_A::TC2_MC0 + } + #[doc = "Checks if the value of the field is `TC2_MC1`"] + #[inline(always)] + pub fn is_tc2_mc1(&self) -> bool { + **self == TRIGSRC_A::TC2_MC1 + } + #[doc = "Checks if the value of the field is `TC3_OVF`"] + #[inline(always)] + pub fn is_tc3_ovf(&self) -> bool { + **self == TRIGSRC_A::TC3_OVF + } + #[doc = "Checks if the value of the field is `TC3_MC0`"] + #[inline(always)] + pub fn is_tc3_mc0(&self) -> bool { + **self == TRIGSRC_A::TC3_MC0 + } + #[doc = "Checks if the value of the field is `TC3_MC1`"] + #[inline(always)] + pub fn is_tc3_mc1(&self) -> bool { + **self == TRIGSRC_A::TC3_MC1 + } + #[doc = "Checks if the value of the field is `TC4_OVF`"] + #[inline(always)] + pub fn is_tc4_ovf(&self) -> bool { + **self == TRIGSRC_A::TC4_OVF + } + #[doc = "Checks if the value of the field is `TC4_MC0`"] + #[inline(always)] + pub fn is_tc4_mc0(&self) -> bool { + **self == TRIGSRC_A::TC4_MC0 + } + #[doc = "Checks if the value of the field is `TC4_MC1`"] + #[inline(always)] + pub fn is_tc4_mc1(&self) -> bool { + **self == TRIGSRC_A::TC4_MC1 + } + #[doc = "Checks if the value of the field is `ADC0_RESRDY`"] + #[inline(always)] + pub fn is_adc0_resrdy(&self) -> bool { + **self == TRIGSRC_A::ADC0_RESRDY + } + #[doc = "Checks if the value of the field is `PTC_EOC`"] + #[inline(always)] + pub fn is_ptc_eoc(&self) -> bool { + **self == TRIGSRC_A::PTC_EOC + } + #[doc = "Checks if the value of the field is `PTC_WCOMP`"] + #[inline(always)] + pub fn is_ptc_wcomp(&self) -> bool { + **self == TRIGSRC_A::PTC_WCOMP + } + #[doc = "Checks if the value of the field is `PTC_SEQ`"] + #[inline(always)] + pub fn is_ptc_seq(&self) -> bool { + **self == TRIGSRC_A::PTC_SEQ + } +} +impl core::ops::Deref for TRIGSRC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRIGSRC` writer - Trigger Source"] +pub struct TRIGSRC_W<'a> { + w: &'a mut W, +} +impl<'a> TRIGSRC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TRIGSRC_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Only software/event triggers"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(TRIGSRC_A::DISABLE) + } + #[doc = "SERCOM0 RX Trigger"] + #[inline(always)] + pub fn sercom0_rx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM0_RX) + } + #[doc = "SERCOM0 TX Trigger"] + #[inline(always)] + pub fn sercom0_tx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM0_TX) + } + #[doc = "SERCOM1 RX Trigger"] + #[inline(always)] + pub fn sercom1_rx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM1_RX) + } + #[doc = "SERCOM1 TX Trigger"] + #[inline(always)] + pub fn sercom1_tx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM1_TX) + } + #[doc = "SERCOM2 RX Trigger"] + #[inline(always)] + pub fn sercom2_rx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM2_RX) + } + #[doc = "SERCOM2 TX Trigger"] + #[inline(always)] + pub fn sercom2_tx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM2_TX) + } + #[doc = "SERCOM3 RX Trigger"] + #[inline(always)] + pub fn sercom3_rx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM3_RX) + } + #[doc = "SERCOM3 TX Trigger"] + #[inline(always)] + pub fn sercom3_tx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM3_TX) + } + #[doc = "TCC0 Overflow Trigger"] + #[inline(always)] + pub fn tcc0_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC0_OVF) + } + #[doc = "TCC0 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tcc0_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC0_MC0) + } + #[doc = "TCC0 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tcc0_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC0_MC1) + } + #[doc = "TCC0 Match/Compare 2 Trigger"] + #[inline(always)] + pub fn tcc0_mc2(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC0_MC2) + } + #[doc = "TCC0 Match/Compare 3 Trigger"] + #[inline(always)] + pub fn tcc0_mc3(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC0_MC3) + } + #[doc = "TCC1 Overflow Trigger"] + #[inline(always)] + pub fn tcc1_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC1_OVF) + } + #[doc = "TCC1 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tcc1_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC1_MC0) + } + #[doc = "TCC1 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tcc1_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC1_MC1) + } + #[doc = "TCC2 Overflow Trigger"] + #[inline(always)] + pub fn tcc2_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC2_OVF) + } + #[doc = "TCC2 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tcc2_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC2_MC0) + } + #[doc = "TCC2 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tcc2_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC2_MC1) + } + #[doc = "TC0 Overflow Trigger"] + #[inline(always)] + pub fn tc0_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC0_OVF) + } + #[doc = "TC0 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tc0_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC0_MC0) + } + #[doc = "TC0 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tc0_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC0_MC1) + } + #[doc = "TC1 Overflow Trigger"] + #[inline(always)] + pub fn tc1_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC1_OVF) + } + #[doc = "TC1 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tc1_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC1_MC0) + } + #[doc = "TC1 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tc1_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC1_MC1) + } + #[doc = "TC2 Overflow Trigger"] + #[inline(always)] + pub fn tc2_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC2_OVF) + } + #[doc = "TC2 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tc2_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC2_MC0) + } + #[doc = "TC2 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tc2_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC2_MC1) + } + #[doc = "TC3 Overflow Trigger"] + #[inline(always)] + pub fn tc3_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC3_OVF) + } + #[doc = "TC3 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tc3_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC3_MC0) + } + #[doc = "TC3 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tc3_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC3_MC1) + } + #[doc = "TC4 Overflow Trigger"] + #[inline(always)] + pub fn tc4_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC4_OVF) + } + #[doc = "TC4 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tc4_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC4_MC0) + } + #[doc = "TC4 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tc4_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC4_MC1) + } + #[doc = "ADC0 Result Ready Trigger"] + #[inline(always)] + pub fn adc0_resrdy(self) -> &'a mut W { + self.variant(TRIGSRC_A::ADC0_RESRDY) + } + #[doc = "PTC End of Conversion Trigger"] + #[inline(always)] + pub fn ptc_eoc(self) -> &'a mut W { + self.variant(TRIGSRC_A::PTC_EOC) + } + #[doc = "PTC Window Compare Trigger"] + #[inline(always)] + pub fn ptc_wcomp(self) -> &'a mut W { + self.variant(TRIGSRC_A::PTC_WCOMP) + } + #[doc = "PTC Sequence Trigger"] + #[inline(always)] + pub fn ptc_seq(self) -> &'a mut W { + self.variant(TRIGSRC_A::PTC_SEQ) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 8)) | ((value as u32 & 0x3f) << 8); + self.w + } +} +#[doc = "Trigger Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum TRIGACT_A { + #[doc = "0: One trigger required for each block transfer"] + BLOCK = 0, + #[doc = "2: One trigger required for each beat transfer"] + BEAT = 2, + #[doc = "3: One trigger required for each transaction"] + TRANSACTION = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: TRIGACT_A) -> Self { + variant as _ + } +} +#[doc = "Field `TRIGACT` reader - Trigger Action"] +pub struct TRIGACT_R(crate::FieldReader); +impl TRIGACT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TRIGACT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(TRIGACT_A::BLOCK), + 2 => Some(TRIGACT_A::BEAT), + 3 => Some(TRIGACT_A::TRANSACTION), + _ => None, + } + } + #[doc = "Checks if the value of the field is `BLOCK`"] + #[inline(always)] + pub fn is_block(&self) -> bool { + **self == TRIGACT_A::BLOCK + } + #[doc = "Checks if the value of the field is `BEAT`"] + #[inline(always)] + pub fn is_beat(&self) -> bool { + **self == TRIGACT_A::BEAT + } + #[doc = "Checks if the value of the field is `TRANSACTION`"] + #[inline(always)] + pub fn is_transaction(&self) -> bool { + **self == TRIGACT_A::TRANSACTION + } +} +impl core::ops::Deref for TRIGACT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRIGACT` writer - Trigger Action"] +pub struct TRIGACT_W<'a> { + w: &'a mut W, +} +impl<'a> TRIGACT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TRIGACT_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "One trigger required for each block transfer"] + #[inline(always)] + pub fn block(self) -> &'a mut W { + self.variant(TRIGACT_A::BLOCK) + } + #[doc = "One trigger required for each beat transfer"] + #[inline(always)] + pub fn beat(self) -> &'a mut W { + self.variant(TRIGACT_A::BEAT) + } + #[doc = "One trigger required for each transaction"] + #[inline(always)] + pub fn transaction(self) -> &'a mut W { + self.variant(TRIGACT_A::TRANSACTION) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 22)) | ((value as u32 & 0x03) << 22); + self.w + } +} +#[doc = "Software Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NOACT = 0, + #[doc = "1: Channel suspend operation"] + SUSPEND = 1, + #[doc = "2: Channel resume operation"] + RESUME = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Software Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NOACT), + 1 => Some(CMD_A::SUSPEND), + 2 => Some(CMD_A::RESUME), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NOACT`"] + #[inline(always)] + pub fn is_noact(&self) -> bool { + **self == CMD_A::NOACT + } + #[doc = "Checks if the value of the field is `SUSPEND`"] + #[inline(always)] + pub fn is_suspend(&self) -> bool { + **self == CMD_A::SUSPEND + } + #[doc = "Checks if the value of the field is `RESUME`"] + #[inline(always)] + pub fn is_resume(&self) -> bool { + **self == CMD_A::RESUME + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Software Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn noact(self) -> &'a mut W { + self.variant(CMD_A::NOACT) + } + #[doc = "Channel suspend operation"] + #[inline(always)] + pub fn suspend(self) -> &'a mut W { + self.variant(CMD_A::SUSPEND) + } + #[doc = "Channel resume operation"] + #[inline(always)] + pub fn resume(self) -> &'a mut W { + self.variant(CMD_A::RESUME) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 24)) | ((value as u32 & 0x03) << 24); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Event Input Action"] + #[inline(always)] + pub fn evact(&self) -> EVACT_R { + EVACT_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 3 - Channel Event Input Enable"] + #[inline(always)] + pub fn evie(&self) -> EVIE_R { + EVIE_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Channel Event Output Enable"] + #[inline(always)] + pub fn evoe(&self) -> EVOE_R { + EVOE_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bits 5:6 - Channel Arbitration Level"] + #[inline(always)] + pub fn lvl(&self) -> LVL_R { + LVL_R::new(((self.bits >> 5) & 0x03) as u8) + } + #[doc = "Bits 8:13 - Trigger Source"] + #[inline(always)] + pub fn trigsrc(&self) -> TRIGSRC_R { + TRIGSRC_R::new(((self.bits >> 8) & 0x3f) as u8) + } + #[doc = "Bits 22:23 - Trigger Action"] + #[inline(always)] + pub fn trigact(&self) -> TRIGACT_R { + TRIGACT_R::new(((self.bits >> 22) & 0x03) as u8) + } + #[doc = "Bits 24:25 - Software Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 24) & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Event Input Action"] + #[inline(always)] + pub fn evact(&mut self) -> EVACT_W { + EVACT_W { w: self } + } + #[doc = "Bit 3 - Channel Event Input Enable"] + #[inline(always)] + pub fn evie(&mut self) -> EVIE_W { + EVIE_W { w: self } + } + #[doc = "Bit 4 - Channel Event Output Enable"] + #[inline(always)] + pub fn evoe(&mut self) -> EVOE_W { + EVOE_W { w: self } + } + #[doc = "Bits 5:6 - Channel Arbitration Level"] + #[inline(always)] + pub fn lvl(&mut self) -> LVL_W { + LVL_W { w: self } + } + #[doc = "Bits 8:13 - Trigger Source"] + #[inline(always)] + pub fn trigsrc(&mut self) -> TRIGSRC_W { + TRIGSRC_W { w: self } + } + #[doc = "Bits 22:23 - Trigger Action"] + #[inline(always)] + pub fn trigact(&mut self) -> TRIGACT_W { + TRIGACT_W { w: self } + } + #[doc = "Bits 24:25 - Software Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chctrlb](index.html) module"] +pub struct CHCTRLB_SPEC; +impl crate::RegisterSpec for CHCTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [chctrlb::R](R) reader structure"] +impl crate::Readable for CHCTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chctrlb::W](W) writer structure"] +impl crate::Writable for CHCTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHCTRLB to value 0"] +impl crate::Resettable for CHCTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/dmac/chid.rs b/pac/atsamc20j/src/dmac/chid.rs new file mode 100644 index 000000000000..1f778a7fc6f0 --- /dev/null +++ b/pac/atsamc20j/src/dmac/chid.rs @@ -0,0 +1,103 @@ +#[doc = "Register `CHID` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHID` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ID` reader - Channel ID"] +pub struct ID_R(crate::FieldReader); +impl ID_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ID_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ID_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ID` writer - Channel ID"] +pub struct ID_W<'a> { + w: &'a mut W, +} +impl<'a> ID_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Channel ID"] + #[inline(always)] + pub fn id(&self) -> ID_R { + ID_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Channel ID"] + #[inline(always)] + pub fn id(&mut self) -> ID_W { + ID_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel ID\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chid](index.html) module"] +pub struct CHID_SPEC; +impl crate::RegisterSpec for CHID_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [chid::R](R) reader structure"] +impl crate::Readable for CHID_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chid::W](W) writer structure"] +impl crate::Writable for CHID_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHID to value 0"] +impl crate::Resettable for CHID_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/dmac/chintenclr.rs b/pac/atsamc20j/src/dmac/chintenclr.rs new file mode 100644 index 000000000000..5ae3096f9ab8 --- /dev/null +++ b/pac/atsamc20j/src/dmac/chintenclr.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CHINTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHINTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TERR` reader - Channel Transfer Error Interrupt Enable"] +pub struct TERR_R(crate::FieldReader); +impl TERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TERR` writer - Channel Transfer Error Interrupt Enable"] +pub struct TERR_W<'a> { + w: &'a mut W, +} +impl<'a> TERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TCMPL` reader - Channel Transfer Complete Interrupt Enable"] +pub struct TCMPL_R(crate::FieldReader); +impl TCMPL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCMPL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCMPL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCMPL` writer - Channel Transfer Complete Interrupt Enable"] +pub struct TCMPL_W<'a> { + w: &'a mut W, +} +impl<'a> TCMPL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SUSP` reader - Channel Suspend Interrupt Enable"] +pub struct SUSP_R(crate::FieldReader); +impl SUSP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SUSP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SUSP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SUSP` writer - Channel Suspend Interrupt Enable"] +pub struct SUSP_W<'a> { + w: &'a mut W, +} +impl<'a> SUSP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Channel Transfer Error Interrupt Enable"] + #[inline(always)] + pub fn terr(&self) -> TERR_R { + TERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel Transfer Complete Interrupt Enable"] + #[inline(always)] + pub fn tcmpl(&self) -> TCMPL_R { + TCMPL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel Suspend Interrupt Enable"] + #[inline(always)] + pub fn susp(&self) -> SUSP_R { + SUSP_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel Transfer Error Interrupt Enable"] + #[inline(always)] + pub fn terr(&mut self) -> TERR_W { + TERR_W { w: self } + } + #[doc = "Bit 1 - Channel Transfer Complete Interrupt Enable"] + #[inline(always)] + pub fn tcmpl(&mut self) -> TCMPL_W { + TCMPL_W { w: self } + } + #[doc = "Bit 2 - Channel Suspend Interrupt Enable"] + #[inline(always)] + pub fn susp(&mut self) -> SUSP_W { + SUSP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chintenclr](index.html) module"] +pub struct CHINTENCLR_SPEC; +impl crate::RegisterSpec for CHINTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [chintenclr::R](R) reader structure"] +impl crate::Readable for CHINTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chintenclr::W](W) writer structure"] +impl crate::Writable for CHINTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHINTENCLR to value 0"] +impl crate::Resettable for CHINTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/dmac/chintenset.rs b/pac/atsamc20j/src/dmac/chintenset.rs new file mode 100644 index 000000000000..2e7daef20a6f --- /dev/null +++ b/pac/atsamc20j/src/dmac/chintenset.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CHINTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHINTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TERR` reader - Channel Transfer Error Interrupt Enable"] +pub struct TERR_R(crate::FieldReader); +impl TERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TERR` writer - Channel Transfer Error Interrupt Enable"] +pub struct TERR_W<'a> { + w: &'a mut W, +} +impl<'a> TERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TCMPL` reader - Channel Transfer Complete Interrupt Enable"] +pub struct TCMPL_R(crate::FieldReader); +impl TCMPL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCMPL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCMPL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCMPL` writer - Channel Transfer Complete Interrupt Enable"] +pub struct TCMPL_W<'a> { + w: &'a mut W, +} +impl<'a> TCMPL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SUSP` reader - Channel Suspend Interrupt Enable"] +pub struct SUSP_R(crate::FieldReader); +impl SUSP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SUSP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SUSP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SUSP` writer - Channel Suspend Interrupt Enable"] +pub struct SUSP_W<'a> { + w: &'a mut W, +} +impl<'a> SUSP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Channel Transfer Error Interrupt Enable"] + #[inline(always)] + pub fn terr(&self) -> TERR_R { + TERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel Transfer Complete Interrupt Enable"] + #[inline(always)] + pub fn tcmpl(&self) -> TCMPL_R { + TCMPL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel Suspend Interrupt Enable"] + #[inline(always)] + pub fn susp(&self) -> SUSP_R { + SUSP_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel Transfer Error Interrupt Enable"] + #[inline(always)] + pub fn terr(&mut self) -> TERR_W { + TERR_W { w: self } + } + #[doc = "Bit 1 - Channel Transfer Complete Interrupt Enable"] + #[inline(always)] + pub fn tcmpl(&mut self) -> TCMPL_W { + TCMPL_W { w: self } + } + #[doc = "Bit 2 - Channel Suspend Interrupt Enable"] + #[inline(always)] + pub fn susp(&mut self) -> SUSP_W { + SUSP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chintenset](index.html) module"] +pub struct CHINTENSET_SPEC; +impl crate::RegisterSpec for CHINTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [chintenset::R](R) reader structure"] +impl crate::Readable for CHINTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chintenset::W](W) writer structure"] +impl crate::Writable for CHINTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHINTENSET to value 0"] +impl crate::Resettable for CHINTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/dmac/chintflag.rs b/pac/atsamc20j/src/dmac/chintflag.rs new file mode 100644 index 000000000000..4e61d6510c30 --- /dev/null +++ b/pac/atsamc20j/src/dmac/chintflag.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CHINTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHINTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TERR` reader - Channel Transfer Error"] +pub struct TERR_R(crate::FieldReader); +impl TERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TERR` writer - Channel Transfer Error"] +pub struct TERR_W<'a> { + w: &'a mut W, +} +impl<'a> TERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TCMPL` reader - Channel Transfer Complete"] +pub struct TCMPL_R(crate::FieldReader); +impl TCMPL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCMPL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCMPL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCMPL` writer - Channel Transfer Complete"] +pub struct TCMPL_W<'a> { + w: &'a mut W, +} +impl<'a> TCMPL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SUSP` reader - Channel Suspend"] +pub struct SUSP_R(crate::FieldReader); +impl SUSP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SUSP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SUSP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SUSP` writer - Channel Suspend"] +pub struct SUSP_W<'a> { + w: &'a mut W, +} +impl<'a> SUSP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Channel Transfer Error"] + #[inline(always)] + pub fn terr(&self) -> TERR_R { + TERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel Transfer Complete"] + #[inline(always)] + pub fn tcmpl(&self) -> TCMPL_R { + TCMPL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel Suspend"] + #[inline(always)] + pub fn susp(&self) -> SUSP_R { + SUSP_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel Transfer Error"] + #[inline(always)] + pub fn terr(&mut self) -> TERR_W { + TERR_W { w: self } + } + #[doc = "Bit 1 - Channel Transfer Complete"] + #[inline(always)] + pub fn tcmpl(&mut self) -> TCMPL_W { + TCMPL_W { w: self } + } + #[doc = "Bit 2 - Channel Suspend"] + #[inline(always)] + pub fn susp(&mut self) -> SUSP_W { + SUSP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chintflag](index.html) module"] +pub struct CHINTFLAG_SPEC; +impl crate::RegisterSpec for CHINTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [chintflag::R](R) reader structure"] +impl crate::Readable for CHINTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chintflag::W](W) writer structure"] +impl crate::Writable for CHINTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHINTFLAG to value 0"] +impl crate::Resettable for CHINTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/dmac/chstatus.rs b/pac/atsamc20j/src/dmac/chstatus.rs new file mode 100644 index 000000000000..98a84345d4f7 --- /dev/null +++ b/pac/atsamc20j/src/dmac/chstatus.rs @@ -0,0 +1,93 @@ +#[doc = "Register `CHSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PEND` reader - Channel Pending"] +pub struct PEND_R(crate::FieldReader); +impl PEND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSY` reader - Channel Busy"] +pub struct BUSY_R(crate::FieldReader); +impl BUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FERR` reader - Channel Fetch Error"] +pub struct FERR_R(crate::FieldReader); +impl FERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Channel Pending"] + #[inline(always)] + pub fn pend(&self) -> PEND_R { + PEND_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel Busy"] + #[inline(always)] + pub fn busy(&self) -> BUSY_R { + BUSY_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel Fetch Error"] + #[inline(always)] + pub fn ferr(&self) -> FERR_R { + FERR_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +#[doc = "Channel Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chstatus](index.html) module"] +pub struct CHSTATUS_SPEC; +impl crate::RegisterSpec for CHSTATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [chstatus::R](R) reader structure"] +impl crate::Readable for CHSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CHSTATUS to value 0"] +impl crate::Resettable for CHSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/dmac/crcchksum.rs b/pac/atsamc20j/src/dmac/crcchksum.rs new file mode 100644 index 000000000000..89eb5b38a093 --- /dev/null +++ b/pac/atsamc20j/src/dmac/crcchksum.rs @@ -0,0 +1,103 @@ +#[doc = "Register `CRCCHKSUM` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CRCCHKSUM` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CRCCHKSUM` reader - CRC Checksum"] +pub struct CRCCHKSUM_R(crate::FieldReader); +impl CRCCHKSUM_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CRCCHKSUM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CRCCHKSUM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCCHKSUM` writer - CRC Checksum"] +pub struct CRCCHKSUM_W<'a> { + w: &'a mut W, +} +impl<'a> CRCCHKSUM_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - CRC Checksum"] + #[inline(always)] + pub fn crcchksum(&self) -> CRCCHKSUM_R { + CRCCHKSUM_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - CRC Checksum"] + #[inline(always)] + pub fn crcchksum(&mut self) -> CRCCHKSUM_W { + CRCCHKSUM_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CRC Checksum\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [crcchksum](index.html) module"] +pub struct CRCCHKSUM_SPEC; +impl crate::RegisterSpec for CRCCHKSUM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [crcchksum::R](R) reader structure"] +impl crate::Readable for CRCCHKSUM_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [crcchksum::W](W) writer structure"] +impl crate::Writable for CRCCHKSUM_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CRCCHKSUM to value 0"] +impl crate::Resettable for CRCCHKSUM_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/dmac/crcctrl.rs b/pac/atsamc20j/src/dmac/crcctrl.rs new file mode 100644 index 000000000000..b8daf7b8259d --- /dev/null +++ b/pac/atsamc20j/src/dmac/crcctrl.rs @@ -0,0 +1,337 @@ +#[doc = "Register `CRCCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CRCCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "CRC Beat Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CRCBEATSIZE_A { + #[doc = "0: 8-bit bus transfer"] + BYTE = 0, + #[doc = "1: 16-bit bus transfer"] + HWORD = 1, + #[doc = "2: 32-bit bus transfer"] + WORD = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CRCBEATSIZE_A) -> Self { + variant as _ + } +} +#[doc = "Field `CRCBEATSIZE` reader - CRC Beat Size"] +pub struct CRCBEATSIZE_R(crate::FieldReader); +impl CRCBEATSIZE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CRCBEATSIZE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CRCBEATSIZE_A::BYTE), + 1 => Some(CRCBEATSIZE_A::HWORD), + 2 => Some(CRCBEATSIZE_A::WORD), + _ => None, + } + } + #[doc = "Checks if the value of the field is `BYTE`"] + #[inline(always)] + pub fn is_byte(&self) -> bool { + **self == CRCBEATSIZE_A::BYTE + } + #[doc = "Checks if the value of the field is `HWORD`"] + #[inline(always)] + pub fn is_hword(&self) -> bool { + **self == CRCBEATSIZE_A::HWORD + } + #[doc = "Checks if the value of the field is `WORD`"] + #[inline(always)] + pub fn is_word(&self) -> bool { + **self == CRCBEATSIZE_A::WORD + } +} +impl core::ops::Deref for CRCBEATSIZE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCBEATSIZE` writer - CRC Beat Size"] +pub struct CRCBEATSIZE_W<'a> { + w: &'a mut W, +} +impl<'a> CRCBEATSIZE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CRCBEATSIZE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8-bit bus transfer"] + #[inline(always)] + pub fn byte(self) -> &'a mut W { + self.variant(CRCBEATSIZE_A::BYTE) + } + #[doc = "16-bit bus transfer"] + #[inline(always)] + pub fn hword(self) -> &'a mut W { + self.variant(CRCBEATSIZE_A::HWORD) + } + #[doc = "32-bit bus transfer"] + #[inline(always)] + pub fn word(self) -> &'a mut W { + self.variant(CRCBEATSIZE_A::WORD) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u16 & 0x03); + self.w + } +} +#[doc = "CRC Polynomial Type\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CRCPOLY_A { + #[doc = "0: CRC-16 (CRC-CCITT)"] + CRC16 = 0, + #[doc = "1: CRC32 (IEEE 802.3)"] + CRC32 = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CRCPOLY_A) -> Self { + variant as _ + } +} +#[doc = "Field `CRCPOLY` reader - CRC Polynomial Type"] +pub struct CRCPOLY_R(crate::FieldReader); +impl CRCPOLY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CRCPOLY_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CRCPOLY_A::CRC16), + 1 => Some(CRCPOLY_A::CRC32), + _ => None, + } + } + #[doc = "Checks if the value of the field is `CRC16`"] + #[inline(always)] + pub fn is_crc16(&self) -> bool { + **self == CRCPOLY_A::CRC16 + } + #[doc = "Checks if the value of the field is `CRC32`"] + #[inline(always)] + pub fn is_crc32(&self) -> bool { + **self == CRCPOLY_A::CRC32 + } +} +impl core::ops::Deref for CRCPOLY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCPOLY` writer - CRC Polynomial Type"] +pub struct CRCPOLY_W<'a> { + w: &'a mut W, +} +impl<'a> CRCPOLY_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CRCPOLY_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "CRC-16 (CRC-CCITT)"] + #[inline(always)] + pub fn crc16(self) -> &'a mut W { + self.variant(CRCPOLY_A::CRC16) + } + #[doc = "CRC32 (IEEE 802.3)"] + #[inline(always)] + pub fn crc32(self) -> &'a mut W { + self.variant(CRCPOLY_A::CRC32) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u16 & 0x03) << 2); + self.w + } +} +#[doc = "CRC Input Source\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CRCSRC_A { + #[doc = "0: No action"] + NOACT = 0, + #[doc = "1: I/O interface"] + IO = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CRCSRC_A) -> Self { + variant as _ + } +} +#[doc = "Field `CRCSRC` reader - CRC Input Source"] +pub struct CRCSRC_R(crate::FieldReader); +impl CRCSRC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CRCSRC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CRCSRC_A::NOACT), + 1 => Some(CRCSRC_A::IO), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NOACT`"] + #[inline(always)] + pub fn is_noact(&self) -> bool { + **self == CRCSRC_A::NOACT + } + #[doc = "Checks if the value of the field is `IO`"] + #[inline(always)] + pub fn is_io(&self) -> bool { + **self == CRCSRC_A::IO + } +} +impl core::ops::Deref for CRCSRC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCSRC` writer - CRC Input Source"] +pub struct CRCSRC_W<'a> { + w: &'a mut W, +} +impl<'a> CRCSRC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CRCSRC_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn noact(self) -> &'a mut W { + self.variant(CRCSRC_A::NOACT) + } + #[doc = "I/O interface"] + #[inline(always)] + pub fn io(self) -> &'a mut W { + self.variant(CRCSRC_A::IO) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 8)) | ((value as u16 & 0x3f) << 8); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - CRC Beat Size"] + #[inline(always)] + pub fn crcbeatsize(&self) -> CRCBEATSIZE_R { + CRCBEATSIZE_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bits 2:3 - CRC Polynomial Type"] + #[inline(always)] + pub fn crcpoly(&self) -> CRCPOLY_R { + CRCPOLY_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bits 8:13 - CRC Input Source"] + #[inline(always)] + pub fn crcsrc(&self) -> CRCSRC_R { + CRCSRC_R::new(((self.bits >> 8) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - CRC Beat Size"] + #[inline(always)] + pub fn crcbeatsize(&mut self) -> CRCBEATSIZE_W { + CRCBEATSIZE_W { w: self } + } + #[doc = "Bits 2:3 - CRC Polynomial Type"] + #[inline(always)] + pub fn crcpoly(&mut self) -> CRCPOLY_W { + CRCPOLY_W { w: self } + } + #[doc = "Bits 8:13 - CRC Input Source"] + #[inline(always)] + pub fn crcsrc(&mut self) -> CRCSRC_W { + CRCSRC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CRC Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [crcctrl](index.html) module"] +pub struct CRCCTRL_SPEC; +impl crate::RegisterSpec for CRCCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [crcctrl::R](R) reader structure"] +impl crate::Readable for CRCCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [crcctrl::W](W) writer structure"] +impl crate::Writable for CRCCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CRCCTRL to value 0"] +impl crate::Resettable for CRCCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/dmac/crcdatain.rs b/pac/atsamc20j/src/dmac/crcdatain.rs new file mode 100644 index 000000000000..ca0879a12136 --- /dev/null +++ b/pac/atsamc20j/src/dmac/crcdatain.rs @@ -0,0 +1,103 @@ +#[doc = "Register `CRCDATAIN` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CRCDATAIN` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CRCDATAIN` reader - CRC Data Input"] +pub struct CRCDATAIN_R(crate::FieldReader); +impl CRCDATAIN_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CRCDATAIN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CRCDATAIN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCDATAIN` writer - CRC Data Input"] +pub struct CRCDATAIN_W<'a> { + w: &'a mut W, +} +impl<'a> CRCDATAIN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - CRC Data Input"] + #[inline(always)] + pub fn crcdatain(&self) -> CRCDATAIN_R { + CRCDATAIN_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - CRC Data Input"] + #[inline(always)] + pub fn crcdatain(&mut self) -> CRCDATAIN_W { + CRCDATAIN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CRC Data Input\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [crcdatain](index.html) module"] +pub struct CRCDATAIN_SPEC; +impl crate::RegisterSpec for CRCDATAIN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [crcdatain::R](R) reader structure"] +impl crate::Readable for CRCDATAIN_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [crcdatain::W](W) writer structure"] +impl crate::Writable for CRCDATAIN_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CRCDATAIN to value 0"] +impl crate::Resettable for CRCDATAIN_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/dmac/crcstatus.rs b/pac/atsamc20j/src/dmac/crcstatus.rs new file mode 100644 index 000000000000..a132e9d5cd03 --- /dev/null +++ b/pac/atsamc20j/src/dmac/crcstatus.rs @@ -0,0 +1,160 @@ +#[doc = "Register `CRCSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CRCSTATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CRCBUSY` reader - CRC Module Busy"] +pub struct CRCBUSY_R(crate::FieldReader); +impl CRCBUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CRCBUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CRCBUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCBUSY` writer - CRC Module Busy"] +pub struct CRCBUSY_W<'a> { + w: &'a mut W, +} +impl<'a> CRCBUSY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `CRCZERO` reader - CRC Zero"] +pub struct CRCZERO_R(crate::FieldReader); +impl CRCZERO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CRCZERO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CRCZERO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCZERO` writer - CRC Zero"] +pub struct CRCZERO_W<'a> { + w: &'a mut W, +} +impl<'a> CRCZERO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - CRC Module Busy"] + #[inline(always)] + pub fn crcbusy(&self) -> CRCBUSY_R { + CRCBUSY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - CRC Zero"] + #[inline(always)] + pub fn crczero(&self) -> CRCZERO_R { + CRCZERO_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - CRC Module Busy"] + #[inline(always)] + pub fn crcbusy(&mut self) -> CRCBUSY_W { + CRCBUSY_W { w: self } + } + #[doc = "Bit 1 - CRC Zero"] + #[inline(always)] + pub fn crczero(&mut self) -> CRCZERO_W { + CRCZERO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CRC Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [crcstatus](index.html) module"] +pub struct CRCSTATUS_SPEC; +impl crate::RegisterSpec for CRCSTATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [crcstatus::R](R) reader structure"] +impl crate::Readable for CRCSTATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [crcstatus::W](W) writer structure"] +impl crate::Writable for CRCSTATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CRCSTATUS to value 0"] +impl crate::Resettable for CRCSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/dmac/ctrl.rs b/pac/atsamc20j/src/dmac/ctrl.rs new file mode 100644 index 000000000000..fabae9d82a6c --- /dev/null +++ b/pac/atsamc20j/src/dmac/ctrl.rs @@ -0,0 +1,395 @@ +#[doc = "Register `CTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `DMAENABLE` reader - DMA Enable"] +pub struct DMAENABLE_R(crate::FieldReader); +impl DMAENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DMAENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DMAENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DMAENABLE` writer - DMA Enable"] +pub struct DMAENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> DMAENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CRCENABLE` reader - CRC Enable"] +pub struct CRCENABLE_R(crate::FieldReader); +impl CRCENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CRCENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CRCENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCENABLE` writer - CRC Enable"] +pub struct CRCENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> CRCENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `LVLEN0` reader - Priority Level 0 Enable"] +pub struct LVLEN0_R(crate::FieldReader); +impl LVLEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LVLEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLEN0` writer - Priority Level 0 Enable"] +pub struct LVLEN0_W<'a> { + w: &'a mut W, +} +impl<'a> LVLEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `LVLEN1` reader - Priority Level 1 Enable"] +pub struct LVLEN1_R(crate::FieldReader); +impl LVLEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LVLEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLEN1` writer - Priority Level 1 Enable"] +pub struct LVLEN1_W<'a> { + w: &'a mut W, +} +impl<'a> LVLEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `LVLEN2` reader - Priority Level 2 Enable"] +pub struct LVLEN2_R(crate::FieldReader); +impl LVLEN2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LVLEN2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEN2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLEN2` writer - Priority Level 2 Enable"] +pub struct LVLEN2_W<'a> { + w: &'a mut W, +} +impl<'a> LVLEN2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u16 & 0x01) << 10); + self.w + } +} +#[doc = "Field `LVLEN3` reader - Priority Level 3 Enable"] +pub struct LVLEN3_R(crate::FieldReader); +impl LVLEN3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LVLEN3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEN3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLEN3` writer - Priority Level 3 Enable"] +pub struct LVLEN3_W<'a> { + w: &'a mut W, +} +impl<'a> LVLEN3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u16 & 0x01) << 11); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - DMA Enable"] + #[inline(always)] + pub fn dmaenable(&self) -> DMAENABLE_R { + DMAENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - CRC Enable"] + #[inline(always)] + pub fn crcenable(&self) -> CRCENABLE_R { + CRCENABLE_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 8 - Priority Level 0 Enable"] + #[inline(always)] + pub fn lvlen0(&self) -> LVLEN0_R { + LVLEN0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Priority Level 1 Enable"] + #[inline(always)] + pub fn lvlen1(&self) -> LVLEN1_R { + LVLEN1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Priority Level 2 Enable"] + #[inline(always)] + pub fn lvlen2(&self) -> LVLEN2_R { + LVLEN2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Priority Level 3 Enable"] + #[inline(always)] + pub fn lvlen3(&self) -> LVLEN3_R { + LVLEN3_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - DMA Enable"] + #[inline(always)] + pub fn dmaenable(&mut self) -> DMAENABLE_W { + DMAENABLE_W { w: self } + } + #[doc = "Bit 2 - CRC Enable"] + #[inline(always)] + pub fn crcenable(&mut self) -> CRCENABLE_W { + CRCENABLE_W { w: self } + } + #[doc = "Bit 8 - Priority Level 0 Enable"] + #[inline(always)] + pub fn lvlen0(&mut self) -> LVLEN0_W { + LVLEN0_W { w: self } + } + #[doc = "Bit 9 - Priority Level 1 Enable"] + #[inline(always)] + pub fn lvlen1(&mut self) -> LVLEN1_W { + LVLEN1_W { w: self } + } + #[doc = "Bit 10 - Priority Level 2 Enable"] + #[inline(always)] + pub fn lvlen2(&mut self) -> LVLEN2_W { + LVLEN2_W { w: self } + } + #[doc = "Bit 11 - Priority Level 3 Enable"] + #[inline(always)] + pub fn lvlen3(&mut self) -> LVLEN3_W { + LVLEN3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"] +pub struct CTRL_SPEC; +impl crate::RegisterSpec for CTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrl::R](R) reader structure"] +impl crate::Readable for CTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"] +impl crate::Writable for CTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/dmac/dbgctrl.rs b/pac/atsamc20j/src/dmac/dbgctrl.rs new file mode 100644 index 000000000000..53636eb2b339 --- /dev/null +++ b/pac/atsamc20j/src/dmac/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Debug Run"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Debug Run"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/dmac/intpend.rs b/pac/atsamc20j/src/dmac/intpend.rs new file mode 100644 index 000000000000..1988b30a190b --- /dev/null +++ b/pac/atsamc20j/src/dmac/intpend.rs @@ -0,0 +1,385 @@ +#[doc = "Register `INTPEND` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTPEND` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ID` reader - Channel ID"] +pub struct ID_R(crate::FieldReader); +impl ID_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ID_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ID_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ID` writer - Channel ID"] +pub struct ID_W<'a> { + w: &'a mut W, +} +impl<'a> ID_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u16 & 0x07); + self.w + } +} +#[doc = "Field `TERR` reader - Transfer Error"] +pub struct TERR_R(crate::FieldReader); +impl TERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TERR` writer - Transfer Error"] +pub struct TERR_W<'a> { + w: &'a mut W, +} +impl<'a> TERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `TCMPL` reader - Transfer Complete"] +pub struct TCMPL_R(crate::FieldReader); +impl TCMPL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCMPL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCMPL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCMPL` writer - Transfer Complete"] +pub struct TCMPL_W<'a> { + w: &'a mut W, +} +impl<'a> TCMPL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `SUSP` reader - Channel Suspend"] +pub struct SUSP_R(crate::FieldReader); +impl SUSP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SUSP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SUSP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SUSP` writer - Channel Suspend"] +pub struct SUSP_W<'a> { + w: &'a mut W, +} +impl<'a> SUSP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u16 & 0x01) << 10); + self.w + } +} +#[doc = "Field `FERR` reader - Fetch Error"] +pub struct FERR_R(crate::FieldReader); +impl FERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FERR` writer - Fetch Error"] +pub struct FERR_W<'a> { + w: &'a mut W, +} +impl<'a> FERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u16 & 0x01) << 13); + self.w + } +} +#[doc = "Field `BUSY` reader - Busy"] +pub struct BUSY_R(crate::FieldReader); +impl BUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSY` writer - Busy"] +pub struct BUSY_W<'a> { + w: &'a mut W, +} +impl<'a> BUSY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u16 & 0x01) << 14); + self.w + } +} +#[doc = "Field `PEND` reader - Pending"] +pub struct PEND_R(crate::FieldReader); +impl PEND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEND` writer - Pending"] +pub struct PEND_W<'a> { + w: &'a mut W, +} +impl<'a> PEND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Channel ID"] + #[inline(always)] + pub fn id(&self) -> ID_R { + ID_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 8 - Transfer Error"] + #[inline(always)] + pub fn terr(&self) -> TERR_R { + TERR_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Transfer Complete"] + #[inline(always)] + pub fn tcmpl(&self) -> TCMPL_R { + TCMPL_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Channel Suspend"] + #[inline(always)] + pub fn susp(&self) -> SUSP_R { + SUSP_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 13 - Fetch Error"] + #[inline(always)] + pub fn ferr(&self) -> FERR_R { + FERR_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Busy"] + #[inline(always)] + pub fn busy(&self) -> BUSY_R { + BUSY_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Pending"] + #[inline(always)] + pub fn pend(&self) -> PEND_R { + PEND_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Channel ID"] + #[inline(always)] + pub fn id(&mut self) -> ID_W { + ID_W { w: self } + } + #[doc = "Bit 8 - Transfer Error"] + #[inline(always)] + pub fn terr(&mut self) -> TERR_W { + TERR_W { w: self } + } + #[doc = "Bit 9 - Transfer Complete"] + #[inline(always)] + pub fn tcmpl(&mut self) -> TCMPL_W { + TCMPL_W { w: self } + } + #[doc = "Bit 10 - Channel Suspend"] + #[inline(always)] + pub fn susp(&mut self) -> SUSP_W { + SUSP_W { w: self } + } + #[doc = "Bit 13 - Fetch Error"] + #[inline(always)] + pub fn ferr(&mut self) -> FERR_W { + FERR_W { w: self } + } + #[doc = "Bit 14 - Busy"] + #[inline(always)] + pub fn busy(&mut self) -> BUSY_W { + BUSY_W { w: self } + } + #[doc = "Bit 15 - Pending"] + #[inline(always)] + pub fn pend(&mut self) -> PEND_W { + PEND_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Pending\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intpend](index.html) module"] +pub struct INTPEND_SPEC; +impl crate::RegisterSpec for INTPEND_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intpend::R](R) reader structure"] +impl crate::Readable for INTPEND_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intpend::W](W) writer structure"] +impl crate::Writable for INTPEND_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTPEND to value 0"] +impl crate::Resettable for INTPEND_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/dmac/intstatus.rs b/pac/atsamc20j/src/dmac/intstatus.rs new file mode 100644 index 000000000000..4e6617d96bef --- /dev/null +++ b/pac/atsamc20j/src/dmac/intstatus.rs @@ -0,0 +1,153 @@ +#[doc = "Register `INTSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `CHINT0` reader - Channel 0 Pending Interrupt"] +pub struct CHINT0_R(crate::FieldReader); +impl CHINT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT1` reader - Channel 1 Pending Interrupt"] +pub struct CHINT1_R(crate::FieldReader); +impl CHINT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT2` reader - Channel 2 Pending Interrupt"] +pub struct CHINT2_R(crate::FieldReader); +impl CHINT2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT3` reader - Channel 3 Pending Interrupt"] +pub struct CHINT3_R(crate::FieldReader); +impl CHINT3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT4` reader - Channel 4 Pending Interrupt"] +pub struct CHINT4_R(crate::FieldReader); +impl CHINT4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT5` reader - Channel 5 Pending Interrupt"] +pub struct CHINT5_R(crate::FieldReader); +impl CHINT5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Channel 0 Pending Interrupt"] + #[inline(always)] + pub fn chint0(&self) -> CHINT0_R { + CHINT0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel 1 Pending Interrupt"] + #[inline(always)] + pub fn chint1(&self) -> CHINT1_R { + CHINT1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel 2 Pending Interrupt"] + #[inline(always)] + pub fn chint2(&self) -> CHINT2_R { + CHINT2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Channel 3 Pending Interrupt"] + #[inline(always)] + pub fn chint3(&self) -> CHINT3_R { + CHINT3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Channel 4 Pending Interrupt"] + #[inline(always)] + pub fn chint4(&self) -> CHINT4_R { + CHINT4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Channel 5 Pending Interrupt"] + #[inline(always)] + pub fn chint5(&self) -> CHINT5_R { + CHINT5_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +#[doc = "Interrupt Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intstatus](index.html) module"] +pub struct INTSTATUS_SPEC; +impl crate::RegisterSpec for INTSTATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intstatus::R](R) reader structure"] +impl crate::Readable for INTSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets INTSTATUS to value 0"] +impl crate::Resettable for INTSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/dmac/pendch.rs b/pac/atsamc20j/src/dmac/pendch.rs new file mode 100644 index 000000000000..1ffc2ca607b1 --- /dev/null +++ b/pac/atsamc20j/src/dmac/pendch.rs @@ -0,0 +1,153 @@ +#[doc = "Register `PENDCH` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PENDCH0` reader - Pending Channel 0"] +pub struct PENDCH0_R(crate::FieldReader); +impl PENDCH0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH1` reader - Pending Channel 1"] +pub struct PENDCH1_R(crate::FieldReader); +impl PENDCH1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH2` reader - Pending Channel 2"] +pub struct PENDCH2_R(crate::FieldReader); +impl PENDCH2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH3` reader - Pending Channel 3"] +pub struct PENDCH3_R(crate::FieldReader); +impl PENDCH3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH4` reader - Pending Channel 4"] +pub struct PENDCH4_R(crate::FieldReader); +impl PENDCH4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH5` reader - Pending Channel 5"] +pub struct PENDCH5_R(crate::FieldReader); +impl PENDCH5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Pending Channel 0"] + #[inline(always)] + pub fn pendch0(&self) -> PENDCH0_R { + PENDCH0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Pending Channel 1"] + #[inline(always)] + pub fn pendch1(&self) -> PENDCH1_R { + PENDCH1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Pending Channel 2"] + #[inline(always)] + pub fn pendch2(&self) -> PENDCH2_R { + PENDCH2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Pending Channel 3"] + #[inline(always)] + pub fn pendch3(&self) -> PENDCH3_R { + PENDCH3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Pending Channel 4"] + #[inline(always)] + pub fn pendch4(&self) -> PENDCH4_R { + PENDCH4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Pending Channel 5"] + #[inline(always)] + pub fn pendch5(&self) -> PENDCH5_R { + PENDCH5_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +#[doc = "Pending Channels\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pendch](index.html) module"] +pub struct PENDCH_SPEC; +impl crate::RegisterSpec for PENDCH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pendch::R](R) reader structure"] +impl crate::Readable for PENDCH_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PENDCH to value 0"] +impl crate::Resettable for PENDCH_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/dmac/prictrl0.rs b/pac/atsamc20j/src/dmac/prictrl0.rs new file mode 100644 index 000000000000..64324f7f2493 --- /dev/null +++ b/pac/atsamc20j/src/dmac/prictrl0.rs @@ -0,0 +1,449 @@ +#[doc = "Register `PRICTRL0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PRICTRL0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `LVLPRI0` reader - Level 0 Channel Priority Number"] +pub struct LVLPRI0_R(crate::FieldReader); +impl LVLPRI0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LVLPRI0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLPRI0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLPRI0` writer - Level 0 Channel Priority Number"] +pub struct LVLPRI0_W<'a> { + w: &'a mut W, +} +impl<'a> LVLPRI0_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Level 0 Round-Robin Scheduling Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RRLVLEN0_A { + #[doc = "0: Static arbitration scheme for channels with level 3 priority"] + STATIC_LVL = 0, + #[doc = "1: Round-robin arbitration scheme for channels with level 3 priority"] + ROUND_ROBIN_LVL = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RRLVLEN0_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RRLVLEN0` reader - Level 0 Round-Robin Scheduling Enable"] +pub struct RRLVLEN0_R(crate::FieldReader); +impl RRLVLEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RRLVLEN0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RRLVLEN0_A { + match self.bits { + false => RRLVLEN0_A::STATIC_LVL, + true => RRLVLEN0_A::ROUND_ROBIN_LVL, + } + } + #[doc = "Checks if the value of the field is `STATIC_LVL`"] + #[inline(always)] + pub fn is_static_lvl(&self) -> bool { + **self == RRLVLEN0_A::STATIC_LVL + } + #[doc = "Checks if the value of the field is `ROUND_ROBIN_LVL`"] + #[inline(always)] + pub fn is_round_robin_lvl(&self) -> bool { + **self == RRLVLEN0_A::ROUND_ROBIN_LVL + } +} +impl core::ops::Deref for RRLVLEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RRLVLEN0` writer - Level 0 Round-Robin Scheduling Enable"] +pub struct RRLVLEN0_W<'a> { + w: &'a mut W, +} +impl<'a> RRLVLEN0_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RRLVLEN0_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Static arbitration scheme for channels with level 3 priority"] + #[inline(always)] + pub fn static_lvl(self) -> &'a mut W { + self.variant(RRLVLEN0_A::STATIC_LVL) + } + #[doc = "Round-robin arbitration scheme for channels with level 3 priority"] + #[inline(always)] + pub fn round_robin_lvl(self) -> &'a mut W { + self.variant(RRLVLEN0_A::ROUND_ROBIN_LVL) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `LVLPRI1` reader - Level 1 Channel Priority Number"] +pub struct LVLPRI1_R(crate::FieldReader); +impl LVLPRI1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LVLPRI1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLPRI1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLPRI1` writer - Level 1 Channel Priority Number"] +pub struct LVLPRI1_W<'a> { + w: &'a mut W, +} +impl<'a> LVLPRI1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +#[doc = "Field `RRLVLEN1` reader - Level 1 Round-Robin Scheduling Enable"] +pub struct RRLVLEN1_R(crate::FieldReader); +impl RRLVLEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RRLVLEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RRLVLEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RRLVLEN1` writer - Level 1 Round-Robin Scheduling Enable"] +pub struct RRLVLEN1_W<'a> { + w: &'a mut W, +} +impl<'a> RRLVLEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `LVLPRI2` reader - Level 2 Channel Priority Number"] +pub struct LVLPRI2_R(crate::FieldReader); +impl LVLPRI2_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LVLPRI2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLPRI2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLPRI2` writer - Level 2 Channel Priority Number"] +pub struct LVLPRI2_W<'a> { + w: &'a mut W, +} +impl<'a> LVLPRI2_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 16)) | ((value as u32 & 0x07) << 16); + self.w + } +} +#[doc = "Field `RRLVLEN2` reader - Level 2 Round-Robin Scheduling Enable"] +pub struct RRLVLEN2_R(crate::FieldReader); +impl RRLVLEN2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RRLVLEN2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RRLVLEN2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RRLVLEN2` writer - Level 2 Round-Robin Scheduling Enable"] +pub struct RRLVLEN2_W<'a> { + w: &'a mut W, +} +impl<'a> RRLVLEN2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `LVLPRI3` reader - Level 3 Channel Priority Number"] +pub struct LVLPRI3_R(crate::FieldReader); +impl LVLPRI3_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LVLPRI3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLPRI3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLPRI3` writer - Level 3 Channel Priority Number"] +pub struct LVLPRI3_W<'a> { + w: &'a mut W, +} +impl<'a> LVLPRI3_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 24)) | ((value as u32 & 0x07) << 24); + self.w + } +} +#[doc = "Field `RRLVLEN3` reader - Level 3 Round-Robin Scheduling Enable"] +pub struct RRLVLEN3_R(crate::FieldReader); +impl RRLVLEN3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RRLVLEN3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RRLVLEN3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RRLVLEN3` writer - Level 3 Round-Robin Scheduling Enable"] +pub struct RRLVLEN3_W<'a> { + w: &'a mut W, +} +impl<'a> RRLVLEN3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Level 0 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri0(&self) -> LVLPRI0_R { + LVLPRI0_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 7 - Level 0 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen0(&self) -> RRLVLEN0_R { + RRLVLEN0_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Level 1 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri1(&self) -> LVLPRI1_R { + LVLPRI1_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 15 - Level 1 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen1(&self) -> RRLVLEN1_R { + RRLVLEN1_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:18 - Level 2 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri2(&self) -> LVLPRI2_R { + LVLPRI2_R::new(((self.bits >> 16) & 0x07) as u8) + } + #[doc = "Bit 23 - Level 2 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen2(&self) -> RRLVLEN2_R { + RRLVLEN2_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bits 24:26 - Level 3 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri3(&self) -> LVLPRI3_R { + LVLPRI3_R::new(((self.bits >> 24) & 0x07) as u8) + } + #[doc = "Bit 31 - Level 3 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen3(&self) -> RRLVLEN3_R { + RRLVLEN3_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Level 0 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri0(&mut self) -> LVLPRI0_W { + LVLPRI0_W { w: self } + } + #[doc = "Bit 7 - Level 0 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen0(&mut self) -> RRLVLEN0_W { + RRLVLEN0_W { w: self } + } + #[doc = "Bits 8:10 - Level 1 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri1(&mut self) -> LVLPRI1_W { + LVLPRI1_W { w: self } + } + #[doc = "Bit 15 - Level 1 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen1(&mut self) -> RRLVLEN1_W { + RRLVLEN1_W { w: self } + } + #[doc = "Bits 16:18 - Level 2 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri2(&mut self) -> LVLPRI2_W { + LVLPRI2_W { w: self } + } + #[doc = "Bit 23 - Level 2 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen2(&mut self) -> RRLVLEN2_W { + RRLVLEN2_W { w: self } + } + #[doc = "Bits 24:26 - Level 3 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri3(&mut self) -> LVLPRI3_W { + LVLPRI3_W { w: self } + } + #[doc = "Bit 31 - Level 3 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen3(&mut self) -> RRLVLEN3_W { + RRLVLEN3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Priority Control 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [prictrl0](index.html) module"] +pub struct PRICTRL0_SPEC; +impl crate::RegisterSpec for PRICTRL0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [prictrl0::R](R) reader structure"] +impl crate::Readable for PRICTRL0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [prictrl0::W](W) writer structure"] +impl crate::Writable for PRICTRL0_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PRICTRL0 to value 0"] +impl crate::Resettable for PRICTRL0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/dmac/qosctrl.rs b/pac/atsamc20j/src/dmac/qosctrl.rs new file mode 100644 index 000000000000..016fcaa221ef --- /dev/null +++ b/pac/atsamc20j/src/dmac/qosctrl.rs @@ -0,0 +1,402 @@ +#[doc = "Register `QOSCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `QOSCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Write-Back Quality of Service\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WRBQOS_A { + #[doc = "0: Background (no sensitive operation)"] + DISABLE = 0, + #[doc = "1: Sensitive Bandwidth"] + LOW = 1, + #[doc = "2: Sensitive Latency"] + MEDIUM = 2, + #[doc = "3: Critical Latency"] + HIGH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WRBQOS_A) -> Self { + variant as _ + } +} +#[doc = "Field `WRBQOS` reader - Write-Back Quality of Service"] +pub struct WRBQOS_R(crate::FieldReader); +impl WRBQOS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WRBQOS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> WRBQOS_A { + match self.bits { + 0 => WRBQOS_A::DISABLE, + 1 => WRBQOS_A::LOW, + 2 => WRBQOS_A::MEDIUM, + 3 => WRBQOS_A::HIGH, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == WRBQOS_A::DISABLE + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == WRBQOS_A::LOW + } + #[doc = "Checks if the value of the field is `MEDIUM`"] + #[inline(always)] + pub fn is_medium(&self) -> bool { + **self == WRBQOS_A::MEDIUM + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == WRBQOS_A::HIGH + } +} +impl core::ops::Deref for WRBQOS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WRBQOS` writer - Write-Back Quality of Service"] +pub struct WRBQOS_W<'a> { + w: &'a mut W, +} +impl<'a> WRBQOS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WRBQOS_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Background (no sensitive operation)"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(WRBQOS_A::DISABLE) + } + #[doc = "Sensitive Bandwidth"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(WRBQOS_A::LOW) + } + #[doc = "Sensitive Latency"] + #[inline(always)] + pub fn medium(self) -> &'a mut W { + self.variant(WRBQOS_A::MEDIUM) + } + #[doc = "Critical Latency"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(WRBQOS_A::HIGH) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u8 & 0x03); + self.w + } +} +#[doc = "Fetch Quality of Service\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FQOS_A { + #[doc = "0: Background (no sensitive operation)"] + DISABLE = 0, + #[doc = "1: Sensitive Bandwidth"] + LOW = 1, + #[doc = "2: Sensitive Latency"] + MEDIUM = 2, + #[doc = "3: Critical Latency"] + HIGH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FQOS_A) -> Self { + variant as _ + } +} +#[doc = "Field `FQOS` reader - Fetch Quality of Service"] +pub struct FQOS_R(crate::FieldReader); +impl FQOS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FQOS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FQOS_A { + match self.bits { + 0 => FQOS_A::DISABLE, + 1 => FQOS_A::LOW, + 2 => FQOS_A::MEDIUM, + 3 => FQOS_A::HIGH, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == FQOS_A::DISABLE + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == FQOS_A::LOW + } + #[doc = "Checks if the value of the field is `MEDIUM`"] + #[inline(always)] + pub fn is_medium(&self) -> bool { + **self == FQOS_A::MEDIUM + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == FQOS_A::HIGH + } +} +impl core::ops::Deref for FQOS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FQOS` writer - Fetch Quality of Service"] +pub struct FQOS_W<'a> { + w: &'a mut W, +} +impl<'a> FQOS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FQOS_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Background (no sensitive operation)"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(FQOS_A::DISABLE) + } + #[doc = "Sensitive Bandwidth"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(FQOS_A::LOW) + } + #[doc = "Sensitive Latency"] + #[inline(always)] + pub fn medium(self) -> &'a mut W { + self.variant(FQOS_A::MEDIUM) + } + #[doc = "Critical Latency"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(FQOS_A::HIGH) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u8 & 0x03) << 2); + self.w + } +} +#[doc = "Data Transfer Quality of Service\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DQOS_A { + #[doc = "0: Background (no sensitive operation)"] + DISABLE = 0, + #[doc = "1: Sensitive Bandwidth"] + LOW = 1, + #[doc = "2: Sensitive Latency"] + MEDIUM = 2, + #[doc = "3: Critical Latency"] + HIGH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DQOS_A) -> Self { + variant as _ + } +} +#[doc = "Field `DQOS` reader - Data Transfer Quality of Service"] +pub struct DQOS_R(crate::FieldReader); +impl DQOS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DQOS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DQOS_A { + match self.bits { + 0 => DQOS_A::DISABLE, + 1 => DQOS_A::LOW, + 2 => DQOS_A::MEDIUM, + 3 => DQOS_A::HIGH, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == DQOS_A::DISABLE + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == DQOS_A::LOW + } + #[doc = "Checks if the value of the field is `MEDIUM`"] + #[inline(always)] + pub fn is_medium(&self) -> bool { + **self == DQOS_A::MEDIUM + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == DQOS_A::HIGH + } +} +impl core::ops::Deref for DQOS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DQOS` writer - Data Transfer Quality of Service"] +pub struct DQOS_W<'a> { + w: &'a mut W, +} +impl<'a> DQOS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DQOS_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Background (no sensitive operation)"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(DQOS_A::DISABLE) + } + #[doc = "Sensitive Bandwidth"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(DQOS_A::LOW) + } + #[doc = "Sensitive Latency"] + #[inline(always)] + pub fn medium(self) -> &'a mut W { + self.variant(DQOS_A::MEDIUM) + } + #[doc = "Critical Latency"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(DQOS_A::HIGH) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u8 & 0x03) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Write-Back Quality of Service"] + #[inline(always)] + pub fn wrbqos(&self) -> WRBQOS_R { + WRBQOS_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bits 2:3 - Fetch Quality of Service"] + #[inline(always)] + pub fn fqos(&self) -> FQOS_R { + FQOS_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bits 4:5 - Data Transfer Quality of Service"] + #[inline(always)] + pub fn dqos(&self) -> DQOS_R { + DQOS_R::new(((self.bits >> 4) & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Write-Back Quality of Service"] + #[inline(always)] + pub fn wrbqos(&mut self) -> WRBQOS_W { + WRBQOS_W { w: self } + } + #[doc = "Bits 2:3 - Fetch Quality of Service"] + #[inline(always)] + pub fn fqos(&mut self) -> FQOS_W { + FQOS_W { w: self } + } + #[doc = "Bits 4:5 - Data Transfer Quality of Service"] + #[inline(always)] + pub fn dqos(&mut self) -> DQOS_W { + DQOS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "QOS Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [qosctrl](index.html) module"] +pub struct QOSCTRL_SPEC; +impl crate::RegisterSpec for QOSCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [qosctrl::R](R) reader structure"] +impl crate::Readable for QOSCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [qosctrl::W](W) writer structure"] +impl crate::Writable for QOSCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets QOSCTRL to value 0x2a"] +impl crate::Resettable for QOSCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x2a + } +} diff --git a/pac/atsamc20j/src/dmac/swtrigctrl.rs b/pac/atsamc20j/src/dmac/swtrigctrl.rs new file mode 100644 index 000000000000..ada7d633a376 --- /dev/null +++ b/pac/atsamc20j/src/dmac/swtrigctrl.rs @@ -0,0 +1,348 @@ +#[doc = "Register `SWTRIGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SWTRIGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWTRIG0` reader - Channel 0 Software Trigger"] +pub struct SWTRIG0_R(crate::FieldReader); +impl SWTRIG0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG0` writer - Channel 0 Software Trigger"] +pub struct SWTRIG0_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `SWTRIG1` reader - Channel 1 Software Trigger"] +pub struct SWTRIG1_R(crate::FieldReader); +impl SWTRIG1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG1` writer - Channel 1 Software Trigger"] +pub struct SWTRIG1_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SWTRIG2` reader - Channel 2 Software Trigger"] +pub struct SWTRIG2_R(crate::FieldReader); +impl SWTRIG2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG2` writer - Channel 2 Software Trigger"] +pub struct SWTRIG2_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SWTRIG3` reader - Channel 3 Software Trigger"] +pub struct SWTRIG3_R(crate::FieldReader); +impl SWTRIG3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG3` writer - Channel 3 Software Trigger"] +pub struct SWTRIG3_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `SWTRIG4` reader - Channel 4 Software Trigger"] +pub struct SWTRIG4_R(crate::FieldReader); +impl SWTRIG4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG4` writer - Channel 4 Software Trigger"] +pub struct SWTRIG4_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `SWTRIG5` reader - Channel 5 Software Trigger"] +pub struct SWTRIG5_R(crate::FieldReader); +impl SWTRIG5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG5` writer - Channel 5 Software Trigger"] +pub struct SWTRIG5_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Channel 0 Software Trigger"] + #[inline(always)] + pub fn swtrig0(&self) -> SWTRIG0_R { + SWTRIG0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel 1 Software Trigger"] + #[inline(always)] + pub fn swtrig1(&self) -> SWTRIG1_R { + SWTRIG1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel 2 Software Trigger"] + #[inline(always)] + pub fn swtrig2(&self) -> SWTRIG2_R { + SWTRIG2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Channel 3 Software Trigger"] + #[inline(always)] + pub fn swtrig3(&self) -> SWTRIG3_R { + SWTRIG3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Channel 4 Software Trigger"] + #[inline(always)] + pub fn swtrig4(&self) -> SWTRIG4_R { + SWTRIG4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Channel 5 Software Trigger"] + #[inline(always)] + pub fn swtrig5(&self) -> SWTRIG5_R { + SWTRIG5_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel 0 Software Trigger"] + #[inline(always)] + pub fn swtrig0(&mut self) -> SWTRIG0_W { + SWTRIG0_W { w: self } + } + #[doc = "Bit 1 - Channel 1 Software Trigger"] + #[inline(always)] + pub fn swtrig1(&mut self) -> SWTRIG1_W { + SWTRIG1_W { w: self } + } + #[doc = "Bit 2 - Channel 2 Software Trigger"] + #[inline(always)] + pub fn swtrig2(&mut self) -> SWTRIG2_W { + SWTRIG2_W { w: self } + } + #[doc = "Bit 3 - Channel 3 Software Trigger"] + #[inline(always)] + pub fn swtrig3(&mut self) -> SWTRIG3_W { + SWTRIG3_W { w: self } + } + #[doc = "Bit 4 - Channel 4 Software Trigger"] + #[inline(always)] + pub fn swtrig4(&mut self) -> SWTRIG4_W { + SWTRIG4_W { w: self } + } + #[doc = "Bit 5 - Channel 5 Software Trigger"] + #[inline(always)] + pub fn swtrig5(&mut self) -> SWTRIG5_W { + SWTRIG5_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Software Trigger Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [swtrigctrl](index.html) module"] +pub struct SWTRIGCTRL_SPEC; +impl crate::RegisterSpec for SWTRIGCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [swtrigctrl::R](R) reader structure"] +impl crate::Readable for SWTRIGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [swtrigctrl::W](W) writer structure"] +impl crate::Writable for SWTRIGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SWTRIGCTRL to value 0"] +impl crate::Resettable for SWTRIGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/dmac/wrbaddr.rs b/pac/atsamc20j/src/dmac/wrbaddr.rs new file mode 100644 index 000000000000..ccf2a376b853 --- /dev/null +++ b/pac/atsamc20j/src/dmac/wrbaddr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `WRBADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WRBADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WRBADDR` reader - Write-Back Memory Base Address"] +pub struct WRBADDR_R(crate::FieldReader); +impl WRBADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + WRBADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WRBADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WRBADDR` writer - Write-Back Memory Base Address"] +pub struct WRBADDR_W<'a> { + w: &'a mut W, +} +impl<'a> WRBADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Write-Back Memory Base Address"] + #[inline(always)] + pub fn wrbaddr(&self) -> WRBADDR_R { + WRBADDR_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Write-Back Memory Base Address"] + #[inline(always)] + pub fn wrbaddr(&mut self) -> WRBADDR_W { + WRBADDR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Write-Back Memory Section Base Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wrbaddr](index.html) module"] +pub struct WRBADDR_SPEC; +impl crate::RegisterSpec for WRBADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [wrbaddr::R](R) reader structure"] +impl crate::Readable for WRBADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wrbaddr::W](W) writer structure"] +impl crate::Writable for WRBADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WRBADDR to value 0"] +impl crate::Resettable for WRBADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/dsu.rs b/pac/atsamc20j/src/dsu.rs new file mode 100644 index 000000000000..88324f764961 --- /dev/null +++ b/pac/atsamc20j/src/dsu.rs @@ -0,0 +1,163 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrl: crate::Reg, + #[doc = "0x01 - Status A"] + pub statusa: crate::Reg, + #[doc = "0x02 - Status B"] + pub statusb: crate::Reg, + #[doc = "0x03 - Status C"] + pub statusc: crate::Reg, + #[doc = "0x04 - Address"] + pub addr: crate::Reg, + #[doc = "0x08 - Length"] + pub length: crate::Reg, + #[doc = "0x0c - Data"] + pub data: crate::Reg, + #[doc = "0x10..0x18 - Debug Communication Channel n"] + pub dcc: [crate::Reg; 2], + #[doc = "0x18 - Device Identification"] + pub did: crate::Reg, + _reserved9: [u8; 0xd4], + #[doc = "0xf0..0xf8 - Device Configuration"] + pub dcfg: [crate::Reg; 2], + _reserved10: [u8; 0x0f08], + #[doc = "0x1000 - CoreSight ROM Table Entry 0"] + pub entry0: crate::Reg, + #[doc = "0x1004 - CoreSight ROM Table Entry 1"] + pub entry1: crate::Reg, + #[doc = "0x1008 - CoreSight ROM Table End"] + pub end: crate::Reg, + _reserved13: [u8; 0x0fc0], + #[doc = "0x1fcc - CoreSight ROM Table Memory Type"] + pub memtype: crate::Reg, + #[doc = "0x1fd0 - Peripheral Identification 4"] + pub pid4: crate::Reg, + #[doc = "0x1fd4 - Peripheral Identification 5"] + pub pid5: crate::Reg, + #[doc = "0x1fd8 - Peripheral Identification 6"] + pub pid6: crate::Reg, + #[doc = "0x1fdc - Peripheral Identification 7"] + pub pid7: crate::Reg, + #[doc = "0x1fe0 - Peripheral Identification 0"] + pub pid0: crate::Reg, + #[doc = "0x1fe4 - Peripheral Identification 1"] + pub pid1: crate::Reg, + #[doc = "0x1fe8 - Peripheral Identification 2"] + pub pid2: crate::Reg, + #[doc = "0x1fec - Peripheral Identification 3"] + pub pid3: crate::Reg, + #[doc = "0x1ff0 - Component Identification 0"] + pub cid0: crate::Reg, + #[doc = "0x1ff4 - Component Identification 1"] + pub cid1: crate::Reg, + #[doc = "0x1ff8 - Component Identification 2"] + pub cid2: crate::Reg, + #[doc = "0x1ffc - Component Identification 3"] + pub cid3: crate::Reg, +} +#[doc = "CTRL register accessor: an alias for `Reg`"] +pub type CTRL = crate::Reg; +#[doc = "Control"] +pub mod ctrl; +#[doc = "STATUSA register accessor: an alias for `Reg`"] +pub type STATUSA = crate::Reg; +#[doc = "Status A"] +pub mod statusa; +#[doc = "STATUSB register accessor: an alias for `Reg`"] +pub type STATUSB = crate::Reg; +#[doc = "Status B"] +pub mod statusb; +#[doc = "STATUSC register accessor: an alias for `Reg`"] +pub type STATUSC = crate::Reg; +#[doc = "Status C"] +pub mod statusc; +#[doc = "ADDR register accessor: an alias for `Reg`"] +pub type ADDR = crate::Reg; +#[doc = "Address"] +pub mod addr; +#[doc = "LENGTH register accessor: an alias for `Reg`"] +pub type LENGTH = crate::Reg; +#[doc = "Length"] +pub mod length; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "Data"] +pub mod data; +#[doc = "DCC register accessor: an alias for `Reg`"] +pub type DCC = crate::Reg; +#[doc = "Debug Communication Channel n"] +pub mod dcc; +#[doc = "DID register accessor: an alias for `Reg`"] +pub type DID = crate::Reg; +#[doc = "Device Identification"] +pub mod did; +#[doc = "DCFG register accessor: an alias for `Reg`"] +pub type DCFG = crate::Reg; +#[doc = "Device Configuration"] +pub mod dcfg; +#[doc = "ENTRY0 register accessor: an alias for `Reg`"] +pub type ENTRY0 = crate::Reg; +#[doc = "CoreSight ROM Table Entry 0"] +pub mod entry0; +#[doc = "ENTRY1 register accessor: an alias for `Reg`"] +pub type ENTRY1 = crate::Reg; +#[doc = "CoreSight ROM Table Entry 1"] +pub mod entry1; +#[doc = "END register accessor: an alias for `Reg`"] +pub type END = crate::Reg; +#[doc = "CoreSight ROM Table End"] +pub mod end; +#[doc = "MEMTYPE register accessor: an alias for `Reg`"] +pub type MEMTYPE = crate::Reg; +#[doc = "CoreSight ROM Table Memory Type"] +pub mod memtype; +#[doc = "PID4 register accessor: an alias for `Reg`"] +pub type PID4 = crate::Reg; +#[doc = "Peripheral Identification 4"] +pub mod pid4; +#[doc = "PID5 register accessor: an alias for `Reg`"] +pub type PID5 = crate::Reg; +#[doc = "Peripheral Identification 5"] +pub mod pid5; +#[doc = "PID6 register accessor: an alias for `Reg`"] +pub type PID6 = crate::Reg; +#[doc = "Peripheral Identification 6"] +pub mod pid6; +#[doc = "PID7 register accessor: an alias for `Reg`"] +pub type PID7 = crate::Reg; +#[doc = "Peripheral Identification 7"] +pub mod pid7; +#[doc = "PID0 register accessor: an alias for `Reg`"] +pub type PID0 = crate::Reg; +#[doc = "Peripheral Identification 0"] +pub mod pid0; +#[doc = "PID1 register accessor: an alias for `Reg`"] +pub type PID1 = crate::Reg; +#[doc = "Peripheral Identification 1"] +pub mod pid1; +#[doc = "PID2 register accessor: an alias for `Reg`"] +pub type PID2 = crate::Reg; +#[doc = "Peripheral Identification 2"] +pub mod pid2; +#[doc = "PID3 register accessor: an alias for `Reg`"] +pub type PID3 = crate::Reg; +#[doc = "Peripheral Identification 3"] +pub mod pid3; +#[doc = "CID0 register accessor: an alias for `Reg`"] +pub type CID0 = crate::Reg; +#[doc = "Component Identification 0"] +pub mod cid0; +#[doc = "CID1 register accessor: an alias for `Reg`"] +pub type CID1 = crate::Reg; +#[doc = "Component Identification 1"] +pub mod cid1; +#[doc = "CID2 register accessor: an alias for `Reg`"] +pub type CID2 = crate::Reg; +#[doc = "Component Identification 2"] +pub mod cid2; +#[doc = "CID3 register accessor: an alias for `Reg`"] +pub type CID3 = crate::Reg; +#[doc = "Component Identification 3"] +pub mod cid3; diff --git a/pac/atsamc20j/src/dsu/addr.rs b/pac/atsamc20j/src/dsu/addr.rs new file mode 100644 index 000000000000..412f874d6b15 --- /dev/null +++ b/pac/atsamc20j/src/dsu/addr.rs @@ -0,0 +1,140 @@ +#[doc = "Register `ADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `AMOD` reader - Access Mode"] +pub struct AMOD_R(crate::FieldReader); +impl AMOD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + AMOD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AMOD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AMOD` writer - Access Mode"] +pub struct AMOD_W<'a> { + w: &'a mut W, +} +impl<'a> AMOD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u32 & 0x03); + self.w + } +} +#[doc = "Field `ADDR` reader - Address"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - Address"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3fff_ffff << 2)) | ((value as u32 & 0x3fff_ffff) << 2); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Access Mode"] + #[inline(always)] + pub fn amod(&self) -> AMOD_R { + AMOD_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bits 2:31 - Address"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new(((self.bits >> 2) & 0x3fff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:1 - Access Mode"] + #[inline(always)] + pub fn amod(&mut self) -> AMOD_W { + AMOD_W { w: self } + } + #[doc = "Bits 2:31 - Address"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [addr](index.html) module"] +pub struct ADDR_SPEC; +impl crate::RegisterSpec for ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [addr::R](R) reader structure"] +impl crate::Readable for ADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [addr::W](W) writer structure"] +impl crate::Writable for ADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ADDR to value 0"] +impl crate::Resettable for ADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/dsu/cid0.rs b/pac/atsamc20j/src/dsu/cid0.rs new file mode 100644 index 000000000000..b3c2373dfc99 --- /dev/null +++ b/pac/atsamc20j/src/dsu/cid0.rs @@ -0,0 +1,53 @@ +#[doc = "Register `CID0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PREAMBLEB0` reader - Preamble Byte 0"] +pub struct PREAMBLEB0_R(crate::FieldReader); +impl PREAMBLEB0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PREAMBLEB0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PREAMBLEB0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:7 - Preamble Byte 0"] + #[inline(always)] + pub fn preambleb0(&self) -> PREAMBLEB0_R { + PREAMBLEB0_R::new((self.bits & 0xff) as u8) + } +} +#[doc = "Component Identification 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid0](index.html) module"] +pub struct CID0_SPEC; +impl crate::RegisterSpec for CID0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid0::R](R) reader structure"] +impl crate::Readable for CID0_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID0 to value 0x0d"] +impl crate::Resettable for CID0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0d + } +} diff --git a/pac/atsamc20j/src/dsu/cid1.rs b/pac/atsamc20j/src/dsu/cid1.rs new file mode 100644 index 000000000000..3628ceac64a7 --- /dev/null +++ b/pac/atsamc20j/src/dsu/cid1.rs @@ -0,0 +1,73 @@ +#[doc = "Register `CID1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PREAMBLE` reader - Preamble"] +pub struct PREAMBLE_R(crate::FieldReader); +impl PREAMBLE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PREAMBLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PREAMBLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCLASS` reader - Component Class"] +pub struct CCLASS_R(crate::FieldReader); +impl CCLASS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CCLASS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCLASS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:3 - Preamble"] + #[inline(always)] + pub fn preamble(&self) -> PREAMBLE_R { + PREAMBLE_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Component Class"] + #[inline(always)] + pub fn cclass(&self) -> CCLASS_R { + CCLASS_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +#[doc = "Component Identification 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid1](index.html) module"] +pub struct CID1_SPEC; +impl crate::RegisterSpec for CID1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid1::R](R) reader structure"] +impl crate::Readable for CID1_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID1 to value 0x10"] +impl crate::Resettable for CID1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x10 + } +} diff --git a/pac/atsamc20j/src/dsu/cid2.rs b/pac/atsamc20j/src/dsu/cid2.rs new file mode 100644 index 000000000000..714078d5c430 --- /dev/null +++ b/pac/atsamc20j/src/dsu/cid2.rs @@ -0,0 +1,53 @@ +#[doc = "Register `CID2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PREAMBLEB2` reader - Preamble Byte 2"] +pub struct PREAMBLEB2_R(crate::FieldReader); +impl PREAMBLEB2_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PREAMBLEB2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PREAMBLEB2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:7 - Preamble Byte 2"] + #[inline(always)] + pub fn preambleb2(&self) -> PREAMBLEB2_R { + PREAMBLEB2_R::new((self.bits & 0xff) as u8) + } +} +#[doc = "Component Identification 2\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid2](index.html) module"] +pub struct CID2_SPEC; +impl crate::RegisterSpec for CID2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid2::R](R) reader structure"] +impl crate::Readable for CID2_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID2 to value 0x05"] +impl crate::Resettable for CID2_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x05 + } +} diff --git a/pac/atsamc20j/src/dsu/cid3.rs b/pac/atsamc20j/src/dsu/cid3.rs new file mode 100644 index 000000000000..a345af7b5166 --- /dev/null +++ b/pac/atsamc20j/src/dsu/cid3.rs @@ -0,0 +1,53 @@ +#[doc = "Register `CID3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PREAMBLEB3` reader - Preamble Byte 3"] +pub struct PREAMBLEB3_R(crate::FieldReader); +impl PREAMBLEB3_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PREAMBLEB3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PREAMBLEB3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:7 - Preamble Byte 3"] + #[inline(always)] + pub fn preambleb3(&self) -> PREAMBLEB3_R { + PREAMBLEB3_R::new((self.bits & 0xff) as u8) + } +} +#[doc = "Component Identification 3\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid3](index.html) module"] +pub struct CID3_SPEC; +impl crate::RegisterSpec for CID3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid3::R](R) reader structure"] +impl crate::Readable for CID3_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID3 to value 0xb1"] +impl crate::Resettable for CID3_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xb1 + } +} diff --git a/pac/atsamc20j/src/dsu/ctrl.rs b/pac/atsamc20j/src/dsu/ctrl.rs new file mode 100644 index 000000000000..0a19db5a5239 --- /dev/null +++ b/pac/atsamc20j/src/dsu/ctrl.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `CRC` writer - 32-bit Cyclic Redundancy Code"] +pub struct CRC_W<'a> { + w: &'a mut W, +} +impl<'a> CRC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `MBIST` writer - Memory built-in self-test"] +pub struct MBIST_W<'a> { + w: &'a mut W, +} +impl<'a> MBIST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CE` writer - Chip-Erase"] +pub struct CE_W<'a> { + w: &'a mut W, +} +impl<'a> CE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `ARR` writer - Auxiliary Row Read"] +pub struct ARR_W<'a> { + w: &'a mut W, +} +impl<'a> ARR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +#[doc = "Field `SMSA` writer - Start Memory Stream Access"] +pub struct SMSA_W<'a> { + w: &'a mut W, +} +impl<'a> SMSA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 2 - 32-bit Cyclic Redundancy Code"] + #[inline(always)] + pub fn crc(&mut self) -> CRC_W { + CRC_W { w: self } + } + #[doc = "Bit 3 - Memory built-in self-test"] + #[inline(always)] + pub fn mbist(&mut self) -> MBIST_W { + MBIST_W { w: self } + } + #[doc = "Bit 4 - Chip-Erase"] + #[inline(always)] + pub fn ce(&mut self) -> CE_W { + CE_W { w: self } + } + #[doc = "Bit 6 - Auxiliary Row Read"] + #[inline(always)] + pub fn arr(&mut self) -> ARR_W { + ARR_W { w: self } + } + #[doc = "Bit 7 - Start Memory Stream Access"] + #[inline(always)] + pub fn smsa(&mut self) -> SMSA_W { + SMSA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"] +pub struct CTRL_SPEC; +impl crate::RegisterSpec for CTRL_SPEC { + type Ux = u8; +} +#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"] +impl crate::Writable for CTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/dsu/data.rs b/pac/atsamc20j/src/dsu/data.rs new file mode 100644 index 000000000000..193cc49a07fd --- /dev/null +++ b/pac/atsamc20j/src/dsu/data.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Data"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Data"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/dsu/dcc.rs b/pac/atsamc20j/src/dsu/dcc.rs new file mode 100644 index 000000000000..354323a499ef --- /dev/null +++ b/pac/atsamc20j/src/dsu/dcc.rs @@ -0,0 +1,104 @@ +#[doc = "Register `DCC[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DCC[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Data"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Data"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Communication Channel n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dcc](index.html) module"] +pub struct DCC_SPEC; +impl crate::RegisterSpec for DCC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dcc::R](R) reader structure"] +impl crate::Readable for DCC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dcc::W](W) writer structure"] +impl crate::Writable for DCC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DCC[%s] +to value 0"] +impl crate::Resettable for DCC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/dsu/dcfg.rs b/pac/atsamc20j/src/dsu/dcfg.rs new file mode 100644 index 000000000000..c6d61d0b496e --- /dev/null +++ b/pac/atsamc20j/src/dsu/dcfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `DCFG[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DCFG[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DCFG` reader - Device Configuration"] +pub struct DCFG_R(crate::FieldReader); +impl DCFG_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + DCFG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DCFG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DCFG` writer - Device Configuration"] +pub struct DCFG_W<'a> { + w: &'a mut W, +} +impl<'a> DCFG_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Device Configuration"] + #[inline(always)] + pub fn dcfg(&self) -> DCFG_R { + DCFG_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Device Configuration"] + #[inline(always)] + pub fn dcfg(&mut self) -> DCFG_W { + DCFG_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Device Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dcfg](index.html) module"] +pub struct DCFG_SPEC; +impl crate::RegisterSpec for DCFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dcfg::R](R) reader structure"] +impl crate::Readable for DCFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dcfg::W](W) writer structure"] +impl crate::Writable for DCFG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DCFG[%s] +to value 0"] +impl crate::Resettable for DCFG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/dsu/did.rs b/pac/atsamc20j/src/dsu/did.rs new file mode 100644 index 000000000000..e7c8e70c505d --- /dev/null +++ b/pac/atsamc20j/src/dsu/did.rs @@ -0,0 +1,279 @@ +#[doc = "Register `DID` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `DEVSEL` reader - Device Select"] +pub struct DEVSEL_R(crate::FieldReader); +impl DEVSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DEVSEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DEVSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REVISION` reader - Revision Number"] +pub struct REVISION_R(crate::FieldReader); +impl REVISION_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REVISION_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REVISION_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIE` reader - Die Number"] +pub struct DIE_R(crate::FieldReader); +impl DIE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DIE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Series\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SERIES_A { + #[doc = "0: Cortex-M0+ processor, basic feature set"] + _0 = 0, + #[doc = "1: Cortex-M0+ processor, CAN"] + _1 = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SERIES_A) -> Self { + variant as _ + } +} +#[doc = "Field `SERIES` reader - Series"] +pub struct SERIES_R(crate::FieldReader); +impl SERIES_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SERIES_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SERIES_A::_0), + 1 => Some(SERIES_A::_1), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_0`"] + #[inline(always)] + pub fn is_0(&self) -> bool { + **self == SERIES_A::_0 + } + #[doc = "Checks if the value of the field is `_1`"] + #[inline(always)] + pub fn is_1(&self) -> bool { + **self == SERIES_A::_1 + } +} +impl core::ops::Deref for SERIES_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Family\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FAMILY_A { + #[doc = "0: General purpose microcontroller"] + _0 = 0, + #[doc = "1: PicoPower"] + _1 = 1, + #[doc = "2: 5V Industrial"] + _2 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FAMILY_A) -> Self { + variant as _ + } +} +#[doc = "Field `FAMILY` reader - Family"] +pub struct FAMILY_R(crate::FieldReader); +impl FAMILY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FAMILY_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(FAMILY_A::_0), + 1 => Some(FAMILY_A::_1), + 2 => Some(FAMILY_A::_2), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_0`"] + #[inline(always)] + pub fn is_0(&self) -> bool { + **self == FAMILY_A::_0 + } + #[doc = "Checks if the value of the field is `_1`"] + #[inline(always)] + pub fn is_1(&self) -> bool { + **self == FAMILY_A::_1 + } + #[doc = "Checks if the value of the field is `_2`"] + #[inline(always)] + pub fn is_2(&self) -> bool { + **self == FAMILY_A::_2 + } +} +impl core::ops::Deref for FAMILY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Processor\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PROCESSOR_A { + #[doc = "0: Cortex-M0"] + _0 = 0, + #[doc = "1: Cortex-M0+"] + _1 = 1, + #[doc = "2: Cortex-M3"] + _2 = 2, + #[doc = "3: Cortex-M4"] + _3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PROCESSOR_A) -> Self { + variant as _ + } +} +#[doc = "Field `PROCESSOR` reader - Processor"] +pub struct PROCESSOR_R(crate::FieldReader); +impl PROCESSOR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PROCESSOR_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PROCESSOR_A::_0), + 1 => Some(PROCESSOR_A::_1), + 2 => Some(PROCESSOR_A::_2), + 3 => Some(PROCESSOR_A::_3), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_0`"] + #[inline(always)] + pub fn is_0(&self) -> bool { + **self == PROCESSOR_A::_0 + } + #[doc = "Checks if the value of the field is `_1`"] + #[inline(always)] + pub fn is_1(&self) -> bool { + **self == PROCESSOR_A::_1 + } + #[doc = "Checks if the value of the field is `_2`"] + #[inline(always)] + pub fn is_2(&self) -> bool { + **self == PROCESSOR_A::_2 + } + #[doc = "Checks if the value of the field is `_3`"] + #[inline(always)] + pub fn is_3(&self) -> bool { + **self == PROCESSOR_A::_3 + } +} +impl core::ops::Deref for PROCESSOR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:7 - Device Select"] + #[inline(always)] + pub fn devsel(&self) -> DEVSEL_R { + DEVSEL_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:11 - Revision Number"] + #[inline(always)] + pub fn revision(&self) -> REVISION_R { + REVISION_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - Die Number"] + #[inline(always)] + pub fn die(&self) -> DIE_R { + DIE_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:21 - Series"] + #[inline(always)] + pub fn series(&self) -> SERIES_R { + SERIES_R::new(((self.bits >> 16) & 0x3f) as u8) + } + #[doc = "Bits 23:27 - Family"] + #[inline(always)] + pub fn family(&self) -> FAMILY_R { + FAMILY_R::new(((self.bits >> 23) & 0x1f) as u8) + } + #[doc = "Bits 28:31 - Processor"] + #[inline(always)] + pub fn processor(&self) -> PROCESSOR_R { + PROCESSOR_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +#[doc = "Device Identification\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [did](index.html) module"] +pub struct DID_SPEC; +impl crate::RegisterSpec for DID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [did::R](R) reader structure"] +impl crate::Readable for DID_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DID to value 0x1100_1420"] +impl crate::Resettable for DID_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x1100_1420 + } +} diff --git a/pac/atsamc20j/src/dsu/end.rs b/pac/atsamc20j/src/dsu/end.rs new file mode 100644 index 000000000000..cce2edea2bce --- /dev/null +++ b/pac/atsamc20j/src/dsu/end.rs @@ -0,0 +1,53 @@ +#[doc = "Register `END` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `END` reader - End Marker"] +pub struct END_R(crate::FieldReader); +impl END_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + END_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for END_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - End Marker"] + #[inline(always)] + pub fn end(&self) -> END_R { + END_R::new(self.bits as u32) + } +} +#[doc = "CoreSight ROM Table End\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [end](index.html) module"] +pub struct END_SPEC; +impl crate::RegisterSpec for END_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [end::R](R) reader structure"] +impl crate::Readable for END_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets END to value 0"] +impl crate::Resettable for END_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/dsu/entry0.rs b/pac/atsamc20j/src/dsu/entry0.rs new file mode 100644 index 000000000000..d8563990e827 --- /dev/null +++ b/pac/atsamc20j/src/dsu/entry0.rs @@ -0,0 +1,93 @@ +#[doc = "Register `ENTRY0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `EPRES` reader - Entry Present"] +pub struct EPRES_R(crate::FieldReader); +impl EPRES_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EPRES_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EPRES_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FMT` reader - Format"] +pub struct FMT_R(crate::FieldReader); +impl FMT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FMT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FMT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDOFF` reader - Address Offset"] +pub struct ADDOFF_R(crate::FieldReader); +impl ADDOFF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + ADDOFF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDOFF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Entry Present"] + #[inline(always)] + pub fn epres(&self) -> EPRES_R { + EPRES_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Format"] + #[inline(always)] + pub fn fmt(&self) -> FMT_R { + FMT_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 12:31 - Address Offset"] + #[inline(always)] + pub fn addoff(&self) -> ADDOFF_R { + ADDOFF_R::new(((self.bits >> 12) & 0x000f_ffff) as u32) + } +} +#[doc = "CoreSight ROM Table Entry 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [entry0](index.html) module"] +pub struct ENTRY0_SPEC; +impl crate::RegisterSpec for ENTRY0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [entry0::R](R) reader structure"] +impl crate::Readable for ENTRY0_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets ENTRY0 to value 0x9f0f_c002"] +impl crate::Resettable for ENTRY0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x9f0f_c002 + } +} diff --git a/pac/atsamc20j/src/dsu/entry1.rs b/pac/atsamc20j/src/dsu/entry1.rs new file mode 100644 index 000000000000..cec8fa367705 --- /dev/null +++ b/pac/atsamc20j/src/dsu/entry1.rs @@ -0,0 +1,31 @@ +#[doc = "Register `ENTRY1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "CoreSight ROM Table Entry 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [entry1](index.html) module"] +pub struct ENTRY1_SPEC; +impl crate::RegisterSpec for ENTRY1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [entry1::R](R) reader structure"] +impl crate::Readable for ENTRY1_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets ENTRY1 to value 0x5002"] +impl crate::Resettable for ENTRY1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x5002 + } +} diff --git a/pac/atsamc20j/src/dsu/length.rs b/pac/atsamc20j/src/dsu/length.rs new file mode 100644 index 000000000000..2dc771f74dfd --- /dev/null +++ b/pac/atsamc20j/src/dsu/length.rs @@ -0,0 +1,103 @@ +#[doc = "Register `LENGTH` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `LENGTH` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `LENGTH` reader - Length"] +pub struct LENGTH_R(crate::FieldReader); +impl LENGTH_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + LENGTH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LENGTH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LENGTH` writer - Length"] +pub struct LENGTH_W<'a> { + w: &'a mut W, +} +impl<'a> LENGTH_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3fff_ffff << 2)) | ((value as u32 & 0x3fff_ffff) << 2); + self.w + } +} +impl R { + #[doc = "Bits 2:31 - Length"] + #[inline(always)] + pub fn length(&self) -> LENGTH_R { + LENGTH_R::new(((self.bits >> 2) & 0x3fff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 2:31 - Length"] + #[inline(always)] + pub fn length(&mut self) -> LENGTH_W { + LENGTH_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Length\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [length](index.html) module"] +pub struct LENGTH_SPEC; +impl crate::RegisterSpec for LENGTH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [length::R](R) reader structure"] +impl crate::Readable for LENGTH_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [length::W](W) writer structure"] +impl crate::Writable for LENGTH_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets LENGTH to value 0"] +impl crate::Resettable for LENGTH_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/dsu/memtype.rs b/pac/atsamc20j/src/dsu/memtype.rs new file mode 100644 index 000000000000..3cc841e2ba78 --- /dev/null +++ b/pac/atsamc20j/src/dsu/memtype.rs @@ -0,0 +1,53 @@ +#[doc = "Register `MEMTYPE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SMEMP` reader - System Memory Present"] +pub struct SMEMP_R(crate::FieldReader); +impl SMEMP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SMEMP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SMEMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - System Memory Present"] + #[inline(always)] + pub fn smemp(&self) -> SMEMP_R { + SMEMP_R::new((self.bits & 0x01) != 0) + } +} +#[doc = "CoreSight ROM Table Memory Type\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [memtype](index.html) module"] +pub struct MEMTYPE_SPEC; +impl crate::RegisterSpec for MEMTYPE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [memtype::R](R) reader structure"] +impl crate::Readable for MEMTYPE_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets MEMTYPE to value 0"] +impl crate::Resettable for MEMTYPE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/dsu/pid0.rs b/pac/atsamc20j/src/dsu/pid0.rs new file mode 100644 index 000000000000..98028ea62838 --- /dev/null +++ b/pac/atsamc20j/src/dsu/pid0.rs @@ -0,0 +1,53 @@ +#[doc = "Register `PID0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PARTNBL` reader - Part Number Low"] +pub struct PARTNBL_R(crate::FieldReader); +impl PARTNBL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PARTNBL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PARTNBL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:7 - Part Number Low"] + #[inline(always)] + pub fn partnbl(&self) -> PARTNBL_R { + PARTNBL_R::new((self.bits & 0xff) as u8) + } +} +#[doc = "Peripheral Identification 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid0](index.html) module"] +pub struct PID0_SPEC; +impl crate::RegisterSpec for PID0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid0::R](R) reader structure"] +impl crate::Readable for PID0_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID0 to value 0xd0"] +impl crate::Resettable for PID0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xd0 + } +} diff --git a/pac/atsamc20j/src/dsu/pid1.rs b/pac/atsamc20j/src/dsu/pid1.rs new file mode 100644 index 000000000000..4f94b853507c --- /dev/null +++ b/pac/atsamc20j/src/dsu/pid1.rs @@ -0,0 +1,73 @@ +#[doc = "Register `PID1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PARTNBH` reader - Part Number High"] +pub struct PARTNBH_R(crate::FieldReader); +impl PARTNBH_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PARTNBH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PARTNBH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `JEPIDCL` reader - Low part of the JEP-106 Identity Code"] +pub struct JEPIDCL_R(crate::FieldReader); +impl JEPIDCL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + JEPIDCL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for JEPIDCL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:3 - Part Number High"] + #[inline(always)] + pub fn partnbh(&self) -> PARTNBH_R { + PARTNBH_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Low part of the JEP-106 Identity Code"] + #[inline(always)] + pub fn jepidcl(&self) -> JEPIDCL_R { + JEPIDCL_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +#[doc = "Peripheral Identification 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid1](index.html) module"] +pub struct PID1_SPEC; +impl crate::RegisterSpec for PID1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid1::R](R) reader structure"] +impl crate::Readable for PID1_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID1 to value 0xfc"] +impl crate::Resettable for PID1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xfc + } +} diff --git a/pac/atsamc20j/src/dsu/pid2.rs b/pac/atsamc20j/src/dsu/pid2.rs new file mode 100644 index 000000000000..d8f8ed10192e --- /dev/null +++ b/pac/atsamc20j/src/dsu/pid2.rs @@ -0,0 +1,93 @@ +#[doc = "Register `PID2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `JEPIDCH` reader - JEP-106 Identity Code High"] +pub struct JEPIDCH_R(crate::FieldReader); +impl JEPIDCH_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + JEPIDCH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for JEPIDCH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `JEPU` reader - JEP-106 Identity Code is used"] +pub struct JEPU_R(crate::FieldReader); +impl JEPU_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + JEPU_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for JEPU_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REVISION` reader - Revision Number"] +pub struct REVISION_R(crate::FieldReader); +impl REVISION_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REVISION_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REVISION_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:2 - JEP-106 Identity Code High"] + #[inline(always)] + pub fn jepidch(&self) -> JEPIDCH_R { + JEPIDCH_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 3 - JEP-106 Identity Code is used"] + #[inline(always)] + pub fn jepu(&self) -> JEPU_R { + JEPU_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bits 4:7 - Revision Number"] + #[inline(always)] + pub fn revision(&self) -> REVISION_R { + REVISION_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +#[doc = "Peripheral Identification 2\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid2](index.html) module"] +pub struct PID2_SPEC; +impl crate::RegisterSpec for PID2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid2::R](R) reader structure"] +impl crate::Readable for PID2_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID2 to value 0x09"] +impl crate::Resettable for PID2_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x09 + } +} diff --git a/pac/atsamc20j/src/dsu/pid3.rs b/pac/atsamc20j/src/dsu/pid3.rs new file mode 100644 index 000000000000..c0a8fb2d7f92 --- /dev/null +++ b/pac/atsamc20j/src/dsu/pid3.rs @@ -0,0 +1,73 @@ +#[doc = "Register `PID3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `CUSMOD` reader - ARM CUSMOD"] +pub struct CUSMOD_R(crate::FieldReader); +impl CUSMOD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CUSMOD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CUSMOD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REVAND` reader - Revision Number"] +pub struct REVAND_R(crate::FieldReader); +impl REVAND_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REVAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REVAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:3 - ARM CUSMOD"] + #[inline(always)] + pub fn cusmod(&self) -> CUSMOD_R { + CUSMOD_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Revision Number"] + #[inline(always)] + pub fn revand(&self) -> REVAND_R { + REVAND_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +#[doc = "Peripheral Identification 3\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid3](index.html) module"] +pub struct PID3_SPEC; +impl crate::RegisterSpec for PID3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid3::R](R) reader structure"] +impl crate::Readable for PID3_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID3 to value 0"] +impl crate::Resettable for PID3_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/dsu/pid4.rs b/pac/atsamc20j/src/dsu/pid4.rs new file mode 100644 index 000000000000..d3a1bd120f0b --- /dev/null +++ b/pac/atsamc20j/src/dsu/pid4.rs @@ -0,0 +1,73 @@ +#[doc = "Register `PID4` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `JEPCC` reader - JEP-106 Continuation Code"] +pub struct JEPCC_R(crate::FieldReader); +impl JEPCC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + JEPCC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for JEPCC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FKBC` reader - 4KB count"] +pub struct FKBC_R(crate::FieldReader); +impl FKBC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FKBC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FKBC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:3 - JEP-106 Continuation Code"] + #[inline(always)] + pub fn jepcc(&self) -> JEPCC_R { + JEPCC_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - 4KB count"] + #[inline(always)] + pub fn fkbc(&self) -> FKBC_R { + FKBC_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +#[doc = "Peripheral Identification 4\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid4](index.html) module"] +pub struct PID4_SPEC; +impl crate::RegisterSpec for PID4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid4::R](R) reader structure"] +impl crate::Readable for PID4_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID4 to value 0"] +impl crate::Resettable for PID4_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/dsu/pid5.rs b/pac/atsamc20j/src/dsu/pid5.rs new file mode 100644 index 000000000000..d343d4800b95 --- /dev/null +++ b/pac/atsamc20j/src/dsu/pid5.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID5` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 5\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid5](index.html) module"] +pub struct PID5_SPEC; +impl crate::RegisterSpec for PID5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid5::R](R) reader structure"] +impl crate::Readable for PID5_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID5 to value 0"] +impl crate::Resettable for PID5_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/dsu/pid6.rs b/pac/atsamc20j/src/dsu/pid6.rs new file mode 100644 index 000000000000..55cc2b8b5861 --- /dev/null +++ b/pac/atsamc20j/src/dsu/pid6.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID6` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 6\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid6](index.html) module"] +pub struct PID6_SPEC; +impl crate::RegisterSpec for PID6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid6::R](R) reader structure"] +impl crate::Readable for PID6_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID6 to value 0"] +impl crate::Resettable for PID6_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/dsu/pid7.rs b/pac/atsamc20j/src/dsu/pid7.rs new file mode 100644 index 000000000000..77664d4f2f95 --- /dev/null +++ b/pac/atsamc20j/src/dsu/pid7.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID7` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 7\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid7](index.html) module"] +pub struct PID7_SPEC; +impl crate::RegisterSpec for PID7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid7::R](R) reader structure"] +impl crate::Readable for PID7_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID7 to value 0"] +impl crate::Resettable for PID7_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/dsu/statusa.rs b/pac/atsamc20j/src/dsu/statusa.rs new file mode 100644 index 000000000000..c7b90a13e491 --- /dev/null +++ b/pac/atsamc20j/src/dsu/statusa.rs @@ -0,0 +1,301 @@ +#[doc = "Register `STATUSA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUSA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DONE` reader - Done"] +pub struct DONE_R(crate::FieldReader); +impl DONE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DONE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DONE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DONE` writer - Done"] +pub struct DONE_W<'a> { + w: &'a mut W, +} +impl<'a> DONE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `CRSTEXT` reader - CPU Reset Phase Extension"] +pub struct CRSTEXT_R(crate::FieldReader); +impl CRSTEXT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CRSTEXT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CRSTEXT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRSTEXT` writer - CPU Reset Phase Extension"] +pub struct CRSTEXT_W<'a> { + w: &'a mut W, +} +impl<'a> CRSTEXT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `BERR` reader - Bus Error"] +pub struct BERR_R(crate::FieldReader); +impl BERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BERR` writer - Bus Error"] +pub struct BERR_W<'a> { + w: &'a mut W, +} +impl<'a> BERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `FAIL` reader - Failure"] +pub struct FAIL_R(crate::FieldReader); +impl FAIL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAIL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAIL` writer - Failure"] +pub struct FAIL_W<'a> { + w: &'a mut W, +} +impl<'a> FAIL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PERR` reader - Protection Error"] +pub struct PERR_R(crate::FieldReader); +impl PERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERR` writer - Protection Error"] +pub struct PERR_W<'a> { + w: &'a mut W, +} +impl<'a> PERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +impl R { + #[doc = "Bit 0 - Done"] + #[inline(always)] + pub fn done(&self) -> DONE_R { + DONE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - CPU Reset Phase Extension"] + #[inline(always)] + pub fn crstext(&self) -> CRSTEXT_R { + CRSTEXT_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Bus Error"] + #[inline(always)] + pub fn berr(&self) -> BERR_R { + BERR_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Failure"] + #[inline(always)] + pub fn fail(&self) -> FAIL_R { + FAIL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Protection Error"] + #[inline(always)] + pub fn perr(&self) -> PERR_R { + PERR_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Done"] + #[inline(always)] + pub fn done(&mut self) -> DONE_W { + DONE_W { w: self } + } + #[doc = "Bit 1 - CPU Reset Phase Extension"] + #[inline(always)] + pub fn crstext(&mut self) -> CRSTEXT_W { + CRSTEXT_W { w: self } + } + #[doc = "Bit 2 - Bus Error"] + #[inline(always)] + pub fn berr(&mut self) -> BERR_W { + BERR_W { w: self } + } + #[doc = "Bit 3 - Failure"] + #[inline(always)] + pub fn fail(&mut self) -> FAIL_W { + FAIL_W { w: self } + } + #[doc = "Bit 4 - Protection Error"] + #[inline(always)] + pub fn perr(&mut self) -> PERR_W { + PERR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [statusa](index.html) module"] +pub struct STATUSA_SPEC; +impl crate::RegisterSpec for STATUSA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [statusa::R](R) reader structure"] +impl crate::Readable for STATUSA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [statusa::W](W) writer structure"] +impl crate::Writable for STATUSA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUSA to value 0"] +impl crate::Resettable for STATUSA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/dsu/statusb.rs b/pac/atsamc20j/src/dsu/statusb.rs new file mode 100644 index 000000000000..1e9374f8deae --- /dev/null +++ b/pac/atsamc20j/src/dsu/statusb.rs @@ -0,0 +1,133 @@ +#[doc = "Register `STATUSB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PROT` reader - Protected"] +pub struct PROT_R(crate::FieldReader); +impl PROT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PROT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PROT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGPRES` reader - Debugger Present"] +pub struct DBGPRES_R(crate::FieldReader); +impl DBGPRES_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGPRES_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGPRES_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DCCD0` reader - Debug Communication Channel 0 Dirty"] +pub struct DCCD0_R(crate::FieldReader); +impl DCCD0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DCCD0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DCCD0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DCCD1` reader - Debug Communication Channel 1 Dirty"] +pub struct DCCD1_R(crate::FieldReader); +impl DCCD1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DCCD1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DCCD1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HPE` reader - Hot-Plugging Enable"] +pub struct HPE_R(crate::FieldReader); +impl HPE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HPE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HPE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Protected"] + #[inline(always)] + pub fn prot(&self) -> PROT_R { + PROT_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Debugger Present"] + #[inline(always)] + pub fn dbgpres(&self) -> DBGPRES_R { + DBGPRES_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Debug Communication Channel 0 Dirty"] + #[inline(always)] + pub fn dccd0(&self) -> DCCD0_R { + DCCD0_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Debug Communication Channel 1 Dirty"] + #[inline(always)] + pub fn dccd1(&self) -> DCCD1_R { + DCCD1_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Hot-Plugging Enable"] + #[inline(always)] + pub fn hpe(&self) -> HPE_R { + HPE_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +#[doc = "Status B\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [statusb](index.html) module"] +pub struct STATUSB_SPEC; +impl crate::RegisterSpec for STATUSB_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [statusb::R](R) reader structure"] +impl crate::Readable for STATUSB_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUSB to value 0"] +impl crate::Resettable for STATUSB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/dsu/statusc.rs b/pac/atsamc20j/src/dsu/statusc.rs new file mode 100644 index 000000000000..14b3f7b1c7e3 --- /dev/null +++ b/pac/atsamc20j/src/dsu/statusc.rs @@ -0,0 +1,53 @@ +#[doc = "Register `STATUSC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `STATE` reader - State"] +pub struct STATE_R(crate::FieldReader); +impl STATE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + STATE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STATE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:2 - State"] + #[inline(always)] + pub fn state(&self) -> STATE_R { + STATE_R::new((self.bits & 0x07) as u8) + } +} +#[doc = "Status C\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [statusc](index.html) module"] +pub struct STATUSC_SPEC; +impl crate::RegisterSpec for STATUSC_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [statusc::R](R) reader structure"] +impl crate::Readable for STATUSC_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUSC to value 0"] +impl crate::Resettable for STATUSC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/eic.rs b/pac/atsamc20j/src/eic.rs new file mode 100644 index 000000000000..606231233f4b --- /dev/null +++ b/pac/atsamc20j/src/eic.rs @@ -0,0 +1,64 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrla: crate::Reg, + #[doc = "0x01 - NMI Control"] + pub nmictrl: crate::Reg, + #[doc = "0x02 - NMI Interrupt Flag"] + pub nmiflag: crate::Reg, + #[doc = "0x04 - Syncbusy register"] + pub syncbusy: crate::Reg, + #[doc = "0x08 - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x0c - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x10 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x14 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x18 - EIC Asynchronous edge Detection Enable"] + pub asynch: crate::Reg, + #[doc = "0x1c..0x24 - Configuration n"] + pub config: [crate::Reg; 2], +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control"] +pub mod ctrla; +#[doc = "NMICTRL register accessor: an alias for `Reg`"] +pub type NMICTRL = crate::Reg; +#[doc = "NMI Control"] +pub mod nmictrl; +#[doc = "NMIFLAG register accessor: an alias for `Reg`"] +pub type NMIFLAG = crate::Reg; +#[doc = "NMI Interrupt Flag"] +pub mod nmiflag; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Syncbusy register"] +pub mod syncbusy; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "ASYNCH register accessor: an alias for `Reg`"] +pub type ASYNCH = crate::Reg; +#[doc = "EIC Asynchronous edge Detection Enable"] +pub mod asynch; +#[doc = "CONFIG register accessor: an alias for `Reg`"] +pub type CONFIG = crate::Reg; +#[doc = "Configuration n"] +pub mod config; diff --git a/pac/atsamc20j/src/eic/asynch.rs b/pac/atsamc20j/src/eic/asynch.rs new file mode 100644 index 000000000000..78a9b5c5f054 --- /dev/null +++ b/pac/atsamc20j/src/eic/asynch.rs @@ -0,0 +1,152 @@ +#[doc = "Register `ASYNCH` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ASYNCH` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "EIC Asynchronous edge Detection Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u16)] +pub enum ASYNCH_A { + #[doc = "0: Edge detection is clock synchronously operated"] + SYNC = 0, + #[doc = "1: Edge detection is clock asynchronously operated"] + ASYNC = 1, +} +impl From for u16 { + #[inline(always)] + fn from(variant: ASYNCH_A) -> Self { + variant as _ + } +} +#[doc = "Field `ASYNCH` reader - EIC Asynchronous edge Detection Enable"] +pub struct ASYNCH_R(crate::FieldReader); +impl ASYNCH_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + ASYNCH_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(ASYNCH_A::SYNC), + 1 => Some(ASYNCH_A::ASYNC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `SYNC`"] + #[inline(always)] + pub fn is_sync(&self) -> bool { + **self == ASYNCH_A::SYNC + } + #[doc = "Checks if the value of the field is `ASYNC`"] + #[inline(always)] + pub fn is_async(&self) -> bool { + **self == ASYNCH_A::ASYNC + } +} +impl core::ops::Deref for ASYNCH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ASYNCH` writer - EIC Asynchronous edge Detection Enable"] +pub struct ASYNCH_W<'a> { + w: &'a mut W, +} +impl<'a> ASYNCH_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: ASYNCH_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Edge detection is clock synchronously operated"] + #[inline(always)] + pub fn sync(self) -> &'a mut W { + self.variant(ASYNCH_A::SYNC) + } + #[doc = "Edge detection is clock asynchronously operated"] + #[inline(always)] + pub fn async_(self) -> &'a mut W { + self.variant(ASYNCH_A::ASYNC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - EIC Asynchronous edge Detection Enable"] + #[inline(always)] + pub fn asynch(&self) -> ASYNCH_R { + ASYNCH_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - EIC Asynchronous edge Detection Enable"] + #[inline(always)] + pub fn asynch(&mut self) -> ASYNCH_W { + ASYNCH_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "EIC Asynchronous edge Detection Enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [asynch](index.html) module"] +pub struct ASYNCH_SPEC; +impl crate::RegisterSpec for ASYNCH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [asynch::R](R) reader structure"] +impl crate::Readable for ASYNCH_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [asynch::W](W) writer structure"] +impl crate::Writable for ASYNCH_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ASYNCH to value 0"] +impl crate::Resettable for ASYNCH_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/eic/config.rs b/pac/atsamc20j/src/eic/config.rs new file mode 100644 index 000000000000..ab2c30950417 --- /dev/null +++ b/pac/atsamc20j/src/eic/config.rs @@ -0,0 +1,1547 @@ +#[doc = "Register `CONFIG[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CONFIG[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Input Sense Configuration 0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE0_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE0_A) -> Self { + variant as _ + } +} +#[doc = "Field `SENSE0` reader - Input Sense Configuration 0"] +pub struct SENSE0_R(crate::FieldReader); +impl SENSE0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SENSE0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE0_A::NONE), + 1 => Some(SENSE0_A::RISE), + 2 => Some(SENSE0_A::FALL), + 3 => Some(SENSE0_A::BOTH), + 4 => Some(SENSE0_A::HIGH), + 5 => Some(SENSE0_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == SENSE0_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == SENSE0_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == SENSE0_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == SENSE0_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SENSE0_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SENSE0_A::LOW + } +} +impl core::ops::Deref for SENSE0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SENSE0` writer - Input Sense Configuration 0"] +pub struct SENSE0_W<'a> { + w: &'a mut W, +} +impl<'a> SENSE0_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SENSE0_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE0_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE0_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE0_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE0_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE0_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE0_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Field `FILTEN0` reader - Filter Enable 0"] +pub struct FILTEN0_R(crate::FieldReader); +impl FILTEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FILTEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTEN0` writer - Filter Enable 0"] +pub struct FILTEN0_W<'a> { + w: &'a mut W, +} +impl<'a> FILTEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Input Sense Configuration 1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE1_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE1_A) -> Self { + variant as _ + } +} +#[doc = "Field `SENSE1` reader - Input Sense Configuration 1"] +pub struct SENSE1_R(crate::FieldReader); +impl SENSE1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SENSE1_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE1_A::NONE), + 1 => Some(SENSE1_A::RISE), + 2 => Some(SENSE1_A::FALL), + 3 => Some(SENSE1_A::BOTH), + 4 => Some(SENSE1_A::HIGH), + 5 => Some(SENSE1_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == SENSE1_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == SENSE1_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == SENSE1_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == SENSE1_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SENSE1_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SENSE1_A::LOW + } +} +impl core::ops::Deref for SENSE1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SENSE1` writer - Input Sense Configuration 1"] +pub struct SENSE1_W<'a> { + w: &'a mut W, +} +impl<'a> SENSE1_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SENSE1_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE1_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE1_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE1_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE1_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE1_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE1_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 4)) | ((value as u32 & 0x07) << 4); + self.w + } +} +#[doc = "Field `FILTEN1` reader - Filter Enable 1"] +pub struct FILTEN1_R(crate::FieldReader); +impl FILTEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FILTEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTEN1` writer - Filter Enable 1"] +pub struct FILTEN1_W<'a> { + w: &'a mut W, +} +impl<'a> FILTEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Input Sense Configuration 2\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE2_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE2_A) -> Self { + variant as _ + } +} +#[doc = "Field `SENSE2` reader - Input Sense Configuration 2"] +pub struct SENSE2_R(crate::FieldReader); +impl SENSE2_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SENSE2_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE2_A::NONE), + 1 => Some(SENSE2_A::RISE), + 2 => Some(SENSE2_A::FALL), + 3 => Some(SENSE2_A::BOTH), + 4 => Some(SENSE2_A::HIGH), + 5 => Some(SENSE2_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == SENSE2_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == SENSE2_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == SENSE2_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == SENSE2_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SENSE2_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SENSE2_A::LOW + } +} +impl core::ops::Deref for SENSE2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SENSE2` writer - Input Sense Configuration 2"] +pub struct SENSE2_W<'a> { + w: &'a mut W, +} +impl<'a> SENSE2_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SENSE2_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE2_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE2_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE2_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE2_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE2_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE2_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +#[doc = "Field `FILTEN2` reader - Filter Enable 2"] +pub struct FILTEN2_R(crate::FieldReader); +impl FILTEN2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FILTEN2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTEN2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTEN2` writer - Filter Enable 2"] +pub struct FILTEN2_W<'a> { + w: &'a mut W, +} +impl<'a> FILTEN2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Input Sense Configuration 3\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE3_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE3_A) -> Self { + variant as _ + } +} +#[doc = "Field `SENSE3` reader - Input Sense Configuration 3"] +pub struct SENSE3_R(crate::FieldReader); +impl SENSE3_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SENSE3_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE3_A::NONE), + 1 => Some(SENSE3_A::RISE), + 2 => Some(SENSE3_A::FALL), + 3 => Some(SENSE3_A::BOTH), + 4 => Some(SENSE3_A::HIGH), + 5 => Some(SENSE3_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == SENSE3_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == SENSE3_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == SENSE3_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == SENSE3_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SENSE3_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SENSE3_A::LOW + } +} +impl core::ops::Deref for SENSE3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SENSE3` writer - Input Sense Configuration 3"] +pub struct SENSE3_W<'a> { + w: &'a mut W, +} +impl<'a> SENSE3_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SENSE3_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE3_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE3_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE3_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE3_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE3_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE3_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 12)) | ((value as u32 & 0x07) << 12); + self.w + } +} +#[doc = "Field `FILTEN3` reader - Filter Enable 3"] +pub struct FILTEN3_R(crate::FieldReader); +impl FILTEN3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FILTEN3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTEN3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTEN3` writer - Filter Enable 3"] +pub struct FILTEN3_W<'a> { + w: &'a mut W, +} +impl<'a> FILTEN3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Input Sense Configuration 4\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE4_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE4_A) -> Self { + variant as _ + } +} +#[doc = "Field `SENSE4` reader - Input Sense Configuration 4"] +pub struct SENSE4_R(crate::FieldReader); +impl SENSE4_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SENSE4_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE4_A::NONE), + 1 => Some(SENSE4_A::RISE), + 2 => Some(SENSE4_A::FALL), + 3 => Some(SENSE4_A::BOTH), + 4 => Some(SENSE4_A::HIGH), + 5 => Some(SENSE4_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == SENSE4_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == SENSE4_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == SENSE4_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == SENSE4_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SENSE4_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SENSE4_A::LOW + } +} +impl core::ops::Deref for SENSE4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SENSE4` writer - Input Sense Configuration 4"] +pub struct SENSE4_W<'a> { + w: &'a mut W, +} +impl<'a> SENSE4_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SENSE4_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE4_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE4_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE4_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE4_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE4_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE4_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 16)) | ((value as u32 & 0x07) << 16); + self.w + } +} +#[doc = "Field `FILTEN4` reader - Filter Enable 4"] +pub struct FILTEN4_R(crate::FieldReader); +impl FILTEN4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FILTEN4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTEN4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTEN4` writer - Filter Enable 4"] +pub struct FILTEN4_W<'a> { + w: &'a mut W, +} +impl<'a> FILTEN4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Input Sense Configuration 5\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE5_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE5_A) -> Self { + variant as _ + } +} +#[doc = "Field `SENSE5` reader - Input Sense Configuration 5"] +pub struct SENSE5_R(crate::FieldReader); +impl SENSE5_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SENSE5_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE5_A::NONE), + 1 => Some(SENSE5_A::RISE), + 2 => Some(SENSE5_A::FALL), + 3 => Some(SENSE5_A::BOTH), + 4 => Some(SENSE5_A::HIGH), + 5 => Some(SENSE5_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == SENSE5_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == SENSE5_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == SENSE5_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == SENSE5_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SENSE5_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SENSE5_A::LOW + } +} +impl core::ops::Deref for SENSE5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SENSE5` writer - Input Sense Configuration 5"] +pub struct SENSE5_W<'a> { + w: &'a mut W, +} +impl<'a> SENSE5_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SENSE5_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE5_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE5_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE5_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE5_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE5_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE5_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 20)) | ((value as u32 & 0x07) << 20); + self.w + } +} +#[doc = "Field `FILTEN5` reader - Filter Enable 5"] +pub struct FILTEN5_R(crate::FieldReader); +impl FILTEN5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FILTEN5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTEN5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTEN5` writer - Filter Enable 5"] +pub struct FILTEN5_W<'a> { + w: &'a mut W, +} +impl<'a> FILTEN5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Input Sense Configuration 6\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE6_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE6_A) -> Self { + variant as _ + } +} +#[doc = "Field `SENSE6` reader - Input Sense Configuration 6"] +pub struct SENSE6_R(crate::FieldReader); +impl SENSE6_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SENSE6_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE6_A::NONE), + 1 => Some(SENSE6_A::RISE), + 2 => Some(SENSE6_A::FALL), + 3 => Some(SENSE6_A::BOTH), + 4 => Some(SENSE6_A::HIGH), + 5 => Some(SENSE6_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == SENSE6_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == SENSE6_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == SENSE6_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == SENSE6_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SENSE6_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SENSE6_A::LOW + } +} +impl core::ops::Deref for SENSE6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SENSE6` writer - Input Sense Configuration 6"] +pub struct SENSE6_W<'a> { + w: &'a mut W, +} +impl<'a> SENSE6_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SENSE6_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE6_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE6_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE6_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE6_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE6_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE6_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 24)) | ((value as u32 & 0x07) << 24); + self.w + } +} +#[doc = "Field `FILTEN6` reader - Filter Enable 6"] +pub struct FILTEN6_R(crate::FieldReader); +impl FILTEN6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FILTEN6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTEN6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTEN6` writer - Filter Enable 6"] +pub struct FILTEN6_W<'a> { + w: &'a mut W, +} +impl<'a> FILTEN6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +#[doc = "Input Sense Configuration 7\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE7_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE7_A) -> Self { + variant as _ + } +} +#[doc = "Field `SENSE7` reader - Input Sense Configuration 7"] +pub struct SENSE7_R(crate::FieldReader); +impl SENSE7_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SENSE7_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE7_A::NONE), + 1 => Some(SENSE7_A::RISE), + 2 => Some(SENSE7_A::FALL), + 3 => Some(SENSE7_A::BOTH), + 4 => Some(SENSE7_A::HIGH), + 5 => Some(SENSE7_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == SENSE7_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == SENSE7_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == SENSE7_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == SENSE7_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SENSE7_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SENSE7_A::LOW + } +} +impl core::ops::Deref for SENSE7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SENSE7` writer - Input Sense Configuration 7"] +pub struct SENSE7_W<'a> { + w: &'a mut W, +} +impl<'a> SENSE7_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SENSE7_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE7_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE7_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE7_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE7_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE7_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE7_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 28)) | ((value as u32 & 0x07) << 28); + self.w + } +} +#[doc = "Field `FILTEN7` reader - Filter Enable 7"] +pub struct FILTEN7_R(crate::FieldReader); +impl FILTEN7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FILTEN7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTEN7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTEN7` writer - Filter Enable 7"] +pub struct FILTEN7_W<'a> { + w: &'a mut W, +} +impl<'a> FILTEN7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Input Sense Configuration 0"] + #[inline(always)] + pub fn sense0(&self) -> SENSE0_R { + SENSE0_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 3 - Filter Enable 0"] + #[inline(always)] + pub fn filten0(&self) -> FILTEN0_R { + FILTEN0_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bits 4:6 - Input Sense Configuration 1"] + #[inline(always)] + pub fn sense1(&self) -> SENSE1_R { + SENSE1_R::new(((self.bits >> 4) & 0x07) as u8) + } + #[doc = "Bit 7 - Filter Enable 1"] + #[inline(always)] + pub fn filten1(&self) -> FILTEN1_R { + FILTEN1_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Input Sense Configuration 2"] + #[inline(always)] + pub fn sense2(&self) -> SENSE2_R { + SENSE2_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 11 - Filter Enable 2"] + #[inline(always)] + pub fn filten2(&self) -> FILTEN2_R { + FILTEN2_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bits 12:14 - Input Sense Configuration 3"] + #[inline(always)] + pub fn sense3(&self) -> SENSE3_R { + SENSE3_R::new(((self.bits >> 12) & 0x07) as u8) + } + #[doc = "Bit 15 - Filter Enable 3"] + #[inline(always)] + pub fn filten3(&self) -> FILTEN3_R { + FILTEN3_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:18 - Input Sense Configuration 4"] + #[inline(always)] + pub fn sense4(&self) -> SENSE4_R { + SENSE4_R::new(((self.bits >> 16) & 0x07) as u8) + } + #[doc = "Bit 19 - Filter Enable 4"] + #[inline(always)] + pub fn filten4(&self) -> FILTEN4_R { + FILTEN4_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bits 20:22 - Input Sense Configuration 5"] + #[inline(always)] + pub fn sense5(&self) -> SENSE5_R { + SENSE5_R::new(((self.bits >> 20) & 0x07) as u8) + } + #[doc = "Bit 23 - Filter Enable 5"] + #[inline(always)] + pub fn filten5(&self) -> FILTEN5_R { + FILTEN5_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bits 24:26 - Input Sense Configuration 6"] + #[inline(always)] + pub fn sense6(&self) -> SENSE6_R { + SENSE6_R::new(((self.bits >> 24) & 0x07) as u8) + } + #[doc = "Bit 27 - Filter Enable 6"] + #[inline(always)] + pub fn filten6(&self) -> FILTEN6_R { + FILTEN6_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bits 28:30 - Input Sense Configuration 7"] + #[inline(always)] + pub fn sense7(&self) -> SENSE7_R { + SENSE7_R::new(((self.bits >> 28) & 0x07) as u8) + } + #[doc = "Bit 31 - Filter Enable 7"] + #[inline(always)] + pub fn filten7(&self) -> FILTEN7_R { + FILTEN7_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Input Sense Configuration 0"] + #[inline(always)] + pub fn sense0(&mut self) -> SENSE0_W { + SENSE0_W { w: self } + } + #[doc = "Bit 3 - Filter Enable 0"] + #[inline(always)] + pub fn filten0(&mut self) -> FILTEN0_W { + FILTEN0_W { w: self } + } + #[doc = "Bits 4:6 - Input Sense Configuration 1"] + #[inline(always)] + pub fn sense1(&mut self) -> SENSE1_W { + SENSE1_W { w: self } + } + #[doc = "Bit 7 - Filter Enable 1"] + #[inline(always)] + pub fn filten1(&mut self) -> FILTEN1_W { + FILTEN1_W { w: self } + } + #[doc = "Bits 8:10 - Input Sense Configuration 2"] + #[inline(always)] + pub fn sense2(&mut self) -> SENSE2_W { + SENSE2_W { w: self } + } + #[doc = "Bit 11 - Filter Enable 2"] + #[inline(always)] + pub fn filten2(&mut self) -> FILTEN2_W { + FILTEN2_W { w: self } + } + #[doc = "Bits 12:14 - Input Sense Configuration 3"] + #[inline(always)] + pub fn sense3(&mut self) -> SENSE3_W { + SENSE3_W { w: self } + } + #[doc = "Bit 15 - Filter Enable 3"] + #[inline(always)] + pub fn filten3(&mut self) -> FILTEN3_W { + FILTEN3_W { w: self } + } + #[doc = "Bits 16:18 - Input Sense Configuration 4"] + #[inline(always)] + pub fn sense4(&mut self) -> SENSE4_W { + SENSE4_W { w: self } + } + #[doc = "Bit 19 - Filter Enable 4"] + #[inline(always)] + pub fn filten4(&mut self) -> FILTEN4_W { + FILTEN4_W { w: self } + } + #[doc = "Bits 20:22 - Input Sense Configuration 5"] + #[inline(always)] + pub fn sense5(&mut self) -> SENSE5_W { + SENSE5_W { w: self } + } + #[doc = "Bit 23 - Filter Enable 5"] + #[inline(always)] + pub fn filten5(&mut self) -> FILTEN5_W { + FILTEN5_W { w: self } + } + #[doc = "Bits 24:26 - Input Sense Configuration 6"] + #[inline(always)] + pub fn sense6(&mut self) -> SENSE6_W { + SENSE6_W { w: self } + } + #[doc = "Bit 27 - Filter Enable 6"] + #[inline(always)] + pub fn filten6(&mut self) -> FILTEN6_W { + FILTEN6_W { w: self } + } + #[doc = "Bits 28:30 - Input Sense Configuration 7"] + #[inline(always)] + pub fn sense7(&mut self) -> SENSE7_W { + SENSE7_W { w: self } + } + #[doc = "Bit 31 - Filter Enable 7"] + #[inline(always)] + pub fn filten7(&mut self) -> FILTEN7_W { + FILTEN7_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Configuration n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [config](index.html) module"] +pub struct CONFIG_SPEC; +impl crate::RegisterSpec for CONFIG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [config::R](R) reader structure"] +impl crate::Readable for CONFIG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [config::W](W) writer structure"] +impl crate::Writable for CONFIG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CONFIG[%s] +to value 0"] +impl crate::Resettable for CONFIG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/eic/ctrla.rs b/pac/atsamc20j/src/eic/ctrla.rs new file mode 100644 index 000000000000..25e701dd3db2 --- /dev/null +++ b/pac/atsamc20j/src/eic/ctrla.rs @@ -0,0 +1,254 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Clock Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CKSEL_A { + #[doc = "0: Clocked by GCLK"] + CLK_GCLK = 0, + #[doc = "1: Clocked by ULP32K"] + CLK_ULP32K = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CKSEL_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CKSEL` reader - Clock Selection"] +pub struct CKSEL_R(crate::FieldReader); +impl CKSEL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CKSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CKSEL_A { + match self.bits { + false => CKSEL_A::CLK_GCLK, + true => CKSEL_A::CLK_ULP32K, + } + } + #[doc = "Checks if the value of the field is `CLK_GCLK`"] + #[inline(always)] + pub fn is_clk_gclk(&self) -> bool { + **self == CKSEL_A::CLK_GCLK + } + #[doc = "Checks if the value of the field is `CLK_ULP32K`"] + #[inline(always)] + pub fn is_clk_ulp32k(&self) -> bool { + **self == CKSEL_A::CLK_ULP32K + } +} +impl core::ops::Deref for CKSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CKSEL` writer - Clock Selection"] +pub struct CKSEL_W<'a> { + w: &'a mut W, +} +impl<'a> CKSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CKSEL_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Clocked by GCLK"] + #[inline(always)] + pub fn clk_gclk(self) -> &'a mut W { + self.variant(CKSEL_A::CLK_GCLK) + } + #[doc = "Clocked by ULP32K"] + #[inline(always)] + pub fn clk_ulp32k(self) -> &'a mut W { + self.variant(CKSEL_A::CLK_ULP32K) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - Clock Selection"] + #[inline(always)] + pub fn cksel(&self) -> CKSEL_R { + CKSEL_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 4 - Clock Selection"] + #[inline(always)] + pub fn cksel(&mut self) -> CKSEL_W { + CKSEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/eic/evctrl.rs b/pac/atsamc20j/src/eic/evctrl.rs new file mode 100644 index 000000000000..25adccf3558e --- /dev/null +++ b/pac/atsamc20j/src/eic/evctrl.rs @@ -0,0 +1,103 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EXTINTEO` reader - External Interrupt Event Output Enable"] +pub struct EXTINTEO_R(crate::FieldReader); +impl EXTINTEO_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + EXTINTEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINTEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINTEO` writer - External Interrupt Event Output Enable"] +pub struct EXTINTEO_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINTEO_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - External Interrupt Event Output Enable"] + #[inline(always)] + pub fn extinteo(&self) -> EXTINTEO_R { + EXTINTEO_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - External Interrupt Event Output Enable"] + #[inline(always)] + pub fn extinteo(&mut self) -> EXTINTEO_W { + EXTINTEO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/eic/intenclr.rs b/pac/atsamc20j/src/eic/intenclr.rs new file mode 100644 index 000000000000..198c3aac9eb1 --- /dev/null +++ b/pac/atsamc20j/src/eic/intenclr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EXTINT` reader - External Interrupt Disable"] +pub struct EXTINT_R(crate::FieldReader); +impl EXTINT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + EXTINT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT` writer - External Interrupt Disable"] +pub struct EXTINT_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - External Interrupt Disable"] + #[inline(always)] + pub fn extint(&self) -> EXTINT_R { + EXTINT_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - External Interrupt Disable"] + #[inline(always)] + pub fn extint(&mut self) -> EXTINT_W { + EXTINT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/eic/intenset.rs b/pac/atsamc20j/src/eic/intenset.rs new file mode 100644 index 000000000000..e2ff6729d71f --- /dev/null +++ b/pac/atsamc20j/src/eic/intenset.rs @@ -0,0 +1,103 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EXTINT` reader - External Interrupt Enable"] +pub struct EXTINT_R(crate::FieldReader); +impl EXTINT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + EXTINT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT` writer - External Interrupt Enable"] +pub struct EXTINT_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - External Interrupt Enable"] + #[inline(always)] + pub fn extint(&self) -> EXTINT_R { + EXTINT_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - External Interrupt Enable"] + #[inline(always)] + pub fn extint(&mut self) -> EXTINT_W { + EXTINT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/eic/intflag.rs b/pac/atsamc20j/src/eic/intflag.rs new file mode 100644 index 000000000000..df2f15490feb --- /dev/null +++ b/pac/atsamc20j/src/eic/intflag.rs @@ -0,0 +1,103 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EXTINT` reader - External Interrupt Flag"] +pub struct EXTINT_R(crate::FieldReader); +impl EXTINT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + EXTINT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT` writer - External Interrupt Flag"] +pub struct EXTINT_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - External Interrupt Flag"] + #[inline(always)] + pub fn extint(&self) -> EXTINT_R { + EXTINT_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - External Interrupt Flag"] + #[inline(always)] + pub fn extint(&mut self) -> EXTINT_W { + EXTINT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/eic/nmictrl.rs b/pac/atsamc20j/src/eic/nmictrl.rs new file mode 100644 index 000000000000..c9b276ea2a29 --- /dev/null +++ b/pac/atsamc20j/src/eic/nmictrl.rs @@ -0,0 +1,345 @@ +#[doc = "Register `NMICTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `NMICTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "NMI Input Sense Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum NMISENSE_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising-edge detection"] + RISE = 1, + #[doc = "2: Falling-edge detection"] + FALL = 2, + #[doc = "3: Both-edges detection"] + BOTH = 3, + #[doc = "4: High-level detection"] + HIGH = 4, + #[doc = "5: Low-level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: NMISENSE_A) -> Self { + variant as _ + } +} +#[doc = "Field `NMISENSE` reader - NMI Input Sense Configuration"] +pub struct NMISENSE_R(crate::FieldReader); +impl NMISENSE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + NMISENSE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(NMISENSE_A::NONE), + 1 => Some(NMISENSE_A::RISE), + 2 => Some(NMISENSE_A::FALL), + 3 => Some(NMISENSE_A::BOTH), + 4 => Some(NMISENSE_A::HIGH), + 5 => Some(NMISENSE_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == NMISENSE_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == NMISENSE_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == NMISENSE_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == NMISENSE_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == NMISENSE_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == NMISENSE_A::LOW + } +} +impl core::ops::Deref for NMISENSE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NMISENSE` writer - NMI Input Sense Configuration"] +pub struct NMISENSE_W<'a> { + w: &'a mut W, +} +impl<'a> NMISENSE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: NMISENSE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(NMISENSE_A::NONE) + } + #[doc = "Rising-edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(NMISENSE_A::RISE) + } + #[doc = "Falling-edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(NMISENSE_A::FALL) + } + #[doc = "Both-edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(NMISENSE_A::BOTH) + } + #[doc = "High-level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(NMISENSE_A::HIGH) + } + #[doc = "Low-level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(NMISENSE_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +#[doc = "Field `NMIFILTEN` reader - NMI Filter Enable"] +pub struct NMIFILTEN_R(crate::FieldReader); +impl NMIFILTEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NMIFILTEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NMIFILTEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NMIFILTEN` writer - NMI Filter Enable"] +pub struct NMIFILTEN_W<'a> { + w: &'a mut W, +} +impl<'a> NMIFILTEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "NMI Asynchronous edge Detection Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum NMIASYNCH_A { + #[doc = "0: Edge detection is clock synchronously operated"] + SYNC = 0, + #[doc = "1: Edge detection is clock asynchronously operated"] + ASYNC = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NMIASYNCH_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NMIASYNCH` reader - NMI Asynchronous edge Detection Enable"] +pub struct NMIASYNCH_R(crate::FieldReader); +impl NMIASYNCH_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NMIASYNCH_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> NMIASYNCH_A { + match self.bits { + false => NMIASYNCH_A::SYNC, + true => NMIASYNCH_A::ASYNC, + } + } + #[doc = "Checks if the value of the field is `SYNC`"] + #[inline(always)] + pub fn is_sync(&self) -> bool { + **self == NMIASYNCH_A::SYNC + } + #[doc = "Checks if the value of the field is `ASYNC`"] + #[inline(always)] + pub fn is_async(&self) -> bool { + **self == NMIASYNCH_A::ASYNC + } +} +impl core::ops::Deref for NMIASYNCH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NMIASYNCH` writer - NMI Asynchronous edge Detection Enable"] +pub struct NMIASYNCH_W<'a> { + w: &'a mut W, +} +impl<'a> NMIASYNCH_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: NMIASYNCH_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Edge detection is clock synchronously operated"] + #[inline(always)] + pub fn sync(self) -> &'a mut W { + self.variant(NMIASYNCH_A::SYNC) + } + #[doc = "Edge detection is clock asynchronously operated"] + #[inline(always)] + pub fn async_(self) -> &'a mut W { + self.variant(NMIASYNCH_A::ASYNC) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - NMI Input Sense Configuration"] + #[inline(always)] + pub fn nmisense(&self) -> NMISENSE_R { + NMISENSE_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 3 - NMI Filter Enable"] + #[inline(always)] + pub fn nmifilten(&self) -> NMIFILTEN_R { + NMIFILTEN_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - NMI Asynchronous edge Detection Enable"] + #[inline(always)] + pub fn nmiasynch(&self) -> NMIASYNCH_R { + NMIASYNCH_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - NMI Input Sense Configuration"] + #[inline(always)] + pub fn nmisense(&mut self) -> NMISENSE_W { + NMISENSE_W { w: self } + } + #[doc = "Bit 3 - NMI Filter Enable"] + #[inline(always)] + pub fn nmifilten(&mut self) -> NMIFILTEN_W { + NMIFILTEN_W { w: self } + } + #[doc = "Bit 4 - NMI Asynchronous edge Detection Enable"] + #[inline(always)] + pub fn nmiasynch(&mut self) -> NMIASYNCH_W { + NMIASYNCH_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "NMI Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [nmictrl](index.html) module"] +pub struct NMICTRL_SPEC; +impl crate::RegisterSpec for NMICTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [nmictrl::R](R) reader structure"] +impl crate::Readable for NMICTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [nmictrl::W](W) writer structure"] +impl crate::Writable for NMICTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets NMICTRL to value 0"] +impl crate::Resettable for NMICTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/eic/nmiflag.rs b/pac/atsamc20j/src/eic/nmiflag.rs new file mode 100644 index 000000000000..97934b501c12 --- /dev/null +++ b/pac/atsamc20j/src/eic/nmiflag.rs @@ -0,0 +1,113 @@ +#[doc = "Register `NMIFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `NMIFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `NMI` reader - NMI Interrupt Flag"] +pub struct NMI_R(crate::FieldReader); +impl NMI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NMI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NMI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NMI` writer - NMI Interrupt Flag"] +pub struct NMI_W<'a> { + w: &'a mut W, +} +impl<'a> NMI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - NMI Interrupt Flag"] + #[inline(always)] + pub fn nmi(&self) -> NMI_R { + NMI_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - NMI Interrupt Flag"] + #[inline(always)] + pub fn nmi(&mut self) -> NMI_W { + NMI_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "NMI Interrupt Flag\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [nmiflag](index.html) module"] +pub struct NMIFLAG_SPEC; +impl crate::RegisterSpec for NMIFLAG_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [nmiflag::R](R) reader structure"] +impl crate::Readable for NMIFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [nmiflag::W](W) writer structure"] +impl crate::Writable for NMIFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets NMIFLAG to value 0"] +impl crate::Resettable for NMIFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/eic/syncbusy.rs b/pac/atsamc20j/src/eic/syncbusy.rs new file mode 100644 index 000000000000..84d125d0acf1 --- /dev/null +++ b/pac/atsamc20j/src/eic/syncbusy.rs @@ -0,0 +1,73 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software reset synchronisation"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - Enable synchronisation"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software reset synchronisation"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable synchronisation"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +#[doc = "Syncbusy register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/evsys.rs b/pac/atsamc20j/src/evsys.rs new file mode 100644 index 000000000000..20d569fd3b90 --- /dev/null +++ b/pac/atsamc20j/src/evsys.rs @@ -0,0 +1,54 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrla: crate::Reg, + _reserved1: [u8; 0x0b], + #[doc = "0x0c - Channel Status"] + pub chstatus: crate::Reg, + #[doc = "0x10 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x14 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x18 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x1c - Software Event"] + pub swevt: crate::Reg, + #[doc = "0x20..0x38 - Channel n"] + pub channel: [crate::Reg; 6], + _reserved7: [u8; 0x48], + #[doc = "0x80..0x13c - User Multiplexer n"] + pub user: [crate::Reg; 47], +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control"] +pub mod ctrla; +#[doc = "CHSTATUS register accessor: an alias for `Reg`"] +pub type CHSTATUS = crate::Reg; +#[doc = "Channel Status"] +pub mod chstatus; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "SWEVT register accessor: an alias for `Reg`"] +pub type SWEVT = crate::Reg; +#[doc = "Software Event"] +pub mod swevt; +#[doc = "CHANNEL register accessor: an alias for `Reg`"] +pub type CHANNEL = crate::Reg; +#[doc = "Channel n"] +pub mod channel; +#[doc = "USER register accessor: an alias for `Reg`"] +pub type USER = crate::Reg; +#[doc = "User Multiplexer n"] +pub mod user; diff --git a/pac/atsamc20j/src/evsys/channel.rs b/pac/atsamc20j/src/evsys/channel.rs new file mode 100644 index 000000000000..20e3857da922 --- /dev/null +++ b/pac/atsamc20j/src/evsys/channel.rs @@ -0,0 +1,409 @@ +#[doc = "Register `CHANNEL[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHANNEL[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVGEN` reader - Event Generator Selection"] +pub struct EVGEN_R(crate::FieldReader); +impl EVGEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVGEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVGEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVGEN` writer - Event Generator Selection"] +pub struct EVGEN_W<'a> { + w: &'a mut W, +} +impl<'a> EVGEN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x7f) | (value as u32 & 0x7f); + self.w + } +} +#[doc = "Path Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PATH_A { + #[doc = "0: Synchronous path"] + SYNCHRONOUS = 0, + #[doc = "1: Resynchronized path"] + RESYNCHRONIZED = 1, + #[doc = "2: Asynchronous path"] + ASYNCHRONOUS = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PATH_A) -> Self { + variant as _ + } +} +#[doc = "Field `PATH` reader - Path Selection"] +pub struct PATH_R(crate::FieldReader); +impl PATH_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PATH_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PATH_A::SYNCHRONOUS), + 1 => Some(PATH_A::RESYNCHRONIZED), + 2 => Some(PATH_A::ASYNCHRONOUS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `SYNCHRONOUS`"] + #[inline(always)] + pub fn is_synchronous(&self) -> bool { + **self == PATH_A::SYNCHRONOUS + } + #[doc = "Checks if the value of the field is `RESYNCHRONIZED`"] + #[inline(always)] + pub fn is_resynchronized(&self) -> bool { + **self == PATH_A::RESYNCHRONIZED + } + #[doc = "Checks if the value of the field is `ASYNCHRONOUS`"] + #[inline(always)] + pub fn is_asynchronous(&self) -> bool { + **self == PATH_A::ASYNCHRONOUS + } +} +impl core::ops::Deref for PATH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PATH` writer - Path Selection"] +pub struct PATH_W<'a> { + w: &'a mut W, +} +impl<'a> PATH_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PATH_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Synchronous path"] + #[inline(always)] + pub fn synchronous(self) -> &'a mut W { + self.variant(PATH_A::SYNCHRONOUS) + } + #[doc = "Resynchronized path"] + #[inline(always)] + pub fn resynchronized(self) -> &'a mut W { + self.variant(PATH_A::RESYNCHRONIZED) + } + #[doc = "Asynchronous path"] + #[inline(always)] + pub fn asynchronous(self) -> &'a mut W { + self.variant(PATH_A::ASYNCHRONOUS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 8)) | ((value as u32 & 0x03) << 8); + self.w + } +} +#[doc = "Edge Detection Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EDGSEL_A { + #[doc = "0: No event output when using the resynchronized or synchronous path"] + NO_EVT_OUTPUT = 0, + #[doc = "1: Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path"] + RISING_EDGE = 1, + #[doc = "2: Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path"] + FALLING_EDGE = 2, + #[doc = "3: Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path"] + BOTH_EDGES = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EDGSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `EDGSEL` reader - Edge Detection Selection"] +pub struct EDGSEL_R(crate::FieldReader); +impl EDGSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EDGSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EDGSEL_A { + match self.bits { + 0 => EDGSEL_A::NO_EVT_OUTPUT, + 1 => EDGSEL_A::RISING_EDGE, + 2 => EDGSEL_A::FALLING_EDGE, + 3 => EDGSEL_A::BOTH_EDGES, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NO_EVT_OUTPUT`"] + #[inline(always)] + pub fn is_no_evt_output(&self) -> bool { + **self == EDGSEL_A::NO_EVT_OUTPUT + } + #[doc = "Checks if the value of the field is `RISING_EDGE`"] + #[inline(always)] + pub fn is_rising_edge(&self) -> bool { + **self == EDGSEL_A::RISING_EDGE + } + #[doc = "Checks if the value of the field is `FALLING_EDGE`"] + #[inline(always)] + pub fn is_falling_edge(&self) -> bool { + **self == EDGSEL_A::FALLING_EDGE + } + #[doc = "Checks if the value of the field is `BOTH_EDGES`"] + #[inline(always)] + pub fn is_both_edges(&self) -> bool { + **self == EDGSEL_A::BOTH_EDGES + } +} +impl core::ops::Deref for EDGSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EDGSEL` writer - Edge Detection Selection"] +pub struct EDGSEL_W<'a> { + w: &'a mut W, +} +impl<'a> EDGSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EDGSEL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "No event output when using the resynchronized or synchronous path"] + #[inline(always)] + pub fn no_evt_output(self) -> &'a mut W { + self.variant(EDGSEL_A::NO_EVT_OUTPUT) + } + #[doc = "Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path"] + #[inline(always)] + pub fn rising_edge(self) -> &'a mut W { + self.variant(EDGSEL_A::RISING_EDGE) + } + #[doc = "Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path"] + #[inline(always)] + pub fn falling_edge(self) -> &'a mut W { + self.variant(EDGSEL_A::FALLING_EDGE) + } + #[doc = "Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path"] + #[inline(always)] + pub fn both_edges(self) -> &'a mut W { + self.variant(EDGSEL_A::BOTH_EDGES) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 10)) | ((value as u32 & 0x03) << 10); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - Generic Clock On Demand"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - Generic Clock On Demand"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bits 0:6 - Event Generator Selection"] + #[inline(always)] + pub fn evgen(&self) -> EVGEN_R { + EVGEN_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bits 8:9 - Path Selection"] + #[inline(always)] + pub fn path(&self) -> PATH_R { + PATH_R::new(((self.bits >> 8) & 0x03) as u8) + } + #[doc = "Bits 10:11 - Edge Detection Selection"] + #[inline(always)] + pub fn edgsel(&self) -> EDGSEL_R { + EDGSEL_R::new(((self.bits >> 10) & 0x03) as u8) + } + #[doc = "Bit 14 - Run in standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Generic Clock On Demand"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:6 - Event Generator Selection"] + #[inline(always)] + pub fn evgen(&mut self) -> EVGEN_W { + EVGEN_W { w: self } + } + #[doc = "Bits 8:9 - Path Selection"] + #[inline(always)] + pub fn path(&mut self) -> PATH_W { + PATH_W { w: self } + } + #[doc = "Bits 10:11 - Edge Detection Selection"] + #[inline(always)] + pub fn edgsel(&mut self) -> EDGSEL_W { + EDGSEL_W { w: self } + } + #[doc = "Bit 14 - Run in standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 15 - Generic Clock On Demand"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [channel](index.html) module"] +pub struct CHANNEL_SPEC; +impl crate::RegisterSpec for CHANNEL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [channel::R](R) reader structure"] +impl crate::Readable for CHANNEL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [channel::W](W) writer structure"] +impl crate::Writable for CHANNEL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHANNEL[%s] +to value 0x8000"] +impl crate::Resettable for CHANNEL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x8000 + } +} diff --git a/pac/atsamc20j/src/evsys/chstatus.rs b/pac/atsamc20j/src/evsys/chstatus.rs new file mode 100644 index 000000000000..43004730356d --- /dev/null +++ b/pac/atsamc20j/src/evsys/chstatus.rs @@ -0,0 +1,273 @@ +#[doc = "Register `CHSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `USRRDY0` reader - Channel 0 User Ready"] +pub struct USRRDY0_R(crate::FieldReader); +impl USRRDY0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY1` reader - Channel 1 User Ready"] +pub struct USRRDY1_R(crate::FieldReader); +impl USRRDY1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY2` reader - Channel 2 User Ready"] +pub struct USRRDY2_R(crate::FieldReader); +impl USRRDY2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY3` reader - Channel 3 User Ready"] +pub struct USRRDY3_R(crate::FieldReader); +impl USRRDY3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY4` reader - Channel 4 User Ready"] +pub struct USRRDY4_R(crate::FieldReader); +impl USRRDY4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY5` reader - Channel 5 User Ready"] +pub struct USRRDY5_R(crate::FieldReader); +impl USRRDY5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY0` reader - Channel 0 Busy"] +pub struct CHBUSY0_R(crate::FieldReader); +impl CHBUSY0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY1` reader - Channel 1 Busy"] +pub struct CHBUSY1_R(crate::FieldReader); +impl CHBUSY1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY2` reader - Channel 2 Busy"] +pub struct CHBUSY2_R(crate::FieldReader); +impl CHBUSY2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY3` reader - Channel 3 Busy"] +pub struct CHBUSY3_R(crate::FieldReader); +impl CHBUSY3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY4` reader - Channel 4 Busy"] +pub struct CHBUSY4_R(crate::FieldReader); +impl CHBUSY4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY5` reader - Channel 5 Busy"] +pub struct CHBUSY5_R(crate::FieldReader); +impl CHBUSY5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Channel 0 User Ready"] + #[inline(always)] + pub fn usrrdy0(&self) -> USRRDY0_R { + USRRDY0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel 1 User Ready"] + #[inline(always)] + pub fn usrrdy1(&self) -> USRRDY1_R { + USRRDY1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel 2 User Ready"] + #[inline(always)] + pub fn usrrdy2(&self) -> USRRDY2_R { + USRRDY2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Channel 3 User Ready"] + #[inline(always)] + pub fn usrrdy3(&self) -> USRRDY3_R { + USRRDY3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Channel 4 User Ready"] + #[inline(always)] + pub fn usrrdy4(&self) -> USRRDY4_R { + USRRDY4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Channel 5 User Ready"] + #[inline(always)] + pub fn usrrdy5(&self) -> USRRDY5_R { + USRRDY5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 16 - Channel 0 Busy"] + #[inline(always)] + pub fn chbusy0(&self) -> CHBUSY0_R { + CHBUSY0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Channel 1 Busy"] + #[inline(always)] + pub fn chbusy1(&self) -> CHBUSY1_R { + CHBUSY1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Channel 2 Busy"] + #[inline(always)] + pub fn chbusy2(&self) -> CHBUSY2_R { + CHBUSY2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Channel 3 Busy"] + #[inline(always)] + pub fn chbusy3(&self) -> CHBUSY3_R { + CHBUSY3_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Channel 4 Busy"] + #[inline(always)] + pub fn chbusy4(&self) -> CHBUSY4_R { + CHBUSY4_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Channel 5 Busy"] + #[inline(always)] + pub fn chbusy5(&self) -> CHBUSY5_R { + CHBUSY5_R::new(((self.bits >> 21) & 0x01) != 0) + } +} +#[doc = "Channel Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chstatus](index.html) module"] +pub struct CHSTATUS_SPEC; +impl crate::RegisterSpec for CHSTATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [chstatus::R](R) reader structure"] +impl crate::Readable for CHSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CHSTATUS to value 0"] +impl crate::Resettable for CHSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/evsys/ctrla.rs b/pac/atsamc20j/src/evsys/ctrla.rs new file mode 100644 index 000000000000..1c24704395ad --- /dev/null +++ b/pac/atsamc20j/src/evsys/ctrla.rs @@ -0,0 +1,113 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/evsys/intenclr.rs b/pac/atsamc20j/src/evsys/intenclr.rs new file mode 100644 index 000000000000..60271a5e2e70 --- /dev/null +++ b/pac/atsamc20j/src/evsys/intenclr.rs @@ -0,0 +1,630 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVR0` reader - Channel 0 Overrun Interrupt Enable"] +pub struct OVR0_R(crate::FieldReader); +impl OVR0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR0` writer - Channel 0 Overrun Interrupt Enable"] +pub struct OVR0_W<'a> { + w: &'a mut W, +} +impl<'a> OVR0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `OVR1` reader - Channel 1 Overrun Interrupt Enable"] +pub struct OVR1_R(crate::FieldReader); +impl OVR1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR1` writer - Channel 1 Overrun Interrupt Enable"] +pub struct OVR1_W<'a> { + w: &'a mut W, +} +impl<'a> OVR1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `OVR2` reader - Channel 2 Overrun Interrupt Enable"] +pub struct OVR2_R(crate::FieldReader); +impl OVR2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR2` writer - Channel 2 Overrun Interrupt Enable"] +pub struct OVR2_W<'a> { + w: &'a mut W, +} +impl<'a> OVR2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `OVR3` reader - Channel 3 Overrun Interrupt Enable"] +pub struct OVR3_R(crate::FieldReader); +impl OVR3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR3` writer - Channel 3 Overrun Interrupt Enable"] +pub struct OVR3_W<'a> { + w: &'a mut W, +} +impl<'a> OVR3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `OVR4` reader - Channel 4 Overrun Interrupt Enable"] +pub struct OVR4_R(crate::FieldReader); +impl OVR4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR4` writer - Channel 4 Overrun Interrupt Enable"] +pub struct OVR4_W<'a> { + w: &'a mut W, +} +impl<'a> OVR4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `OVR5` reader - Channel 5 Overrun Interrupt Enable"] +pub struct OVR5_R(crate::FieldReader); +impl OVR5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR5` writer - Channel 5 Overrun Interrupt Enable"] +pub struct OVR5_W<'a> { + w: &'a mut W, +} +impl<'a> OVR5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `EVD0` reader - Channel 0 Event Detection Interrupt Enable"] +pub struct EVD0_R(crate::FieldReader); +impl EVD0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD0` writer - Channel 0 Event Detection Interrupt Enable"] +pub struct EVD0_W<'a> { + w: &'a mut W, +} +impl<'a> EVD0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `EVD1` reader - Channel 1 Event Detection Interrupt Enable"] +pub struct EVD1_R(crate::FieldReader); +impl EVD1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD1` writer - Channel 1 Event Detection Interrupt Enable"] +pub struct EVD1_W<'a> { + w: &'a mut W, +} +impl<'a> EVD1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `EVD2` reader - Channel 2 Event Detection Interrupt Enable"] +pub struct EVD2_R(crate::FieldReader); +impl EVD2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD2` writer - Channel 2 Event Detection Interrupt Enable"] +pub struct EVD2_W<'a> { + w: &'a mut W, +} +impl<'a> EVD2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `EVD3` reader - Channel 3 Event Detection Interrupt Enable"] +pub struct EVD3_R(crate::FieldReader); +impl EVD3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD3` writer - Channel 3 Event Detection Interrupt Enable"] +pub struct EVD3_W<'a> { + w: &'a mut W, +} +impl<'a> EVD3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `EVD4` reader - Channel 4 Event Detection Interrupt Enable"] +pub struct EVD4_R(crate::FieldReader); +impl EVD4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD4` writer - Channel 4 Event Detection Interrupt Enable"] +pub struct EVD4_W<'a> { + w: &'a mut W, +} +impl<'a> EVD4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `EVD5` reader - Channel 5 Event Detection Interrupt Enable"] +pub struct EVD5_R(crate::FieldReader); +impl EVD5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD5` writer - Channel 5 Event Detection Interrupt Enable"] +pub struct EVD5_W<'a> { + w: &'a mut W, +} +impl<'a> EVD5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +impl R { + #[doc = "Bit 0 - Channel 0 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr0(&self) -> OVR0_R { + OVR0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel 1 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr1(&self) -> OVR1_R { + OVR1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel 2 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr2(&self) -> OVR2_R { + OVR2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Channel 3 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr3(&self) -> OVR3_R { + OVR3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Channel 4 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr4(&self) -> OVR4_R { + OVR4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Channel 5 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr5(&self) -> OVR5_R { + OVR5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 16 - Channel 0 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd0(&self) -> EVD0_R { + EVD0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Channel 1 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd1(&self) -> EVD1_R { + EVD1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Channel 2 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd2(&self) -> EVD2_R { + EVD2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Channel 3 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd3(&self) -> EVD3_R { + EVD3_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Channel 4 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd4(&self) -> EVD4_R { + EVD4_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Channel 5 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd5(&self) -> EVD5_R { + EVD5_R::new(((self.bits >> 21) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel 0 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr0(&mut self) -> OVR0_W { + OVR0_W { w: self } + } + #[doc = "Bit 1 - Channel 1 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr1(&mut self) -> OVR1_W { + OVR1_W { w: self } + } + #[doc = "Bit 2 - Channel 2 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr2(&mut self) -> OVR2_W { + OVR2_W { w: self } + } + #[doc = "Bit 3 - Channel 3 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr3(&mut self) -> OVR3_W { + OVR3_W { w: self } + } + #[doc = "Bit 4 - Channel 4 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr4(&mut self) -> OVR4_W { + OVR4_W { w: self } + } + #[doc = "Bit 5 - Channel 5 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr5(&mut self) -> OVR5_W { + OVR5_W { w: self } + } + #[doc = "Bit 16 - Channel 0 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd0(&mut self) -> EVD0_W { + EVD0_W { w: self } + } + #[doc = "Bit 17 - Channel 1 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd1(&mut self) -> EVD1_W { + EVD1_W { w: self } + } + #[doc = "Bit 18 - Channel 2 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd2(&mut self) -> EVD2_W { + EVD2_W { w: self } + } + #[doc = "Bit 19 - Channel 3 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd3(&mut self) -> EVD3_W { + EVD3_W { w: self } + } + #[doc = "Bit 20 - Channel 4 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd4(&mut self) -> EVD4_W { + EVD4_W { w: self } + } + #[doc = "Bit 21 - Channel 5 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd5(&mut self) -> EVD5_W { + EVD5_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/evsys/intenset.rs b/pac/atsamc20j/src/evsys/intenset.rs new file mode 100644 index 000000000000..974030ec7350 --- /dev/null +++ b/pac/atsamc20j/src/evsys/intenset.rs @@ -0,0 +1,630 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVR0` reader - Channel 0 Overrun Interrupt Enable"] +pub struct OVR0_R(crate::FieldReader); +impl OVR0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR0` writer - Channel 0 Overrun Interrupt Enable"] +pub struct OVR0_W<'a> { + w: &'a mut W, +} +impl<'a> OVR0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `OVR1` reader - Channel 1 Overrun Interrupt Enable"] +pub struct OVR1_R(crate::FieldReader); +impl OVR1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR1` writer - Channel 1 Overrun Interrupt Enable"] +pub struct OVR1_W<'a> { + w: &'a mut W, +} +impl<'a> OVR1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `OVR2` reader - Channel 2 Overrun Interrupt Enable"] +pub struct OVR2_R(crate::FieldReader); +impl OVR2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR2` writer - Channel 2 Overrun Interrupt Enable"] +pub struct OVR2_W<'a> { + w: &'a mut W, +} +impl<'a> OVR2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `OVR3` reader - Channel 3 Overrun Interrupt Enable"] +pub struct OVR3_R(crate::FieldReader); +impl OVR3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR3` writer - Channel 3 Overrun Interrupt Enable"] +pub struct OVR3_W<'a> { + w: &'a mut W, +} +impl<'a> OVR3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `OVR4` reader - Channel 4 Overrun Interrupt Enable"] +pub struct OVR4_R(crate::FieldReader); +impl OVR4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR4` writer - Channel 4 Overrun Interrupt Enable"] +pub struct OVR4_W<'a> { + w: &'a mut W, +} +impl<'a> OVR4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `OVR5` reader - Channel 5 Overrun Interrupt Enable"] +pub struct OVR5_R(crate::FieldReader); +impl OVR5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR5` writer - Channel 5 Overrun Interrupt Enable"] +pub struct OVR5_W<'a> { + w: &'a mut W, +} +impl<'a> OVR5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `EVD0` reader - Channel 0 Event Detection Interrupt Enable"] +pub struct EVD0_R(crate::FieldReader); +impl EVD0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD0` writer - Channel 0 Event Detection Interrupt Enable"] +pub struct EVD0_W<'a> { + w: &'a mut W, +} +impl<'a> EVD0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `EVD1` reader - Channel 1 Event Detection Interrupt Enable"] +pub struct EVD1_R(crate::FieldReader); +impl EVD1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD1` writer - Channel 1 Event Detection Interrupt Enable"] +pub struct EVD1_W<'a> { + w: &'a mut W, +} +impl<'a> EVD1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `EVD2` reader - Channel 2 Event Detection Interrupt Enable"] +pub struct EVD2_R(crate::FieldReader); +impl EVD2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD2` writer - Channel 2 Event Detection Interrupt Enable"] +pub struct EVD2_W<'a> { + w: &'a mut W, +} +impl<'a> EVD2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `EVD3` reader - Channel 3 Event Detection Interrupt Enable"] +pub struct EVD3_R(crate::FieldReader); +impl EVD3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD3` writer - Channel 3 Event Detection Interrupt Enable"] +pub struct EVD3_W<'a> { + w: &'a mut W, +} +impl<'a> EVD3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `EVD4` reader - Channel 4 Event Detection Interrupt Enable"] +pub struct EVD4_R(crate::FieldReader); +impl EVD4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD4` writer - Channel 4 Event Detection Interrupt Enable"] +pub struct EVD4_W<'a> { + w: &'a mut W, +} +impl<'a> EVD4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `EVD5` reader - Channel 5 Event Detection Interrupt Enable"] +pub struct EVD5_R(crate::FieldReader); +impl EVD5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD5` writer - Channel 5 Event Detection Interrupt Enable"] +pub struct EVD5_W<'a> { + w: &'a mut W, +} +impl<'a> EVD5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +impl R { + #[doc = "Bit 0 - Channel 0 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr0(&self) -> OVR0_R { + OVR0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel 1 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr1(&self) -> OVR1_R { + OVR1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel 2 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr2(&self) -> OVR2_R { + OVR2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Channel 3 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr3(&self) -> OVR3_R { + OVR3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Channel 4 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr4(&self) -> OVR4_R { + OVR4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Channel 5 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr5(&self) -> OVR5_R { + OVR5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 16 - Channel 0 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd0(&self) -> EVD0_R { + EVD0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Channel 1 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd1(&self) -> EVD1_R { + EVD1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Channel 2 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd2(&self) -> EVD2_R { + EVD2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Channel 3 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd3(&self) -> EVD3_R { + EVD3_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Channel 4 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd4(&self) -> EVD4_R { + EVD4_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Channel 5 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd5(&self) -> EVD5_R { + EVD5_R::new(((self.bits >> 21) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel 0 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr0(&mut self) -> OVR0_W { + OVR0_W { w: self } + } + #[doc = "Bit 1 - Channel 1 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr1(&mut self) -> OVR1_W { + OVR1_W { w: self } + } + #[doc = "Bit 2 - Channel 2 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr2(&mut self) -> OVR2_W { + OVR2_W { w: self } + } + #[doc = "Bit 3 - Channel 3 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr3(&mut self) -> OVR3_W { + OVR3_W { w: self } + } + #[doc = "Bit 4 - Channel 4 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr4(&mut self) -> OVR4_W { + OVR4_W { w: self } + } + #[doc = "Bit 5 - Channel 5 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr5(&mut self) -> OVR5_W { + OVR5_W { w: self } + } + #[doc = "Bit 16 - Channel 0 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd0(&mut self) -> EVD0_W { + EVD0_W { w: self } + } + #[doc = "Bit 17 - Channel 1 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd1(&mut self) -> EVD1_W { + EVD1_W { w: self } + } + #[doc = "Bit 18 - Channel 2 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd2(&mut self) -> EVD2_W { + EVD2_W { w: self } + } + #[doc = "Bit 19 - Channel 3 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd3(&mut self) -> EVD3_W { + EVD3_W { w: self } + } + #[doc = "Bit 20 - Channel 4 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd4(&mut self) -> EVD4_W { + EVD4_W { w: self } + } + #[doc = "Bit 21 - Channel 5 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd5(&mut self) -> EVD5_W { + EVD5_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/evsys/intflag.rs b/pac/atsamc20j/src/evsys/intflag.rs new file mode 100644 index 000000000000..fa72ee78a84f --- /dev/null +++ b/pac/atsamc20j/src/evsys/intflag.rs @@ -0,0 +1,630 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVR0` reader - Channel 0 Overrun"] +pub struct OVR0_R(crate::FieldReader); +impl OVR0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR0` writer - Channel 0 Overrun"] +pub struct OVR0_W<'a> { + w: &'a mut W, +} +impl<'a> OVR0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `OVR1` reader - Channel 1 Overrun"] +pub struct OVR1_R(crate::FieldReader); +impl OVR1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR1` writer - Channel 1 Overrun"] +pub struct OVR1_W<'a> { + w: &'a mut W, +} +impl<'a> OVR1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `OVR2` reader - Channel 2 Overrun"] +pub struct OVR2_R(crate::FieldReader); +impl OVR2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR2` writer - Channel 2 Overrun"] +pub struct OVR2_W<'a> { + w: &'a mut W, +} +impl<'a> OVR2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `OVR3` reader - Channel 3 Overrun"] +pub struct OVR3_R(crate::FieldReader); +impl OVR3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR3` writer - Channel 3 Overrun"] +pub struct OVR3_W<'a> { + w: &'a mut W, +} +impl<'a> OVR3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `OVR4` reader - Channel 4 Overrun"] +pub struct OVR4_R(crate::FieldReader); +impl OVR4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR4` writer - Channel 4 Overrun"] +pub struct OVR4_W<'a> { + w: &'a mut W, +} +impl<'a> OVR4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `OVR5` reader - Channel 5 Overrun"] +pub struct OVR5_R(crate::FieldReader); +impl OVR5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR5` writer - Channel 5 Overrun"] +pub struct OVR5_W<'a> { + w: &'a mut W, +} +impl<'a> OVR5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `EVD0` reader - Channel 0 Event Detection"] +pub struct EVD0_R(crate::FieldReader); +impl EVD0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD0` writer - Channel 0 Event Detection"] +pub struct EVD0_W<'a> { + w: &'a mut W, +} +impl<'a> EVD0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `EVD1` reader - Channel 1 Event Detection"] +pub struct EVD1_R(crate::FieldReader); +impl EVD1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD1` writer - Channel 1 Event Detection"] +pub struct EVD1_W<'a> { + w: &'a mut W, +} +impl<'a> EVD1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `EVD2` reader - Channel 2 Event Detection"] +pub struct EVD2_R(crate::FieldReader); +impl EVD2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD2` writer - Channel 2 Event Detection"] +pub struct EVD2_W<'a> { + w: &'a mut W, +} +impl<'a> EVD2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `EVD3` reader - Channel 3 Event Detection"] +pub struct EVD3_R(crate::FieldReader); +impl EVD3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD3` writer - Channel 3 Event Detection"] +pub struct EVD3_W<'a> { + w: &'a mut W, +} +impl<'a> EVD3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `EVD4` reader - Channel 4 Event Detection"] +pub struct EVD4_R(crate::FieldReader); +impl EVD4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD4` writer - Channel 4 Event Detection"] +pub struct EVD4_W<'a> { + w: &'a mut W, +} +impl<'a> EVD4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `EVD5` reader - Channel 5 Event Detection"] +pub struct EVD5_R(crate::FieldReader); +impl EVD5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD5` writer - Channel 5 Event Detection"] +pub struct EVD5_W<'a> { + w: &'a mut W, +} +impl<'a> EVD5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +impl R { + #[doc = "Bit 0 - Channel 0 Overrun"] + #[inline(always)] + pub fn ovr0(&self) -> OVR0_R { + OVR0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel 1 Overrun"] + #[inline(always)] + pub fn ovr1(&self) -> OVR1_R { + OVR1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel 2 Overrun"] + #[inline(always)] + pub fn ovr2(&self) -> OVR2_R { + OVR2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Channel 3 Overrun"] + #[inline(always)] + pub fn ovr3(&self) -> OVR3_R { + OVR3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Channel 4 Overrun"] + #[inline(always)] + pub fn ovr4(&self) -> OVR4_R { + OVR4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Channel 5 Overrun"] + #[inline(always)] + pub fn ovr5(&self) -> OVR5_R { + OVR5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 16 - Channel 0 Event Detection"] + #[inline(always)] + pub fn evd0(&self) -> EVD0_R { + EVD0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Channel 1 Event Detection"] + #[inline(always)] + pub fn evd1(&self) -> EVD1_R { + EVD1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Channel 2 Event Detection"] + #[inline(always)] + pub fn evd2(&self) -> EVD2_R { + EVD2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Channel 3 Event Detection"] + #[inline(always)] + pub fn evd3(&self) -> EVD3_R { + EVD3_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Channel 4 Event Detection"] + #[inline(always)] + pub fn evd4(&self) -> EVD4_R { + EVD4_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Channel 5 Event Detection"] + #[inline(always)] + pub fn evd5(&self) -> EVD5_R { + EVD5_R::new(((self.bits >> 21) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel 0 Overrun"] + #[inline(always)] + pub fn ovr0(&mut self) -> OVR0_W { + OVR0_W { w: self } + } + #[doc = "Bit 1 - Channel 1 Overrun"] + #[inline(always)] + pub fn ovr1(&mut self) -> OVR1_W { + OVR1_W { w: self } + } + #[doc = "Bit 2 - Channel 2 Overrun"] + #[inline(always)] + pub fn ovr2(&mut self) -> OVR2_W { + OVR2_W { w: self } + } + #[doc = "Bit 3 - Channel 3 Overrun"] + #[inline(always)] + pub fn ovr3(&mut self) -> OVR3_W { + OVR3_W { w: self } + } + #[doc = "Bit 4 - Channel 4 Overrun"] + #[inline(always)] + pub fn ovr4(&mut self) -> OVR4_W { + OVR4_W { w: self } + } + #[doc = "Bit 5 - Channel 5 Overrun"] + #[inline(always)] + pub fn ovr5(&mut self) -> OVR5_W { + OVR5_W { w: self } + } + #[doc = "Bit 16 - Channel 0 Event Detection"] + #[inline(always)] + pub fn evd0(&mut self) -> EVD0_W { + EVD0_W { w: self } + } + #[doc = "Bit 17 - Channel 1 Event Detection"] + #[inline(always)] + pub fn evd1(&mut self) -> EVD1_W { + EVD1_W { w: self } + } + #[doc = "Bit 18 - Channel 2 Event Detection"] + #[inline(always)] + pub fn evd2(&mut self) -> EVD2_W { + EVD2_W { w: self } + } + #[doc = "Bit 19 - Channel 3 Event Detection"] + #[inline(always)] + pub fn evd3(&mut self) -> EVD3_W { + EVD3_W { w: self } + } + #[doc = "Bit 20 - Channel 4 Event Detection"] + #[inline(always)] + pub fn evd4(&mut self) -> EVD4_W { + EVD4_W { w: self } + } + #[doc = "Bit 21 - Channel 5 Event Detection"] + #[inline(always)] + pub fn evd5(&mut self) -> EVD5_W { + EVD5_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/evsys/swevt.rs b/pac/atsamc20j/src/evsys/swevt.rs new file mode 100644 index 000000000000..ba358dc12664 --- /dev/null +++ b/pac/atsamc20j/src/evsys/swevt.rs @@ -0,0 +1,207 @@ +#[doc = "Register `SWEVT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHANNEL0` writer - Channel 0 Software Selection"] +pub struct CHANNEL0_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `CHANNEL1` writer - Channel 1 Software Selection"] +pub struct CHANNEL1_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CHANNEL2` writer - Channel 2 Software Selection"] +pub struct CHANNEL2_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CHANNEL3` writer - Channel 3 Software Selection"] +pub struct CHANNEL3_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CHANNEL4` writer - Channel 4 Software Selection"] +pub struct CHANNEL4_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `CHANNEL5` writer - Channel 5 Software Selection"] +pub struct CHANNEL5_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +impl W { + #[doc = "Bit 0 - Channel 0 Software Selection"] + #[inline(always)] + pub fn channel0(&mut self) -> CHANNEL0_W { + CHANNEL0_W { w: self } + } + #[doc = "Bit 1 - Channel 1 Software Selection"] + #[inline(always)] + pub fn channel1(&mut self) -> CHANNEL1_W { + CHANNEL1_W { w: self } + } + #[doc = "Bit 2 - Channel 2 Software Selection"] + #[inline(always)] + pub fn channel2(&mut self) -> CHANNEL2_W { + CHANNEL2_W { w: self } + } + #[doc = "Bit 3 - Channel 3 Software Selection"] + #[inline(always)] + pub fn channel3(&mut self) -> CHANNEL3_W { + CHANNEL3_W { w: self } + } + #[doc = "Bit 4 - Channel 4 Software Selection"] + #[inline(always)] + pub fn channel4(&mut self) -> CHANNEL4_W { + CHANNEL4_W { w: self } + } + #[doc = "Bit 5 - Channel 5 Software Selection"] + #[inline(always)] + pub fn channel5(&mut self) -> CHANNEL5_W { + CHANNEL5_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Software Event\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [swevt](index.html) module"] +pub struct SWEVT_SPEC; +impl crate::RegisterSpec for SWEVT_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [swevt::W](W) writer structure"] +impl crate::Writable for SWEVT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SWEVT to value 0"] +impl crate::Resettable for SWEVT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/evsys/user.rs b/pac/atsamc20j/src/evsys/user.rs new file mode 100644 index 000000000000..efc20862bfe8 --- /dev/null +++ b/pac/atsamc20j/src/evsys/user.rs @@ -0,0 +1,104 @@ +#[doc = "Register `USER[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `USER[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHANNEL` reader - Channel Event Selection"] +pub struct CHANNEL_R(crate::FieldReader); +impl CHANNEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CHANNEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHANNEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHANNEL` writer - Channel Event Selection"] +pub struct CHANNEL_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Channel Event Selection"] + #[inline(always)] + pub fn channel(&self) -> CHANNEL_R { + CHANNEL_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Channel Event Selection"] + #[inline(always)] + pub fn channel(&mut self) -> CHANNEL_W { + CHANNEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "User Multiplexer n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [user](index.html) module"] +pub struct USER_SPEC; +impl crate::RegisterSpec for USER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [user::R](R) reader structure"] +impl crate::Readable for USER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [user::W](W) writer structure"] +impl crate::Writable for USER_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets USER[%s] +to value 0"] +impl crate::Resettable for USER_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/freqm.rs b/pac/atsamc20j/src/freqm.rs new file mode 100644 index 000000000000..f0fc6fda975e --- /dev/null +++ b/pac/atsamc20j/src/freqm.rs @@ -0,0 +1,59 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control A Register"] + pub ctrla: crate::Reg, + #[doc = "0x01 - Control B Register"] + pub ctrlb: crate::Reg, + #[doc = "0x02 - Config A register"] + pub cfga: crate::Reg, + _reserved3: [u8; 0x04], + #[doc = "0x08 - Interrupt Enable Clear Register"] + pub intenclr: crate::Reg, + #[doc = "0x09 - Interrupt Enable Set Register"] + pub intenset: crate::Reg, + #[doc = "0x0a - Interrupt Flag Register"] + pub intflag: crate::Reg, + #[doc = "0x0b - Status Register"] + pub status: crate::Reg, + #[doc = "0x0c - Synchronization Busy Register"] + pub syncbusy: crate::Reg, + #[doc = "0x10 - Count Value Register"] + pub value: crate::Reg, +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A Register"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "Control B Register"] +pub mod ctrlb; +#[doc = "CFGA register accessor: an alias for `Reg`"] +pub type CFGA = crate::Reg; +#[doc = "Config A register"] +pub mod cfga; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear Register"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set Register"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Register"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status Register"] +pub mod status; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Busy Register"] +pub mod syncbusy; +#[doc = "VALUE register accessor: an alias for `Reg`"] +pub type VALUE = crate::Reg; +#[doc = "Count Value Register"] +pub mod value; diff --git a/pac/atsamc20j/src/freqm/cfga.rs b/pac/atsamc20j/src/freqm/cfga.rs new file mode 100644 index 000000000000..573c62964185 --- /dev/null +++ b/pac/atsamc20j/src/freqm/cfga.rs @@ -0,0 +1,103 @@ +#[doc = "Register `CFGA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CFGA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `REFNUM` reader - Number of Reference Clock Cycles"] +pub struct REFNUM_R(crate::FieldReader); +impl REFNUM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REFNUM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REFNUM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REFNUM` writer - Number of Reference Clock Cycles"] +pub struct REFNUM_W<'a> { + w: &'a mut W, +} +impl<'a> REFNUM_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u16 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Number of Reference Clock Cycles"] + #[inline(always)] + pub fn refnum(&self) -> REFNUM_R { + REFNUM_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Number of Reference Clock Cycles"] + #[inline(always)] + pub fn refnum(&mut self) -> REFNUM_W { + REFNUM_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Config A register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cfga](index.html) module"] +pub struct CFGA_SPEC; +impl crate::RegisterSpec for CFGA_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [cfga::R](R) reader structure"] +impl crate::Readable for CFGA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cfga::W](W) writer structure"] +impl crate::Writable for CFGA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CFGA to value 0"] +impl crate::Resettable for CFGA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/freqm/ctrla.rs b/pac/atsamc20j/src/freqm/ctrla.rs new file mode 100644 index 000000000000..b2cefdd45770 --- /dev/null +++ b/pac/atsamc20j/src/freqm/ctrla.rs @@ -0,0 +1,160 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/freqm/ctrlb.rs b/pac/atsamc20j/src/freqm/ctrlb.rs new file mode 100644 index 000000000000..7d350e71fbf3 --- /dev/null +++ b/pac/atsamc20j/src/freqm/ctrlb.rs @@ -0,0 +1,72 @@ +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `START` writer - Start Measurement"] +pub struct START_W<'a> { + w: &'a mut W, +} +impl<'a> START_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0 - Start Measurement"] + #[inline(always)] + pub fn start(&mut self) -> START_W { + START_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u8; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/freqm/intenclr.rs b/pac/atsamc20j/src/freqm/intenclr.rs new file mode 100644 index 000000000000..a224aa5500f6 --- /dev/null +++ b/pac/atsamc20j/src/freqm/intenclr.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DONE` reader - Measurement Done Interrupt Enable"] +pub struct DONE_R(crate::FieldReader); +impl DONE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DONE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DONE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DONE` writer - Measurement Done Interrupt Enable"] +pub struct DONE_W<'a> { + w: &'a mut W, +} +impl<'a> DONE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Measurement Done Interrupt Enable"] + #[inline(always)] + pub fn done(&self) -> DONE_R { + DONE_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Measurement Done Interrupt Enable"] + #[inline(always)] + pub fn done(&mut self) -> DONE_W { + DONE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/freqm/intenset.rs b/pac/atsamc20j/src/freqm/intenset.rs new file mode 100644 index 000000000000..53b3d0bef7c0 --- /dev/null +++ b/pac/atsamc20j/src/freqm/intenset.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DONE` reader - Measurement Done Interrupt Enable"] +pub struct DONE_R(crate::FieldReader); +impl DONE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DONE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DONE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DONE` writer - Measurement Done Interrupt Enable"] +pub struct DONE_W<'a> { + w: &'a mut W, +} +impl<'a> DONE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Measurement Done Interrupt Enable"] + #[inline(always)] + pub fn done(&self) -> DONE_R { + DONE_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Measurement Done Interrupt Enable"] + #[inline(always)] + pub fn done(&mut self) -> DONE_W { + DONE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/freqm/intflag.rs b/pac/atsamc20j/src/freqm/intflag.rs new file mode 100644 index 000000000000..3b8fdab47703 --- /dev/null +++ b/pac/atsamc20j/src/freqm/intflag.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DONE` reader - Measurement Done"] +pub struct DONE_R(crate::FieldReader); +impl DONE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DONE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DONE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DONE` writer - Measurement Done"] +pub struct DONE_W<'a> { + w: &'a mut W, +} +impl<'a> DONE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Measurement Done"] + #[inline(always)] + pub fn done(&self) -> DONE_R { + DONE_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Measurement Done"] + #[inline(always)] + pub fn done(&mut self) -> DONE_W { + DONE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/freqm/status.rs b/pac/atsamc20j/src/freqm/status.rs new file mode 100644 index 000000000000..8a81662f51b0 --- /dev/null +++ b/pac/atsamc20j/src/freqm/status.rs @@ -0,0 +1,160 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BUSY` reader - FREQM Status"] +pub struct BUSY_R(crate::FieldReader); +impl BUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSY` writer - FREQM Status"] +pub struct BUSY_W<'a> { + w: &'a mut W, +} +impl<'a> BUSY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `OVF` reader - Sticky Count Value Overflow"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Sticky Count Value Overflow"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - FREQM Status"] + #[inline(always)] + pub fn busy(&self) -> BUSY_R { + BUSY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Sticky Count Value Overflow"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - FREQM Status"] + #[inline(always)] + pub fn busy(&mut self) -> BUSY_W { + BUSY_W { w: self } + } + #[doc = "Bit 1 - Sticky Count Value Overflow"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/freqm/syncbusy.rs b/pac/atsamc20j/src/freqm/syncbusy.rs new file mode 100644 index 000000000000..54396368e817 --- /dev/null +++ b/pac/atsamc20j/src/freqm/syncbusy.rs @@ -0,0 +1,73 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +#[doc = "Synchronization Busy Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/freqm/value.rs b/pac/atsamc20j/src/freqm/value.rs new file mode 100644 index 000000000000..5b0f5dfd9b67 --- /dev/null +++ b/pac/atsamc20j/src/freqm/value.rs @@ -0,0 +1,53 @@ +#[doc = "Register `VALUE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `VALUE` reader - Measurement Value"] +pub struct VALUE_R(crate::FieldReader); +impl VALUE_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + VALUE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VALUE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:23 - Measurement Value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +#[doc = "Count Value Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [value](index.html) module"] +pub struct VALUE_SPEC; +impl crate::RegisterSpec for VALUE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [value::R](R) reader structure"] +impl crate::Readable for VALUE_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets VALUE to value 0"] +impl crate::Resettable for VALUE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/gclk.rs b/pac/atsamc20j/src/gclk.rs new file mode 100644 index 000000000000..2a37bdedcab3 --- /dev/null +++ b/pac/atsamc20j/src/gclk.rs @@ -0,0 +1,31 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrla: crate::Reg, + _reserved1: [u8; 0x03], + #[doc = "0x04 - Synchronization Busy"] + pub syncbusy: crate::Reg, + _reserved2: [u8; 0x18], + #[doc = "0x20..0x44 - Generic Clock Generator Control"] + pub genctrl: [crate::Reg; 9], + _reserved3: [u8; 0x3c], + #[doc = "0x80..0x124 - Peripheral Clock Control"] + pub pchctrl: [crate::Reg; 41], +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control"] +pub mod ctrla; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Busy"] +pub mod syncbusy; +#[doc = "GENCTRL register accessor: an alias for `Reg`"] +pub type GENCTRL = crate::Reg; +#[doc = "Generic Clock Generator Control"] +pub mod genctrl; +#[doc = "PCHCTRL register accessor: an alias for `Reg`"] +pub type PCHCTRL = crate::Reg; +#[doc = "Peripheral Clock Control"] +pub mod pchctrl; diff --git a/pac/atsamc20j/src/gclk/ctrla.rs b/pac/atsamc20j/src/gclk/ctrla.rs new file mode 100644 index 000000000000..1c24704395ad --- /dev/null +++ b/pac/atsamc20j/src/gclk/ctrla.rs @@ -0,0 +1,113 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/gclk/genctrl.rs b/pac/atsamc20j/src/gclk/genctrl.rs new file mode 100644 index 000000000000..052b2915ca7f --- /dev/null +++ b/pac/atsamc20j/src/gclk/genctrl.rs @@ -0,0 +1,597 @@ +#[doc = "Register `GENCTRL[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GENCTRL[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Source Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SRC_A { + #[doc = "0: XOSC oscillator output"] + XOSC = 0, + #[doc = "1: Generator input pad"] + GCLKIN = 1, + #[doc = "2: Generic clock generator 1 output"] + GCLKGEN1 = 2, + #[doc = "3: OSCULP32K oscillator output"] + OSCULP32K = 3, + #[doc = "4: OSC32K oscillator output"] + OSC32K = 4, + #[doc = "5: XOSC32K oscillator output"] + XOSC32K = 5, + #[doc = "6: OSC48M oscillator output"] + OSC48M = 6, + #[doc = "7: DPLL96M output"] + DPLL96M = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SRC_A) -> Self { + variant as _ + } +} +#[doc = "Field `SRC` reader - Source Select"] +pub struct SRC_R(crate::FieldReader); +impl SRC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SRC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SRC_A { + match self.bits { + 0 => SRC_A::XOSC, + 1 => SRC_A::GCLKIN, + 2 => SRC_A::GCLKGEN1, + 3 => SRC_A::OSCULP32K, + 4 => SRC_A::OSC32K, + 5 => SRC_A::XOSC32K, + 6 => SRC_A::OSC48M, + 7 => SRC_A::DPLL96M, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `XOSC`"] + #[inline(always)] + pub fn is_xosc(&self) -> bool { + **self == SRC_A::XOSC + } + #[doc = "Checks if the value of the field is `GCLKIN`"] + #[inline(always)] + pub fn is_gclkin(&self) -> bool { + **self == SRC_A::GCLKIN + } + #[doc = "Checks if the value of the field is `GCLKGEN1`"] + #[inline(always)] + pub fn is_gclkgen1(&self) -> bool { + **self == SRC_A::GCLKGEN1 + } + #[doc = "Checks if the value of the field is `OSCULP32K`"] + #[inline(always)] + pub fn is_osculp32k(&self) -> bool { + **self == SRC_A::OSCULP32K + } + #[doc = "Checks if the value of the field is `OSC32K`"] + #[inline(always)] + pub fn is_osc32k(&self) -> bool { + **self == SRC_A::OSC32K + } + #[doc = "Checks if the value of the field is `XOSC32K`"] + #[inline(always)] + pub fn is_xosc32k(&self) -> bool { + **self == SRC_A::XOSC32K + } + #[doc = "Checks if the value of the field is `OSC48M`"] + #[inline(always)] + pub fn is_osc48m(&self) -> bool { + **self == SRC_A::OSC48M + } + #[doc = "Checks if the value of the field is `DPLL96M`"] + #[inline(always)] + pub fn is_dpll96m(&self) -> bool { + **self == SRC_A::DPLL96M + } +} +impl core::ops::Deref for SRC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SRC` writer - Source Select"] +pub struct SRC_W<'a> { + w: &'a mut W, +} +impl<'a> SRC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SRC_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "XOSC oscillator output"] + #[inline(always)] + pub fn xosc(self) -> &'a mut W { + self.variant(SRC_A::XOSC) + } + #[doc = "Generator input pad"] + #[inline(always)] + pub fn gclkin(self) -> &'a mut W { + self.variant(SRC_A::GCLKIN) + } + #[doc = "Generic clock generator 1 output"] + #[inline(always)] + pub fn gclkgen1(self) -> &'a mut W { + self.variant(SRC_A::GCLKGEN1) + } + #[doc = "OSCULP32K oscillator output"] + #[inline(always)] + pub fn osculp32k(self) -> &'a mut W { + self.variant(SRC_A::OSCULP32K) + } + #[doc = "OSC32K oscillator output"] + #[inline(always)] + pub fn osc32k(self) -> &'a mut W { + self.variant(SRC_A::OSC32K) + } + #[doc = "XOSC32K oscillator output"] + #[inline(always)] + pub fn xosc32k(self) -> &'a mut W { + self.variant(SRC_A::XOSC32K) + } + #[doc = "OSC48M oscillator output"] + #[inline(always)] + pub fn osc48m(self) -> &'a mut W { + self.variant(SRC_A::OSC48M) + } + #[doc = "DPLL96M output"] + #[inline(always)] + pub fn dpll96m(self) -> &'a mut W { + self.variant(SRC_A::DPLL96M) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Field `GENEN` reader - Generic Clock Generator Enable"] +pub struct GENEN_R(crate::FieldReader); +impl GENEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENEN` writer - Generic Clock Generator Enable"] +pub struct GENEN_W<'a> { + w: &'a mut W, +} +impl<'a> GENEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `IDC` reader - Improve Duty Cycle"] +pub struct IDC_R(crate::FieldReader); +impl IDC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IDC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IDC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IDC` writer - Improve Duty Cycle"] +pub struct IDC_W<'a> { + w: &'a mut W, +} +impl<'a> IDC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `OOV` reader - Output Off Value"] +pub struct OOV_R(crate::FieldReader); +impl OOV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OOV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OOV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OOV` writer - Output Off Value"] +pub struct OOV_W<'a> { + w: &'a mut W, +} +impl<'a> OOV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `OE` reader - Output Enable"] +pub struct OE_R(crate::FieldReader); +impl OE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OE` writer - Output Enable"] +pub struct OE_W<'a> { + w: &'a mut W, +} +impl<'a> OE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Divide Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum DIVSEL_A { + #[doc = "0: Divide input directly by divider factor"] + DIV1 = 0, + #[doc = "1: Divide input by 2^(divider factor+ 1)"] + DIV2 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DIVSEL_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DIVSEL` reader - Divide Selection"] +pub struct DIVSEL_R(crate::FieldReader); +impl DIVSEL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIVSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DIVSEL_A { + match self.bits { + false => DIVSEL_A::DIV1, + true => DIVSEL_A::DIV2, + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == DIVSEL_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == DIVSEL_A::DIV2 + } +} +impl core::ops::Deref for DIVSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIVSEL` writer - Divide Selection"] +pub struct DIVSEL_W<'a> { + w: &'a mut W, +} +impl<'a> DIVSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DIVSEL_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Divide input directly by divider factor"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(DIVSEL_A::DIV1) + } + #[doc = "Divide input by 2^(divider factor+ 1)"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(DIVSEL_A::DIV2) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `DIV` reader - Division Factor"] +pub struct DIV_R(crate::FieldReader); +impl DIV_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + DIV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIV` writer - Division Factor"] +pub struct DIV_W<'a> { + w: &'a mut W, +} +impl<'a> DIV_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xffff << 16)) | ((value as u32 & 0xffff) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Source Select"] + #[inline(always)] + pub fn src(&self) -> SRC_R { + SRC_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 8 - Generic Clock Generator Enable"] + #[inline(always)] + pub fn genen(&self) -> GENEN_R { + GENEN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Improve Duty Cycle"] + #[inline(always)] + pub fn idc(&self) -> IDC_R { + IDC_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Output Off Value"] + #[inline(always)] + pub fn oov(&self) -> OOV_R { + OOV_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Output Enable"] + #[inline(always)] + pub fn oe(&self) -> OE_R { + OE_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Divide Selection"] + #[inline(always)] + pub fn divsel(&self) -> DIVSEL_R { + DIVSEL_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bits 16:31 - Division Factor"] + #[inline(always)] + pub fn div(&self) -> DIV_R { + DIV_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:2 - Source Select"] + #[inline(always)] + pub fn src(&mut self) -> SRC_W { + SRC_W { w: self } + } + #[doc = "Bit 8 - Generic Clock Generator Enable"] + #[inline(always)] + pub fn genen(&mut self) -> GENEN_W { + GENEN_W { w: self } + } + #[doc = "Bit 9 - Improve Duty Cycle"] + #[inline(always)] + pub fn idc(&mut self) -> IDC_W { + IDC_W { w: self } + } + #[doc = "Bit 10 - Output Off Value"] + #[inline(always)] + pub fn oov(&mut self) -> OOV_W { + OOV_W { w: self } + } + #[doc = "Bit 11 - Output Enable"] + #[inline(always)] + pub fn oe(&mut self) -> OE_W { + OE_W { w: self } + } + #[doc = "Bit 12 - Divide Selection"] + #[inline(always)] + pub fn divsel(&mut self) -> DIVSEL_W { + DIVSEL_W { w: self } + } + #[doc = "Bit 13 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bits 16:31 - Division Factor"] + #[inline(always)] + pub fn div(&mut self) -> DIV_W { + DIV_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Generic Clock Generator Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [genctrl](index.html) module"] +pub struct GENCTRL_SPEC; +impl crate::RegisterSpec for GENCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [genctrl::R](R) reader structure"] +impl crate::Readable for GENCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [genctrl::W](W) writer structure"] +impl crate::Writable for GENCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets GENCTRL[%s] +to value 0"] +impl crate::Resettable for GENCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/gclk/pchctrl.rs b/pac/atsamc20j/src/gclk/pchctrl.rs new file mode 100644 index 000000000000..8001ffeaa1ee --- /dev/null +++ b/pac/atsamc20j/src/gclk/pchctrl.rs @@ -0,0 +1,338 @@ +#[doc = "Register `PCHCTRL[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PCHCTRL[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Generic Clock Generator\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum GEN_A { + #[doc = "0: Generic clock generator 0"] + GCLK0 = 0, + #[doc = "1: Generic clock generator 1"] + GCLK1 = 1, + #[doc = "2: Generic clock generator 2"] + GCLK2 = 2, + #[doc = "3: Generic clock generator 3"] + GCLK3 = 3, + #[doc = "4: Generic clock generator 4"] + GCLK4 = 4, + #[doc = "5: Generic clock generator 5"] + GCLK5 = 5, + #[doc = "6: Generic clock generator 6"] + GCLK6 = 6, + #[doc = "7: Generic clock generator 7"] + GCLK7 = 7, + #[doc = "8: Generic clock generator 8"] + GCLK8 = 8, +} +impl From for u8 { + #[inline(always)] + fn from(variant: GEN_A) -> Self { + variant as _ + } +} +#[doc = "Field `GEN` reader - Generic Clock Generator"] +pub struct GEN_R(crate::FieldReader); +impl GEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + GEN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(GEN_A::GCLK0), + 1 => Some(GEN_A::GCLK1), + 2 => Some(GEN_A::GCLK2), + 3 => Some(GEN_A::GCLK3), + 4 => Some(GEN_A::GCLK4), + 5 => Some(GEN_A::GCLK5), + 6 => Some(GEN_A::GCLK6), + 7 => Some(GEN_A::GCLK7), + 8 => Some(GEN_A::GCLK8), + _ => None, + } + } + #[doc = "Checks if the value of the field is `GCLK0`"] + #[inline(always)] + pub fn is_gclk0(&self) -> bool { + **self == GEN_A::GCLK0 + } + #[doc = "Checks if the value of the field is `GCLK1`"] + #[inline(always)] + pub fn is_gclk1(&self) -> bool { + **self == GEN_A::GCLK1 + } + #[doc = "Checks if the value of the field is `GCLK2`"] + #[inline(always)] + pub fn is_gclk2(&self) -> bool { + **self == GEN_A::GCLK2 + } + #[doc = "Checks if the value of the field is `GCLK3`"] + #[inline(always)] + pub fn is_gclk3(&self) -> bool { + **self == GEN_A::GCLK3 + } + #[doc = "Checks if the value of the field is `GCLK4`"] + #[inline(always)] + pub fn is_gclk4(&self) -> bool { + **self == GEN_A::GCLK4 + } + #[doc = "Checks if the value of the field is `GCLK5`"] + #[inline(always)] + pub fn is_gclk5(&self) -> bool { + **self == GEN_A::GCLK5 + } + #[doc = "Checks if the value of the field is `GCLK6`"] + #[inline(always)] + pub fn is_gclk6(&self) -> bool { + **self == GEN_A::GCLK6 + } + #[doc = "Checks if the value of the field is `GCLK7`"] + #[inline(always)] + pub fn is_gclk7(&self) -> bool { + **self == GEN_A::GCLK7 + } + #[doc = "Checks if the value of the field is `GCLK8`"] + #[inline(always)] + pub fn is_gclk8(&self) -> bool { + **self == GEN_A::GCLK8 + } +} +impl core::ops::Deref for GEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GEN` writer - Generic Clock Generator"] +pub struct GEN_W<'a> { + w: &'a mut W, +} +impl<'a> GEN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: GEN_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Generic clock generator 0"] + #[inline(always)] + pub fn gclk0(self) -> &'a mut W { + self.variant(GEN_A::GCLK0) + } + #[doc = "Generic clock generator 1"] + #[inline(always)] + pub fn gclk1(self) -> &'a mut W { + self.variant(GEN_A::GCLK1) + } + #[doc = "Generic clock generator 2"] + #[inline(always)] + pub fn gclk2(self) -> &'a mut W { + self.variant(GEN_A::GCLK2) + } + #[doc = "Generic clock generator 3"] + #[inline(always)] + pub fn gclk3(self) -> &'a mut W { + self.variant(GEN_A::GCLK3) + } + #[doc = "Generic clock generator 4"] + #[inline(always)] + pub fn gclk4(self) -> &'a mut W { + self.variant(GEN_A::GCLK4) + } + #[doc = "Generic clock generator 5"] + #[inline(always)] + pub fn gclk5(self) -> &'a mut W { + self.variant(GEN_A::GCLK5) + } + #[doc = "Generic clock generator 6"] + #[inline(always)] + pub fn gclk6(self) -> &'a mut W { + self.variant(GEN_A::GCLK6) + } + #[doc = "Generic clock generator 7"] + #[inline(always)] + pub fn gclk7(self) -> &'a mut W { + self.variant(GEN_A::GCLK7) + } + #[doc = "Generic clock generator 8"] + #[inline(always)] + pub fn gclk8(self) -> &'a mut W { + self.variant(GEN_A::GCLK8) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Field `CHEN` reader - Channel Enable"] +pub struct CHEN_R(crate::FieldReader); +impl CHEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHEN` writer - Channel Enable"] +pub struct CHEN_W<'a> { + w: &'a mut W, +} +impl<'a> CHEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `WRTLOCK` reader - Write Lock"] +pub struct WRTLOCK_R(crate::FieldReader); +impl WRTLOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WRTLOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WRTLOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WRTLOCK` writer - Write Lock"] +pub struct WRTLOCK_W<'a> { + w: &'a mut W, +} +impl<'a> WRTLOCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Generic Clock Generator"] + #[inline(always)] + pub fn gen(&self) -> GEN_R { + GEN_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 6 - Channel Enable"] + #[inline(always)] + pub fn chen(&self) -> CHEN_R { + CHEN_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&self) -> WRTLOCK_R { + WRTLOCK_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Generic Clock Generator"] + #[inline(always)] + pub fn gen(&mut self) -> GEN_W { + GEN_W { w: self } + } + #[doc = "Bit 6 - Channel Enable"] + #[inline(always)] + pub fn chen(&mut self) -> CHEN_W { + CHEN_W { w: self } + } + #[doc = "Bit 7 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&mut self) -> WRTLOCK_W { + WRTLOCK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Peripheral Clock Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pchctrl](index.html) module"] +pub struct PCHCTRL_SPEC; +impl crate::RegisterSpec for PCHCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pchctrl::R](R) reader structure"] +impl crate::Readable for PCHCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [pchctrl::W](W) writer structure"] +impl crate::Writable for PCHCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PCHCTRL[%s] +to value 0"] +impl crate::Resettable for PCHCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/gclk/syncbusy.rs b/pac/atsamc20j/src/gclk/syncbusy.rs new file mode 100644 index 000000000000..f21640440354 --- /dev/null +++ b/pac/atsamc20j/src/gclk/syncbusy.rs @@ -0,0 +1,233 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchroniation Busy bit"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENCTRL0` reader - Generic Clock Generator Control 0 Synchronization Busy bits"] +pub struct GENCTRL0_R(crate::FieldReader); +impl GENCTRL0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENCTRL0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENCTRL0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENCTRL1` reader - Generic Clock Generator Control 1 Synchronization Busy bits"] +pub struct GENCTRL1_R(crate::FieldReader); +impl GENCTRL1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENCTRL1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENCTRL1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENCTRL2` reader - Generic Clock Generator Control 2 Synchronization Busy bits"] +pub struct GENCTRL2_R(crate::FieldReader); +impl GENCTRL2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENCTRL2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENCTRL2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENCTRL3` reader - Generic Clock Generator Control 3 Synchronization Busy bits"] +pub struct GENCTRL3_R(crate::FieldReader); +impl GENCTRL3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENCTRL3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENCTRL3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENCTRL4` reader - Generic Clock Generator Control 4 Synchronization Busy bits"] +pub struct GENCTRL4_R(crate::FieldReader); +impl GENCTRL4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENCTRL4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENCTRL4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENCTRL5` reader - Generic Clock Generator Control 5 Synchronization Busy bits"] +pub struct GENCTRL5_R(crate::FieldReader); +impl GENCTRL5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENCTRL5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENCTRL5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENCTRL6` reader - Generic Clock Generator Control 6 Synchronization Busy bits"] +pub struct GENCTRL6_R(crate::FieldReader); +impl GENCTRL6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENCTRL6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENCTRL6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENCTRL7` reader - Generic Clock Generator Control 7 Synchronization Busy bits"] +pub struct GENCTRL7_R(crate::FieldReader); +impl GENCTRL7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENCTRL7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENCTRL7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENCTRL8` reader - Generic Clock Generator Control 8 Synchronization Busy bits"] +pub struct GENCTRL8_R(crate::FieldReader); +impl GENCTRL8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENCTRL8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENCTRL8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchroniation Busy bit"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 2 - Generic Clock Generator Control 0 Synchronization Busy bits"] + #[inline(always)] + pub fn genctrl0(&self) -> GENCTRL0_R { + GENCTRL0_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Generic Clock Generator Control 1 Synchronization Busy bits"] + #[inline(always)] + pub fn genctrl1(&self) -> GENCTRL1_R { + GENCTRL1_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Generic Clock Generator Control 2 Synchronization Busy bits"] + #[inline(always)] + pub fn genctrl2(&self) -> GENCTRL2_R { + GENCTRL2_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Generic Clock Generator Control 3 Synchronization Busy bits"] + #[inline(always)] + pub fn genctrl3(&self) -> GENCTRL3_R { + GENCTRL3_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Generic Clock Generator Control 4 Synchronization Busy bits"] + #[inline(always)] + pub fn genctrl4(&self) -> GENCTRL4_R { + GENCTRL4_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Generic Clock Generator Control 5 Synchronization Busy bits"] + #[inline(always)] + pub fn genctrl5(&self) -> GENCTRL5_R { + GENCTRL5_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Generic Clock Generator Control 6 Synchronization Busy bits"] + #[inline(always)] + pub fn genctrl6(&self) -> GENCTRL6_R { + GENCTRL6_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Generic Clock Generator Control 7 Synchronization Busy bits"] + #[inline(always)] + pub fn genctrl7(&self) -> GENCTRL7_R { + GENCTRL7_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Generic Clock Generator Control 8 Synchronization Busy bits"] + #[inline(always)] + pub fn genctrl8(&self) -> GENCTRL8_R { + GENCTRL8_R::new(((self.bits >> 10) & 0x01) != 0) + } +} +#[doc = "Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/generic.rs b/pac/atsamc20j/src/generic.rs new file mode 100644 index 000000000000..76159643acfa --- /dev/null +++ b/pac/atsamc20j/src/generic.rs @@ -0,0 +1,260 @@ +use core::marker; +#[doc = " Raw register type"] +pub trait RegisterSpec { + #[doc = " Raw register type (`u8`, `u16`, `u32`, ...)."] + type Ux: Copy; +} +#[doc = " Trait implemented by readable registers to enable the `read` method."] +#[doc = ""] +#[doc = " Registers marked with `Writable` can be also `modify`'ed."] +pub trait Readable: RegisterSpec { + #[doc = " Result from a call to `read` and argument to `modify`."] + type Reader: From> + core::ops::Deref>; +} +#[doc = " Trait implemented by writeable registers."] +#[doc = ""] +#[doc = " This enables the `write`, `write_with_zero` and `reset` methods."] +#[doc = ""] +#[doc = " Registers marked with `Readable` can be also `modify`'ed."] +pub trait Writable: RegisterSpec { + #[doc = " Writer type argument to `write`, et al."] + type Writer: From> + core::ops::DerefMut>; +} +#[doc = " Reset value of the register."] +#[doc = ""] +#[doc = " This value is the initial value for the `write` method. It can also be directly written to the"] +#[doc = " register by using the `reset` method."] +pub trait Resettable: RegisterSpec { + #[doc = " Reset value of the register."] + fn reset_value() -> Self::Ux; +} +#[doc = " This structure provides volatile access to registers."] +#[repr(transparent)] +pub struct Reg { + register: vcell::VolatileCell, + _marker: marker::PhantomData, +} +unsafe impl Send for Reg where REG::Ux: Send {} +impl Reg { + #[doc = " Returns the underlying memory address of register."] + #[doc = ""] + #[doc = " ```ignore"] + #[doc = " let reg_ptr = periph.reg.as_ptr();"] + #[doc = " ```"] + #[inline(always)] + pub fn as_ptr(&self) -> *mut REG::Ux { + self.register.as_ptr() + } +} +impl Reg { + #[doc = " Reads the contents of a `Readable` register."] + #[doc = ""] + #[doc = " You can read the raw contents of a register by using `bits`:"] + #[doc = " ```ignore"] + #[doc = " let bits = periph.reg.read().bits();"] + #[doc = " ```"] + #[doc = " or get the content of a particular field of a register:"] + #[doc = " ```ignore"] + #[doc = " let reader = periph.reg.read();"] + #[doc = " let bits = reader.field1().bits();"] + #[doc = " let flag = reader.field2().bit_is_set();"] + #[doc = " ```"] + #[inline(always)] + pub fn read(&self) -> REG::Reader { + REG::Reader::from(R { + bits: self.register.get(), + _reg: marker::PhantomData, + }) + } +} +impl Reg { + #[doc = " Writes the reset value to `Writable` register."] + #[doc = ""] + #[doc = " Resets the register to its initial state."] + #[inline(always)] + pub fn reset(&self) { + self.register.set(REG::reset_value()) + } + #[doc = " Writes bits to a `Writable` register."] + #[doc = ""] + #[doc = " You can write raw bits into a register:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.write(|w| unsafe { w.bits(rawbits) });"] + #[doc = " ```"] + #[doc = " or write only the fields you need:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.write(|w| w"] + #[doc = " .field1().bits(newfield1bits)"] + #[doc = " .field2().set_bit()"] + #[doc = " .field3().variant(VARIANT)"] + #[doc = " );"] + #[doc = " ```"] + #[doc = " In the latter case, other fields will be set to their reset value."] + #[inline(always)] + pub fn write(&self, f: F) + where + F: FnOnce(&mut REG::Writer) -> &mut W, + { + self.register.set( + f(&mut REG::Writer::from(W { + bits: REG::reset_value(), + _reg: marker::PhantomData, + })) + .bits, + ); + } +} +impl Reg +where + REG::Ux: Default, +{ + #[doc = " Writes 0 to a `Writable` register."] + #[doc = ""] + #[doc = " Similar to `write`, but unused bits will contain 0."] + #[inline(always)] + pub unsafe fn write_with_zero(&self, f: F) + where + F: FnOnce(&mut REG::Writer) -> &mut W, + { + self.register.set( + (*f(&mut REG::Writer::from(W { + bits: REG::Ux::default(), + _reg: marker::PhantomData, + }))) + .bits, + ); + } +} +impl Reg { + #[doc = " Modifies the contents of the register by reading and then writing it."] + #[doc = ""] + #[doc = " E.g. to do a read-modify-write sequence to change parts of a register:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.modify(|r, w| unsafe { w.bits("] + #[doc = " r.bits() | 3"] + #[doc = " ) });"] + #[doc = " ```"] + #[doc = " or"] + #[doc = " ```ignore"] + #[doc = " periph.reg.modify(|_, w| w"] + #[doc = " .field1().bits(newfield1bits)"] + #[doc = " .field2().set_bit()"] + #[doc = " .field3().variant(VARIANT)"] + #[doc = " );"] + #[doc = " ```"] + #[doc = " Other fields will have the value they had before the call to `modify`."] + #[inline(always)] + pub fn modify(&self, f: F) + where + for<'w> F: FnOnce(®::Reader, &'w mut REG::Writer) -> &'w mut W, + { + let bits = self.register.get(); + self.register.set( + f( + ®::Reader::from(R { + bits, + _reg: marker::PhantomData, + }), + &mut REG::Writer::from(W { + bits, + _reg: marker::PhantomData, + }), + ) + .bits, + ); + } +} +#[doc = " Register reader."] +#[doc = ""] +#[doc = " Result of the `read` methods of registers. Also used as a closure argument in the `modify`"] +#[doc = " method."] +pub struct R { + pub(crate) bits: REG::Ux, + _reg: marker::PhantomData, +} +impl R { + #[doc = " Reads raw bits from register."] + #[inline(always)] + pub fn bits(&self) -> REG::Ux { + self.bits + } +} +impl PartialEq for R +where + REG::Ux: PartialEq, + FI: Copy + Into, +{ + #[inline(always)] + fn eq(&self, other: &FI) -> bool { + self.bits.eq(&(*other).into()) + } +} +#[doc = " Register writer."] +#[doc = ""] +#[doc = " Used as an argument to the closures in the `write` and `modify` methods of the register."] +pub struct W { + #[doc = "Writable bits"] + pub(crate) bits: REG::Ux, + _reg: marker::PhantomData, +} +impl W { + #[doc = " Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = " Field reader."] +#[doc = ""] +#[doc = " Result of the `read` methods of fields."] +pub struct FieldReader { + pub(crate) bits: U, + _reg: marker::PhantomData, +} +impl FieldReader +where + U: Copy, +{ + #[doc = " Creates a new instance of the reader."] + #[allow(unused)] + #[inline(always)] + pub(crate) fn new(bits: U) -> Self { + Self { + bits, + _reg: marker::PhantomData, + } + } + #[doc = " Reads raw bits from field."] + #[inline(always)] + pub fn bits(&self) -> U { + self.bits + } +} +impl PartialEq for FieldReader +where + U: PartialEq, + FI: Copy + Into, +{ + #[inline(always)] + fn eq(&self, other: &FI) -> bool { + self.bits.eq(&(*other).into()) + } +} +impl FieldReader { + #[doc = " Value of the field as raw bits."] + #[inline(always)] + pub fn bit(&self) -> bool { + self.bits + } + #[doc = " Returns `true` if the bit is clear (0)."] + #[inline(always)] + pub fn bit_is_clear(&self) -> bool { + !self.bit() + } + #[doc = " Returns `true` if the bit is set (1)."] + #[inline(always)] + pub fn bit_is_set(&self) -> bool { + self.bit() + } +} diff --git a/pac/atsamc20j/src/hmatrixhs.rs b/pac/atsamc20j/src/hmatrixhs.rs new file mode 100644 index 000000000000..c8129ac89b6f --- /dev/null +++ b/pac/atsamc20j/src/hmatrixhs.rs @@ -0,0 +1,43 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00..0x40 - Master Configuration"] + pub mcfg: [crate::Reg; 16], + #[doc = "0x40..0x80 - Slave Configuration"] + pub scfg: [crate::Reg; 16], + #[doc = "0x80..0xa0 - PRS\\[%s\\]"] + pub prs: [PRS; 4], + _reserved3: [u8; 0x60], + #[doc = "0x100 - Master Remap Control"] + pub mrcr: crate::Reg, + _reserved4: [u8; 0x0c], + #[doc = "0x110..0x150 - Special Function"] + pub sfr: [crate::Reg; 16], +} +#[doc = r"Register block"] +#[repr(C)] +pub struct PRS { + #[doc = "0x00 - Priority A for Slave"] + pub pras: crate::Reg, + #[doc = "0x04 - Priority B for Slave"] + pub prbs: crate::Reg, +} +#[doc = r"Register block"] +#[doc = "PRS\\[%s\\]"] +pub mod prs; +#[doc = "MCFG register accessor: an alias for `Reg`"] +pub type MCFG = crate::Reg; +#[doc = "Master Configuration"] +pub mod mcfg; +#[doc = "SCFG register accessor: an alias for `Reg`"] +pub type SCFG = crate::Reg; +#[doc = "Slave Configuration"] +pub mod scfg; +#[doc = "MRCR register accessor: an alias for `Reg`"] +pub type MRCR = crate::Reg; +#[doc = "Master Remap Control"] +pub mod mrcr; +#[doc = "SFR register accessor: an alias for `Reg`"] +pub type SFR = crate::Reg; +#[doc = "Special Function"] +pub mod sfr; diff --git a/pac/atsamc20j/src/hmatrixhs/mcfg.rs b/pac/atsamc20j/src/hmatrixhs/mcfg.rs new file mode 100644 index 000000000000..454a39fabe13 --- /dev/null +++ b/pac/atsamc20j/src/hmatrixhs/mcfg.rs @@ -0,0 +1,192 @@ +#[doc = "Register `MCFG[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MCFG[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Undefined Length Burst Type\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum ULBT_A { + #[doc = "0: Infinite Length"] + INFINITE = 0, + #[doc = "1: Single Access"] + SINGLE = 1, + #[doc = "2: Four Beat Burst"] + FOUR_BEAT = 2, + #[doc = "3: Eight Beat Burst"] + EIGHT_BEAT = 3, + #[doc = "4: Sixteen Beat Burst"] + SIXTEEN_BEAT = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: ULBT_A) -> Self { + variant as _ + } +} +#[doc = "Field `ULBT` reader - Undefined Length Burst Type"] +pub struct ULBT_R(crate::FieldReader); +impl ULBT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ULBT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(ULBT_A::INFINITE), + 1 => Some(ULBT_A::SINGLE), + 2 => Some(ULBT_A::FOUR_BEAT), + 3 => Some(ULBT_A::EIGHT_BEAT), + 4 => Some(ULBT_A::SIXTEEN_BEAT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `INFINITE`"] + #[inline(always)] + pub fn is_infinite(&self) -> bool { + **self == ULBT_A::INFINITE + } + #[doc = "Checks if the value of the field is `SINGLE`"] + #[inline(always)] + pub fn is_single(&self) -> bool { + **self == ULBT_A::SINGLE + } + #[doc = "Checks if the value of the field is `FOUR_BEAT`"] + #[inline(always)] + pub fn is_four_beat(&self) -> bool { + **self == ULBT_A::FOUR_BEAT + } + #[doc = "Checks if the value of the field is `EIGHT_BEAT`"] + #[inline(always)] + pub fn is_eight_beat(&self) -> bool { + **self == ULBT_A::EIGHT_BEAT + } + #[doc = "Checks if the value of the field is `SIXTEEN_BEAT`"] + #[inline(always)] + pub fn is_sixteen_beat(&self) -> bool { + **self == ULBT_A::SIXTEEN_BEAT + } +} +impl core::ops::Deref for ULBT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ULBT` writer - Undefined Length Burst Type"] +pub struct ULBT_W<'a> { + w: &'a mut W, +} +impl<'a> ULBT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: ULBT_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Infinite Length"] + #[inline(always)] + pub fn infinite(self) -> &'a mut W { + self.variant(ULBT_A::INFINITE) + } + #[doc = "Single Access"] + #[inline(always)] + pub fn single(self) -> &'a mut W { + self.variant(ULBT_A::SINGLE) + } + #[doc = "Four Beat Burst"] + #[inline(always)] + pub fn four_beat(self) -> &'a mut W { + self.variant(ULBT_A::FOUR_BEAT) + } + #[doc = "Eight Beat Burst"] + #[inline(always)] + pub fn eight_beat(self) -> &'a mut W { + self.variant(ULBT_A::EIGHT_BEAT) + } + #[doc = "Sixteen Beat Burst"] + #[inline(always)] + pub fn sixteen_beat(self) -> &'a mut W { + self.variant(ULBT_A::SIXTEEN_BEAT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Undefined Length Burst Type"] + #[inline(always)] + pub fn ulbt(&self) -> ULBT_R { + ULBT_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Undefined Length Burst Type"] + #[inline(always)] + pub fn ulbt(&mut self) -> ULBT_W { + ULBT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Master Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mcfg](index.html) module"] +pub struct MCFG_SPEC; +impl crate::RegisterSpec for MCFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [mcfg::R](R) reader structure"] +impl crate::Readable for MCFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [mcfg::W](W) writer structure"] +impl crate::Writable for MCFG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets MCFG[%s] +to value 0x02"] +impl crate::Resettable for MCFG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x02 + } +} diff --git a/pac/atsamc20j/src/hmatrixhs/mrcr.rs b/pac/atsamc20j/src/hmatrixhs/mrcr.rs new file mode 100644 index 000000000000..0cf2a1fb01be --- /dev/null +++ b/pac/atsamc20j/src/hmatrixhs/mrcr.rs @@ -0,0 +1,1570 @@ +#[doc = "Register `MRCR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MRCR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Remap Command Bit for Master 0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB0_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB0_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB0` reader - Remap Command Bit for Master 0"] +pub struct RCB0_R(crate::FieldReader); +impl RCB0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB0_A { + match self.bits { + false => RCB0_A::DIS, + true => RCB0_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB0_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB0_A::ENA + } +} +impl core::ops::Deref for RCB0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB0` writer - Remap Command Bit for Master 0"] +pub struct RCB0_W<'a> { + w: &'a mut W, +} +impl<'a> RCB0_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB0_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB0_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB0_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Remap Command Bit for Master 1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB1_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB1_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB1` reader - Remap Command Bit for Master 1"] +pub struct RCB1_R(crate::FieldReader); +impl RCB1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB1_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB1_A { + match self.bits { + false => RCB1_A::DIS, + true => RCB1_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB1_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB1_A::ENA + } +} +impl core::ops::Deref for RCB1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB1` writer - Remap Command Bit for Master 1"] +pub struct RCB1_W<'a> { + w: &'a mut W, +} +impl<'a> RCB1_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB1_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB1_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB1_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Remap Command Bit for Master 2\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB2_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB2_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB2` reader - Remap Command Bit for Master 2"] +pub struct RCB2_R(crate::FieldReader); +impl RCB2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB2_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB2_A { + match self.bits { + false => RCB2_A::DIS, + true => RCB2_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB2_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB2_A::ENA + } +} +impl core::ops::Deref for RCB2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB2` writer - Remap Command Bit for Master 2"] +pub struct RCB2_W<'a> { + w: &'a mut W, +} +impl<'a> RCB2_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB2_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB2_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB2_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Remap Command Bit for Master 3\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB3_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB3_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB3` reader - Remap Command Bit for Master 3"] +pub struct RCB3_R(crate::FieldReader); +impl RCB3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB3_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB3_A { + match self.bits { + false => RCB3_A::DIS, + true => RCB3_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB3_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB3_A::ENA + } +} +impl core::ops::Deref for RCB3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB3` writer - Remap Command Bit for Master 3"] +pub struct RCB3_W<'a> { + w: &'a mut W, +} +impl<'a> RCB3_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB3_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB3_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB3_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Remap Command Bit for Master 4\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB4_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB4_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB4` reader - Remap Command Bit for Master 4"] +pub struct RCB4_R(crate::FieldReader); +impl RCB4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB4_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB4_A { + match self.bits { + false => RCB4_A::DIS, + true => RCB4_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB4_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB4_A::ENA + } +} +impl core::ops::Deref for RCB4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB4` writer - Remap Command Bit for Master 4"] +pub struct RCB4_W<'a> { + w: &'a mut W, +} +impl<'a> RCB4_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB4_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB4_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB4_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Remap Command Bit for Master 5\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB5_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB5_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB5` reader - Remap Command Bit for Master 5"] +pub struct RCB5_R(crate::FieldReader); +impl RCB5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB5_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB5_A { + match self.bits { + false => RCB5_A::DIS, + true => RCB5_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB5_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB5_A::ENA + } +} +impl core::ops::Deref for RCB5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB5` writer - Remap Command Bit for Master 5"] +pub struct RCB5_W<'a> { + w: &'a mut W, +} +impl<'a> RCB5_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB5_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB5_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB5_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Remap Command Bit for Master 6\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB6_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB6_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB6` reader - Remap Command Bit for Master 6"] +pub struct RCB6_R(crate::FieldReader); +impl RCB6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB6_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB6_A { + match self.bits { + false => RCB6_A::DIS, + true => RCB6_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB6_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB6_A::ENA + } +} +impl core::ops::Deref for RCB6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB6` writer - Remap Command Bit for Master 6"] +pub struct RCB6_W<'a> { + w: &'a mut W, +} +impl<'a> RCB6_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB6_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB6_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB6_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Remap Command Bit for Master 7\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB7_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB7_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB7` reader - Remap Command Bit for Master 7"] +pub struct RCB7_R(crate::FieldReader); +impl RCB7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB7_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB7_A { + match self.bits { + false => RCB7_A::DIS, + true => RCB7_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB7_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB7_A::ENA + } +} +impl core::ops::Deref for RCB7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB7` writer - Remap Command Bit for Master 7"] +pub struct RCB7_W<'a> { + w: &'a mut W, +} +impl<'a> RCB7_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB7_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB7_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB7_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Remap Command Bit for Master 8\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB8_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB8_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB8` reader - Remap Command Bit for Master 8"] +pub struct RCB8_R(crate::FieldReader); +impl RCB8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB8_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB8_A { + match self.bits { + false => RCB8_A::DIS, + true => RCB8_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB8_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB8_A::ENA + } +} +impl core::ops::Deref for RCB8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB8` writer - Remap Command Bit for Master 8"] +pub struct RCB8_W<'a> { + w: &'a mut W, +} +impl<'a> RCB8_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB8_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB8_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB8_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Remap Command Bit for Master 9\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB9_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB9_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB9` reader - Remap Command Bit for Master 9"] +pub struct RCB9_R(crate::FieldReader); +impl RCB9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB9_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB9_A { + match self.bits { + false => RCB9_A::DIS, + true => RCB9_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB9_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB9_A::ENA + } +} +impl core::ops::Deref for RCB9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB9` writer - Remap Command Bit for Master 9"] +pub struct RCB9_W<'a> { + w: &'a mut W, +} +impl<'a> RCB9_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB9_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB9_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB9_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Remap Command Bit for Master 10\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB10_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB10_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB10` reader - Remap Command Bit for Master 10"] +pub struct RCB10_R(crate::FieldReader); +impl RCB10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB10_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB10_A { + match self.bits { + false => RCB10_A::DIS, + true => RCB10_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB10_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB10_A::ENA + } +} +impl core::ops::Deref for RCB10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB10` writer - Remap Command Bit for Master 10"] +pub struct RCB10_W<'a> { + w: &'a mut W, +} +impl<'a> RCB10_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB10_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB10_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB10_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Remap Command Bit for Master 11\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB11_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB11_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB11` reader - Remap Command Bit for Master 11"] +pub struct RCB11_R(crate::FieldReader); +impl RCB11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB11_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB11_A { + match self.bits { + false => RCB11_A::DIS, + true => RCB11_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB11_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB11_A::ENA + } +} +impl core::ops::Deref for RCB11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB11` writer - Remap Command Bit for Master 11"] +pub struct RCB11_W<'a> { + w: &'a mut W, +} +impl<'a> RCB11_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB11_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB11_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB11_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Remap Command Bit for Master 12\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB12_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB12_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB12` reader - Remap Command Bit for Master 12"] +pub struct RCB12_R(crate::FieldReader); +impl RCB12_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB12_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB12_A { + match self.bits { + false => RCB12_A::DIS, + true => RCB12_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB12_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB12_A::ENA + } +} +impl core::ops::Deref for RCB12_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB12` writer - Remap Command Bit for Master 12"] +pub struct RCB12_W<'a> { + w: &'a mut W, +} +impl<'a> RCB12_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB12_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB12_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB12_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Remap Command Bit for Master 13\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB13_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB13_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB13` reader - Remap Command Bit for Master 13"] +pub struct RCB13_R(crate::FieldReader); +impl RCB13_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB13_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB13_A { + match self.bits { + false => RCB13_A::DIS, + true => RCB13_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB13_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB13_A::ENA + } +} +impl core::ops::Deref for RCB13_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB13` writer - Remap Command Bit for Master 13"] +pub struct RCB13_W<'a> { + w: &'a mut W, +} +impl<'a> RCB13_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB13_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB13_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB13_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Remap Command Bit for Master 14\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB14_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB14_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB14` reader - Remap Command Bit for Master 14"] +pub struct RCB14_R(crate::FieldReader); +impl RCB14_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB14_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB14_A { + match self.bits { + false => RCB14_A::DIS, + true => RCB14_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB14_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB14_A::ENA + } +} +impl core::ops::Deref for RCB14_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB14` writer - Remap Command Bit for Master 14"] +pub struct RCB14_W<'a> { + w: &'a mut W, +} +impl<'a> RCB14_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB14_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB14_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB14_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Remap Command Bit for Master 15\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB15_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB15_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB15` reader - Remap Command Bit for Master 15"] +pub struct RCB15_R(crate::FieldReader); +impl RCB15_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB15_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB15_A { + match self.bits { + false => RCB15_A::DIS, + true => RCB15_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB15_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB15_A::ENA + } +} +impl core::ops::Deref for RCB15_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB15` writer - Remap Command Bit for Master 15"] +pub struct RCB15_W<'a> { + w: &'a mut W, +} +impl<'a> RCB15_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB15_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB15_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB15_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Remap Command Bit for Master 0"] + #[inline(always)] + pub fn rcb0(&self) -> RCB0_R { + RCB0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Remap Command Bit for Master 1"] + #[inline(always)] + pub fn rcb1(&self) -> RCB1_R { + RCB1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Remap Command Bit for Master 2"] + #[inline(always)] + pub fn rcb2(&self) -> RCB2_R { + RCB2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Remap Command Bit for Master 3"] + #[inline(always)] + pub fn rcb3(&self) -> RCB3_R { + RCB3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Remap Command Bit for Master 4"] + #[inline(always)] + pub fn rcb4(&self) -> RCB4_R { + RCB4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Remap Command Bit for Master 5"] + #[inline(always)] + pub fn rcb5(&self) -> RCB5_R { + RCB5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Remap Command Bit for Master 6"] + #[inline(always)] + pub fn rcb6(&self) -> RCB6_R { + RCB6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Remap Command Bit for Master 7"] + #[inline(always)] + pub fn rcb7(&self) -> RCB7_R { + RCB7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Remap Command Bit for Master 8"] + #[inline(always)] + pub fn rcb8(&self) -> RCB8_R { + RCB8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Remap Command Bit for Master 9"] + #[inline(always)] + pub fn rcb9(&self) -> RCB9_R { + RCB9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Remap Command Bit for Master 10"] + #[inline(always)] + pub fn rcb10(&self) -> RCB10_R { + RCB10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Remap Command Bit for Master 11"] + #[inline(always)] + pub fn rcb11(&self) -> RCB11_R { + RCB11_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Remap Command Bit for Master 12"] + #[inline(always)] + pub fn rcb12(&self) -> RCB12_R { + RCB12_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Remap Command Bit for Master 13"] + #[inline(always)] + pub fn rcb13(&self) -> RCB13_R { + RCB13_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Remap Command Bit for Master 14"] + #[inline(always)] + pub fn rcb14(&self) -> RCB14_R { + RCB14_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Remap Command Bit for Master 15"] + #[inline(always)] + pub fn rcb15(&self) -> RCB15_R { + RCB15_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Remap Command Bit for Master 0"] + #[inline(always)] + pub fn rcb0(&mut self) -> RCB0_W { + RCB0_W { w: self } + } + #[doc = "Bit 1 - Remap Command Bit for Master 1"] + #[inline(always)] + pub fn rcb1(&mut self) -> RCB1_W { + RCB1_W { w: self } + } + #[doc = "Bit 2 - Remap Command Bit for Master 2"] + #[inline(always)] + pub fn rcb2(&mut self) -> RCB2_W { + RCB2_W { w: self } + } + #[doc = "Bit 3 - Remap Command Bit for Master 3"] + #[inline(always)] + pub fn rcb3(&mut self) -> RCB3_W { + RCB3_W { w: self } + } + #[doc = "Bit 4 - Remap Command Bit for Master 4"] + #[inline(always)] + pub fn rcb4(&mut self) -> RCB4_W { + RCB4_W { w: self } + } + #[doc = "Bit 5 - Remap Command Bit for Master 5"] + #[inline(always)] + pub fn rcb5(&mut self) -> RCB5_W { + RCB5_W { w: self } + } + #[doc = "Bit 6 - Remap Command Bit for Master 6"] + #[inline(always)] + pub fn rcb6(&mut self) -> RCB6_W { + RCB6_W { w: self } + } + #[doc = "Bit 7 - Remap Command Bit for Master 7"] + #[inline(always)] + pub fn rcb7(&mut self) -> RCB7_W { + RCB7_W { w: self } + } + #[doc = "Bit 8 - Remap Command Bit for Master 8"] + #[inline(always)] + pub fn rcb8(&mut self) -> RCB8_W { + RCB8_W { w: self } + } + #[doc = "Bit 9 - Remap Command Bit for Master 9"] + #[inline(always)] + pub fn rcb9(&mut self) -> RCB9_W { + RCB9_W { w: self } + } + #[doc = "Bit 10 - Remap Command Bit for Master 10"] + #[inline(always)] + pub fn rcb10(&mut self) -> RCB10_W { + RCB10_W { w: self } + } + #[doc = "Bit 11 - Remap Command Bit for Master 11"] + #[inline(always)] + pub fn rcb11(&mut self) -> RCB11_W { + RCB11_W { w: self } + } + #[doc = "Bit 12 - Remap Command Bit for Master 12"] + #[inline(always)] + pub fn rcb12(&mut self) -> RCB12_W { + RCB12_W { w: self } + } + #[doc = "Bit 13 - Remap Command Bit for Master 13"] + #[inline(always)] + pub fn rcb13(&mut self) -> RCB13_W { + RCB13_W { w: self } + } + #[doc = "Bit 14 - Remap Command Bit for Master 14"] + #[inline(always)] + pub fn rcb14(&mut self) -> RCB14_W { + RCB14_W { w: self } + } + #[doc = "Bit 15 - Remap Command Bit for Master 15"] + #[inline(always)] + pub fn rcb15(&mut self) -> RCB15_W { + RCB15_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Master Remap Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mrcr](index.html) module"] +pub struct MRCR_SPEC; +impl crate::RegisterSpec for MRCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [mrcr::R](R) reader structure"] +impl crate::Readable for MRCR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [mrcr::W](W) writer structure"] +impl crate::Writable for MRCR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets MRCR to value 0"] +impl crate::Resettable for MRCR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/hmatrixhs/prs.rs b/pac/atsamc20j/src/hmatrixhs/prs.rs new file mode 100644 index 000000000000..0313f3c4fc20 --- /dev/null +++ b/pac/atsamc20j/src/hmatrixhs/prs.rs @@ -0,0 +1,8 @@ +#[doc = "PRAS register accessor: an alias for `Reg`"] +pub type PRAS = crate::Reg; +#[doc = "Priority A for Slave"] +pub mod pras; +#[doc = "PRBS register accessor: an alias for `Reg`"] +pub type PRBS = crate::Reg; +#[doc = "Priority B for Slave"] +pub mod prbs; diff --git a/pac/atsamc20j/src/hmatrixhs/prs/pras.rs b/pac/atsamc20j/src/hmatrixhs/prs/pras.rs new file mode 100644 index 000000000000..ac4744a9e2a0 --- /dev/null +++ b/pac/atsamc20j/src/hmatrixhs/prs/pras.rs @@ -0,0 +1,362 @@ +#[doc = "Register `PRAS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PRAS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `M0PR` reader - Master 0 Priority"] +pub struct M0PR_R(crate::FieldReader); +impl M0PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M0PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M0PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M0PR` writer - Master 0 Priority"] +pub struct M0PR_W<'a> { + w: &'a mut W, +} +impl<'a> M0PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Field `M1PR` reader - Master 1 Priority"] +pub struct M1PR_R(crate::FieldReader); +impl M1PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M1PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M1PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M1PR` writer - Master 1 Priority"] +pub struct M1PR_W<'a> { + w: &'a mut W, +} +impl<'a> M1PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 4)) | ((value as u32 & 0x0f) << 4); + self.w + } +} +#[doc = "Field `M2PR` reader - Master 2 Priority"] +pub struct M2PR_R(crate::FieldReader); +impl M2PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M2PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M2PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M2PR` writer - Master 2 Priority"] +pub struct M2PR_W<'a> { + w: &'a mut W, +} +impl<'a> M2PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 8)) | ((value as u32 & 0x0f) << 8); + self.w + } +} +#[doc = "Field `M3PR` reader - Master 3 Priority"] +pub struct M3PR_R(crate::FieldReader); +impl M3PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M3PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M3PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M3PR` writer - Master 3 Priority"] +pub struct M3PR_W<'a> { + w: &'a mut W, +} +impl<'a> M3PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 12)) | ((value as u32 & 0x0f) << 12); + self.w + } +} +#[doc = "Field `M4PR` reader - Master 4 Priority"] +pub struct M4PR_R(crate::FieldReader); +impl M4PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M4PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M4PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M4PR` writer - Master 4 Priority"] +pub struct M4PR_W<'a> { + w: &'a mut W, +} +impl<'a> M4PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 16)) | ((value as u32 & 0x0f) << 16); + self.w + } +} +#[doc = "Field `M5PR` reader - Master 5 Priority"] +pub struct M5PR_R(crate::FieldReader); +impl M5PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M5PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M5PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M5PR` writer - Master 5 Priority"] +pub struct M5PR_W<'a> { + w: &'a mut W, +} +impl<'a> M5PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 20)) | ((value as u32 & 0x0f) << 20); + self.w + } +} +#[doc = "Field `M6PR` reader - Master 6 Priority"] +pub struct M6PR_R(crate::FieldReader); +impl M6PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M6PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M6PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M6PR` writer - Master 6 Priority"] +pub struct M6PR_W<'a> { + w: &'a mut W, +} +impl<'a> M6PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Field `M7PR` reader - Master 7 Priority"] +pub struct M7PR_R(crate::FieldReader); +impl M7PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M7PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M7PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M7PR` writer - Master 7 Priority"] +pub struct M7PR_W<'a> { + w: &'a mut W, +} +impl<'a> M7PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 28)) | ((value as u32 & 0x0f) << 28); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Master 0 Priority"] + #[inline(always)] + pub fn m0pr(&self) -> M0PR_R { + M0PR_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Master 1 Priority"] + #[inline(always)] + pub fn m1pr(&self) -> M1PR_R { + M1PR_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 8:11 - Master 2 Priority"] + #[inline(always)] + pub fn m2pr(&self) -> M2PR_R { + M2PR_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - Master 3 Priority"] + #[inline(always)] + pub fn m3pr(&self) -> M3PR_R { + M3PR_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:19 - Master 4 Priority"] + #[inline(always)] + pub fn m4pr(&self) -> M4PR_R { + M4PR_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bits 20:23 - Master 5 Priority"] + #[inline(always)] + pub fn m5pr(&self) -> M5PR_R { + M5PR_R::new(((self.bits >> 20) & 0x0f) as u8) + } + #[doc = "Bits 24:27 - Master 6 Priority"] + #[inline(always)] + pub fn m6pr(&self) -> M6PR_R { + M6PR_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bits 28:31 - Master 7 Priority"] + #[inline(always)] + pub fn m7pr(&self) -> M7PR_R { + M7PR_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Master 0 Priority"] + #[inline(always)] + pub fn m0pr(&mut self) -> M0PR_W { + M0PR_W { w: self } + } + #[doc = "Bits 4:7 - Master 1 Priority"] + #[inline(always)] + pub fn m1pr(&mut self) -> M1PR_W { + M1PR_W { w: self } + } + #[doc = "Bits 8:11 - Master 2 Priority"] + #[inline(always)] + pub fn m2pr(&mut self) -> M2PR_W { + M2PR_W { w: self } + } + #[doc = "Bits 12:15 - Master 3 Priority"] + #[inline(always)] + pub fn m3pr(&mut self) -> M3PR_W { + M3PR_W { w: self } + } + #[doc = "Bits 16:19 - Master 4 Priority"] + #[inline(always)] + pub fn m4pr(&mut self) -> M4PR_W { + M4PR_W { w: self } + } + #[doc = "Bits 20:23 - Master 5 Priority"] + #[inline(always)] + pub fn m5pr(&mut self) -> M5PR_W { + M5PR_W { w: self } + } + #[doc = "Bits 24:27 - Master 6 Priority"] + #[inline(always)] + pub fn m6pr(&mut self) -> M6PR_W { + M6PR_W { w: self } + } + #[doc = "Bits 28:31 - Master 7 Priority"] + #[inline(always)] + pub fn m7pr(&mut self) -> M7PR_W { + M7PR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Priority A for Slave\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pras](index.html) module"] +pub struct PRAS_SPEC; +impl crate::RegisterSpec for PRAS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pras::R](R) reader structure"] +impl crate::Readable for PRAS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [pras::W](W) writer structure"] +impl crate::Writable for PRAS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PRAS to value 0"] +impl crate::Resettable for PRAS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/hmatrixhs/prs/prbs.rs b/pac/atsamc20j/src/hmatrixhs/prs/prbs.rs new file mode 100644 index 000000000000..a2cc6bb9f6b0 --- /dev/null +++ b/pac/atsamc20j/src/hmatrixhs/prs/prbs.rs @@ -0,0 +1,362 @@ +#[doc = "Register `PRBS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PRBS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `M8PR` reader - Master 8 Priority"] +pub struct M8PR_R(crate::FieldReader); +impl M8PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M8PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M8PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M8PR` writer - Master 8 Priority"] +pub struct M8PR_W<'a> { + w: &'a mut W, +} +impl<'a> M8PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Field `M9PR` reader - Master 9 Priority"] +pub struct M9PR_R(crate::FieldReader); +impl M9PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M9PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M9PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M9PR` writer - Master 9 Priority"] +pub struct M9PR_W<'a> { + w: &'a mut W, +} +impl<'a> M9PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 4)) | ((value as u32 & 0x0f) << 4); + self.w + } +} +#[doc = "Field `M10PR` reader - Master 10 Priority"] +pub struct M10PR_R(crate::FieldReader); +impl M10PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M10PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M10PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M10PR` writer - Master 10 Priority"] +pub struct M10PR_W<'a> { + w: &'a mut W, +} +impl<'a> M10PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 8)) | ((value as u32 & 0x0f) << 8); + self.w + } +} +#[doc = "Field `M11PR` reader - Master 11 Priority"] +pub struct M11PR_R(crate::FieldReader); +impl M11PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M11PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M11PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M11PR` writer - Master 11 Priority"] +pub struct M11PR_W<'a> { + w: &'a mut W, +} +impl<'a> M11PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 12)) | ((value as u32 & 0x0f) << 12); + self.w + } +} +#[doc = "Field `M12PR` reader - Master 12 Priority"] +pub struct M12PR_R(crate::FieldReader); +impl M12PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M12PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M12PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M12PR` writer - Master 12 Priority"] +pub struct M12PR_W<'a> { + w: &'a mut W, +} +impl<'a> M12PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 16)) | ((value as u32 & 0x0f) << 16); + self.w + } +} +#[doc = "Field `M13PR` reader - Master 13 Priority"] +pub struct M13PR_R(crate::FieldReader); +impl M13PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M13PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M13PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M13PR` writer - Master 13 Priority"] +pub struct M13PR_W<'a> { + w: &'a mut W, +} +impl<'a> M13PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 20)) | ((value as u32 & 0x0f) << 20); + self.w + } +} +#[doc = "Field `M14PR` reader - Master 14 Priority"] +pub struct M14PR_R(crate::FieldReader); +impl M14PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M14PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M14PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M14PR` writer - Master 14 Priority"] +pub struct M14PR_W<'a> { + w: &'a mut W, +} +impl<'a> M14PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Field `M15PR` reader - Master 15 Priority"] +pub struct M15PR_R(crate::FieldReader); +impl M15PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M15PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M15PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M15PR` writer - Master 15 Priority"] +pub struct M15PR_W<'a> { + w: &'a mut W, +} +impl<'a> M15PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 28)) | ((value as u32 & 0x0f) << 28); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Master 8 Priority"] + #[inline(always)] + pub fn m8pr(&self) -> M8PR_R { + M8PR_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Master 9 Priority"] + #[inline(always)] + pub fn m9pr(&self) -> M9PR_R { + M9PR_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 8:11 - Master 10 Priority"] + #[inline(always)] + pub fn m10pr(&self) -> M10PR_R { + M10PR_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - Master 11 Priority"] + #[inline(always)] + pub fn m11pr(&self) -> M11PR_R { + M11PR_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:19 - Master 12 Priority"] + #[inline(always)] + pub fn m12pr(&self) -> M12PR_R { + M12PR_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bits 20:23 - Master 13 Priority"] + #[inline(always)] + pub fn m13pr(&self) -> M13PR_R { + M13PR_R::new(((self.bits >> 20) & 0x0f) as u8) + } + #[doc = "Bits 24:27 - Master 14 Priority"] + #[inline(always)] + pub fn m14pr(&self) -> M14PR_R { + M14PR_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bits 28:31 - Master 15 Priority"] + #[inline(always)] + pub fn m15pr(&self) -> M15PR_R { + M15PR_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Master 8 Priority"] + #[inline(always)] + pub fn m8pr(&mut self) -> M8PR_W { + M8PR_W { w: self } + } + #[doc = "Bits 4:7 - Master 9 Priority"] + #[inline(always)] + pub fn m9pr(&mut self) -> M9PR_W { + M9PR_W { w: self } + } + #[doc = "Bits 8:11 - Master 10 Priority"] + #[inline(always)] + pub fn m10pr(&mut self) -> M10PR_W { + M10PR_W { w: self } + } + #[doc = "Bits 12:15 - Master 11 Priority"] + #[inline(always)] + pub fn m11pr(&mut self) -> M11PR_W { + M11PR_W { w: self } + } + #[doc = "Bits 16:19 - Master 12 Priority"] + #[inline(always)] + pub fn m12pr(&mut self) -> M12PR_W { + M12PR_W { w: self } + } + #[doc = "Bits 20:23 - Master 13 Priority"] + #[inline(always)] + pub fn m13pr(&mut self) -> M13PR_W { + M13PR_W { w: self } + } + #[doc = "Bits 24:27 - Master 14 Priority"] + #[inline(always)] + pub fn m14pr(&mut self) -> M14PR_W { + M14PR_W { w: self } + } + #[doc = "Bits 28:31 - Master 15 Priority"] + #[inline(always)] + pub fn m15pr(&mut self) -> M15PR_W { + M15PR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Priority B for Slave\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [prbs](index.html) module"] +pub struct PRBS_SPEC; +impl crate::RegisterSpec for PRBS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [prbs::R](R) reader structure"] +impl crate::Readable for PRBS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [prbs::W](W) writer structure"] +impl crate::Writable for PRBS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PRBS to value 0"] +impl crate::Resettable for PRBS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/hmatrixhs/scfg.rs b/pac/atsamc20j/src/hmatrixhs/scfg.rs new file mode 100644 index 000000000000..7180c043195a --- /dev/null +++ b/pac/atsamc20j/src/hmatrixhs/scfg.rs @@ -0,0 +1,334 @@ +#[doc = "Register `SCFG[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SCFG[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SLOT_CYCLE` reader - Maximum Number of Allowed Cycles for a Burst"] +pub struct SLOT_CYCLE_R(crate::FieldReader); +impl SLOT_CYCLE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SLOT_CYCLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SLOT_CYCLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLOT_CYCLE` writer - Maximum Number of Allowed Cycles for a Burst"] +pub struct SLOT_CYCLE_W<'a> { + w: &'a mut W, +} +impl<'a> SLOT_CYCLE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +#[doc = "Default Master Type\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DEFMSTR_TYPE_A { + #[doc = "0: No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst."] + NO_DEFAULT = 0, + #[doc = "1: Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave."] + LAST_DEFAULT = 1, + #[doc = "2: Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave."] + FIXED_DEFAULT = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DEFMSTR_TYPE_A) -> Self { + variant as _ + } +} +#[doc = "Field `DEFMSTR_TYPE` reader - Default Master Type"] +pub struct DEFMSTR_TYPE_R(crate::FieldReader); +impl DEFMSTR_TYPE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DEFMSTR_TYPE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(DEFMSTR_TYPE_A::NO_DEFAULT), + 1 => Some(DEFMSTR_TYPE_A::LAST_DEFAULT), + 2 => Some(DEFMSTR_TYPE_A::FIXED_DEFAULT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NO_DEFAULT`"] + #[inline(always)] + pub fn is_no_default(&self) -> bool { + **self == DEFMSTR_TYPE_A::NO_DEFAULT + } + #[doc = "Checks if the value of the field is `LAST_DEFAULT`"] + #[inline(always)] + pub fn is_last_default(&self) -> bool { + **self == DEFMSTR_TYPE_A::LAST_DEFAULT + } + #[doc = "Checks if the value of the field is `FIXED_DEFAULT`"] + #[inline(always)] + pub fn is_fixed_default(&self) -> bool { + **self == DEFMSTR_TYPE_A::FIXED_DEFAULT + } +} +impl core::ops::Deref for DEFMSTR_TYPE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DEFMSTR_TYPE` writer - Default Master Type"] +pub struct DEFMSTR_TYPE_W<'a> { + w: &'a mut W, +} +impl<'a> DEFMSTR_TYPE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DEFMSTR_TYPE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst."] + #[inline(always)] + pub fn no_default(self) -> &'a mut W { + self.variant(DEFMSTR_TYPE_A::NO_DEFAULT) + } + #[doc = "Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave."] + #[inline(always)] + pub fn last_default(self) -> &'a mut W { + self.variant(DEFMSTR_TYPE_A::LAST_DEFAULT) + } + #[doc = "Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave."] + #[inline(always)] + pub fn fixed_default(self) -> &'a mut W { + self.variant(DEFMSTR_TYPE_A::FIXED_DEFAULT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Field `FIXED_DEFMSTR` reader - Fixed Index of Default Master"] +pub struct FIXED_DEFMSTR_R(crate::FieldReader); +impl FIXED_DEFMSTR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FIXED_DEFMSTR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FIXED_DEFMSTR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FIXED_DEFMSTR` writer - Fixed Index of Default Master"] +pub struct FIXED_DEFMSTR_W<'a> { + w: &'a mut W, +} +impl<'a> FIXED_DEFMSTR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 18)) | ((value as u32 & 0x0f) << 18); + self.w + } +} +#[doc = "Arbitration Type\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ARBT_A { + #[doc = "0: Round-Robin Arbitration"] + ROUND_ROBIN = 0, + #[doc = "1: Fixed Priority Arbitration"] + FIXED_PRIORITY = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ARBT_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ARBT` reader - Arbitration Type"] +pub struct ARBT_R(crate::FieldReader); +impl ARBT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ARBT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ARBT_A { + match self.bits { + false => ARBT_A::ROUND_ROBIN, + true => ARBT_A::FIXED_PRIORITY, + } + } + #[doc = "Checks if the value of the field is `ROUND_ROBIN`"] + #[inline(always)] + pub fn is_round_robin(&self) -> bool { + **self == ARBT_A::ROUND_ROBIN + } + #[doc = "Checks if the value of the field is `FIXED_PRIORITY`"] + #[inline(always)] + pub fn is_fixed_priority(&self) -> bool { + **self == ARBT_A::FIXED_PRIORITY + } +} +impl core::ops::Deref for ARBT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ARBT` writer - Arbitration Type"] +pub struct ARBT_W<'a> { + w: &'a mut W, +} +impl<'a> ARBT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: ARBT_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Round-Robin Arbitration"] + #[inline(always)] + pub fn round_robin(self) -> &'a mut W { + self.variant(ARBT_A::ROUND_ROBIN) + } + #[doc = "Fixed Priority Arbitration"] + #[inline(always)] + pub fn fixed_priority(self) -> &'a mut W { + self.variant(ARBT_A::FIXED_PRIORITY) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Maximum Number of Allowed Cycles for a Burst"] + #[inline(always)] + pub fn slot_cycle(&self) -> SLOT_CYCLE_R { + SLOT_CYCLE_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 16:17 - Default Master Type"] + #[inline(always)] + pub fn defmstr_type(&self) -> DEFMSTR_TYPE_R { + DEFMSTR_TYPE_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bits 18:21 - Fixed Index of Default Master"] + #[inline(always)] + pub fn fixed_defmstr(&self) -> FIXED_DEFMSTR_R { + FIXED_DEFMSTR_R::new(((self.bits >> 18) & 0x0f) as u8) + } + #[doc = "Bit 24 - Arbitration Type"] + #[inline(always)] + pub fn arbt(&self) -> ARBT_R { + ARBT_R::new(((self.bits >> 24) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - Maximum Number of Allowed Cycles for a Burst"] + #[inline(always)] + pub fn slot_cycle(&mut self) -> SLOT_CYCLE_W { + SLOT_CYCLE_W { w: self } + } + #[doc = "Bits 16:17 - Default Master Type"] + #[inline(always)] + pub fn defmstr_type(&mut self) -> DEFMSTR_TYPE_W { + DEFMSTR_TYPE_W { w: self } + } + #[doc = "Bits 18:21 - Fixed Index of Default Master"] + #[inline(always)] + pub fn fixed_defmstr(&mut self) -> FIXED_DEFMSTR_W { + FIXED_DEFMSTR_W { w: self } + } + #[doc = "Bit 24 - Arbitration Type"] + #[inline(always)] + pub fn arbt(&mut self) -> ARBT_W { + ARBT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Slave Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [scfg](index.html) module"] +pub struct SCFG_SPEC; +impl crate::RegisterSpec for SCFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [scfg::R](R) reader structure"] +impl crate::Readable for SCFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [scfg::W](W) writer structure"] +impl crate::Writable for SCFG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SCFG[%s] +to value 0x10"] +impl crate::Resettable for SCFG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x10 + } +} diff --git a/pac/atsamc20j/src/hmatrixhs/sfr.rs b/pac/atsamc20j/src/hmatrixhs/sfr.rs new file mode 100644 index 000000000000..0a7e024f73c8 --- /dev/null +++ b/pac/atsamc20j/src/hmatrixhs/sfr.rs @@ -0,0 +1,104 @@ +#[doc = "Register `SFR[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SFR[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SFR` reader - Special Function Register"] +pub struct SFR_R(crate::FieldReader); +impl SFR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + SFR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SFR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SFR` writer - Special Function Register"] +pub struct SFR_W<'a> { + w: &'a mut W, +} +impl<'a> SFR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Special Function Register"] + #[inline(always)] + pub fn sfr(&self) -> SFR_R { + SFR_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Special Function Register"] + #[inline(always)] + pub fn sfr(&mut self) -> SFR_W { + SFR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Special Function\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sfr](index.html) module"] +pub struct SFR_SPEC; +impl crate::RegisterSpec for SFR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [sfr::R](R) reader structure"] +impl crate::Readable for SFR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [sfr::W](W) writer structure"] +impl crate::Writable for SFR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SFR[%s] +to value 0"] +impl crate::Resettable for SFR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/lib.rs b/pac/atsamc20j/src/lib.rs new file mode 100644 index 000000000000..2b020f5f4a5d --- /dev/null +++ b/pac/atsamc20j/src/lib.rs @@ -0,0 +1,1437 @@ +#![doc = "Peripheral access API for ATSAMC20J microcontrollers (generated using svd2rust v0.20.0 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] +svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.20.0/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"] +#![deny(const_err)] +#![deny(dead_code)] +#![deny(improper_ctypes)] +#![deny(missing_docs)] +#![deny(no_mangle_generic_items)] +#![deny(non_shorthand_field_patterns)] +#![deny(overflowing_literals)] +#![deny(path_statements)] +#![deny(patterns_in_fns_without_body)] +#![deny(private_in_public)] +#![deny(unconditional_recursion)] +#![deny(unused_allocation)] +#![deny(unused_comparisons)] +#![deny(unused_parens)] +#![deny(while_true)] +#![allow(non_camel_case_types)] +#![allow(non_snake_case)] +#![allow(clippy::all)] +#![no_std] +use core::marker::PhantomData; +use core::ops::Deref; +#[doc = r"Number available in the NVIC for configuring priority"] +pub const NVIC_PRIO_BITS: u8 = 2; +#[cfg(feature = "rt")] +pub use self::Interrupt as interrupt; +pub use cortex_m::peripheral::Peripherals as CorePeripherals; +pub use cortex_m::peripheral::{CBP, CPUID, DCB, DWT, FPB, ITM, MPU, NVIC, SCB, SYST, TPIU}; +#[cfg(feature = "rt")] +pub use cortex_m_rt::interrupt; +#[allow(unused_imports)] +use generic::*; +#[doc = r"Common register and bit access and modify traits"] +pub mod generic; +#[cfg(feature = "rt")] +extern "C" { + fn WDT(); + fn RTC(); + fn EIC(); + fn FREQM(); + fn NVMCTRL(); + fn DMAC(); + fn EVSYS(); + fn SERCOM0(); + fn SERCOM1(); + fn SERCOM2(); + fn SERCOM3(); + fn TCC0(); + fn TCC1(); + fn TCC2(); + fn TC0(); + fn TC1(); + fn TC2(); + fn TC3(); + fn TC4(); + fn ADC0(); + fn AC(); + fn PTC(); +} +#[doc(hidden)] +pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, +} +#[cfg(feature = "rt")] +#[doc(hidden)] +#[link_section = ".vector_table.interrupts"] +#[no_mangle] +pub static __INTERRUPTS: [Vector; 31] = [ + Vector { _reserved: 0 }, + Vector { _handler: WDT }, + Vector { _handler: RTC }, + Vector { _handler: EIC }, + Vector { _handler: FREQM }, + Vector { _reserved: 0 }, + Vector { _handler: NVMCTRL }, + Vector { _handler: DMAC }, + Vector { _handler: EVSYS }, + Vector { _handler: SERCOM0 }, + Vector { _handler: SERCOM1 }, + Vector { _handler: SERCOM2 }, + Vector { _handler: SERCOM3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TCC0 }, + Vector { _handler: TCC1 }, + Vector { _handler: TCC2 }, + Vector { _handler: TC0 }, + Vector { _handler: TC1 }, + Vector { _handler: TC2 }, + Vector { _handler: TC3 }, + Vector { _handler: TC4 }, + Vector { _handler: ADC0 }, + Vector { _reserved: 0 }, + Vector { _handler: AC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: PTC }, +]; +#[doc = r"Enumeration of all the interrupts."] +#[derive(Copy, Clone, Debug, PartialEq, Eq)] +#[repr(u16)] +pub enum Interrupt { + #[doc = "1 - WDT"] + WDT = 1, + #[doc = "2 - RTC"] + RTC = 2, + #[doc = "3 - EIC"] + EIC = 3, + #[doc = "4 - FREQM"] + FREQM = 4, + #[doc = "6 - NVMCTRL"] + NVMCTRL = 6, + #[doc = "7 - DMAC"] + DMAC = 7, + #[doc = "8 - EVSYS"] + EVSYS = 8, + #[doc = "9 - SERCOM0"] + SERCOM0 = 9, + #[doc = "10 - SERCOM1"] + SERCOM1 = 10, + #[doc = "11 - SERCOM2"] + SERCOM2 = 11, + #[doc = "12 - SERCOM3"] + SERCOM3 = 12, + #[doc = "17 - TCC0"] + TCC0 = 17, + #[doc = "18 - TCC1"] + TCC1 = 18, + #[doc = "19 - TCC2"] + TCC2 = 19, + #[doc = "20 - TC0"] + TC0 = 20, + #[doc = "21 - TC1"] + TC1 = 21, + #[doc = "22 - TC2"] + TC2 = 22, + #[doc = "23 - TC3"] + TC3 = 23, + #[doc = "24 - TC4"] + TC4 = 24, + #[doc = "25 - ADC0"] + ADC0 = 25, + #[doc = "27 - AC"] + AC = 27, + #[doc = "30 - PTC"] + PTC = 30, +} +unsafe impl cortex_m::interrupt::InterruptNumber for Interrupt { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } +} +#[doc = "Analog Comparators"] +pub struct AC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for AC {} +impl AC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const ac::RegisterBlock = 0x4200_5000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const ac::RegisterBlock { + Self::PTR + } +} +impl Deref for AC { + type Target = ac::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for AC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AC").finish() + } +} +#[doc = "Analog Comparators"] +pub mod ac; +#[doc = "Analog Digital Converter"] +pub struct ADC0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for ADC0 {} +impl ADC0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const adc0::RegisterBlock = 0x4200_4400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const adc0::RegisterBlock { + Self::PTR + } +} +impl Deref for ADC0 { + type Target = adc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for ADC0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ADC0").finish() + } +} +#[doc = "Analog Digital Converter"] +pub mod adc0; +#[doc = "Configurable Custom Logic"] +pub struct CCL { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for CCL {} +impl CCL { + #[doc = r"Pointer to the register block"] + pub const PTR: *const ccl::RegisterBlock = 0x4200_5c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const ccl::RegisterBlock { + Self::PTR + } +} +impl Deref for CCL { + type Target = ccl::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for CCL { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CCL").finish() + } +} +#[doc = "Configurable Custom Logic"] +pub mod ccl; +#[doc = "Divide and Square Root Accelerator"] +pub struct DIVAS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for DIVAS {} +impl DIVAS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const divas::RegisterBlock = 0x4800_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const divas::RegisterBlock { + Self::PTR + } +} +impl Deref for DIVAS { + type Target = divas::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for DIVAS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DIVAS").finish() + } +} +#[doc = "Divide and Square Root Accelerator"] +pub mod divas; +#[doc = "Direct Memory Access Controller"] +pub struct DMAC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for DMAC {} +impl DMAC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const dmac::RegisterBlock = 0x4100_6000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const dmac::RegisterBlock { + Self::PTR + } +} +impl Deref for DMAC { + type Target = dmac::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for DMAC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DMAC").finish() + } +} +#[doc = "Direct Memory Access Controller"] +pub mod dmac; +#[doc = "Device Service Unit"] +pub struct DSU { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for DSU {} +impl DSU { + #[doc = r"Pointer to the register block"] + pub const PTR: *const dsu::RegisterBlock = 0x4100_2000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const dsu::RegisterBlock { + Self::PTR + } +} +impl Deref for DSU { + type Target = dsu::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for DSU { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DSU").finish() + } +} +#[doc = "Device Service Unit"] +pub mod dsu; +#[doc = "External Interrupt Controller"] +pub struct EIC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for EIC {} +impl EIC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const eic::RegisterBlock = 0x4000_2800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const eic::RegisterBlock { + Self::PTR + } +} +impl Deref for EIC { + type Target = eic::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for EIC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EIC").finish() + } +} +#[doc = "External Interrupt Controller"] +pub mod eic; +#[doc = "Event System Interface"] +pub struct EVSYS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for EVSYS {} +impl EVSYS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const evsys::RegisterBlock = 0x4200_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const evsys::RegisterBlock { + Self::PTR + } +} +impl Deref for EVSYS { + type Target = evsys::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for EVSYS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EVSYS").finish() + } +} +#[doc = "Event System Interface"] +pub mod evsys; +#[doc = "Frequency Meter"] +pub struct FREQM { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for FREQM {} +impl FREQM { + #[doc = r"Pointer to the register block"] + pub const PTR: *const freqm::RegisterBlock = 0x4000_2c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const freqm::RegisterBlock { + Self::PTR + } +} +impl Deref for FREQM { + type Target = freqm::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for FREQM { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FREQM").finish() + } +} +#[doc = "Frequency Meter"] +pub mod freqm; +#[doc = "Generic Clock Generator"] +pub struct GCLK { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for GCLK {} +impl GCLK { + #[doc = r"Pointer to the register block"] + pub const PTR: *const gclk::RegisterBlock = 0x4000_1c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const gclk::RegisterBlock { + Self::PTR + } +} +impl Deref for GCLK { + type Target = gclk::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for GCLK { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GCLK").finish() + } +} +#[doc = "Generic Clock Generator"] +pub mod gclk; +#[doc = "HSB Matrix"] +pub struct HMATRIXHS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for HMATRIXHS {} +impl HMATRIXHS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const hmatrixhs::RegisterBlock = 0x4100_a000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const hmatrixhs::RegisterBlock { + Self::PTR + } +} +impl Deref for HMATRIXHS { + type Target = hmatrixhs::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for HMATRIXHS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HMATRIXHS").finish() + } +} +#[doc = "HSB Matrix"] +pub mod hmatrixhs; +#[doc = "Main Clock"] +pub struct MCLK { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for MCLK {} +impl MCLK { + #[doc = r"Pointer to the register block"] + pub const PTR: *const mclk::RegisterBlock = 0x4000_0800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const mclk::RegisterBlock { + Self::PTR + } +} +impl Deref for MCLK { + type Target = mclk::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for MCLK { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MCLK").finish() + } +} +#[doc = "Main Clock"] +pub mod mclk; +#[doc = "Cortex-M0+ Micro-Trace Buffer"] +pub struct MTB { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for MTB {} +impl MTB { + #[doc = r"Pointer to the register block"] + pub const PTR: *const mtb::RegisterBlock = 0x4100_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const mtb::RegisterBlock { + Self::PTR + } +} +impl Deref for MTB { + type Target = mtb::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for MTB { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MTB").finish() + } +} +#[doc = "Cortex-M0+ Micro-Trace Buffer"] +pub mod mtb; +#[doc = "Non-Volatile Memory Controller"] +pub struct NVMCTRL { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for NVMCTRL {} +impl NVMCTRL { + #[doc = r"Pointer to the register block"] + pub const PTR: *const nvmctrl::RegisterBlock = 0x4100_4000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const nvmctrl::RegisterBlock { + Self::PTR + } +} +impl Deref for NVMCTRL { + type Target = nvmctrl::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for NVMCTRL { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("NVMCTRL").finish() + } +} +#[doc = "Non-Volatile Memory Controller"] +pub mod nvmctrl; +#[doc = "Oscillators Control"] +pub struct OSCCTRL { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for OSCCTRL {} +impl OSCCTRL { + #[doc = r"Pointer to the register block"] + pub const PTR: *const oscctrl::RegisterBlock = 0x4000_1000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const oscctrl::RegisterBlock { + Self::PTR + } +} +impl Deref for OSCCTRL { + type Target = oscctrl::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for OSCCTRL { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OSCCTRL").finish() + } +} +#[doc = "Oscillators Control"] +pub mod oscctrl; +#[doc = "32k Oscillators Control"] +pub struct OSC32KCTRL { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for OSC32KCTRL {} +impl OSC32KCTRL { + #[doc = r"Pointer to the register block"] + pub const PTR: *const osc32kctrl::RegisterBlock = 0x4000_1400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const osc32kctrl::RegisterBlock { + Self::PTR + } +} +impl Deref for OSC32KCTRL { + type Target = osc32kctrl::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for OSC32KCTRL { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OSC32KCTRL").finish() + } +} +#[doc = "32k Oscillators Control"] +pub mod osc32kctrl; +#[doc = "Peripheral Access Controller"] +pub struct PAC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PAC {} +impl PAC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const pac::RegisterBlock = 0x4000_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const pac::RegisterBlock { + Self::PTR + } +} +impl Deref for PAC { + type Target = pac::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PAC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PAC").finish() + } +} +#[doc = "Peripheral Access Controller"] +pub mod pac; +#[doc = "Power Manager"] +pub struct PM { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PM {} +impl PM { + #[doc = r"Pointer to the register block"] + pub const PTR: *const pm::RegisterBlock = 0x4000_0400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const pm::RegisterBlock { + Self::PTR + } +} +impl Deref for PM { + type Target = pm::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PM { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PM").finish() + } +} +#[doc = "Power Manager"] +pub mod pm; +#[doc = "Port Module"] +pub struct PORT { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PORT {} +impl PORT { + #[doc = r"Pointer to the register block"] + pub const PTR: *const port::RegisterBlock = 0x4100_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const port::RegisterBlock { + Self::PTR + } +} +impl Deref for PORT { + type Target = port::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PORT { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PORT").finish() + } +} +#[doc = "Port Module"] +pub mod port; +#[doc = "Port Module"] +pub struct PORT_IOBUS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PORT_IOBUS {} +impl PORT_IOBUS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const port::RegisterBlock = 0x6000_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const port::RegisterBlock { + Self::PTR + } +} +impl Deref for PORT_IOBUS { + type Target = port::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PORT_IOBUS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PORT_IOBUS").finish() + } +} +#[doc = "Port Module"] +pub use port as port_iobus; +#[doc = "Reset Controller"] +pub struct RSTC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for RSTC {} +impl RSTC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const rstc::RegisterBlock = 0x4000_0c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const rstc::RegisterBlock { + Self::PTR + } +} +impl Deref for RSTC { + type Target = rstc::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for RSTC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RSTC").finish() + } +} +#[doc = "Reset Controller"] +pub mod rstc; +#[doc = "Real-Time Counter"] +pub struct RTC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for RTC {} +impl RTC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const rtc::RegisterBlock = 0x4000_2400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const rtc::RegisterBlock { + Self::PTR + } +} +impl Deref for RTC { + type Target = rtc::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for RTC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RTC").finish() + } +} +#[doc = "Real-Time Counter"] +pub mod rtc; +#[doc = "Serial Communication Interface"] +pub struct SERCOM0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SERCOM0 {} +impl SERCOM0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sercom0::RegisterBlock = 0x4200_0400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sercom0::RegisterBlock { + Self::PTR + } +} +impl Deref for SERCOM0 { + type Target = sercom0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SERCOM0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SERCOM0").finish() + } +} +#[doc = "Serial Communication Interface"] +pub mod sercom0; +#[doc = "Serial Communication Interface"] +pub struct SERCOM1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SERCOM1 {} +impl SERCOM1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sercom0::RegisterBlock = 0x4200_0800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sercom0::RegisterBlock { + Self::PTR + } +} +impl Deref for SERCOM1 { + type Target = sercom0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SERCOM1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SERCOM1").finish() + } +} +#[doc = "Serial Communication Interface"] +pub use sercom0 as sercom1; +#[doc = "Serial Communication Interface"] +pub struct SERCOM2 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SERCOM2 {} +impl SERCOM2 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sercom0::RegisterBlock = 0x4200_0c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sercom0::RegisterBlock { + Self::PTR + } +} +impl Deref for SERCOM2 { + type Target = sercom0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SERCOM2 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SERCOM2").finish() + } +} +#[doc = "Serial Communication Interface"] +pub use sercom0 as sercom2; +#[doc = "Serial Communication Interface"] +pub struct SERCOM3 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SERCOM3 {} +impl SERCOM3 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sercom0::RegisterBlock = 0x4200_1000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sercom0::RegisterBlock { + Self::PTR + } +} +impl Deref for SERCOM3 { + type Target = sercom0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SERCOM3 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SERCOM3").finish() + } +} +#[doc = "Serial Communication Interface"] +pub use sercom0 as sercom3; +#[doc = "Supply Controller"] +pub struct SUPC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SUPC {} +impl SUPC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const supc::RegisterBlock = 0x4000_1800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const supc::RegisterBlock { + Self::PTR + } +} +impl Deref for SUPC { + type Target = supc::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SUPC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SUPC").finish() + } +} +#[doc = "Supply Controller"] +pub mod supc; +#[doc = "Basic Timer Counter"] +pub struct TC0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TC0 {} +impl TC0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tc0::RegisterBlock = 0x4200_3000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tc0::RegisterBlock { + Self::PTR + } +} +impl Deref for TC0 { + type Target = tc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TC0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TC0").finish() + } +} +#[doc = "Basic Timer Counter"] +pub mod tc0; +#[doc = "Basic Timer Counter"] +pub struct TC1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TC1 {} +impl TC1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tc0::RegisterBlock = 0x4200_3400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tc0::RegisterBlock { + Self::PTR + } +} +impl Deref for TC1 { + type Target = tc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TC1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TC1").finish() + } +} +#[doc = "Basic Timer Counter"] +pub use tc0 as tc1; +#[doc = "Basic Timer Counter"] +pub struct TC2 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TC2 {} +impl TC2 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tc0::RegisterBlock = 0x4200_3800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tc0::RegisterBlock { + Self::PTR + } +} +impl Deref for TC2 { + type Target = tc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TC2 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TC2").finish() + } +} +#[doc = "Basic Timer Counter"] +pub use tc0 as tc2; +#[doc = "Basic Timer Counter"] +pub struct TC3 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TC3 {} +impl TC3 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tc0::RegisterBlock = 0x4200_3c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tc0::RegisterBlock { + Self::PTR + } +} +impl Deref for TC3 { + type Target = tc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TC3 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TC3").finish() + } +} +#[doc = "Basic Timer Counter"] +pub use tc0 as tc3; +#[doc = "Basic Timer Counter"] +pub struct TC4 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TC4 {} +impl TC4 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tc0::RegisterBlock = 0x4200_4000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tc0::RegisterBlock { + Self::PTR + } +} +impl Deref for TC4 { + type Target = tc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TC4 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TC4").finish() + } +} +#[doc = "Basic Timer Counter"] +pub use tc0 as tc4; +#[doc = "Timer Counter Control"] +pub struct TCC0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TCC0 {} +impl TCC0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tcc0::RegisterBlock = 0x4200_2400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tcc0::RegisterBlock { + Self::PTR + } +} +impl Deref for TCC0 { + type Target = tcc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TCC0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TCC0").finish() + } +} +#[doc = "Timer Counter Control"] +pub mod tcc0; +#[doc = "Timer Counter Control"] +pub struct TCC1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TCC1 {} +impl TCC1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tcc0::RegisterBlock = 0x4200_2800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tcc0::RegisterBlock { + Self::PTR + } +} +impl Deref for TCC1 { + type Target = tcc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TCC1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TCC1").finish() + } +} +#[doc = "Timer Counter Control"] +pub use tcc0 as tcc1; +#[doc = "Timer Counter Control"] +pub struct TCC2 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TCC2 {} +impl TCC2 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tcc0::RegisterBlock = 0x4200_2c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tcc0::RegisterBlock { + Self::PTR + } +} +impl Deref for TCC2 { + type Target = tcc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TCC2 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TCC2").finish() + } +} +#[doc = "Timer Counter Control"] +pub use tcc0 as tcc2; +#[doc = "Watchdog Timer"] +pub struct WDT { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for WDT {} +impl WDT { + #[doc = r"Pointer to the register block"] + pub const PTR: *const wdt::RegisterBlock = 0x4000_2000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const wdt::RegisterBlock { + Self::PTR + } +} +impl Deref for WDT { + type Target = wdt::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for WDT { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("WDT").finish() + } +} +#[doc = "Watchdog Timer"] +pub mod wdt; +#[doc = "System timer"] +pub struct SYSTICK { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SYSTICK {} +impl SYSTICK { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sys_tick::RegisterBlock = 0xe000_e010 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sys_tick::RegisterBlock { + Self::PTR + } +} +impl Deref for SYSTICK { + type Target = sys_tick::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SYSTICK { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SYSTICK").finish() + } +} +#[doc = "System timer"] +pub mod sys_tick; +#[doc = "System Control Registers"] +pub struct SYSTEMCONTROL { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SYSTEMCONTROL {} +impl SYSTEMCONTROL { + #[doc = r"Pointer to the register block"] + pub const PTR: *const system_control::RegisterBlock = 0xe000_e000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const system_control::RegisterBlock { + Self::PTR + } +} +impl Deref for SYSTEMCONTROL { + type Target = system_control::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SYSTEMCONTROL { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SYSTEMCONTROL").finish() + } +} +#[doc = "System Control Registers"] +pub mod system_control; +#[no_mangle] +static mut DEVICE_PERIPHERALS: bool = false; +#[doc = r"All the peripherals"] +#[allow(non_snake_case)] +pub struct Peripherals { + #[doc = "AC"] + pub AC: AC, + #[doc = "ADC0"] + pub ADC0: ADC0, + #[doc = "CCL"] + pub CCL: CCL, + #[doc = "DIVAS"] + pub DIVAS: DIVAS, + #[doc = "DMAC"] + pub DMAC: DMAC, + #[doc = "DSU"] + pub DSU: DSU, + #[doc = "EIC"] + pub EIC: EIC, + #[doc = "EVSYS"] + pub EVSYS: EVSYS, + #[doc = "FREQM"] + pub FREQM: FREQM, + #[doc = "GCLK"] + pub GCLK: GCLK, + #[doc = "HMATRIXHS"] + pub HMATRIXHS: HMATRIXHS, + #[doc = "MCLK"] + pub MCLK: MCLK, + #[doc = "MTB"] + pub MTB: MTB, + #[doc = "NVMCTRL"] + pub NVMCTRL: NVMCTRL, + #[doc = "OSCCTRL"] + pub OSCCTRL: OSCCTRL, + #[doc = "OSC32KCTRL"] + pub OSC32KCTRL: OSC32KCTRL, + #[doc = "PAC"] + pub PAC: PAC, + #[doc = "PM"] + pub PM: PM, + #[doc = "PORT"] + pub PORT: PORT, + #[doc = "PORT_IOBUS"] + pub PORT_IOBUS: PORT_IOBUS, + #[doc = "RSTC"] + pub RSTC: RSTC, + #[doc = "RTC"] + pub RTC: RTC, + #[doc = "SERCOM0"] + pub SERCOM0: SERCOM0, + #[doc = "SERCOM1"] + pub SERCOM1: SERCOM1, + #[doc = "SERCOM2"] + pub SERCOM2: SERCOM2, + #[doc = "SERCOM3"] + pub SERCOM3: SERCOM3, + #[doc = "SUPC"] + pub SUPC: SUPC, + #[doc = "TC0"] + pub TC0: TC0, + #[doc = "TC1"] + pub TC1: TC1, + #[doc = "TC2"] + pub TC2: TC2, + #[doc = "TC3"] + pub TC3: TC3, + #[doc = "TC4"] + pub TC4: TC4, + #[doc = "TCC0"] + pub TCC0: TCC0, + #[doc = "TCC1"] + pub TCC1: TCC1, + #[doc = "TCC2"] + pub TCC2: TCC2, + #[doc = "WDT"] + pub WDT: WDT, + #[doc = "SYSTICK"] + pub SYSTICK: SYSTICK, + #[doc = "SYSTEMCONTROL"] + pub SYSTEMCONTROL: SYSTEMCONTROL, +} +impl Peripherals { + #[doc = r"Returns all the peripherals *once*"] + #[inline] + pub fn take() -> Option { + cortex_m::interrupt::free(|_| { + if unsafe { DEVICE_PERIPHERALS } { + None + } else { + Some(unsafe { Peripherals::steal() }) + } + }) + } + #[doc = r"Unchecked version of `Peripherals::take`"] + #[inline] + pub unsafe fn steal() -> Self { + DEVICE_PERIPHERALS = true; + Peripherals { + AC: AC { + _marker: PhantomData, + }, + ADC0: ADC0 { + _marker: PhantomData, + }, + CCL: CCL { + _marker: PhantomData, + }, + DIVAS: DIVAS { + _marker: PhantomData, + }, + DMAC: DMAC { + _marker: PhantomData, + }, + DSU: DSU { + _marker: PhantomData, + }, + EIC: EIC { + _marker: PhantomData, + }, + EVSYS: EVSYS { + _marker: PhantomData, + }, + FREQM: FREQM { + _marker: PhantomData, + }, + GCLK: GCLK { + _marker: PhantomData, + }, + HMATRIXHS: HMATRIXHS { + _marker: PhantomData, + }, + MCLK: MCLK { + _marker: PhantomData, + }, + MTB: MTB { + _marker: PhantomData, + }, + NVMCTRL: NVMCTRL { + _marker: PhantomData, + }, + OSCCTRL: OSCCTRL { + _marker: PhantomData, + }, + OSC32KCTRL: OSC32KCTRL { + _marker: PhantomData, + }, + PAC: PAC { + _marker: PhantomData, + }, + PM: PM { + _marker: PhantomData, + }, + PORT: PORT { + _marker: PhantomData, + }, + PORT_IOBUS: PORT_IOBUS { + _marker: PhantomData, + }, + RSTC: RSTC { + _marker: PhantomData, + }, + RTC: RTC { + _marker: PhantomData, + }, + SERCOM0: SERCOM0 { + _marker: PhantomData, + }, + SERCOM1: SERCOM1 { + _marker: PhantomData, + }, + SERCOM2: SERCOM2 { + _marker: PhantomData, + }, + SERCOM3: SERCOM3 { + _marker: PhantomData, + }, + SUPC: SUPC { + _marker: PhantomData, + }, + TC0: TC0 { + _marker: PhantomData, + }, + TC1: TC1 { + _marker: PhantomData, + }, + TC2: TC2 { + _marker: PhantomData, + }, + TC3: TC3 { + _marker: PhantomData, + }, + TC4: TC4 { + _marker: PhantomData, + }, + TCC0: TCC0 { + _marker: PhantomData, + }, + TCC1: TCC1 { + _marker: PhantomData, + }, + TCC2: TCC2 { + _marker: PhantomData, + }, + WDT: WDT { + _marker: PhantomData, + }, + SYSTICK: SYSTICK { + _marker: PhantomData, + }, + SYSTEMCONTROL: SYSTEMCONTROL { + _marker: PhantomData, + }, + } + } +} diff --git a/pac/atsamc20j/src/mclk.rs b/pac/atsamc20j/src/mclk.rs new file mode 100644 index 000000000000..fc7efe3a584e --- /dev/null +++ b/pac/atsamc20j/src/mclk.rs @@ -0,0 +1,54 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved0: [u8; 0x01], + #[doc = "0x01 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x02 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x03 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x04 - CPU Clock Division"] + pub cpudiv: crate::Reg, + _reserved4: [u8; 0x0b], + #[doc = "0x10 - AHB Mask"] + pub ahbmask: crate::Reg, + #[doc = "0x14 - APBA Mask"] + pub apbamask: crate::Reg, + #[doc = "0x18 - APBB Mask"] + pub apbbmask: crate::Reg, + #[doc = "0x1c - APBC Mask"] + pub apbcmask: crate::Reg, +} +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "CPUDIV register accessor: an alias for `Reg`"] +pub type CPUDIV = crate::Reg; +#[doc = "CPU Clock Division"] +pub mod cpudiv; +#[doc = "AHBMASK register accessor: an alias for `Reg`"] +pub type AHBMASK = crate::Reg; +#[doc = "AHB Mask"] +pub mod ahbmask; +#[doc = "APBAMASK register accessor: an alias for `Reg`"] +pub type APBAMASK = crate::Reg; +#[doc = "APBA Mask"] +pub mod apbamask; +#[doc = "APBBMASK register accessor: an alias for `Reg`"] +pub type APBBMASK = crate::Reg; +#[doc = "APBB Mask"] +pub mod apbbmask; +#[doc = "APBCMASK register accessor: an alias for `Reg`"] +pub type APBCMASK = crate::Reg; +#[doc = "APBC Mask"] +pub mod apbcmask; diff --git a/pac/atsamc20j/src/mclk/ahbmask.rs b/pac/atsamc20j/src/mclk/ahbmask.rs new file mode 100644 index 000000000000..9366eb778bfa --- /dev/null +++ b/pac/atsamc20j/src/mclk/ahbmask.rs @@ -0,0 +1,583 @@ +#[doc = "Register `AHBMASK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `AHBMASK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `HPB0_` reader - HPB0 AHB Clock Mask"] +pub struct HPB0__R(crate::FieldReader); +impl HPB0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HPB0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HPB0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HPB0_` writer - HPB0 AHB Clock Mask"] +pub struct HPB0__W<'a> { + w: &'a mut W, +} +impl<'a> HPB0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `HPB1_` reader - HPB1 AHB Clock Mask"] +pub struct HPB1__R(crate::FieldReader); +impl HPB1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HPB1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HPB1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HPB1_` writer - HPB1 AHB Clock Mask"] +pub struct HPB1__W<'a> { + w: &'a mut W, +} +impl<'a> HPB1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `HPB2_` reader - HPB2 AHB Clock Mask"] +pub struct HPB2__R(crate::FieldReader); +impl HPB2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HPB2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HPB2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HPB2_` writer - HPB2 AHB Clock Mask"] +pub struct HPB2__W<'a> { + w: &'a mut W, +} +impl<'a> HPB2__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `DSU_` reader - DSU AHB Clock Mask"] +pub struct DSU__R(crate::FieldReader); +impl DSU__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DSU__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DSU__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DSU_` writer - DSU AHB Clock Mask"] +pub struct DSU__W<'a> { + w: &'a mut W, +} +impl<'a> DSU__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `HMATRIXHS_` reader - HMATRIXHS AHB Clock Mask"] +pub struct HMATRIXHS__R(crate::FieldReader); +impl HMATRIXHS__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HMATRIXHS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HMATRIXHS__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HMATRIXHS_` writer - HMATRIXHS AHB Clock Mask"] +pub struct HMATRIXHS__W<'a> { + w: &'a mut W, +} +impl<'a> HMATRIXHS__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `NVMCTRL_` reader - NVMCTRL AHB Clock Mask"] +pub struct NVMCTRL__R(crate::FieldReader); +impl NVMCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NVMCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NVMCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NVMCTRL_` writer - NVMCTRL AHB Clock Mask"] +pub struct NVMCTRL__W<'a> { + w: &'a mut W, +} +impl<'a> NVMCTRL__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `HSRAM_` reader - HSRAM AHB Clock Mask"] +pub struct HSRAM__R(crate::FieldReader); +impl HSRAM__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HSRAM__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HSRAM__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HSRAM_` writer - HSRAM AHB Clock Mask"] +pub struct HSRAM__W<'a> { + w: &'a mut W, +} +impl<'a> HSRAM__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `DMAC_` reader - DMAC AHB Clock Mask"] +pub struct DMAC__R(crate::FieldReader); +impl DMAC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DMAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DMAC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DMAC_` writer - DMAC AHB Clock Mask"] +pub struct DMAC__W<'a> { + w: &'a mut W, +} +impl<'a> DMAC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `PAC_` reader - PAC AHB Clock Mask"] +pub struct PAC__R(crate::FieldReader); +impl PAC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PAC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PAC_` writer - PAC AHB Clock Mask"] +pub struct PAC__W<'a> { + w: &'a mut W, +} +impl<'a> PAC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `NVMCTRL_PICACHU_` reader - NVMCTRL_PICACHU AHB Clock Mask"] +pub struct NVMCTRL_PICACHU__R(crate::FieldReader); +impl NVMCTRL_PICACHU__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NVMCTRL_PICACHU__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NVMCTRL_PICACHU__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NVMCTRL_PICACHU_` writer - NVMCTRL_PICACHU AHB Clock Mask"] +pub struct NVMCTRL_PICACHU__W<'a> { + w: &'a mut W, +} +impl<'a> NVMCTRL_PICACHU__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `DIVAS_` reader - DIVAS AHB Clock Mask"] +pub struct DIVAS__R(crate::FieldReader); +impl DIVAS__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIVAS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIVAS__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIVAS_` writer - DIVAS AHB Clock Mask"] +pub struct DIVAS__W<'a> { + w: &'a mut W, +} +impl<'a> DIVAS__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +impl R { + #[doc = "Bit 0 - HPB0 AHB Clock Mask"] + #[inline(always)] + pub fn hpb0_(&self) -> HPB0__R { + HPB0__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - HPB1 AHB Clock Mask"] + #[inline(always)] + pub fn hpb1_(&self) -> HPB1__R { + HPB1__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - HPB2 AHB Clock Mask"] + #[inline(always)] + pub fn hpb2_(&self) -> HPB2__R { + HPB2__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - DSU AHB Clock Mask"] + #[inline(always)] + pub fn dsu_(&self) -> DSU__R { + DSU__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - HMATRIXHS AHB Clock Mask"] + #[inline(always)] + pub fn hmatrixhs_(&self) -> HMATRIXHS__R { + HMATRIXHS__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - NVMCTRL AHB Clock Mask"] + #[inline(always)] + pub fn nvmctrl_(&self) -> NVMCTRL__R { + NVMCTRL__R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - HSRAM AHB Clock Mask"] + #[inline(always)] + pub fn hsram_(&self) -> HSRAM__R { + HSRAM__R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - DMAC AHB Clock Mask"] + #[inline(always)] + pub fn dmac_(&self) -> DMAC__R { + DMAC__R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 10 - PAC AHB Clock Mask"] + #[inline(always)] + pub fn pac_(&self) -> PAC__R { + PAC__R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - NVMCTRL_PICACHU AHB Clock Mask"] + #[inline(always)] + pub fn nvmctrl_picachu_(&self) -> NVMCTRL_PICACHU__R { + NVMCTRL_PICACHU__R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - DIVAS AHB Clock Mask"] + #[inline(always)] + pub fn divas_(&self) -> DIVAS__R { + DIVAS__R::new(((self.bits >> 12) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - HPB0 AHB Clock Mask"] + #[inline(always)] + pub fn hpb0_(&mut self) -> HPB0__W { + HPB0__W { w: self } + } + #[doc = "Bit 1 - HPB1 AHB Clock Mask"] + #[inline(always)] + pub fn hpb1_(&mut self) -> HPB1__W { + HPB1__W { w: self } + } + #[doc = "Bit 2 - HPB2 AHB Clock Mask"] + #[inline(always)] + pub fn hpb2_(&mut self) -> HPB2__W { + HPB2__W { w: self } + } + #[doc = "Bit 3 - DSU AHB Clock Mask"] + #[inline(always)] + pub fn dsu_(&mut self) -> DSU__W { + DSU__W { w: self } + } + #[doc = "Bit 4 - HMATRIXHS AHB Clock Mask"] + #[inline(always)] + pub fn hmatrixhs_(&mut self) -> HMATRIXHS__W { + HMATRIXHS__W { w: self } + } + #[doc = "Bit 5 - NVMCTRL AHB Clock Mask"] + #[inline(always)] + pub fn nvmctrl_(&mut self) -> NVMCTRL__W { + NVMCTRL__W { w: self } + } + #[doc = "Bit 6 - HSRAM AHB Clock Mask"] + #[inline(always)] + pub fn hsram_(&mut self) -> HSRAM__W { + HSRAM__W { w: self } + } + #[doc = "Bit 7 - DMAC AHB Clock Mask"] + #[inline(always)] + pub fn dmac_(&mut self) -> DMAC__W { + DMAC__W { w: self } + } + #[doc = "Bit 10 - PAC AHB Clock Mask"] + #[inline(always)] + pub fn pac_(&mut self) -> PAC__W { + PAC__W { w: self } + } + #[doc = "Bit 11 - NVMCTRL_PICACHU AHB Clock Mask"] + #[inline(always)] + pub fn nvmctrl_picachu_(&mut self) -> NVMCTRL_PICACHU__W { + NVMCTRL_PICACHU__W { w: self } + } + #[doc = "Bit 12 - DIVAS AHB Clock Mask"] + #[inline(always)] + pub fn divas_(&mut self) -> DIVAS__W { + DIVAS__W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "AHB Mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ahbmask](index.html) module"] +pub struct AHBMASK_SPEC; +impl crate::RegisterSpec for AHBMASK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ahbmask::R](R) reader structure"] +impl crate::Readable for AHBMASK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ahbmask::W](W) writer structure"] +impl crate::Writable for AHBMASK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets AHBMASK to value 0x1cff"] +impl crate::Resettable for AHBMASK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x1cff + } +} diff --git a/pac/atsamc20j/src/mclk/apbamask.rs b/pac/atsamc20j/src/mclk/apbamask.rs new file mode 100644 index 000000000000..3e095e73a158 --- /dev/null +++ b/pac/atsamc20j/src/mclk/apbamask.rs @@ -0,0 +1,630 @@ +#[doc = "Register `APBAMASK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `APBAMASK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PAC_` reader - PAC APB Clock Enable"] +pub struct PAC__R(crate::FieldReader); +impl PAC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PAC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PAC_` writer - PAC APB Clock Enable"] +pub struct PAC__W<'a> { + w: &'a mut W, +} +impl<'a> PAC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `PM_` reader - PM APB Clock Enable"] +pub struct PM__R(crate::FieldReader); +impl PM__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PM__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PM__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PM_` writer - PM APB Clock Enable"] +pub struct PM__W<'a> { + w: &'a mut W, +} +impl<'a> PM__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MCLK_` reader - MCLK APB Clock Enable"] +pub struct MCLK__R(crate::FieldReader); +impl MCLK__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCLK__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCLK__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCLK_` writer - MCLK APB Clock Enable"] +pub struct MCLK__W<'a> { + w: &'a mut W, +} +impl<'a> MCLK__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RSTC_` reader - RSTC APB Clock Enable"] +pub struct RSTC__R(crate::FieldReader); +impl RSTC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RSTC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RSTC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RSTC_` writer - RSTC APB Clock Enable"] +pub struct RSTC__W<'a> { + w: &'a mut W, +} +impl<'a> RSTC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `OSCCTRL_` reader - OSCCTRL APB Clock Enable"] +pub struct OSCCTRL__R(crate::FieldReader); +impl OSCCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSCCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSCCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSCCTRL_` writer - OSCCTRL APB Clock Enable"] +pub struct OSCCTRL__W<'a> { + w: &'a mut W, +} +impl<'a> OSCCTRL__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `OSC32KCTRL_` reader - OSC32KCTRL APB Clock Enable"] +pub struct OSC32KCTRL__R(crate::FieldReader); +impl OSC32KCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC32KCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC32KCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC32KCTRL_` writer - OSC32KCTRL APB Clock Enable"] +pub struct OSC32KCTRL__W<'a> { + w: &'a mut W, +} +impl<'a> OSC32KCTRL__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `SUPC_` reader - SUPC APB Clock Enable"] +pub struct SUPC__R(crate::FieldReader); +impl SUPC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SUPC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SUPC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SUPC_` writer - SUPC APB Clock Enable"] +pub struct SUPC__W<'a> { + w: &'a mut W, +} +impl<'a> SUPC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `GCLK_` reader - GCLK APB Clock Enable"] +pub struct GCLK__R(crate::FieldReader); +impl GCLK__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GCLK__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GCLK__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GCLK_` writer - GCLK APB Clock Enable"] +pub struct GCLK__W<'a> { + w: &'a mut W, +} +impl<'a> GCLK__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `WDT_` reader - WDT APB Clock Enable"] +pub struct WDT__R(crate::FieldReader); +impl WDT__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WDT__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WDT__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WDT_` writer - WDT APB Clock Enable"] +pub struct WDT__W<'a> { + w: &'a mut W, +} +impl<'a> WDT__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `RTC_` reader - RTC APB Clock Enable"] +pub struct RTC__R(crate::FieldReader); +impl RTC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RTC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RTC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RTC_` writer - RTC APB Clock Enable"] +pub struct RTC__W<'a> { + w: &'a mut W, +} +impl<'a> RTC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `EIC_` reader - EIC APB Clock Enable"] +pub struct EIC__R(crate::FieldReader); +impl EIC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EIC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EIC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EIC_` writer - EIC APB Clock Enable"] +pub struct EIC__W<'a> { + w: &'a mut W, +} +impl<'a> EIC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `FREQM_` reader - FREQM APB Clock Enable"] +pub struct FREQM__R(crate::FieldReader); +impl FREQM__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FREQM__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FREQM__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FREQM_` writer - FREQM APB Clock Enable"] +pub struct FREQM__W<'a> { + w: &'a mut W, +} +impl<'a> FREQM__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +impl R { + #[doc = "Bit 0 - PAC APB Clock Enable"] + #[inline(always)] + pub fn pac_(&self) -> PAC__R { + PAC__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - PM APB Clock Enable"] + #[inline(always)] + pub fn pm_(&self) -> PM__R { + PM__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - MCLK APB Clock Enable"] + #[inline(always)] + pub fn mclk_(&self) -> MCLK__R { + MCLK__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - RSTC APB Clock Enable"] + #[inline(always)] + pub fn rstc_(&self) -> RSTC__R { + RSTC__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - OSCCTRL APB Clock Enable"] + #[inline(always)] + pub fn oscctrl_(&self) -> OSCCTRL__R { + OSCCTRL__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - OSC32KCTRL APB Clock Enable"] + #[inline(always)] + pub fn osc32kctrl_(&self) -> OSC32KCTRL__R { + OSC32KCTRL__R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - SUPC APB Clock Enable"] + #[inline(always)] + pub fn supc_(&self) -> SUPC__R { + SUPC__R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - GCLK APB Clock Enable"] + #[inline(always)] + pub fn gclk_(&self) -> GCLK__R { + GCLK__R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - WDT APB Clock Enable"] + #[inline(always)] + pub fn wdt_(&self) -> WDT__R { + WDT__R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - RTC APB Clock Enable"] + #[inline(always)] + pub fn rtc_(&self) -> RTC__R { + RTC__R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - EIC APB Clock Enable"] + #[inline(always)] + pub fn eic_(&self) -> EIC__R { + EIC__R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - FREQM APB Clock Enable"] + #[inline(always)] + pub fn freqm_(&self) -> FREQM__R { + FREQM__R::new(((self.bits >> 11) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - PAC APB Clock Enable"] + #[inline(always)] + pub fn pac_(&mut self) -> PAC__W { + PAC__W { w: self } + } + #[doc = "Bit 1 - PM APB Clock Enable"] + #[inline(always)] + pub fn pm_(&mut self) -> PM__W { + PM__W { w: self } + } + #[doc = "Bit 2 - MCLK APB Clock Enable"] + #[inline(always)] + pub fn mclk_(&mut self) -> MCLK__W { + MCLK__W { w: self } + } + #[doc = "Bit 3 - RSTC APB Clock Enable"] + #[inline(always)] + pub fn rstc_(&mut self) -> RSTC__W { + RSTC__W { w: self } + } + #[doc = "Bit 4 - OSCCTRL APB Clock Enable"] + #[inline(always)] + pub fn oscctrl_(&mut self) -> OSCCTRL__W { + OSCCTRL__W { w: self } + } + #[doc = "Bit 5 - OSC32KCTRL APB Clock Enable"] + #[inline(always)] + pub fn osc32kctrl_(&mut self) -> OSC32KCTRL__W { + OSC32KCTRL__W { w: self } + } + #[doc = "Bit 6 - SUPC APB Clock Enable"] + #[inline(always)] + pub fn supc_(&mut self) -> SUPC__W { + SUPC__W { w: self } + } + #[doc = "Bit 7 - GCLK APB Clock Enable"] + #[inline(always)] + pub fn gclk_(&mut self) -> GCLK__W { + GCLK__W { w: self } + } + #[doc = "Bit 8 - WDT APB Clock Enable"] + #[inline(always)] + pub fn wdt_(&mut self) -> WDT__W { + WDT__W { w: self } + } + #[doc = "Bit 9 - RTC APB Clock Enable"] + #[inline(always)] + pub fn rtc_(&mut self) -> RTC__W { + RTC__W { w: self } + } + #[doc = "Bit 10 - EIC APB Clock Enable"] + #[inline(always)] + pub fn eic_(&mut self) -> EIC__W { + EIC__W { w: self } + } + #[doc = "Bit 11 - FREQM APB Clock Enable"] + #[inline(always)] + pub fn freqm_(&mut self) -> FREQM__W { + FREQM__W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "APBA Mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [apbamask](index.html) module"] +pub struct APBAMASK_SPEC; +impl crate::RegisterSpec for APBAMASK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [apbamask::R](R) reader structure"] +impl crate::Readable for APBAMASK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [apbamask::W](W) writer structure"] +impl crate::Writable for APBAMASK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets APBAMASK to value 0x0fff"] +impl crate::Resettable for APBAMASK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0fff + } +} diff --git a/pac/atsamc20j/src/mclk/apbbmask.rs b/pac/atsamc20j/src/mclk/apbbmask.rs new file mode 100644 index 000000000000..e1ec6b1f2323 --- /dev/null +++ b/pac/atsamc20j/src/mclk/apbbmask.rs @@ -0,0 +1,254 @@ +#[doc = "Register `APBBMASK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `APBBMASK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PORT_` reader - PORT APB Clock Enable"] +pub struct PORT__R(crate::FieldReader); +impl PORT__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PORT__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PORT__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PORT_` writer - PORT APB Clock Enable"] +pub struct PORT__W<'a> { + w: &'a mut W, +} +impl<'a> PORT__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `DSU_` reader - DSU APB Clock Enable"] +pub struct DSU__R(crate::FieldReader); +impl DSU__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DSU__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DSU__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DSU_` writer - DSU APB Clock Enable"] +pub struct DSU__W<'a> { + w: &'a mut W, +} +impl<'a> DSU__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `NVMCTRL_` reader - NVMCTRL APB Clock Enable"] +pub struct NVMCTRL__R(crate::FieldReader); +impl NVMCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NVMCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NVMCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NVMCTRL_` writer - NVMCTRL APB Clock Enable"] +pub struct NVMCTRL__W<'a> { + w: &'a mut W, +} +impl<'a> NVMCTRL__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `HMATRIXHS_` reader - HMATRIXHS APB Clock Enable"] +pub struct HMATRIXHS__R(crate::FieldReader); +impl HMATRIXHS__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HMATRIXHS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HMATRIXHS__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HMATRIXHS_` writer - HMATRIXHS APB Clock Enable"] +pub struct HMATRIXHS__W<'a> { + w: &'a mut W, +} +impl<'a> HMATRIXHS__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - PORT APB Clock Enable"] + #[inline(always)] + pub fn port_(&self) -> PORT__R { + PORT__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - DSU APB Clock Enable"] + #[inline(always)] + pub fn dsu_(&self) -> DSU__R { + DSU__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - NVMCTRL APB Clock Enable"] + #[inline(always)] + pub fn nvmctrl_(&self) -> NVMCTRL__R { + NVMCTRL__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 5 - HMATRIXHS APB Clock Enable"] + #[inline(always)] + pub fn hmatrixhs_(&self) -> HMATRIXHS__R { + HMATRIXHS__R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - PORT APB Clock Enable"] + #[inline(always)] + pub fn port_(&mut self) -> PORT__W { + PORT__W { w: self } + } + #[doc = "Bit 1 - DSU APB Clock Enable"] + #[inline(always)] + pub fn dsu_(&mut self) -> DSU__W { + DSU__W { w: self } + } + #[doc = "Bit 2 - NVMCTRL APB Clock Enable"] + #[inline(always)] + pub fn nvmctrl_(&mut self) -> NVMCTRL__W { + NVMCTRL__W { w: self } + } + #[doc = "Bit 5 - HMATRIXHS APB Clock Enable"] + #[inline(always)] + pub fn hmatrixhs_(&mut self) -> HMATRIXHS__W { + HMATRIXHS__W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "APBB Mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [apbbmask](index.html) module"] +pub struct APBBMASK_SPEC; +impl crate::RegisterSpec for APBBMASK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [apbbmask::R](R) reader structure"] +impl crate::Readable for APBBMASK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [apbbmask::W](W) writer structure"] +impl crate::Writable for APBBMASK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets APBBMASK to value 0x07"] +impl crate::Resettable for APBBMASK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x07 + } +} diff --git a/pac/atsamc20j/src/mclk/apbcmask.rs b/pac/atsamc20j/src/mclk/apbcmask.rs new file mode 100644 index 000000000000..64b4ce91fe5d --- /dev/null +++ b/pac/atsamc20j/src/mclk/apbcmask.rs @@ -0,0 +1,865 @@ +#[doc = "Register `APBCMASK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `APBCMASK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVSYS_` reader - EVSYS APB Clock Enable"] +pub struct EVSYS__R(crate::FieldReader); +impl EVSYS__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVSYS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVSYS__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVSYS_` writer - EVSYS APB Clock Enable"] +pub struct EVSYS__W<'a> { + w: &'a mut W, +} +impl<'a> EVSYS__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `SERCOM0_` reader - SERCOM0 APB Clock Enable"] +pub struct SERCOM0__R(crate::FieldReader); +impl SERCOM0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM0_` writer - SERCOM0 APB Clock Enable"] +pub struct SERCOM0__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SERCOM1_` reader - SERCOM1 APB Clock Enable"] +pub struct SERCOM1__R(crate::FieldReader); +impl SERCOM1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM1_` writer - SERCOM1 APB Clock Enable"] +pub struct SERCOM1__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SERCOM2_` reader - SERCOM2 APB Clock Enable"] +pub struct SERCOM2__R(crate::FieldReader); +impl SERCOM2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM2_` writer - SERCOM2 APB Clock Enable"] +pub struct SERCOM2__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM2__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `SERCOM3_` reader - SERCOM3 APB Clock Enable"] +pub struct SERCOM3__R(crate::FieldReader); +impl SERCOM3__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM3__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM3__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM3_` writer - SERCOM3 APB Clock Enable"] +pub struct SERCOM3__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM3__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `TCC0_` reader - TCC0 APB Clock Enable"] +pub struct TCC0__R(crate::FieldReader); +impl TCC0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCC0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCC0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCC0_` writer - TCC0 APB Clock Enable"] +pub struct TCC0__W<'a> { + w: &'a mut W, +} +impl<'a> TCC0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `TCC1_` reader - TCC1 APB Clock Enable"] +pub struct TCC1__R(crate::FieldReader); +impl TCC1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCC1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCC1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCC1_` writer - TCC1 APB Clock Enable"] +pub struct TCC1__W<'a> { + w: &'a mut W, +} +impl<'a> TCC1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `TCC2_` reader - TCC2 APB Clock Enable"] +pub struct TCC2__R(crate::FieldReader); +impl TCC2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCC2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCC2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCC2_` writer - TCC2 APB Clock Enable"] +pub struct TCC2__W<'a> { + w: &'a mut W, +} +impl<'a> TCC2__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `TC0_` reader - TC0 APB Clock Enable"] +pub struct TC0__R(crate::FieldReader); +impl TC0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC0_` writer - TC0 APB Clock Enable"] +pub struct TC0__W<'a> { + w: &'a mut W, +} +impl<'a> TC0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `TC1_` reader - TC1 APB Clock Enable"] +pub struct TC1__R(crate::FieldReader); +impl TC1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC1_` writer - TC1 APB Clock Enable"] +pub struct TC1__W<'a> { + w: &'a mut W, +} +impl<'a> TC1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `TC2_` reader - TC2 APB Clock Enable"] +pub struct TC2__R(crate::FieldReader); +impl TC2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC2_` writer - TC2 APB Clock Enable"] +pub struct TC2__W<'a> { + w: &'a mut W, +} +impl<'a> TC2__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `TC3_` reader - TC3 APB Clock Enable"] +pub struct TC3__R(crate::FieldReader); +impl TC3__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC3__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC3__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC3_` writer - TC3 APB Clock Enable"] +pub struct TC3__W<'a> { + w: &'a mut W, +} +impl<'a> TC3__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `TC4_` reader - TC4 APB Clock Enable"] +pub struct TC4__R(crate::FieldReader); +impl TC4__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC4__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC4__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC4_` writer - TC4 APB Clock Enable"] +pub struct TC4__W<'a> { + w: &'a mut W, +} +impl<'a> TC4__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `ADC0_` reader - ADC0 APB Clock Enable"] +pub struct ADC0__R(crate::FieldReader); +impl ADC0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ADC0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADC0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADC0_` writer - ADC0 APB Clock Enable"] +pub struct ADC0__W<'a> { + w: &'a mut W, +} +impl<'a> ADC0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `AC_` reader - AC APB Clock Enable"] +pub struct AC__R(crate::FieldReader); +impl AC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AC_` writer - AC APB Clock Enable"] +pub struct AC__W<'a> { + w: &'a mut W, +} +impl<'a> AC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `PTC_` reader - PTC APB Clock Enable"] +pub struct PTC__R(crate::FieldReader); +impl PTC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PTC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PTC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PTC_` writer - PTC APB Clock Enable"] +pub struct PTC__W<'a> { + w: &'a mut W, +} +impl<'a> PTC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `CCL_` reader - CCL APB Clock Enable"] +pub struct CCL__R(crate::FieldReader); +impl CCL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCL_` writer - CCL APB Clock Enable"] +pub struct CCL__W<'a> { + w: &'a mut W, +} +impl<'a> CCL__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +impl R { + #[doc = "Bit 0 - EVSYS APB Clock Enable"] + #[inline(always)] + pub fn evsys_(&self) -> EVSYS__R { + EVSYS__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM0 APB Clock Enable"] + #[inline(always)] + pub fn sercom0_(&self) -> SERCOM0__R { + SERCOM0__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - SERCOM1 APB Clock Enable"] + #[inline(always)] + pub fn sercom1_(&self) -> SERCOM1__R { + SERCOM1__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - SERCOM2 APB Clock Enable"] + #[inline(always)] + pub fn sercom2_(&self) -> SERCOM2__R { + SERCOM2__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - SERCOM3 APB Clock Enable"] + #[inline(always)] + pub fn sercom3_(&self) -> SERCOM3__R { + SERCOM3__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 9 - TCC0 APB Clock Enable"] + #[inline(always)] + pub fn tcc0_(&self) -> TCC0__R { + TCC0__R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - TCC1 APB Clock Enable"] + #[inline(always)] + pub fn tcc1_(&self) -> TCC1__R { + TCC1__R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - TCC2 APB Clock Enable"] + #[inline(always)] + pub fn tcc2_(&self) -> TCC2__R { + TCC2__R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - TC0 APB Clock Enable"] + #[inline(always)] + pub fn tc0_(&self) -> TC0__R { + TC0__R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - TC1 APB Clock Enable"] + #[inline(always)] + pub fn tc1_(&self) -> TC1__R { + TC1__R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - TC2 APB Clock Enable"] + #[inline(always)] + pub fn tc2_(&self) -> TC2__R { + TC2__R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - TC3 APB Clock Enable"] + #[inline(always)] + pub fn tc3_(&self) -> TC3__R { + TC3__R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - TC4 APB Clock Enable"] + #[inline(always)] + pub fn tc4_(&self) -> TC4__R { + TC4__R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - ADC0 APB Clock Enable"] + #[inline(always)] + pub fn adc0_(&self) -> ADC0__R { + ADC0__R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 20 - AC APB Clock Enable"] + #[inline(always)] + pub fn ac_(&self) -> AC__R { + AC__R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 22 - PTC APB Clock Enable"] + #[inline(always)] + pub fn ptc_(&self) -> PTC__R { + PTC__R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - CCL APB Clock Enable"] + #[inline(always)] + pub fn ccl_(&self) -> CCL__R { + CCL__R::new(((self.bits >> 23) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - EVSYS APB Clock Enable"] + #[inline(always)] + pub fn evsys_(&mut self) -> EVSYS__W { + EVSYS__W { w: self } + } + #[doc = "Bit 1 - SERCOM0 APB Clock Enable"] + #[inline(always)] + pub fn sercom0_(&mut self) -> SERCOM0__W { + SERCOM0__W { w: self } + } + #[doc = "Bit 2 - SERCOM1 APB Clock Enable"] + #[inline(always)] + pub fn sercom1_(&mut self) -> SERCOM1__W { + SERCOM1__W { w: self } + } + #[doc = "Bit 3 - SERCOM2 APB Clock Enable"] + #[inline(always)] + pub fn sercom2_(&mut self) -> SERCOM2__W { + SERCOM2__W { w: self } + } + #[doc = "Bit 4 - SERCOM3 APB Clock Enable"] + #[inline(always)] + pub fn sercom3_(&mut self) -> SERCOM3__W { + SERCOM3__W { w: self } + } + #[doc = "Bit 9 - TCC0 APB Clock Enable"] + #[inline(always)] + pub fn tcc0_(&mut self) -> TCC0__W { + TCC0__W { w: self } + } + #[doc = "Bit 10 - TCC1 APB Clock Enable"] + #[inline(always)] + pub fn tcc1_(&mut self) -> TCC1__W { + TCC1__W { w: self } + } + #[doc = "Bit 11 - TCC2 APB Clock Enable"] + #[inline(always)] + pub fn tcc2_(&mut self) -> TCC2__W { + TCC2__W { w: self } + } + #[doc = "Bit 12 - TC0 APB Clock Enable"] + #[inline(always)] + pub fn tc0_(&mut self) -> TC0__W { + TC0__W { w: self } + } + #[doc = "Bit 13 - TC1 APB Clock Enable"] + #[inline(always)] + pub fn tc1_(&mut self) -> TC1__W { + TC1__W { w: self } + } + #[doc = "Bit 14 - TC2 APB Clock Enable"] + #[inline(always)] + pub fn tc2_(&mut self) -> TC2__W { + TC2__W { w: self } + } + #[doc = "Bit 15 - TC3 APB Clock Enable"] + #[inline(always)] + pub fn tc3_(&mut self) -> TC3__W { + TC3__W { w: self } + } + #[doc = "Bit 16 - TC4 APB Clock Enable"] + #[inline(always)] + pub fn tc4_(&mut self) -> TC4__W { + TC4__W { w: self } + } + #[doc = "Bit 17 - ADC0 APB Clock Enable"] + #[inline(always)] + pub fn adc0_(&mut self) -> ADC0__W { + ADC0__W { w: self } + } + #[doc = "Bit 20 - AC APB Clock Enable"] + #[inline(always)] + pub fn ac_(&mut self) -> AC__W { + AC__W { w: self } + } + #[doc = "Bit 22 - PTC APB Clock Enable"] + #[inline(always)] + pub fn ptc_(&mut self) -> PTC__W { + PTC__W { w: self } + } + #[doc = "Bit 23 - CCL APB Clock Enable"] + #[inline(always)] + pub fn ccl_(&mut self) -> CCL__W { + CCL__W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "APBC Mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [apbcmask](index.html) module"] +pub struct APBCMASK_SPEC; +impl crate::RegisterSpec for APBCMASK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [apbcmask::R](R) reader structure"] +impl crate::Readable for APBCMASK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [apbcmask::W](W) writer structure"] +impl crate::Writable for APBCMASK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets APBCMASK to value 0"] +impl crate::Resettable for APBCMASK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/mclk/cpudiv.rs b/pac/atsamc20j/src/mclk/cpudiv.rs new file mode 100644 index 000000000000..a21fdae21357 --- /dev/null +++ b/pac/atsamc20j/src/mclk/cpudiv.rs @@ -0,0 +1,230 @@ +#[doc = "Register `CPUDIV` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CPUDIV` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "CPU Clock Division Factor\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CPUDIV_A { + #[doc = "1: Divide by 1"] + DIV1 = 1, + #[doc = "2: Divide by 2"] + DIV2 = 2, + #[doc = "4: Divide by 4"] + DIV4 = 4, + #[doc = "8: Divide by 8"] + DIV8 = 8, + #[doc = "16: Divide by 16"] + DIV16 = 16, + #[doc = "32: Divide by 32"] + DIV32 = 32, + #[doc = "64: Divide by 64"] + DIV64 = 64, + #[doc = "128: Divide by 128"] + DIV128 = 128, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CPUDIV_A) -> Self { + variant as _ + } +} +#[doc = "Field `CPUDIV` reader - CPU Clock Division Factor"] +pub struct CPUDIV_R(crate::FieldReader); +impl CPUDIV_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CPUDIV_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 1 => Some(CPUDIV_A::DIV1), + 2 => Some(CPUDIV_A::DIV2), + 4 => Some(CPUDIV_A::DIV4), + 8 => Some(CPUDIV_A::DIV8), + 16 => Some(CPUDIV_A::DIV16), + 32 => Some(CPUDIV_A::DIV32), + 64 => Some(CPUDIV_A::DIV64), + 128 => Some(CPUDIV_A::DIV128), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == CPUDIV_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == CPUDIV_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == CPUDIV_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == CPUDIV_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == CPUDIV_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == CPUDIV_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == CPUDIV_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == CPUDIV_A::DIV128 + } +} +impl core::ops::Deref for CPUDIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPUDIV` writer - CPU Clock Division Factor"] +pub struct CPUDIV_W<'a> { + w: &'a mut W, +} +impl<'a> CPUDIV_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CPUDIV_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Divide by 1"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV1) + } + #[doc = "Divide by 2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV2) + } + #[doc = "Divide by 4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV4) + } + #[doc = "Divide by 8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV8) + } + #[doc = "Divide by 16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV16) + } + #[doc = "Divide by 32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV32) + } + #[doc = "Divide by 64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV64) + } + #[doc = "Divide by 128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV128) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - CPU Clock Division Factor"] + #[inline(always)] + pub fn cpudiv(&self) -> CPUDIV_R { + CPUDIV_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - CPU Clock Division Factor"] + #[inline(always)] + pub fn cpudiv(&mut self) -> CPUDIV_W { + CPUDIV_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CPU Clock Division\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cpudiv](index.html) module"] +pub struct CPUDIV_SPEC; +impl crate::RegisterSpec for CPUDIV_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [cpudiv::R](R) reader structure"] +impl crate::Readable for CPUDIV_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cpudiv::W](W) writer structure"] +impl crate::Writable for CPUDIV_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CPUDIV to value 0x01"] +impl crate::Resettable for CPUDIV_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pac/atsamc20j/src/mclk/intenclr.rs b/pac/atsamc20j/src/mclk/intenclr.rs new file mode 100644 index 000000000000..14feb632dbb7 --- /dev/null +++ b/pac/atsamc20j/src/mclk/intenclr.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CKRDY` reader - Clock Ready Interrupt Enable"] +pub struct CKRDY_R(crate::FieldReader); +impl CKRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CKRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CKRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CKRDY` writer - Clock Ready Interrupt Enable"] +pub struct CKRDY_W<'a> { + w: &'a mut W, +} +impl<'a> CKRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Clock Ready Interrupt Enable"] + #[inline(always)] + pub fn ckrdy(&self) -> CKRDY_R { + CKRDY_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Clock Ready Interrupt Enable"] + #[inline(always)] + pub fn ckrdy(&mut self) -> CKRDY_W { + CKRDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/mclk/intenset.rs b/pac/atsamc20j/src/mclk/intenset.rs new file mode 100644 index 000000000000..f01fcc316d93 --- /dev/null +++ b/pac/atsamc20j/src/mclk/intenset.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CKRDY` reader - Clock Ready Interrupt Enable"] +pub struct CKRDY_R(crate::FieldReader); +impl CKRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CKRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CKRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CKRDY` writer - Clock Ready Interrupt Enable"] +pub struct CKRDY_W<'a> { + w: &'a mut W, +} +impl<'a> CKRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Clock Ready Interrupt Enable"] + #[inline(always)] + pub fn ckrdy(&self) -> CKRDY_R { + CKRDY_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Clock Ready Interrupt Enable"] + #[inline(always)] + pub fn ckrdy(&mut self) -> CKRDY_W { + CKRDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/mclk/intflag.rs b/pac/atsamc20j/src/mclk/intflag.rs new file mode 100644 index 000000000000..cf421d4ac61a --- /dev/null +++ b/pac/atsamc20j/src/mclk/intflag.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CKRDY` reader - Clock Ready"] +pub struct CKRDY_R(crate::FieldReader); +impl CKRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CKRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CKRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CKRDY` writer - Clock Ready"] +pub struct CKRDY_W<'a> { + w: &'a mut W, +} +impl<'a> CKRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Clock Ready"] + #[inline(always)] + pub fn ckrdy(&self) -> CKRDY_R { + CKRDY_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Clock Ready"] + #[inline(always)] + pub fn ckrdy(&mut self) -> CKRDY_W { + CKRDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0x01"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pac/atsamc20j/src/mtb.rs b/pac/atsamc20j/src/mtb.rs new file mode 100644 index 000000000000..01be005c0fb9 --- /dev/null +++ b/pac/atsamc20j/src/mtb.rs @@ -0,0 +1,158 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - MTB Position"] + pub position: crate::Reg, + #[doc = "0x04 - MTB Master"] + pub master: crate::Reg, + #[doc = "0x08 - MTB Flow"] + pub flow: crate::Reg, + #[doc = "0x0c - MTB Base"] + pub base: crate::Reg, + _reserved4: [u8; 0x0ef0], + #[doc = "0xf00 - MTB Integration Mode Control"] + pub itctrl: crate::Reg, + _reserved5: [u8; 0x9c], + #[doc = "0xfa0 - MTB Claim Set"] + pub claimset: crate::Reg, + #[doc = "0xfa4 - MTB Claim Clear"] + pub claimclr: crate::Reg, + _reserved7: [u8; 0x08], + #[doc = "0xfb0 - MTB Lock Access"] + pub lockaccess: crate::Reg, + #[doc = "0xfb4 - MTB Lock Status"] + pub lockstatus: crate::Reg, + #[doc = "0xfb8 - MTB Authentication Status"] + pub authstatus: crate::Reg, + #[doc = "0xfbc - MTB Device Architecture"] + pub devarch: crate::Reg, + _reserved11: [u8; 0x08], + #[doc = "0xfc8 - MTB Device Configuration"] + pub devid: crate::Reg, + #[doc = "0xfcc - MTB Device Type"] + pub devtype: crate::Reg, + #[doc = "0xfd0 - Peripheral Identification 4"] + pub pid4: crate::Reg, + #[doc = "0xfd4 - Peripheral Identification 5"] + pub pid5: crate::Reg, + #[doc = "0xfd8 - Peripheral Identification 6"] + pub pid6: crate::Reg, + #[doc = "0xfdc - Peripheral Identification 7"] + pub pid7: crate::Reg, + #[doc = "0xfe0 - Peripheral Identification 0"] + pub pid0: crate::Reg, + #[doc = "0xfe4 - Peripheral Identification 1"] + pub pid1: crate::Reg, + #[doc = "0xfe8 - Peripheral Identification 2"] + pub pid2: crate::Reg, + #[doc = "0xfec - Peripheral Identification 3"] + pub pid3: crate::Reg, + #[doc = "0xff0 - Component Identification 0"] + pub cid0: crate::Reg, + #[doc = "0xff4 - Component Identification 1"] + pub cid1: crate::Reg, + #[doc = "0xff8 - Component Identification 2"] + pub cid2: crate::Reg, + #[doc = "0xffc - Component Identification 3"] + pub cid3: crate::Reg, +} +#[doc = "POSITION register accessor: an alias for `Reg`"] +pub type POSITION = crate::Reg; +#[doc = "MTB Position"] +pub mod position; +#[doc = "MASTER register accessor: an alias for `Reg`"] +pub type MASTER = crate::Reg; +#[doc = "MTB Master"] +pub mod master; +#[doc = "FLOW register accessor: an alias for `Reg`"] +pub type FLOW = crate::Reg; +#[doc = "MTB Flow"] +pub mod flow; +#[doc = "BASE register accessor: an alias for `Reg`"] +pub type BASE = crate::Reg; +#[doc = "MTB Base"] +pub mod base; +#[doc = "ITCTRL register accessor: an alias for `Reg`"] +pub type ITCTRL = crate::Reg; +#[doc = "MTB Integration Mode Control"] +pub mod itctrl; +#[doc = "CLAIMSET register accessor: an alias for `Reg`"] +pub type CLAIMSET = crate::Reg; +#[doc = "MTB Claim Set"] +pub mod claimset; +#[doc = "CLAIMCLR register accessor: an alias for `Reg`"] +pub type CLAIMCLR = crate::Reg; +#[doc = "MTB Claim Clear"] +pub mod claimclr; +#[doc = "LOCKACCESS register accessor: an alias for `Reg`"] +pub type LOCKACCESS = crate::Reg; +#[doc = "MTB Lock Access"] +pub mod lockaccess; +#[doc = "LOCKSTATUS register accessor: an alias for `Reg`"] +pub type LOCKSTATUS = crate::Reg; +#[doc = "MTB Lock Status"] +pub mod lockstatus; +#[doc = "AUTHSTATUS register accessor: an alias for `Reg`"] +pub type AUTHSTATUS = crate::Reg; +#[doc = "MTB Authentication Status"] +pub mod authstatus; +#[doc = "DEVARCH register accessor: an alias for `Reg`"] +pub type DEVARCH = crate::Reg; +#[doc = "MTB Device Architecture"] +pub mod devarch; +#[doc = "DEVID register accessor: an alias for `Reg`"] +pub type DEVID = crate::Reg; +#[doc = "MTB Device Configuration"] +pub mod devid; +#[doc = "DEVTYPE register accessor: an alias for `Reg`"] +pub type DEVTYPE = crate::Reg; +#[doc = "MTB Device Type"] +pub mod devtype; +#[doc = "PID4 register accessor: an alias for `Reg`"] +pub type PID4 = crate::Reg; +#[doc = "Peripheral Identification 4"] +pub mod pid4; +#[doc = "PID5 register accessor: an alias for `Reg`"] +pub type PID5 = crate::Reg; +#[doc = "Peripheral Identification 5"] +pub mod pid5; +#[doc = "PID6 register accessor: an alias for `Reg`"] +pub type PID6 = crate::Reg; +#[doc = "Peripheral Identification 6"] +pub mod pid6; +#[doc = "PID7 register accessor: an alias for `Reg`"] +pub type PID7 = crate::Reg; +#[doc = "Peripheral Identification 7"] +pub mod pid7; +#[doc = "PID0 register accessor: an alias for `Reg`"] +pub type PID0 = crate::Reg; +#[doc = "Peripheral Identification 0"] +pub mod pid0; +#[doc = "PID1 register accessor: an alias for `Reg`"] +pub type PID1 = crate::Reg; +#[doc = "Peripheral Identification 1"] +pub mod pid1; +#[doc = "PID2 register accessor: an alias for `Reg`"] +pub type PID2 = crate::Reg; +#[doc = "Peripheral Identification 2"] +pub mod pid2; +#[doc = "PID3 register accessor: an alias for `Reg`"] +pub type PID3 = crate::Reg; +#[doc = "Peripheral Identification 3"] +pub mod pid3; +#[doc = "CID0 register accessor: an alias for `Reg`"] +pub type CID0 = crate::Reg; +#[doc = "Component Identification 0"] +pub mod cid0; +#[doc = "CID1 register accessor: an alias for `Reg`"] +pub type CID1 = crate::Reg; +#[doc = "Component Identification 1"] +pub mod cid1; +#[doc = "CID2 register accessor: an alias for `Reg`"] +pub type CID2 = crate::Reg; +#[doc = "Component Identification 2"] +pub mod cid2; +#[doc = "CID3 register accessor: an alias for `Reg`"] +pub type CID3 = crate::Reg; +#[doc = "Component Identification 3"] +pub mod cid3; diff --git a/pac/atsamc20j/src/mtb/authstatus.rs b/pac/atsamc20j/src/mtb/authstatus.rs new file mode 100644 index 000000000000..6fe441e0554d --- /dev/null +++ b/pac/atsamc20j/src/mtb/authstatus.rs @@ -0,0 +1,31 @@ +#[doc = "Register `AUTHSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "MTB Authentication Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [authstatus](index.html) module"] +pub struct AUTHSTATUS_SPEC; +impl crate::RegisterSpec for AUTHSTATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [authstatus::R](R) reader structure"] +impl crate::Readable for AUTHSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets AUTHSTATUS to value 0"] +impl crate::Resettable for AUTHSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/mtb/base.rs b/pac/atsamc20j/src/mtb/base.rs new file mode 100644 index 000000000000..f59b5a97a398 --- /dev/null +++ b/pac/atsamc20j/src/mtb/base.rs @@ -0,0 +1,31 @@ +#[doc = "Register `BASE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "MTB Base\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [base](index.html) module"] +pub struct BASE_SPEC; +impl crate::RegisterSpec for BASE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [base::R](R) reader structure"] +impl crate::Readable for BASE_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets BASE to value 0"] +impl crate::Resettable for BASE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/mtb/cid0.rs b/pac/atsamc20j/src/mtb/cid0.rs new file mode 100644 index 000000000000..e03bd35fa470 --- /dev/null +++ b/pac/atsamc20j/src/mtb/cid0.rs @@ -0,0 +1,31 @@ +#[doc = "Register `CID0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Component Identification 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid0](index.html) module"] +pub struct CID0_SPEC; +impl crate::RegisterSpec for CID0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid0::R](R) reader structure"] +impl crate::Readable for CID0_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID0 to value 0"] +impl crate::Resettable for CID0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/mtb/cid1.rs b/pac/atsamc20j/src/mtb/cid1.rs new file mode 100644 index 000000000000..1cafc8e0fb9a --- /dev/null +++ b/pac/atsamc20j/src/mtb/cid1.rs @@ -0,0 +1,31 @@ +#[doc = "Register `CID1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Component Identification 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid1](index.html) module"] +pub struct CID1_SPEC; +impl crate::RegisterSpec for CID1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid1::R](R) reader structure"] +impl crate::Readable for CID1_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID1 to value 0"] +impl crate::Resettable for CID1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/mtb/cid2.rs b/pac/atsamc20j/src/mtb/cid2.rs new file mode 100644 index 000000000000..6a91e4e23206 --- /dev/null +++ b/pac/atsamc20j/src/mtb/cid2.rs @@ -0,0 +1,31 @@ +#[doc = "Register `CID2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Component Identification 2\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid2](index.html) module"] +pub struct CID2_SPEC; +impl crate::RegisterSpec for CID2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid2::R](R) reader structure"] +impl crate::Readable for CID2_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID2 to value 0"] +impl crate::Resettable for CID2_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/mtb/cid3.rs b/pac/atsamc20j/src/mtb/cid3.rs new file mode 100644 index 000000000000..726290f4ffed --- /dev/null +++ b/pac/atsamc20j/src/mtb/cid3.rs @@ -0,0 +1,31 @@ +#[doc = "Register `CID3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Component Identification 3\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid3](index.html) module"] +pub struct CID3_SPEC; +impl crate::RegisterSpec for CID3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid3::R](R) reader structure"] +impl crate::Readable for CID3_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID3 to value 0"] +impl crate::Resettable for CID3_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/mtb/claimclr.rs b/pac/atsamc20j/src/mtb/claimclr.rs new file mode 100644 index 000000000000..7d0fa5d487b2 --- /dev/null +++ b/pac/atsamc20j/src/mtb/claimclr.rs @@ -0,0 +1,64 @@ +#[doc = "Register `CLAIMCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CLAIMCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MTB Claim Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [claimclr](index.html) module"] +pub struct CLAIMCLR_SPEC; +impl crate::RegisterSpec for CLAIMCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [claimclr::R](R) reader structure"] +impl crate::Readable for CLAIMCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [claimclr::W](W) writer structure"] +impl crate::Writable for CLAIMCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CLAIMCLR to value 0"] +impl crate::Resettable for CLAIMCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/mtb/claimset.rs b/pac/atsamc20j/src/mtb/claimset.rs new file mode 100644 index 000000000000..d5e8ffaa4846 --- /dev/null +++ b/pac/atsamc20j/src/mtb/claimset.rs @@ -0,0 +1,64 @@ +#[doc = "Register `CLAIMSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CLAIMSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MTB Claim Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [claimset](index.html) module"] +pub struct CLAIMSET_SPEC; +impl crate::RegisterSpec for CLAIMSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [claimset::R](R) reader structure"] +impl crate::Readable for CLAIMSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [claimset::W](W) writer structure"] +impl crate::Writable for CLAIMSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CLAIMSET to value 0"] +impl crate::Resettable for CLAIMSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/mtb/devarch.rs b/pac/atsamc20j/src/mtb/devarch.rs new file mode 100644 index 000000000000..b79480753d5e --- /dev/null +++ b/pac/atsamc20j/src/mtb/devarch.rs @@ -0,0 +1,31 @@ +#[doc = "Register `DEVARCH` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "MTB Device Architecture\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [devarch](index.html) module"] +pub struct DEVARCH_SPEC; +impl crate::RegisterSpec for DEVARCH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [devarch::R](R) reader structure"] +impl crate::Readable for DEVARCH_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DEVARCH to value 0"] +impl crate::Resettable for DEVARCH_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/mtb/devid.rs b/pac/atsamc20j/src/mtb/devid.rs new file mode 100644 index 000000000000..21c15d952032 --- /dev/null +++ b/pac/atsamc20j/src/mtb/devid.rs @@ -0,0 +1,31 @@ +#[doc = "Register `DEVID` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "MTB Device Configuration\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [devid](index.html) module"] +pub struct DEVID_SPEC; +impl crate::RegisterSpec for DEVID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [devid::R](R) reader structure"] +impl crate::Readable for DEVID_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DEVID to value 0"] +impl crate::Resettable for DEVID_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/mtb/devtype.rs b/pac/atsamc20j/src/mtb/devtype.rs new file mode 100644 index 000000000000..c00d66b98a2f --- /dev/null +++ b/pac/atsamc20j/src/mtb/devtype.rs @@ -0,0 +1,31 @@ +#[doc = "Register `DEVTYPE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "MTB Device Type\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [devtype](index.html) module"] +pub struct DEVTYPE_SPEC; +impl crate::RegisterSpec for DEVTYPE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [devtype::R](R) reader structure"] +impl crate::Readable for DEVTYPE_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DEVTYPE to value 0"] +impl crate::Resettable for DEVTYPE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/mtb/flow.rs b/pac/atsamc20j/src/mtb/flow.rs new file mode 100644 index 000000000000..1b94efdb89b8 --- /dev/null +++ b/pac/atsamc20j/src/mtb/flow.rs @@ -0,0 +1,197 @@ +#[doc = "Register `FLOW` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FLOW` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `AUTOSTOP` reader - Auto Stop Tracing"] +pub struct AUTOSTOP_R(crate::FieldReader); +impl AUTOSTOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AUTOSTOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AUTOSTOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AUTOSTOP` writer - Auto Stop Tracing"] +pub struct AUTOSTOP_W<'a> { + w: &'a mut W, +} +impl<'a> AUTOSTOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `AUTOHALT` reader - Auto Halt Request"] +pub struct AUTOHALT_R(crate::FieldReader); +impl AUTOHALT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AUTOHALT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AUTOHALT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AUTOHALT` writer - Auto Halt Request"] +pub struct AUTOHALT_W<'a> { + w: &'a mut W, +} +impl<'a> AUTOHALT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WATERMARK` reader - Watermark value"] +pub struct WATERMARK_R(crate::FieldReader); +impl WATERMARK_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + WATERMARK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WATERMARK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WATERMARK` writer - Watermark value"] +pub struct WATERMARK_W<'a> { + w: &'a mut W, +} +impl<'a> WATERMARK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1fff_ffff << 3)) | ((value as u32 & 0x1fff_ffff) << 3); + self.w + } +} +impl R { + #[doc = "Bit 0 - Auto Stop Tracing"] + #[inline(always)] + pub fn autostop(&self) -> AUTOSTOP_R { + AUTOSTOP_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Auto Halt Request"] + #[inline(always)] + pub fn autohalt(&self) -> AUTOHALT_R { + AUTOHALT_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 3:31 - Watermark value"] + #[inline(always)] + pub fn watermark(&self) -> WATERMARK_R { + WATERMARK_R::new(((self.bits >> 3) & 0x1fff_ffff) as u32) + } +} +impl W { + #[doc = "Bit 0 - Auto Stop Tracing"] + #[inline(always)] + pub fn autostop(&mut self) -> AUTOSTOP_W { + AUTOSTOP_W { w: self } + } + #[doc = "Bit 1 - Auto Halt Request"] + #[inline(always)] + pub fn autohalt(&mut self) -> AUTOHALT_W { + AUTOHALT_W { w: self } + } + #[doc = "Bits 3:31 - Watermark value"] + #[inline(always)] + pub fn watermark(&mut self) -> WATERMARK_W { + WATERMARK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MTB Flow\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [flow](index.html) module"] +pub struct FLOW_SPEC; +impl crate::RegisterSpec for FLOW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [flow::R](R) reader structure"] +impl crate::Readable for FLOW_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [flow::W](W) writer structure"] +impl crate::Writable for FLOW_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets FLOW to value 0"] +impl crate::Resettable for FLOW_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/mtb/itctrl.rs b/pac/atsamc20j/src/mtb/itctrl.rs new file mode 100644 index 000000000000..a48364e0b062 --- /dev/null +++ b/pac/atsamc20j/src/mtb/itctrl.rs @@ -0,0 +1,64 @@ +#[doc = "Register `ITCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ITCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MTB Integration Mode Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [itctrl](index.html) module"] +pub struct ITCTRL_SPEC; +impl crate::RegisterSpec for ITCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [itctrl::R](R) reader structure"] +impl crate::Readable for ITCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [itctrl::W](W) writer structure"] +impl crate::Writable for ITCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ITCTRL to value 0"] +impl crate::Resettable for ITCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/mtb/lockaccess.rs b/pac/atsamc20j/src/mtb/lockaccess.rs new file mode 100644 index 000000000000..0400690beade --- /dev/null +++ b/pac/atsamc20j/src/mtb/lockaccess.rs @@ -0,0 +1,64 @@ +#[doc = "Register `LOCKACCESS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `LOCKACCESS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MTB Lock Access\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lockaccess](index.html) module"] +pub struct LOCKACCESS_SPEC; +impl crate::RegisterSpec for LOCKACCESS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [lockaccess::R](R) reader structure"] +impl crate::Readable for LOCKACCESS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [lockaccess::W](W) writer structure"] +impl crate::Writable for LOCKACCESS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets LOCKACCESS to value 0"] +impl crate::Resettable for LOCKACCESS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/mtb/lockstatus.rs b/pac/atsamc20j/src/mtb/lockstatus.rs new file mode 100644 index 000000000000..0c68410c6944 --- /dev/null +++ b/pac/atsamc20j/src/mtb/lockstatus.rs @@ -0,0 +1,31 @@ +#[doc = "Register `LOCKSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "MTB Lock Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lockstatus](index.html) module"] +pub struct LOCKSTATUS_SPEC; +impl crate::RegisterSpec for LOCKSTATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [lockstatus::R](R) reader structure"] +impl crate::Readable for LOCKSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets LOCKSTATUS to value 0"] +impl crate::Resettable for LOCKSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/mtb/master.rs b/pac/atsamc20j/src/mtb/master.rs new file mode 100644 index 000000000000..0190ca1ce909 --- /dev/null +++ b/pac/atsamc20j/src/mtb/master.rs @@ -0,0 +1,385 @@ +#[doc = "Register `MASTER` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MASTER` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MASK` reader - Maximum Value of the Trace Buffer in SRAM"] +pub struct MASK_R(crate::FieldReader); +impl MASK_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MASK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MASK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MASK` writer - Maximum Value of the Trace Buffer in SRAM"] +pub struct MASK_W<'a> { + w: &'a mut W, +} +impl<'a> MASK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f); + self.w + } +} +#[doc = "Field `TSTARTEN` reader - Trace Start Input Enable"] +pub struct TSTARTEN_R(crate::FieldReader); +impl TSTARTEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSTARTEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSTARTEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSTARTEN` writer - Trace Start Input Enable"] +pub struct TSTARTEN_W<'a> { + w: &'a mut W, +} +impl<'a> TSTARTEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `TSTOPEN` reader - Trace Stop Input Enable"] +pub struct TSTOPEN_R(crate::FieldReader); +impl TSTOPEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSTOPEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSTOPEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSTOPEN` writer - Trace Stop Input Enable"] +pub struct TSTOPEN_W<'a> { + w: &'a mut W, +} +impl<'a> TSTOPEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `SFRWPRIV` reader - Special Function Register Write Privilege"] +pub struct SFRWPRIV_R(crate::FieldReader); +impl SFRWPRIV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SFRWPRIV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SFRWPRIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SFRWPRIV` writer - Special Function Register Write Privilege"] +pub struct SFRWPRIV_W<'a> { + w: &'a mut W, +} +impl<'a> SFRWPRIV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `RAMPRIV` reader - SRAM Privilege"] +pub struct RAMPRIV_R(crate::FieldReader); +impl RAMPRIV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RAMPRIV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RAMPRIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RAMPRIV` writer - SRAM Privilege"] +pub struct RAMPRIV_W<'a> { + w: &'a mut W, +} +impl<'a> RAMPRIV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `HALTREQ` reader - Halt Request"] +pub struct HALTREQ_R(crate::FieldReader); +impl HALTREQ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HALTREQ_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HALTREQ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HALTREQ` writer - Halt Request"] +pub struct HALTREQ_W<'a> { + w: &'a mut W, +} +impl<'a> HALTREQ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `EN` reader - Main Trace Enable"] +pub struct EN_R(crate::FieldReader); +impl EN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EN` writer - Main Trace Enable"] +pub struct EN_W<'a> { + w: &'a mut W, +} +impl<'a> EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Maximum Value of the Trace Buffer in SRAM"] + #[inline(always)] + pub fn mask(&self) -> MASK_R { + MASK_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bit 5 - Trace Start Input Enable"] + #[inline(always)] + pub fn tstarten(&self) -> TSTARTEN_R { + TSTARTEN_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Trace Stop Input Enable"] + #[inline(always)] + pub fn tstopen(&self) -> TSTOPEN_R { + TSTOPEN_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Special Function Register Write Privilege"] + #[inline(always)] + pub fn sfrwpriv(&self) -> SFRWPRIV_R { + SFRWPRIV_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - SRAM Privilege"] + #[inline(always)] + pub fn rampriv(&self) -> RAMPRIV_R { + RAMPRIV_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Halt Request"] + #[inline(always)] + pub fn haltreq(&self) -> HALTREQ_R { + HALTREQ_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 31 - Main Trace Enable"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Maximum Value of the Trace Buffer in SRAM"] + #[inline(always)] + pub fn mask(&mut self) -> MASK_W { + MASK_W { w: self } + } + #[doc = "Bit 5 - Trace Start Input Enable"] + #[inline(always)] + pub fn tstarten(&mut self) -> TSTARTEN_W { + TSTARTEN_W { w: self } + } + #[doc = "Bit 6 - Trace Stop Input Enable"] + #[inline(always)] + pub fn tstopen(&mut self) -> TSTOPEN_W { + TSTOPEN_W { w: self } + } + #[doc = "Bit 7 - Special Function Register Write Privilege"] + #[inline(always)] + pub fn sfrwpriv(&mut self) -> SFRWPRIV_W { + SFRWPRIV_W { w: self } + } + #[doc = "Bit 8 - SRAM Privilege"] + #[inline(always)] + pub fn rampriv(&mut self) -> RAMPRIV_W { + RAMPRIV_W { w: self } + } + #[doc = "Bit 9 - Halt Request"] + #[inline(always)] + pub fn haltreq(&mut self) -> HALTREQ_W { + HALTREQ_W { w: self } + } + #[doc = "Bit 31 - Main Trace Enable"] + #[inline(always)] + pub fn en(&mut self) -> EN_W { + EN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MTB Master\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [master](index.html) module"] +pub struct MASTER_SPEC; +impl crate::RegisterSpec for MASTER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [master::R](R) reader structure"] +impl crate::Readable for MASTER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [master::W](W) writer structure"] +impl crate::Writable for MASTER_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets MASTER to value 0"] +impl crate::Resettable for MASTER_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/mtb/pid0.rs b/pac/atsamc20j/src/mtb/pid0.rs new file mode 100644 index 000000000000..0a7183189fe5 --- /dev/null +++ b/pac/atsamc20j/src/mtb/pid0.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid0](index.html) module"] +pub struct PID0_SPEC; +impl crate::RegisterSpec for PID0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid0::R](R) reader structure"] +impl crate::Readable for PID0_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID0 to value 0"] +impl crate::Resettable for PID0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/mtb/pid1.rs b/pac/atsamc20j/src/mtb/pid1.rs new file mode 100644 index 000000000000..7d6381917f5d --- /dev/null +++ b/pac/atsamc20j/src/mtb/pid1.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid1](index.html) module"] +pub struct PID1_SPEC; +impl crate::RegisterSpec for PID1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid1::R](R) reader structure"] +impl crate::Readable for PID1_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID1 to value 0"] +impl crate::Resettable for PID1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/mtb/pid2.rs b/pac/atsamc20j/src/mtb/pid2.rs new file mode 100644 index 000000000000..74c230346b4c --- /dev/null +++ b/pac/atsamc20j/src/mtb/pid2.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 2\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid2](index.html) module"] +pub struct PID2_SPEC; +impl crate::RegisterSpec for PID2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid2::R](R) reader structure"] +impl crate::Readable for PID2_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID2 to value 0"] +impl crate::Resettable for PID2_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/mtb/pid3.rs b/pac/atsamc20j/src/mtb/pid3.rs new file mode 100644 index 000000000000..e9e922aa2f21 --- /dev/null +++ b/pac/atsamc20j/src/mtb/pid3.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 3\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid3](index.html) module"] +pub struct PID3_SPEC; +impl crate::RegisterSpec for PID3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid3::R](R) reader structure"] +impl crate::Readable for PID3_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID3 to value 0"] +impl crate::Resettable for PID3_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/mtb/pid4.rs b/pac/atsamc20j/src/mtb/pid4.rs new file mode 100644 index 000000000000..89074d3c2692 --- /dev/null +++ b/pac/atsamc20j/src/mtb/pid4.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID4` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 4\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid4](index.html) module"] +pub struct PID4_SPEC; +impl crate::RegisterSpec for PID4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid4::R](R) reader structure"] +impl crate::Readable for PID4_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID4 to value 0"] +impl crate::Resettable for PID4_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/mtb/pid5.rs b/pac/atsamc20j/src/mtb/pid5.rs new file mode 100644 index 000000000000..d343d4800b95 --- /dev/null +++ b/pac/atsamc20j/src/mtb/pid5.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID5` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 5\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid5](index.html) module"] +pub struct PID5_SPEC; +impl crate::RegisterSpec for PID5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid5::R](R) reader structure"] +impl crate::Readable for PID5_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID5 to value 0"] +impl crate::Resettable for PID5_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/mtb/pid6.rs b/pac/atsamc20j/src/mtb/pid6.rs new file mode 100644 index 000000000000..55cc2b8b5861 --- /dev/null +++ b/pac/atsamc20j/src/mtb/pid6.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID6` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 6\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid6](index.html) module"] +pub struct PID6_SPEC; +impl crate::RegisterSpec for PID6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid6::R](R) reader structure"] +impl crate::Readable for PID6_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID6 to value 0"] +impl crate::Resettable for PID6_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/mtb/pid7.rs b/pac/atsamc20j/src/mtb/pid7.rs new file mode 100644 index 000000000000..77664d4f2f95 --- /dev/null +++ b/pac/atsamc20j/src/mtb/pid7.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID7` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 7\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid7](index.html) module"] +pub struct PID7_SPEC; +impl crate::RegisterSpec for PID7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid7::R](R) reader structure"] +impl crate::Readable for PID7_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID7 to value 0"] +impl crate::Resettable for PID7_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/mtb/position.rs b/pac/atsamc20j/src/mtb/position.rs new file mode 100644 index 000000000000..4bab0425b142 --- /dev/null +++ b/pac/atsamc20j/src/mtb/position.rs @@ -0,0 +1,150 @@ +#[doc = "Register `POSITION` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `POSITION` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WRAP` reader - Pointer Value Wraps"] +pub struct WRAP_R(crate::FieldReader); +impl WRAP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WRAP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WRAP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WRAP` writer - Pointer Value Wraps"] +pub struct WRAP_W<'a> { + w: &'a mut W, +} +impl<'a> WRAP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `POINTER` reader - Trace Packet Location Pointer"] +pub struct POINTER_R(crate::FieldReader); +impl POINTER_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + POINTER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for POINTER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `POINTER` writer - Trace Packet Location Pointer"] +pub struct POINTER_W<'a> { + w: &'a mut W, +} +impl<'a> POINTER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1fff_ffff << 3)) | ((value as u32 & 0x1fff_ffff) << 3); + self.w + } +} +impl R { + #[doc = "Bit 2 - Pointer Value Wraps"] + #[inline(always)] + pub fn wrap(&self) -> WRAP_R { + WRAP_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 3:31 - Trace Packet Location Pointer"] + #[inline(always)] + pub fn pointer(&self) -> POINTER_R { + POINTER_R::new(((self.bits >> 3) & 0x1fff_ffff) as u32) + } +} +impl W { + #[doc = "Bit 2 - Pointer Value Wraps"] + #[inline(always)] + pub fn wrap(&mut self) -> WRAP_W { + WRAP_W { w: self } + } + #[doc = "Bits 3:31 - Trace Packet Location Pointer"] + #[inline(always)] + pub fn pointer(&mut self) -> POINTER_W { + POINTER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MTB Position\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [position](index.html) module"] +pub struct POSITION_SPEC; +impl crate::RegisterSpec for POSITION_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [position::R](R) reader structure"] +impl crate::Readable for POSITION_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [position::W](W) writer structure"] +impl crate::Writable for POSITION_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets POSITION to value 0"] +impl crate::Resettable for POSITION_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/nvmctrl.rs b/pac/atsamc20j/src/nvmctrl.rs new file mode 100644 index 000000000000..2c017caaef9c --- /dev/null +++ b/pac/atsamc20j/src/nvmctrl.rs @@ -0,0 +1,76 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + _reserved1: [u8; 0x02], + #[doc = "0x04 - Control B"] + pub ctrlb: crate::Reg, + #[doc = "0x08 - NVM Parameter"] + pub param: crate::Reg, + #[doc = "0x0c - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + _reserved4: [u8; 0x03], + #[doc = "0x10 - Interrupt Enable Set"] + pub intenset: crate::Reg, + _reserved5: [u8; 0x03], + #[doc = "0x14 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved6: [u8; 0x03], + #[doc = "0x18 - Status"] + pub status: crate::Reg, + _reserved7: [u8; 0x02], + #[doc = "0x1c - Address"] + pub addr: crate::Reg, + #[doc = "0x20 - Lock Section"] + pub lock: crate::Reg, + _reserved9: [u8; 0x06], + #[doc = "0x28 - Page Buffer Load Data 0"] + pub pbldata0: crate::Reg, + #[doc = "0x2c - Page Buffer Load Data 1"] + pub pbldata1: crate::Reg, +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "Control B"] +pub mod ctrlb; +#[doc = "PARAM register accessor: an alias for `Reg`"] +pub type PARAM = crate::Reg; +#[doc = "NVM Parameter"] +pub mod param; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "ADDR register accessor: an alias for `Reg`"] +pub type ADDR = crate::Reg; +#[doc = "Address"] +pub mod addr; +#[doc = "LOCK register accessor: an alias for `Reg`"] +pub type LOCK = crate::Reg; +#[doc = "Lock Section"] +pub mod lock; +#[doc = "PBLDATA0 register accessor: an alias for `Reg`"] +pub type PBLDATA0 = crate::Reg; +#[doc = "Page Buffer Load Data 0"] +pub mod pbldata0; +#[doc = "PBLDATA1 register accessor: an alias for `Reg`"] +pub type PBLDATA1 = crate::Reg; +#[doc = "Page Buffer Load Data 1"] +pub mod pbldata1; diff --git a/pac/atsamc20j/src/nvmctrl/addr.rs b/pac/atsamc20j/src/nvmctrl/addr.rs new file mode 100644 index 000000000000..74ed27736dac --- /dev/null +++ b/pac/atsamc20j/src/nvmctrl/addr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `ADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ADDR` reader - NVM Address"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - NVM Address"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x003f_ffff) | (value as u32 & 0x003f_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:21 - NVM Address"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new((self.bits & 0x003f_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:21 - NVM Address"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [addr](index.html) module"] +pub struct ADDR_SPEC; +impl crate::RegisterSpec for ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [addr::R](R) reader structure"] +impl crate::Readable for ADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [addr::W](W) writer structure"] +impl crate::Writable for ADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ADDR to value 0"] +impl crate::Resettable for ADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/nvmctrl/ctrla.rs b/pac/atsamc20j/src/nvmctrl/ctrla.rs new file mode 100644 index 000000000000..89f175771e4d --- /dev/null +++ b/pac/atsamc20j/src/nvmctrl/ctrla.rs @@ -0,0 +1,394 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "2: Erase Row - Erases the row addressed by the ADDR register."] + ER = 2, + #[doc = "4: Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register."] + WP = 4, + #[doc = "5: Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row."] + EAR = 5, + #[doc = "6: Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row."] + WAP = 6, + #[doc = "10: Security Flow Command"] + SF = 10, + #[doc = "15: Write lockbits"] + WL = 15, + #[doc = "26: RWW EEPROM area Erase Row - Erases the row addressed by the ADDR register."] + RWWEEER = 26, + #[doc = "28: RWW EEPROM Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register."] + RWWEEWP = 28, + #[doc = "64: Lock Region - Locks the region containing the address location in the ADDR register."] + LR = 64, + #[doc = "65: Unlock Region - Unlocks the region containing the address location in the ADDR register."] + UR = 65, + #[doc = "66: Sets the power reduction mode."] + SPRM = 66, + #[doc = "67: Clears the power reduction mode."] + CPRM = 67, + #[doc = "68: Page Buffer Clear - Clears the page buffer."] + PBC = 68, + #[doc = "69: Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row."] + SSB = 69, + #[doc = "70: Invalidate all cache lines."] + INVALL = 70, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 2 => Some(CMD_A::ER), + 4 => Some(CMD_A::WP), + 5 => Some(CMD_A::EAR), + 6 => Some(CMD_A::WAP), + 10 => Some(CMD_A::SF), + 15 => Some(CMD_A::WL), + 26 => Some(CMD_A::RWWEEER), + 28 => Some(CMD_A::RWWEEWP), + 64 => Some(CMD_A::LR), + 65 => Some(CMD_A::UR), + 66 => Some(CMD_A::SPRM), + 67 => Some(CMD_A::CPRM), + 68 => Some(CMD_A::PBC), + 69 => Some(CMD_A::SSB), + 70 => Some(CMD_A::INVALL), + _ => None, + } + } + #[doc = "Checks if the value of the field is `ER`"] + #[inline(always)] + pub fn is_er(&self) -> bool { + **self == CMD_A::ER + } + #[doc = "Checks if the value of the field is `WP`"] + #[inline(always)] + pub fn is_wp(&self) -> bool { + **self == CMD_A::WP + } + #[doc = "Checks if the value of the field is `EAR`"] + #[inline(always)] + pub fn is_ear(&self) -> bool { + **self == CMD_A::EAR + } + #[doc = "Checks if the value of the field is `WAP`"] + #[inline(always)] + pub fn is_wap(&self) -> bool { + **self == CMD_A::WAP + } + #[doc = "Checks if the value of the field is `SF`"] + #[inline(always)] + pub fn is_sf(&self) -> bool { + **self == CMD_A::SF + } + #[doc = "Checks if the value of the field is `WL`"] + #[inline(always)] + pub fn is_wl(&self) -> bool { + **self == CMD_A::WL + } + #[doc = "Checks if the value of the field is `RWWEEER`"] + #[inline(always)] + pub fn is_rwweeer(&self) -> bool { + **self == CMD_A::RWWEEER + } + #[doc = "Checks if the value of the field is `RWWEEWP`"] + #[inline(always)] + pub fn is_rwweewp(&self) -> bool { + **self == CMD_A::RWWEEWP + } + #[doc = "Checks if the value of the field is `LR`"] + #[inline(always)] + pub fn is_lr(&self) -> bool { + **self == CMD_A::LR + } + #[doc = "Checks if the value of the field is `UR`"] + #[inline(always)] + pub fn is_ur(&self) -> bool { + **self == CMD_A::UR + } + #[doc = "Checks if the value of the field is `SPRM`"] + #[inline(always)] + pub fn is_sprm(&self) -> bool { + **self == CMD_A::SPRM + } + #[doc = "Checks if the value of the field is `CPRM`"] + #[inline(always)] + pub fn is_cprm(&self) -> bool { + **self == CMD_A::CPRM + } + #[doc = "Checks if the value of the field is `PBC`"] + #[inline(always)] + pub fn is_pbc(&self) -> bool { + **self == CMD_A::PBC + } + #[doc = "Checks if the value of the field is `SSB`"] + #[inline(always)] + pub fn is_ssb(&self) -> bool { + **self == CMD_A::SSB + } + #[doc = "Checks if the value of the field is `INVALL`"] + #[inline(always)] + pub fn is_invall(&self) -> bool { + **self == CMD_A::INVALL + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Erase Row - Erases the row addressed by the ADDR register."] + #[inline(always)] + pub fn er(self) -> &'a mut W { + self.variant(CMD_A::ER) + } + #[doc = "Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register."] + #[inline(always)] + pub fn wp(self) -> &'a mut W { + self.variant(CMD_A::WP) + } + #[doc = "Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row."] + #[inline(always)] + pub fn ear(self) -> &'a mut W { + self.variant(CMD_A::EAR) + } + #[doc = "Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row."] + #[inline(always)] + pub fn wap(self) -> &'a mut W { + self.variant(CMD_A::WAP) + } + #[doc = "Security Flow Command"] + #[inline(always)] + pub fn sf(self) -> &'a mut W { + self.variant(CMD_A::SF) + } + #[doc = "Write lockbits"] + #[inline(always)] + pub fn wl(self) -> &'a mut W { + self.variant(CMD_A::WL) + } + #[doc = "RWW EEPROM area Erase Row - Erases the row addressed by the ADDR register."] + #[inline(always)] + pub fn rwweeer(self) -> &'a mut W { + self.variant(CMD_A::RWWEEER) + } + #[doc = "RWW EEPROM Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register."] + #[inline(always)] + pub fn rwweewp(self) -> &'a mut W { + self.variant(CMD_A::RWWEEWP) + } + #[doc = "Lock Region - Locks the region containing the address location in the ADDR register."] + #[inline(always)] + pub fn lr(self) -> &'a mut W { + self.variant(CMD_A::LR) + } + #[doc = "Unlock Region - Unlocks the region containing the address location in the ADDR register."] + #[inline(always)] + pub fn ur(self) -> &'a mut W { + self.variant(CMD_A::UR) + } + #[doc = "Sets the power reduction mode."] + #[inline(always)] + pub fn sprm(self) -> &'a mut W { + self.variant(CMD_A::SPRM) + } + #[doc = "Clears the power reduction mode."] + #[inline(always)] + pub fn cprm(self) -> &'a mut W { + self.variant(CMD_A::CPRM) + } + #[doc = "Page Buffer Clear - Clears the page buffer."] + #[inline(always)] + pub fn pbc(self) -> &'a mut W { + self.variant(CMD_A::PBC) + } + #[doc = "Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row."] + #[inline(always)] + pub fn ssb(self) -> &'a mut W { + self.variant(CMD_A::SSB) + } + #[doc = "Invalidate all cache lines."] + #[inline(always)] + pub fn invall(self) -> &'a mut W { + self.variant(CMD_A::INVALL) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x7f) | (value as u16 & 0x7f); + self.w + } +} +#[doc = "Command Execution\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMDEX_A { + #[doc = "165: Execution Key"] + KEY = 165, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMDEX_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMDEX` reader - Command Execution"] +pub struct CMDEX_R(crate::FieldReader); +impl CMDEX_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMDEX_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 165 => Some(CMDEX_A::KEY), + _ => None, + } + } + #[doc = "Checks if the value of the field is `KEY`"] + #[inline(always)] + pub fn is_key(&self) -> bool { + **self == CMDEX_A::KEY + } +} +impl core::ops::Deref for CMDEX_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMDEX` writer - Command Execution"] +pub struct CMDEX_W<'a> { + w: &'a mut W, +} +impl<'a> CMDEX_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMDEX_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Execution Key"] + #[inline(always)] + pub fn key(self) -> &'a mut W { + self.variant(CMDEX_A::KEY) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u16 & 0xff) << 8); + self.w + } +} +impl R { + #[doc = "Bits 0:6 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bits 8:15 - Command Execution"] + #[inline(always)] + pub fn cmdex(&self) -> CMDEX_R { + CMDEX_R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:6 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Bits 8:15 - Command Execution"] + #[inline(always)] + pub fn cmdex(&mut self) -> CMDEX_W { + CMDEX_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/nvmctrl/ctrlb.rs b/pac/atsamc20j/src/nvmctrl/ctrlb.rs new file mode 100644 index 000000000000..6162d0d4ade0 --- /dev/null +++ b/pac/atsamc20j/src/nvmctrl/ctrlb.rs @@ -0,0 +1,447 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "NVM Read Wait States\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum RWS_A { + #[doc = "0: Single Auto Wait State"] + SINGLE = 0, + #[doc = "1: Half Auto Wait State"] + HALF = 1, + #[doc = "2: Dual Auto Wait State"] + DUAL = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RWS_A) -> Self { + variant as _ + } +} +#[doc = "Field `RWS` reader - NVM Read Wait States"] +pub struct RWS_R(crate::FieldReader); +impl RWS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RWS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(RWS_A::SINGLE), + 1 => Some(RWS_A::HALF), + 2 => Some(RWS_A::DUAL), + _ => None, + } + } + #[doc = "Checks if the value of the field is `SINGLE`"] + #[inline(always)] + pub fn is_single(&self) -> bool { + **self == RWS_A::SINGLE + } + #[doc = "Checks if the value of the field is `HALF`"] + #[inline(always)] + pub fn is_half(&self) -> bool { + **self == RWS_A::HALF + } + #[doc = "Checks if the value of the field is `DUAL`"] + #[inline(always)] + pub fn is_dual(&self) -> bool { + **self == RWS_A::DUAL + } +} +impl core::ops::Deref for RWS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RWS` writer - NVM Read Wait States"] +pub struct RWS_W<'a> { + w: &'a mut W, +} +impl<'a> RWS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RWS_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Single Auto Wait State"] + #[inline(always)] + pub fn single(self) -> &'a mut W { + self.variant(RWS_A::SINGLE) + } + #[doc = "Half Auto Wait State"] + #[inline(always)] + pub fn half(self) -> &'a mut W { + self.variant(RWS_A::HALF) + } + #[doc = "Dual Auto Wait State"] + #[inline(always)] + pub fn dual(self) -> &'a mut W { + self.variant(RWS_A::DUAL) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 1)) | ((value as u32 & 0x0f) << 1); + self.w + } +} +#[doc = "Field `MANW` reader - Manual Write"] +pub struct MANW_R(crate::FieldReader); +impl MANW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MANW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MANW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MANW` writer - Manual Write"] +pub struct MANW_W<'a> { + w: &'a mut W, +} +impl<'a> MANW_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Power Reduction Mode during Sleep\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SLEEPPRM_A { + #[doc = "0: NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access."] + WAKEONACCESS = 0, + #[doc = "1: NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep."] + WAKEUPINSTANT = 1, + #[doc = "3: Auto power reduction disabled."] + DISABLED = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SLEEPPRM_A) -> Self { + variant as _ + } +} +#[doc = "Field `SLEEPPRM` reader - Power Reduction Mode during Sleep"] +pub struct SLEEPPRM_R(crate::FieldReader); +impl SLEEPPRM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SLEEPPRM_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SLEEPPRM_A::WAKEONACCESS), + 1 => Some(SLEEPPRM_A::WAKEUPINSTANT), + 3 => Some(SLEEPPRM_A::DISABLED), + _ => None, + } + } + #[doc = "Checks if the value of the field is `WAKEONACCESS`"] + #[inline(always)] + pub fn is_wakeonaccess(&self) -> bool { + **self == SLEEPPRM_A::WAKEONACCESS + } + #[doc = "Checks if the value of the field is `WAKEUPINSTANT`"] + #[inline(always)] + pub fn is_wakeupinstant(&self) -> bool { + **self == SLEEPPRM_A::WAKEUPINSTANT + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + **self == SLEEPPRM_A::DISABLED + } +} +impl core::ops::Deref for SLEEPPRM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLEEPPRM` writer - Power Reduction Mode during Sleep"] +pub struct SLEEPPRM_W<'a> { + w: &'a mut W, +} +impl<'a> SLEEPPRM_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SLEEPPRM_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access."] + #[inline(always)] + pub fn wakeonaccess(self) -> &'a mut W { + self.variant(SLEEPPRM_A::WAKEONACCESS) + } + #[doc = "NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep."] + #[inline(always)] + pub fn wakeupinstant(self) -> &'a mut W { + self.variant(SLEEPPRM_A::WAKEUPINSTANT) + } + #[doc = "Auto power reduction disabled."] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(SLEEPPRM_A::DISABLED) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 8)) | ((value as u32 & 0x03) << 8); + self.w + } +} +#[doc = "NVMCTRL Read Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum READMODE_A { + #[doc = "0: The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance."] + NO_MISS_PENALTY = 0, + #[doc = "1: Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time."] + LOW_POWER = 1, + #[doc = "2: The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings."] + DETERMINISTIC = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: READMODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `READMODE` reader - NVMCTRL Read Mode"] +pub struct READMODE_R(crate::FieldReader); +impl READMODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + READMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(READMODE_A::NO_MISS_PENALTY), + 1 => Some(READMODE_A::LOW_POWER), + 2 => Some(READMODE_A::DETERMINISTIC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NO_MISS_PENALTY`"] + #[inline(always)] + pub fn is_no_miss_penalty(&self) -> bool { + **self == READMODE_A::NO_MISS_PENALTY + } + #[doc = "Checks if the value of the field is `LOW_POWER`"] + #[inline(always)] + pub fn is_low_power(&self) -> bool { + **self == READMODE_A::LOW_POWER + } + #[doc = "Checks if the value of the field is `DETERMINISTIC`"] + #[inline(always)] + pub fn is_deterministic(&self) -> bool { + **self == READMODE_A::DETERMINISTIC + } +} +impl core::ops::Deref for READMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `READMODE` writer - NVMCTRL Read Mode"] +pub struct READMODE_W<'a> { + w: &'a mut W, +} +impl<'a> READMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: READMODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance."] + #[inline(always)] + pub fn no_miss_penalty(self) -> &'a mut W { + self.variant(READMODE_A::NO_MISS_PENALTY) + } + #[doc = "Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time."] + #[inline(always)] + pub fn low_power(self) -> &'a mut W { + self.variant(READMODE_A::LOW_POWER) + } + #[doc = "The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings."] + #[inline(always)] + pub fn deterministic(self) -> &'a mut W { + self.variant(READMODE_A::DETERMINISTIC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Field `CACHEDIS` reader - Cache Disable"] +pub struct CACHEDIS_R(crate::FieldReader); +impl CACHEDIS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CACHEDIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CACHEDIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CACHEDIS` writer - Cache Disable"] +pub struct CACHEDIS_W<'a> { + w: &'a mut W, +} +impl<'a> CACHEDIS_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 18)) | ((value as u32 & 0x03) << 18); + self.w + } +} +impl R { + #[doc = "Bits 1:4 - NVM Read Wait States"] + #[inline(always)] + pub fn rws(&self) -> RWS_R { + RWS_R::new(((self.bits >> 1) & 0x0f) as u8) + } + #[doc = "Bit 7 - Manual Write"] + #[inline(always)] + pub fn manw(&self) -> MANW_R { + MANW_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:9 - Power Reduction Mode during Sleep"] + #[inline(always)] + pub fn sleepprm(&self) -> SLEEPPRM_R { + SLEEPPRM_R::new(((self.bits >> 8) & 0x03) as u8) + } + #[doc = "Bits 16:17 - NVMCTRL Read Mode"] + #[inline(always)] + pub fn readmode(&self) -> READMODE_R { + READMODE_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bits 18:19 - Cache Disable"] + #[inline(always)] + pub fn cachedis(&self) -> CACHEDIS_R { + CACHEDIS_R::new(((self.bits >> 18) & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 1:4 - NVM Read Wait States"] + #[inline(always)] + pub fn rws(&mut self) -> RWS_W { + RWS_W { w: self } + } + #[doc = "Bit 7 - Manual Write"] + #[inline(always)] + pub fn manw(&mut self) -> MANW_W { + MANW_W { w: self } + } + #[doc = "Bits 8:9 - Power Reduction Mode during Sleep"] + #[inline(always)] + pub fn sleepprm(&mut self) -> SLEEPPRM_W { + SLEEPPRM_W { w: self } + } + #[doc = "Bits 16:17 - NVMCTRL Read Mode"] + #[inline(always)] + pub fn readmode(&mut self) -> READMODE_W { + READMODE_W { w: self } + } + #[doc = "Bits 18:19 - Cache Disable"] + #[inline(always)] + pub fn cachedis(&mut self) -> CACHEDIS_W { + CACHEDIS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0x80"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x80 + } +} diff --git a/pac/atsamc20j/src/nvmctrl/intenclr.rs b/pac/atsamc20j/src/nvmctrl/intenclr.rs new file mode 100644 index 000000000000..6e7db4b52c9d --- /dev/null +++ b/pac/atsamc20j/src/nvmctrl/intenclr.rs @@ -0,0 +1,160 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `READY` reader - NVM Ready Interrupt Enable"] +pub struct READY_R(crate::FieldReader); +impl READY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + READY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for READY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `READY` writer - NVM Ready Interrupt Enable"] +pub struct READY_W<'a> { + w: &'a mut W, +} +impl<'a> READY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERROR` reader - Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - NVM Ready Interrupt Enable"] + #[inline(always)] + pub fn ready(&self) -> READY_R { + READY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - NVM Ready Interrupt Enable"] + #[inline(always)] + pub fn ready(&mut self) -> READY_W { + READY_W { w: self } + } + #[doc = "Bit 1 - Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/nvmctrl/intenset.rs b/pac/atsamc20j/src/nvmctrl/intenset.rs new file mode 100644 index 000000000000..ba8698e86c3e --- /dev/null +++ b/pac/atsamc20j/src/nvmctrl/intenset.rs @@ -0,0 +1,160 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `READY` reader - NVM Ready Interrupt Enable"] +pub struct READY_R(crate::FieldReader); +impl READY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + READY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for READY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `READY` writer - NVM Ready Interrupt Enable"] +pub struct READY_W<'a> { + w: &'a mut W, +} +impl<'a> READY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERROR` reader - Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - NVM Ready Interrupt Enable"] + #[inline(always)] + pub fn ready(&self) -> READY_R { + READY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - NVM Ready Interrupt Enable"] + #[inline(always)] + pub fn ready(&mut self) -> READY_W { + READY_W { w: self } + } + #[doc = "Bit 1 - Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/nvmctrl/intflag.rs b/pac/atsamc20j/src/nvmctrl/intflag.rs new file mode 100644 index 000000000000..1b30cdddf25d --- /dev/null +++ b/pac/atsamc20j/src/nvmctrl/intflag.rs @@ -0,0 +1,160 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `READY` reader - NVM Ready"] +pub struct READY_R(crate::FieldReader); +impl READY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + READY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for READY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `READY` writer - NVM Ready"] +pub struct READY_W<'a> { + w: &'a mut W, +} +impl<'a> READY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERROR` reader - Error"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Error"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - NVM Ready"] + #[inline(always)] + pub fn ready(&self) -> READY_R { + READY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Error"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - NVM Ready"] + #[inline(always)] + pub fn ready(&mut self) -> READY_W { + READY_W { w: self } + } + #[doc = "Bit 1 - Error"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/nvmctrl/lock.rs b/pac/atsamc20j/src/nvmctrl/lock.rs new file mode 100644 index 000000000000..dbcf37a8107f --- /dev/null +++ b/pac/atsamc20j/src/nvmctrl/lock.rs @@ -0,0 +1,103 @@ +#[doc = "Register `LOCK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `LOCK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `LOCK` reader - Region Lock Bits"] +pub struct LOCK_R(crate::FieldReader); +impl LOCK_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + LOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LOCK` writer - Region Lock Bits"] +pub struct LOCK_W<'a> { + w: &'a mut W, +} +impl<'a> LOCK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Region Lock Bits"] + #[inline(always)] + pub fn lock(&self) -> LOCK_R { + LOCK_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Region Lock Bits"] + #[inline(always)] + pub fn lock(&mut self) -> LOCK_W { + LOCK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Lock Section\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lock](index.html) module"] +pub struct LOCK_SPEC; +impl crate::RegisterSpec for LOCK_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [lock::R](R) reader structure"] +impl crate::Readable for LOCK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [lock::W](W) writer structure"] +impl crate::Writable for LOCK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets LOCK to value 0"] +impl crate::Resettable for LOCK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/nvmctrl/param.rs b/pac/atsamc20j/src/nvmctrl/param.rs new file mode 100644 index 000000000000..d9197cf16de4 --- /dev/null +++ b/pac/atsamc20j/src/nvmctrl/param.rs @@ -0,0 +1,304 @@ +#[doc = "Register `PARAM` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PARAM` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `NVMP` reader - NVM Pages"] +pub struct NVMP_R(crate::FieldReader); +impl NVMP_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + NVMP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NVMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NVMP` writer - NVM Pages"] +pub struct NVMP_W<'a> { + w: &'a mut W, +} +impl<'a> NVMP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +#[doc = "Page Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PSZ_A { + #[doc = "0: 8 bytes"] + _8 = 0, + #[doc = "1: 16 bytes"] + _16 = 1, + #[doc = "2: 32 bytes"] + _32 = 2, + #[doc = "3: 64 bytes"] + _64 = 3, + #[doc = "4: 128 bytes"] + _128 = 4, + #[doc = "5: 256 bytes"] + _256 = 5, + #[doc = "6: 512 bytes"] + _512 = 6, + #[doc = "7: 1024 bytes"] + _1024 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PSZ_A) -> Self { + variant as _ + } +} +#[doc = "Field `PSZ` reader - Page Size"] +pub struct PSZ_R(crate::FieldReader); +impl PSZ_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PSZ_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PSZ_A { + match self.bits { + 0 => PSZ_A::_8, + 1 => PSZ_A::_16, + 2 => PSZ_A::_32, + 3 => PSZ_A::_64, + 4 => PSZ_A::_128, + 5 => PSZ_A::_256, + 6 => PSZ_A::_512, + 7 => PSZ_A::_1024, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `_8`"] + #[inline(always)] + pub fn is_8(&self) -> bool { + **self == PSZ_A::_8 + } + #[doc = "Checks if the value of the field is `_16`"] + #[inline(always)] + pub fn is_16(&self) -> bool { + **self == PSZ_A::_16 + } + #[doc = "Checks if the value of the field is `_32`"] + #[inline(always)] + pub fn is_32(&self) -> bool { + **self == PSZ_A::_32 + } + #[doc = "Checks if the value of the field is `_64`"] + #[inline(always)] + pub fn is_64(&self) -> bool { + **self == PSZ_A::_64 + } + #[doc = "Checks if the value of the field is `_128`"] + #[inline(always)] + pub fn is_128(&self) -> bool { + **self == PSZ_A::_128 + } + #[doc = "Checks if the value of the field is `_256`"] + #[inline(always)] + pub fn is_256(&self) -> bool { + **self == PSZ_A::_256 + } + #[doc = "Checks if the value of the field is `_512`"] + #[inline(always)] + pub fn is_512(&self) -> bool { + **self == PSZ_A::_512 + } + #[doc = "Checks if the value of the field is `_1024`"] + #[inline(always)] + pub fn is_1024(&self) -> bool { + **self == PSZ_A::_1024 + } +} +impl core::ops::Deref for PSZ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PSZ` writer - Page Size"] +pub struct PSZ_W<'a> { + w: &'a mut W, +} +impl<'a> PSZ_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PSZ_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "8 bytes"] + #[inline(always)] + pub fn _8(self) -> &'a mut W { + self.variant(PSZ_A::_8) + } + #[doc = "16 bytes"] + #[inline(always)] + pub fn _16(self) -> &'a mut W { + self.variant(PSZ_A::_16) + } + #[doc = "32 bytes"] + #[inline(always)] + pub fn _32(self) -> &'a mut W { + self.variant(PSZ_A::_32) + } + #[doc = "64 bytes"] + #[inline(always)] + pub fn _64(self) -> &'a mut W { + self.variant(PSZ_A::_64) + } + #[doc = "128 bytes"] + #[inline(always)] + pub fn _128(self) -> &'a mut W { + self.variant(PSZ_A::_128) + } + #[doc = "256 bytes"] + #[inline(always)] + pub fn _256(self) -> &'a mut W { + self.variant(PSZ_A::_256) + } + #[doc = "512 bytes"] + #[inline(always)] + pub fn _512(self) -> &'a mut W { + self.variant(PSZ_A::_512) + } + #[doc = "1024 bytes"] + #[inline(always)] + pub fn _1024(self) -> &'a mut W { + self.variant(PSZ_A::_1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 16)) | ((value as u32 & 0x07) << 16); + self.w + } +} +#[doc = "Field `RWWEEP` reader - RWW EEPROM Pages"] +pub struct RWWEEP_R(crate::FieldReader); +impl RWWEEP_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + RWWEEP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RWWEEP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RWWEEP` writer - RWW EEPROM Pages"] +pub struct RWWEEP_W<'a> { + w: &'a mut W, +} +impl<'a> RWWEEP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0fff << 20)) | ((value as u32 & 0x0fff) << 20); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - NVM Pages"] + #[inline(always)] + pub fn nvmp(&self) -> NVMP_R { + NVMP_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:18 - Page Size"] + #[inline(always)] + pub fn psz(&self) -> PSZ_R { + PSZ_R::new(((self.bits >> 16) & 0x07) as u8) + } + #[doc = "Bits 20:31 - RWW EEPROM Pages"] + #[inline(always)] + pub fn rwweep(&self) -> RWWEEP_R { + RWWEEP_R::new(((self.bits >> 20) & 0x0fff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - NVM Pages"] + #[inline(always)] + pub fn nvmp(&mut self) -> NVMP_W { + NVMP_W { w: self } + } + #[doc = "Bits 16:18 - Page Size"] + #[inline(always)] + pub fn psz(&mut self) -> PSZ_W { + PSZ_W { w: self } + } + #[doc = "Bits 20:31 - RWW EEPROM Pages"] + #[inline(always)] + pub fn rwweep(&mut self) -> RWWEEP_W { + RWWEEP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "NVM Parameter\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [param](index.html) module"] +pub struct PARAM_SPEC; +impl crate::RegisterSpec for PARAM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [param::R](R) reader structure"] +impl crate::Readable for PARAM_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [param::W](W) writer structure"] +impl crate::Writable for PARAM_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PARAM to value 0"] +impl crate::Resettable for PARAM_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/nvmctrl/pbldata0.rs b/pac/atsamc20j/src/nvmctrl/pbldata0.rs new file mode 100644 index 000000000000..ff2effaf4d89 --- /dev/null +++ b/pac/atsamc20j/src/nvmctrl/pbldata0.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PBLDATA0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Page Buffer Load Data 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pbldata0](index.html) module"] +pub struct PBLDATA0_SPEC; +impl crate::RegisterSpec for PBLDATA0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pbldata0::R](R) reader structure"] +impl crate::Readable for PBLDATA0_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PBLDATA0 to value 0"] +impl crate::Resettable for PBLDATA0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/nvmctrl/pbldata1.rs b/pac/atsamc20j/src/nvmctrl/pbldata1.rs new file mode 100644 index 000000000000..9fc6404691c5 --- /dev/null +++ b/pac/atsamc20j/src/nvmctrl/pbldata1.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PBLDATA1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Page Buffer Load Data 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pbldata1](index.html) module"] +pub struct PBLDATA1_SPEC; +impl crate::RegisterSpec for PBLDATA1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pbldata1::R](R) reader structure"] +impl crate::Readable for PBLDATA1_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PBLDATA1 to value 0"] +impl crate::Resettable for PBLDATA1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/nvmctrl/status.rs b/pac/atsamc20j/src/nvmctrl/status.rs new file mode 100644 index 000000000000..ce849015560e --- /dev/null +++ b/pac/atsamc20j/src/nvmctrl/status.rs @@ -0,0 +1,348 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PRM` reader - Power Reduction Mode"] +pub struct PRM_R(crate::FieldReader); +impl PRM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PRM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PRM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRM` writer - Power Reduction Mode"] +pub struct PRM_W<'a> { + w: &'a mut W, +} +impl<'a> PRM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `LOAD` reader - NVM Page Buffer Active Loading"] +pub struct LOAD_R(crate::FieldReader); +impl LOAD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LOAD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOAD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LOAD` writer - NVM Page Buffer Active Loading"] +pub struct LOAD_W<'a> { + w: &'a mut W, +} +impl<'a> LOAD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PROGE` reader - Programming Error Status"] +pub struct PROGE_R(crate::FieldReader); +impl PROGE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PROGE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PROGE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PROGE` writer - Programming Error Status"] +pub struct PROGE_W<'a> { + w: &'a mut W, +} +impl<'a> PROGE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `LOCKE` reader - Lock Error Status"] +pub struct LOCKE_R(crate::FieldReader); +impl LOCKE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LOCKE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOCKE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LOCKE` writer - Lock Error Status"] +pub struct LOCKE_W<'a> { + w: &'a mut W, +} +impl<'a> LOCKE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `NVME` reader - NVM Error"] +pub struct NVME_R(crate::FieldReader); +impl NVME_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NVME_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NVME_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NVME` writer - NVM Error"] +pub struct NVME_W<'a> { + w: &'a mut W, +} +impl<'a> NVME_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `SB` reader - Security Bit Status"] +pub struct SB_R(crate::FieldReader); +impl SB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SB` writer - Security Bit Status"] +pub struct SB_W<'a> { + w: &'a mut W, +} +impl<'a> SB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +impl R { + #[doc = "Bit 0 - Power Reduction Mode"] + #[inline(always)] + pub fn prm(&self) -> PRM_R { + PRM_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - NVM Page Buffer Active Loading"] + #[inline(always)] + pub fn load(&self) -> LOAD_R { + LOAD_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Programming Error Status"] + #[inline(always)] + pub fn proge(&self) -> PROGE_R { + PROGE_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Lock Error Status"] + #[inline(always)] + pub fn locke(&self) -> LOCKE_R { + LOCKE_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - NVM Error"] + #[inline(always)] + pub fn nvme(&self) -> NVME_R { + NVME_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 8 - Security Bit Status"] + #[inline(always)] + pub fn sb(&self) -> SB_R { + SB_R::new(((self.bits >> 8) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Power Reduction Mode"] + #[inline(always)] + pub fn prm(&mut self) -> PRM_W { + PRM_W { w: self } + } + #[doc = "Bit 1 - NVM Page Buffer Active Loading"] + #[inline(always)] + pub fn load(&mut self) -> LOAD_W { + LOAD_W { w: self } + } + #[doc = "Bit 2 - Programming Error Status"] + #[inline(always)] + pub fn proge(&mut self) -> PROGE_W { + PROGE_W { w: self } + } + #[doc = "Bit 3 - Lock Error Status"] + #[inline(always)] + pub fn locke(&mut self) -> LOCKE_W { + LOCKE_W { w: self } + } + #[doc = "Bit 4 - NVM Error"] + #[inline(always)] + pub fn nvme(&mut self) -> NVME_W { + NVME_W { w: self } + } + #[doc = "Bit 8 - Security Bit Status"] + #[inline(always)] + pub fn sb(&mut self) -> SB_W { + SB_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/osc32kctrl.rs b/pac/atsamc20j/src/osc32kctrl.rs new file mode 100644 index 000000000000..263cd2f61d59 --- /dev/null +++ b/pac/atsamc20j/src/osc32kctrl.rs @@ -0,0 +1,64 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x04 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x08 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x0c - Power and Clocks Status"] + pub status: crate::Reg, + #[doc = "0x10 - Clock selection"] + pub rtcctrl: crate::Reg, + #[doc = "0x14 - 32kHz External Crystal Oscillator (XOSC32K) Control"] + pub xosc32k: crate::Reg, + #[doc = "0x16 - Clock Failure Detector Control"] + pub cfdctrl: crate::Reg, + #[doc = "0x17 - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x18 - 32kHz Internal Oscillator (OSC32K) Control"] + pub osc32k: crate::Reg, + #[doc = "0x1c - 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control"] + pub osculp32k: crate::Reg, +} +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Power and Clocks Status"] +pub mod status; +#[doc = "RTCCTRL register accessor: an alias for `Reg`"] +pub type RTCCTRL = crate::Reg; +#[doc = "Clock selection"] +pub mod rtcctrl; +#[doc = "XOSC32K register accessor: an alias for `Reg`"] +pub type XOSC32K = crate::Reg; +#[doc = "32kHz External Crystal Oscillator (XOSC32K) Control"] +pub mod xosc32k; +#[doc = "CFDCTRL register accessor: an alias for `Reg`"] +pub type CFDCTRL = crate::Reg; +#[doc = "Clock Failure Detector Control"] +pub mod cfdctrl; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "OSC32K register accessor: an alias for `Reg`"] +pub type OSC32K = crate::Reg; +#[doc = "32kHz Internal Oscillator (OSC32K) Control"] +pub mod osc32k; +#[doc = "OSCULP32K register accessor: an alias for `Reg`"] +pub type OSCULP32K = crate::Reg; +#[doc = "32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control"] +pub mod osculp32k; diff --git a/pac/atsamc20j/src/osc32kctrl/cfdctrl.rs b/pac/atsamc20j/src/osc32kctrl/cfdctrl.rs new file mode 100644 index 000000000000..492a86e1a5a7 --- /dev/null +++ b/pac/atsamc20j/src/osc32kctrl/cfdctrl.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CFDCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CFDCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CFDEN` reader - Clock Failure Detector Enable"] +pub struct CFDEN_R(crate::FieldReader); +impl CFDEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFDEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFDEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFDEN` writer - Clock Failure Detector Enable"] +pub struct CFDEN_W<'a> { + w: &'a mut W, +} +impl<'a> CFDEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SWBACK` reader - Clock Switch Back"] +pub struct SWBACK_R(crate::FieldReader); +impl SWBACK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWBACK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWBACK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWBACK` writer - Clock Switch Back"] +pub struct SWBACK_W<'a> { + w: &'a mut W, +} +impl<'a> SWBACK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CFDPRESC` reader - Clock Failure Detector Prescaler"] +pub struct CFDPRESC_R(crate::FieldReader); +impl CFDPRESC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFDPRESC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFDPRESC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFDPRESC` writer - Clock Failure Detector Prescaler"] +pub struct CFDPRESC_W<'a> { + w: &'a mut W, +} +impl<'a> CFDPRESC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Clock Failure Detector Enable"] + #[inline(always)] + pub fn cfden(&self) -> CFDEN_R { + CFDEN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Clock Switch Back"] + #[inline(always)] + pub fn swback(&self) -> SWBACK_R { + SWBACK_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Clock Failure Detector Prescaler"] + #[inline(always)] + pub fn cfdpresc(&self) -> CFDPRESC_R { + CFDPRESC_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Clock Failure Detector Enable"] + #[inline(always)] + pub fn cfden(&mut self) -> CFDEN_W { + CFDEN_W { w: self } + } + #[doc = "Bit 1 - Clock Switch Back"] + #[inline(always)] + pub fn swback(&mut self) -> SWBACK_W { + SWBACK_W { w: self } + } + #[doc = "Bit 2 - Clock Failure Detector Prescaler"] + #[inline(always)] + pub fn cfdpresc(&mut self) -> CFDPRESC_W { + CFDPRESC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Clock Failure Detector Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cfdctrl](index.html) module"] +pub struct CFDCTRL_SPEC; +impl crate::RegisterSpec for CFDCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [cfdctrl::R](R) reader structure"] +impl crate::Readable for CFDCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cfdctrl::W](W) writer structure"] +impl crate::Writable for CFDCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CFDCTRL to value 0"] +impl crate::Resettable for CFDCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/osc32kctrl/evctrl.rs b/pac/atsamc20j/src/osc32kctrl/evctrl.rs new file mode 100644 index 000000000000..e22ba62f0fe2 --- /dev/null +++ b/pac/atsamc20j/src/osc32kctrl/evctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CFDEO` reader - Clock Failure Detector Event Output Enable"] +pub struct CFDEO_R(crate::FieldReader); +impl CFDEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFDEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFDEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFDEO` writer - Clock Failure Detector Event Output Enable"] +pub struct CFDEO_W<'a> { + w: &'a mut W, +} +impl<'a> CFDEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Clock Failure Detector Event Output Enable"] + #[inline(always)] + pub fn cfdeo(&self) -> CFDEO_R { + CFDEO_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Clock Failure Detector Event Output Enable"] + #[inline(always)] + pub fn cfdeo(&mut self) -> CFDEO_W { + CFDEO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/osc32kctrl/intenclr.rs b/pac/atsamc20j/src/osc32kctrl/intenclr.rs new file mode 100644 index 000000000000..7e330c8de495 --- /dev/null +++ b/pac/atsamc20j/src/osc32kctrl/intenclr.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XOSC32KRDY` reader - XOSC32K Ready Interrupt Enable"] +pub struct XOSC32KRDY_R(crate::FieldReader); +impl XOSC32KRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSC32KRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSC32KRDY` writer - XOSC32K Ready Interrupt Enable"] +pub struct XOSC32KRDY_W<'a> { + w: &'a mut W, +} +impl<'a> XOSC32KRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `OSC32KRDY` reader - OSC32K Ready Interrupt Enable"] +pub struct OSC32KRDY_R(crate::FieldReader); +impl OSC32KRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC32KRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC32KRDY` writer - OSC32K Ready Interrupt Enable"] +pub struct OSC32KRDY_W<'a> { + w: &'a mut W, +} +impl<'a> OSC32KRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CLKFAIL` reader - XOSC32K Clock Failure Detector Interrupt Enable"] +pub struct CLKFAIL_R(crate::FieldReader); +impl CLKFAIL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKFAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKFAIL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKFAIL` writer - XOSC32K Clock Failure Detector Interrupt Enable"] +pub struct CLKFAIL_W<'a> { + w: &'a mut W, +} +impl<'a> CLKFAIL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - XOSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn xosc32krdy(&self) -> XOSC32KRDY_R { + XOSC32KRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - OSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn osc32krdy(&self) -> OSC32KRDY_R { + OSC32KRDY_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - XOSC32K Clock Failure Detector Interrupt Enable"] + #[inline(always)] + pub fn clkfail(&self) -> CLKFAIL_R { + CLKFAIL_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - XOSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn xosc32krdy(&mut self) -> XOSC32KRDY_W { + XOSC32KRDY_W { w: self } + } + #[doc = "Bit 1 - OSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn osc32krdy(&mut self) -> OSC32KRDY_W { + OSC32KRDY_W { w: self } + } + #[doc = "Bit 2 - XOSC32K Clock Failure Detector Interrupt Enable"] + #[inline(always)] + pub fn clkfail(&mut self) -> CLKFAIL_W { + CLKFAIL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/osc32kctrl/intenset.rs b/pac/atsamc20j/src/osc32kctrl/intenset.rs new file mode 100644 index 000000000000..e853d40049f2 --- /dev/null +++ b/pac/atsamc20j/src/osc32kctrl/intenset.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XOSC32KRDY` reader - XOSC32K Ready Interrupt Enable"] +pub struct XOSC32KRDY_R(crate::FieldReader); +impl XOSC32KRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSC32KRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSC32KRDY` writer - XOSC32K Ready Interrupt Enable"] +pub struct XOSC32KRDY_W<'a> { + w: &'a mut W, +} +impl<'a> XOSC32KRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `OSC32KRDY` reader - OSC32K Ready Interrupt Enable"] +pub struct OSC32KRDY_R(crate::FieldReader); +impl OSC32KRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC32KRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC32KRDY` writer - OSC32K Ready Interrupt Enable"] +pub struct OSC32KRDY_W<'a> { + w: &'a mut W, +} +impl<'a> OSC32KRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CLKFAIL` reader - XOSC32K Clock Failure Detector Interrupt Enable"] +pub struct CLKFAIL_R(crate::FieldReader); +impl CLKFAIL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKFAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKFAIL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKFAIL` writer - XOSC32K Clock Failure Detector Interrupt Enable"] +pub struct CLKFAIL_W<'a> { + w: &'a mut W, +} +impl<'a> CLKFAIL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - XOSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn xosc32krdy(&self) -> XOSC32KRDY_R { + XOSC32KRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - OSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn osc32krdy(&self) -> OSC32KRDY_R { + OSC32KRDY_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - XOSC32K Clock Failure Detector Interrupt Enable"] + #[inline(always)] + pub fn clkfail(&self) -> CLKFAIL_R { + CLKFAIL_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - XOSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn xosc32krdy(&mut self) -> XOSC32KRDY_W { + XOSC32KRDY_W { w: self } + } + #[doc = "Bit 1 - OSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn osc32krdy(&mut self) -> OSC32KRDY_W { + OSC32KRDY_W { w: self } + } + #[doc = "Bit 2 - XOSC32K Clock Failure Detector Interrupt Enable"] + #[inline(always)] + pub fn clkfail(&mut self) -> CLKFAIL_W { + CLKFAIL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/osc32kctrl/intflag.rs b/pac/atsamc20j/src/osc32kctrl/intflag.rs new file mode 100644 index 000000000000..9ca42439429d --- /dev/null +++ b/pac/atsamc20j/src/osc32kctrl/intflag.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XOSC32KRDY` reader - XOSC32K Ready"] +pub struct XOSC32KRDY_R(crate::FieldReader); +impl XOSC32KRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSC32KRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSC32KRDY` writer - XOSC32K Ready"] +pub struct XOSC32KRDY_W<'a> { + w: &'a mut W, +} +impl<'a> XOSC32KRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `OSC32KRDY` reader - OSC32K Ready"] +pub struct OSC32KRDY_R(crate::FieldReader); +impl OSC32KRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC32KRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC32KRDY` writer - OSC32K Ready"] +pub struct OSC32KRDY_W<'a> { + w: &'a mut W, +} +impl<'a> OSC32KRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CLKFAIL` reader - XOSC32K Clock Failure Detector"] +pub struct CLKFAIL_R(crate::FieldReader); +impl CLKFAIL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKFAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKFAIL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKFAIL` writer - XOSC32K Clock Failure Detector"] +pub struct CLKFAIL_W<'a> { + w: &'a mut W, +} +impl<'a> CLKFAIL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - XOSC32K Ready"] + #[inline(always)] + pub fn xosc32krdy(&self) -> XOSC32KRDY_R { + XOSC32KRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - OSC32K Ready"] + #[inline(always)] + pub fn osc32krdy(&self) -> OSC32KRDY_R { + OSC32KRDY_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - XOSC32K Clock Failure Detector"] + #[inline(always)] + pub fn clkfail(&self) -> CLKFAIL_R { + CLKFAIL_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - XOSC32K Ready"] + #[inline(always)] + pub fn xosc32krdy(&mut self) -> XOSC32KRDY_W { + XOSC32KRDY_W { w: self } + } + #[doc = "Bit 1 - OSC32K Ready"] + #[inline(always)] + pub fn osc32krdy(&mut self) -> OSC32KRDY_W { + OSC32KRDY_W { w: self } + } + #[doc = "Bit 2 - XOSC32K Clock Failure Detector"] + #[inline(always)] + pub fn clkfail(&mut self) -> CLKFAIL_W { + CLKFAIL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/osc32kctrl/osc32k.rs b/pac/atsamc20j/src/osc32kctrl/osc32k.rs new file mode 100644 index 000000000000..aa32cb287aa7 --- /dev/null +++ b/pac/atsamc20j/src/osc32kctrl/osc32k.rs @@ -0,0 +1,549 @@ +#[doc = "Register `OSC32K` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OSC32K` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Oscillator Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Oscillator Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `EN32K` reader - 32kHz Output Enable"] +pub struct EN32K_R(crate::FieldReader); +impl EN32K_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EN32K_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EN32K_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EN32K` writer - 32kHz Output Enable"] +pub struct EN32K_W<'a> { + w: &'a mut W, +} +impl<'a> EN32K_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `EN1K` reader - 1kHz Output Enable"] +pub struct EN1K_R(crate::FieldReader); +impl EN1K_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EN1K_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EN1K_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EN1K` writer - 1kHz Output Enable"] +pub struct EN1K_W<'a> { + w: &'a mut W, +} +impl<'a> EN1K_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - On Demand Control"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - On Demand Control"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Oscillator Start-Up Time\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum STARTUP_A { + #[doc = "0: 0.092 ms"] + CYCLE3 = 0, + #[doc = "1: 0.122 ms"] + CYCLE4 = 1, + #[doc = "2: 0.183 ms"] + CYCLE6 = 2, + #[doc = "3: 0.305 ms"] + CYCLE10 = 3, + #[doc = "4: 0.549 ms"] + CYCLE18 = 4, + #[doc = "5: 1.038 ms"] + CYCLE34 = 5, + #[doc = "6: 2.014 ms"] + CYCLE66 = 6, + #[doc = "7: 3.967 ms"] + CYCLE130 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: STARTUP_A) -> Self { + variant as _ + } +} +#[doc = "Field `STARTUP` reader - Oscillator Start-Up Time"] +pub struct STARTUP_R(crate::FieldReader); +impl STARTUP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + STARTUP_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STARTUP_A { + match self.bits { + 0 => STARTUP_A::CYCLE3, + 1 => STARTUP_A::CYCLE4, + 2 => STARTUP_A::CYCLE6, + 3 => STARTUP_A::CYCLE10, + 4 => STARTUP_A::CYCLE18, + 5 => STARTUP_A::CYCLE34, + 6 => STARTUP_A::CYCLE66, + 7 => STARTUP_A::CYCLE130, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `CYCLE3`"] + #[inline(always)] + pub fn is_cycle3(&self) -> bool { + **self == STARTUP_A::CYCLE3 + } + #[doc = "Checks if the value of the field is `CYCLE4`"] + #[inline(always)] + pub fn is_cycle4(&self) -> bool { + **self == STARTUP_A::CYCLE4 + } + #[doc = "Checks if the value of the field is `CYCLE6`"] + #[inline(always)] + pub fn is_cycle6(&self) -> bool { + **self == STARTUP_A::CYCLE6 + } + #[doc = "Checks if the value of the field is `CYCLE10`"] + #[inline(always)] + pub fn is_cycle10(&self) -> bool { + **self == STARTUP_A::CYCLE10 + } + #[doc = "Checks if the value of the field is `CYCLE18`"] + #[inline(always)] + pub fn is_cycle18(&self) -> bool { + **self == STARTUP_A::CYCLE18 + } + #[doc = "Checks if the value of the field is `CYCLE34`"] + #[inline(always)] + pub fn is_cycle34(&self) -> bool { + **self == STARTUP_A::CYCLE34 + } + #[doc = "Checks if the value of the field is `CYCLE66`"] + #[inline(always)] + pub fn is_cycle66(&self) -> bool { + **self == STARTUP_A::CYCLE66 + } + #[doc = "Checks if the value of the field is `CYCLE130`"] + #[inline(always)] + pub fn is_cycle130(&self) -> bool { + **self == STARTUP_A::CYCLE130 + } +} +impl core::ops::Deref for STARTUP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STARTUP` writer - Oscillator Start-Up Time"] +pub struct STARTUP_W<'a> { + w: &'a mut W, +} +impl<'a> STARTUP_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: STARTUP_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "0.092 ms"] + #[inline(always)] + pub fn cycle3(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE3) + } + #[doc = "0.122 ms"] + #[inline(always)] + pub fn cycle4(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE4) + } + #[doc = "0.183 ms"] + #[inline(always)] + pub fn cycle6(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE6) + } + #[doc = "0.305 ms"] + #[inline(always)] + pub fn cycle10(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE10) + } + #[doc = "0.549 ms"] + #[inline(always)] + pub fn cycle18(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE18) + } + #[doc = "1.038 ms"] + #[inline(always)] + pub fn cycle34(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE34) + } + #[doc = "2.014 ms"] + #[inline(always)] + pub fn cycle66(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE66) + } + #[doc = "3.967 ms"] + #[inline(always)] + pub fn cycle130(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE130) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +#[doc = "Field `WRTLOCK` reader - Write Lock"] +pub struct WRTLOCK_R(crate::FieldReader); +impl WRTLOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WRTLOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WRTLOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WRTLOCK` writer - Write Lock"] +pub struct WRTLOCK_W<'a> { + w: &'a mut W, +} +impl<'a> WRTLOCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `CALIB` reader - Oscillator Calibration"] +pub struct CALIB_R(crate::FieldReader); +impl CALIB_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CALIB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CALIB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CALIB` writer - Oscillator Calibration"] +pub struct CALIB_W<'a> { + w: &'a mut W, +} +impl<'a> CALIB_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x7f << 16)) | ((value as u32 & 0x7f) << 16); + self.w + } +} +impl R { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - 32kHz Output Enable"] + #[inline(always)] + pub fn en32k(&self) -> EN32K_R { + EN32K_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - 1kHz Output Enable"] + #[inline(always)] + pub fn en1k(&self) -> EN1K_R { + EN1K_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Oscillator Start-Up Time"] + #[inline(always)] + pub fn startup(&self) -> STARTUP_R { + STARTUP_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 12 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&self) -> WRTLOCK_R { + WRTLOCK_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bits 16:22 - Oscillator Calibration"] + #[inline(always)] + pub fn calib(&self) -> CALIB_R { + CALIB_R::new(((self.bits >> 16) & 0x7f) as u8) + } +} +impl W { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - 32kHz Output Enable"] + #[inline(always)] + pub fn en32k(&mut self) -> EN32K_W { + EN32K_W { w: self } + } + #[doc = "Bit 3 - 1kHz Output Enable"] + #[inline(always)] + pub fn en1k(&mut self) -> EN1K_W { + EN1K_W { w: self } + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Bits 8:10 - Oscillator Start-Up Time"] + #[inline(always)] + pub fn startup(&mut self) -> STARTUP_W { + STARTUP_W { w: self } + } + #[doc = "Bit 12 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&mut self) -> WRTLOCK_W { + WRTLOCK_W { w: self } + } + #[doc = "Bits 16:22 - Oscillator Calibration"] + #[inline(always)] + pub fn calib(&mut self) -> CALIB_W { + CALIB_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "32kHz Internal Oscillator (OSC32K) Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [osc32k](index.html) module"] +pub struct OSC32K_SPEC; +impl crate::RegisterSpec for OSC32K_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [osc32k::R](R) reader structure"] +impl crate::Readable for OSC32K_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [osc32k::W](W) writer structure"] +impl crate::Writable for OSC32K_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OSC32K to value 0x003f_0080"] +impl crate::Resettable for OSC32K_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x003f_0080 + } +} diff --git a/pac/atsamc20j/src/osc32kctrl/osculp32k.rs b/pac/atsamc20j/src/osc32kctrl/osculp32k.rs new file mode 100644 index 000000000000..1c351c406e59 --- /dev/null +++ b/pac/atsamc20j/src/osc32kctrl/osculp32k.rs @@ -0,0 +1,150 @@ +#[doc = "Register `OSCULP32K` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OSCULP32K` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CALIB` reader - Oscillator Calibration"] +pub struct CALIB_R(crate::FieldReader); +impl CALIB_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CALIB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CALIB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CALIB` writer - Oscillator Calibration"] +pub struct CALIB_W<'a> { + w: &'a mut W, +} +impl<'a> CALIB_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 8)) | ((value as u32 & 0x1f) << 8); + self.w + } +} +#[doc = "Field `WRTLOCK` reader - Write Lock"] +pub struct WRTLOCK_R(crate::FieldReader); +impl WRTLOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WRTLOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WRTLOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WRTLOCK` writer - Write Lock"] +pub struct WRTLOCK_W<'a> { + w: &'a mut W, +} +impl<'a> WRTLOCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bits 8:12 - Oscillator Calibration"] + #[inline(always)] + pub fn calib(&self) -> CALIB_R { + CALIB_R::new(((self.bits >> 8) & 0x1f) as u8) + } + #[doc = "Bit 15 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&self) -> WRTLOCK_R { + WRTLOCK_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 8:12 - Oscillator Calibration"] + #[inline(always)] + pub fn calib(&mut self) -> CALIB_W { + CALIB_W { w: self } + } + #[doc = "Bit 15 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&mut self) -> WRTLOCK_W { + WRTLOCK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [osculp32k](index.html) module"] +pub struct OSCULP32K_SPEC; +impl crate::RegisterSpec for OSCULP32K_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [osculp32k::R](R) reader structure"] +impl crate::Readable for OSCULP32K_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [osculp32k::W](W) writer structure"] +impl crate::Writable for OSCULP32K_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OSCULP32K to value 0"] +impl crate::Resettable for OSCULP32K_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/osc32kctrl/rtcctrl.rs b/pac/atsamc20j/src/osc32kctrl/rtcctrl.rs new file mode 100644 index 000000000000..1248024a03b9 --- /dev/null +++ b/pac/atsamc20j/src/osc32kctrl/rtcctrl.rs @@ -0,0 +1,204 @@ +#[doc = "Register `RTCCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RTCCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "RTC Clock Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum RTCSEL_A { + #[doc = "0: 1.024kHz from 32kHz internal ULP oscillator"] + ULP1K = 0, + #[doc = "1: 32.768kHz from 32kHz internal ULP oscillator"] + ULP32K = 1, + #[doc = "2: 1.024kHz from 32.768kHz internal oscillator"] + OSC1K = 2, + #[doc = "3: 32.768kHz from 32.768kHz internal oscillator"] + OSC32K = 3, + #[doc = "4: 1.024kHz from 32.768kHz internal oscillator"] + XOSC1K = 4, + #[doc = "5: 32.768kHz from 32.768kHz external crystal oscillator"] + XOSC32K = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RTCSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `RTCSEL` reader - RTC Clock Selection"] +pub struct RTCSEL_R(crate::FieldReader); +impl RTCSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RTCSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(RTCSEL_A::ULP1K), + 1 => Some(RTCSEL_A::ULP32K), + 2 => Some(RTCSEL_A::OSC1K), + 3 => Some(RTCSEL_A::OSC32K), + 4 => Some(RTCSEL_A::XOSC1K), + 5 => Some(RTCSEL_A::XOSC32K), + _ => None, + } + } + #[doc = "Checks if the value of the field is `ULP1K`"] + #[inline(always)] + pub fn is_ulp1k(&self) -> bool { + **self == RTCSEL_A::ULP1K + } + #[doc = "Checks if the value of the field is `ULP32K`"] + #[inline(always)] + pub fn is_ulp32k(&self) -> bool { + **self == RTCSEL_A::ULP32K + } + #[doc = "Checks if the value of the field is `OSC1K`"] + #[inline(always)] + pub fn is_osc1k(&self) -> bool { + **self == RTCSEL_A::OSC1K + } + #[doc = "Checks if the value of the field is `OSC32K`"] + #[inline(always)] + pub fn is_osc32k(&self) -> bool { + **self == RTCSEL_A::OSC32K + } + #[doc = "Checks if the value of the field is `XOSC1K`"] + #[inline(always)] + pub fn is_xosc1k(&self) -> bool { + **self == RTCSEL_A::XOSC1K + } + #[doc = "Checks if the value of the field is `XOSC32K`"] + #[inline(always)] + pub fn is_xosc32k(&self) -> bool { + **self == RTCSEL_A::XOSC32K + } +} +impl core::ops::Deref for RTCSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RTCSEL` writer - RTC Clock Selection"] +pub struct RTCSEL_W<'a> { + w: &'a mut W, +} +impl<'a> RTCSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RTCSEL_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "1.024kHz from 32kHz internal ULP oscillator"] + #[inline(always)] + pub fn ulp1k(self) -> &'a mut W { + self.variant(RTCSEL_A::ULP1K) + } + #[doc = "32.768kHz from 32kHz internal ULP oscillator"] + #[inline(always)] + pub fn ulp32k(self) -> &'a mut W { + self.variant(RTCSEL_A::ULP32K) + } + #[doc = "1.024kHz from 32.768kHz internal oscillator"] + #[inline(always)] + pub fn osc1k(self) -> &'a mut W { + self.variant(RTCSEL_A::OSC1K) + } + #[doc = "32.768kHz from 32.768kHz internal oscillator"] + #[inline(always)] + pub fn osc32k(self) -> &'a mut W { + self.variant(RTCSEL_A::OSC32K) + } + #[doc = "1.024kHz from 32.768kHz internal oscillator"] + #[inline(always)] + pub fn xosc1k(self) -> &'a mut W { + self.variant(RTCSEL_A::XOSC1K) + } + #[doc = "32.768kHz from 32.768kHz external crystal oscillator"] + #[inline(always)] + pub fn xosc32k(self) -> &'a mut W { + self.variant(RTCSEL_A::XOSC32K) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - RTC Clock Selection"] + #[inline(always)] + pub fn rtcsel(&self) -> RTCSEL_R { + RTCSEL_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - RTC Clock Selection"] + #[inline(always)] + pub fn rtcsel(&mut self) -> RTCSEL_W { + RTCSEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Clock selection\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rtcctrl](index.html) module"] +pub struct RTCCTRL_SPEC; +impl crate::RegisterSpec for RTCCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rtcctrl::R](R) reader structure"] +impl crate::Readable for RTCCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rtcctrl::W](W) writer structure"] +impl crate::Writable for RTCCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RTCCTRL to value 0"] +impl crate::Resettable for RTCCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/osc32kctrl/status.rs b/pac/atsamc20j/src/osc32kctrl/status.rs new file mode 100644 index 000000000000..f1f1483ac4e8 --- /dev/null +++ b/pac/atsamc20j/src/osc32kctrl/status.rs @@ -0,0 +1,113 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `XOSC32KRDY` reader - XOSC32K Ready"] +pub struct XOSC32KRDY_R(crate::FieldReader); +impl XOSC32KRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSC32KRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC32KRDY` reader - OSC32K Ready"] +pub struct OSC32KRDY_R(crate::FieldReader); +impl OSC32KRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC32KRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKFAIL` reader - XOSC32K Clock Failure Detector"] +pub struct CLKFAIL_R(crate::FieldReader); +impl CLKFAIL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKFAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKFAIL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKSW` reader - XOSC32K Clock switch"] +pub struct CLKSW_R(crate::FieldReader); +impl CLKSW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKSW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKSW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - XOSC32K Ready"] + #[inline(always)] + pub fn xosc32krdy(&self) -> XOSC32KRDY_R { + XOSC32KRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - OSC32K Ready"] + #[inline(always)] + pub fn osc32krdy(&self) -> OSC32KRDY_R { + OSC32KRDY_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - XOSC32K Clock Failure Detector"] + #[inline(always)] + pub fn clkfail(&self) -> CLKFAIL_R { + CLKFAIL_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - XOSC32K Clock switch"] + #[inline(always)] + pub fn clksw(&self) -> CLKSW_R { + CLKSW_R::new(((self.bits >> 3) & 0x01) != 0) + } +} +#[doc = "Power and Clocks Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/osc32kctrl/xosc32k.rs b/pac/atsamc20j/src/osc32kctrl/xosc32k.rs new file mode 100644 index 000000000000..93e42bba3c0e --- /dev/null +++ b/pac/atsamc20j/src/osc32kctrl/xosc32k.rs @@ -0,0 +1,559 @@ +#[doc = "Register `XOSC32K` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `XOSC32K` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Oscillator Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Oscillator Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `XTALEN` reader - Crystal Oscillator Enable"] +pub struct XTALEN_R(crate::FieldReader); +impl XTALEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XTALEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XTALEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XTALEN` writer - Crystal Oscillator Enable"] +pub struct XTALEN_W<'a> { + w: &'a mut W, +} +impl<'a> XTALEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `EN32K` reader - 32kHz Output Enable"] +pub struct EN32K_R(crate::FieldReader); +impl EN32K_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EN32K_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EN32K_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EN32K` writer - 32kHz Output Enable"] +pub struct EN32K_W<'a> { + w: &'a mut W, +} +impl<'a> EN32K_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `EN1K` reader - 1kHz Output Enable"] +pub struct EN1K_R(crate::FieldReader); +impl EN1K_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EN1K_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EN1K_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EN1K` writer - 1kHz Output Enable"] +pub struct EN1K_W<'a> { + w: &'a mut W, +} +impl<'a> EN1K_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - On Demand Control"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - On Demand Control"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Oscillator Start-Up Time\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum STARTUP_A { + #[doc = "0: 0.122 ms"] + CYCLE1 = 0, + #[doc = "1: 1.068 ms"] + CYCLE32 = 1, + #[doc = "2: 62.6 ms"] + CYCLE2048 = 2, + #[doc = "3: 125 ms"] + CYCLE4096 = 3, + #[doc = "4: 500 ms"] + CYCLE16384 = 4, + #[doc = "5: 1000 ms"] + CYCLE32768 = 5, + #[doc = "6: 2000 ms"] + CYCLE65536 = 6, + #[doc = "7: 4000 ms"] + CYCLE131072 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: STARTUP_A) -> Self { + variant as _ + } +} +#[doc = "Field `STARTUP` reader - Oscillator Start-Up Time"] +pub struct STARTUP_R(crate::FieldReader); +impl STARTUP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + STARTUP_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STARTUP_A { + match self.bits { + 0 => STARTUP_A::CYCLE1, + 1 => STARTUP_A::CYCLE32, + 2 => STARTUP_A::CYCLE2048, + 3 => STARTUP_A::CYCLE4096, + 4 => STARTUP_A::CYCLE16384, + 5 => STARTUP_A::CYCLE32768, + 6 => STARTUP_A::CYCLE65536, + 7 => STARTUP_A::CYCLE131072, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `CYCLE1`"] + #[inline(always)] + pub fn is_cycle1(&self) -> bool { + **self == STARTUP_A::CYCLE1 + } + #[doc = "Checks if the value of the field is `CYCLE32`"] + #[inline(always)] + pub fn is_cycle32(&self) -> bool { + **self == STARTUP_A::CYCLE32 + } + #[doc = "Checks if the value of the field is `CYCLE2048`"] + #[inline(always)] + pub fn is_cycle2048(&self) -> bool { + **self == STARTUP_A::CYCLE2048 + } + #[doc = "Checks if the value of the field is `CYCLE4096`"] + #[inline(always)] + pub fn is_cycle4096(&self) -> bool { + **self == STARTUP_A::CYCLE4096 + } + #[doc = "Checks if the value of the field is `CYCLE16384`"] + #[inline(always)] + pub fn is_cycle16384(&self) -> bool { + **self == STARTUP_A::CYCLE16384 + } + #[doc = "Checks if the value of the field is `CYCLE32768`"] + #[inline(always)] + pub fn is_cycle32768(&self) -> bool { + **self == STARTUP_A::CYCLE32768 + } + #[doc = "Checks if the value of the field is `CYCLE65536`"] + #[inline(always)] + pub fn is_cycle65536(&self) -> bool { + **self == STARTUP_A::CYCLE65536 + } + #[doc = "Checks if the value of the field is `CYCLE131072`"] + #[inline(always)] + pub fn is_cycle131072(&self) -> bool { + **self == STARTUP_A::CYCLE131072 + } +} +impl core::ops::Deref for STARTUP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STARTUP` writer - Oscillator Start-Up Time"] +pub struct STARTUP_W<'a> { + w: &'a mut W, +} +impl<'a> STARTUP_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: STARTUP_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "0.122 ms"] + #[inline(always)] + pub fn cycle1(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE1) + } + #[doc = "1.068 ms"] + #[inline(always)] + pub fn cycle32(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE32) + } + #[doc = "62.6 ms"] + #[inline(always)] + pub fn cycle2048(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE2048) + } + #[doc = "125 ms"] + #[inline(always)] + pub fn cycle4096(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE4096) + } + #[doc = "500 ms"] + #[inline(always)] + pub fn cycle16384(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE16384) + } + #[doc = "1000 ms"] + #[inline(always)] + pub fn cycle32768(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE32768) + } + #[doc = "2000 ms"] + #[inline(always)] + pub fn cycle65536(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE65536) + } + #[doc = "4000 ms"] + #[inline(always)] + pub fn cycle131072(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE131072) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u16 & 0x07) << 8); + self.w + } +} +#[doc = "Field `WRTLOCK` reader - Write Lock"] +pub struct WRTLOCK_R(crate::FieldReader); +impl WRTLOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WRTLOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WRTLOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WRTLOCK` writer - Write Lock"] +pub struct WRTLOCK_W<'a> { + w: &'a mut W, +} +impl<'a> WRTLOCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u16 & 0x01) << 12); + self.w + } +} +impl R { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Crystal Oscillator Enable"] + #[inline(always)] + pub fn xtalen(&self) -> XTALEN_R { + XTALEN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - 32kHz Output Enable"] + #[inline(always)] + pub fn en32k(&self) -> EN32K_R { + EN32K_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - 1kHz Output Enable"] + #[inline(always)] + pub fn en1k(&self) -> EN1K_R { + EN1K_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Oscillator Start-Up Time"] + #[inline(always)] + pub fn startup(&self) -> STARTUP_R { + STARTUP_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 12 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&self) -> WRTLOCK_R { + WRTLOCK_R::new(((self.bits >> 12) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - Crystal Oscillator Enable"] + #[inline(always)] + pub fn xtalen(&mut self) -> XTALEN_W { + XTALEN_W { w: self } + } + #[doc = "Bit 3 - 32kHz Output Enable"] + #[inline(always)] + pub fn en32k(&mut self) -> EN32K_W { + EN32K_W { w: self } + } + #[doc = "Bit 4 - 1kHz Output Enable"] + #[inline(always)] + pub fn en1k(&mut self) -> EN1K_W { + EN1K_W { w: self } + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Bits 8:10 - Oscillator Start-Up Time"] + #[inline(always)] + pub fn startup(&mut self) -> STARTUP_W { + STARTUP_W { w: self } + } + #[doc = "Bit 12 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&mut self) -> WRTLOCK_W { + WRTLOCK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "32kHz External Crystal Oscillator (XOSC32K) Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [xosc32k](index.html) module"] +pub struct XOSC32K_SPEC; +impl crate::RegisterSpec for XOSC32K_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [xosc32k::R](R) reader structure"] +impl crate::Readable for XOSC32K_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [xosc32k::W](W) writer structure"] +impl crate::Writable for XOSC32K_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets XOSC32K to value 0x80"] +impl crate::Resettable for XOSC32K_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x80 + } +} diff --git a/pac/atsamc20j/src/oscctrl.rs b/pac/atsamc20j/src/oscctrl.rs new file mode 100644 index 000000000000..e6dd0929927c --- /dev/null +++ b/pac/atsamc20j/src/oscctrl.rs @@ -0,0 +1,117 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x04 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x08 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x0c - Power and Clocks Status"] + pub status: crate::Reg, + #[doc = "0x10 - External Multipurpose Crystal Oscillator (XOSC) Control"] + pub xoscctrl: crate::Reg, + #[doc = "0x12 - Clock Failure Detector Prescaler"] + pub cfdpresc: crate::Reg, + #[doc = "0x13 - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x14 - 48MHz Internal Oscillator (OSC48M) Control"] + pub osc48mctrl: crate::Reg, + #[doc = "0x15 - OSC48M Divider"] + pub osc48mdiv: crate::Reg, + #[doc = "0x16 - OSC48M Startup Time"] + pub osc48mstup: crate::Reg, + _reserved10: [u8; 0x01], + #[doc = "0x18 - OSC48M Synchronization Busy"] + pub osc48msyncbusy: crate::Reg, + #[doc = "0x1c - DPLL Control"] + pub dpllctrla: crate::Reg, + _reserved12: [u8; 0x03], + #[doc = "0x20 - DPLL Ratio Control"] + pub dpllratio: crate::Reg, + #[doc = "0x24 - Digital Core Configuration"] + pub dpllctrlb: crate::Reg, + #[doc = "0x28 - DPLL Prescaler"] + pub dpllpresc: crate::Reg, + _reserved15: [u8; 0x03], + #[doc = "0x2c - DPLL Synchronization Busy"] + pub dpllsyncbusy: crate::Reg, + _reserved16: [u8; 0x03], + #[doc = "0x30 - DPLL Status"] + pub dpllstatus: crate::Reg, + _reserved17: [u8; 0x07], + #[doc = "0x38 - 48MHz Oscillator Calibration"] + pub cal48m: crate::Reg, +} +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Power and Clocks Status"] +pub mod status; +#[doc = "XOSCCTRL register accessor: an alias for `Reg`"] +pub type XOSCCTRL = crate::Reg; +#[doc = "External Multipurpose Crystal Oscillator (XOSC) Control"] +pub mod xoscctrl; +#[doc = "CFDPRESC register accessor: an alias for `Reg`"] +pub type CFDPRESC = crate::Reg; +#[doc = "Clock Failure Detector Prescaler"] +pub mod cfdpresc; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "OSC48MCTRL register accessor: an alias for `Reg`"] +pub type OSC48MCTRL = crate::Reg; +#[doc = "48MHz Internal Oscillator (OSC48M) Control"] +pub mod osc48mctrl; +#[doc = "OSC48MDIV register accessor: an alias for `Reg`"] +pub type OSC48MDIV = crate::Reg; +#[doc = "OSC48M Divider"] +pub mod osc48mdiv; +#[doc = "OSC48MSTUP register accessor: an alias for `Reg`"] +pub type OSC48MSTUP = crate::Reg; +#[doc = "OSC48M Startup Time"] +pub mod osc48mstup; +#[doc = "OSC48MSYNCBUSY register accessor: an alias for `Reg`"] +pub type OSC48MSYNCBUSY = crate::Reg; +#[doc = "OSC48M Synchronization Busy"] +pub mod osc48msyncbusy; +#[doc = "DPLLCTRLA register accessor: an alias for `Reg`"] +pub type DPLLCTRLA = crate::Reg; +#[doc = "DPLL Control"] +pub mod dpllctrla; +#[doc = "DPLLRATIO register accessor: an alias for `Reg`"] +pub type DPLLRATIO = crate::Reg; +#[doc = "DPLL Ratio Control"] +pub mod dpllratio; +#[doc = "DPLLCTRLB register accessor: an alias for `Reg`"] +pub type DPLLCTRLB = crate::Reg; +#[doc = "Digital Core Configuration"] +pub mod dpllctrlb; +#[doc = "DPLLPRESC register accessor: an alias for `Reg`"] +pub type DPLLPRESC = crate::Reg; +#[doc = "DPLL Prescaler"] +pub mod dpllpresc; +#[doc = "DPLLSYNCBUSY register accessor: an alias for `Reg`"] +pub type DPLLSYNCBUSY = crate::Reg; +#[doc = "DPLL Synchronization Busy"] +pub mod dpllsyncbusy; +#[doc = "DPLLSTATUS register accessor: an alias for `Reg`"] +pub type DPLLSTATUS = crate::Reg; +#[doc = "DPLL Status"] +pub mod dpllstatus; +#[doc = "CAL48M register accessor: an alias for `Reg`"] +pub type CAL48M = crate::Reg; +#[doc = "48MHz Oscillator Calibration"] +pub mod cal48m; diff --git a/pac/atsamc20j/src/oscctrl/cal48m.rs b/pac/atsamc20j/src/oscctrl/cal48m.rs new file mode 100644 index 000000000000..05d5cd2bbc92 --- /dev/null +++ b/pac/atsamc20j/src/oscctrl/cal48m.rs @@ -0,0 +1,177 @@ +#[doc = "Register `CAL48M` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CAL48M` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FCAL` reader - Frequency Calibration (48MHz)"] +pub struct FCAL_R(crate::FieldReader); +impl FCAL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FCAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FCAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FCAL` writer - Frequency Calibration (48MHz)"] +pub struct FCAL_W<'a> { + w: &'a mut W, +} +impl<'a> FCAL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +#[doc = "Field `FRANGE` reader - Frequency Range (48MHz)"] +pub struct FRANGE_R(crate::FieldReader); +impl FRANGE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FRANGE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FRANGE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FRANGE` writer - Frequency Range (48MHz)"] +pub struct FRANGE_W<'a> { + w: &'a mut W, +} +impl<'a> FRANGE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 8)) | ((value as u32 & 0x03) << 8); + self.w + } +} +#[doc = "Field `TCAL` reader - Temperature Calibration (48MHz)"] +pub struct TCAL_R(crate::FieldReader); +impl TCAL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TCAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCAL` writer - Temperature Calibration (48MHz)"] +pub struct TCAL_W<'a> { + w: &'a mut W, +} +impl<'a> TCAL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 16)) | ((value as u32 & 0x3f) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Frequency Calibration (48MHz)"] + #[inline(always)] + pub fn fcal(&self) -> FCAL_R { + FCAL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 8:9 - Frequency Range (48MHz)"] + #[inline(always)] + pub fn frange(&self) -> FRANGE_R { + FRANGE_R::new(((self.bits >> 8) & 0x03) as u8) + } + #[doc = "Bits 16:21 - Temperature Calibration (48MHz)"] + #[inline(always)] + pub fn tcal(&self) -> TCAL_R { + TCAL_R::new(((self.bits >> 16) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - Frequency Calibration (48MHz)"] + #[inline(always)] + pub fn fcal(&mut self) -> FCAL_W { + FCAL_W { w: self } + } + #[doc = "Bits 8:9 - Frequency Range (48MHz)"] + #[inline(always)] + pub fn frange(&mut self) -> FRANGE_W { + FRANGE_W { w: self } + } + #[doc = "Bits 16:21 - Temperature Calibration (48MHz)"] + #[inline(always)] + pub fn tcal(&mut self) -> TCAL_W { + TCAL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "48MHz Oscillator Calibration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cal48m](index.html) module"] +pub struct CAL48M_SPEC; +impl crate::RegisterSpec for CAL48M_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cal48m::R](R) reader structure"] +impl crate::Readable for CAL48M_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cal48m::W](W) writer structure"] +impl crate::Writable for CAL48M_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CAL48M to value 0"] +impl crate::Resettable for CAL48M_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/oscctrl/cfdpresc.rs b/pac/atsamc20j/src/oscctrl/cfdpresc.rs new file mode 100644 index 000000000000..029ae541eec5 --- /dev/null +++ b/pac/atsamc20j/src/oscctrl/cfdpresc.rs @@ -0,0 +1,230 @@ +#[doc = "Register `CFDPRESC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CFDPRESC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Clock Failure Detector Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CFDPRESC_A { + #[doc = "0: 48 MHz"] + DIV1 = 0, + #[doc = "1: 24 MHz"] + DIV2 = 1, + #[doc = "2: 12 MHz"] + DIV4 = 2, + #[doc = "3: 6 MHz"] + DIV8 = 3, + #[doc = "4: 3 MHz"] + DIV16 = 4, + #[doc = "5: 1.5 MHz"] + DIV32 = 5, + #[doc = "6: 0.75 MHz"] + DIV64 = 6, + #[doc = "7: 0.3125 MHz"] + DIV128 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CFDPRESC_A) -> Self { + variant as _ + } +} +#[doc = "Field `CFDPRESC` reader - Clock Failure Detector Prescaler"] +pub struct CFDPRESC_R(crate::FieldReader); +impl CFDPRESC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CFDPRESC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CFDPRESC_A { + match self.bits { + 0 => CFDPRESC_A::DIV1, + 1 => CFDPRESC_A::DIV2, + 2 => CFDPRESC_A::DIV4, + 3 => CFDPRESC_A::DIV8, + 4 => CFDPRESC_A::DIV16, + 5 => CFDPRESC_A::DIV32, + 6 => CFDPRESC_A::DIV64, + 7 => CFDPRESC_A::DIV128, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == CFDPRESC_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == CFDPRESC_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == CFDPRESC_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == CFDPRESC_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == CFDPRESC_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == CFDPRESC_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == CFDPRESC_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == CFDPRESC_A::DIV128 + } +} +impl core::ops::Deref for CFDPRESC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFDPRESC` writer - Clock Failure Detector Prescaler"] +pub struct CFDPRESC_W<'a> { + w: &'a mut W, +} +impl<'a> CFDPRESC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CFDPRESC_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "48 MHz"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(CFDPRESC_A::DIV1) + } + #[doc = "24 MHz"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(CFDPRESC_A::DIV2) + } + #[doc = "12 MHz"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(CFDPRESC_A::DIV4) + } + #[doc = "6 MHz"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(CFDPRESC_A::DIV8) + } + #[doc = "3 MHz"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(CFDPRESC_A::DIV16) + } + #[doc = "1.5 MHz"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(CFDPRESC_A::DIV32) + } + #[doc = "0.75 MHz"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(CFDPRESC_A::DIV64) + } + #[doc = "0.3125 MHz"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(CFDPRESC_A::DIV128) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Clock Failure Detector Prescaler"] + #[inline(always)] + pub fn cfdpresc(&self) -> CFDPRESC_R { + CFDPRESC_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Clock Failure Detector Prescaler"] + #[inline(always)] + pub fn cfdpresc(&mut self) -> CFDPRESC_W { + CFDPRESC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Clock Failure Detector Prescaler\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cfdpresc](index.html) module"] +pub struct CFDPRESC_SPEC; +impl crate::RegisterSpec for CFDPRESC_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [cfdpresc::R](R) reader structure"] +impl crate::Readable for CFDPRESC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cfdpresc::W](W) writer structure"] +impl crate::Writable for CFDPRESC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CFDPRESC to value 0"] +impl crate::Resettable for CFDPRESC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/oscctrl/dpllctrla.rs b/pac/atsamc20j/src/oscctrl/dpllctrla.rs new file mode 100644 index 000000000000..5a60a5087002 --- /dev/null +++ b/pac/atsamc20j/src/oscctrl/dpllctrla.rs @@ -0,0 +1,207 @@ +#[doc = "Register `DPLLCTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DPLLCTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - On Demand"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - On Demand"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - On Demand"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - On Demand"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DPLL Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dpllctrla](index.html) module"] +pub struct DPLLCTRLA_SPEC; +impl crate::RegisterSpec for DPLLCTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dpllctrla::R](R) reader structure"] +impl crate::Readable for DPLLCTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dpllctrla::W](W) writer structure"] +impl crate::Writable for DPLLCTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DPLLCTRLA to value 0x80"] +impl crate::Resettable for DPLLCTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x80 + } +} diff --git a/pac/atsamc20j/src/oscctrl/dpllctrlb.rs b/pac/atsamc20j/src/oscctrl/dpllctrlb.rs new file mode 100644 index 000000000000..8400b0572dd0 --- /dev/null +++ b/pac/atsamc20j/src/oscctrl/dpllctrlb.rs @@ -0,0 +1,580 @@ +#[doc = "Register `DPLLCTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DPLLCTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Proportional Integral Filter Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FILTER_A { + #[doc = "0: Default filter mode"] + DEFAULT = 0, + #[doc = "1: Low bandwidth filter"] + LBFILT = 1, + #[doc = "2: High bandwidth filter"] + HBFILT = 2, + #[doc = "3: High damping filter"] + HDFILT = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FILTER_A) -> Self { + variant as _ + } +} +#[doc = "Field `FILTER` reader - Proportional Integral Filter Selection"] +pub struct FILTER_R(crate::FieldReader); +impl FILTER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FILTER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FILTER_A { + match self.bits { + 0 => FILTER_A::DEFAULT, + 1 => FILTER_A::LBFILT, + 2 => FILTER_A::HBFILT, + 3 => FILTER_A::HDFILT, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DEFAULT`"] + #[inline(always)] + pub fn is_default(&self) -> bool { + **self == FILTER_A::DEFAULT + } + #[doc = "Checks if the value of the field is `LBFILT`"] + #[inline(always)] + pub fn is_lbfilt(&self) -> bool { + **self == FILTER_A::LBFILT + } + #[doc = "Checks if the value of the field is `HBFILT`"] + #[inline(always)] + pub fn is_hbfilt(&self) -> bool { + **self == FILTER_A::HBFILT + } + #[doc = "Checks if the value of the field is `HDFILT`"] + #[inline(always)] + pub fn is_hdfilt(&self) -> bool { + **self == FILTER_A::HDFILT + } +} +impl core::ops::Deref for FILTER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTER` writer - Proportional Integral Filter Selection"] +pub struct FILTER_W<'a> { + w: &'a mut W, +} +impl<'a> FILTER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FILTER_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Default filter mode"] + #[inline(always)] + pub fn default(self) -> &'a mut W { + self.variant(FILTER_A::DEFAULT) + } + #[doc = "Low bandwidth filter"] + #[inline(always)] + pub fn lbfilt(self) -> &'a mut W { + self.variant(FILTER_A::LBFILT) + } + #[doc = "High bandwidth filter"] + #[inline(always)] + pub fn hbfilt(self) -> &'a mut W { + self.variant(FILTER_A::HBFILT) + } + #[doc = "High damping filter"] + #[inline(always)] + pub fn hdfilt(self) -> &'a mut W { + self.variant(FILTER_A::HDFILT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u32 & 0x03); + self.w + } +} +#[doc = "Field `LPEN` reader - Low-Power Enable"] +pub struct LPEN_R(crate::FieldReader); +impl LPEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LPEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LPEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LPEN` writer - Low-Power Enable"] +pub struct LPEN_W<'a> { + w: &'a mut W, +} +impl<'a> LPEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `WUF` reader - Wake Up Fast"] +pub struct WUF_R(crate::FieldReader); +impl WUF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WUF` writer - Wake Up Fast"] +pub struct WUF_W<'a> { + w: &'a mut W, +} +impl<'a> WUF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Reference Clock Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum REFCLK_A { + #[doc = "0: XOSC32K clock reference"] + XOSC32K = 0, + #[doc = "1: XOSC clock reference"] + XOSC = 1, + #[doc = "2: GCLK clock reference"] + GCLK = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: REFCLK_A) -> Self { + variant as _ + } +} +#[doc = "Field `REFCLK` reader - Reference Clock Selection"] +pub struct REFCLK_R(crate::FieldReader); +impl REFCLK_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REFCLK_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(REFCLK_A::XOSC32K), + 1 => Some(REFCLK_A::XOSC), + 2 => Some(REFCLK_A::GCLK), + _ => None, + } + } + #[doc = "Checks if the value of the field is `XOSC32K`"] + #[inline(always)] + pub fn is_xosc32k(&self) -> bool { + **self == REFCLK_A::XOSC32K + } + #[doc = "Checks if the value of the field is `XOSC`"] + #[inline(always)] + pub fn is_xosc(&self) -> bool { + **self == REFCLK_A::XOSC + } + #[doc = "Checks if the value of the field is `GCLK`"] + #[inline(always)] + pub fn is_gclk(&self) -> bool { + **self == REFCLK_A::GCLK + } +} +impl core::ops::Deref for REFCLK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REFCLK` writer - Reference Clock Selection"] +pub struct REFCLK_W<'a> { + w: &'a mut W, +} +impl<'a> REFCLK_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: REFCLK_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "XOSC32K clock reference"] + #[inline(always)] + pub fn xosc32k(self) -> &'a mut W { + self.variant(REFCLK_A::XOSC32K) + } + #[doc = "XOSC clock reference"] + #[inline(always)] + pub fn xosc(self) -> &'a mut W { + self.variant(REFCLK_A::XOSC) + } + #[doc = "GCLK clock reference"] + #[inline(always)] + pub fn gclk(self) -> &'a mut W { + self.variant(REFCLK_A::GCLK) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u32 & 0x03) << 4); + self.w + } +} +#[doc = "Lock Time\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum LTIME_A { + #[doc = "0: No time-out. Automatic lock."] + DEFAULT = 0, + #[doc = "4: Time-out if no lock within 8ms"] + _8MS = 4, + #[doc = "5: Time-out if no lock within 9ms"] + _9MS = 5, + #[doc = "6: Time-out if no lock within 10ms"] + _10MS = 6, + #[doc = "7: Time-out if no lock within 11ms"] + _11MS = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LTIME_A) -> Self { + variant as _ + } +} +#[doc = "Field `LTIME` reader - Lock Time"] +pub struct LTIME_R(crate::FieldReader); +impl LTIME_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LTIME_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(LTIME_A::DEFAULT), + 4 => Some(LTIME_A::_8MS), + 5 => Some(LTIME_A::_9MS), + 6 => Some(LTIME_A::_10MS), + 7 => Some(LTIME_A::_11MS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DEFAULT`"] + #[inline(always)] + pub fn is_default(&self) -> bool { + **self == LTIME_A::DEFAULT + } + #[doc = "Checks if the value of the field is `_8MS`"] + #[inline(always)] + pub fn is_8ms(&self) -> bool { + **self == LTIME_A::_8MS + } + #[doc = "Checks if the value of the field is `_9MS`"] + #[inline(always)] + pub fn is_9ms(&self) -> bool { + **self == LTIME_A::_9MS + } + #[doc = "Checks if the value of the field is `_10MS`"] + #[inline(always)] + pub fn is_10ms(&self) -> bool { + **self == LTIME_A::_10MS + } + #[doc = "Checks if the value of the field is `_11MS`"] + #[inline(always)] + pub fn is_11ms(&self) -> bool { + **self == LTIME_A::_11MS + } +} +impl core::ops::Deref for LTIME_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LTIME` writer - Lock Time"] +pub struct LTIME_W<'a> { + w: &'a mut W, +} +impl<'a> LTIME_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: LTIME_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No time-out. Automatic lock."] + #[inline(always)] + pub fn default(self) -> &'a mut W { + self.variant(LTIME_A::DEFAULT) + } + #[doc = "Time-out if no lock within 8ms"] + #[inline(always)] + pub fn _8ms(self) -> &'a mut W { + self.variant(LTIME_A::_8MS) + } + #[doc = "Time-out if no lock within 9ms"] + #[inline(always)] + pub fn _9ms(self) -> &'a mut W { + self.variant(LTIME_A::_9MS) + } + #[doc = "Time-out if no lock within 10ms"] + #[inline(always)] + pub fn _10ms(self) -> &'a mut W { + self.variant(LTIME_A::_10MS) + } + #[doc = "Time-out if no lock within 11ms"] + #[inline(always)] + pub fn _11ms(self) -> &'a mut W { + self.variant(LTIME_A::_11MS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +#[doc = "Field `LBYPASS` reader - Lock Bypass"] +pub struct LBYPASS_R(crate::FieldReader); +impl LBYPASS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LBYPASS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LBYPASS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LBYPASS` writer - Lock Bypass"] +pub struct LBYPASS_W<'a> { + w: &'a mut W, +} +impl<'a> LBYPASS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `DIV` reader - Clock Divider"] +pub struct DIV_R(crate::FieldReader); +impl DIV_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + DIV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIV` writer - Clock Divider"] +pub struct DIV_W<'a> { + w: &'a mut W, +} +impl<'a> DIV_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07ff << 16)) | ((value as u32 & 0x07ff) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Proportional Integral Filter Selection"] + #[inline(always)] + pub fn filter(&self) -> FILTER_R { + FILTER_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bit 2 - Low-Power Enable"] + #[inline(always)] + pub fn lpen(&self) -> LPEN_R { + LPEN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Wake Up Fast"] + #[inline(always)] + pub fn wuf(&self) -> WUF_R { + WUF_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bits 4:5 - Reference Clock Selection"] + #[inline(always)] + pub fn refclk(&self) -> REFCLK_R { + REFCLK_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bits 8:10 - Lock Time"] + #[inline(always)] + pub fn ltime(&self) -> LTIME_R { + LTIME_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 12 - Lock Bypass"] + #[inline(always)] + pub fn lbypass(&self) -> LBYPASS_R { + LBYPASS_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bits 16:26 - Clock Divider"] + #[inline(always)] + pub fn div(&self) -> DIV_R { + DIV_R::new(((self.bits >> 16) & 0x07ff) as u16) + } +} +impl W { + #[doc = "Bits 0:1 - Proportional Integral Filter Selection"] + #[inline(always)] + pub fn filter(&mut self) -> FILTER_W { + FILTER_W { w: self } + } + #[doc = "Bit 2 - Low-Power Enable"] + #[inline(always)] + pub fn lpen(&mut self) -> LPEN_W { + LPEN_W { w: self } + } + #[doc = "Bit 3 - Wake Up Fast"] + #[inline(always)] + pub fn wuf(&mut self) -> WUF_W { + WUF_W { w: self } + } + #[doc = "Bits 4:5 - Reference Clock Selection"] + #[inline(always)] + pub fn refclk(&mut self) -> REFCLK_W { + REFCLK_W { w: self } + } + #[doc = "Bits 8:10 - Lock Time"] + #[inline(always)] + pub fn ltime(&mut self) -> LTIME_W { + LTIME_W { w: self } + } + #[doc = "Bit 12 - Lock Bypass"] + #[inline(always)] + pub fn lbypass(&mut self) -> LBYPASS_W { + LBYPASS_W { w: self } + } + #[doc = "Bits 16:26 - Clock Divider"] + #[inline(always)] + pub fn div(&mut self) -> DIV_W { + DIV_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Digital Core Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dpllctrlb](index.html) module"] +pub struct DPLLCTRLB_SPEC; +impl crate::RegisterSpec for DPLLCTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dpllctrlb::R](R) reader structure"] +impl crate::Readable for DPLLCTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dpllctrlb::W](W) writer structure"] +impl crate::Writable for DPLLCTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DPLLCTRLB to value 0"] +impl crate::Resettable for DPLLCTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/oscctrl/dpllpresc.rs b/pac/atsamc20j/src/oscctrl/dpllpresc.rs new file mode 100644 index 000000000000..9de662161f99 --- /dev/null +++ b/pac/atsamc20j/src/oscctrl/dpllpresc.rs @@ -0,0 +1,165 @@ +#[doc = "Register `DPLLPRESC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DPLLPRESC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Output Clock Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESC_A { + #[doc = "0: DPLL output is divided by 1"] + DIV1 = 0, + #[doc = "1: DPLL output is divided by 2"] + DIV2 = 1, + #[doc = "2: DPLL output is divided by 4"] + DIV4 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESC_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESC` reader - Output Clock Prescaler"] +pub struct PRESC_R(crate::FieldReader); +impl PRESC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESC_A::DIV1), + 1 => Some(PRESC_A::DIV2), + 2 => Some(PRESC_A::DIV4), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == PRESC_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESC_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESC_A::DIV4 + } +} +impl core::ops::Deref for PRESC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESC` writer - Output Clock Prescaler"] +pub struct PRESC_W<'a> { + w: &'a mut W, +} +impl<'a> PRESC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESC_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "DPLL output is divided by 1"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESC_A::DIV1) + } + #[doc = "DPLL output is divided by 2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESC_A::DIV2) + } + #[doc = "DPLL output is divided by 4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESC_A::DIV4) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u8 & 0x03); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Output Clock Prescaler"] + #[inline(always)] + pub fn presc(&self) -> PRESC_R { + PRESC_R::new((self.bits & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Output Clock Prescaler"] + #[inline(always)] + pub fn presc(&mut self) -> PRESC_W { + PRESC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DPLL Prescaler\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dpllpresc](index.html) module"] +pub struct DPLLPRESC_SPEC; +impl crate::RegisterSpec for DPLLPRESC_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dpllpresc::R](R) reader structure"] +impl crate::Readable for DPLLPRESC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dpllpresc::W](W) writer structure"] +impl crate::Writable for DPLLPRESC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DPLLPRESC to value 0"] +impl crate::Resettable for DPLLPRESC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/oscctrl/dpllratio.rs b/pac/atsamc20j/src/oscctrl/dpllratio.rs new file mode 100644 index 000000000000..93b39e30f1a5 --- /dev/null +++ b/pac/atsamc20j/src/oscctrl/dpllratio.rs @@ -0,0 +1,140 @@ +#[doc = "Register `DPLLRATIO` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DPLLRATIO` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `LDR` reader - Loop Divider Ratio"] +pub struct LDR_R(crate::FieldReader); +impl LDR_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + LDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LDR` writer - Loop Divider Ratio"] +pub struct LDR_W<'a> { + w: &'a mut W, +} +impl<'a> LDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0fff) | (value as u32 & 0x0fff); + self.w + } +} +#[doc = "Field `LDRFRAC` reader - Loop Divider Ratio Fractional Part"] +pub struct LDRFRAC_R(crate::FieldReader); +impl LDRFRAC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LDRFRAC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LDRFRAC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LDRFRAC` writer - Loop Divider Ratio Fractional Part"] +pub struct LDRFRAC_W<'a> { + w: &'a mut W, +} +impl<'a> LDRFRAC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 16)) | ((value as u32 & 0x0f) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:11 - Loop Divider Ratio"] + #[inline(always)] + pub fn ldr(&self) -> LDR_R { + LDR_R::new((self.bits & 0x0fff) as u16) + } + #[doc = "Bits 16:19 - Loop Divider Ratio Fractional Part"] + #[inline(always)] + pub fn ldrfrac(&self) -> LDRFRAC_R { + LDRFRAC_R::new(((self.bits >> 16) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:11 - Loop Divider Ratio"] + #[inline(always)] + pub fn ldr(&mut self) -> LDR_W { + LDR_W { w: self } + } + #[doc = "Bits 16:19 - Loop Divider Ratio Fractional Part"] + #[inline(always)] + pub fn ldrfrac(&mut self) -> LDRFRAC_W { + LDRFRAC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DPLL Ratio Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dpllratio](index.html) module"] +pub struct DPLLRATIO_SPEC; +impl crate::RegisterSpec for DPLLRATIO_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dpllratio::R](R) reader structure"] +impl crate::Readable for DPLLRATIO_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dpllratio::W](W) writer structure"] +impl crate::Writable for DPLLRATIO_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DPLLRATIO to value 0"] +impl crate::Resettable for DPLLRATIO_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/oscctrl/dpllstatus.rs b/pac/atsamc20j/src/oscctrl/dpllstatus.rs new file mode 100644 index 000000000000..931900212816 --- /dev/null +++ b/pac/atsamc20j/src/oscctrl/dpllstatus.rs @@ -0,0 +1,73 @@ +#[doc = "Register `DPLLSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `LOCK` reader - DPLL Lock Status"] +pub struct LOCK_R(crate::FieldReader); +impl LOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKRDY` reader - DPLL Clock Ready"] +pub struct CLKRDY_R(crate::FieldReader); +impl CLKRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - DPLL Lock Status"] + #[inline(always)] + pub fn lock(&self) -> LOCK_R { + LOCK_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - DPLL Clock Ready"] + #[inline(always)] + pub fn clkrdy(&self) -> CLKRDY_R { + CLKRDY_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +#[doc = "DPLL Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dpllstatus](index.html) module"] +pub struct DPLLSTATUS_SPEC; +impl crate::RegisterSpec for DPLLSTATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dpllstatus::R](R) reader structure"] +impl crate::Readable for DPLLSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DPLLSTATUS to value 0"] +impl crate::Resettable for DPLLSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/oscctrl/dpllsyncbusy.rs b/pac/atsamc20j/src/oscctrl/dpllsyncbusy.rs new file mode 100644 index 000000000000..f9fb880a5a59 --- /dev/null +++ b/pac/atsamc20j/src/oscctrl/dpllsyncbusy.rs @@ -0,0 +1,93 @@ +#[doc = "Register `DPLLSYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `ENABLE` reader - DPLL Enable Synchronization Status"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLRATIO` reader - DPLL Ratio Synchronization Status"] +pub struct DPLLRATIO_R(crate::FieldReader); +impl DPLLRATIO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLRATIO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLRATIO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLPRESC` reader - DPLL Prescaler Synchronization Status"] +pub struct DPLLPRESC_R(crate::FieldReader); +impl DPLLPRESC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLPRESC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLPRESC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 1 - DPLL Enable Synchronization Status"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - DPLL Ratio Synchronization Status"] + #[inline(always)] + pub fn dpllratio(&self) -> DPLLRATIO_R { + DPLLRATIO_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - DPLL Prescaler Synchronization Status"] + #[inline(always)] + pub fn dpllpresc(&self) -> DPLLPRESC_R { + DPLLPRESC_R::new(((self.bits >> 3) & 0x01) != 0) + } +} +#[doc = "DPLL Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dpllsyncbusy](index.html) module"] +pub struct DPLLSYNCBUSY_SPEC; +impl crate::RegisterSpec for DPLLSYNCBUSY_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dpllsyncbusy::R](R) reader structure"] +impl crate::Readable for DPLLSYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DPLLSYNCBUSY to value 0"] +impl crate::Resettable for DPLLSYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/oscctrl/evctrl.rs b/pac/atsamc20j/src/oscctrl/evctrl.rs new file mode 100644 index 000000000000..e22ba62f0fe2 --- /dev/null +++ b/pac/atsamc20j/src/oscctrl/evctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CFDEO` reader - Clock Failure Detector Event Output Enable"] +pub struct CFDEO_R(crate::FieldReader); +impl CFDEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFDEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFDEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFDEO` writer - Clock Failure Detector Event Output Enable"] +pub struct CFDEO_W<'a> { + w: &'a mut W, +} +impl<'a> CFDEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Clock Failure Detector Event Output Enable"] + #[inline(always)] + pub fn cfdeo(&self) -> CFDEO_R { + CFDEO_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Clock Failure Detector Event Output Enable"] + #[inline(always)] + pub fn cfdeo(&mut self) -> CFDEO_W { + CFDEO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/oscctrl/intenclr.rs b/pac/atsamc20j/src/oscctrl/intenclr.rs new file mode 100644 index 000000000000..0ea0034a0c02 --- /dev/null +++ b/pac/atsamc20j/src/oscctrl/intenclr.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XOSCRDY` reader - XOSC Ready Interrupt Enable"] +pub struct XOSCRDY_R(crate::FieldReader); +impl XOSCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSCRDY` writer - XOSC Ready Interrupt Enable"] +pub struct XOSCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> XOSCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `XOSCFAIL` reader - XOSC Clock Failure Detector Interrupt Enable"] +pub struct XOSCFAIL_R(crate::FieldReader); +impl XOSCFAIL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSCFAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCFAIL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSCFAIL` writer - XOSC Clock Failure Detector Interrupt Enable"] +pub struct XOSCFAIL_W<'a> { + w: &'a mut W, +} +impl<'a> XOSCFAIL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `OSC48MRDY` reader - OSC48M Ready Interrupt Enable"] +pub struct OSC48MRDY_R(crate::FieldReader); +impl OSC48MRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC48MRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC48MRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC48MRDY` writer - OSC48M Ready Interrupt Enable"] +pub struct OSC48MRDY_W<'a> { + w: &'a mut W, +} +impl<'a> OSC48MRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `DPLLLCKR` reader - DPLL Lock Rise Interrupt Enable"] +pub struct DPLLLCKR_R(crate::FieldReader); +impl DPLLLCKR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKR` writer - DPLL Lock Rise Interrupt Enable"] +pub struct DPLLLCKR_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLCKR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `DPLLLCKF` reader - DPLL Lock Fall Interrupt Enable"] +pub struct DPLLLCKF_R(crate::FieldReader); +impl DPLLLCKF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKF` writer - DPLL Lock Fall Interrupt Enable"] +pub struct DPLLLCKF_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLCKF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `DPLLLTO` reader - DPLL Time Out Interrupt Enable"] +pub struct DPLLLTO_R(crate::FieldReader); +impl DPLLLTO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLTO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLTO` writer - DPLL Time Out Interrupt Enable"] +pub struct DPLLLTO_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLTO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `DPLLLDRTO` reader - DPLL Ratio Ready Interrupt Enable"] +pub struct DPLLLDRTO_R(crate::FieldReader); +impl DPLLLDRTO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLDRTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLDRTO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLDRTO` writer - DPLL Ratio Ready Interrupt Enable"] +pub struct DPLLLDRTO_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLDRTO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +impl R { + #[doc = "Bit 0 - XOSC Ready Interrupt Enable"] + #[inline(always)] + pub fn xoscrdy(&self) -> XOSCRDY_R { + XOSCRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - XOSC Clock Failure Detector Interrupt Enable"] + #[inline(always)] + pub fn xoscfail(&self) -> XOSCFAIL_R { + XOSCFAIL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - OSC48M Ready Interrupt Enable"] + #[inline(always)] + pub fn osc48mrdy(&self) -> OSC48MRDY_R { + OSC48MRDY_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 8 - DPLL Lock Rise Interrupt Enable"] + #[inline(always)] + pub fn dplllckr(&self) -> DPLLLCKR_R { + DPLLLCKR_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - DPLL Lock Fall Interrupt Enable"] + #[inline(always)] + pub fn dplllckf(&self) -> DPLLLCKF_R { + DPLLLCKF_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - DPLL Time Out Interrupt Enable"] + #[inline(always)] + pub fn dplllto(&self) -> DPLLLTO_R { + DPLLLTO_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - DPLL Ratio Ready Interrupt Enable"] + #[inline(always)] + pub fn dpllldrto(&self) -> DPLLLDRTO_R { + DPLLLDRTO_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - XOSC Ready Interrupt Enable"] + #[inline(always)] + pub fn xoscrdy(&mut self) -> XOSCRDY_W { + XOSCRDY_W { w: self } + } + #[doc = "Bit 1 - XOSC Clock Failure Detector Interrupt Enable"] + #[inline(always)] + pub fn xoscfail(&mut self) -> XOSCFAIL_W { + XOSCFAIL_W { w: self } + } + #[doc = "Bit 4 - OSC48M Ready Interrupt Enable"] + #[inline(always)] + pub fn osc48mrdy(&mut self) -> OSC48MRDY_W { + OSC48MRDY_W { w: self } + } + #[doc = "Bit 8 - DPLL Lock Rise Interrupt Enable"] + #[inline(always)] + pub fn dplllckr(&mut self) -> DPLLLCKR_W { + DPLLLCKR_W { w: self } + } + #[doc = "Bit 9 - DPLL Lock Fall Interrupt Enable"] + #[inline(always)] + pub fn dplllckf(&mut self) -> DPLLLCKF_W { + DPLLLCKF_W { w: self } + } + #[doc = "Bit 10 - DPLL Time Out Interrupt Enable"] + #[inline(always)] + pub fn dplllto(&mut self) -> DPLLLTO_W { + DPLLLTO_W { w: self } + } + #[doc = "Bit 11 - DPLL Ratio Ready Interrupt Enable"] + #[inline(always)] + pub fn dpllldrto(&mut self) -> DPLLLDRTO_W { + DPLLLDRTO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/oscctrl/intenset.rs b/pac/atsamc20j/src/oscctrl/intenset.rs new file mode 100644 index 000000000000..2890541e4414 --- /dev/null +++ b/pac/atsamc20j/src/oscctrl/intenset.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XOSCRDY` reader - XOSC Ready Interrupt Enable"] +pub struct XOSCRDY_R(crate::FieldReader); +impl XOSCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSCRDY` writer - XOSC Ready Interrupt Enable"] +pub struct XOSCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> XOSCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `XOSCFAIL` reader - XOSC Clock Failure Detector Interrupt Enable"] +pub struct XOSCFAIL_R(crate::FieldReader); +impl XOSCFAIL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSCFAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCFAIL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSCFAIL` writer - XOSC Clock Failure Detector Interrupt Enable"] +pub struct XOSCFAIL_W<'a> { + w: &'a mut W, +} +impl<'a> XOSCFAIL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `OSC48MRDY` reader - OSC48M Ready Interrupt Enable"] +pub struct OSC48MRDY_R(crate::FieldReader); +impl OSC48MRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC48MRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC48MRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC48MRDY` writer - OSC48M Ready Interrupt Enable"] +pub struct OSC48MRDY_W<'a> { + w: &'a mut W, +} +impl<'a> OSC48MRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `DPLLLCKR` reader - DPLL Lock Rise Interrupt Enable"] +pub struct DPLLLCKR_R(crate::FieldReader); +impl DPLLLCKR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKR` writer - DPLL Lock Rise Interrupt Enable"] +pub struct DPLLLCKR_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLCKR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `DPLLLCKF` reader - DPLL Lock Fall Interrupt Enable"] +pub struct DPLLLCKF_R(crate::FieldReader); +impl DPLLLCKF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKF` writer - DPLL Lock Fall Interrupt Enable"] +pub struct DPLLLCKF_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLCKF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `DPLLLTO` reader - DPLL Time Out Interrupt Enable"] +pub struct DPLLLTO_R(crate::FieldReader); +impl DPLLLTO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLTO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLTO` writer - DPLL Time Out Interrupt Enable"] +pub struct DPLLLTO_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLTO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `DPLLLDRTO` reader - DPLL Ratio Ready Interrupt Enable"] +pub struct DPLLLDRTO_R(crate::FieldReader); +impl DPLLLDRTO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLDRTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLDRTO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLDRTO` writer - DPLL Ratio Ready Interrupt Enable"] +pub struct DPLLLDRTO_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLDRTO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +impl R { + #[doc = "Bit 0 - XOSC Ready Interrupt Enable"] + #[inline(always)] + pub fn xoscrdy(&self) -> XOSCRDY_R { + XOSCRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - XOSC Clock Failure Detector Interrupt Enable"] + #[inline(always)] + pub fn xoscfail(&self) -> XOSCFAIL_R { + XOSCFAIL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - OSC48M Ready Interrupt Enable"] + #[inline(always)] + pub fn osc48mrdy(&self) -> OSC48MRDY_R { + OSC48MRDY_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 8 - DPLL Lock Rise Interrupt Enable"] + #[inline(always)] + pub fn dplllckr(&self) -> DPLLLCKR_R { + DPLLLCKR_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - DPLL Lock Fall Interrupt Enable"] + #[inline(always)] + pub fn dplllckf(&self) -> DPLLLCKF_R { + DPLLLCKF_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - DPLL Time Out Interrupt Enable"] + #[inline(always)] + pub fn dplllto(&self) -> DPLLLTO_R { + DPLLLTO_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - DPLL Ratio Ready Interrupt Enable"] + #[inline(always)] + pub fn dpllldrto(&self) -> DPLLLDRTO_R { + DPLLLDRTO_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - XOSC Ready Interrupt Enable"] + #[inline(always)] + pub fn xoscrdy(&mut self) -> XOSCRDY_W { + XOSCRDY_W { w: self } + } + #[doc = "Bit 1 - XOSC Clock Failure Detector Interrupt Enable"] + #[inline(always)] + pub fn xoscfail(&mut self) -> XOSCFAIL_W { + XOSCFAIL_W { w: self } + } + #[doc = "Bit 4 - OSC48M Ready Interrupt Enable"] + #[inline(always)] + pub fn osc48mrdy(&mut self) -> OSC48MRDY_W { + OSC48MRDY_W { w: self } + } + #[doc = "Bit 8 - DPLL Lock Rise Interrupt Enable"] + #[inline(always)] + pub fn dplllckr(&mut self) -> DPLLLCKR_W { + DPLLLCKR_W { w: self } + } + #[doc = "Bit 9 - DPLL Lock Fall Interrupt Enable"] + #[inline(always)] + pub fn dplllckf(&mut self) -> DPLLLCKF_W { + DPLLLCKF_W { w: self } + } + #[doc = "Bit 10 - DPLL Time Out Interrupt Enable"] + #[inline(always)] + pub fn dplllto(&mut self) -> DPLLLTO_W { + DPLLLTO_W { w: self } + } + #[doc = "Bit 11 - DPLL Ratio Ready Interrupt Enable"] + #[inline(always)] + pub fn dpllldrto(&mut self) -> DPLLLDRTO_W { + DPLLLDRTO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/oscctrl/intflag.rs b/pac/atsamc20j/src/oscctrl/intflag.rs new file mode 100644 index 000000000000..71e452a1b571 --- /dev/null +++ b/pac/atsamc20j/src/oscctrl/intflag.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XOSCRDY` reader - XOSC Ready"] +pub struct XOSCRDY_R(crate::FieldReader); +impl XOSCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSCRDY` writer - XOSC Ready"] +pub struct XOSCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> XOSCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `XOSCFAIL` reader - XOSC Clock Failure Detector"] +pub struct XOSCFAIL_R(crate::FieldReader); +impl XOSCFAIL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSCFAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCFAIL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSCFAIL` writer - XOSC Clock Failure Detector"] +pub struct XOSCFAIL_W<'a> { + w: &'a mut W, +} +impl<'a> XOSCFAIL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `OSC48MRDY` reader - OSC48M Ready"] +pub struct OSC48MRDY_R(crate::FieldReader); +impl OSC48MRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC48MRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC48MRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC48MRDY` writer - OSC48M Ready"] +pub struct OSC48MRDY_W<'a> { + w: &'a mut W, +} +impl<'a> OSC48MRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `DPLLLCKR` reader - DPLL Lock Rise"] +pub struct DPLLLCKR_R(crate::FieldReader); +impl DPLLLCKR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKR` writer - DPLL Lock Rise"] +pub struct DPLLLCKR_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLCKR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `DPLLLCKF` reader - DPLL Lock Fall"] +pub struct DPLLLCKF_R(crate::FieldReader); +impl DPLLLCKF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKF` writer - DPLL Lock Fall"] +pub struct DPLLLCKF_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLCKF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `DPLLLTO` reader - DPLL Timeout"] +pub struct DPLLLTO_R(crate::FieldReader); +impl DPLLLTO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLTO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLTO` writer - DPLL Timeout"] +pub struct DPLLLTO_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLTO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `DPLLLDRTO` reader - DPLL Ratio Ready"] +pub struct DPLLLDRTO_R(crate::FieldReader); +impl DPLLLDRTO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLDRTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLDRTO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLDRTO` writer - DPLL Ratio Ready"] +pub struct DPLLLDRTO_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLDRTO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +impl R { + #[doc = "Bit 0 - XOSC Ready"] + #[inline(always)] + pub fn xoscrdy(&self) -> XOSCRDY_R { + XOSCRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - XOSC Clock Failure Detector"] + #[inline(always)] + pub fn xoscfail(&self) -> XOSCFAIL_R { + XOSCFAIL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - OSC48M Ready"] + #[inline(always)] + pub fn osc48mrdy(&self) -> OSC48MRDY_R { + OSC48MRDY_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 8 - DPLL Lock Rise"] + #[inline(always)] + pub fn dplllckr(&self) -> DPLLLCKR_R { + DPLLLCKR_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - DPLL Lock Fall"] + #[inline(always)] + pub fn dplllckf(&self) -> DPLLLCKF_R { + DPLLLCKF_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - DPLL Timeout"] + #[inline(always)] + pub fn dplllto(&self) -> DPLLLTO_R { + DPLLLTO_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - DPLL Ratio Ready"] + #[inline(always)] + pub fn dpllldrto(&self) -> DPLLLDRTO_R { + DPLLLDRTO_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - XOSC Ready"] + #[inline(always)] + pub fn xoscrdy(&mut self) -> XOSCRDY_W { + XOSCRDY_W { w: self } + } + #[doc = "Bit 1 - XOSC Clock Failure Detector"] + #[inline(always)] + pub fn xoscfail(&mut self) -> XOSCFAIL_W { + XOSCFAIL_W { w: self } + } + #[doc = "Bit 4 - OSC48M Ready"] + #[inline(always)] + pub fn osc48mrdy(&mut self) -> OSC48MRDY_W { + OSC48MRDY_W { w: self } + } + #[doc = "Bit 8 - DPLL Lock Rise"] + #[inline(always)] + pub fn dplllckr(&mut self) -> DPLLLCKR_W { + DPLLLCKR_W { w: self } + } + #[doc = "Bit 9 - DPLL Lock Fall"] + #[inline(always)] + pub fn dplllckf(&mut self) -> DPLLLCKF_W { + DPLLLCKF_W { w: self } + } + #[doc = "Bit 10 - DPLL Timeout"] + #[inline(always)] + pub fn dplllto(&mut self) -> DPLLLTO_W { + DPLLLTO_W { w: self } + } + #[doc = "Bit 11 - DPLL Ratio Ready"] + #[inline(always)] + pub fn dpllldrto(&mut self) -> DPLLLDRTO_W { + DPLLLDRTO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/oscctrl/osc48mctrl.rs b/pac/atsamc20j/src/oscctrl/osc48mctrl.rs new file mode 100644 index 000000000000..8314e21e5775 --- /dev/null +++ b/pac/atsamc20j/src/oscctrl/osc48mctrl.rs @@ -0,0 +1,207 @@ +#[doc = "Register `OSC48MCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OSC48MCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Oscillator Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Oscillator Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - On Demand Control"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - On Demand Control"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "48MHz Internal Oscillator (OSC48M) Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [osc48mctrl](index.html) module"] +pub struct OSC48MCTRL_SPEC; +impl crate::RegisterSpec for OSC48MCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [osc48mctrl::R](R) reader structure"] +impl crate::Readable for OSC48MCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [osc48mctrl::W](W) writer structure"] +impl crate::Writable for OSC48MCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OSC48MCTRL to value 0x82"] +impl crate::Resettable for OSC48MCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x82 + } +} diff --git a/pac/atsamc20j/src/oscctrl/osc48mdiv.rs b/pac/atsamc20j/src/oscctrl/osc48mdiv.rs new file mode 100644 index 000000000000..4ed854b09284 --- /dev/null +++ b/pac/atsamc20j/src/oscctrl/osc48mdiv.rs @@ -0,0 +1,334 @@ +#[doc = "Register `OSC48MDIV` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OSC48MDIV` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "OSC48M Division Factor\n\nValue on reset: 11"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DIV_A { + #[doc = "0: 48 MHz"] + DIV1 = 0, + #[doc = "1: 24 MHz"] + DIV2 = 1, + #[doc = "2: 16 MHz"] + DIV3 = 2, + #[doc = "3: 12 MHz"] + DIV4 = 3, + #[doc = "4: 9.6 MHz"] + DIV5 = 4, + #[doc = "5: 8 MHz"] + DIV6 = 5, + #[doc = "6: 6.86 MHz"] + DIV7 = 6, + #[doc = "7: 6 MHz"] + DIV8 = 7, + #[doc = "8: 5.33 MHz"] + DIV9 = 8, + #[doc = "9: 4.8 MHz"] + DIV10 = 9, + #[doc = "10: 4.36 MHz"] + DIV11 = 10, + #[doc = "11: 4 MHz"] + DIV12 = 11, + #[doc = "12: 3.69 MHz"] + DIV13 = 12, + #[doc = "13: 3.43 MHz"] + DIV14 = 13, + #[doc = "14: 3.2 MHz"] + DIV15 = 14, + #[doc = "15: 3 MHz"] + DIV16 = 15, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DIV_A) -> Self { + variant as _ + } +} +#[doc = "Field `DIV` reader - OSC48M Division Factor"] +pub struct DIV_R(crate::FieldReader); +impl DIV_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DIV_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DIV_A { + match self.bits { + 0 => DIV_A::DIV1, + 1 => DIV_A::DIV2, + 2 => DIV_A::DIV3, + 3 => DIV_A::DIV4, + 4 => DIV_A::DIV5, + 5 => DIV_A::DIV6, + 6 => DIV_A::DIV7, + 7 => DIV_A::DIV8, + 8 => DIV_A::DIV9, + 9 => DIV_A::DIV10, + 10 => DIV_A::DIV11, + 11 => DIV_A::DIV12, + 12 => DIV_A::DIV13, + 13 => DIV_A::DIV14, + 14 => DIV_A::DIV15, + 15 => DIV_A::DIV16, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == DIV_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == DIV_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV3`"] + #[inline(always)] + pub fn is_div3(&self) -> bool { + **self == DIV_A::DIV3 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == DIV_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV5`"] + #[inline(always)] + pub fn is_div5(&self) -> bool { + **self == DIV_A::DIV5 + } + #[doc = "Checks if the value of the field is `DIV6`"] + #[inline(always)] + pub fn is_div6(&self) -> bool { + **self == DIV_A::DIV6 + } + #[doc = "Checks if the value of the field is `DIV7`"] + #[inline(always)] + pub fn is_div7(&self) -> bool { + **self == DIV_A::DIV7 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == DIV_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV9`"] + #[inline(always)] + pub fn is_div9(&self) -> bool { + **self == DIV_A::DIV9 + } + #[doc = "Checks if the value of the field is `DIV10`"] + #[inline(always)] + pub fn is_div10(&self) -> bool { + **self == DIV_A::DIV10 + } + #[doc = "Checks if the value of the field is `DIV11`"] + #[inline(always)] + pub fn is_div11(&self) -> bool { + **self == DIV_A::DIV11 + } + #[doc = "Checks if the value of the field is `DIV12`"] + #[inline(always)] + pub fn is_div12(&self) -> bool { + **self == DIV_A::DIV12 + } + #[doc = "Checks if the value of the field is `DIV13`"] + #[inline(always)] + pub fn is_div13(&self) -> bool { + **self == DIV_A::DIV13 + } + #[doc = "Checks if the value of the field is `DIV14`"] + #[inline(always)] + pub fn is_div14(&self) -> bool { + **self == DIV_A::DIV14 + } + #[doc = "Checks if the value of the field is `DIV15`"] + #[inline(always)] + pub fn is_div15(&self) -> bool { + **self == DIV_A::DIV15 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == DIV_A::DIV16 + } +} +impl core::ops::Deref for DIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIV` writer - OSC48M Division Factor"] +pub struct DIV_W<'a> { + w: &'a mut W, +} +impl<'a> DIV_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DIV_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "48 MHz"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(DIV_A::DIV1) + } + #[doc = "24 MHz"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(DIV_A::DIV2) + } + #[doc = "16 MHz"] + #[inline(always)] + pub fn div3(self) -> &'a mut W { + self.variant(DIV_A::DIV3) + } + #[doc = "12 MHz"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(DIV_A::DIV4) + } + #[doc = "9.6 MHz"] + #[inline(always)] + pub fn div5(self) -> &'a mut W { + self.variant(DIV_A::DIV5) + } + #[doc = "8 MHz"] + #[inline(always)] + pub fn div6(self) -> &'a mut W { + self.variant(DIV_A::DIV6) + } + #[doc = "6.86 MHz"] + #[inline(always)] + pub fn div7(self) -> &'a mut W { + self.variant(DIV_A::DIV7) + } + #[doc = "6 MHz"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(DIV_A::DIV8) + } + #[doc = "5.33 MHz"] + #[inline(always)] + pub fn div9(self) -> &'a mut W { + self.variant(DIV_A::DIV9) + } + #[doc = "4.8 MHz"] + #[inline(always)] + pub fn div10(self) -> &'a mut W { + self.variant(DIV_A::DIV10) + } + #[doc = "4.36 MHz"] + #[inline(always)] + pub fn div11(self) -> &'a mut W { + self.variant(DIV_A::DIV11) + } + #[doc = "4 MHz"] + #[inline(always)] + pub fn div12(self) -> &'a mut W { + self.variant(DIV_A::DIV12) + } + #[doc = "3.69 MHz"] + #[inline(always)] + pub fn div13(self) -> &'a mut W { + self.variant(DIV_A::DIV13) + } + #[doc = "3.43 MHz"] + #[inline(always)] + pub fn div14(self) -> &'a mut W { + self.variant(DIV_A::DIV14) + } + #[doc = "3.2 MHz"] + #[inline(always)] + pub fn div15(self) -> &'a mut W { + self.variant(DIV_A::DIV15) + } + #[doc = "3 MHz"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(DIV_A::DIV16) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - OSC48M Division Factor"] + #[inline(always)] + pub fn div(&self) -> DIV_R { + DIV_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - OSC48M Division Factor"] + #[inline(always)] + pub fn div(&mut self) -> DIV_W { + DIV_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OSC48M Divider\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [osc48mdiv](index.html) module"] +pub struct OSC48MDIV_SPEC; +impl crate::RegisterSpec for OSC48MDIV_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [osc48mdiv::R](R) reader structure"] +impl crate::Readable for OSC48MDIV_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [osc48mdiv::W](W) writer structure"] +impl crate::Writable for OSC48MDIV_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OSC48MDIV to value 0x0b"] +impl crate::Resettable for OSC48MDIV_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0b + } +} diff --git a/pac/atsamc20j/src/oscctrl/osc48mstup.rs b/pac/atsamc20j/src/oscctrl/osc48mstup.rs new file mode 100644 index 000000000000..34da6bb7ef11 --- /dev/null +++ b/pac/atsamc20j/src/oscctrl/osc48mstup.rs @@ -0,0 +1,230 @@ +#[doc = "Register `OSC48MSTUP` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OSC48MSTUP` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Startup Time\n\nValue on reset: 7"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum STARTUP_A { + #[doc = "0: 166 ns"] + CYCLE8 = 0, + #[doc = "1: 333 ns"] + CYCLE16 = 1, + #[doc = "2: 667 ns"] + CYCLE32 = 2, + #[doc = "3: 1.333 us"] + CYCLE64 = 3, + #[doc = "4: 2.667 us"] + CYCLE128 = 4, + #[doc = "5: 5.333 us"] + CYCLE256 = 5, + #[doc = "6: 10.667 us"] + CYCLE512 = 6, + #[doc = "7: 21.333 us"] + CYCLE1024 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: STARTUP_A) -> Self { + variant as _ + } +} +#[doc = "Field `STARTUP` reader - Startup Time"] +pub struct STARTUP_R(crate::FieldReader); +impl STARTUP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + STARTUP_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STARTUP_A { + match self.bits { + 0 => STARTUP_A::CYCLE8, + 1 => STARTUP_A::CYCLE16, + 2 => STARTUP_A::CYCLE32, + 3 => STARTUP_A::CYCLE64, + 4 => STARTUP_A::CYCLE128, + 5 => STARTUP_A::CYCLE256, + 6 => STARTUP_A::CYCLE512, + 7 => STARTUP_A::CYCLE1024, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `CYCLE8`"] + #[inline(always)] + pub fn is_cycle8(&self) -> bool { + **self == STARTUP_A::CYCLE8 + } + #[doc = "Checks if the value of the field is `CYCLE16`"] + #[inline(always)] + pub fn is_cycle16(&self) -> bool { + **self == STARTUP_A::CYCLE16 + } + #[doc = "Checks if the value of the field is `CYCLE32`"] + #[inline(always)] + pub fn is_cycle32(&self) -> bool { + **self == STARTUP_A::CYCLE32 + } + #[doc = "Checks if the value of the field is `CYCLE64`"] + #[inline(always)] + pub fn is_cycle64(&self) -> bool { + **self == STARTUP_A::CYCLE64 + } + #[doc = "Checks if the value of the field is `CYCLE128`"] + #[inline(always)] + pub fn is_cycle128(&self) -> bool { + **self == STARTUP_A::CYCLE128 + } + #[doc = "Checks if the value of the field is `CYCLE256`"] + #[inline(always)] + pub fn is_cycle256(&self) -> bool { + **self == STARTUP_A::CYCLE256 + } + #[doc = "Checks if the value of the field is `CYCLE512`"] + #[inline(always)] + pub fn is_cycle512(&self) -> bool { + **self == STARTUP_A::CYCLE512 + } + #[doc = "Checks if the value of the field is `CYCLE1024`"] + #[inline(always)] + pub fn is_cycle1024(&self) -> bool { + **self == STARTUP_A::CYCLE1024 + } +} +impl core::ops::Deref for STARTUP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STARTUP` writer - Startup Time"] +pub struct STARTUP_W<'a> { + w: &'a mut W, +} +impl<'a> STARTUP_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: STARTUP_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "166 ns"] + #[inline(always)] + pub fn cycle8(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE8) + } + #[doc = "333 ns"] + #[inline(always)] + pub fn cycle16(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE16) + } + #[doc = "667 ns"] + #[inline(always)] + pub fn cycle32(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE32) + } + #[doc = "1.333 us"] + #[inline(always)] + pub fn cycle64(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE64) + } + #[doc = "2.667 us"] + #[inline(always)] + pub fn cycle128(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE128) + } + #[doc = "5.333 us"] + #[inline(always)] + pub fn cycle256(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE256) + } + #[doc = "10.667 us"] + #[inline(always)] + pub fn cycle512(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE512) + } + #[doc = "21.333 us"] + #[inline(always)] + pub fn cycle1024(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Startup Time"] + #[inline(always)] + pub fn startup(&self) -> STARTUP_R { + STARTUP_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Startup Time"] + #[inline(always)] + pub fn startup(&mut self) -> STARTUP_W { + STARTUP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OSC48M Startup Time\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [osc48mstup](index.html) module"] +pub struct OSC48MSTUP_SPEC; +impl crate::RegisterSpec for OSC48MSTUP_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [osc48mstup::R](R) reader structure"] +impl crate::Readable for OSC48MSTUP_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [osc48mstup::W](W) writer structure"] +impl crate::Writable for OSC48MSTUP_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OSC48MSTUP to value 0x07"] +impl crate::Resettable for OSC48MSTUP_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x07 + } +} diff --git a/pac/atsamc20j/src/oscctrl/osc48msyncbusy.rs b/pac/atsamc20j/src/oscctrl/osc48msyncbusy.rs new file mode 100644 index 000000000000..8d4410ae630a --- /dev/null +++ b/pac/atsamc20j/src/oscctrl/osc48msyncbusy.rs @@ -0,0 +1,53 @@ +#[doc = "Register `OSC48MSYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `OSC48MDIV` reader - OSC48MDIV Synchronization Status"] +pub struct OSC48MDIV_R(crate::FieldReader); +impl OSC48MDIV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC48MDIV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC48MDIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 2 - OSC48MDIV Synchronization Status"] + #[inline(always)] + pub fn osc48mdiv(&self) -> OSC48MDIV_R { + OSC48MDIV_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +#[doc = "OSC48M Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [osc48msyncbusy](index.html) module"] +pub struct OSC48MSYNCBUSY_SPEC; +impl crate::RegisterSpec for OSC48MSYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [osc48msyncbusy::R](R) reader structure"] +impl crate::Readable for OSC48MSYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets OSC48MSYNCBUSY to value 0"] +impl crate::Resettable for OSC48MSYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/oscctrl/status.rs b/pac/atsamc20j/src/oscctrl/status.rs new file mode 100644 index 000000000000..3025966192a3 --- /dev/null +++ b/pac/atsamc20j/src/oscctrl/status.rs @@ -0,0 +1,193 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `XOSCRDY` reader - XOSC Ready"] +pub struct XOSCRDY_R(crate::FieldReader); +impl XOSCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSCFAIL` reader - XOSC Clock Failure Detector"] +pub struct XOSCFAIL_R(crate::FieldReader); +impl XOSCFAIL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSCFAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCFAIL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSCCKSW` reader - XOSC Clock Switch"] +pub struct XOSCCKSW_R(crate::FieldReader); +impl XOSCCKSW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSCCKSW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCCKSW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC48MRDY` reader - OSC48M Ready"] +pub struct OSC48MRDY_R(crate::FieldReader); +impl OSC48MRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC48MRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC48MRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKR` reader - DPLL Lock Rise"] +pub struct DPLLLCKR_R(crate::FieldReader); +impl DPLLLCKR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKF` reader - DPLL Lock Fall"] +pub struct DPLLLCKF_R(crate::FieldReader); +impl DPLLLCKF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLTO` reader - DPLL Timeout"] +pub struct DPLLTO_R(crate::FieldReader); +impl DPLLTO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLTO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLDRTO` reader - DPLL Ratio Ready"] +pub struct DPLLLDRTO_R(crate::FieldReader); +impl DPLLLDRTO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLDRTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLDRTO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - XOSC Ready"] + #[inline(always)] + pub fn xoscrdy(&self) -> XOSCRDY_R { + XOSCRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - XOSC Clock Failure Detector"] + #[inline(always)] + pub fn xoscfail(&self) -> XOSCFAIL_R { + XOSCFAIL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - XOSC Clock Switch"] + #[inline(always)] + pub fn xosccksw(&self) -> XOSCCKSW_R { + XOSCCKSW_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 4 - OSC48M Ready"] + #[inline(always)] + pub fn osc48mrdy(&self) -> OSC48MRDY_R { + OSC48MRDY_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 8 - DPLL Lock Rise"] + #[inline(always)] + pub fn dplllckr(&self) -> DPLLLCKR_R { + DPLLLCKR_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - DPLL Lock Fall"] + #[inline(always)] + pub fn dplllckf(&self) -> DPLLLCKF_R { + DPLLLCKF_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - DPLL Timeout"] + #[inline(always)] + pub fn dpllto(&self) -> DPLLTO_R { + DPLLTO_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - DPLL Ratio Ready"] + #[inline(always)] + pub fn dpllldrto(&self) -> DPLLLDRTO_R { + DPLLLDRTO_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +#[doc = "Power and Clocks Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/oscctrl/xoscctrl.rs b/pac/atsamc20j/src/oscctrl/xoscctrl.rs new file mode 100644 index 000000000000..3a5319565c10 --- /dev/null +++ b/pac/atsamc20j/src/oscctrl/xoscctrl.rs @@ -0,0 +1,788 @@ +#[doc = "Register `XOSCCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `XOSCCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Oscillator Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Oscillator Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `XTALEN` reader - Crystal Oscillator Enable"] +pub struct XTALEN_R(crate::FieldReader); +impl XTALEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XTALEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XTALEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XTALEN` writer - Crystal Oscillator Enable"] +pub struct XTALEN_W<'a> { + w: &'a mut W, +} +impl<'a> XTALEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CFDEN` reader - Xosc Clock Failure Detector Enable"] +pub struct CFDEN_R(crate::FieldReader); +impl CFDEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFDEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFDEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFDEN` writer - Xosc Clock Failure Detector Enable"] +pub struct CFDEN_W<'a> { + w: &'a mut W, +} +impl<'a> CFDEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `SWBEN` reader - Xosc Clock Switch Enable"] +pub struct SWBEN_R(crate::FieldReader); +impl SWBEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWBEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWBEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWBEN` writer - Xosc Clock Switch Enable"] +pub struct SWBEN_W<'a> { + w: &'a mut W, +} +impl<'a> SWBEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - On Demand Control"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - On Demand Control"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Oscillator Gain\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum GAIN_A { + #[doc = "0: 2 MHz"] + GAIN2 = 0, + #[doc = "1: 4 MHz"] + GAIN4 = 1, + #[doc = "2: 8 MHz"] + GAIN8 = 2, + #[doc = "3: 16 MHz"] + GAIN16 = 3, + #[doc = "4: 30 MHz"] + GAIN30 = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: GAIN_A) -> Self { + variant as _ + } +} +#[doc = "Field `GAIN` reader - Oscillator Gain"] +pub struct GAIN_R(crate::FieldReader); +impl GAIN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + GAIN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(GAIN_A::GAIN2), + 1 => Some(GAIN_A::GAIN4), + 2 => Some(GAIN_A::GAIN8), + 3 => Some(GAIN_A::GAIN16), + 4 => Some(GAIN_A::GAIN30), + _ => None, + } + } + #[doc = "Checks if the value of the field is `GAIN2`"] + #[inline(always)] + pub fn is_gain2(&self) -> bool { + **self == GAIN_A::GAIN2 + } + #[doc = "Checks if the value of the field is `GAIN4`"] + #[inline(always)] + pub fn is_gain4(&self) -> bool { + **self == GAIN_A::GAIN4 + } + #[doc = "Checks if the value of the field is `GAIN8`"] + #[inline(always)] + pub fn is_gain8(&self) -> bool { + **self == GAIN_A::GAIN8 + } + #[doc = "Checks if the value of the field is `GAIN16`"] + #[inline(always)] + pub fn is_gain16(&self) -> bool { + **self == GAIN_A::GAIN16 + } + #[doc = "Checks if the value of the field is `GAIN30`"] + #[inline(always)] + pub fn is_gain30(&self) -> bool { + **self == GAIN_A::GAIN30 + } +} +impl core::ops::Deref for GAIN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GAIN` writer - Oscillator Gain"] +pub struct GAIN_W<'a> { + w: &'a mut W, +} +impl<'a> GAIN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: GAIN_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "2 MHz"] + #[inline(always)] + pub fn gain2(self) -> &'a mut W { + self.variant(GAIN_A::GAIN2) + } + #[doc = "4 MHz"] + #[inline(always)] + pub fn gain4(self) -> &'a mut W { + self.variant(GAIN_A::GAIN4) + } + #[doc = "8 MHz"] + #[inline(always)] + pub fn gain8(self) -> &'a mut W { + self.variant(GAIN_A::GAIN8) + } + #[doc = "16 MHz"] + #[inline(always)] + pub fn gain16(self) -> &'a mut W { + self.variant(GAIN_A::GAIN16) + } + #[doc = "30 MHz"] + #[inline(always)] + pub fn gain30(self) -> &'a mut W { + self.variant(GAIN_A::GAIN30) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u16 & 0x07) << 8); + self.w + } +} +#[doc = "Field `AMPGC` reader - Automatic Amplitude Gain Control"] +pub struct AMPGC_R(crate::FieldReader); +impl AMPGC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AMPGC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AMPGC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AMPGC` writer - Automatic Amplitude Gain Control"] +pub struct AMPGC_W<'a> { + w: &'a mut W, +} +impl<'a> AMPGC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u16 & 0x01) << 11); + self.w + } +} +#[doc = "Start-Up Time\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum STARTUP_A { + #[doc = "0: 31 us"] + CYCLE1 = 0, + #[doc = "1: 61 us"] + CYCLE2 = 1, + #[doc = "2: 122 us"] + CYCLE4 = 2, + #[doc = "3: 244 us"] + CYCLE8 = 3, + #[doc = "4: 488 us"] + CYCLE16 = 4, + #[doc = "5: 977 us"] + CYCLE32 = 5, + #[doc = "6: 1953 us"] + CYCLE64 = 6, + #[doc = "7: 3906 us"] + CYCLE128 = 7, + #[doc = "8: 7813 us"] + CYCLE256 = 8, + #[doc = "9: 15625 us"] + CYCLE512 = 9, + #[doc = "10: 31250 us"] + CYCLE1024 = 10, + #[doc = "11: 62500 us"] + CYCLE2048 = 11, + #[doc = "12: 125000 us"] + CYCLE4096 = 12, + #[doc = "13: 250000 us"] + CYCLE8192 = 13, + #[doc = "14: 500000 us"] + CYCLE16384 = 14, + #[doc = "15: 1000000 us"] + CYCLE32768 = 15, +} +impl From for u8 { + #[inline(always)] + fn from(variant: STARTUP_A) -> Self { + variant as _ + } +} +#[doc = "Field `STARTUP` reader - Start-Up Time"] +pub struct STARTUP_R(crate::FieldReader); +impl STARTUP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + STARTUP_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STARTUP_A { + match self.bits { + 0 => STARTUP_A::CYCLE1, + 1 => STARTUP_A::CYCLE2, + 2 => STARTUP_A::CYCLE4, + 3 => STARTUP_A::CYCLE8, + 4 => STARTUP_A::CYCLE16, + 5 => STARTUP_A::CYCLE32, + 6 => STARTUP_A::CYCLE64, + 7 => STARTUP_A::CYCLE128, + 8 => STARTUP_A::CYCLE256, + 9 => STARTUP_A::CYCLE512, + 10 => STARTUP_A::CYCLE1024, + 11 => STARTUP_A::CYCLE2048, + 12 => STARTUP_A::CYCLE4096, + 13 => STARTUP_A::CYCLE8192, + 14 => STARTUP_A::CYCLE16384, + 15 => STARTUP_A::CYCLE32768, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `CYCLE1`"] + #[inline(always)] + pub fn is_cycle1(&self) -> bool { + **self == STARTUP_A::CYCLE1 + } + #[doc = "Checks if the value of the field is `CYCLE2`"] + #[inline(always)] + pub fn is_cycle2(&self) -> bool { + **self == STARTUP_A::CYCLE2 + } + #[doc = "Checks if the value of the field is `CYCLE4`"] + #[inline(always)] + pub fn is_cycle4(&self) -> bool { + **self == STARTUP_A::CYCLE4 + } + #[doc = "Checks if the value of the field is `CYCLE8`"] + #[inline(always)] + pub fn is_cycle8(&self) -> bool { + **self == STARTUP_A::CYCLE8 + } + #[doc = "Checks if the value of the field is `CYCLE16`"] + #[inline(always)] + pub fn is_cycle16(&self) -> bool { + **self == STARTUP_A::CYCLE16 + } + #[doc = "Checks if the value of the field is `CYCLE32`"] + #[inline(always)] + pub fn is_cycle32(&self) -> bool { + **self == STARTUP_A::CYCLE32 + } + #[doc = "Checks if the value of the field is `CYCLE64`"] + #[inline(always)] + pub fn is_cycle64(&self) -> bool { + **self == STARTUP_A::CYCLE64 + } + #[doc = "Checks if the value of the field is `CYCLE128`"] + #[inline(always)] + pub fn is_cycle128(&self) -> bool { + **self == STARTUP_A::CYCLE128 + } + #[doc = "Checks if the value of the field is `CYCLE256`"] + #[inline(always)] + pub fn is_cycle256(&self) -> bool { + **self == STARTUP_A::CYCLE256 + } + #[doc = "Checks if the value of the field is `CYCLE512`"] + #[inline(always)] + pub fn is_cycle512(&self) -> bool { + **self == STARTUP_A::CYCLE512 + } + #[doc = "Checks if the value of the field is `CYCLE1024`"] + #[inline(always)] + pub fn is_cycle1024(&self) -> bool { + **self == STARTUP_A::CYCLE1024 + } + #[doc = "Checks if the value of the field is `CYCLE2048`"] + #[inline(always)] + pub fn is_cycle2048(&self) -> bool { + **self == STARTUP_A::CYCLE2048 + } + #[doc = "Checks if the value of the field is `CYCLE4096`"] + #[inline(always)] + pub fn is_cycle4096(&self) -> bool { + **self == STARTUP_A::CYCLE4096 + } + #[doc = "Checks if the value of the field is `CYCLE8192`"] + #[inline(always)] + pub fn is_cycle8192(&self) -> bool { + **self == STARTUP_A::CYCLE8192 + } + #[doc = "Checks if the value of the field is `CYCLE16384`"] + #[inline(always)] + pub fn is_cycle16384(&self) -> bool { + **self == STARTUP_A::CYCLE16384 + } + #[doc = "Checks if the value of the field is `CYCLE32768`"] + #[inline(always)] + pub fn is_cycle32768(&self) -> bool { + **self == STARTUP_A::CYCLE32768 + } +} +impl core::ops::Deref for STARTUP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STARTUP` writer - Start-Up Time"] +pub struct STARTUP_W<'a> { + w: &'a mut W, +} +impl<'a> STARTUP_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: STARTUP_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "31 us"] + #[inline(always)] + pub fn cycle1(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE1) + } + #[doc = "61 us"] + #[inline(always)] + pub fn cycle2(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE2) + } + #[doc = "122 us"] + #[inline(always)] + pub fn cycle4(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE4) + } + #[doc = "244 us"] + #[inline(always)] + pub fn cycle8(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE8) + } + #[doc = "488 us"] + #[inline(always)] + pub fn cycle16(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE16) + } + #[doc = "977 us"] + #[inline(always)] + pub fn cycle32(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE32) + } + #[doc = "1953 us"] + #[inline(always)] + pub fn cycle64(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE64) + } + #[doc = "3906 us"] + #[inline(always)] + pub fn cycle128(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE128) + } + #[doc = "7813 us"] + #[inline(always)] + pub fn cycle256(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE256) + } + #[doc = "15625 us"] + #[inline(always)] + pub fn cycle512(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE512) + } + #[doc = "31250 us"] + #[inline(always)] + pub fn cycle1024(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE1024) + } + #[doc = "62500 us"] + #[inline(always)] + pub fn cycle2048(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE2048) + } + #[doc = "125000 us"] + #[inline(always)] + pub fn cycle4096(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE4096) + } + #[doc = "250000 us"] + #[inline(always)] + pub fn cycle8192(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE8192) + } + #[doc = "500000 us"] + #[inline(always)] + pub fn cycle16384(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE16384) + } + #[doc = "1000000 us"] + #[inline(always)] + pub fn cycle32768(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE32768) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 12)) | ((value as u16 & 0x0f) << 12); + self.w + } +} +impl R { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Crystal Oscillator Enable"] + #[inline(always)] + pub fn xtalen(&self) -> XTALEN_R { + XTALEN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Xosc Clock Failure Detector Enable"] + #[inline(always)] + pub fn cfden(&self) -> CFDEN_R { + CFDEN_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Xosc Clock Switch Enable"] + #[inline(always)] + pub fn swben(&self) -> SWBEN_R { + SWBEN_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Oscillator Gain"] + #[inline(always)] + pub fn gain(&self) -> GAIN_R { + GAIN_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 11 - Automatic Amplitude Gain Control"] + #[inline(always)] + pub fn ampgc(&self) -> AMPGC_R { + AMPGC_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bits 12:15 - Start-Up Time"] + #[inline(always)] + pub fn startup(&self) -> STARTUP_R { + STARTUP_R::new(((self.bits >> 12) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - Crystal Oscillator Enable"] + #[inline(always)] + pub fn xtalen(&mut self) -> XTALEN_W { + XTALEN_W { w: self } + } + #[doc = "Bit 3 - Xosc Clock Failure Detector Enable"] + #[inline(always)] + pub fn cfden(&mut self) -> CFDEN_W { + CFDEN_W { w: self } + } + #[doc = "Bit 4 - Xosc Clock Switch Enable"] + #[inline(always)] + pub fn swben(&mut self) -> SWBEN_W { + SWBEN_W { w: self } + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Bits 8:10 - Oscillator Gain"] + #[inline(always)] + pub fn gain(&mut self) -> GAIN_W { + GAIN_W { w: self } + } + #[doc = "Bit 11 - Automatic Amplitude Gain Control"] + #[inline(always)] + pub fn ampgc(&mut self) -> AMPGC_W { + AMPGC_W { w: self } + } + #[doc = "Bits 12:15 - Start-Up Time"] + #[inline(always)] + pub fn startup(&mut self) -> STARTUP_W { + STARTUP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "External Multipurpose Crystal Oscillator (XOSC) Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [xoscctrl](index.html) module"] +pub struct XOSCCTRL_SPEC; +impl crate::RegisterSpec for XOSCCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [xoscctrl::R](R) reader structure"] +impl crate::Readable for XOSCCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [xoscctrl::W](W) writer structure"] +impl crate::Writable for XOSCCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets XOSCCTRL to value 0x80"] +impl crate::Resettable for XOSCCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x80 + } +} diff --git a/pac/atsamc20j/src/pac.rs b/pac/atsamc20j/src/pac.rs new file mode 100644 index 000000000000..3e365e081945 --- /dev/null +++ b/pac/atsamc20j/src/pac.rs @@ -0,0 +1,73 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Write control"] + pub wrctrl: crate::Reg, + #[doc = "0x04 - Event control"] + pub evctrl: crate::Reg, + _reserved2: [u8; 0x03], + #[doc = "0x08 - Interrupt enable clear"] + pub intenclr: crate::Reg, + #[doc = "0x09 - Interrupt enable set"] + pub intenset: crate::Reg, + _reserved4: [u8; 0x06], + #[doc = "0x10 - Bridge interrupt flag status"] + pub intflagahb: crate::Reg, + #[doc = "0x14 - Peripheral interrupt flag status - Bridge A"] + pub intflaga: crate::Reg, + #[doc = "0x18 - Peripheral interrupt flag status - Bridge B"] + pub intflagb: crate::Reg, + #[doc = "0x1c - Peripheral interrupt flag status - Bridge C"] + pub intflagc: crate::Reg, + _reserved8: [u8; 0x14], + #[doc = "0x34 - Peripheral write protection status - Bridge A"] + pub statusa: crate::Reg, + #[doc = "0x38 - Peripheral write protection status - Bridge B"] + pub statusb: crate::Reg, + #[doc = "0x3c - Peripheral write protection status - Bridge C"] + pub statusc: crate::Reg, +} +#[doc = "WRCTRL register accessor: an alias for `Reg`"] +pub type WRCTRL = crate::Reg; +#[doc = "Write control"] +pub mod wrctrl; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt enable clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt enable set"] +pub mod intenset; +#[doc = "INTFLAGAHB register accessor: an alias for `Reg`"] +pub type INTFLAGAHB = crate::Reg; +#[doc = "Bridge interrupt flag status"] +pub mod intflagahb; +#[doc = "INTFLAGA register accessor: an alias for `Reg`"] +pub type INTFLAGA = crate::Reg; +#[doc = "Peripheral interrupt flag status - Bridge A"] +pub mod intflaga; +#[doc = "INTFLAGB register accessor: an alias for `Reg`"] +pub type INTFLAGB = crate::Reg; +#[doc = "Peripheral interrupt flag status - Bridge B"] +pub mod intflagb; +#[doc = "INTFLAGC register accessor: an alias for `Reg`"] +pub type INTFLAGC = crate::Reg; +#[doc = "Peripheral interrupt flag status - Bridge C"] +pub mod intflagc; +#[doc = "STATUSA register accessor: an alias for `Reg`"] +pub type STATUSA = crate::Reg; +#[doc = "Peripheral write protection status - Bridge A"] +pub mod statusa; +#[doc = "STATUSB register accessor: an alias for `Reg`"] +pub type STATUSB = crate::Reg; +#[doc = "Peripheral write protection status - Bridge B"] +pub mod statusb; +#[doc = "STATUSC register accessor: an alias for `Reg`"] +pub type STATUSC = crate::Reg; +#[doc = "Peripheral write protection status - Bridge C"] +pub mod statusc; diff --git a/pac/atsamc20j/src/pac/evctrl.rs b/pac/atsamc20j/src/pac/evctrl.rs new file mode 100644 index 000000000000..630581b98c85 --- /dev/null +++ b/pac/atsamc20j/src/pac/evctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ERREO` reader - Peripheral acess error event output"] +pub struct ERREO_R(crate::FieldReader); +impl ERREO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERREO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERREO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERREO` writer - Peripheral acess error event output"] +pub struct ERREO_W<'a> { + w: &'a mut W, +} +impl<'a> ERREO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Peripheral acess error event output"] + #[inline(always)] + pub fn erreo(&self) -> ERREO_R { + ERREO_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Peripheral acess error event output"] + #[inline(always)] + pub fn erreo(&mut self) -> ERREO_W { + ERREO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/pac/intenclr.rs b/pac/atsamc20j/src/pac/intenclr.rs new file mode 100644 index 000000000000..609fe0fcf628 --- /dev/null +++ b/pac/atsamc20j/src/pac/intenclr.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ERR` reader - Peripheral access error interrupt disable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - Peripheral access error interrupt disable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Peripheral access error interrupt disable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Peripheral access error interrupt disable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt enable clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/pac/intenset.rs b/pac/atsamc20j/src/pac/intenset.rs new file mode 100644 index 000000000000..390545b588de --- /dev/null +++ b/pac/atsamc20j/src/pac/intenset.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ERR` reader - Peripheral access error interrupt enable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - Peripheral access error interrupt enable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Peripheral access error interrupt enable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Peripheral access error interrupt enable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt enable set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/pac/intflaga.rs b/pac/atsamc20j/src/pac/intflaga.rs new file mode 100644 index 000000000000..df4c8554d9ab --- /dev/null +++ b/pac/atsamc20j/src/pac/intflaga.rs @@ -0,0 +1,630 @@ +#[doc = "Register `INTFLAGA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAGA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PAC_` reader - PAC"] +pub struct PAC__R(crate::FieldReader); +impl PAC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PAC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PAC_` writer - PAC"] +pub struct PAC__W<'a> { + w: &'a mut W, +} +impl<'a> PAC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `PM_` reader - PM"] +pub struct PM__R(crate::FieldReader); +impl PM__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PM__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PM__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PM_` writer - PM"] +pub struct PM__W<'a> { + w: &'a mut W, +} +impl<'a> PM__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MCLK_` reader - MCLK"] +pub struct MCLK__R(crate::FieldReader); +impl MCLK__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCLK__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCLK__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCLK_` writer - MCLK"] +pub struct MCLK__W<'a> { + w: &'a mut W, +} +impl<'a> MCLK__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RSTC_` reader - RSTC"] +pub struct RSTC__R(crate::FieldReader); +impl RSTC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RSTC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RSTC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RSTC_` writer - RSTC"] +pub struct RSTC__W<'a> { + w: &'a mut W, +} +impl<'a> RSTC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `OSCCTRL_` reader - OSCCTRL"] +pub struct OSCCTRL__R(crate::FieldReader); +impl OSCCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSCCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSCCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSCCTRL_` writer - OSCCTRL"] +pub struct OSCCTRL__W<'a> { + w: &'a mut W, +} +impl<'a> OSCCTRL__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `OSC32KCTRL_` reader - OSC32KCTRL"] +pub struct OSC32KCTRL__R(crate::FieldReader); +impl OSC32KCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC32KCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC32KCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC32KCTRL_` writer - OSC32KCTRL"] +pub struct OSC32KCTRL__W<'a> { + w: &'a mut W, +} +impl<'a> OSC32KCTRL__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `SUPC_` reader - SUPC"] +pub struct SUPC__R(crate::FieldReader); +impl SUPC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SUPC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SUPC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SUPC_` writer - SUPC"] +pub struct SUPC__W<'a> { + w: &'a mut W, +} +impl<'a> SUPC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `GCLK_` reader - GCLK"] +pub struct GCLK__R(crate::FieldReader); +impl GCLK__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GCLK__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GCLK__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GCLK_` writer - GCLK"] +pub struct GCLK__W<'a> { + w: &'a mut W, +} +impl<'a> GCLK__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `WDT_` reader - WDT"] +pub struct WDT__R(crate::FieldReader); +impl WDT__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WDT__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WDT__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WDT_` writer - WDT"] +pub struct WDT__W<'a> { + w: &'a mut W, +} +impl<'a> WDT__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `RTC_` reader - RTC"] +pub struct RTC__R(crate::FieldReader); +impl RTC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RTC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RTC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RTC_` writer - RTC"] +pub struct RTC__W<'a> { + w: &'a mut W, +} +impl<'a> RTC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `EIC_` reader - EIC"] +pub struct EIC__R(crate::FieldReader); +impl EIC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EIC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EIC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EIC_` writer - EIC"] +pub struct EIC__W<'a> { + w: &'a mut W, +} +impl<'a> EIC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `FREQM_` reader - FREQM"] +pub struct FREQM__R(crate::FieldReader); +impl FREQM__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FREQM__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FREQM__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FREQM_` writer - FREQM"] +pub struct FREQM__W<'a> { + w: &'a mut W, +} +impl<'a> FREQM__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +impl R { + #[doc = "Bit 0 - PAC"] + #[inline(always)] + pub fn pac_(&self) -> PAC__R { + PAC__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - PM"] + #[inline(always)] + pub fn pm_(&self) -> PM__R { + PM__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - MCLK"] + #[inline(always)] + pub fn mclk_(&self) -> MCLK__R { + MCLK__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - RSTC"] + #[inline(always)] + pub fn rstc_(&self) -> RSTC__R { + RSTC__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - OSCCTRL"] + #[inline(always)] + pub fn oscctrl_(&self) -> OSCCTRL__R { + OSCCTRL__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - OSC32KCTRL"] + #[inline(always)] + pub fn osc32kctrl_(&self) -> OSC32KCTRL__R { + OSC32KCTRL__R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - SUPC"] + #[inline(always)] + pub fn supc_(&self) -> SUPC__R { + SUPC__R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - GCLK"] + #[inline(always)] + pub fn gclk_(&self) -> GCLK__R { + GCLK__R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - WDT"] + #[inline(always)] + pub fn wdt_(&self) -> WDT__R { + WDT__R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - RTC"] + #[inline(always)] + pub fn rtc_(&self) -> RTC__R { + RTC__R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - EIC"] + #[inline(always)] + pub fn eic_(&self) -> EIC__R { + EIC__R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - FREQM"] + #[inline(always)] + pub fn freqm_(&self) -> FREQM__R { + FREQM__R::new(((self.bits >> 11) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - PAC"] + #[inline(always)] + pub fn pac_(&mut self) -> PAC__W { + PAC__W { w: self } + } + #[doc = "Bit 1 - PM"] + #[inline(always)] + pub fn pm_(&mut self) -> PM__W { + PM__W { w: self } + } + #[doc = "Bit 2 - MCLK"] + #[inline(always)] + pub fn mclk_(&mut self) -> MCLK__W { + MCLK__W { w: self } + } + #[doc = "Bit 3 - RSTC"] + #[inline(always)] + pub fn rstc_(&mut self) -> RSTC__W { + RSTC__W { w: self } + } + #[doc = "Bit 4 - OSCCTRL"] + #[inline(always)] + pub fn oscctrl_(&mut self) -> OSCCTRL__W { + OSCCTRL__W { w: self } + } + #[doc = "Bit 5 - OSC32KCTRL"] + #[inline(always)] + pub fn osc32kctrl_(&mut self) -> OSC32KCTRL__W { + OSC32KCTRL__W { w: self } + } + #[doc = "Bit 6 - SUPC"] + #[inline(always)] + pub fn supc_(&mut self) -> SUPC__W { + SUPC__W { w: self } + } + #[doc = "Bit 7 - GCLK"] + #[inline(always)] + pub fn gclk_(&mut self) -> GCLK__W { + GCLK__W { w: self } + } + #[doc = "Bit 8 - WDT"] + #[inline(always)] + pub fn wdt_(&mut self) -> WDT__W { + WDT__W { w: self } + } + #[doc = "Bit 9 - RTC"] + #[inline(always)] + pub fn rtc_(&mut self) -> RTC__W { + RTC__W { w: self } + } + #[doc = "Bit 10 - EIC"] + #[inline(always)] + pub fn eic_(&mut self) -> EIC__W { + EIC__W { w: self } + } + #[doc = "Bit 11 - FREQM"] + #[inline(always)] + pub fn freqm_(&mut self) -> FREQM__W { + FREQM__W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Peripheral interrupt flag status - Bridge A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflaga](index.html) module"] +pub struct INTFLAGA_SPEC; +impl crate::RegisterSpec for INTFLAGA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflaga::R](R) reader structure"] +impl crate::Readable for INTFLAGA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflaga::W](W) writer structure"] +impl crate::Writable for INTFLAGA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAGA to value 0"] +impl crate::Resettable for INTFLAGA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/pac/intflagahb.rs b/pac/atsamc20j/src/pac/intflagahb.rs new file mode 100644 index 000000000000..4b7f7377e25e --- /dev/null +++ b/pac/atsamc20j/src/pac/intflagahb.rs @@ -0,0 +1,442 @@ +#[doc = "Register `INTFLAGAHB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAGAHB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FLASH_` reader - FLASH"] +pub struct FLASH__R(crate::FieldReader); +impl FLASH__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FLASH__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FLASH__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLASH_` writer - FLASH"] +pub struct FLASH__W<'a> { + w: &'a mut W, +} +impl<'a> FLASH__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `HSRAMCM0P_` reader - HSRAMCM0P"] +pub struct HSRAMCM0P__R(crate::FieldReader); +impl HSRAMCM0P__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HSRAMCM0P__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HSRAMCM0P__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HSRAMCM0P_` writer - HSRAMCM0P"] +pub struct HSRAMCM0P__W<'a> { + w: &'a mut W, +} +impl<'a> HSRAMCM0P__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `HSRAMDSU_` reader - HSRAMDSU"] +pub struct HSRAMDSU__R(crate::FieldReader); +impl HSRAMDSU__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HSRAMDSU__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HSRAMDSU__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HSRAMDSU_` writer - HSRAMDSU"] +pub struct HSRAMDSU__W<'a> { + w: &'a mut W, +} +impl<'a> HSRAMDSU__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `HPB1_` reader - HPB1"] +pub struct HPB1__R(crate::FieldReader); +impl HPB1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HPB1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HPB1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HPB1_` writer - HPB1"] +pub struct HPB1__W<'a> { + w: &'a mut W, +} +impl<'a> HPB1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `HPB0_` reader - HPB0"] +pub struct HPB0__R(crate::FieldReader); +impl HPB0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HPB0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HPB0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HPB0_` writer - HPB0"] +pub struct HPB0__W<'a> { + w: &'a mut W, +} +impl<'a> HPB0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `HPB2_` reader - HPB2"] +pub struct HPB2__R(crate::FieldReader); +impl HPB2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HPB2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HPB2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HPB2_` writer - HPB2"] +pub struct HPB2__W<'a> { + w: &'a mut W, +} +impl<'a> HPB2__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `LPRAMDMAC_` reader - LPRAMDMAC"] +pub struct LPRAMDMAC__R(crate::FieldReader); +impl LPRAMDMAC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LPRAMDMAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LPRAMDMAC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LPRAMDMAC_` writer - LPRAMDMAC"] +pub struct LPRAMDMAC__W<'a> { + w: &'a mut W, +} +impl<'a> LPRAMDMAC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `DIVAS_` reader - DIVAS"] +pub struct DIVAS__R(crate::FieldReader); +impl DIVAS__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIVAS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIVAS__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIVAS_` writer - DIVAS"] +pub struct DIVAS__W<'a> { + w: &'a mut W, +} +impl<'a> DIVAS__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - FLASH"] + #[inline(always)] + pub fn flash_(&self) -> FLASH__R { + FLASH__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - HSRAMCM0P"] + #[inline(always)] + pub fn hsramcm0p_(&self) -> HSRAMCM0P__R { + HSRAMCM0P__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - HSRAMDSU"] + #[inline(always)] + pub fn hsramdsu_(&self) -> HSRAMDSU__R { + HSRAMDSU__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - HPB1"] + #[inline(always)] + pub fn hpb1_(&self) -> HPB1__R { + HPB1__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - HPB0"] + #[inline(always)] + pub fn hpb0_(&self) -> HPB0__R { + HPB0__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - HPB2"] + #[inline(always)] + pub fn hpb2_(&self) -> HPB2__R { + HPB2__R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - LPRAMDMAC"] + #[inline(always)] + pub fn lpramdmac_(&self) -> LPRAMDMAC__R { + LPRAMDMAC__R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - DIVAS"] + #[inline(always)] + pub fn divas_(&self) -> DIVAS__R { + DIVAS__R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - FLASH"] + #[inline(always)] + pub fn flash_(&mut self) -> FLASH__W { + FLASH__W { w: self } + } + #[doc = "Bit 1 - HSRAMCM0P"] + #[inline(always)] + pub fn hsramcm0p_(&mut self) -> HSRAMCM0P__W { + HSRAMCM0P__W { w: self } + } + #[doc = "Bit 2 - HSRAMDSU"] + #[inline(always)] + pub fn hsramdsu_(&mut self) -> HSRAMDSU__W { + HSRAMDSU__W { w: self } + } + #[doc = "Bit 3 - HPB1"] + #[inline(always)] + pub fn hpb1_(&mut self) -> HPB1__W { + HPB1__W { w: self } + } + #[doc = "Bit 4 - HPB0"] + #[inline(always)] + pub fn hpb0_(&mut self) -> HPB0__W { + HPB0__W { w: self } + } + #[doc = "Bit 5 - HPB2"] + #[inline(always)] + pub fn hpb2_(&mut self) -> HPB2__W { + HPB2__W { w: self } + } + #[doc = "Bit 6 - LPRAMDMAC"] + #[inline(always)] + pub fn lpramdmac_(&mut self) -> LPRAMDMAC__W { + LPRAMDMAC__W { w: self } + } + #[doc = "Bit 7 - DIVAS"] + #[inline(always)] + pub fn divas_(&mut self) -> DIVAS__W { + DIVAS__W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Bridge interrupt flag status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflagahb](index.html) module"] +pub struct INTFLAGAHB_SPEC; +impl crate::RegisterSpec for INTFLAGAHB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflagahb::R](R) reader structure"] +impl crate::Readable for INTFLAGAHB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflagahb::W](W) writer structure"] +impl crate::Writable for INTFLAGAHB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAGAHB to value 0"] +impl crate::Resettable for INTFLAGAHB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/pac/intflagb.rs b/pac/atsamc20j/src/pac/intflagb.rs new file mode 100644 index 000000000000..8359f7e11f30 --- /dev/null +++ b/pac/atsamc20j/src/pac/intflagb.rs @@ -0,0 +1,348 @@ +#[doc = "Register `INTFLAGB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAGB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PORT_` reader - PORT"] +pub struct PORT__R(crate::FieldReader); +impl PORT__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PORT__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PORT__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PORT_` writer - PORT"] +pub struct PORT__W<'a> { + w: &'a mut W, +} +impl<'a> PORT__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `DSU_` reader - DSU"] +pub struct DSU__R(crate::FieldReader); +impl DSU__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DSU__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DSU__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DSU_` writer - DSU"] +pub struct DSU__W<'a> { + w: &'a mut W, +} +impl<'a> DSU__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `NVMCTRL_` reader - NVMCTRL"] +pub struct NVMCTRL__R(crate::FieldReader); +impl NVMCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NVMCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NVMCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NVMCTRL_` writer - NVMCTRL"] +pub struct NVMCTRL__W<'a> { + w: &'a mut W, +} +impl<'a> NVMCTRL__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `DMAC_` reader - DMAC"] +pub struct DMAC__R(crate::FieldReader); +impl DMAC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DMAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DMAC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DMAC_` writer - DMAC"] +pub struct DMAC__W<'a> { + w: &'a mut W, +} +impl<'a> DMAC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `MTB_` reader - MTB"] +pub struct MTB__R(crate::FieldReader); +impl MTB__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MTB__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MTB__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MTB_` writer - MTB"] +pub struct MTB__W<'a> { + w: &'a mut W, +} +impl<'a> MTB__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `HMATRIXHS_` reader - HMATRIXHS"] +pub struct HMATRIXHS__R(crate::FieldReader); +impl HMATRIXHS__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HMATRIXHS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HMATRIXHS__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HMATRIXHS_` writer - HMATRIXHS"] +pub struct HMATRIXHS__W<'a> { + w: &'a mut W, +} +impl<'a> HMATRIXHS__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - PORT"] + #[inline(always)] + pub fn port_(&self) -> PORT__R { + PORT__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - DSU"] + #[inline(always)] + pub fn dsu_(&self) -> DSU__R { + DSU__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - NVMCTRL"] + #[inline(always)] + pub fn nvmctrl_(&self) -> NVMCTRL__R { + NVMCTRL__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - DMAC"] + #[inline(always)] + pub fn dmac_(&self) -> DMAC__R { + DMAC__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - MTB"] + #[inline(always)] + pub fn mtb_(&self) -> MTB__R { + MTB__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - HMATRIXHS"] + #[inline(always)] + pub fn hmatrixhs_(&self) -> HMATRIXHS__R { + HMATRIXHS__R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - PORT"] + #[inline(always)] + pub fn port_(&mut self) -> PORT__W { + PORT__W { w: self } + } + #[doc = "Bit 1 - DSU"] + #[inline(always)] + pub fn dsu_(&mut self) -> DSU__W { + DSU__W { w: self } + } + #[doc = "Bit 2 - NVMCTRL"] + #[inline(always)] + pub fn nvmctrl_(&mut self) -> NVMCTRL__W { + NVMCTRL__W { w: self } + } + #[doc = "Bit 3 - DMAC"] + #[inline(always)] + pub fn dmac_(&mut self) -> DMAC__W { + DMAC__W { w: self } + } + #[doc = "Bit 4 - MTB"] + #[inline(always)] + pub fn mtb_(&mut self) -> MTB__W { + MTB__W { w: self } + } + #[doc = "Bit 5 - HMATRIXHS"] + #[inline(always)] + pub fn hmatrixhs_(&mut self) -> HMATRIXHS__W { + HMATRIXHS__W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Peripheral interrupt flag status - Bridge B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflagb](index.html) module"] +pub struct INTFLAGB_SPEC; +impl crate::RegisterSpec for INTFLAGB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflagb::R](R) reader structure"] +impl crate::Readable for INTFLAGB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflagb::W](W) writer structure"] +impl crate::Writable for INTFLAGB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAGB to value 0"] +impl crate::Resettable for INTFLAGB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/pac/intflagc.rs b/pac/atsamc20j/src/pac/intflagc.rs new file mode 100644 index 000000000000..25a236fa631a --- /dev/null +++ b/pac/atsamc20j/src/pac/intflagc.rs @@ -0,0 +1,865 @@ +#[doc = "Register `INTFLAGC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAGC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVSYS_` reader - EVSYS"] +pub struct EVSYS__R(crate::FieldReader); +impl EVSYS__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVSYS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVSYS__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVSYS_` writer - EVSYS"] +pub struct EVSYS__W<'a> { + w: &'a mut W, +} +impl<'a> EVSYS__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `SERCOM0_` reader - SERCOM0"] +pub struct SERCOM0__R(crate::FieldReader); +impl SERCOM0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM0_` writer - SERCOM0"] +pub struct SERCOM0__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SERCOM1_` reader - SERCOM1"] +pub struct SERCOM1__R(crate::FieldReader); +impl SERCOM1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM1_` writer - SERCOM1"] +pub struct SERCOM1__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SERCOM2_` reader - SERCOM2"] +pub struct SERCOM2__R(crate::FieldReader); +impl SERCOM2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM2_` writer - SERCOM2"] +pub struct SERCOM2__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM2__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `SERCOM3_` reader - SERCOM3"] +pub struct SERCOM3__R(crate::FieldReader); +impl SERCOM3__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM3__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM3__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM3_` writer - SERCOM3"] +pub struct SERCOM3__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM3__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `TCC0_` reader - TCC0"] +pub struct TCC0__R(crate::FieldReader); +impl TCC0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCC0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCC0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCC0_` writer - TCC0"] +pub struct TCC0__W<'a> { + w: &'a mut W, +} +impl<'a> TCC0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `TCC1_` reader - TCC1"] +pub struct TCC1__R(crate::FieldReader); +impl TCC1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCC1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCC1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCC1_` writer - TCC1"] +pub struct TCC1__W<'a> { + w: &'a mut W, +} +impl<'a> TCC1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `TCC2_` reader - TCC2"] +pub struct TCC2__R(crate::FieldReader); +impl TCC2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCC2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCC2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCC2_` writer - TCC2"] +pub struct TCC2__W<'a> { + w: &'a mut W, +} +impl<'a> TCC2__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `TC0_` reader - TC0"] +pub struct TC0__R(crate::FieldReader); +impl TC0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC0_` writer - TC0"] +pub struct TC0__W<'a> { + w: &'a mut W, +} +impl<'a> TC0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `TC1_` reader - TC1"] +pub struct TC1__R(crate::FieldReader); +impl TC1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC1_` writer - TC1"] +pub struct TC1__W<'a> { + w: &'a mut W, +} +impl<'a> TC1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `TC2_` reader - TC2"] +pub struct TC2__R(crate::FieldReader); +impl TC2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC2_` writer - TC2"] +pub struct TC2__W<'a> { + w: &'a mut W, +} +impl<'a> TC2__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `TC3_` reader - TC3"] +pub struct TC3__R(crate::FieldReader); +impl TC3__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC3__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC3__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC3_` writer - TC3"] +pub struct TC3__W<'a> { + w: &'a mut W, +} +impl<'a> TC3__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `TC4_` reader - TC4"] +pub struct TC4__R(crate::FieldReader); +impl TC4__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC4__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC4__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC4_` writer - TC4"] +pub struct TC4__W<'a> { + w: &'a mut W, +} +impl<'a> TC4__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `ADC0_` reader - ADC0"] +pub struct ADC0__R(crate::FieldReader); +impl ADC0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ADC0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADC0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADC0_` writer - ADC0"] +pub struct ADC0__W<'a> { + w: &'a mut W, +} +impl<'a> ADC0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `AC_` reader - AC"] +pub struct AC__R(crate::FieldReader); +impl AC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AC_` writer - AC"] +pub struct AC__W<'a> { + w: &'a mut W, +} +impl<'a> AC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `PTC_` reader - PTC"] +pub struct PTC__R(crate::FieldReader); +impl PTC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PTC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PTC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PTC_` writer - PTC"] +pub struct PTC__W<'a> { + w: &'a mut W, +} +impl<'a> PTC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `CCL_` reader - CCL"] +pub struct CCL__R(crate::FieldReader); +impl CCL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCL_` writer - CCL"] +pub struct CCL__W<'a> { + w: &'a mut W, +} +impl<'a> CCL__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +impl R { + #[doc = "Bit 0 - EVSYS"] + #[inline(always)] + pub fn evsys_(&self) -> EVSYS__R { + EVSYS__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM0"] + #[inline(always)] + pub fn sercom0_(&self) -> SERCOM0__R { + SERCOM0__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - SERCOM1"] + #[inline(always)] + pub fn sercom1_(&self) -> SERCOM1__R { + SERCOM1__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - SERCOM2"] + #[inline(always)] + pub fn sercom2_(&self) -> SERCOM2__R { + SERCOM2__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - SERCOM3"] + #[inline(always)] + pub fn sercom3_(&self) -> SERCOM3__R { + SERCOM3__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 9 - TCC0"] + #[inline(always)] + pub fn tcc0_(&self) -> TCC0__R { + TCC0__R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - TCC1"] + #[inline(always)] + pub fn tcc1_(&self) -> TCC1__R { + TCC1__R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - TCC2"] + #[inline(always)] + pub fn tcc2_(&self) -> TCC2__R { + TCC2__R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - TC0"] + #[inline(always)] + pub fn tc0_(&self) -> TC0__R { + TC0__R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - TC1"] + #[inline(always)] + pub fn tc1_(&self) -> TC1__R { + TC1__R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - TC2"] + #[inline(always)] + pub fn tc2_(&self) -> TC2__R { + TC2__R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - TC3"] + #[inline(always)] + pub fn tc3_(&self) -> TC3__R { + TC3__R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - TC4"] + #[inline(always)] + pub fn tc4_(&self) -> TC4__R { + TC4__R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - ADC0"] + #[inline(always)] + pub fn adc0_(&self) -> ADC0__R { + ADC0__R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 20 - AC"] + #[inline(always)] + pub fn ac_(&self) -> AC__R { + AC__R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 22 - PTC"] + #[inline(always)] + pub fn ptc_(&self) -> PTC__R { + PTC__R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - CCL"] + #[inline(always)] + pub fn ccl_(&self) -> CCL__R { + CCL__R::new(((self.bits >> 23) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - EVSYS"] + #[inline(always)] + pub fn evsys_(&mut self) -> EVSYS__W { + EVSYS__W { w: self } + } + #[doc = "Bit 1 - SERCOM0"] + #[inline(always)] + pub fn sercom0_(&mut self) -> SERCOM0__W { + SERCOM0__W { w: self } + } + #[doc = "Bit 2 - SERCOM1"] + #[inline(always)] + pub fn sercom1_(&mut self) -> SERCOM1__W { + SERCOM1__W { w: self } + } + #[doc = "Bit 3 - SERCOM2"] + #[inline(always)] + pub fn sercom2_(&mut self) -> SERCOM2__W { + SERCOM2__W { w: self } + } + #[doc = "Bit 4 - SERCOM3"] + #[inline(always)] + pub fn sercom3_(&mut self) -> SERCOM3__W { + SERCOM3__W { w: self } + } + #[doc = "Bit 9 - TCC0"] + #[inline(always)] + pub fn tcc0_(&mut self) -> TCC0__W { + TCC0__W { w: self } + } + #[doc = "Bit 10 - TCC1"] + #[inline(always)] + pub fn tcc1_(&mut self) -> TCC1__W { + TCC1__W { w: self } + } + #[doc = "Bit 11 - TCC2"] + #[inline(always)] + pub fn tcc2_(&mut self) -> TCC2__W { + TCC2__W { w: self } + } + #[doc = "Bit 12 - TC0"] + #[inline(always)] + pub fn tc0_(&mut self) -> TC0__W { + TC0__W { w: self } + } + #[doc = "Bit 13 - TC1"] + #[inline(always)] + pub fn tc1_(&mut self) -> TC1__W { + TC1__W { w: self } + } + #[doc = "Bit 14 - TC2"] + #[inline(always)] + pub fn tc2_(&mut self) -> TC2__W { + TC2__W { w: self } + } + #[doc = "Bit 15 - TC3"] + #[inline(always)] + pub fn tc3_(&mut self) -> TC3__W { + TC3__W { w: self } + } + #[doc = "Bit 16 - TC4"] + #[inline(always)] + pub fn tc4_(&mut self) -> TC4__W { + TC4__W { w: self } + } + #[doc = "Bit 17 - ADC0"] + #[inline(always)] + pub fn adc0_(&mut self) -> ADC0__W { + ADC0__W { w: self } + } + #[doc = "Bit 20 - AC"] + #[inline(always)] + pub fn ac_(&mut self) -> AC__W { + AC__W { w: self } + } + #[doc = "Bit 22 - PTC"] + #[inline(always)] + pub fn ptc_(&mut self) -> PTC__W { + PTC__W { w: self } + } + #[doc = "Bit 23 - CCL"] + #[inline(always)] + pub fn ccl_(&mut self) -> CCL__W { + CCL__W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Peripheral interrupt flag status - Bridge C\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflagc](index.html) module"] +pub struct INTFLAGC_SPEC; +impl crate::RegisterSpec for INTFLAGC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflagc::R](R) reader structure"] +impl crate::Readable for INTFLAGC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflagc::W](W) writer structure"] +impl crate::Writable for INTFLAGC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAGC to value 0"] +impl crate::Resettable for INTFLAGC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/pac/statusa.rs b/pac/atsamc20j/src/pac/statusa.rs new file mode 100644 index 000000000000..32974f65e5d5 --- /dev/null +++ b/pac/atsamc20j/src/pac/statusa.rs @@ -0,0 +1,273 @@ +#[doc = "Register `STATUSA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PAC_` reader - PAC APB Protect Enable"] +pub struct PAC__R(crate::FieldReader); +impl PAC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PAC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PM_` reader - PM APB Protect Enable"] +pub struct PM__R(crate::FieldReader); +impl PM__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PM__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PM__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCLK_` reader - MCLK APB Protect Enable"] +pub struct MCLK__R(crate::FieldReader); +impl MCLK__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCLK__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCLK__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RSTC_` reader - RSTC APB Protect Enable"] +pub struct RSTC__R(crate::FieldReader); +impl RSTC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RSTC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RSTC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSCCTRL_` reader - OSCCTRL APB Protect Enable"] +pub struct OSCCTRL__R(crate::FieldReader); +impl OSCCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSCCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSCCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC32KCTRL_` reader - OSC32KCTRL APB Protect Enable"] +pub struct OSC32KCTRL__R(crate::FieldReader); +impl OSC32KCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC32KCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC32KCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SUPC_` reader - SUPC APB Protect Enable"] +pub struct SUPC__R(crate::FieldReader); +impl SUPC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SUPC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SUPC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GCLK_` reader - GCLK APB Protect Enable"] +pub struct GCLK__R(crate::FieldReader); +impl GCLK__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GCLK__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GCLK__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WDT_` reader - WDT APB Protect Enable"] +pub struct WDT__R(crate::FieldReader); +impl WDT__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WDT__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WDT__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RTC_` reader - RTC APB Protect Enable"] +pub struct RTC__R(crate::FieldReader); +impl RTC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RTC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RTC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EIC_` reader - EIC APB Protect Enable"] +pub struct EIC__R(crate::FieldReader); +impl EIC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EIC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EIC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FREQM_` reader - FREQM APB Protect Enable"] +pub struct FREQM__R(crate::FieldReader); +impl FREQM__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FREQM__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FREQM__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - PAC APB Protect Enable"] + #[inline(always)] + pub fn pac_(&self) -> PAC__R { + PAC__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - PM APB Protect Enable"] + #[inline(always)] + pub fn pm_(&self) -> PM__R { + PM__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - MCLK APB Protect Enable"] + #[inline(always)] + pub fn mclk_(&self) -> MCLK__R { + MCLK__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - RSTC APB Protect Enable"] + #[inline(always)] + pub fn rstc_(&self) -> RSTC__R { + RSTC__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - OSCCTRL APB Protect Enable"] + #[inline(always)] + pub fn oscctrl_(&self) -> OSCCTRL__R { + OSCCTRL__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - OSC32KCTRL APB Protect Enable"] + #[inline(always)] + pub fn osc32kctrl_(&self) -> OSC32KCTRL__R { + OSC32KCTRL__R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - SUPC APB Protect Enable"] + #[inline(always)] + pub fn supc_(&self) -> SUPC__R { + SUPC__R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - GCLK APB Protect Enable"] + #[inline(always)] + pub fn gclk_(&self) -> GCLK__R { + GCLK__R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - WDT APB Protect Enable"] + #[inline(always)] + pub fn wdt_(&self) -> WDT__R { + WDT__R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - RTC APB Protect Enable"] + #[inline(always)] + pub fn rtc_(&self) -> RTC__R { + RTC__R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - EIC APB Protect Enable"] + #[inline(always)] + pub fn eic_(&self) -> EIC__R { + EIC__R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - FREQM APB Protect Enable"] + #[inline(always)] + pub fn freqm_(&self) -> FREQM__R { + FREQM__R::new(((self.bits >> 11) & 0x01) != 0) + } +} +#[doc = "Peripheral write protection status - Bridge A\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [statusa](index.html) module"] +pub struct STATUSA_SPEC; +impl crate::RegisterSpec for STATUSA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [statusa::R](R) reader structure"] +impl crate::Readable for STATUSA_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUSA to value 0"] +impl crate::Resettable for STATUSA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/pac/statusb.rs b/pac/atsamc20j/src/pac/statusb.rs new file mode 100644 index 000000000000..a022cc2f1d54 --- /dev/null +++ b/pac/atsamc20j/src/pac/statusb.rs @@ -0,0 +1,153 @@ +#[doc = "Register `STATUSB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PORT_` reader - PORT APB Protect Enable"] +pub struct PORT__R(crate::FieldReader); +impl PORT__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PORT__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PORT__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DSU_` reader - DSU APB Protect Enable"] +pub struct DSU__R(crate::FieldReader); +impl DSU__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DSU__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DSU__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NVMCTRL_` reader - NVMCTRL APB Protect Enable"] +pub struct NVMCTRL__R(crate::FieldReader); +impl NVMCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NVMCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NVMCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DMAC_` reader - DMAC APB Protect Enable"] +pub struct DMAC__R(crate::FieldReader); +impl DMAC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DMAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DMAC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MTB_` reader - MTB APB Protect Enable"] +pub struct MTB__R(crate::FieldReader); +impl MTB__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MTB__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MTB__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HMATRIXHS_` reader - HMATRIXHS APB Protect Enable"] +pub struct HMATRIXHS__R(crate::FieldReader); +impl HMATRIXHS__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HMATRIXHS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HMATRIXHS__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - PORT APB Protect Enable"] + #[inline(always)] + pub fn port_(&self) -> PORT__R { + PORT__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - DSU APB Protect Enable"] + #[inline(always)] + pub fn dsu_(&self) -> DSU__R { + DSU__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - NVMCTRL APB Protect Enable"] + #[inline(always)] + pub fn nvmctrl_(&self) -> NVMCTRL__R { + NVMCTRL__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - DMAC APB Protect Enable"] + #[inline(always)] + pub fn dmac_(&self) -> DMAC__R { + DMAC__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - MTB APB Protect Enable"] + #[inline(always)] + pub fn mtb_(&self) -> MTB__R { + MTB__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - HMATRIXHS APB Protect Enable"] + #[inline(always)] + pub fn hmatrixhs_(&self) -> HMATRIXHS__R { + HMATRIXHS__R::new(((self.bits >> 5) & 0x01) != 0) + } +} +#[doc = "Peripheral write protection status - Bridge B\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [statusb](index.html) module"] +pub struct STATUSB_SPEC; +impl crate::RegisterSpec for STATUSB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [statusb::R](R) reader structure"] +impl crate::Readable for STATUSB_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUSB to value 0x02"] +impl crate::Resettable for STATUSB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x02 + } +} diff --git a/pac/atsamc20j/src/pac/statusc.rs b/pac/atsamc20j/src/pac/statusc.rs new file mode 100644 index 000000000000..744a02d7454f --- /dev/null +++ b/pac/atsamc20j/src/pac/statusc.rs @@ -0,0 +1,373 @@ +#[doc = "Register `STATUSC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `EVSYS_` reader - EVSYS APB Protect Enable"] +pub struct EVSYS__R(crate::FieldReader); +impl EVSYS__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVSYS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVSYS__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM0_` reader - SERCOM0 APB Protect Enable"] +pub struct SERCOM0__R(crate::FieldReader); +impl SERCOM0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM1_` reader - SERCOM1 APB Protect Enable"] +pub struct SERCOM1__R(crate::FieldReader); +impl SERCOM1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM2_` reader - SERCOM2 APB Protect Enable"] +pub struct SERCOM2__R(crate::FieldReader); +impl SERCOM2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM3_` reader - SERCOM3 APB Protect Enable"] +pub struct SERCOM3__R(crate::FieldReader); +impl SERCOM3__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM3__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM3__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCC0_` reader - TCC0 APB Protect Enable"] +pub struct TCC0__R(crate::FieldReader); +impl TCC0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCC0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCC0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCC1_` reader - TCC1 APB Protect Enable"] +pub struct TCC1__R(crate::FieldReader); +impl TCC1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCC1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCC1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCC2_` reader - TCC2 APB Protect Enable"] +pub struct TCC2__R(crate::FieldReader); +impl TCC2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCC2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCC2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC0_` reader - TC0 APB Protect Enable"] +pub struct TC0__R(crate::FieldReader); +impl TC0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC1_` reader - TC1 APB Protect Enable"] +pub struct TC1__R(crate::FieldReader); +impl TC1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC2_` reader - TC2 APB Protect Enable"] +pub struct TC2__R(crate::FieldReader); +impl TC2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC3_` reader - TC3 APB Protect Enable"] +pub struct TC3__R(crate::FieldReader); +impl TC3__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC3__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC3__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC4_` reader - TC4 APB Protect Enable"] +pub struct TC4__R(crate::FieldReader); +impl TC4__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC4__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC4__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADC0_` reader - ADC0 APB Protect Enable"] +pub struct ADC0__R(crate::FieldReader); +impl ADC0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ADC0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADC0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AC_` reader - AC APB Protect Enable"] +pub struct AC__R(crate::FieldReader); +impl AC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PTC_` reader - PTC APB Protect Enable"] +pub struct PTC__R(crate::FieldReader); +impl PTC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PTC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PTC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCL_` reader - CCL APB Protect Enable"] +pub struct CCL__R(crate::FieldReader); +impl CCL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - EVSYS APB Protect Enable"] + #[inline(always)] + pub fn evsys_(&self) -> EVSYS__R { + EVSYS__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM0 APB Protect Enable"] + #[inline(always)] + pub fn sercom0_(&self) -> SERCOM0__R { + SERCOM0__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - SERCOM1 APB Protect Enable"] + #[inline(always)] + pub fn sercom1_(&self) -> SERCOM1__R { + SERCOM1__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - SERCOM2 APB Protect Enable"] + #[inline(always)] + pub fn sercom2_(&self) -> SERCOM2__R { + SERCOM2__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - SERCOM3 APB Protect Enable"] + #[inline(always)] + pub fn sercom3_(&self) -> SERCOM3__R { + SERCOM3__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 9 - TCC0 APB Protect Enable"] + #[inline(always)] + pub fn tcc0_(&self) -> TCC0__R { + TCC0__R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - TCC1 APB Protect Enable"] + #[inline(always)] + pub fn tcc1_(&self) -> TCC1__R { + TCC1__R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - TCC2 APB Protect Enable"] + #[inline(always)] + pub fn tcc2_(&self) -> TCC2__R { + TCC2__R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - TC0 APB Protect Enable"] + #[inline(always)] + pub fn tc0_(&self) -> TC0__R { + TC0__R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - TC1 APB Protect Enable"] + #[inline(always)] + pub fn tc1_(&self) -> TC1__R { + TC1__R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - TC2 APB Protect Enable"] + #[inline(always)] + pub fn tc2_(&self) -> TC2__R { + TC2__R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - TC3 APB Protect Enable"] + #[inline(always)] + pub fn tc3_(&self) -> TC3__R { + TC3__R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - TC4 APB Protect Enable"] + #[inline(always)] + pub fn tc4_(&self) -> TC4__R { + TC4__R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - ADC0 APB Protect Enable"] + #[inline(always)] + pub fn adc0_(&self) -> ADC0__R { + ADC0__R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 20 - AC APB Protect Enable"] + #[inline(always)] + pub fn ac_(&self) -> AC__R { + AC__R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 22 - PTC APB Protect Enable"] + #[inline(always)] + pub fn ptc_(&self) -> PTC__R { + PTC__R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - CCL APB Protect Enable"] + #[inline(always)] + pub fn ccl_(&self) -> CCL__R { + CCL__R::new(((self.bits >> 23) & 0x01) != 0) + } +} +#[doc = "Peripheral write protection status - Bridge C\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [statusc](index.html) module"] +pub struct STATUSC_SPEC; +impl crate::RegisterSpec for STATUSC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [statusc::R](R) reader structure"] +impl crate::Readable for STATUSC_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUSC to value 0x0200_0000"] +impl crate::Resettable for STATUSC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0200_0000 + } +} diff --git a/pac/atsamc20j/src/pac/wrctrl.rs b/pac/atsamc20j/src/pac/wrctrl.rs new file mode 100644 index 000000000000..65773ea08d64 --- /dev/null +++ b/pac/atsamc20j/src/pac/wrctrl.rs @@ -0,0 +1,215 @@ +#[doc = "Register `WRCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WRCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PERID` reader - Peripheral identifier"] +pub struct PERID_R(crate::FieldReader); +impl PERID_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + PERID_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERID_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERID` writer - Peripheral identifier"] +pub struct PERID_W<'a> { + w: &'a mut W, +} +impl<'a> PERID_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +#[doc = "Peripheral access control key\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum KEY_A { + #[doc = "0: No action"] + OFF = 0, + #[doc = "1: Clear protection"] + CLR = 1, + #[doc = "2: Set protection"] + SET = 2, + #[doc = "3: Set and lock protection"] + SETLCK = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: KEY_A) -> Self { + variant as _ + } +} +#[doc = "Field `KEY` reader - Peripheral access control key"] +pub struct KEY_R(crate::FieldReader); +impl KEY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + KEY_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(KEY_A::OFF), + 1 => Some(KEY_A::CLR), + 2 => Some(KEY_A::SET), + 3 => Some(KEY_A::SETLCK), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == KEY_A::OFF + } + #[doc = "Checks if the value of the field is `CLR`"] + #[inline(always)] + pub fn is_clr(&self) -> bool { + **self == KEY_A::CLR + } + #[doc = "Checks if the value of the field is `SET`"] + #[inline(always)] + pub fn is_set(&self) -> bool { + **self == KEY_A::SET + } + #[doc = "Checks if the value of the field is `SETLCK`"] + #[inline(always)] + pub fn is_setlck(&self) -> bool { + **self == KEY_A::SETLCK + } +} +impl core::ops::Deref for KEY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `KEY` writer - Peripheral access control key"] +pub struct KEY_W<'a> { + w: &'a mut W, +} +impl<'a> KEY_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: KEY_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(KEY_A::OFF) + } + #[doc = "Clear protection"] + #[inline(always)] + pub fn clr(self) -> &'a mut W { + self.variant(KEY_A::CLR) + } + #[doc = "Set protection"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(KEY_A::SET) + } + #[doc = "Set and lock protection"] + #[inline(always)] + pub fn setlck(self) -> &'a mut W { + self.variant(KEY_A::SETLCK) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Peripheral identifier"] + #[inline(always)] + pub fn perid(&self) -> PERID_R { + PERID_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:23 - Peripheral access control key"] + #[inline(always)] + pub fn key(&self) -> KEY_R { + KEY_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:15 - Peripheral identifier"] + #[inline(always)] + pub fn perid(&mut self) -> PERID_W { + PERID_W { w: self } + } + #[doc = "Bits 16:23 - Peripheral access control key"] + #[inline(always)] + pub fn key(&mut self) -> KEY_W { + KEY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Write control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wrctrl](index.html) module"] +pub struct WRCTRL_SPEC; +impl crate::RegisterSpec for WRCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [wrctrl::R](R) reader structure"] +impl crate::Readable for WRCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wrctrl::W](W) writer structure"] +impl crate::Writable for WRCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WRCTRL to value 0"] +impl crate::Resettable for WRCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/pm.rs b/pac/atsamc20j/src/pm.rs new file mode 100644 index 000000000000..9da2b0e13288 --- /dev/null +++ b/pac/atsamc20j/src/pm.rs @@ -0,0 +1,18 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved0: [u8; 0x01], + #[doc = "0x01 - Sleep Configuration"] + pub sleepcfg: crate::Reg, + _reserved1: [u8; 0x06], + #[doc = "0x08 - Standby Configuration"] + pub stdbycfg: crate::Reg, +} +#[doc = "SLEEPCFG register accessor: an alias for `Reg`"] +pub type SLEEPCFG = crate::Reg; +#[doc = "Sleep Configuration"] +pub mod sleepcfg; +#[doc = "STDBYCFG register accessor: an alias for `Reg`"] +pub type STDBYCFG = crate::Reg; +#[doc = "Standby Configuration"] +pub mod stdbycfg; diff --git a/pac/atsamc20j/src/pm/sleepcfg.rs b/pac/atsamc20j/src/pm/sleepcfg.rs new file mode 100644 index 000000000000..ef643311a059 --- /dev/null +++ b/pac/atsamc20j/src/pm/sleepcfg.rs @@ -0,0 +1,178 @@ +#[doc = "Register `SLEEPCFG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SLEEPCFG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Sleep Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SLEEPMODE_A { + #[doc = "0: CPU clock is OFF"] + IDLE0 = 0, + #[doc = "1: AHB clock is OFF"] + IDLE1 = 1, + #[doc = "2: APB clock are OFF"] + IDLE2 = 2, + #[doc = "4: All Clocks are OFF"] + STANDBY = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SLEEPMODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `SLEEPMODE` reader - Sleep Mode"] +pub struct SLEEPMODE_R(crate::FieldReader); +impl SLEEPMODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SLEEPMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SLEEPMODE_A::IDLE0), + 1 => Some(SLEEPMODE_A::IDLE1), + 2 => Some(SLEEPMODE_A::IDLE2), + 4 => Some(SLEEPMODE_A::STANDBY), + _ => None, + } + } + #[doc = "Checks if the value of the field is `IDLE0`"] + #[inline(always)] + pub fn is_idle0(&self) -> bool { + **self == SLEEPMODE_A::IDLE0 + } + #[doc = "Checks if the value of the field is `IDLE1`"] + #[inline(always)] + pub fn is_idle1(&self) -> bool { + **self == SLEEPMODE_A::IDLE1 + } + #[doc = "Checks if the value of the field is `IDLE2`"] + #[inline(always)] + pub fn is_idle2(&self) -> bool { + **self == SLEEPMODE_A::IDLE2 + } + #[doc = "Checks if the value of the field is `STANDBY`"] + #[inline(always)] + pub fn is_standby(&self) -> bool { + **self == SLEEPMODE_A::STANDBY + } +} +impl core::ops::Deref for SLEEPMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLEEPMODE` writer - Sleep Mode"] +pub struct SLEEPMODE_W<'a> { + w: &'a mut W, +} +impl<'a> SLEEPMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SLEEPMODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "CPU clock is OFF"] + #[inline(always)] + pub fn idle0(self) -> &'a mut W { + self.variant(SLEEPMODE_A::IDLE0) + } + #[doc = "AHB clock is OFF"] + #[inline(always)] + pub fn idle1(self) -> &'a mut W { + self.variant(SLEEPMODE_A::IDLE1) + } + #[doc = "APB clock are OFF"] + #[inline(always)] + pub fn idle2(self) -> &'a mut W { + self.variant(SLEEPMODE_A::IDLE2) + } + #[doc = "All Clocks are OFF"] + #[inline(always)] + pub fn standby(self) -> &'a mut W { + self.variant(SLEEPMODE_A::STANDBY) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Sleep Mode"] + #[inline(always)] + pub fn sleepmode(&self) -> SLEEPMODE_R { + SLEEPMODE_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Sleep Mode"] + #[inline(always)] + pub fn sleepmode(&mut self) -> SLEEPMODE_W { + SLEEPMODE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Sleep Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sleepcfg](index.html) module"] +pub struct SLEEPCFG_SPEC; +impl crate::RegisterSpec for SLEEPCFG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [sleepcfg::R](R) reader structure"] +impl crate::Readable for SLEEPCFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [sleepcfg::W](W) writer structure"] +impl crate::Writable for SLEEPCFG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SLEEPCFG to value 0"] +impl crate::Resettable for SLEEPCFG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/pm/stdbycfg.rs b/pac/atsamc20j/src/pm/stdbycfg.rs new file mode 100644 index 000000000000..9780f2b001f5 --- /dev/null +++ b/pac/atsamc20j/src/pm/stdbycfg.rs @@ -0,0 +1,212 @@ +#[doc = "Register `STDBYCFG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STDBYCFG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Voltage Regulator Standby mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum VREGSMOD_A { + #[doc = "0: Automatic mode"] + AUTO = 0, + #[doc = "1: Performance oriented"] + PERFORMANCE = 1, + #[doc = "2: Low Power oriented"] + LP = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: VREGSMOD_A) -> Self { + variant as _ + } +} +#[doc = "Field `VREGSMOD` reader - Voltage Regulator Standby mode"] +pub struct VREGSMOD_R(crate::FieldReader); +impl VREGSMOD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + VREGSMOD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(VREGSMOD_A::AUTO), + 1 => Some(VREGSMOD_A::PERFORMANCE), + 2 => Some(VREGSMOD_A::LP), + _ => None, + } + } + #[doc = "Checks if the value of the field is `AUTO`"] + #[inline(always)] + pub fn is_auto(&self) -> bool { + **self == VREGSMOD_A::AUTO + } + #[doc = "Checks if the value of the field is `PERFORMANCE`"] + #[inline(always)] + pub fn is_performance(&self) -> bool { + **self == VREGSMOD_A::PERFORMANCE + } + #[doc = "Checks if the value of the field is `LP`"] + #[inline(always)] + pub fn is_lp(&self) -> bool { + **self == VREGSMOD_A::LP + } +} +impl core::ops::Deref for VREGSMOD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VREGSMOD` writer - Voltage Regulator Standby mode"] +pub struct VREGSMOD_W<'a> { + w: &'a mut W, +} +impl<'a> VREGSMOD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: VREGSMOD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Automatic mode"] + #[inline(always)] + pub fn auto(self) -> &'a mut W { + self.variant(VREGSMOD_A::AUTO) + } + #[doc = "Performance oriented"] + #[inline(always)] + pub fn performance(self) -> &'a mut W { + self.variant(VREGSMOD_A::PERFORMANCE) + } + #[doc = "Low Power oriented"] + #[inline(always)] + pub fn lp(self) -> &'a mut W { + self.variant(VREGSMOD_A::LP) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 6)) | ((value as u16 & 0x03) << 6); + self.w + } +} +#[doc = "Field `BBIASHS` reader - Back Bias for HMCRAMCHS"] +pub struct BBIASHS_R(crate::FieldReader); +impl BBIASHS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BBIASHS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BBIASHS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BBIASHS` writer - Back Bias for HMCRAMCHS"] +pub struct BBIASHS_W<'a> { + w: &'a mut W, +} +impl<'a> BBIASHS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u16 & 0x01) << 10); + self.w + } +} +impl R { + #[doc = "Bits 6:7 - Voltage Regulator Standby mode"] + #[inline(always)] + pub fn vregsmod(&self) -> VREGSMOD_R { + VREGSMOD_R::new(((self.bits >> 6) & 0x03) as u8) + } + #[doc = "Bit 10 - Back Bias for HMCRAMCHS"] + #[inline(always)] + pub fn bbiashs(&self) -> BBIASHS_R { + BBIASHS_R::new(((self.bits >> 10) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 6:7 - Voltage Regulator Standby mode"] + #[inline(always)] + pub fn vregsmod(&mut self) -> VREGSMOD_W { + VREGSMOD_W { w: self } + } + #[doc = "Bit 10 - Back Bias for HMCRAMCHS"] + #[inline(always)] + pub fn bbiashs(&mut self) -> BBIASHS_W { + BBIASHS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Standby Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [stdbycfg](index.html) module"] +pub struct STDBYCFG_SPEC; +impl crate::RegisterSpec for STDBYCFG_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [stdbycfg::R](R) reader structure"] +impl crate::Readable for STDBYCFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [stdbycfg::W](W) writer structure"] +impl crate::Writable for STDBYCFG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STDBYCFG to value 0x0400"] +impl crate::Resettable for STDBYCFG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0400 + } +} diff --git a/pac/atsamc20j/src/port.rs b/pac/atsamc20j/src/port.rs new file mode 100644 index 000000000000..08c16491ba07 --- /dev/null +++ b/pac/atsamc20j/src/port.rs @@ -0,0 +1,44 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00..0x60 - GROUP\\[%s\\]"] + pub group0: GROUP, + _reserved1: [u8; 0x20], + #[doc = "0x80..0xe0 - GROUP\\[%s\\]"] + pub group1: GROUP, +} +#[doc = r"Register block"] +#[repr(C)] +pub struct GROUP { + #[doc = "0x00 - Data Direction"] + pub dir: crate::Reg, + #[doc = "0x04 - Data Direction Clear"] + pub dirclr: crate::Reg, + #[doc = "0x08 - Data Direction Set"] + pub dirset: crate::Reg, + #[doc = "0x0c - Data Direction Toggle"] + pub dirtgl: crate::Reg, + #[doc = "0x10 - Data Output Value"] + pub out: crate::Reg, + #[doc = "0x14 - Data Output Value Clear"] + pub outclr: crate::Reg, + #[doc = "0x18 - Data Output Value Set"] + pub outset: crate::Reg, + #[doc = "0x1c - Data Output Value Toggle"] + pub outtgl: crate::Reg, + #[doc = "0x20 - Data Input Value"] + pub in_: crate::Reg, + #[doc = "0x24 - Control"] + pub ctrl: crate::Reg, + #[doc = "0x28 - Write Configuration"] + pub wrconfig: crate::Reg, + #[doc = "0x2c - Event Input Control"] + pub evctrl: crate::Reg, + #[doc = "0x30..0x40 - Peripheral Multiplexing n"] + pub pmux: [crate::Reg; 16], + #[doc = "0x40..0x60 - Pin Configuration n"] + pub pincfg: [crate::Reg; 32], +} +#[doc = r"Register block"] +#[doc = "GROUP\\[%s\\]"] +pub mod group; diff --git a/pac/atsamc20j/src/port/group.rs b/pac/atsamc20j/src/port/group.rs new file mode 100644 index 000000000000..d1aabcd73380 --- /dev/null +++ b/pac/atsamc20j/src/port/group.rs @@ -0,0 +1,56 @@ +#[doc = "DIR register accessor: an alias for `Reg`"] +pub type DIR = crate::Reg; +#[doc = "Data Direction"] +pub mod dir; +#[doc = "DIRCLR register accessor: an alias for `Reg`"] +pub type DIRCLR = crate::Reg; +#[doc = "Data Direction Clear"] +pub mod dirclr; +#[doc = "DIRSET register accessor: an alias for `Reg`"] +pub type DIRSET = crate::Reg; +#[doc = "Data Direction Set"] +pub mod dirset; +#[doc = "DIRTGL register accessor: an alias for `Reg`"] +pub type DIRTGL = crate::Reg; +#[doc = "Data Direction Toggle"] +pub mod dirtgl; +#[doc = "OUT register accessor: an alias for `Reg`"] +pub type OUT = crate::Reg; +#[doc = "Data Output Value"] +pub mod out; +#[doc = "OUTCLR register accessor: an alias for `Reg`"] +pub type OUTCLR = crate::Reg; +#[doc = "Data Output Value Clear"] +pub mod outclr; +#[doc = "OUTSET register accessor: an alias for `Reg`"] +pub type OUTSET = crate::Reg; +#[doc = "Data Output Value Set"] +pub mod outset; +#[doc = "OUTTGL register accessor: an alias for `Reg`"] +pub type OUTTGL = crate::Reg; +#[doc = "Data Output Value Toggle"] +pub mod outtgl; +#[doc = "IN register accessor: an alias for `Reg`"] +pub type IN = crate::Reg; +#[doc = "Data Input Value"] +pub mod in_; +#[doc = "CTRL register accessor: an alias for `Reg`"] +pub type CTRL = crate::Reg; +#[doc = "Control"] +pub mod ctrl; +#[doc = "WRCONFIG register accessor: an alias for `Reg`"] +pub type WRCONFIG = crate::Reg; +#[doc = "Write Configuration"] +pub mod wrconfig; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Input Control"] +pub mod evctrl; +#[doc = "PMUX register accessor: an alias for `Reg`"] +pub type PMUX = crate::Reg; +#[doc = "Peripheral Multiplexing n"] +pub mod pmux; +#[doc = "PINCFG register accessor: an alias for `Reg`"] +pub type PINCFG = crate::Reg; +#[doc = "Pin Configuration n"] +pub mod pincfg; diff --git a/pac/atsamc20j/src/port/group/ctrl.rs b/pac/atsamc20j/src/port/group/ctrl.rs new file mode 100644 index 000000000000..4b57cd6fcd2b --- /dev/null +++ b/pac/atsamc20j/src/port/group/ctrl.rs @@ -0,0 +1,103 @@ +#[doc = "Register `CTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SAMPLING` reader - Input Sampling Mode"] +pub struct SAMPLING_R(crate::FieldReader); +impl SAMPLING_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + SAMPLING_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SAMPLING_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SAMPLING` writer - Input Sampling Mode"] +pub struct SAMPLING_W<'a> { + w: &'a mut W, +} +impl<'a> SAMPLING_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Input Sampling Mode"] + #[inline(always)] + pub fn sampling(&self) -> SAMPLING_R { + SAMPLING_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Input Sampling Mode"] + #[inline(always)] + pub fn sampling(&mut self) -> SAMPLING_W { + SAMPLING_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"] +pub struct CTRL_SPEC; +impl crate::RegisterSpec for CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrl::R](R) reader structure"] +impl crate::Readable for CTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"] +impl crate::Writable for CTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/port/group/dir.rs b/pac/atsamc20j/src/port/group/dir.rs new file mode 100644 index 000000000000..e04452fb5d35 --- /dev/null +++ b/pac/atsamc20j/src/port/group/dir.rs @@ -0,0 +1,64 @@ +#[doc = "Register `DIR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Direction\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dir](index.html) module"] +pub struct DIR_SPEC; +impl crate::RegisterSpec for DIR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dir::R](R) reader structure"] +impl crate::Readable for DIR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dir::W](W) writer structure"] +impl crate::Writable for DIR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DIR to value 0"] +impl crate::Resettable for DIR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/port/group/dirclr.rs b/pac/atsamc20j/src/port/group/dirclr.rs new file mode 100644 index 000000000000..5e6d73d032b2 --- /dev/null +++ b/pac/atsamc20j/src/port/group/dirclr.rs @@ -0,0 +1,64 @@ +#[doc = "Register `DIRCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIRCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Direction Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dirclr](index.html) module"] +pub struct DIRCLR_SPEC; +impl crate::RegisterSpec for DIRCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dirclr::R](R) reader structure"] +impl crate::Readable for DIRCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dirclr::W](W) writer structure"] +impl crate::Writable for DIRCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DIRCLR to value 0"] +impl crate::Resettable for DIRCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/port/group/dirset.rs b/pac/atsamc20j/src/port/group/dirset.rs new file mode 100644 index 000000000000..eaa86e14f15d --- /dev/null +++ b/pac/atsamc20j/src/port/group/dirset.rs @@ -0,0 +1,64 @@ +#[doc = "Register `DIRSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIRSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Direction Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dirset](index.html) module"] +pub struct DIRSET_SPEC; +impl crate::RegisterSpec for DIRSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dirset::R](R) reader structure"] +impl crate::Readable for DIRSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dirset::W](W) writer structure"] +impl crate::Writable for DIRSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DIRSET to value 0"] +impl crate::Resettable for DIRSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/port/group/dirtgl.rs b/pac/atsamc20j/src/port/group/dirtgl.rs new file mode 100644 index 000000000000..fbd021438b1b --- /dev/null +++ b/pac/atsamc20j/src/port/group/dirtgl.rs @@ -0,0 +1,64 @@ +#[doc = "Register `DIRTGL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIRTGL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Direction Toggle\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dirtgl](index.html) module"] +pub struct DIRTGL_SPEC; +impl crate::RegisterSpec for DIRTGL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dirtgl::R](R) reader structure"] +impl crate::Readable for DIRTGL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dirtgl::W](W) writer structure"] +impl crate::Writable for DIRTGL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DIRTGL to value 0"] +impl crate::Resettable for DIRTGL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/port/group/evctrl.rs b/pac/atsamc20j/src/port/group/evctrl.rs new file mode 100644 index 000000000000..ef0a35987f3d --- /dev/null +++ b/pac/atsamc20j/src/port/group/evctrl.rs @@ -0,0 +1,625 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PID0` reader - Port Event Pin Identifier 0"] +pub struct PID0_R(crate::FieldReader); +impl PID0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PID0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PID0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PID0` writer - Port Event Pin Identifier 0"] +pub struct PID0_W<'a> { + w: &'a mut W, +} +impl<'a> PID0_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f); + self.w + } +} +#[doc = "Port Event Action 0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EVACT0_A { + #[doc = "0: Event output to pin"] + OUT = 0, + #[doc = "1: Set output register of pin on event"] + SET = 1, + #[doc = "2: Clear output register of pin on event"] + CLR = 2, + #[doc = "3: Toggle output register of pin on event"] + TGL = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EVACT0_A) -> Self { + variant as _ + } +} +#[doc = "Field `EVACT0` reader - Port Event Action 0"] +pub struct EVACT0_R(crate::FieldReader); +impl EVACT0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVACT0_A { + match self.bits { + 0 => EVACT0_A::OUT, + 1 => EVACT0_A::SET, + 2 => EVACT0_A::CLR, + 3 => EVACT0_A::TGL, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `OUT`"] + #[inline(always)] + pub fn is_out(&self) -> bool { + **self == EVACT0_A::OUT + } + #[doc = "Checks if the value of the field is `SET`"] + #[inline(always)] + pub fn is_set(&self) -> bool { + **self == EVACT0_A::SET + } + #[doc = "Checks if the value of the field is `CLR`"] + #[inline(always)] + pub fn is_clr(&self) -> bool { + **self == EVACT0_A::CLR + } + #[doc = "Checks if the value of the field is `TGL`"] + #[inline(always)] + pub fn is_tgl(&self) -> bool { + **self == EVACT0_A::TGL + } +} +impl core::ops::Deref for EVACT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT0` writer - Port Event Action 0"] +pub struct EVACT0_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT0_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EVACT0_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Event output to pin"] + #[inline(always)] + pub fn out(self) -> &'a mut W { + self.variant(EVACT0_A::OUT) + } + #[doc = "Set output register of pin on event"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(EVACT0_A::SET) + } + #[doc = "Clear output register of pin on event"] + #[inline(always)] + pub fn clr(self) -> &'a mut W { + self.variant(EVACT0_A::CLR) + } + #[doc = "Toggle output register of pin on event"] + #[inline(always)] + pub fn tgl(self) -> &'a mut W { + self.variant(EVACT0_A::TGL) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 5)) | ((value as u32 & 0x03) << 5); + self.w + } +} +#[doc = "Field `PORTEI0` reader - Port Event Enable Input 0"] +pub struct PORTEI0_R(crate::FieldReader); +impl PORTEI0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PORTEI0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PORTEI0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PORTEI0` writer - Port Event Enable Input 0"] +pub struct PORTEI0_W<'a> { + w: &'a mut W, +} +impl<'a> PORTEI0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `PID1` reader - Port Event Pin Identifier 1"] +pub struct PID1_R(crate::FieldReader); +impl PID1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PID1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PID1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PID1` writer - Port Event Pin Identifier 1"] +pub struct PID1_W<'a> { + w: &'a mut W, +} +impl<'a> PID1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 8)) | ((value as u32 & 0x1f) << 8); + self.w + } +} +#[doc = "Field `EVACT1` reader - Port Event Action 1"] +pub struct EVACT1_R(crate::FieldReader); +impl EVACT1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVACT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT1` writer - Port Event Action 1"] +pub struct EVACT1_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 13)) | ((value as u32 & 0x03) << 13); + self.w + } +} +#[doc = "Field `PORTEI1` reader - Port Event Enable Input 1"] +pub struct PORTEI1_R(crate::FieldReader); +impl PORTEI1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PORTEI1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PORTEI1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PORTEI1` writer - Port Event Enable Input 1"] +pub struct PORTEI1_W<'a> { + w: &'a mut W, +} +impl<'a> PORTEI1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `PID2` reader - Port Event Pin Identifier 2"] +pub struct PID2_R(crate::FieldReader); +impl PID2_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PID2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PID2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PID2` writer - Port Event Pin Identifier 2"] +pub struct PID2_W<'a> { + w: &'a mut W, +} +impl<'a> PID2_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 16)) | ((value as u32 & 0x1f) << 16); + self.w + } +} +#[doc = "Field `EVACT2` reader - Port Event Action 2"] +pub struct EVACT2_R(crate::FieldReader); +impl EVACT2_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVACT2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT2` writer - Port Event Action 2"] +pub struct EVACT2_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT2_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 21)) | ((value as u32 & 0x03) << 21); + self.w + } +} +#[doc = "Field `PORTEI2` reader - Port Event Enable Input 2"] +pub struct PORTEI2_R(crate::FieldReader); +impl PORTEI2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PORTEI2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PORTEI2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PORTEI2` writer - Port Event Enable Input 2"] +pub struct PORTEI2_W<'a> { + w: &'a mut W, +} +impl<'a> PORTEI2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `PID3` reader - Port Event Pin Identifier 3"] +pub struct PID3_R(crate::FieldReader); +impl PID3_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PID3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PID3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PID3` writer - Port Event Pin Identifier 3"] +pub struct PID3_W<'a> { + w: &'a mut W, +} +impl<'a> PID3_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 24)) | ((value as u32 & 0x1f) << 24); + self.w + } +} +#[doc = "Field `EVACT3` reader - Port Event Action 3"] +pub struct EVACT3_R(crate::FieldReader); +impl EVACT3_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVACT3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT3` writer - Port Event Action 3"] +pub struct EVACT3_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT3_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 29)) | ((value as u32 & 0x03) << 29); + self.w + } +} +#[doc = "Field `PORTEI3` reader - Port Event Enable Input 3"] +pub struct PORTEI3_R(crate::FieldReader); +impl PORTEI3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PORTEI3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PORTEI3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PORTEI3` writer - Port Event Enable Input 3"] +pub struct PORTEI3_W<'a> { + w: &'a mut W, +} +impl<'a> PORTEI3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Port Event Pin Identifier 0"] + #[inline(always)] + pub fn pid0(&self) -> PID0_R { + PID0_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:6 - Port Event Action 0"] + #[inline(always)] + pub fn evact0(&self) -> EVACT0_R { + EVACT0_R::new(((self.bits >> 5) & 0x03) as u8) + } + #[doc = "Bit 7 - Port Event Enable Input 0"] + #[inline(always)] + pub fn portei0(&self) -> PORTEI0_R { + PORTEI0_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:12 - Port Event Pin Identifier 1"] + #[inline(always)] + pub fn pid1(&self) -> PID1_R { + PID1_R::new(((self.bits >> 8) & 0x1f) as u8) + } + #[doc = "Bits 13:14 - Port Event Action 1"] + #[inline(always)] + pub fn evact1(&self) -> EVACT1_R { + EVACT1_R::new(((self.bits >> 13) & 0x03) as u8) + } + #[doc = "Bit 15 - Port Event Enable Input 1"] + #[inline(always)] + pub fn portei1(&self) -> PORTEI1_R { + PORTEI1_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:20 - Port Event Pin Identifier 2"] + #[inline(always)] + pub fn pid2(&self) -> PID2_R { + PID2_R::new(((self.bits >> 16) & 0x1f) as u8) + } + #[doc = "Bits 21:22 - Port Event Action 2"] + #[inline(always)] + pub fn evact2(&self) -> EVACT2_R { + EVACT2_R::new(((self.bits >> 21) & 0x03) as u8) + } + #[doc = "Bit 23 - Port Event Enable Input 2"] + #[inline(always)] + pub fn portei2(&self) -> PORTEI2_R { + PORTEI2_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bits 24:28 - Port Event Pin Identifier 3"] + #[inline(always)] + pub fn pid3(&self) -> PID3_R { + PID3_R::new(((self.bits >> 24) & 0x1f) as u8) + } + #[doc = "Bits 29:30 - Port Event Action 3"] + #[inline(always)] + pub fn evact3(&self) -> EVACT3_R { + EVACT3_R::new(((self.bits >> 29) & 0x03) as u8) + } + #[doc = "Bit 31 - Port Event Enable Input 3"] + #[inline(always)] + pub fn portei3(&self) -> PORTEI3_R { + PORTEI3_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Port Event Pin Identifier 0"] + #[inline(always)] + pub fn pid0(&mut self) -> PID0_W { + PID0_W { w: self } + } + #[doc = "Bits 5:6 - Port Event Action 0"] + #[inline(always)] + pub fn evact0(&mut self) -> EVACT0_W { + EVACT0_W { w: self } + } + #[doc = "Bit 7 - Port Event Enable Input 0"] + #[inline(always)] + pub fn portei0(&mut self) -> PORTEI0_W { + PORTEI0_W { w: self } + } + #[doc = "Bits 8:12 - Port Event Pin Identifier 1"] + #[inline(always)] + pub fn pid1(&mut self) -> PID1_W { + PID1_W { w: self } + } + #[doc = "Bits 13:14 - Port Event Action 1"] + #[inline(always)] + pub fn evact1(&mut self) -> EVACT1_W { + EVACT1_W { w: self } + } + #[doc = "Bit 15 - Port Event Enable Input 1"] + #[inline(always)] + pub fn portei1(&mut self) -> PORTEI1_W { + PORTEI1_W { w: self } + } + #[doc = "Bits 16:20 - Port Event Pin Identifier 2"] + #[inline(always)] + pub fn pid2(&mut self) -> PID2_W { + PID2_W { w: self } + } + #[doc = "Bits 21:22 - Port Event Action 2"] + #[inline(always)] + pub fn evact2(&mut self) -> EVACT2_W { + EVACT2_W { w: self } + } + #[doc = "Bit 23 - Port Event Enable Input 2"] + #[inline(always)] + pub fn portei2(&mut self) -> PORTEI2_W { + PORTEI2_W { w: self } + } + #[doc = "Bits 24:28 - Port Event Pin Identifier 3"] + #[inline(always)] + pub fn pid3(&mut self) -> PID3_W { + PID3_W { w: self } + } + #[doc = "Bits 29:30 - Port Event Action 3"] + #[inline(always)] + pub fn evact3(&mut self) -> EVACT3_W { + EVACT3_W { w: self } + } + #[doc = "Bit 31 - Port Event Enable Input 3"] + #[inline(always)] + pub fn portei3(&mut self) -> PORTEI3_W { + PORTEI3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Input Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/port/group/in_.rs b/pac/atsamc20j/src/port/group/in_.rs new file mode 100644 index 000000000000..1c8e7396a83e --- /dev/null +++ b/pac/atsamc20j/src/port/group/in_.rs @@ -0,0 +1,31 @@ +#[doc = "Register `IN` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Data Input Value\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [in_](index.html) module"] +pub struct IN_SPEC; +impl crate::RegisterSpec for IN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [in_::R](R) reader structure"] +impl crate::Readable for IN_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets IN to value 0"] +impl crate::Resettable for IN_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/port/group/out.rs b/pac/atsamc20j/src/port/group/out.rs new file mode 100644 index 000000000000..092e8dbd8023 --- /dev/null +++ b/pac/atsamc20j/src/port/group/out.rs @@ -0,0 +1,64 @@ +#[doc = "Register `OUT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OUT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Output Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [out](index.html) module"] +pub struct OUT_SPEC; +impl crate::RegisterSpec for OUT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [out::R](R) reader structure"] +impl crate::Readable for OUT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [out::W](W) writer structure"] +impl crate::Writable for OUT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OUT to value 0"] +impl crate::Resettable for OUT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/port/group/outclr.rs b/pac/atsamc20j/src/port/group/outclr.rs new file mode 100644 index 000000000000..6e734396601f --- /dev/null +++ b/pac/atsamc20j/src/port/group/outclr.rs @@ -0,0 +1,64 @@ +#[doc = "Register `OUTCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OUTCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Output Value Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [outclr](index.html) module"] +pub struct OUTCLR_SPEC; +impl crate::RegisterSpec for OUTCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [outclr::R](R) reader structure"] +impl crate::Readable for OUTCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [outclr::W](W) writer structure"] +impl crate::Writable for OUTCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OUTCLR to value 0"] +impl crate::Resettable for OUTCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/port/group/outset.rs b/pac/atsamc20j/src/port/group/outset.rs new file mode 100644 index 000000000000..6d39122deb4b --- /dev/null +++ b/pac/atsamc20j/src/port/group/outset.rs @@ -0,0 +1,64 @@ +#[doc = "Register `OUTSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OUTSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Output Value Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [outset](index.html) module"] +pub struct OUTSET_SPEC; +impl crate::RegisterSpec for OUTSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [outset::R](R) reader structure"] +impl crate::Readable for OUTSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [outset::W](W) writer structure"] +impl crate::Writable for OUTSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OUTSET to value 0"] +impl crate::Resettable for OUTSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/port/group/outtgl.rs b/pac/atsamc20j/src/port/group/outtgl.rs new file mode 100644 index 000000000000..0f3d87d6476d --- /dev/null +++ b/pac/atsamc20j/src/port/group/outtgl.rs @@ -0,0 +1,64 @@ +#[doc = "Register `OUTTGL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OUTTGL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Output Value Toggle\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [outtgl](index.html) module"] +pub struct OUTTGL_SPEC; +impl crate::RegisterSpec for OUTTGL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [outtgl::R](R) reader structure"] +impl crate::Readable for OUTTGL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [outtgl::W](W) writer structure"] +impl crate::Writable for OUTTGL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OUTTGL to value 0"] +impl crate::Resettable for OUTTGL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/port/group/pincfg.rs b/pac/atsamc20j/src/port/group/pincfg.rs new file mode 100644 index 000000000000..920af6550361 --- /dev/null +++ b/pac/atsamc20j/src/port/group/pincfg.rs @@ -0,0 +1,255 @@ +#[doc = "Register `PINCFG[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PINCFG[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PMUXEN` reader - Select Peripheral Multiplexer"] +pub struct PMUXEN_R(crate::FieldReader); +impl PMUXEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PMUXEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PMUXEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PMUXEN` writer - Select Peripheral Multiplexer"] +pub struct PMUXEN_W<'a> { + w: &'a mut W, +} +impl<'a> PMUXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `INEN` reader - Input Enable"] +pub struct INEN_R(crate::FieldReader); +impl INEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INEN` writer - Input Enable"] +pub struct INEN_W<'a> { + w: &'a mut W, +} +impl<'a> INEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PULLEN` reader - Pull Enable"] +pub struct PULLEN_R(crate::FieldReader); +impl PULLEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PULLEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PULLEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PULLEN` writer - Pull Enable"] +pub struct PULLEN_W<'a> { + w: &'a mut W, +} +impl<'a> PULLEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `DRVSTR` reader - Output Driver Strength Selection"] +pub struct DRVSTR_R(crate::FieldReader); +impl DRVSTR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRVSTR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRVSTR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRVSTR` writer - Output Driver Strength Selection"] +pub struct DRVSTR_W<'a> { + w: &'a mut W, +} +impl<'a> DRVSTR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - Select Peripheral Multiplexer"] + #[inline(always)] + pub fn pmuxen(&self) -> PMUXEN_R { + PMUXEN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Input Enable"] + #[inline(always)] + pub fn inen(&self) -> INEN_R { + INEN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Pull Enable"] + #[inline(always)] + pub fn pullen(&self) -> PULLEN_R { + PULLEN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 6 - Output Driver Strength Selection"] + #[inline(always)] + pub fn drvstr(&self) -> DRVSTR_R { + DRVSTR_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Select Peripheral Multiplexer"] + #[inline(always)] + pub fn pmuxen(&mut self) -> PMUXEN_W { + PMUXEN_W { w: self } + } + #[doc = "Bit 1 - Input Enable"] + #[inline(always)] + pub fn inen(&mut self) -> INEN_W { + INEN_W { w: self } + } + #[doc = "Bit 2 - Pull Enable"] + #[inline(always)] + pub fn pullen(&mut self) -> PULLEN_W { + PULLEN_W { w: self } + } + #[doc = "Bit 6 - Output Driver Strength Selection"] + #[inline(always)] + pub fn drvstr(&mut self) -> DRVSTR_W { + DRVSTR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Pin Configuration n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pincfg](index.html) module"] +pub struct PINCFG_SPEC; +impl crate::RegisterSpec for PINCFG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [pincfg::R](R) reader structure"] +impl crate::Readable for PINCFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [pincfg::W](W) writer structure"] +impl crate::Writable for PINCFG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PINCFG[%s] +to value 0"] +impl crate::Resettable for PINCFG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/port/group/pmux.rs b/pac/atsamc20j/src/port/group/pmux.rs new file mode 100644 index 000000000000..79c991a99daf --- /dev/null +++ b/pac/atsamc20j/src/port/group/pmux.rs @@ -0,0 +1,141 @@ +#[doc = "Register `PMUX[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PMUX[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PMUXE` reader - Peripheral Multiplexing for Even-Numbered Pin"] +pub struct PMUXE_R(crate::FieldReader); +impl PMUXE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PMUXE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PMUXE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PMUXE` writer - Peripheral Multiplexing for Even-Numbered Pin"] +pub struct PMUXE_W<'a> { + w: &'a mut W, +} +impl<'a> PMUXE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +#[doc = "Field `PMUXO` reader - Peripheral Multiplexing for Odd-Numbered Pin"] +pub struct PMUXO_R(crate::FieldReader); +impl PMUXO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PMUXO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PMUXO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PMUXO` writer - Peripheral Multiplexing for Odd-Numbered Pin"] +pub struct PMUXO_W<'a> { + w: &'a mut W, +} +impl<'a> PMUXO_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 4)) | ((value as u8 & 0x0f) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Peripheral Multiplexing for Even-Numbered Pin"] + #[inline(always)] + pub fn pmuxe(&self) -> PMUXE_R { + PMUXE_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Peripheral Multiplexing for Odd-Numbered Pin"] + #[inline(always)] + pub fn pmuxo(&self) -> PMUXO_R { + PMUXO_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Peripheral Multiplexing for Even-Numbered Pin"] + #[inline(always)] + pub fn pmuxe(&mut self) -> PMUXE_W { + PMUXE_W { w: self } + } + #[doc = "Bits 4:7 - Peripheral Multiplexing for Odd-Numbered Pin"] + #[inline(always)] + pub fn pmuxo(&mut self) -> PMUXO_W { + PMUXO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Peripheral Multiplexing n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pmux](index.html) module"] +pub struct PMUX_SPEC; +impl crate::RegisterSpec for PMUX_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [pmux::R](R) reader structure"] +impl crate::Readable for PMUX_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [pmux::W](W) writer structure"] +impl crate::Writable for PMUX_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PMUX[%s] +to value 0"] +impl crate::Resettable for PMUX_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/port/group/wrconfig.rs b/pac/atsamc20j/src/port/group/wrconfig.rs new file mode 100644 index 000000000000..c87e4f174728 --- /dev/null +++ b/pac/atsamc20j/src/port/group/wrconfig.rs @@ -0,0 +1,268 @@ +#[doc = "Register `WRCONFIG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PINMASK` writer - Pin Mask for Multiple Pin Configuration"] +pub struct PINMASK_W<'a> { + w: &'a mut W, +} +impl<'a> PINMASK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +#[doc = "Field `PMUXEN` writer - Select Peripheral Multiplexer"] +pub struct PMUXEN_W<'a> { + w: &'a mut W, +} +impl<'a> PMUXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `INEN` writer - Input Enable"] +pub struct INEN_W<'a> { + w: &'a mut W, +} +impl<'a> INEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `PULLEN` writer - Pull Enable"] +pub struct PULLEN_W<'a> { + w: &'a mut W, +} +impl<'a> PULLEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `DRVSTR` writer - Output Driver Strength Selection"] +pub struct DRVSTR_W<'a> { + w: &'a mut W, +} +impl<'a> DRVSTR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `PMUX` writer - Peripheral Multiplexing Template"] +pub struct PMUX_W<'a> { + w: &'a mut W, +} +impl<'a> PMUX_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Field `WRPMUX` writer - Write PMUX Registers"] +pub struct WRPMUX_W<'a> { + w: &'a mut W, +} +impl<'a> WRPMUX_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Field `WRPINCFG` writer - Write PINCFG Registers"] +pub struct WRPINCFG_W<'a> { + w: &'a mut W, +} +impl<'a> WRPINCFG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +#[doc = "Field `HWSEL` writer - Half-Word Select"] +pub struct HWSEL_W<'a> { + w: &'a mut W, +} +impl<'a> HWSEL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl W { + #[doc = "Bits 0:15 - Pin Mask for Multiple Pin Configuration"] + #[inline(always)] + pub fn pinmask(&mut self) -> PINMASK_W { + PINMASK_W { w: self } + } + #[doc = "Bit 16 - Select Peripheral Multiplexer"] + #[inline(always)] + pub fn pmuxen(&mut self) -> PMUXEN_W { + PMUXEN_W { w: self } + } + #[doc = "Bit 17 - Input Enable"] + #[inline(always)] + pub fn inen(&mut self) -> INEN_W { + INEN_W { w: self } + } + #[doc = "Bit 18 - Pull Enable"] + #[inline(always)] + pub fn pullen(&mut self) -> PULLEN_W { + PULLEN_W { w: self } + } + #[doc = "Bit 22 - Output Driver Strength Selection"] + #[inline(always)] + pub fn drvstr(&mut self) -> DRVSTR_W { + DRVSTR_W { w: self } + } + #[doc = "Bits 24:27 - Peripheral Multiplexing Template"] + #[inline(always)] + pub fn pmux(&mut self) -> PMUX_W { + PMUX_W { w: self } + } + #[doc = "Bit 28 - Write PMUX Registers"] + #[inline(always)] + pub fn wrpmux(&mut self) -> WRPMUX_W { + WRPMUX_W { w: self } + } + #[doc = "Bit 30 - Write PINCFG Registers"] + #[inline(always)] + pub fn wrpincfg(&mut self) -> WRPINCFG_W { + WRPINCFG_W { w: self } + } + #[doc = "Bit 31 - Half-Word Select"] + #[inline(always)] + pub fn hwsel(&mut self) -> HWSEL_W { + HWSEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Write Configuration\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wrconfig](index.html) module"] +pub struct WRCONFIG_SPEC; +impl crate::RegisterSpec for WRCONFIG_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [wrconfig::W](W) writer structure"] +impl crate::Writable for WRCONFIG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WRCONFIG to value 0"] +impl crate::Resettable for WRCONFIG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/rstc.rs b/pac/atsamc20j/src/rstc.rs new file mode 100644 index 000000000000..327b511df28a --- /dev/null +++ b/pac/atsamc20j/src/rstc.rs @@ -0,0 +1,10 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Reset Cause"] + pub rcause: crate::Reg, +} +#[doc = "RCAUSE register accessor: an alias for `Reg`"] +pub type RCAUSE = crate::Reg; +#[doc = "Reset Cause"] +pub mod rcause; diff --git a/pac/atsamc20j/src/rstc/rcause.rs b/pac/atsamc20j/src/rstc/rcause.rs new file mode 100644 index 000000000000..3dc13496e74b --- /dev/null +++ b/pac/atsamc20j/src/rstc/rcause.rs @@ -0,0 +1,153 @@ +#[doc = "Register `RCAUSE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `POR` reader - Power On Reset"] +pub struct POR_R(crate::FieldReader); +impl POR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + POR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for POR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODCORE` reader - Brown Out CORE Detector Reset"] +pub struct BODCORE_R(crate::FieldReader); +impl BODCORE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODCORE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODCORE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODVDD` reader - Brown Out VDD Detector Reset"] +pub struct BODVDD_R(crate::FieldReader); +impl BODVDD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODVDD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODVDD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXT` reader - External Reset"] +pub struct EXT_R(crate::FieldReader); +impl EXT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WDT` reader - Watchdog Reset"] +pub struct WDT_R(crate::FieldReader); +impl WDT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WDT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WDT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYST` reader - System Reset Request"] +pub struct SYST_R(crate::FieldReader); +impl SYST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Power On Reset"] + #[inline(always)] + pub fn por(&self) -> POR_R { + POR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Brown Out CORE Detector Reset"] + #[inline(always)] + pub fn bodcore(&self) -> BODCORE_R { + BODCORE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Brown Out VDD Detector Reset"] + #[inline(always)] + pub fn bodvdd(&self) -> BODVDD_R { + BODVDD_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 4 - External Reset"] + #[inline(always)] + pub fn ext(&self) -> EXT_R { + EXT_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Watchdog Reset"] + #[inline(always)] + pub fn wdt(&self) -> WDT_R { + WDT_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - System Reset Request"] + #[inline(always)] + pub fn syst(&self) -> SYST_R { + SYST_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +#[doc = "Reset Cause\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rcause](index.html) module"] +pub struct RCAUSE_SPEC; +impl crate::RegisterSpec for RCAUSE_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [rcause::R](R) reader structure"] +impl crate::Readable for RCAUSE_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets RCAUSE to value 0"] +impl crate::Resettable for RCAUSE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/rtc.rs b/pac/atsamc20j/src/rtc.rs new file mode 100644 index 000000000000..62f424cb1a8e --- /dev/null +++ b/pac/atsamc20j/src/rtc.rs @@ -0,0 +1,120 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved_0_mode0: [u8; 0x25], +} +impl RegisterBlock { + #[doc = "0x00..0x25 - Clock/Calendar with Alarm"] + #[inline(always)] + pub fn mode2(&self) -> &MODE2 { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const MODE2) } + } + #[doc = "0x00..0x24 - 16-bit Counter with Two 16-bit Compares"] + #[inline(always)] + pub fn mode1(&self) -> &MODE1 { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const MODE1) } + } + #[doc = "0x00..0x24 - 32-bit Counter with Single 32-bit Compare"] + #[inline(always)] + pub fn mode0(&self) -> &MODE0 { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const MODE0) } + } +} +#[doc = r"Register block"] +#[repr(C)] +pub struct MODE0 { + #[doc = "0x00 - MODE0 Control A"] + pub ctrla: crate::Reg, + _reserved1: [u8; 0x02], + #[doc = "0x04 - MODE0 Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x08 - MODE0 Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x0a - MODE0 Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x0c - MODE0 Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x0e - Debug Control"] + pub dbgctrl: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x10 - MODE0 Synchronization Busy Status"] + pub syncbusy: crate::Reg, + #[doc = "0x14 - Frequency Correction"] + pub freqcorr: crate::Reg, + _reserved8: [u8; 0x03], + #[doc = "0x18 - MODE0 Counter Value"] + pub count: crate::Reg, + _reserved9: [u8; 0x04], + #[doc = "0x20 - MODE0 Compare n Value"] + pub comp: crate::Reg, +} +#[doc = r"Register block"] +#[doc = "32-bit Counter with Single 32-bit Compare"] +pub mod mode0; +#[doc = r"Register block"] +#[repr(C)] +pub struct MODE1 { + #[doc = "0x00 - MODE1 Control A"] + pub ctrla: crate::Reg, + _reserved1: [u8; 0x02], + #[doc = "0x04 - MODE1 Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x08 - MODE1 Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x0a - MODE1 Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x0c - MODE1 Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x0e - Debug Control"] + pub dbgctrl: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x10 - MODE1 Synchronization Busy Status"] + pub syncbusy: crate::Reg, + #[doc = "0x14 - Frequency Correction"] + pub freqcorr: crate::Reg, + _reserved8: [u8; 0x03], + #[doc = "0x18 - MODE1 Counter Value"] + pub count: crate::Reg, + _reserved9: [u8; 0x02], + #[doc = "0x1c - MODE1 Counter Period"] + pub per: crate::Reg, + _reserved10: [u8; 0x02], + #[doc = "0x20 - MODE1 Compare n Value"] + pub comp: [crate::Reg; 2], +} +#[doc = r"Register block"] +#[doc = "16-bit Counter with Two 16-bit Compares"] +pub mod mode1; +#[doc = r"Register block"] +#[repr(C)] +pub struct MODE2 { + #[doc = "0x00 - MODE2 Control A"] + pub ctrla: crate::Reg, + _reserved1: [u8; 0x02], + #[doc = "0x04 - MODE2 Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x08 - MODE2 Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x0a - MODE2 Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x0c - MODE2 Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x0e - Debug Control"] + pub dbgctrl: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x10 - MODE2 Synchronization Busy Status"] + pub syncbusy: crate::Reg, + #[doc = "0x14 - Frequency Correction"] + pub freqcorr: crate::Reg, + _reserved8: [u8; 0x03], + #[doc = "0x18 - MODE2 Clock Value"] + pub clock: crate::Reg, + _reserved9: [u8; 0x04], + #[doc = "0x20 - MODE2_ALARM Alarm n Value"] + pub alarm: crate::Reg, + #[doc = "0x24 - MODE2_ALARM Alarm n Mask"] + pub mask: crate::Reg, +} +#[doc = r"Register block"] +#[doc = "Clock/Calendar with Alarm"] +pub mod mode2; diff --git a/pac/atsamc20j/src/rtc/mode0.rs b/pac/atsamc20j/src/rtc/mode0.rs new file mode 100644 index 000000000000..9ce5c3808169 --- /dev/null +++ b/pac/atsamc20j/src/rtc/mode0.rs @@ -0,0 +1,40 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "MODE0 Control A"] +pub mod ctrla; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "MODE0 Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "MODE0 Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "MODE0 Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "MODE0 Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "MODE0 Synchronization Busy Status"] +pub mod syncbusy; +#[doc = "FREQCORR register accessor: an alias for `Reg`"] +pub type FREQCORR = crate::Reg; +#[doc = "Frequency Correction"] +pub mod freqcorr; +#[doc = "COUNT register accessor: an alias for `Reg`"] +pub type COUNT = crate::Reg; +#[doc = "MODE0 Counter Value"] +pub mod count; +#[doc = "COMP register accessor: an alias for `Reg`"] +pub type COMP = crate::Reg; +#[doc = "MODE0 Compare n Value"] +pub mod comp; diff --git a/pac/atsamc20j/src/rtc/mode0/comp.rs b/pac/atsamc20j/src/rtc/mode0/comp.rs new file mode 100644 index 000000000000..a909d3cea2d3 --- /dev/null +++ b/pac/atsamc20j/src/rtc/mode0/comp.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COMP` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COMP` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COMP` reader - Compare Value"] +pub struct COMP_R(crate::FieldReader); +impl COMP_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COMP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP` writer - Compare Value"] +pub struct COMP_W<'a> { + w: &'a mut W, +} +impl<'a> COMP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Compare Value"] + #[inline(always)] + pub fn comp(&self) -> COMP_R { + COMP_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Compare Value"] + #[inline(always)] + pub fn comp(&mut self) -> COMP_W { + COMP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE0 Compare n Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [comp](index.html) module"] +pub struct COMP_SPEC; +impl crate::RegisterSpec for COMP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [comp::R](R) reader structure"] +impl crate::Readable for COMP_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [comp::W](W) writer structure"] +impl crate::Writable for COMP_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COMP to value 0"] +impl crate::Resettable for COMP_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/rtc/mode0/count.rs b/pac/atsamc20j/src/rtc/mode0/count.rs new file mode 100644 index 000000000000..cf880b5e77a6 --- /dev/null +++ b/pac/atsamc20j/src/rtc/mode0/count.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE0 Counter Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count](index.html) module"] +pub struct COUNT_SPEC; +impl crate::RegisterSpec for COUNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [count::R](R) reader structure"] +impl crate::Readable for COUNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count::W](W) writer structure"] +impl crate::Writable for COUNT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT to value 0"] +impl crate::Resettable for COUNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/rtc/mode0/ctrla.rs b/pac/atsamc20j/src/rtc/mode0/ctrla.rs new file mode 100644 index 000000000000..423877bd087d --- /dev/null +++ b/pac/atsamc20j/src/rtc/mode0/ctrla.rs @@ -0,0 +1,569 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: Mode 0: 32-bit Counter"] + COUNT32 = 0, + #[doc = "1: Mode 1: 16-bit Counter"] + COUNT16 = 1, + #[doc = "2: Mode 2: Clock/Calendar"] + CLOCK = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::COUNT32), + 1 => Some(MODE_A::COUNT16), + 2 => Some(MODE_A::CLOCK), + _ => None, + } + } + #[doc = "Checks if the value of the field is `COUNT32`"] + #[inline(always)] + pub fn is_count32(&self) -> bool { + **self == MODE_A::COUNT32 + } + #[doc = "Checks if the value of the field is `COUNT16`"] + #[inline(always)] + pub fn is_count16(&self) -> bool { + **self == MODE_A::COUNT16 + } + #[doc = "Checks if the value of the field is `CLOCK`"] + #[inline(always)] + pub fn is_clock(&self) -> bool { + **self == MODE_A::CLOCK + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Mode 0: 32-bit Counter"] + #[inline(always)] + pub fn count32(self) -> &'a mut W { + self.variant(MODE_A::COUNT32) + } + #[doc = "Mode 1: 16-bit Counter"] + #[inline(always)] + pub fn count16(self) -> &'a mut W { + self.variant(MODE_A::COUNT16) + } + #[doc = "Mode 2: Clock/Calendar"] + #[inline(always)] + pub fn clock(self) -> &'a mut W { + self.variant(MODE_A::CLOCK) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u16 & 0x03) << 2); + self.w + } +} +#[doc = "Field `MATCHCLR` reader - Clear on Match"] +pub struct MATCHCLR_R(crate::FieldReader); +impl MATCHCLR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MATCHCLR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MATCHCLR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MATCHCLR` writer - Clear on Match"] +pub struct MATCHCLR_W<'a> { + w: &'a mut W, +} +impl<'a> MATCHCLR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: CLK_RTC_CNT = GCLK_RTC/1"] + OFF = 0, + #[doc = "1: CLK_RTC_CNT = GCLK_RTC/1"] + DIV1 = 1, + #[doc = "2: CLK_RTC_CNT = GCLK_RTC/2"] + DIV2 = 2, + #[doc = "3: CLK_RTC_CNT = GCLK_RTC/4"] + DIV4 = 3, + #[doc = "4: CLK_RTC_CNT = GCLK_RTC/8"] + DIV8 = 4, + #[doc = "5: CLK_RTC_CNT = GCLK_RTC/16"] + DIV16 = 5, + #[doc = "6: CLK_RTC_CNT = GCLK_RTC/32"] + DIV32 = 6, + #[doc = "7: CLK_RTC_CNT = GCLK_RTC/64"] + DIV64 = 7, + #[doc = "8: CLK_RTC_CNT = GCLK_RTC/128"] + DIV128 = 8, + #[doc = "9: CLK_RTC_CNT = GCLK_RTC/256"] + DIV256 = 9, + #[doc = "10: CLK_RTC_CNT = GCLK_RTC/512"] + DIV512 = 10, + #[doc = "11: CLK_RTC_CNT = GCLK_RTC/1024"] + DIV1024 = 11, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCALER_A::OFF), + 1 => Some(PRESCALER_A::DIV1), + 2 => Some(PRESCALER_A::DIV2), + 3 => Some(PRESCALER_A::DIV4), + 4 => Some(PRESCALER_A::DIV8), + 5 => Some(PRESCALER_A::DIV16), + 6 => Some(PRESCALER_A::DIV32), + 7 => Some(PRESCALER_A::DIV64), + 8 => Some(PRESCALER_A::DIV128), + 9 => Some(PRESCALER_A::DIV256), + 10 => Some(PRESCALER_A::DIV512), + 11 => Some(PRESCALER_A::DIV1024), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == PRESCALER_A::OFF + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == PRESCALER_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == PRESCALER_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == PRESCALER_A::DIV128 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV512`"] + #[inline(always)] + pub fn is_div512(&self) -> bool { + **self == PRESCALER_A::DIV512 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PRESCALER_A::DIV1024 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(PRESCALER_A::OFF) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV32) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV128) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/512"] + #[inline(always)] + pub fn div512(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV512) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 8)) | ((value as u16 & 0x0f) << 8); + self.w + } +} +#[doc = "Field `COUNTSYNC` reader - Count Read Synchronization Enable"] +pub struct COUNTSYNC_R(crate::FieldReader); +impl COUNTSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNTSYNC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNTSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNTSYNC` writer - Count Read Synchronization Enable"] +pub struct COUNTSYNC_W<'a> { + w: &'a mut W, +} +impl<'a> COUNTSYNC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:3 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bit 7 - Clear on Match"] + #[inline(always)] + pub fn matchclr(&self) -> MATCHCLR_R { + MATCHCLR_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:11 - Prescaler"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 15 - Count Read Synchronization Enable"] + #[inline(always)] + pub fn countsync(&self) -> COUNTSYNC_R { + COUNTSYNC_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:3 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 7 - Clear on Match"] + #[inline(always)] + pub fn matchclr(&mut self) -> MATCHCLR_W { + MATCHCLR_W { w: self } + } + #[doc = "Bits 8:11 - Prescaler"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Bit 15 - Count Read Synchronization Enable"] + #[inline(always)] + pub fn countsync(&mut self) -> COUNTSYNC_W { + COUNTSYNC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE0 Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/rtc/mode0/dbgctrl.rs b/pac/atsamc20j/src/rtc/mode0/dbgctrl.rs new file mode 100644 index 000000000000..0383e70d0429 --- /dev/null +++ b/pac/atsamc20j/src/rtc/mode0/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Run During Debug"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Run During Debug"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/rtc/mode0/evctrl.rs b/pac/atsamc20j/src/rtc/mode0/evctrl.rs new file mode 100644 index 000000000000..c73647759dbe --- /dev/null +++ b/pac/atsamc20j/src/rtc/mode0/evctrl.rs @@ -0,0 +1,536 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PEREO0` reader - Periodic Interval 0 Event Output Enable"] +pub struct PEREO0_R(crate::FieldReader); +impl PEREO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO0` writer - Periodic Interval 0 Event Output Enable"] +pub struct PEREO0_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `PEREO1` reader - Periodic Interval 1 Event Output Enable"] +pub struct PEREO1_R(crate::FieldReader); +impl PEREO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO1` writer - Periodic Interval 1 Event Output Enable"] +pub struct PEREO1_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PEREO2` reader - Periodic Interval 2 Event Output Enable"] +pub struct PEREO2_R(crate::FieldReader); +impl PEREO2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO2` writer - Periodic Interval 2 Event Output Enable"] +pub struct PEREO2_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PEREO3` reader - Periodic Interval 3 Event Output Enable"] +pub struct PEREO3_R(crate::FieldReader); +impl PEREO3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO3` writer - Periodic Interval 3 Event Output Enable"] +pub struct PEREO3_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PEREO4` reader - Periodic Interval 4 Event Output Enable"] +pub struct PEREO4_R(crate::FieldReader); +impl PEREO4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO4` writer - Periodic Interval 4 Event Output Enable"] +pub struct PEREO4_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PEREO5` reader - Periodic Interval 5 Event Output Enable"] +pub struct PEREO5_R(crate::FieldReader); +impl PEREO5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO5` writer - Periodic Interval 5 Event Output Enable"] +pub struct PEREO5_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PEREO6` reader - Periodic Interval 6 Event Output Enable"] +pub struct PEREO6_R(crate::FieldReader); +impl PEREO6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO6` writer - Periodic Interval 6 Event Output Enable"] +pub struct PEREO6_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PEREO7` reader - Periodic Interval 7 Event Output Enable"] +pub struct PEREO7_R(crate::FieldReader); +impl PEREO7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO7` writer - Periodic Interval 7 Event Output Enable"] +pub struct PEREO7_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CMPEO0` reader - Compare 0 Event Output Enable"] +pub struct CMPEO0_R(crate::FieldReader); +impl CMPEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMPEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMPEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMPEO0` writer - Compare 0 Event Output Enable"] +pub struct CMPEO0_W<'a> { + w: &'a mut W, +} +impl<'a> CMPEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `OVFEO` reader - Overflow Event Output Enable"] +pub struct OVFEO_R(crate::FieldReader); +impl OVFEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVFEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVFEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVFEO` writer - Overflow Event Output Enable"] +pub struct OVFEO_W<'a> { + w: &'a mut W, +} +impl<'a> OVFEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Event Output Enable"] + #[inline(always)] + pub fn pereo0(&self) -> PEREO0_R { + PEREO0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Event Output Enable"] + #[inline(always)] + pub fn pereo1(&self) -> PEREO1_R { + PEREO1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Event Output Enable"] + #[inline(always)] + pub fn pereo2(&self) -> PEREO2_R { + PEREO2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Event Output Enable"] + #[inline(always)] + pub fn pereo3(&self) -> PEREO3_R { + PEREO3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Event Output Enable"] + #[inline(always)] + pub fn pereo4(&self) -> PEREO4_R { + PEREO4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Event Output Enable"] + #[inline(always)] + pub fn pereo5(&self) -> PEREO5_R { + PEREO5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Event Output Enable"] + #[inline(always)] + pub fn pereo6(&self) -> PEREO6_R { + PEREO6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Event Output Enable"] + #[inline(always)] + pub fn pereo7(&self) -> PEREO7_R { + PEREO7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Compare 0 Event Output Enable"] + #[inline(always)] + pub fn cmpeo0(&self) -> CMPEO0_R { + CMPEO0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&self) -> OVFEO_R { + OVFEO_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Event Output Enable"] + #[inline(always)] + pub fn pereo0(&mut self) -> PEREO0_W { + PEREO0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1 Event Output Enable"] + #[inline(always)] + pub fn pereo1(&mut self) -> PEREO1_W { + PEREO1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2 Event Output Enable"] + #[inline(always)] + pub fn pereo2(&mut self) -> PEREO2_W { + PEREO2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3 Event Output Enable"] + #[inline(always)] + pub fn pereo3(&mut self) -> PEREO3_W { + PEREO3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4 Event Output Enable"] + #[inline(always)] + pub fn pereo4(&mut self) -> PEREO4_W { + PEREO4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5 Event Output Enable"] + #[inline(always)] + pub fn pereo5(&mut self) -> PEREO5_W { + PEREO5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6 Event Output Enable"] + #[inline(always)] + pub fn pereo6(&mut self) -> PEREO6_W { + PEREO6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7 Event Output Enable"] + #[inline(always)] + pub fn pereo7(&mut self) -> PEREO7_W { + PEREO7_W { w: self } + } + #[doc = "Bit 8 - Compare 0 Event Output Enable"] + #[inline(always)] + pub fn cmpeo0(&mut self) -> CMPEO0_W { + CMPEO0_W { w: self } + } + #[doc = "Bit 15 - Overflow Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&mut self) -> OVFEO_W { + OVFEO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE0 Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/rtc/mode0/freqcorr.rs b/pac/atsamc20j/src/rtc/mode0/freqcorr.rs new file mode 100644 index 000000000000..043ba6f88eb2 --- /dev/null +++ b/pac/atsamc20j/src/rtc/mode0/freqcorr.rs @@ -0,0 +1,150 @@ +#[doc = "Register `FREQCORR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FREQCORR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `VALUE` reader - Correction Value"] +pub struct VALUE_R(crate::FieldReader); +impl VALUE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + VALUE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VALUE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VALUE` writer - Correction Value"] +pub struct VALUE_W<'a> { + w: &'a mut W, +} +impl<'a> VALUE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x7f) | (value as u8 & 0x7f); + self.w + } +} +#[doc = "Field `SIGN` reader - Correction Sign"] +pub struct SIGN_R(crate::FieldReader); +impl SIGN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SIGN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SIGN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SIGN` writer - Correction Sign"] +pub struct SIGN_W<'a> { + w: &'a mut W, +} +impl<'a> SIGN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bits 0:6 - Correction Value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bit 7 - Correction Sign"] + #[inline(always)] + pub fn sign(&self) -> SIGN_R { + SIGN_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:6 - Correction Value"] + #[inline(always)] + pub fn value(&mut self) -> VALUE_W { + VALUE_W { w: self } + } + #[doc = "Bit 7 - Correction Sign"] + #[inline(always)] + pub fn sign(&mut self) -> SIGN_W { + SIGN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Frequency Correction\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [freqcorr](index.html) module"] +pub struct FREQCORR_SPEC; +impl crate::RegisterSpec for FREQCORR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [freqcorr::R](R) reader structure"] +impl crate::Readable for FREQCORR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [freqcorr::W](W) writer structure"] +impl crate::Writable for FREQCORR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets FREQCORR to value 0"] +impl crate::Resettable for FREQCORR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/rtc/mode0/intenclr.rs b/pac/atsamc20j/src/rtc/mode0/intenclr.rs new file mode 100644 index 000000000000..8be5e2c3920b --- /dev/null +++ b/pac/atsamc20j/src/rtc/mode0/intenclr.rs @@ -0,0 +1,536 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER0` reader - Periodic Interval 0 Interrupt Enable"] +pub struct PER0_R(crate::FieldReader); +impl PER0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER0` writer - Periodic Interval 0 Interrupt Enable"] +pub struct PER0_W<'a> { + w: &'a mut W, +} +impl<'a> PER0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PER1` reader - Periodic Interval 1 Interrupt Enable"] +pub struct PER1_R(crate::FieldReader); +impl PER1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER1` writer - Periodic Interval 1 Interrupt Enable"] +pub struct PER1_W<'a> { + w: &'a mut W, +} +impl<'a> PER1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PER2` reader - Periodic Interval 2 Interrupt Enable"] +pub struct PER2_R(crate::FieldReader); +impl PER2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER2` writer - Periodic Interval 2 Interrupt Enable"] +pub struct PER2_W<'a> { + w: &'a mut W, +} +impl<'a> PER2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PER3` reader - Periodic Interval 3 Interrupt Enable"] +pub struct PER3_R(crate::FieldReader); +impl PER3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER3` writer - Periodic Interval 3 Interrupt Enable"] +pub struct PER3_W<'a> { + w: &'a mut W, +} +impl<'a> PER3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PER4` reader - Periodic Interval 4 Interrupt Enable"] +pub struct PER4_R(crate::FieldReader); +impl PER4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER4` writer - Periodic Interval 4 Interrupt Enable"] +pub struct PER4_W<'a> { + w: &'a mut W, +} +impl<'a> PER4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PER5` reader - Periodic Interval 5 Interrupt Enable"] +pub struct PER5_R(crate::FieldReader); +impl PER5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER5` writer - Periodic Interval 5 Interrupt Enable"] +pub struct PER5_W<'a> { + w: &'a mut W, +} +impl<'a> PER5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PER6` reader - Periodic Interval 6 Interrupt Enable"] +pub struct PER6_R(crate::FieldReader); +impl PER6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER6` writer - Periodic Interval 6 Interrupt Enable"] +pub struct PER6_W<'a> { + w: &'a mut W, +} +impl<'a> PER6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PER7` reader - Periodic Interval 7 Interrupt Enable"] +pub struct PER7_R(crate::FieldReader); +impl PER7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER7` writer - Periodic Interval 7 Interrupt Enable"] +pub struct PER7_W<'a> { + w: &'a mut W, +} +impl<'a> PER7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CMP0` reader - Compare 0 Interrupt Enable"] +pub struct CMP0_R(crate::FieldReader); +impl CMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP0` writer - Compare 0 Interrupt Enable"] +pub struct CMP0_W<'a> { + w: &'a mut W, +} +impl<'a> CMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + pub fn per0(&self) -> PER0_R { + PER0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + pub fn per1(&self) -> PER1_R { + PER1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + pub fn per2(&self) -> PER2_R { + PER2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + pub fn per3(&self) -> PER3_R { + PER3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + pub fn per4(&self) -> PER4_R { + PER4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + pub fn per5(&self) -> PER5_R { + PER5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + pub fn per6(&self) -> PER6_R { + PER6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + pub fn per7(&self) -> PER7_R { + PER7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&self) -> CMP0_R { + CMP0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + pub fn per0(&mut self) -> PER0_W { + PER0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + pub fn per1(&mut self) -> PER1_W { + PER1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + pub fn per2(&mut self) -> PER2_W { + PER2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + pub fn per3(&mut self) -> PER3_W { + PER3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + pub fn per4(&mut self) -> PER4_W { + PER4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + pub fn per5(&mut self) -> PER5_W { + PER5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + pub fn per6(&mut self) -> PER6_W { + PER6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + pub fn per7(&mut self) -> PER7_W { + PER7_W { w: self } + } + #[doc = "Bit 8 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&mut self) -> CMP0_W { + CMP0_W { w: self } + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE0 Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/rtc/mode0/intenset.rs b/pac/atsamc20j/src/rtc/mode0/intenset.rs new file mode 100644 index 000000000000..7228f5d486f5 --- /dev/null +++ b/pac/atsamc20j/src/rtc/mode0/intenset.rs @@ -0,0 +1,536 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER0` reader - Periodic Interval 0 Interrupt Enable"] +pub struct PER0_R(crate::FieldReader); +impl PER0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER0` writer - Periodic Interval 0 Interrupt Enable"] +pub struct PER0_W<'a> { + w: &'a mut W, +} +impl<'a> PER0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PER1` reader - Periodic Interval 1 Interrupt Enable"] +pub struct PER1_R(crate::FieldReader); +impl PER1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER1` writer - Periodic Interval 1 Interrupt Enable"] +pub struct PER1_W<'a> { + w: &'a mut W, +} +impl<'a> PER1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PER2` reader - Periodic Interval 2 Interrupt Enable"] +pub struct PER2_R(crate::FieldReader); +impl PER2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER2` writer - Periodic Interval 2 Interrupt Enable"] +pub struct PER2_W<'a> { + w: &'a mut W, +} +impl<'a> PER2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PER3` reader - Periodic Interval 3 Interrupt Enable"] +pub struct PER3_R(crate::FieldReader); +impl PER3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER3` writer - Periodic Interval 3 Interrupt Enable"] +pub struct PER3_W<'a> { + w: &'a mut W, +} +impl<'a> PER3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PER4` reader - Periodic Interval 4 Interrupt Enable"] +pub struct PER4_R(crate::FieldReader); +impl PER4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER4` writer - Periodic Interval 4 Interrupt Enable"] +pub struct PER4_W<'a> { + w: &'a mut W, +} +impl<'a> PER4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PER5` reader - Periodic Interval 5 Interrupt Enable"] +pub struct PER5_R(crate::FieldReader); +impl PER5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER5` writer - Periodic Interval 5 Interrupt Enable"] +pub struct PER5_W<'a> { + w: &'a mut W, +} +impl<'a> PER5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PER6` reader - Periodic Interval 6 Interrupt Enable"] +pub struct PER6_R(crate::FieldReader); +impl PER6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER6` writer - Periodic Interval 6 Interrupt Enable"] +pub struct PER6_W<'a> { + w: &'a mut W, +} +impl<'a> PER6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PER7` reader - Periodic Interval 7 Interrupt Enable"] +pub struct PER7_R(crate::FieldReader); +impl PER7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER7` writer - Periodic Interval 7 Interrupt Enable"] +pub struct PER7_W<'a> { + w: &'a mut W, +} +impl<'a> PER7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CMP0` reader - Compare 0 Interrupt Enable"] +pub struct CMP0_R(crate::FieldReader); +impl CMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP0` writer - Compare 0 Interrupt Enable"] +pub struct CMP0_W<'a> { + w: &'a mut W, +} +impl<'a> CMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + pub fn per0(&self) -> PER0_R { + PER0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + pub fn per1(&self) -> PER1_R { + PER1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + pub fn per2(&self) -> PER2_R { + PER2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + pub fn per3(&self) -> PER3_R { + PER3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + pub fn per4(&self) -> PER4_R { + PER4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + pub fn per5(&self) -> PER5_R { + PER5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + pub fn per6(&self) -> PER6_R { + PER6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + pub fn per7(&self) -> PER7_R { + PER7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&self) -> CMP0_R { + CMP0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + pub fn per0(&mut self) -> PER0_W { + PER0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + pub fn per1(&mut self) -> PER1_W { + PER1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + pub fn per2(&mut self) -> PER2_W { + PER2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + pub fn per3(&mut self) -> PER3_W { + PER3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + pub fn per4(&mut self) -> PER4_W { + PER4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + pub fn per5(&mut self) -> PER5_W { + PER5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + pub fn per6(&mut self) -> PER6_W { + PER6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + pub fn per7(&mut self) -> PER7_W { + PER7_W { w: self } + } + #[doc = "Bit 8 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&mut self) -> CMP0_W { + CMP0_W { w: self } + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE0 Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/rtc/mode0/intflag.rs b/pac/atsamc20j/src/rtc/mode0/intflag.rs new file mode 100644 index 000000000000..f2dccdb04aa4 --- /dev/null +++ b/pac/atsamc20j/src/rtc/mode0/intflag.rs @@ -0,0 +1,536 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER0` reader - Periodic Interval 0"] +pub struct PER0_R(crate::FieldReader); +impl PER0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER0` writer - Periodic Interval 0"] +pub struct PER0_W<'a> { + w: &'a mut W, +} +impl<'a> PER0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PER1` reader - Periodic Interval 1"] +pub struct PER1_R(crate::FieldReader); +impl PER1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER1` writer - Periodic Interval 1"] +pub struct PER1_W<'a> { + w: &'a mut W, +} +impl<'a> PER1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PER2` reader - Periodic Interval 2"] +pub struct PER2_R(crate::FieldReader); +impl PER2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER2` writer - Periodic Interval 2"] +pub struct PER2_W<'a> { + w: &'a mut W, +} +impl<'a> PER2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PER3` reader - Periodic Interval 3"] +pub struct PER3_R(crate::FieldReader); +impl PER3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER3` writer - Periodic Interval 3"] +pub struct PER3_W<'a> { + w: &'a mut W, +} +impl<'a> PER3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PER4` reader - Periodic Interval 4"] +pub struct PER4_R(crate::FieldReader); +impl PER4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER4` writer - Periodic Interval 4"] +pub struct PER4_W<'a> { + w: &'a mut W, +} +impl<'a> PER4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PER5` reader - Periodic Interval 5"] +pub struct PER5_R(crate::FieldReader); +impl PER5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER5` writer - Periodic Interval 5"] +pub struct PER5_W<'a> { + w: &'a mut W, +} +impl<'a> PER5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PER6` reader - Periodic Interval 6"] +pub struct PER6_R(crate::FieldReader); +impl PER6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER6` writer - Periodic Interval 6"] +pub struct PER6_W<'a> { + w: &'a mut W, +} +impl<'a> PER6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PER7` reader - Periodic Interval 7"] +pub struct PER7_R(crate::FieldReader); +impl PER7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER7` writer - Periodic Interval 7"] +pub struct PER7_W<'a> { + w: &'a mut W, +} +impl<'a> PER7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CMP0` reader - Compare 0"] +pub struct CMP0_R(crate::FieldReader); +impl CMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP0` writer - Compare 0"] +pub struct CMP0_W<'a> { + w: &'a mut W, +} +impl<'a> CMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0"] + #[inline(always)] + pub fn per0(&self) -> PER0_R { + PER0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1"] + #[inline(always)] + pub fn per1(&self) -> PER1_R { + PER1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2"] + #[inline(always)] + pub fn per2(&self) -> PER2_R { + PER2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3"] + #[inline(always)] + pub fn per3(&self) -> PER3_R { + PER3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4"] + #[inline(always)] + pub fn per4(&self) -> PER4_R { + PER4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5"] + #[inline(always)] + pub fn per5(&self) -> PER5_R { + PER5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6"] + #[inline(always)] + pub fn per6(&self) -> PER6_R { + PER6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7"] + #[inline(always)] + pub fn per7(&self) -> PER7_R { + PER7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Compare 0"] + #[inline(always)] + pub fn cmp0(&self) -> CMP0_R { + CMP0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0"] + #[inline(always)] + pub fn per0(&mut self) -> PER0_W { + PER0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1"] + #[inline(always)] + pub fn per1(&mut self) -> PER1_W { + PER1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2"] + #[inline(always)] + pub fn per2(&mut self) -> PER2_W { + PER2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3"] + #[inline(always)] + pub fn per3(&mut self) -> PER3_W { + PER3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4"] + #[inline(always)] + pub fn per4(&mut self) -> PER4_W { + PER4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5"] + #[inline(always)] + pub fn per5(&mut self) -> PER5_W { + PER5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6"] + #[inline(always)] + pub fn per6(&mut self) -> PER6_W { + PER6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7"] + #[inline(always)] + pub fn per7(&mut self) -> PER7_W { + PER7_W { w: self } + } + #[doc = "Bit 8 - Compare 0"] + #[inline(always)] + pub fn cmp0(&mut self) -> CMP0_W { + CMP0_W { w: self } + } + #[doc = "Bit 15 - Overflow"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE0 Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/rtc/mode0/syncbusy.rs b/pac/atsamc20j/src/rtc/mode0/syncbusy.rs new file mode 100644 index 000000000000..518dea115a18 --- /dev/null +++ b/pac/atsamc20j/src/rtc/mode0/syncbusy.rs @@ -0,0 +1,153 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - Enable Bit Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FREQCORR` reader - FREQCORR Register Busy"] +pub struct FREQCORR_R(crate::FieldReader); +impl FREQCORR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FREQCORR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FREQCORR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` reader - COUNT Register Busy"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP0` reader - COMP 0 Register Busy"] +pub struct COMP0_R(crate::FieldReader); +impl COMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNTSYNC` reader - Count Read Synchronization Enable Bit Busy"] +pub struct COUNTSYNC_R(crate::FieldReader); +impl COUNTSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNTSYNC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNTSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable Bit Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - FREQCORR Register Busy"] + #[inline(always)] + pub fn freqcorr(&self) -> FREQCORR_R { + FREQCORR_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - COUNT Register Busy"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 5 - COMP 0 Register Busy"] + #[inline(always)] + pub fn comp0(&self) -> COMP0_R { + COMP0_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 15 - Count Read Synchronization Enable Bit Busy"] + #[inline(always)] + pub fn countsync(&self) -> COUNTSYNC_R { + COUNTSYNC_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +#[doc = "MODE0 Synchronization Busy Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/rtc/mode1.rs b/pac/atsamc20j/src/rtc/mode1.rs new file mode 100644 index 000000000000..9ea1bc17497c --- /dev/null +++ b/pac/atsamc20j/src/rtc/mode1.rs @@ -0,0 +1,44 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "MODE1 Control A"] +pub mod ctrla; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "MODE1 Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "MODE1 Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "MODE1 Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "MODE1 Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "MODE1 Synchronization Busy Status"] +pub mod syncbusy; +#[doc = "FREQCORR register accessor: an alias for `Reg`"] +pub type FREQCORR = crate::Reg; +#[doc = "Frequency Correction"] +pub mod freqcorr; +#[doc = "COUNT register accessor: an alias for `Reg`"] +pub type COUNT = crate::Reg; +#[doc = "MODE1 Counter Value"] +pub mod count; +#[doc = "PER register accessor: an alias for `Reg`"] +pub type PER = crate::Reg; +#[doc = "MODE1 Counter Period"] +pub mod per; +#[doc = "COMP register accessor: an alias for `Reg`"] +pub type COMP = crate::Reg; +#[doc = "MODE1 Compare n Value"] +pub mod comp; diff --git a/pac/atsamc20j/src/rtc/mode1/comp.rs b/pac/atsamc20j/src/rtc/mode1/comp.rs new file mode 100644 index 000000000000..6935385840f1 --- /dev/null +++ b/pac/atsamc20j/src/rtc/mode1/comp.rs @@ -0,0 +1,104 @@ +#[doc = "Register `COMP[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COMP[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COMP` reader - Compare Value"] +pub struct COMP_R(crate::FieldReader); +impl COMP_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + COMP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP` writer - Compare Value"] +pub struct COMP_W<'a> { + w: &'a mut W, +} +impl<'a> COMP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Compare Value"] + #[inline(always)] + pub fn comp(&self) -> COMP_R { + COMP_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Compare Value"] + #[inline(always)] + pub fn comp(&mut self) -> COMP_W { + COMP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Compare n Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [comp](index.html) module"] +pub struct COMP_SPEC; +impl crate::RegisterSpec for COMP_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [comp::R](R) reader structure"] +impl crate::Readable for COMP_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [comp::W](W) writer structure"] +impl crate::Writable for COMP_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COMP[%s] +to value 0"] +impl crate::Resettable for COMP_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/rtc/mode1/count.rs b/pac/atsamc20j/src/rtc/mode1/count.rs new file mode 100644 index 000000000000..2c41937b189c --- /dev/null +++ b/pac/atsamc20j/src/rtc/mode1/count.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Counter Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count](index.html) module"] +pub struct COUNT_SPEC; +impl crate::RegisterSpec for COUNT_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [count::R](R) reader structure"] +impl crate::Readable for COUNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count::W](W) writer structure"] +impl crate::Writable for COUNT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT to value 0"] +impl crate::Resettable for COUNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/rtc/mode1/ctrla.rs b/pac/atsamc20j/src/rtc/mode1/ctrla.rs new file mode 100644 index 000000000000..6e3e2042a9c4 --- /dev/null +++ b/pac/atsamc20j/src/rtc/mode1/ctrla.rs @@ -0,0 +1,522 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: Mode 0: 32-bit Counter"] + COUNT32 = 0, + #[doc = "1: Mode 1: 16-bit Counter"] + COUNT16 = 1, + #[doc = "2: Mode 2: Clock/Calendar"] + CLOCK = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::COUNT32), + 1 => Some(MODE_A::COUNT16), + 2 => Some(MODE_A::CLOCK), + _ => None, + } + } + #[doc = "Checks if the value of the field is `COUNT32`"] + #[inline(always)] + pub fn is_count32(&self) -> bool { + **self == MODE_A::COUNT32 + } + #[doc = "Checks if the value of the field is `COUNT16`"] + #[inline(always)] + pub fn is_count16(&self) -> bool { + **self == MODE_A::COUNT16 + } + #[doc = "Checks if the value of the field is `CLOCK`"] + #[inline(always)] + pub fn is_clock(&self) -> bool { + **self == MODE_A::CLOCK + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Mode 0: 32-bit Counter"] + #[inline(always)] + pub fn count32(self) -> &'a mut W { + self.variant(MODE_A::COUNT32) + } + #[doc = "Mode 1: 16-bit Counter"] + #[inline(always)] + pub fn count16(self) -> &'a mut W { + self.variant(MODE_A::COUNT16) + } + #[doc = "Mode 2: Clock/Calendar"] + #[inline(always)] + pub fn clock(self) -> &'a mut W { + self.variant(MODE_A::CLOCK) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u16 & 0x03) << 2); + self.w + } +} +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: CLK_RTC_CNT = GCLK_RTC/1"] + OFF = 0, + #[doc = "1: CLK_RTC_CNT = GCLK_RTC/1"] + DIV1 = 1, + #[doc = "2: CLK_RTC_CNT = GCLK_RTC/2"] + DIV2 = 2, + #[doc = "3: CLK_RTC_CNT = GCLK_RTC/4"] + DIV4 = 3, + #[doc = "4: CLK_RTC_CNT = GCLK_RTC/8"] + DIV8 = 4, + #[doc = "5: CLK_RTC_CNT = GCLK_RTC/16"] + DIV16 = 5, + #[doc = "6: CLK_RTC_CNT = GCLK_RTC/32"] + DIV32 = 6, + #[doc = "7: CLK_RTC_CNT = GCLK_RTC/64"] + DIV64 = 7, + #[doc = "8: CLK_RTC_CNT = GCLK_RTC/128"] + DIV128 = 8, + #[doc = "9: CLK_RTC_CNT = GCLK_RTC/256"] + DIV256 = 9, + #[doc = "10: CLK_RTC_CNT = GCLK_RTC/512"] + DIV512 = 10, + #[doc = "11: CLK_RTC_CNT = GCLK_RTC/1024"] + DIV1024 = 11, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCALER_A::OFF), + 1 => Some(PRESCALER_A::DIV1), + 2 => Some(PRESCALER_A::DIV2), + 3 => Some(PRESCALER_A::DIV4), + 4 => Some(PRESCALER_A::DIV8), + 5 => Some(PRESCALER_A::DIV16), + 6 => Some(PRESCALER_A::DIV32), + 7 => Some(PRESCALER_A::DIV64), + 8 => Some(PRESCALER_A::DIV128), + 9 => Some(PRESCALER_A::DIV256), + 10 => Some(PRESCALER_A::DIV512), + 11 => Some(PRESCALER_A::DIV1024), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == PRESCALER_A::OFF + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == PRESCALER_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == PRESCALER_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == PRESCALER_A::DIV128 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV512`"] + #[inline(always)] + pub fn is_div512(&self) -> bool { + **self == PRESCALER_A::DIV512 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PRESCALER_A::DIV1024 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(PRESCALER_A::OFF) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV32) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV128) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/512"] + #[inline(always)] + pub fn div512(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV512) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 8)) | ((value as u16 & 0x0f) << 8); + self.w + } +} +#[doc = "Field `COUNTSYNC` reader - Count Read Synchronization Enable"] +pub struct COUNTSYNC_R(crate::FieldReader); +impl COUNTSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNTSYNC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNTSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNTSYNC` writer - Count Read Synchronization Enable"] +pub struct COUNTSYNC_W<'a> { + w: &'a mut W, +} +impl<'a> COUNTSYNC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:3 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bits 8:11 - Prescaler"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 15 - Count Read Synchronization Enable"] + #[inline(always)] + pub fn countsync(&self) -> COUNTSYNC_R { + COUNTSYNC_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:3 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bits 8:11 - Prescaler"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Bit 15 - Count Read Synchronization Enable"] + #[inline(always)] + pub fn countsync(&mut self) -> COUNTSYNC_W { + COUNTSYNC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/rtc/mode1/dbgctrl.rs b/pac/atsamc20j/src/rtc/mode1/dbgctrl.rs new file mode 100644 index 000000000000..0383e70d0429 --- /dev/null +++ b/pac/atsamc20j/src/rtc/mode1/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Run During Debug"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Run During Debug"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/rtc/mode1/evctrl.rs b/pac/atsamc20j/src/rtc/mode1/evctrl.rs new file mode 100644 index 000000000000..e15624f828c7 --- /dev/null +++ b/pac/atsamc20j/src/rtc/mode1/evctrl.rs @@ -0,0 +1,583 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PEREO0` reader - Periodic Interval 0 Event Output Enable"] +pub struct PEREO0_R(crate::FieldReader); +impl PEREO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO0` writer - Periodic Interval 0 Event Output Enable"] +pub struct PEREO0_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `PEREO1` reader - Periodic Interval 1 Event Output Enable"] +pub struct PEREO1_R(crate::FieldReader); +impl PEREO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO1` writer - Periodic Interval 1 Event Output Enable"] +pub struct PEREO1_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PEREO2` reader - Periodic Interval 2 Event Output Enable"] +pub struct PEREO2_R(crate::FieldReader); +impl PEREO2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO2` writer - Periodic Interval 2 Event Output Enable"] +pub struct PEREO2_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PEREO3` reader - Periodic Interval 3 Event Output Enable"] +pub struct PEREO3_R(crate::FieldReader); +impl PEREO3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO3` writer - Periodic Interval 3 Event Output Enable"] +pub struct PEREO3_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PEREO4` reader - Periodic Interval 4 Event Output Enable"] +pub struct PEREO4_R(crate::FieldReader); +impl PEREO4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO4` writer - Periodic Interval 4 Event Output Enable"] +pub struct PEREO4_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PEREO5` reader - Periodic Interval 5 Event Output Enable"] +pub struct PEREO5_R(crate::FieldReader); +impl PEREO5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO5` writer - Periodic Interval 5 Event Output Enable"] +pub struct PEREO5_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PEREO6` reader - Periodic Interval 6 Event Output Enable"] +pub struct PEREO6_R(crate::FieldReader); +impl PEREO6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO6` writer - Periodic Interval 6 Event Output Enable"] +pub struct PEREO6_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PEREO7` reader - Periodic Interval 7 Event Output Enable"] +pub struct PEREO7_R(crate::FieldReader); +impl PEREO7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO7` writer - Periodic Interval 7 Event Output Enable"] +pub struct PEREO7_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CMPEO0` reader - Compare 0 Event Output Enable"] +pub struct CMPEO0_R(crate::FieldReader); +impl CMPEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMPEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMPEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMPEO0` writer - Compare 0 Event Output Enable"] +pub struct CMPEO0_W<'a> { + w: &'a mut W, +} +impl<'a> CMPEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `CMPEO1` reader - Compare 1 Event Output Enable"] +pub struct CMPEO1_R(crate::FieldReader); +impl CMPEO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMPEO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMPEO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMPEO1` writer - Compare 1 Event Output Enable"] +pub struct CMPEO1_W<'a> { + w: &'a mut W, +} +impl<'a> CMPEO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `OVFEO` reader - Overflow Event Output Enable"] +pub struct OVFEO_R(crate::FieldReader); +impl OVFEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVFEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVFEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVFEO` writer - Overflow Event Output Enable"] +pub struct OVFEO_W<'a> { + w: &'a mut W, +} +impl<'a> OVFEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Event Output Enable"] + #[inline(always)] + pub fn pereo0(&self) -> PEREO0_R { + PEREO0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Event Output Enable"] + #[inline(always)] + pub fn pereo1(&self) -> PEREO1_R { + PEREO1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Event Output Enable"] + #[inline(always)] + pub fn pereo2(&self) -> PEREO2_R { + PEREO2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Event Output Enable"] + #[inline(always)] + pub fn pereo3(&self) -> PEREO3_R { + PEREO3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Event Output Enable"] + #[inline(always)] + pub fn pereo4(&self) -> PEREO4_R { + PEREO4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Event Output Enable"] + #[inline(always)] + pub fn pereo5(&self) -> PEREO5_R { + PEREO5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Event Output Enable"] + #[inline(always)] + pub fn pereo6(&self) -> PEREO6_R { + PEREO6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Event Output Enable"] + #[inline(always)] + pub fn pereo7(&self) -> PEREO7_R { + PEREO7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Compare 0 Event Output Enable"] + #[inline(always)] + pub fn cmpeo0(&self) -> CMPEO0_R { + CMPEO0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Compare 1 Event Output Enable"] + #[inline(always)] + pub fn cmpeo1(&self) -> CMPEO1_R { + CMPEO1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&self) -> OVFEO_R { + OVFEO_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Event Output Enable"] + #[inline(always)] + pub fn pereo0(&mut self) -> PEREO0_W { + PEREO0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1 Event Output Enable"] + #[inline(always)] + pub fn pereo1(&mut self) -> PEREO1_W { + PEREO1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2 Event Output Enable"] + #[inline(always)] + pub fn pereo2(&mut self) -> PEREO2_W { + PEREO2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3 Event Output Enable"] + #[inline(always)] + pub fn pereo3(&mut self) -> PEREO3_W { + PEREO3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4 Event Output Enable"] + #[inline(always)] + pub fn pereo4(&mut self) -> PEREO4_W { + PEREO4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5 Event Output Enable"] + #[inline(always)] + pub fn pereo5(&mut self) -> PEREO5_W { + PEREO5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6 Event Output Enable"] + #[inline(always)] + pub fn pereo6(&mut self) -> PEREO6_W { + PEREO6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7 Event Output Enable"] + #[inline(always)] + pub fn pereo7(&mut self) -> PEREO7_W { + PEREO7_W { w: self } + } + #[doc = "Bit 8 - Compare 0 Event Output Enable"] + #[inline(always)] + pub fn cmpeo0(&mut self) -> CMPEO0_W { + CMPEO0_W { w: self } + } + #[doc = "Bit 9 - Compare 1 Event Output Enable"] + #[inline(always)] + pub fn cmpeo1(&mut self) -> CMPEO1_W { + CMPEO1_W { w: self } + } + #[doc = "Bit 15 - Overflow Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&mut self) -> OVFEO_W { + OVFEO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/rtc/mode1/freqcorr.rs b/pac/atsamc20j/src/rtc/mode1/freqcorr.rs new file mode 100644 index 000000000000..043ba6f88eb2 --- /dev/null +++ b/pac/atsamc20j/src/rtc/mode1/freqcorr.rs @@ -0,0 +1,150 @@ +#[doc = "Register `FREQCORR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FREQCORR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `VALUE` reader - Correction Value"] +pub struct VALUE_R(crate::FieldReader); +impl VALUE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + VALUE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VALUE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VALUE` writer - Correction Value"] +pub struct VALUE_W<'a> { + w: &'a mut W, +} +impl<'a> VALUE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x7f) | (value as u8 & 0x7f); + self.w + } +} +#[doc = "Field `SIGN` reader - Correction Sign"] +pub struct SIGN_R(crate::FieldReader); +impl SIGN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SIGN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SIGN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SIGN` writer - Correction Sign"] +pub struct SIGN_W<'a> { + w: &'a mut W, +} +impl<'a> SIGN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bits 0:6 - Correction Value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bit 7 - Correction Sign"] + #[inline(always)] + pub fn sign(&self) -> SIGN_R { + SIGN_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:6 - Correction Value"] + #[inline(always)] + pub fn value(&mut self) -> VALUE_W { + VALUE_W { w: self } + } + #[doc = "Bit 7 - Correction Sign"] + #[inline(always)] + pub fn sign(&mut self) -> SIGN_W { + SIGN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Frequency Correction\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [freqcorr](index.html) module"] +pub struct FREQCORR_SPEC; +impl crate::RegisterSpec for FREQCORR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [freqcorr::R](R) reader structure"] +impl crate::Readable for FREQCORR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [freqcorr::W](W) writer structure"] +impl crate::Writable for FREQCORR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets FREQCORR to value 0"] +impl crate::Resettable for FREQCORR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/rtc/mode1/intenclr.rs b/pac/atsamc20j/src/rtc/mode1/intenclr.rs new file mode 100644 index 000000000000..d3fc5b3df34b --- /dev/null +++ b/pac/atsamc20j/src/rtc/mode1/intenclr.rs @@ -0,0 +1,583 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER0` reader - Periodic Interval 0 Interrupt Enable"] +pub struct PER0_R(crate::FieldReader); +impl PER0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER0` writer - Periodic Interval 0 Interrupt Enable"] +pub struct PER0_W<'a> { + w: &'a mut W, +} +impl<'a> PER0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PER1` reader - Periodic Interval 1 Interrupt Enable"] +pub struct PER1_R(crate::FieldReader); +impl PER1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER1` writer - Periodic Interval 1 Interrupt Enable"] +pub struct PER1_W<'a> { + w: &'a mut W, +} +impl<'a> PER1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PER2` reader - Periodic Interval 2 Interrupt Enable"] +pub struct PER2_R(crate::FieldReader); +impl PER2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER2` writer - Periodic Interval 2 Interrupt Enable"] +pub struct PER2_W<'a> { + w: &'a mut W, +} +impl<'a> PER2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PER3` reader - Periodic Interval 3 Interrupt Enable"] +pub struct PER3_R(crate::FieldReader); +impl PER3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER3` writer - Periodic Interval 3 Interrupt Enable"] +pub struct PER3_W<'a> { + w: &'a mut W, +} +impl<'a> PER3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PER4` reader - Periodic Interval 4 Interrupt Enable"] +pub struct PER4_R(crate::FieldReader); +impl PER4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER4` writer - Periodic Interval 4 Interrupt Enable"] +pub struct PER4_W<'a> { + w: &'a mut W, +} +impl<'a> PER4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PER5` reader - Periodic Interval 5 Interrupt Enable"] +pub struct PER5_R(crate::FieldReader); +impl PER5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER5` writer - Periodic Interval 5 Interrupt Enable"] +pub struct PER5_W<'a> { + w: &'a mut W, +} +impl<'a> PER5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PER6` reader - Periodic Interval 6 Interrupt Enable"] +pub struct PER6_R(crate::FieldReader); +impl PER6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER6` writer - Periodic Interval 6 Interrupt Enable"] +pub struct PER6_W<'a> { + w: &'a mut W, +} +impl<'a> PER6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PER7` reader - Periodic Interval 7 Interrupt Enable"] +pub struct PER7_R(crate::FieldReader); +impl PER7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER7` writer - Periodic Interval 7 Interrupt Enable"] +pub struct PER7_W<'a> { + w: &'a mut W, +} +impl<'a> PER7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CMP0` reader - Compare 0 Interrupt Enable"] +pub struct CMP0_R(crate::FieldReader); +impl CMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP0` writer - Compare 0 Interrupt Enable"] +pub struct CMP0_W<'a> { + w: &'a mut W, +} +impl<'a> CMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `CMP1` reader - Compare 1 Interrupt Enable"] +pub struct CMP1_R(crate::FieldReader); +impl CMP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP1` writer - Compare 1 Interrupt Enable"] +pub struct CMP1_W<'a> { + w: &'a mut W, +} +impl<'a> CMP1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + pub fn per0(&self) -> PER0_R { + PER0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + pub fn per1(&self) -> PER1_R { + PER1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + pub fn per2(&self) -> PER2_R { + PER2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + pub fn per3(&self) -> PER3_R { + PER3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + pub fn per4(&self) -> PER4_R { + PER4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + pub fn per5(&self) -> PER5_R { + PER5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + pub fn per6(&self) -> PER6_R { + PER6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + pub fn per7(&self) -> PER7_R { + PER7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&self) -> CMP0_R { + CMP0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Compare 1 Interrupt Enable"] + #[inline(always)] + pub fn cmp1(&self) -> CMP1_R { + CMP1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + pub fn per0(&mut self) -> PER0_W { + PER0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + pub fn per1(&mut self) -> PER1_W { + PER1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + pub fn per2(&mut self) -> PER2_W { + PER2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + pub fn per3(&mut self) -> PER3_W { + PER3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + pub fn per4(&mut self) -> PER4_W { + PER4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + pub fn per5(&mut self) -> PER5_W { + PER5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + pub fn per6(&mut self) -> PER6_W { + PER6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + pub fn per7(&mut self) -> PER7_W { + PER7_W { w: self } + } + #[doc = "Bit 8 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&mut self) -> CMP0_W { + CMP0_W { w: self } + } + #[doc = "Bit 9 - Compare 1 Interrupt Enable"] + #[inline(always)] + pub fn cmp1(&mut self) -> CMP1_W { + CMP1_W { w: self } + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/rtc/mode1/intenset.rs b/pac/atsamc20j/src/rtc/mode1/intenset.rs new file mode 100644 index 000000000000..074cb377926a --- /dev/null +++ b/pac/atsamc20j/src/rtc/mode1/intenset.rs @@ -0,0 +1,583 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER0` reader - Periodic Interval 0 Interrupt Enable"] +pub struct PER0_R(crate::FieldReader); +impl PER0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER0` writer - Periodic Interval 0 Interrupt Enable"] +pub struct PER0_W<'a> { + w: &'a mut W, +} +impl<'a> PER0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PER1` reader - Periodic Interval 1 Interrupt Enable"] +pub struct PER1_R(crate::FieldReader); +impl PER1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER1` writer - Periodic Interval 1 Interrupt Enable"] +pub struct PER1_W<'a> { + w: &'a mut W, +} +impl<'a> PER1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PER2` reader - Periodic Interval 2 Interrupt Enable"] +pub struct PER2_R(crate::FieldReader); +impl PER2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER2` writer - Periodic Interval 2 Interrupt Enable"] +pub struct PER2_W<'a> { + w: &'a mut W, +} +impl<'a> PER2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PER3` reader - Periodic Interval 3 Interrupt Enable"] +pub struct PER3_R(crate::FieldReader); +impl PER3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER3` writer - Periodic Interval 3 Interrupt Enable"] +pub struct PER3_W<'a> { + w: &'a mut W, +} +impl<'a> PER3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PER4` reader - Periodic Interval 4 Interrupt Enable"] +pub struct PER4_R(crate::FieldReader); +impl PER4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER4` writer - Periodic Interval 4 Interrupt Enable"] +pub struct PER4_W<'a> { + w: &'a mut W, +} +impl<'a> PER4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PER5` reader - Periodic Interval 5 Interrupt Enable"] +pub struct PER5_R(crate::FieldReader); +impl PER5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER5` writer - Periodic Interval 5 Interrupt Enable"] +pub struct PER5_W<'a> { + w: &'a mut W, +} +impl<'a> PER5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PER6` reader - Periodic Interval 6 Interrupt Enable"] +pub struct PER6_R(crate::FieldReader); +impl PER6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER6` writer - Periodic Interval 6 Interrupt Enable"] +pub struct PER6_W<'a> { + w: &'a mut W, +} +impl<'a> PER6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PER7` reader - Periodic Interval 7 Interrupt Enable"] +pub struct PER7_R(crate::FieldReader); +impl PER7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER7` writer - Periodic Interval 7 Interrupt Enable"] +pub struct PER7_W<'a> { + w: &'a mut W, +} +impl<'a> PER7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CMP0` reader - Compare 0 Interrupt Enable"] +pub struct CMP0_R(crate::FieldReader); +impl CMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP0` writer - Compare 0 Interrupt Enable"] +pub struct CMP0_W<'a> { + w: &'a mut W, +} +impl<'a> CMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `CMP1` reader - Compare 1 Interrupt Enable"] +pub struct CMP1_R(crate::FieldReader); +impl CMP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP1` writer - Compare 1 Interrupt Enable"] +pub struct CMP1_W<'a> { + w: &'a mut W, +} +impl<'a> CMP1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + pub fn per0(&self) -> PER0_R { + PER0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + pub fn per1(&self) -> PER1_R { + PER1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + pub fn per2(&self) -> PER2_R { + PER2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + pub fn per3(&self) -> PER3_R { + PER3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + pub fn per4(&self) -> PER4_R { + PER4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + pub fn per5(&self) -> PER5_R { + PER5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + pub fn per6(&self) -> PER6_R { + PER6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + pub fn per7(&self) -> PER7_R { + PER7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&self) -> CMP0_R { + CMP0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Compare 1 Interrupt Enable"] + #[inline(always)] + pub fn cmp1(&self) -> CMP1_R { + CMP1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + pub fn per0(&mut self) -> PER0_W { + PER0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + pub fn per1(&mut self) -> PER1_W { + PER1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + pub fn per2(&mut self) -> PER2_W { + PER2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + pub fn per3(&mut self) -> PER3_W { + PER3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + pub fn per4(&mut self) -> PER4_W { + PER4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + pub fn per5(&mut self) -> PER5_W { + PER5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + pub fn per6(&mut self) -> PER6_W { + PER6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + pub fn per7(&mut self) -> PER7_W { + PER7_W { w: self } + } + #[doc = "Bit 8 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&mut self) -> CMP0_W { + CMP0_W { w: self } + } + #[doc = "Bit 9 - Compare 1 Interrupt Enable"] + #[inline(always)] + pub fn cmp1(&mut self) -> CMP1_W { + CMP1_W { w: self } + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/rtc/mode1/intflag.rs b/pac/atsamc20j/src/rtc/mode1/intflag.rs new file mode 100644 index 000000000000..25bce956f46b --- /dev/null +++ b/pac/atsamc20j/src/rtc/mode1/intflag.rs @@ -0,0 +1,583 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER0` reader - Periodic Interval 0"] +pub struct PER0_R(crate::FieldReader); +impl PER0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER0` writer - Periodic Interval 0"] +pub struct PER0_W<'a> { + w: &'a mut W, +} +impl<'a> PER0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PER1` reader - Periodic Interval 1"] +pub struct PER1_R(crate::FieldReader); +impl PER1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER1` writer - Periodic Interval 1"] +pub struct PER1_W<'a> { + w: &'a mut W, +} +impl<'a> PER1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PER2` reader - Periodic Interval 2"] +pub struct PER2_R(crate::FieldReader); +impl PER2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER2` writer - Periodic Interval 2"] +pub struct PER2_W<'a> { + w: &'a mut W, +} +impl<'a> PER2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PER3` reader - Periodic Interval 3"] +pub struct PER3_R(crate::FieldReader); +impl PER3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER3` writer - Periodic Interval 3"] +pub struct PER3_W<'a> { + w: &'a mut W, +} +impl<'a> PER3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PER4` reader - Periodic Interval 4"] +pub struct PER4_R(crate::FieldReader); +impl PER4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER4` writer - Periodic Interval 4"] +pub struct PER4_W<'a> { + w: &'a mut W, +} +impl<'a> PER4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PER5` reader - Periodic Interval 5"] +pub struct PER5_R(crate::FieldReader); +impl PER5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER5` writer - Periodic Interval 5"] +pub struct PER5_W<'a> { + w: &'a mut W, +} +impl<'a> PER5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PER6` reader - Periodic Interval 6"] +pub struct PER6_R(crate::FieldReader); +impl PER6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER6` writer - Periodic Interval 6"] +pub struct PER6_W<'a> { + w: &'a mut W, +} +impl<'a> PER6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PER7` reader - Periodic Interval 7"] +pub struct PER7_R(crate::FieldReader); +impl PER7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER7` writer - Periodic Interval 7"] +pub struct PER7_W<'a> { + w: &'a mut W, +} +impl<'a> PER7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CMP0` reader - Compare 0"] +pub struct CMP0_R(crate::FieldReader); +impl CMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP0` writer - Compare 0"] +pub struct CMP0_W<'a> { + w: &'a mut W, +} +impl<'a> CMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `CMP1` reader - Compare 1"] +pub struct CMP1_R(crate::FieldReader); +impl CMP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP1` writer - Compare 1"] +pub struct CMP1_W<'a> { + w: &'a mut W, +} +impl<'a> CMP1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0"] + #[inline(always)] + pub fn per0(&self) -> PER0_R { + PER0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1"] + #[inline(always)] + pub fn per1(&self) -> PER1_R { + PER1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2"] + #[inline(always)] + pub fn per2(&self) -> PER2_R { + PER2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3"] + #[inline(always)] + pub fn per3(&self) -> PER3_R { + PER3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4"] + #[inline(always)] + pub fn per4(&self) -> PER4_R { + PER4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5"] + #[inline(always)] + pub fn per5(&self) -> PER5_R { + PER5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6"] + #[inline(always)] + pub fn per6(&self) -> PER6_R { + PER6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7"] + #[inline(always)] + pub fn per7(&self) -> PER7_R { + PER7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Compare 0"] + #[inline(always)] + pub fn cmp0(&self) -> CMP0_R { + CMP0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Compare 1"] + #[inline(always)] + pub fn cmp1(&self) -> CMP1_R { + CMP1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0"] + #[inline(always)] + pub fn per0(&mut self) -> PER0_W { + PER0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1"] + #[inline(always)] + pub fn per1(&mut self) -> PER1_W { + PER1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2"] + #[inline(always)] + pub fn per2(&mut self) -> PER2_W { + PER2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3"] + #[inline(always)] + pub fn per3(&mut self) -> PER3_W { + PER3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4"] + #[inline(always)] + pub fn per4(&mut self) -> PER4_W { + PER4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5"] + #[inline(always)] + pub fn per5(&mut self) -> PER5_W { + PER5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6"] + #[inline(always)] + pub fn per6(&mut self) -> PER6_W { + PER6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7"] + #[inline(always)] + pub fn per7(&mut self) -> PER7_W { + PER7_W { w: self } + } + #[doc = "Bit 8 - Compare 0"] + #[inline(always)] + pub fn cmp0(&mut self) -> CMP0_W { + CMP0_W { w: self } + } + #[doc = "Bit 9 - Compare 1"] + #[inline(always)] + pub fn cmp1(&mut self) -> CMP1_W { + CMP1_W { w: self } + } + #[doc = "Bit 15 - Overflow"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/rtc/mode1/per.rs b/pac/atsamc20j/src/rtc/mode1/per.rs new file mode 100644 index 000000000000..c09b31fa30dd --- /dev/null +++ b/pac/atsamc20j/src/rtc/mode1/per.rs @@ -0,0 +1,103 @@ +#[doc = "Register `PER` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PER` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER` reader - Counter Period"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` writer - Counter Period"] +pub struct PER_W<'a> { + w: &'a mut W, +} +impl<'a> PER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Counter Period"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Counter Period"] + #[inline(always)] + pub fn per(&mut self) -> PER_W { + PER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Counter Period\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [per](index.html) module"] +pub struct PER_SPEC; +impl crate::RegisterSpec for PER_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [per::R](R) reader structure"] +impl crate::Readable for PER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [per::W](W) writer structure"] +impl crate::Writable for PER_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PER to value 0"] +impl crate::Resettable for PER_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/rtc/mode1/syncbusy.rs b/pac/atsamc20j/src/rtc/mode1/syncbusy.rs new file mode 100644 index 000000000000..b64c973bafff --- /dev/null +++ b/pac/atsamc20j/src/rtc/mode1/syncbusy.rs @@ -0,0 +1,193 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Bit Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - Enable Bit Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FREQCORR` reader - FREQCORR Register Busy"] +pub struct FREQCORR_R(crate::FieldReader); +impl FREQCORR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FREQCORR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FREQCORR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` reader - COUNT Register Busy"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` reader - PER Register Busy"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP0` reader - COMP 0 Register Busy"] +pub struct COMP0_R(crate::FieldReader); +impl COMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP1` reader - COMP 1 Register Busy"] +pub struct COMP1_R(crate::FieldReader); +impl COMP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNTSYNC` reader - Count Read Synchronization Enable Bit Busy"] +pub struct COUNTSYNC_R(crate::FieldReader); +impl COUNTSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNTSYNC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNTSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Bit Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable Bit Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - FREQCORR Register Busy"] + #[inline(always)] + pub fn freqcorr(&self) -> FREQCORR_R { + FREQCORR_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - COUNT Register Busy"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - PER Register Busy"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - COMP 0 Register Busy"] + #[inline(always)] + pub fn comp0(&self) -> COMP0_R { + COMP0_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - COMP 1 Register Busy"] + #[inline(always)] + pub fn comp1(&self) -> COMP1_R { + COMP1_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 15 - Count Read Synchronization Enable Bit Busy"] + #[inline(always)] + pub fn countsync(&self) -> COUNTSYNC_R { + COUNTSYNC_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +#[doc = "MODE1 Synchronization Busy Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/rtc/mode2.rs b/pac/atsamc20j/src/rtc/mode2.rs new file mode 100644 index 000000000000..b0bc13e81dbc --- /dev/null +++ b/pac/atsamc20j/src/rtc/mode2.rs @@ -0,0 +1,44 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "MODE2 Control A"] +pub mod ctrla; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "MODE2 Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "MODE2 Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "MODE2 Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "MODE2 Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "MODE2 Synchronization Busy Status"] +pub mod syncbusy; +#[doc = "FREQCORR register accessor: an alias for `Reg`"] +pub type FREQCORR = crate::Reg; +#[doc = "Frequency Correction"] +pub mod freqcorr; +#[doc = "CLOCK register accessor: an alias for `Reg`"] +pub type CLOCK = crate::Reg; +#[doc = "MODE2 Clock Value"] +pub mod clock; +#[doc = "ALARM register accessor: an alias for `Reg`"] +pub type ALARM = crate::Reg; +#[doc = "MODE2_ALARM Alarm n Value"] +pub mod alarm; +#[doc = "MASK register accessor: an alias for `Reg`"] +pub type MASK = crate::Reg; +#[doc = "MODE2_ALARM Alarm n Mask"] +pub mod mask; diff --git a/pac/atsamc20j/src/rtc/mode2/alarm.rs b/pac/atsamc20j/src/rtc/mode2/alarm.rs new file mode 100644 index 000000000000..1242477ea69f --- /dev/null +++ b/pac/atsamc20j/src/rtc/mode2/alarm.rs @@ -0,0 +1,337 @@ +#[doc = "Register `ALARM` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ALARM` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SECOND` reader - Second"] +pub struct SECOND_R(crate::FieldReader); +impl SECOND_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SECOND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SECOND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SECOND` writer - Second"] +pub struct SECOND_W<'a> { + w: &'a mut W, +} +impl<'a> SECOND_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +#[doc = "Field `MINUTE` reader - Minute"] +pub struct MINUTE_R(crate::FieldReader); +impl MINUTE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MINUTE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MINUTE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MINUTE` writer - Minute"] +pub struct MINUTE_W<'a> { + w: &'a mut W, +} +impl<'a> MINUTE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 6)) | ((value as u32 & 0x3f) << 6); + self.w + } +} +#[doc = "Hour\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum HOUR_A { + #[doc = "0: Morning hour"] + AM = 0, + #[doc = "16: Afternoon hour"] + PM = 16, +} +impl From for u8 { + #[inline(always)] + fn from(variant: HOUR_A) -> Self { + variant as _ + } +} +#[doc = "Field `HOUR` reader - Hour"] +pub struct HOUR_R(crate::FieldReader); +impl HOUR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + HOUR_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(HOUR_A::AM), + 16 => Some(HOUR_A::PM), + _ => None, + } + } + #[doc = "Checks if the value of the field is `AM`"] + #[inline(always)] + pub fn is_am(&self) -> bool { + **self == HOUR_A::AM + } + #[doc = "Checks if the value of the field is `PM`"] + #[inline(always)] + pub fn is_pm(&self) -> bool { + **self == HOUR_A::PM + } +} +impl core::ops::Deref for HOUR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HOUR` writer - Hour"] +pub struct HOUR_W<'a> { + w: &'a mut W, +} +impl<'a> HOUR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: HOUR_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Morning hour"] + #[inline(always)] + pub fn am(self) -> &'a mut W { + self.variant(HOUR_A::AM) + } + #[doc = "Afternoon hour"] + #[inline(always)] + pub fn pm(self) -> &'a mut W { + self.variant(HOUR_A::PM) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 12)) | ((value as u32 & 0x1f) << 12); + self.w + } +} +#[doc = "Field `DAY` reader - Day"] +pub struct DAY_R(crate::FieldReader); +impl DAY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DAY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DAY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DAY` writer - Day"] +pub struct DAY_W<'a> { + w: &'a mut W, +} +impl<'a> DAY_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 17)) | ((value as u32 & 0x1f) << 17); + self.w + } +} +#[doc = "Field `MONTH` reader - Month"] +pub struct MONTH_R(crate::FieldReader); +impl MONTH_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MONTH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MONTH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MONTH` writer - Month"] +pub struct MONTH_W<'a> { + w: &'a mut W, +} +impl<'a> MONTH_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 22)) | ((value as u32 & 0x0f) << 22); + self.w + } +} +#[doc = "Field `YEAR` reader - Year"] +pub struct YEAR_R(crate::FieldReader); +impl YEAR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + YEAR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for YEAR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `YEAR` writer - Year"] +pub struct YEAR_W<'a> { + w: &'a mut W, +} +impl<'a> YEAR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 26)) | ((value as u32 & 0x3f) << 26); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Second"] + #[inline(always)] + pub fn second(&self) -> SECOND_R { + SECOND_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:11 - Minute"] + #[inline(always)] + pub fn minute(&self) -> MINUTE_R { + MINUTE_R::new(((self.bits >> 6) & 0x3f) as u8) + } + #[doc = "Bits 12:16 - Hour"] + #[inline(always)] + pub fn hour(&self) -> HOUR_R { + HOUR_R::new(((self.bits >> 12) & 0x1f) as u8) + } + #[doc = "Bits 17:21 - Day"] + #[inline(always)] + pub fn day(&self) -> DAY_R { + DAY_R::new(((self.bits >> 17) & 0x1f) as u8) + } + #[doc = "Bits 22:25 - Month"] + #[inline(always)] + pub fn month(&self) -> MONTH_R { + MONTH_R::new(((self.bits >> 22) & 0x0f) as u8) + } + #[doc = "Bits 26:31 - Year"] + #[inline(always)] + pub fn year(&self) -> YEAR_R { + YEAR_R::new(((self.bits >> 26) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - Second"] + #[inline(always)] + pub fn second(&mut self) -> SECOND_W { + SECOND_W { w: self } + } + #[doc = "Bits 6:11 - Minute"] + #[inline(always)] + pub fn minute(&mut self) -> MINUTE_W { + MINUTE_W { w: self } + } + #[doc = "Bits 12:16 - Hour"] + #[inline(always)] + pub fn hour(&mut self) -> HOUR_W { + HOUR_W { w: self } + } + #[doc = "Bits 17:21 - Day"] + #[inline(always)] + pub fn day(&mut self) -> DAY_W { + DAY_W { w: self } + } + #[doc = "Bits 22:25 - Month"] + #[inline(always)] + pub fn month(&mut self) -> MONTH_W { + MONTH_W { w: self } + } + #[doc = "Bits 26:31 - Year"] + #[inline(always)] + pub fn year(&mut self) -> YEAR_W { + YEAR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2_ALARM Alarm n Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [alarm](index.html) module"] +pub struct ALARM_SPEC; +impl crate::RegisterSpec for ALARM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [alarm::R](R) reader structure"] +impl crate::Readable for ALARM_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [alarm::W](W) writer structure"] +impl crate::Writable for ALARM_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ALARM to value 0"] +impl crate::Resettable for ALARM_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/rtc/mode2/clock.rs b/pac/atsamc20j/src/rtc/mode2/clock.rs new file mode 100644 index 000000000000..3f364ff8e57b --- /dev/null +++ b/pac/atsamc20j/src/rtc/mode2/clock.rs @@ -0,0 +1,337 @@ +#[doc = "Register `CLOCK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CLOCK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SECOND` reader - Second"] +pub struct SECOND_R(crate::FieldReader); +impl SECOND_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SECOND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SECOND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SECOND` writer - Second"] +pub struct SECOND_W<'a> { + w: &'a mut W, +} +impl<'a> SECOND_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +#[doc = "Field `MINUTE` reader - Minute"] +pub struct MINUTE_R(crate::FieldReader); +impl MINUTE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MINUTE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MINUTE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MINUTE` writer - Minute"] +pub struct MINUTE_W<'a> { + w: &'a mut W, +} +impl<'a> MINUTE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 6)) | ((value as u32 & 0x3f) << 6); + self.w + } +} +#[doc = "Hour\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum HOUR_A { + #[doc = "0: AM when CLKREP in 12-hour"] + AM = 0, + #[doc = "16: PM when CLKREP in 12-hour"] + PM = 16, +} +impl From for u8 { + #[inline(always)] + fn from(variant: HOUR_A) -> Self { + variant as _ + } +} +#[doc = "Field `HOUR` reader - Hour"] +pub struct HOUR_R(crate::FieldReader); +impl HOUR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + HOUR_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(HOUR_A::AM), + 16 => Some(HOUR_A::PM), + _ => None, + } + } + #[doc = "Checks if the value of the field is `AM`"] + #[inline(always)] + pub fn is_am(&self) -> bool { + **self == HOUR_A::AM + } + #[doc = "Checks if the value of the field is `PM`"] + #[inline(always)] + pub fn is_pm(&self) -> bool { + **self == HOUR_A::PM + } +} +impl core::ops::Deref for HOUR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HOUR` writer - Hour"] +pub struct HOUR_W<'a> { + w: &'a mut W, +} +impl<'a> HOUR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: HOUR_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "AM when CLKREP in 12-hour"] + #[inline(always)] + pub fn am(self) -> &'a mut W { + self.variant(HOUR_A::AM) + } + #[doc = "PM when CLKREP in 12-hour"] + #[inline(always)] + pub fn pm(self) -> &'a mut W { + self.variant(HOUR_A::PM) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 12)) | ((value as u32 & 0x1f) << 12); + self.w + } +} +#[doc = "Field `DAY` reader - Day"] +pub struct DAY_R(crate::FieldReader); +impl DAY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DAY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DAY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DAY` writer - Day"] +pub struct DAY_W<'a> { + w: &'a mut W, +} +impl<'a> DAY_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 17)) | ((value as u32 & 0x1f) << 17); + self.w + } +} +#[doc = "Field `MONTH` reader - Month"] +pub struct MONTH_R(crate::FieldReader); +impl MONTH_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MONTH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MONTH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MONTH` writer - Month"] +pub struct MONTH_W<'a> { + w: &'a mut W, +} +impl<'a> MONTH_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 22)) | ((value as u32 & 0x0f) << 22); + self.w + } +} +#[doc = "Field `YEAR` reader - Year"] +pub struct YEAR_R(crate::FieldReader); +impl YEAR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + YEAR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for YEAR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `YEAR` writer - Year"] +pub struct YEAR_W<'a> { + w: &'a mut W, +} +impl<'a> YEAR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 26)) | ((value as u32 & 0x3f) << 26); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Second"] + #[inline(always)] + pub fn second(&self) -> SECOND_R { + SECOND_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:11 - Minute"] + #[inline(always)] + pub fn minute(&self) -> MINUTE_R { + MINUTE_R::new(((self.bits >> 6) & 0x3f) as u8) + } + #[doc = "Bits 12:16 - Hour"] + #[inline(always)] + pub fn hour(&self) -> HOUR_R { + HOUR_R::new(((self.bits >> 12) & 0x1f) as u8) + } + #[doc = "Bits 17:21 - Day"] + #[inline(always)] + pub fn day(&self) -> DAY_R { + DAY_R::new(((self.bits >> 17) & 0x1f) as u8) + } + #[doc = "Bits 22:25 - Month"] + #[inline(always)] + pub fn month(&self) -> MONTH_R { + MONTH_R::new(((self.bits >> 22) & 0x0f) as u8) + } + #[doc = "Bits 26:31 - Year"] + #[inline(always)] + pub fn year(&self) -> YEAR_R { + YEAR_R::new(((self.bits >> 26) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - Second"] + #[inline(always)] + pub fn second(&mut self) -> SECOND_W { + SECOND_W { w: self } + } + #[doc = "Bits 6:11 - Minute"] + #[inline(always)] + pub fn minute(&mut self) -> MINUTE_W { + MINUTE_W { w: self } + } + #[doc = "Bits 12:16 - Hour"] + #[inline(always)] + pub fn hour(&mut self) -> HOUR_W { + HOUR_W { w: self } + } + #[doc = "Bits 17:21 - Day"] + #[inline(always)] + pub fn day(&mut self) -> DAY_W { + DAY_W { w: self } + } + #[doc = "Bits 22:25 - Month"] + #[inline(always)] + pub fn month(&mut self) -> MONTH_W { + MONTH_W { w: self } + } + #[doc = "Bits 26:31 - Year"] + #[inline(always)] + pub fn year(&mut self) -> YEAR_W { + YEAR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2 Clock Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clock](index.html) module"] +pub struct CLOCK_SPEC; +impl crate::RegisterSpec for CLOCK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [clock::R](R) reader structure"] +impl crate::Readable for CLOCK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [clock::W](W) writer structure"] +impl crate::Writable for CLOCK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CLOCK to value 0"] +impl crate::Resettable for CLOCK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/rtc/mode2/ctrla.rs b/pac/atsamc20j/src/rtc/mode2/ctrla.rs new file mode 100644 index 000000000000..fc4bfda16bd8 --- /dev/null +++ b/pac/atsamc20j/src/rtc/mode2/ctrla.rs @@ -0,0 +1,616 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: Mode 0: 32-bit Counter"] + COUNT32 = 0, + #[doc = "1: Mode 1: 16-bit Counter"] + COUNT16 = 1, + #[doc = "2: Mode 2: Clock/Calendar"] + CLOCK = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::COUNT32), + 1 => Some(MODE_A::COUNT16), + 2 => Some(MODE_A::CLOCK), + _ => None, + } + } + #[doc = "Checks if the value of the field is `COUNT32`"] + #[inline(always)] + pub fn is_count32(&self) -> bool { + **self == MODE_A::COUNT32 + } + #[doc = "Checks if the value of the field is `COUNT16`"] + #[inline(always)] + pub fn is_count16(&self) -> bool { + **self == MODE_A::COUNT16 + } + #[doc = "Checks if the value of the field is `CLOCK`"] + #[inline(always)] + pub fn is_clock(&self) -> bool { + **self == MODE_A::CLOCK + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Mode 0: 32-bit Counter"] + #[inline(always)] + pub fn count32(self) -> &'a mut W { + self.variant(MODE_A::COUNT32) + } + #[doc = "Mode 1: 16-bit Counter"] + #[inline(always)] + pub fn count16(self) -> &'a mut W { + self.variant(MODE_A::COUNT16) + } + #[doc = "Mode 2: Clock/Calendar"] + #[inline(always)] + pub fn clock(self) -> &'a mut W { + self.variant(MODE_A::CLOCK) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u16 & 0x03) << 2); + self.w + } +} +#[doc = "Field `CLKREP` reader - Clock Representation"] +pub struct CLKREP_R(crate::FieldReader); +impl CLKREP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKREP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKREP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKREP` writer - Clock Representation"] +pub struct CLKREP_W<'a> { + w: &'a mut W, +} +impl<'a> CLKREP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `MATCHCLR` reader - Clear on Match"] +pub struct MATCHCLR_R(crate::FieldReader); +impl MATCHCLR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MATCHCLR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MATCHCLR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MATCHCLR` writer - Clear on Match"] +pub struct MATCHCLR_W<'a> { + w: &'a mut W, +} +impl<'a> MATCHCLR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: CLK_RTC_CNT = GCLK_RTC/1"] + OFF = 0, + #[doc = "1: CLK_RTC_CNT = GCLK_RTC/1"] + DIV1 = 1, + #[doc = "2: CLK_RTC_CNT = GCLK_RTC/2"] + DIV2 = 2, + #[doc = "3: CLK_RTC_CNT = GCLK_RTC/4"] + DIV4 = 3, + #[doc = "4: CLK_RTC_CNT = GCLK_RTC/8"] + DIV8 = 4, + #[doc = "5: CLK_RTC_CNT = GCLK_RTC/16"] + DIV16 = 5, + #[doc = "6: CLK_RTC_CNT = GCLK_RTC/32"] + DIV32 = 6, + #[doc = "7: CLK_RTC_CNT = GCLK_RTC/64"] + DIV64 = 7, + #[doc = "8: CLK_RTC_CNT = GCLK_RTC/128"] + DIV128 = 8, + #[doc = "9: CLK_RTC_CNT = GCLK_RTC/256"] + DIV256 = 9, + #[doc = "10: CLK_RTC_CNT = GCLK_RTC/512"] + DIV512 = 10, + #[doc = "11: CLK_RTC_CNT = GCLK_RTC/1024"] + DIV1024 = 11, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCALER_A::OFF), + 1 => Some(PRESCALER_A::DIV1), + 2 => Some(PRESCALER_A::DIV2), + 3 => Some(PRESCALER_A::DIV4), + 4 => Some(PRESCALER_A::DIV8), + 5 => Some(PRESCALER_A::DIV16), + 6 => Some(PRESCALER_A::DIV32), + 7 => Some(PRESCALER_A::DIV64), + 8 => Some(PRESCALER_A::DIV128), + 9 => Some(PRESCALER_A::DIV256), + 10 => Some(PRESCALER_A::DIV512), + 11 => Some(PRESCALER_A::DIV1024), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == PRESCALER_A::OFF + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == PRESCALER_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == PRESCALER_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == PRESCALER_A::DIV128 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV512`"] + #[inline(always)] + pub fn is_div512(&self) -> bool { + **self == PRESCALER_A::DIV512 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PRESCALER_A::DIV1024 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(PRESCALER_A::OFF) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV32) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV128) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/512"] + #[inline(always)] + pub fn div512(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV512) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 8)) | ((value as u16 & 0x0f) << 8); + self.w + } +} +#[doc = "Field `CLOCKSYNC` reader - Clock Read Synchronization Enable"] +pub struct CLOCKSYNC_R(crate::FieldReader); +impl CLOCKSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLOCKSYNC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLOCKSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLOCKSYNC` writer - Clock Read Synchronization Enable"] +pub struct CLOCKSYNC_W<'a> { + w: &'a mut W, +} +impl<'a> CLOCKSYNC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:3 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bit 6 - Clock Representation"] + #[inline(always)] + pub fn clkrep(&self) -> CLKREP_R { + CLKREP_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Clear on Match"] + #[inline(always)] + pub fn matchclr(&self) -> MATCHCLR_R { + MATCHCLR_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:11 - Prescaler"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 15 - Clock Read Synchronization Enable"] + #[inline(always)] + pub fn clocksync(&self) -> CLOCKSYNC_R { + CLOCKSYNC_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:3 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 6 - Clock Representation"] + #[inline(always)] + pub fn clkrep(&mut self) -> CLKREP_W { + CLKREP_W { w: self } + } + #[doc = "Bit 7 - Clear on Match"] + #[inline(always)] + pub fn matchclr(&mut self) -> MATCHCLR_W { + MATCHCLR_W { w: self } + } + #[doc = "Bits 8:11 - Prescaler"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Bit 15 - Clock Read Synchronization Enable"] + #[inline(always)] + pub fn clocksync(&mut self) -> CLOCKSYNC_W { + CLOCKSYNC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2 Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/rtc/mode2/dbgctrl.rs b/pac/atsamc20j/src/rtc/mode2/dbgctrl.rs new file mode 100644 index 000000000000..0383e70d0429 --- /dev/null +++ b/pac/atsamc20j/src/rtc/mode2/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Run During Debug"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Run During Debug"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/rtc/mode2/evctrl.rs b/pac/atsamc20j/src/rtc/mode2/evctrl.rs new file mode 100644 index 000000000000..17bc3da4a79e --- /dev/null +++ b/pac/atsamc20j/src/rtc/mode2/evctrl.rs @@ -0,0 +1,536 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PEREO0` reader - Periodic Interval 0 Event Output Enable"] +pub struct PEREO0_R(crate::FieldReader); +impl PEREO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO0` writer - Periodic Interval 0 Event Output Enable"] +pub struct PEREO0_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `PEREO1` reader - Periodic Interval 1 Event Output Enable"] +pub struct PEREO1_R(crate::FieldReader); +impl PEREO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO1` writer - Periodic Interval 1 Event Output Enable"] +pub struct PEREO1_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PEREO2` reader - Periodic Interval 2 Event Output Enable"] +pub struct PEREO2_R(crate::FieldReader); +impl PEREO2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO2` writer - Periodic Interval 2 Event Output Enable"] +pub struct PEREO2_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PEREO3` reader - Periodic Interval 3 Event Output Enable"] +pub struct PEREO3_R(crate::FieldReader); +impl PEREO3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO3` writer - Periodic Interval 3 Event Output Enable"] +pub struct PEREO3_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PEREO4` reader - Periodic Interval 4 Event Output Enable"] +pub struct PEREO4_R(crate::FieldReader); +impl PEREO4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO4` writer - Periodic Interval 4 Event Output Enable"] +pub struct PEREO4_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PEREO5` reader - Periodic Interval 5 Event Output Enable"] +pub struct PEREO5_R(crate::FieldReader); +impl PEREO5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO5` writer - Periodic Interval 5 Event Output Enable"] +pub struct PEREO5_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PEREO6` reader - Periodic Interval 6 Event Output Enable"] +pub struct PEREO6_R(crate::FieldReader); +impl PEREO6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO6` writer - Periodic Interval 6 Event Output Enable"] +pub struct PEREO6_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PEREO7` reader - Periodic Interval 7 Event Output Enable"] +pub struct PEREO7_R(crate::FieldReader); +impl PEREO7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO7` writer - Periodic Interval 7 Event Output Enable"] +pub struct PEREO7_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `ALARMEO0` reader - Alarm 0 Event Output Enable"] +pub struct ALARMEO0_R(crate::FieldReader); +impl ALARMEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALARMEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALARMEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALARMEO0` writer - Alarm 0 Event Output Enable"] +pub struct ALARMEO0_W<'a> { + w: &'a mut W, +} +impl<'a> ALARMEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `OVFEO` reader - Overflow Event Output Enable"] +pub struct OVFEO_R(crate::FieldReader); +impl OVFEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVFEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVFEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVFEO` writer - Overflow Event Output Enable"] +pub struct OVFEO_W<'a> { + w: &'a mut W, +} +impl<'a> OVFEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Event Output Enable"] + #[inline(always)] + pub fn pereo0(&self) -> PEREO0_R { + PEREO0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Event Output Enable"] + #[inline(always)] + pub fn pereo1(&self) -> PEREO1_R { + PEREO1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Event Output Enable"] + #[inline(always)] + pub fn pereo2(&self) -> PEREO2_R { + PEREO2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Event Output Enable"] + #[inline(always)] + pub fn pereo3(&self) -> PEREO3_R { + PEREO3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Event Output Enable"] + #[inline(always)] + pub fn pereo4(&self) -> PEREO4_R { + PEREO4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Event Output Enable"] + #[inline(always)] + pub fn pereo5(&self) -> PEREO5_R { + PEREO5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Event Output Enable"] + #[inline(always)] + pub fn pereo6(&self) -> PEREO6_R { + PEREO6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Event Output Enable"] + #[inline(always)] + pub fn pereo7(&self) -> PEREO7_R { + PEREO7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Alarm 0 Event Output Enable"] + #[inline(always)] + pub fn alarmeo0(&self) -> ALARMEO0_R { + ALARMEO0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&self) -> OVFEO_R { + OVFEO_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Event Output Enable"] + #[inline(always)] + pub fn pereo0(&mut self) -> PEREO0_W { + PEREO0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1 Event Output Enable"] + #[inline(always)] + pub fn pereo1(&mut self) -> PEREO1_W { + PEREO1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2 Event Output Enable"] + #[inline(always)] + pub fn pereo2(&mut self) -> PEREO2_W { + PEREO2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3 Event Output Enable"] + #[inline(always)] + pub fn pereo3(&mut self) -> PEREO3_W { + PEREO3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4 Event Output Enable"] + #[inline(always)] + pub fn pereo4(&mut self) -> PEREO4_W { + PEREO4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5 Event Output Enable"] + #[inline(always)] + pub fn pereo5(&mut self) -> PEREO5_W { + PEREO5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6 Event Output Enable"] + #[inline(always)] + pub fn pereo6(&mut self) -> PEREO6_W { + PEREO6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7 Event Output Enable"] + #[inline(always)] + pub fn pereo7(&mut self) -> PEREO7_W { + PEREO7_W { w: self } + } + #[doc = "Bit 8 - Alarm 0 Event Output Enable"] + #[inline(always)] + pub fn alarmeo0(&mut self) -> ALARMEO0_W { + ALARMEO0_W { w: self } + } + #[doc = "Bit 15 - Overflow Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&mut self) -> OVFEO_W { + OVFEO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2 Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/rtc/mode2/freqcorr.rs b/pac/atsamc20j/src/rtc/mode2/freqcorr.rs new file mode 100644 index 000000000000..043ba6f88eb2 --- /dev/null +++ b/pac/atsamc20j/src/rtc/mode2/freqcorr.rs @@ -0,0 +1,150 @@ +#[doc = "Register `FREQCORR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FREQCORR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `VALUE` reader - Correction Value"] +pub struct VALUE_R(crate::FieldReader); +impl VALUE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + VALUE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VALUE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VALUE` writer - Correction Value"] +pub struct VALUE_W<'a> { + w: &'a mut W, +} +impl<'a> VALUE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x7f) | (value as u8 & 0x7f); + self.w + } +} +#[doc = "Field `SIGN` reader - Correction Sign"] +pub struct SIGN_R(crate::FieldReader); +impl SIGN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SIGN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SIGN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SIGN` writer - Correction Sign"] +pub struct SIGN_W<'a> { + w: &'a mut W, +} +impl<'a> SIGN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bits 0:6 - Correction Value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bit 7 - Correction Sign"] + #[inline(always)] + pub fn sign(&self) -> SIGN_R { + SIGN_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:6 - Correction Value"] + #[inline(always)] + pub fn value(&mut self) -> VALUE_W { + VALUE_W { w: self } + } + #[doc = "Bit 7 - Correction Sign"] + #[inline(always)] + pub fn sign(&mut self) -> SIGN_W { + SIGN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Frequency Correction\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [freqcorr](index.html) module"] +pub struct FREQCORR_SPEC; +impl crate::RegisterSpec for FREQCORR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [freqcorr::R](R) reader structure"] +impl crate::Readable for FREQCORR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [freqcorr::W](W) writer structure"] +impl crate::Writable for FREQCORR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets FREQCORR to value 0"] +impl crate::Resettable for FREQCORR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/rtc/mode2/intenclr.rs b/pac/atsamc20j/src/rtc/mode2/intenclr.rs new file mode 100644 index 000000000000..84aa17f78a0e --- /dev/null +++ b/pac/atsamc20j/src/rtc/mode2/intenclr.rs @@ -0,0 +1,536 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER0` reader - Periodic Interval 0 Interrupt Enable"] +pub struct PER0_R(crate::FieldReader); +impl PER0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER0` writer - Periodic Interval 0 Interrupt Enable"] +pub struct PER0_W<'a> { + w: &'a mut W, +} +impl<'a> PER0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PER1` reader - Periodic Interval 1 Interrupt Enable"] +pub struct PER1_R(crate::FieldReader); +impl PER1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER1` writer - Periodic Interval 1 Interrupt Enable"] +pub struct PER1_W<'a> { + w: &'a mut W, +} +impl<'a> PER1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PER2` reader - Periodic Interval 2 Interrupt Enable"] +pub struct PER2_R(crate::FieldReader); +impl PER2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER2` writer - Periodic Interval 2 Interrupt Enable"] +pub struct PER2_W<'a> { + w: &'a mut W, +} +impl<'a> PER2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PER3` reader - Periodic Interval 3 Interrupt Enable"] +pub struct PER3_R(crate::FieldReader); +impl PER3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER3` writer - Periodic Interval 3 Interrupt Enable"] +pub struct PER3_W<'a> { + w: &'a mut W, +} +impl<'a> PER3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PER4` reader - Periodic Interval 4 Interrupt Enable"] +pub struct PER4_R(crate::FieldReader); +impl PER4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER4` writer - Periodic Interval 4 Interrupt Enable"] +pub struct PER4_W<'a> { + w: &'a mut W, +} +impl<'a> PER4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PER5` reader - Periodic Interval 5 Interrupt Enable"] +pub struct PER5_R(crate::FieldReader); +impl PER5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER5` writer - Periodic Interval 5 Interrupt Enable"] +pub struct PER5_W<'a> { + w: &'a mut W, +} +impl<'a> PER5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PER6` reader - Periodic Interval 6 Interrupt Enable"] +pub struct PER6_R(crate::FieldReader); +impl PER6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER6` writer - Periodic Interval 6 Interrupt Enable"] +pub struct PER6_W<'a> { + w: &'a mut W, +} +impl<'a> PER6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PER7` reader - Periodic Interval 7 Interrupt Enable"] +pub struct PER7_R(crate::FieldReader); +impl PER7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER7` writer - Periodic Interval 7 Interrupt Enable"] +pub struct PER7_W<'a> { + w: &'a mut W, +} +impl<'a> PER7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `ALARM0` reader - Alarm 0 Interrupt Enable"] +pub struct ALARM0_R(crate::FieldReader); +impl ALARM0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALARM0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALARM0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALARM0` writer - Alarm 0 Interrupt Enable"] +pub struct ALARM0_W<'a> { + w: &'a mut W, +} +impl<'a> ALARM0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + pub fn per0(&self) -> PER0_R { + PER0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + pub fn per1(&self) -> PER1_R { + PER1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + pub fn per2(&self) -> PER2_R { + PER2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + pub fn per3(&self) -> PER3_R { + PER3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + pub fn per4(&self) -> PER4_R { + PER4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + pub fn per5(&self) -> PER5_R { + PER5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + pub fn per6(&self) -> PER6_R { + PER6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + pub fn per7(&self) -> PER7_R { + PER7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Alarm 0 Interrupt Enable"] + #[inline(always)] + pub fn alarm0(&self) -> ALARM0_R { + ALARM0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + pub fn per0(&mut self) -> PER0_W { + PER0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + pub fn per1(&mut self) -> PER1_W { + PER1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + pub fn per2(&mut self) -> PER2_W { + PER2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + pub fn per3(&mut self) -> PER3_W { + PER3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + pub fn per4(&mut self) -> PER4_W { + PER4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + pub fn per5(&mut self) -> PER5_W { + PER5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + pub fn per6(&mut self) -> PER6_W { + PER6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + pub fn per7(&mut self) -> PER7_W { + PER7_W { w: self } + } + #[doc = "Bit 8 - Alarm 0 Interrupt Enable"] + #[inline(always)] + pub fn alarm0(&mut self) -> ALARM0_W { + ALARM0_W { w: self } + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2 Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/rtc/mode2/intenset.rs b/pac/atsamc20j/src/rtc/mode2/intenset.rs new file mode 100644 index 000000000000..a41687fa1ee5 --- /dev/null +++ b/pac/atsamc20j/src/rtc/mode2/intenset.rs @@ -0,0 +1,536 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER0` reader - Periodic Interval 0 Enable"] +pub struct PER0_R(crate::FieldReader); +impl PER0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER0` writer - Periodic Interval 0 Enable"] +pub struct PER0_W<'a> { + w: &'a mut W, +} +impl<'a> PER0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PER1` reader - Periodic Interval 1 Enable"] +pub struct PER1_R(crate::FieldReader); +impl PER1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER1` writer - Periodic Interval 1 Enable"] +pub struct PER1_W<'a> { + w: &'a mut W, +} +impl<'a> PER1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PER2` reader - Periodic Interval 2 Enable"] +pub struct PER2_R(crate::FieldReader); +impl PER2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER2` writer - Periodic Interval 2 Enable"] +pub struct PER2_W<'a> { + w: &'a mut W, +} +impl<'a> PER2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PER3` reader - Periodic Interval 3 Enable"] +pub struct PER3_R(crate::FieldReader); +impl PER3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER3` writer - Periodic Interval 3 Enable"] +pub struct PER3_W<'a> { + w: &'a mut W, +} +impl<'a> PER3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PER4` reader - Periodic Interval 4 Enable"] +pub struct PER4_R(crate::FieldReader); +impl PER4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER4` writer - Periodic Interval 4 Enable"] +pub struct PER4_W<'a> { + w: &'a mut W, +} +impl<'a> PER4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PER5` reader - Periodic Interval 5 Enable"] +pub struct PER5_R(crate::FieldReader); +impl PER5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER5` writer - Periodic Interval 5 Enable"] +pub struct PER5_W<'a> { + w: &'a mut W, +} +impl<'a> PER5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PER6` reader - Periodic Interval 6 Enable"] +pub struct PER6_R(crate::FieldReader); +impl PER6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER6` writer - Periodic Interval 6 Enable"] +pub struct PER6_W<'a> { + w: &'a mut W, +} +impl<'a> PER6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PER7` reader - Periodic Interval 7 Enable"] +pub struct PER7_R(crate::FieldReader); +impl PER7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER7` writer - Periodic Interval 7 Enable"] +pub struct PER7_W<'a> { + w: &'a mut W, +} +impl<'a> PER7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `ALARM0` reader - Alarm 0 Interrupt Enable"] +pub struct ALARM0_R(crate::FieldReader); +impl ALARM0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALARM0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALARM0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALARM0` writer - Alarm 0 Interrupt Enable"] +pub struct ALARM0_W<'a> { + w: &'a mut W, +} +impl<'a> ALARM0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Enable"] + #[inline(always)] + pub fn per0(&self) -> PER0_R { + PER0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Enable"] + #[inline(always)] + pub fn per1(&self) -> PER1_R { + PER1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Enable"] + #[inline(always)] + pub fn per2(&self) -> PER2_R { + PER2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Enable"] + #[inline(always)] + pub fn per3(&self) -> PER3_R { + PER3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Enable"] + #[inline(always)] + pub fn per4(&self) -> PER4_R { + PER4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Enable"] + #[inline(always)] + pub fn per5(&self) -> PER5_R { + PER5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Enable"] + #[inline(always)] + pub fn per6(&self) -> PER6_R { + PER6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Enable"] + #[inline(always)] + pub fn per7(&self) -> PER7_R { + PER7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Alarm 0 Interrupt Enable"] + #[inline(always)] + pub fn alarm0(&self) -> ALARM0_R { + ALARM0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Enable"] + #[inline(always)] + pub fn per0(&mut self) -> PER0_W { + PER0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1 Enable"] + #[inline(always)] + pub fn per1(&mut self) -> PER1_W { + PER1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2 Enable"] + #[inline(always)] + pub fn per2(&mut self) -> PER2_W { + PER2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3 Enable"] + #[inline(always)] + pub fn per3(&mut self) -> PER3_W { + PER3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4 Enable"] + #[inline(always)] + pub fn per4(&mut self) -> PER4_W { + PER4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5 Enable"] + #[inline(always)] + pub fn per5(&mut self) -> PER5_W { + PER5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6 Enable"] + #[inline(always)] + pub fn per6(&mut self) -> PER6_W { + PER6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7 Enable"] + #[inline(always)] + pub fn per7(&mut self) -> PER7_W { + PER7_W { w: self } + } + #[doc = "Bit 8 - Alarm 0 Interrupt Enable"] + #[inline(always)] + pub fn alarm0(&mut self) -> ALARM0_W { + ALARM0_W { w: self } + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2 Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/rtc/mode2/intflag.rs b/pac/atsamc20j/src/rtc/mode2/intflag.rs new file mode 100644 index 000000000000..8de0f3efd1d0 --- /dev/null +++ b/pac/atsamc20j/src/rtc/mode2/intflag.rs @@ -0,0 +1,536 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER0` reader - Periodic Interval 0"] +pub struct PER0_R(crate::FieldReader); +impl PER0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER0` writer - Periodic Interval 0"] +pub struct PER0_W<'a> { + w: &'a mut W, +} +impl<'a> PER0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PER1` reader - Periodic Interval 1"] +pub struct PER1_R(crate::FieldReader); +impl PER1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER1` writer - Periodic Interval 1"] +pub struct PER1_W<'a> { + w: &'a mut W, +} +impl<'a> PER1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PER2` reader - Periodic Interval 2"] +pub struct PER2_R(crate::FieldReader); +impl PER2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER2` writer - Periodic Interval 2"] +pub struct PER2_W<'a> { + w: &'a mut W, +} +impl<'a> PER2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PER3` reader - Periodic Interval 3"] +pub struct PER3_R(crate::FieldReader); +impl PER3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER3` writer - Periodic Interval 3"] +pub struct PER3_W<'a> { + w: &'a mut W, +} +impl<'a> PER3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PER4` reader - Periodic Interval 4"] +pub struct PER4_R(crate::FieldReader); +impl PER4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER4` writer - Periodic Interval 4"] +pub struct PER4_W<'a> { + w: &'a mut W, +} +impl<'a> PER4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PER5` reader - Periodic Interval 5"] +pub struct PER5_R(crate::FieldReader); +impl PER5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER5` writer - Periodic Interval 5"] +pub struct PER5_W<'a> { + w: &'a mut W, +} +impl<'a> PER5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PER6` reader - Periodic Interval 6"] +pub struct PER6_R(crate::FieldReader); +impl PER6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER6` writer - Periodic Interval 6"] +pub struct PER6_W<'a> { + w: &'a mut W, +} +impl<'a> PER6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PER7` reader - Periodic Interval 7"] +pub struct PER7_R(crate::FieldReader); +impl PER7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER7` writer - Periodic Interval 7"] +pub struct PER7_W<'a> { + w: &'a mut W, +} +impl<'a> PER7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `ALARM0` reader - Alarm 0"] +pub struct ALARM0_R(crate::FieldReader); +impl ALARM0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALARM0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALARM0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALARM0` writer - Alarm 0"] +pub struct ALARM0_W<'a> { + w: &'a mut W, +} +impl<'a> ALARM0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0"] + #[inline(always)] + pub fn per0(&self) -> PER0_R { + PER0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1"] + #[inline(always)] + pub fn per1(&self) -> PER1_R { + PER1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2"] + #[inline(always)] + pub fn per2(&self) -> PER2_R { + PER2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3"] + #[inline(always)] + pub fn per3(&self) -> PER3_R { + PER3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4"] + #[inline(always)] + pub fn per4(&self) -> PER4_R { + PER4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5"] + #[inline(always)] + pub fn per5(&self) -> PER5_R { + PER5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6"] + #[inline(always)] + pub fn per6(&self) -> PER6_R { + PER6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7"] + #[inline(always)] + pub fn per7(&self) -> PER7_R { + PER7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Alarm 0"] + #[inline(always)] + pub fn alarm0(&self) -> ALARM0_R { + ALARM0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0"] + #[inline(always)] + pub fn per0(&mut self) -> PER0_W { + PER0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1"] + #[inline(always)] + pub fn per1(&mut self) -> PER1_W { + PER1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2"] + #[inline(always)] + pub fn per2(&mut self) -> PER2_W { + PER2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3"] + #[inline(always)] + pub fn per3(&mut self) -> PER3_W { + PER3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4"] + #[inline(always)] + pub fn per4(&mut self) -> PER4_W { + PER4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5"] + #[inline(always)] + pub fn per5(&mut self) -> PER5_W { + PER5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6"] + #[inline(always)] + pub fn per6(&mut self) -> PER6_W { + PER6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7"] + #[inline(always)] + pub fn per7(&mut self) -> PER7_W { + PER7_W { w: self } + } + #[doc = "Bit 8 - Alarm 0"] + #[inline(always)] + pub fn alarm0(&mut self) -> ALARM0_W { + ALARM0_W { w: self } + } + #[doc = "Bit 15 - Overflow"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2 Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/rtc/mode2/mask.rs b/pac/atsamc20j/src/rtc/mode2/mask.rs new file mode 100644 index 000000000000..53e0bb491a62 --- /dev/null +++ b/pac/atsamc20j/src/rtc/mode2/mask.rs @@ -0,0 +1,217 @@ +#[doc = "Register `MASK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MASK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Alarm Mask Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SEL_A { + #[doc = "0: Alarm Disabled"] + OFF = 0, + #[doc = "1: Match seconds only"] + SS = 1, + #[doc = "2: Match seconds and minutes only"] + MMSS = 2, + #[doc = "3: Match seconds, minutes, and hours only"] + HHMMSS = 3, + #[doc = "4: Match seconds, minutes, hours, and days only"] + DDHHMMSS = 4, + #[doc = "5: Match seconds, minutes, hours, days, and months only"] + MMDDHHMMSS = 5, + #[doc = "6: Match seconds, minutes, hours, days, months, and years"] + YYMMDDHHMMSS = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `SEL` reader - Alarm Mask Selection"] +pub struct SEL_R(crate::FieldReader); +impl SEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEL_A::OFF), + 1 => Some(SEL_A::SS), + 2 => Some(SEL_A::MMSS), + 3 => Some(SEL_A::HHMMSS), + 4 => Some(SEL_A::DDHHMMSS), + 5 => Some(SEL_A::MMDDHHMMSS), + 6 => Some(SEL_A::YYMMDDHHMMSS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == SEL_A::OFF + } + #[doc = "Checks if the value of the field is `SS`"] + #[inline(always)] + pub fn is_ss(&self) -> bool { + **self == SEL_A::SS + } + #[doc = "Checks if the value of the field is `MMSS`"] + #[inline(always)] + pub fn is_mmss(&self) -> bool { + **self == SEL_A::MMSS + } + #[doc = "Checks if the value of the field is `HHMMSS`"] + #[inline(always)] + pub fn is_hhmmss(&self) -> bool { + **self == SEL_A::HHMMSS + } + #[doc = "Checks if the value of the field is `DDHHMMSS`"] + #[inline(always)] + pub fn is_ddhhmmss(&self) -> bool { + **self == SEL_A::DDHHMMSS + } + #[doc = "Checks if the value of the field is `MMDDHHMMSS`"] + #[inline(always)] + pub fn is_mmddhhmmss(&self) -> bool { + **self == SEL_A::MMDDHHMMSS + } + #[doc = "Checks if the value of the field is `YYMMDDHHMMSS`"] + #[inline(always)] + pub fn is_yymmddhhmmss(&self) -> bool { + **self == SEL_A::YYMMDDHHMMSS + } +} +impl core::ops::Deref for SEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEL` writer - Alarm Mask Selection"] +pub struct SEL_W<'a> { + w: &'a mut W, +} +impl<'a> SEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SEL_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Alarm Disabled"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(SEL_A::OFF) + } + #[doc = "Match seconds only"] + #[inline(always)] + pub fn ss(self) -> &'a mut W { + self.variant(SEL_A::SS) + } + #[doc = "Match seconds and minutes only"] + #[inline(always)] + pub fn mmss(self) -> &'a mut W { + self.variant(SEL_A::MMSS) + } + #[doc = "Match seconds, minutes, and hours only"] + #[inline(always)] + pub fn hhmmss(self) -> &'a mut W { + self.variant(SEL_A::HHMMSS) + } + #[doc = "Match seconds, minutes, hours, and days only"] + #[inline(always)] + pub fn ddhhmmss(self) -> &'a mut W { + self.variant(SEL_A::DDHHMMSS) + } + #[doc = "Match seconds, minutes, hours, days, and months only"] + #[inline(always)] + pub fn mmddhhmmss(self) -> &'a mut W { + self.variant(SEL_A::MMDDHHMMSS) + } + #[doc = "Match seconds, minutes, hours, days, months, and years"] + #[inline(always)] + pub fn yymmddhhmmss(self) -> &'a mut W { + self.variant(SEL_A::YYMMDDHHMMSS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Alarm Mask Selection"] + #[inline(always)] + pub fn sel(&self) -> SEL_R { + SEL_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Alarm Mask Selection"] + #[inline(always)] + pub fn sel(&mut self) -> SEL_W { + SEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2_ALARM Alarm n Mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mask](index.html) module"] +pub struct MASK_SPEC; +impl crate::RegisterSpec for MASK_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [mask::R](R) reader structure"] +impl crate::Readable for MASK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [mask::W](W) writer structure"] +impl crate::Writable for MASK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets MASK to value 0"] +impl crate::Resettable for MASK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/rtc/mode2/syncbusy.rs b/pac/atsamc20j/src/rtc/mode2/syncbusy.rs new file mode 100644 index 000000000000..b517ee5ae8b2 --- /dev/null +++ b/pac/atsamc20j/src/rtc/mode2/syncbusy.rs @@ -0,0 +1,173 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Bit Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - Enable Bit Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FREQCORR` reader - FREQCORR Register Busy"] +pub struct FREQCORR_R(crate::FieldReader); +impl FREQCORR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FREQCORR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FREQCORR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLOCK` reader - CLOCK Register Busy"] +pub struct CLOCK_R(crate::FieldReader); +impl CLOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALARM0` reader - ALARM 0 Register Busy"] +pub struct ALARM0_R(crate::FieldReader); +impl ALARM0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALARM0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALARM0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MASK0` reader - MASK 0 Register Busy"] +pub struct MASK0_R(crate::FieldReader); +impl MASK0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MASK0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MASK0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLOCKSYNC` reader - Clock Read Synchronization Enable Bit Busy"] +pub struct CLOCKSYNC_R(crate::FieldReader); +impl CLOCKSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLOCKSYNC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLOCKSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Bit Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable Bit Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - FREQCORR Register Busy"] + #[inline(always)] + pub fn freqcorr(&self) -> FREQCORR_R { + FREQCORR_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - CLOCK Register Busy"] + #[inline(always)] + pub fn clock(&self) -> CLOCK_R { + CLOCK_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 5 - ALARM 0 Register Busy"] + #[inline(always)] + pub fn alarm0(&self) -> ALARM0_R { + ALARM0_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 11 - MASK 0 Register Busy"] + #[inline(always)] + pub fn mask0(&self) -> MASK0_R { + MASK0_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 15 - Clock Read Synchronization Enable Bit Busy"] + #[inline(always)] + pub fn clocksync(&self) -> CLOCKSYNC_R { + CLOCKSYNC_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +#[doc = "MODE2 Synchronization Busy Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/sercom0.rs b/pac/atsamc20j/src/sercom0.rs new file mode 100644 index 000000000000..da7b62f750c6 --- /dev/null +++ b/pac/atsamc20j/src/sercom0.rs @@ -0,0 +1,327 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved_0_i2cm: [u8; 0x31], +} +impl RegisterBlock { + #[doc = "0x00..0x31 - USART INTERNAL CLOCK Mode"] + #[inline(always)] + pub fn usart_int(&self) -> &USART_INT { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const USART_INT) } + } + #[doc = "0x00..0x31 - USART EXTERNAL CLOCK Mode"] + #[inline(always)] + pub fn usart_ext(&self) -> &USART_EXT { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const USART_EXT) } + } + #[doc = "0x00..0x31 - SPI Master Mode"] + #[inline(always)] + pub fn spim(&self) -> &SPIM { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const SPIM) } + } + #[doc = "0x00..0x31 - SPI Slave Mode"] + #[inline(always)] + pub fn spis(&self) -> &SPIS { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const SPIS) } + } + #[doc = "0x00..0x29 - I2C Slave Mode"] + #[inline(always)] + pub fn i2cs(&self) -> &I2CS { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const I2CS) } + } + #[doc = "0x00..0x31 - I2C Master Mode"] + #[inline(always)] + pub fn i2cm(&self) -> &I2CM { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const I2CM) } + } +} +#[doc = r"Register block"] +#[repr(C)] +pub struct I2CM { + #[doc = "0x00 - I2CM Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - I2CM Control B"] + pub ctrlb: crate::Reg, + _reserved2: [u8; 0x04], + #[doc = "0x0c - I2CM Baud Rate"] + pub baud: crate::Reg, + _reserved3: [u8; 0x04], + #[doc = "0x14 - I2CM Interrupt Enable Clear"] + pub intenclr: crate::Reg, + _reserved4: [u8; 0x01], + #[doc = "0x16 - I2CM Interrupt Enable Set"] + pub intenset: crate::Reg, + _reserved5: [u8; 0x01], + #[doc = "0x18 - I2CM Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x1a - I2CM Status"] + pub status: crate::Reg, + #[doc = "0x1c - I2CM Synchronization Busy"] + pub syncbusy: crate::Reg, + _reserved8: [u8; 0x04], + #[doc = "0x24 - I2CM Address"] + pub addr: crate::Reg, + #[doc = "0x28 - I2CM Data"] + pub data: crate::Reg, + _reserved10: [u8; 0x07], + #[doc = "0x30 - I2CM Debug Control"] + pub dbgctrl: crate::Reg, +} +#[doc = r"Register block"] +#[doc = "I2C Master Mode"] +pub mod i2cm; +#[doc = r"Register block"] +#[repr(C)] +pub struct I2CS { + #[doc = "0x00 - I2CS Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - I2CS Control B"] + pub ctrlb: crate::Reg, + _reserved2: [u8; 0x0c], + #[doc = "0x14 - I2CS Interrupt Enable Clear"] + pub intenclr: crate::Reg, + _reserved3: [u8; 0x01], + #[doc = "0x16 - I2CS Interrupt Enable Set"] + pub intenset: crate::Reg, + _reserved4: [u8; 0x01], + #[doc = "0x18 - I2CS Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved5: [u8; 0x01], + #[doc = "0x1a - I2CS Status"] + pub status: crate::Reg, + #[doc = "0x1c - I2CS Synchronization Busy"] + pub syncbusy: crate::Reg, + _reserved7: [u8; 0x04], + #[doc = "0x24 - I2CS Address"] + pub addr: crate::Reg, + #[doc = "0x28 - I2CS Data"] + pub data: crate::Reg, +} +#[doc = r"Register block"] +#[doc = "I2C Slave Mode"] +pub mod i2cs; +#[doc = r"Register block"] +#[repr(C)] +pub struct SPIS { + #[doc = "0x00 - SPIS Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - SPIS Control B"] + pub ctrlb: crate::Reg, + _reserved2: [u8; 0x04], + #[doc = "0x0c - SPIS Baud Rate"] + pub baud: crate::Reg, + _reserved3: [u8; 0x07], + #[doc = "0x14 - SPIS Interrupt Enable Clear"] + pub intenclr: crate::Reg, + _reserved4: [u8; 0x01], + #[doc = "0x16 - SPIS Interrupt Enable Set"] + pub intenset: crate::Reg, + _reserved5: [u8; 0x01], + #[doc = "0x18 - SPIS Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x1a - SPIS Status"] + pub status: crate::Reg, + #[doc = "0x1c - SPIS Synchronization Busy"] + pub syncbusy: crate::Reg, + _reserved8: [u8; 0x04], + #[doc = "0x24 - SPIS Address"] + pub addr: crate::Reg, + #[doc = "0x28 - SPIS Data"] + pub data: crate::Reg, + _reserved10: [u8; 0x04], + #[doc = "0x30 - SPIS Debug Control"] + pub dbgctrl: crate::Reg, +} +#[doc = r"Register block"] +#[doc = "SPI Slave Mode"] +pub mod spis; +#[doc = r"Register block"] +#[repr(C)] +pub struct SPIM { + #[doc = "0x00 - SPIM Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - SPIM Control B"] + pub ctrlb: crate::Reg, + _reserved2: [u8; 0x04], + #[doc = "0x0c - SPIM Baud Rate"] + pub baud: crate::Reg, + _reserved3: [u8; 0x07], + #[doc = "0x14 - SPIM Interrupt Enable Clear"] + pub intenclr: crate::Reg, + _reserved4: [u8; 0x01], + #[doc = "0x16 - SPIM Interrupt Enable Set"] + pub intenset: crate::Reg, + _reserved5: [u8; 0x01], + #[doc = "0x18 - SPIM Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x1a - SPIM Status"] + pub status: crate::Reg, + #[doc = "0x1c - SPIM Synchronization Busy"] + pub syncbusy: crate::Reg, + _reserved8: [u8; 0x04], + #[doc = "0x24 - SPIM Address"] + pub addr: crate::Reg, + #[doc = "0x28 - SPIM Data"] + pub data: crate::Reg, + _reserved10: [u8; 0x04], + #[doc = "0x30 - SPIM Debug Control"] + pub dbgctrl: crate::Reg, +} +#[doc = r"Register block"] +#[doc = "SPI Master Mode"] +pub mod spim; +#[doc = r"Register block"] +#[repr(C)] +pub struct USART_EXT { + #[doc = "0x00 - USART_EXT Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - USART_EXT Control B"] + pub ctrlb: crate::Reg, + #[doc = "0x08 - USART_EXT Control C"] + pub ctrlc: crate::Reg, + _reserved_3_baud: [u8; 0x02], + #[doc = "0x0e - USART_EXT Receive Pulse Length"] + pub rxpl: crate::Reg, + _reserved5: [u8; 0x05], + #[doc = "0x14 - USART_EXT Interrupt Enable Clear"] + pub intenclr: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x16 - USART_EXT Interrupt Enable Set"] + pub intenset: crate::Reg, + _reserved7: [u8; 0x01], + #[doc = "0x18 - USART_EXT Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved8: [u8; 0x01], + #[doc = "0x1a - USART_EXT Status"] + pub status: crate::Reg, + #[doc = "0x1c - USART_EXT Synchronization Busy"] + pub syncbusy: crate::Reg, + _reserved10: [u8; 0x08], + #[doc = "0x28 - USART_EXT Data"] + pub data: crate::Reg, + _reserved11: [u8; 0x06], + #[doc = "0x30 - USART_EXT Debug Control"] + pub dbgctrl: crate::Reg, +} +impl USART_EXT { + #[doc = "0x0c - USART_EXT Baud Rate"] + #[inline(always)] + pub fn baud_usartfp_mode( + &self, + ) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } + #[doc = "0x0c - USART_EXT Baud Rate"] + #[inline(always)] + pub fn baud_fracfp_mode( + &self, + ) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } + #[doc = "0x0c - USART_EXT Baud Rate"] + #[inline(always)] + pub fn baud_frac_mode( + &self, + ) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } + #[doc = "0x0c - USART_EXT Baud Rate"] + #[inline(always)] + pub fn baud(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } +} +#[doc = r"Register block"] +#[doc = "USART EXTERNAL CLOCK Mode"] +pub mod usart_ext; +#[doc = r"Register block"] +#[repr(C)] +pub struct USART_INT { + #[doc = "0x00 - USART_INT Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - USART_INT Control B"] + pub ctrlb: crate::Reg, + #[doc = "0x08 - USART_INT Control C"] + pub ctrlc: crate::Reg, + _reserved_3_baud: [u8; 0x02], + #[doc = "0x0e - USART_INT Receive Pulse Length"] + pub rxpl: crate::Reg, + _reserved5: [u8; 0x05], + #[doc = "0x14 - USART_INT Interrupt Enable Clear"] + pub intenclr: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x16 - USART_INT Interrupt Enable Set"] + pub intenset: crate::Reg, + _reserved7: [u8; 0x01], + #[doc = "0x18 - USART_INT Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved8: [u8; 0x01], + #[doc = "0x1a - USART_INT Status"] + pub status: crate::Reg, + #[doc = "0x1c - USART_INT Synchronization Busy"] + pub syncbusy: crate::Reg, + _reserved10: [u8; 0x08], + #[doc = "0x28 - USART_INT Data"] + pub data: crate::Reg, + _reserved11: [u8; 0x06], + #[doc = "0x30 - USART_INT Debug Control"] + pub dbgctrl: crate::Reg, +} +impl USART_INT { + #[doc = "0x0c - USART_INT Baud Rate"] + #[inline(always)] + pub fn baud_usartfp_mode( + &self, + ) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } + #[doc = "0x0c - USART_INT Baud Rate"] + #[inline(always)] + pub fn baud_fracfp_mode( + &self, + ) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } + #[doc = "0x0c - USART_INT Baud Rate"] + #[inline(always)] + pub fn baud_frac_mode( + &self, + ) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } + #[doc = "0x0c - USART_INT Baud Rate"] + #[inline(always)] + pub fn baud(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } +} +#[doc = r"Register block"] +#[doc = "USART INTERNAL CLOCK Mode"] +pub mod usart_int; diff --git a/pac/atsamc20j/src/sercom0/i2cm.rs b/pac/atsamc20j/src/sercom0/i2cm.rs new file mode 100644 index 000000000000..8aa217da8b18 --- /dev/null +++ b/pac/atsamc20j/src/sercom0/i2cm.rs @@ -0,0 +1,44 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "I2CM Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "I2CM Control B"] +pub mod ctrlb; +#[doc = "BAUD register accessor: an alias for `Reg`"] +pub type BAUD = crate::Reg; +#[doc = "I2CM Baud Rate"] +pub mod baud; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "I2CM Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "I2CM Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "I2CM Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "I2CM Status"] +pub mod status; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "I2CM Synchronization Busy"] +pub mod syncbusy; +#[doc = "ADDR register accessor: an alias for `Reg`"] +pub type ADDR = crate::Reg; +#[doc = "I2CM Address"] +pub mod addr; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "I2CM Data"] +pub mod data; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "I2CM Debug Control"] +pub mod dbgctrl; diff --git a/pac/atsamc20j/src/sercom0/i2cm/addr.rs b/pac/atsamc20j/src/sercom0/i2cm/addr.rs new file mode 100644 index 000000000000..4efd19e824c6 --- /dev/null +++ b/pac/atsamc20j/src/sercom0/i2cm/addr.rs @@ -0,0 +1,281 @@ +#[doc = "Register `ADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ADDR` reader - Address Value"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - Address Value"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07ff) | (value as u32 & 0x07ff); + self.w + } +} +#[doc = "Field `LENEN` reader - Length Enable"] +pub struct LENEN_R(crate::FieldReader); +impl LENEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LENEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LENEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LENEN` writer - Length Enable"] +pub struct LENEN_W<'a> { + w: &'a mut W, +} +impl<'a> LENEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `HS` reader - High Speed Mode"] +pub struct HS_R(crate::FieldReader); +impl HS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HS` writer - High Speed Mode"] +pub struct HS_W<'a> { + w: &'a mut W, +} +impl<'a> HS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `TENBITEN` reader - Ten Bit Addressing Enable"] +pub struct TENBITEN_R(crate::FieldReader); +impl TENBITEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TENBITEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TENBITEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TENBITEN` writer - Ten Bit Addressing Enable"] +pub struct TENBITEN_W<'a> { + w: &'a mut W, +} +impl<'a> TENBITEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `LEN` reader - Length"] +pub struct LEN_R(crate::FieldReader); +impl LEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LEN` writer - Length"] +pub struct LEN_W<'a> { + w: &'a mut W, +} +impl<'a> LEN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:10 - Address Value"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new((self.bits & 0x07ff) as u16) + } + #[doc = "Bit 13 - Length Enable"] + #[inline(always)] + pub fn lenen(&self) -> LENEN_R { + LENEN_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - High Speed Mode"] + #[inline(always)] + pub fn hs(&self) -> HS_R { + HS_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Ten Bit Addressing Enable"] + #[inline(always)] + pub fn tenbiten(&self) -> TENBITEN_R { + TENBITEN_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:23 - Length"] + #[inline(always)] + pub fn len(&self) -> LEN_R { + LEN_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:10 - Address Value"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Bit 13 - Length Enable"] + #[inline(always)] + pub fn lenen(&mut self) -> LENEN_W { + LENEN_W { w: self } + } + #[doc = "Bit 14 - High Speed Mode"] + #[inline(always)] + pub fn hs(&mut self) -> HS_W { + HS_W { w: self } + } + #[doc = "Bit 15 - Ten Bit Addressing Enable"] + #[inline(always)] + pub fn tenbiten(&mut self) -> TENBITEN_W { + TENBITEN_W { w: self } + } + #[doc = "Bits 16:23 - Length"] + #[inline(always)] + pub fn len(&mut self) -> LEN_W { + LEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [addr](index.html) module"] +pub struct ADDR_SPEC; +impl crate::RegisterSpec for ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [addr::R](R) reader structure"] +impl crate::Readable for ADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [addr::W](W) writer structure"] +impl crate::Writable for ADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ADDR to value 0"] +impl crate::Resettable for ADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/sercom0/i2cm/baud.rs b/pac/atsamc20j/src/sercom0/i2cm/baud.rs new file mode 100644 index 000000000000..7c98d3b5b0de --- /dev/null +++ b/pac/atsamc20j/src/sercom0/i2cm/baud.rs @@ -0,0 +1,214 @@ +#[doc = "Register `BAUD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +#[doc = "Field `BAUDLOW` reader - Baud Rate Value Low"] +pub struct BAUDLOW_R(crate::FieldReader); +impl BAUDLOW_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BAUDLOW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUDLOW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUDLOW` writer - Baud Rate Value Low"] +pub struct BAUDLOW_W<'a> { + w: &'a mut W, +} +impl<'a> BAUDLOW_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +#[doc = "Field `HSBAUD` reader - High Speed Baud Rate Value"] +pub struct HSBAUD_R(crate::FieldReader); +impl HSBAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + HSBAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HSBAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HSBAUD` writer - High Speed Baud Rate Value"] +pub struct HSBAUD_W<'a> { + w: &'a mut W, +} +impl<'a> HSBAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +#[doc = "Field `HSBAUDLOW` reader - High Speed Baud Rate Value Low"] +pub struct HSBAUDLOW_R(crate::FieldReader); +impl HSBAUDLOW_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + HSBAUDLOW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HSBAUDLOW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HSBAUDLOW` writer - High Speed Baud Rate Value Low"] +pub struct HSBAUDLOW_W<'a> { + w: &'a mut W, +} +impl<'a> HSBAUDLOW_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 24)) | ((value as u32 & 0xff) << 24); + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Baud Rate Value Low"] + #[inline(always)] + pub fn baudlow(&self) -> BAUDLOW_R { + BAUDLOW_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - High Speed Baud Rate Value"] + #[inline(always)] + pub fn hsbaud(&self) -> HSBAUD_R { + HSBAUD_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - High Speed Baud Rate Value Low"] + #[inline(always)] + pub fn hsbaudlow(&self) -> HSBAUDLOW_R { + HSBAUDLOW_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Bits 8:15 - Baud Rate Value Low"] + #[inline(always)] + pub fn baudlow(&mut self) -> BAUDLOW_W { + BAUDLOW_W { w: self } + } + #[doc = "Bits 16:23 - High Speed Baud Rate Value"] + #[inline(always)] + pub fn hsbaud(&mut self) -> HSBAUD_W { + HSBAUD_W { w: self } + } + #[doc = "Bits 24:31 - High Speed Baud Rate Value Low"] + #[inline(always)] + pub fn hsbaudlow(&mut self) -> HSBAUDLOW_W { + HSBAUDLOW_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud](index.html) module"] +pub struct BAUD_SPEC; +impl crate::RegisterSpec for BAUD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [baud::R](R) reader structure"] +impl crate::Readable for BAUD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud::W](W) writer structure"] +impl crate::Writable for BAUD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD to value 0"] +impl crate::Resettable for BAUD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/sercom0/i2cm/ctrla.rs b/pac/atsamc20j/src/sercom0/i2cm/ctrla.rs new file mode 100644 index 000000000000..34fa668b7967 --- /dev/null +++ b/pac/atsamc20j/src/sercom0/i2cm/ctrla.rs @@ -0,0 +1,903 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: USART with external clock"] + USART_EXT_CLK = 0, + #[doc = "1: USART with internal clock"] + USART_INT_CLK = 1, + #[doc = "2: SPI in slave operation"] + SPI_SLAVE = 2, + #[doc = "3: SPI in master operation"] + SPI_MASTER = 3, + #[doc = "4: I2C slave operation"] + I2C_SLAVE = 4, + #[doc = "5: I2C master operation"] + I2C_MASTER = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::USART_EXT_CLK), + 1 => Some(MODE_A::USART_INT_CLK), + 2 => Some(MODE_A::SPI_SLAVE), + 3 => Some(MODE_A::SPI_MASTER), + 4 => Some(MODE_A::I2C_SLAVE), + 5 => Some(MODE_A::I2C_MASTER), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_EXT_CLK`"] + #[inline(always)] + pub fn is_usart_ext_clk(&self) -> bool { + **self == MODE_A::USART_EXT_CLK + } + #[doc = "Checks if the value of the field is `USART_INT_CLK`"] + #[inline(always)] + pub fn is_usart_int_clk(&self) -> bool { + **self == MODE_A::USART_INT_CLK + } + #[doc = "Checks if the value of the field is `SPI_SLAVE`"] + #[inline(always)] + pub fn is_spi_slave(&self) -> bool { + **self == MODE_A::SPI_SLAVE + } + #[doc = "Checks if the value of the field is `SPI_MASTER`"] + #[inline(always)] + pub fn is_spi_master(&self) -> bool { + **self == MODE_A::SPI_MASTER + } + #[doc = "Checks if the value of the field is `I2C_SLAVE`"] + #[inline(always)] + pub fn is_i2c_slave(&self) -> bool { + **self == MODE_A::I2C_SLAVE + } + #[doc = "Checks if the value of the field is `I2C_MASTER`"] + #[inline(always)] + pub fn is_i2c_master(&self) -> bool { + **self == MODE_A::I2C_MASTER + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART with external clock"] + #[inline(always)] + pub fn usart_ext_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_EXT_CLK) + } + #[doc = "USART with internal clock"] + #[inline(always)] + pub fn usart_int_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_INT_CLK) + } + #[doc = "SPI in slave operation"] + #[inline(always)] + pub fn spi_slave(self) -> &'a mut W { + self.variant(MODE_A::SPI_SLAVE) + } + #[doc = "SPI in master operation"] + #[inline(always)] + pub fn spi_master(self) -> &'a mut W { + self.variant(MODE_A::SPI_MASTER) + } + #[doc = "I2C slave operation"] + #[inline(always)] + pub fn i2c_slave(self) -> &'a mut W { + self.variant(MODE_A::I2C_SLAVE) + } + #[doc = "I2C master operation"] + #[inline(always)] + pub fn i2c_master(self) -> &'a mut W { + self.variant(MODE_A::I2C_MASTER) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 2)) | ((value as u32 & 0x07) << 2); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `PINOUT` reader - Pin Usage"] +pub struct PINOUT_R(crate::FieldReader); +impl PINOUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PINOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PINOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PINOUT` writer - Pin Usage"] +pub struct PINOUT_W<'a> { + w: &'a mut W, +} +impl<'a> PINOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "SDA Hold Time\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SDAHOLD_A { + #[doc = "0: Disabled"] + DISABLE = 0, + #[doc = "1: 50-100ns hold time"] + _75NS = 1, + #[doc = "2: 300-600ns hold time"] + _450NS = 2, + #[doc = "3: 400-800ns hold time"] + _600NS = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SDAHOLD_A) -> Self { + variant as _ + } +} +#[doc = "Field `SDAHOLD` reader - SDA Hold Time"] +pub struct SDAHOLD_R(crate::FieldReader); +impl SDAHOLD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SDAHOLD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SDAHOLD_A { + match self.bits { + 0 => SDAHOLD_A::DISABLE, + 1 => SDAHOLD_A::_75NS, + 2 => SDAHOLD_A::_450NS, + 3 => SDAHOLD_A::_600NS, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == SDAHOLD_A::DISABLE + } + #[doc = "Checks if the value of the field is `_75NS`"] + #[inline(always)] + pub fn is_75ns(&self) -> bool { + **self == SDAHOLD_A::_75NS + } + #[doc = "Checks if the value of the field is `_450NS`"] + #[inline(always)] + pub fn is_450ns(&self) -> bool { + **self == SDAHOLD_A::_450NS + } + #[doc = "Checks if the value of the field is `_600NS`"] + #[inline(always)] + pub fn is_600ns(&self) -> bool { + **self == SDAHOLD_A::_600NS + } +} +impl core::ops::Deref for SDAHOLD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SDAHOLD` writer - SDA Hold Time"] +pub struct SDAHOLD_W<'a> { + w: &'a mut W, +} +impl<'a> SDAHOLD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SDAHOLD_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(SDAHOLD_A::DISABLE) + } + #[doc = "50-100ns hold time"] + #[inline(always)] + pub fn _75ns(self) -> &'a mut W { + self.variant(SDAHOLD_A::_75NS) + } + #[doc = "300-600ns hold time"] + #[inline(always)] + pub fn _450ns(self) -> &'a mut W { + self.variant(SDAHOLD_A::_450NS) + } + #[doc = "400-800ns hold time"] + #[inline(always)] + pub fn _600ns(self) -> &'a mut W { + self.variant(SDAHOLD_A::_600NS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 20)) | ((value as u32 & 0x03) << 20); + self.w + } +} +#[doc = "Field `MEXTTOEN` reader - Master SCL Low Extend Timeout"] +pub struct MEXTTOEN_R(crate::FieldReader); +impl MEXTTOEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MEXTTOEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MEXTTOEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MEXTTOEN` writer - Master SCL Low Extend Timeout"] +pub struct MEXTTOEN_W<'a> { + w: &'a mut W, +} +impl<'a> MEXTTOEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `SEXTTOEN` reader - Slave SCL Low Extend Timeout"] +pub struct SEXTTOEN_R(crate::FieldReader); +impl SEXTTOEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SEXTTOEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEXTTOEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEXTTOEN` writer - Slave SCL Low Extend Timeout"] +pub struct SEXTTOEN_W<'a> { + w: &'a mut W, +} +impl<'a> SEXTTOEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Transfer Speed\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SPEED_A { + #[doc = "0: Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz"] + STANDARD_AND_FAST_MODE = 0, + #[doc = "1: Fast-mode Plus Upto 1MHz"] + FASTPLUS_MODE = 1, + #[doc = "2: High-speed mode Upto 3.4MHz"] + HIGH_SPEED_MODE = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SPEED_A) -> Self { + variant as _ + } +} +#[doc = "Field `SPEED` reader - Transfer Speed"] +pub struct SPEED_R(crate::FieldReader); +impl SPEED_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SPEED_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SPEED_A::STANDARD_AND_FAST_MODE), + 1 => Some(SPEED_A::FASTPLUS_MODE), + 2 => Some(SPEED_A::HIGH_SPEED_MODE), + _ => None, + } + } + #[doc = "Checks if the value of the field is `STANDARD_AND_FAST_MODE`"] + #[inline(always)] + pub fn is_standard_and_fast_mode(&self) -> bool { + **self == SPEED_A::STANDARD_AND_FAST_MODE + } + #[doc = "Checks if the value of the field is `FASTPLUS_MODE`"] + #[inline(always)] + pub fn is_fastplus_mode(&self) -> bool { + **self == SPEED_A::FASTPLUS_MODE + } + #[doc = "Checks if the value of the field is `HIGH_SPEED_MODE`"] + #[inline(always)] + pub fn is_high_speed_mode(&self) -> bool { + **self == SPEED_A::HIGH_SPEED_MODE + } +} +impl core::ops::Deref for SPEED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SPEED` writer - Transfer Speed"] +pub struct SPEED_W<'a> { + w: &'a mut W, +} +impl<'a> SPEED_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SPEED_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz"] + #[inline(always)] + pub fn standard_and_fast_mode(self) -> &'a mut W { + self.variant(SPEED_A::STANDARD_AND_FAST_MODE) + } + #[doc = "Fast-mode Plus Upto 1MHz"] + #[inline(always)] + pub fn fastplus_mode(self) -> &'a mut W { + self.variant(SPEED_A::FASTPLUS_MODE) + } + #[doc = "High-speed mode Upto 3.4MHz"] + #[inline(always)] + pub fn high_speed_mode(self) -> &'a mut W { + self.variant(SPEED_A::HIGH_SPEED_MODE) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 24)) | ((value as u32 & 0x03) << 24); + self.w + } +} +#[doc = "Field `SCLSM` reader - SCL Clock Stretch Mode"] +pub struct SCLSM_R(crate::FieldReader); +impl SCLSM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SCLSM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SCLSM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SCLSM` writer - SCL Clock Stretch Mode"] +pub struct SCLSM_W<'a> { + w: &'a mut W, +} +impl<'a> SCLSM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +#[doc = "Inactive Time-Out\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum INACTOUT_A { + #[doc = "0: Disabled"] + DISABLE = 0, + #[doc = "1: 5-6 SCL Time-Out(50-60us)"] + _55US = 1, + #[doc = "2: 10-11 SCL Time-Out(100-110us)"] + _105US = 2, + #[doc = "3: 20-21 SCL Time-Out(200-210us)"] + _205US = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: INACTOUT_A) -> Self { + variant as _ + } +} +#[doc = "Field `INACTOUT` reader - Inactive Time-Out"] +pub struct INACTOUT_R(crate::FieldReader); +impl INACTOUT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + INACTOUT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INACTOUT_A { + match self.bits { + 0 => INACTOUT_A::DISABLE, + 1 => INACTOUT_A::_55US, + 2 => INACTOUT_A::_105US, + 3 => INACTOUT_A::_205US, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == INACTOUT_A::DISABLE + } + #[doc = "Checks if the value of the field is `_55US`"] + #[inline(always)] + pub fn is_55us(&self) -> bool { + **self == INACTOUT_A::_55US + } + #[doc = "Checks if the value of the field is `_105US`"] + #[inline(always)] + pub fn is_105us(&self) -> bool { + **self == INACTOUT_A::_105US + } + #[doc = "Checks if the value of the field is `_205US`"] + #[inline(always)] + pub fn is_205us(&self) -> bool { + **self == INACTOUT_A::_205US + } +} +impl core::ops::Deref for INACTOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INACTOUT` writer - Inactive Time-Out"] +pub struct INACTOUT_W<'a> { + w: &'a mut W, +} +impl<'a> INACTOUT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: INACTOUT_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(INACTOUT_A::DISABLE) + } + #[doc = "5-6 SCL Time-Out(50-60us)"] + #[inline(always)] + pub fn _55us(self) -> &'a mut W { + self.variant(INACTOUT_A::_55US) + } + #[doc = "10-11 SCL Time-Out(100-110us)"] + #[inline(always)] + pub fn _105us(self) -> &'a mut W { + self.variant(INACTOUT_A::_105US) + } + #[doc = "20-21 SCL Time-Out(200-210us)"] + #[inline(always)] + pub fn _205us(self) -> &'a mut W { + self.variant(INACTOUT_A::_205US) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 28)) | ((value as u32 & 0x03) << 28); + self.w + } +} +#[doc = "Field `LOWTOUTEN` reader - SCL Low Timeout Enable"] +pub struct LOWTOUTEN_R(crate::FieldReader); +impl LOWTOUTEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LOWTOUTEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOWTOUTEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LOWTOUTEN` writer - SCL Low Timeout Enable"] +pub struct LOWTOUTEN_W<'a> { + w: &'a mut W, +} +impl<'a> LOWTOUTEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x07) as u8) + } + #[doc = "Bit 7 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 16 - Pin Usage"] + #[inline(always)] + pub fn pinout(&self) -> PINOUT_R { + PINOUT_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bits 20:21 - SDA Hold Time"] + #[inline(always)] + pub fn sdahold(&self) -> SDAHOLD_R { + SDAHOLD_R::new(((self.bits >> 20) & 0x03) as u8) + } + #[doc = "Bit 22 - Master SCL Low Extend Timeout"] + #[inline(always)] + pub fn mexttoen(&self) -> MEXTTOEN_R { + MEXTTOEN_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttoen(&self) -> SEXTTOEN_R { + SEXTTOEN_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bits 24:25 - Transfer Speed"] + #[inline(always)] + pub fn speed(&self) -> SPEED_R { + SPEED_R::new(((self.bits >> 24) & 0x03) as u8) + } + #[doc = "Bit 27 - SCL Clock Stretch Mode"] + #[inline(always)] + pub fn sclsm(&self) -> SCLSM_R { + SCLSM_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bits 28:29 - Inactive Time-Out"] + #[inline(always)] + pub fn inactout(&self) -> INACTOUT_R { + INACTOUT_R::new(((self.bits >> 28) & 0x03) as u8) + } + #[doc = "Bit 30 - SCL Low Timeout Enable"] + #[inline(always)] + pub fn lowtouten(&self) -> LOWTOUTEN_R { + LOWTOUTEN_R::new(((self.bits >> 30) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 7 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 16 - Pin Usage"] + #[inline(always)] + pub fn pinout(&mut self) -> PINOUT_W { + PINOUT_W { w: self } + } + #[doc = "Bits 20:21 - SDA Hold Time"] + #[inline(always)] + pub fn sdahold(&mut self) -> SDAHOLD_W { + SDAHOLD_W { w: self } + } + #[doc = "Bit 22 - Master SCL Low Extend Timeout"] + #[inline(always)] + pub fn mexttoen(&mut self) -> MEXTTOEN_W { + MEXTTOEN_W { w: self } + } + #[doc = "Bit 23 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttoen(&mut self) -> SEXTTOEN_W { + SEXTTOEN_W { w: self } + } + #[doc = "Bits 24:25 - Transfer Speed"] + #[inline(always)] + pub fn speed(&mut self) -> SPEED_W { + SPEED_W { w: self } + } + #[doc = "Bit 27 - SCL Clock Stretch Mode"] + #[inline(always)] + pub fn sclsm(&mut self) -> SCLSM_W { + SCLSM_W { w: self } + } + #[doc = "Bits 28:29 - Inactive Time-Out"] + #[inline(always)] + pub fn inactout(&mut self) -> INACTOUT_W { + INACTOUT_W { w: self } + } + #[doc = "Bit 30 - SCL Low Timeout Enable"] + #[inline(always)] + pub fn lowtouten(&mut self) -> LOWTOUTEN_W { + LOWTOUTEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/sercom0/i2cm/ctrlb.rs b/pac/atsamc20j/src/sercom0/i2cm/ctrlb.rs new file mode 100644 index 000000000000..ce534463c0da --- /dev/null +++ b/pac/atsamc20j/src/sercom0/i2cm/ctrlb.rs @@ -0,0 +1,244 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SMEN` reader - Smart Mode Enable"] +pub struct SMEN_R(crate::FieldReader); +impl SMEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SMEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SMEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SMEN` writer - Smart Mode Enable"] +pub struct SMEN_W<'a> { + w: &'a mut W, +} +impl<'a> SMEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `QCEN` reader - Quick Command Enable"] +pub struct QCEN_R(crate::FieldReader); +impl QCEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + QCEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for QCEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `QCEN` writer - Quick Command Enable"] +pub struct QCEN_W<'a> { + w: &'a mut W, +} +impl<'a> QCEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Field `ACKACT` reader - Acknowledge Action"] +pub struct ACKACT_R(crate::FieldReader); +impl ACKACT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ACKACT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ACKACT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ACKACT` writer - Acknowledge Action"] +pub struct ACKACT_W<'a> { + w: &'a mut W, +} +impl<'a> ACKACT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +impl R { + #[doc = "Bit 8 - Smart Mode Enable"] + #[inline(always)] + pub fn smen(&self) -> SMEN_R { + SMEN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Quick Command Enable"] + #[inline(always)] + pub fn qcen(&self) -> QCEN_R { + QCEN_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bits 16:17 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bit 18 - Acknowledge Action"] + #[inline(always)] + pub fn ackact(&self) -> ACKACT_R { + ACKACT_R::new(((self.bits >> 18) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 8 - Smart Mode Enable"] + #[inline(always)] + pub fn smen(&mut self) -> SMEN_W { + SMEN_W { w: self } + } + #[doc = "Bit 9 - Quick Command Enable"] + #[inline(always)] + pub fn qcen(&mut self) -> QCEN_W { + QCEN_W { w: self } + } + #[doc = "Bits 16:17 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Bit 18 - Acknowledge Action"] + #[inline(always)] + pub fn ackact(&mut self) -> ACKACT_W { + ACKACT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/sercom0/i2cm/data.rs b/pac/atsamc20j/src/sercom0/i2cm/data.rs new file mode 100644 index 000000000000..cf204596d3a6 --- /dev/null +++ b/pac/atsamc20j/src/sercom0/i2cm/data.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data Value"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data Value"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Data Value"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Value"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/sercom0/i2cm/dbgctrl.rs b/pac/atsamc20j/src/sercom0/i2cm/dbgctrl.rs new file mode 100644 index 000000000000..0fffdb4c6e39 --- /dev/null +++ b/pac/atsamc20j/src/sercom0/i2cm/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGSTOP` reader - Debug Mode"] +pub struct DBGSTOP_R(crate::FieldReader); +impl DBGSTOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGSTOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGSTOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGSTOP` writer - Debug Mode"] +pub struct DBGSTOP_W<'a> { + w: &'a mut W, +} +impl<'a> DBGSTOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&self) -> DBGSTOP_R { + DBGSTOP_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&mut self) -> DBGSTOP_W { + DBGSTOP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/sercom0/i2cm/intenclr.rs b/pac/atsamc20j/src/sercom0/i2cm/intenclr.rs new file mode 100644 index 000000000000..17f067a55656 --- /dev/null +++ b/pac/atsamc20j/src/sercom0/i2cm/intenclr.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MB` reader - Master On Bus Interrupt Disable"] +pub struct MB_R(crate::FieldReader); +impl MB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MB` writer - Master On Bus Interrupt Disable"] +pub struct MB_W<'a> { + w: &'a mut W, +} +impl<'a> MB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SB` reader - Slave On Bus Interrupt Disable"] +pub struct SB_R(crate::FieldReader); +impl SB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SB` writer - Slave On Bus Interrupt Disable"] +pub struct SB_W<'a> { + w: &'a mut W, +} +impl<'a> SB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Disable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Disable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Master On Bus Interrupt Disable"] + #[inline(always)] + pub fn mb(&self) -> MB_R { + MB_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Slave On Bus Interrupt Disable"] + #[inline(always)] + pub fn sb(&self) -> SB_R { + SB_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Master On Bus Interrupt Disable"] + #[inline(always)] + pub fn mb(&mut self) -> MB_W { + MB_W { w: self } + } + #[doc = "Bit 1 - Slave On Bus Interrupt Disable"] + #[inline(always)] + pub fn sb(&mut self) -> SB_W { + SB_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/sercom0/i2cm/intenset.rs b/pac/atsamc20j/src/sercom0/i2cm/intenset.rs new file mode 100644 index 000000000000..a0cbf96b3aa0 --- /dev/null +++ b/pac/atsamc20j/src/sercom0/i2cm/intenset.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MB` reader - Master On Bus Interrupt Enable"] +pub struct MB_R(crate::FieldReader); +impl MB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MB` writer - Master On Bus Interrupt Enable"] +pub struct MB_W<'a> { + w: &'a mut W, +} +impl<'a> MB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SB` reader - Slave On Bus Interrupt Enable"] +pub struct SB_R(crate::FieldReader); +impl SB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SB` writer - Slave On Bus Interrupt Enable"] +pub struct SB_W<'a> { + w: &'a mut W, +} +impl<'a> SB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Master On Bus Interrupt Enable"] + #[inline(always)] + pub fn mb(&self) -> MB_R { + MB_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Slave On Bus Interrupt Enable"] + #[inline(always)] + pub fn sb(&self) -> SB_R { + SB_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Master On Bus Interrupt Enable"] + #[inline(always)] + pub fn mb(&mut self) -> MB_W { + MB_W { w: self } + } + #[doc = "Bit 1 - Slave On Bus Interrupt Enable"] + #[inline(always)] + pub fn sb(&mut self) -> SB_W { + SB_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/sercom0/i2cm/intflag.rs b/pac/atsamc20j/src/sercom0/i2cm/intflag.rs new file mode 100644 index 000000000000..0fb0d2b9060c --- /dev/null +++ b/pac/atsamc20j/src/sercom0/i2cm/intflag.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MB` reader - Master On Bus Interrupt"] +pub struct MB_R(crate::FieldReader); +impl MB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MB` writer - Master On Bus Interrupt"] +pub struct MB_W<'a> { + w: &'a mut W, +} +impl<'a> MB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SB` reader - Slave On Bus Interrupt"] +pub struct SB_R(crate::FieldReader); +impl SB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SB` writer - Slave On Bus Interrupt"] +pub struct SB_W<'a> { + w: &'a mut W, +} +impl<'a> SB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Master On Bus Interrupt"] + #[inline(always)] + pub fn mb(&self) -> MB_R { + MB_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Slave On Bus Interrupt"] + #[inline(always)] + pub fn sb(&self) -> SB_R { + SB_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Master On Bus Interrupt"] + #[inline(always)] + pub fn mb(&mut self) -> MB_W { + MB_W { w: self } + } + #[doc = "Bit 1 - Slave On Bus Interrupt"] + #[inline(always)] + pub fn sb(&mut self) -> SB_W { + SB_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/sercom0/i2cm/status.rs b/pac/atsamc20j/src/sercom0/i2cm/status.rs new file mode 100644 index 000000000000..95af23673ec4 --- /dev/null +++ b/pac/atsamc20j/src/sercom0/i2cm/status.rs @@ -0,0 +1,479 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BUSERR` reader - Bus Error"] +pub struct BUSERR_R(crate::FieldReader); +impl BUSERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSERR` writer - Bus Error"] +pub struct BUSERR_W<'a> { + w: &'a mut W, +} +impl<'a> BUSERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `ARBLOST` reader - Arbitration Lost"] +pub struct ARBLOST_R(crate::FieldReader); +impl ARBLOST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ARBLOST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ARBLOST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ARBLOST` writer - Arbitration Lost"] +pub struct ARBLOST_W<'a> { + w: &'a mut W, +} +impl<'a> ARBLOST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXNACK` reader - Received Not Acknowledge"] +pub struct RXNACK_R(crate::FieldReader); +impl RXNACK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXNACK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXNACK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXNACK` writer - Received Not Acknowledge"] +pub struct RXNACK_W<'a> { + w: &'a mut W, +} +impl<'a> RXNACK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `BUSSTATE` reader - Bus State"] +pub struct BUSSTATE_R(crate::FieldReader); +impl BUSSTATE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BUSSTATE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSSTATE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSSTATE` writer - Bus State"] +pub struct BUSSTATE_W<'a> { + w: &'a mut W, +} +impl<'a> BUSSTATE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u16 & 0x03) << 4); + self.w + } +} +#[doc = "Field `LOWTOUT` reader - SCL Low Timeout"] +pub struct LOWTOUT_R(crate::FieldReader); +impl LOWTOUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LOWTOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOWTOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LOWTOUT` writer - SCL Low Timeout"] +pub struct LOWTOUT_W<'a> { + w: &'a mut W, +} +impl<'a> LOWTOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `CLKHOLD` reader - Clock Hold"] +pub struct CLKHOLD_R(crate::FieldReader); +impl CLKHOLD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKHOLD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKHOLD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKHOLD` writer - Clock Hold"] +pub struct CLKHOLD_W<'a> { + w: &'a mut W, +} +impl<'a> CLKHOLD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `MEXTTOUT` reader - Master SCL Low Extend Timeout"] +pub struct MEXTTOUT_R(crate::FieldReader); +impl MEXTTOUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MEXTTOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MEXTTOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MEXTTOUT` writer - Master SCL Low Extend Timeout"] +pub struct MEXTTOUT_W<'a> { + w: &'a mut W, +} +impl<'a> MEXTTOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `SEXTTOUT` reader - Slave SCL Low Extend Timeout"] +pub struct SEXTTOUT_R(crate::FieldReader); +impl SEXTTOUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SEXTTOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEXTTOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEXTTOUT` writer - Slave SCL Low Extend Timeout"] +pub struct SEXTTOUT_W<'a> { + w: &'a mut W, +} +impl<'a> SEXTTOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `LENERR` reader - Length Error"] +pub struct LENERR_R(crate::FieldReader); +impl LENERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LENERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LENERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LENERR` writer - Length Error"] +pub struct LENERR_W<'a> { + w: &'a mut W, +} +impl<'a> LENERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u16 & 0x01) << 10); + self.w + } +} +impl R { + #[doc = "Bit 0 - Bus Error"] + #[inline(always)] + pub fn buserr(&self) -> BUSERR_R { + BUSERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Arbitration Lost"] + #[inline(always)] + pub fn arblost(&self) -> ARBLOST_R { + ARBLOST_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Received Not Acknowledge"] + #[inline(always)] + pub fn rxnack(&self) -> RXNACK_R { + RXNACK_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 4:5 - Bus State"] + #[inline(always)] + pub fn busstate(&self) -> BUSSTATE_R { + BUSSTATE_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bit 6 - SCL Low Timeout"] + #[inline(always)] + pub fn lowtout(&self) -> LOWTOUT_R { + LOWTOUT_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Clock Hold"] + #[inline(always)] + pub fn clkhold(&self) -> CLKHOLD_R { + CLKHOLD_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Master SCL Low Extend Timeout"] + #[inline(always)] + pub fn mexttout(&self) -> MEXTTOUT_R { + MEXTTOUT_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttout(&self) -> SEXTTOUT_R { + SEXTTOUT_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Length Error"] + #[inline(always)] + pub fn lenerr(&self) -> LENERR_R { + LENERR_R::new(((self.bits >> 10) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Bus Error"] + #[inline(always)] + pub fn buserr(&mut self) -> BUSERR_W { + BUSERR_W { w: self } + } + #[doc = "Bit 1 - Arbitration Lost"] + #[inline(always)] + pub fn arblost(&mut self) -> ARBLOST_W { + ARBLOST_W { w: self } + } + #[doc = "Bit 2 - Received Not Acknowledge"] + #[inline(always)] + pub fn rxnack(&mut self) -> RXNACK_W { + RXNACK_W { w: self } + } + #[doc = "Bits 4:5 - Bus State"] + #[inline(always)] + pub fn busstate(&mut self) -> BUSSTATE_W { + BUSSTATE_W { w: self } + } + #[doc = "Bit 6 - SCL Low Timeout"] + #[inline(always)] + pub fn lowtout(&mut self) -> LOWTOUT_W { + LOWTOUT_W { w: self } + } + #[doc = "Bit 7 - Clock Hold"] + #[inline(always)] + pub fn clkhold(&mut self) -> CLKHOLD_W { + CLKHOLD_W { w: self } + } + #[doc = "Bit 8 - Master SCL Low Extend Timeout"] + #[inline(always)] + pub fn mexttout(&mut self) -> MEXTTOUT_W { + MEXTTOUT_W { w: self } + } + #[doc = "Bit 9 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttout(&mut self) -> SEXTTOUT_W { + SEXTTOUT_W { w: self } + } + #[doc = "Bit 10 - Length Error"] + #[inline(always)] + pub fn lenerr(&mut self) -> LENERR_W { + LENERR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/sercom0/i2cm/syncbusy.rs b/pac/atsamc20j/src/sercom0/i2cm/syncbusy.rs new file mode 100644 index 000000000000..87dd418d1cd3 --- /dev/null +++ b/pac/atsamc20j/src/sercom0/i2cm/syncbusy.rs @@ -0,0 +1,93 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - SERCOM Enable Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYSOP` reader - System Operation Synchronization Busy"] +pub struct SYSOP_R(crate::FieldReader); +impl SYSOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYSOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYSOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM Enable Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - System Operation Synchronization Busy"] + #[inline(always)] + pub fn sysop(&self) -> SYSOP_R { + SYSOP_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +#[doc = "I2CM Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/sercom0/i2cs.rs b/pac/atsamc20j/src/sercom0/i2cs.rs new file mode 100644 index 000000000000..baf9513c6cc1 --- /dev/null +++ b/pac/atsamc20j/src/sercom0/i2cs.rs @@ -0,0 +1,36 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "I2CS Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "I2CS Control B"] +pub mod ctrlb; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "I2CS Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "I2CS Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "I2CS Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "I2CS Status"] +pub mod status; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "I2CS Synchronization Busy"] +pub mod syncbusy; +#[doc = "ADDR register accessor: an alias for `Reg`"] +pub type ADDR = crate::Reg; +#[doc = "I2CS Address"] +pub mod addr; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "I2CS Data"] +pub mod data; diff --git a/pac/atsamc20j/src/sercom0/i2cs/addr.rs b/pac/atsamc20j/src/sercom0/i2cs/addr.rs new file mode 100644 index 000000000000..c1b69ee22891 --- /dev/null +++ b/pac/atsamc20j/src/sercom0/i2cs/addr.rs @@ -0,0 +1,234 @@ +#[doc = "Register `ADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `GENCEN` reader - General Call Address Enable"] +pub struct GENCEN_R(crate::FieldReader); +impl GENCEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENCEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENCEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENCEN` writer - General Call Address Enable"] +pub struct GENCEN_W<'a> { + w: &'a mut W, +} +impl<'a> GENCEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ADDR` reader - Address Value"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - Address Value"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03ff << 1)) | ((value as u32 & 0x03ff) << 1); + self.w + } +} +#[doc = "Field `TENBITEN` reader - Ten Bit Addressing Enable"] +pub struct TENBITEN_R(crate::FieldReader); +impl TENBITEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TENBITEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TENBITEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TENBITEN` writer - Ten Bit Addressing Enable"] +pub struct TENBITEN_W<'a> { + w: &'a mut W, +} +impl<'a> TENBITEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `ADDRMASK` reader - Address Mask"] +pub struct ADDRMASK_R(crate::FieldReader); +impl ADDRMASK_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + ADDRMASK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDRMASK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDRMASK` writer - Address Mask"] +pub struct ADDRMASK_W<'a> { + w: &'a mut W, +} +impl<'a> ADDRMASK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03ff << 17)) | ((value as u32 & 0x03ff) << 17); + self.w + } +} +impl R { + #[doc = "Bit 0 - General Call Address Enable"] + #[inline(always)] + pub fn gencen(&self) -> GENCEN_R { + GENCEN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bits 1:10 - Address Value"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new(((self.bits >> 1) & 0x03ff) as u16) + } + #[doc = "Bit 15 - Ten Bit Addressing Enable"] + #[inline(always)] + pub fn tenbiten(&self) -> TENBITEN_R { + TENBITEN_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 17:26 - Address Mask"] + #[inline(always)] + pub fn addrmask(&self) -> ADDRMASK_R { + ADDRMASK_R::new(((self.bits >> 17) & 0x03ff) as u16) + } +} +impl W { + #[doc = "Bit 0 - General Call Address Enable"] + #[inline(always)] + pub fn gencen(&mut self) -> GENCEN_W { + GENCEN_W { w: self } + } + #[doc = "Bits 1:10 - Address Value"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Bit 15 - Ten Bit Addressing Enable"] + #[inline(always)] + pub fn tenbiten(&mut self) -> TENBITEN_W { + TENBITEN_W { w: self } + } + #[doc = "Bits 17:26 - Address Mask"] + #[inline(always)] + pub fn addrmask(&mut self) -> ADDRMASK_W { + ADDRMASK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [addr](index.html) module"] +pub struct ADDR_SPEC; +impl crate::RegisterSpec for ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [addr::R](R) reader structure"] +impl crate::Readable for ADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [addr::W](W) writer structure"] +impl crate::Writable for ADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ADDR to value 0"] +impl crate::Resettable for ADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/sercom0/i2cs/ctrla.rs b/pac/atsamc20j/src/sercom0/i2cs/ctrla.rs new file mode 100644 index 000000000000..ec93812b004f --- /dev/null +++ b/pac/atsamc20j/src/sercom0/i2cs/ctrla.rs @@ -0,0 +1,744 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: USART with external clock"] + USART_EXT_CLK = 0, + #[doc = "1: USART with internal clock"] + USART_INT_CLK = 1, + #[doc = "2: SPI in slave operation"] + SPI_SLAVE = 2, + #[doc = "3: SPI in master operation"] + SPI_MASTER = 3, + #[doc = "4: I2C slave operation"] + I2C_SLAVE = 4, + #[doc = "5: I2C master operation"] + I2C_MASTER = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::USART_EXT_CLK), + 1 => Some(MODE_A::USART_INT_CLK), + 2 => Some(MODE_A::SPI_SLAVE), + 3 => Some(MODE_A::SPI_MASTER), + 4 => Some(MODE_A::I2C_SLAVE), + 5 => Some(MODE_A::I2C_MASTER), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_EXT_CLK`"] + #[inline(always)] + pub fn is_usart_ext_clk(&self) -> bool { + **self == MODE_A::USART_EXT_CLK + } + #[doc = "Checks if the value of the field is `USART_INT_CLK`"] + #[inline(always)] + pub fn is_usart_int_clk(&self) -> bool { + **self == MODE_A::USART_INT_CLK + } + #[doc = "Checks if the value of the field is `SPI_SLAVE`"] + #[inline(always)] + pub fn is_spi_slave(&self) -> bool { + **self == MODE_A::SPI_SLAVE + } + #[doc = "Checks if the value of the field is `SPI_MASTER`"] + #[inline(always)] + pub fn is_spi_master(&self) -> bool { + **self == MODE_A::SPI_MASTER + } + #[doc = "Checks if the value of the field is `I2C_SLAVE`"] + #[inline(always)] + pub fn is_i2c_slave(&self) -> bool { + **self == MODE_A::I2C_SLAVE + } + #[doc = "Checks if the value of the field is `I2C_MASTER`"] + #[inline(always)] + pub fn is_i2c_master(&self) -> bool { + **self == MODE_A::I2C_MASTER + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART with external clock"] + #[inline(always)] + pub fn usart_ext_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_EXT_CLK) + } + #[doc = "USART with internal clock"] + #[inline(always)] + pub fn usart_int_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_INT_CLK) + } + #[doc = "SPI in slave operation"] + #[inline(always)] + pub fn spi_slave(self) -> &'a mut W { + self.variant(MODE_A::SPI_SLAVE) + } + #[doc = "SPI in master operation"] + #[inline(always)] + pub fn spi_master(self) -> &'a mut W { + self.variant(MODE_A::SPI_MASTER) + } + #[doc = "I2C slave operation"] + #[inline(always)] + pub fn i2c_slave(self) -> &'a mut W { + self.variant(MODE_A::I2C_SLAVE) + } + #[doc = "I2C master operation"] + #[inline(always)] + pub fn i2c_master(self) -> &'a mut W { + self.variant(MODE_A::I2C_MASTER) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 2)) | ((value as u32 & 0x07) << 2); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `PINOUT` reader - Pin Usage"] +pub struct PINOUT_R(crate::FieldReader); +impl PINOUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PINOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PINOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PINOUT` writer - Pin Usage"] +pub struct PINOUT_W<'a> { + w: &'a mut W, +} +impl<'a> PINOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "SDA Hold Time\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SDAHOLD_A { + #[doc = "0: Disabled"] + DISABLE = 0, + #[doc = "1: 50-100ns hold time"] + _75NS = 1, + #[doc = "2: 300-600ns hold time"] + _450NS = 2, + #[doc = "3: 400-800ns hold time"] + _600NS = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SDAHOLD_A) -> Self { + variant as _ + } +} +#[doc = "Field `SDAHOLD` reader - SDA Hold Time"] +pub struct SDAHOLD_R(crate::FieldReader); +impl SDAHOLD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SDAHOLD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SDAHOLD_A { + match self.bits { + 0 => SDAHOLD_A::DISABLE, + 1 => SDAHOLD_A::_75NS, + 2 => SDAHOLD_A::_450NS, + 3 => SDAHOLD_A::_600NS, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == SDAHOLD_A::DISABLE + } + #[doc = "Checks if the value of the field is `_75NS`"] + #[inline(always)] + pub fn is_75ns(&self) -> bool { + **self == SDAHOLD_A::_75NS + } + #[doc = "Checks if the value of the field is `_450NS`"] + #[inline(always)] + pub fn is_450ns(&self) -> bool { + **self == SDAHOLD_A::_450NS + } + #[doc = "Checks if the value of the field is `_600NS`"] + #[inline(always)] + pub fn is_600ns(&self) -> bool { + **self == SDAHOLD_A::_600NS + } +} +impl core::ops::Deref for SDAHOLD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SDAHOLD` writer - SDA Hold Time"] +pub struct SDAHOLD_W<'a> { + w: &'a mut W, +} +impl<'a> SDAHOLD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SDAHOLD_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(SDAHOLD_A::DISABLE) + } + #[doc = "50-100ns hold time"] + #[inline(always)] + pub fn _75ns(self) -> &'a mut W { + self.variant(SDAHOLD_A::_75NS) + } + #[doc = "300-600ns hold time"] + #[inline(always)] + pub fn _450ns(self) -> &'a mut W { + self.variant(SDAHOLD_A::_450NS) + } + #[doc = "400-800ns hold time"] + #[inline(always)] + pub fn _600ns(self) -> &'a mut W { + self.variant(SDAHOLD_A::_600NS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 20)) | ((value as u32 & 0x03) << 20); + self.w + } +} +#[doc = "Field `SEXTTOEN` reader - Slave SCL Low Extend Timeout"] +pub struct SEXTTOEN_R(crate::FieldReader); +impl SEXTTOEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SEXTTOEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEXTTOEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEXTTOEN` writer - Slave SCL Low Extend Timeout"] +pub struct SEXTTOEN_W<'a> { + w: &'a mut W, +} +impl<'a> SEXTTOEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Transfer Speed\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SPEED_A { + #[doc = "0: Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz"] + STANDARD_AND_FAST_MODE = 0, + #[doc = "1: Fast-mode Plus Upto 1MHz"] + FASTPLUS_MODE = 1, + #[doc = "2: High-speed mode Upto 3.4MHz"] + HIGH_SPEED_MODE = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SPEED_A) -> Self { + variant as _ + } +} +#[doc = "Field `SPEED` reader - Transfer Speed"] +pub struct SPEED_R(crate::FieldReader); +impl SPEED_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SPEED_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SPEED_A::STANDARD_AND_FAST_MODE), + 1 => Some(SPEED_A::FASTPLUS_MODE), + 2 => Some(SPEED_A::HIGH_SPEED_MODE), + _ => None, + } + } + #[doc = "Checks if the value of the field is `STANDARD_AND_FAST_MODE`"] + #[inline(always)] + pub fn is_standard_and_fast_mode(&self) -> bool { + **self == SPEED_A::STANDARD_AND_FAST_MODE + } + #[doc = "Checks if the value of the field is `FASTPLUS_MODE`"] + #[inline(always)] + pub fn is_fastplus_mode(&self) -> bool { + **self == SPEED_A::FASTPLUS_MODE + } + #[doc = "Checks if the value of the field is `HIGH_SPEED_MODE`"] + #[inline(always)] + pub fn is_high_speed_mode(&self) -> bool { + **self == SPEED_A::HIGH_SPEED_MODE + } +} +impl core::ops::Deref for SPEED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SPEED` writer - Transfer Speed"] +pub struct SPEED_W<'a> { + w: &'a mut W, +} +impl<'a> SPEED_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SPEED_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz"] + #[inline(always)] + pub fn standard_and_fast_mode(self) -> &'a mut W { + self.variant(SPEED_A::STANDARD_AND_FAST_MODE) + } + #[doc = "Fast-mode Plus Upto 1MHz"] + #[inline(always)] + pub fn fastplus_mode(self) -> &'a mut W { + self.variant(SPEED_A::FASTPLUS_MODE) + } + #[doc = "High-speed mode Upto 3.4MHz"] + #[inline(always)] + pub fn high_speed_mode(self) -> &'a mut W { + self.variant(SPEED_A::HIGH_SPEED_MODE) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 24)) | ((value as u32 & 0x03) << 24); + self.w + } +} +#[doc = "Field `SCLSM` reader - SCL Clock Stretch Mode"] +pub struct SCLSM_R(crate::FieldReader); +impl SCLSM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SCLSM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SCLSM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SCLSM` writer - SCL Clock Stretch Mode"] +pub struct SCLSM_W<'a> { + w: &'a mut W, +} +impl<'a> SCLSM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +#[doc = "Field `LOWTOUTEN` reader - SCL Low Timeout Enable"] +pub struct LOWTOUTEN_R(crate::FieldReader); +impl LOWTOUTEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LOWTOUTEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOWTOUTEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LOWTOUTEN` writer - SCL Low Timeout Enable"] +pub struct LOWTOUTEN_W<'a> { + w: &'a mut W, +} +impl<'a> LOWTOUTEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x07) as u8) + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 16 - Pin Usage"] + #[inline(always)] + pub fn pinout(&self) -> PINOUT_R { + PINOUT_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bits 20:21 - SDA Hold Time"] + #[inline(always)] + pub fn sdahold(&self) -> SDAHOLD_R { + SDAHOLD_R::new(((self.bits >> 20) & 0x03) as u8) + } + #[doc = "Bit 23 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttoen(&self) -> SEXTTOEN_R { + SEXTTOEN_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bits 24:25 - Transfer Speed"] + #[inline(always)] + pub fn speed(&self) -> SPEED_R { + SPEED_R::new(((self.bits >> 24) & 0x03) as u8) + } + #[doc = "Bit 27 - SCL Clock Stretch Mode"] + #[inline(always)] + pub fn sclsm(&self) -> SCLSM_R { + SCLSM_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 30 - SCL Low Timeout Enable"] + #[inline(always)] + pub fn lowtouten(&self) -> LOWTOUTEN_R { + LOWTOUTEN_R::new(((self.bits >> 30) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 16 - Pin Usage"] + #[inline(always)] + pub fn pinout(&mut self) -> PINOUT_W { + PINOUT_W { w: self } + } + #[doc = "Bits 20:21 - SDA Hold Time"] + #[inline(always)] + pub fn sdahold(&mut self) -> SDAHOLD_W { + SDAHOLD_W { w: self } + } + #[doc = "Bit 23 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttoen(&mut self) -> SEXTTOEN_W { + SEXTTOEN_W { w: self } + } + #[doc = "Bits 24:25 - Transfer Speed"] + #[inline(always)] + pub fn speed(&mut self) -> SPEED_W { + SPEED_W { w: self } + } + #[doc = "Bit 27 - SCL Clock Stretch Mode"] + #[inline(always)] + pub fn sclsm(&mut self) -> SCLSM_W { + SCLSM_W { w: self } + } + #[doc = "Bit 30 - SCL Low Timeout Enable"] + #[inline(always)] + pub fn lowtouten(&mut self) -> LOWTOUTEN_W { + LOWTOUTEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/sercom0/i2cs/ctrlb.rs b/pac/atsamc20j/src/sercom0/i2cs/ctrlb.rs new file mode 100644 index 000000000000..b20f48581ed5 --- /dev/null +++ b/pac/atsamc20j/src/sercom0/i2cs/ctrlb.rs @@ -0,0 +1,328 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SMEN` reader - Smart Mode Enable"] +pub struct SMEN_R(crate::FieldReader); +impl SMEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SMEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SMEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SMEN` writer - Smart Mode Enable"] +pub struct SMEN_W<'a> { + w: &'a mut W, +} +impl<'a> SMEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `GCMD` reader - PMBus Group Command"] +pub struct GCMD_R(crate::FieldReader); +impl GCMD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GCMD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GCMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GCMD` writer - PMBus Group Command"] +pub struct GCMD_W<'a> { + w: &'a mut W, +} +impl<'a> GCMD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `AACKEN` reader - Automatic Address Acknowledge"] +pub struct AACKEN_R(crate::FieldReader); +impl AACKEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AACKEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AACKEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AACKEN` writer - Automatic Address Acknowledge"] +pub struct AACKEN_W<'a> { + w: &'a mut W, +} +impl<'a> AACKEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `AMODE` reader - Address Mode"] +pub struct AMODE_R(crate::FieldReader); +impl AMODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + AMODE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AMODE` writer - Address Mode"] +pub struct AMODE_W<'a> { + w: &'a mut W, +} +impl<'a> AMODE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 14)) | ((value as u32 & 0x03) << 14); + self.w + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Field `ACKACT` reader - Acknowledge Action"] +pub struct ACKACT_R(crate::FieldReader); +impl ACKACT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ACKACT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ACKACT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ACKACT` writer - Acknowledge Action"] +pub struct ACKACT_W<'a> { + w: &'a mut W, +} +impl<'a> ACKACT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +impl R { + #[doc = "Bit 8 - Smart Mode Enable"] + #[inline(always)] + pub fn smen(&self) -> SMEN_R { + SMEN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - PMBus Group Command"] + #[inline(always)] + pub fn gcmd(&self) -> GCMD_R { + GCMD_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Automatic Address Acknowledge"] + #[inline(always)] + pub fn aacken(&self) -> AACKEN_R { + AACKEN_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bits 14:15 - Address Mode"] + #[inline(always)] + pub fn amode(&self) -> AMODE_R { + AMODE_R::new(((self.bits >> 14) & 0x03) as u8) + } + #[doc = "Bits 16:17 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bit 18 - Acknowledge Action"] + #[inline(always)] + pub fn ackact(&self) -> ACKACT_R { + ACKACT_R::new(((self.bits >> 18) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 8 - Smart Mode Enable"] + #[inline(always)] + pub fn smen(&mut self) -> SMEN_W { + SMEN_W { w: self } + } + #[doc = "Bit 9 - PMBus Group Command"] + #[inline(always)] + pub fn gcmd(&mut self) -> GCMD_W { + GCMD_W { w: self } + } + #[doc = "Bit 10 - Automatic Address Acknowledge"] + #[inline(always)] + pub fn aacken(&mut self) -> AACKEN_W { + AACKEN_W { w: self } + } + #[doc = "Bits 14:15 - Address Mode"] + #[inline(always)] + pub fn amode(&mut self) -> AMODE_W { + AMODE_W { w: self } + } + #[doc = "Bits 16:17 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Bit 18 - Acknowledge Action"] + #[inline(always)] + pub fn ackact(&mut self) -> ACKACT_W { + ACKACT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/sercom0/i2cs/data.rs b/pac/atsamc20j/src/sercom0/i2cs/data.rs new file mode 100644 index 000000000000..d8bfe070431a --- /dev/null +++ b/pac/atsamc20j/src/sercom0/i2cs/data.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data Value"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data Value"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Data Value"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Value"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/sercom0/i2cs/intenclr.rs b/pac/atsamc20j/src/sercom0/i2cs/intenclr.rs new file mode 100644 index 000000000000..49f5191c8d63 --- /dev/null +++ b/pac/atsamc20j/src/sercom0/i2cs/intenclr.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PREC` reader - Stop Received Interrupt Disable"] +pub struct PREC_R(crate::FieldReader); +impl PREC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PREC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PREC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PREC` writer - Stop Received Interrupt Disable"] +pub struct PREC_W<'a> { + w: &'a mut W, +} +impl<'a> PREC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `AMATCH` reader - Address Match Interrupt Disable"] +pub struct AMATCH_R(crate::FieldReader); +impl AMATCH_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AMATCH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AMATCH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AMATCH` writer - Address Match Interrupt Disable"] +pub struct AMATCH_W<'a> { + w: &'a mut W, +} +impl<'a> AMATCH_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `DRDY` reader - Data Interrupt Disable"] +pub struct DRDY_R(crate::FieldReader); +impl DRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRDY` writer - Data Interrupt Disable"] +pub struct DRDY_W<'a> { + w: &'a mut W, +} +impl<'a> DRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Disable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Disable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Stop Received Interrupt Disable"] + #[inline(always)] + pub fn prec(&self) -> PREC_R { + PREC_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Address Match Interrupt Disable"] + #[inline(always)] + pub fn amatch(&self) -> AMATCH_R { + AMATCH_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Data Interrupt Disable"] + #[inline(always)] + pub fn drdy(&self) -> DRDY_R { + DRDY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Stop Received Interrupt Disable"] + #[inline(always)] + pub fn prec(&mut self) -> PREC_W { + PREC_W { w: self } + } + #[doc = "Bit 1 - Address Match Interrupt Disable"] + #[inline(always)] + pub fn amatch(&mut self) -> AMATCH_W { + AMATCH_W { w: self } + } + #[doc = "Bit 2 - Data Interrupt Disable"] + #[inline(always)] + pub fn drdy(&mut self) -> DRDY_W { + DRDY_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/sercom0/i2cs/intenset.rs b/pac/atsamc20j/src/sercom0/i2cs/intenset.rs new file mode 100644 index 000000000000..97ea784d7476 --- /dev/null +++ b/pac/atsamc20j/src/sercom0/i2cs/intenset.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PREC` reader - Stop Received Interrupt Enable"] +pub struct PREC_R(crate::FieldReader); +impl PREC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PREC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PREC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PREC` writer - Stop Received Interrupt Enable"] +pub struct PREC_W<'a> { + w: &'a mut W, +} +impl<'a> PREC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `AMATCH` reader - Address Match Interrupt Enable"] +pub struct AMATCH_R(crate::FieldReader); +impl AMATCH_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AMATCH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AMATCH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AMATCH` writer - Address Match Interrupt Enable"] +pub struct AMATCH_W<'a> { + w: &'a mut W, +} +impl<'a> AMATCH_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `DRDY` reader - Data Interrupt Enable"] +pub struct DRDY_R(crate::FieldReader); +impl DRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRDY` writer - Data Interrupt Enable"] +pub struct DRDY_W<'a> { + w: &'a mut W, +} +impl<'a> DRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Stop Received Interrupt Enable"] + #[inline(always)] + pub fn prec(&self) -> PREC_R { + PREC_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Address Match Interrupt Enable"] + #[inline(always)] + pub fn amatch(&self) -> AMATCH_R { + AMATCH_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Data Interrupt Enable"] + #[inline(always)] + pub fn drdy(&self) -> DRDY_R { + DRDY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Stop Received Interrupt Enable"] + #[inline(always)] + pub fn prec(&mut self) -> PREC_W { + PREC_W { w: self } + } + #[doc = "Bit 1 - Address Match Interrupt Enable"] + #[inline(always)] + pub fn amatch(&mut self) -> AMATCH_W { + AMATCH_W { w: self } + } + #[doc = "Bit 2 - Data Interrupt Enable"] + #[inline(always)] + pub fn drdy(&mut self) -> DRDY_W { + DRDY_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/sercom0/i2cs/intflag.rs b/pac/atsamc20j/src/sercom0/i2cs/intflag.rs new file mode 100644 index 000000000000..2eee333e4e59 --- /dev/null +++ b/pac/atsamc20j/src/sercom0/i2cs/intflag.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PREC` reader - Stop Received Interrupt"] +pub struct PREC_R(crate::FieldReader); +impl PREC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PREC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PREC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PREC` writer - Stop Received Interrupt"] +pub struct PREC_W<'a> { + w: &'a mut W, +} +impl<'a> PREC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `AMATCH` reader - Address Match Interrupt"] +pub struct AMATCH_R(crate::FieldReader); +impl AMATCH_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AMATCH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AMATCH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AMATCH` writer - Address Match Interrupt"] +pub struct AMATCH_W<'a> { + w: &'a mut W, +} +impl<'a> AMATCH_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `DRDY` reader - Data Interrupt"] +pub struct DRDY_R(crate::FieldReader); +impl DRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRDY` writer - Data Interrupt"] +pub struct DRDY_W<'a> { + w: &'a mut W, +} +impl<'a> DRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Stop Received Interrupt"] + #[inline(always)] + pub fn prec(&self) -> PREC_R { + PREC_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Address Match Interrupt"] + #[inline(always)] + pub fn amatch(&self) -> AMATCH_R { + AMATCH_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Data Interrupt"] + #[inline(always)] + pub fn drdy(&self) -> DRDY_R { + DRDY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Stop Received Interrupt"] + #[inline(always)] + pub fn prec(&mut self) -> PREC_W { + PREC_W { w: self } + } + #[doc = "Bit 1 - Address Match Interrupt"] + #[inline(always)] + pub fn amatch(&mut self) -> AMATCH_W { + AMATCH_W { w: self } + } + #[doc = "Bit 2 - Data Interrupt"] + #[inline(always)] + pub fn drdy(&mut self) -> DRDY_W { + DRDY_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/sercom0/i2cs/status.rs b/pac/atsamc20j/src/sercom0/i2cs/status.rs new file mode 100644 index 000000000000..b3f6d218fa66 --- /dev/null +++ b/pac/atsamc20j/src/sercom0/i2cs/status.rs @@ -0,0 +1,489 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BUSERR` reader - Bus Error"] +pub struct BUSERR_R(crate::FieldReader); +impl BUSERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSERR` writer - Bus Error"] +pub struct BUSERR_W<'a> { + w: &'a mut W, +} +impl<'a> BUSERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `COLL` reader - Transmit Collision"] +pub struct COLL_R(crate::FieldReader); +impl COLL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COLL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COLL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COLL` writer - Transmit Collision"] +pub struct COLL_W<'a> { + w: &'a mut W, +} +impl<'a> COLL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXNACK` reader - Received Not Acknowledge"] +pub struct RXNACK_R(crate::FieldReader); +impl RXNACK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXNACK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXNACK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXNACK` writer - Received Not Acknowledge"] +pub struct RXNACK_W<'a> { + w: &'a mut W, +} +impl<'a> RXNACK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `DIR` reader - Read/Write Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Read/Write Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `SR` reader - Repeated Start"] +pub struct SR_R(crate::FieldReader); +impl SR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SR` writer - Repeated Start"] +pub struct SR_W<'a> { + w: &'a mut W, +} +impl<'a> SR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `LOWTOUT` reader - SCL Low Timeout"] +pub struct LOWTOUT_R(crate::FieldReader); +impl LOWTOUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LOWTOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOWTOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LOWTOUT` writer - SCL Low Timeout"] +pub struct LOWTOUT_W<'a> { + w: &'a mut W, +} +impl<'a> LOWTOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `CLKHOLD` reader - Clock Hold"] +pub struct CLKHOLD_R(crate::FieldReader); +impl CLKHOLD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKHOLD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKHOLD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKHOLD` writer - Clock Hold"] +pub struct CLKHOLD_W<'a> { + w: &'a mut W, +} +impl<'a> CLKHOLD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `SEXTTOUT` reader - Slave SCL Low Extend Timeout"] +pub struct SEXTTOUT_R(crate::FieldReader); +impl SEXTTOUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SEXTTOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEXTTOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEXTTOUT` writer - Slave SCL Low Extend Timeout"] +pub struct SEXTTOUT_W<'a> { + w: &'a mut W, +} +impl<'a> SEXTTOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `HS` reader - High Speed"] +pub struct HS_R(crate::FieldReader); +impl HS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HS` writer - High Speed"] +pub struct HS_W<'a> { + w: &'a mut W, +} +impl<'a> HS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u16 & 0x01) << 10); + self.w + } +} +impl R { + #[doc = "Bit 0 - Bus Error"] + #[inline(always)] + pub fn buserr(&self) -> BUSERR_R { + BUSERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Collision"] + #[inline(always)] + pub fn coll(&self) -> COLL_R { + COLL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Received Not Acknowledge"] + #[inline(always)] + pub fn rxnack(&self) -> RXNACK_R { + RXNACK_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Read/Write Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Repeated Start"] + #[inline(always)] + pub fn sr(&self) -> SR_R { + SR_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 6 - SCL Low Timeout"] + #[inline(always)] + pub fn lowtout(&self) -> LOWTOUT_R { + LOWTOUT_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Clock Hold"] + #[inline(always)] + pub fn clkhold(&self) -> CLKHOLD_R { + CLKHOLD_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 9 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttout(&self) -> SEXTTOUT_R { + SEXTTOUT_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - High Speed"] + #[inline(always)] + pub fn hs(&self) -> HS_R { + HS_R::new(((self.bits >> 10) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Bus Error"] + #[inline(always)] + pub fn buserr(&mut self) -> BUSERR_W { + BUSERR_W { w: self } + } + #[doc = "Bit 1 - Transmit Collision"] + #[inline(always)] + pub fn coll(&mut self) -> COLL_W { + COLL_W { w: self } + } + #[doc = "Bit 2 - Received Not Acknowledge"] + #[inline(always)] + pub fn rxnack(&mut self) -> RXNACK_W { + RXNACK_W { w: self } + } + #[doc = "Bit 3 - Read/Write Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 4 - Repeated Start"] + #[inline(always)] + pub fn sr(&mut self) -> SR_W { + SR_W { w: self } + } + #[doc = "Bit 6 - SCL Low Timeout"] + #[inline(always)] + pub fn lowtout(&mut self) -> LOWTOUT_W { + LOWTOUT_W { w: self } + } + #[doc = "Bit 7 - Clock Hold"] + #[inline(always)] + pub fn clkhold(&mut self) -> CLKHOLD_W { + CLKHOLD_W { w: self } + } + #[doc = "Bit 9 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttout(&mut self) -> SEXTTOUT_W { + SEXTTOUT_W { w: self } + } + #[doc = "Bit 10 - High Speed"] + #[inline(always)] + pub fn hs(&mut self) -> HS_W { + HS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/sercom0/i2cs/syncbusy.rs b/pac/atsamc20j/src/sercom0/i2cs/syncbusy.rs new file mode 100644 index 000000000000..38e2509d9666 --- /dev/null +++ b/pac/atsamc20j/src/sercom0/i2cs/syncbusy.rs @@ -0,0 +1,73 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - SERCOM Enable Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM Enable Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +#[doc = "I2CS Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/sercom0/spim.rs b/pac/atsamc20j/src/sercom0/spim.rs new file mode 100644 index 000000000000..528e38e1b811 --- /dev/null +++ b/pac/atsamc20j/src/sercom0/spim.rs @@ -0,0 +1,44 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "SPIM Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "SPIM Control B"] +pub mod ctrlb; +#[doc = "BAUD register accessor: an alias for `Reg`"] +pub type BAUD = crate::Reg; +#[doc = "SPIM Baud Rate"] +pub mod baud; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "SPIM Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "SPIM Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "SPIM Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "SPIM Status"] +pub mod status; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "SPIM Synchronization Busy"] +pub mod syncbusy; +#[doc = "ADDR register accessor: an alias for `Reg`"] +pub type ADDR = crate::Reg; +#[doc = "SPIM Address"] +pub mod addr; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "SPIM Data"] +pub mod data; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "SPIM Debug Control"] +pub mod dbgctrl; diff --git a/pac/atsamc20j/src/sercom0/spim/addr.rs b/pac/atsamc20j/src/sercom0/spim/addr.rs new file mode 100644 index 000000000000..7c25cd522ea2 --- /dev/null +++ b/pac/atsamc20j/src/sercom0/spim/addr.rs @@ -0,0 +1,140 @@ +#[doc = "Register `ADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ADDR` reader - Address Value"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - Address Value"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +#[doc = "Field `ADDRMASK` reader - Address Mask"] +pub struct ADDRMASK_R(crate::FieldReader); +impl ADDRMASK_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ADDRMASK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDRMASK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDRMASK` writer - Address Mask"] +pub struct ADDRMASK_W<'a> { + w: &'a mut W, +} +impl<'a> ADDRMASK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Address Value"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 16:23 - Address Mask"] + #[inline(always)] + pub fn addrmask(&self) -> ADDRMASK_R { + ADDRMASK_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Address Value"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Bits 16:23 - Address Mask"] + #[inline(always)] + pub fn addrmask(&mut self) -> ADDRMASK_W { + ADDRMASK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [addr](index.html) module"] +pub struct ADDR_SPEC; +impl crate::RegisterSpec for ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [addr::R](R) reader structure"] +impl crate::Readable for ADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [addr::W](W) writer structure"] +impl crate::Writable for ADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ADDR to value 0"] +impl crate::Resettable for ADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/sercom0/spim/baud.rs b/pac/atsamc20j/src/sercom0/spim/baud.rs new file mode 100644 index 000000000000..6bec9ca74355 --- /dev/null +++ b/pac/atsamc20j/src/sercom0/spim/baud.rs @@ -0,0 +1,103 @@ +#[doc = "Register `BAUD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud](index.html) module"] +pub struct BAUD_SPEC; +impl crate::RegisterSpec for BAUD_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [baud::R](R) reader structure"] +impl crate::Readable for BAUD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud::W](W) writer structure"] +impl crate::Writable for BAUD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD to value 0"] +impl crate::Resettable for BAUD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/sercom0/spim/ctrla.rs b/pac/atsamc20j/src/sercom0/spim/ctrla.rs new file mode 100644 index 000000000000..44028f8cbdd7 --- /dev/null +++ b/pac/atsamc20j/src/sercom0/spim/ctrla.rs @@ -0,0 +1,992 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: USART with external clock"] + USART_EXT_CLK = 0, + #[doc = "1: USART with internal clock"] + USART_INT_CLK = 1, + #[doc = "2: SPI in slave operation"] + SPI_SLAVE = 2, + #[doc = "3: SPI in master operation"] + SPI_MASTER = 3, + #[doc = "4: I2C slave operation"] + I2C_SLAVE = 4, + #[doc = "5: I2C master operation"] + I2C_MASTER = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::USART_EXT_CLK), + 1 => Some(MODE_A::USART_INT_CLK), + 2 => Some(MODE_A::SPI_SLAVE), + 3 => Some(MODE_A::SPI_MASTER), + 4 => Some(MODE_A::I2C_SLAVE), + 5 => Some(MODE_A::I2C_MASTER), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_EXT_CLK`"] + #[inline(always)] + pub fn is_usart_ext_clk(&self) -> bool { + **self == MODE_A::USART_EXT_CLK + } + #[doc = "Checks if the value of the field is `USART_INT_CLK`"] + #[inline(always)] + pub fn is_usart_int_clk(&self) -> bool { + **self == MODE_A::USART_INT_CLK + } + #[doc = "Checks if the value of the field is `SPI_SLAVE`"] + #[inline(always)] + pub fn is_spi_slave(&self) -> bool { + **self == MODE_A::SPI_SLAVE + } + #[doc = "Checks if the value of the field is `SPI_MASTER`"] + #[inline(always)] + pub fn is_spi_master(&self) -> bool { + **self == MODE_A::SPI_MASTER + } + #[doc = "Checks if the value of the field is `I2C_SLAVE`"] + #[inline(always)] + pub fn is_i2c_slave(&self) -> bool { + **self == MODE_A::I2C_SLAVE + } + #[doc = "Checks if the value of the field is `I2C_MASTER`"] + #[inline(always)] + pub fn is_i2c_master(&self) -> bool { + **self == MODE_A::I2C_MASTER + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART with external clock"] + #[inline(always)] + pub fn usart_ext_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_EXT_CLK) + } + #[doc = "USART with internal clock"] + #[inline(always)] + pub fn usart_int_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_INT_CLK) + } + #[doc = "SPI in slave operation"] + #[inline(always)] + pub fn spi_slave(self) -> &'a mut W { + self.variant(MODE_A::SPI_SLAVE) + } + #[doc = "SPI in master operation"] + #[inline(always)] + pub fn spi_master(self) -> &'a mut W { + self.variant(MODE_A::SPI_MASTER) + } + #[doc = "I2C slave operation"] + #[inline(always)] + pub fn i2c_slave(self) -> &'a mut W { + self.variant(MODE_A::I2C_SLAVE) + } + #[doc = "I2C master operation"] + #[inline(always)] + pub fn i2c_master(self) -> &'a mut W { + self.variant(MODE_A::I2C_MASTER) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 2)) | ((value as u32 & 0x07) << 2); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `IBON` reader - Immediate Buffer Overflow Notification"] +pub struct IBON_R(crate::FieldReader); +impl IBON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IBON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IBON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IBON` writer - Immediate Buffer Overflow Notification"] +pub struct IBON_W<'a> { + w: &'a mut W, +} +impl<'a> IBON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Data Out Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DOPO_A { + #[doc = "0: DO on PAD\\[0\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + PAD0 = 0, + #[doc = "1: DO on PAD\\[2\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + PAD1 = 1, + #[doc = "2: DO on PAD\\[3\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + PAD2 = 2, + #[doc = "3: DO on PAD\\[0\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + PAD3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DOPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `DOPO` reader - Data Out Pinout"] +pub struct DOPO_R(crate::FieldReader); +impl DOPO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DOPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DOPO_A { + match self.bits { + 0 => DOPO_A::PAD0, + 1 => DOPO_A::PAD1, + 2 => DOPO_A::PAD2, + 3 => DOPO_A::PAD3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == DOPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD1`"] + #[inline(always)] + pub fn is_pad1(&self) -> bool { + **self == DOPO_A::PAD1 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == DOPO_A::PAD2 + } + #[doc = "Checks if the value of the field is `PAD3`"] + #[inline(always)] + pub fn is_pad3(&self) -> bool { + **self == DOPO_A::PAD3 + } +} +impl core::ops::Deref for DOPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DOPO` writer - Data Out Pinout"] +pub struct DOPO_W<'a> { + w: &'a mut W, +} +impl<'a> DOPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DOPO_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "DO on PAD\\[0\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(DOPO_A::PAD0) + } + #[doc = "DO on PAD\\[2\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + #[inline(always)] + pub fn pad1(self) -> &'a mut W { + self.variant(DOPO_A::PAD1) + } + #[doc = "DO on PAD\\[3\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(DOPO_A::PAD2) + } + #[doc = "DO on PAD\\[0\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + #[inline(always)] + pub fn pad3(self) -> &'a mut W { + self.variant(DOPO_A::PAD3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Data In Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DIPO_A { + #[doc = "0: SERCOM PAD\\[0\\]"] + PAD0 = 0, + #[doc = "1: SERCOM PAD\\[1\\]"] + PAD1 = 1, + #[doc = "2: SERCOM PAD\\[2\\]"] + PAD2 = 2, + #[doc = "3: SERCOM PAD\\[3\\]"] + PAD3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DIPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `DIPO` reader - Data In Pinout"] +pub struct DIPO_R(crate::FieldReader); +impl DIPO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DIPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DIPO_A { + match self.bits { + 0 => DIPO_A::PAD0, + 1 => DIPO_A::PAD1, + 2 => DIPO_A::PAD2, + 3 => DIPO_A::PAD3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == DIPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD1`"] + #[inline(always)] + pub fn is_pad1(&self) -> bool { + **self == DIPO_A::PAD1 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == DIPO_A::PAD2 + } + #[doc = "Checks if the value of the field is `PAD3`"] + #[inline(always)] + pub fn is_pad3(&self) -> bool { + **self == DIPO_A::PAD3 + } +} +impl core::ops::Deref for DIPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIPO` writer - Data In Pinout"] +pub struct DIPO_W<'a> { + w: &'a mut W, +} +impl<'a> DIPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DIPO_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "SERCOM PAD\\[0\\]"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(DIPO_A::PAD0) + } + #[doc = "SERCOM PAD\\[1\\]"] + #[inline(always)] + pub fn pad1(self) -> &'a mut W { + self.variant(DIPO_A::PAD1) + } + #[doc = "SERCOM PAD\\[2\\]"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(DIPO_A::PAD2) + } + #[doc = "SERCOM PAD\\[3\\]"] + #[inline(always)] + pub fn pad3(self) -> &'a mut W { + self.variant(DIPO_A::PAD3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 20)) | ((value as u32 & 0x03) << 20); + self.w + } +} +#[doc = "Frame Format\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FORM_A { + #[doc = "0: SPI Frame"] + SPI_FRAME = 0, + #[doc = "2: SPI Frame with Addr"] + SPI_FRAME_WITH_ADDR = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FORM_A) -> Self { + variant as _ + } +} +#[doc = "Field `FORM` reader - Frame Format"] +pub struct FORM_R(crate::FieldReader); +impl FORM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FORM_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(FORM_A::SPI_FRAME), + 2 => Some(FORM_A::SPI_FRAME_WITH_ADDR), + _ => None, + } + } + #[doc = "Checks if the value of the field is `SPI_FRAME`"] + #[inline(always)] + pub fn is_spi_frame(&self) -> bool { + **self == FORM_A::SPI_FRAME + } + #[doc = "Checks if the value of the field is `SPI_FRAME_WITH_ADDR`"] + #[inline(always)] + pub fn is_spi_frame_with_addr(&self) -> bool { + **self == FORM_A::SPI_FRAME_WITH_ADDR + } +} +impl core::ops::Deref for FORM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FORM` writer - Frame Format"] +pub struct FORM_W<'a> { + w: &'a mut W, +} +impl<'a> FORM_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FORM_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "SPI Frame"] + #[inline(always)] + pub fn spi_frame(self) -> &'a mut W { + self.variant(FORM_A::SPI_FRAME) + } + #[doc = "SPI Frame with Addr"] + #[inline(always)] + pub fn spi_frame_with_addr(self) -> &'a mut W { + self.variant(FORM_A::SPI_FRAME_WITH_ADDR) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Clock Phase\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CPHA_A { + #[doc = "0: The data is sampled on a leading SCK edge and changed on a trailing SCK edge"] + LEADING_EDGE = 0, + #[doc = "1: The data is sampled on a trailing SCK edge and changed on a leading SCK edge"] + TRAILING_EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CPHA_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CPHA` reader - Clock Phase"] +pub struct CPHA_R(crate::FieldReader); +impl CPHA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPHA_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CPHA_A { + match self.bits { + false => CPHA_A::LEADING_EDGE, + true => CPHA_A::TRAILING_EDGE, + } + } + #[doc = "Checks if the value of the field is `LEADING_EDGE`"] + #[inline(always)] + pub fn is_leading_edge(&self) -> bool { + **self == CPHA_A::LEADING_EDGE + } + #[doc = "Checks if the value of the field is `TRAILING_EDGE`"] + #[inline(always)] + pub fn is_trailing_edge(&self) -> bool { + **self == CPHA_A::TRAILING_EDGE + } +} +impl core::ops::Deref for CPHA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPHA` writer - Clock Phase"] +pub struct CPHA_W<'a> { + w: &'a mut W, +} +impl<'a> CPHA_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CPHA_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "The data is sampled on a leading SCK edge and changed on a trailing SCK edge"] + #[inline(always)] + pub fn leading_edge(self) -> &'a mut W { + self.variant(CPHA_A::LEADING_EDGE) + } + #[doc = "The data is sampled on a trailing SCK edge and changed on a leading SCK edge"] + #[inline(always)] + pub fn trailing_edge(self) -> &'a mut W { + self.variant(CPHA_A::TRAILING_EDGE) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Clock Polarity\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CPOL_A { + #[doc = "0: SCK is low when idle"] + IDLE_LOW = 0, + #[doc = "1: SCK is high when idle"] + IDLE_HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CPOL_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CPOL` reader - Clock Polarity"] +pub struct CPOL_R(crate::FieldReader); +impl CPOL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPOL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CPOL_A { + match self.bits { + false => CPOL_A::IDLE_LOW, + true => CPOL_A::IDLE_HIGH, + } + } + #[doc = "Checks if the value of the field is `IDLE_LOW`"] + #[inline(always)] + pub fn is_idle_low(&self) -> bool { + **self == CPOL_A::IDLE_LOW + } + #[doc = "Checks if the value of the field is `IDLE_HIGH`"] + #[inline(always)] + pub fn is_idle_high(&self) -> bool { + **self == CPOL_A::IDLE_HIGH + } +} +impl core::ops::Deref for CPOL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPOL` writer - Clock Polarity"] +pub struct CPOL_W<'a> { + w: &'a mut W, +} +impl<'a> CPOL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CPOL_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "SCK is low when idle"] + #[inline(always)] + pub fn idle_low(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_LOW) + } + #[doc = "SCK is high when idle"] + #[inline(always)] + pub fn idle_high(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_HIGH) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29); + self.w + } +} +#[doc = "Data Order\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum DORD_A { + #[doc = "0: MSB is transferred first"] + MSB = 0, + #[doc = "1: LSB is transferred first"] + LSB = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DORD_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DORD` reader - Data Order"] +pub struct DORD_R(crate::FieldReader); +impl DORD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DORD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DORD_A { + match self.bits { + false => DORD_A::MSB, + true => DORD_A::LSB, + } + } + #[doc = "Checks if the value of the field is `MSB`"] + #[inline(always)] + pub fn is_msb(&self) -> bool { + **self == DORD_A::MSB + } + #[doc = "Checks if the value of the field is `LSB`"] + #[inline(always)] + pub fn is_lsb(&self) -> bool { + **self == DORD_A::LSB + } +} +impl core::ops::Deref for DORD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DORD` writer - Data Order"] +pub struct DORD_W<'a> { + w: &'a mut W, +} +impl<'a> DORD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DORD_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "MSB is transferred first"] + #[inline(always)] + pub fn msb(self) -> &'a mut W { + self.variant(DORD_A::MSB) + } + #[doc = "LSB is transferred first"] + #[inline(always)] + pub fn lsb(self) -> &'a mut W { + self.variant(DORD_A::LSB) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x07) as u8) + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&self) -> IBON_R { + IBON_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bits 16:17 - Data Out Pinout"] + #[inline(always)] + pub fn dopo(&self) -> DOPO_R { + DOPO_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bits 20:21 - Data In Pinout"] + #[inline(always)] + pub fn dipo(&self) -> DIPO_R { + DIPO_R::new(((self.bits >> 20) & 0x03) as u8) + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&self) -> FORM_R { + FORM_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 28 - Clock Phase"] + #[inline(always)] + pub fn cpha(&self) -> CPHA_R { + CPHA_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&self) -> CPOL_R { + CPOL_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&self) -> DORD_R { + DORD_R::new(((self.bits >> 30) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&mut self) -> IBON_W { + IBON_W { w: self } + } + #[doc = "Bits 16:17 - Data Out Pinout"] + #[inline(always)] + pub fn dopo(&mut self) -> DOPO_W { + DOPO_W { w: self } + } + #[doc = "Bits 20:21 - Data In Pinout"] + #[inline(always)] + pub fn dipo(&mut self) -> DIPO_W { + DIPO_W { w: self } + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&mut self) -> FORM_W { + FORM_W { w: self } + } + #[doc = "Bit 28 - Clock Phase"] + #[inline(always)] + pub fn cpha(&mut self) -> CPHA_W { + CPHA_W { w: self } + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&mut self) -> CPOL_W { + CPOL_W { w: self } + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&mut self) -> DORD_W { + DORD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/sercom0/spim/ctrlb.rs b/pac/atsamc20j/src/sercom0/spim/ctrlb.rs new file mode 100644 index 000000000000..3d94f824ce83 --- /dev/null +++ b/pac/atsamc20j/src/sercom0/spim/ctrlb.rs @@ -0,0 +1,439 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Character Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CHSIZE_A { + #[doc = "0: 8 bits"] + _8_BIT = 0, + #[doc = "1: 9 bits"] + _9_BIT = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CHSIZE_A) -> Self { + variant as _ + } +} +#[doc = "Field `CHSIZE` reader - Character Size"] +pub struct CHSIZE_R(crate::FieldReader); +impl CHSIZE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CHSIZE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CHSIZE_A::_8_BIT), + 1 => Some(CHSIZE_A::_9_BIT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_8_BIT`"] + #[inline(always)] + pub fn is_8_bit(&self) -> bool { + **self == CHSIZE_A::_8_BIT + } + #[doc = "Checks if the value of the field is `_9_BIT`"] + #[inline(always)] + pub fn is_9_bit(&self) -> bool { + **self == CHSIZE_A::_9_BIT + } +} +impl core::ops::Deref for CHSIZE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHSIZE` writer - Character Size"] +pub struct CHSIZE_W<'a> { + w: &'a mut W, +} +impl<'a> CHSIZE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CHSIZE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8 bits"] + #[inline(always)] + pub fn _8_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_8_BIT) + } + #[doc = "9 bits"] + #[inline(always)] + pub fn _9_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_9_BIT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Field `PLOADEN` reader - Data Preload Enable"] +pub struct PLOADEN_R(crate::FieldReader); +impl PLOADEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PLOADEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PLOADEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PLOADEN` writer - Data Preload Enable"] +pub struct PLOADEN_W<'a> { + w: &'a mut W, +} +impl<'a> PLOADEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `SSDE` reader - Slave Select Low Detect Enable"] +pub struct SSDE_R(crate::FieldReader); +impl SSDE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SSDE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSDE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSDE` writer - Slave Select Low Detect Enable"] +pub struct SSDE_W<'a> { + w: &'a mut W, +} +impl<'a> SSDE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `MSSEN` reader - Master Slave Select Enable"] +pub struct MSSEN_R(crate::FieldReader); +impl MSSEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MSSEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MSSEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MSSEN` writer - Master Slave Select Enable"] +pub struct MSSEN_W<'a> { + w: &'a mut W, +} +impl<'a> MSSEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Address Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum AMODE_A { + #[doc = "0: SPI Address mask"] + MASK = 0, + #[doc = "1: Two unique Addressess"] + _2_ADDRESSES = 1, + #[doc = "2: Address Range"] + RANGE = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: AMODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `AMODE` reader - Address Mode"] +pub struct AMODE_R(crate::FieldReader); +impl AMODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + AMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(AMODE_A::MASK), + 1 => Some(AMODE_A::_2_ADDRESSES), + 2 => Some(AMODE_A::RANGE), + _ => None, + } + } + #[doc = "Checks if the value of the field is `MASK`"] + #[inline(always)] + pub fn is_mask(&self) -> bool { + **self == AMODE_A::MASK + } + #[doc = "Checks if the value of the field is `_2_ADDRESSES`"] + #[inline(always)] + pub fn is_2_addresses(&self) -> bool { + **self == AMODE_A::_2_ADDRESSES + } + #[doc = "Checks if the value of the field is `RANGE`"] + #[inline(always)] + pub fn is_range(&self) -> bool { + **self == AMODE_A::RANGE + } +} +impl core::ops::Deref for AMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AMODE` writer - Address Mode"] +pub struct AMODE_W<'a> { + w: &'a mut W, +} +impl<'a> AMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: AMODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "SPI Address mask"] + #[inline(always)] + pub fn mask(self) -> &'a mut W { + self.variant(AMODE_A::MASK) + } + #[doc = "Two unique Addressess"] + #[inline(always)] + pub fn _2_addresses(self) -> &'a mut W { + self.variant(AMODE_A::_2_ADDRESSES) + } + #[doc = "Address Range"] + #[inline(always)] + pub fn range(self) -> &'a mut W { + self.variant(AMODE_A::RANGE) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 14)) | ((value as u32 & 0x03) << 14); + self.w + } +} +#[doc = "Field `RXEN` reader - Receiver Enable"] +pub struct RXEN_R(crate::FieldReader); +impl RXEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXEN` writer - Receiver Enable"] +pub struct RXEN_W<'a> { + w: &'a mut W, +} +impl<'a> RXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&self) -> CHSIZE_R { + CHSIZE_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 6 - Data Preload Enable"] + #[inline(always)] + pub fn ploaden(&self) -> PLOADEN_R { + PLOADEN_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 9 - Slave Select Low Detect Enable"] + #[inline(always)] + pub fn ssde(&self) -> SSDE_R { + SSDE_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 13 - Master Slave Select Enable"] + #[inline(always)] + pub fn mssen(&self) -> MSSEN_R { + MSSEN_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bits 14:15 - Address Mode"] + #[inline(always)] + pub fn amode(&self) -> AMODE_R { + AMODE_R::new(((self.bits >> 14) & 0x03) as u8) + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&self) -> RXEN_R { + RXEN_R::new(((self.bits >> 17) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&mut self) -> CHSIZE_W { + CHSIZE_W { w: self } + } + #[doc = "Bit 6 - Data Preload Enable"] + #[inline(always)] + pub fn ploaden(&mut self) -> PLOADEN_W { + PLOADEN_W { w: self } + } + #[doc = "Bit 9 - Slave Select Low Detect Enable"] + #[inline(always)] + pub fn ssde(&mut self) -> SSDE_W { + SSDE_W { w: self } + } + #[doc = "Bit 13 - Master Slave Select Enable"] + #[inline(always)] + pub fn mssen(&mut self) -> MSSEN_W { + MSSEN_W { w: self } + } + #[doc = "Bits 14:15 - Address Mode"] + #[inline(always)] + pub fn amode(&mut self) -> AMODE_W { + AMODE_W { w: self } + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&mut self) -> RXEN_W { + RXEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/sercom0/spim/data.rs b/pac/atsamc20j/src/sercom0/spim/data.rs new file mode 100644 index 000000000000..dc9cd020d2a5 --- /dev/null +++ b/pac/atsamc20j/src/sercom0/spim/data.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data Value"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data Value"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01ff) | (value as u32 & 0x01ff); + self.w + } +} +impl R { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new((self.bits & 0x01ff) as u16) + } +} +impl W { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/sercom0/spim/dbgctrl.rs b/pac/atsamc20j/src/sercom0/spim/dbgctrl.rs new file mode 100644 index 000000000000..d9aa7495940c --- /dev/null +++ b/pac/atsamc20j/src/sercom0/spim/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGSTOP` reader - Debug Mode"] +pub struct DBGSTOP_R(crate::FieldReader); +impl DBGSTOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGSTOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGSTOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGSTOP` writer - Debug Mode"] +pub struct DBGSTOP_W<'a> { + w: &'a mut W, +} +impl<'a> DBGSTOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&self) -> DBGSTOP_R { + DBGSTOP_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&mut self) -> DBGSTOP_W { + DBGSTOP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/sercom0/spim/intenclr.rs b/pac/atsamc20j/src/sercom0/spim/intenclr.rs new file mode 100644 index 000000000000..ccab3de4348d --- /dev/null +++ b/pac/atsamc20j/src/sercom0/spim/intenclr.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Disable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Disable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Disable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Disable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Disable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Disable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SSL` reader - Slave Select Low Interrupt Disable"] +pub struct SSL_R(crate::FieldReader); +impl SSL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SSL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSL` writer - Slave Select Low Interrupt Disable"] +pub struct SSL_W<'a> { + w: &'a mut W, +} +impl<'a> SSL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Disable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Disable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Slave Select Low Interrupt Disable"] + #[inline(always)] + pub fn ssl(&self) -> SSL_R { + SSL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Slave Select Low Interrupt Disable"] + #[inline(always)] + pub fn ssl(&mut self) -> SSL_W { + SSL_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/sercom0/spim/intenset.rs b/pac/atsamc20j/src/sercom0/spim/intenset.rs new file mode 100644 index 000000000000..d9779cf897c2 --- /dev/null +++ b/pac/atsamc20j/src/sercom0/spim/intenset.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Enable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Enable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Enable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Enable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Enable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Enable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SSL` reader - Slave Select Low Interrupt Enable"] +pub struct SSL_R(crate::FieldReader); +impl SSL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SSL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSL` writer - Slave Select Low Interrupt Enable"] +pub struct SSL_W<'a> { + w: &'a mut W, +} +impl<'a> SSL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Slave Select Low Interrupt Enable"] + #[inline(always)] + pub fn ssl(&self) -> SSL_R { + SSL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Slave Select Low Interrupt Enable"] + #[inline(always)] + pub fn ssl(&mut self) -> SSL_W { + SSL_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/sercom0/spim/intflag.rs b/pac/atsamc20j/src/sercom0/spim/intflag.rs new file mode 100644 index 000000000000..e9bc10c271b8 --- /dev/null +++ b/pac/atsamc20j/src/sercom0/spim/intflag.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SSL` reader - Slave Select Low Interrupt Flag"] +pub struct SSL_R(crate::FieldReader); +impl SSL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SSL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSL` writer - Slave Select Low Interrupt Flag"] +pub struct SSL_W<'a> { + w: &'a mut W, +} +impl<'a> SSL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Slave Select Low Interrupt Flag"] + #[inline(always)] + pub fn ssl(&self) -> SSL_R { + SSL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Slave Select Low Interrupt Flag"] + #[inline(always)] + pub fn ssl(&mut self) -> SSL_W { + SSL_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/sercom0/spim/status.rs b/pac/atsamc20j/src/sercom0/spim/status.rs new file mode 100644 index 000000000000..9919460bf0e2 --- /dev/null +++ b/pac/atsamc20j/src/sercom0/spim/status.rs @@ -0,0 +1,113 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BUFOVF` reader - Buffer Overflow"] +pub struct BUFOVF_R(crate::FieldReader); +impl BUFOVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUFOVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUFOVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUFOVF` writer - Buffer Overflow"] +pub struct BUFOVF_W<'a> { + w: &'a mut W, +} +impl<'a> BUFOVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&self) -> BUFOVF_R { + BUFOVF_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&mut self) -> BUFOVF_W { + BUFOVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/sercom0/spim/syncbusy.rs b/pac/atsamc20j/src/sercom0/spim/syncbusy.rs new file mode 100644 index 000000000000..bee13adf7084 --- /dev/null +++ b/pac/atsamc20j/src/sercom0/spim/syncbusy.rs @@ -0,0 +1,93 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - SERCOM Enable Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLB` reader - CTRLB Synchronization Busy"] +pub struct CTRLB_R(crate::FieldReader); +impl CTRLB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM Enable Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - CTRLB Synchronization Busy"] + #[inline(always)] + pub fn ctrlb(&self) -> CTRLB_R { + CTRLB_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +#[doc = "SPIM Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/sercom0/spis.rs b/pac/atsamc20j/src/sercom0/spis.rs new file mode 100644 index 000000000000..eed10c90c460 --- /dev/null +++ b/pac/atsamc20j/src/sercom0/spis.rs @@ -0,0 +1,44 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "SPIS Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "SPIS Control B"] +pub mod ctrlb; +#[doc = "BAUD register accessor: an alias for `Reg`"] +pub type BAUD = crate::Reg; +#[doc = "SPIS Baud Rate"] +pub mod baud; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "SPIS Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "SPIS Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "SPIS Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "SPIS Status"] +pub mod status; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "SPIS Synchronization Busy"] +pub mod syncbusy; +#[doc = "ADDR register accessor: an alias for `Reg`"] +pub type ADDR = crate::Reg; +#[doc = "SPIS Address"] +pub mod addr; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "SPIS Data"] +pub mod data; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "SPIS Debug Control"] +pub mod dbgctrl; diff --git a/pac/atsamc20j/src/sercom0/spis/addr.rs b/pac/atsamc20j/src/sercom0/spis/addr.rs new file mode 100644 index 000000000000..5fca0a698bfe --- /dev/null +++ b/pac/atsamc20j/src/sercom0/spis/addr.rs @@ -0,0 +1,140 @@ +#[doc = "Register `ADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ADDR` reader - Address Value"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - Address Value"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +#[doc = "Field `ADDRMASK` reader - Address Mask"] +pub struct ADDRMASK_R(crate::FieldReader); +impl ADDRMASK_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ADDRMASK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDRMASK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDRMASK` writer - Address Mask"] +pub struct ADDRMASK_W<'a> { + w: &'a mut W, +} +impl<'a> ADDRMASK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Address Value"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 16:23 - Address Mask"] + #[inline(always)] + pub fn addrmask(&self) -> ADDRMASK_R { + ADDRMASK_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Address Value"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Bits 16:23 - Address Mask"] + #[inline(always)] + pub fn addrmask(&mut self) -> ADDRMASK_W { + ADDRMASK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [addr](index.html) module"] +pub struct ADDR_SPEC; +impl crate::RegisterSpec for ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [addr::R](R) reader structure"] +impl crate::Readable for ADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [addr::W](W) writer structure"] +impl crate::Writable for ADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ADDR to value 0"] +impl crate::Resettable for ADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/sercom0/spis/baud.rs b/pac/atsamc20j/src/sercom0/spis/baud.rs new file mode 100644 index 000000000000..eeee4cf633e5 --- /dev/null +++ b/pac/atsamc20j/src/sercom0/spis/baud.rs @@ -0,0 +1,103 @@ +#[doc = "Register `BAUD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud](index.html) module"] +pub struct BAUD_SPEC; +impl crate::RegisterSpec for BAUD_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [baud::R](R) reader structure"] +impl crate::Readable for BAUD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud::W](W) writer structure"] +impl crate::Writable for BAUD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD to value 0"] +impl crate::Resettable for BAUD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/sercom0/spis/ctrla.rs b/pac/atsamc20j/src/sercom0/spis/ctrla.rs new file mode 100644 index 000000000000..6151433a8529 --- /dev/null +++ b/pac/atsamc20j/src/sercom0/spis/ctrla.rs @@ -0,0 +1,992 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: USART with external clock"] + USART_EXT_CLK = 0, + #[doc = "1: USART with internal clock"] + USART_INT_CLK = 1, + #[doc = "2: SPI in slave operation"] + SPI_SLAVE = 2, + #[doc = "3: SPI in master operation"] + SPI_MASTER = 3, + #[doc = "4: I2C slave operation"] + I2C_SLAVE = 4, + #[doc = "5: I2C master operation"] + I2C_MASTER = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::USART_EXT_CLK), + 1 => Some(MODE_A::USART_INT_CLK), + 2 => Some(MODE_A::SPI_SLAVE), + 3 => Some(MODE_A::SPI_MASTER), + 4 => Some(MODE_A::I2C_SLAVE), + 5 => Some(MODE_A::I2C_MASTER), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_EXT_CLK`"] + #[inline(always)] + pub fn is_usart_ext_clk(&self) -> bool { + **self == MODE_A::USART_EXT_CLK + } + #[doc = "Checks if the value of the field is `USART_INT_CLK`"] + #[inline(always)] + pub fn is_usart_int_clk(&self) -> bool { + **self == MODE_A::USART_INT_CLK + } + #[doc = "Checks if the value of the field is `SPI_SLAVE`"] + #[inline(always)] + pub fn is_spi_slave(&self) -> bool { + **self == MODE_A::SPI_SLAVE + } + #[doc = "Checks if the value of the field is `SPI_MASTER`"] + #[inline(always)] + pub fn is_spi_master(&self) -> bool { + **self == MODE_A::SPI_MASTER + } + #[doc = "Checks if the value of the field is `I2C_SLAVE`"] + #[inline(always)] + pub fn is_i2c_slave(&self) -> bool { + **self == MODE_A::I2C_SLAVE + } + #[doc = "Checks if the value of the field is `I2C_MASTER`"] + #[inline(always)] + pub fn is_i2c_master(&self) -> bool { + **self == MODE_A::I2C_MASTER + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART with external clock"] + #[inline(always)] + pub fn usart_ext_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_EXT_CLK) + } + #[doc = "USART with internal clock"] + #[inline(always)] + pub fn usart_int_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_INT_CLK) + } + #[doc = "SPI in slave operation"] + #[inline(always)] + pub fn spi_slave(self) -> &'a mut W { + self.variant(MODE_A::SPI_SLAVE) + } + #[doc = "SPI in master operation"] + #[inline(always)] + pub fn spi_master(self) -> &'a mut W { + self.variant(MODE_A::SPI_MASTER) + } + #[doc = "I2C slave operation"] + #[inline(always)] + pub fn i2c_slave(self) -> &'a mut W { + self.variant(MODE_A::I2C_SLAVE) + } + #[doc = "I2C master operation"] + #[inline(always)] + pub fn i2c_master(self) -> &'a mut W { + self.variant(MODE_A::I2C_MASTER) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 2)) | ((value as u32 & 0x07) << 2); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `IBON` reader - Immediate Buffer Overflow Notification"] +pub struct IBON_R(crate::FieldReader); +impl IBON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IBON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IBON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IBON` writer - Immediate Buffer Overflow Notification"] +pub struct IBON_W<'a> { + w: &'a mut W, +} +impl<'a> IBON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Data Out Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DOPO_A { + #[doc = "0: DO on PAD\\[0\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + PAD0 = 0, + #[doc = "1: DO on PAD\\[2\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + PAD1 = 1, + #[doc = "2: DO on PAD\\[3\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + PAD2 = 2, + #[doc = "3: DO on PAD\\[0\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + PAD3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DOPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `DOPO` reader - Data Out Pinout"] +pub struct DOPO_R(crate::FieldReader); +impl DOPO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DOPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DOPO_A { + match self.bits { + 0 => DOPO_A::PAD0, + 1 => DOPO_A::PAD1, + 2 => DOPO_A::PAD2, + 3 => DOPO_A::PAD3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == DOPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD1`"] + #[inline(always)] + pub fn is_pad1(&self) -> bool { + **self == DOPO_A::PAD1 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == DOPO_A::PAD2 + } + #[doc = "Checks if the value of the field is `PAD3`"] + #[inline(always)] + pub fn is_pad3(&self) -> bool { + **self == DOPO_A::PAD3 + } +} +impl core::ops::Deref for DOPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DOPO` writer - Data Out Pinout"] +pub struct DOPO_W<'a> { + w: &'a mut W, +} +impl<'a> DOPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DOPO_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "DO on PAD\\[0\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(DOPO_A::PAD0) + } + #[doc = "DO on PAD\\[2\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + #[inline(always)] + pub fn pad1(self) -> &'a mut W { + self.variant(DOPO_A::PAD1) + } + #[doc = "DO on PAD\\[3\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(DOPO_A::PAD2) + } + #[doc = "DO on PAD\\[0\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + #[inline(always)] + pub fn pad3(self) -> &'a mut W { + self.variant(DOPO_A::PAD3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Data In Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DIPO_A { + #[doc = "0: SERCOM PAD\\[0\\]"] + PAD0 = 0, + #[doc = "1: SERCOM PAD\\[1\\]"] + PAD1 = 1, + #[doc = "2: SERCOM PAD\\[2\\]"] + PAD2 = 2, + #[doc = "3: SERCOM PAD\\[3\\]"] + PAD3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DIPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `DIPO` reader - Data In Pinout"] +pub struct DIPO_R(crate::FieldReader); +impl DIPO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DIPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DIPO_A { + match self.bits { + 0 => DIPO_A::PAD0, + 1 => DIPO_A::PAD1, + 2 => DIPO_A::PAD2, + 3 => DIPO_A::PAD3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == DIPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD1`"] + #[inline(always)] + pub fn is_pad1(&self) -> bool { + **self == DIPO_A::PAD1 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == DIPO_A::PAD2 + } + #[doc = "Checks if the value of the field is `PAD3`"] + #[inline(always)] + pub fn is_pad3(&self) -> bool { + **self == DIPO_A::PAD3 + } +} +impl core::ops::Deref for DIPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIPO` writer - Data In Pinout"] +pub struct DIPO_W<'a> { + w: &'a mut W, +} +impl<'a> DIPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DIPO_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "SERCOM PAD\\[0\\]"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(DIPO_A::PAD0) + } + #[doc = "SERCOM PAD\\[1\\]"] + #[inline(always)] + pub fn pad1(self) -> &'a mut W { + self.variant(DIPO_A::PAD1) + } + #[doc = "SERCOM PAD\\[2\\]"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(DIPO_A::PAD2) + } + #[doc = "SERCOM PAD\\[3\\]"] + #[inline(always)] + pub fn pad3(self) -> &'a mut W { + self.variant(DIPO_A::PAD3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 20)) | ((value as u32 & 0x03) << 20); + self.w + } +} +#[doc = "Frame Format\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FORM_A { + #[doc = "0: SPI Frame"] + SPI_FRAME = 0, + #[doc = "2: SPI Frame with Addr"] + SPI_FRAME_WITH_ADDR = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FORM_A) -> Self { + variant as _ + } +} +#[doc = "Field `FORM` reader - Frame Format"] +pub struct FORM_R(crate::FieldReader); +impl FORM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FORM_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(FORM_A::SPI_FRAME), + 2 => Some(FORM_A::SPI_FRAME_WITH_ADDR), + _ => None, + } + } + #[doc = "Checks if the value of the field is `SPI_FRAME`"] + #[inline(always)] + pub fn is_spi_frame(&self) -> bool { + **self == FORM_A::SPI_FRAME + } + #[doc = "Checks if the value of the field is `SPI_FRAME_WITH_ADDR`"] + #[inline(always)] + pub fn is_spi_frame_with_addr(&self) -> bool { + **self == FORM_A::SPI_FRAME_WITH_ADDR + } +} +impl core::ops::Deref for FORM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FORM` writer - Frame Format"] +pub struct FORM_W<'a> { + w: &'a mut W, +} +impl<'a> FORM_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FORM_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "SPI Frame"] + #[inline(always)] + pub fn spi_frame(self) -> &'a mut W { + self.variant(FORM_A::SPI_FRAME) + } + #[doc = "SPI Frame with Addr"] + #[inline(always)] + pub fn spi_frame_with_addr(self) -> &'a mut W { + self.variant(FORM_A::SPI_FRAME_WITH_ADDR) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Clock Phase\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CPHA_A { + #[doc = "0: The data is sampled on a leading SCK edge and changed on a trailing SCK edge"] + LEADING_EDGE = 0, + #[doc = "1: The data is sampled on a trailing SCK edge and changed on a leading SCK edge"] + TRAILING_EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CPHA_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CPHA` reader - Clock Phase"] +pub struct CPHA_R(crate::FieldReader); +impl CPHA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPHA_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CPHA_A { + match self.bits { + false => CPHA_A::LEADING_EDGE, + true => CPHA_A::TRAILING_EDGE, + } + } + #[doc = "Checks if the value of the field is `LEADING_EDGE`"] + #[inline(always)] + pub fn is_leading_edge(&self) -> bool { + **self == CPHA_A::LEADING_EDGE + } + #[doc = "Checks if the value of the field is `TRAILING_EDGE`"] + #[inline(always)] + pub fn is_trailing_edge(&self) -> bool { + **self == CPHA_A::TRAILING_EDGE + } +} +impl core::ops::Deref for CPHA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPHA` writer - Clock Phase"] +pub struct CPHA_W<'a> { + w: &'a mut W, +} +impl<'a> CPHA_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CPHA_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "The data is sampled on a leading SCK edge and changed on a trailing SCK edge"] + #[inline(always)] + pub fn leading_edge(self) -> &'a mut W { + self.variant(CPHA_A::LEADING_EDGE) + } + #[doc = "The data is sampled on a trailing SCK edge and changed on a leading SCK edge"] + #[inline(always)] + pub fn trailing_edge(self) -> &'a mut W { + self.variant(CPHA_A::TRAILING_EDGE) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Clock Polarity\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CPOL_A { + #[doc = "0: SCK is low when idle"] + IDLE_LOW = 0, + #[doc = "1: SCK is high when idle"] + IDLE_HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CPOL_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CPOL` reader - Clock Polarity"] +pub struct CPOL_R(crate::FieldReader); +impl CPOL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPOL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CPOL_A { + match self.bits { + false => CPOL_A::IDLE_LOW, + true => CPOL_A::IDLE_HIGH, + } + } + #[doc = "Checks if the value of the field is `IDLE_LOW`"] + #[inline(always)] + pub fn is_idle_low(&self) -> bool { + **self == CPOL_A::IDLE_LOW + } + #[doc = "Checks if the value of the field is `IDLE_HIGH`"] + #[inline(always)] + pub fn is_idle_high(&self) -> bool { + **self == CPOL_A::IDLE_HIGH + } +} +impl core::ops::Deref for CPOL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPOL` writer - Clock Polarity"] +pub struct CPOL_W<'a> { + w: &'a mut W, +} +impl<'a> CPOL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CPOL_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "SCK is low when idle"] + #[inline(always)] + pub fn idle_low(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_LOW) + } + #[doc = "SCK is high when idle"] + #[inline(always)] + pub fn idle_high(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_HIGH) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29); + self.w + } +} +#[doc = "Data Order\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum DORD_A { + #[doc = "0: MSB is transferred first"] + MSB = 0, + #[doc = "1: LSB is transferred first"] + LSB = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DORD_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DORD` reader - Data Order"] +pub struct DORD_R(crate::FieldReader); +impl DORD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DORD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DORD_A { + match self.bits { + false => DORD_A::MSB, + true => DORD_A::LSB, + } + } + #[doc = "Checks if the value of the field is `MSB`"] + #[inline(always)] + pub fn is_msb(&self) -> bool { + **self == DORD_A::MSB + } + #[doc = "Checks if the value of the field is `LSB`"] + #[inline(always)] + pub fn is_lsb(&self) -> bool { + **self == DORD_A::LSB + } +} +impl core::ops::Deref for DORD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DORD` writer - Data Order"] +pub struct DORD_W<'a> { + w: &'a mut W, +} +impl<'a> DORD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DORD_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "MSB is transferred first"] + #[inline(always)] + pub fn msb(self) -> &'a mut W { + self.variant(DORD_A::MSB) + } + #[doc = "LSB is transferred first"] + #[inline(always)] + pub fn lsb(self) -> &'a mut W { + self.variant(DORD_A::LSB) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x07) as u8) + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&self) -> IBON_R { + IBON_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bits 16:17 - Data Out Pinout"] + #[inline(always)] + pub fn dopo(&self) -> DOPO_R { + DOPO_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bits 20:21 - Data In Pinout"] + #[inline(always)] + pub fn dipo(&self) -> DIPO_R { + DIPO_R::new(((self.bits >> 20) & 0x03) as u8) + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&self) -> FORM_R { + FORM_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 28 - Clock Phase"] + #[inline(always)] + pub fn cpha(&self) -> CPHA_R { + CPHA_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&self) -> CPOL_R { + CPOL_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&self) -> DORD_R { + DORD_R::new(((self.bits >> 30) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&mut self) -> IBON_W { + IBON_W { w: self } + } + #[doc = "Bits 16:17 - Data Out Pinout"] + #[inline(always)] + pub fn dopo(&mut self) -> DOPO_W { + DOPO_W { w: self } + } + #[doc = "Bits 20:21 - Data In Pinout"] + #[inline(always)] + pub fn dipo(&mut self) -> DIPO_W { + DIPO_W { w: self } + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&mut self) -> FORM_W { + FORM_W { w: self } + } + #[doc = "Bit 28 - Clock Phase"] + #[inline(always)] + pub fn cpha(&mut self) -> CPHA_W { + CPHA_W { w: self } + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&mut self) -> CPOL_W { + CPOL_W { w: self } + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&mut self) -> DORD_W { + DORD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/sercom0/spis/ctrlb.rs b/pac/atsamc20j/src/sercom0/spis/ctrlb.rs new file mode 100644 index 000000000000..ccb70582cf34 --- /dev/null +++ b/pac/atsamc20j/src/sercom0/spis/ctrlb.rs @@ -0,0 +1,439 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Character Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CHSIZE_A { + #[doc = "0: 8 bits"] + _8_BIT = 0, + #[doc = "1: 9 bits"] + _9_BIT = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CHSIZE_A) -> Self { + variant as _ + } +} +#[doc = "Field `CHSIZE` reader - Character Size"] +pub struct CHSIZE_R(crate::FieldReader); +impl CHSIZE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CHSIZE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CHSIZE_A::_8_BIT), + 1 => Some(CHSIZE_A::_9_BIT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_8_BIT`"] + #[inline(always)] + pub fn is_8_bit(&self) -> bool { + **self == CHSIZE_A::_8_BIT + } + #[doc = "Checks if the value of the field is `_9_BIT`"] + #[inline(always)] + pub fn is_9_bit(&self) -> bool { + **self == CHSIZE_A::_9_BIT + } +} +impl core::ops::Deref for CHSIZE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHSIZE` writer - Character Size"] +pub struct CHSIZE_W<'a> { + w: &'a mut W, +} +impl<'a> CHSIZE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CHSIZE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8 bits"] + #[inline(always)] + pub fn _8_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_8_BIT) + } + #[doc = "9 bits"] + #[inline(always)] + pub fn _9_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_9_BIT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Field `PLOADEN` reader - Data Preload Enable"] +pub struct PLOADEN_R(crate::FieldReader); +impl PLOADEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PLOADEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PLOADEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PLOADEN` writer - Data Preload Enable"] +pub struct PLOADEN_W<'a> { + w: &'a mut W, +} +impl<'a> PLOADEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `SSDE` reader - Slave Select Low Detect Enable"] +pub struct SSDE_R(crate::FieldReader); +impl SSDE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SSDE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSDE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSDE` writer - Slave Select Low Detect Enable"] +pub struct SSDE_W<'a> { + w: &'a mut W, +} +impl<'a> SSDE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `MSSEN` reader - Master Slave Select Enable"] +pub struct MSSEN_R(crate::FieldReader); +impl MSSEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MSSEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MSSEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MSSEN` writer - Master Slave Select Enable"] +pub struct MSSEN_W<'a> { + w: &'a mut W, +} +impl<'a> MSSEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Address Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum AMODE_A { + #[doc = "0: SPI Address mask"] + MASK = 0, + #[doc = "1: Two unique Addressess"] + _2_ADDRESSES = 1, + #[doc = "2: Address Range"] + RANGE = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: AMODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `AMODE` reader - Address Mode"] +pub struct AMODE_R(crate::FieldReader); +impl AMODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + AMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(AMODE_A::MASK), + 1 => Some(AMODE_A::_2_ADDRESSES), + 2 => Some(AMODE_A::RANGE), + _ => None, + } + } + #[doc = "Checks if the value of the field is `MASK`"] + #[inline(always)] + pub fn is_mask(&self) -> bool { + **self == AMODE_A::MASK + } + #[doc = "Checks if the value of the field is `_2_ADDRESSES`"] + #[inline(always)] + pub fn is_2_addresses(&self) -> bool { + **self == AMODE_A::_2_ADDRESSES + } + #[doc = "Checks if the value of the field is `RANGE`"] + #[inline(always)] + pub fn is_range(&self) -> bool { + **self == AMODE_A::RANGE + } +} +impl core::ops::Deref for AMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AMODE` writer - Address Mode"] +pub struct AMODE_W<'a> { + w: &'a mut W, +} +impl<'a> AMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: AMODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "SPI Address mask"] + #[inline(always)] + pub fn mask(self) -> &'a mut W { + self.variant(AMODE_A::MASK) + } + #[doc = "Two unique Addressess"] + #[inline(always)] + pub fn _2_addresses(self) -> &'a mut W { + self.variant(AMODE_A::_2_ADDRESSES) + } + #[doc = "Address Range"] + #[inline(always)] + pub fn range(self) -> &'a mut W { + self.variant(AMODE_A::RANGE) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 14)) | ((value as u32 & 0x03) << 14); + self.w + } +} +#[doc = "Field `RXEN` reader - Receiver Enable"] +pub struct RXEN_R(crate::FieldReader); +impl RXEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXEN` writer - Receiver Enable"] +pub struct RXEN_W<'a> { + w: &'a mut W, +} +impl<'a> RXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&self) -> CHSIZE_R { + CHSIZE_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 6 - Data Preload Enable"] + #[inline(always)] + pub fn ploaden(&self) -> PLOADEN_R { + PLOADEN_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 9 - Slave Select Low Detect Enable"] + #[inline(always)] + pub fn ssde(&self) -> SSDE_R { + SSDE_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 13 - Master Slave Select Enable"] + #[inline(always)] + pub fn mssen(&self) -> MSSEN_R { + MSSEN_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bits 14:15 - Address Mode"] + #[inline(always)] + pub fn amode(&self) -> AMODE_R { + AMODE_R::new(((self.bits >> 14) & 0x03) as u8) + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&self) -> RXEN_R { + RXEN_R::new(((self.bits >> 17) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&mut self) -> CHSIZE_W { + CHSIZE_W { w: self } + } + #[doc = "Bit 6 - Data Preload Enable"] + #[inline(always)] + pub fn ploaden(&mut self) -> PLOADEN_W { + PLOADEN_W { w: self } + } + #[doc = "Bit 9 - Slave Select Low Detect Enable"] + #[inline(always)] + pub fn ssde(&mut self) -> SSDE_W { + SSDE_W { w: self } + } + #[doc = "Bit 13 - Master Slave Select Enable"] + #[inline(always)] + pub fn mssen(&mut self) -> MSSEN_W { + MSSEN_W { w: self } + } + #[doc = "Bits 14:15 - Address Mode"] + #[inline(always)] + pub fn amode(&mut self) -> AMODE_W { + AMODE_W { w: self } + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&mut self) -> RXEN_W { + RXEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/sercom0/spis/data.rs b/pac/atsamc20j/src/sercom0/spis/data.rs new file mode 100644 index 000000000000..4edf8089b29f --- /dev/null +++ b/pac/atsamc20j/src/sercom0/spis/data.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data Value"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data Value"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01ff) | (value as u32 & 0x01ff); + self.w + } +} +impl R { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new((self.bits & 0x01ff) as u16) + } +} +impl W { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/sercom0/spis/dbgctrl.rs b/pac/atsamc20j/src/sercom0/spis/dbgctrl.rs new file mode 100644 index 000000000000..ec36bbd26057 --- /dev/null +++ b/pac/atsamc20j/src/sercom0/spis/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGSTOP` reader - Debug Mode"] +pub struct DBGSTOP_R(crate::FieldReader); +impl DBGSTOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGSTOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGSTOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGSTOP` writer - Debug Mode"] +pub struct DBGSTOP_W<'a> { + w: &'a mut W, +} +impl<'a> DBGSTOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&self) -> DBGSTOP_R { + DBGSTOP_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&mut self) -> DBGSTOP_W { + DBGSTOP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/sercom0/spis/intenclr.rs b/pac/atsamc20j/src/sercom0/spis/intenclr.rs new file mode 100644 index 000000000000..e4c9ee0d506d --- /dev/null +++ b/pac/atsamc20j/src/sercom0/spis/intenclr.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Disable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Disable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Disable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Disable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Disable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Disable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SSL` reader - Slave Select Low Interrupt Disable"] +pub struct SSL_R(crate::FieldReader); +impl SSL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SSL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSL` writer - Slave Select Low Interrupt Disable"] +pub struct SSL_W<'a> { + w: &'a mut W, +} +impl<'a> SSL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Disable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Disable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Slave Select Low Interrupt Disable"] + #[inline(always)] + pub fn ssl(&self) -> SSL_R { + SSL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Slave Select Low Interrupt Disable"] + #[inline(always)] + pub fn ssl(&mut self) -> SSL_W { + SSL_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/sercom0/spis/intenset.rs b/pac/atsamc20j/src/sercom0/spis/intenset.rs new file mode 100644 index 000000000000..99582a624ebc --- /dev/null +++ b/pac/atsamc20j/src/sercom0/spis/intenset.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Enable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Enable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Enable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Enable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Enable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Enable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SSL` reader - Slave Select Low Interrupt Enable"] +pub struct SSL_R(crate::FieldReader); +impl SSL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SSL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSL` writer - Slave Select Low Interrupt Enable"] +pub struct SSL_W<'a> { + w: &'a mut W, +} +impl<'a> SSL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Slave Select Low Interrupt Enable"] + #[inline(always)] + pub fn ssl(&self) -> SSL_R { + SSL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Slave Select Low Interrupt Enable"] + #[inline(always)] + pub fn ssl(&mut self) -> SSL_W { + SSL_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/sercom0/spis/intflag.rs b/pac/atsamc20j/src/sercom0/spis/intflag.rs new file mode 100644 index 000000000000..589e73c2329f --- /dev/null +++ b/pac/atsamc20j/src/sercom0/spis/intflag.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SSL` reader - Slave Select Low Interrupt Flag"] +pub struct SSL_R(crate::FieldReader); +impl SSL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SSL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSL` writer - Slave Select Low Interrupt Flag"] +pub struct SSL_W<'a> { + w: &'a mut W, +} +impl<'a> SSL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Slave Select Low Interrupt Flag"] + #[inline(always)] + pub fn ssl(&self) -> SSL_R { + SSL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Slave Select Low Interrupt Flag"] + #[inline(always)] + pub fn ssl(&mut self) -> SSL_W { + SSL_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/sercom0/spis/status.rs b/pac/atsamc20j/src/sercom0/spis/status.rs new file mode 100644 index 000000000000..55c39c1a709f --- /dev/null +++ b/pac/atsamc20j/src/sercom0/spis/status.rs @@ -0,0 +1,113 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BUFOVF` reader - Buffer Overflow"] +pub struct BUFOVF_R(crate::FieldReader); +impl BUFOVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUFOVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUFOVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUFOVF` writer - Buffer Overflow"] +pub struct BUFOVF_W<'a> { + w: &'a mut W, +} +impl<'a> BUFOVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&self) -> BUFOVF_R { + BUFOVF_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&mut self) -> BUFOVF_W { + BUFOVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/sercom0/spis/syncbusy.rs b/pac/atsamc20j/src/sercom0/spis/syncbusy.rs new file mode 100644 index 000000000000..ac2f2e2c27ec --- /dev/null +++ b/pac/atsamc20j/src/sercom0/spis/syncbusy.rs @@ -0,0 +1,93 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - SERCOM Enable Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLB` reader - CTRLB Synchronization Busy"] +pub struct CTRLB_R(crate::FieldReader); +impl CTRLB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM Enable Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - CTRLB Synchronization Busy"] + #[inline(always)] + pub fn ctrlb(&self) -> CTRLB_R { + CTRLB_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +#[doc = "SPIS Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/sercom0/usart_ext.rs b/pac/atsamc20j/src/sercom0/usart_ext.rs new file mode 100644 index 000000000000..8c08b9efc1d5 --- /dev/null +++ b/pac/atsamc20j/src/sercom0/usart_ext.rs @@ -0,0 +1,60 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "USART_EXT Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "USART_EXT Control B"] +pub mod ctrlb; +#[doc = "CTRLC register accessor: an alias for `Reg`"] +pub type CTRLC = crate::Reg; +#[doc = "USART_EXT Control C"] +pub mod ctrlc; +#[doc = "BAUD register accessor: an alias for `Reg`"] +pub type BAUD = crate::Reg; +#[doc = "USART_EXT Baud Rate"] +pub mod baud; +#[doc = "BAUD_FRAC_MODE register accessor: an alias for `Reg`"] +pub type BAUD_FRAC_MODE = crate::Reg; +#[doc = "USART_EXT Baud Rate"] +pub mod baud_frac_mode; +#[doc = "BAUD_FRACFP_MODE register accessor: an alias for `Reg`"] +pub type BAUD_FRACFP_MODE = crate::Reg; +#[doc = "USART_EXT Baud Rate"] +pub mod baud_fracfp_mode; +#[doc = "BAUD_USARTFP_MODE register accessor: an alias for `Reg`"] +pub type BAUD_USARTFP_MODE = crate::Reg; +#[doc = "USART_EXT Baud Rate"] +pub mod baud_usartfp_mode; +#[doc = "RXPL register accessor: an alias for `Reg`"] +pub type RXPL = crate::Reg; +#[doc = "USART_EXT Receive Pulse Length"] +pub mod rxpl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "USART_EXT Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "USART_EXT Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "USART_EXT Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "USART_EXT Status"] +pub mod status; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "USART_EXT Synchronization Busy"] +pub mod syncbusy; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "USART_EXT Data"] +pub mod data; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "USART_EXT Debug Control"] +pub mod dbgctrl; diff --git a/pac/atsamc20j/src/sercom0/usart_ext/baud.rs b/pac/atsamc20j/src/sercom0/usart_ext/baud.rs new file mode 100644 index 000000000000..9558a8e1a52d --- /dev/null +++ b/pac/atsamc20j/src/sercom0/usart_ext/baud.rs @@ -0,0 +1,103 @@ +#[doc = "Register `BAUD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud](index.html) module"] +pub struct BAUD_SPEC; +impl crate::RegisterSpec for BAUD_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud::R](R) reader structure"] +impl crate::Readable for BAUD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud::W](W) writer structure"] +impl crate::Writable for BAUD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD to value 0"] +impl crate::Resettable for BAUD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/sercom0/usart_ext/baud_frac_mode.rs b/pac/atsamc20j/src/sercom0/usart_ext/baud_frac_mode.rs new file mode 100644 index 000000000000..d7cdd4570e26 --- /dev/null +++ b/pac/atsamc20j/src/sercom0/usart_ext/baud_frac_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `BAUD_FRAC_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD_FRAC_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1fff) | (value as u16 & 0x1fff); + self.w + } +} +#[doc = "Field `FP` reader - Fractional Part"] +pub struct FP_R(crate::FieldReader); +impl FP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FP` writer - Fractional Part"] +pub struct FP_W<'a> { + w: &'a mut W, +} +impl<'a> FP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 13)) | ((value as u16 & 0x07) << 13); + self.w + } +} +impl R { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new((self.bits & 0x1fff) as u16) + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&self) -> FP_R { + FP_R::new(((self.bits >> 13) & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&mut self) -> FP_W { + FP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud_frac_mode](index.html) module"] +pub struct BAUD_FRAC_MODE_SPEC; +impl crate::RegisterSpec for BAUD_FRAC_MODE_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud_frac_mode::R](R) reader structure"] +impl crate::Readable for BAUD_FRAC_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud_frac_mode::W](W) writer structure"] +impl crate::Writable for BAUD_FRAC_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD_FRAC_MODE to value 0"] +impl crate::Resettable for BAUD_FRAC_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/sercom0/usart_ext/baud_fracfp_mode.rs b/pac/atsamc20j/src/sercom0/usart_ext/baud_fracfp_mode.rs new file mode 100644 index 000000000000..c1dc50807677 --- /dev/null +++ b/pac/atsamc20j/src/sercom0/usart_ext/baud_fracfp_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `BAUD_FRACFP_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD_FRACFP_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1fff) | (value as u16 & 0x1fff); + self.w + } +} +#[doc = "Field `FP` reader - Fractional Part"] +pub struct FP_R(crate::FieldReader); +impl FP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FP` writer - Fractional Part"] +pub struct FP_W<'a> { + w: &'a mut W, +} +impl<'a> FP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 13)) | ((value as u16 & 0x07) << 13); + self.w + } +} +impl R { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new((self.bits & 0x1fff) as u16) + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&self) -> FP_R { + FP_R::new(((self.bits >> 13) & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&mut self) -> FP_W { + FP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud_fracfp_mode](index.html) module"] +pub struct BAUD_FRACFP_MODE_SPEC; +impl crate::RegisterSpec for BAUD_FRACFP_MODE_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud_fracfp_mode::R](R) reader structure"] +impl crate::Readable for BAUD_FRACFP_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud_fracfp_mode::W](W) writer structure"] +impl crate::Writable for BAUD_FRACFP_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD_FRACFP_MODE to value 0"] +impl crate::Resettable for BAUD_FRACFP_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/sercom0/usart_ext/baud_usartfp_mode.rs b/pac/atsamc20j/src/sercom0/usart_ext/baud_usartfp_mode.rs new file mode 100644 index 000000000000..8d4db16e0245 --- /dev/null +++ b/pac/atsamc20j/src/sercom0/usart_ext/baud_usartfp_mode.rs @@ -0,0 +1,103 @@ +#[doc = "Register `BAUD_USARTFP_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD_USARTFP_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud_usartfp_mode](index.html) module"] +pub struct BAUD_USARTFP_MODE_SPEC; +impl crate::RegisterSpec for BAUD_USARTFP_MODE_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud_usartfp_mode::R](R) reader structure"] +impl crate::Readable for BAUD_USARTFP_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud_usartfp_mode::W](W) writer structure"] +impl crate::Writable for BAUD_USARTFP_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD_USARTFP_MODE to value 0"] +impl crate::Resettable for BAUD_USARTFP_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/sercom0/usart_ext/ctrla.rs b/pac/atsamc20j/src/sercom0/usart_ext/ctrla.rs new file mode 100644 index 000000000000..535875ac8b25 --- /dev/null +++ b/pac/atsamc20j/src/sercom0/usart_ext/ctrla.rs @@ -0,0 +1,1171 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: USART with external clock"] + USART_EXT_CLK = 0, + #[doc = "1: USART with internal clock"] + USART_INT_CLK = 1, + #[doc = "2: SPI in slave operation"] + SPI_SLAVE = 2, + #[doc = "3: SPI in master operation"] + SPI_MASTER = 3, + #[doc = "4: I2C slave operation"] + I2C_SLAVE = 4, + #[doc = "5: I2C master operation"] + I2C_MASTER = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::USART_EXT_CLK), + 1 => Some(MODE_A::USART_INT_CLK), + 2 => Some(MODE_A::SPI_SLAVE), + 3 => Some(MODE_A::SPI_MASTER), + 4 => Some(MODE_A::I2C_SLAVE), + 5 => Some(MODE_A::I2C_MASTER), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_EXT_CLK`"] + #[inline(always)] + pub fn is_usart_ext_clk(&self) -> bool { + **self == MODE_A::USART_EXT_CLK + } + #[doc = "Checks if the value of the field is `USART_INT_CLK`"] + #[inline(always)] + pub fn is_usart_int_clk(&self) -> bool { + **self == MODE_A::USART_INT_CLK + } + #[doc = "Checks if the value of the field is `SPI_SLAVE`"] + #[inline(always)] + pub fn is_spi_slave(&self) -> bool { + **self == MODE_A::SPI_SLAVE + } + #[doc = "Checks if the value of the field is `SPI_MASTER`"] + #[inline(always)] + pub fn is_spi_master(&self) -> bool { + **self == MODE_A::SPI_MASTER + } + #[doc = "Checks if the value of the field is `I2C_SLAVE`"] + #[inline(always)] + pub fn is_i2c_slave(&self) -> bool { + **self == MODE_A::I2C_SLAVE + } + #[doc = "Checks if the value of the field is `I2C_MASTER`"] + #[inline(always)] + pub fn is_i2c_master(&self) -> bool { + **self == MODE_A::I2C_MASTER + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART with external clock"] + #[inline(always)] + pub fn usart_ext_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_EXT_CLK) + } + #[doc = "USART with internal clock"] + #[inline(always)] + pub fn usart_int_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_INT_CLK) + } + #[doc = "SPI in slave operation"] + #[inline(always)] + pub fn spi_slave(self) -> &'a mut W { + self.variant(MODE_A::SPI_SLAVE) + } + #[doc = "SPI in master operation"] + #[inline(always)] + pub fn spi_master(self) -> &'a mut W { + self.variant(MODE_A::SPI_MASTER) + } + #[doc = "I2C slave operation"] + #[inline(always)] + pub fn i2c_slave(self) -> &'a mut W { + self.variant(MODE_A::I2C_SLAVE) + } + #[doc = "I2C master operation"] + #[inline(always)] + pub fn i2c_master(self) -> &'a mut W { + self.variant(MODE_A::I2C_MASTER) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 2)) | ((value as u32 & 0x07) << 2); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `IBON` reader - Immediate Buffer Overflow Notification"] +pub struct IBON_R(crate::FieldReader); +impl IBON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IBON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IBON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IBON` writer - Immediate Buffer Overflow Notification"] +pub struct IBON_W<'a> { + w: &'a mut W, +} +impl<'a> IBON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Sample\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SAMPR_A { + #[doc = "0: 16x over-sampling using arithmetic baudrate generation"] + _16X_ARITHMETIC = 0, + #[doc = "1: 16x over-sampling using fractional baudrate generation"] + _16X_FRACTIONAL = 1, + #[doc = "2: 8x over-sampling using arithmetic baudrate generation"] + _8X_ARITHMETIC = 2, + #[doc = "3: 8x over-sampling using fractional baudrate generation"] + _8X_FRACTIONAL = 3, + #[doc = "4: 3x over-sampling using arithmetic baudrate generation"] + _3X_ARITHMETIC = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SAMPR_A) -> Self { + variant as _ + } +} +#[doc = "Field `SAMPR` reader - Sample"] +pub struct SAMPR_R(crate::FieldReader); +impl SAMPR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SAMPR_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SAMPR_A::_16X_ARITHMETIC), + 1 => Some(SAMPR_A::_16X_FRACTIONAL), + 2 => Some(SAMPR_A::_8X_ARITHMETIC), + 3 => Some(SAMPR_A::_8X_FRACTIONAL), + 4 => Some(SAMPR_A::_3X_ARITHMETIC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_16X_ARITHMETIC`"] + #[inline(always)] + pub fn is_16x_arithmetic(&self) -> bool { + **self == SAMPR_A::_16X_ARITHMETIC + } + #[doc = "Checks if the value of the field is `_16X_FRACTIONAL`"] + #[inline(always)] + pub fn is_16x_fractional(&self) -> bool { + **self == SAMPR_A::_16X_FRACTIONAL + } + #[doc = "Checks if the value of the field is `_8X_ARITHMETIC`"] + #[inline(always)] + pub fn is_8x_arithmetic(&self) -> bool { + **self == SAMPR_A::_8X_ARITHMETIC + } + #[doc = "Checks if the value of the field is `_8X_FRACTIONAL`"] + #[inline(always)] + pub fn is_8x_fractional(&self) -> bool { + **self == SAMPR_A::_8X_FRACTIONAL + } + #[doc = "Checks if the value of the field is `_3X_ARITHMETIC`"] + #[inline(always)] + pub fn is_3x_arithmetic(&self) -> bool { + **self == SAMPR_A::_3X_ARITHMETIC + } +} +impl core::ops::Deref for SAMPR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SAMPR` writer - Sample"] +pub struct SAMPR_W<'a> { + w: &'a mut W, +} +impl<'a> SAMPR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SAMPR_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "16x over-sampling using arithmetic baudrate generation"] + #[inline(always)] + pub fn _16x_arithmetic(self) -> &'a mut W { + self.variant(SAMPR_A::_16X_ARITHMETIC) + } + #[doc = "16x over-sampling using fractional baudrate generation"] + #[inline(always)] + pub fn _16x_fractional(self) -> &'a mut W { + self.variant(SAMPR_A::_16X_FRACTIONAL) + } + #[doc = "8x over-sampling using arithmetic baudrate generation"] + #[inline(always)] + pub fn _8x_arithmetic(self) -> &'a mut W { + self.variant(SAMPR_A::_8X_ARITHMETIC) + } + #[doc = "8x over-sampling using fractional baudrate generation"] + #[inline(always)] + pub fn _8x_fractional(self) -> &'a mut W { + self.variant(SAMPR_A::_8X_FRACTIONAL) + } + #[doc = "3x over-sampling using arithmetic baudrate generation"] + #[inline(always)] + pub fn _3x_arithmetic(self) -> &'a mut W { + self.variant(SAMPR_A::_3X_ARITHMETIC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 13)) | ((value as u32 & 0x07) << 13); + self.w + } +} +#[doc = "Transmit Data Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum TXPO_A { + #[doc = "0: SERCOM PAD\\[0\\] +is used for data transmission"] + PAD0 = 0, + #[doc = "1: SERCOM PAD\\[2\\] +is used for data transmission"] + PAD2 = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: TXPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `TXPO` reader - Transmit Data Pinout"] +pub struct TXPO_R(crate::FieldReader); +impl TXPO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TXPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(TXPO_A::PAD0), + 1 => Some(TXPO_A::PAD2), + _ => None, + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == TXPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == TXPO_A::PAD2 + } +} +impl core::ops::Deref for TXPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXPO` writer - Transmit Data Pinout"] +pub struct TXPO_W<'a> { + w: &'a mut W, +} +impl<'a> TXPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TXPO_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "SERCOM PAD\\[0\\] +is used for data transmission"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(TXPO_A::PAD0) + } + #[doc = "SERCOM PAD\\[2\\] +is used for data transmission"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(TXPO_A::PAD2) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Receive Data Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum RXPO_A { + #[doc = "0: SERCOM PAD\\[0\\] +is used for data reception"] + PAD0 = 0, + #[doc = "1: SERCOM PAD\\[1\\] +is used for data reception"] + PAD1 = 1, + #[doc = "2: SERCOM PAD\\[2\\] +is used for data reception"] + PAD2 = 2, + #[doc = "3: SERCOM PAD\\[3\\] +is used for data reception"] + PAD3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RXPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `RXPO` reader - Receive Data Pinout"] +pub struct RXPO_R(crate::FieldReader); +impl RXPO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RXPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RXPO_A { + match self.bits { + 0 => RXPO_A::PAD0, + 1 => RXPO_A::PAD1, + 2 => RXPO_A::PAD2, + 3 => RXPO_A::PAD3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == RXPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD1`"] + #[inline(always)] + pub fn is_pad1(&self) -> bool { + **self == RXPO_A::PAD1 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == RXPO_A::PAD2 + } + #[doc = "Checks if the value of the field is `PAD3`"] + #[inline(always)] + pub fn is_pad3(&self) -> bool { + **self == RXPO_A::PAD3 + } +} +impl core::ops::Deref for RXPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXPO` writer - Receive Data Pinout"] +pub struct RXPO_W<'a> { + w: &'a mut W, +} +impl<'a> RXPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RXPO_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "SERCOM PAD\\[0\\] +is used for data reception"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(RXPO_A::PAD0) + } + #[doc = "SERCOM PAD\\[1\\] +is used for data reception"] + #[inline(always)] + pub fn pad1(self) -> &'a mut W { + self.variant(RXPO_A::PAD1) + } + #[doc = "SERCOM PAD\\[2\\] +is used for data reception"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(RXPO_A::PAD2) + } + #[doc = "SERCOM PAD\\[3\\] +is used for data reception"] + #[inline(always)] + pub fn pad3(self) -> &'a mut W { + self.variant(RXPO_A::PAD3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 20)) | ((value as u32 & 0x03) << 20); + self.w + } +} +#[doc = "Field `SAMPA` reader - Sample Adjustment"] +pub struct SAMPA_R(crate::FieldReader); +impl SAMPA_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SAMPA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SAMPA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SAMPA` writer - Sample Adjustment"] +pub struct SAMPA_W<'a> { + w: &'a mut W, +} +impl<'a> SAMPA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 22)) | ((value as u32 & 0x03) << 22); + self.w + } +} +#[doc = "Frame Format\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FORM_A { + #[doc = "0: USART frame"] + USART_FRAME_NO_PARITY = 0, + #[doc = "1: USART frame with parity"] + USART_FRAME_WITH_PARITY = 1, + #[doc = "2: LIN Master - Break and sync generation"] + USART_FRAME_LIN_MASTER_MODE = 2, + #[doc = "4: Auto-baud - break detection and auto-baud"] + USART_FRAME_AUTO_BAUD_NO_PARITY = 4, + #[doc = "5: Auto-baud - break detection and auto-baud with parity"] + USART_FRAME_AUTO_BAUD_WITH_PARITY = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FORM_A) -> Self { + variant as _ + } +} +#[doc = "Field `FORM` reader - Frame Format"] +pub struct FORM_R(crate::FieldReader); +impl FORM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FORM_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(FORM_A::USART_FRAME_NO_PARITY), + 1 => Some(FORM_A::USART_FRAME_WITH_PARITY), + 2 => Some(FORM_A::USART_FRAME_LIN_MASTER_MODE), + 4 => Some(FORM_A::USART_FRAME_AUTO_BAUD_NO_PARITY), + 5 => Some(FORM_A::USART_FRAME_AUTO_BAUD_WITH_PARITY), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_FRAME_NO_PARITY`"] + #[inline(always)] + pub fn is_usart_frame_no_parity(&self) -> bool { + **self == FORM_A::USART_FRAME_NO_PARITY + } + #[doc = "Checks if the value of the field is `USART_FRAME_WITH_PARITY`"] + #[inline(always)] + pub fn is_usart_frame_with_parity(&self) -> bool { + **self == FORM_A::USART_FRAME_WITH_PARITY + } + #[doc = "Checks if the value of the field is `USART_FRAME_LIN_MASTER_MODE`"] + #[inline(always)] + pub fn is_usart_frame_lin_master_mode(&self) -> bool { + **self == FORM_A::USART_FRAME_LIN_MASTER_MODE + } + #[doc = "Checks if the value of the field is `USART_FRAME_AUTO_BAUD_NO_PARITY`"] + #[inline(always)] + pub fn is_usart_frame_auto_baud_no_parity(&self) -> bool { + **self == FORM_A::USART_FRAME_AUTO_BAUD_NO_PARITY + } + #[doc = "Checks if the value of the field is `USART_FRAME_AUTO_BAUD_WITH_PARITY`"] + #[inline(always)] + pub fn is_usart_frame_auto_baud_with_parity(&self) -> bool { + **self == FORM_A::USART_FRAME_AUTO_BAUD_WITH_PARITY + } +} +impl core::ops::Deref for FORM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FORM` writer - Frame Format"] +pub struct FORM_W<'a> { + w: &'a mut W, +} +impl<'a> FORM_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FORM_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART frame"] + #[inline(always)] + pub fn usart_frame_no_parity(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_NO_PARITY) + } + #[doc = "USART frame with parity"] + #[inline(always)] + pub fn usart_frame_with_parity(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_WITH_PARITY) + } + #[doc = "LIN Master - Break and sync generation"] + #[inline(always)] + pub fn usart_frame_lin_master_mode(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_LIN_MASTER_MODE) + } + #[doc = "Auto-baud - break detection and auto-baud"] + #[inline(always)] + pub fn usart_frame_auto_baud_no_parity(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_AUTO_BAUD_NO_PARITY) + } + #[doc = "Auto-baud - break detection and auto-baud with parity"] + #[inline(always)] + pub fn usart_frame_auto_baud_with_parity(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_AUTO_BAUD_WITH_PARITY) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Communication Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CMODE_A { + #[doc = "0: Asynchronous Communication"] + ASYNC = 0, + #[doc = "1: Synchronous Communication"] + SYNC = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CMODE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CMODE` reader - Communication Mode"] +pub struct CMODE_R(crate::FieldReader); +impl CMODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CMODE_A { + match self.bits { + false => CMODE_A::ASYNC, + true => CMODE_A::SYNC, + } + } + #[doc = "Checks if the value of the field is `ASYNC`"] + #[inline(always)] + pub fn is_async(&self) -> bool { + **self == CMODE_A::ASYNC + } + #[doc = "Checks if the value of the field is `SYNC`"] + #[inline(always)] + pub fn is_sync(&self) -> bool { + **self == CMODE_A::SYNC + } +} +impl core::ops::Deref for CMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMODE` writer - Communication Mode"] +pub struct CMODE_W<'a> { + w: &'a mut W, +} +impl<'a> CMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMODE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Asynchronous Communication"] + #[inline(always)] + pub fn async_(self) -> &'a mut W { + self.variant(CMODE_A::ASYNC) + } + #[doc = "Synchronous Communication"] + #[inline(always)] + pub fn sync(self) -> &'a mut W { + self.variant(CMODE_A::SYNC) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Clock Polarity\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CPOL_A { + #[doc = "0: TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge"] + IDLE_LOW = 0, + #[doc = "1: TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge"] + IDLE_HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CPOL_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CPOL` reader - Clock Polarity"] +pub struct CPOL_R(crate::FieldReader); +impl CPOL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPOL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CPOL_A { + match self.bits { + false => CPOL_A::IDLE_LOW, + true => CPOL_A::IDLE_HIGH, + } + } + #[doc = "Checks if the value of the field is `IDLE_LOW`"] + #[inline(always)] + pub fn is_idle_low(&self) -> bool { + **self == CPOL_A::IDLE_LOW + } + #[doc = "Checks if the value of the field is `IDLE_HIGH`"] + #[inline(always)] + pub fn is_idle_high(&self) -> bool { + **self == CPOL_A::IDLE_HIGH + } +} +impl core::ops::Deref for CPOL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPOL` writer - Clock Polarity"] +pub struct CPOL_W<'a> { + w: &'a mut W, +} +impl<'a> CPOL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CPOL_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge"] + #[inline(always)] + pub fn idle_low(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_LOW) + } + #[doc = "TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge"] + #[inline(always)] + pub fn idle_high(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_HIGH) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29); + self.w + } +} +#[doc = "Data Order\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum DORD_A { + #[doc = "0: MSB is transmitted first"] + MSB = 0, + #[doc = "1: LSB is transmitted first"] + LSB = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DORD_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DORD` reader - Data Order"] +pub struct DORD_R(crate::FieldReader); +impl DORD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DORD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DORD_A { + match self.bits { + false => DORD_A::MSB, + true => DORD_A::LSB, + } + } + #[doc = "Checks if the value of the field is `MSB`"] + #[inline(always)] + pub fn is_msb(&self) -> bool { + **self == DORD_A::MSB + } + #[doc = "Checks if the value of the field is `LSB`"] + #[inline(always)] + pub fn is_lsb(&self) -> bool { + **self == DORD_A::LSB + } +} +impl core::ops::Deref for DORD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DORD` writer - Data Order"] +pub struct DORD_W<'a> { + w: &'a mut W, +} +impl<'a> DORD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DORD_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "MSB is transmitted first"] + #[inline(always)] + pub fn msb(self) -> &'a mut W { + self.variant(DORD_A::MSB) + } + #[doc = "LSB is transmitted first"] + #[inline(always)] + pub fn lsb(self) -> &'a mut W { + self.variant(DORD_A::LSB) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x07) as u8) + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&self) -> IBON_R { + IBON_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bits 13:15 - Sample"] + #[inline(always)] + pub fn sampr(&self) -> SAMPR_R { + SAMPR_R::new(((self.bits >> 13) & 0x07) as u8) + } + #[doc = "Bits 16:17 - Transmit Data Pinout"] + #[inline(always)] + pub fn txpo(&self) -> TXPO_R { + TXPO_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bits 20:21 - Receive Data Pinout"] + #[inline(always)] + pub fn rxpo(&self) -> RXPO_R { + RXPO_R::new(((self.bits >> 20) & 0x03) as u8) + } + #[doc = "Bits 22:23 - Sample Adjustment"] + #[inline(always)] + pub fn sampa(&self) -> SAMPA_R { + SAMPA_R::new(((self.bits >> 22) & 0x03) as u8) + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&self) -> FORM_R { + FORM_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 28 - Communication Mode"] + #[inline(always)] + pub fn cmode(&self) -> CMODE_R { + CMODE_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&self) -> CPOL_R { + CPOL_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&self) -> DORD_R { + DORD_R::new(((self.bits >> 30) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&mut self) -> IBON_W { + IBON_W { w: self } + } + #[doc = "Bits 13:15 - Sample"] + #[inline(always)] + pub fn sampr(&mut self) -> SAMPR_W { + SAMPR_W { w: self } + } + #[doc = "Bits 16:17 - Transmit Data Pinout"] + #[inline(always)] + pub fn txpo(&mut self) -> TXPO_W { + TXPO_W { w: self } + } + #[doc = "Bits 20:21 - Receive Data Pinout"] + #[inline(always)] + pub fn rxpo(&mut self) -> RXPO_W { + RXPO_W { w: self } + } + #[doc = "Bits 22:23 - Sample Adjustment"] + #[inline(always)] + pub fn sampa(&mut self) -> SAMPA_W { + SAMPA_W { w: self } + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&mut self) -> FORM_W { + FORM_W { w: self } + } + #[doc = "Bit 28 - Communication Mode"] + #[inline(always)] + pub fn cmode(&mut self) -> CMODE_W { + CMODE_W { w: self } + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&mut self) -> CPOL_W { + CPOL_W { w: self } + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&mut self) -> DORD_W { + DORD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/sercom0/usart_ext/ctrlb.rs b/pac/atsamc20j/src/sercom0/usart_ext/ctrlb.rs new file mode 100644 index 000000000000..37567555e842 --- /dev/null +++ b/pac/atsamc20j/src/sercom0/usart_ext/ctrlb.rs @@ -0,0 +1,651 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Character Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CHSIZE_A { + #[doc = "0: 8 Bits"] + _8_BIT = 0, + #[doc = "1: 9 Bits"] + _9_BIT = 1, + #[doc = "5: 5 Bits"] + _5_BIT = 5, + #[doc = "6: 6 Bits"] + _6_BIT = 6, + #[doc = "7: 7 Bits"] + _7_BIT = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CHSIZE_A) -> Self { + variant as _ + } +} +#[doc = "Field `CHSIZE` reader - Character Size"] +pub struct CHSIZE_R(crate::FieldReader); +impl CHSIZE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CHSIZE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CHSIZE_A::_8_BIT), + 1 => Some(CHSIZE_A::_9_BIT), + 5 => Some(CHSIZE_A::_5_BIT), + 6 => Some(CHSIZE_A::_6_BIT), + 7 => Some(CHSIZE_A::_7_BIT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_8_BIT`"] + #[inline(always)] + pub fn is_8_bit(&self) -> bool { + **self == CHSIZE_A::_8_BIT + } + #[doc = "Checks if the value of the field is `_9_BIT`"] + #[inline(always)] + pub fn is_9_bit(&self) -> bool { + **self == CHSIZE_A::_9_BIT + } + #[doc = "Checks if the value of the field is `_5_BIT`"] + #[inline(always)] + pub fn is_5_bit(&self) -> bool { + **self == CHSIZE_A::_5_BIT + } + #[doc = "Checks if the value of the field is `_6_BIT`"] + #[inline(always)] + pub fn is_6_bit(&self) -> bool { + **self == CHSIZE_A::_6_BIT + } + #[doc = "Checks if the value of the field is `_7_BIT`"] + #[inline(always)] + pub fn is_7_bit(&self) -> bool { + **self == CHSIZE_A::_7_BIT + } +} +impl core::ops::Deref for CHSIZE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHSIZE` writer - Character Size"] +pub struct CHSIZE_W<'a> { + w: &'a mut W, +} +impl<'a> CHSIZE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CHSIZE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8 Bits"] + #[inline(always)] + pub fn _8_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_8_BIT) + } + #[doc = "9 Bits"] + #[inline(always)] + pub fn _9_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_9_BIT) + } + #[doc = "5 Bits"] + #[inline(always)] + pub fn _5_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_5_BIT) + } + #[doc = "6 Bits"] + #[inline(always)] + pub fn _6_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_6_BIT) + } + #[doc = "7 Bits"] + #[inline(always)] + pub fn _7_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_7_BIT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Stop Bit Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SBMODE_A { + #[doc = "0: One Stop Bit"] + _1_BIT = 0, + #[doc = "1: Two Stop Bits"] + _2_BIT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SBMODE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SBMODE` reader - Stop Bit Mode"] +pub struct SBMODE_R(crate::FieldReader); +impl SBMODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SBMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SBMODE_A { + match self.bits { + false => SBMODE_A::_1_BIT, + true => SBMODE_A::_2_BIT, + } + } + #[doc = "Checks if the value of the field is `_1_BIT`"] + #[inline(always)] + pub fn is_1_bit(&self) -> bool { + **self == SBMODE_A::_1_BIT + } + #[doc = "Checks if the value of the field is `_2_BIT`"] + #[inline(always)] + pub fn is_2_bit(&self) -> bool { + **self == SBMODE_A::_2_BIT + } +} +impl core::ops::Deref for SBMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SBMODE` writer - Stop Bit Mode"] +pub struct SBMODE_W<'a> { + w: &'a mut W, +} +impl<'a> SBMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SBMODE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "One Stop Bit"] + #[inline(always)] + pub fn _1_bit(self) -> &'a mut W { + self.variant(SBMODE_A::_1_BIT) + } + #[doc = "Two Stop Bits"] + #[inline(always)] + pub fn _2_bit(self) -> &'a mut W { + self.variant(SBMODE_A::_2_BIT) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `COLDEN` reader - Collision Detection Enable"] +pub struct COLDEN_R(crate::FieldReader); +impl COLDEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COLDEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COLDEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COLDEN` writer - Collision Detection Enable"] +pub struct COLDEN_W<'a> { + w: &'a mut W, +} +impl<'a> COLDEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `SFDE` reader - Start of Frame Detection Enable"] +pub struct SFDE_R(crate::FieldReader); +impl SFDE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SFDE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SFDE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SFDE` writer - Start of Frame Detection Enable"] +pub struct SFDE_W<'a> { + w: &'a mut W, +} +impl<'a> SFDE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `ENC` reader - Encoding Format"] +pub struct ENC_R(crate::FieldReader); +impl ENC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENC` writer - Encoding Format"] +pub struct ENC_W<'a> { + w: &'a mut W, +} +impl<'a> ENC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Parity Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PMODE_A { + #[doc = "0: Even Parity"] + EVEN = 0, + #[doc = "1: Odd Parity"] + ODD = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PMODE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PMODE` reader - Parity Mode"] +pub struct PMODE_R(crate::FieldReader); +impl PMODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PMODE_A { + match self.bits { + false => PMODE_A::EVEN, + true => PMODE_A::ODD, + } + } + #[doc = "Checks if the value of the field is `EVEN`"] + #[inline(always)] + pub fn is_even(&self) -> bool { + **self == PMODE_A::EVEN + } + #[doc = "Checks if the value of the field is `ODD`"] + #[inline(always)] + pub fn is_odd(&self) -> bool { + **self == PMODE_A::ODD + } +} +impl core::ops::Deref for PMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PMODE` writer - Parity Mode"] +pub struct PMODE_W<'a> { + w: &'a mut W, +} +impl<'a> PMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PMODE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Even Parity"] + #[inline(always)] + pub fn even(self) -> &'a mut W { + self.variant(PMODE_A::EVEN) + } + #[doc = "Odd Parity"] + #[inline(always)] + pub fn odd(self) -> &'a mut W { + self.variant(PMODE_A::ODD) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `TXEN` reader - Transmitter Enable"] +pub struct TXEN_R(crate::FieldReader); +impl TXEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXEN` writer - Transmitter Enable"] +pub struct TXEN_W<'a> { + w: &'a mut W, +} +impl<'a> TXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `RXEN` reader - Receiver Enable"] +pub struct RXEN_R(crate::FieldReader); +impl RXEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXEN` writer - Receiver Enable"] +pub struct RXEN_W<'a> { + w: &'a mut W, +} +impl<'a> RXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `LINCMD` reader - LIN Command"] +pub struct LINCMD_R(crate::FieldReader); +impl LINCMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LINCMD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LINCMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LINCMD` writer - LIN Command"] +pub struct LINCMD_W<'a> { + w: &'a mut W, +} +impl<'a> LINCMD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 24)) | ((value as u32 & 0x03) << 24); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&self) -> CHSIZE_R { + CHSIZE_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 6 - Stop Bit Mode"] + #[inline(always)] + pub fn sbmode(&self) -> SBMODE_R { + SBMODE_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 8 - Collision Detection Enable"] + #[inline(always)] + pub fn colden(&self) -> COLDEN_R { + COLDEN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Start of Frame Detection Enable"] + #[inline(always)] + pub fn sfde(&self) -> SFDE_R { + SFDE_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Encoding Format"] + #[inline(always)] + pub fn enc(&self) -> ENC_R { + ENC_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 13 - Parity Mode"] + #[inline(always)] + pub fn pmode(&self) -> PMODE_R { + PMODE_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 16 - Transmitter Enable"] + #[inline(always)] + pub fn txen(&self) -> TXEN_R { + TXEN_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&self) -> RXEN_R { + RXEN_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bits 24:25 - LIN Command"] + #[inline(always)] + pub fn lincmd(&self) -> LINCMD_R { + LINCMD_R::new(((self.bits >> 24) & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&mut self) -> CHSIZE_W { + CHSIZE_W { w: self } + } + #[doc = "Bit 6 - Stop Bit Mode"] + #[inline(always)] + pub fn sbmode(&mut self) -> SBMODE_W { + SBMODE_W { w: self } + } + #[doc = "Bit 8 - Collision Detection Enable"] + #[inline(always)] + pub fn colden(&mut self) -> COLDEN_W { + COLDEN_W { w: self } + } + #[doc = "Bit 9 - Start of Frame Detection Enable"] + #[inline(always)] + pub fn sfde(&mut self) -> SFDE_W { + SFDE_W { w: self } + } + #[doc = "Bit 10 - Encoding Format"] + #[inline(always)] + pub fn enc(&mut self) -> ENC_W { + ENC_W { w: self } + } + #[doc = "Bit 13 - Parity Mode"] + #[inline(always)] + pub fn pmode(&mut self) -> PMODE_W { + PMODE_W { w: self } + } + #[doc = "Bit 16 - Transmitter Enable"] + #[inline(always)] + pub fn txen(&mut self) -> TXEN_W { + TXEN_W { w: self } + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&mut self) -> RXEN_W { + RXEN_W { w: self } + } + #[doc = "Bits 24:25 - LIN Command"] + #[inline(always)] + pub fn lincmd(&mut self) -> LINCMD_W { + LINCMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/sercom0/usart_ext/ctrlc.rs b/pac/atsamc20j/src/sercom0/usart_ext/ctrlc.rs new file mode 100644 index 000000000000..5840d5c3bd06 --- /dev/null +++ b/pac/atsamc20j/src/sercom0/usart_ext/ctrlc.rs @@ -0,0 +1,177 @@ +#[doc = "Register `CTRLC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `GTIME` reader - RS485 Guard Time"] +pub struct GTIME_R(crate::FieldReader); +impl GTIME_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + GTIME_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GTIME_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GTIME` writer - RS485 Guard Time"] +pub struct GTIME_W<'a> { + w: &'a mut W, +} +impl<'a> GTIME_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Field `BRKLEN` reader - LIN Master Break Length"] +pub struct BRKLEN_R(crate::FieldReader); +impl BRKLEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BRKLEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BRKLEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BRKLEN` writer - LIN Master Break Length"] +pub struct BRKLEN_W<'a> { + w: &'a mut W, +} +impl<'a> BRKLEN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 8)) | ((value as u32 & 0x03) << 8); + self.w + } +} +#[doc = "Field `HDRDLY` reader - LIN Master Header Delay"] +pub struct HDRDLY_R(crate::FieldReader); +impl HDRDLY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + HDRDLY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HDRDLY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HDRDLY` writer - LIN Master Header Delay"] +pub struct HDRDLY_W<'a> { + w: &'a mut W, +} +impl<'a> HDRDLY_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 10)) | ((value as u32 & 0x03) << 10); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - RS485 Guard Time"] + #[inline(always)] + pub fn gtime(&self) -> GTIME_R { + GTIME_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bits 8:9 - LIN Master Break Length"] + #[inline(always)] + pub fn brklen(&self) -> BRKLEN_R { + BRKLEN_R::new(((self.bits >> 8) & 0x03) as u8) + } + #[doc = "Bits 10:11 - LIN Master Header Delay"] + #[inline(always)] + pub fn hdrdly(&self) -> HDRDLY_R { + HDRDLY_R::new(((self.bits >> 10) & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - RS485 Guard Time"] + #[inline(always)] + pub fn gtime(&mut self) -> GTIME_W { + GTIME_W { w: self } + } + #[doc = "Bits 8:9 - LIN Master Break Length"] + #[inline(always)] + pub fn brklen(&mut self) -> BRKLEN_W { + BRKLEN_W { w: self } + } + #[doc = "Bits 10:11 - LIN Master Header Delay"] + #[inline(always)] + pub fn hdrdly(&mut self) -> HDRDLY_W { + HDRDLY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Control C\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlc](index.html) module"] +pub struct CTRLC_SPEC; +impl crate::RegisterSpec for CTRLC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlc::R](R) reader structure"] +impl crate::Readable for CTRLC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlc::W](W) writer structure"] +impl crate::Writable for CTRLC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLC to value 0"] +impl crate::Resettable for CTRLC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/sercom0/usart_ext/data.rs b/pac/atsamc20j/src/sercom0/usart_ext/data.rs new file mode 100644 index 000000000000..a54152c9571a --- /dev/null +++ b/pac/atsamc20j/src/sercom0/usart_ext/data.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data Value"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data Value"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01ff) | (value as u16 & 0x01ff); + self.w + } +} +impl R { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new((self.bits & 0x01ff) as u16) + } +} +impl W { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/sercom0/usart_ext/dbgctrl.rs b/pac/atsamc20j/src/sercom0/usart_ext/dbgctrl.rs new file mode 100644 index 000000000000..6c844f3fe40d --- /dev/null +++ b/pac/atsamc20j/src/sercom0/usart_ext/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGSTOP` reader - Debug Mode"] +pub struct DBGSTOP_R(crate::FieldReader); +impl DBGSTOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGSTOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGSTOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGSTOP` writer - Debug Mode"] +pub struct DBGSTOP_W<'a> { + w: &'a mut W, +} +impl<'a> DBGSTOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&self) -> DBGSTOP_R { + DBGSTOP_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&mut self) -> DBGSTOP_W { + DBGSTOP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/sercom0/usart_ext/intenclr.rs b/pac/atsamc20j/src/sercom0/usart_ext/intenclr.rs new file mode 100644 index 000000000000..a815553ce666 --- /dev/null +++ b/pac/atsamc20j/src/sercom0/usart_ext/intenclr.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Disable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Disable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Disable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Disable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Disable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Disable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RXS` reader - Receive Start Interrupt Disable"] +pub struct RXS_R(crate::FieldReader); +impl RXS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXS` writer - Receive Start Interrupt Disable"] +pub struct RXS_W<'a> { + w: &'a mut W, +} +impl<'a> RXS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CTSIC` reader - Clear To Send Input Change Interrupt Disable"] +pub struct CTSIC_R(crate::FieldReader); +impl CTSIC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTSIC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTSIC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTSIC` writer - Clear To Send Input Change Interrupt Disable"] +pub struct CTSIC_W<'a> { + w: &'a mut W, +} +impl<'a> CTSIC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RXBRK` reader - Break Received Interrupt Disable"] +pub struct RXBRK_R(crate::FieldReader); +impl RXBRK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXBRK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXBRK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXBRK` writer - Break Received Interrupt Disable"] +pub struct RXBRK_W<'a> { + w: &'a mut W, +} +impl<'a> RXBRK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Disable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Disable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Receive Start Interrupt Disable"] + #[inline(always)] + pub fn rxs(&self) -> RXS_R { + RXS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Disable"] + #[inline(always)] + pub fn ctsic(&self) -> CTSIC_R { + CTSIC_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Break Received Interrupt Disable"] + #[inline(always)] + pub fn rxbrk(&self) -> RXBRK_R { + RXBRK_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Receive Start Interrupt Disable"] + #[inline(always)] + pub fn rxs(&mut self) -> RXS_W { + RXS_W { w: self } + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Disable"] + #[inline(always)] + pub fn ctsic(&mut self) -> CTSIC_W { + CTSIC_W { w: self } + } + #[doc = "Bit 5 - Break Received Interrupt Disable"] + #[inline(always)] + pub fn rxbrk(&mut self) -> RXBRK_W { + RXBRK_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/sercom0/usart_ext/intenset.rs b/pac/atsamc20j/src/sercom0/usart_ext/intenset.rs new file mode 100644 index 000000000000..e800681cf423 --- /dev/null +++ b/pac/atsamc20j/src/sercom0/usart_ext/intenset.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Enable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Enable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Enable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Enable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Enable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Enable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RXS` reader - Receive Start Interrupt Enable"] +pub struct RXS_R(crate::FieldReader); +impl RXS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXS` writer - Receive Start Interrupt Enable"] +pub struct RXS_W<'a> { + w: &'a mut W, +} +impl<'a> RXS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CTSIC` reader - Clear To Send Input Change Interrupt Enable"] +pub struct CTSIC_R(crate::FieldReader); +impl CTSIC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTSIC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTSIC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTSIC` writer - Clear To Send Input Change Interrupt Enable"] +pub struct CTSIC_W<'a> { + w: &'a mut W, +} +impl<'a> CTSIC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RXBRK` reader - Break Received Interrupt Enable"] +pub struct RXBRK_R(crate::FieldReader); +impl RXBRK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXBRK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXBRK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXBRK` writer - Break Received Interrupt Enable"] +pub struct RXBRK_W<'a> { + w: &'a mut W, +} +impl<'a> RXBRK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Receive Start Interrupt Enable"] + #[inline(always)] + pub fn rxs(&self) -> RXS_R { + RXS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Enable"] + #[inline(always)] + pub fn ctsic(&self) -> CTSIC_R { + CTSIC_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Break Received Interrupt Enable"] + #[inline(always)] + pub fn rxbrk(&self) -> RXBRK_R { + RXBRK_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Receive Start Interrupt Enable"] + #[inline(always)] + pub fn rxs(&mut self) -> RXS_W { + RXS_W { w: self } + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Enable"] + #[inline(always)] + pub fn ctsic(&mut self) -> CTSIC_W { + CTSIC_W { w: self } + } + #[doc = "Bit 5 - Break Received Interrupt Enable"] + #[inline(always)] + pub fn rxbrk(&mut self) -> RXBRK_W { + RXBRK_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/sercom0/usart_ext/intflag.rs b/pac/atsamc20j/src/sercom0/usart_ext/intflag.rs new file mode 100644 index 000000000000..4b0be279a9ae --- /dev/null +++ b/pac/atsamc20j/src/sercom0/usart_ext/intflag.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RXS` reader - Receive Start Interrupt"] +pub struct RXS_R(crate::FieldReader); +impl RXS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXS` writer - Receive Start Interrupt"] +pub struct RXS_W<'a> { + w: &'a mut W, +} +impl<'a> RXS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CTSIC` reader - Clear To Send Input Change Interrupt"] +pub struct CTSIC_R(crate::FieldReader); +impl CTSIC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTSIC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTSIC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTSIC` writer - Clear To Send Input Change Interrupt"] +pub struct CTSIC_W<'a> { + w: &'a mut W, +} +impl<'a> CTSIC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RXBRK` reader - Break Received Interrupt"] +pub struct RXBRK_R(crate::FieldReader); +impl RXBRK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXBRK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXBRK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXBRK` writer - Break Received Interrupt"] +pub struct RXBRK_W<'a> { + w: &'a mut W, +} +impl<'a> RXBRK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Receive Start Interrupt"] + #[inline(always)] + pub fn rxs(&self) -> RXS_R { + RXS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt"] + #[inline(always)] + pub fn ctsic(&self) -> CTSIC_R { + CTSIC_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Break Received Interrupt"] + #[inline(always)] + pub fn rxbrk(&self) -> RXBRK_R { + RXBRK_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Receive Start Interrupt"] + #[inline(always)] + pub fn rxs(&mut self) -> RXS_W { + RXS_W { w: self } + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt"] + #[inline(always)] + pub fn ctsic(&mut self) -> CTSIC_W { + CTSIC_W { w: self } + } + #[doc = "Bit 5 - Break Received Interrupt"] + #[inline(always)] + pub fn rxbrk(&mut self) -> RXBRK_W { + RXBRK_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/sercom0/usart_ext/rxpl.rs b/pac/atsamc20j/src/sercom0/usart_ext/rxpl.rs new file mode 100644 index 000000000000..174464dc16b5 --- /dev/null +++ b/pac/atsamc20j/src/sercom0/usart_ext/rxpl.rs @@ -0,0 +1,103 @@ +#[doc = "Register `RXPL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RXPL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RXPL` reader - Receive Pulse Length"] +pub struct RXPL_R(crate::FieldReader); +impl RXPL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RXPL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXPL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXPL` writer - Receive Pulse Length"] +pub struct RXPL_W<'a> { + w: &'a mut W, +} +impl<'a> RXPL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Receive Pulse Length"] + #[inline(always)] + pub fn rxpl(&self) -> RXPL_R { + RXPL_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Receive Pulse Length"] + #[inline(always)] + pub fn rxpl(&mut self) -> RXPL_W { + RXPL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Receive Pulse Length\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxpl](index.html) module"] +pub struct RXPL_SPEC; +impl crate::RegisterSpec for RXPL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [rxpl::R](R) reader structure"] +impl crate::Readable for RXPL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rxpl::W](W) writer structure"] +impl crate::Writable for RXPL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RXPL to value 0"] +impl crate::Resettable for RXPL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/sercom0/usart_ext/status.rs b/pac/atsamc20j/src/sercom0/usart_ext/status.rs new file mode 100644 index 000000000000..a0c50c1bc2cf --- /dev/null +++ b/pac/atsamc20j/src/sercom0/usart_ext/status.rs @@ -0,0 +1,395 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PERR` reader - Parity Error"] +pub struct PERR_R(crate::FieldReader); +impl PERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERR` writer - Parity Error"] +pub struct PERR_W<'a> { + w: &'a mut W, +} +impl<'a> PERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `FERR` reader - Frame Error"] +pub struct FERR_R(crate::FieldReader); +impl FERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FERR` writer - Frame Error"] +pub struct FERR_W<'a> { + w: &'a mut W, +} +impl<'a> FERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `BUFOVF` reader - Buffer Overflow"] +pub struct BUFOVF_R(crate::FieldReader); +impl BUFOVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUFOVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUFOVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUFOVF` writer - Buffer Overflow"] +pub struct BUFOVF_W<'a> { + w: &'a mut W, +} +impl<'a> BUFOVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CTS` reader - Clear To Send"] +pub struct CTS_R(crate::FieldReader); +impl CTS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTS` writer - Clear To Send"] +pub struct CTS_W<'a> { + w: &'a mut W, +} +impl<'a> CTS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ISF` reader - Inconsistent Sync Field"] +pub struct ISF_R(crate::FieldReader); +impl ISF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ISF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ISF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ISF` writer - Inconsistent Sync Field"] +pub struct ISF_W<'a> { + w: &'a mut W, +} +impl<'a> ISF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `COLL` reader - Collision Detected"] +pub struct COLL_R(crate::FieldReader); +impl COLL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COLL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COLL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COLL` writer - Collision Detected"] +pub struct COLL_W<'a> { + w: &'a mut W, +} +impl<'a> COLL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `TXE` reader - Transmitter Empty"] +pub struct TXE_R(crate::FieldReader); +impl TXE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXE` writer - Transmitter Empty"] +pub struct TXE_W<'a> { + w: &'a mut W, +} +impl<'a> TXE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - Parity Error"] + #[inline(always)] + pub fn perr(&self) -> PERR_R { + PERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Frame Error"] + #[inline(always)] + pub fn ferr(&self) -> FERR_R { + FERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&self) -> BUFOVF_R { + BUFOVF_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Clear To Send"] + #[inline(always)] + pub fn cts(&self) -> CTS_R { + CTS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Inconsistent Sync Field"] + #[inline(always)] + pub fn isf(&self) -> ISF_R { + ISF_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Collision Detected"] + #[inline(always)] + pub fn coll(&self) -> COLL_R { + COLL_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Transmitter Empty"] + #[inline(always)] + pub fn txe(&self) -> TXE_R { + TXE_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Parity Error"] + #[inline(always)] + pub fn perr(&mut self) -> PERR_W { + PERR_W { w: self } + } + #[doc = "Bit 1 - Frame Error"] + #[inline(always)] + pub fn ferr(&mut self) -> FERR_W { + FERR_W { w: self } + } + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&mut self) -> BUFOVF_W { + BUFOVF_W { w: self } + } + #[doc = "Bit 3 - Clear To Send"] + #[inline(always)] + pub fn cts(&mut self) -> CTS_W { + CTS_W { w: self } + } + #[doc = "Bit 4 - Inconsistent Sync Field"] + #[inline(always)] + pub fn isf(&mut self) -> ISF_W { + ISF_W { w: self } + } + #[doc = "Bit 5 - Collision Detected"] + #[inline(always)] + pub fn coll(&mut self) -> COLL_W { + COLL_W { w: self } + } + #[doc = "Bit 6 - Transmitter Empty"] + #[inline(always)] + pub fn txe(&mut self) -> TXE_W { + TXE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/sercom0/usart_ext/syncbusy.rs b/pac/atsamc20j/src/sercom0/usart_ext/syncbusy.rs new file mode 100644 index 000000000000..7c3b817bbb04 --- /dev/null +++ b/pac/atsamc20j/src/sercom0/usart_ext/syncbusy.rs @@ -0,0 +1,93 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - SERCOM Enable Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLB` reader - CTRLB Synchronization Busy"] +pub struct CTRLB_R(crate::FieldReader); +impl CTRLB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM Enable Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - CTRLB Synchronization Busy"] + #[inline(always)] + pub fn ctrlb(&self) -> CTRLB_R { + CTRLB_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +#[doc = "USART_EXT Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/sercom0/usart_int.rs b/pac/atsamc20j/src/sercom0/usart_int.rs new file mode 100644 index 000000000000..157c8c4b4fdc --- /dev/null +++ b/pac/atsamc20j/src/sercom0/usart_int.rs @@ -0,0 +1,60 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "USART_INT Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "USART_INT Control B"] +pub mod ctrlb; +#[doc = "CTRLC register accessor: an alias for `Reg`"] +pub type CTRLC = crate::Reg; +#[doc = "USART_INT Control C"] +pub mod ctrlc; +#[doc = "BAUD register accessor: an alias for `Reg`"] +pub type BAUD = crate::Reg; +#[doc = "USART_INT Baud Rate"] +pub mod baud; +#[doc = "BAUD_FRAC_MODE register accessor: an alias for `Reg`"] +pub type BAUD_FRAC_MODE = crate::Reg; +#[doc = "USART_INT Baud Rate"] +pub mod baud_frac_mode; +#[doc = "BAUD_FRACFP_MODE register accessor: an alias for `Reg`"] +pub type BAUD_FRACFP_MODE = crate::Reg; +#[doc = "USART_INT Baud Rate"] +pub mod baud_fracfp_mode; +#[doc = "BAUD_USARTFP_MODE register accessor: an alias for `Reg`"] +pub type BAUD_USARTFP_MODE = crate::Reg; +#[doc = "USART_INT Baud Rate"] +pub mod baud_usartfp_mode; +#[doc = "RXPL register accessor: an alias for `Reg`"] +pub type RXPL = crate::Reg; +#[doc = "USART_INT Receive Pulse Length"] +pub mod rxpl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "USART_INT Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "USART_INT Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "USART_INT Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "USART_INT Status"] +pub mod status; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "USART_INT Synchronization Busy"] +pub mod syncbusy; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "USART_INT Data"] +pub mod data; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "USART_INT Debug Control"] +pub mod dbgctrl; diff --git a/pac/atsamc20j/src/sercom0/usart_int/baud.rs b/pac/atsamc20j/src/sercom0/usart_int/baud.rs new file mode 100644 index 000000000000..a82df20712b3 --- /dev/null +++ b/pac/atsamc20j/src/sercom0/usart_int/baud.rs @@ -0,0 +1,103 @@ +#[doc = "Register `BAUD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud](index.html) module"] +pub struct BAUD_SPEC; +impl crate::RegisterSpec for BAUD_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud::R](R) reader structure"] +impl crate::Readable for BAUD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud::W](W) writer structure"] +impl crate::Writable for BAUD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD to value 0"] +impl crate::Resettable for BAUD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/sercom0/usart_int/baud_frac_mode.rs b/pac/atsamc20j/src/sercom0/usart_int/baud_frac_mode.rs new file mode 100644 index 000000000000..b9c7fa4c4b2a --- /dev/null +++ b/pac/atsamc20j/src/sercom0/usart_int/baud_frac_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `BAUD_FRAC_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD_FRAC_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1fff) | (value as u16 & 0x1fff); + self.w + } +} +#[doc = "Field `FP` reader - Fractional Part"] +pub struct FP_R(crate::FieldReader); +impl FP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FP` writer - Fractional Part"] +pub struct FP_W<'a> { + w: &'a mut W, +} +impl<'a> FP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 13)) | ((value as u16 & 0x07) << 13); + self.w + } +} +impl R { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new((self.bits & 0x1fff) as u16) + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&self) -> FP_R { + FP_R::new(((self.bits >> 13) & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&mut self) -> FP_W { + FP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud_frac_mode](index.html) module"] +pub struct BAUD_FRAC_MODE_SPEC; +impl crate::RegisterSpec for BAUD_FRAC_MODE_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud_frac_mode::R](R) reader structure"] +impl crate::Readable for BAUD_FRAC_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud_frac_mode::W](W) writer structure"] +impl crate::Writable for BAUD_FRAC_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD_FRAC_MODE to value 0"] +impl crate::Resettable for BAUD_FRAC_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/sercom0/usart_int/baud_fracfp_mode.rs b/pac/atsamc20j/src/sercom0/usart_int/baud_fracfp_mode.rs new file mode 100644 index 000000000000..0671db99cc9d --- /dev/null +++ b/pac/atsamc20j/src/sercom0/usart_int/baud_fracfp_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `BAUD_FRACFP_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD_FRACFP_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1fff) | (value as u16 & 0x1fff); + self.w + } +} +#[doc = "Field `FP` reader - Fractional Part"] +pub struct FP_R(crate::FieldReader); +impl FP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FP` writer - Fractional Part"] +pub struct FP_W<'a> { + w: &'a mut W, +} +impl<'a> FP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 13)) | ((value as u16 & 0x07) << 13); + self.w + } +} +impl R { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new((self.bits & 0x1fff) as u16) + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&self) -> FP_R { + FP_R::new(((self.bits >> 13) & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&mut self) -> FP_W { + FP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud_fracfp_mode](index.html) module"] +pub struct BAUD_FRACFP_MODE_SPEC; +impl crate::RegisterSpec for BAUD_FRACFP_MODE_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud_fracfp_mode::R](R) reader structure"] +impl crate::Readable for BAUD_FRACFP_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud_fracfp_mode::W](W) writer structure"] +impl crate::Writable for BAUD_FRACFP_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD_FRACFP_MODE to value 0"] +impl crate::Resettable for BAUD_FRACFP_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/sercom0/usart_int/baud_usartfp_mode.rs b/pac/atsamc20j/src/sercom0/usart_int/baud_usartfp_mode.rs new file mode 100644 index 000000000000..b49a7ef5b84c --- /dev/null +++ b/pac/atsamc20j/src/sercom0/usart_int/baud_usartfp_mode.rs @@ -0,0 +1,103 @@ +#[doc = "Register `BAUD_USARTFP_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD_USARTFP_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud_usartfp_mode](index.html) module"] +pub struct BAUD_USARTFP_MODE_SPEC; +impl crate::RegisterSpec for BAUD_USARTFP_MODE_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud_usartfp_mode::R](R) reader structure"] +impl crate::Readable for BAUD_USARTFP_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud_usartfp_mode::W](W) writer structure"] +impl crate::Writable for BAUD_USARTFP_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD_USARTFP_MODE to value 0"] +impl crate::Resettable for BAUD_USARTFP_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/sercom0/usart_int/ctrla.rs b/pac/atsamc20j/src/sercom0/usart_int/ctrla.rs new file mode 100644 index 000000000000..19d10ecf8e8f --- /dev/null +++ b/pac/atsamc20j/src/sercom0/usart_int/ctrla.rs @@ -0,0 +1,1171 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: USART with external clock"] + USART_EXT_CLK = 0, + #[doc = "1: USART with internal clock"] + USART_INT_CLK = 1, + #[doc = "2: SPI in slave operation"] + SPI_SLAVE = 2, + #[doc = "3: SPI in master operation"] + SPI_MASTER = 3, + #[doc = "4: I2C slave operation"] + I2C_SLAVE = 4, + #[doc = "5: I2C master operation"] + I2C_MASTER = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::USART_EXT_CLK), + 1 => Some(MODE_A::USART_INT_CLK), + 2 => Some(MODE_A::SPI_SLAVE), + 3 => Some(MODE_A::SPI_MASTER), + 4 => Some(MODE_A::I2C_SLAVE), + 5 => Some(MODE_A::I2C_MASTER), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_EXT_CLK`"] + #[inline(always)] + pub fn is_usart_ext_clk(&self) -> bool { + **self == MODE_A::USART_EXT_CLK + } + #[doc = "Checks if the value of the field is `USART_INT_CLK`"] + #[inline(always)] + pub fn is_usart_int_clk(&self) -> bool { + **self == MODE_A::USART_INT_CLK + } + #[doc = "Checks if the value of the field is `SPI_SLAVE`"] + #[inline(always)] + pub fn is_spi_slave(&self) -> bool { + **self == MODE_A::SPI_SLAVE + } + #[doc = "Checks if the value of the field is `SPI_MASTER`"] + #[inline(always)] + pub fn is_spi_master(&self) -> bool { + **self == MODE_A::SPI_MASTER + } + #[doc = "Checks if the value of the field is `I2C_SLAVE`"] + #[inline(always)] + pub fn is_i2c_slave(&self) -> bool { + **self == MODE_A::I2C_SLAVE + } + #[doc = "Checks if the value of the field is `I2C_MASTER`"] + #[inline(always)] + pub fn is_i2c_master(&self) -> bool { + **self == MODE_A::I2C_MASTER + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART with external clock"] + #[inline(always)] + pub fn usart_ext_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_EXT_CLK) + } + #[doc = "USART with internal clock"] + #[inline(always)] + pub fn usart_int_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_INT_CLK) + } + #[doc = "SPI in slave operation"] + #[inline(always)] + pub fn spi_slave(self) -> &'a mut W { + self.variant(MODE_A::SPI_SLAVE) + } + #[doc = "SPI in master operation"] + #[inline(always)] + pub fn spi_master(self) -> &'a mut W { + self.variant(MODE_A::SPI_MASTER) + } + #[doc = "I2C slave operation"] + #[inline(always)] + pub fn i2c_slave(self) -> &'a mut W { + self.variant(MODE_A::I2C_SLAVE) + } + #[doc = "I2C master operation"] + #[inline(always)] + pub fn i2c_master(self) -> &'a mut W { + self.variant(MODE_A::I2C_MASTER) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 2)) | ((value as u32 & 0x07) << 2); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `IBON` reader - Immediate Buffer Overflow Notification"] +pub struct IBON_R(crate::FieldReader); +impl IBON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IBON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IBON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IBON` writer - Immediate Buffer Overflow Notification"] +pub struct IBON_W<'a> { + w: &'a mut W, +} +impl<'a> IBON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Sample\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SAMPR_A { + #[doc = "0: 16x over-sampling using arithmetic baudrate generation"] + _16X_ARITHMETIC = 0, + #[doc = "1: 16x over-sampling using fractional baudrate generation"] + _16X_FRACTIONAL = 1, + #[doc = "2: 8x over-sampling using arithmetic baudrate generation"] + _8X_ARITHMETIC = 2, + #[doc = "3: 8x over-sampling using fractional baudrate generation"] + _8X_FRACTIONAL = 3, + #[doc = "4: 3x over-sampling using arithmetic baudrate generation"] + _3X_ARITHMETIC = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SAMPR_A) -> Self { + variant as _ + } +} +#[doc = "Field `SAMPR` reader - Sample"] +pub struct SAMPR_R(crate::FieldReader); +impl SAMPR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SAMPR_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SAMPR_A::_16X_ARITHMETIC), + 1 => Some(SAMPR_A::_16X_FRACTIONAL), + 2 => Some(SAMPR_A::_8X_ARITHMETIC), + 3 => Some(SAMPR_A::_8X_FRACTIONAL), + 4 => Some(SAMPR_A::_3X_ARITHMETIC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_16X_ARITHMETIC`"] + #[inline(always)] + pub fn is_16x_arithmetic(&self) -> bool { + **self == SAMPR_A::_16X_ARITHMETIC + } + #[doc = "Checks if the value of the field is `_16X_FRACTIONAL`"] + #[inline(always)] + pub fn is_16x_fractional(&self) -> bool { + **self == SAMPR_A::_16X_FRACTIONAL + } + #[doc = "Checks if the value of the field is `_8X_ARITHMETIC`"] + #[inline(always)] + pub fn is_8x_arithmetic(&self) -> bool { + **self == SAMPR_A::_8X_ARITHMETIC + } + #[doc = "Checks if the value of the field is `_8X_FRACTIONAL`"] + #[inline(always)] + pub fn is_8x_fractional(&self) -> bool { + **self == SAMPR_A::_8X_FRACTIONAL + } + #[doc = "Checks if the value of the field is `_3X_ARITHMETIC`"] + #[inline(always)] + pub fn is_3x_arithmetic(&self) -> bool { + **self == SAMPR_A::_3X_ARITHMETIC + } +} +impl core::ops::Deref for SAMPR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SAMPR` writer - Sample"] +pub struct SAMPR_W<'a> { + w: &'a mut W, +} +impl<'a> SAMPR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SAMPR_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "16x over-sampling using arithmetic baudrate generation"] + #[inline(always)] + pub fn _16x_arithmetic(self) -> &'a mut W { + self.variant(SAMPR_A::_16X_ARITHMETIC) + } + #[doc = "16x over-sampling using fractional baudrate generation"] + #[inline(always)] + pub fn _16x_fractional(self) -> &'a mut W { + self.variant(SAMPR_A::_16X_FRACTIONAL) + } + #[doc = "8x over-sampling using arithmetic baudrate generation"] + #[inline(always)] + pub fn _8x_arithmetic(self) -> &'a mut W { + self.variant(SAMPR_A::_8X_ARITHMETIC) + } + #[doc = "8x over-sampling using fractional baudrate generation"] + #[inline(always)] + pub fn _8x_fractional(self) -> &'a mut W { + self.variant(SAMPR_A::_8X_FRACTIONAL) + } + #[doc = "3x over-sampling using arithmetic baudrate generation"] + #[inline(always)] + pub fn _3x_arithmetic(self) -> &'a mut W { + self.variant(SAMPR_A::_3X_ARITHMETIC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 13)) | ((value as u32 & 0x07) << 13); + self.w + } +} +#[doc = "Transmit Data Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum TXPO_A { + #[doc = "0: SERCOM PAD\\[0\\] +is used for data transmission"] + PAD0 = 0, + #[doc = "1: SERCOM PAD\\[2\\] +is used for data transmission"] + PAD2 = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: TXPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `TXPO` reader - Transmit Data Pinout"] +pub struct TXPO_R(crate::FieldReader); +impl TXPO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TXPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(TXPO_A::PAD0), + 1 => Some(TXPO_A::PAD2), + _ => None, + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == TXPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == TXPO_A::PAD2 + } +} +impl core::ops::Deref for TXPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXPO` writer - Transmit Data Pinout"] +pub struct TXPO_W<'a> { + w: &'a mut W, +} +impl<'a> TXPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TXPO_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "SERCOM PAD\\[0\\] +is used for data transmission"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(TXPO_A::PAD0) + } + #[doc = "SERCOM PAD\\[2\\] +is used for data transmission"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(TXPO_A::PAD2) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Receive Data Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum RXPO_A { + #[doc = "0: SERCOM PAD\\[0\\] +is used for data reception"] + PAD0 = 0, + #[doc = "1: SERCOM PAD\\[1\\] +is used for data reception"] + PAD1 = 1, + #[doc = "2: SERCOM PAD\\[2\\] +is used for data reception"] + PAD2 = 2, + #[doc = "3: SERCOM PAD\\[3\\] +is used for data reception"] + PAD3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RXPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `RXPO` reader - Receive Data Pinout"] +pub struct RXPO_R(crate::FieldReader); +impl RXPO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RXPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RXPO_A { + match self.bits { + 0 => RXPO_A::PAD0, + 1 => RXPO_A::PAD1, + 2 => RXPO_A::PAD2, + 3 => RXPO_A::PAD3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == RXPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD1`"] + #[inline(always)] + pub fn is_pad1(&self) -> bool { + **self == RXPO_A::PAD1 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == RXPO_A::PAD2 + } + #[doc = "Checks if the value of the field is `PAD3`"] + #[inline(always)] + pub fn is_pad3(&self) -> bool { + **self == RXPO_A::PAD3 + } +} +impl core::ops::Deref for RXPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXPO` writer - Receive Data Pinout"] +pub struct RXPO_W<'a> { + w: &'a mut W, +} +impl<'a> RXPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RXPO_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "SERCOM PAD\\[0\\] +is used for data reception"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(RXPO_A::PAD0) + } + #[doc = "SERCOM PAD\\[1\\] +is used for data reception"] + #[inline(always)] + pub fn pad1(self) -> &'a mut W { + self.variant(RXPO_A::PAD1) + } + #[doc = "SERCOM PAD\\[2\\] +is used for data reception"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(RXPO_A::PAD2) + } + #[doc = "SERCOM PAD\\[3\\] +is used for data reception"] + #[inline(always)] + pub fn pad3(self) -> &'a mut W { + self.variant(RXPO_A::PAD3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 20)) | ((value as u32 & 0x03) << 20); + self.w + } +} +#[doc = "Field `SAMPA` reader - Sample Adjustment"] +pub struct SAMPA_R(crate::FieldReader); +impl SAMPA_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SAMPA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SAMPA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SAMPA` writer - Sample Adjustment"] +pub struct SAMPA_W<'a> { + w: &'a mut W, +} +impl<'a> SAMPA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 22)) | ((value as u32 & 0x03) << 22); + self.w + } +} +#[doc = "Frame Format\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FORM_A { + #[doc = "0: USART frame"] + USART_FRAME_NO_PARITY = 0, + #[doc = "1: USART frame with parity"] + USART_FRAME_WITH_PARITY = 1, + #[doc = "2: LIN Master - Break and sync generation"] + USART_FRAME_LIN_MASTER_MODE = 2, + #[doc = "4: Auto-baud - break detection and auto-baud"] + USART_FRAME_AUTO_BAUD_NO_PARITY = 4, + #[doc = "5: Auto-baud - break detection and auto-baud with parity"] + USART_FRAME_AUTO_BAUD_WITH_PARITY = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FORM_A) -> Self { + variant as _ + } +} +#[doc = "Field `FORM` reader - Frame Format"] +pub struct FORM_R(crate::FieldReader); +impl FORM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FORM_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(FORM_A::USART_FRAME_NO_PARITY), + 1 => Some(FORM_A::USART_FRAME_WITH_PARITY), + 2 => Some(FORM_A::USART_FRAME_LIN_MASTER_MODE), + 4 => Some(FORM_A::USART_FRAME_AUTO_BAUD_NO_PARITY), + 5 => Some(FORM_A::USART_FRAME_AUTO_BAUD_WITH_PARITY), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_FRAME_NO_PARITY`"] + #[inline(always)] + pub fn is_usart_frame_no_parity(&self) -> bool { + **self == FORM_A::USART_FRAME_NO_PARITY + } + #[doc = "Checks if the value of the field is `USART_FRAME_WITH_PARITY`"] + #[inline(always)] + pub fn is_usart_frame_with_parity(&self) -> bool { + **self == FORM_A::USART_FRAME_WITH_PARITY + } + #[doc = "Checks if the value of the field is `USART_FRAME_LIN_MASTER_MODE`"] + #[inline(always)] + pub fn is_usart_frame_lin_master_mode(&self) -> bool { + **self == FORM_A::USART_FRAME_LIN_MASTER_MODE + } + #[doc = "Checks if the value of the field is `USART_FRAME_AUTO_BAUD_NO_PARITY`"] + #[inline(always)] + pub fn is_usart_frame_auto_baud_no_parity(&self) -> bool { + **self == FORM_A::USART_FRAME_AUTO_BAUD_NO_PARITY + } + #[doc = "Checks if the value of the field is `USART_FRAME_AUTO_BAUD_WITH_PARITY`"] + #[inline(always)] + pub fn is_usart_frame_auto_baud_with_parity(&self) -> bool { + **self == FORM_A::USART_FRAME_AUTO_BAUD_WITH_PARITY + } +} +impl core::ops::Deref for FORM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FORM` writer - Frame Format"] +pub struct FORM_W<'a> { + w: &'a mut W, +} +impl<'a> FORM_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FORM_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART frame"] + #[inline(always)] + pub fn usart_frame_no_parity(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_NO_PARITY) + } + #[doc = "USART frame with parity"] + #[inline(always)] + pub fn usart_frame_with_parity(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_WITH_PARITY) + } + #[doc = "LIN Master - Break and sync generation"] + #[inline(always)] + pub fn usart_frame_lin_master_mode(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_LIN_MASTER_MODE) + } + #[doc = "Auto-baud - break detection and auto-baud"] + #[inline(always)] + pub fn usart_frame_auto_baud_no_parity(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_AUTO_BAUD_NO_PARITY) + } + #[doc = "Auto-baud - break detection and auto-baud with parity"] + #[inline(always)] + pub fn usart_frame_auto_baud_with_parity(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_AUTO_BAUD_WITH_PARITY) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Communication Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CMODE_A { + #[doc = "0: Asynchronous Communication"] + ASYNC = 0, + #[doc = "1: Synchronous Communication"] + SYNC = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CMODE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CMODE` reader - Communication Mode"] +pub struct CMODE_R(crate::FieldReader); +impl CMODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CMODE_A { + match self.bits { + false => CMODE_A::ASYNC, + true => CMODE_A::SYNC, + } + } + #[doc = "Checks if the value of the field is `ASYNC`"] + #[inline(always)] + pub fn is_async(&self) -> bool { + **self == CMODE_A::ASYNC + } + #[doc = "Checks if the value of the field is `SYNC`"] + #[inline(always)] + pub fn is_sync(&self) -> bool { + **self == CMODE_A::SYNC + } +} +impl core::ops::Deref for CMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMODE` writer - Communication Mode"] +pub struct CMODE_W<'a> { + w: &'a mut W, +} +impl<'a> CMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMODE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Asynchronous Communication"] + #[inline(always)] + pub fn async_(self) -> &'a mut W { + self.variant(CMODE_A::ASYNC) + } + #[doc = "Synchronous Communication"] + #[inline(always)] + pub fn sync(self) -> &'a mut W { + self.variant(CMODE_A::SYNC) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Clock Polarity\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CPOL_A { + #[doc = "0: TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge"] + IDLE_LOW = 0, + #[doc = "1: TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge"] + IDLE_HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CPOL_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CPOL` reader - Clock Polarity"] +pub struct CPOL_R(crate::FieldReader); +impl CPOL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPOL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CPOL_A { + match self.bits { + false => CPOL_A::IDLE_LOW, + true => CPOL_A::IDLE_HIGH, + } + } + #[doc = "Checks if the value of the field is `IDLE_LOW`"] + #[inline(always)] + pub fn is_idle_low(&self) -> bool { + **self == CPOL_A::IDLE_LOW + } + #[doc = "Checks if the value of the field is `IDLE_HIGH`"] + #[inline(always)] + pub fn is_idle_high(&self) -> bool { + **self == CPOL_A::IDLE_HIGH + } +} +impl core::ops::Deref for CPOL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPOL` writer - Clock Polarity"] +pub struct CPOL_W<'a> { + w: &'a mut W, +} +impl<'a> CPOL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CPOL_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge"] + #[inline(always)] + pub fn idle_low(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_LOW) + } + #[doc = "TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge"] + #[inline(always)] + pub fn idle_high(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_HIGH) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29); + self.w + } +} +#[doc = "Data Order\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum DORD_A { + #[doc = "0: MSB is transmitted first"] + MSB = 0, + #[doc = "1: LSB is transmitted first"] + LSB = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DORD_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DORD` reader - Data Order"] +pub struct DORD_R(crate::FieldReader); +impl DORD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DORD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DORD_A { + match self.bits { + false => DORD_A::MSB, + true => DORD_A::LSB, + } + } + #[doc = "Checks if the value of the field is `MSB`"] + #[inline(always)] + pub fn is_msb(&self) -> bool { + **self == DORD_A::MSB + } + #[doc = "Checks if the value of the field is `LSB`"] + #[inline(always)] + pub fn is_lsb(&self) -> bool { + **self == DORD_A::LSB + } +} +impl core::ops::Deref for DORD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DORD` writer - Data Order"] +pub struct DORD_W<'a> { + w: &'a mut W, +} +impl<'a> DORD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DORD_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "MSB is transmitted first"] + #[inline(always)] + pub fn msb(self) -> &'a mut W { + self.variant(DORD_A::MSB) + } + #[doc = "LSB is transmitted first"] + #[inline(always)] + pub fn lsb(self) -> &'a mut W { + self.variant(DORD_A::LSB) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x07) as u8) + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&self) -> IBON_R { + IBON_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bits 13:15 - Sample"] + #[inline(always)] + pub fn sampr(&self) -> SAMPR_R { + SAMPR_R::new(((self.bits >> 13) & 0x07) as u8) + } + #[doc = "Bits 16:17 - Transmit Data Pinout"] + #[inline(always)] + pub fn txpo(&self) -> TXPO_R { + TXPO_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bits 20:21 - Receive Data Pinout"] + #[inline(always)] + pub fn rxpo(&self) -> RXPO_R { + RXPO_R::new(((self.bits >> 20) & 0x03) as u8) + } + #[doc = "Bits 22:23 - Sample Adjustment"] + #[inline(always)] + pub fn sampa(&self) -> SAMPA_R { + SAMPA_R::new(((self.bits >> 22) & 0x03) as u8) + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&self) -> FORM_R { + FORM_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 28 - Communication Mode"] + #[inline(always)] + pub fn cmode(&self) -> CMODE_R { + CMODE_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&self) -> CPOL_R { + CPOL_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&self) -> DORD_R { + DORD_R::new(((self.bits >> 30) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&mut self) -> IBON_W { + IBON_W { w: self } + } + #[doc = "Bits 13:15 - Sample"] + #[inline(always)] + pub fn sampr(&mut self) -> SAMPR_W { + SAMPR_W { w: self } + } + #[doc = "Bits 16:17 - Transmit Data Pinout"] + #[inline(always)] + pub fn txpo(&mut self) -> TXPO_W { + TXPO_W { w: self } + } + #[doc = "Bits 20:21 - Receive Data Pinout"] + #[inline(always)] + pub fn rxpo(&mut self) -> RXPO_W { + RXPO_W { w: self } + } + #[doc = "Bits 22:23 - Sample Adjustment"] + #[inline(always)] + pub fn sampa(&mut self) -> SAMPA_W { + SAMPA_W { w: self } + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&mut self) -> FORM_W { + FORM_W { w: self } + } + #[doc = "Bit 28 - Communication Mode"] + #[inline(always)] + pub fn cmode(&mut self) -> CMODE_W { + CMODE_W { w: self } + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&mut self) -> CPOL_W { + CPOL_W { w: self } + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&mut self) -> DORD_W { + DORD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/sercom0/usart_int/ctrlb.rs b/pac/atsamc20j/src/sercom0/usart_int/ctrlb.rs new file mode 100644 index 000000000000..d556e0c3cfc2 --- /dev/null +++ b/pac/atsamc20j/src/sercom0/usart_int/ctrlb.rs @@ -0,0 +1,651 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Character Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CHSIZE_A { + #[doc = "0: 8 Bits"] + _8_BIT = 0, + #[doc = "1: 9 Bits"] + _9_BIT = 1, + #[doc = "5: 5 Bits"] + _5_BIT = 5, + #[doc = "6: 6 Bits"] + _6_BIT = 6, + #[doc = "7: 7 Bits"] + _7_BIT = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CHSIZE_A) -> Self { + variant as _ + } +} +#[doc = "Field `CHSIZE` reader - Character Size"] +pub struct CHSIZE_R(crate::FieldReader); +impl CHSIZE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CHSIZE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CHSIZE_A::_8_BIT), + 1 => Some(CHSIZE_A::_9_BIT), + 5 => Some(CHSIZE_A::_5_BIT), + 6 => Some(CHSIZE_A::_6_BIT), + 7 => Some(CHSIZE_A::_7_BIT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_8_BIT`"] + #[inline(always)] + pub fn is_8_bit(&self) -> bool { + **self == CHSIZE_A::_8_BIT + } + #[doc = "Checks if the value of the field is `_9_BIT`"] + #[inline(always)] + pub fn is_9_bit(&self) -> bool { + **self == CHSIZE_A::_9_BIT + } + #[doc = "Checks if the value of the field is `_5_BIT`"] + #[inline(always)] + pub fn is_5_bit(&self) -> bool { + **self == CHSIZE_A::_5_BIT + } + #[doc = "Checks if the value of the field is `_6_BIT`"] + #[inline(always)] + pub fn is_6_bit(&self) -> bool { + **self == CHSIZE_A::_6_BIT + } + #[doc = "Checks if the value of the field is `_7_BIT`"] + #[inline(always)] + pub fn is_7_bit(&self) -> bool { + **self == CHSIZE_A::_7_BIT + } +} +impl core::ops::Deref for CHSIZE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHSIZE` writer - Character Size"] +pub struct CHSIZE_W<'a> { + w: &'a mut W, +} +impl<'a> CHSIZE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CHSIZE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8 Bits"] + #[inline(always)] + pub fn _8_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_8_BIT) + } + #[doc = "9 Bits"] + #[inline(always)] + pub fn _9_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_9_BIT) + } + #[doc = "5 Bits"] + #[inline(always)] + pub fn _5_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_5_BIT) + } + #[doc = "6 Bits"] + #[inline(always)] + pub fn _6_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_6_BIT) + } + #[doc = "7 Bits"] + #[inline(always)] + pub fn _7_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_7_BIT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Stop Bit Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SBMODE_A { + #[doc = "0: One Stop Bit"] + _1_BIT = 0, + #[doc = "1: Two Stop Bits"] + _2_BIT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SBMODE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SBMODE` reader - Stop Bit Mode"] +pub struct SBMODE_R(crate::FieldReader); +impl SBMODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SBMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SBMODE_A { + match self.bits { + false => SBMODE_A::_1_BIT, + true => SBMODE_A::_2_BIT, + } + } + #[doc = "Checks if the value of the field is `_1_BIT`"] + #[inline(always)] + pub fn is_1_bit(&self) -> bool { + **self == SBMODE_A::_1_BIT + } + #[doc = "Checks if the value of the field is `_2_BIT`"] + #[inline(always)] + pub fn is_2_bit(&self) -> bool { + **self == SBMODE_A::_2_BIT + } +} +impl core::ops::Deref for SBMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SBMODE` writer - Stop Bit Mode"] +pub struct SBMODE_W<'a> { + w: &'a mut W, +} +impl<'a> SBMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SBMODE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "One Stop Bit"] + #[inline(always)] + pub fn _1_bit(self) -> &'a mut W { + self.variant(SBMODE_A::_1_BIT) + } + #[doc = "Two Stop Bits"] + #[inline(always)] + pub fn _2_bit(self) -> &'a mut W { + self.variant(SBMODE_A::_2_BIT) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `COLDEN` reader - Collision Detection Enable"] +pub struct COLDEN_R(crate::FieldReader); +impl COLDEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COLDEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COLDEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COLDEN` writer - Collision Detection Enable"] +pub struct COLDEN_W<'a> { + w: &'a mut W, +} +impl<'a> COLDEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `SFDE` reader - Start of Frame Detection Enable"] +pub struct SFDE_R(crate::FieldReader); +impl SFDE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SFDE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SFDE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SFDE` writer - Start of Frame Detection Enable"] +pub struct SFDE_W<'a> { + w: &'a mut W, +} +impl<'a> SFDE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `ENC` reader - Encoding Format"] +pub struct ENC_R(crate::FieldReader); +impl ENC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENC` writer - Encoding Format"] +pub struct ENC_W<'a> { + w: &'a mut W, +} +impl<'a> ENC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Parity Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PMODE_A { + #[doc = "0: Even Parity"] + EVEN = 0, + #[doc = "1: Odd Parity"] + ODD = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PMODE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PMODE` reader - Parity Mode"] +pub struct PMODE_R(crate::FieldReader); +impl PMODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PMODE_A { + match self.bits { + false => PMODE_A::EVEN, + true => PMODE_A::ODD, + } + } + #[doc = "Checks if the value of the field is `EVEN`"] + #[inline(always)] + pub fn is_even(&self) -> bool { + **self == PMODE_A::EVEN + } + #[doc = "Checks if the value of the field is `ODD`"] + #[inline(always)] + pub fn is_odd(&self) -> bool { + **self == PMODE_A::ODD + } +} +impl core::ops::Deref for PMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PMODE` writer - Parity Mode"] +pub struct PMODE_W<'a> { + w: &'a mut W, +} +impl<'a> PMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PMODE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Even Parity"] + #[inline(always)] + pub fn even(self) -> &'a mut W { + self.variant(PMODE_A::EVEN) + } + #[doc = "Odd Parity"] + #[inline(always)] + pub fn odd(self) -> &'a mut W { + self.variant(PMODE_A::ODD) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `TXEN` reader - Transmitter Enable"] +pub struct TXEN_R(crate::FieldReader); +impl TXEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXEN` writer - Transmitter Enable"] +pub struct TXEN_W<'a> { + w: &'a mut W, +} +impl<'a> TXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `RXEN` reader - Receiver Enable"] +pub struct RXEN_R(crate::FieldReader); +impl RXEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXEN` writer - Receiver Enable"] +pub struct RXEN_W<'a> { + w: &'a mut W, +} +impl<'a> RXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `LINCMD` reader - LIN Command"] +pub struct LINCMD_R(crate::FieldReader); +impl LINCMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LINCMD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LINCMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LINCMD` writer - LIN Command"] +pub struct LINCMD_W<'a> { + w: &'a mut W, +} +impl<'a> LINCMD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 24)) | ((value as u32 & 0x03) << 24); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&self) -> CHSIZE_R { + CHSIZE_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 6 - Stop Bit Mode"] + #[inline(always)] + pub fn sbmode(&self) -> SBMODE_R { + SBMODE_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 8 - Collision Detection Enable"] + #[inline(always)] + pub fn colden(&self) -> COLDEN_R { + COLDEN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Start of Frame Detection Enable"] + #[inline(always)] + pub fn sfde(&self) -> SFDE_R { + SFDE_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Encoding Format"] + #[inline(always)] + pub fn enc(&self) -> ENC_R { + ENC_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 13 - Parity Mode"] + #[inline(always)] + pub fn pmode(&self) -> PMODE_R { + PMODE_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 16 - Transmitter Enable"] + #[inline(always)] + pub fn txen(&self) -> TXEN_R { + TXEN_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&self) -> RXEN_R { + RXEN_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bits 24:25 - LIN Command"] + #[inline(always)] + pub fn lincmd(&self) -> LINCMD_R { + LINCMD_R::new(((self.bits >> 24) & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&mut self) -> CHSIZE_W { + CHSIZE_W { w: self } + } + #[doc = "Bit 6 - Stop Bit Mode"] + #[inline(always)] + pub fn sbmode(&mut self) -> SBMODE_W { + SBMODE_W { w: self } + } + #[doc = "Bit 8 - Collision Detection Enable"] + #[inline(always)] + pub fn colden(&mut self) -> COLDEN_W { + COLDEN_W { w: self } + } + #[doc = "Bit 9 - Start of Frame Detection Enable"] + #[inline(always)] + pub fn sfde(&mut self) -> SFDE_W { + SFDE_W { w: self } + } + #[doc = "Bit 10 - Encoding Format"] + #[inline(always)] + pub fn enc(&mut self) -> ENC_W { + ENC_W { w: self } + } + #[doc = "Bit 13 - Parity Mode"] + #[inline(always)] + pub fn pmode(&mut self) -> PMODE_W { + PMODE_W { w: self } + } + #[doc = "Bit 16 - Transmitter Enable"] + #[inline(always)] + pub fn txen(&mut self) -> TXEN_W { + TXEN_W { w: self } + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&mut self) -> RXEN_W { + RXEN_W { w: self } + } + #[doc = "Bits 24:25 - LIN Command"] + #[inline(always)] + pub fn lincmd(&mut self) -> LINCMD_W { + LINCMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/sercom0/usart_int/ctrlc.rs b/pac/atsamc20j/src/sercom0/usart_int/ctrlc.rs new file mode 100644 index 000000000000..e2182cc7f768 --- /dev/null +++ b/pac/atsamc20j/src/sercom0/usart_int/ctrlc.rs @@ -0,0 +1,177 @@ +#[doc = "Register `CTRLC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `GTIME` reader - RS485 Guard Time"] +pub struct GTIME_R(crate::FieldReader); +impl GTIME_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + GTIME_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GTIME_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GTIME` writer - RS485 Guard Time"] +pub struct GTIME_W<'a> { + w: &'a mut W, +} +impl<'a> GTIME_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Field `BRKLEN` reader - LIN Master Break Length"] +pub struct BRKLEN_R(crate::FieldReader); +impl BRKLEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BRKLEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BRKLEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BRKLEN` writer - LIN Master Break Length"] +pub struct BRKLEN_W<'a> { + w: &'a mut W, +} +impl<'a> BRKLEN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 8)) | ((value as u32 & 0x03) << 8); + self.w + } +} +#[doc = "Field `HDRDLY` reader - LIN Master Header Delay"] +pub struct HDRDLY_R(crate::FieldReader); +impl HDRDLY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + HDRDLY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HDRDLY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HDRDLY` writer - LIN Master Header Delay"] +pub struct HDRDLY_W<'a> { + w: &'a mut W, +} +impl<'a> HDRDLY_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 10)) | ((value as u32 & 0x03) << 10); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - RS485 Guard Time"] + #[inline(always)] + pub fn gtime(&self) -> GTIME_R { + GTIME_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bits 8:9 - LIN Master Break Length"] + #[inline(always)] + pub fn brklen(&self) -> BRKLEN_R { + BRKLEN_R::new(((self.bits >> 8) & 0x03) as u8) + } + #[doc = "Bits 10:11 - LIN Master Header Delay"] + #[inline(always)] + pub fn hdrdly(&self) -> HDRDLY_R { + HDRDLY_R::new(((self.bits >> 10) & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - RS485 Guard Time"] + #[inline(always)] + pub fn gtime(&mut self) -> GTIME_W { + GTIME_W { w: self } + } + #[doc = "Bits 8:9 - LIN Master Break Length"] + #[inline(always)] + pub fn brklen(&mut self) -> BRKLEN_W { + BRKLEN_W { w: self } + } + #[doc = "Bits 10:11 - LIN Master Header Delay"] + #[inline(always)] + pub fn hdrdly(&mut self) -> HDRDLY_W { + HDRDLY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Control C\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlc](index.html) module"] +pub struct CTRLC_SPEC; +impl crate::RegisterSpec for CTRLC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlc::R](R) reader structure"] +impl crate::Readable for CTRLC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlc::W](W) writer structure"] +impl crate::Writable for CTRLC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLC to value 0"] +impl crate::Resettable for CTRLC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/sercom0/usart_int/data.rs b/pac/atsamc20j/src/sercom0/usart_int/data.rs new file mode 100644 index 000000000000..19d74c337d44 --- /dev/null +++ b/pac/atsamc20j/src/sercom0/usart_int/data.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data Value"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data Value"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01ff) | (value as u16 & 0x01ff); + self.w + } +} +impl R { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new((self.bits & 0x01ff) as u16) + } +} +impl W { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/sercom0/usart_int/dbgctrl.rs b/pac/atsamc20j/src/sercom0/usart_int/dbgctrl.rs new file mode 100644 index 000000000000..0ac5b9c7b902 --- /dev/null +++ b/pac/atsamc20j/src/sercom0/usart_int/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGSTOP` reader - Debug Mode"] +pub struct DBGSTOP_R(crate::FieldReader); +impl DBGSTOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGSTOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGSTOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGSTOP` writer - Debug Mode"] +pub struct DBGSTOP_W<'a> { + w: &'a mut W, +} +impl<'a> DBGSTOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&self) -> DBGSTOP_R { + DBGSTOP_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&mut self) -> DBGSTOP_W { + DBGSTOP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/sercom0/usart_int/intenclr.rs b/pac/atsamc20j/src/sercom0/usart_int/intenclr.rs new file mode 100644 index 000000000000..5ad23ad15636 --- /dev/null +++ b/pac/atsamc20j/src/sercom0/usart_int/intenclr.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Disable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Disable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Disable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Disable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Disable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Disable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RXS` reader - Receive Start Interrupt Disable"] +pub struct RXS_R(crate::FieldReader); +impl RXS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXS` writer - Receive Start Interrupt Disable"] +pub struct RXS_W<'a> { + w: &'a mut W, +} +impl<'a> RXS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CTSIC` reader - Clear To Send Input Change Interrupt Disable"] +pub struct CTSIC_R(crate::FieldReader); +impl CTSIC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTSIC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTSIC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTSIC` writer - Clear To Send Input Change Interrupt Disable"] +pub struct CTSIC_W<'a> { + w: &'a mut W, +} +impl<'a> CTSIC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RXBRK` reader - Break Received Interrupt Disable"] +pub struct RXBRK_R(crate::FieldReader); +impl RXBRK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXBRK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXBRK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXBRK` writer - Break Received Interrupt Disable"] +pub struct RXBRK_W<'a> { + w: &'a mut W, +} +impl<'a> RXBRK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Disable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Disable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Receive Start Interrupt Disable"] + #[inline(always)] + pub fn rxs(&self) -> RXS_R { + RXS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Disable"] + #[inline(always)] + pub fn ctsic(&self) -> CTSIC_R { + CTSIC_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Break Received Interrupt Disable"] + #[inline(always)] + pub fn rxbrk(&self) -> RXBRK_R { + RXBRK_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Receive Start Interrupt Disable"] + #[inline(always)] + pub fn rxs(&mut self) -> RXS_W { + RXS_W { w: self } + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Disable"] + #[inline(always)] + pub fn ctsic(&mut self) -> CTSIC_W { + CTSIC_W { w: self } + } + #[doc = "Bit 5 - Break Received Interrupt Disable"] + #[inline(always)] + pub fn rxbrk(&mut self) -> RXBRK_W { + RXBRK_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/sercom0/usart_int/intenset.rs b/pac/atsamc20j/src/sercom0/usart_int/intenset.rs new file mode 100644 index 000000000000..457f440e13e9 --- /dev/null +++ b/pac/atsamc20j/src/sercom0/usart_int/intenset.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Enable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Enable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Enable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Enable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Enable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Enable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RXS` reader - Receive Start Interrupt Enable"] +pub struct RXS_R(crate::FieldReader); +impl RXS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXS` writer - Receive Start Interrupt Enable"] +pub struct RXS_W<'a> { + w: &'a mut W, +} +impl<'a> RXS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CTSIC` reader - Clear To Send Input Change Interrupt Enable"] +pub struct CTSIC_R(crate::FieldReader); +impl CTSIC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTSIC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTSIC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTSIC` writer - Clear To Send Input Change Interrupt Enable"] +pub struct CTSIC_W<'a> { + w: &'a mut W, +} +impl<'a> CTSIC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RXBRK` reader - Break Received Interrupt Enable"] +pub struct RXBRK_R(crate::FieldReader); +impl RXBRK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXBRK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXBRK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXBRK` writer - Break Received Interrupt Enable"] +pub struct RXBRK_W<'a> { + w: &'a mut W, +} +impl<'a> RXBRK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Receive Start Interrupt Enable"] + #[inline(always)] + pub fn rxs(&self) -> RXS_R { + RXS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Enable"] + #[inline(always)] + pub fn ctsic(&self) -> CTSIC_R { + CTSIC_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Break Received Interrupt Enable"] + #[inline(always)] + pub fn rxbrk(&self) -> RXBRK_R { + RXBRK_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Receive Start Interrupt Enable"] + #[inline(always)] + pub fn rxs(&mut self) -> RXS_W { + RXS_W { w: self } + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Enable"] + #[inline(always)] + pub fn ctsic(&mut self) -> CTSIC_W { + CTSIC_W { w: self } + } + #[doc = "Bit 5 - Break Received Interrupt Enable"] + #[inline(always)] + pub fn rxbrk(&mut self) -> RXBRK_W { + RXBRK_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/sercom0/usart_int/intflag.rs b/pac/atsamc20j/src/sercom0/usart_int/intflag.rs new file mode 100644 index 000000000000..a6a26321b8c4 --- /dev/null +++ b/pac/atsamc20j/src/sercom0/usart_int/intflag.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RXS` reader - Receive Start Interrupt"] +pub struct RXS_R(crate::FieldReader); +impl RXS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXS` writer - Receive Start Interrupt"] +pub struct RXS_W<'a> { + w: &'a mut W, +} +impl<'a> RXS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CTSIC` reader - Clear To Send Input Change Interrupt"] +pub struct CTSIC_R(crate::FieldReader); +impl CTSIC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTSIC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTSIC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTSIC` writer - Clear To Send Input Change Interrupt"] +pub struct CTSIC_W<'a> { + w: &'a mut W, +} +impl<'a> CTSIC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RXBRK` reader - Break Received Interrupt"] +pub struct RXBRK_R(crate::FieldReader); +impl RXBRK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXBRK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXBRK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXBRK` writer - Break Received Interrupt"] +pub struct RXBRK_W<'a> { + w: &'a mut W, +} +impl<'a> RXBRK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Receive Start Interrupt"] + #[inline(always)] + pub fn rxs(&self) -> RXS_R { + RXS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt"] + #[inline(always)] + pub fn ctsic(&self) -> CTSIC_R { + CTSIC_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Break Received Interrupt"] + #[inline(always)] + pub fn rxbrk(&self) -> RXBRK_R { + RXBRK_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Receive Start Interrupt"] + #[inline(always)] + pub fn rxs(&mut self) -> RXS_W { + RXS_W { w: self } + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt"] + #[inline(always)] + pub fn ctsic(&mut self) -> CTSIC_W { + CTSIC_W { w: self } + } + #[doc = "Bit 5 - Break Received Interrupt"] + #[inline(always)] + pub fn rxbrk(&mut self) -> RXBRK_W { + RXBRK_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/sercom0/usart_int/rxpl.rs b/pac/atsamc20j/src/sercom0/usart_int/rxpl.rs new file mode 100644 index 000000000000..324cbac371c1 --- /dev/null +++ b/pac/atsamc20j/src/sercom0/usart_int/rxpl.rs @@ -0,0 +1,103 @@ +#[doc = "Register `RXPL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RXPL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RXPL` reader - Receive Pulse Length"] +pub struct RXPL_R(crate::FieldReader); +impl RXPL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RXPL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXPL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXPL` writer - Receive Pulse Length"] +pub struct RXPL_W<'a> { + w: &'a mut W, +} +impl<'a> RXPL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Receive Pulse Length"] + #[inline(always)] + pub fn rxpl(&self) -> RXPL_R { + RXPL_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Receive Pulse Length"] + #[inline(always)] + pub fn rxpl(&mut self) -> RXPL_W { + RXPL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Receive Pulse Length\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxpl](index.html) module"] +pub struct RXPL_SPEC; +impl crate::RegisterSpec for RXPL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [rxpl::R](R) reader structure"] +impl crate::Readable for RXPL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rxpl::W](W) writer structure"] +impl crate::Writable for RXPL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RXPL to value 0"] +impl crate::Resettable for RXPL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/sercom0/usart_int/status.rs b/pac/atsamc20j/src/sercom0/usart_int/status.rs new file mode 100644 index 000000000000..1a92018a359b --- /dev/null +++ b/pac/atsamc20j/src/sercom0/usart_int/status.rs @@ -0,0 +1,395 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PERR` reader - Parity Error"] +pub struct PERR_R(crate::FieldReader); +impl PERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERR` writer - Parity Error"] +pub struct PERR_W<'a> { + w: &'a mut W, +} +impl<'a> PERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `FERR` reader - Frame Error"] +pub struct FERR_R(crate::FieldReader); +impl FERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FERR` writer - Frame Error"] +pub struct FERR_W<'a> { + w: &'a mut W, +} +impl<'a> FERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `BUFOVF` reader - Buffer Overflow"] +pub struct BUFOVF_R(crate::FieldReader); +impl BUFOVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUFOVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUFOVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUFOVF` writer - Buffer Overflow"] +pub struct BUFOVF_W<'a> { + w: &'a mut W, +} +impl<'a> BUFOVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CTS` reader - Clear To Send"] +pub struct CTS_R(crate::FieldReader); +impl CTS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTS` writer - Clear To Send"] +pub struct CTS_W<'a> { + w: &'a mut W, +} +impl<'a> CTS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ISF` reader - Inconsistent Sync Field"] +pub struct ISF_R(crate::FieldReader); +impl ISF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ISF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ISF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ISF` writer - Inconsistent Sync Field"] +pub struct ISF_W<'a> { + w: &'a mut W, +} +impl<'a> ISF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `COLL` reader - Collision Detected"] +pub struct COLL_R(crate::FieldReader); +impl COLL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COLL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COLL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COLL` writer - Collision Detected"] +pub struct COLL_W<'a> { + w: &'a mut W, +} +impl<'a> COLL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `TXE` reader - Transmitter Empty"] +pub struct TXE_R(crate::FieldReader); +impl TXE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXE` writer - Transmitter Empty"] +pub struct TXE_W<'a> { + w: &'a mut W, +} +impl<'a> TXE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - Parity Error"] + #[inline(always)] + pub fn perr(&self) -> PERR_R { + PERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Frame Error"] + #[inline(always)] + pub fn ferr(&self) -> FERR_R { + FERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&self) -> BUFOVF_R { + BUFOVF_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Clear To Send"] + #[inline(always)] + pub fn cts(&self) -> CTS_R { + CTS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Inconsistent Sync Field"] + #[inline(always)] + pub fn isf(&self) -> ISF_R { + ISF_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Collision Detected"] + #[inline(always)] + pub fn coll(&self) -> COLL_R { + COLL_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Transmitter Empty"] + #[inline(always)] + pub fn txe(&self) -> TXE_R { + TXE_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Parity Error"] + #[inline(always)] + pub fn perr(&mut self) -> PERR_W { + PERR_W { w: self } + } + #[doc = "Bit 1 - Frame Error"] + #[inline(always)] + pub fn ferr(&mut self) -> FERR_W { + FERR_W { w: self } + } + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&mut self) -> BUFOVF_W { + BUFOVF_W { w: self } + } + #[doc = "Bit 3 - Clear To Send"] + #[inline(always)] + pub fn cts(&mut self) -> CTS_W { + CTS_W { w: self } + } + #[doc = "Bit 4 - Inconsistent Sync Field"] + #[inline(always)] + pub fn isf(&mut self) -> ISF_W { + ISF_W { w: self } + } + #[doc = "Bit 5 - Collision Detected"] + #[inline(always)] + pub fn coll(&mut self) -> COLL_W { + COLL_W { w: self } + } + #[doc = "Bit 6 - Transmitter Empty"] + #[inline(always)] + pub fn txe(&mut self) -> TXE_W { + TXE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/sercom0/usart_int/syncbusy.rs b/pac/atsamc20j/src/sercom0/usart_int/syncbusy.rs new file mode 100644 index 000000000000..5dea9a5a7bab --- /dev/null +++ b/pac/atsamc20j/src/sercom0/usart_int/syncbusy.rs @@ -0,0 +1,93 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - SERCOM Enable Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLB` reader - CTRLB Synchronization Busy"] +pub struct CTRLB_R(crate::FieldReader); +impl CTRLB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM Enable Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - CTRLB Synchronization Busy"] + #[inline(always)] + pub fn ctrlb(&self) -> CTRLB_R { + CTRLB_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +#[doc = "USART_INT Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/supc.rs b/pac/atsamc20j/src/supc.rs new file mode 100644 index 000000000000..452d8f3f9613 --- /dev/null +++ b/pac/atsamc20j/src/supc.rs @@ -0,0 +1,52 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x04 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x08 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x0c - Power and Clocks Status"] + pub status: crate::Reg, + #[doc = "0x10 - BODVDD Control"] + pub bodvdd: crate::Reg, + #[doc = "0x14 - BODCORE Control"] + pub bodcore: crate::Reg, + #[doc = "0x18 - VREG Control"] + pub vreg: crate::Reg, + #[doc = "0x1c - VREF Control"] + pub vref: crate::Reg, +} +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Power and Clocks Status"] +pub mod status; +#[doc = "BODVDD register accessor: an alias for `Reg`"] +pub type BODVDD = crate::Reg; +#[doc = "BODVDD Control"] +pub mod bodvdd; +#[doc = "BODCORE register accessor: an alias for `Reg`"] +pub type BODCORE = crate::Reg; +#[doc = "BODCORE Control"] +pub mod bodcore; +#[doc = "VREG register accessor: an alias for `Reg`"] +pub type VREG = crate::Reg; +#[doc = "VREG Control"] +pub mod vreg; +#[doc = "VREF register accessor: an alias for `Reg`"] +pub type VREF = crate::Reg; +#[doc = "VREF Control"] +pub mod vref; diff --git a/pac/atsamc20j/src/supc/bodcore.rs b/pac/atsamc20j/src/supc/bodcore.rs new file mode 100644 index 000000000000..670dec8e048c --- /dev/null +++ b/pac/atsamc20j/src/supc/bodcore.rs @@ -0,0 +1,705 @@ +#[doc = "Register `BODCORE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BODCORE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `HYST` reader - Hysteresis Enable"] +pub struct HYST_R(crate::FieldReader); +impl HYST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HYST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HYST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HYST` writer - Hysteresis Enable"] +pub struct HYST_W<'a> { + w: &'a mut W, +} +impl<'a> HYST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Action when Threshold Crossed\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum ACTION_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: The BODCORE generates a reset"] + RESET = 1, + #[doc = "2: The BODCORE generates an interrupt"] + INT = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: ACTION_A) -> Self { + variant as _ + } +} +#[doc = "Field `ACTION` reader - Action when Threshold Crossed"] +pub struct ACTION_R(crate::FieldReader); +impl ACTION_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ACTION_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(ACTION_A::NONE), + 1 => Some(ACTION_A::RESET), + 2 => Some(ACTION_A::INT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == ACTION_A::NONE + } + #[doc = "Checks if the value of the field is `RESET`"] + #[inline(always)] + pub fn is_reset(&self) -> bool { + **self == ACTION_A::RESET + } + #[doc = "Checks if the value of the field is `INT`"] + #[inline(always)] + pub fn is_int(&self) -> bool { + **self == ACTION_A::INT + } +} +impl core::ops::Deref for ACTION_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ACTION` writer - Action when Threshold Crossed"] +pub struct ACTION_W<'a> { + w: &'a mut W, +} +impl<'a> ACTION_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: ACTION_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(ACTION_A::NONE) + } + #[doc = "The BODCORE generates a reset"] + #[inline(always)] + pub fn reset(self) -> &'a mut W { + self.variant(ACTION_A::RESET) + } + #[doc = "The BODCORE generates an interrupt"] + #[inline(always)] + pub fn int(self) -> &'a mut W { + self.variant(ACTION_A::INT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 3)) | ((value as u32 & 0x03) << 3); + self.w + } +} +#[doc = "Field `STDBYCFG` reader - Configuration in Standby mode"] +pub struct STDBYCFG_R(crate::FieldReader); +impl STDBYCFG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STDBYCFG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STDBYCFG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STDBYCFG` writer - Configuration in Standby mode"] +pub struct STDBYCFG_W<'a> { + w: &'a mut W, +} +impl<'a> STDBYCFG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ACTCFG` reader - Configuration in Active mode"] +pub struct ACTCFG_R(crate::FieldReader); +impl ACTCFG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ACTCFG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ACTCFG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ACTCFG` writer - Configuration in Active mode"] +pub struct ACTCFG_W<'a> { + w: &'a mut W, +} +impl<'a> ACTCFG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Prescaler Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PSEL_A { + #[doc = "0: Divide clock by 2"] + DIV2 = 0, + #[doc = "1: Divide clock by 4"] + DIV4 = 1, + #[doc = "2: Divide clock by 8"] + DIV8 = 2, + #[doc = "3: Divide clock by 16"] + DIV16 = 3, + #[doc = "4: Divide clock by 32"] + DIV32 = 4, + #[doc = "5: Divide clock by 64"] + DIV64 = 5, + #[doc = "6: Divide clock by 128"] + DIV128 = 6, + #[doc = "7: Divide clock by 256"] + DIV256 = 7, + #[doc = "8: Divide clock by 512"] + DIV512 = 8, + #[doc = "9: Divide clock by 1024"] + DIV1024 = 9, + #[doc = "10: Divide clock by 2048"] + DIV2048 = 10, + #[doc = "11: Divide clock by 4096"] + DIV4096 = 11, + #[doc = "12: Divide clock by 8192"] + DIV8192 = 12, + #[doc = "13: Divide clock by 16384"] + DIV16384 = 13, + #[doc = "14: Divide clock by 32768"] + DIV32768 = 14, + #[doc = "15: Divide clock by 65536"] + DIV65536 = 15, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `PSEL` reader - Prescaler Select"] +pub struct PSEL_R(crate::FieldReader); +impl PSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PSEL_A { + match self.bits { + 0 => PSEL_A::DIV2, + 1 => PSEL_A::DIV4, + 2 => PSEL_A::DIV8, + 3 => PSEL_A::DIV16, + 4 => PSEL_A::DIV32, + 5 => PSEL_A::DIV64, + 6 => PSEL_A::DIV128, + 7 => PSEL_A::DIV256, + 8 => PSEL_A::DIV512, + 9 => PSEL_A::DIV1024, + 10 => PSEL_A::DIV2048, + 11 => PSEL_A::DIV4096, + 12 => PSEL_A::DIV8192, + 13 => PSEL_A::DIV16384, + 14 => PSEL_A::DIV32768, + 15 => PSEL_A::DIV65536, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PSEL_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PSEL_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PSEL_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PSEL_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == PSEL_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PSEL_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == PSEL_A::DIV128 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PSEL_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV512`"] + #[inline(always)] + pub fn is_div512(&self) -> bool { + **self == PSEL_A::DIV512 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PSEL_A::DIV1024 + } + #[doc = "Checks if the value of the field is `DIV2048`"] + #[inline(always)] + pub fn is_div2048(&self) -> bool { + **self == PSEL_A::DIV2048 + } + #[doc = "Checks if the value of the field is `DIV4096`"] + #[inline(always)] + pub fn is_div4096(&self) -> bool { + **self == PSEL_A::DIV4096 + } + #[doc = "Checks if the value of the field is `DIV8192`"] + #[inline(always)] + pub fn is_div8192(&self) -> bool { + **self == PSEL_A::DIV8192 + } + #[doc = "Checks if the value of the field is `DIV16384`"] + #[inline(always)] + pub fn is_div16384(&self) -> bool { + **self == PSEL_A::DIV16384 + } + #[doc = "Checks if the value of the field is `DIV32768`"] + #[inline(always)] + pub fn is_div32768(&self) -> bool { + **self == PSEL_A::DIV32768 + } + #[doc = "Checks if the value of the field is `DIV65536`"] + #[inline(always)] + pub fn is_div65536(&self) -> bool { + **self == PSEL_A::DIV65536 + } +} +impl core::ops::Deref for PSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PSEL` writer - Prescaler Select"] +pub struct PSEL_W<'a> { + w: &'a mut W, +} +impl<'a> PSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PSEL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Divide clock by 2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PSEL_A::DIV2) + } + #[doc = "Divide clock by 4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PSEL_A::DIV4) + } + #[doc = "Divide clock by 8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PSEL_A::DIV8) + } + #[doc = "Divide clock by 16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PSEL_A::DIV16) + } + #[doc = "Divide clock by 32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(PSEL_A::DIV32) + } + #[doc = "Divide clock by 64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PSEL_A::DIV64) + } + #[doc = "Divide clock by 128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(PSEL_A::DIV128) + } + #[doc = "Divide clock by 256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PSEL_A::DIV256) + } + #[doc = "Divide clock by 512"] + #[inline(always)] + pub fn div512(self) -> &'a mut W { + self.variant(PSEL_A::DIV512) + } + #[doc = "Divide clock by 1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PSEL_A::DIV1024) + } + #[doc = "Divide clock by 2048"] + #[inline(always)] + pub fn div2048(self) -> &'a mut W { + self.variant(PSEL_A::DIV2048) + } + #[doc = "Divide clock by 4096"] + #[inline(always)] + pub fn div4096(self) -> &'a mut W { + self.variant(PSEL_A::DIV4096) + } + #[doc = "Divide clock by 8192"] + #[inline(always)] + pub fn div8192(self) -> &'a mut W { + self.variant(PSEL_A::DIV8192) + } + #[doc = "Divide clock by 16384"] + #[inline(always)] + pub fn div16384(self) -> &'a mut W { + self.variant(PSEL_A::DIV16384) + } + #[doc = "Divide clock by 32768"] + #[inline(always)] + pub fn div32768(self) -> &'a mut W { + self.variant(PSEL_A::DIV32768) + } + #[doc = "Divide clock by 65536"] + #[inline(always)] + pub fn div65536(self) -> &'a mut W { + self.variant(PSEL_A::DIV65536) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 12)) | ((value as u32 & 0x0f) << 12); + self.w + } +} +#[doc = "Field `LEVEL` reader - Threshold Level"] +pub struct LEVEL_R(crate::FieldReader); +impl LEVEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LEVEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LEVEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LEVEL` writer - Threshold Level"] +pub struct LEVEL_W<'a> { + w: &'a mut W, +} +impl<'a> LEVEL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 16)) | ((value as u32 & 0x3f) << 16); + self.w + } +} +impl R { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Hysteresis Enable"] + #[inline(always)] + pub fn hyst(&self) -> HYST_R { + HYST_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 3:4 - Action when Threshold Crossed"] + #[inline(always)] + pub fn action(&self) -> ACTION_R { + ACTION_R::new(((self.bits >> 3) & 0x03) as u8) + } + #[doc = "Bit 5 - Configuration in Standby mode"] + #[inline(always)] + pub fn stdbycfg(&self) -> STDBYCFG_R { + STDBYCFG_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 8 - Configuration in Active mode"] + #[inline(always)] + pub fn actcfg(&self) -> ACTCFG_R { + ACTCFG_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bits 12:15 - Prescaler Select"] + #[inline(always)] + pub fn psel(&self) -> PSEL_R { + PSEL_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:21 - Threshold Level"] + #[inline(always)] + pub fn level(&self) -> LEVEL_R { + LEVEL_R::new(((self.bits >> 16) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - Hysteresis Enable"] + #[inline(always)] + pub fn hyst(&mut self) -> HYST_W { + HYST_W { w: self } + } + #[doc = "Bits 3:4 - Action when Threshold Crossed"] + #[inline(always)] + pub fn action(&mut self) -> ACTION_W { + ACTION_W { w: self } + } + #[doc = "Bit 5 - Configuration in Standby mode"] + #[inline(always)] + pub fn stdbycfg(&mut self) -> STDBYCFG_W { + STDBYCFG_W { w: self } + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 8 - Configuration in Active mode"] + #[inline(always)] + pub fn actcfg(&mut self) -> ACTCFG_W { + ACTCFG_W { w: self } + } + #[doc = "Bits 12:15 - Prescaler Select"] + #[inline(always)] + pub fn psel(&mut self) -> PSEL_W { + PSEL_W { w: self } + } + #[doc = "Bits 16:21 - Threshold Level"] + #[inline(always)] + pub fn level(&mut self) -> LEVEL_W { + LEVEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "BODCORE Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [bodcore](index.html) module"] +pub struct BODCORE_SPEC; +impl crate::RegisterSpec for BODCORE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [bodcore::R](R) reader structure"] +impl crate::Readable for BODCORE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [bodcore::W](W) writer structure"] +impl crate::Writable for BODCORE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BODCORE to value 0"] +impl crate::Resettable for BODCORE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/supc/bodvdd.rs b/pac/atsamc20j/src/supc/bodvdd.rs new file mode 100644 index 000000000000..f5cbfffb6453 --- /dev/null +++ b/pac/atsamc20j/src/supc/bodvdd.rs @@ -0,0 +1,705 @@ +#[doc = "Register `BODVDD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BODVDD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `HYST` reader - Hysteresis Enable"] +pub struct HYST_R(crate::FieldReader); +impl HYST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HYST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HYST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HYST` writer - Hysteresis Enable"] +pub struct HYST_W<'a> { + w: &'a mut W, +} +impl<'a> HYST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Action when Threshold Crossed\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum ACTION_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: The BODVDD generates a reset"] + RESET = 1, + #[doc = "2: The BODVDD generates an interrupt"] + INT = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: ACTION_A) -> Self { + variant as _ + } +} +#[doc = "Field `ACTION` reader - Action when Threshold Crossed"] +pub struct ACTION_R(crate::FieldReader); +impl ACTION_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ACTION_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(ACTION_A::NONE), + 1 => Some(ACTION_A::RESET), + 2 => Some(ACTION_A::INT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == ACTION_A::NONE + } + #[doc = "Checks if the value of the field is `RESET`"] + #[inline(always)] + pub fn is_reset(&self) -> bool { + **self == ACTION_A::RESET + } + #[doc = "Checks if the value of the field is `INT`"] + #[inline(always)] + pub fn is_int(&self) -> bool { + **self == ACTION_A::INT + } +} +impl core::ops::Deref for ACTION_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ACTION` writer - Action when Threshold Crossed"] +pub struct ACTION_W<'a> { + w: &'a mut W, +} +impl<'a> ACTION_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: ACTION_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(ACTION_A::NONE) + } + #[doc = "The BODVDD generates a reset"] + #[inline(always)] + pub fn reset(self) -> &'a mut W { + self.variant(ACTION_A::RESET) + } + #[doc = "The BODVDD generates an interrupt"] + #[inline(always)] + pub fn int(self) -> &'a mut W { + self.variant(ACTION_A::INT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 3)) | ((value as u32 & 0x03) << 3); + self.w + } +} +#[doc = "Field `STDBYCFG` reader - Configuration in Standby mode"] +pub struct STDBYCFG_R(crate::FieldReader); +impl STDBYCFG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STDBYCFG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STDBYCFG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STDBYCFG` writer - Configuration in Standby mode"] +pub struct STDBYCFG_W<'a> { + w: &'a mut W, +} +impl<'a> STDBYCFG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ACTCFG` reader - Configuration in Active mode"] +pub struct ACTCFG_R(crate::FieldReader); +impl ACTCFG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ACTCFG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ACTCFG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ACTCFG` writer - Configuration in Active mode"] +pub struct ACTCFG_W<'a> { + w: &'a mut W, +} +impl<'a> ACTCFG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Prescaler Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PSEL_A { + #[doc = "0: Divide clock by 2"] + DIV2 = 0, + #[doc = "1: Divide clock by 4"] + DIV4 = 1, + #[doc = "2: Divide clock by 8"] + DIV8 = 2, + #[doc = "3: Divide clock by 16"] + DIV16 = 3, + #[doc = "4: Divide clock by 32"] + DIV32 = 4, + #[doc = "5: Divide clock by 64"] + DIV64 = 5, + #[doc = "6: Divide clock by 128"] + DIV128 = 6, + #[doc = "7: Divide clock by 256"] + DIV256 = 7, + #[doc = "8: Divide clock by 512"] + DIV512 = 8, + #[doc = "9: Divide clock by 1024"] + DIV1024 = 9, + #[doc = "10: Divide clock by 2048"] + DIV2048 = 10, + #[doc = "11: Divide clock by 4096"] + DIV4096 = 11, + #[doc = "12: Divide clock by 8192"] + DIV8192 = 12, + #[doc = "13: Divide clock by 16384"] + DIV16384 = 13, + #[doc = "14: Divide clock by 32768"] + DIV32768 = 14, + #[doc = "15: Divide clock by 65536"] + DIV65536 = 15, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `PSEL` reader - Prescaler Select"] +pub struct PSEL_R(crate::FieldReader); +impl PSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PSEL_A { + match self.bits { + 0 => PSEL_A::DIV2, + 1 => PSEL_A::DIV4, + 2 => PSEL_A::DIV8, + 3 => PSEL_A::DIV16, + 4 => PSEL_A::DIV32, + 5 => PSEL_A::DIV64, + 6 => PSEL_A::DIV128, + 7 => PSEL_A::DIV256, + 8 => PSEL_A::DIV512, + 9 => PSEL_A::DIV1024, + 10 => PSEL_A::DIV2048, + 11 => PSEL_A::DIV4096, + 12 => PSEL_A::DIV8192, + 13 => PSEL_A::DIV16384, + 14 => PSEL_A::DIV32768, + 15 => PSEL_A::DIV65536, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PSEL_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PSEL_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PSEL_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PSEL_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == PSEL_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PSEL_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == PSEL_A::DIV128 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PSEL_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV512`"] + #[inline(always)] + pub fn is_div512(&self) -> bool { + **self == PSEL_A::DIV512 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PSEL_A::DIV1024 + } + #[doc = "Checks if the value of the field is `DIV2048`"] + #[inline(always)] + pub fn is_div2048(&self) -> bool { + **self == PSEL_A::DIV2048 + } + #[doc = "Checks if the value of the field is `DIV4096`"] + #[inline(always)] + pub fn is_div4096(&self) -> bool { + **self == PSEL_A::DIV4096 + } + #[doc = "Checks if the value of the field is `DIV8192`"] + #[inline(always)] + pub fn is_div8192(&self) -> bool { + **self == PSEL_A::DIV8192 + } + #[doc = "Checks if the value of the field is `DIV16384`"] + #[inline(always)] + pub fn is_div16384(&self) -> bool { + **self == PSEL_A::DIV16384 + } + #[doc = "Checks if the value of the field is `DIV32768`"] + #[inline(always)] + pub fn is_div32768(&self) -> bool { + **self == PSEL_A::DIV32768 + } + #[doc = "Checks if the value of the field is `DIV65536`"] + #[inline(always)] + pub fn is_div65536(&self) -> bool { + **self == PSEL_A::DIV65536 + } +} +impl core::ops::Deref for PSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PSEL` writer - Prescaler Select"] +pub struct PSEL_W<'a> { + w: &'a mut W, +} +impl<'a> PSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PSEL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Divide clock by 2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PSEL_A::DIV2) + } + #[doc = "Divide clock by 4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PSEL_A::DIV4) + } + #[doc = "Divide clock by 8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PSEL_A::DIV8) + } + #[doc = "Divide clock by 16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PSEL_A::DIV16) + } + #[doc = "Divide clock by 32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(PSEL_A::DIV32) + } + #[doc = "Divide clock by 64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PSEL_A::DIV64) + } + #[doc = "Divide clock by 128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(PSEL_A::DIV128) + } + #[doc = "Divide clock by 256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PSEL_A::DIV256) + } + #[doc = "Divide clock by 512"] + #[inline(always)] + pub fn div512(self) -> &'a mut W { + self.variant(PSEL_A::DIV512) + } + #[doc = "Divide clock by 1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PSEL_A::DIV1024) + } + #[doc = "Divide clock by 2048"] + #[inline(always)] + pub fn div2048(self) -> &'a mut W { + self.variant(PSEL_A::DIV2048) + } + #[doc = "Divide clock by 4096"] + #[inline(always)] + pub fn div4096(self) -> &'a mut W { + self.variant(PSEL_A::DIV4096) + } + #[doc = "Divide clock by 8192"] + #[inline(always)] + pub fn div8192(self) -> &'a mut W { + self.variant(PSEL_A::DIV8192) + } + #[doc = "Divide clock by 16384"] + #[inline(always)] + pub fn div16384(self) -> &'a mut W { + self.variant(PSEL_A::DIV16384) + } + #[doc = "Divide clock by 32768"] + #[inline(always)] + pub fn div32768(self) -> &'a mut W { + self.variant(PSEL_A::DIV32768) + } + #[doc = "Divide clock by 65536"] + #[inline(always)] + pub fn div65536(self) -> &'a mut W { + self.variant(PSEL_A::DIV65536) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 12)) | ((value as u32 & 0x0f) << 12); + self.w + } +} +#[doc = "Field `LEVEL` reader - Threshold Level for VDD"] +pub struct LEVEL_R(crate::FieldReader); +impl LEVEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LEVEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LEVEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LEVEL` writer - Threshold Level for VDD"] +pub struct LEVEL_W<'a> { + w: &'a mut W, +} +impl<'a> LEVEL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 16)) | ((value as u32 & 0x3f) << 16); + self.w + } +} +impl R { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Hysteresis Enable"] + #[inline(always)] + pub fn hyst(&self) -> HYST_R { + HYST_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 3:4 - Action when Threshold Crossed"] + #[inline(always)] + pub fn action(&self) -> ACTION_R { + ACTION_R::new(((self.bits >> 3) & 0x03) as u8) + } + #[doc = "Bit 5 - Configuration in Standby mode"] + #[inline(always)] + pub fn stdbycfg(&self) -> STDBYCFG_R { + STDBYCFG_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 8 - Configuration in Active mode"] + #[inline(always)] + pub fn actcfg(&self) -> ACTCFG_R { + ACTCFG_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bits 12:15 - Prescaler Select"] + #[inline(always)] + pub fn psel(&self) -> PSEL_R { + PSEL_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:21 - Threshold Level for VDD"] + #[inline(always)] + pub fn level(&self) -> LEVEL_R { + LEVEL_R::new(((self.bits >> 16) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - Hysteresis Enable"] + #[inline(always)] + pub fn hyst(&mut self) -> HYST_W { + HYST_W { w: self } + } + #[doc = "Bits 3:4 - Action when Threshold Crossed"] + #[inline(always)] + pub fn action(&mut self) -> ACTION_W { + ACTION_W { w: self } + } + #[doc = "Bit 5 - Configuration in Standby mode"] + #[inline(always)] + pub fn stdbycfg(&mut self) -> STDBYCFG_W { + STDBYCFG_W { w: self } + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 8 - Configuration in Active mode"] + #[inline(always)] + pub fn actcfg(&mut self) -> ACTCFG_W { + ACTCFG_W { w: self } + } + #[doc = "Bits 12:15 - Prescaler Select"] + #[inline(always)] + pub fn psel(&mut self) -> PSEL_W { + PSEL_W { w: self } + } + #[doc = "Bits 16:21 - Threshold Level for VDD"] + #[inline(always)] + pub fn level(&mut self) -> LEVEL_W { + LEVEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "BODVDD Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [bodvdd](index.html) module"] +pub struct BODVDD_SPEC; +impl crate::RegisterSpec for BODVDD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [bodvdd::R](R) reader structure"] +impl crate::Readable for BODVDD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [bodvdd::W](W) writer structure"] +impl crate::Writable for BODVDD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BODVDD to value 0"] +impl crate::Resettable for BODVDD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/supc/intenclr.rs b/pac/atsamc20j/src/supc/intenclr.rs new file mode 100644 index 000000000000..7b399544fafd --- /dev/null +++ b/pac/atsamc20j/src/supc/intenclr.rs @@ -0,0 +1,348 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BODVDDRDY` reader - BODVDD Ready"] +pub struct BODVDDRDY_R(crate::FieldReader); +impl BODVDDRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODVDDRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODVDDRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODVDDRDY` writer - BODVDD Ready"] +pub struct BODVDDRDY_W<'a> { + w: &'a mut W, +} +impl<'a> BODVDDRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `BODVDDDET` reader - BODVDD Detection"] +pub struct BODVDDDET_R(crate::FieldReader); +impl BODVDDDET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODVDDDET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODVDDDET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODVDDDET` writer - BODVDD Detection"] +pub struct BODVDDDET_W<'a> { + w: &'a mut W, +} +impl<'a> BODVDDDET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `BVDDSRDY` reader - BODVDD Synchronization Ready"] +pub struct BVDDSRDY_R(crate::FieldReader); +impl BVDDSRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BVDDSRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BVDDSRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BVDDSRDY` writer - BODVDD Synchronization Ready"] +pub struct BVDDSRDY_W<'a> { + w: &'a mut W, +} +impl<'a> BVDDSRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `BODCORERDY` reader - BODCORE Ready"] +pub struct BODCORERDY_R(crate::FieldReader); +impl BODCORERDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODCORERDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODCORERDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODCORERDY` writer - BODCORE Ready"] +pub struct BODCORERDY_W<'a> { + w: &'a mut W, +} +impl<'a> BODCORERDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `BODCOREDET` reader - BODCORE Detection"] +pub struct BODCOREDET_R(crate::FieldReader); +impl BODCOREDET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODCOREDET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODCOREDET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODCOREDET` writer - BODCORE Detection"] +pub struct BODCOREDET_W<'a> { + w: &'a mut W, +} +impl<'a> BODCOREDET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `BCORESRDY` reader - BODCORE Synchronization Ready"] +pub struct BCORESRDY_R(crate::FieldReader); +impl BCORESRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BCORESRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BCORESRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BCORESRDY` writer - BODCORE Synchronization Ready"] +pub struct BCORESRDY_W<'a> { + w: &'a mut W, +} +impl<'a> BCORESRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - BODVDD Ready"] + #[inline(always)] + pub fn bodvddrdy(&self) -> BODVDDRDY_R { + BODVDDRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - BODVDD Detection"] + #[inline(always)] + pub fn bodvdddet(&self) -> BODVDDDET_R { + BODVDDDET_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - BODVDD Synchronization Ready"] + #[inline(always)] + pub fn bvddsrdy(&self) -> BVDDSRDY_R { + BVDDSRDY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - BODCORE Ready"] + #[inline(always)] + pub fn bodcorerdy(&self) -> BODCORERDY_R { + BODCORERDY_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - BODCORE Detection"] + #[inline(always)] + pub fn bodcoredet(&self) -> BODCOREDET_R { + BODCOREDET_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - BODCORE Synchronization Ready"] + #[inline(always)] + pub fn bcoresrdy(&self) -> BCORESRDY_R { + BCORESRDY_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - BODVDD Ready"] + #[inline(always)] + pub fn bodvddrdy(&mut self) -> BODVDDRDY_W { + BODVDDRDY_W { w: self } + } + #[doc = "Bit 1 - BODVDD Detection"] + #[inline(always)] + pub fn bodvdddet(&mut self) -> BODVDDDET_W { + BODVDDDET_W { w: self } + } + #[doc = "Bit 2 - BODVDD Synchronization Ready"] + #[inline(always)] + pub fn bvddsrdy(&mut self) -> BVDDSRDY_W { + BVDDSRDY_W { w: self } + } + #[doc = "Bit 3 - BODCORE Ready"] + #[inline(always)] + pub fn bodcorerdy(&mut self) -> BODCORERDY_W { + BODCORERDY_W { w: self } + } + #[doc = "Bit 4 - BODCORE Detection"] + #[inline(always)] + pub fn bodcoredet(&mut self) -> BODCOREDET_W { + BODCOREDET_W { w: self } + } + #[doc = "Bit 5 - BODCORE Synchronization Ready"] + #[inline(always)] + pub fn bcoresrdy(&mut self) -> BCORESRDY_W { + BCORESRDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/supc/intenset.rs b/pac/atsamc20j/src/supc/intenset.rs new file mode 100644 index 000000000000..9e86a6e5b772 --- /dev/null +++ b/pac/atsamc20j/src/supc/intenset.rs @@ -0,0 +1,348 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BODVDDRDY` reader - BODVDD Ready"] +pub struct BODVDDRDY_R(crate::FieldReader); +impl BODVDDRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODVDDRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODVDDRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODVDDRDY` writer - BODVDD Ready"] +pub struct BODVDDRDY_W<'a> { + w: &'a mut W, +} +impl<'a> BODVDDRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `BODVDDDET` reader - BODVDD Detection"] +pub struct BODVDDDET_R(crate::FieldReader); +impl BODVDDDET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODVDDDET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODVDDDET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODVDDDET` writer - BODVDD Detection"] +pub struct BODVDDDET_W<'a> { + w: &'a mut W, +} +impl<'a> BODVDDDET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `BVDDSRDY` reader - BODVDD Synchronization Ready"] +pub struct BVDDSRDY_R(crate::FieldReader); +impl BVDDSRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BVDDSRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BVDDSRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BVDDSRDY` writer - BODVDD Synchronization Ready"] +pub struct BVDDSRDY_W<'a> { + w: &'a mut W, +} +impl<'a> BVDDSRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `BODCORERDY` reader - BODCORE Ready"] +pub struct BODCORERDY_R(crate::FieldReader); +impl BODCORERDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODCORERDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODCORERDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODCORERDY` writer - BODCORE Ready"] +pub struct BODCORERDY_W<'a> { + w: &'a mut W, +} +impl<'a> BODCORERDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `BODCOREDET` reader - BODCORE Detection"] +pub struct BODCOREDET_R(crate::FieldReader); +impl BODCOREDET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODCOREDET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODCOREDET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODCOREDET` writer - BODCORE Detection"] +pub struct BODCOREDET_W<'a> { + w: &'a mut W, +} +impl<'a> BODCOREDET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `BCORESRDY` reader - BODCORE Synchronization Ready"] +pub struct BCORESRDY_R(crate::FieldReader); +impl BCORESRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BCORESRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BCORESRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BCORESRDY` writer - BODCORE Synchronization Ready"] +pub struct BCORESRDY_W<'a> { + w: &'a mut W, +} +impl<'a> BCORESRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - BODVDD Ready"] + #[inline(always)] + pub fn bodvddrdy(&self) -> BODVDDRDY_R { + BODVDDRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - BODVDD Detection"] + #[inline(always)] + pub fn bodvdddet(&self) -> BODVDDDET_R { + BODVDDDET_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - BODVDD Synchronization Ready"] + #[inline(always)] + pub fn bvddsrdy(&self) -> BVDDSRDY_R { + BVDDSRDY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - BODCORE Ready"] + #[inline(always)] + pub fn bodcorerdy(&self) -> BODCORERDY_R { + BODCORERDY_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - BODCORE Detection"] + #[inline(always)] + pub fn bodcoredet(&self) -> BODCOREDET_R { + BODCOREDET_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - BODCORE Synchronization Ready"] + #[inline(always)] + pub fn bcoresrdy(&self) -> BCORESRDY_R { + BCORESRDY_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - BODVDD Ready"] + #[inline(always)] + pub fn bodvddrdy(&mut self) -> BODVDDRDY_W { + BODVDDRDY_W { w: self } + } + #[doc = "Bit 1 - BODVDD Detection"] + #[inline(always)] + pub fn bodvdddet(&mut self) -> BODVDDDET_W { + BODVDDDET_W { w: self } + } + #[doc = "Bit 2 - BODVDD Synchronization Ready"] + #[inline(always)] + pub fn bvddsrdy(&mut self) -> BVDDSRDY_W { + BVDDSRDY_W { w: self } + } + #[doc = "Bit 3 - BODCORE Ready"] + #[inline(always)] + pub fn bodcorerdy(&mut self) -> BODCORERDY_W { + BODCORERDY_W { w: self } + } + #[doc = "Bit 4 - BODCORE Detection"] + #[inline(always)] + pub fn bodcoredet(&mut self) -> BODCOREDET_W { + BODCOREDET_W { w: self } + } + #[doc = "Bit 5 - BODCORE Synchronization Ready"] + #[inline(always)] + pub fn bcoresrdy(&mut self) -> BCORESRDY_W { + BCORESRDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/supc/intflag.rs b/pac/atsamc20j/src/supc/intflag.rs new file mode 100644 index 000000000000..46b4b52add2d --- /dev/null +++ b/pac/atsamc20j/src/supc/intflag.rs @@ -0,0 +1,348 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BODVDDRDY` reader - BODVDD Ready"] +pub struct BODVDDRDY_R(crate::FieldReader); +impl BODVDDRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODVDDRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODVDDRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODVDDRDY` writer - BODVDD Ready"] +pub struct BODVDDRDY_W<'a> { + w: &'a mut W, +} +impl<'a> BODVDDRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `BODVDDDET` reader - BODVDD Detection"] +pub struct BODVDDDET_R(crate::FieldReader); +impl BODVDDDET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODVDDDET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODVDDDET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODVDDDET` writer - BODVDD Detection"] +pub struct BODVDDDET_W<'a> { + w: &'a mut W, +} +impl<'a> BODVDDDET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `BVDDSRDY` reader - BODVDD Synchronization Ready"] +pub struct BVDDSRDY_R(crate::FieldReader); +impl BVDDSRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BVDDSRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BVDDSRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BVDDSRDY` writer - BODVDD Synchronization Ready"] +pub struct BVDDSRDY_W<'a> { + w: &'a mut W, +} +impl<'a> BVDDSRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `BODCORERDY` reader - BODCORE Ready"] +pub struct BODCORERDY_R(crate::FieldReader); +impl BODCORERDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODCORERDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODCORERDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODCORERDY` writer - BODCORE Ready"] +pub struct BODCORERDY_W<'a> { + w: &'a mut W, +} +impl<'a> BODCORERDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `BODCOREDET` reader - BODCORE Detection"] +pub struct BODCOREDET_R(crate::FieldReader); +impl BODCOREDET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODCOREDET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODCOREDET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODCOREDET` writer - BODCORE Detection"] +pub struct BODCOREDET_W<'a> { + w: &'a mut W, +} +impl<'a> BODCOREDET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `BCORESRDY` reader - BODCORE Synchronization Ready"] +pub struct BCORESRDY_R(crate::FieldReader); +impl BCORESRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BCORESRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BCORESRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BCORESRDY` writer - BODCORE Synchronization Ready"] +pub struct BCORESRDY_W<'a> { + w: &'a mut W, +} +impl<'a> BCORESRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - BODVDD Ready"] + #[inline(always)] + pub fn bodvddrdy(&self) -> BODVDDRDY_R { + BODVDDRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - BODVDD Detection"] + #[inline(always)] + pub fn bodvdddet(&self) -> BODVDDDET_R { + BODVDDDET_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - BODVDD Synchronization Ready"] + #[inline(always)] + pub fn bvddsrdy(&self) -> BVDDSRDY_R { + BVDDSRDY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - BODCORE Ready"] + #[inline(always)] + pub fn bodcorerdy(&self) -> BODCORERDY_R { + BODCORERDY_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - BODCORE Detection"] + #[inline(always)] + pub fn bodcoredet(&self) -> BODCOREDET_R { + BODCOREDET_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - BODCORE Synchronization Ready"] + #[inline(always)] + pub fn bcoresrdy(&self) -> BCORESRDY_R { + BCORESRDY_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - BODVDD Ready"] + #[inline(always)] + pub fn bodvddrdy(&mut self) -> BODVDDRDY_W { + BODVDDRDY_W { w: self } + } + #[doc = "Bit 1 - BODVDD Detection"] + #[inline(always)] + pub fn bodvdddet(&mut self) -> BODVDDDET_W { + BODVDDDET_W { w: self } + } + #[doc = "Bit 2 - BODVDD Synchronization Ready"] + #[inline(always)] + pub fn bvddsrdy(&mut self) -> BVDDSRDY_W { + BVDDSRDY_W { w: self } + } + #[doc = "Bit 3 - BODCORE Ready"] + #[inline(always)] + pub fn bodcorerdy(&mut self) -> BODCORERDY_W { + BODCORERDY_W { w: self } + } + #[doc = "Bit 4 - BODCORE Detection"] + #[inline(always)] + pub fn bodcoredet(&mut self) -> BODCOREDET_W { + BODCOREDET_W { w: self } + } + #[doc = "Bit 5 - BODCORE Synchronization Ready"] + #[inline(always)] + pub fn bcoresrdy(&mut self) -> BCORESRDY_W { + BCORESRDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/supc/status.rs b/pac/atsamc20j/src/supc/status.rs new file mode 100644 index 000000000000..0fc1de3635b5 --- /dev/null +++ b/pac/atsamc20j/src/supc/status.rs @@ -0,0 +1,153 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `BODVDDRDY` reader - BODVDD Ready"] +pub struct BODVDDRDY_R(crate::FieldReader); +impl BODVDDRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODVDDRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODVDDRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODVDDDET` reader - BODVDD Detection"] +pub struct BODVDDDET_R(crate::FieldReader); +impl BODVDDDET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODVDDDET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODVDDDET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BVDDSRDY` reader - BODVDD Synchronization Ready"] +pub struct BVDDSRDY_R(crate::FieldReader); +impl BVDDSRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BVDDSRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BVDDSRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODCORERDY` reader - BODCORE Ready"] +pub struct BODCORERDY_R(crate::FieldReader); +impl BODCORERDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODCORERDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODCORERDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODCOREDET` reader - BODCORE Detection"] +pub struct BODCOREDET_R(crate::FieldReader); +impl BODCOREDET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODCOREDET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODCOREDET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BCORESRDY` reader - BODCORE Synchronization Ready"] +pub struct BCORESRDY_R(crate::FieldReader); +impl BCORESRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BCORESRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BCORESRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - BODVDD Ready"] + #[inline(always)] + pub fn bodvddrdy(&self) -> BODVDDRDY_R { + BODVDDRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - BODVDD Detection"] + #[inline(always)] + pub fn bodvdddet(&self) -> BODVDDDET_R { + BODVDDDET_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - BODVDD Synchronization Ready"] + #[inline(always)] + pub fn bvddsrdy(&self) -> BVDDSRDY_R { + BVDDSRDY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - BODCORE Ready"] + #[inline(always)] + pub fn bodcorerdy(&self) -> BODCORERDY_R { + BODCORERDY_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - BODCORE Detection"] + #[inline(always)] + pub fn bodcoredet(&self) -> BODCOREDET_R { + BODCOREDET_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - BODCORE Synchronization Ready"] + #[inline(always)] + pub fn bcoresrdy(&self) -> BCORESRDY_R { + BCORESRDY_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +#[doc = "Power and Clocks Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/supc/vref.rs b/pac/atsamc20j/src/supc/vref.rs new file mode 100644 index 000000000000..2d5b1381885e --- /dev/null +++ b/pac/atsamc20j/src/supc/vref.rs @@ -0,0 +1,353 @@ +#[doc = "Register `VREF` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `VREF` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TSEN` reader - Temperature Sensor Output Enable"] +pub struct TSEN_R(crate::FieldReader); +impl TSEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSEN` writer - Temperature Sensor Output Enable"] +pub struct TSEN_W<'a> { + w: &'a mut W, +} +impl<'a> TSEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `VREFOE` reader - Voltage Reference Output Enable"] +pub struct VREFOE_R(crate::FieldReader); +impl VREFOE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + VREFOE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VREFOE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VREFOE` writer - Voltage Reference Output Enable"] +pub struct VREFOE_W<'a> { + w: &'a mut W, +} +impl<'a> VREFOE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - On Demand Contrl"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - On Demand Contrl"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Voltage Reference Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SEL_A { + #[doc = "0: 1.024V voltage reference typical value"] + _1V024 = 0, + #[doc = "2: 2.048V voltage reference typical value"] + _2V048 = 2, + #[doc = "3: 4.096V voltage reference typical value"] + _4V096 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `SEL` reader - Voltage Reference Selection"] +pub struct SEL_R(crate::FieldReader); +impl SEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEL_A::_1V024), + 2 => Some(SEL_A::_2V048), + 3 => Some(SEL_A::_4V096), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_1V024`"] + #[inline(always)] + pub fn is_1v024(&self) -> bool { + **self == SEL_A::_1V024 + } + #[doc = "Checks if the value of the field is `_2V048`"] + #[inline(always)] + pub fn is_2v048(&self) -> bool { + **self == SEL_A::_2V048 + } + #[doc = "Checks if the value of the field is `_4V096`"] + #[inline(always)] + pub fn is_4v096(&self) -> bool { + **self == SEL_A::_4V096 + } +} +impl core::ops::Deref for SEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEL` writer - Voltage Reference Selection"] +pub struct SEL_W<'a> { + w: &'a mut W, +} +impl<'a> SEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SEL_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "1.024V voltage reference typical value"] + #[inline(always)] + pub fn _1v024(self) -> &'a mut W { + self.variant(SEL_A::_1V024) + } + #[doc = "2.048V voltage reference typical value"] + #[inline(always)] + pub fn _2v048(self) -> &'a mut W { + self.variant(SEL_A::_2V048) + } + #[doc = "4.096V voltage reference typical value"] + #[inline(always)] + pub fn _4v096(self) -> &'a mut W { + self.variant(SEL_A::_4V096) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 16)) | ((value as u32 & 0x0f) << 16); + self.w + } +} +impl R { + #[doc = "Bit 1 - Temperature Sensor Output Enable"] + #[inline(always)] + pub fn tsen(&self) -> TSEN_R { + TSEN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Voltage Reference Output Enable"] + #[inline(always)] + pub fn vrefoe(&self) -> VREFOE_R { + VREFOE_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - On Demand Contrl"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 16:19 - Voltage Reference Selection"] + #[inline(always)] + pub fn sel(&self) -> SEL_R { + SEL_R::new(((self.bits >> 16) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bit 1 - Temperature Sensor Output Enable"] + #[inline(always)] + pub fn tsen(&mut self) -> TSEN_W { + TSEN_W { w: self } + } + #[doc = "Bit 2 - Voltage Reference Output Enable"] + #[inline(always)] + pub fn vrefoe(&mut self) -> VREFOE_W { + VREFOE_W { w: self } + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - On Demand Contrl"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Bits 16:19 - Voltage Reference Selection"] + #[inline(always)] + pub fn sel(&mut self) -> SEL_W { + SEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "VREF Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [vref](index.html) module"] +pub struct VREF_SPEC; +impl crate::RegisterSpec for VREF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [vref::R](R) reader structure"] +impl crate::Readable for VREF_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [vref::W](W) writer structure"] +impl crate::Writable for VREF_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets VREF to value 0"] +impl crate::Resettable for VREF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/supc/vreg.rs b/pac/atsamc20j/src/supc/vreg.rs new file mode 100644 index 000000000000..fb5b12a185cf --- /dev/null +++ b/pac/atsamc20j/src/supc/vreg.rs @@ -0,0 +1,160 @@ +#[doc = "Register `VREG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `VREG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "VREG Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [vreg](index.html) module"] +pub struct VREG_SPEC; +impl crate::RegisterSpec for VREG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [vreg::R](R) reader structure"] +impl crate::Readable for VREG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [vreg::W](W) writer structure"] +impl crate::Writable for VREG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets VREG to value 0"] +impl crate::Resettable for VREG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/sys_tick.rs b/pac/atsamc20j/src/sys_tick.rs new file mode 100644 index 000000000000..b0fe7a59e5ed --- /dev/null +++ b/pac/atsamc20j/src/sys_tick.rs @@ -0,0 +1,28 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - SysTick Control and Status Register"] + pub csr: crate::Reg, + #[doc = "0x04 - SysTick Reload Value Register"] + pub rvr: crate::Reg, + #[doc = "0x08 - SysTick Current Value Register"] + pub cvr: crate::Reg, + #[doc = "0x0c - SysTick Calibration Value Register"] + pub calib: crate::Reg, +} +#[doc = "CSR register accessor: an alias for `Reg`"] +pub type CSR = crate::Reg; +#[doc = "SysTick Control and Status Register"] +pub mod csr; +#[doc = "RVR register accessor: an alias for `Reg`"] +pub type RVR = crate::Reg; +#[doc = "SysTick Reload Value Register"] +pub mod rvr; +#[doc = "CVR register accessor: an alias for `Reg`"] +pub type CVR = crate::Reg; +#[doc = "SysTick Current Value Register"] +pub mod cvr; +#[doc = "CALIB register accessor: an alias for `Reg`"] +pub type CALIB = crate::Reg; +#[doc = "SysTick Calibration Value Register"] +pub mod calib; diff --git a/pac/atsamc20j/src/sys_tick/calib.rs b/pac/atsamc20j/src/sys_tick/calib.rs new file mode 100644 index 000000000000..df7fd80f773a --- /dev/null +++ b/pac/atsamc20j/src/sys_tick/calib.rs @@ -0,0 +1,157 @@ +#[doc = "Register `CALIB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `TENMS` reader - Reload value to use for 10ms timing"] +pub struct TENMS_R(crate::FieldReader); +impl TENMS_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + TENMS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TENMS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "TENMS is rounded from non-integer ratio\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SKEW_A { + #[doc = "0: 10ms calibration value is exact"] + VALUE_0 = 0, + #[doc = "1: 10ms calibration value is inexact, because of the clock frequency"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SKEW_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SKEW` reader - TENMS is rounded from non-integer ratio"] +pub struct SKEW_R(crate::FieldReader); +impl SKEW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SKEW_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SKEW_A { + match self.bits { + false => SKEW_A::VALUE_0, + true => SKEW_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == SKEW_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == SKEW_A::VALUE_1 + } +} +impl core::ops::Deref for SKEW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "No Separate Reference Clock\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum NOREF_A { + #[doc = "0: The reference clock is provided"] + VALUE_0 = 0, + #[doc = "1: The reference clock is not provided"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NOREF_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NOREF` reader - No Separate Reference Clock"] +pub struct NOREF_R(crate::FieldReader); +impl NOREF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NOREF_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> NOREF_A { + match self.bits { + false => NOREF_A::VALUE_0, + true => NOREF_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == NOREF_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == NOREF_A::VALUE_1 + } +} +impl core::ops::Deref for NOREF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:23 - Reload value to use for 10ms timing"] + #[inline(always)] + pub fn tenms(&self) -> TENMS_R { + TENMS_R::new((self.bits & 0x00ff_ffff) as u32) + } + #[doc = "Bit 30 - TENMS is rounded from non-integer ratio"] + #[inline(always)] + pub fn skew(&self) -> SKEW_R { + SKEW_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 31 - No Separate Reference Clock"] + #[inline(always)] + pub fn noref(&self) -> NOREF_R { + NOREF_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +#[doc = "SysTick Calibration Value Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [calib](index.html) module"] +pub struct CALIB_SPEC; +impl crate::RegisterSpec for CALIB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [calib::R](R) reader structure"] +impl crate::Readable for CALIB_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CALIB to value 0"] +impl crate::Resettable for CALIB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/sys_tick/csr.rs b/pac/atsamc20j/src/sys_tick/csr.rs new file mode 100644 index 000000000000..872d637f5a86 --- /dev/null +++ b/pac/atsamc20j/src/sys_tick/csr.rs @@ -0,0 +1,395 @@ +#[doc = "Register `CSR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CSR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "SysTick Counter Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ENABLE_A { + #[doc = "0: Counter disabled"] + VALUE_0 = 0, + #[doc = "1: Counter enabled"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ENABLE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ENABLE` reader - SysTick Counter Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ENABLE_A { + match self.bits { + false => ENABLE_A::VALUE_0, + true => ENABLE_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == ENABLE_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == ENABLE_A::VALUE_1 + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - SysTick Counter Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: ENABLE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Counter disabled"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(ENABLE_A::VALUE_0) + } + #[doc = "Counter enabled"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(ENABLE_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "SysTick Exception Request Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TICKINT_A { + #[doc = "0: Counting down to 0 does not assert the SysTick exception request"] + VALUE_0 = 0, + #[doc = "1: Counting down to 0 asserts the SysTick exception request"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TICKINT_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TICKINT` reader - SysTick Exception Request Enable"] +pub struct TICKINT_R(crate::FieldReader); +impl TICKINT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TICKINT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TICKINT_A { + match self.bits { + false => TICKINT_A::VALUE_0, + true => TICKINT_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == TICKINT_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == TICKINT_A::VALUE_1 + } +} +impl core::ops::Deref for TICKINT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TICKINT` writer - SysTick Exception Request Enable"] +pub struct TICKINT_W<'a> { + w: &'a mut W, +} +impl<'a> TICKINT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TICKINT_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Counting down to 0 does not assert the SysTick exception request"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(TICKINT_A::VALUE_0) + } + #[doc = "Counting down to 0 asserts the SysTick exception request"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(TICKINT_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Clock Source 0=external, 1=processor\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CLKSOURCE_A { + #[doc = "0: External clock"] + VALUE_0 = 0, + #[doc = "1: Processor clock"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CLKSOURCE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CLKSOURCE` reader - Clock Source 0=external, 1=processor"] +pub struct CLKSOURCE_R(crate::FieldReader); +impl CLKSOURCE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKSOURCE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CLKSOURCE_A { + match self.bits { + false => CLKSOURCE_A::VALUE_0, + true => CLKSOURCE_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == CLKSOURCE_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == CLKSOURCE_A::VALUE_1 + } +} +impl core::ops::Deref for CLKSOURCE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKSOURCE` writer - Clock Source 0=external, 1=processor"] +pub struct CLKSOURCE_W<'a> { + w: &'a mut W, +} +impl<'a> CLKSOURCE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CLKSOURCE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "External clock"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(CLKSOURCE_A::VALUE_0) + } + #[doc = "Processor clock"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(CLKSOURCE_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `COUNTFLAG` reader - Timer counted to 0 since last read of register"] +pub struct COUNTFLAG_R(crate::FieldReader); +impl COUNTFLAG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNTFLAG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNTFLAG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNTFLAG` writer - Timer counted to 0 since last read of register"] +pub struct COUNTFLAG_W<'a> { + w: &'a mut W, +} +impl<'a> COUNTFLAG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +impl R { + #[doc = "Bit 0 - SysTick Counter Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SysTick Exception Request Enable"] + #[inline(always)] + pub fn tickint(&self) -> TICKINT_R { + TICKINT_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Clock Source 0=external, 1=processor"] + #[inline(always)] + pub fn clksource(&self) -> CLKSOURCE_R { + CLKSOURCE_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 16 - Timer counted to 0 since last read of register"] + #[inline(always)] + pub fn countflag(&self) -> COUNTFLAG_R { + COUNTFLAG_R::new(((self.bits >> 16) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - SysTick Counter Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 1 - SysTick Exception Request Enable"] + #[inline(always)] + pub fn tickint(&mut self) -> TICKINT_W { + TICKINT_W { w: self } + } + #[doc = "Bit 2 - Clock Source 0=external, 1=processor"] + #[inline(always)] + pub fn clksource(&mut self) -> CLKSOURCE_W { + CLKSOURCE_W { w: self } + } + #[doc = "Bit 16 - Timer counted to 0 since last read of register"] + #[inline(always)] + pub fn countflag(&mut self) -> COUNTFLAG_W { + COUNTFLAG_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SysTick Control and Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [csr](index.html) module"] +pub struct CSR_SPEC; +impl crate::RegisterSpec for CSR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [csr::R](R) reader structure"] +impl crate::Readable for CSR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [csr::W](W) writer structure"] +impl crate::Writable for CSR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CSR to value 0x04"] +impl crate::Resettable for CSR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x04 + } +} diff --git a/pac/atsamc20j/src/sys_tick/cvr.rs b/pac/atsamc20j/src/sys_tick/cvr.rs new file mode 100644 index 000000000000..8a40b5f43b3a --- /dev/null +++ b/pac/atsamc20j/src/sys_tick/cvr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `CVR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CVR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CURRENT` reader - Current value at the time the register is accessed"] +pub struct CURRENT_R(crate::FieldReader); +impl CURRENT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CURRENT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CURRENT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CURRENT` writer - Current value at the time the register is accessed"] +pub struct CURRENT_W<'a> { + w: &'a mut W, +} +impl<'a> CURRENT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Current value at the time the register is accessed"] + #[inline(always)] + pub fn current(&self) -> CURRENT_R { + CURRENT_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Current value at the time the register is accessed"] + #[inline(always)] + pub fn current(&mut self) -> CURRENT_W { + CURRENT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SysTick Current Value Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cvr](index.html) module"] +pub struct CVR_SPEC; +impl crate::RegisterSpec for CVR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cvr::R](R) reader structure"] +impl crate::Readable for CVR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cvr::W](W) writer structure"] +impl crate::Writable for CVR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CVR to value 0"] +impl crate::Resettable for CVR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/sys_tick/rvr.rs b/pac/atsamc20j/src/sys_tick/rvr.rs new file mode 100644 index 000000000000..ac023ff75f36 --- /dev/null +++ b/pac/atsamc20j/src/sys_tick/rvr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `RVR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RVR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RELOAD` reader - Value to load into the SysTick Current Value Register when the counter reaches 0"] +pub struct RELOAD_R(crate::FieldReader); +impl RELOAD_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + RELOAD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RELOAD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RELOAD` writer - Value to load into the SysTick Current Value Register when the counter reaches 0"] +pub struct RELOAD_W<'a> { + w: &'a mut W, +} +impl<'a> RELOAD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Value to load into the SysTick Current Value Register when the counter reaches 0"] + #[inline(always)] + pub fn reload(&self) -> RELOAD_R { + RELOAD_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Value to load into the SysTick Current Value Register when the counter reaches 0"] + #[inline(always)] + pub fn reload(&mut self) -> RELOAD_W { + RELOAD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SysTick Reload Value Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rvr](index.html) module"] +pub struct RVR_SPEC; +impl crate::RegisterSpec for RVR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rvr::R](R) reader structure"] +impl crate::Readable for RVR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rvr::W](W) writer structure"] +impl crate::Writable for RVR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RVR to value 0"] +impl crate::Resettable for RVR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/system_control.rs b/pac/atsamc20j/src/system_control.rs new file mode 100644 index 000000000000..4894b22b258f --- /dev/null +++ b/pac/atsamc20j/src/system_control.rs @@ -0,0 +1,67 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved0: [u8; 0x0d00], + #[doc = "0xd00 - CPUID Base Register"] + pub cpuid: crate::Reg, + #[doc = "0xd04 - Interrupt Control and State Register"] + pub icsr: crate::Reg, + #[doc = "0xd08 - Vector Table Offset Register"] + pub vtor: crate::Reg, + #[doc = "0xd0c - Application Interrupt and Reset Control Register"] + pub aircr: crate::Reg, + #[doc = "0xd10 - System Control Register"] + pub scr: crate::Reg, + #[doc = "0xd14 - Configuration and Control Register"] + pub ccr: crate::Reg, + _reserved6: [u8; 0x04], + #[doc = "0xd1c - System Handler Priority Register 2"] + pub shpr2: crate::Reg, + #[doc = "0xd20 - System Handler Priority Register 3"] + pub shpr3: crate::Reg, + #[doc = "0xd24 - System Handler Control and State Register"] + pub shcsr: crate::Reg, + _reserved9: [u8; 0x08], + #[doc = "0xd30 - Debug Fault Status Register"] + pub dfsr: crate::Reg, +} +#[doc = "CPUID register accessor: an alias for `Reg`"] +pub type CPUID = crate::Reg; +#[doc = "CPUID Base Register"] +pub mod cpuid; +#[doc = "ICSR register accessor: an alias for `Reg`"] +pub type ICSR = crate::Reg; +#[doc = "Interrupt Control and State Register"] +pub mod icsr; +#[doc = "VTOR register accessor: an alias for `Reg`"] +pub type VTOR = crate::Reg; +#[doc = "Vector Table Offset Register"] +pub mod vtor; +#[doc = "AIRCR register accessor: an alias for `Reg`"] +pub type AIRCR = crate::Reg; +#[doc = "Application Interrupt and Reset Control Register"] +pub mod aircr; +#[doc = "SCR register accessor: an alias for `Reg`"] +pub type SCR = crate::Reg; +#[doc = "System Control Register"] +pub mod scr; +#[doc = "CCR register accessor: an alias for `Reg`"] +pub type CCR = crate::Reg; +#[doc = "Configuration and Control Register"] +pub mod ccr; +#[doc = "SHPR2 register accessor: an alias for `Reg`"] +pub type SHPR2 = crate::Reg; +#[doc = "System Handler Priority Register 2"] +pub mod shpr2; +#[doc = "SHPR3 register accessor: an alias for `Reg`"] +pub type SHPR3 = crate::Reg; +#[doc = "System Handler Priority Register 3"] +pub mod shpr3; +#[doc = "SHCSR register accessor: an alias for `Reg`"] +pub type SHCSR = crate::Reg; +#[doc = "System Handler Control and State Register"] +pub mod shcsr; +#[doc = "DFSR register accessor: an alias for `Reg`"] +pub type DFSR = crate::Reg; +#[doc = "Debug Fault Status Register"] +pub mod dfsr; diff --git a/pac/atsamc20j/src/system_control/aircr.rs b/pac/atsamc20j/src/system_control/aircr.rs new file mode 100644 index 000000000000..9453cc6f30bc --- /dev/null +++ b/pac/atsamc20j/src/system_control/aircr.rs @@ -0,0 +1,338 @@ +#[doc = "Register `AIRCR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `AIRCR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `VECTCLRACTIVE` reader - Debug: Clear state information"] +pub struct VECTCLRACTIVE_R(crate::FieldReader); +impl VECTCLRACTIVE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + VECTCLRACTIVE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VECTCLRACTIVE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VECTCLRACTIVE` writer - Debug: Clear state information"] +pub struct VECTCLRACTIVE_W<'a> { + w: &'a mut W, +} +impl<'a> VECTCLRACTIVE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "System Reset Request\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SYSRESETREQ_A { + #[doc = "0: No system reset request"] + VALUE_0 = 0, + #[doc = "1: Asserts a signal to the outer system that requests a reset"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SYSRESETREQ_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SYSRESETREQ` reader - System Reset Request"] +pub struct SYSRESETREQ_R(crate::FieldReader); +impl SYSRESETREQ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYSRESETREQ_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SYSRESETREQ_A { + match self.bits { + false => SYSRESETREQ_A::VALUE_0, + true => SYSRESETREQ_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == SYSRESETREQ_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == SYSRESETREQ_A::VALUE_1 + } +} +impl core::ops::Deref for SYSRESETREQ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYSRESETREQ` writer - System Reset Request"] +pub struct SYSRESETREQ_W<'a> { + w: &'a mut W, +} +impl<'a> SYSRESETREQ_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SYSRESETREQ_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "No system reset request"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(SYSRESETREQ_A::VALUE_0) + } + #[doc = "Asserts a signal to the outer system that requests a reset"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(SYSRESETREQ_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Data Endianness, 0=little, 1=big\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ENDIANNESS_A { + #[doc = "0: Little-endian"] + VALUE_0 = 0, + #[doc = "1: Big-endian"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ENDIANNESS_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ENDIANNESS` reader - Data Endianness, 0=little, 1=big"] +pub struct ENDIANNESS_R(crate::FieldReader); +impl ENDIANNESS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENDIANNESS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ENDIANNESS_A { + match self.bits { + false => ENDIANNESS_A::VALUE_0, + true => ENDIANNESS_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == ENDIANNESS_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == ENDIANNESS_A::VALUE_1 + } +} +impl core::ops::Deref for ENDIANNESS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENDIANNESS` writer - Data Endianness, 0=little, 1=big"] +pub struct ENDIANNESS_W<'a> { + w: &'a mut W, +} +impl<'a> ENDIANNESS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: ENDIANNESS_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Little-endian"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(ENDIANNESS_A::VALUE_0) + } + #[doc = "Big-endian"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(ENDIANNESS_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `VECTKEY` reader - Register key (0x05FA)"] +pub struct VECTKEY_R(crate::FieldReader); +impl VECTKEY_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + VECTKEY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VECTKEY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VECTKEY` writer - Register key (0x05FA)"] +pub struct VECTKEY_W<'a> { + w: &'a mut W, +} +impl<'a> VECTKEY_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xffff << 16)) | ((value as u32 & 0xffff) << 16); + self.w + } +} +impl R { + #[doc = "Bit 1 - Debug: Clear state information"] + #[inline(always)] + pub fn vectclractive(&self) -> VECTCLRACTIVE_R { + VECTCLRACTIVE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - System Reset Request"] + #[inline(always)] + pub fn sysresetreq(&self) -> SYSRESETREQ_R { + SYSRESETREQ_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 15 - Data Endianness, 0=little, 1=big"] + #[inline(always)] + pub fn endianness(&self) -> ENDIANNESS_R { + ENDIANNESS_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:31 - Register key (0x05FA)"] + #[inline(always)] + pub fn vectkey(&self) -> VECTKEY_R { + VECTKEY_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bit 1 - Debug: Clear state information"] + #[inline(always)] + pub fn vectclractive(&mut self) -> VECTCLRACTIVE_W { + VECTCLRACTIVE_W { w: self } + } + #[doc = "Bit 2 - System Reset Request"] + #[inline(always)] + pub fn sysresetreq(&mut self) -> SYSRESETREQ_W { + SYSRESETREQ_W { w: self } + } + #[doc = "Bit 15 - Data Endianness, 0=little, 1=big"] + #[inline(always)] + pub fn endianness(&mut self) -> ENDIANNESS_W { + ENDIANNESS_W { w: self } + } + #[doc = "Bits 16:31 - Register key (0x05FA)"] + #[inline(always)] + pub fn vectkey(&mut self) -> VECTKEY_W { + VECTKEY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Application Interrupt and Reset Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [aircr](index.html) module"] +pub struct AIRCR_SPEC; +impl crate::RegisterSpec for AIRCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [aircr::R](R) reader structure"] +impl crate::Readable for AIRCR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [aircr::W](W) writer structure"] +impl crate::Writable for AIRCR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets AIRCR to value 0"] +impl crate::Resettable for AIRCR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/system_control/ccr.rs b/pac/atsamc20j/src/system_control/ccr.rs new file mode 100644 index 000000000000..62516a7b60c8 --- /dev/null +++ b/pac/atsamc20j/src/system_control/ccr.rs @@ -0,0 +1,137 @@ +#[doc = "Register `CCR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Unaligned accesses generates a Hard Fault\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum UNALIGN_TRP_A { + #[doc = "0: Do not trap unaligned halfword and word accesses"] + VALUE_0 = 0, + #[doc = "1: Trap unaligned halfword and word accesses"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: UNALIGN_TRP_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `UNALIGN_TRP` reader - Unaligned accesses generates a Hard Fault"] +pub struct UNALIGN_TRP_R(crate::FieldReader); +impl UNALIGN_TRP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UNALIGN_TRP_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> UNALIGN_TRP_A { + match self.bits { + false => UNALIGN_TRP_A::VALUE_0, + true => UNALIGN_TRP_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == UNALIGN_TRP_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == UNALIGN_TRP_A::VALUE_1 + } +} +impl core::ops::Deref for UNALIGN_TRP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Stack 8-byte aligned on exception entry\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum STKALIGN_A { + #[doc = "0: 4-byte aligned"] + VALUE_0 = 0, + #[doc = "1: 8-byte aligned"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: STKALIGN_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STKALIGN` reader - Stack 8-byte aligned on exception entry"] +pub struct STKALIGN_R(crate::FieldReader); +impl STKALIGN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STKALIGN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STKALIGN_A { + match self.bits { + false => STKALIGN_A::VALUE_0, + true => STKALIGN_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == STKALIGN_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == STKALIGN_A::VALUE_1 + } +} +impl core::ops::Deref for STKALIGN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 3 - Unaligned accesses generates a Hard Fault"] + #[inline(always)] + pub fn unalign_trp(&self) -> UNALIGN_TRP_R { + UNALIGN_TRP_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 9 - Stack 8-byte aligned on exception entry"] + #[inline(always)] + pub fn stkalign(&self) -> STKALIGN_R { + STKALIGN_R::new(((self.bits >> 9) & 0x01) != 0) + } +} +#[doc = "Configuration and Control Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccr](index.html) module"] +pub struct CCR_SPEC; +impl crate::RegisterSpec for CCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ccr::R](R) reader structure"] +impl crate::Readable for CCR_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CCR to value 0x0204"] +impl crate::Resettable for CCR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0204 + } +} diff --git a/pac/atsamc20j/src/system_control/cpuid.rs b/pac/atsamc20j/src/system_control/cpuid.rs new file mode 100644 index 000000000000..4157d7a94e97 --- /dev/null +++ b/pac/atsamc20j/src/system_control/cpuid.rs @@ -0,0 +1,133 @@ +#[doc = "Register `CPUID` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `REVISION` reader - Minor revision number"] +pub struct REVISION_R(crate::FieldReader); +impl REVISION_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REVISION_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REVISION_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PARTNO` reader - Processor Part Number, 0xC60=Cortex-M0+"] +pub struct PARTNO_R(crate::FieldReader); +impl PARTNO_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + PARTNO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PARTNO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ARCHITECTURE` reader - Processor Architecture, 0xC=ARMv6-M"] +pub struct ARCHITECTURE_R(crate::FieldReader); +impl ARCHITECTURE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ARCHITECTURE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ARCHITECTURE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VARIANT` reader - Major revision number"] +pub struct VARIANT_R(crate::FieldReader); +impl VARIANT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + VARIANT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VARIANT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IMPLEMENTER` reader - Implementer code, ARM=0x41"] +pub struct IMPLEMENTER_R(crate::FieldReader); +impl IMPLEMENTER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + IMPLEMENTER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IMPLEMENTER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:3 - Minor revision number"] + #[inline(always)] + pub fn revision(&self) -> REVISION_R { + REVISION_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:15 - Processor Part Number, 0xC60=Cortex-M0+"] + #[inline(always)] + pub fn partno(&self) -> PARTNO_R { + PARTNO_R::new(((self.bits >> 4) & 0x0fff) as u16) + } + #[doc = "Bits 16:19 - Processor Architecture, 0xC=ARMv6-M"] + #[inline(always)] + pub fn architecture(&self) -> ARCHITECTURE_R { + ARCHITECTURE_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bits 20:23 - Major revision number"] + #[inline(always)] + pub fn variant(&self) -> VARIANT_R { + VARIANT_R::new(((self.bits >> 20) & 0x0f) as u8) + } + #[doc = "Bits 24:31 - Implementer code, ARM=0x41"] + #[inline(always)] + pub fn implementer(&self) -> IMPLEMENTER_R { + IMPLEMENTER_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[doc = "CPUID Base Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cpuid](index.html) module"] +pub struct CPUID_SPEC; +impl crate::RegisterSpec for CPUID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cpuid::R](R) reader structure"] +impl crate::Readable for CPUID_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CPUID to value 0x410c_c601"] +impl crate::Resettable for CPUID_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x410c_c601 + } +} diff --git a/pac/atsamc20j/src/system_control/dfsr.rs b/pac/atsamc20j/src/system_control/dfsr.rs new file mode 100644 index 000000000000..948899af0905 --- /dev/null +++ b/pac/atsamc20j/src/system_control/dfsr.rs @@ -0,0 +1,301 @@ +#[doc = "Register `DFSR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DFSR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `HALTED` reader - Halt request debug event active"] +pub struct HALTED_R(crate::FieldReader); +impl HALTED_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HALTED_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HALTED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HALTED` writer - Halt request debug event active"] +pub struct HALTED_W<'a> { + w: &'a mut W, +} +impl<'a> HALTED_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `BKPT` reader - Breakpoint debug event"] +pub struct BKPT_R(crate::FieldReader); +impl BKPT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BKPT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BKPT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BKPT` writer - Breakpoint debug event"] +pub struct BKPT_W<'a> { + w: &'a mut W, +} +impl<'a> BKPT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `DWTTRAP` reader - DWT debug event"] +pub struct DWTTRAP_R(crate::FieldReader); +impl DWTTRAP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DWTTRAP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DWTTRAP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DWTTRAP` writer - DWT debug event"] +pub struct DWTTRAP_W<'a> { + w: &'a mut W, +} +impl<'a> DWTTRAP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `VCATCH` reader - Vector catch debug event"] +pub struct VCATCH_R(crate::FieldReader); +impl VCATCH_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + VCATCH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VCATCH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VCATCH` writer - Vector catch debug event"] +pub struct VCATCH_W<'a> { + w: &'a mut W, +} +impl<'a> VCATCH_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `EXTERNAL` reader - EDBGRQ debug event"] +pub struct EXTERNAL_R(crate::FieldReader); +impl EXTERNAL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTERNAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTERNAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTERNAL` writer - EDBGRQ debug event"] +pub struct EXTERNAL_W<'a> { + w: &'a mut W, +} +impl<'a> EXTERNAL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +impl R { + #[doc = "Bit 0 - Halt request debug event active"] + #[inline(always)] + pub fn halted(&self) -> HALTED_R { + HALTED_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Breakpoint debug event"] + #[inline(always)] + pub fn bkpt(&self) -> BKPT_R { + BKPT_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - DWT debug event"] + #[inline(always)] + pub fn dwttrap(&self) -> DWTTRAP_R { + DWTTRAP_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Vector catch debug event"] + #[inline(always)] + pub fn vcatch(&self) -> VCATCH_R { + VCATCH_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - EDBGRQ debug event"] + #[inline(always)] + pub fn external(&self) -> EXTERNAL_R { + EXTERNAL_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Halt request debug event active"] + #[inline(always)] + pub fn halted(&mut self) -> HALTED_W { + HALTED_W { w: self } + } + #[doc = "Bit 1 - Breakpoint debug event"] + #[inline(always)] + pub fn bkpt(&mut self) -> BKPT_W { + BKPT_W { w: self } + } + #[doc = "Bit 2 - DWT debug event"] + #[inline(always)] + pub fn dwttrap(&mut self) -> DWTTRAP_W { + DWTTRAP_W { w: self } + } + #[doc = "Bit 3 - Vector catch debug event"] + #[inline(always)] + pub fn vcatch(&mut self) -> VCATCH_W { + VCATCH_W { w: self } + } + #[doc = "Bit 4 - EDBGRQ debug event"] + #[inline(always)] + pub fn external(&mut self) -> EXTERNAL_W { + EXTERNAL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Fault Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dfsr](index.html) module"] +pub struct DFSR_SPEC; +impl crate::RegisterSpec for DFSR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dfsr::R](R) reader structure"] +impl crate::Readable for DFSR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dfsr::W](W) writer structure"] +impl crate::Writable for DFSR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DFSR to value 0"] +impl crate::Resettable for DFSR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/system_control/icsr.rs b/pac/atsamc20j/src/system_control/icsr.rs new file mode 100644 index 000000000000..7fe5fd412116 --- /dev/null +++ b/pac/atsamc20j/src/system_control/icsr.rs @@ -0,0 +1,704 @@ +#[doc = "Register `ICSR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ICSR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `VECTACTIVE` reader - Debug: Exception number of currently executing exception, or 0 if thread mode"] +pub struct VECTACTIVE_R(crate::FieldReader); +impl VECTACTIVE_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + VECTACTIVE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VECTACTIVE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VECTACTIVE` writer - Debug: Exception number of currently executing exception, or 0 if thread mode"] +pub struct VECTACTIVE_W<'a> { + w: &'a mut W, +} +impl<'a> VECTACTIVE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01ff) | (value as u32 & 0x01ff); + self.w + } +} +#[doc = "Field `VECTPENDING` reader - Exception number of the highest priority pending enabled exception"] +pub struct VECTPENDING_R(crate::FieldReader); +impl VECTPENDING_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + VECTPENDING_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VECTPENDING_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VECTPENDING` writer - Exception number of the highest priority pending enabled exception"] +pub struct VECTPENDING_W<'a> { + w: &'a mut W, +} +impl<'a> VECTPENDING_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01ff << 12)) | ((value as u32 & 0x01ff) << 12); + self.w + } +} +#[doc = "Field `ISRPENDING` reader - Debug: NVIC interrupt pending"] +pub struct ISRPENDING_R(crate::FieldReader); +impl ISRPENDING_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ISRPENDING_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ISRPENDING_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ISRPENDING` writer - Debug: NVIC interrupt pending"] +pub struct ISRPENDING_W<'a> { + w: &'a mut W, +} +impl<'a> ISRPENDING_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `ISRPREEMPT` reader - Debug: Pending exception serviced on exit from debug halt"] +pub struct ISRPREEMPT_R(crate::FieldReader); +impl ISRPREEMPT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ISRPREEMPT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ISRPREEMPT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ISRPREEMPT` writer - Debug: Pending exception serviced on exit from debug halt"] +pub struct ISRPREEMPT_W<'a> { + w: &'a mut W, +} +impl<'a> ISRPREEMPT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "SysTick exception clear-pending bit\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PENDSTCLR_A { + #[doc = "0: No effect"] + VALUE_0 = 0, + #[doc = "1: Removes the pending state from the SysTick exception"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PENDSTCLR_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PENDSTCLR` reader - SysTick exception clear-pending bit"] +pub struct PENDSTCLR_R(crate::FieldReader); +impl PENDSTCLR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDSTCLR_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PENDSTCLR_A { + match self.bits { + false => PENDSTCLR_A::VALUE_0, + true => PENDSTCLR_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == PENDSTCLR_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == PENDSTCLR_A::VALUE_1 + } +} +impl core::ops::Deref for PENDSTCLR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDSTCLR` writer - SysTick exception clear-pending bit"] +pub struct PENDSTCLR_W<'a> { + w: &'a mut W, +} +impl<'a> PENDSTCLR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PENDSTCLR_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "No effect"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(PENDSTCLR_A::VALUE_0) + } + #[doc = "Removes the pending state from the SysTick exception"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(PENDSTCLR_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "SysTick exception set-pending bit\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PENDSTSET_A { + #[doc = "0: Write: no effect; read: SysTick exception is not pending"] + VALUE_0 = 0, + #[doc = "1: Write: changes SysTick exception state to pending; read: SysTick exception is pending"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PENDSTSET_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PENDSTSET` reader - SysTick exception set-pending bit"] +pub struct PENDSTSET_R(crate::FieldReader); +impl PENDSTSET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDSTSET_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PENDSTSET_A { + match self.bits { + false => PENDSTSET_A::VALUE_0, + true => PENDSTSET_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == PENDSTSET_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == PENDSTSET_A::VALUE_1 + } +} +impl core::ops::Deref for PENDSTSET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDSTSET` writer - SysTick exception set-pending bit"] +pub struct PENDSTSET_W<'a> { + w: &'a mut W, +} +impl<'a> PENDSTSET_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PENDSTSET_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Write: no effect; read: SysTick exception is not pending"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(PENDSTSET_A::VALUE_0) + } + #[doc = "Write: changes SysTick exception state to pending; read: SysTick exception is pending"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(PENDSTSET_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "PendSV clear-pending bit\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PENDSVCLR_A { + #[doc = "0: No effect"] + VALUE_0 = 0, + #[doc = "1: Removes the pending state from the PendSV exception"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PENDSVCLR_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PENDSVCLR` reader - PendSV clear-pending bit"] +pub struct PENDSVCLR_R(crate::FieldReader); +impl PENDSVCLR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDSVCLR_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PENDSVCLR_A { + match self.bits { + false => PENDSVCLR_A::VALUE_0, + true => PENDSVCLR_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == PENDSVCLR_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == PENDSVCLR_A::VALUE_1 + } +} +impl core::ops::Deref for PENDSVCLR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDSVCLR` writer - PendSV clear-pending bit"] +pub struct PENDSVCLR_W<'a> { + w: &'a mut W, +} +impl<'a> PENDSVCLR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PENDSVCLR_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "No effect"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(PENDSVCLR_A::VALUE_0) + } + #[doc = "Removes the pending state from the PendSV exception"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(PENDSVCLR_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +#[doc = "PendSV set-pending bit\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PENDSVSET_A { + #[doc = "0: Write: no effect; read: PendSV exception is not pending"] + VALUE_0 = 0, + #[doc = "1: Write: changes PendSV exception state to pending; read: PendSV exception is pending"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PENDSVSET_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PENDSVSET` reader - PendSV set-pending bit"] +pub struct PENDSVSET_R(crate::FieldReader); +impl PENDSVSET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDSVSET_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PENDSVSET_A { + match self.bits { + false => PENDSVSET_A::VALUE_0, + true => PENDSVSET_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == PENDSVSET_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == PENDSVSET_A::VALUE_1 + } +} +impl core::ops::Deref for PENDSVSET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDSVSET` writer - PendSV set-pending bit"] +pub struct PENDSVSET_W<'a> { + w: &'a mut W, +} +impl<'a> PENDSVSET_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PENDSVSET_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Write: no effect; read: PendSV exception is not pending"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(PENDSVSET_A::VALUE_0) + } + #[doc = "Write: changes PendSV exception state to pending; read: PendSV exception is pending"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(PENDSVSET_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "NMI set-pending bit\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum NMIPENDSET_A { + #[doc = "0: Write: no effect; read: NMI exception is not pending"] + VALUE_0 = 0, + #[doc = "1: Write: changes NMI exception state to pending; read: NMI exception is pending"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NMIPENDSET_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NMIPENDSET` reader - NMI set-pending bit"] +pub struct NMIPENDSET_R(crate::FieldReader); +impl NMIPENDSET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NMIPENDSET_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> NMIPENDSET_A { + match self.bits { + false => NMIPENDSET_A::VALUE_0, + true => NMIPENDSET_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == NMIPENDSET_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == NMIPENDSET_A::VALUE_1 + } +} +impl core::ops::Deref for NMIPENDSET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NMIPENDSET` writer - NMI set-pending bit"] +pub struct NMIPENDSET_W<'a> { + w: &'a mut W, +} +impl<'a> NMIPENDSET_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: NMIPENDSET_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Write: no effect; read: NMI exception is not pending"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(NMIPENDSET_A::VALUE_0) + } + #[doc = "Write: changes NMI exception state to pending; read: NMI exception is pending"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(NMIPENDSET_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bits 0:8 - Debug: Exception number of currently executing exception, or 0 if thread mode"] + #[inline(always)] + pub fn vectactive(&self) -> VECTACTIVE_R { + VECTACTIVE_R::new((self.bits & 0x01ff) as u16) + } + #[doc = "Bits 12:20 - Exception number of the highest priority pending enabled exception"] + #[inline(always)] + pub fn vectpending(&self) -> VECTPENDING_R { + VECTPENDING_R::new(((self.bits >> 12) & 0x01ff) as u16) + } + #[doc = "Bit 22 - Debug: NVIC interrupt pending"] + #[inline(always)] + pub fn isrpending(&self) -> ISRPENDING_R { + ISRPENDING_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Debug: Pending exception serviced on exit from debug halt"] + #[inline(always)] + pub fn isrpreempt(&self) -> ISRPREEMPT_R { + ISRPREEMPT_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 25 - SysTick exception clear-pending bit"] + #[inline(always)] + pub fn pendstclr(&self) -> PENDSTCLR_R { + PENDSTCLR_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - SysTick exception set-pending bit"] + #[inline(always)] + pub fn pendstset(&self) -> PENDSTSET_R { + PENDSTSET_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - PendSV clear-pending bit"] + #[inline(always)] + pub fn pendsvclr(&self) -> PENDSVCLR_R { + PENDSVCLR_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28 - PendSV set-pending bit"] + #[inline(always)] + pub fn pendsvset(&self) -> PENDSVSET_R { + PENDSVSET_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 31 - NMI set-pending bit"] + #[inline(always)] + pub fn nmipendset(&self) -> NMIPENDSET_R { + NMIPENDSET_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:8 - Debug: Exception number of currently executing exception, or 0 if thread mode"] + #[inline(always)] + pub fn vectactive(&mut self) -> VECTACTIVE_W { + VECTACTIVE_W { w: self } + } + #[doc = "Bits 12:20 - Exception number of the highest priority pending enabled exception"] + #[inline(always)] + pub fn vectpending(&mut self) -> VECTPENDING_W { + VECTPENDING_W { w: self } + } + #[doc = "Bit 22 - Debug: NVIC interrupt pending"] + #[inline(always)] + pub fn isrpending(&mut self) -> ISRPENDING_W { + ISRPENDING_W { w: self } + } + #[doc = "Bit 23 - Debug: Pending exception serviced on exit from debug halt"] + #[inline(always)] + pub fn isrpreempt(&mut self) -> ISRPREEMPT_W { + ISRPREEMPT_W { w: self } + } + #[doc = "Bit 25 - SysTick exception clear-pending bit"] + #[inline(always)] + pub fn pendstclr(&mut self) -> PENDSTCLR_W { + PENDSTCLR_W { w: self } + } + #[doc = "Bit 26 - SysTick exception set-pending bit"] + #[inline(always)] + pub fn pendstset(&mut self) -> PENDSTSET_W { + PENDSTSET_W { w: self } + } + #[doc = "Bit 27 - PendSV clear-pending bit"] + #[inline(always)] + pub fn pendsvclr(&mut self) -> PENDSVCLR_W { + PENDSVCLR_W { w: self } + } + #[doc = "Bit 28 - PendSV set-pending bit"] + #[inline(always)] + pub fn pendsvset(&mut self) -> PENDSVSET_W { + PENDSVSET_W { w: self } + } + #[doc = "Bit 31 - NMI set-pending bit"] + #[inline(always)] + pub fn nmipendset(&mut self) -> NMIPENDSET_W { + NMIPENDSET_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Control and State Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [icsr](index.html) module"] +pub struct ICSR_SPEC; +impl crate::RegisterSpec for ICSR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [icsr::R](R) reader structure"] +impl crate::Readable for ICSR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [icsr::W](W) writer structure"] +impl crate::Writable for ICSR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ICSR to value 0"] +impl crate::Resettable for ICSR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/system_control/scr.rs b/pac/atsamc20j/src/system_control/scr.rs new file mode 100644 index 000000000000..db9c54fe6f6f --- /dev/null +++ b/pac/atsamc20j/src/system_control/scr.rs @@ -0,0 +1,348 @@ +#[doc = "Register `SCR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SCR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Sleep-On-Exit when exiting Handler mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SLEEPONEXIT_A { + #[doc = "0: O not sleep when returning to Thread mode"] + VALUE_0 = 0, + #[doc = "1: Enter sleep, or deep sleep, on return from an ISR"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SLEEPONEXIT_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SLEEPONEXIT` reader - Sleep-On-Exit when exiting Handler mode"] +pub struct SLEEPONEXIT_R(crate::FieldReader); +impl SLEEPONEXIT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLEEPONEXIT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SLEEPONEXIT_A { + match self.bits { + false => SLEEPONEXIT_A::VALUE_0, + true => SLEEPONEXIT_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == SLEEPONEXIT_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == SLEEPONEXIT_A::VALUE_1 + } +} +impl core::ops::Deref for SLEEPONEXIT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLEEPONEXIT` writer - Sleep-On-Exit when exiting Handler mode"] +pub struct SLEEPONEXIT_W<'a> { + w: &'a mut W, +} +impl<'a> SLEEPONEXIT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SLEEPONEXIT_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "O not sleep when returning to Thread mode"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(SLEEPONEXIT_A::VALUE_0) + } + #[doc = "Enter sleep, or deep sleep, on return from an ISR"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(SLEEPONEXIT_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Uses Deep Sleep as low power mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SLEEPDEEP_A { + #[doc = "0: Sleep"] + VALUE_0 = 0, + #[doc = "1: Deep sleep"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SLEEPDEEP_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SLEEPDEEP` reader - Uses Deep Sleep as low power mode"] +pub struct SLEEPDEEP_R(crate::FieldReader); +impl SLEEPDEEP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLEEPDEEP_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SLEEPDEEP_A { + match self.bits { + false => SLEEPDEEP_A::VALUE_0, + true => SLEEPDEEP_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == SLEEPDEEP_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == SLEEPDEEP_A::VALUE_1 + } +} +impl core::ops::Deref for SLEEPDEEP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLEEPDEEP` writer - Uses Deep Sleep as low power mode"] +pub struct SLEEPDEEP_W<'a> { + w: &'a mut W, +} +impl<'a> SLEEPDEEP_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SLEEPDEEP_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Sleep"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(SLEEPDEEP_A::VALUE_0) + } + #[doc = "Deep sleep"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(SLEEPDEEP_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Send Event on Pending bit\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SEVONPEND_A { + #[doc = "0: Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded"] + VALUE_0 = 0, + #[doc = "1: Enabled events and all interrupts, including disabled interrupts, can wakeup the processor"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SEVONPEND_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SEVONPEND` reader - Send Event on Pending bit"] +pub struct SEVONPEND_R(crate::FieldReader); +impl SEVONPEND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SEVONPEND_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SEVONPEND_A { + match self.bits { + false => SEVONPEND_A::VALUE_0, + true => SEVONPEND_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == SEVONPEND_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == SEVONPEND_A::VALUE_1 + } +} +impl core::ops::Deref for SEVONPEND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEVONPEND` writer - Send Event on Pending bit"] +pub struct SEVONPEND_W<'a> { + w: &'a mut W, +} +impl<'a> SEVONPEND_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SEVONPEND_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(SEVONPEND_A::VALUE_0) + } + #[doc = "Enabled events and all interrupts, including disabled interrupts, can wakeup the processor"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(SEVONPEND_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +impl R { + #[doc = "Bit 1 - Sleep-On-Exit when exiting Handler mode"] + #[inline(always)] + pub fn sleeponexit(&self) -> SLEEPONEXIT_R { + SLEEPONEXIT_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Uses Deep Sleep as low power mode"] + #[inline(always)] + pub fn sleepdeep(&self) -> SLEEPDEEP_R { + SLEEPDEEP_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 4 - Send Event on Pending bit"] + #[inline(always)] + pub fn sevonpend(&self) -> SEVONPEND_R { + SEVONPEND_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 1 - Sleep-On-Exit when exiting Handler mode"] + #[inline(always)] + pub fn sleeponexit(&mut self) -> SLEEPONEXIT_W { + SLEEPONEXIT_W { w: self } + } + #[doc = "Bit 2 - Uses Deep Sleep as low power mode"] + #[inline(always)] + pub fn sleepdeep(&mut self) -> SLEEPDEEP_W { + SLEEPDEEP_W { w: self } + } + #[doc = "Bit 4 - Send Event on Pending bit"] + #[inline(always)] + pub fn sevonpend(&mut self) -> SEVONPEND_W { + SEVONPEND_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "System Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [scr](index.html) module"] +pub struct SCR_SPEC; +impl crate::RegisterSpec for SCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [scr::R](R) reader structure"] +impl crate::Readable for SCR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [scr::W](W) writer structure"] +impl crate::Writable for SCR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SCR to value 0"] +impl crate::Resettable for SCR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/system_control/shcsr.rs b/pac/atsamc20j/src/system_control/shcsr.rs new file mode 100644 index 000000000000..bfba26ac06ad --- /dev/null +++ b/pac/atsamc20j/src/system_control/shcsr.rs @@ -0,0 +1,113 @@ +#[doc = "Register `SHCSR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SHCSR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SVCALLPENDED` reader - "] +pub struct SVCALLPENDED_R(crate::FieldReader); +impl SVCALLPENDED_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SVCALLPENDED_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SVCALLPENDED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SVCALLPENDED` writer - "] +pub struct SVCALLPENDED_W<'a> { + w: &'a mut W, +} +impl<'a> SVCALLPENDED_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 15"] + #[inline(always)] + pub fn svcallpended(&self) -> SVCALLPENDED_R { + SVCALLPENDED_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 15"] + #[inline(always)] + pub fn svcallpended(&mut self) -> SVCALLPENDED_W { + SVCALLPENDED_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "System Handler Control and State Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [shcsr](index.html) module"] +pub struct SHCSR_SPEC; +impl crate::RegisterSpec for SHCSR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [shcsr::R](R) reader structure"] +impl crate::Readable for SHCSR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [shcsr::W](W) writer structure"] +impl crate::Writable for SHCSR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SHCSR to value 0"] +impl crate::Resettable for SHCSR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/system_control/shpr2.rs b/pac/atsamc20j/src/system_control/shpr2.rs new file mode 100644 index 000000000000..5665d6a5e8a9 --- /dev/null +++ b/pac/atsamc20j/src/system_control/shpr2.rs @@ -0,0 +1,103 @@ +#[doc = "Register `SHPR2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SHPR2` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PRI_11` reader - Priority of system handler 11, SVCall"] +pub struct PRI_11_R(crate::FieldReader); +impl PRI_11_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRI_11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PRI_11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRI_11` writer - Priority of system handler 11, SVCall"] +pub struct PRI_11_W<'a> { + w: &'a mut W, +} +impl<'a> PRI_11_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 24)) | ((value as u32 & 0xff) << 24); + self.w + } +} +impl R { + #[doc = "Bits 24:31 - Priority of system handler 11, SVCall"] + #[inline(always)] + pub fn pri_11(&self) -> PRI_11_R { + PRI_11_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 24:31 - Priority of system handler 11, SVCall"] + #[inline(always)] + pub fn pri_11(&mut self) -> PRI_11_W { + PRI_11_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "System Handler Priority Register 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [shpr2](index.html) module"] +pub struct SHPR2_SPEC; +impl crate::RegisterSpec for SHPR2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [shpr2::R](R) reader structure"] +impl crate::Readable for SHPR2_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [shpr2::W](W) writer structure"] +impl crate::Writable for SHPR2_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SHPR2 to value 0"] +impl crate::Resettable for SHPR2_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/system_control/shpr3.rs b/pac/atsamc20j/src/system_control/shpr3.rs new file mode 100644 index 000000000000..cb5a92c53503 --- /dev/null +++ b/pac/atsamc20j/src/system_control/shpr3.rs @@ -0,0 +1,140 @@ +#[doc = "Register `SHPR3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SHPR3` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PRI_14` reader - Priority of system handler 14, PendSV"] +pub struct PRI_14_R(crate::FieldReader); +impl PRI_14_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRI_14_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PRI_14_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRI_14` writer - Priority of system handler 14, PendSV"] +pub struct PRI_14_W<'a> { + w: &'a mut W, +} +impl<'a> PRI_14_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +#[doc = "Field `PRI_15` reader - Priority of system handler 15, SysTick exception"] +pub struct PRI_15_R(crate::FieldReader); +impl PRI_15_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRI_15_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PRI_15_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRI_15` writer - Priority of system handler 15, SysTick exception"] +pub struct PRI_15_W<'a> { + w: &'a mut W, +} +impl<'a> PRI_15_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 24)) | ((value as u32 & 0xff) << 24); + self.w + } +} +impl R { + #[doc = "Bits 16:23 - Priority of system handler 14, PendSV"] + #[inline(always)] + pub fn pri_14(&self) -> PRI_14_R { + PRI_14_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Priority of system handler 15, SysTick exception"] + #[inline(always)] + pub fn pri_15(&self) -> PRI_15_R { + PRI_15_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 16:23 - Priority of system handler 14, PendSV"] + #[inline(always)] + pub fn pri_14(&mut self) -> PRI_14_W { + PRI_14_W { w: self } + } + #[doc = "Bits 24:31 - Priority of system handler 15, SysTick exception"] + #[inline(always)] + pub fn pri_15(&mut self) -> PRI_15_W { + PRI_15_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "System Handler Priority Register 3\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [shpr3](index.html) module"] +pub struct SHPR3_SPEC; +impl crate::RegisterSpec for SHPR3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [shpr3::R](R) reader structure"] +impl crate::Readable for SHPR3_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [shpr3::W](W) writer structure"] +impl crate::Writable for SHPR3_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SHPR3 to value 0"] +impl crate::Resettable for SHPR3_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/system_control/vtor.rs b/pac/atsamc20j/src/system_control/vtor.rs new file mode 100644 index 000000000000..0ee4c7817817 --- /dev/null +++ b/pac/atsamc20j/src/system_control/vtor.rs @@ -0,0 +1,103 @@ +#[doc = "Register `VTOR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `VTOR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TBLOFF` reader - Vector table base offset"] +pub struct TBLOFF_R(crate::FieldReader); +impl TBLOFF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + TBLOFF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TBLOFF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TBLOFF` writer - Vector table base offset"] +pub struct TBLOFF_W<'a> { + w: &'a mut W, +} +impl<'a> TBLOFF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01ff_ffff << 7)) | ((value as u32 & 0x01ff_ffff) << 7); + self.w + } +} +impl R { + #[doc = "Bits 7:31 - Vector table base offset"] + #[inline(always)] + pub fn tbloff(&self) -> TBLOFF_R { + TBLOFF_R::new(((self.bits >> 7) & 0x01ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 7:31 - Vector table base offset"] + #[inline(always)] + pub fn tbloff(&mut self) -> TBLOFF_W { + TBLOFF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Vector Table Offset Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [vtor](index.html) module"] +pub struct VTOR_SPEC; +impl crate::RegisterSpec for VTOR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [vtor::R](R) reader structure"] +impl crate::Readable for VTOR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [vtor::W](W) writer structure"] +impl crate::Writable for VTOR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets VTOR to value 0"] +impl crate::Resettable for VTOR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/tc0.rs b/pac/atsamc20j/src/tc0.rs new file mode 100644 index 000000000000..86e973b276e7 --- /dev/null +++ b/pac/atsamc20j/src/tc0.rs @@ -0,0 +1,146 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved_0_count8: [u8; 0x38], +} +impl RegisterBlock { + #[doc = "0x00..0x38 - 32-bit Counter Mode"] + #[inline(always)] + pub fn count32(&self) -> &COUNT32 { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const COUNT32) } + } + #[doc = "0x00..0x34 - 16-bit Counter Mode"] + #[inline(always)] + pub fn count16(&self) -> &COUNT16 { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const COUNT16) } + } + #[doc = "0x00..0x32 - 8-bit Counter Mode"] + #[inline(always)] + pub fn count8(&self) -> &COUNT8 { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const COUNT8) } + } +} +#[doc = r"Register block"] +#[repr(C)] +pub struct COUNT8 { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - Control B Clear"] + pub ctrlbclr: crate::Reg, + #[doc = "0x05 - Control B Set"] + pub ctrlbset: crate::Reg, + #[doc = "0x06 - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x08 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x09 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x0a - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x0b - Status"] + pub status: crate::Reg, + #[doc = "0x0c - Waveform Generation Control"] + pub wave: crate::Reg, + #[doc = "0x0d - Control C"] + pub drvctrl: crate::Reg, + _reserved10: [u8; 0x01], + #[doc = "0x0f - Debug Control"] + pub dbgctrl: crate::Reg, + #[doc = "0x10 - Synchronization Status"] + pub syncbusy: crate::Reg, + #[doc = "0x14 - COUNT8 Count"] + pub count: crate::Reg, + _reserved13: [u8; 0x06], + #[doc = "0x1b - COUNT8 Period"] + pub per: crate::Reg, + #[doc = "0x1c - COUNT8 Compare and Capture"] + pub cc: [crate::Reg; 2], + _reserved15: [u8; 0x11], + #[doc = "0x2f - COUNT8 Period Buffer"] + pub perbuf: crate::Reg, + #[doc = "0x30 - COUNT8 Compare and Capture Buffer"] + pub ccbuf: [crate::Reg; 2], +} +#[doc = r"Register block"] +#[doc = "8-bit Counter Mode"] +pub mod count8; +#[doc = r"Register block"] +#[repr(C)] +pub struct COUNT16 { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - Control B Clear"] + pub ctrlbclr: crate::Reg, + #[doc = "0x05 - Control B Set"] + pub ctrlbset: crate::Reg, + #[doc = "0x06 - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x08 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x09 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x0a - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x0b - Status"] + pub status: crate::Reg, + #[doc = "0x0c - Waveform Generation Control"] + pub wave: crate::Reg, + #[doc = "0x0d - Control C"] + pub drvctrl: crate::Reg, + _reserved10: [u8; 0x01], + #[doc = "0x0f - Debug Control"] + pub dbgctrl: crate::Reg, + #[doc = "0x10 - Synchronization Status"] + pub syncbusy: crate::Reg, + #[doc = "0x14 - COUNT16 Count"] + pub count: crate::Reg, + _reserved13: [u8; 0x06], + #[doc = "0x1c - COUNT16 Compare and Capture"] + pub cc: [crate::Reg; 2], + _reserved14: [u8; 0x10], + #[doc = "0x30 - COUNT16 Compare and Capture Buffer"] + pub ccbuf: [crate::Reg; 2], +} +#[doc = r"Register block"] +#[doc = "16-bit Counter Mode"] +pub mod count16; +#[doc = r"Register block"] +#[repr(C)] +pub struct COUNT32 { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - Control B Clear"] + pub ctrlbclr: crate::Reg, + #[doc = "0x05 - Control B Set"] + pub ctrlbset: crate::Reg, + #[doc = "0x06 - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x08 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x09 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x0a - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x0b - Status"] + pub status: crate::Reg, + #[doc = "0x0c - Waveform Generation Control"] + pub wave: crate::Reg, + #[doc = "0x0d - Control C"] + pub drvctrl: crate::Reg, + _reserved10: [u8; 0x01], + #[doc = "0x0f - Debug Control"] + pub dbgctrl: crate::Reg, + #[doc = "0x10 - Synchronization Status"] + pub syncbusy: crate::Reg, + #[doc = "0x14 - COUNT32 Count"] + pub count: crate::Reg, + _reserved13: [u8; 0x04], + #[doc = "0x1c..0x24 - COUNT32 Compare and Capture"] + pub cc: [crate::Reg; 2], + _reserved14: [u8; 0x0c], + #[doc = "0x30..0x38 - COUNT32 Compare and Capture Buffer"] + pub ccbuf: [crate::Reg; 2], +} +#[doc = r"Register block"] +#[doc = "32-bit Counter Mode"] +pub mod count32; diff --git a/pac/atsamc20j/src/tc0/count16.rs b/pac/atsamc20j/src/tc0/count16.rs new file mode 100644 index 000000000000..5bd1e88c7efb --- /dev/null +++ b/pac/atsamc20j/src/tc0/count16.rs @@ -0,0 +1,60 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "CTRLBCLR register accessor: an alias for `Reg`"] +pub type CTRLBCLR = crate::Reg; +#[doc = "Control B Clear"] +pub mod ctrlbclr; +#[doc = "CTRLBSET register accessor: an alias for `Reg`"] +pub type CTRLBSET = crate::Reg; +#[doc = "Control B Set"] +pub mod ctrlbset; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "WAVE register accessor: an alias for `Reg`"] +pub type WAVE = crate::Reg; +#[doc = "Waveform Generation Control"] +pub mod wave; +#[doc = "DRVCTRL register accessor: an alias for `Reg`"] +pub type DRVCTRL = crate::Reg; +#[doc = "Control C"] +pub mod drvctrl; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Status"] +pub mod syncbusy; +#[doc = "COUNT register accessor: an alias for `Reg`"] +pub type COUNT = crate::Reg; +#[doc = "COUNT16 Count"] +pub mod count; +#[doc = "CC register accessor: an alias for `Reg`"] +pub type CC = crate::Reg; +#[doc = "COUNT16 Compare and Capture"] +pub mod cc; +#[doc = "CCBUF register accessor: an alias for `Reg`"] +pub type CCBUF = crate::Reg; +#[doc = "COUNT16 Compare and Capture Buffer"] +pub mod ccbuf; diff --git a/pac/atsamc20j/src/tc0/count16/cc.rs b/pac/atsamc20j/src/tc0/count16/cc.rs new file mode 100644 index 000000000000..b6f975905e31 --- /dev/null +++ b/pac/atsamc20j/src/tc0/count16/cc.rs @@ -0,0 +1,104 @@ +#[doc = "Register `CC[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CC[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CC` reader - Counter/Compare Value"] +pub struct CC_R(crate::FieldReader); +impl CC_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + CC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC` writer - Counter/Compare Value"] +pub struct CC_W<'a> { + w: &'a mut W, +} +impl<'a> CC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Counter/Compare Value"] + #[inline(always)] + pub fn cc(&self) -> CC_R { + CC_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Counter/Compare Value"] + #[inline(always)] + pub fn cc(&mut self) -> CC_W { + CC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT16 Compare and Capture\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc](index.html) module"] +pub struct CC_SPEC; +impl crate::RegisterSpec for CC_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [cc::R](R) reader structure"] +impl crate::Readable for CC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cc::W](W) writer structure"] +impl crate::Writable for CC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CC[%s] +to value 0"] +impl crate::Resettable for CC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/tc0/count16/ccbuf.rs b/pac/atsamc20j/src/tc0/count16/ccbuf.rs new file mode 100644 index 000000000000..2f922bba8d31 --- /dev/null +++ b/pac/atsamc20j/src/tc0/count16/ccbuf.rs @@ -0,0 +1,104 @@ +#[doc = "Register `CCBUF[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CCBUF[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CCBUF` reader - Counter/Compare Buffer Value"] +pub struct CCBUF_R(crate::FieldReader); +impl CCBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + CCBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUF` writer - Counter/Compare Buffer Value"] +pub struct CCBUF_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Counter/Compare Buffer Value"] + #[inline(always)] + pub fn ccbuf(&self) -> CCBUF_R { + CCBUF_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Counter/Compare Buffer Value"] + #[inline(always)] + pub fn ccbuf(&mut self) -> CCBUF_W { + CCBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT16 Compare and Capture Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccbuf](index.html) module"] +pub struct CCBUF_SPEC; +impl crate::RegisterSpec for CCBUF_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ccbuf::R](R) reader structure"] +impl crate::Readable for CCBUF_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ccbuf::W](W) writer structure"] +impl crate::Writable for CCBUF_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CCBUF[%s] +to value 0"] +impl crate::Resettable for CCBUF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/tc0/count16/count.rs b/pac/atsamc20j/src/tc0/count16/count.rs new file mode 100644 index 000000000000..5d26b509abb1 --- /dev/null +++ b/pac/atsamc20j/src/tc0/count16/count.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT16 Count\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count](index.html) module"] +pub struct COUNT_SPEC; +impl crate::RegisterSpec for COUNT_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [count::R](R) reader structure"] +impl crate::Readable for COUNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count::W](W) writer structure"] +impl crate::Writable for COUNT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT to value 0"] +impl crate::Resettable for COUNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/tc0/count16/ctrla.rs b/pac/atsamc20j/src/tc0/count16/ctrla.rs new file mode 100644 index 000000000000..cadcddaaead8 --- /dev/null +++ b/pac/atsamc20j/src/tc0/count16/ctrla.rs @@ -0,0 +1,851 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Timer Counter Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: Counter in 16-bit mode"] + COUNT16 = 0, + #[doc = "1: Counter in 8-bit mode"] + COUNT8 = 1, + #[doc = "2: Counter in 32-bit mode"] + COUNT32 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Timer Counter Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::COUNT16), + 1 => Some(MODE_A::COUNT8), + 2 => Some(MODE_A::COUNT32), + _ => None, + } + } + #[doc = "Checks if the value of the field is `COUNT16`"] + #[inline(always)] + pub fn is_count16(&self) -> bool { + **self == MODE_A::COUNT16 + } + #[doc = "Checks if the value of the field is `COUNT8`"] + #[inline(always)] + pub fn is_count8(&self) -> bool { + **self == MODE_A::COUNT8 + } + #[doc = "Checks if the value of the field is `COUNT32`"] + #[inline(always)] + pub fn is_count32(&self) -> bool { + **self == MODE_A::COUNT32 + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Timer Counter Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Counter in 16-bit mode"] + #[inline(always)] + pub fn count16(self) -> &'a mut W { + self.variant(MODE_A::COUNT16) + } + #[doc = "Counter in 8-bit mode"] + #[inline(always)] + pub fn count8(self) -> &'a mut W { + self.variant(MODE_A::COUNT8) + } + #[doc = "Counter in 32-bit mode"] + #[inline(always)] + pub fn count32(self) -> &'a mut W { + self.variant(MODE_A::COUNT32) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u32 & 0x03) << 2); + self.w + } +} +#[doc = "Prescaler and Counter Synchronization\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCSYNC_A { + #[doc = "0: Reload or reset the counter on next generic clock"] + GCLK = 0, + #[doc = "1: Reload or reset the counter on next prescaler clock"] + PRESC = 1, + #[doc = "2: Reload or reset the counter on next generic clock and reset the prescaler counter"] + RESYNC = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCSYNC_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCSYNC` reader - Prescaler and Counter Synchronization"] +pub struct PRESCSYNC_R(crate::FieldReader); +impl PRESCSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCSYNC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCSYNC_A::GCLK), + 1 => Some(PRESCSYNC_A::PRESC), + 2 => Some(PRESCSYNC_A::RESYNC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `GCLK`"] + #[inline(always)] + pub fn is_gclk(&self) -> bool { + **self == PRESCSYNC_A::GCLK + } + #[doc = "Checks if the value of the field is `PRESC`"] + #[inline(always)] + pub fn is_presc(&self) -> bool { + **self == PRESCSYNC_A::PRESC + } + #[doc = "Checks if the value of the field is `RESYNC`"] + #[inline(always)] + pub fn is_resync(&self) -> bool { + **self == PRESCSYNC_A::RESYNC + } +} +impl core::ops::Deref for PRESCSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCSYNC` writer - Prescaler and Counter Synchronization"] +pub struct PRESCSYNC_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCSYNC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCSYNC_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Reload or reset the counter on next generic clock"] + #[inline(always)] + pub fn gclk(self) -> &'a mut W { + self.variant(PRESCSYNC_A::GCLK) + } + #[doc = "Reload or reset the counter on next prescaler clock"] + #[inline(always)] + pub fn presc(self) -> &'a mut W { + self.variant(PRESCSYNC_A::PRESC) + } + #[doc = "Reload or reset the counter on next generic clock and reset the prescaler counter"] + #[inline(always)] + pub fn resync(self) -> &'a mut W { + self.variant(PRESCSYNC_A::RESYNC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u32 & 0x03) << 4); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - Clock On Demand"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - Clock On Demand"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: Prescaler: GCLK_TC"] + DIV1 = 0, + #[doc = "1: Prescaler: GCLK_TC/2"] + DIV2 = 1, + #[doc = "2: Prescaler: GCLK_TC/4"] + DIV4 = 2, + #[doc = "3: Prescaler: GCLK_TC/8"] + DIV8 = 3, + #[doc = "4: Prescaler: GCLK_TC/16"] + DIV16 = 4, + #[doc = "5: Prescaler: GCLK_TC/64"] + DIV64 = 5, + #[doc = "6: Prescaler: GCLK_TC/256"] + DIV256 = 6, + #[doc = "7: Prescaler: GCLK_TC/1024"] + DIV1024 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PRESCALER_A { + match self.bits { + 0 => PRESCALER_A::DIV1, + 1 => PRESCALER_A::DIV2, + 2 => PRESCALER_A::DIV4, + 3 => PRESCALER_A::DIV8, + 4 => PRESCALER_A::DIV16, + 5 => PRESCALER_A::DIV64, + 6 => PRESCALER_A::DIV256, + 7 => PRESCALER_A::DIV1024, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == PRESCALER_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PRESCALER_A::DIV1024 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Prescaler: GCLK_TC"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1) + } + #[doc = "Prescaler: GCLK_TC/2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "Prescaler: GCLK_TC/4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "Prescaler: GCLK_TC/8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "Prescaler: GCLK_TC/16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "Prescaler: GCLK_TC/64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "Prescaler: GCLK_TC/256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = "Prescaler: GCLK_TC/1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +#[doc = "Field `ALOCK` reader - Auto Lock"] +pub struct ALOCK_R(crate::FieldReader); +impl ALOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALOCK` writer - Auto Lock"] +pub struct ALOCK_W<'a> { + w: &'a mut W, +} +impl<'a> ALOCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `CAPTEN0` reader - Capture Channel 0 Enable"] +pub struct CAPTEN0_R(crate::FieldReader); +impl CAPTEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CAPTEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CAPTEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAPTEN0` writer - Capture Channel 0 Enable"] +pub struct CAPTEN0_W<'a> { + w: &'a mut W, +} +impl<'a> CAPTEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `CAPTEN1` reader - Capture Channel 1 Enable"] +pub struct CAPTEN1_R(crate::FieldReader); +impl CAPTEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CAPTEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CAPTEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAPTEN1` writer - Capture Channel 1 Enable"] +pub struct CAPTEN1_W<'a> { + w: &'a mut W, +} +impl<'a> CAPTEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `COPEN0` reader - Capture On Pin 0 Enable"] +pub struct COPEN0_R(crate::FieldReader); +impl COPEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COPEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COPEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COPEN0` writer - Capture On Pin 0 Enable"] +pub struct COPEN0_W<'a> { + w: &'a mut W, +} +impl<'a> COPEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `COPEN1` reader - Capture On Pin 1 Enable"] +pub struct COPEN1_R(crate::FieldReader); +impl COPEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COPEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COPEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COPEN1` writer - Capture On Pin 1 Enable"] +pub struct COPEN1_W<'a> { + w: &'a mut W, +} +impl<'a> COPEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:3 - Timer Counter Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bits 4:5 - Prescaler and Counter Synchronization"] + #[inline(always)] + pub fn prescsync(&self) -> PRESCSYNC_R { + PRESCSYNC_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Clock On Demand"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 11 - Auto Lock"] + #[inline(always)] + pub fn alock(&self) -> ALOCK_R { + ALOCK_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 16 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn capten0(&self) -> CAPTEN0_R { + CAPTEN0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn capten1(&self) -> CAPTEN1_R { + CAPTEN1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 20 - Capture On Pin 0 Enable"] + #[inline(always)] + pub fn copen0(&self) -> COPEN0_R { + COPEN0_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Capture On Pin 1 Enable"] + #[inline(always)] + pub fn copen1(&self) -> COPEN1_R { + COPEN1_R::new(((self.bits >> 21) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:3 - Timer Counter Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bits 4:5 - Prescaler and Counter Synchronization"] + #[inline(always)] + pub fn prescsync(&mut self) -> PRESCSYNC_W { + PRESCSYNC_W { w: self } + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - Clock On Demand"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Bit 11 - Auto Lock"] + #[inline(always)] + pub fn alock(&mut self) -> ALOCK_W { + ALOCK_W { w: self } + } + #[doc = "Bit 16 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn capten0(&mut self) -> CAPTEN0_W { + CAPTEN0_W { w: self } + } + #[doc = "Bit 17 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn capten1(&mut self) -> CAPTEN1_W { + CAPTEN1_W { w: self } + } + #[doc = "Bit 20 - Capture On Pin 0 Enable"] + #[inline(always)] + pub fn copen0(&mut self) -> COPEN0_W { + COPEN0_W { w: self } + } + #[doc = "Bit 21 - Capture On Pin 1 Enable"] + #[inline(always)] + pub fn copen1(&mut self) -> COPEN1_W { + COPEN1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/tc0/count16/ctrlbclr.rs b/pac/atsamc20j/src/tc0/count16/ctrlbclr.rs new file mode 100644 index 000000000000..76265674036a --- /dev/null +++ b/pac/atsamc20j/src/tc0/count16/ctrlbclr.rs @@ -0,0 +1,345 @@ +#[doc = "Register `CTRLBCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Counter Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `LUPD` reader - Lock Update"] +pub struct LUPD_R(crate::FieldReader); +impl LUPD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LUPD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LUPD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LUPD` writer - Lock Update"] +pub struct LUPD_W<'a> { + w: &'a mut W, +} +impl<'a> LUPD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ONESHOT` reader - One-Shot on Counter"] +pub struct ONESHOT_R(crate::FieldReader); +impl ONESHOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONESHOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONESHOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONESHOT` writer - One-Shot on Counter"] +pub struct ONESHOT_W<'a> { + w: &'a mut W, +} +impl<'a> ONESHOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Force a start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force a stop"] + STOP = 2, + #[doc = "3: Force update of double-buffered register"] + UPDATE = 3, + #[doc = "4: Force a read synchronization of COUNT"] + READSYNC = 4, + #[doc = "5: One-shot DMA trigger"] + DMAOS = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NONE), + 1 => Some(CMD_A::RETRIGGER), + 2 => Some(CMD_A::STOP), + 3 => Some(CMD_A::UPDATE), + 4 => Some(CMD_A::READSYNC), + 5 => Some(CMD_A::DMAOS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == CMD_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == CMD_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == CMD_A::STOP + } + #[doc = "Checks if the value of the field is `UPDATE`"] + #[inline(always)] + pub fn is_update(&self) -> bool { + **self == CMD_A::UPDATE + } + #[doc = "Checks if the value of the field is `READSYNC`"] + #[inline(always)] + pub fn is_readsync(&self) -> bool { + **self == CMD_A::READSYNC + } + #[doc = "Checks if the value of the field is `DMAOS`"] + #[inline(always)] + pub fn is_dmaos(&self) -> bool { + **self == CMD_A::DMAOS + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMD_A::NONE) + } + #[doc = "Force a start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMD_A::RETRIGGER) + } + #[doc = "Force a stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMD_A::STOP) + } + #[doc = "Force update of double-buffered register"] + #[inline(always)] + pub fn update(self) -> &'a mut W { + self.variant(CMD_A::UPDATE) + } + #[doc = "Force a read synchronization of COUNT"] + #[inline(always)] + pub fn readsync(self) -> &'a mut W { + self.variant(CMD_A::READSYNC) + } + #[doc = "One-shot DMA trigger"] + #[inline(always)] + pub fn dmaos(self) -> &'a mut W { + self.variant(CMD_A::DMAOS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 5)) | ((value as u8 & 0x07) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&self) -> LUPD_R { + LUPD_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 5) & 0x07) as u8) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&mut self) -> LUPD_W { + LUPD_W { w: self } + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&mut self) -> ONESHOT_W { + ONESHOT_W { w: self } + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbclr](index.html) module"] +pub struct CTRLBCLR_SPEC; +impl crate::RegisterSpec for CTRLBCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbclr::R](R) reader structure"] +impl crate::Readable for CTRLBCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbclr::W](W) writer structure"] +impl crate::Writable for CTRLBCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLBCLR to value 0"] +impl crate::Resettable for CTRLBCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/tc0/count16/ctrlbset.rs b/pac/atsamc20j/src/tc0/count16/ctrlbset.rs new file mode 100644 index 000000000000..610914c9c7c8 --- /dev/null +++ b/pac/atsamc20j/src/tc0/count16/ctrlbset.rs @@ -0,0 +1,345 @@ +#[doc = "Register `CTRLBSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Counter Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `LUPD` reader - Lock Update"] +pub struct LUPD_R(crate::FieldReader); +impl LUPD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LUPD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LUPD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LUPD` writer - Lock Update"] +pub struct LUPD_W<'a> { + w: &'a mut W, +} +impl<'a> LUPD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ONESHOT` reader - One-Shot on Counter"] +pub struct ONESHOT_R(crate::FieldReader); +impl ONESHOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONESHOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONESHOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONESHOT` writer - One-Shot on Counter"] +pub struct ONESHOT_W<'a> { + w: &'a mut W, +} +impl<'a> ONESHOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Force a start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force a stop"] + STOP = 2, + #[doc = "3: Force update of double-buffered register"] + UPDATE = 3, + #[doc = "4: Force a read synchronization of COUNT"] + READSYNC = 4, + #[doc = "5: One-shot DMA trigger"] + DMAOS = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NONE), + 1 => Some(CMD_A::RETRIGGER), + 2 => Some(CMD_A::STOP), + 3 => Some(CMD_A::UPDATE), + 4 => Some(CMD_A::READSYNC), + 5 => Some(CMD_A::DMAOS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == CMD_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == CMD_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == CMD_A::STOP + } + #[doc = "Checks if the value of the field is `UPDATE`"] + #[inline(always)] + pub fn is_update(&self) -> bool { + **self == CMD_A::UPDATE + } + #[doc = "Checks if the value of the field is `READSYNC`"] + #[inline(always)] + pub fn is_readsync(&self) -> bool { + **self == CMD_A::READSYNC + } + #[doc = "Checks if the value of the field is `DMAOS`"] + #[inline(always)] + pub fn is_dmaos(&self) -> bool { + **self == CMD_A::DMAOS + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMD_A::NONE) + } + #[doc = "Force a start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMD_A::RETRIGGER) + } + #[doc = "Force a stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMD_A::STOP) + } + #[doc = "Force update of double-buffered register"] + #[inline(always)] + pub fn update(self) -> &'a mut W { + self.variant(CMD_A::UPDATE) + } + #[doc = "Force a read synchronization of COUNT"] + #[inline(always)] + pub fn readsync(self) -> &'a mut W { + self.variant(CMD_A::READSYNC) + } + #[doc = "One-shot DMA trigger"] + #[inline(always)] + pub fn dmaos(self) -> &'a mut W { + self.variant(CMD_A::DMAOS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 5)) | ((value as u8 & 0x07) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&self) -> LUPD_R { + LUPD_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 5) & 0x07) as u8) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&mut self) -> LUPD_W { + LUPD_W { w: self } + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&mut self) -> ONESHOT_W { + ONESHOT_W { w: self } + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbset](index.html) module"] +pub struct CTRLBSET_SPEC; +impl crate::RegisterSpec for CTRLBSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbset::R](R) reader structure"] +impl crate::Readable for CTRLBSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbset::W](W) writer structure"] +impl crate::Writable for CTRLBSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLBSET to value 0"] +impl crate::Resettable for CTRLBSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/tc0/count16/dbgctrl.rs b/pac/atsamc20j/src/tc0/count16/dbgctrl.rs new file mode 100644 index 000000000000..0383e70d0429 --- /dev/null +++ b/pac/atsamc20j/src/tc0/count16/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Run During Debug"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Run During Debug"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/tc0/count16/drvctrl.rs b/pac/atsamc20j/src/tc0/count16/drvctrl.rs new file mode 100644 index 000000000000..323926b4b22d --- /dev/null +++ b/pac/atsamc20j/src/tc0/count16/drvctrl.rs @@ -0,0 +1,160 @@ +#[doc = "Register `DRVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DRVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INVEN0` reader - Output Waveform Invert Enable 0"] +pub struct INVEN0_R(crate::FieldReader); +impl INVEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN0` writer - Output Waveform Invert Enable 0"] +pub struct INVEN0_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `INVEN1` reader - Output Waveform Invert Enable 1"] +pub struct INVEN1_R(crate::FieldReader); +impl INVEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN1` writer - Output Waveform Invert Enable 1"] +pub struct INVEN1_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - Output Waveform Invert Enable 0"] + #[inline(always)] + pub fn inven0(&self) -> INVEN0_R { + INVEN0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Output Waveform Invert Enable 1"] + #[inline(always)] + pub fn inven1(&self) -> INVEN1_R { + INVEN1_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Output Waveform Invert Enable 0"] + #[inline(always)] + pub fn inven0(&mut self) -> INVEN0_W { + INVEN0_W { w: self } + } + #[doc = "Bit 1 - Output Waveform Invert Enable 1"] + #[inline(always)] + pub fn inven1(&mut self) -> INVEN1_W { + INVEN1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control C\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [drvctrl](index.html) module"] +pub struct DRVCTRL_SPEC; +impl crate::RegisterSpec for DRVCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [drvctrl::R](R) reader structure"] +impl crate::Readable for DRVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [drvctrl::W](W) writer structure"] +impl crate::Writable for DRVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DRVCTRL to value 0"] +impl crate::Resettable for DRVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/tc0/count16/evctrl.rs b/pac/atsamc20j/src/tc0/count16/evctrl.rs new file mode 100644 index 000000000000..7d4c38d486c1 --- /dev/null +++ b/pac/atsamc20j/src/tc0/count16/evctrl.rs @@ -0,0 +1,465 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Event Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EVACT_A { + #[doc = "0: Event action disabled"] + OFF = 0, + #[doc = "1: Start, restart or retrigger TC on event"] + RETRIGGER = 1, + #[doc = "2: Count on event"] + COUNT = 2, + #[doc = "3: Start TC on event"] + START = 3, + #[doc = "4: Time stamp capture"] + STAMP = 4, + #[doc = "5: Period catured in CC0, pulse width in CC1"] + PPW = 5, + #[doc = "6: Period catured in CC1, pulse width in CC0"] + PWP = 6, + #[doc = "7: Pulse width capture"] + PW = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EVACT_A) -> Self { + variant as _ + } +} +#[doc = "Field `EVACT` reader - Event Action"] +pub struct EVACT_R(crate::FieldReader); +impl EVACT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVACT_A { + match self.bits { + 0 => EVACT_A::OFF, + 1 => EVACT_A::RETRIGGER, + 2 => EVACT_A::COUNT, + 3 => EVACT_A::START, + 4 => EVACT_A::STAMP, + 5 => EVACT_A::PPW, + 6 => EVACT_A::PWP, + 7 => EVACT_A::PW, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == EVACT_A::OFF + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == EVACT_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `COUNT`"] + #[inline(always)] + pub fn is_count(&self) -> bool { + **self == EVACT_A::COUNT + } + #[doc = "Checks if the value of the field is `START`"] + #[inline(always)] + pub fn is_start(&self) -> bool { + **self == EVACT_A::START + } + #[doc = "Checks if the value of the field is `STAMP`"] + #[inline(always)] + pub fn is_stamp(&self) -> bool { + **self == EVACT_A::STAMP + } + #[doc = "Checks if the value of the field is `PPW`"] + #[inline(always)] + pub fn is_ppw(&self) -> bool { + **self == EVACT_A::PPW + } + #[doc = "Checks if the value of the field is `PWP`"] + #[inline(always)] + pub fn is_pwp(&self) -> bool { + **self == EVACT_A::PWP + } + #[doc = "Checks if the value of the field is `PW`"] + #[inline(always)] + pub fn is_pw(&self) -> bool { + **self == EVACT_A::PW + } +} +impl core::ops::Deref for EVACT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT` writer - Event Action"] +pub struct EVACT_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EVACT_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Event action disabled"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(EVACT_A::OFF) + } + #[doc = "Start, restart or retrigger TC on event"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(EVACT_A::RETRIGGER) + } + #[doc = "Count on event"] + #[inline(always)] + pub fn count(self) -> &'a mut W { + self.variant(EVACT_A::COUNT) + } + #[doc = "Start TC on event"] + #[inline(always)] + pub fn start(self) -> &'a mut W { + self.variant(EVACT_A::START) + } + #[doc = "Time stamp capture"] + #[inline(always)] + pub fn stamp(self) -> &'a mut W { + self.variant(EVACT_A::STAMP) + } + #[doc = "Period catured in CC0, pulse width in CC1"] + #[inline(always)] + pub fn ppw(self) -> &'a mut W { + self.variant(EVACT_A::PPW) + } + #[doc = "Period catured in CC1, pulse width in CC0"] + #[inline(always)] + pub fn pwp(self) -> &'a mut W { + self.variant(EVACT_A::PWP) + } + #[doc = "Pulse width capture"] + #[inline(always)] + pub fn pw(self) -> &'a mut W { + self.variant(EVACT_A::PW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u16 & 0x07); + self.w + } +} +#[doc = "Field `TCINV` reader - TC Event Input Polarity"] +pub struct TCINV_R(crate::FieldReader); +impl TCINV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCINV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCINV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCINV` writer - TC Event Input Polarity"] +pub struct TCINV_W<'a> { + w: &'a mut W, +} +impl<'a> TCINV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `TCEI` reader - TC Event Enable"] +pub struct TCEI_R(crate::FieldReader); +impl TCEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCEI` writer - TC Event Enable"] +pub struct TCEI_W<'a> { + w: &'a mut W, +} +impl<'a> TCEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `OVFEO` reader - Event Output Enable"] +pub struct OVFEO_R(crate::FieldReader); +impl OVFEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVFEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVFEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVFEO` writer - Event Output Enable"] +pub struct OVFEO_W<'a> { + w: &'a mut W, +} +impl<'a> OVFEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `MCEO0` reader - MC Event Output Enable 0"] +pub struct MCEO0_R(crate::FieldReader); +impl MCEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO0` writer - MC Event Output Enable 0"] +pub struct MCEO0_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u16 & 0x01) << 12); + self.w + } +} +#[doc = "Field `MCEO1` reader - MC Event Output Enable 1"] +pub struct MCEO1_R(crate::FieldReader); +impl MCEO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO1` writer - MC Event Output Enable 1"] +pub struct MCEO1_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u16 & 0x01) << 13); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Event Action"] + #[inline(always)] + pub fn evact(&self) -> EVACT_R { + EVACT_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 4 - TC Event Input Polarity"] + #[inline(always)] + pub fn tcinv(&self) -> TCINV_R { + TCINV_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - TC Event Enable"] + #[inline(always)] + pub fn tcei(&self) -> TCEI_R { + TCEI_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 8 - Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&self) -> OVFEO_R { + OVFEO_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 12 - MC Event Output Enable 0"] + #[inline(always)] + pub fn mceo0(&self) -> MCEO0_R { + MCEO0_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - MC Event Output Enable 1"] + #[inline(always)] + pub fn mceo1(&self) -> MCEO1_R { + MCEO1_R::new(((self.bits >> 13) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Event Action"] + #[inline(always)] + pub fn evact(&mut self) -> EVACT_W { + EVACT_W { w: self } + } + #[doc = "Bit 4 - TC Event Input Polarity"] + #[inline(always)] + pub fn tcinv(&mut self) -> TCINV_W { + TCINV_W { w: self } + } + #[doc = "Bit 5 - TC Event Enable"] + #[inline(always)] + pub fn tcei(&mut self) -> TCEI_W { + TCEI_W { w: self } + } + #[doc = "Bit 8 - Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&mut self) -> OVFEO_W { + OVFEO_W { w: self } + } + #[doc = "Bit 12 - MC Event Output Enable 0"] + #[inline(always)] + pub fn mceo0(&mut self) -> MCEO0_W { + MCEO0_W { w: self } + } + #[doc = "Bit 13 - MC Event Output Enable 1"] + #[inline(always)] + pub fn mceo1(&mut self) -> MCEO1_W { + MCEO1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/tc0/count16/intenclr.rs b/pac/atsamc20j/src/tc0/count16/intenclr.rs new file mode 100644 index 000000000000..af01ef5b7dca --- /dev/null +++ b/pac/atsamc20j/src/tc0/count16/intenclr.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - OVF Interrupt Disable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - OVF Interrupt Disable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - ERR Interrupt Disable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - ERR Interrupt Disable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MC0` reader - MC Interrupt Disable 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - MC Interrupt Disable 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - MC Interrupt Disable 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - MC Interrupt Disable 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - OVF Interrupt Disable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ERR Interrupt Disable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - MC Interrupt Disable 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - MC Interrupt Disable 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - OVF Interrupt Disable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - ERR Interrupt Disable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 4 - MC Interrupt Disable 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - MC Interrupt Disable 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/tc0/count16/intenset.rs b/pac/atsamc20j/src/tc0/count16/intenset.rs new file mode 100644 index 000000000000..0e1883a2f20a --- /dev/null +++ b/pac/atsamc20j/src/tc0/count16/intenset.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - OVF Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - OVF Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - ERR Interrupt Enable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - ERR Interrupt Enable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MC0` reader - MC Interrupt Enable 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - MC Interrupt Enable 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - MC Interrupt Enable 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - MC Interrupt Enable 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - OVF Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ERR Interrupt Enable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - MC Interrupt Enable 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - MC Interrupt Enable 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - OVF Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - ERR Interrupt Enable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 4 - MC Interrupt Enable 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - MC Interrupt Enable 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/tc0/count16/intflag.rs b/pac/atsamc20j/src/tc0/count16/intflag.rs new file mode 100644 index 000000000000..1dddffaf8e7f --- /dev/null +++ b/pac/atsamc20j/src/tc0/count16/intflag.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - OVF Interrupt Flag"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - OVF Interrupt Flag"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - ERR Interrupt Flag"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - ERR Interrupt Flag"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MC0` reader - MC Interrupt Flag 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - MC Interrupt Flag 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - MC Interrupt Flag 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - MC Interrupt Flag 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - OVF Interrupt Flag"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ERR Interrupt Flag"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - MC Interrupt Flag 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - MC Interrupt Flag 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - OVF Interrupt Flag"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - ERR Interrupt Flag"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 4 - MC Interrupt Flag 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - MC Interrupt Flag 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/tc0/count16/status.rs b/pac/atsamc20j/src/tc0/count16/status.rs new file mode 100644 index 000000000000..5088af446830 --- /dev/null +++ b/pac/atsamc20j/src/tc0/count16/status.rs @@ -0,0 +1,301 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `STOP` reader - Stop Status Flag"] +pub struct STOP_R(crate::FieldReader); +impl STOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STOP` writer - Stop Status Flag"] +pub struct STOP_W<'a> { + w: &'a mut W, +} +impl<'a> STOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SLAVE` reader - Slave Status Flag"] +pub struct SLAVE_R(crate::FieldReader); +impl SLAVE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLAVE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SLAVE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLAVE` writer - Slave Status Flag"] +pub struct SLAVE_W<'a> { + w: &'a mut W, +} +impl<'a> SLAVE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PERBUFV` reader - Synchronization Busy Status"] +pub struct PERBUFV_R(crate::FieldReader); +impl PERBUFV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PERBUFV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERBUFV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERBUFV` writer - Synchronization Busy Status"] +pub struct PERBUFV_W<'a> { + w: &'a mut W, +} +impl<'a> PERBUFV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CCBUFV0` reader - Compare channel buffer 0 valid"] +pub struct CCBUFV0_R(crate::FieldReader); +impl CCBUFV0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBUFV0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUFV0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUFV0` writer - Compare channel buffer 0 valid"] +pub struct CCBUFV0_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUFV0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `CCBUFV1` reader - Compare channel buffer 1 valid"] +pub struct CCBUFV1_R(crate::FieldReader); +impl CCBUFV1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBUFV1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUFV1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUFV1` writer - Compare channel buffer 1 valid"] +pub struct CCBUFV1_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUFV1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Stop Status Flag"] + #[inline(always)] + pub fn stop(&self) -> STOP_R { + STOP_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Slave Status Flag"] + #[inline(always)] + pub fn slave(&self) -> SLAVE_R { + SLAVE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 3 - Synchronization Busy Status"] + #[inline(always)] + pub fn perbufv(&self) -> PERBUFV_R { + PERBUFV_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Compare channel buffer 0 valid"] + #[inline(always)] + pub fn ccbufv0(&self) -> CCBUFV0_R { + CCBUFV0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Compare channel buffer 1 valid"] + #[inline(always)] + pub fn ccbufv1(&self) -> CCBUFV1_R { + CCBUFV1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Stop Status Flag"] + #[inline(always)] + pub fn stop(&mut self) -> STOP_W { + STOP_W { w: self } + } + #[doc = "Bit 1 - Slave Status Flag"] + #[inline(always)] + pub fn slave(&mut self) -> SLAVE_W { + SLAVE_W { w: self } + } + #[doc = "Bit 3 - Synchronization Busy Status"] + #[inline(always)] + pub fn perbufv(&mut self) -> PERBUFV_W { + PERBUFV_W { w: self } + } + #[doc = "Bit 4 - Compare channel buffer 0 valid"] + #[inline(always)] + pub fn ccbufv0(&mut self) -> CCBUFV0_W { + CCBUFV0_W { w: self } + } + #[doc = "Bit 5 - Compare channel buffer 1 valid"] + #[inline(always)] + pub fn ccbufv1(&mut self) -> CCBUFV1_W { + CCBUFV1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0x01"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pac/atsamc20j/src/tc0/count16/syncbusy.rs b/pac/atsamc20j/src/tc0/count16/syncbusy.rs new file mode 100644 index 000000000000..7ad8d91a84de --- /dev/null +++ b/pac/atsamc20j/src/tc0/count16/syncbusy.rs @@ -0,0 +1,193 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - swrst"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLB` reader - CTRLB"] +pub struct CTRLB_R(crate::FieldReader); +impl CTRLB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STATUS` reader - STATUS"] +pub struct STATUS_R(crate::FieldReader); +impl STATUS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STATUS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STATUS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` reader - Counter"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` reader - Period"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC0` reader - Compare Channel 0"] +pub struct CC0_R(crate::FieldReader); +impl CC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC1` reader - Compare Channel 1"] +pub struct CC1_R(crate::FieldReader); +impl CC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - swrst"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - CTRLB"] + #[inline(always)] + pub fn ctrlb(&self) -> CTRLB_R { + CTRLB_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - STATUS"] + #[inline(always)] + pub fn status(&self) -> STATUS_R { + STATUS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Counter"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Period"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Compare Channel 0"] + #[inline(always)] + pub fn cc0(&self) -> CC0_R { + CC0_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Compare Channel 1"] + #[inline(always)] + pub fn cc1(&self) -> CC1_R { + CC1_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +#[doc = "Synchronization Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/tc0/count16/wave.rs b/pac/atsamc20j/src/tc0/count16/wave.rs new file mode 100644 index 000000000000..46061b24b75d --- /dev/null +++ b/pac/atsamc20j/src/tc0/count16/wave.rs @@ -0,0 +1,178 @@ +#[doc = "Register `WAVE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WAVE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Waveform Generation Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WAVEGEN_A { + #[doc = "0: Normal frequency"] + NFRQ = 0, + #[doc = "1: Match frequency"] + MFRQ = 1, + #[doc = "2: Normal PWM"] + NPWM = 2, + #[doc = "3: Match PWM"] + MPWM = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WAVEGEN_A) -> Self { + variant as _ + } +} +#[doc = "Field `WAVEGEN` reader - Waveform Generation Mode"] +pub struct WAVEGEN_R(crate::FieldReader); +impl WAVEGEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WAVEGEN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> WAVEGEN_A { + match self.bits { + 0 => WAVEGEN_A::NFRQ, + 1 => WAVEGEN_A::MFRQ, + 2 => WAVEGEN_A::NPWM, + 3 => WAVEGEN_A::MPWM, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NFRQ`"] + #[inline(always)] + pub fn is_nfrq(&self) -> bool { + **self == WAVEGEN_A::NFRQ + } + #[doc = "Checks if the value of the field is `MFRQ`"] + #[inline(always)] + pub fn is_mfrq(&self) -> bool { + **self == WAVEGEN_A::MFRQ + } + #[doc = "Checks if the value of the field is `NPWM`"] + #[inline(always)] + pub fn is_npwm(&self) -> bool { + **self == WAVEGEN_A::NPWM + } + #[doc = "Checks if the value of the field is `MPWM`"] + #[inline(always)] + pub fn is_mpwm(&self) -> bool { + **self == WAVEGEN_A::MPWM + } +} +impl core::ops::Deref for WAVEGEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAVEGEN` writer - Waveform Generation Mode"] +pub struct WAVEGEN_W<'a> { + w: &'a mut W, +} +impl<'a> WAVEGEN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WAVEGEN_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Normal frequency"] + #[inline(always)] + pub fn nfrq(self) -> &'a mut W { + self.variant(WAVEGEN_A::NFRQ) + } + #[doc = "Match frequency"] + #[inline(always)] + pub fn mfrq(self) -> &'a mut W { + self.variant(WAVEGEN_A::MFRQ) + } + #[doc = "Normal PWM"] + #[inline(always)] + pub fn npwm(self) -> &'a mut W { + self.variant(WAVEGEN_A::NPWM) + } + #[doc = "Match PWM"] + #[inline(always)] + pub fn mpwm(self) -> &'a mut W { + self.variant(WAVEGEN_A::MPWM) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u8 & 0x03); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Waveform Generation Mode"] + #[inline(always)] + pub fn wavegen(&self) -> WAVEGEN_R { + WAVEGEN_R::new((self.bits & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Waveform Generation Mode"] + #[inline(always)] + pub fn wavegen(&mut self) -> WAVEGEN_W { + WAVEGEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Waveform Generation Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wave](index.html) module"] +pub struct WAVE_SPEC; +impl crate::RegisterSpec for WAVE_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [wave::R](R) reader structure"] +impl crate::Readable for WAVE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wave::W](W) writer structure"] +impl crate::Writable for WAVE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WAVE to value 0"] +impl crate::Resettable for WAVE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/tc0/count32.rs b/pac/atsamc20j/src/tc0/count32.rs new file mode 100644 index 000000000000..9062acfbbd7f --- /dev/null +++ b/pac/atsamc20j/src/tc0/count32.rs @@ -0,0 +1,60 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "CTRLBCLR register accessor: an alias for `Reg`"] +pub type CTRLBCLR = crate::Reg; +#[doc = "Control B Clear"] +pub mod ctrlbclr; +#[doc = "CTRLBSET register accessor: an alias for `Reg`"] +pub type CTRLBSET = crate::Reg; +#[doc = "Control B Set"] +pub mod ctrlbset; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "WAVE register accessor: an alias for `Reg`"] +pub type WAVE = crate::Reg; +#[doc = "Waveform Generation Control"] +pub mod wave; +#[doc = "DRVCTRL register accessor: an alias for `Reg`"] +pub type DRVCTRL = crate::Reg; +#[doc = "Control C"] +pub mod drvctrl; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Status"] +pub mod syncbusy; +#[doc = "COUNT register accessor: an alias for `Reg`"] +pub type COUNT = crate::Reg; +#[doc = "COUNT32 Count"] +pub mod count; +#[doc = "CC register accessor: an alias for `Reg`"] +pub type CC = crate::Reg; +#[doc = "COUNT32 Compare and Capture"] +pub mod cc; +#[doc = "CCBUF register accessor: an alias for `Reg`"] +pub type CCBUF = crate::Reg; +#[doc = "COUNT32 Compare and Capture Buffer"] +pub mod ccbuf; diff --git a/pac/atsamc20j/src/tc0/count32/cc.rs b/pac/atsamc20j/src/tc0/count32/cc.rs new file mode 100644 index 000000000000..512a1e01ffd4 --- /dev/null +++ b/pac/atsamc20j/src/tc0/count32/cc.rs @@ -0,0 +1,104 @@ +#[doc = "Register `CC[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CC[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CC` reader - Counter/Compare Value"] +pub struct CC_R(crate::FieldReader); +impl CC_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC` writer - Counter/Compare Value"] +pub struct CC_W<'a> { + w: &'a mut W, +} +impl<'a> CC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Counter/Compare Value"] + #[inline(always)] + pub fn cc(&self) -> CC_R { + CC_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Counter/Compare Value"] + #[inline(always)] + pub fn cc(&mut self) -> CC_W { + CC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT32 Compare and Capture\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc](index.html) module"] +pub struct CC_SPEC; +impl crate::RegisterSpec for CC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cc::R](R) reader structure"] +impl crate::Readable for CC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cc::W](W) writer structure"] +impl crate::Writable for CC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CC[%s] +to value 0"] +impl crate::Resettable for CC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/tc0/count32/ccbuf.rs b/pac/atsamc20j/src/tc0/count32/ccbuf.rs new file mode 100644 index 000000000000..9fb2d9f8f66c --- /dev/null +++ b/pac/atsamc20j/src/tc0/count32/ccbuf.rs @@ -0,0 +1,104 @@ +#[doc = "Register `CCBUF[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CCBUF[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CCBUF` reader - Counter/Compare Buffer Value"] +pub struct CCBUF_R(crate::FieldReader); +impl CCBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CCBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUF` writer - Counter/Compare Buffer Value"] +pub struct CCBUF_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Counter/Compare Buffer Value"] + #[inline(always)] + pub fn ccbuf(&self) -> CCBUF_R { + CCBUF_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Counter/Compare Buffer Value"] + #[inline(always)] + pub fn ccbuf(&mut self) -> CCBUF_W { + CCBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT32 Compare and Capture Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccbuf](index.html) module"] +pub struct CCBUF_SPEC; +impl crate::RegisterSpec for CCBUF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ccbuf::R](R) reader structure"] +impl crate::Readable for CCBUF_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ccbuf::W](W) writer structure"] +impl crate::Writable for CCBUF_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CCBUF[%s] +to value 0"] +impl crate::Resettable for CCBUF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/tc0/count32/count.rs b/pac/atsamc20j/src/tc0/count32/count.rs new file mode 100644 index 000000000000..9aea527a8b3c --- /dev/null +++ b/pac/atsamc20j/src/tc0/count32/count.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT32 Count\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count](index.html) module"] +pub struct COUNT_SPEC; +impl crate::RegisterSpec for COUNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [count::R](R) reader structure"] +impl crate::Readable for COUNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count::W](W) writer structure"] +impl crate::Writable for COUNT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT to value 0"] +impl crate::Resettable for COUNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/tc0/count32/ctrla.rs b/pac/atsamc20j/src/tc0/count32/ctrla.rs new file mode 100644 index 000000000000..cadcddaaead8 --- /dev/null +++ b/pac/atsamc20j/src/tc0/count32/ctrla.rs @@ -0,0 +1,851 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Timer Counter Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: Counter in 16-bit mode"] + COUNT16 = 0, + #[doc = "1: Counter in 8-bit mode"] + COUNT8 = 1, + #[doc = "2: Counter in 32-bit mode"] + COUNT32 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Timer Counter Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::COUNT16), + 1 => Some(MODE_A::COUNT8), + 2 => Some(MODE_A::COUNT32), + _ => None, + } + } + #[doc = "Checks if the value of the field is `COUNT16`"] + #[inline(always)] + pub fn is_count16(&self) -> bool { + **self == MODE_A::COUNT16 + } + #[doc = "Checks if the value of the field is `COUNT8`"] + #[inline(always)] + pub fn is_count8(&self) -> bool { + **self == MODE_A::COUNT8 + } + #[doc = "Checks if the value of the field is `COUNT32`"] + #[inline(always)] + pub fn is_count32(&self) -> bool { + **self == MODE_A::COUNT32 + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Timer Counter Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Counter in 16-bit mode"] + #[inline(always)] + pub fn count16(self) -> &'a mut W { + self.variant(MODE_A::COUNT16) + } + #[doc = "Counter in 8-bit mode"] + #[inline(always)] + pub fn count8(self) -> &'a mut W { + self.variant(MODE_A::COUNT8) + } + #[doc = "Counter in 32-bit mode"] + #[inline(always)] + pub fn count32(self) -> &'a mut W { + self.variant(MODE_A::COUNT32) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u32 & 0x03) << 2); + self.w + } +} +#[doc = "Prescaler and Counter Synchronization\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCSYNC_A { + #[doc = "0: Reload or reset the counter on next generic clock"] + GCLK = 0, + #[doc = "1: Reload or reset the counter on next prescaler clock"] + PRESC = 1, + #[doc = "2: Reload or reset the counter on next generic clock and reset the prescaler counter"] + RESYNC = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCSYNC_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCSYNC` reader - Prescaler and Counter Synchronization"] +pub struct PRESCSYNC_R(crate::FieldReader); +impl PRESCSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCSYNC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCSYNC_A::GCLK), + 1 => Some(PRESCSYNC_A::PRESC), + 2 => Some(PRESCSYNC_A::RESYNC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `GCLK`"] + #[inline(always)] + pub fn is_gclk(&self) -> bool { + **self == PRESCSYNC_A::GCLK + } + #[doc = "Checks if the value of the field is `PRESC`"] + #[inline(always)] + pub fn is_presc(&self) -> bool { + **self == PRESCSYNC_A::PRESC + } + #[doc = "Checks if the value of the field is `RESYNC`"] + #[inline(always)] + pub fn is_resync(&self) -> bool { + **self == PRESCSYNC_A::RESYNC + } +} +impl core::ops::Deref for PRESCSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCSYNC` writer - Prescaler and Counter Synchronization"] +pub struct PRESCSYNC_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCSYNC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCSYNC_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Reload or reset the counter on next generic clock"] + #[inline(always)] + pub fn gclk(self) -> &'a mut W { + self.variant(PRESCSYNC_A::GCLK) + } + #[doc = "Reload or reset the counter on next prescaler clock"] + #[inline(always)] + pub fn presc(self) -> &'a mut W { + self.variant(PRESCSYNC_A::PRESC) + } + #[doc = "Reload or reset the counter on next generic clock and reset the prescaler counter"] + #[inline(always)] + pub fn resync(self) -> &'a mut W { + self.variant(PRESCSYNC_A::RESYNC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u32 & 0x03) << 4); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - Clock On Demand"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - Clock On Demand"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: Prescaler: GCLK_TC"] + DIV1 = 0, + #[doc = "1: Prescaler: GCLK_TC/2"] + DIV2 = 1, + #[doc = "2: Prescaler: GCLK_TC/4"] + DIV4 = 2, + #[doc = "3: Prescaler: GCLK_TC/8"] + DIV8 = 3, + #[doc = "4: Prescaler: GCLK_TC/16"] + DIV16 = 4, + #[doc = "5: Prescaler: GCLK_TC/64"] + DIV64 = 5, + #[doc = "6: Prescaler: GCLK_TC/256"] + DIV256 = 6, + #[doc = "7: Prescaler: GCLK_TC/1024"] + DIV1024 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PRESCALER_A { + match self.bits { + 0 => PRESCALER_A::DIV1, + 1 => PRESCALER_A::DIV2, + 2 => PRESCALER_A::DIV4, + 3 => PRESCALER_A::DIV8, + 4 => PRESCALER_A::DIV16, + 5 => PRESCALER_A::DIV64, + 6 => PRESCALER_A::DIV256, + 7 => PRESCALER_A::DIV1024, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == PRESCALER_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PRESCALER_A::DIV1024 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Prescaler: GCLK_TC"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1) + } + #[doc = "Prescaler: GCLK_TC/2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "Prescaler: GCLK_TC/4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "Prescaler: GCLK_TC/8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "Prescaler: GCLK_TC/16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "Prescaler: GCLK_TC/64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "Prescaler: GCLK_TC/256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = "Prescaler: GCLK_TC/1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +#[doc = "Field `ALOCK` reader - Auto Lock"] +pub struct ALOCK_R(crate::FieldReader); +impl ALOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALOCK` writer - Auto Lock"] +pub struct ALOCK_W<'a> { + w: &'a mut W, +} +impl<'a> ALOCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `CAPTEN0` reader - Capture Channel 0 Enable"] +pub struct CAPTEN0_R(crate::FieldReader); +impl CAPTEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CAPTEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CAPTEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAPTEN0` writer - Capture Channel 0 Enable"] +pub struct CAPTEN0_W<'a> { + w: &'a mut W, +} +impl<'a> CAPTEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `CAPTEN1` reader - Capture Channel 1 Enable"] +pub struct CAPTEN1_R(crate::FieldReader); +impl CAPTEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CAPTEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CAPTEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAPTEN1` writer - Capture Channel 1 Enable"] +pub struct CAPTEN1_W<'a> { + w: &'a mut W, +} +impl<'a> CAPTEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `COPEN0` reader - Capture On Pin 0 Enable"] +pub struct COPEN0_R(crate::FieldReader); +impl COPEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COPEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COPEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COPEN0` writer - Capture On Pin 0 Enable"] +pub struct COPEN0_W<'a> { + w: &'a mut W, +} +impl<'a> COPEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `COPEN1` reader - Capture On Pin 1 Enable"] +pub struct COPEN1_R(crate::FieldReader); +impl COPEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COPEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COPEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COPEN1` writer - Capture On Pin 1 Enable"] +pub struct COPEN1_W<'a> { + w: &'a mut W, +} +impl<'a> COPEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:3 - Timer Counter Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bits 4:5 - Prescaler and Counter Synchronization"] + #[inline(always)] + pub fn prescsync(&self) -> PRESCSYNC_R { + PRESCSYNC_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Clock On Demand"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 11 - Auto Lock"] + #[inline(always)] + pub fn alock(&self) -> ALOCK_R { + ALOCK_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 16 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn capten0(&self) -> CAPTEN0_R { + CAPTEN0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn capten1(&self) -> CAPTEN1_R { + CAPTEN1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 20 - Capture On Pin 0 Enable"] + #[inline(always)] + pub fn copen0(&self) -> COPEN0_R { + COPEN0_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Capture On Pin 1 Enable"] + #[inline(always)] + pub fn copen1(&self) -> COPEN1_R { + COPEN1_R::new(((self.bits >> 21) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:3 - Timer Counter Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bits 4:5 - Prescaler and Counter Synchronization"] + #[inline(always)] + pub fn prescsync(&mut self) -> PRESCSYNC_W { + PRESCSYNC_W { w: self } + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - Clock On Demand"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Bit 11 - Auto Lock"] + #[inline(always)] + pub fn alock(&mut self) -> ALOCK_W { + ALOCK_W { w: self } + } + #[doc = "Bit 16 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn capten0(&mut self) -> CAPTEN0_W { + CAPTEN0_W { w: self } + } + #[doc = "Bit 17 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn capten1(&mut self) -> CAPTEN1_W { + CAPTEN1_W { w: self } + } + #[doc = "Bit 20 - Capture On Pin 0 Enable"] + #[inline(always)] + pub fn copen0(&mut self) -> COPEN0_W { + COPEN0_W { w: self } + } + #[doc = "Bit 21 - Capture On Pin 1 Enable"] + #[inline(always)] + pub fn copen1(&mut self) -> COPEN1_W { + COPEN1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/tc0/count32/ctrlbclr.rs b/pac/atsamc20j/src/tc0/count32/ctrlbclr.rs new file mode 100644 index 000000000000..76265674036a --- /dev/null +++ b/pac/atsamc20j/src/tc0/count32/ctrlbclr.rs @@ -0,0 +1,345 @@ +#[doc = "Register `CTRLBCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Counter Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `LUPD` reader - Lock Update"] +pub struct LUPD_R(crate::FieldReader); +impl LUPD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LUPD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LUPD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LUPD` writer - Lock Update"] +pub struct LUPD_W<'a> { + w: &'a mut W, +} +impl<'a> LUPD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ONESHOT` reader - One-Shot on Counter"] +pub struct ONESHOT_R(crate::FieldReader); +impl ONESHOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONESHOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONESHOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONESHOT` writer - One-Shot on Counter"] +pub struct ONESHOT_W<'a> { + w: &'a mut W, +} +impl<'a> ONESHOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Force a start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force a stop"] + STOP = 2, + #[doc = "3: Force update of double-buffered register"] + UPDATE = 3, + #[doc = "4: Force a read synchronization of COUNT"] + READSYNC = 4, + #[doc = "5: One-shot DMA trigger"] + DMAOS = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NONE), + 1 => Some(CMD_A::RETRIGGER), + 2 => Some(CMD_A::STOP), + 3 => Some(CMD_A::UPDATE), + 4 => Some(CMD_A::READSYNC), + 5 => Some(CMD_A::DMAOS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == CMD_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == CMD_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == CMD_A::STOP + } + #[doc = "Checks if the value of the field is `UPDATE`"] + #[inline(always)] + pub fn is_update(&self) -> bool { + **self == CMD_A::UPDATE + } + #[doc = "Checks if the value of the field is `READSYNC`"] + #[inline(always)] + pub fn is_readsync(&self) -> bool { + **self == CMD_A::READSYNC + } + #[doc = "Checks if the value of the field is `DMAOS`"] + #[inline(always)] + pub fn is_dmaos(&self) -> bool { + **self == CMD_A::DMAOS + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMD_A::NONE) + } + #[doc = "Force a start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMD_A::RETRIGGER) + } + #[doc = "Force a stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMD_A::STOP) + } + #[doc = "Force update of double-buffered register"] + #[inline(always)] + pub fn update(self) -> &'a mut W { + self.variant(CMD_A::UPDATE) + } + #[doc = "Force a read synchronization of COUNT"] + #[inline(always)] + pub fn readsync(self) -> &'a mut W { + self.variant(CMD_A::READSYNC) + } + #[doc = "One-shot DMA trigger"] + #[inline(always)] + pub fn dmaos(self) -> &'a mut W { + self.variant(CMD_A::DMAOS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 5)) | ((value as u8 & 0x07) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&self) -> LUPD_R { + LUPD_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 5) & 0x07) as u8) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&mut self) -> LUPD_W { + LUPD_W { w: self } + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&mut self) -> ONESHOT_W { + ONESHOT_W { w: self } + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbclr](index.html) module"] +pub struct CTRLBCLR_SPEC; +impl crate::RegisterSpec for CTRLBCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbclr::R](R) reader structure"] +impl crate::Readable for CTRLBCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbclr::W](W) writer structure"] +impl crate::Writable for CTRLBCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLBCLR to value 0"] +impl crate::Resettable for CTRLBCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/tc0/count32/ctrlbset.rs b/pac/atsamc20j/src/tc0/count32/ctrlbset.rs new file mode 100644 index 000000000000..610914c9c7c8 --- /dev/null +++ b/pac/atsamc20j/src/tc0/count32/ctrlbset.rs @@ -0,0 +1,345 @@ +#[doc = "Register `CTRLBSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Counter Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `LUPD` reader - Lock Update"] +pub struct LUPD_R(crate::FieldReader); +impl LUPD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LUPD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LUPD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LUPD` writer - Lock Update"] +pub struct LUPD_W<'a> { + w: &'a mut W, +} +impl<'a> LUPD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ONESHOT` reader - One-Shot on Counter"] +pub struct ONESHOT_R(crate::FieldReader); +impl ONESHOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONESHOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONESHOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONESHOT` writer - One-Shot on Counter"] +pub struct ONESHOT_W<'a> { + w: &'a mut W, +} +impl<'a> ONESHOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Force a start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force a stop"] + STOP = 2, + #[doc = "3: Force update of double-buffered register"] + UPDATE = 3, + #[doc = "4: Force a read synchronization of COUNT"] + READSYNC = 4, + #[doc = "5: One-shot DMA trigger"] + DMAOS = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NONE), + 1 => Some(CMD_A::RETRIGGER), + 2 => Some(CMD_A::STOP), + 3 => Some(CMD_A::UPDATE), + 4 => Some(CMD_A::READSYNC), + 5 => Some(CMD_A::DMAOS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == CMD_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == CMD_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == CMD_A::STOP + } + #[doc = "Checks if the value of the field is `UPDATE`"] + #[inline(always)] + pub fn is_update(&self) -> bool { + **self == CMD_A::UPDATE + } + #[doc = "Checks if the value of the field is `READSYNC`"] + #[inline(always)] + pub fn is_readsync(&self) -> bool { + **self == CMD_A::READSYNC + } + #[doc = "Checks if the value of the field is `DMAOS`"] + #[inline(always)] + pub fn is_dmaos(&self) -> bool { + **self == CMD_A::DMAOS + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMD_A::NONE) + } + #[doc = "Force a start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMD_A::RETRIGGER) + } + #[doc = "Force a stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMD_A::STOP) + } + #[doc = "Force update of double-buffered register"] + #[inline(always)] + pub fn update(self) -> &'a mut W { + self.variant(CMD_A::UPDATE) + } + #[doc = "Force a read synchronization of COUNT"] + #[inline(always)] + pub fn readsync(self) -> &'a mut W { + self.variant(CMD_A::READSYNC) + } + #[doc = "One-shot DMA trigger"] + #[inline(always)] + pub fn dmaos(self) -> &'a mut W { + self.variant(CMD_A::DMAOS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 5)) | ((value as u8 & 0x07) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&self) -> LUPD_R { + LUPD_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 5) & 0x07) as u8) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&mut self) -> LUPD_W { + LUPD_W { w: self } + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&mut self) -> ONESHOT_W { + ONESHOT_W { w: self } + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbset](index.html) module"] +pub struct CTRLBSET_SPEC; +impl crate::RegisterSpec for CTRLBSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbset::R](R) reader structure"] +impl crate::Readable for CTRLBSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbset::W](W) writer structure"] +impl crate::Writable for CTRLBSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLBSET to value 0"] +impl crate::Resettable for CTRLBSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/tc0/count32/dbgctrl.rs b/pac/atsamc20j/src/tc0/count32/dbgctrl.rs new file mode 100644 index 000000000000..0383e70d0429 --- /dev/null +++ b/pac/atsamc20j/src/tc0/count32/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Run During Debug"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Run During Debug"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/tc0/count32/drvctrl.rs b/pac/atsamc20j/src/tc0/count32/drvctrl.rs new file mode 100644 index 000000000000..323926b4b22d --- /dev/null +++ b/pac/atsamc20j/src/tc0/count32/drvctrl.rs @@ -0,0 +1,160 @@ +#[doc = "Register `DRVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DRVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INVEN0` reader - Output Waveform Invert Enable 0"] +pub struct INVEN0_R(crate::FieldReader); +impl INVEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN0` writer - Output Waveform Invert Enable 0"] +pub struct INVEN0_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `INVEN1` reader - Output Waveform Invert Enable 1"] +pub struct INVEN1_R(crate::FieldReader); +impl INVEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN1` writer - Output Waveform Invert Enable 1"] +pub struct INVEN1_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - Output Waveform Invert Enable 0"] + #[inline(always)] + pub fn inven0(&self) -> INVEN0_R { + INVEN0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Output Waveform Invert Enable 1"] + #[inline(always)] + pub fn inven1(&self) -> INVEN1_R { + INVEN1_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Output Waveform Invert Enable 0"] + #[inline(always)] + pub fn inven0(&mut self) -> INVEN0_W { + INVEN0_W { w: self } + } + #[doc = "Bit 1 - Output Waveform Invert Enable 1"] + #[inline(always)] + pub fn inven1(&mut self) -> INVEN1_W { + INVEN1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control C\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [drvctrl](index.html) module"] +pub struct DRVCTRL_SPEC; +impl crate::RegisterSpec for DRVCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [drvctrl::R](R) reader structure"] +impl crate::Readable for DRVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [drvctrl::W](W) writer structure"] +impl crate::Writable for DRVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DRVCTRL to value 0"] +impl crate::Resettable for DRVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/tc0/count32/evctrl.rs b/pac/atsamc20j/src/tc0/count32/evctrl.rs new file mode 100644 index 000000000000..7d4c38d486c1 --- /dev/null +++ b/pac/atsamc20j/src/tc0/count32/evctrl.rs @@ -0,0 +1,465 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Event Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EVACT_A { + #[doc = "0: Event action disabled"] + OFF = 0, + #[doc = "1: Start, restart or retrigger TC on event"] + RETRIGGER = 1, + #[doc = "2: Count on event"] + COUNT = 2, + #[doc = "3: Start TC on event"] + START = 3, + #[doc = "4: Time stamp capture"] + STAMP = 4, + #[doc = "5: Period catured in CC0, pulse width in CC1"] + PPW = 5, + #[doc = "6: Period catured in CC1, pulse width in CC0"] + PWP = 6, + #[doc = "7: Pulse width capture"] + PW = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EVACT_A) -> Self { + variant as _ + } +} +#[doc = "Field `EVACT` reader - Event Action"] +pub struct EVACT_R(crate::FieldReader); +impl EVACT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVACT_A { + match self.bits { + 0 => EVACT_A::OFF, + 1 => EVACT_A::RETRIGGER, + 2 => EVACT_A::COUNT, + 3 => EVACT_A::START, + 4 => EVACT_A::STAMP, + 5 => EVACT_A::PPW, + 6 => EVACT_A::PWP, + 7 => EVACT_A::PW, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == EVACT_A::OFF + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == EVACT_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `COUNT`"] + #[inline(always)] + pub fn is_count(&self) -> bool { + **self == EVACT_A::COUNT + } + #[doc = "Checks if the value of the field is `START`"] + #[inline(always)] + pub fn is_start(&self) -> bool { + **self == EVACT_A::START + } + #[doc = "Checks if the value of the field is `STAMP`"] + #[inline(always)] + pub fn is_stamp(&self) -> bool { + **self == EVACT_A::STAMP + } + #[doc = "Checks if the value of the field is `PPW`"] + #[inline(always)] + pub fn is_ppw(&self) -> bool { + **self == EVACT_A::PPW + } + #[doc = "Checks if the value of the field is `PWP`"] + #[inline(always)] + pub fn is_pwp(&self) -> bool { + **self == EVACT_A::PWP + } + #[doc = "Checks if the value of the field is `PW`"] + #[inline(always)] + pub fn is_pw(&self) -> bool { + **self == EVACT_A::PW + } +} +impl core::ops::Deref for EVACT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT` writer - Event Action"] +pub struct EVACT_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EVACT_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Event action disabled"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(EVACT_A::OFF) + } + #[doc = "Start, restart or retrigger TC on event"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(EVACT_A::RETRIGGER) + } + #[doc = "Count on event"] + #[inline(always)] + pub fn count(self) -> &'a mut W { + self.variant(EVACT_A::COUNT) + } + #[doc = "Start TC on event"] + #[inline(always)] + pub fn start(self) -> &'a mut W { + self.variant(EVACT_A::START) + } + #[doc = "Time stamp capture"] + #[inline(always)] + pub fn stamp(self) -> &'a mut W { + self.variant(EVACT_A::STAMP) + } + #[doc = "Period catured in CC0, pulse width in CC1"] + #[inline(always)] + pub fn ppw(self) -> &'a mut W { + self.variant(EVACT_A::PPW) + } + #[doc = "Period catured in CC1, pulse width in CC0"] + #[inline(always)] + pub fn pwp(self) -> &'a mut W { + self.variant(EVACT_A::PWP) + } + #[doc = "Pulse width capture"] + #[inline(always)] + pub fn pw(self) -> &'a mut W { + self.variant(EVACT_A::PW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u16 & 0x07); + self.w + } +} +#[doc = "Field `TCINV` reader - TC Event Input Polarity"] +pub struct TCINV_R(crate::FieldReader); +impl TCINV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCINV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCINV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCINV` writer - TC Event Input Polarity"] +pub struct TCINV_W<'a> { + w: &'a mut W, +} +impl<'a> TCINV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `TCEI` reader - TC Event Enable"] +pub struct TCEI_R(crate::FieldReader); +impl TCEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCEI` writer - TC Event Enable"] +pub struct TCEI_W<'a> { + w: &'a mut W, +} +impl<'a> TCEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `OVFEO` reader - Event Output Enable"] +pub struct OVFEO_R(crate::FieldReader); +impl OVFEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVFEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVFEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVFEO` writer - Event Output Enable"] +pub struct OVFEO_W<'a> { + w: &'a mut W, +} +impl<'a> OVFEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `MCEO0` reader - MC Event Output Enable 0"] +pub struct MCEO0_R(crate::FieldReader); +impl MCEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO0` writer - MC Event Output Enable 0"] +pub struct MCEO0_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u16 & 0x01) << 12); + self.w + } +} +#[doc = "Field `MCEO1` reader - MC Event Output Enable 1"] +pub struct MCEO1_R(crate::FieldReader); +impl MCEO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO1` writer - MC Event Output Enable 1"] +pub struct MCEO1_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u16 & 0x01) << 13); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Event Action"] + #[inline(always)] + pub fn evact(&self) -> EVACT_R { + EVACT_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 4 - TC Event Input Polarity"] + #[inline(always)] + pub fn tcinv(&self) -> TCINV_R { + TCINV_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - TC Event Enable"] + #[inline(always)] + pub fn tcei(&self) -> TCEI_R { + TCEI_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 8 - Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&self) -> OVFEO_R { + OVFEO_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 12 - MC Event Output Enable 0"] + #[inline(always)] + pub fn mceo0(&self) -> MCEO0_R { + MCEO0_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - MC Event Output Enable 1"] + #[inline(always)] + pub fn mceo1(&self) -> MCEO1_R { + MCEO1_R::new(((self.bits >> 13) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Event Action"] + #[inline(always)] + pub fn evact(&mut self) -> EVACT_W { + EVACT_W { w: self } + } + #[doc = "Bit 4 - TC Event Input Polarity"] + #[inline(always)] + pub fn tcinv(&mut self) -> TCINV_W { + TCINV_W { w: self } + } + #[doc = "Bit 5 - TC Event Enable"] + #[inline(always)] + pub fn tcei(&mut self) -> TCEI_W { + TCEI_W { w: self } + } + #[doc = "Bit 8 - Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&mut self) -> OVFEO_W { + OVFEO_W { w: self } + } + #[doc = "Bit 12 - MC Event Output Enable 0"] + #[inline(always)] + pub fn mceo0(&mut self) -> MCEO0_W { + MCEO0_W { w: self } + } + #[doc = "Bit 13 - MC Event Output Enable 1"] + #[inline(always)] + pub fn mceo1(&mut self) -> MCEO1_W { + MCEO1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/tc0/count32/intenclr.rs b/pac/atsamc20j/src/tc0/count32/intenclr.rs new file mode 100644 index 000000000000..af01ef5b7dca --- /dev/null +++ b/pac/atsamc20j/src/tc0/count32/intenclr.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - OVF Interrupt Disable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - OVF Interrupt Disable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - ERR Interrupt Disable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - ERR Interrupt Disable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MC0` reader - MC Interrupt Disable 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - MC Interrupt Disable 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - MC Interrupt Disable 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - MC Interrupt Disable 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - OVF Interrupt Disable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ERR Interrupt Disable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - MC Interrupt Disable 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - MC Interrupt Disable 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - OVF Interrupt Disable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - ERR Interrupt Disable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 4 - MC Interrupt Disable 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - MC Interrupt Disable 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/tc0/count32/intenset.rs b/pac/atsamc20j/src/tc0/count32/intenset.rs new file mode 100644 index 000000000000..0e1883a2f20a --- /dev/null +++ b/pac/atsamc20j/src/tc0/count32/intenset.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - OVF Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - OVF Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - ERR Interrupt Enable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - ERR Interrupt Enable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MC0` reader - MC Interrupt Enable 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - MC Interrupt Enable 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - MC Interrupt Enable 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - MC Interrupt Enable 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - OVF Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ERR Interrupt Enable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - MC Interrupt Enable 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - MC Interrupt Enable 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - OVF Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - ERR Interrupt Enable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 4 - MC Interrupt Enable 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - MC Interrupt Enable 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/tc0/count32/intflag.rs b/pac/atsamc20j/src/tc0/count32/intflag.rs new file mode 100644 index 000000000000..1dddffaf8e7f --- /dev/null +++ b/pac/atsamc20j/src/tc0/count32/intflag.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - OVF Interrupt Flag"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - OVF Interrupt Flag"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - ERR Interrupt Flag"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - ERR Interrupt Flag"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MC0` reader - MC Interrupt Flag 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - MC Interrupt Flag 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - MC Interrupt Flag 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - MC Interrupt Flag 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - OVF Interrupt Flag"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ERR Interrupt Flag"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - MC Interrupt Flag 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - MC Interrupt Flag 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - OVF Interrupt Flag"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - ERR Interrupt Flag"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 4 - MC Interrupt Flag 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - MC Interrupt Flag 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/tc0/count32/status.rs b/pac/atsamc20j/src/tc0/count32/status.rs new file mode 100644 index 000000000000..5088af446830 --- /dev/null +++ b/pac/atsamc20j/src/tc0/count32/status.rs @@ -0,0 +1,301 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `STOP` reader - Stop Status Flag"] +pub struct STOP_R(crate::FieldReader); +impl STOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STOP` writer - Stop Status Flag"] +pub struct STOP_W<'a> { + w: &'a mut W, +} +impl<'a> STOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SLAVE` reader - Slave Status Flag"] +pub struct SLAVE_R(crate::FieldReader); +impl SLAVE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLAVE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SLAVE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLAVE` writer - Slave Status Flag"] +pub struct SLAVE_W<'a> { + w: &'a mut W, +} +impl<'a> SLAVE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PERBUFV` reader - Synchronization Busy Status"] +pub struct PERBUFV_R(crate::FieldReader); +impl PERBUFV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PERBUFV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERBUFV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERBUFV` writer - Synchronization Busy Status"] +pub struct PERBUFV_W<'a> { + w: &'a mut W, +} +impl<'a> PERBUFV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CCBUFV0` reader - Compare channel buffer 0 valid"] +pub struct CCBUFV0_R(crate::FieldReader); +impl CCBUFV0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBUFV0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUFV0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUFV0` writer - Compare channel buffer 0 valid"] +pub struct CCBUFV0_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUFV0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `CCBUFV1` reader - Compare channel buffer 1 valid"] +pub struct CCBUFV1_R(crate::FieldReader); +impl CCBUFV1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBUFV1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUFV1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUFV1` writer - Compare channel buffer 1 valid"] +pub struct CCBUFV1_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUFV1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Stop Status Flag"] + #[inline(always)] + pub fn stop(&self) -> STOP_R { + STOP_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Slave Status Flag"] + #[inline(always)] + pub fn slave(&self) -> SLAVE_R { + SLAVE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 3 - Synchronization Busy Status"] + #[inline(always)] + pub fn perbufv(&self) -> PERBUFV_R { + PERBUFV_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Compare channel buffer 0 valid"] + #[inline(always)] + pub fn ccbufv0(&self) -> CCBUFV0_R { + CCBUFV0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Compare channel buffer 1 valid"] + #[inline(always)] + pub fn ccbufv1(&self) -> CCBUFV1_R { + CCBUFV1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Stop Status Flag"] + #[inline(always)] + pub fn stop(&mut self) -> STOP_W { + STOP_W { w: self } + } + #[doc = "Bit 1 - Slave Status Flag"] + #[inline(always)] + pub fn slave(&mut self) -> SLAVE_W { + SLAVE_W { w: self } + } + #[doc = "Bit 3 - Synchronization Busy Status"] + #[inline(always)] + pub fn perbufv(&mut self) -> PERBUFV_W { + PERBUFV_W { w: self } + } + #[doc = "Bit 4 - Compare channel buffer 0 valid"] + #[inline(always)] + pub fn ccbufv0(&mut self) -> CCBUFV0_W { + CCBUFV0_W { w: self } + } + #[doc = "Bit 5 - Compare channel buffer 1 valid"] + #[inline(always)] + pub fn ccbufv1(&mut self) -> CCBUFV1_W { + CCBUFV1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0x01"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pac/atsamc20j/src/tc0/count32/syncbusy.rs b/pac/atsamc20j/src/tc0/count32/syncbusy.rs new file mode 100644 index 000000000000..7ad8d91a84de --- /dev/null +++ b/pac/atsamc20j/src/tc0/count32/syncbusy.rs @@ -0,0 +1,193 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - swrst"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLB` reader - CTRLB"] +pub struct CTRLB_R(crate::FieldReader); +impl CTRLB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STATUS` reader - STATUS"] +pub struct STATUS_R(crate::FieldReader); +impl STATUS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STATUS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STATUS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` reader - Counter"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` reader - Period"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC0` reader - Compare Channel 0"] +pub struct CC0_R(crate::FieldReader); +impl CC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC1` reader - Compare Channel 1"] +pub struct CC1_R(crate::FieldReader); +impl CC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - swrst"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - CTRLB"] + #[inline(always)] + pub fn ctrlb(&self) -> CTRLB_R { + CTRLB_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - STATUS"] + #[inline(always)] + pub fn status(&self) -> STATUS_R { + STATUS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Counter"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Period"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Compare Channel 0"] + #[inline(always)] + pub fn cc0(&self) -> CC0_R { + CC0_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Compare Channel 1"] + #[inline(always)] + pub fn cc1(&self) -> CC1_R { + CC1_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +#[doc = "Synchronization Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/tc0/count32/wave.rs b/pac/atsamc20j/src/tc0/count32/wave.rs new file mode 100644 index 000000000000..46061b24b75d --- /dev/null +++ b/pac/atsamc20j/src/tc0/count32/wave.rs @@ -0,0 +1,178 @@ +#[doc = "Register `WAVE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WAVE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Waveform Generation Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WAVEGEN_A { + #[doc = "0: Normal frequency"] + NFRQ = 0, + #[doc = "1: Match frequency"] + MFRQ = 1, + #[doc = "2: Normal PWM"] + NPWM = 2, + #[doc = "3: Match PWM"] + MPWM = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WAVEGEN_A) -> Self { + variant as _ + } +} +#[doc = "Field `WAVEGEN` reader - Waveform Generation Mode"] +pub struct WAVEGEN_R(crate::FieldReader); +impl WAVEGEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WAVEGEN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> WAVEGEN_A { + match self.bits { + 0 => WAVEGEN_A::NFRQ, + 1 => WAVEGEN_A::MFRQ, + 2 => WAVEGEN_A::NPWM, + 3 => WAVEGEN_A::MPWM, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NFRQ`"] + #[inline(always)] + pub fn is_nfrq(&self) -> bool { + **self == WAVEGEN_A::NFRQ + } + #[doc = "Checks if the value of the field is `MFRQ`"] + #[inline(always)] + pub fn is_mfrq(&self) -> bool { + **self == WAVEGEN_A::MFRQ + } + #[doc = "Checks if the value of the field is `NPWM`"] + #[inline(always)] + pub fn is_npwm(&self) -> bool { + **self == WAVEGEN_A::NPWM + } + #[doc = "Checks if the value of the field is `MPWM`"] + #[inline(always)] + pub fn is_mpwm(&self) -> bool { + **self == WAVEGEN_A::MPWM + } +} +impl core::ops::Deref for WAVEGEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAVEGEN` writer - Waveform Generation Mode"] +pub struct WAVEGEN_W<'a> { + w: &'a mut W, +} +impl<'a> WAVEGEN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WAVEGEN_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Normal frequency"] + #[inline(always)] + pub fn nfrq(self) -> &'a mut W { + self.variant(WAVEGEN_A::NFRQ) + } + #[doc = "Match frequency"] + #[inline(always)] + pub fn mfrq(self) -> &'a mut W { + self.variant(WAVEGEN_A::MFRQ) + } + #[doc = "Normal PWM"] + #[inline(always)] + pub fn npwm(self) -> &'a mut W { + self.variant(WAVEGEN_A::NPWM) + } + #[doc = "Match PWM"] + #[inline(always)] + pub fn mpwm(self) -> &'a mut W { + self.variant(WAVEGEN_A::MPWM) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u8 & 0x03); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Waveform Generation Mode"] + #[inline(always)] + pub fn wavegen(&self) -> WAVEGEN_R { + WAVEGEN_R::new((self.bits & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Waveform Generation Mode"] + #[inline(always)] + pub fn wavegen(&mut self) -> WAVEGEN_W { + WAVEGEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Waveform Generation Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wave](index.html) module"] +pub struct WAVE_SPEC; +impl crate::RegisterSpec for WAVE_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [wave::R](R) reader structure"] +impl crate::Readable for WAVE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wave::W](W) writer structure"] +impl crate::Writable for WAVE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WAVE to value 0"] +impl crate::Resettable for WAVE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/tc0/count8.rs b/pac/atsamc20j/src/tc0/count8.rs new file mode 100644 index 000000000000..777da5744358 --- /dev/null +++ b/pac/atsamc20j/src/tc0/count8.rs @@ -0,0 +1,68 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "CTRLBCLR register accessor: an alias for `Reg`"] +pub type CTRLBCLR = crate::Reg; +#[doc = "Control B Clear"] +pub mod ctrlbclr; +#[doc = "CTRLBSET register accessor: an alias for `Reg`"] +pub type CTRLBSET = crate::Reg; +#[doc = "Control B Set"] +pub mod ctrlbset; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "WAVE register accessor: an alias for `Reg`"] +pub type WAVE = crate::Reg; +#[doc = "Waveform Generation Control"] +pub mod wave; +#[doc = "DRVCTRL register accessor: an alias for `Reg`"] +pub type DRVCTRL = crate::Reg; +#[doc = "Control C"] +pub mod drvctrl; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Status"] +pub mod syncbusy; +#[doc = "COUNT register accessor: an alias for `Reg`"] +pub type COUNT = crate::Reg; +#[doc = "COUNT8 Count"] +pub mod count; +#[doc = "PER register accessor: an alias for `Reg`"] +pub type PER = crate::Reg; +#[doc = "COUNT8 Period"] +pub mod per; +#[doc = "CC register accessor: an alias for `Reg`"] +pub type CC = crate::Reg; +#[doc = "COUNT8 Compare and Capture"] +pub mod cc; +#[doc = "PERBUF register accessor: an alias for `Reg`"] +pub type PERBUF = crate::Reg; +#[doc = "COUNT8 Period Buffer"] +pub mod perbuf; +#[doc = "CCBUF register accessor: an alias for `Reg`"] +pub type CCBUF = crate::Reg; +#[doc = "COUNT8 Compare and Capture Buffer"] +pub mod ccbuf; diff --git a/pac/atsamc20j/src/tc0/count8/cc.rs b/pac/atsamc20j/src/tc0/count8/cc.rs new file mode 100644 index 000000000000..45f5c29c89af --- /dev/null +++ b/pac/atsamc20j/src/tc0/count8/cc.rs @@ -0,0 +1,104 @@ +#[doc = "Register `CC[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CC[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CC` reader - Counter/Compare Value"] +pub struct CC_R(crate::FieldReader); +impl CC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC` writer - Counter/Compare Value"] +pub struct CC_W<'a> { + w: &'a mut W, +} +impl<'a> CC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Counter/Compare Value"] + #[inline(always)] + pub fn cc(&self) -> CC_R { + CC_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Counter/Compare Value"] + #[inline(always)] + pub fn cc(&mut self) -> CC_W { + CC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT8 Compare and Capture\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc](index.html) module"] +pub struct CC_SPEC; +impl crate::RegisterSpec for CC_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [cc::R](R) reader structure"] +impl crate::Readable for CC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cc::W](W) writer structure"] +impl crate::Writable for CC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CC[%s] +to value 0"] +impl crate::Resettable for CC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/tc0/count8/ccbuf.rs b/pac/atsamc20j/src/tc0/count8/ccbuf.rs new file mode 100644 index 000000000000..cd81b1219860 --- /dev/null +++ b/pac/atsamc20j/src/tc0/count8/ccbuf.rs @@ -0,0 +1,104 @@ +#[doc = "Register `CCBUF[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CCBUF[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CCBUF` reader - Counter/Compare Buffer Value"] +pub struct CCBUF_R(crate::FieldReader); +impl CCBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CCBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUF` writer - Counter/Compare Buffer Value"] +pub struct CCBUF_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Counter/Compare Buffer Value"] + #[inline(always)] + pub fn ccbuf(&self) -> CCBUF_R { + CCBUF_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Counter/Compare Buffer Value"] + #[inline(always)] + pub fn ccbuf(&mut self) -> CCBUF_W { + CCBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT8 Compare and Capture Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccbuf](index.html) module"] +pub struct CCBUF_SPEC; +impl crate::RegisterSpec for CCBUF_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ccbuf::R](R) reader structure"] +impl crate::Readable for CCBUF_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ccbuf::W](W) writer structure"] +impl crate::Writable for CCBUF_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CCBUF[%s] +to value 0"] +impl crate::Resettable for CCBUF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/tc0/count8/count.rs b/pac/atsamc20j/src/tc0/count8/count.rs new file mode 100644 index 000000000000..0edbb0f17bb7 --- /dev/null +++ b/pac/atsamc20j/src/tc0/count8/count.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT8 Count\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count](index.html) module"] +pub struct COUNT_SPEC; +impl crate::RegisterSpec for COUNT_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [count::R](R) reader structure"] +impl crate::Readable for COUNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count::W](W) writer structure"] +impl crate::Writable for COUNT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT to value 0"] +impl crate::Resettable for COUNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/tc0/count8/ctrla.rs b/pac/atsamc20j/src/tc0/count8/ctrla.rs new file mode 100644 index 000000000000..cadcddaaead8 --- /dev/null +++ b/pac/atsamc20j/src/tc0/count8/ctrla.rs @@ -0,0 +1,851 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Timer Counter Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: Counter in 16-bit mode"] + COUNT16 = 0, + #[doc = "1: Counter in 8-bit mode"] + COUNT8 = 1, + #[doc = "2: Counter in 32-bit mode"] + COUNT32 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Timer Counter Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::COUNT16), + 1 => Some(MODE_A::COUNT8), + 2 => Some(MODE_A::COUNT32), + _ => None, + } + } + #[doc = "Checks if the value of the field is `COUNT16`"] + #[inline(always)] + pub fn is_count16(&self) -> bool { + **self == MODE_A::COUNT16 + } + #[doc = "Checks if the value of the field is `COUNT8`"] + #[inline(always)] + pub fn is_count8(&self) -> bool { + **self == MODE_A::COUNT8 + } + #[doc = "Checks if the value of the field is `COUNT32`"] + #[inline(always)] + pub fn is_count32(&self) -> bool { + **self == MODE_A::COUNT32 + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Timer Counter Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Counter in 16-bit mode"] + #[inline(always)] + pub fn count16(self) -> &'a mut W { + self.variant(MODE_A::COUNT16) + } + #[doc = "Counter in 8-bit mode"] + #[inline(always)] + pub fn count8(self) -> &'a mut W { + self.variant(MODE_A::COUNT8) + } + #[doc = "Counter in 32-bit mode"] + #[inline(always)] + pub fn count32(self) -> &'a mut W { + self.variant(MODE_A::COUNT32) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u32 & 0x03) << 2); + self.w + } +} +#[doc = "Prescaler and Counter Synchronization\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCSYNC_A { + #[doc = "0: Reload or reset the counter on next generic clock"] + GCLK = 0, + #[doc = "1: Reload or reset the counter on next prescaler clock"] + PRESC = 1, + #[doc = "2: Reload or reset the counter on next generic clock and reset the prescaler counter"] + RESYNC = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCSYNC_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCSYNC` reader - Prescaler and Counter Synchronization"] +pub struct PRESCSYNC_R(crate::FieldReader); +impl PRESCSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCSYNC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCSYNC_A::GCLK), + 1 => Some(PRESCSYNC_A::PRESC), + 2 => Some(PRESCSYNC_A::RESYNC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `GCLK`"] + #[inline(always)] + pub fn is_gclk(&self) -> bool { + **self == PRESCSYNC_A::GCLK + } + #[doc = "Checks if the value of the field is `PRESC`"] + #[inline(always)] + pub fn is_presc(&self) -> bool { + **self == PRESCSYNC_A::PRESC + } + #[doc = "Checks if the value of the field is `RESYNC`"] + #[inline(always)] + pub fn is_resync(&self) -> bool { + **self == PRESCSYNC_A::RESYNC + } +} +impl core::ops::Deref for PRESCSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCSYNC` writer - Prescaler and Counter Synchronization"] +pub struct PRESCSYNC_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCSYNC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCSYNC_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Reload or reset the counter on next generic clock"] + #[inline(always)] + pub fn gclk(self) -> &'a mut W { + self.variant(PRESCSYNC_A::GCLK) + } + #[doc = "Reload or reset the counter on next prescaler clock"] + #[inline(always)] + pub fn presc(self) -> &'a mut W { + self.variant(PRESCSYNC_A::PRESC) + } + #[doc = "Reload or reset the counter on next generic clock and reset the prescaler counter"] + #[inline(always)] + pub fn resync(self) -> &'a mut W { + self.variant(PRESCSYNC_A::RESYNC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u32 & 0x03) << 4); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - Clock On Demand"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - Clock On Demand"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: Prescaler: GCLK_TC"] + DIV1 = 0, + #[doc = "1: Prescaler: GCLK_TC/2"] + DIV2 = 1, + #[doc = "2: Prescaler: GCLK_TC/4"] + DIV4 = 2, + #[doc = "3: Prescaler: GCLK_TC/8"] + DIV8 = 3, + #[doc = "4: Prescaler: GCLK_TC/16"] + DIV16 = 4, + #[doc = "5: Prescaler: GCLK_TC/64"] + DIV64 = 5, + #[doc = "6: Prescaler: GCLK_TC/256"] + DIV256 = 6, + #[doc = "7: Prescaler: GCLK_TC/1024"] + DIV1024 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PRESCALER_A { + match self.bits { + 0 => PRESCALER_A::DIV1, + 1 => PRESCALER_A::DIV2, + 2 => PRESCALER_A::DIV4, + 3 => PRESCALER_A::DIV8, + 4 => PRESCALER_A::DIV16, + 5 => PRESCALER_A::DIV64, + 6 => PRESCALER_A::DIV256, + 7 => PRESCALER_A::DIV1024, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == PRESCALER_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PRESCALER_A::DIV1024 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Prescaler: GCLK_TC"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1) + } + #[doc = "Prescaler: GCLK_TC/2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "Prescaler: GCLK_TC/4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "Prescaler: GCLK_TC/8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "Prescaler: GCLK_TC/16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "Prescaler: GCLK_TC/64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "Prescaler: GCLK_TC/256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = "Prescaler: GCLK_TC/1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +#[doc = "Field `ALOCK` reader - Auto Lock"] +pub struct ALOCK_R(crate::FieldReader); +impl ALOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALOCK` writer - Auto Lock"] +pub struct ALOCK_W<'a> { + w: &'a mut W, +} +impl<'a> ALOCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `CAPTEN0` reader - Capture Channel 0 Enable"] +pub struct CAPTEN0_R(crate::FieldReader); +impl CAPTEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CAPTEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CAPTEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAPTEN0` writer - Capture Channel 0 Enable"] +pub struct CAPTEN0_W<'a> { + w: &'a mut W, +} +impl<'a> CAPTEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `CAPTEN1` reader - Capture Channel 1 Enable"] +pub struct CAPTEN1_R(crate::FieldReader); +impl CAPTEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CAPTEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CAPTEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAPTEN1` writer - Capture Channel 1 Enable"] +pub struct CAPTEN1_W<'a> { + w: &'a mut W, +} +impl<'a> CAPTEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `COPEN0` reader - Capture On Pin 0 Enable"] +pub struct COPEN0_R(crate::FieldReader); +impl COPEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COPEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COPEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COPEN0` writer - Capture On Pin 0 Enable"] +pub struct COPEN0_W<'a> { + w: &'a mut W, +} +impl<'a> COPEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `COPEN1` reader - Capture On Pin 1 Enable"] +pub struct COPEN1_R(crate::FieldReader); +impl COPEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COPEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COPEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COPEN1` writer - Capture On Pin 1 Enable"] +pub struct COPEN1_W<'a> { + w: &'a mut W, +} +impl<'a> COPEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:3 - Timer Counter Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bits 4:5 - Prescaler and Counter Synchronization"] + #[inline(always)] + pub fn prescsync(&self) -> PRESCSYNC_R { + PRESCSYNC_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Clock On Demand"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 11 - Auto Lock"] + #[inline(always)] + pub fn alock(&self) -> ALOCK_R { + ALOCK_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 16 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn capten0(&self) -> CAPTEN0_R { + CAPTEN0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn capten1(&self) -> CAPTEN1_R { + CAPTEN1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 20 - Capture On Pin 0 Enable"] + #[inline(always)] + pub fn copen0(&self) -> COPEN0_R { + COPEN0_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Capture On Pin 1 Enable"] + #[inline(always)] + pub fn copen1(&self) -> COPEN1_R { + COPEN1_R::new(((self.bits >> 21) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:3 - Timer Counter Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bits 4:5 - Prescaler and Counter Synchronization"] + #[inline(always)] + pub fn prescsync(&mut self) -> PRESCSYNC_W { + PRESCSYNC_W { w: self } + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - Clock On Demand"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Bit 11 - Auto Lock"] + #[inline(always)] + pub fn alock(&mut self) -> ALOCK_W { + ALOCK_W { w: self } + } + #[doc = "Bit 16 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn capten0(&mut self) -> CAPTEN0_W { + CAPTEN0_W { w: self } + } + #[doc = "Bit 17 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn capten1(&mut self) -> CAPTEN1_W { + CAPTEN1_W { w: self } + } + #[doc = "Bit 20 - Capture On Pin 0 Enable"] + #[inline(always)] + pub fn copen0(&mut self) -> COPEN0_W { + COPEN0_W { w: self } + } + #[doc = "Bit 21 - Capture On Pin 1 Enable"] + #[inline(always)] + pub fn copen1(&mut self) -> COPEN1_W { + COPEN1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/tc0/count8/ctrlbclr.rs b/pac/atsamc20j/src/tc0/count8/ctrlbclr.rs new file mode 100644 index 000000000000..76265674036a --- /dev/null +++ b/pac/atsamc20j/src/tc0/count8/ctrlbclr.rs @@ -0,0 +1,345 @@ +#[doc = "Register `CTRLBCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Counter Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `LUPD` reader - Lock Update"] +pub struct LUPD_R(crate::FieldReader); +impl LUPD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LUPD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LUPD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LUPD` writer - Lock Update"] +pub struct LUPD_W<'a> { + w: &'a mut W, +} +impl<'a> LUPD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ONESHOT` reader - One-Shot on Counter"] +pub struct ONESHOT_R(crate::FieldReader); +impl ONESHOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONESHOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONESHOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONESHOT` writer - One-Shot on Counter"] +pub struct ONESHOT_W<'a> { + w: &'a mut W, +} +impl<'a> ONESHOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Force a start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force a stop"] + STOP = 2, + #[doc = "3: Force update of double-buffered register"] + UPDATE = 3, + #[doc = "4: Force a read synchronization of COUNT"] + READSYNC = 4, + #[doc = "5: One-shot DMA trigger"] + DMAOS = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NONE), + 1 => Some(CMD_A::RETRIGGER), + 2 => Some(CMD_A::STOP), + 3 => Some(CMD_A::UPDATE), + 4 => Some(CMD_A::READSYNC), + 5 => Some(CMD_A::DMAOS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == CMD_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == CMD_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == CMD_A::STOP + } + #[doc = "Checks if the value of the field is `UPDATE`"] + #[inline(always)] + pub fn is_update(&self) -> bool { + **self == CMD_A::UPDATE + } + #[doc = "Checks if the value of the field is `READSYNC`"] + #[inline(always)] + pub fn is_readsync(&self) -> bool { + **self == CMD_A::READSYNC + } + #[doc = "Checks if the value of the field is `DMAOS`"] + #[inline(always)] + pub fn is_dmaos(&self) -> bool { + **self == CMD_A::DMAOS + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMD_A::NONE) + } + #[doc = "Force a start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMD_A::RETRIGGER) + } + #[doc = "Force a stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMD_A::STOP) + } + #[doc = "Force update of double-buffered register"] + #[inline(always)] + pub fn update(self) -> &'a mut W { + self.variant(CMD_A::UPDATE) + } + #[doc = "Force a read synchronization of COUNT"] + #[inline(always)] + pub fn readsync(self) -> &'a mut W { + self.variant(CMD_A::READSYNC) + } + #[doc = "One-shot DMA trigger"] + #[inline(always)] + pub fn dmaos(self) -> &'a mut W { + self.variant(CMD_A::DMAOS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 5)) | ((value as u8 & 0x07) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&self) -> LUPD_R { + LUPD_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 5) & 0x07) as u8) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&mut self) -> LUPD_W { + LUPD_W { w: self } + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&mut self) -> ONESHOT_W { + ONESHOT_W { w: self } + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbclr](index.html) module"] +pub struct CTRLBCLR_SPEC; +impl crate::RegisterSpec for CTRLBCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbclr::R](R) reader structure"] +impl crate::Readable for CTRLBCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbclr::W](W) writer structure"] +impl crate::Writable for CTRLBCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLBCLR to value 0"] +impl crate::Resettable for CTRLBCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/tc0/count8/ctrlbset.rs b/pac/atsamc20j/src/tc0/count8/ctrlbset.rs new file mode 100644 index 000000000000..610914c9c7c8 --- /dev/null +++ b/pac/atsamc20j/src/tc0/count8/ctrlbset.rs @@ -0,0 +1,345 @@ +#[doc = "Register `CTRLBSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Counter Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `LUPD` reader - Lock Update"] +pub struct LUPD_R(crate::FieldReader); +impl LUPD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LUPD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LUPD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LUPD` writer - Lock Update"] +pub struct LUPD_W<'a> { + w: &'a mut W, +} +impl<'a> LUPD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ONESHOT` reader - One-Shot on Counter"] +pub struct ONESHOT_R(crate::FieldReader); +impl ONESHOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONESHOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONESHOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONESHOT` writer - One-Shot on Counter"] +pub struct ONESHOT_W<'a> { + w: &'a mut W, +} +impl<'a> ONESHOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Force a start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force a stop"] + STOP = 2, + #[doc = "3: Force update of double-buffered register"] + UPDATE = 3, + #[doc = "4: Force a read synchronization of COUNT"] + READSYNC = 4, + #[doc = "5: One-shot DMA trigger"] + DMAOS = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NONE), + 1 => Some(CMD_A::RETRIGGER), + 2 => Some(CMD_A::STOP), + 3 => Some(CMD_A::UPDATE), + 4 => Some(CMD_A::READSYNC), + 5 => Some(CMD_A::DMAOS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == CMD_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == CMD_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == CMD_A::STOP + } + #[doc = "Checks if the value of the field is `UPDATE`"] + #[inline(always)] + pub fn is_update(&self) -> bool { + **self == CMD_A::UPDATE + } + #[doc = "Checks if the value of the field is `READSYNC`"] + #[inline(always)] + pub fn is_readsync(&self) -> bool { + **self == CMD_A::READSYNC + } + #[doc = "Checks if the value of the field is `DMAOS`"] + #[inline(always)] + pub fn is_dmaos(&self) -> bool { + **self == CMD_A::DMAOS + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMD_A::NONE) + } + #[doc = "Force a start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMD_A::RETRIGGER) + } + #[doc = "Force a stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMD_A::STOP) + } + #[doc = "Force update of double-buffered register"] + #[inline(always)] + pub fn update(self) -> &'a mut W { + self.variant(CMD_A::UPDATE) + } + #[doc = "Force a read synchronization of COUNT"] + #[inline(always)] + pub fn readsync(self) -> &'a mut W { + self.variant(CMD_A::READSYNC) + } + #[doc = "One-shot DMA trigger"] + #[inline(always)] + pub fn dmaos(self) -> &'a mut W { + self.variant(CMD_A::DMAOS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 5)) | ((value as u8 & 0x07) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&self) -> LUPD_R { + LUPD_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 5) & 0x07) as u8) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&mut self) -> LUPD_W { + LUPD_W { w: self } + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&mut self) -> ONESHOT_W { + ONESHOT_W { w: self } + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbset](index.html) module"] +pub struct CTRLBSET_SPEC; +impl crate::RegisterSpec for CTRLBSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbset::R](R) reader structure"] +impl crate::Readable for CTRLBSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbset::W](W) writer structure"] +impl crate::Writable for CTRLBSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLBSET to value 0"] +impl crate::Resettable for CTRLBSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/tc0/count8/dbgctrl.rs b/pac/atsamc20j/src/tc0/count8/dbgctrl.rs new file mode 100644 index 000000000000..0383e70d0429 --- /dev/null +++ b/pac/atsamc20j/src/tc0/count8/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Run During Debug"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Run During Debug"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/tc0/count8/drvctrl.rs b/pac/atsamc20j/src/tc0/count8/drvctrl.rs new file mode 100644 index 000000000000..323926b4b22d --- /dev/null +++ b/pac/atsamc20j/src/tc0/count8/drvctrl.rs @@ -0,0 +1,160 @@ +#[doc = "Register `DRVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DRVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INVEN0` reader - Output Waveform Invert Enable 0"] +pub struct INVEN0_R(crate::FieldReader); +impl INVEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN0` writer - Output Waveform Invert Enable 0"] +pub struct INVEN0_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `INVEN1` reader - Output Waveform Invert Enable 1"] +pub struct INVEN1_R(crate::FieldReader); +impl INVEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN1` writer - Output Waveform Invert Enable 1"] +pub struct INVEN1_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - Output Waveform Invert Enable 0"] + #[inline(always)] + pub fn inven0(&self) -> INVEN0_R { + INVEN0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Output Waveform Invert Enable 1"] + #[inline(always)] + pub fn inven1(&self) -> INVEN1_R { + INVEN1_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Output Waveform Invert Enable 0"] + #[inline(always)] + pub fn inven0(&mut self) -> INVEN0_W { + INVEN0_W { w: self } + } + #[doc = "Bit 1 - Output Waveform Invert Enable 1"] + #[inline(always)] + pub fn inven1(&mut self) -> INVEN1_W { + INVEN1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control C\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [drvctrl](index.html) module"] +pub struct DRVCTRL_SPEC; +impl crate::RegisterSpec for DRVCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [drvctrl::R](R) reader structure"] +impl crate::Readable for DRVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [drvctrl::W](W) writer structure"] +impl crate::Writable for DRVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DRVCTRL to value 0"] +impl crate::Resettable for DRVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/tc0/count8/evctrl.rs b/pac/atsamc20j/src/tc0/count8/evctrl.rs new file mode 100644 index 000000000000..7d4c38d486c1 --- /dev/null +++ b/pac/atsamc20j/src/tc0/count8/evctrl.rs @@ -0,0 +1,465 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Event Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EVACT_A { + #[doc = "0: Event action disabled"] + OFF = 0, + #[doc = "1: Start, restart or retrigger TC on event"] + RETRIGGER = 1, + #[doc = "2: Count on event"] + COUNT = 2, + #[doc = "3: Start TC on event"] + START = 3, + #[doc = "4: Time stamp capture"] + STAMP = 4, + #[doc = "5: Period catured in CC0, pulse width in CC1"] + PPW = 5, + #[doc = "6: Period catured in CC1, pulse width in CC0"] + PWP = 6, + #[doc = "7: Pulse width capture"] + PW = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EVACT_A) -> Self { + variant as _ + } +} +#[doc = "Field `EVACT` reader - Event Action"] +pub struct EVACT_R(crate::FieldReader); +impl EVACT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVACT_A { + match self.bits { + 0 => EVACT_A::OFF, + 1 => EVACT_A::RETRIGGER, + 2 => EVACT_A::COUNT, + 3 => EVACT_A::START, + 4 => EVACT_A::STAMP, + 5 => EVACT_A::PPW, + 6 => EVACT_A::PWP, + 7 => EVACT_A::PW, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == EVACT_A::OFF + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == EVACT_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `COUNT`"] + #[inline(always)] + pub fn is_count(&self) -> bool { + **self == EVACT_A::COUNT + } + #[doc = "Checks if the value of the field is `START`"] + #[inline(always)] + pub fn is_start(&self) -> bool { + **self == EVACT_A::START + } + #[doc = "Checks if the value of the field is `STAMP`"] + #[inline(always)] + pub fn is_stamp(&self) -> bool { + **self == EVACT_A::STAMP + } + #[doc = "Checks if the value of the field is `PPW`"] + #[inline(always)] + pub fn is_ppw(&self) -> bool { + **self == EVACT_A::PPW + } + #[doc = "Checks if the value of the field is `PWP`"] + #[inline(always)] + pub fn is_pwp(&self) -> bool { + **self == EVACT_A::PWP + } + #[doc = "Checks if the value of the field is `PW`"] + #[inline(always)] + pub fn is_pw(&self) -> bool { + **self == EVACT_A::PW + } +} +impl core::ops::Deref for EVACT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT` writer - Event Action"] +pub struct EVACT_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EVACT_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Event action disabled"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(EVACT_A::OFF) + } + #[doc = "Start, restart or retrigger TC on event"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(EVACT_A::RETRIGGER) + } + #[doc = "Count on event"] + #[inline(always)] + pub fn count(self) -> &'a mut W { + self.variant(EVACT_A::COUNT) + } + #[doc = "Start TC on event"] + #[inline(always)] + pub fn start(self) -> &'a mut W { + self.variant(EVACT_A::START) + } + #[doc = "Time stamp capture"] + #[inline(always)] + pub fn stamp(self) -> &'a mut W { + self.variant(EVACT_A::STAMP) + } + #[doc = "Period catured in CC0, pulse width in CC1"] + #[inline(always)] + pub fn ppw(self) -> &'a mut W { + self.variant(EVACT_A::PPW) + } + #[doc = "Period catured in CC1, pulse width in CC0"] + #[inline(always)] + pub fn pwp(self) -> &'a mut W { + self.variant(EVACT_A::PWP) + } + #[doc = "Pulse width capture"] + #[inline(always)] + pub fn pw(self) -> &'a mut W { + self.variant(EVACT_A::PW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u16 & 0x07); + self.w + } +} +#[doc = "Field `TCINV` reader - TC Event Input Polarity"] +pub struct TCINV_R(crate::FieldReader); +impl TCINV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCINV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCINV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCINV` writer - TC Event Input Polarity"] +pub struct TCINV_W<'a> { + w: &'a mut W, +} +impl<'a> TCINV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `TCEI` reader - TC Event Enable"] +pub struct TCEI_R(crate::FieldReader); +impl TCEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCEI` writer - TC Event Enable"] +pub struct TCEI_W<'a> { + w: &'a mut W, +} +impl<'a> TCEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `OVFEO` reader - Event Output Enable"] +pub struct OVFEO_R(crate::FieldReader); +impl OVFEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVFEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVFEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVFEO` writer - Event Output Enable"] +pub struct OVFEO_W<'a> { + w: &'a mut W, +} +impl<'a> OVFEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `MCEO0` reader - MC Event Output Enable 0"] +pub struct MCEO0_R(crate::FieldReader); +impl MCEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO0` writer - MC Event Output Enable 0"] +pub struct MCEO0_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u16 & 0x01) << 12); + self.w + } +} +#[doc = "Field `MCEO1` reader - MC Event Output Enable 1"] +pub struct MCEO1_R(crate::FieldReader); +impl MCEO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO1` writer - MC Event Output Enable 1"] +pub struct MCEO1_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u16 & 0x01) << 13); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Event Action"] + #[inline(always)] + pub fn evact(&self) -> EVACT_R { + EVACT_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 4 - TC Event Input Polarity"] + #[inline(always)] + pub fn tcinv(&self) -> TCINV_R { + TCINV_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - TC Event Enable"] + #[inline(always)] + pub fn tcei(&self) -> TCEI_R { + TCEI_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 8 - Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&self) -> OVFEO_R { + OVFEO_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 12 - MC Event Output Enable 0"] + #[inline(always)] + pub fn mceo0(&self) -> MCEO0_R { + MCEO0_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - MC Event Output Enable 1"] + #[inline(always)] + pub fn mceo1(&self) -> MCEO1_R { + MCEO1_R::new(((self.bits >> 13) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Event Action"] + #[inline(always)] + pub fn evact(&mut self) -> EVACT_W { + EVACT_W { w: self } + } + #[doc = "Bit 4 - TC Event Input Polarity"] + #[inline(always)] + pub fn tcinv(&mut self) -> TCINV_W { + TCINV_W { w: self } + } + #[doc = "Bit 5 - TC Event Enable"] + #[inline(always)] + pub fn tcei(&mut self) -> TCEI_W { + TCEI_W { w: self } + } + #[doc = "Bit 8 - Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&mut self) -> OVFEO_W { + OVFEO_W { w: self } + } + #[doc = "Bit 12 - MC Event Output Enable 0"] + #[inline(always)] + pub fn mceo0(&mut self) -> MCEO0_W { + MCEO0_W { w: self } + } + #[doc = "Bit 13 - MC Event Output Enable 1"] + #[inline(always)] + pub fn mceo1(&mut self) -> MCEO1_W { + MCEO1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/tc0/count8/intenclr.rs b/pac/atsamc20j/src/tc0/count8/intenclr.rs new file mode 100644 index 000000000000..af01ef5b7dca --- /dev/null +++ b/pac/atsamc20j/src/tc0/count8/intenclr.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - OVF Interrupt Disable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - OVF Interrupt Disable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - ERR Interrupt Disable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - ERR Interrupt Disable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MC0` reader - MC Interrupt Disable 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - MC Interrupt Disable 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - MC Interrupt Disable 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - MC Interrupt Disable 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - OVF Interrupt Disable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ERR Interrupt Disable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - MC Interrupt Disable 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - MC Interrupt Disable 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - OVF Interrupt Disable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - ERR Interrupt Disable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 4 - MC Interrupt Disable 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - MC Interrupt Disable 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/tc0/count8/intenset.rs b/pac/atsamc20j/src/tc0/count8/intenset.rs new file mode 100644 index 000000000000..0e1883a2f20a --- /dev/null +++ b/pac/atsamc20j/src/tc0/count8/intenset.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - OVF Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - OVF Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - ERR Interrupt Enable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - ERR Interrupt Enable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MC0` reader - MC Interrupt Enable 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - MC Interrupt Enable 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - MC Interrupt Enable 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - MC Interrupt Enable 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - OVF Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ERR Interrupt Enable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - MC Interrupt Enable 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - MC Interrupt Enable 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - OVF Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - ERR Interrupt Enable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 4 - MC Interrupt Enable 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - MC Interrupt Enable 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/tc0/count8/intflag.rs b/pac/atsamc20j/src/tc0/count8/intflag.rs new file mode 100644 index 000000000000..1dddffaf8e7f --- /dev/null +++ b/pac/atsamc20j/src/tc0/count8/intflag.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - OVF Interrupt Flag"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - OVF Interrupt Flag"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - ERR Interrupt Flag"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - ERR Interrupt Flag"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MC0` reader - MC Interrupt Flag 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - MC Interrupt Flag 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - MC Interrupt Flag 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - MC Interrupt Flag 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - OVF Interrupt Flag"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ERR Interrupt Flag"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - MC Interrupt Flag 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - MC Interrupt Flag 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - OVF Interrupt Flag"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - ERR Interrupt Flag"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 4 - MC Interrupt Flag 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - MC Interrupt Flag 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/tc0/count8/per.rs b/pac/atsamc20j/src/tc0/count8/per.rs new file mode 100644 index 000000000000..c9ab52e247d8 --- /dev/null +++ b/pac/atsamc20j/src/tc0/count8/per.rs @@ -0,0 +1,103 @@ +#[doc = "Register `PER` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PER` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER` reader - Period Value"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` writer - Period Value"] +pub struct PER_W<'a> { + w: &'a mut W, +} +impl<'a> PER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Period Value"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Period Value"] + #[inline(always)] + pub fn per(&mut self) -> PER_W { + PER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT8 Period\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [per](index.html) module"] +pub struct PER_SPEC; +impl crate::RegisterSpec for PER_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [per::R](R) reader structure"] +impl crate::Readable for PER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [per::W](W) writer structure"] +impl crate::Writable for PER_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PER to value 0xff"] +impl crate::Resettable for PER_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xff + } +} diff --git a/pac/atsamc20j/src/tc0/count8/perbuf.rs b/pac/atsamc20j/src/tc0/count8/perbuf.rs new file mode 100644 index 000000000000..cbd500e2bbe1 --- /dev/null +++ b/pac/atsamc20j/src/tc0/count8/perbuf.rs @@ -0,0 +1,103 @@ +#[doc = "Register `PERBUF` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PERBUF` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PERBUF` reader - Period Buffer Value"] +pub struct PERBUF_R(crate::FieldReader); +impl PERBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PERBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERBUF` writer - Period Buffer Value"] +pub struct PERBUF_W<'a> { + w: &'a mut W, +} +impl<'a> PERBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Period Buffer Value"] + #[inline(always)] + pub fn perbuf(&self) -> PERBUF_R { + PERBUF_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Period Buffer Value"] + #[inline(always)] + pub fn perbuf(&mut self) -> PERBUF_W { + PERBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT8 Period Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [perbuf](index.html) module"] +pub struct PERBUF_SPEC; +impl crate::RegisterSpec for PERBUF_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [perbuf::R](R) reader structure"] +impl crate::Readable for PERBUF_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [perbuf::W](W) writer structure"] +impl crate::Writable for PERBUF_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PERBUF to value 0xff"] +impl crate::Resettable for PERBUF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xff + } +} diff --git a/pac/atsamc20j/src/tc0/count8/status.rs b/pac/atsamc20j/src/tc0/count8/status.rs new file mode 100644 index 000000000000..5088af446830 --- /dev/null +++ b/pac/atsamc20j/src/tc0/count8/status.rs @@ -0,0 +1,301 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `STOP` reader - Stop Status Flag"] +pub struct STOP_R(crate::FieldReader); +impl STOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STOP` writer - Stop Status Flag"] +pub struct STOP_W<'a> { + w: &'a mut W, +} +impl<'a> STOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SLAVE` reader - Slave Status Flag"] +pub struct SLAVE_R(crate::FieldReader); +impl SLAVE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLAVE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SLAVE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLAVE` writer - Slave Status Flag"] +pub struct SLAVE_W<'a> { + w: &'a mut W, +} +impl<'a> SLAVE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PERBUFV` reader - Synchronization Busy Status"] +pub struct PERBUFV_R(crate::FieldReader); +impl PERBUFV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PERBUFV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERBUFV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERBUFV` writer - Synchronization Busy Status"] +pub struct PERBUFV_W<'a> { + w: &'a mut W, +} +impl<'a> PERBUFV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CCBUFV0` reader - Compare channel buffer 0 valid"] +pub struct CCBUFV0_R(crate::FieldReader); +impl CCBUFV0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBUFV0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUFV0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUFV0` writer - Compare channel buffer 0 valid"] +pub struct CCBUFV0_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUFV0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `CCBUFV1` reader - Compare channel buffer 1 valid"] +pub struct CCBUFV1_R(crate::FieldReader); +impl CCBUFV1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBUFV1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUFV1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUFV1` writer - Compare channel buffer 1 valid"] +pub struct CCBUFV1_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUFV1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Stop Status Flag"] + #[inline(always)] + pub fn stop(&self) -> STOP_R { + STOP_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Slave Status Flag"] + #[inline(always)] + pub fn slave(&self) -> SLAVE_R { + SLAVE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 3 - Synchronization Busy Status"] + #[inline(always)] + pub fn perbufv(&self) -> PERBUFV_R { + PERBUFV_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Compare channel buffer 0 valid"] + #[inline(always)] + pub fn ccbufv0(&self) -> CCBUFV0_R { + CCBUFV0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Compare channel buffer 1 valid"] + #[inline(always)] + pub fn ccbufv1(&self) -> CCBUFV1_R { + CCBUFV1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Stop Status Flag"] + #[inline(always)] + pub fn stop(&mut self) -> STOP_W { + STOP_W { w: self } + } + #[doc = "Bit 1 - Slave Status Flag"] + #[inline(always)] + pub fn slave(&mut self) -> SLAVE_W { + SLAVE_W { w: self } + } + #[doc = "Bit 3 - Synchronization Busy Status"] + #[inline(always)] + pub fn perbufv(&mut self) -> PERBUFV_W { + PERBUFV_W { w: self } + } + #[doc = "Bit 4 - Compare channel buffer 0 valid"] + #[inline(always)] + pub fn ccbufv0(&mut self) -> CCBUFV0_W { + CCBUFV0_W { w: self } + } + #[doc = "Bit 5 - Compare channel buffer 1 valid"] + #[inline(always)] + pub fn ccbufv1(&mut self) -> CCBUFV1_W { + CCBUFV1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0x01"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pac/atsamc20j/src/tc0/count8/syncbusy.rs b/pac/atsamc20j/src/tc0/count8/syncbusy.rs new file mode 100644 index 000000000000..7ad8d91a84de --- /dev/null +++ b/pac/atsamc20j/src/tc0/count8/syncbusy.rs @@ -0,0 +1,193 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - swrst"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLB` reader - CTRLB"] +pub struct CTRLB_R(crate::FieldReader); +impl CTRLB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STATUS` reader - STATUS"] +pub struct STATUS_R(crate::FieldReader); +impl STATUS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STATUS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STATUS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` reader - Counter"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` reader - Period"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC0` reader - Compare Channel 0"] +pub struct CC0_R(crate::FieldReader); +impl CC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC1` reader - Compare Channel 1"] +pub struct CC1_R(crate::FieldReader); +impl CC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - swrst"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - CTRLB"] + #[inline(always)] + pub fn ctrlb(&self) -> CTRLB_R { + CTRLB_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - STATUS"] + #[inline(always)] + pub fn status(&self) -> STATUS_R { + STATUS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Counter"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Period"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Compare Channel 0"] + #[inline(always)] + pub fn cc0(&self) -> CC0_R { + CC0_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Compare Channel 1"] + #[inline(always)] + pub fn cc1(&self) -> CC1_R { + CC1_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +#[doc = "Synchronization Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/tc0/count8/wave.rs b/pac/atsamc20j/src/tc0/count8/wave.rs new file mode 100644 index 000000000000..46061b24b75d --- /dev/null +++ b/pac/atsamc20j/src/tc0/count8/wave.rs @@ -0,0 +1,178 @@ +#[doc = "Register `WAVE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WAVE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Waveform Generation Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WAVEGEN_A { + #[doc = "0: Normal frequency"] + NFRQ = 0, + #[doc = "1: Match frequency"] + MFRQ = 1, + #[doc = "2: Normal PWM"] + NPWM = 2, + #[doc = "3: Match PWM"] + MPWM = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WAVEGEN_A) -> Self { + variant as _ + } +} +#[doc = "Field `WAVEGEN` reader - Waveform Generation Mode"] +pub struct WAVEGEN_R(crate::FieldReader); +impl WAVEGEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WAVEGEN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> WAVEGEN_A { + match self.bits { + 0 => WAVEGEN_A::NFRQ, + 1 => WAVEGEN_A::MFRQ, + 2 => WAVEGEN_A::NPWM, + 3 => WAVEGEN_A::MPWM, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NFRQ`"] + #[inline(always)] + pub fn is_nfrq(&self) -> bool { + **self == WAVEGEN_A::NFRQ + } + #[doc = "Checks if the value of the field is `MFRQ`"] + #[inline(always)] + pub fn is_mfrq(&self) -> bool { + **self == WAVEGEN_A::MFRQ + } + #[doc = "Checks if the value of the field is `NPWM`"] + #[inline(always)] + pub fn is_npwm(&self) -> bool { + **self == WAVEGEN_A::NPWM + } + #[doc = "Checks if the value of the field is `MPWM`"] + #[inline(always)] + pub fn is_mpwm(&self) -> bool { + **self == WAVEGEN_A::MPWM + } +} +impl core::ops::Deref for WAVEGEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAVEGEN` writer - Waveform Generation Mode"] +pub struct WAVEGEN_W<'a> { + w: &'a mut W, +} +impl<'a> WAVEGEN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WAVEGEN_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Normal frequency"] + #[inline(always)] + pub fn nfrq(self) -> &'a mut W { + self.variant(WAVEGEN_A::NFRQ) + } + #[doc = "Match frequency"] + #[inline(always)] + pub fn mfrq(self) -> &'a mut W { + self.variant(WAVEGEN_A::MFRQ) + } + #[doc = "Normal PWM"] + #[inline(always)] + pub fn npwm(self) -> &'a mut W { + self.variant(WAVEGEN_A::NPWM) + } + #[doc = "Match PWM"] + #[inline(always)] + pub fn mpwm(self) -> &'a mut W { + self.variant(WAVEGEN_A::MPWM) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u8 & 0x03); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Waveform Generation Mode"] + #[inline(always)] + pub fn wavegen(&self) -> WAVEGEN_R { + WAVEGEN_R::new((self.bits & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Waveform Generation Mode"] + #[inline(always)] + pub fn wavegen(&mut self) -> WAVEGEN_W { + WAVEGEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Waveform Generation Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wave](index.html) module"] +pub struct WAVE_SPEC; +impl crate::RegisterSpec for WAVE_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [wave::R](R) reader structure"] +impl crate::Readable for WAVE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wave::W](W) writer structure"] +impl crate::Writable for WAVE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WAVE to value 0"] +impl crate::Resettable for WAVE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/tcc0.rs b/pac/atsamc20j/src/tcc0.rs new file mode 100644 index 000000000000..6ce813a9e3d5 --- /dev/null +++ b/pac/atsamc20j/src/tcc0.rs @@ -0,0 +1,359 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - Control B Clear"] + pub ctrlbclr: crate::Reg, + #[doc = "0x05 - Control B Set"] + pub ctrlbset: crate::Reg, + _reserved3: [u8; 0x02], + #[doc = "0x08 - Synchronization Busy"] + pub syncbusy: crate::Reg, + #[doc = "0x0c - Recoverable Fault A Configuration"] + pub fctrla: crate::Reg, + #[doc = "0x10 - Recoverable Fault B Configuration"] + pub fctrlb: crate::Reg, + #[doc = "0x14 - Waveform Extension Configuration"] + pub wexctrl: crate::Reg, + #[doc = "0x18 - Driver Control"] + pub drvctrl: crate::Reg, + _reserved8: [u8; 0x02], + #[doc = "0x1e - Debug Control"] + pub dbgctrl: crate::Reg, + _reserved9: [u8; 0x01], + #[doc = "0x20 - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x24 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x28 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x2c - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x30 - Status"] + pub status: crate::Reg, + _reserved_14_count: [u8; 0x04], + #[doc = "0x38 - Pattern"] + pub patt: crate::Reg, + _reserved16: [u8; 0x02], + #[doc = "0x3c - Waveform Control"] + pub wave: crate::Reg, + _reserved_17_per: [u8; 0x04], + _reserved_18_cc: [u8; 0x10], + _reserved19: [u8; 0x10], + #[doc = "0x64 - Pattern Buffer"] + pub pattbuf: crate::Reg, + _reserved20: [u8; 0x06], + _reserved_20_perbuf: [u8; 0x04], + _reserved_21_ccbuf: [u8; 0x10], +} +impl RegisterBlock { + #[doc = "0x34 - Count"] + #[inline(always)] + pub fn count_dith6_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(52usize) + as *const crate::Reg) + } + } + #[doc = "0x34 - Count"] + #[inline(always)] + pub fn count_dith5_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(52usize) + as *const crate::Reg) + } + } + #[doc = "0x34 - Count"] + #[inline(always)] + pub fn count_dith4_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(52usize) + as *const crate::Reg) + } + } + #[doc = "0x34 - Count"] + #[inline(always)] + pub fn count(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(52usize) + as *const crate::Reg) + } + } + #[doc = "0x40 - Period"] + #[inline(always)] + pub fn per_dith6_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(64usize) + as *const crate::Reg) + } + } + #[doc = "0x40 - Period"] + #[inline(always)] + pub fn per_dith5_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(64usize) + as *const crate::Reg) + } + } + #[doc = "0x40 - Period"] + #[inline(always)] + pub fn per_dith4_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(64usize) + as *const crate::Reg) + } + } + #[doc = "0x40 - Period"] + #[inline(always)] + pub fn per(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(64usize) + as *const crate::Reg) + } + } + #[doc = "0x44..0x54 - Compare and Capture"] + #[inline(always)] + pub fn cc_dith6_mode(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(68usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x44..0x54 - Compare and Capture"] + #[inline(always)] + pub fn cc_dith5_mode(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(68usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x44..0x54 - Compare and Capture"] + #[inline(always)] + pub fn cc_dith4_mode(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(68usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x44..0x54 - Compare and Capture"] + #[inline(always)] + pub fn cc(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(68usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x6c - Period Buffer"] + #[inline(always)] + pub fn perbuf_dith6_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(108usize) + as *const crate::Reg) + } + } + #[doc = "0x6c - Period Buffer"] + #[inline(always)] + pub fn perbuf_dith5_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(108usize) + as *const crate::Reg) + } + } + #[doc = "0x6c - Period Buffer"] + #[inline(always)] + pub fn perbuf_dith4_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(108usize) + as *const crate::Reg) + } + } + #[doc = "0x6c - Period Buffer"] + #[inline(always)] + pub fn perbuf(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(108usize) + as *const crate::Reg) + } + } + #[doc = "0x70..0x80 - Compare and Capture Buffer"] + #[inline(always)] + pub fn ccbuf_dith6_mode(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(112usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x70..0x80 - Compare and Capture Buffer"] + #[inline(always)] + pub fn ccbuf_dith5_mode(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(112usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x70..0x80 - Compare and Capture Buffer"] + #[inline(always)] + pub fn ccbuf_dith4_mode(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(112usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x70..0x80 - Compare and Capture Buffer"] + #[inline(always)] + pub fn ccbuf(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(112usize) + as *const [crate::Reg; 4]) + } + } +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "CTRLBCLR register accessor: an alias for `Reg`"] +pub type CTRLBCLR = crate::Reg; +#[doc = "Control B Clear"] +pub mod ctrlbclr; +#[doc = "CTRLBSET register accessor: an alias for `Reg`"] +pub type CTRLBSET = crate::Reg; +#[doc = "Control B Set"] +pub mod ctrlbset; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Busy"] +pub mod syncbusy; +#[doc = "FCTRLA register accessor: an alias for `Reg`"] +pub type FCTRLA = crate::Reg; +#[doc = "Recoverable Fault A Configuration"] +pub mod fctrla; +#[doc = "FCTRLB register accessor: an alias for `Reg`"] +pub type FCTRLB = crate::Reg; +#[doc = "Recoverable Fault B Configuration"] +pub mod fctrlb; +#[doc = "WEXCTRL register accessor: an alias for `Reg`"] +pub type WEXCTRL = crate::Reg; +#[doc = "Waveform Extension Configuration"] +pub mod wexctrl; +#[doc = "DRVCTRL register accessor: an alias for `Reg`"] +pub type DRVCTRL = crate::Reg; +#[doc = "Driver Control"] +pub mod drvctrl; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "COUNT register accessor: an alias for `Reg`"] +pub type COUNT = crate::Reg; +#[doc = "Count"] +pub mod count; +#[doc = "COUNT_DITH4_MODE register accessor: an alias for `Reg`"] +pub type COUNT_DITH4_MODE = crate::Reg; +#[doc = "Count"] +pub mod count_dith4_mode; +#[doc = "COUNT_DITH5_MODE register accessor: an alias for `Reg`"] +pub type COUNT_DITH5_MODE = crate::Reg; +#[doc = "Count"] +pub mod count_dith5_mode; +#[doc = "COUNT_DITH6_MODE register accessor: an alias for `Reg`"] +pub type COUNT_DITH6_MODE = crate::Reg; +#[doc = "Count"] +pub mod count_dith6_mode; +#[doc = "PATT register accessor: an alias for `Reg`"] +pub type PATT = crate::Reg; +#[doc = "Pattern"] +pub mod patt; +#[doc = "WAVE register accessor: an alias for `Reg`"] +pub type WAVE = crate::Reg; +#[doc = "Waveform Control"] +pub mod wave; +#[doc = "PER register accessor: an alias for `Reg`"] +pub type PER = crate::Reg; +#[doc = "Period"] +pub mod per; +#[doc = "PER_DITH4_MODE register accessor: an alias for `Reg`"] +pub type PER_DITH4_MODE = crate::Reg; +#[doc = "Period"] +pub mod per_dith4_mode; +#[doc = "PER_DITH5_MODE register accessor: an alias for `Reg`"] +pub type PER_DITH5_MODE = crate::Reg; +#[doc = "Period"] +pub mod per_dith5_mode; +#[doc = "PER_DITH6_MODE register accessor: an alias for `Reg`"] +pub type PER_DITH6_MODE = crate::Reg; +#[doc = "Period"] +pub mod per_dith6_mode; +#[doc = "CC register accessor: an alias for `Reg`"] +pub type CC = crate::Reg; +#[doc = "Compare and Capture"] +pub mod cc; +#[doc = "CC_DITH4_MODE register accessor: an alias for `Reg`"] +pub type CC_DITH4_MODE = crate::Reg; +#[doc = "Compare and Capture"] +pub mod cc_dith4_mode; +#[doc = "CC_DITH5_MODE register accessor: an alias for `Reg`"] +pub type CC_DITH5_MODE = crate::Reg; +#[doc = "Compare and Capture"] +pub mod cc_dith5_mode; +#[doc = "CC_DITH6_MODE register accessor: an alias for `Reg`"] +pub type CC_DITH6_MODE = crate::Reg; +#[doc = "Compare and Capture"] +pub mod cc_dith6_mode; +#[doc = "PATTBUF register accessor: an alias for `Reg`"] +pub type PATTBUF = crate::Reg; +#[doc = "Pattern Buffer"] +pub mod pattbuf; +#[doc = "PERBUF register accessor: an alias for `Reg`"] +pub type PERBUF = crate::Reg; +#[doc = "Period Buffer"] +pub mod perbuf; +#[doc = "PERBUF_DITH4_MODE register accessor: an alias for `Reg`"] +pub type PERBUF_DITH4_MODE = crate::Reg; +#[doc = "Period Buffer"] +pub mod perbuf_dith4_mode; +#[doc = "PERBUF_DITH5_MODE register accessor: an alias for `Reg`"] +pub type PERBUF_DITH5_MODE = crate::Reg; +#[doc = "Period Buffer"] +pub mod perbuf_dith5_mode; +#[doc = "PERBUF_DITH6_MODE register accessor: an alias for `Reg`"] +pub type PERBUF_DITH6_MODE = crate::Reg; +#[doc = "Period Buffer"] +pub mod perbuf_dith6_mode; +#[doc = "CCBUF register accessor: an alias for `Reg`"] +pub type CCBUF = crate::Reg; +#[doc = "Compare and Capture Buffer"] +pub mod ccbuf; +#[doc = "CCBUF_DITH4_MODE register accessor: an alias for `Reg`"] +pub type CCBUF_DITH4_MODE = crate::Reg; +#[doc = "Compare and Capture Buffer"] +pub mod ccbuf_dith4_mode; +#[doc = "CCBUF_DITH5_MODE register accessor: an alias for `Reg`"] +pub type CCBUF_DITH5_MODE = crate::Reg; +#[doc = "Compare and Capture Buffer"] +pub mod ccbuf_dith5_mode; +#[doc = "CCBUF_DITH6_MODE register accessor: an alias for `Reg`"] +pub type CCBUF_DITH6_MODE = crate::Reg; +#[doc = "Compare and Capture Buffer"] +pub mod ccbuf_dith6_mode; diff --git a/pac/atsamc20j/src/tcc0/cc.rs b/pac/atsamc20j/src/tcc0/cc.rs new file mode 100644 index 000000000000..c4d6df7a9a20 --- /dev/null +++ b/pac/atsamc20j/src/tcc0/cc.rs @@ -0,0 +1,104 @@ +#[doc = "Register `CC[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CC[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CC` reader - Channel Compare/Capture Value"] +pub struct CC_R(crate::FieldReader); +impl CC_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC` writer - Channel Compare/Capture Value"] +pub struct CC_W<'a> { + w: &'a mut W, +} +impl<'a> CC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&self) -> CC_R { + CC_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&mut self) -> CC_W { + CC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc](index.html) module"] +pub struct CC_SPEC; +impl crate::RegisterSpec for CC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cc::R](R) reader structure"] +impl crate::Readable for CC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cc::W](W) writer structure"] +impl crate::Writable for CC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CC[%s] +to value 0"] +impl crate::Resettable for CC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/tcc0/cc_dith4_mode.rs b/pac/atsamc20j/src/tcc0/cc_dith4_mode.rs new file mode 100644 index 000000000000..c45d8b6bac41 --- /dev/null +++ b/pac/atsamc20j/src/tcc0/cc_dith4_mode.rs @@ -0,0 +1,141 @@ +#[doc = "Register `CC_DITH4_MODE[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CC_DITH4_MODE[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHER` reader - Dithering Cycle Number"] +pub struct DITHER_R(crate::FieldReader); +impl DITHER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHER` writer - Dithering Cycle Number"] +pub struct DITHER_W<'a> { + w: &'a mut W, +} +impl<'a> DITHER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Field `CC` reader - Channel Compare/Capture Value"] +pub struct CC_R(crate::FieldReader); +impl CC_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC` writer - Channel Compare/Capture Value"] +pub struct CC_W<'a> { + w: &'a mut W, +} +impl<'a> CC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x000f_ffff << 4)) | ((value as u32 & 0x000f_ffff) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&self) -> DITHER_R { + DITHER_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&self) -> CC_R { + CC_R::new(((self.bits >> 4) & 0x000f_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:3 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&mut self) -> DITHER_W { + DITHER_W { w: self } + } + #[doc = "Bits 4:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&mut self) -> CC_W { + CC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc_dith4_mode](index.html) module"] +pub struct CC_DITH4_MODE_SPEC; +impl crate::RegisterSpec for CC_DITH4_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cc_dith4_mode::R](R) reader structure"] +impl crate::Readable for CC_DITH4_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cc_dith4_mode::W](W) writer structure"] +impl crate::Writable for CC_DITH4_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CC_DITH4_MODE[%s] +to value 0"] +impl crate::Resettable for CC_DITH4_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/tcc0/cc_dith5_mode.rs b/pac/atsamc20j/src/tcc0/cc_dith5_mode.rs new file mode 100644 index 000000000000..0592b923051a --- /dev/null +++ b/pac/atsamc20j/src/tcc0/cc_dith5_mode.rs @@ -0,0 +1,141 @@ +#[doc = "Register `CC_DITH5_MODE[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CC_DITH5_MODE[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHER` reader - Dithering Cycle Number"] +pub struct DITHER_R(crate::FieldReader); +impl DITHER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHER` writer - Dithering Cycle Number"] +pub struct DITHER_W<'a> { + w: &'a mut W, +} +impl<'a> DITHER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f); + self.w + } +} +#[doc = "Field `CC` reader - Channel Compare/Capture Value"] +pub struct CC_R(crate::FieldReader); +impl CC_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC` writer - Channel Compare/Capture Value"] +pub struct CC_W<'a> { + w: &'a mut W, +} +impl<'a> CC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0007_ffff << 5)) | ((value as u32 & 0x0007_ffff) << 5); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&self) -> DITHER_R { + DITHER_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&self) -> CC_R { + CC_R::new(((self.bits >> 5) & 0x0007_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:4 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&mut self) -> DITHER_W { + DITHER_W { w: self } + } + #[doc = "Bits 5:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&mut self) -> CC_W { + CC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc_dith5_mode](index.html) module"] +pub struct CC_DITH5_MODE_SPEC; +impl crate::RegisterSpec for CC_DITH5_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cc_dith5_mode::R](R) reader structure"] +impl crate::Readable for CC_DITH5_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cc_dith5_mode::W](W) writer structure"] +impl crate::Writable for CC_DITH5_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CC_DITH5_MODE[%s] +to value 0"] +impl crate::Resettable for CC_DITH5_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/tcc0/cc_dith6_mode.rs b/pac/atsamc20j/src/tcc0/cc_dith6_mode.rs new file mode 100644 index 000000000000..62a82a872426 --- /dev/null +++ b/pac/atsamc20j/src/tcc0/cc_dith6_mode.rs @@ -0,0 +1,141 @@ +#[doc = "Register `CC_DITH6_MODE[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CC_DITH6_MODE[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHER` reader - Dithering Cycle Number"] +pub struct DITHER_R(crate::FieldReader); +impl DITHER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHER` writer - Dithering Cycle Number"] +pub struct DITHER_W<'a> { + w: &'a mut W, +} +impl<'a> DITHER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +#[doc = "Field `CC` reader - Channel Compare/Capture Value"] +pub struct CC_R(crate::FieldReader); +impl CC_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC` writer - Channel Compare/Capture Value"] +pub struct CC_W<'a> { + w: &'a mut W, +} +impl<'a> CC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0003_ffff << 6)) | ((value as u32 & 0x0003_ffff) << 6); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&self) -> DITHER_R { + DITHER_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&self) -> CC_R { + CC_R::new(((self.bits >> 6) & 0x0003_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:5 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&mut self) -> DITHER_W { + DITHER_W { w: self } + } + #[doc = "Bits 6:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&mut self) -> CC_W { + CC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc_dith6_mode](index.html) module"] +pub struct CC_DITH6_MODE_SPEC; +impl crate::RegisterSpec for CC_DITH6_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cc_dith6_mode::R](R) reader structure"] +impl crate::Readable for CC_DITH6_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cc_dith6_mode::W](W) writer structure"] +impl crate::Writable for CC_DITH6_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CC_DITH6_MODE[%s] +to value 0"] +impl crate::Resettable for CC_DITH6_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/tcc0/ccbuf.rs b/pac/atsamc20j/src/tcc0/ccbuf.rs new file mode 100644 index 000000000000..a4db1135f095 --- /dev/null +++ b/pac/atsamc20j/src/tcc0/ccbuf.rs @@ -0,0 +1,104 @@ +#[doc = "Register `CCBUF[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CCBUF[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CCBUF` reader - Channel Compare/Capture Buffer Value"] +pub struct CCBUF_R(crate::FieldReader); +impl CCBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CCBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUF` writer - Channel Compare/Capture Buffer Value"] +pub struct CCBUF_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccbuf(&self) -> CCBUF_R { + CCBUF_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccbuf(&mut self) -> CCBUF_W { + CCBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccbuf](index.html) module"] +pub struct CCBUF_SPEC; +impl crate::RegisterSpec for CCBUF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ccbuf::R](R) reader structure"] +impl crate::Readable for CCBUF_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ccbuf::W](W) writer structure"] +impl crate::Writable for CCBUF_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CCBUF[%s] +to value 0"] +impl crate::Resettable for CCBUF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/tcc0/ccbuf_dith4_mode.rs b/pac/atsamc20j/src/tcc0/ccbuf_dith4_mode.rs new file mode 100644 index 000000000000..dfa16e936175 --- /dev/null +++ b/pac/atsamc20j/src/tcc0/ccbuf_dith4_mode.rs @@ -0,0 +1,141 @@ +#[doc = "Register `CCBUF_DITH4_MODE[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CCBUF_DITH4_MODE[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CCBUF` reader - Channel Compare/Capture Buffer Value"] +pub struct CCBUF_R(crate::FieldReader); +impl CCBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CCBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUF` writer - Channel Compare/Capture Buffer Value"] +pub struct CCBUF_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Field `DITHERBUF` reader - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_R(crate::FieldReader); +impl DITHERBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + DITHERBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHERBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHERBUF` writer - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_W<'a> { + w: &'a mut W, +} +impl<'a> DITHERBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x000f_ffff << 4)) | ((value as u32 & 0x000f_ffff) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccbuf(&self) -> CCBUF_R { + CCBUF_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:23 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&self) -> DITHERBUF_R { + DITHERBUF_R::new(((self.bits >> 4) & 0x000f_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:3 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccbuf(&mut self) -> CCBUF_W { + CCBUF_W { w: self } + } + #[doc = "Bits 4:23 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&mut self) -> DITHERBUF_W { + DITHERBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccbuf_dith4_mode](index.html) module"] +pub struct CCBUF_DITH4_MODE_SPEC; +impl crate::RegisterSpec for CCBUF_DITH4_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ccbuf_dith4_mode::R](R) reader structure"] +impl crate::Readable for CCBUF_DITH4_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ccbuf_dith4_mode::W](W) writer structure"] +impl crate::Writable for CCBUF_DITH4_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CCBUF_DITH4_MODE[%s] +to value 0"] +impl crate::Resettable for CCBUF_DITH4_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/tcc0/ccbuf_dith5_mode.rs b/pac/atsamc20j/src/tcc0/ccbuf_dith5_mode.rs new file mode 100644 index 000000000000..0c78ba3303c0 --- /dev/null +++ b/pac/atsamc20j/src/tcc0/ccbuf_dith5_mode.rs @@ -0,0 +1,141 @@ +#[doc = "Register `CCBUF_DITH5_MODE[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CCBUF_DITH5_MODE[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHERBUF` reader - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_R(crate::FieldReader); +impl DITHERBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHERBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHERBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHERBUF` writer - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_W<'a> { + w: &'a mut W, +} +impl<'a> DITHERBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f); + self.w + } +} +#[doc = "Field `CCBUF` reader - Channel Compare/Capture Buffer Value"] +pub struct CCBUF_R(crate::FieldReader); +impl CCBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CCBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUF` writer - Channel Compare/Capture Buffer Value"] +pub struct CCBUF_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0007_ffff << 5)) | ((value as u32 & 0x0007_ffff) << 5); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&self) -> DITHERBUF_R { + DITHERBUF_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:23 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccbuf(&self) -> CCBUF_R { + CCBUF_R::new(((self.bits >> 5) & 0x0007_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:4 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&mut self) -> DITHERBUF_W { + DITHERBUF_W { w: self } + } + #[doc = "Bits 5:23 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccbuf(&mut self) -> CCBUF_W { + CCBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccbuf_dith5_mode](index.html) module"] +pub struct CCBUF_DITH5_MODE_SPEC; +impl crate::RegisterSpec for CCBUF_DITH5_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ccbuf_dith5_mode::R](R) reader structure"] +impl crate::Readable for CCBUF_DITH5_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ccbuf_dith5_mode::W](W) writer structure"] +impl crate::Writable for CCBUF_DITH5_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CCBUF_DITH5_MODE[%s] +to value 0"] +impl crate::Resettable for CCBUF_DITH5_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/tcc0/ccbuf_dith6_mode.rs b/pac/atsamc20j/src/tcc0/ccbuf_dith6_mode.rs new file mode 100644 index 000000000000..8d19b8a9e595 --- /dev/null +++ b/pac/atsamc20j/src/tcc0/ccbuf_dith6_mode.rs @@ -0,0 +1,141 @@ +#[doc = "Register `CCBUF_DITH6_MODE[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CCBUF_DITH6_MODE[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHERBUF` reader - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_R(crate::FieldReader); +impl DITHERBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHERBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHERBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHERBUF` writer - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_W<'a> { + w: &'a mut W, +} +impl<'a> DITHERBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +#[doc = "Field `CCBUF` reader - Channel Compare/Capture Buffer Value"] +pub struct CCBUF_R(crate::FieldReader); +impl CCBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CCBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUF` writer - Channel Compare/Capture Buffer Value"] +pub struct CCBUF_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0003_ffff << 6)) | ((value as u32 & 0x0003_ffff) << 6); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&self) -> DITHERBUF_R { + DITHERBUF_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:23 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccbuf(&self) -> CCBUF_R { + CCBUF_R::new(((self.bits >> 6) & 0x0003_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:5 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&mut self) -> DITHERBUF_W { + DITHERBUF_W { w: self } + } + #[doc = "Bits 6:23 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccbuf(&mut self) -> CCBUF_W { + CCBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccbuf_dith6_mode](index.html) module"] +pub struct CCBUF_DITH6_MODE_SPEC; +impl crate::RegisterSpec for CCBUF_DITH6_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ccbuf_dith6_mode::R](R) reader structure"] +impl crate::Readable for CCBUF_DITH6_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ccbuf_dith6_mode::W](W) writer structure"] +impl crate::Writable for CCBUF_DITH6_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CCBUF_DITH6_MODE[%s] +to value 0"] +impl crate::Resettable for CCBUF_DITH6_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/tcc0/count.rs b/pac/atsamc20j/src/tcc0/count.rs new file mode 100644 index 000000000000..7628f2c0d5e1 --- /dev/null +++ b/pac/atsamc20j/src/tcc0/count.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Count\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count](index.html) module"] +pub struct COUNT_SPEC; +impl crate::RegisterSpec for COUNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [count::R](R) reader structure"] +impl crate::Readable for COUNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count::W](W) writer structure"] +impl crate::Writable for COUNT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT to value 0"] +impl crate::Resettable for COUNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/tcc0/count_dith4_mode.rs b/pac/atsamc20j/src/tcc0/count_dith4_mode.rs new file mode 100644 index 000000000000..fc058ae5efd5 --- /dev/null +++ b/pac/atsamc20j/src/tcc0/count_dith4_mode.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT_DITH4_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT_DITH4_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x000f_ffff << 4)) | ((value as u32 & 0x000f_ffff) << 4); + self.w + } +} +impl R { + #[doc = "Bits 4:23 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 4) & 0x000f_ffff) as u32) + } +} +impl W { + #[doc = "Bits 4:23 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Count\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count_dith4_mode](index.html) module"] +pub struct COUNT_DITH4_MODE_SPEC; +impl crate::RegisterSpec for COUNT_DITH4_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [count_dith4_mode::R](R) reader structure"] +impl crate::Readable for COUNT_DITH4_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count_dith4_mode::W](W) writer structure"] +impl crate::Writable for COUNT_DITH4_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT_DITH4_MODE to value 0"] +impl crate::Resettable for COUNT_DITH4_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/tcc0/count_dith5_mode.rs b/pac/atsamc20j/src/tcc0/count_dith5_mode.rs new file mode 100644 index 000000000000..e66e20310726 --- /dev/null +++ b/pac/atsamc20j/src/tcc0/count_dith5_mode.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT_DITH5_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT_DITH5_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0007_ffff << 5)) | ((value as u32 & 0x0007_ffff) << 5); + self.w + } +} +impl R { + #[doc = "Bits 5:23 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 5) & 0x0007_ffff) as u32) + } +} +impl W { + #[doc = "Bits 5:23 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Count\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count_dith5_mode](index.html) module"] +pub struct COUNT_DITH5_MODE_SPEC; +impl crate::RegisterSpec for COUNT_DITH5_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [count_dith5_mode::R](R) reader structure"] +impl crate::Readable for COUNT_DITH5_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count_dith5_mode::W](W) writer structure"] +impl crate::Writable for COUNT_DITH5_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT_DITH5_MODE to value 0"] +impl crate::Resettable for COUNT_DITH5_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/tcc0/count_dith6_mode.rs b/pac/atsamc20j/src/tcc0/count_dith6_mode.rs new file mode 100644 index 000000000000..5410fc6c9459 --- /dev/null +++ b/pac/atsamc20j/src/tcc0/count_dith6_mode.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT_DITH6_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT_DITH6_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0003_ffff << 6)) | ((value as u32 & 0x0003_ffff) << 6); + self.w + } +} +impl R { + #[doc = "Bits 6:23 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 6) & 0x0003_ffff) as u32) + } +} +impl W { + #[doc = "Bits 6:23 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Count\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count_dith6_mode](index.html) module"] +pub struct COUNT_DITH6_MODE_SPEC; +impl crate::RegisterSpec for COUNT_DITH6_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [count_dith6_mode::R](R) reader structure"] +impl crate::Readable for COUNT_DITH6_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count_dith6_mode::W](W) writer structure"] +impl crate::Writable for COUNT_DITH6_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT_DITH6_MODE to value 0"] +impl crate::Resettable for COUNT_DITH6_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/tcc0/ctrla.rs b/pac/atsamc20j/src/tcc0/ctrla.rs new file mode 100644 index 000000000000..b717d1ac6ae0 --- /dev/null +++ b/pac/atsamc20j/src/tcc0/ctrla.rs @@ -0,0 +1,911 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Enhanced Resolution\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum RESOLUTION_A { + #[doc = "0: Dithering is disabled"] + NONE = 0, + #[doc = "1: Dithering is done every 16 PWM frames"] + DITH4 = 1, + #[doc = "2: Dithering is done every 32 PWM frames"] + DITH5 = 2, + #[doc = "3: Dithering is done every 64 PWM frames"] + DITH6 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RESOLUTION_A) -> Self { + variant as _ + } +} +#[doc = "Field `RESOLUTION` reader - Enhanced Resolution"] +pub struct RESOLUTION_R(crate::FieldReader); +impl RESOLUTION_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RESOLUTION_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RESOLUTION_A { + match self.bits { + 0 => RESOLUTION_A::NONE, + 1 => RESOLUTION_A::DITH4, + 2 => RESOLUTION_A::DITH5, + 3 => RESOLUTION_A::DITH6, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == RESOLUTION_A::NONE + } + #[doc = "Checks if the value of the field is `DITH4`"] + #[inline(always)] + pub fn is_dith4(&self) -> bool { + **self == RESOLUTION_A::DITH4 + } + #[doc = "Checks if the value of the field is `DITH5`"] + #[inline(always)] + pub fn is_dith5(&self) -> bool { + **self == RESOLUTION_A::DITH5 + } + #[doc = "Checks if the value of the field is `DITH6`"] + #[inline(always)] + pub fn is_dith6(&self) -> bool { + **self == RESOLUTION_A::DITH6 + } +} +impl core::ops::Deref for RESOLUTION_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESOLUTION` writer - Enhanced Resolution"] +pub struct RESOLUTION_W<'a> { + w: &'a mut W, +} +impl<'a> RESOLUTION_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RESOLUTION_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Dithering is disabled"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(RESOLUTION_A::NONE) + } + #[doc = "Dithering is done every 16 PWM frames"] + #[inline(always)] + pub fn dith4(self) -> &'a mut W { + self.variant(RESOLUTION_A::DITH4) + } + #[doc = "Dithering is done every 32 PWM frames"] + #[inline(always)] + pub fn dith5(self) -> &'a mut W { + self.variant(RESOLUTION_A::DITH5) + } + #[doc = "Dithering is done every 64 PWM frames"] + #[inline(always)] + pub fn dith6(self) -> &'a mut W { + self.variant(RESOLUTION_A::DITH6) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 5)) | ((value as u32 & 0x03) << 5); + self.w + } +} +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: No division"] + DIV1 = 0, + #[doc = "1: Divide by 2"] + DIV2 = 1, + #[doc = "2: Divide by 4"] + DIV4 = 2, + #[doc = "3: Divide by 8"] + DIV8 = 3, + #[doc = "4: Divide by 16"] + DIV16 = 4, + #[doc = "5: Divide by 64"] + DIV64 = 5, + #[doc = "6: Divide by 256"] + DIV256 = 6, + #[doc = "7: Divide by 1024"] + DIV1024 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PRESCALER_A { + match self.bits { + 0 => PRESCALER_A::DIV1, + 1 => PRESCALER_A::DIV2, + 2 => PRESCALER_A::DIV4, + 3 => PRESCALER_A::DIV8, + 4 => PRESCALER_A::DIV16, + 5 => PRESCALER_A::DIV64, + 6 => PRESCALER_A::DIV256, + 7 => PRESCALER_A::DIV1024, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == PRESCALER_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PRESCALER_A::DIV1024 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "No division"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1) + } + #[doc = "Divide by 2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "Divide by 4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "Divide by 8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "Divide by 16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "Divide by 64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "Divide by 256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = "Divide by 1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Prescaler and Counter Synchronization Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCSYNC_A { + #[doc = "0: Reload or reset counter on next GCLK"] + GCLK = 0, + #[doc = "1: Reload or reset counter on next prescaler clock"] + PRESC = 1, + #[doc = "2: Reload or reset counter on next GCLK and reset prescaler counter"] + RESYNC = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCSYNC_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCSYNC` reader - Prescaler and Counter Synchronization Selection"] +pub struct PRESCSYNC_R(crate::FieldReader); +impl PRESCSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCSYNC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCSYNC_A::GCLK), + 1 => Some(PRESCSYNC_A::PRESC), + 2 => Some(PRESCSYNC_A::RESYNC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `GCLK`"] + #[inline(always)] + pub fn is_gclk(&self) -> bool { + **self == PRESCSYNC_A::GCLK + } + #[doc = "Checks if the value of the field is `PRESC`"] + #[inline(always)] + pub fn is_presc(&self) -> bool { + **self == PRESCSYNC_A::PRESC + } + #[doc = "Checks if the value of the field is `RESYNC`"] + #[inline(always)] + pub fn is_resync(&self) -> bool { + **self == PRESCSYNC_A::RESYNC + } +} +impl core::ops::Deref for PRESCSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCSYNC` writer - Prescaler and Counter Synchronization Selection"] +pub struct PRESCSYNC_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCSYNC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCSYNC_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Reload or reset counter on next GCLK"] + #[inline(always)] + pub fn gclk(self) -> &'a mut W { + self.variant(PRESCSYNC_A::GCLK) + } + #[doc = "Reload or reset counter on next prescaler clock"] + #[inline(always)] + pub fn presc(self) -> &'a mut W { + self.variant(PRESCSYNC_A::PRESC) + } + #[doc = "Reload or reset counter on next GCLK and reset prescaler counter"] + #[inline(always)] + pub fn resync(self) -> &'a mut W { + self.variant(PRESCSYNC_A::RESYNC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 12)) | ((value as u32 & 0x03) << 12); + self.w + } +} +#[doc = "Field `ALOCK` reader - Auto Lock"] +pub struct ALOCK_R(crate::FieldReader); +impl ALOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALOCK` writer - Auto Lock"] +pub struct ALOCK_W<'a> { + w: &'a mut W, +} +impl<'a> ALOCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `MSYNC` reader - Master Synchronization (only for TCC Slave Instance)"] +pub struct MSYNC_R(crate::FieldReader); +impl MSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MSYNC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MSYNC` writer - Master Synchronization (only for TCC Slave Instance)"] +pub struct MSYNC_W<'a> { + w: &'a mut W, +} +impl<'a> MSYNC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `DMAOS` reader - DMA One-shot Trigger Mode"] +pub struct DMAOS_R(crate::FieldReader); +impl DMAOS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DMAOS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DMAOS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DMAOS` writer - DMA One-shot Trigger Mode"] +pub struct DMAOS_W<'a> { + w: &'a mut W, +} +impl<'a> DMAOS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `CPTEN0` reader - Capture Channel 0 Enable"] +pub struct CPTEN0_R(crate::FieldReader); +impl CPTEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPTEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CPTEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPTEN0` writer - Capture Channel 0 Enable"] +pub struct CPTEN0_W<'a> { + w: &'a mut W, +} +impl<'a> CPTEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `CPTEN1` reader - Capture Channel 1 Enable"] +pub struct CPTEN1_R(crate::FieldReader); +impl CPTEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPTEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CPTEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPTEN1` writer - Capture Channel 1 Enable"] +pub struct CPTEN1_W<'a> { + w: &'a mut W, +} +impl<'a> CPTEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `CPTEN2` reader - Capture Channel 2 Enable"] +pub struct CPTEN2_R(crate::FieldReader); +impl CPTEN2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPTEN2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CPTEN2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPTEN2` writer - Capture Channel 2 Enable"] +pub struct CPTEN2_W<'a> { + w: &'a mut W, +} +impl<'a> CPTEN2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `CPTEN3` reader - Capture Channel 3 Enable"] +pub struct CPTEN3_R(crate::FieldReader); +impl CPTEN3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPTEN3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CPTEN3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPTEN3` writer - Capture Channel 3 Enable"] +pub struct CPTEN3_W<'a> { + w: &'a mut W, +} +impl<'a> CPTEN3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 5:6 - Enhanced Resolution"] + #[inline(always)] + pub fn resolution(&self) -> RESOLUTION_R { + RESOLUTION_R::new(((self.bits >> 5) & 0x03) as u8) + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 11 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bits 12:13 - Prescaler and Counter Synchronization Selection"] + #[inline(always)] + pub fn prescsync(&self) -> PRESCSYNC_R { + PRESCSYNC_R::new(((self.bits >> 12) & 0x03) as u8) + } + #[doc = "Bit 14 - Auto Lock"] + #[inline(always)] + pub fn alock(&self) -> ALOCK_R { + ALOCK_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Master Synchronization (only for TCC Slave Instance)"] + #[inline(always)] + pub fn msync(&self) -> MSYNC_R { + MSYNC_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 23 - DMA One-shot Trigger Mode"] + #[inline(always)] + pub fn dmaos(&self) -> DMAOS_R { + DMAOS_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn cpten0(&self) -> CPTEN0_R { + CPTEN0_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn cpten1(&self) -> CPTEN1_R { + CPTEN1_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Capture Channel 2 Enable"] + #[inline(always)] + pub fn cpten2(&self) -> CPTEN2_R { + CPTEN2_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Capture Channel 3 Enable"] + #[inline(always)] + pub fn cpten3(&self) -> CPTEN3_R { + CPTEN3_R::new(((self.bits >> 27) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 5:6 - Enhanced Resolution"] + #[inline(always)] + pub fn resolution(&mut self) -> RESOLUTION_W { + RESOLUTION_W { w: self } + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Bit 11 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bits 12:13 - Prescaler and Counter Synchronization Selection"] + #[inline(always)] + pub fn prescsync(&mut self) -> PRESCSYNC_W { + PRESCSYNC_W { w: self } + } + #[doc = "Bit 14 - Auto Lock"] + #[inline(always)] + pub fn alock(&mut self) -> ALOCK_W { + ALOCK_W { w: self } + } + #[doc = "Bit 15 - Master Synchronization (only for TCC Slave Instance)"] + #[inline(always)] + pub fn msync(&mut self) -> MSYNC_W { + MSYNC_W { w: self } + } + #[doc = "Bit 23 - DMA One-shot Trigger Mode"] + #[inline(always)] + pub fn dmaos(&mut self) -> DMAOS_W { + DMAOS_W { w: self } + } + #[doc = "Bit 24 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn cpten0(&mut self) -> CPTEN0_W { + CPTEN0_W { w: self } + } + #[doc = "Bit 25 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn cpten1(&mut self) -> CPTEN1_W { + CPTEN1_W { w: self } + } + #[doc = "Bit 26 - Capture Channel 2 Enable"] + #[inline(always)] + pub fn cpten2(&mut self) -> CPTEN2_W { + CPTEN2_W { w: self } + } + #[doc = "Bit 27 - Capture Channel 3 Enable"] + #[inline(always)] + pub fn cpten3(&mut self) -> CPTEN3_W { + CPTEN3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/tcc0/ctrlbclr.rs b/pac/atsamc20j/src/tcc0/ctrlbclr.rs new file mode 100644 index 000000000000..f96ce81ffde3 --- /dev/null +++ b/pac/atsamc20j/src/tcc0/ctrlbclr.rs @@ -0,0 +1,457 @@ +#[doc = "Register `CTRLBCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Counter Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `LUPD` reader - Lock Update"] +pub struct LUPD_R(crate::FieldReader); +impl LUPD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LUPD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LUPD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LUPD` writer - Lock Update"] +pub struct LUPD_W<'a> { + w: &'a mut W, +} +impl<'a> LUPD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ONESHOT` reader - One-Shot"] +pub struct ONESHOT_R(crate::FieldReader); +impl ONESHOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONESHOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONESHOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONESHOT` writer - One-Shot"] +pub struct ONESHOT_W<'a> { + w: &'a mut W, +} +impl<'a> ONESHOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Ramp Index Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum IDXCMD_A { + #[doc = "0: Command disabled: Index toggles between cycles A and B"] + DISABLE = 0, + #[doc = "1: Set index: cycle B will be forced in the next cycle"] + SET = 1, + #[doc = "2: Clear index: cycle A will be forced in the next cycle"] + CLEAR = 2, + #[doc = "3: Hold index: the next cycle will be the same as the current cycle"] + HOLD = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: IDXCMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `IDXCMD` reader - Ramp Index Command"] +pub struct IDXCMD_R(crate::FieldReader); +impl IDXCMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + IDXCMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> IDXCMD_A { + match self.bits { + 0 => IDXCMD_A::DISABLE, + 1 => IDXCMD_A::SET, + 2 => IDXCMD_A::CLEAR, + 3 => IDXCMD_A::HOLD, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == IDXCMD_A::DISABLE + } + #[doc = "Checks if the value of the field is `SET`"] + #[inline(always)] + pub fn is_set(&self) -> bool { + **self == IDXCMD_A::SET + } + #[doc = "Checks if the value of the field is `CLEAR`"] + #[inline(always)] + pub fn is_clear(&self) -> bool { + **self == IDXCMD_A::CLEAR + } + #[doc = "Checks if the value of the field is `HOLD`"] + #[inline(always)] + pub fn is_hold(&self) -> bool { + **self == IDXCMD_A::HOLD + } +} +impl core::ops::Deref for IDXCMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IDXCMD` writer - Ramp Index Command"] +pub struct IDXCMD_W<'a> { + w: &'a mut W, +} +impl<'a> IDXCMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: IDXCMD_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Command disabled: Index toggles between cycles A and B"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(IDXCMD_A::DISABLE) + } + #[doc = "Set index: cycle B will be forced in the next cycle"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(IDXCMD_A::SET) + } + #[doc = "Clear index: cycle A will be forced in the next cycle"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(IDXCMD_A::CLEAR) + } + #[doc = "Hold index: the next cycle will be the same as the current cycle"] + #[inline(always)] + pub fn hold(self) -> &'a mut W { + self.variant(IDXCMD_A::HOLD) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 3)) | ((value as u8 & 0x03) << 3); + self.w + } +} +#[doc = "TCC Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Clear start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force stop"] + STOP = 2, + #[doc = "3: Force update or double buffered registers"] + UPDATE = 3, + #[doc = "4: Force COUNT read synchronization"] + READSYNC = 4, + #[doc = "5: One-shot DMA trigger"] + DMAOS = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - TCC Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NONE), + 1 => Some(CMD_A::RETRIGGER), + 2 => Some(CMD_A::STOP), + 3 => Some(CMD_A::UPDATE), + 4 => Some(CMD_A::READSYNC), + 5 => Some(CMD_A::DMAOS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == CMD_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == CMD_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == CMD_A::STOP + } + #[doc = "Checks if the value of the field is `UPDATE`"] + #[inline(always)] + pub fn is_update(&self) -> bool { + **self == CMD_A::UPDATE + } + #[doc = "Checks if the value of the field is `READSYNC`"] + #[inline(always)] + pub fn is_readsync(&self) -> bool { + **self == CMD_A::READSYNC + } + #[doc = "Checks if the value of the field is `DMAOS`"] + #[inline(always)] + pub fn is_dmaos(&self) -> bool { + **self == CMD_A::DMAOS + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - TCC Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMD_A::NONE) + } + #[doc = "Clear start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMD_A::RETRIGGER) + } + #[doc = "Force stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMD_A::STOP) + } + #[doc = "Force update or double buffered registers"] + #[inline(always)] + pub fn update(self) -> &'a mut W { + self.variant(CMD_A::UPDATE) + } + #[doc = "Force COUNT read synchronization"] + #[inline(always)] + pub fn readsync(self) -> &'a mut W { + self.variant(CMD_A::READSYNC) + } + #[doc = "One-shot DMA trigger"] + #[inline(always)] + pub fn dmaos(self) -> &'a mut W { + self.variant(CMD_A::DMAOS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 5)) | ((value as u8 & 0x07) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&self) -> LUPD_R { + LUPD_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - One-Shot"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 3:4 - Ramp Index Command"] + #[inline(always)] + pub fn idxcmd(&self) -> IDXCMD_R { + IDXCMD_R::new(((self.bits >> 3) & 0x03) as u8) + } + #[doc = "Bits 5:7 - TCC Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 5) & 0x07) as u8) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&mut self) -> LUPD_W { + LUPD_W { w: self } + } + #[doc = "Bit 2 - One-Shot"] + #[inline(always)] + pub fn oneshot(&mut self) -> ONESHOT_W { + ONESHOT_W { w: self } + } + #[doc = "Bits 3:4 - Ramp Index Command"] + #[inline(always)] + pub fn idxcmd(&mut self) -> IDXCMD_W { + IDXCMD_W { w: self } + } + #[doc = "Bits 5:7 - TCC Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbclr](index.html) module"] +pub struct CTRLBCLR_SPEC; +impl crate::RegisterSpec for CTRLBCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbclr::R](R) reader structure"] +impl crate::Readable for CTRLBCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbclr::W](W) writer structure"] +impl crate::Writable for CTRLBCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLBCLR to value 0"] +impl crate::Resettable for CTRLBCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/tcc0/ctrlbset.rs b/pac/atsamc20j/src/tcc0/ctrlbset.rs new file mode 100644 index 000000000000..7002dd71efe7 --- /dev/null +++ b/pac/atsamc20j/src/tcc0/ctrlbset.rs @@ -0,0 +1,457 @@ +#[doc = "Register `CTRLBSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Counter Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `LUPD` reader - Lock Update"] +pub struct LUPD_R(crate::FieldReader); +impl LUPD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LUPD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LUPD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LUPD` writer - Lock Update"] +pub struct LUPD_W<'a> { + w: &'a mut W, +} +impl<'a> LUPD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ONESHOT` reader - One-Shot"] +pub struct ONESHOT_R(crate::FieldReader); +impl ONESHOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONESHOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONESHOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONESHOT` writer - One-Shot"] +pub struct ONESHOT_W<'a> { + w: &'a mut W, +} +impl<'a> ONESHOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Ramp Index Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum IDXCMD_A { + #[doc = "0: Command disabled: Index toggles between cycles A and B"] + DISABLE = 0, + #[doc = "1: Set index: cycle B will be forced in the next cycle"] + SET = 1, + #[doc = "2: Clear index: cycle A will be forced in the next cycle"] + CLEAR = 2, + #[doc = "3: Hold index: the next cycle will be the same as the current cycle"] + HOLD = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: IDXCMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `IDXCMD` reader - Ramp Index Command"] +pub struct IDXCMD_R(crate::FieldReader); +impl IDXCMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + IDXCMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> IDXCMD_A { + match self.bits { + 0 => IDXCMD_A::DISABLE, + 1 => IDXCMD_A::SET, + 2 => IDXCMD_A::CLEAR, + 3 => IDXCMD_A::HOLD, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == IDXCMD_A::DISABLE + } + #[doc = "Checks if the value of the field is `SET`"] + #[inline(always)] + pub fn is_set(&self) -> bool { + **self == IDXCMD_A::SET + } + #[doc = "Checks if the value of the field is `CLEAR`"] + #[inline(always)] + pub fn is_clear(&self) -> bool { + **self == IDXCMD_A::CLEAR + } + #[doc = "Checks if the value of the field is `HOLD`"] + #[inline(always)] + pub fn is_hold(&self) -> bool { + **self == IDXCMD_A::HOLD + } +} +impl core::ops::Deref for IDXCMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IDXCMD` writer - Ramp Index Command"] +pub struct IDXCMD_W<'a> { + w: &'a mut W, +} +impl<'a> IDXCMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: IDXCMD_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Command disabled: Index toggles between cycles A and B"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(IDXCMD_A::DISABLE) + } + #[doc = "Set index: cycle B will be forced in the next cycle"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(IDXCMD_A::SET) + } + #[doc = "Clear index: cycle A will be forced in the next cycle"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(IDXCMD_A::CLEAR) + } + #[doc = "Hold index: the next cycle will be the same as the current cycle"] + #[inline(always)] + pub fn hold(self) -> &'a mut W { + self.variant(IDXCMD_A::HOLD) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 3)) | ((value as u8 & 0x03) << 3); + self.w + } +} +#[doc = "TCC Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Clear start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force stop"] + STOP = 2, + #[doc = "3: Force update or double buffered registers"] + UPDATE = 3, + #[doc = "4: Force COUNT read synchronization"] + READSYNC = 4, + #[doc = "5: One-shot DMA trigger"] + DMAOS = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - TCC Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NONE), + 1 => Some(CMD_A::RETRIGGER), + 2 => Some(CMD_A::STOP), + 3 => Some(CMD_A::UPDATE), + 4 => Some(CMD_A::READSYNC), + 5 => Some(CMD_A::DMAOS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == CMD_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == CMD_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == CMD_A::STOP + } + #[doc = "Checks if the value of the field is `UPDATE`"] + #[inline(always)] + pub fn is_update(&self) -> bool { + **self == CMD_A::UPDATE + } + #[doc = "Checks if the value of the field is `READSYNC`"] + #[inline(always)] + pub fn is_readsync(&self) -> bool { + **self == CMD_A::READSYNC + } + #[doc = "Checks if the value of the field is `DMAOS`"] + #[inline(always)] + pub fn is_dmaos(&self) -> bool { + **self == CMD_A::DMAOS + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - TCC Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMD_A::NONE) + } + #[doc = "Clear start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMD_A::RETRIGGER) + } + #[doc = "Force stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMD_A::STOP) + } + #[doc = "Force update or double buffered registers"] + #[inline(always)] + pub fn update(self) -> &'a mut W { + self.variant(CMD_A::UPDATE) + } + #[doc = "Force COUNT read synchronization"] + #[inline(always)] + pub fn readsync(self) -> &'a mut W { + self.variant(CMD_A::READSYNC) + } + #[doc = "One-shot DMA trigger"] + #[inline(always)] + pub fn dmaos(self) -> &'a mut W { + self.variant(CMD_A::DMAOS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 5)) | ((value as u8 & 0x07) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&self) -> LUPD_R { + LUPD_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - One-Shot"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 3:4 - Ramp Index Command"] + #[inline(always)] + pub fn idxcmd(&self) -> IDXCMD_R { + IDXCMD_R::new(((self.bits >> 3) & 0x03) as u8) + } + #[doc = "Bits 5:7 - TCC Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 5) & 0x07) as u8) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&mut self) -> LUPD_W { + LUPD_W { w: self } + } + #[doc = "Bit 2 - One-Shot"] + #[inline(always)] + pub fn oneshot(&mut self) -> ONESHOT_W { + ONESHOT_W { w: self } + } + #[doc = "Bits 3:4 - Ramp Index Command"] + #[inline(always)] + pub fn idxcmd(&mut self) -> IDXCMD_W { + IDXCMD_W { w: self } + } + #[doc = "Bits 5:7 - TCC Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbset](index.html) module"] +pub struct CTRLBSET_SPEC; +impl crate::RegisterSpec for CTRLBSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbset::R](R) reader structure"] +impl crate::Readable for CTRLBSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbset::W](W) writer structure"] +impl crate::Writable for CTRLBSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLBSET to value 0"] +impl crate::Resettable for CTRLBSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/tcc0/dbgctrl.rs b/pac/atsamc20j/src/tcc0/dbgctrl.rs new file mode 100644 index 000000000000..313ebe3f5c18 --- /dev/null +++ b/pac/atsamc20j/src/tcc0/dbgctrl.rs @@ -0,0 +1,160 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Debug Running Mode"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Debug Running Mode"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `FDDBD` reader - Fault Detection on Debug Break Detection"] +pub struct FDDBD_R(crate::FieldReader); +impl FDDBD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FDDBD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FDDBD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FDDBD` writer - Fault Detection on Debug Break Detection"] +pub struct FDDBD_W<'a> { + w: &'a mut W, +} +impl<'a> FDDBD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Running Mode"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 2 - Fault Detection on Debug Break Detection"] + #[inline(always)] + pub fn fddbd(&self) -> FDDBD_R { + FDDBD_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Running Mode"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Bit 2 - Fault Detection on Debug Break Detection"] + #[inline(always)] + pub fn fddbd(&mut self) -> FDDBD_W { + FDDBD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/tcc0/drvctrl.rs b/pac/atsamc20j/src/tcc0/drvctrl.rs new file mode 100644 index 000000000000..316041e1e3be --- /dev/null +++ b/pac/atsamc20j/src/tcc0/drvctrl.rs @@ -0,0 +1,1268 @@ +#[doc = "Register `DRVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DRVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `NRE0` reader - Non-Recoverable State 0 Output Enable"] +pub struct NRE0_R(crate::FieldReader); +impl NRE0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRE0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRE0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRE0` writer - Non-Recoverable State 0 Output Enable"] +pub struct NRE0_W<'a> { + w: &'a mut W, +} +impl<'a> NRE0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `NRE1` reader - Non-Recoverable State 1 Output Enable"] +pub struct NRE1_R(crate::FieldReader); +impl NRE1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRE1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRE1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRE1` writer - Non-Recoverable State 1 Output Enable"] +pub struct NRE1_W<'a> { + w: &'a mut W, +} +impl<'a> NRE1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `NRE2` reader - Non-Recoverable State 2 Output Enable"] +pub struct NRE2_R(crate::FieldReader); +impl NRE2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRE2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRE2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRE2` writer - Non-Recoverable State 2 Output Enable"] +pub struct NRE2_W<'a> { + w: &'a mut W, +} +impl<'a> NRE2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `NRE3` reader - Non-Recoverable State 3 Output Enable"] +pub struct NRE3_R(crate::FieldReader); +impl NRE3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRE3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRE3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRE3` writer - Non-Recoverable State 3 Output Enable"] +pub struct NRE3_W<'a> { + w: &'a mut W, +} +impl<'a> NRE3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `NRE4` reader - Non-Recoverable State 4 Output Enable"] +pub struct NRE4_R(crate::FieldReader); +impl NRE4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRE4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRE4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRE4` writer - Non-Recoverable State 4 Output Enable"] +pub struct NRE4_W<'a> { + w: &'a mut W, +} +impl<'a> NRE4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `NRE5` reader - Non-Recoverable State 5 Output Enable"] +pub struct NRE5_R(crate::FieldReader); +impl NRE5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRE5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRE5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRE5` writer - Non-Recoverable State 5 Output Enable"] +pub struct NRE5_W<'a> { + w: &'a mut W, +} +impl<'a> NRE5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `NRE6` reader - Non-Recoverable State 6 Output Enable"] +pub struct NRE6_R(crate::FieldReader); +impl NRE6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRE6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRE6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRE6` writer - Non-Recoverable State 6 Output Enable"] +pub struct NRE6_W<'a> { + w: &'a mut W, +} +impl<'a> NRE6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `NRE7` reader - Non-Recoverable State 7 Output Enable"] +pub struct NRE7_R(crate::FieldReader); +impl NRE7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRE7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRE7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRE7` writer - Non-Recoverable State 7 Output Enable"] +pub struct NRE7_W<'a> { + w: &'a mut W, +} +impl<'a> NRE7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `NRV0` reader - Non-Recoverable State 0 Output Value"] +pub struct NRV0_R(crate::FieldReader); +impl NRV0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRV0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRV0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRV0` writer - Non-Recoverable State 0 Output Value"] +pub struct NRV0_W<'a> { + w: &'a mut W, +} +impl<'a> NRV0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `NRV1` reader - Non-Recoverable State 1 Output Value"] +pub struct NRV1_R(crate::FieldReader); +impl NRV1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRV1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRV1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRV1` writer - Non-Recoverable State 1 Output Value"] +pub struct NRV1_W<'a> { + w: &'a mut W, +} +impl<'a> NRV1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `NRV2` reader - Non-Recoverable State 2 Output Value"] +pub struct NRV2_R(crate::FieldReader); +impl NRV2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRV2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRV2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRV2` writer - Non-Recoverable State 2 Output Value"] +pub struct NRV2_W<'a> { + w: &'a mut W, +} +impl<'a> NRV2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `NRV3` reader - Non-Recoverable State 3 Output Value"] +pub struct NRV3_R(crate::FieldReader); +impl NRV3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRV3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRV3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRV3` writer - Non-Recoverable State 3 Output Value"] +pub struct NRV3_W<'a> { + w: &'a mut W, +} +impl<'a> NRV3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `NRV4` reader - Non-Recoverable State 4 Output Value"] +pub struct NRV4_R(crate::FieldReader); +impl NRV4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRV4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRV4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRV4` writer - Non-Recoverable State 4 Output Value"] +pub struct NRV4_W<'a> { + w: &'a mut W, +} +impl<'a> NRV4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `NRV5` reader - Non-Recoverable State 5 Output Value"] +pub struct NRV5_R(crate::FieldReader); +impl NRV5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRV5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRV5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRV5` writer - Non-Recoverable State 5 Output Value"] +pub struct NRV5_W<'a> { + w: &'a mut W, +} +impl<'a> NRV5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `NRV6` reader - Non-Recoverable State 6 Output Value"] +pub struct NRV6_R(crate::FieldReader); +impl NRV6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRV6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRV6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRV6` writer - Non-Recoverable State 6 Output Value"] +pub struct NRV6_W<'a> { + w: &'a mut W, +} +impl<'a> NRV6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `NRV7` reader - Non-Recoverable State 7 Output Value"] +pub struct NRV7_R(crate::FieldReader); +impl NRV7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRV7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRV7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRV7` writer - Non-Recoverable State 7 Output Value"] +pub struct NRV7_W<'a> { + w: &'a mut W, +} +impl<'a> NRV7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `INVEN0` reader - Output Waveform 0 Inversion"] +pub struct INVEN0_R(crate::FieldReader); +impl INVEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN0` writer - Output Waveform 0 Inversion"] +pub struct INVEN0_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `INVEN1` reader - Output Waveform 1 Inversion"] +pub struct INVEN1_R(crate::FieldReader); +impl INVEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN1` writer - Output Waveform 1 Inversion"] +pub struct INVEN1_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `INVEN2` reader - Output Waveform 2 Inversion"] +pub struct INVEN2_R(crate::FieldReader); +impl INVEN2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN2` writer - Output Waveform 2 Inversion"] +pub struct INVEN2_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `INVEN3` reader - Output Waveform 3 Inversion"] +pub struct INVEN3_R(crate::FieldReader); +impl INVEN3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN3` writer - Output Waveform 3 Inversion"] +pub struct INVEN3_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `INVEN4` reader - Output Waveform 4 Inversion"] +pub struct INVEN4_R(crate::FieldReader); +impl INVEN4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN4` writer - Output Waveform 4 Inversion"] +pub struct INVEN4_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `INVEN5` reader - Output Waveform 5 Inversion"] +pub struct INVEN5_R(crate::FieldReader); +impl INVEN5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN5` writer - Output Waveform 5 Inversion"] +pub struct INVEN5_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `INVEN6` reader - Output Waveform 6 Inversion"] +pub struct INVEN6_R(crate::FieldReader); +impl INVEN6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN6` writer - Output Waveform 6 Inversion"] +pub struct INVEN6_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `INVEN7` reader - Output Waveform 7 Inversion"] +pub struct INVEN7_R(crate::FieldReader); +impl INVEN7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN7` writer - Output Waveform 7 Inversion"] +pub struct INVEN7_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `FILTERVAL0` reader - Non-Recoverable Fault Input 0 Filter Value"] +pub struct FILTERVAL0_R(crate::FieldReader); +impl FILTERVAL0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FILTERVAL0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTERVAL0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTERVAL0` writer - Non-Recoverable Fault Input 0 Filter Value"] +pub struct FILTERVAL0_W<'a> { + w: &'a mut W, +} +impl<'a> FILTERVAL0_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Field `FILTERVAL1` reader - Non-Recoverable Fault Input 1 Filter Value"] +pub struct FILTERVAL1_R(crate::FieldReader); +impl FILTERVAL1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FILTERVAL1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTERVAL1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTERVAL1` writer - Non-Recoverable Fault Input 1 Filter Value"] +pub struct FILTERVAL1_W<'a> { + w: &'a mut W, +} +impl<'a> FILTERVAL1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 28)) | ((value as u32 & 0x0f) << 28); + self.w + } +} +impl R { + #[doc = "Bit 0 - Non-Recoverable State 0 Output Enable"] + #[inline(always)] + pub fn nre0(&self) -> NRE0_R { + NRE0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Non-Recoverable State 1 Output Enable"] + #[inline(always)] + pub fn nre1(&self) -> NRE1_R { + NRE1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Non-Recoverable State 2 Output Enable"] + #[inline(always)] + pub fn nre2(&self) -> NRE2_R { + NRE2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Non-Recoverable State 3 Output Enable"] + #[inline(always)] + pub fn nre3(&self) -> NRE3_R { + NRE3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Non-Recoverable State 4 Output Enable"] + #[inline(always)] + pub fn nre4(&self) -> NRE4_R { + NRE4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Non-Recoverable State 5 Output Enable"] + #[inline(always)] + pub fn nre5(&self) -> NRE5_R { + NRE5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Non-Recoverable State 6 Output Enable"] + #[inline(always)] + pub fn nre6(&self) -> NRE6_R { + NRE6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Non-Recoverable State 7 Output Enable"] + #[inline(always)] + pub fn nre7(&self) -> NRE7_R { + NRE7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Non-Recoverable State 0 Output Value"] + #[inline(always)] + pub fn nrv0(&self) -> NRV0_R { + NRV0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Non-Recoverable State 1 Output Value"] + #[inline(always)] + pub fn nrv1(&self) -> NRV1_R { + NRV1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Non-Recoverable State 2 Output Value"] + #[inline(always)] + pub fn nrv2(&self) -> NRV2_R { + NRV2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Non-Recoverable State 3 Output Value"] + #[inline(always)] + pub fn nrv3(&self) -> NRV3_R { + NRV3_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Non-Recoverable State 4 Output Value"] + #[inline(always)] + pub fn nrv4(&self) -> NRV4_R { + NRV4_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Non-Recoverable State 5 Output Value"] + #[inline(always)] + pub fn nrv5(&self) -> NRV5_R { + NRV5_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Non-Recoverable State 6 Output Value"] + #[inline(always)] + pub fn nrv6(&self) -> NRV6_R { + NRV6_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Non-Recoverable State 7 Output Value"] + #[inline(always)] + pub fn nrv7(&self) -> NRV7_R { + NRV7_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Output Waveform 0 Inversion"] + #[inline(always)] + pub fn inven0(&self) -> INVEN0_R { + INVEN0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Output Waveform 1 Inversion"] + #[inline(always)] + pub fn inven1(&self) -> INVEN1_R { + INVEN1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Output Waveform 2 Inversion"] + #[inline(always)] + pub fn inven2(&self) -> INVEN2_R { + INVEN2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Output Waveform 3 Inversion"] + #[inline(always)] + pub fn inven3(&self) -> INVEN3_R { + INVEN3_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Output Waveform 4 Inversion"] + #[inline(always)] + pub fn inven4(&self) -> INVEN4_R { + INVEN4_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Output Waveform 5 Inversion"] + #[inline(always)] + pub fn inven5(&self) -> INVEN5_R { + INVEN5_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Output Waveform 6 Inversion"] + #[inline(always)] + pub fn inven6(&self) -> INVEN6_R { + INVEN6_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Output Waveform 7 Inversion"] + #[inline(always)] + pub fn inven7(&self) -> INVEN7_R { + INVEN7_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bits 24:27 - Non-Recoverable Fault Input 0 Filter Value"] + #[inline(always)] + pub fn filterval0(&self) -> FILTERVAL0_R { + FILTERVAL0_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bits 28:31 - Non-Recoverable Fault Input 1 Filter Value"] + #[inline(always)] + pub fn filterval1(&self) -> FILTERVAL1_R { + FILTERVAL1_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bit 0 - Non-Recoverable State 0 Output Enable"] + #[inline(always)] + pub fn nre0(&mut self) -> NRE0_W { + NRE0_W { w: self } + } + #[doc = "Bit 1 - Non-Recoverable State 1 Output Enable"] + #[inline(always)] + pub fn nre1(&mut self) -> NRE1_W { + NRE1_W { w: self } + } + #[doc = "Bit 2 - Non-Recoverable State 2 Output Enable"] + #[inline(always)] + pub fn nre2(&mut self) -> NRE2_W { + NRE2_W { w: self } + } + #[doc = "Bit 3 - Non-Recoverable State 3 Output Enable"] + #[inline(always)] + pub fn nre3(&mut self) -> NRE3_W { + NRE3_W { w: self } + } + #[doc = "Bit 4 - Non-Recoverable State 4 Output Enable"] + #[inline(always)] + pub fn nre4(&mut self) -> NRE4_W { + NRE4_W { w: self } + } + #[doc = "Bit 5 - Non-Recoverable State 5 Output Enable"] + #[inline(always)] + pub fn nre5(&mut self) -> NRE5_W { + NRE5_W { w: self } + } + #[doc = "Bit 6 - Non-Recoverable State 6 Output Enable"] + #[inline(always)] + pub fn nre6(&mut self) -> NRE6_W { + NRE6_W { w: self } + } + #[doc = "Bit 7 - Non-Recoverable State 7 Output Enable"] + #[inline(always)] + pub fn nre7(&mut self) -> NRE7_W { + NRE7_W { w: self } + } + #[doc = "Bit 8 - Non-Recoverable State 0 Output Value"] + #[inline(always)] + pub fn nrv0(&mut self) -> NRV0_W { + NRV0_W { w: self } + } + #[doc = "Bit 9 - Non-Recoverable State 1 Output Value"] + #[inline(always)] + pub fn nrv1(&mut self) -> NRV1_W { + NRV1_W { w: self } + } + #[doc = "Bit 10 - Non-Recoverable State 2 Output Value"] + #[inline(always)] + pub fn nrv2(&mut self) -> NRV2_W { + NRV2_W { w: self } + } + #[doc = "Bit 11 - Non-Recoverable State 3 Output Value"] + #[inline(always)] + pub fn nrv3(&mut self) -> NRV3_W { + NRV3_W { w: self } + } + #[doc = "Bit 12 - Non-Recoverable State 4 Output Value"] + #[inline(always)] + pub fn nrv4(&mut self) -> NRV4_W { + NRV4_W { w: self } + } + #[doc = "Bit 13 - Non-Recoverable State 5 Output Value"] + #[inline(always)] + pub fn nrv5(&mut self) -> NRV5_W { + NRV5_W { w: self } + } + #[doc = "Bit 14 - Non-Recoverable State 6 Output Value"] + #[inline(always)] + pub fn nrv6(&mut self) -> NRV6_W { + NRV6_W { w: self } + } + #[doc = "Bit 15 - Non-Recoverable State 7 Output Value"] + #[inline(always)] + pub fn nrv7(&mut self) -> NRV7_W { + NRV7_W { w: self } + } + #[doc = "Bit 16 - Output Waveform 0 Inversion"] + #[inline(always)] + pub fn inven0(&mut self) -> INVEN0_W { + INVEN0_W { w: self } + } + #[doc = "Bit 17 - Output Waveform 1 Inversion"] + #[inline(always)] + pub fn inven1(&mut self) -> INVEN1_W { + INVEN1_W { w: self } + } + #[doc = "Bit 18 - Output Waveform 2 Inversion"] + #[inline(always)] + pub fn inven2(&mut self) -> INVEN2_W { + INVEN2_W { w: self } + } + #[doc = "Bit 19 - Output Waveform 3 Inversion"] + #[inline(always)] + pub fn inven3(&mut self) -> INVEN3_W { + INVEN3_W { w: self } + } + #[doc = "Bit 20 - Output Waveform 4 Inversion"] + #[inline(always)] + pub fn inven4(&mut self) -> INVEN4_W { + INVEN4_W { w: self } + } + #[doc = "Bit 21 - Output Waveform 5 Inversion"] + #[inline(always)] + pub fn inven5(&mut self) -> INVEN5_W { + INVEN5_W { w: self } + } + #[doc = "Bit 22 - Output Waveform 6 Inversion"] + #[inline(always)] + pub fn inven6(&mut self) -> INVEN6_W { + INVEN6_W { w: self } + } + #[doc = "Bit 23 - Output Waveform 7 Inversion"] + #[inline(always)] + pub fn inven7(&mut self) -> INVEN7_W { + INVEN7_W { w: self } + } + #[doc = "Bits 24:27 - Non-Recoverable Fault Input 0 Filter Value"] + #[inline(always)] + pub fn filterval0(&mut self) -> FILTERVAL0_W { + FILTERVAL0_W { w: self } + } + #[doc = "Bits 28:31 - Non-Recoverable Fault Input 1 Filter Value"] + #[inline(always)] + pub fn filterval1(&mut self) -> FILTERVAL1_W { + FILTERVAL1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Driver Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [drvctrl](index.html) module"] +pub struct DRVCTRL_SPEC; +impl crate::RegisterSpec for DRVCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [drvctrl::R](R) reader structure"] +impl crate::Readable for DRVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [drvctrl::W](W) writer structure"] +impl crate::Writable for DRVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DRVCTRL to value 0"] +impl crate::Resettable for DRVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/tcc0/evctrl.rs b/pac/atsamc20j/src/tcc0/evctrl.rs new file mode 100644 index 000000000000..334a53924d61 --- /dev/null +++ b/pac/atsamc20j/src/tcc0/evctrl.rs @@ -0,0 +1,1211 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Timer/counter Input Event0 Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EVACT0_A { + #[doc = "0: Event action disabled"] + OFF = 0, + #[doc = "1: Start, restart or re-trigger counter on event"] + RETRIGGER = 1, + #[doc = "2: Count on event"] + COUNTEV = 2, + #[doc = "3: Start counter on event"] + START = 3, + #[doc = "4: Increment counter on event"] + INC = 4, + #[doc = "5: Count on active state of asynchronous event"] + COUNT = 5, + #[doc = "6: Stamp capture"] + STAMP = 6, + #[doc = "7: Non-recoverable fault"] + FAULT = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EVACT0_A) -> Self { + variant as _ + } +} +#[doc = "Field `EVACT0` reader - Timer/counter Input Event0 Action"] +pub struct EVACT0_R(crate::FieldReader); +impl EVACT0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVACT0_A { + match self.bits { + 0 => EVACT0_A::OFF, + 1 => EVACT0_A::RETRIGGER, + 2 => EVACT0_A::COUNTEV, + 3 => EVACT0_A::START, + 4 => EVACT0_A::INC, + 5 => EVACT0_A::COUNT, + 6 => EVACT0_A::STAMP, + 7 => EVACT0_A::FAULT, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == EVACT0_A::OFF + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == EVACT0_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `COUNTEV`"] + #[inline(always)] + pub fn is_countev(&self) -> bool { + **self == EVACT0_A::COUNTEV + } + #[doc = "Checks if the value of the field is `START`"] + #[inline(always)] + pub fn is_start(&self) -> bool { + **self == EVACT0_A::START + } + #[doc = "Checks if the value of the field is `INC`"] + #[inline(always)] + pub fn is_inc(&self) -> bool { + **self == EVACT0_A::INC + } + #[doc = "Checks if the value of the field is `COUNT`"] + #[inline(always)] + pub fn is_count(&self) -> bool { + **self == EVACT0_A::COUNT + } + #[doc = "Checks if the value of the field is `STAMP`"] + #[inline(always)] + pub fn is_stamp(&self) -> bool { + **self == EVACT0_A::STAMP + } + #[doc = "Checks if the value of the field is `FAULT`"] + #[inline(always)] + pub fn is_fault(&self) -> bool { + **self == EVACT0_A::FAULT + } +} +impl core::ops::Deref for EVACT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT0` writer - Timer/counter Input Event0 Action"] +pub struct EVACT0_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT0_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EVACT0_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Event action disabled"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(EVACT0_A::OFF) + } + #[doc = "Start, restart or re-trigger counter on event"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(EVACT0_A::RETRIGGER) + } + #[doc = "Count on event"] + #[inline(always)] + pub fn countev(self) -> &'a mut W { + self.variant(EVACT0_A::COUNTEV) + } + #[doc = "Start counter on event"] + #[inline(always)] + pub fn start(self) -> &'a mut W { + self.variant(EVACT0_A::START) + } + #[doc = "Increment counter on event"] + #[inline(always)] + pub fn inc(self) -> &'a mut W { + self.variant(EVACT0_A::INC) + } + #[doc = "Count on active state of asynchronous event"] + #[inline(always)] + pub fn count(self) -> &'a mut W { + self.variant(EVACT0_A::COUNT) + } + #[doc = "Stamp capture"] + #[inline(always)] + pub fn stamp(self) -> &'a mut W { + self.variant(EVACT0_A::STAMP) + } + #[doc = "Non-recoverable fault"] + #[inline(always)] + pub fn fault(self) -> &'a mut W { + self.variant(EVACT0_A::FAULT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Timer/counter Input Event1 Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EVACT1_A { + #[doc = "0: Event action disabled"] + OFF = 0, + #[doc = "1: Re-trigger counter on event"] + RETRIGGER = 1, + #[doc = "2: Direction control"] + DIR = 2, + #[doc = "3: Stop counter on event"] + STOP = 3, + #[doc = "4: Decrement counter on event"] + DEC = 4, + #[doc = "5: Period capture value in CC0 register, pulse width capture value in CC1 register"] + PPW = 5, + #[doc = "6: Period capture value in CC1 register, pulse width capture value in CC0 register"] + PWP = 6, + #[doc = "7: Non-recoverable fault"] + FAULT = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EVACT1_A) -> Self { + variant as _ + } +} +#[doc = "Field `EVACT1` reader - Timer/counter Input Event1 Action"] +pub struct EVACT1_R(crate::FieldReader); +impl EVACT1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT1_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVACT1_A { + match self.bits { + 0 => EVACT1_A::OFF, + 1 => EVACT1_A::RETRIGGER, + 2 => EVACT1_A::DIR, + 3 => EVACT1_A::STOP, + 4 => EVACT1_A::DEC, + 5 => EVACT1_A::PPW, + 6 => EVACT1_A::PWP, + 7 => EVACT1_A::FAULT, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == EVACT1_A::OFF + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == EVACT1_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `DIR`"] + #[inline(always)] + pub fn is_dir(&self) -> bool { + **self == EVACT1_A::DIR + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == EVACT1_A::STOP + } + #[doc = "Checks if the value of the field is `DEC`"] + #[inline(always)] + pub fn is_dec(&self) -> bool { + **self == EVACT1_A::DEC + } + #[doc = "Checks if the value of the field is `PPW`"] + #[inline(always)] + pub fn is_ppw(&self) -> bool { + **self == EVACT1_A::PPW + } + #[doc = "Checks if the value of the field is `PWP`"] + #[inline(always)] + pub fn is_pwp(&self) -> bool { + **self == EVACT1_A::PWP + } + #[doc = "Checks if the value of the field is `FAULT`"] + #[inline(always)] + pub fn is_fault(&self) -> bool { + **self == EVACT1_A::FAULT + } +} +impl core::ops::Deref for EVACT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT1` writer - Timer/counter Input Event1 Action"] +pub struct EVACT1_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT1_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EVACT1_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Event action disabled"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(EVACT1_A::OFF) + } + #[doc = "Re-trigger counter on event"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(EVACT1_A::RETRIGGER) + } + #[doc = "Direction control"] + #[inline(always)] + pub fn dir(self) -> &'a mut W { + self.variant(EVACT1_A::DIR) + } + #[doc = "Stop counter on event"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(EVACT1_A::STOP) + } + #[doc = "Decrement counter on event"] + #[inline(always)] + pub fn dec(self) -> &'a mut W { + self.variant(EVACT1_A::DEC) + } + #[doc = "Period capture value in CC0 register, pulse width capture value in CC1 register"] + #[inline(always)] + pub fn ppw(self) -> &'a mut W { + self.variant(EVACT1_A::PPW) + } + #[doc = "Period capture value in CC1 register, pulse width capture value in CC0 register"] + #[inline(always)] + pub fn pwp(self) -> &'a mut W { + self.variant(EVACT1_A::PWP) + } + #[doc = "Non-recoverable fault"] + #[inline(always)] + pub fn fault(self) -> &'a mut W { + self.variant(EVACT1_A::FAULT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 3)) | ((value as u32 & 0x07) << 3); + self.w + } +} +#[doc = "Timer/counter Output Event Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CNTSEL_A { + #[doc = "0: An interrupt/event is generated when a new counter cycle starts"] + START = 0, + #[doc = "1: An interrupt/event is generated when a counter cycle ends"] + END = 1, + #[doc = "2: An interrupt/event is generated when a counter cycle ends, except for the first and last cycles"] + BETWEEN = 2, + #[doc = "3: An interrupt/event is generated when a new counter cycle starts or a counter cycle ends"] + BOUNDARY = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CNTSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `CNTSEL` reader - Timer/counter Output Event Mode"] +pub struct CNTSEL_R(crate::FieldReader); +impl CNTSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CNTSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CNTSEL_A { + match self.bits { + 0 => CNTSEL_A::START, + 1 => CNTSEL_A::END, + 2 => CNTSEL_A::BETWEEN, + 3 => CNTSEL_A::BOUNDARY, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `START`"] + #[inline(always)] + pub fn is_start(&self) -> bool { + **self == CNTSEL_A::START + } + #[doc = "Checks if the value of the field is `END`"] + #[inline(always)] + pub fn is_end(&self) -> bool { + **self == CNTSEL_A::END + } + #[doc = "Checks if the value of the field is `BETWEEN`"] + #[inline(always)] + pub fn is_between(&self) -> bool { + **self == CNTSEL_A::BETWEEN + } + #[doc = "Checks if the value of the field is `BOUNDARY`"] + #[inline(always)] + pub fn is_boundary(&self) -> bool { + **self == CNTSEL_A::BOUNDARY + } +} +impl core::ops::Deref for CNTSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CNTSEL` writer - Timer/counter Output Event Mode"] +pub struct CNTSEL_W<'a> { + w: &'a mut W, +} +impl<'a> CNTSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CNTSEL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "An interrupt/event is generated when a new counter cycle starts"] + #[inline(always)] + pub fn start(self) -> &'a mut W { + self.variant(CNTSEL_A::START) + } + #[doc = "An interrupt/event is generated when a counter cycle ends"] + #[inline(always)] + pub fn end(self) -> &'a mut W { + self.variant(CNTSEL_A::END) + } + #[doc = "An interrupt/event is generated when a counter cycle ends, except for the first and last cycles"] + #[inline(always)] + pub fn between(self) -> &'a mut W { + self.variant(CNTSEL_A::BETWEEN) + } + #[doc = "An interrupt/event is generated when a new counter cycle starts or a counter cycle ends"] + #[inline(always)] + pub fn boundary(self) -> &'a mut W { + self.variant(CNTSEL_A::BOUNDARY) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 6)) | ((value as u32 & 0x03) << 6); + self.w + } +} +#[doc = "Field `OVFEO` reader - Overflow/Underflow Output Event Enable"] +pub struct OVFEO_R(crate::FieldReader); +impl OVFEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVFEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVFEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVFEO` writer - Overflow/Underflow Output Event Enable"] +pub struct OVFEO_W<'a> { + w: &'a mut W, +} +impl<'a> OVFEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `TRGEO` reader - Retrigger Output Event Enable"] +pub struct TRGEO_R(crate::FieldReader); +impl TRGEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRGEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRGEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRGEO` writer - Retrigger Output Event Enable"] +pub struct TRGEO_W<'a> { + w: &'a mut W, +} +impl<'a> TRGEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `CNTEO` reader - Timer/counter Output Event Enable"] +pub struct CNTEO_R(crate::FieldReader); +impl CNTEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CNTEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CNTEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CNTEO` writer - Timer/counter Output Event Enable"] +pub struct CNTEO_W<'a> { + w: &'a mut W, +} +impl<'a> CNTEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `TCINV0` reader - Inverted Event 0 Input Enable"] +pub struct TCINV0_R(crate::FieldReader); +impl TCINV0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCINV0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCINV0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCINV0` writer - Inverted Event 0 Input Enable"] +pub struct TCINV0_W<'a> { + w: &'a mut W, +} +impl<'a> TCINV0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `TCINV1` reader - Inverted Event 1 Input Enable"] +pub struct TCINV1_R(crate::FieldReader); +impl TCINV1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCINV1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCINV1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCINV1` writer - Inverted Event 1 Input Enable"] +pub struct TCINV1_W<'a> { + w: &'a mut W, +} +impl<'a> TCINV1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `TCEI0` reader - Timer/counter Event 0 Input Enable"] +pub struct TCEI0_R(crate::FieldReader); +impl TCEI0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCEI0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCEI0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCEI0` writer - Timer/counter Event 0 Input Enable"] +pub struct TCEI0_W<'a> { + w: &'a mut W, +} +impl<'a> TCEI0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `TCEI1` reader - Timer/counter Event 1 Input Enable"] +pub struct TCEI1_R(crate::FieldReader); +impl TCEI1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCEI1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCEI1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCEI1` writer - Timer/counter Event 1 Input Enable"] +pub struct TCEI1_W<'a> { + w: &'a mut W, +} +impl<'a> TCEI1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `MCEI0` reader - Match or Capture Channel 0 Event Input Enable"] +pub struct MCEI0_R(crate::FieldReader); +impl MCEI0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEI0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEI0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEI0` writer - Match or Capture Channel 0 Event Input Enable"] +pub struct MCEI0_W<'a> { + w: &'a mut W, +} +impl<'a> MCEI0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `MCEI1` reader - Match or Capture Channel 1 Event Input Enable"] +pub struct MCEI1_R(crate::FieldReader); +impl MCEI1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEI1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEI1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEI1` writer - Match or Capture Channel 1 Event Input Enable"] +pub struct MCEI1_W<'a> { + w: &'a mut W, +} +impl<'a> MCEI1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `MCEI2` reader - Match or Capture Channel 2 Event Input Enable"] +pub struct MCEI2_R(crate::FieldReader); +impl MCEI2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEI2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEI2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEI2` writer - Match or Capture Channel 2 Event Input Enable"] +pub struct MCEI2_W<'a> { + w: &'a mut W, +} +impl<'a> MCEI2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `MCEI3` reader - Match or Capture Channel 3 Event Input Enable"] +pub struct MCEI3_R(crate::FieldReader); +impl MCEI3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEI3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEI3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEI3` writer - Match or Capture Channel 3 Event Input Enable"] +pub struct MCEI3_W<'a> { + w: &'a mut W, +} +impl<'a> MCEI3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `MCEO0` reader - Match or Capture Channel 0 Event Output Enable"] +pub struct MCEO0_R(crate::FieldReader); +impl MCEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO0` writer - Match or Capture Channel 0 Event Output Enable"] +pub struct MCEO0_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `MCEO1` reader - Match or Capture Channel 1 Event Output Enable"] +pub struct MCEO1_R(crate::FieldReader); +impl MCEO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO1` writer - Match or Capture Channel 1 Event Output Enable"] +pub struct MCEO1_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `MCEO2` reader - Match or Capture Channel 2 Event Output Enable"] +pub struct MCEO2_R(crate::FieldReader); +impl MCEO2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO2` writer - Match or Capture Channel 2 Event Output Enable"] +pub struct MCEO2_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `MCEO3` reader - Match or Capture Channel 3 Event Output Enable"] +pub struct MCEO3_R(crate::FieldReader); +impl MCEO3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO3` writer - Match or Capture Channel 3 Event Output Enable"] +pub struct MCEO3_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Timer/counter Input Event0 Action"] + #[inline(always)] + pub fn evact0(&self) -> EVACT0_R { + EVACT0_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bits 3:5 - Timer/counter Input Event1 Action"] + #[inline(always)] + pub fn evact1(&self) -> EVACT1_R { + EVACT1_R::new(((self.bits >> 3) & 0x07) as u8) + } + #[doc = "Bits 6:7 - Timer/counter Output Event Mode"] + #[inline(always)] + pub fn cntsel(&self) -> CNTSEL_R { + CNTSEL_R::new(((self.bits >> 6) & 0x03) as u8) + } + #[doc = "Bit 8 - Overflow/Underflow Output Event Enable"] + #[inline(always)] + pub fn ovfeo(&self) -> OVFEO_R { + OVFEO_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Retrigger Output Event Enable"] + #[inline(always)] + pub fn trgeo(&self) -> TRGEO_R { + TRGEO_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Timer/counter Output Event Enable"] + #[inline(always)] + pub fn cnteo(&self) -> CNTEO_R { + CNTEO_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 12 - Inverted Event 0 Input Enable"] + #[inline(always)] + pub fn tcinv0(&self) -> TCINV0_R { + TCINV0_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Inverted Event 1 Input Enable"] + #[inline(always)] + pub fn tcinv1(&self) -> TCINV1_R { + TCINV1_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Timer/counter Event 0 Input Enable"] + #[inline(always)] + pub fn tcei0(&self) -> TCEI0_R { + TCEI0_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Timer/counter Event 1 Input Enable"] + #[inline(always)] + pub fn tcei1(&self) -> TCEI1_R { + TCEI1_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Match or Capture Channel 0 Event Input Enable"] + #[inline(always)] + pub fn mcei0(&self) -> MCEI0_R { + MCEI0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Match or Capture Channel 1 Event Input Enable"] + #[inline(always)] + pub fn mcei1(&self) -> MCEI1_R { + MCEI1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Match or Capture Channel 2 Event Input Enable"] + #[inline(always)] + pub fn mcei2(&self) -> MCEI2_R { + MCEI2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Match or Capture Channel 3 Event Input Enable"] + #[inline(always)] + pub fn mcei3(&self) -> MCEI3_R { + MCEI3_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 24 - Match or Capture Channel 0 Event Output Enable"] + #[inline(always)] + pub fn mceo0(&self) -> MCEO0_R { + MCEO0_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Match or Capture Channel 1 Event Output Enable"] + #[inline(always)] + pub fn mceo1(&self) -> MCEO1_R { + MCEO1_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Match or Capture Channel 2 Event Output Enable"] + #[inline(always)] + pub fn mceo2(&self) -> MCEO2_R { + MCEO2_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Match or Capture Channel 3 Event Output Enable"] + #[inline(always)] + pub fn mceo3(&self) -> MCEO3_R { + MCEO3_R::new(((self.bits >> 27) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Timer/counter Input Event0 Action"] + #[inline(always)] + pub fn evact0(&mut self) -> EVACT0_W { + EVACT0_W { w: self } + } + #[doc = "Bits 3:5 - Timer/counter Input Event1 Action"] + #[inline(always)] + pub fn evact1(&mut self) -> EVACT1_W { + EVACT1_W { w: self } + } + #[doc = "Bits 6:7 - Timer/counter Output Event Mode"] + #[inline(always)] + pub fn cntsel(&mut self) -> CNTSEL_W { + CNTSEL_W { w: self } + } + #[doc = "Bit 8 - Overflow/Underflow Output Event Enable"] + #[inline(always)] + pub fn ovfeo(&mut self) -> OVFEO_W { + OVFEO_W { w: self } + } + #[doc = "Bit 9 - Retrigger Output Event Enable"] + #[inline(always)] + pub fn trgeo(&mut self) -> TRGEO_W { + TRGEO_W { w: self } + } + #[doc = "Bit 10 - Timer/counter Output Event Enable"] + #[inline(always)] + pub fn cnteo(&mut self) -> CNTEO_W { + CNTEO_W { w: self } + } + #[doc = "Bit 12 - Inverted Event 0 Input Enable"] + #[inline(always)] + pub fn tcinv0(&mut self) -> TCINV0_W { + TCINV0_W { w: self } + } + #[doc = "Bit 13 - Inverted Event 1 Input Enable"] + #[inline(always)] + pub fn tcinv1(&mut self) -> TCINV1_W { + TCINV1_W { w: self } + } + #[doc = "Bit 14 - Timer/counter Event 0 Input Enable"] + #[inline(always)] + pub fn tcei0(&mut self) -> TCEI0_W { + TCEI0_W { w: self } + } + #[doc = "Bit 15 - Timer/counter Event 1 Input Enable"] + #[inline(always)] + pub fn tcei1(&mut self) -> TCEI1_W { + TCEI1_W { w: self } + } + #[doc = "Bit 16 - Match or Capture Channel 0 Event Input Enable"] + #[inline(always)] + pub fn mcei0(&mut self) -> MCEI0_W { + MCEI0_W { w: self } + } + #[doc = "Bit 17 - Match or Capture Channel 1 Event Input Enable"] + #[inline(always)] + pub fn mcei1(&mut self) -> MCEI1_W { + MCEI1_W { w: self } + } + #[doc = "Bit 18 - Match or Capture Channel 2 Event Input Enable"] + #[inline(always)] + pub fn mcei2(&mut self) -> MCEI2_W { + MCEI2_W { w: self } + } + #[doc = "Bit 19 - Match or Capture Channel 3 Event Input Enable"] + #[inline(always)] + pub fn mcei3(&mut self) -> MCEI3_W { + MCEI3_W { w: self } + } + #[doc = "Bit 24 - Match or Capture Channel 0 Event Output Enable"] + #[inline(always)] + pub fn mceo0(&mut self) -> MCEO0_W { + MCEO0_W { w: self } + } + #[doc = "Bit 25 - Match or Capture Channel 1 Event Output Enable"] + #[inline(always)] + pub fn mceo1(&mut self) -> MCEO1_W { + MCEO1_W { w: self } + } + #[doc = "Bit 26 - Match or Capture Channel 2 Event Output Enable"] + #[inline(always)] + pub fn mceo2(&mut self) -> MCEO2_W { + MCEO2_W { w: self } + } + #[doc = "Bit 27 - Match or Capture Channel 3 Event Output Enable"] + #[inline(always)] + pub fn mceo3(&mut self) -> MCEO3_W { + MCEO3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/tcc0/fctrla.rs b/pac/atsamc20j/src/tcc0/fctrla.rs new file mode 100644 index 000000000000..77c7276fee23 --- /dev/null +++ b/pac/atsamc20j/src/tcc0/fctrla.rs @@ -0,0 +1,940 @@ +#[doc = "Register `FCTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FCTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Fault A Source\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SRC_A { + #[doc = "0: Fault input disabled"] + DISABLE = 0, + #[doc = "1: MCEx (x=0,1) event input"] + ENABLE = 1, + #[doc = "2: Inverted MCEx (x=0,1) event input"] + INVERT = 2, + #[doc = "3: Alternate fault (A or B) state at the end of the previous period"] + ALTFAULT = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SRC_A) -> Self { + variant as _ + } +} +#[doc = "Field `SRC` reader - Fault A Source"] +pub struct SRC_R(crate::FieldReader); +impl SRC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SRC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SRC_A { + match self.bits { + 0 => SRC_A::DISABLE, + 1 => SRC_A::ENABLE, + 2 => SRC_A::INVERT, + 3 => SRC_A::ALTFAULT, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == SRC_A::DISABLE + } + #[doc = "Checks if the value of the field is `ENABLE`"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + **self == SRC_A::ENABLE + } + #[doc = "Checks if the value of the field is `INVERT`"] + #[inline(always)] + pub fn is_invert(&self) -> bool { + **self == SRC_A::INVERT + } + #[doc = "Checks if the value of the field is `ALTFAULT`"] + #[inline(always)] + pub fn is_altfault(&self) -> bool { + **self == SRC_A::ALTFAULT + } +} +impl core::ops::Deref for SRC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SRC` writer - Fault A Source"] +pub struct SRC_W<'a> { + w: &'a mut W, +} +impl<'a> SRC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SRC_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Fault input disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(SRC_A::DISABLE) + } + #[doc = "MCEx (x=0,1) event input"] + #[inline(always)] + pub fn enable(self) -> &'a mut W { + self.variant(SRC_A::ENABLE) + } + #[doc = "Inverted MCEx (x=0,1) event input"] + #[inline(always)] + pub fn invert(self) -> &'a mut W { + self.variant(SRC_A::INVERT) + } + #[doc = "Alternate fault (A or B) state at the end of the previous period"] + #[inline(always)] + pub fn altfault(self) -> &'a mut W { + self.variant(SRC_A::ALTFAULT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u32 & 0x03); + self.w + } +} +#[doc = "Field `KEEP` reader - Fault A Keeper"] +pub struct KEEP_R(crate::FieldReader); +impl KEEP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + KEEP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for KEEP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `KEEP` writer - Fault A Keeper"] +pub struct KEEP_W<'a> { + w: &'a mut W, +} +impl<'a> KEEP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `QUAL` reader - Fault A Qualification"] +pub struct QUAL_R(crate::FieldReader); +impl QUAL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + QUAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for QUAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `QUAL` writer - Fault A Qualification"] +pub struct QUAL_W<'a> { + w: &'a mut W, +} +impl<'a> QUAL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Fault A Blanking Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum BLANK_A { + #[doc = "0: Blanking applied from start of the ramp"] + START = 0, + #[doc = "1: Blanking applied from rising edge of the output waveform"] + RISE = 1, + #[doc = "2: Blanking applied from falling edge of the output waveform"] + FALL = 2, + #[doc = "3: Blanking applied from each toggle of the output waveform"] + BOTH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: BLANK_A) -> Self { + variant as _ + } +} +#[doc = "Field `BLANK` reader - Fault A Blanking Mode"] +pub struct BLANK_R(crate::FieldReader); +impl BLANK_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BLANK_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> BLANK_A { + match self.bits { + 0 => BLANK_A::START, + 1 => BLANK_A::RISE, + 2 => BLANK_A::FALL, + 3 => BLANK_A::BOTH, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `START`"] + #[inline(always)] + pub fn is_start(&self) -> bool { + **self == BLANK_A::START + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == BLANK_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == BLANK_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == BLANK_A::BOTH + } +} +impl core::ops::Deref for BLANK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BLANK` writer - Fault A Blanking Mode"] +pub struct BLANK_W<'a> { + w: &'a mut W, +} +impl<'a> BLANK_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: BLANK_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Blanking applied from start of the ramp"] + #[inline(always)] + pub fn start(self) -> &'a mut W { + self.variant(BLANK_A::START) + } + #[doc = "Blanking applied from rising edge of the output waveform"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(BLANK_A::RISE) + } + #[doc = "Blanking applied from falling edge of the output waveform"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(BLANK_A::FALL) + } + #[doc = "Blanking applied from each toggle of the output waveform"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(BLANK_A::BOTH) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 5)) | ((value as u32 & 0x03) << 5); + self.w + } +} +#[doc = "Field `RESTART` reader - Fault A Restart"] +pub struct RESTART_R(crate::FieldReader); +impl RESTART_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESTART_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESTART_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESTART` writer - Fault A Restart"] +pub struct RESTART_W<'a> { + w: &'a mut W, +} +impl<'a> RESTART_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Fault A Halt Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum HALT_A { + #[doc = "0: Halt action disabled"] + DISABLE = 0, + #[doc = "1: Hardware halt action"] + HW = 1, + #[doc = "2: Software halt action"] + SW = 2, + #[doc = "3: Non-recoverable fault"] + NR = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: HALT_A) -> Self { + variant as _ + } +} +#[doc = "Field `HALT` reader - Fault A Halt Mode"] +pub struct HALT_R(crate::FieldReader); +impl HALT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + HALT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> HALT_A { + match self.bits { + 0 => HALT_A::DISABLE, + 1 => HALT_A::HW, + 2 => HALT_A::SW, + 3 => HALT_A::NR, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == HALT_A::DISABLE + } + #[doc = "Checks if the value of the field is `HW`"] + #[inline(always)] + pub fn is_hw(&self) -> bool { + **self == HALT_A::HW + } + #[doc = "Checks if the value of the field is `SW`"] + #[inline(always)] + pub fn is_sw(&self) -> bool { + **self == HALT_A::SW + } + #[doc = "Checks if the value of the field is `NR`"] + #[inline(always)] + pub fn is_nr(&self) -> bool { + **self == HALT_A::NR + } +} +impl core::ops::Deref for HALT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HALT` writer - Fault A Halt Mode"] +pub struct HALT_W<'a> { + w: &'a mut W, +} +impl<'a> HALT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: HALT_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Halt action disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(HALT_A::DISABLE) + } + #[doc = "Hardware halt action"] + #[inline(always)] + pub fn hw(self) -> &'a mut W { + self.variant(HALT_A::HW) + } + #[doc = "Software halt action"] + #[inline(always)] + pub fn sw(self) -> &'a mut W { + self.variant(HALT_A::SW) + } + #[doc = "Non-recoverable fault"] + #[inline(always)] + pub fn nr(self) -> &'a mut W { + self.variant(HALT_A::NR) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 8)) | ((value as u32 & 0x03) << 8); + self.w + } +} +#[doc = "Fault A Capture Channel\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CHSEL_A { + #[doc = "0: Capture value stored in channel 0"] + CC0 = 0, + #[doc = "1: Capture value stored in channel 1"] + CC1 = 1, + #[doc = "2: Capture value stored in channel 2"] + CC2 = 2, + #[doc = "3: Capture value stored in channel 3"] + CC3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CHSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `CHSEL` reader - Fault A Capture Channel"] +pub struct CHSEL_R(crate::FieldReader); +impl CHSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CHSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CHSEL_A { + match self.bits { + 0 => CHSEL_A::CC0, + 1 => CHSEL_A::CC1, + 2 => CHSEL_A::CC2, + 3 => CHSEL_A::CC3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `CC0`"] + #[inline(always)] + pub fn is_cc0(&self) -> bool { + **self == CHSEL_A::CC0 + } + #[doc = "Checks if the value of the field is `CC1`"] + #[inline(always)] + pub fn is_cc1(&self) -> bool { + **self == CHSEL_A::CC1 + } + #[doc = "Checks if the value of the field is `CC2`"] + #[inline(always)] + pub fn is_cc2(&self) -> bool { + **self == CHSEL_A::CC2 + } + #[doc = "Checks if the value of the field is `CC3`"] + #[inline(always)] + pub fn is_cc3(&self) -> bool { + **self == CHSEL_A::CC3 + } +} +impl core::ops::Deref for CHSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHSEL` writer - Fault A Capture Channel"] +pub struct CHSEL_W<'a> { + w: &'a mut W, +} +impl<'a> CHSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CHSEL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Capture value stored in channel 0"] + #[inline(always)] + pub fn cc0(self) -> &'a mut W { + self.variant(CHSEL_A::CC0) + } + #[doc = "Capture value stored in channel 1"] + #[inline(always)] + pub fn cc1(self) -> &'a mut W { + self.variant(CHSEL_A::CC1) + } + #[doc = "Capture value stored in channel 2"] + #[inline(always)] + pub fn cc2(self) -> &'a mut W { + self.variant(CHSEL_A::CC2) + } + #[doc = "Capture value stored in channel 3"] + #[inline(always)] + pub fn cc3(self) -> &'a mut W { + self.variant(CHSEL_A::CC3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 10)) | ((value as u32 & 0x03) << 10); + self.w + } +} +#[doc = "Fault A Capture Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CAPTURE_A { + #[doc = "0: No capture"] + DISABLE = 0, + #[doc = "1: Capture on fault"] + CAPT = 1, + #[doc = "2: Minimum capture"] + CAPTMIN = 2, + #[doc = "3: Maximum capture"] + CAPTMAX = 3, + #[doc = "4: Minimum local detection"] + LOCMIN = 4, + #[doc = "5: Maximum local detection"] + LOCMAX = 5, + #[doc = "6: Minimum and maximum local detection"] + DERIV0 = 6, + #[doc = "7: Capture with ramp index as MSB value"] + CAPTMARK = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CAPTURE_A) -> Self { + variant as _ + } +} +#[doc = "Field `CAPTURE` reader - Fault A Capture Action"] +pub struct CAPTURE_R(crate::FieldReader); +impl CAPTURE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CAPTURE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CAPTURE_A { + match self.bits { + 0 => CAPTURE_A::DISABLE, + 1 => CAPTURE_A::CAPT, + 2 => CAPTURE_A::CAPTMIN, + 3 => CAPTURE_A::CAPTMAX, + 4 => CAPTURE_A::LOCMIN, + 5 => CAPTURE_A::LOCMAX, + 6 => CAPTURE_A::DERIV0, + 7 => CAPTURE_A::CAPTMARK, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == CAPTURE_A::DISABLE + } + #[doc = "Checks if the value of the field is `CAPT`"] + #[inline(always)] + pub fn is_capt(&self) -> bool { + **self == CAPTURE_A::CAPT + } + #[doc = "Checks if the value of the field is `CAPTMIN`"] + #[inline(always)] + pub fn is_captmin(&self) -> bool { + **self == CAPTURE_A::CAPTMIN + } + #[doc = "Checks if the value of the field is `CAPTMAX`"] + #[inline(always)] + pub fn is_captmax(&self) -> bool { + **self == CAPTURE_A::CAPTMAX + } + #[doc = "Checks if the value of the field is `LOCMIN`"] + #[inline(always)] + pub fn is_locmin(&self) -> bool { + **self == CAPTURE_A::LOCMIN + } + #[doc = "Checks if the value of the field is `LOCMAX`"] + #[inline(always)] + pub fn is_locmax(&self) -> bool { + **self == CAPTURE_A::LOCMAX + } + #[doc = "Checks if the value of the field is `DERIV0`"] + #[inline(always)] + pub fn is_deriv0(&self) -> bool { + **self == CAPTURE_A::DERIV0 + } + #[doc = "Checks if the value of the field is `CAPTMARK`"] + #[inline(always)] + pub fn is_captmark(&self) -> bool { + **self == CAPTURE_A::CAPTMARK + } +} +impl core::ops::Deref for CAPTURE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAPTURE` writer - Fault A Capture Action"] +pub struct CAPTURE_W<'a> { + w: &'a mut W, +} +impl<'a> CAPTURE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CAPTURE_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "No capture"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(CAPTURE_A::DISABLE) + } + #[doc = "Capture on fault"] + #[inline(always)] + pub fn capt(self) -> &'a mut W { + self.variant(CAPTURE_A::CAPT) + } + #[doc = "Minimum capture"] + #[inline(always)] + pub fn captmin(self) -> &'a mut W { + self.variant(CAPTURE_A::CAPTMIN) + } + #[doc = "Maximum capture"] + #[inline(always)] + pub fn captmax(self) -> &'a mut W { + self.variant(CAPTURE_A::CAPTMAX) + } + #[doc = "Minimum local detection"] + #[inline(always)] + pub fn locmin(self) -> &'a mut W { + self.variant(CAPTURE_A::LOCMIN) + } + #[doc = "Maximum local detection"] + #[inline(always)] + pub fn locmax(self) -> &'a mut W { + self.variant(CAPTURE_A::LOCMAX) + } + #[doc = "Minimum and maximum local detection"] + #[inline(always)] + pub fn deriv0(self) -> &'a mut W { + self.variant(CAPTURE_A::DERIV0) + } + #[doc = "Capture with ramp index as MSB value"] + #[inline(always)] + pub fn captmark(self) -> &'a mut W { + self.variant(CAPTURE_A::CAPTMARK) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 12)) | ((value as u32 & 0x07) << 12); + self.w + } +} +#[doc = "Field `BLANKPRESC` reader - Fault A Blanking Prescaler"] +pub struct BLANKPRESC_R(crate::FieldReader); +impl BLANKPRESC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BLANKPRESC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BLANKPRESC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BLANKPRESC` writer - Fault A Blanking Prescaler"] +pub struct BLANKPRESC_W<'a> { + w: &'a mut W, +} +impl<'a> BLANKPRESC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `BLANKVAL` reader - Fault A Blanking Time"] +pub struct BLANKVAL_R(crate::FieldReader); +impl BLANKVAL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BLANKVAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BLANKVAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BLANKVAL` writer - Fault A Blanking Time"] +pub struct BLANKVAL_W<'a> { + w: &'a mut W, +} +impl<'a> BLANKVAL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +#[doc = "Field `FILTERVAL` reader - Fault A Filter Value"] +pub struct FILTERVAL_R(crate::FieldReader); +impl FILTERVAL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FILTERVAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTERVAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTERVAL` writer - Fault A Filter Value"] +pub struct FILTERVAL_W<'a> { + w: &'a mut W, +} +impl<'a> FILTERVAL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Fault A Source"] + #[inline(always)] + pub fn src(&self) -> SRC_R { + SRC_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bit 3 - Fault A Keeper"] + #[inline(always)] + pub fn keep(&self) -> KEEP_R { + KEEP_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Fault A Qualification"] + #[inline(always)] + pub fn qual(&self) -> QUAL_R { + QUAL_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bits 5:6 - Fault A Blanking Mode"] + #[inline(always)] + pub fn blank(&self) -> BLANK_R { + BLANK_R::new(((self.bits >> 5) & 0x03) as u8) + } + #[doc = "Bit 7 - Fault A Restart"] + #[inline(always)] + pub fn restart(&self) -> RESTART_R { + RESTART_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:9 - Fault A Halt Mode"] + #[inline(always)] + pub fn halt(&self) -> HALT_R { + HALT_R::new(((self.bits >> 8) & 0x03) as u8) + } + #[doc = "Bits 10:11 - Fault A Capture Channel"] + #[inline(always)] + pub fn chsel(&self) -> CHSEL_R { + CHSEL_R::new(((self.bits >> 10) & 0x03) as u8) + } + #[doc = "Bits 12:14 - Fault A Capture Action"] + #[inline(always)] + pub fn capture(&self) -> CAPTURE_R { + CAPTURE_R::new(((self.bits >> 12) & 0x07) as u8) + } + #[doc = "Bit 15 - Fault A Blanking Prescaler"] + #[inline(always)] + pub fn blankpresc(&self) -> BLANKPRESC_R { + BLANKPRESC_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:23 - Fault A Blanking Time"] + #[inline(always)] + pub fn blankval(&self) -> BLANKVAL_R { + BLANKVAL_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:27 - Fault A Filter Value"] + #[inline(always)] + pub fn filterval(&self) -> FILTERVAL_R { + FILTERVAL_R::new(((self.bits >> 24) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Fault A Source"] + #[inline(always)] + pub fn src(&mut self) -> SRC_W { + SRC_W { w: self } + } + #[doc = "Bit 3 - Fault A Keeper"] + #[inline(always)] + pub fn keep(&mut self) -> KEEP_W { + KEEP_W { w: self } + } + #[doc = "Bit 4 - Fault A Qualification"] + #[inline(always)] + pub fn qual(&mut self) -> QUAL_W { + QUAL_W { w: self } + } + #[doc = "Bits 5:6 - Fault A Blanking Mode"] + #[inline(always)] + pub fn blank(&mut self) -> BLANK_W { + BLANK_W { w: self } + } + #[doc = "Bit 7 - Fault A Restart"] + #[inline(always)] + pub fn restart(&mut self) -> RESTART_W { + RESTART_W { w: self } + } + #[doc = "Bits 8:9 - Fault A Halt Mode"] + #[inline(always)] + pub fn halt(&mut self) -> HALT_W { + HALT_W { w: self } + } + #[doc = "Bits 10:11 - Fault A Capture Channel"] + #[inline(always)] + pub fn chsel(&mut self) -> CHSEL_W { + CHSEL_W { w: self } + } + #[doc = "Bits 12:14 - Fault A Capture Action"] + #[inline(always)] + pub fn capture(&mut self) -> CAPTURE_W { + CAPTURE_W { w: self } + } + #[doc = "Bit 15 - Fault A Blanking Prescaler"] + #[inline(always)] + pub fn blankpresc(&mut self) -> BLANKPRESC_W { + BLANKPRESC_W { w: self } + } + #[doc = "Bits 16:23 - Fault A Blanking Time"] + #[inline(always)] + pub fn blankval(&mut self) -> BLANKVAL_W { + BLANKVAL_W { w: self } + } + #[doc = "Bits 24:27 - Fault A Filter Value"] + #[inline(always)] + pub fn filterval(&mut self) -> FILTERVAL_W { + FILTERVAL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Recoverable Fault A Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fctrla](index.html) module"] +pub struct FCTRLA_SPEC; +impl crate::RegisterSpec for FCTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [fctrla::R](R) reader structure"] +impl crate::Readable for FCTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [fctrla::W](W) writer structure"] +impl crate::Writable for FCTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets FCTRLA to value 0"] +impl crate::Resettable for FCTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/tcc0/fctrlb.rs b/pac/atsamc20j/src/tcc0/fctrlb.rs new file mode 100644 index 000000000000..4c1dfd1af93d --- /dev/null +++ b/pac/atsamc20j/src/tcc0/fctrlb.rs @@ -0,0 +1,940 @@ +#[doc = "Register `FCTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FCTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Fault B Source\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SRC_A { + #[doc = "0: Fault input disabled"] + DISABLE = 0, + #[doc = "1: MCEx (x=0,1) event input"] + ENABLE = 1, + #[doc = "2: Inverted MCEx (x=0,1) event input"] + INVERT = 2, + #[doc = "3: Alternate fault (A or B) state at the end of the previous period"] + ALTFAULT = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SRC_A) -> Self { + variant as _ + } +} +#[doc = "Field `SRC` reader - Fault B Source"] +pub struct SRC_R(crate::FieldReader); +impl SRC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SRC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SRC_A { + match self.bits { + 0 => SRC_A::DISABLE, + 1 => SRC_A::ENABLE, + 2 => SRC_A::INVERT, + 3 => SRC_A::ALTFAULT, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == SRC_A::DISABLE + } + #[doc = "Checks if the value of the field is `ENABLE`"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + **self == SRC_A::ENABLE + } + #[doc = "Checks if the value of the field is `INVERT`"] + #[inline(always)] + pub fn is_invert(&self) -> bool { + **self == SRC_A::INVERT + } + #[doc = "Checks if the value of the field is `ALTFAULT`"] + #[inline(always)] + pub fn is_altfault(&self) -> bool { + **self == SRC_A::ALTFAULT + } +} +impl core::ops::Deref for SRC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SRC` writer - Fault B Source"] +pub struct SRC_W<'a> { + w: &'a mut W, +} +impl<'a> SRC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SRC_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Fault input disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(SRC_A::DISABLE) + } + #[doc = "MCEx (x=0,1) event input"] + #[inline(always)] + pub fn enable(self) -> &'a mut W { + self.variant(SRC_A::ENABLE) + } + #[doc = "Inverted MCEx (x=0,1) event input"] + #[inline(always)] + pub fn invert(self) -> &'a mut W { + self.variant(SRC_A::INVERT) + } + #[doc = "Alternate fault (A or B) state at the end of the previous period"] + #[inline(always)] + pub fn altfault(self) -> &'a mut W { + self.variant(SRC_A::ALTFAULT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u32 & 0x03); + self.w + } +} +#[doc = "Field `KEEP` reader - Fault B Keeper"] +pub struct KEEP_R(crate::FieldReader); +impl KEEP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + KEEP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for KEEP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `KEEP` writer - Fault B Keeper"] +pub struct KEEP_W<'a> { + w: &'a mut W, +} +impl<'a> KEEP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `QUAL` reader - Fault B Qualification"] +pub struct QUAL_R(crate::FieldReader); +impl QUAL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + QUAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for QUAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `QUAL` writer - Fault B Qualification"] +pub struct QUAL_W<'a> { + w: &'a mut W, +} +impl<'a> QUAL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Fault B Blanking Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum BLANK_A { + #[doc = "0: Blanking applied from start of the ramp"] + START = 0, + #[doc = "1: Blanking applied from rising edge of the output waveform"] + RISE = 1, + #[doc = "2: Blanking applied from falling edge of the output waveform"] + FALL = 2, + #[doc = "3: Blanking applied from each toggle of the output waveform"] + BOTH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: BLANK_A) -> Self { + variant as _ + } +} +#[doc = "Field `BLANK` reader - Fault B Blanking Mode"] +pub struct BLANK_R(crate::FieldReader); +impl BLANK_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BLANK_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> BLANK_A { + match self.bits { + 0 => BLANK_A::START, + 1 => BLANK_A::RISE, + 2 => BLANK_A::FALL, + 3 => BLANK_A::BOTH, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `START`"] + #[inline(always)] + pub fn is_start(&self) -> bool { + **self == BLANK_A::START + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == BLANK_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == BLANK_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == BLANK_A::BOTH + } +} +impl core::ops::Deref for BLANK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BLANK` writer - Fault B Blanking Mode"] +pub struct BLANK_W<'a> { + w: &'a mut W, +} +impl<'a> BLANK_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: BLANK_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Blanking applied from start of the ramp"] + #[inline(always)] + pub fn start(self) -> &'a mut W { + self.variant(BLANK_A::START) + } + #[doc = "Blanking applied from rising edge of the output waveform"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(BLANK_A::RISE) + } + #[doc = "Blanking applied from falling edge of the output waveform"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(BLANK_A::FALL) + } + #[doc = "Blanking applied from each toggle of the output waveform"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(BLANK_A::BOTH) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 5)) | ((value as u32 & 0x03) << 5); + self.w + } +} +#[doc = "Field `RESTART` reader - Fault B Restart"] +pub struct RESTART_R(crate::FieldReader); +impl RESTART_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESTART_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESTART_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESTART` writer - Fault B Restart"] +pub struct RESTART_W<'a> { + w: &'a mut W, +} +impl<'a> RESTART_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Fault B Halt Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum HALT_A { + #[doc = "0: Halt action disabled"] + DISABLE = 0, + #[doc = "1: Hardware halt action"] + HW = 1, + #[doc = "2: Software halt action"] + SW = 2, + #[doc = "3: Non-recoverable fault"] + NR = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: HALT_A) -> Self { + variant as _ + } +} +#[doc = "Field `HALT` reader - Fault B Halt Mode"] +pub struct HALT_R(crate::FieldReader); +impl HALT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + HALT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> HALT_A { + match self.bits { + 0 => HALT_A::DISABLE, + 1 => HALT_A::HW, + 2 => HALT_A::SW, + 3 => HALT_A::NR, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == HALT_A::DISABLE + } + #[doc = "Checks if the value of the field is `HW`"] + #[inline(always)] + pub fn is_hw(&self) -> bool { + **self == HALT_A::HW + } + #[doc = "Checks if the value of the field is `SW`"] + #[inline(always)] + pub fn is_sw(&self) -> bool { + **self == HALT_A::SW + } + #[doc = "Checks if the value of the field is `NR`"] + #[inline(always)] + pub fn is_nr(&self) -> bool { + **self == HALT_A::NR + } +} +impl core::ops::Deref for HALT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HALT` writer - Fault B Halt Mode"] +pub struct HALT_W<'a> { + w: &'a mut W, +} +impl<'a> HALT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: HALT_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Halt action disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(HALT_A::DISABLE) + } + #[doc = "Hardware halt action"] + #[inline(always)] + pub fn hw(self) -> &'a mut W { + self.variant(HALT_A::HW) + } + #[doc = "Software halt action"] + #[inline(always)] + pub fn sw(self) -> &'a mut W { + self.variant(HALT_A::SW) + } + #[doc = "Non-recoverable fault"] + #[inline(always)] + pub fn nr(self) -> &'a mut W { + self.variant(HALT_A::NR) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 8)) | ((value as u32 & 0x03) << 8); + self.w + } +} +#[doc = "Fault B Capture Channel\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CHSEL_A { + #[doc = "0: Capture value stored in channel 0"] + CC0 = 0, + #[doc = "1: Capture value stored in channel 1"] + CC1 = 1, + #[doc = "2: Capture value stored in channel 2"] + CC2 = 2, + #[doc = "3: Capture value stored in channel 3"] + CC3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CHSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `CHSEL` reader - Fault B Capture Channel"] +pub struct CHSEL_R(crate::FieldReader); +impl CHSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CHSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CHSEL_A { + match self.bits { + 0 => CHSEL_A::CC0, + 1 => CHSEL_A::CC1, + 2 => CHSEL_A::CC2, + 3 => CHSEL_A::CC3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `CC0`"] + #[inline(always)] + pub fn is_cc0(&self) -> bool { + **self == CHSEL_A::CC0 + } + #[doc = "Checks if the value of the field is `CC1`"] + #[inline(always)] + pub fn is_cc1(&self) -> bool { + **self == CHSEL_A::CC1 + } + #[doc = "Checks if the value of the field is `CC2`"] + #[inline(always)] + pub fn is_cc2(&self) -> bool { + **self == CHSEL_A::CC2 + } + #[doc = "Checks if the value of the field is `CC3`"] + #[inline(always)] + pub fn is_cc3(&self) -> bool { + **self == CHSEL_A::CC3 + } +} +impl core::ops::Deref for CHSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHSEL` writer - Fault B Capture Channel"] +pub struct CHSEL_W<'a> { + w: &'a mut W, +} +impl<'a> CHSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CHSEL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Capture value stored in channel 0"] + #[inline(always)] + pub fn cc0(self) -> &'a mut W { + self.variant(CHSEL_A::CC0) + } + #[doc = "Capture value stored in channel 1"] + #[inline(always)] + pub fn cc1(self) -> &'a mut W { + self.variant(CHSEL_A::CC1) + } + #[doc = "Capture value stored in channel 2"] + #[inline(always)] + pub fn cc2(self) -> &'a mut W { + self.variant(CHSEL_A::CC2) + } + #[doc = "Capture value stored in channel 3"] + #[inline(always)] + pub fn cc3(self) -> &'a mut W { + self.variant(CHSEL_A::CC3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 10)) | ((value as u32 & 0x03) << 10); + self.w + } +} +#[doc = "Fault B Capture Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CAPTURE_A { + #[doc = "0: No capture"] + DISABLE = 0, + #[doc = "1: Capture on fault"] + CAPT = 1, + #[doc = "2: Minimum capture"] + CAPTMIN = 2, + #[doc = "3: Maximum capture"] + CAPTMAX = 3, + #[doc = "4: Minimum local detection"] + LOCMIN = 4, + #[doc = "5: Maximum local detection"] + LOCMAX = 5, + #[doc = "6: Minimum and maximum local detection"] + DERIV0 = 6, + #[doc = "7: Capture with ramp index as MSB value"] + CAPTMARK = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CAPTURE_A) -> Self { + variant as _ + } +} +#[doc = "Field `CAPTURE` reader - Fault B Capture Action"] +pub struct CAPTURE_R(crate::FieldReader); +impl CAPTURE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CAPTURE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CAPTURE_A { + match self.bits { + 0 => CAPTURE_A::DISABLE, + 1 => CAPTURE_A::CAPT, + 2 => CAPTURE_A::CAPTMIN, + 3 => CAPTURE_A::CAPTMAX, + 4 => CAPTURE_A::LOCMIN, + 5 => CAPTURE_A::LOCMAX, + 6 => CAPTURE_A::DERIV0, + 7 => CAPTURE_A::CAPTMARK, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == CAPTURE_A::DISABLE + } + #[doc = "Checks if the value of the field is `CAPT`"] + #[inline(always)] + pub fn is_capt(&self) -> bool { + **self == CAPTURE_A::CAPT + } + #[doc = "Checks if the value of the field is `CAPTMIN`"] + #[inline(always)] + pub fn is_captmin(&self) -> bool { + **self == CAPTURE_A::CAPTMIN + } + #[doc = "Checks if the value of the field is `CAPTMAX`"] + #[inline(always)] + pub fn is_captmax(&self) -> bool { + **self == CAPTURE_A::CAPTMAX + } + #[doc = "Checks if the value of the field is `LOCMIN`"] + #[inline(always)] + pub fn is_locmin(&self) -> bool { + **self == CAPTURE_A::LOCMIN + } + #[doc = "Checks if the value of the field is `LOCMAX`"] + #[inline(always)] + pub fn is_locmax(&self) -> bool { + **self == CAPTURE_A::LOCMAX + } + #[doc = "Checks if the value of the field is `DERIV0`"] + #[inline(always)] + pub fn is_deriv0(&self) -> bool { + **self == CAPTURE_A::DERIV0 + } + #[doc = "Checks if the value of the field is `CAPTMARK`"] + #[inline(always)] + pub fn is_captmark(&self) -> bool { + **self == CAPTURE_A::CAPTMARK + } +} +impl core::ops::Deref for CAPTURE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAPTURE` writer - Fault B Capture Action"] +pub struct CAPTURE_W<'a> { + w: &'a mut W, +} +impl<'a> CAPTURE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CAPTURE_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "No capture"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(CAPTURE_A::DISABLE) + } + #[doc = "Capture on fault"] + #[inline(always)] + pub fn capt(self) -> &'a mut W { + self.variant(CAPTURE_A::CAPT) + } + #[doc = "Minimum capture"] + #[inline(always)] + pub fn captmin(self) -> &'a mut W { + self.variant(CAPTURE_A::CAPTMIN) + } + #[doc = "Maximum capture"] + #[inline(always)] + pub fn captmax(self) -> &'a mut W { + self.variant(CAPTURE_A::CAPTMAX) + } + #[doc = "Minimum local detection"] + #[inline(always)] + pub fn locmin(self) -> &'a mut W { + self.variant(CAPTURE_A::LOCMIN) + } + #[doc = "Maximum local detection"] + #[inline(always)] + pub fn locmax(self) -> &'a mut W { + self.variant(CAPTURE_A::LOCMAX) + } + #[doc = "Minimum and maximum local detection"] + #[inline(always)] + pub fn deriv0(self) -> &'a mut W { + self.variant(CAPTURE_A::DERIV0) + } + #[doc = "Capture with ramp index as MSB value"] + #[inline(always)] + pub fn captmark(self) -> &'a mut W { + self.variant(CAPTURE_A::CAPTMARK) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 12)) | ((value as u32 & 0x07) << 12); + self.w + } +} +#[doc = "Field `BLANKPRESC` reader - Fault B Blanking Prescaler"] +pub struct BLANKPRESC_R(crate::FieldReader); +impl BLANKPRESC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BLANKPRESC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BLANKPRESC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BLANKPRESC` writer - Fault B Blanking Prescaler"] +pub struct BLANKPRESC_W<'a> { + w: &'a mut W, +} +impl<'a> BLANKPRESC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `BLANKVAL` reader - Fault B Blanking Time"] +pub struct BLANKVAL_R(crate::FieldReader); +impl BLANKVAL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BLANKVAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BLANKVAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BLANKVAL` writer - Fault B Blanking Time"] +pub struct BLANKVAL_W<'a> { + w: &'a mut W, +} +impl<'a> BLANKVAL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +#[doc = "Field `FILTERVAL` reader - Fault B Filter Value"] +pub struct FILTERVAL_R(crate::FieldReader); +impl FILTERVAL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FILTERVAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTERVAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTERVAL` writer - Fault B Filter Value"] +pub struct FILTERVAL_W<'a> { + w: &'a mut W, +} +impl<'a> FILTERVAL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Fault B Source"] + #[inline(always)] + pub fn src(&self) -> SRC_R { + SRC_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bit 3 - Fault B Keeper"] + #[inline(always)] + pub fn keep(&self) -> KEEP_R { + KEEP_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Fault B Qualification"] + #[inline(always)] + pub fn qual(&self) -> QUAL_R { + QUAL_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bits 5:6 - Fault B Blanking Mode"] + #[inline(always)] + pub fn blank(&self) -> BLANK_R { + BLANK_R::new(((self.bits >> 5) & 0x03) as u8) + } + #[doc = "Bit 7 - Fault B Restart"] + #[inline(always)] + pub fn restart(&self) -> RESTART_R { + RESTART_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:9 - Fault B Halt Mode"] + #[inline(always)] + pub fn halt(&self) -> HALT_R { + HALT_R::new(((self.bits >> 8) & 0x03) as u8) + } + #[doc = "Bits 10:11 - Fault B Capture Channel"] + #[inline(always)] + pub fn chsel(&self) -> CHSEL_R { + CHSEL_R::new(((self.bits >> 10) & 0x03) as u8) + } + #[doc = "Bits 12:14 - Fault B Capture Action"] + #[inline(always)] + pub fn capture(&self) -> CAPTURE_R { + CAPTURE_R::new(((self.bits >> 12) & 0x07) as u8) + } + #[doc = "Bit 15 - Fault B Blanking Prescaler"] + #[inline(always)] + pub fn blankpresc(&self) -> BLANKPRESC_R { + BLANKPRESC_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:23 - Fault B Blanking Time"] + #[inline(always)] + pub fn blankval(&self) -> BLANKVAL_R { + BLANKVAL_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:27 - Fault B Filter Value"] + #[inline(always)] + pub fn filterval(&self) -> FILTERVAL_R { + FILTERVAL_R::new(((self.bits >> 24) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Fault B Source"] + #[inline(always)] + pub fn src(&mut self) -> SRC_W { + SRC_W { w: self } + } + #[doc = "Bit 3 - Fault B Keeper"] + #[inline(always)] + pub fn keep(&mut self) -> KEEP_W { + KEEP_W { w: self } + } + #[doc = "Bit 4 - Fault B Qualification"] + #[inline(always)] + pub fn qual(&mut self) -> QUAL_W { + QUAL_W { w: self } + } + #[doc = "Bits 5:6 - Fault B Blanking Mode"] + #[inline(always)] + pub fn blank(&mut self) -> BLANK_W { + BLANK_W { w: self } + } + #[doc = "Bit 7 - Fault B Restart"] + #[inline(always)] + pub fn restart(&mut self) -> RESTART_W { + RESTART_W { w: self } + } + #[doc = "Bits 8:9 - Fault B Halt Mode"] + #[inline(always)] + pub fn halt(&mut self) -> HALT_W { + HALT_W { w: self } + } + #[doc = "Bits 10:11 - Fault B Capture Channel"] + #[inline(always)] + pub fn chsel(&mut self) -> CHSEL_W { + CHSEL_W { w: self } + } + #[doc = "Bits 12:14 - Fault B Capture Action"] + #[inline(always)] + pub fn capture(&mut self) -> CAPTURE_W { + CAPTURE_W { w: self } + } + #[doc = "Bit 15 - Fault B Blanking Prescaler"] + #[inline(always)] + pub fn blankpresc(&mut self) -> BLANKPRESC_W { + BLANKPRESC_W { w: self } + } + #[doc = "Bits 16:23 - Fault B Blanking Time"] + #[inline(always)] + pub fn blankval(&mut self) -> BLANKVAL_W { + BLANKVAL_W { w: self } + } + #[doc = "Bits 24:27 - Fault B Filter Value"] + #[inline(always)] + pub fn filterval(&mut self) -> FILTERVAL_W { + FILTERVAL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Recoverable Fault B Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fctrlb](index.html) module"] +pub struct FCTRLB_SPEC; +impl crate::RegisterSpec for FCTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [fctrlb::R](R) reader structure"] +impl crate::Readable for FCTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [fctrlb::W](W) writer structure"] +impl crate::Writable for FCTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets FCTRLB to value 0"] +impl crate::Resettable for FCTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/tcc0/intenclr.rs b/pac/atsamc20j/src/tcc0/intenclr.rs new file mode 100644 index 000000000000..a227a8405a3c --- /dev/null +++ b/pac/atsamc20j/src/tcc0/intenclr.rs @@ -0,0 +1,724 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `TRG` reader - Retrigger Interrupt Enable"] +pub struct TRG_R(crate::FieldReader); +impl TRG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRG` writer - Retrigger Interrupt Enable"] +pub struct TRG_W<'a> { + w: &'a mut W, +} +impl<'a> TRG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CNT` reader - Counter Interrupt Enable"] +pub struct CNT_R(crate::FieldReader); +impl CNT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CNT` writer - Counter Interrupt Enable"] +pub struct CNT_W<'a> { + w: &'a mut W, +} +impl<'a> CNT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `ERR` reader - Error Interrupt Enable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - Error Interrupt Enable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `UFS` reader - Non-Recoverable Update Fault Interrupt Enable"] +pub struct UFS_R(crate::FieldReader); +impl UFS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UFS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for UFS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `UFS` writer - Non-Recoverable Update Fault Interrupt Enable"] +pub struct UFS_W<'a> { + w: &'a mut W, +} +impl<'a> UFS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `DFS` reader - Non-Recoverable Debug Fault Interrupt Enable"] +pub struct DFS_R(crate::FieldReader); +impl DFS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFS` writer - Non-Recoverable Debug Fault Interrupt Enable"] +pub struct DFS_W<'a> { + w: &'a mut W, +} +impl<'a> DFS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `FAULTA` reader - Recoverable Fault A Interrupt Enable"] +pub struct FAULTA_R(crate::FieldReader); +impl FAULTA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTA` writer - Recoverable Fault A Interrupt Enable"] +pub struct FAULTA_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `FAULTB` reader - Recoverable Fault B Interrupt Enable"] +pub struct FAULTB_R(crate::FieldReader); +impl FAULTB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTB` writer - Recoverable Fault B Interrupt Enable"] +pub struct FAULTB_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `FAULT0` reader - Non-Recoverable Fault 0 Interrupt Enable"] +pub struct FAULT0_R(crate::FieldReader); +impl FAULT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT0` writer - Non-Recoverable Fault 0 Interrupt Enable"] +pub struct FAULT0_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `FAULT1` reader - Non-Recoverable Fault 1 Interrupt Enable"] +pub struct FAULT1_R(crate::FieldReader); +impl FAULT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT1` writer - Non-Recoverable Fault 1 Interrupt Enable"] +pub struct FAULT1_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `MC0` reader - Match or Capture Channel 0 Interrupt Enable"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - Match or Capture Channel 0 Interrupt Enable"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `MC1` reader - Match or Capture Channel 1 Interrupt Enable"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - Match or Capture Channel 1 Interrupt Enable"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `MC2` reader - Match or Capture Channel 2 Interrupt Enable"] +pub struct MC2_R(crate::FieldReader); +impl MC2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC2` writer - Match or Capture Channel 2 Interrupt Enable"] +pub struct MC2_W<'a> { + w: &'a mut W, +} +impl<'a> MC2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `MC3` reader - Match or Capture Channel 3 Interrupt Enable"] +pub struct MC3_R(crate::FieldReader); +impl MC3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC3` writer - Match or Capture Channel 3 Interrupt Enable"] +pub struct MC3_W<'a> { + w: &'a mut W, +} +impl<'a> MC3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +impl R { + #[doc = "Bit 0 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Retrigger Interrupt Enable"] + #[inline(always)] + pub fn trg(&self) -> TRG_R { + TRG_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Counter Interrupt Enable"] + #[inline(always)] + pub fn cnt(&self) -> CNT_R { + CNT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Error Interrupt Enable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 10 - Non-Recoverable Update Fault Interrupt Enable"] + #[inline(always)] + pub fn ufs(&self) -> UFS_R { + UFS_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Non-Recoverable Debug Fault Interrupt Enable"] + #[inline(always)] + pub fn dfs(&self) -> DFS_R { + DFS_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Recoverable Fault A Interrupt Enable"] + #[inline(always)] + pub fn faulta(&self) -> FAULTA_R { + FAULTA_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Recoverable Fault B Interrupt Enable"] + #[inline(always)] + pub fn faultb(&self) -> FAULTB_R { + FAULTB_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Non-Recoverable Fault 0 Interrupt Enable"] + #[inline(always)] + pub fn fault0(&self) -> FAULT0_R { + FAULT0_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Non-Recoverable Fault 1 Interrupt Enable"] + #[inline(always)] + pub fn fault1(&self) -> FAULT1_R { + FAULT1_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Match or Capture Channel 0 Interrupt Enable"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Match or Capture Channel 1 Interrupt Enable"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Match or Capture Channel 2 Interrupt Enable"] + #[inline(always)] + pub fn mc2(&self) -> MC2_R { + MC2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Match or Capture Channel 3 Interrupt Enable"] + #[inline(always)] + pub fn mc3(&self) -> MC3_R { + MC3_R::new(((self.bits >> 19) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - Retrigger Interrupt Enable"] + #[inline(always)] + pub fn trg(&mut self) -> TRG_W { + TRG_W { w: self } + } + #[doc = "Bit 2 - Counter Interrupt Enable"] + #[inline(always)] + pub fn cnt(&mut self) -> CNT_W { + CNT_W { w: self } + } + #[doc = "Bit 3 - Error Interrupt Enable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 10 - Non-Recoverable Update Fault Interrupt Enable"] + #[inline(always)] + pub fn ufs(&mut self) -> UFS_W { + UFS_W { w: self } + } + #[doc = "Bit 11 - Non-Recoverable Debug Fault Interrupt Enable"] + #[inline(always)] + pub fn dfs(&mut self) -> DFS_W { + DFS_W { w: self } + } + #[doc = "Bit 12 - Recoverable Fault A Interrupt Enable"] + #[inline(always)] + pub fn faulta(&mut self) -> FAULTA_W { + FAULTA_W { w: self } + } + #[doc = "Bit 13 - Recoverable Fault B Interrupt Enable"] + #[inline(always)] + pub fn faultb(&mut self) -> FAULTB_W { + FAULTB_W { w: self } + } + #[doc = "Bit 14 - Non-Recoverable Fault 0 Interrupt Enable"] + #[inline(always)] + pub fn fault0(&mut self) -> FAULT0_W { + FAULT0_W { w: self } + } + #[doc = "Bit 15 - Non-Recoverable Fault 1 Interrupt Enable"] + #[inline(always)] + pub fn fault1(&mut self) -> FAULT1_W { + FAULT1_W { w: self } + } + #[doc = "Bit 16 - Match or Capture Channel 0 Interrupt Enable"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 17 - Match or Capture Channel 1 Interrupt Enable"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Bit 18 - Match or Capture Channel 2 Interrupt Enable"] + #[inline(always)] + pub fn mc2(&mut self) -> MC2_W { + MC2_W { w: self } + } + #[doc = "Bit 19 - Match or Capture Channel 3 Interrupt Enable"] + #[inline(always)] + pub fn mc3(&mut self) -> MC3_W { + MC3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/tcc0/intenset.rs b/pac/atsamc20j/src/tcc0/intenset.rs new file mode 100644 index 000000000000..0125a220bd02 --- /dev/null +++ b/pac/atsamc20j/src/tcc0/intenset.rs @@ -0,0 +1,724 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `TRG` reader - Retrigger Interrupt Enable"] +pub struct TRG_R(crate::FieldReader); +impl TRG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRG` writer - Retrigger Interrupt Enable"] +pub struct TRG_W<'a> { + w: &'a mut W, +} +impl<'a> TRG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CNT` reader - Counter Interrupt Enable"] +pub struct CNT_R(crate::FieldReader); +impl CNT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CNT` writer - Counter Interrupt Enable"] +pub struct CNT_W<'a> { + w: &'a mut W, +} +impl<'a> CNT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `ERR` reader - Error Interrupt Enable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - Error Interrupt Enable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `UFS` reader - Non-Recoverable Update Fault Interrupt Enable"] +pub struct UFS_R(crate::FieldReader); +impl UFS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UFS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for UFS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `UFS` writer - Non-Recoverable Update Fault Interrupt Enable"] +pub struct UFS_W<'a> { + w: &'a mut W, +} +impl<'a> UFS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `DFS` reader - Non-Recoverable Debug Fault Interrupt Enable"] +pub struct DFS_R(crate::FieldReader); +impl DFS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFS` writer - Non-Recoverable Debug Fault Interrupt Enable"] +pub struct DFS_W<'a> { + w: &'a mut W, +} +impl<'a> DFS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `FAULTA` reader - Recoverable Fault A Interrupt Enable"] +pub struct FAULTA_R(crate::FieldReader); +impl FAULTA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTA` writer - Recoverable Fault A Interrupt Enable"] +pub struct FAULTA_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `FAULTB` reader - Recoverable Fault B Interrupt Enable"] +pub struct FAULTB_R(crate::FieldReader); +impl FAULTB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTB` writer - Recoverable Fault B Interrupt Enable"] +pub struct FAULTB_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `FAULT0` reader - Non-Recoverable Fault 0 Interrupt Enable"] +pub struct FAULT0_R(crate::FieldReader); +impl FAULT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT0` writer - Non-Recoverable Fault 0 Interrupt Enable"] +pub struct FAULT0_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `FAULT1` reader - Non-Recoverable Fault 1 Interrupt Enable"] +pub struct FAULT1_R(crate::FieldReader); +impl FAULT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT1` writer - Non-Recoverable Fault 1 Interrupt Enable"] +pub struct FAULT1_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `MC0` reader - Match or Capture Channel 0 Interrupt Enable"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - Match or Capture Channel 0 Interrupt Enable"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `MC1` reader - Match or Capture Channel 1 Interrupt Enable"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - Match or Capture Channel 1 Interrupt Enable"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `MC2` reader - Match or Capture Channel 2 Interrupt Enable"] +pub struct MC2_R(crate::FieldReader); +impl MC2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC2` writer - Match or Capture Channel 2 Interrupt Enable"] +pub struct MC2_W<'a> { + w: &'a mut W, +} +impl<'a> MC2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `MC3` reader - Match or Capture Channel 3 Interrupt Enable"] +pub struct MC3_R(crate::FieldReader); +impl MC3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC3` writer - Match or Capture Channel 3 Interrupt Enable"] +pub struct MC3_W<'a> { + w: &'a mut W, +} +impl<'a> MC3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +impl R { + #[doc = "Bit 0 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Retrigger Interrupt Enable"] + #[inline(always)] + pub fn trg(&self) -> TRG_R { + TRG_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Counter Interrupt Enable"] + #[inline(always)] + pub fn cnt(&self) -> CNT_R { + CNT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Error Interrupt Enable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 10 - Non-Recoverable Update Fault Interrupt Enable"] + #[inline(always)] + pub fn ufs(&self) -> UFS_R { + UFS_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Non-Recoverable Debug Fault Interrupt Enable"] + #[inline(always)] + pub fn dfs(&self) -> DFS_R { + DFS_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Recoverable Fault A Interrupt Enable"] + #[inline(always)] + pub fn faulta(&self) -> FAULTA_R { + FAULTA_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Recoverable Fault B Interrupt Enable"] + #[inline(always)] + pub fn faultb(&self) -> FAULTB_R { + FAULTB_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Non-Recoverable Fault 0 Interrupt Enable"] + #[inline(always)] + pub fn fault0(&self) -> FAULT0_R { + FAULT0_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Non-Recoverable Fault 1 Interrupt Enable"] + #[inline(always)] + pub fn fault1(&self) -> FAULT1_R { + FAULT1_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Match or Capture Channel 0 Interrupt Enable"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Match or Capture Channel 1 Interrupt Enable"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Match or Capture Channel 2 Interrupt Enable"] + #[inline(always)] + pub fn mc2(&self) -> MC2_R { + MC2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Match or Capture Channel 3 Interrupt Enable"] + #[inline(always)] + pub fn mc3(&self) -> MC3_R { + MC3_R::new(((self.bits >> 19) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - Retrigger Interrupt Enable"] + #[inline(always)] + pub fn trg(&mut self) -> TRG_W { + TRG_W { w: self } + } + #[doc = "Bit 2 - Counter Interrupt Enable"] + #[inline(always)] + pub fn cnt(&mut self) -> CNT_W { + CNT_W { w: self } + } + #[doc = "Bit 3 - Error Interrupt Enable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 10 - Non-Recoverable Update Fault Interrupt Enable"] + #[inline(always)] + pub fn ufs(&mut self) -> UFS_W { + UFS_W { w: self } + } + #[doc = "Bit 11 - Non-Recoverable Debug Fault Interrupt Enable"] + #[inline(always)] + pub fn dfs(&mut self) -> DFS_W { + DFS_W { w: self } + } + #[doc = "Bit 12 - Recoverable Fault A Interrupt Enable"] + #[inline(always)] + pub fn faulta(&mut self) -> FAULTA_W { + FAULTA_W { w: self } + } + #[doc = "Bit 13 - Recoverable Fault B Interrupt Enable"] + #[inline(always)] + pub fn faultb(&mut self) -> FAULTB_W { + FAULTB_W { w: self } + } + #[doc = "Bit 14 - Non-Recoverable Fault 0 Interrupt Enable"] + #[inline(always)] + pub fn fault0(&mut self) -> FAULT0_W { + FAULT0_W { w: self } + } + #[doc = "Bit 15 - Non-Recoverable Fault 1 Interrupt Enable"] + #[inline(always)] + pub fn fault1(&mut self) -> FAULT1_W { + FAULT1_W { w: self } + } + #[doc = "Bit 16 - Match or Capture Channel 0 Interrupt Enable"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 17 - Match or Capture Channel 1 Interrupt Enable"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Bit 18 - Match or Capture Channel 2 Interrupt Enable"] + #[inline(always)] + pub fn mc2(&mut self) -> MC2_W { + MC2_W { w: self } + } + #[doc = "Bit 19 - Match or Capture Channel 3 Interrupt Enable"] + #[inline(always)] + pub fn mc3(&mut self) -> MC3_W { + MC3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/tcc0/intflag.rs b/pac/atsamc20j/src/tcc0/intflag.rs new file mode 100644 index 000000000000..b2d5088f4087 --- /dev/null +++ b/pac/atsamc20j/src/tcc0/intflag.rs @@ -0,0 +1,724 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - Overflow"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `TRG` reader - Retrigger"] +pub struct TRG_R(crate::FieldReader); +impl TRG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRG` writer - Retrigger"] +pub struct TRG_W<'a> { + w: &'a mut W, +} +impl<'a> TRG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CNT` reader - Counter"] +pub struct CNT_R(crate::FieldReader); +impl CNT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CNT` writer - Counter"] +pub struct CNT_W<'a> { + w: &'a mut W, +} +impl<'a> CNT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `ERR` reader - Error"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - Error"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `UFS` reader - Non-Recoverable Update Fault"] +pub struct UFS_R(crate::FieldReader); +impl UFS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UFS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for UFS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `UFS` writer - Non-Recoverable Update Fault"] +pub struct UFS_W<'a> { + w: &'a mut W, +} +impl<'a> UFS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `DFS` reader - Non-Recoverable Debug Fault"] +pub struct DFS_R(crate::FieldReader); +impl DFS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFS` writer - Non-Recoverable Debug Fault"] +pub struct DFS_W<'a> { + w: &'a mut W, +} +impl<'a> DFS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `FAULTA` reader - Recoverable Fault A"] +pub struct FAULTA_R(crate::FieldReader); +impl FAULTA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTA` writer - Recoverable Fault A"] +pub struct FAULTA_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `FAULTB` reader - Recoverable Fault B"] +pub struct FAULTB_R(crate::FieldReader); +impl FAULTB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTB` writer - Recoverable Fault B"] +pub struct FAULTB_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `FAULT0` reader - Non-Recoverable Fault 0"] +pub struct FAULT0_R(crate::FieldReader); +impl FAULT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT0` writer - Non-Recoverable Fault 0"] +pub struct FAULT0_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `FAULT1` reader - Non-Recoverable Fault 1"] +pub struct FAULT1_R(crate::FieldReader); +impl FAULT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT1` writer - Non-Recoverable Fault 1"] +pub struct FAULT1_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `MC0` reader - Match or Capture 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - Match or Capture 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `MC1` reader - Match or Capture 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - Match or Capture 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `MC2` reader - Match or Capture 2"] +pub struct MC2_R(crate::FieldReader); +impl MC2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC2` writer - Match or Capture 2"] +pub struct MC2_W<'a> { + w: &'a mut W, +} +impl<'a> MC2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `MC3` reader - Match or Capture 3"] +pub struct MC3_R(crate::FieldReader); +impl MC3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC3` writer - Match or Capture 3"] +pub struct MC3_W<'a> { + w: &'a mut W, +} +impl<'a> MC3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +impl R { + #[doc = "Bit 0 - Overflow"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Retrigger"] + #[inline(always)] + pub fn trg(&self) -> TRG_R { + TRG_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Counter"] + #[inline(always)] + pub fn cnt(&self) -> CNT_R { + CNT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Error"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 10 - Non-Recoverable Update Fault"] + #[inline(always)] + pub fn ufs(&self) -> UFS_R { + UFS_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Non-Recoverable Debug Fault"] + #[inline(always)] + pub fn dfs(&self) -> DFS_R { + DFS_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Recoverable Fault A"] + #[inline(always)] + pub fn faulta(&self) -> FAULTA_R { + FAULTA_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Recoverable Fault B"] + #[inline(always)] + pub fn faultb(&self) -> FAULTB_R { + FAULTB_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Non-Recoverable Fault 0"] + #[inline(always)] + pub fn fault0(&self) -> FAULT0_R { + FAULT0_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Non-Recoverable Fault 1"] + #[inline(always)] + pub fn fault1(&self) -> FAULT1_R { + FAULT1_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Match or Capture 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Match or Capture 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Match or Capture 2"] + #[inline(always)] + pub fn mc2(&self) -> MC2_R { + MC2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Match or Capture 3"] + #[inline(always)] + pub fn mc3(&self) -> MC3_R { + MC3_R::new(((self.bits >> 19) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Overflow"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - Retrigger"] + #[inline(always)] + pub fn trg(&mut self) -> TRG_W { + TRG_W { w: self } + } + #[doc = "Bit 2 - Counter"] + #[inline(always)] + pub fn cnt(&mut self) -> CNT_W { + CNT_W { w: self } + } + #[doc = "Bit 3 - Error"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 10 - Non-Recoverable Update Fault"] + #[inline(always)] + pub fn ufs(&mut self) -> UFS_W { + UFS_W { w: self } + } + #[doc = "Bit 11 - Non-Recoverable Debug Fault"] + #[inline(always)] + pub fn dfs(&mut self) -> DFS_W { + DFS_W { w: self } + } + #[doc = "Bit 12 - Recoverable Fault A"] + #[inline(always)] + pub fn faulta(&mut self) -> FAULTA_W { + FAULTA_W { w: self } + } + #[doc = "Bit 13 - Recoverable Fault B"] + #[inline(always)] + pub fn faultb(&mut self) -> FAULTB_W { + FAULTB_W { w: self } + } + #[doc = "Bit 14 - Non-Recoverable Fault 0"] + #[inline(always)] + pub fn fault0(&mut self) -> FAULT0_W { + FAULT0_W { w: self } + } + #[doc = "Bit 15 - Non-Recoverable Fault 1"] + #[inline(always)] + pub fn fault1(&mut self) -> FAULT1_W { + FAULT1_W { w: self } + } + #[doc = "Bit 16 - Match or Capture 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 17 - Match or Capture 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Bit 18 - Match or Capture 2"] + #[inline(always)] + pub fn mc2(&mut self) -> MC2_W { + MC2_W { w: self } + } + #[doc = "Bit 19 - Match or Capture 3"] + #[inline(always)] + pub fn mc3(&mut self) -> MC3_W { + MC3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/tcc0/patt.rs b/pac/atsamc20j/src/tcc0/patt.rs new file mode 100644 index 000000000000..ea458642b182 --- /dev/null +++ b/pac/atsamc20j/src/tcc0/patt.rs @@ -0,0 +1,818 @@ +#[doc = "Register `PATT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PATT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PGE0` reader - Pattern Generator 0 Output Enable"] +pub struct PGE0_R(crate::FieldReader); +impl PGE0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGE0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGE0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGE0` writer - Pattern Generator 0 Output Enable"] +pub struct PGE0_W<'a> { + w: &'a mut W, +} +impl<'a> PGE0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PGE1` reader - Pattern Generator 1 Output Enable"] +pub struct PGE1_R(crate::FieldReader); +impl PGE1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGE1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGE1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGE1` writer - Pattern Generator 1 Output Enable"] +pub struct PGE1_W<'a> { + w: &'a mut W, +} +impl<'a> PGE1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PGE2` reader - Pattern Generator 2 Output Enable"] +pub struct PGE2_R(crate::FieldReader); +impl PGE2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGE2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGE2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGE2` writer - Pattern Generator 2 Output Enable"] +pub struct PGE2_W<'a> { + w: &'a mut W, +} +impl<'a> PGE2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PGE3` reader - Pattern Generator 3 Output Enable"] +pub struct PGE3_R(crate::FieldReader); +impl PGE3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGE3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGE3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGE3` writer - Pattern Generator 3 Output Enable"] +pub struct PGE3_W<'a> { + w: &'a mut W, +} +impl<'a> PGE3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PGE4` reader - Pattern Generator 4 Output Enable"] +pub struct PGE4_R(crate::FieldReader); +impl PGE4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGE4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGE4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGE4` writer - Pattern Generator 4 Output Enable"] +pub struct PGE4_W<'a> { + w: &'a mut W, +} +impl<'a> PGE4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PGE5` reader - Pattern Generator 5 Output Enable"] +pub struct PGE5_R(crate::FieldReader); +impl PGE5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGE5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGE5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGE5` writer - Pattern Generator 5 Output Enable"] +pub struct PGE5_W<'a> { + w: &'a mut W, +} +impl<'a> PGE5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PGE6` reader - Pattern Generator 6 Output Enable"] +pub struct PGE6_R(crate::FieldReader); +impl PGE6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGE6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGE6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGE6` writer - Pattern Generator 6 Output Enable"] +pub struct PGE6_W<'a> { + w: &'a mut W, +} +impl<'a> PGE6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PGE7` reader - Pattern Generator 7 Output Enable"] +pub struct PGE7_R(crate::FieldReader); +impl PGE7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGE7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGE7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGE7` writer - Pattern Generator 7 Output Enable"] +pub struct PGE7_W<'a> { + w: &'a mut W, +} +impl<'a> PGE7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `PGV0` reader - Pattern Generator 0 Output Value"] +pub struct PGV0_R(crate::FieldReader); +impl PGV0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGV0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGV0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGV0` writer - Pattern Generator 0 Output Value"] +pub struct PGV0_W<'a> { + w: &'a mut W, +} +impl<'a> PGV0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `PGV1` reader - Pattern Generator 1 Output Value"] +pub struct PGV1_R(crate::FieldReader); +impl PGV1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGV1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGV1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGV1` writer - Pattern Generator 1 Output Value"] +pub struct PGV1_W<'a> { + w: &'a mut W, +} +impl<'a> PGV1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `PGV2` reader - Pattern Generator 2 Output Value"] +pub struct PGV2_R(crate::FieldReader); +impl PGV2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGV2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGV2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGV2` writer - Pattern Generator 2 Output Value"] +pub struct PGV2_W<'a> { + w: &'a mut W, +} +impl<'a> PGV2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u16 & 0x01) << 10); + self.w + } +} +#[doc = "Field `PGV3` reader - Pattern Generator 3 Output Value"] +pub struct PGV3_R(crate::FieldReader); +impl PGV3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGV3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGV3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGV3` writer - Pattern Generator 3 Output Value"] +pub struct PGV3_W<'a> { + w: &'a mut W, +} +impl<'a> PGV3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u16 & 0x01) << 11); + self.w + } +} +#[doc = "Field `PGV4` reader - Pattern Generator 4 Output Value"] +pub struct PGV4_R(crate::FieldReader); +impl PGV4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGV4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGV4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGV4` writer - Pattern Generator 4 Output Value"] +pub struct PGV4_W<'a> { + w: &'a mut W, +} +impl<'a> PGV4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u16 & 0x01) << 12); + self.w + } +} +#[doc = "Field `PGV5` reader - Pattern Generator 5 Output Value"] +pub struct PGV5_R(crate::FieldReader); +impl PGV5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGV5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGV5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGV5` writer - Pattern Generator 5 Output Value"] +pub struct PGV5_W<'a> { + w: &'a mut W, +} +impl<'a> PGV5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u16 & 0x01) << 13); + self.w + } +} +#[doc = "Field `PGV6` reader - Pattern Generator 6 Output Value"] +pub struct PGV6_R(crate::FieldReader); +impl PGV6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGV6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGV6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGV6` writer - Pattern Generator 6 Output Value"] +pub struct PGV6_W<'a> { + w: &'a mut W, +} +impl<'a> PGV6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u16 & 0x01) << 14); + self.w + } +} +#[doc = "Field `PGV7` reader - Pattern Generator 7 Output Value"] +pub struct PGV7_R(crate::FieldReader); +impl PGV7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGV7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGV7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGV7` writer - Pattern Generator 7 Output Value"] +pub struct PGV7_W<'a> { + w: &'a mut W, +} +impl<'a> PGV7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Pattern Generator 0 Output Enable"] + #[inline(always)] + pub fn pge0(&self) -> PGE0_R { + PGE0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Pattern Generator 1 Output Enable"] + #[inline(always)] + pub fn pge1(&self) -> PGE1_R { + PGE1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Pattern Generator 2 Output Enable"] + #[inline(always)] + pub fn pge2(&self) -> PGE2_R { + PGE2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Pattern Generator 3 Output Enable"] + #[inline(always)] + pub fn pge3(&self) -> PGE3_R { + PGE3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Pattern Generator 4 Output Enable"] + #[inline(always)] + pub fn pge4(&self) -> PGE4_R { + PGE4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Pattern Generator 5 Output Enable"] + #[inline(always)] + pub fn pge5(&self) -> PGE5_R { + PGE5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Pattern Generator 6 Output Enable"] + #[inline(always)] + pub fn pge6(&self) -> PGE6_R { + PGE6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Pattern Generator 7 Output Enable"] + #[inline(always)] + pub fn pge7(&self) -> PGE7_R { + PGE7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Pattern Generator 0 Output Value"] + #[inline(always)] + pub fn pgv0(&self) -> PGV0_R { + PGV0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Pattern Generator 1 Output Value"] + #[inline(always)] + pub fn pgv1(&self) -> PGV1_R { + PGV1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Pattern Generator 2 Output Value"] + #[inline(always)] + pub fn pgv2(&self) -> PGV2_R { + PGV2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Pattern Generator 3 Output Value"] + #[inline(always)] + pub fn pgv3(&self) -> PGV3_R { + PGV3_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Pattern Generator 4 Output Value"] + #[inline(always)] + pub fn pgv4(&self) -> PGV4_R { + PGV4_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Pattern Generator 5 Output Value"] + #[inline(always)] + pub fn pgv5(&self) -> PGV5_R { + PGV5_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Pattern Generator 6 Output Value"] + #[inline(always)] + pub fn pgv6(&self) -> PGV6_R { + PGV6_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Pattern Generator 7 Output Value"] + #[inline(always)] + pub fn pgv7(&self) -> PGV7_R { + PGV7_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pattern Generator 0 Output Enable"] + #[inline(always)] + pub fn pge0(&mut self) -> PGE0_W { + PGE0_W { w: self } + } + #[doc = "Bit 1 - Pattern Generator 1 Output Enable"] + #[inline(always)] + pub fn pge1(&mut self) -> PGE1_W { + PGE1_W { w: self } + } + #[doc = "Bit 2 - Pattern Generator 2 Output Enable"] + #[inline(always)] + pub fn pge2(&mut self) -> PGE2_W { + PGE2_W { w: self } + } + #[doc = "Bit 3 - Pattern Generator 3 Output Enable"] + #[inline(always)] + pub fn pge3(&mut self) -> PGE3_W { + PGE3_W { w: self } + } + #[doc = "Bit 4 - Pattern Generator 4 Output Enable"] + #[inline(always)] + pub fn pge4(&mut self) -> PGE4_W { + PGE4_W { w: self } + } + #[doc = "Bit 5 - Pattern Generator 5 Output Enable"] + #[inline(always)] + pub fn pge5(&mut self) -> PGE5_W { + PGE5_W { w: self } + } + #[doc = "Bit 6 - Pattern Generator 6 Output Enable"] + #[inline(always)] + pub fn pge6(&mut self) -> PGE6_W { + PGE6_W { w: self } + } + #[doc = "Bit 7 - Pattern Generator 7 Output Enable"] + #[inline(always)] + pub fn pge7(&mut self) -> PGE7_W { + PGE7_W { w: self } + } + #[doc = "Bit 8 - Pattern Generator 0 Output Value"] + #[inline(always)] + pub fn pgv0(&mut self) -> PGV0_W { + PGV0_W { w: self } + } + #[doc = "Bit 9 - Pattern Generator 1 Output Value"] + #[inline(always)] + pub fn pgv1(&mut self) -> PGV1_W { + PGV1_W { w: self } + } + #[doc = "Bit 10 - Pattern Generator 2 Output Value"] + #[inline(always)] + pub fn pgv2(&mut self) -> PGV2_W { + PGV2_W { w: self } + } + #[doc = "Bit 11 - Pattern Generator 3 Output Value"] + #[inline(always)] + pub fn pgv3(&mut self) -> PGV3_W { + PGV3_W { w: self } + } + #[doc = "Bit 12 - Pattern Generator 4 Output Value"] + #[inline(always)] + pub fn pgv4(&mut self) -> PGV4_W { + PGV4_W { w: self } + } + #[doc = "Bit 13 - Pattern Generator 5 Output Value"] + #[inline(always)] + pub fn pgv5(&mut self) -> PGV5_W { + PGV5_W { w: self } + } + #[doc = "Bit 14 - Pattern Generator 6 Output Value"] + #[inline(always)] + pub fn pgv6(&mut self) -> PGV6_W { + PGV6_W { w: self } + } + #[doc = "Bit 15 - Pattern Generator 7 Output Value"] + #[inline(always)] + pub fn pgv7(&mut self) -> PGV7_W { + PGV7_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Pattern\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [patt](index.html) module"] +pub struct PATT_SPEC; +impl crate::RegisterSpec for PATT_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [patt::R](R) reader structure"] +impl crate::Readable for PATT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [patt::W](W) writer structure"] +impl crate::Writable for PATT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PATT to value 0"] +impl crate::Resettable for PATT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/tcc0/pattbuf.rs b/pac/atsamc20j/src/tcc0/pattbuf.rs new file mode 100644 index 000000000000..c9375e27645c --- /dev/null +++ b/pac/atsamc20j/src/tcc0/pattbuf.rs @@ -0,0 +1,818 @@ +#[doc = "Register `PATTBUF` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PATTBUF` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PGEB0` reader - Pattern Generator 0 Output Enable Buffer"] +pub struct PGEB0_R(crate::FieldReader); +impl PGEB0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGEB0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGEB0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGEB0` writer - Pattern Generator 0 Output Enable Buffer"] +pub struct PGEB0_W<'a> { + w: &'a mut W, +} +impl<'a> PGEB0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PGEB1` reader - Pattern Generator 1 Output Enable Buffer"] +pub struct PGEB1_R(crate::FieldReader); +impl PGEB1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGEB1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGEB1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGEB1` writer - Pattern Generator 1 Output Enable Buffer"] +pub struct PGEB1_W<'a> { + w: &'a mut W, +} +impl<'a> PGEB1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PGEB2` reader - Pattern Generator 2 Output Enable Buffer"] +pub struct PGEB2_R(crate::FieldReader); +impl PGEB2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGEB2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGEB2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGEB2` writer - Pattern Generator 2 Output Enable Buffer"] +pub struct PGEB2_W<'a> { + w: &'a mut W, +} +impl<'a> PGEB2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PGEB3` reader - Pattern Generator 3 Output Enable Buffer"] +pub struct PGEB3_R(crate::FieldReader); +impl PGEB3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGEB3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGEB3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGEB3` writer - Pattern Generator 3 Output Enable Buffer"] +pub struct PGEB3_W<'a> { + w: &'a mut W, +} +impl<'a> PGEB3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PGEB4` reader - Pattern Generator 4 Output Enable Buffer"] +pub struct PGEB4_R(crate::FieldReader); +impl PGEB4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGEB4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGEB4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGEB4` writer - Pattern Generator 4 Output Enable Buffer"] +pub struct PGEB4_W<'a> { + w: &'a mut W, +} +impl<'a> PGEB4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PGEB5` reader - Pattern Generator 5 Output Enable Buffer"] +pub struct PGEB5_R(crate::FieldReader); +impl PGEB5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGEB5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGEB5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGEB5` writer - Pattern Generator 5 Output Enable Buffer"] +pub struct PGEB5_W<'a> { + w: &'a mut W, +} +impl<'a> PGEB5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PGEB6` reader - Pattern Generator 6 Output Enable Buffer"] +pub struct PGEB6_R(crate::FieldReader); +impl PGEB6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGEB6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGEB6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGEB6` writer - Pattern Generator 6 Output Enable Buffer"] +pub struct PGEB6_W<'a> { + w: &'a mut W, +} +impl<'a> PGEB6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PGEB7` reader - Pattern Generator 7 Output Enable Buffer"] +pub struct PGEB7_R(crate::FieldReader); +impl PGEB7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGEB7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGEB7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGEB7` writer - Pattern Generator 7 Output Enable Buffer"] +pub struct PGEB7_W<'a> { + w: &'a mut W, +} +impl<'a> PGEB7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `PGVB0` reader - Pattern Generator 0 Output Enable"] +pub struct PGVB0_R(crate::FieldReader); +impl PGVB0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGVB0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGVB0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGVB0` writer - Pattern Generator 0 Output Enable"] +pub struct PGVB0_W<'a> { + w: &'a mut W, +} +impl<'a> PGVB0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `PGVB1` reader - Pattern Generator 1 Output Enable"] +pub struct PGVB1_R(crate::FieldReader); +impl PGVB1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGVB1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGVB1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGVB1` writer - Pattern Generator 1 Output Enable"] +pub struct PGVB1_W<'a> { + w: &'a mut W, +} +impl<'a> PGVB1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `PGVB2` reader - Pattern Generator 2 Output Enable"] +pub struct PGVB2_R(crate::FieldReader); +impl PGVB2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGVB2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGVB2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGVB2` writer - Pattern Generator 2 Output Enable"] +pub struct PGVB2_W<'a> { + w: &'a mut W, +} +impl<'a> PGVB2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u16 & 0x01) << 10); + self.w + } +} +#[doc = "Field `PGVB3` reader - Pattern Generator 3 Output Enable"] +pub struct PGVB3_R(crate::FieldReader); +impl PGVB3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGVB3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGVB3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGVB3` writer - Pattern Generator 3 Output Enable"] +pub struct PGVB3_W<'a> { + w: &'a mut W, +} +impl<'a> PGVB3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u16 & 0x01) << 11); + self.w + } +} +#[doc = "Field `PGVB4` reader - Pattern Generator 4 Output Enable"] +pub struct PGVB4_R(crate::FieldReader); +impl PGVB4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGVB4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGVB4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGVB4` writer - Pattern Generator 4 Output Enable"] +pub struct PGVB4_W<'a> { + w: &'a mut W, +} +impl<'a> PGVB4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u16 & 0x01) << 12); + self.w + } +} +#[doc = "Field `PGVB5` reader - Pattern Generator 5 Output Enable"] +pub struct PGVB5_R(crate::FieldReader); +impl PGVB5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGVB5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGVB5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGVB5` writer - Pattern Generator 5 Output Enable"] +pub struct PGVB5_W<'a> { + w: &'a mut W, +} +impl<'a> PGVB5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u16 & 0x01) << 13); + self.w + } +} +#[doc = "Field `PGVB6` reader - Pattern Generator 6 Output Enable"] +pub struct PGVB6_R(crate::FieldReader); +impl PGVB6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGVB6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGVB6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGVB6` writer - Pattern Generator 6 Output Enable"] +pub struct PGVB6_W<'a> { + w: &'a mut W, +} +impl<'a> PGVB6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u16 & 0x01) << 14); + self.w + } +} +#[doc = "Field `PGVB7` reader - Pattern Generator 7 Output Enable"] +pub struct PGVB7_R(crate::FieldReader); +impl PGVB7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGVB7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGVB7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGVB7` writer - Pattern Generator 7 Output Enable"] +pub struct PGVB7_W<'a> { + w: &'a mut W, +} +impl<'a> PGVB7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Pattern Generator 0 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb0(&self) -> PGEB0_R { + PGEB0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Pattern Generator 1 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb1(&self) -> PGEB1_R { + PGEB1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Pattern Generator 2 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb2(&self) -> PGEB2_R { + PGEB2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Pattern Generator 3 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb3(&self) -> PGEB3_R { + PGEB3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Pattern Generator 4 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb4(&self) -> PGEB4_R { + PGEB4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Pattern Generator 5 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb5(&self) -> PGEB5_R { + PGEB5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Pattern Generator 6 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb6(&self) -> PGEB6_R { + PGEB6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Pattern Generator 7 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb7(&self) -> PGEB7_R { + PGEB7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Pattern Generator 0 Output Enable"] + #[inline(always)] + pub fn pgvb0(&self) -> PGVB0_R { + PGVB0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Pattern Generator 1 Output Enable"] + #[inline(always)] + pub fn pgvb1(&self) -> PGVB1_R { + PGVB1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Pattern Generator 2 Output Enable"] + #[inline(always)] + pub fn pgvb2(&self) -> PGVB2_R { + PGVB2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Pattern Generator 3 Output Enable"] + #[inline(always)] + pub fn pgvb3(&self) -> PGVB3_R { + PGVB3_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Pattern Generator 4 Output Enable"] + #[inline(always)] + pub fn pgvb4(&self) -> PGVB4_R { + PGVB4_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Pattern Generator 5 Output Enable"] + #[inline(always)] + pub fn pgvb5(&self) -> PGVB5_R { + PGVB5_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Pattern Generator 6 Output Enable"] + #[inline(always)] + pub fn pgvb6(&self) -> PGVB6_R { + PGVB6_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Pattern Generator 7 Output Enable"] + #[inline(always)] + pub fn pgvb7(&self) -> PGVB7_R { + PGVB7_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pattern Generator 0 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb0(&mut self) -> PGEB0_W { + PGEB0_W { w: self } + } + #[doc = "Bit 1 - Pattern Generator 1 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb1(&mut self) -> PGEB1_W { + PGEB1_W { w: self } + } + #[doc = "Bit 2 - Pattern Generator 2 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb2(&mut self) -> PGEB2_W { + PGEB2_W { w: self } + } + #[doc = "Bit 3 - Pattern Generator 3 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb3(&mut self) -> PGEB3_W { + PGEB3_W { w: self } + } + #[doc = "Bit 4 - Pattern Generator 4 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb4(&mut self) -> PGEB4_W { + PGEB4_W { w: self } + } + #[doc = "Bit 5 - Pattern Generator 5 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb5(&mut self) -> PGEB5_W { + PGEB5_W { w: self } + } + #[doc = "Bit 6 - Pattern Generator 6 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb6(&mut self) -> PGEB6_W { + PGEB6_W { w: self } + } + #[doc = "Bit 7 - Pattern Generator 7 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb7(&mut self) -> PGEB7_W { + PGEB7_W { w: self } + } + #[doc = "Bit 8 - Pattern Generator 0 Output Enable"] + #[inline(always)] + pub fn pgvb0(&mut self) -> PGVB0_W { + PGVB0_W { w: self } + } + #[doc = "Bit 9 - Pattern Generator 1 Output Enable"] + #[inline(always)] + pub fn pgvb1(&mut self) -> PGVB1_W { + PGVB1_W { w: self } + } + #[doc = "Bit 10 - Pattern Generator 2 Output Enable"] + #[inline(always)] + pub fn pgvb2(&mut self) -> PGVB2_W { + PGVB2_W { w: self } + } + #[doc = "Bit 11 - Pattern Generator 3 Output Enable"] + #[inline(always)] + pub fn pgvb3(&mut self) -> PGVB3_W { + PGVB3_W { w: self } + } + #[doc = "Bit 12 - Pattern Generator 4 Output Enable"] + #[inline(always)] + pub fn pgvb4(&mut self) -> PGVB4_W { + PGVB4_W { w: self } + } + #[doc = "Bit 13 - Pattern Generator 5 Output Enable"] + #[inline(always)] + pub fn pgvb5(&mut self) -> PGVB5_W { + PGVB5_W { w: self } + } + #[doc = "Bit 14 - Pattern Generator 6 Output Enable"] + #[inline(always)] + pub fn pgvb6(&mut self) -> PGVB6_W { + PGVB6_W { w: self } + } + #[doc = "Bit 15 - Pattern Generator 7 Output Enable"] + #[inline(always)] + pub fn pgvb7(&mut self) -> PGVB7_W { + PGVB7_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Pattern Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pattbuf](index.html) module"] +pub struct PATTBUF_SPEC; +impl crate::RegisterSpec for PATTBUF_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [pattbuf::R](R) reader structure"] +impl crate::Readable for PATTBUF_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [pattbuf::W](W) writer structure"] +impl crate::Writable for PATTBUF_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PATTBUF to value 0"] +impl crate::Resettable for PATTBUF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/tcc0/per.rs b/pac/atsamc20j/src/tcc0/per.rs new file mode 100644 index 000000000000..9d8618631650 --- /dev/null +++ b/pac/atsamc20j/src/tcc0/per.rs @@ -0,0 +1,103 @@ +#[doc = "Register `PER` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PER` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER` reader - Period Value"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` writer - Period Value"] +pub struct PER_W<'a> { + w: &'a mut W, +} +impl<'a> PER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Period Value"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Period Value"] + #[inline(always)] + pub fn per(&mut self) -> PER_W { + PER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [per](index.html) module"] +pub struct PER_SPEC; +impl crate::RegisterSpec for PER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [per::R](R) reader structure"] +impl crate::Readable for PER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [per::W](W) writer structure"] +impl crate::Writable for PER_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PER to value 0xffff_ffff"] +impl crate::Resettable for PER_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pac/atsamc20j/src/tcc0/per_dith4_mode.rs b/pac/atsamc20j/src/tcc0/per_dith4_mode.rs new file mode 100644 index 000000000000..2f600552db84 --- /dev/null +++ b/pac/atsamc20j/src/tcc0/per_dith4_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PER_DITH4_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PER_DITH4_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHER` reader - Dithering Cycle Number"] +pub struct DITHER_R(crate::FieldReader); +impl DITHER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHER` writer - Dithering Cycle Number"] +pub struct DITHER_W<'a> { + w: &'a mut W, +} +impl<'a> DITHER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Field `PER` reader - Period Value"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` writer - Period Value"] +pub struct PER_W<'a> { + w: &'a mut W, +} +impl<'a> PER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x000f_ffff << 4)) | ((value as u32 & 0x000f_ffff) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&self) -> DITHER_R { + DITHER_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:23 - Period Value"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(((self.bits >> 4) & 0x000f_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:3 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&mut self) -> DITHER_W { + DITHER_W { w: self } + } + #[doc = "Bits 4:23 - Period Value"] + #[inline(always)] + pub fn per(&mut self) -> PER_W { + PER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [per_dith4_mode](index.html) module"] +pub struct PER_DITH4_MODE_SPEC; +impl crate::RegisterSpec for PER_DITH4_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [per_dith4_mode::R](R) reader structure"] +impl crate::Readable for PER_DITH4_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [per_dith4_mode::W](W) writer structure"] +impl crate::Writable for PER_DITH4_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PER_DITH4_MODE to value 0xffff_ffff"] +impl crate::Resettable for PER_DITH4_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pac/atsamc20j/src/tcc0/per_dith5_mode.rs b/pac/atsamc20j/src/tcc0/per_dith5_mode.rs new file mode 100644 index 000000000000..1906582e4c95 --- /dev/null +++ b/pac/atsamc20j/src/tcc0/per_dith5_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PER_DITH5_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PER_DITH5_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHER` reader - Dithering Cycle Number"] +pub struct DITHER_R(crate::FieldReader); +impl DITHER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHER` writer - Dithering Cycle Number"] +pub struct DITHER_W<'a> { + w: &'a mut W, +} +impl<'a> DITHER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f); + self.w + } +} +#[doc = "Field `PER` reader - Period Value"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` writer - Period Value"] +pub struct PER_W<'a> { + w: &'a mut W, +} +impl<'a> PER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0007_ffff << 5)) | ((value as u32 & 0x0007_ffff) << 5); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&self) -> DITHER_R { + DITHER_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:23 - Period Value"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(((self.bits >> 5) & 0x0007_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:4 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&mut self) -> DITHER_W { + DITHER_W { w: self } + } + #[doc = "Bits 5:23 - Period Value"] + #[inline(always)] + pub fn per(&mut self) -> PER_W { + PER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [per_dith5_mode](index.html) module"] +pub struct PER_DITH5_MODE_SPEC; +impl crate::RegisterSpec for PER_DITH5_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [per_dith5_mode::R](R) reader structure"] +impl crate::Readable for PER_DITH5_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [per_dith5_mode::W](W) writer structure"] +impl crate::Writable for PER_DITH5_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PER_DITH5_MODE to value 0xffff_ffff"] +impl crate::Resettable for PER_DITH5_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pac/atsamc20j/src/tcc0/per_dith6_mode.rs b/pac/atsamc20j/src/tcc0/per_dith6_mode.rs new file mode 100644 index 000000000000..67880e220a9c --- /dev/null +++ b/pac/atsamc20j/src/tcc0/per_dith6_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PER_DITH6_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PER_DITH6_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHER` reader - Dithering Cycle Number"] +pub struct DITHER_R(crate::FieldReader); +impl DITHER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHER` writer - Dithering Cycle Number"] +pub struct DITHER_W<'a> { + w: &'a mut W, +} +impl<'a> DITHER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +#[doc = "Field `PER` reader - Period Value"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` writer - Period Value"] +pub struct PER_W<'a> { + w: &'a mut W, +} +impl<'a> PER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0003_ffff << 6)) | ((value as u32 & 0x0003_ffff) << 6); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&self) -> DITHER_R { + DITHER_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:23 - Period Value"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(((self.bits >> 6) & 0x0003_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:5 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&mut self) -> DITHER_W { + DITHER_W { w: self } + } + #[doc = "Bits 6:23 - Period Value"] + #[inline(always)] + pub fn per(&mut self) -> PER_W { + PER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [per_dith6_mode](index.html) module"] +pub struct PER_DITH6_MODE_SPEC; +impl crate::RegisterSpec for PER_DITH6_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [per_dith6_mode::R](R) reader structure"] +impl crate::Readable for PER_DITH6_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [per_dith6_mode::W](W) writer structure"] +impl crate::Writable for PER_DITH6_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PER_DITH6_MODE to value 0xffff_ffff"] +impl crate::Resettable for PER_DITH6_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pac/atsamc20j/src/tcc0/perbuf.rs b/pac/atsamc20j/src/tcc0/perbuf.rs new file mode 100644 index 000000000000..169f17479616 --- /dev/null +++ b/pac/atsamc20j/src/tcc0/perbuf.rs @@ -0,0 +1,103 @@ +#[doc = "Register `PERBUF` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PERBUF` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PERBUF` reader - Period Buffer Value"] +pub struct PERBUF_R(crate::FieldReader); +impl PERBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + PERBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERBUF` writer - Period Buffer Value"] +pub struct PERBUF_W<'a> { + w: &'a mut W, +} +impl<'a> PERBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Period Buffer Value"] + #[inline(always)] + pub fn perbuf(&self) -> PERBUF_R { + PERBUF_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Period Buffer Value"] + #[inline(always)] + pub fn perbuf(&mut self) -> PERBUF_W { + PERBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [perbuf](index.html) module"] +pub struct PERBUF_SPEC; +impl crate::RegisterSpec for PERBUF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [perbuf::R](R) reader structure"] +impl crate::Readable for PERBUF_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [perbuf::W](W) writer structure"] +impl crate::Writable for PERBUF_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PERBUF to value 0xffff_ffff"] +impl crate::Resettable for PERBUF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pac/atsamc20j/src/tcc0/perbuf_dith4_mode.rs b/pac/atsamc20j/src/tcc0/perbuf_dith4_mode.rs new file mode 100644 index 000000000000..ccf96ecef185 --- /dev/null +++ b/pac/atsamc20j/src/tcc0/perbuf_dith4_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PERBUF_DITH4_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PERBUF_DITH4_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHERBUF` reader - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_R(crate::FieldReader); +impl DITHERBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHERBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHERBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHERBUF` writer - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_W<'a> { + w: &'a mut W, +} +impl<'a> DITHERBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Field `PERBUF` reader - Period Buffer Value"] +pub struct PERBUF_R(crate::FieldReader); +impl PERBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + PERBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERBUF` writer - Period Buffer Value"] +pub struct PERBUF_W<'a> { + w: &'a mut W, +} +impl<'a> PERBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x000f_ffff << 4)) | ((value as u32 & 0x000f_ffff) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&self) -> DITHERBUF_R { + DITHERBUF_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:23 - Period Buffer Value"] + #[inline(always)] + pub fn perbuf(&self) -> PERBUF_R { + PERBUF_R::new(((self.bits >> 4) & 0x000f_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:3 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&mut self) -> DITHERBUF_W { + DITHERBUF_W { w: self } + } + #[doc = "Bits 4:23 - Period Buffer Value"] + #[inline(always)] + pub fn perbuf(&mut self) -> PERBUF_W { + PERBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [perbuf_dith4_mode](index.html) module"] +pub struct PERBUF_DITH4_MODE_SPEC; +impl crate::RegisterSpec for PERBUF_DITH4_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [perbuf_dith4_mode::R](R) reader structure"] +impl crate::Readable for PERBUF_DITH4_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [perbuf_dith4_mode::W](W) writer structure"] +impl crate::Writable for PERBUF_DITH4_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PERBUF_DITH4_MODE to value 0xffff_ffff"] +impl crate::Resettable for PERBUF_DITH4_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pac/atsamc20j/src/tcc0/perbuf_dith5_mode.rs b/pac/atsamc20j/src/tcc0/perbuf_dith5_mode.rs new file mode 100644 index 000000000000..d55f6d52c5ba --- /dev/null +++ b/pac/atsamc20j/src/tcc0/perbuf_dith5_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PERBUF_DITH5_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PERBUF_DITH5_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHERBUF` reader - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_R(crate::FieldReader); +impl DITHERBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHERBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHERBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHERBUF` writer - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_W<'a> { + w: &'a mut W, +} +impl<'a> DITHERBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f); + self.w + } +} +#[doc = "Field `PERBUF` reader - Period Buffer Value"] +pub struct PERBUF_R(crate::FieldReader); +impl PERBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + PERBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERBUF` writer - Period Buffer Value"] +pub struct PERBUF_W<'a> { + w: &'a mut W, +} +impl<'a> PERBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0007_ffff << 5)) | ((value as u32 & 0x0007_ffff) << 5); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&self) -> DITHERBUF_R { + DITHERBUF_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:23 - Period Buffer Value"] + #[inline(always)] + pub fn perbuf(&self) -> PERBUF_R { + PERBUF_R::new(((self.bits >> 5) & 0x0007_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:4 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&mut self) -> DITHERBUF_W { + DITHERBUF_W { w: self } + } + #[doc = "Bits 5:23 - Period Buffer Value"] + #[inline(always)] + pub fn perbuf(&mut self) -> PERBUF_W { + PERBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [perbuf_dith5_mode](index.html) module"] +pub struct PERBUF_DITH5_MODE_SPEC; +impl crate::RegisterSpec for PERBUF_DITH5_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [perbuf_dith5_mode::R](R) reader structure"] +impl crate::Readable for PERBUF_DITH5_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [perbuf_dith5_mode::W](W) writer structure"] +impl crate::Writable for PERBUF_DITH5_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PERBUF_DITH5_MODE to value 0xffff_ffff"] +impl crate::Resettable for PERBUF_DITH5_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pac/atsamc20j/src/tcc0/perbuf_dith6_mode.rs b/pac/atsamc20j/src/tcc0/perbuf_dith6_mode.rs new file mode 100644 index 000000000000..983c849f9073 --- /dev/null +++ b/pac/atsamc20j/src/tcc0/perbuf_dith6_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PERBUF_DITH6_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PERBUF_DITH6_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHERBUF` reader - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_R(crate::FieldReader); +impl DITHERBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHERBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHERBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHERBUF` writer - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_W<'a> { + w: &'a mut W, +} +impl<'a> DITHERBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +#[doc = "Field `PERBUF` reader - Period Buffer Value"] +pub struct PERBUF_R(crate::FieldReader); +impl PERBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + PERBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERBUF` writer - Period Buffer Value"] +pub struct PERBUF_W<'a> { + w: &'a mut W, +} +impl<'a> PERBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0003_ffff << 6)) | ((value as u32 & 0x0003_ffff) << 6); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&self) -> DITHERBUF_R { + DITHERBUF_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:23 - Period Buffer Value"] + #[inline(always)] + pub fn perbuf(&self) -> PERBUF_R { + PERBUF_R::new(((self.bits >> 6) & 0x0003_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:5 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&mut self) -> DITHERBUF_W { + DITHERBUF_W { w: self } + } + #[doc = "Bits 6:23 - Period Buffer Value"] + #[inline(always)] + pub fn perbuf(&mut self) -> PERBUF_W { + PERBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [perbuf_dith6_mode](index.html) module"] +pub struct PERBUF_DITH6_MODE_SPEC; +impl crate::RegisterSpec for PERBUF_DITH6_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [perbuf_dith6_mode::R](R) reader structure"] +impl crate::Readable for PERBUF_DITH6_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [perbuf_dith6_mode::W](W) writer structure"] +impl crate::Writable for PERBUF_DITH6_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PERBUF_DITH6_MODE to value 0xffff_ffff"] +impl crate::Resettable for PERBUF_DITH6_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pac/atsamc20j/src/tcc0/status.rs b/pac/atsamc20j/src/tcc0/status.rs new file mode 100644 index 000000000000..eecd909e6093 --- /dev/null +++ b/pac/atsamc20j/src/tcc0/status.rs @@ -0,0 +1,1147 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `STOP` reader - Stop"] +pub struct STOP_R(crate::FieldReader); +impl STOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STOP` writer - Stop"] +pub struct STOP_W<'a> { + w: &'a mut W, +} +impl<'a> STOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `IDX` reader - Ramp"] +pub struct IDX_R(crate::FieldReader); +impl IDX_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IDX_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IDX_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IDX` writer - Ramp"] +pub struct IDX_W<'a> { + w: &'a mut W, +} +impl<'a> IDX_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `UFS` reader - Non-recoverable Update Fault State"] +pub struct UFS_R(crate::FieldReader); +impl UFS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UFS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for UFS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `UFS` writer - Non-recoverable Update Fault State"] +pub struct UFS_W<'a> { + w: &'a mut W, +} +impl<'a> UFS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `DFS` reader - Non-Recoverable Debug Fault State"] +pub struct DFS_R(crate::FieldReader); +impl DFS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFS` writer - Non-Recoverable Debug Fault State"] +pub struct DFS_W<'a> { + w: &'a mut W, +} +impl<'a> DFS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `SLAVE` reader - Slave"] +pub struct SLAVE_R(crate::FieldReader); +impl SLAVE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLAVE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SLAVE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLAVE` writer - Slave"] +pub struct SLAVE_W<'a> { + w: &'a mut W, +} +impl<'a> SLAVE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PATTBUFV` reader - Pattern Buffer Valid"] +pub struct PATTBUFV_R(crate::FieldReader); +impl PATTBUFV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PATTBUFV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PATTBUFV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PATTBUFV` writer - Pattern Buffer Valid"] +pub struct PATTBUFV_W<'a> { + w: &'a mut W, +} +impl<'a> PATTBUFV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PERBUFV` reader - Period Buffer Valid"] +pub struct PERBUFV_R(crate::FieldReader); +impl PERBUFV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PERBUFV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERBUFV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERBUFV` writer - Period Buffer Valid"] +pub struct PERBUFV_W<'a> { + w: &'a mut W, +} +impl<'a> PERBUFV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `FAULTAIN` reader - Recoverable Fault A Input"] +pub struct FAULTAIN_R(crate::FieldReader); +impl FAULTAIN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTAIN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTAIN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTAIN` writer - Recoverable Fault A Input"] +pub struct FAULTAIN_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTAIN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `FAULTBIN` reader - Recoverable Fault B Input"] +pub struct FAULTBIN_R(crate::FieldReader); +impl FAULTBIN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTBIN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTBIN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTBIN` writer - Recoverable Fault B Input"] +pub struct FAULTBIN_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTBIN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `FAULT0IN` reader - Non-Recoverable Fault0 Input"] +pub struct FAULT0IN_R(crate::FieldReader); +impl FAULT0IN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT0IN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT0IN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT0IN` writer - Non-Recoverable Fault0 Input"] +pub struct FAULT0IN_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT0IN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `FAULT1IN` reader - Non-Recoverable Fault1 Input"] +pub struct FAULT1IN_R(crate::FieldReader); +impl FAULT1IN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT1IN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT1IN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT1IN` writer - Non-Recoverable Fault1 Input"] +pub struct FAULT1IN_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT1IN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `FAULTA` reader - Recoverable Fault A State"] +pub struct FAULTA_R(crate::FieldReader); +impl FAULTA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTA` writer - Recoverable Fault A State"] +pub struct FAULTA_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `FAULTB` reader - Recoverable Fault B State"] +pub struct FAULTB_R(crate::FieldReader); +impl FAULTB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTB` writer - Recoverable Fault B State"] +pub struct FAULTB_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `FAULT0` reader - Non-Recoverable Fault 0 State"] +pub struct FAULT0_R(crate::FieldReader); +impl FAULT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT0` writer - Non-Recoverable Fault 0 State"] +pub struct FAULT0_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `FAULT1` reader - Non-Recoverable Fault 1 State"] +pub struct FAULT1_R(crate::FieldReader); +impl FAULT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT1` writer - Non-Recoverable Fault 1 State"] +pub struct FAULT1_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `CCBUFV0` reader - Compare Channel 0 Buffer Valid"] +pub struct CCBUFV0_R(crate::FieldReader); +impl CCBUFV0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBUFV0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUFV0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUFV0` writer - Compare Channel 0 Buffer Valid"] +pub struct CCBUFV0_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUFV0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `CCBUFV1` reader - Compare Channel 1 Buffer Valid"] +pub struct CCBUFV1_R(crate::FieldReader); +impl CCBUFV1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBUFV1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUFV1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUFV1` writer - Compare Channel 1 Buffer Valid"] +pub struct CCBUFV1_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUFV1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `CCBUFV2` reader - Compare Channel 2 Buffer Valid"] +pub struct CCBUFV2_R(crate::FieldReader); +impl CCBUFV2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBUFV2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUFV2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUFV2` writer - Compare Channel 2 Buffer Valid"] +pub struct CCBUFV2_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUFV2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `CCBUFV3` reader - Compare Channel 3 Buffer Valid"] +pub struct CCBUFV3_R(crate::FieldReader); +impl CCBUFV3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBUFV3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUFV3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUFV3` writer - Compare Channel 3 Buffer Valid"] +pub struct CCBUFV3_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUFV3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `CMP0` reader - Compare Channel 0 Value"] +pub struct CMP0_R(crate::FieldReader); +impl CMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP0` writer - Compare Channel 0 Value"] +pub struct CMP0_W<'a> { + w: &'a mut W, +} +impl<'a> CMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `CMP1` reader - Compare Channel 1 Value"] +pub struct CMP1_R(crate::FieldReader); +impl CMP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP1` writer - Compare Channel 1 Value"] +pub struct CMP1_W<'a> { + w: &'a mut W, +} +impl<'a> CMP1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `CMP2` reader - Compare Channel 2 Value"] +pub struct CMP2_R(crate::FieldReader); +impl CMP2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP2` writer - Compare Channel 2 Value"] +pub struct CMP2_W<'a> { + w: &'a mut W, +} +impl<'a> CMP2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `CMP3` reader - Compare Channel 3 Value"] +pub struct CMP3_R(crate::FieldReader); +impl CMP3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP3` writer - Compare Channel 3 Value"] +pub struct CMP3_W<'a> { + w: &'a mut W, +} +impl<'a> CMP3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +impl R { + #[doc = "Bit 0 - Stop"] + #[inline(always)] + pub fn stop(&self) -> STOP_R { + STOP_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Ramp"] + #[inline(always)] + pub fn idx(&self) -> IDX_R { + IDX_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Non-recoverable Update Fault State"] + #[inline(always)] + pub fn ufs(&self) -> UFS_R { + UFS_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Non-Recoverable Debug Fault State"] + #[inline(always)] + pub fn dfs(&self) -> DFS_R { + DFS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Slave"] + #[inline(always)] + pub fn slave(&self) -> SLAVE_R { + SLAVE_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Pattern Buffer Valid"] + #[inline(always)] + pub fn pattbufv(&self) -> PATTBUFV_R { + PATTBUFV_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 7 - Period Buffer Valid"] + #[inline(always)] + pub fn perbufv(&self) -> PERBUFV_R { + PERBUFV_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Recoverable Fault A Input"] + #[inline(always)] + pub fn faultain(&self) -> FAULTAIN_R { + FAULTAIN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Recoverable Fault B Input"] + #[inline(always)] + pub fn faultbin(&self) -> FAULTBIN_R { + FAULTBIN_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Non-Recoverable Fault0 Input"] + #[inline(always)] + pub fn fault0in(&self) -> FAULT0IN_R { + FAULT0IN_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Non-Recoverable Fault1 Input"] + #[inline(always)] + pub fn fault1in(&self) -> FAULT1IN_R { + FAULT1IN_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Recoverable Fault A State"] + #[inline(always)] + pub fn faulta(&self) -> FAULTA_R { + FAULTA_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Recoverable Fault B State"] + #[inline(always)] + pub fn faultb(&self) -> FAULTB_R { + FAULTB_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Non-Recoverable Fault 0 State"] + #[inline(always)] + pub fn fault0(&self) -> FAULT0_R { + FAULT0_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Non-Recoverable Fault 1 State"] + #[inline(always)] + pub fn fault1(&self) -> FAULT1_R { + FAULT1_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Compare Channel 0 Buffer Valid"] + #[inline(always)] + pub fn ccbufv0(&self) -> CCBUFV0_R { + CCBUFV0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Compare Channel 1 Buffer Valid"] + #[inline(always)] + pub fn ccbufv1(&self) -> CCBUFV1_R { + CCBUFV1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Compare Channel 2 Buffer Valid"] + #[inline(always)] + pub fn ccbufv2(&self) -> CCBUFV2_R { + CCBUFV2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Compare Channel 3 Buffer Valid"] + #[inline(always)] + pub fn ccbufv3(&self) -> CCBUFV3_R { + CCBUFV3_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 24 - Compare Channel 0 Value"] + #[inline(always)] + pub fn cmp0(&self) -> CMP0_R { + CMP0_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Compare Channel 1 Value"] + #[inline(always)] + pub fn cmp1(&self) -> CMP1_R { + CMP1_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Compare Channel 2 Value"] + #[inline(always)] + pub fn cmp2(&self) -> CMP2_R { + CMP2_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Compare Channel 3 Value"] + #[inline(always)] + pub fn cmp3(&self) -> CMP3_R { + CMP3_R::new(((self.bits >> 27) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Stop"] + #[inline(always)] + pub fn stop(&mut self) -> STOP_W { + STOP_W { w: self } + } + #[doc = "Bit 1 - Ramp"] + #[inline(always)] + pub fn idx(&mut self) -> IDX_W { + IDX_W { w: self } + } + #[doc = "Bit 2 - Non-recoverable Update Fault State"] + #[inline(always)] + pub fn ufs(&mut self) -> UFS_W { + UFS_W { w: self } + } + #[doc = "Bit 3 - Non-Recoverable Debug Fault State"] + #[inline(always)] + pub fn dfs(&mut self) -> DFS_W { + DFS_W { w: self } + } + #[doc = "Bit 4 - Slave"] + #[inline(always)] + pub fn slave(&mut self) -> SLAVE_W { + SLAVE_W { w: self } + } + #[doc = "Bit 5 - Pattern Buffer Valid"] + #[inline(always)] + pub fn pattbufv(&mut self) -> PATTBUFV_W { + PATTBUFV_W { w: self } + } + #[doc = "Bit 7 - Period Buffer Valid"] + #[inline(always)] + pub fn perbufv(&mut self) -> PERBUFV_W { + PERBUFV_W { w: self } + } + #[doc = "Bit 8 - Recoverable Fault A Input"] + #[inline(always)] + pub fn faultain(&mut self) -> FAULTAIN_W { + FAULTAIN_W { w: self } + } + #[doc = "Bit 9 - Recoverable Fault B Input"] + #[inline(always)] + pub fn faultbin(&mut self) -> FAULTBIN_W { + FAULTBIN_W { w: self } + } + #[doc = "Bit 10 - Non-Recoverable Fault0 Input"] + #[inline(always)] + pub fn fault0in(&mut self) -> FAULT0IN_W { + FAULT0IN_W { w: self } + } + #[doc = "Bit 11 - Non-Recoverable Fault1 Input"] + #[inline(always)] + pub fn fault1in(&mut self) -> FAULT1IN_W { + FAULT1IN_W { w: self } + } + #[doc = "Bit 12 - Recoverable Fault A State"] + #[inline(always)] + pub fn faulta(&mut self) -> FAULTA_W { + FAULTA_W { w: self } + } + #[doc = "Bit 13 - Recoverable Fault B State"] + #[inline(always)] + pub fn faultb(&mut self) -> FAULTB_W { + FAULTB_W { w: self } + } + #[doc = "Bit 14 - Non-Recoverable Fault 0 State"] + #[inline(always)] + pub fn fault0(&mut self) -> FAULT0_W { + FAULT0_W { w: self } + } + #[doc = "Bit 15 - Non-Recoverable Fault 1 State"] + #[inline(always)] + pub fn fault1(&mut self) -> FAULT1_W { + FAULT1_W { w: self } + } + #[doc = "Bit 16 - Compare Channel 0 Buffer Valid"] + #[inline(always)] + pub fn ccbufv0(&mut self) -> CCBUFV0_W { + CCBUFV0_W { w: self } + } + #[doc = "Bit 17 - Compare Channel 1 Buffer Valid"] + #[inline(always)] + pub fn ccbufv1(&mut self) -> CCBUFV1_W { + CCBUFV1_W { w: self } + } + #[doc = "Bit 18 - Compare Channel 2 Buffer Valid"] + #[inline(always)] + pub fn ccbufv2(&mut self) -> CCBUFV2_W { + CCBUFV2_W { w: self } + } + #[doc = "Bit 19 - Compare Channel 3 Buffer Valid"] + #[inline(always)] + pub fn ccbufv3(&mut self) -> CCBUFV3_W { + CCBUFV3_W { w: self } + } + #[doc = "Bit 24 - Compare Channel 0 Value"] + #[inline(always)] + pub fn cmp0(&mut self) -> CMP0_W { + CMP0_W { w: self } + } + #[doc = "Bit 25 - Compare Channel 1 Value"] + #[inline(always)] + pub fn cmp1(&mut self) -> CMP1_W { + CMP1_W { w: self } + } + #[doc = "Bit 26 - Compare Channel 2 Value"] + #[inline(always)] + pub fn cmp2(&mut self) -> CMP2_W { + CMP2_W { w: self } + } + #[doc = "Bit 27 - Compare Channel 3 Value"] + #[inline(always)] + pub fn cmp3(&mut self) -> CMP3_W { + CMP3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0x01"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pac/atsamc20j/src/tcc0/syncbusy.rs b/pac/atsamc20j/src/tcc0/syncbusy.rs new file mode 100644 index 000000000000..db0788c3f206 --- /dev/null +++ b/pac/atsamc20j/src/tcc0/syncbusy.rs @@ -0,0 +1,273 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Swrst Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - Enable Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLB` reader - Ctrlb Busy"] +pub struct CTRLB_R(crate::FieldReader); +impl CTRLB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STATUS` reader - Status Busy"] +pub struct STATUS_R(crate::FieldReader); +impl STATUS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STATUS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STATUS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` reader - Count Busy"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PATT` reader - Pattern Busy"] +pub struct PATT_R(crate::FieldReader); +impl PATT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PATT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PATT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAVE` reader - Wave Busy"] +pub struct WAVE_R(crate::FieldReader); +impl WAVE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAVE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAVE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` reader - Period Busy"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC0` reader - Compare Channel 0 Busy"] +pub struct CC0_R(crate::FieldReader); +impl CC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC1` reader - Compare Channel 1 Busy"] +pub struct CC1_R(crate::FieldReader); +impl CC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC2` reader - Compare Channel 2 Busy"] +pub struct CC2_R(crate::FieldReader); +impl CC2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC3` reader - Compare Channel 3 Busy"] +pub struct CC3_R(crate::FieldReader); +impl CC3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Swrst Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Ctrlb Busy"] + #[inline(always)] + pub fn ctrlb(&self) -> CTRLB_R { + CTRLB_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Status Busy"] + #[inline(always)] + pub fn status(&self) -> STATUS_R { + STATUS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Count Busy"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Pattern Busy"] + #[inline(always)] + pub fn patt(&self) -> PATT_R { + PATT_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Wave Busy"] + #[inline(always)] + pub fn wave(&self) -> WAVE_R { + WAVE_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Period Busy"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Compare Channel 0 Busy"] + #[inline(always)] + pub fn cc0(&self) -> CC0_R { + CC0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Compare Channel 1 Busy"] + #[inline(always)] + pub fn cc1(&self) -> CC1_R { + CC1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Compare Channel 2 Busy"] + #[inline(always)] + pub fn cc2(&self) -> CC2_R { + CC2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Compare Channel 3 Busy"] + #[inline(always)] + pub fn cc3(&self) -> CC3_R { + CC3_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +#[doc = "Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/tcc0/wave.rs b/pac/atsamc20j/src/tcc0/wave.rs new file mode 100644 index 000000000000..8d092d429a91 --- /dev/null +++ b/pac/atsamc20j/src/tcc0/wave.rs @@ -0,0 +1,940 @@ +#[doc = "Register `WAVE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WAVE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Waveform Generation\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WAVEGEN_A { + #[doc = "0: Normal frequency"] + NFRQ = 0, + #[doc = "1: Match frequency"] + MFRQ = 1, + #[doc = "2: Normal PWM"] + NPWM = 2, + #[doc = "4: Dual-slope critical"] + DSCRITICAL = 4, + #[doc = "5: Dual-slope with interrupt/event condition when COUNT reaches ZERO"] + DSBOTTOM = 5, + #[doc = "6: Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP"] + DSBOTH = 6, + #[doc = "7: Dual-slope with interrupt/event condition when COUNT reaches TOP"] + DSTOP = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WAVEGEN_A) -> Self { + variant as _ + } +} +#[doc = "Field `WAVEGEN` reader - Waveform Generation"] +pub struct WAVEGEN_R(crate::FieldReader); +impl WAVEGEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WAVEGEN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(WAVEGEN_A::NFRQ), + 1 => Some(WAVEGEN_A::MFRQ), + 2 => Some(WAVEGEN_A::NPWM), + 4 => Some(WAVEGEN_A::DSCRITICAL), + 5 => Some(WAVEGEN_A::DSBOTTOM), + 6 => Some(WAVEGEN_A::DSBOTH), + 7 => Some(WAVEGEN_A::DSTOP), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NFRQ`"] + #[inline(always)] + pub fn is_nfrq(&self) -> bool { + **self == WAVEGEN_A::NFRQ + } + #[doc = "Checks if the value of the field is `MFRQ`"] + #[inline(always)] + pub fn is_mfrq(&self) -> bool { + **self == WAVEGEN_A::MFRQ + } + #[doc = "Checks if the value of the field is `NPWM`"] + #[inline(always)] + pub fn is_npwm(&self) -> bool { + **self == WAVEGEN_A::NPWM + } + #[doc = "Checks if the value of the field is `DSCRITICAL`"] + #[inline(always)] + pub fn is_dscritical(&self) -> bool { + **self == WAVEGEN_A::DSCRITICAL + } + #[doc = "Checks if the value of the field is `DSBOTTOM`"] + #[inline(always)] + pub fn is_dsbottom(&self) -> bool { + **self == WAVEGEN_A::DSBOTTOM + } + #[doc = "Checks if the value of the field is `DSBOTH`"] + #[inline(always)] + pub fn is_dsboth(&self) -> bool { + **self == WAVEGEN_A::DSBOTH + } + #[doc = "Checks if the value of the field is `DSTOP`"] + #[inline(always)] + pub fn is_dstop(&self) -> bool { + **self == WAVEGEN_A::DSTOP + } +} +impl core::ops::Deref for WAVEGEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAVEGEN` writer - Waveform Generation"] +pub struct WAVEGEN_W<'a> { + w: &'a mut W, +} +impl<'a> WAVEGEN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WAVEGEN_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Normal frequency"] + #[inline(always)] + pub fn nfrq(self) -> &'a mut W { + self.variant(WAVEGEN_A::NFRQ) + } + #[doc = "Match frequency"] + #[inline(always)] + pub fn mfrq(self) -> &'a mut W { + self.variant(WAVEGEN_A::MFRQ) + } + #[doc = "Normal PWM"] + #[inline(always)] + pub fn npwm(self) -> &'a mut W { + self.variant(WAVEGEN_A::NPWM) + } + #[doc = "Dual-slope critical"] + #[inline(always)] + pub fn dscritical(self) -> &'a mut W { + self.variant(WAVEGEN_A::DSCRITICAL) + } + #[doc = "Dual-slope with interrupt/event condition when COUNT reaches ZERO"] + #[inline(always)] + pub fn dsbottom(self) -> &'a mut W { + self.variant(WAVEGEN_A::DSBOTTOM) + } + #[doc = "Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP"] + #[inline(always)] + pub fn dsboth(self) -> &'a mut W { + self.variant(WAVEGEN_A::DSBOTH) + } + #[doc = "Dual-slope with interrupt/event condition when COUNT reaches TOP"] + #[inline(always)] + pub fn dstop(self) -> &'a mut W { + self.variant(WAVEGEN_A::DSTOP) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Ramp Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum RAMP_A { + #[doc = "0: RAMP1 operation"] + RAMP1 = 0, + #[doc = "1: Alternative RAMP2 operation"] + RAMP2A = 1, + #[doc = "2: RAMP2 operation"] + RAMP2 = 2, + #[doc = "3: Critical RAMP2 operation"] + RAMP2C = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RAMP_A) -> Self { + variant as _ + } +} +#[doc = "Field `RAMP` reader - Ramp Mode"] +pub struct RAMP_R(crate::FieldReader); +impl RAMP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RAMP_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RAMP_A { + match self.bits { + 0 => RAMP_A::RAMP1, + 1 => RAMP_A::RAMP2A, + 2 => RAMP_A::RAMP2, + 3 => RAMP_A::RAMP2C, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `RAMP1`"] + #[inline(always)] + pub fn is_ramp1(&self) -> bool { + **self == RAMP_A::RAMP1 + } + #[doc = "Checks if the value of the field is `RAMP2A`"] + #[inline(always)] + pub fn is_ramp2a(&self) -> bool { + **self == RAMP_A::RAMP2A + } + #[doc = "Checks if the value of the field is `RAMP2`"] + #[inline(always)] + pub fn is_ramp2(&self) -> bool { + **self == RAMP_A::RAMP2 + } + #[doc = "Checks if the value of the field is `RAMP2C`"] + #[inline(always)] + pub fn is_ramp2c(&self) -> bool { + **self == RAMP_A::RAMP2C + } +} +impl core::ops::Deref for RAMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RAMP` writer - Ramp Mode"] +pub struct RAMP_W<'a> { + w: &'a mut W, +} +impl<'a> RAMP_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RAMP_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "RAMP1 operation"] + #[inline(always)] + pub fn ramp1(self) -> &'a mut W { + self.variant(RAMP_A::RAMP1) + } + #[doc = "Alternative RAMP2 operation"] + #[inline(always)] + pub fn ramp2a(self) -> &'a mut W { + self.variant(RAMP_A::RAMP2A) + } + #[doc = "RAMP2 operation"] + #[inline(always)] + pub fn ramp2(self) -> &'a mut W { + self.variant(RAMP_A::RAMP2) + } + #[doc = "Critical RAMP2 operation"] + #[inline(always)] + pub fn ramp2c(self) -> &'a mut W { + self.variant(RAMP_A::RAMP2C) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u32 & 0x03) << 4); + self.w + } +} +#[doc = "Field `CIPEREN` reader - Circular period Enable"] +pub struct CIPEREN_R(crate::FieldReader); +impl CIPEREN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CIPEREN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CIPEREN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CIPEREN` writer - Circular period Enable"] +pub struct CIPEREN_W<'a> { + w: &'a mut W, +} +impl<'a> CIPEREN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CICCEN0` reader - Circular Channel 0 Enable"] +pub struct CICCEN0_R(crate::FieldReader); +impl CICCEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CICCEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CICCEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CICCEN0` writer - Circular Channel 0 Enable"] +pub struct CICCEN0_W<'a> { + w: &'a mut W, +} +impl<'a> CICCEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `CICCEN1` reader - Circular Channel 1 Enable"] +pub struct CICCEN1_R(crate::FieldReader); +impl CICCEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CICCEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CICCEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CICCEN1` writer - Circular Channel 1 Enable"] +pub struct CICCEN1_W<'a> { + w: &'a mut W, +} +impl<'a> CICCEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `CICCEN2` reader - Circular Channel 2 Enable"] +pub struct CICCEN2_R(crate::FieldReader); +impl CICCEN2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CICCEN2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CICCEN2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CICCEN2` writer - Circular Channel 2 Enable"] +pub struct CICCEN2_W<'a> { + w: &'a mut W, +} +impl<'a> CICCEN2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `CICCEN3` reader - Circular Channel 3 Enable"] +pub struct CICCEN3_R(crate::FieldReader); +impl CICCEN3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CICCEN3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CICCEN3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CICCEN3` writer - Circular Channel 3 Enable"] +pub struct CICCEN3_W<'a> { + w: &'a mut W, +} +impl<'a> CICCEN3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `POL0` reader - Channel 0 Polarity"] +pub struct POL0_R(crate::FieldReader); +impl POL0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + POL0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for POL0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `POL0` writer - Channel 0 Polarity"] +pub struct POL0_W<'a> { + w: &'a mut W, +} +impl<'a> POL0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `POL1` reader - Channel 1 Polarity"] +pub struct POL1_R(crate::FieldReader); +impl POL1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + POL1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for POL1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `POL1` writer - Channel 1 Polarity"] +pub struct POL1_W<'a> { + w: &'a mut W, +} +impl<'a> POL1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `POL2` reader - Channel 2 Polarity"] +pub struct POL2_R(crate::FieldReader); +impl POL2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + POL2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for POL2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `POL2` writer - Channel 2 Polarity"] +pub struct POL2_W<'a> { + w: &'a mut W, +} +impl<'a> POL2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `POL3` reader - Channel 3 Polarity"] +pub struct POL3_R(crate::FieldReader); +impl POL3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + POL3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for POL3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `POL3` writer - Channel 3 Polarity"] +pub struct POL3_W<'a> { + w: &'a mut W, +} +impl<'a> POL3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `SWAP0` reader - Swap DTI Output Pair 0"] +pub struct SWAP0_R(crate::FieldReader); +impl SWAP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWAP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWAP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWAP0` writer - Swap DTI Output Pair 0"] +pub struct SWAP0_W<'a> { + w: &'a mut W, +} +impl<'a> SWAP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `SWAP1` reader - Swap DTI Output Pair 1"] +pub struct SWAP1_R(crate::FieldReader); +impl SWAP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWAP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWAP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWAP1` writer - Swap DTI Output Pair 1"] +pub struct SWAP1_W<'a> { + w: &'a mut W, +} +impl<'a> SWAP1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `SWAP2` reader - Swap DTI Output Pair 2"] +pub struct SWAP2_R(crate::FieldReader); +impl SWAP2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWAP2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWAP2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWAP2` writer - Swap DTI Output Pair 2"] +pub struct SWAP2_W<'a> { + w: &'a mut W, +} +impl<'a> SWAP2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `SWAP3` reader - Swap DTI Output Pair 3"] +pub struct SWAP3_R(crate::FieldReader); +impl SWAP3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWAP3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWAP3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWAP3` writer - Swap DTI Output Pair 3"] +pub struct SWAP3_W<'a> { + w: &'a mut W, +} +impl<'a> SWAP3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Waveform Generation"] + #[inline(always)] + pub fn wavegen(&self) -> WAVEGEN_R { + WAVEGEN_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bits 4:5 - Ramp Mode"] + #[inline(always)] + pub fn ramp(&self) -> RAMP_R { + RAMP_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bit 7 - Circular period Enable"] + #[inline(always)] + pub fn ciperen(&self) -> CIPEREN_R { + CIPEREN_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Circular Channel 0 Enable"] + #[inline(always)] + pub fn ciccen0(&self) -> CICCEN0_R { + CICCEN0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Circular Channel 1 Enable"] + #[inline(always)] + pub fn ciccen1(&self) -> CICCEN1_R { + CICCEN1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Circular Channel 2 Enable"] + #[inline(always)] + pub fn ciccen2(&self) -> CICCEN2_R { + CICCEN2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Circular Channel 3 Enable"] + #[inline(always)] + pub fn ciccen3(&self) -> CICCEN3_R { + CICCEN3_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 16 - Channel 0 Polarity"] + #[inline(always)] + pub fn pol0(&self) -> POL0_R { + POL0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Channel 1 Polarity"] + #[inline(always)] + pub fn pol1(&self) -> POL1_R { + POL1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Channel 2 Polarity"] + #[inline(always)] + pub fn pol2(&self) -> POL2_R { + POL2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Channel 3 Polarity"] + #[inline(always)] + pub fn pol3(&self) -> POL3_R { + POL3_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 24 - Swap DTI Output Pair 0"] + #[inline(always)] + pub fn swap0(&self) -> SWAP0_R { + SWAP0_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Swap DTI Output Pair 1"] + #[inline(always)] + pub fn swap1(&self) -> SWAP1_R { + SWAP1_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Swap DTI Output Pair 2"] + #[inline(always)] + pub fn swap2(&self) -> SWAP2_R { + SWAP2_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Swap DTI Output Pair 3"] + #[inline(always)] + pub fn swap3(&self) -> SWAP3_R { + SWAP3_R::new(((self.bits >> 27) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Waveform Generation"] + #[inline(always)] + pub fn wavegen(&mut self) -> WAVEGEN_W { + WAVEGEN_W { w: self } + } + #[doc = "Bits 4:5 - Ramp Mode"] + #[inline(always)] + pub fn ramp(&mut self) -> RAMP_W { + RAMP_W { w: self } + } + #[doc = "Bit 7 - Circular period Enable"] + #[inline(always)] + pub fn ciperen(&mut self) -> CIPEREN_W { + CIPEREN_W { w: self } + } + #[doc = "Bit 8 - Circular Channel 0 Enable"] + #[inline(always)] + pub fn ciccen0(&mut self) -> CICCEN0_W { + CICCEN0_W { w: self } + } + #[doc = "Bit 9 - Circular Channel 1 Enable"] + #[inline(always)] + pub fn ciccen1(&mut self) -> CICCEN1_W { + CICCEN1_W { w: self } + } + #[doc = "Bit 10 - Circular Channel 2 Enable"] + #[inline(always)] + pub fn ciccen2(&mut self) -> CICCEN2_W { + CICCEN2_W { w: self } + } + #[doc = "Bit 11 - Circular Channel 3 Enable"] + #[inline(always)] + pub fn ciccen3(&mut self) -> CICCEN3_W { + CICCEN3_W { w: self } + } + #[doc = "Bit 16 - Channel 0 Polarity"] + #[inline(always)] + pub fn pol0(&mut self) -> POL0_W { + POL0_W { w: self } + } + #[doc = "Bit 17 - Channel 1 Polarity"] + #[inline(always)] + pub fn pol1(&mut self) -> POL1_W { + POL1_W { w: self } + } + #[doc = "Bit 18 - Channel 2 Polarity"] + #[inline(always)] + pub fn pol2(&mut self) -> POL2_W { + POL2_W { w: self } + } + #[doc = "Bit 19 - Channel 3 Polarity"] + #[inline(always)] + pub fn pol3(&mut self) -> POL3_W { + POL3_W { w: self } + } + #[doc = "Bit 24 - Swap DTI Output Pair 0"] + #[inline(always)] + pub fn swap0(&mut self) -> SWAP0_W { + SWAP0_W { w: self } + } + #[doc = "Bit 25 - Swap DTI Output Pair 1"] + #[inline(always)] + pub fn swap1(&mut self) -> SWAP1_W { + SWAP1_W { w: self } + } + #[doc = "Bit 26 - Swap DTI Output Pair 2"] + #[inline(always)] + pub fn swap2(&mut self) -> SWAP2_W { + SWAP2_W { w: self } + } + #[doc = "Bit 27 - Swap DTI Output Pair 3"] + #[inline(always)] + pub fn swap3(&mut self) -> SWAP3_W { + SWAP3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Waveform Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wave](index.html) module"] +pub struct WAVE_SPEC; +impl crate::RegisterSpec for WAVE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [wave::R](R) reader structure"] +impl crate::Readable for WAVE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wave::W](W) writer structure"] +impl crate::Writable for WAVE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WAVE to value 0"] +impl crate::Resettable for WAVE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/tcc0/wexctrl.rs b/pac/atsamc20j/src/tcc0/wexctrl.rs new file mode 100644 index 000000000000..8eb0d29cbee5 --- /dev/null +++ b/pac/atsamc20j/src/tcc0/wexctrl.rs @@ -0,0 +1,365 @@ +#[doc = "Register `WEXCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WEXCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OTMX` reader - Output Matrix"] +pub struct OTMX_R(crate::FieldReader); +impl OTMX_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + OTMX_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OTMX_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OTMX` writer - Output Matrix"] +pub struct OTMX_W<'a> { + w: &'a mut W, +} +impl<'a> OTMX_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u32 & 0x03); + self.w + } +} +#[doc = "Field `DTIEN0` reader - Dead-time Insertion Generator 0 Enable"] +pub struct DTIEN0_R(crate::FieldReader); +impl DTIEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DTIEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DTIEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DTIEN0` writer - Dead-time Insertion Generator 0 Enable"] +pub struct DTIEN0_W<'a> { + w: &'a mut W, +} +impl<'a> DTIEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `DTIEN1` reader - Dead-time Insertion Generator 1 Enable"] +pub struct DTIEN1_R(crate::FieldReader); +impl DTIEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DTIEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DTIEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DTIEN1` writer - Dead-time Insertion Generator 1 Enable"] +pub struct DTIEN1_W<'a> { + w: &'a mut W, +} +impl<'a> DTIEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `DTIEN2` reader - Dead-time Insertion Generator 2 Enable"] +pub struct DTIEN2_R(crate::FieldReader); +impl DTIEN2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DTIEN2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DTIEN2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DTIEN2` writer - Dead-time Insertion Generator 2 Enable"] +pub struct DTIEN2_W<'a> { + w: &'a mut W, +} +impl<'a> DTIEN2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `DTIEN3` reader - Dead-time Insertion Generator 3 Enable"] +pub struct DTIEN3_R(crate::FieldReader); +impl DTIEN3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DTIEN3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DTIEN3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DTIEN3` writer - Dead-time Insertion Generator 3 Enable"] +pub struct DTIEN3_W<'a> { + w: &'a mut W, +} +impl<'a> DTIEN3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `DTLS` reader - Dead-time Low Side Outputs Value"] +pub struct DTLS_R(crate::FieldReader); +impl DTLS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DTLS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DTLS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DTLS` writer - Dead-time Low Side Outputs Value"] +pub struct DTLS_W<'a> { + w: &'a mut W, +} +impl<'a> DTLS_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +#[doc = "Field `DTHS` reader - Dead-time High Side Outputs Value"] +pub struct DTHS_R(crate::FieldReader); +impl DTHS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DTHS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DTHS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DTHS` writer - Dead-time High Side Outputs Value"] +pub struct DTHS_W<'a> { + w: &'a mut W, +} +impl<'a> DTHS_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 24)) | ((value as u32 & 0xff) << 24); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Output Matrix"] + #[inline(always)] + pub fn otmx(&self) -> OTMX_R { + OTMX_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bit 8 - Dead-time Insertion Generator 0 Enable"] + #[inline(always)] + pub fn dtien0(&self) -> DTIEN0_R { + DTIEN0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Dead-time Insertion Generator 1 Enable"] + #[inline(always)] + pub fn dtien1(&self) -> DTIEN1_R { + DTIEN1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Dead-time Insertion Generator 2 Enable"] + #[inline(always)] + pub fn dtien2(&self) -> DTIEN2_R { + DTIEN2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Dead-time Insertion Generator 3 Enable"] + #[inline(always)] + pub fn dtien3(&self) -> DTIEN3_R { + DTIEN3_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bits 16:23 - Dead-time Low Side Outputs Value"] + #[inline(always)] + pub fn dtls(&self) -> DTLS_R { + DTLS_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Dead-time High Side Outputs Value"] + #[inline(always)] + pub fn dths(&self) -> DTHS_R { + DTHS_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Output Matrix"] + #[inline(always)] + pub fn otmx(&mut self) -> OTMX_W { + OTMX_W { w: self } + } + #[doc = "Bit 8 - Dead-time Insertion Generator 0 Enable"] + #[inline(always)] + pub fn dtien0(&mut self) -> DTIEN0_W { + DTIEN0_W { w: self } + } + #[doc = "Bit 9 - Dead-time Insertion Generator 1 Enable"] + #[inline(always)] + pub fn dtien1(&mut self) -> DTIEN1_W { + DTIEN1_W { w: self } + } + #[doc = "Bit 10 - Dead-time Insertion Generator 2 Enable"] + #[inline(always)] + pub fn dtien2(&mut self) -> DTIEN2_W { + DTIEN2_W { w: self } + } + #[doc = "Bit 11 - Dead-time Insertion Generator 3 Enable"] + #[inline(always)] + pub fn dtien3(&mut self) -> DTIEN3_W { + DTIEN3_W { w: self } + } + #[doc = "Bits 16:23 - Dead-time Low Side Outputs Value"] + #[inline(always)] + pub fn dtls(&mut self) -> DTLS_W { + DTLS_W { w: self } + } + #[doc = "Bits 24:31 - Dead-time High Side Outputs Value"] + #[inline(always)] + pub fn dths(&mut self) -> DTHS_W { + DTHS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Waveform Extension Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wexctrl](index.html) module"] +pub struct WEXCTRL_SPEC; +impl crate::RegisterSpec for WEXCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [wexctrl::R](R) reader structure"] +impl crate::Readable for WEXCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wexctrl::W](W) writer structure"] +impl crate::Writable for WEXCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WEXCTRL to value 0"] +impl crate::Resettable for WEXCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/wdt.rs b/pac/atsamc20j/src/wdt.rs new file mode 100644 index 000000000000..22b5c2bb706f --- /dev/null +++ b/pac/atsamc20j/src/wdt.rs @@ -0,0 +1,54 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrla: crate::Reg, + #[doc = "0x01 - Configuration"] + pub config: crate::Reg, + #[doc = "0x02 - Early Warning Interrupt Control"] + pub ewctrl: crate::Reg, + _reserved3: [u8; 0x01], + #[doc = "0x04 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x05 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x06 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x08 - Synchronization Busy"] + pub syncbusy: crate::Reg, + #[doc = "0x0c - Clear"] + pub clear: crate::Reg, +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control"] +pub mod ctrla; +#[doc = "CONFIG register accessor: an alias for `Reg`"] +pub type CONFIG = crate::Reg; +#[doc = "Configuration"] +pub mod config; +#[doc = "EWCTRL register accessor: an alias for `Reg`"] +pub type EWCTRL = crate::Reg; +#[doc = "Early Warning Interrupt Control"] +pub mod ewctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Busy"] +pub mod syncbusy; +#[doc = "CLEAR register accessor: an alias for `Reg`"] +pub type CLEAR = crate::Reg; +#[doc = "Clear"] +pub mod clear; diff --git a/pac/atsamc20j/src/wdt/clear.rs b/pac/atsamc20j/src/wdt/clear.rs new file mode 100644 index 000000000000..61ee21f3246a --- /dev/null +++ b/pac/atsamc20j/src/wdt/clear.rs @@ -0,0 +1,85 @@ +#[doc = "Register `CLEAR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Watchdog Clear\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CLEAR_AW { + #[doc = "165: Clear Key"] + KEY = 165, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CLEAR_AW) -> Self { + variant as _ + } +} +#[doc = "Field `CLEAR` writer - Watchdog Clear"] +pub struct CLEAR_W<'a> { + w: &'a mut W, +} +impl<'a> CLEAR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CLEAR_AW) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Clear Key"] + #[inline(always)] + pub fn key(self) -> &'a mut W { + self.variant(CLEAR_AW::KEY) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl W { + #[doc = "Bits 0:7 - Watchdog Clear"] + #[inline(always)] + pub fn clear(&mut self) -> CLEAR_W { + CLEAR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Clear\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clear](index.html) module"] +pub struct CLEAR_SPEC; +impl crate::RegisterSpec for CLEAR_SPEC { + type Ux = u8; +} +#[doc = "`write(|w| ..)` method takes [clear::W](W) writer structure"] +impl crate::Writable for CLEAR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CLEAR to value 0"] +impl crate::Resettable for CLEAR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/wdt/config.rs b/pac/atsamc20j/src/wdt/config.rs new file mode 100644 index 000000000000..c90f062b01f0 --- /dev/null +++ b/pac/atsamc20j/src/wdt/config.rs @@ -0,0 +1,498 @@ +#[doc = "Register `CONFIG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CONFIG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Time-Out Period\n\nValue on reset: 11"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PER_A { + #[doc = "0: 8 clock cycles"] + CYC8 = 0, + #[doc = "1: 16 clock cycles"] + CYC16 = 1, + #[doc = "2: 32 clock cycles"] + CYC32 = 2, + #[doc = "3: 64 clock cycles"] + CYC64 = 3, + #[doc = "4: 128 clock cycles"] + CYC128 = 4, + #[doc = "5: 256 clock cycles"] + CYC256 = 5, + #[doc = "6: 512 clock cycles"] + CYC512 = 6, + #[doc = "7: 1024 clock cycles"] + CYC1024 = 7, + #[doc = "8: 2048 clock cycles"] + CYC2048 = 8, + #[doc = "9: 4096 clock cycles"] + CYC4096 = 9, + #[doc = "10: 8192 clock cycles"] + CYC8192 = 10, + #[doc = "11: 16384 clock cycles"] + CYC16384 = 11, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PER` reader - Time-Out Period"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PER_A::CYC8), + 1 => Some(PER_A::CYC16), + 2 => Some(PER_A::CYC32), + 3 => Some(PER_A::CYC64), + 4 => Some(PER_A::CYC128), + 5 => Some(PER_A::CYC256), + 6 => Some(PER_A::CYC512), + 7 => Some(PER_A::CYC1024), + 8 => Some(PER_A::CYC2048), + 9 => Some(PER_A::CYC4096), + 10 => Some(PER_A::CYC8192), + 11 => Some(PER_A::CYC16384), + _ => None, + } + } + #[doc = "Checks if the value of the field is `CYC8`"] + #[inline(always)] + pub fn is_cyc8(&self) -> bool { + **self == PER_A::CYC8 + } + #[doc = "Checks if the value of the field is `CYC16`"] + #[inline(always)] + pub fn is_cyc16(&self) -> bool { + **self == PER_A::CYC16 + } + #[doc = "Checks if the value of the field is `CYC32`"] + #[inline(always)] + pub fn is_cyc32(&self) -> bool { + **self == PER_A::CYC32 + } + #[doc = "Checks if the value of the field is `CYC64`"] + #[inline(always)] + pub fn is_cyc64(&self) -> bool { + **self == PER_A::CYC64 + } + #[doc = "Checks if the value of the field is `CYC128`"] + #[inline(always)] + pub fn is_cyc128(&self) -> bool { + **self == PER_A::CYC128 + } + #[doc = "Checks if the value of the field is `CYC256`"] + #[inline(always)] + pub fn is_cyc256(&self) -> bool { + **self == PER_A::CYC256 + } + #[doc = "Checks if the value of the field is `CYC512`"] + #[inline(always)] + pub fn is_cyc512(&self) -> bool { + **self == PER_A::CYC512 + } + #[doc = "Checks if the value of the field is `CYC1024`"] + #[inline(always)] + pub fn is_cyc1024(&self) -> bool { + **self == PER_A::CYC1024 + } + #[doc = "Checks if the value of the field is `CYC2048`"] + #[inline(always)] + pub fn is_cyc2048(&self) -> bool { + **self == PER_A::CYC2048 + } + #[doc = "Checks if the value of the field is `CYC4096`"] + #[inline(always)] + pub fn is_cyc4096(&self) -> bool { + **self == PER_A::CYC4096 + } + #[doc = "Checks if the value of the field is `CYC8192`"] + #[inline(always)] + pub fn is_cyc8192(&self) -> bool { + **self == PER_A::CYC8192 + } + #[doc = "Checks if the value of the field is `CYC16384`"] + #[inline(always)] + pub fn is_cyc16384(&self) -> bool { + **self == PER_A::CYC16384 + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` writer - Time-Out Period"] +pub struct PER_W<'a> { + w: &'a mut W, +} +impl<'a> PER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PER_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8 clock cycles"] + #[inline(always)] + pub fn cyc8(self) -> &'a mut W { + self.variant(PER_A::CYC8) + } + #[doc = "16 clock cycles"] + #[inline(always)] + pub fn cyc16(self) -> &'a mut W { + self.variant(PER_A::CYC16) + } + #[doc = "32 clock cycles"] + #[inline(always)] + pub fn cyc32(self) -> &'a mut W { + self.variant(PER_A::CYC32) + } + #[doc = "64 clock cycles"] + #[inline(always)] + pub fn cyc64(self) -> &'a mut W { + self.variant(PER_A::CYC64) + } + #[doc = "128 clock cycles"] + #[inline(always)] + pub fn cyc128(self) -> &'a mut W { + self.variant(PER_A::CYC128) + } + #[doc = "256 clock cycles"] + #[inline(always)] + pub fn cyc256(self) -> &'a mut W { + self.variant(PER_A::CYC256) + } + #[doc = "512 clock cycles"] + #[inline(always)] + pub fn cyc512(self) -> &'a mut W { + self.variant(PER_A::CYC512) + } + #[doc = "1024 clock cycles"] + #[inline(always)] + pub fn cyc1024(self) -> &'a mut W { + self.variant(PER_A::CYC1024) + } + #[doc = "2048 clock cycles"] + #[inline(always)] + pub fn cyc2048(self) -> &'a mut W { + self.variant(PER_A::CYC2048) + } + #[doc = "4096 clock cycles"] + #[inline(always)] + pub fn cyc4096(self) -> &'a mut W { + self.variant(PER_A::CYC4096) + } + #[doc = "8192 clock cycles"] + #[inline(always)] + pub fn cyc8192(self) -> &'a mut W { + self.variant(PER_A::CYC8192) + } + #[doc = "16384 clock cycles"] + #[inline(always)] + pub fn cyc16384(self) -> &'a mut W { + self.variant(PER_A::CYC16384) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +#[doc = "Window Mode Time-Out Period\n\nValue on reset: 11"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WINDOW_A { + #[doc = "0: 8 clock cycles"] + CYC8 = 0, + #[doc = "1: 16 clock cycles"] + CYC16 = 1, + #[doc = "2: 32 clock cycles"] + CYC32 = 2, + #[doc = "3: 64 clock cycles"] + CYC64 = 3, + #[doc = "4: 128 clock cycles"] + CYC128 = 4, + #[doc = "5: 256 clock cycles"] + CYC256 = 5, + #[doc = "6: 512 clock cycles"] + CYC512 = 6, + #[doc = "7: 1024 clock cycles"] + CYC1024 = 7, + #[doc = "8: 2048 clock cycles"] + CYC2048 = 8, + #[doc = "9: 4096 clock cycles"] + CYC4096 = 9, + #[doc = "10: 8192 clock cycles"] + CYC8192 = 10, + #[doc = "11: 16384 clock cycles"] + CYC16384 = 11, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WINDOW_A) -> Self { + variant as _ + } +} +#[doc = "Field `WINDOW` reader - Window Mode Time-Out Period"] +pub struct WINDOW_R(crate::FieldReader); +impl WINDOW_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WINDOW_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(WINDOW_A::CYC8), + 1 => Some(WINDOW_A::CYC16), + 2 => Some(WINDOW_A::CYC32), + 3 => Some(WINDOW_A::CYC64), + 4 => Some(WINDOW_A::CYC128), + 5 => Some(WINDOW_A::CYC256), + 6 => Some(WINDOW_A::CYC512), + 7 => Some(WINDOW_A::CYC1024), + 8 => Some(WINDOW_A::CYC2048), + 9 => Some(WINDOW_A::CYC4096), + 10 => Some(WINDOW_A::CYC8192), + 11 => Some(WINDOW_A::CYC16384), + _ => None, + } + } + #[doc = "Checks if the value of the field is `CYC8`"] + #[inline(always)] + pub fn is_cyc8(&self) -> bool { + **self == WINDOW_A::CYC8 + } + #[doc = "Checks if the value of the field is `CYC16`"] + #[inline(always)] + pub fn is_cyc16(&self) -> bool { + **self == WINDOW_A::CYC16 + } + #[doc = "Checks if the value of the field is `CYC32`"] + #[inline(always)] + pub fn is_cyc32(&self) -> bool { + **self == WINDOW_A::CYC32 + } + #[doc = "Checks if the value of the field is `CYC64`"] + #[inline(always)] + pub fn is_cyc64(&self) -> bool { + **self == WINDOW_A::CYC64 + } + #[doc = "Checks if the value of the field is `CYC128`"] + #[inline(always)] + pub fn is_cyc128(&self) -> bool { + **self == WINDOW_A::CYC128 + } + #[doc = "Checks if the value of the field is `CYC256`"] + #[inline(always)] + pub fn is_cyc256(&self) -> bool { + **self == WINDOW_A::CYC256 + } + #[doc = "Checks if the value of the field is `CYC512`"] + #[inline(always)] + pub fn is_cyc512(&self) -> bool { + **self == WINDOW_A::CYC512 + } + #[doc = "Checks if the value of the field is `CYC1024`"] + #[inline(always)] + pub fn is_cyc1024(&self) -> bool { + **self == WINDOW_A::CYC1024 + } + #[doc = "Checks if the value of the field is `CYC2048`"] + #[inline(always)] + pub fn is_cyc2048(&self) -> bool { + **self == WINDOW_A::CYC2048 + } + #[doc = "Checks if the value of the field is `CYC4096`"] + #[inline(always)] + pub fn is_cyc4096(&self) -> bool { + **self == WINDOW_A::CYC4096 + } + #[doc = "Checks if the value of the field is `CYC8192`"] + #[inline(always)] + pub fn is_cyc8192(&self) -> bool { + **self == WINDOW_A::CYC8192 + } + #[doc = "Checks if the value of the field is `CYC16384`"] + #[inline(always)] + pub fn is_cyc16384(&self) -> bool { + **self == WINDOW_A::CYC16384 + } +} +impl core::ops::Deref for WINDOW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINDOW` writer - Window Mode Time-Out Period"] +pub struct WINDOW_W<'a> { + w: &'a mut W, +} +impl<'a> WINDOW_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WINDOW_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8 clock cycles"] + #[inline(always)] + pub fn cyc8(self) -> &'a mut W { + self.variant(WINDOW_A::CYC8) + } + #[doc = "16 clock cycles"] + #[inline(always)] + pub fn cyc16(self) -> &'a mut W { + self.variant(WINDOW_A::CYC16) + } + #[doc = "32 clock cycles"] + #[inline(always)] + pub fn cyc32(self) -> &'a mut W { + self.variant(WINDOW_A::CYC32) + } + #[doc = "64 clock cycles"] + #[inline(always)] + pub fn cyc64(self) -> &'a mut W { + self.variant(WINDOW_A::CYC64) + } + #[doc = "128 clock cycles"] + #[inline(always)] + pub fn cyc128(self) -> &'a mut W { + self.variant(WINDOW_A::CYC128) + } + #[doc = "256 clock cycles"] + #[inline(always)] + pub fn cyc256(self) -> &'a mut W { + self.variant(WINDOW_A::CYC256) + } + #[doc = "512 clock cycles"] + #[inline(always)] + pub fn cyc512(self) -> &'a mut W { + self.variant(WINDOW_A::CYC512) + } + #[doc = "1024 clock cycles"] + #[inline(always)] + pub fn cyc1024(self) -> &'a mut W { + self.variant(WINDOW_A::CYC1024) + } + #[doc = "2048 clock cycles"] + #[inline(always)] + pub fn cyc2048(self) -> &'a mut W { + self.variant(WINDOW_A::CYC2048) + } + #[doc = "4096 clock cycles"] + #[inline(always)] + pub fn cyc4096(self) -> &'a mut W { + self.variant(WINDOW_A::CYC4096) + } + #[doc = "8192 clock cycles"] + #[inline(always)] + pub fn cyc8192(self) -> &'a mut W { + self.variant(WINDOW_A::CYC8192) + } + #[doc = "16384 clock cycles"] + #[inline(always)] + pub fn cyc16384(self) -> &'a mut W { + self.variant(WINDOW_A::CYC16384) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 4)) | ((value as u8 & 0x0f) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Time-Out Period"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Window Mode Time-Out Period"] + #[inline(always)] + pub fn window(&self) -> WINDOW_R { + WINDOW_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Time-Out Period"] + #[inline(always)] + pub fn per(&mut self) -> PER_W { + PER_W { w: self } + } + #[doc = "Bits 4:7 - Window Mode Time-Out Period"] + #[inline(always)] + pub fn window(&mut self) -> WINDOW_W { + WINDOW_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [config](index.html) module"] +pub struct CONFIG_SPEC; +impl crate::RegisterSpec for CONFIG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [config::R](R) reader structure"] +impl crate::Readable for CONFIG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [config::W](W) writer structure"] +impl crate::Writable for CONFIG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CONFIG to value 0xbb"] +impl crate::Resettable for CONFIG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xbb + } +} diff --git a/pac/atsamc20j/src/wdt/ctrla.rs b/pac/atsamc20j/src/wdt/ctrla.rs new file mode 100644 index 000000000000..895169d36aeb --- /dev/null +++ b/pac/atsamc20j/src/wdt/ctrla.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WEN` reader - Watchdog Timer Window Mode Enable"] +pub struct WEN_R(crate::FieldReader); +impl WEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WEN` writer - Watchdog Timer Window Mode Enable"] +pub struct WEN_W<'a> { + w: &'a mut W, +} +impl<'a> WEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `ALWAYSON` reader - Always-On"] +pub struct ALWAYSON_R(crate::FieldReader); +impl ALWAYSON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALWAYSON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALWAYSON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALWAYSON` writer - Always-On"] +pub struct ALWAYSON_W<'a> { + w: &'a mut W, +} +impl<'a> ALWAYSON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Watchdog Timer Window Mode Enable"] + #[inline(always)] + pub fn wen(&self) -> WEN_R { + WEN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 7 - Always-On"] + #[inline(always)] + pub fn alwayson(&self) -> ALWAYSON_R { + ALWAYSON_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - Watchdog Timer Window Mode Enable"] + #[inline(always)] + pub fn wen(&mut self) -> WEN_W { + WEN_W { w: self } + } + #[doc = "Bit 7 - Always-On"] + #[inline(always)] + pub fn alwayson(&mut self) -> ALWAYSON_W { + ALWAYSON_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/wdt/ewctrl.rs b/pac/atsamc20j/src/wdt/ewctrl.rs new file mode 100644 index 000000000000..94542e9897a9 --- /dev/null +++ b/pac/atsamc20j/src/wdt/ewctrl.rs @@ -0,0 +1,282 @@ +#[doc = "Register `EWCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EWCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Early Warning Interrupt Time Offset\n\nValue on reset: 11"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EWOFFSET_A { + #[doc = "0: 8 clock cycles"] + CYC8 = 0, + #[doc = "1: 16 clock cycles"] + CYC16 = 1, + #[doc = "2: 32 clock cycles"] + CYC32 = 2, + #[doc = "3: 64 clock cycles"] + CYC64 = 3, + #[doc = "4: 128 clock cycles"] + CYC128 = 4, + #[doc = "5: 256 clock cycles"] + CYC256 = 5, + #[doc = "6: 512 clock cycles"] + CYC512 = 6, + #[doc = "7: 1024 clock cycles"] + CYC1024 = 7, + #[doc = "8: 2048 clock cycles"] + CYC2048 = 8, + #[doc = "9: 4096 clock cycles"] + CYC4096 = 9, + #[doc = "10: 8192 clock cycles"] + CYC8192 = 10, + #[doc = "11: 16384 clock cycles"] + CYC16384 = 11, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EWOFFSET_A) -> Self { + variant as _ + } +} +#[doc = "Field `EWOFFSET` reader - Early Warning Interrupt Time Offset"] +pub struct EWOFFSET_R(crate::FieldReader); +impl EWOFFSET_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EWOFFSET_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(EWOFFSET_A::CYC8), + 1 => Some(EWOFFSET_A::CYC16), + 2 => Some(EWOFFSET_A::CYC32), + 3 => Some(EWOFFSET_A::CYC64), + 4 => Some(EWOFFSET_A::CYC128), + 5 => Some(EWOFFSET_A::CYC256), + 6 => Some(EWOFFSET_A::CYC512), + 7 => Some(EWOFFSET_A::CYC1024), + 8 => Some(EWOFFSET_A::CYC2048), + 9 => Some(EWOFFSET_A::CYC4096), + 10 => Some(EWOFFSET_A::CYC8192), + 11 => Some(EWOFFSET_A::CYC16384), + _ => None, + } + } + #[doc = "Checks if the value of the field is `CYC8`"] + #[inline(always)] + pub fn is_cyc8(&self) -> bool { + **self == EWOFFSET_A::CYC8 + } + #[doc = "Checks if the value of the field is `CYC16`"] + #[inline(always)] + pub fn is_cyc16(&self) -> bool { + **self == EWOFFSET_A::CYC16 + } + #[doc = "Checks if the value of the field is `CYC32`"] + #[inline(always)] + pub fn is_cyc32(&self) -> bool { + **self == EWOFFSET_A::CYC32 + } + #[doc = "Checks if the value of the field is `CYC64`"] + #[inline(always)] + pub fn is_cyc64(&self) -> bool { + **self == EWOFFSET_A::CYC64 + } + #[doc = "Checks if the value of the field is `CYC128`"] + #[inline(always)] + pub fn is_cyc128(&self) -> bool { + **self == EWOFFSET_A::CYC128 + } + #[doc = "Checks if the value of the field is `CYC256`"] + #[inline(always)] + pub fn is_cyc256(&self) -> bool { + **self == EWOFFSET_A::CYC256 + } + #[doc = "Checks if the value of the field is `CYC512`"] + #[inline(always)] + pub fn is_cyc512(&self) -> bool { + **self == EWOFFSET_A::CYC512 + } + #[doc = "Checks if the value of the field is `CYC1024`"] + #[inline(always)] + pub fn is_cyc1024(&self) -> bool { + **self == EWOFFSET_A::CYC1024 + } + #[doc = "Checks if the value of the field is `CYC2048`"] + #[inline(always)] + pub fn is_cyc2048(&self) -> bool { + **self == EWOFFSET_A::CYC2048 + } + #[doc = "Checks if the value of the field is `CYC4096`"] + #[inline(always)] + pub fn is_cyc4096(&self) -> bool { + **self == EWOFFSET_A::CYC4096 + } + #[doc = "Checks if the value of the field is `CYC8192`"] + #[inline(always)] + pub fn is_cyc8192(&self) -> bool { + **self == EWOFFSET_A::CYC8192 + } + #[doc = "Checks if the value of the field is `CYC16384`"] + #[inline(always)] + pub fn is_cyc16384(&self) -> bool { + **self == EWOFFSET_A::CYC16384 + } +} +impl core::ops::Deref for EWOFFSET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EWOFFSET` writer - Early Warning Interrupt Time Offset"] +pub struct EWOFFSET_W<'a> { + w: &'a mut W, +} +impl<'a> EWOFFSET_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EWOFFSET_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8 clock cycles"] + #[inline(always)] + pub fn cyc8(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC8) + } + #[doc = "16 clock cycles"] + #[inline(always)] + pub fn cyc16(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC16) + } + #[doc = "32 clock cycles"] + #[inline(always)] + pub fn cyc32(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC32) + } + #[doc = "64 clock cycles"] + #[inline(always)] + pub fn cyc64(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC64) + } + #[doc = "128 clock cycles"] + #[inline(always)] + pub fn cyc128(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC128) + } + #[doc = "256 clock cycles"] + #[inline(always)] + pub fn cyc256(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC256) + } + #[doc = "512 clock cycles"] + #[inline(always)] + pub fn cyc512(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC512) + } + #[doc = "1024 clock cycles"] + #[inline(always)] + pub fn cyc1024(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC1024) + } + #[doc = "2048 clock cycles"] + #[inline(always)] + pub fn cyc2048(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC2048) + } + #[doc = "4096 clock cycles"] + #[inline(always)] + pub fn cyc4096(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC4096) + } + #[doc = "8192 clock cycles"] + #[inline(always)] + pub fn cyc8192(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC8192) + } + #[doc = "16384 clock cycles"] + #[inline(always)] + pub fn cyc16384(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC16384) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Early Warning Interrupt Time Offset"] + #[inline(always)] + pub fn ewoffset(&self) -> EWOFFSET_R { + EWOFFSET_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Early Warning Interrupt Time Offset"] + #[inline(always)] + pub fn ewoffset(&mut self) -> EWOFFSET_W { + EWOFFSET_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Early Warning Interrupt Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ewctrl](index.html) module"] +pub struct EWCTRL_SPEC; +impl crate::RegisterSpec for EWCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ewctrl::R](R) reader structure"] +impl crate::Readable for EWCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ewctrl::W](W) writer structure"] +impl crate::Writable for EWCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EWCTRL to value 0x0b"] +impl crate::Resettable for EWCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0b + } +} diff --git a/pac/atsamc20j/src/wdt/intenclr.rs b/pac/atsamc20j/src/wdt/intenclr.rs new file mode 100644 index 000000000000..ed4021f96cce --- /dev/null +++ b/pac/atsamc20j/src/wdt/intenclr.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EW` reader - Early Warning Interrupt Enable"] +pub struct EW_R(crate::FieldReader); +impl EW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EW` writer - Early Warning Interrupt Enable"] +pub struct EW_W<'a> { + w: &'a mut W, +} +impl<'a> EW_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Early Warning Interrupt Enable"] + #[inline(always)] + pub fn ew(&self) -> EW_R { + EW_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Early Warning Interrupt Enable"] + #[inline(always)] + pub fn ew(&mut self) -> EW_W { + EW_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/wdt/intenset.rs b/pac/atsamc20j/src/wdt/intenset.rs new file mode 100644 index 000000000000..5a0928ff0532 --- /dev/null +++ b/pac/atsamc20j/src/wdt/intenset.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EW` reader - Early Warning Interrupt Enable"] +pub struct EW_R(crate::FieldReader); +impl EW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EW` writer - Early Warning Interrupt Enable"] +pub struct EW_W<'a> { + w: &'a mut W, +} +impl<'a> EW_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Early Warning Interrupt Enable"] + #[inline(always)] + pub fn ew(&self) -> EW_R { + EW_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Early Warning Interrupt Enable"] + #[inline(always)] + pub fn ew(&mut self) -> EW_W { + EW_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/wdt/intflag.rs b/pac/atsamc20j/src/wdt/intflag.rs new file mode 100644 index 000000000000..f2c9b858a199 --- /dev/null +++ b/pac/atsamc20j/src/wdt/intflag.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EW` reader - Early Warning"] +pub struct EW_R(crate::FieldReader); +impl EW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EW` writer - Early Warning"] +pub struct EW_W<'a> { + w: &'a mut W, +} +impl<'a> EW_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Early Warning"] + #[inline(always)] + pub fn ew(&self) -> EW_R { + EW_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Early Warning"] + #[inline(always)] + pub fn ew(&mut self) -> EW_W { + EW_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20j/src/wdt/syncbusy.rs b/pac/atsamc20j/src/wdt/syncbusy.rs new file mode 100644 index 000000000000..a3ecf7fbdb8a --- /dev/null +++ b/pac/atsamc20j/src/wdt/syncbusy.rs @@ -0,0 +1,113 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `ENABLE` reader - Enable Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WEN` reader - Window Enable Busy"] +pub struct WEN_R(crate::FieldReader); +impl WEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALWAYSON` reader - Always-On Busy"] +pub struct ALWAYSON_R(crate::FieldReader); +impl ALWAYSON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALWAYSON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALWAYSON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLEAR` reader - Clear Busy"] +pub struct CLEAR_R(crate::FieldReader); +impl CLEAR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLEAR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLEAR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 1 - Enable Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Window Enable Busy"] + #[inline(always)] + pub fn wen(&self) -> WEN_R { + WEN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Always-On Busy"] + #[inline(always)] + pub fn alwayson(&self) -> ALWAYSON_R { + ALWAYSON_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Clear Busy"] + #[inline(always)] + pub fn clear(&self) -> CLEAR_R { + CLEAR_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +#[doc = "Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/CHANGELOG.md b/pac/atsamc20n/CHANGELOG.md new file mode 100644 index 000000000000..e28d85f63b31 --- /dev/null +++ b/pac/atsamc20n/CHANGELOG.md @@ -0,0 +1,6 @@ +# Unreleased + +- Initial version +--- + +Changelog tracking started at v0.0.1 diff --git a/pac/atsamc20n/Cargo.toml b/pac/atsamc20n/Cargo.toml new file mode 100644 index 000000000000..c81c503b6cf8 --- /dev/null +++ b/pac/atsamc20n/Cargo.toml @@ -0,0 +1,22 @@ +[package] +name = "atsamc20n" +description = "Peripheral access API for ATSAMC20N microcontrollers (generated using svd2rust)" +version = "0.0.1" +authors = ["Jeremy Boynes "] +keywords = ["no-std", "arm", "cortex-m"] +categories = ["embedded", "hardware-support", "no-std"] +license = "MIT OR Apache-2.0" +repository = "https://github.com/atsamd-rs/atsamd" +readme = "README.md" +edition = "2021" + +[dependencies] +cortex-m = "0.7" +vcell = "0.1" + +[dependencies.cortex-m-rt] +version = "0.7" +optional = true + +[features] +rt = ["cortex-m-rt/device"] diff --git a/pac/atsamc20n/README.md b/pac/atsamc20n/README.md new file mode 100644 index 000000000000..2491310ee9da --- /dev/null +++ b/pac/atsamc20n/README.md @@ -0,0 +1,26 @@ +# ATSAMC20N + +A peripheral access crate for the ATSAMC20N chip from Microchip (née Atmel) for Rust Embedded projects. + +[![Build Status](https://travis-ci.org/atsamd-rs/atsamd.svg?branch=master)](https://travis-ci.org/atsamd-rs/atsamd) +[![Crates.io](https://img.shields.io/crates/v/atsamc20n.svg)](https://crates.io/crates/atsamc20n) + +## [Documentation](https://docs.rs/atsamc20n) + +This source was automatically generated using `svd2rust`, split into smaller pieces using `form` and formatted via `rustfmt`. + +## License + +Licensed under either of: + +- Apache License, Version 2.0 ([LICENSE-APACHE](https://github.com/atsamd-rs/atsamd/blob/master/LICENSE-APACHE) or + http://www.apache.org/licenses/LICENSE-2.0) +- MIT license ([LICENSE-MIT](https://github.com/atsamd-rs/atsamd/blob/master/LICENSE-MIT) or http://opensource.org/licenses/MIT) + +at your option. + +### Contribution + +Unless you explicitly state otherwise, any contribution intentionally submitted +for inclusion in the work by you, as defined in the Apache-2.0 license, shall +be dual licensed as above, without any additional terms or conditions. diff --git a/pac/atsamc20n/build.rs b/pac/atsamc20n/build.rs new file mode 100644 index 000000000000..597923f50892 --- /dev/null +++ b/pac/atsamc20n/build.rs @@ -0,0 +1,16 @@ +use std::env; +use std::fs::File; +use std::io::Write; +use std::path::PathBuf; +fn main() { + if env::var_os("CARGO_FEATURE_RT").is_some() { + let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap()); + File::create(out.join("device.x")) + .unwrap() + .write_all(include_bytes!("device.x")) + .unwrap(); + println!("cargo:rustc-link-search={}", out.display()); + println!("cargo:rerun-if-changed=device.x"); + } + println!("cargo:rerun-if-changed=build.rs"); +} diff --git a/pac/atsamc20n/device.x b/pac/atsamc20n/device.x new file mode 100644 index 000000000000..a3d3f9dc0478 --- /dev/null +++ b/pac/atsamc20n/device.x @@ -0,0 +1,20 @@ +PROVIDE(WDT = DefaultHandler); +PROVIDE(RTC = DefaultHandler); +PROVIDE(EIC = DefaultHandler); +PROVIDE(FREQM = DefaultHandler); +PROVIDE(NVMCTRL = DefaultHandler); +PROVIDE(DMAC = DefaultHandler); +PROVIDE(EVSYS = DefaultHandler); +PROVIDE(SERCOM2 = DefaultHandler); +PROVIDE(SERCOM3 = DefaultHandler); +PROVIDE(SERCOM4 = DefaultHandler); +PROVIDE(SERCOM5 = DefaultHandler); +PROVIDE(TCC0 = DefaultHandler); +PROVIDE(TCC1 = DefaultHandler); +PROVIDE(TCC2 = DefaultHandler); +PROVIDE(TC3 = DefaultHandler); +PROVIDE(TC4 = DefaultHandler); +PROVIDE(ADC0 = DefaultHandler); +PROVIDE(AC = DefaultHandler); +PROVIDE(PTC = DefaultHandler); + diff --git a/pac/atsamc20n/src/ac.rs b/pac/atsamc20n/src/ac.rs new file mode 100644 index 000000000000..b66620475572 --- /dev/null +++ b/pac/atsamc20n/src/ac.rs @@ -0,0 +1,83 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + #[doc = "0x01 - Control B"] + pub ctrlb: crate::Reg, + #[doc = "0x02 - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x04 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x05 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x06 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x07 - Status A"] + pub statusa: crate::Reg, + #[doc = "0x08 - Status B"] + pub statusb: crate::Reg, + #[doc = "0x09 - Debug Control"] + pub dbgctrl: crate::Reg, + #[doc = "0x0a - Window Control"] + pub winctrl: crate::Reg, + _reserved10: [u8; 0x01], + #[doc = "0x0c - Scaler n"] + pub scaler: [crate::Reg; 4], + #[doc = "0x10..0x20 - Comparator Control n"] + pub compctrl: [crate::Reg; 4], + #[doc = "0x20 - Synchronization Busy"] + pub syncbusy: crate::Reg, +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "Control B"] +pub mod ctrlb; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUSA register accessor: an alias for `Reg`"] +pub type STATUSA = crate::Reg; +#[doc = "Status A"] +pub mod statusa; +#[doc = "STATUSB register accessor: an alias for `Reg`"] +pub type STATUSB = crate::Reg; +#[doc = "Status B"] +pub mod statusb; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "WINCTRL register accessor: an alias for `Reg`"] +pub type WINCTRL = crate::Reg; +#[doc = "Window Control"] +pub mod winctrl; +#[doc = "SCALER register accessor: an alias for `Reg`"] +pub type SCALER = crate::Reg; +#[doc = "Scaler n"] +pub mod scaler; +#[doc = "COMPCTRL register accessor: an alias for `Reg`"] +pub type COMPCTRL = crate::Reg; +#[doc = "Comparator Control n"] +pub mod compctrl; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Busy"] +pub mod syncbusy; diff --git a/pac/atsamc20n/src/ac/compctrl.rs b/pac/atsamc20n/src/ac/compctrl.rs new file mode 100644 index 000000000000..c52cb53fe56f --- /dev/null +++ b/pac/atsamc20n/src/ac/compctrl.rs @@ -0,0 +1,974 @@ +#[doc = "Register `COMPCTRL[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COMPCTRL[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SINGLE` reader - Single-Shot Mode"] +pub struct SINGLE_R(crate::FieldReader); +impl SINGLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SINGLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SINGLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SINGLE` writer - Single-Shot Mode"] +pub struct SINGLE_W<'a> { + w: &'a mut W, +} +impl<'a> SINGLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Interrupt Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum INTSEL_A { + #[doc = "0: Interrupt on comparator output toggle"] + TOGGLE = 0, + #[doc = "1: Interrupt on comparator output rising"] + RISING = 1, + #[doc = "2: Interrupt on comparator output falling"] + FALLING = 2, + #[doc = "3: Interrupt on end of comparison (single-shot mode only)"] + EOC = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: INTSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `INTSEL` reader - Interrupt Selection"] +pub struct INTSEL_R(crate::FieldReader); +impl INTSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + INTSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INTSEL_A { + match self.bits { + 0 => INTSEL_A::TOGGLE, + 1 => INTSEL_A::RISING, + 2 => INTSEL_A::FALLING, + 3 => INTSEL_A::EOC, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `TOGGLE`"] + #[inline(always)] + pub fn is_toggle(&self) -> bool { + **self == INTSEL_A::TOGGLE + } + #[doc = "Checks if the value of the field is `RISING`"] + #[inline(always)] + pub fn is_rising(&self) -> bool { + **self == INTSEL_A::RISING + } + #[doc = "Checks if the value of the field is `FALLING`"] + #[inline(always)] + pub fn is_falling(&self) -> bool { + **self == INTSEL_A::FALLING + } + #[doc = "Checks if the value of the field is `EOC`"] + #[inline(always)] + pub fn is_eoc(&self) -> bool { + **self == INTSEL_A::EOC + } +} +impl core::ops::Deref for INTSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INTSEL` writer - Interrupt Selection"] +pub struct INTSEL_W<'a> { + w: &'a mut W, +} +impl<'a> INTSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: INTSEL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Interrupt on comparator output toggle"] + #[inline(always)] + pub fn toggle(self) -> &'a mut W { + self.variant(INTSEL_A::TOGGLE) + } + #[doc = "Interrupt on comparator output rising"] + #[inline(always)] + pub fn rising(self) -> &'a mut W { + self.variant(INTSEL_A::RISING) + } + #[doc = "Interrupt on comparator output falling"] + #[inline(always)] + pub fn falling(self) -> &'a mut W { + self.variant(INTSEL_A::FALLING) + } + #[doc = "Interrupt on end of comparison (single-shot mode only)"] + #[inline(always)] + pub fn eoc(self) -> &'a mut W { + self.variant(INTSEL_A::EOC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 3)) | ((value as u32 & 0x03) << 3); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Negative Input Mux Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MUXNEG_A { + #[doc = "0: I/O pin 0"] + PIN0 = 0, + #[doc = "1: I/O pin 1"] + PIN1 = 1, + #[doc = "2: I/O pin 2"] + PIN2 = 2, + #[doc = "3: I/O pin 3"] + PIN3 = 3, + #[doc = "4: Ground"] + GND = 4, + #[doc = "5: VDD scaler"] + VSCALE = 5, + #[doc = "6: Internal bandgap voltage"] + BANDGAP = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MUXNEG_A) -> Self { + variant as _ + } +} +#[doc = "Field `MUXNEG` reader - Negative Input Mux Selection"] +pub struct MUXNEG_R(crate::FieldReader); +impl MUXNEG_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MUXNEG_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MUXNEG_A::PIN0), + 1 => Some(MUXNEG_A::PIN1), + 2 => Some(MUXNEG_A::PIN2), + 3 => Some(MUXNEG_A::PIN3), + 4 => Some(MUXNEG_A::GND), + 5 => Some(MUXNEG_A::VSCALE), + 6 => Some(MUXNEG_A::BANDGAP), + _ => None, + } + } + #[doc = "Checks if the value of the field is `PIN0`"] + #[inline(always)] + pub fn is_pin0(&self) -> bool { + **self == MUXNEG_A::PIN0 + } + #[doc = "Checks if the value of the field is `PIN1`"] + #[inline(always)] + pub fn is_pin1(&self) -> bool { + **self == MUXNEG_A::PIN1 + } + #[doc = "Checks if the value of the field is `PIN2`"] + #[inline(always)] + pub fn is_pin2(&self) -> bool { + **self == MUXNEG_A::PIN2 + } + #[doc = "Checks if the value of the field is `PIN3`"] + #[inline(always)] + pub fn is_pin3(&self) -> bool { + **self == MUXNEG_A::PIN3 + } + #[doc = "Checks if the value of the field is `GND`"] + #[inline(always)] + pub fn is_gnd(&self) -> bool { + **self == MUXNEG_A::GND + } + #[doc = "Checks if the value of the field is `VSCALE`"] + #[inline(always)] + pub fn is_vscale(&self) -> bool { + **self == MUXNEG_A::VSCALE + } + #[doc = "Checks if the value of the field is `BANDGAP`"] + #[inline(always)] + pub fn is_bandgap(&self) -> bool { + **self == MUXNEG_A::BANDGAP + } +} +impl core::ops::Deref for MUXNEG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MUXNEG` writer - Negative Input Mux Selection"] +pub struct MUXNEG_W<'a> { + w: &'a mut W, +} +impl<'a> MUXNEG_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MUXNEG_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "I/O pin 0"] + #[inline(always)] + pub fn pin0(self) -> &'a mut W { + self.variant(MUXNEG_A::PIN0) + } + #[doc = "I/O pin 1"] + #[inline(always)] + pub fn pin1(self) -> &'a mut W { + self.variant(MUXNEG_A::PIN1) + } + #[doc = "I/O pin 2"] + #[inline(always)] + pub fn pin2(self) -> &'a mut W { + self.variant(MUXNEG_A::PIN2) + } + #[doc = "I/O pin 3"] + #[inline(always)] + pub fn pin3(self) -> &'a mut W { + self.variant(MUXNEG_A::PIN3) + } + #[doc = "Ground"] + #[inline(always)] + pub fn gnd(self) -> &'a mut W { + self.variant(MUXNEG_A::GND) + } + #[doc = "VDD scaler"] + #[inline(always)] + pub fn vscale(self) -> &'a mut W { + self.variant(MUXNEG_A::VSCALE) + } + #[doc = "Internal bandgap voltage"] + #[inline(always)] + pub fn bandgap(self) -> &'a mut W { + self.variant(MUXNEG_A::BANDGAP) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +#[doc = "Positive Input Mux Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MUXPOS_A { + #[doc = "0: I/O pin 0"] + PIN0 = 0, + #[doc = "1: I/O pin 1"] + PIN1 = 1, + #[doc = "2: I/O pin 2"] + PIN2 = 2, + #[doc = "3: I/O pin 3"] + PIN3 = 3, + #[doc = "4: VDD Scaler"] + VSCALE = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MUXPOS_A) -> Self { + variant as _ + } +} +#[doc = "Field `MUXPOS` reader - Positive Input Mux Selection"] +pub struct MUXPOS_R(crate::FieldReader); +impl MUXPOS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MUXPOS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MUXPOS_A::PIN0), + 1 => Some(MUXPOS_A::PIN1), + 2 => Some(MUXPOS_A::PIN2), + 3 => Some(MUXPOS_A::PIN3), + 4 => Some(MUXPOS_A::VSCALE), + _ => None, + } + } + #[doc = "Checks if the value of the field is `PIN0`"] + #[inline(always)] + pub fn is_pin0(&self) -> bool { + **self == MUXPOS_A::PIN0 + } + #[doc = "Checks if the value of the field is `PIN1`"] + #[inline(always)] + pub fn is_pin1(&self) -> bool { + **self == MUXPOS_A::PIN1 + } + #[doc = "Checks if the value of the field is `PIN2`"] + #[inline(always)] + pub fn is_pin2(&self) -> bool { + **self == MUXPOS_A::PIN2 + } + #[doc = "Checks if the value of the field is `PIN3`"] + #[inline(always)] + pub fn is_pin3(&self) -> bool { + **self == MUXPOS_A::PIN3 + } + #[doc = "Checks if the value of the field is `VSCALE`"] + #[inline(always)] + pub fn is_vscale(&self) -> bool { + **self == MUXPOS_A::VSCALE + } +} +impl core::ops::Deref for MUXPOS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MUXPOS` writer - Positive Input Mux Selection"] +pub struct MUXPOS_W<'a> { + w: &'a mut W, +} +impl<'a> MUXPOS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MUXPOS_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "I/O pin 0"] + #[inline(always)] + pub fn pin0(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN0) + } + #[doc = "I/O pin 1"] + #[inline(always)] + pub fn pin1(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN1) + } + #[doc = "I/O pin 2"] + #[inline(always)] + pub fn pin2(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN2) + } + #[doc = "I/O pin 3"] + #[inline(always)] + pub fn pin3(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN3) + } + #[doc = "VDD Scaler"] + #[inline(always)] + pub fn vscale(self) -> &'a mut W { + self.variant(MUXPOS_A::VSCALE) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 12)) | ((value as u32 & 0x07) << 12); + self.w + } +} +#[doc = "Field `SWAP` reader - Swap Inputs and Invert"] +pub struct SWAP_R(crate::FieldReader); +impl SWAP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWAP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWAP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWAP` writer - Swap Inputs and Invert"] +pub struct SWAP_W<'a> { + w: &'a mut W, +} +impl<'a> SWAP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Speed Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SPEED_A { + #[doc = "0: Low speed"] + LOW = 0, + #[doc = "3: High speed"] + HIGH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SPEED_A) -> Self { + variant as _ + } +} +#[doc = "Field `SPEED` reader - Speed Selection"] +pub struct SPEED_R(crate::FieldReader); +impl SPEED_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SPEED_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SPEED_A::LOW), + 3 => Some(SPEED_A::HIGH), + _ => None, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SPEED_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SPEED_A::HIGH + } +} +impl core::ops::Deref for SPEED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SPEED` writer - Speed Selection"] +pub struct SPEED_W<'a> { + w: &'a mut W, +} +impl<'a> SPEED_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SPEED_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Low speed"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SPEED_A::LOW) + } + #[doc = "High speed"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SPEED_A::HIGH) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Field `HYSTEN` reader - Hysteresis Enable"] +pub struct HYSTEN_R(crate::FieldReader); +impl HYSTEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HYSTEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HYSTEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HYSTEN` writer - Hysteresis Enable"] +pub struct HYSTEN_W<'a> { + w: &'a mut W, +} +impl<'a> HYSTEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Filter Length\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FLEN_A { + #[doc = "0: No filtering"] + OFF = 0, + #[doc = "1: 3-bit majority function (2 of 3)"] + MAJ3 = 1, + #[doc = "2: 5-bit majority function (3 of 5)"] + MAJ5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FLEN_A) -> Self { + variant as _ + } +} +#[doc = "Field `FLEN` reader - Filter Length"] +pub struct FLEN_R(crate::FieldReader); +impl FLEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FLEN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(FLEN_A::OFF), + 1 => Some(FLEN_A::MAJ3), + 2 => Some(FLEN_A::MAJ5), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == FLEN_A::OFF + } + #[doc = "Checks if the value of the field is `MAJ3`"] + #[inline(always)] + pub fn is_maj3(&self) -> bool { + **self == FLEN_A::MAJ3 + } + #[doc = "Checks if the value of the field is `MAJ5`"] + #[inline(always)] + pub fn is_maj5(&self) -> bool { + **self == FLEN_A::MAJ5 + } +} +impl core::ops::Deref for FLEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLEN` writer - Filter Length"] +pub struct FLEN_W<'a> { + w: &'a mut W, +} +impl<'a> FLEN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FLEN_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No filtering"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(FLEN_A::OFF) + } + #[doc = "3-bit majority function (2 of 3)"] + #[inline(always)] + pub fn maj3(self) -> &'a mut W { + self.variant(FLEN_A::MAJ3) + } + #[doc = "5-bit majority function (3 of 5)"] + #[inline(always)] + pub fn maj5(self) -> &'a mut W { + self.variant(FLEN_A::MAJ5) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 24)) | ((value as u32 & 0x07) << 24); + self.w + } +} +#[doc = "Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum OUT_A { + #[doc = "0: The output of COMPn is not routed to the COMPn I/O port"] + OFF = 0, + #[doc = "1: The asynchronous output of COMPn is routed to the COMPn I/O port"] + ASYNC = 1, + #[doc = "2: The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port"] + SYNC = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: OUT_A) -> Self { + variant as _ + } +} +#[doc = "Field `OUT` reader - Output"] +pub struct OUT_R(crate::FieldReader); +impl OUT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + OUT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(OUT_A::OFF), + 1 => Some(OUT_A::ASYNC), + 2 => Some(OUT_A::SYNC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == OUT_A::OFF + } + #[doc = "Checks if the value of the field is `ASYNC`"] + #[inline(always)] + pub fn is_async(&self) -> bool { + **self == OUT_A::ASYNC + } + #[doc = "Checks if the value of the field is `SYNC`"] + #[inline(always)] + pub fn is_sync(&self) -> bool { + **self == OUT_A::SYNC + } +} +impl core::ops::Deref for OUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OUT` writer - Output"] +pub struct OUT_W<'a> { + w: &'a mut W, +} +impl<'a> OUT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: OUT_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "The output of COMPn is not routed to the COMPn I/O port"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(OUT_A::OFF) + } + #[doc = "The asynchronous output of COMPn is routed to the COMPn I/O port"] + #[inline(always)] + pub fn async_(self) -> &'a mut W { + self.variant(OUT_A::ASYNC) + } + #[doc = "The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port"] + #[inline(always)] + pub fn sync(self) -> &'a mut W { + self.variant(OUT_A::SYNC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 28)) | ((value as u32 & 0x03) << 28); + self.w + } +} +impl R { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Single-Shot Mode"] + #[inline(always)] + pub fn single(&self) -> SINGLE_R { + SINGLE_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 3:4 - Interrupt Selection"] + #[inline(always)] + pub fn intsel(&self) -> INTSEL_R { + INTSEL_R::new(((self.bits >> 3) & 0x03) as u8) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Negative Input Mux Selection"] + #[inline(always)] + pub fn muxneg(&self) -> MUXNEG_R { + MUXNEG_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bits 12:14 - Positive Input Mux Selection"] + #[inline(always)] + pub fn muxpos(&self) -> MUXPOS_R { + MUXPOS_R::new(((self.bits >> 12) & 0x07) as u8) + } + #[doc = "Bit 15 - Swap Inputs and Invert"] + #[inline(always)] + pub fn swap(&self) -> SWAP_R { + SWAP_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:17 - Speed Selection"] + #[inline(always)] + pub fn speed(&self) -> SPEED_R { + SPEED_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bit 19 - Hysteresis Enable"] + #[inline(always)] + pub fn hysten(&self) -> HYSTEN_R { + HYSTEN_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bits 24:26 - Filter Length"] + #[inline(always)] + pub fn flen(&self) -> FLEN_R { + FLEN_R::new(((self.bits >> 24) & 0x07) as u8) + } + #[doc = "Bits 28:29 - Output"] + #[inline(always)] + pub fn out(&self) -> OUT_R { + OUT_R::new(((self.bits >> 28) & 0x03) as u8) + } +} +impl W { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - Single-Shot Mode"] + #[inline(always)] + pub fn single(&mut self) -> SINGLE_W { + SINGLE_W { w: self } + } + #[doc = "Bits 3:4 - Interrupt Selection"] + #[inline(always)] + pub fn intsel(&mut self) -> INTSEL_W { + INTSEL_W { w: self } + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bits 8:10 - Negative Input Mux Selection"] + #[inline(always)] + pub fn muxneg(&mut self) -> MUXNEG_W { + MUXNEG_W { w: self } + } + #[doc = "Bits 12:14 - Positive Input Mux Selection"] + #[inline(always)] + pub fn muxpos(&mut self) -> MUXPOS_W { + MUXPOS_W { w: self } + } + #[doc = "Bit 15 - Swap Inputs and Invert"] + #[inline(always)] + pub fn swap(&mut self) -> SWAP_W { + SWAP_W { w: self } + } + #[doc = "Bits 16:17 - Speed Selection"] + #[inline(always)] + pub fn speed(&mut self) -> SPEED_W { + SPEED_W { w: self } + } + #[doc = "Bit 19 - Hysteresis Enable"] + #[inline(always)] + pub fn hysten(&mut self) -> HYSTEN_W { + HYSTEN_W { w: self } + } + #[doc = "Bits 24:26 - Filter Length"] + #[inline(always)] + pub fn flen(&mut self) -> FLEN_W { + FLEN_W { w: self } + } + #[doc = "Bits 28:29 - Output"] + #[inline(always)] + pub fn out(&mut self) -> OUT_W { + OUT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Comparator Control n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [compctrl](index.html) module"] +pub struct COMPCTRL_SPEC; +impl crate::RegisterSpec for COMPCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [compctrl::R](R) reader structure"] +impl crate::Readable for COMPCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [compctrl::W](W) writer structure"] +impl crate::Writable for COMPCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COMPCTRL[%s] +to value 0"] +impl crate::Resettable for COMPCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/ac/ctrla.rs b/pac/atsamc20n/src/ac/ctrla.rs new file mode 100644 index 000000000000..5f2c406226f4 --- /dev/null +++ b/pac/atsamc20n/src/ac/ctrla.rs @@ -0,0 +1,160 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/ac/ctrlb.rs b/pac/atsamc20n/src/ac/ctrlb.rs new file mode 100644 index 000000000000..fa9d604101c2 --- /dev/null +++ b/pac/atsamc20n/src/ac/ctrlb.rs @@ -0,0 +1,153 @@ +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `START0` writer - Comparator 0 Start Comparison"] +pub struct START0_W<'a> { + w: &'a mut W, +} +impl<'a> START0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `START1` writer - Comparator 1 Start Comparison"] +pub struct START1_W<'a> { + w: &'a mut W, +} +impl<'a> START1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `START2` writer - Comparator 2 Start Comparison"] +pub struct START2_W<'a> { + w: &'a mut W, +} +impl<'a> START2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `START3` writer - Comparator 3 Start Comparison"] +pub struct START3_W<'a> { + w: &'a mut W, +} +impl<'a> START3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +impl W { + #[doc = "Bit 0 - Comparator 0 Start Comparison"] + #[inline(always)] + pub fn start0(&mut self) -> START0_W { + START0_W { w: self } + } + #[doc = "Bit 1 - Comparator 1 Start Comparison"] + #[inline(always)] + pub fn start1(&mut self) -> START1_W { + START1_W { w: self } + } + #[doc = "Bit 2 - Comparator 2 Start Comparison"] + #[inline(always)] + pub fn start2(&mut self) -> START2_W { + START2_W { w: self } + } + #[doc = "Bit 3 - Comparator 3 Start Comparison"] + #[inline(always)] + pub fn start3(&mut self) -> START3_W { + START3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u8; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/ac/dbgctrl.rs b/pac/atsamc20n/src/ac/dbgctrl.rs new file mode 100644 index 000000000000..53636eb2b339 --- /dev/null +++ b/pac/atsamc20n/src/ac/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Debug Run"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Debug Run"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/ac/evctrl.rs b/pac/atsamc20n/src/ac/evctrl.rs new file mode 100644 index 000000000000..b2f64ee12108 --- /dev/null +++ b/pac/atsamc20n/src/ac/evctrl.rs @@ -0,0 +1,724 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COMPEO0` reader - Comparator 0 Event Output Enable"] +pub struct COMPEO0_R(crate::FieldReader); +impl COMPEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPEO0` writer - Comparator 0 Event Output Enable"] +pub struct COMPEO0_W<'a> { + w: &'a mut W, +} +impl<'a> COMPEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `COMPEO1` reader - Comparator 1 Event Output Enable"] +pub struct COMPEO1_R(crate::FieldReader); +impl COMPEO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPEO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPEO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPEO1` writer - Comparator 1 Event Output Enable"] +pub struct COMPEO1_W<'a> { + w: &'a mut W, +} +impl<'a> COMPEO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `COMPEO2` reader - Comparator 2 Event Output Enable"] +pub struct COMPEO2_R(crate::FieldReader); +impl COMPEO2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPEO2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPEO2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPEO2` writer - Comparator 2 Event Output Enable"] +pub struct COMPEO2_W<'a> { + w: &'a mut W, +} +impl<'a> COMPEO2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `COMPEO3` reader - Comparator 3 Event Output Enable"] +pub struct COMPEO3_R(crate::FieldReader); +impl COMPEO3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPEO3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPEO3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPEO3` writer - Comparator 3 Event Output Enable"] +pub struct COMPEO3_W<'a> { + w: &'a mut W, +} +impl<'a> COMPEO3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `WINEO0` reader - Window 0 Event Output Enable"] +pub struct WINEO0_R(crate::FieldReader); +impl WINEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINEO0` writer - Window 0 Event Output Enable"] +pub struct WINEO0_W<'a> { + w: &'a mut W, +} +impl<'a> WINEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `WINEO1` reader - Window 1 Event Output Enable"] +pub struct WINEO1_R(crate::FieldReader); +impl WINEO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINEO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINEO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINEO1` writer - Window 1 Event Output Enable"] +pub struct WINEO1_W<'a> { + w: &'a mut W, +} +impl<'a> WINEO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `COMPEI0` reader - Comparator 0 Event Input Enable"] +pub struct COMPEI0_R(crate::FieldReader); +impl COMPEI0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPEI0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPEI0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPEI0` writer - Comparator 0 Event Input Enable"] +pub struct COMPEI0_W<'a> { + w: &'a mut W, +} +impl<'a> COMPEI0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `COMPEI1` reader - Comparator 1 Event Input Enable"] +pub struct COMPEI1_R(crate::FieldReader); +impl COMPEI1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPEI1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPEI1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPEI1` writer - Comparator 1 Event Input Enable"] +pub struct COMPEI1_W<'a> { + w: &'a mut W, +} +impl<'a> COMPEI1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `COMPEI2` reader - Comparator 2 Event Input Enable"] +pub struct COMPEI2_R(crate::FieldReader); +impl COMPEI2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPEI2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPEI2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPEI2` writer - Comparator 2 Event Input Enable"] +pub struct COMPEI2_W<'a> { + w: &'a mut W, +} +impl<'a> COMPEI2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u16 & 0x01) << 10); + self.w + } +} +#[doc = "Field `COMPEI3` reader - Comparator 3 Event Input Enable"] +pub struct COMPEI3_R(crate::FieldReader); +impl COMPEI3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPEI3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPEI3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPEI3` writer - Comparator 3 Event Input Enable"] +pub struct COMPEI3_W<'a> { + w: &'a mut W, +} +impl<'a> COMPEI3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u16 & 0x01) << 11); + self.w + } +} +#[doc = "Field `INVEI0` reader - Comparator 0 Input Event Invert Enable"] +pub struct INVEI0_R(crate::FieldReader); +impl INVEI0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEI0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEI0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEI0` writer - Comparator 0 Input Event Invert Enable"] +pub struct INVEI0_W<'a> { + w: &'a mut W, +} +impl<'a> INVEI0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u16 & 0x01) << 12); + self.w + } +} +#[doc = "Field `INVEI1` reader - Comparator 1 Input Event Invert Enable"] +pub struct INVEI1_R(crate::FieldReader); +impl INVEI1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEI1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEI1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEI1` writer - Comparator 1 Input Event Invert Enable"] +pub struct INVEI1_W<'a> { + w: &'a mut W, +} +impl<'a> INVEI1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u16 & 0x01) << 13); + self.w + } +} +#[doc = "Field `INVEI2` reader - Comparator 2 Input Event Invert Enable"] +pub struct INVEI2_R(crate::FieldReader); +impl INVEI2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEI2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEI2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEI2` writer - Comparator 2 Input Event Invert Enable"] +pub struct INVEI2_W<'a> { + w: &'a mut W, +} +impl<'a> INVEI2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u16 & 0x01) << 14); + self.w + } +} +#[doc = "Field `INVEI3` reader - Comparator 3 Input Event Invert Enable"] +pub struct INVEI3_R(crate::FieldReader); +impl INVEI3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEI3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEI3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEI3` writer - Comparator 3 Input Event Invert Enable"] +pub struct INVEI3_W<'a> { + w: &'a mut W, +} +impl<'a> INVEI3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Comparator 0 Event Output Enable"] + #[inline(always)] + pub fn compeo0(&self) -> COMPEO0_R { + COMPEO0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Comparator 1 Event Output Enable"] + #[inline(always)] + pub fn compeo1(&self) -> COMPEO1_R { + COMPEO1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Comparator 2 Event Output Enable"] + #[inline(always)] + pub fn compeo2(&self) -> COMPEO2_R { + COMPEO2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Comparator 3 Event Output Enable"] + #[inline(always)] + pub fn compeo3(&self) -> COMPEO3_R { + COMPEO3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Window 0 Event Output Enable"] + #[inline(always)] + pub fn wineo0(&self) -> WINEO0_R { + WINEO0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Window 1 Event Output Enable"] + #[inline(always)] + pub fn wineo1(&self) -> WINEO1_R { + WINEO1_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 8 - Comparator 0 Event Input Enable"] + #[inline(always)] + pub fn compei0(&self) -> COMPEI0_R { + COMPEI0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Comparator 1 Event Input Enable"] + #[inline(always)] + pub fn compei1(&self) -> COMPEI1_R { + COMPEI1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Comparator 2 Event Input Enable"] + #[inline(always)] + pub fn compei2(&self) -> COMPEI2_R { + COMPEI2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Comparator 3 Event Input Enable"] + #[inline(always)] + pub fn compei3(&self) -> COMPEI3_R { + COMPEI3_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Comparator 0 Input Event Invert Enable"] + #[inline(always)] + pub fn invei0(&self) -> INVEI0_R { + INVEI0_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Comparator 1 Input Event Invert Enable"] + #[inline(always)] + pub fn invei1(&self) -> INVEI1_R { + INVEI1_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Comparator 2 Input Event Invert Enable"] + #[inline(always)] + pub fn invei2(&self) -> INVEI2_R { + INVEI2_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Comparator 3 Input Event Invert Enable"] + #[inline(always)] + pub fn invei3(&self) -> INVEI3_R { + INVEI3_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Comparator 0 Event Output Enable"] + #[inline(always)] + pub fn compeo0(&mut self) -> COMPEO0_W { + COMPEO0_W { w: self } + } + #[doc = "Bit 1 - Comparator 1 Event Output Enable"] + #[inline(always)] + pub fn compeo1(&mut self) -> COMPEO1_W { + COMPEO1_W { w: self } + } + #[doc = "Bit 2 - Comparator 2 Event Output Enable"] + #[inline(always)] + pub fn compeo2(&mut self) -> COMPEO2_W { + COMPEO2_W { w: self } + } + #[doc = "Bit 3 - Comparator 3 Event Output Enable"] + #[inline(always)] + pub fn compeo3(&mut self) -> COMPEO3_W { + COMPEO3_W { w: self } + } + #[doc = "Bit 4 - Window 0 Event Output Enable"] + #[inline(always)] + pub fn wineo0(&mut self) -> WINEO0_W { + WINEO0_W { w: self } + } + #[doc = "Bit 5 - Window 1 Event Output Enable"] + #[inline(always)] + pub fn wineo1(&mut self) -> WINEO1_W { + WINEO1_W { w: self } + } + #[doc = "Bit 8 - Comparator 0 Event Input Enable"] + #[inline(always)] + pub fn compei0(&mut self) -> COMPEI0_W { + COMPEI0_W { w: self } + } + #[doc = "Bit 9 - Comparator 1 Event Input Enable"] + #[inline(always)] + pub fn compei1(&mut self) -> COMPEI1_W { + COMPEI1_W { w: self } + } + #[doc = "Bit 10 - Comparator 2 Event Input Enable"] + #[inline(always)] + pub fn compei2(&mut self) -> COMPEI2_W { + COMPEI2_W { w: self } + } + #[doc = "Bit 11 - Comparator 3 Event Input Enable"] + #[inline(always)] + pub fn compei3(&mut self) -> COMPEI3_W { + COMPEI3_W { w: self } + } + #[doc = "Bit 12 - Comparator 0 Input Event Invert Enable"] + #[inline(always)] + pub fn invei0(&mut self) -> INVEI0_W { + INVEI0_W { w: self } + } + #[doc = "Bit 13 - Comparator 1 Input Event Invert Enable"] + #[inline(always)] + pub fn invei1(&mut self) -> INVEI1_W { + INVEI1_W { w: self } + } + #[doc = "Bit 14 - Comparator 2 Input Event Invert Enable"] + #[inline(always)] + pub fn invei2(&mut self) -> INVEI2_W { + INVEI2_W { w: self } + } + #[doc = "Bit 15 - Comparator 3 Input Event Invert Enable"] + #[inline(always)] + pub fn invei3(&mut self) -> INVEI3_W { + INVEI3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/ac/intenclr.rs b/pac/atsamc20n/src/ac/intenclr.rs new file mode 100644 index 000000000000..e948bee83d3f --- /dev/null +++ b/pac/atsamc20n/src/ac/intenclr.rs @@ -0,0 +1,348 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COMP0` reader - Comparator 0 Interrupt Enable"] +pub struct COMP0_R(crate::FieldReader); +impl COMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP0` writer - Comparator 0 Interrupt Enable"] +pub struct COMP0_W<'a> { + w: &'a mut W, +} +impl<'a> COMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `COMP1` reader - Comparator 1 Interrupt Enable"] +pub struct COMP1_R(crate::FieldReader); +impl COMP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP1` writer - Comparator 1 Interrupt Enable"] +pub struct COMP1_W<'a> { + w: &'a mut W, +} +impl<'a> COMP1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `COMP2` reader - Comparator 2 Interrupt Enable"] +pub struct COMP2_R(crate::FieldReader); +impl COMP2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP2` writer - Comparator 2 Interrupt Enable"] +pub struct COMP2_W<'a> { + w: &'a mut W, +} +impl<'a> COMP2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `COMP3` reader - Comparator 3 Interrupt Enable"] +pub struct COMP3_R(crate::FieldReader); +impl COMP3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP3` writer - Comparator 3 Interrupt Enable"] +pub struct COMP3_W<'a> { + w: &'a mut W, +} +impl<'a> COMP3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `WIN0` reader - Window 0 Interrupt Enable"] +pub struct WIN0_R(crate::FieldReader); +impl WIN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WIN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WIN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WIN0` writer - Window 0 Interrupt Enable"] +pub struct WIN0_W<'a> { + w: &'a mut W, +} +impl<'a> WIN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `WIN1` reader - Window 1 Interrupt Enable"] +pub struct WIN1_R(crate::FieldReader); +impl WIN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WIN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WIN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WIN1` writer - Window 1 Interrupt Enable"] +pub struct WIN1_W<'a> { + w: &'a mut W, +} +impl<'a> WIN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Comparator 0 Interrupt Enable"] + #[inline(always)] + pub fn comp0(&self) -> COMP0_R { + COMP0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Comparator 1 Interrupt Enable"] + #[inline(always)] + pub fn comp1(&self) -> COMP1_R { + COMP1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Comparator 2 Interrupt Enable"] + #[inline(always)] + pub fn comp2(&self) -> COMP2_R { + COMP2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Comparator 3 Interrupt Enable"] + #[inline(always)] + pub fn comp3(&self) -> COMP3_R { + COMP3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Window 0 Interrupt Enable"] + #[inline(always)] + pub fn win0(&self) -> WIN0_R { + WIN0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Window 1 Interrupt Enable"] + #[inline(always)] + pub fn win1(&self) -> WIN1_R { + WIN1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Comparator 0 Interrupt Enable"] + #[inline(always)] + pub fn comp0(&mut self) -> COMP0_W { + COMP0_W { w: self } + } + #[doc = "Bit 1 - Comparator 1 Interrupt Enable"] + #[inline(always)] + pub fn comp1(&mut self) -> COMP1_W { + COMP1_W { w: self } + } + #[doc = "Bit 2 - Comparator 2 Interrupt Enable"] + #[inline(always)] + pub fn comp2(&mut self) -> COMP2_W { + COMP2_W { w: self } + } + #[doc = "Bit 3 - Comparator 3 Interrupt Enable"] + #[inline(always)] + pub fn comp3(&mut self) -> COMP3_W { + COMP3_W { w: self } + } + #[doc = "Bit 4 - Window 0 Interrupt Enable"] + #[inline(always)] + pub fn win0(&mut self) -> WIN0_W { + WIN0_W { w: self } + } + #[doc = "Bit 5 - Window 1 Interrupt Enable"] + #[inline(always)] + pub fn win1(&mut self) -> WIN1_W { + WIN1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/ac/intenset.rs b/pac/atsamc20n/src/ac/intenset.rs new file mode 100644 index 000000000000..b631f5136fb6 --- /dev/null +++ b/pac/atsamc20n/src/ac/intenset.rs @@ -0,0 +1,348 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COMP0` reader - Comparator 0 Interrupt Enable"] +pub struct COMP0_R(crate::FieldReader); +impl COMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP0` writer - Comparator 0 Interrupt Enable"] +pub struct COMP0_W<'a> { + w: &'a mut W, +} +impl<'a> COMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `COMP1` reader - Comparator 1 Interrupt Enable"] +pub struct COMP1_R(crate::FieldReader); +impl COMP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP1` writer - Comparator 1 Interrupt Enable"] +pub struct COMP1_W<'a> { + w: &'a mut W, +} +impl<'a> COMP1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `COMP2` reader - Comparator 2 Interrupt Enable"] +pub struct COMP2_R(crate::FieldReader); +impl COMP2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP2` writer - Comparator 2 Interrupt Enable"] +pub struct COMP2_W<'a> { + w: &'a mut W, +} +impl<'a> COMP2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `COMP3` reader - Comparator 3 Interrupt Enable"] +pub struct COMP3_R(crate::FieldReader); +impl COMP3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP3` writer - Comparator 3 Interrupt Enable"] +pub struct COMP3_W<'a> { + w: &'a mut W, +} +impl<'a> COMP3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `WIN0` reader - Window 0 Interrupt Enable"] +pub struct WIN0_R(crate::FieldReader); +impl WIN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WIN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WIN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WIN0` writer - Window 0 Interrupt Enable"] +pub struct WIN0_W<'a> { + w: &'a mut W, +} +impl<'a> WIN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `WIN1` reader - Window 1 Interrupt Enable"] +pub struct WIN1_R(crate::FieldReader); +impl WIN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WIN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WIN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WIN1` writer - Window 1 Interrupt Enable"] +pub struct WIN1_W<'a> { + w: &'a mut W, +} +impl<'a> WIN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Comparator 0 Interrupt Enable"] + #[inline(always)] + pub fn comp0(&self) -> COMP0_R { + COMP0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Comparator 1 Interrupt Enable"] + #[inline(always)] + pub fn comp1(&self) -> COMP1_R { + COMP1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Comparator 2 Interrupt Enable"] + #[inline(always)] + pub fn comp2(&self) -> COMP2_R { + COMP2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Comparator 3 Interrupt Enable"] + #[inline(always)] + pub fn comp3(&self) -> COMP3_R { + COMP3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Window 0 Interrupt Enable"] + #[inline(always)] + pub fn win0(&self) -> WIN0_R { + WIN0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Window 1 Interrupt Enable"] + #[inline(always)] + pub fn win1(&self) -> WIN1_R { + WIN1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Comparator 0 Interrupt Enable"] + #[inline(always)] + pub fn comp0(&mut self) -> COMP0_W { + COMP0_W { w: self } + } + #[doc = "Bit 1 - Comparator 1 Interrupt Enable"] + #[inline(always)] + pub fn comp1(&mut self) -> COMP1_W { + COMP1_W { w: self } + } + #[doc = "Bit 2 - Comparator 2 Interrupt Enable"] + #[inline(always)] + pub fn comp2(&mut self) -> COMP2_W { + COMP2_W { w: self } + } + #[doc = "Bit 3 - Comparator 3 Interrupt Enable"] + #[inline(always)] + pub fn comp3(&mut self) -> COMP3_W { + COMP3_W { w: self } + } + #[doc = "Bit 4 - Window 0 Interrupt Enable"] + #[inline(always)] + pub fn win0(&mut self) -> WIN0_W { + WIN0_W { w: self } + } + #[doc = "Bit 5 - Window 1 Interrupt Enable"] + #[inline(always)] + pub fn win1(&mut self) -> WIN1_W { + WIN1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/ac/intflag.rs b/pac/atsamc20n/src/ac/intflag.rs new file mode 100644 index 000000000000..6557a5e48464 --- /dev/null +++ b/pac/atsamc20n/src/ac/intflag.rs @@ -0,0 +1,348 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COMP0` reader - Comparator 0"] +pub struct COMP0_R(crate::FieldReader); +impl COMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP0` writer - Comparator 0"] +pub struct COMP0_W<'a> { + w: &'a mut W, +} +impl<'a> COMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `COMP1` reader - Comparator 1"] +pub struct COMP1_R(crate::FieldReader); +impl COMP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP1` writer - Comparator 1"] +pub struct COMP1_W<'a> { + w: &'a mut W, +} +impl<'a> COMP1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `COMP2` reader - Comparator 2"] +pub struct COMP2_R(crate::FieldReader); +impl COMP2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP2` writer - Comparator 2"] +pub struct COMP2_W<'a> { + w: &'a mut W, +} +impl<'a> COMP2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `COMP3` reader - Comparator 3"] +pub struct COMP3_R(crate::FieldReader); +impl COMP3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP3` writer - Comparator 3"] +pub struct COMP3_W<'a> { + w: &'a mut W, +} +impl<'a> COMP3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `WIN0` reader - Window 0"] +pub struct WIN0_R(crate::FieldReader); +impl WIN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WIN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WIN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WIN0` writer - Window 0"] +pub struct WIN0_W<'a> { + w: &'a mut W, +} +impl<'a> WIN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `WIN1` reader - Window 1"] +pub struct WIN1_R(crate::FieldReader); +impl WIN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WIN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WIN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WIN1` writer - Window 1"] +pub struct WIN1_W<'a> { + w: &'a mut W, +} +impl<'a> WIN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Comparator 0"] + #[inline(always)] + pub fn comp0(&self) -> COMP0_R { + COMP0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Comparator 1"] + #[inline(always)] + pub fn comp1(&self) -> COMP1_R { + COMP1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Comparator 2"] + #[inline(always)] + pub fn comp2(&self) -> COMP2_R { + COMP2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Comparator 3"] + #[inline(always)] + pub fn comp3(&self) -> COMP3_R { + COMP3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Window 0"] + #[inline(always)] + pub fn win0(&self) -> WIN0_R { + WIN0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Window 1"] + #[inline(always)] + pub fn win1(&self) -> WIN1_R { + WIN1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Comparator 0"] + #[inline(always)] + pub fn comp0(&mut self) -> COMP0_W { + COMP0_W { w: self } + } + #[doc = "Bit 1 - Comparator 1"] + #[inline(always)] + pub fn comp1(&mut self) -> COMP1_W { + COMP1_W { w: self } + } + #[doc = "Bit 2 - Comparator 2"] + #[inline(always)] + pub fn comp2(&mut self) -> COMP2_W { + COMP2_W { w: self } + } + #[doc = "Bit 3 - Comparator 3"] + #[inline(always)] + pub fn comp3(&mut self) -> COMP3_W { + COMP3_W { w: self } + } + #[doc = "Bit 4 - Window 0"] + #[inline(always)] + pub fn win0(&mut self) -> WIN0_W { + WIN0_W { w: self } + } + #[doc = "Bit 5 - Window 1"] + #[inline(always)] + pub fn win1(&mut self) -> WIN1_W { + WIN1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/ac/scaler.rs b/pac/atsamc20n/src/ac/scaler.rs new file mode 100644 index 000000000000..091cacfaeb4b --- /dev/null +++ b/pac/atsamc20n/src/ac/scaler.rs @@ -0,0 +1,104 @@ +#[doc = "Register `SCALER[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SCALER[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `VALUE` reader - Scaler Value"] +pub struct VALUE_R(crate::FieldReader); +impl VALUE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + VALUE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VALUE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VALUE` writer - Scaler Value"] +pub struct VALUE_W<'a> { + w: &'a mut W, +} +impl<'a> VALUE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u8 & 0x3f); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Scaler Value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - Scaler Value"] + #[inline(always)] + pub fn value(&mut self) -> VALUE_W { + VALUE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Scaler n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [scaler](index.html) module"] +pub struct SCALER_SPEC; +impl crate::RegisterSpec for SCALER_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [scaler::R](R) reader structure"] +impl crate::Readable for SCALER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [scaler::W](W) writer structure"] +impl crate::Writable for SCALER_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SCALER[%s] +to value 0"] +impl crate::Resettable for SCALER_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/ac/statusa.rs b/pac/atsamc20n/src/ac/statusa.rs new file mode 100644 index 000000000000..f79619555497 --- /dev/null +++ b/pac/atsamc20n/src/ac/statusa.rs @@ -0,0 +1,237 @@ +#[doc = "Register `STATUSA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `STATE0` reader - Comparator 0 Current State"] +pub struct STATE0_R(crate::FieldReader); +impl STATE0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STATE0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STATE0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STATE1` reader - Comparator 1 Current State"] +pub struct STATE1_R(crate::FieldReader); +impl STATE1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STATE1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STATE1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STATE2` reader - Comparator 2 Current State"] +pub struct STATE2_R(crate::FieldReader); +impl STATE2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STATE2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STATE2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STATE3` reader - Comparator 3 Current State"] +pub struct STATE3_R(crate::FieldReader); +impl STATE3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STATE3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STATE3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Window 0 Current State\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WSTATE0_A { + #[doc = "0: Signal is above window"] + ABOVE = 0, + #[doc = "1: Signal is inside window"] + INSIDE = 1, + #[doc = "2: Signal is below window"] + BELOW = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WSTATE0_A) -> Self { + variant as _ + } +} +#[doc = "Field `WSTATE0` reader - Window 0 Current State"] +pub struct WSTATE0_R(crate::FieldReader); +impl WSTATE0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WSTATE0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(WSTATE0_A::ABOVE), + 1 => Some(WSTATE0_A::INSIDE), + 2 => Some(WSTATE0_A::BELOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `ABOVE`"] + #[inline(always)] + pub fn is_above(&self) -> bool { + **self == WSTATE0_A::ABOVE + } + #[doc = "Checks if the value of the field is `INSIDE`"] + #[inline(always)] + pub fn is_inside(&self) -> bool { + **self == WSTATE0_A::INSIDE + } + #[doc = "Checks if the value of the field is `BELOW`"] + #[inline(always)] + pub fn is_below(&self) -> bool { + **self == WSTATE0_A::BELOW + } +} +impl core::ops::Deref for WSTATE0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Window 1 Current State\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WSTATE1_A { + #[doc = "0: Signal is above window"] + ABOVE = 0, + #[doc = "1: Signal is inside window"] + INSIDE = 1, + #[doc = "2: Signal is below window"] + BELOW = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WSTATE1_A) -> Self { + variant as _ + } +} +#[doc = "Field `WSTATE1` reader - Window 1 Current State"] +pub struct WSTATE1_R(crate::FieldReader); +impl WSTATE1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WSTATE1_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(WSTATE1_A::ABOVE), + 1 => Some(WSTATE1_A::INSIDE), + 2 => Some(WSTATE1_A::BELOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `ABOVE`"] + #[inline(always)] + pub fn is_above(&self) -> bool { + **self == WSTATE1_A::ABOVE + } + #[doc = "Checks if the value of the field is `INSIDE`"] + #[inline(always)] + pub fn is_inside(&self) -> bool { + **self == WSTATE1_A::INSIDE + } + #[doc = "Checks if the value of the field is `BELOW`"] + #[inline(always)] + pub fn is_below(&self) -> bool { + **self == WSTATE1_A::BELOW + } +} +impl core::ops::Deref for WSTATE1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Comparator 0 Current State"] + #[inline(always)] + pub fn state0(&self) -> STATE0_R { + STATE0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Comparator 1 Current State"] + #[inline(always)] + pub fn state1(&self) -> STATE1_R { + STATE1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Comparator 2 Current State"] + #[inline(always)] + pub fn state2(&self) -> STATE2_R { + STATE2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Comparator 3 Current State"] + #[inline(always)] + pub fn state3(&self) -> STATE3_R { + STATE3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bits 4:5 - Window 0 Current State"] + #[inline(always)] + pub fn wstate0(&self) -> WSTATE0_R { + WSTATE0_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bits 6:7 - Window 1 Current State"] + #[inline(always)] + pub fn wstate1(&self) -> WSTATE1_R { + WSTATE1_R::new(((self.bits >> 6) & 0x03) as u8) + } +} +#[doc = "Status A\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [statusa](index.html) module"] +pub struct STATUSA_SPEC; +impl crate::RegisterSpec for STATUSA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [statusa::R](R) reader structure"] +impl crate::Readable for STATUSA_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUSA to value 0"] +impl crate::Resettable for STATUSA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/ac/statusb.rs b/pac/atsamc20n/src/ac/statusb.rs new file mode 100644 index 000000000000..1f7035958bd8 --- /dev/null +++ b/pac/atsamc20n/src/ac/statusb.rs @@ -0,0 +1,113 @@ +#[doc = "Register `STATUSB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `READY0` reader - Comparator 0 Ready"] +pub struct READY0_R(crate::FieldReader); +impl READY0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + READY0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for READY0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `READY1` reader - Comparator 1 Ready"] +pub struct READY1_R(crate::FieldReader); +impl READY1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + READY1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for READY1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `READY2` reader - Comparator 2 Ready"] +pub struct READY2_R(crate::FieldReader); +impl READY2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + READY2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for READY2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `READY3` reader - Comparator 3 Ready"] +pub struct READY3_R(crate::FieldReader); +impl READY3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + READY3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for READY3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Comparator 0 Ready"] + #[inline(always)] + pub fn ready0(&self) -> READY0_R { + READY0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Comparator 1 Ready"] + #[inline(always)] + pub fn ready1(&self) -> READY1_R { + READY1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Comparator 2 Ready"] + #[inline(always)] + pub fn ready2(&self) -> READY2_R { + READY2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Comparator 3 Ready"] + #[inline(always)] + pub fn ready3(&self) -> READY3_R { + READY3_R::new(((self.bits >> 3) & 0x01) != 0) + } +} +#[doc = "Status B\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [statusb](index.html) module"] +pub struct STATUSB_SPEC; +impl crate::RegisterSpec for STATUSB_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [statusb::R](R) reader structure"] +impl crate::Readable for STATUSB_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUSB to value 0"] +impl crate::Resettable for STATUSB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/ac/syncbusy.rs b/pac/atsamc20n/src/ac/syncbusy.rs new file mode 100644 index 000000000000..bbd5b5cbe18f --- /dev/null +++ b/pac/atsamc20n/src/ac/syncbusy.rs @@ -0,0 +1,173 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - Enable Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINCTRL` reader - WINCTRL Synchronization Busy"] +pub struct WINCTRL_R(crate::FieldReader); +impl WINCTRL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINCTRL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINCTRL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPCTRL0` reader - COMPCTRL 0 Synchronization Busy"] +pub struct COMPCTRL0_R(crate::FieldReader); +impl COMPCTRL0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPCTRL0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPCTRL0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPCTRL1` reader - COMPCTRL 1 Synchronization Busy"] +pub struct COMPCTRL1_R(crate::FieldReader); +impl COMPCTRL1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPCTRL1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPCTRL1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPCTRL2` reader - COMPCTRL 2 Synchronization Busy"] +pub struct COMPCTRL2_R(crate::FieldReader); +impl COMPCTRL2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPCTRL2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPCTRL2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPCTRL3` reader - COMPCTRL 3 Synchronization Busy"] +pub struct COMPCTRL3_R(crate::FieldReader); +impl COMPCTRL3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPCTRL3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPCTRL3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - WINCTRL Synchronization Busy"] + #[inline(always)] + pub fn winctrl(&self) -> WINCTRL_R { + WINCTRL_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - COMPCTRL 0 Synchronization Busy"] + #[inline(always)] + pub fn compctrl0(&self) -> COMPCTRL0_R { + COMPCTRL0_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - COMPCTRL 1 Synchronization Busy"] + #[inline(always)] + pub fn compctrl1(&self) -> COMPCTRL1_R { + COMPCTRL1_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - COMPCTRL 2 Synchronization Busy"] + #[inline(always)] + pub fn compctrl2(&self) -> COMPCTRL2_R { + COMPCTRL2_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - COMPCTRL 3 Synchronization Busy"] + #[inline(always)] + pub fn compctrl3(&self) -> COMPCTRL3_R { + COMPCTRL3_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +#[doc = "Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/ac/winctrl.rs b/pac/atsamc20n/src/ac/winctrl.rs new file mode 100644 index 000000000000..e3fe941f07bd --- /dev/null +++ b/pac/atsamc20n/src/ac/winctrl.rs @@ -0,0 +1,384 @@ +#[doc = "Register `WINCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WINCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WEN0` reader - Window 0 Mode Enable"] +pub struct WEN0_R(crate::FieldReader); +impl WEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WEN0` writer - Window 0 Mode Enable"] +pub struct WEN0_W<'a> { + w: &'a mut W, +} +impl<'a> WEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Window 0 Interrupt Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WINTSEL0_A { + #[doc = "0: Interrupt on signal above window"] + ABOVE = 0, + #[doc = "1: Interrupt on signal inside window"] + INSIDE = 1, + #[doc = "2: Interrupt on signal below window"] + BELOW = 2, + #[doc = "3: Interrupt on signal outside window"] + OUTSIDE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WINTSEL0_A) -> Self { + variant as _ + } +} +#[doc = "Field `WINTSEL0` reader - Window 0 Interrupt Selection"] +pub struct WINTSEL0_R(crate::FieldReader); +impl WINTSEL0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WINTSEL0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> WINTSEL0_A { + match self.bits { + 0 => WINTSEL0_A::ABOVE, + 1 => WINTSEL0_A::INSIDE, + 2 => WINTSEL0_A::BELOW, + 3 => WINTSEL0_A::OUTSIDE, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `ABOVE`"] + #[inline(always)] + pub fn is_above(&self) -> bool { + **self == WINTSEL0_A::ABOVE + } + #[doc = "Checks if the value of the field is `INSIDE`"] + #[inline(always)] + pub fn is_inside(&self) -> bool { + **self == WINTSEL0_A::INSIDE + } + #[doc = "Checks if the value of the field is `BELOW`"] + #[inline(always)] + pub fn is_below(&self) -> bool { + **self == WINTSEL0_A::BELOW + } + #[doc = "Checks if the value of the field is `OUTSIDE`"] + #[inline(always)] + pub fn is_outside(&self) -> bool { + **self == WINTSEL0_A::OUTSIDE + } +} +impl core::ops::Deref for WINTSEL0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINTSEL0` writer - Window 0 Interrupt Selection"] +pub struct WINTSEL0_W<'a> { + w: &'a mut W, +} +impl<'a> WINTSEL0_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WINTSEL0_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Interrupt on signal above window"] + #[inline(always)] + pub fn above(self) -> &'a mut W { + self.variant(WINTSEL0_A::ABOVE) + } + #[doc = "Interrupt on signal inside window"] + #[inline(always)] + pub fn inside(self) -> &'a mut W { + self.variant(WINTSEL0_A::INSIDE) + } + #[doc = "Interrupt on signal below window"] + #[inline(always)] + pub fn below(self) -> &'a mut W { + self.variant(WINTSEL0_A::BELOW) + } + #[doc = "Interrupt on signal outside window"] + #[inline(always)] + pub fn outside(self) -> &'a mut W { + self.variant(WINTSEL0_A::OUTSIDE) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 1)) | ((value as u8 & 0x03) << 1); + self.w + } +} +#[doc = "Field `WEN1` reader - Window 1 Mode Enable"] +pub struct WEN1_R(crate::FieldReader); +impl WEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WEN1` writer - Window 1 Mode Enable"] +pub struct WEN1_W<'a> { + w: &'a mut W, +} +impl<'a> WEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Window 1 Interrupt Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WINTSEL1_A { + #[doc = "0: Interrupt on signal above window"] + ABOVE = 0, + #[doc = "1: Interrupt on signal inside window"] + INSIDE = 1, + #[doc = "2: Interrupt on signal below window"] + BELOW = 2, + #[doc = "3: Interrupt on signal outside window"] + OUTSIDE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WINTSEL1_A) -> Self { + variant as _ + } +} +#[doc = "Field `WINTSEL1` reader - Window 1 Interrupt Selection"] +pub struct WINTSEL1_R(crate::FieldReader); +impl WINTSEL1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WINTSEL1_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> WINTSEL1_A { + match self.bits { + 0 => WINTSEL1_A::ABOVE, + 1 => WINTSEL1_A::INSIDE, + 2 => WINTSEL1_A::BELOW, + 3 => WINTSEL1_A::OUTSIDE, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `ABOVE`"] + #[inline(always)] + pub fn is_above(&self) -> bool { + **self == WINTSEL1_A::ABOVE + } + #[doc = "Checks if the value of the field is `INSIDE`"] + #[inline(always)] + pub fn is_inside(&self) -> bool { + **self == WINTSEL1_A::INSIDE + } + #[doc = "Checks if the value of the field is `BELOW`"] + #[inline(always)] + pub fn is_below(&self) -> bool { + **self == WINTSEL1_A::BELOW + } + #[doc = "Checks if the value of the field is `OUTSIDE`"] + #[inline(always)] + pub fn is_outside(&self) -> bool { + **self == WINTSEL1_A::OUTSIDE + } +} +impl core::ops::Deref for WINTSEL1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINTSEL1` writer - Window 1 Interrupt Selection"] +pub struct WINTSEL1_W<'a> { + w: &'a mut W, +} +impl<'a> WINTSEL1_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WINTSEL1_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Interrupt on signal above window"] + #[inline(always)] + pub fn above(self) -> &'a mut W { + self.variant(WINTSEL1_A::ABOVE) + } + #[doc = "Interrupt on signal inside window"] + #[inline(always)] + pub fn inside(self) -> &'a mut W { + self.variant(WINTSEL1_A::INSIDE) + } + #[doc = "Interrupt on signal below window"] + #[inline(always)] + pub fn below(self) -> &'a mut W { + self.variant(WINTSEL1_A::BELOW) + } + #[doc = "Interrupt on signal outside window"] + #[inline(always)] + pub fn outside(self) -> &'a mut W { + self.variant(WINTSEL1_A::OUTSIDE) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 5)) | ((value as u8 & 0x03) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Window 0 Mode Enable"] + #[inline(always)] + pub fn wen0(&self) -> WEN0_R { + WEN0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bits 1:2 - Window 0 Interrupt Selection"] + #[inline(always)] + pub fn wintsel0(&self) -> WINTSEL0_R { + WINTSEL0_R::new(((self.bits >> 1) & 0x03) as u8) + } + #[doc = "Bit 4 - Window 1 Mode Enable"] + #[inline(always)] + pub fn wen1(&self) -> WEN1_R { + WEN1_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bits 5:6 - Window 1 Interrupt Selection"] + #[inline(always)] + pub fn wintsel1(&self) -> WINTSEL1_R { + WINTSEL1_R::new(((self.bits >> 5) & 0x03) as u8) + } +} +impl W { + #[doc = "Bit 0 - Window 0 Mode Enable"] + #[inline(always)] + pub fn wen0(&mut self) -> WEN0_W { + WEN0_W { w: self } + } + #[doc = "Bits 1:2 - Window 0 Interrupt Selection"] + #[inline(always)] + pub fn wintsel0(&mut self) -> WINTSEL0_W { + WINTSEL0_W { w: self } + } + #[doc = "Bit 4 - Window 1 Mode Enable"] + #[inline(always)] + pub fn wen1(&mut self) -> WEN1_W { + WEN1_W { w: self } + } + #[doc = "Bits 5:6 - Window 1 Interrupt Selection"] + #[inline(always)] + pub fn wintsel1(&mut self) -> WINTSEL1_W { + WINTSEL1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Window Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [winctrl](index.html) module"] +pub struct WINCTRL_SPEC; +impl crate::RegisterSpec for WINCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [winctrl::R](R) reader structure"] +impl crate::Readable for WINCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [winctrl::W](W) writer structure"] +impl crate::Writable for WINCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WINCTRL to value 0"] +impl crate::Resettable for WINCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/adc0.rs b/pac/atsamc20n/src/adc0.rs new file mode 100644 index 000000000000..453f56ed28c8 --- /dev/null +++ b/pac/atsamc20n/src/adc0.rs @@ -0,0 +1,141 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + #[doc = "0x01 - Control B"] + pub ctrlb: crate::Reg, + #[doc = "0x02 - Reference Control"] + pub refctrl: crate::Reg, + #[doc = "0x03 - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x04 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x05 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x06 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x07 - Sequence Status"] + pub seqstatus: crate::Reg, + #[doc = "0x08 - Input Control"] + pub inputctrl: crate::Reg, + #[doc = "0x0a - Control C"] + pub ctrlc: crate::Reg, + #[doc = "0x0c - Average Control"] + pub avgctrl: crate::Reg, + #[doc = "0x0d - Sample Time Control"] + pub sampctrl: crate::Reg, + #[doc = "0x0e - Window Monitor Lower Threshold"] + pub winlt: crate::Reg, + #[doc = "0x10 - Window Monitor Upper Threshold"] + pub winut: crate::Reg, + #[doc = "0x12 - Gain Correction"] + pub gaincorr: crate::Reg, + #[doc = "0x14 - Offset Correction"] + pub offsetcorr: crate::Reg, + _reserved16: [u8; 0x02], + #[doc = "0x18 - Software Trigger"] + pub swtrig: crate::Reg, + _reserved17: [u8; 0x03], + #[doc = "0x1c - Debug Control"] + pub dbgctrl: crate::Reg, + _reserved18: [u8; 0x03], + #[doc = "0x20 - Synchronization Busy"] + pub syncbusy: crate::Reg, + _reserved19: [u8; 0x02], + #[doc = "0x24 - Result"] + pub result: crate::Reg, + _reserved20: [u8; 0x02], + #[doc = "0x28 - Sequence Control"] + pub seqctrl: crate::Reg, + #[doc = "0x2c - Calibration"] + pub calib: crate::Reg, +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "Control B"] +pub mod ctrlb; +#[doc = "REFCTRL register accessor: an alias for `Reg`"] +pub type REFCTRL = crate::Reg; +#[doc = "Reference Control"] +pub mod refctrl; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "SEQSTATUS register accessor: an alias for `Reg`"] +pub type SEQSTATUS = crate::Reg; +#[doc = "Sequence Status"] +pub mod seqstatus; +#[doc = "INPUTCTRL register accessor: an alias for `Reg`"] +pub type INPUTCTRL = crate::Reg; +#[doc = "Input Control"] +pub mod inputctrl; +#[doc = "CTRLC register accessor: an alias for `Reg`"] +pub type CTRLC = crate::Reg; +#[doc = "Control C"] +pub mod ctrlc; +#[doc = "AVGCTRL register accessor: an alias for `Reg`"] +pub type AVGCTRL = crate::Reg; +#[doc = "Average Control"] +pub mod avgctrl; +#[doc = "SAMPCTRL register accessor: an alias for `Reg`"] +pub type SAMPCTRL = crate::Reg; +#[doc = "Sample Time Control"] +pub mod sampctrl; +#[doc = "WINLT register accessor: an alias for `Reg`"] +pub type WINLT = crate::Reg; +#[doc = "Window Monitor Lower Threshold"] +pub mod winlt; +#[doc = "WINUT register accessor: an alias for `Reg`"] +pub type WINUT = crate::Reg; +#[doc = "Window Monitor Upper Threshold"] +pub mod winut; +#[doc = "GAINCORR register accessor: an alias for `Reg`"] +pub type GAINCORR = crate::Reg; +#[doc = "Gain Correction"] +pub mod gaincorr; +#[doc = "OFFSETCORR register accessor: an alias for `Reg`"] +pub type OFFSETCORR = crate::Reg; +#[doc = "Offset Correction"] +pub mod offsetcorr; +#[doc = "SWTRIG register accessor: an alias for `Reg`"] +pub type SWTRIG = crate::Reg; +#[doc = "Software Trigger"] +pub mod swtrig; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Busy"] +pub mod syncbusy; +#[doc = "RESULT register accessor: an alias for `Reg`"] +pub type RESULT = crate::Reg; +#[doc = "Result"] +pub mod result; +#[doc = "SEQCTRL register accessor: an alias for `Reg`"] +pub type SEQCTRL = crate::Reg; +#[doc = "Sequence Control"] +pub mod seqctrl; +#[doc = "CALIB register accessor: an alias for `Reg`"] +pub type CALIB = crate::Reg; +#[doc = "Calibration"] +pub mod calib; diff --git a/pac/atsamc20n/src/adc0/avgctrl.rs b/pac/atsamc20n/src/adc0/avgctrl.rs new file mode 100644 index 000000000000..ddb735715c98 --- /dev/null +++ b/pac/atsamc20n/src/adc0/avgctrl.rs @@ -0,0 +1,306 @@ +#[doc = "Register `AVGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `AVGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Number of Samples to be Collected\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SAMPLENUM_A { + #[doc = "0: 1 sample"] + _1 = 0, + #[doc = "1: 2 samples"] + _2 = 1, + #[doc = "2: 4 samples"] + _4 = 2, + #[doc = "3: 8 samples"] + _8 = 3, + #[doc = "4: 16 samples"] + _16 = 4, + #[doc = "5: 32 samples"] + _32 = 5, + #[doc = "6: 64 samples"] + _64 = 6, + #[doc = "7: 128 samples"] + _128 = 7, + #[doc = "8: 256 samples"] + _256 = 8, + #[doc = "9: 512 samples"] + _512 = 9, + #[doc = "10: 1024 samples"] + _1024 = 10, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SAMPLENUM_A) -> Self { + variant as _ + } +} +#[doc = "Field `SAMPLENUM` reader - Number of Samples to be Collected"] +pub struct SAMPLENUM_R(crate::FieldReader); +impl SAMPLENUM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SAMPLENUM_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SAMPLENUM_A::_1), + 1 => Some(SAMPLENUM_A::_2), + 2 => Some(SAMPLENUM_A::_4), + 3 => Some(SAMPLENUM_A::_8), + 4 => Some(SAMPLENUM_A::_16), + 5 => Some(SAMPLENUM_A::_32), + 6 => Some(SAMPLENUM_A::_64), + 7 => Some(SAMPLENUM_A::_128), + 8 => Some(SAMPLENUM_A::_256), + 9 => Some(SAMPLENUM_A::_512), + 10 => Some(SAMPLENUM_A::_1024), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_1`"] + #[inline(always)] + pub fn is_1(&self) -> bool { + **self == SAMPLENUM_A::_1 + } + #[doc = "Checks if the value of the field is `_2`"] + #[inline(always)] + pub fn is_2(&self) -> bool { + **self == SAMPLENUM_A::_2 + } + #[doc = "Checks if the value of the field is `_4`"] + #[inline(always)] + pub fn is_4(&self) -> bool { + **self == SAMPLENUM_A::_4 + } + #[doc = "Checks if the value of the field is `_8`"] + #[inline(always)] + pub fn is_8(&self) -> bool { + **self == SAMPLENUM_A::_8 + } + #[doc = "Checks if the value of the field is `_16`"] + #[inline(always)] + pub fn is_16(&self) -> bool { + **self == SAMPLENUM_A::_16 + } + #[doc = "Checks if the value of the field is `_32`"] + #[inline(always)] + pub fn is_32(&self) -> bool { + **self == SAMPLENUM_A::_32 + } + #[doc = "Checks if the value of the field is `_64`"] + #[inline(always)] + pub fn is_64(&self) -> bool { + **self == SAMPLENUM_A::_64 + } + #[doc = "Checks if the value of the field is `_128`"] + #[inline(always)] + pub fn is_128(&self) -> bool { + **self == SAMPLENUM_A::_128 + } + #[doc = "Checks if the value of the field is `_256`"] + #[inline(always)] + pub fn is_256(&self) -> bool { + **self == SAMPLENUM_A::_256 + } + #[doc = "Checks if the value of the field is `_512`"] + #[inline(always)] + pub fn is_512(&self) -> bool { + **self == SAMPLENUM_A::_512 + } + #[doc = "Checks if the value of the field is `_1024`"] + #[inline(always)] + pub fn is_1024(&self) -> bool { + **self == SAMPLENUM_A::_1024 + } +} +impl core::ops::Deref for SAMPLENUM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SAMPLENUM` writer - Number of Samples to be Collected"] +pub struct SAMPLENUM_W<'a> { + w: &'a mut W, +} +impl<'a> SAMPLENUM_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SAMPLENUM_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "1 sample"] + #[inline(always)] + pub fn _1(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_1) + } + #[doc = "2 samples"] + #[inline(always)] + pub fn _2(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_2) + } + #[doc = "4 samples"] + #[inline(always)] + pub fn _4(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_4) + } + #[doc = "8 samples"] + #[inline(always)] + pub fn _8(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_8) + } + #[doc = "16 samples"] + #[inline(always)] + pub fn _16(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_16) + } + #[doc = "32 samples"] + #[inline(always)] + pub fn _32(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_32) + } + #[doc = "64 samples"] + #[inline(always)] + pub fn _64(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_64) + } + #[doc = "128 samples"] + #[inline(always)] + pub fn _128(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_128) + } + #[doc = "256 samples"] + #[inline(always)] + pub fn _256(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_256) + } + #[doc = "512 samples"] + #[inline(always)] + pub fn _512(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_512) + } + #[doc = "1024 samples"] + #[inline(always)] + pub fn _1024(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +#[doc = "Field `ADJRES` reader - Adjusting Result / Division Coefficient"] +pub struct ADJRES_R(crate::FieldReader); +impl ADJRES_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ADJRES_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADJRES_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADJRES` writer - Adjusting Result / Division Coefficient"] +pub struct ADJRES_W<'a> { + w: &'a mut W, +} +impl<'a> ADJRES_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 4)) | ((value as u8 & 0x07) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Number of Samples to be Collected"] + #[inline(always)] + pub fn samplenum(&self) -> SAMPLENUM_R { + SAMPLENUM_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:6 - Adjusting Result / Division Coefficient"] + #[inline(always)] + pub fn adjres(&self) -> ADJRES_R { + ADJRES_R::new(((self.bits >> 4) & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Number of Samples to be Collected"] + #[inline(always)] + pub fn samplenum(&mut self) -> SAMPLENUM_W { + SAMPLENUM_W { w: self } + } + #[doc = "Bits 4:6 - Adjusting Result / Division Coefficient"] + #[inline(always)] + pub fn adjres(&mut self) -> ADJRES_W { + ADJRES_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Average Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [avgctrl](index.html) module"] +pub struct AVGCTRL_SPEC; +impl crate::RegisterSpec for AVGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [avgctrl::R](R) reader structure"] +impl crate::Readable for AVGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [avgctrl::W](W) writer structure"] +impl crate::Writable for AVGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets AVGCTRL to value 0"] +impl crate::Resettable for AVGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/adc0/calib.rs b/pac/atsamc20n/src/adc0/calib.rs new file mode 100644 index 000000000000..8a1a99b8c47d --- /dev/null +++ b/pac/atsamc20n/src/adc0/calib.rs @@ -0,0 +1,140 @@ +#[doc = "Register `CALIB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CALIB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BIASCOMP` reader - Bias Comparator Scaling"] +pub struct BIASCOMP_R(crate::FieldReader); +impl BIASCOMP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BIASCOMP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BIASCOMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BIASCOMP` writer - Bias Comparator Scaling"] +pub struct BIASCOMP_W<'a> { + w: &'a mut W, +} +impl<'a> BIASCOMP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u16 & 0x07); + self.w + } +} +#[doc = "Field `BIASREFBUF` reader - Bias Reference Buffer Scaling"] +pub struct BIASREFBUF_R(crate::FieldReader); +impl BIASREFBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BIASREFBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BIASREFBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BIASREFBUF` writer - Bias Reference Buffer Scaling"] +pub struct BIASREFBUF_W<'a> { + w: &'a mut W, +} +impl<'a> BIASREFBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u16 & 0x07) << 8); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Bias Comparator Scaling"] + #[inline(always)] + pub fn biascomp(&self) -> BIASCOMP_R { + BIASCOMP_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bits 8:10 - Bias Reference Buffer Scaling"] + #[inline(always)] + pub fn biasrefbuf(&self) -> BIASREFBUF_R { + BIASREFBUF_R::new(((self.bits >> 8) & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Bias Comparator Scaling"] + #[inline(always)] + pub fn biascomp(&mut self) -> BIASCOMP_W { + BIASCOMP_W { w: self } + } + #[doc = "Bits 8:10 - Bias Reference Buffer Scaling"] + #[inline(always)] + pub fn biasrefbuf(&mut self) -> BIASREFBUF_W { + BIASREFBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Calibration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [calib](index.html) module"] +pub struct CALIB_SPEC; +impl crate::RegisterSpec for CALIB_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [calib::R](R) reader structure"] +impl crate::Readable for CALIB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [calib::W](W) writer structure"] +impl crate::Writable for CALIB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CALIB to value 0"] +impl crate::Resettable for CALIB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/adc0/ctrla.rs b/pac/atsamc20n/src/adc0/ctrla.rs new file mode 100644 index 000000000000..47c681045f95 --- /dev/null +++ b/pac/atsamc20n/src/adc0/ctrla.rs @@ -0,0 +1,301 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SLAVEEN` reader - Slave Enable"] +pub struct SLAVEEN_R(crate::FieldReader); +impl SLAVEEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLAVEEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SLAVEEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLAVEEN` writer - Slave Enable"] +pub struct SLAVEEN_W<'a> { + w: &'a mut W, +} +impl<'a> SLAVEEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run During Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run During Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - On Demand Control"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - On Demand Control"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 5 - Slave Enable"] + #[inline(always)] + pub fn slaveen(&self) -> SLAVEEN_R { + SLAVEEN_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Run During Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 5 - Slave Enable"] + #[inline(always)] + pub fn slaveen(&mut self) -> SLAVEEN_W { + SLAVEEN_W { w: self } + } + #[doc = "Bit 6 - Run During Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/adc0/ctrlb.rs b/pac/atsamc20n/src/adc0/ctrlb.rs new file mode 100644 index 000000000000..60dabcbf562e --- /dev/null +++ b/pac/atsamc20n/src/adc0/ctrlb.rs @@ -0,0 +1,230 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Prescaler Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: Peripheral clock divided by 2"] + DIV2 = 0, + #[doc = "1: Peripheral clock divided by 4"] + DIV4 = 1, + #[doc = "2: Peripheral clock divided by 8"] + DIV8 = 2, + #[doc = "3: Peripheral clock divided by 16"] + DIV16 = 3, + #[doc = "4: Peripheral clock divided by 32"] + DIV32 = 4, + #[doc = "5: Peripheral clock divided by 64"] + DIV64 = 5, + #[doc = "6: Peripheral clock divided by 128"] + DIV128 = 6, + #[doc = "7: Peripheral clock divided by 256"] + DIV256 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler Configuration"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PRESCALER_A { + match self.bits { + 0 => PRESCALER_A::DIV2, + 1 => PRESCALER_A::DIV4, + 2 => PRESCALER_A::DIV8, + 3 => PRESCALER_A::DIV16, + 4 => PRESCALER_A::DIV32, + 5 => PRESCALER_A::DIV64, + 6 => PRESCALER_A::DIV128, + 7 => PRESCALER_A::DIV256, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == PRESCALER_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == PRESCALER_A::DIV128 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler Configuration"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Peripheral clock divided by 2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "Peripheral clock divided by 4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "Peripheral clock divided by 8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "Peripheral clock divided by 16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "Peripheral clock divided by 32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV32) + } + #[doc = "Peripheral clock divided by 64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "Peripheral clock divided by 128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV128) + } + #[doc = "Peripheral clock divided by 256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Prescaler Configuration"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Prescaler Configuration"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/adc0/ctrlc.rs b/pac/atsamc20n/src/adc0/ctrlc.rs new file mode 100644 index 000000000000..fa45a771545a --- /dev/null +++ b/pac/atsamc20n/src/adc0/ctrlc.rs @@ -0,0 +1,538 @@ +#[doc = "Register `CTRLC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIFFMODE` reader - Differential Mode"] +pub struct DIFFMODE_R(crate::FieldReader); +impl DIFFMODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIFFMODE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIFFMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIFFMODE` writer - Differential Mode"] +pub struct DIFFMODE_W<'a> { + w: &'a mut W, +} +impl<'a> DIFFMODE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `LEFTADJ` reader - Left-Adjusted Result"] +pub struct LEFTADJ_R(crate::FieldReader); +impl LEFTADJ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LEFTADJ_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LEFTADJ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LEFTADJ` writer - Left-Adjusted Result"] +pub struct LEFTADJ_W<'a> { + w: &'a mut W, +} +impl<'a> LEFTADJ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `FREERUN` reader - Free Running Mode"] +pub struct FREERUN_R(crate::FieldReader); +impl FREERUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FREERUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FREERUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FREERUN` writer - Free Running Mode"] +pub struct FREERUN_W<'a> { + w: &'a mut W, +} +impl<'a> FREERUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CORREN` reader - Digital Correction Logic Enable"] +pub struct CORREN_R(crate::FieldReader); +impl CORREN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CORREN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CORREN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CORREN` writer - Digital Correction Logic Enable"] +pub struct CORREN_W<'a> { + w: &'a mut W, +} +impl<'a> CORREN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Conversion Result Resolution\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum RESSEL_A { + #[doc = "0: 12-bit"] + _12BIT = 0, + #[doc = "1: 16-bit averaging mode"] + _16BIT = 1, + #[doc = "2: 10-bit"] + _10BIT = 2, + #[doc = "3: 8-bit"] + _8BIT = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RESSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `RESSEL` reader - Conversion Result Resolution"] +pub struct RESSEL_R(crate::FieldReader); +impl RESSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RESSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RESSEL_A { + match self.bits { + 0 => RESSEL_A::_12BIT, + 1 => RESSEL_A::_16BIT, + 2 => RESSEL_A::_10BIT, + 3 => RESSEL_A::_8BIT, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `_12BIT`"] + #[inline(always)] + pub fn is_12bit(&self) -> bool { + **self == RESSEL_A::_12BIT + } + #[doc = "Checks if the value of the field is `_16BIT`"] + #[inline(always)] + pub fn is_16bit(&self) -> bool { + **self == RESSEL_A::_16BIT + } + #[doc = "Checks if the value of the field is `_10BIT`"] + #[inline(always)] + pub fn is_10bit(&self) -> bool { + **self == RESSEL_A::_10BIT + } + #[doc = "Checks if the value of the field is `_8BIT`"] + #[inline(always)] + pub fn is_8bit(&self) -> bool { + **self == RESSEL_A::_8BIT + } +} +impl core::ops::Deref for RESSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESSEL` writer - Conversion Result Resolution"] +pub struct RESSEL_W<'a> { + w: &'a mut W, +} +impl<'a> RESSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RESSEL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "12-bit"] + #[inline(always)] + pub fn _12bit(self) -> &'a mut W { + self.variant(RESSEL_A::_12BIT) + } + #[doc = "16-bit averaging mode"] + #[inline(always)] + pub fn _16bit(self) -> &'a mut W { + self.variant(RESSEL_A::_16BIT) + } + #[doc = "10-bit"] + #[inline(always)] + pub fn _10bit(self) -> &'a mut W { + self.variant(RESSEL_A::_10BIT) + } + #[doc = "8-bit"] + #[inline(always)] + pub fn _8bit(self) -> &'a mut W { + self.variant(RESSEL_A::_8BIT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u16 & 0x03) << 4); + self.w + } +} +#[doc = "Field `R2R` reader - Rail-to-Rail mode enable"] +pub struct R2R_R(crate::FieldReader); +impl R2R_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + R2R_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for R2R_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `R2R` writer - Rail-to-Rail mode enable"] +pub struct R2R_W<'a> { + w: &'a mut W, +} +impl<'a> R2R_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Window Monitor Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WINMODE_A { + #[doc = "0: No window mode (default)"] + DISABLE = 0, + #[doc = "1: RESULT > WINLT"] + MODE1 = 1, + #[doc = "2: RESULT < WINUT"] + MODE2 = 2, + #[doc = "3: WINLT < RESULT < WINUT"] + MODE3 = 3, + #[doc = "4: !(WINLT < RESULT < WINUT)"] + MODE4 = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WINMODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `WINMODE` reader - Window Monitor Mode"] +pub struct WINMODE_R(crate::FieldReader); +impl WINMODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WINMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(WINMODE_A::DISABLE), + 1 => Some(WINMODE_A::MODE1), + 2 => Some(WINMODE_A::MODE2), + 3 => Some(WINMODE_A::MODE3), + 4 => Some(WINMODE_A::MODE4), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == WINMODE_A::DISABLE + } + #[doc = "Checks if the value of the field is `MODE1`"] + #[inline(always)] + pub fn is_mode1(&self) -> bool { + **self == WINMODE_A::MODE1 + } + #[doc = "Checks if the value of the field is `MODE2`"] + #[inline(always)] + pub fn is_mode2(&self) -> bool { + **self == WINMODE_A::MODE2 + } + #[doc = "Checks if the value of the field is `MODE3`"] + #[inline(always)] + pub fn is_mode3(&self) -> bool { + **self == WINMODE_A::MODE3 + } + #[doc = "Checks if the value of the field is `MODE4`"] + #[inline(always)] + pub fn is_mode4(&self) -> bool { + **self == WINMODE_A::MODE4 + } +} +impl core::ops::Deref for WINMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMODE` writer - Window Monitor Mode"] +pub struct WINMODE_W<'a> { + w: &'a mut W, +} +impl<'a> WINMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WINMODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No window mode (default)"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(WINMODE_A::DISABLE) + } + #[doc = "RESULT > WINLT"] + #[inline(always)] + pub fn mode1(self) -> &'a mut W { + self.variant(WINMODE_A::MODE1) + } + #[doc = "RESULT < WINUT"] + #[inline(always)] + pub fn mode2(self) -> &'a mut W { + self.variant(WINMODE_A::MODE2) + } + #[doc = "WINLT < RESULT < WINUT"] + #[inline(always)] + pub fn mode3(self) -> &'a mut W { + self.variant(WINMODE_A::MODE3) + } + #[doc = "!(WINLT < RESULT < WINUT)"] + #[inline(always)] + pub fn mode4(self) -> &'a mut W { + self.variant(WINMODE_A::MODE4) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u16 & 0x07) << 8); + self.w + } +} +impl R { + #[doc = "Bit 0 - Differential Mode"] + #[inline(always)] + pub fn diffmode(&self) -> DIFFMODE_R { + DIFFMODE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Left-Adjusted Result"] + #[inline(always)] + pub fn leftadj(&self) -> LEFTADJ_R { + LEFTADJ_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Free Running Mode"] + #[inline(always)] + pub fn freerun(&self) -> FREERUN_R { + FREERUN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Digital Correction Logic Enable"] + #[inline(always)] + pub fn corren(&self) -> CORREN_R { + CORREN_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bits 4:5 - Conversion Result Resolution"] + #[inline(always)] + pub fn ressel(&self) -> RESSEL_R { + RESSEL_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bit 7 - Rail-to-Rail mode enable"] + #[inline(always)] + pub fn r2r(&self) -> R2R_R { + R2R_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Window Monitor Mode"] + #[inline(always)] + pub fn winmode(&self) -> WINMODE_R { + WINMODE_R::new(((self.bits >> 8) & 0x07) as u8) + } +} +impl W { + #[doc = "Bit 0 - Differential Mode"] + #[inline(always)] + pub fn diffmode(&mut self) -> DIFFMODE_W { + DIFFMODE_W { w: self } + } + #[doc = "Bit 1 - Left-Adjusted Result"] + #[inline(always)] + pub fn leftadj(&mut self) -> LEFTADJ_W { + LEFTADJ_W { w: self } + } + #[doc = "Bit 2 - Free Running Mode"] + #[inline(always)] + pub fn freerun(&mut self) -> FREERUN_W { + FREERUN_W { w: self } + } + #[doc = "Bit 3 - Digital Correction Logic Enable"] + #[inline(always)] + pub fn corren(&mut self) -> CORREN_W { + CORREN_W { w: self } + } + #[doc = "Bits 4:5 - Conversion Result Resolution"] + #[inline(always)] + pub fn ressel(&mut self) -> RESSEL_W { + RESSEL_W { w: self } + } + #[doc = "Bit 7 - Rail-to-Rail mode enable"] + #[inline(always)] + pub fn r2r(&mut self) -> R2R_W { + R2R_W { w: self } + } + #[doc = "Bits 8:10 - Window Monitor Mode"] + #[inline(always)] + pub fn winmode(&mut self) -> WINMODE_W { + WINMODE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control C\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlc](index.html) module"] +pub struct CTRLC_SPEC; +impl crate::RegisterSpec for CTRLC_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrlc::R](R) reader structure"] +impl crate::Readable for CTRLC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlc::W](W) writer structure"] +impl crate::Writable for CTRLC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLC to value 0"] +impl crate::Resettable for CTRLC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/adc0/dbgctrl.rs b/pac/atsamc20n/src/adc0/dbgctrl.rs new file mode 100644 index 000000000000..53636eb2b339 --- /dev/null +++ b/pac/atsamc20n/src/adc0/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Debug Run"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Debug Run"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/adc0/evctrl.rs b/pac/atsamc20n/src/adc0/evctrl.rs new file mode 100644 index 000000000000..295508f82de3 --- /dev/null +++ b/pac/atsamc20n/src/adc0/evctrl.rs @@ -0,0 +1,348 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FLUSHEI` reader - Flush Event Input Enable"] +pub struct FLUSHEI_R(crate::FieldReader); +impl FLUSHEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FLUSHEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FLUSHEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLUSHEI` writer - Flush Event Input Enable"] +pub struct FLUSHEI_W<'a> { + w: &'a mut W, +} +impl<'a> FLUSHEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `STARTEI` reader - Start Conversion Event Input Enable"] +pub struct STARTEI_R(crate::FieldReader); +impl STARTEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STARTEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STARTEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STARTEI` writer - Start Conversion Event Input Enable"] +pub struct STARTEI_W<'a> { + w: &'a mut W, +} +impl<'a> STARTEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `FLUSHINV` reader - Flush Event Invert Enable"] +pub struct FLUSHINV_R(crate::FieldReader); +impl FLUSHINV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FLUSHINV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FLUSHINV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLUSHINV` writer - Flush Event Invert Enable"] +pub struct FLUSHINV_W<'a> { + w: &'a mut W, +} +impl<'a> FLUSHINV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `STARTINV` reader - Start Event Invert Enable"] +pub struct STARTINV_R(crate::FieldReader); +impl STARTINV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STARTINV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STARTINV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STARTINV` writer - Start Event Invert Enable"] +pub struct STARTINV_W<'a> { + w: &'a mut W, +} +impl<'a> STARTINV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `RESRDYEO` reader - Result Ready Event Out"] +pub struct RESRDYEO_R(crate::FieldReader); +impl RESRDYEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESRDYEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESRDYEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESRDYEO` writer - Result Ready Event Out"] +pub struct RESRDYEO_W<'a> { + w: &'a mut W, +} +impl<'a> RESRDYEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `WINMONEO` reader - Window Monitor Event Out"] +pub struct WINMONEO_R(crate::FieldReader); +impl WINMONEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINMONEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINMONEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMONEO` writer - Window Monitor Event Out"] +pub struct WINMONEO_W<'a> { + w: &'a mut W, +} +impl<'a> WINMONEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Flush Event Input Enable"] + #[inline(always)] + pub fn flushei(&self) -> FLUSHEI_R { + FLUSHEI_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Start Conversion Event Input Enable"] + #[inline(always)] + pub fn startei(&self) -> STARTEI_R { + STARTEI_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Flush Event Invert Enable"] + #[inline(always)] + pub fn flushinv(&self) -> FLUSHINV_R { + FLUSHINV_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Start Event Invert Enable"] + #[inline(always)] + pub fn startinv(&self) -> STARTINV_R { + STARTINV_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Result Ready Event Out"] + #[inline(always)] + pub fn resrdyeo(&self) -> RESRDYEO_R { + RESRDYEO_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Window Monitor Event Out"] + #[inline(always)] + pub fn winmoneo(&self) -> WINMONEO_R { + WINMONEO_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Flush Event Input Enable"] + #[inline(always)] + pub fn flushei(&mut self) -> FLUSHEI_W { + FLUSHEI_W { w: self } + } + #[doc = "Bit 1 - Start Conversion Event Input Enable"] + #[inline(always)] + pub fn startei(&mut self) -> STARTEI_W { + STARTEI_W { w: self } + } + #[doc = "Bit 2 - Flush Event Invert Enable"] + #[inline(always)] + pub fn flushinv(&mut self) -> FLUSHINV_W { + FLUSHINV_W { w: self } + } + #[doc = "Bit 3 - Start Event Invert Enable"] + #[inline(always)] + pub fn startinv(&mut self) -> STARTINV_W { + STARTINV_W { w: self } + } + #[doc = "Bit 4 - Result Ready Event Out"] + #[inline(always)] + pub fn resrdyeo(&mut self) -> RESRDYEO_W { + RESRDYEO_W { w: self } + } + #[doc = "Bit 5 - Window Monitor Event Out"] + #[inline(always)] + pub fn winmoneo(&mut self) -> WINMONEO_W { + WINMONEO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/adc0/gaincorr.rs b/pac/atsamc20n/src/adc0/gaincorr.rs new file mode 100644 index 000000000000..496cb8c6021c --- /dev/null +++ b/pac/atsamc20n/src/adc0/gaincorr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `GAINCORR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GAINCORR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `GAINCORR` reader - Gain Correction Value"] +pub struct GAINCORR_R(crate::FieldReader); +impl GAINCORR_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + GAINCORR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GAINCORR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GAINCORR` writer - Gain Correction Value"] +pub struct GAINCORR_W<'a> { + w: &'a mut W, +} +impl<'a> GAINCORR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0fff) | (value as u16 & 0x0fff); + self.w + } +} +impl R { + #[doc = "Bits 0:11 - Gain Correction Value"] + #[inline(always)] + pub fn gaincorr(&self) -> GAINCORR_R { + GAINCORR_R::new((self.bits & 0x0fff) as u16) + } +} +impl W { + #[doc = "Bits 0:11 - Gain Correction Value"] + #[inline(always)] + pub fn gaincorr(&mut self) -> GAINCORR_W { + GAINCORR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Gain Correction\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gaincorr](index.html) module"] +pub struct GAINCORR_SPEC; +impl crate::RegisterSpec for GAINCORR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [gaincorr::R](R) reader structure"] +impl crate::Readable for GAINCORR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gaincorr::W](W) writer structure"] +impl crate::Writable for GAINCORR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets GAINCORR to value 0"] +impl crate::Resettable for GAINCORR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/adc0/inputctrl.rs b/pac/atsamc20n/src/adc0/inputctrl.rs new file mode 100644 index 000000000000..0c11377f5391 --- /dev/null +++ b/pac/atsamc20n/src/adc0/inputctrl.rs @@ -0,0 +1,485 @@ +#[doc = "Register `INPUTCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INPUTCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Positive Mux Input Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MUXPOS_A { + #[doc = "0: ADC AIN0 Pin"] + AIN0 = 0, + #[doc = "1: ADC AIN1 Pin"] + AIN1 = 1, + #[doc = "2: ADC AIN2 Pin"] + AIN2 = 2, + #[doc = "3: ADC AIN3 Pin"] + AIN3 = 3, + #[doc = "4: ADC AIN4 Pin"] + AIN4 = 4, + #[doc = "5: ADC AIN5 Pin"] + AIN5 = 5, + #[doc = "6: ADC AIN6 Pin"] + AIN6 = 6, + #[doc = "7: ADC AIN7 Pin"] + AIN7 = 7, + #[doc = "8: ADC AIN8 Pin"] + AIN8 = 8, + #[doc = "9: ADC AIN9 Pin"] + AIN9 = 9, + #[doc = "10: ADC AIN10 Pin"] + AIN10 = 10, + #[doc = "11: ADC AIN11 Pin"] + AIN11 = 11, + #[doc = "24: Temperature Sensor"] + TEMP = 24, + #[doc = "25: Bandgap Voltage"] + BANDGAP = 25, + #[doc = "26: 1/4 Scaled Core Supply"] + SCALEDCOREVCC = 26, + #[doc = "27: 1/4 Scaled I/O Supply"] + SCALEDIOVCC = 27, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MUXPOS_A) -> Self { + variant as _ + } +} +#[doc = "Field `MUXPOS` reader - Positive Mux Input Selection"] +pub struct MUXPOS_R(crate::FieldReader); +impl MUXPOS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MUXPOS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MUXPOS_A::AIN0), + 1 => Some(MUXPOS_A::AIN1), + 2 => Some(MUXPOS_A::AIN2), + 3 => Some(MUXPOS_A::AIN3), + 4 => Some(MUXPOS_A::AIN4), + 5 => Some(MUXPOS_A::AIN5), + 6 => Some(MUXPOS_A::AIN6), + 7 => Some(MUXPOS_A::AIN7), + 8 => Some(MUXPOS_A::AIN8), + 9 => Some(MUXPOS_A::AIN9), + 10 => Some(MUXPOS_A::AIN10), + 11 => Some(MUXPOS_A::AIN11), + 24 => Some(MUXPOS_A::TEMP), + 25 => Some(MUXPOS_A::BANDGAP), + 26 => Some(MUXPOS_A::SCALEDCOREVCC), + 27 => Some(MUXPOS_A::SCALEDIOVCC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `AIN0`"] + #[inline(always)] + pub fn is_ain0(&self) -> bool { + **self == MUXPOS_A::AIN0 + } + #[doc = "Checks if the value of the field is `AIN1`"] + #[inline(always)] + pub fn is_ain1(&self) -> bool { + **self == MUXPOS_A::AIN1 + } + #[doc = "Checks if the value of the field is `AIN2`"] + #[inline(always)] + pub fn is_ain2(&self) -> bool { + **self == MUXPOS_A::AIN2 + } + #[doc = "Checks if the value of the field is `AIN3`"] + #[inline(always)] + pub fn is_ain3(&self) -> bool { + **self == MUXPOS_A::AIN3 + } + #[doc = "Checks if the value of the field is `AIN4`"] + #[inline(always)] + pub fn is_ain4(&self) -> bool { + **self == MUXPOS_A::AIN4 + } + #[doc = "Checks if the value of the field is `AIN5`"] + #[inline(always)] + pub fn is_ain5(&self) -> bool { + **self == MUXPOS_A::AIN5 + } + #[doc = "Checks if the value of the field is `AIN6`"] + #[inline(always)] + pub fn is_ain6(&self) -> bool { + **self == MUXPOS_A::AIN6 + } + #[doc = "Checks if the value of the field is `AIN7`"] + #[inline(always)] + pub fn is_ain7(&self) -> bool { + **self == MUXPOS_A::AIN7 + } + #[doc = "Checks if the value of the field is `AIN8`"] + #[inline(always)] + pub fn is_ain8(&self) -> bool { + **self == MUXPOS_A::AIN8 + } + #[doc = "Checks if the value of the field is `AIN9`"] + #[inline(always)] + pub fn is_ain9(&self) -> bool { + **self == MUXPOS_A::AIN9 + } + #[doc = "Checks if the value of the field is `AIN10`"] + #[inline(always)] + pub fn is_ain10(&self) -> bool { + **self == MUXPOS_A::AIN10 + } + #[doc = "Checks if the value of the field is `AIN11`"] + #[inline(always)] + pub fn is_ain11(&self) -> bool { + **self == MUXPOS_A::AIN11 + } + #[doc = "Checks if the value of the field is `TEMP`"] + #[inline(always)] + pub fn is_temp(&self) -> bool { + **self == MUXPOS_A::TEMP + } + #[doc = "Checks if the value of the field is `BANDGAP`"] + #[inline(always)] + pub fn is_bandgap(&self) -> bool { + **self == MUXPOS_A::BANDGAP + } + #[doc = "Checks if the value of the field is `SCALEDCOREVCC`"] + #[inline(always)] + pub fn is_scaledcorevcc(&self) -> bool { + **self == MUXPOS_A::SCALEDCOREVCC + } + #[doc = "Checks if the value of the field is `SCALEDIOVCC`"] + #[inline(always)] + pub fn is_scalediovcc(&self) -> bool { + **self == MUXPOS_A::SCALEDIOVCC + } +} +impl core::ops::Deref for MUXPOS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MUXPOS` writer - Positive Mux Input Selection"] +pub struct MUXPOS_W<'a> { + w: &'a mut W, +} +impl<'a> MUXPOS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MUXPOS_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "ADC AIN0 Pin"] + #[inline(always)] + pub fn ain0(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN0) + } + #[doc = "ADC AIN1 Pin"] + #[inline(always)] + pub fn ain1(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN1) + } + #[doc = "ADC AIN2 Pin"] + #[inline(always)] + pub fn ain2(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN2) + } + #[doc = "ADC AIN3 Pin"] + #[inline(always)] + pub fn ain3(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN3) + } + #[doc = "ADC AIN4 Pin"] + #[inline(always)] + pub fn ain4(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN4) + } + #[doc = "ADC AIN5 Pin"] + #[inline(always)] + pub fn ain5(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN5) + } + #[doc = "ADC AIN6 Pin"] + #[inline(always)] + pub fn ain6(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN6) + } + #[doc = "ADC AIN7 Pin"] + #[inline(always)] + pub fn ain7(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN7) + } + #[doc = "ADC AIN8 Pin"] + #[inline(always)] + pub fn ain8(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN8) + } + #[doc = "ADC AIN9 Pin"] + #[inline(always)] + pub fn ain9(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN9) + } + #[doc = "ADC AIN10 Pin"] + #[inline(always)] + pub fn ain10(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN10) + } + #[doc = "ADC AIN11 Pin"] + #[inline(always)] + pub fn ain11(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN11) + } + #[doc = "Temperature Sensor"] + #[inline(always)] + pub fn temp(self) -> &'a mut W { + self.variant(MUXPOS_A::TEMP) + } + #[doc = "Bandgap Voltage"] + #[inline(always)] + pub fn bandgap(self) -> &'a mut W { + self.variant(MUXPOS_A::BANDGAP) + } + #[doc = "1/4 Scaled Core Supply"] + #[inline(always)] + pub fn scaledcorevcc(self) -> &'a mut W { + self.variant(MUXPOS_A::SCALEDCOREVCC) + } + #[doc = "1/4 Scaled I/O Supply"] + #[inline(always)] + pub fn scalediovcc(self) -> &'a mut W { + self.variant(MUXPOS_A::SCALEDIOVCC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u16 & 0x1f); + self.w + } +} +#[doc = "Negative Mux Input Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MUXNEG_A { + #[doc = "0: ADC AIN0 Pin"] + AIN0 = 0, + #[doc = "1: ADC AIN1 Pin"] + AIN1 = 1, + #[doc = "2: ADC AIN2 Pin"] + AIN2 = 2, + #[doc = "3: ADC AIN3 Pin"] + AIN3 = 3, + #[doc = "4: ADC AIN4 Pin"] + AIN4 = 4, + #[doc = "5: ADC AIN5 Pin"] + AIN5 = 5, + #[doc = "24: Internal Ground"] + GND = 24, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MUXNEG_A) -> Self { + variant as _ + } +} +#[doc = "Field `MUXNEG` reader - Negative Mux Input Selection"] +pub struct MUXNEG_R(crate::FieldReader); +impl MUXNEG_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MUXNEG_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MUXNEG_A::AIN0), + 1 => Some(MUXNEG_A::AIN1), + 2 => Some(MUXNEG_A::AIN2), + 3 => Some(MUXNEG_A::AIN3), + 4 => Some(MUXNEG_A::AIN4), + 5 => Some(MUXNEG_A::AIN5), + 24 => Some(MUXNEG_A::GND), + _ => None, + } + } + #[doc = "Checks if the value of the field is `AIN0`"] + #[inline(always)] + pub fn is_ain0(&self) -> bool { + **self == MUXNEG_A::AIN0 + } + #[doc = "Checks if the value of the field is `AIN1`"] + #[inline(always)] + pub fn is_ain1(&self) -> bool { + **self == MUXNEG_A::AIN1 + } + #[doc = "Checks if the value of the field is `AIN2`"] + #[inline(always)] + pub fn is_ain2(&self) -> bool { + **self == MUXNEG_A::AIN2 + } + #[doc = "Checks if the value of the field is `AIN3`"] + #[inline(always)] + pub fn is_ain3(&self) -> bool { + **self == MUXNEG_A::AIN3 + } + #[doc = "Checks if the value of the field is `AIN4`"] + #[inline(always)] + pub fn is_ain4(&self) -> bool { + **self == MUXNEG_A::AIN4 + } + #[doc = "Checks if the value of the field is `AIN5`"] + #[inline(always)] + pub fn is_ain5(&self) -> bool { + **self == MUXNEG_A::AIN5 + } + #[doc = "Checks if the value of the field is `GND`"] + #[inline(always)] + pub fn is_gnd(&self) -> bool { + **self == MUXNEG_A::GND + } +} +impl core::ops::Deref for MUXNEG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MUXNEG` writer - Negative Mux Input Selection"] +pub struct MUXNEG_W<'a> { + w: &'a mut W, +} +impl<'a> MUXNEG_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MUXNEG_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "ADC AIN0 Pin"] + #[inline(always)] + pub fn ain0(self) -> &'a mut W { + self.variant(MUXNEG_A::AIN0) + } + #[doc = "ADC AIN1 Pin"] + #[inline(always)] + pub fn ain1(self) -> &'a mut W { + self.variant(MUXNEG_A::AIN1) + } + #[doc = "ADC AIN2 Pin"] + #[inline(always)] + pub fn ain2(self) -> &'a mut W { + self.variant(MUXNEG_A::AIN2) + } + #[doc = "ADC AIN3 Pin"] + #[inline(always)] + pub fn ain3(self) -> &'a mut W { + self.variant(MUXNEG_A::AIN3) + } + #[doc = "ADC AIN4 Pin"] + #[inline(always)] + pub fn ain4(self) -> &'a mut W { + self.variant(MUXNEG_A::AIN4) + } + #[doc = "ADC AIN5 Pin"] + #[inline(always)] + pub fn ain5(self) -> &'a mut W { + self.variant(MUXNEG_A::AIN5) + } + #[doc = "Internal Ground"] + #[inline(always)] + pub fn gnd(self) -> &'a mut W { + self.variant(MUXNEG_A::GND) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 8)) | ((value as u16 & 0x1f) << 8); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Positive Mux Input Selection"] + #[inline(always)] + pub fn muxpos(&self) -> MUXPOS_R { + MUXPOS_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 8:12 - Negative Mux Input Selection"] + #[inline(always)] + pub fn muxneg(&self) -> MUXNEG_R { + MUXNEG_R::new(((self.bits >> 8) & 0x1f) as u8) + } +} +impl W { + #[doc = "Bits 0:4 - Positive Mux Input Selection"] + #[inline(always)] + pub fn muxpos(&mut self) -> MUXPOS_W { + MUXPOS_W { w: self } + } + #[doc = "Bits 8:12 - Negative Mux Input Selection"] + #[inline(always)] + pub fn muxneg(&mut self) -> MUXNEG_W { + MUXNEG_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Input Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [inputctrl](index.html) module"] +pub struct INPUTCTRL_SPEC; +impl crate::RegisterSpec for INPUTCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [inputctrl::R](R) reader structure"] +impl crate::Readable for INPUTCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [inputctrl::W](W) writer structure"] +impl crate::Writable for INPUTCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INPUTCTRL to value 0"] +impl crate::Resettable for INPUTCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/adc0/intenclr.rs b/pac/atsamc20n/src/adc0/intenclr.rs new file mode 100644 index 000000000000..b10f428d30b1 --- /dev/null +++ b/pac/atsamc20n/src/adc0/intenclr.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RESRDY` reader - Result Ready Interrupt Disable"] +pub struct RESRDY_R(crate::FieldReader); +impl RESRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESRDY` writer - Result Ready Interrupt Disable"] +pub struct RESRDY_W<'a> { + w: &'a mut W, +} +impl<'a> RESRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `OVERRUN` reader - Overrun Interrupt Disable"] +pub struct OVERRUN_R(crate::FieldReader); +impl OVERRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVERRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVERRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVERRUN` writer - Overrun Interrupt Disable"] +pub struct OVERRUN_W<'a> { + w: &'a mut W, +} +impl<'a> OVERRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WINMON` reader - Window Monitor Interrupt Disable"] +pub struct WINMON_R(crate::FieldReader); +impl WINMON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINMON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINMON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMON` writer - Window Monitor Interrupt Disable"] +pub struct WINMON_W<'a> { + w: &'a mut W, +} +impl<'a> WINMON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Result Ready Interrupt Disable"] + #[inline(always)] + pub fn resrdy(&self) -> RESRDY_R { + RESRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Overrun Interrupt Disable"] + #[inline(always)] + pub fn overrun(&self) -> OVERRUN_R { + OVERRUN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Window Monitor Interrupt Disable"] + #[inline(always)] + pub fn winmon(&self) -> WINMON_R { + WINMON_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Result Ready Interrupt Disable"] + #[inline(always)] + pub fn resrdy(&mut self) -> RESRDY_W { + RESRDY_W { w: self } + } + #[doc = "Bit 1 - Overrun Interrupt Disable"] + #[inline(always)] + pub fn overrun(&mut self) -> OVERRUN_W { + OVERRUN_W { w: self } + } + #[doc = "Bit 2 - Window Monitor Interrupt Disable"] + #[inline(always)] + pub fn winmon(&mut self) -> WINMON_W { + WINMON_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/adc0/intenset.rs b/pac/atsamc20n/src/adc0/intenset.rs new file mode 100644 index 000000000000..5ca93b05b859 --- /dev/null +++ b/pac/atsamc20n/src/adc0/intenset.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RESRDY` reader - Result Ready Interrupt Enable"] +pub struct RESRDY_R(crate::FieldReader); +impl RESRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESRDY` writer - Result Ready Interrupt Enable"] +pub struct RESRDY_W<'a> { + w: &'a mut W, +} +impl<'a> RESRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `OVERRUN` reader - Overrun Interrupt Enable"] +pub struct OVERRUN_R(crate::FieldReader); +impl OVERRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVERRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVERRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVERRUN` writer - Overrun Interrupt Enable"] +pub struct OVERRUN_W<'a> { + w: &'a mut W, +} +impl<'a> OVERRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WINMON` reader - Window Monitor Interrupt Enable"] +pub struct WINMON_R(crate::FieldReader); +impl WINMON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINMON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINMON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMON` writer - Window Monitor Interrupt Enable"] +pub struct WINMON_W<'a> { + w: &'a mut W, +} +impl<'a> WINMON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Result Ready Interrupt Enable"] + #[inline(always)] + pub fn resrdy(&self) -> RESRDY_R { + RESRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Overrun Interrupt Enable"] + #[inline(always)] + pub fn overrun(&self) -> OVERRUN_R { + OVERRUN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Window Monitor Interrupt Enable"] + #[inline(always)] + pub fn winmon(&self) -> WINMON_R { + WINMON_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Result Ready Interrupt Enable"] + #[inline(always)] + pub fn resrdy(&mut self) -> RESRDY_W { + RESRDY_W { w: self } + } + #[doc = "Bit 1 - Overrun Interrupt Enable"] + #[inline(always)] + pub fn overrun(&mut self) -> OVERRUN_W { + OVERRUN_W { w: self } + } + #[doc = "Bit 2 - Window Monitor Interrupt Enable"] + #[inline(always)] + pub fn winmon(&mut self) -> WINMON_W { + WINMON_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/adc0/intflag.rs b/pac/atsamc20n/src/adc0/intflag.rs new file mode 100644 index 000000000000..3cd74788b226 --- /dev/null +++ b/pac/atsamc20n/src/adc0/intflag.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RESRDY` reader - Result Ready Interrupt Flag"] +pub struct RESRDY_R(crate::FieldReader); +impl RESRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESRDY` writer - Result Ready Interrupt Flag"] +pub struct RESRDY_W<'a> { + w: &'a mut W, +} +impl<'a> RESRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `OVERRUN` reader - Overrun Interrupt Flag"] +pub struct OVERRUN_R(crate::FieldReader); +impl OVERRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVERRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVERRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVERRUN` writer - Overrun Interrupt Flag"] +pub struct OVERRUN_W<'a> { + w: &'a mut W, +} +impl<'a> OVERRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WINMON` reader - Window Monitor Interrupt Flag"] +pub struct WINMON_R(crate::FieldReader); +impl WINMON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINMON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINMON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMON` writer - Window Monitor Interrupt Flag"] +pub struct WINMON_W<'a> { + w: &'a mut W, +} +impl<'a> WINMON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Result Ready Interrupt Flag"] + #[inline(always)] + pub fn resrdy(&self) -> RESRDY_R { + RESRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Overrun Interrupt Flag"] + #[inline(always)] + pub fn overrun(&self) -> OVERRUN_R { + OVERRUN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Window Monitor Interrupt Flag"] + #[inline(always)] + pub fn winmon(&self) -> WINMON_R { + WINMON_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Result Ready Interrupt Flag"] + #[inline(always)] + pub fn resrdy(&mut self) -> RESRDY_W { + RESRDY_W { w: self } + } + #[doc = "Bit 1 - Overrun Interrupt Flag"] + #[inline(always)] + pub fn overrun(&mut self) -> OVERRUN_W { + OVERRUN_W { w: self } + } + #[doc = "Bit 2 - Window Monitor Interrupt Flag"] + #[inline(always)] + pub fn winmon(&mut self) -> WINMON_W { + WINMON_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/adc0/offsetcorr.rs b/pac/atsamc20n/src/adc0/offsetcorr.rs new file mode 100644 index 000000000000..24a97427c64e --- /dev/null +++ b/pac/atsamc20n/src/adc0/offsetcorr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `OFFSETCORR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OFFSETCORR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OFFSETCORR` reader - Offset Correction Value"] +pub struct OFFSETCORR_R(crate::FieldReader); +impl OFFSETCORR_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + OFFSETCORR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OFFSETCORR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OFFSETCORR` writer - Offset Correction Value"] +pub struct OFFSETCORR_W<'a> { + w: &'a mut W, +} +impl<'a> OFFSETCORR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0fff) | (value as u16 & 0x0fff); + self.w + } +} +impl R { + #[doc = "Bits 0:11 - Offset Correction Value"] + #[inline(always)] + pub fn offsetcorr(&self) -> OFFSETCORR_R { + OFFSETCORR_R::new((self.bits & 0x0fff) as u16) + } +} +impl W { + #[doc = "Bits 0:11 - Offset Correction Value"] + #[inline(always)] + pub fn offsetcorr(&mut self) -> OFFSETCORR_W { + OFFSETCORR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Offset Correction\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [offsetcorr](index.html) module"] +pub struct OFFSETCORR_SPEC; +impl crate::RegisterSpec for OFFSETCORR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [offsetcorr::R](R) reader structure"] +impl crate::Readable for OFFSETCORR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [offsetcorr::W](W) writer structure"] +impl crate::Writable for OFFSETCORR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OFFSETCORR to value 0"] +impl crate::Resettable for OFFSETCORR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/adc0/refctrl.rs b/pac/atsamc20n/src/adc0/refctrl.rs new file mode 100644 index 000000000000..c21b6532936f --- /dev/null +++ b/pac/atsamc20n/src/adc0/refctrl.rs @@ -0,0 +1,238 @@ +#[doc = "Register `REFCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `REFCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Reference Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum REFSEL_A { + #[doc = "0: Internal Bandgap Reference"] + INTREF = 0, + #[doc = "1: 1/1.6 VDDANA"] + INTVCC0 = 1, + #[doc = "2: 1/2 VDDANA"] + INTVCC1 = 2, + #[doc = "3: External Reference"] + AREFA = 3, + #[doc = "5: VDDANA"] + INTVCC2 = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: REFSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `REFSEL` reader - Reference Selection"] +pub struct REFSEL_R(crate::FieldReader); +impl REFSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REFSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(REFSEL_A::INTREF), + 1 => Some(REFSEL_A::INTVCC0), + 2 => Some(REFSEL_A::INTVCC1), + 3 => Some(REFSEL_A::AREFA), + 5 => Some(REFSEL_A::INTVCC2), + _ => None, + } + } + #[doc = "Checks if the value of the field is `INTREF`"] + #[inline(always)] + pub fn is_intref(&self) -> bool { + **self == REFSEL_A::INTREF + } + #[doc = "Checks if the value of the field is `INTVCC0`"] + #[inline(always)] + pub fn is_intvcc0(&self) -> bool { + **self == REFSEL_A::INTVCC0 + } + #[doc = "Checks if the value of the field is `INTVCC1`"] + #[inline(always)] + pub fn is_intvcc1(&self) -> bool { + **self == REFSEL_A::INTVCC1 + } + #[doc = "Checks if the value of the field is `AREFA`"] + #[inline(always)] + pub fn is_arefa(&self) -> bool { + **self == REFSEL_A::AREFA + } + #[doc = "Checks if the value of the field is `INTVCC2`"] + #[inline(always)] + pub fn is_intvcc2(&self) -> bool { + **self == REFSEL_A::INTVCC2 + } +} +impl core::ops::Deref for REFSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REFSEL` writer - Reference Selection"] +pub struct REFSEL_W<'a> { + w: &'a mut W, +} +impl<'a> REFSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: REFSEL_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Internal Bandgap Reference"] + #[inline(always)] + pub fn intref(self) -> &'a mut W { + self.variant(REFSEL_A::INTREF) + } + #[doc = "1/1.6 VDDANA"] + #[inline(always)] + pub fn intvcc0(self) -> &'a mut W { + self.variant(REFSEL_A::INTVCC0) + } + #[doc = "1/2 VDDANA"] + #[inline(always)] + pub fn intvcc1(self) -> &'a mut W { + self.variant(REFSEL_A::INTVCC1) + } + #[doc = "External Reference"] + #[inline(always)] + pub fn arefa(self) -> &'a mut W { + self.variant(REFSEL_A::AREFA) + } + #[doc = "VDDANA"] + #[inline(always)] + pub fn intvcc2(self) -> &'a mut W { + self.variant(REFSEL_A::INTVCC2) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +#[doc = "Field `REFCOMP` reader - Reference Buffer Offset Compensation Enable"] +pub struct REFCOMP_R(crate::FieldReader); +impl REFCOMP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + REFCOMP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REFCOMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REFCOMP` writer - Reference Buffer Offset Compensation Enable"] +pub struct REFCOMP_W<'a> { + w: &'a mut W, +} +impl<'a> REFCOMP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Reference Selection"] + #[inline(always)] + pub fn refsel(&self) -> REFSEL_R { + REFSEL_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 7 - Reference Buffer Offset Compensation Enable"] + #[inline(always)] + pub fn refcomp(&self) -> REFCOMP_R { + REFCOMP_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Reference Selection"] + #[inline(always)] + pub fn refsel(&mut self) -> REFSEL_W { + REFSEL_W { w: self } + } + #[doc = "Bit 7 - Reference Buffer Offset Compensation Enable"] + #[inline(always)] + pub fn refcomp(&mut self) -> REFCOMP_W { + REFCOMP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Reference Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [refctrl](index.html) module"] +pub struct REFCTRL_SPEC; +impl crate::RegisterSpec for REFCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [refctrl::R](R) reader structure"] +impl crate::Readable for REFCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [refctrl::W](W) writer structure"] +impl crate::Writable for REFCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets REFCTRL to value 0"] +impl crate::Resettable for REFCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/adc0/result.rs b/pac/atsamc20n/src/adc0/result.rs new file mode 100644 index 000000000000..b63b08cc72b9 --- /dev/null +++ b/pac/atsamc20n/src/adc0/result.rs @@ -0,0 +1,53 @@ +#[doc = "Register `RESULT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `RESULT` reader - Result Value"] +pub struct RESULT_R(crate::FieldReader); +impl RESULT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + RESULT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESULT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:15 - Result Value"] + #[inline(always)] + pub fn result(&self) -> RESULT_R { + RESULT_R::new(self.bits as u16) + } +} +#[doc = "Result\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [result](index.html) module"] +pub struct RESULT_SPEC; +impl crate::RegisterSpec for RESULT_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [result::R](R) reader structure"] +impl crate::Readable for RESULT_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets RESULT to value 0"] +impl crate::Resettable for RESULT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/adc0/sampctrl.rs b/pac/atsamc20n/src/adc0/sampctrl.rs new file mode 100644 index 000000000000..be4b77a80410 --- /dev/null +++ b/pac/atsamc20n/src/adc0/sampctrl.rs @@ -0,0 +1,150 @@ +#[doc = "Register `SAMPCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SAMPCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SAMPLEN` reader - Sampling Time Length"] +pub struct SAMPLEN_R(crate::FieldReader); +impl SAMPLEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SAMPLEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SAMPLEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SAMPLEN` writer - Sampling Time Length"] +pub struct SAMPLEN_W<'a> { + w: &'a mut W, +} +impl<'a> SAMPLEN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u8 & 0x3f); + self.w + } +} +#[doc = "Field `OFFCOMP` reader - Comparator Offset Compensation Enable"] +pub struct OFFCOMP_R(crate::FieldReader); +impl OFFCOMP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OFFCOMP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OFFCOMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OFFCOMP` writer - Comparator Offset Compensation Enable"] +pub struct OFFCOMP_W<'a> { + w: &'a mut W, +} +impl<'a> OFFCOMP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Sampling Time Length"] + #[inline(always)] + pub fn samplen(&self) -> SAMPLEN_R { + SAMPLEN_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 7 - Comparator Offset Compensation Enable"] + #[inline(always)] + pub fn offcomp(&self) -> OFFCOMP_R { + OFFCOMP_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:5 - Sampling Time Length"] + #[inline(always)] + pub fn samplen(&mut self) -> SAMPLEN_W { + SAMPLEN_W { w: self } + } + #[doc = "Bit 7 - Comparator Offset Compensation Enable"] + #[inline(always)] + pub fn offcomp(&mut self) -> OFFCOMP_W { + OFFCOMP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Sample Time Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sampctrl](index.html) module"] +pub struct SAMPCTRL_SPEC; +impl crate::RegisterSpec for SAMPCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [sampctrl::R](R) reader structure"] +impl crate::Readable for SAMPCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [sampctrl::W](W) writer structure"] +impl crate::Writable for SAMPCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SAMPCTRL to value 0"] +impl crate::Resettable for SAMPCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/adc0/seqctrl.rs b/pac/atsamc20n/src/adc0/seqctrl.rs new file mode 100644 index 000000000000..c8388c9a393f --- /dev/null +++ b/pac/atsamc20n/src/adc0/seqctrl.rs @@ -0,0 +1,103 @@ +#[doc = "Register `SEQCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SEQCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SEQEN` reader - Enable Positive Input in the Sequence"] +pub struct SEQEN_R(crate::FieldReader); +impl SEQEN_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + SEQEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEQEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEQEN` writer - Enable Positive Input in the Sequence"] +pub struct SEQEN_W<'a> { + w: &'a mut W, +} +impl<'a> SEQEN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Enable Positive Input in the Sequence"] + #[inline(always)] + pub fn seqen(&self) -> SEQEN_R { + SEQEN_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Enable Positive Input in the Sequence"] + #[inline(always)] + pub fn seqen(&mut self) -> SEQEN_W { + SEQEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Sequence Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [seqctrl](index.html) module"] +pub struct SEQCTRL_SPEC; +impl crate::RegisterSpec for SEQCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [seqctrl::R](R) reader structure"] +impl crate::Readable for SEQCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [seqctrl::W](W) writer structure"] +impl crate::Writable for SEQCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SEQCTRL to value 0"] +impl crate::Resettable for SEQCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/adc0/seqstatus.rs b/pac/atsamc20n/src/adc0/seqstatus.rs new file mode 100644 index 000000000000..42c820892e9a --- /dev/null +++ b/pac/atsamc20n/src/adc0/seqstatus.rs @@ -0,0 +1,73 @@ +#[doc = "Register `SEQSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SEQSTATE` reader - Sequence State"] +pub struct SEQSTATE_R(crate::FieldReader); +impl SEQSTATE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SEQSTATE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEQSTATE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEQBUSY` reader - Sequence Busy"] +pub struct SEQBUSY_R(crate::FieldReader); +impl SEQBUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SEQBUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEQBUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:4 - Sequence State"] + #[inline(always)] + pub fn seqstate(&self) -> SEQSTATE_R { + SEQSTATE_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bit 7 - Sequence Busy"] + #[inline(always)] + pub fn seqbusy(&self) -> SEQBUSY_R { + SEQBUSY_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +#[doc = "Sequence Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [seqstatus](index.html) module"] +pub struct SEQSTATUS_SPEC; +impl crate::RegisterSpec for SEQSTATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [seqstatus::R](R) reader structure"] +impl crate::Readable for SEQSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SEQSTATUS to value 0"] +impl crate::Resettable for SEQSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/adc0/swtrig.rs b/pac/atsamc20n/src/adc0/swtrig.rs new file mode 100644 index 000000000000..5e23ed7865ed --- /dev/null +++ b/pac/atsamc20n/src/adc0/swtrig.rs @@ -0,0 +1,160 @@ +#[doc = "Register `SWTRIG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SWTRIG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FLUSH` reader - ADC Flush"] +pub struct FLUSH_R(crate::FieldReader); +impl FLUSH_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FLUSH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FLUSH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLUSH` writer - ADC Flush"] +pub struct FLUSH_W<'a> { + w: &'a mut W, +} +impl<'a> FLUSH_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `START` reader - Start ADC Conversion"] +pub struct START_R(crate::FieldReader); +impl START_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + START_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for START_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `START` writer - Start ADC Conversion"] +pub struct START_W<'a> { + w: &'a mut W, +} +impl<'a> START_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - ADC Flush"] + #[inline(always)] + pub fn flush(&self) -> FLUSH_R { + FLUSH_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Start ADC Conversion"] + #[inline(always)] + pub fn start(&self) -> START_R { + START_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - ADC Flush"] + #[inline(always)] + pub fn flush(&mut self) -> FLUSH_W { + FLUSH_W { w: self } + } + #[doc = "Bit 1 - Start ADC Conversion"] + #[inline(always)] + pub fn start(&mut self) -> START_W { + START_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Software Trigger\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [swtrig](index.html) module"] +pub struct SWTRIG_SPEC; +impl crate::RegisterSpec for SWTRIG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [swtrig::R](R) reader structure"] +impl crate::Readable for SWTRIG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [swtrig::W](W) writer structure"] +impl crate::Writable for SWTRIG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SWTRIG to value 0"] +impl crate::Resettable for SWTRIG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/adc0/syncbusy.rs b/pac/atsamc20n/src/adc0/syncbusy.rs new file mode 100644 index 000000000000..9c92da8a7c74 --- /dev/null +++ b/pac/atsamc20n/src/adc0/syncbusy.rs @@ -0,0 +1,253 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - SWRST Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - ENABLE Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INPUTCTRL` reader - INPUTCTRL Synchronization Busy"] +pub struct INPUTCTRL_R(crate::FieldReader); +impl INPUTCTRL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INPUTCTRL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INPUTCTRL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLC` reader - CTRLC Synchronization Busy"] +pub struct CTRLC_R(crate::FieldReader); +impl CTRLC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AVGCTRL` reader - AVGCTRL Synchronization Busy"] +pub struct AVGCTRL_R(crate::FieldReader); +impl AVGCTRL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AVGCTRL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AVGCTRL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SAMPCTRL` reader - SAMPCTRL Synchronization Busy"] +pub struct SAMPCTRL_R(crate::FieldReader); +impl SAMPCTRL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SAMPCTRL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SAMPCTRL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINLT` reader - WINLT Synchronization Busy"] +pub struct WINLT_R(crate::FieldReader); +impl WINLT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINLT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINLT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINUT` reader - WINUT Synchronization Busy"] +pub struct WINUT_R(crate::FieldReader); +impl WINUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GAINCORR` reader - GAINCORR Synchronization Busy"] +pub struct GAINCORR_R(crate::FieldReader); +impl GAINCORR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GAINCORR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GAINCORR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OFFSETCORR` reader - OFFSETCTRL Synchronization Busy"] +pub struct OFFSETCORR_R(crate::FieldReader); +impl OFFSETCORR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OFFSETCORR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OFFSETCORR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG` reader - SWTRG Synchronization Busy"] +pub struct SWTRIG_R(crate::FieldReader); +impl SWTRIG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - SWRST Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ENABLE Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - INPUTCTRL Synchronization Busy"] + #[inline(always)] + pub fn inputctrl(&self) -> INPUTCTRL_R { + INPUTCTRL_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - CTRLC Synchronization Busy"] + #[inline(always)] + pub fn ctrlc(&self) -> CTRLC_R { + CTRLC_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - AVGCTRL Synchronization Busy"] + #[inline(always)] + pub fn avgctrl(&self) -> AVGCTRL_R { + AVGCTRL_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - SAMPCTRL Synchronization Busy"] + #[inline(always)] + pub fn sampctrl(&self) -> SAMPCTRL_R { + SAMPCTRL_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - WINLT Synchronization Busy"] + #[inline(always)] + pub fn winlt(&self) -> WINLT_R { + WINLT_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - WINUT Synchronization Busy"] + #[inline(always)] + pub fn winut(&self) -> WINUT_R { + WINUT_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - GAINCORR Synchronization Busy"] + #[inline(always)] + pub fn gaincorr(&self) -> GAINCORR_R { + GAINCORR_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - OFFSETCTRL Synchronization Busy"] + #[inline(always)] + pub fn offsetcorr(&self) -> OFFSETCORR_R { + OFFSETCORR_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - SWTRG Synchronization Busy"] + #[inline(always)] + pub fn swtrig(&self) -> SWTRIG_R { + SWTRIG_R::new(((self.bits >> 10) & 0x01) != 0) + } +} +#[doc = "Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/adc0/winlt.rs b/pac/atsamc20n/src/adc0/winlt.rs new file mode 100644 index 000000000000..2a3397684767 --- /dev/null +++ b/pac/atsamc20n/src/adc0/winlt.rs @@ -0,0 +1,103 @@ +#[doc = "Register `WINLT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WINLT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WINLT` reader - Window Lower Threshold"] +pub struct WINLT_R(crate::FieldReader); +impl WINLT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + WINLT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINLT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINLT` writer - Window Lower Threshold"] +pub struct WINLT_W<'a> { + w: &'a mut W, +} +impl<'a> WINLT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Window Lower Threshold"] + #[inline(always)] + pub fn winlt(&self) -> WINLT_R { + WINLT_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Window Lower Threshold"] + #[inline(always)] + pub fn winlt(&mut self) -> WINLT_W { + WINLT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Window Monitor Lower Threshold\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [winlt](index.html) module"] +pub struct WINLT_SPEC; +impl crate::RegisterSpec for WINLT_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [winlt::R](R) reader structure"] +impl crate::Readable for WINLT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [winlt::W](W) writer structure"] +impl crate::Writable for WINLT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WINLT to value 0"] +impl crate::Resettable for WINLT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/adc0/winut.rs b/pac/atsamc20n/src/adc0/winut.rs new file mode 100644 index 000000000000..0ea123174937 --- /dev/null +++ b/pac/atsamc20n/src/adc0/winut.rs @@ -0,0 +1,103 @@ +#[doc = "Register `WINUT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WINUT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WINUT` reader - Window Upper Threshold"] +pub struct WINUT_R(crate::FieldReader); +impl WINUT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + WINUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINUT` writer - Window Upper Threshold"] +pub struct WINUT_W<'a> { + w: &'a mut W, +} +impl<'a> WINUT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Window Upper Threshold"] + #[inline(always)] + pub fn winut(&self) -> WINUT_R { + WINUT_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Window Upper Threshold"] + #[inline(always)] + pub fn winut(&mut self) -> WINUT_W { + WINUT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Window Monitor Upper Threshold\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [winut](index.html) module"] +pub struct WINUT_SPEC; +impl crate::RegisterSpec for WINUT_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [winut::R](R) reader structure"] +impl crate::Readable for WINUT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [winut::W](W) writer structure"] +impl crate::Writable for WINUT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WINUT to value 0"] +impl crate::Resettable for WINUT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/ccl.rs b/pac/atsamc20n/src/ccl.rs new file mode 100644 index 000000000000..30b1f41639c1 --- /dev/null +++ b/pac/atsamc20n/src/ccl.rs @@ -0,0 +1,24 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrl: crate::Reg, + _reserved1: [u8; 0x03], + #[doc = "0x04 - SEQ Control x"] + pub seqctrl: [crate::Reg; 2], + _reserved2: [u8; 0x02], + #[doc = "0x08..0x18 - LUT Control x"] + pub lutctrl: [crate::Reg; 4], +} +#[doc = "CTRL register accessor: an alias for `Reg`"] +pub type CTRL = crate::Reg; +#[doc = "Control"] +pub mod ctrl; +#[doc = "SEQCTRL register accessor: an alias for `Reg`"] +pub type SEQCTRL = crate::Reg; +#[doc = "SEQ Control x"] +pub mod seqctrl; +#[doc = "LUTCTRL register accessor: an alias for `Reg`"] +pub type LUTCTRL = crate::Reg; +#[doc = "LUT Control x"] +pub mod lutctrl; diff --git a/pac/atsamc20n/src/ccl/ctrl.rs b/pac/atsamc20n/src/ccl/ctrl.rs new file mode 100644 index 000000000000..5e515fe037ca --- /dev/null +++ b/pac/atsamc20n/src/ccl/ctrl.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"] +pub struct CTRL_SPEC; +impl crate::RegisterSpec for CTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrl::R](R) reader structure"] +impl crate::Readable for CTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"] +impl crate::Writable for CTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/ccl/lutctrl.rs b/pac/atsamc20n/src/ccl/lutctrl.rs new file mode 100644 index 000000000000..e1f8d4e05482 --- /dev/null +++ b/pac/atsamc20n/src/ccl/lutctrl.rs @@ -0,0 +1,728 @@ +#[doc = "Register `LUTCTRL[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `LUTCTRL[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - LUT Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - LUT Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Filter Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FILTSEL_A { + #[doc = "0: Filter disabled"] + DISABLE = 0, + #[doc = "1: Synchronizer enabled"] + SYNCH = 1, + #[doc = "2: Filter enabled"] + FILTER = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FILTSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `FILTSEL` reader - Filter Selection"] +pub struct FILTSEL_R(crate::FieldReader); +impl FILTSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FILTSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(FILTSEL_A::DISABLE), + 1 => Some(FILTSEL_A::SYNCH), + 2 => Some(FILTSEL_A::FILTER), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == FILTSEL_A::DISABLE + } + #[doc = "Checks if the value of the field is `SYNCH`"] + #[inline(always)] + pub fn is_synch(&self) -> bool { + **self == FILTSEL_A::SYNCH + } + #[doc = "Checks if the value of the field is `FILTER`"] + #[inline(always)] + pub fn is_filter(&self) -> bool { + **self == FILTSEL_A::FILTER + } +} +impl core::ops::Deref for FILTSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTSEL` writer - Filter Selection"] +pub struct FILTSEL_W<'a> { + w: &'a mut W, +} +impl<'a> FILTSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FILTSEL_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Filter disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(FILTSEL_A::DISABLE) + } + #[doc = "Synchronizer enabled"] + #[inline(always)] + pub fn synch(self) -> &'a mut W { + self.variant(FILTSEL_A::SYNCH) + } + #[doc = "Filter enabled"] + #[inline(always)] + pub fn filter(self) -> &'a mut W { + self.variant(FILTSEL_A::FILTER) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u32 & 0x03) << 4); + self.w + } +} +#[doc = "Field `EDGESEL` reader - Edge Selection"] +pub struct EDGESEL_R(crate::FieldReader); +impl EDGESEL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EDGESEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EDGESEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EDGESEL` writer - Edge Selection"] +pub struct EDGESEL_W<'a> { + w: &'a mut W, +} +impl<'a> EDGESEL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Input Selection 0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum INSEL0_A { + #[doc = "0: Masked input"] + MASK = 0, + #[doc = "1: Feedback input source"] + FEEDBACK = 1, + #[doc = "2: Linked LUT input source"] + LINK = 2, + #[doc = "3: Event in put source"] + EVENT = 3, + #[doc = "4: I/O pin input source"] + IO = 4, + #[doc = "5: AC input source"] + AC = 5, + #[doc = "6: TC input source"] + TC = 6, + #[doc = "7: Alternate TC input source"] + ALTTC = 7, + #[doc = "8: TCC input source"] + TCC = 8, + #[doc = "9: SERCOM inout source"] + SERCOM = 9, + #[doc = "10: Alternate 2 TC input source"] + ALT2TC = 10, + #[doc = "11: ASYNC EVENT input source. The EVENT input will bypass edge detection logic."] + ASYNCEVENT = 11, +} +impl From for u8 { + #[inline(always)] + fn from(variant: INSEL0_A) -> Self { + variant as _ + } +} +#[doc = "Field `INSEL0` reader - Input Selection 0"] +pub struct INSEL0_R(crate::FieldReader); +impl INSEL0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + INSEL0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(INSEL0_A::MASK), + 1 => Some(INSEL0_A::FEEDBACK), + 2 => Some(INSEL0_A::LINK), + 3 => Some(INSEL0_A::EVENT), + 4 => Some(INSEL0_A::IO), + 5 => Some(INSEL0_A::AC), + 6 => Some(INSEL0_A::TC), + 7 => Some(INSEL0_A::ALTTC), + 8 => Some(INSEL0_A::TCC), + 9 => Some(INSEL0_A::SERCOM), + 10 => Some(INSEL0_A::ALT2TC), + 11 => Some(INSEL0_A::ASYNCEVENT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `MASK`"] + #[inline(always)] + pub fn is_mask(&self) -> bool { + **self == INSEL0_A::MASK + } + #[doc = "Checks if the value of the field is `FEEDBACK`"] + #[inline(always)] + pub fn is_feedback(&self) -> bool { + **self == INSEL0_A::FEEDBACK + } + #[doc = "Checks if the value of the field is `LINK`"] + #[inline(always)] + pub fn is_link(&self) -> bool { + **self == INSEL0_A::LINK + } + #[doc = "Checks if the value of the field is `EVENT`"] + #[inline(always)] + pub fn is_event(&self) -> bool { + **self == INSEL0_A::EVENT + } + #[doc = "Checks if the value of the field is `IO`"] + #[inline(always)] + pub fn is_io(&self) -> bool { + **self == INSEL0_A::IO + } + #[doc = "Checks if the value of the field is `AC`"] + #[inline(always)] + pub fn is_ac(&self) -> bool { + **self == INSEL0_A::AC + } + #[doc = "Checks if the value of the field is `TC`"] + #[inline(always)] + pub fn is_tc(&self) -> bool { + **self == INSEL0_A::TC + } + #[doc = "Checks if the value of the field is `ALTTC`"] + #[inline(always)] + pub fn is_alttc(&self) -> bool { + **self == INSEL0_A::ALTTC + } + #[doc = "Checks if the value of the field is `TCC`"] + #[inline(always)] + pub fn is_tcc(&self) -> bool { + **self == INSEL0_A::TCC + } + #[doc = "Checks if the value of the field is `SERCOM`"] + #[inline(always)] + pub fn is_sercom(&self) -> bool { + **self == INSEL0_A::SERCOM + } + #[doc = "Checks if the value of the field is `ALT2TC`"] + #[inline(always)] + pub fn is_alt2tc(&self) -> bool { + **self == INSEL0_A::ALT2TC + } + #[doc = "Checks if the value of the field is `ASYNCEVENT`"] + #[inline(always)] + pub fn is_asyncevent(&self) -> bool { + **self == INSEL0_A::ASYNCEVENT + } +} +impl core::ops::Deref for INSEL0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INSEL0` writer - Input Selection 0"] +pub struct INSEL0_W<'a> { + w: &'a mut W, +} +impl<'a> INSEL0_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: INSEL0_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Masked input"] + #[inline(always)] + pub fn mask(self) -> &'a mut W { + self.variant(INSEL0_A::MASK) + } + #[doc = "Feedback input source"] + #[inline(always)] + pub fn feedback(self) -> &'a mut W { + self.variant(INSEL0_A::FEEDBACK) + } + #[doc = "Linked LUT input source"] + #[inline(always)] + pub fn link(self) -> &'a mut W { + self.variant(INSEL0_A::LINK) + } + #[doc = "Event in put source"] + #[inline(always)] + pub fn event(self) -> &'a mut W { + self.variant(INSEL0_A::EVENT) + } + #[doc = "I/O pin input source"] + #[inline(always)] + pub fn io(self) -> &'a mut W { + self.variant(INSEL0_A::IO) + } + #[doc = "AC input source"] + #[inline(always)] + pub fn ac(self) -> &'a mut W { + self.variant(INSEL0_A::AC) + } + #[doc = "TC input source"] + #[inline(always)] + pub fn tc(self) -> &'a mut W { + self.variant(INSEL0_A::TC) + } + #[doc = "Alternate TC input source"] + #[inline(always)] + pub fn alttc(self) -> &'a mut W { + self.variant(INSEL0_A::ALTTC) + } + #[doc = "TCC input source"] + #[inline(always)] + pub fn tcc(self) -> &'a mut W { + self.variant(INSEL0_A::TCC) + } + #[doc = "SERCOM inout source"] + #[inline(always)] + pub fn sercom(self) -> &'a mut W { + self.variant(INSEL0_A::SERCOM) + } + #[doc = "Alternate 2 TC input source"] + #[inline(always)] + pub fn alt2tc(self) -> &'a mut W { + self.variant(INSEL0_A::ALT2TC) + } + #[doc = "ASYNC EVENT input source. The EVENT input will bypass edge detection logic."] + #[inline(always)] + pub fn asyncevent(self) -> &'a mut W { + self.variant(INSEL0_A::ASYNCEVENT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 8)) | ((value as u32 & 0x0f) << 8); + self.w + } +} +#[doc = "Field `INSEL1` reader - Input Selection 1"] +pub struct INSEL1_R(crate::FieldReader); +impl INSEL1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + INSEL1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INSEL1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INSEL1` writer - Input Selection 1"] +pub struct INSEL1_W<'a> { + w: &'a mut W, +} +impl<'a> INSEL1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 12)) | ((value as u32 & 0x0f) << 12); + self.w + } +} +#[doc = "Field `INSEL2` reader - Input Selection 2"] +pub struct INSEL2_R(crate::FieldReader); +impl INSEL2_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + INSEL2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INSEL2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INSEL2` writer - Input Selection 2"] +pub struct INSEL2_W<'a> { + w: &'a mut W, +} +impl<'a> INSEL2_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 16)) | ((value as u32 & 0x0f) << 16); + self.w + } +} +#[doc = "Field `INVEI` reader - Input Event Invert"] +pub struct INVEI_R(crate::FieldReader); +impl INVEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEI` writer - Input Event Invert"] +pub struct INVEI_W<'a> { + w: &'a mut W, +} +impl<'a> INVEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `LUTEI` reader - Event Input Enable"] +pub struct LUTEI_R(crate::FieldReader); +impl LUTEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LUTEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LUTEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LUTEI` writer - Event Input Enable"] +pub struct LUTEI_W<'a> { + w: &'a mut W, +} +impl<'a> LUTEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `LUTEO` reader - Event Output Enable"] +pub struct LUTEO_R(crate::FieldReader); +impl LUTEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LUTEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LUTEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LUTEO` writer - Event Output Enable"] +pub struct LUTEO_W<'a> { + w: &'a mut W, +} +impl<'a> LUTEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `TRUTH` reader - Truth Value"] +pub struct TRUTH_R(crate::FieldReader); +impl TRUTH_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TRUTH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRUTH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRUTH` writer - Truth Value"] +pub struct TRUTH_W<'a> { + w: &'a mut W, +} +impl<'a> TRUTH_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 24)) | ((value as u32 & 0xff) << 24); + self.w + } +} +impl R { + #[doc = "Bit 1 - LUT Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 4:5 - Filter Selection"] + #[inline(always)] + pub fn filtsel(&self) -> FILTSEL_R { + FILTSEL_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bit 7 - Edge Selection"] + #[inline(always)] + pub fn edgesel(&self) -> EDGESEL_R { + EDGESEL_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:11 - Input Selection 0"] + #[inline(always)] + pub fn insel0(&self) -> INSEL0_R { + INSEL0_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - Input Selection 1"] + #[inline(always)] + pub fn insel1(&self) -> INSEL1_R { + INSEL1_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:19 - Input Selection 2"] + #[inline(always)] + pub fn insel2(&self) -> INSEL2_R { + INSEL2_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Input Event Invert"] + #[inline(always)] + pub fn invei(&self) -> INVEI_R { + INVEI_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Event Input Enable"] + #[inline(always)] + pub fn lutei(&self) -> LUTEI_R { + LUTEI_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Event Output Enable"] + #[inline(always)] + pub fn luteo(&self) -> LUTEO_R { + LUTEO_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bits 24:31 - Truth Value"] + #[inline(always)] + pub fn truth(&self) -> TRUTH_R { + TRUTH_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bit 1 - LUT Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 4:5 - Filter Selection"] + #[inline(always)] + pub fn filtsel(&mut self) -> FILTSEL_W { + FILTSEL_W { w: self } + } + #[doc = "Bit 7 - Edge Selection"] + #[inline(always)] + pub fn edgesel(&mut self) -> EDGESEL_W { + EDGESEL_W { w: self } + } + #[doc = "Bits 8:11 - Input Selection 0"] + #[inline(always)] + pub fn insel0(&mut self) -> INSEL0_W { + INSEL0_W { w: self } + } + #[doc = "Bits 12:15 - Input Selection 1"] + #[inline(always)] + pub fn insel1(&mut self) -> INSEL1_W { + INSEL1_W { w: self } + } + #[doc = "Bits 16:19 - Input Selection 2"] + #[inline(always)] + pub fn insel2(&mut self) -> INSEL2_W { + INSEL2_W { w: self } + } + #[doc = "Bit 20 - Input Event Invert"] + #[inline(always)] + pub fn invei(&mut self) -> INVEI_W { + INVEI_W { w: self } + } + #[doc = "Bit 21 - Event Input Enable"] + #[inline(always)] + pub fn lutei(&mut self) -> LUTEI_W { + LUTEI_W { w: self } + } + #[doc = "Bit 22 - Event Output Enable"] + #[inline(always)] + pub fn luteo(&mut self) -> LUTEO_W { + LUTEO_W { w: self } + } + #[doc = "Bits 24:31 - Truth Value"] + #[inline(always)] + pub fn truth(&mut self) -> TRUTH_W { + TRUTH_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "LUT Control x\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lutctrl](index.html) module"] +pub struct LUTCTRL_SPEC; +impl crate::RegisterSpec for LUTCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [lutctrl::R](R) reader structure"] +impl crate::Readable for LUTCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [lutctrl::W](W) writer structure"] +impl crate::Writable for LUTCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets LUTCTRL[%s] +to value 0"] +impl crate::Resettable for LUTCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/ccl/seqctrl.rs b/pac/atsamc20n/src/ccl/seqctrl.rs new file mode 100644 index 000000000000..e2597a1042f3 --- /dev/null +++ b/pac/atsamc20n/src/ccl/seqctrl.rs @@ -0,0 +1,192 @@ +#[doc = "Register `SEQCTRL[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SEQCTRL[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Sequential Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SEQSEL_A { + #[doc = "0: Sequential logic is disabled"] + DISABLE = 0, + #[doc = "1: D flip flop"] + DFF = 1, + #[doc = "2: JK flip flop"] + JK = 2, + #[doc = "3: D latch"] + LATCH = 3, + #[doc = "4: RS latch"] + RS = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEQSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `SEQSEL` reader - Sequential Selection"] +pub struct SEQSEL_R(crate::FieldReader); +impl SEQSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SEQSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEQSEL_A::DISABLE), + 1 => Some(SEQSEL_A::DFF), + 2 => Some(SEQSEL_A::JK), + 3 => Some(SEQSEL_A::LATCH), + 4 => Some(SEQSEL_A::RS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == SEQSEL_A::DISABLE + } + #[doc = "Checks if the value of the field is `DFF`"] + #[inline(always)] + pub fn is_dff(&self) -> bool { + **self == SEQSEL_A::DFF + } + #[doc = "Checks if the value of the field is `JK`"] + #[inline(always)] + pub fn is_jk(&self) -> bool { + **self == SEQSEL_A::JK + } + #[doc = "Checks if the value of the field is `LATCH`"] + #[inline(always)] + pub fn is_latch(&self) -> bool { + **self == SEQSEL_A::LATCH + } + #[doc = "Checks if the value of the field is `RS`"] + #[inline(always)] + pub fn is_rs(&self) -> bool { + **self == SEQSEL_A::RS + } +} +impl core::ops::Deref for SEQSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEQSEL` writer - Sequential Selection"] +pub struct SEQSEL_W<'a> { + w: &'a mut W, +} +impl<'a> SEQSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SEQSEL_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Sequential logic is disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(SEQSEL_A::DISABLE) + } + #[doc = "D flip flop"] + #[inline(always)] + pub fn dff(self) -> &'a mut W { + self.variant(SEQSEL_A::DFF) + } + #[doc = "JK flip flop"] + #[inline(always)] + pub fn jk(self) -> &'a mut W { + self.variant(SEQSEL_A::JK) + } + #[doc = "D latch"] + #[inline(always)] + pub fn latch(self) -> &'a mut W { + self.variant(SEQSEL_A::LATCH) + } + #[doc = "RS latch"] + #[inline(always)] + pub fn rs(self) -> &'a mut W { + self.variant(SEQSEL_A::RS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Sequential Selection"] + #[inline(always)] + pub fn seqsel(&self) -> SEQSEL_R { + SEQSEL_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Sequential Selection"] + #[inline(always)] + pub fn seqsel(&mut self) -> SEQSEL_W { + SEQSEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SEQ Control x\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [seqctrl](index.html) module"] +pub struct SEQCTRL_SPEC; +impl crate::RegisterSpec for SEQCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [seqctrl::R](R) reader structure"] +impl crate::Readable for SEQCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [seqctrl::W](W) writer structure"] +impl crate::Writable for SEQCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SEQCTRL[%s] +to value 0"] +impl crate::Resettable for SEQCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/divas.rs b/pac/atsamc20n/src/divas.rs new file mode 100644 index 000000000000..dbc2f5f226da --- /dev/null +++ b/pac/atsamc20n/src/divas.rs @@ -0,0 +1,48 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrla: crate::Reg, + _reserved1: [u8; 0x03], + #[doc = "0x04 - Status"] + pub status: crate::Reg, + _reserved2: [u8; 0x03], + #[doc = "0x08 - Dividend"] + pub dividend: crate::Reg, + #[doc = "0x0c - Divisor"] + pub divisor: crate::Reg, + #[doc = "0x10 - Result"] + pub result: crate::Reg, + #[doc = "0x14 - Remainder"] + pub rem: crate::Reg, + #[doc = "0x18 - Square Root Input"] + pub sqrnum: crate::Reg, +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control"] +pub mod ctrla; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "DIVIDEND register accessor: an alias for `Reg`"] +pub type DIVIDEND = crate::Reg; +#[doc = "Dividend"] +pub mod dividend; +#[doc = "DIVISOR register accessor: an alias for `Reg`"] +pub type DIVISOR = crate::Reg; +#[doc = "Divisor"] +pub mod divisor; +#[doc = "RESULT register accessor: an alias for `Reg`"] +pub type RESULT = crate::Reg; +#[doc = "Result"] +pub mod result; +#[doc = "REM register accessor: an alias for `Reg`"] +pub type REM = crate::Reg; +#[doc = "Remainder"] +pub mod rem; +#[doc = "SQRNUM register accessor: an alias for `Reg`"] +pub type SQRNUM = crate::Reg; +#[doc = "Square Root Input"] +pub mod sqrnum; diff --git a/pac/atsamc20n/src/divas/ctrla.rs b/pac/atsamc20n/src/divas/ctrla.rs new file mode 100644 index 000000000000..7f79349da05c --- /dev/null +++ b/pac/atsamc20n/src/divas/ctrla.rs @@ -0,0 +1,160 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SIGNED` reader - Signed"] +pub struct SIGNED_R(crate::FieldReader); +impl SIGNED_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SIGNED_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SIGNED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SIGNED` writer - Signed"] +pub struct SIGNED_W<'a> { + w: &'a mut W, +} +impl<'a> SIGNED_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `DLZ` reader - Disable Leading Zero Optimization"] +pub struct DLZ_R(crate::FieldReader); +impl DLZ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DLZ_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DLZ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DLZ` writer - Disable Leading Zero Optimization"] +pub struct DLZ_W<'a> { + w: &'a mut W, +} +impl<'a> DLZ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - Signed"] + #[inline(always)] + pub fn signed(&self) -> SIGNED_R { + SIGNED_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Disable Leading Zero Optimization"] + #[inline(always)] + pub fn dlz(&self) -> DLZ_R { + DLZ_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Signed"] + #[inline(always)] + pub fn signed(&mut self) -> SIGNED_W { + SIGNED_W { w: self } + } + #[doc = "Bit 1 - Disable Leading Zero Optimization"] + #[inline(always)] + pub fn dlz(&mut self) -> DLZ_W { + DLZ_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/divas/dividend.rs b/pac/atsamc20n/src/divas/dividend.rs new file mode 100644 index 000000000000..215f44261a6c --- /dev/null +++ b/pac/atsamc20n/src/divas/dividend.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DIVIDEND` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIVIDEND` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIVIDEND` reader - DIVIDEND"] +pub struct DIVIDEND_R(crate::FieldReader); +impl DIVIDEND_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + DIVIDEND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIVIDEND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIVIDEND` writer - DIVIDEND"] +pub struct DIVIDEND_W<'a> { + w: &'a mut W, +} +impl<'a> DIVIDEND_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - DIVIDEND"] + #[inline(always)] + pub fn dividend(&self) -> DIVIDEND_R { + DIVIDEND_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - DIVIDEND"] + #[inline(always)] + pub fn dividend(&mut self) -> DIVIDEND_W { + DIVIDEND_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Dividend\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dividend](index.html) module"] +pub struct DIVIDEND_SPEC; +impl crate::RegisterSpec for DIVIDEND_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dividend::R](R) reader structure"] +impl crate::Readable for DIVIDEND_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dividend::W](W) writer structure"] +impl crate::Writable for DIVIDEND_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DIVIDEND to value 0"] +impl crate::Resettable for DIVIDEND_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/divas/divisor.rs b/pac/atsamc20n/src/divas/divisor.rs new file mode 100644 index 000000000000..b711870a5cd6 --- /dev/null +++ b/pac/atsamc20n/src/divas/divisor.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DIVISOR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIVISOR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIVISOR` reader - DIVISOR"] +pub struct DIVISOR_R(crate::FieldReader); +impl DIVISOR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + DIVISOR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIVISOR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIVISOR` writer - DIVISOR"] +pub struct DIVISOR_W<'a> { + w: &'a mut W, +} +impl<'a> DIVISOR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - DIVISOR"] + #[inline(always)] + pub fn divisor(&self) -> DIVISOR_R { + DIVISOR_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - DIVISOR"] + #[inline(always)] + pub fn divisor(&mut self) -> DIVISOR_W { + DIVISOR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Divisor\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [divisor](index.html) module"] +pub struct DIVISOR_SPEC; +impl crate::RegisterSpec for DIVISOR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [divisor::R](R) reader structure"] +impl crate::Readable for DIVISOR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [divisor::W](W) writer structure"] +impl crate::Writable for DIVISOR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DIVISOR to value 0"] +impl crate::Resettable for DIVISOR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/divas/rem.rs b/pac/atsamc20n/src/divas/rem.rs new file mode 100644 index 000000000000..76f3a90878ed --- /dev/null +++ b/pac/atsamc20n/src/divas/rem.rs @@ -0,0 +1,53 @@ +#[doc = "Register `REM` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `REM` reader - REM"] +pub struct REM_R(crate::FieldReader); +impl REM_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + REM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - REM"] + #[inline(always)] + pub fn rem(&self) -> REM_R { + REM_R::new(self.bits as u32) + } +} +#[doc = "Remainder\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rem](index.html) module"] +pub struct REM_SPEC; +impl crate::RegisterSpec for REM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rem::R](R) reader structure"] +impl crate::Readable for REM_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets REM to value 0"] +impl crate::Resettable for REM_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/divas/result.rs b/pac/atsamc20n/src/divas/result.rs new file mode 100644 index 000000000000..85fc1a025f9e --- /dev/null +++ b/pac/atsamc20n/src/divas/result.rs @@ -0,0 +1,53 @@ +#[doc = "Register `RESULT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `RESULT` reader - RESULT"] +pub struct RESULT_R(crate::FieldReader); +impl RESULT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + RESULT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESULT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - RESULT"] + #[inline(always)] + pub fn result(&self) -> RESULT_R { + RESULT_R::new(self.bits as u32) + } +} +#[doc = "Result\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [result](index.html) module"] +pub struct RESULT_SPEC; +impl crate::RegisterSpec for RESULT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [result::R](R) reader structure"] +impl crate::Readable for RESULT_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets RESULT to value 0"] +impl crate::Resettable for RESULT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/divas/sqrnum.rs b/pac/atsamc20n/src/divas/sqrnum.rs new file mode 100644 index 000000000000..cc0ce6806beb --- /dev/null +++ b/pac/atsamc20n/src/divas/sqrnum.rs @@ -0,0 +1,103 @@ +#[doc = "Register `SQRNUM` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SQRNUM` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SQRNUM` reader - Square Root Input"] +pub struct SQRNUM_R(crate::FieldReader); +impl SQRNUM_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + SQRNUM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SQRNUM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SQRNUM` writer - Square Root Input"] +pub struct SQRNUM_W<'a> { + w: &'a mut W, +} +impl<'a> SQRNUM_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Square Root Input"] + #[inline(always)] + pub fn sqrnum(&self) -> SQRNUM_R { + SQRNUM_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Square Root Input"] + #[inline(always)] + pub fn sqrnum(&mut self) -> SQRNUM_W { + SQRNUM_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Square Root Input\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sqrnum](index.html) module"] +pub struct SQRNUM_SPEC; +impl crate::RegisterSpec for SQRNUM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [sqrnum::R](R) reader structure"] +impl crate::Readable for SQRNUM_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [sqrnum::W](W) writer structure"] +impl crate::Writable for SQRNUM_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SQRNUM to value 0"] +impl crate::Resettable for SQRNUM_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/divas/status.rs b/pac/atsamc20n/src/divas/status.rs new file mode 100644 index 000000000000..feffbccec659 --- /dev/null +++ b/pac/atsamc20n/src/divas/status.rs @@ -0,0 +1,160 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BUSY` reader - DIVAS Accelerator Busy"] +pub struct BUSY_R(crate::FieldReader); +impl BUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSY` writer - DIVAS Accelerator Busy"] +pub struct BUSY_W<'a> { + w: &'a mut W, +} +impl<'a> BUSY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `DBZ` reader - Writing a one to this bit clears DBZ to zero"] +pub struct DBZ_R(crate::FieldReader); +impl DBZ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBZ_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBZ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBZ` writer - Writing a one to this bit clears DBZ to zero"] +pub struct DBZ_W<'a> { + w: &'a mut W, +} +impl<'a> DBZ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - DIVAS Accelerator Busy"] + #[inline(always)] + pub fn busy(&self) -> BUSY_R { + BUSY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Writing a one to this bit clears DBZ to zero"] + #[inline(always)] + pub fn dbz(&self) -> DBZ_R { + DBZ_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - DIVAS Accelerator Busy"] + #[inline(always)] + pub fn busy(&mut self) -> BUSY_W { + BUSY_W { w: self } + } + #[doc = "Bit 1 - Writing a one to this bit clears DBZ to zero"] + #[inline(always)] + pub fn dbz(&mut self) -> DBZ_W { + DBZ_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/dmac.rs b/pac/atsamc20n/src/dmac.rs new file mode 100644 index 000000000000..c23d36697550 --- /dev/null +++ b/pac/atsamc20n/src/dmac.rs @@ -0,0 +1,148 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrl: crate::Reg, + #[doc = "0x02 - CRC Control"] + pub crcctrl: crate::Reg, + #[doc = "0x04 - CRC Data Input"] + pub crcdatain: crate::Reg, + #[doc = "0x08 - CRC Checksum"] + pub crcchksum: crate::Reg, + #[doc = "0x0c - CRC Status"] + pub crcstatus: crate::Reg, + #[doc = "0x0d - Debug Control"] + pub dbgctrl: crate::Reg, + #[doc = "0x0e - QOS Control"] + pub qosctrl: crate::Reg, + _reserved7: [u8; 0x01], + #[doc = "0x10 - Software Trigger Control"] + pub swtrigctrl: crate::Reg, + #[doc = "0x14 - Priority Control 0"] + pub prictrl0: crate::Reg, + _reserved9: [u8; 0x08], + #[doc = "0x20 - Interrupt Pending"] + pub intpend: crate::Reg, + _reserved10: [u8; 0x02], + #[doc = "0x24 - Interrupt Status"] + pub intstatus: crate::Reg, + #[doc = "0x28 - Busy Channels"] + pub busych: crate::Reg, + #[doc = "0x2c - Pending Channels"] + pub pendch: crate::Reg, + #[doc = "0x30 - Active Channel and Levels"] + pub active: crate::Reg, + #[doc = "0x34 - Descriptor Memory Section Base Address"] + pub baseaddr: crate::Reg, + #[doc = "0x38 - Write-Back Memory Section Base Address"] + pub wrbaddr: crate::Reg, + _reserved16: [u8; 0x03], + #[doc = "0x3f - Channel ID"] + pub chid: crate::Reg, + #[doc = "0x40 - Channel Control A"] + pub chctrla: crate::Reg, + _reserved18: [u8; 0x03], + #[doc = "0x44 - Channel Control B"] + pub chctrlb: crate::Reg, + _reserved19: [u8; 0x04], + #[doc = "0x4c - Channel Interrupt Enable Clear"] + pub chintenclr: crate::Reg, + #[doc = "0x4d - Channel Interrupt Enable Set"] + pub chintenset: crate::Reg, + #[doc = "0x4e - Channel Interrupt Flag Status and Clear"] + pub chintflag: crate::Reg, + #[doc = "0x4f - Channel Status"] + pub chstatus: crate::Reg, +} +#[doc = "CTRL register accessor: an alias for `Reg`"] +pub type CTRL = crate::Reg; +#[doc = "Control"] +pub mod ctrl; +#[doc = "CRCCTRL register accessor: an alias for `Reg`"] +pub type CRCCTRL = crate::Reg; +#[doc = "CRC Control"] +pub mod crcctrl; +#[doc = "CRCDATAIN register accessor: an alias for `Reg`"] +pub type CRCDATAIN = crate::Reg; +#[doc = "CRC Data Input"] +pub mod crcdatain; +#[doc = "CRCCHKSUM register accessor: an alias for `Reg`"] +pub type CRCCHKSUM = crate::Reg; +#[doc = "CRC Checksum"] +pub mod crcchksum; +#[doc = "CRCSTATUS register accessor: an alias for `Reg`"] +pub type CRCSTATUS = crate::Reg; +#[doc = "CRC Status"] +pub mod crcstatus; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "QOSCTRL register accessor: an alias for `Reg`"] +pub type QOSCTRL = crate::Reg; +#[doc = "QOS Control"] +pub mod qosctrl; +#[doc = "SWTRIGCTRL register accessor: an alias for `Reg`"] +pub type SWTRIGCTRL = crate::Reg; +#[doc = "Software Trigger Control"] +pub mod swtrigctrl; +#[doc = "PRICTRL0 register accessor: an alias for `Reg`"] +pub type PRICTRL0 = crate::Reg; +#[doc = "Priority Control 0"] +pub mod prictrl0; +#[doc = "INTPEND register accessor: an alias for `Reg`"] +pub type INTPEND = crate::Reg; +#[doc = "Interrupt Pending"] +pub mod intpend; +#[doc = "INTSTATUS register accessor: an alias for `Reg`"] +pub type INTSTATUS = crate::Reg; +#[doc = "Interrupt Status"] +pub mod intstatus; +#[doc = "BUSYCH register accessor: an alias for `Reg`"] +pub type BUSYCH = crate::Reg; +#[doc = "Busy Channels"] +pub mod busych; +#[doc = "PENDCH register accessor: an alias for `Reg`"] +pub type PENDCH = crate::Reg; +#[doc = "Pending Channels"] +pub mod pendch; +#[doc = "ACTIVE register accessor: an alias for `Reg`"] +pub type ACTIVE = crate::Reg; +#[doc = "Active Channel and Levels"] +pub mod active; +#[doc = "BASEADDR register accessor: an alias for `Reg`"] +pub type BASEADDR = crate::Reg; +#[doc = "Descriptor Memory Section Base Address"] +pub mod baseaddr; +#[doc = "WRBADDR register accessor: an alias for `Reg`"] +pub type WRBADDR = crate::Reg; +#[doc = "Write-Back Memory Section Base Address"] +pub mod wrbaddr; +#[doc = "CHID register accessor: an alias for `Reg`"] +pub type CHID = crate::Reg; +#[doc = "Channel ID"] +pub mod chid; +#[doc = "CHCTRLA register accessor: an alias for `Reg`"] +pub type CHCTRLA = crate::Reg; +#[doc = "Channel Control A"] +pub mod chctrla; +#[doc = "CHCTRLB register accessor: an alias for `Reg`"] +pub type CHCTRLB = crate::Reg; +#[doc = "Channel Control B"] +pub mod chctrlb; +#[doc = "CHINTENCLR register accessor: an alias for `Reg`"] +pub type CHINTENCLR = crate::Reg; +#[doc = "Channel Interrupt Enable Clear"] +pub mod chintenclr; +#[doc = "CHINTENSET register accessor: an alias for `Reg`"] +pub type CHINTENSET = crate::Reg; +#[doc = "Channel Interrupt Enable Set"] +pub mod chintenset; +#[doc = "CHINTFLAG register accessor: an alias for `Reg`"] +pub type CHINTFLAG = crate::Reg; +#[doc = "Channel Interrupt Flag Status and Clear"] +pub mod chintflag; +#[doc = "CHSTATUS register accessor: an alias for `Reg`"] +pub type CHSTATUS = crate::Reg; +#[doc = "Channel Status"] +pub mod chstatus; diff --git a/pac/atsamc20n/src/dmac/active.rs b/pac/atsamc20n/src/dmac/active.rs new file mode 100644 index 000000000000..c3cc5a0420bc --- /dev/null +++ b/pac/atsamc20n/src/dmac/active.rs @@ -0,0 +1,173 @@ +#[doc = "Register `ACTIVE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `LVLEX0` reader - Level 0 Channel Trigger Request Executing"] +pub struct LVLEX0_R(crate::FieldReader); +impl LVLEX0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LVLEX0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEX0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLEX1` reader - Level 1 Channel Trigger Request Executing"] +pub struct LVLEX1_R(crate::FieldReader); +impl LVLEX1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LVLEX1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEX1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLEX2` reader - Level 2 Channel Trigger Request Executing"] +pub struct LVLEX2_R(crate::FieldReader); +impl LVLEX2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LVLEX2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEX2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLEX3` reader - Level 3 Channel Trigger Request Executing"] +pub struct LVLEX3_R(crate::FieldReader); +impl LVLEX3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LVLEX3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEX3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ID` reader - Active Channel ID"] +pub struct ID_R(crate::FieldReader); +impl ID_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ID_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ID_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ABUSY` reader - Active Channel Busy"] +pub struct ABUSY_R(crate::FieldReader); +impl ABUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ABUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ABUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BTCNT` reader - Active Channel Block Transfer Count"] +pub struct BTCNT_R(crate::FieldReader); +impl BTCNT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BTCNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BTCNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Level 0 Channel Trigger Request Executing"] + #[inline(always)] + pub fn lvlex0(&self) -> LVLEX0_R { + LVLEX0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Level 1 Channel Trigger Request Executing"] + #[inline(always)] + pub fn lvlex1(&self) -> LVLEX1_R { + LVLEX1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Level 2 Channel Trigger Request Executing"] + #[inline(always)] + pub fn lvlex2(&self) -> LVLEX2_R { + LVLEX2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Level 3 Channel Trigger Request Executing"] + #[inline(always)] + pub fn lvlex3(&self) -> LVLEX3_R { + LVLEX3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bits 8:12 - Active Channel ID"] + #[inline(always)] + pub fn id(&self) -> ID_R { + ID_R::new(((self.bits >> 8) & 0x1f) as u8) + } + #[doc = "Bit 15 - Active Channel Busy"] + #[inline(always)] + pub fn abusy(&self) -> ABUSY_R { + ABUSY_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:31 - Active Channel Block Transfer Count"] + #[inline(always)] + pub fn btcnt(&self) -> BTCNT_R { + BTCNT_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[doc = "Active Channel and Levels\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [active](index.html) module"] +pub struct ACTIVE_SPEC; +impl crate::RegisterSpec for ACTIVE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [active::R](R) reader structure"] +impl crate::Readable for ACTIVE_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets ACTIVE to value 0"] +impl crate::Resettable for ACTIVE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/dmac/baseaddr.rs b/pac/atsamc20n/src/dmac/baseaddr.rs new file mode 100644 index 000000000000..cec8c8cf0777 --- /dev/null +++ b/pac/atsamc20n/src/dmac/baseaddr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `BASEADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BASEADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BASEADDR` reader - Descriptor Memory Base Address"] +pub struct BASEADDR_R(crate::FieldReader); +impl BASEADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + BASEADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BASEADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BASEADDR` writer - Descriptor Memory Base Address"] +pub struct BASEADDR_W<'a> { + w: &'a mut W, +} +impl<'a> BASEADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Descriptor Memory Base Address"] + #[inline(always)] + pub fn baseaddr(&self) -> BASEADDR_R { + BASEADDR_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Descriptor Memory Base Address"] + #[inline(always)] + pub fn baseaddr(&mut self) -> BASEADDR_W { + BASEADDR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Descriptor Memory Section Base Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baseaddr](index.html) module"] +pub struct BASEADDR_SPEC; +impl crate::RegisterSpec for BASEADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [baseaddr::R](R) reader structure"] +impl crate::Readable for BASEADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baseaddr::W](W) writer structure"] +impl crate::Writable for BASEADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BASEADDR to value 0"] +impl crate::Resettable for BASEADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/dmac/busych.rs b/pac/atsamc20n/src/dmac/busych.rs new file mode 100644 index 000000000000..6f9419d5828b --- /dev/null +++ b/pac/atsamc20n/src/dmac/busych.rs @@ -0,0 +1,273 @@ +#[doc = "Register `BUSYCH` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `BUSYCH0` reader - Busy Channel 0"] +pub struct BUSYCH0_R(crate::FieldReader); +impl BUSYCH0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH1` reader - Busy Channel 1"] +pub struct BUSYCH1_R(crate::FieldReader); +impl BUSYCH1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH2` reader - Busy Channel 2"] +pub struct BUSYCH2_R(crate::FieldReader); +impl BUSYCH2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH3` reader - Busy Channel 3"] +pub struct BUSYCH3_R(crate::FieldReader); +impl BUSYCH3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH4` reader - Busy Channel 4"] +pub struct BUSYCH4_R(crate::FieldReader); +impl BUSYCH4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH5` reader - Busy Channel 5"] +pub struct BUSYCH5_R(crate::FieldReader); +impl BUSYCH5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH6` reader - Busy Channel 6"] +pub struct BUSYCH6_R(crate::FieldReader); +impl BUSYCH6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH7` reader - Busy Channel 7"] +pub struct BUSYCH7_R(crate::FieldReader); +impl BUSYCH7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH8` reader - Busy Channel 8"] +pub struct BUSYCH8_R(crate::FieldReader); +impl BUSYCH8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH9` reader - Busy Channel 9"] +pub struct BUSYCH9_R(crate::FieldReader); +impl BUSYCH9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH10` reader - Busy Channel 10"] +pub struct BUSYCH10_R(crate::FieldReader); +impl BUSYCH10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH11` reader - Busy Channel 11"] +pub struct BUSYCH11_R(crate::FieldReader); +impl BUSYCH11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Busy Channel 0"] + #[inline(always)] + pub fn busych0(&self) -> BUSYCH0_R { + BUSYCH0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Busy Channel 1"] + #[inline(always)] + pub fn busych1(&self) -> BUSYCH1_R { + BUSYCH1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Busy Channel 2"] + #[inline(always)] + pub fn busych2(&self) -> BUSYCH2_R { + BUSYCH2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Busy Channel 3"] + #[inline(always)] + pub fn busych3(&self) -> BUSYCH3_R { + BUSYCH3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Busy Channel 4"] + #[inline(always)] + pub fn busych4(&self) -> BUSYCH4_R { + BUSYCH4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Busy Channel 5"] + #[inline(always)] + pub fn busych5(&self) -> BUSYCH5_R { + BUSYCH5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Busy Channel 6"] + #[inline(always)] + pub fn busych6(&self) -> BUSYCH6_R { + BUSYCH6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Busy Channel 7"] + #[inline(always)] + pub fn busych7(&self) -> BUSYCH7_R { + BUSYCH7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Busy Channel 8"] + #[inline(always)] + pub fn busych8(&self) -> BUSYCH8_R { + BUSYCH8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Busy Channel 9"] + #[inline(always)] + pub fn busych9(&self) -> BUSYCH9_R { + BUSYCH9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Busy Channel 10"] + #[inline(always)] + pub fn busych10(&self) -> BUSYCH10_R { + BUSYCH10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Busy Channel 11"] + #[inline(always)] + pub fn busych11(&self) -> BUSYCH11_R { + BUSYCH11_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +#[doc = "Busy Channels\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [busych](index.html) module"] +pub struct BUSYCH_SPEC; +impl crate::RegisterSpec for BUSYCH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [busych::R](R) reader structure"] +impl crate::Readable for BUSYCH_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets BUSYCH to value 0"] +impl crate::Resettable for BUSYCH_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/dmac/chctrla.rs b/pac/atsamc20n/src/dmac/chctrla.rs new file mode 100644 index 000000000000..22e8d456e05c --- /dev/null +++ b/pac/atsamc20n/src/dmac/chctrla.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CHCTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHCTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Channel Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Channel Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Channel Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Channel Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Channel run in standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Channel run in standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - Channel Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 6 - Channel run in standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Channel Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 6 - Channel run in standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chctrla](index.html) module"] +pub struct CHCTRLA_SPEC; +impl crate::RegisterSpec for CHCTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [chctrla::R](R) reader structure"] +impl crate::Readable for CHCTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chctrla::W](W) writer structure"] +impl crate::Writable for CHCTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHCTRLA to value 0"] +impl crate::Resettable for CHCTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/dmac/chctrlb.rs b/pac/atsamc20n/src/dmac/chctrlb.rs new file mode 100644 index 000000000000..3ac6768f8d65 --- /dev/null +++ b/pac/atsamc20n/src/dmac/chctrlb.rs @@ -0,0 +1,1409 @@ +#[doc = "Register `CHCTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHCTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Event Input Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EVACT_A { + #[doc = "0: No action"] + NOACT = 0, + #[doc = "1: Transfer and periodic transfer trigger"] + TRIG = 1, + #[doc = "2: Conditional transfer trigger"] + CTRIG = 2, + #[doc = "3: Conditional block transfer"] + CBLOCK = 3, + #[doc = "4: Channel suspend operation"] + SUSPEND = 4, + #[doc = "5: Channel resume operation"] + RESUME = 5, + #[doc = "6: Skip next block suspend action"] + SSKIP = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EVACT_A) -> Self { + variant as _ + } +} +#[doc = "Field `EVACT` reader - Event Input Action"] +pub struct EVACT_R(crate::FieldReader); +impl EVACT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(EVACT_A::NOACT), + 1 => Some(EVACT_A::TRIG), + 2 => Some(EVACT_A::CTRIG), + 3 => Some(EVACT_A::CBLOCK), + 4 => Some(EVACT_A::SUSPEND), + 5 => Some(EVACT_A::RESUME), + 6 => Some(EVACT_A::SSKIP), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NOACT`"] + #[inline(always)] + pub fn is_noact(&self) -> bool { + **self == EVACT_A::NOACT + } + #[doc = "Checks if the value of the field is `TRIG`"] + #[inline(always)] + pub fn is_trig(&self) -> bool { + **self == EVACT_A::TRIG + } + #[doc = "Checks if the value of the field is `CTRIG`"] + #[inline(always)] + pub fn is_ctrig(&self) -> bool { + **self == EVACT_A::CTRIG + } + #[doc = "Checks if the value of the field is `CBLOCK`"] + #[inline(always)] + pub fn is_cblock(&self) -> bool { + **self == EVACT_A::CBLOCK + } + #[doc = "Checks if the value of the field is `SUSPEND`"] + #[inline(always)] + pub fn is_suspend(&self) -> bool { + **self == EVACT_A::SUSPEND + } + #[doc = "Checks if the value of the field is `RESUME`"] + #[inline(always)] + pub fn is_resume(&self) -> bool { + **self == EVACT_A::RESUME + } + #[doc = "Checks if the value of the field is `SSKIP`"] + #[inline(always)] + pub fn is_sskip(&self) -> bool { + **self == EVACT_A::SSKIP + } +} +impl core::ops::Deref for EVACT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT` writer - Event Input Action"] +pub struct EVACT_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EVACT_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn noact(self) -> &'a mut W { + self.variant(EVACT_A::NOACT) + } + #[doc = "Transfer and periodic transfer trigger"] + #[inline(always)] + pub fn trig(self) -> &'a mut W { + self.variant(EVACT_A::TRIG) + } + #[doc = "Conditional transfer trigger"] + #[inline(always)] + pub fn ctrig(self) -> &'a mut W { + self.variant(EVACT_A::CTRIG) + } + #[doc = "Conditional block transfer"] + #[inline(always)] + pub fn cblock(self) -> &'a mut W { + self.variant(EVACT_A::CBLOCK) + } + #[doc = "Channel suspend operation"] + #[inline(always)] + pub fn suspend(self) -> &'a mut W { + self.variant(EVACT_A::SUSPEND) + } + #[doc = "Channel resume operation"] + #[inline(always)] + pub fn resume(self) -> &'a mut W { + self.variant(EVACT_A::RESUME) + } + #[doc = "Skip next block suspend action"] + #[inline(always)] + pub fn sskip(self) -> &'a mut W { + self.variant(EVACT_A::SSKIP) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Field `EVIE` reader - Channel Event Input Enable"] +pub struct EVIE_R(crate::FieldReader); +impl EVIE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVIE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVIE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVIE` writer - Channel Event Input Enable"] +pub struct EVIE_W<'a> { + w: &'a mut W, +} +impl<'a> EVIE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `EVOE` reader - Channel Event Output Enable"] +pub struct EVOE_R(crate::FieldReader); +impl EVOE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVOE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVOE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVOE` writer - Channel Event Output Enable"] +pub struct EVOE_W<'a> { + w: &'a mut W, +} +impl<'a> EVOE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Channel Arbitration Level\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum LVL_A { + #[doc = "0: Channel Priority Level 0"] + LVL0 = 0, + #[doc = "1: Channel Priority Level 1"] + LVL1 = 1, + #[doc = "2: Channel Priority Level 2"] + LVL2 = 2, + #[doc = "3: Channel Priority Level 3"] + LVL3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LVL_A) -> Self { + variant as _ + } +} +#[doc = "Field `LVL` reader - Channel Arbitration Level"] +pub struct LVL_R(crate::FieldReader); +impl LVL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LVL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> LVL_A { + match self.bits { + 0 => LVL_A::LVL0, + 1 => LVL_A::LVL1, + 2 => LVL_A::LVL2, + 3 => LVL_A::LVL3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `LVL0`"] + #[inline(always)] + pub fn is_lvl0(&self) -> bool { + **self == LVL_A::LVL0 + } + #[doc = "Checks if the value of the field is `LVL1`"] + #[inline(always)] + pub fn is_lvl1(&self) -> bool { + **self == LVL_A::LVL1 + } + #[doc = "Checks if the value of the field is `LVL2`"] + #[inline(always)] + pub fn is_lvl2(&self) -> bool { + **self == LVL_A::LVL2 + } + #[doc = "Checks if the value of the field is `LVL3`"] + #[inline(always)] + pub fn is_lvl3(&self) -> bool { + **self == LVL_A::LVL3 + } +} +impl core::ops::Deref for LVL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVL` writer - Channel Arbitration Level"] +pub struct LVL_W<'a> { + w: &'a mut W, +} +impl<'a> LVL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: LVL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Channel Priority Level 0"] + #[inline(always)] + pub fn lvl0(self) -> &'a mut W { + self.variant(LVL_A::LVL0) + } + #[doc = "Channel Priority Level 1"] + #[inline(always)] + pub fn lvl1(self) -> &'a mut W { + self.variant(LVL_A::LVL1) + } + #[doc = "Channel Priority Level 2"] + #[inline(always)] + pub fn lvl2(self) -> &'a mut W { + self.variant(LVL_A::LVL2) + } + #[doc = "Channel Priority Level 3"] + #[inline(always)] + pub fn lvl3(self) -> &'a mut W { + self.variant(LVL_A::LVL3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 5)) | ((value as u32 & 0x03) << 5); + self.w + } +} +#[doc = "Trigger Source\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum TRIGSRC_A { + #[doc = "0: Only software/event triggers"] + DISABLE = 0, + #[doc = "2: SERCOM0 RX Trigger"] + SERCOM0_RX = 2, + #[doc = "3: SERCOM0 TX Trigger"] + SERCOM0_TX = 3, + #[doc = "4: SERCOM1 RX Trigger"] + SERCOM1_RX = 4, + #[doc = "5: SERCOM1 TX Trigger"] + SERCOM1_TX = 5, + #[doc = "6: SERCOM2 RX Trigger"] + SERCOM2_RX = 6, + #[doc = "7: SERCOM2 TX Trigger"] + SERCOM2_TX = 7, + #[doc = "8: SERCOM3 RX Trigger"] + SERCOM3_RX = 8, + #[doc = "9: SERCOM3 TX Trigger"] + SERCOM3_TX = 9, + #[doc = "10: SERCOM4 RX Trigger"] + SERCOM4_RX = 10, + #[doc = "11: SERCOM4 TX Trigger"] + SERCOM4_TX = 11, + #[doc = "12: SERCOM5 RX Trigger"] + SERCOM5_RX = 12, + #[doc = "13: SERCOM5 TX Trigger"] + SERCOM5_TX = 13, + #[doc = "16: TCC0 Overflow Trigger"] + TCC0_OVF = 16, + #[doc = "17: TCC0 Match/Compare 0 Trigger"] + TCC0_MC0 = 17, + #[doc = "18: TCC0 Match/Compare 1 Trigger"] + TCC0_MC1 = 18, + #[doc = "19: TCC0 Match/Compare 2 Trigger"] + TCC0_MC2 = 19, + #[doc = "20: TCC0 Match/Compare 3 Trigger"] + TCC0_MC3 = 20, + #[doc = "21: TCC1 Overflow Trigger"] + TCC1_OVF = 21, + #[doc = "22: TCC1 Match/Compare 0 Trigger"] + TCC1_MC0 = 22, + #[doc = "23: TCC1 Match/Compare 1 Trigger"] + TCC1_MC1 = 23, + #[doc = "24: TCC2 Overflow Trigger"] + TCC2_OVF = 24, + #[doc = "25: TCC2 Match/Compare 0 Trigger"] + TCC2_MC0 = 25, + #[doc = "26: TCC2 Match/Compare 1 Trigger"] + TCC2_MC1 = 26, + #[doc = "27: TC0 Overflow Trigger"] + TC0_OVF = 27, + #[doc = "28: TC0 Match/Compare 0 Trigger"] + TC0_MC0 = 28, + #[doc = "29: TC0 Match/Compare 1 Trigger"] + TC0_MC1 = 29, + #[doc = "30: TC1 Overflow Trigger"] + TC1_OVF = 30, + #[doc = "31: TC1 Match/Compare 0 Trigger"] + TC1_MC0 = 31, + #[doc = "32: TC1 Match/Compare 1 Trigger"] + TC1_MC1 = 32, + #[doc = "33: TC2 Overflow Trigger"] + TC2_OVF = 33, + #[doc = "34: TC2 Match/Compare 0 Trigger"] + TC2_MC0 = 34, + #[doc = "35: TC2 Match/Compare 1 Trigger"] + TC2_MC1 = 35, + #[doc = "36: TC3 Overflow Trigger"] + TC3_OVF = 36, + #[doc = "37: TC3 Match/Compare 0 Trigger"] + TC3_MC0 = 37, + #[doc = "38: TC3 Match/Compare 1 Trigger"] + TC3_MC1 = 38, + #[doc = "39: TC4 Overflow Trigger"] + TC4_OVF = 39, + #[doc = "40: TC4 Match/Compare 0 Trigger"] + TC4_MC0 = 40, + #[doc = "41: TC4 Match/Compare 1 Trigger"] + TC4_MC1 = 41, + #[doc = "42: ADC0 Result Ready Trigger"] + ADC0_RESRDY = 42, + #[doc = "46: PTC End of Conversion Trigger"] + PTC_EOC = 46, + #[doc = "47: PTC Window Compare Trigger"] + PTC_WCOMP = 47, + #[doc = "48: PTC Sequence Trigger"] + PTC_SEQ = 48, + #[doc = "49: SERCOM6 RX Trigger"] + SERCOM6_RX = 49, + #[doc = "50: SERCOM6 TX Trigger"] + SERCOM6_TX = 50, + #[doc = "51: SERCOM7 RX Trigger"] + SERCOM7_RX = 51, + #[doc = "52: SERCOM7 TX Trigger"] + SERCOM7_TX = 52, + #[doc = "53: TC5 Overflow Trigger"] + TC5_OVF = 53, + #[doc = "54: TC5 Match/Compare 0 Trigger"] + TC5_MC0 = 54, + #[doc = "55: TC5 Match/Compare 1 Trigger"] + TC5_MC1 = 55, + #[doc = "56: TC6 Overflow Trigger"] + TC6_OVF = 56, + #[doc = "57: TC6 Match/Compare 0 Trigger"] + TC6_MC0 = 57, + #[doc = "58: TC6 Match/Compare 1 Trigger"] + TC6_MC1 = 58, + #[doc = "59: TC7 Overflow Trigger"] + TC7_OVF = 59, + #[doc = "60: TC7 Match/Compare 0 Trigger"] + TC7_MC0 = 60, + #[doc = "61: TC7 Match/Compare 1 Trigger"] + TC7_MC1 = 61, +} +impl From for u8 { + #[inline(always)] + fn from(variant: TRIGSRC_A) -> Self { + variant as _ + } +} +#[doc = "Field `TRIGSRC` reader - Trigger Source"] +pub struct TRIGSRC_R(crate::FieldReader); +impl TRIGSRC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TRIGSRC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(TRIGSRC_A::DISABLE), + 2 => Some(TRIGSRC_A::SERCOM0_RX), + 3 => Some(TRIGSRC_A::SERCOM0_TX), + 4 => Some(TRIGSRC_A::SERCOM1_RX), + 5 => Some(TRIGSRC_A::SERCOM1_TX), + 6 => Some(TRIGSRC_A::SERCOM2_RX), + 7 => Some(TRIGSRC_A::SERCOM2_TX), + 8 => Some(TRIGSRC_A::SERCOM3_RX), + 9 => Some(TRIGSRC_A::SERCOM3_TX), + 10 => Some(TRIGSRC_A::SERCOM4_RX), + 11 => Some(TRIGSRC_A::SERCOM4_TX), + 12 => Some(TRIGSRC_A::SERCOM5_RX), + 13 => Some(TRIGSRC_A::SERCOM5_TX), + 16 => Some(TRIGSRC_A::TCC0_OVF), + 17 => Some(TRIGSRC_A::TCC0_MC0), + 18 => Some(TRIGSRC_A::TCC0_MC1), + 19 => Some(TRIGSRC_A::TCC0_MC2), + 20 => Some(TRIGSRC_A::TCC0_MC3), + 21 => Some(TRIGSRC_A::TCC1_OVF), + 22 => Some(TRIGSRC_A::TCC1_MC0), + 23 => Some(TRIGSRC_A::TCC1_MC1), + 24 => Some(TRIGSRC_A::TCC2_OVF), + 25 => Some(TRIGSRC_A::TCC2_MC0), + 26 => Some(TRIGSRC_A::TCC2_MC1), + 27 => Some(TRIGSRC_A::TC0_OVF), + 28 => Some(TRIGSRC_A::TC0_MC0), + 29 => Some(TRIGSRC_A::TC0_MC1), + 30 => Some(TRIGSRC_A::TC1_OVF), + 31 => Some(TRIGSRC_A::TC1_MC0), + 32 => Some(TRIGSRC_A::TC1_MC1), + 33 => Some(TRIGSRC_A::TC2_OVF), + 34 => Some(TRIGSRC_A::TC2_MC0), + 35 => Some(TRIGSRC_A::TC2_MC1), + 36 => Some(TRIGSRC_A::TC3_OVF), + 37 => Some(TRIGSRC_A::TC3_MC0), + 38 => Some(TRIGSRC_A::TC3_MC1), + 39 => Some(TRIGSRC_A::TC4_OVF), + 40 => Some(TRIGSRC_A::TC4_MC0), + 41 => Some(TRIGSRC_A::TC4_MC1), + 42 => Some(TRIGSRC_A::ADC0_RESRDY), + 46 => Some(TRIGSRC_A::PTC_EOC), + 47 => Some(TRIGSRC_A::PTC_WCOMP), + 48 => Some(TRIGSRC_A::PTC_SEQ), + 49 => Some(TRIGSRC_A::SERCOM6_RX), + 50 => Some(TRIGSRC_A::SERCOM6_TX), + 51 => Some(TRIGSRC_A::SERCOM7_RX), + 52 => Some(TRIGSRC_A::SERCOM7_TX), + 53 => Some(TRIGSRC_A::TC5_OVF), + 54 => Some(TRIGSRC_A::TC5_MC0), + 55 => Some(TRIGSRC_A::TC5_MC1), + 56 => Some(TRIGSRC_A::TC6_OVF), + 57 => Some(TRIGSRC_A::TC6_MC0), + 58 => Some(TRIGSRC_A::TC6_MC1), + 59 => Some(TRIGSRC_A::TC7_OVF), + 60 => Some(TRIGSRC_A::TC7_MC0), + 61 => Some(TRIGSRC_A::TC7_MC1), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == TRIGSRC_A::DISABLE + } + #[doc = "Checks if the value of the field is `SERCOM0_RX`"] + #[inline(always)] + pub fn is_sercom0_rx(&self) -> bool { + **self == TRIGSRC_A::SERCOM0_RX + } + #[doc = "Checks if the value of the field is `SERCOM0_TX`"] + #[inline(always)] + pub fn is_sercom0_tx(&self) -> bool { + **self == TRIGSRC_A::SERCOM0_TX + } + #[doc = "Checks if the value of the field is `SERCOM1_RX`"] + #[inline(always)] + pub fn is_sercom1_rx(&self) -> bool { + **self == TRIGSRC_A::SERCOM1_RX + } + #[doc = "Checks if the value of the field is `SERCOM1_TX`"] + #[inline(always)] + pub fn is_sercom1_tx(&self) -> bool { + **self == TRIGSRC_A::SERCOM1_TX + } + #[doc = "Checks if the value of the field is `SERCOM2_RX`"] + #[inline(always)] + pub fn is_sercom2_rx(&self) -> bool { + **self == TRIGSRC_A::SERCOM2_RX + } + #[doc = "Checks if the value of the field is `SERCOM2_TX`"] + #[inline(always)] + pub fn is_sercom2_tx(&self) -> bool { + **self == TRIGSRC_A::SERCOM2_TX + } + #[doc = "Checks if the value of the field is `SERCOM3_RX`"] + #[inline(always)] + pub fn is_sercom3_rx(&self) -> bool { + **self == TRIGSRC_A::SERCOM3_RX + } + #[doc = "Checks if the value of the field is `SERCOM3_TX`"] + #[inline(always)] + pub fn is_sercom3_tx(&self) -> bool { + **self == TRIGSRC_A::SERCOM3_TX + } + #[doc = "Checks if the value of the field is `SERCOM4_RX`"] + #[inline(always)] + pub fn is_sercom4_rx(&self) -> bool { + **self == TRIGSRC_A::SERCOM4_RX + } + #[doc = "Checks if the value of the field is `SERCOM4_TX`"] + #[inline(always)] + pub fn is_sercom4_tx(&self) -> bool { + **self == TRIGSRC_A::SERCOM4_TX + } + #[doc = "Checks if the value of the field is `SERCOM5_RX`"] + #[inline(always)] + pub fn is_sercom5_rx(&self) -> bool { + **self == TRIGSRC_A::SERCOM5_RX + } + #[doc = "Checks if the value of the field is `SERCOM5_TX`"] + #[inline(always)] + pub fn is_sercom5_tx(&self) -> bool { + **self == TRIGSRC_A::SERCOM5_TX + } + #[doc = "Checks if the value of the field is `TCC0_OVF`"] + #[inline(always)] + pub fn is_tcc0_ovf(&self) -> bool { + **self == TRIGSRC_A::TCC0_OVF + } + #[doc = "Checks if the value of the field is `TCC0_MC0`"] + #[inline(always)] + pub fn is_tcc0_mc0(&self) -> bool { + **self == TRIGSRC_A::TCC0_MC0 + } + #[doc = "Checks if the value of the field is `TCC0_MC1`"] + #[inline(always)] + pub fn is_tcc0_mc1(&self) -> bool { + **self == TRIGSRC_A::TCC0_MC1 + } + #[doc = "Checks if the value of the field is `TCC0_MC2`"] + #[inline(always)] + pub fn is_tcc0_mc2(&self) -> bool { + **self == TRIGSRC_A::TCC0_MC2 + } + #[doc = "Checks if the value of the field is `TCC0_MC3`"] + #[inline(always)] + pub fn is_tcc0_mc3(&self) -> bool { + **self == TRIGSRC_A::TCC0_MC3 + } + #[doc = "Checks if the value of the field is `TCC1_OVF`"] + #[inline(always)] + pub fn is_tcc1_ovf(&self) -> bool { + **self == TRIGSRC_A::TCC1_OVF + } + #[doc = "Checks if the value of the field is `TCC1_MC0`"] + #[inline(always)] + pub fn is_tcc1_mc0(&self) -> bool { + **self == TRIGSRC_A::TCC1_MC0 + } + #[doc = "Checks if the value of the field is `TCC1_MC1`"] + #[inline(always)] + pub fn is_tcc1_mc1(&self) -> bool { + **self == TRIGSRC_A::TCC1_MC1 + } + #[doc = "Checks if the value of the field is `TCC2_OVF`"] + #[inline(always)] + pub fn is_tcc2_ovf(&self) -> bool { + **self == TRIGSRC_A::TCC2_OVF + } + #[doc = "Checks if the value of the field is `TCC2_MC0`"] + #[inline(always)] + pub fn is_tcc2_mc0(&self) -> bool { + **self == TRIGSRC_A::TCC2_MC0 + } + #[doc = "Checks if the value of the field is `TCC2_MC1`"] + #[inline(always)] + pub fn is_tcc2_mc1(&self) -> bool { + **self == TRIGSRC_A::TCC2_MC1 + } + #[doc = "Checks if the value of the field is `TC0_OVF`"] + #[inline(always)] + pub fn is_tc0_ovf(&self) -> bool { + **self == TRIGSRC_A::TC0_OVF + } + #[doc = "Checks if the value of the field is `TC0_MC0`"] + #[inline(always)] + pub fn is_tc0_mc0(&self) -> bool { + **self == TRIGSRC_A::TC0_MC0 + } + #[doc = "Checks if the value of the field is `TC0_MC1`"] + #[inline(always)] + pub fn is_tc0_mc1(&self) -> bool { + **self == TRIGSRC_A::TC0_MC1 + } + #[doc = "Checks if the value of the field is `TC1_OVF`"] + #[inline(always)] + pub fn is_tc1_ovf(&self) -> bool { + **self == TRIGSRC_A::TC1_OVF + } + #[doc = "Checks if the value of the field is `TC1_MC0`"] + #[inline(always)] + pub fn is_tc1_mc0(&self) -> bool { + **self == TRIGSRC_A::TC1_MC0 + } + #[doc = "Checks if the value of the field is `TC1_MC1`"] + #[inline(always)] + pub fn is_tc1_mc1(&self) -> bool { + **self == TRIGSRC_A::TC1_MC1 + } + #[doc = "Checks if the value of the field is `TC2_OVF`"] + #[inline(always)] + pub fn is_tc2_ovf(&self) -> bool { + **self == TRIGSRC_A::TC2_OVF + } + #[doc = "Checks if the value of the field is `TC2_MC0`"] + #[inline(always)] + pub fn is_tc2_mc0(&self) -> bool { + **self == TRIGSRC_A::TC2_MC0 + } + #[doc = "Checks if the value of the field is `TC2_MC1`"] + #[inline(always)] + pub fn is_tc2_mc1(&self) -> bool { + **self == TRIGSRC_A::TC2_MC1 + } + #[doc = "Checks if the value of the field is `TC3_OVF`"] + #[inline(always)] + pub fn is_tc3_ovf(&self) -> bool { + **self == TRIGSRC_A::TC3_OVF + } + #[doc = "Checks if the value of the field is `TC3_MC0`"] + #[inline(always)] + pub fn is_tc3_mc0(&self) -> bool { + **self == TRIGSRC_A::TC3_MC0 + } + #[doc = "Checks if the value of the field is `TC3_MC1`"] + #[inline(always)] + pub fn is_tc3_mc1(&self) -> bool { + **self == TRIGSRC_A::TC3_MC1 + } + #[doc = "Checks if the value of the field is `TC4_OVF`"] + #[inline(always)] + pub fn is_tc4_ovf(&self) -> bool { + **self == TRIGSRC_A::TC4_OVF + } + #[doc = "Checks if the value of the field is `TC4_MC0`"] + #[inline(always)] + pub fn is_tc4_mc0(&self) -> bool { + **self == TRIGSRC_A::TC4_MC0 + } + #[doc = "Checks if the value of the field is `TC4_MC1`"] + #[inline(always)] + pub fn is_tc4_mc1(&self) -> bool { + **self == TRIGSRC_A::TC4_MC1 + } + #[doc = "Checks if the value of the field is `ADC0_RESRDY`"] + #[inline(always)] + pub fn is_adc0_resrdy(&self) -> bool { + **self == TRIGSRC_A::ADC0_RESRDY + } + #[doc = "Checks if the value of the field is `PTC_EOC`"] + #[inline(always)] + pub fn is_ptc_eoc(&self) -> bool { + **self == TRIGSRC_A::PTC_EOC + } + #[doc = "Checks if the value of the field is `PTC_WCOMP`"] + #[inline(always)] + pub fn is_ptc_wcomp(&self) -> bool { + **self == TRIGSRC_A::PTC_WCOMP + } + #[doc = "Checks if the value of the field is `PTC_SEQ`"] + #[inline(always)] + pub fn is_ptc_seq(&self) -> bool { + **self == TRIGSRC_A::PTC_SEQ + } + #[doc = "Checks if the value of the field is `SERCOM6_RX`"] + #[inline(always)] + pub fn is_sercom6_rx(&self) -> bool { + **self == TRIGSRC_A::SERCOM6_RX + } + #[doc = "Checks if the value of the field is `SERCOM6_TX`"] + #[inline(always)] + pub fn is_sercom6_tx(&self) -> bool { + **self == TRIGSRC_A::SERCOM6_TX + } + #[doc = "Checks if the value of the field is `SERCOM7_RX`"] + #[inline(always)] + pub fn is_sercom7_rx(&self) -> bool { + **self == TRIGSRC_A::SERCOM7_RX + } + #[doc = "Checks if the value of the field is `SERCOM7_TX`"] + #[inline(always)] + pub fn is_sercom7_tx(&self) -> bool { + **self == TRIGSRC_A::SERCOM7_TX + } + #[doc = "Checks if the value of the field is `TC5_OVF`"] + #[inline(always)] + pub fn is_tc5_ovf(&self) -> bool { + **self == TRIGSRC_A::TC5_OVF + } + #[doc = "Checks if the value of the field is `TC5_MC0`"] + #[inline(always)] + pub fn is_tc5_mc0(&self) -> bool { + **self == TRIGSRC_A::TC5_MC0 + } + #[doc = "Checks if the value of the field is `TC5_MC1`"] + #[inline(always)] + pub fn is_tc5_mc1(&self) -> bool { + **self == TRIGSRC_A::TC5_MC1 + } + #[doc = "Checks if the value of the field is `TC6_OVF`"] + #[inline(always)] + pub fn is_tc6_ovf(&self) -> bool { + **self == TRIGSRC_A::TC6_OVF + } + #[doc = "Checks if the value of the field is `TC6_MC0`"] + #[inline(always)] + pub fn is_tc6_mc0(&self) -> bool { + **self == TRIGSRC_A::TC6_MC0 + } + #[doc = "Checks if the value of the field is `TC6_MC1`"] + #[inline(always)] + pub fn is_tc6_mc1(&self) -> bool { + **self == TRIGSRC_A::TC6_MC1 + } + #[doc = "Checks if the value of the field is `TC7_OVF`"] + #[inline(always)] + pub fn is_tc7_ovf(&self) -> bool { + **self == TRIGSRC_A::TC7_OVF + } + #[doc = "Checks if the value of the field is `TC7_MC0`"] + #[inline(always)] + pub fn is_tc7_mc0(&self) -> bool { + **self == TRIGSRC_A::TC7_MC0 + } + #[doc = "Checks if the value of the field is `TC7_MC1`"] + #[inline(always)] + pub fn is_tc7_mc1(&self) -> bool { + **self == TRIGSRC_A::TC7_MC1 + } +} +impl core::ops::Deref for TRIGSRC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRIGSRC` writer - Trigger Source"] +pub struct TRIGSRC_W<'a> { + w: &'a mut W, +} +impl<'a> TRIGSRC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TRIGSRC_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Only software/event triggers"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(TRIGSRC_A::DISABLE) + } + #[doc = "SERCOM0 RX Trigger"] + #[inline(always)] + pub fn sercom0_rx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM0_RX) + } + #[doc = "SERCOM0 TX Trigger"] + #[inline(always)] + pub fn sercom0_tx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM0_TX) + } + #[doc = "SERCOM1 RX Trigger"] + #[inline(always)] + pub fn sercom1_rx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM1_RX) + } + #[doc = "SERCOM1 TX Trigger"] + #[inline(always)] + pub fn sercom1_tx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM1_TX) + } + #[doc = "SERCOM2 RX Trigger"] + #[inline(always)] + pub fn sercom2_rx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM2_RX) + } + #[doc = "SERCOM2 TX Trigger"] + #[inline(always)] + pub fn sercom2_tx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM2_TX) + } + #[doc = "SERCOM3 RX Trigger"] + #[inline(always)] + pub fn sercom3_rx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM3_RX) + } + #[doc = "SERCOM3 TX Trigger"] + #[inline(always)] + pub fn sercom3_tx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM3_TX) + } + #[doc = "SERCOM4 RX Trigger"] + #[inline(always)] + pub fn sercom4_rx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM4_RX) + } + #[doc = "SERCOM4 TX Trigger"] + #[inline(always)] + pub fn sercom4_tx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM4_TX) + } + #[doc = "SERCOM5 RX Trigger"] + #[inline(always)] + pub fn sercom5_rx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM5_RX) + } + #[doc = "SERCOM5 TX Trigger"] + #[inline(always)] + pub fn sercom5_tx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM5_TX) + } + #[doc = "TCC0 Overflow Trigger"] + #[inline(always)] + pub fn tcc0_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC0_OVF) + } + #[doc = "TCC0 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tcc0_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC0_MC0) + } + #[doc = "TCC0 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tcc0_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC0_MC1) + } + #[doc = "TCC0 Match/Compare 2 Trigger"] + #[inline(always)] + pub fn tcc0_mc2(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC0_MC2) + } + #[doc = "TCC0 Match/Compare 3 Trigger"] + #[inline(always)] + pub fn tcc0_mc3(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC0_MC3) + } + #[doc = "TCC1 Overflow Trigger"] + #[inline(always)] + pub fn tcc1_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC1_OVF) + } + #[doc = "TCC1 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tcc1_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC1_MC0) + } + #[doc = "TCC1 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tcc1_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC1_MC1) + } + #[doc = "TCC2 Overflow Trigger"] + #[inline(always)] + pub fn tcc2_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC2_OVF) + } + #[doc = "TCC2 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tcc2_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC2_MC0) + } + #[doc = "TCC2 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tcc2_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC2_MC1) + } + #[doc = "TC0 Overflow Trigger"] + #[inline(always)] + pub fn tc0_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC0_OVF) + } + #[doc = "TC0 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tc0_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC0_MC0) + } + #[doc = "TC0 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tc0_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC0_MC1) + } + #[doc = "TC1 Overflow Trigger"] + #[inline(always)] + pub fn tc1_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC1_OVF) + } + #[doc = "TC1 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tc1_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC1_MC0) + } + #[doc = "TC1 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tc1_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC1_MC1) + } + #[doc = "TC2 Overflow Trigger"] + #[inline(always)] + pub fn tc2_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC2_OVF) + } + #[doc = "TC2 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tc2_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC2_MC0) + } + #[doc = "TC2 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tc2_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC2_MC1) + } + #[doc = "TC3 Overflow Trigger"] + #[inline(always)] + pub fn tc3_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC3_OVF) + } + #[doc = "TC3 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tc3_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC3_MC0) + } + #[doc = "TC3 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tc3_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC3_MC1) + } + #[doc = "TC4 Overflow Trigger"] + #[inline(always)] + pub fn tc4_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC4_OVF) + } + #[doc = "TC4 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tc4_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC4_MC0) + } + #[doc = "TC4 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tc4_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC4_MC1) + } + #[doc = "ADC0 Result Ready Trigger"] + #[inline(always)] + pub fn adc0_resrdy(self) -> &'a mut W { + self.variant(TRIGSRC_A::ADC0_RESRDY) + } + #[doc = "PTC End of Conversion Trigger"] + #[inline(always)] + pub fn ptc_eoc(self) -> &'a mut W { + self.variant(TRIGSRC_A::PTC_EOC) + } + #[doc = "PTC Window Compare Trigger"] + #[inline(always)] + pub fn ptc_wcomp(self) -> &'a mut W { + self.variant(TRIGSRC_A::PTC_WCOMP) + } + #[doc = "PTC Sequence Trigger"] + #[inline(always)] + pub fn ptc_seq(self) -> &'a mut W { + self.variant(TRIGSRC_A::PTC_SEQ) + } + #[doc = "SERCOM6 RX Trigger"] + #[inline(always)] + pub fn sercom6_rx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM6_RX) + } + #[doc = "SERCOM6 TX Trigger"] + #[inline(always)] + pub fn sercom6_tx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM6_TX) + } + #[doc = "SERCOM7 RX Trigger"] + #[inline(always)] + pub fn sercom7_rx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM7_RX) + } + #[doc = "SERCOM7 TX Trigger"] + #[inline(always)] + pub fn sercom7_tx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM7_TX) + } + #[doc = "TC5 Overflow Trigger"] + #[inline(always)] + pub fn tc5_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC5_OVF) + } + #[doc = "TC5 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tc5_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC5_MC0) + } + #[doc = "TC5 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tc5_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC5_MC1) + } + #[doc = "TC6 Overflow Trigger"] + #[inline(always)] + pub fn tc6_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC6_OVF) + } + #[doc = "TC6 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tc6_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC6_MC0) + } + #[doc = "TC6 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tc6_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC6_MC1) + } + #[doc = "TC7 Overflow Trigger"] + #[inline(always)] + pub fn tc7_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC7_OVF) + } + #[doc = "TC7 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tc7_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC7_MC0) + } + #[doc = "TC7 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tc7_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC7_MC1) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 8)) | ((value as u32 & 0x3f) << 8); + self.w + } +} +#[doc = "Trigger Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum TRIGACT_A { + #[doc = "0: One trigger required for each block transfer"] + BLOCK = 0, + #[doc = "2: One trigger required for each beat transfer"] + BEAT = 2, + #[doc = "3: One trigger required for each transaction"] + TRANSACTION = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: TRIGACT_A) -> Self { + variant as _ + } +} +#[doc = "Field `TRIGACT` reader - Trigger Action"] +pub struct TRIGACT_R(crate::FieldReader); +impl TRIGACT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TRIGACT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(TRIGACT_A::BLOCK), + 2 => Some(TRIGACT_A::BEAT), + 3 => Some(TRIGACT_A::TRANSACTION), + _ => None, + } + } + #[doc = "Checks if the value of the field is `BLOCK`"] + #[inline(always)] + pub fn is_block(&self) -> bool { + **self == TRIGACT_A::BLOCK + } + #[doc = "Checks if the value of the field is `BEAT`"] + #[inline(always)] + pub fn is_beat(&self) -> bool { + **self == TRIGACT_A::BEAT + } + #[doc = "Checks if the value of the field is `TRANSACTION`"] + #[inline(always)] + pub fn is_transaction(&self) -> bool { + **self == TRIGACT_A::TRANSACTION + } +} +impl core::ops::Deref for TRIGACT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRIGACT` writer - Trigger Action"] +pub struct TRIGACT_W<'a> { + w: &'a mut W, +} +impl<'a> TRIGACT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TRIGACT_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "One trigger required for each block transfer"] + #[inline(always)] + pub fn block(self) -> &'a mut W { + self.variant(TRIGACT_A::BLOCK) + } + #[doc = "One trigger required for each beat transfer"] + #[inline(always)] + pub fn beat(self) -> &'a mut W { + self.variant(TRIGACT_A::BEAT) + } + #[doc = "One trigger required for each transaction"] + #[inline(always)] + pub fn transaction(self) -> &'a mut W { + self.variant(TRIGACT_A::TRANSACTION) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 22)) | ((value as u32 & 0x03) << 22); + self.w + } +} +#[doc = "Software Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NOACT = 0, + #[doc = "1: Channel suspend operation"] + SUSPEND = 1, + #[doc = "2: Channel resume operation"] + RESUME = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Software Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NOACT), + 1 => Some(CMD_A::SUSPEND), + 2 => Some(CMD_A::RESUME), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NOACT`"] + #[inline(always)] + pub fn is_noact(&self) -> bool { + **self == CMD_A::NOACT + } + #[doc = "Checks if the value of the field is `SUSPEND`"] + #[inline(always)] + pub fn is_suspend(&self) -> bool { + **self == CMD_A::SUSPEND + } + #[doc = "Checks if the value of the field is `RESUME`"] + #[inline(always)] + pub fn is_resume(&self) -> bool { + **self == CMD_A::RESUME + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Software Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn noact(self) -> &'a mut W { + self.variant(CMD_A::NOACT) + } + #[doc = "Channel suspend operation"] + #[inline(always)] + pub fn suspend(self) -> &'a mut W { + self.variant(CMD_A::SUSPEND) + } + #[doc = "Channel resume operation"] + #[inline(always)] + pub fn resume(self) -> &'a mut W { + self.variant(CMD_A::RESUME) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 24)) | ((value as u32 & 0x03) << 24); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Event Input Action"] + #[inline(always)] + pub fn evact(&self) -> EVACT_R { + EVACT_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 3 - Channel Event Input Enable"] + #[inline(always)] + pub fn evie(&self) -> EVIE_R { + EVIE_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Channel Event Output Enable"] + #[inline(always)] + pub fn evoe(&self) -> EVOE_R { + EVOE_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bits 5:6 - Channel Arbitration Level"] + #[inline(always)] + pub fn lvl(&self) -> LVL_R { + LVL_R::new(((self.bits >> 5) & 0x03) as u8) + } + #[doc = "Bits 8:13 - Trigger Source"] + #[inline(always)] + pub fn trigsrc(&self) -> TRIGSRC_R { + TRIGSRC_R::new(((self.bits >> 8) & 0x3f) as u8) + } + #[doc = "Bits 22:23 - Trigger Action"] + #[inline(always)] + pub fn trigact(&self) -> TRIGACT_R { + TRIGACT_R::new(((self.bits >> 22) & 0x03) as u8) + } + #[doc = "Bits 24:25 - Software Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 24) & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Event Input Action"] + #[inline(always)] + pub fn evact(&mut self) -> EVACT_W { + EVACT_W { w: self } + } + #[doc = "Bit 3 - Channel Event Input Enable"] + #[inline(always)] + pub fn evie(&mut self) -> EVIE_W { + EVIE_W { w: self } + } + #[doc = "Bit 4 - Channel Event Output Enable"] + #[inline(always)] + pub fn evoe(&mut self) -> EVOE_W { + EVOE_W { w: self } + } + #[doc = "Bits 5:6 - Channel Arbitration Level"] + #[inline(always)] + pub fn lvl(&mut self) -> LVL_W { + LVL_W { w: self } + } + #[doc = "Bits 8:13 - Trigger Source"] + #[inline(always)] + pub fn trigsrc(&mut self) -> TRIGSRC_W { + TRIGSRC_W { w: self } + } + #[doc = "Bits 22:23 - Trigger Action"] + #[inline(always)] + pub fn trigact(&mut self) -> TRIGACT_W { + TRIGACT_W { w: self } + } + #[doc = "Bits 24:25 - Software Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chctrlb](index.html) module"] +pub struct CHCTRLB_SPEC; +impl crate::RegisterSpec for CHCTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [chctrlb::R](R) reader structure"] +impl crate::Readable for CHCTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chctrlb::W](W) writer structure"] +impl crate::Writable for CHCTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHCTRLB to value 0"] +impl crate::Resettable for CHCTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/dmac/chid.rs b/pac/atsamc20n/src/dmac/chid.rs new file mode 100644 index 000000000000..19151d8e10b0 --- /dev/null +++ b/pac/atsamc20n/src/dmac/chid.rs @@ -0,0 +1,103 @@ +#[doc = "Register `CHID` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHID` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ID` reader - Channel ID"] +pub struct ID_R(crate::FieldReader); +impl ID_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ID_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ID_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ID` writer - Channel ID"] +pub struct ID_W<'a> { + w: &'a mut W, +} +impl<'a> ID_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Channel ID"] + #[inline(always)] + pub fn id(&self) -> ID_R { + ID_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Channel ID"] + #[inline(always)] + pub fn id(&mut self) -> ID_W { + ID_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel ID\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chid](index.html) module"] +pub struct CHID_SPEC; +impl crate::RegisterSpec for CHID_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [chid::R](R) reader structure"] +impl crate::Readable for CHID_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chid::W](W) writer structure"] +impl crate::Writable for CHID_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHID to value 0"] +impl crate::Resettable for CHID_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/dmac/chintenclr.rs b/pac/atsamc20n/src/dmac/chintenclr.rs new file mode 100644 index 000000000000..5ae3096f9ab8 --- /dev/null +++ b/pac/atsamc20n/src/dmac/chintenclr.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CHINTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHINTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TERR` reader - Channel Transfer Error Interrupt Enable"] +pub struct TERR_R(crate::FieldReader); +impl TERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TERR` writer - Channel Transfer Error Interrupt Enable"] +pub struct TERR_W<'a> { + w: &'a mut W, +} +impl<'a> TERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TCMPL` reader - Channel Transfer Complete Interrupt Enable"] +pub struct TCMPL_R(crate::FieldReader); +impl TCMPL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCMPL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCMPL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCMPL` writer - Channel Transfer Complete Interrupt Enable"] +pub struct TCMPL_W<'a> { + w: &'a mut W, +} +impl<'a> TCMPL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SUSP` reader - Channel Suspend Interrupt Enable"] +pub struct SUSP_R(crate::FieldReader); +impl SUSP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SUSP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SUSP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SUSP` writer - Channel Suspend Interrupt Enable"] +pub struct SUSP_W<'a> { + w: &'a mut W, +} +impl<'a> SUSP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Channel Transfer Error Interrupt Enable"] + #[inline(always)] + pub fn terr(&self) -> TERR_R { + TERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel Transfer Complete Interrupt Enable"] + #[inline(always)] + pub fn tcmpl(&self) -> TCMPL_R { + TCMPL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel Suspend Interrupt Enable"] + #[inline(always)] + pub fn susp(&self) -> SUSP_R { + SUSP_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel Transfer Error Interrupt Enable"] + #[inline(always)] + pub fn terr(&mut self) -> TERR_W { + TERR_W { w: self } + } + #[doc = "Bit 1 - Channel Transfer Complete Interrupt Enable"] + #[inline(always)] + pub fn tcmpl(&mut self) -> TCMPL_W { + TCMPL_W { w: self } + } + #[doc = "Bit 2 - Channel Suspend Interrupt Enable"] + #[inline(always)] + pub fn susp(&mut self) -> SUSP_W { + SUSP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chintenclr](index.html) module"] +pub struct CHINTENCLR_SPEC; +impl crate::RegisterSpec for CHINTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [chintenclr::R](R) reader structure"] +impl crate::Readable for CHINTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chintenclr::W](W) writer structure"] +impl crate::Writable for CHINTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHINTENCLR to value 0"] +impl crate::Resettable for CHINTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/dmac/chintenset.rs b/pac/atsamc20n/src/dmac/chintenset.rs new file mode 100644 index 000000000000..2e7daef20a6f --- /dev/null +++ b/pac/atsamc20n/src/dmac/chintenset.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CHINTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHINTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TERR` reader - Channel Transfer Error Interrupt Enable"] +pub struct TERR_R(crate::FieldReader); +impl TERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TERR` writer - Channel Transfer Error Interrupt Enable"] +pub struct TERR_W<'a> { + w: &'a mut W, +} +impl<'a> TERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TCMPL` reader - Channel Transfer Complete Interrupt Enable"] +pub struct TCMPL_R(crate::FieldReader); +impl TCMPL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCMPL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCMPL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCMPL` writer - Channel Transfer Complete Interrupt Enable"] +pub struct TCMPL_W<'a> { + w: &'a mut W, +} +impl<'a> TCMPL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SUSP` reader - Channel Suspend Interrupt Enable"] +pub struct SUSP_R(crate::FieldReader); +impl SUSP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SUSP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SUSP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SUSP` writer - Channel Suspend Interrupt Enable"] +pub struct SUSP_W<'a> { + w: &'a mut W, +} +impl<'a> SUSP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Channel Transfer Error Interrupt Enable"] + #[inline(always)] + pub fn terr(&self) -> TERR_R { + TERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel Transfer Complete Interrupt Enable"] + #[inline(always)] + pub fn tcmpl(&self) -> TCMPL_R { + TCMPL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel Suspend Interrupt Enable"] + #[inline(always)] + pub fn susp(&self) -> SUSP_R { + SUSP_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel Transfer Error Interrupt Enable"] + #[inline(always)] + pub fn terr(&mut self) -> TERR_W { + TERR_W { w: self } + } + #[doc = "Bit 1 - Channel Transfer Complete Interrupt Enable"] + #[inline(always)] + pub fn tcmpl(&mut self) -> TCMPL_W { + TCMPL_W { w: self } + } + #[doc = "Bit 2 - Channel Suspend Interrupt Enable"] + #[inline(always)] + pub fn susp(&mut self) -> SUSP_W { + SUSP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chintenset](index.html) module"] +pub struct CHINTENSET_SPEC; +impl crate::RegisterSpec for CHINTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [chintenset::R](R) reader structure"] +impl crate::Readable for CHINTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chintenset::W](W) writer structure"] +impl crate::Writable for CHINTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHINTENSET to value 0"] +impl crate::Resettable for CHINTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/dmac/chintflag.rs b/pac/atsamc20n/src/dmac/chintflag.rs new file mode 100644 index 000000000000..4e61d6510c30 --- /dev/null +++ b/pac/atsamc20n/src/dmac/chintflag.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CHINTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHINTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TERR` reader - Channel Transfer Error"] +pub struct TERR_R(crate::FieldReader); +impl TERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TERR` writer - Channel Transfer Error"] +pub struct TERR_W<'a> { + w: &'a mut W, +} +impl<'a> TERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TCMPL` reader - Channel Transfer Complete"] +pub struct TCMPL_R(crate::FieldReader); +impl TCMPL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCMPL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCMPL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCMPL` writer - Channel Transfer Complete"] +pub struct TCMPL_W<'a> { + w: &'a mut W, +} +impl<'a> TCMPL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SUSP` reader - Channel Suspend"] +pub struct SUSP_R(crate::FieldReader); +impl SUSP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SUSP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SUSP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SUSP` writer - Channel Suspend"] +pub struct SUSP_W<'a> { + w: &'a mut W, +} +impl<'a> SUSP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Channel Transfer Error"] + #[inline(always)] + pub fn terr(&self) -> TERR_R { + TERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel Transfer Complete"] + #[inline(always)] + pub fn tcmpl(&self) -> TCMPL_R { + TCMPL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel Suspend"] + #[inline(always)] + pub fn susp(&self) -> SUSP_R { + SUSP_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel Transfer Error"] + #[inline(always)] + pub fn terr(&mut self) -> TERR_W { + TERR_W { w: self } + } + #[doc = "Bit 1 - Channel Transfer Complete"] + #[inline(always)] + pub fn tcmpl(&mut self) -> TCMPL_W { + TCMPL_W { w: self } + } + #[doc = "Bit 2 - Channel Suspend"] + #[inline(always)] + pub fn susp(&mut self) -> SUSP_W { + SUSP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chintflag](index.html) module"] +pub struct CHINTFLAG_SPEC; +impl crate::RegisterSpec for CHINTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [chintflag::R](R) reader structure"] +impl crate::Readable for CHINTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chintflag::W](W) writer structure"] +impl crate::Writable for CHINTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHINTFLAG to value 0"] +impl crate::Resettable for CHINTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/dmac/chstatus.rs b/pac/atsamc20n/src/dmac/chstatus.rs new file mode 100644 index 000000000000..98a84345d4f7 --- /dev/null +++ b/pac/atsamc20n/src/dmac/chstatus.rs @@ -0,0 +1,93 @@ +#[doc = "Register `CHSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PEND` reader - Channel Pending"] +pub struct PEND_R(crate::FieldReader); +impl PEND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSY` reader - Channel Busy"] +pub struct BUSY_R(crate::FieldReader); +impl BUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FERR` reader - Channel Fetch Error"] +pub struct FERR_R(crate::FieldReader); +impl FERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Channel Pending"] + #[inline(always)] + pub fn pend(&self) -> PEND_R { + PEND_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel Busy"] + #[inline(always)] + pub fn busy(&self) -> BUSY_R { + BUSY_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel Fetch Error"] + #[inline(always)] + pub fn ferr(&self) -> FERR_R { + FERR_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +#[doc = "Channel Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chstatus](index.html) module"] +pub struct CHSTATUS_SPEC; +impl crate::RegisterSpec for CHSTATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [chstatus::R](R) reader structure"] +impl crate::Readable for CHSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CHSTATUS to value 0"] +impl crate::Resettable for CHSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/dmac/crcchksum.rs b/pac/atsamc20n/src/dmac/crcchksum.rs new file mode 100644 index 000000000000..89eb5b38a093 --- /dev/null +++ b/pac/atsamc20n/src/dmac/crcchksum.rs @@ -0,0 +1,103 @@ +#[doc = "Register `CRCCHKSUM` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CRCCHKSUM` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CRCCHKSUM` reader - CRC Checksum"] +pub struct CRCCHKSUM_R(crate::FieldReader); +impl CRCCHKSUM_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CRCCHKSUM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CRCCHKSUM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCCHKSUM` writer - CRC Checksum"] +pub struct CRCCHKSUM_W<'a> { + w: &'a mut W, +} +impl<'a> CRCCHKSUM_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - CRC Checksum"] + #[inline(always)] + pub fn crcchksum(&self) -> CRCCHKSUM_R { + CRCCHKSUM_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - CRC Checksum"] + #[inline(always)] + pub fn crcchksum(&mut self) -> CRCCHKSUM_W { + CRCCHKSUM_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CRC Checksum\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [crcchksum](index.html) module"] +pub struct CRCCHKSUM_SPEC; +impl crate::RegisterSpec for CRCCHKSUM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [crcchksum::R](R) reader structure"] +impl crate::Readable for CRCCHKSUM_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [crcchksum::W](W) writer structure"] +impl crate::Writable for CRCCHKSUM_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CRCCHKSUM to value 0"] +impl crate::Resettable for CRCCHKSUM_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/dmac/crcctrl.rs b/pac/atsamc20n/src/dmac/crcctrl.rs new file mode 100644 index 000000000000..b8daf7b8259d --- /dev/null +++ b/pac/atsamc20n/src/dmac/crcctrl.rs @@ -0,0 +1,337 @@ +#[doc = "Register `CRCCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CRCCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "CRC Beat Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CRCBEATSIZE_A { + #[doc = "0: 8-bit bus transfer"] + BYTE = 0, + #[doc = "1: 16-bit bus transfer"] + HWORD = 1, + #[doc = "2: 32-bit bus transfer"] + WORD = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CRCBEATSIZE_A) -> Self { + variant as _ + } +} +#[doc = "Field `CRCBEATSIZE` reader - CRC Beat Size"] +pub struct CRCBEATSIZE_R(crate::FieldReader); +impl CRCBEATSIZE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CRCBEATSIZE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CRCBEATSIZE_A::BYTE), + 1 => Some(CRCBEATSIZE_A::HWORD), + 2 => Some(CRCBEATSIZE_A::WORD), + _ => None, + } + } + #[doc = "Checks if the value of the field is `BYTE`"] + #[inline(always)] + pub fn is_byte(&self) -> bool { + **self == CRCBEATSIZE_A::BYTE + } + #[doc = "Checks if the value of the field is `HWORD`"] + #[inline(always)] + pub fn is_hword(&self) -> bool { + **self == CRCBEATSIZE_A::HWORD + } + #[doc = "Checks if the value of the field is `WORD`"] + #[inline(always)] + pub fn is_word(&self) -> bool { + **self == CRCBEATSIZE_A::WORD + } +} +impl core::ops::Deref for CRCBEATSIZE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCBEATSIZE` writer - CRC Beat Size"] +pub struct CRCBEATSIZE_W<'a> { + w: &'a mut W, +} +impl<'a> CRCBEATSIZE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CRCBEATSIZE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8-bit bus transfer"] + #[inline(always)] + pub fn byte(self) -> &'a mut W { + self.variant(CRCBEATSIZE_A::BYTE) + } + #[doc = "16-bit bus transfer"] + #[inline(always)] + pub fn hword(self) -> &'a mut W { + self.variant(CRCBEATSIZE_A::HWORD) + } + #[doc = "32-bit bus transfer"] + #[inline(always)] + pub fn word(self) -> &'a mut W { + self.variant(CRCBEATSIZE_A::WORD) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u16 & 0x03); + self.w + } +} +#[doc = "CRC Polynomial Type\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CRCPOLY_A { + #[doc = "0: CRC-16 (CRC-CCITT)"] + CRC16 = 0, + #[doc = "1: CRC32 (IEEE 802.3)"] + CRC32 = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CRCPOLY_A) -> Self { + variant as _ + } +} +#[doc = "Field `CRCPOLY` reader - CRC Polynomial Type"] +pub struct CRCPOLY_R(crate::FieldReader); +impl CRCPOLY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CRCPOLY_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CRCPOLY_A::CRC16), + 1 => Some(CRCPOLY_A::CRC32), + _ => None, + } + } + #[doc = "Checks if the value of the field is `CRC16`"] + #[inline(always)] + pub fn is_crc16(&self) -> bool { + **self == CRCPOLY_A::CRC16 + } + #[doc = "Checks if the value of the field is `CRC32`"] + #[inline(always)] + pub fn is_crc32(&self) -> bool { + **self == CRCPOLY_A::CRC32 + } +} +impl core::ops::Deref for CRCPOLY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCPOLY` writer - CRC Polynomial Type"] +pub struct CRCPOLY_W<'a> { + w: &'a mut W, +} +impl<'a> CRCPOLY_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CRCPOLY_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "CRC-16 (CRC-CCITT)"] + #[inline(always)] + pub fn crc16(self) -> &'a mut W { + self.variant(CRCPOLY_A::CRC16) + } + #[doc = "CRC32 (IEEE 802.3)"] + #[inline(always)] + pub fn crc32(self) -> &'a mut W { + self.variant(CRCPOLY_A::CRC32) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u16 & 0x03) << 2); + self.w + } +} +#[doc = "CRC Input Source\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CRCSRC_A { + #[doc = "0: No action"] + NOACT = 0, + #[doc = "1: I/O interface"] + IO = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CRCSRC_A) -> Self { + variant as _ + } +} +#[doc = "Field `CRCSRC` reader - CRC Input Source"] +pub struct CRCSRC_R(crate::FieldReader); +impl CRCSRC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CRCSRC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CRCSRC_A::NOACT), + 1 => Some(CRCSRC_A::IO), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NOACT`"] + #[inline(always)] + pub fn is_noact(&self) -> bool { + **self == CRCSRC_A::NOACT + } + #[doc = "Checks if the value of the field is `IO`"] + #[inline(always)] + pub fn is_io(&self) -> bool { + **self == CRCSRC_A::IO + } +} +impl core::ops::Deref for CRCSRC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCSRC` writer - CRC Input Source"] +pub struct CRCSRC_W<'a> { + w: &'a mut W, +} +impl<'a> CRCSRC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CRCSRC_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn noact(self) -> &'a mut W { + self.variant(CRCSRC_A::NOACT) + } + #[doc = "I/O interface"] + #[inline(always)] + pub fn io(self) -> &'a mut W { + self.variant(CRCSRC_A::IO) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 8)) | ((value as u16 & 0x3f) << 8); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - CRC Beat Size"] + #[inline(always)] + pub fn crcbeatsize(&self) -> CRCBEATSIZE_R { + CRCBEATSIZE_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bits 2:3 - CRC Polynomial Type"] + #[inline(always)] + pub fn crcpoly(&self) -> CRCPOLY_R { + CRCPOLY_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bits 8:13 - CRC Input Source"] + #[inline(always)] + pub fn crcsrc(&self) -> CRCSRC_R { + CRCSRC_R::new(((self.bits >> 8) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - CRC Beat Size"] + #[inline(always)] + pub fn crcbeatsize(&mut self) -> CRCBEATSIZE_W { + CRCBEATSIZE_W { w: self } + } + #[doc = "Bits 2:3 - CRC Polynomial Type"] + #[inline(always)] + pub fn crcpoly(&mut self) -> CRCPOLY_W { + CRCPOLY_W { w: self } + } + #[doc = "Bits 8:13 - CRC Input Source"] + #[inline(always)] + pub fn crcsrc(&mut self) -> CRCSRC_W { + CRCSRC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CRC Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [crcctrl](index.html) module"] +pub struct CRCCTRL_SPEC; +impl crate::RegisterSpec for CRCCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [crcctrl::R](R) reader structure"] +impl crate::Readable for CRCCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [crcctrl::W](W) writer structure"] +impl crate::Writable for CRCCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CRCCTRL to value 0"] +impl crate::Resettable for CRCCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/dmac/crcdatain.rs b/pac/atsamc20n/src/dmac/crcdatain.rs new file mode 100644 index 000000000000..ca0879a12136 --- /dev/null +++ b/pac/atsamc20n/src/dmac/crcdatain.rs @@ -0,0 +1,103 @@ +#[doc = "Register `CRCDATAIN` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CRCDATAIN` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CRCDATAIN` reader - CRC Data Input"] +pub struct CRCDATAIN_R(crate::FieldReader); +impl CRCDATAIN_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CRCDATAIN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CRCDATAIN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCDATAIN` writer - CRC Data Input"] +pub struct CRCDATAIN_W<'a> { + w: &'a mut W, +} +impl<'a> CRCDATAIN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - CRC Data Input"] + #[inline(always)] + pub fn crcdatain(&self) -> CRCDATAIN_R { + CRCDATAIN_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - CRC Data Input"] + #[inline(always)] + pub fn crcdatain(&mut self) -> CRCDATAIN_W { + CRCDATAIN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CRC Data Input\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [crcdatain](index.html) module"] +pub struct CRCDATAIN_SPEC; +impl crate::RegisterSpec for CRCDATAIN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [crcdatain::R](R) reader structure"] +impl crate::Readable for CRCDATAIN_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [crcdatain::W](W) writer structure"] +impl crate::Writable for CRCDATAIN_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CRCDATAIN to value 0"] +impl crate::Resettable for CRCDATAIN_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/dmac/crcstatus.rs b/pac/atsamc20n/src/dmac/crcstatus.rs new file mode 100644 index 000000000000..a132e9d5cd03 --- /dev/null +++ b/pac/atsamc20n/src/dmac/crcstatus.rs @@ -0,0 +1,160 @@ +#[doc = "Register `CRCSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CRCSTATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CRCBUSY` reader - CRC Module Busy"] +pub struct CRCBUSY_R(crate::FieldReader); +impl CRCBUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CRCBUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CRCBUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCBUSY` writer - CRC Module Busy"] +pub struct CRCBUSY_W<'a> { + w: &'a mut W, +} +impl<'a> CRCBUSY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `CRCZERO` reader - CRC Zero"] +pub struct CRCZERO_R(crate::FieldReader); +impl CRCZERO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CRCZERO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CRCZERO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCZERO` writer - CRC Zero"] +pub struct CRCZERO_W<'a> { + w: &'a mut W, +} +impl<'a> CRCZERO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - CRC Module Busy"] + #[inline(always)] + pub fn crcbusy(&self) -> CRCBUSY_R { + CRCBUSY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - CRC Zero"] + #[inline(always)] + pub fn crczero(&self) -> CRCZERO_R { + CRCZERO_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - CRC Module Busy"] + #[inline(always)] + pub fn crcbusy(&mut self) -> CRCBUSY_W { + CRCBUSY_W { w: self } + } + #[doc = "Bit 1 - CRC Zero"] + #[inline(always)] + pub fn crczero(&mut self) -> CRCZERO_W { + CRCZERO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CRC Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [crcstatus](index.html) module"] +pub struct CRCSTATUS_SPEC; +impl crate::RegisterSpec for CRCSTATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [crcstatus::R](R) reader structure"] +impl crate::Readable for CRCSTATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [crcstatus::W](W) writer structure"] +impl crate::Writable for CRCSTATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CRCSTATUS to value 0"] +impl crate::Resettable for CRCSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/dmac/ctrl.rs b/pac/atsamc20n/src/dmac/ctrl.rs new file mode 100644 index 000000000000..fabae9d82a6c --- /dev/null +++ b/pac/atsamc20n/src/dmac/ctrl.rs @@ -0,0 +1,395 @@ +#[doc = "Register `CTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `DMAENABLE` reader - DMA Enable"] +pub struct DMAENABLE_R(crate::FieldReader); +impl DMAENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DMAENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DMAENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DMAENABLE` writer - DMA Enable"] +pub struct DMAENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> DMAENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CRCENABLE` reader - CRC Enable"] +pub struct CRCENABLE_R(crate::FieldReader); +impl CRCENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CRCENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CRCENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCENABLE` writer - CRC Enable"] +pub struct CRCENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> CRCENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `LVLEN0` reader - Priority Level 0 Enable"] +pub struct LVLEN0_R(crate::FieldReader); +impl LVLEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LVLEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLEN0` writer - Priority Level 0 Enable"] +pub struct LVLEN0_W<'a> { + w: &'a mut W, +} +impl<'a> LVLEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `LVLEN1` reader - Priority Level 1 Enable"] +pub struct LVLEN1_R(crate::FieldReader); +impl LVLEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LVLEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLEN1` writer - Priority Level 1 Enable"] +pub struct LVLEN1_W<'a> { + w: &'a mut W, +} +impl<'a> LVLEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `LVLEN2` reader - Priority Level 2 Enable"] +pub struct LVLEN2_R(crate::FieldReader); +impl LVLEN2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LVLEN2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEN2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLEN2` writer - Priority Level 2 Enable"] +pub struct LVLEN2_W<'a> { + w: &'a mut W, +} +impl<'a> LVLEN2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u16 & 0x01) << 10); + self.w + } +} +#[doc = "Field `LVLEN3` reader - Priority Level 3 Enable"] +pub struct LVLEN3_R(crate::FieldReader); +impl LVLEN3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LVLEN3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEN3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLEN3` writer - Priority Level 3 Enable"] +pub struct LVLEN3_W<'a> { + w: &'a mut W, +} +impl<'a> LVLEN3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u16 & 0x01) << 11); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - DMA Enable"] + #[inline(always)] + pub fn dmaenable(&self) -> DMAENABLE_R { + DMAENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - CRC Enable"] + #[inline(always)] + pub fn crcenable(&self) -> CRCENABLE_R { + CRCENABLE_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 8 - Priority Level 0 Enable"] + #[inline(always)] + pub fn lvlen0(&self) -> LVLEN0_R { + LVLEN0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Priority Level 1 Enable"] + #[inline(always)] + pub fn lvlen1(&self) -> LVLEN1_R { + LVLEN1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Priority Level 2 Enable"] + #[inline(always)] + pub fn lvlen2(&self) -> LVLEN2_R { + LVLEN2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Priority Level 3 Enable"] + #[inline(always)] + pub fn lvlen3(&self) -> LVLEN3_R { + LVLEN3_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - DMA Enable"] + #[inline(always)] + pub fn dmaenable(&mut self) -> DMAENABLE_W { + DMAENABLE_W { w: self } + } + #[doc = "Bit 2 - CRC Enable"] + #[inline(always)] + pub fn crcenable(&mut self) -> CRCENABLE_W { + CRCENABLE_W { w: self } + } + #[doc = "Bit 8 - Priority Level 0 Enable"] + #[inline(always)] + pub fn lvlen0(&mut self) -> LVLEN0_W { + LVLEN0_W { w: self } + } + #[doc = "Bit 9 - Priority Level 1 Enable"] + #[inline(always)] + pub fn lvlen1(&mut self) -> LVLEN1_W { + LVLEN1_W { w: self } + } + #[doc = "Bit 10 - Priority Level 2 Enable"] + #[inline(always)] + pub fn lvlen2(&mut self) -> LVLEN2_W { + LVLEN2_W { w: self } + } + #[doc = "Bit 11 - Priority Level 3 Enable"] + #[inline(always)] + pub fn lvlen3(&mut self) -> LVLEN3_W { + LVLEN3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"] +pub struct CTRL_SPEC; +impl crate::RegisterSpec for CTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrl::R](R) reader structure"] +impl crate::Readable for CTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"] +impl crate::Writable for CTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/dmac/dbgctrl.rs b/pac/atsamc20n/src/dmac/dbgctrl.rs new file mode 100644 index 000000000000..53636eb2b339 --- /dev/null +++ b/pac/atsamc20n/src/dmac/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Debug Run"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Debug Run"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/dmac/intpend.rs b/pac/atsamc20n/src/dmac/intpend.rs new file mode 100644 index 000000000000..a107c4c32e66 --- /dev/null +++ b/pac/atsamc20n/src/dmac/intpend.rs @@ -0,0 +1,385 @@ +#[doc = "Register `INTPEND` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTPEND` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ID` reader - Channel ID"] +pub struct ID_R(crate::FieldReader); +impl ID_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ID_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ID_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ID` writer - Channel ID"] +pub struct ID_W<'a> { + w: &'a mut W, +} +impl<'a> ID_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u16 & 0x0f); + self.w + } +} +#[doc = "Field `TERR` reader - Transfer Error"] +pub struct TERR_R(crate::FieldReader); +impl TERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TERR` writer - Transfer Error"] +pub struct TERR_W<'a> { + w: &'a mut W, +} +impl<'a> TERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `TCMPL` reader - Transfer Complete"] +pub struct TCMPL_R(crate::FieldReader); +impl TCMPL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCMPL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCMPL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCMPL` writer - Transfer Complete"] +pub struct TCMPL_W<'a> { + w: &'a mut W, +} +impl<'a> TCMPL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `SUSP` reader - Channel Suspend"] +pub struct SUSP_R(crate::FieldReader); +impl SUSP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SUSP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SUSP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SUSP` writer - Channel Suspend"] +pub struct SUSP_W<'a> { + w: &'a mut W, +} +impl<'a> SUSP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u16 & 0x01) << 10); + self.w + } +} +#[doc = "Field `FERR` reader - Fetch Error"] +pub struct FERR_R(crate::FieldReader); +impl FERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FERR` writer - Fetch Error"] +pub struct FERR_W<'a> { + w: &'a mut W, +} +impl<'a> FERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u16 & 0x01) << 13); + self.w + } +} +#[doc = "Field `BUSY` reader - Busy"] +pub struct BUSY_R(crate::FieldReader); +impl BUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSY` writer - Busy"] +pub struct BUSY_W<'a> { + w: &'a mut W, +} +impl<'a> BUSY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u16 & 0x01) << 14); + self.w + } +} +#[doc = "Field `PEND` reader - Pending"] +pub struct PEND_R(crate::FieldReader); +impl PEND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEND` writer - Pending"] +pub struct PEND_W<'a> { + w: &'a mut W, +} +impl<'a> PEND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Channel ID"] + #[inline(always)] + pub fn id(&self) -> ID_R { + ID_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 8 - Transfer Error"] + #[inline(always)] + pub fn terr(&self) -> TERR_R { + TERR_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Transfer Complete"] + #[inline(always)] + pub fn tcmpl(&self) -> TCMPL_R { + TCMPL_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Channel Suspend"] + #[inline(always)] + pub fn susp(&self) -> SUSP_R { + SUSP_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 13 - Fetch Error"] + #[inline(always)] + pub fn ferr(&self) -> FERR_R { + FERR_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Busy"] + #[inline(always)] + pub fn busy(&self) -> BUSY_R { + BUSY_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Pending"] + #[inline(always)] + pub fn pend(&self) -> PEND_R { + PEND_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Channel ID"] + #[inline(always)] + pub fn id(&mut self) -> ID_W { + ID_W { w: self } + } + #[doc = "Bit 8 - Transfer Error"] + #[inline(always)] + pub fn terr(&mut self) -> TERR_W { + TERR_W { w: self } + } + #[doc = "Bit 9 - Transfer Complete"] + #[inline(always)] + pub fn tcmpl(&mut self) -> TCMPL_W { + TCMPL_W { w: self } + } + #[doc = "Bit 10 - Channel Suspend"] + #[inline(always)] + pub fn susp(&mut self) -> SUSP_W { + SUSP_W { w: self } + } + #[doc = "Bit 13 - Fetch Error"] + #[inline(always)] + pub fn ferr(&mut self) -> FERR_W { + FERR_W { w: self } + } + #[doc = "Bit 14 - Busy"] + #[inline(always)] + pub fn busy(&mut self) -> BUSY_W { + BUSY_W { w: self } + } + #[doc = "Bit 15 - Pending"] + #[inline(always)] + pub fn pend(&mut self) -> PEND_W { + PEND_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Pending\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intpend](index.html) module"] +pub struct INTPEND_SPEC; +impl crate::RegisterSpec for INTPEND_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intpend::R](R) reader structure"] +impl crate::Readable for INTPEND_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intpend::W](W) writer structure"] +impl crate::Writable for INTPEND_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTPEND to value 0"] +impl crate::Resettable for INTPEND_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/dmac/intstatus.rs b/pac/atsamc20n/src/dmac/intstatus.rs new file mode 100644 index 000000000000..74a836f4a2ff --- /dev/null +++ b/pac/atsamc20n/src/dmac/intstatus.rs @@ -0,0 +1,273 @@ +#[doc = "Register `INTSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `CHINT0` reader - Channel 0 Pending Interrupt"] +pub struct CHINT0_R(crate::FieldReader); +impl CHINT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT1` reader - Channel 1 Pending Interrupt"] +pub struct CHINT1_R(crate::FieldReader); +impl CHINT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT2` reader - Channel 2 Pending Interrupt"] +pub struct CHINT2_R(crate::FieldReader); +impl CHINT2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT3` reader - Channel 3 Pending Interrupt"] +pub struct CHINT3_R(crate::FieldReader); +impl CHINT3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT4` reader - Channel 4 Pending Interrupt"] +pub struct CHINT4_R(crate::FieldReader); +impl CHINT4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT5` reader - Channel 5 Pending Interrupt"] +pub struct CHINT5_R(crate::FieldReader); +impl CHINT5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT6` reader - Channel 6 Pending Interrupt"] +pub struct CHINT6_R(crate::FieldReader); +impl CHINT6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT7` reader - Channel 7 Pending Interrupt"] +pub struct CHINT7_R(crate::FieldReader); +impl CHINT7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT8` reader - Channel 8 Pending Interrupt"] +pub struct CHINT8_R(crate::FieldReader); +impl CHINT8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT9` reader - Channel 9 Pending Interrupt"] +pub struct CHINT9_R(crate::FieldReader); +impl CHINT9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT10` reader - Channel 10 Pending Interrupt"] +pub struct CHINT10_R(crate::FieldReader); +impl CHINT10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT11` reader - Channel 11 Pending Interrupt"] +pub struct CHINT11_R(crate::FieldReader); +impl CHINT11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Channel 0 Pending Interrupt"] + #[inline(always)] + pub fn chint0(&self) -> CHINT0_R { + CHINT0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel 1 Pending Interrupt"] + #[inline(always)] + pub fn chint1(&self) -> CHINT1_R { + CHINT1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel 2 Pending Interrupt"] + #[inline(always)] + pub fn chint2(&self) -> CHINT2_R { + CHINT2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Channel 3 Pending Interrupt"] + #[inline(always)] + pub fn chint3(&self) -> CHINT3_R { + CHINT3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Channel 4 Pending Interrupt"] + #[inline(always)] + pub fn chint4(&self) -> CHINT4_R { + CHINT4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Channel 5 Pending Interrupt"] + #[inline(always)] + pub fn chint5(&self) -> CHINT5_R { + CHINT5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Channel 6 Pending Interrupt"] + #[inline(always)] + pub fn chint6(&self) -> CHINT6_R { + CHINT6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Channel 7 Pending Interrupt"] + #[inline(always)] + pub fn chint7(&self) -> CHINT7_R { + CHINT7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Channel 8 Pending Interrupt"] + #[inline(always)] + pub fn chint8(&self) -> CHINT8_R { + CHINT8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Channel 9 Pending Interrupt"] + #[inline(always)] + pub fn chint9(&self) -> CHINT9_R { + CHINT9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Channel 10 Pending Interrupt"] + #[inline(always)] + pub fn chint10(&self) -> CHINT10_R { + CHINT10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Channel 11 Pending Interrupt"] + #[inline(always)] + pub fn chint11(&self) -> CHINT11_R { + CHINT11_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +#[doc = "Interrupt Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intstatus](index.html) module"] +pub struct INTSTATUS_SPEC; +impl crate::RegisterSpec for INTSTATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intstatus::R](R) reader structure"] +impl crate::Readable for INTSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets INTSTATUS to value 0"] +impl crate::Resettable for INTSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/dmac/pendch.rs b/pac/atsamc20n/src/dmac/pendch.rs new file mode 100644 index 000000000000..8bb68ff8fa5d --- /dev/null +++ b/pac/atsamc20n/src/dmac/pendch.rs @@ -0,0 +1,273 @@ +#[doc = "Register `PENDCH` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PENDCH0` reader - Pending Channel 0"] +pub struct PENDCH0_R(crate::FieldReader); +impl PENDCH0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH1` reader - Pending Channel 1"] +pub struct PENDCH1_R(crate::FieldReader); +impl PENDCH1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH2` reader - Pending Channel 2"] +pub struct PENDCH2_R(crate::FieldReader); +impl PENDCH2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH3` reader - Pending Channel 3"] +pub struct PENDCH3_R(crate::FieldReader); +impl PENDCH3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH4` reader - Pending Channel 4"] +pub struct PENDCH4_R(crate::FieldReader); +impl PENDCH4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH5` reader - Pending Channel 5"] +pub struct PENDCH5_R(crate::FieldReader); +impl PENDCH5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH6` reader - Pending Channel 6"] +pub struct PENDCH6_R(crate::FieldReader); +impl PENDCH6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH7` reader - Pending Channel 7"] +pub struct PENDCH7_R(crate::FieldReader); +impl PENDCH7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH8` reader - Pending Channel 8"] +pub struct PENDCH8_R(crate::FieldReader); +impl PENDCH8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH9` reader - Pending Channel 9"] +pub struct PENDCH9_R(crate::FieldReader); +impl PENDCH9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH10` reader - Pending Channel 10"] +pub struct PENDCH10_R(crate::FieldReader); +impl PENDCH10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH11` reader - Pending Channel 11"] +pub struct PENDCH11_R(crate::FieldReader); +impl PENDCH11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Pending Channel 0"] + #[inline(always)] + pub fn pendch0(&self) -> PENDCH0_R { + PENDCH0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Pending Channel 1"] + #[inline(always)] + pub fn pendch1(&self) -> PENDCH1_R { + PENDCH1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Pending Channel 2"] + #[inline(always)] + pub fn pendch2(&self) -> PENDCH2_R { + PENDCH2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Pending Channel 3"] + #[inline(always)] + pub fn pendch3(&self) -> PENDCH3_R { + PENDCH3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Pending Channel 4"] + #[inline(always)] + pub fn pendch4(&self) -> PENDCH4_R { + PENDCH4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Pending Channel 5"] + #[inline(always)] + pub fn pendch5(&self) -> PENDCH5_R { + PENDCH5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Pending Channel 6"] + #[inline(always)] + pub fn pendch6(&self) -> PENDCH6_R { + PENDCH6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Pending Channel 7"] + #[inline(always)] + pub fn pendch7(&self) -> PENDCH7_R { + PENDCH7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Pending Channel 8"] + #[inline(always)] + pub fn pendch8(&self) -> PENDCH8_R { + PENDCH8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Pending Channel 9"] + #[inline(always)] + pub fn pendch9(&self) -> PENDCH9_R { + PENDCH9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Pending Channel 10"] + #[inline(always)] + pub fn pendch10(&self) -> PENDCH10_R { + PENDCH10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Pending Channel 11"] + #[inline(always)] + pub fn pendch11(&self) -> PENDCH11_R { + PENDCH11_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +#[doc = "Pending Channels\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pendch](index.html) module"] +pub struct PENDCH_SPEC; +impl crate::RegisterSpec for PENDCH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pendch::R](R) reader structure"] +impl crate::Readable for PENDCH_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PENDCH to value 0"] +impl crate::Resettable for PENDCH_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/dmac/prictrl0.rs b/pac/atsamc20n/src/dmac/prictrl0.rs new file mode 100644 index 000000000000..618e54ad23f2 --- /dev/null +++ b/pac/atsamc20n/src/dmac/prictrl0.rs @@ -0,0 +1,449 @@ +#[doc = "Register `PRICTRL0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PRICTRL0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `LVLPRI0` reader - Level 0 Channel Priority Number"] +pub struct LVLPRI0_R(crate::FieldReader); +impl LVLPRI0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LVLPRI0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLPRI0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLPRI0` writer - Level 0 Channel Priority Number"] +pub struct LVLPRI0_W<'a> { + w: &'a mut W, +} +impl<'a> LVLPRI0_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Level 0 Round-Robin Scheduling Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RRLVLEN0_A { + #[doc = "0: Static arbitration scheme for channels with level 3 priority"] + STATIC_LVL = 0, + #[doc = "1: Round-robin arbitration scheme for channels with level 3 priority"] + ROUND_ROBIN_LVL = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RRLVLEN0_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RRLVLEN0` reader - Level 0 Round-Robin Scheduling Enable"] +pub struct RRLVLEN0_R(crate::FieldReader); +impl RRLVLEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RRLVLEN0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RRLVLEN0_A { + match self.bits { + false => RRLVLEN0_A::STATIC_LVL, + true => RRLVLEN0_A::ROUND_ROBIN_LVL, + } + } + #[doc = "Checks if the value of the field is `STATIC_LVL`"] + #[inline(always)] + pub fn is_static_lvl(&self) -> bool { + **self == RRLVLEN0_A::STATIC_LVL + } + #[doc = "Checks if the value of the field is `ROUND_ROBIN_LVL`"] + #[inline(always)] + pub fn is_round_robin_lvl(&self) -> bool { + **self == RRLVLEN0_A::ROUND_ROBIN_LVL + } +} +impl core::ops::Deref for RRLVLEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RRLVLEN0` writer - Level 0 Round-Robin Scheduling Enable"] +pub struct RRLVLEN0_W<'a> { + w: &'a mut W, +} +impl<'a> RRLVLEN0_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RRLVLEN0_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Static arbitration scheme for channels with level 3 priority"] + #[inline(always)] + pub fn static_lvl(self) -> &'a mut W { + self.variant(RRLVLEN0_A::STATIC_LVL) + } + #[doc = "Round-robin arbitration scheme for channels with level 3 priority"] + #[inline(always)] + pub fn round_robin_lvl(self) -> &'a mut W { + self.variant(RRLVLEN0_A::ROUND_ROBIN_LVL) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `LVLPRI1` reader - Level 1 Channel Priority Number"] +pub struct LVLPRI1_R(crate::FieldReader); +impl LVLPRI1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LVLPRI1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLPRI1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLPRI1` writer - Level 1 Channel Priority Number"] +pub struct LVLPRI1_W<'a> { + w: &'a mut W, +} +impl<'a> LVLPRI1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 8)) | ((value as u32 & 0x0f) << 8); + self.w + } +} +#[doc = "Field `RRLVLEN1` reader - Level 1 Round-Robin Scheduling Enable"] +pub struct RRLVLEN1_R(crate::FieldReader); +impl RRLVLEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RRLVLEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RRLVLEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RRLVLEN1` writer - Level 1 Round-Robin Scheduling Enable"] +pub struct RRLVLEN1_W<'a> { + w: &'a mut W, +} +impl<'a> RRLVLEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `LVLPRI2` reader - Level 2 Channel Priority Number"] +pub struct LVLPRI2_R(crate::FieldReader); +impl LVLPRI2_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LVLPRI2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLPRI2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLPRI2` writer - Level 2 Channel Priority Number"] +pub struct LVLPRI2_W<'a> { + w: &'a mut W, +} +impl<'a> LVLPRI2_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 16)) | ((value as u32 & 0x0f) << 16); + self.w + } +} +#[doc = "Field `RRLVLEN2` reader - Level 2 Round-Robin Scheduling Enable"] +pub struct RRLVLEN2_R(crate::FieldReader); +impl RRLVLEN2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RRLVLEN2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RRLVLEN2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RRLVLEN2` writer - Level 2 Round-Robin Scheduling Enable"] +pub struct RRLVLEN2_W<'a> { + w: &'a mut W, +} +impl<'a> RRLVLEN2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `LVLPRI3` reader - Level 3 Channel Priority Number"] +pub struct LVLPRI3_R(crate::FieldReader); +impl LVLPRI3_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LVLPRI3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLPRI3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLPRI3` writer - Level 3 Channel Priority Number"] +pub struct LVLPRI3_W<'a> { + w: &'a mut W, +} +impl<'a> LVLPRI3_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Field `RRLVLEN3` reader - Level 3 Round-Robin Scheduling Enable"] +pub struct RRLVLEN3_R(crate::FieldReader); +impl RRLVLEN3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RRLVLEN3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RRLVLEN3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RRLVLEN3` writer - Level 3 Round-Robin Scheduling Enable"] +pub struct RRLVLEN3_W<'a> { + w: &'a mut W, +} +impl<'a> RRLVLEN3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Level 0 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri0(&self) -> LVLPRI0_R { + LVLPRI0_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 7 - Level 0 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen0(&self) -> RRLVLEN0_R { + RRLVLEN0_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:11 - Level 1 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri1(&self) -> LVLPRI1_R { + LVLPRI1_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 15 - Level 1 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen1(&self) -> RRLVLEN1_R { + RRLVLEN1_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:19 - Level 2 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri2(&self) -> LVLPRI2_R { + LVLPRI2_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 23 - Level 2 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen2(&self) -> RRLVLEN2_R { + RRLVLEN2_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bits 24:27 - Level 3 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri3(&self) -> LVLPRI3_R { + LVLPRI3_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 31 - Level 3 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen3(&self) -> RRLVLEN3_R { + RRLVLEN3_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Level 0 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri0(&mut self) -> LVLPRI0_W { + LVLPRI0_W { w: self } + } + #[doc = "Bit 7 - Level 0 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen0(&mut self) -> RRLVLEN0_W { + RRLVLEN0_W { w: self } + } + #[doc = "Bits 8:11 - Level 1 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri1(&mut self) -> LVLPRI1_W { + LVLPRI1_W { w: self } + } + #[doc = "Bit 15 - Level 1 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen1(&mut self) -> RRLVLEN1_W { + RRLVLEN1_W { w: self } + } + #[doc = "Bits 16:19 - Level 2 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri2(&mut self) -> LVLPRI2_W { + LVLPRI2_W { w: self } + } + #[doc = "Bit 23 - Level 2 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen2(&mut self) -> RRLVLEN2_W { + RRLVLEN2_W { w: self } + } + #[doc = "Bits 24:27 - Level 3 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri3(&mut self) -> LVLPRI3_W { + LVLPRI3_W { w: self } + } + #[doc = "Bit 31 - Level 3 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen3(&mut self) -> RRLVLEN3_W { + RRLVLEN3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Priority Control 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [prictrl0](index.html) module"] +pub struct PRICTRL0_SPEC; +impl crate::RegisterSpec for PRICTRL0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [prictrl0::R](R) reader structure"] +impl crate::Readable for PRICTRL0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [prictrl0::W](W) writer structure"] +impl crate::Writable for PRICTRL0_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PRICTRL0 to value 0"] +impl crate::Resettable for PRICTRL0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/dmac/qosctrl.rs b/pac/atsamc20n/src/dmac/qosctrl.rs new file mode 100644 index 000000000000..016fcaa221ef --- /dev/null +++ b/pac/atsamc20n/src/dmac/qosctrl.rs @@ -0,0 +1,402 @@ +#[doc = "Register `QOSCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `QOSCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Write-Back Quality of Service\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WRBQOS_A { + #[doc = "0: Background (no sensitive operation)"] + DISABLE = 0, + #[doc = "1: Sensitive Bandwidth"] + LOW = 1, + #[doc = "2: Sensitive Latency"] + MEDIUM = 2, + #[doc = "3: Critical Latency"] + HIGH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WRBQOS_A) -> Self { + variant as _ + } +} +#[doc = "Field `WRBQOS` reader - Write-Back Quality of Service"] +pub struct WRBQOS_R(crate::FieldReader); +impl WRBQOS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WRBQOS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> WRBQOS_A { + match self.bits { + 0 => WRBQOS_A::DISABLE, + 1 => WRBQOS_A::LOW, + 2 => WRBQOS_A::MEDIUM, + 3 => WRBQOS_A::HIGH, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == WRBQOS_A::DISABLE + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == WRBQOS_A::LOW + } + #[doc = "Checks if the value of the field is `MEDIUM`"] + #[inline(always)] + pub fn is_medium(&self) -> bool { + **self == WRBQOS_A::MEDIUM + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == WRBQOS_A::HIGH + } +} +impl core::ops::Deref for WRBQOS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WRBQOS` writer - Write-Back Quality of Service"] +pub struct WRBQOS_W<'a> { + w: &'a mut W, +} +impl<'a> WRBQOS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WRBQOS_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Background (no sensitive operation)"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(WRBQOS_A::DISABLE) + } + #[doc = "Sensitive Bandwidth"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(WRBQOS_A::LOW) + } + #[doc = "Sensitive Latency"] + #[inline(always)] + pub fn medium(self) -> &'a mut W { + self.variant(WRBQOS_A::MEDIUM) + } + #[doc = "Critical Latency"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(WRBQOS_A::HIGH) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u8 & 0x03); + self.w + } +} +#[doc = "Fetch Quality of Service\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FQOS_A { + #[doc = "0: Background (no sensitive operation)"] + DISABLE = 0, + #[doc = "1: Sensitive Bandwidth"] + LOW = 1, + #[doc = "2: Sensitive Latency"] + MEDIUM = 2, + #[doc = "3: Critical Latency"] + HIGH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FQOS_A) -> Self { + variant as _ + } +} +#[doc = "Field `FQOS` reader - Fetch Quality of Service"] +pub struct FQOS_R(crate::FieldReader); +impl FQOS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FQOS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FQOS_A { + match self.bits { + 0 => FQOS_A::DISABLE, + 1 => FQOS_A::LOW, + 2 => FQOS_A::MEDIUM, + 3 => FQOS_A::HIGH, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == FQOS_A::DISABLE + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == FQOS_A::LOW + } + #[doc = "Checks if the value of the field is `MEDIUM`"] + #[inline(always)] + pub fn is_medium(&self) -> bool { + **self == FQOS_A::MEDIUM + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == FQOS_A::HIGH + } +} +impl core::ops::Deref for FQOS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FQOS` writer - Fetch Quality of Service"] +pub struct FQOS_W<'a> { + w: &'a mut W, +} +impl<'a> FQOS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FQOS_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Background (no sensitive operation)"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(FQOS_A::DISABLE) + } + #[doc = "Sensitive Bandwidth"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(FQOS_A::LOW) + } + #[doc = "Sensitive Latency"] + #[inline(always)] + pub fn medium(self) -> &'a mut W { + self.variant(FQOS_A::MEDIUM) + } + #[doc = "Critical Latency"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(FQOS_A::HIGH) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u8 & 0x03) << 2); + self.w + } +} +#[doc = "Data Transfer Quality of Service\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DQOS_A { + #[doc = "0: Background (no sensitive operation)"] + DISABLE = 0, + #[doc = "1: Sensitive Bandwidth"] + LOW = 1, + #[doc = "2: Sensitive Latency"] + MEDIUM = 2, + #[doc = "3: Critical Latency"] + HIGH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DQOS_A) -> Self { + variant as _ + } +} +#[doc = "Field `DQOS` reader - Data Transfer Quality of Service"] +pub struct DQOS_R(crate::FieldReader); +impl DQOS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DQOS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DQOS_A { + match self.bits { + 0 => DQOS_A::DISABLE, + 1 => DQOS_A::LOW, + 2 => DQOS_A::MEDIUM, + 3 => DQOS_A::HIGH, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == DQOS_A::DISABLE + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == DQOS_A::LOW + } + #[doc = "Checks if the value of the field is `MEDIUM`"] + #[inline(always)] + pub fn is_medium(&self) -> bool { + **self == DQOS_A::MEDIUM + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == DQOS_A::HIGH + } +} +impl core::ops::Deref for DQOS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DQOS` writer - Data Transfer Quality of Service"] +pub struct DQOS_W<'a> { + w: &'a mut W, +} +impl<'a> DQOS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DQOS_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Background (no sensitive operation)"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(DQOS_A::DISABLE) + } + #[doc = "Sensitive Bandwidth"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(DQOS_A::LOW) + } + #[doc = "Sensitive Latency"] + #[inline(always)] + pub fn medium(self) -> &'a mut W { + self.variant(DQOS_A::MEDIUM) + } + #[doc = "Critical Latency"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(DQOS_A::HIGH) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u8 & 0x03) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Write-Back Quality of Service"] + #[inline(always)] + pub fn wrbqos(&self) -> WRBQOS_R { + WRBQOS_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bits 2:3 - Fetch Quality of Service"] + #[inline(always)] + pub fn fqos(&self) -> FQOS_R { + FQOS_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bits 4:5 - Data Transfer Quality of Service"] + #[inline(always)] + pub fn dqos(&self) -> DQOS_R { + DQOS_R::new(((self.bits >> 4) & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Write-Back Quality of Service"] + #[inline(always)] + pub fn wrbqos(&mut self) -> WRBQOS_W { + WRBQOS_W { w: self } + } + #[doc = "Bits 2:3 - Fetch Quality of Service"] + #[inline(always)] + pub fn fqos(&mut self) -> FQOS_W { + FQOS_W { w: self } + } + #[doc = "Bits 4:5 - Data Transfer Quality of Service"] + #[inline(always)] + pub fn dqos(&mut self) -> DQOS_W { + DQOS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "QOS Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [qosctrl](index.html) module"] +pub struct QOSCTRL_SPEC; +impl crate::RegisterSpec for QOSCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [qosctrl::R](R) reader structure"] +impl crate::Readable for QOSCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [qosctrl::W](W) writer structure"] +impl crate::Writable for QOSCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets QOSCTRL to value 0x2a"] +impl crate::Resettable for QOSCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x2a + } +} diff --git a/pac/atsamc20n/src/dmac/swtrigctrl.rs b/pac/atsamc20n/src/dmac/swtrigctrl.rs new file mode 100644 index 000000000000..8590fef852dc --- /dev/null +++ b/pac/atsamc20n/src/dmac/swtrigctrl.rs @@ -0,0 +1,630 @@ +#[doc = "Register `SWTRIGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SWTRIGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWTRIG0` reader - Channel 0 Software Trigger"] +pub struct SWTRIG0_R(crate::FieldReader); +impl SWTRIG0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG0` writer - Channel 0 Software Trigger"] +pub struct SWTRIG0_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `SWTRIG1` reader - Channel 1 Software Trigger"] +pub struct SWTRIG1_R(crate::FieldReader); +impl SWTRIG1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG1` writer - Channel 1 Software Trigger"] +pub struct SWTRIG1_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SWTRIG2` reader - Channel 2 Software Trigger"] +pub struct SWTRIG2_R(crate::FieldReader); +impl SWTRIG2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG2` writer - Channel 2 Software Trigger"] +pub struct SWTRIG2_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SWTRIG3` reader - Channel 3 Software Trigger"] +pub struct SWTRIG3_R(crate::FieldReader); +impl SWTRIG3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG3` writer - Channel 3 Software Trigger"] +pub struct SWTRIG3_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `SWTRIG4` reader - Channel 4 Software Trigger"] +pub struct SWTRIG4_R(crate::FieldReader); +impl SWTRIG4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG4` writer - Channel 4 Software Trigger"] +pub struct SWTRIG4_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `SWTRIG5` reader - Channel 5 Software Trigger"] +pub struct SWTRIG5_R(crate::FieldReader); +impl SWTRIG5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG5` writer - Channel 5 Software Trigger"] +pub struct SWTRIG5_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `SWTRIG6` reader - Channel 6 Software Trigger"] +pub struct SWTRIG6_R(crate::FieldReader); +impl SWTRIG6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG6` writer - Channel 6 Software Trigger"] +pub struct SWTRIG6_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `SWTRIG7` reader - Channel 7 Software Trigger"] +pub struct SWTRIG7_R(crate::FieldReader); +impl SWTRIG7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG7` writer - Channel 7 Software Trigger"] +pub struct SWTRIG7_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `SWTRIG8` reader - Channel 8 Software Trigger"] +pub struct SWTRIG8_R(crate::FieldReader); +impl SWTRIG8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG8` writer - Channel 8 Software Trigger"] +pub struct SWTRIG8_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `SWTRIG9` reader - Channel 9 Software Trigger"] +pub struct SWTRIG9_R(crate::FieldReader); +impl SWTRIG9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG9` writer - Channel 9 Software Trigger"] +pub struct SWTRIG9_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `SWTRIG10` reader - Channel 10 Software Trigger"] +pub struct SWTRIG10_R(crate::FieldReader); +impl SWTRIG10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG10` writer - Channel 10 Software Trigger"] +pub struct SWTRIG10_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `SWTRIG11` reader - Channel 11 Software Trigger"] +pub struct SWTRIG11_R(crate::FieldReader); +impl SWTRIG11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG11` writer - Channel 11 Software Trigger"] +pub struct SWTRIG11_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +impl R { + #[doc = "Bit 0 - Channel 0 Software Trigger"] + #[inline(always)] + pub fn swtrig0(&self) -> SWTRIG0_R { + SWTRIG0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel 1 Software Trigger"] + #[inline(always)] + pub fn swtrig1(&self) -> SWTRIG1_R { + SWTRIG1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel 2 Software Trigger"] + #[inline(always)] + pub fn swtrig2(&self) -> SWTRIG2_R { + SWTRIG2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Channel 3 Software Trigger"] + #[inline(always)] + pub fn swtrig3(&self) -> SWTRIG3_R { + SWTRIG3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Channel 4 Software Trigger"] + #[inline(always)] + pub fn swtrig4(&self) -> SWTRIG4_R { + SWTRIG4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Channel 5 Software Trigger"] + #[inline(always)] + pub fn swtrig5(&self) -> SWTRIG5_R { + SWTRIG5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Channel 6 Software Trigger"] + #[inline(always)] + pub fn swtrig6(&self) -> SWTRIG6_R { + SWTRIG6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Channel 7 Software Trigger"] + #[inline(always)] + pub fn swtrig7(&self) -> SWTRIG7_R { + SWTRIG7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Channel 8 Software Trigger"] + #[inline(always)] + pub fn swtrig8(&self) -> SWTRIG8_R { + SWTRIG8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Channel 9 Software Trigger"] + #[inline(always)] + pub fn swtrig9(&self) -> SWTRIG9_R { + SWTRIG9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Channel 10 Software Trigger"] + #[inline(always)] + pub fn swtrig10(&self) -> SWTRIG10_R { + SWTRIG10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Channel 11 Software Trigger"] + #[inline(always)] + pub fn swtrig11(&self) -> SWTRIG11_R { + SWTRIG11_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel 0 Software Trigger"] + #[inline(always)] + pub fn swtrig0(&mut self) -> SWTRIG0_W { + SWTRIG0_W { w: self } + } + #[doc = "Bit 1 - Channel 1 Software Trigger"] + #[inline(always)] + pub fn swtrig1(&mut self) -> SWTRIG1_W { + SWTRIG1_W { w: self } + } + #[doc = "Bit 2 - Channel 2 Software Trigger"] + #[inline(always)] + pub fn swtrig2(&mut self) -> SWTRIG2_W { + SWTRIG2_W { w: self } + } + #[doc = "Bit 3 - Channel 3 Software Trigger"] + #[inline(always)] + pub fn swtrig3(&mut self) -> SWTRIG3_W { + SWTRIG3_W { w: self } + } + #[doc = "Bit 4 - Channel 4 Software Trigger"] + #[inline(always)] + pub fn swtrig4(&mut self) -> SWTRIG4_W { + SWTRIG4_W { w: self } + } + #[doc = "Bit 5 - Channel 5 Software Trigger"] + #[inline(always)] + pub fn swtrig5(&mut self) -> SWTRIG5_W { + SWTRIG5_W { w: self } + } + #[doc = "Bit 6 - Channel 6 Software Trigger"] + #[inline(always)] + pub fn swtrig6(&mut self) -> SWTRIG6_W { + SWTRIG6_W { w: self } + } + #[doc = "Bit 7 - Channel 7 Software Trigger"] + #[inline(always)] + pub fn swtrig7(&mut self) -> SWTRIG7_W { + SWTRIG7_W { w: self } + } + #[doc = "Bit 8 - Channel 8 Software Trigger"] + #[inline(always)] + pub fn swtrig8(&mut self) -> SWTRIG8_W { + SWTRIG8_W { w: self } + } + #[doc = "Bit 9 - Channel 9 Software Trigger"] + #[inline(always)] + pub fn swtrig9(&mut self) -> SWTRIG9_W { + SWTRIG9_W { w: self } + } + #[doc = "Bit 10 - Channel 10 Software Trigger"] + #[inline(always)] + pub fn swtrig10(&mut self) -> SWTRIG10_W { + SWTRIG10_W { w: self } + } + #[doc = "Bit 11 - Channel 11 Software Trigger"] + #[inline(always)] + pub fn swtrig11(&mut self) -> SWTRIG11_W { + SWTRIG11_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Software Trigger Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [swtrigctrl](index.html) module"] +pub struct SWTRIGCTRL_SPEC; +impl crate::RegisterSpec for SWTRIGCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [swtrigctrl::R](R) reader structure"] +impl crate::Readable for SWTRIGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [swtrigctrl::W](W) writer structure"] +impl crate::Writable for SWTRIGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SWTRIGCTRL to value 0"] +impl crate::Resettable for SWTRIGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/dmac/wrbaddr.rs b/pac/atsamc20n/src/dmac/wrbaddr.rs new file mode 100644 index 000000000000..ccf2a376b853 --- /dev/null +++ b/pac/atsamc20n/src/dmac/wrbaddr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `WRBADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WRBADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WRBADDR` reader - Write-Back Memory Base Address"] +pub struct WRBADDR_R(crate::FieldReader); +impl WRBADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + WRBADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WRBADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WRBADDR` writer - Write-Back Memory Base Address"] +pub struct WRBADDR_W<'a> { + w: &'a mut W, +} +impl<'a> WRBADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Write-Back Memory Base Address"] + #[inline(always)] + pub fn wrbaddr(&self) -> WRBADDR_R { + WRBADDR_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Write-Back Memory Base Address"] + #[inline(always)] + pub fn wrbaddr(&mut self) -> WRBADDR_W { + WRBADDR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Write-Back Memory Section Base Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wrbaddr](index.html) module"] +pub struct WRBADDR_SPEC; +impl crate::RegisterSpec for WRBADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [wrbaddr::R](R) reader structure"] +impl crate::Readable for WRBADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wrbaddr::W](W) writer structure"] +impl crate::Writable for WRBADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WRBADDR to value 0"] +impl crate::Resettable for WRBADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/dsu.rs b/pac/atsamc20n/src/dsu.rs new file mode 100644 index 000000000000..14b78f6abfde --- /dev/null +++ b/pac/atsamc20n/src/dsu.rs @@ -0,0 +1,158 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrl: crate::Reg, + #[doc = "0x01 - Status A"] + pub statusa: crate::Reg, + #[doc = "0x02 - Status B"] + pub statusb: crate::Reg, + _reserved3: [u8; 0x01], + #[doc = "0x04 - Address"] + pub addr: crate::Reg, + #[doc = "0x08 - Length"] + pub length: crate::Reg, + #[doc = "0x0c - Data"] + pub data: crate::Reg, + #[doc = "0x10..0x18 - Debug Communication Channel n"] + pub dcc: [crate::Reg; 2], + #[doc = "0x18 - Device Identification"] + pub did: crate::Reg, + _reserved8: [u8; 0xd4], + #[doc = "0xf0..0xf8 - Device Configuration"] + pub dcfg: [crate::Reg; 2], + _reserved9: [u8; 0x0f08], + #[doc = "0x1000 - CoreSight ROM Table Entry 0"] + pub entry0: crate::Reg, + #[doc = "0x1004 - CoreSight ROM Table Entry 1"] + pub entry1: crate::Reg, + #[doc = "0x1008 - CoreSight ROM Table End"] + pub end: crate::Reg, + _reserved12: [u8; 0x0fc0], + #[doc = "0x1fcc - CoreSight ROM Table Memory Type"] + pub memtype: crate::Reg, + #[doc = "0x1fd0 - Peripheral Identification 4"] + pub pid4: crate::Reg, + #[doc = "0x1fd4 - Peripheral Identification 5"] + pub pid5: crate::Reg, + #[doc = "0x1fd8 - Peripheral Identification 6"] + pub pid6: crate::Reg, + #[doc = "0x1fdc - Peripheral Identification 7"] + pub pid7: crate::Reg, + #[doc = "0x1fe0 - Peripheral Identification 0"] + pub pid0: crate::Reg, + #[doc = "0x1fe4 - Peripheral Identification 1"] + pub pid1: crate::Reg, + #[doc = "0x1fe8 - Peripheral Identification 2"] + pub pid2: crate::Reg, + #[doc = "0x1fec - Peripheral Identification 3"] + pub pid3: crate::Reg, + #[doc = "0x1ff0 - Component Identification 0"] + pub cid0: crate::Reg, + #[doc = "0x1ff4 - Component Identification 1"] + pub cid1: crate::Reg, + #[doc = "0x1ff8 - Component Identification 2"] + pub cid2: crate::Reg, + #[doc = "0x1ffc - Component Identification 3"] + pub cid3: crate::Reg, +} +#[doc = "CTRL register accessor: an alias for `Reg`"] +pub type CTRL = crate::Reg; +#[doc = "Control"] +pub mod ctrl; +#[doc = "STATUSA register accessor: an alias for `Reg`"] +pub type STATUSA = crate::Reg; +#[doc = "Status A"] +pub mod statusa; +#[doc = "STATUSB register accessor: an alias for `Reg`"] +pub type STATUSB = crate::Reg; +#[doc = "Status B"] +pub mod statusb; +#[doc = "ADDR register accessor: an alias for `Reg`"] +pub type ADDR = crate::Reg; +#[doc = "Address"] +pub mod addr; +#[doc = "LENGTH register accessor: an alias for `Reg`"] +pub type LENGTH = crate::Reg; +#[doc = "Length"] +pub mod length; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "Data"] +pub mod data; +#[doc = "DCC register accessor: an alias for `Reg`"] +pub type DCC = crate::Reg; +#[doc = "Debug Communication Channel n"] +pub mod dcc; +#[doc = "DID register accessor: an alias for `Reg`"] +pub type DID = crate::Reg; +#[doc = "Device Identification"] +pub mod did; +#[doc = "DCFG register accessor: an alias for `Reg`"] +pub type DCFG = crate::Reg; +#[doc = "Device Configuration"] +pub mod dcfg; +#[doc = "ENTRY0 register accessor: an alias for `Reg`"] +pub type ENTRY0 = crate::Reg; +#[doc = "CoreSight ROM Table Entry 0"] +pub mod entry0; +#[doc = "ENTRY1 register accessor: an alias for `Reg`"] +pub type ENTRY1 = crate::Reg; +#[doc = "CoreSight ROM Table Entry 1"] +pub mod entry1; +#[doc = "END register accessor: an alias for `Reg`"] +pub type END = crate::Reg; +#[doc = "CoreSight ROM Table End"] +pub mod end; +#[doc = "MEMTYPE register accessor: an alias for `Reg`"] +pub type MEMTYPE = crate::Reg; +#[doc = "CoreSight ROM Table Memory Type"] +pub mod memtype; +#[doc = "PID4 register accessor: an alias for `Reg`"] +pub type PID4 = crate::Reg; +#[doc = "Peripheral Identification 4"] +pub mod pid4; +#[doc = "PID5 register accessor: an alias for `Reg`"] +pub type PID5 = crate::Reg; +#[doc = "Peripheral Identification 5"] +pub mod pid5; +#[doc = "PID6 register accessor: an alias for `Reg`"] +pub type PID6 = crate::Reg; +#[doc = "Peripheral Identification 6"] +pub mod pid6; +#[doc = "PID7 register accessor: an alias for `Reg`"] +pub type PID7 = crate::Reg; +#[doc = "Peripheral Identification 7"] +pub mod pid7; +#[doc = "PID0 register accessor: an alias for `Reg`"] +pub type PID0 = crate::Reg; +#[doc = "Peripheral Identification 0"] +pub mod pid0; +#[doc = "PID1 register accessor: an alias for `Reg`"] +pub type PID1 = crate::Reg; +#[doc = "Peripheral Identification 1"] +pub mod pid1; +#[doc = "PID2 register accessor: an alias for `Reg`"] +pub type PID2 = crate::Reg; +#[doc = "Peripheral Identification 2"] +pub mod pid2; +#[doc = "PID3 register accessor: an alias for `Reg`"] +pub type PID3 = crate::Reg; +#[doc = "Peripheral Identification 3"] +pub mod pid3; +#[doc = "CID0 register accessor: an alias for `Reg`"] +pub type CID0 = crate::Reg; +#[doc = "Component Identification 0"] +pub mod cid0; +#[doc = "CID1 register accessor: an alias for `Reg`"] +pub type CID1 = crate::Reg; +#[doc = "Component Identification 1"] +pub mod cid1; +#[doc = "CID2 register accessor: an alias for `Reg`"] +pub type CID2 = crate::Reg; +#[doc = "Component Identification 2"] +pub mod cid2; +#[doc = "CID3 register accessor: an alias for `Reg`"] +pub type CID3 = crate::Reg; +#[doc = "Component Identification 3"] +pub mod cid3; diff --git a/pac/atsamc20n/src/dsu/addr.rs b/pac/atsamc20n/src/dsu/addr.rs new file mode 100644 index 000000000000..412f874d6b15 --- /dev/null +++ b/pac/atsamc20n/src/dsu/addr.rs @@ -0,0 +1,140 @@ +#[doc = "Register `ADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `AMOD` reader - Access Mode"] +pub struct AMOD_R(crate::FieldReader); +impl AMOD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + AMOD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AMOD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AMOD` writer - Access Mode"] +pub struct AMOD_W<'a> { + w: &'a mut W, +} +impl<'a> AMOD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u32 & 0x03); + self.w + } +} +#[doc = "Field `ADDR` reader - Address"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - Address"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3fff_ffff << 2)) | ((value as u32 & 0x3fff_ffff) << 2); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Access Mode"] + #[inline(always)] + pub fn amod(&self) -> AMOD_R { + AMOD_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bits 2:31 - Address"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new(((self.bits >> 2) & 0x3fff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:1 - Access Mode"] + #[inline(always)] + pub fn amod(&mut self) -> AMOD_W { + AMOD_W { w: self } + } + #[doc = "Bits 2:31 - Address"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [addr](index.html) module"] +pub struct ADDR_SPEC; +impl crate::RegisterSpec for ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [addr::R](R) reader structure"] +impl crate::Readable for ADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [addr::W](W) writer structure"] +impl crate::Writable for ADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ADDR to value 0"] +impl crate::Resettable for ADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/dsu/cid0.rs b/pac/atsamc20n/src/dsu/cid0.rs new file mode 100644 index 000000000000..b3c2373dfc99 --- /dev/null +++ b/pac/atsamc20n/src/dsu/cid0.rs @@ -0,0 +1,53 @@ +#[doc = "Register `CID0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PREAMBLEB0` reader - Preamble Byte 0"] +pub struct PREAMBLEB0_R(crate::FieldReader); +impl PREAMBLEB0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PREAMBLEB0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PREAMBLEB0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:7 - Preamble Byte 0"] + #[inline(always)] + pub fn preambleb0(&self) -> PREAMBLEB0_R { + PREAMBLEB0_R::new((self.bits & 0xff) as u8) + } +} +#[doc = "Component Identification 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid0](index.html) module"] +pub struct CID0_SPEC; +impl crate::RegisterSpec for CID0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid0::R](R) reader structure"] +impl crate::Readable for CID0_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID0 to value 0x0d"] +impl crate::Resettable for CID0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0d + } +} diff --git a/pac/atsamc20n/src/dsu/cid1.rs b/pac/atsamc20n/src/dsu/cid1.rs new file mode 100644 index 000000000000..3628ceac64a7 --- /dev/null +++ b/pac/atsamc20n/src/dsu/cid1.rs @@ -0,0 +1,73 @@ +#[doc = "Register `CID1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PREAMBLE` reader - Preamble"] +pub struct PREAMBLE_R(crate::FieldReader); +impl PREAMBLE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PREAMBLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PREAMBLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCLASS` reader - Component Class"] +pub struct CCLASS_R(crate::FieldReader); +impl CCLASS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CCLASS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCLASS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:3 - Preamble"] + #[inline(always)] + pub fn preamble(&self) -> PREAMBLE_R { + PREAMBLE_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Component Class"] + #[inline(always)] + pub fn cclass(&self) -> CCLASS_R { + CCLASS_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +#[doc = "Component Identification 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid1](index.html) module"] +pub struct CID1_SPEC; +impl crate::RegisterSpec for CID1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid1::R](R) reader structure"] +impl crate::Readable for CID1_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID1 to value 0x10"] +impl crate::Resettable for CID1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x10 + } +} diff --git a/pac/atsamc20n/src/dsu/cid2.rs b/pac/atsamc20n/src/dsu/cid2.rs new file mode 100644 index 000000000000..714078d5c430 --- /dev/null +++ b/pac/atsamc20n/src/dsu/cid2.rs @@ -0,0 +1,53 @@ +#[doc = "Register `CID2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PREAMBLEB2` reader - Preamble Byte 2"] +pub struct PREAMBLEB2_R(crate::FieldReader); +impl PREAMBLEB2_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PREAMBLEB2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PREAMBLEB2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:7 - Preamble Byte 2"] + #[inline(always)] + pub fn preambleb2(&self) -> PREAMBLEB2_R { + PREAMBLEB2_R::new((self.bits & 0xff) as u8) + } +} +#[doc = "Component Identification 2\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid2](index.html) module"] +pub struct CID2_SPEC; +impl crate::RegisterSpec for CID2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid2::R](R) reader structure"] +impl crate::Readable for CID2_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID2 to value 0x05"] +impl crate::Resettable for CID2_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x05 + } +} diff --git a/pac/atsamc20n/src/dsu/cid3.rs b/pac/atsamc20n/src/dsu/cid3.rs new file mode 100644 index 000000000000..a345af7b5166 --- /dev/null +++ b/pac/atsamc20n/src/dsu/cid3.rs @@ -0,0 +1,53 @@ +#[doc = "Register `CID3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PREAMBLEB3` reader - Preamble Byte 3"] +pub struct PREAMBLEB3_R(crate::FieldReader); +impl PREAMBLEB3_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PREAMBLEB3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PREAMBLEB3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:7 - Preamble Byte 3"] + #[inline(always)] + pub fn preambleb3(&self) -> PREAMBLEB3_R { + PREAMBLEB3_R::new((self.bits & 0xff) as u8) + } +} +#[doc = "Component Identification 3\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid3](index.html) module"] +pub struct CID3_SPEC; +impl crate::RegisterSpec for CID3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid3::R](R) reader structure"] +impl crate::Readable for CID3_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID3 to value 0xb1"] +impl crate::Resettable for CID3_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xb1 + } +} diff --git a/pac/atsamc20n/src/dsu/ctrl.rs b/pac/atsamc20n/src/dsu/ctrl.rs new file mode 100644 index 000000000000..0a19db5a5239 --- /dev/null +++ b/pac/atsamc20n/src/dsu/ctrl.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `CRC` writer - 32-bit Cyclic Redundancy Code"] +pub struct CRC_W<'a> { + w: &'a mut W, +} +impl<'a> CRC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `MBIST` writer - Memory built-in self-test"] +pub struct MBIST_W<'a> { + w: &'a mut W, +} +impl<'a> MBIST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CE` writer - Chip-Erase"] +pub struct CE_W<'a> { + w: &'a mut W, +} +impl<'a> CE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `ARR` writer - Auxiliary Row Read"] +pub struct ARR_W<'a> { + w: &'a mut W, +} +impl<'a> ARR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +#[doc = "Field `SMSA` writer - Start Memory Stream Access"] +pub struct SMSA_W<'a> { + w: &'a mut W, +} +impl<'a> SMSA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 2 - 32-bit Cyclic Redundancy Code"] + #[inline(always)] + pub fn crc(&mut self) -> CRC_W { + CRC_W { w: self } + } + #[doc = "Bit 3 - Memory built-in self-test"] + #[inline(always)] + pub fn mbist(&mut self) -> MBIST_W { + MBIST_W { w: self } + } + #[doc = "Bit 4 - Chip-Erase"] + #[inline(always)] + pub fn ce(&mut self) -> CE_W { + CE_W { w: self } + } + #[doc = "Bit 6 - Auxiliary Row Read"] + #[inline(always)] + pub fn arr(&mut self) -> ARR_W { + ARR_W { w: self } + } + #[doc = "Bit 7 - Start Memory Stream Access"] + #[inline(always)] + pub fn smsa(&mut self) -> SMSA_W { + SMSA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"] +pub struct CTRL_SPEC; +impl crate::RegisterSpec for CTRL_SPEC { + type Ux = u8; +} +#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"] +impl crate::Writable for CTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/dsu/data.rs b/pac/atsamc20n/src/dsu/data.rs new file mode 100644 index 000000000000..193cc49a07fd --- /dev/null +++ b/pac/atsamc20n/src/dsu/data.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Data"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Data"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/dsu/dcc.rs b/pac/atsamc20n/src/dsu/dcc.rs new file mode 100644 index 000000000000..354323a499ef --- /dev/null +++ b/pac/atsamc20n/src/dsu/dcc.rs @@ -0,0 +1,104 @@ +#[doc = "Register `DCC[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DCC[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Data"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Data"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Communication Channel n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dcc](index.html) module"] +pub struct DCC_SPEC; +impl crate::RegisterSpec for DCC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dcc::R](R) reader structure"] +impl crate::Readable for DCC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dcc::W](W) writer structure"] +impl crate::Writable for DCC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DCC[%s] +to value 0"] +impl crate::Resettable for DCC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/dsu/dcfg.rs b/pac/atsamc20n/src/dsu/dcfg.rs new file mode 100644 index 000000000000..c6d61d0b496e --- /dev/null +++ b/pac/atsamc20n/src/dsu/dcfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `DCFG[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DCFG[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DCFG` reader - Device Configuration"] +pub struct DCFG_R(crate::FieldReader); +impl DCFG_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + DCFG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DCFG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DCFG` writer - Device Configuration"] +pub struct DCFG_W<'a> { + w: &'a mut W, +} +impl<'a> DCFG_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Device Configuration"] + #[inline(always)] + pub fn dcfg(&self) -> DCFG_R { + DCFG_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Device Configuration"] + #[inline(always)] + pub fn dcfg(&mut self) -> DCFG_W { + DCFG_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Device Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dcfg](index.html) module"] +pub struct DCFG_SPEC; +impl crate::RegisterSpec for DCFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dcfg::R](R) reader structure"] +impl crate::Readable for DCFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dcfg::W](W) writer structure"] +impl crate::Writable for DCFG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DCFG[%s] +to value 0"] +impl crate::Resettable for DCFG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/dsu/did.rs b/pac/atsamc20n/src/dsu/did.rs new file mode 100644 index 000000000000..77fce37602c0 --- /dev/null +++ b/pac/atsamc20n/src/dsu/did.rs @@ -0,0 +1,279 @@ +#[doc = "Register `DID` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `DEVSEL` reader - Device Select"] +pub struct DEVSEL_R(crate::FieldReader); +impl DEVSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DEVSEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DEVSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REVISION` reader - Revision Number"] +pub struct REVISION_R(crate::FieldReader); +impl REVISION_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REVISION_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REVISION_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIE` reader - Die Number"] +pub struct DIE_R(crate::FieldReader); +impl DIE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DIE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Series\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SERIES_A { + #[doc = "0: Cortex-M0+ processor, basic feature set"] + _0 = 0, + #[doc = "1: Cortex-M0+ processor, USB"] + _1 = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SERIES_A) -> Self { + variant as _ + } +} +#[doc = "Field `SERIES` reader - Series"] +pub struct SERIES_R(crate::FieldReader); +impl SERIES_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SERIES_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SERIES_A::_0), + 1 => Some(SERIES_A::_1), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_0`"] + #[inline(always)] + pub fn is_0(&self) -> bool { + **self == SERIES_A::_0 + } + #[doc = "Checks if the value of the field is `_1`"] + #[inline(always)] + pub fn is_1(&self) -> bool { + **self == SERIES_A::_1 + } +} +impl core::ops::Deref for SERIES_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Family\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FAMILY_A { + #[doc = "0: General purpose microcontroller"] + _0 = 0, + #[doc = "1: PicoPower"] + _1 = 1, + #[doc = "2: 5V Industrial"] + _2 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FAMILY_A) -> Self { + variant as _ + } +} +#[doc = "Field `FAMILY` reader - Family"] +pub struct FAMILY_R(crate::FieldReader); +impl FAMILY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FAMILY_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(FAMILY_A::_0), + 1 => Some(FAMILY_A::_1), + 2 => Some(FAMILY_A::_2), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_0`"] + #[inline(always)] + pub fn is_0(&self) -> bool { + **self == FAMILY_A::_0 + } + #[doc = "Checks if the value of the field is `_1`"] + #[inline(always)] + pub fn is_1(&self) -> bool { + **self == FAMILY_A::_1 + } + #[doc = "Checks if the value of the field is `_2`"] + #[inline(always)] + pub fn is_2(&self) -> bool { + **self == FAMILY_A::_2 + } +} +impl core::ops::Deref for FAMILY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Processor\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PROCESSOR_A { + #[doc = "0: Cortex-M0"] + _0 = 0, + #[doc = "1: Cortex-M0+"] + _1 = 1, + #[doc = "2: Cortex-M3"] + _2 = 2, + #[doc = "3: Cortex-M4"] + _3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PROCESSOR_A) -> Self { + variant as _ + } +} +#[doc = "Field `PROCESSOR` reader - Processor"] +pub struct PROCESSOR_R(crate::FieldReader); +impl PROCESSOR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PROCESSOR_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PROCESSOR_A::_0), + 1 => Some(PROCESSOR_A::_1), + 2 => Some(PROCESSOR_A::_2), + 3 => Some(PROCESSOR_A::_3), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_0`"] + #[inline(always)] + pub fn is_0(&self) -> bool { + **self == PROCESSOR_A::_0 + } + #[doc = "Checks if the value of the field is `_1`"] + #[inline(always)] + pub fn is_1(&self) -> bool { + **self == PROCESSOR_A::_1 + } + #[doc = "Checks if the value of the field is `_2`"] + #[inline(always)] + pub fn is_2(&self) -> bool { + **self == PROCESSOR_A::_2 + } + #[doc = "Checks if the value of the field is `_3`"] + #[inline(always)] + pub fn is_3(&self) -> bool { + **self == PROCESSOR_A::_3 + } +} +impl core::ops::Deref for PROCESSOR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:7 - Device Select"] + #[inline(always)] + pub fn devsel(&self) -> DEVSEL_R { + DEVSEL_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:11 - Revision Number"] + #[inline(always)] + pub fn revision(&self) -> REVISION_R { + REVISION_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - Die Number"] + #[inline(always)] + pub fn die(&self) -> DIE_R { + DIE_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:21 - Series"] + #[inline(always)] + pub fn series(&self) -> SERIES_R { + SERIES_R::new(((self.bits >> 16) & 0x3f) as u8) + } + #[doc = "Bits 23:27 - Family"] + #[inline(always)] + pub fn family(&self) -> FAMILY_R { + FAMILY_R::new(((self.bits >> 23) & 0x1f) as u8) + } + #[doc = "Bits 28:31 - Processor"] + #[inline(always)] + pub fn processor(&self) -> PROCESSOR_R { + PROCESSOR_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +#[doc = "Device Identification\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [did](index.html) module"] +pub struct DID_SPEC; +impl crate::RegisterSpec for DID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [did::R](R) reader structure"] +impl crate::Readable for DID_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DID to value 0x1100_1420"] +impl crate::Resettable for DID_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x1100_1420 + } +} diff --git a/pac/atsamc20n/src/dsu/end.rs b/pac/atsamc20n/src/dsu/end.rs new file mode 100644 index 000000000000..cce2edea2bce --- /dev/null +++ b/pac/atsamc20n/src/dsu/end.rs @@ -0,0 +1,53 @@ +#[doc = "Register `END` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `END` reader - End Marker"] +pub struct END_R(crate::FieldReader); +impl END_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + END_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for END_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - End Marker"] + #[inline(always)] + pub fn end(&self) -> END_R { + END_R::new(self.bits as u32) + } +} +#[doc = "CoreSight ROM Table End\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [end](index.html) module"] +pub struct END_SPEC; +impl crate::RegisterSpec for END_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [end::R](R) reader structure"] +impl crate::Readable for END_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets END to value 0"] +impl crate::Resettable for END_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/dsu/entry0.rs b/pac/atsamc20n/src/dsu/entry0.rs new file mode 100644 index 000000000000..d8563990e827 --- /dev/null +++ b/pac/atsamc20n/src/dsu/entry0.rs @@ -0,0 +1,93 @@ +#[doc = "Register `ENTRY0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `EPRES` reader - Entry Present"] +pub struct EPRES_R(crate::FieldReader); +impl EPRES_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EPRES_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EPRES_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FMT` reader - Format"] +pub struct FMT_R(crate::FieldReader); +impl FMT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FMT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FMT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDOFF` reader - Address Offset"] +pub struct ADDOFF_R(crate::FieldReader); +impl ADDOFF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + ADDOFF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDOFF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Entry Present"] + #[inline(always)] + pub fn epres(&self) -> EPRES_R { + EPRES_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Format"] + #[inline(always)] + pub fn fmt(&self) -> FMT_R { + FMT_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 12:31 - Address Offset"] + #[inline(always)] + pub fn addoff(&self) -> ADDOFF_R { + ADDOFF_R::new(((self.bits >> 12) & 0x000f_ffff) as u32) + } +} +#[doc = "CoreSight ROM Table Entry 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [entry0](index.html) module"] +pub struct ENTRY0_SPEC; +impl crate::RegisterSpec for ENTRY0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [entry0::R](R) reader structure"] +impl crate::Readable for ENTRY0_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets ENTRY0 to value 0x9f0f_c002"] +impl crate::Resettable for ENTRY0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x9f0f_c002 + } +} diff --git a/pac/atsamc20n/src/dsu/entry1.rs b/pac/atsamc20n/src/dsu/entry1.rs new file mode 100644 index 000000000000..cec8fa367705 --- /dev/null +++ b/pac/atsamc20n/src/dsu/entry1.rs @@ -0,0 +1,31 @@ +#[doc = "Register `ENTRY1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "CoreSight ROM Table Entry 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [entry1](index.html) module"] +pub struct ENTRY1_SPEC; +impl crate::RegisterSpec for ENTRY1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [entry1::R](R) reader structure"] +impl crate::Readable for ENTRY1_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets ENTRY1 to value 0x5002"] +impl crate::Resettable for ENTRY1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x5002 + } +} diff --git a/pac/atsamc20n/src/dsu/length.rs b/pac/atsamc20n/src/dsu/length.rs new file mode 100644 index 000000000000..2dc771f74dfd --- /dev/null +++ b/pac/atsamc20n/src/dsu/length.rs @@ -0,0 +1,103 @@ +#[doc = "Register `LENGTH` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `LENGTH` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `LENGTH` reader - Length"] +pub struct LENGTH_R(crate::FieldReader); +impl LENGTH_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + LENGTH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LENGTH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LENGTH` writer - Length"] +pub struct LENGTH_W<'a> { + w: &'a mut W, +} +impl<'a> LENGTH_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3fff_ffff << 2)) | ((value as u32 & 0x3fff_ffff) << 2); + self.w + } +} +impl R { + #[doc = "Bits 2:31 - Length"] + #[inline(always)] + pub fn length(&self) -> LENGTH_R { + LENGTH_R::new(((self.bits >> 2) & 0x3fff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 2:31 - Length"] + #[inline(always)] + pub fn length(&mut self) -> LENGTH_W { + LENGTH_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Length\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [length](index.html) module"] +pub struct LENGTH_SPEC; +impl crate::RegisterSpec for LENGTH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [length::R](R) reader structure"] +impl crate::Readable for LENGTH_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [length::W](W) writer structure"] +impl crate::Writable for LENGTH_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets LENGTH to value 0"] +impl crate::Resettable for LENGTH_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/dsu/memtype.rs b/pac/atsamc20n/src/dsu/memtype.rs new file mode 100644 index 000000000000..3cc841e2ba78 --- /dev/null +++ b/pac/atsamc20n/src/dsu/memtype.rs @@ -0,0 +1,53 @@ +#[doc = "Register `MEMTYPE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SMEMP` reader - System Memory Present"] +pub struct SMEMP_R(crate::FieldReader); +impl SMEMP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SMEMP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SMEMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - System Memory Present"] + #[inline(always)] + pub fn smemp(&self) -> SMEMP_R { + SMEMP_R::new((self.bits & 0x01) != 0) + } +} +#[doc = "CoreSight ROM Table Memory Type\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [memtype](index.html) module"] +pub struct MEMTYPE_SPEC; +impl crate::RegisterSpec for MEMTYPE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [memtype::R](R) reader structure"] +impl crate::Readable for MEMTYPE_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets MEMTYPE to value 0"] +impl crate::Resettable for MEMTYPE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/dsu/pid0.rs b/pac/atsamc20n/src/dsu/pid0.rs new file mode 100644 index 000000000000..98028ea62838 --- /dev/null +++ b/pac/atsamc20n/src/dsu/pid0.rs @@ -0,0 +1,53 @@ +#[doc = "Register `PID0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PARTNBL` reader - Part Number Low"] +pub struct PARTNBL_R(crate::FieldReader); +impl PARTNBL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PARTNBL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PARTNBL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:7 - Part Number Low"] + #[inline(always)] + pub fn partnbl(&self) -> PARTNBL_R { + PARTNBL_R::new((self.bits & 0xff) as u8) + } +} +#[doc = "Peripheral Identification 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid0](index.html) module"] +pub struct PID0_SPEC; +impl crate::RegisterSpec for PID0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid0::R](R) reader structure"] +impl crate::Readable for PID0_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID0 to value 0xd0"] +impl crate::Resettable for PID0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xd0 + } +} diff --git a/pac/atsamc20n/src/dsu/pid1.rs b/pac/atsamc20n/src/dsu/pid1.rs new file mode 100644 index 000000000000..4f94b853507c --- /dev/null +++ b/pac/atsamc20n/src/dsu/pid1.rs @@ -0,0 +1,73 @@ +#[doc = "Register `PID1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PARTNBH` reader - Part Number High"] +pub struct PARTNBH_R(crate::FieldReader); +impl PARTNBH_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PARTNBH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PARTNBH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `JEPIDCL` reader - Low part of the JEP-106 Identity Code"] +pub struct JEPIDCL_R(crate::FieldReader); +impl JEPIDCL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + JEPIDCL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for JEPIDCL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:3 - Part Number High"] + #[inline(always)] + pub fn partnbh(&self) -> PARTNBH_R { + PARTNBH_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Low part of the JEP-106 Identity Code"] + #[inline(always)] + pub fn jepidcl(&self) -> JEPIDCL_R { + JEPIDCL_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +#[doc = "Peripheral Identification 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid1](index.html) module"] +pub struct PID1_SPEC; +impl crate::RegisterSpec for PID1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid1::R](R) reader structure"] +impl crate::Readable for PID1_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID1 to value 0xfc"] +impl crate::Resettable for PID1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xfc + } +} diff --git a/pac/atsamc20n/src/dsu/pid2.rs b/pac/atsamc20n/src/dsu/pid2.rs new file mode 100644 index 000000000000..d8f8ed10192e --- /dev/null +++ b/pac/atsamc20n/src/dsu/pid2.rs @@ -0,0 +1,93 @@ +#[doc = "Register `PID2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `JEPIDCH` reader - JEP-106 Identity Code High"] +pub struct JEPIDCH_R(crate::FieldReader); +impl JEPIDCH_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + JEPIDCH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for JEPIDCH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `JEPU` reader - JEP-106 Identity Code is used"] +pub struct JEPU_R(crate::FieldReader); +impl JEPU_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + JEPU_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for JEPU_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REVISION` reader - Revision Number"] +pub struct REVISION_R(crate::FieldReader); +impl REVISION_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REVISION_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REVISION_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:2 - JEP-106 Identity Code High"] + #[inline(always)] + pub fn jepidch(&self) -> JEPIDCH_R { + JEPIDCH_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 3 - JEP-106 Identity Code is used"] + #[inline(always)] + pub fn jepu(&self) -> JEPU_R { + JEPU_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bits 4:7 - Revision Number"] + #[inline(always)] + pub fn revision(&self) -> REVISION_R { + REVISION_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +#[doc = "Peripheral Identification 2\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid2](index.html) module"] +pub struct PID2_SPEC; +impl crate::RegisterSpec for PID2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid2::R](R) reader structure"] +impl crate::Readable for PID2_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID2 to value 0x09"] +impl crate::Resettable for PID2_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x09 + } +} diff --git a/pac/atsamc20n/src/dsu/pid3.rs b/pac/atsamc20n/src/dsu/pid3.rs new file mode 100644 index 000000000000..c0a8fb2d7f92 --- /dev/null +++ b/pac/atsamc20n/src/dsu/pid3.rs @@ -0,0 +1,73 @@ +#[doc = "Register `PID3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `CUSMOD` reader - ARM CUSMOD"] +pub struct CUSMOD_R(crate::FieldReader); +impl CUSMOD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CUSMOD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CUSMOD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REVAND` reader - Revision Number"] +pub struct REVAND_R(crate::FieldReader); +impl REVAND_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REVAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REVAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:3 - ARM CUSMOD"] + #[inline(always)] + pub fn cusmod(&self) -> CUSMOD_R { + CUSMOD_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Revision Number"] + #[inline(always)] + pub fn revand(&self) -> REVAND_R { + REVAND_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +#[doc = "Peripheral Identification 3\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid3](index.html) module"] +pub struct PID3_SPEC; +impl crate::RegisterSpec for PID3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid3::R](R) reader structure"] +impl crate::Readable for PID3_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID3 to value 0"] +impl crate::Resettable for PID3_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/dsu/pid4.rs b/pac/atsamc20n/src/dsu/pid4.rs new file mode 100644 index 000000000000..d3a1bd120f0b --- /dev/null +++ b/pac/atsamc20n/src/dsu/pid4.rs @@ -0,0 +1,73 @@ +#[doc = "Register `PID4` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `JEPCC` reader - JEP-106 Continuation Code"] +pub struct JEPCC_R(crate::FieldReader); +impl JEPCC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + JEPCC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for JEPCC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FKBC` reader - 4KB count"] +pub struct FKBC_R(crate::FieldReader); +impl FKBC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FKBC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FKBC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:3 - JEP-106 Continuation Code"] + #[inline(always)] + pub fn jepcc(&self) -> JEPCC_R { + JEPCC_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - 4KB count"] + #[inline(always)] + pub fn fkbc(&self) -> FKBC_R { + FKBC_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +#[doc = "Peripheral Identification 4\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid4](index.html) module"] +pub struct PID4_SPEC; +impl crate::RegisterSpec for PID4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid4::R](R) reader structure"] +impl crate::Readable for PID4_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID4 to value 0"] +impl crate::Resettable for PID4_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/dsu/pid5.rs b/pac/atsamc20n/src/dsu/pid5.rs new file mode 100644 index 000000000000..d343d4800b95 --- /dev/null +++ b/pac/atsamc20n/src/dsu/pid5.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID5` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 5\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid5](index.html) module"] +pub struct PID5_SPEC; +impl crate::RegisterSpec for PID5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid5::R](R) reader structure"] +impl crate::Readable for PID5_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID5 to value 0"] +impl crate::Resettable for PID5_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/dsu/pid6.rs b/pac/atsamc20n/src/dsu/pid6.rs new file mode 100644 index 000000000000..55cc2b8b5861 --- /dev/null +++ b/pac/atsamc20n/src/dsu/pid6.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID6` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 6\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid6](index.html) module"] +pub struct PID6_SPEC; +impl crate::RegisterSpec for PID6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid6::R](R) reader structure"] +impl crate::Readable for PID6_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID6 to value 0"] +impl crate::Resettable for PID6_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/dsu/pid7.rs b/pac/atsamc20n/src/dsu/pid7.rs new file mode 100644 index 000000000000..77664d4f2f95 --- /dev/null +++ b/pac/atsamc20n/src/dsu/pid7.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID7` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 7\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid7](index.html) module"] +pub struct PID7_SPEC; +impl crate::RegisterSpec for PID7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid7::R](R) reader structure"] +impl crate::Readable for PID7_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID7 to value 0"] +impl crate::Resettable for PID7_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/dsu/statusa.rs b/pac/atsamc20n/src/dsu/statusa.rs new file mode 100644 index 000000000000..c7b90a13e491 --- /dev/null +++ b/pac/atsamc20n/src/dsu/statusa.rs @@ -0,0 +1,301 @@ +#[doc = "Register `STATUSA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUSA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DONE` reader - Done"] +pub struct DONE_R(crate::FieldReader); +impl DONE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DONE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DONE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DONE` writer - Done"] +pub struct DONE_W<'a> { + w: &'a mut W, +} +impl<'a> DONE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `CRSTEXT` reader - CPU Reset Phase Extension"] +pub struct CRSTEXT_R(crate::FieldReader); +impl CRSTEXT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CRSTEXT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CRSTEXT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRSTEXT` writer - CPU Reset Phase Extension"] +pub struct CRSTEXT_W<'a> { + w: &'a mut W, +} +impl<'a> CRSTEXT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `BERR` reader - Bus Error"] +pub struct BERR_R(crate::FieldReader); +impl BERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BERR` writer - Bus Error"] +pub struct BERR_W<'a> { + w: &'a mut W, +} +impl<'a> BERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `FAIL` reader - Failure"] +pub struct FAIL_R(crate::FieldReader); +impl FAIL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAIL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAIL` writer - Failure"] +pub struct FAIL_W<'a> { + w: &'a mut W, +} +impl<'a> FAIL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PERR` reader - Protection Error"] +pub struct PERR_R(crate::FieldReader); +impl PERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERR` writer - Protection Error"] +pub struct PERR_W<'a> { + w: &'a mut W, +} +impl<'a> PERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +impl R { + #[doc = "Bit 0 - Done"] + #[inline(always)] + pub fn done(&self) -> DONE_R { + DONE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - CPU Reset Phase Extension"] + #[inline(always)] + pub fn crstext(&self) -> CRSTEXT_R { + CRSTEXT_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Bus Error"] + #[inline(always)] + pub fn berr(&self) -> BERR_R { + BERR_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Failure"] + #[inline(always)] + pub fn fail(&self) -> FAIL_R { + FAIL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Protection Error"] + #[inline(always)] + pub fn perr(&self) -> PERR_R { + PERR_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Done"] + #[inline(always)] + pub fn done(&mut self) -> DONE_W { + DONE_W { w: self } + } + #[doc = "Bit 1 - CPU Reset Phase Extension"] + #[inline(always)] + pub fn crstext(&mut self) -> CRSTEXT_W { + CRSTEXT_W { w: self } + } + #[doc = "Bit 2 - Bus Error"] + #[inline(always)] + pub fn berr(&mut self) -> BERR_W { + BERR_W { w: self } + } + #[doc = "Bit 3 - Failure"] + #[inline(always)] + pub fn fail(&mut self) -> FAIL_W { + FAIL_W { w: self } + } + #[doc = "Bit 4 - Protection Error"] + #[inline(always)] + pub fn perr(&mut self) -> PERR_W { + PERR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [statusa](index.html) module"] +pub struct STATUSA_SPEC; +impl crate::RegisterSpec for STATUSA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [statusa::R](R) reader structure"] +impl crate::Readable for STATUSA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [statusa::W](W) writer structure"] +impl crate::Writable for STATUSA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUSA to value 0"] +impl crate::Resettable for STATUSA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/dsu/statusb.rs b/pac/atsamc20n/src/dsu/statusb.rs new file mode 100644 index 000000000000..1e9374f8deae --- /dev/null +++ b/pac/atsamc20n/src/dsu/statusb.rs @@ -0,0 +1,133 @@ +#[doc = "Register `STATUSB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PROT` reader - Protected"] +pub struct PROT_R(crate::FieldReader); +impl PROT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PROT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PROT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGPRES` reader - Debugger Present"] +pub struct DBGPRES_R(crate::FieldReader); +impl DBGPRES_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGPRES_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGPRES_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DCCD0` reader - Debug Communication Channel 0 Dirty"] +pub struct DCCD0_R(crate::FieldReader); +impl DCCD0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DCCD0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DCCD0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DCCD1` reader - Debug Communication Channel 1 Dirty"] +pub struct DCCD1_R(crate::FieldReader); +impl DCCD1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DCCD1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DCCD1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HPE` reader - Hot-Plugging Enable"] +pub struct HPE_R(crate::FieldReader); +impl HPE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HPE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HPE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Protected"] + #[inline(always)] + pub fn prot(&self) -> PROT_R { + PROT_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Debugger Present"] + #[inline(always)] + pub fn dbgpres(&self) -> DBGPRES_R { + DBGPRES_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Debug Communication Channel 0 Dirty"] + #[inline(always)] + pub fn dccd0(&self) -> DCCD0_R { + DCCD0_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Debug Communication Channel 1 Dirty"] + #[inline(always)] + pub fn dccd1(&self) -> DCCD1_R { + DCCD1_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Hot-Plugging Enable"] + #[inline(always)] + pub fn hpe(&self) -> HPE_R { + HPE_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +#[doc = "Status B\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [statusb](index.html) module"] +pub struct STATUSB_SPEC; +impl crate::RegisterSpec for STATUSB_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [statusb::R](R) reader structure"] +impl crate::Readable for STATUSB_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUSB to value 0"] +impl crate::Resettable for STATUSB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/eic.rs b/pac/atsamc20n/src/eic.rs new file mode 100644 index 000000000000..08d0a8f18bbf --- /dev/null +++ b/pac/atsamc20n/src/eic.rs @@ -0,0 +1,83 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + #[doc = "0x01 - Non-Maskable Interrupt Control"] + pub nmictrl: crate::Reg, + #[doc = "0x02 - Non-Maskable Interrupt Flag Status and Clear"] + pub nmiflag: crate::Reg, + #[doc = "0x04 - Synchronization Busy"] + pub syncbusy: crate::Reg, + #[doc = "0x08 - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x0c - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x10 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x14 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x18 - External Interrupt Asynchronous Mode"] + pub asynch: crate::Reg, + #[doc = "0x1c..0x24 - External Interrupt Sense Configuration"] + pub config: [crate::Reg; 2], + _reserved10: [u8; 0x0c], + #[doc = "0x30 - Debouncer Enable"] + pub debouncen: crate::Reg, + #[doc = "0x34 - Debouncer Prescaler"] + pub dprescaler: crate::Reg, + #[doc = "0x38 - Pin State"] + pub pinstate: crate::Reg, +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "NMICTRL register accessor: an alias for `Reg`"] +pub type NMICTRL = crate::Reg; +#[doc = "Non-Maskable Interrupt Control"] +pub mod nmictrl; +#[doc = "NMIFLAG register accessor: an alias for `Reg`"] +pub type NMIFLAG = crate::Reg; +#[doc = "Non-Maskable Interrupt Flag Status and Clear"] +pub mod nmiflag; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Busy"] +pub mod syncbusy; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "ASYNCH register accessor: an alias for `Reg`"] +pub type ASYNCH = crate::Reg; +#[doc = "External Interrupt Asynchronous Mode"] +pub mod asynch; +#[doc = "CONFIG register accessor: an alias for `Reg`"] +pub type CONFIG = crate::Reg; +#[doc = "External Interrupt Sense Configuration"] +pub mod config; +#[doc = "DEBOUNCEN register accessor: an alias for `Reg`"] +pub type DEBOUNCEN = crate::Reg; +#[doc = "Debouncer Enable"] +pub mod debouncen; +#[doc = "DPRESCALER register accessor: an alias for `Reg`"] +pub type DPRESCALER = crate::Reg; +#[doc = "Debouncer Prescaler"] +pub mod dprescaler; +#[doc = "PINSTATE register accessor: an alias for `Reg`"] +pub type PINSTATE = crate::Reg; +#[doc = "Pin State"] +pub mod pinstate; diff --git a/pac/atsamc20n/src/eic/asynch.rs b/pac/atsamc20n/src/eic/asynch.rs new file mode 100644 index 000000000000..e8c893400684 --- /dev/null +++ b/pac/atsamc20n/src/eic/asynch.rs @@ -0,0 +1,152 @@ +#[doc = "Register `ASYNCH` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ASYNCH` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Asynchronous Edge Detection Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u16)] +pub enum ASYNCH_A { + #[doc = "0: Edge detection is clock synchronously operated"] + SYNC = 0, + #[doc = "1: Edge detection is clock asynchronously operated"] + ASYNC = 1, +} +impl From for u16 { + #[inline(always)] + fn from(variant: ASYNCH_A) -> Self { + variant as _ + } +} +#[doc = "Field `ASYNCH` reader - Asynchronous Edge Detection Mode"] +pub struct ASYNCH_R(crate::FieldReader); +impl ASYNCH_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + ASYNCH_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(ASYNCH_A::SYNC), + 1 => Some(ASYNCH_A::ASYNC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `SYNC`"] + #[inline(always)] + pub fn is_sync(&self) -> bool { + **self == ASYNCH_A::SYNC + } + #[doc = "Checks if the value of the field is `ASYNC`"] + #[inline(always)] + pub fn is_async(&self) -> bool { + **self == ASYNCH_A::ASYNC + } +} +impl core::ops::Deref for ASYNCH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ASYNCH` writer - Asynchronous Edge Detection Mode"] +pub struct ASYNCH_W<'a> { + w: &'a mut W, +} +impl<'a> ASYNCH_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: ASYNCH_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Edge detection is clock synchronously operated"] + #[inline(always)] + pub fn sync(self) -> &'a mut W { + self.variant(ASYNCH_A::SYNC) + } + #[doc = "Edge detection is clock asynchronously operated"] + #[inline(always)] + pub fn async_(self) -> &'a mut W { + self.variant(ASYNCH_A::ASYNC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Asynchronous Edge Detection Mode"] + #[inline(always)] + pub fn asynch(&self) -> ASYNCH_R { + ASYNCH_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Asynchronous Edge Detection Mode"] + #[inline(always)] + pub fn asynch(&mut self) -> ASYNCH_W { + ASYNCH_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "External Interrupt Asynchronous Mode\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [asynch](index.html) module"] +pub struct ASYNCH_SPEC; +impl crate::RegisterSpec for ASYNCH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [asynch::R](R) reader structure"] +impl crate::Readable for ASYNCH_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [asynch::W](W) writer structure"] +impl crate::Writable for ASYNCH_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ASYNCH to value 0"] +impl crate::Resettable for ASYNCH_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/eic/config.rs b/pac/atsamc20n/src/eic/config.rs new file mode 100644 index 000000000000..2235889ac17f --- /dev/null +++ b/pac/atsamc20n/src/eic/config.rs @@ -0,0 +1,1547 @@ +#[doc = "Register `CONFIG[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CONFIG[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Input Sense Configuration 0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE0_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE0_A) -> Self { + variant as _ + } +} +#[doc = "Field `SENSE0` reader - Input Sense Configuration 0"] +pub struct SENSE0_R(crate::FieldReader); +impl SENSE0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SENSE0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE0_A::NONE), + 1 => Some(SENSE0_A::RISE), + 2 => Some(SENSE0_A::FALL), + 3 => Some(SENSE0_A::BOTH), + 4 => Some(SENSE0_A::HIGH), + 5 => Some(SENSE0_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == SENSE0_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == SENSE0_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == SENSE0_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == SENSE0_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SENSE0_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SENSE0_A::LOW + } +} +impl core::ops::Deref for SENSE0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SENSE0` writer - Input Sense Configuration 0"] +pub struct SENSE0_W<'a> { + w: &'a mut W, +} +impl<'a> SENSE0_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SENSE0_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE0_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE0_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE0_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE0_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE0_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE0_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Field `FILTEN0` reader - Filter Enable 0"] +pub struct FILTEN0_R(crate::FieldReader); +impl FILTEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FILTEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTEN0` writer - Filter Enable 0"] +pub struct FILTEN0_W<'a> { + w: &'a mut W, +} +impl<'a> FILTEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Input Sense Configuration 1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE1_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE1_A) -> Self { + variant as _ + } +} +#[doc = "Field `SENSE1` reader - Input Sense Configuration 1"] +pub struct SENSE1_R(crate::FieldReader); +impl SENSE1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SENSE1_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE1_A::NONE), + 1 => Some(SENSE1_A::RISE), + 2 => Some(SENSE1_A::FALL), + 3 => Some(SENSE1_A::BOTH), + 4 => Some(SENSE1_A::HIGH), + 5 => Some(SENSE1_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == SENSE1_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == SENSE1_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == SENSE1_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == SENSE1_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SENSE1_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SENSE1_A::LOW + } +} +impl core::ops::Deref for SENSE1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SENSE1` writer - Input Sense Configuration 1"] +pub struct SENSE1_W<'a> { + w: &'a mut W, +} +impl<'a> SENSE1_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SENSE1_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE1_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE1_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE1_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE1_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE1_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE1_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 4)) | ((value as u32 & 0x07) << 4); + self.w + } +} +#[doc = "Field `FILTEN1` reader - Filter Enable 1"] +pub struct FILTEN1_R(crate::FieldReader); +impl FILTEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FILTEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTEN1` writer - Filter Enable 1"] +pub struct FILTEN1_W<'a> { + w: &'a mut W, +} +impl<'a> FILTEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Input Sense Configuration 2\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE2_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE2_A) -> Self { + variant as _ + } +} +#[doc = "Field `SENSE2` reader - Input Sense Configuration 2"] +pub struct SENSE2_R(crate::FieldReader); +impl SENSE2_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SENSE2_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE2_A::NONE), + 1 => Some(SENSE2_A::RISE), + 2 => Some(SENSE2_A::FALL), + 3 => Some(SENSE2_A::BOTH), + 4 => Some(SENSE2_A::HIGH), + 5 => Some(SENSE2_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == SENSE2_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == SENSE2_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == SENSE2_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == SENSE2_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SENSE2_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SENSE2_A::LOW + } +} +impl core::ops::Deref for SENSE2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SENSE2` writer - Input Sense Configuration 2"] +pub struct SENSE2_W<'a> { + w: &'a mut W, +} +impl<'a> SENSE2_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SENSE2_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE2_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE2_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE2_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE2_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE2_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE2_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +#[doc = "Field `FILTEN2` reader - Filter Enable 2"] +pub struct FILTEN2_R(crate::FieldReader); +impl FILTEN2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FILTEN2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTEN2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTEN2` writer - Filter Enable 2"] +pub struct FILTEN2_W<'a> { + w: &'a mut W, +} +impl<'a> FILTEN2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Input Sense Configuration 3\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE3_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE3_A) -> Self { + variant as _ + } +} +#[doc = "Field `SENSE3` reader - Input Sense Configuration 3"] +pub struct SENSE3_R(crate::FieldReader); +impl SENSE3_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SENSE3_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE3_A::NONE), + 1 => Some(SENSE3_A::RISE), + 2 => Some(SENSE3_A::FALL), + 3 => Some(SENSE3_A::BOTH), + 4 => Some(SENSE3_A::HIGH), + 5 => Some(SENSE3_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == SENSE3_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == SENSE3_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == SENSE3_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == SENSE3_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SENSE3_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SENSE3_A::LOW + } +} +impl core::ops::Deref for SENSE3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SENSE3` writer - Input Sense Configuration 3"] +pub struct SENSE3_W<'a> { + w: &'a mut W, +} +impl<'a> SENSE3_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SENSE3_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE3_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE3_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE3_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE3_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE3_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE3_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 12)) | ((value as u32 & 0x07) << 12); + self.w + } +} +#[doc = "Field `FILTEN3` reader - Filter Enable 3"] +pub struct FILTEN3_R(crate::FieldReader); +impl FILTEN3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FILTEN3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTEN3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTEN3` writer - Filter Enable 3"] +pub struct FILTEN3_W<'a> { + w: &'a mut W, +} +impl<'a> FILTEN3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Input Sense Configuration 4\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE4_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE4_A) -> Self { + variant as _ + } +} +#[doc = "Field `SENSE4` reader - Input Sense Configuration 4"] +pub struct SENSE4_R(crate::FieldReader); +impl SENSE4_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SENSE4_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE4_A::NONE), + 1 => Some(SENSE4_A::RISE), + 2 => Some(SENSE4_A::FALL), + 3 => Some(SENSE4_A::BOTH), + 4 => Some(SENSE4_A::HIGH), + 5 => Some(SENSE4_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == SENSE4_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == SENSE4_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == SENSE4_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == SENSE4_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SENSE4_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SENSE4_A::LOW + } +} +impl core::ops::Deref for SENSE4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SENSE4` writer - Input Sense Configuration 4"] +pub struct SENSE4_W<'a> { + w: &'a mut W, +} +impl<'a> SENSE4_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SENSE4_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE4_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE4_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE4_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE4_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE4_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE4_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 16)) | ((value as u32 & 0x07) << 16); + self.w + } +} +#[doc = "Field `FILTEN4` reader - Filter Enable 4"] +pub struct FILTEN4_R(crate::FieldReader); +impl FILTEN4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FILTEN4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTEN4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTEN4` writer - Filter Enable 4"] +pub struct FILTEN4_W<'a> { + w: &'a mut W, +} +impl<'a> FILTEN4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Input Sense Configuration 5\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE5_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE5_A) -> Self { + variant as _ + } +} +#[doc = "Field `SENSE5` reader - Input Sense Configuration 5"] +pub struct SENSE5_R(crate::FieldReader); +impl SENSE5_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SENSE5_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE5_A::NONE), + 1 => Some(SENSE5_A::RISE), + 2 => Some(SENSE5_A::FALL), + 3 => Some(SENSE5_A::BOTH), + 4 => Some(SENSE5_A::HIGH), + 5 => Some(SENSE5_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == SENSE5_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == SENSE5_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == SENSE5_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == SENSE5_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SENSE5_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SENSE5_A::LOW + } +} +impl core::ops::Deref for SENSE5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SENSE5` writer - Input Sense Configuration 5"] +pub struct SENSE5_W<'a> { + w: &'a mut W, +} +impl<'a> SENSE5_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SENSE5_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE5_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE5_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE5_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE5_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE5_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE5_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 20)) | ((value as u32 & 0x07) << 20); + self.w + } +} +#[doc = "Field `FILTEN5` reader - Filter Enable 5"] +pub struct FILTEN5_R(crate::FieldReader); +impl FILTEN5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FILTEN5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTEN5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTEN5` writer - Filter Enable 5"] +pub struct FILTEN5_W<'a> { + w: &'a mut W, +} +impl<'a> FILTEN5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Input Sense Configuration 6\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE6_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE6_A) -> Self { + variant as _ + } +} +#[doc = "Field `SENSE6` reader - Input Sense Configuration 6"] +pub struct SENSE6_R(crate::FieldReader); +impl SENSE6_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SENSE6_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE6_A::NONE), + 1 => Some(SENSE6_A::RISE), + 2 => Some(SENSE6_A::FALL), + 3 => Some(SENSE6_A::BOTH), + 4 => Some(SENSE6_A::HIGH), + 5 => Some(SENSE6_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == SENSE6_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == SENSE6_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == SENSE6_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == SENSE6_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SENSE6_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SENSE6_A::LOW + } +} +impl core::ops::Deref for SENSE6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SENSE6` writer - Input Sense Configuration 6"] +pub struct SENSE6_W<'a> { + w: &'a mut W, +} +impl<'a> SENSE6_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SENSE6_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE6_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE6_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE6_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE6_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE6_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE6_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 24)) | ((value as u32 & 0x07) << 24); + self.w + } +} +#[doc = "Field `FILTEN6` reader - Filter Enable 6"] +pub struct FILTEN6_R(crate::FieldReader); +impl FILTEN6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FILTEN6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTEN6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTEN6` writer - Filter Enable 6"] +pub struct FILTEN6_W<'a> { + w: &'a mut W, +} +impl<'a> FILTEN6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +#[doc = "Input Sense Configuration 7\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE7_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE7_A) -> Self { + variant as _ + } +} +#[doc = "Field `SENSE7` reader - Input Sense Configuration 7"] +pub struct SENSE7_R(crate::FieldReader); +impl SENSE7_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SENSE7_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE7_A::NONE), + 1 => Some(SENSE7_A::RISE), + 2 => Some(SENSE7_A::FALL), + 3 => Some(SENSE7_A::BOTH), + 4 => Some(SENSE7_A::HIGH), + 5 => Some(SENSE7_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == SENSE7_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == SENSE7_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == SENSE7_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == SENSE7_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SENSE7_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SENSE7_A::LOW + } +} +impl core::ops::Deref for SENSE7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SENSE7` writer - Input Sense Configuration 7"] +pub struct SENSE7_W<'a> { + w: &'a mut W, +} +impl<'a> SENSE7_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SENSE7_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE7_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE7_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE7_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE7_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE7_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE7_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 28)) | ((value as u32 & 0x07) << 28); + self.w + } +} +#[doc = "Field `FILTEN7` reader - Filter Enable 7"] +pub struct FILTEN7_R(crate::FieldReader); +impl FILTEN7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FILTEN7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTEN7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTEN7` writer - Filter Enable 7"] +pub struct FILTEN7_W<'a> { + w: &'a mut W, +} +impl<'a> FILTEN7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Input Sense Configuration 0"] + #[inline(always)] + pub fn sense0(&self) -> SENSE0_R { + SENSE0_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 3 - Filter Enable 0"] + #[inline(always)] + pub fn filten0(&self) -> FILTEN0_R { + FILTEN0_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bits 4:6 - Input Sense Configuration 1"] + #[inline(always)] + pub fn sense1(&self) -> SENSE1_R { + SENSE1_R::new(((self.bits >> 4) & 0x07) as u8) + } + #[doc = "Bit 7 - Filter Enable 1"] + #[inline(always)] + pub fn filten1(&self) -> FILTEN1_R { + FILTEN1_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Input Sense Configuration 2"] + #[inline(always)] + pub fn sense2(&self) -> SENSE2_R { + SENSE2_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 11 - Filter Enable 2"] + #[inline(always)] + pub fn filten2(&self) -> FILTEN2_R { + FILTEN2_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bits 12:14 - Input Sense Configuration 3"] + #[inline(always)] + pub fn sense3(&self) -> SENSE3_R { + SENSE3_R::new(((self.bits >> 12) & 0x07) as u8) + } + #[doc = "Bit 15 - Filter Enable 3"] + #[inline(always)] + pub fn filten3(&self) -> FILTEN3_R { + FILTEN3_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:18 - Input Sense Configuration 4"] + #[inline(always)] + pub fn sense4(&self) -> SENSE4_R { + SENSE4_R::new(((self.bits >> 16) & 0x07) as u8) + } + #[doc = "Bit 19 - Filter Enable 4"] + #[inline(always)] + pub fn filten4(&self) -> FILTEN4_R { + FILTEN4_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bits 20:22 - Input Sense Configuration 5"] + #[inline(always)] + pub fn sense5(&self) -> SENSE5_R { + SENSE5_R::new(((self.bits >> 20) & 0x07) as u8) + } + #[doc = "Bit 23 - Filter Enable 5"] + #[inline(always)] + pub fn filten5(&self) -> FILTEN5_R { + FILTEN5_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bits 24:26 - Input Sense Configuration 6"] + #[inline(always)] + pub fn sense6(&self) -> SENSE6_R { + SENSE6_R::new(((self.bits >> 24) & 0x07) as u8) + } + #[doc = "Bit 27 - Filter Enable 6"] + #[inline(always)] + pub fn filten6(&self) -> FILTEN6_R { + FILTEN6_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bits 28:30 - Input Sense Configuration 7"] + #[inline(always)] + pub fn sense7(&self) -> SENSE7_R { + SENSE7_R::new(((self.bits >> 28) & 0x07) as u8) + } + #[doc = "Bit 31 - Filter Enable 7"] + #[inline(always)] + pub fn filten7(&self) -> FILTEN7_R { + FILTEN7_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Input Sense Configuration 0"] + #[inline(always)] + pub fn sense0(&mut self) -> SENSE0_W { + SENSE0_W { w: self } + } + #[doc = "Bit 3 - Filter Enable 0"] + #[inline(always)] + pub fn filten0(&mut self) -> FILTEN0_W { + FILTEN0_W { w: self } + } + #[doc = "Bits 4:6 - Input Sense Configuration 1"] + #[inline(always)] + pub fn sense1(&mut self) -> SENSE1_W { + SENSE1_W { w: self } + } + #[doc = "Bit 7 - Filter Enable 1"] + #[inline(always)] + pub fn filten1(&mut self) -> FILTEN1_W { + FILTEN1_W { w: self } + } + #[doc = "Bits 8:10 - Input Sense Configuration 2"] + #[inline(always)] + pub fn sense2(&mut self) -> SENSE2_W { + SENSE2_W { w: self } + } + #[doc = "Bit 11 - Filter Enable 2"] + #[inline(always)] + pub fn filten2(&mut self) -> FILTEN2_W { + FILTEN2_W { w: self } + } + #[doc = "Bits 12:14 - Input Sense Configuration 3"] + #[inline(always)] + pub fn sense3(&mut self) -> SENSE3_W { + SENSE3_W { w: self } + } + #[doc = "Bit 15 - Filter Enable 3"] + #[inline(always)] + pub fn filten3(&mut self) -> FILTEN3_W { + FILTEN3_W { w: self } + } + #[doc = "Bits 16:18 - Input Sense Configuration 4"] + #[inline(always)] + pub fn sense4(&mut self) -> SENSE4_W { + SENSE4_W { w: self } + } + #[doc = "Bit 19 - Filter Enable 4"] + #[inline(always)] + pub fn filten4(&mut self) -> FILTEN4_W { + FILTEN4_W { w: self } + } + #[doc = "Bits 20:22 - Input Sense Configuration 5"] + #[inline(always)] + pub fn sense5(&mut self) -> SENSE5_W { + SENSE5_W { w: self } + } + #[doc = "Bit 23 - Filter Enable 5"] + #[inline(always)] + pub fn filten5(&mut self) -> FILTEN5_W { + FILTEN5_W { w: self } + } + #[doc = "Bits 24:26 - Input Sense Configuration 6"] + #[inline(always)] + pub fn sense6(&mut self) -> SENSE6_W { + SENSE6_W { w: self } + } + #[doc = "Bit 27 - Filter Enable 6"] + #[inline(always)] + pub fn filten6(&mut self) -> FILTEN6_W { + FILTEN6_W { w: self } + } + #[doc = "Bits 28:30 - Input Sense Configuration 7"] + #[inline(always)] + pub fn sense7(&mut self) -> SENSE7_W { + SENSE7_W { w: self } + } + #[doc = "Bit 31 - Filter Enable 7"] + #[inline(always)] + pub fn filten7(&mut self) -> FILTEN7_W { + FILTEN7_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "External Interrupt Sense Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [config](index.html) module"] +pub struct CONFIG_SPEC; +impl crate::RegisterSpec for CONFIG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [config::R](R) reader structure"] +impl crate::Readable for CONFIG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [config::W](W) writer structure"] +impl crate::Writable for CONFIG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CONFIG[%s] +to value 0"] +impl crate::Resettable for CONFIG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/eic/ctrla.rs b/pac/atsamc20n/src/eic/ctrla.rs new file mode 100644 index 000000000000..4e119fc05c61 --- /dev/null +++ b/pac/atsamc20n/src/eic/ctrla.rs @@ -0,0 +1,254 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Clock Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CKSEL_A { + #[doc = "0: Clocked by GCLK"] + CLK_GCLK = 0, + #[doc = "1: Clocked by ULP32K"] + CLK_ULP32K = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CKSEL_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CKSEL` reader - Clock Selection"] +pub struct CKSEL_R(crate::FieldReader); +impl CKSEL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CKSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CKSEL_A { + match self.bits { + false => CKSEL_A::CLK_GCLK, + true => CKSEL_A::CLK_ULP32K, + } + } + #[doc = "Checks if the value of the field is `CLK_GCLK`"] + #[inline(always)] + pub fn is_clk_gclk(&self) -> bool { + **self == CKSEL_A::CLK_GCLK + } + #[doc = "Checks if the value of the field is `CLK_ULP32K`"] + #[inline(always)] + pub fn is_clk_ulp32k(&self) -> bool { + **self == CKSEL_A::CLK_ULP32K + } +} +impl core::ops::Deref for CKSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CKSEL` writer - Clock Selection"] +pub struct CKSEL_W<'a> { + w: &'a mut W, +} +impl<'a> CKSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CKSEL_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Clocked by GCLK"] + #[inline(always)] + pub fn clk_gclk(self) -> &'a mut W { + self.variant(CKSEL_A::CLK_GCLK) + } + #[doc = "Clocked by ULP32K"] + #[inline(always)] + pub fn clk_ulp32k(self) -> &'a mut W { + self.variant(CKSEL_A::CLK_ULP32K) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - Clock Selection"] + #[inline(always)] + pub fn cksel(&self) -> CKSEL_R { + CKSEL_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 4 - Clock Selection"] + #[inline(always)] + pub fn cksel(&mut self) -> CKSEL_W { + CKSEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/eic/debouncen.rs b/pac/atsamc20n/src/eic/debouncen.rs new file mode 100644 index 000000000000..4861c11a8f28 --- /dev/null +++ b/pac/atsamc20n/src/eic/debouncen.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DEBOUNCEN` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DEBOUNCEN` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DEBOUNCEN` reader - Debouncer Enable"] +pub struct DEBOUNCEN_R(crate::FieldReader); +impl DEBOUNCEN_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + DEBOUNCEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DEBOUNCEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DEBOUNCEN` writer - Debouncer Enable"] +pub struct DEBOUNCEN_W<'a> { + w: &'a mut W, +} +impl<'a> DEBOUNCEN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Debouncer Enable"] + #[inline(always)] + pub fn debouncen(&self) -> DEBOUNCEN_R { + DEBOUNCEN_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Debouncer Enable"] + #[inline(always)] + pub fn debouncen(&mut self) -> DEBOUNCEN_W { + DEBOUNCEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debouncer Enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [debouncen](index.html) module"] +pub struct DEBOUNCEN_SPEC; +impl crate::RegisterSpec for DEBOUNCEN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [debouncen::R](R) reader structure"] +impl crate::Readable for DEBOUNCEN_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [debouncen::W](W) writer structure"] +impl crate::Writable for DEBOUNCEN_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DEBOUNCEN to value 0"] +impl crate::Resettable for DEBOUNCEN_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/eic/dprescaler.rs b/pac/atsamc20n/src/eic/dprescaler.rs new file mode 100644 index 000000000000..9a0c93b3e3e5 --- /dev/null +++ b/pac/atsamc20n/src/eic/dprescaler.rs @@ -0,0 +1,676 @@ +#[doc = "Register `DPRESCALER` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DPRESCALER` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Debouncer Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER0_A { + #[doc = "0: EIC clock divided by 2"] + DIV2 = 0, + #[doc = "1: EIC clock divided by 4"] + DIV4 = 1, + #[doc = "2: EIC clock divided by 8"] + DIV8 = 2, + #[doc = "3: EIC clock divided by 16"] + DIV16 = 3, + #[doc = "4: EIC clock divided by 32"] + DIV32 = 4, + #[doc = "5: EIC clock divided by 64"] + DIV64 = 5, + #[doc = "6: EIC clock divided by 128"] + DIV128 = 6, + #[doc = "7: EIC clock divided by 256"] + DIV256 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER0_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER0` reader - Debouncer Prescaler"] +pub struct PRESCALER0_R(crate::FieldReader); +impl PRESCALER0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PRESCALER0_A { + match self.bits { + 0 => PRESCALER0_A::DIV2, + 1 => PRESCALER0_A::DIV4, + 2 => PRESCALER0_A::DIV8, + 3 => PRESCALER0_A::DIV16, + 4 => PRESCALER0_A::DIV32, + 5 => PRESCALER0_A::DIV64, + 6 => PRESCALER0_A::DIV128, + 7 => PRESCALER0_A::DIV256, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER0_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER0_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER0_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER0_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == PRESCALER0_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER0_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == PRESCALER0_A::DIV128 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER0_A::DIV256 + } +} +impl core::ops::Deref for PRESCALER0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER0` writer - Debouncer Prescaler"] +pub struct PRESCALER0_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER0_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER0_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "EIC clock divided by 2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER0_A::DIV2) + } + #[doc = "EIC clock divided by 4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER0_A::DIV4) + } + #[doc = "EIC clock divided by 8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER0_A::DIV8) + } + #[doc = "EIC clock divided by 16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER0_A::DIV16) + } + #[doc = "EIC clock divided by 32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(PRESCALER0_A::DIV32) + } + #[doc = "EIC clock divided by 64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER0_A::DIV64) + } + #[doc = "EIC clock divided by 128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(PRESCALER0_A::DIV128) + } + #[doc = "EIC clock divided by 256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER0_A::DIV256) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Debouncer number of states\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum STATES0_A { + #[doc = "0: 3 low frequency samples"] + LFREQ3 = 0, + #[doc = "1: 7 low frequency samples"] + LFREQ7 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: STATES0_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STATES0` reader - Debouncer number of states"] +pub struct STATES0_R(crate::FieldReader); +impl STATES0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STATES0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STATES0_A { + match self.bits { + false => STATES0_A::LFREQ3, + true => STATES0_A::LFREQ7, + } + } + #[doc = "Checks if the value of the field is `LFREQ3`"] + #[inline(always)] + pub fn is_lfreq3(&self) -> bool { + **self == STATES0_A::LFREQ3 + } + #[doc = "Checks if the value of the field is `LFREQ7`"] + #[inline(always)] + pub fn is_lfreq7(&self) -> bool { + **self == STATES0_A::LFREQ7 + } +} +impl core::ops::Deref for STATES0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STATES0` writer - Debouncer number of states"] +pub struct STATES0_W<'a> { + w: &'a mut W, +} +impl<'a> STATES0_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: STATES0_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "3 low frequency samples"] + #[inline(always)] + pub fn lfreq3(self) -> &'a mut W { + self.variant(STATES0_A::LFREQ3) + } + #[doc = "7 low frequency samples"] + #[inline(always)] + pub fn lfreq7(self) -> &'a mut W { + self.variant(STATES0_A::LFREQ7) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Debouncer Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER1_A { + #[doc = "0: EIC clock divided by 2"] + DIV2 = 0, + #[doc = "1: EIC clock divided by 4"] + DIV4 = 1, + #[doc = "2: EIC clock divided by 8"] + DIV8 = 2, + #[doc = "3: EIC clock divided by 16"] + DIV16 = 3, + #[doc = "4: EIC clock divided by 32"] + DIV32 = 4, + #[doc = "5: EIC clock divided by 64"] + DIV64 = 5, + #[doc = "6: EIC clock divided by 128"] + DIV128 = 6, + #[doc = "7: EIC clock divided by 256"] + DIV256 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER1_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER1` reader - Debouncer Prescaler"] +pub struct PRESCALER1_R(crate::FieldReader); +impl PRESCALER1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER1_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PRESCALER1_A { + match self.bits { + 0 => PRESCALER1_A::DIV2, + 1 => PRESCALER1_A::DIV4, + 2 => PRESCALER1_A::DIV8, + 3 => PRESCALER1_A::DIV16, + 4 => PRESCALER1_A::DIV32, + 5 => PRESCALER1_A::DIV64, + 6 => PRESCALER1_A::DIV128, + 7 => PRESCALER1_A::DIV256, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER1_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER1_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER1_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER1_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == PRESCALER1_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER1_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == PRESCALER1_A::DIV128 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER1_A::DIV256 + } +} +impl core::ops::Deref for PRESCALER1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER1` writer - Debouncer Prescaler"] +pub struct PRESCALER1_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER1_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER1_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "EIC clock divided by 2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER1_A::DIV2) + } + #[doc = "EIC clock divided by 4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER1_A::DIV4) + } + #[doc = "EIC clock divided by 8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER1_A::DIV8) + } + #[doc = "EIC clock divided by 16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER1_A::DIV16) + } + #[doc = "EIC clock divided by 32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(PRESCALER1_A::DIV32) + } + #[doc = "EIC clock divided by 64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER1_A::DIV64) + } + #[doc = "EIC clock divided by 128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(PRESCALER1_A::DIV128) + } + #[doc = "EIC clock divided by 256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER1_A::DIV256) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 4)) | ((value as u32 & 0x07) << 4); + self.w + } +} +#[doc = "Debouncer number of states\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum STATES1_A { + #[doc = "0: 3 low frequency samples"] + LFREQ3 = 0, + #[doc = "1: 7 low frequency samples"] + LFREQ7 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: STATES1_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STATES1` reader - Debouncer number of states"] +pub struct STATES1_R(crate::FieldReader); +impl STATES1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STATES1_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STATES1_A { + match self.bits { + false => STATES1_A::LFREQ3, + true => STATES1_A::LFREQ7, + } + } + #[doc = "Checks if the value of the field is `LFREQ3`"] + #[inline(always)] + pub fn is_lfreq3(&self) -> bool { + **self == STATES1_A::LFREQ3 + } + #[doc = "Checks if the value of the field is `LFREQ7`"] + #[inline(always)] + pub fn is_lfreq7(&self) -> bool { + **self == STATES1_A::LFREQ7 + } +} +impl core::ops::Deref for STATES1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STATES1` writer - Debouncer number of states"] +pub struct STATES1_W<'a> { + w: &'a mut W, +} +impl<'a> STATES1_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: STATES1_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "3 low frequency samples"] + #[inline(always)] + pub fn lfreq3(self) -> &'a mut W { + self.variant(STATES1_A::LFREQ3) + } + #[doc = "7 low frequency samples"] + #[inline(always)] + pub fn lfreq7(self) -> &'a mut W { + self.variant(STATES1_A::LFREQ7) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Pin Sampler frequency selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TICKON_A { + #[doc = "0: Clocked by GCLK"] + CLK_GCLK_EIC = 0, + #[doc = "1: Clocked by Low Frequency Clock"] + CLK_LFREQ = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TICKON_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TICKON` reader - Pin Sampler frequency selection"] +pub struct TICKON_R(crate::FieldReader); +impl TICKON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TICKON_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TICKON_A { + match self.bits { + false => TICKON_A::CLK_GCLK_EIC, + true => TICKON_A::CLK_LFREQ, + } + } + #[doc = "Checks if the value of the field is `CLK_GCLK_EIC`"] + #[inline(always)] + pub fn is_clk_gclk_eic(&self) -> bool { + **self == TICKON_A::CLK_GCLK_EIC + } + #[doc = "Checks if the value of the field is `CLK_LFREQ`"] + #[inline(always)] + pub fn is_clk_lfreq(&self) -> bool { + **self == TICKON_A::CLK_LFREQ + } +} +impl core::ops::Deref for TICKON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TICKON` writer - Pin Sampler frequency selection"] +pub struct TICKON_W<'a> { + w: &'a mut W, +} +impl<'a> TICKON_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TICKON_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Clocked by GCLK"] + #[inline(always)] + pub fn clk_gclk_eic(self) -> &'a mut W { + self.variant(TICKON_A::CLK_GCLK_EIC) + } + #[doc = "Clocked by Low Frequency Clock"] + #[inline(always)] + pub fn clk_lfreq(self) -> &'a mut W { + self.variant(TICKON_A::CLK_LFREQ) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Debouncer Prescaler"] + #[inline(always)] + pub fn prescaler0(&self) -> PRESCALER0_R { + PRESCALER0_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 3 - Debouncer number of states"] + #[inline(always)] + pub fn states0(&self) -> STATES0_R { + STATES0_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bits 4:6 - Debouncer Prescaler"] + #[inline(always)] + pub fn prescaler1(&self) -> PRESCALER1_R { + PRESCALER1_R::new(((self.bits >> 4) & 0x07) as u8) + } + #[doc = "Bit 7 - Debouncer number of states"] + #[inline(always)] + pub fn states1(&self) -> STATES1_R { + STATES1_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 16 - Pin Sampler frequency selection"] + #[inline(always)] + pub fn tickon(&self) -> TICKON_R { + TICKON_R::new(((self.bits >> 16) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Debouncer Prescaler"] + #[inline(always)] + pub fn prescaler0(&mut self) -> PRESCALER0_W { + PRESCALER0_W { w: self } + } + #[doc = "Bit 3 - Debouncer number of states"] + #[inline(always)] + pub fn states0(&mut self) -> STATES0_W { + STATES0_W { w: self } + } + #[doc = "Bits 4:6 - Debouncer Prescaler"] + #[inline(always)] + pub fn prescaler1(&mut self) -> PRESCALER1_W { + PRESCALER1_W { w: self } + } + #[doc = "Bit 7 - Debouncer number of states"] + #[inline(always)] + pub fn states1(&mut self) -> STATES1_W { + STATES1_W { w: self } + } + #[doc = "Bit 16 - Pin Sampler frequency selection"] + #[inline(always)] + pub fn tickon(&mut self) -> TICKON_W { + TICKON_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debouncer Prescaler\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dprescaler](index.html) module"] +pub struct DPRESCALER_SPEC; +impl crate::RegisterSpec for DPRESCALER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dprescaler::R](R) reader structure"] +impl crate::Readable for DPRESCALER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dprescaler::W](W) writer structure"] +impl crate::Writable for DPRESCALER_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DPRESCALER to value 0"] +impl crate::Resettable for DPRESCALER_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/eic/evctrl.rs b/pac/atsamc20n/src/eic/evctrl.rs new file mode 100644 index 000000000000..25adccf3558e --- /dev/null +++ b/pac/atsamc20n/src/eic/evctrl.rs @@ -0,0 +1,103 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EXTINTEO` reader - External Interrupt Event Output Enable"] +pub struct EXTINTEO_R(crate::FieldReader); +impl EXTINTEO_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + EXTINTEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINTEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINTEO` writer - External Interrupt Event Output Enable"] +pub struct EXTINTEO_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINTEO_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - External Interrupt Event Output Enable"] + #[inline(always)] + pub fn extinteo(&self) -> EXTINTEO_R { + EXTINTEO_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - External Interrupt Event Output Enable"] + #[inline(always)] + pub fn extinteo(&mut self) -> EXTINTEO_W { + EXTINTEO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/eic/intenclr.rs b/pac/atsamc20n/src/eic/intenclr.rs new file mode 100644 index 000000000000..3d2675e0dfb8 --- /dev/null +++ b/pac/atsamc20n/src/eic/intenclr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EXTINT` reader - External Interrupt Enable"] +pub struct EXTINT_R(crate::FieldReader); +impl EXTINT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + EXTINT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT` writer - External Interrupt Enable"] +pub struct EXTINT_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - External Interrupt Enable"] + #[inline(always)] + pub fn extint(&self) -> EXTINT_R { + EXTINT_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - External Interrupt Enable"] + #[inline(always)] + pub fn extint(&mut self) -> EXTINT_W { + EXTINT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/eic/intenset.rs b/pac/atsamc20n/src/eic/intenset.rs new file mode 100644 index 000000000000..e2ff6729d71f --- /dev/null +++ b/pac/atsamc20n/src/eic/intenset.rs @@ -0,0 +1,103 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EXTINT` reader - External Interrupt Enable"] +pub struct EXTINT_R(crate::FieldReader); +impl EXTINT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + EXTINT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT` writer - External Interrupt Enable"] +pub struct EXTINT_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - External Interrupt Enable"] + #[inline(always)] + pub fn extint(&self) -> EXTINT_R { + EXTINT_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - External Interrupt Enable"] + #[inline(always)] + pub fn extint(&mut self) -> EXTINT_W { + EXTINT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/eic/intflag.rs b/pac/atsamc20n/src/eic/intflag.rs new file mode 100644 index 000000000000..c4a3ff581110 --- /dev/null +++ b/pac/atsamc20n/src/eic/intflag.rs @@ -0,0 +1,103 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EXTINT` reader - External Interrupt"] +pub struct EXTINT_R(crate::FieldReader); +impl EXTINT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + EXTINT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT` writer - External Interrupt"] +pub struct EXTINT_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - External Interrupt"] + #[inline(always)] + pub fn extint(&self) -> EXTINT_R { + EXTINT_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - External Interrupt"] + #[inline(always)] + pub fn extint(&mut self) -> EXTINT_W { + EXTINT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/eic/nmictrl.rs b/pac/atsamc20n/src/eic/nmictrl.rs new file mode 100644 index 000000000000..b80743e9e3e6 --- /dev/null +++ b/pac/atsamc20n/src/eic/nmictrl.rs @@ -0,0 +1,345 @@ +#[doc = "Register `NMICTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `NMICTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Non-Maskable Interrupt Sense Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum NMISENSE_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising-edge detection"] + RISE = 1, + #[doc = "2: Falling-edge detection"] + FALL = 2, + #[doc = "3: Both-edges detection"] + BOTH = 3, + #[doc = "4: High-level detection"] + HIGH = 4, + #[doc = "5: Low-level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: NMISENSE_A) -> Self { + variant as _ + } +} +#[doc = "Field `NMISENSE` reader - Non-Maskable Interrupt Sense Configuration"] +pub struct NMISENSE_R(crate::FieldReader); +impl NMISENSE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + NMISENSE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(NMISENSE_A::NONE), + 1 => Some(NMISENSE_A::RISE), + 2 => Some(NMISENSE_A::FALL), + 3 => Some(NMISENSE_A::BOTH), + 4 => Some(NMISENSE_A::HIGH), + 5 => Some(NMISENSE_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == NMISENSE_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == NMISENSE_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == NMISENSE_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == NMISENSE_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == NMISENSE_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == NMISENSE_A::LOW + } +} +impl core::ops::Deref for NMISENSE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NMISENSE` writer - Non-Maskable Interrupt Sense Configuration"] +pub struct NMISENSE_W<'a> { + w: &'a mut W, +} +impl<'a> NMISENSE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: NMISENSE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(NMISENSE_A::NONE) + } + #[doc = "Rising-edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(NMISENSE_A::RISE) + } + #[doc = "Falling-edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(NMISENSE_A::FALL) + } + #[doc = "Both-edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(NMISENSE_A::BOTH) + } + #[doc = "High-level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(NMISENSE_A::HIGH) + } + #[doc = "Low-level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(NMISENSE_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +#[doc = "Field `NMIFILTEN` reader - Non-Maskable Interrupt Filter Enable"] +pub struct NMIFILTEN_R(crate::FieldReader); +impl NMIFILTEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NMIFILTEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NMIFILTEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NMIFILTEN` writer - Non-Maskable Interrupt Filter Enable"] +pub struct NMIFILTEN_W<'a> { + w: &'a mut W, +} +impl<'a> NMIFILTEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Asynchronous Edge Detection Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum NMIASYNCH_A { + #[doc = "0: Edge detection is clock synchronously operated"] + SYNC = 0, + #[doc = "1: Edge detection is clock asynchronously operated"] + ASYNC = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NMIASYNCH_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NMIASYNCH` reader - Asynchronous Edge Detection Mode"] +pub struct NMIASYNCH_R(crate::FieldReader); +impl NMIASYNCH_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NMIASYNCH_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> NMIASYNCH_A { + match self.bits { + false => NMIASYNCH_A::SYNC, + true => NMIASYNCH_A::ASYNC, + } + } + #[doc = "Checks if the value of the field is `SYNC`"] + #[inline(always)] + pub fn is_sync(&self) -> bool { + **self == NMIASYNCH_A::SYNC + } + #[doc = "Checks if the value of the field is `ASYNC`"] + #[inline(always)] + pub fn is_async(&self) -> bool { + **self == NMIASYNCH_A::ASYNC + } +} +impl core::ops::Deref for NMIASYNCH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NMIASYNCH` writer - Asynchronous Edge Detection Mode"] +pub struct NMIASYNCH_W<'a> { + w: &'a mut W, +} +impl<'a> NMIASYNCH_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: NMIASYNCH_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Edge detection is clock synchronously operated"] + #[inline(always)] + pub fn sync(self) -> &'a mut W { + self.variant(NMIASYNCH_A::SYNC) + } + #[doc = "Edge detection is clock asynchronously operated"] + #[inline(always)] + pub fn async_(self) -> &'a mut W { + self.variant(NMIASYNCH_A::ASYNC) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Non-Maskable Interrupt Sense Configuration"] + #[inline(always)] + pub fn nmisense(&self) -> NMISENSE_R { + NMISENSE_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 3 - Non-Maskable Interrupt Filter Enable"] + #[inline(always)] + pub fn nmifilten(&self) -> NMIFILTEN_R { + NMIFILTEN_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Asynchronous Edge Detection Mode"] + #[inline(always)] + pub fn nmiasynch(&self) -> NMIASYNCH_R { + NMIASYNCH_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Non-Maskable Interrupt Sense Configuration"] + #[inline(always)] + pub fn nmisense(&mut self) -> NMISENSE_W { + NMISENSE_W { w: self } + } + #[doc = "Bit 3 - Non-Maskable Interrupt Filter Enable"] + #[inline(always)] + pub fn nmifilten(&mut self) -> NMIFILTEN_W { + NMIFILTEN_W { w: self } + } + #[doc = "Bit 4 - Asynchronous Edge Detection Mode"] + #[inline(always)] + pub fn nmiasynch(&mut self) -> NMIASYNCH_W { + NMIASYNCH_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Non-Maskable Interrupt Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [nmictrl](index.html) module"] +pub struct NMICTRL_SPEC; +impl crate::RegisterSpec for NMICTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [nmictrl::R](R) reader structure"] +impl crate::Readable for NMICTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [nmictrl::W](W) writer structure"] +impl crate::Writable for NMICTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets NMICTRL to value 0"] +impl crate::Resettable for NMICTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/eic/nmiflag.rs b/pac/atsamc20n/src/eic/nmiflag.rs new file mode 100644 index 000000000000..a373bb4b8d9c --- /dev/null +++ b/pac/atsamc20n/src/eic/nmiflag.rs @@ -0,0 +1,113 @@ +#[doc = "Register `NMIFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `NMIFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `NMI` reader - Non-Maskable Interrupt"] +pub struct NMI_R(crate::FieldReader); +impl NMI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NMI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NMI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NMI` writer - Non-Maskable Interrupt"] +pub struct NMI_W<'a> { + w: &'a mut W, +} +impl<'a> NMI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Non-Maskable Interrupt"] + #[inline(always)] + pub fn nmi(&self) -> NMI_R { + NMI_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Non-Maskable Interrupt"] + #[inline(always)] + pub fn nmi(&mut self) -> NMI_W { + NMI_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Non-Maskable Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [nmiflag](index.html) module"] +pub struct NMIFLAG_SPEC; +impl crate::RegisterSpec for NMIFLAG_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [nmiflag::R](R) reader structure"] +impl crate::Readable for NMIFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [nmiflag::W](W) writer structure"] +impl crate::Writable for NMIFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets NMIFLAG to value 0"] +impl crate::Resettable for NMIFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/eic/pinstate.rs b/pac/atsamc20n/src/eic/pinstate.rs new file mode 100644 index 000000000000..da07c8f57423 --- /dev/null +++ b/pac/atsamc20n/src/eic/pinstate.rs @@ -0,0 +1,53 @@ +#[doc = "Register `PINSTATE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PINSTATE` reader - Pin State"] +pub struct PINSTATE_R(crate::FieldReader); +impl PINSTATE_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + PINSTATE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PINSTATE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:15 - Pin State"] + #[inline(always)] + pub fn pinstate(&self) -> PINSTATE_R { + PINSTATE_R::new((self.bits & 0xffff) as u16) + } +} +#[doc = "Pin State\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pinstate](index.html) module"] +pub struct PINSTATE_SPEC; +impl crate::RegisterSpec for PINSTATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pinstate::R](R) reader structure"] +impl crate::Readable for PINSTATE_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PINSTATE to value 0"] +impl crate::Resettable for PINSTATE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/eic/syncbusy.rs b/pac/atsamc20n/src/eic/syncbusy.rs new file mode 100644 index 000000000000..fb4e99bcbcb0 --- /dev/null +++ b/pac/atsamc20n/src/eic/syncbusy.rs @@ -0,0 +1,73 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy Status"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - Enable Synchronization Busy Status"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy Status"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable Synchronization Busy Status"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +#[doc = "Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/evsys.rs b/pac/atsamc20n/src/evsys.rs new file mode 100644 index 000000000000..664de5fe9cab --- /dev/null +++ b/pac/atsamc20n/src/evsys.rs @@ -0,0 +1,54 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrla: crate::Reg, + _reserved1: [u8; 0x0b], + #[doc = "0x0c - Channel Status"] + pub chstatus: crate::Reg, + #[doc = "0x10 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x14 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x18 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x1c - Software Event"] + pub swevt: crate::Reg, + #[doc = "0x20..0x50 - Channel n"] + pub channel: [crate::Reg; 12], + _reserved7: [u8; 0x30], + #[doc = "0x80..0x148 - User Multiplexer n"] + pub user: [crate::Reg; 50], +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control"] +pub mod ctrla; +#[doc = "CHSTATUS register accessor: an alias for `Reg`"] +pub type CHSTATUS = crate::Reg; +#[doc = "Channel Status"] +pub mod chstatus; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "SWEVT register accessor: an alias for `Reg`"] +pub type SWEVT = crate::Reg; +#[doc = "Software Event"] +pub mod swevt; +#[doc = "CHANNEL register accessor: an alias for `Reg`"] +pub type CHANNEL = crate::Reg; +#[doc = "Channel n"] +pub mod channel; +#[doc = "USER register accessor: an alias for `Reg`"] +pub type USER = crate::Reg; +#[doc = "User Multiplexer n"] +pub mod user; diff --git a/pac/atsamc20n/src/evsys/channel.rs b/pac/atsamc20n/src/evsys/channel.rs new file mode 100644 index 000000000000..20e3857da922 --- /dev/null +++ b/pac/atsamc20n/src/evsys/channel.rs @@ -0,0 +1,409 @@ +#[doc = "Register `CHANNEL[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHANNEL[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVGEN` reader - Event Generator Selection"] +pub struct EVGEN_R(crate::FieldReader); +impl EVGEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVGEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVGEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVGEN` writer - Event Generator Selection"] +pub struct EVGEN_W<'a> { + w: &'a mut W, +} +impl<'a> EVGEN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x7f) | (value as u32 & 0x7f); + self.w + } +} +#[doc = "Path Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PATH_A { + #[doc = "0: Synchronous path"] + SYNCHRONOUS = 0, + #[doc = "1: Resynchronized path"] + RESYNCHRONIZED = 1, + #[doc = "2: Asynchronous path"] + ASYNCHRONOUS = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PATH_A) -> Self { + variant as _ + } +} +#[doc = "Field `PATH` reader - Path Selection"] +pub struct PATH_R(crate::FieldReader); +impl PATH_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PATH_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PATH_A::SYNCHRONOUS), + 1 => Some(PATH_A::RESYNCHRONIZED), + 2 => Some(PATH_A::ASYNCHRONOUS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `SYNCHRONOUS`"] + #[inline(always)] + pub fn is_synchronous(&self) -> bool { + **self == PATH_A::SYNCHRONOUS + } + #[doc = "Checks if the value of the field is `RESYNCHRONIZED`"] + #[inline(always)] + pub fn is_resynchronized(&self) -> bool { + **self == PATH_A::RESYNCHRONIZED + } + #[doc = "Checks if the value of the field is `ASYNCHRONOUS`"] + #[inline(always)] + pub fn is_asynchronous(&self) -> bool { + **self == PATH_A::ASYNCHRONOUS + } +} +impl core::ops::Deref for PATH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PATH` writer - Path Selection"] +pub struct PATH_W<'a> { + w: &'a mut W, +} +impl<'a> PATH_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PATH_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Synchronous path"] + #[inline(always)] + pub fn synchronous(self) -> &'a mut W { + self.variant(PATH_A::SYNCHRONOUS) + } + #[doc = "Resynchronized path"] + #[inline(always)] + pub fn resynchronized(self) -> &'a mut W { + self.variant(PATH_A::RESYNCHRONIZED) + } + #[doc = "Asynchronous path"] + #[inline(always)] + pub fn asynchronous(self) -> &'a mut W { + self.variant(PATH_A::ASYNCHRONOUS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 8)) | ((value as u32 & 0x03) << 8); + self.w + } +} +#[doc = "Edge Detection Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EDGSEL_A { + #[doc = "0: No event output when using the resynchronized or synchronous path"] + NO_EVT_OUTPUT = 0, + #[doc = "1: Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path"] + RISING_EDGE = 1, + #[doc = "2: Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path"] + FALLING_EDGE = 2, + #[doc = "3: Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path"] + BOTH_EDGES = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EDGSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `EDGSEL` reader - Edge Detection Selection"] +pub struct EDGSEL_R(crate::FieldReader); +impl EDGSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EDGSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EDGSEL_A { + match self.bits { + 0 => EDGSEL_A::NO_EVT_OUTPUT, + 1 => EDGSEL_A::RISING_EDGE, + 2 => EDGSEL_A::FALLING_EDGE, + 3 => EDGSEL_A::BOTH_EDGES, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NO_EVT_OUTPUT`"] + #[inline(always)] + pub fn is_no_evt_output(&self) -> bool { + **self == EDGSEL_A::NO_EVT_OUTPUT + } + #[doc = "Checks if the value of the field is `RISING_EDGE`"] + #[inline(always)] + pub fn is_rising_edge(&self) -> bool { + **self == EDGSEL_A::RISING_EDGE + } + #[doc = "Checks if the value of the field is `FALLING_EDGE`"] + #[inline(always)] + pub fn is_falling_edge(&self) -> bool { + **self == EDGSEL_A::FALLING_EDGE + } + #[doc = "Checks if the value of the field is `BOTH_EDGES`"] + #[inline(always)] + pub fn is_both_edges(&self) -> bool { + **self == EDGSEL_A::BOTH_EDGES + } +} +impl core::ops::Deref for EDGSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EDGSEL` writer - Edge Detection Selection"] +pub struct EDGSEL_W<'a> { + w: &'a mut W, +} +impl<'a> EDGSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EDGSEL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "No event output when using the resynchronized or synchronous path"] + #[inline(always)] + pub fn no_evt_output(self) -> &'a mut W { + self.variant(EDGSEL_A::NO_EVT_OUTPUT) + } + #[doc = "Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path"] + #[inline(always)] + pub fn rising_edge(self) -> &'a mut W { + self.variant(EDGSEL_A::RISING_EDGE) + } + #[doc = "Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path"] + #[inline(always)] + pub fn falling_edge(self) -> &'a mut W { + self.variant(EDGSEL_A::FALLING_EDGE) + } + #[doc = "Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path"] + #[inline(always)] + pub fn both_edges(self) -> &'a mut W { + self.variant(EDGSEL_A::BOTH_EDGES) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 10)) | ((value as u32 & 0x03) << 10); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - Generic Clock On Demand"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - Generic Clock On Demand"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bits 0:6 - Event Generator Selection"] + #[inline(always)] + pub fn evgen(&self) -> EVGEN_R { + EVGEN_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bits 8:9 - Path Selection"] + #[inline(always)] + pub fn path(&self) -> PATH_R { + PATH_R::new(((self.bits >> 8) & 0x03) as u8) + } + #[doc = "Bits 10:11 - Edge Detection Selection"] + #[inline(always)] + pub fn edgsel(&self) -> EDGSEL_R { + EDGSEL_R::new(((self.bits >> 10) & 0x03) as u8) + } + #[doc = "Bit 14 - Run in standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Generic Clock On Demand"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:6 - Event Generator Selection"] + #[inline(always)] + pub fn evgen(&mut self) -> EVGEN_W { + EVGEN_W { w: self } + } + #[doc = "Bits 8:9 - Path Selection"] + #[inline(always)] + pub fn path(&mut self) -> PATH_W { + PATH_W { w: self } + } + #[doc = "Bits 10:11 - Edge Detection Selection"] + #[inline(always)] + pub fn edgsel(&mut self) -> EDGSEL_W { + EDGSEL_W { w: self } + } + #[doc = "Bit 14 - Run in standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 15 - Generic Clock On Demand"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [channel](index.html) module"] +pub struct CHANNEL_SPEC; +impl crate::RegisterSpec for CHANNEL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [channel::R](R) reader structure"] +impl crate::Readable for CHANNEL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [channel::W](W) writer structure"] +impl crate::Writable for CHANNEL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHANNEL[%s] +to value 0x8000"] +impl crate::Resettable for CHANNEL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x8000 + } +} diff --git a/pac/atsamc20n/src/evsys/chstatus.rs b/pac/atsamc20n/src/evsys/chstatus.rs new file mode 100644 index 000000000000..811089dfdeb8 --- /dev/null +++ b/pac/atsamc20n/src/evsys/chstatus.rs @@ -0,0 +1,513 @@ +#[doc = "Register `CHSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `USRRDY0` reader - Channel 0 User Ready"] +pub struct USRRDY0_R(crate::FieldReader); +impl USRRDY0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY1` reader - Channel 1 User Ready"] +pub struct USRRDY1_R(crate::FieldReader); +impl USRRDY1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY2` reader - Channel 2 User Ready"] +pub struct USRRDY2_R(crate::FieldReader); +impl USRRDY2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY3` reader - Channel 3 User Ready"] +pub struct USRRDY3_R(crate::FieldReader); +impl USRRDY3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY4` reader - Channel 4 User Ready"] +pub struct USRRDY4_R(crate::FieldReader); +impl USRRDY4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY5` reader - Channel 5 User Ready"] +pub struct USRRDY5_R(crate::FieldReader); +impl USRRDY5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY6` reader - Channel 6 User Ready"] +pub struct USRRDY6_R(crate::FieldReader); +impl USRRDY6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY7` reader - Channel 7 User Ready"] +pub struct USRRDY7_R(crate::FieldReader); +impl USRRDY7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY8` reader - Channel 8 User Ready"] +pub struct USRRDY8_R(crate::FieldReader); +impl USRRDY8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY9` reader - Channel 9 User Ready"] +pub struct USRRDY9_R(crate::FieldReader); +impl USRRDY9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY10` reader - Channel 10 User Ready"] +pub struct USRRDY10_R(crate::FieldReader); +impl USRRDY10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY11` reader - Channel 11 User Ready"] +pub struct USRRDY11_R(crate::FieldReader); +impl USRRDY11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY0` reader - Channel 0 Busy"] +pub struct CHBUSY0_R(crate::FieldReader); +impl CHBUSY0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY1` reader - Channel 1 Busy"] +pub struct CHBUSY1_R(crate::FieldReader); +impl CHBUSY1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY2` reader - Channel 2 Busy"] +pub struct CHBUSY2_R(crate::FieldReader); +impl CHBUSY2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY3` reader - Channel 3 Busy"] +pub struct CHBUSY3_R(crate::FieldReader); +impl CHBUSY3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY4` reader - Channel 4 Busy"] +pub struct CHBUSY4_R(crate::FieldReader); +impl CHBUSY4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY5` reader - Channel 5 Busy"] +pub struct CHBUSY5_R(crate::FieldReader); +impl CHBUSY5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY6` reader - Channel 6 Busy"] +pub struct CHBUSY6_R(crate::FieldReader); +impl CHBUSY6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY7` reader - Channel 7 Busy"] +pub struct CHBUSY7_R(crate::FieldReader); +impl CHBUSY7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY8` reader - Channel 8 Busy"] +pub struct CHBUSY8_R(crate::FieldReader); +impl CHBUSY8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY9` reader - Channel 9 Busy"] +pub struct CHBUSY9_R(crate::FieldReader); +impl CHBUSY9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY10` reader - Channel 10 Busy"] +pub struct CHBUSY10_R(crate::FieldReader); +impl CHBUSY10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY11` reader - Channel 11 Busy"] +pub struct CHBUSY11_R(crate::FieldReader); +impl CHBUSY11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Channel 0 User Ready"] + #[inline(always)] + pub fn usrrdy0(&self) -> USRRDY0_R { + USRRDY0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel 1 User Ready"] + #[inline(always)] + pub fn usrrdy1(&self) -> USRRDY1_R { + USRRDY1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel 2 User Ready"] + #[inline(always)] + pub fn usrrdy2(&self) -> USRRDY2_R { + USRRDY2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Channel 3 User Ready"] + #[inline(always)] + pub fn usrrdy3(&self) -> USRRDY3_R { + USRRDY3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Channel 4 User Ready"] + #[inline(always)] + pub fn usrrdy4(&self) -> USRRDY4_R { + USRRDY4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Channel 5 User Ready"] + #[inline(always)] + pub fn usrrdy5(&self) -> USRRDY5_R { + USRRDY5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Channel 6 User Ready"] + #[inline(always)] + pub fn usrrdy6(&self) -> USRRDY6_R { + USRRDY6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Channel 7 User Ready"] + #[inline(always)] + pub fn usrrdy7(&self) -> USRRDY7_R { + USRRDY7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Channel 8 User Ready"] + #[inline(always)] + pub fn usrrdy8(&self) -> USRRDY8_R { + USRRDY8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Channel 9 User Ready"] + #[inline(always)] + pub fn usrrdy9(&self) -> USRRDY9_R { + USRRDY9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Channel 10 User Ready"] + #[inline(always)] + pub fn usrrdy10(&self) -> USRRDY10_R { + USRRDY10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Channel 11 User Ready"] + #[inline(always)] + pub fn usrrdy11(&self) -> USRRDY11_R { + USRRDY11_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 16 - Channel 0 Busy"] + #[inline(always)] + pub fn chbusy0(&self) -> CHBUSY0_R { + CHBUSY0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Channel 1 Busy"] + #[inline(always)] + pub fn chbusy1(&self) -> CHBUSY1_R { + CHBUSY1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Channel 2 Busy"] + #[inline(always)] + pub fn chbusy2(&self) -> CHBUSY2_R { + CHBUSY2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Channel 3 Busy"] + #[inline(always)] + pub fn chbusy3(&self) -> CHBUSY3_R { + CHBUSY3_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Channel 4 Busy"] + #[inline(always)] + pub fn chbusy4(&self) -> CHBUSY4_R { + CHBUSY4_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Channel 5 Busy"] + #[inline(always)] + pub fn chbusy5(&self) -> CHBUSY5_R { + CHBUSY5_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Channel 6 Busy"] + #[inline(always)] + pub fn chbusy6(&self) -> CHBUSY6_R { + CHBUSY6_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Channel 7 Busy"] + #[inline(always)] + pub fn chbusy7(&self) -> CHBUSY7_R { + CHBUSY7_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24 - Channel 8 Busy"] + #[inline(always)] + pub fn chbusy8(&self) -> CHBUSY8_R { + CHBUSY8_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Channel 9 Busy"] + #[inline(always)] + pub fn chbusy9(&self) -> CHBUSY9_R { + CHBUSY9_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Channel 10 Busy"] + #[inline(always)] + pub fn chbusy10(&self) -> CHBUSY10_R { + CHBUSY10_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Channel 11 Busy"] + #[inline(always)] + pub fn chbusy11(&self) -> CHBUSY11_R { + CHBUSY11_R::new(((self.bits >> 27) & 0x01) != 0) + } +} +#[doc = "Channel Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chstatus](index.html) module"] +pub struct CHSTATUS_SPEC; +impl crate::RegisterSpec for CHSTATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [chstatus::R](R) reader structure"] +impl crate::Readable for CHSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CHSTATUS to value 0"] +impl crate::Resettable for CHSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/evsys/ctrla.rs b/pac/atsamc20n/src/evsys/ctrla.rs new file mode 100644 index 000000000000..1c24704395ad --- /dev/null +++ b/pac/atsamc20n/src/evsys/ctrla.rs @@ -0,0 +1,113 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/evsys/intenclr.rs b/pac/atsamc20n/src/evsys/intenclr.rs new file mode 100644 index 000000000000..6a6a0b2b94c5 --- /dev/null +++ b/pac/atsamc20n/src/evsys/intenclr.rs @@ -0,0 +1,1194 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVR0` reader - Channel 0 Overrun Interrupt Enable"] +pub struct OVR0_R(crate::FieldReader); +impl OVR0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR0` writer - Channel 0 Overrun Interrupt Enable"] +pub struct OVR0_W<'a> { + w: &'a mut W, +} +impl<'a> OVR0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `OVR1` reader - Channel 1 Overrun Interrupt Enable"] +pub struct OVR1_R(crate::FieldReader); +impl OVR1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR1` writer - Channel 1 Overrun Interrupt Enable"] +pub struct OVR1_W<'a> { + w: &'a mut W, +} +impl<'a> OVR1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `OVR2` reader - Channel 2 Overrun Interrupt Enable"] +pub struct OVR2_R(crate::FieldReader); +impl OVR2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR2` writer - Channel 2 Overrun Interrupt Enable"] +pub struct OVR2_W<'a> { + w: &'a mut W, +} +impl<'a> OVR2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `OVR3` reader - Channel 3 Overrun Interrupt Enable"] +pub struct OVR3_R(crate::FieldReader); +impl OVR3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR3` writer - Channel 3 Overrun Interrupt Enable"] +pub struct OVR3_W<'a> { + w: &'a mut W, +} +impl<'a> OVR3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `OVR4` reader - Channel 4 Overrun Interrupt Enable"] +pub struct OVR4_R(crate::FieldReader); +impl OVR4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR4` writer - Channel 4 Overrun Interrupt Enable"] +pub struct OVR4_W<'a> { + w: &'a mut W, +} +impl<'a> OVR4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `OVR5` reader - Channel 5 Overrun Interrupt Enable"] +pub struct OVR5_R(crate::FieldReader); +impl OVR5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR5` writer - Channel 5 Overrun Interrupt Enable"] +pub struct OVR5_W<'a> { + w: &'a mut W, +} +impl<'a> OVR5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `OVR6` reader - Channel 6 Overrun Interrupt Enable"] +pub struct OVR6_R(crate::FieldReader); +impl OVR6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR6` writer - Channel 6 Overrun Interrupt Enable"] +pub struct OVR6_W<'a> { + w: &'a mut W, +} +impl<'a> OVR6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `OVR7` reader - Channel 7 Overrun Interrupt Enable"] +pub struct OVR7_R(crate::FieldReader); +impl OVR7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR7` writer - Channel 7 Overrun Interrupt Enable"] +pub struct OVR7_W<'a> { + w: &'a mut W, +} +impl<'a> OVR7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `OVR8` reader - Channel 8 Overrun Interrupt Enable"] +pub struct OVR8_R(crate::FieldReader); +impl OVR8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR8` writer - Channel 8 Overrun Interrupt Enable"] +pub struct OVR8_W<'a> { + w: &'a mut W, +} +impl<'a> OVR8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `OVR9` reader - Channel 9 Overrun Interrupt Enable"] +pub struct OVR9_R(crate::FieldReader); +impl OVR9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR9` writer - Channel 9 Overrun Interrupt Enable"] +pub struct OVR9_W<'a> { + w: &'a mut W, +} +impl<'a> OVR9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `OVR10` reader - Channel 10 Overrun Interrupt Enable"] +pub struct OVR10_R(crate::FieldReader); +impl OVR10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR10` writer - Channel 10 Overrun Interrupt Enable"] +pub struct OVR10_W<'a> { + w: &'a mut W, +} +impl<'a> OVR10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `OVR11` reader - Channel 11 Overrun Interrupt Enable"] +pub struct OVR11_R(crate::FieldReader); +impl OVR11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR11` writer - Channel 11 Overrun Interrupt Enable"] +pub struct OVR11_W<'a> { + w: &'a mut W, +} +impl<'a> OVR11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `EVD0` reader - Channel 0 Event Detection Interrupt Enable"] +pub struct EVD0_R(crate::FieldReader); +impl EVD0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD0` writer - Channel 0 Event Detection Interrupt Enable"] +pub struct EVD0_W<'a> { + w: &'a mut W, +} +impl<'a> EVD0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `EVD1` reader - Channel 1 Event Detection Interrupt Enable"] +pub struct EVD1_R(crate::FieldReader); +impl EVD1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD1` writer - Channel 1 Event Detection Interrupt Enable"] +pub struct EVD1_W<'a> { + w: &'a mut W, +} +impl<'a> EVD1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `EVD2` reader - Channel 2 Event Detection Interrupt Enable"] +pub struct EVD2_R(crate::FieldReader); +impl EVD2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD2` writer - Channel 2 Event Detection Interrupt Enable"] +pub struct EVD2_W<'a> { + w: &'a mut W, +} +impl<'a> EVD2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `EVD3` reader - Channel 3 Event Detection Interrupt Enable"] +pub struct EVD3_R(crate::FieldReader); +impl EVD3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD3` writer - Channel 3 Event Detection Interrupt Enable"] +pub struct EVD3_W<'a> { + w: &'a mut W, +} +impl<'a> EVD3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `EVD4` reader - Channel 4 Event Detection Interrupt Enable"] +pub struct EVD4_R(crate::FieldReader); +impl EVD4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD4` writer - Channel 4 Event Detection Interrupt Enable"] +pub struct EVD4_W<'a> { + w: &'a mut W, +} +impl<'a> EVD4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `EVD5` reader - Channel 5 Event Detection Interrupt Enable"] +pub struct EVD5_R(crate::FieldReader); +impl EVD5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD5` writer - Channel 5 Event Detection Interrupt Enable"] +pub struct EVD5_W<'a> { + w: &'a mut W, +} +impl<'a> EVD5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `EVD6` reader - Channel 6 Event Detection Interrupt Enable"] +pub struct EVD6_R(crate::FieldReader); +impl EVD6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD6` writer - Channel 6 Event Detection Interrupt Enable"] +pub struct EVD6_W<'a> { + w: &'a mut W, +} +impl<'a> EVD6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `EVD7` reader - Channel 7 Event Detection Interrupt Enable"] +pub struct EVD7_R(crate::FieldReader); +impl EVD7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD7` writer - Channel 7 Event Detection Interrupt Enable"] +pub struct EVD7_W<'a> { + w: &'a mut W, +} +impl<'a> EVD7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `EVD8` reader - Channel 8 Event Detection Interrupt Enable"] +pub struct EVD8_R(crate::FieldReader); +impl EVD8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD8` writer - Channel 8 Event Detection Interrupt Enable"] +pub struct EVD8_W<'a> { + w: &'a mut W, +} +impl<'a> EVD8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `EVD9` reader - Channel 9 Event Detection Interrupt Enable"] +pub struct EVD9_R(crate::FieldReader); +impl EVD9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD9` writer - Channel 9 Event Detection Interrupt Enable"] +pub struct EVD9_W<'a> { + w: &'a mut W, +} +impl<'a> EVD9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `EVD10` reader - Channel 10 Event Detection Interrupt Enable"] +pub struct EVD10_R(crate::FieldReader); +impl EVD10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD10` writer - Channel 10 Event Detection Interrupt Enable"] +pub struct EVD10_W<'a> { + w: &'a mut W, +} +impl<'a> EVD10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `EVD11` reader - Channel 11 Event Detection Interrupt Enable"] +pub struct EVD11_R(crate::FieldReader); +impl EVD11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD11` writer - Channel 11 Event Detection Interrupt Enable"] +pub struct EVD11_W<'a> { + w: &'a mut W, +} +impl<'a> EVD11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +impl R { + #[doc = "Bit 0 - Channel 0 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr0(&self) -> OVR0_R { + OVR0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel 1 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr1(&self) -> OVR1_R { + OVR1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel 2 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr2(&self) -> OVR2_R { + OVR2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Channel 3 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr3(&self) -> OVR3_R { + OVR3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Channel 4 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr4(&self) -> OVR4_R { + OVR4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Channel 5 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr5(&self) -> OVR5_R { + OVR5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Channel 6 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr6(&self) -> OVR6_R { + OVR6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Channel 7 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr7(&self) -> OVR7_R { + OVR7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Channel 8 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr8(&self) -> OVR8_R { + OVR8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Channel 9 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr9(&self) -> OVR9_R { + OVR9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Channel 10 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr10(&self) -> OVR10_R { + OVR10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Channel 11 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr11(&self) -> OVR11_R { + OVR11_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 16 - Channel 0 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd0(&self) -> EVD0_R { + EVD0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Channel 1 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd1(&self) -> EVD1_R { + EVD1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Channel 2 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd2(&self) -> EVD2_R { + EVD2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Channel 3 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd3(&self) -> EVD3_R { + EVD3_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Channel 4 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd4(&self) -> EVD4_R { + EVD4_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Channel 5 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd5(&self) -> EVD5_R { + EVD5_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Channel 6 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd6(&self) -> EVD6_R { + EVD6_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Channel 7 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd7(&self) -> EVD7_R { + EVD7_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24 - Channel 8 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd8(&self) -> EVD8_R { + EVD8_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Channel 9 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd9(&self) -> EVD9_R { + EVD9_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Channel 10 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd10(&self) -> EVD10_R { + EVD10_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Channel 11 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd11(&self) -> EVD11_R { + EVD11_R::new(((self.bits >> 27) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel 0 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr0(&mut self) -> OVR0_W { + OVR0_W { w: self } + } + #[doc = "Bit 1 - Channel 1 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr1(&mut self) -> OVR1_W { + OVR1_W { w: self } + } + #[doc = "Bit 2 - Channel 2 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr2(&mut self) -> OVR2_W { + OVR2_W { w: self } + } + #[doc = "Bit 3 - Channel 3 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr3(&mut self) -> OVR3_W { + OVR3_W { w: self } + } + #[doc = "Bit 4 - Channel 4 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr4(&mut self) -> OVR4_W { + OVR4_W { w: self } + } + #[doc = "Bit 5 - Channel 5 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr5(&mut self) -> OVR5_W { + OVR5_W { w: self } + } + #[doc = "Bit 6 - Channel 6 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr6(&mut self) -> OVR6_W { + OVR6_W { w: self } + } + #[doc = "Bit 7 - Channel 7 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr7(&mut self) -> OVR7_W { + OVR7_W { w: self } + } + #[doc = "Bit 8 - Channel 8 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr8(&mut self) -> OVR8_W { + OVR8_W { w: self } + } + #[doc = "Bit 9 - Channel 9 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr9(&mut self) -> OVR9_W { + OVR9_W { w: self } + } + #[doc = "Bit 10 - Channel 10 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr10(&mut self) -> OVR10_W { + OVR10_W { w: self } + } + #[doc = "Bit 11 - Channel 11 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr11(&mut self) -> OVR11_W { + OVR11_W { w: self } + } + #[doc = "Bit 16 - Channel 0 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd0(&mut self) -> EVD0_W { + EVD0_W { w: self } + } + #[doc = "Bit 17 - Channel 1 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd1(&mut self) -> EVD1_W { + EVD1_W { w: self } + } + #[doc = "Bit 18 - Channel 2 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd2(&mut self) -> EVD2_W { + EVD2_W { w: self } + } + #[doc = "Bit 19 - Channel 3 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd3(&mut self) -> EVD3_W { + EVD3_W { w: self } + } + #[doc = "Bit 20 - Channel 4 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd4(&mut self) -> EVD4_W { + EVD4_W { w: self } + } + #[doc = "Bit 21 - Channel 5 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd5(&mut self) -> EVD5_W { + EVD5_W { w: self } + } + #[doc = "Bit 22 - Channel 6 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd6(&mut self) -> EVD6_W { + EVD6_W { w: self } + } + #[doc = "Bit 23 - Channel 7 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd7(&mut self) -> EVD7_W { + EVD7_W { w: self } + } + #[doc = "Bit 24 - Channel 8 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd8(&mut self) -> EVD8_W { + EVD8_W { w: self } + } + #[doc = "Bit 25 - Channel 9 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd9(&mut self) -> EVD9_W { + EVD9_W { w: self } + } + #[doc = "Bit 26 - Channel 10 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd10(&mut self) -> EVD10_W { + EVD10_W { w: self } + } + #[doc = "Bit 27 - Channel 11 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd11(&mut self) -> EVD11_W { + EVD11_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/evsys/intenset.rs b/pac/atsamc20n/src/evsys/intenset.rs new file mode 100644 index 000000000000..d84061297909 --- /dev/null +++ b/pac/atsamc20n/src/evsys/intenset.rs @@ -0,0 +1,1194 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVR0` reader - Channel 0 Overrun Interrupt Enable"] +pub struct OVR0_R(crate::FieldReader); +impl OVR0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR0` writer - Channel 0 Overrun Interrupt Enable"] +pub struct OVR0_W<'a> { + w: &'a mut W, +} +impl<'a> OVR0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `OVR1` reader - Channel 1 Overrun Interrupt Enable"] +pub struct OVR1_R(crate::FieldReader); +impl OVR1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR1` writer - Channel 1 Overrun Interrupt Enable"] +pub struct OVR1_W<'a> { + w: &'a mut W, +} +impl<'a> OVR1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `OVR2` reader - Channel 2 Overrun Interrupt Enable"] +pub struct OVR2_R(crate::FieldReader); +impl OVR2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR2` writer - Channel 2 Overrun Interrupt Enable"] +pub struct OVR2_W<'a> { + w: &'a mut W, +} +impl<'a> OVR2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `OVR3` reader - Channel 3 Overrun Interrupt Enable"] +pub struct OVR3_R(crate::FieldReader); +impl OVR3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR3` writer - Channel 3 Overrun Interrupt Enable"] +pub struct OVR3_W<'a> { + w: &'a mut W, +} +impl<'a> OVR3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `OVR4` reader - Channel 4 Overrun Interrupt Enable"] +pub struct OVR4_R(crate::FieldReader); +impl OVR4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR4` writer - Channel 4 Overrun Interrupt Enable"] +pub struct OVR4_W<'a> { + w: &'a mut W, +} +impl<'a> OVR4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `OVR5` reader - Channel 5 Overrun Interrupt Enable"] +pub struct OVR5_R(crate::FieldReader); +impl OVR5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR5` writer - Channel 5 Overrun Interrupt Enable"] +pub struct OVR5_W<'a> { + w: &'a mut W, +} +impl<'a> OVR5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `OVR6` reader - Channel 6 Overrun Interrupt Enable"] +pub struct OVR6_R(crate::FieldReader); +impl OVR6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR6` writer - Channel 6 Overrun Interrupt Enable"] +pub struct OVR6_W<'a> { + w: &'a mut W, +} +impl<'a> OVR6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `OVR7` reader - Channel 7 Overrun Interrupt Enable"] +pub struct OVR7_R(crate::FieldReader); +impl OVR7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR7` writer - Channel 7 Overrun Interrupt Enable"] +pub struct OVR7_W<'a> { + w: &'a mut W, +} +impl<'a> OVR7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `OVR8` reader - Channel 8 Overrun Interrupt Enable"] +pub struct OVR8_R(crate::FieldReader); +impl OVR8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR8` writer - Channel 8 Overrun Interrupt Enable"] +pub struct OVR8_W<'a> { + w: &'a mut W, +} +impl<'a> OVR8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `OVR9` reader - Channel 9 Overrun Interrupt Enable"] +pub struct OVR9_R(crate::FieldReader); +impl OVR9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR9` writer - Channel 9 Overrun Interrupt Enable"] +pub struct OVR9_W<'a> { + w: &'a mut W, +} +impl<'a> OVR9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `OVR10` reader - Channel 10 Overrun Interrupt Enable"] +pub struct OVR10_R(crate::FieldReader); +impl OVR10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR10` writer - Channel 10 Overrun Interrupt Enable"] +pub struct OVR10_W<'a> { + w: &'a mut W, +} +impl<'a> OVR10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `OVR11` reader - Channel 11 Overrun Interrupt Enable"] +pub struct OVR11_R(crate::FieldReader); +impl OVR11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR11` writer - Channel 11 Overrun Interrupt Enable"] +pub struct OVR11_W<'a> { + w: &'a mut W, +} +impl<'a> OVR11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `EVD0` reader - Channel 0 Event Detection Interrupt Enable"] +pub struct EVD0_R(crate::FieldReader); +impl EVD0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD0` writer - Channel 0 Event Detection Interrupt Enable"] +pub struct EVD0_W<'a> { + w: &'a mut W, +} +impl<'a> EVD0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `EVD1` reader - Channel 1 Event Detection Interrupt Enable"] +pub struct EVD1_R(crate::FieldReader); +impl EVD1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD1` writer - Channel 1 Event Detection Interrupt Enable"] +pub struct EVD1_W<'a> { + w: &'a mut W, +} +impl<'a> EVD1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `EVD2` reader - Channel 2 Event Detection Interrupt Enable"] +pub struct EVD2_R(crate::FieldReader); +impl EVD2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD2` writer - Channel 2 Event Detection Interrupt Enable"] +pub struct EVD2_W<'a> { + w: &'a mut W, +} +impl<'a> EVD2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `EVD3` reader - Channel 3 Event Detection Interrupt Enable"] +pub struct EVD3_R(crate::FieldReader); +impl EVD3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD3` writer - Channel 3 Event Detection Interrupt Enable"] +pub struct EVD3_W<'a> { + w: &'a mut W, +} +impl<'a> EVD3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `EVD4` reader - Channel 4 Event Detection Interrupt Enable"] +pub struct EVD4_R(crate::FieldReader); +impl EVD4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD4` writer - Channel 4 Event Detection Interrupt Enable"] +pub struct EVD4_W<'a> { + w: &'a mut W, +} +impl<'a> EVD4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `EVD5` reader - Channel 5 Event Detection Interrupt Enable"] +pub struct EVD5_R(crate::FieldReader); +impl EVD5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD5` writer - Channel 5 Event Detection Interrupt Enable"] +pub struct EVD5_W<'a> { + w: &'a mut W, +} +impl<'a> EVD5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `EVD6` reader - Channel 6 Event Detection Interrupt Enable"] +pub struct EVD6_R(crate::FieldReader); +impl EVD6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD6` writer - Channel 6 Event Detection Interrupt Enable"] +pub struct EVD6_W<'a> { + w: &'a mut W, +} +impl<'a> EVD6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `EVD7` reader - Channel 7 Event Detection Interrupt Enable"] +pub struct EVD7_R(crate::FieldReader); +impl EVD7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD7` writer - Channel 7 Event Detection Interrupt Enable"] +pub struct EVD7_W<'a> { + w: &'a mut W, +} +impl<'a> EVD7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `EVD8` reader - Channel 8 Event Detection Interrupt Enable"] +pub struct EVD8_R(crate::FieldReader); +impl EVD8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD8` writer - Channel 8 Event Detection Interrupt Enable"] +pub struct EVD8_W<'a> { + w: &'a mut W, +} +impl<'a> EVD8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `EVD9` reader - Channel 9 Event Detection Interrupt Enable"] +pub struct EVD9_R(crate::FieldReader); +impl EVD9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD9` writer - Channel 9 Event Detection Interrupt Enable"] +pub struct EVD9_W<'a> { + w: &'a mut W, +} +impl<'a> EVD9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `EVD10` reader - Channel 10 Event Detection Interrupt Enable"] +pub struct EVD10_R(crate::FieldReader); +impl EVD10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD10` writer - Channel 10 Event Detection Interrupt Enable"] +pub struct EVD10_W<'a> { + w: &'a mut W, +} +impl<'a> EVD10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `EVD11` reader - Channel 11 Event Detection Interrupt Enable"] +pub struct EVD11_R(crate::FieldReader); +impl EVD11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD11` writer - Channel 11 Event Detection Interrupt Enable"] +pub struct EVD11_W<'a> { + w: &'a mut W, +} +impl<'a> EVD11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +impl R { + #[doc = "Bit 0 - Channel 0 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr0(&self) -> OVR0_R { + OVR0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel 1 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr1(&self) -> OVR1_R { + OVR1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel 2 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr2(&self) -> OVR2_R { + OVR2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Channel 3 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr3(&self) -> OVR3_R { + OVR3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Channel 4 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr4(&self) -> OVR4_R { + OVR4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Channel 5 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr5(&self) -> OVR5_R { + OVR5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Channel 6 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr6(&self) -> OVR6_R { + OVR6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Channel 7 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr7(&self) -> OVR7_R { + OVR7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Channel 8 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr8(&self) -> OVR8_R { + OVR8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Channel 9 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr9(&self) -> OVR9_R { + OVR9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Channel 10 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr10(&self) -> OVR10_R { + OVR10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Channel 11 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr11(&self) -> OVR11_R { + OVR11_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 16 - Channel 0 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd0(&self) -> EVD0_R { + EVD0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Channel 1 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd1(&self) -> EVD1_R { + EVD1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Channel 2 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd2(&self) -> EVD2_R { + EVD2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Channel 3 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd3(&self) -> EVD3_R { + EVD3_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Channel 4 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd4(&self) -> EVD4_R { + EVD4_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Channel 5 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd5(&self) -> EVD5_R { + EVD5_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Channel 6 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd6(&self) -> EVD6_R { + EVD6_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Channel 7 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd7(&self) -> EVD7_R { + EVD7_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24 - Channel 8 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd8(&self) -> EVD8_R { + EVD8_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Channel 9 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd9(&self) -> EVD9_R { + EVD9_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Channel 10 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd10(&self) -> EVD10_R { + EVD10_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Channel 11 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd11(&self) -> EVD11_R { + EVD11_R::new(((self.bits >> 27) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel 0 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr0(&mut self) -> OVR0_W { + OVR0_W { w: self } + } + #[doc = "Bit 1 - Channel 1 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr1(&mut self) -> OVR1_W { + OVR1_W { w: self } + } + #[doc = "Bit 2 - Channel 2 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr2(&mut self) -> OVR2_W { + OVR2_W { w: self } + } + #[doc = "Bit 3 - Channel 3 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr3(&mut self) -> OVR3_W { + OVR3_W { w: self } + } + #[doc = "Bit 4 - Channel 4 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr4(&mut self) -> OVR4_W { + OVR4_W { w: self } + } + #[doc = "Bit 5 - Channel 5 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr5(&mut self) -> OVR5_W { + OVR5_W { w: self } + } + #[doc = "Bit 6 - Channel 6 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr6(&mut self) -> OVR6_W { + OVR6_W { w: self } + } + #[doc = "Bit 7 - Channel 7 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr7(&mut self) -> OVR7_W { + OVR7_W { w: self } + } + #[doc = "Bit 8 - Channel 8 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr8(&mut self) -> OVR8_W { + OVR8_W { w: self } + } + #[doc = "Bit 9 - Channel 9 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr9(&mut self) -> OVR9_W { + OVR9_W { w: self } + } + #[doc = "Bit 10 - Channel 10 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr10(&mut self) -> OVR10_W { + OVR10_W { w: self } + } + #[doc = "Bit 11 - Channel 11 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr11(&mut self) -> OVR11_W { + OVR11_W { w: self } + } + #[doc = "Bit 16 - Channel 0 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd0(&mut self) -> EVD0_W { + EVD0_W { w: self } + } + #[doc = "Bit 17 - Channel 1 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd1(&mut self) -> EVD1_W { + EVD1_W { w: self } + } + #[doc = "Bit 18 - Channel 2 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd2(&mut self) -> EVD2_W { + EVD2_W { w: self } + } + #[doc = "Bit 19 - Channel 3 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd3(&mut self) -> EVD3_W { + EVD3_W { w: self } + } + #[doc = "Bit 20 - Channel 4 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd4(&mut self) -> EVD4_W { + EVD4_W { w: self } + } + #[doc = "Bit 21 - Channel 5 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd5(&mut self) -> EVD5_W { + EVD5_W { w: self } + } + #[doc = "Bit 22 - Channel 6 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd6(&mut self) -> EVD6_W { + EVD6_W { w: self } + } + #[doc = "Bit 23 - Channel 7 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd7(&mut self) -> EVD7_W { + EVD7_W { w: self } + } + #[doc = "Bit 24 - Channel 8 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd8(&mut self) -> EVD8_W { + EVD8_W { w: self } + } + #[doc = "Bit 25 - Channel 9 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd9(&mut self) -> EVD9_W { + EVD9_W { w: self } + } + #[doc = "Bit 26 - Channel 10 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd10(&mut self) -> EVD10_W { + EVD10_W { w: self } + } + #[doc = "Bit 27 - Channel 11 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd11(&mut self) -> EVD11_W { + EVD11_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/evsys/intflag.rs b/pac/atsamc20n/src/evsys/intflag.rs new file mode 100644 index 000000000000..4d5cbe3950f6 --- /dev/null +++ b/pac/atsamc20n/src/evsys/intflag.rs @@ -0,0 +1,1194 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVR0` reader - Channel 0 Overrun"] +pub struct OVR0_R(crate::FieldReader); +impl OVR0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR0` writer - Channel 0 Overrun"] +pub struct OVR0_W<'a> { + w: &'a mut W, +} +impl<'a> OVR0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `OVR1` reader - Channel 1 Overrun"] +pub struct OVR1_R(crate::FieldReader); +impl OVR1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR1` writer - Channel 1 Overrun"] +pub struct OVR1_W<'a> { + w: &'a mut W, +} +impl<'a> OVR1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `OVR2` reader - Channel 2 Overrun"] +pub struct OVR2_R(crate::FieldReader); +impl OVR2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR2` writer - Channel 2 Overrun"] +pub struct OVR2_W<'a> { + w: &'a mut W, +} +impl<'a> OVR2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `OVR3` reader - Channel 3 Overrun"] +pub struct OVR3_R(crate::FieldReader); +impl OVR3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR3` writer - Channel 3 Overrun"] +pub struct OVR3_W<'a> { + w: &'a mut W, +} +impl<'a> OVR3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `OVR4` reader - Channel 4 Overrun"] +pub struct OVR4_R(crate::FieldReader); +impl OVR4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR4` writer - Channel 4 Overrun"] +pub struct OVR4_W<'a> { + w: &'a mut W, +} +impl<'a> OVR4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `OVR5` reader - Channel 5 Overrun"] +pub struct OVR5_R(crate::FieldReader); +impl OVR5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR5` writer - Channel 5 Overrun"] +pub struct OVR5_W<'a> { + w: &'a mut W, +} +impl<'a> OVR5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `OVR6` reader - Channel 6 Overrun"] +pub struct OVR6_R(crate::FieldReader); +impl OVR6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR6` writer - Channel 6 Overrun"] +pub struct OVR6_W<'a> { + w: &'a mut W, +} +impl<'a> OVR6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `OVR7` reader - Channel 7 Overrun"] +pub struct OVR7_R(crate::FieldReader); +impl OVR7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR7` writer - Channel 7 Overrun"] +pub struct OVR7_W<'a> { + w: &'a mut W, +} +impl<'a> OVR7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `OVR8` reader - Channel 8 Overrun"] +pub struct OVR8_R(crate::FieldReader); +impl OVR8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR8` writer - Channel 8 Overrun"] +pub struct OVR8_W<'a> { + w: &'a mut W, +} +impl<'a> OVR8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `OVR9` reader - Channel 9 Overrun"] +pub struct OVR9_R(crate::FieldReader); +impl OVR9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR9` writer - Channel 9 Overrun"] +pub struct OVR9_W<'a> { + w: &'a mut W, +} +impl<'a> OVR9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `OVR10` reader - Channel 10 Overrun"] +pub struct OVR10_R(crate::FieldReader); +impl OVR10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR10` writer - Channel 10 Overrun"] +pub struct OVR10_W<'a> { + w: &'a mut W, +} +impl<'a> OVR10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `OVR11` reader - Channel 11 Overrun"] +pub struct OVR11_R(crate::FieldReader); +impl OVR11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR11` writer - Channel 11 Overrun"] +pub struct OVR11_W<'a> { + w: &'a mut W, +} +impl<'a> OVR11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `EVD0` reader - Channel 0 Event Detection"] +pub struct EVD0_R(crate::FieldReader); +impl EVD0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD0` writer - Channel 0 Event Detection"] +pub struct EVD0_W<'a> { + w: &'a mut W, +} +impl<'a> EVD0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `EVD1` reader - Channel 1 Event Detection"] +pub struct EVD1_R(crate::FieldReader); +impl EVD1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD1` writer - Channel 1 Event Detection"] +pub struct EVD1_W<'a> { + w: &'a mut W, +} +impl<'a> EVD1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `EVD2` reader - Channel 2 Event Detection"] +pub struct EVD2_R(crate::FieldReader); +impl EVD2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD2` writer - Channel 2 Event Detection"] +pub struct EVD2_W<'a> { + w: &'a mut W, +} +impl<'a> EVD2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `EVD3` reader - Channel 3 Event Detection"] +pub struct EVD3_R(crate::FieldReader); +impl EVD3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD3` writer - Channel 3 Event Detection"] +pub struct EVD3_W<'a> { + w: &'a mut W, +} +impl<'a> EVD3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `EVD4` reader - Channel 4 Event Detection"] +pub struct EVD4_R(crate::FieldReader); +impl EVD4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD4` writer - Channel 4 Event Detection"] +pub struct EVD4_W<'a> { + w: &'a mut W, +} +impl<'a> EVD4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `EVD5` reader - Channel 5 Event Detection"] +pub struct EVD5_R(crate::FieldReader); +impl EVD5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD5` writer - Channel 5 Event Detection"] +pub struct EVD5_W<'a> { + w: &'a mut W, +} +impl<'a> EVD5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `EVD6` reader - Channel 6 Event Detection"] +pub struct EVD6_R(crate::FieldReader); +impl EVD6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD6` writer - Channel 6 Event Detection"] +pub struct EVD6_W<'a> { + w: &'a mut W, +} +impl<'a> EVD6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `EVD7` reader - Channel 7 Event Detection"] +pub struct EVD7_R(crate::FieldReader); +impl EVD7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD7` writer - Channel 7 Event Detection"] +pub struct EVD7_W<'a> { + w: &'a mut W, +} +impl<'a> EVD7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `EVD8` reader - Channel 8 Event Detection"] +pub struct EVD8_R(crate::FieldReader); +impl EVD8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD8` writer - Channel 8 Event Detection"] +pub struct EVD8_W<'a> { + w: &'a mut W, +} +impl<'a> EVD8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `EVD9` reader - Channel 9 Event Detection"] +pub struct EVD9_R(crate::FieldReader); +impl EVD9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD9` writer - Channel 9 Event Detection"] +pub struct EVD9_W<'a> { + w: &'a mut W, +} +impl<'a> EVD9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `EVD10` reader - Channel 10 Event Detection"] +pub struct EVD10_R(crate::FieldReader); +impl EVD10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD10` writer - Channel 10 Event Detection"] +pub struct EVD10_W<'a> { + w: &'a mut W, +} +impl<'a> EVD10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `EVD11` reader - Channel 11 Event Detection"] +pub struct EVD11_R(crate::FieldReader); +impl EVD11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD11` writer - Channel 11 Event Detection"] +pub struct EVD11_W<'a> { + w: &'a mut W, +} +impl<'a> EVD11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +impl R { + #[doc = "Bit 0 - Channel 0 Overrun"] + #[inline(always)] + pub fn ovr0(&self) -> OVR0_R { + OVR0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel 1 Overrun"] + #[inline(always)] + pub fn ovr1(&self) -> OVR1_R { + OVR1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel 2 Overrun"] + #[inline(always)] + pub fn ovr2(&self) -> OVR2_R { + OVR2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Channel 3 Overrun"] + #[inline(always)] + pub fn ovr3(&self) -> OVR3_R { + OVR3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Channel 4 Overrun"] + #[inline(always)] + pub fn ovr4(&self) -> OVR4_R { + OVR4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Channel 5 Overrun"] + #[inline(always)] + pub fn ovr5(&self) -> OVR5_R { + OVR5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Channel 6 Overrun"] + #[inline(always)] + pub fn ovr6(&self) -> OVR6_R { + OVR6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Channel 7 Overrun"] + #[inline(always)] + pub fn ovr7(&self) -> OVR7_R { + OVR7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Channel 8 Overrun"] + #[inline(always)] + pub fn ovr8(&self) -> OVR8_R { + OVR8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Channel 9 Overrun"] + #[inline(always)] + pub fn ovr9(&self) -> OVR9_R { + OVR9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Channel 10 Overrun"] + #[inline(always)] + pub fn ovr10(&self) -> OVR10_R { + OVR10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Channel 11 Overrun"] + #[inline(always)] + pub fn ovr11(&self) -> OVR11_R { + OVR11_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 16 - Channel 0 Event Detection"] + #[inline(always)] + pub fn evd0(&self) -> EVD0_R { + EVD0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Channel 1 Event Detection"] + #[inline(always)] + pub fn evd1(&self) -> EVD1_R { + EVD1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Channel 2 Event Detection"] + #[inline(always)] + pub fn evd2(&self) -> EVD2_R { + EVD2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Channel 3 Event Detection"] + #[inline(always)] + pub fn evd3(&self) -> EVD3_R { + EVD3_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Channel 4 Event Detection"] + #[inline(always)] + pub fn evd4(&self) -> EVD4_R { + EVD4_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Channel 5 Event Detection"] + #[inline(always)] + pub fn evd5(&self) -> EVD5_R { + EVD5_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Channel 6 Event Detection"] + #[inline(always)] + pub fn evd6(&self) -> EVD6_R { + EVD6_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Channel 7 Event Detection"] + #[inline(always)] + pub fn evd7(&self) -> EVD7_R { + EVD7_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24 - Channel 8 Event Detection"] + #[inline(always)] + pub fn evd8(&self) -> EVD8_R { + EVD8_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Channel 9 Event Detection"] + #[inline(always)] + pub fn evd9(&self) -> EVD9_R { + EVD9_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Channel 10 Event Detection"] + #[inline(always)] + pub fn evd10(&self) -> EVD10_R { + EVD10_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Channel 11 Event Detection"] + #[inline(always)] + pub fn evd11(&self) -> EVD11_R { + EVD11_R::new(((self.bits >> 27) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel 0 Overrun"] + #[inline(always)] + pub fn ovr0(&mut self) -> OVR0_W { + OVR0_W { w: self } + } + #[doc = "Bit 1 - Channel 1 Overrun"] + #[inline(always)] + pub fn ovr1(&mut self) -> OVR1_W { + OVR1_W { w: self } + } + #[doc = "Bit 2 - Channel 2 Overrun"] + #[inline(always)] + pub fn ovr2(&mut self) -> OVR2_W { + OVR2_W { w: self } + } + #[doc = "Bit 3 - Channel 3 Overrun"] + #[inline(always)] + pub fn ovr3(&mut self) -> OVR3_W { + OVR3_W { w: self } + } + #[doc = "Bit 4 - Channel 4 Overrun"] + #[inline(always)] + pub fn ovr4(&mut self) -> OVR4_W { + OVR4_W { w: self } + } + #[doc = "Bit 5 - Channel 5 Overrun"] + #[inline(always)] + pub fn ovr5(&mut self) -> OVR5_W { + OVR5_W { w: self } + } + #[doc = "Bit 6 - Channel 6 Overrun"] + #[inline(always)] + pub fn ovr6(&mut self) -> OVR6_W { + OVR6_W { w: self } + } + #[doc = "Bit 7 - Channel 7 Overrun"] + #[inline(always)] + pub fn ovr7(&mut self) -> OVR7_W { + OVR7_W { w: self } + } + #[doc = "Bit 8 - Channel 8 Overrun"] + #[inline(always)] + pub fn ovr8(&mut self) -> OVR8_W { + OVR8_W { w: self } + } + #[doc = "Bit 9 - Channel 9 Overrun"] + #[inline(always)] + pub fn ovr9(&mut self) -> OVR9_W { + OVR9_W { w: self } + } + #[doc = "Bit 10 - Channel 10 Overrun"] + #[inline(always)] + pub fn ovr10(&mut self) -> OVR10_W { + OVR10_W { w: self } + } + #[doc = "Bit 11 - Channel 11 Overrun"] + #[inline(always)] + pub fn ovr11(&mut self) -> OVR11_W { + OVR11_W { w: self } + } + #[doc = "Bit 16 - Channel 0 Event Detection"] + #[inline(always)] + pub fn evd0(&mut self) -> EVD0_W { + EVD0_W { w: self } + } + #[doc = "Bit 17 - Channel 1 Event Detection"] + #[inline(always)] + pub fn evd1(&mut self) -> EVD1_W { + EVD1_W { w: self } + } + #[doc = "Bit 18 - Channel 2 Event Detection"] + #[inline(always)] + pub fn evd2(&mut self) -> EVD2_W { + EVD2_W { w: self } + } + #[doc = "Bit 19 - Channel 3 Event Detection"] + #[inline(always)] + pub fn evd3(&mut self) -> EVD3_W { + EVD3_W { w: self } + } + #[doc = "Bit 20 - Channel 4 Event Detection"] + #[inline(always)] + pub fn evd4(&mut self) -> EVD4_W { + EVD4_W { w: self } + } + #[doc = "Bit 21 - Channel 5 Event Detection"] + #[inline(always)] + pub fn evd5(&mut self) -> EVD5_W { + EVD5_W { w: self } + } + #[doc = "Bit 22 - Channel 6 Event Detection"] + #[inline(always)] + pub fn evd6(&mut self) -> EVD6_W { + EVD6_W { w: self } + } + #[doc = "Bit 23 - Channel 7 Event Detection"] + #[inline(always)] + pub fn evd7(&mut self) -> EVD7_W { + EVD7_W { w: self } + } + #[doc = "Bit 24 - Channel 8 Event Detection"] + #[inline(always)] + pub fn evd8(&mut self) -> EVD8_W { + EVD8_W { w: self } + } + #[doc = "Bit 25 - Channel 9 Event Detection"] + #[inline(always)] + pub fn evd9(&mut self) -> EVD9_W { + EVD9_W { w: self } + } + #[doc = "Bit 26 - Channel 10 Event Detection"] + #[inline(always)] + pub fn evd10(&mut self) -> EVD10_W { + EVD10_W { w: self } + } + #[doc = "Bit 27 - Channel 11 Event Detection"] + #[inline(always)] + pub fn evd11(&mut self) -> EVD11_W { + EVD11_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/evsys/swevt.rs b/pac/atsamc20n/src/evsys/swevt.rs new file mode 100644 index 000000000000..df58fe290de2 --- /dev/null +++ b/pac/atsamc20n/src/evsys/swevt.rs @@ -0,0 +1,369 @@ +#[doc = "Register `SWEVT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHANNEL0` writer - Channel 0 Software Selection"] +pub struct CHANNEL0_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `CHANNEL1` writer - Channel 1 Software Selection"] +pub struct CHANNEL1_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CHANNEL2` writer - Channel 2 Software Selection"] +pub struct CHANNEL2_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CHANNEL3` writer - Channel 3 Software Selection"] +pub struct CHANNEL3_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CHANNEL4` writer - Channel 4 Software Selection"] +pub struct CHANNEL4_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `CHANNEL5` writer - Channel 5 Software Selection"] +pub struct CHANNEL5_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `CHANNEL6` writer - Channel 6 Software Selection"] +pub struct CHANNEL6_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `CHANNEL7` writer - Channel 7 Software Selection"] +pub struct CHANNEL7_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CHANNEL8` writer - Channel 8 Software Selection"] +pub struct CHANNEL8_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `CHANNEL9` writer - Channel 9 Software Selection"] +pub struct CHANNEL9_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `CHANNEL10` writer - Channel 10 Software Selection"] +pub struct CHANNEL10_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `CHANNEL11` writer - Channel 11 Software Selection"] +pub struct CHANNEL11_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +impl W { + #[doc = "Bit 0 - Channel 0 Software Selection"] + #[inline(always)] + pub fn channel0(&mut self) -> CHANNEL0_W { + CHANNEL0_W { w: self } + } + #[doc = "Bit 1 - Channel 1 Software Selection"] + #[inline(always)] + pub fn channel1(&mut self) -> CHANNEL1_W { + CHANNEL1_W { w: self } + } + #[doc = "Bit 2 - Channel 2 Software Selection"] + #[inline(always)] + pub fn channel2(&mut self) -> CHANNEL2_W { + CHANNEL2_W { w: self } + } + #[doc = "Bit 3 - Channel 3 Software Selection"] + #[inline(always)] + pub fn channel3(&mut self) -> CHANNEL3_W { + CHANNEL3_W { w: self } + } + #[doc = "Bit 4 - Channel 4 Software Selection"] + #[inline(always)] + pub fn channel4(&mut self) -> CHANNEL4_W { + CHANNEL4_W { w: self } + } + #[doc = "Bit 5 - Channel 5 Software Selection"] + #[inline(always)] + pub fn channel5(&mut self) -> CHANNEL5_W { + CHANNEL5_W { w: self } + } + #[doc = "Bit 6 - Channel 6 Software Selection"] + #[inline(always)] + pub fn channel6(&mut self) -> CHANNEL6_W { + CHANNEL6_W { w: self } + } + #[doc = "Bit 7 - Channel 7 Software Selection"] + #[inline(always)] + pub fn channel7(&mut self) -> CHANNEL7_W { + CHANNEL7_W { w: self } + } + #[doc = "Bit 8 - Channel 8 Software Selection"] + #[inline(always)] + pub fn channel8(&mut self) -> CHANNEL8_W { + CHANNEL8_W { w: self } + } + #[doc = "Bit 9 - Channel 9 Software Selection"] + #[inline(always)] + pub fn channel9(&mut self) -> CHANNEL9_W { + CHANNEL9_W { w: self } + } + #[doc = "Bit 10 - Channel 10 Software Selection"] + #[inline(always)] + pub fn channel10(&mut self) -> CHANNEL10_W { + CHANNEL10_W { w: self } + } + #[doc = "Bit 11 - Channel 11 Software Selection"] + #[inline(always)] + pub fn channel11(&mut self) -> CHANNEL11_W { + CHANNEL11_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Software Event\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [swevt](index.html) module"] +pub struct SWEVT_SPEC; +impl crate::RegisterSpec for SWEVT_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [swevt::W](W) writer structure"] +impl crate::Writable for SWEVT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SWEVT to value 0"] +impl crate::Resettable for SWEVT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/evsys/user.rs b/pac/atsamc20n/src/evsys/user.rs new file mode 100644 index 000000000000..848f9f599b79 --- /dev/null +++ b/pac/atsamc20n/src/evsys/user.rs @@ -0,0 +1,104 @@ +#[doc = "Register `USER[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `USER[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHANNEL` reader - Channel Event Selection"] +pub struct CHANNEL_R(crate::FieldReader); +impl CHANNEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CHANNEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHANNEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHANNEL` writer - Channel Event Selection"] +pub struct CHANNEL_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Channel Event Selection"] + #[inline(always)] + pub fn channel(&self) -> CHANNEL_R { + CHANNEL_R::new((self.bits & 0x1f) as u8) + } +} +impl W { + #[doc = "Bits 0:4 - Channel Event Selection"] + #[inline(always)] + pub fn channel(&mut self) -> CHANNEL_W { + CHANNEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "User Multiplexer n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [user](index.html) module"] +pub struct USER_SPEC; +impl crate::RegisterSpec for USER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [user::R](R) reader structure"] +impl crate::Readable for USER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [user::W](W) writer structure"] +impl crate::Writable for USER_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets USER[%s] +to value 0"] +impl crate::Resettable for USER_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/freqm.rs b/pac/atsamc20n/src/freqm.rs new file mode 100644 index 000000000000..f0fc6fda975e --- /dev/null +++ b/pac/atsamc20n/src/freqm.rs @@ -0,0 +1,59 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control A Register"] + pub ctrla: crate::Reg, + #[doc = "0x01 - Control B Register"] + pub ctrlb: crate::Reg, + #[doc = "0x02 - Config A register"] + pub cfga: crate::Reg, + _reserved3: [u8; 0x04], + #[doc = "0x08 - Interrupt Enable Clear Register"] + pub intenclr: crate::Reg, + #[doc = "0x09 - Interrupt Enable Set Register"] + pub intenset: crate::Reg, + #[doc = "0x0a - Interrupt Flag Register"] + pub intflag: crate::Reg, + #[doc = "0x0b - Status Register"] + pub status: crate::Reg, + #[doc = "0x0c - Synchronization Busy Register"] + pub syncbusy: crate::Reg, + #[doc = "0x10 - Count Value Register"] + pub value: crate::Reg, +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A Register"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "Control B Register"] +pub mod ctrlb; +#[doc = "CFGA register accessor: an alias for `Reg`"] +pub type CFGA = crate::Reg; +#[doc = "Config A register"] +pub mod cfga; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear Register"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set Register"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Register"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status Register"] +pub mod status; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Busy Register"] +pub mod syncbusy; +#[doc = "VALUE register accessor: an alias for `Reg`"] +pub type VALUE = crate::Reg; +#[doc = "Count Value Register"] +pub mod value; diff --git a/pac/atsamc20n/src/freqm/cfga.rs b/pac/atsamc20n/src/freqm/cfga.rs new file mode 100644 index 000000000000..a63cf01f0b96 --- /dev/null +++ b/pac/atsamc20n/src/freqm/cfga.rs @@ -0,0 +1,150 @@ +#[doc = "Register `CFGA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CFGA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `REFNUM` reader - Number of Reference Clock Cycles"] +pub struct REFNUM_R(crate::FieldReader); +impl REFNUM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REFNUM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REFNUM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REFNUM` writer - Number of Reference Clock Cycles"] +pub struct REFNUM_W<'a> { + w: &'a mut W, +} +impl<'a> REFNUM_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u16 & 0xff); + self.w + } +} +#[doc = "Field `DIVREF` reader - Divide Reference Clock"] +pub struct DIVREF_R(crate::FieldReader); +impl DIVREF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIVREF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIVREF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIVREF` writer - Divide Reference Clock"] +pub struct DIVREF_W<'a> { + w: &'a mut W, +} +impl<'a> DIVREF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Number of Reference Clock Cycles"] + #[inline(always)] + pub fn refnum(&self) -> REFNUM_R { + REFNUM_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 15 - Divide Reference Clock"] + #[inline(always)] + pub fn divref(&self) -> DIVREF_R { + DIVREF_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - Number of Reference Clock Cycles"] + #[inline(always)] + pub fn refnum(&mut self) -> REFNUM_W { + REFNUM_W { w: self } + } + #[doc = "Bit 15 - Divide Reference Clock"] + #[inline(always)] + pub fn divref(&mut self) -> DIVREF_W { + DIVREF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Config A register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cfga](index.html) module"] +pub struct CFGA_SPEC; +impl crate::RegisterSpec for CFGA_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [cfga::R](R) reader structure"] +impl crate::Readable for CFGA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cfga::W](W) writer structure"] +impl crate::Writable for CFGA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CFGA to value 0"] +impl crate::Resettable for CFGA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/freqm/ctrla.rs b/pac/atsamc20n/src/freqm/ctrla.rs new file mode 100644 index 000000000000..b2cefdd45770 --- /dev/null +++ b/pac/atsamc20n/src/freqm/ctrla.rs @@ -0,0 +1,160 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/freqm/ctrlb.rs b/pac/atsamc20n/src/freqm/ctrlb.rs new file mode 100644 index 000000000000..7d350e71fbf3 --- /dev/null +++ b/pac/atsamc20n/src/freqm/ctrlb.rs @@ -0,0 +1,72 @@ +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `START` writer - Start Measurement"] +pub struct START_W<'a> { + w: &'a mut W, +} +impl<'a> START_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0 - Start Measurement"] + #[inline(always)] + pub fn start(&mut self) -> START_W { + START_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u8; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/freqm/intenclr.rs b/pac/atsamc20n/src/freqm/intenclr.rs new file mode 100644 index 000000000000..a224aa5500f6 --- /dev/null +++ b/pac/atsamc20n/src/freqm/intenclr.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DONE` reader - Measurement Done Interrupt Enable"] +pub struct DONE_R(crate::FieldReader); +impl DONE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DONE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DONE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DONE` writer - Measurement Done Interrupt Enable"] +pub struct DONE_W<'a> { + w: &'a mut W, +} +impl<'a> DONE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Measurement Done Interrupt Enable"] + #[inline(always)] + pub fn done(&self) -> DONE_R { + DONE_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Measurement Done Interrupt Enable"] + #[inline(always)] + pub fn done(&mut self) -> DONE_W { + DONE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/freqm/intenset.rs b/pac/atsamc20n/src/freqm/intenset.rs new file mode 100644 index 000000000000..53b3d0bef7c0 --- /dev/null +++ b/pac/atsamc20n/src/freqm/intenset.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DONE` reader - Measurement Done Interrupt Enable"] +pub struct DONE_R(crate::FieldReader); +impl DONE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DONE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DONE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DONE` writer - Measurement Done Interrupt Enable"] +pub struct DONE_W<'a> { + w: &'a mut W, +} +impl<'a> DONE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Measurement Done Interrupt Enable"] + #[inline(always)] + pub fn done(&self) -> DONE_R { + DONE_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Measurement Done Interrupt Enable"] + #[inline(always)] + pub fn done(&mut self) -> DONE_W { + DONE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/freqm/intflag.rs b/pac/atsamc20n/src/freqm/intflag.rs new file mode 100644 index 000000000000..3b8fdab47703 --- /dev/null +++ b/pac/atsamc20n/src/freqm/intflag.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DONE` reader - Measurement Done"] +pub struct DONE_R(crate::FieldReader); +impl DONE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DONE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DONE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DONE` writer - Measurement Done"] +pub struct DONE_W<'a> { + w: &'a mut W, +} +impl<'a> DONE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Measurement Done"] + #[inline(always)] + pub fn done(&self) -> DONE_R { + DONE_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Measurement Done"] + #[inline(always)] + pub fn done(&mut self) -> DONE_W { + DONE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/freqm/status.rs b/pac/atsamc20n/src/freqm/status.rs new file mode 100644 index 000000000000..8a81662f51b0 --- /dev/null +++ b/pac/atsamc20n/src/freqm/status.rs @@ -0,0 +1,160 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BUSY` reader - FREQM Status"] +pub struct BUSY_R(crate::FieldReader); +impl BUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSY` writer - FREQM Status"] +pub struct BUSY_W<'a> { + w: &'a mut W, +} +impl<'a> BUSY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `OVF` reader - Sticky Count Value Overflow"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Sticky Count Value Overflow"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - FREQM Status"] + #[inline(always)] + pub fn busy(&self) -> BUSY_R { + BUSY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Sticky Count Value Overflow"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - FREQM Status"] + #[inline(always)] + pub fn busy(&mut self) -> BUSY_W { + BUSY_W { w: self } + } + #[doc = "Bit 1 - Sticky Count Value Overflow"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/freqm/syncbusy.rs b/pac/atsamc20n/src/freqm/syncbusy.rs new file mode 100644 index 000000000000..54396368e817 --- /dev/null +++ b/pac/atsamc20n/src/freqm/syncbusy.rs @@ -0,0 +1,73 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +#[doc = "Synchronization Busy Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/freqm/value.rs b/pac/atsamc20n/src/freqm/value.rs new file mode 100644 index 000000000000..5b0f5dfd9b67 --- /dev/null +++ b/pac/atsamc20n/src/freqm/value.rs @@ -0,0 +1,53 @@ +#[doc = "Register `VALUE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `VALUE` reader - Measurement Value"] +pub struct VALUE_R(crate::FieldReader); +impl VALUE_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + VALUE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VALUE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:23 - Measurement Value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +#[doc = "Count Value Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [value](index.html) module"] +pub struct VALUE_SPEC; +impl crate::RegisterSpec for VALUE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [value::R](R) reader structure"] +impl crate::Readable for VALUE_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets VALUE to value 0"] +impl crate::Resettable for VALUE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/gclk.rs b/pac/atsamc20n/src/gclk.rs new file mode 100644 index 000000000000..b91b638be958 --- /dev/null +++ b/pac/atsamc20n/src/gclk.rs @@ -0,0 +1,31 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrla: crate::Reg, + _reserved1: [u8; 0x03], + #[doc = "0x04 - Synchronization Busy"] + pub syncbusy: crate::Reg, + _reserved2: [u8; 0x18], + #[doc = "0x20..0x44 - Generic Clock Generator Control"] + pub genctrl: [crate::Reg; 9], + _reserved3: [u8; 0x3c], + #[doc = "0x80..0x138 - Peripheral Clock Control"] + pub pchctrl: [crate::Reg; 46], +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control"] +pub mod ctrla; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Busy"] +pub mod syncbusy; +#[doc = "GENCTRL register accessor: an alias for `Reg`"] +pub type GENCTRL = crate::Reg; +#[doc = "Generic Clock Generator Control"] +pub mod genctrl; +#[doc = "PCHCTRL register accessor: an alias for `Reg`"] +pub type PCHCTRL = crate::Reg; +#[doc = "Peripheral Clock Control"] +pub mod pchctrl; diff --git a/pac/atsamc20n/src/gclk/ctrla.rs b/pac/atsamc20n/src/gclk/ctrla.rs new file mode 100644 index 000000000000..1c24704395ad --- /dev/null +++ b/pac/atsamc20n/src/gclk/ctrla.rs @@ -0,0 +1,113 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/gclk/genctrl.rs b/pac/atsamc20n/src/gclk/genctrl.rs new file mode 100644 index 000000000000..052b2915ca7f --- /dev/null +++ b/pac/atsamc20n/src/gclk/genctrl.rs @@ -0,0 +1,597 @@ +#[doc = "Register `GENCTRL[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GENCTRL[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Source Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SRC_A { + #[doc = "0: XOSC oscillator output"] + XOSC = 0, + #[doc = "1: Generator input pad"] + GCLKIN = 1, + #[doc = "2: Generic clock generator 1 output"] + GCLKGEN1 = 2, + #[doc = "3: OSCULP32K oscillator output"] + OSCULP32K = 3, + #[doc = "4: OSC32K oscillator output"] + OSC32K = 4, + #[doc = "5: XOSC32K oscillator output"] + XOSC32K = 5, + #[doc = "6: OSC48M oscillator output"] + OSC48M = 6, + #[doc = "7: DPLL96M output"] + DPLL96M = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SRC_A) -> Self { + variant as _ + } +} +#[doc = "Field `SRC` reader - Source Select"] +pub struct SRC_R(crate::FieldReader); +impl SRC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SRC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SRC_A { + match self.bits { + 0 => SRC_A::XOSC, + 1 => SRC_A::GCLKIN, + 2 => SRC_A::GCLKGEN1, + 3 => SRC_A::OSCULP32K, + 4 => SRC_A::OSC32K, + 5 => SRC_A::XOSC32K, + 6 => SRC_A::OSC48M, + 7 => SRC_A::DPLL96M, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `XOSC`"] + #[inline(always)] + pub fn is_xosc(&self) -> bool { + **self == SRC_A::XOSC + } + #[doc = "Checks if the value of the field is `GCLKIN`"] + #[inline(always)] + pub fn is_gclkin(&self) -> bool { + **self == SRC_A::GCLKIN + } + #[doc = "Checks if the value of the field is `GCLKGEN1`"] + #[inline(always)] + pub fn is_gclkgen1(&self) -> bool { + **self == SRC_A::GCLKGEN1 + } + #[doc = "Checks if the value of the field is `OSCULP32K`"] + #[inline(always)] + pub fn is_osculp32k(&self) -> bool { + **self == SRC_A::OSCULP32K + } + #[doc = "Checks if the value of the field is `OSC32K`"] + #[inline(always)] + pub fn is_osc32k(&self) -> bool { + **self == SRC_A::OSC32K + } + #[doc = "Checks if the value of the field is `XOSC32K`"] + #[inline(always)] + pub fn is_xosc32k(&self) -> bool { + **self == SRC_A::XOSC32K + } + #[doc = "Checks if the value of the field is `OSC48M`"] + #[inline(always)] + pub fn is_osc48m(&self) -> bool { + **self == SRC_A::OSC48M + } + #[doc = "Checks if the value of the field is `DPLL96M`"] + #[inline(always)] + pub fn is_dpll96m(&self) -> bool { + **self == SRC_A::DPLL96M + } +} +impl core::ops::Deref for SRC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SRC` writer - Source Select"] +pub struct SRC_W<'a> { + w: &'a mut W, +} +impl<'a> SRC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SRC_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "XOSC oscillator output"] + #[inline(always)] + pub fn xosc(self) -> &'a mut W { + self.variant(SRC_A::XOSC) + } + #[doc = "Generator input pad"] + #[inline(always)] + pub fn gclkin(self) -> &'a mut W { + self.variant(SRC_A::GCLKIN) + } + #[doc = "Generic clock generator 1 output"] + #[inline(always)] + pub fn gclkgen1(self) -> &'a mut W { + self.variant(SRC_A::GCLKGEN1) + } + #[doc = "OSCULP32K oscillator output"] + #[inline(always)] + pub fn osculp32k(self) -> &'a mut W { + self.variant(SRC_A::OSCULP32K) + } + #[doc = "OSC32K oscillator output"] + #[inline(always)] + pub fn osc32k(self) -> &'a mut W { + self.variant(SRC_A::OSC32K) + } + #[doc = "XOSC32K oscillator output"] + #[inline(always)] + pub fn xosc32k(self) -> &'a mut W { + self.variant(SRC_A::XOSC32K) + } + #[doc = "OSC48M oscillator output"] + #[inline(always)] + pub fn osc48m(self) -> &'a mut W { + self.variant(SRC_A::OSC48M) + } + #[doc = "DPLL96M output"] + #[inline(always)] + pub fn dpll96m(self) -> &'a mut W { + self.variant(SRC_A::DPLL96M) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Field `GENEN` reader - Generic Clock Generator Enable"] +pub struct GENEN_R(crate::FieldReader); +impl GENEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENEN` writer - Generic Clock Generator Enable"] +pub struct GENEN_W<'a> { + w: &'a mut W, +} +impl<'a> GENEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `IDC` reader - Improve Duty Cycle"] +pub struct IDC_R(crate::FieldReader); +impl IDC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IDC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IDC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IDC` writer - Improve Duty Cycle"] +pub struct IDC_W<'a> { + w: &'a mut W, +} +impl<'a> IDC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `OOV` reader - Output Off Value"] +pub struct OOV_R(crate::FieldReader); +impl OOV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OOV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OOV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OOV` writer - Output Off Value"] +pub struct OOV_W<'a> { + w: &'a mut W, +} +impl<'a> OOV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `OE` reader - Output Enable"] +pub struct OE_R(crate::FieldReader); +impl OE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OE` writer - Output Enable"] +pub struct OE_W<'a> { + w: &'a mut W, +} +impl<'a> OE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Divide Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum DIVSEL_A { + #[doc = "0: Divide input directly by divider factor"] + DIV1 = 0, + #[doc = "1: Divide input by 2^(divider factor+ 1)"] + DIV2 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DIVSEL_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DIVSEL` reader - Divide Selection"] +pub struct DIVSEL_R(crate::FieldReader); +impl DIVSEL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIVSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DIVSEL_A { + match self.bits { + false => DIVSEL_A::DIV1, + true => DIVSEL_A::DIV2, + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == DIVSEL_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == DIVSEL_A::DIV2 + } +} +impl core::ops::Deref for DIVSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIVSEL` writer - Divide Selection"] +pub struct DIVSEL_W<'a> { + w: &'a mut W, +} +impl<'a> DIVSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DIVSEL_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Divide input directly by divider factor"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(DIVSEL_A::DIV1) + } + #[doc = "Divide input by 2^(divider factor+ 1)"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(DIVSEL_A::DIV2) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `DIV` reader - Division Factor"] +pub struct DIV_R(crate::FieldReader); +impl DIV_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + DIV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIV` writer - Division Factor"] +pub struct DIV_W<'a> { + w: &'a mut W, +} +impl<'a> DIV_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xffff << 16)) | ((value as u32 & 0xffff) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Source Select"] + #[inline(always)] + pub fn src(&self) -> SRC_R { + SRC_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 8 - Generic Clock Generator Enable"] + #[inline(always)] + pub fn genen(&self) -> GENEN_R { + GENEN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Improve Duty Cycle"] + #[inline(always)] + pub fn idc(&self) -> IDC_R { + IDC_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Output Off Value"] + #[inline(always)] + pub fn oov(&self) -> OOV_R { + OOV_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Output Enable"] + #[inline(always)] + pub fn oe(&self) -> OE_R { + OE_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Divide Selection"] + #[inline(always)] + pub fn divsel(&self) -> DIVSEL_R { + DIVSEL_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bits 16:31 - Division Factor"] + #[inline(always)] + pub fn div(&self) -> DIV_R { + DIV_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:2 - Source Select"] + #[inline(always)] + pub fn src(&mut self) -> SRC_W { + SRC_W { w: self } + } + #[doc = "Bit 8 - Generic Clock Generator Enable"] + #[inline(always)] + pub fn genen(&mut self) -> GENEN_W { + GENEN_W { w: self } + } + #[doc = "Bit 9 - Improve Duty Cycle"] + #[inline(always)] + pub fn idc(&mut self) -> IDC_W { + IDC_W { w: self } + } + #[doc = "Bit 10 - Output Off Value"] + #[inline(always)] + pub fn oov(&mut self) -> OOV_W { + OOV_W { w: self } + } + #[doc = "Bit 11 - Output Enable"] + #[inline(always)] + pub fn oe(&mut self) -> OE_W { + OE_W { w: self } + } + #[doc = "Bit 12 - Divide Selection"] + #[inline(always)] + pub fn divsel(&mut self) -> DIVSEL_W { + DIVSEL_W { w: self } + } + #[doc = "Bit 13 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bits 16:31 - Division Factor"] + #[inline(always)] + pub fn div(&mut self) -> DIV_W { + DIV_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Generic Clock Generator Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [genctrl](index.html) module"] +pub struct GENCTRL_SPEC; +impl crate::RegisterSpec for GENCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [genctrl::R](R) reader structure"] +impl crate::Readable for GENCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [genctrl::W](W) writer structure"] +impl crate::Writable for GENCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets GENCTRL[%s] +to value 0"] +impl crate::Resettable for GENCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/gclk/pchctrl.rs b/pac/atsamc20n/src/gclk/pchctrl.rs new file mode 100644 index 000000000000..8001ffeaa1ee --- /dev/null +++ b/pac/atsamc20n/src/gclk/pchctrl.rs @@ -0,0 +1,338 @@ +#[doc = "Register `PCHCTRL[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PCHCTRL[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Generic Clock Generator\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum GEN_A { + #[doc = "0: Generic clock generator 0"] + GCLK0 = 0, + #[doc = "1: Generic clock generator 1"] + GCLK1 = 1, + #[doc = "2: Generic clock generator 2"] + GCLK2 = 2, + #[doc = "3: Generic clock generator 3"] + GCLK3 = 3, + #[doc = "4: Generic clock generator 4"] + GCLK4 = 4, + #[doc = "5: Generic clock generator 5"] + GCLK5 = 5, + #[doc = "6: Generic clock generator 6"] + GCLK6 = 6, + #[doc = "7: Generic clock generator 7"] + GCLK7 = 7, + #[doc = "8: Generic clock generator 8"] + GCLK8 = 8, +} +impl From for u8 { + #[inline(always)] + fn from(variant: GEN_A) -> Self { + variant as _ + } +} +#[doc = "Field `GEN` reader - Generic Clock Generator"] +pub struct GEN_R(crate::FieldReader); +impl GEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + GEN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(GEN_A::GCLK0), + 1 => Some(GEN_A::GCLK1), + 2 => Some(GEN_A::GCLK2), + 3 => Some(GEN_A::GCLK3), + 4 => Some(GEN_A::GCLK4), + 5 => Some(GEN_A::GCLK5), + 6 => Some(GEN_A::GCLK6), + 7 => Some(GEN_A::GCLK7), + 8 => Some(GEN_A::GCLK8), + _ => None, + } + } + #[doc = "Checks if the value of the field is `GCLK0`"] + #[inline(always)] + pub fn is_gclk0(&self) -> bool { + **self == GEN_A::GCLK0 + } + #[doc = "Checks if the value of the field is `GCLK1`"] + #[inline(always)] + pub fn is_gclk1(&self) -> bool { + **self == GEN_A::GCLK1 + } + #[doc = "Checks if the value of the field is `GCLK2`"] + #[inline(always)] + pub fn is_gclk2(&self) -> bool { + **self == GEN_A::GCLK2 + } + #[doc = "Checks if the value of the field is `GCLK3`"] + #[inline(always)] + pub fn is_gclk3(&self) -> bool { + **self == GEN_A::GCLK3 + } + #[doc = "Checks if the value of the field is `GCLK4`"] + #[inline(always)] + pub fn is_gclk4(&self) -> bool { + **self == GEN_A::GCLK4 + } + #[doc = "Checks if the value of the field is `GCLK5`"] + #[inline(always)] + pub fn is_gclk5(&self) -> bool { + **self == GEN_A::GCLK5 + } + #[doc = "Checks if the value of the field is `GCLK6`"] + #[inline(always)] + pub fn is_gclk6(&self) -> bool { + **self == GEN_A::GCLK6 + } + #[doc = "Checks if the value of the field is `GCLK7`"] + #[inline(always)] + pub fn is_gclk7(&self) -> bool { + **self == GEN_A::GCLK7 + } + #[doc = "Checks if the value of the field is `GCLK8`"] + #[inline(always)] + pub fn is_gclk8(&self) -> bool { + **self == GEN_A::GCLK8 + } +} +impl core::ops::Deref for GEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GEN` writer - Generic Clock Generator"] +pub struct GEN_W<'a> { + w: &'a mut W, +} +impl<'a> GEN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: GEN_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Generic clock generator 0"] + #[inline(always)] + pub fn gclk0(self) -> &'a mut W { + self.variant(GEN_A::GCLK0) + } + #[doc = "Generic clock generator 1"] + #[inline(always)] + pub fn gclk1(self) -> &'a mut W { + self.variant(GEN_A::GCLK1) + } + #[doc = "Generic clock generator 2"] + #[inline(always)] + pub fn gclk2(self) -> &'a mut W { + self.variant(GEN_A::GCLK2) + } + #[doc = "Generic clock generator 3"] + #[inline(always)] + pub fn gclk3(self) -> &'a mut W { + self.variant(GEN_A::GCLK3) + } + #[doc = "Generic clock generator 4"] + #[inline(always)] + pub fn gclk4(self) -> &'a mut W { + self.variant(GEN_A::GCLK4) + } + #[doc = "Generic clock generator 5"] + #[inline(always)] + pub fn gclk5(self) -> &'a mut W { + self.variant(GEN_A::GCLK5) + } + #[doc = "Generic clock generator 6"] + #[inline(always)] + pub fn gclk6(self) -> &'a mut W { + self.variant(GEN_A::GCLK6) + } + #[doc = "Generic clock generator 7"] + #[inline(always)] + pub fn gclk7(self) -> &'a mut W { + self.variant(GEN_A::GCLK7) + } + #[doc = "Generic clock generator 8"] + #[inline(always)] + pub fn gclk8(self) -> &'a mut W { + self.variant(GEN_A::GCLK8) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Field `CHEN` reader - Channel Enable"] +pub struct CHEN_R(crate::FieldReader); +impl CHEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHEN` writer - Channel Enable"] +pub struct CHEN_W<'a> { + w: &'a mut W, +} +impl<'a> CHEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `WRTLOCK` reader - Write Lock"] +pub struct WRTLOCK_R(crate::FieldReader); +impl WRTLOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WRTLOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WRTLOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WRTLOCK` writer - Write Lock"] +pub struct WRTLOCK_W<'a> { + w: &'a mut W, +} +impl<'a> WRTLOCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Generic Clock Generator"] + #[inline(always)] + pub fn gen(&self) -> GEN_R { + GEN_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 6 - Channel Enable"] + #[inline(always)] + pub fn chen(&self) -> CHEN_R { + CHEN_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&self) -> WRTLOCK_R { + WRTLOCK_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Generic Clock Generator"] + #[inline(always)] + pub fn gen(&mut self) -> GEN_W { + GEN_W { w: self } + } + #[doc = "Bit 6 - Channel Enable"] + #[inline(always)] + pub fn chen(&mut self) -> CHEN_W { + CHEN_W { w: self } + } + #[doc = "Bit 7 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&mut self) -> WRTLOCK_W { + WRTLOCK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Peripheral Clock Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pchctrl](index.html) module"] +pub struct PCHCTRL_SPEC; +impl crate::RegisterSpec for PCHCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pchctrl::R](R) reader structure"] +impl crate::Readable for PCHCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [pchctrl::W](W) writer structure"] +impl crate::Writable for PCHCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PCHCTRL[%s] +to value 0"] +impl crate::Resettable for PCHCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/gclk/syncbusy.rs b/pac/atsamc20n/src/gclk/syncbusy.rs new file mode 100644 index 000000000000..f21640440354 --- /dev/null +++ b/pac/atsamc20n/src/gclk/syncbusy.rs @@ -0,0 +1,233 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchroniation Busy bit"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENCTRL0` reader - Generic Clock Generator Control 0 Synchronization Busy bits"] +pub struct GENCTRL0_R(crate::FieldReader); +impl GENCTRL0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENCTRL0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENCTRL0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENCTRL1` reader - Generic Clock Generator Control 1 Synchronization Busy bits"] +pub struct GENCTRL1_R(crate::FieldReader); +impl GENCTRL1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENCTRL1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENCTRL1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENCTRL2` reader - Generic Clock Generator Control 2 Synchronization Busy bits"] +pub struct GENCTRL2_R(crate::FieldReader); +impl GENCTRL2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENCTRL2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENCTRL2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENCTRL3` reader - Generic Clock Generator Control 3 Synchronization Busy bits"] +pub struct GENCTRL3_R(crate::FieldReader); +impl GENCTRL3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENCTRL3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENCTRL3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENCTRL4` reader - Generic Clock Generator Control 4 Synchronization Busy bits"] +pub struct GENCTRL4_R(crate::FieldReader); +impl GENCTRL4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENCTRL4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENCTRL4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENCTRL5` reader - Generic Clock Generator Control 5 Synchronization Busy bits"] +pub struct GENCTRL5_R(crate::FieldReader); +impl GENCTRL5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENCTRL5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENCTRL5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENCTRL6` reader - Generic Clock Generator Control 6 Synchronization Busy bits"] +pub struct GENCTRL6_R(crate::FieldReader); +impl GENCTRL6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENCTRL6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENCTRL6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENCTRL7` reader - Generic Clock Generator Control 7 Synchronization Busy bits"] +pub struct GENCTRL7_R(crate::FieldReader); +impl GENCTRL7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENCTRL7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENCTRL7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENCTRL8` reader - Generic Clock Generator Control 8 Synchronization Busy bits"] +pub struct GENCTRL8_R(crate::FieldReader); +impl GENCTRL8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENCTRL8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENCTRL8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchroniation Busy bit"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 2 - Generic Clock Generator Control 0 Synchronization Busy bits"] + #[inline(always)] + pub fn genctrl0(&self) -> GENCTRL0_R { + GENCTRL0_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Generic Clock Generator Control 1 Synchronization Busy bits"] + #[inline(always)] + pub fn genctrl1(&self) -> GENCTRL1_R { + GENCTRL1_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Generic Clock Generator Control 2 Synchronization Busy bits"] + #[inline(always)] + pub fn genctrl2(&self) -> GENCTRL2_R { + GENCTRL2_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Generic Clock Generator Control 3 Synchronization Busy bits"] + #[inline(always)] + pub fn genctrl3(&self) -> GENCTRL3_R { + GENCTRL3_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Generic Clock Generator Control 4 Synchronization Busy bits"] + #[inline(always)] + pub fn genctrl4(&self) -> GENCTRL4_R { + GENCTRL4_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Generic Clock Generator Control 5 Synchronization Busy bits"] + #[inline(always)] + pub fn genctrl5(&self) -> GENCTRL5_R { + GENCTRL5_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Generic Clock Generator Control 6 Synchronization Busy bits"] + #[inline(always)] + pub fn genctrl6(&self) -> GENCTRL6_R { + GENCTRL6_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Generic Clock Generator Control 7 Synchronization Busy bits"] + #[inline(always)] + pub fn genctrl7(&self) -> GENCTRL7_R { + GENCTRL7_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Generic Clock Generator Control 8 Synchronization Busy bits"] + #[inline(always)] + pub fn genctrl8(&self) -> GENCTRL8_R { + GENCTRL8_R::new(((self.bits >> 10) & 0x01) != 0) + } +} +#[doc = "Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/generic.rs b/pac/atsamc20n/src/generic.rs new file mode 100644 index 000000000000..76159643acfa --- /dev/null +++ b/pac/atsamc20n/src/generic.rs @@ -0,0 +1,260 @@ +use core::marker; +#[doc = " Raw register type"] +pub trait RegisterSpec { + #[doc = " Raw register type (`u8`, `u16`, `u32`, ...)."] + type Ux: Copy; +} +#[doc = " Trait implemented by readable registers to enable the `read` method."] +#[doc = ""] +#[doc = " Registers marked with `Writable` can be also `modify`'ed."] +pub trait Readable: RegisterSpec { + #[doc = " Result from a call to `read` and argument to `modify`."] + type Reader: From> + core::ops::Deref>; +} +#[doc = " Trait implemented by writeable registers."] +#[doc = ""] +#[doc = " This enables the `write`, `write_with_zero` and `reset` methods."] +#[doc = ""] +#[doc = " Registers marked with `Readable` can be also `modify`'ed."] +pub trait Writable: RegisterSpec { + #[doc = " Writer type argument to `write`, et al."] + type Writer: From> + core::ops::DerefMut>; +} +#[doc = " Reset value of the register."] +#[doc = ""] +#[doc = " This value is the initial value for the `write` method. It can also be directly written to the"] +#[doc = " register by using the `reset` method."] +pub trait Resettable: RegisterSpec { + #[doc = " Reset value of the register."] + fn reset_value() -> Self::Ux; +} +#[doc = " This structure provides volatile access to registers."] +#[repr(transparent)] +pub struct Reg { + register: vcell::VolatileCell, + _marker: marker::PhantomData, +} +unsafe impl Send for Reg where REG::Ux: Send {} +impl Reg { + #[doc = " Returns the underlying memory address of register."] + #[doc = ""] + #[doc = " ```ignore"] + #[doc = " let reg_ptr = periph.reg.as_ptr();"] + #[doc = " ```"] + #[inline(always)] + pub fn as_ptr(&self) -> *mut REG::Ux { + self.register.as_ptr() + } +} +impl Reg { + #[doc = " Reads the contents of a `Readable` register."] + #[doc = ""] + #[doc = " You can read the raw contents of a register by using `bits`:"] + #[doc = " ```ignore"] + #[doc = " let bits = periph.reg.read().bits();"] + #[doc = " ```"] + #[doc = " or get the content of a particular field of a register:"] + #[doc = " ```ignore"] + #[doc = " let reader = periph.reg.read();"] + #[doc = " let bits = reader.field1().bits();"] + #[doc = " let flag = reader.field2().bit_is_set();"] + #[doc = " ```"] + #[inline(always)] + pub fn read(&self) -> REG::Reader { + REG::Reader::from(R { + bits: self.register.get(), + _reg: marker::PhantomData, + }) + } +} +impl Reg { + #[doc = " Writes the reset value to `Writable` register."] + #[doc = ""] + #[doc = " Resets the register to its initial state."] + #[inline(always)] + pub fn reset(&self) { + self.register.set(REG::reset_value()) + } + #[doc = " Writes bits to a `Writable` register."] + #[doc = ""] + #[doc = " You can write raw bits into a register:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.write(|w| unsafe { w.bits(rawbits) });"] + #[doc = " ```"] + #[doc = " or write only the fields you need:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.write(|w| w"] + #[doc = " .field1().bits(newfield1bits)"] + #[doc = " .field2().set_bit()"] + #[doc = " .field3().variant(VARIANT)"] + #[doc = " );"] + #[doc = " ```"] + #[doc = " In the latter case, other fields will be set to their reset value."] + #[inline(always)] + pub fn write(&self, f: F) + where + F: FnOnce(&mut REG::Writer) -> &mut W, + { + self.register.set( + f(&mut REG::Writer::from(W { + bits: REG::reset_value(), + _reg: marker::PhantomData, + })) + .bits, + ); + } +} +impl Reg +where + REG::Ux: Default, +{ + #[doc = " Writes 0 to a `Writable` register."] + #[doc = ""] + #[doc = " Similar to `write`, but unused bits will contain 0."] + #[inline(always)] + pub unsafe fn write_with_zero(&self, f: F) + where + F: FnOnce(&mut REG::Writer) -> &mut W, + { + self.register.set( + (*f(&mut REG::Writer::from(W { + bits: REG::Ux::default(), + _reg: marker::PhantomData, + }))) + .bits, + ); + } +} +impl Reg { + #[doc = " Modifies the contents of the register by reading and then writing it."] + #[doc = ""] + #[doc = " E.g. to do a read-modify-write sequence to change parts of a register:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.modify(|r, w| unsafe { w.bits("] + #[doc = " r.bits() | 3"] + #[doc = " ) });"] + #[doc = " ```"] + #[doc = " or"] + #[doc = " ```ignore"] + #[doc = " periph.reg.modify(|_, w| w"] + #[doc = " .field1().bits(newfield1bits)"] + #[doc = " .field2().set_bit()"] + #[doc = " .field3().variant(VARIANT)"] + #[doc = " );"] + #[doc = " ```"] + #[doc = " Other fields will have the value they had before the call to `modify`."] + #[inline(always)] + pub fn modify(&self, f: F) + where + for<'w> F: FnOnce(®::Reader, &'w mut REG::Writer) -> &'w mut W, + { + let bits = self.register.get(); + self.register.set( + f( + ®::Reader::from(R { + bits, + _reg: marker::PhantomData, + }), + &mut REG::Writer::from(W { + bits, + _reg: marker::PhantomData, + }), + ) + .bits, + ); + } +} +#[doc = " Register reader."] +#[doc = ""] +#[doc = " Result of the `read` methods of registers. Also used as a closure argument in the `modify`"] +#[doc = " method."] +pub struct R { + pub(crate) bits: REG::Ux, + _reg: marker::PhantomData, +} +impl R { + #[doc = " Reads raw bits from register."] + #[inline(always)] + pub fn bits(&self) -> REG::Ux { + self.bits + } +} +impl PartialEq for R +where + REG::Ux: PartialEq, + FI: Copy + Into, +{ + #[inline(always)] + fn eq(&self, other: &FI) -> bool { + self.bits.eq(&(*other).into()) + } +} +#[doc = " Register writer."] +#[doc = ""] +#[doc = " Used as an argument to the closures in the `write` and `modify` methods of the register."] +pub struct W { + #[doc = "Writable bits"] + pub(crate) bits: REG::Ux, + _reg: marker::PhantomData, +} +impl W { + #[doc = " Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = " Field reader."] +#[doc = ""] +#[doc = " Result of the `read` methods of fields."] +pub struct FieldReader { + pub(crate) bits: U, + _reg: marker::PhantomData, +} +impl FieldReader +where + U: Copy, +{ + #[doc = " Creates a new instance of the reader."] + #[allow(unused)] + #[inline(always)] + pub(crate) fn new(bits: U) -> Self { + Self { + bits, + _reg: marker::PhantomData, + } + } + #[doc = " Reads raw bits from field."] + #[inline(always)] + pub fn bits(&self) -> U { + self.bits + } +} +impl PartialEq for FieldReader +where + U: PartialEq, + FI: Copy + Into, +{ + #[inline(always)] + fn eq(&self, other: &FI) -> bool { + self.bits.eq(&(*other).into()) + } +} +impl FieldReader { + #[doc = " Value of the field as raw bits."] + #[inline(always)] + pub fn bit(&self) -> bool { + self.bits + } + #[doc = " Returns `true` if the bit is clear (0)."] + #[inline(always)] + pub fn bit_is_clear(&self) -> bool { + !self.bit() + } + #[doc = " Returns `true` if the bit is set (1)."] + #[inline(always)] + pub fn bit_is_set(&self) -> bool { + self.bit() + } +} diff --git a/pac/atsamc20n/src/hmatrixhs.rs b/pac/atsamc20n/src/hmatrixhs.rs new file mode 100644 index 000000000000..c8129ac89b6f --- /dev/null +++ b/pac/atsamc20n/src/hmatrixhs.rs @@ -0,0 +1,43 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00..0x40 - Master Configuration"] + pub mcfg: [crate::Reg; 16], + #[doc = "0x40..0x80 - Slave Configuration"] + pub scfg: [crate::Reg; 16], + #[doc = "0x80..0xa0 - PRS\\[%s\\]"] + pub prs: [PRS; 4], + _reserved3: [u8; 0x60], + #[doc = "0x100 - Master Remap Control"] + pub mrcr: crate::Reg, + _reserved4: [u8; 0x0c], + #[doc = "0x110..0x150 - Special Function"] + pub sfr: [crate::Reg; 16], +} +#[doc = r"Register block"] +#[repr(C)] +pub struct PRS { + #[doc = "0x00 - Priority A for Slave"] + pub pras: crate::Reg, + #[doc = "0x04 - Priority B for Slave"] + pub prbs: crate::Reg, +} +#[doc = r"Register block"] +#[doc = "PRS\\[%s\\]"] +pub mod prs; +#[doc = "MCFG register accessor: an alias for `Reg`"] +pub type MCFG = crate::Reg; +#[doc = "Master Configuration"] +pub mod mcfg; +#[doc = "SCFG register accessor: an alias for `Reg`"] +pub type SCFG = crate::Reg; +#[doc = "Slave Configuration"] +pub mod scfg; +#[doc = "MRCR register accessor: an alias for `Reg`"] +pub type MRCR = crate::Reg; +#[doc = "Master Remap Control"] +pub mod mrcr; +#[doc = "SFR register accessor: an alias for `Reg`"] +pub type SFR = crate::Reg; +#[doc = "Special Function"] +pub mod sfr; diff --git a/pac/atsamc20n/src/hmatrixhs/mcfg.rs b/pac/atsamc20n/src/hmatrixhs/mcfg.rs new file mode 100644 index 000000000000..454a39fabe13 --- /dev/null +++ b/pac/atsamc20n/src/hmatrixhs/mcfg.rs @@ -0,0 +1,192 @@ +#[doc = "Register `MCFG[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MCFG[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Undefined Length Burst Type\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum ULBT_A { + #[doc = "0: Infinite Length"] + INFINITE = 0, + #[doc = "1: Single Access"] + SINGLE = 1, + #[doc = "2: Four Beat Burst"] + FOUR_BEAT = 2, + #[doc = "3: Eight Beat Burst"] + EIGHT_BEAT = 3, + #[doc = "4: Sixteen Beat Burst"] + SIXTEEN_BEAT = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: ULBT_A) -> Self { + variant as _ + } +} +#[doc = "Field `ULBT` reader - Undefined Length Burst Type"] +pub struct ULBT_R(crate::FieldReader); +impl ULBT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ULBT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(ULBT_A::INFINITE), + 1 => Some(ULBT_A::SINGLE), + 2 => Some(ULBT_A::FOUR_BEAT), + 3 => Some(ULBT_A::EIGHT_BEAT), + 4 => Some(ULBT_A::SIXTEEN_BEAT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `INFINITE`"] + #[inline(always)] + pub fn is_infinite(&self) -> bool { + **self == ULBT_A::INFINITE + } + #[doc = "Checks if the value of the field is `SINGLE`"] + #[inline(always)] + pub fn is_single(&self) -> bool { + **self == ULBT_A::SINGLE + } + #[doc = "Checks if the value of the field is `FOUR_BEAT`"] + #[inline(always)] + pub fn is_four_beat(&self) -> bool { + **self == ULBT_A::FOUR_BEAT + } + #[doc = "Checks if the value of the field is `EIGHT_BEAT`"] + #[inline(always)] + pub fn is_eight_beat(&self) -> bool { + **self == ULBT_A::EIGHT_BEAT + } + #[doc = "Checks if the value of the field is `SIXTEEN_BEAT`"] + #[inline(always)] + pub fn is_sixteen_beat(&self) -> bool { + **self == ULBT_A::SIXTEEN_BEAT + } +} +impl core::ops::Deref for ULBT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ULBT` writer - Undefined Length Burst Type"] +pub struct ULBT_W<'a> { + w: &'a mut W, +} +impl<'a> ULBT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: ULBT_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Infinite Length"] + #[inline(always)] + pub fn infinite(self) -> &'a mut W { + self.variant(ULBT_A::INFINITE) + } + #[doc = "Single Access"] + #[inline(always)] + pub fn single(self) -> &'a mut W { + self.variant(ULBT_A::SINGLE) + } + #[doc = "Four Beat Burst"] + #[inline(always)] + pub fn four_beat(self) -> &'a mut W { + self.variant(ULBT_A::FOUR_BEAT) + } + #[doc = "Eight Beat Burst"] + #[inline(always)] + pub fn eight_beat(self) -> &'a mut W { + self.variant(ULBT_A::EIGHT_BEAT) + } + #[doc = "Sixteen Beat Burst"] + #[inline(always)] + pub fn sixteen_beat(self) -> &'a mut W { + self.variant(ULBT_A::SIXTEEN_BEAT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Undefined Length Burst Type"] + #[inline(always)] + pub fn ulbt(&self) -> ULBT_R { + ULBT_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Undefined Length Burst Type"] + #[inline(always)] + pub fn ulbt(&mut self) -> ULBT_W { + ULBT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Master Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mcfg](index.html) module"] +pub struct MCFG_SPEC; +impl crate::RegisterSpec for MCFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [mcfg::R](R) reader structure"] +impl crate::Readable for MCFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [mcfg::W](W) writer structure"] +impl crate::Writable for MCFG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets MCFG[%s] +to value 0x02"] +impl crate::Resettable for MCFG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x02 + } +} diff --git a/pac/atsamc20n/src/hmatrixhs/mrcr.rs b/pac/atsamc20n/src/hmatrixhs/mrcr.rs new file mode 100644 index 000000000000..0cf2a1fb01be --- /dev/null +++ b/pac/atsamc20n/src/hmatrixhs/mrcr.rs @@ -0,0 +1,1570 @@ +#[doc = "Register `MRCR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MRCR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Remap Command Bit for Master 0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB0_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB0_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB0` reader - Remap Command Bit for Master 0"] +pub struct RCB0_R(crate::FieldReader); +impl RCB0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB0_A { + match self.bits { + false => RCB0_A::DIS, + true => RCB0_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB0_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB0_A::ENA + } +} +impl core::ops::Deref for RCB0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB0` writer - Remap Command Bit for Master 0"] +pub struct RCB0_W<'a> { + w: &'a mut W, +} +impl<'a> RCB0_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB0_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB0_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB0_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Remap Command Bit for Master 1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB1_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB1_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB1` reader - Remap Command Bit for Master 1"] +pub struct RCB1_R(crate::FieldReader); +impl RCB1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB1_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB1_A { + match self.bits { + false => RCB1_A::DIS, + true => RCB1_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB1_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB1_A::ENA + } +} +impl core::ops::Deref for RCB1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB1` writer - Remap Command Bit for Master 1"] +pub struct RCB1_W<'a> { + w: &'a mut W, +} +impl<'a> RCB1_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB1_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB1_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB1_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Remap Command Bit for Master 2\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB2_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB2_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB2` reader - Remap Command Bit for Master 2"] +pub struct RCB2_R(crate::FieldReader); +impl RCB2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB2_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB2_A { + match self.bits { + false => RCB2_A::DIS, + true => RCB2_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB2_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB2_A::ENA + } +} +impl core::ops::Deref for RCB2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB2` writer - Remap Command Bit for Master 2"] +pub struct RCB2_W<'a> { + w: &'a mut W, +} +impl<'a> RCB2_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB2_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB2_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB2_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Remap Command Bit for Master 3\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB3_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB3_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB3` reader - Remap Command Bit for Master 3"] +pub struct RCB3_R(crate::FieldReader); +impl RCB3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB3_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB3_A { + match self.bits { + false => RCB3_A::DIS, + true => RCB3_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB3_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB3_A::ENA + } +} +impl core::ops::Deref for RCB3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB3` writer - Remap Command Bit for Master 3"] +pub struct RCB3_W<'a> { + w: &'a mut W, +} +impl<'a> RCB3_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB3_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB3_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB3_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Remap Command Bit for Master 4\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB4_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB4_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB4` reader - Remap Command Bit for Master 4"] +pub struct RCB4_R(crate::FieldReader); +impl RCB4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB4_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB4_A { + match self.bits { + false => RCB4_A::DIS, + true => RCB4_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB4_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB4_A::ENA + } +} +impl core::ops::Deref for RCB4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB4` writer - Remap Command Bit for Master 4"] +pub struct RCB4_W<'a> { + w: &'a mut W, +} +impl<'a> RCB4_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB4_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB4_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB4_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Remap Command Bit for Master 5\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB5_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB5_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB5` reader - Remap Command Bit for Master 5"] +pub struct RCB5_R(crate::FieldReader); +impl RCB5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB5_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB5_A { + match self.bits { + false => RCB5_A::DIS, + true => RCB5_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB5_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB5_A::ENA + } +} +impl core::ops::Deref for RCB5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB5` writer - Remap Command Bit for Master 5"] +pub struct RCB5_W<'a> { + w: &'a mut W, +} +impl<'a> RCB5_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB5_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB5_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB5_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Remap Command Bit for Master 6\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB6_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB6_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB6` reader - Remap Command Bit for Master 6"] +pub struct RCB6_R(crate::FieldReader); +impl RCB6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB6_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB6_A { + match self.bits { + false => RCB6_A::DIS, + true => RCB6_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB6_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB6_A::ENA + } +} +impl core::ops::Deref for RCB6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB6` writer - Remap Command Bit for Master 6"] +pub struct RCB6_W<'a> { + w: &'a mut W, +} +impl<'a> RCB6_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB6_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB6_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB6_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Remap Command Bit for Master 7\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB7_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB7_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB7` reader - Remap Command Bit for Master 7"] +pub struct RCB7_R(crate::FieldReader); +impl RCB7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB7_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB7_A { + match self.bits { + false => RCB7_A::DIS, + true => RCB7_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB7_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB7_A::ENA + } +} +impl core::ops::Deref for RCB7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB7` writer - Remap Command Bit for Master 7"] +pub struct RCB7_W<'a> { + w: &'a mut W, +} +impl<'a> RCB7_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB7_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB7_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB7_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Remap Command Bit for Master 8\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB8_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB8_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB8` reader - Remap Command Bit for Master 8"] +pub struct RCB8_R(crate::FieldReader); +impl RCB8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB8_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB8_A { + match self.bits { + false => RCB8_A::DIS, + true => RCB8_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB8_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB8_A::ENA + } +} +impl core::ops::Deref for RCB8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB8` writer - Remap Command Bit for Master 8"] +pub struct RCB8_W<'a> { + w: &'a mut W, +} +impl<'a> RCB8_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB8_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB8_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB8_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Remap Command Bit for Master 9\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB9_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB9_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB9` reader - Remap Command Bit for Master 9"] +pub struct RCB9_R(crate::FieldReader); +impl RCB9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB9_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB9_A { + match self.bits { + false => RCB9_A::DIS, + true => RCB9_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB9_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB9_A::ENA + } +} +impl core::ops::Deref for RCB9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB9` writer - Remap Command Bit for Master 9"] +pub struct RCB9_W<'a> { + w: &'a mut W, +} +impl<'a> RCB9_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB9_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB9_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB9_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Remap Command Bit for Master 10\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB10_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB10_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB10` reader - Remap Command Bit for Master 10"] +pub struct RCB10_R(crate::FieldReader); +impl RCB10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB10_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB10_A { + match self.bits { + false => RCB10_A::DIS, + true => RCB10_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB10_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB10_A::ENA + } +} +impl core::ops::Deref for RCB10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB10` writer - Remap Command Bit for Master 10"] +pub struct RCB10_W<'a> { + w: &'a mut W, +} +impl<'a> RCB10_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB10_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB10_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB10_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Remap Command Bit for Master 11\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB11_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB11_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB11` reader - Remap Command Bit for Master 11"] +pub struct RCB11_R(crate::FieldReader); +impl RCB11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB11_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB11_A { + match self.bits { + false => RCB11_A::DIS, + true => RCB11_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB11_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB11_A::ENA + } +} +impl core::ops::Deref for RCB11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB11` writer - Remap Command Bit for Master 11"] +pub struct RCB11_W<'a> { + w: &'a mut W, +} +impl<'a> RCB11_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB11_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB11_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB11_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Remap Command Bit for Master 12\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB12_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB12_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB12` reader - Remap Command Bit for Master 12"] +pub struct RCB12_R(crate::FieldReader); +impl RCB12_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB12_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB12_A { + match self.bits { + false => RCB12_A::DIS, + true => RCB12_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB12_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB12_A::ENA + } +} +impl core::ops::Deref for RCB12_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB12` writer - Remap Command Bit for Master 12"] +pub struct RCB12_W<'a> { + w: &'a mut W, +} +impl<'a> RCB12_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB12_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB12_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB12_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Remap Command Bit for Master 13\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB13_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB13_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB13` reader - Remap Command Bit for Master 13"] +pub struct RCB13_R(crate::FieldReader); +impl RCB13_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB13_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB13_A { + match self.bits { + false => RCB13_A::DIS, + true => RCB13_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB13_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB13_A::ENA + } +} +impl core::ops::Deref for RCB13_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB13` writer - Remap Command Bit for Master 13"] +pub struct RCB13_W<'a> { + w: &'a mut W, +} +impl<'a> RCB13_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB13_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB13_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB13_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Remap Command Bit for Master 14\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB14_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB14_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB14` reader - Remap Command Bit for Master 14"] +pub struct RCB14_R(crate::FieldReader); +impl RCB14_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB14_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB14_A { + match self.bits { + false => RCB14_A::DIS, + true => RCB14_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB14_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB14_A::ENA + } +} +impl core::ops::Deref for RCB14_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB14` writer - Remap Command Bit for Master 14"] +pub struct RCB14_W<'a> { + w: &'a mut W, +} +impl<'a> RCB14_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB14_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB14_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB14_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Remap Command Bit for Master 15\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB15_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB15_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB15` reader - Remap Command Bit for Master 15"] +pub struct RCB15_R(crate::FieldReader); +impl RCB15_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB15_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB15_A { + match self.bits { + false => RCB15_A::DIS, + true => RCB15_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB15_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB15_A::ENA + } +} +impl core::ops::Deref for RCB15_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB15` writer - Remap Command Bit for Master 15"] +pub struct RCB15_W<'a> { + w: &'a mut W, +} +impl<'a> RCB15_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB15_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB15_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB15_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Remap Command Bit for Master 0"] + #[inline(always)] + pub fn rcb0(&self) -> RCB0_R { + RCB0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Remap Command Bit for Master 1"] + #[inline(always)] + pub fn rcb1(&self) -> RCB1_R { + RCB1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Remap Command Bit for Master 2"] + #[inline(always)] + pub fn rcb2(&self) -> RCB2_R { + RCB2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Remap Command Bit for Master 3"] + #[inline(always)] + pub fn rcb3(&self) -> RCB3_R { + RCB3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Remap Command Bit for Master 4"] + #[inline(always)] + pub fn rcb4(&self) -> RCB4_R { + RCB4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Remap Command Bit for Master 5"] + #[inline(always)] + pub fn rcb5(&self) -> RCB5_R { + RCB5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Remap Command Bit for Master 6"] + #[inline(always)] + pub fn rcb6(&self) -> RCB6_R { + RCB6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Remap Command Bit for Master 7"] + #[inline(always)] + pub fn rcb7(&self) -> RCB7_R { + RCB7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Remap Command Bit for Master 8"] + #[inline(always)] + pub fn rcb8(&self) -> RCB8_R { + RCB8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Remap Command Bit for Master 9"] + #[inline(always)] + pub fn rcb9(&self) -> RCB9_R { + RCB9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Remap Command Bit for Master 10"] + #[inline(always)] + pub fn rcb10(&self) -> RCB10_R { + RCB10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Remap Command Bit for Master 11"] + #[inline(always)] + pub fn rcb11(&self) -> RCB11_R { + RCB11_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Remap Command Bit for Master 12"] + #[inline(always)] + pub fn rcb12(&self) -> RCB12_R { + RCB12_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Remap Command Bit for Master 13"] + #[inline(always)] + pub fn rcb13(&self) -> RCB13_R { + RCB13_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Remap Command Bit for Master 14"] + #[inline(always)] + pub fn rcb14(&self) -> RCB14_R { + RCB14_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Remap Command Bit for Master 15"] + #[inline(always)] + pub fn rcb15(&self) -> RCB15_R { + RCB15_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Remap Command Bit for Master 0"] + #[inline(always)] + pub fn rcb0(&mut self) -> RCB0_W { + RCB0_W { w: self } + } + #[doc = "Bit 1 - Remap Command Bit for Master 1"] + #[inline(always)] + pub fn rcb1(&mut self) -> RCB1_W { + RCB1_W { w: self } + } + #[doc = "Bit 2 - Remap Command Bit for Master 2"] + #[inline(always)] + pub fn rcb2(&mut self) -> RCB2_W { + RCB2_W { w: self } + } + #[doc = "Bit 3 - Remap Command Bit for Master 3"] + #[inline(always)] + pub fn rcb3(&mut self) -> RCB3_W { + RCB3_W { w: self } + } + #[doc = "Bit 4 - Remap Command Bit for Master 4"] + #[inline(always)] + pub fn rcb4(&mut self) -> RCB4_W { + RCB4_W { w: self } + } + #[doc = "Bit 5 - Remap Command Bit for Master 5"] + #[inline(always)] + pub fn rcb5(&mut self) -> RCB5_W { + RCB5_W { w: self } + } + #[doc = "Bit 6 - Remap Command Bit for Master 6"] + #[inline(always)] + pub fn rcb6(&mut self) -> RCB6_W { + RCB6_W { w: self } + } + #[doc = "Bit 7 - Remap Command Bit for Master 7"] + #[inline(always)] + pub fn rcb7(&mut self) -> RCB7_W { + RCB7_W { w: self } + } + #[doc = "Bit 8 - Remap Command Bit for Master 8"] + #[inline(always)] + pub fn rcb8(&mut self) -> RCB8_W { + RCB8_W { w: self } + } + #[doc = "Bit 9 - Remap Command Bit for Master 9"] + #[inline(always)] + pub fn rcb9(&mut self) -> RCB9_W { + RCB9_W { w: self } + } + #[doc = "Bit 10 - Remap Command Bit for Master 10"] + #[inline(always)] + pub fn rcb10(&mut self) -> RCB10_W { + RCB10_W { w: self } + } + #[doc = "Bit 11 - Remap Command Bit for Master 11"] + #[inline(always)] + pub fn rcb11(&mut self) -> RCB11_W { + RCB11_W { w: self } + } + #[doc = "Bit 12 - Remap Command Bit for Master 12"] + #[inline(always)] + pub fn rcb12(&mut self) -> RCB12_W { + RCB12_W { w: self } + } + #[doc = "Bit 13 - Remap Command Bit for Master 13"] + #[inline(always)] + pub fn rcb13(&mut self) -> RCB13_W { + RCB13_W { w: self } + } + #[doc = "Bit 14 - Remap Command Bit for Master 14"] + #[inline(always)] + pub fn rcb14(&mut self) -> RCB14_W { + RCB14_W { w: self } + } + #[doc = "Bit 15 - Remap Command Bit for Master 15"] + #[inline(always)] + pub fn rcb15(&mut self) -> RCB15_W { + RCB15_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Master Remap Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mrcr](index.html) module"] +pub struct MRCR_SPEC; +impl crate::RegisterSpec for MRCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [mrcr::R](R) reader structure"] +impl crate::Readable for MRCR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [mrcr::W](W) writer structure"] +impl crate::Writable for MRCR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets MRCR to value 0"] +impl crate::Resettable for MRCR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/hmatrixhs/prs.rs b/pac/atsamc20n/src/hmatrixhs/prs.rs new file mode 100644 index 000000000000..0313f3c4fc20 --- /dev/null +++ b/pac/atsamc20n/src/hmatrixhs/prs.rs @@ -0,0 +1,8 @@ +#[doc = "PRAS register accessor: an alias for `Reg`"] +pub type PRAS = crate::Reg; +#[doc = "Priority A for Slave"] +pub mod pras; +#[doc = "PRBS register accessor: an alias for `Reg`"] +pub type PRBS = crate::Reg; +#[doc = "Priority B for Slave"] +pub mod prbs; diff --git a/pac/atsamc20n/src/hmatrixhs/prs/pras.rs b/pac/atsamc20n/src/hmatrixhs/prs/pras.rs new file mode 100644 index 000000000000..ac4744a9e2a0 --- /dev/null +++ b/pac/atsamc20n/src/hmatrixhs/prs/pras.rs @@ -0,0 +1,362 @@ +#[doc = "Register `PRAS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PRAS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `M0PR` reader - Master 0 Priority"] +pub struct M0PR_R(crate::FieldReader); +impl M0PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M0PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M0PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M0PR` writer - Master 0 Priority"] +pub struct M0PR_W<'a> { + w: &'a mut W, +} +impl<'a> M0PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Field `M1PR` reader - Master 1 Priority"] +pub struct M1PR_R(crate::FieldReader); +impl M1PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M1PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M1PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M1PR` writer - Master 1 Priority"] +pub struct M1PR_W<'a> { + w: &'a mut W, +} +impl<'a> M1PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 4)) | ((value as u32 & 0x0f) << 4); + self.w + } +} +#[doc = "Field `M2PR` reader - Master 2 Priority"] +pub struct M2PR_R(crate::FieldReader); +impl M2PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M2PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M2PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M2PR` writer - Master 2 Priority"] +pub struct M2PR_W<'a> { + w: &'a mut W, +} +impl<'a> M2PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 8)) | ((value as u32 & 0x0f) << 8); + self.w + } +} +#[doc = "Field `M3PR` reader - Master 3 Priority"] +pub struct M3PR_R(crate::FieldReader); +impl M3PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M3PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M3PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M3PR` writer - Master 3 Priority"] +pub struct M3PR_W<'a> { + w: &'a mut W, +} +impl<'a> M3PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 12)) | ((value as u32 & 0x0f) << 12); + self.w + } +} +#[doc = "Field `M4PR` reader - Master 4 Priority"] +pub struct M4PR_R(crate::FieldReader); +impl M4PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M4PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M4PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M4PR` writer - Master 4 Priority"] +pub struct M4PR_W<'a> { + w: &'a mut W, +} +impl<'a> M4PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 16)) | ((value as u32 & 0x0f) << 16); + self.w + } +} +#[doc = "Field `M5PR` reader - Master 5 Priority"] +pub struct M5PR_R(crate::FieldReader); +impl M5PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M5PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M5PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M5PR` writer - Master 5 Priority"] +pub struct M5PR_W<'a> { + w: &'a mut W, +} +impl<'a> M5PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 20)) | ((value as u32 & 0x0f) << 20); + self.w + } +} +#[doc = "Field `M6PR` reader - Master 6 Priority"] +pub struct M6PR_R(crate::FieldReader); +impl M6PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M6PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M6PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M6PR` writer - Master 6 Priority"] +pub struct M6PR_W<'a> { + w: &'a mut W, +} +impl<'a> M6PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Field `M7PR` reader - Master 7 Priority"] +pub struct M7PR_R(crate::FieldReader); +impl M7PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M7PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M7PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M7PR` writer - Master 7 Priority"] +pub struct M7PR_W<'a> { + w: &'a mut W, +} +impl<'a> M7PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 28)) | ((value as u32 & 0x0f) << 28); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Master 0 Priority"] + #[inline(always)] + pub fn m0pr(&self) -> M0PR_R { + M0PR_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Master 1 Priority"] + #[inline(always)] + pub fn m1pr(&self) -> M1PR_R { + M1PR_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 8:11 - Master 2 Priority"] + #[inline(always)] + pub fn m2pr(&self) -> M2PR_R { + M2PR_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - Master 3 Priority"] + #[inline(always)] + pub fn m3pr(&self) -> M3PR_R { + M3PR_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:19 - Master 4 Priority"] + #[inline(always)] + pub fn m4pr(&self) -> M4PR_R { + M4PR_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bits 20:23 - Master 5 Priority"] + #[inline(always)] + pub fn m5pr(&self) -> M5PR_R { + M5PR_R::new(((self.bits >> 20) & 0x0f) as u8) + } + #[doc = "Bits 24:27 - Master 6 Priority"] + #[inline(always)] + pub fn m6pr(&self) -> M6PR_R { + M6PR_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bits 28:31 - Master 7 Priority"] + #[inline(always)] + pub fn m7pr(&self) -> M7PR_R { + M7PR_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Master 0 Priority"] + #[inline(always)] + pub fn m0pr(&mut self) -> M0PR_W { + M0PR_W { w: self } + } + #[doc = "Bits 4:7 - Master 1 Priority"] + #[inline(always)] + pub fn m1pr(&mut self) -> M1PR_W { + M1PR_W { w: self } + } + #[doc = "Bits 8:11 - Master 2 Priority"] + #[inline(always)] + pub fn m2pr(&mut self) -> M2PR_W { + M2PR_W { w: self } + } + #[doc = "Bits 12:15 - Master 3 Priority"] + #[inline(always)] + pub fn m3pr(&mut self) -> M3PR_W { + M3PR_W { w: self } + } + #[doc = "Bits 16:19 - Master 4 Priority"] + #[inline(always)] + pub fn m4pr(&mut self) -> M4PR_W { + M4PR_W { w: self } + } + #[doc = "Bits 20:23 - Master 5 Priority"] + #[inline(always)] + pub fn m5pr(&mut self) -> M5PR_W { + M5PR_W { w: self } + } + #[doc = "Bits 24:27 - Master 6 Priority"] + #[inline(always)] + pub fn m6pr(&mut self) -> M6PR_W { + M6PR_W { w: self } + } + #[doc = "Bits 28:31 - Master 7 Priority"] + #[inline(always)] + pub fn m7pr(&mut self) -> M7PR_W { + M7PR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Priority A for Slave\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pras](index.html) module"] +pub struct PRAS_SPEC; +impl crate::RegisterSpec for PRAS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pras::R](R) reader structure"] +impl crate::Readable for PRAS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [pras::W](W) writer structure"] +impl crate::Writable for PRAS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PRAS to value 0"] +impl crate::Resettable for PRAS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/hmatrixhs/prs/prbs.rs b/pac/atsamc20n/src/hmatrixhs/prs/prbs.rs new file mode 100644 index 000000000000..a2cc6bb9f6b0 --- /dev/null +++ b/pac/atsamc20n/src/hmatrixhs/prs/prbs.rs @@ -0,0 +1,362 @@ +#[doc = "Register `PRBS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PRBS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `M8PR` reader - Master 8 Priority"] +pub struct M8PR_R(crate::FieldReader); +impl M8PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M8PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M8PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M8PR` writer - Master 8 Priority"] +pub struct M8PR_W<'a> { + w: &'a mut W, +} +impl<'a> M8PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Field `M9PR` reader - Master 9 Priority"] +pub struct M9PR_R(crate::FieldReader); +impl M9PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M9PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M9PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M9PR` writer - Master 9 Priority"] +pub struct M9PR_W<'a> { + w: &'a mut W, +} +impl<'a> M9PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 4)) | ((value as u32 & 0x0f) << 4); + self.w + } +} +#[doc = "Field `M10PR` reader - Master 10 Priority"] +pub struct M10PR_R(crate::FieldReader); +impl M10PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M10PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M10PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M10PR` writer - Master 10 Priority"] +pub struct M10PR_W<'a> { + w: &'a mut W, +} +impl<'a> M10PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 8)) | ((value as u32 & 0x0f) << 8); + self.w + } +} +#[doc = "Field `M11PR` reader - Master 11 Priority"] +pub struct M11PR_R(crate::FieldReader); +impl M11PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M11PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M11PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M11PR` writer - Master 11 Priority"] +pub struct M11PR_W<'a> { + w: &'a mut W, +} +impl<'a> M11PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 12)) | ((value as u32 & 0x0f) << 12); + self.w + } +} +#[doc = "Field `M12PR` reader - Master 12 Priority"] +pub struct M12PR_R(crate::FieldReader); +impl M12PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M12PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M12PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M12PR` writer - Master 12 Priority"] +pub struct M12PR_W<'a> { + w: &'a mut W, +} +impl<'a> M12PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 16)) | ((value as u32 & 0x0f) << 16); + self.w + } +} +#[doc = "Field `M13PR` reader - Master 13 Priority"] +pub struct M13PR_R(crate::FieldReader); +impl M13PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M13PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M13PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M13PR` writer - Master 13 Priority"] +pub struct M13PR_W<'a> { + w: &'a mut W, +} +impl<'a> M13PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 20)) | ((value as u32 & 0x0f) << 20); + self.w + } +} +#[doc = "Field `M14PR` reader - Master 14 Priority"] +pub struct M14PR_R(crate::FieldReader); +impl M14PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M14PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M14PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M14PR` writer - Master 14 Priority"] +pub struct M14PR_W<'a> { + w: &'a mut W, +} +impl<'a> M14PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Field `M15PR` reader - Master 15 Priority"] +pub struct M15PR_R(crate::FieldReader); +impl M15PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M15PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M15PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M15PR` writer - Master 15 Priority"] +pub struct M15PR_W<'a> { + w: &'a mut W, +} +impl<'a> M15PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 28)) | ((value as u32 & 0x0f) << 28); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Master 8 Priority"] + #[inline(always)] + pub fn m8pr(&self) -> M8PR_R { + M8PR_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Master 9 Priority"] + #[inline(always)] + pub fn m9pr(&self) -> M9PR_R { + M9PR_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 8:11 - Master 10 Priority"] + #[inline(always)] + pub fn m10pr(&self) -> M10PR_R { + M10PR_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - Master 11 Priority"] + #[inline(always)] + pub fn m11pr(&self) -> M11PR_R { + M11PR_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:19 - Master 12 Priority"] + #[inline(always)] + pub fn m12pr(&self) -> M12PR_R { + M12PR_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bits 20:23 - Master 13 Priority"] + #[inline(always)] + pub fn m13pr(&self) -> M13PR_R { + M13PR_R::new(((self.bits >> 20) & 0x0f) as u8) + } + #[doc = "Bits 24:27 - Master 14 Priority"] + #[inline(always)] + pub fn m14pr(&self) -> M14PR_R { + M14PR_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bits 28:31 - Master 15 Priority"] + #[inline(always)] + pub fn m15pr(&self) -> M15PR_R { + M15PR_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Master 8 Priority"] + #[inline(always)] + pub fn m8pr(&mut self) -> M8PR_W { + M8PR_W { w: self } + } + #[doc = "Bits 4:7 - Master 9 Priority"] + #[inline(always)] + pub fn m9pr(&mut self) -> M9PR_W { + M9PR_W { w: self } + } + #[doc = "Bits 8:11 - Master 10 Priority"] + #[inline(always)] + pub fn m10pr(&mut self) -> M10PR_W { + M10PR_W { w: self } + } + #[doc = "Bits 12:15 - Master 11 Priority"] + #[inline(always)] + pub fn m11pr(&mut self) -> M11PR_W { + M11PR_W { w: self } + } + #[doc = "Bits 16:19 - Master 12 Priority"] + #[inline(always)] + pub fn m12pr(&mut self) -> M12PR_W { + M12PR_W { w: self } + } + #[doc = "Bits 20:23 - Master 13 Priority"] + #[inline(always)] + pub fn m13pr(&mut self) -> M13PR_W { + M13PR_W { w: self } + } + #[doc = "Bits 24:27 - Master 14 Priority"] + #[inline(always)] + pub fn m14pr(&mut self) -> M14PR_W { + M14PR_W { w: self } + } + #[doc = "Bits 28:31 - Master 15 Priority"] + #[inline(always)] + pub fn m15pr(&mut self) -> M15PR_W { + M15PR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Priority B for Slave\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [prbs](index.html) module"] +pub struct PRBS_SPEC; +impl crate::RegisterSpec for PRBS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [prbs::R](R) reader structure"] +impl crate::Readable for PRBS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [prbs::W](W) writer structure"] +impl crate::Writable for PRBS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PRBS to value 0"] +impl crate::Resettable for PRBS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/hmatrixhs/scfg.rs b/pac/atsamc20n/src/hmatrixhs/scfg.rs new file mode 100644 index 000000000000..7180c043195a --- /dev/null +++ b/pac/atsamc20n/src/hmatrixhs/scfg.rs @@ -0,0 +1,334 @@ +#[doc = "Register `SCFG[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SCFG[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SLOT_CYCLE` reader - Maximum Number of Allowed Cycles for a Burst"] +pub struct SLOT_CYCLE_R(crate::FieldReader); +impl SLOT_CYCLE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SLOT_CYCLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SLOT_CYCLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLOT_CYCLE` writer - Maximum Number of Allowed Cycles for a Burst"] +pub struct SLOT_CYCLE_W<'a> { + w: &'a mut W, +} +impl<'a> SLOT_CYCLE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +#[doc = "Default Master Type\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DEFMSTR_TYPE_A { + #[doc = "0: No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst."] + NO_DEFAULT = 0, + #[doc = "1: Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave."] + LAST_DEFAULT = 1, + #[doc = "2: Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave."] + FIXED_DEFAULT = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DEFMSTR_TYPE_A) -> Self { + variant as _ + } +} +#[doc = "Field `DEFMSTR_TYPE` reader - Default Master Type"] +pub struct DEFMSTR_TYPE_R(crate::FieldReader); +impl DEFMSTR_TYPE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DEFMSTR_TYPE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(DEFMSTR_TYPE_A::NO_DEFAULT), + 1 => Some(DEFMSTR_TYPE_A::LAST_DEFAULT), + 2 => Some(DEFMSTR_TYPE_A::FIXED_DEFAULT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NO_DEFAULT`"] + #[inline(always)] + pub fn is_no_default(&self) -> bool { + **self == DEFMSTR_TYPE_A::NO_DEFAULT + } + #[doc = "Checks if the value of the field is `LAST_DEFAULT`"] + #[inline(always)] + pub fn is_last_default(&self) -> bool { + **self == DEFMSTR_TYPE_A::LAST_DEFAULT + } + #[doc = "Checks if the value of the field is `FIXED_DEFAULT`"] + #[inline(always)] + pub fn is_fixed_default(&self) -> bool { + **self == DEFMSTR_TYPE_A::FIXED_DEFAULT + } +} +impl core::ops::Deref for DEFMSTR_TYPE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DEFMSTR_TYPE` writer - Default Master Type"] +pub struct DEFMSTR_TYPE_W<'a> { + w: &'a mut W, +} +impl<'a> DEFMSTR_TYPE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DEFMSTR_TYPE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst."] + #[inline(always)] + pub fn no_default(self) -> &'a mut W { + self.variant(DEFMSTR_TYPE_A::NO_DEFAULT) + } + #[doc = "Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave."] + #[inline(always)] + pub fn last_default(self) -> &'a mut W { + self.variant(DEFMSTR_TYPE_A::LAST_DEFAULT) + } + #[doc = "Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave."] + #[inline(always)] + pub fn fixed_default(self) -> &'a mut W { + self.variant(DEFMSTR_TYPE_A::FIXED_DEFAULT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Field `FIXED_DEFMSTR` reader - Fixed Index of Default Master"] +pub struct FIXED_DEFMSTR_R(crate::FieldReader); +impl FIXED_DEFMSTR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FIXED_DEFMSTR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FIXED_DEFMSTR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FIXED_DEFMSTR` writer - Fixed Index of Default Master"] +pub struct FIXED_DEFMSTR_W<'a> { + w: &'a mut W, +} +impl<'a> FIXED_DEFMSTR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 18)) | ((value as u32 & 0x0f) << 18); + self.w + } +} +#[doc = "Arbitration Type\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ARBT_A { + #[doc = "0: Round-Robin Arbitration"] + ROUND_ROBIN = 0, + #[doc = "1: Fixed Priority Arbitration"] + FIXED_PRIORITY = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ARBT_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ARBT` reader - Arbitration Type"] +pub struct ARBT_R(crate::FieldReader); +impl ARBT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ARBT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ARBT_A { + match self.bits { + false => ARBT_A::ROUND_ROBIN, + true => ARBT_A::FIXED_PRIORITY, + } + } + #[doc = "Checks if the value of the field is `ROUND_ROBIN`"] + #[inline(always)] + pub fn is_round_robin(&self) -> bool { + **self == ARBT_A::ROUND_ROBIN + } + #[doc = "Checks if the value of the field is `FIXED_PRIORITY`"] + #[inline(always)] + pub fn is_fixed_priority(&self) -> bool { + **self == ARBT_A::FIXED_PRIORITY + } +} +impl core::ops::Deref for ARBT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ARBT` writer - Arbitration Type"] +pub struct ARBT_W<'a> { + w: &'a mut W, +} +impl<'a> ARBT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: ARBT_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Round-Robin Arbitration"] + #[inline(always)] + pub fn round_robin(self) -> &'a mut W { + self.variant(ARBT_A::ROUND_ROBIN) + } + #[doc = "Fixed Priority Arbitration"] + #[inline(always)] + pub fn fixed_priority(self) -> &'a mut W { + self.variant(ARBT_A::FIXED_PRIORITY) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Maximum Number of Allowed Cycles for a Burst"] + #[inline(always)] + pub fn slot_cycle(&self) -> SLOT_CYCLE_R { + SLOT_CYCLE_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 16:17 - Default Master Type"] + #[inline(always)] + pub fn defmstr_type(&self) -> DEFMSTR_TYPE_R { + DEFMSTR_TYPE_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bits 18:21 - Fixed Index of Default Master"] + #[inline(always)] + pub fn fixed_defmstr(&self) -> FIXED_DEFMSTR_R { + FIXED_DEFMSTR_R::new(((self.bits >> 18) & 0x0f) as u8) + } + #[doc = "Bit 24 - Arbitration Type"] + #[inline(always)] + pub fn arbt(&self) -> ARBT_R { + ARBT_R::new(((self.bits >> 24) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - Maximum Number of Allowed Cycles for a Burst"] + #[inline(always)] + pub fn slot_cycle(&mut self) -> SLOT_CYCLE_W { + SLOT_CYCLE_W { w: self } + } + #[doc = "Bits 16:17 - Default Master Type"] + #[inline(always)] + pub fn defmstr_type(&mut self) -> DEFMSTR_TYPE_W { + DEFMSTR_TYPE_W { w: self } + } + #[doc = "Bits 18:21 - Fixed Index of Default Master"] + #[inline(always)] + pub fn fixed_defmstr(&mut self) -> FIXED_DEFMSTR_W { + FIXED_DEFMSTR_W { w: self } + } + #[doc = "Bit 24 - Arbitration Type"] + #[inline(always)] + pub fn arbt(&mut self) -> ARBT_W { + ARBT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Slave Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [scfg](index.html) module"] +pub struct SCFG_SPEC; +impl crate::RegisterSpec for SCFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [scfg::R](R) reader structure"] +impl crate::Readable for SCFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [scfg::W](W) writer structure"] +impl crate::Writable for SCFG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SCFG[%s] +to value 0x10"] +impl crate::Resettable for SCFG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x10 + } +} diff --git a/pac/atsamc20n/src/hmatrixhs/sfr.rs b/pac/atsamc20n/src/hmatrixhs/sfr.rs new file mode 100644 index 000000000000..0a7e024f73c8 --- /dev/null +++ b/pac/atsamc20n/src/hmatrixhs/sfr.rs @@ -0,0 +1,104 @@ +#[doc = "Register `SFR[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SFR[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SFR` reader - Special Function Register"] +pub struct SFR_R(crate::FieldReader); +impl SFR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + SFR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SFR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SFR` writer - Special Function Register"] +pub struct SFR_W<'a> { + w: &'a mut W, +} +impl<'a> SFR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Special Function Register"] + #[inline(always)] + pub fn sfr(&self) -> SFR_R { + SFR_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Special Function Register"] + #[inline(always)] + pub fn sfr(&mut self) -> SFR_W { + SFR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Special Function\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sfr](index.html) module"] +pub struct SFR_SPEC; +impl crate::RegisterSpec for SFR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [sfr::R](R) reader structure"] +impl crate::Readable for SFR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [sfr::W](W) writer structure"] +impl crate::Writable for SFR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SFR[%s] +to value 0"] +impl crate::Resettable for SFR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/lib.rs b/pac/atsamc20n/src/lib.rs new file mode 100644 index 000000000000..567d4dc6a259 --- /dev/null +++ b/pac/atsamc20n/src/lib.rs @@ -0,0 +1,1659 @@ +#![doc = "Peripheral access API for ATSAMC20N microcontrollers (generated using svd2rust v0.20.0 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] +svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.20.0/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"] +#![deny(const_err)] +#![deny(dead_code)] +#![deny(improper_ctypes)] +#![deny(missing_docs)] +#![deny(no_mangle_generic_items)] +#![deny(non_shorthand_field_patterns)] +#![deny(overflowing_literals)] +#![deny(path_statements)] +#![deny(patterns_in_fns_without_body)] +#![deny(private_in_public)] +#![deny(unconditional_recursion)] +#![deny(unused_allocation)] +#![deny(unused_comparisons)] +#![deny(unused_parens)] +#![deny(while_true)] +#![allow(non_camel_case_types)] +#![allow(non_snake_case)] +#![allow(clippy::all)] +#![no_std] +use core::marker::PhantomData; +use core::ops::Deref; +#[doc = r"Number available in the NVIC for configuring priority"] +pub const NVIC_PRIO_BITS: u8 = 2; +#[cfg(feature = "rt")] +pub use self::Interrupt as interrupt; +pub use cortex_m::peripheral::Peripherals as CorePeripherals; +pub use cortex_m::peripheral::{CBP, CPUID, DCB, DWT, FPB, ITM, MPU, NVIC, SCB, SYST, TPIU}; +#[cfg(feature = "rt")] +pub use cortex_m_rt::interrupt; +#[allow(unused_imports)] +use generic::*; +#[doc = r"Common register and bit access and modify traits"] +pub mod generic; +#[cfg(feature = "rt")] +extern "C" { + fn WDT(); + fn RTC(); + fn EIC(); + fn FREQM(); + fn NVMCTRL(); + fn DMAC(); + fn EVSYS(); + fn SERCOM2(); + fn SERCOM3(); + fn SERCOM4(); + fn SERCOM5(); + fn TCC0(); + fn TCC1(); + fn TCC2(); + fn TC3(); + fn TC4(); + fn ADC0(); + fn AC(); + fn PTC(); +} +#[doc(hidden)] +pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, +} +#[cfg(feature = "rt")] +#[doc(hidden)] +#[link_section = ".vector_table.interrupts"] +#[no_mangle] +pub static __INTERRUPTS: [Vector; 31] = [ + Vector { _reserved: 0 }, + Vector { _handler: WDT }, + Vector { _handler: RTC }, + Vector { _handler: EIC }, + Vector { _handler: FREQM }, + Vector { _reserved: 0 }, + Vector { _handler: NVMCTRL }, + Vector { _handler: DMAC }, + Vector { _handler: EVSYS }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SERCOM2 }, + Vector { _handler: SERCOM3 }, + Vector { _handler: SERCOM4 }, + Vector { _handler: SERCOM5 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TCC0 }, + Vector { _handler: TCC1 }, + Vector { _handler: TCC2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TC3 }, + Vector { _handler: TC4 }, + Vector { _handler: ADC0 }, + Vector { _reserved: 0 }, + Vector { _handler: AC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: PTC }, +]; +#[doc = r"Enumeration of all the interrupts."] +#[derive(Copy, Clone, Debug, PartialEq, Eq)] +#[repr(u16)] +pub enum Interrupt { + #[doc = "1 - WDT"] + WDT = 1, + #[doc = "2 - RTC"] + RTC = 2, + #[doc = "3 - EIC"] + EIC = 3, + #[doc = "4 - FREQM"] + FREQM = 4, + #[doc = "6 - NVMCTRL"] + NVMCTRL = 6, + #[doc = "7 - DMAC"] + DMAC = 7, + #[doc = "8 - EVSYS"] + EVSYS = 8, + #[doc = "11 - SERCOM2"] + SERCOM2 = 11, + #[doc = "12 - SERCOM3"] + SERCOM3 = 12, + #[doc = "13 - SERCOM4"] + SERCOM4 = 13, + #[doc = "14 - SERCOM5"] + SERCOM5 = 14, + #[doc = "17 - TCC0"] + TCC0 = 17, + #[doc = "18 - TCC1"] + TCC1 = 18, + #[doc = "19 - TCC2"] + TCC2 = 19, + #[doc = "23 - TC3"] + TC3 = 23, + #[doc = "24 - TC4"] + TC4 = 24, + #[doc = "25 - ADC0"] + ADC0 = 25, + #[doc = "27 - AC"] + AC = 27, + #[doc = "30 - PTC"] + PTC = 30, +} +unsafe impl cortex_m::interrupt::InterruptNumber for Interrupt { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } +} +#[doc = "Analog Comparators"] +pub struct AC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for AC {} +impl AC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const ac::RegisterBlock = 0x4200_5000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const ac::RegisterBlock { + Self::PTR + } +} +impl Deref for AC { + type Target = ac::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for AC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AC").finish() + } +} +#[doc = "Analog Comparators"] +pub mod ac; +#[doc = "Analog Digital Converter"] +pub struct ADC0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for ADC0 {} +impl ADC0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const adc0::RegisterBlock = 0x4200_4400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const adc0::RegisterBlock { + Self::PTR + } +} +impl Deref for ADC0 { + type Target = adc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for ADC0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ADC0").finish() + } +} +#[doc = "Analog Digital Converter"] +pub mod adc0; +#[doc = "Configurable Custom Logic"] +pub struct CCL { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for CCL {} +impl CCL { + #[doc = r"Pointer to the register block"] + pub const PTR: *const ccl::RegisterBlock = 0x4200_5c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const ccl::RegisterBlock { + Self::PTR + } +} +impl Deref for CCL { + type Target = ccl::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for CCL { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CCL").finish() + } +} +#[doc = "Configurable Custom Logic"] +pub mod ccl; +#[doc = "Divide and Square Root Accelerator"] +pub struct DIVAS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for DIVAS {} +impl DIVAS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const divas::RegisterBlock = 0x4800_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const divas::RegisterBlock { + Self::PTR + } +} +impl Deref for DIVAS { + type Target = divas::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for DIVAS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DIVAS").finish() + } +} +#[doc = "Divide and Square Root Accelerator"] +pub mod divas; +#[doc = "Direct Memory Access Controller"] +pub struct DMAC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for DMAC {} +impl DMAC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const dmac::RegisterBlock = 0x4100_6000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const dmac::RegisterBlock { + Self::PTR + } +} +impl Deref for DMAC { + type Target = dmac::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for DMAC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DMAC").finish() + } +} +#[doc = "Direct Memory Access Controller"] +pub mod dmac; +#[doc = "Device Service Unit"] +pub struct DSU { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for DSU {} +impl DSU { + #[doc = r"Pointer to the register block"] + pub const PTR: *const dsu::RegisterBlock = 0x4100_2000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const dsu::RegisterBlock { + Self::PTR + } +} +impl Deref for DSU { + type Target = dsu::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for DSU { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DSU").finish() + } +} +#[doc = "Device Service Unit"] +pub mod dsu; +#[doc = "External Interrupt Controller"] +pub struct EIC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for EIC {} +impl EIC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const eic::RegisterBlock = 0x4000_2800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const eic::RegisterBlock { + Self::PTR + } +} +impl Deref for EIC { + type Target = eic::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for EIC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EIC").finish() + } +} +#[doc = "External Interrupt Controller"] +pub mod eic; +#[doc = "Event System Interface"] +pub struct EVSYS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for EVSYS {} +impl EVSYS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const evsys::RegisterBlock = 0x4200_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const evsys::RegisterBlock { + Self::PTR + } +} +impl Deref for EVSYS { + type Target = evsys::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for EVSYS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EVSYS").finish() + } +} +#[doc = "Event System Interface"] +pub mod evsys; +#[doc = "Frequency Meter"] +pub struct FREQM { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for FREQM {} +impl FREQM { + #[doc = r"Pointer to the register block"] + pub const PTR: *const freqm::RegisterBlock = 0x4000_2c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const freqm::RegisterBlock { + Self::PTR + } +} +impl Deref for FREQM { + type Target = freqm::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for FREQM { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FREQM").finish() + } +} +#[doc = "Frequency Meter"] +pub mod freqm; +#[doc = "Generic Clock Generator"] +pub struct GCLK { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for GCLK {} +impl GCLK { + #[doc = r"Pointer to the register block"] + pub const PTR: *const gclk::RegisterBlock = 0x4000_1c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const gclk::RegisterBlock { + Self::PTR + } +} +impl Deref for GCLK { + type Target = gclk::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for GCLK { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GCLK").finish() + } +} +#[doc = "Generic Clock Generator"] +pub mod gclk; +#[doc = "HSB Matrix"] +pub struct HMATRIXHS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for HMATRIXHS {} +impl HMATRIXHS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const hmatrixhs::RegisterBlock = 0x4100_a000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const hmatrixhs::RegisterBlock { + Self::PTR + } +} +impl Deref for HMATRIXHS { + type Target = hmatrixhs::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for HMATRIXHS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HMATRIXHS").finish() + } +} +#[doc = "HSB Matrix"] +pub mod hmatrixhs; +#[doc = "Main Clock"] +pub struct MCLK { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for MCLK {} +impl MCLK { + #[doc = r"Pointer to the register block"] + pub const PTR: *const mclk::RegisterBlock = 0x4000_0800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const mclk::RegisterBlock { + Self::PTR + } +} +impl Deref for MCLK { + type Target = mclk::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for MCLK { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MCLK").finish() + } +} +#[doc = "Main Clock"] +pub mod mclk; +#[doc = "Cortex-M0+ Micro-Trace Buffer"] +pub struct MTB { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for MTB {} +impl MTB { + #[doc = r"Pointer to the register block"] + pub const PTR: *const mtb::RegisterBlock = 0x4100_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const mtb::RegisterBlock { + Self::PTR + } +} +impl Deref for MTB { + type Target = mtb::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for MTB { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MTB").finish() + } +} +#[doc = "Cortex-M0+ Micro-Trace Buffer"] +pub mod mtb; +#[doc = "Non-Volatile Memory Controller"] +pub struct NVMCTRL { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for NVMCTRL {} +impl NVMCTRL { + #[doc = r"Pointer to the register block"] + pub const PTR: *const nvmctrl::RegisterBlock = 0x4100_4000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const nvmctrl::RegisterBlock { + Self::PTR + } +} +impl Deref for NVMCTRL { + type Target = nvmctrl::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for NVMCTRL { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("NVMCTRL").finish() + } +} +#[doc = "Non-Volatile Memory Controller"] +pub mod nvmctrl; +#[doc = "Oscillators Control"] +pub struct OSCCTRL { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for OSCCTRL {} +impl OSCCTRL { + #[doc = r"Pointer to the register block"] + pub const PTR: *const oscctrl::RegisterBlock = 0x4000_1000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const oscctrl::RegisterBlock { + Self::PTR + } +} +impl Deref for OSCCTRL { + type Target = oscctrl::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for OSCCTRL { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OSCCTRL").finish() + } +} +#[doc = "Oscillators Control"] +pub mod oscctrl; +#[doc = "32k Oscillators Control"] +pub struct OSC32KCTRL { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for OSC32KCTRL {} +impl OSC32KCTRL { + #[doc = r"Pointer to the register block"] + pub const PTR: *const osc32kctrl::RegisterBlock = 0x4000_1400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const osc32kctrl::RegisterBlock { + Self::PTR + } +} +impl Deref for OSC32KCTRL { + type Target = osc32kctrl::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for OSC32KCTRL { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OSC32KCTRL").finish() + } +} +#[doc = "32k Oscillators Control"] +pub mod osc32kctrl; +#[doc = "Peripheral Access Controller"] +pub struct PAC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PAC {} +impl PAC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const pac::RegisterBlock = 0x4000_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const pac::RegisterBlock { + Self::PTR + } +} +impl Deref for PAC { + type Target = pac::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PAC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PAC").finish() + } +} +#[doc = "Peripheral Access Controller"] +pub mod pac; +#[doc = "Power Manager"] +pub struct PM { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PM {} +impl PM { + #[doc = r"Pointer to the register block"] + pub const PTR: *const pm::RegisterBlock = 0x4000_0400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const pm::RegisterBlock { + Self::PTR + } +} +impl Deref for PM { + type Target = pm::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PM { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PM").finish() + } +} +#[doc = "Power Manager"] +pub mod pm; +#[doc = "Port Module"] +pub struct PORT { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PORT {} +impl PORT { + #[doc = r"Pointer to the register block"] + pub const PTR: *const port::RegisterBlock = 0x4100_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const port::RegisterBlock { + Self::PTR + } +} +impl Deref for PORT { + type Target = port::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PORT { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PORT").finish() + } +} +#[doc = "Port Module"] +pub mod port; +#[doc = "Port Module"] +pub struct PORT_IOBUS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PORT_IOBUS {} +impl PORT_IOBUS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const port::RegisterBlock = 0x6000_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const port::RegisterBlock { + Self::PTR + } +} +impl Deref for PORT_IOBUS { + type Target = port::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PORT_IOBUS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PORT_IOBUS").finish() + } +} +#[doc = "Port Module"] +pub use port as port_iobus; +#[doc = "Reset Controller"] +pub struct RSTC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for RSTC {} +impl RSTC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const rstc::RegisterBlock = 0x4000_0c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const rstc::RegisterBlock { + Self::PTR + } +} +impl Deref for RSTC { + type Target = rstc::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for RSTC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RSTC").finish() + } +} +#[doc = "Reset Controller"] +pub mod rstc; +#[doc = "Real-Time Counter"] +pub struct RTC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for RTC {} +impl RTC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const rtc::RegisterBlock = 0x4000_2400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const rtc::RegisterBlock { + Self::PTR + } +} +impl Deref for RTC { + type Target = rtc::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for RTC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RTC").finish() + } +} +#[doc = "Real-Time Counter"] +pub mod rtc; +#[doc = "Serial Communication Interface"] +pub struct SERCOM0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SERCOM0 {} +impl SERCOM0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sercom0::RegisterBlock = 0x4200_0400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sercom0::RegisterBlock { + Self::PTR + } +} +impl Deref for SERCOM0 { + type Target = sercom0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SERCOM0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SERCOM0").finish() + } +} +#[doc = "Serial Communication Interface"] +pub mod sercom0; +#[doc = "Serial Communication Interface"] +pub struct SERCOM1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SERCOM1 {} +impl SERCOM1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sercom0::RegisterBlock = 0x4200_0800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sercom0::RegisterBlock { + Self::PTR + } +} +impl Deref for SERCOM1 { + type Target = sercom0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SERCOM1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SERCOM1").finish() + } +} +#[doc = "Serial Communication Interface"] +pub use sercom0 as sercom1; +#[doc = "Serial Communication Interface"] +pub struct SERCOM2 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SERCOM2 {} +impl SERCOM2 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sercom0::RegisterBlock = 0x4200_0c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sercom0::RegisterBlock { + Self::PTR + } +} +impl Deref for SERCOM2 { + type Target = sercom0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SERCOM2 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SERCOM2").finish() + } +} +#[doc = "Serial Communication Interface"] +pub use sercom0 as sercom2; +#[doc = "Serial Communication Interface"] +pub struct SERCOM3 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SERCOM3 {} +impl SERCOM3 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sercom0::RegisterBlock = 0x4200_1000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sercom0::RegisterBlock { + Self::PTR + } +} +impl Deref for SERCOM3 { + type Target = sercom0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SERCOM3 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SERCOM3").finish() + } +} +#[doc = "Serial Communication Interface"] +pub use sercom0 as sercom3; +#[doc = "Serial Communication Interface"] +pub struct SERCOM4 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SERCOM4 {} +impl SERCOM4 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sercom0::RegisterBlock = 0x4200_1400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sercom0::RegisterBlock { + Self::PTR + } +} +impl Deref for SERCOM4 { + type Target = sercom0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SERCOM4 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SERCOM4").finish() + } +} +#[doc = "Serial Communication Interface"] +pub use sercom0 as sercom4; +#[doc = "Serial Communication Interface"] +pub struct SERCOM5 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SERCOM5 {} +impl SERCOM5 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sercom0::RegisterBlock = 0x4200_1800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sercom0::RegisterBlock { + Self::PTR + } +} +impl Deref for SERCOM5 { + type Target = sercom0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SERCOM5 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SERCOM5").finish() + } +} +#[doc = "Serial Communication Interface"] +pub use sercom0 as sercom5; +#[doc = "Serial Communication Interface"] +pub struct SERCOM6 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SERCOM6 {} +impl SERCOM6 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sercom0::RegisterBlock = 0x4300_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sercom0::RegisterBlock { + Self::PTR + } +} +impl Deref for SERCOM6 { + type Target = sercom0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SERCOM6 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SERCOM6").finish() + } +} +#[doc = "Serial Communication Interface"] +pub use sercom0 as sercom6; +#[doc = "Serial Communication Interface"] +pub struct SERCOM7 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SERCOM7 {} +impl SERCOM7 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sercom0::RegisterBlock = 0x4300_0400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sercom0::RegisterBlock { + Self::PTR + } +} +impl Deref for SERCOM7 { + type Target = sercom0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SERCOM7 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SERCOM7").finish() + } +} +#[doc = "Serial Communication Interface"] +pub use sercom0 as sercom7; +#[doc = "Supply Controller"] +pub struct SUPC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SUPC {} +impl SUPC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const supc::RegisterBlock = 0x4000_1800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const supc::RegisterBlock { + Self::PTR + } +} +impl Deref for SUPC { + type Target = supc::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SUPC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SUPC").finish() + } +} +#[doc = "Supply Controller"] +pub mod supc; +#[doc = "Basic Timer Counter"] +pub struct TC0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TC0 {} +impl TC0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tc0::RegisterBlock = 0x4200_3000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tc0::RegisterBlock { + Self::PTR + } +} +impl Deref for TC0 { + type Target = tc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TC0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TC0").finish() + } +} +#[doc = "Basic Timer Counter"] +pub mod tc0; +#[doc = "Basic Timer Counter"] +pub struct TC1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TC1 {} +impl TC1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tc0::RegisterBlock = 0x4200_3400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tc0::RegisterBlock { + Self::PTR + } +} +impl Deref for TC1 { + type Target = tc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TC1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TC1").finish() + } +} +#[doc = "Basic Timer Counter"] +pub use tc0 as tc1; +#[doc = "Basic Timer Counter"] +pub struct TC2 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TC2 {} +impl TC2 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tc0::RegisterBlock = 0x4200_3800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tc0::RegisterBlock { + Self::PTR + } +} +impl Deref for TC2 { + type Target = tc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TC2 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TC2").finish() + } +} +#[doc = "Basic Timer Counter"] +pub use tc0 as tc2; +#[doc = "Basic Timer Counter"] +pub struct TC3 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TC3 {} +impl TC3 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tc0::RegisterBlock = 0x4200_3c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tc0::RegisterBlock { + Self::PTR + } +} +impl Deref for TC3 { + type Target = tc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TC3 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TC3").finish() + } +} +#[doc = "Basic Timer Counter"] +pub use tc0 as tc3; +#[doc = "Basic Timer Counter"] +pub struct TC4 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TC4 {} +impl TC4 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tc0::RegisterBlock = 0x4200_4000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tc0::RegisterBlock { + Self::PTR + } +} +impl Deref for TC4 { + type Target = tc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TC4 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TC4").finish() + } +} +#[doc = "Basic Timer Counter"] +pub use tc0 as tc4; +#[doc = "Basic Timer Counter"] +pub struct TC5 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TC5 {} +impl TC5 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tc0::RegisterBlock = 0x4300_0800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tc0::RegisterBlock { + Self::PTR + } +} +impl Deref for TC5 { + type Target = tc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TC5 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TC5").finish() + } +} +#[doc = "Basic Timer Counter"] +pub use tc0 as tc5; +#[doc = "Basic Timer Counter"] +pub struct TC6 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TC6 {} +impl TC6 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tc0::RegisterBlock = 0x4300_0c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tc0::RegisterBlock { + Self::PTR + } +} +impl Deref for TC6 { + type Target = tc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TC6 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TC6").finish() + } +} +#[doc = "Basic Timer Counter"] +pub use tc0 as tc6; +#[doc = "Basic Timer Counter"] +pub struct TC7 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TC7 {} +impl TC7 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tc0::RegisterBlock = 0x4300_1000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tc0::RegisterBlock { + Self::PTR + } +} +impl Deref for TC7 { + type Target = tc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TC7 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TC7").finish() + } +} +#[doc = "Basic Timer Counter"] +pub use tc0 as tc7; +#[doc = "Timer Counter Control"] +pub struct TCC0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TCC0 {} +impl TCC0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tcc0::RegisterBlock = 0x4200_2400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tcc0::RegisterBlock { + Self::PTR + } +} +impl Deref for TCC0 { + type Target = tcc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TCC0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TCC0").finish() + } +} +#[doc = "Timer Counter Control"] +pub mod tcc0; +#[doc = "Timer Counter Control"] +pub struct TCC1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TCC1 {} +impl TCC1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tcc0::RegisterBlock = 0x4200_2800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tcc0::RegisterBlock { + Self::PTR + } +} +impl Deref for TCC1 { + type Target = tcc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TCC1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TCC1").finish() + } +} +#[doc = "Timer Counter Control"] +pub use tcc0 as tcc1; +#[doc = "Timer Counter Control"] +pub struct TCC2 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TCC2 {} +impl TCC2 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tcc0::RegisterBlock = 0x4200_2c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tcc0::RegisterBlock { + Self::PTR + } +} +impl Deref for TCC2 { + type Target = tcc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TCC2 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TCC2").finish() + } +} +#[doc = "Timer Counter Control"] +pub use tcc0 as tcc2; +#[doc = "Watchdog Timer"] +pub struct WDT { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for WDT {} +impl WDT { + #[doc = r"Pointer to the register block"] + pub const PTR: *const wdt::RegisterBlock = 0x4000_2000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const wdt::RegisterBlock { + Self::PTR + } +} +impl Deref for WDT { + type Target = wdt::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for WDT { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("WDT").finish() + } +} +#[doc = "Watchdog Timer"] +pub mod wdt; +#[doc = "System timer"] +pub struct SYSTICK { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SYSTICK {} +impl SYSTICK { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sys_tick::RegisterBlock = 0xe000_e010 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sys_tick::RegisterBlock { + Self::PTR + } +} +impl Deref for SYSTICK { + type Target = sys_tick::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SYSTICK { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SYSTICK").finish() + } +} +#[doc = "System timer"] +pub mod sys_tick; +#[doc = "System Control Registers"] +pub struct SYSTEMCONTROL { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SYSTEMCONTROL {} +impl SYSTEMCONTROL { + #[doc = r"Pointer to the register block"] + pub const PTR: *const system_control::RegisterBlock = 0xe000_e000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const system_control::RegisterBlock { + Self::PTR + } +} +impl Deref for SYSTEMCONTROL { + type Target = system_control::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SYSTEMCONTROL { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SYSTEMCONTROL").finish() + } +} +#[doc = "System Control Registers"] +pub mod system_control; +#[no_mangle] +static mut DEVICE_PERIPHERALS: bool = false; +#[doc = r"All the peripherals"] +#[allow(non_snake_case)] +pub struct Peripherals { + #[doc = "AC"] + pub AC: AC, + #[doc = "ADC0"] + pub ADC0: ADC0, + #[doc = "CCL"] + pub CCL: CCL, + #[doc = "DIVAS"] + pub DIVAS: DIVAS, + #[doc = "DMAC"] + pub DMAC: DMAC, + #[doc = "DSU"] + pub DSU: DSU, + #[doc = "EIC"] + pub EIC: EIC, + #[doc = "EVSYS"] + pub EVSYS: EVSYS, + #[doc = "FREQM"] + pub FREQM: FREQM, + #[doc = "GCLK"] + pub GCLK: GCLK, + #[doc = "HMATRIXHS"] + pub HMATRIXHS: HMATRIXHS, + #[doc = "MCLK"] + pub MCLK: MCLK, + #[doc = "MTB"] + pub MTB: MTB, + #[doc = "NVMCTRL"] + pub NVMCTRL: NVMCTRL, + #[doc = "OSCCTRL"] + pub OSCCTRL: OSCCTRL, + #[doc = "OSC32KCTRL"] + pub OSC32KCTRL: OSC32KCTRL, + #[doc = "PAC"] + pub PAC: PAC, + #[doc = "PM"] + pub PM: PM, + #[doc = "PORT"] + pub PORT: PORT, + #[doc = "PORT_IOBUS"] + pub PORT_IOBUS: PORT_IOBUS, + #[doc = "RSTC"] + pub RSTC: RSTC, + #[doc = "RTC"] + pub RTC: RTC, + #[doc = "SERCOM0"] + pub SERCOM0: SERCOM0, + #[doc = "SERCOM1"] + pub SERCOM1: SERCOM1, + #[doc = "SERCOM2"] + pub SERCOM2: SERCOM2, + #[doc = "SERCOM3"] + pub SERCOM3: SERCOM3, + #[doc = "SERCOM4"] + pub SERCOM4: SERCOM4, + #[doc = "SERCOM5"] + pub SERCOM5: SERCOM5, + #[doc = "SERCOM6"] + pub SERCOM6: SERCOM6, + #[doc = "SERCOM7"] + pub SERCOM7: SERCOM7, + #[doc = "SUPC"] + pub SUPC: SUPC, + #[doc = "TC0"] + pub TC0: TC0, + #[doc = "TC1"] + pub TC1: TC1, + #[doc = "TC2"] + pub TC2: TC2, + #[doc = "TC3"] + pub TC3: TC3, + #[doc = "TC4"] + pub TC4: TC4, + #[doc = "TC5"] + pub TC5: TC5, + #[doc = "TC6"] + pub TC6: TC6, + #[doc = "TC7"] + pub TC7: TC7, + #[doc = "TCC0"] + pub TCC0: TCC0, + #[doc = "TCC1"] + pub TCC1: TCC1, + #[doc = "TCC2"] + pub TCC2: TCC2, + #[doc = "WDT"] + pub WDT: WDT, + #[doc = "SYSTICK"] + pub SYSTICK: SYSTICK, + #[doc = "SYSTEMCONTROL"] + pub SYSTEMCONTROL: SYSTEMCONTROL, +} +impl Peripherals { + #[doc = r"Returns all the peripherals *once*"] + #[inline] + pub fn take() -> Option { + cortex_m::interrupt::free(|_| { + if unsafe { DEVICE_PERIPHERALS } { + None + } else { + Some(unsafe { Peripherals::steal() }) + } + }) + } + #[doc = r"Unchecked version of `Peripherals::take`"] + #[inline] + pub unsafe fn steal() -> Self { + DEVICE_PERIPHERALS = true; + Peripherals { + AC: AC { + _marker: PhantomData, + }, + ADC0: ADC0 { + _marker: PhantomData, + }, + CCL: CCL { + _marker: PhantomData, + }, + DIVAS: DIVAS { + _marker: PhantomData, + }, + DMAC: DMAC { + _marker: PhantomData, + }, + DSU: DSU { + _marker: PhantomData, + }, + EIC: EIC { + _marker: PhantomData, + }, + EVSYS: EVSYS { + _marker: PhantomData, + }, + FREQM: FREQM { + _marker: PhantomData, + }, + GCLK: GCLK { + _marker: PhantomData, + }, + HMATRIXHS: HMATRIXHS { + _marker: PhantomData, + }, + MCLK: MCLK { + _marker: PhantomData, + }, + MTB: MTB { + _marker: PhantomData, + }, + NVMCTRL: NVMCTRL { + _marker: PhantomData, + }, + OSCCTRL: OSCCTRL { + _marker: PhantomData, + }, + OSC32KCTRL: OSC32KCTRL { + _marker: PhantomData, + }, + PAC: PAC { + _marker: PhantomData, + }, + PM: PM { + _marker: PhantomData, + }, + PORT: PORT { + _marker: PhantomData, + }, + PORT_IOBUS: PORT_IOBUS { + _marker: PhantomData, + }, + RSTC: RSTC { + _marker: PhantomData, + }, + RTC: RTC { + _marker: PhantomData, + }, + SERCOM0: SERCOM0 { + _marker: PhantomData, + }, + SERCOM1: SERCOM1 { + _marker: PhantomData, + }, + SERCOM2: SERCOM2 { + _marker: PhantomData, + }, + SERCOM3: SERCOM3 { + _marker: PhantomData, + }, + SERCOM4: SERCOM4 { + _marker: PhantomData, + }, + SERCOM5: SERCOM5 { + _marker: PhantomData, + }, + SERCOM6: SERCOM6 { + _marker: PhantomData, + }, + SERCOM7: SERCOM7 { + _marker: PhantomData, + }, + SUPC: SUPC { + _marker: PhantomData, + }, + TC0: TC0 { + _marker: PhantomData, + }, + TC1: TC1 { + _marker: PhantomData, + }, + TC2: TC2 { + _marker: PhantomData, + }, + TC3: TC3 { + _marker: PhantomData, + }, + TC4: TC4 { + _marker: PhantomData, + }, + TC5: TC5 { + _marker: PhantomData, + }, + TC6: TC6 { + _marker: PhantomData, + }, + TC7: TC7 { + _marker: PhantomData, + }, + TCC0: TCC0 { + _marker: PhantomData, + }, + TCC1: TCC1 { + _marker: PhantomData, + }, + TCC2: TCC2 { + _marker: PhantomData, + }, + WDT: WDT { + _marker: PhantomData, + }, + SYSTICK: SYSTICK { + _marker: PhantomData, + }, + SYSTEMCONTROL: SYSTEMCONTROL { + _marker: PhantomData, + }, + } + } +} diff --git a/pac/atsamc20n/src/mclk.rs b/pac/atsamc20n/src/mclk.rs new file mode 100644 index 000000000000..2713af2692b7 --- /dev/null +++ b/pac/atsamc20n/src/mclk.rs @@ -0,0 +1,60 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved0: [u8; 0x01], + #[doc = "0x01 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x02 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x03 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x04 - CPU Clock Division"] + pub cpudiv: crate::Reg, + _reserved4: [u8; 0x0b], + #[doc = "0x10 - AHB Mask"] + pub ahbmask: crate::Reg, + #[doc = "0x14 - APBA Mask"] + pub apbamask: crate::Reg, + #[doc = "0x18 - APBB Mask"] + pub apbbmask: crate::Reg, + #[doc = "0x1c - APBC Mask"] + pub apbcmask: crate::Reg, + #[doc = "0x20 - APBD Mask"] + pub apbdmask: crate::Reg, +} +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "CPUDIV register accessor: an alias for `Reg`"] +pub type CPUDIV = crate::Reg; +#[doc = "CPU Clock Division"] +pub mod cpudiv; +#[doc = "AHBMASK register accessor: an alias for `Reg`"] +pub type AHBMASK = crate::Reg; +#[doc = "AHB Mask"] +pub mod ahbmask; +#[doc = "APBAMASK register accessor: an alias for `Reg`"] +pub type APBAMASK = crate::Reg; +#[doc = "APBA Mask"] +pub mod apbamask; +#[doc = "APBBMASK register accessor: an alias for `Reg`"] +pub type APBBMASK = crate::Reg; +#[doc = "APBB Mask"] +pub mod apbbmask; +#[doc = "APBCMASK register accessor: an alias for `Reg`"] +pub type APBCMASK = crate::Reg; +#[doc = "APBC Mask"] +pub mod apbcmask; +#[doc = "APBDMASK register accessor: an alias for `Reg`"] +pub type APBDMASK = crate::Reg; +#[doc = "APBD Mask"] +pub mod apbdmask; diff --git a/pac/atsamc20n/src/mclk/ahbmask.rs b/pac/atsamc20n/src/mclk/ahbmask.rs new file mode 100644 index 000000000000..f3630d0ec305 --- /dev/null +++ b/pac/atsamc20n/src/mclk/ahbmask.rs @@ -0,0 +1,630 @@ +#[doc = "Register `AHBMASK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `AHBMASK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `HPB0_` reader - HPB0 AHB Clock Mask"] +pub struct HPB0__R(crate::FieldReader); +impl HPB0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HPB0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HPB0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HPB0_` writer - HPB0 AHB Clock Mask"] +pub struct HPB0__W<'a> { + w: &'a mut W, +} +impl<'a> HPB0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `HPB1_` reader - HPB1 AHB Clock Mask"] +pub struct HPB1__R(crate::FieldReader); +impl HPB1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HPB1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HPB1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HPB1_` writer - HPB1 AHB Clock Mask"] +pub struct HPB1__W<'a> { + w: &'a mut W, +} +impl<'a> HPB1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `HPB2_` reader - HPB2 AHB Clock Mask"] +pub struct HPB2__R(crate::FieldReader); +impl HPB2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HPB2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HPB2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HPB2_` writer - HPB2 AHB Clock Mask"] +pub struct HPB2__W<'a> { + w: &'a mut W, +} +impl<'a> HPB2__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `DSU_` reader - DSU AHB Clock Mask"] +pub struct DSU__R(crate::FieldReader); +impl DSU__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DSU__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DSU__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DSU_` writer - DSU AHB Clock Mask"] +pub struct DSU__W<'a> { + w: &'a mut W, +} +impl<'a> DSU__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `HMATRIXHS_` reader - HMATRIXHS AHB Clock Mask"] +pub struct HMATRIXHS__R(crate::FieldReader); +impl HMATRIXHS__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HMATRIXHS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HMATRIXHS__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HMATRIXHS_` writer - HMATRIXHS AHB Clock Mask"] +pub struct HMATRIXHS__W<'a> { + w: &'a mut W, +} +impl<'a> HMATRIXHS__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `NVMCTRL_` reader - NVMCTRL AHB Clock Mask"] +pub struct NVMCTRL__R(crate::FieldReader); +impl NVMCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NVMCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NVMCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NVMCTRL_` writer - NVMCTRL AHB Clock Mask"] +pub struct NVMCTRL__W<'a> { + w: &'a mut W, +} +impl<'a> NVMCTRL__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `HSRAM_` reader - HSRAM AHB Clock Mask"] +pub struct HSRAM__R(crate::FieldReader); +impl HSRAM__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HSRAM__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HSRAM__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HSRAM_` writer - HSRAM AHB Clock Mask"] +pub struct HSRAM__W<'a> { + w: &'a mut W, +} +impl<'a> HSRAM__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `DMAC_` reader - DMAC AHB Clock Mask"] +pub struct DMAC__R(crate::FieldReader); +impl DMAC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DMAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DMAC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DMAC_` writer - DMAC AHB Clock Mask"] +pub struct DMAC__W<'a> { + w: &'a mut W, +} +impl<'a> DMAC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `PAC_` reader - PAC AHB Clock Mask"] +pub struct PAC__R(crate::FieldReader); +impl PAC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PAC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PAC_` writer - PAC AHB Clock Mask"] +pub struct PAC__W<'a> { + w: &'a mut W, +} +impl<'a> PAC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `NVMCTRL_PICACHU_` reader - NVMCTRL_PICACHU AHB Clock Mask"] +pub struct NVMCTRL_PICACHU__R(crate::FieldReader); +impl NVMCTRL_PICACHU__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NVMCTRL_PICACHU__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NVMCTRL_PICACHU__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NVMCTRL_PICACHU_` writer - NVMCTRL_PICACHU AHB Clock Mask"] +pub struct NVMCTRL_PICACHU__W<'a> { + w: &'a mut W, +} +impl<'a> NVMCTRL_PICACHU__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `DIVAS_` reader - DIVAS AHB Clock Mask"] +pub struct DIVAS__R(crate::FieldReader); +impl DIVAS__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIVAS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIVAS__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIVAS_` writer - DIVAS AHB Clock Mask"] +pub struct DIVAS__W<'a> { + w: &'a mut W, +} +impl<'a> DIVAS__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `HPB3_` reader - HPB3 AHB Clock Mask"] +pub struct HPB3__R(crate::FieldReader); +impl HPB3__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HPB3__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HPB3__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HPB3_` writer - HPB3 AHB Clock Mask"] +pub struct HPB3__W<'a> { + w: &'a mut W, +} +impl<'a> HPB3__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +impl R { + #[doc = "Bit 0 - HPB0 AHB Clock Mask"] + #[inline(always)] + pub fn hpb0_(&self) -> HPB0__R { + HPB0__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - HPB1 AHB Clock Mask"] + #[inline(always)] + pub fn hpb1_(&self) -> HPB1__R { + HPB1__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - HPB2 AHB Clock Mask"] + #[inline(always)] + pub fn hpb2_(&self) -> HPB2__R { + HPB2__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - DSU AHB Clock Mask"] + #[inline(always)] + pub fn dsu_(&self) -> DSU__R { + DSU__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - HMATRIXHS AHB Clock Mask"] + #[inline(always)] + pub fn hmatrixhs_(&self) -> HMATRIXHS__R { + HMATRIXHS__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - NVMCTRL AHB Clock Mask"] + #[inline(always)] + pub fn nvmctrl_(&self) -> NVMCTRL__R { + NVMCTRL__R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - HSRAM AHB Clock Mask"] + #[inline(always)] + pub fn hsram_(&self) -> HSRAM__R { + HSRAM__R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - DMAC AHB Clock Mask"] + #[inline(always)] + pub fn dmac_(&self) -> DMAC__R { + DMAC__R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 10 - PAC AHB Clock Mask"] + #[inline(always)] + pub fn pac_(&self) -> PAC__R { + PAC__R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - NVMCTRL_PICACHU AHB Clock Mask"] + #[inline(always)] + pub fn nvmctrl_picachu_(&self) -> NVMCTRL_PICACHU__R { + NVMCTRL_PICACHU__R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - DIVAS AHB Clock Mask"] + #[inline(always)] + pub fn divas_(&self) -> DIVAS__R { + DIVAS__R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - HPB3 AHB Clock Mask"] + #[inline(always)] + pub fn hpb3_(&self) -> HPB3__R { + HPB3__R::new(((self.bits >> 13) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - HPB0 AHB Clock Mask"] + #[inline(always)] + pub fn hpb0_(&mut self) -> HPB0__W { + HPB0__W { w: self } + } + #[doc = "Bit 1 - HPB1 AHB Clock Mask"] + #[inline(always)] + pub fn hpb1_(&mut self) -> HPB1__W { + HPB1__W { w: self } + } + #[doc = "Bit 2 - HPB2 AHB Clock Mask"] + #[inline(always)] + pub fn hpb2_(&mut self) -> HPB2__W { + HPB2__W { w: self } + } + #[doc = "Bit 3 - DSU AHB Clock Mask"] + #[inline(always)] + pub fn dsu_(&mut self) -> DSU__W { + DSU__W { w: self } + } + #[doc = "Bit 4 - HMATRIXHS AHB Clock Mask"] + #[inline(always)] + pub fn hmatrixhs_(&mut self) -> HMATRIXHS__W { + HMATRIXHS__W { w: self } + } + #[doc = "Bit 5 - NVMCTRL AHB Clock Mask"] + #[inline(always)] + pub fn nvmctrl_(&mut self) -> NVMCTRL__W { + NVMCTRL__W { w: self } + } + #[doc = "Bit 6 - HSRAM AHB Clock Mask"] + #[inline(always)] + pub fn hsram_(&mut self) -> HSRAM__W { + HSRAM__W { w: self } + } + #[doc = "Bit 7 - DMAC AHB Clock Mask"] + #[inline(always)] + pub fn dmac_(&mut self) -> DMAC__W { + DMAC__W { w: self } + } + #[doc = "Bit 10 - PAC AHB Clock Mask"] + #[inline(always)] + pub fn pac_(&mut self) -> PAC__W { + PAC__W { w: self } + } + #[doc = "Bit 11 - NVMCTRL_PICACHU AHB Clock Mask"] + #[inline(always)] + pub fn nvmctrl_picachu_(&mut self) -> NVMCTRL_PICACHU__W { + NVMCTRL_PICACHU__W { w: self } + } + #[doc = "Bit 12 - DIVAS AHB Clock Mask"] + #[inline(always)] + pub fn divas_(&mut self) -> DIVAS__W { + DIVAS__W { w: self } + } + #[doc = "Bit 13 - HPB3 AHB Clock Mask"] + #[inline(always)] + pub fn hpb3_(&mut self) -> HPB3__W { + HPB3__W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "AHB Mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ahbmask](index.html) module"] +pub struct AHBMASK_SPEC; +impl crate::RegisterSpec for AHBMASK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ahbmask::R](R) reader structure"] +impl crate::Readable for AHBMASK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ahbmask::W](W) writer structure"] +impl crate::Writable for AHBMASK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets AHBMASK to value 0x3cff"] +impl crate::Resettable for AHBMASK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x3cff + } +} diff --git a/pac/atsamc20n/src/mclk/apbamask.rs b/pac/atsamc20n/src/mclk/apbamask.rs new file mode 100644 index 000000000000..3e095e73a158 --- /dev/null +++ b/pac/atsamc20n/src/mclk/apbamask.rs @@ -0,0 +1,630 @@ +#[doc = "Register `APBAMASK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `APBAMASK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PAC_` reader - PAC APB Clock Enable"] +pub struct PAC__R(crate::FieldReader); +impl PAC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PAC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PAC_` writer - PAC APB Clock Enable"] +pub struct PAC__W<'a> { + w: &'a mut W, +} +impl<'a> PAC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `PM_` reader - PM APB Clock Enable"] +pub struct PM__R(crate::FieldReader); +impl PM__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PM__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PM__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PM_` writer - PM APB Clock Enable"] +pub struct PM__W<'a> { + w: &'a mut W, +} +impl<'a> PM__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MCLK_` reader - MCLK APB Clock Enable"] +pub struct MCLK__R(crate::FieldReader); +impl MCLK__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCLK__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCLK__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCLK_` writer - MCLK APB Clock Enable"] +pub struct MCLK__W<'a> { + w: &'a mut W, +} +impl<'a> MCLK__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RSTC_` reader - RSTC APB Clock Enable"] +pub struct RSTC__R(crate::FieldReader); +impl RSTC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RSTC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RSTC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RSTC_` writer - RSTC APB Clock Enable"] +pub struct RSTC__W<'a> { + w: &'a mut W, +} +impl<'a> RSTC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `OSCCTRL_` reader - OSCCTRL APB Clock Enable"] +pub struct OSCCTRL__R(crate::FieldReader); +impl OSCCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSCCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSCCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSCCTRL_` writer - OSCCTRL APB Clock Enable"] +pub struct OSCCTRL__W<'a> { + w: &'a mut W, +} +impl<'a> OSCCTRL__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `OSC32KCTRL_` reader - OSC32KCTRL APB Clock Enable"] +pub struct OSC32KCTRL__R(crate::FieldReader); +impl OSC32KCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC32KCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC32KCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC32KCTRL_` writer - OSC32KCTRL APB Clock Enable"] +pub struct OSC32KCTRL__W<'a> { + w: &'a mut W, +} +impl<'a> OSC32KCTRL__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `SUPC_` reader - SUPC APB Clock Enable"] +pub struct SUPC__R(crate::FieldReader); +impl SUPC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SUPC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SUPC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SUPC_` writer - SUPC APB Clock Enable"] +pub struct SUPC__W<'a> { + w: &'a mut W, +} +impl<'a> SUPC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `GCLK_` reader - GCLK APB Clock Enable"] +pub struct GCLK__R(crate::FieldReader); +impl GCLK__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GCLK__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GCLK__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GCLK_` writer - GCLK APB Clock Enable"] +pub struct GCLK__W<'a> { + w: &'a mut W, +} +impl<'a> GCLK__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `WDT_` reader - WDT APB Clock Enable"] +pub struct WDT__R(crate::FieldReader); +impl WDT__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WDT__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WDT__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WDT_` writer - WDT APB Clock Enable"] +pub struct WDT__W<'a> { + w: &'a mut W, +} +impl<'a> WDT__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `RTC_` reader - RTC APB Clock Enable"] +pub struct RTC__R(crate::FieldReader); +impl RTC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RTC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RTC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RTC_` writer - RTC APB Clock Enable"] +pub struct RTC__W<'a> { + w: &'a mut W, +} +impl<'a> RTC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `EIC_` reader - EIC APB Clock Enable"] +pub struct EIC__R(crate::FieldReader); +impl EIC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EIC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EIC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EIC_` writer - EIC APB Clock Enable"] +pub struct EIC__W<'a> { + w: &'a mut W, +} +impl<'a> EIC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `FREQM_` reader - FREQM APB Clock Enable"] +pub struct FREQM__R(crate::FieldReader); +impl FREQM__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FREQM__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FREQM__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FREQM_` writer - FREQM APB Clock Enable"] +pub struct FREQM__W<'a> { + w: &'a mut W, +} +impl<'a> FREQM__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +impl R { + #[doc = "Bit 0 - PAC APB Clock Enable"] + #[inline(always)] + pub fn pac_(&self) -> PAC__R { + PAC__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - PM APB Clock Enable"] + #[inline(always)] + pub fn pm_(&self) -> PM__R { + PM__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - MCLK APB Clock Enable"] + #[inline(always)] + pub fn mclk_(&self) -> MCLK__R { + MCLK__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - RSTC APB Clock Enable"] + #[inline(always)] + pub fn rstc_(&self) -> RSTC__R { + RSTC__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - OSCCTRL APB Clock Enable"] + #[inline(always)] + pub fn oscctrl_(&self) -> OSCCTRL__R { + OSCCTRL__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - OSC32KCTRL APB Clock Enable"] + #[inline(always)] + pub fn osc32kctrl_(&self) -> OSC32KCTRL__R { + OSC32KCTRL__R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - SUPC APB Clock Enable"] + #[inline(always)] + pub fn supc_(&self) -> SUPC__R { + SUPC__R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - GCLK APB Clock Enable"] + #[inline(always)] + pub fn gclk_(&self) -> GCLK__R { + GCLK__R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - WDT APB Clock Enable"] + #[inline(always)] + pub fn wdt_(&self) -> WDT__R { + WDT__R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - RTC APB Clock Enable"] + #[inline(always)] + pub fn rtc_(&self) -> RTC__R { + RTC__R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - EIC APB Clock Enable"] + #[inline(always)] + pub fn eic_(&self) -> EIC__R { + EIC__R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - FREQM APB Clock Enable"] + #[inline(always)] + pub fn freqm_(&self) -> FREQM__R { + FREQM__R::new(((self.bits >> 11) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - PAC APB Clock Enable"] + #[inline(always)] + pub fn pac_(&mut self) -> PAC__W { + PAC__W { w: self } + } + #[doc = "Bit 1 - PM APB Clock Enable"] + #[inline(always)] + pub fn pm_(&mut self) -> PM__W { + PM__W { w: self } + } + #[doc = "Bit 2 - MCLK APB Clock Enable"] + #[inline(always)] + pub fn mclk_(&mut self) -> MCLK__W { + MCLK__W { w: self } + } + #[doc = "Bit 3 - RSTC APB Clock Enable"] + #[inline(always)] + pub fn rstc_(&mut self) -> RSTC__W { + RSTC__W { w: self } + } + #[doc = "Bit 4 - OSCCTRL APB Clock Enable"] + #[inline(always)] + pub fn oscctrl_(&mut self) -> OSCCTRL__W { + OSCCTRL__W { w: self } + } + #[doc = "Bit 5 - OSC32KCTRL APB Clock Enable"] + #[inline(always)] + pub fn osc32kctrl_(&mut self) -> OSC32KCTRL__W { + OSC32KCTRL__W { w: self } + } + #[doc = "Bit 6 - SUPC APB Clock Enable"] + #[inline(always)] + pub fn supc_(&mut self) -> SUPC__W { + SUPC__W { w: self } + } + #[doc = "Bit 7 - GCLK APB Clock Enable"] + #[inline(always)] + pub fn gclk_(&mut self) -> GCLK__W { + GCLK__W { w: self } + } + #[doc = "Bit 8 - WDT APB Clock Enable"] + #[inline(always)] + pub fn wdt_(&mut self) -> WDT__W { + WDT__W { w: self } + } + #[doc = "Bit 9 - RTC APB Clock Enable"] + #[inline(always)] + pub fn rtc_(&mut self) -> RTC__W { + RTC__W { w: self } + } + #[doc = "Bit 10 - EIC APB Clock Enable"] + #[inline(always)] + pub fn eic_(&mut self) -> EIC__W { + EIC__W { w: self } + } + #[doc = "Bit 11 - FREQM APB Clock Enable"] + #[inline(always)] + pub fn freqm_(&mut self) -> FREQM__W { + FREQM__W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "APBA Mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [apbamask](index.html) module"] +pub struct APBAMASK_SPEC; +impl crate::RegisterSpec for APBAMASK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [apbamask::R](R) reader structure"] +impl crate::Readable for APBAMASK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [apbamask::W](W) writer structure"] +impl crate::Writable for APBAMASK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets APBAMASK to value 0x0fff"] +impl crate::Resettable for APBAMASK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0fff + } +} diff --git a/pac/atsamc20n/src/mclk/apbbmask.rs b/pac/atsamc20n/src/mclk/apbbmask.rs new file mode 100644 index 000000000000..e1ec6b1f2323 --- /dev/null +++ b/pac/atsamc20n/src/mclk/apbbmask.rs @@ -0,0 +1,254 @@ +#[doc = "Register `APBBMASK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `APBBMASK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PORT_` reader - PORT APB Clock Enable"] +pub struct PORT__R(crate::FieldReader); +impl PORT__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PORT__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PORT__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PORT_` writer - PORT APB Clock Enable"] +pub struct PORT__W<'a> { + w: &'a mut W, +} +impl<'a> PORT__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `DSU_` reader - DSU APB Clock Enable"] +pub struct DSU__R(crate::FieldReader); +impl DSU__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DSU__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DSU__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DSU_` writer - DSU APB Clock Enable"] +pub struct DSU__W<'a> { + w: &'a mut W, +} +impl<'a> DSU__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `NVMCTRL_` reader - NVMCTRL APB Clock Enable"] +pub struct NVMCTRL__R(crate::FieldReader); +impl NVMCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NVMCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NVMCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NVMCTRL_` writer - NVMCTRL APB Clock Enable"] +pub struct NVMCTRL__W<'a> { + w: &'a mut W, +} +impl<'a> NVMCTRL__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `HMATRIXHS_` reader - HMATRIXHS APB Clock Enable"] +pub struct HMATRIXHS__R(crate::FieldReader); +impl HMATRIXHS__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HMATRIXHS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HMATRIXHS__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HMATRIXHS_` writer - HMATRIXHS APB Clock Enable"] +pub struct HMATRIXHS__W<'a> { + w: &'a mut W, +} +impl<'a> HMATRIXHS__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - PORT APB Clock Enable"] + #[inline(always)] + pub fn port_(&self) -> PORT__R { + PORT__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - DSU APB Clock Enable"] + #[inline(always)] + pub fn dsu_(&self) -> DSU__R { + DSU__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - NVMCTRL APB Clock Enable"] + #[inline(always)] + pub fn nvmctrl_(&self) -> NVMCTRL__R { + NVMCTRL__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 5 - HMATRIXHS APB Clock Enable"] + #[inline(always)] + pub fn hmatrixhs_(&self) -> HMATRIXHS__R { + HMATRIXHS__R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - PORT APB Clock Enable"] + #[inline(always)] + pub fn port_(&mut self) -> PORT__W { + PORT__W { w: self } + } + #[doc = "Bit 1 - DSU APB Clock Enable"] + #[inline(always)] + pub fn dsu_(&mut self) -> DSU__W { + DSU__W { w: self } + } + #[doc = "Bit 2 - NVMCTRL APB Clock Enable"] + #[inline(always)] + pub fn nvmctrl_(&mut self) -> NVMCTRL__W { + NVMCTRL__W { w: self } + } + #[doc = "Bit 5 - HMATRIXHS APB Clock Enable"] + #[inline(always)] + pub fn hmatrixhs_(&mut self) -> HMATRIXHS__W { + HMATRIXHS__W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "APBB Mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [apbbmask](index.html) module"] +pub struct APBBMASK_SPEC; +impl crate::RegisterSpec for APBBMASK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [apbbmask::R](R) reader structure"] +impl crate::Readable for APBBMASK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [apbbmask::W](W) writer structure"] +impl crate::Writable for APBBMASK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets APBBMASK to value 0x07"] +impl crate::Resettable for APBBMASK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x07 + } +} diff --git a/pac/atsamc20n/src/mclk/apbcmask.rs b/pac/atsamc20n/src/mclk/apbcmask.rs new file mode 100644 index 000000000000..ad35986e6e16 --- /dev/null +++ b/pac/atsamc20n/src/mclk/apbcmask.rs @@ -0,0 +1,959 @@ +#[doc = "Register `APBCMASK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `APBCMASK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVSYS_` reader - EVSYS APB Clock Enable"] +pub struct EVSYS__R(crate::FieldReader); +impl EVSYS__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVSYS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVSYS__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVSYS_` writer - EVSYS APB Clock Enable"] +pub struct EVSYS__W<'a> { + w: &'a mut W, +} +impl<'a> EVSYS__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `SERCOM0_` reader - SERCOM0 APB Clock Enable"] +pub struct SERCOM0__R(crate::FieldReader); +impl SERCOM0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM0_` writer - SERCOM0 APB Clock Enable"] +pub struct SERCOM0__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SERCOM1_` reader - SERCOM1 APB Clock Enable"] +pub struct SERCOM1__R(crate::FieldReader); +impl SERCOM1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM1_` writer - SERCOM1 APB Clock Enable"] +pub struct SERCOM1__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SERCOM2_` reader - SERCOM2 APB Clock Enable"] +pub struct SERCOM2__R(crate::FieldReader); +impl SERCOM2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM2_` writer - SERCOM2 APB Clock Enable"] +pub struct SERCOM2__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM2__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `SERCOM3_` reader - SERCOM3 APB Clock Enable"] +pub struct SERCOM3__R(crate::FieldReader); +impl SERCOM3__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM3__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM3__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM3_` writer - SERCOM3 APB Clock Enable"] +pub struct SERCOM3__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM3__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `SERCOM4_` reader - SERCOM4 APB Clock Enable"] +pub struct SERCOM4__R(crate::FieldReader); +impl SERCOM4__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM4__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM4__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM4_` writer - SERCOM4 APB Clock Enable"] +pub struct SERCOM4__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM4__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `SERCOM5_` reader - SERCOM5 APB Clock Enable"] +pub struct SERCOM5__R(crate::FieldReader); +impl SERCOM5__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM5__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM5__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM5_` writer - SERCOM5 APB Clock Enable"] +pub struct SERCOM5__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM5__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `TCC0_` reader - TCC0 APB Clock Enable"] +pub struct TCC0__R(crate::FieldReader); +impl TCC0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCC0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCC0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCC0_` writer - TCC0 APB Clock Enable"] +pub struct TCC0__W<'a> { + w: &'a mut W, +} +impl<'a> TCC0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `TCC1_` reader - TCC1 APB Clock Enable"] +pub struct TCC1__R(crate::FieldReader); +impl TCC1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCC1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCC1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCC1_` writer - TCC1 APB Clock Enable"] +pub struct TCC1__W<'a> { + w: &'a mut W, +} +impl<'a> TCC1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `TCC2_` reader - TCC2 APB Clock Enable"] +pub struct TCC2__R(crate::FieldReader); +impl TCC2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCC2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCC2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCC2_` writer - TCC2 APB Clock Enable"] +pub struct TCC2__W<'a> { + w: &'a mut W, +} +impl<'a> TCC2__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `TC0_` reader - TC0 APB Clock Enable"] +pub struct TC0__R(crate::FieldReader); +impl TC0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC0_` writer - TC0 APB Clock Enable"] +pub struct TC0__W<'a> { + w: &'a mut W, +} +impl<'a> TC0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `TC1_` reader - TC1 APB Clock Enable"] +pub struct TC1__R(crate::FieldReader); +impl TC1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC1_` writer - TC1 APB Clock Enable"] +pub struct TC1__W<'a> { + w: &'a mut W, +} +impl<'a> TC1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `TC2_` reader - TC2 APB Clock Enable"] +pub struct TC2__R(crate::FieldReader); +impl TC2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC2_` writer - TC2 APB Clock Enable"] +pub struct TC2__W<'a> { + w: &'a mut W, +} +impl<'a> TC2__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `TC3_` reader - TC3 APB Clock Enable"] +pub struct TC3__R(crate::FieldReader); +impl TC3__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC3__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC3__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC3_` writer - TC3 APB Clock Enable"] +pub struct TC3__W<'a> { + w: &'a mut W, +} +impl<'a> TC3__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `TC4_` reader - TC4 APB Clock Enable"] +pub struct TC4__R(crate::FieldReader); +impl TC4__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC4__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC4__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC4_` writer - TC4 APB Clock Enable"] +pub struct TC4__W<'a> { + w: &'a mut W, +} +impl<'a> TC4__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `ADC0_` reader - ADC0 APB Clock Enable"] +pub struct ADC0__R(crate::FieldReader); +impl ADC0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ADC0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADC0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADC0_` writer - ADC0 APB Clock Enable"] +pub struct ADC0__W<'a> { + w: &'a mut W, +} +impl<'a> ADC0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `AC_` reader - AC APB Clock Enable"] +pub struct AC__R(crate::FieldReader); +impl AC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AC_` writer - AC APB Clock Enable"] +pub struct AC__W<'a> { + w: &'a mut W, +} +impl<'a> AC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `PTC_` reader - PTC APB Clock Enable"] +pub struct PTC__R(crate::FieldReader); +impl PTC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PTC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PTC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PTC_` writer - PTC APB Clock Enable"] +pub struct PTC__W<'a> { + w: &'a mut W, +} +impl<'a> PTC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `CCL_` reader - CCL APB Clock Enable"] +pub struct CCL__R(crate::FieldReader); +impl CCL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCL_` writer - CCL APB Clock Enable"] +pub struct CCL__W<'a> { + w: &'a mut W, +} +impl<'a> CCL__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +impl R { + #[doc = "Bit 0 - EVSYS APB Clock Enable"] + #[inline(always)] + pub fn evsys_(&self) -> EVSYS__R { + EVSYS__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM0 APB Clock Enable"] + #[inline(always)] + pub fn sercom0_(&self) -> SERCOM0__R { + SERCOM0__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - SERCOM1 APB Clock Enable"] + #[inline(always)] + pub fn sercom1_(&self) -> SERCOM1__R { + SERCOM1__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - SERCOM2 APB Clock Enable"] + #[inline(always)] + pub fn sercom2_(&self) -> SERCOM2__R { + SERCOM2__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - SERCOM3 APB Clock Enable"] + #[inline(always)] + pub fn sercom3_(&self) -> SERCOM3__R { + SERCOM3__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - SERCOM4 APB Clock Enable"] + #[inline(always)] + pub fn sercom4_(&self) -> SERCOM4__R { + SERCOM4__R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - SERCOM5 APB Clock Enable"] + #[inline(always)] + pub fn sercom5_(&self) -> SERCOM5__R { + SERCOM5__R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 9 - TCC0 APB Clock Enable"] + #[inline(always)] + pub fn tcc0_(&self) -> TCC0__R { + TCC0__R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - TCC1 APB Clock Enable"] + #[inline(always)] + pub fn tcc1_(&self) -> TCC1__R { + TCC1__R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - TCC2 APB Clock Enable"] + #[inline(always)] + pub fn tcc2_(&self) -> TCC2__R { + TCC2__R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - TC0 APB Clock Enable"] + #[inline(always)] + pub fn tc0_(&self) -> TC0__R { + TC0__R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - TC1 APB Clock Enable"] + #[inline(always)] + pub fn tc1_(&self) -> TC1__R { + TC1__R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - TC2 APB Clock Enable"] + #[inline(always)] + pub fn tc2_(&self) -> TC2__R { + TC2__R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - TC3 APB Clock Enable"] + #[inline(always)] + pub fn tc3_(&self) -> TC3__R { + TC3__R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - TC4 APB Clock Enable"] + #[inline(always)] + pub fn tc4_(&self) -> TC4__R { + TC4__R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - ADC0 APB Clock Enable"] + #[inline(always)] + pub fn adc0_(&self) -> ADC0__R { + ADC0__R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 20 - AC APB Clock Enable"] + #[inline(always)] + pub fn ac_(&self) -> AC__R { + AC__R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 22 - PTC APB Clock Enable"] + #[inline(always)] + pub fn ptc_(&self) -> PTC__R { + PTC__R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - CCL APB Clock Enable"] + #[inline(always)] + pub fn ccl_(&self) -> CCL__R { + CCL__R::new(((self.bits >> 23) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - EVSYS APB Clock Enable"] + #[inline(always)] + pub fn evsys_(&mut self) -> EVSYS__W { + EVSYS__W { w: self } + } + #[doc = "Bit 1 - SERCOM0 APB Clock Enable"] + #[inline(always)] + pub fn sercom0_(&mut self) -> SERCOM0__W { + SERCOM0__W { w: self } + } + #[doc = "Bit 2 - SERCOM1 APB Clock Enable"] + #[inline(always)] + pub fn sercom1_(&mut self) -> SERCOM1__W { + SERCOM1__W { w: self } + } + #[doc = "Bit 3 - SERCOM2 APB Clock Enable"] + #[inline(always)] + pub fn sercom2_(&mut self) -> SERCOM2__W { + SERCOM2__W { w: self } + } + #[doc = "Bit 4 - SERCOM3 APB Clock Enable"] + #[inline(always)] + pub fn sercom3_(&mut self) -> SERCOM3__W { + SERCOM3__W { w: self } + } + #[doc = "Bit 5 - SERCOM4 APB Clock Enable"] + #[inline(always)] + pub fn sercom4_(&mut self) -> SERCOM4__W { + SERCOM4__W { w: self } + } + #[doc = "Bit 6 - SERCOM5 APB Clock Enable"] + #[inline(always)] + pub fn sercom5_(&mut self) -> SERCOM5__W { + SERCOM5__W { w: self } + } + #[doc = "Bit 9 - TCC0 APB Clock Enable"] + #[inline(always)] + pub fn tcc0_(&mut self) -> TCC0__W { + TCC0__W { w: self } + } + #[doc = "Bit 10 - TCC1 APB Clock Enable"] + #[inline(always)] + pub fn tcc1_(&mut self) -> TCC1__W { + TCC1__W { w: self } + } + #[doc = "Bit 11 - TCC2 APB Clock Enable"] + #[inline(always)] + pub fn tcc2_(&mut self) -> TCC2__W { + TCC2__W { w: self } + } + #[doc = "Bit 12 - TC0 APB Clock Enable"] + #[inline(always)] + pub fn tc0_(&mut self) -> TC0__W { + TC0__W { w: self } + } + #[doc = "Bit 13 - TC1 APB Clock Enable"] + #[inline(always)] + pub fn tc1_(&mut self) -> TC1__W { + TC1__W { w: self } + } + #[doc = "Bit 14 - TC2 APB Clock Enable"] + #[inline(always)] + pub fn tc2_(&mut self) -> TC2__W { + TC2__W { w: self } + } + #[doc = "Bit 15 - TC3 APB Clock Enable"] + #[inline(always)] + pub fn tc3_(&mut self) -> TC3__W { + TC3__W { w: self } + } + #[doc = "Bit 16 - TC4 APB Clock Enable"] + #[inline(always)] + pub fn tc4_(&mut self) -> TC4__W { + TC4__W { w: self } + } + #[doc = "Bit 17 - ADC0 APB Clock Enable"] + #[inline(always)] + pub fn adc0_(&mut self) -> ADC0__W { + ADC0__W { w: self } + } + #[doc = "Bit 20 - AC APB Clock Enable"] + #[inline(always)] + pub fn ac_(&mut self) -> AC__W { + AC__W { w: self } + } + #[doc = "Bit 22 - PTC APB Clock Enable"] + #[inline(always)] + pub fn ptc_(&mut self) -> PTC__W { + PTC__W { w: self } + } + #[doc = "Bit 23 - CCL APB Clock Enable"] + #[inline(always)] + pub fn ccl_(&mut self) -> CCL__W { + CCL__W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "APBC Mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [apbcmask](index.html) module"] +pub struct APBCMASK_SPEC; +impl crate::RegisterSpec for APBCMASK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [apbcmask::R](R) reader structure"] +impl crate::Readable for APBCMASK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [apbcmask::W](W) writer structure"] +impl crate::Writable for APBCMASK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets APBCMASK to value 0"] +impl crate::Resettable for APBCMASK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/mclk/apbdmask.rs b/pac/atsamc20n/src/mclk/apbdmask.rs new file mode 100644 index 000000000000..64592ea4d041 --- /dev/null +++ b/pac/atsamc20n/src/mclk/apbdmask.rs @@ -0,0 +1,301 @@ +#[doc = "Register `APBDMASK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `APBDMASK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SERCOM6_` reader - SERCOM6 APB Clock Enable"] +pub struct SERCOM6__R(crate::FieldReader); +impl SERCOM6__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM6__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM6__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM6_` writer - SERCOM6 APB Clock Enable"] +pub struct SERCOM6__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM6__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `SERCOM7_` reader - SERCOM7 APB Clock Enable"] +pub struct SERCOM7__R(crate::FieldReader); +impl SERCOM7__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM7__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM7__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM7_` writer - SERCOM7 APB Clock Enable"] +pub struct SERCOM7__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM7__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `TC5_` reader - TC5 APB Clock Enable"] +pub struct TC5__R(crate::FieldReader); +impl TC5__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC5__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC5__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC5_` writer - TC5 APB Clock Enable"] +pub struct TC5__W<'a> { + w: &'a mut W, +} +impl<'a> TC5__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `TC6_` reader - TC6 APB Clock Enable"] +pub struct TC6__R(crate::FieldReader); +impl TC6__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC6__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC6__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC6_` writer - TC6 APB Clock Enable"] +pub struct TC6__W<'a> { + w: &'a mut W, +} +impl<'a> TC6__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `TC7_` reader - TC7 APB Clock Enable"] +pub struct TC7__R(crate::FieldReader); +impl TC7__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC7__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC7__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC7_` writer - TC7 APB Clock Enable"] +pub struct TC7__W<'a> { + w: &'a mut W, +} +impl<'a> TC7__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +impl R { + #[doc = "Bit 0 - SERCOM6 APB Clock Enable"] + #[inline(always)] + pub fn sercom6_(&self) -> SERCOM6__R { + SERCOM6__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM7 APB Clock Enable"] + #[inline(always)] + pub fn sercom7_(&self) -> SERCOM7__R { + SERCOM7__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - TC5 APB Clock Enable"] + #[inline(always)] + pub fn tc5_(&self) -> TC5__R { + TC5__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - TC6 APB Clock Enable"] + #[inline(always)] + pub fn tc6_(&self) -> TC6__R { + TC6__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - TC7 APB Clock Enable"] + #[inline(always)] + pub fn tc7_(&self) -> TC7__R { + TC7__R::new(((self.bits >> 4) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - SERCOM6 APB Clock Enable"] + #[inline(always)] + pub fn sercom6_(&mut self) -> SERCOM6__W { + SERCOM6__W { w: self } + } + #[doc = "Bit 1 - SERCOM7 APB Clock Enable"] + #[inline(always)] + pub fn sercom7_(&mut self) -> SERCOM7__W { + SERCOM7__W { w: self } + } + #[doc = "Bit 2 - TC5 APB Clock Enable"] + #[inline(always)] + pub fn tc5_(&mut self) -> TC5__W { + TC5__W { w: self } + } + #[doc = "Bit 3 - TC6 APB Clock Enable"] + #[inline(always)] + pub fn tc6_(&mut self) -> TC6__W { + TC6__W { w: self } + } + #[doc = "Bit 4 - TC7 APB Clock Enable"] + #[inline(always)] + pub fn tc7_(&mut self) -> TC7__W { + TC7__W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "APBD Mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [apbdmask](index.html) module"] +pub struct APBDMASK_SPEC; +impl crate::RegisterSpec for APBDMASK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [apbdmask::R](R) reader structure"] +impl crate::Readable for APBDMASK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [apbdmask::W](W) writer structure"] +impl crate::Writable for APBDMASK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets APBDMASK to value 0"] +impl crate::Resettable for APBDMASK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/mclk/cpudiv.rs b/pac/atsamc20n/src/mclk/cpudiv.rs new file mode 100644 index 000000000000..a21fdae21357 --- /dev/null +++ b/pac/atsamc20n/src/mclk/cpudiv.rs @@ -0,0 +1,230 @@ +#[doc = "Register `CPUDIV` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CPUDIV` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "CPU Clock Division Factor\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CPUDIV_A { + #[doc = "1: Divide by 1"] + DIV1 = 1, + #[doc = "2: Divide by 2"] + DIV2 = 2, + #[doc = "4: Divide by 4"] + DIV4 = 4, + #[doc = "8: Divide by 8"] + DIV8 = 8, + #[doc = "16: Divide by 16"] + DIV16 = 16, + #[doc = "32: Divide by 32"] + DIV32 = 32, + #[doc = "64: Divide by 64"] + DIV64 = 64, + #[doc = "128: Divide by 128"] + DIV128 = 128, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CPUDIV_A) -> Self { + variant as _ + } +} +#[doc = "Field `CPUDIV` reader - CPU Clock Division Factor"] +pub struct CPUDIV_R(crate::FieldReader); +impl CPUDIV_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CPUDIV_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 1 => Some(CPUDIV_A::DIV1), + 2 => Some(CPUDIV_A::DIV2), + 4 => Some(CPUDIV_A::DIV4), + 8 => Some(CPUDIV_A::DIV8), + 16 => Some(CPUDIV_A::DIV16), + 32 => Some(CPUDIV_A::DIV32), + 64 => Some(CPUDIV_A::DIV64), + 128 => Some(CPUDIV_A::DIV128), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == CPUDIV_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == CPUDIV_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == CPUDIV_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == CPUDIV_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == CPUDIV_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == CPUDIV_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == CPUDIV_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == CPUDIV_A::DIV128 + } +} +impl core::ops::Deref for CPUDIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPUDIV` writer - CPU Clock Division Factor"] +pub struct CPUDIV_W<'a> { + w: &'a mut W, +} +impl<'a> CPUDIV_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CPUDIV_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Divide by 1"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV1) + } + #[doc = "Divide by 2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV2) + } + #[doc = "Divide by 4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV4) + } + #[doc = "Divide by 8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV8) + } + #[doc = "Divide by 16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV16) + } + #[doc = "Divide by 32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV32) + } + #[doc = "Divide by 64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV64) + } + #[doc = "Divide by 128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV128) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - CPU Clock Division Factor"] + #[inline(always)] + pub fn cpudiv(&self) -> CPUDIV_R { + CPUDIV_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - CPU Clock Division Factor"] + #[inline(always)] + pub fn cpudiv(&mut self) -> CPUDIV_W { + CPUDIV_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CPU Clock Division\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cpudiv](index.html) module"] +pub struct CPUDIV_SPEC; +impl crate::RegisterSpec for CPUDIV_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [cpudiv::R](R) reader structure"] +impl crate::Readable for CPUDIV_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cpudiv::W](W) writer structure"] +impl crate::Writable for CPUDIV_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CPUDIV to value 0x01"] +impl crate::Resettable for CPUDIV_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pac/atsamc20n/src/mclk/intenclr.rs b/pac/atsamc20n/src/mclk/intenclr.rs new file mode 100644 index 000000000000..14feb632dbb7 --- /dev/null +++ b/pac/atsamc20n/src/mclk/intenclr.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CKRDY` reader - Clock Ready Interrupt Enable"] +pub struct CKRDY_R(crate::FieldReader); +impl CKRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CKRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CKRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CKRDY` writer - Clock Ready Interrupt Enable"] +pub struct CKRDY_W<'a> { + w: &'a mut W, +} +impl<'a> CKRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Clock Ready Interrupt Enable"] + #[inline(always)] + pub fn ckrdy(&self) -> CKRDY_R { + CKRDY_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Clock Ready Interrupt Enable"] + #[inline(always)] + pub fn ckrdy(&mut self) -> CKRDY_W { + CKRDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/mclk/intenset.rs b/pac/atsamc20n/src/mclk/intenset.rs new file mode 100644 index 000000000000..f01fcc316d93 --- /dev/null +++ b/pac/atsamc20n/src/mclk/intenset.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CKRDY` reader - Clock Ready Interrupt Enable"] +pub struct CKRDY_R(crate::FieldReader); +impl CKRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CKRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CKRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CKRDY` writer - Clock Ready Interrupt Enable"] +pub struct CKRDY_W<'a> { + w: &'a mut W, +} +impl<'a> CKRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Clock Ready Interrupt Enable"] + #[inline(always)] + pub fn ckrdy(&self) -> CKRDY_R { + CKRDY_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Clock Ready Interrupt Enable"] + #[inline(always)] + pub fn ckrdy(&mut self) -> CKRDY_W { + CKRDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/mclk/intflag.rs b/pac/atsamc20n/src/mclk/intflag.rs new file mode 100644 index 000000000000..cf421d4ac61a --- /dev/null +++ b/pac/atsamc20n/src/mclk/intflag.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CKRDY` reader - Clock Ready"] +pub struct CKRDY_R(crate::FieldReader); +impl CKRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CKRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CKRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CKRDY` writer - Clock Ready"] +pub struct CKRDY_W<'a> { + w: &'a mut W, +} +impl<'a> CKRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Clock Ready"] + #[inline(always)] + pub fn ckrdy(&self) -> CKRDY_R { + CKRDY_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Clock Ready"] + #[inline(always)] + pub fn ckrdy(&mut self) -> CKRDY_W { + CKRDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0x01"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pac/atsamc20n/src/mtb.rs b/pac/atsamc20n/src/mtb.rs new file mode 100644 index 000000000000..01be005c0fb9 --- /dev/null +++ b/pac/atsamc20n/src/mtb.rs @@ -0,0 +1,158 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - MTB Position"] + pub position: crate::Reg, + #[doc = "0x04 - MTB Master"] + pub master: crate::Reg, + #[doc = "0x08 - MTB Flow"] + pub flow: crate::Reg, + #[doc = "0x0c - MTB Base"] + pub base: crate::Reg, + _reserved4: [u8; 0x0ef0], + #[doc = "0xf00 - MTB Integration Mode Control"] + pub itctrl: crate::Reg, + _reserved5: [u8; 0x9c], + #[doc = "0xfa0 - MTB Claim Set"] + pub claimset: crate::Reg, + #[doc = "0xfa4 - MTB Claim Clear"] + pub claimclr: crate::Reg, + _reserved7: [u8; 0x08], + #[doc = "0xfb0 - MTB Lock Access"] + pub lockaccess: crate::Reg, + #[doc = "0xfb4 - MTB Lock Status"] + pub lockstatus: crate::Reg, + #[doc = "0xfb8 - MTB Authentication Status"] + pub authstatus: crate::Reg, + #[doc = "0xfbc - MTB Device Architecture"] + pub devarch: crate::Reg, + _reserved11: [u8; 0x08], + #[doc = "0xfc8 - MTB Device Configuration"] + pub devid: crate::Reg, + #[doc = "0xfcc - MTB Device Type"] + pub devtype: crate::Reg, + #[doc = "0xfd0 - Peripheral Identification 4"] + pub pid4: crate::Reg, + #[doc = "0xfd4 - Peripheral Identification 5"] + pub pid5: crate::Reg, + #[doc = "0xfd8 - Peripheral Identification 6"] + pub pid6: crate::Reg, + #[doc = "0xfdc - Peripheral Identification 7"] + pub pid7: crate::Reg, + #[doc = "0xfe0 - Peripheral Identification 0"] + pub pid0: crate::Reg, + #[doc = "0xfe4 - Peripheral Identification 1"] + pub pid1: crate::Reg, + #[doc = "0xfe8 - Peripheral Identification 2"] + pub pid2: crate::Reg, + #[doc = "0xfec - Peripheral Identification 3"] + pub pid3: crate::Reg, + #[doc = "0xff0 - Component Identification 0"] + pub cid0: crate::Reg, + #[doc = "0xff4 - Component Identification 1"] + pub cid1: crate::Reg, + #[doc = "0xff8 - Component Identification 2"] + pub cid2: crate::Reg, + #[doc = "0xffc - Component Identification 3"] + pub cid3: crate::Reg, +} +#[doc = "POSITION register accessor: an alias for `Reg`"] +pub type POSITION = crate::Reg; +#[doc = "MTB Position"] +pub mod position; +#[doc = "MASTER register accessor: an alias for `Reg`"] +pub type MASTER = crate::Reg; +#[doc = "MTB Master"] +pub mod master; +#[doc = "FLOW register accessor: an alias for `Reg`"] +pub type FLOW = crate::Reg; +#[doc = "MTB Flow"] +pub mod flow; +#[doc = "BASE register accessor: an alias for `Reg`"] +pub type BASE = crate::Reg; +#[doc = "MTB Base"] +pub mod base; +#[doc = "ITCTRL register accessor: an alias for `Reg`"] +pub type ITCTRL = crate::Reg; +#[doc = "MTB Integration Mode Control"] +pub mod itctrl; +#[doc = "CLAIMSET register accessor: an alias for `Reg`"] +pub type CLAIMSET = crate::Reg; +#[doc = "MTB Claim Set"] +pub mod claimset; +#[doc = "CLAIMCLR register accessor: an alias for `Reg`"] +pub type CLAIMCLR = crate::Reg; +#[doc = "MTB Claim Clear"] +pub mod claimclr; +#[doc = "LOCKACCESS register accessor: an alias for `Reg`"] +pub type LOCKACCESS = crate::Reg; +#[doc = "MTB Lock Access"] +pub mod lockaccess; +#[doc = "LOCKSTATUS register accessor: an alias for `Reg`"] +pub type LOCKSTATUS = crate::Reg; +#[doc = "MTB Lock Status"] +pub mod lockstatus; +#[doc = "AUTHSTATUS register accessor: an alias for `Reg`"] +pub type AUTHSTATUS = crate::Reg; +#[doc = "MTB Authentication Status"] +pub mod authstatus; +#[doc = "DEVARCH register accessor: an alias for `Reg`"] +pub type DEVARCH = crate::Reg; +#[doc = "MTB Device Architecture"] +pub mod devarch; +#[doc = "DEVID register accessor: an alias for `Reg`"] +pub type DEVID = crate::Reg; +#[doc = "MTB Device Configuration"] +pub mod devid; +#[doc = "DEVTYPE register accessor: an alias for `Reg`"] +pub type DEVTYPE = crate::Reg; +#[doc = "MTB Device Type"] +pub mod devtype; +#[doc = "PID4 register accessor: an alias for `Reg`"] +pub type PID4 = crate::Reg; +#[doc = "Peripheral Identification 4"] +pub mod pid4; +#[doc = "PID5 register accessor: an alias for `Reg`"] +pub type PID5 = crate::Reg; +#[doc = "Peripheral Identification 5"] +pub mod pid5; +#[doc = "PID6 register accessor: an alias for `Reg`"] +pub type PID6 = crate::Reg; +#[doc = "Peripheral Identification 6"] +pub mod pid6; +#[doc = "PID7 register accessor: an alias for `Reg`"] +pub type PID7 = crate::Reg; +#[doc = "Peripheral Identification 7"] +pub mod pid7; +#[doc = "PID0 register accessor: an alias for `Reg`"] +pub type PID0 = crate::Reg; +#[doc = "Peripheral Identification 0"] +pub mod pid0; +#[doc = "PID1 register accessor: an alias for `Reg`"] +pub type PID1 = crate::Reg; +#[doc = "Peripheral Identification 1"] +pub mod pid1; +#[doc = "PID2 register accessor: an alias for `Reg`"] +pub type PID2 = crate::Reg; +#[doc = "Peripheral Identification 2"] +pub mod pid2; +#[doc = "PID3 register accessor: an alias for `Reg`"] +pub type PID3 = crate::Reg; +#[doc = "Peripheral Identification 3"] +pub mod pid3; +#[doc = "CID0 register accessor: an alias for `Reg`"] +pub type CID0 = crate::Reg; +#[doc = "Component Identification 0"] +pub mod cid0; +#[doc = "CID1 register accessor: an alias for `Reg`"] +pub type CID1 = crate::Reg; +#[doc = "Component Identification 1"] +pub mod cid1; +#[doc = "CID2 register accessor: an alias for `Reg`"] +pub type CID2 = crate::Reg; +#[doc = "Component Identification 2"] +pub mod cid2; +#[doc = "CID3 register accessor: an alias for `Reg`"] +pub type CID3 = crate::Reg; +#[doc = "Component Identification 3"] +pub mod cid3; diff --git a/pac/atsamc20n/src/mtb/authstatus.rs b/pac/atsamc20n/src/mtb/authstatus.rs new file mode 100644 index 000000000000..6fe441e0554d --- /dev/null +++ b/pac/atsamc20n/src/mtb/authstatus.rs @@ -0,0 +1,31 @@ +#[doc = "Register `AUTHSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "MTB Authentication Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [authstatus](index.html) module"] +pub struct AUTHSTATUS_SPEC; +impl crate::RegisterSpec for AUTHSTATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [authstatus::R](R) reader structure"] +impl crate::Readable for AUTHSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets AUTHSTATUS to value 0"] +impl crate::Resettable for AUTHSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/mtb/base.rs b/pac/atsamc20n/src/mtb/base.rs new file mode 100644 index 000000000000..f59b5a97a398 --- /dev/null +++ b/pac/atsamc20n/src/mtb/base.rs @@ -0,0 +1,31 @@ +#[doc = "Register `BASE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "MTB Base\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [base](index.html) module"] +pub struct BASE_SPEC; +impl crate::RegisterSpec for BASE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [base::R](R) reader structure"] +impl crate::Readable for BASE_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets BASE to value 0"] +impl crate::Resettable for BASE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/mtb/cid0.rs b/pac/atsamc20n/src/mtb/cid0.rs new file mode 100644 index 000000000000..e03bd35fa470 --- /dev/null +++ b/pac/atsamc20n/src/mtb/cid0.rs @@ -0,0 +1,31 @@ +#[doc = "Register `CID0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Component Identification 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid0](index.html) module"] +pub struct CID0_SPEC; +impl crate::RegisterSpec for CID0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid0::R](R) reader structure"] +impl crate::Readable for CID0_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID0 to value 0"] +impl crate::Resettable for CID0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/mtb/cid1.rs b/pac/atsamc20n/src/mtb/cid1.rs new file mode 100644 index 000000000000..1cafc8e0fb9a --- /dev/null +++ b/pac/atsamc20n/src/mtb/cid1.rs @@ -0,0 +1,31 @@ +#[doc = "Register `CID1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Component Identification 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid1](index.html) module"] +pub struct CID1_SPEC; +impl crate::RegisterSpec for CID1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid1::R](R) reader structure"] +impl crate::Readable for CID1_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID1 to value 0"] +impl crate::Resettable for CID1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/mtb/cid2.rs b/pac/atsamc20n/src/mtb/cid2.rs new file mode 100644 index 000000000000..6a91e4e23206 --- /dev/null +++ b/pac/atsamc20n/src/mtb/cid2.rs @@ -0,0 +1,31 @@ +#[doc = "Register `CID2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Component Identification 2\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid2](index.html) module"] +pub struct CID2_SPEC; +impl crate::RegisterSpec for CID2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid2::R](R) reader structure"] +impl crate::Readable for CID2_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID2 to value 0"] +impl crate::Resettable for CID2_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/mtb/cid3.rs b/pac/atsamc20n/src/mtb/cid3.rs new file mode 100644 index 000000000000..726290f4ffed --- /dev/null +++ b/pac/atsamc20n/src/mtb/cid3.rs @@ -0,0 +1,31 @@ +#[doc = "Register `CID3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Component Identification 3\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid3](index.html) module"] +pub struct CID3_SPEC; +impl crate::RegisterSpec for CID3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid3::R](R) reader structure"] +impl crate::Readable for CID3_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID3 to value 0"] +impl crate::Resettable for CID3_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/mtb/claimclr.rs b/pac/atsamc20n/src/mtb/claimclr.rs new file mode 100644 index 000000000000..7d0fa5d487b2 --- /dev/null +++ b/pac/atsamc20n/src/mtb/claimclr.rs @@ -0,0 +1,64 @@ +#[doc = "Register `CLAIMCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CLAIMCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MTB Claim Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [claimclr](index.html) module"] +pub struct CLAIMCLR_SPEC; +impl crate::RegisterSpec for CLAIMCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [claimclr::R](R) reader structure"] +impl crate::Readable for CLAIMCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [claimclr::W](W) writer structure"] +impl crate::Writable for CLAIMCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CLAIMCLR to value 0"] +impl crate::Resettable for CLAIMCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/mtb/claimset.rs b/pac/atsamc20n/src/mtb/claimset.rs new file mode 100644 index 000000000000..d5e8ffaa4846 --- /dev/null +++ b/pac/atsamc20n/src/mtb/claimset.rs @@ -0,0 +1,64 @@ +#[doc = "Register `CLAIMSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CLAIMSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MTB Claim Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [claimset](index.html) module"] +pub struct CLAIMSET_SPEC; +impl crate::RegisterSpec for CLAIMSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [claimset::R](R) reader structure"] +impl crate::Readable for CLAIMSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [claimset::W](W) writer structure"] +impl crate::Writable for CLAIMSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CLAIMSET to value 0"] +impl crate::Resettable for CLAIMSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/mtb/devarch.rs b/pac/atsamc20n/src/mtb/devarch.rs new file mode 100644 index 000000000000..b79480753d5e --- /dev/null +++ b/pac/atsamc20n/src/mtb/devarch.rs @@ -0,0 +1,31 @@ +#[doc = "Register `DEVARCH` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "MTB Device Architecture\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [devarch](index.html) module"] +pub struct DEVARCH_SPEC; +impl crate::RegisterSpec for DEVARCH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [devarch::R](R) reader structure"] +impl crate::Readable for DEVARCH_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DEVARCH to value 0"] +impl crate::Resettable for DEVARCH_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/mtb/devid.rs b/pac/atsamc20n/src/mtb/devid.rs new file mode 100644 index 000000000000..21c15d952032 --- /dev/null +++ b/pac/atsamc20n/src/mtb/devid.rs @@ -0,0 +1,31 @@ +#[doc = "Register `DEVID` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "MTB Device Configuration\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [devid](index.html) module"] +pub struct DEVID_SPEC; +impl crate::RegisterSpec for DEVID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [devid::R](R) reader structure"] +impl crate::Readable for DEVID_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DEVID to value 0"] +impl crate::Resettable for DEVID_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/mtb/devtype.rs b/pac/atsamc20n/src/mtb/devtype.rs new file mode 100644 index 000000000000..c00d66b98a2f --- /dev/null +++ b/pac/atsamc20n/src/mtb/devtype.rs @@ -0,0 +1,31 @@ +#[doc = "Register `DEVTYPE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "MTB Device Type\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [devtype](index.html) module"] +pub struct DEVTYPE_SPEC; +impl crate::RegisterSpec for DEVTYPE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [devtype::R](R) reader structure"] +impl crate::Readable for DEVTYPE_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DEVTYPE to value 0"] +impl crate::Resettable for DEVTYPE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/mtb/flow.rs b/pac/atsamc20n/src/mtb/flow.rs new file mode 100644 index 000000000000..1b94efdb89b8 --- /dev/null +++ b/pac/atsamc20n/src/mtb/flow.rs @@ -0,0 +1,197 @@ +#[doc = "Register `FLOW` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FLOW` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `AUTOSTOP` reader - Auto Stop Tracing"] +pub struct AUTOSTOP_R(crate::FieldReader); +impl AUTOSTOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AUTOSTOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AUTOSTOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AUTOSTOP` writer - Auto Stop Tracing"] +pub struct AUTOSTOP_W<'a> { + w: &'a mut W, +} +impl<'a> AUTOSTOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `AUTOHALT` reader - Auto Halt Request"] +pub struct AUTOHALT_R(crate::FieldReader); +impl AUTOHALT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AUTOHALT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AUTOHALT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AUTOHALT` writer - Auto Halt Request"] +pub struct AUTOHALT_W<'a> { + w: &'a mut W, +} +impl<'a> AUTOHALT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WATERMARK` reader - Watermark value"] +pub struct WATERMARK_R(crate::FieldReader); +impl WATERMARK_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + WATERMARK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WATERMARK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WATERMARK` writer - Watermark value"] +pub struct WATERMARK_W<'a> { + w: &'a mut W, +} +impl<'a> WATERMARK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1fff_ffff << 3)) | ((value as u32 & 0x1fff_ffff) << 3); + self.w + } +} +impl R { + #[doc = "Bit 0 - Auto Stop Tracing"] + #[inline(always)] + pub fn autostop(&self) -> AUTOSTOP_R { + AUTOSTOP_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Auto Halt Request"] + #[inline(always)] + pub fn autohalt(&self) -> AUTOHALT_R { + AUTOHALT_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 3:31 - Watermark value"] + #[inline(always)] + pub fn watermark(&self) -> WATERMARK_R { + WATERMARK_R::new(((self.bits >> 3) & 0x1fff_ffff) as u32) + } +} +impl W { + #[doc = "Bit 0 - Auto Stop Tracing"] + #[inline(always)] + pub fn autostop(&mut self) -> AUTOSTOP_W { + AUTOSTOP_W { w: self } + } + #[doc = "Bit 1 - Auto Halt Request"] + #[inline(always)] + pub fn autohalt(&mut self) -> AUTOHALT_W { + AUTOHALT_W { w: self } + } + #[doc = "Bits 3:31 - Watermark value"] + #[inline(always)] + pub fn watermark(&mut self) -> WATERMARK_W { + WATERMARK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MTB Flow\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [flow](index.html) module"] +pub struct FLOW_SPEC; +impl crate::RegisterSpec for FLOW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [flow::R](R) reader structure"] +impl crate::Readable for FLOW_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [flow::W](W) writer structure"] +impl crate::Writable for FLOW_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets FLOW to value 0"] +impl crate::Resettable for FLOW_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/mtb/itctrl.rs b/pac/atsamc20n/src/mtb/itctrl.rs new file mode 100644 index 000000000000..a48364e0b062 --- /dev/null +++ b/pac/atsamc20n/src/mtb/itctrl.rs @@ -0,0 +1,64 @@ +#[doc = "Register `ITCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ITCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MTB Integration Mode Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [itctrl](index.html) module"] +pub struct ITCTRL_SPEC; +impl crate::RegisterSpec for ITCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [itctrl::R](R) reader structure"] +impl crate::Readable for ITCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [itctrl::W](W) writer structure"] +impl crate::Writable for ITCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ITCTRL to value 0"] +impl crate::Resettable for ITCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/mtb/lockaccess.rs b/pac/atsamc20n/src/mtb/lockaccess.rs new file mode 100644 index 000000000000..0400690beade --- /dev/null +++ b/pac/atsamc20n/src/mtb/lockaccess.rs @@ -0,0 +1,64 @@ +#[doc = "Register `LOCKACCESS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `LOCKACCESS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MTB Lock Access\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lockaccess](index.html) module"] +pub struct LOCKACCESS_SPEC; +impl crate::RegisterSpec for LOCKACCESS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [lockaccess::R](R) reader structure"] +impl crate::Readable for LOCKACCESS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [lockaccess::W](W) writer structure"] +impl crate::Writable for LOCKACCESS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets LOCKACCESS to value 0"] +impl crate::Resettable for LOCKACCESS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/mtb/lockstatus.rs b/pac/atsamc20n/src/mtb/lockstatus.rs new file mode 100644 index 000000000000..0c68410c6944 --- /dev/null +++ b/pac/atsamc20n/src/mtb/lockstatus.rs @@ -0,0 +1,31 @@ +#[doc = "Register `LOCKSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "MTB Lock Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lockstatus](index.html) module"] +pub struct LOCKSTATUS_SPEC; +impl crate::RegisterSpec for LOCKSTATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [lockstatus::R](R) reader structure"] +impl crate::Readable for LOCKSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets LOCKSTATUS to value 0"] +impl crate::Resettable for LOCKSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/mtb/master.rs b/pac/atsamc20n/src/mtb/master.rs new file mode 100644 index 000000000000..0190ca1ce909 --- /dev/null +++ b/pac/atsamc20n/src/mtb/master.rs @@ -0,0 +1,385 @@ +#[doc = "Register `MASTER` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MASTER` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MASK` reader - Maximum Value of the Trace Buffer in SRAM"] +pub struct MASK_R(crate::FieldReader); +impl MASK_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MASK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MASK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MASK` writer - Maximum Value of the Trace Buffer in SRAM"] +pub struct MASK_W<'a> { + w: &'a mut W, +} +impl<'a> MASK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f); + self.w + } +} +#[doc = "Field `TSTARTEN` reader - Trace Start Input Enable"] +pub struct TSTARTEN_R(crate::FieldReader); +impl TSTARTEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSTARTEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSTARTEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSTARTEN` writer - Trace Start Input Enable"] +pub struct TSTARTEN_W<'a> { + w: &'a mut W, +} +impl<'a> TSTARTEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `TSTOPEN` reader - Trace Stop Input Enable"] +pub struct TSTOPEN_R(crate::FieldReader); +impl TSTOPEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSTOPEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSTOPEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSTOPEN` writer - Trace Stop Input Enable"] +pub struct TSTOPEN_W<'a> { + w: &'a mut W, +} +impl<'a> TSTOPEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `SFRWPRIV` reader - Special Function Register Write Privilege"] +pub struct SFRWPRIV_R(crate::FieldReader); +impl SFRWPRIV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SFRWPRIV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SFRWPRIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SFRWPRIV` writer - Special Function Register Write Privilege"] +pub struct SFRWPRIV_W<'a> { + w: &'a mut W, +} +impl<'a> SFRWPRIV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `RAMPRIV` reader - SRAM Privilege"] +pub struct RAMPRIV_R(crate::FieldReader); +impl RAMPRIV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RAMPRIV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RAMPRIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RAMPRIV` writer - SRAM Privilege"] +pub struct RAMPRIV_W<'a> { + w: &'a mut W, +} +impl<'a> RAMPRIV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `HALTREQ` reader - Halt Request"] +pub struct HALTREQ_R(crate::FieldReader); +impl HALTREQ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HALTREQ_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HALTREQ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HALTREQ` writer - Halt Request"] +pub struct HALTREQ_W<'a> { + w: &'a mut W, +} +impl<'a> HALTREQ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `EN` reader - Main Trace Enable"] +pub struct EN_R(crate::FieldReader); +impl EN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EN` writer - Main Trace Enable"] +pub struct EN_W<'a> { + w: &'a mut W, +} +impl<'a> EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Maximum Value of the Trace Buffer in SRAM"] + #[inline(always)] + pub fn mask(&self) -> MASK_R { + MASK_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bit 5 - Trace Start Input Enable"] + #[inline(always)] + pub fn tstarten(&self) -> TSTARTEN_R { + TSTARTEN_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Trace Stop Input Enable"] + #[inline(always)] + pub fn tstopen(&self) -> TSTOPEN_R { + TSTOPEN_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Special Function Register Write Privilege"] + #[inline(always)] + pub fn sfrwpriv(&self) -> SFRWPRIV_R { + SFRWPRIV_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - SRAM Privilege"] + #[inline(always)] + pub fn rampriv(&self) -> RAMPRIV_R { + RAMPRIV_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Halt Request"] + #[inline(always)] + pub fn haltreq(&self) -> HALTREQ_R { + HALTREQ_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 31 - Main Trace Enable"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Maximum Value of the Trace Buffer in SRAM"] + #[inline(always)] + pub fn mask(&mut self) -> MASK_W { + MASK_W { w: self } + } + #[doc = "Bit 5 - Trace Start Input Enable"] + #[inline(always)] + pub fn tstarten(&mut self) -> TSTARTEN_W { + TSTARTEN_W { w: self } + } + #[doc = "Bit 6 - Trace Stop Input Enable"] + #[inline(always)] + pub fn tstopen(&mut self) -> TSTOPEN_W { + TSTOPEN_W { w: self } + } + #[doc = "Bit 7 - Special Function Register Write Privilege"] + #[inline(always)] + pub fn sfrwpriv(&mut self) -> SFRWPRIV_W { + SFRWPRIV_W { w: self } + } + #[doc = "Bit 8 - SRAM Privilege"] + #[inline(always)] + pub fn rampriv(&mut self) -> RAMPRIV_W { + RAMPRIV_W { w: self } + } + #[doc = "Bit 9 - Halt Request"] + #[inline(always)] + pub fn haltreq(&mut self) -> HALTREQ_W { + HALTREQ_W { w: self } + } + #[doc = "Bit 31 - Main Trace Enable"] + #[inline(always)] + pub fn en(&mut self) -> EN_W { + EN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MTB Master\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [master](index.html) module"] +pub struct MASTER_SPEC; +impl crate::RegisterSpec for MASTER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [master::R](R) reader structure"] +impl crate::Readable for MASTER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [master::W](W) writer structure"] +impl crate::Writable for MASTER_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets MASTER to value 0"] +impl crate::Resettable for MASTER_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/mtb/pid0.rs b/pac/atsamc20n/src/mtb/pid0.rs new file mode 100644 index 000000000000..0a7183189fe5 --- /dev/null +++ b/pac/atsamc20n/src/mtb/pid0.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid0](index.html) module"] +pub struct PID0_SPEC; +impl crate::RegisterSpec for PID0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid0::R](R) reader structure"] +impl crate::Readable for PID0_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID0 to value 0"] +impl crate::Resettable for PID0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/mtb/pid1.rs b/pac/atsamc20n/src/mtb/pid1.rs new file mode 100644 index 000000000000..7d6381917f5d --- /dev/null +++ b/pac/atsamc20n/src/mtb/pid1.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid1](index.html) module"] +pub struct PID1_SPEC; +impl crate::RegisterSpec for PID1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid1::R](R) reader structure"] +impl crate::Readable for PID1_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID1 to value 0"] +impl crate::Resettable for PID1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/mtb/pid2.rs b/pac/atsamc20n/src/mtb/pid2.rs new file mode 100644 index 000000000000..74c230346b4c --- /dev/null +++ b/pac/atsamc20n/src/mtb/pid2.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 2\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid2](index.html) module"] +pub struct PID2_SPEC; +impl crate::RegisterSpec for PID2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid2::R](R) reader structure"] +impl crate::Readable for PID2_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID2 to value 0"] +impl crate::Resettable for PID2_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/mtb/pid3.rs b/pac/atsamc20n/src/mtb/pid3.rs new file mode 100644 index 000000000000..e9e922aa2f21 --- /dev/null +++ b/pac/atsamc20n/src/mtb/pid3.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 3\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid3](index.html) module"] +pub struct PID3_SPEC; +impl crate::RegisterSpec for PID3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid3::R](R) reader structure"] +impl crate::Readable for PID3_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID3 to value 0"] +impl crate::Resettable for PID3_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/mtb/pid4.rs b/pac/atsamc20n/src/mtb/pid4.rs new file mode 100644 index 000000000000..89074d3c2692 --- /dev/null +++ b/pac/atsamc20n/src/mtb/pid4.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID4` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 4\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid4](index.html) module"] +pub struct PID4_SPEC; +impl crate::RegisterSpec for PID4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid4::R](R) reader structure"] +impl crate::Readable for PID4_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID4 to value 0"] +impl crate::Resettable for PID4_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/mtb/pid5.rs b/pac/atsamc20n/src/mtb/pid5.rs new file mode 100644 index 000000000000..d343d4800b95 --- /dev/null +++ b/pac/atsamc20n/src/mtb/pid5.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID5` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 5\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid5](index.html) module"] +pub struct PID5_SPEC; +impl crate::RegisterSpec for PID5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid5::R](R) reader structure"] +impl crate::Readable for PID5_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID5 to value 0"] +impl crate::Resettable for PID5_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/mtb/pid6.rs b/pac/atsamc20n/src/mtb/pid6.rs new file mode 100644 index 000000000000..55cc2b8b5861 --- /dev/null +++ b/pac/atsamc20n/src/mtb/pid6.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID6` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 6\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid6](index.html) module"] +pub struct PID6_SPEC; +impl crate::RegisterSpec for PID6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid6::R](R) reader structure"] +impl crate::Readable for PID6_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID6 to value 0"] +impl crate::Resettable for PID6_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/mtb/pid7.rs b/pac/atsamc20n/src/mtb/pid7.rs new file mode 100644 index 000000000000..77664d4f2f95 --- /dev/null +++ b/pac/atsamc20n/src/mtb/pid7.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID7` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 7\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid7](index.html) module"] +pub struct PID7_SPEC; +impl crate::RegisterSpec for PID7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid7::R](R) reader structure"] +impl crate::Readable for PID7_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID7 to value 0"] +impl crate::Resettable for PID7_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/mtb/position.rs b/pac/atsamc20n/src/mtb/position.rs new file mode 100644 index 000000000000..4bab0425b142 --- /dev/null +++ b/pac/atsamc20n/src/mtb/position.rs @@ -0,0 +1,150 @@ +#[doc = "Register `POSITION` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `POSITION` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WRAP` reader - Pointer Value Wraps"] +pub struct WRAP_R(crate::FieldReader); +impl WRAP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WRAP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WRAP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WRAP` writer - Pointer Value Wraps"] +pub struct WRAP_W<'a> { + w: &'a mut W, +} +impl<'a> WRAP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `POINTER` reader - Trace Packet Location Pointer"] +pub struct POINTER_R(crate::FieldReader); +impl POINTER_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + POINTER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for POINTER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `POINTER` writer - Trace Packet Location Pointer"] +pub struct POINTER_W<'a> { + w: &'a mut W, +} +impl<'a> POINTER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1fff_ffff << 3)) | ((value as u32 & 0x1fff_ffff) << 3); + self.w + } +} +impl R { + #[doc = "Bit 2 - Pointer Value Wraps"] + #[inline(always)] + pub fn wrap(&self) -> WRAP_R { + WRAP_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 3:31 - Trace Packet Location Pointer"] + #[inline(always)] + pub fn pointer(&self) -> POINTER_R { + POINTER_R::new(((self.bits >> 3) & 0x1fff_ffff) as u32) + } +} +impl W { + #[doc = "Bit 2 - Pointer Value Wraps"] + #[inline(always)] + pub fn wrap(&mut self) -> WRAP_W { + WRAP_W { w: self } + } + #[doc = "Bits 3:31 - Trace Packet Location Pointer"] + #[inline(always)] + pub fn pointer(&mut self) -> POINTER_W { + POINTER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MTB Position\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [position](index.html) module"] +pub struct POSITION_SPEC; +impl crate::RegisterSpec for POSITION_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [position::R](R) reader structure"] +impl crate::Readable for POSITION_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [position::W](W) writer structure"] +impl crate::Writable for POSITION_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets POSITION to value 0"] +impl crate::Resettable for POSITION_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/nvmctrl.rs b/pac/atsamc20n/src/nvmctrl.rs new file mode 100644 index 000000000000..2c017caaef9c --- /dev/null +++ b/pac/atsamc20n/src/nvmctrl.rs @@ -0,0 +1,76 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + _reserved1: [u8; 0x02], + #[doc = "0x04 - Control B"] + pub ctrlb: crate::Reg, + #[doc = "0x08 - NVM Parameter"] + pub param: crate::Reg, + #[doc = "0x0c - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + _reserved4: [u8; 0x03], + #[doc = "0x10 - Interrupt Enable Set"] + pub intenset: crate::Reg, + _reserved5: [u8; 0x03], + #[doc = "0x14 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved6: [u8; 0x03], + #[doc = "0x18 - Status"] + pub status: crate::Reg, + _reserved7: [u8; 0x02], + #[doc = "0x1c - Address"] + pub addr: crate::Reg, + #[doc = "0x20 - Lock Section"] + pub lock: crate::Reg, + _reserved9: [u8; 0x06], + #[doc = "0x28 - Page Buffer Load Data 0"] + pub pbldata0: crate::Reg, + #[doc = "0x2c - Page Buffer Load Data 1"] + pub pbldata1: crate::Reg, +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "Control B"] +pub mod ctrlb; +#[doc = "PARAM register accessor: an alias for `Reg`"] +pub type PARAM = crate::Reg; +#[doc = "NVM Parameter"] +pub mod param; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "ADDR register accessor: an alias for `Reg`"] +pub type ADDR = crate::Reg; +#[doc = "Address"] +pub mod addr; +#[doc = "LOCK register accessor: an alias for `Reg`"] +pub type LOCK = crate::Reg; +#[doc = "Lock Section"] +pub mod lock; +#[doc = "PBLDATA0 register accessor: an alias for `Reg`"] +pub type PBLDATA0 = crate::Reg; +#[doc = "Page Buffer Load Data 0"] +pub mod pbldata0; +#[doc = "PBLDATA1 register accessor: an alias for `Reg`"] +pub type PBLDATA1 = crate::Reg; +#[doc = "Page Buffer Load Data 1"] +pub mod pbldata1; diff --git a/pac/atsamc20n/src/nvmctrl/addr.rs b/pac/atsamc20n/src/nvmctrl/addr.rs new file mode 100644 index 000000000000..74ed27736dac --- /dev/null +++ b/pac/atsamc20n/src/nvmctrl/addr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `ADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ADDR` reader - NVM Address"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - NVM Address"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x003f_ffff) | (value as u32 & 0x003f_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:21 - NVM Address"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new((self.bits & 0x003f_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:21 - NVM Address"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [addr](index.html) module"] +pub struct ADDR_SPEC; +impl crate::RegisterSpec for ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [addr::R](R) reader structure"] +impl crate::Readable for ADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [addr::W](W) writer structure"] +impl crate::Writable for ADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ADDR to value 0"] +impl crate::Resettable for ADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/nvmctrl/ctrla.rs b/pac/atsamc20n/src/nvmctrl/ctrla.rs new file mode 100644 index 000000000000..89f175771e4d --- /dev/null +++ b/pac/atsamc20n/src/nvmctrl/ctrla.rs @@ -0,0 +1,394 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "2: Erase Row - Erases the row addressed by the ADDR register."] + ER = 2, + #[doc = "4: Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register."] + WP = 4, + #[doc = "5: Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row."] + EAR = 5, + #[doc = "6: Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row."] + WAP = 6, + #[doc = "10: Security Flow Command"] + SF = 10, + #[doc = "15: Write lockbits"] + WL = 15, + #[doc = "26: RWW EEPROM area Erase Row - Erases the row addressed by the ADDR register."] + RWWEEER = 26, + #[doc = "28: RWW EEPROM Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register."] + RWWEEWP = 28, + #[doc = "64: Lock Region - Locks the region containing the address location in the ADDR register."] + LR = 64, + #[doc = "65: Unlock Region - Unlocks the region containing the address location in the ADDR register."] + UR = 65, + #[doc = "66: Sets the power reduction mode."] + SPRM = 66, + #[doc = "67: Clears the power reduction mode."] + CPRM = 67, + #[doc = "68: Page Buffer Clear - Clears the page buffer."] + PBC = 68, + #[doc = "69: Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row."] + SSB = 69, + #[doc = "70: Invalidate all cache lines."] + INVALL = 70, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 2 => Some(CMD_A::ER), + 4 => Some(CMD_A::WP), + 5 => Some(CMD_A::EAR), + 6 => Some(CMD_A::WAP), + 10 => Some(CMD_A::SF), + 15 => Some(CMD_A::WL), + 26 => Some(CMD_A::RWWEEER), + 28 => Some(CMD_A::RWWEEWP), + 64 => Some(CMD_A::LR), + 65 => Some(CMD_A::UR), + 66 => Some(CMD_A::SPRM), + 67 => Some(CMD_A::CPRM), + 68 => Some(CMD_A::PBC), + 69 => Some(CMD_A::SSB), + 70 => Some(CMD_A::INVALL), + _ => None, + } + } + #[doc = "Checks if the value of the field is `ER`"] + #[inline(always)] + pub fn is_er(&self) -> bool { + **self == CMD_A::ER + } + #[doc = "Checks if the value of the field is `WP`"] + #[inline(always)] + pub fn is_wp(&self) -> bool { + **self == CMD_A::WP + } + #[doc = "Checks if the value of the field is `EAR`"] + #[inline(always)] + pub fn is_ear(&self) -> bool { + **self == CMD_A::EAR + } + #[doc = "Checks if the value of the field is `WAP`"] + #[inline(always)] + pub fn is_wap(&self) -> bool { + **self == CMD_A::WAP + } + #[doc = "Checks if the value of the field is `SF`"] + #[inline(always)] + pub fn is_sf(&self) -> bool { + **self == CMD_A::SF + } + #[doc = "Checks if the value of the field is `WL`"] + #[inline(always)] + pub fn is_wl(&self) -> bool { + **self == CMD_A::WL + } + #[doc = "Checks if the value of the field is `RWWEEER`"] + #[inline(always)] + pub fn is_rwweeer(&self) -> bool { + **self == CMD_A::RWWEEER + } + #[doc = "Checks if the value of the field is `RWWEEWP`"] + #[inline(always)] + pub fn is_rwweewp(&self) -> bool { + **self == CMD_A::RWWEEWP + } + #[doc = "Checks if the value of the field is `LR`"] + #[inline(always)] + pub fn is_lr(&self) -> bool { + **self == CMD_A::LR + } + #[doc = "Checks if the value of the field is `UR`"] + #[inline(always)] + pub fn is_ur(&self) -> bool { + **self == CMD_A::UR + } + #[doc = "Checks if the value of the field is `SPRM`"] + #[inline(always)] + pub fn is_sprm(&self) -> bool { + **self == CMD_A::SPRM + } + #[doc = "Checks if the value of the field is `CPRM`"] + #[inline(always)] + pub fn is_cprm(&self) -> bool { + **self == CMD_A::CPRM + } + #[doc = "Checks if the value of the field is `PBC`"] + #[inline(always)] + pub fn is_pbc(&self) -> bool { + **self == CMD_A::PBC + } + #[doc = "Checks if the value of the field is `SSB`"] + #[inline(always)] + pub fn is_ssb(&self) -> bool { + **self == CMD_A::SSB + } + #[doc = "Checks if the value of the field is `INVALL`"] + #[inline(always)] + pub fn is_invall(&self) -> bool { + **self == CMD_A::INVALL + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Erase Row - Erases the row addressed by the ADDR register."] + #[inline(always)] + pub fn er(self) -> &'a mut W { + self.variant(CMD_A::ER) + } + #[doc = "Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register."] + #[inline(always)] + pub fn wp(self) -> &'a mut W { + self.variant(CMD_A::WP) + } + #[doc = "Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row."] + #[inline(always)] + pub fn ear(self) -> &'a mut W { + self.variant(CMD_A::EAR) + } + #[doc = "Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row."] + #[inline(always)] + pub fn wap(self) -> &'a mut W { + self.variant(CMD_A::WAP) + } + #[doc = "Security Flow Command"] + #[inline(always)] + pub fn sf(self) -> &'a mut W { + self.variant(CMD_A::SF) + } + #[doc = "Write lockbits"] + #[inline(always)] + pub fn wl(self) -> &'a mut W { + self.variant(CMD_A::WL) + } + #[doc = "RWW EEPROM area Erase Row - Erases the row addressed by the ADDR register."] + #[inline(always)] + pub fn rwweeer(self) -> &'a mut W { + self.variant(CMD_A::RWWEEER) + } + #[doc = "RWW EEPROM Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register."] + #[inline(always)] + pub fn rwweewp(self) -> &'a mut W { + self.variant(CMD_A::RWWEEWP) + } + #[doc = "Lock Region - Locks the region containing the address location in the ADDR register."] + #[inline(always)] + pub fn lr(self) -> &'a mut W { + self.variant(CMD_A::LR) + } + #[doc = "Unlock Region - Unlocks the region containing the address location in the ADDR register."] + #[inline(always)] + pub fn ur(self) -> &'a mut W { + self.variant(CMD_A::UR) + } + #[doc = "Sets the power reduction mode."] + #[inline(always)] + pub fn sprm(self) -> &'a mut W { + self.variant(CMD_A::SPRM) + } + #[doc = "Clears the power reduction mode."] + #[inline(always)] + pub fn cprm(self) -> &'a mut W { + self.variant(CMD_A::CPRM) + } + #[doc = "Page Buffer Clear - Clears the page buffer."] + #[inline(always)] + pub fn pbc(self) -> &'a mut W { + self.variant(CMD_A::PBC) + } + #[doc = "Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row."] + #[inline(always)] + pub fn ssb(self) -> &'a mut W { + self.variant(CMD_A::SSB) + } + #[doc = "Invalidate all cache lines."] + #[inline(always)] + pub fn invall(self) -> &'a mut W { + self.variant(CMD_A::INVALL) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x7f) | (value as u16 & 0x7f); + self.w + } +} +#[doc = "Command Execution\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMDEX_A { + #[doc = "165: Execution Key"] + KEY = 165, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMDEX_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMDEX` reader - Command Execution"] +pub struct CMDEX_R(crate::FieldReader); +impl CMDEX_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMDEX_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 165 => Some(CMDEX_A::KEY), + _ => None, + } + } + #[doc = "Checks if the value of the field is `KEY`"] + #[inline(always)] + pub fn is_key(&self) -> bool { + **self == CMDEX_A::KEY + } +} +impl core::ops::Deref for CMDEX_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMDEX` writer - Command Execution"] +pub struct CMDEX_W<'a> { + w: &'a mut W, +} +impl<'a> CMDEX_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMDEX_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Execution Key"] + #[inline(always)] + pub fn key(self) -> &'a mut W { + self.variant(CMDEX_A::KEY) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u16 & 0xff) << 8); + self.w + } +} +impl R { + #[doc = "Bits 0:6 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bits 8:15 - Command Execution"] + #[inline(always)] + pub fn cmdex(&self) -> CMDEX_R { + CMDEX_R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:6 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Bits 8:15 - Command Execution"] + #[inline(always)] + pub fn cmdex(&mut self) -> CMDEX_W { + CMDEX_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/nvmctrl/ctrlb.rs b/pac/atsamc20n/src/nvmctrl/ctrlb.rs new file mode 100644 index 000000000000..6162d0d4ade0 --- /dev/null +++ b/pac/atsamc20n/src/nvmctrl/ctrlb.rs @@ -0,0 +1,447 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "NVM Read Wait States\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum RWS_A { + #[doc = "0: Single Auto Wait State"] + SINGLE = 0, + #[doc = "1: Half Auto Wait State"] + HALF = 1, + #[doc = "2: Dual Auto Wait State"] + DUAL = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RWS_A) -> Self { + variant as _ + } +} +#[doc = "Field `RWS` reader - NVM Read Wait States"] +pub struct RWS_R(crate::FieldReader); +impl RWS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RWS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(RWS_A::SINGLE), + 1 => Some(RWS_A::HALF), + 2 => Some(RWS_A::DUAL), + _ => None, + } + } + #[doc = "Checks if the value of the field is `SINGLE`"] + #[inline(always)] + pub fn is_single(&self) -> bool { + **self == RWS_A::SINGLE + } + #[doc = "Checks if the value of the field is `HALF`"] + #[inline(always)] + pub fn is_half(&self) -> bool { + **self == RWS_A::HALF + } + #[doc = "Checks if the value of the field is `DUAL`"] + #[inline(always)] + pub fn is_dual(&self) -> bool { + **self == RWS_A::DUAL + } +} +impl core::ops::Deref for RWS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RWS` writer - NVM Read Wait States"] +pub struct RWS_W<'a> { + w: &'a mut W, +} +impl<'a> RWS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RWS_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Single Auto Wait State"] + #[inline(always)] + pub fn single(self) -> &'a mut W { + self.variant(RWS_A::SINGLE) + } + #[doc = "Half Auto Wait State"] + #[inline(always)] + pub fn half(self) -> &'a mut W { + self.variant(RWS_A::HALF) + } + #[doc = "Dual Auto Wait State"] + #[inline(always)] + pub fn dual(self) -> &'a mut W { + self.variant(RWS_A::DUAL) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 1)) | ((value as u32 & 0x0f) << 1); + self.w + } +} +#[doc = "Field `MANW` reader - Manual Write"] +pub struct MANW_R(crate::FieldReader); +impl MANW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MANW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MANW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MANW` writer - Manual Write"] +pub struct MANW_W<'a> { + w: &'a mut W, +} +impl<'a> MANW_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Power Reduction Mode during Sleep\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SLEEPPRM_A { + #[doc = "0: NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access."] + WAKEONACCESS = 0, + #[doc = "1: NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep."] + WAKEUPINSTANT = 1, + #[doc = "3: Auto power reduction disabled."] + DISABLED = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SLEEPPRM_A) -> Self { + variant as _ + } +} +#[doc = "Field `SLEEPPRM` reader - Power Reduction Mode during Sleep"] +pub struct SLEEPPRM_R(crate::FieldReader); +impl SLEEPPRM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SLEEPPRM_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SLEEPPRM_A::WAKEONACCESS), + 1 => Some(SLEEPPRM_A::WAKEUPINSTANT), + 3 => Some(SLEEPPRM_A::DISABLED), + _ => None, + } + } + #[doc = "Checks if the value of the field is `WAKEONACCESS`"] + #[inline(always)] + pub fn is_wakeonaccess(&self) -> bool { + **self == SLEEPPRM_A::WAKEONACCESS + } + #[doc = "Checks if the value of the field is `WAKEUPINSTANT`"] + #[inline(always)] + pub fn is_wakeupinstant(&self) -> bool { + **self == SLEEPPRM_A::WAKEUPINSTANT + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + **self == SLEEPPRM_A::DISABLED + } +} +impl core::ops::Deref for SLEEPPRM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLEEPPRM` writer - Power Reduction Mode during Sleep"] +pub struct SLEEPPRM_W<'a> { + w: &'a mut W, +} +impl<'a> SLEEPPRM_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SLEEPPRM_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access."] + #[inline(always)] + pub fn wakeonaccess(self) -> &'a mut W { + self.variant(SLEEPPRM_A::WAKEONACCESS) + } + #[doc = "NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep."] + #[inline(always)] + pub fn wakeupinstant(self) -> &'a mut W { + self.variant(SLEEPPRM_A::WAKEUPINSTANT) + } + #[doc = "Auto power reduction disabled."] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(SLEEPPRM_A::DISABLED) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 8)) | ((value as u32 & 0x03) << 8); + self.w + } +} +#[doc = "NVMCTRL Read Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum READMODE_A { + #[doc = "0: The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance."] + NO_MISS_PENALTY = 0, + #[doc = "1: Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time."] + LOW_POWER = 1, + #[doc = "2: The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings."] + DETERMINISTIC = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: READMODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `READMODE` reader - NVMCTRL Read Mode"] +pub struct READMODE_R(crate::FieldReader); +impl READMODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + READMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(READMODE_A::NO_MISS_PENALTY), + 1 => Some(READMODE_A::LOW_POWER), + 2 => Some(READMODE_A::DETERMINISTIC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NO_MISS_PENALTY`"] + #[inline(always)] + pub fn is_no_miss_penalty(&self) -> bool { + **self == READMODE_A::NO_MISS_PENALTY + } + #[doc = "Checks if the value of the field is `LOW_POWER`"] + #[inline(always)] + pub fn is_low_power(&self) -> bool { + **self == READMODE_A::LOW_POWER + } + #[doc = "Checks if the value of the field is `DETERMINISTIC`"] + #[inline(always)] + pub fn is_deterministic(&self) -> bool { + **self == READMODE_A::DETERMINISTIC + } +} +impl core::ops::Deref for READMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `READMODE` writer - NVMCTRL Read Mode"] +pub struct READMODE_W<'a> { + w: &'a mut W, +} +impl<'a> READMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: READMODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance."] + #[inline(always)] + pub fn no_miss_penalty(self) -> &'a mut W { + self.variant(READMODE_A::NO_MISS_PENALTY) + } + #[doc = "Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time."] + #[inline(always)] + pub fn low_power(self) -> &'a mut W { + self.variant(READMODE_A::LOW_POWER) + } + #[doc = "The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings."] + #[inline(always)] + pub fn deterministic(self) -> &'a mut W { + self.variant(READMODE_A::DETERMINISTIC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Field `CACHEDIS` reader - Cache Disable"] +pub struct CACHEDIS_R(crate::FieldReader); +impl CACHEDIS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CACHEDIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CACHEDIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CACHEDIS` writer - Cache Disable"] +pub struct CACHEDIS_W<'a> { + w: &'a mut W, +} +impl<'a> CACHEDIS_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 18)) | ((value as u32 & 0x03) << 18); + self.w + } +} +impl R { + #[doc = "Bits 1:4 - NVM Read Wait States"] + #[inline(always)] + pub fn rws(&self) -> RWS_R { + RWS_R::new(((self.bits >> 1) & 0x0f) as u8) + } + #[doc = "Bit 7 - Manual Write"] + #[inline(always)] + pub fn manw(&self) -> MANW_R { + MANW_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:9 - Power Reduction Mode during Sleep"] + #[inline(always)] + pub fn sleepprm(&self) -> SLEEPPRM_R { + SLEEPPRM_R::new(((self.bits >> 8) & 0x03) as u8) + } + #[doc = "Bits 16:17 - NVMCTRL Read Mode"] + #[inline(always)] + pub fn readmode(&self) -> READMODE_R { + READMODE_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bits 18:19 - Cache Disable"] + #[inline(always)] + pub fn cachedis(&self) -> CACHEDIS_R { + CACHEDIS_R::new(((self.bits >> 18) & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 1:4 - NVM Read Wait States"] + #[inline(always)] + pub fn rws(&mut self) -> RWS_W { + RWS_W { w: self } + } + #[doc = "Bit 7 - Manual Write"] + #[inline(always)] + pub fn manw(&mut self) -> MANW_W { + MANW_W { w: self } + } + #[doc = "Bits 8:9 - Power Reduction Mode during Sleep"] + #[inline(always)] + pub fn sleepprm(&mut self) -> SLEEPPRM_W { + SLEEPPRM_W { w: self } + } + #[doc = "Bits 16:17 - NVMCTRL Read Mode"] + #[inline(always)] + pub fn readmode(&mut self) -> READMODE_W { + READMODE_W { w: self } + } + #[doc = "Bits 18:19 - Cache Disable"] + #[inline(always)] + pub fn cachedis(&mut self) -> CACHEDIS_W { + CACHEDIS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0x80"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x80 + } +} diff --git a/pac/atsamc20n/src/nvmctrl/intenclr.rs b/pac/atsamc20n/src/nvmctrl/intenclr.rs new file mode 100644 index 000000000000..6e7db4b52c9d --- /dev/null +++ b/pac/atsamc20n/src/nvmctrl/intenclr.rs @@ -0,0 +1,160 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `READY` reader - NVM Ready Interrupt Enable"] +pub struct READY_R(crate::FieldReader); +impl READY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + READY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for READY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `READY` writer - NVM Ready Interrupt Enable"] +pub struct READY_W<'a> { + w: &'a mut W, +} +impl<'a> READY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERROR` reader - Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - NVM Ready Interrupt Enable"] + #[inline(always)] + pub fn ready(&self) -> READY_R { + READY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - NVM Ready Interrupt Enable"] + #[inline(always)] + pub fn ready(&mut self) -> READY_W { + READY_W { w: self } + } + #[doc = "Bit 1 - Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/nvmctrl/intenset.rs b/pac/atsamc20n/src/nvmctrl/intenset.rs new file mode 100644 index 000000000000..ba8698e86c3e --- /dev/null +++ b/pac/atsamc20n/src/nvmctrl/intenset.rs @@ -0,0 +1,160 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `READY` reader - NVM Ready Interrupt Enable"] +pub struct READY_R(crate::FieldReader); +impl READY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + READY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for READY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `READY` writer - NVM Ready Interrupt Enable"] +pub struct READY_W<'a> { + w: &'a mut W, +} +impl<'a> READY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERROR` reader - Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - NVM Ready Interrupt Enable"] + #[inline(always)] + pub fn ready(&self) -> READY_R { + READY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - NVM Ready Interrupt Enable"] + #[inline(always)] + pub fn ready(&mut self) -> READY_W { + READY_W { w: self } + } + #[doc = "Bit 1 - Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/nvmctrl/intflag.rs b/pac/atsamc20n/src/nvmctrl/intflag.rs new file mode 100644 index 000000000000..1b30cdddf25d --- /dev/null +++ b/pac/atsamc20n/src/nvmctrl/intflag.rs @@ -0,0 +1,160 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `READY` reader - NVM Ready"] +pub struct READY_R(crate::FieldReader); +impl READY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + READY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for READY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `READY` writer - NVM Ready"] +pub struct READY_W<'a> { + w: &'a mut W, +} +impl<'a> READY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERROR` reader - Error"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Error"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - NVM Ready"] + #[inline(always)] + pub fn ready(&self) -> READY_R { + READY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Error"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - NVM Ready"] + #[inline(always)] + pub fn ready(&mut self) -> READY_W { + READY_W { w: self } + } + #[doc = "Bit 1 - Error"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/nvmctrl/lock.rs b/pac/atsamc20n/src/nvmctrl/lock.rs new file mode 100644 index 000000000000..dbcf37a8107f --- /dev/null +++ b/pac/atsamc20n/src/nvmctrl/lock.rs @@ -0,0 +1,103 @@ +#[doc = "Register `LOCK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `LOCK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `LOCK` reader - Region Lock Bits"] +pub struct LOCK_R(crate::FieldReader); +impl LOCK_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + LOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LOCK` writer - Region Lock Bits"] +pub struct LOCK_W<'a> { + w: &'a mut W, +} +impl<'a> LOCK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Region Lock Bits"] + #[inline(always)] + pub fn lock(&self) -> LOCK_R { + LOCK_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Region Lock Bits"] + #[inline(always)] + pub fn lock(&mut self) -> LOCK_W { + LOCK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Lock Section\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lock](index.html) module"] +pub struct LOCK_SPEC; +impl crate::RegisterSpec for LOCK_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [lock::R](R) reader structure"] +impl crate::Readable for LOCK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [lock::W](W) writer structure"] +impl crate::Writable for LOCK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets LOCK to value 0"] +impl crate::Resettable for LOCK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/nvmctrl/param.rs b/pac/atsamc20n/src/nvmctrl/param.rs new file mode 100644 index 000000000000..d9197cf16de4 --- /dev/null +++ b/pac/atsamc20n/src/nvmctrl/param.rs @@ -0,0 +1,304 @@ +#[doc = "Register `PARAM` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PARAM` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `NVMP` reader - NVM Pages"] +pub struct NVMP_R(crate::FieldReader); +impl NVMP_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + NVMP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NVMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NVMP` writer - NVM Pages"] +pub struct NVMP_W<'a> { + w: &'a mut W, +} +impl<'a> NVMP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +#[doc = "Page Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PSZ_A { + #[doc = "0: 8 bytes"] + _8 = 0, + #[doc = "1: 16 bytes"] + _16 = 1, + #[doc = "2: 32 bytes"] + _32 = 2, + #[doc = "3: 64 bytes"] + _64 = 3, + #[doc = "4: 128 bytes"] + _128 = 4, + #[doc = "5: 256 bytes"] + _256 = 5, + #[doc = "6: 512 bytes"] + _512 = 6, + #[doc = "7: 1024 bytes"] + _1024 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PSZ_A) -> Self { + variant as _ + } +} +#[doc = "Field `PSZ` reader - Page Size"] +pub struct PSZ_R(crate::FieldReader); +impl PSZ_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PSZ_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PSZ_A { + match self.bits { + 0 => PSZ_A::_8, + 1 => PSZ_A::_16, + 2 => PSZ_A::_32, + 3 => PSZ_A::_64, + 4 => PSZ_A::_128, + 5 => PSZ_A::_256, + 6 => PSZ_A::_512, + 7 => PSZ_A::_1024, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `_8`"] + #[inline(always)] + pub fn is_8(&self) -> bool { + **self == PSZ_A::_8 + } + #[doc = "Checks if the value of the field is `_16`"] + #[inline(always)] + pub fn is_16(&self) -> bool { + **self == PSZ_A::_16 + } + #[doc = "Checks if the value of the field is `_32`"] + #[inline(always)] + pub fn is_32(&self) -> bool { + **self == PSZ_A::_32 + } + #[doc = "Checks if the value of the field is `_64`"] + #[inline(always)] + pub fn is_64(&self) -> bool { + **self == PSZ_A::_64 + } + #[doc = "Checks if the value of the field is `_128`"] + #[inline(always)] + pub fn is_128(&self) -> bool { + **self == PSZ_A::_128 + } + #[doc = "Checks if the value of the field is `_256`"] + #[inline(always)] + pub fn is_256(&self) -> bool { + **self == PSZ_A::_256 + } + #[doc = "Checks if the value of the field is `_512`"] + #[inline(always)] + pub fn is_512(&self) -> bool { + **self == PSZ_A::_512 + } + #[doc = "Checks if the value of the field is `_1024`"] + #[inline(always)] + pub fn is_1024(&self) -> bool { + **self == PSZ_A::_1024 + } +} +impl core::ops::Deref for PSZ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PSZ` writer - Page Size"] +pub struct PSZ_W<'a> { + w: &'a mut W, +} +impl<'a> PSZ_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PSZ_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "8 bytes"] + #[inline(always)] + pub fn _8(self) -> &'a mut W { + self.variant(PSZ_A::_8) + } + #[doc = "16 bytes"] + #[inline(always)] + pub fn _16(self) -> &'a mut W { + self.variant(PSZ_A::_16) + } + #[doc = "32 bytes"] + #[inline(always)] + pub fn _32(self) -> &'a mut W { + self.variant(PSZ_A::_32) + } + #[doc = "64 bytes"] + #[inline(always)] + pub fn _64(self) -> &'a mut W { + self.variant(PSZ_A::_64) + } + #[doc = "128 bytes"] + #[inline(always)] + pub fn _128(self) -> &'a mut W { + self.variant(PSZ_A::_128) + } + #[doc = "256 bytes"] + #[inline(always)] + pub fn _256(self) -> &'a mut W { + self.variant(PSZ_A::_256) + } + #[doc = "512 bytes"] + #[inline(always)] + pub fn _512(self) -> &'a mut W { + self.variant(PSZ_A::_512) + } + #[doc = "1024 bytes"] + #[inline(always)] + pub fn _1024(self) -> &'a mut W { + self.variant(PSZ_A::_1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 16)) | ((value as u32 & 0x07) << 16); + self.w + } +} +#[doc = "Field `RWWEEP` reader - RWW EEPROM Pages"] +pub struct RWWEEP_R(crate::FieldReader); +impl RWWEEP_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + RWWEEP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RWWEEP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RWWEEP` writer - RWW EEPROM Pages"] +pub struct RWWEEP_W<'a> { + w: &'a mut W, +} +impl<'a> RWWEEP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0fff << 20)) | ((value as u32 & 0x0fff) << 20); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - NVM Pages"] + #[inline(always)] + pub fn nvmp(&self) -> NVMP_R { + NVMP_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:18 - Page Size"] + #[inline(always)] + pub fn psz(&self) -> PSZ_R { + PSZ_R::new(((self.bits >> 16) & 0x07) as u8) + } + #[doc = "Bits 20:31 - RWW EEPROM Pages"] + #[inline(always)] + pub fn rwweep(&self) -> RWWEEP_R { + RWWEEP_R::new(((self.bits >> 20) & 0x0fff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - NVM Pages"] + #[inline(always)] + pub fn nvmp(&mut self) -> NVMP_W { + NVMP_W { w: self } + } + #[doc = "Bits 16:18 - Page Size"] + #[inline(always)] + pub fn psz(&mut self) -> PSZ_W { + PSZ_W { w: self } + } + #[doc = "Bits 20:31 - RWW EEPROM Pages"] + #[inline(always)] + pub fn rwweep(&mut self) -> RWWEEP_W { + RWWEEP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "NVM Parameter\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [param](index.html) module"] +pub struct PARAM_SPEC; +impl crate::RegisterSpec for PARAM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [param::R](R) reader structure"] +impl crate::Readable for PARAM_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [param::W](W) writer structure"] +impl crate::Writable for PARAM_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PARAM to value 0"] +impl crate::Resettable for PARAM_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/nvmctrl/pbldata0.rs b/pac/atsamc20n/src/nvmctrl/pbldata0.rs new file mode 100644 index 000000000000..ff2effaf4d89 --- /dev/null +++ b/pac/atsamc20n/src/nvmctrl/pbldata0.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PBLDATA0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Page Buffer Load Data 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pbldata0](index.html) module"] +pub struct PBLDATA0_SPEC; +impl crate::RegisterSpec for PBLDATA0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pbldata0::R](R) reader structure"] +impl crate::Readable for PBLDATA0_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PBLDATA0 to value 0"] +impl crate::Resettable for PBLDATA0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/nvmctrl/pbldata1.rs b/pac/atsamc20n/src/nvmctrl/pbldata1.rs new file mode 100644 index 000000000000..9fc6404691c5 --- /dev/null +++ b/pac/atsamc20n/src/nvmctrl/pbldata1.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PBLDATA1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Page Buffer Load Data 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pbldata1](index.html) module"] +pub struct PBLDATA1_SPEC; +impl crate::RegisterSpec for PBLDATA1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pbldata1::R](R) reader structure"] +impl crate::Readable for PBLDATA1_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PBLDATA1 to value 0"] +impl crate::Resettable for PBLDATA1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/nvmctrl/status.rs b/pac/atsamc20n/src/nvmctrl/status.rs new file mode 100644 index 000000000000..ce849015560e --- /dev/null +++ b/pac/atsamc20n/src/nvmctrl/status.rs @@ -0,0 +1,348 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PRM` reader - Power Reduction Mode"] +pub struct PRM_R(crate::FieldReader); +impl PRM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PRM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PRM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRM` writer - Power Reduction Mode"] +pub struct PRM_W<'a> { + w: &'a mut W, +} +impl<'a> PRM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `LOAD` reader - NVM Page Buffer Active Loading"] +pub struct LOAD_R(crate::FieldReader); +impl LOAD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LOAD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOAD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LOAD` writer - NVM Page Buffer Active Loading"] +pub struct LOAD_W<'a> { + w: &'a mut W, +} +impl<'a> LOAD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PROGE` reader - Programming Error Status"] +pub struct PROGE_R(crate::FieldReader); +impl PROGE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PROGE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PROGE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PROGE` writer - Programming Error Status"] +pub struct PROGE_W<'a> { + w: &'a mut W, +} +impl<'a> PROGE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `LOCKE` reader - Lock Error Status"] +pub struct LOCKE_R(crate::FieldReader); +impl LOCKE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LOCKE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOCKE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LOCKE` writer - Lock Error Status"] +pub struct LOCKE_W<'a> { + w: &'a mut W, +} +impl<'a> LOCKE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `NVME` reader - NVM Error"] +pub struct NVME_R(crate::FieldReader); +impl NVME_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NVME_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NVME_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NVME` writer - NVM Error"] +pub struct NVME_W<'a> { + w: &'a mut W, +} +impl<'a> NVME_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `SB` reader - Security Bit Status"] +pub struct SB_R(crate::FieldReader); +impl SB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SB` writer - Security Bit Status"] +pub struct SB_W<'a> { + w: &'a mut W, +} +impl<'a> SB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +impl R { + #[doc = "Bit 0 - Power Reduction Mode"] + #[inline(always)] + pub fn prm(&self) -> PRM_R { + PRM_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - NVM Page Buffer Active Loading"] + #[inline(always)] + pub fn load(&self) -> LOAD_R { + LOAD_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Programming Error Status"] + #[inline(always)] + pub fn proge(&self) -> PROGE_R { + PROGE_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Lock Error Status"] + #[inline(always)] + pub fn locke(&self) -> LOCKE_R { + LOCKE_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - NVM Error"] + #[inline(always)] + pub fn nvme(&self) -> NVME_R { + NVME_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 8 - Security Bit Status"] + #[inline(always)] + pub fn sb(&self) -> SB_R { + SB_R::new(((self.bits >> 8) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Power Reduction Mode"] + #[inline(always)] + pub fn prm(&mut self) -> PRM_W { + PRM_W { w: self } + } + #[doc = "Bit 1 - NVM Page Buffer Active Loading"] + #[inline(always)] + pub fn load(&mut self) -> LOAD_W { + LOAD_W { w: self } + } + #[doc = "Bit 2 - Programming Error Status"] + #[inline(always)] + pub fn proge(&mut self) -> PROGE_W { + PROGE_W { w: self } + } + #[doc = "Bit 3 - Lock Error Status"] + #[inline(always)] + pub fn locke(&mut self) -> LOCKE_W { + LOCKE_W { w: self } + } + #[doc = "Bit 4 - NVM Error"] + #[inline(always)] + pub fn nvme(&mut self) -> NVME_W { + NVME_W { w: self } + } + #[doc = "Bit 8 - Security Bit Status"] + #[inline(always)] + pub fn sb(&mut self) -> SB_W { + SB_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/osc32kctrl.rs b/pac/atsamc20n/src/osc32kctrl.rs new file mode 100644 index 000000000000..263cd2f61d59 --- /dev/null +++ b/pac/atsamc20n/src/osc32kctrl.rs @@ -0,0 +1,64 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x04 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x08 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x0c - Power and Clocks Status"] + pub status: crate::Reg, + #[doc = "0x10 - Clock selection"] + pub rtcctrl: crate::Reg, + #[doc = "0x14 - 32kHz External Crystal Oscillator (XOSC32K) Control"] + pub xosc32k: crate::Reg, + #[doc = "0x16 - Clock Failure Detector Control"] + pub cfdctrl: crate::Reg, + #[doc = "0x17 - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x18 - 32kHz Internal Oscillator (OSC32K) Control"] + pub osc32k: crate::Reg, + #[doc = "0x1c - 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control"] + pub osculp32k: crate::Reg, +} +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Power and Clocks Status"] +pub mod status; +#[doc = "RTCCTRL register accessor: an alias for `Reg`"] +pub type RTCCTRL = crate::Reg; +#[doc = "Clock selection"] +pub mod rtcctrl; +#[doc = "XOSC32K register accessor: an alias for `Reg`"] +pub type XOSC32K = crate::Reg; +#[doc = "32kHz External Crystal Oscillator (XOSC32K) Control"] +pub mod xosc32k; +#[doc = "CFDCTRL register accessor: an alias for `Reg`"] +pub type CFDCTRL = crate::Reg; +#[doc = "Clock Failure Detector Control"] +pub mod cfdctrl; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "OSC32K register accessor: an alias for `Reg`"] +pub type OSC32K = crate::Reg; +#[doc = "32kHz Internal Oscillator (OSC32K) Control"] +pub mod osc32k; +#[doc = "OSCULP32K register accessor: an alias for `Reg`"] +pub type OSCULP32K = crate::Reg; +#[doc = "32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control"] +pub mod osculp32k; diff --git a/pac/atsamc20n/src/osc32kctrl/cfdctrl.rs b/pac/atsamc20n/src/osc32kctrl/cfdctrl.rs new file mode 100644 index 000000000000..492a86e1a5a7 --- /dev/null +++ b/pac/atsamc20n/src/osc32kctrl/cfdctrl.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CFDCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CFDCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CFDEN` reader - Clock Failure Detector Enable"] +pub struct CFDEN_R(crate::FieldReader); +impl CFDEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFDEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFDEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFDEN` writer - Clock Failure Detector Enable"] +pub struct CFDEN_W<'a> { + w: &'a mut W, +} +impl<'a> CFDEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SWBACK` reader - Clock Switch Back"] +pub struct SWBACK_R(crate::FieldReader); +impl SWBACK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWBACK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWBACK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWBACK` writer - Clock Switch Back"] +pub struct SWBACK_W<'a> { + w: &'a mut W, +} +impl<'a> SWBACK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CFDPRESC` reader - Clock Failure Detector Prescaler"] +pub struct CFDPRESC_R(crate::FieldReader); +impl CFDPRESC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFDPRESC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFDPRESC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFDPRESC` writer - Clock Failure Detector Prescaler"] +pub struct CFDPRESC_W<'a> { + w: &'a mut W, +} +impl<'a> CFDPRESC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Clock Failure Detector Enable"] + #[inline(always)] + pub fn cfden(&self) -> CFDEN_R { + CFDEN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Clock Switch Back"] + #[inline(always)] + pub fn swback(&self) -> SWBACK_R { + SWBACK_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Clock Failure Detector Prescaler"] + #[inline(always)] + pub fn cfdpresc(&self) -> CFDPRESC_R { + CFDPRESC_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Clock Failure Detector Enable"] + #[inline(always)] + pub fn cfden(&mut self) -> CFDEN_W { + CFDEN_W { w: self } + } + #[doc = "Bit 1 - Clock Switch Back"] + #[inline(always)] + pub fn swback(&mut self) -> SWBACK_W { + SWBACK_W { w: self } + } + #[doc = "Bit 2 - Clock Failure Detector Prescaler"] + #[inline(always)] + pub fn cfdpresc(&mut self) -> CFDPRESC_W { + CFDPRESC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Clock Failure Detector Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cfdctrl](index.html) module"] +pub struct CFDCTRL_SPEC; +impl crate::RegisterSpec for CFDCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [cfdctrl::R](R) reader structure"] +impl crate::Readable for CFDCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cfdctrl::W](W) writer structure"] +impl crate::Writable for CFDCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CFDCTRL to value 0"] +impl crate::Resettable for CFDCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/osc32kctrl/evctrl.rs b/pac/atsamc20n/src/osc32kctrl/evctrl.rs new file mode 100644 index 000000000000..e22ba62f0fe2 --- /dev/null +++ b/pac/atsamc20n/src/osc32kctrl/evctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CFDEO` reader - Clock Failure Detector Event Output Enable"] +pub struct CFDEO_R(crate::FieldReader); +impl CFDEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFDEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFDEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFDEO` writer - Clock Failure Detector Event Output Enable"] +pub struct CFDEO_W<'a> { + w: &'a mut W, +} +impl<'a> CFDEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Clock Failure Detector Event Output Enable"] + #[inline(always)] + pub fn cfdeo(&self) -> CFDEO_R { + CFDEO_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Clock Failure Detector Event Output Enable"] + #[inline(always)] + pub fn cfdeo(&mut self) -> CFDEO_W { + CFDEO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/osc32kctrl/intenclr.rs b/pac/atsamc20n/src/osc32kctrl/intenclr.rs new file mode 100644 index 000000000000..7e330c8de495 --- /dev/null +++ b/pac/atsamc20n/src/osc32kctrl/intenclr.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XOSC32KRDY` reader - XOSC32K Ready Interrupt Enable"] +pub struct XOSC32KRDY_R(crate::FieldReader); +impl XOSC32KRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSC32KRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSC32KRDY` writer - XOSC32K Ready Interrupt Enable"] +pub struct XOSC32KRDY_W<'a> { + w: &'a mut W, +} +impl<'a> XOSC32KRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `OSC32KRDY` reader - OSC32K Ready Interrupt Enable"] +pub struct OSC32KRDY_R(crate::FieldReader); +impl OSC32KRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC32KRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC32KRDY` writer - OSC32K Ready Interrupt Enable"] +pub struct OSC32KRDY_W<'a> { + w: &'a mut W, +} +impl<'a> OSC32KRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CLKFAIL` reader - XOSC32K Clock Failure Detector Interrupt Enable"] +pub struct CLKFAIL_R(crate::FieldReader); +impl CLKFAIL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKFAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKFAIL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKFAIL` writer - XOSC32K Clock Failure Detector Interrupt Enable"] +pub struct CLKFAIL_W<'a> { + w: &'a mut W, +} +impl<'a> CLKFAIL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - XOSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn xosc32krdy(&self) -> XOSC32KRDY_R { + XOSC32KRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - OSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn osc32krdy(&self) -> OSC32KRDY_R { + OSC32KRDY_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - XOSC32K Clock Failure Detector Interrupt Enable"] + #[inline(always)] + pub fn clkfail(&self) -> CLKFAIL_R { + CLKFAIL_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - XOSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn xosc32krdy(&mut self) -> XOSC32KRDY_W { + XOSC32KRDY_W { w: self } + } + #[doc = "Bit 1 - OSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn osc32krdy(&mut self) -> OSC32KRDY_W { + OSC32KRDY_W { w: self } + } + #[doc = "Bit 2 - XOSC32K Clock Failure Detector Interrupt Enable"] + #[inline(always)] + pub fn clkfail(&mut self) -> CLKFAIL_W { + CLKFAIL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/osc32kctrl/intenset.rs b/pac/atsamc20n/src/osc32kctrl/intenset.rs new file mode 100644 index 000000000000..e853d40049f2 --- /dev/null +++ b/pac/atsamc20n/src/osc32kctrl/intenset.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XOSC32KRDY` reader - XOSC32K Ready Interrupt Enable"] +pub struct XOSC32KRDY_R(crate::FieldReader); +impl XOSC32KRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSC32KRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSC32KRDY` writer - XOSC32K Ready Interrupt Enable"] +pub struct XOSC32KRDY_W<'a> { + w: &'a mut W, +} +impl<'a> XOSC32KRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `OSC32KRDY` reader - OSC32K Ready Interrupt Enable"] +pub struct OSC32KRDY_R(crate::FieldReader); +impl OSC32KRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC32KRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC32KRDY` writer - OSC32K Ready Interrupt Enable"] +pub struct OSC32KRDY_W<'a> { + w: &'a mut W, +} +impl<'a> OSC32KRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CLKFAIL` reader - XOSC32K Clock Failure Detector Interrupt Enable"] +pub struct CLKFAIL_R(crate::FieldReader); +impl CLKFAIL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKFAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKFAIL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKFAIL` writer - XOSC32K Clock Failure Detector Interrupt Enable"] +pub struct CLKFAIL_W<'a> { + w: &'a mut W, +} +impl<'a> CLKFAIL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - XOSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn xosc32krdy(&self) -> XOSC32KRDY_R { + XOSC32KRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - OSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn osc32krdy(&self) -> OSC32KRDY_R { + OSC32KRDY_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - XOSC32K Clock Failure Detector Interrupt Enable"] + #[inline(always)] + pub fn clkfail(&self) -> CLKFAIL_R { + CLKFAIL_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - XOSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn xosc32krdy(&mut self) -> XOSC32KRDY_W { + XOSC32KRDY_W { w: self } + } + #[doc = "Bit 1 - OSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn osc32krdy(&mut self) -> OSC32KRDY_W { + OSC32KRDY_W { w: self } + } + #[doc = "Bit 2 - XOSC32K Clock Failure Detector Interrupt Enable"] + #[inline(always)] + pub fn clkfail(&mut self) -> CLKFAIL_W { + CLKFAIL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/osc32kctrl/intflag.rs b/pac/atsamc20n/src/osc32kctrl/intflag.rs new file mode 100644 index 000000000000..9ca42439429d --- /dev/null +++ b/pac/atsamc20n/src/osc32kctrl/intflag.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XOSC32KRDY` reader - XOSC32K Ready"] +pub struct XOSC32KRDY_R(crate::FieldReader); +impl XOSC32KRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSC32KRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSC32KRDY` writer - XOSC32K Ready"] +pub struct XOSC32KRDY_W<'a> { + w: &'a mut W, +} +impl<'a> XOSC32KRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `OSC32KRDY` reader - OSC32K Ready"] +pub struct OSC32KRDY_R(crate::FieldReader); +impl OSC32KRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC32KRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC32KRDY` writer - OSC32K Ready"] +pub struct OSC32KRDY_W<'a> { + w: &'a mut W, +} +impl<'a> OSC32KRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CLKFAIL` reader - XOSC32K Clock Failure Detector"] +pub struct CLKFAIL_R(crate::FieldReader); +impl CLKFAIL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKFAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKFAIL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKFAIL` writer - XOSC32K Clock Failure Detector"] +pub struct CLKFAIL_W<'a> { + w: &'a mut W, +} +impl<'a> CLKFAIL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - XOSC32K Ready"] + #[inline(always)] + pub fn xosc32krdy(&self) -> XOSC32KRDY_R { + XOSC32KRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - OSC32K Ready"] + #[inline(always)] + pub fn osc32krdy(&self) -> OSC32KRDY_R { + OSC32KRDY_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - XOSC32K Clock Failure Detector"] + #[inline(always)] + pub fn clkfail(&self) -> CLKFAIL_R { + CLKFAIL_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - XOSC32K Ready"] + #[inline(always)] + pub fn xosc32krdy(&mut self) -> XOSC32KRDY_W { + XOSC32KRDY_W { w: self } + } + #[doc = "Bit 1 - OSC32K Ready"] + #[inline(always)] + pub fn osc32krdy(&mut self) -> OSC32KRDY_W { + OSC32KRDY_W { w: self } + } + #[doc = "Bit 2 - XOSC32K Clock Failure Detector"] + #[inline(always)] + pub fn clkfail(&mut self) -> CLKFAIL_W { + CLKFAIL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/osc32kctrl/osc32k.rs b/pac/atsamc20n/src/osc32kctrl/osc32k.rs new file mode 100644 index 000000000000..aa32cb287aa7 --- /dev/null +++ b/pac/atsamc20n/src/osc32kctrl/osc32k.rs @@ -0,0 +1,549 @@ +#[doc = "Register `OSC32K` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OSC32K` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Oscillator Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Oscillator Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `EN32K` reader - 32kHz Output Enable"] +pub struct EN32K_R(crate::FieldReader); +impl EN32K_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EN32K_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EN32K_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EN32K` writer - 32kHz Output Enable"] +pub struct EN32K_W<'a> { + w: &'a mut W, +} +impl<'a> EN32K_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `EN1K` reader - 1kHz Output Enable"] +pub struct EN1K_R(crate::FieldReader); +impl EN1K_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EN1K_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EN1K_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EN1K` writer - 1kHz Output Enable"] +pub struct EN1K_W<'a> { + w: &'a mut W, +} +impl<'a> EN1K_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - On Demand Control"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - On Demand Control"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Oscillator Start-Up Time\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum STARTUP_A { + #[doc = "0: 0.092 ms"] + CYCLE3 = 0, + #[doc = "1: 0.122 ms"] + CYCLE4 = 1, + #[doc = "2: 0.183 ms"] + CYCLE6 = 2, + #[doc = "3: 0.305 ms"] + CYCLE10 = 3, + #[doc = "4: 0.549 ms"] + CYCLE18 = 4, + #[doc = "5: 1.038 ms"] + CYCLE34 = 5, + #[doc = "6: 2.014 ms"] + CYCLE66 = 6, + #[doc = "7: 3.967 ms"] + CYCLE130 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: STARTUP_A) -> Self { + variant as _ + } +} +#[doc = "Field `STARTUP` reader - Oscillator Start-Up Time"] +pub struct STARTUP_R(crate::FieldReader); +impl STARTUP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + STARTUP_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STARTUP_A { + match self.bits { + 0 => STARTUP_A::CYCLE3, + 1 => STARTUP_A::CYCLE4, + 2 => STARTUP_A::CYCLE6, + 3 => STARTUP_A::CYCLE10, + 4 => STARTUP_A::CYCLE18, + 5 => STARTUP_A::CYCLE34, + 6 => STARTUP_A::CYCLE66, + 7 => STARTUP_A::CYCLE130, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `CYCLE3`"] + #[inline(always)] + pub fn is_cycle3(&self) -> bool { + **self == STARTUP_A::CYCLE3 + } + #[doc = "Checks if the value of the field is `CYCLE4`"] + #[inline(always)] + pub fn is_cycle4(&self) -> bool { + **self == STARTUP_A::CYCLE4 + } + #[doc = "Checks if the value of the field is `CYCLE6`"] + #[inline(always)] + pub fn is_cycle6(&self) -> bool { + **self == STARTUP_A::CYCLE6 + } + #[doc = "Checks if the value of the field is `CYCLE10`"] + #[inline(always)] + pub fn is_cycle10(&self) -> bool { + **self == STARTUP_A::CYCLE10 + } + #[doc = "Checks if the value of the field is `CYCLE18`"] + #[inline(always)] + pub fn is_cycle18(&self) -> bool { + **self == STARTUP_A::CYCLE18 + } + #[doc = "Checks if the value of the field is `CYCLE34`"] + #[inline(always)] + pub fn is_cycle34(&self) -> bool { + **self == STARTUP_A::CYCLE34 + } + #[doc = "Checks if the value of the field is `CYCLE66`"] + #[inline(always)] + pub fn is_cycle66(&self) -> bool { + **self == STARTUP_A::CYCLE66 + } + #[doc = "Checks if the value of the field is `CYCLE130`"] + #[inline(always)] + pub fn is_cycle130(&self) -> bool { + **self == STARTUP_A::CYCLE130 + } +} +impl core::ops::Deref for STARTUP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STARTUP` writer - Oscillator Start-Up Time"] +pub struct STARTUP_W<'a> { + w: &'a mut W, +} +impl<'a> STARTUP_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: STARTUP_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "0.092 ms"] + #[inline(always)] + pub fn cycle3(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE3) + } + #[doc = "0.122 ms"] + #[inline(always)] + pub fn cycle4(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE4) + } + #[doc = "0.183 ms"] + #[inline(always)] + pub fn cycle6(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE6) + } + #[doc = "0.305 ms"] + #[inline(always)] + pub fn cycle10(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE10) + } + #[doc = "0.549 ms"] + #[inline(always)] + pub fn cycle18(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE18) + } + #[doc = "1.038 ms"] + #[inline(always)] + pub fn cycle34(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE34) + } + #[doc = "2.014 ms"] + #[inline(always)] + pub fn cycle66(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE66) + } + #[doc = "3.967 ms"] + #[inline(always)] + pub fn cycle130(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE130) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +#[doc = "Field `WRTLOCK` reader - Write Lock"] +pub struct WRTLOCK_R(crate::FieldReader); +impl WRTLOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WRTLOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WRTLOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WRTLOCK` writer - Write Lock"] +pub struct WRTLOCK_W<'a> { + w: &'a mut W, +} +impl<'a> WRTLOCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `CALIB` reader - Oscillator Calibration"] +pub struct CALIB_R(crate::FieldReader); +impl CALIB_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CALIB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CALIB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CALIB` writer - Oscillator Calibration"] +pub struct CALIB_W<'a> { + w: &'a mut W, +} +impl<'a> CALIB_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x7f << 16)) | ((value as u32 & 0x7f) << 16); + self.w + } +} +impl R { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - 32kHz Output Enable"] + #[inline(always)] + pub fn en32k(&self) -> EN32K_R { + EN32K_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - 1kHz Output Enable"] + #[inline(always)] + pub fn en1k(&self) -> EN1K_R { + EN1K_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Oscillator Start-Up Time"] + #[inline(always)] + pub fn startup(&self) -> STARTUP_R { + STARTUP_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 12 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&self) -> WRTLOCK_R { + WRTLOCK_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bits 16:22 - Oscillator Calibration"] + #[inline(always)] + pub fn calib(&self) -> CALIB_R { + CALIB_R::new(((self.bits >> 16) & 0x7f) as u8) + } +} +impl W { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - 32kHz Output Enable"] + #[inline(always)] + pub fn en32k(&mut self) -> EN32K_W { + EN32K_W { w: self } + } + #[doc = "Bit 3 - 1kHz Output Enable"] + #[inline(always)] + pub fn en1k(&mut self) -> EN1K_W { + EN1K_W { w: self } + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Bits 8:10 - Oscillator Start-Up Time"] + #[inline(always)] + pub fn startup(&mut self) -> STARTUP_W { + STARTUP_W { w: self } + } + #[doc = "Bit 12 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&mut self) -> WRTLOCK_W { + WRTLOCK_W { w: self } + } + #[doc = "Bits 16:22 - Oscillator Calibration"] + #[inline(always)] + pub fn calib(&mut self) -> CALIB_W { + CALIB_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "32kHz Internal Oscillator (OSC32K) Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [osc32k](index.html) module"] +pub struct OSC32K_SPEC; +impl crate::RegisterSpec for OSC32K_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [osc32k::R](R) reader structure"] +impl crate::Readable for OSC32K_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [osc32k::W](W) writer structure"] +impl crate::Writable for OSC32K_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OSC32K to value 0x003f_0080"] +impl crate::Resettable for OSC32K_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x003f_0080 + } +} diff --git a/pac/atsamc20n/src/osc32kctrl/osculp32k.rs b/pac/atsamc20n/src/osc32kctrl/osculp32k.rs new file mode 100644 index 000000000000..1c351c406e59 --- /dev/null +++ b/pac/atsamc20n/src/osc32kctrl/osculp32k.rs @@ -0,0 +1,150 @@ +#[doc = "Register `OSCULP32K` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OSCULP32K` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CALIB` reader - Oscillator Calibration"] +pub struct CALIB_R(crate::FieldReader); +impl CALIB_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CALIB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CALIB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CALIB` writer - Oscillator Calibration"] +pub struct CALIB_W<'a> { + w: &'a mut W, +} +impl<'a> CALIB_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 8)) | ((value as u32 & 0x1f) << 8); + self.w + } +} +#[doc = "Field `WRTLOCK` reader - Write Lock"] +pub struct WRTLOCK_R(crate::FieldReader); +impl WRTLOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WRTLOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WRTLOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WRTLOCK` writer - Write Lock"] +pub struct WRTLOCK_W<'a> { + w: &'a mut W, +} +impl<'a> WRTLOCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bits 8:12 - Oscillator Calibration"] + #[inline(always)] + pub fn calib(&self) -> CALIB_R { + CALIB_R::new(((self.bits >> 8) & 0x1f) as u8) + } + #[doc = "Bit 15 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&self) -> WRTLOCK_R { + WRTLOCK_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 8:12 - Oscillator Calibration"] + #[inline(always)] + pub fn calib(&mut self) -> CALIB_W { + CALIB_W { w: self } + } + #[doc = "Bit 15 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&mut self) -> WRTLOCK_W { + WRTLOCK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [osculp32k](index.html) module"] +pub struct OSCULP32K_SPEC; +impl crate::RegisterSpec for OSCULP32K_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [osculp32k::R](R) reader structure"] +impl crate::Readable for OSCULP32K_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [osculp32k::W](W) writer structure"] +impl crate::Writable for OSCULP32K_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OSCULP32K to value 0"] +impl crate::Resettable for OSCULP32K_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/osc32kctrl/rtcctrl.rs b/pac/atsamc20n/src/osc32kctrl/rtcctrl.rs new file mode 100644 index 000000000000..1248024a03b9 --- /dev/null +++ b/pac/atsamc20n/src/osc32kctrl/rtcctrl.rs @@ -0,0 +1,204 @@ +#[doc = "Register `RTCCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RTCCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "RTC Clock Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum RTCSEL_A { + #[doc = "0: 1.024kHz from 32kHz internal ULP oscillator"] + ULP1K = 0, + #[doc = "1: 32.768kHz from 32kHz internal ULP oscillator"] + ULP32K = 1, + #[doc = "2: 1.024kHz from 32.768kHz internal oscillator"] + OSC1K = 2, + #[doc = "3: 32.768kHz from 32.768kHz internal oscillator"] + OSC32K = 3, + #[doc = "4: 1.024kHz from 32.768kHz internal oscillator"] + XOSC1K = 4, + #[doc = "5: 32.768kHz from 32.768kHz external crystal oscillator"] + XOSC32K = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RTCSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `RTCSEL` reader - RTC Clock Selection"] +pub struct RTCSEL_R(crate::FieldReader); +impl RTCSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RTCSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(RTCSEL_A::ULP1K), + 1 => Some(RTCSEL_A::ULP32K), + 2 => Some(RTCSEL_A::OSC1K), + 3 => Some(RTCSEL_A::OSC32K), + 4 => Some(RTCSEL_A::XOSC1K), + 5 => Some(RTCSEL_A::XOSC32K), + _ => None, + } + } + #[doc = "Checks if the value of the field is `ULP1K`"] + #[inline(always)] + pub fn is_ulp1k(&self) -> bool { + **self == RTCSEL_A::ULP1K + } + #[doc = "Checks if the value of the field is `ULP32K`"] + #[inline(always)] + pub fn is_ulp32k(&self) -> bool { + **self == RTCSEL_A::ULP32K + } + #[doc = "Checks if the value of the field is `OSC1K`"] + #[inline(always)] + pub fn is_osc1k(&self) -> bool { + **self == RTCSEL_A::OSC1K + } + #[doc = "Checks if the value of the field is `OSC32K`"] + #[inline(always)] + pub fn is_osc32k(&self) -> bool { + **self == RTCSEL_A::OSC32K + } + #[doc = "Checks if the value of the field is `XOSC1K`"] + #[inline(always)] + pub fn is_xosc1k(&self) -> bool { + **self == RTCSEL_A::XOSC1K + } + #[doc = "Checks if the value of the field is `XOSC32K`"] + #[inline(always)] + pub fn is_xosc32k(&self) -> bool { + **self == RTCSEL_A::XOSC32K + } +} +impl core::ops::Deref for RTCSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RTCSEL` writer - RTC Clock Selection"] +pub struct RTCSEL_W<'a> { + w: &'a mut W, +} +impl<'a> RTCSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RTCSEL_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "1.024kHz from 32kHz internal ULP oscillator"] + #[inline(always)] + pub fn ulp1k(self) -> &'a mut W { + self.variant(RTCSEL_A::ULP1K) + } + #[doc = "32.768kHz from 32kHz internal ULP oscillator"] + #[inline(always)] + pub fn ulp32k(self) -> &'a mut W { + self.variant(RTCSEL_A::ULP32K) + } + #[doc = "1.024kHz from 32.768kHz internal oscillator"] + #[inline(always)] + pub fn osc1k(self) -> &'a mut W { + self.variant(RTCSEL_A::OSC1K) + } + #[doc = "32.768kHz from 32.768kHz internal oscillator"] + #[inline(always)] + pub fn osc32k(self) -> &'a mut W { + self.variant(RTCSEL_A::OSC32K) + } + #[doc = "1.024kHz from 32.768kHz internal oscillator"] + #[inline(always)] + pub fn xosc1k(self) -> &'a mut W { + self.variant(RTCSEL_A::XOSC1K) + } + #[doc = "32.768kHz from 32.768kHz external crystal oscillator"] + #[inline(always)] + pub fn xosc32k(self) -> &'a mut W { + self.variant(RTCSEL_A::XOSC32K) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - RTC Clock Selection"] + #[inline(always)] + pub fn rtcsel(&self) -> RTCSEL_R { + RTCSEL_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - RTC Clock Selection"] + #[inline(always)] + pub fn rtcsel(&mut self) -> RTCSEL_W { + RTCSEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Clock selection\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rtcctrl](index.html) module"] +pub struct RTCCTRL_SPEC; +impl crate::RegisterSpec for RTCCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rtcctrl::R](R) reader structure"] +impl crate::Readable for RTCCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rtcctrl::W](W) writer structure"] +impl crate::Writable for RTCCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RTCCTRL to value 0"] +impl crate::Resettable for RTCCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/osc32kctrl/status.rs b/pac/atsamc20n/src/osc32kctrl/status.rs new file mode 100644 index 000000000000..f1f1483ac4e8 --- /dev/null +++ b/pac/atsamc20n/src/osc32kctrl/status.rs @@ -0,0 +1,113 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `XOSC32KRDY` reader - XOSC32K Ready"] +pub struct XOSC32KRDY_R(crate::FieldReader); +impl XOSC32KRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSC32KRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC32KRDY` reader - OSC32K Ready"] +pub struct OSC32KRDY_R(crate::FieldReader); +impl OSC32KRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC32KRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKFAIL` reader - XOSC32K Clock Failure Detector"] +pub struct CLKFAIL_R(crate::FieldReader); +impl CLKFAIL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKFAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKFAIL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKSW` reader - XOSC32K Clock switch"] +pub struct CLKSW_R(crate::FieldReader); +impl CLKSW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKSW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKSW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - XOSC32K Ready"] + #[inline(always)] + pub fn xosc32krdy(&self) -> XOSC32KRDY_R { + XOSC32KRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - OSC32K Ready"] + #[inline(always)] + pub fn osc32krdy(&self) -> OSC32KRDY_R { + OSC32KRDY_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - XOSC32K Clock Failure Detector"] + #[inline(always)] + pub fn clkfail(&self) -> CLKFAIL_R { + CLKFAIL_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - XOSC32K Clock switch"] + #[inline(always)] + pub fn clksw(&self) -> CLKSW_R { + CLKSW_R::new(((self.bits >> 3) & 0x01) != 0) + } +} +#[doc = "Power and Clocks Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/osc32kctrl/xosc32k.rs b/pac/atsamc20n/src/osc32kctrl/xosc32k.rs new file mode 100644 index 000000000000..93e42bba3c0e --- /dev/null +++ b/pac/atsamc20n/src/osc32kctrl/xosc32k.rs @@ -0,0 +1,559 @@ +#[doc = "Register `XOSC32K` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `XOSC32K` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Oscillator Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Oscillator Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `XTALEN` reader - Crystal Oscillator Enable"] +pub struct XTALEN_R(crate::FieldReader); +impl XTALEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XTALEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XTALEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XTALEN` writer - Crystal Oscillator Enable"] +pub struct XTALEN_W<'a> { + w: &'a mut W, +} +impl<'a> XTALEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `EN32K` reader - 32kHz Output Enable"] +pub struct EN32K_R(crate::FieldReader); +impl EN32K_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EN32K_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EN32K_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EN32K` writer - 32kHz Output Enable"] +pub struct EN32K_W<'a> { + w: &'a mut W, +} +impl<'a> EN32K_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `EN1K` reader - 1kHz Output Enable"] +pub struct EN1K_R(crate::FieldReader); +impl EN1K_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EN1K_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EN1K_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EN1K` writer - 1kHz Output Enable"] +pub struct EN1K_W<'a> { + w: &'a mut W, +} +impl<'a> EN1K_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - On Demand Control"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - On Demand Control"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Oscillator Start-Up Time\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum STARTUP_A { + #[doc = "0: 0.122 ms"] + CYCLE1 = 0, + #[doc = "1: 1.068 ms"] + CYCLE32 = 1, + #[doc = "2: 62.6 ms"] + CYCLE2048 = 2, + #[doc = "3: 125 ms"] + CYCLE4096 = 3, + #[doc = "4: 500 ms"] + CYCLE16384 = 4, + #[doc = "5: 1000 ms"] + CYCLE32768 = 5, + #[doc = "6: 2000 ms"] + CYCLE65536 = 6, + #[doc = "7: 4000 ms"] + CYCLE131072 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: STARTUP_A) -> Self { + variant as _ + } +} +#[doc = "Field `STARTUP` reader - Oscillator Start-Up Time"] +pub struct STARTUP_R(crate::FieldReader); +impl STARTUP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + STARTUP_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STARTUP_A { + match self.bits { + 0 => STARTUP_A::CYCLE1, + 1 => STARTUP_A::CYCLE32, + 2 => STARTUP_A::CYCLE2048, + 3 => STARTUP_A::CYCLE4096, + 4 => STARTUP_A::CYCLE16384, + 5 => STARTUP_A::CYCLE32768, + 6 => STARTUP_A::CYCLE65536, + 7 => STARTUP_A::CYCLE131072, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `CYCLE1`"] + #[inline(always)] + pub fn is_cycle1(&self) -> bool { + **self == STARTUP_A::CYCLE1 + } + #[doc = "Checks if the value of the field is `CYCLE32`"] + #[inline(always)] + pub fn is_cycle32(&self) -> bool { + **self == STARTUP_A::CYCLE32 + } + #[doc = "Checks if the value of the field is `CYCLE2048`"] + #[inline(always)] + pub fn is_cycle2048(&self) -> bool { + **self == STARTUP_A::CYCLE2048 + } + #[doc = "Checks if the value of the field is `CYCLE4096`"] + #[inline(always)] + pub fn is_cycle4096(&self) -> bool { + **self == STARTUP_A::CYCLE4096 + } + #[doc = "Checks if the value of the field is `CYCLE16384`"] + #[inline(always)] + pub fn is_cycle16384(&self) -> bool { + **self == STARTUP_A::CYCLE16384 + } + #[doc = "Checks if the value of the field is `CYCLE32768`"] + #[inline(always)] + pub fn is_cycle32768(&self) -> bool { + **self == STARTUP_A::CYCLE32768 + } + #[doc = "Checks if the value of the field is `CYCLE65536`"] + #[inline(always)] + pub fn is_cycle65536(&self) -> bool { + **self == STARTUP_A::CYCLE65536 + } + #[doc = "Checks if the value of the field is `CYCLE131072`"] + #[inline(always)] + pub fn is_cycle131072(&self) -> bool { + **self == STARTUP_A::CYCLE131072 + } +} +impl core::ops::Deref for STARTUP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STARTUP` writer - Oscillator Start-Up Time"] +pub struct STARTUP_W<'a> { + w: &'a mut W, +} +impl<'a> STARTUP_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: STARTUP_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "0.122 ms"] + #[inline(always)] + pub fn cycle1(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE1) + } + #[doc = "1.068 ms"] + #[inline(always)] + pub fn cycle32(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE32) + } + #[doc = "62.6 ms"] + #[inline(always)] + pub fn cycle2048(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE2048) + } + #[doc = "125 ms"] + #[inline(always)] + pub fn cycle4096(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE4096) + } + #[doc = "500 ms"] + #[inline(always)] + pub fn cycle16384(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE16384) + } + #[doc = "1000 ms"] + #[inline(always)] + pub fn cycle32768(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE32768) + } + #[doc = "2000 ms"] + #[inline(always)] + pub fn cycle65536(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE65536) + } + #[doc = "4000 ms"] + #[inline(always)] + pub fn cycle131072(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE131072) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u16 & 0x07) << 8); + self.w + } +} +#[doc = "Field `WRTLOCK` reader - Write Lock"] +pub struct WRTLOCK_R(crate::FieldReader); +impl WRTLOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WRTLOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WRTLOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WRTLOCK` writer - Write Lock"] +pub struct WRTLOCK_W<'a> { + w: &'a mut W, +} +impl<'a> WRTLOCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u16 & 0x01) << 12); + self.w + } +} +impl R { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Crystal Oscillator Enable"] + #[inline(always)] + pub fn xtalen(&self) -> XTALEN_R { + XTALEN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - 32kHz Output Enable"] + #[inline(always)] + pub fn en32k(&self) -> EN32K_R { + EN32K_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - 1kHz Output Enable"] + #[inline(always)] + pub fn en1k(&self) -> EN1K_R { + EN1K_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Oscillator Start-Up Time"] + #[inline(always)] + pub fn startup(&self) -> STARTUP_R { + STARTUP_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 12 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&self) -> WRTLOCK_R { + WRTLOCK_R::new(((self.bits >> 12) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - Crystal Oscillator Enable"] + #[inline(always)] + pub fn xtalen(&mut self) -> XTALEN_W { + XTALEN_W { w: self } + } + #[doc = "Bit 3 - 32kHz Output Enable"] + #[inline(always)] + pub fn en32k(&mut self) -> EN32K_W { + EN32K_W { w: self } + } + #[doc = "Bit 4 - 1kHz Output Enable"] + #[inline(always)] + pub fn en1k(&mut self) -> EN1K_W { + EN1K_W { w: self } + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Bits 8:10 - Oscillator Start-Up Time"] + #[inline(always)] + pub fn startup(&mut self) -> STARTUP_W { + STARTUP_W { w: self } + } + #[doc = "Bit 12 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&mut self) -> WRTLOCK_W { + WRTLOCK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "32kHz External Crystal Oscillator (XOSC32K) Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [xosc32k](index.html) module"] +pub struct XOSC32K_SPEC; +impl crate::RegisterSpec for XOSC32K_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [xosc32k::R](R) reader structure"] +impl crate::Readable for XOSC32K_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [xosc32k::W](W) writer structure"] +impl crate::Writable for XOSC32K_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets XOSC32K to value 0x80"] +impl crate::Resettable for XOSC32K_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x80 + } +} diff --git a/pac/atsamc20n/src/oscctrl.rs b/pac/atsamc20n/src/oscctrl.rs new file mode 100644 index 000000000000..e6dd0929927c --- /dev/null +++ b/pac/atsamc20n/src/oscctrl.rs @@ -0,0 +1,117 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x04 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x08 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x0c - Power and Clocks Status"] + pub status: crate::Reg, + #[doc = "0x10 - External Multipurpose Crystal Oscillator (XOSC) Control"] + pub xoscctrl: crate::Reg, + #[doc = "0x12 - Clock Failure Detector Prescaler"] + pub cfdpresc: crate::Reg, + #[doc = "0x13 - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x14 - 48MHz Internal Oscillator (OSC48M) Control"] + pub osc48mctrl: crate::Reg, + #[doc = "0x15 - OSC48M Divider"] + pub osc48mdiv: crate::Reg, + #[doc = "0x16 - OSC48M Startup Time"] + pub osc48mstup: crate::Reg, + _reserved10: [u8; 0x01], + #[doc = "0x18 - OSC48M Synchronization Busy"] + pub osc48msyncbusy: crate::Reg, + #[doc = "0x1c - DPLL Control"] + pub dpllctrla: crate::Reg, + _reserved12: [u8; 0x03], + #[doc = "0x20 - DPLL Ratio Control"] + pub dpllratio: crate::Reg, + #[doc = "0x24 - Digital Core Configuration"] + pub dpllctrlb: crate::Reg, + #[doc = "0x28 - DPLL Prescaler"] + pub dpllpresc: crate::Reg, + _reserved15: [u8; 0x03], + #[doc = "0x2c - DPLL Synchronization Busy"] + pub dpllsyncbusy: crate::Reg, + _reserved16: [u8; 0x03], + #[doc = "0x30 - DPLL Status"] + pub dpllstatus: crate::Reg, + _reserved17: [u8; 0x07], + #[doc = "0x38 - 48MHz Oscillator Calibration"] + pub cal48m: crate::Reg, +} +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Power and Clocks Status"] +pub mod status; +#[doc = "XOSCCTRL register accessor: an alias for `Reg`"] +pub type XOSCCTRL = crate::Reg; +#[doc = "External Multipurpose Crystal Oscillator (XOSC) Control"] +pub mod xoscctrl; +#[doc = "CFDPRESC register accessor: an alias for `Reg`"] +pub type CFDPRESC = crate::Reg; +#[doc = "Clock Failure Detector Prescaler"] +pub mod cfdpresc; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "OSC48MCTRL register accessor: an alias for `Reg`"] +pub type OSC48MCTRL = crate::Reg; +#[doc = "48MHz Internal Oscillator (OSC48M) Control"] +pub mod osc48mctrl; +#[doc = "OSC48MDIV register accessor: an alias for `Reg`"] +pub type OSC48MDIV = crate::Reg; +#[doc = "OSC48M Divider"] +pub mod osc48mdiv; +#[doc = "OSC48MSTUP register accessor: an alias for `Reg`"] +pub type OSC48MSTUP = crate::Reg; +#[doc = "OSC48M Startup Time"] +pub mod osc48mstup; +#[doc = "OSC48MSYNCBUSY register accessor: an alias for `Reg`"] +pub type OSC48MSYNCBUSY = crate::Reg; +#[doc = "OSC48M Synchronization Busy"] +pub mod osc48msyncbusy; +#[doc = "DPLLCTRLA register accessor: an alias for `Reg`"] +pub type DPLLCTRLA = crate::Reg; +#[doc = "DPLL Control"] +pub mod dpllctrla; +#[doc = "DPLLRATIO register accessor: an alias for `Reg`"] +pub type DPLLRATIO = crate::Reg; +#[doc = "DPLL Ratio Control"] +pub mod dpllratio; +#[doc = "DPLLCTRLB register accessor: an alias for `Reg`"] +pub type DPLLCTRLB = crate::Reg; +#[doc = "Digital Core Configuration"] +pub mod dpllctrlb; +#[doc = "DPLLPRESC register accessor: an alias for `Reg`"] +pub type DPLLPRESC = crate::Reg; +#[doc = "DPLL Prescaler"] +pub mod dpllpresc; +#[doc = "DPLLSYNCBUSY register accessor: an alias for `Reg`"] +pub type DPLLSYNCBUSY = crate::Reg; +#[doc = "DPLL Synchronization Busy"] +pub mod dpllsyncbusy; +#[doc = "DPLLSTATUS register accessor: an alias for `Reg`"] +pub type DPLLSTATUS = crate::Reg; +#[doc = "DPLL Status"] +pub mod dpllstatus; +#[doc = "CAL48M register accessor: an alias for `Reg`"] +pub type CAL48M = crate::Reg; +#[doc = "48MHz Oscillator Calibration"] +pub mod cal48m; diff --git a/pac/atsamc20n/src/oscctrl/cal48m.rs b/pac/atsamc20n/src/oscctrl/cal48m.rs new file mode 100644 index 000000000000..05d5cd2bbc92 --- /dev/null +++ b/pac/atsamc20n/src/oscctrl/cal48m.rs @@ -0,0 +1,177 @@ +#[doc = "Register `CAL48M` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CAL48M` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FCAL` reader - Frequency Calibration (48MHz)"] +pub struct FCAL_R(crate::FieldReader); +impl FCAL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FCAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FCAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FCAL` writer - Frequency Calibration (48MHz)"] +pub struct FCAL_W<'a> { + w: &'a mut W, +} +impl<'a> FCAL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +#[doc = "Field `FRANGE` reader - Frequency Range (48MHz)"] +pub struct FRANGE_R(crate::FieldReader); +impl FRANGE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FRANGE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FRANGE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FRANGE` writer - Frequency Range (48MHz)"] +pub struct FRANGE_W<'a> { + w: &'a mut W, +} +impl<'a> FRANGE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 8)) | ((value as u32 & 0x03) << 8); + self.w + } +} +#[doc = "Field `TCAL` reader - Temperature Calibration (48MHz)"] +pub struct TCAL_R(crate::FieldReader); +impl TCAL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TCAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCAL` writer - Temperature Calibration (48MHz)"] +pub struct TCAL_W<'a> { + w: &'a mut W, +} +impl<'a> TCAL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 16)) | ((value as u32 & 0x3f) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Frequency Calibration (48MHz)"] + #[inline(always)] + pub fn fcal(&self) -> FCAL_R { + FCAL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 8:9 - Frequency Range (48MHz)"] + #[inline(always)] + pub fn frange(&self) -> FRANGE_R { + FRANGE_R::new(((self.bits >> 8) & 0x03) as u8) + } + #[doc = "Bits 16:21 - Temperature Calibration (48MHz)"] + #[inline(always)] + pub fn tcal(&self) -> TCAL_R { + TCAL_R::new(((self.bits >> 16) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - Frequency Calibration (48MHz)"] + #[inline(always)] + pub fn fcal(&mut self) -> FCAL_W { + FCAL_W { w: self } + } + #[doc = "Bits 8:9 - Frequency Range (48MHz)"] + #[inline(always)] + pub fn frange(&mut self) -> FRANGE_W { + FRANGE_W { w: self } + } + #[doc = "Bits 16:21 - Temperature Calibration (48MHz)"] + #[inline(always)] + pub fn tcal(&mut self) -> TCAL_W { + TCAL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "48MHz Oscillator Calibration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cal48m](index.html) module"] +pub struct CAL48M_SPEC; +impl crate::RegisterSpec for CAL48M_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cal48m::R](R) reader structure"] +impl crate::Readable for CAL48M_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cal48m::W](W) writer structure"] +impl crate::Writable for CAL48M_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CAL48M to value 0"] +impl crate::Resettable for CAL48M_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/oscctrl/cfdpresc.rs b/pac/atsamc20n/src/oscctrl/cfdpresc.rs new file mode 100644 index 000000000000..029ae541eec5 --- /dev/null +++ b/pac/atsamc20n/src/oscctrl/cfdpresc.rs @@ -0,0 +1,230 @@ +#[doc = "Register `CFDPRESC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CFDPRESC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Clock Failure Detector Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CFDPRESC_A { + #[doc = "0: 48 MHz"] + DIV1 = 0, + #[doc = "1: 24 MHz"] + DIV2 = 1, + #[doc = "2: 12 MHz"] + DIV4 = 2, + #[doc = "3: 6 MHz"] + DIV8 = 3, + #[doc = "4: 3 MHz"] + DIV16 = 4, + #[doc = "5: 1.5 MHz"] + DIV32 = 5, + #[doc = "6: 0.75 MHz"] + DIV64 = 6, + #[doc = "7: 0.3125 MHz"] + DIV128 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CFDPRESC_A) -> Self { + variant as _ + } +} +#[doc = "Field `CFDPRESC` reader - Clock Failure Detector Prescaler"] +pub struct CFDPRESC_R(crate::FieldReader); +impl CFDPRESC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CFDPRESC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CFDPRESC_A { + match self.bits { + 0 => CFDPRESC_A::DIV1, + 1 => CFDPRESC_A::DIV2, + 2 => CFDPRESC_A::DIV4, + 3 => CFDPRESC_A::DIV8, + 4 => CFDPRESC_A::DIV16, + 5 => CFDPRESC_A::DIV32, + 6 => CFDPRESC_A::DIV64, + 7 => CFDPRESC_A::DIV128, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == CFDPRESC_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == CFDPRESC_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == CFDPRESC_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == CFDPRESC_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == CFDPRESC_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == CFDPRESC_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == CFDPRESC_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == CFDPRESC_A::DIV128 + } +} +impl core::ops::Deref for CFDPRESC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFDPRESC` writer - Clock Failure Detector Prescaler"] +pub struct CFDPRESC_W<'a> { + w: &'a mut W, +} +impl<'a> CFDPRESC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CFDPRESC_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "48 MHz"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(CFDPRESC_A::DIV1) + } + #[doc = "24 MHz"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(CFDPRESC_A::DIV2) + } + #[doc = "12 MHz"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(CFDPRESC_A::DIV4) + } + #[doc = "6 MHz"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(CFDPRESC_A::DIV8) + } + #[doc = "3 MHz"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(CFDPRESC_A::DIV16) + } + #[doc = "1.5 MHz"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(CFDPRESC_A::DIV32) + } + #[doc = "0.75 MHz"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(CFDPRESC_A::DIV64) + } + #[doc = "0.3125 MHz"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(CFDPRESC_A::DIV128) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Clock Failure Detector Prescaler"] + #[inline(always)] + pub fn cfdpresc(&self) -> CFDPRESC_R { + CFDPRESC_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Clock Failure Detector Prescaler"] + #[inline(always)] + pub fn cfdpresc(&mut self) -> CFDPRESC_W { + CFDPRESC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Clock Failure Detector Prescaler\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cfdpresc](index.html) module"] +pub struct CFDPRESC_SPEC; +impl crate::RegisterSpec for CFDPRESC_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [cfdpresc::R](R) reader structure"] +impl crate::Readable for CFDPRESC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cfdpresc::W](W) writer structure"] +impl crate::Writable for CFDPRESC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CFDPRESC to value 0"] +impl crate::Resettable for CFDPRESC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/oscctrl/dpllctrla.rs b/pac/atsamc20n/src/oscctrl/dpllctrla.rs new file mode 100644 index 000000000000..5a60a5087002 --- /dev/null +++ b/pac/atsamc20n/src/oscctrl/dpllctrla.rs @@ -0,0 +1,207 @@ +#[doc = "Register `DPLLCTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DPLLCTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - On Demand"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - On Demand"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - On Demand"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - On Demand"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DPLL Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dpllctrla](index.html) module"] +pub struct DPLLCTRLA_SPEC; +impl crate::RegisterSpec for DPLLCTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dpllctrla::R](R) reader structure"] +impl crate::Readable for DPLLCTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dpllctrla::W](W) writer structure"] +impl crate::Writable for DPLLCTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DPLLCTRLA to value 0x80"] +impl crate::Resettable for DPLLCTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x80 + } +} diff --git a/pac/atsamc20n/src/oscctrl/dpllctrlb.rs b/pac/atsamc20n/src/oscctrl/dpllctrlb.rs new file mode 100644 index 000000000000..8400b0572dd0 --- /dev/null +++ b/pac/atsamc20n/src/oscctrl/dpllctrlb.rs @@ -0,0 +1,580 @@ +#[doc = "Register `DPLLCTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DPLLCTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Proportional Integral Filter Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FILTER_A { + #[doc = "0: Default filter mode"] + DEFAULT = 0, + #[doc = "1: Low bandwidth filter"] + LBFILT = 1, + #[doc = "2: High bandwidth filter"] + HBFILT = 2, + #[doc = "3: High damping filter"] + HDFILT = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FILTER_A) -> Self { + variant as _ + } +} +#[doc = "Field `FILTER` reader - Proportional Integral Filter Selection"] +pub struct FILTER_R(crate::FieldReader); +impl FILTER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FILTER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FILTER_A { + match self.bits { + 0 => FILTER_A::DEFAULT, + 1 => FILTER_A::LBFILT, + 2 => FILTER_A::HBFILT, + 3 => FILTER_A::HDFILT, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DEFAULT`"] + #[inline(always)] + pub fn is_default(&self) -> bool { + **self == FILTER_A::DEFAULT + } + #[doc = "Checks if the value of the field is `LBFILT`"] + #[inline(always)] + pub fn is_lbfilt(&self) -> bool { + **self == FILTER_A::LBFILT + } + #[doc = "Checks if the value of the field is `HBFILT`"] + #[inline(always)] + pub fn is_hbfilt(&self) -> bool { + **self == FILTER_A::HBFILT + } + #[doc = "Checks if the value of the field is `HDFILT`"] + #[inline(always)] + pub fn is_hdfilt(&self) -> bool { + **self == FILTER_A::HDFILT + } +} +impl core::ops::Deref for FILTER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTER` writer - Proportional Integral Filter Selection"] +pub struct FILTER_W<'a> { + w: &'a mut W, +} +impl<'a> FILTER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FILTER_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Default filter mode"] + #[inline(always)] + pub fn default(self) -> &'a mut W { + self.variant(FILTER_A::DEFAULT) + } + #[doc = "Low bandwidth filter"] + #[inline(always)] + pub fn lbfilt(self) -> &'a mut W { + self.variant(FILTER_A::LBFILT) + } + #[doc = "High bandwidth filter"] + #[inline(always)] + pub fn hbfilt(self) -> &'a mut W { + self.variant(FILTER_A::HBFILT) + } + #[doc = "High damping filter"] + #[inline(always)] + pub fn hdfilt(self) -> &'a mut W { + self.variant(FILTER_A::HDFILT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u32 & 0x03); + self.w + } +} +#[doc = "Field `LPEN` reader - Low-Power Enable"] +pub struct LPEN_R(crate::FieldReader); +impl LPEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LPEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LPEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LPEN` writer - Low-Power Enable"] +pub struct LPEN_W<'a> { + w: &'a mut W, +} +impl<'a> LPEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `WUF` reader - Wake Up Fast"] +pub struct WUF_R(crate::FieldReader); +impl WUF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WUF` writer - Wake Up Fast"] +pub struct WUF_W<'a> { + w: &'a mut W, +} +impl<'a> WUF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Reference Clock Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum REFCLK_A { + #[doc = "0: XOSC32K clock reference"] + XOSC32K = 0, + #[doc = "1: XOSC clock reference"] + XOSC = 1, + #[doc = "2: GCLK clock reference"] + GCLK = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: REFCLK_A) -> Self { + variant as _ + } +} +#[doc = "Field `REFCLK` reader - Reference Clock Selection"] +pub struct REFCLK_R(crate::FieldReader); +impl REFCLK_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REFCLK_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(REFCLK_A::XOSC32K), + 1 => Some(REFCLK_A::XOSC), + 2 => Some(REFCLK_A::GCLK), + _ => None, + } + } + #[doc = "Checks if the value of the field is `XOSC32K`"] + #[inline(always)] + pub fn is_xosc32k(&self) -> bool { + **self == REFCLK_A::XOSC32K + } + #[doc = "Checks if the value of the field is `XOSC`"] + #[inline(always)] + pub fn is_xosc(&self) -> bool { + **self == REFCLK_A::XOSC + } + #[doc = "Checks if the value of the field is `GCLK`"] + #[inline(always)] + pub fn is_gclk(&self) -> bool { + **self == REFCLK_A::GCLK + } +} +impl core::ops::Deref for REFCLK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REFCLK` writer - Reference Clock Selection"] +pub struct REFCLK_W<'a> { + w: &'a mut W, +} +impl<'a> REFCLK_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: REFCLK_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "XOSC32K clock reference"] + #[inline(always)] + pub fn xosc32k(self) -> &'a mut W { + self.variant(REFCLK_A::XOSC32K) + } + #[doc = "XOSC clock reference"] + #[inline(always)] + pub fn xosc(self) -> &'a mut W { + self.variant(REFCLK_A::XOSC) + } + #[doc = "GCLK clock reference"] + #[inline(always)] + pub fn gclk(self) -> &'a mut W { + self.variant(REFCLK_A::GCLK) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u32 & 0x03) << 4); + self.w + } +} +#[doc = "Lock Time\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum LTIME_A { + #[doc = "0: No time-out. Automatic lock."] + DEFAULT = 0, + #[doc = "4: Time-out if no lock within 8ms"] + _8MS = 4, + #[doc = "5: Time-out if no lock within 9ms"] + _9MS = 5, + #[doc = "6: Time-out if no lock within 10ms"] + _10MS = 6, + #[doc = "7: Time-out if no lock within 11ms"] + _11MS = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LTIME_A) -> Self { + variant as _ + } +} +#[doc = "Field `LTIME` reader - Lock Time"] +pub struct LTIME_R(crate::FieldReader); +impl LTIME_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LTIME_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(LTIME_A::DEFAULT), + 4 => Some(LTIME_A::_8MS), + 5 => Some(LTIME_A::_9MS), + 6 => Some(LTIME_A::_10MS), + 7 => Some(LTIME_A::_11MS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DEFAULT`"] + #[inline(always)] + pub fn is_default(&self) -> bool { + **self == LTIME_A::DEFAULT + } + #[doc = "Checks if the value of the field is `_8MS`"] + #[inline(always)] + pub fn is_8ms(&self) -> bool { + **self == LTIME_A::_8MS + } + #[doc = "Checks if the value of the field is `_9MS`"] + #[inline(always)] + pub fn is_9ms(&self) -> bool { + **self == LTIME_A::_9MS + } + #[doc = "Checks if the value of the field is `_10MS`"] + #[inline(always)] + pub fn is_10ms(&self) -> bool { + **self == LTIME_A::_10MS + } + #[doc = "Checks if the value of the field is `_11MS`"] + #[inline(always)] + pub fn is_11ms(&self) -> bool { + **self == LTIME_A::_11MS + } +} +impl core::ops::Deref for LTIME_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LTIME` writer - Lock Time"] +pub struct LTIME_W<'a> { + w: &'a mut W, +} +impl<'a> LTIME_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: LTIME_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No time-out. Automatic lock."] + #[inline(always)] + pub fn default(self) -> &'a mut W { + self.variant(LTIME_A::DEFAULT) + } + #[doc = "Time-out if no lock within 8ms"] + #[inline(always)] + pub fn _8ms(self) -> &'a mut W { + self.variant(LTIME_A::_8MS) + } + #[doc = "Time-out if no lock within 9ms"] + #[inline(always)] + pub fn _9ms(self) -> &'a mut W { + self.variant(LTIME_A::_9MS) + } + #[doc = "Time-out if no lock within 10ms"] + #[inline(always)] + pub fn _10ms(self) -> &'a mut W { + self.variant(LTIME_A::_10MS) + } + #[doc = "Time-out if no lock within 11ms"] + #[inline(always)] + pub fn _11ms(self) -> &'a mut W { + self.variant(LTIME_A::_11MS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +#[doc = "Field `LBYPASS` reader - Lock Bypass"] +pub struct LBYPASS_R(crate::FieldReader); +impl LBYPASS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LBYPASS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LBYPASS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LBYPASS` writer - Lock Bypass"] +pub struct LBYPASS_W<'a> { + w: &'a mut W, +} +impl<'a> LBYPASS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `DIV` reader - Clock Divider"] +pub struct DIV_R(crate::FieldReader); +impl DIV_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + DIV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIV` writer - Clock Divider"] +pub struct DIV_W<'a> { + w: &'a mut W, +} +impl<'a> DIV_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07ff << 16)) | ((value as u32 & 0x07ff) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Proportional Integral Filter Selection"] + #[inline(always)] + pub fn filter(&self) -> FILTER_R { + FILTER_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bit 2 - Low-Power Enable"] + #[inline(always)] + pub fn lpen(&self) -> LPEN_R { + LPEN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Wake Up Fast"] + #[inline(always)] + pub fn wuf(&self) -> WUF_R { + WUF_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bits 4:5 - Reference Clock Selection"] + #[inline(always)] + pub fn refclk(&self) -> REFCLK_R { + REFCLK_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bits 8:10 - Lock Time"] + #[inline(always)] + pub fn ltime(&self) -> LTIME_R { + LTIME_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 12 - Lock Bypass"] + #[inline(always)] + pub fn lbypass(&self) -> LBYPASS_R { + LBYPASS_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bits 16:26 - Clock Divider"] + #[inline(always)] + pub fn div(&self) -> DIV_R { + DIV_R::new(((self.bits >> 16) & 0x07ff) as u16) + } +} +impl W { + #[doc = "Bits 0:1 - Proportional Integral Filter Selection"] + #[inline(always)] + pub fn filter(&mut self) -> FILTER_W { + FILTER_W { w: self } + } + #[doc = "Bit 2 - Low-Power Enable"] + #[inline(always)] + pub fn lpen(&mut self) -> LPEN_W { + LPEN_W { w: self } + } + #[doc = "Bit 3 - Wake Up Fast"] + #[inline(always)] + pub fn wuf(&mut self) -> WUF_W { + WUF_W { w: self } + } + #[doc = "Bits 4:5 - Reference Clock Selection"] + #[inline(always)] + pub fn refclk(&mut self) -> REFCLK_W { + REFCLK_W { w: self } + } + #[doc = "Bits 8:10 - Lock Time"] + #[inline(always)] + pub fn ltime(&mut self) -> LTIME_W { + LTIME_W { w: self } + } + #[doc = "Bit 12 - Lock Bypass"] + #[inline(always)] + pub fn lbypass(&mut self) -> LBYPASS_W { + LBYPASS_W { w: self } + } + #[doc = "Bits 16:26 - Clock Divider"] + #[inline(always)] + pub fn div(&mut self) -> DIV_W { + DIV_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Digital Core Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dpllctrlb](index.html) module"] +pub struct DPLLCTRLB_SPEC; +impl crate::RegisterSpec for DPLLCTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dpllctrlb::R](R) reader structure"] +impl crate::Readable for DPLLCTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dpllctrlb::W](W) writer structure"] +impl crate::Writable for DPLLCTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DPLLCTRLB to value 0"] +impl crate::Resettable for DPLLCTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/oscctrl/dpllpresc.rs b/pac/atsamc20n/src/oscctrl/dpllpresc.rs new file mode 100644 index 000000000000..9de662161f99 --- /dev/null +++ b/pac/atsamc20n/src/oscctrl/dpllpresc.rs @@ -0,0 +1,165 @@ +#[doc = "Register `DPLLPRESC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DPLLPRESC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Output Clock Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESC_A { + #[doc = "0: DPLL output is divided by 1"] + DIV1 = 0, + #[doc = "1: DPLL output is divided by 2"] + DIV2 = 1, + #[doc = "2: DPLL output is divided by 4"] + DIV4 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESC_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESC` reader - Output Clock Prescaler"] +pub struct PRESC_R(crate::FieldReader); +impl PRESC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESC_A::DIV1), + 1 => Some(PRESC_A::DIV2), + 2 => Some(PRESC_A::DIV4), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == PRESC_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESC_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESC_A::DIV4 + } +} +impl core::ops::Deref for PRESC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESC` writer - Output Clock Prescaler"] +pub struct PRESC_W<'a> { + w: &'a mut W, +} +impl<'a> PRESC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESC_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "DPLL output is divided by 1"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESC_A::DIV1) + } + #[doc = "DPLL output is divided by 2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESC_A::DIV2) + } + #[doc = "DPLL output is divided by 4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESC_A::DIV4) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u8 & 0x03); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Output Clock Prescaler"] + #[inline(always)] + pub fn presc(&self) -> PRESC_R { + PRESC_R::new((self.bits & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Output Clock Prescaler"] + #[inline(always)] + pub fn presc(&mut self) -> PRESC_W { + PRESC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DPLL Prescaler\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dpllpresc](index.html) module"] +pub struct DPLLPRESC_SPEC; +impl crate::RegisterSpec for DPLLPRESC_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dpllpresc::R](R) reader structure"] +impl crate::Readable for DPLLPRESC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dpllpresc::W](W) writer structure"] +impl crate::Writable for DPLLPRESC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DPLLPRESC to value 0"] +impl crate::Resettable for DPLLPRESC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/oscctrl/dpllratio.rs b/pac/atsamc20n/src/oscctrl/dpllratio.rs new file mode 100644 index 000000000000..93b39e30f1a5 --- /dev/null +++ b/pac/atsamc20n/src/oscctrl/dpllratio.rs @@ -0,0 +1,140 @@ +#[doc = "Register `DPLLRATIO` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DPLLRATIO` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `LDR` reader - Loop Divider Ratio"] +pub struct LDR_R(crate::FieldReader); +impl LDR_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + LDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LDR` writer - Loop Divider Ratio"] +pub struct LDR_W<'a> { + w: &'a mut W, +} +impl<'a> LDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0fff) | (value as u32 & 0x0fff); + self.w + } +} +#[doc = "Field `LDRFRAC` reader - Loop Divider Ratio Fractional Part"] +pub struct LDRFRAC_R(crate::FieldReader); +impl LDRFRAC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LDRFRAC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LDRFRAC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LDRFRAC` writer - Loop Divider Ratio Fractional Part"] +pub struct LDRFRAC_W<'a> { + w: &'a mut W, +} +impl<'a> LDRFRAC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 16)) | ((value as u32 & 0x0f) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:11 - Loop Divider Ratio"] + #[inline(always)] + pub fn ldr(&self) -> LDR_R { + LDR_R::new((self.bits & 0x0fff) as u16) + } + #[doc = "Bits 16:19 - Loop Divider Ratio Fractional Part"] + #[inline(always)] + pub fn ldrfrac(&self) -> LDRFRAC_R { + LDRFRAC_R::new(((self.bits >> 16) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:11 - Loop Divider Ratio"] + #[inline(always)] + pub fn ldr(&mut self) -> LDR_W { + LDR_W { w: self } + } + #[doc = "Bits 16:19 - Loop Divider Ratio Fractional Part"] + #[inline(always)] + pub fn ldrfrac(&mut self) -> LDRFRAC_W { + LDRFRAC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DPLL Ratio Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dpllratio](index.html) module"] +pub struct DPLLRATIO_SPEC; +impl crate::RegisterSpec for DPLLRATIO_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dpllratio::R](R) reader structure"] +impl crate::Readable for DPLLRATIO_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dpllratio::W](W) writer structure"] +impl crate::Writable for DPLLRATIO_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DPLLRATIO to value 0"] +impl crate::Resettable for DPLLRATIO_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/oscctrl/dpllstatus.rs b/pac/atsamc20n/src/oscctrl/dpllstatus.rs new file mode 100644 index 000000000000..931900212816 --- /dev/null +++ b/pac/atsamc20n/src/oscctrl/dpllstatus.rs @@ -0,0 +1,73 @@ +#[doc = "Register `DPLLSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `LOCK` reader - DPLL Lock Status"] +pub struct LOCK_R(crate::FieldReader); +impl LOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKRDY` reader - DPLL Clock Ready"] +pub struct CLKRDY_R(crate::FieldReader); +impl CLKRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - DPLL Lock Status"] + #[inline(always)] + pub fn lock(&self) -> LOCK_R { + LOCK_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - DPLL Clock Ready"] + #[inline(always)] + pub fn clkrdy(&self) -> CLKRDY_R { + CLKRDY_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +#[doc = "DPLL Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dpllstatus](index.html) module"] +pub struct DPLLSTATUS_SPEC; +impl crate::RegisterSpec for DPLLSTATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dpllstatus::R](R) reader structure"] +impl crate::Readable for DPLLSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DPLLSTATUS to value 0"] +impl crate::Resettable for DPLLSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/oscctrl/dpllsyncbusy.rs b/pac/atsamc20n/src/oscctrl/dpllsyncbusy.rs new file mode 100644 index 000000000000..f9fb880a5a59 --- /dev/null +++ b/pac/atsamc20n/src/oscctrl/dpllsyncbusy.rs @@ -0,0 +1,93 @@ +#[doc = "Register `DPLLSYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `ENABLE` reader - DPLL Enable Synchronization Status"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLRATIO` reader - DPLL Ratio Synchronization Status"] +pub struct DPLLRATIO_R(crate::FieldReader); +impl DPLLRATIO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLRATIO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLRATIO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLPRESC` reader - DPLL Prescaler Synchronization Status"] +pub struct DPLLPRESC_R(crate::FieldReader); +impl DPLLPRESC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLPRESC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLPRESC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 1 - DPLL Enable Synchronization Status"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - DPLL Ratio Synchronization Status"] + #[inline(always)] + pub fn dpllratio(&self) -> DPLLRATIO_R { + DPLLRATIO_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - DPLL Prescaler Synchronization Status"] + #[inline(always)] + pub fn dpllpresc(&self) -> DPLLPRESC_R { + DPLLPRESC_R::new(((self.bits >> 3) & 0x01) != 0) + } +} +#[doc = "DPLL Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dpllsyncbusy](index.html) module"] +pub struct DPLLSYNCBUSY_SPEC; +impl crate::RegisterSpec for DPLLSYNCBUSY_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dpllsyncbusy::R](R) reader structure"] +impl crate::Readable for DPLLSYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DPLLSYNCBUSY to value 0"] +impl crate::Resettable for DPLLSYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/oscctrl/evctrl.rs b/pac/atsamc20n/src/oscctrl/evctrl.rs new file mode 100644 index 000000000000..e22ba62f0fe2 --- /dev/null +++ b/pac/atsamc20n/src/oscctrl/evctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CFDEO` reader - Clock Failure Detector Event Output Enable"] +pub struct CFDEO_R(crate::FieldReader); +impl CFDEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFDEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFDEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFDEO` writer - Clock Failure Detector Event Output Enable"] +pub struct CFDEO_W<'a> { + w: &'a mut W, +} +impl<'a> CFDEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Clock Failure Detector Event Output Enable"] + #[inline(always)] + pub fn cfdeo(&self) -> CFDEO_R { + CFDEO_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Clock Failure Detector Event Output Enable"] + #[inline(always)] + pub fn cfdeo(&mut self) -> CFDEO_W { + CFDEO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/oscctrl/intenclr.rs b/pac/atsamc20n/src/oscctrl/intenclr.rs new file mode 100644 index 000000000000..0ea0034a0c02 --- /dev/null +++ b/pac/atsamc20n/src/oscctrl/intenclr.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XOSCRDY` reader - XOSC Ready Interrupt Enable"] +pub struct XOSCRDY_R(crate::FieldReader); +impl XOSCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSCRDY` writer - XOSC Ready Interrupt Enable"] +pub struct XOSCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> XOSCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `XOSCFAIL` reader - XOSC Clock Failure Detector Interrupt Enable"] +pub struct XOSCFAIL_R(crate::FieldReader); +impl XOSCFAIL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSCFAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCFAIL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSCFAIL` writer - XOSC Clock Failure Detector Interrupt Enable"] +pub struct XOSCFAIL_W<'a> { + w: &'a mut W, +} +impl<'a> XOSCFAIL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `OSC48MRDY` reader - OSC48M Ready Interrupt Enable"] +pub struct OSC48MRDY_R(crate::FieldReader); +impl OSC48MRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC48MRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC48MRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC48MRDY` writer - OSC48M Ready Interrupt Enable"] +pub struct OSC48MRDY_W<'a> { + w: &'a mut W, +} +impl<'a> OSC48MRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `DPLLLCKR` reader - DPLL Lock Rise Interrupt Enable"] +pub struct DPLLLCKR_R(crate::FieldReader); +impl DPLLLCKR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKR` writer - DPLL Lock Rise Interrupt Enable"] +pub struct DPLLLCKR_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLCKR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `DPLLLCKF` reader - DPLL Lock Fall Interrupt Enable"] +pub struct DPLLLCKF_R(crate::FieldReader); +impl DPLLLCKF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKF` writer - DPLL Lock Fall Interrupt Enable"] +pub struct DPLLLCKF_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLCKF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `DPLLLTO` reader - DPLL Time Out Interrupt Enable"] +pub struct DPLLLTO_R(crate::FieldReader); +impl DPLLLTO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLTO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLTO` writer - DPLL Time Out Interrupt Enable"] +pub struct DPLLLTO_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLTO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `DPLLLDRTO` reader - DPLL Ratio Ready Interrupt Enable"] +pub struct DPLLLDRTO_R(crate::FieldReader); +impl DPLLLDRTO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLDRTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLDRTO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLDRTO` writer - DPLL Ratio Ready Interrupt Enable"] +pub struct DPLLLDRTO_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLDRTO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +impl R { + #[doc = "Bit 0 - XOSC Ready Interrupt Enable"] + #[inline(always)] + pub fn xoscrdy(&self) -> XOSCRDY_R { + XOSCRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - XOSC Clock Failure Detector Interrupt Enable"] + #[inline(always)] + pub fn xoscfail(&self) -> XOSCFAIL_R { + XOSCFAIL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - OSC48M Ready Interrupt Enable"] + #[inline(always)] + pub fn osc48mrdy(&self) -> OSC48MRDY_R { + OSC48MRDY_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 8 - DPLL Lock Rise Interrupt Enable"] + #[inline(always)] + pub fn dplllckr(&self) -> DPLLLCKR_R { + DPLLLCKR_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - DPLL Lock Fall Interrupt Enable"] + #[inline(always)] + pub fn dplllckf(&self) -> DPLLLCKF_R { + DPLLLCKF_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - DPLL Time Out Interrupt Enable"] + #[inline(always)] + pub fn dplllto(&self) -> DPLLLTO_R { + DPLLLTO_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - DPLL Ratio Ready Interrupt Enable"] + #[inline(always)] + pub fn dpllldrto(&self) -> DPLLLDRTO_R { + DPLLLDRTO_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - XOSC Ready Interrupt Enable"] + #[inline(always)] + pub fn xoscrdy(&mut self) -> XOSCRDY_W { + XOSCRDY_W { w: self } + } + #[doc = "Bit 1 - XOSC Clock Failure Detector Interrupt Enable"] + #[inline(always)] + pub fn xoscfail(&mut self) -> XOSCFAIL_W { + XOSCFAIL_W { w: self } + } + #[doc = "Bit 4 - OSC48M Ready Interrupt Enable"] + #[inline(always)] + pub fn osc48mrdy(&mut self) -> OSC48MRDY_W { + OSC48MRDY_W { w: self } + } + #[doc = "Bit 8 - DPLL Lock Rise Interrupt Enable"] + #[inline(always)] + pub fn dplllckr(&mut self) -> DPLLLCKR_W { + DPLLLCKR_W { w: self } + } + #[doc = "Bit 9 - DPLL Lock Fall Interrupt Enable"] + #[inline(always)] + pub fn dplllckf(&mut self) -> DPLLLCKF_W { + DPLLLCKF_W { w: self } + } + #[doc = "Bit 10 - DPLL Time Out Interrupt Enable"] + #[inline(always)] + pub fn dplllto(&mut self) -> DPLLLTO_W { + DPLLLTO_W { w: self } + } + #[doc = "Bit 11 - DPLL Ratio Ready Interrupt Enable"] + #[inline(always)] + pub fn dpllldrto(&mut self) -> DPLLLDRTO_W { + DPLLLDRTO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/oscctrl/intenset.rs b/pac/atsamc20n/src/oscctrl/intenset.rs new file mode 100644 index 000000000000..2890541e4414 --- /dev/null +++ b/pac/atsamc20n/src/oscctrl/intenset.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XOSCRDY` reader - XOSC Ready Interrupt Enable"] +pub struct XOSCRDY_R(crate::FieldReader); +impl XOSCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSCRDY` writer - XOSC Ready Interrupt Enable"] +pub struct XOSCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> XOSCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `XOSCFAIL` reader - XOSC Clock Failure Detector Interrupt Enable"] +pub struct XOSCFAIL_R(crate::FieldReader); +impl XOSCFAIL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSCFAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCFAIL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSCFAIL` writer - XOSC Clock Failure Detector Interrupt Enable"] +pub struct XOSCFAIL_W<'a> { + w: &'a mut W, +} +impl<'a> XOSCFAIL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `OSC48MRDY` reader - OSC48M Ready Interrupt Enable"] +pub struct OSC48MRDY_R(crate::FieldReader); +impl OSC48MRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC48MRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC48MRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC48MRDY` writer - OSC48M Ready Interrupt Enable"] +pub struct OSC48MRDY_W<'a> { + w: &'a mut W, +} +impl<'a> OSC48MRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `DPLLLCKR` reader - DPLL Lock Rise Interrupt Enable"] +pub struct DPLLLCKR_R(crate::FieldReader); +impl DPLLLCKR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKR` writer - DPLL Lock Rise Interrupt Enable"] +pub struct DPLLLCKR_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLCKR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `DPLLLCKF` reader - DPLL Lock Fall Interrupt Enable"] +pub struct DPLLLCKF_R(crate::FieldReader); +impl DPLLLCKF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKF` writer - DPLL Lock Fall Interrupt Enable"] +pub struct DPLLLCKF_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLCKF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `DPLLLTO` reader - DPLL Time Out Interrupt Enable"] +pub struct DPLLLTO_R(crate::FieldReader); +impl DPLLLTO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLTO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLTO` writer - DPLL Time Out Interrupt Enable"] +pub struct DPLLLTO_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLTO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `DPLLLDRTO` reader - DPLL Ratio Ready Interrupt Enable"] +pub struct DPLLLDRTO_R(crate::FieldReader); +impl DPLLLDRTO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLDRTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLDRTO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLDRTO` writer - DPLL Ratio Ready Interrupt Enable"] +pub struct DPLLLDRTO_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLDRTO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +impl R { + #[doc = "Bit 0 - XOSC Ready Interrupt Enable"] + #[inline(always)] + pub fn xoscrdy(&self) -> XOSCRDY_R { + XOSCRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - XOSC Clock Failure Detector Interrupt Enable"] + #[inline(always)] + pub fn xoscfail(&self) -> XOSCFAIL_R { + XOSCFAIL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - OSC48M Ready Interrupt Enable"] + #[inline(always)] + pub fn osc48mrdy(&self) -> OSC48MRDY_R { + OSC48MRDY_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 8 - DPLL Lock Rise Interrupt Enable"] + #[inline(always)] + pub fn dplllckr(&self) -> DPLLLCKR_R { + DPLLLCKR_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - DPLL Lock Fall Interrupt Enable"] + #[inline(always)] + pub fn dplllckf(&self) -> DPLLLCKF_R { + DPLLLCKF_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - DPLL Time Out Interrupt Enable"] + #[inline(always)] + pub fn dplllto(&self) -> DPLLLTO_R { + DPLLLTO_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - DPLL Ratio Ready Interrupt Enable"] + #[inline(always)] + pub fn dpllldrto(&self) -> DPLLLDRTO_R { + DPLLLDRTO_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - XOSC Ready Interrupt Enable"] + #[inline(always)] + pub fn xoscrdy(&mut self) -> XOSCRDY_W { + XOSCRDY_W { w: self } + } + #[doc = "Bit 1 - XOSC Clock Failure Detector Interrupt Enable"] + #[inline(always)] + pub fn xoscfail(&mut self) -> XOSCFAIL_W { + XOSCFAIL_W { w: self } + } + #[doc = "Bit 4 - OSC48M Ready Interrupt Enable"] + #[inline(always)] + pub fn osc48mrdy(&mut self) -> OSC48MRDY_W { + OSC48MRDY_W { w: self } + } + #[doc = "Bit 8 - DPLL Lock Rise Interrupt Enable"] + #[inline(always)] + pub fn dplllckr(&mut self) -> DPLLLCKR_W { + DPLLLCKR_W { w: self } + } + #[doc = "Bit 9 - DPLL Lock Fall Interrupt Enable"] + #[inline(always)] + pub fn dplllckf(&mut self) -> DPLLLCKF_W { + DPLLLCKF_W { w: self } + } + #[doc = "Bit 10 - DPLL Time Out Interrupt Enable"] + #[inline(always)] + pub fn dplllto(&mut self) -> DPLLLTO_W { + DPLLLTO_W { w: self } + } + #[doc = "Bit 11 - DPLL Ratio Ready Interrupt Enable"] + #[inline(always)] + pub fn dpllldrto(&mut self) -> DPLLLDRTO_W { + DPLLLDRTO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/oscctrl/intflag.rs b/pac/atsamc20n/src/oscctrl/intflag.rs new file mode 100644 index 000000000000..71e452a1b571 --- /dev/null +++ b/pac/atsamc20n/src/oscctrl/intflag.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XOSCRDY` reader - XOSC Ready"] +pub struct XOSCRDY_R(crate::FieldReader); +impl XOSCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSCRDY` writer - XOSC Ready"] +pub struct XOSCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> XOSCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `XOSCFAIL` reader - XOSC Clock Failure Detector"] +pub struct XOSCFAIL_R(crate::FieldReader); +impl XOSCFAIL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSCFAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCFAIL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSCFAIL` writer - XOSC Clock Failure Detector"] +pub struct XOSCFAIL_W<'a> { + w: &'a mut W, +} +impl<'a> XOSCFAIL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `OSC48MRDY` reader - OSC48M Ready"] +pub struct OSC48MRDY_R(crate::FieldReader); +impl OSC48MRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC48MRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC48MRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC48MRDY` writer - OSC48M Ready"] +pub struct OSC48MRDY_W<'a> { + w: &'a mut W, +} +impl<'a> OSC48MRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `DPLLLCKR` reader - DPLL Lock Rise"] +pub struct DPLLLCKR_R(crate::FieldReader); +impl DPLLLCKR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKR` writer - DPLL Lock Rise"] +pub struct DPLLLCKR_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLCKR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `DPLLLCKF` reader - DPLL Lock Fall"] +pub struct DPLLLCKF_R(crate::FieldReader); +impl DPLLLCKF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKF` writer - DPLL Lock Fall"] +pub struct DPLLLCKF_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLCKF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `DPLLLTO` reader - DPLL Timeout"] +pub struct DPLLLTO_R(crate::FieldReader); +impl DPLLLTO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLTO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLTO` writer - DPLL Timeout"] +pub struct DPLLLTO_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLTO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `DPLLLDRTO` reader - DPLL Ratio Ready"] +pub struct DPLLLDRTO_R(crate::FieldReader); +impl DPLLLDRTO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLDRTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLDRTO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLDRTO` writer - DPLL Ratio Ready"] +pub struct DPLLLDRTO_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLDRTO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +impl R { + #[doc = "Bit 0 - XOSC Ready"] + #[inline(always)] + pub fn xoscrdy(&self) -> XOSCRDY_R { + XOSCRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - XOSC Clock Failure Detector"] + #[inline(always)] + pub fn xoscfail(&self) -> XOSCFAIL_R { + XOSCFAIL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - OSC48M Ready"] + #[inline(always)] + pub fn osc48mrdy(&self) -> OSC48MRDY_R { + OSC48MRDY_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 8 - DPLL Lock Rise"] + #[inline(always)] + pub fn dplllckr(&self) -> DPLLLCKR_R { + DPLLLCKR_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - DPLL Lock Fall"] + #[inline(always)] + pub fn dplllckf(&self) -> DPLLLCKF_R { + DPLLLCKF_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - DPLL Timeout"] + #[inline(always)] + pub fn dplllto(&self) -> DPLLLTO_R { + DPLLLTO_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - DPLL Ratio Ready"] + #[inline(always)] + pub fn dpllldrto(&self) -> DPLLLDRTO_R { + DPLLLDRTO_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - XOSC Ready"] + #[inline(always)] + pub fn xoscrdy(&mut self) -> XOSCRDY_W { + XOSCRDY_W { w: self } + } + #[doc = "Bit 1 - XOSC Clock Failure Detector"] + #[inline(always)] + pub fn xoscfail(&mut self) -> XOSCFAIL_W { + XOSCFAIL_W { w: self } + } + #[doc = "Bit 4 - OSC48M Ready"] + #[inline(always)] + pub fn osc48mrdy(&mut self) -> OSC48MRDY_W { + OSC48MRDY_W { w: self } + } + #[doc = "Bit 8 - DPLL Lock Rise"] + #[inline(always)] + pub fn dplllckr(&mut self) -> DPLLLCKR_W { + DPLLLCKR_W { w: self } + } + #[doc = "Bit 9 - DPLL Lock Fall"] + #[inline(always)] + pub fn dplllckf(&mut self) -> DPLLLCKF_W { + DPLLLCKF_W { w: self } + } + #[doc = "Bit 10 - DPLL Timeout"] + #[inline(always)] + pub fn dplllto(&mut self) -> DPLLLTO_W { + DPLLLTO_W { w: self } + } + #[doc = "Bit 11 - DPLL Ratio Ready"] + #[inline(always)] + pub fn dpllldrto(&mut self) -> DPLLLDRTO_W { + DPLLLDRTO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/oscctrl/osc48mctrl.rs b/pac/atsamc20n/src/oscctrl/osc48mctrl.rs new file mode 100644 index 000000000000..8314e21e5775 --- /dev/null +++ b/pac/atsamc20n/src/oscctrl/osc48mctrl.rs @@ -0,0 +1,207 @@ +#[doc = "Register `OSC48MCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OSC48MCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Oscillator Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Oscillator Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - On Demand Control"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - On Demand Control"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "48MHz Internal Oscillator (OSC48M) Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [osc48mctrl](index.html) module"] +pub struct OSC48MCTRL_SPEC; +impl crate::RegisterSpec for OSC48MCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [osc48mctrl::R](R) reader structure"] +impl crate::Readable for OSC48MCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [osc48mctrl::W](W) writer structure"] +impl crate::Writable for OSC48MCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OSC48MCTRL to value 0x82"] +impl crate::Resettable for OSC48MCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x82 + } +} diff --git a/pac/atsamc20n/src/oscctrl/osc48mdiv.rs b/pac/atsamc20n/src/oscctrl/osc48mdiv.rs new file mode 100644 index 000000000000..4ed854b09284 --- /dev/null +++ b/pac/atsamc20n/src/oscctrl/osc48mdiv.rs @@ -0,0 +1,334 @@ +#[doc = "Register `OSC48MDIV` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OSC48MDIV` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "OSC48M Division Factor\n\nValue on reset: 11"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DIV_A { + #[doc = "0: 48 MHz"] + DIV1 = 0, + #[doc = "1: 24 MHz"] + DIV2 = 1, + #[doc = "2: 16 MHz"] + DIV3 = 2, + #[doc = "3: 12 MHz"] + DIV4 = 3, + #[doc = "4: 9.6 MHz"] + DIV5 = 4, + #[doc = "5: 8 MHz"] + DIV6 = 5, + #[doc = "6: 6.86 MHz"] + DIV7 = 6, + #[doc = "7: 6 MHz"] + DIV8 = 7, + #[doc = "8: 5.33 MHz"] + DIV9 = 8, + #[doc = "9: 4.8 MHz"] + DIV10 = 9, + #[doc = "10: 4.36 MHz"] + DIV11 = 10, + #[doc = "11: 4 MHz"] + DIV12 = 11, + #[doc = "12: 3.69 MHz"] + DIV13 = 12, + #[doc = "13: 3.43 MHz"] + DIV14 = 13, + #[doc = "14: 3.2 MHz"] + DIV15 = 14, + #[doc = "15: 3 MHz"] + DIV16 = 15, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DIV_A) -> Self { + variant as _ + } +} +#[doc = "Field `DIV` reader - OSC48M Division Factor"] +pub struct DIV_R(crate::FieldReader); +impl DIV_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DIV_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DIV_A { + match self.bits { + 0 => DIV_A::DIV1, + 1 => DIV_A::DIV2, + 2 => DIV_A::DIV3, + 3 => DIV_A::DIV4, + 4 => DIV_A::DIV5, + 5 => DIV_A::DIV6, + 6 => DIV_A::DIV7, + 7 => DIV_A::DIV8, + 8 => DIV_A::DIV9, + 9 => DIV_A::DIV10, + 10 => DIV_A::DIV11, + 11 => DIV_A::DIV12, + 12 => DIV_A::DIV13, + 13 => DIV_A::DIV14, + 14 => DIV_A::DIV15, + 15 => DIV_A::DIV16, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == DIV_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == DIV_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV3`"] + #[inline(always)] + pub fn is_div3(&self) -> bool { + **self == DIV_A::DIV3 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == DIV_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV5`"] + #[inline(always)] + pub fn is_div5(&self) -> bool { + **self == DIV_A::DIV5 + } + #[doc = "Checks if the value of the field is `DIV6`"] + #[inline(always)] + pub fn is_div6(&self) -> bool { + **self == DIV_A::DIV6 + } + #[doc = "Checks if the value of the field is `DIV7`"] + #[inline(always)] + pub fn is_div7(&self) -> bool { + **self == DIV_A::DIV7 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == DIV_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV9`"] + #[inline(always)] + pub fn is_div9(&self) -> bool { + **self == DIV_A::DIV9 + } + #[doc = "Checks if the value of the field is `DIV10`"] + #[inline(always)] + pub fn is_div10(&self) -> bool { + **self == DIV_A::DIV10 + } + #[doc = "Checks if the value of the field is `DIV11`"] + #[inline(always)] + pub fn is_div11(&self) -> bool { + **self == DIV_A::DIV11 + } + #[doc = "Checks if the value of the field is `DIV12`"] + #[inline(always)] + pub fn is_div12(&self) -> bool { + **self == DIV_A::DIV12 + } + #[doc = "Checks if the value of the field is `DIV13`"] + #[inline(always)] + pub fn is_div13(&self) -> bool { + **self == DIV_A::DIV13 + } + #[doc = "Checks if the value of the field is `DIV14`"] + #[inline(always)] + pub fn is_div14(&self) -> bool { + **self == DIV_A::DIV14 + } + #[doc = "Checks if the value of the field is `DIV15`"] + #[inline(always)] + pub fn is_div15(&self) -> bool { + **self == DIV_A::DIV15 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == DIV_A::DIV16 + } +} +impl core::ops::Deref for DIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIV` writer - OSC48M Division Factor"] +pub struct DIV_W<'a> { + w: &'a mut W, +} +impl<'a> DIV_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DIV_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "48 MHz"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(DIV_A::DIV1) + } + #[doc = "24 MHz"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(DIV_A::DIV2) + } + #[doc = "16 MHz"] + #[inline(always)] + pub fn div3(self) -> &'a mut W { + self.variant(DIV_A::DIV3) + } + #[doc = "12 MHz"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(DIV_A::DIV4) + } + #[doc = "9.6 MHz"] + #[inline(always)] + pub fn div5(self) -> &'a mut W { + self.variant(DIV_A::DIV5) + } + #[doc = "8 MHz"] + #[inline(always)] + pub fn div6(self) -> &'a mut W { + self.variant(DIV_A::DIV6) + } + #[doc = "6.86 MHz"] + #[inline(always)] + pub fn div7(self) -> &'a mut W { + self.variant(DIV_A::DIV7) + } + #[doc = "6 MHz"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(DIV_A::DIV8) + } + #[doc = "5.33 MHz"] + #[inline(always)] + pub fn div9(self) -> &'a mut W { + self.variant(DIV_A::DIV9) + } + #[doc = "4.8 MHz"] + #[inline(always)] + pub fn div10(self) -> &'a mut W { + self.variant(DIV_A::DIV10) + } + #[doc = "4.36 MHz"] + #[inline(always)] + pub fn div11(self) -> &'a mut W { + self.variant(DIV_A::DIV11) + } + #[doc = "4 MHz"] + #[inline(always)] + pub fn div12(self) -> &'a mut W { + self.variant(DIV_A::DIV12) + } + #[doc = "3.69 MHz"] + #[inline(always)] + pub fn div13(self) -> &'a mut W { + self.variant(DIV_A::DIV13) + } + #[doc = "3.43 MHz"] + #[inline(always)] + pub fn div14(self) -> &'a mut W { + self.variant(DIV_A::DIV14) + } + #[doc = "3.2 MHz"] + #[inline(always)] + pub fn div15(self) -> &'a mut W { + self.variant(DIV_A::DIV15) + } + #[doc = "3 MHz"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(DIV_A::DIV16) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - OSC48M Division Factor"] + #[inline(always)] + pub fn div(&self) -> DIV_R { + DIV_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - OSC48M Division Factor"] + #[inline(always)] + pub fn div(&mut self) -> DIV_W { + DIV_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OSC48M Divider\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [osc48mdiv](index.html) module"] +pub struct OSC48MDIV_SPEC; +impl crate::RegisterSpec for OSC48MDIV_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [osc48mdiv::R](R) reader structure"] +impl crate::Readable for OSC48MDIV_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [osc48mdiv::W](W) writer structure"] +impl crate::Writable for OSC48MDIV_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OSC48MDIV to value 0x0b"] +impl crate::Resettable for OSC48MDIV_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0b + } +} diff --git a/pac/atsamc20n/src/oscctrl/osc48mstup.rs b/pac/atsamc20n/src/oscctrl/osc48mstup.rs new file mode 100644 index 000000000000..34da6bb7ef11 --- /dev/null +++ b/pac/atsamc20n/src/oscctrl/osc48mstup.rs @@ -0,0 +1,230 @@ +#[doc = "Register `OSC48MSTUP` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OSC48MSTUP` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Startup Time\n\nValue on reset: 7"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum STARTUP_A { + #[doc = "0: 166 ns"] + CYCLE8 = 0, + #[doc = "1: 333 ns"] + CYCLE16 = 1, + #[doc = "2: 667 ns"] + CYCLE32 = 2, + #[doc = "3: 1.333 us"] + CYCLE64 = 3, + #[doc = "4: 2.667 us"] + CYCLE128 = 4, + #[doc = "5: 5.333 us"] + CYCLE256 = 5, + #[doc = "6: 10.667 us"] + CYCLE512 = 6, + #[doc = "7: 21.333 us"] + CYCLE1024 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: STARTUP_A) -> Self { + variant as _ + } +} +#[doc = "Field `STARTUP` reader - Startup Time"] +pub struct STARTUP_R(crate::FieldReader); +impl STARTUP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + STARTUP_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STARTUP_A { + match self.bits { + 0 => STARTUP_A::CYCLE8, + 1 => STARTUP_A::CYCLE16, + 2 => STARTUP_A::CYCLE32, + 3 => STARTUP_A::CYCLE64, + 4 => STARTUP_A::CYCLE128, + 5 => STARTUP_A::CYCLE256, + 6 => STARTUP_A::CYCLE512, + 7 => STARTUP_A::CYCLE1024, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `CYCLE8`"] + #[inline(always)] + pub fn is_cycle8(&self) -> bool { + **self == STARTUP_A::CYCLE8 + } + #[doc = "Checks if the value of the field is `CYCLE16`"] + #[inline(always)] + pub fn is_cycle16(&self) -> bool { + **self == STARTUP_A::CYCLE16 + } + #[doc = "Checks if the value of the field is `CYCLE32`"] + #[inline(always)] + pub fn is_cycle32(&self) -> bool { + **self == STARTUP_A::CYCLE32 + } + #[doc = "Checks if the value of the field is `CYCLE64`"] + #[inline(always)] + pub fn is_cycle64(&self) -> bool { + **self == STARTUP_A::CYCLE64 + } + #[doc = "Checks if the value of the field is `CYCLE128`"] + #[inline(always)] + pub fn is_cycle128(&self) -> bool { + **self == STARTUP_A::CYCLE128 + } + #[doc = "Checks if the value of the field is `CYCLE256`"] + #[inline(always)] + pub fn is_cycle256(&self) -> bool { + **self == STARTUP_A::CYCLE256 + } + #[doc = "Checks if the value of the field is `CYCLE512`"] + #[inline(always)] + pub fn is_cycle512(&self) -> bool { + **self == STARTUP_A::CYCLE512 + } + #[doc = "Checks if the value of the field is `CYCLE1024`"] + #[inline(always)] + pub fn is_cycle1024(&self) -> bool { + **self == STARTUP_A::CYCLE1024 + } +} +impl core::ops::Deref for STARTUP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STARTUP` writer - Startup Time"] +pub struct STARTUP_W<'a> { + w: &'a mut W, +} +impl<'a> STARTUP_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: STARTUP_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "166 ns"] + #[inline(always)] + pub fn cycle8(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE8) + } + #[doc = "333 ns"] + #[inline(always)] + pub fn cycle16(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE16) + } + #[doc = "667 ns"] + #[inline(always)] + pub fn cycle32(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE32) + } + #[doc = "1.333 us"] + #[inline(always)] + pub fn cycle64(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE64) + } + #[doc = "2.667 us"] + #[inline(always)] + pub fn cycle128(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE128) + } + #[doc = "5.333 us"] + #[inline(always)] + pub fn cycle256(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE256) + } + #[doc = "10.667 us"] + #[inline(always)] + pub fn cycle512(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE512) + } + #[doc = "21.333 us"] + #[inline(always)] + pub fn cycle1024(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Startup Time"] + #[inline(always)] + pub fn startup(&self) -> STARTUP_R { + STARTUP_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Startup Time"] + #[inline(always)] + pub fn startup(&mut self) -> STARTUP_W { + STARTUP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OSC48M Startup Time\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [osc48mstup](index.html) module"] +pub struct OSC48MSTUP_SPEC; +impl crate::RegisterSpec for OSC48MSTUP_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [osc48mstup::R](R) reader structure"] +impl crate::Readable for OSC48MSTUP_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [osc48mstup::W](W) writer structure"] +impl crate::Writable for OSC48MSTUP_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OSC48MSTUP to value 0x07"] +impl crate::Resettable for OSC48MSTUP_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x07 + } +} diff --git a/pac/atsamc20n/src/oscctrl/osc48msyncbusy.rs b/pac/atsamc20n/src/oscctrl/osc48msyncbusy.rs new file mode 100644 index 000000000000..8d4410ae630a --- /dev/null +++ b/pac/atsamc20n/src/oscctrl/osc48msyncbusy.rs @@ -0,0 +1,53 @@ +#[doc = "Register `OSC48MSYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `OSC48MDIV` reader - OSC48MDIV Synchronization Status"] +pub struct OSC48MDIV_R(crate::FieldReader); +impl OSC48MDIV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC48MDIV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC48MDIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 2 - OSC48MDIV Synchronization Status"] + #[inline(always)] + pub fn osc48mdiv(&self) -> OSC48MDIV_R { + OSC48MDIV_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +#[doc = "OSC48M Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [osc48msyncbusy](index.html) module"] +pub struct OSC48MSYNCBUSY_SPEC; +impl crate::RegisterSpec for OSC48MSYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [osc48msyncbusy::R](R) reader structure"] +impl crate::Readable for OSC48MSYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets OSC48MSYNCBUSY to value 0"] +impl crate::Resettable for OSC48MSYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/oscctrl/status.rs b/pac/atsamc20n/src/oscctrl/status.rs new file mode 100644 index 000000000000..3025966192a3 --- /dev/null +++ b/pac/atsamc20n/src/oscctrl/status.rs @@ -0,0 +1,193 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `XOSCRDY` reader - XOSC Ready"] +pub struct XOSCRDY_R(crate::FieldReader); +impl XOSCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSCFAIL` reader - XOSC Clock Failure Detector"] +pub struct XOSCFAIL_R(crate::FieldReader); +impl XOSCFAIL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSCFAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCFAIL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSCCKSW` reader - XOSC Clock Switch"] +pub struct XOSCCKSW_R(crate::FieldReader); +impl XOSCCKSW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSCCKSW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCCKSW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC48MRDY` reader - OSC48M Ready"] +pub struct OSC48MRDY_R(crate::FieldReader); +impl OSC48MRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC48MRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC48MRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKR` reader - DPLL Lock Rise"] +pub struct DPLLLCKR_R(crate::FieldReader); +impl DPLLLCKR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKF` reader - DPLL Lock Fall"] +pub struct DPLLLCKF_R(crate::FieldReader); +impl DPLLLCKF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLTO` reader - DPLL Timeout"] +pub struct DPLLTO_R(crate::FieldReader); +impl DPLLTO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLTO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLDRTO` reader - DPLL Ratio Ready"] +pub struct DPLLLDRTO_R(crate::FieldReader); +impl DPLLLDRTO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLDRTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLDRTO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - XOSC Ready"] + #[inline(always)] + pub fn xoscrdy(&self) -> XOSCRDY_R { + XOSCRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - XOSC Clock Failure Detector"] + #[inline(always)] + pub fn xoscfail(&self) -> XOSCFAIL_R { + XOSCFAIL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - XOSC Clock Switch"] + #[inline(always)] + pub fn xosccksw(&self) -> XOSCCKSW_R { + XOSCCKSW_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 4 - OSC48M Ready"] + #[inline(always)] + pub fn osc48mrdy(&self) -> OSC48MRDY_R { + OSC48MRDY_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 8 - DPLL Lock Rise"] + #[inline(always)] + pub fn dplllckr(&self) -> DPLLLCKR_R { + DPLLLCKR_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - DPLL Lock Fall"] + #[inline(always)] + pub fn dplllckf(&self) -> DPLLLCKF_R { + DPLLLCKF_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - DPLL Timeout"] + #[inline(always)] + pub fn dpllto(&self) -> DPLLTO_R { + DPLLTO_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - DPLL Ratio Ready"] + #[inline(always)] + pub fn dpllldrto(&self) -> DPLLLDRTO_R { + DPLLLDRTO_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +#[doc = "Power and Clocks Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/oscctrl/xoscctrl.rs b/pac/atsamc20n/src/oscctrl/xoscctrl.rs new file mode 100644 index 000000000000..3a5319565c10 --- /dev/null +++ b/pac/atsamc20n/src/oscctrl/xoscctrl.rs @@ -0,0 +1,788 @@ +#[doc = "Register `XOSCCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `XOSCCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Oscillator Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Oscillator Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `XTALEN` reader - Crystal Oscillator Enable"] +pub struct XTALEN_R(crate::FieldReader); +impl XTALEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XTALEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XTALEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XTALEN` writer - Crystal Oscillator Enable"] +pub struct XTALEN_W<'a> { + w: &'a mut W, +} +impl<'a> XTALEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CFDEN` reader - Xosc Clock Failure Detector Enable"] +pub struct CFDEN_R(crate::FieldReader); +impl CFDEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFDEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFDEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFDEN` writer - Xosc Clock Failure Detector Enable"] +pub struct CFDEN_W<'a> { + w: &'a mut W, +} +impl<'a> CFDEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `SWBEN` reader - Xosc Clock Switch Enable"] +pub struct SWBEN_R(crate::FieldReader); +impl SWBEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWBEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWBEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWBEN` writer - Xosc Clock Switch Enable"] +pub struct SWBEN_W<'a> { + w: &'a mut W, +} +impl<'a> SWBEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - On Demand Control"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - On Demand Control"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Oscillator Gain\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum GAIN_A { + #[doc = "0: 2 MHz"] + GAIN2 = 0, + #[doc = "1: 4 MHz"] + GAIN4 = 1, + #[doc = "2: 8 MHz"] + GAIN8 = 2, + #[doc = "3: 16 MHz"] + GAIN16 = 3, + #[doc = "4: 30 MHz"] + GAIN30 = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: GAIN_A) -> Self { + variant as _ + } +} +#[doc = "Field `GAIN` reader - Oscillator Gain"] +pub struct GAIN_R(crate::FieldReader); +impl GAIN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + GAIN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(GAIN_A::GAIN2), + 1 => Some(GAIN_A::GAIN4), + 2 => Some(GAIN_A::GAIN8), + 3 => Some(GAIN_A::GAIN16), + 4 => Some(GAIN_A::GAIN30), + _ => None, + } + } + #[doc = "Checks if the value of the field is `GAIN2`"] + #[inline(always)] + pub fn is_gain2(&self) -> bool { + **self == GAIN_A::GAIN2 + } + #[doc = "Checks if the value of the field is `GAIN4`"] + #[inline(always)] + pub fn is_gain4(&self) -> bool { + **self == GAIN_A::GAIN4 + } + #[doc = "Checks if the value of the field is `GAIN8`"] + #[inline(always)] + pub fn is_gain8(&self) -> bool { + **self == GAIN_A::GAIN8 + } + #[doc = "Checks if the value of the field is `GAIN16`"] + #[inline(always)] + pub fn is_gain16(&self) -> bool { + **self == GAIN_A::GAIN16 + } + #[doc = "Checks if the value of the field is `GAIN30`"] + #[inline(always)] + pub fn is_gain30(&self) -> bool { + **self == GAIN_A::GAIN30 + } +} +impl core::ops::Deref for GAIN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GAIN` writer - Oscillator Gain"] +pub struct GAIN_W<'a> { + w: &'a mut W, +} +impl<'a> GAIN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: GAIN_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "2 MHz"] + #[inline(always)] + pub fn gain2(self) -> &'a mut W { + self.variant(GAIN_A::GAIN2) + } + #[doc = "4 MHz"] + #[inline(always)] + pub fn gain4(self) -> &'a mut W { + self.variant(GAIN_A::GAIN4) + } + #[doc = "8 MHz"] + #[inline(always)] + pub fn gain8(self) -> &'a mut W { + self.variant(GAIN_A::GAIN8) + } + #[doc = "16 MHz"] + #[inline(always)] + pub fn gain16(self) -> &'a mut W { + self.variant(GAIN_A::GAIN16) + } + #[doc = "30 MHz"] + #[inline(always)] + pub fn gain30(self) -> &'a mut W { + self.variant(GAIN_A::GAIN30) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u16 & 0x07) << 8); + self.w + } +} +#[doc = "Field `AMPGC` reader - Automatic Amplitude Gain Control"] +pub struct AMPGC_R(crate::FieldReader); +impl AMPGC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AMPGC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AMPGC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AMPGC` writer - Automatic Amplitude Gain Control"] +pub struct AMPGC_W<'a> { + w: &'a mut W, +} +impl<'a> AMPGC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u16 & 0x01) << 11); + self.w + } +} +#[doc = "Start-Up Time\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum STARTUP_A { + #[doc = "0: 31 us"] + CYCLE1 = 0, + #[doc = "1: 61 us"] + CYCLE2 = 1, + #[doc = "2: 122 us"] + CYCLE4 = 2, + #[doc = "3: 244 us"] + CYCLE8 = 3, + #[doc = "4: 488 us"] + CYCLE16 = 4, + #[doc = "5: 977 us"] + CYCLE32 = 5, + #[doc = "6: 1953 us"] + CYCLE64 = 6, + #[doc = "7: 3906 us"] + CYCLE128 = 7, + #[doc = "8: 7813 us"] + CYCLE256 = 8, + #[doc = "9: 15625 us"] + CYCLE512 = 9, + #[doc = "10: 31250 us"] + CYCLE1024 = 10, + #[doc = "11: 62500 us"] + CYCLE2048 = 11, + #[doc = "12: 125000 us"] + CYCLE4096 = 12, + #[doc = "13: 250000 us"] + CYCLE8192 = 13, + #[doc = "14: 500000 us"] + CYCLE16384 = 14, + #[doc = "15: 1000000 us"] + CYCLE32768 = 15, +} +impl From for u8 { + #[inline(always)] + fn from(variant: STARTUP_A) -> Self { + variant as _ + } +} +#[doc = "Field `STARTUP` reader - Start-Up Time"] +pub struct STARTUP_R(crate::FieldReader); +impl STARTUP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + STARTUP_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STARTUP_A { + match self.bits { + 0 => STARTUP_A::CYCLE1, + 1 => STARTUP_A::CYCLE2, + 2 => STARTUP_A::CYCLE4, + 3 => STARTUP_A::CYCLE8, + 4 => STARTUP_A::CYCLE16, + 5 => STARTUP_A::CYCLE32, + 6 => STARTUP_A::CYCLE64, + 7 => STARTUP_A::CYCLE128, + 8 => STARTUP_A::CYCLE256, + 9 => STARTUP_A::CYCLE512, + 10 => STARTUP_A::CYCLE1024, + 11 => STARTUP_A::CYCLE2048, + 12 => STARTUP_A::CYCLE4096, + 13 => STARTUP_A::CYCLE8192, + 14 => STARTUP_A::CYCLE16384, + 15 => STARTUP_A::CYCLE32768, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `CYCLE1`"] + #[inline(always)] + pub fn is_cycle1(&self) -> bool { + **self == STARTUP_A::CYCLE1 + } + #[doc = "Checks if the value of the field is `CYCLE2`"] + #[inline(always)] + pub fn is_cycle2(&self) -> bool { + **self == STARTUP_A::CYCLE2 + } + #[doc = "Checks if the value of the field is `CYCLE4`"] + #[inline(always)] + pub fn is_cycle4(&self) -> bool { + **self == STARTUP_A::CYCLE4 + } + #[doc = "Checks if the value of the field is `CYCLE8`"] + #[inline(always)] + pub fn is_cycle8(&self) -> bool { + **self == STARTUP_A::CYCLE8 + } + #[doc = "Checks if the value of the field is `CYCLE16`"] + #[inline(always)] + pub fn is_cycle16(&self) -> bool { + **self == STARTUP_A::CYCLE16 + } + #[doc = "Checks if the value of the field is `CYCLE32`"] + #[inline(always)] + pub fn is_cycle32(&self) -> bool { + **self == STARTUP_A::CYCLE32 + } + #[doc = "Checks if the value of the field is `CYCLE64`"] + #[inline(always)] + pub fn is_cycle64(&self) -> bool { + **self == STARTUP_A::CYCLE64 + } + #[doc = "Checks if the value of the field is `CYCLE128`"] + #[inline(always)] + pub fn is_cycle128(&self) -> bool { + **self == STARTUP_A::CYCLE128 + } + #[doc = "Checks if the value of the field is `CYCLE256`"] + #[inline(always)] + pub fn is_cycle256(&self) -> bool { + **self == STARTUP_A::CYCLE256 + } + #[doc = "Checks if the value of the field is `CYCLE512`"] + #[inline(always)] + pub fn is_cycle512(&self) -> bool { + **self == STARTUP_A::CYCLE512 + } + #[doc = "Checks if the value of the field is `CYCLE1024`"] + #[inline(always)] + pub fn is_cycle1024(&self) -> bool { + **self == STARTUP_A::CYCLE1024 + } + #[doc = "Checks if the value of the field is `CYCLE2048`"] + #[inline(always)] + pub fn is_cycle2048(&self) -> bool { + **self == STARTUP_A::CYCLE2048 + } + #[doc = "Checks if the value of the field is `CYCLE4096`"] + #[inline(always)] + pub fn is_cycle4096(&self) -> bool { + **self == STARTUP_A::CYCLE4096 + } + #[doc = "Checks if the value of the field is `CYCLE8192`"] + #[inline(always)] + pub fn is_cycle8192(&self) -> bool { + **self == STARTUP_A::CYCLE8192 + } + #[doc = "Checks if the value of the field is `CYCLE16384`"] + #[inline(always)] + pub fn is_cycle16384(&self) -> bool { + **self == STARTUP_A::CYCLE16384 + } + #[doc = "Checks if the value of the field is `CYCLE32768`"] + #[inline(always)] + pub fn is_cycle32768(&self) -> bool { + **self == STARTUP_A::CYCLE32768 + } +} +impl core::ops::Deref for STARTUP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STARTUP` writer - Start-Up Time"] +pub struct STARTUP_W<'a> { + w: &'a mut W, +} +impl<'a> STARTUP_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: STARTUP_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "31 us"] + #[inline(always)] + pub fn cycle1(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE1) + } + #[doc = "61 us"] + #[inline(always)] + pub fn cycle2(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE2) + } + #[doc = "122 us"] + #[inline(always)] + pub fn cycle4(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE4) + } + #[doc = "244 us"] + #[inline(always)] + pub fn cycle8(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE8) + } + #[doc = "488 us"] + #[inline(always)] + pub fn cycle16(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE16) + } + #[doc = "977 us"] + #[inline(always)] + pub fn cycle32(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE32) + } + #[doc = "1953 us"] + #[inline(always)] + pub fn cycle64(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE64) + } + #[doc = "3906 us"] + #[inline(always)] + pub fn cycle128(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE128) + } + #[doc = "7813 us"] + #[inline(always)] + pub fn cycle256(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE256) + } + #[doc = "15625 us"] + #[inline(always)] + pub fn cycle512(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE512) + } + #[doc = "31250 us"] + #[inline(always)] + pub fn cycle1024(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE1024) + } + #[doc = "62500 us"] + #[inline(always)] + pub fn cycle2048(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE2048) + } + #[doc = "125000 us"] + #[inline(always)] + pub fn cycle4096(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE4096) + } + #[doc = "250000 us"] + #[inline(always)] + pub fn cycle8192(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE8192) + } + #[doc = "500000 us"] + #[inline(always)] + pub fn cycle16384(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE16384) + } + #[doc = "1000000 us"] + #[inline(always)] + pub fn cycle32768(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE32768) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 12)) | ((value as u16 & 0x0f) << 12); + self.w + } +} +impl R { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Crystal Oscillator Enable"] + #[inline(always)] + pub fn xtalen(&self) -> XTALEN_R { + XTALEN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Xosc Clock Failure Detector Enable"] + #[inline(always)] + pub fn cfden(&self) -> CFDEN_R { + CFDEN_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Xosc Clock Switch Enable"] + #[inline(always)] + pub fn swben(&self) -> SWBEN_R { + SWBEN_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Oscillator Gain"] + #[inline(always)] + pub fn gain(&self) -> GAIN_R { + GAIN_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 11 - Automatic Amplitude Gain Control"] + #[inline(always)] + pub fn ampgc(&self) -> AMPGC_R { + AMPGC_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bits 12:15 - Start-Up Time"] + #[inline(always)] + pub fn startup(&self) -> STARTUP_R { + STARTUP_R::new(((self.bits >> 12) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - Crystal Oscillator Enable"] + #[inline(always)] + pub fn xtalen(&mut self) -> XTALEN_W { + XTALEN_W { w: self } + } + #[doc = "Bit 3 - Xosc Clock Failure Detector Enable"] + #[inline(always)] + pub fn cfden(&mut self) -> CFDEN_W { + CFDEN_W { w: self } + } + #[doc = "Bit 4 - Xosc Clock Switch Enable"] + #[inline(always)] + pub fn swben(&mut self) -> SWBEN_W { + SWBEN_W { w: self } + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Bits 8:10 - Oscillator Gain"] + #[inline(always)] + pub fn gain(&mut self) -> GAIN_W { + GAIN_W { w: self } + } + #[doc = "Bit 11 - Automatic Amplitude Gain Control"] + #[inline(always)] + pub fn ampgc(&mut self) -> AMPGC_W { + AMPGC_W { w: self } + } + #[doc = "Bits 12:15 - Start-Up Time"] + #[inline(always)] + pub fn startup(&mut self) -> STARTUP_W { + STARTUP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "External Multipurpose Crystal Oscillator (XOSC) Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [xoscctrl](index.html) module"] +pub struct XOSCCTRL_SPEC; +impl crate::RegisterSpec for XOSCCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [xoscctrl::R](R) reader structure"] +impl crate::Readable for XOSCCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [xoscctrl::W](W) writer structure"] +impl crate::Writable for XOSCCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets XOSCCTRL to value 0x80"] +impl crate::Resettable for XOSCCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x80 + } +} diff --git a/pac/atsamc20n/src/pac.rs b/pac/atsamc20n/src/pac.rs new file mode 100644 index 000000000000..6510f73b90c1 --- /dev/null +++ b/pac/atsamc20n/src/pac.rs @@ -0,0 +1,85 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Write control"] + pub wrctrl: crate::Reg, + #[doc = "0x04 - Event control"] + pub evctrl: crate::Reg, + _reserved2: [u8; 0x03], + #[doc = "0x08 - Interrupt enable clear"] + pub intenclr: crate::Reg, + #[doc = "0x09 - Interrupt enable set"] + pub intenset: crate::Reg, + _reserved4: [u8; 0x06], + #[doc = "0x10 - Bridge interrupt flag status"] + pub intflagahb: crate::Reg, + #[doc = "0x14 - Peripheral interrupt flag status - Bridge A"] + pub intflaga: crate::Reg, + #[doc = "0x18 - Peripheral interrupt flag status - Bridge B"] + pub intflagb: crate::Reg, + #[doc = "0x1c - Peripheral interrupt flag status - Bridge C"] + pub intflagc: crate::Reg, + #[doc = "0x20 - Peripheral interrupt flag status - Bridge D"] + pub intflagd: crate::Reg, + _reserved9: [u8; 0x10], + #[doc = "0x34 - Peripheral write protection status - Bridge A"] + pub statusa: crate::Reg, + #[doc = "0x38 - Peripheral write protection status - Bridge B"] + pub statusb: crate::Reg, + #[doc = "0x3c - Peripheral write protection status - Bridge C"] + pub statusc: crate::Reg, + #[doc = "0x40 - Peripheral write protection status - Bridge D"] + pub statusd: crate::Reg, +} +#[doc = "WRCTRL register accessor: an alias for `Reg`"] +pub type WRCTRL = crate::Reg; +#[doc = "Write control"] +pub mod wrctrl; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt enable clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt enable set"] +pub mod intenset; +#[doc = "INTFLAGAHB register accessor: an alias for `Reg`"] +pub type INTFLAGAHB = crate::Reg; +#[doc = "Bridge interrupt flag status"] +pub mod intflagahb; +#[doc = "INTFLAGA register accessor: an alias for `Reg`"] +pub type INTFLAGA = crate::Reg; +#[doc = "Peripheral interrupt flag status - Bridge A"] +pub mod intflaga; +#[doc = "INTFLAGB register accessor: an alias for `Reg`"] +pub type INTFLAGB = crate::Reg; +#[doc = "Peripheral interrupt flag status - Bridge B"] +pub mod intflagb; +#[doc = "INTFLAGC register accessor: an alias for `Reg`"] +pub type INTFLAGC = crate::Reg; +#[doc = "Peripheral interrupt flag status - Bridge C"] +pub mod intflagc; +#[doc = "INTFLAGD register accessor: an alias for `Reg`"] +pub type INTFLAGD = crate::Reg; +#[doc = "Peripheral interrupt flag status - Bridge D"] +pub mod intflagd; +#[doc = "STATUSA register accessor: an alias for `Reg`"] +pub type STATUSA = crate::Reg; +#[doc = "Peripheral write protection status - Bridge A"] +pub mod statusa; +#[doc = "STATUSB register accessor: an alias for `Reg`"] +pub type STATUSB = crate::Reg; +#[doc = "Peripheral write protection status - Bridge B"] +pub mod statusb; +#[doc = "STATUSC register accessor: an alias for `Reg`"] +pub type STATUSC = crate::Reg; +#[doc = "Peripheral write protection status - Bridge C"] +pub mod statusc; +#[doc = "STATUSD register accessor: an alias for `Reg`"] +pub type STATUSD = crate::Reg; +#[doc = "Peripheral write protection status - Bridge D"] +pub mod statusd; diff --git a/pac/atsamc20n/src/pac/evctrl.rs b/pac/atsamc20n/src/pac/evctrl.rs new file mode 100644 index 000000000000..630581b98c85 --- /dev/null +++ b/pac/atsamc20n/src/pac/evctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ERREO` reader - Peripheral acess error event output"] +pub struct ERREO_R(crate::FieldReader); +impl ERREO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERREO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERREO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERREO` writer - Peripheral acess error event output"] +pub struct ERREO_W<'a> { + w: &'a mut W, +} +impl<'a> ERREO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Peripheral acess error event output"] + #[inline(always)] + pub fn erreo(&self) -> ERREO_R { + ERREO_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Peripheral acess error event output"] + #[inline(always)] + pub fn erreo(&mut self) -> ERREO_W { + ERREO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/pac/intenclr.rs b/pac/atsamc20n/src/pac/intenclr.rs new file mode 100644 index 000000000000..609fe0fcf628 --- /dev/null +++ b/pac/atsamc20n/src/pac/intenclr.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ERR` reader - Peripheral access error interrupt disable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - Peripheral access error interrupt disable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Peripheral access error interrupt disable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Peripheral access error interrupt disable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt enable clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/pac/intenset.rs b/pac/atsamc20n/src/pac/intenset.rs new file mode 100644 index 000000000000..390545b588de --- /dev/null +++ b/pac/atsamc20n/src/pac/intenset.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ERR` reader - Peripheral access error interrupt enable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - Peripheral access error interrupt enable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Peripheral access error interrupt enable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Peripheral access error interrupt enable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt enable set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/pac/intflaga.rs b/pac/atsamc20n/src/pac/intflaga.rs new file mode 100644 index 000000000000..df4c8554d9ab --- /dev/null +++ b/pac/atsamc20n/src/pac/intflaga.rs @@ -0,0 +1,630 @@ +#[doc = "Register `INTFLAGA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAGA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PAC_` reader - PAC"] +pub struct PAC__R(crate::FieldReader); +impl PAC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PAC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PAC_` writer - PAC"] +pub struct PAC__W<'a> { + w: &'a mut W, +} +impl<'a> PAC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `PM_` reader - PM"] +pub struct PM__R(crate::FieldReader); +impl PM__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PM__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PM__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PM_` writer - PM"] +pub struct PM__W<'a> { + w: &'a mut W, +} +impl<'a> PM__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MCLK_` reader - MCLK"] +pub struct MCLK__R(crate::FieldReader); +impl MCLK__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCLK__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCLK__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCLK_` writer - MCLK"] +pub struct MCLK__W<'a> { + w: &'a mut W, +} +impl<'a> MCLK__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RSTC_` reader - RSTC"] +pub struct RSTC__R(crate::FieldReader); +impl RSTC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RSTC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RSTC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RSTC_` writer - RSTC"] +pub struct RSTC__W<'a> { + w: &'a mut W, +} +impl<'a> RSTC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `OSCCTRL_` reader - OSCCTRL"] +pub struct OSCCTRL__R(crate::FieldReader); +impl OSCCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSCCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSCCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSCCTRL_` writer - OSCCTRL"] +pub struct OSCCTRL__W<'a> { + w: &'a mut W, +} +impl<'a> OSCCTRL__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `OSC32KCTRL_` reader - OSC32KCTRL"] +pub struct OSC32KCTRL__R(crate::FieldReader); +impl OSC32KCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC32KCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC32KCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC32KCTRL_` writer - OSC32KCTRL"] +pub struct OSC32KCTRL__W<'a> { + w: &'a mut W, +} +impl<'a> OSC32KCTRL__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `SUPC_` reader - SUPC"] +pub struct SUPC__R(crate::FieldReader); +impl SUPC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SUPC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SUPC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SUPC_` writer - SUPC"] +pub struct SUPC__W<'a> { + w: &'a mut W, +} +impl<'a> SUPC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `GCLK_` reader - GCLK"] +pub struct GCLK__R(crate::FieldReader); +impl GCLK__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GCLK__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GCLK__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GCLK_` writer - GCLK"] +pub struct GCLK__W<'a> { + w: &'a mut W, +} +impl<'a> GCLK__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `WDT_` reader - WDT"] +pub struct WDT__R(crate::FieldReader); +impl WDT__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WDT__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WDT__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WDT_` writer - WDT"] +pub struct WDT__W<'a> { + w: &'a mut W, +} +impl<'a> WDT__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `RTC_` reader - RTC"] +pub struct RTC__R(crate::FieldReader); +impl RTC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RTC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RTC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RTC_` writer - RTC"] +pub struct RTC__W<'a> { + w: &'a mut W, +} +impl<'a> RTC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `EIC_` reader - EIC"] +pub struct EIC__R(crate::FieldReader); +impl EIC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EIC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EIC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EIC_` writer - EIC"] +pub struct EIC__W<'a> { + w: &'a mut W, +} +impl<'a> EIC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `FREQM_` reader - FREQM"] +pub struct FREQM__R(crate::FieldReader); +impl FREQM__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FREQM__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FREQM__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FREQM_` writer - FREQM"] +pub struct FREQM__W<'a> { + w: &'a mut W, +} +impl<'a> FREQM__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +impl R { + #[doc = "Bit 0 - PAC"] + #[inline(always)] + pub fn pac_(&self) -> PAC__R { + PAC__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - PM"] + #[inline(always)] + pub fn pm_(&self) -> PM__R { + PM__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - MCLK"] + #[inline(always)] + pub fn mclk_(&self) -> MCLK__R { + MCLK__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - RSTC"] + #[inline(always)] + pub fn rstc_(&self) -> RSTC__R { + RSTC__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - OSCCTRL"] + #[inline(always)] + pub fn oscctrl_(&self) -> OSCCTRL__R { + OSCCTRL__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - OSC32KCTRL"] + #[inline(always)] + pub fn osc32kctrl_(&self) -> OSC32KCTRL__R { + OSC32KCTRL__R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - SUPC"] + #[inline(always)] + pub fn supc_(&self) -> SUPC__R { + SUPC__R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - GCLK"] + #[inline(always)] + pub fn gclk_(&self) -> GCLK__R { + GCLK__R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - WDT"] + #[inline(always)] + pub fn wdt_(&self) -> WDT__R { + WDT__R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - RTC"] + #[inline(always)] + pub fn rtc_(&self) -> RTC__R { + RTC__R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - EIC"] + #[inline(always)] + pub fn eic_(&self) -> EIC__R { + EIC__R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - FREQM"] + #[inline(always)] + pub fn freqm_(&self) -> FREQM__R { + FREQM__R::new(((self.bits >> 11) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - PAC"] + #[inline(always)] + pub fn pac_(&mut self) -> PAC__W { + PAC__W { w: self } + } + #[doc = "Bit 1 - PM"] + #[inline(always)] + pub fn pm_(&mut self) -> PM__W { + PM__W { w: self } + } + #[doc = "Bit 2 - MCLK"] + #[inline(always)] + pub fn mclk_(&mut self) -> MCLK__W { + MCLK__W { w: self } + } + #[doc = "Bit 3 - RSTC"] + #[inline(always)] + pub fn rstc_(&mut self) -> RSTC__W { + RSTC__W { w: self } + } + #[doc = "Bit 4 - OSCCTRL"] + #[inline(always)] + pub fn oscctrl_(&mut self) -> OSCCTRL__W { + OSCCTRL__W { w: self } + } + #[doc = "Bit 5 - OSC32KCTRL"] + #[inline(always)] + pub fn osc32kctrl_(&mut self) -> OSC32KCTRL__W { + OSC32KCTRL__W { w: self } + } + #[doc = "Bit 6 - SUPC"] + #[inline(always)] + pub fn supc_(&mut self) -> SUPC__W { + SUPC__W { w: self } + } + #[doc = "Bit 7 - GCLK"] + #[inline(always)] + pub fn gclk_(&mut self) -> GCLK__W { + GCLK__W { w: self } + } + #[doc = "Bit 8 - WDT"] + #[inline(always)] + pub fn wdt_(&mut self) -> WDT__W { + WDT__W { w: self } + } + #[doc = "Bit 9 - RTC"] + #[inline(always)] + pub fn rtc_(&mut self) -> RTC__W { + RTC__W { w: self } + } + #[doc = "Bit 10 - EIC"] + #[inline(always)] + pub fn eic_(&mut self) -> EIC__W { + EIC__W { w: self } + } + #[doc = "Bit 11 - FREQM"] + #[inline(always)] + pub fn freqm_(&mut self) -> FREQM__W { + FREQM__W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Peripheral interrupt flag status - Bridge A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflaga](index.html) module"] +pub struct INTFLAGA_SPEC; +impl crate::RegisterSpec for INTFLAGA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflaga::R](R) reader structure"] +impl crate::Readable for INTFLAGA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflaga::W](W) writer structure"] +impl crate::Writable for INTFLAGA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAGA to value 0"] +impl crate::Resettable for INTFLAGA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/pac/intflagahb.rs b/pac/atsamc20n/src/pac/intflagahb.rs new file mode 100644 index 000000000000..72fe915eb008 --- /dev/null +++ b/pac/atsamc20n/src/pac/intflagahb.rs @@ -0,0 +1,489 @@ +#[doc = "Register `INTFLAGAHB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAGAHB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FLASH_` reader - FLASH"] +pub struct FLASH__R(crate::FieldReader); +impl FLASH__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FLASH__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FLASH__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLASH_` writer - FLASH"] +pub struct FLASH__W<'a> { + w: &'a mut W, +} +impl<'a> FLASH__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `HSRAMCM0P_` reader - HSRAMCM0P"] +pub struct HSRAMCM0P__R(crate::FieldReader); +impl HSRAMCM0P__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HSRAMCM0P__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HSRAMCM0P__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HSRAMCM0P_` writer - HSRAMCM0P"] +pub struct HSRAMCM0P__W<'a> { + w: &'a mut W, +} +impl<'a> HSRAMCM0P__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `HSRAMDSU_` reader - HSRAMDSU"] +pub struct HSRAMDSU__R(crate::FieldReader); +impl HSRAMDSU__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HSRAMDSU__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HSRAMDSU__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HSRAMDSU_` writer - HSRAMDSU"] +pub struct HSRAMDSU__W<'a> { + w: &'a mut W, +} +impl<'a> HSRAMDSU__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `HPB1_` reader - HPB1"] +pub struct HPB1__R(crate::FieldReader); +impl HPB1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HPB1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HPB1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HPB1_` writer - HPB1"] +pub struct HPB1__W<'a> { + w: &'a mut W, +} +impl<'a> HPB1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `HPB0_` reader - HPB0"] +pub struct HPB0__R(crate::FieldReader); +impl HPB0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HPB0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HPB0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HPB0_` writer - HPB0"] +pub struct HPB0__W<'a> { + w: &'a mut W, +} +impl<'a> HPB0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `HPB2_` reader - HPB2"] +pub struct HPB2__R(crate::FieldReader); +impl HPB2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HPB2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HPB2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HPB2_` writer - HPB2"] +pub struct HPB2__W<'a> { + w: &'a mut W, +} +impl<'a> HPB2__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `LPRAMDMAC_` reader - LPRAMDMAC"] +pub struct LPRAMDMAC__R(crate::FieldReader); +impl LPRAMDMAC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LPRAMDMAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LPRAMDMAC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LPRAMDMAC_` writer - LPRAMDMAC"] +pub struct LPRAMDMAC__W<'a> { + w: &'a mut W, +} +impl<'a> LPRAMDMAC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `DIVAS_` reader - DIVAS"] +pub struct DIVAS__R(crate::FieldReader); +impl DIVAS__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIVAS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIVAS__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIVAS_` writer - DIVAS"] +pub struct DIVAS__W<'a> { + w: &'a mut W, +} +impl<'a> DIVAS__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `HPB3_` reader - HPB3"] +pub struct HPB3__R(crate::FieldReader); +impl HPB3__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HPB3__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HPB3__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HPB3_` writer - HPB3"] +pub struct HPB3__W<'a> { + w: &'a mut W, +} +impl<'a> HPB3__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +impl R { + #[doc = "Bit 0 - FLASH"] + #[inline(always)] + pub fn flash_(&self) -> FLASH__R { + FLASH__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - HSRAMCM0P"] + #[inline(always)] + pub fn hsramcm0p_(&self) -> HSRAMCM0P__R { + HSRAMCM0P__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - HSRAMDSU"] + #[inline(always)] + pub fn hsramdsu_(&self) -> HSRAMDSU__R { + HSRAMDSU__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - HPB1"] + #[inline(always)] + pub fn hpb1_(&self) -> HPB1__R { + HPB1__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - HPB0"] + #[inline(always)] + pub fn hpb0_(&self) -> HPB0__R { + HPB0__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - HPB2"] + #[inline(always)] + pub fn hpb2_(&self) -> HPB2__R { + HPB2__R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - LPRAMDMAC"] + #[inline(always)] + pub fn lpramdmac_(&self) -> LPRAMDMAC__R { + LPRAMDMAC__R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - DIVAS"] + #[inline(always)] + pub fn divas_(&self) -> DIVAS__R { + DIVAS__R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - HPB3"] + #[inline(always)] + pub fn hpb3_(&self) -> HPB3__R { + HPB3__R::new(((self.bits >> 8) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - FLASH"] + #[inline(always)] + pub fn flash_(&mut self) -> FLASH__W { + FLASH__W { w: self } + } + #[doc = "Bit 1 - HSRAMCM0P"] + #[inline(always)] + pub fn hsramcm0p_(&mut self) -> HSRAMCM0P__W { + HSRAMCM0P__W { w: self } + } + #[doc = "Bit 2 - HSRAMDSU"] + #[inline(always)] + pub fn hsramdsu_(&mut self) -> HSRAMDSU__W { + HSRAMDSU__W { w: self } + } + #[doc = "Bit 3 - HPB1"] + #[inline(always)] + pub fn hpb1_(&mut self) -> HPB1__W { + HPB1__W { w: self } + } + #[doc = "Bit 4 - HPB0"] + #[inline(always)] + pub fn hpb0_(&mut self) -> HPB0__W { + HPB0__W { w: self } + } + #[doc = "Bit 5 - HPB2"] + #[inline(always)] + pub fn hpb2_(&mut self) -> HPB2__W { + HPB2__W { w: self } + } + #[doc = "Bit 6 - LPRAMDMAC"] + #[inline(always)] + pub fn lpramdmac_(&mut self) -> LPRAMDMAC__W { + LPRAMDMAC__W { w: self } + } + #[doc = "Bit 7 - DIVAS"] + #[inline(always)] + pub fn divas_(&mut self) -> DIVAS__W { + DIVAS__W { w: self } + } + #[doc = "Bit 8 - HPB3"] + #[inline(always)] + pub fn hpb3_(&mut self) -> HPB3__W { + HPB3__W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Bridge interrupt flag status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflagahb](index.html) module"] +pub struct INTFLAGAHB_SPEC; +impl crate::RegisterSpec for INTFLAGAHB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflagahb::R](R) reader structure"] +impl crate::Readable for INTFLAGAHB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflagahb::W](W) writer structure"] +impl crate::Writable for INTFLAGAHB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAGAHB to value 0"] +impl crate::Resettable for INTFLAGAHB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/pac/intflagb.rs b/pac/atsamc20n/src/pac/intflagb.rs new file mode 100644 index 000000000000..8359f7e11f30 --- /dev/null +++ b/pac/atsamc20n/src/pac/intflagb.rs @@ -0,0 +1,348 @@ +#[doc = "Register `INTFLAGB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAGB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PORT_` reader - PORT"] +pub struct PORT__R(crate::FieldReader); +impl PORT__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PORT__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PORT__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PORT_` writer - PORT"] +pub struct PORT__W<'a> { + w: &'a mut W, +} +impl<'a> PORT__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `DSU_` reader - DSU"] +pub struct DSU__R(crate::FieldReader); +impl DSU__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DSU__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DSU__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DSU_` writer - DSU"] +pub struct DSU__W<'a> { + w: &'a mut W, +} +impl<'a> DSU__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `NVMCTRL_` reader - NVMCTRL"] +pub struct NVMCTRL__R(crate::FieldReader); +impl NVMCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NVMCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NVMCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NVMCTRL_` writer - NVMCTRL"] +pub struct NVMCTRL__W<'a> { + w: &'a mut W, +} +impl<'a> NVMCTRL__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `DMAC_` reader - DMAC"] +pub struct DMAC__R(crate::FieldReader); +impl DMAC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DMAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DMAC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DMAC_` writer - DMAC"] +pub struct DMAC__W<'a> { + w: &'a mut W, +} +impl<'a> DMAC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `MTB_` reader - MTB"] +pub struct MTB__R(crate::FieldReader); +impl MTB__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MTB__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MTB__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MTB_` writer - MTB"] +pub struct MTB__W<'a> { + w: &'a mut W, +} +impl<'a> MTB__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `HMATRIXHS_` reader - HMATRIXHS"] +pub struct HMATRIXHS__R(crate::FieldReader); +impl HMATRIXHS__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HMATRIXHS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HMATRIXHS__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HMATRIXHS_` writer - HMATRIXHS"] +pub struct HMATRIXHS__W<'a> { + w: &'a mut W, +} +impl<'a> HMATRIXHS__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - PORT"] + #[inline(always)] + pub fn port_(&self) -> PORT__R { + PORT__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - DSU"] + #[inline(always)] + pub fn dsu_(&self) -> DSU__R { + DSU__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - NVMCTRL"] + #[inline(always)] + pub fn nvmctrl_(&self) -> NVMCTRL__R { + NVMCTRL__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - DMAC"] + #[inline(always)] + pub fn dmac_(&self) -> DMAC__R { + DMAC__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - MTB"] + #[inline(always)] + pub fn mtb_(&self) -> MTB__R { + MTB__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - HMATRIXHS"] + #[inline(always)] + pub fn hmatrixhs_(&self) -> HMATRIXHS__R { + HMATRIXHS__R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - PORT"] + #[inline(always)] + pub fn port_(&mut self) -> PORT__W { + PORT__W { w: self } + } + #[doc = "Bit 1 - DSU"] + #[inline(always)] + pub fn dsu_(&mut self) -> DSU__W { + DSU__W { w: self } + } + #[doc = "Bit 2 - NVMCTRL"] + #[inline(always)] + pub fn nvmctrl_(&mut self) -> NVMCTRL__W { + NVMCTRL__W { w: self } + } + #[doc = "Bit 3 - DMAC"] + #[inline(always)] + pub fn dmac_(&mut self) -> DMAC__W { + DMAC__W { w: self } + } + #[doc = "Bit 4 - MTB"] + #[inline(always)] + pub fn mtb_(&mut self) -> MTB__W { + MTB__W { w: self } + } + #[doc = "Bit 5 - HMATRIXHS"] + #[inline(always)] + pub fn hmatrixhs_(&mut self) -> HMATRIXHS__W { + HMATRIXHS__W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Peripheral interrupt flag status - Bridge B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflagb](index.html) module"] +pub struct INTFLAGB_SPEC; +impl crate::RegisterSpec for INTFLAGB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflagb::R](R) reader structure"] +impl crate::Readable for INTFLAGB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflagb::W](W) writer structure"] +impl crate::Writable for INTFLAGB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAGB to value 0"] +impl crate::Resettable for INTFLAGB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/pac/intflagc.rs b/pac/atsamc20n/src/pac/intflagc.rs new file mode 100644 index 000000000000..f5b83d23881d --- /dev/null +++ b/pac/atsamc20n/src/pac/intflagc.rs @@ -0,0 +1,959 @@ +#[doc = "Register `INTFLAGC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAGC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVSYS_` reader - EVSYS"] +pub struct EVSYS__R(crate::FieldReader); +impl EVSYS__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVSYS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVSYS__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVSYS_` writer - EVSYS"] +pub struct EVSYS__W<'a> { + w: &'a mut W, +} +impl<'a> EVSYS__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `SERCOM0_` reader - SERCOM0"] +pub struct SERCOM0__R(crate::FieldReader); +impl SERCOM0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM0_` writer - SERCOM0"] +pub struct SERCOM0__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SERCOM1_` reader - SERCOM1"] +pub struct SERCOM1__R(crate::FieldReader); +impl SERCOM1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM1_` writer - SERCOM1"] +pub struct SERCOM1__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SERCOM2_` reader - SERCOM2"] +pub struct SERCOM2__R(crate::FieldReader); +impl SERCOM2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM2_` writer - SERCOM2"] +pub struct SERCOM2__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM2__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `SERCOM3_` reader - SERCOM3"] +pub struct SERCOM3__R(crate::FieldReader); +impl SERCOM3__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM3__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM3__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM3_` writer - SERCOM3"] +pub struct SERCOM3__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM3__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `SERCOM4_` reader - SERCOM4"] +pub struct SERCOM4__R(crate::FieldReader); +impl SERCOM4__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM4__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM4__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM4_` writer - SERCOM4"] +pub struct SERCOM4__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM4__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `SERCOM5_` reader - SERCOM5"] +pub struct SERCOM5__R(crate::FieldReader); +impl SERCOM5__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM5__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM5__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM5_` writer - SERCOM5"] +pub struct SERCOM5__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM5__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `TCC0_` reader - TCC0"] +pub struct TCC0__R(crate::FieldReader); +impl TCC0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCC0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCC0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCC0_` writer - TCC0"] +pub struct TCC0__W<'a> { + w: &'a mut W, +} +impl<'a> TCC0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `TCC1_` reader - TCC1"] +pub struct TCC1__R(crate::FieldReader); +impl TCC1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCC1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCC1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCC1_` writer - TCC1"] +pub struct TCC1__W<'a> { + w: &'a mut W, +} +impl<'a> TCC1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `TCC2_` reader - TCC2"] +pub struct TCC2__R(crate::FieldReader); +impl TCC2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCC2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCC2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCC2_` writer - TCC2"] +pub struct TCC2__W<'a> { + w: &'a mut W, +} +impl<'a> TCC2__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `TC0_` reader - TC0"] +pub struct TC0__R(crate::FieldReader); +impl TC0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC0_` writer - TC0"] +pub struct TC0__W<'a> { + w: &'a mut W, +} +impl<'a> TC0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `TC1_` reader - TC1"] +pub struct TC1__R(crate::FieldReader); +impl TC1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC1_` writer - TC1"] +pub struct TC1__W<'a> { + w: &'a mut W, +} +impl<'a> TC1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `TC2_` reader - TC2"] +pub struct TC2__R(crate::FieldReader); +impl TC2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC2_` writer - TC2"] +pub struct TC2__W<'a> { + w: &'a mut W, +} +impl<'a> TC2__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `TC3_` reader - TC3"] +pub struct TC3__R(crate::FieldReader); +impl TC3__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC3__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC3__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC3_` writer - TC3"] +pub struct TC3__W<'a> { + w: &'a mut W, +} +impl<'a> TC3__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `TC4_` reader - TC4"] +pub struct TC4__R(crate::FieldReader); +impl TC4__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC4__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC4__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC4_` writer - TC4"] +pub struct TC4__W<'a> { + w: &'a mut W, +} +impl<'a> TC4__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `ADC0_` reader - ADC0"] +pub struct ADC0__R(crate::FieldReader); +impl ADC0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ADC0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADC0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADC0_` writer - ADC0"] +pub struct ADC0__W<'a> { + w: &'a mut W, +} +impl<'a> ADC0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `AC_` reader - AC"] +pub struct AC__R(crate::FieldReader); +impl AC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AC_` writer - AC"] +pub struct AC__W<'a> { + w: &'a mut W, +} +impl<'a> AC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `PTC_` reader - PTC"] +pub struct PTC__R(crate::FieldReader); +impl PTC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PTC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PTC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PTC_` writer - PTC"] +pub struct PTC__W<'a> { + w: &'a mut W, +} +impl<'a> PTC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `CCL_` reader - CCL"] +pub struct CCL__R(crate::FieldReader); +impl CCL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCL_` writer - CCL"] +pub struct CCL__W<'a> { + w: &'a mut W, +} +impl<'a> CCL__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +impl R { + #[doc = "Bit 0 - EVSYS"] + #[inline(always)] + pub fn evsys_(&self) -> EVSYS__R { + EVSYS__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM0"] + #[inline(always)] + pub fn sercom0_(&self) -> SERCOM0__R { + SERCOM0__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - SERCOM1"] + #[inline(always)] + pub fn sercom1_(&self) -> SERCOM1__R { + SERCOM1__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - SERCOM2"] + #[inline(always)] + pub fn sercom2_(&self) -> SERCOM2__R { + SERCOM2__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - SERCOM3"] + #[inline(always)] + pub fn sercom3_(&self) -> SERCOM3__R { + SERCOM3__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - SERCOM4"] + #[inline(always)] + pub fn sercom4_(&self) -> SERCOM4__R { + SERCOM4__R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - SERCOM5"] + #[inline(always)] + pub fn sercom5_(&self) -> SERCOM5__R { + SERCOM5__R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 9 - TCC0"] + #[inline(always)] + pub fn tcc0_(&self) -> TCC0__R { + TCC0__R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - TCC1"] + #[inline(always)] + pub fn tcc1_(&self) -> TCC1__R { + TCC1__R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - TCC2"] + #[inline(always)] + pub fn tcc2_(&self) -> TCC2__R { + TCC2__R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - TC0"] + #[inline(always)] + pub fn tc0_(&self) -> TC0__R { + TC0__R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - TC1"] + #[inline(always)] + pub fn tc1_(&self) -> TC1__R { + TC1__R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - TC2"] + #[inline(always)] + pub fn tc2_(&self) -> TC2__R { + TC2__R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - TC3"] + #[inline(always)] + pub fn tc3_(&self) -> TC3__R { + TC3__R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - TC4"] + #[inline(always)] + pub fn tc4_(&self) -> TC4__R { + TC4__R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - ADC0"] + #[inline(always)] + pub fn adc0_(&self) -> ADC0__R { + ADC0__R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 20 - AC"] + #[inline(always)] + pub fn ac_(&self) -> AC__R { + AC__R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 22 - PTC"] + #[inline(always)] + pub fn ptc_(&self) -> PTC__R { + PTC__R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - CCL"] + #[inline(always)] + pub fn ccl_(&self) -> CCL__R { + CCL__R::new(((self.bits >> 23) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - EVSYS"] + #[inline(always)] + pub fn evsys_(&mut self) -> EVSYS__W { + EVSYS__W { w: self } + } + #[doc = "Bit 1 - SERCOM0"] + #[inline(always)] + pub fn sercom0_(&mut self) -> SERCOM0__W { + SERCOM0__W { w: self } + } + #[doc = "Bit 2 - SERCOM1"] + #[inline(always)] + pub fn sercom1_(&mut self) -> SERCOM1__W { + SERCOM1__W { w: self } + } + #[doc = "Bit 3 - SERCOM2"] + #[inline(always)] + pub fn sercom2_(&mut self) -> SERCOM2__W { + SERCOM2__W { w: self } + } + #[doc = "Bit 4 - SERCOM3"] + #[inline(always)] + pub fn sercom3_(&mut self) -> SERCOM3__W { + SERCOM3__W { w: self } + } + #[doc = "Bit 5 - SERCOM4"] + #[inline(always)] + pub fn sercom4_(&mut self) -> SERCOM4__W { + SERCOM4__W { w: self } + } + #[doc = "Bit 6 - SERCOM5"] + #[inline(always)] + pub fn sercom5_(&mut self) -> SERCOM5__W { + SERCOM5__W { w: self } + } + #[doc = "Bit 9 - TCC0"] + #[inline(always)] + pub fn tcc0_(&mut self) -> TCC0__W { + TCC0__W { w: self } + } + #[doc = "Bit 10 - TCC1"] + #[inline(always)] + pub fn tcc1_(&mut self) -> TCC1__W { + TCC1__W { w: self } + } + #[doc = "Bit 11 - TCC2"] + #[inline(always)] + pub fn tcc2_(&mut self) -> TCC2__W { + TCC2__W { w: self } + } + #[doc = "Bit 12 - TC0"] + #[inline(always)] + pub fn tc0_(&mut self) -> TC0__W { + TC0__W { w: self } + } + #[doc = "Bit 13 - TC1"] + #[inline(always)] + pub fn tc1_(&mut self) -> TC1__W { + TC1__W { w: self } + } + #[doc = "Bit 14 - TC2"] + #[inline(always)] + pub fn tc2_(&mut self) -> TC2__W { + TC2__W { w: self } + } + #[doc = "Bit 15 - TC3"] + #[inline(always)] + pub fn tc3_(&mut self) -> TC3__W { + TC3__W { w: self } + } + #[doc = "Bit 16 - TC4"] + #[inline(always)] + pub fn tc4_(&mut self) -> TC4__W { + TC4__W { w: self } + } + #[doc = "Bit 17 - ADC0"] + #[inline(always)] + pub fn adc0_(&mut self) -> ADC0__W { + ADC0__W { w: self } + } + #[doc = "Bit 20 - AC"] + #[inline(always)] + pub fn ac_(&mut self) -> AC__W { + AC__W { w: self } + } + #[doc = "Bit 22 - PTC"] + #[inline(always)] + pub fn ptc_(&mut self) -> PTC__W { + PTC__W { w: self } + } + #[doc = "Bit 23 - CCL"] + #[inline(always)] + pub fn ccl_(&mut self) -> CCL__W { + CCL__W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Peripheral interrupt flag status - Bridge C\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflagc](index.html) module"] +pub struct INTFLAGC_SPEC; +impl crate::RegisterSpec for INTFLAGC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflagc::R](R) reader structure"] +impl crate::Readable for INTFLAGC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflagc::W](W) writer structure"] +impl crate::Writable for INTFLAGC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAGC to value 0"] +impl crate::Resettable for INTFLAGC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/pac/intflagd.rs b/pac/atsamc20n/src/pac/intflagd.rs new file mode 100644 index 000000000000..9beeb48bdb72 --- /dev/null +++ b/pac/atsamc20n/src/pac/intflagd.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTFLAGD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAGD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SERCOM6_` reader - SERCOM6"] +pub struct SERCOM6__R(crate::FieldReader); +impl SERCOM6__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM6__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM6__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM6_` writer - SERCOM6"] +pub struct SERCOM6__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM6__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `SERCOM7_` reader - SERCOM7"] +pub struct SERCOM7__R(crate::FieldReader); +impl SERCOM7__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM7__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM7__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM7_` writer - SERCOM7"] +pub struct SERCOM7__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM7__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `TC5_` reader - TC5"] +pub struct TC5__R(crate::FieldReader); +impl TC5__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC5__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC5__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC5_` writer - TC5"] +pub struct TC5__W<'a> { + w: &'a mut W, +} +impl<'a> TC5__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `TC6_` reader - TC6"] +pub struct TC6__R(crate::FieldReader); +impl TC6__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC6__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC6__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC6_` writer - TC6"] +pub struct TC6__W<'a> { + w: &'a mut W, +} +impl<'a> TC6__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `TC7_` reader - TC7"] +pub struct TC7__R(crate::FieldReader); +impl TC7__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC7__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC7__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC7_` writer - TC7"] +pub struct TC7__W<'a> { + w: &'a mut W, +} +impl<'a> TC7__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +impl R { + #[doc = "Bit 0 - SERCOM6"] + #[inline(always)] + pub fn sercom6_(&self) -> SERCOM6__R { + SERCOM6__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM7"] + #[inline(always)] + pub fn sercom7_(&self) -> SERCOM7__R { + SERCOM7__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - TC5"] + #[inline(always)] + pub fn tc5_(&self) -> TC5__R { + TC5__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - TC6"] + #[inline(always)] + pub fn tc6_(&self) -> TC6__R { + TC6__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - TC7"] + #[inline(always)] + pub fn tc7_(&self) -> TC7__R { + TC7__R::new(((self.bits >> 4) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - SERCOM6"] + #[inline(always)] + pub fn sercom6_(&mut self) -> SERCOM6__W { + SERCOM6__W { w: self } + } + #[doc = "Bit 1 - SERCOM7"] + #[inline(always)] + pub fn sercom7_(&mut self) -> SERCOM7__W { + SERCOM7__W { w: self } + } + #[doc = "Bit 2 - TC5"] + #[inline(always)] + pub fn tc5_(&mut self) -> TC5__W { + TC5__W { w: self } + } + #[doc = "Bit 3 - TC6"] + #[inline(always)] + pub fn tc6_(&mut self) -> TC6__W { + TC6__W { w: self } + } + #[doc = "Bit 4 - TC7"] + #[inline(always)] + pub fn tc7_(&mut self) -> TC7__W { + TC7__W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Peripheral interrupt flag status - Bridge D\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflagd](index.html) module"] +pub struct INTFLAGD_SPEC; +impl crate::RegisterSpec for INTFLAGD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflagd::R](R) reader structure"] +impl crate::Readable for INTFLAGD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflagd::W](W) writer structure"] +impl crate::Writable for INTFLAGD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAGD to value 0"] +impl crate::Resettable for INTFLAGD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/pac/statusa.rs b/pac/atsamc20n/src/pac/statusa.rs new file mode 100644 index 000000000000..32974f65e5d5 --- /dev/null +++ b/pac/atsamc20n/src/pac/statusa.rs @@ -0,0 +1,273 @@ +#[doc = "Register `STATUSA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PAC_` reader - PAC APB Protect Enable"] +pub struct PAC__R(crate::FieldReader); +impl PAC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PAC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PM_` reader - PM APB Protect Enable"] +pub struct PM__R(crate::FieldReader); +impl PM__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PM__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PM__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCLK_` reader - MCLK APB Protect Enable"] +pub struct MCLK__R(crate::FieldReader); +impl MCLK__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCLK__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCLK__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RSTC_` reader - RSTC APB Protect Enable"] +pub struct RSTC__R(crate::FieldReader); +impl RSTC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RSTC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RSTC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSCCTRL_` reader - OSCCTRL APB Protect Enable"] +pub struct OSCCTRL__R(crate::FieldReader); +impl OSCCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSCCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSCCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC32KCTRL_` reader - OSC32KCTRL APB Protect Enable"] +pub struct OSC32KCTRL__R(crate::FieldReader); +impl OSC32KCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC32KCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC32KCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SUPC_` reader - SUPC APB Protect Enable"] +pub struct SUPC__R(crate::FieldReader); +impl SUPC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SUPC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SUPC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GCLK_` reader - GCLK APB Protect Enable"] +pub struct GCLK__R(crate::FieldReader); +impl GCLK__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GCLK__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GCLK__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WDT_` reader - WDT APB Protect Enable"] +pub struct WDT__R(crate::FieldReader); +impl WDT__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WDT__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WDT__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RTC_` reader - RTC APB Protect Enable"] +pub struct RTC__R(crate::FieldReader); +impl RTC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RTC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RTC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EIC_` reader - EIC APB Protect Enable"] +pub struct EIC__R(crate::FieldReader); +impl EIC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EIC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EIC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FREQM_` reader - FREQM APB Protect Enable"] +pub struct FREQM__R(crate::FieldReader); +impl FREQM__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FREQM__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FREQM__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - PAC APB Protect Enable"] + #[inline(always)] + pub fn pac_(&self) -> PAC__R { + PAC__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - PM APB Protect Enable"] + #[inline(always)] + pub fn pm_(&self) -> PM__R { + PM__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - MCLK APB Protect Enable"] + #[inline(always)] + pub fn mclk_(&self) -> MCLK__R { + MCLK__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - RSTC APB Protect Enable"] + #[inline(always)] + pub fn rstc_(&self) -> RSTC__R { + RSTC__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - OSCCTRL APB Protect Enable"] + #[inline(always)] + pub fn oscctrl_(&self) -> OSCCTRL__R { + OSCCTRL__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - OSC32KCTRL APB Protect Enable"] + #[inline(always)] + pub fn osc32kctrl_(&self) -> OSC32KCTRL__R { + OSC32KCTRL__R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - SUPC APB Protect Enable"] + #[inline(always)] + pub fn supc_(&self) -> SUPC__R { + SUPC__R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - GCLK APB Protect Enable"] + #[inline(always)] + pub fn gclk_(&self) -> GCLK__R { + GCLK__R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - WDT APB Protect Enable"] + #[inline(always)] + pub fn wdt_(&self) -> WDT__R { + WDT__R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - RTC APB Protect Enable"] + #[inline(always)] + pub fn rtc_(&self) -> RTC__R { + RTC__R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - EIC APB Protect Enable"] + #[inline(always)] + pub fn eic_(&self) -> EIC__R { + EIC__R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - FREQM APB Protect Enable"] + #[inline(always)] + pub fn freqm_(&self) -> FREQM__R { + FREQM__R::new(((self.bits >> 11) & 0x01) != 0) + } +} +#[doc = "Peripheral write protection status - Bridge A\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [statusa](index.html) module"] +pub struct STATUSA_SPEC; +impl crate::RegisterSpec for STATUSA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [statusa::R](R) reader structure"] +impl crate::Readable for STATUSA_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUSA to value 0"] +impl crate::Resettable for STATUSA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/pac/statusb.rs b/pac/atsamc20n/src/pac/statusb.rs new file mode 100644 index 000000000000..a022cc2f1d54 --- /dev/null +++ b/pac/atsamc20n/src/pac/statusb.rs @@ -0,0 +1,153 @@ +#[doc = "Register `STATUSB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PORT_` reader - PORT APB Protect Enable"] +pub struct PORT__R(crate::FieldReader); +impl PORT__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PORT__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PORT__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DSU_` reader - DSU APB Protect Enable"] +pub struct DSU__R(crate::FieldReader); +impl DSU__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DSU__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DSU__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NVMCTRL_` reader - NVMCTRL APB Protect Enable"] +pub struct NVMCTRL__R(crate::FieldReader); +impl NVMCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NVMCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NVMCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DMAC_` reader - DMAC APB Protect Enable"] +pub struct DMAC__R(crate::FieldReader); +impl DMAC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DMAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DMAC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MTB_` reader - MTB APB Protect Enable"] +pub struct MTB__R(crate::FieldReader); +impl MTB__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MTB__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MTB__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HMATRIXHS_` reader - HMATRIXHS APB Protect Enable"] +pub struct HMATRIXHS__R(crate::FieldReader); +impl HMATRIXHS__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HMATRIXHS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HMATRIXHS__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - PORT APB Protect Enable"] + #[inline(always)] + pub fn port_(&self) -> PORT__R { + PORT__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - DSU APB Protect Enable"] + #[inline(always)] + pub fn dsu_(&self) -> DSU__R { + DSU__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - NVMCTRL APB Protect Enable"] + #[inline(always)] + pub fn nvmctrl_(&self) -> NVMCTRL__R { + NVMCTRL__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - DMAC APB Protect Enable"] + #[inline(always)] + pub fn dmac_(&self) -> DMAC__R { + DMAC__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - MTB APB Protect Enable"] + #[inline(always)] + pub fn mtb_(&self) -> MTB__R { + MTB__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - HMATRIXHS APB Protect Enable"] + #[inline(always)] + pub fn hmatrixhs_(&self) -> HMATRIXHS__R { + HMATRIXHS__R::new(((self.bits >> 5) & 0x01) != 0) + } +} +#[doc = "Peripheral write protection status - Bridge B\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [statusb](index.html) module"] +pub struct STATUSB_SPEC; +impl crate::RegisterSpec for STATUSB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [statusb::R](R) reader structure"] +impl crate::Readable for STATUSB_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUSB to value 0x02"] +impl crate::Resettable for STATUSB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x02 + } +} diff --git a/pac/atsamc20n/src/pac/statusc.rs b/pac/atsamc20n/src/pac/statusc.rs new file mode 100644 index 000000000000..a741707bddf3 --- /dev/null +++ b/pac/atsamc20n/src/pac/statusc.rs @@ -0,0 +1,413 @@ +#[doc = "Register `STATUSC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `EVSYS_` reader - EVSYS APB Protect Enable"] +pub struct EVSYS__R(crate::FieldReader); +impl EVSYS__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVSYS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVSYS__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM0_` reader - SERCOM0 APB Protect Enable"] +pub struct SERCOM0__R(crate::FieldReader); +impl SERCOM0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM1_` reader - SERCOM1 APB Protect Enable"] +pub struct SERCOM1__R(crate::FieldReader); +impl SERCOM1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM2_` reader - SERCOM2 APB Protect Enable"] +pub struct SERCOM2__R(crate::FieldReader); +impl SERCOM2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM3_` reader - SERCOM3 APB Protect Enable"] +pub struct SERCOM3__R(crate::FieldReader); +impl SERCOM3__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM3__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM3__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM4_` reader - SERCOM4 APB Protect Enable"] +pub struct SERCOM4__R(crate::FieldReader); +impl SERCOM4__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM4__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM4__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM5_` reader - SERCOM5 APB Protect Enable"] +pub struct SERCOM5__R(crate::FieldReader); +impl SERCOM5__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM5__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM5__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCC0_` reader - TCC0 APB Protect Enable"] +pub struct TCC0__R(crate::FieldReader); +impl TCC0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCC0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCC0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCC1_` reader - TCC1 APB Protect Enable"] +pub struct TCC1__R(crate::FieldReader); +impl TCC1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCC1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCC1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCC2_` reader - TCC2 APB Protect Enable"] +pub struct TCC2__R(crate::FieldReader); +impl TCC2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCC2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCC2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC0_` reader - TC0 APB Protect Enable"] +pub struct TC0__R(crate::FieldReader); +impl TC0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC1_` reader - TC1 APB Protect Enable"] +pub struct TC1__R(crate::FieldReader); +impl TC1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC2_` reader - TC2 APB Protect Enable"] +pub struct TC2__R(crate::FieldReader); +impl TC2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC3_` reader - TC3 APB Protect Enable"] +pub struct TC3__R(crate::FieldReader); +impl TC3__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC3__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC3__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC4_` reader - TC4 APB Protect Enable"] +pub struct TC4__R(crate::FieldReader); +impl TC4__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC4__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC4__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADC0_` reader - ADC0 APB Protect Enable"] +pub struct ADC0__R(crate::FieldReader); +impl ADC0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ADC0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADC0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AC_` reader - AC APB Protect Enable"] +pub struct AC__R(crate::FieldReader); +impl AC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PTC_` reader - PTC APB Protect Enable"] +pub struct PTC__R(crate::FieldReader); +impl PTC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PTC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PTC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCL_` reader - CCL APB Protect Enable"] +pub struct CCL__R(crate::FieldReader); +impl CCL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - EVSYS APB Protect Enable"] + #[inline(always)] + pub fn evsys_(&self) -> EVSYS__R { + EVSYS__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM0 APB Protect Enable"] + #[inline(always)] + pub fn sercom0_(&self) -> SERCOM0__R { + SERCOM0__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - SERCOM1 APB Protect Enable"] + #[inline(always)] + pub fn sercom1_(&self) -> SERCOM1__R { + SERCOM1__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - SERCOM2 APB Protect Enable"] + #[inline(always)] + pub fn sercom2_(&self) -> SERCOM2__R { + SERCOM2__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - SERCOM3 APB Protect Enable"] + #[inline(always)] + pub fn sercom3_(&self) -> SERCOM3__R { + SERCOM3__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - SERCOM4 APB Protect Enable"] + #[inline(always)] + pub fn sercom4_(&self) -> SERCOM4__R { + SERCOM4__R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - SERCOM5 APB Protect Enable"] + #[inline(always)] + pub fn sercom5_(&self) -> SERCOM5__R { + SERCOM5__R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 9 - TCC0 APB Protect Enable"] + #[inline(always)] + pub fn tcc0_(&self) -> TCC0__R { + TCC0__R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - TCC1 APB Protect Enable"] + #[inline(always)] + pub fn tcc1_(&self) -> TCC1__R { + TCC1__R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - TCC2 APB Protect Enable"] + #[inline(always)] + pub fn tcc2_(&self) -> TCC2__R { + TCC2__R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - TC0 APB Protect Enable"] + #[inline(always)] + pub fn tc0_(&self) -> TC0__R { + TC0__R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - TC1 APB Protect Enable"] + #[inline(always)] + pub fn tc1_(&self) -> TC1__R { + TC1__R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - TC2 APB Protect Enable"] + #[inline(always)] + pub fn tc2_(&self) -> TC2__R { + TC2__R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - TC3 APB Protect Enable"] + #[inline(always)] + pub fn tc3_(&self) -> TC3__R { + TC3__R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - TC4 APB Protect Enable"] + #[inline(always)] + pub fn tc4_(&self) -> TC4__R { + TC4__R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - ADC0 APB Protect Enable"] + #[inline(always)] + pub fn adc0_(&self) -> ADC0__R { + ADC0__R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 20 - AC APB Protect Enable"] + #[inline(always)] + pub fn ac_(&self) -> AC__R { + AC__R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 22 - PTC APB Protect Enable"] + #[inline(always)] + pub fn ptc_(&self) -> PTC__R { + PTC__R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - CCL APB Protect Enable"] + #[inline(always)] + pub fn ccl_(&self) -> CCL__R { + CCL__R::new(((self.bits >> 23) & 0x01) != 0) + } +} +#[doc = "Peripheral write protection status - Bridge C\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [statusc](index.html) module"] +pub struct STATUSC_SPEC; +impl crate::RegisterSpec for STATUSC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [statusc::R](R) reader structure"] +impl crate::Readable for STATUSC_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUSC to value 0x0200_0000"] +impl crate::Resettable for STATUSC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0200_0000 + } +} diff --git a/pac/atsamc20n/src/pac/statusd.rs b/pac/atsamc20n/src/pac/statusd.rs new file mode 100644 index 000000000000..69c78dd013e1 --- /dev/null +++ b/pac/atsamc20n/src/pac/statusd.rs @@ -0,0 +1,133 @@ +#[doc = "Register `STATUSD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SERCOM6_` reader - SERCOM6 APB Protect Enable"] +pub struct SERCOM6__R(crate::FieldReader); +impl SERCOM6__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM6__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM6__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM7_` reader - SERCOM7 APB Protect Enable"] +pub struct SERCOM7__R(crate::FieldReader); +impl SERCOM7__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM7__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM7__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC5_` reader - TC5 APB Protect Enable"] +pub struct TC5__R(crate::FieldReader); +impl TC5__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC5__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC5__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC6_` reader - TC6 APB Protect Enable"] +pub struct TC6__R(crate::FieldReader); +impl TC6__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC6__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC6__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC7_` reader - TC7 APB Protect Enable"] +pub struct TC7__R(crate::FieldReader); +impl TC7__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC7__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC7__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - SERCOM6 APB Protect Enable"] + #[inline(always)] + pub fn sercom6_(&self) -> SERCOM6__R { + SERCOM6__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM7 APB Protect Enable"] + #[inline(always)] + pub fn sercom7_(&self) -> SERCOM7__R { + SERCOM7__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - TC5 APB Protect Enable"] + #[inline(always)] + pub fn tc5_(&self) -> TC5__R { + TC5__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - TC6 APB Protect Enable"] + #[inline(always)] + pub fn tc6_(&self) -> TC6__R { + TC6__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - TC7 APB Protect Enable"] + #[inline(always)] + pub fn tc7_(&self) -> TC7__R { + TC7__R::new(((self.bits >> 4) & 0x01) != 0) + } +} +#[doc = "Peripheral write protection status - Bridge D\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [statusd](index.html) module"] +pub struct STATUSD_SPEC; +impl crate::RegisterSpec for STATUSD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [statusd::R](R) reader structure"] +impl crate::Readable for STATUSD_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUSD to value 0"] +impl crate::Resettable for STATUSD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/pac/wrctrl.rs b/pac/atsamc20n/src/pac/wrctrl.rs new file mode 100644 index 000000000000..65773ea08d64 --- /dev/null +++ b/pac/atsamc20n/src/pac/wrctrl.rs @@ -0,0 +1,215 @@ +#[doc = "Register `WRCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WRCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PERID` reader - Peripheral identifier"] +pub struct PERID_R(crate::FieldReader); +impl PERID_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + PERID_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERID_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERID` writer - Peripheral identifier"] +pub struct PERID_W<'a> { + w: &'a mut W, +} +impl<'a> PERID_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +#[doc = "Peripheral access control key\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum KEY_A { + #[doc = "0: No action"] + OFF = 0, + #[doc = "1: Clear protection"] + CLR = 1, + #[doc = "2: Set protection"] + SET = 2, + #[doc = "3: Set and lock protection"] + SETLCK = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: KEY_A) -> Self { + variant as _ + } +} +#[doc = "Field `KEY` reader - Peripheral access control key"] +pub struct KEY_R(crate::FieldReader); +impl KEY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + KEY_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(KEY_A::OFF), + 1 => Some(KEY_A::CLR), + 2 => Some(KEY_A::SET), + 3 => Some(KEY_A::SETLCK), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == KEY_A::OFF + } + #[doc = "Checks if the value of the field is `CLR`"] + #[inline(always)] + pub fn is_clr(&self) -> bool { + **self == KEY_A::CLR + } + #[doc = "Checks if the value of the field is `SET`"] + #[inline(always)] + pub fn is_set(&self) -> bool { + **self == KEY_A::SET + } + #[doc = "Checks if the value of the field is `SETLCK`"] + #[inline(always)] + pub fn is_setlck(&self) -> bool { + **self == KEY_A::SETLCK + } +} +impl core::ops::Deref for KEY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `KEY` writer - Peripheral access control key"] +pub struct KEY_W<'a> { + w: &'a mut W, +} +impl<'a> KEY_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: KEY_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(KEY_A::OFF) + } + #[doc = "Clear protection"] + #[inline(always)] + pub fn clr(self) -> &'a mut W { + self.variant(KEY_A::CLR) + } + #[doc = "Set protection"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(KEY_A::SET) + } + #[doc = "Set and lock protection"] + #[inline(always)] + pub fn setlck(self) -> &'a mut W { + self.variant(KEY_A::SETLCK) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Peripheral identifier"] + #[inline(always)] + pub fn perid(&self) -> PERID_R { + PERID_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:23 - Peripheral access control key"] + #[inline(always)] + pub fn key(&self) -> KEY_R { + KEY_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:15 - Peripheral identifier"] + #[inline(always)] + pub fn perid(&mut self) -> PERID_W { + PERID_W { w: self } + } + #[doc = "Bits 16:23 - Peripheral access control key"] + #[inline(always)] + pub fn key(&mut self) -> KEY_W { + KEY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Write control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wrctrl](index.html) module"] +pub struct WRCTRL_SPEC; +impl crate::RegisterSpec for WRCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [wrctrl::R](R) reader structure"] +impl crate::Readable for WRCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wrctrl::W](W) writer structure"] +impl crate::Writable for WRCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WRCTRL to value 0"] +impl crate::Resettable for WRCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/pm.rs b/pac/atsamc20n/src/pm.rs new file mode 100644 index 000000000000..9da2b0e13288 --- /dev/null +++ b/pac/atsamc20n/src/pm.rs @@ -0,0 +1,18 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved0: [u8; 0x01], + #[doc = "0x01 - Sleep Configuration"] + pub sleepcfg: crate::Reg, + _reserved1: [u8; 0x06], + #[doc = "0x08 - Standby Configuration"] + pub stdbycfg: crate::Reg, +} +#[doc = "SLEEPCFG register accessor: an alias for `Reg`"] +pub type SLEEPCFG = crate::Reg; +#[doc = "Sleep Configuration"] +pub mod sleepcfg; +#[doc = "STDBYCFG register accessor: an alias for `Reg`"] +pub type STDBYCFG = crate::Reg; +#[doc = "Standby Configuration"] +pub mod stdbycfg; diff --git a/pac/atsamc20n/src/pm/sleepcfg.rs b/pac/atsamc20n/src/pm/sleepcfg.rs new file mode 100644 index 000000000000..9ff91fdee046 --- /dev/null +++ b/pac/atsamc20n/src/pm/sleepcfg.rs @@ -0,0 +1,204 @@ +#[doc = "Register `SLEEPCFG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SLEEPCFG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Sleep Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SLEEPMODE_A { + #[doc = "0: CPU clock is OFF"] + IDLE0 = 0, + #[doc = "1: AHB clock is OFF"] + IDLE1 = 1, + #[doc = "2: APB clock are OFF"] + IDLE2 = 2, + #[doc = "4: All Clocks are OFF"] + STANDBY = 4, + #[doc = "5: Only Backup domain is powered ON"] + BACKUP = 5, + #[doc = "6: All power domains are powered OFF"] + OFF = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SLEEPMODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `SLEEPMODE` reader - Sleep Mode"] +pub struct SLEEPMODE_R(crate::FieldReader); +impl SLEEPMODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SLEEPMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SLEEPMODE_A::IDLE0), + 1 => Some(SLEEPMODE_A::IDLE1), + 2 => Some(SLEEPMODE_A::IDLE2), + 4 => Some(SLEEPMODE_A::STANDBY), + 5 => Some(SLEEPMODE_A::BACKUP), + 6 => Some(SLEEPMODE_A::OFF), + _ => None, + } + } + #[doc = "Checks if the value of the field is `IDLE0`"] + #[inline(always)] + pub fn is_idle0(&self) -> bool { + **self == SLEEPMODE_A::IDLE0 + } + #[doc = "Checks if the value of the field is `IDLE1`"] + #[inline(always)] + pub fn is_idle1(&self) -> bool { + **self == SLEEPMODE_A::IDLE1 + } + #[doc = "Checks if the value of the field is `IDLE2`"] + #[inline(always)] + pub fn is_idle2(&self) -> bool { + **self == SLEEPMODE_A::IDLE2 + } + #[doc = "Checks if the value of the field is `STANDBY`"] + #[inline(always)] + pub fn is_standby(&self) -> bool { + **self == SLEEPMODE_A::STANDBY + } + #[doc = "Checks if the value of the field is `BACKUP`"] + #[inline(always)] + pub fn is_backup(&self) -> bool { + **self == SLEEPMODE_A::BACKUP + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == SLEEPMODE_A::OFF + } +} +impl core::ops::Deref for SLEEPMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLEEPMODE` writer - Sleep Mode"] +pub struct SLEEPMODE_W<'a> { + w: &'a mut W, +} +impl<'a> SLEEPMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SLEEPMODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "CPU clock is OFF"] + #[inline(always)] + pub fn idle0(self) -> &'a mut W { + self.variant(SLEEPMODE_A::IDLE0) + } + #[doc = "AHB clock is OFF"] + #[inline(always)] + pub fn idle1(self) -> &'a mut W { + self.variant(SLEEPMODE_A::IDLE1) + } + #[doc = "APB clock are OFF"] + #[inline(always)] + pub fn idle2(self) -> &'a mut W { + self.variant(SLEEPMODE_A::IDLE2) + } + #[doc = "All Clocks are OFF"] + #[inline(always)] + pub fn standby(self) -> &'a mut W { + self.variant(SLEEPMODE_A::STANDBY) + } + #[doc = "Only Backup domain is powered ON"] + #[inline(always)] + pub fn backup(self) -> &'a mut W { + self.variant(SLEEPMODE_A::BACKUP) + } + #[doc = "All power domains are powered OFF"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(SLEEPMODE_A::OFF) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Sleep Mode"] + #[inline(always)] + pub fn sleepmode(&self) -> SLEEPMODE_R { + SLEEPMODE_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Sleep Mode"] + #[inline(always)] + pub fn sleepmode(&mut self) -> SLEEPMODE_W { + SLEEPMODE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Sleep Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sleepcfg](index.html) module"] +pub struct SLEEPCFG_SPEC; +impl crate::RegisterSpec for SLEEPCFG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [sleepcfg::R](R) reader structure"] +impl crate::Readable for SLEEPCFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [sleepcfg::W](W) writer structure"] +impl crate::Writable for SLEEPCFG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SLEEPCFG to value 0"] +impl crate::Resettable for SLEEPCFG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/pm/stdbycfg.rs b/pac/atsamc20n/src/pm/stdbycfg.rs new file mode 100644 index 000000000000..9be67f240062 --- /dev/null +++ b/pac/atsamc20n/src/pm/stdbycfg.rs @@ -0,0 +1,202 @@ +#[doc = "Register `STDBYCFG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STDBYCFG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Voltage Regulator Standby mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum VREGSMOD_A { + #[doc = "0: Automatic mode"] + AUTO = 0, + #[doc = "1: Performance oriented"] + PERFORMANCE = 1, + #[doc = "2: Low Power oriented"] + LP = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: VREGSMOD_A) -> Self { + variant as _ + } +} +#[doc = "Field `VREGSMOD` reader - Voltage Regulator Standby mode"] +pub struct VREGSMOD_R(crate::FieldReader); +impl VREGSMOD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + VREGSMOD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(VREGSMOD_A::AUTO), + 1 => Some(VREGSMOD_A::PERFORMANCE), + 2 => Some(VREGSMOD_A::LP), + _ => None, + } + } + #[doc = "Checks if the value of the field is `AUTO`"] + #[inline(always)] + pub fn is_auto(&self) -> bool { + **self == VREGSMOD_A::AUTO + } + #[doc = "Checks if the value of the field is `PERFORMANCE`"] + #[inline(always)] + pub fn is_performance(&self) -> bool { + **self == VREGSMOD_A::PERFORMANCE + } + #[doc = "Checks if the value of the field is `LP`"] + #[inline(always)] + pub fn is_lp(&self) -> bool { + **self == VREGSMOD_A::LP + } +} +impl core::ops::Deref for VREGSMOD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VREGSMOD` writer - Voltage Regulator Standby mode"] +pub struct VREGSMOD_W<'a> { + w: &'a mut W, +} +impl<'a> VREGSMOD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: VREGSMOD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Automatic mode"] + #[inline(always)] + pub fn auto(self) -> &'a mut W { + self.variant(VREGSMOD_A::AUTO) + } + #[doc = "Performance oriented"] + #[inline(always)] + pub fn performance(self) -> &'a mut W { + self.variant(VREGSMOD_A::PERFORMANCE) + } + #[doc = "Low Power oriented"] + #[inline(always)] + pub fn lp(self) -> &'a mut W { + self.variant(VREGSMOD_A::LP) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 6)) | ((value as u16 & 0x03) << 6); + self.w + } +} +#[doc = "Field `BBIASHS` reader - Back Bias for HMCRAMCHS"] +pub struct BBIASHS_R(crate::FieldReader); +impl BBIASHS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BBIASHS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BBIASHS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BBIASHS` writer - Back Bias for HMCRAMCHS"] +pub struct BBIASHS_W<'a> { + w: &'a mut W, +} +impl<'a> BBIASHS_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 10)) | ((value as u16 & 0x03) << 10); + self.w + } +} +impl R { + #[doc = "Bits 6:7 - Voltage Regulator Standby mode"] + #[inline(always)] + pub fn vregsmod(&self) -> VREGSMOD_R { + VREGSMOD_R::new(((self.bits >> 6) & 0x03) as u8) + } + #[doc = "Bits 10:11 - Back Bias for HMCRAMCHS"] + #[inline(always)] + pub fn bbiashs(&self) -> BBIASHS_R { + BBIASHS_R::new(((self.bits >> 10) & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 6:7 - Voltage Regulator Standby mode"] + #[inline(always)] + pub fn vregsmod(&mut self) -> VREGSMOD_W { + VREGSMOD_W { w: self } + } + #[doc = "Bits 10:11 - Back Bias for HMCRAMCHS"] + #[inline(always)] + pub fn bbiashs(&mut self) -> BBIASHS_W { + BBIASHS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Standby Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [stdbycfg](index.html) module"] +pub struct STDBYCFG_SPEC; +impl crate::RegisterSpec for STDBYCFG_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [stdbycfg::R](R) reader structure"] +impl crate::Readable for STDBYCFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [stdbycfg::W](W) writer structure"] +impl crate::Writable for STDBYCFG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STDBYCFG to value 0x0400"] +impl crate::Resettable for STDBYCFG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0400 + } +} diff --git a/pac/atsamc20n/src/port.rs b/pac/atsamc20n/src/port.rs new file mode 100644 index 000000000000..b901dd415a91 --- /dev/null +++ b/pac/atsamc20n/src/port.rs @@ -0,0 +1,47 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00..0x60 - GROUP\\[%s\\]"] + pub group0: GROUP, + _reserved1: [u8; 0x20], + #[doc = "0x80..0xe0 - GROUP\\[%s\\]"] + pub group1: GROUP, + _reserved2: [u8; 0x20], + #[doc = "0x100..0x160 - GROUP\\[%s\\]"] + pub group2: GROUP, +} +#[doc = r"Register block"] +#[repr(C)] +pub struct GROUP { + #[doc = "0x00 - Data Direction"] + pub dir: crate::Reg, + #[doc = "0x04 - Data Direction Clear"] + pub dirclr: crate::Reg, + #[doc = "0x08 - Data Direction Set"] + pub dirset: crate::Reg, + #[doc = "0x0c - Data Direction Toggle"] + pub dirtgl: crate::Reg, + #[doc = "0x10 - Data Output Value"] + pub out: crate::Reg, + #[doc = "0x14 - Data Output Value Clear"] + pub outclr: crate::Reg, + #[doc = "0x18 - Data Output Value Set"] + pub outset: crate::Reg, + #[doc = "0x1c - Data Output Value Toggle"] + pub outtgl: crate::Reg, + #[doc = "0x20 - Data Input Value"] + pub in_: crate::Reg, + #[doc = "0x24 - Control"] + pub ctrl: crate::Reg, + #[doc = "0x28 - Write Configuration"] + pub wrconfig: crate::Reg, + #[doc = "0x2c - Event Input Control"] + pub evctrl: crate::Reg, + #[doc = "0x30..0x40 - Peripheral Multiplexing n"] + pub pmux: [crate::Reg; 16], + #[doc = "0x40..0x60 - Pin Configuration n"] + pub pincfg: [crate::Reg; 32], +} +#[doc = r"Register block"] +#[doc = "GROUP\\[%s\\]"] +pub mod group; diff --git a/pac/atsamc20n/src/port/group.rs b/pac/atsamc20n/src/port/group.rs new file mode 100644 index 000000000000..d1aabcd73380 --- /dev/null +++ b/pac/atsamc20n/src/port/group.rs @@ -0,0 +1,56 @@ +#[doc = "DIR register accessor: an alias for `Reg`"] +pub type DIR = crate::Reg; +#[doc = "Data Direction"] +pub mod dir; +#[doc = "DIRCLR register accessor: an alias for `Reg`"] +pub type DIRCLR = crate::Reg; +#[doc = "Data Direction Clear"] +pub mod dirclr; +#[doc = "DIRSET register accessor: an alias for `Reg`"] +pub type DIRSET = crate::Reg; +#[doc = "Data Direction Set"] +pub mod dirset; +#[doc = "DIRTGL register accessor: an alias for `Reg`"] +pub type DIRTGL = crate::Reg; +#[doc = "Data Direction Toggle"] +pub mod dirtgl; +#[doc = "OUT register accessor: an alias for `Reg`"] +pub type OUT = crate::Reg; +#[doc = "Data Output Value"] +pub mod out; +#[doc = "OUTCLR register accessor: an alias for `Reg`"] +pub type OUTCLR = crate::Reg; +#[doc = "Data Output Value Clear"] +pub mod outclr; +#[doc = "OUTSET register accessor: an alias for `Reg`"] +pub type OUTSET = crate::Reg; +#[doc = "Data Output Value Set"] +pub mod outset; +#[doc = "OUTTGL register accessor: an alias for `Reg`"] +pub type OUTTGL = crate::Reg; +#[doc = "Data Output Value Toggle"] +pub mod outtgl; +#[doc = "IN register accessor: an alias for `Reg`"] +pub type IN = crate::Reg; +#[doc = "Data Input Value"] +pub mod in_; +#[doc = "CTRL register accessor: an alias for `Reg`"] +pub type CTRL = crate::Reg; +#[doc = "Control"] +pub mod ctrl; +#[doc = "WRCONFIG register accessor: an alias for `Reg`"] +pub type WRCONFIG = crate::Reg; +#[doc = "Write Configuration"] +pub mod wrconfig; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Input Control"] +pub mod evctrl; +#[doc = "PMUX register accessor: an alias for `Reg`"] +pub type PMUX = crate::Reg; +#[doc = "Peripheral Multiplexing n"] +pub mod pmux; +#[doc = "PINCFG register accessor: an alias for `Reg`"] +pub type PINCFG = crate::Reg; +#[doc = "Pin Configuration n"] +pub mod pincfg; diff --git a/pac/atsamc20n/src/port/group/ctrl.rs b/pac/atsamc20n/src/port/group/ctrl.rs new file mode 100644 index 000000000000..4b57cd6fcd2b --- /dev/null +++ b/pac/atsamc20n/src/port/group/ctrl.rs @@ -0,0 +1,103 @@ +#[doc = "Register `CTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SAMPLING` reader - Input Sampling Mode"] +pub struct SAMPLING_R(crate::FieldReader); +impl SAMPLING_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + SAMPLING_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SAMPLING_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SAMPLING` writer - Input Sampling Mode"] +pub struct SAMPLING_W<'a> { + w: &'a mut W, +} +impl<'a> SAMPLING_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Input Sampling Mode"] + #[inline(always)] + pub fn sampling(&self) -> SAMPLING_R { + SAMPLING_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Input Sampling Mode"] + #[inline(always)] + pub fn sampling(&mut self) -> SAMPLING_W { + SAMPLING_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"] +pub struct CTRL_SPEC; +impl crate::RegisterSpec for CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrl::R](R) reader structure"] +impl crate::Readable for CTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"] +impl crate::Writable for CTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/port/group/dir.rs b/pac/atsamc20n/src/port/group/dir.rs new file mode 100644 index 000000000000..e04452fb5d35 --- /dev/null +++ b/pac/atsamc20n/src/port/group/dir.rs @@ -0,0 +1,64 @@ +#[doc = "Register `DIR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Direction\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dir](index.html) module"] +pub struct DIR_SPEC; +impl crate::RegisterSpec for DIR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dir::R](R) reader structure"] +impl crate::Readable for DIR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dir::W](W) writer structure"] +impl crate::Writable for DIR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DIR to value 0"] +impl crate::Resettable for DIR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/port/group/dirclr.rs b/pac/atsamc20n/src/port/group/dirclr.rs new file mode 100644 index 000000000000..5e6d73d032b2 --- /dev/null +++ b/pac/atsamc20n/src/port/group/dirclr.rs @@ -0,0 +1,64 @@ +#[doc = "Register `DIRCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIRCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Direction Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dirclr](index.html) module"] +pub struct DIRCLR_SPEC; +impl crate::RegisterSpec for DIRCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dirclr::R](R) reader structure"] +impl crate::Readable for DIRCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dirclr::W](W) writer structure"] +impl crate::Writable for DIRCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DIRCLR to value 0"] +impl crate::Resettable for DIRCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/port/group/dirset.rs b/pac/atsamc20n/src/port/group/dirset.rs new file mode 100644 index 000000000000..eaa86e14f15d --- /dev/null +++ b/pac/atsamc20n/src/port/group/dirset.rs @@ -0,0 +1,64 @@ +#[doc = "Register `DIRSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIRSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Direction Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dirset](index.html) module"] +pub struct DIRSET_SPEC; +impl crate::RegisterSpec for DIRSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dirset::R](R) reader structure"] +impl crate::Readable for DIRSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dirset::W](W) writer structure"] +impl crate::Writable for DIRSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DIRSET to value 0"] +impl crate::Resettable for DIRSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/port/group/dirtgl.rs b/pac/atsamc20n/src/port/group/dirtgl.rs new file mode 100644 index 000000000000..fbd021438b1b --- /dev/null +++ b/pac/atsamc20n/src/port/group/dirtgl.rs @@ -0,0 +1,64 @@ +#[doc = "Register `DIRTGL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIRTGL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Direction Toggle\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dirtgl](index.html) module"] +pub struct DIRTGL_SPEC; +impl crate::RegisterSpec for DIRTGL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dirtgl::R](R) reader structure"] +impl crate::Readable for DIRTGL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dirtgl::W](W) writer structure"] +impl crate::Writable for DIRTGL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DIRTGL to value 0"] +impl crate::Resettable for DIRTGL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/port/group/evctrl.rs b/pac/atsamc20n/src/port/group/evctrl.rs new file mode 100644 index 000000000000..ef0a35987f3d --- /dev/null +++ b/pac/atsamc20n/src/port/group/evctrl.rs @@ -0,0 +1,625 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PID0` reader - Port Event Pin Identifier 0"] +pub struct PID0_R(crate::FieldReader); +impl PID0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PID0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PID0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PID0` writer - Port Event Pin Identifier 0"] +pub struct PID0_W<'a> { + w: &'a mut W, +} +impl<'a> PID0_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f); + self.w + } +} +#[doc = "Port Event Action 0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EVACT0_A { + #[doc = "0: Event output to pin"] + OUT = 0, + #[doc = "1: Set output register of pin on event"] + SET = 1, + #[doc = "2: Clear output register of pin on event"] + CLR = 2, + #[doc = "3: Toggle output register of pin on event"] + TGL = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EVACT0_A) -> Self { + variant as _ + } +} +#[doc = "Field `EVACT0` reader - Port Event Action 0"] +pub struct EVACT0_R(crate::FieldReader); +impl EVACT0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVACT0_A { + match self.bits { + 0 => EVACT0_A::OUT, + 1 => EVACT0_A::SET, + 2 => EVACT0_A::CLR, + 3 => EVACT0_A::TGL, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `OUT`"] + #[inline(always)] + pub fn is_out(&self) -> bool { + **self == EVACT0_A::OUT + } + #[doc = "Checks if the value of the field is `SET`"] + #[inline(always)] + pub fn is_set(&self) -> bool { + **self == EVACT0_A::SET + } + #[doc = "Checks if the value of the field is `CLR`"] + #[inline(always)] + pub fn is_clr(&self) -> bool { + **self == EVACT0_A::CLR + } + #[doc = "Checks if the value of the field is `TGL`"] + #[inline(always)] + pub fn is_tgl(&self) -> bool { + **self == EVACT0_A::TGL + } +} +impl core::ops::Deref for EVACT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT0` writer - Port Event Action 0"] +pub struct EVACT0_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT0_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EVACT0_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Event output to pin"] + #[inline(always)] + pub fn out(self) -> &'a mut W { + self.variant(EVACT0_A::OUT) + } + #[doc = "Set output register of pin on event"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(EVACT0_A::SET) + } + #[doc = "Clear output register of pin on event"] + #[inline(always)] + pub fn clr(self) -> &'a mut W { + self.variant(EVACT0_A::CLR) + } + #[doc = "Toggle output register of pin on event"] + #[inline(always)] + pub fn tgl(self) -> &'a mut W { + self.variant(EVACT0_A::TGL) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 5)) | ((value as u32 & 0x03) << 5); + self.w + } +} +#[doc = "Field `PORTEI0` reader - Port Event Enable Input 0"] +pub struct PORTEI0_R(crate::FieldReader); +impl PORTEI0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PORTEI0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PORTEI0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PORTEI0` writer - Port Event Enable Input 0"] +pub struct PORTEI0_W<'a> { + w: &'a mut W, +} +impl<'a> PORTEI0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `PID1` reader - Port Event Pin Identifier 1"] +pub struct PID1_R(crate::FieldReader); +impl PID1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PID1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PID1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PID1` writer - Port Event Pin Identifier 1"] +pub struct PID1_W<'a> { + w: &'a mut W, +} +impl<'a> PID1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 8)) | ((value as u32 & 0x1f) << 8); + self.w + } +} +#[doc = "Field `EVACT1` reader - Port Event Action 1"] +pub struct EVACT1_R(crate::FieldReader); +impl EVACT1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVACT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT1` writer - Port Event Action 1"] +pub struct EVACT1_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 13)) | ((value as u32 & 0x03) << 13); + self.w + } +} +#[doc = "Field `PORTEI1` reader - Port Event Enable Input 1"] +pub struct PORTEI1_R(crate::FieldReader); +impl PORTEI1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PORTEI1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PORTEI1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PORTEI1` writer - Port Event Enable Input 1"] +pub struct PORTEI1_W<'a> { + w: &'a mut W, +} +impl<'a> PORTEI1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `PID2` reader - Port Event Pin Identifier 2"] +pub struct PID2_R(crate::FieldReader); +impl PID2_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PID2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PID2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PID2` writer - Port Event Pin Identifier 2"] +pub struct PID2_W<'a> { + w: &'a mut W, +} +impl<'a> PID2_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 16)) | ((value as u32 & 0x1f) << 16); + self.w + } +} +#[doc = "Field `EVACT2` reader - Port Event Action 2"] +pub struct EVACT2_R(crate::FieldReader); +impl EVACT2_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVACT2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT2` writer - Port Event Action 2"] +pub struct EVACT2_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT2_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 21)) | ((value as u32 & 0x03) << 21); + self.w + } +} +#[doc = "Field `PORTEI2` reader - Port Event Enable Input 2"] +pub struct PORTEI2_R(crate::FieldReader); +impl PORTEI2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PORTEI2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PORTEI2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PORTEI2` writer - Port Event Enable Input 2"] +pub struct PORTEI2_W<'a> { + w: &'a mut W, +} +impl<'a> PORTEI2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `PID3` reader - Port Event Pin Identifier 3"] +pub struct PID3_R(crate::FieldReader); +impl PID3_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PID3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PID3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PID3` writer - Port Event Pin Identifier 3"] +pub struct PID3_W<'a> { + w: &'a mut W, +} +impl<'a> PID3_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 24)) | ((value as u32 & 0x1f) << 24); + self.w + } +} +#[doc = "Field `EVACT3` reader - Port Event Action 3"] +pub struct EVACT3_R(crate::FieldReader); +impl EVACT3_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVACT3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT3` writer - Port Event Action 3"] +pub struct EVACT3_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT3_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 29)) | ((value as u32 & 0x03) << 29); + self.w + } +} +#[doc = "Field `PORTEI3` reader - Port Event Enable Input 3"] +pub struct PORTEI3_R(crate::FieldReader); +impl PORTEI3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PORTEI3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PORTEI3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PORTEI3` writer - Port Event Enable Input 3"] +pub struct PORTEI3_W<'a> { + w: &'a mut W, +} +impl<'a> PORTEI3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Port Event Pin Identifier 0"] + #[inline(always)] + pub fn pid0(&self) -> PID0_R { + PID0_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:6 - Port Event Action 0"] + #[inline(always)] + pub fn evact0(&self) -> EVACT0_R { + EVACT0_R::new(((self.bits >> 5) & 0x03) as u8) + } + #[doc = "Bit 7 - Port Event Enable Input 0"] + #[inline(always)] + pub fn portei0(&self) -> PORTEI0_R { + PORTEI0_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:12 - Port Event Pin Identifier 1"] + #[inline(always)] + pub fn pid1(&self) -> PID1_R { + PID1_R::new(((self.bits >> 8) & 0x1f) as u8) + } + #[doc = "Bits 13:14 - Port Event Action 1"] + #[inline(always)] + pub fn evact1(&self) -> EVACT1_R { + EVACT1_R::new(((self.bits >> 13) & 0x03) as u8) + } + #[doc = "Bit 15 - Port Event Enable Input 1"] + #[inline(always)] + pub fn portei1(&self) -> PORTEI1_R { + PORTEI1_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:20 - Port Event Pin Identifier 2"] + #[inline(always)] + pub fn pid2(&self) -> PID2_R { + PID2_R::new(((self.bits >> 16) & 0x1f) as u8) + } + #[doc = "Bits 21:22 - Port Event Action 2"] + #[inline(always)] + pub fn evact2(&self) -> EVACT2_R { + EVACT2_R::new(((self.bits >> 21) & 0x03) as u8) + } + #[doc = "Bit 23 - Port Event Enable Input 2"] + #[inline(always)] + pub fn portei2(&self) -> PORTEI2_R { + PORTEI2_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bits 24:28 - Port Event Pin Identifier 3"] + #[inline(always)] + pub fn pid3(&self) -> PID3_R { + PID3_R::new(((self.bits >> 24) & 0x1f) as u8) + } + #[doc = "Bits 29:30 - Port Event Action 3"] + #[inline(always)] + pub fn evact3(&self) -> EVACT3_R { + EVACT3_R::new(((self.bits >> 29) & 0x03) as u8) + } + #[doc = "Bit 31 - Port Event Enable Input 3"] + #[inline(always)] + pub fn portei3(&self) -> PORTEI3_R { + PORTEI3_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Port Event Pin Identifier 0"] + #[inline(always)] + pub fn pid0(&mut self) -> PID0_W { + PID0_W { w: self } + } + #[doc = "Bits 5:6 - Port Event Action 0"] + #[inline(always)] + pub fn evact0(&mut self) -> EVACT0_W { + EVACT0_W { w: self } + } + #[doc = "Bit 7 - Port Event Enable Input 0"] + #[inline(always)] + pub fn portei0(&mut self) -> PORTEI0_W { + PORTEI0_W { w: self } + } + #[doc = "Bits 8:12 - Port Event Pin Identifier 1"] + #[inline(always)] + pub fn pid1(&mut self) -> PID1_W { + PID1_W { w: self } + } + #[doc = "Bits 13:14 - Port Event Action 1"] + #[inline(always)] + pub fn evact1(&mut self) -> EVACT1_W { + EVACT1_W { w: self } + } + #[doc = "Bit 15 - Port Event Enable Input 1"] + #[inline(always)] + pub fn portei1(&mut self) -> PORTEI1_W { + PORTEI1_W { w: self } + } + #[doc = "Bits 16:20 - Port Event Pin Identifier 2"] + #[inline(always)] + pub fn pid2(&mut self) -> PID2_W { + PID2_W { w: self } + } + #[doc = "Bits 21:22 - Port Event Action 2"] + #[inline(always)] + pub fn evact2(&mut self) -> EVACT2_W { + EVACT2_W { w: self } + } + #[doc = "Bit 23 - Port Event Enable Input 2"] + #[inline(always)] + pub fn portei2(&mut self) -> PORTEI2_W { + PORTEI2_W { w: self } + } + #[doc = "Bits 24:28 - Port Event Pin Identifier 3"] + #[inline(always)] + pub fn pid3(&mut self) -> PID3_W { + PID3_W { w: self } + } + #[doc = "Bits 29:30 - Port Event Action 3"] + #[inline(always)] + pub fn evact3(&mut self) -> EVACT3_W { + EVACT3_W { w: self } + } + #[doc = "Bit 31 - Port Event Enable Input 3"] + #[inline(always)] + pub fn portei3(&mut self) -> PORTEI3_W { + PORTEI3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Input Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/port/group/in_.rs b/pac/atsamc20n/src/port/group/in_.rs new file mode 100644 index 000000000000..1c8e7396a83e --- /dev/null +++ b/pac/atsamc20n/src/port/group/in_.rs @@ -0,0 +1,31 @@ +#[doc = "Register `IN` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Data Input Value\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [in_](index.html) module"] +pub struct IN_SPEC; +impl crate::RegisterSpec for IN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [in_::R](R) reader structure"] +impl crate::Readable for IN_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets IN to value 0"] +impl crate::Resettable for IN_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/port/group/out.rs b/pac/atsamc20n/src/port/group/out.rs new file mode 100644 index 000000000000..092e8dbd8023 --- /dev/null +++ b/pac/atsamc20n/src/port/group/out.rs @@ -0,0 +1,64 @@ +#[doc = "Register `OUT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OUT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Output Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [out](index.html) module"] +pub struct OUT_SPEC; +impl crate::RegisterSpec for OUT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [out::R](R) reader structure"] +impl crate::Readable for OUT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [out::W](W) writer structure"] +impl crate::Writable for OUT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OUT to value 0"] +impl crate::Resettable for OUT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/port/group/outclr.rs b/pac/atsamc20n/src/port/group/outclr.rs new file mode 100644 index 000000000000..6e734396601f --- /dev/null +++ b/pac/atsamc20n/src/port/group/outclr.rs @@ -0,0 +1,64 @@ +#[doc = "Register `OUTCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OUTCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Output Value Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [outclr](index.html) module"] +pub struct OUTCLR_SPEC; +impl crate::RegisterSpec for OUTCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [outclr::R](R) reader structure"] +impl crate::Readable for OUTCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [outclr::W](W) writer structure"] +impl crate::Writable for OUTCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OUTCLR to value 0"] +impl crate::Resettable for OUTCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/port/group/outset.rs b/pac/atsamc20n/src/port/group/outset.rs new file mode 100644 index 000000000000..6d39122deb4b --- /dev/null +++ b/pac/atsamc20n/src/port/group/outset.rs @@ -0,0 +1,64 @@ +#[doc = "Register `OUTSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OUTSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Output Value Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [outset](index.html) module"] +pub struct OUTSET_SPEC; +impl crate::RegisterSpec for OUTSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [outset::R](R) reader structure"] +impl crate::Readable for OUTSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [outset::W](W) writer structure"] +impl crate::Writable for OUTSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OUTSET to value 0"] +impl crate::Resettable for OUTSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/port/group/outtgl.rs b/pac/atsamc20n/src/port/group/outtgl.rs new file mode 100644 index 000000000000..0f3d87d6476d --- /dev/null +++ b/pac/atsamc20n/src/port/group/outtgl.rs @@ -0,0 +1,64 @@ +#[doc = "Register `OUTTGL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OUTTGL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Output Value Toggle\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [outtgl](index.html) module"] +pub struct OUTTGL_SPEC; +impl crate::RegisterSpec for OUTTGL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [outtgl::R](R) reader structure"] +impl crate::Readable for OUTTGL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [outtgl::W](W) writer structure"] +impl crate::Writable for OUTTGL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OUTTGL to value 0"] +impl crate::Resettable for OUTTGL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/port/group/pincfg.rs b/pac/atsamc20n/src/port/group/pincfg.rs new file mode 100644 index 000000000000..920af6550361 --- /dev/null +++ b/pac/atsamc20n/src/port/group/pincfg.rs @@ -0,0 +1,255 @@ +#[doc = "Register `PINCFG[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PINCFG[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PMUXEN` reader - Select Peripheral Multiplexer"] +pub struct PMUXEN_R(crate::FieldReader); +impl PMUXEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PMUXEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PMUXEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PMUXEN` writer - Select Peripheral Multiplexer"] +pub struct PMUXEN_W<'a> { + w: &'a mut W, +} +impl<'a> PMUXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `INEN` reader - Input Enable"] +pub struct INEN_R(crate::FieldReader); +impl INEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INEN` writer - Input Enable"] +pub struct INEN_W<'a> { + w: &'a mut W, +} +impl<'a> INEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PULLEN` reader - Pull Enable"] +pub struct PULLEN_R(crate::FieldReader); +impl PULLEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PULLEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PULLEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PULLEN` writer - Pull Enable"] +pub struct PULLEN_W<'a> { + w: &'a mut W, +} +impl<'a> PULLEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `DRVSTR` reader - Output Driver Strength Selection"] +pub struct DRVSTR_R(crate::FieldReader); +impl DRVSTR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRVSTR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRVSTR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRVSTR` writer - Output Driver Strength Selection"] +pub struct DRVSTR_W<'a> { + w: &'a mut W, +} +impl<'a> DRVSTR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - Select Peripheral Multiplexer"] + #[inline(always)] + pub fn pmuxen(&self) -> PMUXEN_R { + PMUXEN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Input Enable"] + #[inline(always)] + pub fn inen(&self) -> INEN_R { + INEN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Pull Enable"] + #[inline(always)] + pub fn pullen(&self) -> PULLEN_R { + PULLEN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 6 - Output Driver Strength Selection"] + #[inline(always)] + pub fn drvstr(&self) -> DRVSTR_R { + DRVSTR_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Select Peripheral Multiplexer"] + #[inline(always)] + pub fn pmuxen(&mut self) -> PMUXEN_W { + PMUXEN_W { w: self } + } + #[doc = "Bit 1 - Input Enable"] + #[inline(always)] + pub fn inen(&mut self) -> INEN_W { + INEN_W { w: self } + } + #[doc = "Bit 2 - Pull Enable"] + #[inline(always)] + pub fn pullen(&mut self) -> PULLEN_W { + PULLEN_W { w: self } + } + #[doc = "Bit 6 - Output Driver Strength Selection"] + #[inline(always)] + pub fn drvstr(&mut self) -> DRVSTR_W { + DRVSTR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Pin Configuration n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pincfg](index.html) module"] +pub struct PINCFG_SPEC; +impl crate::RegisterSpec for PINCFG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [pincfg::R](R) reader structure"] +impl crate::Readable for PINCFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [pincfg::W](W) writer structure"] +impl crate::Writable for PINCFG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PINCFG[%s] +to value 0"] +impl crate::Resettable for PINCFG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/port/group/pmux.rs b/pac/atsamc20n/src/port/group/pmux.rs new file mode 100644 index 000000000000..79c991a99daf --- /dev/null +++ b/pac/atsamc20n/src/port/group/pmux.rs @@ -0,0 +1,141 @@ +#[doc = "Register `PMUX[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PMUX[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PMUXE` reader - Peripheral Multiplexing for Even-Numbered Pin"] +pub struct PMUXE_R(crate::FieldReader); +impl PMUXE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PMUXE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PMUXE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PMUXE` writer - Peripheral Multiplexing for Even-Numbered Pin"] +pub struct PMUXE_W<'a> { + w: &'a mut W, +} +impl<'a> PMUXE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +#[doc = "Field `PMUXO` reader - Peripheral Multiplexing for Odd-Numbered Pin"] +pub struct PMUXO_R(crate::FieldReader); +impl PMUXO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PMUXO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PMUXO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PMUXO` writer - Peripheral Multiplexing for Odd-Numbered Pin"] +pub struct PMUXO_W<'a> { + w: &'a mut W, +} +impl<'a> PMUXO_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 4)) | ((value as u8 & 0x0f) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Peripheral Multiplexing for Even-Numbered Pin"] + #[inline(always)] + pub fn pmuxe(&self) -> PMUXE_R { + PMUXE_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Peripheral Multiplexing for Odd-Numbered Pin"] + #[inline(always)] + pub fn pmuxo(&self) -> PMUXO_R { + PMUXO_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Peripheral Multiplexing for Even-Numbered Pin"] + #[inline(always)] + pub fn pmuxe(&mut self) -> PMUXE_W { + PMUXE_W { w: self } + } + #[doc = "Bits 4:7 - Peripheral Multiplexing for Odd-Numbered Pin"] + #[inline(always)] + pub fn pmuxo(&mut self) -> PMUXO_W { + PMUXO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Peripheral Multiplexing n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pmux](index.html) module"] +pub struct PMUX_SPEC; +impl crate::RegisterSpec for PMUX_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [pmux::R](R) reader structure"] +impl crate::Readable for PMUX_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [pmux::W](W) writer structure"] +impl crate::Writable for PMUX_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PMUX[%s] +to value 0"] +impl crate::Resettable for PMUX_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/port/group/wrconfig.rs b/pac/atsamc20n/src/port/group/wrconfig.rs new file mode 100644 index 000000000000..c87e4f174728 --- /dev/null +++ b/pac/atsamc20n/src/port/group/wrconfig.rs @@ -0,0 +1,268 @@ +#[doc = "Register `WRCONFIG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PINMASK` writer - Pin Mask for Multiple Pin Configuration"] +pub struct PINMASK_W<'a> { + w: &'a mut W, +} +impl<'a> PINMASK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +#[doc = "Field `PMUXEN` writer - Select Peripheral Multiplexer"] +pub struct PMUXEN_W<'a> { + w: &'a mut W, +} +impl<'a> PMUXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `INEN` writer - Input Enable"] +pub struct INEN_W<'a> { + w: &'a mut W, +} +impl<'a> INEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `PULLEN` writer - Pull Enable"] +pub struct PULLEN_W<'a> { + w: &'a mut W, +} +impl<'a> PULLEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `DRVSTR` writer - Output Driver Strength Selection"] +pub struct DRVSTR_W<'a> { + w: &'a mut W, +} +impl<'a> DRVSTR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `PMUX` writer - Peripheral Multiplexing Template"] +pub struct PMUX_W<'a> { + w: &'a mut W, +} +impl<'a> PMUX_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Field `WRPMUX` writer - Write PMUX Registers"] +pub struct WRPMUX_W<'a> { + w: &'a mut W, +} +impl<'a> WRPMUX_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Field `WRPINCFG` writer - Write PINCFG Registers"] +pub struct WRPINCFG_W<'a> { + w: &'a mut W, +} +impl<'a> WRPINCFG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +#[doc = "Field `HWSEL` writer - Half-Word Select"] +pub struct HWSEL_W<'a> { + w: &'a mut W, +} +impl<'a> HWSEL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl W { + #[doc = "Bits 0:15 - Pin Mask for Multiple Pin Configuration"] + #[inline(always)] + pub fn pinmask(&mut self) -> PINMASK_W { + PINMASK_W { w: self } + } + #[doc = "Bit 16 - Select Peripheral Multiplexer"] + #[inline(always)] + pub fn pmuxen(&mut self) -> PMUXEN_W { + PMUXEN_W { w: self } + } + #[doc = "Bit 17 - Input Enable"] + #[inline(always)] + pub fn inen(&mut self) -> INEN_W { + INEN_W { w: self } + } + #[doc = "Bit 18 - Pull Enable"] + #[inline(always)] + pub fn pullen(&mut self) -> PULLEN_W { + PULLEN_W { w: self } + } + #[doc = "Bit 22 - Output Driver Strength Selection"] + #[inline(always)] + pub fn drvstr(&mut self) -> DRVSTR_W { + DRVSTR_W { w: self } + } + #[doc = "Bits 24:27 - Peripheral Multiplexing Template"] + #[inline(always)] + pub fn pmux(&mut self) -> PMUX_W { + PMUX_W { w: self } + } + #[doc = "Bit 28 - Write PMUX Registers"] + #[inline(always)] + pub fn wrpmux(&mut self) -> WRPMUX_W { + WRPMUX_W { w: self } + } + #[doc = "Bit 30 - Write PINCFG Registers"] + #[inline(always)] + pub fn wrpincfg(&mut self) -> WRPINCFG_W { + WRPINCFG_W { w: self } + } + #[doc = "Bit 31 - Half-Word Select"] + #[inline(always)] + pub fn hwsel(&mut self) -> HWSEL_W { + HWSEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Write Configuration\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wrconfig](index.html) module"] +pub struct WRCONFIG_SPEC; +impl crate::RegisterSpec for WRCONFIG_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [wrconfig::W](W) writer structure"] +impl crate::Writable for WRCONFIG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WRCONFIG to value 0"] +impl crate::Resettable for WRCONFIG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/rstc.rs b/pac/atsamc20n/src/rstc.rs new file mode 100644 index 000000000000..327b511df28a --- /dev/null +++ b/pac/atsamc20n/src/rstc.rs @@ -0,0 +1,10 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Reset Cause"] + pub rcause: crate::Reg, +} +#[doc = "RCAUSE register accessor: an alias for `Reg`"] +pub type RCAUSE = crate::Reg; +#[doc = "Reset Cause"] +pub mod rcause; diff --git a/pac/atsamc20n/src/rstc/rcause.rs b/pac/atsamc20n/src/rstc/rcause.rs new file mode 100644 index 000000000000..3dc13496e74b --- /dev/null +++ b/pac/atsamc20n/src/rstc/rcause.rs @@ -0,0 +1,153 @@ +#[doc = "Register `RCAUSE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `POR` reader - Power On Reset"] +pub struct POR_R(crate::FieldReader); +impl POR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + POR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for POR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODCORE` reader - Brown Out CORE Detector Reset"] +pub struct BODCORE_R(crate::FieldReader); +impl BODCORE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODCORE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODCORE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODVDD` reader - Brown Out VDD Detector Reset"] +pub struct BODVDD_R(crate::FieldReader); +impl BODVDD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODVDD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODVDD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXT` reader - External Reset"] +pub struct EXT_R(crate::FieldReader); +impl EXT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WDT` reader - Watchdog Reset"] +pub struct WDT_R(crate::FieldReader); +impl WDT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WDT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WDT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYST` reader - System Reset Request"] +pub struct SYST_R(crate::FieldReader); +impl SYST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Power On Reset"] + #[inline(always)] + pub fn por(&self) -> POR_R { + POR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Brown Out CORE Detector Reset"] + #[inline(always)] + pub fn bodcore(&self) -> BODCORE_R { + BODCORE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Brown Out VDD Detector Reset"] + #[inline(always)] + pub fn bodvdd(&self) -> BODVDD_R { + BODVDD_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 4 - External Reset"] + #[inline(always)] + pub fn ext(&self) -> EXT_R { + EXT_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Watchdog Reset"] + #[inline(always)] + pub fn wdt(&self) -> WDT_R { + WDT_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - System Reset Request"] + #[inline(always)] + pub fn syst(&self) -> SYST_R { + SYST_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +#[doc = "Reset Cause\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rcause](index.html) module"] +pub struct RCAUSE_SPEC; +impl crate::RegisterSpec for RCAUSE_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [rcause::R](R) reader structure"] +impl crate::Readable for RCAUSE_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets RCAUSE to value 0"] +impl crate::Resettable for RCAUSE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/rtc.rs b/pac/atsamc20n/src/rtc.rs new file mode 100644 index 000000000000..62f424cb1a8e --- /dev/null +++ b/pac/atsamc20n/src/rtc.rs @@ -0,0 +1,120 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved_0_mode0: [u8; 0x25], +} +impl RegisterBlock { + #[doc = "0x00..0x25 - Clock/Calendar with Alarm"] + #[inline(always)] + pub fn mode2(&self) -> &MODE2 { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const MODE2) } + } + #[doc = "0x00..0x24 - 16-bit Counter with Two 16-bit Compares"] + #[inline(always)] + pub fn mode1(&self) -> &MODE1 { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const MODE1) } + } + #[doc = "0x00..0x24 - 32-bit Counter with Single 32-bit Compare"] + #[inline(always)] + pub fn mode0(&self) -> &MODE0 { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const MODE0) } + } +} +#[doc = r"Register block"] +#[repr(C)] +pub struct MODE0 { + #[doc = "0x00 - MODE0 Control A"] + pub ctrla: crate::Reg, + _reserved1: [u8; 0x02], + #[doc = "0x04 - MODE0 Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x08 - MODE0 Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x0a - MODE0 Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x0c - MODE0 Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x0e - Debug Control"] + pub dbgctrl: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x10 - MODE0 Synchronization Busy Status"] + pub syncbusy: crate::Reg, + #[doc = "0x14 - Frequency Correction"] + pub freqcorr: crate::Reg, + _reserved8: [u8; 0x03], + #[doc = "0x18 - MODE0 Counter Value"] + pub count: crate::Reg, + _reserved9: [u8; 0x04], + #[doc = "0x20 - MODE0 Compare n Value"] + pub comp: crate::Reg, +} +#[doc = r"Register block"] +#[doc = "32-bit Counter with Single 32-bit Compare"] +pub mod mode0; +#[doc = r"Register block"] +#[repr(C)] +pub struct MODE1 { + #[doc = "0x00 - MODE1 Control A"] + pub ctrla: crate::Reg, + _reserved1: [u8; 0x02], + #[doc = "0x04 - MODE1 Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x08 - MODE1 Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x0a - MODE1 Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x0c - MODE1 Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x0e - Debug Control"] + pub dbgctrl: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x10 - MODE1 Synchronization Busy Status"] + pub syncbusy: crate::Reg, + #[doc = "0x14 - Frequency Correction"] + pub freqcorr: crate::Reg, + _reserved8: [u8; 0x03], + #[doc = "0x18 - MODE1 Counter Value"] + pub count: crate::Reg, + _reserved9: [u8; 0x02], + #[doc = "0x1c - MODE1 Counter Period"] + pub per: crate::Reg, + _reserved10: [u8; 0x02], + #[doc = "0x20 - MODE1 Compare n Value"] + pub comp: [crate::Reg; 2], +} +#[doc = r"Register block"] +#[doc = "16-bit Counter with Two 16-bit Compares"] +pub mod mode1; +#[doc = r"Register block"] +#[repr(C)] +pub struct MODE2 { + #[doc = "0x00 - MODE2 Control A"] + pub ctrla: crate::Reg, + _reserved1: [u8; 0x02], + #[doc = "0x04 - MODE2 Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x08 - MODE2 Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x0a - MODE2 Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x0c - MODE2 Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x0e - Debug Control"] + pub dbgctrl: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x10 - MODE2 Synchronization Busy Status"] + pub syncbusy: crate::Reg, + #[doc = "0x14 - Frequency Correction"] + pub freqcorr: crate::Reg, + _reserved8: [u8; 0x03], + #[doc = "0x18 - MODE2 Clock Value"] + pub clock: crate::Reg, + _reserved9: [u8; 0x04], + #[doc = "0x20 - MODE2_ALARM Alarm n Value"] + pub alarm: crate::Reg, + #[doc = "0x24 - MODE2_ALARM Alarm n Mask"] + pub mask: crate::Reg, +} +#[doc = r"Register block"] +#[doc = "Clock/Calendar with Alarm"] +pub mod mode2; diff --git a/pac/atsamc20n/src/rtc/mode0.rs b/pac/atsamc20n/src/rtc/mode0.rs new file mode 100644 index 000000000000..9ce5c3808169 --- /dev/null +++ b/pac/atsamc20n/src/rtc/mode0.rs @@ -0,0 +1,40 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "MODE0 Control A"] +pub mod ctrla; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "MODE0 Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "MODE0 Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "MODE0 Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "MODE0 Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "MODE0 Synchronization Busy Status"] +pub mod syncbusy; +#[doc = "FREQCORR register accessor: an alias for `Reg`"] +pub type FREQCORR = crate::Reg; +#[doc = "Frequency Correction"] +pub mod freqcorr; +#[doc = "COUNT register accessor: an alias for `Reg`"] +pub type COUNT = crate::Reg; +#[doc = "MODE0 Counter Value"] +pub mod count; +#[doc = "COMP register accessor: an alias for `Reg`"] +pub type COMP = crate::Reg; +#[doc = "MODE0 Compare n Value"] +pub mod comp; diff --git a/pac/atsamc20n/src/rtc/mode0/comp.rs b/pac/atsamc20n/src/rtc/mode0/comp.rs new file mode 100644 index 000000000000..a909d3cea2d3 --- /dev/null +++ b/pac/atsamc20n/src/rtc/mode0/comp.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COMP` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COMP` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COMP` reader - Compare Value"] +pub struct COMP_R(crate::FieldReader); +impl COMP_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COMP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP` writer - Compare Value"] +pub struct COMP_W<'a> { + w: &'a mut W, +} +impl<'a> COMP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Compare Value"] + #[inline(always)] + pub fn comp(&self) -> COMP_R { + COMP_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Compare Value"] + #[inline(always)] + pub fn comp(&mut self) -> COMP_W { + COMP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE0 Compare n Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [comp](index.html) module"] +pub struct COMP_SPEC; +impl crate::RegisterSpec for COMP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [comp::R](R) reader structure"] +impl crate::Readable for COMP_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [comp::W](W) writer structure"] +impl crate::Writable for COMP_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COMP to value 0"] +impl crate::Resettable for COMP_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/rtc/mode0/count.rs b/pac/atsamc20n/src/rtc/mode0/count.rs new file mode 100644 index 000000000000..cf880b5e77a6 --- /dev/null +++ b/pac/atsamc20n/src/rtc/mode0/count.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE0 Counter Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count](index.html) module"] +pub struct COUNT_SPEC; +impl crate::RegisterSpec for COUNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [count::R](R) reader structure"] +impl crate::Readable for COUNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count::W](W) writer structure"] +impl crate::Writable for COUNT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT to value 0"] +impl crate::Resettable for COUNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/rtc/mode0/ctrla.rs b/pac/atsamc20n/src/rtc/mode0/ctrla.rs new file mode 100644 index 000000000000..423877bd087d --- /dev/null +++ b/pac/atsamc20n/src/rtc/mode0/ctrla.rs @@ -0,0 +1,569 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: Mode 0: 32-bit Counter"] + COUNT32 = 0, + #[doc = "1: Mode 1: 16-bit Counter"] + COUNT16 = 1, + #[doc = "2: Mode 2: Clock/Calendar"] + CLOCK = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::COUNT32), + 1 => Some(MODE_A::COUNT16), + 2 => Some(MODE_A::CLOCK), + _ => None, + } + } + #[doc = "Checks if the value of the field is `COUNT32`"] + #[inline(always)] + pub fn is_count32(&self) -> bool { + **self == MODE_A::COUNT32 + } + #[doc = "Checks if the value of the field is `COUNT16`"] + #[inline(always)] + pub fn is_count16(&self) -> bool { + **self == MODE_A::COUNT16 + } + #[doc = "Checks if the value of the field is `CLOCK`"] + #[inline(always)] + pub fn is_clock(&self) -> bool { + **self == MODE_A::CLOCK + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Mode 0: 32-bit Counter"] + #[inline(always)] + pub fn count32(self) -> &'a mut W { + self.variant(MODE_A::COUNT32) + } + #[doc = "Mode 1: 16-bit Counter"] + #[inline(always)] + pub fn count16(self) -> &'a mut W { + self.variant(MODE_A::COUNT16) + } + #[doc = "Mode 2: Clock/Calendar"] + #[inline(always)] + pub fn clock(self) -> &'a mut W { + self.variant(MODE_A::CLOCK) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u16 & 0x03) << 2); + self.w + } +} +#[doc = "Field `MATCHCLR` reader - Clear on Match"] +pub struct MATCHCLR_R(crate::FieldReader); +impl MATCHCLR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MATCHCLR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MATCHCLR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MATCHCLR` writer - Clear on Match"] +pub struct MATCHCLR_W<'a> { + w: &'a mut W, +} +impl<'a> MATCHCLR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: CLK_RTC_CNT = GCLK_RTC/1"] + OFF = 0, + #[doc = "1: CLK_RTC_CNT = GCLK_RTC/1"] + DIV1 = 1, + #[doc = "2: CLK_RTC_CNT = GCLK_RTC/2"] + DIV2 = 2, + #[doc = "3: CLK_RTC_CNT = GCLK_RTC/4"] + DIV4 = 3, + #[doc = "4: CLK_RTC_CNT = GCLK_RTC/8"] + DIV8 = 4, + #[doc = "5: CLK_RTC_CNT = GCLK_RTC/16"] + DIV16 = 5, + #[doc = "6: CLK_RTC_CNT = GCLK_RTC/32"] + DIV32 = 6, + #[doc = "7: CLK_RTC_CNT = GCLK_RTC/64"] + DIV64 = 7, + #[doc = "8: CLK_RTC_CNT = GCLK_RTC/128"] + DIV128 = 8, + #[doc = "9: CLK_RTC_CNT = GCLK_RTC/256"] + DIV256 = 9, + #[doc = "10: CLK_RTC_CNT = GCLK_RTC/512"] + DIV512 = 10, + #[doc = "11: CLK_RTC_CNT = GCLK_RTC/1024"] + DIV1024 = 11, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCALER_A::OFF), + 1 => Some(PRESCALER_A::DIV1), + 2 => Some(PRESCALER_A::DIV2), + 3 => Some(PRESCALER_A::DIV4), + 4 => Some(PRESCALER_A::DIV8), + 5 => Some(PRESCALER_A::DIV16), + 6 => Some(PRESCALER_A::DIV32), + 7 => Some(PRESCALER_A::DIV64), + 8 => Some(PRESCALER_A::DIV128), + 9 => Some(PRESCALER_A::DIV256), + 10 => Some(PRESCALER_A::DIV512), + 11 => Some(PRESCALER_A::DIV1024), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == PRESCALER_A::OFF + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == PRESCALER_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == PRESCALER_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == PRESCALER_A::DIV128 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV512`"] + #[inline(always)] + pub fn is_div512(&self) -> bool { + **self == PRESCALER_A::DIV512 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PRESCALER_A::DIV1024 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(PRESCALER_A::OFF) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV32) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV128) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/512"] + #[inline(always)] + pub fn div512(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV512) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 8)) | ((value as u16 & 0x0f) << 8); + self.w + } +} +#[doc = "Field `COUNTSYNC` reader - Count Read Synchronization Enable"] +pub struct COUNTSYNC_R(crate::FieldReader); +impl COUNTSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNTSYNC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNTSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNTSYNC` writer - Count Read Synchronization Enable"] +pub struct COUNTSYNC_W<'a> { + w: &'a mut W, +} +impl<'a> COUNTSYNC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:3 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bit 7 - Clear on Match"] + #[inline(always)] + pub fn matchclr(&self) -> MATCHCLR_R { + MATCHCLR_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:11 - Prescaler"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 15 - Count Read Synchronization Enable"] + #[inline(always)] + pub fn countsync(&self) -> COUNTSYNC_R { + COUNTSYNC_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:3 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 7 - Clear on Match"] + #[inline(always)] + pub fn matchclr(&mut self) -> MATCHCLR_W { + MATCHCLR_W { w: self } + } + #[doc = "Bits 8:11 - Prescaler"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Bit 15 - Count Read Synchronization Enable"] + #[inline(always)] + pub fn countsync(&mut self) -> COUNTSYNC_W { + COUNTSYNC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE0 Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/rtc/mode0/dbgctrl.rs b/pac/atsamc20n/src/rtc/mode0/dbgctrl.rs new file mode 100644 index 000000000000..0383e70d0429 --- /dev/null +++ b/pac/atsamc20n/src/rtc/mode0/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Run During Debug"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Run During Debug"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/rtc/mode0/evctrl.rs b/pac/atsamc20n/src/rtc/mode0/evctrl.rs new file mode 100644 index 000000000000..c73647759dbe --- /dev/null +++ b/pac/atsamc20n/src/rtc/mode0/evctrl.rs @@ -0,0 +1,536 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PEREO0` reader - Periodic Interval 0 Event Output Enable"] +pub struct PEREO0_R(crate::FieldReader); +impl PEREO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO0` writer - Periodic Interval 0 Event Output Enable"] +pub struct PEREO0_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `PEREO1` reader - Periodic Interval 1 Event Output Enable"] +pub struct PEREO1_R(crate::FieldReader); +impl PEREO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO1` writer - Periodic Interval 1 Event Output Enable"] +pub struct PEREO1_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PEREO2` reader - Periodic Interval 2 Event Output Enable"] +pub struct PEREO2_R(crate::FieldReader); +impl PEREO2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO2` writer - Periodic Interval 2 Event Output Enable"] +pub struct PEREO2_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PEREO3` reader - Periodic Interval 3 Event Output Enable"] +pub struct PEREO3_R(crate::FieldReader); +impl PEREO3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO3` writer - Periodic Interval 3 Event Output Enable"] +pub struct PEREO3_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PEREO4` reader - Periodic Interval 4 Event Output Enable"] +pub struct PEREO4_R(crate::FieldReader); +impl PEREO4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO4` writer - Periodic Interval 4 Event Output Enable"] +pub struct PEREO4_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PEREO5` reader - Periodic Interval 5 Event Output Enable"] +pub struct PEREO5_R(crate::FieldReader); +impl PEREO5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO5` writer - Periodic Interval 5 Event Output Enable"] +pub struct PEREO5_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PEREO6` reader - Periodic Interval 6 Event Output Enable"] +pub struct PEREO6_R(crate::FieldReader); +impl PEREO6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO6` writer - Periodic Interval 6 Event Output Enable"] +pub struct PEREO6_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PEREO7` reader - Periodic Interval 7 Event Output Enable"] +pub struct PEREO7_R(crate::FieldReader); +impl PEREO7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO7` writer - Periodic Interval 7 Event Output Enable"] +pub struct PEREO7_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CMPEO0` reader - Compare 0 Event Output Enable"] +pub struct CMPEO0_R(crate::FieldReader); +impl CMPEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMPEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMPEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMPEO0` writer - Compare 0 Event Output Enable"] +pub struct CMPEO0_W<'a> { + w: &'a mut W, +} +impl<'a> CMPEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `OVFEO` reader - Overflow Event Output Enable"] +pub struct OVFEO_R(crate::FieldReader); +impl OVFEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVFEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVFEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVFEO` writer - Overflow Event Output Enable"] +pub struct OVFEO_W<'a> { + w: &'a mut W, +} +impl<'a> OVFEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Event Output Enable"] + #[inline(always)] + pub fn pereo0(&self) -> PEREO0_R { + PEREO0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Event Output Enable"] + #[inline(always)] + pub fn pereo1(&self) -> PEREO1_R { + PEREO1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Event Output Enable"] + #[inline(always)] + pub fn pereo2(&self) -> PEREO2_R { + PEREO2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Event Output Enable"] + #[inline(always)] + pub fn pereo3(&self) -> PEREO3_R { + PEREO3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Event Output Enable"] + #[inline(always)] + pub fn pereo4(&self) -> PEREO4_R { + PEREO4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Event Output Enable"] + #[inline(always)] + pub fn pereo5(&self) -> PEREO5_R { + PEREO5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Event Output Enable"] + #[inline(always)] + pub fn pereo6(&self) -> PEREO6_R { + PEREO6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Event Output Enable"] + #[inline(always)] + pub fn pereo7(&self) -> PEREO7_R { + PEREO7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Compare 0 Event Output Enable"] + #[inline(always)] + pub fn cmpeo0(&self) -> CMPEO0_R { + CMPEO0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&self) -> OVFEO_R { + OVFEO_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Event Output Enable"] + #[inline(always)] + pub fn pereo0(&mut self) -> PEREO0_W { + PEREO0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1 Event Output Enable"] + #[inline(always)] + pub fn pereo1(&mut self) -> PEREO1_W { + PEREO1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2 Event Output Enable"] + #[inline(always)] + pub fn pereo2(&mut self) -> PEREO2_W { + PEREO2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3 Event Output Enable"] + #[inline(always)] + pub fn pereo3(&mut self) -> PEREO3_W { + PEREO3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4 Event Output Enable"] + #[inline(always)] + pub fn pereo4(&mut self) -> PEREO4_W { + PEREO4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5 Event Output Enable"] + #[inline(always)] + pub fn pereo5(&mut self) -> PEREO5_W { + PEREO5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6 Event Output Enable"] + #[inline(always)] + pub fn pereo6(&mut self) -> PEREO6_W { + PEREO6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7 Event Output Enable"] + #[inline(always)] + pub fn pereo7(&mut self) -> PEREO7_W { + PEREO7_W { w: self } + } + #[doc = "Bit 8 - Compare 0 Event Output Enable"] + #[inline(always)] + pub fn cmpeo0(&mut self) -> CMPEO0_W { + CMPEO0_W { w: self } + } + #[doc = "Bit 15 - Overflow Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&mut self) -> OVFEO_W { + OVFEO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE0 Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/rtc/mode0/freqcorr.rs b/pac/atsamc20n/src/rtc/mode0/freqcorr.rs new file mode 100644 index 000000000000..043ba6f88eb2 --- /dev/null +++ b/pac/atsamc20n/src/rtc/mode0/freqcorr.rs @@ -0,0 +1,150 @@ +#[doc = "Register `FREQCORR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FREQCORR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `VALUE` reader - Correction Value"] +pub struct VALUE_R(crate::FieldReader); +impl VALUE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + VALUE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VALUE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VALUE` writer - Correction Value"] +pub struct VALUE_W<'a> { + w: &'a mut W, +} +impl<'a> VALUE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x7f) | (value as u8 & 0x7f); + self.w + } +} +#[doc = "Field `SIGN` reader - Correction Sign"] +pub struct SIGN_R(crate::FieldReader); +impl SIGN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SIGN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SIGN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SIGN` writer - Correction Sign"] +pub struct SIGN_W<'a> { + w: &'a mut W, +} +impl<'a> SIGN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bits 0:6 - Correction Value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bit 7 - Correction Sign"] + #[inline(always)] + pub fn sign(&self) -> SIGN_R { + SIGN_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:6 - Correction Value"] + #[inline(always)] + pub fn value(&mut self) -> VALUE_W { + VALUE_W { w: self } + } + #[doc = "Bit 7 - Correction Sign"] + #[inline(always)] + pub fn sign(&mut self) -> SIGN_W { + SIGN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Frequency Correction\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [freqcorr](index.html) module"] +pub struct FREQCORR_SPEC; +impl crate::RegisterSpec for FREQCORR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [freqcorr::R](R) reader structure"] +impl crate::Readable for FREQCORR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [freqcorr::W](W) writer structure"] +impl crate::Writable for FREQCORR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets FREQCORR to value 0"] +impl crate::Resettable for FREQCORR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/rtc/mode0/intenclr.rs b/pac/atsamc20n/src/rtc/mode0/intenclr.rs new file mode 100644 index 000000000000..8be5e2c3920b --- /dev/null +++ b/pac/atsamc20n/src/rtc/mode0/intenclr.rs @@ -0,0 +1,536 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER0` reader - Periodic Interval 0 Interrupt Enable"] +pub struct PER0_R(crate::FieldReader); +impl PER0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER0` writer - Periodic Interval 0 Interrupt Enable"] +pub struct PER0_W<'a> { + w: &'a mut W, +} +impl<'a> PER0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PER1` reader - Periodic Interval 1 Interrupt Enable"] +pub struct PER1_R(crate::FieldReader); +impl PER1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER1` writer - Periodic Interval 1 Interrupt Enable"] +pub struct PER1_W<'a> { + w: &'a mut W, +} +impl<'a> PER1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PER2` reader - Periodic Interval 2 Interrupt Enable"] +pub struct PER2_R(crate::FieldReader); +impl PER2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER2` writer - Periodic Interval 2 Interrupt Enable"] +pub struct PER2_W<'a> { + w: &'a mut W, +} +impl<'a> PER2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PER3` reader - Periodic Interval 3 Interrupt Enable"] +pub struct PER3_R(crate::FieldReader); +impl PER3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER3` writer - Periodic Interval 3 Interrupt Enable"] +pub struct PER3_W<'a> { + w: &'a mut W, +} +impl<'a> PER3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PER4` reader - Periodic Interval 4 Interrupt Enable"] +pub struct PER4_R(crate::FieldReader); +impl PER4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER4` writer - Periodic Interval 4 Interrupt Enable"] +pub struct PER4_W<'a> { + w: &'a mut W, +} +impl<'a> PER4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PER5` reader - Periodic Interval 5 Interrupt Enable"] +pub struct PER5_R(crate::FieldReader); +impl PER5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER5` writer - Periodic Interval 5 Interrupt Enable"] +pub struct PER5_W<'a> { + w: &'a mut W, +} +impl<'a> PER5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PER6` reader - Periodic Interval 6 Interrupt Enable"] +pub struct PER6_R(crate::FieldReader); +impl PER6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER6` writer - Periodic Interval 6 Interrupt Enable"] +pub struct PER6_W<'a> { + w: &'a mut W, +} +impl<'a> PER6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PER7` reader - Periodic Interval 7 Interrupt Enable"] +pub struct PER7_R(crate::FieldReader); +impl PER7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER7` writer - Periodic Interval 7 Interrupt Enable"] +pub struct PER7_W<'a> { + w: &'a mut W, +} +impl<'a> PER7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CMP0` reader - Compare 0 Interrupt Enable"] +pub struct CMP0_R(crate::FieldReader); +impl CMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP0` writer - Compare 0 Interrupt Enable"] +pub struct CMP0_W<'a> { + w: &'a mut W, +} +impl<'a> CMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + pub fn per0(&self) -> PER0_R { + PER0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + pub fn per1(&self) -> PER1_R { + PER1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + pub fn per2(&self) -> PER2_R { + PER2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + pub fn per3(&self) -> PER3_R { + PER3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + pub fn per4(&self) -> PER4_R { + PER4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + pub fn per5(&self) -> PER5_R { + PER5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + pub fn per6(&self) -> PER6_R { + PER6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + pub fn per7(&self) -> PER7_R { + PER7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&self) -> CMP0_R { + CMP0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + pub fn per0(&mut self) -> PER0_W { + PER0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + pub fn per1(&mut self) -> PER1_W { + PER1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + pub fn per2(&mut self) -> PER2_W { + PER2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + pub fn per3(&mut self) -> PER3_W { + PER3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + pub fn per4(&mut self) -> PER4_W { + PER4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + pub fn per5(&mut self) -> PER5_W { + PER5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + pub fn per6(&mut self) -> PER6_W { + PER6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + pub fn per7(&mut self) -> PER7_W { + PER7_W { w: self } + } + #[doc = "Bit 8 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&mut self) -> CMP0_W { + CMP0_W { w: self } + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE0 Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/rtc/mode0/intenset.rs b/pac/atsamc20n/src/rtc/mode0/intenset.rs new file mode 100644 index 000000000000..7228f5d486f5 --- /dev/null +++ b/pac/atsamc20n/src/rtc/mode0/intenset.rs @@ -0,0 +1,536 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER0` reader - Periodic Interval 0 Interrupt Enable"] +pub struct PER0_R(crate::FieldReader); +impl PER0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER0` writer - Periodic Interval 0 Interrupt Enable"] +pub struct PER0_W<'a> { + w: &'a mut W, +} +impl<'a> PER0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PER1` reader - Periodic Interval 1 Interrupt Enable"] +pub struct PER1_R(crate::FieldReader); +impl PER1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER1` writer - Periodic Interval 1 Interrupt Enable"] +pub struct PER1_W<'a> { + w: &'a mut W, +} +impl<'a> PER1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PER2` reader - Periodic Interval 2 Interrupt Enable"] +pub struct PER2_R(crate::FieldReader); +impl PER2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER2` writer - Periodic Interval 2 Interrupt Enable"] +pub struct PER2_W<'a> { + w: &'a mut W, +} +impl<'a> PER2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PER3` reader - Periodic Interval 3 Interrupt Enable"] +pub struct PER3_R(crate::FieldReader); +impl PER3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER3` writer - Periodic Interval 3 Interrupt Enable"] +pub struct PER3_W<'a> { + w: &'a mut W, +} +impl<'a> PER3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PER4` reader - Periodic Interval 4 Interrupt Enable"] +pub struct PER4_R(crate::FieldReader); +impl PER4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER4` writer - Periodic Interval 4 Interrupt Enable"] +pub struct PER4_W<'a> { + w: &'a mut W, +} +impl<'a> PER4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PER5` reader - Periodic Interval 5 Interrupt Enable"] +pub struct PER5_R(crate::FieldReader); +impl PER5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER5` writer - Periodic Interval 5 Interrupt Enable"] +pub struct PER5_W<'a> { + w: &'a mut W, +} +impl<'a> PER5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PER6` reader - Periodic Interval 6 Interrupt Enable"] +pub struct PER6_R(crate::FieldReader); +impl PER6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER6` writer - Periodic Interval 6 Interrupt Enable"] +pub struct PER6_W<'a> { + w: &'a mut W, +} +impl<'a> PER6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PER7` reader - Periodic Interval 7 Interrupt Enable"] +pub struct PER7_R(crate::FieldReader); +impl PER7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER7` writer - Periodic Interval 7 Interrupt Enable"] +pub struct PER7_W<'a> { + w: &'a mut W, +} +impl<'a> PER7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CMP0` reader - Compare 0 Interrupt Enable"] +pub struct CMP0_R(crate::FieldReader); +impl CMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP0` writer - Compare 0 Interrupt Enable"] +pub struct CMP0_W<'a> { + w: &'a mut W, +} +impl<'a> CMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + pub fn per0(&self) -> PER0_R { + PER0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + pub fn per1(&self) -> PER1_R { + PER1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + pub fn per2(&self) -> PER2_R { + PER2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + pub fn per3(&self) -> PER3_R { + PER3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + pub fn per4(&self) -> PER4_R { + PER4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + pub fn per5(&self) -> PER5_R { + PER5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + pub fn per6(&self) -> PER6_R { + PER6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + pub fn per7(&self) -> PER7_R { + PER7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&self) -> CMP0_R { + CMP0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + pub fn per0(&mut self) -> PER0_W { + PER0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + pub fn per1(&mut self) -> PER1_W { + PER1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + pub fn per2(&mut self) -> PER2_W { + PER2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + pub fn per3(&mut self) -> PER3_W { + PER3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + pub fn per4(&mut self) -> PER4_W { + PER4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + pub fn per5(&mut self) -> PER5_W { + PER5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + pub fn per6(&mut self) -> PER6_W { + PER6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + pub fn per7(&mut self) -> PER7_W { + PER7_W { w: self } + } + #[doc = "Bit 8 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&mut self) -> CMP0_W { + CMP0_W { w: self } + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE0 Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/rtc/mode0/intflag.rs b/pac/atsamc20n/src/rtc/mode0/intflag.rs new file mode 100644 index 000000000000..f2dccdb04aa4 --- /dev/null +++ b/pac/atsamc20n/src/rtc/mode0/intflag.rs @@ -0,0 +1,536 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER0` reader - Periodic Interval 0"] +pub struct PER0_R(crate::FieldReader); +impl PER0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER0` writer - Periodic Interval 0"] +pub struct PER0_W<'a> { + w: &'a mut W, +} +impl<'a> PER0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PER1` reader - Periodic Interval 1"] +pub struct PER1_R(crate::FieldReader); +impl PER1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER1` writer - Periodic Interval 1"] +pub struct PER1_W<'a> { + w: &'a mut W, +} +impl<'a> PER1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PER2` reader - Periodic Interval 2"] +pub struct PER2_R(crate::FieldReader); +impl PER2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER2` writer - Periodic Interval 2"] +pub struct PER2_W<'a> { + w: &'a mut W, +} +impl<'a> PER2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PER3` reader - Periodic Interval 3"] +pub struct PER3_R(crate::FieldReader); +impl PER3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER3` writer - Periodic Interval 3"] +pub struct PER3_W<'a> { + w: &'a mut W, +} +impl<'a> PER3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PER4` reader - Periodic Interval 4"] +pub struct PER4_R(crate::FieldReader); +impl PER4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER4` writer - Periodic Interval 4"] +pub struct PER4_W<'a> { + w: &'a mut W, +} +impl<'a> PER4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PER5` reader - Periodic Interval 5"] +pub struct PER5_R(crate::FieldReader); +impl PER5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER5` writer - Periodic Interval 5"] +pub struct PER5_W<'a> { + w: &'a mut W, +} +impl<'a> PER5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PER6` reader - Periodic Interval 6"] +pub struct PER6_R(crate::FieldReader); +impl PER6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER6` writer - Periodic Interval 6"] +pub struct PER6_W<'a> { + w: &'a mut W, +} +impl<'a> PER6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PER7` reader - Periodic Interval 7"] +pub struct PER7_R(crate::FieldReader); +impl PER7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER7` writer - Periodic Interval 7"] +pub struct PER7_W<'a> { + w: &'a mut W, +} +impl<'a> PER7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CMP0` reader - Compare 0"] +pub struct CMP0_R(crate::FieldReader); +impl CMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP0` writer - Compare 0"] +pub struct CMP0_W<'a> { + w: &'a mut W, +} +impl<'a> CMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0"] + #[inline(always)] + pub fn per0(&self) -> PER0_R { + PER0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1"] + #[inline(always)] + pub fn per1(&self) -> PER1_R { + PER1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2"] + #[inline(always)] + pub fn per2(&self) -> PER2_R { + PER2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3"] + #[inline(always)] + pub fn per3(&self) -> PER3_R { + PER3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4"] + #[inline(always)] + pub fn per4(&self) -> PER4_R { + PER4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5"] + #[inline(always)] + pub fn per5(&self) -> PER5_R { + PER5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6"] + #[inline(always)] + pub fn per6(&self) -> PER6_R { + PER6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7"] + #[inline(always)] + pub fn per7(&self) -> PER7_R { + PER7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Compare 0"] + #[inline(always)] + pub fn cmp0(&self) -> CMP0_R { + CMP0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0"] + #[inline(always)] + pub fn per0(&mut self) -> PER0_W { + PER0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1"] + #[inline(always)] + pub fn per1(&mut self) -> PER1_W { + PER1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2"] + #[inline(always)] + pub fn per2(&mut self) -> PER2_W { + PER2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3"] + #[inline(always)] + pub fn per3(&mut self) -> PER3_W { + PER3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4"] + #[inline(always)] + pub fn per4(&mut self) -> PER4_W { + PER4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5"] + #[inline(always)] + pub fn per5(&mut self) -> PER5_W { + PER5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6"] + #[inline(always)] + pub fn per6(&mut self) -> PER6_W { + PER6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7"] + #[inline(always)] + pub fn per7(&mut self) -> PER7_W { + PER7_W { w: self } + } + #[doc = "Bit 8 - Compare 0"] + #[inline(always)] + pub fn cmp0(&mut self) -> CMP0_W { + CMP0_W { w: self } + } + #[doc = "Bit 15 - Overflow"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE0 Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/rtc/mode0/syncbusy.rs b/pac/atsamc20n/src/rtc/mode0/syncbusy.rs new file mode 100644 index 000000000000..518dea115a18 --- /dev/null +++ b/pac/atsamc20n/src/rtc/mode0/syncbusy.rs @@ -0,0 +1,153 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - Enable Bit Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FREQCORR` reader - FREQCORR Register Busy"] +pub struct FREQCORR_R(crate::FieldReader); +impl FREQCORR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FREQCORR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FREQCORR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` reader - COUNT Register Busy"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP0` reader - COMP 0 Register Busy"] +pub struct COMP0_R(crate::FieldReader); +impl COMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNTSYNC` reader - Count Read Synchronization Enable Bit Busy"] +pub struct COUNTSYNC_R(crate::FieldReader); +impl COUNTSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNTSYNC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNTSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable Bit Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - FREQCORR Register Busy"] + #[inline(always)] + pub fn freqcorr(&self) -> FREQCORR_R { + FREQCORR_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - COUNT Register Busy"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 5 - COMP 0 Register Busy"] + #[inline(always)] + pub fn comp0(&self) -> COMP0_R { + COMP0_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 15 - Count Read Synchronization Enable Bit Busy"] + #[inline(always)] + pub fn countsync(&self) -> COUNTSYNC_R { + COUNTSYNC_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +#[doc = "MODE0 Synchronization Busy Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/rtc/mode1.rs b/pac/atsamc20n/src/rtc/mode1.rs new file mode 100644 index 000000000000..9ea1bc17497c --- /dev/null +++ b/pac/atsamc20n/src/rtc/mode1.rs @@ -0,0 +1,44 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "MODE1 Control A"] +pub mod ctrla; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "MODE1 Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "MODE1 Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "MODE1 Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "MODE1 Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "MODE1 Synchronization Busy Status"] +pub mod syncbusy; +#[doc = "FREQCORR register accessor: an alias for `Reg`"] +pub type FREQCORR = crate::Reg; +#[doc = "Frequency Correction"] +pub mod freqcorr; +#[doc = "COUNT register accessor: an alias for `Reg`"] +pub type COUNT = crate::Reg; +#[doc = "MODE1 Counter Value"] +pub mod count; +#[doc = "PER register accessor: an alias for `Reg`"] +pub type PER = crate::Reg; +#[doc = "MODE1 Counter Period"] +pub mod per; +#[doc = "COMP register accessor: an alias for `Reg`"] +pub type COMP = crate::Reg; +#[doc = "MODE1 Compare n Value"] +pub mod comp; diff --git a/pac/atsamc20n/src/rtc/mode1/comp.rs b/pac/atsamc20n/src/rtc/mode1/comp.rs new file mode 100644 index 000000000000..6935385840f1 --- /dev/null +++ b/pac/atsamc20n/src/rtc/mode1/comp.rs @@ -0,0 +1,104 @@ +#[doc = "Register `COMP[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COMP[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COMP` reader - Compare Value"] +pub struct COMP_R(crate::FieldReader); +impl COMP_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + COMP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP` writer - Compare Value"] +pub struct COMP_W<'a> { + w: &'a mut W, +} +impl<'a> COMP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Compare Value"] + #[inline(always)] + pub fn comp(&self) -> COMP_R { + COMP_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Compare Value"] + #[inline(always)] + pub fn comp(&mut self) -> COMP_W { + COMP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Compare n Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [comp](index.html) module"] +pub struct COMP_SPEC; +impl crate::RegisterSpec for COMP_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [comp::R](R) reader structure"] +impl crate::Readable for COMP_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [comp::W](W) writer structure"] +impl crate::Writable for COMP_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COMP[%s] +to value 0"] +impl crate::Resettable for COMP_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/rtc/mode1/count.rs b/pac/atsamc20n/src/rtc/mode1/count.rs new file mode 100644 index 000000000000..2c41937b189c --- /dev/null +++ b/pac/atsamc20n/src/rtc/mode1/count.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Counter Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count](index.html) module"] +pub struct COUNT_SPEC; +impl crate::RegisterSpec for COUNT_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [count::R](R) reader structure"] +impl crate::Readable for COUNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count::W](W) writer structure"] +impl crate::Writable for COUNT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT to value 0"] +impl crate::Resettable for COUNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/rtc/mode1/ctrla.rs b/pac/atsamc20n/src/rtc/mode1/ctrla.rs new file mode 100644 index 000000000000..6e3e2042a9c4 --- /dev/null +++ b/pac/atsamc20n/src/rtc/mode1/ctrla.rs @@ -0,0 +1,522 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: Mode 0: 32-bit Counter"] + COUNT32 = 0, + #[doc = "1: Mode 1: 16-bit Counter"] + COUNT16 = 1, + #[doc = "2: Mode 2: Clock/Calendar"] + CLOCK = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::COUNT32), + 1 => Some(MODE_A::COUNT16), + 2 => Some(MODE_A::CLOCK), + _ => None, + } + } + #[doc = "Checks if the value of the field is `COUNT32`"] + #[inline(always)] + pub fn is_count32(&self) -> bool { + **self == MODE_A::COUNT32 + } + #[doc = "Checks if the value of the field is `COUNT16`"] + #[inline(always)] + pub fn is_count16(&self) -> bool { + **self == MODE_A::COUNT16 + } + #[doc = "Checks if the value of the field is `CLOCK`"] + #[inline(always)] + pub fn is_clock(&self) -> bool { + **self == MODE_A::CLOCK + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Mode 0: 32-bit Counter"] + #[inline(always)] + pub fn count32(self) -> &'a mut W { + self.variant(MODE_A::COUNT32) + } + #[doc = "Mode 1: 16-bit Counter"] + #[inline(always)] + pub fn count16(self) -> &'a mut W { + self.variant(MODE_A::COUNT16) + } + #[doc = "Mode 2: Clock/Calendar"] + #[inline(always)] + pub fn clock(self) -> &'a mut W { + self.variant(MODE_A::CLOCK) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u16 & 0x03) << 2); + self.w + } +} +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: CLK_RTC_CNT = GCLK_RTC/1"] + OFF = 0, + #[doc = "1: CLK_RTC_CNT = GCLK_RTC/1"] + DIV1 = 1, + #[doc = "2: CLK_RTC_CNT = GCLK_RTC/2"] + DIV2 = 2, + #[doc = "3: CLK_RTC_CNT = GCLK_RTC/4"] + DIV4 = 3, + #[doc = "4: CLK_RTC_CNT = GCLK_RTC/8"] + DIV8 = 4, + #[doc = "5: CLK_RTC_CNT = GCLK_RTC/16"] + DIV16 = 5, + #[doc = "6: CLK_RTC_CNT = GCLK_RTC/32"] + DIV32 = 6, + #[doc = "7: CLK_RTC_CNT = GCLK_RTC/64"] + DIV64 = 7, + #[doc = "8: CLK_RTC_CNT = GCLK_RTC/128"] + DIV128 = 8, + #[doc = "9: CLK_RTC_CNT = GCLK_RTC/256"] + DIV256 = 9, + #[doc = "10: CLK_RTC_CNT = GCLK_RTC/512"] + DIV512 = 10, + #[doc = "11: CLK_RTC_CNT = GCLK_RTC/1024"] + DIV1024 = 11, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCALER_A::OFF), + 1 => Some(PRESCALER_A::DIV1), + 2 => Some(PRESCALER_A::DIV2), + 3 => Some(PRESCALER_A::DIV4), + 4 => Some(PRESCALER_A::DIV8), + 5 => Some(PRESCALER_A::DIV16), + 6 => Some(PRESCALER_A::DIV32), + 7 => Some(PRESCALER_A::DIV64), + 8 => Some(PRESCALER_A::DIV128), + 9 => Some(PRESCALER_A::DIV256), + 10 => Some(PRESCALER_A::DIV512), + 11 => Some(PRESCALER_A::DIV1024), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == PRESCALER_A::OFF + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == PRESCALER_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == PRESCALER_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == PRESCALER_A::DIV128 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV512`"] + #[inline(always)] + pub fn is_div512(&self) -> bool { + **self == PRESCALER_A::DIV512 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PRESCALER_A::DIV1024 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(PRESCALER_A::OFF) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV32) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV128) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/512"] + #[inline(always)] + pub fn div512(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV512) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 8)) | ((value as u16 & 0x0f) << 8); + self.w + } +} +#[doc = "Field `COUNTSYNC` reader - Count Read Synchronization Enable"] +pub struct COUNTSYNC_R(crate::FieldReader); +impl COUNTSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNTSYNC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNTSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNTSYNC` writer - Count Read Synchronization Enable"] +pub struct COUNTSYNC_W<'a> { + w: &'a mut W, +} +impl<'a> COUNTSYNC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:3 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bits 8:11 - Prescaler"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 15 - Count Read Synchronization Enable"] + #[inline(always)] + pub fn countsync(&self) -> COUNTSYNC_R { + COUNTSYNC_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:3 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bits 8:11 - Prescaler"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Bit 15 - Count Read Synchronization Enable"] + #[inline(always)] + pub fn countsync(&mut self) -> COUNTSYNC_W { + COUNTSYNC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/rtc/mode1/dbgctrl.rs b/pac/atsamc20n/src/rtc/mode1/dbgctrl.rs new file mode 100644 index 000000000000..0383e70d0429 --- /dev/null +++ b/pac/atsamc20n/src/rtc/mode1/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Run During Debug"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Run During Debug"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/rtc/mode1/evctrl.rs b/pac/atsamc20n/src/rtc/mode1/evctrl.rs new file mode 100644 index 000000000000..e15624f828c7 --- /dev/null +++ b/pac/atsamc20n/src/rtc/mode1/evctrl.rs @@ -0,0 +1,583 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PEREO0` reader - Periodic Interval 0 Event Output Enable"] +pub struct PEREO0_R(crate::FieldReader); +impl PEREO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO0` writer - Periodic Interval 0 Event Output Enable"] +pub struct PEREO0_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `PEREO1` reader - Periodic Interval 1 Event Output Enable"] +pub struct PEREO1_R(crate::FieldReader); +impl PEREO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO1` writer - Periodic Interval 1 Event Output Enable"] +pub struct PEREO1_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PEREO2` reader - Periodic Interval 2 Event Output Enable"] +pub struct PEREO2_R(crate::FieldReader); +impl PEREO2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO2` writer - Periodic Interval 2 Event Output Enable"] +pub struct PEREO2_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PEREO3` reader - Periodic Interval 3 Event Output Enable"] +pub struct PEREO3_R(crate::FieldReader); +impl PEREO3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO3` writer - Periodic Interval 3 Event Output Enable"] +pub struct PEREO3_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PEREO4` reader - Periodic Interval 4 Event Output Enable"] +pub struct PEREO4_R(crate::FieldReader); +impl PEREO4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO4` writer - Periodic Interval 4 Event Output Enable"] +pub struct PEREO4_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PEREO5` reader - Periodic Interval 5 Event Output Enable"] +pub struct PEREO5_R(crate::FieldReader); +impl PEREO5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO5` writer - Periodic Interval 5 Event Output Enable"] +pub struct PEREO5_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PEREO6` reader - Periodic Interval 6 Event Output Enable"] +pub struct PEREO6_R(crate::FieldReader); +impl PEREO6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO6` writer - Periodic Interval 6 Event Output Enable"] +pub struct PEREO6_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PEREO7` reader - Periodic Interval 7 Event Output Enable"] +pub struct PEREO7_R(crate::FieldReader); +impl PEREO7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO7` writer - Periodic Interval 7 Event Output Enable"] +pub struct PEREO7_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CMPEO0` reader - Compare 0 Event Output Enable"] +pub struct CMPEO0_R(crate::FieldReader); +impl CMPEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMPEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMPEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMPEO0` writer - Compare 0 Event Output Enable"] +pub struct CMPEO0_W<'a> { + w: &'a mut W, +} +impl<'a> CMPEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `CMPEO1` reader - Compare 1 Event Output Enable"] +pub struct CMPEO1_R(crate::FieldReader); +impl CMPEO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMPEO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMPEO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMPEO1` writer - Compare 1 Event Output Enable"] +pub struct CMPEO1_W<'a> { + w: &'a mut W, +} +impl<'a> CMPEO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `OVFEO` reader - Overflow Event Output Enable"] +pub struct OVFEO_R(crate::FieldReader); +impl OVFEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVFEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVFEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVFEO` writer - Overflow Event Output Enable"] +pub struct OVFEO_W<'a> { + w: &'a mut W, +} +impl<'a> OVFEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Event Output Enable"] + #[inline(always)] + pub fn pereo0(&self) -> PEREO0_R { + PEREO0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Event Output Enable"] + #[inline(always)] + pub fn pereo1(&self) -> PEREO1_R { + PEREO1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Event Output Enable"] + #[inline(always)] + pub fn pereo2(&self) -> PEREO2_R { + PEREO2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Event Output Enable"] + #[inline(always)] + pub fn pereo3(&self) -> PEREO3_R { + PEREO3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Event Output Enable"] + #[inline(always)] + pub fn pereo4(&self) -> PEREO4_R { + PEREO4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Event Output Enable"] + #[inline(always)] + pub fn pereo5(&self) -> PEREO5_R { + PEREO5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Event Output Enable"] + #[inline(always)] + pub fn pereo6(&self) -> PEREO6_R { + PEREO6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Event Output Enable"] + #[inline(always)] + pub fn pereo7(&self) -> PEREO7_R { + PEREO7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Compare 0 Event Output Enable"] + #[inline(always)] + pub fn cmpeo0(&self) -> CMPEO0_R { + CMPEO0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Compare 1 Event Output Enable"] + #[inline(always)] + pub fn cmpeo1(&self) -> CMPEO1_R { + CMPEO1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&self) -> OVFEO_R { + OVFEO_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Event Output Enable"] + #[inline(always)] + pub fn pereo0(&mut self) -> PEREO0_W { + PEREO0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1 Event Output Enable"] + #[inline(always)] + pub fn pereo1(&mut self) -> PEREO1_W { + PEREO1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2 Event Output Enable"] + #[inline(always)] + pub fn pereo2(&mut self) -> PEREO2_W { + PEREO2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3 Event Output Enable"] + #[inline(always)] + pub fn pereo3(&mut self) -> PEREO3_W { + PEREO3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4 Event Output Enable"] + #[inline(always)] + pub fn pereo4(&mut self) -> PEREO4_W { + PEREO4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5 Event Output Enable"] + #[inline(always)] + pub fn pereo5(&mut self) -> PEREO5_W { + PEREO5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6 Event Output Enable"] + #[inline(always)] + pub fn pereo6(&mut self) -> PEREO6_W { + PEREO6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7 Event Output Enable"] + #[inline(always)] + pub fn pereo7(&mut self) -> PEREO7_W { + PEREO7_W { w: self } + } + #[doc = "Bit 8 - Compare 0 Event Output Enable"] + #[inline(always)] + pub fn cmpeo0(&mut self) -> CMPEO0_W { + CMPEO0_W { w: self } + } + #[doc = "Bit 9 - Compare 1 Event Output Enable"] + #[inline(always)] + pub fn cmpeo1(&mut self) -> CMPEO1_W { + CMPEO1_W { w: self } + } + #[doc = "Bit 15 - Overflow Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&mut self) -> OVFEO_W { + OVFEO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/rtc/mode1/freqcorr.rs b/pac/atsamc20n/src/rtc/mode1/freqcorr.rs new file mode 100644 index 000000000000..043ba6f88eb2 --- /dev/null +++ b/pac/atsamc20n/src/rtc/mode1/freqcorr.rs @@ -0,0 +1,150 @@ +#[doc = "Register `FREQCORR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FREQCORR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `VALUE` reader - Correction Value"] +pub struct VALUE_R(crate::FieldReader); +impl VALUE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + VALUE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VALUE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VALUE` writer - Correction Value"] +pub struct VALUE_W<'a> { + w: &'a mut W, +} +impl<'a> VALUE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x7f) | (value as u8 & 0x7f); + self.w + } +} +#[doc = "Field `SIGN` reader - Correction Sign"] +pub struct SIGN_R(crate::FieldReader); +impl SIGN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SIGN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SIGN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SIGN` writer - Correction Sign"] +pub struct SIGN_W<'a> { + w: &'a mut W, +} +impl<'a> SIGN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bits 0:6 - Correction Value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bit 7 - Correction Sign"] + #[inline(always)] + pub fn sign(&self) -> SIGN_R { + SIGN_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:6 - Correction Value"] + #[inline(always)] + pub fn value(&mut self) -> VALUE_W { + VALUE_W { w: self } + } + #[doc = "Bit 7 - Correction Sign"] + #[inline(always)] + pub fn sign(&mut self) -> SIGN_W { + SIGN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Frequency Correction\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [freqcorr](index.html) module"] +pub struct FREQCORR_SPEC; +impl crate::RegisterSpec for FREQCORR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [freqcorr::R](R) reader structure"] +impl crate::Readable for FREQCORR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [freqcorr::W](W) writer structure"] +impl crate::Writable for FREQCORR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets FREQCORR to value 0"] +impl crate::Resettable for FREQCORR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/rtc/mode1/intenclr.rs b/pac/atsamc20n/src/rtc/mode1/intenclr.rs new file mode 100644 index 000000000000..d3fc5b3df34b --- /dev/null +++ b/pac/atsamc20n/src/rtc/mode1/intenclr.rs @@ -0,0 +1,583 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER0` reader - Periodic Interval 0 Interrupt Enable"] +pub struct PER0_R(crate::FieldReader); +impl PER0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER0` writer - Periodic Interval 0 Interrupt Enable"] +pub struct PER0_W<'a> { + w: &'a mut W, +} +impl<'a> PER0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PER1` reader - Periodic Interval 1 Interrupt Enable"] +pub struct PER1_R(crate::FieldReader); +impl PER1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER1` writer - Periodic Interval 1 Interrupt Enable"] +pub struct PER1_W<'a> { + w: &'a mut W, +} +impl<'a> PER1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PER2` reader - Periodic Interval 2 Interrupt Enable"] +pub struct PER2_R(crate::FieldReader); +impl PER2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER2` writer - Periodic Interval 2 Interrupt Enable"] +pub struct PER2_W<'a> { + w: &'a mut W, +} +impl<'a> PER2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PER3` reader - Periodic Interval 3 Interrupt Enable"] +pub struct PER3_R(crate::FieldReader); +impl PER3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER3` writer - Periodic Interval 3 Interrupt Enable"] +pub struct PER3_W<'a> { + w: &'a mut W, +} +impl<'a> PER3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PER4` reader - Periodic Interval 4 Interrupt Enable"] +pub struct PER4_R(crate::FieldReader); +impl PER4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER4` writer - Periodic Interval 4 Interrupt Enable"] +pub struct PER4_W<'a> { + w: &'a mut W, +} +impl<'a> PER4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PER5` reader - Periodic Interval 5 Interrupt Enable"] +pub struct PER5_R(crate::FieldReader); +impl PER5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER5` writer - Periodic Interval 5 Interrupt Enable"] +pub struct PER5_W<'a> { + w: &'a mut W, +} +impl<'a> PER5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PER6` reader - Periodic Interval 6 Interrupt Enable"] +pub struct PER6_R(crate::FieldReader); +impl PER6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER6` writer - Periodic Interval 6 Interrupt Enable"] +pub struct PER6_W<'a> { + w: &'a mut W, +} +impl<'a> PER6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PER7` reader - Periodic Interval 7 Interrupt Enable"] +pub struct PER7_R(crate::FieldReader); +impl PER7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER7` writer - Periodic Interval 7 Interrupt Enable"] +pub struct PER7_W<'a> { + w: &'a mut W, +} +impl<'a> PER7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CMP0` reader - Compare 0 Interrupt Enable"] +pub struct CMP0_R(crate::FieldReader); +impl CMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP0` writer - Compare 0 Interrupt Enable"] +pub struct CMP0_W<'a> { + w: &'a mut W, +} +impl<'a> CMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `CMP1` reader - Compare 1 Interrupt Enable"] +pub struct CMP1_R(crate::FieldReader); +impl CMP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP1` writer - Compare 1 Interrupt Enable"] +pub struct CMP1_W<'a> { + w: &'a mut W, +} +impl<'a> CMP1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + pub fn per0(&self) -> PER0_R { + PER0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + pub fn per1(&self) -> PER1_R { + PER1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + pub fn per2(&self) -> PER2_R { + PER2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + pub fn per3(&self) -> PER3_R { + PER3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + pub fn per4(&self) -> PER4_R { + PER4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + pub fn per5(&self) -> PER5_R { + PER5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + pub fn per6(&self) -> PER6_R { + PER6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + pub fn per7(&self) -> PER7_R { + PER7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&self) -> CMP0_R { + CMP0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Compare 1 Interrupt Enable"] + #[inline(always)] + pub fn cmp1(&self) -> CMP1_R { + CMP1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + pub fn per0(&mut self) -> PER0_W { + PER0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + pub fn per1(&mut self) -> PER1_W { + PER1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + pub fn per2(&mut self) -> PER2_W { + PER2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + pub fn per3(&mut self) -> PER3_W { + PER3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + pub fn per4(&mut self) -> PER4_W { + PER4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + pub fn per5(&mut self) -> PER5_W { + PER5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + pub fn per6(&mut self) -> PER6_W { + PER6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + pub fn per7(&mut self) -> PER7_W { + PER7_W { w: self } + } + #[doc = "Bit 8 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&mut self) -> CMP0_W { + CMP0_W { w: self } + } + #[doc = "Bit 9 - Compare 1 Interrupt Enable"] + #[inline(always)] + pub fn cmp1(&mut self) -> CMP1_W { + CMP1_W { w: self } + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/rtc/mode1/intenset.rs b/pac/atsamc20n/src/rtc/mode1/intenset.rs new file mode 100644 index 000000000000..074cb377926a --- /dev/null +++ b/pac/atsamc20n/src/rtc/mode1/intenset.rs @@ -0,0 +1,583 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER0` reader - Periodic Interval 0 Interrupt Enable"] +pub struct PER0_R(crate::FieldReader); +impl PER0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER0` writer - Periodic Interval 0 Interrupt Enable"] +pub struct PER0_W<'a> { + w: &'a mut W, +} +impl<'a> PER0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PER1` reader - Periodic Interval 1 Interrupt Enable"] +pub struct PER1_R(crate::FieldReader); +impl PER1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER1` writer - Periodic Interval 1 Interrupt Enable"] +pub struct PER1_W<'a> { + w: &'a mut W, +} +impl<'a> PER1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PER2` reader - Periodic Interval 2 Interrupt Enable"] +pub struct PER2_R(crate::FieldReader); +impl PER2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER2` writer - Periodic Interval 2 Interrupt Enable"] +pub struct PER2_W<'a> { + w: &'a mut W, +} +impl<'a> PER2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PER3` reader - Periodic Interval 3 Interrupt Enable"] +pub struct PER3_R(crate::FieldReader); +impl PER3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER3` writer - Periodic Interval 3 Interrupt Enable"] +pub struct PER3_W<'a> { + w: &'a mut W, +} +impl<'a> PER3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PER4` reader - Periodic Interval 4 Interrupt Enable"] +pub struct PER4_R(crate::FieldReader); +impl PER4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER4` writer - Periodic Interval 4 Interrupt Enable"] +pub struct PER4_W<'a> { + w: &'a mut W, +} +impl<'a> PER4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PER5` reader - Periodic Interval 5 Interrupt Enable"] +pub struct PER5_R(crate::FieldReader); +impl PER5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER5` writer - Periodic Interval 5 Interrupt Enable"] +pub struct PER5_W<'a> { + w: &'a mut W, +} +impl<'a> PER5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PER6` reader - Periodic Interval 6 Interrupt Enable"] +pub struct PER6_R(crate::FieldReader); +impl PER6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER6` writer - Periodic Interval 6 Interrupt Enable"] +pub struct PER6_W<'a> { + w: &'a mut W, +} +impl<'a> PER6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PER7` reader - Periodic Interval 7 Interrupt Enable"] +pub struct PER7_R(crate::FieldReader); +impl PER7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER7` writer - Periodic Interval 7 Interrupt Enable"] +pub struct PER7_W<'a> { + w: &'a mut W, +} +impl<'a> PER7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CMP0` reader - Compare 0 Interrupt Enable"] +pub struct CMP0_R(crate::FieldReader); +impl CMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP0` writer - Compare 0 Interrupt Enable"] +pub struct CMP0_W<'a> { + w: &'a mut W, +} +impl<'a> CMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `CMP1` reader - Compare 1 Interrupt Enable"] +pub struct CMP1_R(crate::FieldReader); +impl CMP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP1` writer - Compare 1 Interrupt Enable"] +pub struct CMP1_W<'a> { + w: &'a mut W, +} +impl<'a> CMP1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + pub fn per0(&self) -> PER0_R { + PER0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + pub fn per1(&self) -> PER1_R { + PER1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + pub fn per2(&self) -> PER2_R { + PER2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + pub fn per3(&self) -> PER3_R { + PER3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + pub fn per4(&self) -> PER4_R { + PER4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + pub fn per5(&self) -> PER5_R { + PER5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + pub fn per6(&self) -> PER6_R { + PER6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + pub fn per7(&self) -> PER7_R { + PER7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&self) -> CMP0_R { + CMP0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Compare 1 Interrupt Enable"] + #[inline(always)] + pub fn cmp1(&self) -> CMP1_R { + CMP1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + pub fn per0(&mut self) -> PER0_W { + PER0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + pub fn per1(&mut self) -> PER1_W { + PER1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + pub fn per2(&mut self) -> PER2_W { + PER2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + pub fn per3(&mut self) -> PER3_W { + PER3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + pub fn per4(&mut self) -> PER4_W { + PER4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + pub fn per5(&mut self) -> PER5_W { + PER5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + pub fn per6(&mut self) -> PER6_W { + PER6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + pub fn per7(&mut self) -> PER7_W { + PER7_W { w: self } + } + #[doc = "Bit 8 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&mut self) -> CMP0_W { + CMP0_W { w: self } + } + #[doc = "Bit 9 - Compare 1 Interrupt Enable"] + #[inline(always)] + pub fn cmp1(&mut self) -> CMP1_W { + CMP1_W { w: self } + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/rtc/mode1/intflag.rs b/pac/atsamc20n/src/rtc/mode1/intflag.rs new file mode 100644 index 000000000000..25bce956f46b --- /dev/null +++ b/pac/atsamc20n/src/rtc/mode1/intflag.rs @@ -0,0 +1,583 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER0` reader - Periodic Interval 0"] +pub struct PER0_R(crate::FieldReader); +impl PER0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER0` writer - Periodic Interval 0"] +pub struct PER0_W<'a> { + w: &'a mut W, +} +impl<'a> PER0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PER1` reader - Periodic Interval 1"] +pub struct PER1_R(crate::FieldReader); +impl PER1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER1` writer - Periodic Interval 1"] +pub struct PER1_W<'a> { + w: &'a mut W, +} +impl<'a> PER1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PER2` reader - Periodic Interval 2"] +pub struct PER2_R(crate::FieldReader); +impl PER2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER2` writer - Periodic Interval 2"] +pub struct PER2_W<'a> { + w: &'a mut W, +} +impl<'a> PER2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PER3` reader - Periodic Interval 3"] +pub struct PER3_R(crate::FieldReader); +impl PER3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER3` writer - Periodic Interval 3"] +pub struct PER3_W<'a> { + w: &'a mut W, +} +impl<'a> PER3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PER4` reader - Periodic Interval 4"] +pub struct PER4_R(crate::FieldReader); +impl PER4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER4` writer - Periodic Interval 4"] +pub struct PER4_W<'a> { + w: &'a mut W, +} +impl<'a> PER4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PER5` reader - Periodic Interval 5"] +pub struct PER5_R(crate::FieldReader); +impl PER5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER5` writer - Periodic Interval 5"] +pub struct PER5_W<'a> { + w: &'a mut W, +} +impl<'a> PER5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PER6` reader - Periodic Interval 6"] +pub struct PER6_R(crate::FieldReader); +impl PER6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER6` writer - Periodic Interval 6"] +pub struct PER6_W<'a> { + w: &'a mut W, +} +impl<'a> PER6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PER7` reader - Periodic Interval 7"] +pub struct PER7_R(crate::FieldReader); +impl PER7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER7` writer - Periodic Interval 7"] +pub struct PER7_W<'a> { + w: &'a mut W, +} +impl<'a> PER7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CMP0` reader - Compare 0"] +pub struct CMP0_R(crate::FieldReader); +impl CMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP0` writer - Compare 0"] +pub struct CMP0_W<'a> { + w: &'a mut W, +} +impl<'a> CMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `CMP1` reader - Compare 1"] +pub struct CMP1_R(crate::FieldReader); +impl CMP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP1` writer - Compare 1"] +pub struct CMP1_W<'a> { + w: &'a mut W, +} +impl<'a> CMP1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0"] + #[inline(always)] + pub fn per0(&self) -> PER0_R { + PER0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1"] + #[inline(always)] + pub fn per1(&self) -> PER1_R { + PER1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2"] + #[inline(always)] + pub fn per2(&self) -> PER2_R { + PER2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3"] + #[inline(always)] + pub fn per3(&self) -> PER3_R { + PER3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4"] + #[inline(always)] + pub fn per4(&self) -> PER4_R { + PER4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5"] + #[inline(always)] + pub fn per5(&self) -> PER5_R { + PER5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6"] + #[inline(always)] + pub fn per6(&self) -> PER6_R { + PER6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7"] + #[inline(always)] + pub fn per7(&self) -> PER7_R { + PER7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Compare 0"] + #[inline(always)] + pub fn cmp0(&self) -> CMP0_R { + CMP0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Compare 1"] + #[inline(always)] + pub fn cmp1(&self) -> CMP1_R { + CMP1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0"] + #[inline(always)] + pub fn per0(&mut self) -> PER0_W { + PER0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1"] + #[inline(always)] + pub fn per1(&mut self) -> PER1_W { + PER1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2"] + #[inline(always)] + pub fn per2(&mut self) -> PER2_W { + PER2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3"] + #[inline(always)] + pub fn per3(&mut self) -> PER3_W { + PER3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4"] + #[inline(always)] + pub fn per4(&mut self) -> PER4_W { + PER4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5"] + #[inline(always)] + pub fn per5(&mut self) -> PER5_W { + PER5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6"] + #[inline(always)] + pub fn per6(&mut self) -> PER6_W { + PER6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7"] + #[inline(always)] + pub fn per7(&mut self) -> PER7_W { + PER7_W { w: self } + } + #[doc = "Bit 8 - Compare 0"] + #[inline(always)] + pub fn cmp0(&mut self) -> CMP0_W { + CMP0_W { w: self } + } + #[doc = "Bit 9 - Compare 1"] + #[inline(always)] + pub fn cmp1(&mut self) -> CMP1_W { + CMP1_W { w: self } + } + #[doc = "Bit 15 - Overflow"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/rtc/mode1/per.rs b/pac/atsamc20n/src/rtc/mode1/per.rs new file mode 100644 index 000000000000..c09b31fa30dd --- /dev/null +++ b/pac/atsamc20n/src/rtc/mode1/per.rs @@ -0,0 +1,103 @@ +#[doc = "Register `PER` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PER` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER` reader - Counter Period"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` writer - Counter Period"] +pub struct PER_W<'a> { + w: &'a mut W, +} +impl<'a> PER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Counter Period"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Counter Period"] + #[inline(always)] + pub fn per(&mut self) -> PER_W { + PER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Counter Period\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [per](index.html) module"] +pub struct PER_SPEC; +impl crate::RegisterSpec for PER_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [per::R](R) reader structure"] +impl crate::Readable for PER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [per::W](W) writer structure"] +impl crate::Writable for PER_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PER to value 0"] +impl crate::Resettable for PER_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/rtc/mode1/syncbusy.rs b/pac/atsamc20n/src/rtc/mode1/syncbusy.rs new file mode 100644 index 000000000000..b64c973bafff --- /dev/null +++ b/pac/atsamc20n/src/rtc/mode1/syncbusy.rs @@ -0,0 +1,193 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Bit Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - Enable Bit Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FREQCORR` reader - FREQCORR Register Busy"] +pub struct FREQCORR_R(crate::FieldReader); +impl FREQCORR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FREQCORR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FREQCORR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` reader - COUNT Register Busy"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` reader - PER Register Busy"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP0` reader - COMP 0 Register Busy"] +pub struct COMP0_R(crate::FieldReader); +impl COMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP1` reader - COMP 1 Register Busy"] +pub struct COMP1_R(crate::FieldReader); +impl COMP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNTSYNC` reader - Count Read Synchronization Enable Bit Busy"] +pub struct COUNTSYNC_R(crate::FieldReader); +impl COUNTSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNTSYNC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNTSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Bit Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable Bit Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - FREQCORR Register Busy"] + #[inline(always)] + pub fn freqcorr(&self) -> FREQCORR_R { + FREQCORR_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - COUNT Register Busy"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - PER Register Busy"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - COMP 0 Register Busy"] + #[inline(always)] + pub fn comp0(&self) -> COMP0_R { + COMP0_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - COMP 1 Register Busy"] + #[inline(always)] + pub fn comp1(&self) -> COMP1_R { + COMP1_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 15 - Count Read Synchronization Enable Bit Busy"] + #[inline(always)] + pub fn countsync(&self) -> COUNTSYNC_R { + COUNTSYNC_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +#[doc = "MODE1 Synchronization Busy Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/rtc/mode2.rs b/pac/atsamc20n/src/rtc/mode2.rs new file mode 100644 index 000000000000..b0bc13e81dbc --- /dev/null +++ b/pac/atsamc20n/src/rtc/mode2.rs @@ -0,0 +1,44 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "MODE2 Control A"] +pub mod ctrla; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "MODE2 Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "MODE2 Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "MODE2 Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "MODE2 Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "MODE2 Synchronization Busy Status"] +pub mod syncbusy; +#[doc = "FREQCORR register accessor: an alias for `Reg`"] +pub type FREQCORR = crate::Reg; +#[doc = "Frequency Correction"] +pub mod freqcorr; +#[doc = "CLOCK register accessor: an alias for `Reg`"] +pub type CLOCK = crate::Reg; +#[doc = "MODE2 Clock Value"] +pub mod clock; +#[doc = "ALARM register accessor: an alias for `Reg`"] +pub type ALARM = crate::Reg; +#[doc = "MODE2_ALARM Alarm n Value"] +pub mod alarm; +#[doc = "MASK register accessor: an alias for `Reg`"] +pub type MASK = crate::Reg; +#[doc = "MODE2_ALARM Alarm n Mask"] +pub mod mask; diff --git a/pac/atsamc20n/src/rtc/mode2/alarm.rs b/pac/atsamc20n/src/rtc/mode2/alarm.rs new file mode 100644 index 000000000000..1242477ea69f --- /dev/null +++ b/pac/atsamc20n/src/rtc/mode2/alarm.rs @@ -0,0 +1,337 @@ +#[doc = "Register `ALARM` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ALARM` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SECOND` reader - Second"] +pub struct SECOND_R(crate::FieldReader); +impl SECOND_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SECOND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SECOND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SECOND` writer - Second"] +pub struct SECOND_W<'a> { + w: &'a mut W, +} +impl<'a> SECOND_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +#[doc = "Field `MINUTE` reader - Minute"] +pub struct MINUTE_R(crate::FieldReader); +impl MINUTE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MINUTE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MINUTE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MINUTE` writer - Minute"] +pub struct MINUTE_W<'a> { + w: &'a mut W, +} +impl<'a> MINUTE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 6)) | ((value as u32 & 0x3f) << 6); + self.w + } +} +#[doc = "Hour\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum HOUR_A { + #[doc = "0: Morning hour"] + AM = 0, + #[doc = "16: Afternoon hour"] + PM = 16, +} +impl From for u8 { + #[inline(always)] + fn from(variant: HOUR_A) -> Self { + variant as _ + } +} +#[doc = "Field `HOUR` reader - Hour"] +pub struct HOUR_R(crate::FieldReader); +impl HOUR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + HOUR_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(HOUR_A::AM), + 16 => Some(HOUR_A::PM), + _ => None, + } + } + #[doc = "Checks if the value of the field is `AM`"] + #[inline(always)] + pub fn is_am(&self) -> bool { + **self == HOUR_A::AM + } + #[doc = "Checks if the value of the field is `PM`"] + #[inline(always)] + pub fn is_pm(&self) -> bool { + **self == HOUR_A::PM + } +} +impl core::ops::Deref for HOUR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HOUR` writer - Hour"] +pub struct HOUR_W<'a> { + w: &'a mut W, +} +impl<'a> HOUR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: HOUR_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Morning hour"] + #[inline(always)] + pub fn am(self) -> &'a mut W { + self.variant(HOUR_A::AM) + } + #[doc = "Afternoon hour"] + #[inline(always)] + pub fn pm(self) -> &'a mut W { + self.variant(HOUR_A::PM) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 12)) | ((value as u32 & 0x1f) << 12); + self.w + } +} +#[doc = "Field `DAY` reader - Day"] +pub struct DAY_R(crate::FieldReader); +impl DAY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DAY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DAY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DAY` writer - Day"] +pub struct DAY_W<'a> { + w: &'a mut W, +} +impl<'a> DAY_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 17)) | ((value as u32 & 0x1f) << 17); + self.w + } +} +#[doc = "Field `MONTH` reader - Month"] +pub struct MONTH_R(crate::FieldReader); +impl MONTH_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MONTH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MONTH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MONTH` writer - Month"] +pub struct MONTH_W<'a> { + w: &'a mut W, +} +impl<'a> MONTH_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 22)) | ((value as u32 & 0x0f) << 22); + self.w + } +} +#[doc = "Field `YEAR` reader - Year"] +pub struct YEAR_R(crate::FieldReader); +impl YEAR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + YEAR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for YEAR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `YEAR` writer - Year"] +pub struct YEAR_W<'a> { + w: &'a mut W, +} +impl<'a> YEAR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 26)) | ((value as u32 & 0x3f) << 26); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Second"] + #[inline(always)] + pub fn second(&self) -> SECOND_R { + SECOND_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:11 - Minute"] + #[inline(always)] + pub fn minute(&self) -> MINUTE_R { + MINUTE_R::new(((self.bits >> 6) & 0x3f) as u8) + } + #[doc = "Bits 12:16 - Hour"] + #[inline(always)] + pub fn hour(&self) -> HOUR_R { + HOUR_R::new(((self.bits >> 12) & 0x1f) as u8) + } + #[doc = "Bits 17:21 - Day"] + #[inline(always)] + pub fn day(&self) -> DAY_R { + DAY_R::new(((self.bits >> 17) & 0x1f) as u8) + } + #[doc = "Bits 22:25 - Month"] + #[inline(always)] + pub fn month(&self) -> MONTH_R { + MONTH_R::new(((self.bits >> 22) & 0x0f) as u8) + } + #[doc = "Bits 26:31 - Year"] + #[inline(always)] + pub fn year(&self) -> YEAR_R { + YEAR_R::new(((self.bits >> 26) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - Second"] + #[inline(always)] + pub fn second(&mut self) -> SECOND_W { + SECOND_W { w: self } + } + #[doc = "Bits 6:11 - Minute"] + #[inline(always)] + pub fn minute(&mut self) -> MINUTE_W { + MINUTE_W { w: self } + } + #[doc = "Bits 12:16 - Hour"] + #[inline(always)] + pub fn hour(&mut self) -> HOUR_W { + HOUR_W { w: self } + } + #[doc = "Bits 17:21 - Day"] + #[inline(always)] + pub fn day(&mut self) -> DAY_W { + DAY_W { w: self } + } + #[doc = "Bits 22:25 - Month"] + #[inline(always)] + pub fn month(&mut self) -> MONTH_W { + MONTH_W { w: self } + } + #[doc = "Bits 26:31 - Year"] + #[inline(always)] + pub fn year(&mut self) -> YEAR_W { + YEAR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2_ALARM Alarm n Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [alarm](index.html) module"] +pub struct ALARM_SPEC; +impl crate::RegisterSpec for ALARM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [alarm::R](R) reader structure"] +impl crate::Readable for ALARM_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [alarm::W](W) writer structure"] +impl crate::Writable for ALARM_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ALARM to value 0"] +impl crate::Resettable for ALARM_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/rtc/mode2/clock.rs b/pac/atsamc20n/src/rtc/mode2/clock.rs new file mode 100644 index 000000000000..3f364ff8e57b --- /dev/null +++ b/pac/atsamc20n/src/rtc/mode2/clock.rs @@ -0,0 +1,337 @@ +#[doc = "Register `CLOCK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CLOCK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SECOND` reader - Second"] +pub struct SECOND_R(crate::FieldReader); +impl SECOND_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SECOND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SECOND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SECOND` writer - Second"] +pub struct SECOND_W<'a> { + w: &'a mut W, +} +impl<'a> SECOND_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +#[doc = "Field `MINUTE` reader - Minute"] +pub struct MINUTE_R(crate::FieldReader); +impl MINUTE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MINUTE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MINUTE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MINUTE` writer - Minute"] +pub struct MINUTE_W<'a> { + w: &'a mut W, +} +impl<'a> MINUTE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 6)) | ((value as u32 & 0x3f) << 6); + self.w + } +} +#[doc = "Hour\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum HOUR_A { + #[doc = "0: AM when CLKREP in 12-hour"] + AM = 0, + #[doc = "16: PM when CLKREP in 12-hour"] + PM = 16, +} +impl From for u8 { + #[inline(always)] + fn from(variant: HOUR_A) -> Self { + variant as _ + } +} +#[doc = "Field `HOUR` reader - Hour"] +pub struct HOUR_R(crate::FieldReader); +impl HOUR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + HOUR_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(HOUR_A::AM), + 16 => Some(HOUR_A::PM), + _ => None, + } + } + #[doc = "Checks if the value of the field is `AM`"] + #[inline(always)] + pub fn is_am(&self) -> bool { + **self == HOUR_A::AM + } + #[doc = "Checks if the value of the field is `PM`"] + #[inline(always)] + pub fn is_pm(&self) -> bool { + **self == HOUR_A::PM + } +} +impl core::ops::Deref for HOUR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HOUR` writer - Hour"] +pub struct HOUR_W<'a> { + w: &'a mut W, +} +impl<'a> HOUR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: HOUR_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "AM when CLKREP in 12-hour"] + #[inline(always)] + pub fn am(self) -> &'a mut W { + self.variant(HOUR_A::AM) + } + #[doc = "PM when CLKREP in 12-hour"] + #[inline(always)] + pub fn pm(self) -> &'a mut W { + self.variant(HOUR_A::PM) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 12)) | ((value as u32 & 0x1f) << 12); + self.w + } +} +#[doc = "Field `DAY` reader - Day"] +pub struct DAY_R(crate::FieldReader); +impl DAY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DAY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DAY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DAY` writer - Day"] +pub struct DAY_W<'a> { + w: &'a mut W, +} +impl<'a> DAY_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 17)) | ((value as u32 & 0x1f) << 17); + self.w + } +} +#[doc = "Field `MONTH` reader - Month"] +pub struct MONTH_R(crate::FieldReader); +impl MONTH_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MONTH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MONTH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MONTH` writer - Month"] +pub struct MONTH_W<'a> { + w: &'a mut W, +} +impl<'a> MONTH_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 22)) | ((value as u32 & 0x0f) << 22); + self.w + } +} +#[doc = "Field `YEAR` reader - Year"] +pub struct YEAR_R(crate::FieldReader); +impl YEAR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + YEAR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for YEAR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `YEAR` writer - Year"] +pub struct YEAR_W<'a> { + w: &'a mut W, +} +impl<'a> YEAR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 26)) | ((value as u32 & 0x3f) << 26); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Second"] + #[inline(always)] + pub fn second(&self) -> SECOND_R { + SECOND_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:11 - Minute"] + #[inline(always)] + pub fn minute(&self) -> MINUTE_R { + MINUTE_R::new(((self.bits >> 6) & 0x3f) as u8) + } + #[doc = "Bits 12:16 - Hour"] + #[inline(always)] + pub fn hour(&self) -> HOUR_R { + HOUR_R::new(((self.bits >> 12) & 0x1f) as u8) + } + #[doc = "Bits 17:21 - Day"] + #[inline(always)] + pub fn day(&self) -> DAY_R { + DAY_R::new(((self.bits >> 17) & 0x1f) as u8) + } + #[doc = "Bits 22:25 - Month"] + #[inline(always)] + pub fn month(&self) -> MONTH_R { + MONTH_R::new(((self.bits >> 22) & 0x0f) as u8) + } + #[doc = "Bits 26:31 - Year"] + #[inline(always)] + pub fn year(&self) -> YEAR_R { + YEAR_R::new(((self.bits >> 26) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - Second"] + #[inline(always)] + pub fn second(&mut self) -> SECOND_W { + SECOND_W { w: self } + } + #[doc = "Bits 6:11 - Minute"] + #[inline(always)] + pub fn minute(&mut self) -> MINUTE_W { + MINUTE_W { w: self } + } + #[doc = "Bits 12:16 - Hour"] + #[inline(always)] + pub fn hour(&mut self) -> HOUR_W { + HOUR_W { w: self } + } + #[doc = "Bits 17:21 - Day"] + #[inline(always)] + pub fn day(&mut self) -> DAY_W { + DAY_W { w: self } + } + #[doc = "Bits 22:25 - Month"] + #[inline(always)] + pub fn month(&mut self) -> MONTH_W { + MONTH_W { w: self } + } + #[doc = "Bits 26:31 - Year"] + #[inline(always)] + pub fn year(&mut self) -> YEAR_W { + YEAR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2 Clock Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clock](index.html) module"] +pub struct CLOCK_SPEC; +impl crate::RegisterSpec for CLOCK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [clock::R](R) reader structure"] +impl crate::Readable for CLOCK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [clock::W](W) writer structure"] +impl crate::Writable for CLOCK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CLOCK to value 0"] +impl crate::Resettable for CLOCK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/rtc/mode2/ctrla.rs b/pac/atsamc20n/src/rtc/mode2/ctrla.rs new file mode 100644 index 000000000000..fc4bfda16bd8 --- /dev/null +++ b/pac/atsamc20n/src/rtc/mode2/ctrla.rs @@ -0,0 +1,616 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: Mode 0: 32-bit Counter"] + COUNT32 = 0, + #[doc = "1: Mode 1: 16-bit Counter"] + COUNT16 = 1, + #[doc = "2: Mode 2: Clock/Calendar"] + CLOCK = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::COUNT32), + 1 => Some(MODE_A::COUNT16), + 2 => Some(MODE_A::CLOCK), + _ => None, + } + } + #[doc = "Checks if the value of the field is `COUNT32`"] + #[inline(always)] + pub fn is_count32(&self) -> bool { + **self == MODE_A::COUNT32 + } + #[doc = "Checks if the value of the field is `COUNT16`"] + #[inline(always)] + pub fn is_count16(&self) -> bool { + **self == MODE_A::COUNT16 + } + #[doc = "Checks if the value of the field is `CLOCK`"] + #[inline(always)] + pub fn is_clock(&self) -> bool { + **self == MODE_A::CLOCK + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Mode 0: 32-bit Counter"] + #[inline(always)] + pub fn count32(self) -> &'a mut W { + self.variant(MODE_A::COUNT32) + } + #[doc = "Mode 1: 16-bit Counter"] + #[inline(always)] + pub fn count16(self) -> &'a mut W { + self.variant(MODE_A::COUNT16) + } + #[doc = "Mode 2: Clock/Calendar"] + #[inline(always)] + pub fn clock(self) -> &'a mut W { + self.variant(MODE_A::CLOCK) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u16 & 0x03) << 2); + self.w + } +} +#[doc = "Field `CLKREP` reader - Clock Representation"] +pub struct CLKREP_R(crate::FieldReader); +impl CLKREP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKREP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKREP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKREP` writer - Clock Representation"] +pub struct CLKREP_W<'a> { + w: &'a mut W, +} +impl<'a> CLKREP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `MATCHCLR` reader - Clear on Match"] +pub struct MATCHCLR_R(crate::FieldReader); +impl MATCHCLR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MATCHCLR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MATCHCLR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MATCHCLR` writer - Clear on Match"] +pub struct MATCHCLR_W<'a> { + w: &'a mut W, +} +impl<'a> MATCHCLR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: CLK_RTC_CNT = GCLK_RTC/1"] + OFF = 0, + #[doc = "1: CLK_RTC_CNT = GCLK_RTC/1"] + DIV1 = 1, + #[doc = "2: CLK_RTC_CNT = GCLK_RTC/2"] + DIV2 = 2, + #[doc = "3: CLK_RTC_CNT = GCLK_RTC/4"] + DIV4 = 3, + #[doc = "4: CLK_RTC_CNT = GCLK_RTC/8"] + DIV8 = 4, + #[doc = "5: CLK_RTC_CNT = GCLK_RTC/16"] + DIV16 = 5, + #[doc = "6: CLK_RTC_CNT = GCLK_RTC/32"] + DIV32 = 6, + #[doc = "7: CLK_RTC_CNT = GCLK_RTC/64"] + DIV64 = 7, + #[doc = "8: CLK_RTC_CNT = GCLK_RTC/128"] + DIV128 = 8, + #[doc = "9: CLK_RTC_CNT = GCLK_RTC/256"] + DIV256 = 9, + #[doc = "10: CLK_RTC_CNT = GCLK_RTC/512"] + DIV512 = 10, + #[doc = "11: CLK_RTC_CNT = GCLK_RTC/1024"] + DIV1024 = 11, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCALER_A::OFF), + 1 => Some(PRESCALER_A::DIV1), + 2 => Some(PRESCALER_A::DIV2), + 3 => Some(PRESCALER_A::DIV4), + 4 => Some(PRESCALER_A::DIV8), + 5 => Some(PRESCALER_A::DIV16), + 6 => Some(PRESCALER_A::DIV32), + 7 => Some(PRESCALER_A::DIV64), + 8 => Some(PRESCALER_A::DIV128), + 9 => Some(PRESCALER_A::DIV256), + 10 => Some(PRESCALER_A::DIV512), + 11 => Some(PRESCALER_A::DIV1024), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == PRESCALER_A::OFF + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == PRESCALER_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == PRESCALER_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == PRESCALER_A::DIV128 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV512`"] + #[inline(always)] + pub fn is_div512(&self) -> bool { + **self == PRESCALER_A::DIV512 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PRESCALER_A::DIV1024 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(PRESCALER_A::OFF) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV32) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV128) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/512"] + #[inline(always)] + pub fn div512(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV512) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 8)) | ((value as u16 & 0x0f) << 8); + self.w + } +} +#[doc = "Field `CLOCKSYNC` reader - Clock Read Synchronization Enable"] +pub struct CLOCKSYNC_R(crate::FieldReader); +impl CLOCKSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLOCKSYNC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLOCKSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLOCKSYNC` writer - Clock Read Synchronization Enable"] +pub struct CLOCKSYNC_W<'a> { + w: &'a mut W, +} +impl<'a> CLOCKSYNC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:3 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bit 6 - Clock Representation"] + #[inline(always)] + pub fn clkrep(&self) -> CLKREP_R { + CLKREP_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Clear on Match"] + #[inline(always)] + pub fn matchclr(&self) -> MATCHCLR_R { + MATCHCLR_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:11 - Prescaler"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 15 - Clock Read Synchronization Enable"] + #[inline(always)] + pub fn clocksync(&self) -> CLOCKSYNC_R { + CLOCKSYNC_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:3 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 6 - Clock Representation"] + #[inline(always)] + pub fn clkrep(&mut self) -> CLKREP_W { + CLKREP_W { w: self } + } + #[doc = "Bit 7 - Clear on Match"] + #[inline(always)] + pub fn matchclr(&mut self) -> MATCHCLR_W { + MATCHCLR_W { w: self } + } + #[doc = "Bits 8:11 - Prescaler"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Bit 15 - Clock Read Synchronization Enable"] + #[inline(always)] + pub fn clocksync(&mut self) -> CLOCKSYNC_W { + CLOCKSYNC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2 Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/rtc/mode2/dbgctrl.rs b/pac/atsamc20n/src/rtc/mode2/dbgctrl.rs new file mode 100644 index 000000000000..0383e70d0429 --- /dev/null +++ b/pac/atsamc20n/src/rtc/mode2/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Run During Debug"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Run During Debug"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/rtc/mode2/evctrl.rs b/pac/atsamc20n/src/rtc/mode2/evctrl.rs new file mode 100644 index 000000000000..17bc3da4a79e --- /dev/null +++ b/pac/atsamc20n/src/rtc/mode2/evctrl.rs @@ -0,0 +1,536 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PEREO0` reader - Periodic Interval 0 Event Output Enable"] +pub struct PEREO0_R(crate::FieldReader); +impl PEREO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO0` writer - Periodic Interval 0 Event Output Enable"] +pub struct PEREO0_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `PEREO1` reader - Periodic Interval 1 Event Output Enable"] +pub struct PEREO1_R(crate::FieldReader); +impl PEREO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO1` writer - Periodic Interval 1 Event Output Enable"] +pub struct PEREO1_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PEREO2` reader - Periodic Interval 2 Event Output Enable"] +pub struct PEREO2_R(crate::FieldReader); +impl PEREO2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO2` writer - Periodic Interval 2 Event Output Enable"] +pub struct PEREO2_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PEREO3` reader - Periodic Interval 3 Event Output Enable"] +pub struct PEREO3_R(crate::FieldReader); +impl PEREO3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO3` writer - Periodic Interval 3 Event Output Enable"] +pub struct PEREO3_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PEREO4` reader - Periodic Interval 4 Event Output Enable"] +pub struct PEREO4_R(crate::FieldReader); +impl PEREO4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO4` writer - Periodic Interval 4 Event Output Enable"] +pub struct PEREO4_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PEREO5` reader - Periodic Interval 5 Event Output Enable"] +pub struct PEREO5_R(crate::FieldReader); +impl PEREO5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO5` writer - Periodic Interval 5 Event Output Enable"] +pub struct PEREO5_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PEREO6` reader - Periodic Interval 6 Event Output Enable"] +pub struct PEREO6_R(crate::FieldReader); +impl PEREO6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO6` writer - Periodic Interval 6 Event Output Enable"] +pub struct PEREO6_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PEREO7` reader - Periodic Interval 7 Event Output Enable"] +pub struct PEREO7_R(crate::FieldReader); +impl PEREO7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO7` writer - Periodic Interval 7 Event Output Enable"] +pub struct PEREO7_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `ALARMEO0` reader - Alarm 0 Event Output Enable"] +pub struct ALARMEO0_R(crate::FieldReader); +impl ALARMEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALARMEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALARMEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALARMEO0` writer - Alarm 0 Event Output Enable"] +pub struct ALARMEO0_W<'a> { + w: &'a mut W, +} +impl<'a> ALARMEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `OVFEO` reader - Overflow Event Output Enable"] +pub struct OVFEO_R(crate::FieldReader); +impl OVFEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVFEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVFEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVFEO` writer - Overflow Event Output Enable"] +pub struct OVFEO_W<'a> { + w: &'a mut W, +} +impl<'a> OVFEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Event Output Enable"] + #[inline(always)] + pub fn pereo0(&self) -> PEREO0_R { + PEREO0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Event Output Enable"] + #[inline(always)] + pub fn pereo1(&self) -> PEREO1_R { + PEREO1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Event Output Enable"] + #[inline(always)] + pub fn pereo2(&self) -> PEREO2_R { + PEREO2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Event Output Enable"] + #[inline(always)] + pub fn pereo3(&self) -> PEREO3_R { + PEREO3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Event Output Enable"] + #[inline(always)] + pub fn pereo4(&self) -> PEREO4_R { + PEREO4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Event Output Enable"] + #[inline(always)] + pub fn pereo5(&self) -> PEREO5_R { + PEREO5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Event Output Enable"] + #[inline(always)] + pub fn pereo6(&self) -> PEREO6_R { + PEREO6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Event Output Enable"] + #[inline(always)] + pub fn pereo7(&self) -> PEREO7_R { + PEREO7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Alarm 0 Event Output Enable"] + #[inline(always)] + pub fn alarmeo0(&self) -> ALARMEO0_R { + ALARMEO0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&self) -> OVFEO_R { + OVFEO_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Event Output Enable"] + #[inline(always)] + pub fn pereo0(&mut self) -> PEREO0_W { + PEREO0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1 Event Output Enable"] + #[inline(always)] + pub fn pereo1(&mut self) -> PEREO1_W { + PEREO1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2 Event Output Enable"] + #[inline(always)] + pub fn pereo2(&mut self) -> PEREO2_W { + PEREO2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3 Event Output Enable"] + #[inline(always)] + pub fn pereo3(&mut self) -> PEREO3_W { + PEREO3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4 Event Output Enable"] + #[inline(always)] + pub fn pereo4(&mut self) -> PEREO4_W { + PEREO4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5 Event Output Enable"] + #[inline(always)] + pub fn pereo5(&mut self) -> PEREO5_W { + PEREO5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6 Event Output Enable"] + #[inline(always)] + pub fn pereo6(&mut self) -> PEREO6_W { + PEREO6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7 Event Output Enable"] + #[inline(always)] + pub fn pereo7(&mut self) -> PEREO7_W { + PEREO7_W { w: self } + } + #[doc = "Bit 8 - Alarm 0 Event Output Enable"] + #[inline(always)] + pub fn alarmeo0(&mut self) -> ALARMEO0_W { + ALARMEO0_W { w: self } + } + #[doc = "Bit 15 - Overflow Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&mut self) -> OVFEO_W { + OVFEO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2 Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/rtc/mode2/freqcorr.rs b/pac/atsamc20n/src/rtc/mode2/freqcorr.rs new file mode 100644 index 000000000000..043ba6f88eb2 --- /dev/null +++ b/pac/atsamc20n/src/rtc/mode2/freqcorr.rs @@ -0,0 +1,150 @@ +#[doc = "Register `FREQCORR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FREQCORR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `VALUE` reader - Correction Value"] +pub struct VALUE_R(crate::FieldReader); +impl VALUE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + VALUE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VALUE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VALUE` writer - Correction Value"] +pub struct VALUE_W<'a> { + w: &'a mut W, +} +impl<'a> VALUE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x7f) | (value as u8 & 0x7f); + self.w + } +} +#[doc = "Field `SIGN` reader - Correction Sign"] +pub struct SIGN_R(crate::FieldReader); +impl SIGN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SIGN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SIGN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SIGN` writer - Correction Sign"] +pub struct SIGN_W<'a> { + w: &'a mut W, +} +impl<'a> SIGN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bits 0:6 - Correction Value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bit 7 - Correction Sign"] + #[inline(always)] + pub fn sign(&self) -> SIGN_R { + SIGN_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:6 - Correction Value"] + #[inline(always)] + pub fn value(&mut self) -> VALUE_W { + VALUE_W { w: self } + } + #[doc = "Bit 7 - Correction Sign"] + #[inline(always)] + pub fn sign(&mut self) -> SIGN_W { + SIGN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Frequency Correction\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [freqcorr](index.html) module"] +pub struct FREQCORR_SPEC; +impl crate::RegisterSpec for FREQCORR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [freqcorr::R](R) reader structure"] +impl crate::Readable for FREQCORR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [freqcorr::W](W) writer structure"] +impl crate::Writable for FREQCORR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets FREQCORR to value 0"] +impl crate::Resettable for FREQCORR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/rtc/mode2/intenclr.rs b/pac/atsamc20n/src/rtc/mode2/intenclr.rs new file mode 100644 index 000000000000..84aa17f78a0e --- /dev/null +++ b/pac/atsamc20n/src/rtc/mode2/intenclr.rs @@ -0,0 +1,536 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER0` reader - Periodic Interval 0 Interrupt Enable"] +pub struct PER0_R(crate::FieldReader); +impl PER0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER0` writer - Periodic Interval 0 Interrupt Enable"] +pub struct PER0_W<'a> { + w: &'a mut W, +} +impl<'a> PER0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PER1` reader - Periodic Interval 1 Interrupt Enable"] +pub struct PER1_R(crate::FieldReader); +impl PER1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER1` writer - Periodic Interval 1 Interrupt Enable"] +pub struct PER1_W<'a> { + w: &'a mut W, +} +impl<'a> PER1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PER2` reader - Periodic Interval 2 Interrupt Enable"] +pub struct PER2_R(crate::FieldReader); +impl PER2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER2` writer - Periodic Interval 2 Interrupt Enable"] +pub struct PER2_W<'a> { + w: &'a mut W, +} +impl<'a> PER2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PER3` reader - Periodic Interval 3 Interrupt Enable"] +pub struct PER3_R(crate::FieldReader); +impl PER3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER3` writer - Periodic Interval 3 Interrupt Enable"] +pub struct PER3_W<'a> { + w: &'a mut W, +} +impl<'a> PER3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PER4` reader - Periodic Interval 4 Interrupt Enable"] +pub struct PER4_R(crate::FieldReader); +impl PER4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER4` writer - Periodic Interval 4 Interrupt Enable"] +pub struct PER4_W<'a> { + w: &'a mut W, +} +impl<'a> PER4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PER5` reader - Periodic Interval 5 Interrupt Enable"] +pub struct PER5_R(crate::FieldReader); +impl PER5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER5` writer - Periodic Interval 5 Interrupt Enable"] +pub struct PER5_W<'a> { + w: &'a mut W, +} +impl<'a> PER5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PER6` reader - Periodic Interval 6 Interrupt Enable"] +pub struct PER6_R(crate::FieldReader); +impl PER6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER6` writer - Periodic Interval 6 Interrupt Enable"] +pub struct PER6_W<'a> { + w: &'a mut W, +} +impl<'a> PER6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PER7` reader - Periodic Interval 7 Interrupt Enable"] +pub struct PER7_R(crate::FieldReader); +impl PER7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER7` writer - Periodic Interval 7 Interrupt Enable"] +pub struct PER7_W<'a> { + w: &'a mut W, +} +impl<'a> PER7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `ALARM0` reader - Alarm 0 Interrupt Enable"] +pub struct ALARM0_R(crate::FieldReader); +impl ALARM0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALARM0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALARM0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALARM0` writer - Alarm 0 Interrupt Enable"] +pub struct ALARM0_W<'a> { + w: &'a mut W, +} +impl<'a> ALARM0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + pub fn per0(&self) -> PER0_R { + PER0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + pub fn per1(&self) -> PER1_R { + PER1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + pub fn per2(&self) -> PER2_R { + PER2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + pub fn per3(&self) -> PER3_R { + PER3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + pub fn per4(&self) -> PER4_R { + PER4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + pub fn per5(&self) -> PER5_R { + PER5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + pub fn per6(&self) -> PER6_R { + PER6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + pub fn per7(&self) -> PER7_R { + PER7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Alarm 0 Interrupt Enable"] + #[inline(always)] + pub fn alarm0(&self) -> ALARM0_R { + ALARM0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + pub fn per0(&mut self) -> PER0_W { + PER0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + pub fn per1(&mut self) -> PER1_W { + PER1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + pub fn per2(&mut self) -> PER2_W { + PER2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + pub fn per3(&mut self) -> PER3_W { + PER3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + pub fn per4(&mut self) -> PER4_W { + PER4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + pub fn per5(&mut self) -> PER5_W { + PER5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + pub fn per6(&mut self) -> PER6_W { + PER6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + pub fn per7(&mut self) -> PER7_W { + PER7_W { w: self } + } + #[doc = "Bit 8 - Alarm 0 Interrupt Enable"] + #[inline(always)] + pub fn alarm0(&mut self) -> ALARM0_W { + ALARM0_W { w: self } + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2 Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/rtc/mode2/intenset.rs b/pac/atsamc20n/src/rtc/mode2/intenset.rs new file mode 100644 index 000000000000..a41687fa1ee5 --- /dev/null +++ b/pac/atsamc20n/src/rtc/mode2/intenset.rs @@ -0,0 +1,536 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER0` reader - Periodic Interval 0 Enable"] +pub struct PER0_R(crate::FieldReader); +impl PER0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER0` writer - Periodic Interval 0 Enable"] +pub struct PER0_W<'a> { + w: &'a mut W, +} +impl<'a> PER0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PER1` reader - Periodic Interval 1 Enable"] +pub struct PER1_R(crate::FieldReader); +impl PER1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER1` writer - Periodic Interval 1 Enable"] +pub struct PER1_W<'a> { + w: &'a mut W, +} +impl<'a> PER1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PER2` reader - Periodic Interval 2 Enable"] +pub struct PER2_R(crate::FieldReader); +impl PER2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER2` writer - Periodic Interval 2 Enable"] +pub struct PER2_W<'a> { + w: &'a mut W, +} +impl<'a> PER2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PER3` reader - Periodic Interval 3 Enable"] +pub struct PER3_R(crate::FieldReader); +impl PER3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER3` writer - Periodic Interval 3 Enable"] +pub struct PER3_W<'a> { + w: &'a mut W, +} +impl<'a> PER3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PER4` reader - Periodic Interval 4 Enable"] +pub struct PER4_R(crate::FieldReader); +impl PER4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER4` writer - Periodic Interval 4 Enable"] +pub struct PER4_W<'a> { + w: &'a mut W, +} +impl<'a> PER4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PER5` reader - Periodic Interval 5 Enable"] +pub struct PER5_R(crate::FieldReader); +impl PER5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER5` writer - Periodic Interval 5 Enable"] +pub struct PER5_W<'a> { + w: &'a mut W, +} +impl<'a> PER5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PER6` reader - Periodic Interval 6 Enable"] +pub struct PER6_R(crate::FieldReader); +impl PER6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER6` writer - Periodic Interval 6 Enable"] +pub struct PER6_W<'a> { + w: &'a mut W, +} +impl<'a> PER6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PER7` reader - Periodic Interval 7 Enable"] +pub struct PER7_R(crate::FieldReader); +impl PER7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER7` writer - Periodic Interval 7 Enable"] +pub struct PER7_W<'a> { + w: &'a mut W, +} +impl<'a> PER7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `ALARM0` reader - Alarm 0 Interrupt Enable"] +pub struct ALARM0_R(crate::FieldReader); +impl ALARM0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALARM0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALARM0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALARM0` writer - Alarm 0 Interrupt Enable"] +pub struct ALARM0_W<'a> { + w: &'a mut W, +} +impl<'a> ALARM0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Enable"] + #[inline(always)] + pub fn per0(&self) -> PER0_R { + PER0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Enable"] + #[inline(always)] + pub fn per1(&self) -> PER1_R { + PER1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Enable"] + #[inline(always)] + pub fn per2(&self) -> PER2_R { + PER2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Enable"] + #[inline(always)] + pub fn per3(&self) -> PER3_R { + PER3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Enable"] + #[inline(always)] + pub fn per4(&self) -> PER4_R { + PER4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Enable"] + #[inline(always)] + pub fn per5(&self) -> PER5_R { + PER5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Enable"] + #[inline(always)] + pub fn per6(&self) -> PER6_R { + PER6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Enable"] + #[inline(always)] + pub fn per7(&self) -> PER7_R { + PER7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Alarm 0 Interrupt Enable"] + #[inline(always)] + pub fn alarm0(&self) -> ALARM0_R { + ALARM0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Enable"] + #[inline(always)] + pub fn per0(&mut self) -> PER0_W { + PER0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1 Enable"] + #[inline(always)] + pub fn per1(&mut self) -> PER1_W { + PER1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2 Enable"] + #[inline(always)] + pub fn per2(&mut self) -> PER2_W { + PER2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3 Enable"] + #[inline(always)] + pub fn per3(&mut self) -> PER3_W { + PER3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4 Enable"] + #[inline(always)] + pub fn per4(&mut self) -> PER4_W { + PER4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5 Enable"] + #[inline(always)] + pub fn per5(&mut self) -> PER5_W { + PER5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6 Enable"] + #[inline(always)] + pub fn per6(&mut self) -> PER6_W { + PER6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7 Enable"] + #[inline(always)] + pub fn per7(&mut self) -> PER7_W { + PER7_W { w: self } + } + #[doc = "Bit 8 - Alarm 0 Interrupt Enable"] + #[inline(always)] + pub fn alarm0(&mut self) -> ALARM0_W { + ALARM0_W { w: self } + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2 Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/rtc/mode2/intflag.rs b/pac/atsamc20n/src/rtc/mode2/intflag.rs new file mode 100644 index 000000000000..8de0f3efd1d0 --- /dev/null +++ b/pac/atsamc20n/src/rtc/mode2/intflag.rs @@ -0,0 +1,536 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER0` reader - Periodic Interval 0"] +pub struct PER0_R(crate::FieldReader); +impl PER0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER0` writer - Periodic Interval 0"] +pub struct PER0_W<'a> { + w: &'a mut W, +} +impl<'a> PER0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PER1` reader - Periodic Interval 1"] +pub struct PER1_R(crate::FieldReader); +impl PER1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER1` writer - Periodic Interval 1"] +pub struct PER1_W<'a> { + w: &'a mut W, +} +impl<'a> PER1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PER2` reader - Periodic Interval 2"] +pub struct PER2_R(crate::FieldReader); +impl PER2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER2` writer - Periodic Interval 2"] +pub struct PER2_W<'a> { + w: &'a mut W, +} +impl<'a> PER2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PER3` reader - Periodic Interval 3"] +pub struct PER3_R(crate::FieldReader); +impl PER3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER3` writer - Periodic Interval 3"] +pub struct PER3_W<'a> { + w: &'a mut W, +} +impl<'a> PER3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PER4` reader - Periodic Interval 4"] +pub struct PER4_R(crate::FieldReader); +impl PER4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER4` writer - Periodic Interval 4"] +pub struct PER4_W<'a> { + w: &'a mut W, +} +impl<'a> PER4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PER5` reader - Periodic Interval 5"] +pub struct PER5_R(crate::FieldReader); +impl PER5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER5` writer - Periodic Interval 5"] +pub struct PER5_W<'a> { + w: &'a mut W, +} +impl<'a> PER5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PER6` reader - Periodic Interval 6"] +pub struct PER6_R(crate::FieldReader); +impl PER6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER6` writer - Periodic Interval 6"] +pub struct PER6_W<'a> { + w: &'a mut W, +} +impl<'a> PER6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PER7` reader - Periodic Interval 7"] +pub struct PER7_R(crate::FieldReader); +impl PER7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER7` writer - Periodic Interval 7"] +pub struct PER7_W<'a> { + w: &'a mut W, +} +impl<'a> PER7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `ALARM0` reader - Alarm 0"] +pub struct ALARM0_R(crate::FieldReader); +impl ALARM0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALARM0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALARM0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALARM0` writer - Alarm 0"] +pub struct ALARM0_W<'a> { + w: &'a mut W, +} +impl<'a> ALARM0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0"] + #[inline(always)] + pub fn per0(&self) -> PER0_R { + PER0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1"] + #[inline(always)] + pub fn per1(&self) -> PER1_R { + PER1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2"] + #[inline(always)] + pub fn per2(&self) -> PER2_R { + PER2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3"] + #[inline(always)] + pub fn per3(&self) -> PER3_R { + PER3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4"] + #[inline(always)] + pub fn per4(&self) -> PER4_R { + PER4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5"] + #[inline(always)] + pub fn per5(&self) -> PER5_R { + PER5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6"] + #[inline(always)] + pub fn per6(&self) -> PER6_R { + PER6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7"] + #[inline(always)] + pub fn per7(&self) -> PER7_R { + PER7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Alarm 0"] + #[inline(always)] + pub fn alarm0(&self) -> ALARM0_R { + ALARM0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0"] + #[inline(always)] + pub fn per0(&mut self) -> PER0_W { + PER0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1"] + #[inline(always)] + pub fn per1(&mut self) -> PER1_W { + PER1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2"] + #[inline(always)] + pub fn per2(&mut self) -> PER2_W { + PER2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3"] + #[inline(always)] + pub fn per3(&mut self) -> PER3_W { + PER3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4"] + #[inline(always)] + pub fn per4(&mut self) -> PER4_W { + PER4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5"] + #[inline(always)] + pub fn per5(&mut self) -> PER5_W { + PER5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6"] + #[inline(always)] + pub fn per6(&mut self) -> PER6_W { + PER6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7"] + #[inline(always)] + pub fn per7(&mut self) -> PER7_W { + PER7_W { w: self } + } + #[doc = "Bit 8 - Alarm 0"] + #[inline(always)] + pub fn alarm0(&mut self) -> ALARM0_W { + ALARM0_W { w: self } + } + #[doc = "Bit 15 - Overflow"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2 Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/rtc/mode2/mask.rs b/pac/atsamc20n/src/rtc/mode2/mask.rs new file mode 100644 index 000000000000..53e0bb491a62 --- /dev/null +++ b/pac/atsamc20n/src/rtc/mode2/mask.rs @@ -0,0 +1,217 @@ +#[doc = "Register `MASK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MASK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Alarm Mask Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SEL_A { + #[doc = "0: Alarm Disabled"] + OFF = 0, + #[doc = "1: Match seconds only"] + SS = 1, + #[doc = "2: Match seconds and minutes only"] + MMSS = 2, + #[doc = "3: Match seconds, minutes, and hours only"] + HHMMSS = 3, + #[doc = "4: Match seconds, minutes, hours, and days only"] + DDHHMMSS = 4, + #[doc = "5: Match seconds, minutes, hours, days, and months only"] + MMDDHHMMSS = 5, + #[doc = "6: Match seconds, minutes, hours, days, months, and years"] + YYMMDDHHMMSS = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `SEL` reader - Alarm Mask Selection"] +pub struct SEL_R(crate::FieldReader); +impl SEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEL_A::OFF), + 1 => Some(SEL_A::SS), + 2 => Some(SEL_A::MMSS), + 3 => Some(SEL_A::HHMMSS), + 4 => Some(SEL_A::DDHHMMSS), + 5 => Some(SEL_A::MMDDHHMMSS), + 6 => Some(SEL_A::YYMMDDHHMMSS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == SEL_A::OFF + } + #[doc = "Checks if the value of the field is `SS`"] + #[inline(always)] + pub fn is_ss(&self) -> bool { + **self == SEL_A::SS + } + #[doc = "Checks if the value of the field is `MMSS`"] + #[inline(always)] + pub fn is_mmss(&self) -> bool { + **self == SEL_A::MMSS + } + #[doc = "Checks if the value of the field is `HHMMSS`"] + #[inline(always)] + pub fn is_hhmmss(&self) -> bool { + **self == SEL_A::HHMMSS + } + #[doc = "Checks if the value of the field is `DDHHMMSS`"] + #[inline(always)] + pub fn is_ddhhmmss(&self) -> bool { + **self == SEL_A::DDHHMMSS + } + #[doc = "Checks if the value of the field is `MMDDHHMMSS`"] + #[inline(always)] + pub fn is_mmddhhmmss(&self) -> bool { + **self == SEL_A::MMDDHHMMSS + } + #[doc = "Checks if the value of the field is `YYMMDDHHMMSS`"] + #[inline(always)] + pub fn is_yymmddhhmmss(&self) -> bool { + **self == SEL_A::YYMMDDHHMMSS + } +} +impl core::ops::Deref for SEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEL` writer - Alarm Mask Selection"] +pub struct SEL_W<'a> { + w: &'a mut W, +} +impl<'a> SEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SEL_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Alarm Disabled"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(SEL_A::OFF) + } + #[doc = "Match seconds only"] + #[inline(always)] + pub fn ss(self) -> &'a mut W { + self.variant(SEL_A::SS) + } + #[doc = "Match seconds and minutes only"] + #[inline(always)] + pub fn mmss(self) -> &'a mut W { + self.variant(SEL_A::MMSS) + } + #[doc = "Match seconds, minutes, and hours only"] + #[inline(always)] + pub fn hhmmss(self) -> &'a mut W { + self.variant(SEL_A::HHMMSS) + } + #[doc = "Match seconds, minutes, hours, and days only"] + #[inline(always)] + pub fn ddhhmmss(self) -> &'a mut W { + self.variant(SEL_A::DDHHMMSS) + } + #[doc = "Match seconds, minutes, hours, days, and months only"] + #[inline(always)] + pub fn mmddhhmmss(self) -> &'a mut W { + self.variant(SEL_A::MMDDHHMMSS) + } + #[doc = "Match seconds, minutes, hours, days, months, and years"] + #[inline(always)] + pub fn yymmddhhmmss(self) -> &'a mut W { + self.variant(SEL_A::YYMMDDHHMMSS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Alarm Mask Selection"] + #[inline(always)] + pub fn sel(&self) -> SEL_R { + SEL_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Alarm Mask Selection"] + #[inline(always)] + pub fn sel(&mut self) -> SEL_W { + SEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2_ALARM Alarm n Mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mask](index.html) module"] +pub struct MASK_SPEC; +impl crate::RegisterSpec for MASK_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [mask::R](R) reader structure"] +impl crate::Readable for MASK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [mask::W](W) writer structure"] +impl crate::Writable for MASK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets MASK to value 0"] +impl crate::Resettable for MASK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/rtc/mode2/syncbusy.rs b/pac/atsamc20n/src/rtc/mode2/syncbusy.rs new file mode 100644 index 000000000000..b517ee5ae8b2 --- /dev/null +++ b/pac/atsamc20n/src/rtc/mode2/syncbusy.rs @@ -0,0 +1,173 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Bit Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - Enable Bit Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FREQCORR` reader - FREQCORR Register Busy"] +pub struct FREQCORR_R(crate::FieldReader); +impl FREQCORR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FREQCORR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FREQCORR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLOCK` reader - CLOCK Register Busy"] +pub struct CLOCK_R(crate::FieldReader); +impl CLOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALARM0` reader - ALARM 0 Register Busy"] +pub struct ALARM0_R(crate::FieldReader); +impl ALARM0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALARM0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALARM0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MASK0` reader - MASK 0 Register Busy"] +pub struct MASK0_R(crate::FieldReader); +impl MASK0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MASK0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MASK0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLOCKSYNC` reader - Clock Read Synchronization Enable Bit Busy"] +pub struct CLOCKSYNC_R(crate::FieldReader); +impl CLOCKSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLOCKSYNC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLOCKSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Bit Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable Bit Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - FREQCORR Register Busy"] + #[inline(always)] + pub fn freqcorr(&self) -> FREQCORR_R { + FREQCORR_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - CLOCK Register Busy"] + #[inline(always)] + pub fn clock(&self) -> CLOCK_R { + CLOCK_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 5 - ALARM 0 Register Busy"] + #[inline(always)] + pub fn alarm0(&self) -> ALARM0_R { + ALARM0_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 11 - MASK 0 Register Busy"] + #[inline(always)] + pub fn mask0(&self) -> MASK0_R { + MASK0_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 15 - Clock Read Synchronization Enable Bit Busy"] + #[inline(always)] + pub fn clocksync(&self) -> CLOCKSYNC_R { + CLOCKSYNC_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +#[doc = "MODE2 Synchronization Busy Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/sercom0.rs b/pac/atsamc20n/src/sercom0.rs new file mode 100644 index 000000000000..da7b62f750c6 --- /dev/null +++ b/pac/atsamc20n/src/sercom0.rs @@ -0,0 +1,327 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved_0_i2cm: [u8; 0x31], +} +impl RegisterBlock { + #[doc = "0x00..0x31 - USART INTERNAL CLOCK Mode"] + #[inline(always)] + pub fn usart_int(&self) -> &USART_INT { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const USART_INT) } + } + #[doc = "0x00..0x31 - USART EXTERNAL CLOCK Mode"] + #[inline(always)] + pub fn usart_ext(&self) -> &USART_EXT { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const USART_EXT) } + } + #[doc = "0x00..0x31 - SPI Master Mode"] + #[inline(always)] + pub fn spim(&self) -> &SPIM { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const SPIM) } + } + #[doc = "0x00..0x31 - SPI Slave Mode"] + #[inline(always)] + pub fn spis(&self) -> &SPIS { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const SPIS) } + } + #[doc = "0x00..0x29 - I2C Slave Mode"] + #[inline(always)] + pub fn i2cs(&self) -> &I2CS { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const I2CS) } + } + #[doc = "0x00..0x31 - I2C Master Mode"] + #[inline(always)] + pub fn i2cm(&self) -> &I2CM { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const I2CM) } + } +} +#[doc = r"Register block"] +#[repr(C)] +pub struct I2CM { + #[doc = "0x00 - I2CM Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - I2CM Control B"] + pub ctrlb: crate::Reg, + _reserved2: [u8; 0x04], + #[doc = "0x0c - I2CM Baud Rate"] + pub baud: crate::Reg, + _reserved3: [u8; 0x04], + #[doc = "0x14 - I2CM Interrupt Enable Clear"] + pub intenclr: crate::Reg, + _reserved4: [u8; 0x01], + #[doc = "0x16 - I2CM Interrupt Enable Set"] + pub intenset: crate::Reg, + _reserved5: [u8; 0x01], + #[doc = "0x18 - I2CM Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x1a - I2CM Status"] + pub status: crate::Reg, + #[doc = "0x1c - I2CM Synchronization Busy"] + pub syncbusy: crate::Reg, + _reserved8: [u8; 0x04], + #[doc = "0x24 - I2CM Address"] + pub addr: crate::Reg, + #[doc = "0x28 - I2CM Data"] + pub data: crate::Reg, + _reserved10: [u8; 0x07], + #[doc = "0x30 - I2CM Debug Control"] + pub dbgctrl: crate::Reg, +} +#[doc = r"Register block"] +#[doc = "I2C Master Mode"] +pub mod i2cm; +#[doc = r"Register block"] +#[repr(C)] +pub struct I2CS { + #[doc = "0x00 - I2CS Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - I2CS Control B"] + pub ctrlb: crate::Reg, + _reserved2: [u8; 0x0c], + #[doc = "0x14 - I2CS Interrupt Enable Clear"] + pub intenclr: crate::Reg, + _reserved3: [u8; 0x01], + #[doc = "0x16 - I2CS Interrupt Enable Set"] + pub intenset: crate::Reg, + _reserved4: [u8; 0x01], + #[doc = "0x18 - I2CS Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved5: [u8; 0x01], + #[doc = "0x1a - I2CS Status"] + pub status: crate::Reg, + #[doc = "0x1c - I2CS Synchronization Busy"] + pub syncbusy: crate::Reg, + _reserved7: [u8; 0x04], + #[doc = "0x24 - I2CS Address"] + pub addr: crate::Reg, + #[doc = "0x28 - I2CS Data"] + pub data: crate::Reg, +} +#[doc = r"Register block"] +#[doc = "I2C Slave Mode"] +pub mod i2cs; +#[doc = r"Register block"] +#[repr(C)] +pub struct SPIS { + #[doc = "0x00 - SPIS Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - SPIS Control B"] + pub ctrlb: crate::Reg, + _reserved2: [u8; 0x04], + #[doc = "0x0c - SPIS Baud Rate"] + pub baud: crate::Reg, + _reserved3: [u8; 0x07], + #[doc = "0x14 - SPIS Interrupt Enable Clear"] + pub intenclr: crate::Reg, + _reserved4: [u8; 0x01], + #[doc = "0x16 - SPIS Interrupt Enable Set"] + pub intenset: crate::Reg, + _reserved5: [u8; 0x01], + #[doc = "0x18 - SPIS Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x1a - SPIS Status"] + pub status: crate::Reg, + #[doc = "0x1c - SPIS Synchronization Busy"] + pub syncbusy: crate::Reg, + _reserved8: [u8; 0x04], + #[doc = "0x24 - SPIS Address"] + pub addr: crate::Reg, + #[doc = "0x28 - SPIS Data"] + pub data: crate::Reg, + _reserved10: [u8; 0x04], + #[doc = "0x30 - SPIS Debug Control"] + pub dbgctrl: crate::Reg, +} +#[doc = r"Register block"] +#[doc = "SPI Slave Mode"] +pub mod spis; +#[doc = r"Register block"] +#[repr(C)] +pub struct SPIM { + #[doc = "0x00 - SPIM Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - SPIM Control B"] + pub ctrlb: crate::Reg, + _reserved2: [u8; 0x04], + #[doc = "0x0c - SPIM Baud Rate"] + pub baud: crate::Reg, + _reserved3: [u8; 0x07], + #[doc = "0x14 - SPIM Interrupt Enable Clear"] + pub intenclr: crate::Reg, + _reserved4: [u8; 0x01], + #[doc = "0x16 - SPIM Interrupt Enable Set"] + pub intenset: crate::Reg, + _reserved5: [u8; 0x01], + #[doc = "0x18 - SPIM Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x1a - SPIM Status"] + pub status: crate::Reg, + #[doc = "0x1c - SPIM Synchronization Busy"] + pub syncbusy: crate::Reg, + _reserved8: [u8; 0x04], + #[doc = "0x24 - SPIM Address"] + pub addr: crate::Reg, + #[doc = "0x28 - SPIM Data"] + pub data: crate::Reg, + _reserved10: [u8; 0x04], + #[doc = "0x30 - SPIM Debug Control"] + pub dbgctrl: crate::Reg, +} +#[doc = r"Register block"] +#[doc = "SPI Master Mode"] +pub mod spim; +#[doc = r"Register block"] +#[repr(C)] +pub struct USART_EXT { + #[doc = "0x00 - USART_EXT Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - USART_EXT Control B"] + pub ctrlb: crate::Reg, + #[doc = "0x08 - USART_EXT Control C"] + pub ctrlc: crate::Reg, + _reserved_3_baud: [u8; 0x02], + #[doc = "0x0e - USART_EXT Receive Pulse Length"] + pub rxpl: crate::Reg, + _reserved5: [u8; 0x05], + #[doc = "0x14 - USART_EXT Interrupt Enable Clear"] + pub intenclr: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x16 - USART_EXT Interrupt Enable Set"] + pub intenset: crate::Reg, + _reserved7: [u8; 0x01], + #[doc = "0x18 - USART_EXT Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved8: [u8; 0x01], + #[doc = "0x1a - USART_EXT Status"] + pub status: crate::Reg, + #[doc = "0x1c - USART_EXT Synchronization Busy"] + pub syncbusy: crate::Reg, + _reserved10: [u8; 0x08], + #[doc = "0x28 - USART_EXT Data"] + pub data: crate::Reg, + _reserved11: [u8; 0x06], + #[doc = "0x30 - USART_EXT Debug Control"] + pub dbgctrl: crate::Reg, +} +impl USART_EXT { + #[doc = "0x0c - USART_EXT Baud Rate"] + #[inline(always)] + pub fn baud_usartfp_mode( + &self, + ) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } + #[doc = "0x0c - USART_EXT Baud Rate"] + #[inline(always)] + pub fn baud_fracfp_mode( + &self, + ) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } + #[doc = "0x0c - USART_EXT Baud Rate"] + #[inline(always)] + pub fn baud_frac_mode( + &self, + ) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } + #[doc = "0x0c - USART_EXT Baud Rate"] + #[inline(always)] + pub fn baud(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } +} +#[doc = r"Register block"] +#[doc = "USART EXTERNAL CLOCK Mode"] +pub mod usart_ext; +#[doc = r"Register block"] +#[repr(C)] +pub struct USART_INT { + #[doc = "0x00 - USART_INT Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - USART_INT Control B"] + pub ctrlb: crate::Reg, + #[doc = "0x08 - USART_INT Control C"] + pub ctrlc: crate::Reg, + _reserved_3_baud: [u8; 0x02], + #[doc = "0x0e - USART_INT Receive Pulse Length"] + pub rxpl: crate::Reg, + _reserved5: [u8; 0x05], + #[doc = "0x14 - USART_INT Interrupt Enable Clear"] + pub intenclr: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x16 - USART_INT Interrupt Enable Set"] + pub intenset: crate::Reg, + _reserved7: [u8; 0x01], + #[doc = "0x18 - USART_INT Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved8: [u8; 0x01], + #[doc = "0x1a - USART_INT Status"] + pub status: crate::Reg, + #[doc = "0x1c - USART_INT Synchronization Busy"] + pub syncbusy: crate::Reg, + _reserved10: [u8; 0x08], + #[doc = "0x28 - USART_INT Data"] + pub data: crate::Reg, + _reserved11: [u8; 0x06], + #[doc = "0x30 - USART_INT Debug Control"] + pub dbgctrl: crate::Reg, +} +impl USART_INT { + #[doc = "0x0c - USART_INT Baud Rate"] + #[inline(always)] + pub fn baud_usartfp_mode( + &self, + ) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } + #[doc = "0x0c - USART_INT Baud Rate"] + #[inline(always)] + pub fn baud_fracfp_mode( + &self, + ) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } + #[doc = "0x0c - USART_INT Baud Rate"] + #[inline(always)] + pub fn baud_frac_mode( + &self, + ) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } + #[doc = "0x0c - USART_INT Baud Rate"] + #[inline(always)] + pub fn baud(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } +} +#[doc = r"Register block"] +#[doc = "USART INTERNAL CLOCK Mode"] +pub mod usart_int; diff --git a/pac/atsamc20n/src/sercom0/i2cm.rs b/pac/atsamc20n/src/sercom0/i2cm.rs new file mode 100644 index 000000000000..8aa217da8b18 --- /dev/null +++ b/pac/atsamc20n/src/sercom0/i2cm.rs @@ -0,0 +1,44 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "I2CM Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "I2CM Control B"] +pub mod ctrlb; +#[doc = "BAUD register accessor: an alias for `Reg`"] +pub type BAUD = crate::Reg; +#[doc = "I2CM Baud Rate"] +pub mod baud; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "I2CM Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "I2CM Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "I2CM Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "I2CM Status"] +pub mod status; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "I2CM Synchronization Busy"] +pub mod syncbusy; +#[doc = "ADDR register accessor: an alias for `Reg`"] +pub type ADDR = crate::Reg; +#[doc = "I2CM Address"] +pub mod addr; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "I2CM Data"] +pub mod data; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "I2CM Debug Control"] +pub mod dbgctrl; diff --git a/pac/atsamc20n/src/sercom0/i2cm/addr.rs b/pac/atsamc20n/src/sercom0/i2cm/addr.rs new file mode 100644 index 000000000000..4efd19e824c6 --- /dev/null +++ b/pac/atsamc20n/src/sercom0/i2cm/addr.rs @@ -0,0 +1,281 @@ +#[doc = "Register `ADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ADDR` reader - Address Value"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - Address Value"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07ff) | (value as u32 & 0x07ff); + self.w + } +} +#[doc = "Field `LENEN` reader - Length Enable"] +pub struct LENEN_R(crate::FieldReader); +impl LENEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LENEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LENEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LENEN` writer - Length Enable"] +pub struct LENEN_W<'a> { + w: &'a mut W, +} +impl<'a> LENEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `HS` reader - High Speed Mode"] +pub struct HS_R(crate::FieldReader); +impl HS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HS` writer - High Speed Mode"] +pub struct HS_W<'a> { + w: &'a mut W, +} +impl<'a> HS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `TENBITEN` reader - Ten Bit Addressing Enable"] +pub struct TENBITEN_R(crate::FieldReader); +impl TENBITEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TENBITEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TENBITEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TENBITEN` writer - Ten Bit Addressing Enable"] +pub struct TENBITEN_W<'a> { + w: &'a mut W, +} +impl<'a> TENBITEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `LEN` reader - Length"] +pub struct LEN_R(crate::FieldReader); +impl LEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LEN` writer - Length"] +pub struct LEN_W<'a> { + w: &'a mut W, +} +impl<'a> LEN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:10 - Address Value"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new((self.bits & 0x07ff) as u16) + } + #[doc = "Bit 13 - Length Enable"] + #[inline(always)] + pub fn lenen(&self) -> LENEN_R { + LENEN_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - High Speed Mode"] + #[inline(always)] + pub fn hs(&self) -> HS_R { + HS_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Ten Bit Addressing Enable"] + #[inline(always)] + pub fn tenbiten(&self) -> TENBITEN_R { + TENBITEN_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:23 - Length"] + #[inline(always)] + pub fn len(&self) -> LEN_R { + LEN_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:10 - Address Value"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Bit 13 - Length Enable"] + #[inline(always)] + pub fn lenen(&mut self) -> LENEN_W { + LENEN_W { w: self } + } + #[doc = "Bit 14 - High Speed Mode"] + #[inline(always)] + pub fn hs(&mut self) -> HS_W { + HS_W { w: self } + } + #[doc = "Bit 15 - Ten Bit Addressing Enable"] + #[inline(always)] + pub fn tenbiten(&mut self) -> TENBITEN_W { + TENBITEN_W { w: self } + } + #[doc = "Bits 16:23 - Length"] + #[inline(always)] + pub fn len(&mut self) -> LEN_W { + LEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [addr](index.html) module"] +pub struct ADDR_SPEC; +impl crate::RegisterSpec for ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [addr::R](R) reader structure"] +impl crate::Readable for ADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [addr::W](W) writer structure"] +impl crate::Writable for ADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ADDR to value 0"] +impl crate::Resettable for ADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/sercom0/i2cm/baud.rs b/pac/atsamc20n/src/sercom0/i2cm/baud.rs new file mode 100644 index 000000000000..7c98d3b5b0de --- /dev/null +++ b/pac/atsamc20n/src/sercom0/i2cm/baud.rs @@ -0,0 +1,214 @@ +#[doc = "Register `BAUD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +#[doc = "Field `BAUDLOW` reader - Baud Rate Value Low"] +pub struct BAUDLOW_R(crate::FieldReader); +impl BAUDLOW_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BAUDLOW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUDLOW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUDLOW` writer - Baud Rate Value Low"] +pub struct BAUDLOW_W<'a> { + w: &'a mut W, +} +impl<'a> BAUDLOW_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +#[doc = "Field `HSBAUD` reader - High Speed Baud Rate Value"] +pub struct HSBAUD_R(crate::FieldReader); +impl HSBAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + HSBAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HSBAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HSBAUD` writer - High Speed Baud Rate Value"] +pub struct HSBAUD_W<'a> { + w: &'a mut W, +} +impl<'a> HSBAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +#[doc = "Field `HSBAUDLOW` reader - High Speed Baud Rate Value Low"] +pub struct HSBAUDLOW_R(crate::FieldReader); +impl HSBAUDLOW_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + HSBAUDLOW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HSBAUDLOW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HSBAUDLOW` writer - High Speed Baud Rate Value Low"] +pub struct HSBAUDLOW_W<'a> { + w: &'a mut W, +} +impl<'a> HSBAUDLOW_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 24)) | ((value as u32 & 0xff) << 24); + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Baud Rate Value Low"] + #[inline(always)] + pub fn baudlow(&self) -> BAUDLOW_R { + BAUDLOW_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - High Speed Baud Rate Value"] + #[inline(always)] + pub fn hsbaud(&self) -> HSBAUD_R { + HSBAUD_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - High Speed Baud Rate Value Low"] + #[inline(always)] + pub fn hsbaudlow(&self) -> HSBAUDLOW_R { + HSBAUDLOW_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Bits 8:15 - Baud Rate Value Low"] + #[inline(always)] + pub fn baudlow(&mut self) -> BAUDLOW_W { + BAUDLOW_W { w: self } + } + #[doc = "Bits 16:23 - High Speed Baud Rate Value"] + #[inline(always)] + pub fn hsbaud(&mut self) -> HSBAUD_W { + HSBAUD_W { w: self } + } + #[doc = "Bits 24:31 - High Speed Baud Rate Value Low"] + #[inline(always)] + pub fn hsbaudlow(&mut self) -> HSBAUDLOW_W { + HSBAUDLOW_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud](index.html) module"] +pub struct BAUD_SPEC; +impl crate::RegisterSpec for BAUD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [baud::R](R) reader structure"] +impl crate::Readable for BAUD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud::W](W) writer structure"] +impl crate::Writable for BAUD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD to value 0"] +impl crate::Resettable for BAUD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/sercom0/i2cm/ctrla.rs b/pac/atsamc20n/src/sercom0/i2cm/ctrla.rs new file mode 100644 index 000000000000..34fa668b7967 --- /dev/null +++ b/pac/atsamc20n/src/sercom0/i2cm/ctrla.rs @@ -0,0 +1,903 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: USART with external clock"] + USART_EXT_CLK = 0, + #[doc = "1: USART with internal clock"] + USART_INT_CLK = 1, + #[doc = "2: SPI in slave operation"] + SPI_SLAVE = 2, + #[doc = "3: SPI in master operation"] + SPI_MASTER = 3, + #[doc = "4: I2C slave operation"] + I2C_SLAVE = 4, + #[doc = "5: I2C master operation"] + I2C_MASTER = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::USART_EXT_CLK), + 1 => Some(MODE_A::USART_INT_CLK), + 2 => Some(MODE_A::SPI_SLAVE), + 3 => Some(MODE_A::SPI_MASTER), + 4 => Some(MODE_A::I2C_SLAVE), + 5 => Some(MODE_A::I2C_MASTER), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_EXT_CLK`"] + #[inline(always)] + pub fn is_usart_ext_clk(&self) -> bool { + **self == MODE_A::USART_EXT_CLK + } + #[doc = "Checks if the value of the field is `USART_INT_CLK`"] + #[inline(always)] + pub fn is_usart_int_clk(&self) -> bool { + **self == MODE_A::USART_INT_CLK + } + #[doc = "Checks if the value of the field is `SPI_SLAVE`"] + #[inline(always)] + pub fn is_spi_slave(&self) -> bool { + **self == MODE_A::SPI_SLAVE + } + #[doc = "Checks if the value of the field is `SPI_MASTER`"] + #[inline(always)] + pub fn is_spi_master(&self) -> bool { + **self == MODE_A::SPI_MASTER + } + #[doc = "Checks if the value of the field is `I2C_SLAVE`"] + #[inline(always)] + pub fn is_i2c_slave(&self) -> bool { + **self == MODE_A::I2C_SLAVE + } + #[doc = "Checks if the value of the field is `I2C_MASTER`"] + #[inline(always)] + pub fn is_i2c_master(&self) -> bool { + **self == MODE_A::I2C_MASTER + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART with external clock"] + #[inline(always)] + pub fn usart_ext_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_EXT_CLK) + } + #[doc = "USART with internal clock"] + #[inline(always)] + pub fn usart_int_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_INT_CLK) + } + #[doc = "SPI in slave operation"] + #[inline(always)] + pub fn spi_slave(self) -> &'a mut W { + self.variant(MODE_A::SPI_SLAVE) + } + #[doc = "SPI in master operation"] + #[inline(always)] + pub fn spi_master(self) -> &'a mut W { + self.variant(MODE_A::SPI_MASTER) + } + #[doc = "I2C slave operation"] + #[inline(always)] + pub fn i2c_slave(self) -> &'a mut W { + self.variant(MODE_A::I2C_SLAVE) + } + #[doc = "I2C master operation"] + #[inline(always)] + pub fn i2c_master(self) -> &'a mut W { + self.variant(MODE_A::I2C_MASTER) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 2)) | ((value as u32 & 0x07) << 2); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `PINOUT` reader - Pin Usage"] +pub struct PINOUT_R(crate::FieldReader); +impl PINOUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PINOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PINOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PINOUT` writer - Pin Usage"] +pub struct PINOUT_W<'a> { + w: &'a mut W, +} +impl<'a> PINOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "SDA Hold Time\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SDAHOLD_A { + #[doc = "0: Disabled"] + DISABLE = 0, + #[doc = "1: 50-100ns hold time"] + _75NS = 1, + #[doc = "2: 300-600ns hold time"] + _450NS = 2, + #[doc = "3: 400-800ns hold time"] + _600NS = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SDAHOLD_A) -> Self { + variant as _ + } +} +#[doc = "Field `SDAHOLD` reader - SDA Hold Time"] +pub struct SDAHOLD_R(crate::FieldReader); +impl SDAHOLD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SDAHOLD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SDAHOLD_A { + match self.bits { + 0 => SDAHOLD_A::DISABLE, + 1 => SDAHOLD_A::_75NS, + 2 => SDAHOLD_A::_450NS, + 3 => SDAHOLD_A::_600NS, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == SDAHOLD_A::DISABLE + } + #[doc = "Checks if the value of the field is `_75NS`"] + #[inline(always)] + pub fn is_75ns(&self) -> bool { + **self == SDAHOLD_A::_75NS + } + #[doc = "Checks if the value of the field is `_450NS`"] + #[inline(always)] + pub fn is_450ns(&self) -> bool { + **self == SDAHOLD_A::_450NS + } + #[doc = "Checks if the value of the field is `_600NS`"] + #[inline(always)] + pub fn is_600ns(&self) -> bool { + **self == SDAHOLD_A::_600NS + } +} +impl core::ops::Deref for SDAHOLD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SDAHOLD` writer - SDA Hold Time"] +pub struct SDAHOLD_W<'a> { + w: &'a mut W, +} +impl<'a> SDAHOLD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SDAHOLD_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(SDAHOLD_A::DISABLE) + } + #[doc = "50-100ns hold time"] + #[inline(always)] + pub fn _75ns(self) -> &'a mut W { + self.variant(SDAHOLD_A::_75NS) + } + #[doc = "300-600ns hold time"] + #[inline(always)] + pub fn _450ns(self) -> &'a mut W { + self.variant(SDAHOLD_A::_450NS) + } + #[doc = "400-800ns hold time"] + #[inline(always)] + pub fn _600ns(self) -> &'a mut W { + self.variant(SDAHOLD_A::_600NS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 20)) | ((value as u32 & 0x03) << 20); + self.w + } +} +#[doc = "Field `MEXTTOEN` reader - Master SCL Low Extend Timeout"] +pub struct MEXTTOEN_R(crate::FieldReader); +impl MEXTTOEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MEXTTOEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MEXTTOEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MEXTTOEN` writer - Master SCL Low Extend Timeout"] +pub struct MEXTTOEN_W<'a> { + w: &'a mut W, +} +impl<'a> MEXTTOEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `SEXTTOEN` reader - Slave SCL Low Extend Timeout"] +pub struct SEXTTOEN_R(crate::FieldReader); +impl SEXTTOEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SEXTTOEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEXTTOEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEXTTOEN` writer - Slave SCL Low Extend Timeout"] +pub struct SEXTTOEN_W<'a> { + w: &'a mut W, +} +impl<'a> SEXTTOEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Transfer Speed\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SPEED_A { + #[doc = "0: Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz"] + STANDARD_AND_FAST_MODE = 0, + #[doc = "1: Fast-mode Plus Upto 1MHz"] + FASTPLUS_MODE = 1, + #[doc = "2: High-speed mode Upto 3.4MHz"] + HIGH_SPEED_MODE = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SPEED_A) -> Self { + variant as _ + } +} +#[doc = "Field `SPEED` reader - Transfer Speed"] +pub struct SPEED_R(crate::FieldReader); +impl SPEED_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SPEED_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SPEED_A::STANDARD_AND_FAST_MODE), + 1 => Some(SPEED_A::FASTPLUS_MODE), + 2 => Some(SPEED_A::HIGH_SPEED_MODE), + _ => None, + } + } + #[doc = "Checks if the value of the field is `STANDARD_AND_FAST_MODE`"] + #[inline(always)] + pub fn is_standard_and_fast_mode(&self) -> bool { + **self == SPEED_A::STANDARD_AND_FAST_MODE + } + #[doc = "Checks if the value of the field is `FASTPLUS_MODE`"] + #[inline(always)] + pub fn is_fastplus_mode(&self) -> bool { + **self == SPEED_A::FASTPLUS_MODE + } + #[doc = "Checks if the value of the field is `HIGH_SPEED_MODE`"] + #[inline(always)] + pub fn is_high_speed_mode(&self) -> bool { + **self == SPEED_A::HIGH_SPEED_MODE + } +} +impl core::ops::Deref for SPEED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SPEED` writer - Transfer Speed"] +pub struct SPEED_W<'a> { + w: &'a mut W, +} +impl<'a> SPEED_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SPEED_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz"] + #[inline(always)] + pub fn standard_and_fast_mode(self) -> &'a mut W { + self.variant(SPEED_A::STANDARD_AND_FAST_MODE) + } + #[doc = "Fast-mode Plus Upto 1MHz"] + #[inline(always)] + pub fn fastplus_mode(self) -> &'a mut W { + self.variant(SPEED_A::FASTPLUS_MODE) + } + #[doc = "High-speed mode Upto 3.4MHz"] + #[inline(always)] + pub fn high_speed_mode(self) -> &'a mut W { + self.variant(SPEED_A::HIGH_SPEED_MODE) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 24)) | ((value as u32 & 0x03) << 24); + self.w + } +} +#[doc = "Field `SCLSM` reader - SCL Clock Stretch Mode"] +pub struct SCLSM_R(crate::FieldReader); +impl SCLSM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SCLSM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SCLSM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SCLSM` writer - SCL Clock Stretch Mode"] +pub struct SCLSM_W<'a> { + w: &'a mut W, +} +impl<'a> SCLSM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +#[doc = "Inactive Time-Out\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum INACTOUT_A { + #[doc = "0: Disabled"] + DISABLE = 0, + #[doc = "1: 5-6 SCL Time-Out(50-60us)"] + _55US = 1, + #[doc = "2: 10-11 SCL Time-Out(100-110us)"] + _105US = 2, + #[doc = "3: 20-21 SCL Time-Out(200-210us)"] + _205US = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: INACTOUT_A) -> Self { + variant as _ + } +} +#[doc = "Field `INACTOUT` reader - Inactive Time-Out"] +pub struct INACTOUT_R(crate::FieldReader); +impl INACTOUT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + INACTOUT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INACTOUT_A { + match self.bits { + 0 => INACTOUT_A::DISABLE, + 1 => INACTOUT_A::_55US, + 2 => INACTOUT_A::_105US, + 3 => INACTOUT_A::_205US, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == INACTOUT_A::DISABLE + } + #[doc = "Checks if the value of the field is `_55US`"] + #[inline(always)] + pub fn is_55us(&self) -> bool { + **self == INACTOUT_A::_55US + } + #[doc = "Checks if the value of the field is `_105US`"] + #[inline(always)] + pub fn is_105us(&self) -> bool { + **self == INACTOUT_A::_105US + } + #[doc = "Checks if the value of the field is `_205US`"] + #[inline(always)] + pub fn is_205us(&self) -> bool { + **self == INACTOUT_A::_205US + } +} +impl core::ops::Deref for INACTOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INACTOUT` writer - Inactive Time-Out"] +pub struct INACTOUT_W<'a> { + w: &'a mut W, +} +impl<'a> INACTOUT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: INACTOUT_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(INACTOUT_A::DISABLE) + } + #[doc = "5-6 SCL Time-Out(50-60us)"] + #[inline(always)] + pub fn _55us(self) -> &'a mut W { + self.variant(INACTOUT_A::_55US) + } + #[doc = "10-11 SCL Time-Out(100-110us)"] + #[inline(always)] + pub fn _105us(self) -> &'a mut W { + self.variant(INACTOUT_A::_105US) + } + #[doc = "20-21 SCL Time-Out(200-210us)"] + #[inline(always)] + pub fn _205us(self) -> &'a mut W { + self.variant(INACTOUT_A::_205US) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 28)) | ((value as u32 & 0x03) << 28); + self.w + } +} +#[doc = "Field `LOWTOUTEN` reader - SCL Low Timeout Enable"] +pub struct LOWTOUTEN_R(crate::FieldReader); +impl LOWTOUTEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LOWTOUTEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOWTOUTEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LOWTOUTEN` writer - SCL Low Timeout Enable"] +pub struct LOWTOUTEN_W<'a> { + w: &'a mut W, +} +impl<'a> LOWTOUTEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x07) as u8) + } + #[doc = "Bit 7 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 16 - Pin Usage"] + #[inline(always)] + pub fn pinout(&self) -> PINOUT_R { + PINOUT_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bits 20:21 - SDA Hold Time"] + #[inline(always)] + pub fn sdahold(&self) -> SDAHOLD_R { + SDAHOLD_R::new(((self.bits >> 20) & 0x03) as u8) + } + #[doc = "Bit 22 - Master SCL Low Extend Timeout"] + #[inline(always)] + pub fn mexttoen(&self) -> MEXTTOEN_R { + MEXTTOEN_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttoen(&self) -> SEXTTOEN_R { + SEXTTOEN_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bits 24:25 - Transfer Speed"] + #[inline(always)] + pub fn speed(&self) -> SPEED_R { + SPEED_R::new(((self.bits >> 24) & 0x03) as u8) + } + #[doc = "Bit 27 - SCL Clock Stretch Mode"] + #[inline(always)] + pub fn sclsm(&self) -> SCLSM_R { + SCLSM_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bits 28:29 - Inactive Time-Out"] + #[inline(always)] + pub fn inactout(&self) -> INACTOUT_R { + INACTOUT_R::new(((self.bits >> 28) & 0x03) as u8) + } + #[doc = "Bit 30 - SCL Low Timeout Enable"] + #[inline(always)] + pub fn lowtouten(&self) -> LOWTOUTEN_R { + LOWTOUTEN_R::new(((self.bits >> 30) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 7 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 16 - Pin Usage"] + #[inline(always)] + pub fn pinout(&mut self) -> PINOUT_W { + PINOUT_W { w: self } + } + #[doc = "Bits 20:21 - SDA Hold Time"] + #[inline(always)] + pub fn sdahold(&mut self) -> SDAHOLD_W { + SDAHOLD_W { w: self } + } + #[doc = "Bit 22 - Master SCL Low Extend Timeout"] + #[inline(always)] + pub fn mexttoen(&mut self) -> MEXTTOEN_W { + MEXTTOEN_W { w: self } + } + #[doc = "Bit 23 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttoen(&mut self) -> SEXTTOEN_W { + SEXTTOEN_W { w: self } + } + #[doc = "Bits 24:25 - Transfer Speed"] + #[inline(always)] + pub fn speed(&mut self) -> SPEED_W { + SPEED_W { w: self } + } + #[doc = "Bit 27 - SCL Clock Stretch Mode"] + #[inline(always)] + pub fn sclsm(&mut self) -> SCLSM_W { + SCLSM_W { w: self } + } + #[doc = "Bits 28:29 - Inactive Time-Out"] + #[inline(always)] + pub fn inactout(&mut self) -> INACTOUT_W { + INACTOUT_W { w: self } + } + #[doc = "Bit 30 - SCL Low Timeout Enable"] + #[inline(always)] + pub fn lowtouten(&mut self) -> LOWTOUTEN_W { + LOWTOUTEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/sercom0/i2cm/ctrlb.rs b/pac/atsamc20n/src/sercom0/i2cm/ctrlb.rs new file mode 100644 index 000000000000..ce534463c0da --- /dev/null +++ b/pac/atsamc20n/src/sercom0/i2cm/ctrlb.rs @@ -0,0 +1,244 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SMEN` reader - Smart Mode Enable"] +pub struct SMEN_R(crate::FieldReader); +impl SMEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SMEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SMEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SMEN` writer - Smart Mode Enable"] +pub struct SMEN_W<'a> { + w: &'a mut W, +} +impl<'a> SMEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `QCEN` reader - Quick Command Enable"] +pub struct QCEN_R(crate::FieldReader); +impl QCEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + QCEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for QCEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `QCEN` writer - Quick Command Enable"] +pub struct QCEN_W<'a> { + w: &'a mut W, +} +impl<'a> QCEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Field `ACKACT` reader - Acknowledge Action"] +pub struct ACKACT_R(crate::FieldReader); +impl ACKACT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ACKACT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ACKACT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ACKACT` writer - Acknowledge Action"] +pub struct ACKACT_W<'a> { + w: &'a mut W, +} +impl<'a> ACKACT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +impl R { + #[doc = "Bit 8 - Smart Mode Enable"] + #[inline(always)] + pub fn smen(&self) -> SMEN_R { + SMEN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Quick Command Enable"] + #[inline(always)] + pub fn qcen(&self) -> QCEN_R { + QCEN_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bits 16:17 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bit 18 - Acknowledge Action"] + #[inline(always)] + pub fn ackact(&self) -> ACKACT_R { + ACKACT_R::new(((self.bits >> 18) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 8 - Smart Mode Enable"] + #[inline(always)] + pub fn smen(&mut self) -> SMEN_W { + SMEN_W { w: self } + } + #[doc = "Bit 9 - Quick Command Enable"] + #[inline(always)] + pub fn qcen(&mut self) -> QCEN_W { + QCEN_W { w: self } + } + #[doc = "Bits 16:17 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Bit 18 - Acknowledge Action"] + #[inline(always)] + pub fn ackact(&mut self) -> ACKACT_W { + ACKACT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/sercom0/i2cm/data.rs b/pac/atsamc20n/src/sercom0/i2cm/data.rs new file mode 100644 index 000000000000..cf204596d3a6 --- /dev/null +++ b/pac/atsamc20n/src/sercom0/i2cm/data.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data Value"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data Value"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Data Value"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Value"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/sercom0/i2cm/dbgctrl.rs b/pac/atsamc20n/src/sercom0/i2cm/dbgctrl.rs new file mode 100644 index 000000000000..0fffdb4c6e39 --- /dev/null +++ b/pac/atsamc20n/src/sercom0/i2cm/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGSTOP` reader - Debug Mode"] +pub struct DBGSTOP_R(crate::FieldReader); +impl DBGSTOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGSTOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGSTOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGSTOP` writer - Debug Mode"] +pub struct DBGSTOP_W<'a> { + w: &'a mut W, +} +impl<'a> DBGSTOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&self) -> DBGSTOP_R { + DBGSTOP_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&mut self) -> DBGSTOP_W { + DBGSTOP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/sercom0/i2cm/intenclr.rs b/pac/atsamc20n/src/sercom0/i2cm/intenclr.rs new file mode 100644 index 000000000000..17f067a55656 --- /dev/null +++ b/pac/atsamc20n/src/sercom0/i2cm/intenclr.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MB` reader - Master On Bus Interrupt Disable"] +pub struct MB_R(crate::FieldReader); +impl MB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MB` writer - Master On Bus Interrupt Disable"] +pub struct MB_W<'a> { + w: &'a mut W, +} +impl<'a> MB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SB` reader - Slave On Bus Interrupt Disable"] +pub struct SB_R(crate::FieldReader); +impl SB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SB` writer - Slave On Bus Interrupt Disable"] +pub struct SB_W<'a> { + w: &'a mut W, +} +impl<'a> SB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Disable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Disable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Master On Bus Interrupt Disable"] + #[inline(always)] + pub fn mb(&self) -> MB_R { + MB_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Slave On Bus Interrupt Disable"] + #[inline(always)] + pub fn sb(&self) -> SB_R { + SB_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Master On Bus Interrupt Disable"] + #[inline(always)] + pub fn mb(&mut self) -> MB_W { + MB_W { w: self } + } + #[doc = "Bit 1 - Slave On Bus Interrupt Disable"] + #[inline(always)] + pub fn sb(&mut self) -> SB_W { + SB_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/sercom0/i2cm/intenset.rs b/pac/atsamc20n/src/sercom0/i2cm/intenset.rs new file mode 100644 index 000000000000..a0cbf96b3aa0 --- /dev/null +++ b/pac/atsamc20n/src/sercom0/i2cm/intenset.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MB` reader - Master On Bus Interrupt Enable"] +pub struct MB_R(crate::FieldReader); +impl MB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MB` writer - Master On Bus Interrupt Enable"] +pub struct MB_W<'a> { + w: &'a mut W, +} +impl<'a> MB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SB` reader - Slave On Bus Interrupt Enable"] +pub struct SB_R(crate::FieldReader); +impl SB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SB` writer - Slave On Bus Interrupt Enable"] +pub struct SB_W<'a> { + w: &'a mut W, +} +impl<'a> SB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Master On Bus Interrupt Enable"] + #[inline(always)] + pub fn mb(&self) -> MB_R { + MB_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Slave On Bus Interrupt Enable"] + #[inline(always)] + pub fn sb(&self) -> SB_R { + SB_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Master On Bus Interrupt Enable"] + #[inline(always)] + pub fn mb(&mut self) -> MB_W { + MB_W { w: self } + } + #[doc = "Bit 1 - Slave On Bus Interrupt Enable"] + #[inline(always)] + pub fn sb(&mut self) -> SB_W { + SB_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/sercom0/i2cm/intflag.rs b/pac/atsamc20n/src/sercom0/i2cm/intflag.rs new file mode 100644 index 000000000000..0fb0d2b9060c --- /dev/null +++ b/pac/atsamc20n/src/sercom0/i2cm/intflag.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MB` reader - Master On Bus Interrupt"] +pub struct MB_R(crate::FieldReader); +impl MB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MB` writer - Master On Bus Interrupt"] +pub struct MB_W<'a> { + w: &'a mut W, +} +impl<'a> MB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SB` reader - Slave On Bus Interrupt"] +pub struct SB_R(crate::FieldReader); +impl SB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SB` writer - Slave On Bus Interrupt"] +pub struct SB_W<'a> { + w: &'a mut W, +} +impl<'a> SB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Master On Bus Interrupt"] + #[inline(always)] + pub fn mb(&self) -> MB_R { + MB_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Slave On Bus Interrupt"] + #[inline(always)] + pub fn sb(&self) -> SB_R { + SB_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Master On Bus Interrupt"] + #[inline(always)] + pub fn mb(&mut self) -> MB_W { + MB_W { w: self } + } + #[doc = "Bit 1 - Slave On Bus Interrupt"] + #[inline(always)] + pub fn sb(&mut self) -> SB_W { + SB_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/sercom0/i2cm/status.rs b/pac/atsamc20n/src/sercom0/i2cm/status.rs new file mode 100644 index 000000000000..95af23673ec4 --- /dev/null +++ b/pac/atsamc20n/src/sercom0/i2cm/status.rs @@ -0,0 +1,479 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BUSERR` reader - Bus Error"] +pub struct BUSERR_R(crate::FieldReader); +impl BUSERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSERR` writer - Bus Error"] +pub struct BUSERR_W<'a> { + w: &'a mut W, +} +impl<'a> BUSERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `ARBLOST` reader - Arbitration Lost"] +pub struct ARBLOST_R(crate::FieldReader); +impl ARBLOST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ARBLOST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ARBLOST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ARBLOST` writer - Arbitration Lost"] +pub struct ARBLOST_W<'a> { + w: &'a mut W, +} +impl<'a> ARBLOST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXNACK` reader - Received Not Acknowledge"] +pub struct RXNACK_R(crate::FieldReader); +impl RXNACK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXNACK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXNACK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXNACK` writer - Received Not Acknowledge"] +pub struct RXNACK_W<'a> { + w: &'a mut W, +} +impl<'a> RXNACK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `BUSSTATE` reader - Bus State"] +pub struct BUSSTATE_R(crate::FieldReader); +impl BUSSTATE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BUSSTATE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSSTATE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSSTATE` writer - Bus State"] +pub struct BUSSTATE_W<'a> { + w: &'a mut W, +} +impl<'a> BUSSTATE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u16 & 0x03) << 4); + self.w + } +} +#[doc = "Field `LOWTOUT` reader - SCL Low Timeout"] +pub struct LOWTOUT_R(crate::FieldReader); +impl LOWTOUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LOWTOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOWTOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LOWTOUT` writer - SCL Low Timeout"] +pub struct LOWTOUT_W<'a> { + w: &'a mut W, +} +impl<'a> LOWTOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `CLKHOLD` reader - Clock Hold"] +pub struct CLKHOLD_R(crate::FieldReader); +impl CLKHOLD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKHOLD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKHOLD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKHOLD` writer - Clock Hold"] +pub struct CLKHOLD_W<'a> { + w: &'a mut W, +} +impl<'a> CLKHOLD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `MEXTTOUT` reader - Master SCL Low Extend Timeout"] +pub struct MEXTTOUT_R(crate::FieldReader); +impl MEXTTOUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MEXTTOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MEXTTOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MEXTTOUT` writer - Master SCL Low Extend Timeout"] +pub struct MEXTTOUT_W<'a> { + w: &'a mut W, +} +impl<'a> MEXTTOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `SEXTTOUT` reader - Slave SCL Low Extend Timeout"] +pub struct SEXTTOUT_R(crate::FieldReader); +impl SEXTTOUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SEXTTOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEXTTOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEXTTOUT` writer - Slave SCL Low Extend Timeout"] +pub struct SEXTTOUT_W<'a> { + w: &'a mut W, +} +impl<'a> SEXTTOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `LENERR` reader - Length Error"] +pub struct LENERR_R(crate::FieldReader); +impl LENERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LENERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LENERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LENERR` writer - Length Error"] +pub struct LENERR_W<'a> { + w: &'a mut W, +} +impl<'a> LENERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u16 & 0x01) << 10); + self.w + } +} +impl R { + #[doc = "Bit 0 - Bus Error"] + #[inline(always)] + pub fn buserr(&self) -> BUSERR_R { + BUSERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Arbitration Lost"] + #[inline(always)] + pub fn arblost(&self) -> ARBLOST_R { + ARBLOST_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Received Not Acknowledge"] + #[inline(always)] + pub fn rxnack(&self) -> RXNACK_R { + RXNACK_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 4:5 - Bus State"] + #[inline(always)] + pub fn busstate(&self) -> BUSSTATE_R { + BUSSTATE_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bit 6 - SCL Low Timeout"] + #[inline(always)] + pub fn lowtout(&self) -> LOWTOUT_R { + LOWTOUT_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Clock Hold"] + #[inline(always)] + pub fn clkhold(&self) -> CLKHOLD_R { + CLKHOLD_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Master SCL Low Extend Timeout"] + #[inline(always)] + pub fn mexttout(&self) -> MEXTTOUT_R { + MEXTTOUT_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttout(&self) -> SEXTTOUT_R { + SEXTTOUT_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Length Error"] + #[inline(always)] + pub fn lenerr(&self) -> LENERR_R { + LENERR_R::new(((self.bits >> 10) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Bus Error"] + #[inline(always)] + pub fn buserr(&mut self) -> BUSERR_W { + BUSERR_W { w: self } + } + #[doc = "Bit 1 - Arbitration Lost"] + #[inline(always)] + pub fn arblost(&mut self) -> ARBLOST_W { + ARBLOST_W { w: self } + } + #[doc = "Bit 2 - Received Not Acknowledge"] + #[inline(always)] + pub fn rxnack(&mut self) -> RXNACK_W { + RXNACK_W { w: self } + } + #[doc = "Bits 4:5 - Bus State"] + #[inline(always)] + pub fn busstate(&mut self) -> BUSSTATE_W { + BUSSTATE_W { w: self } + } + #[doc = "Bit 6 - SCL Low Timeout"] + #[inline(always)] + pub fn lowtout(&mut self) -> LOWTOUT_W { + LOWTOUT_W { w: self } + } + #[doc = "Bit 7 - Clock Hold"] + #[inline(always)] + pub fn clkhold(&mut self) -> CLKHOLD_W { + CLKHOLD_W { w: self } + } + #[doc = "Bit 8 - Master SCL Low Extend Timeout"] + #[inline(always)] + pub fn mexttout(&mut self) -> MEXTTOUT_W { + MEXTTOUT_W { w: self } + } + #[doc = "Bit 9 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttout(&mut self) -> SEXTTOUT_W { + SEXTTOUT_W { w: self } + } + #[doc = "Bit 10 - Length Error"] + #[inline(always)] + pub fn lenerr(&mut self) -> LENERR_W { + LENERR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/sercom0/i2cm/syncbusy.rs b/pac/atsamc20n/src/sercom0/i2cm/syncbusy.rs new file mode 100644 index 000000000000..87dd418d1cd3 --- /dev/null +++ b/pac/atsamc20n/src/sercom0/i2cm/syncbusy.rs @@ -0,0 +1,93 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - SERCOM Enable Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYSOP` reader - System Operation Synchronization Busy"] +pub struct SYSOP_R(crate::FieldReader); +impl SYSOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYSOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYSOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM Enable Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - System Operation Synchronization Busy"] + #[inline(always)] + pub fn sysop(&self) -> SYSOP_R { + SYSOP_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +#[doc = "I2CM Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/sercom0/i2cs.rs b/pac/atsamc20n/src/sercom0/i2cs.rs new file mode 100644 index 000000000000..baf9513c6cc1 --- /dev/null +++ b/pac/atsamc20n/src/sercom0/i2cs.rs @@ -0,0 +1,36 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "I2CS Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "I2CS Control B"] +pub mod ctrlb; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "I2CS Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "I2CS Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "I2CS Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "I2CS Status"] +pub mod status; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "I2CS Synchronization Busy"] +pub mod syncbusy; +#[doc = "ADDR register accessor: an alias for `Reg`"] +pub type ADDR = crate::Reg; +#[doc = "I2CS Address"] +pub mod addr; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "I2CS Data"] +pub mod data; diff --git a/pac/atsamc20n/src/sercom0/i2cs/addr.rs b/pac/atsamc20n/src/sercom0/i2cs/addr.rs new file mode 100644 index 000000000000..c1b69ee22891 --- /dev/null +++ b/pac/atsamc20n/src/sercom0/i2cs/addr.rs @@ -0,0 +1,234 @@ +#[doc = "Register `ADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `GENCEN` reader - General Call Address Enable"] +pub struct GENCEN_R(crate::FieldReader); +impl GENCEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENCEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENCEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENCEN` writer - General Call Address Enable"] +pub struct GENCEN_W<'a> { + w: &'a mut W, +} +impl<'a> GENCEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ADDR` reader - Address Value"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - Address Value"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03ff << 1)) | ((value as u32 & 0x03ff) << 1); + self.w + } +} +#[doc = "Field `TENBITEN` reader - Ten Bit Addressing Enable"] +pub struct TENBITEN_R(crate::FieldReader); +impl TENBITEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TENBITEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TENBITEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TENBITEN` writer - Ten Bit Addressing Enable"] +pub struct TENBITEN_W<'a> { + w: &'a mut W, +} +impl<'a> TENBITEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `ADDRMASK` reader - Address Mask"] +pub struct ADDRMASK_R(crate::FieldReader); +impl ADDRMASK_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + ADDRMASK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDRMASK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDRMASK` writer - Address Mask"] +pub struct ADDRMASK_W<'a> { + w: &'a mut W, +} +impl<'a> ADDRMASK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03ff << 17)) | ((value as u32 & 0x03ff) << 17); + self.w + } +} +impl R { + #[doc = "Bit 0 - General Call Address Enable"] + #[inline(always)] + pub fn gencen(&self) -> GENCEN_R { + GENCEN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bits 1:10 - Address Value"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new(((self.bits >> 1) & 0x03ff) as u16) + } + #[doc = "Bit 15 - Ten Bit Addressing Enable"] + #[inline(always)] + pub fn tenbiten(&self) -> TENBITEN_R { + TENBITEN_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 17:26 - Address Mask"] + #[inline(always)] + pub fn addrmask(&self) -> ADDRMASK_R { + ADDRMASK_R::new(((self.bits >> 17) & 0x03ff) as u16) + } +} +impl W { + #[doc = "Bit 0 - General Call Address Enable"] + #[inline(always)] + pub fn gencen(&mut self) -> GENCEN_W { + GENCEN_W { w: self } + } + #[doc = "Bits 1:10 - Address Value"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Bit 15 - Ten Bit Addressing Enable"] + #[inline(always)] + pub fn tenbiten(&mut self) -> TENBITEN_W { + TENBITEN_W { w: self } + } + #[doc = "Bits 17:26 - Address Mask"] + #[inline(always)] + pub fn addrmask(&mut self) -> ADDRMASK_W { + ADDRMASK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [addr](index.html) module"] +pub struct ADDR_SPEC; +impl crate::RegisterSpec for ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [addr::R](R) reader structure"] +impl crate::Readable for ADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [addr::W](W) writer structure"] +impl crate::Writable for ADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ADDR to value 0"] +impl crate::Resettable for ADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/sercom0/i2cs/ctrla.rs b/pac/atsamc20n/src/sercom0/i2cs/ctrla.rs new file mode 100644 index 000000000000..ec93812b004f --- /dev/null +++ b/pac/atsamc20n/src/sercom0/i2cs/ctrla.rs @@ -0,0 +1,744 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: USART with external clock"] + USART_EXT_CLK = 0, + #[doc = "1: USART with internal clock"] + USART_INT_CLK = 1, + #[doc = "2: SPI in slave operation"] + SPI_SLAVE = 2, + #[doc = "3: SPI in master operation"] + SPI_MASTER = 3, + #[doc = "4: I2C slave operation"] + I2C_SLAVE = 4, + #[doc = "5: I2C master operation"] + I2C_MASTER = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::USART_EXT_CLK), + 1 => Some(MODE_A::USART_INT_CLK), + 2 => Some(MODE_A::SPI_SLAVE), + 3 => Some(MODE_A::SPI_MASTER), + 4 => Some(MODE_A::I2C_SLAVE), + 5 => Some(MODE_A::I2C_MASTER), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_EXT_CLK`"] + #[inline(always)] + pub fn is_usart_ext_clk(&self) -> bool { + **self == MODE_A::USART_EXT_CLK + } + #[doc = "Checks if the value of the field is `USART_INT_CLK`"] + #[inline(always)] + pub fn is_usart_int_clk(&self) -> bool { + **self == MODE_A::USART_INT_CLK + } + #[doc = "Checks if the value of the field is `SPI_SLAVE`"] + #[inline(always)] + pub fn is_spi_slave(&self) -> bool { + **self == MODE_A::SPI_SLAVE + } + #[doc = "Checks if the value of the field is `SPI_MASTER`"] + #[inline(always)] + pub fn is_spi_master(&self) -> bool { + **self == MODE_A::SPI_MASTER + } + #[doc = "Checks if the value of the field is `I2C_SLAVE`"] + #[inline(always)] + pub fn is_i2c_slave(&self) -> bool { + **self == MODE_A::I2C_SLAVE + } + #[doc = "Checks if the value of the field is `I2C_MASTER`"] + #[inline(always)] + pub fn is_i2c_master(&self) -> bool { + **self == MODE_A::I2C_MASTER + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART with external clock"] + #[inline(always)] + pub fn usart_ext_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_EXT_CLK) + } + #[doc = "USART with internal clock"] + #[inline(always)] + pub fn usart_int_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_INT_CLK) + } + #[doc = "SPI in slave operation"] + #[inline(always)] + pub fn spi_slave(self) -> &'a mut W { + self.variant(MODE_A::SPI_SLAVE) + } + #[doc = "SPI in master operation"] + #[inline(always)] + pub fn spi_master(self) -> &'a mut W { + self.variant(MODE_A::SPI_MASTER) + } + #[doc = "I2C slave operation"] + #[inline(always)] + pub fn i2c_slave(self) -> &'a mut W { + self.variant(MODE_A::I2C_SLAVE) + } + #[doc = "I2C master operation"] + #[inline(always)] + pub fn i2c_master(self) -> &'a mut W { + self.variant(MODE_A::I2C_MASTER) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 2)) | ((value as u32 & 0x07) << 2); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `PINOUT` reader - Pin Usage"] +pub struct PINOUT_R(crate::FieldReader); +impl PINOUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PINOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PINOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PINOUT` writer - Pin Usage"] +pub struct PINOUT_W<'a> { + w: &'a mut W, +} +impl<'a> PINOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "SDA Hold Time\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SDAHOLD_A { + #[doc = "0: Disabled"] + DISABLE = 0, + #[doc = "1: 50-100ns hold time"] + _75NS = 1, + #[doc = "2: 300-600ns hold time"] + _450NS = 2, + #[doc = "3: 400-800ns hold time"] + _600NS = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SDAHOLD_A) -> Self { + variant as _ + } +} +#[doc = "Field `SDAHOLD` reader - SDA Hold Time"] +pub struct SDAHOLD_R(crate::FieldReader); +impl SDAHOLD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SDAHOLD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SDAHOLD_A { + match self.bits { + 0 => SDAHOLD_A::DISABLE, + 1 => SDAHOLD_A::_75NS, + 2 => SDAHOLD_A::_450NS, + 3 => SDAHOLD_A::_600NS, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == SDAHOLD_A::DISABLE + } + #[doc = "Checks if the value of the field is `_75NS`"] + #[inline(always)] + pub fn is_75ns(&self) -> bool { + **self == SDAHOLD_A::_75NS + } + #[doc = "Checks if the value of the field is `_450NS`"] + #[inline(always)] + pub fn is_450ns(&self) -> bool { + **self == SDAHOLD_A::_450NS + } + #[doc = "Checks if the value of the field is `_600NS`"] + #[inline(always)] + pub fn is_600ns(&self) -> bool { + **self == SDAHOLD_A::_600NS + } +} +impl core::ops::Deref for SDAHOLD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SDAHOLD` writer - SDA Hold Time"] +pub struct SDAHOLD_W<'a> { + w: &'a mut W, +} +impl<'a> SDAHOLD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SDAHOLD_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(SDAHOLD_A::DISABLE) + } + #[doc = "50-100ns hold time"] + #[inline(always)] + pub fn _75ns(self) -> &'a mut W { + self.variant(SDAHOLD_A::_75NS) + } + #[doc = "300-600ns hold time"] + #[inline(always)] + pub fn _450ns(self) -> &'a mut W { + self.variant(SDAHOLD_A::_450NS) + } + #[doc = "400-800ns hold time"] + #[inline(always)] + pub fn _600ns(self) -> &'a mut W { + self.variant(SDAHOLD_A::_600NS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 20)) | ((value as u32 & 0x03) << 20); + self.w + } +} +#[doc = "Field `SEXTTOEN` reader - Slave SCL Low Extend Timeout"] +pub struct SEXTTOEN_R(crate::FieldReader); +impl SEXTTOEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SEXTTOEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEXTTOEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEXTTOEN` writer - Slave SCL Low Extend Timeout"] +pub struct SEXTTOEN_W<'a> { + w: &'a mut W, +} +impl<'a> SEXTTOEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Transfer Speed\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SPEED_A { + #[doc = "0: Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz"] + STANDARD_AND_FAST_MODE = 0, + #[doc = "1: Fast-mode Plus Upto 1MHz"] + FASTPLUS_MODE = 1, + #[doc = "2: High-speed mode Upto 3.4MHz"] + HIGH_SPEED_MODE = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SPEED_A) -> Self { + variant as _ + } +} +#[doc = "Field `SPEED` reader - Transfer Speed"] +pub struct SPEED_R(crate::FieldReader); +impl SPEED_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SPEED_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SPEED_A::STANDARD_AND_FAST_MODE), + 1 => Some(SPEED_A::FASTPLUS_MODE), + 2 => Some(SPEED_A::HIGH_SPEED_MODE), + _ => None, + } + } + #[doc = "Checks if the value of the field is `STANDARD_AND_FAST_MODE`"] + #[inline(always)] + pub fn is_standard_and_fast_mode(&self) -> bool { + **self == SPEED_A::STANDARD_AND_FAST_MODE + } + #[doc = "Checks if the value of the field is `FASTPLUS_MODE`"] + #[inline(always)] + pub fn is_fastplus_mode(&self) -> bool { + **self == SPEED_A::FASTPLUS_MODE + } + #[doc = "Checks if the value of the field is `HIGH_SPEED_MODE`"] + #[inline(always)] + pub fn is_high_speed_mode(&self) -> bool { + **self == SPEED_A::HIGH_SPEED_MODE + } +} +impl core::ops::Deref for SPEED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SPEED` writer - Transfer Speed"] +pub struct SPEED_W<'a> { + w: &'a mut W, +} +impl<'a> SPEED_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SPEED_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz"] + #[inline(always)] + pub fn standard_and_fast_mode(self) -> &'a mut W { + self.variant(SPEED_A::STANDARD_AND_FAST_MODE) + } + #[doc = "Fast-mode Plus Upto 1MHz"] + #[inline(always)] + pub fn fastplus_mode(self) -> &'a mut W { + self.variant(SPEED_A::FASTPLUS_MODE) + } + #[doc = "High-speed mode Upto 3.4MHz"] + #[inline(always)] + pub fn high_speed_mode(self) -> &'a mut W { + self.variant(SPEED_A::HIGH_SPEED_MODE) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 24)) | ((value as u32 & 0x03) << 24); + self.w + } +} +#[doc = "Field `SCLSM` reader - SCL Clock Stretch Mode"] +pub struct SCLSM_R(crate::FieldReader); +impl SCLSM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SCLSM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SCLSM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SCLSM` writer - SCL Clock Stretch Mode"] +pub struct SCLSM_W<'a> { + w: &'a mut W, +} +impl<'a> SCLSM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +#[doc = "Field `LOWTOUTEN` reader - SCL Low Timeout Enable"] +pub struct LOWTOUTEN_R(crate::FieldReader); +impl LOWTOUTEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LOWTOUTEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOWTOUTEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LOWTOUTEN` writer - SCL Low Timeout Enable"] +pub struct LOWTOUTEN_W<'a> { + w: &'a mut W, +} +impl<'a> LOWTOUTEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x07) as u8) + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 16 - Pin Usage"] + #[inline(always)] + pub fn pinout(&self) -> PINOUT_R { + PINOUT_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bits 20:21 - SDA Hold Time"] + #[inline(always)] + pub fn sdahold(&self) -> SDAHOLD_R { + SDAHOLD_R::new(((self.bits >> 20) & 0x03) as u8) + } + #[doc = "Bit 23 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttoen(&self) -> SEXTTOEN_R { + SEXTTOEN_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bits 24:25 - Transfer Speed"] + #[inline(always)] + pub fn speed(&self) -> SPEED_R { + SPEED_R::new(((self.bits >> 24) & 0x03) as u8) + } + #[doc = "Bit 27 - SCL Clock Stretch Mode"] + #[inline(always)] + pub fn sclsm(&self) -> SCLSM_R { + SCLSM_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 30 - SCL Low Timeout Enable"] + #[inline(always)] + pub fn lowtouten(&self) -> LOWTOUTEN_R { + LOWTOUTEN_R::new(((self.bits >> 30) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 16 - Pin Usage"] + #[inline(always)] + pub fn pinout(&mut self) -> PINOUT_W { + PINOUT_W { w: self } + } + #[doc = "Bits 20:21 - SDA Hold Time"] + #[inline(always)] + pub fn sdahold(&mut self) -> SDAHOLD_W { + SDAHOLD_W { w: self } + } + #[doc = "Bit 23 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttoen(&mut self) -> SEXTTOEN_W { + SEXTTOEN_W { w: self } + } + #[doc = "Bits 24:25 - Transfer Speed"] + #[inline(always)] + pub fn speed(&mut self) -> SPEED_W { + SPEED_W { w: self } + } + #[doc = "Bit 27 - SCL Clock Stretch Mode"] + #[inline(always)] + pub fn sclsm(&mut self) -> SCLSM_W { + SCLSM_W { w: self } + } + #[doc = "Bit 30 - SCL Low Timeout Enable"] + #[inline(always)] + pub fn lowtouten(&mut self) -> LOWTOUTEN_W { + LOWTOUTEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/sercom0/i2cs/ctrlb.rs b/pac/atsamc20n/src/sercom0/i2cs/ctrlb.rs new file mode 100644 index 000000000000..b20f48581ed5 --- /dev/null +++ b/pac/atsamc20n/src/sercom0/i2cs/ctrlb.rs @@ -0,0 +1,328 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SMEN` reader - Smart Mode Enable"] +pub struct SMEN_R(crate::FieldReader); +impl SMEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SMEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SMEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SMEN` writer - Smart Mode Enable"] +pub struct SMEN_W<'a> { + w: &'a mut W, +} +impl<'a> SMEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `GCMD` reader - PMBus Group Command"] +pub struct GCMD_R(crate::FieldReader); +impl GCMD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GCMD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GCMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GCMD` writer - PMBus Group Command"] +pub struct GCMD_W<'a> { + w: &'a mut W, +} +impl<'a> GCMD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `AACKEN` reader - Automatic Address Acknowledge"] +pub struct AACKEN_R(crate::FieldReader); +impl AACKEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AACKEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AACKEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AACKEN` writer - Automatic Address Acknowledge"] +pub struct AACKEN_W<'a> { + w: &'a mut W, +} +impl<'a> AACKEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `AMODE` reader - Address Mode"] +pub struct AMODE_R(crate::FieldReader); +impl AMODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + AMODE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AMODE` writer - Address Mode"] +pub struct AMODE_W<'a> { + w: &'a mut W, +} +impl<'a> AMODE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 14)) | ((value as u32 & 0x03) << 14); + self.w + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Field `ACKACT` reader - Acknowledge Action"] +pub struct ACKACT_R(crate::FieldReader); +impl ACKACT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ACKACT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ACKACT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ACKACT` writer - Acknowledge Action"] +pub struct ACKACT_W<'a> { + w: &'a mut W, +} +impl<'a> ACKACT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +impl R { + #[doc = "Bit 8 - Smart Mode Enable"] + #[inline(always)] + pub fn smen(&self) -> SMEN_R { + SMEN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - PMBus Group Command"] + #[inline(always)] + pub fn gcmd(&self) -> GCMD_R { + GCMD_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Automatic Address Acknowledge"] + #[inline(always)] + pub fn aacken(&self) -> AACKEN_R { + AACKEN_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bits 14:15 - Address Mode"] + #[inline(always)] + pub fn amode(&self) -> AMODE_R { + AMODE_R::new(((self.bits >> 14) & 0x03) as u8) + } + #[doc = "Bits 16:17 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bit 18 - Acknowledge Action"] + #[inline(always)] + pub fn ackact(&self) -> ACKACT_R { + ACKACT_R::new(((self.bits >> 18) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 8 - Smart Mode Enable"] + #[inline(always)] + pub fn smen(&mut self) -> SMEN_W { + SMEN_W { w: self } + } + #[doc = "Bit 9 - PMBus Group Command"] + #[inline(always)] + pub fn gcmd(&mut self) -> GCMD_W { + GCMD_W { w: self } + } + #[doc = "Bit 10 - Automatic Address Acknowledge"] + #[inline(always)] + pub fn aacken(&mut self) -> AACKEN_W { + AACKEN_W { w: self } + } + #[doc = "Bits 14:15 - Address Mode"] + #[inline(always)] + pub fn amode(&mut self) -> AMODE_W { + AMODE_W { w: self } + } + #[doc = "Bits 16:17 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Bit 18 - Acknowledge Action"] + #[inline(always)] + pub fn ackact(&mut self) -> ACKACT_W { + ACKACT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/sercom0/i2cs/data.rs b/pac/atsamc20n/src/sercom0/i2cs/data.rs new file mode 100644 index 000000000000..d8bfe070431a --- /dev/null +++ b/pac/atsamc20n/src/sercom0/i2cs/data.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data Value"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data Value"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Data Value"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Value"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/sercom0/i2cs/intenclr.rs b/pac/atsamc20n/src/sercom0/i2cs/intenclr.rs new file mode 100644 index 000000000000..49f5191c8d63 --- /dev/null +++ b/pac/atsamc20n/src/sercom0/i2cs/intenclr.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PREC` reader - Stop Received Interrupt Disable"] +pub struct PREC_R(crate::FieldReader); +impl PREC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PREC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PREC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PREC` writer - Stop Received Interrupt Disable"] +pub struct PREC_W<'a> { + w: &'a mut W, +} +impl<'a> PREC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `AMATCH` reader - Address Match Interrupt Disable"] +pub struct AMATCH_R(crate::FieldReader); +impl AMATCH_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AMATCH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AMATCH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AMATCH` writer - Address Match Interrupt Disable"] +pub struct AMATCH_W<'a> { + w: &'a mut W, +} +impl<'a> AMATCH_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `DRDY` reader - Data Interrupt Disable"] +pub struct DRDY_R(crate::FieldReader); +impl DRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRDY` writer - Data Interrupt Disable"] +pub struct DRDY_W<'a> { + w: &'a mut W, +} +impl<'a> DRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Disable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Disable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Stop Received Interrupt Disable"] + #[inline(always)] + pub fn prec(&self) -> PREC_R { + PREC_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Address Match Interrupt Disable"] + #[inline(always)] + pub fn amatch(&self) -> AMATCH_R { + AMATCH_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Data Interrupt Disable"] + #[inline(always)] + pub fn drdy(&self) -> DRDY_R { + DRDY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Stop Received Interrupt Disable"] + #[inline(always)] + pub fn prec(&mut self) -> PREC_W { + PREC_W { w: self } + } + #[doc = "Bit 1 - Address Match Interrupt Disable"] + #[inline(always)] + pub fn amatch(&mut self) -> AMATCH_W { + AMATCH_W { w: self } + } + #[doc = "Bit 2 - Data Interrupt Disable"] + #[inline(always)] + pub fn drdy(&mut self) -> DRDY_W { + DRDY_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/sercom0/i2cs/intenset.rs b/pac/atsamc20n/src/sercom0/i2cs/intenset.rs new file mode 100644 index 000000000000..97ea784d7476 --- /dev/null +++ b/pac/atsamc20n/src/sercom0/i2cs/intenset.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PREC` reader - Stop Received Interrupt Enable"] +pub struct PREC_R(crate::FieldReader); +impl PREC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PREC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PREC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PREC` writer - Stop Received Interrupt Enable"] +pub struct PREC_W<'a> { + w: &'a mut W, +} +impl<'a> PREC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `AMATCH` reader - Address Match Interrupt Enable"] +pub struct AMATCH_R(crate::FieldReader); +impl AMATCH_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AMATCH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AMATCH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AMATCH` writer - Address Match Interrupt Enable"] +pub struct AMATCH_W<'a> { + w: &'a mut W, +} +impl<'a> AMATCH_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `DRDY` reader - Data Interrupt Enable"] +pub struct DRDY_R(crate::FieldReader); +impl DRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRDY` writer - Data Interrupt Enable"] +pub struct DRDY_W<'a> { + w: &'a mut W, +} +impl<'a> DRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Stop Received Interrupt Enable"] + #[inline(always)] + pub fn prec(&self) -> PREC_R { + PREC_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Address Match Interrupt Enable"] + #[inline(always)] + pub fn amatch(&self) -> AMATCH_R { + AMATCH_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Data Interrupt Enable"] + #[inline(always)] + pub fn drdy(&self) -> DRDY_R { + DRDY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Stop Received Interrupt Enable"] + #[inline(always)] + pub fn prec(&mut self) -> PREC_W { + PREC_W { w: self } + } + #[doc = "Bit 1 - Address Match Interrupt Enable"] + #[inline(always)] + pub fn amatch(&mut self) -> AMATCH_W { + AMATCH_W { w: self } + } + #[doc = "Bit 2 - Data Interrupt Enable"] + #[inline(always)] + pub fn drdy(&mut self) -> DRDY_W { + DRDY_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/sercom0/i2cs/intflag.rs b/pac/atsamc20n/src/sercom0/i2cs/intflag.rs new file mode 100644 index 000000000000..2eee333e4e59 --- /dev/null +++ b/pac/atsamc20n/src/sercom0/i2cs/intflag.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PREC` reader - Stop Received Interrupt"] +pub struct PREC_R(crate::FieldReader); +impl PREC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PREC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PREC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PREC` writer - Stop Received Interrupt"] +pub struct PREC_W<'a> { + w: &'a mut W, +} +impl<'a> PREC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `AMATCH` reader - Address Match Interrupt"] +pub struct AMATCH_R(crate::FieldReader); +impl AMATCH_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AMATCH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AMATCH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AMATCH` writer - Address Match Interrupt"] +pub struct AMATCH_W<'a> { + w: &'a mut W, +} +impl<'a> AMATCH_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `DRDY` reader - Data Interrupt"] +pub struct DRDY_R(crate::FieldReader); +impl DRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRDY` writer - Data Interrupt"] +pub struct DRDY_W<'a> { + w: &'a mut W, +} +impl<'a> DRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Stop Received Interrupt"] + #[inline(always)] + pub fn prec(&self) -> PREC_R { + PREC_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Address Match Interrupt"] + #[inline(always)] + pub fn amatch(&self) -> AMATCH_R { + AMATCH_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Data Interrupt"] + #[inline(always)] + pub fn drdy(&self) -> DRDY_R { + DRDY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Stop Received Interrupt"] + #[inline(always)] + pub fn prec(&mut self) -> PREC_W { + PREC_W { w: self } + } + #[doc = "Bit 1 - Address Match Interrupt"] + #[inline(always)] + pub fn amatch(&mut self) -> AMATCH_W { + AMATCH_W { w: self } + } + #[doc = "Bit 2 - Data Interrupt"] + #[inline(always)] + pub fn drdy(&mut self) -> DRDY_W { + DRDY_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/sercom0/i2cs/status.rs b/pac/atsamc20n/src/sercom0/i2cs/status.rs new file mode 100644 index 000000000000..b3f6d218fa66 --- /dev/null +++ b/pac/atsamc20n/src/sercom0/i2cs/status.rs @@ -0,0 +1,489 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BUSERR` reader - Bus Error"] +pub struct BUSERR_R(crate::FieldReader); +impl BUSERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSERR` writer - Bus Error"] +pub struct BUSERR_W<'a> { + w: &'a mut W, +} +impl<'a> BUSERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `COLL` reader - Transmit Collision"] +pub struct COLL_R(crate::FieldReader); +impl COLL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COLL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COLL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COLL` writer - Transmit Collision"] +pub struct COLL_W<'a> { + w: &'a mut W, +} +impl<'a> COLL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXNACK` reader - Received Not Acknowledge"] +pub struct RXNACK_R(crate::FieldReader); +impl RXNACK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXNACK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXNACK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXNACK` writer - Received Not Acknowledge"] +pub struct RXNACK_W<'a> { + w: &'a mut W, +} +impl<'a> RXNACK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `DIR` reader - Read/Write Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Read/Write Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `SR` reader - Repeated Start"] +pub struct SR_R(crate::FieldReader); +impl SR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SR` writer - Repeated Start"] +pub struct SR_W<'a> { + w: &'a mut W, +} +impl<'a> SR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `LOWTOUT` reader - SCL Low Timeout"] +pub struct LOWTOUT_R(crate::FieldReader); +impl LOWTOUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LOWTOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOWTOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LOWTOUT` writer - SCL Low Timeout"] +pub struct LOWTOUT_W<'a> { + w: &'a mut W, +} +impl<'a> LOWTOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `CLKHOLD` reader - Clock Hold"] +pub struct CLKHOLD_R(crate::FieldReader); +impl CLKHOLD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKHOLD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKHOLD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKHOLD` writer - Clock Hold"] +pub struct CLKHOLD_W<'a> { + w: &'a mut W, +} +impl<'a> CLKHOLD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `SEXTTOUT` reader - Slave SCL Low Extend Timeout"] +pub struct SEXTTOUT_R(crate::FieldReader); +impl SEXTTOUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SEXTTOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEXTTOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEXTTOUT` writer - Slave SCL Low Extend Timeout"] +pub struct SEXTTOUT_W<'a> { + w: &'a mut W, +} +impl<'a> SEXTTOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `HS` reader - High Speed"] +pub struct HS_R(crate::FieldReader); +impl HS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HS` writer - High Speed"] +pub struct HS_W<'a> { + w: &'a mut W, +} +impl<'a> HS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u16 & 0x01) << 10); + self.w + } +} +impl R { + #[doc = "Bit 0 - Bus Error"] + #[inline(always)] + pub fn buserr(&self) -> BUSERR_R { + BUSERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Collision"] + #[inline(always)] + pub fn coll(&self) -> COLL_R { + COLL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Received Not Acknowledge"] + #[inline(always)] + pub fn rxnack(&self) -> RXNACK_R { + RXNACK_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Read/Write Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Repeated Start"] + #[inline(always)] + pub fn sr(&self) -> SR_R { + SR_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 6 - SCL Low Timeout"] + #[inline(always)] + pub fn lowtout(&self) -> LOWTOUT_R { + LOWTOUT_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Clock Hold"] + #[inline(always)] + pub fn clkhold(&self) -> CLKHOLD_R { + CLKHOLD_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 9 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttout(&self) -> SEXTTOUT_R { + SEXTTOUT_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - High Speed"] + #[inline(always)] + pub fn hs(&self) -> HS_R { + HS_R::new(((self.bits >> 10) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Bus Error"] + #[inline(always)] + pub fn buserr(&mut self) -> BUSERR_W { + BUSERR_W { w: self } + } + #[doc = "Bit 1 - Transmit Collision"] + #[inline(always)] + pub fn coll(&mut self) -> COLL_W { + COLL_W { w: self } + } + #[doc = "Bit 2 - Received Not Acknowledge"] + #[inline(always)] + pub fn rxnack(&mut self) -> RXNACK_W { + RXNACK_W { w: self } + } + #[doc = "Bit 3 - Read/Write Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 4 - Repeated Start"] + #[inline(always)] + pub fn sr(&mut self) -> SR_W { + SR_W { w: self } + } + #[doc = "Bit 6 - SCL Low Timeout"] + #[inline(always)] + pub fn lowtout(&mut self) -> LOWTOUT_W { + LOWTOUT_W { w: self } + } + #[doc = "Bit 7 - Clock Hold"] + #[inline(always)] + pub fn clkhold(&mut self) -> CLKHOLD_W { + CLKHOLD_W { w: self } + } + #[doc = "Bit 9 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttout(&mut self) -> SEXTTOUT_W { + SEXTTOUT_W { w: self } + } + #[doc = "Bit 10 - High Speed"] + #[inline(always)] + pub fn hs(&mut self) -> HS_W { + HS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/sercom0/i2cs/syncbusy.rs b/pac/atsamc20n/src/sercom0/i2cs/syncbusy.rs new file mode 100644 index 000000000000..38e2509d9666 --- /dev/null +++ b/pac/atsamc20n/src/sercom0/i2cs/syncbusy.rs @@ -0,0 +1,73 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - SERCOM Enable Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM Enable Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +#[doc = "I2CS Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/sercom0/spim.rs b/pac/atsamc20n/src/sercom0/spim.rs new file mode 100644 index 000000000000..528e38e1b811 --- /dev/null +++ b/pac/atsamc20n/src/sercom0/spim.rs @@ -0,0 +1,44 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "SPIM Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "SPIM Control B"] +pub mod ctrlb; +#[doc = "BAUD register accessor: an alias for `Reg`"] +pub type BAUD = crate::Reg; +#[doc = "SPIM Baud Rate"] +pub mod baud; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "SPIM Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "SPIM Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "SPIM Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "SPIM Status"] +pub mod status; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "SPIM Synchronization Busy"] +pub mod syncbusy; +#[doc = "ADDR register accessor: an alias for `Reg`"] +pub type ADDR = crate::Reg; +#[doc = "SPIM Address"] +pub mod addr; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "SPIM Data"] +pub mod data; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "SPIM Debug Control"] +pub mod dbgctrl; diff --git a/pac/atsamc20n/src/sercom0/spim/addr.rs b/pac/atsamc20n/src/sercom0/spim/addr.rs new file mode 100644 index 000000000000..7c25cd522ea2 --- /dev/null +++ b/pac/atsamc20n/src/sercom0/spim/addr.rs @@ -0,0 +1,140 @@ +#[doc = "Register `ADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ADDR` reader - Address Value"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - Address Value"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +#[doc = "Field `ADDRMASK` reader - Address Mask"] +pub struct ADDRMASK_R(crate::FieldReader); +impl ADDRMASK_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ADDRMASK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDRMASK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDRMASK` writer - Address Mask"] +pub struct ADDRMASK_W<'a> { + w: &'a mut W, +} +impl<'a> ADDRMASK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Address Value"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 16:23 - Address Mask"] + #[inline(always)] + pub fn addrmask(&self) -> ADDRMASK_R { + ADDRMASK_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Address Value"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Bits 16:23 - Address Mask"] + #[inline(always)] + pub fn addrmask(&mut self) -> ADDRMASK_W { + ADDRMASK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [addr](index.html) module"] +pub struct ADDR_SPEC; +impl crate::RegisterSpec for ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [addr::R](R) reader structure"] +impl crate::Readable for ADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [addr::W](W) writer structure"] +impl crate::Writable for ADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ADDR to value 0"] +impl crate::Resettable for ADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/sercom0/spim/baud.rs b/pac/atsamc20n/src/sercom0/spim/baud.rs new file mode 100644 index 000000000000..6bec9ca74355 --- /dev/null +++ b/pac/atsamc20n/src/sercom0/spim/baud.rs @@ -0,0 +1,103 @@ +#[doc = "Register `BAUD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud](index.html) module"] +pub struct BAUD_SPEC; +impl crate::RegisterSpec for BAUD_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [baud::R](R) reader structure"] +impl crate::Readable for BAUD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud::W](W) writer structure"] +impl crate::Writable for BAUD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD to value 0"] +impl crate::Resettable for BAUD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/sercom0/spim/ctrla.rs b/pac/atsamc20n/src/sercom0/spim/ctrla.rs new file mode 100644 index 000000000000..44028f8cbdd7 --- /dev/null +++ b/pac/atsamc20n/src/sercom0/spim/ctrla.rs @@ -0,0 +1,992 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: USART with external clock"] + USART_EXT_CLK = 0, + #[doc = "1: USART with internal clock"] + USART_INT_CLK = 1, + #[doc = "2: SPI in slave operation"] + SPI_SLAVE = 2, + #[doc = "3: SPI in master operation"] + SPI_MASTER = 3, + #[doc = "4: I2C slave operation"] + I2C_SLAVE = 4, + #[doc = "5: I2C master operation"] + I2C_MASTER = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::USART_EXT_CLK), + 1 => Some(MODE_A::USART_INT_CLK), + 2 => Some(MODE_A::SPI_SLAVE), + 3 => Some(MODE_A::SPI_MASTER), + 4 => Some(MODE_A::I2C_SLAVE), + 5 => Some(MODE_A::I2C_MASTER), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_EXT_CLK`"] + #[inline(always)] + pub fn is_usart_ext_clk(&self) -> bool { + **self == MODE_A::USART_EXT_CLK + } + #[doc = "Checks if the value of the field is `USART_INT_CLK`"] + #[inline(always)] + pub fn is_usart_int_clk(&self) -> bool { + **self == MODE_A::USART_INT_CLK + } + #[doc = "Checks if the value of the field is `SPI_SLAVE`"] + #[inline(always)] + pub fn is_spi_slave(&self) -> bool { + **self == MODE_A::SPI_SLAVE + } + #[doc = "Checks if the value of the field is `SPI_MASTER`"] + #[inline(always)] + pub fn is_spi_master(&self) -> bool { + **self == MODE_A::SPI_MASTER + } + #[doc = "Checks if the value of the field is `I2C_SLAVE`"] + #[inline(always)] + pub fn is_i2c_slave(&self) -> bool { + **self == MODE_A::I2C_SLAVE + } + #[doc = "Checks if the value of the field is `I2C_MASTER`"] + #[inline(always)] + pub fn is_i2c_master(&self) -> bool { + **self == MODE_A::I2C_MASTER + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART with external clock"] + #[inline(always)] + pub fn usart_ext_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_EXT_CLK) + } + #[doc = "USART with internal clock"] + #[inline(always)] + pub fn usart_int_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_INT_CLK) + } + #[doc = "SPI in slave operation"] + #[inline(always)] + pub fn spi_slave(self) -> &'a mut W { + self.variant(MODE_A::SPI_SLAVE) + } + #[doc = "SPI in master operation"] + #[inline(always)] + pub fn spi_master(self) -> &'a mut W { + self.variant(MODE_A::SPI_MASTER) + } + #[doc = "I2C slave operation"] + #[inline(always)] + pub fn i2c_slave(self) -> &'a mut W { + self.variant(MODE_A::I2C_SLAVE) + } + #[doc = "I2C master operation"] + #[inline(always)] + pub fn i2c_master(self) -> &'a mut W { + self.variant(MODE_A::I2C_MASTER) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 2)) | ((value as u32 & 0x07) << 2); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `IBON` reader - Immediate Buffer Overflow Notification"] +pub struct IBON_R(crate::FieldReader); +impl IBON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IBON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IBON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IBON` writer - Immediate Buffer Overflow Notification"] +pub struct IBON_W<'a> { + w: &'a mut W, +} +impl<'a> IBON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Data Out Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DOPO_A { + #[doc = "0: DO on PAD\\[0\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + PAD0 = 0, + #[doc = "1: DO on PAD\\[2\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + PAD1 = 1, + #[doc = "2: DO on PAD\\[3\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + PAD2 = 2, + #[doc = "3: DO on PAD\\[0\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + PAD3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DOPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `DOPO` reader - Data Out Pinout"] +pub struct DOPO_R(crate::FieldReader); +impl DOPO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DOPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DOPO_A { + match self.bits { + 0 => DOPO_A::PAD0, + 1 => DOPO_A::PAD1, + 2 => DOPO_A::PAD2, + 3 => DOPO_A::PAD3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == DOPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD1`"] + #[inline(always)] + pub fn is_pad1(&self) -> bool { + **self == DOPO_A::PAD1 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == DOPO_A::PAD2 + } + #[doc = "Checks if the value of the field is `PAD3`"] + #[inline(always)] + pub fn is_pad3(&self) -> bool { + **self == DOPO_A::PAD3 + } +} +impl core::ops::Deref for DOPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DOPO` writer - Data Out Pinout"] +pub struct DOPO_W<'a> { + w: &'a mut W, +} +impl<'a> DOPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DOPO_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "DO on PAD\\[0\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(DOPO_A::PAD0) + } + #[doc = "DO on PAD\\[2\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + #[inline(always)] + pub fn pad1(self) -> &'a mut W { + self.variant(DOPO_A::PAD1) + } + #[doc = "DO on PAD\\[3\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(DOPO_A::PAD2) + } + #[doc = "DO on PAD\\[0\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + #[inline(always)] + pub fn pad3(self) -> &'a mut W { + self.variant(DOPO_A::PAD3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Data In Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DIPO_A { + #[doc = "0: SERCOM PAD\\[0\\]"] + PAD0 = 0, + #[doc = "1: SERCOM PAD\\[1\\]"] + PAD1 = 1, + #[doc = "2: SERCOM PAD\\[2\\]"] + PAD2 = 2, + #[doc = "3: SERCOM PAD\\[3\\]"] + PAD3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DIPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `DIPO` reader - Data In Pinout"] +pub struct DIPO_R(crate::FieldReader); +impl DIPO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DIPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DIPO_A { + match self.bits { + 0 => DIPO_A::PAD0, + 1 => DIPO_A::PAD1, + 2 => DIPO_A::PAD2, + 3 => DIPO_A::PAD3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == DIPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD1`"] + #[inline(always)] + pub fn is_pad1(&self) -> bool { + **self == DIPO_A::PAD1 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == DIPO_A::PAD2 + } + #[doc = "Checks if the value of the field is `PAD3`"] + #[inline(always)] + pub fn is_pad3(&self) -> bool { + **self == DIPO_A::PAD3 + } +} +impl core::ops::Deref for DIPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIPO` writer - Data In Pinout"] +pub struct DIPO_W<'a> { + w: &'a mut W, +} +impl<'a> DIPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DIPO_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "SERCOM PAD\\[0\\]"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(DIPO_A::PAD0) + } + #[doc = "SERCOM PAD\\[1\\]"] + #[inline(always)] + pub fn pad1(self) -> &'a mut W { + self.variant(DIPO_A::PAD1) + } + #[doc = "SERCOM PAD\\[2\\]"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(DIPO_A::PAD2) + } + #[doc = "SERCOM PAD\\[3\\]"] + #[inline(always)] + pub fn pad3(self) -> &'a mut W { + self.variant(DIPO_A::PAD3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 20)) | ((value as u32 & 0x03) << 20); + self.w + } +} +#[doc = "Frame Format\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FORM_A { + #[doc = "0: SPI Frame"] + SPI_FRAME = 0, + #[doc = "2: SPI Frame with Addr"] + SPI_FRAME_WITH_ADDR = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FORM_A) -> Self { + variant as _ + } +} +#[doc = "Field `FORM` reader - Frame Format"] +pub struct FORM_R(crate::FieldReader); +impl FORM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FORM_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(FORM_A::SPI_FRAME), + 2 => Some(FORM_A::SPI_FRAME_WITH_ADDR), + _ => None, + } + } + #[doc = "Checks if the value of the field is `SPI_FRAME`"] + #[inline(always)] + pub fn is_spi_frame(&self) -> bool { + **self == FORM_A::SPI_FRAME + } + #[doc = "Checks if the value of the field is `SPI_FRAME_WITH_ADDR`"] + #[inline(always)] + pub fn is_spi_frame_with_addr(&self) -> bool { + **self == FORM_A::SPI_FRAME_WITH_ADDR + } +} +impl core::ops::Deref for FORM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FORM` writer - Frame Format"] +pub struct FORM_W<'a> { + w: &'a mut W, +} +impl<'a> FORM_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FORM_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "SPI Frame"] + #[inline(always)] + pub fn spi_frame(self) -> &'a mut W { + self.variant(FORM_A::SPI_FRAME) + } + #[doc = "SPI Frame with Addr"] + #[inline(always)] + pub fn spi_frame_with_addr(self) -> &'a mut W { + self.variant(FORM_A::SPI_FRAME_WITH_ADDR) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Clock Phase\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CPHA_A { + #[doc = "0: The data is sampled on a leading SCK edge and changed on a trailing SCK edge"] + LEADING_EDGE = 0, + #[doc = "1: The data is sampled on a trailing SCK edge and changed on a leading SCK edge"] + TRAILING_EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CPHA_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CPHA` reader - Clock Phase"] +pub struct CPHA_R(crate::FieldReader); +impl CPHA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPHA_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CPHA_A { + match self.bits { + false => CPHA_A::LEADING_EDGE, + true => CPHA_A::TRAILING_EDGE, + } + } + #[doc = "Checks if the value of the field is `LEADING_EDGE`"] + #[inline(always)] + pub fn is_leading_edge(&self) -> bool { + **self == CPHA_A::LEADING_EDGE + } + #[doc = "Checks if the value of the field is `TRAILING_EDGE`"] + #[inline(always)] + pub fn is_trailing_edge(&self) -> bool { + **self == CPHA_A::TRAILING_EDGE + } +} +impl core::ops::Deref for CPHA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPHA` writer - Clock Phase"] +pub struct CPHA_W<'a> { + w: &'a mut W, +} +impl<'a> CPHA_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CPHA_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "The data is sampled on a leading SCK edge and changed on a trailing SCK edge"] + #[inline(always)] + pub fn leading_edge(self) -> &'a mut W { + self.variant(CPHA_A::LEADING_EDGE) + } + #[doc = "The data is sampled on a trailing SCK edge and changed on a leading SCK edge"] + #[inline(always)] + pub fn trailing_edge(self) -> &'a mut W { + self.variant(CPHA_A::TRAILING_EDGE) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Clock Polarity\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CPOL_A { + #[doc = "0: SCK is low when idle"] + IDLE_LOW = 0, + #[doc = "1: SCK is high when idle"] + IDLE_HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CPOL_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CPOL` reader - Clock Polarity"] +pub struct CPOL_R(crate::FieldReader); +impl CPOL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPOL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CPOL_A { + match self.bits { + false => CPOL_A::IDLE_LOW, + true => CPOL_A::IDLE_HIGH, + } + } + #[doc = "Checks if the value of the field is `IDLE_LOW`"] + #[inline(always)] + pub fn is_idle_low(&self) -> bool { + **self == CPOL_A::IDLE_LOW + } + #[doc = "Checks if the value of the field is `IDLE_HIGH`"] + #[inline(always)] + pub fn is_idle_high(&self) -> bool { + **self == CPOL_A::IDLE_HIGH + } +} +impl core::ops::Deref for CPOL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPOL` writer - Clock Polarity"] +pub struct CPOL_W<'a> { + w: &'a mut W, +} +impl<'a> CPOL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CPOL_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "SCK is low when idle"] + #[inline(always)] + pub fn idle_low(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_LOW) + } + #[doc = "SCK is high when idle"] + #[inline(always)] + pub fn idle_high(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_HIGH) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29); + self.w + } +} +#[doc = "Data Order\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum DORD_A { + #[doc = "0: MSB is transferred first"] + MSB = 0, + #[doc = "1: LSB is transferred first"] + LSB = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DORD_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DORD` reader - Data Order"] +pub struct DORD_R(crate::FieldReader); +impl DORD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DORD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DORD_A { + match self.bits { + false => DORD_A::MSB, + true => DORD_A::LSB, + } + } + #[doc = "Checks if the value of the field is `MSB`"] + #[inline(always)] + pub fn is_msb(&self) -> bool { + **self == DORD_A::MSB + } + #[doc = "Checks if the value of the field is `LSB`"] + #[inline(always)] + pub fn is_lsb(&self) -> bool { + **self == DORD_A::LSB + } +} +impl core::ops::Deref for DORD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DORD` writer - Data Order"] +pub struct DORD_W<'a> { + w: &'a mut W, +} +impl<'a> DORD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DORD_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "MSB is transferred first"] + #[inline(always)] + pub fn msb(self) -> &'a mut W { + self.variant(DORD_A::MSB) + } + #[doc = "LSB is transferred first"] + #[inline(always)] + pub fn lsb(self) -> &'a mut W { + self.variant(DORD_A::LSB) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x07) as u8) + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&self) -> IBON_R { + IBON_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bits 16:17 - Data Out Pinout"] + #[inline(always)] + pub fn dopo(&self) -> DOPO_R { + DOPO_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bits 20:21 - Data In Pinout"] + #[inline(always)] + pub fn dipo(&self) -> DIPO_R { + DIPO_R::new(((self.bits >> 20) & 0x03) as u8) + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&self) -> FORM_R { + FORM_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 28 - Clock Phase"] + #[inline(always)] + pub fn cpha(&self) -> CPHA_R { + CPHA_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&self) -> CPOL_R { + CPOL_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&self) -> DORD_R { + DORD_R::new(((self.bits >> 30) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&mut self) -> IBON_W { + IBON_W { w: self } + } + #[doc = "Bits 16:17 - Data Out Pinout"] + #[inline(always)] + pub fn dopo(&mut self) -> DOPO_W { + DOPO_W { w: self } + } + #[doc = "Bits 20:21 - Data In Pinout"] + #[inline(always)] + pub fn dipo(&mut self) -> DIPO_W { + DIPO_W { w: self } + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&mut self) -> FORM_W { + FORM_W { w: self } + } + #[doc = "Bit 28 - Clock Phase"] + #[inline(always)] + pub fn cpha(&mut self) -> CPHA_W { + CPHA_W { w: self } + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&mut self) -> CPOL_W { + CPOL_W { w: self } + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&mut self) -> DORD_W { + DORD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/sercom0/spim/ctrlb.rs b/pac/atsamc20n/src/sercom0/spim/ctrlb.rs new file mode 100644 index 000000000000..3d94f824ce83 --- /dev/null +++ b/pac/atsamc20n/src/sercom0/spim/ctrlb.rs @@ -0,0 +1,439 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Character Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CHSIZE_A { + #[doc = "0: 8 bits"] + _8_BIT = 0, + #[doc = "1: 9 bits"] + _9_BIT = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CHSIZE_A) -> Self { + variant as _ + } +} +#[doc = "Field `CHSIZE` reader - Character Size"] +pub struct CHSIZE_R(crate::FieldReader); +impl CHSIZE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CHSIZE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CHSIZE_A::_8_BIT), + 1 => Some(CHSIZE_A::_9_BIT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_8_BIT`"] + #[inline(always)] + pub fn is_8_bit(&self) -> bool { + **self == CHSIZE_A::_8_BIT + } + #[doc = "Checks if the value of the field is `_9_BIT`"] + #[inline(always)] + pub fn is_9_bit(&self) -> bool { + **self == CHSIZE_A::_9_BIT + } +} +impl core::ops::Deref for CHSIZE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHSIZE` writer - Character Size"] +pub struct CHSIZE_W<'a> { + w: &'a mut W, +} +impl<'a> CHSIZE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CHSIZE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8 bits"] + #[inline(always)] + pub fn _8_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_8_BIT) + } + #[doc = "9 bits"] + #[inline(always)] + pub fn _9_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_9_BIT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Field `PLOADEN` reader - Data Preload Enable"] +pub struct PLOADEN_R(crate::FieldReader); +impl PLOADEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PLOADEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PLOADEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PLOADEN` writer - Data Preload Enable"] +pub struct PLOADEN_W<'a> { + w: &'a mut W, +} +impl<'a> PLOADEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `SSDE` reader - Slave Select Low Detect Enable"] +pub struct SSDE_R(crate::FieldReader); +impl SSDE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SSDE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSDE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSDE` writer - Slave Select Low Detect Enable"] +pub struct SSDE_W<'a> { + w: &'a mut W, +} +impl<'a> SSDE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `MSSEN` reader - Master Slave Select Enable"] +pub struct MSSEN_R(crate::FieldReader); +impl MSSEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MSSEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MSSEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MSSEN` writer - Master Slave Select Enable"] +pub struct MSSEN_W<'a> { + w: &'a mut W, +} +impl<'a> MSSEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Address Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum AMODE_A { + #[doc = "0: SPI Address mask"] + MASK = 0, + #[doc = "1: Two unique Addressess"] + _2_ADDRESSES = 1, + #[doc = "2: Address Range"] + RANGE = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: AMODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `AMODE` reader - Address Mode"] +pub struct AMODE_R(crate::FieldReader); +impl AMODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + AMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(AMODE_A::MASK), + 1 => Some(AMODE_A::_2_ADDRESSES), + 2 => Some(AMODE_A::RANGE), + _ => None, + } + } + #[doc = "Checks if the value of the field is `MASK`"] + #[inline(always)] + pub fn is_mask(&self) -> bool { + **self == AMODE_A::MASK + } + #[doc = "Checks if the value of the field is `_2_ADDRESSES`"] + #[inline(always)] + pub fn is_2_addresses(&self) -> bool { + **self == AMODE_A::_2_ADDRESSES + } + #[doc = "Checks if the value of the field is `RANGE`"] + #[inline(always)] + pub fn is_range(&self) -> bool { + **self == AMODE_A::RANGE + } +} +impl core::ops::Deref for AMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AMODE` writer - Address Mode"] +pub struct AMODE_W<'a> { + w: &'a mut W, +} +impl<'a> AMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: AMODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "SPI Address mask"] + #[inline(always)] + pub fn mask(self) -> &'a mut W { + self.variant(AMODE_A::MASK) + } + #[doc = "Two unique Addressess"] + #[inline(always)] + pub fn _2_addresses(self) -> &'a mut W { + self.variant(AMODE_A::_2_ADDRESSES) + } + #[doc = "Address Range"] + #[inline(always)] + pub fn range(self) -> &'a mut W { + self.variant(AMODE_A::RANGE) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 14)) | ((value as u32 & 0x03) << 14); + self.w + } +} +#[doc = "Field `RXEN` reader - Receiver Enable"] +pub struct RXEN_R(crate::FieldReader); +impl RXEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXEN` writer - Receiver Enable"] +pub struct RXEN_W<'a> { + w: &'a mut W, +} +impl<'a> RXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&self) -> CHSIZE_R { + CHSIZE_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 6 - Data Preload Enable"] + #[inline(always)] + pub fn ploaden(&self) -> PLOADEN_R { + PLOADEN_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 9 - Slave Select Low Detect Enable"] + #[inline(always)] + pub fn ssde(&self) -> SSDE_R { + SSDE_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 13 - Master Slave Select Enable"] + #[inline(always)] + pub fn mssen(&self) -> MSSEN_R { + MSSEN_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bits 14:15 - Address Mode"] + #[inline(always)] + pub fn amode(&self) -> AMODE_R { + AMODE_R::new(((self.bits >> 14) & 0x03) as u8) + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&self) -> RXEN_R { + RXEN_R::new(((self.bits >> 17) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&mut self) -> CHSIZE_W { + CHSIZE_W { w: self } + } + #[doc = "Bit 6 - Data Preload Enable"] + #[inline(always)] + pub fn ploaden(&mut self) -> PLOADEN_W { + PLOADEN_W { w: self } + } + #[doc = "Bit 9 - Slave Select Low Detect Enable"] + #[inline(always)] + pub fn ssde(&mut self) -> SSDE_W { + SSDE_W { w: self } + } + #[doc = "Bit 13 - Master Slave Select Enable"] + #[inline(always)] + pub fn mssen(&mut self) -> MSSEN_W { + MSSEN_W { w: self } + } + #[doc = "Bits 14:15 - Address Mode"] + #[inline(always)] + pub fn amode(&mut self) -> AMODE_W { + AMODE_W { w: self } + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&mut self) -> RXEN_W { + RXEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/sercom0/spim/data.rs b/pac/atsamc20n/src/sercom0/spim/data.rs new file mode 100644 index 000000000000..dc9cd020d2a5 --- /dev/null +++ b/pac/atsamc20n/src/sercom0/spim/data.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data Value"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data Value"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01ff) | (value as u32 & 0x01ff); + self.w + } +} +impl R { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new((self.bits & 0x01ff) as u16) + } +} +impl W { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/sercom0/spim/dbgctrl.rs b/pac/atsamc20n/src/sercom0/spim/dbgctrl.rs new file mode 100644 index 000000000000..d9aa7495940c --- /dev/null +++ b/pac/atsamc20n/src/sercom0/spim/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGSTOP` reader - Debug Mode"] +pub struct DBGSTOP_R(crate::FieldReader); +impl DBGSTOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGSTOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGSTOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGSTOP` writer - Debug Mode"] +pub struct DBGSTOP_W<'a> { + w: &'a mut W, +} +impl<'a> DBGSTOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&self) -> DBGSTOP_R { + DBGSTOP_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&mut self) -> DBGSTOP_W { + DBGSTOP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/sercom0/spim/intenclr.rs b/pac/atsamc20n/src/sercom0/spim/intenclr.rs new file mode 100644 index 000000000000..ccab3de4348d --- /dev/null +++ b/pac/atsamc20n/src/sercom0/spim/intenclr.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Disable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Disable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Disable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Disable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Disable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Disable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SSL` reader - Slave Select Low Interrupt Disable"] +pub struct SSL_R(crate::FieldReader); +impl SSL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SSL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSL` writer - Slave Select Low Interrupt Disable"] +pub struct SSL_W<'a> { + w: &'a mut W, +} +impl<'a> SSL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Disable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Disable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Slave Select Low Interrupt Disable"] + #[inline(always)] + pub fn ssl(&self) -> SSL_R { + SSL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Slave Select Low Interrupt Disable"] + #[inline(always)] + pub fn ssl(&mut self) -> SSL_W { + SSL_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/sercom0/spim/intenset.rs b/pac/atsamc20n/src/sercom0/spim/intenset.rs new file mode 100644 index 000000000000..d9779cf897c2 --- /dev/null +++ b/pac/atsamc20n/src/sercom0/spim/intenset.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Enable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Enable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Enable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Enable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Enable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Enable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SSL` reader - Slave Select Low Interrupt Enable"] +pub struct SSL_R(crate::FieldReader); +impl SSL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SSL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSL` writer - Slave Select Low Interrupt Enable"] +pub struct SSL_W<'a> { + w: &'a mut W, +} +impl<'a> SSL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Slave Select Low Interrupt Enable"] + #[inline(always)] + pub fn ssl(&self) -> SSL_R { + SSL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Slave Select Low Interrupt Enable"] + #[inline(always)] + pub fn ssl(&mut self) -> SSL_W { + SSL_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/sercom0/spim/intflag.rs b/pac/atsamc20n/src/sercom0/spim/intflag.rs new file mode 100644 index 000000000000..e9bc10c271b8 --- /dev/null +++ b/pac/atsamc20n/src/sercom0/spim/intflag.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SSL` reader - Slave Select Low Interrupt Flag"] +pub struct SSL_R(crate::FieldReader); +impl SSL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SSL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSL` writer - Slave Select Low Interrupt Flag"] +pub struct SSL_W<'a> { + w: &'a mut W, +} +impl<'a> SSL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Slave Select Low Interrupt Flag"] + #[inline(always)] + pub fn ssl(&self) -> SSL_R { + SSL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Slave Select Low Interrupt Flag"] + #[inline(always)] + pub fn ssl(&mut self) -> SSL_W { + SSL_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/sercom0/spim/status.rs b/pac/atsamc20n/src/sercom0/spim/status.rs new file mode 100644 index 000000000000..9919460bf0e2 --- /dev/null +++ b/pac/atsamc20n/src/sercom0/spim/status.rs @@ -0,0 +1,113 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BUFOVF` reader - Buffer Overflow"] +pub struct BUFOVF_R(crate::FieldReader); +impl BUFOVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUFOVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUFOVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUFOVF` writer - Buffer Overflow"] +pub struct BUFOVF_W<'a> { + w: &'a mut W, +} +impl<'a> BUFOVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&self) -> BUFOVF_R { + BUFOVF_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&mut self) -> BUFOVF_W { + BUFOVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/sercom0/spim/syncbusy.rs b/pac/atsamc20n/src/sercom0/spim/syncbusy.rs new file mode 100644 index 000000000000..bee13adf7084 --- /dev/null +++ b/pac/atsamc20n/src/sercom0/spim/syncbusy.rs @@ -0,0 +1,93 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - SERCOM Enable Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLB` reader - CTRLB Synchronization Busy"] +pub struct CTRLB_R(crate::FieldReader); +impl CTRLB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM Enable Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - CTRLB Synchronization Busy"] + #[inline(always)] + pub fn ctrlb(&self) -> CTRLB_R { + CTRLB_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +#[doc = "SPIM Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/sercom0/spis.rs b/pac/atsamc20n/src/sercom0/spis.rs new file mode 100644 index 000000000000..eed10c90c460 --- /dev/null +++ b/pac/atsamc20n/src/sercom0/spis.rs @@ -0,0 +1,44 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "SPIS Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "SPIS Control B"] +pub mod ctrlb; +#[doc = "BAUD register accessor: an alias for `Reg`"] +pub type BAUD = crate::Reg; +#[doc = "SPIS Baud Rate"] +pub mod baud; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "SPIS Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "SPIS Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "SPIS Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "SPIS Status"] +pub mod status; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "SPIS Synchronization Busy"] +pub mod syncbusy; +#[doc = "ADDR register accessor: an alias for `Reg`"] +pub type ADDR = crate::Reg; +#[doc = "SPIS Address"] +pub mod addr; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "SPIS Data"] +pub mod data; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "SPIS Debug Control"] +pub mod dbgctrl; diff --git a/pac/atsamc20n/src/sercom0/spis/addr.rs b/pac/atsamc20n/src/sercom0/spis/addr.rs new file mode 100644 index 000000000000..5fca0a698bfe --- /dev/null +++ b/pac/atsamc20n/src/sercom0/spis/addr.rs @@ -0,0 +1,140 @@ +#[doc = "Register `ADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ADDR` reader - Address Value"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - Address Value"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +#[doc = "Field `ADDRMASK` reader - Address Mask"] +pub struct ADDRMASK_R(crate::FieldReader); +impl ADDRMASK_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ADDRMASK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDRMASK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDRMASK` writer - Address Mask"] +pub struct ADDRMASK_W<'a> { + w: &'a mut W, +} +impl<'a> ADDRMASK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Address Value"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 16:23 - Address Mask"] + #[inline(always)] + pub fn addrmask(&self) -> ADDRMASK_R { + ADDRMASK_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Address Value"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Bits 16:23 - Address Mask"] + #[inline(always)] + pub fn addrmask(&mut self) -> ADDRMASK_W { + ADDRMASK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [addr](index.html) module"] +pub struct ADDR_SPEC; +impl crate::RegisterSpec for ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [addr::R](R) reader structure"] +impl crate::Readable for ADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [addr::W](W) writer structure"] +impl crate::Writable for ADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ADDR to value 0"] +impl crate::Resettable for ADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/sercom0/spis/baud.rs b/pac/atsamc20n/src/sercom0/spis/baud.rs new file mode 100644 index 000000000000..eeee4cf633e5 --- /dev/null +++ b/pac/atsamc20n/src/sercom0/spis/baud.rs @@ -0,0 +1,103 @@ +#[doc = "Register `BAUD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud](index.html) module"] +pub struct BAUD_SPEC; +impl crate::RegisterSpec for BAUD_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [baud::R](R) reader structure"] +impl crate::Readable for BAUD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud::W](W) writer structure"] +impl crate::Writable for BAUD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD to value 0"] +impl crate::Resettable for BAUD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/sercom0/spis/ctrla.rs b/pac/atsamc20n/src/sercom0/spis/ctrla.rs new file mode 100644 index 000000000000..6151433a8529 --- /dev/null +++ b/pac/atsamc20n/src/sercom0/spis/ctrla.rs @@ -0,0 +1,992 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: USART with external clock"] + USART_EXT_CLK = 0, + #[doc = "1: USART with internal clock"] + USART_INT_CLK = 1, + #[doc = "2: SPI in slave operation"] + SPI_SLAVE = 2, + #[doc = "3: SPI in master operation"] + SPI_MASTER = 3, + #[doc = "4: I2C slave operation"] + I2C_SLAVE = 4, + #[doc = "5: I2C master operation"] + I2C_MASTER = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::USART_EXT_CLK), + 1 => Some(MODE_A::USART_INT_CLK), + 2 => Some(MODE_A::SPI_SLAVE), + 3 => Some(MODE_A::SPI_MASTER), + 4 => Some(MODE_A::I2C_SLAVE), + 5 => Some(MODE_A::I2C_MASTER), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_EXT_CLK`"] + #[inline(always)] + pub fn is_usart_ext_clk(&self) -> bool { + **self == MODE_A::USART_EXT_CLK + } + #[doc = "Checks if the value of the field is `USART_INT_CLK`"] + #[inline(always)] + pub fn is_usart_int_clk(&self) -> bool { + **self == MODE_A::USART_INT_CLK + } + #[doc = "Checks if the value of the field is `SPI_SLAVE`"] + #[inline(always)] + pub fn is_spi_slave(&self) -> bool { + **self == MODE_A::SPI_SLAVE + } + #[doc = "Checks if the value of the field is `SPI_MASTER`"] + #[inline(always)] + pub fn is_spi_master(&self) -> bool { + **self == MODE_A::SPI_MASTER + } + #[doc = "Checks if the value of the field is `I2C_SLAVE`"] + #[inline(always)] + pub fn is_i2c_slave(&self) -> bool { + **self == MODE_A::I2C_SLAVE + } + #[doc = "Checks if the value of the field is `I2C_MASTER`"] + #[inline(always)] + pub fn is_i2c_master(&self) -> bool { + **self == MODE_A::I2C_MASTER + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART with external clock"] + #[inline(always)] + pub fn usart_ext_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_EXT_CLK) + } + #[doc = "USART with internal clock"] + #[inline(always)] + pub fn usart_int_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_INT_CLK) + } + #[doc = "SPI in slave operation"] + #[inline(always)] + pub fn spi_slave(self) -> &'a mut W { + self.variant(MODE_A::SPI_SLAVE) + } + #[doc = "SPI in master operation"] + #[inline(always)] + pub fn spi_master(self) -> &'a mut W { + self.variant(MODE_A::SPI_MASTER) + } + #[doc = "I2C slave operation"] + #[inline(always)] + pub fn i2c_slave(self) -> &'a mut W { + self.variant(MODE_A::I2C_SLAVE) + } + #[doc = "I2C master operation"] + #[inline(always)] + pub fn i2c_master(self) -> &'a mut W { + self.variant(MODE_A::I2C_MASTER) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 2)) | ((value as u32 & 0x07) << 2); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `IBON` reader - Immediate Buffer Overflow Notification"] +pub struct IBON_R(crate::FieldReader); +impl IBON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IBON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IBON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IBON` writer - Immediate Buffer Overflow Notification"] +pub struct IBON_W<'a> { + w: &'a mut W, +} +impl<'a> IBON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Data Out Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DOPO_A { + #[doc = "0: DO on PAD\\[0\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + PAD0 = 0, + #[doc = "1: DO on PAD\\[2\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + PAD1 = 1, + #[doc = "2: DO on PAD\\[3\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + PAD2 = 2, + #[doc = "3: DO on PAD\\[0\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + PAD3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DOPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `DOPO` reader - Data Out Pinout"] +pub struct DOPO_R(crate::FieldReader); +impl DOPO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DOPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DOPO_A { + match self.bits { + 0 => DOPO_A::PAD0, + 1 => DOPO_A::PAD1, + 2 => DOPO_A::PAD2, + 3 => DOPO_A::PAD3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == DOPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD1`"] + #[inline(always)] + pub fn is_pad1(&self) -> bool { + **self == DOPO_A::PAD1 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == DOPO_A::PAD2 + } + #[doc = "Checks if the value of the field is `PAD3`"] + #[inline(always)] + pub fn is_pad3(&self) -> bool { + **self == DOPO_A::PAD3 + } +} +impl core::ops::Deref for DOPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DOPO` writer - Data Out Pinout"] +pub struct DOPO_W<'a> { + w: &'a mut W, +} +impl<'a> DOPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DOPO_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "DO on PAD\\[0\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(DOPO_A::PAD0) + } + #[doc = "DO on PAD\\[2\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + #[inline(always)] + pub fn pad1(self) -> &'a mut W { + self.variant(DOPO_A::PAD1) + } + #[doc = "DO on PAD\\[3\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(DOPO_A::PAD2) + } + #[doc = "DO on PAD\\[0\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + #[inline(always)] + pub fn pad3(self) -> &'a mut W { + self.variant(DOPO_A::PAD3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Data In Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DIPO_A { + #[doc = "0: SERCOM PAD\\[0\\]"] + PAD0 = 0, + #[doc = "1: SERCOM PAD\\[1\\]"] + PAD1 = 1, + #[doc = "2: SERCOM PAD\\[2\\]"] + PAD2 = 2, + #[doc = "3: SERCOM PAD\\[3\\]"] + PAD3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DIPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `DIPO` reader - Data In Pinout"] +pub struct DIPO_R(crate::FieldReader); +impl DIPO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DIPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DIPO_A { + match self.bits { + 0 => DIPO_A::PAD0, + 1 => DIPO_A::PAD1, + 2 => DIPO_A::PAD2, + 3 => DIPO_A::PAD3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == DIPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD1`"] + #[inline(always)] + pub fn is_pad1(&self) -> bool { + **self == DIPO_A::PAD1 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == DIPO_A::PAD2 + } + #[doc = "Checks if the value of the field is `PAD3`"] + #[inline(always)] + pub fn is_pad3(&self) -> bool { + **self == DIPO_A::PAD3 + } +} +impl core::ops::Deref for DIPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIPO` writer - Data In Pinout"] +pub struct DIPO_W<'a> { + w: &'a mut W, +} +impl<'a> DIPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DIPO_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "SERCOM PAD\\[0\\]"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(DIPO_A::PAD0) + } + #[doc = "SERCOM PAD\\[1\\]"] + #[inline(always)] + pub fn pad1(self) -> &'a mut W { + self.variant(DIPO_A::PAD1) + } + #[doc = "SERCOM PAD\\[2\\]"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(DIPO_A::PAD2) + } + #[doc = "SERCOM PAD\\[3\\]"] + #[inline(always)] + pub fn pad3(self) -> &'a mut W { + self.variant(DIPO_A::PAD3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 20)) | ((value as u32 & 0x03) << 20); + self.w + } +} +#[doc = "Frame Format\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FORM_A { + #[doc = "0: SPI Frame"] + SPI_FRAME = 0, + #[doc = "2: SPI Frame with Addr"] + SPI_FRAME_WITH_ADDR = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FORM_A) -> Self { + variant as _ + } +} +#[doc = "Field `FORM` reader - Frame Format"] +pub struct FORM_R(crate::FieldReader); +impl FORM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FORM_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(FORM_A::SPI_FRAME), + 2 => Some(FORM_A::SPI_FRAME_WITH_ADDR), + _ => None, + } + } + #[doc = "Checks if the value of the field is `SPI_FRAME`"] + #[inline(always)] + pub fn is_spi_frame(&self) -> bool { + **self == FORM_A::SPI_FRAME + } + #[doc = "Checks if the value of the field is `SPI_FRAME_WITH_ADDR`"] + #[inline(always)] + pub fn is_spi_frame_with_addr(&self) -> bool { + **self == FORM_A::SPI_FRAME_WITH_ADDR + } +} +impl core::ops::Deref for FORM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FORM` writer - Frame Format"] +pub struct FORM_W<'a> { + w: &'a mut W, +} +impl<'a> FORM_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FORM_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "SPI Frame"] + #[inline(always)] + pub fn spi_frame(self) -> &'a mut W { + self.variant(FORM_A::SPI_FRAME) + } + #[doc = "SPI Frame with Addr"] + #[inline(always)] + pub fn spi_frame_with_addr(self) -> &'a mut W { + self.variant(FORM_A::SPI_FRAME_WITH_ADDR) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Clock Phase\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CPHA_A { + #[doc = "0: The data is sampled on a leading SCK edge and changed on a trailing SCK edge"] + LEADING_EDGE = 0, + #[doc = "1: The data is sampled on a trailing SCK edge and changed on a leading SCK edge"] + TRAILING_EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CPHA_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CPHA` reader - Clock Phase"] +pub struct CPHA_R(crate::FieldReader); +impl CPHA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPHA_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CPHA_A { + match self.bits { + false => CPHA_A::LEADING_EDGE, + true => CPHA_A::TRAILING_EDGE, + } + } + #[doc = "Checks if the value of the field is `LEADING_EDGE`"] + #[inline(always)] + pub fn is_leading_edge(&self) -> bool { + **self == CPHA_A::LEADING_EDGE + } + #[doc = "Checks if the value of the field is `TRAILING_EDGE`"] + #[inline(always)] + pub fn is_trailing_edge(&self) -> bool { + **self == CPHA_A::TRAILING_EDGE + } +} +impl core::ops::Deref for CPHA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPHA` writer - Clock Phase"] +pub struct CPHA_W<'a> { + w: &'a mut W, +} +impl<'a> CPHA_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CPHA_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "The data is sampled on a leading SCK edge and changed on a trailing SCK edge"] + #[inline(always)] + pub fn leading_edge(self) -> &'a mut W { + self.variant(CPHA_A::LEADING_EDGE) + } + #[doc = "The data is sampled on a trailing SCK edge and changed on a leading SCK edge"] + #[inline(always)] + pub fn trailing_edge(self) -> &'a mut W { + self.variant(CPHA_A::TRAILING_EDGE) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Clock Polarity\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CPOL_A { + #[doc = "0: SCK is low when idle"] + IDLE_LOW = 0, + #[doc = "1: SCK is high when idle"] + IDLE_HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CPOL_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CPOL` reader - Clock Polarity"] +pub struct CPOL_R(crate::FieldReader); +impl CPOL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPOL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CPOL_A { + match self.bits { + false => CPOL_A::IDLE_LOW, + true => CPOL_A::IDLE_HIGH, + } + } + #[doc = "Checks if the value of the field is `IDLE_LOW`"] + #[inline(always)] + pub fn is_idle_low(&self) -> bool { + **self == CPOL_A::IDLE_LOW + } + #[doc = "Checks if the value of the field is `IDLE_HIGH`"] + #[inline(always)] + pub fn is_idle_high(&self) -> bool { + **self == CPOL_A::IDLE_HIGH + } +} +impl core::ops::Deref for CPOL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPOL` writer - Clock Polarity"] +pub struct CPOL_W<'a> { + w: &'a mut W, +} +impl<'a> CPOL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CPOL_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "SCK is low when idle"] + #[inline(always)] + pub fn idle_low(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_LOW) + } + #[doc = "SCK is high when idle"] + #[inline(always)] + pub fn idle_high(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_HIGH) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29); + self.w + } +} +#[doc = "Data Order\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum DORD_A { + #[doc = "0: MSB is transferred first"] + MSB = 0, + #[doc = "1: LSB is transferred first"] + LSB = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DORD_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DORD` reader - Data Order"] +pub struct DORD_R(crate::FieldReader); +impl DORD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DORD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DORD_A { + match self.bits { + false => DORD_A::MSB, + true => DORD_A::LSB, + } + } + #[doc = "Checks if the value of the field is `MSB`"] + #[inline(always)] + pub fn is_msb(&self) -> bool { + **self == DORD_A::MSB + } + #[doc = "Checks if the value of the field is `LSB`"] + #[inline(always)] + pub fn is_lsb(&self) -> bool { + **self == DORD_A::LSB + } +} +impl core::ops::Deref for DORD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DORD` writer - Data Order"] +pub struct DORD_W<'a> { + w: &'a mut W, +} +impl<'a> DORD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DORD_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "MSB is transferred first"] + #[inline(always)] + pub fn msb(self) -> &'a mut W { + self.variant(DORD_A::MSB) + } + #[doc = "LSB is transferred first"] + #[inline(always)] + pub fn lsb(self) -> &'a mut W { + self.variant(DORD_A::LSB) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x07) as u8) + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&self) -> IBON_R { + IBON_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bits 16:17 - Data Out Pinout"] + #[inline(always)] + pub fn dopo(&self) -> DOPO_R { + DOPO_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bits 20:21 - Data In Pinout"] + #[inline(always)] + pub fn dipo(&self) -> DIPO_R { + DIPO_R::new(((self.bits >> 20) & 0x03) as u8) + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&self) -> FORM_R { + FORM_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 28 - Clock Phase"] + #[inline(always)] + pub fn cpha(&self) -> CPHA_R { + CPHA_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&self) -> CPOL_R { + CPOL_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&self) -> DORD_R { + DORD_R::new(((self.bits >> 30) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&mut self) -> IBON_W { + IBON_W { w: self } + } + #[doc = "Bits 16:17 - Data Out Pinout"] + #[inline(always)] + pub fn dopo(&mut self) -> DOPO_W { + DOPO_W { w: self } + } + #[doc = "Bits 20:21 - Data In Pinout"] + #[inline(always)] + pub fn dipo(&mut self) -> DIPO_W { + DIPO_W { w: self } + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&mut self) -> FORM_W { + FORM_W { w: self } + } + #[doc = "Bit 28 - Clock Phase"] + #[inline(always)] + pub fn cpha(&mut self) -> CPHA_W { + CPHA_W { w: self } + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&mut self) -> CPOL_W { + CPOL_W { w: self } + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&mut self) -> DORD_W { + DORD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/sercom0/spis/ctrlb.rs b/pac/atsamc20n/src/sercom0/spis/ctrlb.rs new file mode 100644 index 000000000000..ccb70582cf34 --- /dev/null +++ b/pac/atsamc20n/src/sercom0/spis/ctrlb.rs @@ -0,0 +1,439 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Character Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CHSIZE_A { + #[doc = "0: 8 bits"] + _8_BIT = 0, + #[doc = "1: 9 bits"] + _9_BIT = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CHSIZE_A) -> Self { + variant as _ + } +} +#[doc = "Field `CHSIZE` reader - Character Size"] +pub struct CHSIZE_R(crate::FieldReader); +impl CHSIZE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CHSIZE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CHSIZE_A::_8_BIT), + 1 => Some(CHSIZE_A::_9_BIT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_8_BIT`"] + #[inline(always)] + pub fn is_8_bit(&self) -> bool { + **self == CHSIZE_A::_8_BIT + } + #[doc = "Checks if the value of the field is `_9_BIT`"] + #[inline(always)] + pub fn is_9_bit(&self) -> bool { + **self == CHSIZE_A::_9_BIT + } +} +impl core::ops::Deref for CHSIZE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHSIZE` writer - Character Size"] +pub struct CHSIZE_W<'a> { + w: &'a mut W, +} +impl<'a> CHSIZE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CHSIZE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8 bits"] + #[inline(always)] + pub fn _8_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_8_BIT) + } + #[doc = "9 bits"] + #[inline(always)] + pub fn _9_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_9_BIT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Field `PLOADEN` reader - Data Preload Enable"] +pub struct PLOADEN_R(crate::FieldReader); +impl PLOADEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PLOADEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PLOADEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PLOADEN` writer - Data Preload Enable"] +pub struct PLOADEN_W<'a> { + w: &'a mut W, +} +impl<'a> PLOADEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `SSDE` reader - Slave Select Low Detect Enable"] +pub struct SSDE_R(crate::FieldReader); +impl SSDE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SSDE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSDE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSDE` writer - Slave Select Low Detect Enable"] +pub struct SSDE_W<'a> { + w: &'a mut W, +} +impl<'a> SSDE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `MSSEN` reader - Master Slave Select Enable"] +pub struct MSSEN_R(crate::FieldReader); +impl MSSEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MSSEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MSSEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MSSEN` writer - Master Slave Select Enable"] +pub struct MSSEN_W<'a> { + w: &'a mut W, +} +impl<'a> MSSEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Address Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum AMODE_A { + #[doc = "0: SPI Address mask"] + MASK = 0, + #[doc = "1: Two unique Addressess"] + _2_ADDRESSES = 1, + #[doc = "2: Address Range"] + RANGE = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: AMODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `AMODE` reader - Address Mode"] +pub struct AMODE_R(crate::FieldReader); +impl AMODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + AMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(AMODE_A::MASK), + 1 => Some(AMODE_A::_2_ADDRESSES), + 2 => Some(AMODE_A::RANGE), + _ => None, + } + } + #[doc = "Checks if the value of the field is `MASK`"] + #[inline(always)] + pub fn is_mask(&self) -> bool { + **self == AMODE_A::MASK + } + #[doc = "Checks if the value of the field is `_2_ADDRESSES`"] + #[inline(always)] + pub fn is_2_addresses(&self) -> bool { + **self == AMODE_A::_2_ADDRESSES + } + #[doc = "Checks if the value of the field is `RANGE`"] + #[inline(always)] + pub fn is_range(&self) -> bool { + **self == AMODE_A::RANGE + } +} +impl core::ops::Deref for AMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AMODE` writer - Address Mode"] +pub struct AMODE_W<'a> { + w: &'a mut W, +} +impl<'a> AMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: AMODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "SPI Address mask"] + #[inline(always)] + pub fn mask(self) -> &'a mut W { + self.variant(AMODE_A::MASK) + } + #[doc = "Two unique Addressess"] + #[inline(always)] + pub fn _2_addresses(self) -> &'a mut W { + self.variant(AMODE_A::_2_ADDRESSES) + } + #[doc = "Address Range"] + #[inline(always)] + pub fn range(self) -> &'a mut W { + self.variant(AMODE_A::RANGE) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 14)) | ((value as u32 & 0x03) << 14); + self.w + } +} +#[doc = "Field `RXEN` reader - Receiver Enable"] +pub struct RXEN_R(crate::FieldReader); +impl RXEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXEN` writer - Receiver Enable"] +pub struct RXEN_W<'a> { + w: &'a mut W, +} +impl<'a> RXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&self) -> CHSIZE_R { + CHSIZE_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 6 - Data Preload Enable"] + #[inline(always)] + pub fn ploaden(&self) -> PLOADEN_R { + PLOADEN_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 9 - Slave Select Low Detect Enable"] + #[inline(always)] + pub fn ssde(&self) -> SSDE_R { + SSDE_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 13 - Master Slave Select Enable"] + #[inline(always)] + pub fn mssen(&self) -> MSSEN_R { + MSSEN_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bits 14:15 - Address Mode"] + #[inline(always)] + pub fn amode(&self) -> AMODE_R { + AMODE_R::new(((self.bits >> 14) & 0x03) as u8) + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&self) -> RXEN_R { + RXEN_R::new(((self.bits >> 17) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&mut self) -> CHSIZE_W { + CHSIZE_W { w: self } + } + #[doc = "Bit 6 - Data Preload Enable"] + #[inline(always)] + pub fn ploaden(&mut self) -> PLOADEN_W { + PLOADEN_W { w: self } + } + #[doc = "Bit 9 - Slave Select Low Detect Enable"] + #[inline(always)] + pub fn ssde(&mut self) -> SSDE_W { + SSDE_W { w: self } + } + #[doc = "Bit 13 - Master Slave Select Enable"] + #[inline(always)] + pub fn mssen(&mut self) -> MSSEN_W { + MSSEN_W { w: self } + } + #[doc = "Bits 14:15 - Address Mode"] + #[inline(always)] + pub fn amode(&mut self) -> AMODE_W { + AMODE_W { w: self } + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&mut self) -> RXEN_W { + RXEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/sercom0/spis/data.rs b/pac/atsamc20n/src/sercom0/spis/data.rs new file mode 100644 index 000000000000..4edf8089b29f --- /dev/null +++ b/pac/atsamc20n/src/sercom0/spis/data.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data Value"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data Value"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01ff) | (value as u32 & 0x01ff); + self.w + } +} +impl R { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new((self.bits & 0x01ff) as u16) + } +} +impl W { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/sercom0/spis/dbgctrl.rs b/pac/atsamc20n/src/sercom0/spis/dbgctrl.rs new file mode 100644 index 000000000000..ec36bbd26057 --- /dev/null +++ b/pac/atsamc20n/src/sercom0/spis/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGSTOP` reader - Debug Mode"] +pub struct DBGSTOP_R(crate::FieldReader); +impl DBGSTOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGSTOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGSTOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGSTOP` writer - Debug Mode"] +pub struct DBGSTOP_W<'a> { + w: &'a mut W, +} +impl<'a> DBGSTOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&self) -> DBGSTOP_R { + DBGSTOP_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&mut self) -> DBGSTOP_W { + DBGSTOP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/sercom0/spis/intenclr.rs b/pac/atsamc20n/src/sercom0/spis/intenclr.rs new file mode 100644 index 000000000000..e4c9ee0d506d --- /dev/null +++ b/pac/atsamc20n/src/sercom0/spis/intenclr.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Disable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Disable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Disable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Disable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Disable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Disable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SSL` reader - Slave Select Low Interrupt Disable"] +pub struct SSL_R(crate::FieldReader); +impl SSL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SSL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSL` writer - Slave Select Low Interrupt Disable"] +pub struct SSL_W<'a> { + w: &'a mut W, +} +impl<'a> SSL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Disable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Disable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Slave Select Low Interrupt Disable"] + #[inline(always)] + pub fn ssl(&self) -> SSL_R { + SSL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Slave Select Low Interrupt Disable"] + #[inline(always)] + pub fn ssl(&mut self) -> SSL_W { + SSL_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/sercom0/spis/intenset.rs b/pac/atsamc20n/src/sercom0/spis/intenset.rs new file mode 100644 index 000000000000..99582a624ebc --- /dev/null +++ b/pac/atsamc20n/src/sercom0/spis/intenset.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Enable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Enable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Enable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Enable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Enable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Enable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SSL` reader - Slave Select Low Interrupt Enable"] +pub struct SSL_R(crate::FieldReader); +impl SSL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SSL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSL` writer - Slave Select Low Interrupt Enable"] +pub struct SSL_W<'a> { + w: &'a mut W, +} +impl<'a> SSL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Slave Select Low Interrupt Enable"] + #[inline(always)] + pub fn ssl(&self) -> SSL_R { + SSL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Slave Select Low Interrupt Enable"] + #[inline(always)] + pub fn ssl(&mut self) -> SSL_W { + SSL_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/sercom0/spis/intflag.rs b/pac/atsamc20n/src/sercom0/spis/intflag.rs new file mode 100644 index 000000000000..589e73c2329f --- /dev/null +++ b/pac/atsamc20n/src/sercom0/spis/intflag.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SSL` reader - Slave Select Low Interrupt Flag"] +pub struct SSL_R(crate::FieldReader); +impl SSL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SSL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSL` writer - Slave Select Low Interrupt Flag"] +pub struct SSL_W<'a> { + w: &'a mut W, +} +impl<'a> SSL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Slave Select Low Interrupt Flag"] + #[inline(always)] + pub fn ssl(&self) -> SSL_R { + SSL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Slave Select Low Interrupt Flag"] + #[inline(always)] + pub fn ssl(&mut self) -> SSL_W { + SSL_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/sercom0/spis/status.rs b/pac/atsamc20n/src/sercom0/spis/status.rs new file mode 100644 index 000000000000..55c39c1a709f --- /dev/null +++ b/pac/atsamc20n/src/sercom0/spis/status.rs @@ -0,0 +1,113 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BUFOVF` reader - Buffer Overflow"] +pub struct BUFOVF_R(crate::FieldReader); +impl BUFOVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUFOVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUFOVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUFOVF` writer - Buffer Overflow"] +pub struct BUFOVF_W<'a> { + w: &'a mut W, +} +impl<'a> BUFOVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&self) -> BUFOVF_R { + BUFOVF_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&mut self) -> BUFOVF_W { + BUFOVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/sercom0/spis/syncbusy.rs b/pac/atsamc20n/src/sercom0/spis/syncbusy.rs new file mode 100644 index 000000000000..ac2f2e2c27ec --- /dev/null +++ b/pac/atsamc20n/src/sercom0/spis/syncbusy.rs @@ -0,0 +1,93 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - SERCOM Enable Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLB` reader - CTRLB Synchronization Busy"] +pub struct CTRLB_R(crate::FieldReader); +impl CTRLB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM Enable Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - CTRLB Synchronization Busy"] + #[inline(always)] + pub fn ctrlb(&self) -> CTRLB_R { + CTRLB_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +#[doc = "SPIS Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/sercom0/usart_ext.rs b/pac/atsamc20n/src/sercom0/usart_ext.rs new file mode 100644 index 000000000000..8c08b9efc1d5 --- /dev/null +++ b/pac/atsamc20n/src/sercom0/usart_ext.rs @@ -0,0 +1,60 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "USART_EXT Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "USART_EXT Control B"] +pub mod ctrlb; +#[doc = "CTRLC register accessor: an alias for `Reg`"] +pub type CTRLC = crate::Reg; +#[doc = "USART_EXT Control C"] +pub mod ctrlc; +#[doc = "BAUD register accessor: an alias for `Reg`"] +pub type BAUD = crate::Reg; +#[doc = "USART_EXT Baud Rate"] +pub mod baud; +#[doc = "BAUD_FRAC_MODE register accessor: an alias for `Reg`"] +pub type BAUD_FRAC_MODE = crate::Reg; +#[doc = "USART_EXT Baud Rate"] +pub mod baud_frac_mode; +#[doc = "BAUD_FRACFP_MODE register accessor: an alias for `Reg`"] +pub type BAUD_FRACFP_MODE = crate::Reg; +#[doc = "USART_EXT Baud Rate"] +pub mod baud_fracfp_mode; +#[doc = "BAUD_USARTFP_MODE register accessor: an alias for `Reg`"] +pub type BAUD_USARTFP_MODE = crate::Reg; +#[doc = "USART_EXT Baud Rate"] +pub mod baud_usartfp_mode; +#[doc = "RXPL register accessor: an alias for `Reg`"] +pub type RXPL = crate::Reg; +#[doc = "USART_EXT Receive Pulse Length"] +pub mod rxpl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "USART_EXT Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "USART_EXT Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "USART_EXT Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "USART_EXT Status"] +pub mod status; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "USART_EXT Synchronization Busy"] +pub mod syncbusy; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "USART_EXT Data"] +pub mod data; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "USART_EXT Debug Control"] +pub mod dbgctrl; diff --git a/pac/atsamc20n/src/sercom0/usart_ext/baud.rs b/pac/atsamc20n/src/sercom0/usart_ext/baud.rs new file mode 100644 index 000000000000..9558a8e1a52d --- /dev/null +++ b/pac/atsamc20n/src/sercom0/usart_ext/baud.rs @@ -0,0 +1,103 @@ +#[doc = "Register `BAUD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud](index.html) module"] +pub struct BAUD_SPEC; +impl crate::RegisterSpec for BAUD_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud::R](R) reader structure"] +impl crate::Readable for BAUD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud::W](W) writer structure"] +impl crate::Writable for BAUD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD to value 0"] +impl crate::Resettable for BAUD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/sercom0/usart_ext/baud_frac_mode.rs b/pac/atsamc20n/src/sercom0/usart_ext/baud_frac_mode.rs new file mode 100644 index 000000000000..d7cdd4570e26 --- /dev/null +++ b/pac/atsamc20n/src/sercom0/usart_ext/baud_frac_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `BAUD_FRAC_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD_FRAC_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1fff) | (value as u16 & 0x1fff); + self.w + } +} +#[doc = "Field `FP` reader - Fractional Part"] +pub struct FP_R(crate::FieldReader); +impl FP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FP` writer - Fractional Part"] +pub struct FP_W<'a> { + w: &'a mut W, +} +impl<'a> FP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 13)) | ((value as u16 & 0x07) << 13); + self.w + } +} +impl R { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new((self.bits & 0x1fff) as u16) + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&self) -> FP_R { + FP_R::new(((self.bits >> 13) & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&mut self) -> FP_W { + FP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud_frac_mode](index.html) module"] +pub struct BAUD_FRAC_MODE_SPEC; +impl crate::RegisterSpec for BAUD_FRAC_MODE_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud_frac_mode::R](R) reader structure"] +impl crate::Readable for BAUD_FRAC_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud_frac_mode::W](W) writer structure"] +impl crate::Writable for BAUD_FRAC_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD_FRAC_MODE to value 0"] +impl crate::Resettable for BAUD_FRAC_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/sercom0/usart_ext/baud_fracfp_mode.rs b/pac/atsamc20n/src/sercom0/usart_ext/baud_fracfp_mode.rs new file mode 100644 index 000000000000..c1dc50807677 --- /dev/null +++ b/pac/atsamc20n/src/sercom0/usart_ext/baud_fracfp_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `BAUD_FRACFP_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD_FRACFP_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1fff) | (value as u16 & 0x1fff); + self.w + } +} +#[doc = "Field `FP` reader - Fractional Part"] +pub struct FP_R(crate::FieldReader); +impl FP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FP` writer - Fractional Part"] +pub struct FP_W<'a> { + w: &'a mut W, +} +impl<'a> FP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 13)) | ((value as u16 & 0x07) << 13); + self.w + } +} +impl R { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new((self.bits & 0x1fff) as u16) + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&self) -> FP_R { + FP_R::new(((self.bits >> 13) & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&mut self) -> FP_W { + FP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud_fracfp_mode](index.html) module"] +pub struct BAUD_FRACFP_MODE_SPEC; +impl crate::RegisterSpec for BAUD_FRACFP_MODE_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud_fracfp_mode::R](R) reader structure"] +impl crate::Readable for BAUD_FRACFP_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud_fracfp_mode::W](W) writer structure"] +impl crate::Writable for BAUD_FRACFP_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD_FRACFP_MODE to value 0"] +impl crate::Resettable for BAUD_FRACFP_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/sercom0/usart_ext/baud_usartfp_mode.rs b/pac/atsamc20n/src/sercom0/usart_ext/baud_usartfp_mode.rs new file mode 100644 index 000000000000..8d4db16e0245 --- /dev/null +++ b/pac/atsamc20n/src/sercom0/usart_ext/baud_usartfp_mode.rs @@ -0,0 +1,103 @@ +#[doc = "Register `BAUD_USARTFP_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD_USARTFP_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud_usartfp_mode](index.html) module"] +pub struct BAUD_USARTFP_MODE_SPEC; +impl crate::RegisterSpec for BAUD_USARTFP_MODE_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud_usartfp_mode::R](R) reader structure"] +impl crate::Readable for BAUD_USARTFP_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud_usartfp_mode::W](W) writer structure"] +impl crate::Writable for BAUD_USARTFP_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD_USARTFP_MODE to value 0"] +impl crate::Resettable for BAUD_USARTFP_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/sercom0/usart_ext/ctrla.rs b/pac/atsamc20n/src/sercom0/usart_ext/ctrla.rs new file mode 100644 index 000000000000..535875ac8b25 --- /dev/null +++ b/pac/atsamc20n/src/sercom0/usart_ext/ctrla.rs @@ -0,0 +1,1171 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: USART with external clock"] + USART_EXT_CLK = 0, + #[doc = "1: USART with internal clock"] + USART_INT_CLK = 1, + #[doc = "2: SPI in slave operation"] + SPI_SLAVE = 2, + #[doc = "3: SPI in master operation"] + SPI_MASTER = 3, + #[doc = "4: I2C slave operation"] + I2C_SLAVE = 4, + #[doc = "5: I2C master operation"] + I2C_MASTER = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::USART_EXT_CLK), + 1 => Some(MODE_A::USART_INT_CLK), + 2 => Some(MODE_A::SPI_SLAVE), + 3 => Some(MODE_A::SPI_MASTER), + 4 => Some(MODE_A::I2C_SLAVE), + 5 => Some(MODE_A::I2C_MASTER), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_EXT_CLK`"] + #[inline(always)] + pub fn is_usart_ext_clk(&self) -> bool { + **self == MODE_A::USART_EXT_CLK + } + #[doc = "Checks if the value of the field is `USART_INT_CLK`"] + #[inline(always)] + pub fn is_usart_int_clk(&self) -> bool { + **self == MODE_A::USART_INT_CLK + } + #[doc = "Checks if the value of the field is `SPI_SLAVE`"] + #[inline(always)] + pub fn is_spi_slave(&self) -> bool { + **self == MODE_A::SPI_SLAVE + } + #[doc = "Checks if the value of the field is `SPI_MASTER`"] + #[inline(always)] + pub fn is_spi_master(&self) -> bool { + **self == MODE_A::SPI_MASTER + } + #[doc = "Checks if the value of the field is `I2C_SLAVE`"] + #[inline(always)] + pub fn is_i2c_slave(&self) -> bool { + **self == MODE_A::I2C_SLAVE + } + #[doc = "Checks if the value of the field is `I2C_MASTER`"] + #[inline(always)] + pub fn is_i2c_master(&self) -> bool { + **self == MODE_A::I2C_MASTER + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART with external clock"] + #[inline(always)] + pub fn usart_ext_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_EXT_CLK) + } + #[doc = "USART with internal clock"] + #[inline(always)] + pub fn usart_int_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_INT_CLK) + } + #[doc = "SPI in slave operation"] + #[inline(always)] + pub fn spi_slave(self) -> &'a mut W { + self.variant(MODE_A::SPI_SLAVE) + } + #[doc = "SPI in master operation"] + #[inline(always)] + pub fn spi_master(self) -> &'a mut W { + self.variant(MODE_A::SPI_MASTER) + } + #[doc = "I2C slave operation"] + #[inline(always)] + pub fn i2c_slave(self) -> &'a mut W { + self.variant(MODE_A::I2C_SLAVE) + } + #[doc = "I2C master operation"] + #[inline(always)] + pub fn i2c_master(self) -> &'a mut W { + self.variant(MODE_A::I2C_MASTER) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 2)) | ((value as u32 & 0x07) << 2); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `IBON` reader - Immediate Buffer Overflow Notification"] +pub struct IBON_R(crate::FieldReader); +impl IBON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IBON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IBON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IBON` writer - Immediate Buffer Overflow Notification"] +pub struct IBON_W<'a> { + w: &'a mut W, +} +impl<'a> IBON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Sample\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SAMPR_A { + #[doc = "0: 16x over-sampling using arithmetic baudrate generation"] + _16X_ARITHMETIC = 0, + #[doc = "1: 16x over-sampling using fractional baudrate generation"] + _16X_FRACTIONAL = 1, + #[doc = "2: 8x over-sampling using arithmetic baudrate generation"] + _8X_ARITHMETIC = 2, + #[doc = "3: 8x over-sampling using fractional baudrate generation"] + _8X_FRACTIONAL = 3, + #[doc = "4: 3x over-sampling using arithmetic baudrate generation"] + _3X_ARITHMETIC = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SAMPR_A) -> Self { + variant as _ + } +} +#[doc = "Field `SAMPR` reader - Sample"] +pub struct SAMPR_R(crate::FieldReader); +impl SAMPR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SAMPR_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SAMPR_A::_16X_ARITHMETIC), + 1 => Some(SAMPR_A::_16X_FRACTIONAL), + 2 => Some(SAMPR_A::_8X_ARITHMETIC), + 3 => Some(SAMPR_A::_8X_FRACTIONAL), + 4 => Some(SAMPR_A::_3X_ARITHMETIC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_16X_ARITHMETIC`"] + #[inline(always)] + pub fn is_16x_arithmetic(&self) -> bool { + **self == SAMPR_A::_16X_ARITHMETIC + } + #[doc = "Checks if the value of the field is `_16X_FRACTIONAL`"] + #[inline(always)] + pub fn is_16x_fractional(&self) -> bool { + **self == SAMPR_A::_16X_FRACTIONAL + } + #[doc = "Checks if the value of the field is `_8X_ARITHMETIC`"] + #[inline(always)] + pub fn is_8x_arithmetic(&self) -> bool { + **self == SAMPR_A::_8X_ARITHMETIC + } + #[doc = "Checks if the value of the field is `_8X_FRACTIONAL`"] + #[inline(always)] + pub fn is_8x_fractional(&self) -> bool { + **self == SAMPR_A::_8X_FRACTIONAL + } + #[doc = "Checks if the value of the field is `_3X_ARITHMETIC`"] + #[inline(always)] + pub fn is_3x_arithmetic(&self) -> bool { + **self == SAMPR_A::_3X_ARITHMETIC + } +} +impl core::ops::Deref for SAMPR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SAMPR` writer - Sample"] +pub struct SAMPR_W<'a> { + w: &'a mut W, +} +impl<'a> SAMPR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SAMPR_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "16x over-sampling using arithmetic baudrate generation"] + #[inline(always)] + pub fn _16x_arithmetic(self) -> &'a mut W { + self.variant(SAMPR_A::_16X_ARITHMETIC) + } + #[doc = "16x over-sampling using fractional baudrate generation"] + #[inline(always)] + pub fn _16x_fractional(self) -> &'a mut W { + self.variant(SAMPR_A::_16X_FRACTIONAL) + } + #[doc = "8x over-sampling using arithmetic baudrate generation"] + #[inline(always)] + pub fn _8x_arithmetic(self) -> &'a mut W { + self.variant(SAMPR_A::_8X_ARITHMETIC) + } + #[doc = "8x over-sampling using fractional baudrate generation"] + #[inline(always)] + pub fn _8x_fractional(self) -> &'a mut W { + self.variant(SAMPR_A::_8X_FRACTIONAL) + } + #[doc = "3x over-sampling using arithmetic baudrate generation"] + #[inline(always)] + pub fn _3x_arithmetic(self) -> &'a mut W { + self.variant(SAMPR_A::_3X_ARITHMETIC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 13)) | ((value as u32 & 0x07) << 13); + self.w + } +} +#[doc = "Transmit Data Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum TXPO_A { + #[doc = "0: SERCOM PAD\\[0\\] +is used for data transmission"] + PAD0 = 0, + #[doc = "1: SERCOM PAD\\[2\\] +is used for data transmission"] + PAD2 = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: TXPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `TXPO` reader - Transmit Data Pinout"] +pub struct TXPO_R(crate::FieldReader); +impl TXPO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TXPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(TXPO_A::PAD0), + 1 => Some(TXPO_A::PAD2), + _ => None, + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == TXPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == TXPO_A::PAD2 + } +} +impl core::ops::Deref for TXPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXPO` writer - Transmit Data Pinout"] +pub struct TXPO_W<'a> { + w: &'a mut W, +} +impl<'a> TXPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TXPO_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "SERCOM PAD\\[0\\] +is used for data transmission"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(TXPO_A::PAD0) + } + #[doc = "SERCOM PAD\\[2\\] +is used for data transmission"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(TXPO_A::PAD2) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Receive Data Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum RXPO_A { + #[doc = "0: SERCOM PAD\\[0\\] +is used for data reception"] + PAD0 = 0, + #[doc = "1: SERCOM PAD\\[1\\] +is used for data reception"] + PAD1 = 1, + #[doc = "2: SERCOM PAD\\[2\\] +is used for data reception"] + PAD2 = 2, + #[doc = "3: SERCOM PAD\\[3\\] +is used for data reception"] + PAD3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RXPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `RXPO` reader - Receive Data Pinout"] +pub struct RXPO_R(crate::FieldReader); +impl RXPO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RXPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RXPO_A { + match self.bits { + 0 => RXPO_A::PAD0, + 1 => RXPO_A::PAD1, + 2 => RXPO_A::PAD2, + 3 => RXPO_A::PAD3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == RXPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD1`"] + #[inline(always)] + pub fn is_pad1(&self) -> bool { + **self == RXPO_A::PAD1 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == RXPO_A::PAD2 + } + #[doc = "Checks if the value of the field is `PAD3`"] + #[inline(always)] + pub fn is_pad3(&self) -> bool { + **self == RXPO_A::PAD3 + } +} +impl core::ops::Deref for RXPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXPO` writer - Receive Data Pinout"] +pub struct RXPO_W<'a> { + w: &'a mut W, +} +impl<'a> RXPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RXPO_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "SERCOM PAD\\[0\\] +is used for data reception"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(RXPO_A::PAD0) + } + #[doc = "SERCOM PAD\\[1\\] +is used for data reception"] + #[inline(always)] + pub fn pad1(self) -> &'a mut W { + self.variant(RXPO_A::PAD1) + } + #[doc = "SERCOM PAD\\[2\\] +is used for data reception"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(RXPO_A::PAD2) + } + #[doc = "SERCOM PAD\\[3\\] +is used for data reception"] + #[inline(always)] + pub fn pad3(self) -> &'a mut W { + self.variant(RXPO_A::PAD3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 20)) | ((value as u32 & 0x03) << 20); + self.w + } +} +#[doc = "Field `SAMPA` reader - Sample Adjustment"] +pub struct SAMPA_R(crate::FieldReader); +impl SAMPA_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SAMPA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SAMPA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SAMPA` writer - Sample Adjustment"] +pub struct SAMPA_W<'a> { + w: &'a mut W, +} +impl<'a> SAMPA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 22)) | ((value as u32 & 0x03) << 22); + self.w + } +} +#[doc = "Frame Format\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FORM_A { + #[doc = "0: USART frame"] + USART_FRAME_NO_PARITY = 0, + #[doc = "1: USART frame with parity"] + USART_FRAME_WITH_PARITY = 1, + #[doc = "2: LIN Master - Break and sync generation"] + USART_FRAME_LIN_MASTER_MODE = 2, + #[doc = "4: Auto-baud - break detection and auto-baud"] + USART_FRAME_AUTO_BAUD_NO_PARITY = 4, + #[doc = "5: Auto-baud - break detection and auto-baud with parity"] + USART_FRAME_AUTO_BAUD_WITH_PARITY = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FORM_A) -> Self { + variant as _ + } +} +#[doc = "Field `FORM` reader - Frame Format"] +pub struct FORM_R(crate::FieldReader); +impl FORM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FORM_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(FORM_A::USART_FRAME_NO_PARITY), + 1 => Some(FORM_A::USART_FRAME_WITH_PARITY), + 2 => Some(FORM_A::USART_FRAME_LIN_MASTER_MODE), + 4 => Some(FORM_A::USART_FRAME_AUTO_BAUD_NO_PARITY), + 5 => Some(FORM_A::USART_FRAME_AUTO_BAUD_WITH_PARITY), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_FRAME_NO_PARITY`"] + #[inline(always)] + pub fn is_usart_frame_no_parity(&self) -> bool { + **self == FORM_A::USART_FRAME_NO_PARITY + } + #[doc = "Checks if the value of the field is `USART_FRAME_WITH_PARITY`"] + #[inline(always)] + pub fn is_usart_frame_with_parity(&self) -> bool { + **self == FORM_A::USART_FRAME_WITH_PARITY + } + #[doc = "Checks if the value of the field is `USART_FRAME_LIN_MASTER_MODE`"] + #[inline(always)] + pub fn is_usart_frame_lin_master_mode(&self) -> bool { + **self == FORM_A::USART_FRAME_LIN_MASTER_MODE + } + #[doc = "Checks if the value of the field is `USART_FRAME_AUTO_BAUD_NO_PARITY`"] + #[inline(always)] + pub fn is_usart_frame_auto_baud_no_parity(&self) -> bool { + **self == FORM_A::USART_FRAME_AUTO_BAUD_NO_PARITY + } + #[doc = "Checks if the value of the field is `USART_FRAME_AUTO_BAUD_WITH_PARITY`"] + #[inline(always)] + pub fn is_usart_frame_auto_baud_with_parity(&self) -> bool { + **self == FORM_A::USART_FRAME_AUTO_BAUD_WITH_PARITY + } +} +impl core::ops::Deref for FORM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FORM` writer - Frame Format"] +pub struct FORM_W<'a> { + w: &'a mut W, +} +impl<'a> FORM_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FORM_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART frame"] + #[inline(always)] + pub fn usart_frame_no_parity(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_NO_PARITY) + } + #[doc = "USART frame with parity"] + #[inline(always)] + pub fn usart_frame_with_parity(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_WITH_PARITY) + } + #[doc = "LIN Master - Break and sync generation"] + #[inline(always)] + pub fn usart_frame_lin_master_mode(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_LIN_MASTER_MODE) + } + #[doc = "Auto-baud - break detection and auto-baud"] + #[inline(always)] + pub fn usart_frame_auto_baud_no_parity(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_AUTO_BAUD_NO_PARITY) + } + #[doc = "Auto-baud - break detection and auto-baud with parity"] + #[inline(always)] + pub fn usart_frame_auto_baud_with_parity(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_AUTO_BAUD_WITH_PARITY) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Communication Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CMODE_A { + #[doc = "0: Asynchronous Communication"] + ASYNC = 0, + #[doc = "1: Synchronous Communication"] + SYNC = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CMODE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CMODE` reader - Communication Mode"] +pub struct CMODE_R(crate::FieldReader); +impl CMODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CMODE_A { + match self.bits { + false => CMODE_A::ASYNC, + true => CMODE_A::SYNC, + } + } + #[doc = "Checks if the value of the field is `ASYNC`"] + #[inline(always)] + pub fn is_async(&self) -> bool { + **self == CMODE_A::ASYNC + } + #[doc = "Checks if the value of the field is `SYNC`"] + #[inline(always)] + pub fn is_sync(&self) -> bool { + **self == CMODE_A::SYNC + } +} +impl core::ops::Deref for CMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMODE` writer - Communication Mode"] +pub struct CMODE_W<'a> { + w: &'a mut W, +} +impl<'a> CMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMODE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Asynchronous Communication"] + #[inline(always)] + pub fn async_(self) -> &'a mut W { + self.variant(CMODE_A::ASYNC) + } + #[doc = "Synchronous Communication"] + #[inline(always)] + pub fn sync(self) -> &'a mut W { + self.variant(CMODE_A::SYNC) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Clock Polarity\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CPOL_A { + #[doc = "0: TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge"] + IDLE_LOW = 0, + #[doc = "1: TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge"] + IDLE_HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CPOL_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CPOL` reader - Clock Polarity"] +pub struct CPOL_R(crate::FieldReader); +impl CPOL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPOL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CPOL_A { + match self.bits { + false => CPOL_A::IDLE_LOW, + true => CPOL_A::IDLE_HIGH, + } + } + #[doc = "Checks if the value of the field is `IDLE_LOW`"] + #[inline(always)] + pub fn is_idle_low(&self) -> bool { + **self == CPOL_A::IDLE_LOW + } + #[doc = "Checks if the value of the field is `IDLE_HIGH`"] + #[inline(always)] + pub fn is_idle_high(&self) -> bool { + **self == CPOL_A::IDLE_HIGH + } +} +impl core::ops::Deref for CPOL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPOL` writer - Clock Polarity"] +pub struct CPOL_W<'a> { + w: &'a mut W, +} +impl<'a> CPOL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CPOL_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge"] + #[inline(always)] + pub fn idle_low(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_LOW) + } + #[doc = "TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge"] + #[inline(always)] + pub fn idle_high(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_HIGH) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29); + self.w + } +} +#[doc = "Data Order\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum DORD_A { + #[doc = "0: MSB is transmitted first"] + MSB = 0, + #[doc = "1: LSB is transmitted first"] + LSB = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DORD_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DORD` reader - Data Order"] +pub struct DORD_R(crate::FieldReader); +impl DORD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DORD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DORD_A { + match self.bits { + false => DORD_A::MSB, + true => DORD_A::LSB, + } + } + #[doc = "Checks if the value of the field is `MSB`"] + #[inline(always)] + pub fn is_msb(&self) -> bool { + **self == DORD_A::MSB + } + #[doc = "Checks if the value of the field is `LSB`"] + #[inline(always)] + pub fn is_lsb(&self) -> bool { + **self == DORD_A::LSB + } +} +impl core::ops::Deref for DORD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DORD` writer - Data Order"] +pub struct DORD_W<'a> { + w: &'a mut W, +} +impl<'a> DORD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DORD_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "MSB is transmitted first"] + #[inline(always)] + pub fn msb(self) -> &'a mut W { + self.variant(DORD_A::MSB) + } + #[doc = "LSB is transmitted first"] + #[inline(always)] + pub fn lsb(self) -> &'a mut W { + self.variant(DORD_A::LSB) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x07) as u8) + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&self) -> IBON_R { + IBON_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bits 13:15 - Sample"] + #[inline(always)] + pub fn sampr(&self) -> SAMPR_R { + SAMPR_R::new(((self.bits >> 13) & 0x07) as u8) + } + #[doc = "Bits 16:17 - Transmit Data Pinout"] + #[inline(always)] + pub fn txpo(&self) -> TXPO_R { + TXPO_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bits 20:21 - Receive Data Pinout"] + #[inline(always)] + pub fn rxpo(&self) -> RXPO_R { + RXPO_R::new(((self.bits >> 20) & 0x03) as u8) + } + #[doc = "Bits 22:23 - Sample Adjustment"] + #[inline(always)] + pub fn sampa(&self) -> SAMPA_R { + SAMPA_R::new(((self.bits >> 22) & 0x03) as u8) + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&self) -> FORM_R { + FORM_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 28 - Communication Mode"] + #[inline(always)] + pub fn cmode(&self) -> CMODE_R { + CMODE_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&self) -> CPOL_R { + CPOL_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&self) -> DORD_R { + DORD_R::new(((self.bits >> 30) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&mut self) -> IBON_W { + IBON_W { w: self } + } + #[doc = "Bits 13:15 - Sample"] + #[inline(always)] + pub fn sampr(&mut self) -> SAMPR_W { + SAMPR_W { w: self } + } + #[doc = "Bits 16:17 - Transmit Data Pinout"] + #[inline(always)] + pub fn txpo(&mut self) -> TXPO_W { + TXPO_W { w: self } + } + #[doc = "Bits 20:21 - Receive Data Pinout"] + #[inline(always)] + pub fn rxpo(&mut self) -> RXPO_W { + RXPO_W { w: self } + } + #[doc = "Bits 22:23 - Sample Adjustment"] + #[inline(always)] + pub fn sampa(&mut self) -> SAMPA_W { + SAMPA_W { w: self } + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&mut self) -> FORM_W { + FORM_W { w: self } + } + #[doc = "Bit 28 - Communication Mode"] + #[inline(always)] + pub fn cmode(&mut self) -> CMODE_W { + CMODE_W { w: self } + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&mut self) -> CPOL_W { + CPOL_W { w: self } + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&mut self) -> DORD_W { + DORD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/sercom0/usart_ext/ctrlb.rs b/pac/atsamc20n/src/sercom0/usart_ext/ctrlb.rs new file mode 100644 index 000000000000..37567555e842 --- /dev/null +++ b/pac/atsamc20n/src/sercom0/usart_ext/ctrlb.rs @@ -0,0 +1,651 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Character Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CHSIZE_A { + #[doc = "0: 8 Bits"] + _8_BIT = 0, + #[doc = "1: 9 Bits"] + _9_BIT = 1, + #[doc = "5: 5 Bits"] + _5_BIT = 5, + #[doc = "6: 6 Bits"] + _6_BIT = 6, + #[doc = "7: 7 Bits"] + _7_BIT = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CHSIZE_A) -> Self { + variant as _ + } +} +#[doc = "Field `CHSIZE` reader - Character Size"] +pub struct CHSIZE_R(crate::FieldReader); +impl CHSIZE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CHSIZE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CHSIZE_A::_8_BIT), + 1 => Some(CHSIZE_A::_9_BIT), + 5 => Some(CHSIZE_A::_5_BIT), + 6 => Some(CHSIZE_A::_6_BIT), + 7 => Some(CHSIZE_A::_7_BIT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_8_BIT`"] + #[inline(always)] + pub fn is_8_bit(&self) -> bool { + **self == CHSIZE_A::_8_BIT + } + #[doc = "Checks if the value of the field is `_9_BIT`"] + #[inline(always)] + pub fn is_9_bit(&self) -> bool { + **self == CHSIZE_A::_9_BIT + } + #[doc = "Checks if the value of the field is `_5_BIT`"] + #[inline(always)] + pub fn is_5_bit(&self) -> bool { + **self == CHSIZE_A::_5_BIT + } + #[doc = "Checks if the value of the field is `_6_BIT`"] + #[inline(always)] + pub fn is_6_bit(&self) -> bool { + **self == CHSIZE_A::_6_BIT + } + #[doc = "Checks if the value of the field is `_7_BIT`"] + #[inline(always)] + pub fn is_7_bit(&self) -> bool { + **self == CHSIZE_A::_7_BIT + } +} +impl core::ops::Deref for CHSIZE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHSIZE` writer - Character Size"] +pub struct CHSIZE_W<'a> { + w: &'a mut W, +} +impl<'a> CHSIZE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CHSIZE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8 Bits"] + #[inline(always)] + pub fn _8_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_8_BIT) + } + #[doc = "9 Bits"] + #[inline(always)] + pub fn _9_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_9_BIT) + } + #[doc = "5 Bits"] + #[inline(always)] + pub fn _5_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_5_BIT) + } + #[doc = "6 Bits"] + #[inline(always)] + pub fn _6_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_6_BIT) + } + #[doc = "7 Bits"] + #[inline(always)] + pub fn _7_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_7_BIT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Stop Bit Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SBMODE_A { + #[doc = "0: One Stop Bit"] + _1_BIT = 0, + #[doc = "1: Two Stop Bits"] + _2_BIT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SBMODE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SBMODE` reader - Stop Bit Mode"] +pub struct SBMODE_R(crate::FieldReader); +impl SBMODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SBMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SBMODE_A { + match self.bits { + false => SBMODE_A::_1_BIT, + true => SBMODE_A::_2_BIT, + } + } + #[doc = "Checks if the value of the field is `_1_BIT`"] + #[inline(always)] + pub fn is_1_bit(&self) -> bool { + **self == SBMODE_A::_1_BIT + } + #[doc = "Checks if the value of the field is `_2_BIT`"] + #[inline(always)] + pub fn is_2_bit(&self) -> bool { + **self == SBMODE_A::_2_BIT + } +} +impl core::ops::Deref for SBMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SBMODE` writer - Stop Bit Mode"] +pub struct SBMODE_W<'a> { + w: &'a mut W, +} +impl<'a> SBMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SBMODE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "One Stop Bit"] + #[inline(always)] + pub fn _1_bit(self) -> &'a mut W { + self.variant(SBMODE_A::_1_BIT) + } + #[doc = "Two Stop Bits"] + #[inline(always)] + pub fn _2_bit(self) -> &'a mut W { + self.variant(SBMODE_A::_2_BIT) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `COLDEN` reader - Collision Detection Enable"] +pub struct COLDEN_R(crate::FieldReader); +impl COLDEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COLDEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COLDEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COLDEN` writer - Collision Detection Enable"] +pub struct COLDEN_W<'a> { + w: &'a mut W, +} +impl<'a> COLDEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `SFDE` reader - Start of Frame Detection Enable"] +pub struct SFDE_R(crate::FieldReader); +impl SFDE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SFDE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SFDE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SFDE` writer - Start of Frame Detection Enable"] +pub struct SFDE_W<'a> { + w: &'a mut W, +} +impl<'a> SFDE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `ENC` reader - Encoding Format"] +pub struct ENC_R(crate::FieldReader); +impl ENC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENC` writer - Encoding Format"] +pub struct ENC_W<'a> { + w: &'a mut W, +} +impl<'a> ENC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Parity Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PMODE_A { + #[doc = "0: Even Parity"] + EVEN = 0, + #[doc = "1: Odd Parity"] + ODD = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PMODE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PMODE` reader - Parity Mode"] +pub struct PMODE_R(crate::FieldReader); +impl PMODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PMODE_A { + match self.bits { + false => PMODE_A::EVEN, + true => PMODE_A::ODD, + } + } + #[doc = "Checks if the value of the field is `EVEN`"] + #[inline(always)] + pub fn is_even(&self) -> bool { + **self == PMODE_A::EVEN + } + #[doc = "Checks if the value of the field is `ODD`"] + #[inline(always)] + pub fn is_odd(&self) -> bool { + **self == PMODE_A::ODD + } +} +impl core::ops::Deref for PMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PMODE` writer - Parity Mode"] +pub struct PMODE_W<'a> { + w: &'a mut W, +} +impl<'a> PMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PMODE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Even Parity"] + #[inline(always)] + pub fn even(self) -> &'a mut W { + self.variant(PMODE_A::EVEN) + } + #[doc = "Odd Parity"] + #[inline(always)] + pub fn odd(self) -> &'a mut W { + self.variant(PMODE_A::ODD) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `TXEN` reader - Transmitter Enable"] +pub struct TXEN_R(crate::FieldReader); +impl TXEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXEN` writer - Transmitter Enable"] +pub struct TXEN_W<'a> { + w: &'a mut W, +} +impl<'a> TXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `RXEN` reader - Receiver Enable"] +pub struct RXEN_R(crate::FieldReader); +impl RXEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXEN` writer - Receiver Enable"] +pub struct RXEN_W<'a> { + w: &'a mut W, +} +impl<'a> RXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `LINCMD` reader - LIN Command"] +pub struct LINCMD_R(crate::FieldReader); +impl LINCMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LINCMD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LINCMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LINCMD` writer - LIN Command"] +pub struct LINCMD_W<'a> { + w: &'a mut W, +} +impl<'a> LINCMD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 24)) | ((value as u32 & 0x03) << 24); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&self) -> CHSIZE_R { + CHSIZE_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 6 - Stop Bit Mode"] + #[inline(always)] + pub fn sbmode(&self) -> SBMODE_R { + SBMODE_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 8 - Collision Detection Enable"] + #[inline(always)] + pub fn colden(&self) -> COLDEN_R { + COLDEN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Start of Frame Detection Enable"] + #[inline(always)] + pub fn sfde(&self) -> SFDE_R { + SFDE_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Encoding Format"] + #[inline(always)] + pub fn enc(&self) -> ENC_R { + ENC_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 13 - Parity Mode"] + #[inline(always)] + pub fn pmode(&self) -> PMODE_R { + PMODE_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 16 - Transmitter Enable"] + #[inline(always)] + pub fn txen(&self) -> TXEN_R { + TXEN_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&self) -> RXEN_R { + RXEN_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bits 24:25 - LIN Command"] + #[inline(always)] + pub fn lincmd(&self) -> LINCMD_R { + LINCMD_R::new(((self.bits >> 24) & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&mut self) -> CHSIZE_W { + CHSIZE_W { w: self } + } + #[doc = "Bit 6 - Stop Bit Mode"] + #[inline(always)] + pub fn sbmode(&mut self) -> SBMODE_W { + SBMODE_W { w: self } + } + #[doc = "Bit 8 - Collision Detection Enable"] + #[inline(always)] + pub fn colden(&mut self) -> COLDEN_W { + COLDEN_W { w: self } + } + #[doc = "Bit 9 - Start of Frame Detection Enable"] + #[inline(always)] + pub fn sfde(&mut self) -> SFDE_W { + SFDE_W { w: self } + } + #[doc = "Bit 10 - Encoding Format"] + #[inline(always)] + pub fn enc(&mut self) -> ENC_W { + ENC_W { w: self } + } + #[doc = "Bit 13 - Parity Mode"] + #[inline(always)] + pub fn pmode(&mut self) -> PMODE_W { + PMODE_W { w: self } + } + #[doc = "Bit 16 - Transmitter Enable"] + #[inline(always)] + pub fn txen(&mut self) -> TXEN_W { + TXEN_W { w: self } + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&mut self) -> RXEN_W { + RXEN_W { w: self } + } + #[doc = "Bits 24:25 - LIN Command"] + #[inline(always)] + pub fn lincmd(&mut self) -> LINCMD_W { + LINCMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/sercom0/usart_ext/ctrlc.rs b/pac/atsamc20n/src/sercom0/usart_ext/ctrlc.rs new file mode 100644 index 000000000000..5840d5c3bd06 --- /dev/null +++ b/pac/atsamc20n/src/sercom0/usart_ext/ctrlc.rs @@ -0,0 +1,177 @@ +#[doc = "Register `CTRLC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `GTIME` reader - RS485 Guard Time"] +pub struct GTIME_R(crate::FieldReader); +impl GTIME_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + GTIME_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GTIME_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GTIME` writer - RS485 Guard Time"] +pub struct GTIME_W<'a> { + w: &'a mut W, +} +impl<'a> GTIME_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Field `BRKLEN` reader - LIN Master Break Length"] +pub struct BRKLEN_R(crate::FieldReader); +impl BRKLEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BRKLEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BRKLEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BRKLEN` writer - LIN Master Break Length"] +pub struct BRKLEN_W<'a> { + w: &'a mut W, +} +impl<'a> BRKLEN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 8)) | ((value as u32 & 0x03) << 8); + self.w + } +} +#[doc = "Field `HDRDLY` reader - LIN Master Header Delay"] +pub struct HDRDLY_R(crate::FieldReader); +impl HDRDLY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + HDRDLY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HDRDLY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HDRDLY` writer - LIN Master Header Delay"] +pub struct HDRDLY_W<'a> { + w: &'a mut W, +} +impl<'a> HDRDLY_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 10)) | ((value as u32 & 0x03) << 10); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - RS485 Guard Time"] + #[inline(always)] + pub fn gtime(&self) -> GTIME_R { + GTIME_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bits 8:9 - LIN Master Break Length"] + #[inline(always)] + pub fn brklen(&self) -> BRKLEN_R { + BRKLEN_R::new(((self.bits >> 8) & 0x03) as u8) + } + #[doc = "Bits 10:11 - LIN Master Header Delay"] + #[inline(always)] + pub fn hdrdly(&self) -> HDRDLY_R { + HDRDLY_R::new(((self.bits >> 10) & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - RS485 Guard Time"] + #[inline(always)] + pub fn gtime(&mut self) -> GTIME_W { + GTIME_W { w: self } + } + #[doc = "Bits 8:9 - LIN Master Break Length"] + #[inline(always)] + pub fn brklen(&mut self) -> BRKLEN_W { + BRKLEN_W { w: self } + } + #[doc = "Bits 10:11 - LIN Master Header Delay"] + #[inline(always)] + pub fn hdrdly(&mut self) -> HDRDLY_W { + HDRDLY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Control C\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlc](index.html) module"] +pub struct CTRLC_SPEC; +impl crate::RegisterSpec for CTRLC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlc::R](R) reader structure"] +impl crate::Readable for CTRLC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlc::W](W) writer structure"] +impl crate::Writable for CTRLC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLC to value 0"] +impl crate::Resettable for CTRLC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/sercom0/usart_ext/data.rs b/pac/atsamc20n/src/sercom0/usart_ext/data.rs new file mode 100644 index 000000000000..a54152c9571a --- /dev/null +++ b/pac/atsamc20n/src/sercom0/usart_ext/data.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data Value"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data Value"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01ff) | (value as u16 & 0x01ff); + self.w + } +} +impl R { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new((self.bits & 0x01ff) as u16) + } +} +impl W { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/sercom0/usart_ext/dbgctrl.rs b/pac/atsamc20n/src/sercom0/usart_ext/dbgctrl.rs new file mode 100644 index 000000000000..6c844f3fe40d --- /dev/null +++ b/pac/atsamc20n/src/sercom0/usart_ext/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGSTOP` reader - Debug Mode"] +pub struct DBGSTOP_R(crate::FieldReader); +impl DBGSTOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGSTOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGSTOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGSTOP` writer - Debug Mode"] +pub struct DBGSTOP_W<'a> { + w: &'a mut W, +} +impl<'a> DBGSTOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&self) -> DBGSTOP_R { + DBGSTOP_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&mut self) -> DBGSTOP_W { + DBGSTOP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/sercom0/usart_ext/intenclr.rs b/pac/atsamc20n/src/sercom0/usart_ext/intenclr.rs new file mode 100644 index 000000000000..a815553ce666 --- /dev/null +++ b/pac/atsamc20n/src/sercom0/usart_ext/intenclr.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Disable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Disable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Disable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Disable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Disable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Disable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RXS` reader - Receive Start Interrupt Disable"] +pub struct RXS_R(crate::FieldReader); +impl RXS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXS` writer - Receive Start Interrupt Disable"] +pub struct RXS_W<'a> { + w: &'a mut W, +} +impl<'a> RXS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CTSIC` reader - Clear To Send Input Change Interrupt Disable"] +pub struct CTSIC_R(crate::FieldReader); +impl CTSIC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTSIC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTSIC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTSIC` writer - Clear To Send Input Change Interrupt Disable"] +pub struct CTSIC_W<'a> { + w: &'a mut W, +} +impl<'a> CTSIC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RXBRK` reader - Break Received Interrupt Disable"] +pub struct RXBRK_R(crate::FieldReader); +impl RXBRK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXBRK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXBRK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXBRK` writer - Break Received Interrupt Disable"] +pub struct RXBRK_W<'a> { + w: &'a mut W, +} +impl<'a> RXBRK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Disable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Disable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Receive Start Interrupt Disable"] + #[inline(always)] + pub fn rxs(&self) -> RXS_R { + RXS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Disable"] + #[inline(always)] + pub fn ctsic(&self) -> CTSIC_R { + CTSIC_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Break Received Interrupt Disable"] + #[inline(always)] + pub fn rxbrk(&self) -> RXBRK_R { + RXBRK_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Receive Start Interrupt Disable"] + #[inline(always)] + pub fn rxs(&mut self) -> RXS_W { + RXS_W { w: self } + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Disable"] + #[inline(always)] + pub fn ctsic(&mut self) -> CTSIC_W { + CTSIC_W { w: self } + } + #[doc = "Bit 5 - Break Received Interrupt Disable"] + #[inline(always)] + pub fn rxbrk(&mut self) -> RXBRK_W { + RXBRK_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/sercom0/usart_ext/intenset.rs b/pac/atsamc20n/src/sercom0/usart_ext/intenset.rs new file mode 100644 index 000000000000..e800681cf423 --- /dev/null +++ b/pac/atsamc20n/src/sercom0/usart_ext/intenset.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Enable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Enable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Enable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Enable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Enable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Enable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RXS` reader - Receive Start Interrupt Enable"] +pub struct RXS_R(crate::FieldReader); +impl RXS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXS` writer - Receive Start Interrupt Enable"] +pub struct RXS_W<'a> { + w: &'a mut W, +} +impl<'a> RXS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CTSIC` reader - Clear To Send Input Change Interrupt Enable"] +pub struct CTSIC_R(crate::FieldReader); +impl CTSIC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTSIC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTSIC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTSIC` writer - Clear To Send Input Change Interrupt Enable"] +pub struct CTSIC_W<'a> { + w: &'a mut W, +} +impl<'a> CTSIC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RXBRK` reader - Break Received Interrupt Enable"] +pub struct RXBRK_R(crate::FieldReader); +impl RXBRK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXBRK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXBRK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXBRK` writer - Break Received Interrupt Enable"] +pub struct RXBRK_W<'a> { + w: &'a mut W, +} +impl<'a> RXBRK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Receive Start Interrupt Enable"] + #[inline(always)] + pub fn rxs(&self) -> RXS_R { + RXS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Enable"] + #[inline(always)] + pub fn ctsic(&self) -> CTSIC_R { + CTSIC_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Break Received Interrupt Enable"] + #[inline(always)] + pub fn rxbrk(&self) -> RXBRK_R { + RXBRK_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Receive Start Interrupt Enable"] + #[inline(always)] + pub fn rxs(&mut self) -> RXS_W { + RXS_W { w: self } + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Enable"] + #[inline(always)] + pub fn ctsic(&mut self) -> CTSIC_W { + CTSIC_W { w: self } + } + #[doc = "Bit 5 - Break Received Interrupt Enable"] + #[inline(always)] + pub fn rxbrk(&mut self) -> RXBRK_W { + RXBRK_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/sercom0/usart_ext/intflag.rs b/pac/atsamc20n/src/sercom0/usart_ext/intflag.rs new file mode 100644 index 000000000000..4b0be279a9ae --- /dev/null +++ b/pac/atsamc20n/src/sercom0/usart_ext/intflag.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RXS` reader - Receive Start Interrupt"] +pub struct RXS_R(crate::FieldReader); +impl RXS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXS` writer - Receive Start Interrupt"] +pub struct RXS_W<'a> { + w: &'a mut W, +} +impl<'a> RXS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CTSIC` reader - Clear To Send Input Change Interrupt"] +pub struct CTSIC_R(crate::FieldReader); +impl CTSIC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTSIC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTSIC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTSIC` writer - Clear To Send Input Change Interrupt"] +pub struct CTSIC_W<'a> { + w: &'a mut W, +} +impl<'a> CTSIC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RXBRK` reader - Break Received Interrupt"] +pub struct RXBRK_R(crate::FieldReader); +impl RXBRK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXBRK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXBRK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXBRK` writer - Break Received Interrupt"] +pub struct RXBRK_W<'a> { + w: &'a mut W, +} +impl<'a> RXBRK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Receive Start Interrupt"] + #[inline(always)] + pub fn rxs(&self) -> RXS_R { + RXS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt"] + #[inline(always)] + pub fn ctsic(&self) -> CTSIC_R { + CTSIC_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Break Received Interrupt"] + #[inline(always)] + pub fn rxbrk(&self) -> RXBRK_R { + RXBRK_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Receive Start Interrupt"] + #[inline(always)] + pub fn rxs(&mut self) -> RXS_W { + RXS_W { w: self } + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt"] + #[inline(always)] + pub fn ctsic(&mut self) -> CTSIC_W { + CTSIC_W { w: self } + } + #[doc = "Bit 5 - Break Received Interrupt"] + #[inline(always)] + pub fn rxbrk(&mut self) -> RXBRK_W { + RXBRK_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/sercom0/usart_ext/rxpl.rs b/pac/atsamc20n/src/sercom0/usart_ext/rxpl.rs new file mode 100644 index 000000000000..174464dc16b5 --- /dev/null +++ b/pac/atsamc20n/src/sercom0/usart_ext/rxpl.rs @@ -0,0 +1,103 @@ +#[doc = "Register `RXPL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RXPL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RXPL` reader - Receive Pulse Length"] +pub struct RXPL_R(crate::FieldReader); +impl RXPL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RXPL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXPL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXPL` writer - Receive Pulse Length"] +pub struct RXPL_W<'a> { + w: &'a mut W, +} +impl<'a> RXPL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Receive Pulse Length"] + #[inline(always)] + pub fn rxpl(&self) -> RXPL_R { + RXPL_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Receive Pulse Length"] + #[inline(always)] + pub fn rxpl(&mut self) -> RXPL_W { + RXPL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Receive Pulse Length\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxpl](index.html) module"] +pub struct RXPL_SPEC; +impl crate::RegisterSpec for RXPL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [rxpl::R](R) reader structure"] +impl crate::Readable for RXPL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rxpl::W](W) writer structure"] +impl crate::Writable for RXPL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RXPL to value 0"] +impl crate::Resettable for RXPL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/sercom0/usart_ext/status.rs b/pac/atsamc20n/src/sercom0/usart_ext/status.rs new file mode 100644 index 000000000000..a0c50c1bc2cf --- /dev/null +++ b/pac/atsamc20n/src/sercom0/usart_ext/status.rs @@ -0,0 +1,395 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PERR` reader - Parity Error"] +pub struct PERR_R(crate::FieldReader); +impl PERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERR` writer - Parity Error"] +pub struct PERR_W<'a> { + w: &'a mut W, +} +impl<'a> PERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `FERR` reader - Frame Error"] +pub struct FERR_R(crate::FieldReader); +impl FERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FERR` writer - Frame Error"] +pub struct FERR_W<'a> { + w: &'a mut W, +} +impl<'a> FERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `BUFOVF` reader - Buffer Overflow"] +pub struct BUFOVF_R(crate::FieldReader); +impl BUFOVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUFOVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUFOVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUFOVF` writer - Buffer Overflow"] +pub struct BUFOVF_W<'a> { + w: &'a mut W, +} +impl<'a> BUFOVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CTS` reader - Clear To Send"] +pub struct CTS_R(crate::FieldReader); +impl CTS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTS` writer - Clear To Send"] +pub struct CTS_W<'a> { + w: &'a mut W, +} +impl<'a> CTS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ISF` reader - Inconsistent Sync Field"] +pub struct ISF_R(crate::FieldReader); +impl ISF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ISF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ISF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ISF` writer - Inconsistent Sync Field"] +pub struct ISF_W<'a> { + w: &'a mut W, +} +impl<'a> ISF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `COLL` reader - Collision Detected"] +pub struct COLL_R(crate::FieldReader); +impl COLL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COLL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COLL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COLL` writer - Collision Detected"] +pub struct COLL_W<'a> { + w: &'a mut W, +} +impl<'a> COLL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `TXE` reader - Transmitter Empty"] +pub struct TXE_R(crate::FieldReader); +impl TXE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXE` writer - Transmitter Empty"] +pub struct TXE_W<'a> { + w: &'a mut W, +} +impl<'a> TXE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - Parity Error"] + #[inline(always)] + pub fn perr(&self) -> PERR_R { + PERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Frame Error"] + #[inline(always)] + pub fn ferr(&self) -> FERR_R { + FERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&self) -> BUFOVF_R { + BUFOVF_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Clear To Send"] + #[inline(always)] + pub fn cts(&self) -> CTS_R { + CTS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Inconsistent Sync Field"] + #[inline(always)] + pub fn isf(&self) -> ISF_R { + ISF_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Collision Detected"] + #[inline(always)] + pub fn coll(&self) -> COLL_R { + COLL_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Transmitter Empty"] + #[inline(always)] + pub fn txe(&self) -> TXE_R { + TXE_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Parity Error"] + #[inline(always)] + pub fn perr(&mut self) -> PERR_W { + PERR_W { w: self } + } + #[doc = "Bit 1 - Frame Error"] + #[inline(always)] + pub fn ferr(&mut self) -> FERR_W { + FERR_W { w: self } + } + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&mut self) -> BUFOVF_W { + BUFOVF_W { w: self } + } + #[doc = "Bit 3 - Clear To Send"] + #[inline(always)] + pub fn cts(&mut self) -> CTS_W { + CTS_W { w: self } + } + #[doc = "Bit 4 - Inconsistent Sync Field"] + #[inline(always)] + pub fn isf(&mut self) -> ISF_W { + ISF_W { w: self } + } + #[doc = "Bit 5 - Collision Detected"] + #[inline(always)] + pub fn coll(&mut self) -> COLL_W { + COLL_W { w: self } + } + #[doc = "Bit 6 - Transmitter Empty"] + #[inline(always)] + pub fn txe(&mut self) -> TXE_W { + TXE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/sercom0/usart_ext/syncbusy.rs b/pac/atsamc20n/src/sercom0/usart_ext/syncbusy.rs new file mode 100644 index 000000000000..7c3b817bbb04 --- /dev/null +++ b/pac/atsamc20n/src/sercom0/usart_ext/syncbusy.rs @@ -0,0 +1,93 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - SERCOM Enable Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLB` reader - CTRLB Synchronization Busy"] +pub struct CTRLB_R(crate::FieldReader); +impl CTRLB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM Enable Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - CTRLB Synchronization Busy"] + #[inline(always)] + pub fn ctrlb(&self) -> CTRLB_R { + CTRLB_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +#[doc = "USART_EXT Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/sercom0/usart_int.rs b/pac/atsamc20n/src/sercom0/usart_int.rs new file mode 100644 index 000000000000..157c8c4b4fdc --- /dev/null +++ b/pac/atsamc20n/src/sercom0/usart_int.rs @@ -0,0 +1,60 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "USART_INT Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "USART_INT Control B"] +pub mod ctrlb; +#[doc = "CTRLC register accessor: an alias for `Reg`"] +pub type CTRLC = crate::Reg; +#[doc = "USART_INT Control C"] +pub mod ctrlc; +#[doc = "BAUD register accessor: an alias for `Reg`"] +pub type BAUD = crate::Reg; +#[doc = "USART_INT Baud Rate"] +pub mod baud; +#[doc = "BAUD_FRAC_MODE register accessor: an alias for `Reg`"] +pub type BAUD_FRAC_MODE = crate::Reg; +#[doc = "USART_INT Baud Rate"] +pub mod baud_frac_mode; +#[doc = "BAUD_FRACFP_MODE register accessor: an alias for `Reg`"] +pub type BAUD_FRACFP_MODE = crate::Reg; +#[doc = "USART_INT Baud Rate"] +pub mod baud_fracfp_mode; +#[doc = "BAUD_USARTFP_MODE register accessor: an alias for `Reg`"] +pub type BAUD_USARTFP_MODE = crate::Reg; +#[doc = "USART_INT Baud Rate"] +pub mod baud_usartfp_mode; +#[doc = "RXPL register accessor: an alias for `Reg`"] +pub type RXPL = crate::Reg; +#[doc = "USART_INT Receive Pulse Length"] +pub mod rxpl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "USART_INT Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "USART_INT Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "USART_INT Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "USART_INT Status"] +pub mod status; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "USART_INT Synchronization Busy"] +pub mod syncbusy; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "USART_INT Data"] +pub mod data; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "USART_INT Debug Control"] +pub mod dbgctrl; diff --git a/pac/atsamc20n/src/sercom0/usart_int/baud.rs b/pac/atsamc20n/src/sercom0/usart_int/baud.rs new file mode 100644 index 000000000000..a82df20712b3 --- /dev/null +++ b/pac/atsamc20n/src/sercom0/usart_int/baud.rs @@ -0,0 +1,103 @@ +#[doc = "Register `BAUD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud](index.html) module"] +pub struct BAUD_SPEC; +impl crate::RegisterSpec for BAUD_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud::R](R) reader structure"] +impl crate::Readable for BAUD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud::W](W) writer structure"] +impl crate::Writable for BAUD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD to value 0"] +impl crate::Resettable for BAUD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/sercom0/usart_int/baud_frac_mode.rs b/pac/atsamc20n/src/sercom0/usart_int/baud_frac_mode.rs new file mode 100644 index 000000000000..b9c7fa4c4b2a --- /dev/null +++ b/pac/atsamc20n/src/sercom0/usart_int/baud_frac_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `BAUD_FRAC_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD_FRAC_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1fff) | (value as u16 & 0x1fff); + self.w + } +} +#[doc = "Field `FP` reader - Fractional Part"] +pub struct FP_R(crate::FieldReader); +impl FP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FP` writer - Fractional Part"] +pub struct FP_W<'a> { + w: &'a mut W, +} +impl<'a> FP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 13)) | ((value as u16 & 0x07) << 13); + self.w + } +} +impl R { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new((self.bits & 0x1fff) as u16) + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&self) -> FP_R { + FP_R::new(((self.bits >> 13) & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&mut self) -> FP_W { + FP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud_frac_mode](index.html) module"] +pub struct BAUD_FRAC_MODE_SPEC; +impl crate::RegisterSpec for BAUD_FRAC_MODE_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud_frac_mode::R](R) reader structure"] +impl crate::Readable for BAUD_FRAC_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud_frac_mode::W](W) writer structure"] +impl crate::Writable for BAUD_FRAC_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD_FRAC_MODE to value 0"] +impl crate::Resettable for BAUD_FRAC_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/sercom0/usart_int/baud_fracfp_mode.rs b/pac/atsamc20n/src/sercom0/usart_int/baud_fracfp_mode.rs new file mode 100644 index 000000000000..0671db99cc9d --- /dev/null +++ b/pac/atsamc20n/src/sercom0/usart_int/baud_fracfp_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `BAUD_FRACFP_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD_FRACFP_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1fff) | (value as u16 & 0x1fff); + self.w + } +} +#[doc = "Field `FP` reader - Fractional Part"] +pub struct FP_R(crate::FieldReader); +impl FP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FP` writer - Fractional Part"] +pub struct FP_W<'a> { + w: &'a mut W, +} +impl<'a> FP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 13)) | ((value as u16 & 0x07) << 13); + self.w + } +} +impl R { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new((self.bits & 0x1fff) as u16) + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&self) -> FP_R { + FP_R::new(((self.bits >> 13) & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&mut self) -> FP_W { + FP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud_fracfp_mode](index.html) module"] +pub struct BAUD_FRACFP_MODE_SPEC; +impl crate::RegisterSpec for BAUD_FRACFP_MODE_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud_fracfp_mode::R](R) reader structure"] +impl crate::Readable for BAUD_FRACFP_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud_fracfp_mode::W](W) writer structure"] +impl crate::Writable for BAUD_FRACFP_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD_FRACFP_MODE to value 0"] +impl crate::Resettable for BAUD_FRACFP_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/sercom0/usart_int/baud_usartfp_mode.rs b/pac/atsamc20n/src/sercom0/usart_int/baud_usartfp_mode.rs new file mode 100644 index 000000000000..b49a7ef5b84c --- /dev/null +++ b/pac/atsamc20n/src/sercom0/usart_int/baud_usartfp_mode.rs @@ -0,0 +1,103 @@ +#[doc = "Register `BAUD_USARTFP_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD_USARTFP_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud_usartfp_mode](index.html) module"] +pub struct BAUD_USARTFP_MODE_SPEC; +impl crate::RegisterSpec for BAUD_USARTFP_MODE_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud_usartfp_mode::R](R) reader structure"] +impl crate::Readable for BAUD_USARTFP_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud_usartfp_mode::W](W) writer structure"] +impl crate::Writable for BAUD_USARTFP_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD_USARTFP_MODE to value 0"] +impl crate::Resettable for BAUD_USARTFP_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/sercom0/usart_int/ctrla.rs b/pac/atsamc20n/src/sercom0/usart_int/ctrla.rs new file mode 100644 index 000000000000..19d10ecf8e8f --- /dev/null +++ b/pac/atsamc20n/src/sercom0/usart_int/ctrla.rs @@ -0,0 +1,1171 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: USART with external clock"] + USART_EXT_CLK = 0, + #[doc = "1: USART with internal clock"] + USART_INT_CLK = 1, + #[doc = "2: SPI in slave operation"] + SPI_SLAVE = 2, + #[doc = "3: SPI in master operation"] + SPI_MASTER = 3, + #[doc = "4: I2C slave operation"] + I2C_SLAVE = 4, + #[doc = "5: I2C master operation"] + I2C_MASTER = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::USART_EXT_CLK), + 1 => Some(MODE_A::USART_INT_CLK), + 2 => Some(MODE_A::SPI_SLAVE), + 3 => Some(MODE_A::SPI_MASTER), + 4 => Some(MODE_A::I2C_SLAVE), + 5 => Some(MODE_A::I2C_MASTER), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_EXT_CLK`"] + #[inline(always)] + pub fn is_usart_ext_clk(&self) -> bool { + **self == MODE_A::USART_EXT_CLK + } + #[doc = "Checks if the value of the field is `USART_INT_CLK`"] + #[inline(always)] + pub fn is_usart_int_clk(&self) -> bool { + **self == MODE_A::USART_INT_CLK + } + #[doc = "Checks if the value of the field is `SPI_SLAVE`"] + #[inline(always)] + pub fn is_spi_slave(&self) -> bool { + **self == MODE_A::SPI_SLAVE + } + #[doc = "Checks if the value of the field is `SPI_MASTER`"] + #[inline(always)] + pub fn is_spi_master(&self) -> bool { + **self == MODE_A::SPI_MASTER + } + #[doc = "Checks if the value of the field is `I2C_SLAVE`"] + #[inline(always)] + pub fn is_i2c_slave(&self) -> bool { + **self == MODE_A::I2C_SLAVE + } + #[doc = "Checks if the value of the field is `I2C_MASTER`"] + #[inline(always)] + pub fn is_i2c_master(&self) -> bool { + **self == MODE_A::I2C_MASTER + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART with external clock"] + #[inline(always)] + pub fn usart_ext_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_EXT_CLK) + } + #[doc = "USART with internal clock"] + #[inline(always)] + pub fn usart_int_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_INT_CLK) + } + #[doc = "SPI in slave operation"] + #[inline(always)] + pub fn spi_slave(self) -> &'a mut W { + self.variant(MODE_A::SPI_SLAVE) + } + #[doc = "SPI in master operation"] + #[inline(always)] + pub fn spi_master(self) -> &'a mut W { + self.variant(MODE_A::SPI_MASTER) + } + #[doc = "I2C slave operation"] + #[inline(always)] + pub fn i2c_slave(self) -> &'a mut W { + self.variant(MODE_A::I2C_SLAVE) + } + #[doc = "I2C master operation"] + #[inline(always)] + pub fn i2c_master(self) -> &'a mut W { + self.variant(MODE_A::I2C_MASTER) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 2)) | ((value as u32 & 0x07) << 2); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `IBON` reader - Immediate Buffer Overflow Notification"] +pub struct IBON_R(crate::FieldReader); +impl IBON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IBON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IBON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IBON` writer - Immediate Buffer Overflow Notification"] +pub struct IBON_W<'a> { + w: &'a mut W, +} +impl<'a> IBON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Sample\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SAMPR_A { + #[doc = "0: 16x over-sampling using arithmetic baudrate generation"] + _16X_ARITHMETIC = 0, + #[doc = "1: 16x over-sampling using fractional baudrate generation"] + _16X_FRACTIONAL = 1, + #[doc = "2: 8x over-sampling using arithmetic baudrate generation"] + _8X_ARITHMETIC = 2, + #[doc = "3: 8x over-sampling using fractional baudrate generation"] + _8X_FRACTIONAL = 3, + #[doc = "4: 3x over-sampling using arithmetic baudrate generation"] + _3X_ARITHMETIC = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SAMPR_A) -> Self { + variant as _ + } +} +#[doc = "Field `SAMPR` reader - Sample"] +pub struct SAMPR_R(crate::FieldReader); +impl SAMPR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SAMPR_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SAMPR_A::_16X_ARITHMETIC), + 1 => Some(SAMPR_A::_16X_FRACTIONAL), + 2 => Some(SAMPR_A::_8X_ARITHMETIC), + 3 => Some(SAMPR_A::_8X_FRACTIONAL), + 4 => Some(SAMPR_A::_3X_ARITHMETIC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_16X_ARITHMETIC`"] + #[inline(always)] + pub fn is_16x_arithmetic(&self) -> bool { + **self == SAMPR_A::_16X_ARITHMETIC + } + #[doc = "Checks if the value of the field is `_16X_FRACTIONAL`"] + #[inline(always)] + pub fn is_16x_fractional(&self) -> bool { + **self == SAMPR_A::_16X_FRACTIONAL + } + #[doc = "Checks if the value of the field is `_8X_ARITHMETIC`"] + #[inline(always)] + pub fn is_8x_arithmetic(&self) -> bool { + **self == SAMPR_A::_8X_ARITHMETIC + } + #[doc = "Checks if the value of the field is `_8X_FRACTIONAL`"] + #[inline(always)] + pub fn is_8x_fractional(&self) -> bool { + **self == SAMPR_A::_8X_FRACTIONAL + } + #[doc = "Checks if the value of the field is `_3X_ARITHMETIC`"] + #[inline(always)] + pub fn is_3x_arithmetic(&self) -> bool { + **self == SAMPR_A::_3X_ARITHMETIC + } +} +impl core::ops::Deref for SAMPR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SAMPR` writer - Sample"] +pub struct SAMPR_W<'a> { + w: &'a mut W, +} +impl<'a> SAMPR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SAMPR_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "16x over-sampling using arithmetic baudrate generation"] + #[inline(always)] + pub fn _16x_arithmetic(self) -> &'a mut W { + self.variant(SAMPR_A::_16X_ARITHMETIC) + } + #[doc = "16x over-sampling using fractional baudrate generation"] + #[inline(always)] + pub fn _16x_fractional(self) -> &'a mut W { + self.variant(SAMPR_A::_16X_FRACTIONAL) + } + #[doc = "8x over-sampling using arithmetic baudrate generation"] + #[inline(always)] + pub fn _8x_arithmetic(self) -> &'a mut W { + self.variant(SAMPR_A::_8X_ARITHMETIC) + } + #[doc = "8x over-sampling using fractional baudrate generation"] + #[inline(always)] + pub fn _8x_fractional(self) -> &'a mut W { + self.variant(SAMPR_A::_8X_FRACTIONAL) + } + #[doc = "3x over-sampling using arithmetic baudrate generation"] + #[inline(always)] + pub fn _3x_arithmetic(self) -> &'a mut W { + self.variant(SAMPR_A::_3X_ARITHMETIC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 13)) | ((value as u32 & 0x07) << 13); + self.w + } +} +#[doc = "Transmit Data Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum TXPO_A { + #[doc = "0: SERCOM PAD\\[0\\] +is used for data transmission"] + PAD0 = 0, + #[doc = "1: SERCOM PAD\\[2\\] +is used for data transmission"] + PAD2 = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: TXPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `TXPO` reader - Transmit Data Pinout"] +pub struct TXPO_R(crate::FieldReader); +impl TXPO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TXPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(TXPO_A::PAD0), + 1 => Some(TXPO_A::PAD2), + _ => None, + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == TXPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == TXPO_A::PAD2 + } +} +impl core::ops::Deref for TXPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXPO` writer - Transmit Data Pinout"] +pub struct TXPO_W<'a> { + w: &'a mut W, +} +impl<'a> TXPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TXPO_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "SERCOM PAD\\[0\\] +is used for data transmission"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(TXPO_A::PAD0) + } + #[doc = "SERCOM PAD\\[2\\] +is used for data transmission"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(TXPO_A::PAD2) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Receive Data Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum RXPO_A { + #[doc = "0: SERCOM PAD\\[0\\] +is used for data reception"] + PAD0 = 0, + #[doc = "1: SERCOM PAD\\[1\\] +is used for data reception"] + PAD1 = 1, + #[doc = "2: SERCOM PAD\\[2\\] +is used for data reception"] + PAD2 = 2, + #[doc = "3: SERCOM PAD\\[3\\] +is used for data reception"] + PAD3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RXPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `RXPO` reader - Receive Data Pinout"] +pub struct RXPO_R(crate::FieldReader); +impl RXPO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RXPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RXPO_A { + match self.bits { + 0 => RXPO_A::PAD0, + 1 => RXPO_A::PAD1, + 2 => RXPO_A::PAD2, + 3 => RXPO_A::PAD3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == RXPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD1`"] + #[inline(always)] + pub fn is_pad1(&self) -> bool { + **self == RXPO_A::PAD1 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == RXPO_A::PAD2 + } + #[doc = "Checks if the value of the field is `PAD3`"] + #[inline(always)] + pub fn is_pad3(&self) -> bool { + **self == RXPO_A::PAD3 + } +} +impl core::ops::Deref for RXPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXPO` writer - Receive Data Pinout"] +pub struct RXPO_W<'a> { + w: &'a mut W, +} +impl<'a> RXPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RXPO_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "SERCOM PAD\\[0\\] +is used for data reception"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(RXPO_A::PAD0) + } + #[doc = "SERCOM PAD\\[1\\] +is used for data reception"] + #[inline(always)] + pub fn pad1(self) -> &'a mut W { + self.variant(RXPO_A::PAD1) + } + #[doc = "SERCOM PAD\\[2\\] +is used for data reception"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(RXPO_A::PAD2) + } + #[doc = "SERCOM PAD\\[3\\] +is used for data reception"] + #[inline(always)] + pub fn pad3(self) -> &'a mut W { + self.variant(RXPO_A::PAD3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 20)) | ((value as u32 & 0x03) << 20); + self.w + } +} +#[doc = "Field `SAMPA` reader - Sample Adjustment"] +pub struct SAMPA_R(crate::FieldReader); +impl SAMPA_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SAMPA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SAMPA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SAMPA` writer - Sample Adjustment"] +pub struct SAMPA_W<'a> { + w: &'a mut W, +} +impl<'a> SAMPA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 22)) | ((value as u32 & 0x03) << 22); + self.w + } +} +#[doc = "Frame Format\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FORM_A { + #[doc = "0: USART frame"] + USART_FRAME_NO_PARITY = 0, + #[doc = "1: USART frame with parity"] + USART_FRAME_WITH_PARITY = 1, + #[doc = "2: LIN Master - Break and sync generation"] + USART_FRAME_LIN_MASTER_MODE = 2, + #[doc = "4: Auto-baud - break detection and auto-baud"] + USART_FRAME_AUTO_BAUD_NO_PARITY = 4, + #[doc = "5: Auto-baud - break detection and auto-baud with parity"] + USART_FRAME_AUTO_BAUD_WITH_PARITY = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FORM_A) -> Self { + variant as _ + } +} +#[doc = "Field `FORM` reader - Frame Format"] +pub struct FORM_R(crate::FieldReader); +impl FORM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FORM_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(FORM_A::USART_FRAME_NO_PARITY), + 1 => Some(FORM_A::USART_FRAME_WITH_PARITY), + 2 => Some(FORM_A::USART_FRAME_LIN_MASTER_MODE), + 4 => Some(FORM_A::USART_FRAME_AUTO_BAUD_NO_PARITY), + 5 => Some(FORM_A::USART_FRAME_AUTO_BAUD_WITH_PARITY), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_FRAME_NO_PARITY`"] + #[inline(always)] + pub fn is_usart_frame_no_parity(&self) -> bool { + **self == FORM_A::USART_FRAME_NO_PARITY + } + #[doc = "Checks if the value of the field is `USART_FRAME_WITH_PARITY`"] + #[inline(always)] + pub fn is_usart_frame_with_parity(&self) -> bool { + **self == FORM_A::USART_FRAME_WITH_PARITY + } + #[doc = "Checks if the value of the field is `USART_FRAME_LIN_MASTER_MODE`"] + #[inline(always)] + pub fn is_usart_frame_lin_master_mode(&self) -> bool { + **self == FORM_A::USART_FRAME_LIN_MASTER_MODE + } + #[doc = "Checks if the value of the field is `USART_FRAME_AUTO_BAUD_NO_PARITY`"] + #[inline(always)] + pub fn is_usart_frame_auto_baud_no_parity(&self) -> bool { + **self == FORM_A::USART_FRAME_AUTO_BAUD_NO_PARITY + } + #[doc = "Checks if the value of the field is `USART_FRAME_AUTO_BAUD_WITH_PARITY`"] + #[inline(always)] + pub fn is_usart_frame_auto_baud_with_parity(&self) -> bool { + **self == FORM_A::USART_FRAME_AUTO_BAUD_WITH_PARITY + } +} +impl core::ops::Deref for FORM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FORM` writer - Frame Format"] +pub struct FORM_W<'a> { + w: &'a mut W, +} +impl<'a> FORM_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FORM_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART frame"] + #[inline(always)] + pub fn usart_frame_no_parity(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_NO_PARITY) + } + #[doc = "USART frame with parity"] + #[inline(always)] + pub fn usart_frame_with_parity(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_WITH_PARITY) + } + #[doc = "LIN Master - Break and sync generation"] + #[inline(always)] + pub fn usart_frame_lin_master_mode(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_LIN_MASTER_MODE) + } + #[doc = "Auto-baud - break detection and auto-baud"] + #[inline(always)] + pub fn usart_frame_auto_baud_no_parity(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_AUTO_BAUD_NO_PARITY) + } + #[doc = "Auto-baud - break detection and auto-baud with parity"] + #[inline(always)] + pub fn usart_frame_auto_baud_with_parity(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_AUTO_BAUD_WITH_PARITY) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Communication Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CMODE_A { + #[doc = "0: Asynchronous Communication"] + ASYNC = 0, + #[doc = "1: Synchronous Communication"] + SYNC = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CMODE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CMODE` reader - Communication Mode"] +pub struct CMODE_R(crate::FieldReader); +impl CMODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CMODE_A { + match self.bits { + false => CMODE_A::ASYNC, + true => CMODE_A::SYNC, + } + } + #[doc = "Checks if the value of the field is `ASYNC`"] + #[inline(always)] + pub fn is_async(&self) -> bool { + **self == CMODE_A::ASYNC + } + #[doc = "Checks if the value of the field is `SYNC`"] + #[inline(always)] + pub fn is_sync(&self) -> bool { + **self == CMODE_A::SYNC + } +} +impl core::ops::Deref for CMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMODE` writer - Communication Mode"] +pub struct CMODE_W<'a> { + w: &'a mut W, +} +impl<'a> CMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMODE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Asynchronous Communication"] + #[inline(always)] + pub fn async_(self) -> &'a mut W { + self.variant(CMODE_A::ASYNC) + } + #[doc = "Synchronous Communication"] + #[inline(always)] + pub fn sync(self) -> &'a mut W { + self.variant(CMODE_A::SYNC) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Clock Polarity\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CPOL_A { + #[doc = "0: TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge"] + IDLE_LOW = 0, + #[doc = "1: TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge"] + IDLE_HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CPOL_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CPOL` reader - Clock Polarity"] +pub struct CPOL_R(crate::FieldReader); +impl CPOL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPOL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CPOL_A { + match self.bits { + false => CPOL_A::IDLE_LOW, + true => CPOL_A::IDLE_HIGH, + } + } + #[doc = "Checks if the value of the field is `IDLE_LOW`"] + #[inline(always)] + pub fn is_idle_low(&self) -> bool { + **self == CPOL_A::IDLE_LOW + } + #[doc = "Checks if the value of the field is `IDLE_HIGH`"] + #[inline(always)] + pub fn is_idle_high(&self) -> bool { + **self == CPOL_A::IDLE_HIGH + } +} +impl core::ops::Deref for CPOL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPOL` writer - Clock Polarity"] +pub struct CPOL_W<'a> { + w: &'a mut W, +} +impl<'a> CPOL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CPOL_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge"] + #[inline(always)] + pub fn idle_low(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_LOW) + } + #[doc = "TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge"] + #[inline(always)] + pub fn idle_high(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_HIGH) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29); + self.w + } +} +#[doc = "Data Order\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum DORD_A { + #[doc = "0: MSB is transmitted first"] + MSB = 0, + #[doc = "1: LSB is transmitted first"] + LSB = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DORD_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DORD` reader - Data Order"] +pub struct DORD_R(crate::FieldReader); +impl DORD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DORD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DORD_A { + match self.bits { + false => DORD_A::MSB, + true => DORD_A::LSB, + } + } + #[doc = "Checks if the value of the field is `MSB`"] + #[inline(always)] + pub fn is_msb(&self) -> bool { + **self == DORD_A::MSB + } + #[doc = "Checks if the value of the field is `LSB`"] + #[inline(always)] + pub fn is_lsb(&self) -> bool { + **self == DORD_A::LSB + } +} +impl core::ops::Deref for DORD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DORD` writer - Data Order"] +pub struct DORD_W<'a> { + w: &'a mut W, +} +impl<'a> DORD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DORD_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "MSB is transmitted first"] + #[inline(always)] + pub fn msb(self) -> &'a mut W { + self.variant(DORD_A::MSB) + } + #[doc = "LSB is transmitted first"] + #[inline(always)] + pub fn lsb(self) -> &'a mut W { + self.variant(DORD_A::LSB) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x07) as u8) + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&self) -> IBON_R { + IBON_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bits 13:15 - Sample"] + #[inline(always)] + pub fn sampr(&self) -> SAMPR_R { + SAMPR_R::new(((self.bits >> 13) & 0x07) as u8) + } + #[doc = "Bits 16:17 - Transmit Data Pinout"] + #[inline(always)] + pub fn txpo(&self) -> TXPO_R { + TXPO_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bits 20:21 - Receive Data Pinout"] + #[inline(always)] + pub fn rxpo(&self) -> RXPO_R { + RXPO_R::new(((self.bits >> 20) & 0x03) as u8) + } + #[doc = "Bits 22:23 - Sample Adjustment"] + #[inline(always)] + pub fn sampa(&self) -> SAMPA_R { + SAMPA_R::new(((self.bits >> 22) & 0x03) as u8) + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&self) -> FORM_R { + FORM_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 28 - Communication Mode"] + #[inline(always)] + pub fn cmode(&self) -> CMODE_R { + CMODE_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&self) -> CPOL_R { + CPOL_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&self) -> DORD_R { + DORD_R::new(((self.bits >> 30) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&mut self) -> IBON_W { + IBON_W { w: self } + } + #[doc = "Bits 13:15 - Sample"] + #[inline(always)] + pub fn sampr(&mut self) -> SAMPR_W { + SAMPR_W { w: self } + } + #[doc = "Bits 16:17 - Transmit Data Pinout"] + #[inline(always)] + pub fn txpo(&mut self) -> TXPO_W { + TXPO_W { w: self } + } + #[doc = "Bits 20:21 - Receive Data Pinout"] + #[inline(always)] + pub fn rxpo(&mut self) -> RXPO_W { + RXPO_W { w: self } + } + #[doc = "Bits 22:23 - Sample Adjustment"] + #[inline(always)] + pub fn sampa(&mut self) -> SAMPA_W { + SAMPA_W { w: self } + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&mut self) -> FORM_W { + FORM_W { w: self } + } + #[doc = "Bit 28 - Communication Mode"] + #[inline(always)] + pub fn cmode(&mut self) -> CMODE_W { + CMODE_W { w: self } + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&mut self) -> CPOL_W { + CPOL_W { w: self } + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&mut self) -> DORD_W { + DORD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/sercom0/usart_int/ctrlb.rs b/pac/atsamc20n/src/sercom0/usart_int/ctrlb.rs new file mode 100644 index 000000000000..d556e0c3cfc2 --- /dev/null +++ b/pac/atsamc20n/src/sercom0/usart_int/ctrlb.rs @@ -0,0 +1,651 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Character Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CHSIZE_A { + #[doc = "0: 8 Bits"] + _8_BIT = 0, + #[doc = "1: 9 Bits"] + _9_BIT = 1, + #[doc = "5: 5 Bits"] + _5_BIT = 5, + #[doc = "6: 6 Bits"] + _6_BIT = 6, + #[doc = "7: 7 Bits"] + _7_BIT = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CHSIZE_A) -> Self { + variant as _ + } +} +#[doc = "Field `CHSIZE` reader - Character Size"] +pub struct CHSIZE_R(crate::FieldReader); +impl CHSIZE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CHSIZE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CHSIZE_A::_8_BIT), + 1 => Some(CHSIZE_A::_9_BIT), + 5 => Some(CHSIZE_A::_5_BIT), + 6 => Some(CHSIZE_A::_6_BIT), + 7 => Some(CHSIZE_A::_7_BIT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_8_BIT`"] + #[inline(always)] + pub fn is_8_bit(&self) -> bool { + **self == CHSIZE_A::_8_BIT + } + #[doc = "Checks if the value of the field is `_9_BIT`"] + #[inline(always)] + pub fn is_9_bit(&self) -> bool { + **self == CHSIZE_A::_9_BIT + } + #[doc = "Checks if the value of the field is `_5_BIT`"] + #[inline(always)] + pub fn is_5_bit(&self) -> bool { + **self == CHSIZE_A::_5_BIT + } + #[doc = "Checks if the value of the field is `_6_BIT`"] + #[inline(always)] + pub fn is_6_bit(&self) -> bool { + **self == CHSIZE_A::_6_BIT + } + #[doc = "Checks if the value of the field is `_7_BIT`"] + #[inline(always)] + pub fn is_7_bit(&self) -> bool { + **self == CHSIZE_A::_7_BIT + } +} +impl core::ops::Deref for CHSIZE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHSIZE` writer - Character Size"] +pub struct CHSIZE_W<'a> { + w: &'a mut W, +} +impl<'a> CHSIZE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CHSIZE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8 Bits"] + #[inline(always)] + pub fn _8_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_8_BIT) + } + #[doc = "9 Bits"] + #[inline(always)] + pub fn _9_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_9_BIT) + } + #[doc = "5 Bits"] + #[inline(always)] + pub fn _5_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_5_BIT) + } + #[doc = "6 Bits"] + #[inline(always)] + pub fn _6_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_6_BIT) + } + #[doc = "7 Bits"] + #[inline(always)] + pub fn _7_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_7_BIT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Stop Bit Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SBMODE_A { + #[doc = "0: One Stop Bit"] + _1_BIT = 0, + #[doc = "1: Two Stop Bits"] + _2_BIT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SBMODE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SBMODE` reader - Stop Bit Mode"] +pub struct SBMODE_R(crate::FieldReader); +impl SBMODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SBMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SBMODE_A { + match self.bits { + false => SBMODE_A::_1_BIT, + true => SBMODE_A::_2_BIT, + } + } + #[doc = "Checks if the value of the field is `_1_BIT`"] + #[inline(always)] + pub fn is_1_bit(&self) -> bool { + **self == SBMODE_A::_1_BIT + } + #[doc = "Checks if the value of the field is `_2_BIT`"] + #[inline(always)] + pub fn is_2_bit(&self) -> bool { + **self == SBMODE_A::_2_BIT + } +} +impl core::ops::Deref for SBMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SBMODE` writer - Stop Bit Mode"] +pub struct SBMODE_W<'a> { + w: &'a mut W, +} +impl<'a> SBMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SBMODE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "One Stop Bit"] + #[inline(always)] + pub fn _1_bit(self) -> &'a mut W { + self.variant(SBMODE_A::_1_BIT) + } + #[doc = "Two Stop Bits"] + #[inline(always)] + pub fn _2_bit(self) -> &'a mut W { + self.variant(SBMODE_A::_2_BIT) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `COLDEN` reader - Collision Detection Enable"] +pub struct COLDEN_R(crate::FieldReader); +impl COLDEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COLDEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COLDEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COLDEN` writer - Collision Detection Enable"] +pub struct COLDEN_W<'a> { + w: &'a mut W, +} +impl<'a> COLDEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `SFDE` reader - Start of Frame Detection Enable"] +pub struct SFDE_R(crate::FieldReader); +impl SFDE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SFDE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SFDE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SFDE` writer - Start of Frame Detection Enable"] +pub struct SFDE_W<'a> { + w: &'a mut W, +} +impl<'a> SFDE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `ENC` reader - Encoding Format"] +pub struct ENC_R(crate::FieldReader); +impl ENC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENC` writer - Encoding Format"] +pub struct ENC_W<'a> { + w: &'a mut W, +} +impl<'a> ENC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Parity Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PMODE_A { + #[doc = "0: Even Parity"] + EVEN = 0, + #[doc = "1: Odd Parity"] + ODD = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PMODE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PMODE` reader - Parity Mode"] +pub struct PMODE_R(crate::FieldReader); +impl PMODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PMODE_A { + match self.bits { + false => PMODE_A::EVEN, + true => PMODE_A::ODD, + } + } + #[doc = "Checks if the value of the field is `EVEN`"] + #[inline(always)] + pub fn is_even(&self) -> bool { + **self == PMODE_A::EVEN + } + #[doc = "Checks if the value of the field is `ODD`"] + #[inline(always)] + pub fn is_odd(&self) -> bool { + **self == PMODE_A::ODD + } +} +impl core::ops::Deref for PMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PMODE` writer - Parity Mode"] +pub struct PMODE_W<'a> { + w: &'a mut W, +} +impl<'a> PMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PMODE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Even Parity"] + #[inline(always)] + pub fn even(self) -> &'a mut W { + self.variant(PMODE_A::EVEN) + } + #[doc = "Odd Parity"] + #[inline(always)] + pub fn odd(self) -> &'a mut W { + self.variant(PMODE_A::ODD) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `TXEN` reader - Transmitter Enable"] +pub struct TXEN_R(crate::FieldReader); +impl TXEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXEN` writer - Transmitter Enable"] +pub struct TXEN_W<'a> { + w: &'a mut W, +} +impl<'a> TXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `RXEN` reader - Receiver Enable"] +pub struct RXEN_R(crate::FieldReader); +impl RXEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXEN` writer - Receiver Enable"] +pub struct RXEN_W<'a> { + w: &'a mut W, +} +impl<'a> RXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `LINCMD` reader - LIN Command"] +pub struct LINCMD_R(crate::FieldReader); +impl LINCMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LINCMD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LINCMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LINCMD` writer - LIN Command"] +pub struct LINCMD_W<'a> { + w: &'a mut W, +} +impl<'a> LINCMD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 24)) | ((value as u32 & 0x03) << 24); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&self) -> CHSIZE_R { + CHSIZE_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 6 - Stop Bit Mode"] + #[inline(always)] + pub fn sbmode(&self) -> SBMODE_R { + SBMODE_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 8 - Collision Detection Enable"] + #[inline(always)] + pub fn colden(&self) -> COLDEN_R { + COLDEN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Start of Frame Detection Enable"] + #[inline(always)] + pub fn sfde(&self) -> SFDE_R { + SFDE_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Encoding Format"] + #[inline(always)] + pub fn enc(&self) -> ENC_R { + ENC_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 13 - Parity Mode"] + #[inline(always)] + pub fn pmode(&self) -> PMODE_R { + PMODE_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 16 - Transmitter Enable"] + #[inline(always)] + pub fn txen(&self) -> TXEN_R { + TXEN_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&self) -> RXEN_R { + RXEN_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bits 24:25 - LIN Command"] + #[inline(always)] + pub fn lincmd(&self) -> LINCMD_R { + LINCMD_R::new(((self.bits >> 24) & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&mut self) -> CHSIZE_W { + CHSIZE_W { w: self } + } + #[doc = "Bit 6 - Stop Bit Mode"] + #[inline(always)] + pub fn sbmode(&mut self) -> SBMODE_W { + SBMODE_W { w: self } + } + #[doc = "Bit 8 - Collision Detection Enable"] + #[inline(always)] + pub fn colden(&mut self) -> COLDEN_W { + COLDEN_W { w: self } + } + #[doc = "Bit 9 - Start of Frame Detection Enable"] + #[inline(always)] + pub fn sfde(&mut self) -> SFDE_W { + SFDE_W { w: self } + } + #[doc = "Bit 10 - Encoding Format"] + #[inline(always)] + pub fn enc(&mut self) -> ENC_W { + ENC_W { w: self } + } + #[doc = "Bit 13 - Parity Mode"] + #[inline(always)] + pub fn pmode(&mut self) -> PMODE_W { + PMODE_W { w: self } + } + #[doc = "Bit 16 - Transmitter Enable"] + #[inline(always)] + pub fn txen(&mut self) -> TXEN_W { + TXEN_W { w: self } + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&mut self) -> RXEN_W { + RXEN_W { w: self } + } + #[doc = "Bits 24:25 - LIN Command"] + #[inline(always)] + pub fn lincmd(&mut self) -> LINCMD_W { + LINCMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/sercom0/usart_int/ctrlc.rs b/pac/atsamc20n/src/sercom0/usart_int/ctrlc.rs new file mode 100644 index 000000000000..e2182cc7f768 --- /dev/null +++ b/pac/atsamc20n/src/sercom0/usart_int/ctrlc.rs @@ -0,0 +1,177 @@ +#[doc = "Register `CTRLC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `GTIME` reader - RS485 Guard Time"] +pub struct GTIME_R(crate::FieldReader); +impl GTIME_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + GTIME_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GTIME_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GTIME` writer - RS485 Guard Time"] +pub struct GTIME_W<'a> { + w: &'a mut W, +} +impl<'a> GTIME_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Field `BRKLEN` reader - LIN Master Break Length"] +pub struct BRKLEN_R(crate::FieldReader); +impl BRKLEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BRKLEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BRKLEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BRKLEN` writer - LIN Master Break Length"] +pub struct BRKLEN_W<'a> { + w: &'a mut W, +} +impl<'a> BRKLEN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 8)) | ((value as u32 & 0x03) << 8); + self.w + } +} +#[doc = "Field `HDRDLY` reader - LIN Master Header Delay"] +pub struct HDRDLY_R(crate::FieldReader); +impl HDRDLY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + HDRDLY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HDRDLY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HDRDLY` writer - LIN Master Header Delay"] +pub struct HDRDLY_W<'a> { + w: &'a mut W, +} +impl<'a> HDRDLY_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 10)) | ((value as u32 & 0x03) << 10); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - RS485 Guard Time"] + #[inline(always)] + pub fn gtime(&self) -> GTIME_R { + GTIME_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bits 8:9 - LIN Master Break Length"] + #[inline(always)] + pub fn brklen(&self) -> BRKLEN_R { + BRKLEN_R::new(((self.bits >> 8) & 0x03) as u8) + } + #[doc = "Bits 10:11 - LIN Master Header Delay"] + #[inline(always)] + pub fn hdrdly(&self) -> HDRDLY_R { + HDRDLY_R::new(((self.bits >> 10) & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - RS485 Guard Time"] + #[inline(always)] + pub fn gtime(&mut self) -> GTIME_W { + GTIME_W { w: self } + } + #[doc = "Bits 8:9 - LIN Master Break Length"] + #[inline(always)] + pub fn brklen(&mut self) -> BRKLEN_W { + BRKLEN_W { w: self } + } + #[doc = "Bits 10:11 - LIN Master Header Delay"] + #[inline(always)] + pub fn hdrdly(&mut self) -> HDRDLY_W { + HDRDLY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Control C\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlc](index.html) module"] +pub struct CTRLC_SPEC; +impl crate::RegisterSpec for CTRLC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlc::R](R) reader structure"] +impl crate::Readable for CTRLC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlc::W](W) writer structure"] +impl crate::Writable for CTRLC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLC to value 0"] +impl crate::Resettable for CTRLC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/sercom0/usart_int/data.rs b/pac/atsamc20n/src/sercom0/usart_int/data.rs new file mode 100644 index 000000000000..19d74c337d44 --- /dev/null +++ b/pac/atsamc20n/src/sercom0/usart_int/data.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data Value"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data Value"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01ff) | (value as u16 & 0x01ff); + self.w + } +} +impl R { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new((self.bits & 0x01ff) as u16) + } +} +impl W { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/sercom0/usart_int/dbgctrl.rs b/pac/atsamc20n/src/sercom0/usart_int/dbgctrl.rs new file mode 100644 index 000000000000..0ac5b9c7b902 --- /dev/null +++ b/pac/atsamc20n/src/sercom0/usart_int/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGSTOP` reader - Debug Mode"] +pub struct DBGSTOP_R(crate::FieldReader); +impl DBGSTOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGSTOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGSTOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGSTOP` writer - Debug Mode"] +pub struct DBGSTOP_W<'a> { + w: &'a mut W, +} +impl<'a> DBGSTOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&self) -> DBGSTOP_R { + DBGSTOP_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&mut self) -> DBGSTOP_W { + DBGSTOP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/sercom0/usart_int/intenclr.rs b/pac/atsamc20n/src/sercom0/usart_int/intenclr.rs new file mode 100644 index 000000000000..5ad23ad15636 --- /dev/null +++ b/pac/atsamc20n/src/sercom0/usart_int/intenclr.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Disable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Disable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Disable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Disable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Disable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Disable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RXS` reader - Receive Start Interrupt Disable"] +pub struct RXS_R(crate::FieldReader); +impl RXS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXS` writer - Receive Start Interrupt Disable"] +pub struct RXS_W<'a> { + w: &'a mut W, +} +impl<'a> RXS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CTSIC` reader - Clear To Send Input Change Interrupt Disable"] +pub struct CTSIC_R(crate::FieldReader); +impl CTSIC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTSIC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTSIC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTSIC` writer - Clear To Send Input Change Interrupt Disable"] +pub struct CTSIC_W<'a> { + w: &'a mut W, +} +impl<'a> CTSIC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RXBRK` reader - Break Received Interrupt Disable"] +pub struct RXBRK_R(crate::FieldReader); +impl RXBRK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXBRK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXBRK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXBRK` writer - Break Received Interrupt Disable"] +pub struct RXBRK_W<'a> { + w: &'a mut W, +} +impl<'a> RXBRK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Disable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Disable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Receive Start Interrupt Disable"] + #[inline(always)] + pub fn rxs(&self) -> RXS_R { + RXS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Disable"] + #[inline(always)] + pub fn ctsic(&self) -> CTSIC_R { + CTSIC_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Break Received Interrupt Disable"] + #[inline(always)] + pub fn rxbrk(&self) -> RXBRK_R { + RXBRK_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Receive Start Interrupt Disable"] + #[inline(always)] + pub fn rxs(&mut self) -> RXS_W { + RXS_W { w: self } + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Disable"] + #[inline(always)] + pub fn ctsic(&mut self) -> CTSIC_W { + CTSIC_W { w: self } + } + #[doc = "Bit 5 - Break Received Interrupt Disable"] + #[inline(always)] + pub fn rxbrk(&mut self) -> RXBRK_W { + RXBRK_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/sercom0/usart_int/intenset.rs b/pac/atsamc20n/src/sercom0/usart_int/intenset.rs new file mode 100644 index 000000000000..457f440e13e9 --- /dev/null +++ b/pac/atsamc20n/src/sercom0/usart_int/intenset.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Enable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Enable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Enable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Enable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Enable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Enable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RXS` reader - Receive Start Interrupt Enable"] +pub struct RXS_R(crate::FieldReader); +impl RXS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXS` writer - Receive Start Interrupt Enable"] +pub struct RXS_W<'a> { + w: &'a mut W, +} +impl<'a> RXS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CTSIC` reader - Clear To Send Input Change Interrupt Enable"] +pub struct CTSIC_R(crate::FieldReader); +impl CTSIC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTSIC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTSIC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTSIC` writer - Clear To Send Input Change Interrupt Enable"] +pub struct CTSIC_W<'a> { + w: &'a mut W, +} +impl<'a> CTSIC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RXBRK` reader - Break Received Interrupt Enable"] +pub struct RXBRK_R(crate::FieldReader); +impl RXBRK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXBRK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXBRK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXBRK` writer - Break Received Interrupt Enable"] +pub struct RXBRK_W<'a> { + w: &'a mut W, +} +impl<'a> RXBRK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Receive Start Interrupt Enable"] + #[inline(always)] + pub fn rxs(&self) -> RXS_R { + RXS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Enable"] + #[inline(always)] + pub fn ctsic(&self) -> CTSIC_R { + CTSIC_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Break Received Interrupt Enable"] + #[inline(always)] + pub fn rxbrk(&self) -> RXBRK_R { + RXBRK_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Receive Start Interrupt Enable"] + #[inline(always)] + pub fn rxs(&mut self) -> RXS_W { + RXS_W { w: self } + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Enable"] + #[inline(always)] + pub fn ctsic(&mut self) -> CTSIC_W { + CTSIC_W { w: self } + } + #[doc = "Bit 5 - Break Received Interrupt Enable"] + #[inline(always)] + pub fn rxbrk(&mut self) -> RXBRK_W { + RXBRK_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/sercom0/usart_int/intflag.rs b/pac/atsamc20n/src/sercom0/usart_int/intflag.rs new file mode 100644 index 000000000000..a6a26321b8c4 --- /dev/null +++ b/pac/atsamc20n/src/sercom0/usart_int/intflag.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RXS` reader - Receive Start Interrupt"] +pub struct RXS_R(crate::FieldReader); +impl RXS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXS` writer - Receive Start Interrupt"] +pub struct RXS_W<'a> { + w: &'a mut W, +} +impl<'a> RXS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CTSIC` reader - Clear To Send Input Change Interrupt"] +pub struct CTSIC_R(crate::FieldReader); +impl CTSIC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTSIC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTSIC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTSIC` writer - Clear To Send Input Change Interrupt"] +pub struct CTSIC_W<'a> { + w: &'a mut W, +} +impl<'a> CTSIC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RXBRK` reader - Break Received Interrupt"] +pub struct RXBRK_R(crate::FieldReader); +impl RXBRK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXBRK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXBRK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXBRK` writer - Break Received Interrupt"] +pub struct RXBRK_W<'a> { + w: &'a mut W, +} +impl<'a> RXBRK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Receive Start Interrupt"] + #[inline(always)] + pub fn rxs(&self) -> RXS_R { + RXS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt"] + #[inline(always)] + pub fn ctsic(&self) -> CTSIC_R { + CTSIC_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Break Received Interrupt"] + #[inline(always)] + pub fn rxbrk(&self) -> RXBRK_R { + RXBRK_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Receive Start Interrupt"] + #[inline(always)] + pub fn rxs(&mut self) -> RXS_W { + RXS_W { w: self } + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt"] + #[inline(always)] + pub fn ctsic(&mut self) -> CTSIC_W { + CTSIC_W { w: self } + } + #[doc = "Bit 5 - Break Received Interrupt"] + #[inline(always)] + pub fn rxbrk(&mut self) -> RXBRK_W { + RXBRK_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/sercom0/usart_int/rxpl.rs b/pac/atsamc20n/src/sercom0/usart_int/rxpl.rs new file mode 100644 index 000000000000..324cbac371c1 --- /dev/null +++ b/pac/atsamc20n/src/sercom0/usart_int/rxpl.rs @@ -0,0 +1,103 @@ +#[doc = "Register `RXPL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RXPL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RXPL` reader - Receive Pulse Length"] +pub struct RXPL_R(crate::FieldReader); +impl RXPL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RXPL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXPL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXPL` writer - Receive Pulse Length"] +pub struct RXPL_W<'a> { + w: &'a mut W, +} +impl<'a> RXPL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Receive Pulse Length"] + #[inline(always)] + pub fn rxpl(&self) -> RXPL_R { + RXPL_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Receive Pulse Length"] + #[inline(always)] + pub fn rxpl(&mut self) -> RXPL_W { + RXPL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Receive Pulse Length\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxpl](index.html) module"] +pub struct RXPL_SPEC; +impl crate::RegisterSpec for RXPL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [rxpl::R](R) reader structure"] +impl crate::Readable for RXPL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rxpl::W](W) writer structure"] +impl crate::Writable for RXPL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RXPL to value 0"] +impl crate::Resettable for RXPL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/sercom0/usart_int/status.rs b/pac/atsamc20n/src/sercom0/usart_int/status.rs new file mode 100644 index 000000000000..1a92018a359b --- /dev/null +++ b/pac/atsamc20n/src/sercom0/usart_int/status.rs @@ -0,0 +1,395 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PERR` reader - Parity Error"] +pub struct PERR_R(crate::FieldReader); +impl PERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERR` writer - Parity Error"] +pub struct PERR_W<'a> { + w: &'a mut W, +} +impl<'a> PERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `FERR` reader - Frame Error"] +pub struct FERR_R(crate::FieldReader); +impl FERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FERR` writer - Frame Error"] +pub struct FERR_W<'a> { + w: &'a mut W, +} +impl<'a> FERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `BUFOVF` reader - Buffer Overflow"] +pub struct BUFOVF_R(crate::FieldReader); +impl BUFOVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUFOVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUFOVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUFOVF` writer - Buffer Overflow"] +pub struct BUFOVF_W<'a> { + w: &'a mut W, +} +impl<'a> BUFOVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CTS` reader - Clear To Send"] +pub struct CTS_R(crate::FieldReader); +impl CTS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTS` writer - Clear To Send"] +pub struct CTS_W<'a> { + w: &'a mut W, +} +impl<'a> CTS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ISF` reader - Inconsistent Sync Field"] +pub struct ISF_R(crate::FieldReader); +impl ISF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ISF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ISF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ISF` writer - Inconsistent Sync Field"] +pub struct ISF_W<'a> { + w: &'a mut W, +} +impl<'a> ISF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `COLL` reader - Collision Detected"] +pub struct COLL_R(crate::FieldReader); +impl COLL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COLL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COLL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COLL` writer - Collision Detected"] +pub struct COLL_W<'a> { + w: &'a mut W, +} +impl<'a> COLL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `TXE` reader - Transmitter Empty"] +pub struct TXE_R(crate::FieldReader); +impl TXE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXE` writer - Transmitter Empty"] +pub struct TXE_W<'a> { + w: &'a mut W, +} +impl<'a> TXE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - Parity Error"] + #[inline(always)] + pub fn perr(&self) -> PERR_R { + PERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Frame Error"] + #[inline(always)] + pub fn ferr(&self) -> FERR_R { + FERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&self) -> BUFOVF_R { + BUFOVF_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Clear To Send"] + #[inline(always)] + pub fn cts(&self) -> CTS_R { + CTS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Inconsistent Sync Field"] + #[inline(always)] + pub fn isf(&self) -> ISF_R { + ISF_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Collision Detected"] + #[inline(always)] + pub fn coll(&self) -> COLL_R { + COLL_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Transmitter Empty"] + #[inline(always)] + pub fn txe(&self) -> TXE_R { + TXE_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Parity Error"] + #[inline(always)] + pub fn perr(&mut self) -> PERR_W { + PERR_W { w: self } + } + #[doc = "Bit 1 - Frame Error"] + #[inline(always)] + pub fn ferr(&mut self) -> FERR_W { + FERR_W { w: self } + } + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&mut self) -> BUFOVF_W { + BUFOVF_W { w: self } + } + #[doc = "Bit 3 - Clear To Send"] + #[inline(always)] + pub fn cts(&mut self) -> CTS_W { + CTS_W { w: self } + } + #[doc = "Bit 4 - Inconsistent Sync Field"] + #[inline(always)] + pub fn isf(&mut self) -> ISF_W { + ISF_W { w: self } + } + #[doc = "Bit 5 - Collision Detected"] + #[inline(always)] + pub fn coll(&mut self) -> COLL_W { + COLL_W { w: self } + } + #[doc = "Bit 6 - Transmitter Empty"] + #[inline(always)] + pub fn txe(&mut self) -> TXE_W { + TXE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/sercom0/usart_int/syncbusy.rs b/pac/atsamc20n/src/sercom0/usart_int/syncbusy.rs new file mode 100644 index 000000000000..5dea9a5a7bab --- /dev/null +++ b/pac/atsamc20n/src/sercom0/usart_int/syncbusy.rs @@ -0,0 +1,93 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - SERCOM Enable Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLB` reader - CTRLB Synchronization Busy"] +pub struct CTRLB_R(crate::FieldReader); +impl CTRLB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM Enable Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - CTRLB Synchronization Busy"] + #[inline(always)] + pub fn ctrlb(&self) -> CTRLB_R { + CTRLB_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +#[doc = "USART_INT Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/supc.rs b/pac/atsamc20n/src/supc.rs new file mode 100644 index 000000000000..0ad1d125bfd9 --- /dev/null +++ b/pac/atsamc20n/src/supc.rs @@ -0,0 +1,53 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x04 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x08 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x0c - Power and Clocks Status"] + pub status: crate::Reg, + #[doc = "0x10 - BODVDD Control"] + pub bodvdd: crate::Reg, + _reserved5: [u8; 0x04], + #[doc = "0x18 - VREG Control"] + pub vreg: crate::Reg, + #[doc = "0x1c - VREF Control"] + pub vref: crate::Reg, + #[doc = "0x20 - VREG33 Control"] + pub vreg33: crate::Reg, +} +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Power and Clocks Status"] +pub mod status; +#[doc = "BODVDD register accessor: an alias for `Reg`"] +pub type BODVDD = crate::Reg; +#[doc = "BODVDD Control"] +pub mod bodvdd; +#[doc = "VREG register accessor: an alias for `Reg`"] +pub type VREG = crate::Reg; +#[doc = "VREG Control"] +pub mod vreg; +#[doc = "VREF register accessor: an alias for `Reg`"] +pub type VREF = crate::Reg; +#[doc = "VREF Control"] +pub mod vref; +#[doc = "VREG33 register accessor: an alias for `Reg`"] +pub type VREG33 = crate::Reg; +#[doc = "VREG33 Control"] +pub mod vreg33; diff --git a/pac/atsamc20n/src/supc/bodvdd.rs b/pac/atsamc20n/src/supc/bodvdd.rs new file mode 100644 index 000000000000..f5cbfffb6453 --- /dev/null +++ b/pac/atsamc20n/src/supc/bodvdd.rs @@ -0,0 +1,705 @@ +#[doc = "Register `BODVDD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BODVDD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `HYST` reader - Hysteresis Enable"] +pub struct HYST_R(crate::FieldReader); +impl HYST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HYST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HYST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HYST` writer - Hysteresis Enable"] +pub struct HYST_W<'a> { + w: &'a mut W, +} +impl<'a> HYST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Action when Threshold Crossed\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum ACTION_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: The BODVDD generates a reset"] + RESET = 1, + #[doc = "2: The BODVDD generates an interrupt"] + INT = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: ACTION_A) -> Self { + variant as _ + } +} +#[doc = "Field `ACTION` reader - Action when Threshold Crossed"] +pub struct ACTION_R(crate::FieldReader); +impl ACTION_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ACTION_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(ACTION_A::NONE), + 1 => Some(ACTION_A::RESET), + 2 => Some(ACTION_A::INT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == ACTION_A::NONE + } + #[doc = "Checks if the value of the field is `RESET`"] + #[inline(always)] + pub fn is_reset(&self) -> bool { + **self == ACTION_A::RESET + } + #[doc = "Checks if the value of the field is `INT`"] + #[inline(always)] + pub fn is_int(&self) -> bool { + **self == ACTION_A::INT + } +} +impl core::ops::Deref for ACTION_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ACTION` writer - Action when Threshold Crossed"] +pub struct ACTION_W<'a> { + w: &'a mut W, +} +impl<'a> ACTION_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: ACTION_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(ACTION_A::NONE) + } + #[doc = "The BODVDD generates a reset"] + #[inline(always)] + pub fn reset(self) -> &'a mut W { + self.variant(ACTION_A::RESET) + } + #[doc = "The BODVDD generates an interrupt"] + #[inline(always)] + pub fn int(self) -> &'a mut W { + self.variant(ACTION_A::INT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 3)) | ((value as u32 & 0x03) << 3); + self.w + } +} +#[doc = "Field `STDBYCFG` reader - Configuration in Standby mode"] +pub struct STDBYCFG_R(crate::FieldReader); +impl STDBYCFG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STDBYCFG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STDBYCFG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STDBYCFG` writer - Configuration in Standby mode"] +pub struct STDBYCFG_W<'a> { + w: &'a mut W, +} +impl<'a> STDBYCFG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ACTCFG` reader - Configuration in Active mode"] +pub struct ACTCFG_R(crate::FieldReader); +impl ACTCFG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ACTCFG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ACTCFG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ACTCFG` writer - Configuration in Active mode"] +pub struct ACTCFG_W<'a> { + w: &'a mut W, +} +impl<'a> ACTCFG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Prescaler Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PSEL_A { + #[doc = "0: Divide clock by 2"] + DIV2 = 0, + #[doc = "1: Divide clock by 4"] + DIV4 = 1, + #[doc = "2: Divide clock by 8"] + DIV8 = 2, + #[doc = "3: Divide clock by 16"] + DIV16 = 3, + #[doc = "4: Divide clock by 32"] + DIV32 = 4, + #[doc = "5: Divide clock by 64"] + DIV64 = 5, + #[doc = "6: Divide clock by 128"] + DIV128 = 6, + #[doc = "7: Divide clock by 256"] + DIV256 = 7, + #[doc = "8: Divide clock by 512"] + DIV512 = 8, + #[doc = "9: Divide clock by 1024"] + DIV1024 = 9, + #[doc = "10: Divide clock by 2048"] + DIV2048 = 10, + #[doc = "11: Divide clock by 4096"] + DIV4096 = 11, + #[doc = "12: Divide clock by 8192"] + DIV8192 = 12, + #[doc = "13: Divide clock by 16384"] + DIV16384 = 13, + #[doc = "14: Divide clock by 32768"] + DIV32768 = 14, + #[doc = "15: Divide clock by 65536"] + DIV65536 = 15, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `PSEL` reader - Prescaler Select"] +pub struct PSEL_R(crate::FieldReader); +impl PSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PSEL_A { + match self.bits { + 0 => PSEL_A::DIV2, + 1 => PSEL_A::DIV4, + 2 => PSEL_A::DIV8, + 3 => PSEL_A::DIV16, + 4 => PSEL_A::DIV32, + 5 => PSEL_A::DIV64, + 6 => PSEL_A::DIV128, + 7 => PSEL_A::DIV256, + 8 => PSEL_A::DIV512, + 9 => PSEL_A::DIV1024, + 10 => PSEL_A::DIV2048, + 11 => PSEL_A::DIV4096, + 12 => PSEL_A::DIV8192, + 13 => PSEL_A::DIV16384, + 14 => PSEL_A::DIV32768, + 15 => PSEL_A::DIV65536, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PSEL_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PSEL_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PSEL_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PSEL_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == PSEL_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PSEL_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == PSEL_A::DIV128 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PSEL_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV512`"] + #[inline(always)] + pub fn is_div512(&self) -> bool { + **self == PSEL_A::DIV512 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PSEL_A::DIV1024 + } + #[doc = "Checks if the value of the field is `DIV2048`"] + #[inline(always)] + pub fn is_div2048(&self) -> bool { + **self == PSEL_A::DIV2048 + } + #[doc = "Checks if the value of the field is `DIV4096`"] + #[inline(always)] + pub fn is_div4096(&self) -> bool { + **self == PSEL_A::DIV4096 + } + #[doc = "Checks if the value of the field is `DIV8192`"] + #[inline(always)] + pub fn is_div8192(&self) -> bool { + **self == PSEL_A::DIV8192 + } + #[doc = "Checks if the value of the field is `DIV16384`"] + #[inline(always)] + pub fn is_div16384(&self) -> bool { + **self == PSEL_A::DIV16384 + } + #[doc = "Checks if the value of the field is `DIV32768`"] + #[inline(always)] + pub fn is_div32768(&self) -> bool { + **self == PSEL_A::DIV32768 + } + #[doc = "Checks if the value of the field is `DIV65536`"] + #[inline(always)] + pub fn is_div65536(&self) -> bool { + **self == PSEL_A::DIV65536 + } +} +impl core::ops::Deref for PSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PSEL` writer - Prescaler Select"] +pub struct PSEL_W<'a> { + w: &'a mut W, +} +impl<'a> PSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PSEL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Divide clock by 2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PSEL_A::DIV2) + } + #[doc = "Divide clock by 4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PSEL_A::DIV4) + } + #[doc = "Divide clock by 8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PSEL_A::DIV8) + } + #[doc = "Divide clock by 16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PSEL_A::DIV16) + } + #[doc = "Divide clock by 32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(PSEL_A::DIV32) + } + #[doc = "Divide clock by 64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PSEL_A::DIV64) + } + #[doc = "Divide clock by 128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(PSEL_A::DIV128) + } + #[doc = "Divide clock by 256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PSEL_A::DIV256) + } + #[doc = "Divide clock by 512"] + #[inline(always)] + pub fn div512(self) -> &'a mut W { + self.variant(PSEL_A::DIV512) + } + #[doc = "Divide clock by 1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PSEL_A::DIV1024) + } + #[doc = "Divide clock by 2048"] + #[inline(always)] + pub fn div2048(self) -> &'a mut W { + self.variant(PSEL_A::DIV2048) + } + #[doc = "Divide clock by 4096"] + #[inline(always)] + pub fn div4096(self) -> &'a mut W { + self.variant(PSEL_A::DIV4096) + } + #[doc = "Divide clock by 8192"] + #[inline(always)] + pub fn div8192(self) -> &'a mut W { + self.variant(PSEL_A::DIV8192) + } + #[doc = "Divide clock by 16384"] + #[inline(always)] + pub fn div16384(self) -> &'a mut W { + self.variant(PSEL_A::DIV16384) + } + #[doc = "Divide clock by 32768"] + #[inline(always)] + pub fn div32768(self) -> &'a mut W { + self.variant(PSEL_A::DIV32768) + } + #[doc = "Divide clock by 65536"] + #[inline(always)] + pub fn div65536(self) -> &'a mut W { + self.variant(PSEL_A::DIV65536) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 12)) | ((value as u32 & 0x0f) << 12); + self.w + } +} +#[doc = "Field `LEVEL` reader - Threshold Level for VDD"] +pub struct LEVEL_R(crate::FieldReader); +impl LEVEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LEVEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LEVEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LEVEL` writer - Threshold Level for VDD"] +pub struct LEVEL_W<'a> { + w: &'a mut W, +} +impl<'a> LEVEL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 16)) | ((value as u32 & 0x3f) << 16); + self.w + } +} +impl R { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Hysteresis Enable"] + #[inline(always)] + pub fn hyst(&self) -> HYST_R { + HYST_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 3:4 - Action when Threshold Crossed"] + #[inline(always)] + pub fn action(&self) -> ACTION_R { + ACTION_R::new(((self.bits >> 3) & 0x03) as u8) + } + #[doc = "Bit 5 - Configuration in Standby mode"] + #[inline(always)] + pub fn stdbycfg(&self) -> STDBYCFG_R { + STDBYCFG_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 8 - Configuration in Active mode"] + #[inline(always)] + pub fn actcfg(&self) -> ACTCFG_R { + ACTCFG_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bits 12:15 - Prescaler Select"] + #[inline(always)] + pub fn psel(&self) -> PSEL_R { + PSEL_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:21 - Threshold Level for VDD"] + #[inline(always)] + pub fn level(&self) -> LEVEL_R { + LEVEL_R::new(((self.bits >> 16) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - Hysteresis Enable"] + #[inline(always)] + pub fn hyst(&mut self) -> HYST_W { + HYST_W { w: self } + } + #[doc = "Bits 3:4 - Action when Threshold Crossed"] + #[inline(always)] + pub fn action(&mut self) -> ACTION_W { + ACTION_W { w: self } + } + #[doc = "Bit 5 - Configuration in Standby mode"] + #[inline(always)] + pub fn stdbycfg(&mut self) -> STDBYCFG_W { + STDBYCFG_W { w: self } + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 8 - Configuration in Active mode"] + #[inline(always)] + pub fn actcfg(&mut self) -> ACTCFG_W { + ACTCFG_W { w: self } + } + #[doc = "Bits 12:15 - Prescaler Select"] + #[inline(always)] + pub fn psel(&mut self) -> PSEL_W { + PSEL_W { w: self } + } + #[doc = "Bits 16:21 - Threshold Level for VDD"] + #[inline(always)] + pub fn level(&mut self) -> LEVEL_W { + LEVEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "BODVDD Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [bodvdd](index.html) module"] +pub struct BODVDD_SPEC; +impl crate::RegisterSpec for BODVDD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [bodvdd::R](R) reader structure"] +impl crate::Readable for BODVDD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [bodvdd::W](W) writer structure"] +impl crate::Writable for BODVDD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BODVDD to value 0"] +impl crate::Resettable for BODVDD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/supc/intenclr.rs b/pac/atsamc20n/src/supc/intenclr.rs new file mode 100644 index 000000000000..555165e5dcb2 --- /dev/null +++ b/pac/atsamc20n/src/supc/intenclr.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BODVDDRDY` reader - BODVDD Ready"] +pub struct BODVDDRDY_R(crate::FieldReader); +impl BODVDDRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODVDDRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODVDDRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODVDDRDY` writer - BODVDD Ready"] +pub struct BODVDDRDY_W<'a> { + w: &'a mut W, +} +impl<'a> BODVDDRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `BODVDDDET` reader - BODVDD Detection"] +pub struct BODVDDDET_R(crate::FieldReader); +impl BODVDDDET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODVDDDET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODVDDDET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODVDDDET` writer - BODVDD Detection"] +pub struct BODVDDDET_W<'a> { + w: &'a mut W, +} +impl<'a> BODVDDDET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `BVDDSRDY` reader - BODVDD Synchronization Ready"] +pub struct BVDDSRDY_R(crate::FieldReader); +impl BVDDSRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BVDDSRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BVDDSRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BVDDSRDY` writer - BODVDD Synchronization Ready"] +pub struct BVDDSRDY_W<'a> { + w: &'a mut W, +} +impl<'a> BVDDSRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `VREG33RDY` reader - VREG33 Ready"] +pub struct VREG33RDY_R(crate::FieldReader); +impl VREG33RDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + VREG33RDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VREG33RDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VREG33RDY` writer - VREG33 Ready"] +pub struct VREG33RDY_W<'a> { + w: &'a mut W, +} +impl<'a> VREG33RDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - BODVDD Ready"] + #[inline(always)] + pub fn bodvddrdy(&self) -> BODVDDRDY_R { + BODVDDRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - BODVDD Detection"] + #[inline(always)] + pub fn bodvdddet(&self) -> BODVDDDET_R { + BODVDDDET_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - BODVDD Synchronization Ready"] + #[inline(always)] + pub fn bvddsrdy(&self) -> BVDDSRDY_R { + BVDDSRDY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 6 - VREG33 Ready"] + #[inline(always)] + pub fn vreg33rdy(&self) -> VREG33RDY_R { + VREG33RDY_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - BODVDD Ready"] + #[inline(always)] + pub fn bodvddrdy(&mut self) -> BODVDDRDY_W { + BODVDDRDY_W { w: self } + } + #[doc = "Bit 1 - BODVDD Detection"] + #[inline(always)] + pub fn bodvdddet(&mut self) -> BODVDDDET_W { + BODVDDDET_W { w: self } + } + #[doc = "Bit 2 - BODVDD Synchronization Ready"] + #[inline(always)] + pub fn bvddsrdy(&mut self) -> BVDDSRDY_W { + BVDDSRDY_W { w: self } + } + #[doc = "Bit 6 - VREG33 Ready"] + #[inline(always)] + pub fn vreg33rdy(&mut self) -> VREG33RDY_W { + VREG33RDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/supc/intenset.rs b/pac/atsamc20n/src/supc/intenset.rs new file mode 100644 index 000000000000..a0adfbaffa74 --- /dev/null +++ b/pac/atsamc20n/src/supc/intenset.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BODVDDRDY` reader - BODVDD Ready"] +pub struct BODVDDRDY_R(crate::FieldReader); +impl BODVDDRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODVDDRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODVDDRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODVDDRDY` writer - BODVDD Ready"] +pub struct BODVDDRDY_W<'a> { + w: &'a mut W, +} +impl<'a> BODVDDRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `BODVDDDET` reader - BODVDD Detection"] +pub struct BODVDDDET_R(crate::FieldReader); +impl BODVDDDET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODVDDDET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODVDDDET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODVDDDET` writer - BODVDD Detection"] +pub struct BODVDDDET_W<'a> { + w: &'a mut W, +} +impl<'a> BODVDDDET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `BVDDSRDY` reader - BODVDD Synchronization Ready"] +pub struct BVDDSRDY_R(crate::FieldReader); +impl BVDDSRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BVDDSRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BVDDSRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BVDDSRDY` writer - BODVDD Synchronization Ready"] +pub struct BVDDSRDY_W<'a> { + w: &'a mut W, +} +impl<'a> BVDDSRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `VREG33RDY` reader - VREG33 Ready"] +pub struct VREG33RDY_R(crate::FieldReader); +impl VREG33RDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + VREG33RDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VREG33RDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VREG33RDY` writer - VREG33 Ready"] +pub struct VREG33RDY_W<'a> { + w: &'a mut W, +} +impl<'a> VREG33RDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - BODVDD Ready"] + #[inline(always)] + pub fn bodvddrdy(&self) -> BODVDDRDY_R { + BODVDDRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - BODVDD Detection"] + #[inline(always)] + pub fn bodvdddet(&self) -> BODVDDDET_R { + BODVDDDET_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - BODVDD Synchronization Ready"] + #[inline(always)] + pub fn bvddsrdy(&self) -> BVDDSRDY_R { + BVDDSRDY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 6 - VREG33 Ready"] + #[inline(always)] + pub fn vreg33rdy(&self) -> VREG33RDY_R { + VREG33RDY_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - BODVDD Ready"] + #[inline(always)] + pub fn bodvddrdy(&mut self) -> BODVDDRDY_W { + BODVDDRDY_W { w: self } + } + #[doc = "Bit 1 - BODVDD Detection"] + #[inline(always)] + pub fn bodvdddet(&mut self) -> BODVDDDET_W { + BODVDDDET_W { w: self } + } + #[doc = "Bit 2 - BODVDD Synchronization Ready"] + #[inline(always)] + pub fn bvddsrdy(&mut self) -> BVDDSRDY_W { + BVDDSRDY_W { w: self } + } + #[doc = "Bit 6 - VREG33 Ready"] + #[inline(always)] + pub fn vreg33rdy(&mut self) -> VREG33RDY_W { + VREG33RDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/supc/intflag.rs b/pac/atsamc20n/src/supc/intflag.rs new file mode 100644 index 000000000000..ae4c2e125b6f --- /dev/null +++ b/pac/atsamc20n/src/supc/intflag.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BODVDDRDY` reader - BODVDD Ready"] +pub struct BODVDDRDY_R(crate::FieldReader); +impl BODVDDRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODVDDRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODVDDRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODVDDRDY` writer - BODVDD Ready"] +pub struct BODVDDRDY_W<'a> { + w: &'a mut W, +} +impl<'a> BODVDDRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `BODVDDDET` reader - BODVDD Detection"] +pub struct BODVDDDET_R(crate::FieldReader); +impl BODVDDDET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODVDDDET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODVDDDET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODVDDDET` writer - BODVDD Detection"] +pub struct BODVDDDET_W<'a> { + w: &'a mut W, +} +impl<'a> BODVDDDET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `BVDDSRDY` reader - BODVDD Synchronization Ready"] +pub struct BVDDSRDY_R(crate::FieldReader); +impl BVDDSRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BVDDSRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BVDDSRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BVDDSRDY` writer - BODVDD Synchronization Ready"] +pub struct BVDDSRDY_W<'a> { + w: &'a mut W, +} +impl<'a> BVDDSRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `VREG33RDY` reader - VREG33 Ready"] +pub struct VREG33RDY_R(crate::FieldReader); +impl VREG33RDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + VREG33RDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VREG33RDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VREG33RDY` writer - VREG33 Ready"] +pub struct VREG33RDY_W<'a> { + w: &'a mut W, +} +impl<'a> VREG33RDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - BODVDD Ready"] + #[inline(always)] + pub fn bodvddrdy(&self) -> BODVDDRDY_R { + BODVDDRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - BODVDD Detection"] + #[inline(always)] + pub fn bodvdddet(&self) -> BODVDDDET_R { + BODVDDDET_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - BODVDD Synchronization Ready"] + #[inline(always)] + pub fn bvddsrdy(&self) -> BVDDSRDY_R { + BVDDSRDY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 6 - VREG33 Ready"] + #[inline(always)] + pub fn vreg33rdy(&self) -> VREG33RDY_R { + VREG33RDY_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - BODVDD Ready"] + #[inline(always)] + pub fn bodvddrdy(&mut self) -> BODVDDRDY_W { + BODVDDRDY_W { w: self } + } + #[doc = "Bit 1 - BODVDD Detection"] + #[inline(always)] + pub fn bodvdddet(&mut self) -> BODVDDDET_W { + BODVDDDET_W { w: self } + } + #[doc = "Bit 2 - BODVDD Synchronization Ready"] + #[inline(always)] + pub fn bvddsrdy(&mut self) -> BVDDSRDY_W { + BVDDSRDY_W { w: self } + } + #[doc = "Bit 6 - VREG33 Ready"] + #[inline(always)] + pub fn vreg33rdy(&mut self) -> VREG33RDY_W { + VREG33RDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/supc/status.rs b/pac/atsamc20n/src/supc/status.rs new file mode 100644 index 000000000000..b15a68212223 --- /dev/null +++ b/pac/atsamc20n/src/supc/status.rs @@ -0,0 +1,113 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `BODVDDRDY` reader - BODVDD Ready"] +pub struct BODVDDRDY_R(crate::FieldReader); +impl BODVDDRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODVDDRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODVDDRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODVDDDET` reader - BODVDD Detection"] +pub struct BODVDDDET_R(crate::FieldReader); +impl BODVDDDET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODVDDDET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODVDDDET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BVDDSRDY` reader - BODVDD Synchronization Ready"] +pub struct BVDDSRDY_R(crate::FieldReader); +impl BVDDSRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BVDDSRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BVDDSRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VREG33RDY` reader - VREG33 Ready"] +pub struct VREG33RDY_R(crate::FieldReader); +impl VREG33RDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + VREG33RDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VREG33RDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - BODVDD Ready"] + #[inline(always)] + pub fn bodvddrdy(&self) -> BODVDDRDY_R { + BODVDDRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - BODVDD Detection"] + #[inline(always)] + pub fn bodvdddet(&self) -> BODVDDDET_R { + BODVDDDET_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - BODVDD Synchronization Ready"] + #[inline(always)] + pub fn bvddsrdy(&self) -> BVDDSRDY_R { + BVDDSRDY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 6 - VREG33 Ready"] + #[inline(always)] + pub fn vreg33rdy(&self) -> VREG33RDY_R { + VREG33RDY_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +#[doc = "Power and Clocks Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/supc/vref.rs b/pac/atsamc20n/src/supc/vref.rs new file mode 100644 index 000000000000..55e25e0ceb9f --- /dev/null +++ b/pac/atsamc20n/src/supc/vref.rs @@ -0,0 +1,353 @@ +#[doc = "Register `VREF` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `VREF` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TSEN` reader - Temperature Sensor Output Enable"] +pub struct TSEN_R(crate::FieldReader); +impl TSEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSEN` writer - Temperature Sensor Output Enable"] +pub struct TSEN_W<'a> { + w: &'a mut W, +} +impl<'a> TSEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `VREFOE` reader - Voltage Reference Output Enable"] +pub struct VREFOE_R(crate::FieldReader); +impl VREFOE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + VREFOE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VREFOE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VREFOE` writer - Voltage Reference Output Enable"] +pub struct VREFOE_W<'a> { + w: &'a mut W, +} +impl<'a> VREFOE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - On Demand Control"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - On Demand Control"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Voltage Reference Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SEL_A { + #[doc = "0: 1.024V voltage reference typical value"] + _1V024 = 0, + #[doc = "2: 2.048V voltage reference typical value"] + _2V048 = 2, + #[doc = "3: 4.096V voltage reference typical value"] + _4V096 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `SEL` reader - Voltage Reference Selection"] +pub struct SEL_R(crate::FieldReader); +impl SEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEL_A::_1V024), + 2 => Some(SEL_A::_2V048), + 3 => Some(SEL_A::_4V096), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_1V024`"] + #[inline(always)] + pub fn is_1v024(&self) -> bool { + **self == SEL_A::_1V024 + } + #[doc = "Checks if the value of the field is `_2V048`"] + #[inline(always)] + pub fn is_2v048(&self) -> bool { + **self == SEL_A::_2V048 + } + #[doc = "Checks if the value of the field is `_4V096`"] + #[inline(always)] + pub fn is_4v096(&self) -> bool { + **self == SEL_A::_4V096 + } +} +impl core::ops::Deref for SEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEL` writer - Voltage Reference Selection"] +pub struct SEL_W<'a> { + w: &'a mut W, +} +impl<'a> SEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SEL_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "1.024V voltage reference typical value"] + #[inline(always)] + pub fn _1v024(self) -> &'a mut W { + self.variant(SEL_A::_1V024) + } + #[doc = "2.048V voltage reference typical value"] + #[inline(always)] + pub fn _2v048(self) -> &'a mut W { + self.variant(SEL_A::_2V048) + } + #[doc = "4.096V voltage reference typical value"] + #[inline(always)] + pub fn _4v096(self) -> &'a mut W { + self.variant(SEL_A::_4V096) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 16)) | ((value as u32 & 0x0f) << 16); + self.w + } +} +impl R { + #[doc = "Bit 1 - Temperature Sensor Output Enable"] + #[inline(always)] + pub fn tsen(&self) -> TSEN_R { + TSEN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Voltage Reference Output Enable"] + #[inline(always)] + pub fn vrefoe(&self) -> VREFOE_R { + VREFOE_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 16:19 - Voltage Reference Selection"] + #[inline(always)] + pub fn sel(&self) -> SEL_R { + SEL_R::new(((self.bits >> 16) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bit 1 - Temperature Sensor Output Enable"] + #[inline(always)] + pub fn tsen(&mut self) -> TSEN_W { + TSEN_W { w: self } + } + #[doc = "Bit 2 - Voltage Reference Output Enable"] + #[inline(always)] + pub fn vrefoe(&mut self) -> VREFOE_W { + VREFOE_W { w: self } + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Bits 16:19 - Voltage Reference Selection"] + #[inline(always)] + pub fn sel(&mut self) -> SEL_W { + SEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "VREF Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [vref](index.html) module"] +pub struct VREF_SPEC; +impl crate::RegisterSpec for VREF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [vref::R](R) reader structure"] +impl crate::Readable for VREF_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [vref::W](W) writer structure"] +impl crate::Writable for VREF_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets VREF to value 0"] +impl crate::Resettable for VREF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/supc/vreg.rs b/pac/atsamc20n/src/supc/vreg.rs new file mode 100644 index 000000000000..fb5b12a185cf --- /dev/null +++ b/pac/atsamc20n/src/supc/vreg.rs @@ -0,0 +1,160 @@ +#[doc = "Register `VREG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `VREG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "VREG Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [vreg](index.html) module"] +pub struct VREG_SPEC; +impl crate::RegisterSpec for VREG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [vreg::R](R) reader structure"] +impl crate::Readable for VREG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [vreg::W](W) writer structure"] +impl crate::Writable for VREG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets VREG to value 0"] +impl crate::Resettable for VREG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/supc/vreg33.rs b/pac/atsamc20n/src/supc/vreg33.rs new file mode 100644 index 000000000000..dde6a2a14950 --- /dev/null +++ b/pac/atsamc20n/src/supc/vreg33.rs @@ -0,0 +1,254 @@ +#[doc = "Register `VREG33` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `VREG33` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - VREG33 Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - VREG33 Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ENRDY` reader - VREG33 Ready Enable"] +pub struct ENRDY_R(crate::FieldReader); +impl ENRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENRDY` writer - VREG33 Ready Enable"] +pub struct ENRDY_W<'a> { + w: &'a mut W, +} +impl<'a> ENRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `BYPASS` reader - VREG33 Bypass"] +pub struct BYPASS_R(crate::FieldReader); +impl BYPASS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BYPASS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYPASS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYPASS` writer - VREG33 Bypass"] +pub struct BYPASS_W<'a> { + w: &'a mut W, +} +impl<'a> BYPASS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ISOEN` reader - Isolation Enable"] +pub struct ISOEN_R(crate::FieldReader); +impl ISOEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ISOEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ISOEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ISOEN` writer - Isolation Enable"] +pub struct ISOEN_W<'a> { + w: &'a mut W, +} +impl<'a> ISOEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +impl R { + #[doc = "Bit 1 - VREG33 Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - VREG33 Ready Enable"] + #[inline(always)] + pub fn enrdy(&self) -> ENRDY_R { + ENRDY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - VREG33 Bypass"] + #[inline(always)] + pub fn bypass(&self) -> BYPASS_R { + BYPASS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Isolation Enable"] + #[inline(always)] + pub fn isoen(&self) -> ISOEN_R { + ISOEN_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 1 - VREG33 Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - VREG33 Ready Enable"] + #[inline(always)] + pub fn enrdy(&mut self) -> ENRDY_W { + ENRDY_W { w: self } + } + #[doc = "Bit 3 - VREG33 Bypass"] + #[inline(always)] + pub fn bypass(&mut self) -> BYPASS_W { + BYPASS_W { w: self } + } + #[doc = "Bit 4 - Isolation Enable"] + #[inline(always)] + pub fn isoen(&mut self) -> ISOEN_W { + ISOEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "VREG33 Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [vreg33](index.html) module"] +pub struct VREG33_SPEC; +impl crate::RegisterSpec for VREG33_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [vreg33::R](R) reader structure"] +impl crate::Readable for VREG33_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [vreg33::W](W) writer structure"] +impl crate::Writable for VREG33_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets VREG33 to value 0x10"] +impl crate::Resettable for VREG33_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x10 + } +} diff --git a/pac/atsamc20n/src/sys_tick.rs b/pac/atsamc20n/src/sys_tick.rs new file mode 100644 index 000000000000..b0fe7a59e5ed --- /dev/null +++ b/pac/atsamc20n/src/sys_tick.rs @@ -0,0 +1,28 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - SysTick Control and Status Register"] + pub csr: crate::Reg, + #[doc = "0x04 - SysTick Reload Value Register"] + pub rvr: crate::Reg, + #[doc = "0x08 - SysTick Current Value Register"] + pub cvr: crate::Reg, + #[doc = "0x0c - SysTick Calibration Value Register"] + pub calib: crate::Reg, +} +#[doc = "CSR register accessor: an alias for `Reg`"] +pub type CSR = crate::Reg; +#[doc = "SysTick Control and Status Register"] +pub mod csr; +#[doc = "RVR register accessor: an alias for `Reg`"] +pub type RVR = crate::Reg; +#[doc = "SysTick Reload Value Register"] +pub mod rvr; +#[doc = "CVR register accessor: an alias for `Reg`"] +pub type CVR = crate::Reg; +#[doc = "SysTick Current Value Register"] +pub mod cvr; +#[doc = "CALIB register accessor: an alias for `Reg`"] +pub type CALIB = crate::Reg; +#[doc = "SysTick Calibration Value Register"] +pub mod calib; diff --git a/pac/atsamc20n/src/sys_tick/calib.rs b/pac/atsamc20n/src/sys_tick/calib.rs new file mode 100644 index 000000000000..df7fd80f773a --- /dev/null +++ b/pac/atsamc20n/src/sys_tick/calib.rs @@ -0,0 +1,157 @@ +#[doc = "Register `CALIB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `TENMS` reader - Reload value to use for 10ms timing"] +pub struct TENMS_R(crate::FieldReader); +impl TENMS_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + TENMS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TENMS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "TENMS is rounded from non-integer ratio\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SKEW_A { + #[doc = "0: 10ms calibration value is exact"] + VALUE_0 = 0, + #[doc = "1: 10ms calibration value is inexact, because of the clock frequency"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SKEW_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SKEW` reader - TENMS is rounded from non-integer ratio"] +pub struct SKEW_R(crate::FieldReader); +impl SKEW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SKEW_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SKEW_A { + match self.bits { + false => SKEW_A::VALUE_0, + true => SKEW_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == SKEW_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == SKEW_A::VALUE_1 + } +} +impl core::ops::Deref for SKEW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "No Separate Reference Clock\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum NOREF_A { + #[doc = "0: The reference clock is provided"] + VALUE_0 = 0, + #[doc = "1: The reference clock is not provided"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NOREF_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NOREF` reader - No Separate Reference Clock"] +pub struct NOREF_R(crate::FieldReader); +impl NOREF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NOREF_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> NOREF_A { + match self.bits { + false => NOREF_A::VALUE_0, + true => NOREF_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == NOREF_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == NOREF_A::VALUE_1 + } +} +impl core::ops::Deref for NOREF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:23 - Reload value to use for 10ms timing"] + #[inline(always)] + pub fn tenms(&self) -> TENMS_R { + TENMS_R::new((self.bits & 0x00ff_ffff) as u32) + } + #[doc = "Bit 30 - TENMS is rounded from non-integer ratio"] + #[inline(always)] + pub fn skew(&self) -> SKEW_R { + SKEW_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 31 - No Separate Reference Clock"] + #[inline(always)] + pub fn noref(&self) -> NOREF_R { + NOREF_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +#[doc = "SysTick Calibration Value Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [calib](index.html) module"] +pub struct CALIB_SPEC; +impl crate::RegisterSpec for CALIB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [calib::R](R) reader structure"] +impl crate::Readable for CALIB_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CALIB to value 0"] +impl crate::Resettable for CALIB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/sys_tick/csr.rs b/pac/atsamc20n/src/sys_tick/csr.rs new file mode 100644 index 000000000000..872d637f5a86 --- /dev/null +++ b/pac/atsamc20n/src/sys_tick/csr.rs @@ -0,0 +1,395 @@ +#[doc = "Register `CSR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CSR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "SysTick Counter Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ENABLE_A { + #[doc = "0: Counter disabled"] + VALUE_0 = 0, + #[doc = "1: Counter enabled"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ENABLE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ENABLE` reader - SysTick Counter Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ENABLE_A { + match self.bits { + false => ENABLE_A::VALUE_0, + true => ENABLE_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == ENABLE_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == ENABLE_A::VALUE_1 + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - SysTick Counter Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: ENABLE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Counter disabled"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(ENABLE_A::VALUE_0) + } + #[doc = "Counter enabled"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(ENABLE_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "SysTick Exception Request Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TICKINT_A { + #[doc = "0: Counting down to 0 does not assert the SysTick exception request"] + VALUE_0 = 0, + #[doc = "1: Counting down to 0 asserts the SysTick exception request"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TICKINT_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TICKINT` reader - SysTick Exception Request Enable"] +pub struct TICKINT_R(crate::FieldReader); +impl TICKINT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TICKINT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TICKINT_A { + match self.bits { + false => TICKINT_A::VALUE_0, + true => TICKINT_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == TICKINT_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == TICKINT_A::VALUE_1 + } +} +impl core::ops::Deref for TICKINT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TICKINT` writer - SysTick Exception Request Enable"] +pub struct TICKINT_W<'a> { + w: &'a mut W, +} +impl<'a> TICKINT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TICKINT_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Counting down to 0 does not assert the SysTick exception request"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(TICKINT_A::VALUE_0) + } + #[doc = "Counting down to 0 asserts the SysTick exception request"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(TICKINT_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Clock Source 0=external, 1=processor\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CLKSOURCE_A { + #[doc = "0: External clock"] + VALUE_0 = 0, + #[doc = "1: Processor clock"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CLKSOURCE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CLKSOURCE` reader - Clock Source 0=external, 1=processor"] +pub struct CLKSOURCE_R(crate::FieldReader); +impl CLKSOURCE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKSOURCE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CLKSOURCE_A { + match self.bits { + false => CLKSOURCE_A::VALUE_0, + true => CLKSOURCE_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == CLKSOURCE_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == CLKSOURCE_A::VALUE_1 + } +} +impl core::ops::Deref for CLKSOURCE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKSOURCE` writer - Clock Source 0=external, 1=processor"] +pub struct CLKSOURCE_W<'a> { + w: &'a mut W, +} +impl<'a> CLKSOURCE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CLKSOURCE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "External clock"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(CLKSOURCE_A::VALUE_0) + } + #[doc = "Processor clock"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(CLKSOURCE_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `COUNTFLAG` reader - Timer counted to 0 since last read of register"] +pub struct COUNTFLAG_R(crate::FieldReader); +impl COUNTFLAG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNTFLAG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNTFLAG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNTFLAG` writer - Timer counted to 0 since last read of register"] +pub struct COUNTFLAG_W<'a> { + w: &'a mut W, +} +impl<'a> COUNTFLAG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +impl R { + #[doc = "Bit 0 - SysTick Counter Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SysTick Exception Request Enable"] + #[inline(always)] + pub fn tickint(&self) -> TICKINT_R { + TICKINT_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Clock Source 0=external, 1=processor"] + #[inline(always)] + pub fn clksource(&self) -> CLKSOURCE_R { + CLKSOURCE_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 16 - Timer counted to 0 since last read of register"] + #[inline(always)] + pub fn countflag(&self) -> COUNTFLAG_R { + COUNTFLAG_R::new(((self.bits >> 16) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - SysTick Counter Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 1 - SysTick Exception Request Enable"] + #[inline(always)] + pub fn tickint(&mut self) -> TICKINT_W { + TICKINT_W { w: self } + } + #[doc = "Bit 2 - Clock Source 0=external, 1=processor"] + #[inline(always)] + pub fn clksource(&mut self) -> CLKSOURCE_W { + CLKSOURCE_W { w: self } + } + #[doc = "Bit 16 - Timer counted to 0 since last read of register"] + #[inline(always)] + pub fn countflag(&mut self) -> COUNTFLAG_W { + COUNTFLAG_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SysTick Control and Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [csr](index.html) module"] +pub struct CSR_SPEC; +impl crate::RegisterSpec for CSR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [csr::R](R) reader structure"] +impl crate::Readable for CSR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [csr::W](W) writer structure"] +impl crate::Writable for CSR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CSR to value 0x04"] +impl crate::Resettable for CSR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x04 + } +} diff --git a/pac/atsamc20n/src/sys_tick/cvr.rs b/pac/atsamc20n/src/sys_tick/cvr.rs new file mode 100644 index 000000000000..8a40b5f43b3a --- /dev/null +++ b/pac/atsamc20n/src/sys_tick/cvr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `CVR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CVR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CURRENT` reader - Current value at the time the register is accessed"] +pub struct CURRENT_R(crate::FieldReader); +impl CURRENT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CURRENT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CURRENT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CURRENT` writer - Current value at the time the register is accessed"] +pub struct CURRENT_W<'a> { + w: &'a mut W, +} +impl<'a> CURRENT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Current value at the time the register is accessed"] + #[inline(always)] + pub fn current(&self) -> CURRENT_R { + CURRENT_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Current value at the time the register is accessed"] + #[inline(always)] + pub fn current(&mut self) -> CURRENT_W { + CURRENT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SysTick Current Value Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cvr](index.html) module"] +pub struct CVR_SPEC; +impl crate::RegisterSpec for CVR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cvr::R](R) reader structure"] +impl crate::Readable for CVR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cvr::W](W) writer structure"] +impl crate::Writable for CVR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CVR to value 0"] +impl crate::Resettable for CVR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/sys_tick/rvr.rs b/pac/atsamc20n/src/sys_tick/rvr.rs new file mode 100644 index 000000000000..ac023ff75f36 --- /dev/null +++ b/pac/atsamc20n/src/sys_tick/rvr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `RVR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RVR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RELOAD` reader - Value to load into the SysTick Current Value Register when the counter reaches 0"] +pub struct RELOAD_R(crate::FieldReader); +impl RELOAD_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + RELOAD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RELOAD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RELOAD` writer - Value to load into the SysTick Current Value Register when the counter reaches 0"] +pub struct RELOAD_W<'a> { + w: &'a mut W, +} +impl<'a> RELOAD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Value to load into the SysTick Current Value Register when the counter reaches 0"] + #[inline(always)] + pub fn reload(&self) -> RELOAD_R { + RELOAD_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Value to load into the SysTick Current Value Register when the counter reaches 0"] + #[inline(always)] + pub fn reload(&mut self) -> RELOAD_W { + RELOAD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SysTick Reload Value Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rvr](index.html) module"] +pub struct RVR_SPEC; +impl crate::RegisterSpec for RVR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rvr::R](R) reader structure"] +impl crate::Readable for RVR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rvr::W](W) writer structure"] +impl crate::Writable for RVR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RVR to value 0"] +impl crate::Resettable for RVR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/system_control.rs b/pac/atsamc20n/src/system_control.rs new file mode 100644 index 000000000000..4894b22b258f --- /dev/null +++ b/pac/atsamc20n/src/system_control.rs @@ -0,0 +1,67 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved0: [u8; 0x0d00], + #[doc = "0xd00 - CPUID Base Register"] + pub cpuid: crate::Reg, + #[doc = "0xd04 - Interrupt Control and State Register"] + pub icsr: crate::Reg, + #[doc = "0xd08 - Vector Table Offset Register"] + pub vtor: crate::Reg, + #[doc = "0xd0c - Application Interrupt and Reset Control Register"] + pub aircr: crate::Reg, + #[doc = "0xd10 - System Control Register"] + pub scr: crate::Reg, + #[doc = "0xd14 - Configuration and Control Register"] + pub ccr: crate::Reg, + _reserved6: [u8; 0x04], + #[doc = "0xd1c - System Handler Priority Register 2"] + pub shpr2: crate::Reg, + #[doc = "0xd20 - System Handler Priority Register 3"] + pub shpr3: crate::Reg, + #[doc = "0xd24 - System Handler Control and State Register"] + pub shcsr: crate::Reg, + _reserved9: [u8; 0x08], + #[doc = "0xd30 - Debug Fault Status Register"] + pub dfsr: crate::Reg, +} +#[doc = "CPUID register accessor: an alias for `Reg`"] +pub type CPUID = crate::Reg; +#[doc = "CPUID Base Register"] +pub mod cpuid; +#[doc = "ICSR register accessor: an alias for `Reg`"] +pub type ICSR = crate::Reg; +#[doc = "Interrupt Control and State Register"] +pub mod icsr; +#[doc = "VTOR register accessor: an alias for `Reg`"] +pub type VTOR = crate::Reg; +#[doc = "Vector Table Offset Register"] +pub mod vtor; +#[doc = "AIRCR register accessor: an alias for `Reg`"] +pub type AIRCR = crate::Reg; +#[doc = "Application Interrupt and Reset Control Register"] +pub mod aircr; +#[doc = "SCR register accessor: an alias for `Reg`"] +pub type SCR = crate::Reg; +#[doc = "System Control Register"] +pub mod scr; +#[doc = "CCR register accessor: an alias for `Reg`"] +pub type CCR = crate::Reg; +#[doc = "Configuration and Control Register"] +pub mod ccr; +#[doc = "SHPR2 register accessor: an alias for `Reg`"] +pub type SHPR2 = crate::Reg; +#[doc = "System Handler Priority Register 2"] +pub mod shpr2; +#[doc = "SHPR3 register accessor: an alias for `Reg`"] +pub type SHPR3 = crate::Reg; +#[doc = "System Handler Priority Register 3"] +pub mod shpr3; +#[doc = "SHCSR register accessor: an alias for `Reg`"] +pub type SHCSR = crate::Reg; +#[doc = "System Handler Control and State Register"] +pub mod shcsr; +#[doc = "DFSR register accessor: an alias for `Reg`"] +pub type DFSR = crate::Reg; +#[doc = "Debug Fault Status Register"] +pub mod dfsr; diff --git a/pac/atsamc20n/src/system_control/aircr.rs b/pac/atsamc20n/src/system_control/aircr.rs new file mode 100644 index 000000000000..9453cc6f30bc --- /dev/null +++ b/pac/atsamc20n/src/system_control/aircr.rs @@ -0,0 +1,338 @@ +#[doc = "Register `AIRCR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `AIRCR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `VECTCLRACTIVE` reader - Debug: Clear state information"] +pub struct VECTCLRACTIVE_R(crate::FieldReader); +impl VECTCLRACTIVE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + VECTCLRACTIVE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VECTCLRACTIVE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VECTCLRACTIVE` writer - Debug: Clear state information"] +pub struct VECTCLRACTIVE_W<'a> { + w: &'a mut W, +} +impl<'a> VECTCLRACTIVE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "System Reset Request\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SYSRESETREQ_A { + #[doc = "0: No system reset request"] + VALUE_0 = 0, + #[doc = "1: Asserts a signal to the outer system that requests a reset"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SYSRESETREQ_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SYSRESETREQ` reader - System Reset Request"] +pub struct SYSRESETREQ_R(crate::FieldReader); +impl SYSRESETREQ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYSRESETREQ_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SYSRESETREQ_A { + match self.bits { + false => SYSRESETREQ_A::VALUE_0, + true => SYSRESETREQ_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == SYSRESETREQ_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == SYSRESETREQ_A::VALUE_1 + } +} +impl core::ops::Deref for SYSRESETREQ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYSRESETREQ` writer - System Reset Request"] +pub struct SYSRESETREQ_W<'a> { + w: &'a mut W, +} +impl<'a> SYSRESETREQ_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SYSRESETREQ_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "No system reset request"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(SYSRESETREQ_A::VALUE_0) + } + #[doc = "Asserts a signal to the outer system that requests a reset"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(SYSRESETREQ_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Data Endianness, 0=little, 1=big\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ENDIANNESS_A { + #[doc = "0: Little-endian"] + VALUE_0 = 0, + #[doc = "1: Big-endian"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ENDIANNESS_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ENDIANNESS` reader - Data Endianness, 0=little, 1=big"] +pub struct ENDIANNESS_R(crate::FieldReader); +impl ENDIANNESS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENDIANNESS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ENDIANNESS_A { + match self.bits { + false => ENDIANNESS_A::VALUE_0, + true => ENDIANNESS_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == ENDIANNESS_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == ENDIANNESS_A::VALUE_1 + } +} +impl core::ops::Deref for ENDIANNESS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENDIANNESS` writer - Data Endianness, 0=little, 1=big"] +pub struct ENDIANNESS_W<'a> { + w: &'a mut W, +} +impl<'a> ENDIANNESS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: ENDIANNESS_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Little-endian"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(ENDIANNESS_A::VALUE_0) + } + #[doc = "Big-endian"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(ENDIANNESS_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `VECTKEY` reader - Register key (0x05FA)"] +pub struct VECTKEY_R(crate::FieldReader); +impl VECTKEY_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + VECTKEY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VECTKEY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VECTKEY` writer - Register key (0x05FA)"] +pub struct VECTKEY_W<'a> { + w: &'a mut W, +} +impl<'a> VECTKEY_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xffff << 16)) | ((value as u32 & 0xffff) << 16); + self.w + } +} +impl R { + #[doc = "Bit 1 - Debug: Clear state information"] + #[inline(always)] + pub fn vectclractive(&self) -> VECTCLRACTIVE_R { + VECTCLRACTIVE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - System Reset Request"] + #[inline(always)] + pub fn sysresetreq(&self) -> SYSRESETREQ_R { + SYSRESETREQ_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 15 - Data Endianness, 0=little, 1=big"] + #[inline(always)] + pub fn endianness(&self) -> ENDIANNESS_R { + ENDIANNESS_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:31 - Register key (0x05FA)"] + #[inline(always)] + pub fn vectkey(&self) -> VECTKEY_R { + VECTKEY_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bit 1 - Debug: Clear state information"] + #[inline(always)] + pub fn vectclractive(&mut self) -> VECTCLRACTIVE_W { + VECTCLRACTIVE_W { w: self } + } + #[doc = "Bit 2 - System Reset Request"] + #[inline(always)] + pub fn sysresetreq(&mut self) -> SYSRESETREQ_W { + SYSRESETREQ_W { w: self } + } + #[doc = "Bit 15 - Data Endianness, 0=little, 1=big"] + #[inline(always)] + pub fn endianness(&mut self) -> ENDIANNESS_W { + ENDIANNESS_W { w: self } + } + #[doc = "Bits 16:31 - Register key (0x05FA)"] + #[inline(always)] + pub fn vectkey(&mut self) -> VECTKEY_W { + VECTKEY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Application Interrupt and Reset Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [aircr](index.html) module"] +pub struct AIRCR_SPEC; +impl crate::RegisterSpec for AIRCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [aircr::R](R) reader structure"] +impl crate::Readable for AIRCR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [aircr::W](W) writer structure"] +impl crate::Writable for AIRCR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets AIRCR to value 0"] +impl crate::Resettable for AIRCR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/system_control/ccr.rs b/pac/atsamc20n/src/system_control/ccr.rs new file mode 100644 index 000000000000..62516a7b60c8 --- /dev/null +++ b/pac/atsamc20n/src/system_control/ccr.rs @@ -0,0 +1,137 @@ +#[doc = "Register `CCR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Unaligned accesses generates a Hard Fault\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum UNALIGN_TRP_A { + #[doc = "0: Do not trap unaligned halfword and word accesses"] + VALUE_0 = 0, + #[doc = "1: Trap unaligned halfword and word accesses"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: UNALIGN_TRP_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `UNALIGN_TRP` reader - Unaligned accesses generates a Hard Fault"] +pub struct UNALIGN_TRP_R(crate::FieldReader); +impl UNALIGN_TRP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UNALIGN_TRP_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> UNALIGN_TRP_A { + match self.bits { + false => UNALIGN_TRP_A::VALUE_0, + true => UNALIGN_TRP_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == UNALIGN_TRP_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == UNALIGN_TRP_A::VALUE_1 + } +} +impl core::ops::Deref for UNALIGN_TRP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Stack 8-byte aligned on exception entry\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum STKALIGN_A { + #[doc = "0: 4-byte aligned"] + VALUE_0 = 0, + #[doc = "1: 8-byte aligned"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: STKALIGN_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STKALIGN` reader - Stack 8-byte aligned on exception entry"] +pub struct STKALIGN_R(crate::FieldReader); +impl STKALIGN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STKALIGN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STKALIGN_A { + match self.bits { + false => STKALIGN_A::VALUE_0, + true => STKALIGN_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == STKALIGN_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == STKALIGN_A::VALUE_1 + } +} +impl core::ops::Deref for STKALIGN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 3 - Unaligned accesses generates a Hard Fault"] + #[inline(always)] + pub fn unalign_trp(&self) -> UNALIGN_TRP_R { + UNALIGN_TRP_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 9 - Stack 8-byte aligned on exception entry"] + #[inline(always)] + pub fn stkalign(&self) -> STKALIGN_R { + STKALIGN_R::new(((self.bits >> 9) & 0x01) != 0) + } +} +#[doc = "Configuration and Control Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccr](index.html) module"] +pub struct CCR_SPEC; +impl crate::RegisterSpec for CCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ccr::R](R) reader structure"] +impl crate::Readable for CCR_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CCR to value 0x0204"] +impl crate::Resettable for CCR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0204 + } +} diff --git a/pac/atsamc20n/src/system_control/cpuid.rs b/pac/atsamc20n/src/system_control/cpuid.rs new file mode 100644 index 000000000000..4157d7a94e97 --- /dev/null +++ b/pac/atsamc20n/src/system_control/cpuid.rs @@ -0,0 +1,133 @@ +#[doc = "Register `CPUID` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `REVISION` reader - Minor revision number"] +pub struct REVISION_R(crate::FieldReader); +impl REVISION_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REVISION_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REVISION_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PARTNO` reader - Processor Part Number, 0xC60=Cortex-M0+"] +pub struct PARTNO_R(crate::FieldReader); +impl PARTNO_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + PARTNO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PARTNO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ARCHITECTURE` reader - Processor Architecture, 0xC=ARMv6-M"] +pub struct ARCHITECTURE_R(crate::FieldReader); +impl ARCHITECTURE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ARCHITECTURE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ARCHITECTURE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VARIANT` reader - Major revision number"] +pub struct VARIANT_R(crate::FieldReader); +impl VARIANT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + VARIANT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VARIANT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IMPLEMENTER` reader - Implementer code, ARM=0x41"] +pub struct IMPLEMENTER_R(crate::FieldReader); +impl IMPLEMENTER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + IMPLEMENTER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IMPLEMENTER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:3 - Minor revision number"] + #[inline(always)] + pub fn revision(&self) -> REVISION_R { + REVISION_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:15 - Processor Part Number, 0xC60=Cortex-M0+"] + #[inline(always)] + pub fn partno(&self) -> PARTNO_R { + PARTNO_R::new(((self.bits >> 4) & 0x0fff) as u16) + } + #[doc = "Bits 16:19 - Processor Architecture, 0xC=ARMv6-M"] + #[inline(always)] + pub fn architecture(&self) -> ARCHITECTURE_R { + ARCHITECTURE_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bits 20:23 - Major revision number"] + #[inline(always)] + pub fn variant(&self) -> VARIANT_R { + VARIANT_R::new(((self.bits >> 20) & 0x0f) as u8) + } + #[doc = "Bits 24:31 - Implementer code, ARM=0x41"] + #[inline(always)] + pub fn implementer(&self) -> IMPLEMENTER_R { + IMPLEMENTER_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[doc = "CPUID Base Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cpuid](index.html) module"] +pub struct CPUID_SPEC; +impl crate::RegisterSpec for CPUID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cpuid::R](R) reader structure"] +impl crate::Readable for CPUID_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CPUID to value 0x410c_c601"] +impl crate::Resettable for CPUID_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x410c_c601 + } +} diff --git a/pac/atsamc20n/src/system_control/dfsr.rs b/pac/atsamc20n/src/system_control/dfsr.rs new file mode 100644 index 000000000000..948899af0905 --- /dev/null +++ b/pac/atsamc20n/src/system_control/dfsr.rs @@ -0,0 +1,301 @@ +#[doc = "Register `DFSR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DFSR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `HALTED` reader - Halt request debug event active"] +pub struct HALTED_R(crate::FieldReader); +impl HALTED_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HALTED_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HALTED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HALTED` writer - Halt request debug event active"] +pub struct HALTED_W<'a> { + w: &'a mut W, +} +impl<'a> HALTED_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `BKPT` reader - Breakpoint debug event"] +pub struct BKPT_R(crate::FieldReader); +impl BKPT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BKPT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BKPT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BKPT` writer - Breakpoint debug event"] +pub struct BKPT_W<'a> { + w: &'a mut W, +} +impl<'a> BKPT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `DWTTRAP` reader - DWT debug event"] +pub struct DWTTRAP_R(crate::FieldReader); +impl DWTTRAP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DWTTRAP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DWTTRAP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DWTTRAP` writer - DWT debug event"] +pub struct DWTTRAP_W<'a> { + w: &'a mut W, +} +impl<'a> DWTTRAP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `VCATCH` reader - Vector catch debug event"] +pub struct VCATCH_R(crate::FieldReader); +impl VCATCH_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + VCATCH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VCATCH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VCATCH` writer - Vector catch debug event"] +pub struct VCATCH_W<'a> { + w: &'a mut W, +} +impl<'a> VCATCH_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `EXTERNAL` reader - EDBGRQ debug event"] +pub struct EXTERNAL_R(crate::FieldReader); +impl EXTERNAL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTERNAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTERNAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTERNAL` writer - EDBGRQ debug event"] +pub struct EXTERNAL_W<'a> { + w: &'a mut W, +} +impl<'a> EXTERNAL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +impl R { + #[doc = "Bit 0 - Halt request debug event active"] + #[inline(always)] + pub fn halted(&self) -> HALTED_R { + HALTED_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Breakpoint debug event"] + #[inline(always)] + pub fn bkpt(&self) -> BKPT_R { + BKPT_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - DWT debug event"] + #[inline(always)] + pub fn dwttrap(&self) -> DWTTRAP_R { + DWTTRAP_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Vector catch debug event"] + #[inline(always)] + pub fn vcatch(&self) -> VCATCH_R { + VCATCH_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - EDBGRQ debug event"] + #[inline(always)] + pub fn external(&self) -> EXTERNAL_R { + EXTERNAL_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Halt request debug event active"] + #[inline(always)] + pub fn halted(&mut self) -> HALTED_W { + HALTED_W { w: self } + } + #[doc = "Bit 1 - Breakpoint debug event"] + #[inline(always)] + pub fn bkpt(&mut self) -> BKPT_W { + BKPT_W { w: self } + } + #[doc = "Bit 2 - DWT debug event"] + #[inline(always)] + pub fn dwttrap(&mut self) -> DWTTRAP_W { + DWTTRAP_W { w: self } + } + #[doc = "Bit 3 - Vector catch debug event"] + #[inline(always)] + pub fn vcatch(&mut self) -> VCATCH_W { + VCATCH_W { w: self } + } + #[doc = "Bit 4 - EDBGRQ debug event"] + #[inline(always)] + pub fn external(&mut self) -> EXTERNAL_W { + EXTERNAL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Fault Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dfsr](index.html) module"] +pub struct DFSR_SPEC; +impl crate::RegisterSpec for DFSR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dfsr::R](R) reader structure"] +impl crate::Readable for DFSR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dfsr::W](W) writer structure"] +impl crate::Writable for DFSR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DFSR to value 0"] +impl crate::Resettable for DFSR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/system_control/icsr.rs b/pac/atsamc20n/src/system_control/icsr.rs new file mode 100644 index 000000000000..7fe5fd412116 --- /dev/null +++ b/pac/atsamc20n/src/system_control/icsr.rs @@ -0,0 +1,704 @@ +#[doc = "Register `ICSR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ICSR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `VECTACTIVE` reader - Debug: Exception number of currently executing exception, or 0 if thread mode"] +pub struct VECTACTIVE_R(crate::FieldReader); +impl VECTACTIVE_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + VECTACTIVE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VECTACTIVE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VECTACTIVE` writer - Debug: Exception number of currently executing exception, or 0 if thread mode"] +pub struct VECTACTIVE_W<'a> { + w: &'a mut W, +} +impl<'a> VECTACTIVE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01ff) | (value as u32 & 0x01ff); + self.w + } +} +#[doc = "Field `VECTPENDING` reader - Exception number of the highest priority pending enabled exception"] +pub struct VECTPENDING_R(crate::FieldReader); +impl VECTPENDING_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + VECTPENDING_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VECTPENDING_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VECTPENDING` writer - Exception number of the highest priority pending enabled exception"] +pub struct VECTPENDING_W<'a> { + w: &'a mut W, +} +impl<'a> VECTPENDING_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01ff << 12)) | ((value as u32 & 0x01ff) << 12); + self.w + } +} +#[doc = "Field `ISRPENDING` reader - Debug: NVIC interrupt pending"] +pub struct ISRPENDING_R(crate::FieldReader); +impl ISRPENDING_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ISRPENDING_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ISRPENDING_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ISRPENDING` writer - Debug: NVIC interrupt pending"] +pub struct ISRPENDING_W<'a> { + w: &'a mut W, +} +impl<'a> ISRPENDING_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `ISRPREEMPT` reader - Debug: Pending exception serviced on exit from debug halt"] +pub struct ISRPREEMPT_R(crate::FieldReader); +impl ISRPREEMPT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ISRPREEMPT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ISRPREEMPT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ISRPREEMPT` writer - Debug: Pending exception serviced on exit from debug halt"] +pub struct ISRPREEMPT_W<'a> { + w: &'a mut W, +} +impl<'a> ISRPREEMPT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "SysTick exception clear-pending bit\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PENDSTCLR_A { + #[doc = "0: No effect"] + VALUE_0 = 0, + #[doc = "1: Removes the pending state from the SysTick exception"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PENDSTCLR_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PENDSTCLR` reader - SysTick exception clear-pending bit"] +pub struct PENDSTCLR_R(crate::FieldReader); +impl PENDSTCLR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDSTCLR_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PENDSTCLR_A { + match self.bits { + false => PENDSTCLR_A::VALUE_0, + true => PENDSTCLR_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == PENDSTCLR_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == PENDSTCLR_A::VALUE_1 + } +} +impl core::ops::Deref for PENDSTCLR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDSTCLR` writer - SysTick exception clear-pending bit"] +pub struct PENDSTCLR_W<'a> { + w: &'a mut W, +} +impl<'a> PENDSTCLR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PENDSTCLR_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "No effect"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(PENDSTCLR_A::VALUE_0) + } + #[doc = "Removes the pending state from the SysTick exception"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(PENDSTCLR_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "SysTick exception set-pending bit\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PENDSTSET_A { + #[doc = "0: Write: no effect; read: SysTick exception is not pending"] + VALUE_0 = 0, + #[doc = "1: Write: changes SysTick exception state to pending; read: SysTick exception is pending"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PENDSTSET_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PENDSTSET` reader - SysTick exception set-pending bit"] +pub struct PENDSTSET_R(crate::FieldReader); +impl PENDSTSET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDSTSET_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PENDSTSET_A { + match self.bits { + false => PENDSTSET_A::VALUE_0, + true => PENDSTSET_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == PENDSTSET_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == PENDSTSET_A::VALUE_1 + } +} +impl core::ops::Deref for PENDSTSET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDSTSET` writer - SysTick exception set-pending bit"] +pub struct PENDSTSET_W<'a> { + w: &'a mut W, +} +impl<'a> PENDSTSET_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PENDSTSET_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Write: no effect; read: SysTick exception is not pending"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(PENDSTSET_A::VALUE_0) + } + #[doc = "Write: changes SysTick exception state to pending; read: SysTick exception is pending"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(PENDSTSET_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "PendSV clear-pending bit\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PENDSVCLR_A { + #[doc = "0: No effect"] + VALUE_0 = 0, + #[doc = "1: Removes the pending state from the PendSV exception"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PENDSVCLR_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PENDSVCLR` reader - PendSV clear-pending bit"] +pub struct PENDSVCLR_R(crate::FieldReader); +impl PENDSVCLR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDSVCLR_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PENDSVCLR_A { + match self.bits { + false => PENDSVCLR_A::VALUE_0, + true => PENDSVCLR_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == PENDSVCLR_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == PENDSVCLR_A::VALUE_1 + } +} +impl core::ops::Deref for PENDSVCLR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDSVCLR` writer - PendSV clear-pending bit"] +pub struct PENDSVCLR_W<'a> { + w: &'a mut W, +} +impl<'a> PENDSVCLR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PENDSVCLR_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "No effect"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(PENDSVCLR_A::VALUE_0) + } + #[doc = "Removes the pending state from the PendSV exception"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(PENDSVCLR_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +#[doc = "PendSV set-pending bit\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PENDSVSET_A { + #[doc = "0: Write: no effect; read: PendSV exception is not pending"] + VALUE_0 = 0, + #[doc = "1: Write: changes PendSV exception state to pending; read: PendSV exception is pending"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PENDSVSET_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PENDSVSET` reader - PendSV set-pending bit"] +pub struct PENDSVSET_R(crate::FieldReader); +impl PENDSVSET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDSVSET_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PENDSVSET_A { + match self.bits { + false => PENDSVSET_A::VALUE_0, + true => PENDSVSET_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == PENDSVSET_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == PENDSVSET_A::VALUE_1 + } +} +impl core::ops::Deref for PENDSVSET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDSVSET` writer - PendSV set-pending bit"] +pub struct PENDSVSET_W<'a> { + w: &'a mut W, +} +impl<'a> PENDSVSET_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PENDSVSET_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Write: no effect; read: PendSV exception is not pending"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(PENDSVSET_A::VALUE_0) + } + #[doc = "Write: changes PendSV exception state to pending; read: PendSV exception is pending"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(PENDSVSET_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "NMI set-pending bit\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum NMIPENDSET_A { + #[doc = "0: Write: no effect; read: NMI exception is not pending"] + VALUE_0 = 0, + #[doc = "1: Write: changes NMI exception state to pending; read: NMI exception is pending"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NMIPENDSET_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NMIPENDSET` reader - NMI set-pending bit"] +pub struct NMIPENDSET_R(crate::FieldReader); +impl NMIPENDSET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NMIPENDSET_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> NMIPENDSET_A { + match self.bits { + false => NMIPENDSET_A::VALUE_0, + true => NMIPENDSET_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == NMIPENDSET_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == NMIPENDSET_A::VALUE_1 + } +} +impl core::ops::Deref for NMIPENDSET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NMIPENDSET` writer - NMI set-pending bit"] +pub struct NMIPENDSET_W<'a> { + w: &'a mut W, +} +impl<'a> NMIPENDSET_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: NMIPENDSET_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Write: no effect; read: NMI exception is not pending"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(NMIPENDSET_A::VALUE_0) + } + #[doc = "Write: changes NMI exception state to pending; read: NMI exception is pending"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(NMIPENDSET_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bits 0:8 - Debug: Exception number of currently executing exception, or 0 if thread mode"] + #[inline(always)] + pub fn vectactive(&self) -> VECTACTIVE_R { + VECTACTIVE_R::new((self.bits & 0x01ff) as u16) + } + #[doc = "Bits 12:20 - Exception number of the highest priority pending enabled exception"] + #[inline(always)] + pub fn vectpending(&self) -> VECTPENDING_R { + VECTPENDING_R::new(((self.bits >> 12) & 0x01ff) as u16) + } + #[doc = "Bit 22 - Debug: NVIC interrupt pending"] + #[inline(always)] + pub fn isrpending(&self) -> ISRPENDING_R { + ISRPENDING_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Debug: Pending exception serviced on exit from debug halt"] + #[inline(always)] + pub fn isrpreempt(&self) -> ISRPREEMPT_R { + ISRPREEMPT_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 25 - SysTick exception clear-pending bit"] + #[inline(always)] + pub fn pendstclr(&self) -> PENDSTCLR_R { + PENDSTCLR_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - SysTick exception set-pending bit"] + #[inline(always)] + pub fn pendstset(&self) -> PENDSTSET_R { + PENDSTSET_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - PendSV clear-pending bit"] + #[inline(always)] + pub fn pendsvclr(&self) -> PENDSVCLR_R { + PENDSVCLR_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28 - PendSV set-pending bit"] + #[inline(always)] + pub fn pendsvset(&self) -> PENDSVSET_R { + PENDSVSET_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 31 - NMI set-pending bit"] + #[inline(always)] + pub fn nmipendset(&self) -> NMIPENDSET_R { + NMIPENDSET_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:8 - Debug: Exception number of currently executing exception, or 0 if thread mode"] + #[inline(always)] + pub fn vectactive(&mut self) -> VECTACTIVE_W { + VECTACTIVE_W { w: self } + } + #[doc = "Bits 12:20 - Exception number of the highest priority pending enabled exception"] + #[inline(always)] + pub fn vectpending(&mut self) -> VECTPENDING_W { + VECTPENDING_W { w: self } + } + #[doc = "Bit 22 - Debug: NVIC interrupt pending"] + #[inline(always)] + pub fn isrpending(&mut self) -> ISRPENDING_W { + ISRPENDING_W { w: self } + } + #[doc = "Bit 23 - Debug: Pending exception serviced on exit from debug halt"] + #[inline(always)] + pub fn isrpreempt(&mut self) -> ISRPREEMPT_W { + ISRPREEMPT_W { w: self } + } + #[doc = "Bit 25 - SysTick exception clear-pending bit"] + #[inline(always)] + pub fn pendstclr(&mut self) -> PENDSTCLR_W { + PENDSTCLR_W { w: self } + } + #[doc = "Bit 26 - SysTick exception set-pending bit"] + #[inline(always)] + pub fn pendstset(&mut self) -> PENDSTSET_W { + PENDSTSET_W { w: self } + } + #[doc = "Bit 27 - PendSV clear-pending bit"] + #[inline(always)] + pub fn pendsvclr(&mut self) -> PENDSVCLR_W { + PENDSVCLR_W { w: self } + } + #[doc = "Bit 28 - PendSV set-pending bit"] + #[inline(always)] + pub fn pendsvset(&mut self) -> PENDSVSET_W { + PENDSVSET_W { w: self } + } + #[doc = "Bit 31 - NMI set-pending bit"] + #[inline(always)] + pub fn nmipendset(&mut self) -> NMIPENDSET_W { + NMIPENDSET_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Control and State Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [icsr](index.html) module"] +pub struct ICSR_SPEC; +impl crate::RegisterSpec for ICSR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [icsr::R](R) reader structure"] +impl crate::Readable for ICSR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [icsr::W](W) writer structure"] +impl crate::Writable for ICSR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ICSR to value 0"] +impl crate::Resettable for ICSR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/system_control/scr.rs b/pac/atsamc20n/src/system_control/scr.rs new file mode 100644 index 000000000000..db9c54fe6f6f --- /dev/null +++ b/pac/atsamc20n/src/system_control/scr.rs @@ -0,0 +1,348 @@ +#[doc = "Register `SCR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SCR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Sleep-On-Exit when exiting Handler mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SLEEPONEXIT_A { + #[doc = "0: O not sleep when returning to Thread mode"] + VALUE_0 = 0, + #[doc = "1: Enter sleep, or deep sleep, on return from an ISR"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SLEEPONEXIT_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SLEEPONEXIT` reader - Sleep-On-Exit when exiting Handler mode"] +pub struct SLEEPONEXIT_R(crate::FieldReader); +impl SLEEPONEXIT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLEEPONEXIT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SLEEPONEXIT_A { + match self.bits { + false => SLEEPONEXIT_A::VALUE_0, + true => SLEEPONEXIT_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == SLEEPONEXIT_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == SLEEPONEXIT_A::VALUE_1 + } +} +impl core::ops::Deref for SLEEPONEXIT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLEEPONEXIT` writer - Sleep-On-Exit when exiting Handler mode"] +pub struct SLEEPONEXIT_W<'a> { + w: &'a mut W, +} +impl<'a> SLEEPONEXIT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SLEEPONEXIT_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "O not sleep when returning to Thread mode"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(SLEEPONEXIT_A::VALUE_0) + } + #[doc = "Enter sleep, or deep sleep, on return from an ISR"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(SLEEPONEXIT_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Uses Deep Sleep as low power mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SLEEPDEEP_A { + #[doc = "0: Sleep"] + VALUE_0 = 0, + #[doc = "1: Deep sleep"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SLEEPDEEP_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SLEEPDEEP` reader - Uses Deep Sleep as low power mode"] +pub struct SLEEPDEEP_R(crate::FieldReader); +impl SLEEPDEEP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLEEPDEEP_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SLEEPDEEP_A { + match self.bits { + false => SLEEPDEEP_A::VALUE_0, + true => SLEEPDEEP_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == SLEEPDEEP_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == SLEEPDEEP_A::VALUE_1 + } +} +impl core::ops::Deref for SLEEPDEEP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLEEPDEEP` writer - Uses Deep Sleep as low power mode"] +pub struct SLEEPDEEP_W<'a> { + w: &'a mut W, +} +impl<'a> SLEEPDEEP_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SLEEPDEEP_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Sleep"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(SLEEPDEEP_A::VALUE_0) + } + #[doc = "Deep sleep"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(SLEEPDEEP_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Send Event on Pending bit\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SEVONPEND_A { + #[doc = "0: Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded"] + VALUE_0 = 0, + #[doc = "1: Enabled events and all interrupts, including disabled interrupts, can wakeup the processor"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SEVONPEND_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SEVONPEND` reader - Send Event on Pending bit"] +pub struct SEVONPEND_R(crate::FieldReader); +impl SEVONPEND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SEVONPEND_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SEVONPEND_A { + match self.bits { + false => SEVONPEND_A::VALUE_0, + true => SEVONPEND_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == SEVONPEND_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == SEVONPEND_A::VALUE_1 + } +} +impl core::ops::Deref for SEVONPEND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEVONPEND` writer - Send Event on Pending bit"] +pub struct SEVONPEND_W<'a> { + w: &'a mut W, +} +impl<'a> SEVONPEND_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SEVONPEND_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(SEVONPEND_A::VALUE_0) + } + #[doc = "Enabled events and all interrupts, including disabled interrupts, can wakeup the processor"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(SEVONPEND_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +impl R { + #[doc = "Bit 1 - Sleep-On-Exit when exiting Handler mode"] + #[inline(always)] + pub fn sleeponexit(&self) -> SLEEPONEXIT_R { + SLEEPONEXIT_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Uses Deep Sleep as low power mode"] + #[inline(always)] + pub fn sleepdeep(&self) -> SLEEPDEEP_R { + SLEEPDEEP_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 4 - Send Event on Pending bit"] + #[inline(always)] + pub fn sevonpend(&self) -> SEVONPEND_R { + SEVONPEND_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 1 - Sleep-On-Exit when exiting Handler mode"] + #[inline(always)] + pub fn sleeponexit(&mut self) -> SLEEPONEXIT_W { + SLEEPONEXIT_W { w: self } + } + #[doc = "Bit 2 - Uses Deep Sleep as low power mode"] + #[inline(always)] + pub fn sleepdeep(&mut self) -> SLEEPDEEP_W { + SLEEPDEEP_W { w: self } + } + #[doc = "Bit 4 - Send Event on Pending bit"] + #[inline(always)] + pub fn sevonpend(&mut self) -> SEVONPEND_W { + SEVONPEND_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "System Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [scr](index.html) module"] +pub struct SCR_SPEC; +impl crate::RegisterSpec for SCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [scr::R](R) reader structure"] +impl crate::Readable for SCR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [scr::W](W) writer structure"] +impl crate::Writable for SCR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SCR to value 0"] +impl crate::Resettable for SCR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/system_control/shcsr.rs b/pac/atsamc20n/src/system_control/shcsr.rs new file mode 100644 index 000000000000..bfba26ac06ad --- /dev/null +++ b/pac/atsamc20n/src/system_control/shcsr.rs @@ -0,0 +1,113 @@ +#[doc = "Register `SHCSR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SHCSR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SVCALLPENDED` reader - "] +pub struct SVCALLPENDED_R(crate::FieldReader); +impl SVCALLPENDED_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SVCALLPENDED_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SVCALLPENDED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SVCALLPENDED` writer - "] +pub struct SVCALLPENDED_W<'a> { + w: &'a mut W, +} +impl<'a> SVCALLPENDED_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 15"] + #[inline(always)] + pub fn svcallpended(&self) -> SVCALLPENDED_R { + SVCALLPENDED_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 15"] + #[inline(always)] + pub fn svcallpended(&mut self) -> SVCALLPENDED_W { + SVCALLPENDED_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "System Handler Control and State Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [shcsr](index.html) module"] +pub struct SHCSR_SPEC; +impl crate::RegisterSpec for SHCSR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [shcsr::R](R) reader structure"] +impl crate::Readable for SHCSR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [shcsr::W](W) writer structure"] +impl crate::Writable for SHCSR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SHCSR to value 0"] +impl crate::Resettable for SHCSR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/system_control/shpr2.rs b/pac/atsamc20n/src/system_control/shpr2.rs new file mode 100644 index 000000000000..5665d6a5e8a9 --- /dev/null +++ b/pac/atsamc20n/src/system_control/shpr2.rs @@ -0,0 +1,103 @@ +#[doc = "Register `SHPR2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SHPR2` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PRI_11` reader - Priority of system handler 11, SVCall"] +pub struct PRI_11_R(crate::FieldReader); +impl PRI_11_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRI_11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PRI_11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRI_11` writer - Priority of system handler 11, SVCall"] +pub struct PRI_11_W<'a> { + w: &'a mut W, +} +impl<'a> PRI_11_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 24)) | ((value as u32 & 0xff) << 24); + self.w + } +} +impl R { + #[doc = "Bits 24:31 - Priority of system handler 11, SVCall"] + #[inline(always)] + pub fn pri_11(&self) -> PRI_11_R { + PRI_11_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 24:31 - Priority of system handler 11, SVCall"] + #[inline(always)] + pub fn pri_11(&mut self) -> PRI_11_W { + PRI_11_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "System Handler Priority Register 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [shpr2](index.html) module"] +pub struct SHPR2_SPEC; +impl crate::RegisterSpec for SHPR2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [shpr2::R](R) reader structure"] +impl crate::Readable for SHPR2_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [shpr2::W](W) writer structure"] +impl crate::Writable for SHPR2_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SHPR2 to value 0"] +impl crate::Resettable for SHPR2_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/system_control/shpr3.rs b/pac/atsamc20n/src/system_control/shpr3.rs new file mode 100644 index 000000000000..cb5a92c53503 --- /dev/null +++ b/pac/atsamc20n/src/system_control/shpr3.rs @@ -0,0 +1,140 @@ +#[doc = "Register `SHPR3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SHPR3` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PRI_14` reader - Priority of system handler 14, PendSV"] +pub struct PRI_14_R(crate::FieldReader); +impl PRI_14_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRI_14_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PRI_14_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRI_14` writer - Priority of system handler 14, PendSV"] +pub struct PRI_14_W<'a> { + w: &'a mut W, +} +impl<'a> PRI_14_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +#[doc = "Field `PRI_15` reader - Priority of system handler 15, SysTick exception"] +pub struct PRI_15_R(crate::FieldReader); +impl PRI_15_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRI_15_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PRI_15_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRI_15` writer - Priority of system handler 15, SysTick exception"] +pub struct PRI_15_W<'a> { + w: &'a mut W, +} +impl<'a> PRI_15_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 24)) | ((value as u32 & 0xff) << 24); + self.w + } +} +impl R { + #[doc = "Bits 16:23 - Priority of system handler 14, PendSV"] + #[inline(always)] + pub fn pri_14(&self) -> PRI_14_R { + PRI_14_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Priority of system handler 15, SysTick exception"] + #[inline(always)] + pub fn pri_15(&self) -> PRI_15_R { + PRI_15_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 16:23 - Priority of system handler 14, PendSV"] + #[inline(always)] + pub fn pri_14(&mut self) -> PRI_14_W { + PRI_14_W { w: self } + } + #[doc = "Bits 24:31 - Priority of system handler 15, SysTick exception"] + #[inline(always)] + pub fn pri_15(&mut self) -> PRI_15_W { + PRI_15_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "System Handler Priority Register 3\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [shpr3](index.html) module"] +pub struct SHPR3_SPEC; +impl crate::RegisterSpec for SHPR3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [shpr3::R](R) reader structure"] +impl crate::Readable for SHPR3_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [shpr3::W](W) writer structure"] +impl crate::Writable for SHPR3_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SHPR3 to value 0"] +impl crate::Resettable for SHPR3_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/system_control/vtor.rs b/pac/atsamc20n/src/system_control/vtor.rs new file mode 100644 index 000000000000..0ee4c7817817 --- /dev/null +++ b/pac/atsamc20n/src/system_control/vtor.rs @@ -0,0 +1,103 @@ +#[doc = "Register `VTOR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `VTOR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TBLOFF` reader - Vector table base offset"] +pub struct TBLOFF_R(crate::FieldReader); +impl TBLOFF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + TBLOFF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TBLOFF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TBLOFF` writer - Vector table base offset"] +pub struct TBLOFF_W<'a> { + w: &'a mut W, +} +impl<'a> TBLOFF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01ff_ffff << 7)) | ((value as u32 & 0x01ff_ffff) << 7); + self.w + } +} +impl R { + #[doc = "Bits 7:31 - Vector table base offset"] + #[inline(always)] + pub fn tbloff(&self) -> TBLOFF_R { + TBLOFF_R::new(((self.bits >> 7) & 0x01ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 7:31 - Vector table base offset"] + #[inline(always)] + pub fn tbloff(&mut self) -> TBLOFF_W { + TBLOFF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Vector Table Offset Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [vtor](index.html) module"] +pub struct VTOR_SPEC; +impl crate::RegisterSpec for VTOR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [vtor::R](R) reader structure"] +impl crate::Readable for VTOR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [vtor::W](W) writer structure"] +impl crate::Writable for VTOR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets VTOR to value 0"] +impl crate::Resettable for VTOR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/tc0.rs b/pac/atsamc20n/src/tc0.rs new file mode 100644 index 000000000000..86e973b276e7 --- /dev/null +++ b/pac/atsamc20n/src/tc0.rs @@ -0,0 +1,146 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved_0_count8: [u8; 0x38], +} +impl RegisterBlock { + #[doc = "0x00..0x38 - 32-bit Counter Mode"] + #[inline(always)] + pub fn count32(&self) -> &COUNT32 { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const COUNT32) } + } + #[doc = "0x00..0x34 - 16-bit Counter Mode"] + #[inline(always)] + pub fn count16(&self) -> &COUNT16 { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const COUNT16) } + } + #[doc = "0x00..0x32 - 8-bit Counter Mode"] + #[inline(always)] + pub fn count8(&self) -> &COUNT8 { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const COUNT8) } + } +} +#[doc = r"Register block"] +#[repr(C)] +pub struct COUNT8 { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - Control B Clear"] + pub ctrlbclr: crate::Reg, + #[doc = "0x05 - Control B Set"] + pub ctrlbset: crate::Reg, + #[doc = "0x06 - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x08 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x09 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x0a - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x0b - Status"] + pub status: crate::Reg, + #[doc = "0x0c - Waveform Generation Control"] + pub wave: crate::Reg, + #[doc = "0x0d - Control C"] + pub drvctrl: crate::Reg, + _reserved10: [u8; 0x01], + #[doc = "0x0f - Debug Control"] + pub dbgctrl: crate::Reg, + #[doc = "0x10 - Synchronization Status"] + pub syncbusy: crate::Reg, + #[doc = "0x14 - COUNT8 Count"] + pub count: crate::Reg, + _reserved13: [u8; 0x06], + #[doc = "0x1b - COUNT8 Period"] + pub per: crate::Reg, + #[doc = "0x1c - COUNT8 Compare and Capture"] + pub cc: [crate::Reg; 2], + _reserved15: [u8; 0x11], + #[doc = "0x2f - COUNT8 Period Buffer"] + pub perbuf: crate::Reg, + #[doc = "0x30 - COUNT8 Compare and Capture Buffer"] + pub ccbuf: [crate::Reg; 2], +} +#[doc = r"Register block"] +#[doc = "8-bit Counter Mode"] +pub mod count8; +#[doc = r"Register block"] +#[repr(C)] +pub struct COUNT16 { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - Control B Clear"] + pub ctrlbclr: crate::Reg, + #[doc = "0x05 - Control B Set"] + pub ctrlbset: crate::Reg, + #[doc = "0x06 - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x08 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x09 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x0a - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x0b - Status"] + pub status: crate::Reg, + #[doc = "0x0c - Waveform Generation Control"] + pub wave: crate::Reg, + #[doc = "0x0d - Control C"] + pub drvctrl: crate::Reg, + _reserved10: [u8; 0x01], + #[doc = "0x0f - Debug Control"] + pub dbgctrl: crate::Reg, + #[doc = "0x10 - Synchronization Status"] + pub syncbusy: crate::Reg, + #[doc = "0x14 - COUNT16 Count"] + pub count: crate::Reg, + _reserved13: [u8; 0x06], + #[doc = "0x1c - COUNT16 Compare and Capture"] + pub cc: [crate::Reg; 2], + _reserved14: [u8; 0x10], + #[doc = "0x30 - COUNT16 Compare and Capture Buffer"] + pub ccbuf: [crate::Reg; 2], +} +#[doc = r"Register block"] +#[doc = "16-bit Counter Mode"] +pub mod count16; +#[doc = r"Register block"] +#[repr(C)] +pub struct COUNT32 { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - Control B Clear"] + pub ctrlbclr: crate::Reg, + #[doc = "0x05 - Control B Set"] + pub ctrlbset: crate::Reg, + #[doc = "0x06 - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x08 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x09 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x0a - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x0b - Status"] + pub status: crate::Reg, + #[doc = "0x0c - Waveform Generation Control"] + pub wave: crate::Reg, + #[doc = "0x0d - Control C"] + pub drvctrl: crate::Reg, + _reserved10: [u8; 0x01], + #[doc = "0x0f - Debug Control"] + pub dbgctrl: crate::Reg, + #[doc = "0x10 - Synchronization Status"] + pub syncbusy: crate::Reg, + #[doc = "0x14 - COUNT32 Count"] + pub count: crate::Reg, + _reserved13: [u8; 0x04], + #[doc = "0x1c..0x24 - COUNT32 Compare and Capture"] + pub cc: [crate::Reg; 2], + _reserved14: [u8; 0x0c], + #[doc = "0x30..0x38 - COUNT32 Compare and Capture Buffer"] + pub ccbuf: [crate::Reg; 2], +} +#[doc = r"Register block"] +#[doc = "32-bit Counter Mode"] +pub mod count32; diff --git a/pac/atsamc20n/src/tc0/count16.rs b/pac/atsamc20n/src/tc0/count16.rs new file mode 100644 index 000000000000..5bd1e88c7efb --- /dev/null +++ b/pac/atsamc20n/src/tc0/count16.rs @@ -0,0 +1,60 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "CTRLBCLR register accessor: an alias for `Reg`"] +pub type CTRLBCLR = crate::Reg; +#[doc = "Control B Clear"] +pub mod ctrlbclr; +#[doc = "CTRLBSET register accessor: an alias for `Reg`"] +pub type CTRLBSET = crate::Reg; +#[doc = "Control B Set"] +pub mod ctrlbset; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "WAVE register accessor: an alias for `Reg`"] +pub type WAVE = crate::Reg; +#[doc = "Waveform Generation Control"] +pub mod wave; +#[doc = "DRVCTRL register accessor: an alias for `Reg`"] +pub type DRVCTRL = crate::Reg; +#[doc = "Control C"] +pub mod drvctrl; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Status"] +pub mod syncbusy; +#[doc = "COUNT register accessor: an alias for `Reg`"] +pub type COUNT = crate::Reg; +#[doc = "COUNT16 Count"] +pub mod count; +#[doc = "CC register accessor: an alias for `Reg`"] +pub type CC = crate::Reg; +#[doc = "COUNT16 Compare and Capture"] +pub mod cc; +#[doc = "CCBUF register accessor: an alias for `Reg`"] +pub type CCBUF = crate::Reg; +#[doc = "COUNT16 Compare and Capture Buffer"] +pub mod ccbuf; diff --git a/pac/atsamc20n/src/tc0/count16/cc.rs b/pac/atsamc20n/src/tc0/count16/cc.rs new file mode 100644 index 000000000000..b6f975905e31 --- /dev/null +++ b/pac/atsamc20n/src/tc0/count16/cc.rs @@ -0,0 +1,104 @@ +#[doc = "Register `CC[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CC[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CC` reader - Counter/Compare Value"] +pub struct CC_R(crate::FieldReader); +impl CC_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + CC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC` writer - Counter/Compare Value"] +pub struct CC_W<'a> { + w: &'a mut W, +} +impl<'a> CC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Counter/Compare Value"] + #[inline(always)] + pub fn cc(&self) -> CC_R { + CC_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Counter/Compare Value"] + #[inline(always)] + pub fn cc(&mut self) -> CC_W { + CC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT16 Compare and Capture\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc](index.html) module"] +pub struct CC_SPEC; +impl crate::RegisterSpec for CC_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [cc::R](R) reader structure"] +impl crate::Readable for CC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cc::W](W) writer structure"] +impl crate::Writable for CC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CC[%s] +to value 0"] +impl crate::Resettable for CC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/tc0/count16/ccbuf.rs b/pac/atsamc20n/src/tc0/count16/ccbuf.rs new file mode 100644 index 000000000000..2f922bba8d31 --- /dev/null +++ b/pac/atsamc20n/src/tc0/count16/ccbuf.rs @@ -0,0 +1,104 @@ +#[doc = "Register `CCBUF[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CCBUF[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CCBUF` reader - Counter/Compare Buffer Value"] +pub struct CCBUF_R(crate::FieldReader); +impl CCBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + CCBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUF` writer - Counter/Compare Buffer Value"] +pub struct CCBUF_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Counter/Compare Buffer Value"] + #[inline(always)] + pub fn ccbuf(&self) -> CCBUF_R { + CCBUF_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Counter/Compare Buffer Value"] + #[inline(always)] + pub fn ccbuf(&mut self) -> CCBUF_W { + CCBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT16 Compare and Capture Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccbuf](index.html) module"] +pub struct CCBUF_SPEC; +impl crate::RegisterSpec for CCBUF_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ccbuf::R](R) reader structure"] +impl crate::Readable for CCBUF_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ccbuf::W](W) writer structure"] +impl crate::Writable for CCBUF_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CCBUF[%s] +to value 0"] +impl crate::Resettable for CCBUF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/tc0/count16/count.rs b/pac/atsamc20n/src/tc0/count16/count.rs new file mode 100644 index 000000000000..5d26b509abb1 --- /dev/null +++ b/pac/atsamc20n/src/tc0/count16/count.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT16 Count\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count](index.html) module"] +pub struct COUNT_SPEC; +impl crate::RegisterSpec for COUNT_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [count::R](R) reader structure"] +impl crate::Readable for COUNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count::W](W) writer structure"] +impl crate::Writable for COUNT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT to value 0"] +impl crate::Resettable for COUNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/tc0/count16/ctrla.rs b/pac/atsamc20n/src/tc0/count16/ctrla.rs new file mode 100644 index 000000000000..e1be912fdfcd --- /dev/null +++ b/pac/atsamc20n/src/tc0/count16/ctrla.rs @@ -0,0 +1,1049 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Timer Counter Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: Counter in 16-bit mode"] + COUNT16 = 0, + #[doc = "1: Counter in 8-bit mode"] + COUNT8 = 1, + #[doc = "2: Counter in 32-bit mode"] + COUNT32 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Timer Counter Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::COUNT16), + 1 => Some(MODE_A::COUNT8), + 2 => Some(MODE_A::COUNT32), + _ => None, + } + } + #[doc = "Checks if the value of the field is `COUNT16`"] + #[inline(always)] + pub fn is_count16(&self) -> bool { + **self == MODE_A::COUNT16 + } + #[doc = "Checks if the value of the field is `COUNT8`"] + #[inline(always)] + pub fn is_count8(&self) -> bool { + **self == MODE_A::COUNT8 + } + #[doc = "Checks if the value of the field is `COUNT32`"] + #[inline(always)] + pub fn is_count32(&self) -> bool { + **self == MODE_A::COUNT32 + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Timer Counter Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Counter in 16-bit mode"] + #[inline(always)] + pub fn count16(self) -> &'a mut W { + self.variant(MODE_A::COUNT16) + } + #[doc = "Counter in 8-bit mode"] + #[inline(always)] + pub fn count8(self) -> &'a mut W { + self.variant(MODE_A::COUNT8) + } + #[doc = "Counter in 32-bit mode"] + #[inline(always)] + pub fn count32(self) -> &'a mut W { + self.variant(MODE_A::COUNT32) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u32 & 0x03) << 2); + self.w + } +} +#[doc = "Prescaler and Counter Synchronization\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCSYNC_A { + #[doc = "0: Reload or reset the counter on next generic clock"] + GCLK = 0, + #[doc = "1: Reload or reset the counter on next prescaler clock"] + PRESC = 1, + #[doc = "2: Reload or reset the counter on next generic clock and reset the prescaler counter"] + RESYNC = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCSYNC_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCSYNC` reader - Prescaler and Counter Synchronization"] +pub struct PRESCSYNC_R(crate::FieldReader); +impl PRESCSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCSYNC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCSYNC_A::GCLK), + 1 => Some(PRESCSYNC_A::PRESC), + 2 => Some(PRESCSYNC_A::RESYNC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `GCLK`"] + #[inline(always)] + pub fn is_gclk(&self) -> bool { + **self == PRESCSYNC_A::GCLK + } + #[doc = "Checks if the value of the field is `PRESC`"] + #[inline(always)] + pub fn is_presc(&self) -> bool { + **self == PRESCSYNC_A::PRESC + } + #[doc = "Checks if the value of the field is `RESYNC`"] + #[inline(always)] + pub fn is_resync(&self) -> bool { + **self == PRESCSYNC_A::RESYNC + } +} +impl core::ops::Deref for PRESCSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCSYNC` writer - Prescaler and Counter Synchronization"] +pub struct PRESCSYNC_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCSYNC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCSYNC_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Reload or reset the counter on next generic clock"] + #[inline(always)] + pub fn gclk(self) -> &'a mut W { + self.variant(PRESCSYNC_A::GCLK) + } + #[doc = "Reload or reset the counter on next prescaler clock"] + #[inline(always)] + pub fn presc(self) -> &'a mut W { + self.variant(PRESCSYNC_A::PRESC) + } + #[doc = "Reload or reset the counter on next generic clock and reset the prescaler counter"] + #[inline(always)] + pub fn resync(self) -> &'a mut W { + self.variant(PRESCSYNC_A::RESYNC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u32 & 0x03) << 4); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - Clock On Demand"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - Clock On Demand"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: Prescaler: GCLK_TC"] + DIV1 = 0, + #[doc = "1: Prescaler: GCLK_TC/2"] + DIV2 = 1, + #[doc = "2: Prescaler: GCLK_TC/4"] + DIV4 = 2, + #[doc = "3: Prescaler: GCLK_TC/8"] + DIV8 = 3, + #[doc = "4: Prescaler: GCLK_TC/16"] + DIV16 = 4, + #[doc = "5: Prescaler: GCLK_TC/64"] + DIV64 = 5, + #[doc = "6: Prescaler: GCLK_TC/256"] + DIV256 = 6, + #[doc = "7: Prescaler: GCLK_TC/1024"] + DIV1024 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PRESCALER_A { + match self.bits { + 0 => PRESCALER_A::DIV1, + 1 => PRESCALER_A::DIV2, + 2 => PRESCALER_A::DIV4, + 3 => PRESCALER_A::DIV8, + 4 => PRESCALER_A::DIV16, + 5 => PRESCALER_A::DIV64, + 6 => PRESCALER_A::DIV256, + 7 => PRESCALER_A::DIV1024, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == PRESCALER_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PRESCALER_A::DIV1024 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Prescaler: GCLK_TC"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1) + } + #[doc = "Prescaler: GCLK_TC/2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "Prescaler: GCLK_TC/4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "Prescaler: GCLK_TC/8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "Prescaler: GCLK_TC/16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "Prescaler: GCLK_TC/64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "Prescaler: GCLK_TC/256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = "Prescaler: GCLK_TC/1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +#[doc = "Field `ALOCK` reader - Auto Lock"] +pub struct ALOCK_R(crate::FieldReader); +impl ALOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALOCK` writer - Auto Lock"] +pub struct ALOCK_W<'a> { + w: &'a mut W, +} +impl<'a> ALOCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `CAPTEN0` reader - Capture Channel 0 Enable"] +pub struct CAPTEN0_R(crate::FieldReader); +impl CAPTEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CAPTEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CAPTEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAPTEN0` writer - Capture Channel 0 Enable"] +pub struct CAPTEN0_W<'a> { + w: &'a mut W, +} +impl<'a> CAPTEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `CAPTEN1` reader - Capture Channel 1 Enable"] +pub struct CAPTEN1_R(crate::FieldReader); +impl CAPTEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CAPTEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CAPTEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAPTEN1` writer - Capture Channel 1 Enable"] +pub struct CAPTEN1_W<'a> { + w: &'a mut W, +} +impl<'a> CAPTEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `COPEN0` reader - Capture On Pin 0 Enable"] +pub struct COPEN0_R(crate::FieldReader); +impl COPEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COPEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COPEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COPEN0` writer - Capture On Pin 0 Enable"] +pub struct COPEN0_W<'a> { + w: &'a mut W, +} +impl<'a> COPEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `COPEN1` reader - Capture On Pin 1 Enable"] +pub struct COPEN1_R(crate::FieldReader); +impl COPEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COPEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COPEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COPEN1` writer - Capture On Pin 1 Enable"] +pub struct COPEN1_W<'a> { + w: &'a mut W, +} +impl<'a> COPEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Capture Mode Channel 0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CAPTMODE0_A { + #[doc = "0: Default capture"] + DEFAULT = 0, + #[doc = "1: Minimum capture"] + CAPTMIN = 1, + #[doc = "2: Maximum capture"] + CAPTMAX = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CAPTMODE0_A) -> Self { + variant as _ + } +} +#[doc = "Field `CAPTMODE0` reader - Capture Mode Channel 0"] +pub struct CAPTMODE0_R(crate::FieldReader); +impl CAPTMODE0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CAPTMODE0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CAPTMODE0_A::DEFAULT), + 1 => Some(CAPTMODE0_A::CAPTMIN), + 2 => Some(CAPTMODE0_A::CAPTMAX), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DEFAULT`"] + #[inline(always)] + pub fn is_default(&self) -> bool { + **self == CAPTMODE0_A::DEFAULT + } + #[doc = "Checks if the value of the field is `CAPTMIN`"] + #[inline(always)] + pub fn is_captmin(&self) -> bool { + **self == CAPTMODE0_A::CAPTMIN + } + #[doc = "Checks if the value of the field is `CAPTMAX`"] + #[inline(always)] + pub fn is_captmax(&self) -> bool { + **self == CAPTMODE0_A::CAPTMAX + } +} +impl core::ops::Deref for CAPTMODE0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAPTMODE0` writer - Capture Mode Channel 0"] +pub struct CAPTMODE0_W<'a> { + w: &'a mut W, +} +impl<'a> CAPTMODE0_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CAPTMODE0_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Default capture"] + #[inline(always)] + pub fn default(self) -> &'a mut W { + self.variant(CAPTMODE0_A::DEFAULT) + } + #[doc = "Minimum capture"] + #[inline(always)] + pub fn captmin(self) -> &'a mut W { + self.variant(CAPTMODE0_A::CAPTMIN) + } + #[doc = "Maximum capture"] + #[inline(always)] + pub fn captmax(self) -> &'a mut W { + self.variant(CAPTMODE0_A::CAPTMAX) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 24)) | ((value as u32 & 0x03) << 24); + self.w + } +} +#[doc = "Capture mode Channel 1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CAPTMODE1_A { + #[doc = "0: Default capture"] + DEFAULT = 0, + #[doc = "1: Minimum capture"] + CAPTMIN = 1, + #[doc = "2: Maximum capture"] + CAPTMAX = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CAPTMODE1_A) -> Self { + variant as _ + } +} +#[doc = "Field `CAPTMODE1` reader - Capture mode Channel 1"] +pub struct CAPTMODE1_R(crate::FieldReader); +impl CAPTMODE1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CAPTMODE1_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CAPTMODE1_A::DEFAULT), + 1 => Some(CAPTMODE1_A::CAPTMIN), + 2 => Some(CAPTMODE1_A::CAPTMAX), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DEFAULT`"] + #[inline(always)] + pub fn is_default(&self) -> bool { + **self == CAPTMODE1_A::DEFAULT + } + #[doc = "Checks if the value of the field is `CAPTMIN`"] + #[inline(always)] + pub fn is_captmin(&self) -> bool { + **self == CAPTMODE1_A::CAPTMIN + } + #[doc = "Checks if the value of the field is `CAPTMAX`"] + #[inline(always)] + pub fn is_captmax(&self) -> bool { + **self == CAPTMODE1_A::CAPTMAX + } +} +impl core::ops::Deref for CAPTMODE1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAPTMODE1` writer - Capture mode Channel 1"] +pub struct CAPTMODE1_W<'a> { + w: &'a mut W, +} +impl<'a> CAPTMODE1_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CAPTMODE1_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Default capture"] + #[inline(always)] + pub fn default(self) -> &'a mut W { + self.variant(CAPTMODE1_A::DEFAULT) + } + #[doc = "Minimum capture"] + #[inline(always)] + pub fn captmin(self) -> &'a mut W { + self.variant(CAPTMODE1_A::CAPTMIN) + } + #[doc = "Maximum capture"] + #[inline(always)] + pub fn captmax(self) -> &'a mut W { + self.variant(CAPTMODE1_A::CAPTMAX) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 27)) | ((value as u32 & 0x03) << 27); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:3 - Timer Counter Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bits 4:5 - Prescaler and Counter Synchronization"] + #[inline(always)] + pub fn prescsync(&self) -> PRESCSYNC_R { + PRESCSYNC_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Clock On Demand"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 11 - Auto Lock"] + #[inline(always)] + pub fn alock(&self) -> ALOCK_R { + ALOCK_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 16 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn capten0(&self) -> CAPTEN0_R { + CAPTEN0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn capten1(&self) -> CAPTEN1_R { + CAPTEN1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 20 - Capture On Pin 0 Enable"] + #[inline(always)] + pub fn copen0(&self) -> COPEN0_R { + COPEN0_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Capture On Pin 1 Enable"] + #[inline(always)] + pub fn copen1(&self) -> COPEN1_R { + COPEN1_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bits 24:25 - Capture Mode Channel 0"] + #[inline(always)] + pub fn captmode0(&self) -> CAPTMODE0_R { + CAPTMODE0_R::new(((self.bits >> 24) & 0x03) as u8) + } + #[doc = "Bits 27:28 - Capture mode Channel 1"] + #[inline(always)] + pub fn captmode1(&self) -> CAPTMODE1_R { + CAPTMODE1_R::new(((self.bits >> 27) & 0x03) as u8) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:3 - Timer Counter Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bits 4:5 - Prescaler and Counter Synchronization"] + #[inline(always)] + pub fn prescsync(&mut self) -> PRESCSYNC_W { + PRESCSYNC_W { w: self } + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - Clock On Demand"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Bit 11 - Auto Lock"] + #[inline(always)] + pub fn alock(&mut self) -> ALOCK_W { + ALOCK_W { w: self } + } + #[doc = "Bit 16 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn capten0(&mut self) -> CAPTEN0_W { + CAPTEN0_W { w: self } + } + #[doc = "Bit 17 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn capten1(&mut self) -> CAPTEN1_W { + CAPTEN1_W { w: self } + } + #[doc = "Bit 20 - Capture On Pin 0 Enable"] + #[inline(always)] + pub fn copen0(&mut self) -> COPEN0_W { + COPEN0_W { w: self } + } + #[doc = "Bit 21 - Capture On Pin 1 Enable"] + #[inline(always)] + pub fn copen1(&mut self) -> COPEN1_W { + COPEN1_W { w: self } + } + #[doc = "Bits 24:25 - Capture Mode Channel 0"] + #[inline(always)] + pub fn captmode0(&mut self) -> CAPTMODE0_W { + CAPTMODE0_W { w: self } + } + #[doc = "Bits 27:28 - Capture mode Channel 1"] + #[inline(always)] + pub fn captmode1(&mut self) -> CAPTMODE1_W { + CAPTMODE1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/tc0/count16/ctrlbclr.rs b/pac/atsamc20n/src/tc0/count16/ctrlbclr.rs new file mode 100644 index 000000000000..76265674036a --- /dev/null +++ b/pac/atsamc20n/src/tc0/count16/ctrlbclr.rs @@ -0,0 +1,345 @@ +#[doc = "Register `CTRLBCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Counter Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `LUPD` reader - Lock Update"] +pub struct LUPD_R(crate::FieldReader); +impl LUPD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LUPD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LUPD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LUPD` writer - Lock Update"] +pub struct LUPD_W<'a> { + w: &'a mut W, +} +impl<'a> LUPD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ONESHOT` reader - One-Shot on Counter"] +pub struct ONESHOT_R(crate::FieldReader); +impl ONESHOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONESHOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONESHOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONESHOT` writer - One-Shot on Counter"] +pub struct ONESHOT_W<'a> { + w: &'a mut W, +} +impl<'a> ONESHOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Force a start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force a stop"] + STOP = 2, + #[doc = "3: Force update of double-buffered register"] + UPDATE = 3, + #[doc = "4: Force a read synchronization of COUNT"] + READSYNC = 4, + #[doc = "5: One-shot DMA trigger"] + DMAOS = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NONE), + 1 => Some(CMD_A::RETRIGGER), + 2 => Some(CMD_A::STOP), + 3 => Some(CMD_A::UPDATE), + 4 => Some(CMD_A::READSYNC), + 5 => Some(CMD_A::DMAOS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == CMD_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == CMD_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == CMD_A::STOP + } + #[doc = "Checks if the value of the field is `UPDATE`"] + #[inline(always)] + pub fn is_update(&self) -> bool { + **self == CMD_A::UPDATE + } + #[doc = "Checks if the value of the field is `READSYNC`"] + #[inline(always)] + pub fn is_readsync(&self) -> bool { + **self == CMD_A::READSYNC + } + #[doc = "Checks if the value of the field is `DMAOS`"] + #[inline(always)] + pub fn is_dmaos(&self) -> bool { + **self == CMD_A::DMAOS + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMD_A::NONE) + } + #[doc = "Force a start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMD_A::RETRIGGER) + } + #[doc = "Force a stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMD_A::STOP) + } + #[doc = "Force update of double-buffered register"] + #[inline(always)] + pub fn update(self) -> &'a mut W { + self.variant(CMD_A::UPDATE) + } + #[doc = "Force a read synchronization of COUNT"] + #[inline(always)] + pub fn readsync(self) -> &'a mut W { + self.variant(CMD_A::READSYNC) + } + #[doc = "One-shot DMA trigger"] + #[inline(always)] + pub fn dmaos(self) -> &'a mut W { + self.variant(CMD_A::DMAOS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 5)) | ((value as u8 & 0x07) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&self) -> LUPD_R { + LUPD_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 5) & 0x07) as u8) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&mut self) -> LUPD_W { + LUPD_W { w: self } + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&mut self) -> ONESHOT_W { + ONESHOT_W { w: self } + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbclr](index.html) module"] +pub struct CTRLBCLR_SPEC; +impl crate::RegisterSpec for CTRLBCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbclr::R](R) reader structure"] +impl crate::Readable for CTRLBCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbclr::W](W) writer structure"] +impl crate::Writable for CTRLBCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLBCLR to value 0"] +impl crate::Resettable for CTRLBCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/tc0/count16/ctrlbset.rs b/pac/atsamc20n/src/tc0/count16/ctrlbset.rs new file mode 100644 index 000000000000..610914c9c7c8 --- /dev/null +++ b/pac/atsamc20n/src/tc0/count16/ctrlbset.rs @@ -0,0 +1,345 @@ +#[doc = "Register `CTRLBSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Counter Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `LUPD` reader - Lock Update"] +pub struct LUPD_R(crate::FieldReader); +impl LUPD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LUPD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LUPD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LUPD` writer - Lock Update"] +pub struct LUPD_W<'a> { + w: &'a mut W, +} +impl<'a> LUPD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ONESHOT` reader - One-Shot on Counter"] +pub struct ONESHOT_R(crate::FieldReader); +impl ONESHOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONESHOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONESHOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONESHOT` writer - One-Shot on Counter"] +pub struct ONESHOT_W<'a> { + w: &'a mut W, +} +impl<'a> ONESHOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Force a start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force a stop"] + STOP = 2, + #[doc = "3: Force update of double-buffered register"] + UPDATE = 3, + #[doc = "4: Force a read synchronization of COUNT"] + READSYNC = 4, + #[doc = "5: One-shot DMA trigger"] + DMAOS = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NONE), + 1 => Some(CMD_A::RETRIGGER), + 2 => Some(CMD_A::STOP), + 3 => Some(CMD_A::UPDATE), + 4 => Some(CMD_A::READSYNC), + 5 => Some(CMD_A::DMAOS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == CMD_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == CMD_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == CMD_A::STOP + } + #[doc = "Checks if the value of the field is `UPDATE`"] + #[inline(always)] + pub fn is_update(&self) -> bool { + **self == CMD_A::UPDATE + } + #[doc = "Checks if the value of the field is `READSYNC`"] + #[inline(always)] + pub fn is_readsync(&self) -> bool { + **self == CMD_A::READSYNC + } + #[doc = "Checks if the value of the field is `DMAOS`"] + #[inline(always)] + pub fn is_dmaos(&self) -> bool { + **self == CMD_A::DMAOS + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMD_A::NONE) + } + #[doc = "Force a start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMD_A::RETRIGGER) + } + #[doc = "Force a stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMD_A::STOP) + } + #[doc = "Force update of double-buffered register"] + #[inline(always)] + pub fn update(self) -> &'a mut W { + self.variant(CMD_A::UPDATE) + } + #[doc = "Force a read synchronization of COUNT"] + #[inline(always)] + pub fn readsync(self) -> &'a mut W { + self.variant(CMD_A::READSYNC) + } + #[doc = "One-shot DMA trigger"] + #[inline(always)] + pub fn dmaos(self) -> &'a mut W { + self.variant(CMD_A::DMAOS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 5)) | ((value as u8 & 0x07) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&self) -> LUPD_R { + LUPD_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 5) & 0x07) as u8) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&mut self) -> LUPD_W { + LUPD_W { w: self } + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&mut self) -> ONESHOT_W { + ONESHOT_W { w: self } + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbset](index.html) module"] +pub struct CTRLBSET_SPEC; +impl crate::RegisterSpec for CTRLBSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbset::R](R) reader structure"] +impl crate::Readable for CTRLBSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbset::W](W) writer structure"] +impl crate::Writable for CTRLBSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLBSET to value 0"] +impl crate::Resettable for CTRLBSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/tc0/count16/dbgctrl.rs b/pac/atsamc20n/src/tc0/count16/dbgctrl.rs new file mode 100644 index 000000000000..0383e70d0429 --- /dev/null +++ b/pac/atsamc20n/src/tc0/count16/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Run During Debug"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Run During Debug"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/tc0/count16/drvctrl.rs b/pac/atsamc20n/src/tc0/count16/drvctrl.rs new file mode 100644 index 000000000000..323926b4b22d --- /dev/null +++ b/pac/atsamc20n/src/tc0/count16/drvctrl.rs @@ -0,0 +1,160 @@ +#[doc = "Register `DRVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DRVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INVEN0` reader - Output Waveform Invert Enable 0"] +pub struct INVEN0_R(crate::FieldReader); +impl INVEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN0` writer - Output Waveform Invert Enable 0"] +pub struct INVEN0_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `INVEN1` reader - Output Waveform Invert Enable 1"] +pub struct INVEN1_R(crate::FieldReader); +impl INVEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN1` writer - Output Waveform Invert Enable 1"] +pub struct INVEN1_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - Output Waveform Invert Enable 0"] + #[inline(always)] + pub fn inven0(&self) -> INVEN0_R { + INVEN0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Output Waveform Invert Enable 1"] + #[inline(always)] + pub fn inven1(&self) -> INVEN1_R { + INVEN1_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Output Waveform Invert Enable 0"] + #[inline(always)] + pub fn inven0(&mut self) -> INVEN0_W { + INVEN0_W { w: self } + } + #[doc = "Bit 1 - Output Waveform Invert Enable 1"] + #[inline(always)] + pub fn inven1(&mut self) -> INVEN1_W { + INVEN1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control C\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [drvctrl](index.html) module"] +pub struct DRVCTRL_SPEC; +impl crate::RegisterSpec for DRVCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [drvctrl::R](R) reader structure"] +impl crate::Readable for DRVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [drvctrl::W](W) writer structure"] +impl crate::Writable for DRVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DRVCTRL to value 0"] +impl crate::Resettable for DRVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/tc0/count16/evctrl.rs b/pac/atsamc20n/src/tc0/count16/evctrl.rs new file mode 100644 index 000000000000..7d4c38d486c1 --- /dev/null +++ b/pac/atsamc20n/src/tc0/count16/evctrl.rs @@ -0,0 +1,465 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Event Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EVACT_A { + #[doc = "0: Event action disabled"] + OFF = 0, + #[doc = "1: Start, restart or retrigger TC on event"] + RETRIGGER = 1, + #[doc = "2: Count on event"] + COUNT = 2, + #[doc = "3: Start TC on event"] + START = 3, + #[doc = "4: Time stamp capture"] + STAMP = 4, + #[doc = "5: Period catured in CC0, pulse width in CC1"] + PPW = 5, + #[doc = "6: Period catured in CC1, pulse width in CC0"] + PWP = 6, + #[doc = "7: Pulse width capture"] + PW = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EVACT_A) -> Self { + variant as _ + } +} +#[doc = "Field `EVACT` reader - Event Action"] +pub struct EVACT_R(crate::FieldReader); +impl EVACT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVACT_A { + match self.bits { + 0 => EVACT_A::OFF, + 1 => EVACT_A::RETRIGGER, + 2 => EVACT_A::COUNT, + 3 => EVACT_A::START, + 4 => EVACT_A::STAMP, + 5 => EVACT_A::PPW, + 6 => EVACT_A::PWP, + 7 => EVACT_A::PW, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == EVACT_A::OFF + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == EVACT_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `COUNT`"] + #[inline(always)] + pub fn is_count(&self) -> bool { + **self == EVACT_A::COUNT + } + #[doc = "Checks if the value of the field is `START`"] + #[inline(always)] + pub fn is_start(&self) -> bool { + **self == EVACT_A::START + } + #[doc = "Checks if the value of the field is `STAMP`"] + #[inline(always)] + pub fn is_stamp(&self) -> bool { + **self == EVACT_A::STAMP + } + #[doc = "Checks if the value of the field is `PPW`"] + #[inline(always)] + pub fn is_ppw(&self) -> bool { + **self == EVACT_A::PPW + } + #[doc = "Checks if the value of the field is `PWP`"] + #[inline(always)] + pub fn is_pwp(&self) -> bool { + **self == EVACT_A::PWP + } + #[doc = "Checks if the value of the field is `PW`"] + #[inline(always)] + pub fn is_pw(&self) -> bool { + **self == EVACT_A::PW + } +} +impl core::ops::Deref for EVACT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT` writer - Event Action"] +pub struct EVACT_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EVACT_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Event action disabled"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(EVACT_A::OFF) + } + #[doc = "Start, restart or retrigger TC on event"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(EVACT_A::RETRIGGER) + } + #[doc = "Count on event"] + #[inline(always)] + pub fn count(self) -> &'a mut W { + self.variant(EVACT_A::COUNT) + } + #[doc = "Start TC on event"] + #[inline(always)] + pub fn start(self) -> &'a mut W { + self.variant(EVACT_A::START) + } + #[doc = "Time stamp capture"] + #[inline(always)] + pub fn stamp(self) -> &'a mut W { + self.variant(EVACT_A::STAMP) + } + #[doc = "Period catured in CC0, pulse width in CC1"] + #[inline(always)] + pub fn ppw(self) -> &'a mut W { + self.variant(EVACT_A::PPW) + } + #[doc = "Period catured in CC1, pulse width in CC0"] + #[inline(always)] + pub fn pwp(self) -> &'a mut W { + self.variant(EVACT_A::PWP) + } + #[doc = "Pulse width capture"] + #[inline(always)] + pub fn pw(self) -> &'a mut W { + self.variant(EVACT_A::PW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u16 & 0x07); + self.w + } +} +#[doc = "Field `TCINV` reader - TC Event Input Polarity"] +pub struct TCINV_R(crate::FieldReader); +impl TCINV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCINV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCINV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCINV` writer - TC Event Input Polarity"] +pub struct TCINV_W<'a> { + w: &'a mut W, +} +impl<'a> TCINV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `TCEI` reader - TC Event Enable"] +pub struct TCEI_R(crate::FieldReader); +impl TCEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCEI` writer - TC Event Enable"] +pub struct TCEI_W<'a> { + w: &'a mut W, +} +impl<'a> TCEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `OVFEO` reader - Event Output Enable"] +pub struct OVFEO_R(crate::FieldReader); +impl OVFEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVFEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVFEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVFEO` writer - Event Output Enable"] +pub struct OVFEO_W<'a> { + w: &'a mut W, +} +impl<'a> OVFEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `MCEO0` reader - MC Event Output Enable 0"] +pub struct MCEO0_R(crate::FieldReader); +impl MCEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO0` writer - MC Event Output Enable 0"] +pub struct MCEO0_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u16 & 0x01) << 12); + self.w + } +} +#[doc = "Field `MCEO1` reader - MC Event Output Enable 1"] +pub struct MCEO1_R(crate::FieldReader); +impl MCEO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO1` writer - MC Event Output Enable 1"] +pub struct MCEO1_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u16 & 0x01) << 13); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Event Action"] + #[inline(always)] + pub fn evact(&self) -> EVACT_R { + EVACT_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 4 - TC Event Input Polarity"] + #[inline(always)] + pub fn tcinv(&self) -> TCINV_R { + TCINV_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - TC Event Enable"] + #[inline(always)] + pub fn tcei(&self) -> TCEI_R { + TCEI_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 8 - Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&self) -> OVFEO_R { + OVFEO_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 12 - MC Event Output Enable 0"] + #[inline(always)] + pub fn mceo0(&self) -> MCEO0_R { + MCEO0_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - MC Event Output Enable 1"] + #[inline(always)] + pub fn mceo1(&self) -> MCEO1_R { + MCEO1_R::new(((self.bits >> 13) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Event Action"] + #[inline(always)] + pub fn evact(&mut self) -> EVACT_W { + EVACT_W { w: self } + } + #[doc = "Bit 4 - TC Event Input Polarity"] + #[inline(always)] + pub fn tcinv(&mut self) -> TCINV_W { + TCINV_W { w: self } + } + #[doc = "Bit 5 - TC Event Enable"] + #[inline(always)] + pub fn tcei(&mut self) -> TCEI_W { + TCEI_W { w: self } + } + #[doc = "Bit 8 - Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&mut self) -> OVFEO_W { + OVFEO_W { w: self } + } + #[doc = "Bit 12 - MC Event Output Enable 0"] + #[inline(always)] + pub fn mceo0(&mut self) -> MCEO0_W { + MCEO0_W { w: self } + } + #[doc = "Bit 13 - MC Event Output Enable 1"] + #[inline(always)] + pub fn mceo1(&mut self) -> MCEO1_W { + MCEO1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/tc0/count16/intenclr.rs b/pac/atsamc20n/src/tc0/count16/intenclr.rs new file mode 100644 index 000000000000..af01ef5b7dca --- /dev/null +++ b/pac/atsamc20n/src/tc0/count16/intenclr.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - OVF Interrupt Disable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - OVF Interrupt Disable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - ERR Interrupt Disable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - ERR Interrupt Disable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MC0` reader - MC Interrupt Disable 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - MC Interrupt Disable 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - MC Interrupt Disable 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - MC Interrupt Disable 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - OVF Interrupt Disable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ERR Interrupt Disable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - MC Interrupt Disable 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - MC Interrupt Disable 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - OVF Interrupt Disable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - ERR Interrupt Disable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 4 - MC Interrupt Disable 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - MC Interrupt Disable 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/tc0/count16/intenset.rs b/pac/atsamc20n/src/tc0/count16/intenset.rs new file mode 100644 index 000000000000..0e1883a2f20a --- /dev/null +++ b/pac/atsamc20n/src/tc0/count16/intenset.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - OVF Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - OVF Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - ERR Interrupt Enable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - ERR Interrupt Enable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MC0` reader - MC Interrupt Enable 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - MC Interrupt Enable 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - MC Interrupt Enable 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - MC Interrupt Enable 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - OVF Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ERR Interrupt Enable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - MC Interrupt Enable 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - MC Interrupt Enable 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - OVF Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - ERR Interrupt Enable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 4 - MC Interrupt Enable 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - MC Interrupt Enable 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/tc0/count16/intflag.rs b/pac/atsamc20n/src/tc0/count16/intflag.rs new file mode 100644 index 000000000000..1dddffaf8e7f --- /dev/null +++ b/pac/atsamc20n/src/tc0/count16/intflag.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - OVF Interrupt Flag"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - OVF Interrupt Flag"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - ERR Interrupt Flag"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - ERR Interrupt Flag"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MC0` reader - MC Interrupt Flag 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - MC Interrupt Flag 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - MC Interrupt Flag 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - MC Interrupt Flag 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - OVF Interrupt Flag"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ERR Interrupt Flag"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - MC Interrupt Flag 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - MC Interrupt Flag 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - OVF Interrupt Flag"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - ERR Interrupt Flag"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 4 - MC Interrupt Flag 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - MC Interrupt Flag 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/tc0/count16/status.rs b/pac/atsamc20n/src/tc0/count16/status.rs new file mode 100644 index 000000000000..5088af446830 --- /dev/null +++ b/pac/atsamc20n/src/tc0/count16/status.rs @@ -0,0 +1,301 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `STOP` reader - Stop Status Flag"] +pub struct STOP_R(crate::FieldReader); +impl STOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STOP` writer - Stop Status Flag"] +pub struct STOP_W<'a> { + w: &'a mut W, +} +impl<'a> STOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SLAVE` reader - Slave Status Flag"] +pub struct SLAVE_R(crate::FieldReader); +impl SLAVE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLAVE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SLAVE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLAVE` writer - Slave Status Flag"] +pub struct SLAVE_W<'a> { + w: &'a mut W, +} +impl<'a> SLAVE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PERBUFV` reader - Synchronization Busy Status"] +pub struct PERBUFV_R(crate::FieldReader); +impl PERBUFV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PERBUFV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERBUFV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERBUFV` writer - Synchronization Busy Status"] +pub struct PERBUFV_W<'a> { + w: &'a mut W, +} +impl<'a> PERBUFV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CCBUFV0` reader - Compare channel buffer 0 valid"] +pub struct CCBUFV0_R(crate::FieldReader); +impl CCBUFV0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBUFV0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUFV0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUFV0` writer - Compare channel buffer 0 valid"] +pub struct CCBUFV0_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUFV0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `CCBUFV1` reader - Compare channel buffer 1 valid"] +pub struct CCBUFV1_R(crate::FieldReader); +impl CCBUFV1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBUFV1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUFV1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUFV1` writer - Compare channel buffer 1 valid"] +pub struct CCBUFV1_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUFV1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Stop Status Flag"] + #[inline(always)] + pub fn stop(&self) -> STOP_R { + STOP_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Slave Status Flag"] + #[inline(always)] + pub fn slave(&self) -> SLAVE_R { + SLAVE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 3 - Synchronization Busy Status"] + #[inline(always)] + pub fn perbufv(&self) -> PERBUFV_R { + PERBUFV_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Compare channel buffer 0 valid"] + #[inline(always)] + pub fn ccbufv0(&self) -> CCBUFV0_R { + CCBUFV0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Compare channel buffer 1 valid"] + #[inline(always)] + pub fn ccbufv1(&self) -> CCBUFV1_R { + CCBUFV1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Stop Status Flag"] + #[inline(always)] + pub fn stop(&mut self) -> STOP_W { + STOP_W { w: self } + } + #[doc = "Bit 1 - Slave Status Flag"] + #[inline(always)] + pub fn slave(&mut self) -> SLAVE_W { + SLAVE_W { w: self } + } + #[doc = "Bit 3 - Synchronization Busy Status"] + #[inline(always)] + pub fn perbufv(&mut self) -> PERBUFV_W { + PERBUFV_W { w: self } + } + #[doc = "Bit 4 - Compare channel buffer 0 valid"] + #[inline(always)] + pub fn ccbufv0(&mut self) -> CCBUFV0_W { + CCBUFV0_W { w: self } + } + #[doc = "Bit 5 - Compare channel buffer 1 valid"] + #[inline(always)] + pub fn ccbufv1(&mut self) -> CCBUFV1_W { + CCBUFV1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0x01"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pac/atsamc20n/src/tc0/count16/syncbusy.rs b/pac/atsamc20n/src/tc0/count16/syncbusy.rs new file mode 100644 index 000000000000..7ad8d91a84de --- /dev/null +++ b/pac/atsamc20n/src/tc0/count16/syncbusy.rs @@ -0,0 +1,193 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - swrst"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLB` reader - CTRLB"] +pub struct CTRLB_R(crate::FieldReader); +impl CTRLB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STATUS` reader - STATUS"] +pub struct STATUS_R(crate::FieldReader); +impl STATUS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STATUS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STATUS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` reader - Counter"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` reader - Period"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC0` reader - Compare Channel 0"] +pub struct CC0_R(crate::FieldReader); +impl CC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC1` reader - Compare Channel 1"] +pub struct CC1_R(crate::FieldReader); +impl CC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - swrst"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - CTRLB"] + #[inline(always)] + pub fn ctrlb(&self) -> CTRLB_R { + CTRLB_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - STATUS"] + #[inline(always)] + pub fn status(&self) -> STATUS_R { + STATUS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Counter"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Period"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Compare Channel 0"] + #[inline(always)] + pub fn cc0(&self) -> CC0_R { + CC0_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Compare Channel 1"] + #[inline(always)] + pub fn cc1(&self) -> CC1_R { + CC1_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +#[doc = "Synchronization Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/tc0/count16/wave.rs b/pac/atsamc20n/src/tc0/count16/wave.rs new file mode 100644 index 000000000000..46061b24b75d --- /dev/null +++ b/pac/atsamc20n/src/tc0/count16/wave.rs @@ -0,0 +1,178 @@ +#[doc = "Register `WAVE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WAVE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Waveform Generation Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WAVEGEN_A { + #[doc = "0: Normal frequency"] + NFRQ = 0, + #[doc = "1: Match frequency"] + MFRQ = 1, + #[doc = "2: Normal PWM"] + NPWM = 2, + #[doc = "3: Match PWM"] + MPWM = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WAVEGEN_A) -> Self { + variant as _ + } +} +#[doc = "Field `WAVEGEN` reader - Waveform Generation Mode"] +pub struct WAVEGEN_R(crate::FieldReader); +impl WAVEGEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WAVEGEN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> WAVEGEN_A { + match self.bits { + 0 => WAVEGEN_A::NFRQ, + 1 => WAVEGEN_A::MFRQ, + 2 => WAVEGEN_A::NPWM, + 3 => WAVEGEN_A::MPWM, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NFRQ`"] + #[inline(always)] + pub fn is_nfrq(&self) -> bool { + **self == WAVEGEN_A::NFRQ + } + #[doc = "Checks if the value of the field is `MFRQ`"] + #[inline(always)] + pub fn is_mfrq(&self) -> bool { + **self == WAVEGEN_A::MFRQ + } + #[doc = "Checks if the value of the field is `NPWM`"] + #[inline(always)] + pub fn is_npwm(&self) -> bool { + **self == WAVEGEN_A::NPWM + } + #[doc = "Checks if the value of the field is `MPWM`"] + #[inline(always)] + pub fn is_mpwm(&self) -> bool { + **self == WAVEGEN_A::MPWM + } +} +impl core::ops::Deref for WAVEGEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAVEGEN` writer - Waveform Generation Mode"] +pub struct WAVEGEN_W<'a> { + w: &'a mut W, +} +impl<'a> WAVEGEN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WAVEGEN_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Normal frequency"] + #[inline(always)] + pub fn nfrq(self) -> &'a mut W { + self.variant(WAVEGEN_A::NFRQ) + } + #[doc = "Match frequency"] + #[inline(always)] + pub fn mfrq(self) -> &'a mut W { + self.variant(WAVEGEN_A::MFRQ) + } + #[doc = "Normal PWM"] + #[inline(always)] + pub fn npwm(self) -> &'a mut W { + self.variant(WAVEGEN_A::NPWM) + } + #[doc = "Match PWM"] + #[inline(always)] + pub fn mpwm(self) -> &'a mut W { + self.variant(WAVEGEN_A::MPWM) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u8 & 0x03); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Waveform Generation Mode"] + #[inline(always)] + pub fn wavegen(&self) -> WAVEGEN_R { + WAVEGEN_R::new((self.bits & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Waveform Generation Mode"] + #[inline(always)] + pub fn wavegen(&mut self) -> WAVEGEN_W { + WAVEGEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Waveform Generation Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wave](index.html) module"] +pub struct WAVE_SPEC; +impl crate::RegisterSpec for WAVE_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [wave::R](R) reader structure"] +impl crate::Readable for WAVE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wave::W](W) writer structure"] +impl crate::Writable for WAVE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WAVE to value 0"] +impl crate::Resettable for WAVE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/tc0/count32.rs b/pac/atsamc20n/src/tc0/count32.rs new file mode 100644 index 000000000000..9062acfbbd7f --- /dev/null +++ b/pac/atsamc20n/src/tc0/count32.rs @@ -0,0 +1,60 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "CTRLBCLR register accessor: an alias for `Reg`"] +pub type CTRLBCLR = crate::Reg; +#[doc = "Control B Clear"] +pub mod ctrlbclr; +#[doc = "CTRLBSET register accessor: an alias for `Reg`"] +pub type CTRLBSET = crate::Reg; +#[doc = "Control B Set"] +pub mod ctrlbset; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "WAVE register accessor: an alias for `Reg`"] +pub type WAVE = crate::Reg; +#[doc = "Waveform Generation Control"] +pub mod wave; +#[doc = "DRVCTRL register accessor: an alias for `Reg`"] +pub type DRVCTRL = crate::Reg; +#[doc = "Control C"] +pub mod drvctrl; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Status"] +pub mod syncbusy; +#[doc = "COUNT register accessor: an alias for `Reg`"] +pub type COUNT = crate::Reg; +#[doc = "COUNT32 Count"] +pub mod count; +#[doc = "CC register accessor: an alias for `Reg`"] +pub type CC = crate::Reg; +#[doc = "COUNT32 Compare and Capture"] +pub mod cc; +#[doc = "CCBUF register accessor: an alias for `Reg`"] +pub type CCBUF = crate::Reg; +#[doc = "COUNT32 Compare and Capture Buffer"] +pub mod ccbuf; diff --git a/pac/atsamc20n/src/tc0/count32/cc.rs b/pac/atsamc20n/src/tc0/count32/cc.rs new file mode 100644 index 000000000000..512a1e01ffd4 --- /dev/null +++ b/pac/atsamc20n/src/tc0/count32/cc.rs @@ -0,0 +1,104 @@ +#[doc = "Register `CC[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CC[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CC` reader - Counter/Compare Value"] +pub struct CC_R(crate::FieldReader); +impl CC_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC` writer - Counter/Compare Value"] +pub struct CC_W<'a> { + w: &'a mut W, +} +impl<'a> CC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Counter/Compare Value"] + #[inline(always)] + pub fn cc(&self) -> CC_R { + CC_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Counter/Compare Value"] + #[inline(always)] + pub fn cc(&mut self) -> CC_W { + CC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT32 Compare and Capture\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc](index.html) module"] +pub struct CC_SPEC; +impl crate::RegisterSpec for CC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cc::R](R) reader structure"] +impl crate::Readable for CC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cc::W](W) writer structure"] +impl crate::Writable for CC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CC[%s] +to value 0"] +impl crate::Resettable for CC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/tc0/count32/ccbuf.rs b/pac/atsamc20n/src/tc0/count32/ccbuf.rs new file mode 100644 index 000000000000..9fb2d9f8f66c --- /dev/null +++ b/pac/atsamc20n/src/tc0/count32/ccbuf.rs @@ -0,0 +1,104 @@ +#[doc = "Register `CCBUF[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CCBUF[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CCBUF` reader - Counter/Compare Buffer Value"] +pub struct CCBUF_R(crate::FieldReader); +impl CCBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CCBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUF` writer - Counter/Compare Buffer Value"] +pub struct CCBUF_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Counter/Compare Buffer Value"] + #[inline(always)] + pub fn ccbuf(&self) -> CCBUF_R { + CCBUF_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Counter/Compare Buffer Value"] + #[inline(always)] + pub fn ccbuf(&mut self) -> CCBUF_W { + CCBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT32 Compare and Capture Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccbuf](index.html) module"] +pub struct CCBUF_SPEC; +impl crate::RegisterSpec for CCBUF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ccbuf::R](R) reader structure"] +impl crate::Readable for CCBUF_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ccbuf::W](W) writer structure"] +impl crate::Writable for CCBUF_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CCBUF[%s] +to value 0"] +impl crate::Resettable for CCBUF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/tc0/count32/count.rs b/pac/atsamc20n/src/tc0/count32/count.rs new file mode 100644 index 000000000000..9aea527a8b3c --- /dev/null +++ b/pac/atsamc20n/src/tc0/count32/count.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT32 Count\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count](index.html) module"] +pub struct COUNT_SPEC; +impl crate::RegisterSpec for COUNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [count::R](R) reader structure"] +impl crate::Readable for COUNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count::W](W) writer structure"] +impl crate::Writable for COUNT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT to value 0"] +impl crate::Resettable for COUNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/tc0/count32/ctrla.rs b/pac/atsamc20n/src/tc0/count32/ctrla.rs new file mode 100644 index 000000000000..e1be912fdfcd --- /dev/null +++ b/pac/atsamc20n/src/tc0/count32/ctrla.rs @@ -0,0 +1,1049 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Timer Counter Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: Counter in 16-bit mode"] + COUNT16 = 0, + #[doc = "1: Counter in 8-bit mode"] + COUNT8 = 1, + #[doc = "2: Counter in 32-bit mode"] + COUNT32 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Timer Counter Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::COUNT16), + 1 => Some(MODE_A::COUNT8), + 2 => Some(MODE_A::COUNT32), + _ => None, + } + } + #[doc = "Checks if the value of the field is `COUNT16`"] + #[inline(always)] + pub fn is_count16(&self) -> bool { + **self == MODE_A::COUNT16 + } + #[doc = "Checks if the value of the field is `COUNT8`"] + #[inline(always)] + pub fn is_count8(&self) -> bool { + **self == MODE_A::COUNT8 + } + #[doc = "Checks if the value of the field is `COUNT32`"] + #[inline(always)] + pub fn is_count32(&self) -> bool { + **self == MODE_A::COUNT32 + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Timer Counter Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Counter in 16-bit mode"] + #[inline(always)] + pub fn count16(self) -> &'a mut W { + self.variant(MODE_A::COUNT16) + } + #[doc = "Counter in 8-bit mode"] + #[inline(always)] + pub fn count8(self) -> &'a mut W { + self.variant(MODE_A::COUNT8) + } + #[doc = "Counter in 32-bit mode"] + #[inline(always)] + pub fn count32(self) -> &'a mut W { + self.variant(MODE_A::COUNT32) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u32 & 0x03) << 2); + self.w + } +} +#[doc = "Prescaler and Counter Synchronization\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCSYNC_A { + #[doc = "0: Reload or reset the counter on next generic clock"] + GCLK = 0, + #[doc = "1: Reload or reset the counter on next prescaler clock"] + PRESC = 1, + #[doc = "2: Reload or reset the counter on next generic clock and reset the prescaler counter"] + RESYNC = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCSYNC_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCSYNC` reader - Prescaler and Counter Synchronization"] +pub struct PRESCSYNC_R(crate::FieldReader); +impl PRESCSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCSYNC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCSYNC_A::GCLK), + 1 => Some(PRESCSYNC_A::PRESC), + 2 => Some(PRESCSYNC_A::RESYNC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `GCLK`"] + #[inline(always)] + pub fn is_gclk(&self) -> bool { + **self == PRESCSYNC_A::GCLK + } + #[doc = "Checks if the value of the field is `PRESC`"] + #[inline(always)] + pub fn is_presc(&self) -> bool { + **self == PRESCSYNC_A::PRESC + } + #[doc = "Checks if the value of the field is `RESYNC`"] + #[inline(always)] + pub fn is_resync(&self) -> bool { + **self == PRESCSYNC_A::RESYNC + } +} +impl core::ops::Deref for PRESCSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCSYNC` writer - Prescaler and Counter Synchronization"] +pub struct PRESCSYNC_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCSYNC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCSYNC_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Reload or reset the counter on next generic clock"] + #[inline(always)] + pub fn gclk(self) -> &'a mut W { + self.variant(PRESCSYNC_A::GCLK) + } + #[doc = "Reload or reset the counter on next prescaler clock"] + #[inline(always)] + pub fn presc(self) -> &'a mut W { + self.variant(PRESCSYNC_A::PRESC) + } + #[doc = "Reload or reset the counter on next generic clock and reset the prescaler counter"] + #[inline(always)] + pub fn resync(self) -> &'a mut W { + self.variant(PRESCSYNC_A::RESYNC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u32 & 0x03) << 4); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - Clock On Demand"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - Clock On Demand"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: Prescaler: GCLK_TC"] + DIV1 = 0, + #[doc = "1: Prescaler: GCLK_TC/2"] + DIV2 = 1, + #[doc = "2: Prescaler: GCLK_TC/4"] + DIV4 = 2, + #[doc = "3: Prescaler: GCLK_TC/8"] + DIV8 = 3, + #[doc = "4: Prescaler: GCLK_TC/16"] + DIV16 = 4, + #[doc = "5: Prescaler: GCLK_TC/64"] + DIV64 = 5, + #[doc = "6: Prescaler: GCLK_TC/256"] + DIV256 = 6, + #[doc = "7: Prescaler: GCLK_TC/1024"] + DIV1024 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PRESCALER_A { + match self.bits { + 0 => PRESCALER_A::DIV1, + 1 => PRESCALER_A::DIV2, + 2 => PRESCALER_A::DIV4, + 3 => PRESCALER_A::DIV8, + 4 => PRESCALER_A::DIV16, + 5 => PRESCALER_A::DIV64, + 6 => PRESCALER_A::DIV256, + 7 => PRESCALER_A::DIV1024, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == PRESCALER_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PRESCALER_A::DIV1024 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Prescaler: GCLK_TC"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1) + } + #[doc = "Prescaler: GCLK_TC/2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "Prescaler: GCLK_TC/4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "Prescaler: GCLK_TC/8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "Prescaler: GCLK_TC/16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "Prescaler: GCLK_TC/64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "Prescaler: GCLK_TC/256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = "Prescaler: GCLK_TC/1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +#[doc = "Field `ALOCK` reader - Auto Lock"] +pub struct ALOCK_R(crate::FieldReader); +impl ALOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALOCK` writer - Auto Lock"] +pub struct ALOCK_W<'a> { + w: &'a mut W, +} +impl<'a> ALOCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `CAPTEN0` reader - Capture Channel 0 Enable"] +pub struct CAPTEN0_R(crate::FieldReader); +impl CAPTEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CAPTEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CAPTEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAPTEN0` writer - Capture Channel 0 Enable"] +pub struct CAPTEN0_W<'a> { + w: &'a mut W, +} +impl<'a> CAPTEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `CAPTEN1` reader - Capture Channel 1 Enable"] +pub struct CAPTEN1_R(crate::FieldReader); +impl CAPTEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CAPTEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CAPTEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAPTEN1` writer - Capture Channel 1 Enable"] +pub struct CAPTEN1_W<'a> { + w: &'a mut W, +} +impl<'a> CAPTEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `COPEN0` reader - Capture On Pin 0 Enable"] +pub struct COPEN0_R(crate::FieldReader); +impl COPEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COPEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COPEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COPEN0` writer - Capture On Pin 0 Enable"] +pub struct COPEN0_W<'a> { + w: &'a mut W, +} +impl<'a> COPEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `COPEN1` reader - Capture On Pin 1 Enable"] +pub struct COPEN1_R(crate::FieldReader); +impl COPEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COPEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COPEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COPEN1` writer - Capture On Pin 1 Enable"] +pub struct COPEN1_W<'a> { + w: &'a mut W, +} +impl<'a> COPEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Capture Mode Channel 0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CAPTMODE0_A { + #[doc = "0: Default capture"] + DEFAULT = 0, + #[doc = "1: Minimum capture"] + CAPTMIN = 1, + #[doc = "2: Maximum capture"] + CAPTMAX = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CAPTMODE0_A) -> Self { + variant as _ + } +} +#[doc = "Field `CAPTMODE0` reader - Capture Mode Channel 0"] +pub struct CAPTMODE0_R(crate::FieldReader); +impl CAPTMODE0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CAPTMODE0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CAPTMODE0_A::DEFAULT), + 1 => Some(CAPTMODE0_A::CAPTMIN), + 2 => Some(CAPTMODE0_A::CAPTMAX), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DEFAULT`"] + #[inline(always)] + pub fn is_default(&self) -> bool { + **self == CAPTMODE0_A::DEFAULT + } + #[doc = "Checks if the value of the field is `CAPTMIN`"] + #[inline(always)] + pub fn is_captmin(&self) -> bool { + **self == CAPTMODE0_A::CAPTMIN + } + #[doc = "Checks if the value of the field is `CAPTMAX`"] + #[inline(always)] + pub fn is_captmax(&self) -> bool { + **self == CAPTMODE0_A::CAPTMAX + } +} +impl core::ops::Deref for CAPTMODE0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAPTMODE0` writer - Capture Mode Channel 0"] +pub struct CAPTMODE0_W<'a> { + w: &'a mut W, +} +impl<'a> CAPTMODE0_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CAPTMODE0_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Default capture"] + #[inline(always)] + pub fn default(self) -> &'a mut W { + self.variant(CAPTMODE0_A::DEFAULT) + } + #[doc = "Minimum capture"] + #[inline(always)] + pub fn captmin(self) -> &'a mut W { + self.variant(CAPTMODE0_A::CAPTMIN) + } + #[doc = "Maximum capture"] + #[inline(always)] + pub fn captmax(self) -> &'a mut W { + self.variant(CAPTMODE0_A::CAPTMAX) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 24)) | ((value as u32 & 0x03) << 24); + self.w + } +} +#[doc = "Capture mode Channel 1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CAPTMODE1_A { + #[doc = "0: Default capture"] + DEFAULT = 0, + #[doc = "1: Minimum capture"] + CAPTMIN = 1, + #[doc = "2: Maximum capture"] + CAPTMAX = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CAPTMODE1_A) -> Self { + variant as _ + } +} +#[doc = "Field `CAPTMODE1` reader - Capture mode Channel 1"] +pub struct CAPTMODE1_R(crate::FieldReader); +impl CAPTMODE1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CAPTMODE1_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CAPTMODE1_A::DEFAULT), + 1 => Some(CAPTMODE1_A::CAPTMIN), + 2 => Some(CAPTMODE1_A::CAPTMAX), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DEFAULT`"] + #[inline(always)] + pub fn is_default(&self) -> bool { + **self == CAPTMODE1_A::DEFAULT + } + #[doc = "Checks if the value of the field is `CAPTMIN`"] + #[inline(always)] + pub fn is_captmin(&self) -> bool { + **self == CAPTMODE1_A::CAPTMIN + } + #[doc = "Checks if the value of the field is `CAPTMAX`"] + #[inline(always)] + pub fn is_captmax(&self) -> bool { + **self == CAPTMODE1_A::CAPTMAX + } +} +impl core::ops::Deref for CAPTMODE1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAPTMODE1` writer - Capture mode Channel 1"] +pub struct CAPTMODE1_W<'a> { + w: &'a mut W, +} +impl<'a> CAPTMODE1_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CAPTMODE1_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Default capture"] + #[inline(always)] + pub fn default(self) -> &'a mut W { + self.variant(CAPTMODE1_A::DEFAULT) + } + #[doc = "Minimum capture"] + #[inline(always)] + pub fn captmin(self) -> &'a mut W { + self.variant(CAPTMODE1_A::CAPTMIN) + } + #[doc = "Maximum capture"] + #[inline(always)] + pub fn captmax(self) -> &'a mut W { + self.variant(CAPTMODE1_A::CAPTMAX) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 27)) | ((value as u32 & 0x03) << 27); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:3 - Timer Counter Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bits 4:5 - Prescaler and Counter Synchronization"] + #[inline(always)] + pub fn prescsync(&self) -> PRESCSYNC_R { + PRESCSYNC_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Clock On Demand"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 11 - Auto Lock"] + #[inline(always)] + pub fn alock(&self) -> ALOCK_R { + ALOCK_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 16 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn capten0(&self) -> CAPTEN0_R { + CAPTEN0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn capten1(&self) -> CAPTEN1_R { + CAPTEN1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 20 - Capture On Pin 0 Enable"] + #[inline(always)] + pub fn copen0(&self) -> COPEN0_R { + COPEN0_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Capture On Pin 1 Enable"] + #[inline(always)] + pub fn copen1(&self) -> COPEN1_R { + COPEN1_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bits 24:25 - Capture Mode Channel 0"] + #[inline(always)] + pub fn captmode0(&self) -> CAPTMODE0_R { + CAPTMODE0_R::new(((self.bits >> 24) & 0x03) as u8) + } + #[doc = "Bits 27:28 - Capture mode Channel 1"] + #[inline(always)] + pub fn captmode1(&self) -> CAPTMODE1_R { + CAPTMODE1_R::new(((self.bits >> 27) & 0x03) as u8) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:3 - Timer Counter Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bits 4:5 - Prescaler and Counter Synchronization"] + #[inline(always)] + pub fn prescsync(&mut self) -> PRESCSYNC_W { + PRESCSYNC_W { w: self } + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - Clock On Demand"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Bit 11 - Auto Lock"] + #[inline(always)] + pub fn alock(&mut self) -> ALOCK_W { + ALOCK_W { w: self } + } + #[doc = "Bit 16 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn capten0(&mut self) -> CAPTEN0_W { + CAPTEN0_W { w: self } + } + #[doc = "Bit 17 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn capten1(&mut self) -> CAPTEN1_W { + CAPTEN1_W { w: self } + } + #[doc = "Bit 20 - Capture On Pin 0 Enable"] + #[inline(always)] + pub fn copen0(&mut self) -> COPEN0_W { + COPEN0_W { w: self } + } + #[doc = "Bit 21 - Capture On Pin 1 Enable"] + #[inline(always)] + pub fn copen1(&mut self) -> COPEN1_W { + COPEN1_W { w: self } + } + #[doc = "Bits 24:25 - Capture Mode Channel 0"] + #[inline(always)] + pub fn captmode0(&mut self) -> CAPTMODE0_W { + CAPTMODE0_W { w: self } + } + #[doc = "Bits 27:28 - Capture mode Channel 1"] + #[inline(always)] + pub fn captmode1(&mut self) -> CAPTMODE1_W { + CAPTMODE1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/tc0/count32/ctrlbclr.rs b/pac/atsamc20n/src/tc0/count32/ctrlbclr.rs new file mode 100644 index 000000000000..76265674036a --- /dev/null +++ b/pac/atsamc20n/src/tc0/count32/ctrlbclr.rs @@ -0,0 +1,345 @@ +#[doc = "Register `CTRLBCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Counter Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `LUPD` reader - Lock Update"] +pub struct LUPD_R(crate::FieldReader); +impl LUPD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LUPD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LUPD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LUPD` writer - Lock Update"] +pub struct LUPD_W<'a> { + w: &'a mut W, +} +impl<'a> LUPD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ONESHOT` reader - One-Shot on Counter"] +pub struct ONESHOT_R(crate::FieldReader); +impl ONESHOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONESHOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONESHOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONESHOT` writer - One-Shot on Counter"] +pub struct ONESHOT_W<'a> { + w: &'a mut W, +} +impl<'a> ONESHOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Force a start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force a stop"] + STOP = 2, + #[doc = "3: Force update of double-buffered register"] + UPDATE = 3, + #[doc = "4: Force a read synchronization of COUNT"] + READSYNC = 4, + #[doc = "5: One-shot DMA trigger"] + DMAOS = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NONE), + 1 => Some(CMD_A::RETRIGGER), + 2 => Some(CMD_A::STOP), + 3 => Some(CMD_A::UPDATE), + 4 => Some(CMD_A::READSYNC), + 5 => Some(CMD_A::DMAOS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == CMD_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == CMD_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == CMD_A::STOP + } + #[doc = "Checks if the value of the field is `UPDATE`"] + #[inline(always)] + pub fn is_update(&self) -> bool { + **self == CMD_A::UPDATE + } + #[doc = "Checks if the value of the field is `READSYNC`"] + #[inline(always)] + pub fn is_readsync(&self) -> bool { + **self == CMD_A::READSYNC + } + #[doc = "Checks if the value of the field is `DMAOS`"] + #[inline(always)] + pub fn is_dmaos(&self) -> bool { + **self == CMD_A::DMAOS + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMD_A::NONE) + } + #[doc = "Force a start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMD_A::RETRIGGER) + } + #[doc = "Force a stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMD_A::STOP) + } + #[doc = "Force update of double-buffered register"] + #[inline(always)] + pub fn update(self) -> &'a mut W { + self.variant(CMD_A::UPDATE) + } + #[doc = "Force a read synchronization of COUNT"] + #[inline(always)] + pub fn readsync(self) -> &'a mut W { + self.variant(CMD_A::READSYNC) + } + #[doc = "One-shot DMA trigger"] + #[inline(always)] + pub fn dmaos(self) -> &'a mut W { + self.variant(CMD_A::DMAOS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 5)) | ((value as u8 & 0x07) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&self) -> LUPD_R { + LUPD_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 5) & 0x07) as u8) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&mut self) -> LUPD_W { + LUPD_W { w: self } + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&mut self) -> ONESHOT_W { + ONESHOT_W { w: self } + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbclr](index.html) module"] +pub struct CTRLBCLR_SPEC; +impl crate::RegisterSpec for CTRLBCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbclr::R](R) reader structure"] +impl crate::Readable for CTRLBCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbclr::W](W) writer structure"] +impl crate::Writable for CTRLBCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLBCLR to value 0"] +impl crate::Resettable for CTRLBCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/tc0/count32/ctrlbset.rs b/pac/atsamc20n/src/tc0/count32/ctrlbset.rs new file mode 100644 index 000000000000..610914c9c7c8 --- /dev/null +++ b/pac/atsamc20n/src/tc0/count32/ctrlbset.rs @@ -0,0 +1,345 @@ +#[doc = "Register `CTRLBSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Counter Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `LUPD` reader - Lock Update"] +pub struct LUPD_R(crate::FieldReader); +impl LUPD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LUPD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LUPD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LUPD` writer - Lock Update"] +pub struct LUPD_W<'a> { + w: &'a mut W, +} +impl<'a> LUPD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ONESHOT` reader - One-Shot on Counter"] +pub struct ONESHOT_R(crate::FieldReader); +impl ONESHOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONESHOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONESHOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONESHOT` writer - One-Shot on Counter"] +pub struct ONESHOT_W<'a> { + w: &'a mut W, +} +impl<'a> ONESHOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Force a start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force a stop"] + STOP = 2, + #[doc = "3: Force update of double-buffered register"] + UPDATE = 3, + #[doc = "4: Force a read synchronization of COUNT"] + READSYNC = 4, + #[doc = "5: One-shot DMA trigger"] + DMAOS = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NONE), + 1 => Some(CMD_A::RETRIGGER), + 2 => Some(CMD_A::STOP), + 3 => Some(CMD_A::UPDATE), + 4 => Some(CMD_A::READSYNC), + 5 => Some(CMD_A::DMAOS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == CMD_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == CMD_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == CMD_A::STOP + } + #[doc = "Checks if the value of the field is `UPDATE`"] + #[inline(always)] + pub fn is_update(&self) -> bool { + **self == CMD_A::UPDATE + } + #[doc = "Checks if the value of the field is `READSYNC`"] + #[inline(always)] + pub fn is_readsync(&self) -> bool { + **self == CMD_A::READSYNC + } + #[doc = "Checks if the value of the field is `DMAOS`"] + #[inline(always)] + pub fn is_dmaos(&self) -> bool { + **self == CMD_A::DMAOS + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMD_A::NONE) + } + #[doc = "Force a start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMD_A::RETRIGGER) + } + #[doc = "Force a stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMD_A::STOP) + } + #[doc = "Force update of double-buffered register"] + #[inline(always)] + pub fn update(self) -> &'a mut W { + self.variant(CMD_A::UPDATE) + } + #[doc = "Force a read synchronization of COUNT"] + #[inline(always)] + pub fn readsync(self) -> &'a mut W { + self.variant(CMD_A::READSYNC) + } + #[doc = "One-shot DMA trigger"] + #[inline(always)] + pub fn dmaos(self) -> &'a mut W { + self.variant(CMD_A::DMAOS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 5)) | ((value as u8 & 0x07) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&self) -> LUPD_R { + LUPD_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 5) & 0x07) as u8) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&mut self) -> LUPD_W { + LUPD_W { w: self } + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&mut self) -> ONESHOT_W { + ONESHOT_W { w: self } + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbset](index.html) module"] +pub struct CTRLBSET_SPEC; +impl crate::RegisterSpec for CTRLBSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbset::R](R) reader structure"] +impl crate::Readable for CTRLBSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbset::W](W) writer structure"] +impl crate::Writable for CTRLBSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLBSET to value 0"] +impl crate::Resettable for CTRLBSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/tc0/count32/dbgctrl.rs b/pac/atsamc20n/src/tc0/count32/dbgctrl.rs new file mode 100644 index 000000000000..0383e70d0429 --- /dev/null +++ b/pac/atsamc20n/src/tc0/count32/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Run During Debug"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Run During Debug"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/tc0/count32/drvctrl.rs b/pac/atsamc20n/src/tc0/count32/drvctrl.rs new file mode 100644 index 000000000000..323926b4b22d --- /dev/null +++ b/pac/atsamc20n/src/tc0/count32/drvctrl.rs @@ -0,0 +1,160 @@ +#[doc = "Register `DRVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DRVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INVEN0` reader - Output Waveform Invert Enable 0"] +pub struct INVEN0_R(crate::FieldReader); +impl INVEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN0` writer - Output Waveform Invert Enable 0"] +pub struct INVEN0_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `INVEN1` reader - Output Waveform Invert Enable 1"] +pub struct INVEN1_R(crate::FieldReader); +impl INVEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN1` writer - Output Waveform Invert Enable 1"] +pub struct INVEN1_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - Output Waveform Invert Enable 0"] + #[inline(always)] + pub fn inven0(&self) -> INVEN0_R { + INVEN0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Output Waveform Invert Enable 1"] + #[inline(always)] + pub fn inven1(&self) -> INVEN1_R { + INVEN1_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Output Waveform Invert Enable 0"] + #[inline(always)] + pub fn inven0(&mut self) -> INVEN0_W { + INVEN0_W { w: self } + } + #[doc = "Bit 1 - Output Waveform Invert Enable 1"] + #[inline(always)] + pub fn inven1(&mut self) -> INVEN1_W { + INVEN1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control C\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [drvctrl](index.html) module"] +pub struct DRVCTRL_SPEC; +impl crate::RegisterSpec for DRVCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [drvctrl::R](R) reader structure"] +impl crate::Readable for DRVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [drvctrl::W](W) writer structure"] +impl crate::Writable for DRVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DRVCTRL to value 0"] +impl crate::Resettable for DRVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/tc0/count32/evctrl.rs b/pac/atsamc20n/src/tc0/count32/evctrl.rs new file mode 100644 index 000000000000..7d4c38d486c1 --- /dev/null +++ b/pac/atsamc20n/src/tc0/count32/evctrl.rs @@ -0,0 +1,465 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Event Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EVACT_A { + #[doc = "0: Event action disabled"] + OFF = 0, + #[doc = "1: Start, restart or retrigger TC on event"] + RETRIGGER = 1, + #[doc = "2: Count on event"] + COUNT = 2, + #[doc = "3: Start TC on event"] + START = 3, + #[doc = "4: Time stamp capture"] + STAMP = 4, + #[doc = "5: Period catured in CC0, pulse width in CC1"] + PPW = 5, + #[doc = "6: Period catured in CC1, pulse width in CC0"] + PWP = 6, + #[doc = "7: Pulse width capture"] + PW = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EVACT_A) -> Self { + variant as _ + } +} +#[doc = "Field `EVACT` reader - Event Action"] +pub struct EVACT_R(crate::FieldReader); +impl EVACT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVACT_A { + match self.bits { + 0 => EVACT_A::OFF, + 1 => EVACT_A::RETRIGGER, + 2 => EVACT_A::COUNT, + 3 => EVACT_A::START, + 4 => EVACT_A::STAMP, + 5 => EVACT_A::PPW, + 6 => EVACT_A::PWP, + 7 => EVACT_A::PW, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == EVACT_A::OFF + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == EVACT_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `COUNT`"] + #[inline(always)] + pub fn is_count(&self) -> bool { + **self == EVACT_A::COUNT + } + #[doc = "Checks if the value of the field is `START`"] + #[inline(always)] + pub fn is_start(&self) -> bool { + **self == EVACT_A::START + } + #[doc = "Checks if the value of the field is `STAMP`"] + #[inline(always)] + pub fn is_stamp(&self) -> bool { + **self == EVACT_A::STAMP + } + #[doc = "Checks if the value of the field is `PPW`"] + #[inline(always)] + pub fn is_ppw(&self) -> bool { + **self == EVACT_A::PPW + } + #[doc = "Checks if the value of the field is `PWP`"] + #[inline(always)] + pub fn is_pwp(&self) -> bool { + **self == EVACT_A::PWP + } + #[doc = "Checks if the value of the field is `PW`"] + #[inline(always)] + pub fn is_pw(&self) -> bool { + **self == EVACT_A::PW + } +} +impl core::ops::Deref for EVACT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT` writer - Event Action"] +pub struct EVACT_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EVACT_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Event action disabled"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(EVACT_A::OFF) + } + #[doc = "Start, restart or retrigger TC on event"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(EVACT_A::RETRIGGER) + } + #[doc = "Count on event"] + #[inline(always)] + pub fn count(self) -> &'a mut W { + self.variant(EVACT_A::COUNT) + } + #[doc = "Start TC on event"] + #[inline(always)] + pub fn start(self) -> &'a mut W { + self.variant(EVACT_A::START) + } + #[doc = "Time stamp capture"] + #[inline(always)] + pub fn stamp(self) -> &'a mut W { + self.variant(EVACT_A::STAMP) + } + #[doc = "Period catured in CC0, pulse width in CC1"] + #[inline(always)] + pub fn ppw(self) -> &'a mut W { + self.variant(EVACT_A::PPW) + } + #[doc = "Period catured in CC1, pulse width in CC0"] + #[inline(always)] + pub fn pwp(self) -> &'a mut W { + self.variant(EVACT_A::PWP) + } + #[doc = "Pulse width capture"] + #[inline(always)] + pub fn pw(self) -> &'a mut W { + self.variant(EVACT_A::PW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u16 & 0x07); + self.w + } +} +#[doc = "Field `TCINV` reader - TC Event Input Polarity"] +pub struct TCINV_R(crate::FieldReader); +impl TCINV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCINV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCINV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCINV` writer - TC Event Input Polarity"] +pub struct TCINV_W<'a> { + w: &'a mut W, +} +impl<'a> TCINV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `TCEI` reader - TC Event Enable"] +pub struct TCEI_R(crate::FieldReader); +impl TCEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCEI` writer - TC Event Enable"] +pub struct TCEI_W<'a> { + w: &'a mut W, +} +impl<'a> TCEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `OVFEO` reader - Event Output Enable"] +pub struct OVFEO_R(crate::FieldReader); +impl OVFEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVFEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVFEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVFEO` writer - Event Output Enable"] +pub struct OVFEO_W<'a> { + w: &'a mut W, +} +impl<'a> OVFEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `MCEO0` reader - MC Event Output Enable 0"] +pub struct MCEO0_R(crate::FieldReader); +impl MCEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO0` writer - MC Event Output Enable 0"] +pub struct MCEO0_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u16 & 0x01) << 12); + self.w + } +} +#[doc = "Field `MCEO1` reader - MC Event Output Enable 1"] +pub struct MCEO1_R(crate::FieldReader); +impl MCEO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO1` writer - MC Event Output Enable 1"] +pub struct MCEO1_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u16 & 0x01) << 13); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Event Action"] + #[inline(always)] + pub fn evact(&self) -> EVACT_R { + EVACT_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 4 - TC Event Input Polarity"] + #[inline(always)] + pub fn tcinv(&self) -> TCINV_R { + TCINV_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - TC Event Enable"] + #[inline(always)] + pub fn tcei(&self) -> TCEI_R { + TCEI_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 8 - Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&self) -> OVFEO_R { + OVFEO_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 12 - MC Event Output Enable 0"] + #[inline(always)] + pub fn mceo0(&self) -> MCEO0_R { + MCEO0_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - MC Event Output Enable 1"] + #[inline(always)] + pub fn mceo1(&self) -> MCEO1_R { + MCEO1_R::new(((self.bits >> 13) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Event Action"] + #[inline(always)] + pub fn evact(&mut self) -> EVACT_W { + EVACT_W { w: self } + } + #[doc = "Bit 4 - TC Event Input Polarity"] + #[inline(always)] + pub fn tcinv(&mut self) -> TCINV_W { + TCINV_W { w: self } + } + #[doc = "Bit 5 - TC Event Enable"] + #[inline(always)] + pub fn tcei(&mut self) -> TCEI_W { + TCEI_W { w: self } + } + #[doc = "Bit 8 - Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&mut self) -> OVFEO_W { + OVFEO_W { w: self } + } + #[doc = "Bit 12 - MC Event Output Enable 0"] + #[inline(always)] + pub fn mceo0(&mut self) -> MCEO0_W { + MCEO0_W { w: self } + } + #[doc = "Bit 13 - MC Event Output Enable 1"] + #[inline(always)] + pub fn mceo1(&mut self) -> MCEO1_W { + MCEO1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/tc0/count32/intenclr.rs b/pac/atsamc20n/src/tc0/count32/intenclr.rs new file mode 100644 index 000000000000..af01ef5b7dca --- /dev/null +++ b/pac/atsamc20n/src/tc0/count32/intenclr.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - OVF Interrupt Disable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - OVF Interrupt Disable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - ERR Interrupt Disable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - ERR Interrupt Disable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MC0` reader - MC Interrupt Disable 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - MC Interrupt Disable 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - MC Interrupt Disable 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - MC Interrupt Disable 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - OVF Interrupt Disable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ERR Interrupt Disable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - MC Interrupt Disable 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - MC Interrupt Disable 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - OVF Interrupt Disable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - ERR Interrupt Disable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 4 - MC Interrupt Disable 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - MC Interrupt Disable 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/tc0/count32/intenset.rs b/pac/atsamc20n/src/tc0/count32/intenset.rs new file mode 100644 index 000000000000..0e1883a2f20a --- /dev/null +++ b/pac/atsamc20n/src/tc0/count32/intenset.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - OVF Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - OVF Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - ERR Interrupt Enable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - ERR Interrupt Enable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MC0` reader - MC Interrupt Enable 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - MC Interrupt Enable 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - MC Interrupt Enable 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - MC Interrupt Enable 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - OVF Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ERR Interrupt Enable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - MC Interrupt Enable 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - MC Interrupt Enable 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - OVF Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - ERR Interrupt Enable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 4 - MC Interrupt Enable 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - MC Interrupt Enable 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/tc0/count32/intflag.rs b/pac/atsamc20n/src/tc0/count32/intflag.rs new file mode 100644 index 000000000000..1dddffaf8e7f --- /dev/null +++ b/pac/atsamc20n/src/tc0/count32/intflag.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - OVF Interrupt Flag"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - OVF Interrupt Flag"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - ERR Interrupt Flag"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - ERR Interrupt Flag"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MC0` reader - MC Interrupt Flag 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - MC Interrupt Flag 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - MC Interrupt Flag 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - MC Interrupt Flag 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - OVF Interrupt Flag"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ERR Interrupt Flag"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - MC Interrupt Flag 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - MC Interrupt Flag 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - OVF Interrupt Flag"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - ERR Interrupt Flag"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 4 - MC Interrupt Flag 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - MC Interrupt Flag 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/tc0/count32/status.rs b/pac/atsamc20n/src/tc0/count32/status.rs new file mode 100644 index 000000000000..5088af446830 --- /dev/null +++ b/pac/atsamc20n/src/tc0/count32/status.rs @@ -0,0 +1,301 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `STOP` reader - Stop Status Flag"] +pub struct STOP_R(crate::FieldReader); +impl STOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STOP` writer - Stop Status Flag"] +pub struct STOP_W<'a> { + w: &'a mut W, +} +impl<'a> STOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SLAVE` reader - Slave Status Flag"] +pub struct SLAVE_R(crate::FieldReader); +impl SLAVE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLAVE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SLAVE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLAVE` writer - Slave Status Flag"] +pub struct SLAVE_W<'a> { + w: &'a mut W, +} +impl<'a> SLAVE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PERBUFV` reader - Synchronization Busy Status"] +pub struct PERBUFV_R(crate::FieldReader); +impl PERBUFV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PERBUFV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERBUFV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERBUFV` writer - Synchronization Busy Status"] +pub struct PERBUFV_W<'a> { + w: &'a mut W, +} +impl<'a> PERBUFV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CCBUFV0` reader - Compare channel buffer 0 valid"] +pub struct CCBUFV0_R(crate::FieldReader); +impl CCBUFV0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBUFV0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUFV0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUFV0` writer - Compare channel buffer 0 valid"] +pub struct CCBUFV0_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUFV0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `CCBUFV1` reader - Compare channel buffer 1 valid"] +pub struct CCBUFV1_R(crate::FieldReader); +impl CCBUFV1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBUFV1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUFV1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUFV1` writer - Compare channel buffer 1 valid"] +pub struct CCBUFV1_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUFV1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Stop Status Flag"] + #[inline(always)] + pub fn stop(&self) -> STOP_R { + STOP_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Slave Status Flag"] + #[inline(always)] + pub fn slave(&self) -> SLAVE_R { + SLAVE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 3 - Synchronization Busy Status"] + #[inline(always)] + pub fn perbufv(&self) -> PERBUFV_R { + PERBUFV_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Compare channel buffer 0 valid"] + #[inline(always)] + pub fn ccbufv0(&self) -> CCBUFV0_R { + CCBUFV0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Compare channel buffer 1 valid"] + #[inline(always)] + pub fn ccbufv1(&self) -> CCBUFV1_R { + CCBUFV1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Stop Status Flag"] + #[inline(always)] + pub fn stop(&mut self) -> STOP_W { + STOP_W { w: self } + } + #[doc = "Bit 1 - Slave Status Flag"] + #[inline(always)] + pub fn slave(&mut self) -> SLAVE_W { + SLAVE_W { w: self } + } + #[doc = "Bit 3 - Synchronization Busy Status"] + #[inline(always)] + pub fn perbufv(&mut self) -> PERBUFV_W { + PERBUFV_W { w: self } + } + #[doc = "Bit 4 - Compare channel buffer 0 valid"] + #[inline(always)] + pub fn ccbufv0(&mut self) -> CCBUFV0_W { + CCBUFV0_W { w: self } + } + #[doc = "Bit 5 - Compare channel buffer 1 valid"] + #[inline(always)] + pub fn ccbufv1(&mut self) -> CCBUFV1_W { + CCBUFV1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0x01"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pac/atsamc20n/src/tc0/count32/syncbusy.rs b/pac/atsamc20n/src/tc0/count32/syncbusy.rs new file mode 100644 index 000000000000..7ad8d91a84de --- /dev/null +++ b/pac/atsamc20n/src/tc0/count32/syncbusy.rs @@ -0,0 +1,193 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - swrst"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLB` reader - CTRLB"] +pub struct CTRLB_R(crate::FieldReader); +impl CTRLB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STATUS` reader - STATUS"] +pub struct STATUS_R(crate::FieldReader); +impl STATUS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STATUS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STATUS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` reader - Counter"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` reader - Period"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC0` reader - Compare Channel 0"] +pub struct CC0_R(crate::FieldReader); +impl CC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC1` reader - Compare Channel 1"] +pub struct CC1_R(crate::FieldReader); +impl CC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - swrst"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - CTRLB"] + #[inline(always)] + pub fn ctrlb(&self) -> CTRLB_R { + CTRLB_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - STATUS"] + #[inline(always)] + pub fn status(&self) -> STATUS_R { + STATUS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Counter"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Period"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Compare Channel 0"] + #[inline(always)] + pub fn cc0(&self) -> CC0_R { + CC0_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Compare Channel 1"] + #[inline(always)] + pub fn cc1(&self) -> CC1_R { + CC1_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +#[doc = "Synchronization Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/tc0/count32/wave.rs b/pac/atsamc20n/src/tc0/count32/wave.rs new file mode 100644 index 000000000000..46061b24b75d --- /dev/null +++ b/pac/atsamc20n/src/tc0/count32/wave.rs @@ -0,0 +1,178 @@ +#[doc = "Register `WAVE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WAVE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Waveform Generation Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WAVEGEN_A { + #[doc = "0: Normal frequency"] + NFRQ = 0, + #[doc = "1: Match frequency"] + MFRQ = 1, + #[doc = "2: Normal PWM"] + NPWM = 2, + #[doc = "3: Match PWM"] + MPWM = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WAVEGEN_A) -> Self { + variant as _ + } +} +#[doc = "Field `WAVEGEN` reader - Waveform Generation Mode"] +pub struct WAVEGEN_R(crate::FieldReader); +impl WAVEGEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WAVEGEN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> WAVEGEN_A { + match self.bits { + 0 => WAVEGEN_A::NFRQ, + 1 => WAVEGEN_A::MFRQ, + 2 => WAVEGEN_A::NPWM, + 3 => WAVEGEN_A::MPWM, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NFRQ`"] + #[inline(always)] + pub fn is_nfrq(&self) -> bool { + **self == WAVEGEN_A::NFRQ + } + #[doc = "Checks if the value of the field is `MFRQ`"] + #[inline(always)] + pub fn is_mfrq(&self) -> bool { + **self == WAVEGEN_A::MFRQ + } + #[doc = "Checks if the value of the field is `NPWM`"] + #[inline(always)] + pub fn is_npwm(&self) -> bool { + **self == WAVEGEN_A::NPWM + } + #[doc = "Checks if the value of the field is `MPWM`"] + #[inline(always)] + pub fn is_mpwm(&self) -> bool { + **self == WAVEGEN_A::MPWM + } +} +impl core::ops::Deref for WAVEGEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAVEGEN` writer - Waveform Generation Mode"] +pub struct WAVEGEN_W<'a> { + w: &'a mut W, +} +impl<'a> WAVEGEN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WAVEGEN_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Normal frequency"] + #[inline(always)] + pub fn nfrq(self) -> &'a mut W { + self.variant(WAVEGEN_A::NFRQ) + } + #[doc = "Match frequency"] + #[inline(always)] + pub fn mfrq(self) -> &'a mut W { + self.variant(WAVEGEN_A::MFRQ) + } + #[doc = "Normal PWM"] + #[inline(always)] + pub fn npwm(self) -> &'a mut W { + self.variant(WAVEGEN_A::NPWM) + } + #[doc = "Match PWM"] + #[inline(always)] + pub fn mpwm(self) -> &'a mut W { + self.variant(WAVEGEN_A::MPWM) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u8 & 0x03); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Waveform Generation Mode"] + #[inline(always)] + pub fn wavegen(&self) -> WAVEGEN_R { + WAVEGEN_R::new((self.bits & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Waveform Generation Mode"] + #[inline(always)] + pub fn wavegen(&mut self) -> WAVEGEN_W { + WAVEGEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Waveform Generation Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wave](index.html) module"] +pub struct WAVE_SPEC; +impl crate::RegisterSpec for WAVE_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [wave::R](R) reader structure"] +impl crate::Readable for WAVE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wave::W](W) writer structure"] +impl crate::Writable for WAVE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WAVE to value 0"] +impl crate::Resettable for WAVE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/tc0/count8.rs b/pac/atsamc20n/src/tc0/count8.rs new file mode 100644 index 000000000000..777da5744358 --- /dev/null +++ b/pac/atsamc20n/src/tc0/count8.rs @@ -0,0 +1,68 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "CTRLBCLR register accessor: an alias for `Reg`"] +pub type CTRLBCLR = crate::Reg; +#[doc = "Control B Clear"] +pub mod ctrlbclr; +#[doc = "CTRLBSET register accessor: an alias for `Reg`"] +pub type CTRLBSET = crate::Reg; +#[doc = "Control B Set"] +pub mod ctrlbset; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "WAVE register accessor: an alias for `Reg`"] +pub type WAVE = crate::Reg; +#[doc = "Waveform Generation Control"] +pub mod wave; +#[doc = "DRVCTRL register accessor: an alias for `Reg`"] +pub type DRVCTRL = crate::Reg; +#[doc = "Control C"] +pub mod drvctrl; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Status"] +pub mod syncbusy; +#[doc = "COUNT register accessor: an alias for `Reg`"] +pub type COUNT = crate::Reg; +#[doc = "COUNT8 Count"] +pub mod count; +#[doc = "PER register accessor: an alias for `Reg`"] +pub type PER = crate::Reg; +#[doc = "COUNT8 Period"] +pub mod per; +#[doc = "CC register accessor: an alias for `Reg`"] +pub type CC = crate::Reg; +#[doc = "COUNT8 Compare and Capture"] +pub mod cc; +#[doc = "PERBUF register accessor: an alias for `Reg`"] +pub type PERBUF = crate::Reg; +#[doc = "COUNT8 Period Buffer"] +pub mod perbuf; +#[doc = "CCBUF register accessor: an alias for `Reg`"] +pub type CCBUF = crate::Reg; +#[doc = "COUNT8 Compare and Capture Buffer"] +pub mod ccbuf; diff --git a/pac/atsamc20n/src/tc0/count8/cc.rs b/pac/atsamc20n/src/tc0/count8/cc.rs new file mode 100644 index 000000000000..45f5c29c89af --- /dev/null +++ b/pac/atsamc20n/src/tc0/count8/cc.rs @@ -0,0 +1,104 @@ +#[doc = "Register `CC[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CC[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CC` reader - Counter/Compare Value"] +pub struct CC_R(crate::FieldReader); +impl CC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC` writer - Counter/Compare Value"] +pub struct CC_W<'a> { + w: &'a mut W, +} +impl<'a> CC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Counter/Compare Value"] + #[inline(always)] + pub fn cc(&self) -> CC_R { + CC_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Counter/Compare Value"] + #[inline(always)] + pub fn cc(&mut self) -> CC_W { + CC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT8 Compare and Capture\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc](index.html) module"] +pub struct CC_SPEC; +impl crate::RegisterSpec for CC_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [cc::R](R) reader structure"] +impl crate::Readable for CC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cc::W](W) writer structure"] +impl crate::Writable for CC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CC[%s] +to value 0"] +impl crate::Resettable for CC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/tc0/count8/ccbuf.rs b/pac/atsamc20n/src/tc0/count8/ccbuf.rs new file mode 100644 index 000000000000..cd81b1219860 --- /dev/null +++ b/pac/atsamc20n/src/tc0/count8/ccbuf.rs @@ -0,0 +1,104 @@ +#[doc = "Register `CCBUF[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CCBUF[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CCBUF` reader - Counter/Compare Buffer Value"] +pub struct CCBUF_R(crate::FieldReader); +impl CCBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CCBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUF` writer - Counter/Compare Buffer Value"] +pub struct CCBUF_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Counter/Compare Buffer Value"] + #[inline(always)] + pub fn ccbuf(&self) -> CCBUF_R { + CCBUF_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Counter/Compare Buffer Value"] + #[inline(always)] + pub fn ccbuf(&mut self) -> CCBUF_W { + CCBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT8 Compare and Capture Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccbuf](index.html) module"] +pub struct CCBUF_SPEC; +impl crate::RegisterSpec for CCBUF_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ccbuf::R](R) reader structure"] +impl crate::Readable for CCBUF_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ccbuf::W](W) writer structure"] +impl crate::Writable for CCBUF_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CCBUF[%s] +to value 0"] +impl crate::Resettable for CCBUF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/tc0/count8/count.rs b/pac/atsamc20n/src/tc0/count8/count.rs new file mode 100644 index 000000000000..0edbb0f17bb7 --- /dev/null +++ b/pac/atsamc20n/src/tc0/count8/count.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT8 Count\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count](index.html) module"] +pub struct COUNT_SPEC; +impl crate::RegisterSpec for COUNT_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [count::R](R) reader structure"] +impl crate::Readable for COUNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count::W](W) writer structure"] +impl crate::Writable for COUNT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT to value 0"] +impl crate::Resettable for COUNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/tc0/count8/ctrla.rs b/pac/atsamc20n/src/tc0/count8/ctrla.rs new file mode 100644 index 000000000000..e1be912fdfcd --- /dev/null +++ b/pac/atsamc20n/src/tc0/count8/ctrla.rs @@ -0,0 +1,1049 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Timer Counter Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: Counter in 16-bit mode"] + COUNT16 = 0, + #[doc = "1: Counter in 8-bit mode"] + COUNT8 = 1, + #[doc = "2: Counter in 32-bit mode"] + COUNT32 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Timer Counter Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::COUNT16), + 1 => Some(MODE_A::COUNT8), + 2 => Some(MODE_A::COUNT32), + _ => None, + } + } + #[doc = "Checks if the value of the field is `COUNT16`"] + #[inline(always)] + pub fn is_count16(&self) -> bool { + **self == MODE_A::COUNT16 + } + #[doc = "Checks if the value of the field is `COUNT8`"] + #[inline(always)] + pub fn is_count8(&self) -> bool { + **self == MODE_A::COUNT8 + } + #[doc = "Checks if the value of the field is `COUNT32`"] + #[inline(always)] + pub fn is_count32(&self) -> bool { + **self == MODE_A::COUNT32 + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Timer Counter Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Counter in 16-bit mode"] + #[inline(always)] + pub fn count16(self) -> &'a mut W { + self.variant(MODE_A::COUNT16) + } + #[doc = "Counter in 8-bit mode"] + #[inline(always)] + pub fn count8(self) -> &'a mut W { + self.variant(MODE_A::COUNT8) + } + #[doc = "Counter in 32-bit mode"] + #[inline(always)] + pub fn count32(self) -> &'a mut W { + self.variant(MODE_A::COUNT32) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u32 & 0x03) << 2); + self.w + } +} +#[doc = "Prescaler and Counter Synchronization\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCSYNC_A { + #[doc = "0: Reload or reset the counter on next generic clock"] + GCLK = 0, + #[doc = "1: Reload or reset the counter on next prescaler clock"] + PRESC = 1, + #[doc = "2: Reload or reset the counter on next generic clock and reset the prescaler counter"] + RESYNC = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCSYNC_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCSYNC` reader - Prescaler and Counter Synchronization"] +pub struct PRESCSYNC_R(crate::FieldReader); +impl PRESCSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCSYNC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCSYNC_A::GCLK), + 1 => Some(PRESCSYNC_A::PRESC), + 2 => Some(PRESCSYNC_A::RESYNC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `GCLK`"] + #[inline(always)] + pub fn is_gclk(&self) -> bool { + **self == PRESCSYNC_A::GCLK + } + #[doc = "Checks if the value of the field is `PRESC`"] + #[inline(always)] + pub fn is_presc(&self) -> bool { + **self == PRESCSYNC_A::PRESC + } + #[doc = "Checks if the value of the field is `RESYNC`"] + #[inline(always)] + pub fn is_resync(&self) -> bool { + **self == PRESCSYNC_A::RESYNC + } +} +impl core::ops::Deref for PRESCSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCSYNC` writer - Prescaler and Counter Synchronization"] +pub struct PRESCSYNC_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCSYNC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCSYNC_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Reload or reset the counter on next generic clock"] + #[inline(always)] + pub fn gclk(self) -> &'a mut W { + self.variant(PRESCSYNC_A::GCLK) + } + #[doc = "Reload or reset the counter on next prescaler clock"] + #[inline(always)] + pub fn presc(self) -> &'a mut W { + self.variant(PRESCSYNC_A::PRESC) + } + #[doc = "Reload or reset the counter on next generic clock and reset the prescaler counter"] + #[inline(always)] + pub fn resync(self) -> &'a mut W { + self.variant(PRESCSYNC_A::RESYNC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u32 & 0x03) << 4); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - Clock On Demand"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - Clock On Demand"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: Prescaler: GCLK_TC"] + DIV1 = 0, + #[doc = "1: Prescaler: GCLK_TC/2"] + DIV2 = 1, + #[doc = "2: Prescaler: GCLK_TC/4"] + DIV4 = 2, + #[doc = "3: Prescaler: GCLK_TC/8"] + DIV8 = 3, + #[doc = "4: Prescaler: GCLK_TC/16"] + DIV16 = 4, + #[doc = "5: Prescaler: GCLK_TC/64"] + DIV64 = 5, + #[doc = "6: Prescaler: GCLK_TC/256"] + DIV256 = 6, + #[doc = "7: Prescaler: GCLK_TC/1024"] + DIV1024 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PRESCALER_A { + match self.bits { + 0 => PRESCALER_A::DIV1, + 1 => PRESCALER_A::DIV2, + 2 => PRESCALER_A::DIV4, + 3 => PRESCALER_A::DIV8, + 4 => PRESCALER_A::DIV16, + 5 => PRESCALER_A::DIV64, + 6 => PRESCALER_A::DIV256, + 7 => PRESCALER_A::DIV1024, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == PRESCALER_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PRESCALER_A::DIV1024 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Prescaler: GCLK_TC"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1) + } + #[doc = "Prescaler: GCLK_TC/2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "Prescaler: GCLK_TC/4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "Prescaler: GCLK_TC/8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "Prescaler: GCLK_TC/16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "Prescaler: GCLK_TC/64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "Prescaler: GCLK_TC/256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = "Prescaler: GCLK_TC/1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +#[doc = "Field `ALOCK` reader - Auto Lock"] +pub struct ALOCK_R(crate::FieldReader); +impl ALOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALOCK` writer - Auto Lock"] +pub struct ALOCK_W<'a> { + w: &'a mut W, +} +impl<'a> ALOCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `CAPTEN0` reader - Capture Channel 0 Enable"] +pub struct CAPTEN0_R(crate::FieldReader); +impl CAPTEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CAPTEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CAPTEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAPTEN0` writer - Capture Channel 0 Enable"] +pub struct CAPTEN0_W<'a> { + w: &'a mut W, +} +impl<'a> CAPTEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `CAPTEN1` reader - Capture Channel 1 Enable"] +pub struct CAPTEN1_R(crate::FieldReader); +impl CAPTEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CAPTEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CAPTEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAPTEN1` writer - Capture Channel 1 Enable"] +pub struct CAPTEN1_W<'a> { + w: &'a mut W, +} +impl<'a> CAPTEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `COPEN0` reader - Capture On Pin 0 Enable"] +pub struct COPEN0_R(crate::FieldReader); +impl COPEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COPEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COPEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COPEN0` writer - Capture On Pin 0 Enable"] +pub struct COPEN0_W<'a> { + w: &'a mut W, +} +impl<'a> COPEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `COPEN1` reader - Capture On Pin 1 Enable"] +pub struct COPEN1_R(crate::FieldReader); +impl COPEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COPEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COPEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COPEN1` writer - Capture On Pin 1 Enable"] +pub struct COPEN1_W<'a> { + w: &'a mut W, +} +impl<'a> COPEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Capture Mode Channel 0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CAPTMODE0_A { + #[doc = "0: Default capture"] + DEFAULT = 0, + #[doc = "1: Minimum capture"] + CAPTMIN = 1, + #[doc = "2: Maximum capture"] + CAPTMAX = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CAPTMODE0_A) -> Self { + variant as _ + } +} +#[doc = "Field `CAPTMODE0` reader - Capture Mode Channel 0"] +pub struct CAPTMODE0_R(crate::FieldReader); +impl CAPTMODE0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CAPTMODE0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CAPTMODE0_A::DEFAULT), + 1 => Some(CAPTMODE0_A::CAPTMIN), + 2 => Some(CAPTMODE0_A::CAPTMAX), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DEFAULT`"] + #[inline(always)] + pub fn is_default(&self) -> bool { + **self == CAPTMODE0_A::DEFAULT + } + #[doc = "Checks if the value of the field is `CAPTMIN`"] + #[inline(always)] + pub fn is_captmin(&self) -> bool { + **self == CAPTMODE0_A::CAPTMIN + } + #[doc = "Checks if the value of the field is `CAPTMAX`"] + #[inline(always)] + pub fn is_captmax(&self) -> bool { + **self == CAPTMODE0_A::CAPTMAX + } +} +impl core::ops::Deref for CAPTMODE0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAPTMODE0` writer - Capture Mode Channel 0"] +pub struct CAPTMODE0_W<'a> { + w: &'a mut W, +} +impl<'a> CAPTMODE0_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CAPTMODE0_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Default capture"] + #[inline(always)] + pub fn default(self) -> &'a mut W { + self.variant(CAPTMODE0_A::DEFAULT) + } + #[doc = "Minimum capture"] + #[inline(always)] + pub fn captmin(self) -> &'a mut W { + self.variant(CAPTMODE0_A::CAPTMIN) + } + #[doc = "Maximum capture"] + #[inline(always)] + pub fn captmax(self) -> &'a mut W { + self.variant(CAPTMODE0_A::CAPTMAX) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 24)) | ((value as u32 & 0x03) << 24); + self.w + } +} +#[doc = "Capture mode Channel 1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CAPTMODE1_A { + #[doc = "0: Default capture"] + DEFAULT = 0, + #[doc = "1: Minimum capture"] + CAPTMIN = 1, + #[doc = "2: Maximum capture"] + CAPTMAX = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CAPTMODE1_A) -> Self { + variant as _ + } +} +#[doc = "Field `CAPTMODE1` reader - Capture mode Channel 1"] +pub struct CAPTMODE1_R(crate::FieldReader); +impl CAPTMODE1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CAPTMODE1_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CAPTMODE1_A::DEFAULT), + 1 => Some(CAPTMODE1_A::CAPTMIN), + 2 => Some(CAPTMODE1_A::CAPTMAX), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DEFAULT`"] + #[inline(always)] + pub fn is_default(&self) -> bool { + **self == CAPTMODE1_A::DEFAULT + } + #[doc = "Checks if the value of the field is `CAPTMIN`"] + #[inline(always)] + pub fn is_captmin(&self) -> bool { + **self == CAPTMODE1_A::CAPTMIN + } + #[doc = "Checks if the value of the field is `CAPTMAX`"] + #[inline(always)] + pub fn is_captmax(&self) -> bool { + **self == CAPTMODE1_A::CAPTMAX + } +} +impl core::ops::Deref for CAPTMODE1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAPTMODE1` writer - Capture mode Channel 1"] +pub struct CAPTMODE1_W<'a> { + w: &'a mut W, +} +impl<'a> CAPTMODE1_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CAPTMODE1_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Default capture"] + #[inline(always)] + pub fn default(self) -> &'a mut W { + self.variant(CAPTMODE1_A::DEFAULT) + } + #[doc = "Minimum capture"] + #[inline(always)] + pub fn captmin(self) -> &'a mut W { + self.variant(CAPTMODE1_A::CAPTMIN) + } + #[doc = "Maximum capture"] + #[inline(always)] + pub fn captmax(self) -> &'a mut W { + self.variant(CAPTMODE1_A::CAPTMAX) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 27)) | ((value as u32 & 0x03) << 27); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:3 - Timer Counter Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bits 4:5 - Prescaler and Counter Synchronization"] + #[inline(always)] + pub fn prescsync(&self) -> PRESCSYNC_R { + PRESCSYNC_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Clock On Demand"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 11 - Auto Lock"] + #[inline(always)] + pub fn alock(&self) -> ALOCK_R { + ALOCK_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 16 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn capten0(&self) -> CAPTEN0_R { + CAPTEN0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn capten1(&self) -> CAPTEN1_R { + CAPTEN1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 20 - Capture On Pin 0 Enable"] + #[inline(always)] + pub fn copen0(&self) -> COPEN0_R { + COPEN0_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Capture On Pin 1 Enable"] + #[inline(always)] + pub fn copen1(&self) -> COPEN1_R { + COPEN1_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bits 24:25 - Capture Mode Channel 0"] + #[inline(always)] + pub fn captmode0(&self) -> CAPTMODE0_R { + CAPTMODE0_R::new(((self.bits >> 24) & 0x03) as u8) + } + #[doc = "Bits 27:28 - Capture mode Channel 1"] + #[inline(always)] + pub fn captmode1(&self) -> CAPTMODE1_R { + CAPTMODE1_R::new(((self.bits >> 27) & 0x03) as u8) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:3 - Timer Counter Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bits 4:5 - Prescaler and Counter Synchronization"] + #[inline(always)] + pub fn prescsync(&mut self) -> PRESCSYNC_W { + PRESCSYNC_W { w: self } + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - Clock On Demand"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Bit 11 - Auto Lock"] + #[inline(always)] + pub fn alock(&mut self) -> ALOCK_W { + ALOCK_W { w: self } + } + #[doc = "Bit 16 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn capten0(&mut self) -> CAPTEN0_W { + CAPTEN0_W { w: self } + } + #[doc = "Bit 17 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn capten1(&mut self) -> CAPTEN1_W { + CAPTEN1_W { w: self } + } + #[doc = "Bit 20 - Capture On Pin 0 Enable"] + #[inline(always)] + pub fn copen0(&mut self) -> COPEN0_W { + COPEN0_W { w: self } + } + #[doc = "Bit 21 - Capture On Pin 1 Enable"] + #[inline(always)] + pub fn copen1(&mut self) -> COPEN1_W { + COPEN1_W { w: self } + } + #[doc = "Bits 24:25 - Capture Mode Channel 0"] + #[inline(always)] + pub fn captmode0(&mut self) -> CAPTMODE0_W { + CAPTMODE0_W { w: self } + } + #[doc = "Bits 27:28 - Capture mode Channel 1"] + #[inline(always)] + pub fn captmode1(&mut self) -> CAPTMODE1_W { + CAPTMODE1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/tc0/count8/ctrlbclr.rs b/pac/atsamc20n/src/tc0/count8/ctrlbclr.rs new file mode 100644 index 000000000000..76265674036a --- /dev/null +++ b/pac/atsamc20n/src/tc0/count8/ctrlbclr.rs @@ -0,0 +1,345 @@ +#[doc = "Register `CTRLBCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Counter Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `LUPD` reader - Lock Update"] +pub struct LUPD_R(crate::FieldReader); +impl LUPD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LUPD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LUPD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LUPD` writer - Lock Update"] +pub struct LUPD_W<'a> { + w: &'a mut W, +} +impl<'a> LUPD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ONESHOT` reader - One-Shot on Counter"] +pub struct ONESHOT_R(crate::FieldReader); +impl ONESHOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONESHOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONESHOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONESHOT` writer - One-Shot on Counter"] +pub struct ONESHOT_W<'a> { + w: &'a mut W, +} +impl<'a> ONESHOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Force a start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force a stop"] + STOP = 2, + #[doc = "3: Force update of double-buffered register"] + UPDATE = 3, + #[doc = "4: Force a read synchronization of COUNT"] + READSYNC = 4, + #[doc = "5: One-shot DMA trigger"] + DMAOS = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NONE), + 1 => Some(CMD_A::RETRIGGER), + 2 => Some(CMD_A::STOP), + 3 => Some(CMD_A::UPDATE), + 4 => Some(CMD_A::READSYNC), + 5 => Some(CMD_A::DMAOS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == CMD_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == CMD_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == CMD_A::STOP + } + #[doc = "Checks if the value of the field is `UPDATE`"] + #[inline(always)] + pub fn is_update(&self) -> bool { + **self == CMD_A::UPDATE + } + #[doc = "Checks if the value of the field is `READSYNC`"] + #[inline(always)] + pub fn is_readsync(&self) -> bool { + **self == CMD_A::READSYNC + } + #[doc = "Checks if the value of the field is `DMAOS`"] + #[inline(always)] + pub fn is_dmaos(&self) -> bool { + **self == CMD_A::DMAOS + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMD_A::NONE) + } + #[doc = "Force a start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMD_A::RETRIGGER) + } + #[doc = "Force a stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMD_A::STOP) + } + #[doc = "Force update of double-buffered register"] + #[inline(always)] + pub fn update(self) -> &'a mut W { + self.variant(CMD_A::UPDATE) + } + #[doc = "Force a read synchronization of COUNT"] + #[inline(always)] + pub fn readsync(self) -> &'a mut W { + self.variant(CMD_A::READSYNC) + } + #[doc = "One-shot DMA trigger"] + #[inline(always)] + pub fn dmaos(self) -> &'a mut W { + self.variant(CMD_A::DMAOS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 5)) | ((value as u8 & 0x07) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&self) -> LUPD_R { + LUPD_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 5) & 0x07) as u8) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&mut self) -> LUPD_W { + LUPD_W { w: self } + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&mut self) -> ONESHOT_W { + ONESHOT_W { w: self } + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbclr](index.html) module"] +pub struct CTRLBCLR_SPEC; +impl crate::RegisterSpec for CTRLBCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbclr::R](R) reader structure"] +impl crate::Readable for CTRLBCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbclr::W](W) writer structure"] +impl crate::Writable for CTRLBCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLBCLR to value 0"] +impl crate::Resettable for CTRLBCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/tc0/count8/ctrlbset.rs b/pac/atsamc20n/src/tc0/count8/ctrlbset.rs new file mode 100644 index 000000000000..610914c9c7c8 --- /dev/null +++ b/pac/atsamc20n/src/tc0/count8/ctrlbset.rs @@ -0,0 +1,345 @@ +#[doc = "Register `CTRLBSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Counter Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `LUPD` reader - Lock Update"] +pub struct LUPD_R(crate::FieldReader); +impl LUPD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LUPD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LUPD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LUPD` writer - Lock Update"] +pub struct LUPD_W<'a> { + w: &'a mut W, +} +impl<'a> LUPD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ONESHOT` reader - One-Shot on Counter"] +pub struct ONESHOT_R(crate::FieldReader); +impl ONESHOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONESHOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONESHOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONESHOT` writer - One-Shot on Counter"] +pub struct ONESHOT_W<'a> { + w: &'a mut W, +} +impl<'a> ONESHOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Force a start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force a stop"] + STOP = 2, + #[doc = "3: Force update of double-buffered register"] + UPDATE = 3, + #[doc = "4: Force a read synchronization of COUNT"] + READSYNC = 4, + #[doc = "5: One-shot DMA trigger"] + DMAOS = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NONE), + 1 => Some(CMD_A::RETRIGGER), + 2 => Some(CMD_A::STOP), + 3 => Some(CMD_A::UPDATE), + 4 => Some(CMD_A::READSYNC), + 5 => Some(CMD_A::DMAOS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == CMD_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == CMD_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == CMD_A::STOP + } + #[doc = "Checks if the value of the field is `UPDATE`"] + #[inline(always)] + pub fn is_update(&self) -> bool { + **self == CMD_A::UPDATE + } + #[doc = "Checks if the value of the field is `READSYNC`"] + #[inline(always)] + pub fn is_readsync(&self) -> bool { + **self == CMD_A::READSYNC + } + #[doc = "Checks if the value of the field is `DMAOS`"] + #[inline(always)] + pub fn is_dmaos(&self) -> bool { + **self == CMD_A::DMAOS + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMD_A::NONE) + } + #[doc = "Force a start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMD_A::RETRIGGER) + } + #[doc = "Force a stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMD_A::STOP) + } + #[doc = "Force update of double-buffered register"] + #[inline(always)] + pub fn update(self) -> &'a mut W { + self.variant(CMD_A::UPDATE) + } + #[doc = "Force a read synchronization of COUNT"] + #[inline(always)] + pub fn readsync(self) -> &'a mut W { + self.variant(CMD_A::READSYNC) + } + #[doc = "One-shot DMA trigger"] + #[inline(always)] + pub fn dmaos(self) -> &'a mut W { + self.variant(CMD_A::DMAOS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 5)) | ((value as u8 & 0x07) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&self) -> LUPD_R { + LUPD_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 5) & 0x07) as u8) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&mut self) -> LUPD_W { + LUPD_W { w: self } + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&mut self) -> ONESHOT_W { + ONESHOT_W { w: self } + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbset](index.html) module"] +pub struct CTRLBSET_SPEC; +impl crate::RegisterSpec for CTRLBSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbset::R](R) reader structure"] +impl crate::Readable for CTRLBSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbset::W](W) writer structure"] +impl crate::Writable for CTRLBSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLBSET to value 0"] +impl crate::Resettable for CTRLBSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/tc0/count8/dbgctrl.rs b/pac/atsamc20n/src/tc0/count8/dbgctrl.rs new file mode 100644 index 000000000000..0383e70d0429 --- /dev/null +++ b/pac/atsamc20n/src/tc0/count8/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Run During Debug"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Run During Debug"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/tc0/count8/drvctrl.rs b/pac/atsamc20n/src/tc0/count8/drvctrl.rs new file mode 100644 index 000000000000..323926b4b22d --- /dev/null +++ b/pac/atsamc20n/src/tc0/count8/drvctrl.rs @@ -0,0 +1,160 @@ +#[doc = "Register `DRVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DRVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INVEN0` reader - Output Waveform Invert Enable 0"] +pub struct INVEN0_R(crate::FieldReader); +impl INVEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN0` writer - Output Waveform Invert Enable 0"] +pub struct INVEN0_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `INVEN1` reader - Output Waveform Invert Enable 1"] +pub struct INVEN1_R(crate::FieldReader); +impl INVEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN1` writer - Output Waveform Invert Enable 1"] +pub struct INVEN1_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - Output Waveform Invert Enable 0"] + #[inline(always)] + pub fn inven0(&self) -> INVEN0_R { + INVEN0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Output Waveform Invert Enable 1"] + #[inline(always)] + pub fn inven1(&self) -> INVEN1_R { + INVEN1_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Output Waveform Invert Enable 0"] + #[inline(always)] + pub fn inven0(&mut self) -> INVEN0_W { + INVEN0_W { w: self } + } + #[doc = "Bit 1 - Output Waveform Invert Enable 1"] + #[inline(always)] + pub fn inven1(&mut self) -> INVEN1_W { + INVEN1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control C\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [drvctrl](index.html) module"] +pub struct DRVCTRL_SPEC; +impl crate::RegisterSpec for DRVCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [drvctrl::R](R) reader structure"] +impl crate::Readable for DRVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [drvctrl::W](W) writer structure"] +impl crate::Writable for DRVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DRVCTRL to value 0"] +impl crate::Resettable for DRVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/tc0/count8/evctrl.rs b/pac/atsamc20n/src/tc0/count8/evctrl.rs new file mode 100644 index 000000000000..7d4c38d486c1 --- /dev/null +++ b/pac/atsamc20n/src/tc0/count8/evctrl.rs @@ -0,0 +1,465 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Event Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EVACT_A { + #[doc = "0: Event action disabled"] + OFF = 0, + #[doc = "1: Start, restart or retrigger TC on event"] + RETRIGGER = 1, + #[doc = "2: Count on event"] + COUNT = 2, + #[doc = "3: Start TC on event"] + START = 3, + #[doc = "4: Time stamp capture"] + STAMP = 4, + #[doc = "5: Period catured in CC0, pulse width in CC1"] + PPW = 5, + #[doc = "6: Period catured in CC1, pulse width in CC0"] + PWP = 6, + #[doc = "7: Pulse width capture"] + PW = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EVACT_A) -> Self { + variant as _ + } +} +#[doc = "Field `EVACT` reader - Event Action"] +pub struct EVACT_R(crate::FieldReader); +impl EVACT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVACT_A { + match self.bits { + 0 => EVACT_A::OFF, + 1 => EVACT_A::RETRIGGER, + 2 => EVACT_A::COUNT, + 3 => EVACT_A::START, + 4 => EVACT_A::STAMP, + 5 => EVACT_A::PPW, + 6 => EVACT_A::PWP, + 7 => EVACT_A::PW, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == EVACT_A::OFF + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == EVACT_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `COUNT`"] + #[inline(always)] + pub fn is_count(&self) -> bool { + **self == EVACT_A::COUNT + } + #[doc = "Checks if the value of the field is `START`"] + #[inline(always)] + pub fn is_start(&self) -> bool { + **self == EVACT_A::START + } + #[doc = "Checks if the value of the field is `STAMP`"] + #[inline(always)] + pub fn is_stamp(&self) -> bool { + **self == EVACT_A::STAMP + } + #[doc = "Checks if the value of the field is `PPW`"] + #[inline(always)] + pub fn is_ppw(&self) -> bool { + **self == EVACT_A::PPW + } + #[doc = "Checks if the value of the field is `PWP`"] + #[inline(always)] + pub fn is_pwp(&self) -> bool { + **self == EVACT_A::PWP + } + #[doc = "Checks if the value of the field is `PW`"] + #[inline(always)] + pub fn is_pw(&self) -> bool { + **self == EVACT_A::PW + } +} +impl core::ops::Deref for EVACT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT` writer - Event Action"] +pub struct EVACT_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EVACT_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Event action disabled"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(EVACT_A::OFF) + } + #[doc = "Start, restart or retrigger TC on event"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(EVACT_A::RETRIGGER) + } + #[doc = "Count on event"] + #[inline(always)] + pub fn count(self) -> &'a mut W { + self.variant(EVACT_A::COUNT) + } + #[doc = "Start TC on event"] + #[inline(always)] + pub fn start(self) -> &'a mut W { + self.variant(EVACT_A::START) + } + #[doc = "Time stamp capture"] + #[inline(always)] + pub fn stamp(self) -> &'a mut W { + self.variant(EVACT_A::STAMP) + } + #[doc = "Period catured in CC0, pulse width in CC1"] + #[inline(always)] + pub fn ppw(self) -> &'a mut W { + self.variant(EVACT_A::PPW) + } + #[doc = "Period catured in CC1, pulse width in CC0"] + #[inline(always)] + pub fn pwp(self) -> &'a mut W { + self.variant(EVACT_A::PWP) + } + #[doc = "Pulse width capture"] + #[inline(always)] + pub fn pw(self) -> &'a mut W { + self.variant(EVACT_A::PW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u16 & 0x07); + self.w + } +} +#[doc = "Field `TCINV` reader - TC Event Input Polarity"] +pub struct TCINV_R(crate::FieldReader); +impl TCINV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCINV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCINV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCINV` writer - TC Event Input Polarity"] +pub struct TCINV_W<'a> { + w: &'a mut W, +} +impl<'a> TCINV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `TCEI` reader - TC Event Enable"] +pub struct TCEI_R(crate::FieldReader); +impl TCEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCEI` writer - TC Event Enable"] +pub struct TCEI_W<'a> { + w: &'a mut W, +} +impl<'a> TCEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `OVFEO` reader - Event Output Enable"] +pub struct OVFEO_R(crate::FieldReader); +impl OVFEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVFEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVFEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVFEO` writer - Event Output Enable"] +pub struct OVFEO_W<'a> { + w: &'a mut W, +} +impl<'a> OVFEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `MCEO0` reader - MC Event Output Enable 0"] +pub struct MCEO0_R(crate::FieldReader); +impl MCEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO0` writer - MC Event Output Enable 0"] +pub struct MCEO0_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u16 & 0x01) << 12); + self.w + } +} +#[doc = "Field `MCEO1` reader - MC Event Output Enable 1"] +pub struct MCEO1_R(crate::FieldReader); +impl MCEO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO1` writer - MC Event Output Enable 1"] +pub struct MCEO1_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u16 & 0x01) << 13); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Event Action"] + #[inline(always)] + pub fn evact(&self) -> EVACT_R { + EVACT_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 4 - TC Event Input Polarity"] + #[inline(always)] + pub fn tcinv(&self) -> TCINV_R { + TCINV_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - TC Event Enable"] + #[inline(always)] + pub fn tcei(&self) -> TCEI_R { + TCEI_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 8 - Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&self) -> OVFEO_R { + OVFEO_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 12 - MC Event Output Enable 0"] + #[inline(always)] + pub fn mceo0(&self) -> MCEO0_R { + MCEO0_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - MC Event Output Enable 1"] + #[inline(always)] + pub fn mceo1(&self) -> MCEO1_R { + MCEO1_R::new(((self.bits >> 13) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Event Action"] + #[inline(always)] + pub fn evact(&mut self) -> EVACT_W { + EVACT_W { w: self } + } + #[doc = "Bit 4 - TC Event Input Polarity"] + #[inline(always)] + pub fn tcinv(&mut self) -> TCINV_W { + TCINV_W { w: self } + } + #[doc = "Bit 5 - TC Event Enable"] + #[inline(always)] + pub fn tcei(&mut self) -> TCEI_W { + TCEI_W { w: self } + } + #[doc = "Bit 8 - Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&mut self) -> OVFEO_W { + OVFEO_W { w: self } + } + #[doc = "Bit 12 - MC Event Output Enable 0"] + #[inline(always)] + pub fn mceo0(&mut self) -> MCEO0_W { + MCEO0_W { w: self } + } + #[doc = "Bit 13 - MC Event Output Enable 1"] + #[inline(always)] + pub fn mceo1(&mut self) -> MCEO1_W { + MCEO1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/tc0/count8/intenclr.rs b/pac/atsamc20n/src/tc0/count8/intenclr.rs new file mode 100644 index 000000000000..af01ef5b7dca --- /dev/null +++ b/pac/atsamc20n/src/tc0/count8/intenclr.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - OVF Interrupt Disable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - OVF Interrupt Disable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - ERR Interrupt Disable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - ERR Interrupt Disable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MC0` reader - MC Interrupt Disable 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - MC Interrupt Disable 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - MC Interrupt Disable 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - MC Interrupt Disable 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - OVF Interrupt Disable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ERR Interrupt Disable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - MC Interrupt Disable 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - MC Interrupt Disable 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - OVF Interrupt Disable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - ERR Interrupt Disable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 4 - MC Interrupt Disable 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - MC Interrupt Disable 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/tc0/count8/intenset.rs b/pac/atsamc20n/src/tc0/count8/intenset.rs new file mode 100644 index 000000000000..0e1883a2f20a --- /dev/null +++ b/pac/atsamc20n/src/tc0/count8/intenset.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - OVF Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - OVF Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - ERR Interrupt Enable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - ERR Interrupt Enable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MC0` reader - MC Interrupt Enable 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - MC Interrupt Enable 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - MC Interrupt Enable 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - MC Interrupt Enable 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - OVF Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ERR Interrupt Enable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - MC Interrupt Enable 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - MC Interrupt Enable 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - OVF Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - ERR Interrupt Enable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 4 - MC Interrupt Enable 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - MC Interrupt Enable 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/tc0/count8/intflag.rs b/pac/atsamc20n/src/tc0/count8/intflag.rs new file mode 100644 index 000000000000..1dddffaf8e7f --- /dev/null +++ b/pac/atsamc20n/src/tc0/count8/intflag.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - OVF Interrupt Flag"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - OVF Interrupt Flag"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - ERR Interrupt Flag"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - ERR Interrupt Flag"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MC0` reader - MC Interrupt Flag 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - MC Interrupt Flag 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - MC Interrupt Flag 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - MC Interrupt Flag 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - OVF Interrupt Flag"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ERR Interrupt Flag"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - MC Interrupt Flag 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - MC Interrupt Flag 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - OVF Interrupt Flag"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - ERR Interrupt Flag"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 4 - MC Interrupt Flag 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - MC Interrupt Flag 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/tc0/count8/per.rs b/pac/atsamc20n/src/tc0/count8/per.rs new file mode 100644 index 000000000000..c9ab52e247d8 --- /dev/null +++ b/pac/atsamc20n/src/tc0/count8/per.rs @@ -0,0 +1,103 @@ +#[doc = "Register `PER` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PER` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER` reader - Period Value"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` writer - Period Value"] +pub struct PER_W<'a> { + w: &'a mut W, +} +impl<'a> PER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Period Value"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Period Value"] + #[inline(always)] + pub fn per(&mut self) -> PER_W { + PER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT8 Period\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [per](index.html) module"] +pub struct PER_SPEC; +impl crate::RegisterSpec for PER_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [per::R](R) reader structure"] +impl crate::Readable for PER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [per::W](W) writer structure"] +impl crate::Writable for PER_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PER to value 0xff"] +impl crate::Resettable for PER_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xff + } +} diff --git a/pac/atsamc20n/src/tc0/count8/perbuf.rs b/pac/atsamc20n/src/tc0/count8/perbuf.rs new file mode 100644 index 000000000000..cbd500e2bbe1 --- /dev/null +++ b/pac/atsamc20n/src/tc0/count8/perbuf.rs @@ -0,0 +1,103 @@ +#[doc = "Register `PERBUF` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PERBUF` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PERBUF` reader - Period Buffer Value"] +pub struct PERBUF_R(crate::FieldReader); +impl PERBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PERBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERBUF` writer - Period Buffer Value"] +pub struct PERBUF_W<'a> { + w: &'a mut W, +} +impl<'a> PERBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Period Buffer Value"] + #[inline(always)] + pub fn perbuf(&self) -> PERBUF_R { + PERBUF_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Period Buffer Value"] + #[inline(always)] + pub fn perbuf(&mut self) -> PERBUF_W { + PERBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT8 Period Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [perbuf](index.html) module"] +pub struct PERBUF_SPEC; +impl crate::RegisterSpec for PERBUF_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [perbuf::R](R) reader structure"] +impl crate::Readable for PERBUF_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [perbuf::W](W) writer structure"] +impl crate::Writable for PERBUF_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PERBUF to value 0xff"] +impl crate::Resettable for PERBUF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xff + } +} diff --git a/pac/atsamc20n/src/tc0/count8/status.rs b/pac/atsamc20n/src/tc0/count8/status.rs new file mode 100644 index 000000000000..5088af446830 --- /dev/null +++ b/pac/atsamc20n/src/tc0/count8/status.rs @@ -0,0 +1,301 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `STOP` reader - Stop Status Flag"] +pub struct STOP_R(crate::FieldReader); +impl STOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STOP` writer - Stop Status Flag"] +pub struct STOP_W<'a> { + w: &'a mut W, +} +impl<'a> STOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SLAVE` reader - Slave Status Flag"] +pub struct SLAVE_R(crate::FieldReader); +impl SLAVE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLAVE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SLAVE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLAVE` writer - Slave Status Flag"] +pub struct SLAVE_W<'a> { + w: &'a mut W, +} +impl<'a> SLAVE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PERBUFV` reader - Synchronization Busy Status"] +pub struct PERBUFV_R(crate::FieldReader); +impl PERBUFV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PERBUFV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERBUFV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERBUFV` writer - Synchronization Busy Status"] +pub struct PERBUFV_W<'a> { + w: &'a mut W, +} +impl<'a> PERBUFV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CCBUFV0` reader - Compare channel buffer 0 valid"] +pub struct CCBUFV0_R(crate::FieldReader); +impl CCBUFV0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBUFV0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUFV0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUFV0` writer - Compare channel buffer 0 valid"] +pub struct CCBUFV0_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUFV0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `CCBUFV1` reader - Compare channel buffer 1 valid"] +pub struct CCBUFV1_R(crate::FieldReader); +impl CCBUFV1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBUFV1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUFV1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUFV1` writer - Compare channel buffer 1 valid"] +pub struct CCBUFV1_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUFV1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Stop Status Flag"] + #[inline(always)] + pub fn stop(&self) -> STOP_R { + STOP_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Slave Status Flag"] + #[inline(always)] + pub fn slave(&self) -> SLAVE_R { + SLAVE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 3 - Synchronization Busy Status"] + #[inline(always)] + pub fn perbufv(&self) -> PERBUFV_R { + PERBUFV_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Compare channel buffer 0 valid"] + #[inline(always)] + pub fn ccbufv0(&self) -> CCBUFV0_R { + CCBUFV0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Compare channel buffer 1 valid"] + #[inline(always)] + pub fn ccbufv1(&self) -> CCBUFV1_R { + CCBUFV1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Stop Status Flag"] + #[inline(always)] + pub fn stop(&mut self) -> STOP_W { + STOP_W { w: self } + } + #[doc = "Bit 1 - Slave Status Flag"] + #[inline(always)] + pub fn slave(&mut self) -> SLAVE_W { + SLAVE_W { w: self } + } + #[doc = "Bit 3 - Synchronization Busy Status"] + #[inline(always)] + pub fn perbufv(&mut self) -> PERBUFV_W { + PERBUFV_W { w: self } + } + #[doc = "Bit 4 - Compare channel buffer 0 valid"] + #[inline(always)] + pub fn ccbufv0(&mut self) -> CCBUFV0_W { + CCBUFV0_W { w: self } + } + #[doc = "Bit 5 - Compare channel buffer 1 valid"] + #[inline(always)] + pub fn ccbufv1(&mut self) -> CCBUFV1_W { + CCBUFV1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0x01"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pac/atsamc20n/src/tc0/count8/syncbusy.rs b/pac/atsamc20n/src/tc0/count8/syncbusy.rs new file mode 100644 index 000000000000..7ad8d91a84de --- /dev/null +++ b/pac/atsamc20n/src/tc0/count8/syncbusy.rs @@ -0,0 +1,193 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - swrst"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLB` reader - CTRLB"] +pub struct CTRLB_R(crate::FieldReader); +impl CTRLB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STATUS` reader - STATUS"] +pub struct STATUS_R(crate::FieldReader); +impl STATUS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STATUS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STATUS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` reader - Counter"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` reader - Period"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC0` reader - Compare Channel 0"] +pub struct CC0_R(crate::FieldReader); +impl CC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC1` reader - Compare Channel 1"] +pub struct CC1_R(crate::FieldReader); +impl CC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - swrst"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - CTRLB"] + #[inline(always)] + pub fn ctrlb(&self) -> CTRLB_R { + CTRLB_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - STATUS"] + #[inline(always)] + pub fn status(&self) -> STATUS_R { + STATUS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Counter"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Period"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Compare Channel 0"] + #[inline(always)] + pub fn cc0(&self) -> CC0_R { + CC0_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Compare Channel 1"] + #[inline(always)] + pub fn cc1(&self) -> CC1_R { + CC1_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +#[doc = "Synchronization Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/tc0/count8/wave.rs b/pac/atsamc20n/src/tc0/count8/wave.rs new file mode 100644 index 000000000000..46061b24b75d --- /dev/null +++ b/pac/atsamc20n/src/tc0/count8/wave.rs @@ -0,0 +1,178 @@ +#[doc = "Register `WAVE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WAVE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Waveform Generation Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WAVEGEN_A { + #[doc = "0: Normal frequency"] + NFRQ = 0, + #[doc = "1: Match frequency"] + MFRQ = 1, + #[doc = "2: Normal PWM"] + NPWM = 2, + #[doc = "3: Match PWM"] + MPWM = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WAVEGEN_A) -> Self { + variant as _ + } +} +#[doc = "Field `WAVEGEN` reader - Waveform Generation Mode"] +pub struct WAVEGEN_R(crate::FieldReader); +impl WAVEGEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WAVEGEN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> WAVEGEN_A { + match self.bits { + 0 => WAVEGEN_A::NFRQ, + 1 => WAVEGEN_A::MFRQ, + 2 => WAVEGEN_A::NPWM, + 3 => WAVEGEN_A::MPWM, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NFRQ`"] + #[inline(always)] + pub fn is_nfrq(&self) -> bool { + **self == WAVEGEN_A::NFRQ + } + #[doc = "Checks if the value of the field is `MFRQ`"] + #[inline(always)] + pub fn is_mfrq(&self) -> bool { + **self == WAVEGEN_A::MFRQ + } + #[doc = "Checks if the value of the field is `NPWM`"] + #[inline(always)] + pub fn is_npwm(&self) -> bool { + **self == WAVEGEN_A::NPWM + } + #[doc = "Checks if the value of the field is `MPWM`"] + #[inline(always)] + pub fn is_mpwm(&self) -> bool { + **self == WAVEGEN_A::MPWM + } +} +impl core::ops::Deref for WAVEGEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAVEGEN` writer - Waveform Generation Mode"] +pub struct WAVEGEN_W<'a> { + w: &'a mut W, +} +impl<'a> WAVEGEN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WAVEGEN_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Normal frequency"] + #[inline(always)] + pub fn nfrq(self) -> &'a mut W { + self.variant(WAVEGEN_A::NFRQ) + } + #[doc = "Match frequency"] + #[inline(always)] + pub fn mfrq(self) -> &'a mut W { + self.variant(WAVEGEN_A::MFRQ) + } + #[doc = "Normal PWM"] + #[inline(always)] + pub fn npwm(self) -> &'a mut W { + self.variant(WAVEGEN_A::NPWM) + } + #[doc = "Match PWM"] + #[inline(always)] + pub fn mpwm(self) -> &'a mut W { + self.variant(WAVEGEN_A::MPWM) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u8 & 0x03); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Waveform Generation Mode"] + #[inline(always)] + pub fn wavegen(&self) -> WAVEGEN_R { + WAVEGEN_R::new((self.bits & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Waveform Generation Mode"] + #[inline(always)] + pub fn wavegen(&mut self) -> WAVEGEN_W { + WAVEGEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Waveform Generation Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wave](index.html) module"] +pub struct WAVE_SPEC; +impl crate::RegisterSpec for WAVE_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [wave::R](R) reader structure"] +impl crate::Readable for WAVE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wave::W](W) writer structure"] +impl crate::Writable for WAVE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WAVE to value 0"] +impl crate::Resettable for WAVE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/tcc0.rs b/pac/atsamc20n/src/tcc0.rs new file mode 100644 index 000000000000..6ce813a9e3d5 --- /dev/null +++ b/pac/atsamc20n/src/tcc0.rs @@ -0,0 +1,359 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - Control B Clear"] + pub ctrlbclr: crate::Reg, + #[doc = "0x05 - Control B Set"] + pub ctrlbset: crate::Reg, + _reserved3: [u8; 0x02], + #[doc = "0x08 - Synchronization Busy"] + pub syncbusy: crate::Reg, + #[doc = "0x0c - Recoverable Fault A Configuration"] + pub fctrla: crate::Reg, + #[doc = "0x10 - Recoverable Fault B Configuration"] + pub fctrlb: crate::Reg, + #[doc = "0x14 - Waveform Extension Configuration"] + pub wexctrl: crate::Reg, + #[doc = "0x18 - Driver Control"] + pub drvctrl: crate::Reg, + _reserved8: [u8; 0x02], + #[doc = "0x1e - Debug Control"] + pub dbgctrl: crate::Reg, + _reserved9: [u8; 0x01], + #[doc = "0x20 - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x24 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x28 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x2c - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x30 - Status"] + pub status: crate::Reg, + _reserved_14_count: [u8; 0x04], + #[doc = "0x38 - Pattern"] + pub patt: crate::Reg, + _reserved16: [u8; 0x02], + #[doc = "0x3c - Waveform Control"] + pub wave: crate::Reg, + _reserved_17_per: [u8; 0x04], + _reserved_18_cc: [u8; 0x10], + _reserved19: [u8; 0x10], + #[doc = "0x64 - Pattern Buffer"] + pub pattbuf: crate::Reg, + _reserved20: [u8; 0x06], + _reserved_20_perbuf: [u8; 0x04], + _reserved_21_ccbuf: [u8; 0x10], +} +impl RegisterBlock { + #[doc = "0x34 - Count"] + #[inline(always)] + pub fn count_dith6_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(52usize) + as *const crate::Reg) + } + } + #[doc = "0x34 - Count"] + #[inline(always)] + pub fn count_dith5_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(52usize) + as *const crate::Reg) + } + } + #[doc = "0x34 - Count"] + #[inline(always)] + pub fn count_dith4_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(52usize) + as *const crate::Reg) + } + } + #[doc = "0x34 - Count"] + #[inline(always)] + pub fn count(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(52usize) + as *const crate::Reg) + } + } + #[doc = "0x40 - Period"] + #[inline(always)] + pub fn per_dith6_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(64usize) + as *const crate::Reg) + } + } + #[doc = "0x40 - Period"] + #[inline(always)] + pub fn per_dith5_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(64usize) + as *const crate::Reg) + } + } + #[doc = "0x40 - Period"] + #[inline(always)] + pub fn per_dith4_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(64usize) + as *const crate::Reg) + } + } + #[doc = "0x40 - Period"] + #[inline(always)] + pub fn per(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(64usize) + as *const crate::Reg) + } + } + #[doc = "0x44..0x54 - Compare and Capture"] + #[inline(always)] + pub fn cc_dith6_mode(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(68usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x44..0x54 - Compare and Capture"] + #[inline(always)] + pub fn cc_dith5_mode(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(68usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x44..0x54 - Compare and Capture"] + #[inline(always)] + pub fn cc_dith4_mode(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(68usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x44..0x54 - Compare and Capture"] + #[inline(always)] + pub fn cc(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(68usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x6c - Period Buffer"] + #[inline(always)] + pub fn perbuf_dith6_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(108usize) + as *const crate::Reg) + } + } + #[doc = "0x6c - Period Buffer"] + #[inline(always)] + pub fn perbuf_dith5_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(108usize) + as *const crate::Reg) + } + } + #[doc = "0x6c - Period Buffer"] + #[inline(always)] + pub fn perbuf_dith4_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(108usize) + as *const crate::Reg) + } + } + #[doc = "0x6c - Period Buffer"] + #[inline(always)] + pub fn perbuf(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(108usize) + as *const crate::Reg) + } + } + #[doc = "0x70..0x80 - Compare and Capture Buffer"] + #[inline(always)] + pub fn ccbuf_dith6_mode(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(112usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x70..0x80 - Compare and Capture Buffer"] + #[inline(always)] + pub fn ccbuf_dith5_mode(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(112usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x70..0x80 - Compare and Capture Buffer"] + #[inline(always)] + pub fn ccbuf_dith4_mode(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(112usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x70..0x80 - Compare and Capture Buffer"] + #[inline(always)] + pub fn ccbuf(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(112usize) + as *const [crate::Reg; 4]) + } + } +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "CTRLBCLR register accessor: an alias for `Reg`"] +pub type CTRLBCLR = crate::Reg; +#[doc = "Control B Clear"] +pub mod ctrlbclr; +#[doc = "CTRLBSET register accessor: an alias for `Reg`"] +pub type CTRLBSET = crate::Reg; +#[doc = "Control B Set"] +pub mod ctrlbset; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Busy"] +pub mod syncbusy; +#[doc = "FCTRLA register accessor: an alias for `Reg`"] +pub type FCTRLA = crate::Reg; +#[doc = "Recoverable Fault A Configuration"] +pub mod fctrla; +#[doc = "FCTRLB register accessor: an alias for `Reg`"] +pub type FCTRLB = crate::Reg; +#[doc = "Recoverable Fault B Configuration"] +pub mod fctrlb; +#[doc = "WEXCTRL register accessor: an alias for `Reg`"] +pub type WEXCTRL = crate::Reg; +#[doc = "Waveform Extension Configuration"] +pub mod wexctrl; +#[doc = "DRVCTRL register accessor: an alias for `Reg`"] +pub type DRVCTRL = crate::Reg; +#[doc = "Driver Control"] +pub mod drvctrl; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "COUNT register accessor: an alias for `Reg`"] +pub type COUNT = crate::Reg; +#[doc = "Count"] +pub mod count; +#[doc = "COUNT_DITH4_MODE register accessor: an alias for `Reg`"] +pub type COUNT_DITH4_MODE = crate::Reg; +#[doc = "Count"] +pub mod count_dith4_mode; +#[doc = "COUNT_DITH5_MODE register accessor: an alias for `Reg`"] +pub type COUNT_DITH5_MODE = crate::Reg; +#[doc = "Count"] +pub mod count_dith5_mode; +#[doc = "COUNT_DITH6_MODE register accessor: an alias for `Reg`"] +pub type COUNT_DITH6_MODE = crate::Reg; +#[doc = "Count"] +pub mod count_dith6_mode; +#[doc = "PATT register accessor: an alias for `Reg`"] +pub type PATT = crate::Reg; +#[doc = "Pattern"] +pub mod patt; +#[doc = "WAVE register accessor: an alias for `Reg`"] +pub type WAVE = crate::Reg; +#[doc = "Waveform Control"] +pub mod wave; +#[doc = "PER register accessor: an alias for `Reg`"] +pub type PER = crate::Reg; +#[doc = "Period"] +pub mod per; +#[doc = "PER_DITH4_MODE register accessor: an alias for `Reg`"] +pub type PER_DITH4_MODE = crate::Reg; +#[doc = "Period"] +pub mod per_dith4_mode; +#[doc = "PER_DITH5_MODE register accessor: an alias for `Reg`"] +pub type PER_DITH5_MODE = crate::Reg; +#[doc = "Period"] +pub mod per_dith5_mode; +#[doc = "PER_DITH6_MODE register accessor: an alias for `Reg`"] +pub type PER_DITH6_MODE = crate::Reg; +#[doc = "Period"] +pub mod per_dith6_mode; +#[doc = "CC register accessor: an alias for `Reg`"] +pub type CC = crate::Reg; +#[doc = "Compare and Capture"] +pub mod cc; +#[doc = "CC_DITH4_MODE register accessor: an alias for `Reg`"] +pub type CC_DITH4_MODE = crate::Reg; +#[doc = "Compare and Capture"] +pub mod cc_dith4_mode; +#[doc = "CC_DITH5_MODE register accessor: an alias for `Reg`"] +pub type CC_DITH5_MODE = crate::Reg; +#[doc = "Compare and Capture"] +pub mod cc_dith5_mode; +#[doc = "CC_DITH6_MODE register accessor: an alias for `Reg`"] +pub type CC_DITH6_MODE = crate::Reg; +#[doc = "Compare and Capture"] +pub mod cc_dith6_mode; +#[doc = "PATTBUF register accessor: an alias for `Reg`"] +pub type PATTBUF = crate::Reg; +#[doc = "Pattern Buffer"] +pub mod pattbuf; +#[doc = "PERBUF register accessor: an alias for `Reg`"] +pub type PERBUF = crate::Reg; +#[doc = "Period Buffer"] +pub mod perbuf; +#[doc = "PERBUF_DITH4_MODE register accessor: an alias for `Reg`"] +pub type PERBUF_DITH4_MODE = crate::Reg; +#[doc = "Period Buffer"] +pub mod perbuf_dith4_mode; +#[doc = "PERBUF_DITH5_MODE register accessor: an alias for `Reg`"] +pub type PERBUF_DITH5_MODE = crate::Reg; +#[doc = "Period Buffer"] +pub mod perbuf_dith5_mode; +#[doc = "PERBUF_DITH6_MODE register accessor: an alias for `Reg`"] +pub type PERBUF_DITH6_MODE = crate::Reg; +#[doc = "Period Buffer"] +pub mod perbuf_dith6_mode; +#[doc = "CCBUF register accessor: an alias for `Reg`"] +pub type CCBUF = crate::Reg; +#[doc = "Compare and Capture Buffer"] +pub mod ccbuf; +#[doc = "CCBUF_DITH4_MODE register accessor: an alias for `Reg`"] +pub type CCBUF_DITH4_MODE = crate::Reg; +#[doc = "Compare and Capture Buffer"] +pub mod ccbuf_dith4_mode; +#[doc = "CCBUF_DITH5_MODE register accessor: an alias for `Reg`"] +pub type CCBUF_DITH5_MODE = crate::Reg; +#[doc = "Compare and Capture Buffer"] +pub mod ccbuf_dith5_mode; +#[doc = "CCBUF_DITH6_MODE register accessor: an alias for `Reg`"] +pub type CCBUF_DITH6_MODE = crate::Reg; +#[doc = "Compare and Capture Buffer"] +pub mod ccbuf_dith6_mode; diff --git a/pac/atsamc20n/src/tcc0/cc.rs b/pac/atsamc20n/src/tcc0/cc.rs new file mode 100644 index 000000000000..c4d6df7a9a20 --- /dev/null +++ b/pac/atsamc20n/src/tcc0/cc.rs @@ -0,0 +1,104 @@ +#[doc = "Register `CC[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CC[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CC` reader - Channel Compare/Capture Value"] +pub struct CC_R(crate::FieldReader); +impl CC_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC` writer - Channel Compare/Capture Value"] +pub struct CC_W<'a> { + w: &'a mut W, +} +impl<'a> CC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&self) -> CC_R { + CC_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&mut self) -> CC_W { + CC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc](index.html) module"] +pub struct CC_SPEC; +impl crate::RegisterSpec for CC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cc::R](R) reader structure"] +impl crate::Readable for CC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cc::W](W) writer structure"] +impl crate::Writable for CC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CC[%s] +to value 0"] +impl crate::Resettable for CC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/tcc0/cc_dith4_mode.rs b/pac/atsamc20n/src/tcc0/cc_dith4_mode.rs new file mode 100644 index 000000000000..c45d8b6bac41 --- /dev/null +++ b/pac/atsamc20n/src/tcc0/cc_dith4_mode.rs @@ -0,0 +1,141 @@ +#[doc = "Register `CC_DITH4_MODE[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CC_DITH4_MODE[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHER` reader - Dithering Cycle Number"] +pub struct DITHER_R(crate::FieldReader); +impl DITHER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHER` writer - Dithering Cycle Number"] +pub struct DITHER_W<'a> { + w: &'a mut W, +} +impl<'a> DITHER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Field `CC` reader - Channel Compare/Capture Value"] +pub struct CC_R(crate::FieldReader); +impl CC_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC` writer - Channel Compare/Capture Value"] +pub struct CC_W<'a> { + w: &'a mut W, +} +impl<'a> CC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x000f_ffff << 4)) | ((value as u32 & 0x000f_ffff) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&self) -> DITHER_R { + DITHER_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&self) -> CC_R { + CC_R::new(((self.bits >> 4) & 0x000f_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:3 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&mut self) -> DITHER_W { + DITHER_W { w: self } + } + #[doc = "Bits 4:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&mut self) -> CC_W { + CC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc_dith4_mode](index.html) module"] +pub struct CC_DITH4_MODE_SPEC; +impl crate::RegisterSpec for CC_DITH4_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cc_dith4_mode::R](R) reader structure"] +impl crate::Readable for CC_DITH4_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cc_dith4_mode::W](W) writer structure"] +impl crate::Writable for CC_DITH4_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CC_DITH4_MODE[%s] +to value 0"] +impl crate::Resettable for CC_DITH4_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/tcc0/cc_dith5_mode.rs b/pac/atsamc20n/src/tcc0/cc_dith5_mode.rs new file mode 100644 index 000000000000..0592b923051a --- /dev/null +++ b/pac/atsamc20n/src/tcc0/cc_dith5_mode.rs @@ -0,0 +1,141 @@ +#[doc = "Register `CC_DITH5_MODE[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CC_DITH5_MODE[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHER` reader - Dithering Cycle Number"] +pub struct DITHER_R(crate::FieldReader); +impl DITHER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHER` writer - Dithering Cycle Number"] +pub struct DITHER_W<'a> { + w: &'a mut W, +} +impl<'a> DITHER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f); + self.w + } +} +#[doc = "Field `CC` reader - Channel Compare/Capture Value"] +pub struct CC_R(crate::FieldReader); +impl CC_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC` writer - Channel Compare/Capture Value"] +pub struct CC_W<'a> { + w: &'a mut W, +} +impl<'a> CC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0007_ffff << 5)) | ((value as u32 & 0x0007_ffff) << 5); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&self) -> DITHER_R { + DITHER_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&self) -> CC_R { + CC_R::new(((self.bits >> 5) & 0x0007_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:4 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&mut self) -> DITHER_W { + DITHER_W { w: self } + } + #[doc = "Bits 5:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&mut self) -> CC_W { + CC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc_dith5_mode](index.html) module"] +pub struct CC_DITH5_MODE_SPEC; +impl crate::RegisterSpec for CC_DITH5_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cc_dith5_mode::R](R) reader structure"] +impl crate::Readable for CC_DITH5_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cc_dith5_mode::W](W) writer structure"] +impl crate::Writable for CC_DITH5_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CC_DITH5_MODE[%s] +to value 0"] +impl crate::Resettable for CC_DITH5_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/tcc0/cc_dith6_mode.rs b/pac/atsamc20n/src/tcc0/cc_dith6_mode.rs new file mode 100644 index 000000000000..62a82a872426 --- /dev/null +++ b/pac/atsamc20n/src/tcc0/cc_dith6_mode.rs @@ -0,0 +1,141 @@ +#[doc = "Register `CC_DITH6_MODE[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CC_DITH6_MODE[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHER` reader - Dithering Cycle Number"] +pub struct DITHER_R(crate::FieldReader); +impl DITHER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHER` writer - Dithering Cycle Number"] +pub struct DITHER_W<'a> { + w: &'a mut W, +} +impl<'a> DITHER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +#[doc = "Field `CC` reader - Channel Compare/Capture Value"] +pub struct CC_R(crate::FieldReader); +impl CC_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC` writer - Channel Compare/Capture Value"] +pub struct CC_W<'a> { + w: &'a mut W, +} +impl<'a> CC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0003_ffff << 6)) | ((value as u32 & 0x0003_ffff) << 6); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&self) -> DITHER_R { + DITHER_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&self) -> CC_R { + CC_R::new(((self.bits >> 6) & 0x0003_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:5 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&mut self) -> DITHER_W { + DITHER_W { w: self } + } + #[doc = "Bits 6:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&mut self) -> CC_W { + CC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc_dith6_mode](index.html) module"] +pub struct CC_DITH6_MODE_SPEC; +impl crate::RegisterSpec for CC_DITH6_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cc_dith6_mode::R](R) reader structure"] +impl crate::Readable for CC_DITH6_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cc_dith6_mode::W](W) writer structure"] +impl crate::Writable for CC_DITH6_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CC_DITH6_MODE[%s] +to value 0"] +impl crate::Resettable for CC_DITH6_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/tcc0/ccbuf.rs b/pac/atsamc20n/src/tcc0/ccbuf.rs new file mode 100644 index 000000000000..a4db1135f095 --- /dev/null +++ b/pac/atsamc20n/src/tcc0/ccbuf.rs @@ -0,0 +1,104 @@ +#[doc = "Register `CCBUF[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CCBUF[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CCBUF` reader - Channel Compare/Capture Buffer Value"] +pub struct CCBUF_R(crate::FieldReader); +impl CCBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CCBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUF` writer - Channel Compare/Capture Buffer Value"] +pub struct CCBUF_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccbuf(&self) -> CCBUF_R { + CCBUF_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccbuf(&mut self) -> CCBUF_W { + CCBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccbuf](index.html) module"] +pub struct CCBUF_SPEC; +impl crate::RegisterSpec for CCBUF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ccbuf::R](R) reader structure"] +impl crate::Readable for CCBUF_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ccbuf::W](W) writer structure"] +impl crate::Writable for CCBUF_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CCBUF[%s] +to value 0"] +impl crate::Resettable for CCBUF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/tcc0/ccbuf_dith4_mode.rs b/pac/atsamc20n/src/tcc0/ccbuf_dith4_mode.rs new file mode 100644 index 000000000000..dfa16e936175 --- /dev/null +++ b/pac/atsamc20n/src/tcc0/ccbuf_dith4_mode.rs @@ -0,0 +1,141 @@ +#[doc = "Register `CCBUF_DITH4_MODE[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CCBUF_DITH4_MODE[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CCBUF` reader - Channel Compare/Capture Buffer Value"] +pub struct CCBUF_R(crate::FieldReader); +impl CCBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CCBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUF` writer - Channel Compare/Capture Buffer Value"] +pub struct CCBUF_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Field `DITHERBUF` reader - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_R(crate::FieldReader); +impl DITHERBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + DITHERBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHERBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHERBUF` writer - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_W<'a> { + w: &'a mut W, +} +impl<'a> DITHERBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x000f_ffff << 4)) | ((value as u32 & 0x000f_ffff) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccbuf(&self) -> CCBUF_R { + CCBUF_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:23 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&self) -> DITHERBUF_R { + DITHERBUF_R::new(((self.bits >> 4) & 0x000f_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:3 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccbuf(&mut self) -> CCBUF_W { + CCBUF_W { w: self } + } + #[doc = "Bits 4:23 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&mut self) -> DITHERBUF_W { + DITHERBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccbuf_dith4_mode](index.html) module"] +pub struct CCBUF_DITH4_MODE_SPEC; +impl crate::RegisterSpec for CCBUF_DITH4_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ccbuf_dith4_mode::R](R) reader structure"] +impl crate::Readable for CCBUF_DITH4_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ccbuf_dith4_mode::W](W) writer structure"] +impl crate::Writable for CCBUF_DITH4_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CCBUF_DITH4_MODE[%s] +to value 0"] +impl crate::Resettable for CCBUF_DITH4_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/tcc0/ccbuf_dith5_mode.rs b/pac/atsamc20n/src/tcc0/ccbuf_dith5_mode.rs new file mode 100644 index 000000000000..0c78ba3303c0 --- /dev/null +++ b/pac/atsamc20n/src/tcc0/ccbuf_dith5_mode.rs @@ -0,0 +1,141 @@ +#[doc = "Register `CCBUF_DITH5_MODE[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CCBUF_DITH5_MODE[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHERBUF` reader - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_R(crate::FieldReader); +impl DITHERBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHERBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHERBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHERBUF` writer - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_W<'a> { + w: &'a mut W, +} +impl<'a> DITHERBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f); + self.w + } +} +#[doc = "Field `CCBUF` reader - Channel Compare/Capture Buffer Value"] +pub struct CCBUF_R(crate::FieldReader); +impl CCBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CCBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUF` writer - Channel Compare/Capture Buffer Value"] +pub struct CCBUF_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0007_ffff << 5)) | ((value as u32 & 0x0007_ffff) << 5); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&self) -> DITHERBUF_R { + DITHERBUF_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:23 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccbuf(&self) -> CCBUF_R { + CCBUF_R::new(((self.bits >> 5) & 0x0007_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:4 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&mut self) -> DITHERBUF_W { + DITHERBUF_W { w: self } + } + #[doc = "Bits 5:23 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccbuf(&mut self) -> CCBUF_W { + CCBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccbuf_dith5_mode](index.html) module"] +pub struct CCBUF_DITH5_MODE_SPEC; +impl crate::RegisterSpec for CCBUF_DITH5_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ccbuf_dith5_mode::R](R) reader structure"] +impl crate::Readable for CCBUF_DITH5_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ccbuf_dith5_mode::W](W) writer structure"] +impl crate::Writable for CCBUF_DITH5_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CCBUF_DITH5_MODE[%s] +to value 0"] +impl crate::Resettable for CCBUF_DITH5_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/tcc0/ccbuf_dith6_mode.rs b/pac/atsamc20n/src/tcc0/ccbuf_dith6_mode.rs new file mode 100644 index 000000000000..8d19b8a9e595 --- /dev/null +++ b/pac/atsamc20n/src/tcc0/ccbuf_dith6_mode.rs @@ -0,0 +1,141 @@ +#[doc = "Register `CCBUF_DITH6_MODE[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CCBUF_DITH6_MODE[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHERBUF` reader - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_R(crate::FieldReader); +impl DITHERBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHERBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHERBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHERBUF` writer - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_W<'a> { + w: &'a mut W, +} +impl<'a> DITHERBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +#[doc = "Field `CCBUF` reader - Channel Compare/Capture Buffer Value"] +pub struct CCBUF_R(crate::FieldReader); +impl CCBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CCBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUF` writer - Channel Compare/Capture Buffer Value"] +pub struct CCBUF_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0003_ffff << 6)) | ((value as u32 & 0x0003_ffff) << 6); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&self) -> DITHERBUF_R { + DITHERBUF_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:23 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccbuf(&self) -> CCBUF_R { + CCBUF_R::new(((self.bits >> 6) & 0x0003_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:5 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&mut self) -> DITHERBUF_W { + DITHERBUF_W { w: self } + } + #[doc = "Bits 6:23 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccbuf(&mut self) -> CCBUF_W { + CCBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccbuf_dith6_mode](index.html) module"] +pub struct CCBUF_DITH6_MODE_SPEC; +impl crate::RegisterSpec for CCBUF_DITH6_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ccbuf_dith6_mode::R](R) reader structure"] +impl crate::Readable for CCBUF_DITH6_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ccbuf_dith6_mode::W](W) writer structure"] +impl crate::Writable for CCBUF_DITH6_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CCBUF_DITH6_MODE[%s] +to value 0"] +impl crate::Resettable for CCBUF_DITH6_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/tcc0/count.rs b/pac/atsamc20n/src/tcc0/count.rs new file mode 100644 index 000000000000..7628f2c0d5e1 --- /dev/null +++ b/pac/atsamc20n/src/tcc0/count.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Count\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count](index.html) module"] +pub struct COUNT_SPEC; +impl crate::RegisterSpec for COUNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [count::R](R) reader structure"] +impl crate::Readable for COUNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count::W](W) writer structure"] +impl crate::Writable for COUNT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT to value 0"] +impl crate::Resettable for COUNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/tcc0/count_dith4_mode.rs b/pac/atsamc20n/src/tcc0/count_dith4_mode.rs new file mode 100644 index 000000000000..fc058ae5efd5 --- /dev/null +++ b/pac/atsamc20n/src/tcc0/count_dith4_mode.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT_DITH4_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT_DITH4_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x000f_ffff << 4)) | ((value as u32 & 0x000f_ffff) << 4); + self.w + } +} +impl R { + #[doc = "Bits 4:23 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 4) & 0x000f_ffff) as u32) + } +} +impl W { + #[doc = "Bits 4:23 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Count\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count_dith4_mode](index.html) module"] +pub struct COUNT_DITH4_MODE_SPEC; +impl crate::RegisterSpec for COUNT_DITH4_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [count_dith4_mode::R](R) reader structure"] +impl crate::Readable for COUNT_DITH4_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count_dith4_mode::W](W) writer structure"] +impl crate::Writable for COUNT_DITH4_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT_DITH4_MODE to value 0"] +impl crate::Resettable for COUNT_DITH4_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/tcc0/count_dith5_mode.rs b/pac/atsamc20n/src/tcc0/count_dith5_mode.rs new file mode 100644 index 000000000000..e66e20310726 --- /dev/null +++ b/pac/atsamc20n/src/tcc0/count_dith5_mode.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT_DITH5_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT_DITH5_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0007_ffff << 5)) | ((value as u32 & 0x0007_ffff) << 5); + self.w + } +} +impl R { + #[doc = "Bits 5:23 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 5) & 0x0007_ffff) as u32) + } +} +impl W { + #[doc = "Bits 5:23 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Count\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count_dith5_mode](index.html) module"] +pub struct COUNT_DITH5_MODE_SPEC; +impl crate::RegisterSpec for COUNT_DITH5_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [count_dith5_mode::R](R) reader structure"] +impl crate::Readable for COUNT_DITH5_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count_dith5_mode::W](W) writer structure"] +impl crate::Writable for COUNT_DITH5_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT_DITH5_MODE to value 0"] +impl crate::Resettable for COUNT_DITH5_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/tcc0/count_dith6_mode.rs b/pac/atsamc20n/src/tcc0/count_dith6_mode.rs new file mode 100644 index 000000000000..5410fc6c9459 --- /dev/null +++ b/pac/atsamc20n/src/tcc0/count_dith6_mode.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT_DITH6_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT_DITH6_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0003_ffff << 6)) | ((value as u32 & 0x0003_ffff) << 6); + self.w + } +} +impl R { + #[doc = "Bits 6:23 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 6) & 0x0003_ffff) as u32) + } +} +impl W { + #[doc = "Bits 6:23 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Count\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count_dith6_mode](index.html) module"] +pub struct COUNT_DITH6_MODE_SPEC; +impl crate::RegisterSpec for COUNT_DITH6_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [count_dith6_mode::R](R) reader structure"] +impl crate::Readable for COUNT_DITH6_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count_dith6_mode::W](W) writer structure"] +impl crate::Writable for COUNT_DITH6_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT_DITH6_MODE to value 0"] +impl crate::Resettable for COUNT_DITH6_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/tcc0/ctrla.rs b/pac/atsamc20n/src/tcc0/ctrla.rs new file mode 100644 index 000000000000..b717d1ac6ae0 --- /dev/null +++ b/pac/atsamc20n/src/tcc0/ctrla.rs @@ -0,0 +1,911 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Enhanced Resolution\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum RESOLUTION_A { + #[doc = "0: Dithering is disabled"] + NONE = 0, + #[doc = "1: Dithering is done every 16 PWM frames"] + DITH4 = 1, + #[doc = "2: Dithering is done every 32 PWM frames"] + DITH5 = 2, + #[doc = "3: Dithering is done every 64 PWM frames"] + DITH6 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RESOLUTION_A) -> Self { + variant as _ + } +} +#[doc = "Field `RESOLUTION` reader - Enhanced Resolution"] +pub struct RESOLUTION_R(crate::FieldReader); +impl RESOLUTION_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RESOLUTION_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RESOLUTION_A { + match self.bits { + 0 => RESOLUTION_A::NONE, + 1 => RESOLUTION_A::DITH4, + 2 => RESOLUTION_A::DITH5, + 3 => RESOLUTION_A::DITH6, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == RESOLUTION_A::NONE + } + #[doc = "Checks if the value of the field is `DITH4`"] + #[inline(always)] + pub fn is_dith4(&self) -> bool { + **self == RESOLUTION_A::DITH4 + } + #[doc = "Checks if the value of the field is `DITH5`"] + #[inline(always)] + pub fn is_dith5(&self) -> bool { + **self == RESOLUTION_A::DITH5 + } + #[doc = "Checks if the value of the field is `DITH6`"] + #[inline(always)] + pub fn is_dith6(&self) -> bool { + **self == RESOLUTION_A::DITH6 + } +} +impl core::ops::Deref for RESOLUTION_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESOLUTION` writer - Enhanced Resolution"] +pub struct RESOLUTION_W<'a> { + w: &'a mut W, +} +impl<'a> RESOLUTION_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RESOLUTION_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Dithering is disabled"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(RESOLUTION_A::NONE) + } + #[doc = "Dithering is done every 16 PWM frames"] + #[inline(always)] + pub fn dith4(self) -> &'a mut W { + self.variant(RESOLUTION_A::DITH4) + } + #[doc = "Dithering is done every 32 PWM frames"] + #[inline(always)] + pub fn dith5(self) -> &'a mut W { + self.variant(RESOLUTION_A::DITH5) + } + #[doc = "Dithering is done every 64 PWM frames"] + #[inline(always)] + pub fn dith6(self) -> &'a mut W { + self.variant(RESOLUTION_A::DITH6) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 5)) | ((value as u32 & 0x03) << 5); + self.w + } +} +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: No division"] + DIV1 = 0, + #[doc = "1: Divide by 2"] + DIV2 = 1, + #[doc = "2: Divide by 4"] + DIV4 = 2, + #[doc = "3: Divide by 8"] + DIV8 = 3, + #[doc = "4: Divide by 16"] + DIV16 = 4, + #[doc = "5: Divide by 64"] + DIV64 = 5, + #[doc = "6: Divide by 256"] + DIV256 = 6, + #[doc = "7: Divide by 1024"] + DIV1024 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PRESCALER_A { + match self.bits { + 0 => PRESCALER_A::DIV1, + 1 => PRESCALER_A::DIV2, + 2 => PRESCALER_A::DIV4, + 3 => PRESCALER_A::DIV8, + 4 => PRESCALER_A::DIV16, + 5 => PRESCALER_A::DIV64, + 6 => PRESCALER_A::DIV256, + 7 => PRESCALER_A::DIV1024, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == PRESCALER_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PRESCALER_A::DIV1024 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "No division"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1) + } + #[doc = "Divide by 2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "Divide by 4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "Divide by 8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "Divide by 16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "Divide by 64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "Divide by 256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = "Divide by 1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Prescaler and Counter Synchronization Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCSYNC_A { + #[doc = "0: Reload or reset counter on next GCLK"] + GCLK = 0, + #[doc = "1: Reload or reset counter on next prescaler clock"] + PRESC = 1, + #[doc = "2: Reload or reset counter on next GCLK and reset prescaler counter"] + RESYNC = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCSYNC_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCSYNC` reader - Prescaler and Counter Synchronization Selection"] +pub struct PRESCSYNC_R(crate::FieldReader); +impl PRESCSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCSYNC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCSYNC_A::GCLK), + 1 => Some(PRESCSYNC_A::PRESC), + 2 => Some(PRESCSYNC_A::RESYNC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `GCLK`"] + #[inline(always)] + pub fn is_gclk(&self) -> bool { + **self == PRESCSYNC_A::GCLK + } + #[doc = "Checks if the value of the field is `PRESC`"] + #[inline(always)] + pub fn is_presc(&self) -> bool { + **self == PRESCSYNC_A::PRESC + } + #[doc = "Checks if the value of the field is `RESYNC`"] + #[inline(always)] + pub fn is_resync(&self) -> bool { + **self == PRESCSYNC_A::RESYNC + } +} +impl core::ops::Deref for PRESCSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCSYNC` writer - Prescaler and Counter Synchronization Selection"] +pub struct PRESCSYNC_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCSYNC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCSYNC_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Reload or reset counter on next GCLK"] + #[inline(always)] + pub fn gclk(self) -> &'a mut W { + self.variant(PRESCSYNC_A::GCLK) + } + #[doc = "Reload or reset counter on next prescaler clock"] + #[inline(always)] + pub fn presc(self) -> &'a mut W { + self.variant(PRESCSYNC_A::PRESC) + } + #[doc = "Reload or reset counter on next GCLK and reset prescaler counter"] + #[inline(always)] + pub fn resync(self) -> &'a mut W { + self.variant(PRESCSYNC_A::RESYNC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 12)) | ((value as u32 & 0x03) << 12); + self.w + } +} +#[doc = "Field `ALOCK` reader - Auto Lock"] +pub struct ALOCK_R(crate::FieldReader); +impl ALOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALOCK` writer - Auto Lock"] +pub struct ALOCK_W<'a> { + w: &'a mut W, +} +impl<'a> ALOCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `MSYNC` reader - Master Synchronization (only for TCC Slave Instance)"] +pub struct MSYNC_R(crate::FieldReader); +impl MSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MSYNC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MSYNC` writer - Master Synchronization (only for TCC Slave Instance)"] +pub struct MSYNC_W<'a> { + w: &'a mut W, +} +impl<'a> MSYNC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `DMAOS` reader - DMA One-shot Trigger Mode"] +pub struct DMAOS_R(crate::FieldReader); +impl DMAOS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DMAOS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DMAOS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DMAOS` writer - DMA One-shot Trigger Mode"] +pub struct DMAOS_W<'a> { + w: &'a mut W, +} +impl<'a> DMAOS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `CPTEN0` reader - Capture Channel 0 Enable"] +pub struct CPTEN0_R(crate::FieldReader); +impl CPTEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPTEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CPTEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPTEN0` writer - Capture Channel 0 Enable"] +pub struct CPTEN0_W<'a> { + w: &'a mut W, +} +impl<'a> CPTEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `CPTEN1` reader - Capture Channel 1 Enable"] +pub struct CPTEN1_R(crate::FieldReader); +impl CPTEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPTEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CPTEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPTEN1` writer - Capture Channel 1 Enable"] +pub struct CPTEN1_W<'a> { + w: &'a mut W, +} +impl<'a> CPTEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `CPTEN2` reader - Capture Channel 2 Enable"] +pub struct CPTEN2_R(crate::FieldReader); +impl CPTEN2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPTEN2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CPTEN2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPTEN2` writer - Capture Channel 2 Enable"] +pub struct CPTEN2_W<'a> { + w: &'a mut W, +} +impl<'a> CPTEN2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `CPTEN3` reader - Capture Channel 3 Enable"] +pub struct CPTEN3_R(crate::FieldReader); +impl CPTEN3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPTEN3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CPTEN3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPTEN3` writer - Capture Channel 3 Enable"] +pub struct CPTEN3_W<'a> { + w: &'a mut W, +} +impl<'a> CPTEN3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 5:6 - Enhanced Resolution"] + #[inline(always)] + pub fn resolution(&self) -> RESOLUTION_R { + RESOLUTION_R::new(((self.bits >> 5) & 0x03) as u8) + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 11 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bits 12:13 - Prescaler and Counter Synchronization Selection"] + #[inline(always)] + pub fn prescsync(&self) -> PRESCSYNC_R { + PRESCSYNC_R::new(((self.bits >> 12) & 0x03) as u8) + } + #[doc = "Bit 14 - Auto Lock"] + #[inline(always)] + pub fn alock(&self) -> ALOCK_R { + ALOCK_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Master Synchronization (only for TCC Slave Instance)"] + #[inline(always)] + pub fn msync(&self) -> MSYNC_R { + MSYNC_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 23 - DMA One-shot Trigger Mode"] + #[inline(always)] + pub fn dmaos(&self) -> DMAOS_R { + DMAOS_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn cpten0(&self) -> CPTEN0_R { + CPTEN0_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn cpten1(&self) -> CPTEN1_R { + CPTEN1_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Capture Channel 2 Enable"] + #[inline(always)] + pub fn cpten2(&self) -> CPTEN2_R { + CPTEN2_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Capture Channel 3 Enable"] + #[inline(always)] + pub fn cpten3(&self) -> CPTEN3_R { + CPTEN3_R::new(((self.bits >> 27) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 5:6 - Enhanced Resolution"] + #[inline(always)] + pub fn resolution(&mut self) -> RESOLUTION_W { + RESOLUTION_W { w: self } + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Bit 11 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bits 12:13 - Prescaler and Counter Synchronization Selection"] + #[inline(always)] + pub fn prescsync(&mut self) -> PRESCSYNC_W { + PRESCSYNC_W { w: self } + } + #[doc = "Bit 14 - Auto Lock"] + #[inline(always)] + pub fn alock(&mut self) -> ALOCK_W { + ALOCK_W { w: self } + } + #[doc = "Bit 15 - Master Synchronization (only for TCC Slave Instance)"] + #[inline(always)] + pub fn msync(&mut self) -> MSYNC_W { + MSYNC_W { w: self } + } + #[doc = "Bit 23 - DMA One-shot Trigger Mode"] + #[inline(always)] + pub fn dmaos(&mut self) -> DMAOS_W { + DMAOS_W { w: self } + } + #[doc = "Bit 24 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn cpten0(&mut self) -> CPTEN0_W { + CPTEN0_W { w: self } + } + #[doc = "Bit 25 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn cpten1(&mut self) -> CPTEN1_W { + CPTEN1_W { w: self } + } + #[doc = "Bit 26 - Capture Channel 2 Enable"] + #[inline(always)] + pub fn cpten2(&mut self) -> CPTEN2_W { + CPTEN2_W { w: self } + } + #[doc = "Bit 27 - Capture Channel 3 Enable"] + #[inline(always)] + pub fn cpten3(&mut self) -> CPTEN3_W { + CPTEN3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/tcc0/ctrlbclr.rs b/pac/atsamc20n/src/tcc0/ctrlbclr.rs new file mode 100644 index 000000000000..f96ce81ffde3 --- /dev/null +++ b/pac/atsamc20n/src/tcc0/ctrlbclr.rs @@ -0,0 +1,457 @@ +#[doc = "Register `CTRLBCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Counter Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `LUPD` reader - Lock Update"] +pub struct LUPD_R(crate::FieldReader); +impl LUPD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LUPD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LUPD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LUPD` writer - Lock Update"] +pub struct LUPD_W<'a> { + w: &'a mut W, +} +impl<'a> LUPD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ONESHOT` reader - One-Shot"] +pub struct ONESHOT_R(crate::FieldReader); +impl ONESHOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONESHOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONESHOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONESHOT` writer - One-Shot"] +pub struct ONESHOT_W<'a> { + w: &'a mut W, +} +impl<'a> ONESHOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Ramp Index Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum IDXCMD_A { + #[doc = "0: Command disabled: Index toggles between cycles A and B"] + DISABLE = 0, + #[doc = "1: Set index: cycle B will be forced in the next cycle"] + SET = 1, + #[doc = "2: Clear index: cycle A will be forced in the next cycle"] + CLEAR = 2, + #[doc = "3: Hold index: the next cycle will be the same as the current cycle"] + HOLD = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: IDXCMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `IDXCMD` reader - Ramp Index Command"] +pub struct IDXCMD_R(crate::FieldReader); +impl IDXCMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + IDXCMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> IDXCMD_A { + match self.bits { + 0 => IDXCMD_A::DISABLE, + 1 => IDXCMD_A::SET, + 2 => IDXCMD_A::CLEAR, + 3 => IDXCMD_A::HOLD, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == IDXCMD_A::DISABLE + } + #[doc = "Checks if the value of the field is `SET`"] + #[inline(always)] + pub fn is_set(&self) -> bool { + **self == IDXCMD_A::SET + } + #[doc = "Checks if the value of the field is `CLEAR`"] + #[inline(always)] + pub fn is_clear(&self) -> bool { + **self == IDXCMD_A::CLEAR + } + #[doc = "Checks if the value of the field is `HOLD`"] + #[inline(always)] + pub fn is_hold(&self) -> bool { + **self == IDXCMD_A::HOLD + } +} +impl core::ops::Deref for IDXCMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IDXCMD` writer - Ramp Index Command"] +pub struct IDXCMD_W<'a> { + w: &'a mut W, +} +impl<'a> IDXCMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: IDXCMD_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Command disabled: Index toggles between cycles A and B"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(IDXCMD_A::DISABLE) + } + #[doc = "Set index: cycle B will be forced in the next cycle"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(IDXCMD_A::SET) + } + #[doc = "Clear index: cycle A will be forced in the next cycle"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(IDXCMD_A::CLEAR) + } + #[doc = "Hold index: the next cycle will be the same as the current cycle"] + #[inline(always)] + pub fn hold(self) -> &'a mut W { + self.variant(IDXCMD_A::HOLD) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 3)) | ((value as u8 & 0x03) << 3); + self.w + } +} +#[doc = "TCC Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Clear start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force stop"] + STOP = 2, + #[doc = "3: Force update or double buffered registers"] + UPDATE = 3, + #[doc = "4: Force COUNT read synchronization"] + READSYNC = 4, + #[doc = "5: One-shot DMA trigger"] + DMAOS = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - TCC Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NONE), + 1 => Some(CMD_A::RETRIGGER), + 2 => Some(CMD_A::STOP), + 3 => Some(CMD_A::UPDATE), + 4 => Some(CMD_A::READSYNC), + 5 => Some(CMD_A::DMAOS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == CMD_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == CMD_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == CMD_A::STOP + } + #[doc = "Checks if the value of the field is `UPDATE`"] + #[inline(always)] + pub fn is_update(&self) -> bool { + **self == CMD_A::UPDATE + } + #[doc = "Checks if the value of the field is `READSYNC`"] + #[inline(always)] + pub fn is_readsync(&self) -> bool { + **self == CMD_A::READSYNC + } + #[doc = "Checks if the value of the field is `DMAOS`"] + #[inline(always)] + pub fn is_dmaos(&self) -> bool { + **self == CMD_A::DMAOS + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - TCC Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMD_A::NONE) + } + #[doc = "Clear start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMD_A::RETRIGGER) + } + #[doc = "Force stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMD_A::STOP) + } + #[doc = "Force update or double buffered registers"] + #[inline(always)] + pub fn update(self) -> &'a mut W { + self.variant(CMD_A::UPDATE) + } + #[doc = "Force COUNT read synchronization"] + #[inline(always)] + pub fn readsync(self) -> &'a mut W { + self.variant(CMD_A::READSYNC) + } + #[doc = "One-shot DMA trigger"] + #[inline(always)] + pub fn dmaos(self) -> &'a mut W { + self.variant(CMD_A::DMAOS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 5)) | ((value as u8 & 0x07) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&self) -> LUPD_R { + LUPD_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - One-Shot"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 3:4 - Ramp Index Command"] + #[inline(always)] + pub fn idxcmd(&self) -> IDXCMD_R { + IDXCMD_R::new(((self.bits >> 3) & 0x03) as u8) + } + #[doc = "Bits 5:7 - TCC Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 5) & 0x07) as u8) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&mut self) -> LUPD_W { + LUPD_W { w: self } + } + #[doc = "Bit 2 - One-Shot"] + #[inline(always)] + pub fn oneshot(&mut self) -> ONESHOT_W { + ONESHOT_W { w: self } + } + #[doc = "Bits 3:4 - Ramp Index Command"] + #[inline(always)] + pub fn idxcmd(&mut self) -> IDXCMD_W { + IDXCMD_W { w: self } + } + #[doc = "Bits 5:7 - TCC Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbclr](index.html) module"] +pub struct CTRLBCLR_SPEC; +impl crate::RegisterSpec for CTRLBCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbclr::R](R) reader structure"] +impl crate::Readable for CTRLBCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbclr::W](W) writer structure"] +impl crate::Writable for CTRLBCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLBCLR to value 0"] +impl crate::Resettable for CTRLBCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/tcc0/ctrlbset.rs b/pac/atsamc20n/src/tcc0/ctrlbset.rs new file mode 100644 index 000000000000..7002dd71efe7 --- /dev/null +++ b/pac/atsamc20n/src/tcc0/ctrlbset.rs @@ -0,0 +1,457 @@ +#[doc = "Register `CTRLBSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Counter Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `LUPD` reader - Lock Update"] +pub struct LUPD_R(crate::FieldReader); +impl LUPD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LUPD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LUPD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LUPD` writer - Lock Update"] +pub struct LUPD_W<'a> { + w: &'a mut W, +} +impl<'a> LUPD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ONESHOT` reader - One-Shot"] +pub struct ONESHOT_R(crate::FieldReader); +impl ONESHOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONESHOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONESHOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONESHOT` writer - One-Shot"] +pub struct ONESHOT_W<'a> { + w: &'a mut W, +} +impl<'a> ONESHOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Ramp Index Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum IDXCMD_A { + #[doc = "0: Command disabled: Index toggles between cycles A and B"] + DISABLE = 0, + #[doc = "1: Set index: cycle B will be forced in the next cycle"] + SET = 1, + #[doc = "2: Clear index: cycle A will be forced in the next cycle"] + CLEAR = 2, + #[doc = "3: Hold index: the next cycle will be the same as the current cycle"] + HOLD = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: IDXCMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `IDXCMD` reader - Ramp Index Command"] +pub struct IDXCMD_R(crate::FieldReader); +impl IDXCMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + IDXCMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> IDXCMD_A { + match self.bits { + 0 => IDXCMD_A::DISABLE, + 1 => IDXCMD_A::SET, + 2 => IDXCMD_A::CLEAR, + 3 => IDXCMD_A::HOLD, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == IDXCMD_A::DISABLE + } + #[doc = "Checks if the value of the field is `SET`"] + #[inline(always)] + pub fn is_set(&self) -> bool { + **self == IDXCMD_A::SET + } + #[doc = "Checks if the value of the field is `CLEAR`"] + #[inline(always)] + pub fn is_clear(&self) -> bool { + **self == IDXCMD_A::CLEAR + } + #[doc = "Checks if the value of the field is `HOLD`"] + #[inline(always)] + pub fn is_hold(&self) -> bool { + **self == IDXCMD_A::HOLD + } +} +impl core::ops::Deref for IDXCMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IDXCMD` writer - Ramp Index Command"] +pub struct IDXCMD_W<'a> { + w: &'a mut W, +} +impl<'a> IDXCMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: IDXCMD_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Command disabled: Index toggles between cycles A and B"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(IDXCMD_A::DISABLE) + } + #[doc = "Set index: cycle B will be forced in the next cycle"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(IDXCMD_A::SET) + } + #[doc = "Clear index: cycle A will be forced in the next cycle"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(IDXCMD_A::CLEAR) + } + #[doc = "Hold index: the next cycle will be the same as the current cycle"] + #[inline(always)] + pub fn hold(self) -> &'a mut W { + self.variant(IDXCMD_A::HOLD) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 3)) | ((value as u8 & 0x03) << 3); + self.w + } +} +#[doc = "TCC Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Clear start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force stop"] + STOP = 2, + #[doc = "3: Force update or double buffered registers"] + UPDATE = 3, + #[doc = "4: Force COUNT read synchronization"] + READSYNC = 4, + #[doc = "5: One-shot DMA trigger"] + DMAOS = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - TCC Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NONE), + 1 => Some(CMD_A::RETRIGGER), + 2 => Some(CMD_A::STOP), + 3 => Some(CMD_A::UPDATE), + 4 => Some(CMD_A::READSYNC), + 5 => Some(CMD_A::DMAOS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == CMD_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == CMD_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == CMD_A::STOP + } + #[doc = "Checks if the value of the field is `UPDATE`"] + #[inline(always)] + pub fn is_update(&self) -> bool { + **self == CMD_A::UPDATE + } + #[doc = "Checks if the value of the field is `READSYNC`"] + #[inline(always)] + pub fn is_readsync(&self) -> bool { + **self == CMD_A::READSYNC + } + #[doc = "Checks if the value of the field is `DMAOS`"] + #[inline(always)] + pub fn is_dmaos(&self) -> bool { + **self == CMD_A::DMAOS + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - TCC Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMD_A::NONE) + } + #[doc = "Clear start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMD_A::RETRIGGER) + } + #[doc = "Force stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMD_A::STOP) + } + #[doc = "Force update or double buffered registers"] + #[inline(always)] + pub fn update(self) -> &'a mut W { + self.variant(CMD_A::UPDATE) + } + #[doc = "Force COUNT read synchronization"] + #[inline(always)] + pub fn readsync(self) -> &'a mut W { + self.variant(CMD_A::READSYNC) + } + #[doc = "One-shot DMA trigger"] + #[inline(always)] + pub fn dmaos(self) -> &'a mut W { + self.variant(CMD_A::DMAOS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 5)) | ((value as u8 & 0x07) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&self) -> LUPD_R { + LUPD_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - One-Shot"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 3:4 - Ramp Index Command"] + #[inline(always)] + pub fn idxcmd(&self) -> IDXCMD_R { + IDXCMD_R::new(((self.bits >> 3) & 0x03) as u8) + } + #[doc = "Bits 5:7 - TCC Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 5) & 0x07) as u8) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&mut self) -> LUPD_W { + LUPD_W { w: self } + } + #[doc = "Bit 2 - One-Shot"] + #[inline(always)] + pub fn oneshot(&mut self) -> ONESHOT_W { + ONESHOT_W { w: self } + } + #[doc = "Bits 3:4 - Ramp Index Command"] + #[inline(always)] + pub fn idxcmd(&mut self) -> IDXCMD_W { + IDXCMD_W { w: self } + } + #[doc = "Bits 5:7 - TCC Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbset](index.html) module"] +pub struct CTRLBSET_SPEC; +impl crate::RegisterSpec for CTRLBSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbset::R](R) reader structure"] +impl crate::Readable for CTRLBSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbset::W](W) writer structure"] +impl crate::Writable for CTRLBSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLBSET to value 0"] +impl crate::Resettable for CTRLBSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/tcc0/dbgctrl.rs b/pac/atsamc20n/src/tcc0/dbgctrl.rs new file mode 100644 index 000000000000..313ebe3f5c18 --- /dev/null +++ b/pac/atsamc20n/src/tcc0/dbgctrl.rs @@ -0,0 +1,160 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Debug Running Mode"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Debug Running Mode"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `FDDBD` reader - Fault Detection on Debug Break Detection"] +pub struct FDDBD_R(crate::FieldReader); +impl FDDBD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FDDBD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FDDBD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FDDBD` writer - Fault Detection on Debug Break Detection"] +pub struct FDDBD_W<'a> { + w: &'a mut W, +} +impl<'a> FDDBD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Running Mode"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 2 - Fault Detection on Debug Break Detection"] + #[inline(always)] + pub fn fddbd(&self) -> FDDBD_R { + FDDBD_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Running Mode"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Bit 2 - Fault Detection on Debug Break Detection"] + #[inline(always)] + pub fn fddbd(&mut self) -> FDDBD_W { + FDDBD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/tcc0/drvctrl.rs b/pac/atsamc20n/src/tcc0/drvctrl.rs new file mode 100644 index 000000000000..316041e1e3be --- /dev/null +++ b/pac/atsamc20n/src/tcc0/drvctrl.rs @@ -0,0 +1,1268 @@ +#[doc = "Register `DRVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DRVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `NRE0` reader - Non-Recoverable State 0 Output Enable"] +pub struct NRE0_R(crate::FieldReader); +impl NRE0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRE0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRE0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRE0` writer - Non-Recoverable State 0 Output Enable"] +pub struct NRE0_W<'a> { + w: &'a mut W, +} +impl<'a> NRE0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `NRE1` reader - Non-Recoverable State 1 Output Enable"] +pub struct NRE1_R(crate::FieldReader); +impl NRE1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRE1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRE1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRE1` writer - Non-Recoverable State 1 Output Enable"] +pub struct NRE1_W<'a> { + w: &'a mut W, +} +impl<'a> NRE1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `NRE2` reader - Non-Recoverable State 2 Output Enable"] +pub struct NRE2_R(crate::FieldReader); +impl NRE2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRE2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRE2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRE2` writer - Non-Recoverable State 2 Output Enable"] +pub struct NRE2_W<'a> { + w: &'a mut W, +} +impl<'a> NRE2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `NRE3` reader - Non-Recoverable State 3 Output Enable"] +pub struct NRE3_R(crate::FieldReader); +impl NRE3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRE3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRE3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRE3` writer - Non-Recoverable State 3 Output Enable"] +pub struct NRE3_W<'a> { + w: &'a mut W, +} +impl<'a> NRE3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `NRE4` reader - Non-Recoverable State 4 Output Enable"] +pub struct NRE4_R(crate::FieldReader); +impl NRE4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRE4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRE4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRE4` writer - Non-Recoverable State 4 Output Enable"] +pub struct NRE4_W<'a> { + w: &'a mut W, +} +impl<'a> NRE4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `NRE5` reader - Non-Recoverable State 5 Output Enable"] +pub struct NRE5_R(crate::FieldReader); +impl NRE5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRE5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRE5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRE5` writer - Non-Recoverable State 5 Output Enable"] +pub struct NRE5_W<'a> { + w: &'a mut W, +} +impl<'a> NRE5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `NRE6` reader - Non-Recoverable State 6 Output Enable"] +pub struct NRE6_R(crate::FieldReader); +impl NRE6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRE6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRE6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRE6` writer - Non-Recoverable State 6 Output Enable"] +pub struct NRE6_W<'a> { + w: &'a mut W, +} +impl<'a> NRE6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `NRE7` reader - Non-Recoverable State 7 Output Enable"] +pub struct NRE7_R(crate::FieldReader); +impl NRE7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRE7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRE7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRE7` writer - Non-Recoverable State 7 Output Enable"] +pub struct NRE7_W<'a> { + w: &'a mut W, +} +impl<'a> NRE7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `NRV0` reader - Non-Recoverable State 0 Output Value"] +pub struct NRV0_R(crate::FieldReader); +impl NRV0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRV0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRV0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRV0` writer - Non-Recoverable State 0 Output Value"] +pub struct NRV0_W<'a> { + w: &'a mut W, +} +impl<'a> NRV0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `NRV1` reader - Non-Recoverable State 1 Output Value"] +pub struct NRV1_R(crate::FieldReader); +impl NRV1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRV1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRV1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRV1` writer - Non-Recoverable State 1 Output Value"] +pub struct NRV1_W<'a> { + w: &'a mut W, +} +impl<'a> NRV1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `NRV2` reader - Non-Recoverable State 2 Output Value"] +pub struct NRV2_R(crate::FieldReader); +impl NRV2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRV2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRV2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRV2` writer - Non-Recoverable State 2 Output Value"] +pub struct NRV2_W<'a> { + w: &'a mut W, +} +impl<'a> NRV2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `NRV3` reader - Non-Recoverable State 3 Output Value"] +pub struct NRV3_R(crate::FieldReader); +impl NRV3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRV3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRV3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRV3` writer - Non-Recoverable State 3 Output Value"] +pub struct NRV3_W<'a> { + w: &'a mut W, +} +impl<'a> NRV3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `NRV4` reader - Non-Recoverable State 4 Output Value"] +pub struct NRV4_R(crate::FieldReader); +impl NRV4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRV4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRV4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRV4` writer - Non-Recoverable State 4 Output Value"] +pub struct NRV4_W<'a> { + w: &'a mut W, +} +impl<'a> NRV4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `NRV5` reader - Non-Recoverable State 5 Output Value"] +pub struct NRV5_R(crate::FieldReader); +impl NRV5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRV5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRV5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRV5` writer - Non-Recoverable State 5 Output Value"] +pub struct NRV5_W<'a> { + w: &'a mut W, +} +impl<'a> NRV5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `NRV6` reader - Non-Recoverable State 6 Output Value"] +pub struct NRV6_R(crate::FieldReader); +impl NRV6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRV6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRV6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRV6` writer - Non-Recoverable State 6 Output Value"] +pub struct NRV6_W<'a> { + w: &'a mut W, +} +impl<'a> NRV6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `NRV7` reader - Non-Recoverable State 7 Output Value"] +pub struct NRV7_R(crate::FieldReader); +impl NRV7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRV7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRV7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRV7` writer - Non-Recoverable State 7 Output Value"] +pub struct NRV7_W<'a> { + w: &'a mut W, +} +impl<'a> NRV7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `INVEN0` reader - Output Waveform 0 Inversion"] +pub struct INVEN0_R(crate::FieldReader); +impl INVEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN0` writer - Output Waveform 0 Inversion"] +pub struct INVEN0_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `INVEN1` reader - Output Waveform 1 Inversion"] +pub struct INVEN1_R(crate::FieldReader); +impl INVEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN1` writer - Output Waveform 1 Inversion"] +pub struct INVEN1_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `INVEN2` reader - Output Waveform 2 Inversion"] +pub struct INVEN2_R(crate::FieldReader); +impl INVEN2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN2` writer - Output Waveform 2 Inversion"] +pub struct INVEN2_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `INVEN3` reader - Output Waveform 3 Inversion"] +pub struct INVEN3_R(crate::FieldReader); +impl INVEN3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN3` writer - Output Waveform 3 Inversion"] +pub struct INVEN3_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `INVEN4` reader - Output Waveform 4 Inversion"] +pub struct INVEN4_R(crate::FieldReader); +impl INVEN4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN4` writer - Output Waveform 4 Inversion"] +pub struct INVEN4_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `INVEN5` reader - Output Waveform 5 Inversion"] +pub struct INVEN5_R(crate::FieldReader); +impl INVEN5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN5` writer - Output Waveform 5 Inversion"] +pub struct INVEN5_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `INVEN6` reader - Output Waveform 6 Inversion"] +pub struct INVEN6_R(crate::FieldReader); +impl INVEN6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN6` writer - Output Waveform 6 Inversion"] +pub struct INVEN6_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `INVEN7` reader - Output Waveform 7 Inversion"] +pub struct INVEN7_R(crate::FieldReader); +impl INVEN7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN7` writer - Output Waveform 7 Inversion"] +pub struct INVEN7_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `FILTERVAL0` reader - Non-Recoverable Fault Input 0 Filter Value"] +pub struct FILTERVAL0_R(crate::FieldReader); +impl FILTERVAL0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FILTERVAL0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTERVAL0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTERVAL0` writer - Non-Recoverable Fault Input 0 Filter Value"] +pub struct FILTERVAL0_W<'a> { + w: &'a mut W, +} +impl<'a> FILTERVAL0_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Field `FILTERVAL1` reader - Non-Recoverable Fault Input 1 Filter Value"] +pub struct FILTERVAL1_R(crate::FieldReader); +impl FILTERVAL1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FILTERVAL1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTERVAL1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTERVAL1` writer - Non-Recoverable Fault Input 1 Filter Value"] +pub struct FILTERVAL1_W<'a> { + w: &'a mut W, +} +impl<'a> FILTERVAL1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 28)) | ((value as u32 & 0x0f) << 28); + self.w + } +} +impl R { + #[doc = "Bit 0 - Non-Recoverable State 0 Output Enable"] + #[inline(always)] + pub fn nre0(&self) -> NRE0_R { + NRE0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Non-Recoverable State 1 Output Enable"] + #[inline(always)] + pub fn nre1(&self) -> NRE1_R { + NRE1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Non-Recoverable State 2 Output Enable"] + #[inline(always)] + pub fn nre2(&self) -> NRE2_R { + NRE2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Non-Recoverable State 3 Output Enable"] + #[inline(always)] + pub fn nre3(&self) -> NRE3_R { + NRE3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Non-Recoverable State 4 Output Enable"] + #[inline(always)] + pub fn nre4(&self) -> NRE4_R { + NRE4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Non-Recoverable State 5 Output Enable"] + #[inline(always)] + pub fn nre5(&self) -> NRE5_R { + NRE5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Non-Recoverable State 6 Output Enable"] + #[inline(always)] + pub fn nre6(&self) -> NRE6_R { + NRE6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Non-Recoverable State 7 Output Enable"] + #[inline(always)] + pub fn nre7(&self) -> NRE7_R { + NRE7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Non-Recoverable State 0 Output Value"] + #[inline(always)] + pub fn nrv0(&self) -> NRV0_R { + NRV0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Non-Recoverable State 1 Output Value"] + #[inline(always)] + pub fn nrv1(&self) -> NRV1_R { + NRV1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Non-Recoverable State 2 Output Value"] + #[inline(always)] + pub fn nrv2(&self) -> NRV2_R { + NRV2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Non-Recoverable State 3 Output Value"] + #[inline(always)] + pub fn nrv3(&self) -> NRV3_R { + NRV3_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Non-Recoverable State 4 Output Value"] + #[inline(always)] + pub fn nrv4(&self) -> NRV4_R { + NRV4_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Non-Recoverable State 5 Output Value"] + #[inline(always)] + pub fn nrv5(&self) -> NRV5_R { + NRV5_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Non-Recoverable State 6 Output Value"] + #[inline(always)] + pub fn nrv6(&self) -> NRV6_R { + NRV6_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Non-Recoverable State 7 Output Value"] + #[inline(always)] + pub fn nrv7(&self) -> NRV7_R { + NRV7_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Output Waveform 0 Inversion"] + #[inline(always)] + pub fn inven0(&self) -> INVEN0_R { + INVEN0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Output Waveform 1 Inversion"] + #[inline(always)] + pub fn inven1(&self) -> INVEN1_R { + INVEN1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Output Waveform 2 Inversion"] + #[inline(always)] + pub fn inven2(&self) -> INVEN2_R { + INVEN2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Output Waveform 3 Inversion"] + #[inline(always)] + pub fn inven3(&self) -> INVEN3_R { + INVEN3_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Output Waveform 4 Inversion"] + #[inline(always)] + pub fn inven4(&self) -> INVEN4_R { + INVEN4_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Output Waveform 5 Inversion"] + #[inline(always)] + pub fn inven5(&self) -> INVEN5_R { + INVEN5_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Output Waveform 6 Inversion"] + #[inline(always)] + pub fn inven6(&self) -> INVEN6_R { + INVEN6_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Output Waveform 7 Inversion"] + #[inline(always)] + pub fn inven7(&self) -> INVEN7_R { + INVEN7_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bits 24:27 - Non-Recoverable Fault Input 0 Filter Value"] + #[inline(always)] + pub fn filterval0(&self) -> FILTERVAL0_R { + FILTERVAL0_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bits 28:31 - Non-Recoverable Fault Input 1 Filter Value"] + #[inline(always)] + pub fn filterval1(&self) -> FILTERVAL1_R { + FILTERVAL1_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bit 0 - Non-Recoverable State 0 Output Enable"] + #[inline(always)] + pub fn nre0(&mut self) -> NRE0_W { + NRE0_W { w: self } + } + #[doc = "Bit 1 - Non-Recoverable State 1 Output Enable"] + #[inline(always)] + pub fn nre1(&mut self) -> NRE1_W { + NRE1_W { w: self } + } + #[doc = "Bit 2 - Non-Recoverable State 2 Output Enable"] + #[inline(always)] + pub fn nre2(&mut self) -> NRE2_W { + NRE2_W { w: self } + } + #[doc = "Bit 3 - Non-Recoverable State 3 Output Enable"] + #[inline(always)] + pub fn nre3(&mut self) -> NRE3_W { + NRE3_W { w: self } + } + #[doc = "Bit 4 - Non-Recoverable State 4 Output Enable"] + #[inline(always)] + pub fn nre4(&mut self) -> NRE4_W { + NRE4_W { w: self } + } + #[doc = "Bit 5 - Non-Recoverable State 5 Output Enable"] + #[inline(always)] + pub fn nre5(&mut self) -> NRE5_W { + NRE5_W { w: self } + } + #[doc = "Bit 6 - Non-Recoverable State 6 Output Enable"] + #[inline(always)] + pub fn nre6(&mut self) -> NRE6_W { + NRE6_W { w: self } + } + #[doc = "Bit 7 - Non-Recoverable State 7 Output Enable"] + #[inline(always)] + pub fn nre7(&mut self) -> NRE7_W { + NRE7_W { w: self } + } + #[doc = "Bit 8 - Non-Recoverable State 0 Output Value"] + #[inline(always)] + pub fn nrv0(&mut self) -> NRV0_W { + NRV0_W { w: self } + } + #[doc = "Bit 9 - Non-Recoverable State 1 Output Value"] + #[inline(always)] + pub fn nrv1(&mut self) -> NRV1_W { + NRV1_W { w: self } + } + #[doc = "Bit 10 - Non-Recoverable State 2 Output Value"] + #[inline(always)] + pub fn nrv2(&mut self) -> NRV2_W { + NRV2_W { w: self } + } + #[doc = "Bit 11 - Non-Recoverable State 3 Output Value"] + #[inline(always)] + pub fn nrv3(&mut self) -> NRV3_W { + NRV3_W { w: self } + } + #[doc = "Bit 12 - Non-Recoverable State 4 Output Value"] + #[inline(always)] + pub fn nrv4(&mut self) -> NRV4_W { + NRV4_W { w: self } + } + #[doc = "Bit 13 - Non-Recoverable State 5 Output Value"] + #[inline(always)] + pub fn nrv5(&mut self) -> NRV5_W { + NRV5_W { w: self } + } + #[doc = "Bit 14 - Non-Recoverable State 6 Output Value"] + #[inline(always)] + pub fn nrv6(&mut self) -> NRV6_W { + NRV6_W { w: self } + } + #[doc = "Bit 15 - Non-Recoverable State 7 Output Value"] + #[inline(always)] + pub fn nrv7(&mut self) -> NRV7_W { + NRV7_W { w: self } + } + #[doc = "Bit 16 - Output Waveform 0 Inversion"] + #[inline(always)] + pub fn inven0(&mut self) -> INVEN0_W { + INVEN0_W { w: self } + } + #[doc = "Bit 17 - Output Waveform 1 Inversion"] + #[inline(always)] + pub fn inven1(&mut self) -> INVEN1_W { + INVEN1_W { w: self } + } + #[doc = "Bit 18 - Output Waveform 2 Inversion"] + #[inline(always)] + pub fn inven2(&mut self) -> INVEN2_W { + INVEN2_W { w: self } + } + #[doc = "Bit 19 - Output Waveform 3 Inversion"] + #[inline(always)] + pub fn inven3(&mut self) -> INVEN3_W { + INVEN3_W { w: self } + } + #[doc = "Bit 20 - Output Waveform 4 Inversion"] + #[inline(always)] + pub fn inven4(&mut self) -> INVEN4_W { + INVEN4_W { w: self } + } + #[doc = "Bit 21 - Output Waveform 5 Inversion"] + #[inline(always)] + pub fn inven5(&mut self) -> INVEN5_W { + INVEN5_W { w: self } + } + #[doc = "Bit 22 - Output Waveform 6 Inversion"] + #[inline(always)] + pub fn inven6(&mut self) -> INVEN6_W { + INVEN6_W { w: self } + } + #[doc = "Bit 23 - Output Waveform 7 Inversion"] + #[inline(always)] + pub fn inven7(&mut self) -> INVEN7_W { + INVEN7_W { w: self } + } + #[doc = "Bits 24:27 - Non-Recoverable Fault Input 0 Filter Value"] + #[inline(always)] + pub fn filterval0(&mut self) -> FILTERVAL0_W { + FILTERVAL0_W { w: self } + } + #[doc = "Bits 28:31 - Non-Recoverable Fault Input 1 Filter Value"] + #[inline(always)] + pub fn filterval1(&mut self) -> FILTERVAL1_W { + FILTERVAL1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Driver Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [drvctrl](index.html) module"] +pub struct DRVCTRL_SPEC; +impl crate::RegisterSpec for DRVCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [drvctrl::R](R) reader structure"] +impl crate::Readable for DRVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [drvctrl::W](W) writer structure"] +impl crate::Writable for DRVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DRVCTRL to value 0"] +impl crate::Resettable for DRVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/tcc0/evctrl.rs b/pac/atsamc20n/src/tcc0/evctrl.rs new file mode 100644 index 000000000000..334a53924d61 --- /dev/null +++ b/pac/atsamc20n/src/tcc0/evctrl.rs @@ -0,0 +1,1211 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Timer/counter Input Event0 Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EVACT0_A { + #[doc = "0: Event action disabled"] + OFF = 0, + #[doc = "1: Start, restart or re-trigger counter on event"] + RETRIGGER = 1, + #[doc = "2: Count on event"] + COUNTEV = 2, + #[doc = "3: Start counter on event"] + START = 3, + #[doc = "4: Increment counter on event"] + INC = 4, + #[doc = "5: Count on active state of asynchronous event"] + COUNT = 5, + #[doc = "6: Stamp capture"] + STAMP = 6, + #[doc = "7: Non-recoverable fault"] + FAULT = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EVACT0_A) -> Self { + variant as _ + } +} +#[doc = "Field `EVACT0` reader - Timer/counter Input Event0 Action"] +pub struct EVACT0_R(crate::FieldReader); +impl EVACT0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVACT0_A { + match self.bits { + 0 => EVACT0_A::OFF, + 1 => EVACT0_A::RETRIGGER, + 2 => EVACT0_A::COUNTEV, + 3 => EVACT0_A::START, + 4 => EVACT0_A::INC, + 5 => EVACT0_A::COUNT, + 6 => EVACT0_A::STAMP, + 7 => EVACT0_A::FAULT, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == EVACT0_A::OFF + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == EVACT0_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `COUNTEV`"] + #[inline(always)] + pub fn is_countev(&self) -> bool { + **self == EVACT0_A::COUNTEV + } + #[doc = "Checks if the value of the field is `START`"] + #[inline(always)] + pub fn is_start(&self) -> bool { + **self == EVACT0_A::START + } + #[doc = "Checks if the value of the field is `INC`"] + #[inline(always)] + pub fn is_inc(&self) -> bool { + **self == EVACT0_A::INC + } + #[doc = "Checks if the value of the field is `COUNT`"] + #[inline(always)] + pub fn is_count(&self) -> bool { + **self == EVACT0_A::COUNT + } + #[doc = "Checks if the value of the field is `STAMP`"] + #[inline(always)] + pub fn is_stamp(&self) -> bool { + **self == EVACT0_A::STAMP + } + #[doc = "Checks if the value of the field is `FAULT`"] + #[inline(always)] + pub fn is_fault(&self) -> bool { + **self == EVACT0_A::FAULT + } +} +impl core::ops::Deref for EVACT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT0` writer - Timer/counter Input Event0 Action"] +pub struct EVACT0_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT0_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EVACT0_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Event action disabled"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(EVACT0_A::OFF) + } + #[doc = "Start, restart or re-trigger counter on event"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(EVACT0_A::RETRIGGER) + } + #[doc = "Count on event"] + #[inline(always)] + pub fn countev(self) -> &'a mut W { + self.variant(EVACT0_A::COUNTEV) + } + #[doc = "Start counter on event"] + #[inline(always)] + pub fn start(self) -> &'a mut W { + self.variant(EVACT0_A::START) + } + #[doc = "Increment counter on event"] + #[inline(always)] + pub fn inc(self) -> &'a mut W { + self.variant(EVACT0_A::INC) + } + #[doc = "Count on active state of asynchronous event"] + #[inline(always)] + pub fn count(self) -> &'a mut W { + self.variant(EVACT0_A::COUNT) + } + #[doc = "Stamp capture"] + #[inline(always)] + pub fn stamp(self) -> &'a mut W { + self.variant(EVACT0_A::STAMP) + } + #[doc = "Non-recoverable fault"] + #[inline(always)] + pub fn fault(self) -> &'a mut W { + self.variant(EVACT0_A::FAULT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Timer/counter Input Event1 Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EVACT1_A { + #[doc = "0: Event action disabled"] + OFF = 0, + #[doc = "1: Re-trigger counter on event"] + RETRIGGER = 1, + #[doc = "2: Direction control"] + DIR = 2, + #[doc = "3: Stop counter on event"] + STOP = 3, + #[doc = "4: Decrement counter on event"] + DEC = 4, + #[doc = "5: Period capture value in CC0 register, pulse width capture value in CC1 register"] + PPW = 5, + #[doc = "6: Period capture value in CC1 register, pulse width capture value in CC0 register"] + PWP = 6, + #[doc = "7: Non-recoverable fault"] + FAULT = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EVACT1_A) -> Self { + variant as _ + } +} +#[doc = "Field `EVACT1` reader - Timer/counter Input Event1 Action"] +pub struct EVACT1_R(crate::FieldReader); +impl EVACT1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT1_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVACT1_A { + match self.bits { + 0 => EVACT1_A::OFF, + 1 => EVACT1_A::RETRIGGER, + 2 => EVACT1_A::DIR, + 3 => EVACT1_A::STOP, + 4 => EVACT1_A::DEC, + 5 => EVACT1_A::PPW, + 6 => EVACT1_A::PWP, + 7 => EVACT1_A::FAULT, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == EVACT1_A::OFF + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == EVACT1_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `DIR`"] + #[inline(always)] + pub fn is_dir(&self) -> bool { + **self == EVACT1_A::DIR + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == EVACT1_A::STOP + } + #[doc = "Checks if the value of the field is `DEC`"] + #[inline(always)] + pub fn is_dec(&self) -> bool { + **self == EVACT1_A::DEC + } + #[doc = "Checks if the value of the field is `PPW`"] + #[inline(always)] + pub fn is_ppw(&self) -> bool { + **self == EVACT1_A::PPW + } + #[doc = "Checks if the value of the field is `PWP`"] + #[inline(always)] + pub fn is_pwp(&self) -> bool { + **self == EVACT1_A::PWP + } + #[doc = "Checks if the value of the field is `FAULT`"] + #[inline(always)] + pub fn is_fault(&self) -> bool { + **self == EVACT1_A::FAULT + } +} +impl core::ops::Deref for EVACT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT1` writer - Timer/counter Input Event1 Action"] +pub struct EVACT1_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT1_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EVACT1_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Event action disabled"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(EVACT1_A::OFF) + } + #[doc = "Re-trigger counter on event"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(EVACT1_A::RETRIGGER) + } + #[doc = "Direction control"] + #[inline(always)] + pub fn dir(self) -> &'a mut W { + self.variant(EVACT1_A::DIR) + } + #[doc = "Stop counter on event"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(EVACT1_A::STOP) + } + #[doc = "Decrement counter on event"] + #[inline(always)] + pub fn dec(self) -> &'a mut W { + self.variant(EVACT1_A::DEC) + } + #[doc = "Period capture value in CC0 register, pulse width capture value in CC1 register"] + #[inline(always)] + pub fn ppw(self) -> &'a mut W { + self.variant(EVACT1_A::PPW) + } + #[doc = "Period capture value in CC1 register, pulse width capture value in CC0 register"] + #[inline(always)] + pub fn pwp(self) -> &'a mut W { + self.variant(EVACT1_A::PWP) + } + #[doc = "Non-recoverable fault"] + #[inline(always)] + pub fn fault(self) -> &'a mut W { + self.variant(EVACT1_A::FAULT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 3)) | ((value as u32 & 0x07) << 3); + self.w + } +} +#[doc = "Timer/counter Output Event Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CNTSEL_A { + #[doc = "0: An interrupt/event is generated when a new counter cycle starts"] + START = 0, + #[doc = "1: An interrupt/event is generated when a counter cycle ends"] + END = 1, + #[doc = "2: An interrupt/event is generated when a counter cycle ends, except for the first and last cycles"] + BETWEEN = 2, + #[doc = "3: An interrupt/event is generated when a new counter cycle starts or a counter cycle ends"] + BOUNDARY = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CNTSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `CNTSEL` reader - Timer/counter Output Event Mode"] +pub struct CNTSEL_R(crate::FieldReader); +impl CNTSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CNTSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CNTSEL_A { + match self.bits { + 0 => CNTSEL_A::START, + 1 => CNTSEL_A::END, + 2 => CNTSEL_A::BETWEEN, + 3 => CNTSEL_A::BOUNDARY, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `START`"] + #[inline(always)] + pub fn is_start(&self) -> bool { + **self == CNTSEL_A::START + } + #[doc = "Checks if the value of the field is `END`"] + #[inline(always)] + pub fn is_end(&self) -> bool { + **self == CNTSEL_A::END + } + #[doc = "Checks if the value of the field is `BETWEEN`"] + #[inline(always)] + pub fn is_between(&self) -> bool { + **self == CNTSEL_A::BETWEEN + } + #[doc = "Checks if the value of the field is `BOUNDARY`"] + #[inline(always)] + pub fn is_boundary(&self) -> bool { + **self == CNTSEL_A::BOUNDARY + } +} +impl core::ops::Deref for CNTSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CNTSEL` writer - Timer/counter Output Event Mode"] +pub struct CNTSEL_W<'a> { + w: &'a mut W, +} +impl<'a> CNTSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CNTSEL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "An interrupt/event is generated when a new counter cycle starts"] + #[inline(always)] + pub fn start(self) -> &'a mut W { + self.variant(CNTSEL_A::START) + } + #[doc = "An interrupt/event is generated when a counter cycle ends"] + #[inline(always)] + pub fn end(self) -> &'a mut W { + self.variant(CNTSEL_A::END) + } + #[doc = "An interrupt/event is generated when a counter cycle ends, except for the first and last cycles"] + #[inline(always)] + pub fn between(self) -> &'a mut W { + self.variant(CNTSEL_A::BETWEEN) + } + #[doc = "An interrupt/event is generated when a new counter cycle starts or a counter cycle ends"] + #[inline(always)] + pub fn boundary(self) -> &'a mut W { + self.variant(CNTSEL_A::BOUNDARY) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 6)) | ((value as u32 & 0x03) << 6); + self.w + } +} +#[doc = "Field `OVFEO` reader - Overflow/Underflow Output Event Enable"] +pub struct OVFEO_R(crate::FieldReader); +impl OVFEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVFEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVFEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVFEO` writer - Overflow/Underflow Output Event Enable"] +pub struct OVFEO_W<'a> { + w: &'a mut W, +} +impl<'a> OVFEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `TRGEO` reader - Retrigger Output Event Enable"] +pub struct TRGEO_R(crate::FieldReader); +impl TRGEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRGEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRGEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRGEO` writer - Retrigger Output Event Enable"] +pub struct TRGEO_W<'a> { + w: &'a mut W, +} +impl<'a> TRGEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `CNTEO` reader - Timer/counter Output Event Enable"] +pub struct CNTEO_R(crate::FieldReader); +impl CNTEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CNTEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CNTEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CNTEO` writer - Timer/counter Output Event Enable"] +pub struct CNTEO_W<'a> { + w: &'a mut W, +} +impl<'a> CNTEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `TCINV0` reader - Inverted Event 0 Input Enable"] +pub struct TCINV0_R(crate::FieldReader); +impl TCINV0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCINV0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCINV0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCINV0` writer - Inverted Event 0 Input Enable"] +pub struct TCINV0_W<'a> { + w: &'a mut W, +} +impl<'a> TCINV0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `TCINV1` reader - Inverted Event 1 Input Enable"] +pub struct TCINV1_R(crate::FieldReader); +impl TCINV1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCINV1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCINV1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCINV1` writer - Inverted Event 1 Input Enable"] +pub struct TCINV1_W<'a> { + w: &'a mut W, +} +impl<'a> TCINV1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `TCEI0` reader - Timer/counter Event 0 Input Enable"] +pub struct TCEI0_R(crate::FieldReader); +impl TCEI0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCEI0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCEI0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCEI0` writer - Timer/counter Event 0 Input Enable"] +pub struct TCEI0_W<'a> { + w: &'a mut W, +} +impl<'a> TCEI0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `TCEI1` reader - Timer/counter Event 1 Input Enable"] +pub struct TCEI1_R(crate::FieldReader); +impl TCEI1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCEI1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCEI1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCEI1` writer - Timer/counter Event 1 Input Enable"] +pub struct TCEI1_W<'a> { + w: &'a mut W, +} +impl<'a> TCEI1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `MCEI0` reader - Match or Capture Channel 0 Event Input Enable"] +pub struct MCEI0_R(crate::FieldReader); +impl MCEI0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEI0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEI0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEI0` writer - Match or Capture Channel 0 Event Input Enable"] +pub struct MCEI0_W<'a> { + w: &'a mut W, +} +impl<'a> MCEI0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `MCEI1` reader - Match or Capture Channel 1 Event Input Enable"] +pub struct MCEI1_R(crate::FieldReader); +impl MCEI1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEI1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEI1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEI1` writer - Match or Capture Channel 1 Event Input Enable"] +pub struct MCEI1_W<'a> { + w: &'a mut W, +} +impl<'a> MCEI1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `MCEI2` reader - Match or Capture Channel 2 Event Input Enable"] +pub struct MCEI2_R(crate::FieldReader); +impl MCEI2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEI2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEI2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEI2` writer - Match or Capture Channel 2 Event Input Enable"] +pub struct MCEI2_W<'a> { + w: &'a mut W, +} +impl<'a> MCEI2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `MCEI3` reader - Match or Capture Channel 3 Event Input Enable"] +pub struct MCEI3_R(crate::FieldReader); +impl MCEI3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEI3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEI3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEI3` writer - Match or Capture Channel 3 Event Input Enable"] +pub struct MCEI3_W<'a> { + w: &'a mut W, +} +impl<'a> MCEI3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `MCEO0` reader - Match or Capture Channel 0 Event Output Enable"] +pub struct MCEO0_R(crate::FieldReader); +impl MCEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO0` writer - Match or Capture Channel 0 Event Output Enable"] +pub struct MCEO0_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `MCEO1` reader - Match or Capture Channel 1 Event Output Enable"] +pub struct MCEO1_R(crate::FieldReader); +impl MCEO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO1` writer - Match or Capture Channel 1 Event Output Enable"] +pub struct MCEO1_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `MCEO2` reader - Match or Capture Channel 2 Event Output Enable"] +pub struct MCEO2_R(crate::FieldReader); +impl MCEO2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO2` writer - Match or Capture Channel 2 Event Output Enable"] +pub struct MCEO2_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `MCEO3` reader - Match or Capture Channel 3 Event Output Enable"] +pub struct MCEO3_R(crate::FieldReader); +impl MCEO3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO3` writer - Match or Capture Channel 3 Event Output Enable"] +pub struct MCEO3_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Timer/counter Input Event0 Action"] + #[inline(always)] + pub fn evact0(&self) -> EVACT0_R { + EVACT0_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bits 3:5 - Timer/counter Input Event1 Action"] + #[inline(always)] + pub fn evact1(&self) -> EVACT1_R { + EVACT1_R::new(((self.bits >> 3) & 0x07) as u8) + } + #[doc = "Bits 6:7 - Timer/counter Output Event Mode"] + #[inline(always)] + pub fn cntsel(&self) -> CNTSEL_R { + CNTSEL_R::new(((self.bits >> 6) & 0x03) as u8) + } + #[doc = "Bit 8 - Overflow/Underflow Output Event Enable"] + #[inline(always)] + pub fn ovfeo(&self) -> OVFEO_R { + OVFEO_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Retrigger Output Event Enable"] + #[inline(always)] + pub fn trgeo(&self) -> TRGEO_R { + TRGEO_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Timer/counter Output Event Enable"] + #[inline(always)] + pub fn cnteo(&self) -> CNTEO_R { + CNTEO_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 12 - Inverted Event 0 Input Enable"] + #[inline(always)] + pub fn tcinv0(&self) -> TCINV0_R { + TCINV0_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Inverted Event 1 Input Enable"] + #[inline(always)] + pub fn tcinv1(&self) -> TCINV1_R { + TCINV1_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Timer/counter Event 0 Input Enable"] + #[inline(always)] + pub fn tcei0(&self) -> TCEI0_R { + TCEI0_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Timer/counter Event 1 Input Enable"] + #[inline(always)] + pub fn tcei1(&self) -> TCEI1_R { + TCEI1_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Match or Capture Channel 0 Event Input Enable"] + #[inline(always)] + pub fn mcei0(&self) -> MCEI0_R { + MCEI0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Match or Capture Channel 1 Event Input Enable"] + #[inline(always)] + pub fn mcei1(&self) -> MCEI1_R { + MCEI1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Match or Capture Channel 2 Event Input Enable"] + #[inline(always)] + pub fn mcei2(&self) -> MCEI2_R { + MCEI2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Match or Capture Channel 3 Event Input Enable"] + #[inline(always)] + pub fn mcei3(&self) -> MCEI3_R { + MCEI3_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 24 - Match or Capture Channel 0 Event Output Enable"] + #[inline(always)] + pub fn mceo0(&self) -> MCEO0_R { + MCEO0_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Match or Capture Channel 1 Event Output Enable"] + #[inline(always)] + pub fn mceo1(&self) -> MCEO1_R { + MCEO1_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Match or Capture Channel 2 Event Output Enable"] + #[inline(always)] + pub fn mceo2(&self) -> MCEO2_R { + MCEO2_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Match or Capture Channel 3 Event Output Enable"] + #[inline(always)] + pub fn mceo3(&self) -> MCEO3_R { + MCEO3_R::new(((self.bits >> 27) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Timer/counter Input Event0 Action"] + #[inline(always)] + pub fn evact0(&mut self) -> EVACT0_W { + EVACT0_W { w: self } + } + #[doc = "Bits 3:5 - Timer/counter Input Event1 Action"] + #[inline(always)] + pub fn evact1(&mut self) -> EVACT1_W { + EVACT1_W { w: self } + } + #[doc = "Bits 6:7 - Timer/counter Output Event Mode"] + #[inline(always)] + pub fn cntsel(&mut self) -> CNTSEL_W { + CNTSEL_W { w: self } + } + #[doc = "Bit 8 - Overflow/Underflow Output Event Enable"] + #[inline(always)] + pub fn ovfeo(&mut self) -> OVFEO_W { + OVFEO_W { w: self } + } + #[doc = "Bit 9 - Retrigger Output Event Enable"] + #[inline(always)] + pub fn trgeo(&mut self) -> TRGEO_W { + TRGEO_W { w: self } + } + #[doc = "Bit 10 - Timer/counter Output Event Enable"] + #[inline(always)] + pub fn cnteo(&mut self) -> CNTEO_W { + CNTEO_W { w: self } + } + #[doc = "Bit 12 - Inverted Event 0 Input Enable"] + #[inline(always)] + pub fn tcinv0(&mut self) -> TCINV0_W { + TCINV0_W { w: self } + } + #[doc = "Bit 13 - Inverted Event 1 Input Enable"] + #[inline(always)] + pub fn tcinv1(&mut self) -> TCINV1_W { + TCINV1_W { w: self } + } + #[doc = "Bit 14 - Timer/counter Event 0 Input Enable"] + #[inline(always)] + pub fn tcei0(&mut self) -> TCEI0_W { + TCEI0_W { w: self } + } + #[doc = "Bit 15 - Timer/counter Event 1 Input Enable"] + #[inline(always)] + pub fn tcei1(&mut self) -> TCEI1_W { + TCEI1_W { w: self } + } + #[doc = "Bit 16 - Match or Capture Channel 0 Event Input Enable"] + #[inline(always)] + pub fn mcei0(&mut self) -> MCEI0_W { + MCEI0_W { w: self } + } + #[doc = "Bit 17 - Match or Capture Channel 1 Event Input Enable"] + #[inline(always)] + pub fn mcei1(&mut self) -> MCEI1_W { + MCEI1_W { w: self } + } + #[doc = "Bit 18 - Match or Capture Channel 2 Event Input Enable"] + #[inline(always)] + pub fn mcei2(&mut self) -> MCEI2_W { + MCEI2_W { w: self } + } + #[doc = "Bit 19 - Match or Capture Channel 3 Event Input Enable"] + #[inline(always)] + pub fn mcei3(&mut self) -> MCEI3_W { + MCEI3_W { w: self } + } + #[doc = "Bit 24 - Match or Capture Channel 0 Event Output Enable"] + #[inline(always)] + pub fn mceo0(&mut self) -> MCEO0_W { + MCEO0_W { w: self } + } + #[doc = "Bit 25 - Match or Capture Channel 1 Event Output Enable"] + #[inline(always)] + pub fn mceo1(&mut self) -> MCEO1_W { + MCEO1_W { w: self } + } + #[doc = "Bit 26 - Match or Capture Channel 2 Event Output Enable"] + #[inline(always)] + pub fn mceo2(&mut self) -> MCEO2_W { + MCEO2_W { w: self } + } + #[doc = "Bit 27 - Match or Capture Channel 3 Event Output Enable"] + #[inline(always)] + pub fn mceo3(&mut self) -> MCEO3_W { + MCEO3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/tcc0/fctrla.rs b/pac/atsamc20n/src/tcc0/fctrla.rs new file mode 100644 index 000000000000..77c7276fee23 --- /dev/null +++ b/pac/atsamc20n/src/tcc0/fctrla.rs @@ -0,0 +1,940 @@ +#[doc = "Register `FCTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FCTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Fault A Source\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SRC_A { + #[doc = "0: Fault input disabled"] + DISABLE = 0, + #[doc = "1: MCEx (x=0,1) event input"] + ENABLE = 1, + #[doc = "2: Inverted MCEx (x=0,1) event input"] + INVERT = 2, + #[doc = "3: Alternate fault (A or B) state at the end of the previous period"] + ALTFAULT = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SRC_A) -> Self { + variant as _ + } +} +#[doc = "Field `SRC` reader - Fault A Source"] +pub struct SRC_R(crate::FieldReader); +impl SRC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SRC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SRC_A { + match self.bits { + 0 => SRC_A::DISABLE, + 1 => SRC_A::ENABLE, + 2 => SRC_A::INVERT, + 3 => SRC_A::ALTFAULT, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == SRC_A::DISABLE + } + #[doc = "Checks if the value of the field is `ENABLE`"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + **self == SRC_A::ENABLE + } + #[doc = "Checks if the value of the field is `INVERT`"] + #[inline(always)] + pub fn is_invert(&self) -> bool { + **self == SRC_A::INVERT + } + #[doc = "Checks if the value of the field is `ALTFAULT`"] + #[inline(always)] + pub fn is_altfault(&self) -> bool { + **self == SRC_A::ALTFAULT + } +} +impl core::ops::Deref for SRC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SRC` writer - Fault A Source"] +pub struct SRC_W<'a> { + w: &'a mut W, +} +impl<'a> SRC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SRC_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Fault input disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(SRC_A::DISABLE) + } + #[doc = "MCEx (x=0,1) event input"] + #[inline(always)] + pub fn enable(self) -> &'a mut W { + self.variant(SRC_A::ENABLE) + } + #[doc = "Inverted MCEx (x=0,1) event input"] + #[inline(always)] + pub fn invert(self) -> &'a mut W { + self.variant(SRC_A::INVERT) + } + #[doc = "Alternate fault (A or B) state at the end of the previous period"] + #[inline(always)] + pub fn altfault(self) -> &'a mut W { + self.variant(SRC_A::ALTFAULT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u32 & 0x03); + self.w + } +} +#[doc = "Field `KEEP` reader - Fault A Keeper"] +pub struct KEEP_R(crate::FieldReader); +impl KEEP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + KEEP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for KEEP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `KEEP` writer - Fault A Keeper"] +pub struct KEEP_W<'a> { + w: &'a mut W, +} +impl<'a> KEEP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `QUAL` reader - Fault A Qualification"] +pub struct QUAL_R(crate::FieldReader); +impl QUAL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + QUAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for QUAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `QUAL` writer - Fault A Qualification"] +pub struct QUAL_W<'a> { + w: &'a mut W, +} +impl<'a> QUAL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Fault A Blanking Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum BLANK_A { + #[doc = "0: Blanking applied from start of the ramp"] + START = 0, + #[doc = "1: Blanking applied from rising edge of the output waveform"] + RISE = 1, + #[doc = "2: Blanking applied from falling edge of the output waveform"] + FALL = 2, + #[doc = "3: Blanking applied from each toggle of the output waveform"] + BOTH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: BLANK_A) -> Self { + variant as _ + } +} +#[doc = "Field `BLANK` reader - Fault A Blanking Mode"] +pub struct BLANK_R(crate::FieldReader); +impl BLANK_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BLANK_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> BLANK_A { + match self.bits { + 0 => BLANK_A::START, + 1 => BLANK_A::RISE, + 2 => BLANK_A::FALL, + 3 => BLANK_A::BOTH, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `START`"] + #[inline(always)] + pub fn is_start(&self) -> bool { + **self == BLANK_A::START + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == BLANK_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == BLANK_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == BLANK_A::BOTH + } +} +impl core::ops::Deref for BLANK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BLANK` writer - Fault A Blanking Mode"] +pub struct BLANK_W<'a> { + w: &'a mut W, +} +impl<'a> BLANK_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: BLANK_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Blanking applied from start of the ramp"] + #[inline(always)] + pub fn start(self) -> &'a mut W { + self.variant(BLANK_A::START) + } + #[doc = "Blanking applied from rising edge of the output waveform"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(BLANK_A::RISE) + } + #[doc = "Blanking applied from falling edge of the output waveform"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(BLANK_A::FALL) + } + #[doc = "Blanking applied from each toggle of the output waveform"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(BLANK_A::BOTH) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 5)) | ((value as u32 & 0x03) << 5); + self.w + } +} +#[doc = "Field `RESTART` reader - Fault A Restart"] +pub struct RESTART_R(crate::FieldReader); +impl RESTART_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESTART_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESTART_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESTART` writer - Fault A Restart"] +pub struct RESTART_W<'a> { + w: &'a mut W, +} +impl<'a> RESTART_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Fault A Halt Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum HALT_A { + #[doc = "0: Halt action disabled"] + DISABLE = 0, + #[doc = "1: Hardware halt action"] + HW = 1, + #[doc = "2: Software halt action"] + SW = 2, + #[doc = "3: Non-recoverable fault"] + NR = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: HALT_A) -> Self { + variant as _ + } +} +#[doc = "Field `HALT` reader - Fault A Halt Mode"] +pub struct HALT_R(crate::FieldReader); +impl HALT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + HALT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> HALT_A { + match self.bits { + 0 => HALT_A::DISABLE, + 1 => HALT_A::HW, + 2 => HALT_A::SW, + 3 => HALT_A::NR, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == HALT_A::DISABLE + } + #[doc = "Checks if the value of the field is `HW`"] + #[inline(always)] + pub fn is_hw(&self) -> bool { + **self == HALT_A::HW + } + #[doc = "Checks if the value of the field is `SW`"] + #[inline(always)] + pub fn is_sw(&self) -> bool { + **self == HALT_A::SW + } + #[doc = "Checks if the value of the field is `NR`"] + #[inline(always)] + pub fn is_nr(&self) -> bool { + **self == HALT_A::NR + } +} +impl core::ops::Deref for HALT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HALT` writer - Fault A Halt Mode"] +pub struct HALT_W<'a> { + w: &'a mut W, +} +impl<'a> HALT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: HALT_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Halt action disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(HALT_A::DISABLE) + } + #[doc = "Hardware halt action"] + #[inline(always)] + pub fn hw(self) -> &'a mut W { + self.variant(HALT_A::HW) + } + #[doc = "Software halt action"] + #[inline(always)] + pub fn sw(self) -> &'a mut W { + self.variant(HALT_A::SW) + } + #[doc = "Non-recoverable fault"] + #[inline(always)] + pub fn nr(self) -> &'a mut W { + self.variant(HALT_A::NR) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 8)) | ((value as u32 & 0x03) << 8); + self.w + } +} +#[doc = "Fault A Capture Channel\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CHSEL_A { + #[doc = "0: Capture value stored in channel 0"] + CC0 = 0, + #[doc = "1: Capture value stored in channel 1"] + CC1 = 1, + #[doc = "2: Capture value stored in channel 2"] + CC2 = 2, + #[doc = "3: Capture value stored in channel 3"] + CC3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CHSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `CHSEL` reader - Fault A Capture Channel"] +pub struct CHSEL_R(crate::FieldReader); +impl CHSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CHSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CHSEL_A { + match self.bits { + 0 => CHSEL_A::CC0, + 1 => CHSEL_A::CC1, + 2 => CHSEL_A::CC2, + 3 => CHSEL_A::CC3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `CC0`"] + #[inline(always)] + pub fn is_cc0(&self) -> bool { + **self == CHSEL_A::CC0 + } + #[doc = "Checks if the value of the field is `CC1`"] + #[inline(always)] + pub fn is_cc1(&self) -> bool { + **self == CHSEL_A::CC1 + } + #[doc = "Checks if the value of the field is `CC2`"] + #[inline(always)] + pub fn is_cc2(&self) -> bool { + **self == CHSEL_A::CC2 + } + #[doc = "Checks if the value of the field is `CC3`"] + #[inline(always)] + pub fn is_cc3(&self) -> bool { + **self == CHSEL_A::CC3 + } +} +impl core::ops::Deref for CHSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHSEL` writer - Fault A Capture Channel"] +pub struct CHSEL_W<'a> { + w: &'a mut W, +} +impl<'a> CHSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CHSEL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Capture value stored in channel 0"] + #[inline(always)] + pub fn cc0(self) -> &'a mut W { + self.variant(CHSEL_A::CC0) + } + #[doc = "Capture value stored in channel 1"] + #[inline(always)] + pub fn cc1(self) -> &'a mut W { + self.variant(CHSEL_A::CC1) + } + #[doc = "Capture value stored in channel 2"] + #[inline(always)] + pub fn cc2(self) -> &'a mut W { + self.variant(CHSEL_A::CC2) + } + #[doc = "Capture value stored in channel 3"] + #[inline(always)] + pub fn cc3(self) -> &'a mut W { + self.variant(CHSEL_A::CC3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 10)) | ((value as u32 & 0x03) << 10); + self.w + } +} +#[doc = "Fault A Capture Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CAPTURE_A { + #[doc = "0: No capture"] + DISABLE = 0, + #[doc = "1: Capture on fault"] + CAPT = 1, + #[doc = "2: Minimum capture"] + CAPTMIN = 2, + #[doc = "3: Maximum capture"] + CAPTMAX = 3, + #[doc = "4: Minimum local detection"] + LOCMIN = 4, + #[doc = "5: Maximum local detection"] + LOCMAX = 5, + #[doc = "6: Minimum and maximum local detection"] + DERIV0 = 6, + #[doc = "7: Capture with ramp index as MSB value"] + CAPTMARK = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CAPTURE_A) -> Self { + variant as _ + } +} +#[doc = "Field `CAPTURE` reader - Fault A Capture Action"] +pub struct CAPTURE_R(crate::FieldReader); +impl CAPTURE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CAPTURE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CAPTURE_A { + match self.bits { + 0 => CAPTURE_A::DISABLE, + 1 => CAPTURE_A::CAPT, + 2 => CAPTURE_A::CAPTMIN, + 3 => CAPTURE_A::CAPTMAX, + 4 => CAPTURE_A::LOCMIN, + 5 => CAPTURE_A::LOCMAX, + 6 => CAPTURE_A::DERIV0, + 7 => CAPTURE_A::CAPTMARK, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == CAPTURE_A::DISABLE + } + #[doc = "Checks if the value of the field is `CAPT`"] + #[inline(always)] + pub fn is_capt(&self) -> bool { + **self == CAPTURE_A::CAPT + } + #[doc = "Checks if the value of the field is `CAPTMIN`"] + #[inline(always)] + pub fn is_captmin(&self) -> bool { + **self == CAPTURE_A::CAPTMIN + } + #[doc = "Checks if the value of the field is `CAPTMAX`"] + #[inline(always)] + pub fn is_captmax(&self) -> bool { + **self == CAPTURE_A::CAPTMAX + } + #[doc = "Checks if the value of the field is `LOCMIN`"] + #[inline(always)] + pub fn is_locmin(&self) -> bool { + **self == CAPTURE_A::LOCMIN + } + #[doc = "Checks if the value of the field is `LOCMAX`"] + #[inline(always)] + pub fn is_locmax(&self) -> bool { + **self == CAPTURE_A::LOCMAX + } + #[doc = "Checks if the value of the field is `DERIV0`"] + #[inline(always)] + pub fn is_deriv0(&self) -> bool { + **self == CAPTURE_A::DERIV0 + } + #[doc = "Checks if the value of the field is `CAPTMARK`"] + #[inline(always)] + pub fn is_captmark(&self) -> bool { + **self == CAPTURE_A::CAPTMARK + } +} +impl core::ops::Deref for CAPTURE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAPTURE` writer - Fault A Capture Action"] +pub struct CAPTURE_W<'a> { + w: &'a mut W, +} +impl<'a> CAPTURE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CAPTURE_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "No capture"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(CAPTURE_A::DISABLE) + } + #[doc = "Capture on fault"] + #[inline(always)] + pub fn capt(self) -> &'a mut W { + self.variant(CAPTURE_A::CAPT) + } + #[doc = "Minimum capture"] + #[inline(always)] + pub fn captmin(self) -> &'a mut W { + self.variant(CAPTURE_A::CAPTMIN) + } + #[doc = "Maximum capture"] + #[inline(always)] + pub fn captmax(self) -> &'a mut W { + self.variant(CAPTURE_A::CAPTMAX) + } + #[doc = "Minimum local detection"] + #[inline(always)] + pub fn locmin(self) -> &'a mut W { + self.variant(CAPTURE_A::LOCMIN) + } + #[doc = "Maximum local detection"] + #[inline(always)] + pub fn locmax(self) -> &'a mut W { + self.variant(CAPTURE_A::LOCMAX) + } + #[doc = "Minimum and maximum local detection"] + #[inline(always)] + pub fn deriv0(self) -> &'a mut W { + self.variant(CAPTURE_A::DERIV0) + } + #[doc = "Capture with ramp index as MSB value"] + #[inline(always)] + pub fn captmark(self) -> &'a mut W { + self.variant(CAPTURE_A::CAPTMARK) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 12)) | ((value as u32 & 0x07) << 12); + self.w + } +} +#[doc = "Field `BLANKPRESC` reader - Fault A Blanking Prescaler"] +pub struct BLANKPRESC_R(crate::FieldReader); +impl BLANKPRESC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BLANKPRESC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BLANKPRESC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BLANKPRESC` writer - Fault A Blanking Prescaler"] +pub struct BLANKPRESC_W<'a> { + w: &'a mut W, +} +impl<'a> BLANKPRESC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `BLANKVAL` reader - Fault A Blanking Time"] +pub struct BLANKVAL_R(crate::FieldReader); +impl BLANKVAL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BLANKVAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BLANKVAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BLANKVAL` writer - Fault A Blanking Time"] +pub struct BLANKVAL_W<'a> { + w: &'a mut W, +} +impl<'a> BLANKVAL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +#[doc = "Field `FILTERVAL` reader - Fault A Filter Value"] +pub struct FILTERVAL_R(crate::FieldReader); +impl FILTERVAL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FILTERVAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTERVAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTERVAL` writer - Fault A Filter Value"] +pub struct FILTERVAL_W<'a> { + w: &'a mut W, +} +impl<'a> FILTERVAL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Fault A Source"] + #[inline(always)] + pub fn src(&self) -> SRC_R { + SRC_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bit 3 - Fault A Keeper"] + #[inline(always)] + pub fn keep(&self) -> KEEP_R { + KEEP_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Fault A Qualification"] + #[inline(always)] + pub fn qual(&self) -> QUAL_R { + QUAL_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bits 5:6 - Fault A Blanking Mode"] + #[inline(always)] + pub fn blank(&self) -> BLANK_R { + BLANK_R::new(((self.bits >> 5) & 0x03) as u8) + } + #[doc = "Bit 7 - Fault A Restart"] + #[inline(always)] + pub fn restart(&self) -> RESTART_R { + RESTART_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:9 - Fault A Halt Mode"] + #[inline(always)] + pub fn halt(&self) -> HALT_R { + HALT_R::new(((self.bits >> 8) & 0x03) as u8) + } + #[doc = "Bits 10:11 - Fault A Capture Channel"] + #[inline(always)] + pub fn chsel(&self) -> CHSEL_R { + CHSEL_R::new(((self.bits >> 10) & 0x03) as u8) + } + #[doc = "Bits 12:14 - Fault A Capture Action"] + #[inline(always)] + pub fn capture(&self) -> CAPTURE_R { + CAPTURE_R::new(((self.bits >> 12) & 0x07) as u8) + } + #[doc = "Bit 15 - Fault A Blanking Prescaler"] + #[inline(always)] + pub fn blankpresc(&self) -> BLANKPRESC_R { + BLANKPRESC_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:23 - Fault A Blanking Time"] + #[inline(always)] + pub fn blankval(&self) -> BLANKVAL_R { + BLANKVAL_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:27 - Fault A Filter Value"] + #[inline(always)] + pub fn filterval(&self) -> FILTERVAL_R { + FILTERVAL_R::new(((self.bits >> 24) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Fault A Source"] + #[inline(always)] + pub fn src(&mut self) -> SRC_W { + SRC_W { w: self } + } + #[doc = "Bit 3 - Fault A Keeper"] + #[inline(always)] + pub fn keep(&mut self) -> KEEP_W { + KEEP_W { w: self } + } + #[doc = "Bit 4 - Fault A Qualification"] + #[inline(always)] + pub fn qual(&mut self) -> QUAL_W { + QUAL_W { w: self } + } + #[doc = "Bits 5:6 - Fault A Blanking Mode"] + #[inline(always)] + pub fn blank(&mut self) -> BLANK_W { + BLANK_W { w: self } + } + #[doc = "Bit 7 - Fault A Restart"] + #[inline(always)] + pub fn restart(&mut self) -> RESTART_W { + RESTART_W { w: self } + } + #[doc = "Bits 8:9 - Fault A Halt Mode"] + #[inline(always)] + pub fn halt(&mut self) -> HALT_W { + HALT_W { w: self } + } + #[doc = "Bits 10:11 - Fault A Capture Channel"] + #[inline(always)] + pub fn chsel(&mut self) -> CHSEL_W { + CHSEL_W { w: self } + } + #[doc = "Bits 12:14 - Fault A Capture Action"] + #[inline(always)] + pub fn capture(&mut self) -> CAPTURE_W { + CAPTURE_W { w: self } + } + #[doc = "Bit 15 - Fault A Blanking Prescaler"] + #[inline(always)] + pub fn blankpresc(&mut self) -> BLANKPRESC_W { + BLANKPRESC_W { w: self } + } + #[doc = "Bits 16:23 - Fault A Blanking Time"] + #[inline(always)] + pub fn blankval(&mut self) -> BLANKVAL_W { + BLANKVAL_W { w: self } + } + #[doc = "Bits 24:27 - Fault A Filter Value"] + #[inline(always)] + pub fn filterval(&mut self) -> FILTERVAL_W { + FILTERVAL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Recoverable Fault A Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fctrla](index.html) module"] +pub struct FCTRLA_SPEC; +impl crate::RegisterSpec for FCTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [fctrla::R](R) reader structure"] +impl crate::Readable for FCTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [fctrla::W](W) writer structure"] +impl crate::Writable for FCTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets FCTRLA to value 0"] +impl crate::Resettable for FCTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/tcc0/fctrlb.rs b/pac/atsamc20n/src/tcc0/fctrlb.rs new file mode 100644 index 000000000000..4c1dfd1af93d --- /dev/null +++ b/pac/atsamc20n/src/tcc0/fctrlb.rs @@ -0,0 +1,940 @@ +#[doc = "Register `FCTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FCTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Fault B Source\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SRC_A { + #[doc = "0: Fault input disabled"] + DISABLE = 0, + #[doc = "1: MCEx (x=0,1) event input"] + ENABLE = 1, + #[doc = "2: Inverted MCEx (x=0,1) event input"] + INVERT = 2, + #[doc = "3: Alternate fault (A or B) state at the end of the previous period"] + ALTFAULT = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SRC_A) -> Self { + variant as _ + } +} +#[doc = "Field `SRC` reader - Fault B Source"] +pub struct SRC_R(crate::FieldReader); +impl SRC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SRC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SRC_A { + match self.bits { + 0 => SRC_A::DISABLE, + 1 => SRC_A::ENABLE, + 2 => SRC_A::INVERT, + 3 => SRC_A::ALTFAULT, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == SRC_A::DISABLE + } + #[doc = "Checks if the value of the field is `ENABLE`"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + **self == SRC_A::ENABLE + } + #[doc = "Checks if the value of the field is `INVERT`"] + #[inline(always)] + pub fn is_invert(&self) -> bool { + **self == SRC_A::INVERT + } + #[doc = "Checks if the value of the field is `ALTFAULT`"] + #[inline(always)] + pub fn is_altfault(&self) -> bool { + **self == SRC_A::ALTFAULT + } +} +impl core::ops::Deref for SRC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SRC` writer - Fault B Source"] +pub struct SRC_W<'a> { + w: &'a mut W, +} +impl<'a> SRC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SRC_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Fault input disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(SRC_A::DISABLE) + } + #[doc = "MCEx (x=0,1) event input"] + #[inline(always)] + pub fn enable(self) -> &'a mut W { + self.variant(SRC_A::ENABLE) + } + #[doc = "Inverted MCEx (x=0,1) event input"] + #[inline(always)] + pub fn invert(self) -> &'a mut W { + self.variant(SRC_A::INVERT) + } + #[doc = "Alternate fault (A or B) state at the end of the previous period"] + #[inline(always)] + pub fn altfault(self) -> &'a mut W { + self.variant(SRC_A::ALTFAULT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u32 & 0x03); + self.w + } +} +#[doc = "Field `KEEP` reader - Fault B Keeper"] +pub struct KEEP_R(crate::FieldReader); +impl KEEP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + KEEP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for KEEP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `KEEP` writer - Fault B Keeper"] +pub struct KEEP_W<'a> { + w: &'a mut W, +} +impl<'a> KEEP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `QUAL` reader - Fault B Qualification"] +pub struct QUAL_R(crate::FieldReader); +impl QUAL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + QUAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for QUAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `QUAL` writer - Fault B Qualification"] +pub struct QUAL_W<'a> { + w: &'a mut W, +} +impl<'a> QUAL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Fault B Blanking Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum BLANK_A { + #[doc = "0: Blanking applied from start of the ramp"] + START = 0, + #[doc = "1: Blanking applied from rising edge of the output waveform"] + RISE = 1, + #[doc = "2: Blanking applied from falling edge of the output waveform"] + FALL = 2, + #[doc = "3: Blanking applied from each toggle of the output waveform"] + BOTH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: BLANK_A) -> Self { + variant as _ + } +} +#[doc = "Field `BLANK` reader - Fault B Blanking Mode"] +pub struct BLANK_R(crate::FieldReader); +impl BLANK_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BLANK_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> BLANK_A { + match self.bits { + 0 => BLANK_A::START, + 1 => BLANK_A::RISE, + 2 => BLANK_A::FALL, + 3 => BLANK_A::BOTH, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `START`"] + #[inline(always)] + pub fn is_start(&self) -> bool { + **self == BLANK_A::START + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == BLANK_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == BLANK_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == BLANK_A::BOTH + } +} +impl core::ops::Deref for BLANK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BLANK` writer - Fault B Blanking Mode"] +pub struct BLANK_W<'a> { + w: &'a mut W, +} +impl<'a> BLANK_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: BLANK_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Blanking applied from start of the ramp"] + #[inline(always)] + pub fn start(self) -> &'a mut W { + self.variant(BLANK_A::START) + } + #[doc = "Blanking applied from rising edge of the output waveform"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(BLANK_A::RISE) + } + #[doc = "Blanking applied from falling edge of the output waveform"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(BLANK_A::FALL) + } + #[doc = "Blanking applied from each toggle of the output waveform"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(BLANK_A::BOTH) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 5)) | ((value as u32 & 0x03) << 5); + self.w + } +} +#[doc = "Field `RESTART` reader - Fault B Restart"] +pub struct RESTART_R(crate::FieldReader); +impl RESTART_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESTART_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESTART_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESTART` writer - Fault B Restart"] +pub struct RESTART_W<'a> { + w: &'a mut W, +} +impl<'a> RESTART_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Fault B Halt Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum HALT_A { + #[doc = "0: Halt action disabled"] + DISABLE = 0, + #[doc = "1: Hardware halt action"] + HW = 1, + #[doc = "2: Software halt action"] + SW = 2, + #[doc = "3: Non-recoverable fault"] + NR = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: HALT_A) -> Self { + variant as _ + } +} +#[doc = "Field `HALT` reader - Fault B Halt Mode"] +pub struct HALT_R(crate::FieldReader); +impl HALT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + HALT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> HALT_A { + match self.bits { + 0 => HALT_A::DISABLE, + 1 => HALT_A::HW, + 2 => HALT_A::SW, + 3 => HALT_A::NR, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == HALT_A::DISABLE + } + #[doc = "Checks if the value of the field is `HW`"] + #[inline(always)] + pub fn is_hw(&self) -> bool { + **self == HALT_A::HW + } + #[doc = "Checks if the value of the field is `SW`"] + #[inline(always)] + pub fn is_sw(&self) -> bool { + **self == HALT_A::SW + } + #[doc = "Checks if the value of the field is `NR`"] + #[inline(always)] + pub fn is_nr(&self) -> bool { + **self == HALT_A::NR + } +} +impl core::ops::Deref for HALT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HALT` writer - Fault B Halt Mode"] +pub struct HALT_W<'a> { + w: &'a mut W, +} +impl<'a> HALT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: HALT_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Halt action disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(HALT_A::DISABLE) + } + #[doc = "Hardware halt action"] + #[inline(always)] + pub fn hw(self) -> &'a mut W { + self.variant(HALT_A::HW) + } + #[doc = "Software halt action"] + #[inline(always)] + pub fn sw(self) -> &'a mut W { + self.variant(HALT_A::SW) + } + #[doc = "Non-recoverable fault"] + #[inline(always)] + pub fn nr(self) -> &'a mut W { + self.variant(HALT_A::NR) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 8)) | ((value as u32 & 0x03) << 8); + self.w + } +} +#[doc = "Fault B Capture Channel\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CHSEL_A { + #[doc = "0: Capture value stored in channel 0"] + CC0 = 0, + #[doc = "1: Capture value stored in channel 1"] + CC1 = 1, + #[doc = "2: Capture value stored in channel 2"] + CC2 = 2, + #[doc = "3: Capture value stored in channel 3"] + CC3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CHSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `CHSEL` reader - Fault B Capture Channel"] +pub struct CHSEL_R(crate::FieldReader); +impl CHSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CHSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CHSEL_A { + match self.bits { + 0 => CHSEL_A::CC0, + 1 => CHSEL_A::CC1, + 2 => CHSEL_A::CC2, + 3 => CHSEL_A::CC3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `CC0`"] + #[inline(always)] + pub fn is_cc0(&self) -> bool { + **self == CHSEL_A::CC0 + } + #[doc = "Checks if the value of the field is `CC1`"] + #[inline(always)] + pub fn is_cc1(&self) -> bool { + **self == CHSEL_A::CC1 + } + #[doc = "Checks if the value of the field is `CC2`"] + #[inline(always)] + pub fn is_cc2(&self) -> bool { + **self == CHSEL_A::CC2 + } + #[doc = "Checks if the value of the field is `CC3`"] + #[inline(always)] + pub fn is_cc3(&self) -> bool { + **self == CHSEL_A::CC3 + } +} +impl core::ops::Deref for CHSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHSEL` writer - Fault B Capture Channel"] +pub struct CHSEL_W<'a> { + w: &'a mut W, +} +impl<'a> CHSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CHSEL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Capture value stored in channel 0"] + #[inline(always)] + pub fn cc0(self) -> &'a mut W { + self.variant(CHSEL_A::CC0) + } + #[doc = "Capture value stored in channel 1"] + #[inline(always)] + pub fn cc1(self) -> &'a mut W { + self.variant(CHSEL_A::CC1) + } + #[doc = "Capture value stored in channel 2"] + #[inline(always)] + pub fn cc2(self) -> &'a mut W { + self.variant(CHSEL_A::CC2) + } + #[doc = "Capture value stored in channel 3"] + #[inline(always)] + pub fn cc3(self) -> &'a mut W { + self.variant(CHSEL_A::CC3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 10)) | ((value as u32 & 0x03) << 10); + self.w + } +} +#[doc = "Fault B Capture Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CAPTURE_A { + #[doc = "0: No capture"] + DISABLE = 0, + #[doc = "1: Capture on fault"] + CAPT = 1, + #[doc = "2: Minimum capture"] + CAPTMIN = 2, + #[doc = "3: Maximum capture"] + CAPTMAX = 3, + #[doc = "4: Minimum local detection"] + LOCMIN = 4, + #[doc = "5: Maximum local detection"] + LOCMAX = 5, + #[doc = "6: Minimum and maximum local detection"] + DERIV0 = 6, + #[doc = "7: Capture with ramp index as MSB value"] + CAPTMARK = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CAPTURE_A) -> Self { + variant as _ + } +} +#[doc = "Field `CAPTURE` reader - Fault B Capture Action"] +pub struct CAPTURE_R(crate::FieldReader); +impl CAPTURE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CAPTURE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CAPTURE_A { + match self.bits { + 0 => CAPTURE_A::DISABLE, + 1 => CAPTURE_A::CAPT, + 2 => CAPTURE_A::CAPTMIN, + 3 => CAPTURE_A::CAPTMAX, + 4 => CAPTURE_A::LOCMIN, + 5 => CAPTURE_A::LOCMAX, + 6 => CAPTURE_A::DERIV0, + 7 => CAPTURE_A::CAPTMARK, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == CAPTURE_A::DISABLE + } + #[doc = "Checks if the value of the field is `CAPT`"] + #[inline(always)] + pub fn is_capt(&self) -> bool { + **self == CAPTURE_A::CAPT + } + #[doc = "Checks if the value of the field is `CAPTMIN`"] + #[inline(always)] + pub fn is_captmin(&self) -> bool { + **self == CAPTURE_A::CAPTMIN + } + #[doc = "Checks if the value of the field is `CAPTMAX`"] + #[inline(always)] + pub fn is_captmax(&self) -> bool { + **self == CAPTURE_A::CAPTMAX + } + #[doc = "Checks if the value of the field is `LOCMIN`"] + #[inline(always)] + pub fn is_locmin(&self) -> bool { + **self == CAPTURE_A::LOCMIN + } + #[doc = "Checks if the value of the field is `LOCMAX`"] + #[inline(always)] + pub fn is_locmax(&self) -> bool { + **self == CAPTURE_A::LOCMAX + } + #[doc = "Checks if the value of the field is `DERIV0`"] + #[inline(always)] + pub fn is_deriv0(&self) -> bool { + **self == CAPTURE_A::DERIV0 + } + #[doc = "Checks if the value of the field is `CAPTMARK`"] + #[inline(always)] + pub fn is_captmark(&self) -> bool { + **self == CAPTURE_A::CAPTMARK + } +} +impl core::ops::Deref for CAPTURE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAPTURE` writer - Fault B Capture Action"] +pub struct CAPTURE_W<'a> { + w: &'a mut W, +} +impl<'a> CAPTURE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CAPTURE_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "No capture"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(CAPTURE_A::DISABLE) + } + #[doc = "Capture on fault"] + #[inline(always)] + pub fn capt(self) -> &'a mut W { + self.variant(CAPTURE_A::CAPT) + } + #[doc = "Minimum capture"] + #[inline(always)] + pub fn captmin(self) -> &'a mut W { + self.variant(CAPTURE_A::CAPTMIN) + } + #[doc = "Maximum capture"] + #[inline(always)] + pub fn captmax(self) -> &'a mut W { + self.variant(CAPTURE_A::CAPTMAX) + } + #[doc = "Minimum local detection"] + #[inline(always)] + pub fn locmin(self) -> &'a mut W { + self.variant(CAPTURE_A::LOCMIN) + } + #[doc = "Maximum local detection"] + #[inline(always)] + pub fn locmax(self) -> &'a mut W { + self.variant(CAPTURE_A::LOCMAX) + } + #[doc = "Minimum and maximum local detection"] + #[inline(always)] + pub fn deriv0(self) -> &'a mut W { + self.variant(CAPTURE_A::DERIV0) + } + #[doc = "Capture with ramp index as MSB value"] + #[inline(always)] + pub fn captmark(self) -> &'a mut W { + self.variant(CAPTURE_A::CAPTMARK) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 12)) | ((value as u32 & 0x07) << 12); + self.w + } +} +#[doc = "Field `BLANKPRESC` reader - Fault B Blanking Prescaler"] +pub struct BLANKPRESC_R(crate::FieldReader); +impl BLANKPRESC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BLANKPRESC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BLANKPRESC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BLANKPRESC` writer - Fault B Blanking Prescaler"] +pub struct BLANKPRESC_W<'a> { + w: &'a mut W, +} +impl<'a> BLANKPRESC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `BLANKVAL` reader - Fault B Blanking Time"] +pub struct BLANKVAL_R(crate::FieldReader); +impl BLANKVAL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BLANKVAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BLANKVAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BLANKVAL` writer - Fault B Blanking Time"] +pub struct BLANKVAL_W<'a> { + w: &'a mut W, +} +impl<'a> BLANKVAL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +#[doc = "Field `FILTERVAL` reader - Fault B Filter Value"] +pub struct FILTERVAL_R(crate::FieldReader); +impl FILTERVAL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FILTERVAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTERVAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTERVAL` writer - Fault B Filter Value"] +pub struct FILTERVAL_W<'a> { + w: &'a mut W, +} +impl<'a> FILTERVAL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Fault B Source"] + #[inline(always)] + pub fn src(&self) -> SRC_R { + SRC_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bit 3 - Fault B Keeper"] + #[inline(always)] + pub fn keep(&self) -> KEEP_R { + KEEP_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Fault B Qualification"] + #[inline(always)] + pub fn qual(&self) -> QUAL_R { + QUAL_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bits 5:6 - Fault B Blanking Mode"] + #[inline(always)] + pub fn blank(&self) -> BLANK_R { + BLANK_R::new(((self.bits >> 5) & 0x03) as u8) + } + #[doc = "Bit 7 - Fault B Restart"] + #[inline(always)] + pub fn restart(&self) -> RESTART_R { + RESTART_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:9 - Fault B Halt Mode"] + #[inline(always)] + pub fn halt(&self) -> HALT_R { + HALT_R::new(((self.bits >> 8) & 0x03) as u8) + } + #[doc = "Bits 10:11 - Fault B Capture Channel"] + #[inline(always)] + pub fn chsel(&self) -> CHSEL_R { + CHSEL_R::new(((self.bits >> 10) & 0x03) as u8) + } + #[doc = "Bits 12:14 - Fault B Capture Action"] + #[inline(always)] + pub fn capture(&self) -> CAPTURE_R { + CAPTURE_R::new(((self.bits >> 12) & 0x07) as u8) + } + #[doc = "Bit 15 - Fault B Blanking Prescaler"] + #[inline(always)] + pub fn blankpresc(&self) -> BLANKPRESC_R { + BLANKPRESC_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:23 - Fault B Blanking Time"] + #[inline(always)] + pub fn blankval(&self) -> BLANKVAL_R { + BLANKVAL_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:27 - Fault B Filter Value"] + #[inline(always)] + pub fn filterval(&self) -> FILTERVAL_R { + FILTERVAL_R::new(((self.bits >> 24) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Fault B Source"] + #[inline(always)] + pub fn src(&mut self) -> SRC_W { + SRC_W { w: self } + } + #[doc = "Bit 3 - Fault B Keeper"] + #[inline(always)] + pub fn keep(&mut self) -> KEEP_W { + KEEP_W { w: self } + } + #[doc = "Bit 4 - Fault B Qualification"] + #[inline(always)] + pub fn qual(&mut self) -> QUAL_W { + QUAL_W { w: self } + } + #[doc = "Bits 5:6 - Fault B Blanking Mode"] + #[inline(always)] + pub fn blank(&mut self) -> BLANK_W { + BLANK_W { w: self } + } + #[doc = "Bit 7 - Fault B Restart"] + #[inline(always)] + pub fn restart(&mut self) -> RESTART_W { + RESTART_W { w: self } + } + #[doc = "Bits 8:9 - Fault B Halt Mode"] + #[inline(always)] + pub fn halt(&mut self) -> HALT_W { + HALT_W { w: self } + } + #[doc = "Bits 10:11 - Fault B Capture Channel"] + #[inline(always)] + pub fn chsel(&mut self) -> CHSEL_W { + CHSEL_W { w: self } + } + #[doc = "Bits 12:14 - Fault B Capture Action"] + #[inline(always)] + pub fn capture(&mut self) -> CAPTURE_W { + CAPTURE_W { w: self } + } + #[doc = "Bit 15 - Fault B Blanking Prescaler"] + #[inline(always)] + pub fn blankpresc(&mut self) -> BLANKPRESC_W { + BLANKPRESC_W { w: self } + } + #[doc = "Bits 16:23 - Fault B Blanking Time"] + #[inline(always)] + pub fn blankval(&mut self) -> BLANKVAL_W { + BLANKVAL_W { w: self } + } + #[doc = "Bits 24:27 - Fault B Filter Value"] + #[inline(always)] + pub fn filterval(&mut self) -> FILTERVAL_W { + FILTERVAL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Recoverable Fault B Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fctrlb](index.html) module"] +pub struct FCTRLB_SPEC; +impl crate::RegisterSpec for FCTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [fctrlb::R](R) reader structure"] +impl crate::Readable for FCTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [fctrlb::W](W) writer structure"] +impl crate::Writable for FCTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets FCTRLB to value 0"] +impl crate::Resettable for FCTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/tcc0/intenclr.rs b/pac/atsamc20n/src/tcc0/intenclr.rs new file mode 100644 index 000000000000..a227a8405a3c --- /dev/null +++ b/pac/atsamc20n/src/tcc0/intenclr.rs @@ -0,0 +1,724 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `TRG` reader - Retrigger Interrupt Enable"] +pub struct TRG_R(crate::FieldReader); +impl TRG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRG` writer - Retrigger Interrupt Enable"] +pub struct TRG_W<'a> { + w: &'a mut W, +} +impl<'a> TRG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CNT` reader - Counter Interrupt Enable"] +pub struct CNT_R(crate::FieldReader); +impl CNT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CNT` writer - Counter Interrupt Enable"] +pub struct CNT_W<'a> { + w: &'a mut W, +} +impl<'a> CNT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `ERR` reader - Error Interrupt Enable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - Error Interrupt Enable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `UFS` reader - Non-Recoverable Update Fault Interrupt Enable"] +pub struct UFS_R(crate::FieldReader); +impl UFS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UFS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for UFS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `UFS` writer - Non-Recoverable Update Fault Interrupt Enable"] +pub struct UFS_W<'a> { + w: &'a mut W, +} +impl<'a> UFS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `DFS` reader - Non-Recoverable Debug Fault Interrupt Enable"] +pub struct DFS_R(crate::FieldReader); +impl DFS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFS` writer - Non-Recoverable Debug Fault Interrupt Enable"] +pub struct DFS_W<'a> { + w: &'a mut W, +} +impl<'a> DFS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `FAULTA` reader - Recoverable Fault A Interrupt Enable"] +pub struct FAULTA_R(crate::FieldReader); +impl FAULTA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTA` writer - Recoverable Fault A Interrupt Enable"] +pub struct FAULTA_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `FAULTB` reader - Recoverable Fault B Interrupt Enable"] +pub struct FAULTB_R(crate::FieldReader); +impl FAULTB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTB` writer - Recoverable Fault B Interrupt Enable"] +pub struct FAULTB_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `FAULT0` reader - Non-Recoverable Fault 0 Interrupt Enable"] +pub struct FAULT0_R(crate::FieldReader); +impl FAULT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT0` writer - Non-Recoverable Fault 0 Interrupt Enable"] +pub struct FAULT0_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `FAULT1` reader - Non-Recoverable Fault 1 Interrupt Enable"] +pub struct FAULT1_R(crate::FieldReader); +impl FAULT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT1` writer - Non-Recoverable Fault 1 Interrupt Enable"] +pub struct FAULT1_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `MC0` reader - Match or Capture Channel 0 Interrupt Enable"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - Match or Capture Channel 0 Interrupt Enable"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `MC1` reader - Match or Capture Channel 1 Interrupt Enable"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - Match or Capture Channel 1 Interrupt Enable"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `MC2` reader - Match or Capture Channel 2 Interrupt Enable"] +pub struct MC2_R(crate::FieldReader); +impl MC2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC2` writer - Match or Capture Channel 2 Interrupt Enable"] +pub struct MC2_W<'a> { + w: &'a mut W, +} +impl<'a> MC2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `MC3` reader - Match or Capture Channel 3 Interrupt Enable"] +pub struct MC3_R(crate::FieldReader); +impl MC3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC3` writer - Match or Capture Channel 3 Interrupt Enable"] +pub struct MC3_W<'a> { + w: &'a mut W, +} +impl<'a> MC3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +impl R { + #[doc = "Bit 0 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Retrigger Interrupt Enable"] + #[inline(always)] + pub fn trg(&self) -> TRG_R { + TRG_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Counter Interrupt Enable"] + #[inline(always)] + pub fn cnt(&self) -> CNT_R { + CNT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Error Interrupt Enable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 10 - Non-Recoverable Update Fault Interrupt Enable"] + #[inline(always)] + pub fn ufs(&self) -> UFS_R { + UFS_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Non-Recoverable Debug Fault Interrupt Enable"] + #[inline(always)] + pub fn dfs(&self) -> DFS_R { + DFS_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Recoverable Fault A Interrupt Enable"] + #[inline(always)] + pub fn faulta(&self) -> FAULTA_R { + FAULTA_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Recoverable Fault B Interrupt Enable"] + #[inline(always)] + pub fn faultb(&self) -> FAULTB_R { + FAULTB_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Non-Recoverable Fault 0 Interrupt Enable"] + #[inline(always)] + pub fn fault0(&self) -> FAULT0_R { + FAULT0_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Non-Recoverable Fault 1 Interrupt Enable"] + #[inline(always)] + pub fn fault1(&self) -> FAULT1_R { + FAULT1_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Match or Capture Channel 0 Interrupt Enable"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Match or Capture Channel 1 Interrupt Enable"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Match or Capture Channel 2 Interrupt Enable"] + #[inline(always)] + pub fn mc2(&self) -> MC2_R { + MC2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Match or Capture Channel 3 Interrupt Enable"] + #[inline(always)] + pub fn mc3(&self) -> MC3_R { + MC3_R::new(((self.bits >> 19) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - Retrigger Interrupt Enable"] + #[inline(always)] + pub fn trg(&mut self) -> TRG_W { + TRG_W { w: self } + } + #[doc = "Bit 2 - Counter Interrupt Enable"] + #[inline(always)] + pub fn cnt(&mut self) -> CNT_W { + CNT_W { w: self } + } + #[doc = "Bit 3 - Error Interrupt Enable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 10 - Non-Recoverable Update Fault Interrupt Enable"] + #[inline(always)] + pub fn ufs(&mut self) -> UFS_W { + UFS_W { w: self } + } + #[doc = "Bit 11 - Non-Recoverable Debug Fault Interrupt Enable"] + #[inline(always)] + pub fn dfs(&mut self) -> DFS_W { + DFS_W { w: self } + } + #[doc = "Bit 12 - Recoverable Fault A Interrupt Enable"] + #[inline(always)] + pub fn faulta(&mut self) -> FAULTA_W { + FAULTA_W { w: self } + } + #[doc = "Bit 13 - Recoverable Fault B Interrupt Enable"] + #[inline(always)] + pub fn faultb(&mut self) -> FAULTB_W { + FAULTB_W { w: self } + } + #[doc = "Bit 14 - Non-Recoverable Fault 0 Interrupt Enable"] + #[inline(always)] + pub fn fault0(&mut self) -> FAULT0_W { + FAULT0_W { w: self } + } + #[doc = "Bit 15 - Non-Recoverable Fault 1 Interrupt Enable"] + #[inline(always)] + pub fn fault1(&mut self) -> FAULT1_W { + FAULT1_W { w: self } + } + #[doc = "Bit 16 - Match or Capture Channel 0 Interrupt Enable"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 17 - Match or Capture Channel 1 Interrupt Enable"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Bit 18 - Match or Capture Channel 2 Interrupt Enable"] + #[inline(always)] + pub fn mc2(&mut self) -> MC2_W { + MC2_W { w: self } + } + #[doc = "Bit 19 - Match or Capture Channel 3 Interrupt Enable"] + #[inline(always)] + pub fn mc3(&mut self) -> MC3_W { + MC3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/tcc0/intenset.rs b/pac/atsamc20n/src/tcc0/intenset.rs new file mode 100644 index 000000000000..0125a220bd02 --- /dev/null +++ b/pac/atsamc20n/src/tcc0/intenset.rs @@ -0,0 +1,724 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `TRG` reader - Retrigger Interrupt Enable"] +pub struct TRG_R(crate::FieldReader); +impl TRG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRG` writer - Retrigger Interrupt Enable"] +pub struct TRG_W<'a> { + w: &'a mut W, +} +impl<'a> TRG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CNT` reader - Counter Interrupt Enable"] +pub struct CNT_R(crate::FieldReader); +impl CNT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CNT` writer - Counter Interrupt Enable"] +pub struct CNT_W<'a> { + w: &'a mut W, +} +impl<'a> CNT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `ERR` reader - Error Interrupt Enable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - Error Interrupt Enable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `UFS` reader - Non-Recoverable Update Fault Interrupt Enable"] +pub struct UFS_R(crate::FieldReader); +impl UFS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UFS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for UFS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `UFS` writer - Non-Recoverable Update Fault Interrupt Enable"] +pub struct UFS_W<'a> { + w: &'a mut W, +} +impl<'a> UFS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `DFS` reader - Non-Recoverable Debug Fault Interrupt Enable"] +pub struct DFS_R(crate::FieldReader); +impl DFS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFS` writer - Non-Recoverable Debug Fault Interrupt Enable"] +pub struct DFS_W<'a> { + w: &'a mut W, +} +impl<'a> DFS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `FAULTA` reader - Recoverable Fault A Interrupt Enable"] +pub struct FAULTA_R(crate::FieldReader); +impl FAULTA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTA` writer - Recoverable Fault A Interrupt Enable"] +pub struct FAULTA_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `FAULTB` reader - Recoverable Fault B Interrupt Enable"] +pub struct FAULTB_R(crate::FieldReader); +impl FAULTB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTB` writer - Recoverable Fault B Interrupt Enable"] +pub struct FAULTB_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `FAULT0` reader - Non-Recoverable Fault 0 Interrupt Enable"] +pub struct FAULT0_R(crate::FieldReader); +impl FAULT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT0` writer - Non-Recoverable Fault 0 Interrupt Enable"] +pub struct FAULT0_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `FAULT1` reader - Non-Recoverable Fault 1 Interrupt Enable"] +pub struct FAULT1_R(crate::FieldReader); +impl FAULT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT1` writer - Non-Recoverable Fault 1 Interrupt Enable"] +pub struct FAULT1_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `MC0` reader - Match or Capture Channel 0 Interrupt Enable"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - Match or Capture Channel 0 Interrupt Enable"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `MC1` reader - Match or Capture Channel 1 Interrupt Enable"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - Match or Capture Channel 1 Interrupt Enable"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `MC2` reader - Match or Capture Channel 2 Interrupt Enable"] +pub struct MC2_R(crate::FieldReader); +impl MC2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC2` writer - Match or Capture Channel 2 Interrupt Enable"] +pub struct MC2_W<'a> { + w: &'a mut W, +} +impl<'a> MC2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `MC3` reader - Match or Capture Channel 3 Interrupt Enable"] +pub struct MC3_R(crate::FieldReader); +impl MC3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC3` writer - Match or Capture Channel 3 Interrupt Enable"] +pub struct MC3_W<'a> { + w: &'a mut W, +} +impl<'a> MC3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +impl R { + #[doc = "Bit 0 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Retrigger Interrupt Enable"] + #[inline(always)] + pub fn trg(&self) -> TRG_R { + TRG_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Counter Interrupt Enable"] + #[inline(always)] + pub fn cnt(&self) -> CNT_R { + CNT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Error Interrupt Enable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 10 - Non-Recoverable Update Fault Interrupt Enable"] + #[inline(always)] + pub fn ufs(&self) -> UFS_R { + UFS_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Non-Recoverable Debug Fault Interrupt Enable"] + #[inline(always)] + pub fn dfs(&self) -> DFS_R { + DFS_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Recoverable Fault A Interrupt Enable"] + #[inline(always)] + pub fn faulta(&self) -> FAULTA_R { + FAULTA_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Recoverable Fault B Interrupt Enable"] + #[inline(always)] + pub fn faultb(&self) -> FAULTB_R { + FAULTB_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Non-Recoverable Fault 0 Interrupt Enable"] + #[inline(always)] + pub fn fault0(&self) -> FAULT0_R { + FAULT0_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Non-Recoverable Fault 1 Interrupt Enable"] + #[inline(always)] + pub fn fault1(&self) -> FAULT1_R { + FAULT1_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Match or Capture Channel 0 Interrupt Enable"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Match or Capture Channel 1 Interrupt Enable"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Match or Capture Channel 2 Interrupt Enable"] + #[inline(always)] + pub fn mc2(&self) -> MC2_R { + MC2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Match or Capture Channel 3 Interrupt Enable"] + #[inline(always)] + pub fn mc3(&self) -> MC3_R { + MC3_R::new(((self.bits >> 19) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - Retrigger Interrupt Enable"] + #[inline(always)] + pub fn trg(&mut self) -> TRG_W { + TRG_W { w: self } + } + #[doc = "Bit 2 - Counter Interrupt Enable"] + #[inline(always)] + pub fn cnt(&mut self) -> CNT_W { + CNT_W { w: self } + } + #[doc = "Bit 3 - Error Interrupt Enable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 10 - Non-Recoverable Update Fault Interrupt Enable"] + #[inline(always)] + pub fn ufs(&mut self) -> UFS_W { + UFS_W { w: self } + } + #[doc = "Bit 11 - Non-Recoverable Debug Fault Interrupt Enable"] + #[inline(always)] + pub fn dfs(&mut self) -> DFS_W { + DFS_W { w: self } + } + #[doc = "Bit 12 - Recoverable Fault A Interrupt Enable"] + #[inline(always)] + pub fn faulta(&mut self) -> FAULTA_W { + FAULTA_W { w: self } + } + #[doc = "Bit 13 - Recoverable Fault B Interrupt Enable"] + #[inline(always)] + pub fn faultb(&mut self) -> FAULTB_W { + FAULTB_W { w: self } + } + #[doc = "Bit 14 - Non-Recoverable Fault 0 Interrupt Enable"] + #[inline(always)] + pub fn fault0(&mut self) -> FAULT0_W { + FAULT0_W { w: self } + } + #[doc = "Bit 15 - Non-Recoverable Fault 1 Interrupt Enable"] + #[inline(always)] + pub fn fault1(&mut self) -> FAULT1_W { + FAULT1_W { w: self } + } + #[doc = "Bit 16 - Match or Capture Channel 0 Interrupt Enable"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 17 - Match or Capture Channel 1 Interrupt Enable"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Bit 18 - Match or Capture Channel 2 Interrupt Enable"] + #[inline(always)] + pub fn mc2(&mut self) -> MC2_W { + MC2_W { w: self } + } + #[doc = "Bit 19 - Match or Capture Channel 3 Interrupt Enable"] + #[inline(always)] + pub fn mc3(&mut self) -> MC3_W { + MC3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/tcc0/intflag.rs b/pac/atsamc20n/src/tcc0/intflag.rs new file mode 100644 index 000000000000..b2d5088f4087 --- /dev/null +++ b/pac/atsamc20n/src/tcc0/intflag.rs @@ -0,0 +1,724 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - Overflow"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `TRG` reader - Retrigger"] +pub struct TRG_R(crate::FieldReader); +impl TRG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRG` writer - Retrigger"] +pub struct TRG_W<'a> { + w: &'a mut W, +} +impl<'a> TRG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CNT` reader - Counter"] +pub struct CNT_R(crate::FieldReader); +impl CNT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CNT` writer - Counter"] +pub struct CNT_W<'a> { + w: &'a mut W, +} +impl<'a> CNT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `ERR` reader - Error"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - Error"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `UFS` reader - Non-Recoverable Update Fault"] +pub struct UFS_R(crate::FieldReader); +impl UFS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UFS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for UFS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `UFS` writer - Non-Recoverable Update Fault"] +pub struct UFS_W<'a> { + w: &'a mut W, +} +impl<'a> UFS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `DFS` reader - Non-Recoverable Debug Fault"] +pub struct DFS_R(crate::FieldReader); +impl DFS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFS` writer - Non-Recoverable Debug Fault"] +pub struct DFS_W<'a> { + w: &'a mut W, +} +impl<'a> DFS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `FAULTA` reader - Recoverable Fault A"] +pub struct FAULTA_R(crate::FieldReader); +impl FAULTA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTA` writer - Recoverable Fault A"] +pub struct FAULTA_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `FAULTB` reader - Recoverable Fault B"] +pub struct FAULTB_R(crate::FieldReader); +impl FAULTB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTB` writer - Recoverable Fault B"] +pub struct FAULTB_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `FAULT0` reader - Non-Recoverable Fault 0"] +pub struct FAULT0_R(crate::FieldReader); +impl FAULT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT0` writer - Non-Recoverable Fault 0"] +pub struct FAULT0_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `FAULT1` reader - Non-Recoverable Fault 1"] +pub struct FAULT1_R(crate::FieldReader); +impl FAULT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT1` writer - Non-Recoverable Fault 1"] +pub struct FAULT1_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `MC0` reader - Match or Capture 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - Match or Capture 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `MC1` reader - Match or Capture 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - Match or Capture 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `MC2` reader - Match or Capture 2"] +pub struct MC2_R(crate::FieldReader); +impl MC2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC2` writer - Match or Capture 2"] +pub struct MC2_W<'a> { + w: &'a mut W, +} +impl<'a> MC2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `MC3` reader - Match or Capture 3"] +pub struct MC3_R(crate::FieldReader); +impl MC3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC3` writer - Match or Capture 3"] +pub struct MC3_W<'a> { + w: &'a mut W, +} +impl<'a> MC3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +impl R { + #[doc = "Bit 0 - Overflow"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Retrigger"] + #[inline(always)] + pub fn trg(&self) -> TRG_R { + TRG_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Counter"] + #[inline(always)] + pub fn cnt(&self) -> CNT_R { + CNT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Error"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 10 - Non-Recoverable Update Fault"] + #[inline(always)] + pub fn ufs(&self) -> UFS_R { + UFS_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Non-Recoverable Debug Fault"] + #[inline(always)] + pub fn dfs(&self) -> DFS_R { + DFS_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Recoverable Fault A"] + #[inline(always)] + pub fn faulta(&self) -> FAULTA_R { + FAULTA_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Recoverable Fault B"] + #[inline(always)] + pub fn faultb(&self) -> FAULTB_R { + FAULTB_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Non-Recoverable Fault 0"] + #[inline(always)] + pub fn fault0(&self) -> FAULT0_R { + FAULT0_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Non-Recoverable Fault 1"] + #[inline(always)] + pub fn fault1(&self) -> FAULT1_R { + FAULT1_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Match or Capture 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Match or Capture 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Match or Capture 2"] + #[inline(always)] + pub fn mc2(&self) -> MC2_R { + MC2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Match or Capture 3"] + #[inline(always)] + pub fn mc3(&self) -> MC3_R { + MC3_R::new(((self.bits >> 19) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Overflow"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - Retrigger"] + #[inline(always)] + pub fn trg(&mut self) -> TRG_W { + TRG_W { w: self } + } + #[doc = "Bit 2 - Counter"] + #[inline(always)] + pub fn cnt(&mut self) -> CNT_W { + CNT_W { w: self } + } + #[doc = "Bit 3 - Error"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 10 - Non-Recoverable Update Fault"] + #[inline(always)] + pub fn ufs(&mut self) -> UFS_W { + UFS_W { w: self } + } + #[doc = "Bit 11 - Non-Recoverable Debug Fault"] + #[inline(always)] + pub fn dfs(&mut self) -> DFS_W { + DFS_W { w: self } + } + #[doc = "Bit 12 - Recoverable Fault A"] + #[inline(always)] + pub fn faulta(&mut self) -> FAULTA_W { + FAULTA_W { w: self } + } + #[doc = "Bit 13 - Recoverable Fault B"] + #[inline(always)] + pub fn faultb(&mut self) -> FAULTB_W { + FAULTB_W { w: self } + } + #[doc = "Bit 14 - Non-Recoverable Fault 0"] + #[inline(always)] + pub fn fault0(&mut self) -> FAULT0_W { + FAULT0_W { w: self } + } + #[doc = "Bit 15 - Non-Recoverable Fault 1"] + #[inline(always)] + pub fn fault1(&mut self) -> FAULT1_W { + FAULT1_W { w: self } + } + #[doc = "Bit 16 - Match or Capture 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 17 - Match or Capture 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Bit 18 - Match or Capture 2"] + #[inline(always)] + pub fn mc2(&mut self) -> MC2_W { + MC2_W { w: self } + } + #[doc = "Bit 19 - Match or Capture 3"] + #[inline(always)] + pub fn mc3(&mut self) -> MC3_W { + MC3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/tcc0/patt.rs b/pac/atsamc20n/src/tcc0/patt.rs new file mode 100644 index 000000000000..ea458642b182 --- /dev/null +++ b/pac/atsamc20n/src/tcc0/patt.rs @@ -0,0 +1,818 @@ +#[doc = "Register `PATT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PATT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PGE0` reader - Pattern Generator 0 Output Enable"] +pub struct PGE0_R(crate::FieldReader); +impl PGE0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGE0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGE0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGE0` writer - Pattern Generator 0 Output Enable"] +pub struct PGE0_W<'a> { + w: &'a mut W, +} +impl<'a> PGE0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PGE1` reader - Pattern Generator 1 Output Enable"] +pub struct PGE1_R(crate::FieldReader); +impl PGE1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGE1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGE1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGE1` writer - Pattern Generator 1 Output Enable"] +pub struct PGE1_W<'a> { + w: &'a mut W, +} +impl<'a> PGE1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PGE2` reader - Pattern Generator 2 Output Enable"] +pub struct PGE2_R(crate::FieldReader); +impl PGE2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGE2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGE2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGE2` writer - Pattern Generator 2 Output Enable"] +pub struct PGE2_W<'a> { + w: &'a mut W, +} +impl<'a> PGE2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PGE3` reader - Pattern Generator 3 Output Enable"] +pub struct PGE3_R(crate::FieldReader); +impl PGE3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGE3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGE3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGE3` writer - Pattern Generator 3 Output Enable"] +pub struct PGE3_W<'a> { + w: &'a mut W, +} +impl<'a> PGE3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PGE4` reader - Pattern Generator 4 Output Enable"] +pub struct PGE4_R(crate::FieldReader); +impl PGE4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGE4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGE4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGE4` writer - Pattern Generator 4 Output Enable"] +pub struct PGE4_W<'a> { + w: &'a mut W, +} +impl<'a> PGE4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PGE5` reader - Pattern Generator 5 Output Enable"] +pub struct PGE5_R(crate::FieldReader); +impl PGE5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGE5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGE5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGE5` writer - Pattern Generator 5 Output Enable"] +pub struct PGE5_W<'a> { + w: &'a mut W, +} +impl<'a> PGE5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PGE6` reader - Pattern Generator 6 Output Enable"] +pub struct PGE6_R(crate::FieldReader); +impl PGE6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGE6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGE6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGE6` writer - Pattern Generator 6 Output Enable"] +pub struct PGE6_W<'a> { + w: &'a mut W, +} +impl<'a> PGE6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PGE7` reader - Pattern Generator 7 Output Enable"] +pub struct PGE7_R(crate::FieldReader); +impl PGE7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGE7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGE7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGE7` writer - Pattern Generator 7 Output Enable"] +pub struct PGE7_W<'a> { + w: &'a mut W, +} +impl<'a> PGE7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `PGV0` reader - Pattern Generator 0 Output Value"] +pub struct PGV0_R(crate::FieldReader); +impl PGV0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGV0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGV0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGV0` writer - Pattern Generator 0 Output Value"] +pub struct PGV0_W<'a> { + w: &'a mut W, +} +impl<'a> PGV0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `PGV1` reader - Pattern Generator 1 Output Value"] +pub struct PGV1_R(crate::FieldReader); +impl PGV1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGV1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGV1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGV1` writer - Pattern Generator 1 Output Value"] +pub struct PGV1_W<'a> { + w: &'a mut W, +} +impl<'a> PGV1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `PGV2` reader - Pattern Generator 2 Output Value"] +pub struct PGV2_R(crate::FieldReader); +impl PGV2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGV2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGV2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGV2` writer - Pattern Generator 2 Output Value"] +pub struct PGV2_W<'a> { + w: &'a mut W, +} +impl<'a> PGV2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u16 & 0x01) << 10); + self.w + } +} +#[doc = "Field `PGV3` reader - Pattern Generator 3 Output Value"] +pub struct PGV3_R(crate::FieldReader); +impl PGV3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGV3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGV3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGV3` writer - Pattern Generator 3 Output Value"] +pub struct PGV3_W<'a> { + w: &'a mut W, +} +impl<'a> PGV3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u16 & 0x01) << 11); + self.w + } +} +#[doc = "Field `PGV4` reader - Pattern Generator 4 Output Value"] +pub struct PGV4_R(crate::FieldReader); +impl PGV4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGV4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGV4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGV4` writer - Pattern Generator 4 Output Value"] +pub struct PGV4_W<'a> { + w: &'a mut W, +} +impl<'a> PGV4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u16 & 0x01) << 12); + self.w + } +} +#[doc = "Field `PGV5` reader - Pattern Generator 5 Output Value"] +pub struct PGV5_R(crate::FieldReader); +impl PGV5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGV5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGV5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGV5` writer - Pattern Generator 5 Output Value"] +pub struct PGV5_W<'a> { + w: &'a mut W, +} +impl<'a> PGV5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u16 & 0x01) << 13); + self.w + } +} +#[doc = "Field `PGV6` reader - Pattern Generator 6 Output Value"] +pub struct PGV6_R(crate::FieldReader); +impl PGV6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGV6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGV6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGV6` writer - Pattern Generator 6 Output Value"] +pub struct PGV6_W<'a> { + w: &'a mut W, +} +impl<'a> PGV6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u16 & 0x01) << 14); + self.w + } +} +#[doc = "Field `PGV7` reader - Pattern Generator 7 Output Value"] +pub struct PGV7_R(crate::FieldReader); +impl PGV7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGV7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGV7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGV7` writer - Pattern Generator 7 Output Value"] +pub struct PGV7_W<'a> { + w: &'a mut W, +} +impl<'a> PGV7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Pattern Generator 0 Output Enable"] + #[inline(always)] + pub fn pge0(&self) -> PGE0_R { + PGE0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Pattern Generator 1 Output Enable"] + #[inline(always)] + pub fn pge1(&self) -> PGE1_R { + PGE1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Pattern Generator 2 Output Enable"] + #[inline(always)] + pub fn pge2(&self) -> PGE2_R { + PGE2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Pattern Generator 3 Output Enable"] + #[inline(always)] + pub fn pge3(&self) -> PGE3_R { + PGE3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Pattern Generator 4 Output Enable"] + #[inline(always)] + pub fn pge4(&self) -> PGE4_R { + PGE4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Pattern Generator 5 Output Enable"] + #[inline(always)] + pub fn pge5(&self) -> PGE5_R { + PGE5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Pattern Generator 6 Output Enable"] + #[inline(always)] + pub fn pge6(&self) -> PGE6_R { + PGE6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Pattern Generator 7 Output Enable"] + #[inline(always)] + pub fn pge7(&self) -> PGE7_R { + PGE7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Pattern Generator 0 Output Value"] + #[inline(always)] + pub fn pgv0(&self) -> PGV0_R { + PGV0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Pattern Generator 1 Output Value"] + #[inline(always)] + pub fn pgv1(&self) -> PGV1_R { + PGV1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Pattern Generator 2 Output Value"] + #[inline(always)] + pub fn pgv2(&self) -> PGV2_R { + PGV2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Pattern Generator 3 Output Value"] + #[inline(always)] + pub fn pgv3(&self) -> PGV3_R { + PGV3_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Pattern Generator 4 Output Value"] + #[inline(always)] + pub fn pgv4(&self) -> PGV4_R { + PGV4_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Pattern Generator 5 Output Value"] + #[inline(always)] + pub fn pgv5(&self) -> PGV5_R { + PGV5_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Pattern Generator 6 Output Value"] + #[inline(always)] + pub fn pgv6(&self) -> PGV6_R { + PGV6_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Pattern Generator 7 Output Value"] + #[inline(always)] + pub fn pgv7(&self) -> PGV7_R { + PGV7_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pattern Generator 0 Output Enable"] + #[inline(always)] + pub fn pge0(&mut self) -> PGE0_W { + PGE0_W { w: self } + } + #[doc = "Bit 1 - Pattern Generator 1 Output Enable"] + #[inline(always)] + pub fn pge1(&mut self) -> PGE1_W { + PGE1_W { w: self } + } + #[doc = "Bit 2 - Pattern Generator 2 Output Enable"] + #[inline(always)] + pub fn pge2(&mut self) -> PGE2_W { + PGE2_W { w: self } + } + #[doc = "Bit 3 - Pattern Generator 3 Output Enable"] + #[inline(always)] + pub fn pge3(&mut self) -> PGE3_W { + PGE3_W { w: self } + } + #[doc = "Bit 4 - Pattern Generator 4 Output Enable"] + #[inline(always)] + pub fn pge4(&mut self) -> PGE4_W { + PGE4_W { w: self } + } + #[doc = "Bit 5 - Pattern Generator 5 Output Enable"] + #[inline(always)] + pub fn pge5(&mut self) -> PGE5_W { + PGE5_W { w: self } + } + #[doc = "Bit 6 - Pattern Generator 6 Output Enable"] + #[inline(always)] + pub fn pge6(&mut self) -> PGE6_W { + PGE6_W { w: self } + } + #[doc = "Bit 7 - Pattern Generator 7 Output Enable"] + #[inline(always)] + pub fn pge7(&mut self) -> PGE7_W { + PGE7_W { w: self } + } + #[doc = "Bit 8 - Pattern Generator 0 Output Value"] + #[inline(always)] + pub fn pgv0(&mut self) -> PGV0_W { + PGV0_W { w: self } + } + #[doc = "Bit 9 - Pattern Generator 1 Output Value"] + #[inline(always)] + pub fn pgv1(&mut self) -> PGV1_W { + PGV1_W { w: self } + } + #[doc = "Bit 10 - Pattern Generator 2 Output Value"] + #[inline(always)] + pub fn pgv2(&mut self) -> PGV2_W { + PGV2_W { w: self } + } + #[doc = "Bit 11 - Pattern Generator 3 Output Value"] + #[inline(always)] + pub fn pgv3(&mut self) -> PGV3_W { + PGV3_W { w: self } + } + #[doc = "Bit 12 - Pattern Generator 4 Output Value"] + #[inline(always)] + pub fn pgv4(&mut self) -> PGV4_W { + PGV4_W { w: self } + } + #[doc = "Bit 13 - Pattern Generator 5 Output Value"] + #[inline(always)] + pub fn pgv5(&mut self) -> PGV5_W { + PGV5_W { w: self } + } + #[doc = "Bit 14 - Pattern Generator 6 Output Value"] + #[inline(always)] + pub fn pgv6(&mut self) -> PGV6_W { + PGV6_W { w: self } + } + #[doc = "Bit 15 - Pattern Generator 7 Output Value"] + #[inline(always)] + pub fn pgv7(&mut self) -> PGV7_W { + PGV7_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Pattern\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [patt](index.html) module"] +pub struct PATT_SPEC; +impl crate::RegisterSpec for PATT_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [patt::R](R) reader structure"] +impl crate::Readable for PATT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [patt::W](W) writer structure"] +impl crate::Writable for PATT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PATT to value 0"] +impl crate::Resettable for PATT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/tcc0/pattbuf.rs b/pac/atsamc20n/src/tcc0/pattbuf.rs new file mode 100644 index 000000000000..c9375e27645c --- /dev/null +++ b/pac/atsamc20n/src/tcc0/pattbuf.rs @@ -0,0 +1,818 @@ +#[doc = "Register `PATTBUF` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PATTBUF` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PGEB0` reader - Pattern Generator 0 Output Enable Buffer"] +pub struct PGEB0_R(crate::FieldReader); +impl PGEB0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGEB0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGEB0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGEB0` writer - Pattern Generator 0 Output Enable Buffer"] +pub struct PGEB0_W<'a> { + w: &'a mut W, +} +impl<'a> PGEB0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PGEB1` reader - Pattern Generator 1 Output Enable Buffer"] +pub struct PGEB1_R(crate::FieldReader); +impl PGEB1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGEB1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGEB1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGEB1` writer - Pattern Generator 1 Output Enable Buffer"] +pub struct PGEB1_W<'a> { + w: &'a mut W, +} +impl<'a> PGEB1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PGEB2` reader - Pattern Generator 2 Output Enable Buffer"] +pub struct PGEB2_R(crate::FieldReader); +impl PGEB2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGEB2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGEB2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGEB2` writer - Pattern Generator 2 Output Enable Buffer"] +pub struct PGEB2_W<'a> { + w: &'a mut W, +} +impl<'a> PGEB2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PGEB3` reader - Pattern Generator 3 Output Enable Buffer"] +pub struct PGEB3_R(crate::FieldReader); +impl PGEB3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGEB3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGEB3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGEB3` writer - Pattern Generator 3 Output Enable Buffer"] +pub struct PGEB3_W<'a> { + w: &'a mut W, +} +impl<'a> PGEB3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PGEB4` reader - Pattern Generator 4 Output Enable Buffer"] +pub struct PGEB4_R(crate::FieldReader); +impl PGEB4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGEB4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGEB4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGEB4` writer - Pattern Generator 4 Output Enable Buffer"] +pub struct PGEB4_W<'a> { + w: &'a mut W, +} +impl<'a> PGEB4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PGEB5` reader - Pattern Generator 5 Output Enable Buffer"] +pub struct PGEB5_R(crate::FieldReader); +impl PGEB5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGEB5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGEB5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGEB5` writer - Pattern Generator 5 Output Enable Buffer"] +pub struct PGEB5_W<'a> { + w: &'a mut W, +} +impl<'a> PGEB5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PGEB6` reader - Pattern Generator 6 Output Enable Buffer"] +pub struct PGEB6_R(crate::FieldReader); +impl PGEB6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGEB6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGEB6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGEB6` writer - Pattern Generator 6 Output Enable Buffer"] +pub struct PGEB6_W<'a> { + w: &'a mut W, +} +impl<'a> PGEB6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PGEB7` reader - Pattern Generator 7 Output Enable Buffer"] +pub struct PGEB7_R(crate::FieldReader); +impl PGEB7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGEB7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGEB7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGEB7` writer - Pattern Generator 7 Output Enable Buffer"] +pub struct PGEB7_W<'a> { + w: &'a mut W, +} +impl<'a> PGEB7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `PGVB0` reader - Pattern Generator 0 Output Enable"] +pub struct PGVB0_R(crate::FieldReader); +impl PGVB0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGVB0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGVB0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGVB0` writer - Pattern Generator 0 Output Enable"] +pub struct PGVB0_W<'a> { + w: &'a mut W, +} +impl<'a> PGVB0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `PGVB1` reader - Pattern Generator 1 Output Enable"] +pub struct PGVB1_R(crate::FieldReader); +impl PGVB1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGVB1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGVB1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGVB1` writer - Pattern Generator 1 Output Enable"] +pub struct PGVB1_W<'a> { + w: &'a mut W, +} +impl<'a> PGVB1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `PGVB2` reader - Pattern Generator 2 Output Enable"] +pub struct PGVB2_R(crate::FieldReader); +impl PGVB2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGVB2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGVB2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGVB2` writer - Pattern Generator 2 Output Enable"] +pub struct PGVB2_W<'a> { + w: &'a mut W, +} +impl<'a> PGVB2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u16 & 0x01) << 10); + self.w + } +} +#[doc = "Field `PGVB3` reader - Pattern Generator 3 Output Enable"] +pub struct PGVB3_R(crate::FieldReader); +impl PGVB3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGVB3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGVB3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGVB3` writer - Pattern Generator 3 Output Enable"] +pub struct PGVB3_W<'a> { + w: &'a mut W, +} +impl<'a> PGVB3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u16 & 0x01) << 11); + self.w + } +} +#[doc = "Field `PGVB4` reader - Pattern Generator 4 Output Enable"] +pub struct PGVB4_R(crate::FieldReader); +impl PGVB4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGVB4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGVB4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGVB4` writer - Pattern Generator 4 Output Enable"] +pub struct PGVB4_W<'a> { + w: &'a mut W, +} +impl<'a> PGVB4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u16 & 0x01) << 12); + self.w + } +} +#[doc = "Field `PGVB5` reader - Pattern Generator 5 Output Enable"] +pub struct PGVB5_R(crate::FieldReader); +impl PGVB5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGVB5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGVB5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGVB5` writer - Pattern Generator 5 Output Enable"] +pub struct PGVB5_W<'a> { + w: &'a mut W, +} +impl<'a> PGVB5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u16 & 0x01) << 13); + self.w + } +} +#[doc = "Field `PGVB6` reader - Pattern Generator 6 Output Enable"] +pub struct PGVB6_R(crate::FieldReader); +impl PGVB6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGVB6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGVB6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGVB6` writer - Pattern Generator 6 Output Enable"] +pub struct PGVB6_W<'a> { + w: &'a mut W, +} +impl<'a> PGVB6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u16 & 0x01) << 14); + self.w + } +} +#[doc = "Field `PGVB7` reader - Pattern Generator 7 Output Enable"] +pub struct PGVB7_R(crate::FieldReader); +impl PGVB7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGVB7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGVB7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGVB7` writer - Pattern Generator 7 Output Enable"] +pub struct PGVB7_W<'a> { + w: &'a mut W, +} +impl<'a> PGVB7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Pattern Generator 0 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb0(&self) -> PGEB0_R { + PGEB0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Pattern Generator 1 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb1(&self) -> PGEB1_R { + PGEB1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Pattern Generator 2 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb2(&self) -> PGEB2_R { + PGEB2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Pattern Generator 3 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb3(&self) -> PGEB3_R { + PGEB3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Pattern Generator 4 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb4(&self) -> PGEB4_R { + PGEB4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Pattern Generator 5 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb5(&self) -> PGEB5_R { + PGEB5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Pattern Generator 6 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb6(&self) -> PGEB6_R { + PGEB6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Pattern Generator 7 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb7(&self) -> PGEB7_R { + PGEB7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Pattern Generator 0 Output Enable"] + #[inline(always)] + pub fn pgvb0(&self) -> PGVB0_R { + PGVB0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Pattern Generator 1 Output Enable"] + #[inline(always)] + pub fn pgvb1(&self) -> PGVB1_R { + PGVB1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Pattern Generator 2 Output Enable"] + #[inline(always)] + pub fn pgvb2(&self) -> PGVB2_R { + PGVB2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Pattern Generator 3 Output Enable"] + #[inline(always)] + pub fn pgvb3(&self) -> PGVB3_R { + PGVB3_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Pattern Generator 4 Output Enable"] + #[inline(always)] + pub fn pgvb4(&self) -> PGVB4_R { + PGVB4_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Pattern Generator 5 Output Enable"] + #[inline(always)] + pub fn pgvb5(&self) -> PGVB5_R { + PGVB5_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Pattern Generator 6 Output Enable"] + #[inline(always)] + pub fn pgvb6(&self) -> PGVB6_R { + PGVB6_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Pattern Generator 7 Output Enable"] + #[inline(always)] + pub fn pgvb7(&self) -> PGVB7_R { + PGVB7_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pattern Generator 0 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb0(&mut self) -> PGEB0_W { + PGEB0_W { w: self } + } + #[doc = "Bit 1 - Pattern Generator 1 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb1(&mut self) -> PGEB1_W { + PGEB1_W { w: self } + } + #[doc = "Bit 2 - Pattern Generator 2 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb2(&mut self) -> PGEB2_W { + PGEB2_W { w: self } + } + #[doc = "Bit 3 - Pattern Generator 3 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb3(&mut self) -> PGEB3_W { + PGEB3_W { w: self } + } + #[doc = "Bit 4 - Pattern Generator 4 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb4(&mut self) -> PGEB4_W { + PGEB4_W { w: self } + } + #[doc = "Bit 5 - Pattern Generator 5 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb5(&mut self) -> PGEB5_W { + PGEB5_W { w: self } + } + #[doc = "Bit 6 - Pattern Generator 6 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb6(&mut self) -> PGEB6_W { + PGEB6_W { w: self } + } + #[doc = "Bit 7 - Pattern Generator 7 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb7(&mut self) -> PGEB7_W { + PGEB7_W { w: self } + } + #[doc = "Bit 8 - Pattern Generator 0 Output Enable"] + #[inline(always)] + pub fn pgvb0(&mut self) -> PGVB0_W { + PGVB0_W { w: self } + } + #[doc = "Bit 9 - Pattern Generator 1 Output Enable"] + #[inline(always)] + pub fn pgvb1(&mut self) -> PGVB1_W { + PGVB1_W { w: self } + } + #[doc = "Bit 10 - Pattern Generator 2 Output Enable"] + #[inline(always)] + pub fn pgvb2(&mut self) -> PGVB2_W { + PGVB2_W { w: self } + } + #[doc = "Bit 11 - Pattern Generator 3 Output Enable"] + #[inline(always)] + pub fn pgvb3(&mut self) -> PGVB3_W { + PGVB3_W { w: self } + } + #[doc = "Bit 12 - Pattern Generator 4 Output Enable"] + #[inline(always)] + pub fn pgvb4(&mut self) -> PGVB4_W { + PGVB4_W { w: self } + } + #[doc = "Bit 13 - Pattern Generator 5 Output Enable"] + #[inline(always)] + pub fn pgvb5(&mut self) -> PGVB5_W { + PGVB5_W { w: self } + } + #[doc = "Bit 14 - Pattern Generator 6 Output Enable"] + #[inline(always)] + pub fn pgvb6(&mut self) -> PGVB6_W { + PGVB6_W { w: self } + } + #[doc = "Bit 15 - Pattern Generator 7 Output Enable"] + #[inline(always)] + pub fn pgvb7(&mut self) -> PGVB7_W { + PGVB7_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Pattern Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pattbuf](index.html) module"] +pub struct PATTBUF_SPEC; +impl crate::RegisterSpec for PATTBUF_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [pattbuf::R](R) reader structure"] +impl crate::Readable for PATTBUF_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [pattbuf::W](W) writer structure"] +impl crate::Writable for PATTBUF_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PATTBUF to value 0"] +impl crate::Resettable for PATTBUF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/tcc0/per.rs b/pac/atsamc20n/src/tcc0/per.rs new file mode 100644 index 000000000000..9d8618631650 --- /dev/null +++ b/pac/atsamc20n/src/tcc0/per.rs @@ -0,0 +1,103 @@ +#[doc = "Register `PER` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PER` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER` reader - Period Value"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` writer - Period Value"] +pub struct PER_W<'a> { + w: &'a mut W, +} +impl<'a> PER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Period Value"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Period Value"] + #[inline(always)] + pub fn per(&mut self) -> PER_W { + PER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [per](index.html) module"] +pub struct PER_SPEC; +impl crate::RegisterSpec for PER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [per::R](R) reader structure"] +impl crate::Readable for PER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [per::W](W) writer structure"] +impl crate::Writable for PER_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PER to value 0xffff_ffff"] +impl crate::Resettable for PER_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pac/atsamc20n/src/tcc0/per_dith4_mode.rs b/pac/atsamc20n/src/tcc0/per_dith4_mode.rs new file mode 100644 index 000000000000..2f600552db84 --- /dev/null +++ b/pac/atsamc20n/src/tcc0/per_dith4_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PER_DITH4_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PER_DITH4_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHER` reader - Dithering Cycle Number"] +pub struct DITHER_R(crate::FieldReader); +impl DITHER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHER` writer - Dithering Cycle Number"] +pub struct DITHER_W<'a> { + w: &'a mut W, +} +impl<'a> DITHER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Field `PER` reader - Period Value"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` writer - Period Value"] +pub struct PER_W<'a> { + w: &'a mut W, +} +impl<'a> PER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x000f_ffff << 4)) | ((value as u32 & 0x000f_ffff) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&self) -> DITHER_R { + DITHER_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:23 - Period Value"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(((self.bits >> 4) & 0x000f_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:3 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&mut self) -> DITHER_W { + DITHER_W { w: self } + } + #[doc = "Bits 4:23 - Period Value"] + #[inline(always)] + pub fn per(&mut self) -> PER_W { + PER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [per_dith4_mode](index.html) module"] +pub struct PER_DITH4_MODE_SPEC; +impl crate::RegisterSpec for PER_DITH4_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [per_dith4_mode::R](R) reader structure"] +impl crate::Readable for PER_DITH4_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [per_dith4_mode::W](W) writer structure"] +impl crate::Writable for PER_DITH4_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PER_DITH4_MODE to value 0xffff_ffff"] +impl crate::Resettable for PER_DITH4_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pac/atsamc20n/src/tcc0/per_dith5_mode.rs b/pac/atsamc20n/src/tcc0/per_dith5_mode.rs new file mode 100644 index 000000000000..1906582e4c95 --- /dev/null +++ b/pac/atsamc20n/src/tcc0/per_dith5_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PER_DITH5_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PER_DITH5_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHER` reader - Dithering Cycle Number"] +pub struct DITHER_R(crate::FieldReader); +impl DITHER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHER` writer - Dithering Cycle Number"] +pub struct DITHER_W<'a> { + w: &'a mut W, +} +impl<'a> DITHER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f); + self.w + } +} +#[doc = "Field `PER` reader - Period Value"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` writer - Period Value"] +pub struct PER_W<'a> { + w: &'a mut W, +} +impl<'a> PER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0007_ffff << 5)) | ((value as u32 & 0x0007_ffff) << 5); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&self) -> DITHER_R { + DITHER_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:23 - Period Value"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(((self.bits >> 5) & 0x0007_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:4 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&mut self) -> DITHER_W { + DITHER_W { w: self } + } + #[doc = "Bits 5:23 - Period Value"] + #[inline(always)] + pub fn per(&mut self) -> PER_W { + PER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [per_dith5_mode](index.html) module"] +pub struct PER_DITH5_MODE_SPEC; +impl crate::RegisterSpec for PER_DITH5_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [per_dith5_mode::R](R) reader structure"] +impl crate::Readable for PER_DITH5_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [per_dith5_mode::W](W) writer structure"] +impl crate::Writable for PER_DITH5_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PER_DITH5_MODE to value 0xffff_ffff"] +impl crate::Resettable for PER_DITH5_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pac/atsamc20n/src/tcc0/per_dith6_mode.rs b/pac/atsamc20n/src/tcc0/per_dith6_mode.rs new file mode 100644 index 000000000000..67880e220a9c --- /dev/null +++ b/pac/atsamc20n/src/tcc0/per_dith6_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PER_DITH6_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PER_DITH6_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHER` reader - Dithering Cycle Number"] +pub struct DITHER_R(crate::FieldReader); +impl DITHER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHER` writer - Dithering Cycle Number"] +pub struct DITHER_W<'a> { + w: &'a mut W, +} +impl<'a> DITHER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +#[doc = "Field `PER` reader - Period Value"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` writer - Period Value"] +pub struct PER_W<'a> { + w: &'a mut W, +} +impl<'a> PER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0003_ffff << 6)) | ((value as u32 & 0x0003_ffff) << 6); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&self) -> DITHER_R { + DITHER_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:23 - Period Value"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(((self.bits >> 6) & 0x0003_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:5 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&mut self) -> DITHER_W { + DITHER_W { w: self } + } + #[doc = "Bits 6:23 - Period Value"] + #[inline(always)] + pub fn per(&mut self) -> PER_W { + PER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [per_dith6_mode](index.html) module"] +pub struct PER_DITH6_MODE_SPEC; +impl crate::RegisterSpec for PER_DITH6_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [per_dith6_mode::R](R) reader structure"] +impl crate::Readable for PER_DITH6_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [per_dith6_mode::W](W) writer structure"] +impl crate::Writable for PER_DITH6_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PER_DITH6_MODE to value 0xffff_ffff"] +impl crate::Resettable for PER_DITH6_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pac/atsamc20n/src/tcc0/perbuf.rs b/pac/atsamc20n/src/tcc0/perbuf.rs new file mode 100644 index 000000000000..169f17479616 --- /dev/null +++ b/pac/atsamc20n/src/tcc0/perbuf.rs @@ -0,0 +1,103 @@ +#[doc = "Register `PERBUF` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PERBUF` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PERBUF` reader - Period Buffer Value"] +pub struct PERBUF_R(crate::FieldReader); +impl PERBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + PERBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERBUF` writer - Period Buffer Value"] +pub struct PERBUF_W<'a> { + w: &'a mut W, +} +impl<'a> PERBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Period Buffer Value"] + #[inline(always)] + pub fn perbuf(&self) -> PERBUF_R { + PERBUF_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Period Buffer Value"] + #[inline(always)] + pub fn perbuf(&mut self) -> PERBUF_W { + PERBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [perbuf](index.html) module"] +pub struct PERBUF_SPEC; +impl crate::RegisterSpec for PERBUF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [perbuf::R](R) reader structure"] +impl crate::Readable for PERBUF_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [perbuf::W](W) writer structure"] +impl crate::Writable for PERBUF_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PERBUF to value 0xffff_ffff"] +impl crate::Resettable for PERBUF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pac/atsamc20n/src/tcc0/perbuf_dith4_mode.rs b/pac/atsamc20n/src/tcc0/perbuf_dith4_mode.rs new file mode 100644 index 000000000000..ccf96ecef185 --- /dev/null +++ b/pac/atsamc20n/src/tcc0/perbuf_dith4_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PERBUF_DITH4_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PERBUF_DITH4_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHERBUF` reader - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_R(crate::FieldReader); +impl DITHERBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHERBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHERBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHERBUF` writer - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_W<'a> { + w: &'a mut W, +} +impl<'a> DITHERBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Field `PERBUF` reader - Period Buffer Value"] +pub struct PERBUF_R(crate::FieldReader); +impl PERBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + PERBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERBUF` writer - Period Buffer Value"] +pub struct PERBUF_W<'a> { + w: &'a mut W, +} +impl<'a> PERBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x000f_ffff << 4)) | ((value as u32 & 0x000f_ffff) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&self) -> DITHERBUF_R { + DITHERBUF_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:23 - Period Buffer Value"] + #[inline(always)] + pub fn perbuf(&self) -> PERBUF_R { + PERBUF_R::new(((self.bits >> 4) & 0x000f_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:3 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&mut self) -> DITHERBUF_W { + DITHERBUF_W { w: self } + } + #[doc = "Bits 4:23 - Period Buffer Value"] + #[inline(always)] + pub fn perbuf(&mut self) -> PERBUF_W { + PERBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [perbuf_dith4_mode](index.html) module"] +pub struct PERBUF_DITH4_MODE_SPEC; +impl crate::RegisterSpec for PERBUF_DITH4_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [perbuf_dith4_mode::R](R) reader structure"] +impl crate::Readable for PERBUF_DITH4_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [perbuf_dith4_mode::W](W) writer structure"] +impl crate::Writable for PERBUF_DITH4_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PERBUF_DITH4_MODE to value 0xffff_ffff"] +impl crate::Resettable for PERBUF_DITH4_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pac/atsamc20n/src/tcc0/perbuf_dith5_mode.rs b/pac/atsamc20n/src/tcc0/perbuf_dith5_mode.rs new file mode 100644 index 000000000000..d55f6d52c5ba --- /dev/null +++ b/pac/atsamc20n/src/tcc0/perbuf_dith5_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PERBUF_DITH5_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PERBUF_DITH5_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHERBUF` reader - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_R(crate::FieldReader); +impl DITHERBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHERBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHERBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHERBUF` writer - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_W<'a> { + w: &'a mut W, +} +impl<'a> DITHERBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f); + self.w + } +} +#[doc = "Field `PERBUF` reader - Period Buffer Value"] +pub struct PERBUF_R(crate::FieldReader); +impl PERBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + PERBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERBUF` writer - Period Buffer Value"] +pub struct PERBUF_W<'a> { + w: &'a mut W, +} +impl<'a> PERBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0007_ffff << 5)) | ((value as u32 & 0x0007_ffff) << 5); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&self) -> DITHERBUF_R { + DITHERBUF_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:23 - Period Buffer Value"] + #[inline(always)] + pub fn perbuf(&self) -> PERBUF_R { + PERBUF_R::new(((self.bits >> 5) & 0x0007_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:4 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&mut self) -> DITHERBUF_W { + DITHERBUF_W { w: self } + } + #[doc = "Bits 5:23 - Period Buffer Value"] + #[inline(always)] + pub fn perbuf(&mut self) -> PERBUF_W { + PERBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [perbuf_dith5_mode](index.html) module"] +pub struct PERBUF_DITH5_MODE_SPEC; +impl crate::RegisterSpec for PERBUF_DITH5_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [perbuf_dith5_mode::R](R) reader structure"] +impl crate::Readable for PERBUF_DITH5_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [perbuf_dith5_mode::W](W) writer structure"] +impl crate::Writable for PERBUF_DITH5_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PERBUF_DITH5_MODE to value 0xffff_ffff"] +impl crate::Resettable for PERBUF_DITH5_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pac/atsamc20n/src/tcc0/perbuf_dith6_mode.rs b/pac/atsamc20n/src/tcc0/perbuf_dith6_mode.rs new file mode 100644 index 000000000000..983c849f9073 --- /dev/null +++ b/pac/atsamc20n/src/tcc0/perbuf_dith6_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PERBUF_DITH6_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PERBUF_DITH6_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHERBUF` reader - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_R(crate::FieldReader); +impl DITHERBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHERBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHERBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHERBUF` writer - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_W<'a> { + w: &'a mut W, +} +impl<'a> DITHERBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +#[doc = "Field `PERBUF` reader - Period Buffer Value"] +pub struct PERBUF_R(crate::FieldReader); +impl PERBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + PERBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERBUF` writer - Period Buffer Value"] +pub struct PERBUF_W<'a> { + w: &'a mut W, +} +impl<'a> PERBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0003_ffff << 6)) | ((value as u32 & 0x0003_ffff) << 6); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&self) -> DITHERBUF_R { + DITHERBUF_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:23 - Period Buffer Value"] + #[inline(always)] + pub fn perbuf(&self) -> PERBUF_R { + PERBUF_R::new(((self.bits >> 6) & 0x0003_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:5 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&mut self) -> DITHERBUF_W { + DITHERBUF_W { w: self } + } + #[doc = "Bits 6:23 - Period Buffer Value"] + #[inline(always)] + pub fn perbuf(&mut self) -> PERBUF_W { + PERBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [perbuf_dith6_mode](index.html) module"] +pub struct PERBUF_DITH6_MODE_SPEC; +impl crate::RegisterSpec for PERBUF_DITH6_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [perbuf_dith6_mode::R](R) reader structure"] +impl crate::Readable for PERBUF_DITH6_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [perbuf_dith6_mode::W](W) writer structure"] +impl crate::Writable for PERBUF_DITH6_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PERBUF_DITH6_MODE to value 0xffff_ffff"] +impl crate::Resettable for PERBUF_DITH6_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pac/atsamc20n/src/tcc0/status.rs b/pac/atsamc20n/src/tcc0/status.rs new file mode 100644 index 000000000000..eecd909e6093 --- /dev/null +++ b/pac/atsamc20n/src/tcc0/status.rs @@ -0,0 +1,1147 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `STOP` reader - Stop"] +pub struct STOP_R(crate::FieldReader); +impl STOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STOP` writer - Stop"] +pub struct STOP_W<'a> { + w: &'a mut W, +} +impl<'a> STOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `IDX` reader - Ramp"] +pub struct IDX_R(crate::FieldReader); +impl IDX_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IDX_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IDX_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IDX` writer - Ramp"] +pub struct IDX_W<'a> { + w: &'a mut W, +} +impl<'a> IDX_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `UFS` reader - Non-recoverable Update Fault State"] +pub struct UFS_R(crate::FieldReader); +impl UFS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UFS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for UFS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `UFS` writer - Non-recoverable Update Fault State"] +pub struct UFS_W<'a> { + w: &'a mut W, +} +impl<'a> UFS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `DFS` reader - Non-Recoverable Debug Fault State"] +pub struct DFS_R(crate::FieldReader); +impl DFS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFS` writer - Non-Recoverable Debug Fault State"] +pub struct DFS_W<'a> { + w: &'a mut W, +} +impl<'a> DFS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `SLAVE` reader - Slave"] +pub struct SLAVE_R(crate::FieldReader); +impl SLAVE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLAVE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SLAVE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLAVE` writer - Slave"] +pub struct SLAVE_W<'a> { + w: &'a mut W, +} +impl<'a> SLAVE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PATTBUFV` reader - Pattern Buffer Valid"] +pub struct PATTBUFV_R(crate::FieldReader); +impl PATTBUFV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PATTBUFV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PATTBUFV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PATTBUFV` writer - Pattern Buffer Valid"] +pub struct PATTBUFV_W<'a> { + w: &'a mut W, +} +impl<'a> PATTBUFV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PERBUFV` reader - Period Buffer Valid"] +pub struct PERBUFV_R(crate::FieldReader); +impl PERBUFV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PERBUFV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERBUFV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERBUFV` writer - Period Buffer Valid"] +pub struct PERBUFV_W<'a> { + w: &'a mut W, +} +impl<'a> PERBUFV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `FAULTAIN` reader - Recoverable Fault A Input"] +pub struct FAULTAIN_R(crate::FieldReader); +impl FAULTAIN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTAIN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTAIN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTAIN` writer - Recoverable Fault A Input"] +pub struct FAULTAIN_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTAIN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `FAULTBIN` reader - Recoverable Fault B Input"] +pub struct FAULTBIN_R(crate::FieldReader); +impl FAULTBIN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTBIN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTBIN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTBIN` writer - Recoverable Fault B Input"] +pub struct FAULTBIN_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTBIN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `FAULT0IN` reader - Non-Recoverable Fault0 Input"] +pub struct FAULT0IN_R(crate::FieldReader); +impl FAULT0IN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT0IN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT0IN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT0IN` writer - Non-Recoverable Fault0 Input"] +pub struct FAULT0IN_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT0IN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `FAULT1IN` reader - Non-Recoverable Fault1 Input"] +pub struct FAULT1IN_R(crate::FieldReader); +impl FAULT1IN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT1IN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT1IN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT1IN` writer - Non-Recoverable Fault1 Input"] +pub struct FAULT1IN_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT1IN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `FAULTA` reader - Recoverable Fault A State"] +pub struct FAULTA_R(crate::FieldReader); +impl FAULTA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTA` writer - Recoverable Fault A State"] +pub struct FAULTA_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `FAULTB` reader - Recoverable Fault B State"] +pub struct FAULTB_R(crate::FieldReader); +impl FAULTB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTB` writer - Recoverable Fault B State"] +pub struct FAULTB_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `FAULT0` reader - Non-Recoverable Fault 0 State"] +pub struct FAULT0_R(crate::FieldReader); +impl FAULT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT0` writer - Non-Recoverable Fault 0 State"] +pub struct FAULT0_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `FAULT1` reader - Non-Recoverable Fault 1 State"] +pub struct FAULT1_R(crate::FieldReader); +impl FAULT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT1` writer - Non-Recoverable Fault 1 State"] +pub struct FAULT1_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `CCBUFV0` reader - Compare Channel 0 Buffer Valid"] +pub struct CCBUFV0_R(crate::FieldReader); +impl CCBUFV0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBUFV0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUFV0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUFV0` writer - Compare Channel 0 Buffer Valid"] +pub struct CCBUFV0_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUFV0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `CCBUFV1` reader - Compare Channel 1 Buffer Valid"] +pub struct CCBUFV1_R(crate::FieldReader); +impl CCBUFV1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBUFV1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUFV1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUFV1` writer - Compare Channel 1 Buffer Valid"] +pub struct CCBUFV1_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUFV1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `CCBUFV2` reader - Compare Channel 2 Buffer Valid"] +pub struct CCBUFV2_R(crate::FieldReader); +impl CCBUFV2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBUFV2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUFV2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUFV2` writer - Compare Channel 2 Buffer Valid"] +pub struct CCBUFV2_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUFV2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `CCBUFV3` reader - Compare Channel 3 Buffer Valid"] +pub struct CCBUFV3_R(crate::FieldReader); +impl CCBUFV3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBUFV3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUFV3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUFV3` writer - Compare Channel 3 Buffer Valid"] +pub struct CCBUFV3_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUFV3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `CMP0` reader - Compare Channel 0 Value"] +pub struct CMP0_R(crate::FieldReader); +impl CMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP0` writer - Compare Channel 0 Value"] +pub struct CMP0_W<'a> { + w: &'a mut W, +} +impl<'a> CMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `CMP1` reader - Compare Channel 1 Value"] +pub struct CMP1_R(crate::FieldReader); +impl CMP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP1` writer - Compare Channel 1 Value"] +pub struct CMP1_W<'a> { + w: &'a mut W, +} +impl<'a> CMP1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `CMP2` reader - Compare Channel 2 Value"] +pub struct CMP2_R(crate::FieldReader); +impl CMP2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP2` writer - Compare Channel 2 Value"] +pub struct CMP2_W<'a> { + w: &'a mut W, +} +impl<'a> CMP2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `CMP3` reader - Compare Channel 3 Value"] +pub struct CMP3_R(crate::FieldReader); +impl CMP3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP3` writer - Compare Channel 3 Value"] +pub struct CMP3_W<'a> { + w: &'a mut W, +} +impl<'a> CMP3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +impl R { + #[doc = "Bit 0 - Stop"] + #[inline(always)] + pub fn stop(&self) -> STOP_R { + STOP_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Ramp"] + #[inline(always)] + pub fn idx(&self) -> IDX_R { + IDX_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Non-recoverable Update Fault State"] + #[inline(always)] + pub fn ufs(&self) -> UFS_R { + UFS_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Non-Recoverable Debug Fault State"] + #[inline(always)] + pub fn dfs(&self) -> DFS_R { + DFS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Slave"] + #[inline(always)] + pub fn slave(&self) -> SLAVE_R { + SLAVE_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Pattern Buffer Valid"] + #[inline(always)] + pub fn pattbufv(&self) -> PATTBUFV_R { + PATTBUFV_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 7 - Period Buffer Valid"] + #[inline(always)] + pub fn perbufv(&self) -> PERBUFV_R { + PERBUFV_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Recoverable Fault A Input"] + #[inline(always)] + pub fn faultain(&self) -> FAULTAIN_R { + FAULTAIN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Recoverable Fault B Input"] + #[inline(always)] + pub fn faultbin(&self) -> FAULTBIN_R { + FAULTBIN_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Non-Recoverable Fault0 Input"] + #[inline(always)] + pub fn fault0in(&self) -> FAULT0IN_R { + FAULT0IN_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Non-Recoverable Fault1 Input"] + #[inline(always)] + pub fn fault1in(&self) -> FAULT1IN_R { + FAULT1IN_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Recoverable Fault A State"] + #[inline(always)] + pub fn faulta(&self) -> FAULTA_R { + FAULTA_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Recoverable Fault B State"] + #[inline(always)] + pub fn faultb(&self) -> FAULTB_R { + FAULTB_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Non-Recoverable Fault 0 State"] + #[inline(always)] + pub fn fault0(&self) -> FAULT0_R { + FAULT0_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Non-Recoverable Fault 1 State"] + #[inline(always)] + pub fn fault1(&self) -> FAULT1_R { + FAULT1_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Compare Channel 0 Buffer Valid"] + #[inline(always)] + pub fn ccbufv0(&self) -> CCBUFV0_R { + CCBUFV0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Compare Channel 1 Buffer Valid"] + #[inline(always)] + pub fn ccbufv1(&self) -> CCBUFV1_R { + CCBUFV1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Compare Channel 2 Buffer Valid"] + #[inline(always)] + pub fn ccbufv2(&self) -> CCBUFV2_R { + CCBUFV2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Compare Channel 3 Buffer Valid"] + #[inline(always)] + pub fn ccbufv3(&self) -> CCBUFV3_R { + CCBUFV3_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 24 - Compare Channel 0 Value"] + #[inline(always)] + pub fn cmp0(&self) -> CMP0_R { + CMP0_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Compare Channel 1 Value"] + #[inline(always)] + pub fn cmp1(&self) -> CMP1_R { + CMP1_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Compare Channel 2 Value"] + #[inline(always)] + pub fn cmp2(&self) -> CMP2_R { + CMP2_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Compare Channel 3 Value"] + #[inline(always)] + pub fn cmp3(&self) -> CMP3_R { + CMP3_R::new(((self.bits >> 27) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Stop"] + #[inline(always)] + pub fn stop(&mut self) -> STOP_W { + STOP_W { w: self } + } + #[doc = "Bit 1 - Ramp"] + #[inline(always)] + pub fn idx(&mut self) -> IDX_W { + IDX_W { w: self } + } + #[doc = "Bit 2 - Non-recoverable Update Fault State"] + #[inline(always)] + pub fn ufs(&mut self) -> UFS_W { + UFS_W { w: self } + } + #[doc = "Bit 3 - Non-Recoverable Debug Fault State"] + #[inline(always)] + pub fn dfs(&mut self) -> DFS_W { + DFS_W { w: self } + } + #[doc = "Bit 4 - Slave"] + #[inline(always)] + pub fn slave(&mut self) -> SLAVE_W { + SLAVE_W { w: self } + } + #[doc = "Bit 5 - Pattern Buffer Valid"] + #[inline(always)] + pub fn pattbufv(&mut self) -> PATTBUFV_W { + PATTBUFV_W { w: self } + } + #[doc = "Bit 7 - Period Buffer Valid"] + #[inline(always)] + pub fn perbufv(&mut self) -> PERBUFV_W { + PERBUFV_W { w: self } + } + #[doc = "Bit 8 - Recoverable Fault A Input"] + #[inline(always)] + pub fn faultain(&mut self) -> FAULTAIN_W { + FAULTAIN_W { w: self } + } + #[doc = "Bit 9 - Recoverable Fault B Input"] + #[inline(always)] + pub fn faultbin(&mut self) -> FAULTBIN_W { + FAULTBIN_W { w: self } + } + #[doc = "Bit 10 - Non-Recoverable Fault0 Input"] + #[inline(always)] + pub fn fault0in(&mut self) -> FAULT0IN_W { + FAULT0IN_W { w: self } + } + #[doc = "Bit 11 - Non-Recoverable Fault1 Input"] + #[inline(always)] + pub fn fault1in(&mut self) -> FAULT1IN_W { + FAULT1IN_W { w: self } + } + #[doc = "Bit 12 - Recoverable Fault A State"] + #[inline(always)] + pub fn faulta(&mut self) -> FAULTA_W { + FAULTA_W { w: self } + } + #[doc = "Bit 13 - Recoverable Fault B State"] + #[inline(always)] + pub fn faultb(&mut self) -> FAULTB_W { + FAULTB_W { w: self } + } + #[doc = "Bit 14 - Non-Recoverable Fault 0 State"] + #[inline(always)] + pub fn fault0(&mut self) -> FAULT0_W { + FAULT0_W { w: self } + } + #[doc = "Bit 15 - Non-Recoverable Fault 1 State"] + #[inline(always)] + pub fn fault1(&mut self) -> FAULT1_W { + FAULT1_W { w: self } + } + #[doc = "Bit 16 - Compare Channel 0 Buffer Valid"] + #[inline(always)] + pub fn ccbufv0(&mut self) -> CCBUFV0_W { + CCBUFV0_W { w: self } + } + #[doc = "Bit 17 - Compare Channel 1 Buffer Valid"] + #[inline(always)] + pub fn ccbufv1(&mut self) -> CCBUFV1_W { + CCBUFV1_W { w: self } + } + #[doc = "Bit 18 - Compare Channel 2 Buffer Valid"] + #[inline(always)] + pub fn ccbufv2(&mut self) -> CCBUFV2_W { + CCBUFV2_W { w: self } + } + #[doc = "Bit 19 - Compare Channel 3 Buffer Valid"] + #[inline(always)] + pub fn ccbufv3(&mut self) -> CCBUFV3_W { + CCBUFV3_W { w: self } + } + #[doc = "Bit 24 - Compare Channel 0 Value"] + #[inline(always)] + pub fn cmp0(&mut self) -> CMP0_W { + CMP0_W { w: self } + } + #[doc = "Bit 25 - Compare Channel 1 Value"] + #[inline(always)] + pub fn cmp1(&mut self) -> CMP1_W { + CMP1_W { w: self } + } + #[doc = "Bit 26 - Compare Channel 2 Value"] + #[inline(always)] + pub fn cmp2(&mut self) -> CMP2_W { + CMP2_W { w: self } + } + #[doc = "Bit 27 - Compare Channel 3 Value"] + #[inline(always)] + pub fn cmp3(&mut self) -> CMP3_W { + CMP3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0x01"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pac/atsamc20n/src/tcc0/syncbusy.rs b/pac/atsamc20n/src/tcc0/syncbusy.rs new file mode 100644 index 000000000000..db0788c3f206 --- /dev/null +++ b/pac/atsamc20n/src/tcc0/syncbusy.rs @@ -0,0 +1,273 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Swrst Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - Enable Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLB` reader - Ctrlb Busy"] +pub struct CTRLB_R(crate::FieldReader); +impl CTRLB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STATUS` reader - Status Busy"] +pub struct STATUS_R(crate::FieldReader); +impl STATUS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STATUS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STATUS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` reader - Count Busy"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PATT` reader - Pattern Busy"] +pub struct PATT_R(crate::FieldReader); +impl PATT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PATT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PATT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAVE` reader - Wave Busy"] +pub struct WAVE_R(crate::FieldReader); +impl WAVE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAVE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAVE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` reader - Period Busy"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC0` reader - Compare Channel 0 Busy"] +pub struct CC0_R(crate::FieldReader); +impl CC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC1` reader - Compare Channel 1 Busy"] +pub struct CC1_R(crate::FieldReader); +impl CC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC2` reader - Compare Channel 2 Busy"] +pub struct CC2_R(crate::FieldReader); +impl CC2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC3` reader - Compare Channel 3 Busy"] +pub struct CC3_R(crate::FieldReader); +impl CC3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Swrst Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Ctrlb Busy"] + #[inline(always)] + pub fn ctrlb(&self) -> CTRLB_R { + CTRLB_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Status Busy"] + #[inline(always)] + pub fn status(&self) -> STATUS_R { + STATUS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Count Busy"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Pattern Busy"] + #[inline(always)] + pub fn patt(&self) -> PATT_R { + PATT_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Wave Busy"] + #[inline(always)] + pub fn wave(&self) -> WAVE_R { + WAVE_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Period Busy"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Compare Channel 0 Busy"] + #[inline(always)] + pub fn cc0(&self) -> CC0_R { + CC0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Compare Channel 1 Busy"] + #[inline(always)] + pub fn cc1(&self) -> CC1_R { + CC1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Compare Channel 2 Busy"] + #[inline(always)] + pub fn cc2(&self) -> CC2_R { + CC2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Compare Channel 3 Busy"] + #[inline(always)] + pub fn cc3(&self) -> CC3_R { + CC3_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +#[doc = "Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/tcc0/wave.rs b/pac/atsamc20n/src/tcc0/wave.rs new file mode 100644 index 000000000000..8d092d429a91 --- /dev/null +++ b/pac/atsamc20n/src/tcc0/wave.rs @@ -0,0 +1,940 @@ +#[doc = "Register `WAVE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WAVE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Waveform Generation\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WAVEGEN_A { + #[doc = "0: Normal frequency"] + NFRQ = 0, + #[doc = "1: Match frequency"] + MFRQ = 1, + #[doc = "2: Normal PWM"] + NPWM = 2, + #[doc = "4: Dual-slope critical"] + DSCRITICAL = 4, + #[doc = "5: Dual-slope with interrupt/event condition when COUNT reaches ZERO"] + DSBOTTOM = 5, + #[doc = "6: Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP"] + DSBOTH = 6, + #[doc = "7: Dual-slope with interrupt/event condition when COUNT reaches TOP"] + DSTOP = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WAVEGEN_A) -> Self { + variant as _ + } +} +#[doc = "Field `WAVEGEN` reader - Waveform Generation"] +pub struct WAVEGEN_R(crate::FieldReader); +impl WAVEGEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WAVEGEN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(WAVEGEN_A::NFRQ), + 1 => Some(WAVEGEN_A::MFRQ), + 2 => Some(WAVEGEN_A::NPWM), + 4 => Some(WAVEGEN_A::DSCRITICAL), + 5 => Some(WAVEGEN_A::DSBOTTOM), + 6 => Some(WAVEGEN_A::DSBOTH), + 7 => Some(WAVEGEN_A::DSTOP), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NFRQ`"] + #[inline(always)] + pub fn is_nfrq(&self) -> bool { + **self == WAVEGEN_A::NFRQ + } + #[doc = "Checks if the value of the field is `MFRQ`"] + #[inline(always)] + pub fn is_mfrq(&self) -> bool { + **self == WAVEGEN_A::MFRQ + } + #[doc = "Checks if the value of the field is `NPWM`"] + #[inline(always)] + pub fn is_npwm(&self) -> bool { + **self == WAVEGEN_A::NPWM + } + #[doc = "Checks if the value of the field is `DSCRITICAL`"] + #[inline(always)] + pub fn is_dscritical(&self) -> bool { + **self == WAVEGEN_A::DSCRITICAL + } + #[doc = "Checks if the value of the field is `DSBOTTOM`"] + #[inline(always)] + pub fn is_dsbottom(&self) -> bool { + **self == WAVEGEN_A::DSBOTTOM + } + #[doc = "Checks if the value of the field is `DSBOTH`"] + #[inline(always)] + pub fn is_dsboth(&self) -> bool { + **self == WAVEGEN_A::DSBOTH + } + #[doc = "Checks if the value of the field is `DSTOP`"] + #[inline(always)] + pub fn is_dstop(&self) -> bool { + **self == WAVEGEN_A::DSTOP + } +} +impl core::ops::Deref for WAVEGEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAVEGEN` writer - Waveform Generation"] +pub struct WAVEGEN_W<'a> { + w: &'a mut W, +} +impl<'a> WAVEGEN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WAVEGEN_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Normal frequency"] + #[inline(always)] + pub fn nfrq(self) -> &'a mut W { + self.variant(WAVEGEN_A::NFRQ) + } + #[doc = "Match frequency"] + #[inline(always)] + pub fn mfrq(self) -> &'a mut W { + self.variant(WAVEGEN_A::MFRQ) + } + #[doc = "Normal PWM"] + #[inline(always)] + pub fn npwm(self) -> &'a mut W { + self.variant(WAVEGEN_A::NPWM) + } + #[doc = "Dual-slope critical"] + #[inline(always)] + pub fn dscritical(self) -> &'a mut W { + self.variant(WAVEGEN_A::DSCRITICAL) + } + #[doc = "Dual-slope with interrupt/event condition when COUNT reaches ZERO"] + #[inline(always)] + pub fn dsbottom(self) -> &'a mut W { + self.variant(WAVEGEN_A::DSBOTTOM) + } + #[doc = "Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP"] + #[inline(always)] + pub fn dsboth(self) -> &'a mut W { + self.variant(WAVEGEN_A::DSBOTH) + } + #[doc = "Dual-slope with interrupt/event condition when COUNT reaches TOP"] + #[inline(always)] + pub fn dstop(self) -> &'a mut W { + self.variant(WAVEGEN_A::DSTOP) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Ramp Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum RAMP_A { + #[doc = "0: RAMP1 operation"] + RAMP1 = 0, + #[doc = "1: Alternative RAMP2 operation"] + RAMP2A = 1, + #[doc = "2: RAMP2 operation"] + RAMP2 = 2, + #[doc = "3: Critical RAMP2 operation"] + RAMP2C = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RAMP_A) -> Self { + variant as _ + } +} +#[doc = "Field `RAMP` reader - Ramp Mode"] +pub struct RAMP_R(crate::FieldReader); +impl RAMP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RAMP_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RAMP_A { + match self.bits { + 0 => RAMP_A::RAMP1, + 1 => RAMP_A::RAMP2A, + 2 => RAMP_A::RAMP2, + 3 => RAMP_A::RAMP2C, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `RAMP1`"] + #[inline(always)] + pub fn is_ramp1(&self) -> bool { + **self == RAMP_A::RAMP1 + } + #[doc = "Checks if the value of the field is `RAMP2A`"] + #[inline(always)] + pub fn is_ramp2a(&self) -> bool { + **self == RAMP_A::RAMP2A + } + #[doc = "Checks if the value of the field is `RAMP2`"] + #[inline(always)] + pub fn is_ramp2(&self) -> bool { + **self == RAMP_A::RAMP2 + } + #[doc = "Checks if the value of the field is `RAMP2C`"] + #[inline(always)] + pub fn is_ramp2c(&self) -> bool { + **self == RAMP_A::RAMP2C + } +} +impl core::ops::Deref for RAMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RAMP` writer - Ramp Mode"] +pub struct RAMP_W<'a> { + w: &'a mut W, +} +impl<'a> RAMP_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RAMP_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "RAMP1 operation"] + #[inline(always)] + pub fn ramp1(self) -> &'a mut W { + self.variant(RAMP_A::RAMP1) + } + #[doc = "Alternative RAMP2 operation"] + #[inline(always)] + pub fn ramp2a(self) -> &'a mut W { + self.variant(RAMP_A::RAMP2A) + } + #[doc = "RAMP2 operation"] + #[inline(always)] + pub fn ramp2(self) -> &'a mut W { + self.variant(RAMP_A::RAMP2) + } + #[doc = "Critical RAMP2 operation"] + #[inline(always)] + pub fn ramp2c(self) -> &'a mut W { + self.variant(RAMP_A::RAMP2C) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u32 & 0x03) << 4); + self.w + } +} +#[doc = "Field `CIPEREN` reader - Circular period Enable"] +pub struct CIPEREN_R(crate::FieldReader); +impl CIPEREN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CIPEREN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CIPEREN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CIPEREN` writer - Circular period Enable"] +pub struct CIPEREN_W<'a> { + w: &'a mut W, +} +impl<'a> CIPEREN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CICCEN0` reader - Circular Channel 0 Enable"] +pub struct CICCEN0_R(crate::FieldReader); +impl CICCEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CICCEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CICCEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CICCEN0` writer - Circular Channel 0 Enable"] +pub struct CICCEN0_W<'a> { + w: &'a mut W, +} +impl<'a> CICCEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `CICCEN1` reader - Circular Channel 1 Enable"] +pub struct CICCEN1_R(crate::FieldReader); +impl CICCEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CICCEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CICCEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CICCEN1` writer - Circular Channel 1 Enable"] +pub struct CICCEN1_W<'a> { + w: &'a mut W, +} +impl<'a> CICCEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `CICCEN2` reader - Circular Channel 2 Enable"] +pub struct CICCEN2_R(crate::FieldReader); +impl CICCEN2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CICCEN2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CICCEN2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CICCEN2` writer - Circular Channel 2 Enable"] +pub struct CICCEN2_W<'a> { + w: &'a mut W, +} +impl<'a> CICCEN2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `CICCEN3` reader - Circular Channel 3 Enable"] +pub struct CICCEN3_R(crate::FieldReader); +impl CICCEN3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CICCEN3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CICCEN3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CICCEN3` writer - Circular Channel 3 Enable"] +pub struct CICCEN3_W<'a> { + w: &'a mut W, +} +impl<'a> CICCEN3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `POL0` reader - Channel 0 Polarity"] +pub struct POL0_R(crate::FieldReader); +impl POL0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + POL0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for POL0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `POL0` writer - Channel 0 Polarity"] +pub struct POL0_W<'a> { + w: &'a mut W, +} +impl<'a> POL0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `POL1` reader - Channel 1 Polarity"] +pub struct POL1_R(crate::FieldReader); +impl POL1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + POL1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for POL1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `POL1` writer - Channel 1 Polarity"] +pub struct POL1_W<'a> { + w: &'a mut W, +} +impl<'a> POL1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `POL2` reader - Channel 2 Polarity"] +pub struct POL2_R(crate::FieldReader); +impl POL2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + POL2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for POL2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `POL2` writer - Channel 2 Polarity"] +pub struct POL2_W<'a> { + w: &'a mut W, +} +impl<'a> POL2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `POL3` reader - Channel 3 Polarity"] +pub struct POL3_R(crate::FieldReader); +impl POL3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + POL3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for POL3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `POL3` writer - Channel 3 Polarity"] +pub struct POL3_W<'a> { + w: &'a mut W, +} +impl<'a> POL3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `SWAP0` reader - Swap DTI Output Pair 0"] +pub struct SWAP0_R(crate::FieldReader); +impl SWAP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWAP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWAP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWAP0` writer - Swap DTI Output Pair 0"] +pub struct SWAP0_W<'a> { + w: &'a mut W, +} +impl<'a> SWAP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `SWAP1` reader - Swap DTI Output Pair 1"] +pub struct SWAP1_R(crate::FieldReader); +impl SWAP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWAP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWAP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWAP1` writer - Swap DTI Output Pair 1"] +pub struct SWAP1_W<'a> { + w: &'a mut W, +} +impl<'a> SWAP1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `SWAP2` reader - Swap DTI Output Pair 2"] +pub struct SWAP2_R(crate::FieldReader); +impl SWAP2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWAP2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWAP2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWAP2` writer - Swap DTI Output Pair 2"] +pub struct SWAP2_W<'a> { + w: &'a mut W, +} +impl<'a> SWAP2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `SWAP3` reader - Swap DTI Output Pair 3"] +pub struct SWAP3_R(crate::FieldReader); +impl SWAP3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWAP3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWAP3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWAP3` writer - Swap DTI Output Pair 3"] +pub struct SWAP3_W<'a> { + w: &'a mut W, +} +impl<'a> SWAP3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Waveform Generation"] + #[inline(always)] + pub fn wavegen(&self) -> WAVEGEN_R { + WAVEGEN_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bits 4:5 - Ramp Mode"] + #[inline(always)] + pub fn ramp(&self) -> RAMP_R { + RAMP_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bit 7 - Circular period Enable"] + #[inline(always)] + pub fn ciperen(&self) -> CIPEREN_R { + CIPEREN_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Circular Channel 0 Enable"] + #[inline(always)] + pub fn ciccen0(&self) -> CICCEN0_R { + CICCEN0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Circular Channel 1 Enable"] + #[inline(always)] + pub fn ciccen1(&self) -> CICCEN1_R { + CICCEN1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Circular Channel 2 Enable"] + #[inline(always)] + pub fn ciccen2(&self) -> CICCEN2_R { + CICCEN2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Circular Channel 3 Enable"] + #[inline(always)] + pub fn ciccen3(&self) -> CICCEN3_R { + CICCEN3_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 16 - Channel 0 Polarity"] + #[inline(always)] + pub fn pol0(&self) -> POL0_R { + POL0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Channel 1 Polarity"] + #[inline(always)] + pub fn pol1(&self) -> POL1_R { + POL1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Channel 2 Polarity"] + #[inline(always)] + pub fn pol2(&self) -> POL2_R { + POL2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Channel 3 Polarity"] + #[inline(always)] + pub fn pol3(&self) -> POL3_R { + POL3_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 24 - Swap DTI Output Pair 0"] + #[inline(always)] + pub fn swap0(&self) -> SWAP0_R { + SWAP0_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Swap DTI Output Pair 1"] + #[inline(always)] + pub fn swap1(&self) -> SWAP1_R { + SWAP1_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Swap DTI Output Pair 2"] + #[inline(always)] + pub fn swap2(&self) -> SWAP2_R { + SWAP2_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Swap DTI Output Pair 3"] + #[inline(always)] + pub fn swap3(&self) -> SWAP3_R { + SWAP3_R::new(((self.bits >> 27) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Waveform Generation"] + #[inline(always)] + pub fn wavegen(&mut self) -> WAVEGEN_W { + WAVEGEN_W { w: self } + } + #[doc = "Bits 4:5 - Ramp Mode"] + #[inline(always)] + pub fn ramp(&mut self) -> RAMP_W { + RAMP_W { w: self } + } + #[doc = "Bit 7 - Circular period Enable"] + #[inline(always)] + pub fn ciperen(&mut self) -> CIPEREN_W { + CIPEREN_W { w: self } + } + #[doc = "Bit 8 - Circular Channel 0 Enable"] + #[inline(always)] + pub fn ciccen0(&mut self) -> CICCEN0_W { + CICCEN0_W { w: self } + } + #[doc = "Bit 9 - Circular Channel 1 Enable"] + #[inline(always)] + pub fn ciccen1(&mut self) -> CICCEN1_W { + CICCEN1_W { w: self } + } + #[doc = "Bit 10 - Circular Channel 2 Enable"] + #[inline(always)] + pub fn ciccen2(&mut self) -> CICCEN2_W { + CICCEN2_W { w: self } + } + #[doc = "Bit 11 - Circular Channel 3 Enable"] + #[inline(always)] + pub fn ciccen3(&mut self) -> CICCEN3_W { + CICCEN3_W { w: self } + } + #[doc = "Bit 16 - Channel 0 Polarity"] + #[inline(always)] + pub fn pol0(&mut self) -> POL0_W { + POL0_W { w: self } + } + #[doc = "Bit 17 - Channel 1 Polarity"] + #[inline(always)] + pub fn pol1(&mut self) -> POL1_W { + POL1_W { w: self } + } + #[doc = "Bit 18 - Channel 2 Polarity"] + #[inline(always)] + pub fn pol2(&mut self) -> POL2_W { + POL2_W { w: self } + } + #[doc = "Bit 19 - Channel 3 Polarity"] + #[inline(always)] + pub fn pol3(&mut self) -> POL3_W { + POL3_W { w: self } + } + #[doc = "Bit 24 - Swap DTI Output Pair 0"] + #[inline(always)] + pub fn swap0(&mut self) -> SWAP0_W { + SWAP0_W { w: self } + } + #[doc = "Bit 25 - Swap DTI Output Pair 1"] + #[inline(always)] + pub fn swap1(&mut self) -> SWAP1_W { + SWAP1_W { w: self } + } + #[doc = "Bit 26 - Swap DTI Output Pair 2"] + #[inline(always)] + pub fn swap2(&mut self) -> SWAP2_W { + SWAP2_W { w: self } + } + #[doc = "Bit 27 - Swap DTI Output Pair 3"] + #[inline(always)] + pub fn swap3(&mut self) -> SWAP3_W { + SWAP3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Waveform Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wave](index.html) module"] +pub struct WAVE_SPEC; +impl crate::RegisterSpec for WAVE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [wave::R](R) reader structure"] +impl crate::Readable for WAVE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wave::W](W) writer structure"] +impl crate::Writable for WAVE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WAVE to value 0"] +impl crate::Resettable for WAVE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/tcc0/wexctrl.rs b/pac/atsamc20n/src/tcc0/wexctrl.rs new file mode 100644 index 000000000000..8eb0d29cbee5 --- /dev/null +++ b/pac/atsamc20n/src/tcc0/wexctrl.rs @@ -0,0 +1,365 @@ +#[doc = "Register `WEXCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WEXCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OTMX` reader - Output Matrix"] +pub struct OTMX_R(crate::FieldReader); +impl OTMX_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + OTMX_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OTMX_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OTMX` writer - Output Matrix"] +pub struct OTMX_W<'a> { + w: &'a mut W, +} +impl<'a> OTMX_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u32 & 0x03); + self.w + } +} +#[doc = "Field `DTIEN0` reader - Dead-time Insertion Generator 0 Enable"] +pub struct DTIEN0_R(crate::FieldReader); +impl DTIEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DTIEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DTIEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DTIEN0` writer - Dead-time Insertion Generator 0 Enable"] +pub struct DTIEN0_W<'a> { + w: &'a mut W, +} +impl<'a> DTIEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `DTIEN1` reader - Dead-time Insertion Generator 1 Enable"] +pub struct DTIEN1_R(crate::FieldReader); +impl DTIEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DTIEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DTIEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DTIEN1` writer - Dead-time Insertion Generator 1 Enable"] +pub struct DTIEN1_W<'a> { + w: &'a mut W, +} +impl<'a> DTIEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `DTIEN2` reader - Dead-time Insertion Generator 2 Enable"] +pub struct DTIEN2_R(crate::FieldReader); +impl DTIEN2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DTIEN2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DTIEN2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DTIEN2` writer - Dead-time Insertion Generator 2 Enable"] +pub struct DTIEN2_W<'a> { + w: &'a mut W, +} +impl<'a> DTIEN2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `DTIEN3` reader - Dead-time Insertion Generator 3 Enable"] +pub struct DTIEN3_R(crate::FieldReader); +impl DTIEN3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DTIEN3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DTIEN3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DTIEN3` writer - Dead-time Insertion Generator 3 Enable"] +pub struct DTIEN3_W<'a> { + w: &'a mut W, +} +impl<'a> DTIEN3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `DTLS` reader - Dead-time Low Side Outputs Value"] +pub struct DTLS_R(crate::FieldReader); +impl DTLS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DTLS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DTLS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DTLS` writer - Dead-time Low Side Outputs Value"] +pub struct DTLS_W<'a> { + w: &'a mut W, +} +impl<'a> DTLS_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +#[doc = "Field `DTHS` reader - Dead-time High Side Outputs Value"] +pub struct DTHS_R(crate::FieldReader); +impl DTHS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DTHS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DTHS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DTHS` writer - Dead-time High Side Outputs Value"] +pub struct DTHS_W<'a> { + w: &'a mut W, +} +impl<'a> DTHS_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 24)) | ((value as u32 & 0xff) << 24); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Output Matrix"] + #[inline(always)] + pub fn otmx(&self) -> OTMX_R { + OTMX_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bit 8 - Dead-time Insertion Generator 0 Enable"] + #[inline(always)] + pub fn dtien0(&self) -> DTIEN0_R { + DTIEN0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Dead-time Insertion Generator 1 Enable"] + #[inline(always)] + pub fn dtien1(&self) -> DTIEN1_R { + DTIEN1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Dead-time Insertion Generator 2 Enable"] + #[inline(always)] + pub fn dtien2(&self) -> DTIEN2_R { + DTIEN2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Dead-time Insertion Generator 3 Enable"] + #[inline(always)] + pub fn dtien3(&self) -> DTIEN3_R { + DTIEN3_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bits 16:23 - Dead-time Low Side Outputs Value"] + #[inline(always)] + pub fn dtls(&self) -> DTLS_R { + DTLS_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Dead-time High Side Outputs Value"] + #[inline(always)] + pub fn dths(&self) -> DTHS_R { + DTHS_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Output Matrix"] + #[inline(always)] + pub fn otmx(&mut self) -> OTMX_W { + OTMX_W { w: self } + } + #[doc = "Bit 8 - Dead-time Insertion Generator 0 Enable"] + #[inline(always)] + pub fn dtien0(&mut self) -> DTIEN0_W { + DTIEN0_W { w: self } + } + #[doc = "Bit 9 - Dead-time Insertion Generator 1 Enable"] + #[inline(always)] + pub fn dtien1(&mut self) -> DTIEN1_W { + DTIEN1_W { w: self } + } + #[doc = "Bit 10 - Dead-time Insertion Generator 2 Enable"] + #[inline(always)] + pub fn dtien2(&mut self) -> DTIEN2_W { + DTIEN2_W { w: self } + } + #[doc = "Bit 11 - Dead-time Insertion Generator 3 Enable"] + #[inline(always)] + pub fn dtien3(&mut self) -> DTIEN3_W { + DTIEN3_W { w: self } + } + #[doc = "Bits 16:23 - Dead-time Low Side Outputs Value"] + #[inline(always)] + pub fn dtls(&mut self) -> DTLS_W { + DTLS_W { w: self } + } + #[doc = "Bits 24:31 - Dead-time High Side Outputs Value"] + #[inline(always)] + pub fn dths(&mut self) -> DTHS_W { + DTHS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Waveform Extension Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wexctrl](index.html) module"] +pub struct WEXCTRL_SPEC; +impl crate::RegisterSpec for WEXCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [wexctrl::R](R) reader structure"] +impl crate::Readable for WEXCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wexctrl::W](W) writer structure"] +impl crate::Writable for WEXCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WEXCTRL to value 0"] +impl crate::Resettable for WEXCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/wdt.rs b/pac/atsamc20n/src/wdt.rs new file mode 100644 index 000000000000..22b5c2bb706f --- /dev/null +++ b/pac/atsamc20n/src/wdt.rs @@ -0,0 +1,54 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrla: crate::Reg, + #[doc = "0x01 - Configuration"] + pub config: crate::Reg, + #[doc = "0x02 - Early Warning Interrupt Control"] + pub ewctrl: crate::Reg, + _reserved3: [u8; 0x01], + #[doc = "0x04 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x05 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x06 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x08 - Synchronization Busy"] + pub syncbusy: crate::Reg, + #[doc = "0x0c - Clear"] + pub clear: crate::Reg, +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control"] +pub mod ctrla; +#[doc = "CONFIG register accessor: an alias for `Reg`"] +pub type CONFIG = crate::Reg; +#[doc = "Configuration"] +pub mod config; +#[doc = "EWCTRL register accessor: an alias for `Reg`"] +pub type EWCTRL = crate::Reg; +#[doc = "Early Warning Interrupt Control"] +pub mod ewctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Busy"] +pub mod syncbusy; +#[doc = "CLEAR register accessor: an alias for `Reg`"] +pub type CLEAR = crate::Reg; +#[doc = "Clear"] +pub mod clear; diff --git a/pac/atsamc20n/src/wdt/clear.rs b/pac/atsamc20n/src/wdt/clear.rs new file mode 100644 index 000000000000..61ee21f3246a --- /dev/null +++ b/pac/atsamc20n/src/wdt/clear.rs @@ -0,0 +1,85 @@ +#[doc = "Register `CLEAR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Watchdog Clear\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CLEAR_AW { + #[doc = "165: Clear Key"] + KEY = 165, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CLEAR_AW) -> Self { + variant as _ + } +} +#[doc = "Field `CLEAR` writer - Watchdog Clear"] +pub struct CLEAR_W<'a> { + w: &'a mut W, +} +impl<'a> CLEAR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CLEAR_AW) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Clear Key"] + #[inline(always)] + pub fn key(self) -> &'a mut W { + self.variant(CLEAR_AW::KEY) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl W { + #[doc = "Bits 0:7 - Watchdog Clear"] + #[inline(always)] + pub fn clear(&mut self) -> CLEAR_W { + CLEAR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Clear\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clear](index.html) module"] +pub struct CLEAR_SPEC; +impl crate::RegisterSpec for CLEAR_SPEC { + type Ux = u8; +} +#[doc = "`write(|w| ..)` method takes [clear::W](W) writer structure"] +impl crate::Writable for CLEAR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CLEAR to value 0"] +impl crate::Resettable for CLEAR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/wdt/config.rs b/pac/atsamc20n/src/wdt/config.rs new file mode 100644 index 000000000000..c90f062b01f0 --- /dev/null +++ b/pac/atsamc20n/src/wdt/config.rs @@ -0,0 +1,498 @@ +#[doc = "Register `CONFIG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CONFIG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Time-Out Period\n\nValue on reset: 11"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PER_A { + #[doc = "0: 8 clock cycles"] + CYC8 = 0, + #[doc = "1: 16 clock cycles"] + CYC16 = 1, + #[doc = "2: 32 clock cycles"] + CYC32 = 2, + #[doc = "3: 64 clock cycles"] + CYC64 = 3, + #[doc = "4: 128 clock cycles"] + CYC128 = 4, + #[doc = "5: 256 clock cycles"] + CYC256 = 5, + #[doc = "6: 512 clock cycles"] + CYC512 = 6, + #[doc = "7: 1024 clock cycles"] + CYC1024 = 7, + #[doc = "8: 2048 clock cycles"] + CYC2048 = 8, + #[doc = "9: 4096 clock cycles"] + CYC4096 = 9, + #[doc = "10: 8192 clock cycles"] + CYC8192 = 10, + #[doc = "11: 16384 clock cycles"] + CYC16384 = 11, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PER` reader - Time-Out Period"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PER_A::CYC8), + 1 => Some(PER_A::CYC16), + 2 => Some(PER_A::CYC32), + 3 => Some(PER_A::CYC64), + 4 => Some(PER_A::CYC128), + 5 => Some(PER_A::CYC256), + 6 => Some(PER_A::CYC512), + 7 => Some(PER_A::CYC1024), + 8 => Some(PER_A::CYC2048), + 9 => Some(PER_A::CYC4096), + 10 => Some(PER_A::CYC8192), + 11 => Some(PER_A::CYC16384), + _ => None, + } + } + #[doc = "Checks if the value of the field is `CYC8`"] + #[inline(always)] + pub fn is_cyc8(&self) -> bool { + **self == PER_A::CYC8 + } + #[doc = "Checks if the value of the field is `CYC16`"] + #[inline(always)] + pub fn is_cyc16(&self) -> bool { + **self == PER_A::CYC16 + } + #[doc = "Checks if the value of the field is `CYC32`"] + #[inline(always)] + pub fn is_cyc32(&self) -> bool { + **self == PER_A::CYC32 + } + #[doc = "Checks if the value of the field is `CYC64`"] + #[inline(always)] + pub fn is_cyc64(&self) -> bool { + **self == PER_A::CYC64 + } + #[doc = "Checks if the value of the field is `CYC128`"] + #[inline(always)] + pub fn is_cyc128(&self) -> bool { + **self == PER_A::CYC128 + } + #[doc = "Checks if the value of the field is `CYC256`"] + #[inline(always)] + pub fn is_cyc256(&self) -> bool { + **self == PER_A::CYC256 + } + #[doc = "Checks if the value of the field is `CYC512`"] + #[inline(always)] + pub fn is_cyc512(&self) -> bool { + **self == PER_A::CYC512 + } + #[doc = "Checks if the value of the field is `CYC1024`"] + #[inline(always)] + pub fn is_cyc1024(&self) -> bool { + **self == PER_A::CYC1024 + } + #[doc = "Checks if the value of the field is `CYC2048`"] + #[inline(always)] + pub fn is_cyc2048(&self) -> bool { + **self == PER_A::CYC2048 + } + #[doc = "Checks if the value of the field is `CYC4096`"] + #[inline(always)] + pub fn is_cyc4096(&self) -> bool { + **self == PER_A::CYC4096 + } + #[doc = "Checks if the value of the field is `CYC8192`"] + #[inline(always)] + pub fn is_cyc8192(&self) -> bool { + **self == PER_A::CYC8192 + } + #[doc = "Checks if the value of the field is `CYC16384`"] + #[inline(always)] + pub fn is_cyc16384(&self) -> bool { + **self == PER_A::CYC16384 + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` writer - Time-Out Period"] +pub struct PER_W<'a> { + w: &'a mut W, +} +impl<'a> PER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PER_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8 clock cycles"] + #[inline(always)] + pub fn cyc8(self) -> &'a mut W { + self.variant(PER_A::CYC8) + } + #[doc = "16 clock cycles"] + #[inline(always)] + pub fn cyc16(self) -> &'a mut W { + self.variant(PER_A::CYC16) + } + #[doc = "32 clock cycles"] + #[inline(always)] + pub fn cyc32(self) -> &'a mut W { + self.variant(PER_A::CYC32) + } + #[doc = "64 clock cycles"] + #[inline(always)] + pub fn cyc64(self) -> &'a mut W { + self.variant(PER_A::CYC64) + } + #[doc = "128 clock cycles"] + #[inline(always)] + pub fn cyc128(self) -> &'a mut W { + self.variant(PER_A::CYC128) + } + #[doc = "256 clock cycles"] + #[inline(always)] + pub fn cyc256(self) -> &'a mut W { + self.variant(PER_A::CYC256) + } + #[doc = "512 clock cycles"] + #[inline(always)] + pub fn cyc512(self) -> &'a mut W { + self.variant(PER_A::CYC512) + } + #[doc = "1024 clock cycles"] + #[inline(always)] + pub fn cyc1024(self) -> &'a mut W { + self.variant(PER_A::CYC1024) + } + #[doc = "2048 clock cycles"] + #[inline(always)] + pub fn cyc2048(self) -> &'a mut W { + self.variant(PER_A::CYC2048) + } + #[doc = "4096 clock cycles"] + #[inline(always)] + pub fn cyc4096(self) -> &'a mut W { + self.variant(PER_A::CYC4096) + } + #[doc = "8192 clock cycles"] + #[inline(always)] + pub fn cyc8192(self) -> &'a mut W { + self.variant(PER_A::CYC8192) + } + #[doc = "16384 clock cycles"] + #[inline(always)] + pub fn cyc16384(self) -> &'a mut W { + self.variant(PER_A::CYC16384) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +#[doc = "Window Mode Time-Out Period\n\nValue on reset: 11"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WINDOW_A { + #[doc = "0: 8 clock cycles"] + CYC8 = 0, + #[doc = "1: 16 clock cycles"] + CYC16 = 1, + #[doc = "2: 32 clock cycles"] + CYC32 = 2, + #[doc = "3: 64 clock cycles"] + CYC64 = 3, + #[doc = "4: 128 clock cycles"] + CYC128 = 4, + #[doc = "5: 256 clock cycles"] + CYC256 = 5, + #[doc = "6: 512 clock cycles"] + CYC512 = 6, + #[doc = "7: 1024 clock cycles"] + CYC1024 = 7, + #[doc = "8: 2048 clock cycles"] + CYC2048 = 8, + #[doc = "9: 4096 clock cycles"] + CYC4096 = 9, + #[doc = "10: 8192 clock cycles"] + CYC8192 = 10, + #[doc = "11: 16384 clock cycles"] + CYC16384 = 11, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WINDOW_A) -> Self { + variant as _ + } +} +#[doc = "Field `WINDOW` reader - Window Mode Time-Out Period"] +pub struct WINDOW_R(crate::FieldReader); +impl WINDOW_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WINDOW_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(WINDOW_A::CYC8), + 1 => Some(WINDOW_A::CYC16), + 2 => Some(WINDOW_A::CYC32), + 3 => Some(WINDOW_A::CYC64), + 4 => Some(WINDOW_A::CYC128), + 5 => Some(WINDOW_A::CYC256), + 6 => Some(WINDOW_A::CYC512), + 7 => Some(WINDOW_A::CYC1024), + 8 => Some(WINDOW_A::CYC2048), + 9 => Some(WINDOW_A::CYC4096), + 10 => Some(WINDOW_A::CYC8192), + 11 => Some(WINDOW_A::CYC16384), + _ => None, + } + } + #[doc = "Checks if the value of the field is `CYC8`"] + #[inline(always)] + pub fn is_cyc8(&self) -> bool { + **self == WINDOW_A::CYC8 + } + #[doc = "Checks if the value of the field is `CYC16`"] + #[inline(always)] + pub fn is_cyc16(&self) -> bool { + **self == WINDOW_A::CYC16 + } + #[doc = "Checks if the value of the field is `CYC32`"] + #[inline(always)] + pub fn is_cyc32(&self) -> bool { + **self == WINDOW_A::CYC32 + } + #[doc = "Checks if the value of the field is `CYC64`"] + #[inline(always)] + pub fn is_cyc64(&self) -> bool { + **self == WINDOW_A::CYC64 + } + #[doc = "Checks if the value of the field is `CYC128`"] + #[inline(always)] + pub fn is_cyc128(&self) -> bool { + **self == WINDOW_A::CYC128 + } + #[doc = "Checks if the value of the field is `CYC256`"] + #[inline(always)] + pub fn is_cyc256(&self) -> bool { + **self == WINDOW_A::CYC256 + } + #[doc = "Checks if the value of the field is `CYC512`"] + #[inline(always)] + pub fn is_cyc512(&self) -> bool { + **self == WINDOW_A::CYC512 + } + #[doc = "Checks if the value of the field is `CYC1024`"] + #[inline(always)] + pub fn is_cyc1024(&self) -> bool { + **self == WINDOW_A::CYC1024 + } + #[doc = "Checks if the value of the field is `CYC2048`"] + #[inline(always)] + pub fn is_cyc2048(&self) -> bool { + **self == WINDOW_A::CYC2048 + } + #[doc = "Checks if the value of the field is `CYC4096`"] + #[inline(always)] + pub fn is_cyc4096(&self) -> bool { + **self == WINDOW_A::CYC4096 + } + #[doc = "Checks if the value of the field is `CYC8192`"] + #[inline(always)] + pub fn is_cyc8192(&self) -> bool { + **self == WINDOW_A::CYC8192 + } + #[doc = "Checks if the value of the field is `CYC16384`"] + #[inline(always)] + pub fn is_cyc16384(&self) -> bool { + **self == WINDOW_A::CYC16384 + } +} +impl core::ops::Deref for WINDOW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINDOW` writer - Window Mode Time-Out Period"] +pub struct WINDOW_W<'a> { + w: &'a mut W, +} +impl<'a> WINDOW_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WINDOW_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8 clock cycles"] + #[inline(always)] + pub fn cyc8(self) -> &'a mut W { + self.variant(WINDOW_A::CYC8) + } + #[doc = "16 clock cycles"] + #[inline(always)] + pub fn cyc16(self) -> &'a mut W { + self.variant(WINDOW_A::CYC16) + } + #[doc = "32 clock cycles"] + #[inline(always)] + pub fn cyc32(self) -> &'a mut W { + self.variant(WINDOW_A::CYC32) + } + #[doc = "64 clock cycles"] + #[inline(always)] + pub fn cyc64(self) -> &'a mut W { + self.variant(WINDOW_A::CYC64) + } + #[doc = "128 clock cycles"] + #[inline(always)] + pub fn cyc128(self) -> &'a mut W { + self.variant(WINDOW_A::CYC128) + } + #[doc = "256 clock cycles"] + #[inline(always)] + pub fn cyc256(self) -> &'a mut W { + self.variant(WINDOW_A::CYC256) + } + #[doc = "512 clock cycles"] + #[inline(always)] + pub fn cyc512(self) -> &'a mut W { + self.variant(WINDOW_A::CYC512) + } + #[doc = "1024 clock cycles"] + #[inline(always)] + pub fn cyc1024(self) -> &'a mut W { + self.variant(WINDOW_A::CYC1024) + } + #[doc = "2048 clock cycles"] + #[inline(always)] + pub fn cyc2048(self) -> &'a mut W { + self.variant(WINDOW_A::CYC2048) + } + #[doc = "4096 clock cycles"] + #[inline(always)] + pub fn cyc4096(self) -> &'a mut W { + self.variant(WINDOW_A::CYC4096) + } + #[doc = "8192 clock cycles"] + #[inline(always)] + pub fn cyc8192(self) -> &'a mut W { + self.variant(WINDOW_A::CYC8192) + } + #[doc = "16384 clock cycles"] + #[inline(always)] + pub fn cyc16384(self) -> &'a mut W { + self.variant(WINDOW_A::CYC16384) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 4)) | ((value as u8 & 0x0f) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Time-Out Period"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Window Mode Time-Out Period"] + #[inline(always)] + pub fn window(&self) -> WINDOW_R { + WINDOW_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Time-Out Period"] + #[inline(always)] + pub fn per(&mut self) -> PER_W { + PER_W { w: self } + } + #[doc = "Bits 4:7 - Window Mode Time-Out Period"] + #[inline(always)] + pub fn window(&mut self) -> WINDOW_W { + WINDOW_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [config](index.html) module"] +pub struct CONFIG_SPEC; +impl crate::RegisterSpec for CONFIG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [config::R](R) reader structure"] +impl crate::Readable for CONFIG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [config::W](W) writer structure"] +impl crate::Writable for CONFIG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CONFIG to value 0xbb"] +impl crate::Resettable for CONFIG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xbb + } +} diff --git a/pac/atsamc20n/src/wdt/ctrla.rs b/pac/atsamc20n/src/wdt/ctrla.rs new file mode 100644 index 000000000000..895169d36aeb --- /dev/null +++ b/pac/atsamc20n/src/wdt/ctrla.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WEN` reader - Watchdog Timer Window Mode Enable"] +pub struct WEN_R(crate::FieldReader); +impl WEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WEN` writer - Watchdog Timer Window Mode Enable"] +pub struct WEN_W<'a> { + w: &'a mut W, +} +impl<'a> WEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `ALWAYSON` reader - Always-On"] +pub struct ALWAYSON_R(crate::FieldReader); +impl ALWAYSON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALWAYSON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALWAYSON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALWAYSON` writer - Always-On"] +pub struct ALWAYSON_W<'a> { + w: &'a mut W, +} +impl<'a> ALWAYSON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Watchdog Timer Window Mode Enable"] + #[inline(always)] + pub fn wen(&self) -> WEN_R { + WEN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 7 - Always-On"] + #[inline(always)] + pub fn alwayson(&self) -> ALWAYSON_R { + ALWAYSON_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - Watchdog Timer Window Mode Enable"] + #[inline(always)] + pub fn wen(&mut self) -> WEN_W { + WEN_W { w: self } + } + #[doc = "Bit 7 - Always-On"] + #[inline(always)] + pub fn alwayson(&mut self) -> ALWAYSON_W { + ALWAYSON_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/wdt/ewctrl.rs b/pac/atsamc20n/src/wdt/ewctrl.rs new file mode 100644 index 000000000000..94542e9897a9 --- /dev/null +++ b/pac/atsamc20n/src/wdt/ewctrl.rs @@ -0,0 +1,282 @@ +#[doc = "Register `EWCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EWCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Early Warning Interrupt Time Offset\n\nValue on reset: 11"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EWOFFSET_A { + #[doc = "0: 8 clock cycles"] + CYC8 = 0, + #[doc = "1: 16 clock cycles"] + CYC16 = 1, + #[doc = "2: 32 clock cycles"] + CYC32 = 2, + #[doc = "3: 64 clock cycles"] + CYC64 = 3, + #[doc = "4: 128 clock cycles"] + CYC128 = 4, + #[doc = "5: 256 clock cycles"] + CYC256 = 5, + #[doc = "6: 512 clock cycles"] + CYC512 = 6, + #[doc = "7: 1024 clock cycles"] + CYC1024 = 7, + #[doc = "8: 2048 clock cycles"] + CYC2048 = 8, + #[doc = "9: 4096 clock cycles"] + CYC4096 = 9, + #[doc = "10: 8192 clock cycles"] + CYC8192 = 10, + #[doc = "11: 16384 clock cycles"] + CYC16384 = 11, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EWOFFSET_A) -> Self { + variant as _ + } +} +#[doc = "Field `EWOFFSET` reader - Early Warning Interrupt Time Offset"] +pub struct EWOFFSET_R(crate::FieldReader); +impl EWOFFSET_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EWOFFSET_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(EWOFFSET_A::CYC8), + 1 => Some(EWOFFSET_A::CYC16), + 2 => Some(EWOFFSET_A::CYC32), + 3 => Some(EWOFFSET_A::CYC64), + 4 => Some(EWOFFSET_A::CYC128), + 5 => Some(EWOFFSET_A::CYC256), + 6 => Some(EWOFFSET_A::CYC512), + 7 => Some(EWOFFSET_A::CYC1024), + 8 => Some(EWOFFSET_A::CYC2048), + 9 => Some(EWOFFSET_A::CYC4096), + 10 => Some(EWOFFSET_A::CYC8192), + 11 => Some(EWOFFSET_A::CYC16384), + _ => None, + } + } + #[doc = "Checks if the value of the field is `CYC8`"] + #[inline(always)] + pub fn is_cyc8(&self) -> bool { + **self == EWOFFSET_A::CYC8 + } + #[doc = "Checks if the value of the field is `CYC16`"] + #[inline(always)] + pub fn is_cyc16(&self) -> bool { + **self == EWOFFSET_A::CYC16 + } + #[doc = "Checks if the value of the field is `CYC32`"] + #[inline(always)] + pub fn is_cyc32(&self) -> bool { + **self == EWOFFSET_A::CYC32 + } + #[doc = "Checks if the value of the field is `CYC64`"] + #[inline(always)] + pub fn is_cyc64(&self) -> bool { + **self == EWOFFSET_A::CYC64 + } + #[doc = "Checks if the value of the field is `CYC128`"] + #[inline(always)] + pub fn is_cyc128(&self) -> bool { + **self == EWOFFSET_A::CYC128 + } + #[doc = "Checks if the value of the field is `CYC256`"] + #[inline(always)] + pub fn is_cyc256(&self) -> bool { + **self == EWOFFSET_A::CYC256 + } + #[doc = "Checks if the value of the field is `CYC512`"] + #[inline(always)] + pub fn is_cyc512(&self) -> bool { + **self == EWOFFSET_A::CYC512 + } + #[doc = "Checks if the value of the field is `CYC1024`"] + #[inline(always)] + pub fn is_cyc1024(&self) -> bool { + **self == EWOFFSET_A::CYC1024 + } + #[doc = "Checks if the value of the field is `CYC2048`"] + #[inline(always)] + pub fn is_cyc2048(&self) -> bool { + **self == EWOFFSET_A::CYC2048 + } + #[doc = "Checks if the value of the field is `CYC4096`"] + #[inline(always)] + pub fn is_cyc4096(&self) -> bool { + **self == EWOFFSET_A::CYC4096 + } + #[doc = "Checks if the value of the field is `CYC8192`"] + #[inline(always)] + pub fn is_cyc8192(&self) -> bool { + **self == EWOFFSET_A::CYC8192 + } + #[doc = "Checks if the value of the field is `CYC16384`"] + #[inline(always)] + pub fn is_cyc16384(&self) -> bool { + **self == EWOFFSET_A::CYC16384 + } +} +impl core::ops::Deref for EWOFFSET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EWOFFSET` writer - Early Warning Interrupt Time Offset"] +pub struct EWOFFSET_W<'a> { + w: &'a mut W, +} +impl<'a> EWOFFSET_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EWOFFSET_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8 clock cycles"] + #[inline(always)] + pub fn cyc8(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC8) + } + #[doc = "16 clock cycles"] + #[inline(always)] + pub fn cyc16(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC16) + } + #[doc = "32 clock cycles"] + #[inline(always)] + pub fn cyc32(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC32) + } + #[doc = "64 clock cycles"] + #[inline(always)] + pub fn cyc64(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC64) + } + #[doc = "128 clock cycles"] + #[inline(always)] + pub fn cyc128(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC128) + } + #[doc = "256 clock cycles"] + #[inline(always)] + pub fn cyc256(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC256) + } + #[doc = "512 clock cycles"] + #[inline(always)] + pub fn cyc512(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC512) + } + #[doc = "1024 clock cycles"] + #[inline(always)] + pub fn cyc1024(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC1024) + } + #[doc = "2048 clock cycles"] + #[inline(always)] + pub fn cyc2048(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC2048) + } + #[doc = "4096 clock cycles"] + #[inline(always)] + pub fn cyc4096(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC4096) + } + #[doc = "8192 clock cycles"] + #[inline(always)] + pub fn cyc8192(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC8192) + } + #[doc = "16384 clock cycles"] + #[inline(always)] + pub fn cyc16384(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC16384) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Early Warning Interrupt Time Offset"] + #[inline(always)] + pub fn ewoffset(&self) -> EWOFFSET_R { + EWOFFSET_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Early Warning Interrupt Time Offset"] + #[inline(always)] + pub fn ewoffset(&mut self) -> EWOFFSET_W { + EWOFFSET_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Early Warning Interrupt Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ewctrl](index.html) module"] +pub struct EWCTRL_SPEC; +impl crate::RegisterSpec for EWCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ewctrl::R](R) reader structure"] +impl crate::Readable for EWCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ewctrl::W](W) writer structure"] +impl crate::Writable for EWCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EWCTRL to value 0x0b"] +impl crate::Resettable for EWCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0b + } +} diff --git a/pac/atsamc20n/src/wdt/intenclr.rs b/pac/atsamc20n/src/wdt/intenclr.rs new file mode 100644 index 000000000000..ed4021f96cce --- /dev/null +++ b/pac/atsamc20n/src/wdt/intenclr.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EW` reader - Early Warning Interrupt Enable"] +pub struct EW_R(crate::FieldReader); +impl EW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EW` writer - Early Warning Interrupt Enable"] +pub struct EW_W<'a> { + w: &'a mut W, +} +impl<'a> EW_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Early Warning Interrupt Enable"] + #[inline(always)] + pub fn ew(&self) -> EW_R { + EW_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Early Warning Interrupt Enable"] + #[inline(always)] + pub fn ew(&mut self) -> EW_W { + EW_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/wdt/intenset.rs b/pac/atsamc20n/src/wdt/intenset.rs new file mode 100644 index 000000000000..5a0928ff0532 --- /dev/null +++ b/pac/atsamc20n/src/wdt/intenset.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EW` reader - Early Warning Interrupt Enable"] +pub struct EW_R(crate::FieldReader); +impl EW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EW` writer - Early Warning Interrupt Enable"] +pub struct EW_W<'a> { + w: &'a mut W, +} +impl<'a> EW_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Early Warning Interrupt Enable"] + #[inline(always)] + pub fn ew(&self) -> EW_R { + EW_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Early Warning Interrupt Enable"] + #[inline(always)] + pub fn ew(&mut self) -> EW_W { + EW_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/wdt/intflag.rs b/pac/atsamc20n/src/wdt/intflag.rs new file mode 100644 index 000000000000..f2c9b858a199 --- /dev/null +++ b/pac/atsamc20n/src/wdt/intflag.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EW` reader - Early Warning"] +pub struct EW_R(crate::FieldReader); +impl EW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EW` writer - Early Warning"] +pub struct EW_W<'a> { + w: &'a mut W, +} +impl<'a> EW_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Early Warning"] + #[inline(always)] + pub fn ew(&self) -> EW_R { + EW_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Early Warning"] + #[inline(always)] + pub fn ew(&mut self) -> EW_W { + EW_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc20n/src/wdt/syncbusy.rs b/pac/atsamc20n/src/wdt/syncbusy.rs new file mode 100644 index 000000000000..a3ecf7fbdb8a --- /dev/null +++ b/pac/atsamc20n/src/wdt/syncbusy.rs @@ -0,0 +1,113 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `ENABLE` reader - Enable Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WEN` reader - Window Enable Busy"] +pub struct WEN_R(crate::FieldReader); +impl WEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALWAYSON` reader - Always-On Busy"] +pub struct ALWAYSON_R(crate::FieldReader); +impl ALWAYSON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALWAYSON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALWAYSON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLEAR` reader - Clear Busy"] +pub struct CLEAR_R(crate::FieldReader); +impl CLEAR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLEAR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLEAR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 1 - Enable Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Window Enable Busy"] + #[inline(always)] + pub fn wen(&self) -> WEN_R { + WEN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Always-On Busy"] + #[inline(always)] + pub fn alwayson(&self) -> ALWAYSON_R { + ALWAYSON_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Clear Busy"] + #[inline(always)] + pub fn clear(&self) -> CLEAR_R { + CLEAR_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +#[doc = "Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/CHANGELOG.md b/pac/atsamc21e/CHANGELOG.md new file mode 100644 index 000000000000..e28d85f63b31 --- /dev/null +++ b/pac/atsamc21e/CHANGELOG.md @@ -0,0 +1,6 @@ +# Unreleased + +- Initial version +--- + +Changelog tracking started at v0.0.1 diff --git a/pac/atsamc21e/Cargo.toml b/pac/atsamc21e/Cargo.toml new file mode 100644 index 000000000000..bbb8c65fa361 --- /dev/null +++ b/pac/atsamc21e/Cargo.toml @@ -0,0 +1,22 @@ +[package] +name = "atsamc21e" +description = "Peripheral access API for ATSAMC21E microcontrollers (generated using svd2rust)" +version = "0.0.1" +authors = ["Jeremy Boynes "] +keywords = ["no-std", "arm", "cortex-m"] +categories = ["embedded", "hardware-support", "no-std"] +license = "MIT OR Apache-2.0" +repository = "https://github.com/atsamd-rs/atsamd" +readme = "README.md" +edition = "2021" + +[dependencies] +cortex-m = "0.7" +vcell = "0.1" + +[dependencies.cortex-m-rt] +version = "0.7" +optional = true + +[features] +rt = ["cortex-m-rt/device"] diff --git a/pac/atsamc21e/README.md b/pac/atsamc21e/README.md new file mode 100644 index 000000000000..87e751cedbce --- /dev/null +++ b/pac/atsamc21e/README.md @@ -0,0 +1,26 @@ +# ATSAMC21E + +A peripheral access crate for the ATSAMC21E chip from Microchip (née Atmel) for Rust Embedded projects. + +[![Build Status](https://travis-ci.org/atsamd-rs/atsamd.svg?branch=master)](https://travis-ci.org/atsamd-rs/atsamd) +[![Crates.io](https://img.shields.io/crates/v/atsamc21e.svg)](https://crates.io/crates/atsamc21e) + +## [Documentation](https://docs.rs/atsamc21e) + +This source was automatically generated using `svd2rust`, split into smaller pieces using `form` and formatted via `rustfmt`. + +## License + +Licensed under either of: + +- Apache License, Version 2.0 ([LICENSE-APACHE](https://github.com/atsamd-rs/atsamd/blob/master/LICENSE-APACHE) or + http://www.apache.org/licenses/LICENSE-2.0) +- MIT license ([LICENSE-MIT](https://github.com/atsamd-rs/atsamd/blob/master/LICENSE-MIT) or http://opensource.org/licenses/MIT) + +at your option. + +### Contribution + +Unless you explicitly state otherwise, any contribution intentionally submitted +for inclusion in the work by you, as defined in the Apache-2.0 license, shall +be dual licensed as above, without any additional terms or conditions. diff --git a/pac/atsamc21e/build.rs b/pac/atsamc21e/build.rs new file mode 100644 index 000000000000..597923f50892 --- /dev/null +++ b/pac/atsamc21e/build.rs @@ -0,0 +1,16 @@ +use std::env; +use std::fs::File; +use std::io::Write; +use std::path::PathBuf; +fn main() { + if env::var_os("CARGO_FEATURE_RT").is_some() { + let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap()); + File::create(out.join("device.x")) + .unwrap() + .write_all(include_bytes!("device.x")) + .unwrap(); + println!("cargo:rustc-link-search={}", out.display()); + println!("cargo:rerun-if-changed=device.x"); + } + println!("cargo:rerun-if-changed=build.rs"); +} diff --git a/pac/atsamc21e/device.x b/pac/atsamc21e/device.x new file mode 100644 index 000000000000..203ad24edbea --- /dev/null +++ b/pac/atsamc21e/device.x @@ -0,0 +1,28 @@ +PROVIDE(WDT = DefaultHandler); +PROVIDE(RTC = DefaultHandler); +PROVIDE(EIC = DefaultHandler); +PROVIDE(FREQM = DefaultHandler); +PROVIDE(TSENS = DefaultHandler); +PROVIDE(NVMCTRL = DefaultHandler); +PROVIDE(DMAC = DefaultHandler); +PROVIDE(EVSYS = DefaultHandler); +PROVIDE(SERCOM0 = DefaultHandler); +PROVIDE(SERCOM1 = DefaultHandler); +PROVIDE(SERCOM2 = DefaultHandler); +PROVIDE(SERCOM3 = DefaultHandler); +PROVIDE(CAN0 = DefaultHandler); +PROVIDE(TCC0 = DefaultHandler); +PROVIDE(TCC1 = DefaultHandler); +PROVIDE(TCC2 = DefaultHandler); +PROVIDE(TC0 = DefaultHandler); +PROVIDE(TC1 = DefaultHandler); +PROVIDE(TC2 = DefaultHandler); +PROVIDE(TC3 = DefaultHandler); +PROVIDE(TC4 = DefaultHandler); +PROVIDE(ADC0 = DefaultHandler); +PROVIDE(ADC1 = DefaultHandler); +PROVIDE(AC = DefaultHandler); +PROVIDE(DAC = DefaultHandler); +PROVIDE(SDADC = DefaultHandler); +PROVIDE(PTC = DefaultHandler); + diff --git a/pac/atsamc21e/src/ac.rs b/pac/atsamc21e/src/ac.rs new file mode 100644 index 000000000000..b66620475572 --- /dev/null +++ b/pac/atsamc21e/src/ac.rs @@ -0,0 +1,83 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + #[doc = "0x01 - Control B"] + pub ctrlb: crate::Reg, + #[doc = "0x02 - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x04 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x05 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x06 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x07 - Status A"] + pub statusa: crate::Reg, + #[doc = "0x08 - Status B"] + pub statusb: crate::Reg, + #[doc = "0x09 - Debug Control"] + pub dbgctrl: crate::Reg, + #[doc = "0x0a - Window Control"] + pub winctrl: crate::Reg, + _reserved10: [u8; 0x01], + #[doc = "0x0c - Scaler n"] + pub scaler: [crate::Reg; 4], + #[doc = "0x10..0x20 - Comparator Control n"] + pub compctrl: [crate::Reg; 4], + #[doc = "0x20 - Synchronization Busy"] + pub syncbusy: crate::Reg, +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "Control B"] +pub mod ctrlb; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUSA register accessor: an alias for `Reg`"] +pub type STATUSA = crate::Reg; +#[doc = "Status A"] +pub mod statusa; +#[doc = "STATUSB register accessor: an alias for `Reg`"] +pub type STATUSB = crate::Reg; +#[doc = "Status B"] +pub mod statusb; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "WINCTRL register accessor: an alias for `Reg`"] +pub type WINCTRL = crate::Reg; +#[doc = "Window Control"] +pub mod winctrl; +#[doc = "SCALER register accessor: an alias for `Reg`"] +pub type SCALER = crate::Reg; +#[doc = "Scaler n"] +pub mod scaler; +#[doc = "COMPCTRL register accessor: an alias for `Reg`"] +pub type COMPCTRL = crate::Reg; +#[doc = "Comparator Control n"] +pub mod compctrl; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Busy"] +pub mod syncbusy; diff --git a/pac/atsamc21e/src/ac/compctrl.rs b/pac/atsamc21e/src/ac/compctrl.rs new file mode 100644 index 000000000000..791525fd7407 --- /dev/null +++ b/pac/atsamc21e/src/ac/compctrl.rs @@ -0,0 +1,987 @@ +#[doc = "Register `COMPCTRL[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COMPCTRL[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SINGLE` reader - Single-Shot Mode"] +pub struct SINGLE_R(crate::FieldReader); +impl SINGLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SINGLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SINGLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SINGLE` writer - Single-Shot Mode"] +pub struct SINGLE_W<'a> { + w: &'a mut W, +} +impl<'a> SINGLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Interrupt Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum INTSEL_A { + #[doc = "0: Interrupt on comparator output toggle"] + TOGGLE = 0, + #[doc = "1: Interrupt on comparator output rising"] + RISING = 1, + #[doc = "2: Interrupt on comparator output falling"] + FALLING = 2, + #[doc = "3: Interrupt on end of comparison (single-shot mode only)"] + EOC = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: INTSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `INTSEL` reader - Interrupt Selection"] +pub struct INTSEL_R(crate::FieldReader); +impl INTSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + INTSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INTSEL_A { + match self.bits { + 0 => INTSEL_A::TOGGLE, + 1 => INTSEL_A::RISING, + 2 => INTSEL_A::FALLING, + 3 => INTSEL_A::EOC, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `TOGGLE`"] + #[inline(always)] + pub fn is_toggle(&self) -> bool { + **self == INTSEL_A::TOGGLE + } + #[doc = "Checks if the value of the field is `RISING`"] + #[inline(always)] + pub fn is_rising(&self) -> bool { + **self == INTSEL_A::RISING + } + #[doc = "Checks if the value of the field is `FALLING`"] + #[inline(always)] + pub fn is_falling(&self) -> bool { + **self == INTSEL_A::FALLING + } + #[doc = "Checks if the value of the field is `EOC`"] + #[inline(always)] + pub fn is_eoc(&self) -> bool { + **self == INTSEL_A::EOC + } +} +impl core::ops::Deref for INTSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INTSEL` writer - Interrupt Selection"] +pub struct INTSEL_W<'a> { + w: &'a mut W, +} +impl<'a> INTSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: INTSEL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Interrupt on comparator output toggle"] + #[inline(always)] + pub fn toggle(self) -> &'a mut W { + self.variant(INTSEL_A::TOGGLE) + } + #[doc = "Interrupt on comparator output rising"] + #[inline(always)] + pub fn rising(self) -> &'a mut W { + self.variant(INTSEL_A::RISING) + } + #[doc = "Interrupt on comparator output falling"] + #[inline(always)] + pub fn falling(self) -> &'a mut W { + self.variant(INTSEL_A::FALLING) + } + #[doc = "Interrupt on end of comparison (single-shot mode only)"] + #[inline(always)] + pub fn eoc(self) -> &'a mut W { + self.variant(INTSEL_A::EOC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 3)) | ((value as u32 & 0x03) << 3); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Negative Input Mux Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MUXNEG_A { + #[doc = "0: I/O pin 0"] + PIN0 = 0, + #[doc = "1: I/O pin 1"] + PIN1 = 1, + #[doc = "2: I/O pin 2"] + PIN2 = 2, + #[doc = "3: I/O pin 3"] + PIN3 = 3, + #[doc = "4: Ground"] + GND = 4, + #[doc = "5: VDD scaler"] + VSCALE = 5, + #[doc = "6: Internal bandgap voltage"] + BANDGAP = 6, + #[doc = "7: DAC output"] + DAC = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MUXNEG_A) -> Self { + variant as _ + } +} +#[doc = "Field `MUXNEG` reader - Negative Input Mux Selection"] +pub struct MUXNEG_R(crate::FieldReader); +impl MUXNEG_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MUXNEG_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> MUXNEG_A { + match self.bits { + 0 => MUXNEG_A::PIN0, + 1 => MUXNEG_A::PIN1, + 2 => MUXNEG_A::PIN2, + 3 => MUXNEG_A::PIN3, + 4 => MUXNEG_A::GND, + 5 => MUXNEG_A::VSCALE, + 6 => MUXNEG_A::BANDGAP, + 7 => MUXNEG_A::DAC, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `PIN0`"] + #[inline(always)] + pub fn is_pin0(&self) -> bool { + **self == MUXNEG_A::PIN0 + } + #[doc = "Checks if the value of the field is `PIN1`"] + #[inline(always)] + pub fn is_pin1(&self) -> bool { + **self == MUXNEG_A::PIN1 + } + #[doc = "Checks if the value of the field is `PIN2`"] + #[inline(always)] + pub fn is_pin2(&self) -> bool { + **self == MUXNEG_A::PIN2 + } + #[doc = "Checks if the value of the field is `PIN3`"] + #[inline(always)] + pub fn is_pin3(&self) -> bool { + **self == MUXNEG_A::PIN3 + } + #[doc = "Checks if the value of the field is `GND`"] + #[inline(always)] + pub fn is_gnd(&self) -> bool { + **self == MUXNEG_A::GND + } + #[doc = "Checks if the value of the field is `VSCALE`"] + #[inline(always)] + pub fn is_vscale(&self) -> bool { + **self == MUXNEG_A::VSCALE + } + #[doc = "Checks if the value of the field is `BANDGAP`"] + #[inline(always)] + pub fn is_bandgap(&self) -> bool { + **self == MUXNEG_A::BANDGAP + } + #[doc = "Checks if the value of the field is `DAC`"] + #[inline(always)] + pub fn is_dac(&self) -> bool { + **self == MUXNEG_A::DAC + } +} +impl core::ops::Deref for MUXNEG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MUXNEG` writer - Negative Input Mux Selection"] +pub struct MUXNEG_W<'a> { + w: &'a mut W, +} +impl<'a> MUXNEG_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MUXNEG_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "I/O pin 0"] + #[inline(always)] + pub fn pin0(self) -> &'a mut W { + self.variant(MUXNEG_A::PIN0) + } + #[doc = "I/O pin 1"] + #[inline(always)] + pub fn pin1(self) -> &'a mut W { + self.variant(MUXNEG_A::PIN1) + } + #[doc = "I/O pin 2"] + #[inline(always)] + pub fn pin2(self) -> &'a mut W { + self.variant(MUXNEG_A::PIN2) + } + #[doc = "I/O pin 3"] + #[inline(always)] + pub fn pin3(self) -> &'a mut W { + self.variant(MUXNEG_A::PIN3) + } + #[doc = "Ground"] + #[inline(always)] + pub fn gnd(self) -> &'a mut W { + self.variant(MUXNEG_A::GND) + } + #[doc = "VDD scaler"] + #[inline(always)] + pub fn vscale(self) -> &'a mut W { + self.variant(MUXNEG_A::VSCALE) + } + #[doc = "Internal bandgap voltage"] + #[inline(always)] + pub fn bandgap(self) -> &'a mut W { + self.variant(MUXNEG_A::BANDGAP) + } + #[doc = "DAC output"] + #[inline(always)] + pub fn dac(self) -> &'a mut W { + self.variant(MUXNEG_A::DAC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +#[doc = "Positive Input Mux Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MUXPOS_A { + #[doc = "0: I/O pin 0"] + PIN0 = 0, + #[doc = "1: I/O pin 1"] + PIN1 = 1, + #[doc = "2: I/O pin 2"] + PIN2 = 2, + #[doc = "3: I/O pin 3"] + PIN3 = 3, + #[doc = "4: VDD Scaler"] + VSCALE = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MUXPOS_A) -> Self { + variant as _ + } +} +#[doc = "Field `MUXPOS` reader - Positive Input Mux Selection"] +pub struct MUXPOS_R(crate::FieldReader); +impl MUXPOS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MUXPOS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MUXPOS_A::PIN0), + 1 => Some(MUXPOS_A::PIN1), + 2 => Some(MUXPOS_A::PIN2), + 3 => Some(MUXPOS_A::PIN3), + 4 => Some(MUXPOS_A::VSCALE), + _ => None, + } + } + #[doc = "Checks if the value of the field is `PIN0`"] + #[inline(always)] + pub fn is_pin0(&self) -> bool { + **self == MUXPOS_A::PIN0 + } + #[doc = "Checks if the value of the field is `PIN1`"] + #[inline(always)] + pub fn is_pin1(&self) -> bool { + **self == MUXPOS_A::PIN1 + } + #[doc = "Checks if the value of the field is `PIN2`"] + #[inline(always)] + pub fn is_pin2(&self) -> bool { + **self == MUXPOS_A::PIN2 + } + #[doc = "Checks if the value of the field is `PIN3`"] + #[inline(always)] + pub fn is_pin3(&self) -> bool { + **self == MUXPOS_A::PIN3 + } + #[doc = "Checks if the value of the field is `VSCALE`"] + #[inline(always)] + pub fn is_vscale(&self) -> bool { + **self == MUXPOS_A::VSCALE + } +} +impl core::ops::Deref for MUXPOS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MUXPOS` writer - Positive Input Mux Selection"] +pub struct MUXPOS_W<'a> { + w: &'a mut W, +} +impl<'a> MUXPOS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MUXPOS_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "I/O pin 0"] + #[inline(always)] + pub fn pin0(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN0) + } + #[doc = "I/O pin 1"] + #[inline(always)] + pub fn pin1(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN1) + } + #[doc = "I/O pin 2"] + #[inline(always)] + pub fn pin2(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN2) + } + #[doc = "I/O pin 3"] + #[inline(always)] + pub fn pin3(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN3) + } + #[doc = "VDD Scaler"] + #[inline(always)] + pub fn vscale(self) -> &'a mut W { + self.variant(MUXPOS_A::VSCALE) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 12)) | ((value as u32 & 0x07) << 12); + self.w + } +} +#[doc = "Field `SWAP` reader - Swap Inputs and Invert"] +pub struct SWAP_R(crate::FieldReader); +impl SWAP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWAP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWAP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWAP` writer - Swap Inputs and Invert"] +pub struct SWAP_W<'a> { + w: &'a mut W, +} +impl<'a> SWAP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Speed Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SPEED_A { + #[doc = "0: Low speed"] + LOW = 0, + #[doc = "3: High speed"] + HIGH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SPEED_A) -> Self { + variant as _ + } +} +#[doc = "Field `SPEED` reader - Speed Selection"] +pub struct SPEED_R(crate::FieldReader); +impl SPEED_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SPEED_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SPEED_A::LOW), + 3 => Some(SPEED_A::HIGH), + _ => None, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SPEED_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SPEED_A::HIGH + } +} +impl core::ops::Deref for SPEED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SPEED` writer - Speed Selection"] +pub struct SPEED_W<'a> { + w: &'a mut W, +} +impl<'a> SPEED_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SPEED_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Low speed"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SPEED_A::LOW) + } + #[doc = "High speed"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SPEED_A::HIGH) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Field `HYSTEN` reader - Hysteresis Enable"] +pub struct HYSTEN_R(crate::FieldReader); +impl HYSTEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HYSTEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HYSTEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HYSTEN` writer - Hysteresis Enable"] +pub struct HYSTEN_W<'a> { + w: &'a mut W, +} +impl<'a> HYSTEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Filter Length\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FLEN_A { + #[doc = "0: No filtering"] + OFF = 0, + #[doc = "1: 3-bit majority function (2 of 3)"] + MAJ3 = 1, + #[doc = "2: 5-bit majority function (3 of 5)"] + MAJ5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FLEN_A) -> Self { + variant as _ + } +} +#[doc = "Field `FLEN` reader - Filter Length"] +pub struct FLEN_R(crate::FieldReader); +impl FLEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FLEN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(FLEN_A::OFF), + 1 => Some(FLEN_A::MAJ3), + 2 => Some(FLEN_A::MAJ5), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == FLEN_A::OFF + } + #[doc = "Checks if the value of the field is `MAJ3`"] + #[inline(always)] + pub fn is_maj3(&self) -> bool { + **self == FLEN_A::MAJ3 + } + #[doc = "Checks if the value of the field is `MAJ5`"] + #[inline(always)] + pub fn is_maj5(&self) -> bool { + **self == FLEN_A::MAJ5 + } +} +impl core::ops::Deref for FLEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLEN` writer - Filter Length"] +pub struct FLEN_W<'a> { + w: &'a mut W, +} +impl<'a> FLEN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FLEN_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No filtering"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(FLEN_A::OFF) + } + #[doc = "3-bit majority function (2 of 3)"] + #[inline(always)] + pub fn maj3(self) -> &'a mut W { + self.variant(FLEN_A::MAJ3) + } + #[doc = "5-bit majority function (3 of 5)"] + #[inline(always)] + pub fn maj5(self) -> &'a mut W { + self.variant(FLEN_A::MAJ5) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 24)) | ((value as u32 & 0x07) << 24); + self.w + } +} +#[doc = "Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum OUT_A { + #[doc = "0: The output of COMPn is not routed to the COMPn I/O port"] + OFF = 0, + #[doc = "1: The asynchronous output of COMPn is routed to the COMPn I/O port"] + ASYNC = 1, + #[doc = "2: The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port"] + SYNC = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: OUT_A) -> Self { + variant as _ + } +} +#[doc = "Field `OUT` reader - Output"] +pub struct OUT_R(crate::FieldReader); +impl OUT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + OUT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(OUT_A::OFF), + 1 => Some(OUT_A::ASYNC), + 2 => Some(OUT_A::SYNC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == OUT_A::OFF + } + #[doc = "Checks if the value of the field is `ASYNC`"] + #[inline(always)] + pub fn is_async(&self) -> bool { + **self == OUT_A::ASYNC + } + #[doc = "Checks if the value of the field is `SYNC`"] + #[inline(always)] + pub fn is_sync(&self) -> bool { + **self == OUT_A::SYNC + } +} +impl core::ops::Deref for OUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OUT` writer - Output"] +pub struct OUT_W<'a> { + w: &'a mut W, +} +impl<'a> OUT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: OUT_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "The output of COMPn is not routed to the COMPn I/O port"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(OUT_A::OFF) + } + #[doc = "The asynchronous output of COMPn is routed to the COMPn I/O port"] + #[inline(always)] + pub fn async_(self) -> &'a mut W { + self.variant(OUT_A::ASYNC) + } + #[doc = "The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port"] + #[inline(always)] + pub fn sync(self) -> &'a mut W { + self.variant(OUT_A::SYNC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 28)) | ((value as u32 & 0x03) << 28); + self.w + } +} +impl R { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Single-Shot Mode"] + #[inline(always)] + pub fn single(&self) -> SINGLE_R { + SINGLE_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 3:4 - Interrupt Selection"] + #[inline(always)] + pub fn intsel(&self) -> INTSEL_R { + INTSEL_R::new(((self.bits >> 3) & 0x03) as u8) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Negative Input Mux Selection"] + #[inline(always)] + pub fn muxneg(&self) -> MUXNEG_R { + MUXNEG_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bits 12:14 - Positive Input Mux Selection"] + #[inline(always)] + pub fn muxpos(&self) -> MUXPOS_R { + MUXPOS_R::new(((self.bits >> 12) & 0x07) as u8) + } + #[doc = "Bit 15 - Swap Inputs and Invert"] + #[inline(always)] + pub fn swap(&self) -> SWAP_R { + SWAP_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:17 - Speed Selection"] + #[inline(always)] + pub fn speed(&self) -> SPEED_R { + SPEED_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bit 19 - Hysteresis Enable"] + #[inline(always)] + pub fn hysten(&self) -> HYSTEN_R { + HYSTEN_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bits 24:26 - Filter Length"] + #[inline(always)] + pub fn flen(&self) -> FLEN_R { + FLEN_R::new(((self.bits >> 24) & 0x07) as u8) + } + #[doc = "Bits 28:29 - Output"] + #[inline(always)] + pub fn out(&self) -> OUT_R { + OUT_R::new(((self.bits >> 28) & 0x03) as u8) + } +} +impl W { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - Single-Shot Mode"] + #[inline(always)] + pub fn single(&mut self) -> SINGLE_W { + SINGLE_W { w: self } + } + #[doc = "Bits 3:4 - Interrupt Selection"] + #[inline(always)] + pub fn intsel(&mut self) -> INTSEL_W { + INTSEL_W { w: self } + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bits 8:10 - Negative Input Mux Selection"] + #[inline(always)] + pub fn muxneg(&mut self) -> MUXNEG_W { + MUXNEG_W { w: self } + } + #[doc = "Bits 12:14 - Positive Input Mux Selection"] + #[inline(always)] + pub fn muxpos(&mut self) -> MUXPOS_W { + MUXPOS_W { w: self } + } + #[doc = "Bit 15 - Swap Inputs and Invert"] + #[inline(always)] + pub fn swap(&mut self) -> SWAP_W { + SWAP_W { w: self } + } + #[doc = "Bits 16:17 - Speed Selection"] + #[inline(always)] + pub fn speed(&mut self) -> SPEED_W { + SPEED_W { w: self } + } + #[doc = "Bit 19 - Hysteresis Enable"] + #[inline(always)] + pub fn hysten(&mut self) -> HYSTEN_W { + HYSTEN_W { w: self } + } + #[doc = "Bits 24:26 - Filter Length"] + #[inline(always)] + pub fn flen(&mut self) -> FLEN_W { + FLEN_W { w: self } + } + #[doc = "Bits 28:29 - Output"] + #[inline(always)] + pub fn out(&mut self) -> OUT_W { + OUT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Comparator Control n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [compctrl](index.html) module"] +pub struct COMPCTRL_SPEC; +impl crate::RegisterSpec for COMPCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [compctrl::R](R) reader structure"] +impl crate::Readable for COMPCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [compctrl::W](W) writer structure"] +impl crate::Writable for COMPCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COMPCTRL[%s] +to value 0"] +impl crate::Resettable for COMPCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/ac/ctrla.rs b/pac/atsamc21e/src/ac/ctrla.rs new file mode 100644 index 000000000000..5f2c406226f4 --- /dev/null +++ b/pac/atsamc21e/src/ac/ctrla.rs @@ -0,0 +1,160 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/ac/ctrlb.rs b/pac/atsamc21e/src/ac/ctrlb.rs new file mode 100644 index 000000000000..fa9d604101c2 --- /dev/null +++ b/pac/atsamc21e/src/ac/ctrlb.rs @@ -0,0 +1,153 @@ +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `START0` writer - Comparator 0 Start Comparison"] +pub struct START0_W<'a> { + w: &'a mut W, +} +impl<'a> START0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `START1` writer - Comparator 1 Start Comparison"] +pub struct START1_W<'a> { + w: &'a mut W, +} +impl<'a> START1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `START2` writer - Comparator 2 Start Comparison"] +pub struct START2_W<'a> { + w: &'a mut W, +} +impl<'a> START2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `START3` writer - Comparator 3 Start Comparison"] +pub struct START3_W<'a> { + w: &'a mut W, +} +impl<'a> START3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +impl W { + #[doc = "Bit 0 - Comparator 0 Start Comparison"] + #[inline(always)] + pub fn start0(&mut self) -> START0_W { + START0_W { w: self } + } + #[doc = "Bit 1 - Comparator 1 Start Comparison"] + #[inline(always)] + pub fn start1(&mut self) -> START1_W { + START1_W { w: self } + } + #[doc = "Bit 2 - Comparator 2 Start Comparison"] + #[inline(always)] + pub fn start2(&mut self) -> START2_W { + START2_W { w: self } + } + #[doc = "Bit 3 - Comparator 3 Start Comparison"] + #[inline(always)] + pub fn start3(&mut self) -> START3_W { + START3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u8; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/ac/dbgctrl.rs b/pac/atsamc21e/src/ac/dbgctrl.rs new file mode 100644 index 000000000000..53636eb2b339 --- /dev/null +++ b/pac/atsamc21e/src/ac/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Debug Run"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Debug Run"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/ac/evctrl.rs b/pac/atsamc21e/src/ac/evctrl.rs new file mode 100644 index 000000000000..b2f64ee12108 --- /dev/null +++ b/pac/atsamc21e/src/ac/evctrl.rs @@ -0,0 +1,724 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COMPEO0` reader - Comparator 0 Event Output Enable"] +pub struct COMPEO0_R(crate::FieldReader); +impl COMPEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPEO0` writer - Comparator 0 Event Output Enable"] +pub struct COMPEO0_W<'a> { + w: &'a mut W, +} +impl<'a> COMPEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `COMPEO1` reader - Comparator 1 Event Output Enable"] +pub struct COMPEO1_R(crate::FieldReader); +impl COMPEO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPEO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPEO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPEO1` writer - Comparator 1 Event Output Enable"] +pub struct COMPEO1_W<'a> { + w: &'a mut W, +} +impl<'a> COMPEO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `COMPEO2` reader - Comparator 2 Event Output Enable"] +pub struct COMPEO2_R(crate::FieldReader); +impl COMPEO2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPEO2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPEO2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPEO2` writer - Comparator 2 Event Output Enable"] +pub struct COMPEO2_W<'a> { + w: &'a mut W, +} +impl<'a> COMPEO2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `COMPEO3` reader - Comparator 3 Event Output Enable"] +pub struct COMPEO3_R(crate::FieldReader); +impl COMPEO3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPEO3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPEO3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPEO3` writer - Comparator 3 Event Output Enable"] +pub struct COMPEO3_W<'a> { + w: &'a mut W, +} +impl<'a> COMPEO3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `WINEO0` reader - Window 0 Event Output Enable"] +pub struct WINEO0_R(crate::FieldReader); +impl WINEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINEO0` writer - Window 0 Event Output Enable"] +pub struct WINEO0_W<'a> { + w: &'a mut W, +} +impl<'a> WINEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `WINEO1` reader - Window 1 Event Output Enable"] +pub struct WINEO1_R(crate::FieldReader); +impl WINEO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINEO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINEO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINEO1` writer - Window 1 Event Output Enable"] +pub struct WINEO1_W<'a> { + w: &'a mut W, +} +impl<'a> WINEO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `COMPEI0` reader - Comparator 0 Event Input Enable"] +pub struct COMPEI0_R(crate::FieldReader); +impl COMPEI0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPEI0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPEI0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPEI0` writer - Comparator 0 Event Input Enable"] +pub struct COMPEI0_W<'a> { + w: &'a mut W, +} +impl<'a> COMPEI0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `COMPEI1` reader - Comparator 1 Event Input Enable"] +pub struct COMPEI1_R(crate::FieldReader); +impl COMPEI1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPEI1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPEI1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPEI1` writer - Comparator 1 Event Input Enable"] +pub struct COMPEI1_W<'a> { + w: &'a mut W, +} +impl<'a> COMPEI1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `COMPEI2` reader - Comparator 2 Event Input Enable"] +pub struct COMPEI2_R(crate::FieldReader); +impl COMPEI2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPEI2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPEI2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPEI2` writer - Comparator 2 Event Input Enable"] +pub struct COMPEI2_W<'a> { + w: &'a mut W, +} +impl<'a> COMPEI2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u16 & 0x01) << 10); + self.w + } +} +#[doc = "Field `COMPEI3` reader - Comparator 3 Event Input Enable"] +pub struct COMPEI3_R(crate::FieldReader); +impl COMPEI3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPEI3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPEI3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPEI3` writer - Comparator 3 Event Input Enable"] +pub struct COMPEI3_W<'a> { + w: &'a mut W, +} +impl<'a> COMPEI3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u16 & 0x01) << 11); + self.w + } +} +#[doc = "Field `INVEI0` reader - Comparator 0 Input Event Invert Enable"] +pub struct INVEI0_R(crate::FieldReader); +impl INVEI0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEI0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEI0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEI0` writer - Comparator 0 Input Event Invert Enable"] +pub struct INVEI0_W<'a> { + w: &'a mut W, +} +impl<'a> INVEI0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u16 & 0x01) << 12); + self.w + } +} +#[doc = "Field `INVEI1` reader - Comparator 1 Input Event Invert Enable"] +pub struct INVEI1_R(crate::FieldReader); +impl INVEI1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEI1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEI1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEI1` writer - Comparator 1 Input Event Invert Enable"] +pub struct INVEI1_W<'a> { + w: &'a mut W, +} +impl<'a> INVEI1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u16 & 0x01) << 13); + self.w + } +} +#[doc = "Field `INVEI2` reader - Comparator 2 Input Event Invert Enable"] +pub struct INVEI2_R(crate::FieldReader); +impl INVEI2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEI2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEI2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEI2` writer - Comparator 2 Input Event Invert Enable"] +pub struct INVEI2_W<'a> { + w: &'a mut W, +} +impl<'a> INVEI2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u16 & 0x01) << 14); + self.w + } +} +#[doc = "Field `INVEI3` reader - Comparator 3 Input Event Invert Enable"] +pub struct INVEI3_R(crate::FieldReader); +impl INVEI3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEI3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEI3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEI3` writer - Comparator 3 Input Event Invert Enable"] +pub struct INVEI3_W<'a> { + w: &'a mut W, +} +impl<'a> INVEI3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Comparator 0 Event Output Enable"] + #[inline(always)] + pub fn compeo0(&self) -> COMPEO0_R { + COMPEO0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Comparator 1 Event Output Enable"] + #[inline(always)] + pub fn compeo1(&self) -> COMPEO1_R { + COMPEO1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Comparator 2 Event Output Enable"] + #[inline(always)] + pub fn compeo2(&self) -> COMPEO2_R { + COMPEO2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Comparator 3 Event Output Enable"] + #[inline(always)] + pub fn compeo3(&self) -> COMPEO3_R { + COMPEO3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Window 0 Event Output Enable"] + #[inline(always)] + pub fn wineo0(&self) -> WINEO0_R { + WINEO0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Window 1 Event Output Enable"] + #[inline(always)] + pub fn wineo1(&self) -> WINEO1_R { + WINEO1_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 8 - Comparator 0 Event Input Enable"] + #[inline(always)] + pub fn compei0(&self) -> COMPEI0_R { + COMPEI0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Comparator 1 Event Input Enable"] + #[inline(always)] + pub fn compei1(&self) -> COMPEI1_R { + COMPEI1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Comparator 2 Event Input Enable"] + #[inline(always)] + pub fn compei2(&self) -> COMPEI2_R { + COMPEI2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Comparator 3 Event Input Enable"] + #[inline(always)] + pub fn compei3(&self) -> COMPEI3_R { + COMPEI3_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Comparator 0 Input Event Invert Enable"] + #[inline(always)] + pub fn invei0(&self) -> INVEI0_R { + INVEI0_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Comparator 1 Input Event Invert Enable"] + #[inline(always)] + pub fn invei1(&self) -> INVEI1_R { + INVEI1_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Comparator 2 Input Event Invert Enable"] + #[inline(always)] + pub fn invei2(&self) -> INVEI2_R { + INVEI2_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Comparator 3 Input Event Invert Enable"] + #[inline(always)] + pub fn invei3(&self) -> INVEI3_R { + INVEI3_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Comparator 0 Event Output Enable"] + #[inline(always)] + pub fn compeo0(&mut self) -> COMPEO0_W { + COMPEO0_W { w: self } + } + #[doc = "Bit 1 - Comparator 1 Event Output Enable"] + #[inline(always)] + pub fn compeo1(&mut self) -> COMPEO1_W { + COMPEO1_W { w: self } + } + #[doc = "Bit 2 - Comparator 2 Event Output Enable"] + #[inline(always)] + pub fn compeo2(&mut self) -> COMPEO2_W { + COMPEO2_W { w: self } + } + #[doc = "Bit 3 - Comparator 3 Event Output Enable"] + #[inline(always)] + pub fn compeo3(&mut self) -> COMPEO3_W { + COMPEO3_W { w: self } + } + #[doc = "Bit 4 - Window 0 Event Output Enable"] + #[inline(always)] + pub fn wineo0(&mut self) -> WINEO0_W { + WINEO0_W { w: self } + } + #[doc = "Bit 5 - Window 1 Event Output Enable"] + #[inline(always)] + pub fn wineo1(&mut self) -> WINEO1_W { + WINEO1_W { w: self } + } + #[doc = "Bit 8 - Comparator 0 Event Input Enable"] + #[inline(always)] + pub fn compei0(&mut self) -> COMPEI0_W { + COMPEI0_W { w: self } + } + #[doc = "Bit 9 - Comparator 1 Event Input Enable"] + #[inline(always)] + pub fn compei1(&mut self) -> COMPEI1_W { + COMPEI1_W { w: self } + } + #[doc = "Bit 10 - Comparator 2 Event Input Enable"] + #[inline(always)] + pub fn compei2(&mut self) -> COMPEI2_W { + COMPEI2_W { w: self } + } + #[doc = "Bit 11 - Comparator 3 Event Input Enable"] + #[inline(always)] + pub fn compei3(&mut self) -> COMPEI3_W { + COMPEI3_W { w: self } + } + #[doc = "Bit 12 - Comparator 0 Input Event Invert Enable"] + #[inline(always)] + pub fn invei0(&mut self) -> INVEI0_W { + INVEI0_W { w: self } + } + #[doc = "Bit 13 - Comparator 1 Input Event Invert Enable"] + #[inline(always)] + pub fn invei1(&mut self) -> INVEI1_W { + INVEI1_W { w: self } + } + #[doc = "Bit 14 - Comparator 2 Input Event Invert Enable"] + #[inline(always)] + pub fn invei2(&mut self) -> INVEI2_W { + INVEI2_W { w: self } + } + #[doc = "Bit 15 - Comparator 3 Input Event Invert Enable"] + #[inline(always)] + pub fn invei3(&mut self) -> INVEI3_W { + INVEI3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/ac/intenclr.rs b/pac/atsamc21e/src/ac/intenclr.rs new file mode 100644 index 000000000000..e948bee83d3f --- /dev/null +++ b/pac/atsamc21e/src/ac/intenclr.rs @@ -0,0 +1,348 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COMP0` reader - Comparator 0 Interrupt Enable"] +pub struct COMP0_R(crate::FieldReader); +impl COMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP0` writer - Comparator 0 Interrupt Enable"] +pub struct COMP0_W<'a> { + w: &'a mut W, +} +impl<'a> COMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `COMP1` reader - Comparator 1 Interrupt Enable"] +pub struct COMP1_R(crate::FieldReader); +impl COMP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP1` writer - Comparator 1 Interrupt Enable"] +pub struct COMP1_W<'a> { + w: &'a mut W, +} +impl<'a> COMP1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `COMP2` reader - Comparator 2 Interrupt Enable"] +pub struct COMP2_R(crate::FieldReader); +impl COMP2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP2` writer - Comparator 2 Interrupt Enable"] +pub struct COMP2_W<'a> { + w: &'a mut W, +} +impl<'a> COMP2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `COMP3` reader - Comparator 3 Interrupt Enable"] +pub struct COMP3_R(crate::FieldReader); +impl COMP3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP3` writer - Comparator 3 Interrupt Enable"] +pub struct COMP3_W<'a> { + w: &'a mut W, +} +impl<'a> COMP3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `WIN0` reader - Window 0 Interrupt Enable"] +pub struct WIN0_R(crate::FieldReader); +impl WIN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WIN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WIN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WIN0` writer - Window 0 Interrupt Enable"] +pub struct WIN0_W<'a> { + w: &'a mut W, +} +impl<'a> WIN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `WIN1` reader - Window 1 Interrupt Enable"] +pub struct WIN1_R(crate::FieldReader); +impl WIN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WIN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WIN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WIN1` writer - Window 1 Interrupt Enable"] +pub struct WIN1_W<'a> { + w: &'a mut W, +} +impl<'a> WIN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Comparator 0 Interrupt Enable"] + #[inline(always)] + pub fn comp0(&self) -> COMP0_R { + COMP0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Comparator 1 Interrupt Enable"] + #[inline(always)] + pub fn comp1(&self) -> COMP1_R { + COMP1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Comparator 2 Interrupt Enable"] + #[inline(always)] + pub fn comp2(&self) -> COMP2_R { + COMP2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Comparator 3 Interrupt Enable"] + #[inline(always)] + pub fn comp3(&self) -> COMP3_R { + COMP3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Window 0 Interrupt Enable"] + #[inline(always)] + pub fn win0(&self) -> WIN0_R { + WIN0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Window 1 Interrupt Enable"] + #[inline(always)] + pub fn win1(&self) -> WIN1_R { + WIN1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Comparator 0 Interrupt Enable"] + #[inline(always)] + pub fn comp0(&mut self) -> COMP0_W { + COMP0_W { w: self } + } + #[doc = "Bit 1 - Comparator 1 Interrupt Enable"] + #[inline(always)] + pub fn comp1(&mut self) -> COMP1_W { + COMP1_W { w: self } + } + #[doc = "Bit 2 - Comparator 2 Interrupt Enable"] + #[inline(always)] + pub fn comp2(&mut self) -> COMP2_W { + COMP2_W { w: self } + } + #[doc = "Bit 3 - Comparator 3 Interrupt Enable"] + #[inline(always)] + pub fn comp3(&mut self) -> COMP3_W { + COMP3_W { w: self } + } + #[doc = "Bit 4 - Window 0 Interrupt Enable"] + #[inline(always)] + pub fn win0(&mut self) -> WIN0_W { + WIN0_W { w: self } + } + #[doc = "Bit 5 - Window 1 Interrupt Enable"] + #[inline(always)] + pub fn win1(&mut self) -> WIN1_W { + WIN1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/ac/intenset.rs b/pac/atsamc21e/src/ac/intenset.rs new file mode 100644 index 000000000000..b631f5136fb6 --- /dev/null +++ b/pac/atsamc21e/src/ac/intenset.rs @@ -0,0 +1,348 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COMP0` reader - Comparator 0 Interrupt Enable"] +pub struct COMP0_R(crate::FieldReader); +impl COMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP0` writer - Comparator 0 Interrupt Enable"] +pub struct COMP0_W<'a> { + w: &'a mut W, +} +impl<'a> COMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `COMP1` reader - Comparator 1 Interrupt Enable"] +pub struct COMP1_R(crate::FieldReader); +impl COMP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP1` writer - Comparator 1 Interrupt Enable"] +pub struct COMP1_W<'a> { + w: &'a mut W, +} +impl<'a> COMP1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `COMP2` reader - Comparator 2 Interrupt Enable"] +pub struct COMP2_R(crate::FieldReader); +impl COMP2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP2` writer - Comparator 2 Interrupt Enable"] +pub struct COMP2_W<'a> { + w: &'a mut W, +} +impl<'a> COMP2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `COMP3` reader - Comparator 3 Interrupt Enable"] +pub struct COMP3_R(crate::FieldReader); +impl COMP3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP3` writer - Comparator 3 Interrupt Enable"] +pub struct COMP3_W<'a> { + w: &'a mut W, +} +impl<'a> COMP3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `WIN0` reader - Window 0 Interrupt Enable"] +pub struct WIN0_R(crate::FieldReader); +impl WIN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WIN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WIN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WIN0` writer - Window 0 Interrupt Enable"] +pub struct WIN0_W<'a> { + w: &'a mut W, +} +impl<'a> WIN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `WIN1` reader - Window 1 Interrupt Enable"] +pub struct WIN1_R(crate::FieldReader); +impl WIN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WIN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WIN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WIN1` writer - Window 1 Interrupt Enable"] +pub struct WIN1_W<'a> { + w: &'a mut W, +} +impl<'a> WIN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Comparator 0 Interrupt Enable"] + #[inline(always)] + pub fn comp0(&self) -> COMP0_R { + COMP0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Comparator 1 Interrupt Enable"] + #[inline(always)] + pub fn comp1(&self) -> COMP1_R { + COMP1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Comparator 2 Interrupt Enable"] + #[inline(always)] + pub fn comp2(&self) -> COMP2_R { + COMP2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Comparator 3 Interrupt Enable"] + #[inline(always)] + pub fn comp3(&self) -> COMP3_R { + COMP3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Window 0 Interrupt Enable"] + #[inline(always)] + pub fn win0(&self) -> WIN0_R { + WIN0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Window 1 Interrupt Enable"] + #[inline(always)] + pub fn win1(&self) -> WIN1_R { + WIN1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Comparator 0 Interrupt Enable"] + #[inline(always)] + pub fn comp0(&mut self) -> COMP0_W { + COMP0_W { w: self } + } + #[doc = "Bit 1 - Comparator 1 Interrupt Enable"] + #[inline(always)] + pub fn comp1(&mut self) -> COMP1_W { + COMP1_W { w: self } + } + #[doc = "Bit 2 - Comparator 2 Interrupt Enable"] + #[inline(always)] + pub fn comp2(&mut self) -> COMP2_W { + COMP2_W { w: self } + } + #[doc = "Bit 3 - Comparator 3 Interrupt Enable"] + #[inline(always)] + pub fn comp3(&mut self) -> COMP3_W { + COMP3_W { w: self } + } + #[doc = "Bit 4 - Window 0 Interrupt Enable"] + #[inline(always)] + pub fn win0(&mut self) -> WIN0_W { + WIN0_W { w: self } + } + #[doc = "Bit 5 - Window 1 Interrupt Enable"] + #[inline(always)] + pub fn win1(&mut self) -> WIN1_W { + WIN1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/ac/intflag.rs b/pac/atsamc21e/src/ac/intflag.rs new file mode 100644 index 000000000000..6557a5e48464 --- /dev/null +++ b/pac/atsamc21e/src/ac/intflag.rs @@ -0,0 +1,348 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COMP0` reader - Comparator 0"] +pub struct COMP0_R(crate::FieldReader); +impl COMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP0` writer - Comparator 0"] +pub struct COMP0_W<'a> { + w: &'a mut W, +} +impl<'a> COMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `COMP1` reader - Comparator 1"] +pub struct COMP1_R(crate::FieldReader); +impl COMP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP1` writer - Comparator 1"] +pub struct COMP1_W<'a> { + w: &'a mut W, +} +impl<'a> COMP1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `COMP2` reader - Comparator 2"] +pub struct COMP2_R(crate::FieldReader); +impl COMP2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP2` writer - Comparator 2"] +pub struct COMP2_W<'a> { + w: &'a mut W, +} +impl<'a> COMP2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `COMP3` reader - Comparator 3"] +pub struct COMP3_R(crate::FieldReader); +impl COMP3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP3` writer - Comparator 3"] +pub struct COMP3_W<'a> { + w: &'a mut W, +} +impl<'a> COMP3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `WIN0` reader - Window 0"] +pub struct WIN0_R(crate::FieldReader); +impl WIN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WIN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WIN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WIN0` writer - Window 0"] +pub struct WIN0_W<'a> { + w: &'a mut W, +} +impl<'a> WIN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `WIN1` reader - Window 1"] +pub struct WIN1_R(crate::FieldReader); +impl WIN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WIN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WIN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WIN1` writer - Window 1"] +pub struct WIN1_W<'a> { + w: &'a mut W, +} +impl<'a> WIN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Comparator 0"] + #[inline(always)] + pub fn comp0(&self) -> COMP0_R { + COMP0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Comparator 1"] + #[inline(always)] + pub fn comp1(&self) -> COMP1_R { + COMP1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Comparator 2"] + #[inline(always)] + pub fn comp2(&self) -> COMP2_R { + COMP2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Comparator 3"] + #[inline(always)] + pub fn comp3(&self) -> COMP3_R { + COMP3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Window 0"] + #[inline(always)] + pub fn win0(&self) -> WIN0_R { + WIN0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Window 1"] + #[inline(always)] + pub fn win1(&self) -> WIN1_R { + WIN1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Comparator 0"] + #[inline(always)] + pub fn comp0(&mut self) -> COMP0_W { + COMP0_W { w: self } + } + #[doc = "Bit 1 - Comparator 1"] + #[inline(always)] + pub fn comp1(&mut self) -> COMP1_W { + COMP1_W { w: self } + } + #[doc = "Bit 2 - Comparator 2"] + #[inline(always)] + pub fn comp2(&mut self) -> COMP2_W { + COMP2_W { w: self } + } + #[doc = "Bit 3 - Comparator 3"] + #[inline(always)] + pub fn comp3(&mut self) -> COMP3_W { + COMP3_W { w: self } + } + #[doc = "Bit 4 - Window 0"] + #[inline(always)] + pub fn win0(&mut self) -> WIN0_W { + WIN0_W { w: self } + } + #[doc = "Bit 5 - Window 1"] + #[inline(always)] + pub fn win1(&mut self) -> WIN1_W { + WIN1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/ac/scaler.rs b/pac/atsamc21e/src/ac/scaler.rs new file mode 100644 index 000000000000..091cacfaeb4b --- /dev/null +++ b/pac/atsamc21e/src/ac/scaler.rs @@ -0,0 +1,104 @@ +#[doc = "Register `SCALER[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SCALER[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `VALUE` reader - Scaler Value"] +pub struct VALUE_R(crate::FieldReader); +impl VALUE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + VALUE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VALUE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VALUE` writer - Scaler Value"] +pub struct VALUE_W<'a> { + w: &'a mut W, +} +impl<'a> VALUE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u8 & 0x3f); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Scaler Value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - Scaler Value"] + #[inline(always)] + pub fn value(&mut self) -> VALUE_W { + VALUE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Scaler n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [scaler](index.html) module"] +pub struct SCALER_SPEC; +impl crate::RegisterSpec for SCALER_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [scaler::R](R) reader structure"] +impl crate::Readable for SCALER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [scaler::W](W) writer structure"] +impl crate::Writable for SCALER_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SCALER[%s] +to value 0"] +impl crate::Resettable for SCALER_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/ac/statusa.rs b/pac/atsamc21e/src/ac/statusa.rs new file mode 100644 index 000000000000..f79619555497 --- /dev/null +++ b/pac/atsamc21e/src/ac/statusa.rs @@ -0,0 +1,237 @@ +#[doc = "Register `STATUSA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `STATE0` reader - Comparator 0 Current State"] +pub struct STATE0_R(crate::FieldReader); +impl STATE0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STATE0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STATE0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STATE1` reader - Comparator 1 Current State"] +pub struct STATE1_R(crate::FieldReader); +impl STATE1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STATE1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STATE1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STATE2` reader - Comparator 2 Current State"] +pub struct STATE2_R(crate::FieldReader); +impl STATE2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STATE2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STATE2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STATE3` reader - Comparator 3 Current State"] +pub struct STATE3_R(crate::FieldReader); +impl STATE3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STATE3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STATE3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Window 0 Current State\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WSTATE0_A { + #[doc = "0: Signal is above window"] + ABOVE = 0, + #[doc = "1: Signal is inside window"] + INSIDE = 1, + #[doc = "2: Signal is below window"] + BELOW = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WSTATE0_A) -> Self { + variant as _ + } +} +#[doc = "Field `WSTATE0` reader - Window 0 Current State"] +pub struct WSTATE0_R(crate::FieldReader); +impl WSTATE0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WSTATE0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(WSTATE0_A::ABOVE), + 1 => Some(WSTATE0_A::INSIDE), + 2 => Some(WSTATE0_A::BELOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `ABOVE`"] + #[inline(always)] + pub fn is_above(&self) -> bool { + **self == WSTATE0_A::ABOVE + } + #[doc = "Checks if the value of the field is `INSIDE`"] + #[inline(always)] + pub fn is_inside(&self) -> bool { + **self == WSTATE0_A::INSIDE + } + #[doc = "Checks if the value of the field is `BELOW`"] + #[inline(always)] + pub fn is_below(&self) -> bool { + **self == WSTATE0_A::BELOW + } +} +impl core::ops::Deref for WSTATE0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Window 1 Current State\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WSTATE1_A { + #[doc = "0: Signal is above window"] + ABOVE = 0, + #[doc = "1: Signal is inside window"] + INSIDE = 1, + #[doc = "2: Signal is below window"] + BELOW = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WSTATE1_A) -> Self { + variant as _ + } +} +#[doc = "Field `WSTATE1` reader - Window 1 Current State"] +pub struct WSTATE1_R(crate::FieldReader); +impl WSTATE1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WSTATE1_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(WSTATE1_A::ABOVE), + 1 => Some(WSTATE1_A::INSIDE), + 2 => Some(WSTATE1_A::BELOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `ABOVE`"] + #[inline(always)] + pub fn is_above(&self) -> bool { + **self == WSTATE1_A::ABOVE + } + #[doc = "Checks if the value of the field is `INSIDE`"] + #[inline(always)] + pub fn is_inside(&self) -> bool { + **self == WSTATE1_A::INSIDE + } + #[doc = "Checks if the value of the field is `BELOW`"] + #[inline(always)] + pub fn is_below(&self) -> bool { + **self == WSTATE1_A::BELOW + } +} +impl core::ops::Deref for WSTATE1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Comparator 0 Current State"] + #[inline(always)] + pub fn state0(&self) -> STATE0_R { + STATE0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Comparator 1 Current State"] + #[inline(always)] + pub fn state1(&self) -> STATE1_R { + STATE1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Comparator 2 Current State"] + #[inline(always)] + pub fn state2(&self) -> STATE2_R { + STATE2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Comparator 3 Current State"] + #[inline(always)] + pub fn state3(&self) -> STATE3_R { + STATE3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bits 4:5 - Window 0 Current State"] + #[inline(always)] + pub fn wstate0(&self) -> WSTATE0_R { + WSTATE0_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bits 6:7 - Window 1 Current State"] + #[inline(always)] + pub fn wstate1(&self) -> WSTATE1_R { + WSTATE1_R::new(((self.bits >> 6) & 0x03) as u8) + } +} +#[doc = "Status A\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [statusa](index.html) module"] +pub struct STATUSA_SPEC; +impl crate::RegisterSpec for STATUSA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [statusa::R](R) reader structure"] +impl crate::Readable for STATUSA_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUSA to value 0"] +impl crate::Resettable for STATUSA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/ac/statusb.rs b/pac/atsamc21e/src/ac/statusb.rs new file mode 100644 index 000000000000..1f7035958bd8 --- /dev/null +++ b/pac/atsamc21e/src/ac/statusb.rs @@ -0,0 +1,113 @@ +#[doc = "Register `STATUSB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `READY0` reader - Comparator 0 Ready"] +pub struct READY0_R(crate::FieldReader); +impl READY0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + READY0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for READY0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `READY1` reader - Comparator 1 Ready"] +pub struct READY1_R(crate::FieldReader); +impl READY1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + READY1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for READY1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `READY2` reader - Comparator 2 Ready"] +pub struct READY2_R(crate::FieldReader); +impl READY2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + READY2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for READY2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `READY3` reader - Comparator 3 Ready"] +pub struct READY3_R(crate::FieldReader); +impl READY3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + READY3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for READY3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Comparator 0 Ready"] + #[inline(always)] + pub fn ready0(&self) -> READY0_R { + READY0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Comparator 1 Ready"] + #[inline(always)] + pub fn ready1(&self) -> READY1_R { + READY1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Comparator 2 Ready"] + #[inline(always)] + pub fn ready2(&self) -> READY2_R { + READY2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Comparator 3 Ready"] + #[inline(always)] + pub fn ready3(&self) -> READY3_R { + READY3_R::new(((self.bits >> 3) & 0x01) != 0) + } +} +#[doc = "Status B\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [statusb](index.html) module"] +pub struct STATUSB_SPEC; +impl crate::RegisterSpec for STATUSB_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [statusb::R](R) reader structure"] +impl crate::Readable for STATUSB_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUSB to value 0"] +impl crate::Resettable for STATUSB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/ac/syncbusy.rs b/pac/atsamc21e/src/ac/syncbusy.rs new file mode 100644 index 000000000000..bbd5b5cbe18f --- /dev/null +++ b/pac/atsamc21e/src/ac/syncbusy.rs @@ -0,0 +1,173 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - Enable Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINCTRL` reader - WINCTRL Synchronization Busy"] +pub struct WINCTRL_R(crate::FieldReader); +impl WINCTRL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINCTRL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINCTRL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPCTRL0` reader - COMPCTRL 0 Synchronization Busy"] +pub struct COMPCTRL0_R(crate::FieldReader); +impl COMPCTRL0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPCTRL0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPCTRL0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPCTRL1` reader - COMPCTRL 1 Synchronization Busy"] +pub struct COMPCTRL1_R(crate::FieldReader); +impl COMPCTRL1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPCTRL1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPCTRL1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPCTRL2` reader - COMPCTRL 2 Synchronization Busy"] +pub struct COMPCTRL2_R(crate::FieldReader); +impl COMPCTRL2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPCTRL2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPCTRL2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPCTRL3` reader - COMPCTRL 3 Synchronization Busy"] +pub struct COMPCTRL3_R(crate::FieldReader); +impl COMPCTRL3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPCTRL3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPCTRL3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - WINCTRL Synchronization Busy"] + #[inline(always)] + pub fn winctrl(&self) -> WINCTRL_R { + WINCTRL_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - COMPCTRL 0 Synchronization Busy"] + #[inline(always)] + pub fn compctrl0(&self) -> COMPCTRL0_R { + COMPCTRL0_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - COMPCTRL 1 Synchronization Busy"] + #[inline(always)] + pub fn compctrl1(&self) -> COMPCTRL1_R { + COMPCTRL1_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - COMPCTRL 2 Synchronization Busy"] + #[inline(always)] + pub fn compctrl2(&self) -> COMPCTRL2_R { + COMPCTRL2_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - COMPCTRL 3 Synchronization Busy"] + #[inline(always)] + pub fn compctrl3(&self) -> COMPCTRL3_R { + COMPCTRL3_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +#[doc = "Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/ac/winctrl.rs b/pac/atsamc21e/src/ac/winctrl.rs new file mode 100644 index 000000000000..e3fe941f07bd --- /dev/null +++ b/pac/atsamc21e/src/ac/winctrl.rs @@ -0,0 +1,384 @@ +#[doc = "Register `WINCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WINCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WEN0` reader - Window 0 Mode Enable"] +pub struct WEN0_R(crate::FieldReader); +impl WEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WEN0` writer - Window 0 Mode Enable"] +pub struct WEN0_W<'a> { + w: &'a mut W, +} +impl<'a> WEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Window 0 Interrupt Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WINTSEL0_A { + #[doc = "0: Interrupt on signal above window"] + ABOVE = 0, + #[doc = "1: Interrupt on signal inside window"] + INSIDE = 1, + #[doc = "2: Interrupt on signal below window"] + BELOW = 2, + #[doc = "3: Interrupt on signal outside window"] + OUTSIDE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WINTSEL0_A) -> Self { + variant as _ + } +} +#[doc = "Field `WINTSEL0` reader - Window 0 Interrupt Selection"] +pub struct WINTSEL0_R(crate::FieldReader); +impl WINTSEL0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WINTSEL0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> WINTSEL0_A { + match self.bits { + 0 => WINTSEL0_A::ABOVE, + 1 => WINTSEL0_A::INSIDE, + 2 => WINTSEL0_A::BELOW, + 3 => WINTSEL0_A::OUTSIDE, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `ABOVE`"] + #[inline(always)] + pub fn is_above(&self) -> bool { + **self == WINTSEL0_A::ABOVE + } + #[doc = "Checks if the value of the field is `INSIDE`"] + #[inline(always)] + pub fn is_inside(&self) -> bool { + **self == WINTSEL0_A::INSIDE + } + #[doc = "Checks if the value of the field is `BELOW`"] + #[inline(always)] + pub fn is_below(&self) -> bool { + **self == WINTSEL0_A::BELOW + } + #[doc = "Checks if the value of the field is `OUTSIDE`"] + #[inline(always)] + pub fn is_outside(&self) -> bool { + **self == WINTSEL0_A::OUTSIDE + } +} +impl core::ops::Deref for WINTSEL0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINTSEL0` writer - Window 0 Interrupt Selection"] +pub struct WINTSEL0_W<'a> { + w: &'a mut W, +} +impl<'a> WINTSEL0_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WINTSEL0_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Interrupt on signal above window"] + #[inline(always)] + pub fn above(self) -> &'a mut W { + self.variant(WINTSEL0_A::ABOVE) + } + #[doc = "Interrupt on signal inside window"] + #[inline(always)] + pub fn inside(self) -> &'a mut W { + self.variant(WINTSEL0_A::INSIDE) + } + #[doc = "Interrupt on signal below window"] + #[inline(always)] + pub fn below(self) -> &'a mut W { + self.variant(WINTSEL0_A::BELOW) + } + #[doc = "Interrupt on signal outside window"] + #[inline(always)] + pub fn outside(self) -> &'a mut W { + self.variant(WINTSEL0_A::OUTSIDE) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 1)) | ((value as u8 & 0x03) << 1); + self.w + } +} +#[doc = "Field `WEN1` reader - Window 1 Mode Enable"] +pub struct WEN1_R(crate::FieldReader); +impl WEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WEN1` writer - Window 1 Mode Enable"] +pub struct WEN1_W<'a> { + w: &'a mut W, +} +impl<'a> WEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Window 1 Interrupt Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WINTSEL1_A { + #[doc = "0: Interrupt on signal above window"] + ABOVE = 0, + #[doc = "1: Interrupt on signal inside window"] + INSIDE = 1, + #[doc = "2: Interrupt on signal below window"] + BELOW = 2, + #[doc = "3: Interrupt on signal outside window"] + OUTSIDE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WINTSEL1_A) -> Self { + variant as _ + } +} +#[doc = "Field `WINTSEL1` reader - Window 1 Interrupt Selection"] +pub struct WINTSEL1_R(crate::FieldReader); +impl WINTSEL1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WINTSEL1_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> WINTSEL1_A { + match self.bits { + 0 => WINTSEL1_A::ABOVE, + 1 => WINTSEL1_A::INSIDE, + 2 => WINTSEL1_A::BELOW, + 3 => WINTSEL1_A::OUTSIDE, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `ABOVE`"] + #[inline(always)] + pub fn is_above(&self) -> bool { + **self == WINTSEL1_A::ABOVE + } + #[doc = "Checks if the value of the field is `INSIDE`"] + #[inline(always)] + pub fn is_inside(&self) -> bool { + **self == WINTSEL1_A::INSIDE + } + #[doc = "Checks if the value of the field is `BELOW`"] + #[inline(always)] + pub fn is_below(&self) -> bool { + **self == WINTSEL1_A::BELOW + } + #[doc = "Checks if the value of the field is `OUTSIDE`"] + #[inline(always)] + pub fn is_outside(&self) -> bool { + **self == WINTSEL1_A::OUTSIDE + } +} +impl core::ops::Deref for WINTSEL1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINTSEL1` writer - Window 1 Interrupt Selection"] +pub struct WINTSEL1_W<'a> { + w: &'a mut W, +} +impl<'a> WINTSEL1_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WINTSEL1_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Interrupt on signal above window"] + #[inline(always)] + pub fn above(self) -> &'a mut W { + self.variant(WINTSEL1_A::ABOVE) + } + #[doc = "Interrupt on signal inside window"] + #[inline(always)] + pub fn inside(self) -> &'a mut W { + self.variant(WINTSEL1_A::INSIDE) + } + #[doc = "Interrupt on signal below window"] + #[inline(always)] + pub fn below(self) -> &'a mut W { + self.variant(WINTSEL1_A::BELOW) + } + #[doc = "Interrupt on signal outside window"] + #[inline(always)] + pub fn outside(self) -> &'a mut W { + self.variant(WINTSEL1_A::OUTSIDE) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 5)) | ((value as u8 & 0x03) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Window 0 Mode Enable"] + #[inline(always)] + pub fn wen0(&self) -> WEN0_R { + WEN0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bits 1:2 - Window 0 Interrupt Selection"] + #[inline(always)] + pub fn wintsel0(&self) -> WINTSEL0_R { + WINTSEL0_R::new(((self.bits >> 1) & 0x03) as u8) + } + #[doc = "Bit 4 - Window 1 Mode Enable"] + #[inline(always)] + pub fn wen1(&self) -> WEN1_R { + WEN1_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bits 5:6 - Window 1 Interrupt Selection"] + #[inline(always)] + pub fn wintsel1(&self) -> WINTSEL1_R { + WINTSEL1_R::new(((self.bits >> 5) & 0x03) as u8) + } +} +impl W { + #[doc = "Bit 0 - Window 0 Mode Enable"] + #[inline(always)] + pub fn wen0(&mut self) -> WEN0_W { + WEN0_W { w: self } + } + #[doc = "Bits 1:2 - Window 0 Interrupt Selection"] + #[inline(always)] + pub fn wintsel0(&mut self) -> WINTSEL0_W { + WINTSEL0_W { w: self } + } + #[doc = "Bit 4 - Window 1 Mode Enable"] + #[inline(always)] + pub fn wen1(&mut self) -> WEN1_W { + WEN1_W { w: self } + } + #[doc = "Bits 5:6 - Window 1 Interrupt Selection"] + #[inline(always)] + pub fn wintsel1(&mut self) -> WINTSEL1_W { + WINTSEL1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Window Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [winctrl](index.html) module"] +pub struct WINCTRL_SPEC; +impl crate::RegisterSpec for WINCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [winctrl::R](R) reader structure"] +impl crate::Readable for WINCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [winctrl::W](W) writer structure"] +impl crate::Writable for WINCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WINCTRL to value 0"] +impl crate::Resettable for WINCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/adc0.rs b/pac/atsamc21e/src/adc0.rs new file mode 100644 index 000000000000..453f56ed28c8 --- /dev/null +++ b/pac/atsamc21e/src/adc0.rs @@ -0,0 +1,141 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + #[doc = "0x01 - Control B"] + pub ctrlb: crate::Reg, + #[doc = "0x02 - Reference Control"] + pub refctrl: crate::Reg, + #[doc = "0x03 - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x04 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x05 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x06 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x07 - Sequence Status"] + pub seqstatus: crate::Reg, + #[doc = "0x08 - Input Control"] + pub inputctrl: crate::Reg, + #[doc = "0x0a - Control C"] + pub ctrlc: crate::Reg, + #[doc = "0x0c - Average Control"] + pub avgctrl: crate::Reg, + #[doc = "0x0d - Sample Time Control"] + pub sampctrl: crate::Reg, + #[doc = "0x0e - Window Monitor Lower Threshold"] + pub winlt: crate::Reg, + #[doc = "0x10 - Window Monitor Upper Threshold"] + pub winut: crate::Reg, + #[doc = "0x12 - Gain Correction"] + pub gaincorr: crate::Reg, + #[doc = "0x14 - Offset Correction"] + pub offsetcorr: crate::Reg, + _reserved16: [u8; 0x02], + #[doc = "0x18 - Software Trigger"] + pub swtrig: crate::Reg, + _reserved17: [u8; 0x03], + #[doc = "0x1c - Debug Control"] + pub dbgctrl: crate::Reg, + _reserved18: [u8; 0x03], + #[doc = "0x20 - Synchronization Busy"] + pub syncbusy: crate::Reg, + _reserved19: [u8; 0x02], + #[doc = "0x24 - Result"] + pub result: crate::Reg, + _reserved20: [u8; 0x02], + #[doc = "0x28 - Sequence Control"] + pub seqctrl: crate::Reg, + #[doc = "0x2c - Calibration"] + pub calib: crate::Reg, +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "Control B"] +pub mod ctrlb; +#[doc = "REFCTRL register accessor: an alias for `Reg`"] +pub type REFCTRL = crate::Reg; +#[doc = "Reference Control"] +pub mod refctrl; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "SEQSTATUS register accessor: an alias for `Reg`"] +pub type SEQSTATUS = crate::Reg; +#[doc = "Sequence Status"] +pub mod seqstatus; +#[doc = "INPUTCTRL register accessor: an alias for `Reg`"] +pub type INPUTCTRL = crate::Reg; +#[doc = "Input Control"] +pub mod inputctrl; +#[doc = "CTRLC register accessor: an alias for `Reg`"] +pub type CTRLC = crate::Reg; +#[doc = "Control C"] +pub mod ctrlc; +#[doc = "AVGCTRL register accessor: an alias for `Reg`"] +pub type AVGCTRL = crate::Reg; +#[doc = "Average Control"] +pub mod avgctrl; +#[doc = "SAMPCTRL register accessor: an alias for `Reg`"] +pub type SAMPCTRL = crate::Reg; +#[doc = "Sample Time Control"] +pub mod sampctrl; +#[doc = "WINLT register accessor: an alias for `Reg`"] +pub type WINLT = crate::Reg; +#[doc = "Window Monitor Lower Threshold"] +pub mod winlt; +#[doc = "WINUT register accessor: an alias for `Reg`"] +pub type WINUT = crate::Reg; +#[doc = "Window Monitor Upper Threshold"] +pub mod winut; +#[doc = "GAINCORR register accessor: an alias for `Reg`"] +pub type GAINCORR = crate::Reg; +#[doc = "Gain Correction"] +pub mod gaincorr; +#[doc = "OFFSETCORR register accessor: an alias for `Reg`"] +pub type OFFSETCORR = crate::Reg; +#[doc = "Offset Correction"] +pub mod offsetcorr; +#[doc = "SWTRIG register accessor: an alias for `Reg`"] +pub type SWTRIG = crate::Reg; +#[doc = "Software Trigger"] +pub mod swtrig; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Busy"] +pub mod syncbusy; +#[doc = "RESULT register accessor: an alias for `Reg`"] +pub type RESULT = crate::Reg; +#[doc = "Result"] +pub mod result; +#[doc = "SEQCTRL register accessor: an alias for `Reg`"] +pub type SEQCTRL = crate::Reg; +#[doc = "Sequence Control"] +pub mod seqctrl; +#[doc = "CALIB register accessor: an alias for `Reg`"] +pub type CALIB = crate::Reg; +#[doc = "Calibration"] +pub mod calib; diff --git a/pac/atsamc21e/src/adc0/avgctrl.rs b/pac/atsamc21e/src/adc0/avgctrl.rs new file mode 100644 index 000000000000..ddb735715c98 --- /dev/null +++ b/pac/atsamc21e/src/adc0/avgctrl.rs @@ -0,0 +1,306 @@ +#[doc = "Register `AVGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `AVGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Number of Samples to be Collected\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SAMPLENUM_A { + #[doc = "0: 1 sample"] + _1 = 0, + #[doc = "1: 2 samples"] + _2 = 1, + #[doc = "2: 4 samples"] + _4 = 2, + #[doc = "3: 8 samples"] + _8 = 3, + #[doc = "4: 16 samples"] + _16 = 4, + #[doc = "5: 32 samples"] + _32 = 5, + #[doc = "6: 64 samples"] + _64 = 6, + #[doc = "7: 128 samples"] + _128 = 7, + #[doc = "8: 256 samples"] + _256 = 8, + #[doc = "9: 512 samples"] + _512 = 9, + #[doc = "10: 1024 samples"] + _1024 = 10, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SAMPLENUM_A) -> Self { + variant as _ + } +} +#[doc = "Field `SAMPLENUM` reader - Number of Samples to be Collected"] +pub struct SAMPLENUM_R(crate::FieldReader); +impl SAMPLENUM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SAMPLENUM_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SAMPLENUM_A::_1), + 1 => Some(SAMPLENUM_A::_2), + 2 => Some(SAMPLENUM_A::_4), + 3 => Some(SAMPLENUM_A::_8), + 4 => Some(SAMPLENUM_A::_16), + 5 => Some(SAMPLENUM_A::_32), + 6 => Some(SAMPLENUM_A::_64), + 7 => Some(SAMPLENUM_A::_128), + 8 => Some(SAMPLENUM_A::_256), + 9 => Some(SAMPLENUM_A::_512), + 10 => Some(SAMPLENUM_A::_1024), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_1`"] + #[inline(always)] + pub fn is_1(&self) -> bool { + **self == SAMPLENUM_A::_1 + } + #[doc = "Checks if the value of the field is `_2`"] + #[inline(always)] + pub fn is_2(&self) -> bool { + **self == SAMPLENUM_A::_2 + } + #[doc = "Checks if the value of the field is `_4`"] + #[inline(always)] + pub fn is_4(&self) -> bool { + **self == SAMPLENUM_A::_4 + } + #[doc = "Checks if the value of the field is `_8`"] + #[inline(always)] + pub fn is_8(&self) -> bool { + **self == SAMPLENUM_A::_8 + } + #[doc = "Checks if the value of the field is `_16`"] + #[inline(always)] + pub fn is_16(&self) -> bool { + **self == SAMPLENUM_A::_16 + } + #[doc = "Checks if the value of the field is `_32`"] + #[inline(always)] + pub fn is_32(&self) -> bool { + **self == SAMPLENUM_A::_32 + } + #[doc = "Checks if the value of the field is `_64`"] + #[inline(always)] + pub fn is_64(&self) -> bool { + **self == SAMPLENUM_A::_64 + } + #[doc = "Checks if the value of the field is `_128`"] + #[inline(always)] + pub fn is_128(&self) -> bool { + **self == SAMPLENUM_A::_128 + } + #[doc = "Checks if the value of the field is `_256`"] + #[inline(always)] + pub fn is_256(&self) -> bool { + **self == SAMPLENUM_A::_256 + } + #[doc = "Checks if the value of the field is `_512`"] + #[inline(always)] + pub fn is_512(&self) -> bool { + **self == SAMPLENUM_A::_512 + } + #[doc = "Checks if the value of the field is `_1024`"] + #[inline(always)] + pub fn is_1024(&self) -> bool { + **self == SAMPLENUM_A::_1024 + } +} +impl core::ops::Deref for SAMPLENUM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SAMPLENUM` writer - Number of Samples to be Collected"] +pub struct SAMPLENUM_W<'a> { + w: &'a mut W, +} +impl<'a> SAMPLENUM_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SAMPLENUM_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "1 sample"] + #[inline(always)] + pub fn _1(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_1) + } + #[doc = "2 samples"] + #[inline(always)] + pub fn _2(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_2) + } + #[doc = "4 samples"] + #[inline(always)] + pub fn _4(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_4) + } + #[doc = "8 samples"] + #[inline(always)] + pub fn _8(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_8) + } + #[doc = "16 samples"] + #[inline(always)] + pub fn _16(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_16) + } + #[doc = "32 samples"] + #[inline(always)] + pub fn _32(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_32) + } + #[doc = "64 samples"] + #[inline(always)] + pub fn _64(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_64) + } + #[doc = "128 samples"] + #[inline(always)] + pub fn _128(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_128) + } + #[doc = "256 samples"] + #[inline(always)] + pub fn _256(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_256) + } + #[doc = "512 samples"] + #[inline(always)] + pub fn _512(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_512) + } + #[doc = "1024 samples"] + #[inline(always)] + pub fn _1024(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +#[doc = "Field `ADJRES` reader - Adjusting Result / Division Coefficient"] +pub struct ADJRES_R(crate::FieldReader); +impl ADJRES_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ADJRES_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADJRES_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADJRES` writer - Adjusting Result / Division Coefficient"] +pub struct ADJRES_W<'a> { + w: &'a mut W, +} +impl<'a> ADJRES_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 4)) | ((value as u8 & 0x07) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Number of Samples to be Collected"] + #[inline(always)] + pub fn samplenum(&self) -> SAMPLENUM_R { + SAMPLENUM_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:6 - Adjusting Result / Division Coefficient"] + #[inline(always)] + pub fn adjres(&self) -> ADJRES_R { + ADJRES_R::new(((self.bits >> 4) & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Number of Samples to be Collected"] + #[inline(always)] + pub fn samplenum(&mut self) -> SAMPLENUM_W { + SAMPLENUM_W { w: self } + } + #[doc = "Bits 4:6 - Adjusting Result / Division Coefficient"] + #[inline(always)] + pub fn adjres(&mut self) -> ADJRES_W { + ADJRES_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Average Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [avgctrl](index.html) module"] +pub struct AVGCTRL_SPEC; +impl crate::RegisterSpec for AVGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [avgctrl::R](R) reader structure"] +impl crate::Readable for AVGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [avgctrl::W](W) writer structure"] +impl crate::Writable for AVGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets AVGCTRL to value 0"] +impl crate::Resettable for AVGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/adc0/calib.rs b/pac/atsamc21e/src/adc0/calib.rs new file mode 100644 index 000000000000..8a1a99b8c47d --- /dev/null +++ b/pac/atsamc21e/src/adc0/calib.rs @@ -0,0 +1,140 @@ +#[doc = "Register `CALIB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CALIB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BIASCOMP` reader - Bias Comparator Scaling"] +pub struct BIASCOMP_R(crate::FieldReader); +impl BIASCOMP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BIASCOMP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BIASCOMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BIASCOMP` writer - Bias Comparator Scaling"] +pub struct BIASCOMP_W<'a> { + w: &'a mut W, +} +impl<'a> BIASCOMP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u16 & 0x07); + self.w + } +} +#[doc = "Field `BIASREFBUF` reader - Bias Reference Buffer Scaling"] +pub struct BIASREFBUF_R(crate::FieldReader); +impl BIASREFBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BIASREFBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BIASREFBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BIASREFBUF` writer - Bias Reference Buffer Scaling"] +pub struct BIASREFBUF_W<'a> { + w: &'a mut W, +} +impl<'a> BIASREFBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u16 & 0x07) << 8); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Bias Comparator Scaling"] + #[inline(always)] + pub fn biascomp(&self) -> BIASCOMP_R { + BIASCOMP_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bits 8:10 - Bias Reference Buffer Scaling"] + #[inline(always)] + pub fn biasrefbuf(&self) -> BIASREFBUF_R { + BIASREFBUF_R::new(((self.bits >> 8) & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Bias Comparator Scaling"] + #[inline(always)] + pub fn biascomp(&mut self) -> BIASCOMP_W { + BIASCOMP_W { w: self } + } + #[doc = "Bits 8:10 - Bias Reference Buffer Scaling"] + #[inline(always)] + pub fn biasrefbuf(&mut self) -> BIASREFBUF_W { + BIASREFBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Calibration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [calib](index.html) module"] +pub struct CALIB_SPEC; +impl crate::RegisterSpec for CALIB_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [calib::R](R) reader structure"] +impl crate::Readable for CALIB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [calib::W](W) writer structure"] +impl crate::Writable for CALIB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CALIB to value 0"] +impl crate::Resettable for CALIB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/adc0/ctrla.rs b/pac/atsamc21e/src/adc0/ctrla.rs new file mode 100644 index 000000000000..47c681045f95 --- /dev/null +++ b/pac/atsamc21e/src/adc0/ctrla.rs @@ -0,0 +1,301 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SLAVEEN` reader - Slave Enable"] +pub struct SLAVEEN_R(crate::FieldReader); +impl SLAVEEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLAVEEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SLAVEEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLAVEEN` writer - Slave Enable"] +pub struct SLAVEEN_W<'a> { + w: &'a mut W, +} +impl<'a> SLAVEEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run During Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run During Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - On Demand Control"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - On Demand Control"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 5 - Slave Enable"] + #[inline(always)] + pub fn slaveen(&self) -> SLAVEEN_R { + SLAVEEN_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Run During Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 5 - Slave Enable"] + #[inline(always)] + pub fn slaveen(&mut self) -> SLAVEEN_W { + SLAVEEN_W { w: self } + } + #[doc = "Bit 6 - Run During Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/adc0/ctrlb.rs b/pac/atsamc21e/src/adc0/ctrlb.rs new file mode 100644 index 000000000000..4d39688fc975 --- /dev/null +++ b/pac/atsamc21e/src/adc0/ctrlb.rs @@ -0,0 +1,230 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Prescaler Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: Peripheral clock / 2"] + DIV2 = 0, + #[doc = "1: Peripheral clock / 4"] + DIV4 = 1, + #[doc = "2: Peripheral clock / 8"] + DIV8 = 2, + #[doc = "3: Peripheral clock / 16"] + DIV16 = 3, + #[doc = "4: Peripheral clock / 32"] + DIV32 = 4, + #[doc = "5: Peripheral clock / 64"] + DIV64 = 5, + #[doc = "6: Peripheral clock / 128"] + DIV128 = 6, + #[doc = "7: Peripheral clock / 256"] + DIV256 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler Configuration"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PRESCALER_A { + match self.bits { + 0 => PRESCALER_A::DIV2, + 1 => PRESCALER_A::DIV4, + 2 => PRESCALER_A::DIV8, + 3 => PRESCALER_A::DIV16, + 4 => PRESCALER_A::DIV32, + 5 => PRESCALER_A::DIV64, + 6 => PRESCALER_A::DIV128, + 7 => PRESCALER_A::DIV256, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == PRESCALER_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == PRESCALER_A::DIV128 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler Configuration"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Peripheral clock / 2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "Peripheral clock / 4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "Peripheral clock / 8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "Peripheral clock / 16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "Peripheral clock / 32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV32) + } + #[doc = "Peripheral clock / 64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "Peripheral clock / 128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV128) + } + #[doc = "Peripheral clock / 256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Prescaler Configuration"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Prescaler Configuration"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/adc0/ctrlc.rs b/pac/atsamc21e/src/adc0/ctrlc.rs new file mode 100644 index 000000000000..1b6ac5a6ea17 --- /dev/null +++ b/pac/atsamc21e/src/adc0/ctrlc.rs @@ -0,0 +1,624 @@ +#[doc = "Register `CTRLC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIFFMODE` reader - Differential Mode"] +pub struct DIFFMODE_R(crate::FieldReader); +impl DIFFMODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIFFMODE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIFFMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIFFMODE` writer - Differential Mode"] +pub struct DIFFMODE_W<'a> { + w: &'a mut W, +} +impl<'a> DIFFMODE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `LEFTADJ` reader - Left-Adjusted Result"] +pub struct LEFTADJ_R(crate::FieldReader); +impl LEFTADJ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LEFTADJ_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LEFTADJ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LEFTADJ` writer - Left-Adjusted Result"] +pub struct LEFTADJ_W<'a> { + w: &'a mut W, +} +impl<'a> LEFTADJ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `FREERUN` reader - Free Running Mode"] +pub struct FREERUN_R(crate::FieldReader); +impl FREERUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FREERUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FREERUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FREERUN` writer - Free Running Mode"] +pub struct FREERUN_W<'a> { + w: &'a mut W, +} +impl<'a> FREERUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CORREN` reader - Digital Correction Logic Enable"] +pub struct CORREN_R(crate::FieldReader); +impl CORREN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CORREN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CORREN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CORREN` writer - Digital Correction Logic Enable"] +pub struct CORREN_W<'a> { + w: &'a mut W, +} +impl<'a> CORREN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Conversion Result Resolution\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum RESSEL_A { + #[doc = "0: 12-bit"] + _12BIT = 0, + #[doc = "1: 16-bit averaging mode"] + _16BIT = 1, + #[doc = "2: 10-bit"] + _10BIT = 2, + #[doc = "3: 8-bit"] + _8BIT = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RESSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `RESSEL` reader - Conversion Result Resolution"] +pub struct RESSEL_R(crate::FieldReader); +impl RESSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RESSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RESSEL_A { + match self.bits { + 0 => RESSEL_A::_12BIT, + 1 => RESSEL_A::_16BIT, + 2 => RESSEL_A::_10BIT, + 3 => RESSEL_A::_8BIT, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `_12BIT`"] + #[inline(always)] + pub fn is_12bit(&self) -> bool { + **self == RESSEL_A::_12BIT + } + #[doc = "Checks if the value of the field is `_16BIT`"] + #[inline(always)] + pub fn is_16bit(&self) -> bool { + **self == RESSEL_A::_16BIT + } + #[doc = "Checks if the value of the field is `_10BIT`"] + #[inline(always)] + pub fn is_10bit(&self) -> bool { + **self == RESSEL_A::_10BIT + } + #[doc = "Checks if the value of the field is `_8BIT`"] + #[inline(always)] + pub fn is_8bit(&self) -> bool { + **self == RESSEL_A::_8BIT + } +} +impl core::ops::Deref for RESSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESSEL` writer - Conversion Result Resolution"] +pub struct RESSEL_W<'a> { + w: &'a mut W, +} +impl<'a> RESSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RESSEL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "12-bit"] + #[inline(always)] + pub fn _12bit(self) -> &'a mut W { + self.variant(RESSEL_A::_12BIT) + } + #[doc = "16-bit averaging mode"] + #[inline(always)] + pub fn _16bit(self) -> &'a mut W { + self.variant(RESSEL_A::_16BIT) + } + #[doc = "10-bit"] + #[inline(always)] + pub fn _10bit(self) -> &'a mut W { + self.variant(RESSEL_A::_10BIT) + } + #[doc = "8-bit"] + #[inline(always)] + pub fn _8bit(self) -> &'a mut W { + self.variant(RESSEL_A::_8BIT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u16 & 0x03) << 4); + self.w + } +} +#[doc = "Field `R2R` reader - Rail-to-Rail mode enable"] +pub struct R2R_R(crate::FieldReader); +impl R2R_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + R2R_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for R2R_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `R2R` writer - Rail-to-Rail mode enable"] +pub struct R2R_W<'a> { + w: &'a mut W, +} +impl<'a> R2R_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Window Monitor Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WINMODE_A { + #[doc = "0: No window mode (default)"] + DISABLE = 0, + #[doc = "1: RESULT > WINLT"] + MODE1 = 1, + #[doc = "2: RESULT < WINUT"] + MODE2 = 2, + #[doc = "3: WINLT < RESULT < WINUT"] + MODE3 = 3, + #[doc = "4: !(WINLT < RESULT < WINUT)"] + MODE4 = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WINMODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `WINMODE` reader - Window Monitor Mode"] +pub struct WINMODE_R(crate::FieldReader); +impl WINMODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WINMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(WINMODE_A::DISABLE), + 1 => Some(WINMODE_A::MODE1), + 2 => Some(WINMODE_A::MODE2), + 3 => Some(WINMODE_A::MODE3), + 4 => Some(WINMODE_A::MODE4), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == WINMODE_A::DISABLE + } + #[doc = "Checks if the value of the field is `MODE1`"] + #[inline(always)] + pub fn is_mode1(&self) -> bool { + **self == WINMODE_A::MODE1 + } + #[doc = "Checks if the value of the field is `MODE2`"] + #[inline(always)] + pub fn is_mode2(&self) -> bool { + **self == WINMODE_A::MODE2 + } + #[doc = "Checks if the value of the field is `MODE3`"] + #[inline(always)] + pub fn is_mode3(&self) -> bool { + **self == WINMODE_A::MODE3 + } + #[doc = "Checks if the value of the field is `MODE4`"] + #[inline(always)] + pub fn is_mode4(&self) -> bool { + **self == WINMODE_A::MODE4 + } +} +impl core::ops::Deref for WINMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMODE` writer - Window Monitor Mode"] +pub struct WINMODE_W<'a> { + w: &'a mut W, +} +impl<'a> WINMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WINMODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No window mode (default)"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(WINMODE_A::DISABLE) + } + #[doc = "RESULT > WINLT"] + #[inline(always)] + pub fn mode1(self) -> &'a mut W { + self.variant(WINMODE_A::MODE1) + } + #[doc = "RESULT < WINUT"] + #[inline(always)] + pub fn mode2(self) -> &'a mut W { + self.variant(WINMODE_A::MODE2) + } + #[doc = "WINLT < RESULT < WINUT"] + #[inline(always)] + pub fn mode3(self) -> &'a mut W { + self.variant(WINMODE_A::MODE3) + } + #[doc = "!(WINLT < RESULT < WINUT)"] + #[inline(always)] + pub fn mode4(self) -> &'a mut W { + self.variant(WINMODE_A::MODE4) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u16 & 0x07) << 8); + self.w + } +} +#[doc = "Dual Mode Trigger Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DUALSEL_A { + #[doc = "0: Start event or software trigger will start a conversion on both ADCs"] + BOTH = 0, + #[doc = "1: START event or software trigger will alternately start a conversion on ADC0 and ADC1"] + INTERLEAVE = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DUALSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `DUALSEL` reader - Dual Mode Trigger Selection"] +pub struct DUALSEL_R(crate::FieldReader); +impl DUALSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DUALSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(DUALSEL_A::BOTH), + 1 => Some(DUALSEL_A::INTERLEAVE), + _ => None, + } + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == DUALSEL_A::BOTH + } + #[doc = "Checks if the value of the field is `INTERLEAVE`"] + #[inline(always)] + pub fn is_interleave(&self) -> bool { + **self == DUALSEL_A::INTERLEAVE + } +} +impl core::ops::Deref for DUALSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DUALSEL` writer - Dual Mode Trigger Selection"] +pub struct DUALSEL_W<'a> { + w: &'a mut W, +} +impl<'a> DUALSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DUALSEL_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Start event or software trigger will start a conversion on both ADCs"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(DUALSEL_A::BOTH) + } + #[doc = "START event or software trigger will alternately start a conversion on ADC0 and ADC1"] + #[inline(always)] + pub fn interleave(self) -> &'a mut W { + self.variant(DUALSEL_A::INTERLEAVE) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 12)) | ((value as u16 & 0x03) << 12); + self.w + } +} +impl R { + #[doc = "Bit 0 - Differential Mode"] + #[inline(always)] + pub fn diffmode(&self) -> DIFFMODE_R { + DIFFMODE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Left-Adjusted Result"] + #[inline(always)] + pub fn leftadj(&self) -> LEFTADJ_R { + LEFTADJ_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Free Running Mode"] + #[inline(always)] + pub fn freerun(&self) -> FREERUN_R { + FREERUN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Digital Correction Logic Enable"] + #[inline(always)] + pub fn corren(&self) -> CORREN_R { + CORREN_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bits 4:5 - Conversion Result Resolution"] + #[inline(always)] + pub fn ressel(&self) -> RESSEL_R { + RESSEL_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bit 7 - Rail-to-Rail mode enable"] + #[inline(always)] + pub fn r2r(&self) -> R2R_R { + R2R_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Window Monitor Mode"] + #[inline(always)] + pub fn winmode(&self) -> WINMODE_R { + WINMODE_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bits 12:13 - Dual Mode Trigger Selection"] + #[inline(always)] + pub fn dualsel(&self) -> DUALSEL_R { + DUALSEL_R::new(((self.bits >> 12) & 0x03) as u8) + } +} +impl W { + #[doc = "Bit 0 - Differential Mode"] + #[inline(always)] + pub fn diffmode(&mut self) -> DIFFMODE_W { + DIFFMODE_W { w: self } + } + #[doc = "Bit 1 - Left-Adjusted Result"] + #[inline(always)] + pub fn leftadj(&mut self) -> LEFTADJ_W { + LEFTADJ_W { w: self } + } + #[doc = "Bit 2 - Free Running Mode"] + #[inline(always)] + pub fn freerun(&mut self) -> FREERUN_W { + FREERUN_W { w: self } + } + #[doc = "Bit 3 - Digital Correction Logic Enable"] + #[inline(always)] + pub fn corren(&mut self) -> CORREN_W { + CORREN_W { w: self } + } + #[doc = "Bits 4:5 - Conversion Result Resolution"] + #[inline(always)] + pub fn ressel(&mut self) -> RESSEL_W { + RESSEL_W { w: self } + } + #[doc = "Bit 7 - Rail-to-Rail mode enable"] + #[inline(always)] + pub fn r2r(&mut self) -> R2R_W { + R2R_W { w: self } + } + #[doc = "Bits 8:10 - Window Monitor Mode"] + #[inline(always)] + pub fn winmode(&mut self) -> WINMODE_W { + WINMODE_W { w: self } + } + #[doc = "Bits 12:13 - Dual Mode Trigger Selection"] + #[inline(always)] + pub fn dualsel(&mut self) -> DUALSEL_W { + DUALSEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control C\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlc](index.html) module"] +pub struct CTRLC_SPEC; +impl crate::RegisterSpec for CTRLC_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrlc::R](R) reader structure"] +impl crate::Readable for CTRLC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlc::W](W) writer structure"] +impl crate::Writable for CTRLC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLC to value 0"] +impl crate::Resettable for CTRLC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/adc0/dbgctrl.rs b/pac/atsamc21e/src/adc0/dbgctrl.rs new file mode 100644 index 000000000000..53636eb2b339 --- /dev/null +++ b/pac/atsamc21e/src/adc0/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Debug Run"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Debug Run"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/adc0/evctrl.rs b/pac/atsamc21e/src/adc0/evctrl.rs new file mode 100644 index 000000000000..295508f82de3 --- /dev/null +++ b/pac/atsamc21e/src/adc0/evctrl.rs @@ -0,0 +1,348 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FLUSHEI` reader - Flush Event Input Enable"] +pub struct FLUSHEI_R(crate::FieldReader); +impl FLUSHEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FLUSHEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FLUSHEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLUSHEI` writer - Flush Event Input Enable"] +pub struct FLUSHEI_W<'a> { + w: &'a mut W, +} +impl<'a> FLUSHEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `STARTEI` reader - Start Conversion Event Input Enable"] +pub struct STARTEI_R(crate::FieldReader); +impl STARTEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STARTEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STARTEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STARTEI` writer - Start Conversion Event Input Enable"] +pub struct STARTEI_W<'a> { + w: &'a mut W, +} +impl<'a> STARTEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `FLUSHINV` reader - Flush Event Invert Enable"] +pub struct FLUSHINV_R(crate::FieldReader); +impl FLUSHINV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FLUSHINV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FLUSHINV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLUSHINV` writer - Flush Event Invert Enable"] +pub struct FLUSHINV_W<'a> { + w: &'a mut W, +} +impl<'a> FLUSHINV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `STARTINV` reader - Start Event Invert Enable"] +pub struct STARTINV_R(crate::FieldReader); +impl STARTINV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STARTINV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STARTINV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STARTINV` writer - Start Event Invert Enable"] +pub struct STARTINV_W<'a> { + w: &'a mut W, +} +impl<'a> STARTINV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `RESRDYEO` reader - Result Ready Event Out"] +pub struct RESRDYEO_R(crate::FieldReader); +impl RESRDYEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESRDYEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESRDYEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESRDYEO` writer - Result Ready Event Out"] +pub struct RESRDYEO_W<'a> { + w: &'a mut W, +} +impl<'a> RESRDYEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `WINMONEO` reader - Window Monitor Event Out"] +pub struct WINMONEO_R(crate::FieldReader); +impl WINMONEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINMONEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINMONEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMONEO` writer - Window Monitor Event Out"] +pub struct WINMONEO_W<'a> { + w: &'a mut W, +} +impl<'a> WINMONEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Flush Event Input Enable"] + #[inline(always)] + pub fn flushei(&self) -> FLUSHEI_R { + FLUSHEI_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Start Conversion Event Input Enable"] + #[inline(always)] + pub fn startei(&self) -> STARTEI_R { + STARTEI_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Flush Event Invert Enable"] + #[inline(always)] + pub fn flushinv(&self) -> FLUSHINV_R { + FLUSHINV_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Start Event Invert Enable"] + #[inline(always)] + pub fn startinv(&self) -> STARTINV_R { + STARTINV_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Result Ready Event Out"] + #[inline(always)] + pub fn resrdyeo(&self) -> RESRDYEO_R { + RESRDYEO_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Window Monitor Event Out"] + #[inline(always)] + pub fn winmoneo(&self) -> WINMONEO_R { + WINMONEO_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Flush Event Input Enable"] + #[inline(always)] + pub fn flushei(&mut self) -> FLUSHEI_W { + FLUSHEI_W { w: self } + } + #[doc = "Bit 1 - Start Conversion Event Input Enable"] + #[inline(always)] + pub fn startei(&mut self) -> STARTEI_W { + STARTEI_W { w: self } + } + #[doc = "Bit 2 - Flush Event Invert Enable"] + #[inline(always)] + pub fn flushinv(&mut self) -> FLUSHINV_W { + FLUSHINV_W { w: self } + } + #[doc = "Bit 3 - Start Event Invert Enable"] + #[inline(always)] + pub fn startinv(&mut self) -> STARTINV_W { + STARTINV_W { w: self } + } + #[doc = "Bit 4 - Result Ready Event Out"] + #[inline(always)] + pub fn resrdyeo(&mut self) -> RESRDYEO_W { + RESRDYEO_W { w: self } + } + #[doc = "Bit 5 - Window Monitor Event Out"] + #[inline(always)] + pub fn winmoneo(&mut self) -> WINMONEO_W { + WINMONEO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/adc0/gaincorr.rs b/pac/atsamc21e/src/adc0/gaincorr.rs new file mode 100644 index 000000000000..496cb8c6021c --- /dev/null +++ b/pac/atsamc21e/src/adc0/gaincorr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `GAINCORR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GAINCORR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `GAINCORR` reader - Gain Correction Value"] +pub struct GAINCORR_R(crate::FieldReader); +impl GAINCORR_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + GAINCORR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GAINCORR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GAINCORR` writer - Gain Correction Value"] +pub struct GAINCORR_W<'a> { + w: &'a mut W, +} +impl<'a> GAINCORR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0fff) | (value as u16 & 0x0fff); + self.w + } +} +impl R { + #[doc = "Bits 0:11 - Gain Correction Value"] + #[inline(always)] + pub fn gaincorr(&self) -> GAINCORR_R { + GAINCORR_R::new((self.bits & 0x0fff) as u16) + } +} +impl W { + #[doc = "Bits 0:11 - Gain Correction Value"] + #[inline(always)] + pub fn gaincorr(&mut self) -> GAINCORR_W { + GAINCORR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Gain Correction\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gaincorr](index.html) module"] +pub struct GAINCORR_SPEC; +impl crate::RegisterSpec for GAINCORR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [gaincorr::R](R) reader structure"] +impl crate::Readable for GAINCORR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gaincorr::W](W) writer structure"] +impl crate::Writable for GAINCORR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets GAINCORR to value 0"] +impl crate::Resettable for GAINCORR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/adc0/inputctrl.rs b/pac/atsamc21e/src/adc0/inputctrl.rs new file mode 100644 index 000000000000..82367a5d38c7 --- /dev/null +++ b/pac/atsamc21e/src/adc0/inputctrl.rs @@ -0,0 +1,485 @@ +#[doc = "Register `INPUTCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INPUTCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Positive Mux Input Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MUXPOS_A { + #[doc = "0: ADC AIN0 Pin"] + AIN0 = 0, + #[doc = "1: ADC AIN1 Pin"] + AIN1 = 1, + #[doc = "2: ADC AIN2 Pin"] + AIN2 = 2, + #[doc = "3: ADC AIN3 Pin"] + AIN3 = 3, + #[doc = "4: ADC AIN4 Pin"] + AIN4 = 4, + #[doc = "5: ADC AIN5 Pin"] + AIN5 = 5, + #[doc = "6: ADC AIN6 Pin"] + AIN6 = 6, + #[doc = "7: ADC AIN7 Pin"] + AIN7 = 7, + #[doc = "8: ADC AIN8 Pin"] + AIN8 = 8, + #[doc = "9: ADC AIN9 Pin"] + AIN9 = 9, + #[doc = "10: ADC AIN10 Pin"] + AIN10 = 10, + #[doc = "11: ADC AIN11 Pin"] + AIN11 = 11, + #[doc = "25: Bandgap Voltage"] + BANDGAP = 25, + #[doc = "26: 1/4 Scaled Core Supply"] + SCALEDCOREVCC = 26, + #[doc = "27: 1/4 Scaled I/O Supply"] + SCALEDIOVCC = 27, + #[doc = "28: DAC Output"] + DAC = 28, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MUXPOS_A) -> Self { + variant as _ + } +} +#[doc = "Field `MUXPOS` reader - Positive Mux Input Selection"] +pub struct MUXPOS_R(crate::FieldReader); +impl MUXPOS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MUXPOS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MUXPOS_A::AIN0), + 1 => Some(MUXPOS_A::AIN1), + 2 => Some(MUXPOS_A::AIN2), + 3 => Some(MUXPOS_A::AIN3), + 4 => Some(MUXPOS_A::AIN4), + 5 => Some(MUXPOS_A::AIN5), + 6 => Some(MUXPOS_A::AIN6), + 7 => Some(MUXPOS_A::AIN7), + 8 => Some(MUXPOS_A::AIN8), + 9 => Some(MUXPOS_A::AIN9), + 10 => Some(MUXPOS_A::AIN10), + 11 => Some(MUXPOS_A::AIN11), + 25 => Some(MUXPOS_A::BANDGAP), + 26 => Some(MUXPOS_A::SCALEDCOREVCC), + 27 => Some(MUXPOS_A::SCALEDIOVCC), + 28 => Some(MUXPOS_A::DAC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `AIN0`"] + #[inline(always)] + pub fn is_ain0(&self) -> bool { + **self == MUXPOS_A::AIN0 + } + #[doc = "Checks if the value of the field is `AIN1`"] + #[inline(always)] + pub fn is_ain1(&self) -> bool { + **self == MUXPOS_A::AIN1 + } + #[doc = "Checks if the value of the field is `AIN2`"] + #[inline(always)] + pub fn is_ain2(&self) -> bool { + **self == MUXPOS_A::AIN2 + } + #[doc = "Checks if the value of the field is `AIN3`"] + #[inline(always)] + pub fn is_ain3(&self) -> bool { + **self == MUXPOS_A::AIN3 + } + #[doc = "Checks if the value of the field is `AIN4`"] + #[inline(always)] + pub fn is_ain4(&self) -> bool { + **self == MUXPOS_A::AIN4 + } + #[doc = "Checks if the value of the field is `AIN5`"] + #[inline(always)] + pub fn is_ain5(&self) -> bool { + **self == MUXPOS_A::AIN5 + } + #[doc = "Checks if the value of the field is `AIN6`"] + #[inline(always)] + pub fn is_ain6(&self) -> bool { + **self == MUXPOS_A::AIN6 + } + #[doc = "Checks if the value of the field is `AIN7`"] + #[inline(always)] + pub fn is_ain7(&self) -> bool { + **self == MUXPOS_A::AIN7 + } + #[doc = "Checks if the value of the field is `AIN8`"] + #[inline(always)] + pub fn is_ain8(&self) -> bool { + **self == MUXPOS_A::AIN8 + } + #[doc = "Checks if the value of the field is `AIN9`"] + #[inline(always)] + pub fn is_ain9(&self) -> bool { + **self == MUXPOS_A::AIN9 + } + #[doc = "Checks if the value of the field is `AIN10`"] + #[inline(always)] + pub fn is_ain10(&self) -> bool { + **self == MUXPOS_A::AIN10 + } + #[doc = "Checks if the value of the field is `AIN11`"] + #[inline(always)] + pub fn is_ain11(&self) -> bool { + **self == MUXPOS_A::AIN11 + } + #[doc = "Checks if the value of the field is `BANDGAP`"] + #[inline(always)] + pub fn is_bandgap(&self) -> bool { + **self == MUXPOS_A::BANDGAP + } + #[doc = "Checks if the value of the field is `SCALEDCOREVCC`"] + #[inline(always)] + pub fn is_scaledcorevcc(&self) -> bool { + **self == MUXPOS_A::SCALEDCOREVCC + } + #[doc = "Checks if the value of the field is `SCALEDIOVCC`"] + #[inline(always)] + pub fn is_scalediovcc(&self) -> bool { + **self == MUXPOS_A::SCALEDIOVCC + } + #[doc = "Checks if the value of the field is `DAC`"] + #[inline(always)] + pub fn is_dac(&self) -> bool { + **self == MUXPOS_A::DAC + } +} +impl core::ops::Deref for MUXPOS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MUXPOS` writer - Positive Mux Input Selection"] +pub struct MUXPOS_W<'a> { + w: &'a mut W, +} +impl<'a> MUXPOS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MUXPOS_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "ADC AIN0 Pin"] + #[inline(always)] + pub fn ain0(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN0) + } + #[doc = "ADC AIN1 Pin"] + #[inline(always)] + pub fn ain1(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN1) + } + #[doc = "ADC AIN2 Pin"] + #[inline(always)] + pub fn ain2(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN2) + } + #[doc = "ADC AIN3 Pin"] + #[inline(always)] + pub fn ain3(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN3) + } + #[doc = "ADC AIN4 Pin"] + #[inline(always)] + pub fn ain4(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN4) + } + #[doc = "ADC AIN5 Pin"] + #[inline(always)] + pub fn ain5(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN5) + } + #[doc = "ADC AIN6 Pin"] + #[inline(always)] + pub fn ain6(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN6) + } + #[doc = "ADC AIN7 Pin"] + #[inline(always)] + pub fn ain7(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN7) + } + #[doc = "ADC AIN8 Pin"] + #[inline(always)] + pub fn ain8(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN8) + } + #[doc = "ADC AIN9 Pin"] + #[inline(always)] + pub fn ain9(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN9) + } + #[doc = "ADC AIN10 Pin"] + #[inline(always)] + pub fn ain10(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN10) + } + #[doc = "ADC AIN11 Pin"] + #[inline(always)] + pub fn ain11(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN11) + } + #[doc = "Bandgap Voltage"] + #[inline(always)] + pub fn bandgap(self) -> &'a mut W { + self.variant(MUXPOS_A::BANDGAP) + } + #[doc = "1/4 Scaled Core Supply"] + #[inline(always)] + pub fn scaledcorevcc(self) -> &'a mut W { + self.variant(MUXPOS_A::SCALEDCOREVCC) + } + #[doc = "1/4 Scaled I/O Supply"] + #[inline(always)] + pub fn scalediovcc(self) -> &'a mut W { + self.variant(MUXPOS_A::SCALEDIOVCC) + } + #[doc = "DAC Output"] + #[inline(always)] + pub fn dac(self) -> &'a mut W { + self.variant(MUXPOS_A::DAC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u16 & 0x1f); + self.w + } +} +#[doc = "Negative Mux Input Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MUXNEG_A { + #[doc = "0: ADC AIN0 Pin"] + AIN0 = 0, + #[doc = "1: ADC AIN1 Pin"] + AIN1 = 1, + #[doc = "2: ADC AIN2 Pin"] + AIN2 = 2, + #[doc = "3: ADC AIN3 Pin"] + AIN3 = 3, + #[doc = "4: ADC AIN4 Pin"] + AIN4 = 4, + #[doc = "5: ADC AIN5 Pin"] + AIN5 = 5, + #[doc = "24: Internal Ground"] + GND = 24, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MUXNEG_A) -> Self { + variant as _ + } +} +#[doc = "Field `MUXNEG` reader - Negative Mux Input Selection"] +pub struct MUXNEG_R(crate::FieldReader); +impl MUXNEG_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MUXNEG_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MUXNEG_A::AIN0), + 1 => Some(MUXNEG_A::AIN1), + 2 => Some(MUXNEG_A::AIN2), + 3 => Some(MUXNEG_A::AIN3), + 4 => Some(MUXNEG_A::AIN4), + 5 => Some(MUXNEG_A::AIN5), + 24 => Some(MUXNEG_A::GND), + _ => None, + } + } + #[doc = "Checks if the value of the field is `AIN0`"] + #[inline(always)] + pub fn is_ain0(&self) -> bool { + **self == MUXNEG_A::AIN0 + } + #[doc = "Checks if the value of the field is `AIN1`"] + #[inline(always)] + pub fn is_ain1(&self) -> bool { + **self == MUXNEG_A::AIN1 + } + #[doc = "Checks if the value of the field is `AIN2`"] + #[inline(always)] + pub fn is_ain2(&self) -> bool { + **self == MUXNEG_A::AIN2 + } + #[doc = "Checks if the value of the field is `AIN3`"] + #[inline(always)] + pub fn is_ain3(&self) -> bool { + **self == MUXNEG_A::AIN3 + } + #[doc = "Checks if the value of the field is `AIN4`"] + #[inline(always)] + pub fn is_ain4(&self) -> bool { + **self == MUXNEG_A::AIN4 + } + #[doc = "Checks if the value of the field is `AIN5`"] + #[inline(always)] + pub fn is_ain5(&self) -> bool { + **self == MUXNEG_A::AIN5 + } + #[doc = "Checks if the value of the field is `GND`"] + #[inline(always)] + pub fn is_gnd(&self) -> bool { + **self == MUXNEG_A::GND + } +} +impl core::ops::Deref for MUXNEG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MUXNEG` writer - Negative Mux Input Selection"] +pub struct MUXNEG_W<'a> { + w: &'a mut W, +} +impl<'a> MUXNEG_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MUXNEG_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "ADC AIN0 Pin"] + #[inline(always)] + pub fn ain0(self) -> &'a mut W { + self.variant(MUXNEG_A::AIN0) + } + #[doc = "ADC AIN1 Pin"] + #[inline(always)] + pub fn ain1(self) -> &'a mut W { + self.variant(MUXNEG_A::AIN1) + } + #[doc = "ADC AIN2 Pin"] + #[inline(always)] + pub fn ain2(self) -> &'a mut W { + self.variant(MUXNEG_A::AIN2) + } + #[doc = "ADC AIN3 Pin"] + #[inline(always)] + pub fn ain3(self) -> &'a mut W { + self.variant(MUXNEG_A::AIN3) + } + #[doc = "ADC AIN4 Pin"] + #[inline(always)] + pub fn ain4(self) -> &'a mut W { + self.variant(MUXNEG_A::AIN4) + } + #[doc = "ADC AIN5 Pin"] + #[inline(always)] + pub fn ain5(self) -> &'a mut W { + self.variant(MUXNEG_A::AIN5) + } + #[doc = "Internal Ground"] + #[inline(always)] + pub fn gnd(self) -> &'a mut W { + self.variant(MUXNEG_A::GND) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 8)) | ((value as u16 & 0x1f) << 8); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Positive Mux Input Selection"] + #[inline(always)] + pub fn muxpos(&self) -> MUXPOS_R { + MUXPOS_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 8:12 - Negative Mux Input Selection"] + #[inline(always)] + pub fn muxneg(&self) -> MUXNEG_R { + MUXNEG_R::new(((self.bits >> 8) & 0x1f) as u8) + } +} +impl W { + #[doc = "Bits 0:4 - Positive Mux Input Selection"] + #[inline(always)] + pub fn muxpos(&mut self) -> MUXPOS_W { + MUXPOS_W { w: self } + } + #[doc = "Bits 8:12 - Negative Mux Input Selection"] + #[inline(always)] + pub fn muxneg(&mut self) -> MUXNEG_W { + MUXNEG_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Input Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [inputctrl](index.html) module"] +pub struct INPUTCTRL_SPEC; +impl crate::RegisterSpec for INPUTCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [inputctrl::R](R) reader structure"] +impl crate::Readable for INPUTCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [inputctrl::W](W) writer structure"] +impl crate::Writable for INPUTCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INPUTCTRL to value 0"] +impl crate::Resettable for INPUTCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/adc0/intenclr.rs b/pac/atsamc21e/src/adc0/intenclr.rs new file mode 100644 index 000000000000..b10f428d30b1 --- /dev/null +++ b/pac/atsamc21e/src/adc0/intenclr.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RESRDY` reader - Result Ready Interrupt Disable"] +pub struct RESRDY_R(crate::FieldReader); +impl RESRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESRDY` writer - Result Ready Interrupt Disable"] +pub struct RESRDY_W<'a> { + w: &'a mut W, +} +impl<'a> RESRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `OVERRUN` reader - Overrun Interrupt Disable"] +pub struct OVERRUN_R(crate::FieldReader); +impl OVERRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVERRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVERRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVERRUN` writer - Overrun Interrupt Disable"] +pub struct OVERRUN_W<'a> { + w: &'a mut W, +} +impl<'a> OVERRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WINMON` reader - Window Monitor Interrupt Disable"] +pub struct WINMON_R(crate::FieldReader); +impl WINMON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINMON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINMON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMON` writer - Window Monitor Interrupt Disable"] +pub struct WINMON_W<'a> { + w: &'a mut W, +} +impl<'a> WINMON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Result Ready Interrupt Disable"] + #[inline(always)] + pub fn resrdy(&self) -> RESRDY_R { + RESRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Overrun Interrupt Disable"] + #[inline(always)] + pub fn overrun(&self) -> OVERRUN_R { + OVERRUN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Window Monitor Interrupt Disable"] + #[inline(always)] + pub fn winmon(&self) -> WINMON_R { + WINMON_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Result Ready Interrupt Disable"] + #[inline(always)] + pub fn resrdy(&mut self) -> RESRDY_W { + RESRDY_W { w: self } + } + #[doc = "Bit 1 - Overrun Interrupt Disable"] + #[inline(always)] + pub fn overrun(&mut self) -> OVERRUN_W { + OVERRUN_W { w: self } + } + #[doc = "Bit 2 - Window Monitor Interrupt Disable"] + #[inline(always)] + pub fn winmon(&mut self) -> WINMON_W { + WINMON_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/adc0/intenset.rs b/pac/atsamc21e/src/adc0/intenset.rs new file mode 100644 index 000000000000..5ca93b05b859 --- /dev/null +++ b/pac/atsamc21e/src/adc0/intenset.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RESRDY` reader - Result Ready Interrupt Enable"] +pub struct RESRDY_R(crate::FieldReader); +impl RESRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESRDY` writer - Result Ready Interrupt Enable"] +pub struct RESRDY_W<'a> { + w: &'a mut W, +} +impl<'a> RESRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `OVERRUN` reader - Overrun Interrupt Enable"] +pub struct OVERRUN_R(crate::FieldReader); +impl OVERRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVERRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVERRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVERRUN` writer - Overrun Interrupt Enable"] +pub struct OVERRUN_W<'a> { + w: &'a mut W, +} +impl<'a> OVERRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WINMON` reader - Window Monitor Interrupt Enable"] +pub struct WINMON_R(crate::FieldReader); +impl WINMON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINMON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINMON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMON` writer - Window Monitor Interrupt Enable"] +pub struct WINMON_W<'a> { + w: &'a mut W, +} +impl<'a> WINMON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Result Ready Interrupt Enable"] + #[inline(always)] + pub fn resrdy(&self) -> RESRDY_R { + RESRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Overrun Interrupt Enable"] + #[inline(always)] + pub fn overrun(&self) -> OVERRUN_R { + OVERRUN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Window Monitor Interrupt Enable"] + #[inline(always)] + pub fn winmon(&self) -> WINMON_R { + WINMON_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Result Ready Interrupt Enable"] + #[inline(always)] + pub fn resrdy(&mut self) -> RESRDY_W { + RESRDY_W { w: self } + } + #[doc = "Bit 1 - Overrun Interrupt Enable"] + #[inline(always)] + pub fn overrun(&mut self) -> OVERRUN_W { + OVERRUN_W { w: self } + } + #[doc = "Bit 2 - Window Monitor Interrupt Enable"] + #[inline(always)] + pub fn winmon(&mut self) -> WINMON_W { + WINMON_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/adc0/intflag.rs b/pac/atsamc21e/src/adc0/intflag.rs new file mode 100644 index 000000000000..3cd74788b226 --- /dev/null +++ b/pac/atsamc21e/src/adc0/intflag.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RESRDY` reader - Result Ready Interrupt Flag"] +pub struct RESRDY_R(crate::FieldReader); +impl RESRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESRDY` writer - Result Ready Interrupt Flag"] +pub struct RESRDY_W<'a> { + w: &'a mut W, +} +impl<'a> RESRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `OVERRUN` reader - Overrun Interrupt Flag"] +pub struct OVERRUN_R(crate::FieldReader); +impl OVERRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVERRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVERRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVERRUN` writer - Overrun Interrupt Flag"] +pub struct OVERRUN_W<'a> { + w: &'a mut W, +} +impl<'a> OVERRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WINMON` reader - Window Monitor Interrupt Flag"] +pub struct WINMON_R(crate::FieldReader); +impl WINMON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINMON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINMON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMON` writer - Window Monitor Interrupt Flag"] +pub struct WINMON_W<'a> { + w: &'a mut W, +} +impl<'a> WINMON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Result Ready Interrupt Flag"] + #[inline(always)] + pub fn resrdy(&self) -> RESRDY_R { + RESRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Overrun Interrupt Flag"] + #[inline(always)] + pub fn overrun(&self) -> OVERRUN_R { + OVERRUN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Window Monitor Interrupt Flag"] + #[inline(always)] + pub fn winmon(&self) -> WINMON_R { + WINMON_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Result Ready Interrupt Flag"] + #[inline(always)] + pub fn resrdy(&mut self) -> RESRDY_W { + RESRDY_W { w: self } + } + #[doc = "Bit 1 - Overrun Interrupt Flag"] + #[inline(always)] + pub fn overrun(&mut self) -> OVERRUN_W { + OVERRUN_W { w: self } + } + #[doc = "Bit 2 - Window Monitor Interrupt Flag"] + #[inline(always)] + pub fn winmon(&mut self) -> WINMON_W { + WINMON_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/adc0/offsetcorr.rs b/pac/atsamc21e/src/adc0/offsetcorr.rs new file mode 100644 index 000000000000..24a97427c64e --- /dev/null +++ b/pac/atsamc21e/src/adc0/offsetcorr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `OFFSETCORR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OFFSETCORR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OFFSETCORR` reader - Offset Correction Value"] +pub struct OFFSETCORR_R(crate::FieldReader); +impl OFFSETCORR_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + OFFSETCORR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OFFSETCORR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OFFSETCORR` writer - Offset Correction Value"] +pub struct OFFSETCORR_W<'a> { + w: &'a mut W, +} +impl<'a> OFFSETCORR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0fff) | (value as u16 & 0x0fff); + self.w + } +} +impl R { + #[doc = "Bits 0:11 - Offset Correction Value"] + #[inline(always)] + pub fn offsetcorr(&self) -> OFFSETCORR_R { + OFFSETCORR_R::new((self.bits & 0x0fff) as u16) + } +} +impl W { + #[doc = "Bits 0:11 - Offset Correction Value"] + #[inline(always)] + pub fn offsetcorr(&mut self) -> OFFSETCORR_W { + OFFSETCORR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Offset Correction\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [offsetcorr](index.html) module"] +pub struct OFFSETCORR_SPEC; +impl crate::RegisterSpec for OFFSETCORR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [offsetcorr::R](R) reader structure"] +impl crate::Readable for OFFSETCORR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [offsetcorr::W](W) writer structure"] +impl crate::Writable for OFFSETCORR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OFFSETCORR to value 0"] +impl crate::Resettable for OFFSETCORR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/adc0/refctrl.rs b/pac/atsamc21e/src/adc0/refctrl.rs new file mode 100644 index 000000000000..007d86e306bc --- /dev/null +++ b/pac/atsamc21e/src/adc0/refctrl.rs @@ -0,0 +1,251 @@ +#[doc = "Register `REFCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `REFCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Reference Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum REFSEL_A { + #[doc = "0: Internal Bandgap Reference"] + INTREF = 0, + #[doc = "1: 1/1.6 VDDANA"] + INTVCC0 = 1, + #[doc = "2: 1/2 VDDANA"] + INTVCC1 = 2, + #[doc = "3: External Reference"] + AREFA = 3, + #[doc = "4: DAC"] + DAC = 4, + #[doc = "5: VDDANA"] + INTVCC2 = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: REFSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `REFSEL` reader - Reference Selection"] +pub struct REFSEL_R(crate::FieldReader); +impl REFSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REFSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(REFSEL_A::INTREF), + 1 => Some(REFSEL_A::INTVCC0), + 2 => Some(REFSEL_A::INTVCC1), + 3 => Some(REFSEL_A::AREFA), + 4 => Some(REFSEL_A::DAC), + 5 => Some(REFSEL_A::INTVCC2), + _ => None, + } + } + #[doc = "Checks if the value of the field is `INTREF`"] + #[inline(always)] + pub fn is_intref(&self) -> bool { + **self == REFSEL_A::INTREF + } + #[doc = "Checks if the value of the field is `INTVCC0`"] + #[inline(always)] + pub fn is_intvcc0(&self) -> bool { + **self == REFSEL_A::INTVCC0 + } + #[doc = "Checks if the value of the field is `INTVCC1`"] + #[inline(always)] + pub fn is_intvcc1(&self) -> bool { + **self == REFSEL_A::INTVCC1 + } + #[doc = "Checks if the value of the field is `AREFA`"] + #[inline(always)] + pub fn is_arefa(&self) -> bool { + **self == REFSEL_A::AREFA + } + #[doc = "Checks if the value of the field is `DAC`"] + #[inline(always)] + pub fn is_dac(&self) -> bool { + **self == REFSEL_A::DAC + } + #[doc = "Checks if the value of the field is `INTVCC2`"] + #[inline(always)] + pub fn is_intvcc2(&self) -> bool { + **self == REFSEL_A::INTVCC2 + } +} +impl core::ops::Deref for REFSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REFSEL` writer - Reference Selection"] +pub struct REFSEL_W<'a> { + w: &'a mut W, +} +impl<'a> REFSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: REFSEL_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Internal Bandgap Reference"] + #[inline(always)] + pub fn intref(self) -> &'a mut W { + self.variant(REFSEL_A::INTREF) + } + #[doc = "1/1.6 VDDANA"] + #[inline(always)] + pub fn intvcc0(self) -> &'a mut W { + self.variant(REFSEL_A::INTVCC0) + } + #[doc = "1/2 VDDANA"] + #[inline(always)] + pub fn intvcc1(self) -> &'a mut W { + self.variant(REFSEL_A::INTVCC1) + } + #[doc = "External Reference"] + #[inline(always)] + pub fn arefa(self) -> &'a mut W { + self.variant(REFSEL_A::AREFA) + } + #[doc = "DAC"] + #[inline(always)] + pub fn dac(self) -> &'a mut W { + self.variant(REFSEL_A::DAC) + } + #[doc = "VDDANA"] + #[inline(always)] + pub fn intvcc2(self) -> &'a mut W { + self.variant(REFSEL_A::INTVCC2) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +#[doc = "Field `REFCOMP` reader - Reference Buffer Offset Compensation Enable"] +pub struct REFCOMP_R(crate::FieldReader); +impl REFCOMP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + REFCOMP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REFCOMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REFCOMP` writer - Reference Buffer Offset Compensation Enable"] +pub struct REFCOMP_W<'a> { + w: &'a mut W, +} +impl<'a> REFCOMP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Reference Selection"] + #[inline(always)] + pub fn refsel(&self) -> REFSEL_R { + REFSEL_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 7 - Reference Buffer Offset Compensation Enable"] + #[inline(always)] + pub fn refcomp(&self) -> REFCOMP_R { + REFCOMP_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Reference Selection"] + #[inline(always)] + pub fn refsel(&mut self) -> REFSEL_W { + REFSEL_W { w: self } + } + #[doc = "Bit 7 - Reference Buffer Offset Compensation Enable"] + #[inline(always)] + pub fn refcomp(&mut self) -> REFCOMP_W { + REFCOMP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Reference Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [refctrl](index.html) module"] +pub struct REFCTRL_SPEC; +impl crate::RegisterSpec for REFCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [refctrl::R](R) reader structure"] +impl crate::Readable for REFCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [refctrl::W](W) writer structure"] +impl crate::Writable for REFCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets REFCTRL to value 0"] +impl crate::Resettable for REFCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/adc0/result.rs b/pac/atsamc21e/src/adc0/result.rs new file mode 100644 index 000000000000..b63b08cc72b9 --- /dev/null +++ b/pac/atsamc21e/src/adc0/result.rs @@ -0,0 +1,53 @@ +#[doc = "Register `RESULT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `RESULT` reader - Result Value"] +pub struct RESULT_R(crate::FieldReader); +impl RESULT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + RESULT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESULT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:15 - Result Value"] + #[inline(always)] + pub fn result(&self) -> RESULT_R { + RESULT_R::new(self.bits as u16) + } +} +#[doc = "Result\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [result](index.html) module"] +pub struct RESULT_SPEC; +impl crate::RegisterSpec for RESULT_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [result::R](R) reader structure"] +impl crate::Readable for RESULT_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets RESULT to value 0"] +impl crate::Resettable for RESULT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/adc0/sampctrl.rs b/pac/atsamc21e/src/adc0/sampctrl.rs new file mode 100644 index 000000000000..be4b77a80410 --- /dev/null +++ b/pac/atsamc21e/src/adc0/sampctrl.rs @@ -0,0 +1,150 @@ +#[doc = "Register `SAMPCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SAMPCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SAMPLEN` reader - Sampling Time Length"] +pub struct SAMPLEN_R(crate::FieldReader); +impl SAMPLEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SAMPLEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SAMPLEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SAMPLEN` writer - Sampling Time Length"] +pub struct SAMPLEN_W<'a> { + w: &'a mut W, +} +impl<'a> SAMPLEN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u8 & 0x3f); + self.w + } +} +#[doc = "Field `OFFCOMP` reader - Comparator Offset Compensation Enable"] +pub struct OFFCOMP_R(crate::FieldReader); +impl OFFCOMP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OFFCOMP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OFFCOMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OFFCOMP` writer - Comparator Offset Compensation Enable"] +pub struct OFFCOMP_W<'a> { + w: &'a mut W, +} +impl<'a> OFFCOMP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Sampling Time Length"] + #[inline(always)] + pub fn samplen(&self) -> SAMPLEN_R { + SAMPLEN_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 7 - Comparator Offset Compensation Enable"] + #[inline(always)] + pub fn offcomp(&self) -> OFFCOMP_R { + OFFCOMP_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:5 - Sampling Time Length"] + #[inline(always)] + pub fn samplen(&mut self) -> SAMPLEN_W { + SAMPLEN_W { w: self } + } + #[doc = "Bit 7 - Comparator Offset Compensation Enable"] + #[inline(always)] + pub fn offcomp(&mut self) -> OFFCOMP_W { + OFFCOMP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Sample Time Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sampctrl](index.html) module"] +pub struct SAMPCTRL_SPEC; +impl crate::RegisterSpec for SAMPCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [sampctrl::R](R) reader structure"] +impl crate::Readable for SAMPCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [sampctrl::W](W) writer structure"] +impl crate::Writable for SAMPCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SAMPCTRL to value 0"] +impl crate::Resettable for SAMPCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/adc0/seqctrl.rs b/pac/atsamc21e/src/adc0/seqctrl.rs new file mode 100644 index 000000000000..c8388c9a393f --- /dev/null +++ b/pac/atsamc21e/src/adc0/seqctrl.rs @@ -0,0 +1,103 @@ +#[doc = "Register `SEQCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SEQCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SEQEN` reader - Enable Positive Input in the Sequence"] +pub struct SEQEN_R(crate::FieldReader); +impl SEQEN_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + SEQEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEQEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEQEN` writer - Enable Positive Input in the Sequence"] +pub struct SEQEN_W<'a> { + w: &'a mut W, +} +impl<'a> SEQEN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Enable Positive Input in the Sequence"] + #[inline(always)] + pub fn seqen(&self) -> SEQEN_R { + SEQEN_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Enable Positive Input in the Sequence"] + #[inline(always)] + pub fn seqen(&mut self) -> SEQEN_W { + SEQEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Sequence Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [seqctrl](index.html) module"] +pub struct SEQCTRL_SPEC; +impl crate::RegisterSpec for SEQCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [seqctrl::R](R) reader structure"] +impl crate::Readable for SEQCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [seqctrl::W](W) writer structure"] +impl crate::Writable for SEQCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SEQCTRL to value 0"] +impl crate::Resettable for SEQCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/adc0/seqstatus.rs b/pac/atsamc21e/src/adc0/seqstatus.rs new file mode 100644 index 000000000000..42c820892e9a --- /dev/null +++ b/pac/atsamc21e/src/adc0/seqstatus.rs @@ -0,0 +1,73 @@ +#[doc = "Register `SEQSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SEQSTATE` reader - Sequence State"] +pub struct SEQSTATE_R(crate::FieldReader); +impl SEQSTATE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SEQSTATE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEQSTATE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEQBUSY` reader - Sequence Busy"] +pub struct SEQBUSY_R(crate::FieldReader); +impl SEQBUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SEQBUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEQBUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:4 - Sequence State"] + #[inline(always)] + pub fn seqstate(&self) -> SEQSTATE_R { + SEQSTATE_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bit 7 - Sequence Busy"] + #[inline(always)] + pub fn seqbusy(&self) -> SEQBUSY_R { + SEQBUSY_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +#[doc = "Sequence Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [seqstatus](index.html) module"] +pub struct SEQSTATUS_SPEC; +impl crate::RegisterSpec for SEQSTATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [seqstatus::R](R) reader structure"] +impl crate::Readable for SEQSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SEQSTATUS to value 0"] +impl crate::Resettable for SEQSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/adc0/swtrig.rs b/pac/atsamc21e/src/adc0/swtrig.rs new file mode 100644 index 000000000000..5e23ed7865ed --- /dev/null +++ b/pac/atsamc21e/src/adc0/swtrig.rs @@ -0,0 +1,160 @@ +#[doc = "Register `SWTRIG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SWTRIG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FLUSH` reader - ADC Flush"] +pub struct FLUSH_R(crate::FieldReader); +impl FLUSH_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FLUSH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FLUSH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLUSH` writer - ADC Flush"] +pub struct FLUSH_W<'a> { + w: &'a mut W, +} +impl<'a> FLUSH_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `START` reader - Start ADC Conversion"] +pub struct START_R(crate::FieldReader); +impl START_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + START_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for START_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `START` writer - Start ADC Conversion"] +pub struct START_W<'a> { + w: &'a mut W, +} +impl<'a> START_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - ADC Flush"] + #[inline(always)] + pub fn flush(&self) -> FLUSH_R { + FLUSH_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Start ADC Conversion"] + #[inline(always)] + pub fn start(&self) -> START_R { + START_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - ADC Flush"] + #[inline(always)] + pub fn flush(&mut self) -> FLUSH_W { + FLUSH_W { w: self } + } + #[doc = "Bit 1 - Start ADC Conversion"] + #[inline(always)] + pub fn start(&mut self) -> START_W { + START_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Software Trigger\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [swtrig](index.html) module"] +pub struct SWTRIG_SPEC; +impl crate::RegisterSpec for SWTRIG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [swtrig::R](R) reader structure"] +impl crate::Readable for SWTRIG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [swtrig::W](W) writer structure"] +impl crate::Writable for SWTRIG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SWTRIG to value 0"] +impl crate::Resettable for SWTRIG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/adc0/syncbusy.rs b/pac/atsamc21e/src/adc0/syncbusy.rs new file mode 100644 index 000000000000..9c92da8a7c74 --- /dev/null +++ b/pac/atsamc21e/src/adc0/syncbusy.rs @@ -0,0 +1,253 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - SWRST Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - ENABLE Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INPUTCTRL` reader - INPUTCTRL Synchronization Busy"] +pub struct INPUTCTRL_R(crate::FieldReader); +impl INPUTCTRL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INPUTCTRL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INPUTCTRL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLC` reader - CTRLC Synchronization Busy"] +pub struct CTRLC_R(crate::FieldReader); +impl CTRLC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AVGCTRL` reader - AVGCTRL Synchronization Busy"] +pub struct AVGCTRL_R(crate::FieldReader); +impl AVGCTRL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AVGCTRL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AVGCTRL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SAMPCTRL` reader - SAMPCTRL Synchronization Busy"] +pub struct SAMPCTRL_R(crate::FieldReader); +impl SAMPCTRL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SAMPCTRL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SAMPCTRL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINLT` reader - WINLT Synchronization Busy"] +pub struct WINLT_R(crate::FieldReader); +impl WINLT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINLT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINLT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINUT` reader - WINUT Synchronization Busy"] +pub struct WINUT_R(crate::FieldReader); +impl WINUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GAINCORR` reader - GAINCORR Synchronization Busy"] +pub struct GAINCORR_R(crate::FieldReader); +impl GAINCORR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GAINCORR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GAINCORR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OFFSETCORR` reader - OFFSETCTRL Synchronization Busy"] +pub struct OFFSETCORR_R(crate::FieldReader); +impl OFFSETCORR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OFFSETCORR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OFFSETCORR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG` reader - SWTRG Synchronization Busy"] +pub struct SWTRIG_R(crate::FieldReader); +impl SWTRIG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - SWRST Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ENABLE Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - INPUTCTRL Synchronization Busy"] + #[inline(always)] + pub fn inputctrl(&self) -> INPUTCTRL_R { + INPUTCTRL_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - CTRLC Synchronization Busy"] + #[inline(always)] + pub fn ctrlc(&self) -> CTRLC_R { + CTRLC_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - AVGCTRL Synchronization Busy"] + #[inline(always)] + pub fn avgctrl(&self) -> AVGCTRL_R { + AVGCTRL_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - SAMPCTRL Synchronization Busy"] + #[inline(always)] + pub fn sampctrl(&self) -> SAMPCTRL_R { + SAMPCTRL_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - WINLT Synchronization Busy"] + #[inline(always)] + pub fn winlt(&self) -> WINLT_R { + WINLT_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - WINUT Synchronization Busy"] + #[inline(always)] + pub fn winut(&self) -> WINUT_R { + WINUT_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - GAINCORR Synchronization Busy"] + #[inline(always)] + pub fn gaincorr(&self) -> GAINCORR_R { + GAINCORR_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - OFFSETCTRL Synchronization Busy"] + #[inline(always)] + pub fn offsetcorr(&self) -> OFFSETCORR_R { + OFFSETCORR_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - SWTRG Synchronization Busy"] + #[inline(always)] + pub fn swtrig(&self) -> SWTRIG_R { + SWTRIG_R::new(((self.bits >> 10) & 0x01) != 0) + } +} +#[doc = "Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/adc0/winlt.rs b/pac/atsamc21e/src/adc0/winlt.rs new file mode 100644 index 000000000000..2a3397684767 --- /dev/null +++ b/pac/atsamc21e/src/adc0/winlt.rs @@ -0,0 +1,103 @@ +#[doc = "Register `WINLT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WINLT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WINLT` reader - Window Lower Threshold"] +pub struct WINLT_R(crate::FieldReader); +impl WINLT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + WINLT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINLT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINLT` writer - Window Lower Threshold"] +pub struct WINLT_W<'a> { + w: &'a mut W, +} +impl<'a> WINLT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Window Lower Threshold"] + #[inline(always)] + pub fn winlt(&self) -> WINLT_R { + WINLT_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Window Lower Threshold"] + #[inline(always)] + pub fn winlt(&mut self) -> WINLT_W { + WINLT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Window Monitor Lower Threshold\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [winlt](index.html) module"] +pub struct WINLT_SPEC; +impl crate::RegisterSpec for WINLT_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [winlt::R](R) reader structure"] +impl crate::Readable for WINLT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [winlt::W](W) writer structure"] +impl crate::Writable for WINLT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WINLT to value 0"] +impl crate::Resettable for WINLT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/adc0/winut.rs b/pac/atsamc21e/src/adc0/winut.rs new file mode 100644 index 000000000000..0ea123174937 --- /dev/null +++ b/pac/atsamc21e/src/adc0/winut.rs @@ -0,0 +1,103 @@ +#[doc = "Register `WINUT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WINUT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WINUT` reader - Window Upper Threshold"] +pub struct WINUT_R(crate::FieldReader); +impl WINUT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + WINUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINUT` writer - Window Upper Threshold"] +pub struct WINUT_W<'a> { + w: &'a mut W, +} +impl<'a> WINUT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Window Upper Threshold"] + #[inline(always)] + pub fn winut(&self) -> WINUT_R { + WINUT_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Window Upper Threshold"] + #[inline(always)] + pub fn winut(&mut self) -> WINUT_W { + WINUT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Window Monitor Upper Threshold\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [winut](index.html) module"] +pub struct WINUT_SPEC; +impl crate::RegisterSpec for WINUT_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [winut::R](R) reader structure"] +impl crate::Readable for WINUT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [winut::W](W) writer structure"] +impl crate::Writable for WINUT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WINUT to value 0"] +impl crate::Resettable for WINUT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/can0.rs b/pac/atsamc21e/src/can0.rs new file mode 100644 index 000000000000..96ccd4c5970c --- /dev/null +++ b/pac/atsamc21e/src/can0.rs @@ -0,0 +1,291 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Core Release"] + pub crel: crate::Reg, + #[doc = "0x04 - Endian"] + pub endn: crate::Reg, + #[doc = "0x08 - Message RAM Configuration"] + pub mrcfg: crate::Reg, + #[doc = "0x0c - Fast Bit Timing and Prescaler"] + pub dbtp: crate::Reg, + #[doc = "0x10 - Test"] + pub test: crate::Reg, + #[doc = "0x14 - RAM Watchdog"] + pub rwd: crate::Reg, + #[doc = "0x18 - CC Control"] + pub cccr: crate::Reg, + #[doc = "0x1c - Nominal Bit Timing and Prescaler"] + pub nbtp: crate::Reg, + #[doc = "0x20 - Timestamp Counter Configuration"] + pub tscc: crate::Reg, + #[doc = "0x24 - Timestamp Counter Value"] + pub tscv: crate::Reg, + #[doc = "0x28 - Timeout Counter Configuration"] + pub tocc: crate::Reg, + #[doc = "0x2c - Timeout Counter Value"] + pub tocv: crate::Reg, + _reserved12: [u8; 0x10], + #[doc = "0x40 - Error Counter"] + pub ecr: crate::Reg, + #[doc = "0x44 - Protocol Status"] + pub psr: crate::Reg, + #[doc = "0x48 - Extended ID Filter Configuration"] + pub tdcr: crate::Reg, + _reserved15: [u8; 0x04], + #[doc = "0x50 - Interrupt"] + pub ir: crate::Reg, + #[doc = "0x54 - Interrupt Enable"] + pub ie: crate::Reg, + #[doc = "0x58 - Interrupt Line Select"] + pub ils: crate::Reg, + #[doc = "0x5c - Interrupt Line Enable"] + pub ile: crate::Reg, + _reserved19: [u8; 0x20], + #[doc = "0x80 - Global Filter Configuration"] + pub gfc: crate::Reg, + #[doc = "0x84 - Standard ID Filter Configuration"] + pub sidfc: crate::Reg, + #[doc = "0x88 - Extended ID Filter Configuration"] + pub xidfc: crate::Reg, + _reserved22: [u8; 0x04], + #[doc = "0x90 - Extended ID AND Mask"] + pub xidam: crate::Reg, + #[doc = "0x94 - High Priority Message Status"] + pub hpms: crate::Reg, + #[doc = "0x98 - New Data 1"] + pub ndat1: crate::Reg, + #[doc = "0x9c - New Data 2"] + pub ndat2: crate::Reg, + #[doc = "0xa0 - Rx FIFO 0 Configuration"] + pub rxf0c: crate::Reg, + #[doc = "0xa4 - Rx FIFO 0 Status"] + pub rxf0s: crate::Reg, + #[doc = "0xa8 - Rx FIFO 0 Acknowledge"] + pub rxf0a: crate::Reg, + #[doc = "0xac - Rx Buffer Configuration"] + pub rxbc: crate::Reg, + #[doc = "0xb0 - Rx FIFO 1 Configuration"] + pub rxf1c: crate::Reg, + #[doc = "0xb4 - Rx FIFO 1 Status"] + pub rxf1s: crate::Reg, + #[doc = "0xb8 - Rx FIFO 1 Acknowledge"] + pub rxf1a: crate::Reg, + #[doc = "0xbc - Rx Buffer / FIFO Element Size Configuration"] + pub rxesc: crate::Reg, + #[doc = "0xc0 - Tx Buffer Configuration"] + pub txbc: crate::Reg, + #[doc = "0xc4 - Tx FIFO / Queue Status"] + pub txfqs: crate::Reg, + #[doc = "0xc8 - Tx Buffer Element Size Configuration"] + pub txesc: crate::Reg, + #[doc = "0xcc - Tx Buffer Request Pending"] + pub txbrp: crate::Reg, + #[doc = "0xd0 - Tx Buffer Add Request"] + pub txbar: crate::Reg, + #[doc = "0xd4 - Tx Buffer Cancellation Request"] + pub txbcr: crate::Reg, + #[doc = "0xd8 - Tx Buffer Transmission Occurred"] + pub txbto: crate::Reg, + #[doc = "0xdc - Tx Buffer Cancellation Finished"] + pub txbcf: crate::Reg, + #[doc = "0xe0 - Tx Buffer Transmission Interrupt Enable"] + pub txbtie: crate::Reg, + #[doc = "0xe4 - Tx Buffer Cancellation Finished Interrupt Enable"] + pub txbcie: crate::Reg, + _reserved44: [u8; 0x08], + #[doc = "0xf0 - Tx Event FIFO Configuration"] + pub txefc: crate::Reg, + #[doc = "0xf4 - Tx Event FIFO Status"] + pub txefs: crate::Reg, + #[doc = "0xf8 - Tx Event FIFO Acknowledge"] + pub txefa: crate::Reg, +} +#[doc = "CREL register accessor: an alias for `Reg`"] +pub type CREL = crate::Reg; +#[doc = "Core Release"] +pub mod crel; +#[doc = "ENDN register accessor: an alias for `Reg`"] +pub type ENDN = crate::Reg; +#[doc = "Endian"] +pub mod endn; +#[doc = "MRCFG register accessor: an alias for `Reg`"] +pub type MRCFG = crate::Reg; +#[doc = "Message RAM Configuration"] +pub mod mrcfg; +#[doc = "DBTP register accessor: an alias for `Reg`"] +pub type DBTP = crate::Reg; +#[doc = "Fast Bit Timing and Prescaler"] +pub mod dbtp; +#[doc = "TEST register accessor: an alias for `Reg`"] +pub type TEST = crate::Reg; +#[doc = "Test"] +pub mod test; +#[doc = "RWD register accessor: an alias for `Reg`"] +pub type RWD = crate::Reg; +#[doc = "RAM Watchdog"] +pub mod rwd; +#[doc = "CCCR register accessor: an alias for `Reg`"] +pub type CCCR = crate::Reg; +#[doc = "CC Control"] +pub mod cccr; +#[doc = "NBTP register accessor: an alias for `Reg`"] +pub type NBTP = crate::Reg; +#[doc = "Nominal Bit Timing and Prescaler"] +pub mod nbtp; +#[doc = "TSCC register accessor: an alias for `Reg`"] +pub type TSCC = crate::Reg; +#[doc = "Timestamp Counter Configuration"] +pub mod tscc; +#[doc = "TSCV register accessor: an alias for `Reg`"] +pub type TSCV = crate::Reg; +#[doc = "Timestamp Counter Value"] +pub mod tscv; +#[doc = "TOCC register accessor: an alias for `Reg`"] +pub type TOCC = crate::Reg; +#[doc = "Timeout Counter Configuration"] +pub mod tocc; +#[doc = "TOCV register accessor: an alias for `Reg`"] +pub type TOCV = crate::Reg; +#[doc = "Timeout Counter Value"] +pub mod tocv; +#[doc = "ECR register accessor: an alias for `Reg`"] +pub type ECR = crate::Reg; +#[doc = "Error Counter"] +pub mod ecr; +#[doc = "PSR register accessor: an alias for `Reg`"] +pub type PSR = crate::Reg; +#[doc = "Protocol Status"] +pub mod psr; +#[doc = "TDCR register accessor: an alias for `Reg`"] +pub type TDCR = crate::Reg; +#[doc = "Extended ID Filter Configuration"] +pub mod tdcr; +#[doc = "IR register accessor: an alias for `Reg`"] +pub type IR = crate::Reg; +#[doc = "Interrupt"] +pub mod ir; +#[doc = "IE register accessor: an alias for `Reg`"] +pub type IE = crate::Reg; +#[doc = "Interrupt Enable"] +pub mod ie; +#[doc = "ILS register accessor: an alias for `Reg`"] +pub type ILS = crate::Reg; +#[doc = "Interrupt Line Select"] +pub mod ils; +#[doc = "ILE register accessor: an alias for `Reg`"] +pub type ILE = crate::Reg; +#[doc = "Interrupt Line Enable"] +pub mod ile; +#[doc = "GFC register accessor: an alias for `Reg`"] +pub type GFC = crate::Reg; +#[doc = "Global Filter Configuration"] +pub mod gfc; +#[doc = "SIDFC register accessor: an alias for `Reg`"] +pub type SIDFC = crate::Reg; +#[doc = "Standard ID Filter Configuration"] +pub mod sidfc; +#[doc = "XIDFC register accessor: an alias for `Reg`"] +pub type XIDFC = crate::Reg; +#[doc = "Extended ID Filter Configuration"] +pub mod xidfc; +#[doc = "XIDAM register accessor: an alias for `Reg`"] +pub type XIDAM = crate::Reg; +#[doc = "Extended ID AND Mask"] +pub mod xidam; +#[doc = "HPMS register accessor: an alias for `Reg`"] +pub type HPMS = crate::Reg; +#[doc = "High Priority Message Status"] +pub mod hpms; +#[doc = "NDAT1 register accessor: an alias for `Reg`"] +pub type NDAT1 = crate::Reg; +#[doc = "New Data 1"] +pub mod ndat1; +#[doc = "NDAT2 register accessor: an alias for `Reg`"] +pub type NDAT2 = crate::Reg; +#[doc = "New Data 2"] +pub mod ndat2; +#[doc = "RXF0C register accessor: an alias for `Reg`"] +pub type RXF0C = crate::Reg; +#[doc = "Rx FIFO 0 Configuration"] +pub mod rxf0c; +#[doc = "RXF0S register accessor: an alias for `Reg`"] +pub type RXF0S = crate::Reg; +#[doc = "Rx FIFO 0 Status"] +pub mod rxf0s; +#[doc = "RXF0A register accessor: an alias for `Reg`"] +pub type RXF0A = crate::Reg; +#[doc = "Rx FIFO 0 Acknowledge"] +pub mod rxf0a; +#[doc = "RXBC register accessor: an alias for `Reg`"] +pub type RXBC = crate::Reg; +#[doc = "Rx Buffer Configuration"] +pub mod rxbc; +#[doc = "RXF1C register accessor: an alias for `Reg`"] +pub type RXF1C = crate::Reg; +#[doc = "Rx FIFO 1 Configuration"] +pub mod rxf1c; +#[doc = "RXF1S register accessor: an alias for `Reg`"] +pub type RXF1S = crate::Reg; +#[doc = "Rx FIFO 1 Status"] +pub mod rxf1s; +#[doc = "RXF1A register accessor: an alias for `Reg`"] +pub type RXF1A = crate::Reg; +#[doc = "Rx FIFO 1 Acknowledge"] +pub mod rxf1a; +#[doc = "RXESC register accessor: an alias for `Reg`"] +pub type RXESC = crate::Reg; +#[doc = "Rx Buffer / FIFO Element Size Configuration"] +pub mod rxesc; +#[doc = "TXBC register accessor: an alias for `Reg`"] +pub type TXBC = crate::Reg; +#[doc = "Tx Buffer Configuration"] +pub mod txbc; +#[doc = "TXFQS register accessor: an alias for `Reg`"] +pub type TXFQS = crate::Reg; +#[doc = "Tx FIFO / Queue Status"] +pub mod txfqs; +#[doc = "TXESC register accessor: an alias for `Reg`"] +pub type TXESC = crate::Reg; +#[doc = "Tx Buffer Element Size Configuration"] +pub mod txesc; +#[doc = "TXBRP register accessor: an alias for `Reg`"] +pub type TXBRP = crate::Reg; +#[doc = "Tx Buffer Request Pending"] +pub mod txbrp; +#[doc = "TXBAR register accessor: an alias for `Reg`"] +pub type TXBAR = crate::Reg; +#[doc = "Tx Buffer Add Request"] +pub mod txbar; +#[doc = "TXBCR register accessor: an alias for `Reg`"] +pub type TXBCR = crate::Reg; +#[doc = "Tx Buffer Cancellation Request"] +pub mod txbcr; +#[doc = "TXBTO register accessor: an alias for `Reg`"] +pub type TXBTO = crate::Reg; +#[doc = "Tx Buffer Transmission Occurred"] +pub mod txbto; +#[doc = "TXBCF register accessor: an alias for `Reg`"] +pub type TXBCF = crate::Reg; +#[doc = "Tx Buffer Cancellation Finished"] +pub mod txbcf; +#[doc = "TXBTIE register accessor: an alias for `Reg`"] +pub type TXBTIE = crate::Reg; +#[doc = "Tx Buffer Transmission Interrupt Enable"] +pub mod txbtie; +#[doc = "TXBCIE register accessor: an alias for `Reg`"] +pub type TXBCIE = crate::Reg; +#[doc = "Tx Buffer Cancellation Finished Interrupt Enable"] +pub mod txbcie; +#[doc = "TXEFC register accessor: an alias for `Reg`"] +pub type TXEFC = crate::Reg; +#[doc = "Tx Event FIFO Configuration"] +pub mod txefc; +#[doc = "TXEFS register accessor: an alias for `Reg`"] +pub type TXEFS = crate::Reg; +#[doc = "Tx Event FIFO Status"] +pub mod txefs; +#[doc = "TXEFA register accessor: an alias for `Reg`"] +pub type TXEFA = crate::Reg; +#[doc = "Tx Event FIFO Acknowledge"] +pub mod txefa; diff --git a/pac/atsamc21e/src/can0/cccr.rs b/pac/atsamc21e/src/can0/cccr.rs new file mode 100644 index 000000000000..c2ff17d123cf --- /dev/null +++ b/pac/atsamc21e/src/can0/cccr.rs @@ -0,0 +1,724 @@ +#[doc = "Register `CCCR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CCCR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INIT` reader - Initialization"] +pub struct INIT_R(crate::FieldReader); +impl INIT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INIT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INIT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INIT` writer - Initialization"] +pub struct INIT_W<'a> { + w: &'a mut W, +} +impl<'a> INIT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `CCE` reader - Configuration Change Enable"] +pub struct CCE_R(crate::FieldReader); +impl CCE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCE` writer - Configuration Change Enable"] +pub struct CCE_W<'a> { + w: &'a mut W, +} +impl<'a> CCE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ASM` reader - ASM Restricted Operation Mode"] +pub struct ASM_R(crate::FieldReader); +impl ASM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ASM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ASM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ASM` writer - ASM Restricted Operation Mode"] +pub struct ASM_W<'a> { + w: &'a mut W, +} +impl<'a> ASM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CSA` reader - Clock Stop Acknowledge"] +pub struct CSA_R(crate::FieldReader); +impl CSA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CSA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CSA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CSA` writer - Clock Stop Acknowledge"] +pub struct CSA_W<'a> { + w: &'a mut W, +} +impl<'a> CSA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CSR` reader - Clock Stop Request"] +pub struct CSR_R(crate::FieldReader); +impl CSR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CSR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CSR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CSR` writer - Clock Stop Request"] +pub struct CSR_W<'a> { + w: &'a mut W, +} +impl<'a> CSR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MON` reader - Bus Monitoring Mode"] +pub struct MON_R(crate::FieldReader); +impl MON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MON` writer - Bus Monitoring Mode"] +pub struct MON_W<'a> { + w: &'a mut W, +} +impl<'a> MON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `DAR` reader - Disable Automatic Retransmission"] +pub struct DAR_R(crate::FieldReader); +impl DAR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DAR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DAR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DAR` writer - Disable Automatic Retransmission"] +pub struct DAR_W<'a> { + w: &'a mut W, +} +impl<'a> DAR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `TEST` reader - Test Mode Enable"] +pub struct TEST_R(crate::FieldReader); +impl TEST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TEST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TEST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TEST` writer - Test Mode Enable"] +pub struct TEST_W<'a> { + w: &'a mut W, +} +impl<'a> TEST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `FDOE` reader - FD Operation Enable"] +pub struct FDOE_R(crate::FieldReader); +impl FDOE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FDOE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FDOE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FDOE` writer - FD Operation Enable"] +pub struct FDOE_W<'a> { + w: &'a mut W, +} +impl<'a> FDOE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `BRSE` reader - Bit Rate Switch Enable"] +pub struct BRSE_R(crate::FieldReader); +impl BRSE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BRSE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BRSE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BRSE` writer - Bit Rate Switch Enable"] +pub struct BRSE_W<'a> { + w: &'a mut W, +} +impl<'a> BRSE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `PXHD` reader - Protocol Exception Handling Disable"] +pub struct PXHD_R(crate::FieldReader); +impl PXHD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PXHD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PXHD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PXHD` writer - Protocol Exception Handling Disable"] +pub struct PXHD_W<'a> { + w: &'a mut W, +} +impl<'a> PXHD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `EFBI` reader - Edge Filtering during Bus Integration"] +pub struct EFBI_R(crate::FieldReader); +impl EFBI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EFBI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EFBI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EFBI` writer - Edge Filtering during Bus Integration"] +pub struct EFBI_W<'a> { + w: &'a mut W, +} +impl<'a> EFBI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `TXP` reader - Transmit Pause"] +pub struct TXP_R(crate::FieldReader); +impl TXP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXP` writer - Transmit Pause"] +pub struct TXP_W<'a> { + w: &'a mut W, +} +impl<'a> TXP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `NISO` reader - Non ISO Operation"] +pub struct NISO_R(crate::FieldReader); +impl NISO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NISO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NISO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NISO` writer - Non ISO Operation"] +pub struct NISO_W<'a> { + w: &'a mut W, +} +impl<'a> NISO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Initialization"] + #[inline(always)] + pub fn init(&self) -> INIT_R { + INIT_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Configuration Change Enable"] + #[inline(always)] + pub fn cce(&self) -> CCE_R { + CCE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - ASM Restricted Operation Mode"] + #[inline(always)] + pub fn asm(&self) -> ASM_R { + ASM_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Clock Stop Acknowledge"] + #[inline(always)] + pub fn csa(&self) -> CSA_R { + CSA_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Clock Stop Request"] + #[inline(always)] + pub fn csr(&self) -> CSR_R { + CSR_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Bus Monitoring Mode"] + #[inline(always)] + pub fn mon(&self) -> MON_R { + MON_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Disable Automatic Retransmission"] + #[inline(always)] + pub fn dar(&self) -> DAR_R { + DAR_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Test Mode Enable"] + #[inline(always)] + pub fn test(&self) -> TEST_R { + TEST_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - FD Operation Enable"] + #[inline(always)] + pub fn fdoe(&self) -> FDOE_R { + FDOE_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Bit Rate Switch Enable"] + #[inline(always)] + pub fn brse(&self) -> BRSE_R { + BRSE_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 12 - Protocol Exception Handling Disable"] + #[inline(always)] + pub fn pxhd(&self) -> PXHD_R { + PXHD_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Edge Filtering during Bus Integration"] + #[inline(always)] + pub fn efbi(&self) -> EFBI_R { + EFBI_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Transmit Pause"] + #[inline(always)] + pub fn txp(&self) -> TXP_R { + TXP_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Non ISO Operation"] + #[inline(always)] + pub fn niso(&self) -> NISO_R { + NISO_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Initialization"] + #[inline(always)] + pub fn init(&mut self) -> INIT_W { + INIT_W { w: self } + } + #[doc = "Bit 1 - Configuration Change Enable"] + #[inline(always)] + pub fn cce(&mut self) -> CCE_W { + CCE_W { w: self } + } + #[doc = "Bit 2 - ASM Restricted Operation Mode"] + #[inline(always)] + pub fn asm(&mut self) -> ASM_W { + ASM_W { w: self } + } + #[doc = "Bit 3 - Clock Stop Acknowledge"] + #[inline(always)] + pub fn csa(&mut self) -> CSA_W { + CSA_W { w: self } + } + #[doc = "Bit 4 - Clock Stop Request"] + #[inline(always)] + pub fn csr(&mut self) -> CSR_W { + CSR_W { w: self } + } + #[doc = "Bit 5 - Bus Monitoring Mode"] + #[inline(always)] + pub fn mon(&mut self) -> MON_W { + MON_W { w: self } + } + #[doc = "Bit 6 - Disable Automatic Retransmission"] + #[inline(always)] + pub fn dar(&mut self) -> DAR_W { + DAR_W { w: self } + } + #[doc = "Bit 7 - Test Mode Enable"] + #[inline(always)] + pub fn test(&mut self) -> TEST_W { + TEST_W { w: self } + } + #[doc = "Bit 8 - FD Operation Enable"] + #[inline(always)] + pub fn fdoe(&mut self) -> FDOE_W { + FDOE_W { w: self } + } + #[doc = "Bit 9 - Bit Rate Switch Enable"] + #[inline(always)] + pub fn brse(&mut self) -> BRSE_W { + BRSE_W { w: self } + } + #[doc = "Bit 12 - Protocol Exception Handling Disable"] + #[inline(always)] + pub fn pxhd(&mut self) -> PXHD_W { + PXHD_W { w: self } + } + #[doc = "Bit 13 - Edge Filtering during Bus Integration"] + #[inline(always)] + pub fn efbi(&mut self) -> EFBI_W { + EFBI_W { w: self } + } + #[doc = "Bit 14 - Transmit Pause"] + #[inline(always)] + pub fn txp(&mut self) -> TXP_W { + TXP_W { w: self } + } + #[doc = "Bit 15 - Non ISO Operation"] + #[inline(always)] + pub fn niso(&mut self) -> NISO_W { + NISO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CC Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cccr](index.html) module"] +pub struct CCCR_SPEC; +impl crate::RegisterSpec for CCCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cccr::R](R) reader structure"] +impl crate::Readable for CCCR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cccr::W](W) writer structure"] +impl crate::Writable for CCCR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CCCR to value 0x01"] +impl crate::Resettable for CCCR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pac/atsamc21e/src/can0/crel.rs b/pac/atsamc21e/src/can0/crel.rs new file mode 100644 index 000000000000..4e9dcdbf5f03 --- /dev/null +++ b/pac/atsamc21e/src/can0/crel.rs @@ -0,0 +1,93 @@ +#[doc = "Register `CREL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SUBSTEP` reader - Sub-step of Core Release"] +pub struct SUBSTEP_R(crate::FieldReader); +impl SUBSTEP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SUBSTEP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SUBSTEP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STEP` reader - Step of Core Release"] +pub struct STEP_R(crate::FieldReader); +impl STEP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + STEP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STEP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REL` reader - Core Release"] +pub struct REL_R(crate::FieldReader); +impl REL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 20:23 - Sub-step of Core Release"] + #[inline(always)] + pub fn substep(&self) -> SUBSTEP_R { + SUBSTEP_R::new(((self.bits >> 20) & 0x0f) as u8) + } + #[doc = "Bits 24:27 - Step of Core Release"] + #[inline(always)] + pub fn step(&self) -> STEP_R { + STEP_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bits 28:31 - Core Release"] + #[inline(always)] + pub fn rel(&self) -> REL_R { + REL_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +#[doc = "Core Release\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [crel](index.html) module"] +pub struct CREL_SPEC; +impl crate::RegisterSpec for CREL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [crel::R](R) reader structure"] +impl crate::Readable for CREL_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CREL to value 0x3210_0000"] +impl crate::Resettable for CREL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x3210_0000 + } +} diff --git a/pac/atsamc21e/src/can0/dbtp.rs b/pac/atsamc21e/src/can0/dbtp.rs new file mode 100644 index 000000000000..5c1d2bc7ccdd --- /dev/null +++ b/pac/atsamc21e/src/can0/dbtp.rs @@ -0,0 +1,261 @@ +#[doc = "Register `DBTP` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBTP` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DSJW` reader - Data (Re)Synchronization Jump Width"] +pub struct DSJW_R(crate::FieldReader); +impl DSJW_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DSJW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DSJW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DSJW` writer - Data (Re)Synchronization Jump Width"] +pub struct DSJW_W<'a> { + w: &'a mut W, +} +impl<'a> DSJW_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Field `DTSEG2` reader - Data time segment after sample point"] +pub struct DTSEG2_R(crate::FieldReader); +impl DTSEG2_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DTSEG2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DTSEG2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DTSEG2` writer - Data time segment after sample point"] +pub struct DTSEG2_W<'a> { + w: &'a mut W, +} +impl<'a> DTSEG2_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 4)) | ((value as u32 & 0x0f) << 4); + self.w + } +} +#[doc = "Field `DTSEG1` reader - Data time segment before sample point"] +pub struct DTSEG1_R(crate::FieldReader); +impl DTSEG1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DTSEG1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DTSEG1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DTSEG1` writer - Data time segment before sample point"] +pub struct DTSEG1_W<'a> { + w: &'a mut W, +} +impl<'a> DTSEG1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 8)) | ((value as u32 & 0x1f) << 8); + self.w + } +} +#[doc = "Field `DBRP` reader - Data Baud Rate Prescaler"] +pub struct DBRP_R(crate::FieldReader); +impl DBRP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DBRP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBRP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBRP` writer - Data Baud Rate Prescaler"] +pub struct DBRP_W<'a> { + w: &'a mut W, +} +impl<'a> DBRP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 16)) | ((value as u32 & 0x1f) << 16); + self.w + } +} +#[doc = "Field `TDC` reader - Tranceiver Delay Compensation"] +pub struct TDC_R(crate::FieldReader); +impl TDC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TDC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TDC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TDC` writer - Tranceiver Delay Compensation"] +pub struct TDC_W<'a> { + w: &'a mut W, +} +impl<'a> TDC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Data (Re)Synchronization Jump Width"] + #[inline(always)] + pub fn dsjw(&self) -> DSJW_R { + DSJW_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Data time segment after sample point"] + #[inline(always)] + pub fn dtseg2(&self) -> DTSEG2_R { + DTSEG2_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 8:12 - Data time segment before sample point"] + #[inline(always)] + pub fn dtseg1(&self) -> DTSEG1_R { + DTSEG1_R::new(((self.bits >> 8) & 0x1f) as u8) + } + #[doc = "Bits 16:20 - Data Baud Rate Prescaler"] + #[inline(always)] + pub fn dbrp(&self) -> DBRP_R { + DBRP_R::new(((self.bits >> 16) & 0x1f) as u8) + } + #[doc = "Bit 23 - Tranceiver Delay Compensation"] + #[inline(always)] + pub fn tdc(&self) -> TDC_R { + TDC_R::new(((self.bits >> 23) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Data (Re)Synchronization Jump Width"] + #[inline(always)] + pub fn dsjw(&mut self) -> DSJW_W { + DSJW_W { w: self } + } + #[doc = "Bits 4:7 - Data time segment after sample point"] + #[inline(always)] + pub fn dtseg2(&mut self) -> DTSEG2_W { + DTSEG2_W { w: self } + } + #[doc = "Bits 8:12 - Data time segment before sample point"] + #[inline(always)] + pub fn dtseg1(&mut self) -> DTSEG1_W { + DTSEG1_W { w: self } + } + #[doc = "Bits 16:20 - Data Baud Rate Prescaler"] + #[inline(always)] + pub fn dbrp(&mut self) -> DBRP_W { + DBRP_W { w: self } + } + #[doc = "Bit 23 - Tranceiver Delay Compensation"] + #[inline(always)] + pub fn tdc(&mut self) -> TDC_W { + TDC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Fast Bit Timing and Prescaler\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbtp](index.html) module"] +pub struct DBTP_SPEC; +impl crate::RegisterSpec for DBTP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dbtp::R](R) reader structure"] +impl crate::Readable for DBTP_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbtp::W](W) writer structure"] +impl crate::Writable for DBTP_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBTP to value 0x0a33"] +impl crate::Resettable for DBTP_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0a33 + } +} diff --git a/pac/atsamc21e/src/can0/ecr.rs b/pac/atsamc21e/src/can0/ecr.rs new file mode 100644 index 000000000000..044085d7706d --- /dev/null +++ b/pac/atsamc21e/src/can0/ecr.rs @@ -0,0 +1,113 @@ +#[doc = "Register `ECR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `TEC` reader - Transmit Error Counter"] +pub struct TEC_R(crate::FieldReader); +impl TEC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TEC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TEC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REC` reader - Receive Error Counter"] +pub struct REC_R(crate::FieldReader); +impl REC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RP` reader - Receive Error Passive"] +pub struct RP_R(crate::FieldReader); +impl RP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CEL` reader - CAN Error Logging"] +pub struct CEL_R(crate::FieldReader); +impl CEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:7 - Transmit Error Counter"] + #[inline(always)] + pub fn tec(&self) -> TEC_R { + TEC_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:14 - Receive Error Counter"] + #[inline(always)] + pub fn rec(&self) -> REC_R { + REC_R::new(((self.bits >> 8) & 0x7f) as u8) + } + #[doc = "Bit 15 - Receive Error Passive"] + #[inline(always)] + pub fn rp(&self) -> RP_R { + RP_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:23 - CAN Error Logging"] + #[inline(always)] + pub fn cel(&self) -> CEL_R { + CEL_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +#[doc = "Error Counter\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ecr](index.html) module"] +pub struct ECR_SPEC; +impl crate::RegisterSpec for ECR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ecr::R](R) reader structure"] +impl crate::Readable for ECR_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets ECR to value 0"] +impl crate::Resettable for ECR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/can0/endn.rs b/pac/atsamc21e/src/can0/endn.rs new file mode 100644 index 000000000000..9628fa2a3f48 --- /dev/null +++ b/pac/atsamc21e/src/can0/endn.rs @@ -0,0 +1,53 @@ +#[doc = "Register `ENDN` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `ETV` reader - Endianness Test Value"] +pub struct ETV_R(crate::FieldReader); +impl ETV_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + ETV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ETV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - Endianness Test Value"] + #[inline(always)] + pub fn etv(&self) -> ETV_R { + ETV_R::new(self.bits as u32) + } +} +#[doc = "Endian\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [endn](index.html) module"] +pub struct ENDN_SPEC; +impl crate::RegisterSpec for ENDN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [endn::R](R) reader structure"] +impl crate::Readable for ENDN_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets ENDN to value 0x8765_4321"] +impl crate::Resettable for ENDN_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x8765_4321 + } +} diff --git a/pac/atsamc21e/src/can0/gfc.rs b/pac/atsamc21e/src/can0/gfc.rs new file mode 100644 index 000000000000..a9e7a8cc9f62 --- /dev/null +++ b/pac/atsamc21e/src/can0/gfc.rs @@ -0,0 +1,358 @@ +#[doc = "Register `GFC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GFC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RRFE` reader - Reject Remote Frames Extended"] +pub struct RRFE_R(crate::FieldReader); +impl RRFE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RRFE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RRFE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RRFE` writer - Reject Remote Frames Extended"] +pub struct RRFE_W<'a> { + w: &'a mut W, +} +impl<'a> RRFE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `RRFS` reader - Reject Remote Frames Standard"] +pub struct RRFS_R(crate::FieldReader); +impl RRFS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RRFS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RRFS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RRFS` writer - Reject Remote Frames Standard"] +pub struct RRFS_W<'a> { + w: &'a mut W, +} +impl<'a> RRFS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Accept Non-matching Frames Extended\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum ANFE_A { + #[doc = "0: Accept in Rx FIFO 0"] + RXF0 = 0, + #[doc = "1: Accept in Rx FIFO 1"] + RXF1 = 1, + #[doc = "2: Reject"] + REJECT = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: ANFE_A) -> Self { + variant as _ + } +} +#[doc = "Field `ANFE` reader - Accept Non-matching Frames Extended"] +pub struct ANFE_R(crate::FieldReader); +impl ANFE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ANFE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(ANFE_A::RXF0), + 1 => Some(ANFE_A::RXF1), + 2 => Some(ANFE_A::REJECT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `RXF0`"] + #[inline(always)] + pub fn is_rxf0(&self) -> bool { + **self == ANFE_A::RXF0 + } + #[doc = "Checks if the value of the field is `RXF1`"] + #[inline(always)] + pub fn is_rxf1(&self) -> bool { + **self == ANFE_A::RXF1 + } + #[doc = "Checks if the value of the field is `REJECT`"] + #[inline(always)] + pub fn is_reject(&self) -> bool { + **self == ANFE_A::REJECT + } +} +impl core::ops::Deref for ANFE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ANFE` writer - Accept Non-matching Frames Extended"] +pub struct ANFE_W<'a> { + w: &'a mut W, +} +impl<'a> ANFE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: ANFE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Accept in Rx FIFO 0"] + #[inline(always)] + pub fn rxf0(self) -> &'a mut W { + self.variant(ANFE_A::RXF0) + } + #[doc = "Accept in Rx FIFO 1"] + #[inline(always)] + pub fn rxf1(self) -> &'a mut W { + self.variant(ANFE_A::RXF1) + } + #[doc = "Reject"] + #[inline(always)] + pub fn reject(self) -> &'a mut W { + self.variant(ANFE_A::REJECT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u32 & 0x03) << 2); + self.w + } +} +#[doc = "Accept Non-matching Frames Standard\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum ANFS_A { + #[doc = "0: Accept in Rx FIFO 0"] + RXF0 = 0, + #[doc = "1: Accept in Rx FIFO 1"] + RXF1 = 1, + #[doc = "2: Reject"] + REJECT = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: ANFS_A) -> Self { + variant as _ + } +} +#[doc = "Field `ANFS` reader - Accept Non-matching Frames Standard"] +pub struct ANFS_R(crate::FieldReader); +impl ANFS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ANFS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(ANFS_A::RXF0), + 1 => Some(ANFS_A::RXF1), + 2 => Some(ANFS_A::REJECT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `RXF0`"] + #[inline(always)] + pub fn is_rxf0(&self) -> bool { + **self == ANFS_A::RXF0 + } + #[doc = "Checks if the value of the field is `RXF1`"] + #[inline(always)] + pub fn is_rxf1(&self) -> bool { + **self == ANFS_A::RXF1 + } + #[doc = "Checks if the value of the field is `REJECT`"] + #[inline(always)] + pub fn is_reject(&self) -> bool { + **self == ANFS_A::REJECT + } +} +impl core::ops::Deref for ANFS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ANFS` writer - Accept Non-matching Frames Standard"] +pub struct ANFS_W<'a> { + w: &'a mut W, +} +impl<'a> ANFS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: ANFS_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Accept in Rx FIFO 0"] + #[inline(always)] + pub fn rxf0(self) -> &'a mut W { + self.variant(ANFS_A::RXF0) + } + #[doc = "Accept in Rx FIFO 1"] + #[inline(always)] + pub fn rxf1(self) -> &'a mut W { + self.variant(ANFS_A::RXF1) + } + #[doc = "Reject"] + #[inline(always)] + pub fn reject(self) -> &'a mut W { + self.variant(ANFS_A::REJECT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u32 & 0x03) << 4); + self.w + } +} +impl R { + #[doc = "Bit 0 - Reject Remote Frames Extended"] + #[inline(always)] + pub fn rrfe(&self) -> RRFE_R { + RRFE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Reject Remote Frames Standard"] + #[inline(always)] + pub fn rrfs(&self) -> RRFS_R { + RRFS_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:3 - Accept Non-matching Frames Extended"] + #[inline(always)] + pub fn anfe(&self) -> ANFE_R { + ANFE_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bits 4:5 - Accept Non-matching Frames Standard"] + #[inline(always)] + pub fn anfs(&self) -> ANFS_R { + ANFS_R::new(((self.bits >> 4) & 0x03) as u8) + } +} +impl W { + #[doc = "Bit 0 - Reject Remote Frames Extended"] + #[inline(always)] + pub fn rrfe(&mut self) -> RRFE_W { + RRFE_W { w: self } + } + #[doc = "Bit 1 - Reject Remote Frames Standard"] + #[inline(always)] + pub fn rrfs(&mut self) -> RRFS_W { + RRFS_W { w: self } + } + #[doc = "Bits 2:3 - Accept Non-matching Frames Extended"] + #[inline(always)] + pub fn anfe(&mut self) -> ANFE_W { + ANFE_W { w: self } + } + #[doc = "Bits 4:5 - Accept Non-matching Frames Standard"] + #[inline(always)] + pub fn anfs(&mut self) -> ANFS_W { + ANFS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Global Filter Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gfc](index.html) module"] +pub struct GFC_SPEC; +impl crate::RegisterSpec for GFC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gfc::R](R) reader structure"] +impl crate::Readable for GFC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gfc::W](W) writer structure"] +impl crate::Writable for GFC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets GFC to value 0"] +impl crate::Resettable for GFC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/can0/hpms.rs b/pac/atsamc21e/src/can0/hpms.rs new file mode 100644 index 000000000000..ff26a312fb47 --- /dev/null +++ b/pac/atsamc21e/src/can0/hpms.rs @@ -0,0 +1,163 @@ +#[doc = "Register `HPMS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `BIDX` reader - Buffer Index"] +pub struct BIDX_R(crate::FieldReader); +impl BIDX_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BIDX_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BIDX_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Message Storage Indicator\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MSI_A { + #[doc = "0: No FIFO selected"] + NONE = 0, + #[doc = "1: FIFO message lost"] + LOST = 1, + #[doc = "2: Message stored in FIFO 0"] + FIFO0 = 2, + #[doc = "3: Message stored in FIFO 1"] + FIFO1 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MSI_A) -> Self { + variant as _ + } +} +#[doc = "Field `MSI` reader - Message Storage Indicator"] +pub struct MSI_R(crate::FieldReader); +impl MSI_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MSI_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> MSI_A { + match self.bits { + 0 => MSI_A::NONE, + 1 => MSI_A::LOST, + 2 => MSI_A::FIFO0, + 3 => MSI_A::FIFO1, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == MSI_A::NONE + } + #[doc = "Checks if the value of the field is `LOST`"] + #[inline(always)] + pub fn is_lost(&self) -> bool { + **self == MSI_A::LOST + } + #[doc = "Checks if the value of the field is `FIFO0`"] + #[inline(always)] + pub fn is_fifo0(&self) -> bool { + **self == MSI_A::FIFO0 + } + #[doc = "Checks if the value of the field is `FIFO1`"] + #[inline(always)] + pub fn is_fifo1(&self) -> bool { + **self == MSI_A::FIFO1 + } +} +impl core::ops::Deref for MSI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FIDX` reader - Filter Index"] +pub struct FIDX_R(crate::FieldReader); +impl FIDX_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FIDX_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FIDX_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLST` reader - Filter List"] +pub struct FLST_R(crate::FieldReader); +impl FLST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FLST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FLST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:5 - Buffer Index"] + #[inline(always)] + pub fn bidx(&self) -> BIDX_R { + BIDX_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:7 - Message Storage Indicator"] + #[inline(always)] + pub fn msi(&self) -> MSI_R { + MSI_R::new(((self.bits >> 6) & 0x03) as u8) + } + #[doc = "Bits 8:14 - Filter Index"] + #[inline(always)] + pub fn fidx(&self) -> FIDX_R { + FIDX_R::new(((self.bits >> 8) & 0x7f) as u8) + } + #[doc = "Bit 15 - Filter List"] + #[inline(always)] + pub fn flst(&self) -> FLST_R { + FLST_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +#[doc = "High Priority Message Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hpms](index.html) module"] +pub struct HPMS_SPEC; +impl crate::RegisterSpec for HPMS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [hpms::R](R) reader structure"] +impl crate::Readable for HPMS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets HPMS to value 0"] +impl crate::Resettable for HPMS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/can0/ie.rs b/pac/atsamc21e/src/can0/ie.rs new file mode 100644 index 000000000000..c773ba115329 --- /dev/null +++ b/pac/atsamc21e/src/can0/ie.rs @@ -0,0 +1,1476 @@ +#[doc = "Register `IE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `IE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RF0NE` reader - Rx FIFO 0 New Message Interrupt Enable"] +pub struct RF0NE_R(crate::FieldReader); +impl RF0NE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF0NE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF0NE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF0NE` writer - Rx FIFO 0 New Message Interrupt Enable"] +pub struct RF0NE_W<'a> { + w: &'a mut W, +} +impl<'a> RF0NE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `RF0WE` reader - Rx FIFO 0 Watermark Reached Interrupt Enable"] +pub struct RF0WE_R(crate::FieldReader); +impl RF0WE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF0WE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF0WE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF0WE` writer - Rx FIFO 0 Watermark Reached Interrupt Enable"] +pub struct RF0WE_W<'a> { + w: &'a mut W, +} +impl<'a> RF0WE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RF0FE` reader - Rx FIFO 0 Full Interrupt Enable"] +pub struct RF0FE_R(crate::FieldReader); +impl RF0FE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF0FE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF0FE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF0FE` writer - Rx FIFO 0 Full Interrupt Enable"] +pub struct RF0FE_W<'a> { + w: &'a mut W, +} +impl<'a> RF0FE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RF0LE` reader - Rx FIFO 0 Message Lost Interrupt Enable"] +pub struct RF0LE_R(crate::FieldReader); +impl RF0LE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF0LE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF0LE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF0LE` writer - Rx FIFO 0 Message Lost Interrupt Enable"] +pub struct RF0LE_W<'a> { + w: &'a mut W, +} +impl<'a> RF0LE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `RF1NE` reader - Rx FIFO 1 New Message Interrupt Enable"] +pub struct RF1NE_R(crate::FieldReader); +impl RF1NE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF1NE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF1NE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF1NE` writer - Rx FIFO 1 New Message Interrupt Enable"] +pub struct RF1NE_W<'a> { + w: &'a mut W, +} +impl<'a> RF1NE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RF1WE` reader - Rx FIFO 1 Watermark Reached Interrupt Enable"] +pub struct RF1WE_R(crate::FieldReader); +impl RF1WE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF1WE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF1WE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF1WE` writer - Rx FIFO 1 Watermark Reached Interrupt Enable"] +pub struct RF1WE_W<'a> { + w: &'a mut W, +} +impl<'a> RF1WE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `RF1FE` reader - Rx FIFO 1 FIFO Full Interrupt Enable"] +pub struct RF1FE_R(crate::FieldReader); +impl RF1FE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF1FE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF1FE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF1FE` writer - Rx FIFO 1 FIFO Full Interrupt Enable"] +pub struct RF1FE_W<'a> { + w: &'a mut W, +} +impl<'a> RF1FE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `RF1LE` reader - Rx FIFO 1 Message Lost Interrupt Enable"] +pub struct RF1LE_R(crate::FieldReader); +impl RF1LE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF1LE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF1LE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF1LE` writer - Rx FIFO 1 Message Lost Interrupt Enable"] +pub struct RF1LE_W<'a> { + w: &'a mut W, +} +impl<'a> RF1LE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `HPME` reader - High Priority Message Interrupt Enable"] +pub struct HPME_R(crate::FieldReader); +impl HPME_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HPME_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HPME_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HPME` writer - High Priority Message Interrupt Enable"] +pub struct HPME_W<'a> { + w: &'a mut W, +} +impl<'a> HPME_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `TCE` reader - Timestamp Completed Interrupt Enable"] +pub struct TCE_R(crate::FieldReader); +impl TCE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCE` writer - Timestamp Completed Interrupt Enable"] +pub struct TCE_W<'a> { + w: &'a mut W, +} +impl<'a> TCE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `TCFE` reader - Transmission Cancellation Finished Interrupt Enable"] +pub struct TCFE_R(crate::FieldReader); +impl TCFE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCFE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCFE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCFE` writer - Transmission Cancellation Finished Interrupt Enable"] +pub struct TCFE_W<'a> { + w: &'a mut W, +} +impl<'a> TCFE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `TFEE` reader - Tx FIFO Empty Interrupt Enable"] +pub struct TFEE_R(crate::FieldReader); +impl TFEE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TFEE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TFEE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TFEE` writer - Tx FIFO Empty Interrupt Enable"] +pub struct TFEE_W<'a> { + w: &'a mut W, +} +impl<'a> TFEE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `TEFNE` reader - Tx Event FIFO New Entry Interrupt Enable"] +pub struct TEFNE_R(crate::FieldReader); +impl TEFNE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TEFNE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TEFNE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TEFNE` writer - Tx Event FIFO New Entry Interrupt Enable"] +pub struct TEFNE_W<'a> { + w: &'a mut W, +} +impl<'a> TEFNE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `TEFWE` reader - Tx Event FIFO Watermark Reached Interrupt Enable"] +pub struct TEFWE_R(crate::FieldReader); +impl TEFWE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TEFWE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TEFWE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TEFWE` writer - Tx Event FIFO Watermark Reached Interrupt Enable"] +pub struct TEFWE_W<'a> { + w: &'a mut W, +} +impl<'a> TEFWE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `TEFFE` reader - Tx Event FIFO Full Interrupt Enable"] +pub struct TEFFE_R(crate::FieldReader); +impl TEFFE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TEFFE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TEFFE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TEFFE` writer - Tx Event FIFO Full Interrupt Enable"] +pub struct TEFFE_W<'a> { + w: &'a mut W, +} +impl<'a> TEFFE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `TEFLE` reader - Tx Event FIFO Element Lost Interrupt Enable"] +pub struct TEFLE_R(crate::FieldReader); +impl TEFLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TEFLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TEFLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TEFLE` writer - Tx Event FIFO Element Lost Interrupt Enable"] +pub struct TEFLE_W<'a> { + w: &'a mut W, +} +impl<'a> TEFLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `TSWE` reader - Timestamp Wraparound Interrupt Enable"] +pub struct TSWE_R(crate::FieldReader); +impl TSWE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSWE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSWE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSWE` writer - Timestamp Wraparound Interrupt Enable"] +pub struct TSWE_W<'a> { + w: &'a mut W, +} +impl<'a> TSWE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `MRAFE` reader - Message RAM Access Failure Interrupt Enable"] +pub struct MRAFE_R(crate::FieldReader); +impl MRAFE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MRAFE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MRAFE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MRAFE` writer - Message RAM Access Failure Interrupt Enable"] +pub struct MRAFE_W<'a> { + w: &'a mut W, +} +impl<'a> MRAFE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `TOOE` reader - Timeout Occurred Interrupt Enable"] +pub struct TOOE_R(crate::FieldReader); +impl TOOE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TOOE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TOOE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TOOE` writer - Timeout Occurred Interrupt Enable"] +pub struct TOOE_W<'a> { + w: &'a mut W, +} +impl<'a> TOOE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `DRXE` reader - Message stored to Dedicated Rx Buffer Interrupt Enable"] +pub struct DRXE_R(crate::FieldReader); +impl DRXE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRXE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRXE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRXE` writer - Message stored to Dedicated Rx Buffer Interrupt Enable"] +pub struct DRXE_W<'a> { + w: &'a mut W, +} +impl<'a> DRXE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `BECE` reader - Bit Error Corrected Interrupt Enable"] +pub struct BECE_R(crate::FieldReader); +impl BECE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BECE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BECE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BECE` writer - Bit Error Corrected Interrupt Enable"] +pub struct BECE_W<'a> { + w: &'a mut W, +} +impl<'a> BECE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `BEUE` reader - Bit Error Uncorrected Interrupt Enable"] +pub struct BEUE_R(crate::FieldReader); +impl BEUE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BEUE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BEUE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BEUE` writer - Bit Error Uncorrected Interrupt Enable"] +pub struct BEUE_W<'a> { + w: &'a mut W, +} +impl<'a> BEUE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `ELOE` reader - Error Logging Overflow Interrupt Enable"] +pub struct ELOE_R(crate::FieldReader); +impl ELOE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ELOE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ELOE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ELOE` writer - Error Logging Overflow Interrupt Enable"] +pub struct ELOE_W<'a> { + w: &'a mut W, +} +impl<'a> ELOE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `EPE` reader - Error Passive Interrupt Enable"] +pub struct EPE_R(crate::FieldReader); +impl EPE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EPE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EPE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EPE` writer - Error Passive Interrupt Enable"] +pub struct EPE_W<'a> { + w: &'a mut W, +} +impl<'a> EPE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `EWE` reader - Warning Status Interrupt Enable"] +pub struct EWE_R(crate::FieldReader); +impl EWE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EWE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EWE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EWE` writer - Warning Status Interrupt Enable"] +pub struct EWE_W<'a> { + w: &'a mut W, +} +impl<'a> EWE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `BOE` reader - Bus_Off Status Interrupt Enable"] +pub struct BOE_R(crate::FieldReader); +impl BOE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BOE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BOE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BOE` writer - Bus_Off Status Interrupt Enable"] +pub struct BOE_W<'a> { + w: &'a mut W, +} +impl<'a> BOE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `WDIE` reader - Watchdog Interrupt Interrupt Enable"] +pub struct WDIE_R(crate::FieldReader); +impl WDIE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WDIE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WDIE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WDIE` writer - Watchdog Interrupt Interrupt Enable"] +pub struct WDIE_W<'a> { + w: &'a mut W, +} +impl<'a> WDIE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `PEAE` reader - Protocol Error in Arbitration Phase Enable"] +pub struct PEAE_R(crate::FieldReader); +impl PEAE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEAE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEAE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEAE` writer - Protocol Error in Arbitration Phase Enable"] +pub struct PEAE_W<'a> { + w: &'a mut W, +} +impl<'a> PEAE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +#[doc = "Field `PEDE` reader - Protocol Error in Data Phase Enable"] +pub struct PEDE_R(crate::FieldReader); +impl PEDE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEDE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEDE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEDE` writer - Protocol Error in Data Phase Enable"] +pub struct PEDE_W<'a> { + w: &'a mut W, +} +impl<'a> PEDE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Field `ARAE` reader - Access to Reserved Address Enable"] +pub struct ARAE_R(crate::FieldReader); +impl ARAE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ARAE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ARAE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ARAE` writer - Access to Reserved Address Enable"] +pub struct ARAE_W<'a> { + w: &'a mut W, +} +impl<'a> ARAE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29); + self.w + } +} +impl R { + #[doc = "Bit 0 - Rx FIFO 0 New Message Interrupt Enable"] + #[inline(always)] + pub fn rf0ne(&self) -> RF0NE_R { + RF0NE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Rx FIFO 0 Watermark Reached Interrupt Enable"] + #[inline(always)] + pub fn rf0we(&self) -> RF0WE_R { + RF0WE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Rx FIFO 0 Full Interrupt Enable"] + #[inline(always)] + pub fn rf0fe(&self) -> RF0FE_R { + RF0FE_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Rx FIFO 0 Message Lost Interrupt Enable"] + #[inline(always)] + pub fn rf0le(&self) -> RF0LE_R { + RF0LE_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Rx FIFO 1 New Message Interrupt Enable"] + #[inline(always)] + pub fn rf1ne(&self) -> RF1NE_R { + RF1NE_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Rx FIFO 1 Watermark Reached Interrupt Enable"] + #[inline(always)] + pub fn rf1we(&self) -> RF1WE_R { + RF1WE_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Rx FIFO 1 FIFO Full Interrupt Enable"] + #[inline(always)] + pub fn rf1fe(&self) -> RF1FE_R { + RF1FE_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Rx FIFO 1 Message Lost Interrupt Enable"] + #[inline(always)] + pub fn rf1le(&self) -> RF1LE_R { + RF1LE_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - High Priority Message Interrupt Enable"] + #[inline(always)] + pub fn hpme(&self) -> HPME_R { + HPME_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Timestamp Completed Interrupt Enable"] + #[inline(always)] + pub fn tce(&self) -> TCE_R { + TCE_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Transmission Cancellation Finished Interrupt Enable"] + #[inline(always)] + pub fn tcfe(&self) -> TCFE_R { + TCFE_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Tx FIFO Empty Interrupt Enable"] + #[inline(always)] + pub fn tfee(&self) -> TFEE_R { + TFEE_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Tx Event FIFO New Entry Interrupt Enable"] + #[inline(always)] + pub fn tefne(&self) -> TEFNE_R { + TEFNE_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Tx Event FIFO Watermark Reached Interrupt Enable"] + #[inline(always)] + pub fn tefwe(&self) -> TEFWE_R { + TEFWE_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Tx Event FIFO Full Interrupt Enable"] + #[inline(always)] + pub fn teffe(&self) -> TEFFE_R { + TEFFE_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Tx Event FIFO Element Lost Interrupt Enable"] + #[inline(always)] + pub fn tefle(&self) -> TEFLE_R { + TEFLE_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Timestamp Wraparound Interrupt Enable"] + #[inline(always)] + pub fn tswe(&self) -> TSWE_R { + TSWE_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Message RAM Access Failure Interrupt Enable"] + #[inline(always)] + pub fn mrafe(&self) -> MRAFE_R { + MRAFE_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Timeout Occurred Interrupt Enable"] + #[inline(always)] + pub fn tooe(&self) -> TOOE_R { + TOOE_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Message stored to Dedicated Rx Buffer Interrupt Enable"] + #[inline(always)] + pub fn drxe(&self) -> DRXE_R { + DRXE_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Bit Error Corrected Interrupt Enable"] + #[inline(always)] + pub fn bece(&self) -> BECE_R { + BECE_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Bit Error Uncorrected Interrupt Enable"] + #[inline(always)] + pub fn beue(&self) -> BEUE_R { + BEUE_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Error Logging Overflow Interrupt Enable"] + #[inline(always)] + pub fn eloe(&self) -> ELOE_R { + ELOE_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Error Passive Interrupt Enable"] + #[inline(always)] + pub fn epe(&self) -> EPE_R { + EPE_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24 - Warning Status Interrupt Enable"] + #[inline(always)] + pub fn ewe(&self) -> EWE_R { + EWE_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Bus_Off Status Interrupt Enable"] + #[inline(always)] + pub fn boe(&self) -> BOE_R { + BOE_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Watchdog Interrupt Interrupt Enable"] + #[inline(always)] + pub fn wdie(&self) -> WDIE_R { + WDIE_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Protocol Error in Arbitration Phase Enable"] + #[inline(always)] + pub fn peae(&self) -> PEAE_R { + PEAE_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28 - Protocol Error in Data Phase Enable"] + #[inline(always)] + pub fn pede(&self) -> PEDE_R { + PEDE_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Access to Reserved Address Enable"] + #[inline(always)] + pub fn arae(&self) -> ARAE_R { + ARAE_R::new(((self.bits >> 29) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Rx FIFO 0 New Message Interrupt Enable"] + #[inline(always)] + pub fn rf0ne(&mut self) -> RF0NE_W { + RF0NE_W { w: self } + } + #[doc = "Bit 1 - Rx FIFO 0 Watermark Reached Interrupt Enable"] + #[inline(always)] + pub fn rf0we(&mut self) -> RF0WE_W { + RF0WE_W { w: self } + } + #[doc = "Bit 2 - Rx FIFO 0 Full Interrupt Enable"] + #[inline(always)] + pub fn rf0fe(&mut self) -> RF0FE_W { + RF0FE_W { w: self } + } + #[doc = "Bit 3 - Rx FIFO 0 Message Lost Interrupt Enable"] + #[inline(always)] + pub fn rf0le(&mut self) -> RF0LE_W { + RF0LE_W { w: self } + } + #[doc = "Bit 4 - Rx FIFO 1 New Message Interrupt Enable"] + #[inline(always)] + pub fn rf1ne(&mut self) -> RF1NE_W { + RF1NE_W { w: self } + } + #[doc = "Bit 5 - Rx FIFO 1 Watermark Reached Interrupt Enable"] + #[inline(always)] + pub fn rf1we(&mut self) -> RF1WE_W { + RF1WE_W { w: self } + } + #[doc = "Bit 6 - Rx FIFO 1 FIFO Full Interrupt Enable"] + #[inline(always)] + pub fn rf1fe(&mut self) -> RF1FE_W { + RF1FE_W { w: self } + } + #[doc = "Bit 7 - Rx FIFO 1 Message Lost Interrupt Enable"] + #[inline(always)] + pub fn rf1le(&mut self) -> RF1LE_W { + RF1LE_W { w: self } + } + #[doc = "Bit 8 - High Priority Message Interrupt Enable"] + #[inline(always)] + pub fn hpme(&mut self) -> HPME_W { + HPME_W { w: self } + } + #[doc = "Bit 9 - Timestamp Completed Interrupt Enable"] + #[inline(always)] + pub fn tce(&mut self) -> TCE_W { + TCE_W { w: self } + } + #[doc = "Bit 10 - Transmission Cancellation Finished Interrupt Enable"] + #[inline(always)] + pub fn tcfe(&mut self) -> TCFE_W { + TCFE_W { w: self } + } + #[doc = "Bit 11 - Tx FIFO Empty Interrupt Enable"] + #[inline(always)] + pub fn tfee(&mut self) -> TFEE_W { + TFEE_W { w: self } + } + #[doc = "Bit 12 - Tx Event FIFO New Entry Interrupt Enable"] + #[inline(always)] + pub fn tefne(&mut self) -> TEFNE_W { + TEFNE_W { w: self } + } + #[doc = "Bit 13 - Tx Event FIFO Watermark Reached Interrupt Enable"] + #[inline(always)] + pub fn tefwe(&mut self) -> TEFWE_W { + TEFWE_W { w: self } + } + #[doc = "Bit 14 - Tx Event FIFO Full Interrupt Enable"] + #[inline(always)] + pub fn teffe(&mut self) -> TEFFE_W { + TEFFE_W { w: self } + } + #[doc = "Bit 15 - Tx Event FIFO Element Lost Interrupt Enable"] + #[inline(always)] + pub fn tefle(&mut self) -> TEFLE_W { + TEFLE_W { w: self } + } + #[doc = "Bit 16 - Timestamp Wraparound Interrupt Enable"] + #[inline(always)] + pub fn tswe(&mut self) -> TSWE_W { + TSWE_W { w: self } + } + #[doc = "Bit 17 - Message RAM Access Failure Interrupt Enable"] + #[inline(always)] + pub fn mrafe(&mut self) -> MRAFE_W { + MRAFE_W { w: self } + } + #[doc = "Bit 18 - Timeout Occurred Interrupt Enable"] + #[inline(always)] + pub fn tooe(&mut self) -> TOOE_W { + TOOE_W { w: self } + } + #[doc = "Bit 19 - Message stored to Dedicated Rx Buffer Interrupt Enable"] + #[inline(always)] + pub fn drxe(&mut self) -> DRXE_W { + DRXE_W { w: self } + } + #[doc = "Bit 20 - Bit Error Corrected Interrupt Enable"] + #[inline(always)] + pub fn bece(&mut self) -> BECE_W { + BECE_W { w: self } + } + #[doc = "Bit 21 - Bit Error Uncorrected Interrupt Enable"] + #[inline(always)] + pub fn beue(&mut self) -> BEUE_W { + BEUE_W { w: self } + } + #[doc = "Bit 22 - Error Logging Overflow Interrupt Enable"] + #[inline(always)] + pub fn eloe(&mut self) -> ELOE_W { + ELOE_W { w: self } + } + #[doc = "Bit 23 - Error Passive Interrupt Enable"] + #[inline(always)] + pub fn epe(&mut self) -> EPE_W { + EPE_W { w: self } + } + #[doc = "Bit 24 - Warning Status Interrupt Enable"] + #[inline(always)] + pub fn ewe(&mut self) -> EWE_W { + EWE_W { w: self } + } + #[doc = "Bit 25 - Bus_Off Status Interrupt Enable"] + #[inline(always)] + pub fn boe(&mut self) -> BOE_W { + BOE_W { w: self } + } + #[doc = "Bit 26 - Watchdog Interrupt Interrupt Enable"] + #[inline(always)] + pub fn wdie(&mut self) -> WDIE_W { + WDIE_W { w: self } + } + #[doc = "Bit 27 - Protocol Error in Arbitration Phase Enable"] + #[inline(always)] + pub fn peae(&mut self) -> PEAE_W { + PEAE_W { w: self } + } + #[doc = "Bit 28 - Protocol Error in Data Phase Enable"] + #[inline(always)] + pub fn pede(&mut self) -> PEDE_W { + PEDE_W { w: self } + } + #[doc = "Bit 29 - Access to Reserved Address Enable"] + #[inline(always)] + pub fn arae(&mut self) -> ARAE_W { + ARAE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ie](index.html) module"] +pub struct IE_SPEC; +impl crate::RegisterSpec for IE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ie::R](R) reader structure"] +impl crate::Readable for IE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ie::W](W) writer structure"] +impl crate::Writable for IE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets IE to value 0"] +impl crate::Resettable for IE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/can0/ile.rs b/pac/atsamc21e/src/can0/ile.rs new file mode 100644 index 000000000000..3284b08f7d4c --- /dev/null +++ b/pac/atsamc21e/src/can0/ile.rs @@ -0,0 +1,160 @@ +#[doc = "Register `ILE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ILE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EINT0` reader - Enable Interrupt Line 0"] +pub struct EINT0_R(crate::FieldReader); +impl EINT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EINT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EINT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EINT0` writer - Enable Interrupt Line 0"] +pub struct EINT0_W<'a> { + w: &'a mut W, +} +impl<'a> EINT0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `EINT1` reader - Enable Interrupt Line 1"] +pub struct EINT1_R(crate::FieldReader); +impl EINT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EINT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EINT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EINT1` writer - Enable Interrupt Line 1"] +pub struct EINT1_W<'a> { + w: &'a mut W, +} +impl<'a> EINT1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - Enable Interrupt Line 0"] + #[inline(always)] + pub fn eint0(&self) -> EINT0_R { + EINT0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable Interrupt Line 1"] + #[inline(always)] + pub fn eint1(&self) -> EINT1_R { + EINT1_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Enable Interrupt Line 0"] + #[inline(always)] + pub fn eint0(&mut self) -> EINT0_W { + EINT0_W { w: self } + } + #[doc = "Bit 1 - Enable Interrupt Line 1"] + #[inline(always)] + pub fn eint1(&mut self) -> EINT1_W { + EINT1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Line Enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ile](index.html) module"] +pub struct ILE_SPEC; +impl crate::RegisterSpec for ILE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ile::R](R) reader structure"] +impl crate::Readable for ILE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ile::W](W) writer structure"] +impl crate::Writable for ILE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ILE to value 0"] +impl crate::Resettable for ILE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/can0/ils.rs b/pac/atsamc21e/src/can0/ils.rs new file mode 100644 index 000000000000..14ac6de68d59 --- /dev/null +++ b/pac/atsamc21e/src/can0/ils.rs @@ -0,0 +1,1476 @@ +#[doc = "Register `ILS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ILS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RF0NL` reader - Rx FIFO 0 New Message Interrupt Line"] +pub struct RF0NL_R(crate::FieldReader); +impl RF0NL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF0NL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF0NL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF0NL` writer - Rx FIFO 0 New Message Interrupt Line"] +pub struct RF0NL_W<'a> { + w: &'a mut W, +} +impl<'a> RF0NL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `RF0WL` reader - Rx FIFO 0 Watermark Reached Interrupt Line"] +pub struct RF0WL_R(crate::FieldReader); +impl RF0WL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF0WL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF0WL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF0WL` writer - Rx FIFO 0 Watermark Reached Interrupt Line"] +pub struct RF0WL_W<'a> { + w: &'a mut W, +} +impl<'a> RF0WL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RF0FL` reader - Rx FIFO 0 Full Interrupt Line"] +pub struct RF0FL_R(crate::FieldReader); +impl RF0FL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF0FL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF0FL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF0FL` writer - Rx FIFO 0 Full Interrupt Line"] +pub struct RF0FL_W<'a> { + w: &'a mut W, +} +impl<'a> RF0FL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RF0LL` reader - Rx FIFO 0 Message Lost Interrupt Line"] +pub struct RF0LL_R(crate::FieldReader); +impl RF0LL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF0LL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF0LL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF0LL` writer - Rx FIFO 0 Message Lost Interrupt Line"] +pub struct RF0LL_W<'a> { + w: &'a mut W, +} +impl<'a> RF0LL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `RF1NL` reader - Rx FIFO 1 New Message Interrupt Line"] +pub struct RF1NL_R(crate::FieldReader); +impl RF1NL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF1NL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF1NL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF1NL` writer - Rx FIFO 1 New Message Interrupt Line"] +pub struct RF1NL_W<'a> { + w: &'a mut W, +} +impl<'a> RF1NL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RF1WL` reader - Rx FIFO 1 Watermark Reached Interrupt Line"] +pub struct RF1WL_R(crate::FieldReader); +impl RF1WL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF1WL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF1WL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF1WL` writer - Rx FIFO 1 Watermark Reached Interrupt Line"] +pub struct RF1WL_W<'a> { + w: &'a mut W, +} +impl<'a> RF1WL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `RF1FL` reader - Rx FIFO 1 FIFO Full Interrupt Line"] +pub struct RF1FL_R(crate::FieldReader); +impl RF1FL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF1FL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF1FL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF1FL` writer - Rx FIFO 1 FIFO Full Interrupt Line"] +pub struct RF1FL_W<'a> { + w: &'a mut W, +} +impl<'a> RF1FL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `RF1LL` reader - Rx FIFO 1 Message Lost Interrupt Line"] +pub struct RF1LL_R(crate::FieldReader); +impl RF1LL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF1LL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF1LL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF1LL` writer - Rx FIFO 1 Message Lost Interrupt Line"] +pub struct RF1LL_W<'a> { + w: &'a mut W, +} +impl<'a> RF1LL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `HPML` reader - High Priority Message Interrupt Line"] +pub struct HPML_R(crate::FieldReader); +impl HPML_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HPML_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HPML_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HPML` writer - High Priority Message Interrupt Line"] +pub struct HPML_W<'a> { + w: &'a mut W, +} +impl<'a> HPML_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `TCL` reader - Timestamp Completed Interrupt Line"] +pub struct TCL_R(crate::FieldReader); +impl TCL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCL` writer - Timestamp Completed Interrupt Line"] +pub struct TCL_W<'a> { + w: &'a mut W, +} +impl<'a> TCL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `TCFL` reader - Transmission Cancellation Finished Interrupt Line"] +pub struct TCFL_R(crate::FieldReader); +impl TCFL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCFL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCFL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCFL` writer - Transmission Cancellation Finished Interrupt Line"] +pub struct TCFL_W<'a> { + w: &'a mut W, +} +impl<'a> TCFL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `TFEL` reader - Tx FIFO Empty Interrupt Line"] +pub struct TFEL_R(crate::FieldReader); +impl TFEL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TFEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TFEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TFEL` writer - Tx FIFO Empty Interrupt Line"] +pub struct TFEL_W<'a> { + w: &'a mut W, +} +impl<'a> TFEL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `TEFNL` reader - Tx Event FIFO New Entry Interrupt Line"] +pub struct TEFNL_R(crate::FieldReader); +impl TEFNL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TEFNL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TEFNL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TEFNL` writer - Tx Event FIFO New Entry Interrupt Line"] +pub struct TEFNL_W<'a> { + w: &'a mut W, +} +impl<'a> TEFNL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `TEFWL` reader - Tx Event FIFO Watermark Reached Interrupt Line"] +pub struct TEFWL_R(crate::FieldReader); +impl TEFWL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TEFWL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TEFWL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TEFWL` writer - Tx Event FIFO Watermark Reached Interrupt Line"] +pub struct TEFWL_W<'a> { + w: &'a mut W, +} +impl<'a> TEFWL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `TEFFL` reader - Tx Event FIFO Full Interrupt Line"] +pub struct TEFFL_R(crate::FieldReader); +impl TEFFL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TEFFL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TEFFL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TEFFL` writer - Tx Event FIFO Full Interrupt Line"] +pub struct TEFFL_W<'a> { + w: &'a mut W, +} +impl<'a> TEFFL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `TEFLL` reader - Tx Event FIFO Element Lost Interrupt Line"] +pub struct TEFLL_R(crate::FieldReader); +impl TEFLL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TEFLL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TEFLL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TEFLL` writer - Tx Event FIFO Element Lost Interrupt Line"] +pub struct TEFLL_W<'a> { + w: &'a mut W, +} +impl<'a> TEFLL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `TSWL` reader - Timestamp Wraparound Interrupt Line"] +pub struct TSWL_R(crate::FieldReader); +impl TSWL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSWL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSWL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSWL` writer - Timestamp Wraparound Interrupt Line"] +pub struct TSWL_W<'a> { + w: &'a mut W, +} +impl<'a> TSWL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `MRAFL` reader - Message RAM Access Failure Interrupt Line"] +pub struct MRAFL_R(crate::FieldReader); +impl MRAFL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MRAFL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MRAFL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MRAFL` writer - Message RAM Access Failure Interrupt Line"] +pub struct MRAFL_W<'a> { + w: &'a mut W, +} +impl<'a> MRAFL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `TOOL` reader - Timeout Occurred Interrupt Line"] +pub struct TOOL_R(crate::FieldReader); +impl TOOL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TOOL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TOOL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TOOL` writer - Timeout Occurred Interrupt Line"] +pub struct TOOL_W<'a> { + w: &'a mut W, +} +impl<'a> TOOL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `DRXL` reader - Message stored to Dedicated Rx Buffer Interrupt Line"] +pub struct DRXL_R(crate::FieldReader); +impl DRXL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRXL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRXL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRXL` writer - Message stored to Dedicated Rx Buffer Interrupt Line"] +pub struct DRXL_W<'a> { + w: &'a mut W, +} +impl<'a> DRXL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `BECL` reader - Bit Error Corrected Interrupt Line"] +pub struct BECL_R(crate::FieldReader); +impl BECL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BECL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BECL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BECL` writer - Bit Error Corrected Interrupt Line"] +pub struct BECL_W<'a> { + w: &'a mut W, +} +impl<'a> BECL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `BEUL` reader - Bit Error Uncorrected Interrupt Line"] +pub struct BEUL_R(crate::FieldReader); +impl BEUL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BEUL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BEUL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BEUL` writer - Bit Error Uncorrected Interrupt Line"] +pub struct BEUL_W<'a> { + w: &'a mut W, +} +impl<'a> BEUL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `ELOL` reader - Error Logging Overflow Interrupt Line"] +pub struct ELOL_R(crate::FieldReader); +impl ELOL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ELOL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ELOL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ELOL` writer - Error Logging Overflow Interrupt Line"] +pub struct ELOL_W<'a> { + w: &'a mut W, +} +impl<'a> ELOL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `EPL` reader - Error Passive Interrupt Line"] +pub struct EPL_R(crate::FieldReader); +impl EPL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EPL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EPL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EPL` writer - Error Passive Interrupt Line"] +pub struct EPL_W<'a> { + w: &'a mut W, +} +impl<'a> EPL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `EWL` reader - Warning Status Interrupt Line"] +pub struct EWL_R(crate::FieldReader); +impl EWL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EWL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EWL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EWL` writer - Warning Status Interrupt Line"] +pub struct EWL_W<'a> { + w: &'a mut W, +} +impl<'a> EWL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `BOL` reader - Bus_Off Status Interrupt Line"] +pub struct BOL_R(crate::FieldReader); +impl BOL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BOL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BOL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BOL` writer - Bus_Off Status Interrupt Line"] +pub struct BOL_W<'a> { + w: &'a mut W, +} +impl<'a> BOL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `WDIL` reader - Watchdog Interrupt Interrupt Line"] +pub struct WDIL_R(crate::FieldReader); +impl WDIL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WDIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WDIL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WDIL` writer - Watchdog Interrupt Interrupt Line"] +pub struct WDIL_W<'a> { + w: &'a mut W, +} +impl<'a> WDIL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `PEAL` reader - Protocol Error in Arbitration Phase Line"] +pub struct PEAL_R(crate::FieldReader); +impl PEAL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEAL` writer - Protocol Error in Arbitration Phase Line"] +pub struct PEAL_W<'a> { + w: &'a mut W, +} +impl<'a> PEAL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +#[doc = "Field `PEDL` reader - Protocol Error in Data Phase Line"] +pub struct PEDL_R(crate::FieldReader); +impl PEDL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEDL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEDL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEDL` writer - Protocol Error in Data Phase Line"] +pub struct PEDL_W<'a> { + w: &'a mut W, +} +impl<'a> PEDL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Field `ARAL` reader - Access to Reserved Address Line"] +pub struct ARAL_R(crate::FieldReader); +impl ARAL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ARAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ARAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ARAL` writer - Access to Reserved Address Line"] +pub struct ARAL_W<'a> { + w: &'a mut W, +} +impl<'a> ARAL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29); + self.w + } +} +impl R { + #[doc = "Bit 0 - Rx FIFO 0 New Message Interrupt Line"] + #[inline(always)] + pub fn rf0nl(&self) -> RF0NL_R { + RF0NL_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Rx FIFO 0 Watermark Reached Interrupt Line"] + #[inline(always)] + pub fn rf0wl(&self) -> RF0WL_R { + RF0WL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Rx FIFO 0 Full Interrupt Line"] + #[inline(always)] + pub fn rf0fl(&self) -> RF0FL_R { + RF0FL_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Rx FIFO 0 Message Lost Interrupt Line"] + #[inline(always)] + pub fn rf0ll(&self) -> RF0LL_R { + RF0LL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Rx FIFO 1 New Message Interrupt Line"] + #[inline(always)] + pub fn rf1nl(&self) -> RF1NL_R { + RF1NL_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Rx FIFO 1 Watermark Reached Interrupt Line"] + #[inline(always)] + pub fn rf1wl(&self) -> RF1WL_R { + RF1WL_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Rx FIFO 1 FIFO Full Interrupt Line"] + #[inline(always)] + pub fn rf1fl(&self) -> RF1FL_R { + RF1FL_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Rx FIFO 1 Message Lost Interrupt Line"] + #[inline(always)] + pub fn rf1ll(&self) -> RF1LL_R { + RF1LL_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - High Priority Message Interrupt Line"] + #[inline(always)] + pub fn hpml(&self) -> HPML_R { + HPML_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Timestamp Completed Interrupt Line"] + #[inline(always)] + pub fn tcl(&self) -> TCL_R { + TCL_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Transmission Cancellation Finished Interrupt Line"] + #[inline(always)] + pub fn tcfl(&self) -> TCFL_R { + TCFL_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Tx FIFO Empty Interrupt Line"] + #[inline(always)] + pub fn tfel(&self) -> TFEL_R { + TFEL_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Tx Event FIFO New Entry Interrupt Line"] + #[inline(always)] + pub fn tefnl(&self) -> TEFNL_R { + TEFNL_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Tx Event FIFO Watermark Reached Interrupt Line"] + #[inline(always)] + pub fn tefwl(&self) -> TEFWL_R { + TEFWL_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Tx Event FIFO Full Interrupt Line"] + #[inline(always)] + pub fn teffl(&self) -> TEFFL_R { + TEFFL_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Tx Event FIFO Element Lost Interrupt Line"] + #[inline(always)] + pub fn tefll(&self) -> TEFLL_R { + TEFLL_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Timestamp Wraparound Interrupt Line"] + #[inline(always)] + pub fn tswl(&self) -> TSWL_R { + TSWL_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Message RAM Access Failure Interrupt Line"] + #[inline(always)] + pub fn mrafl(&self) -> MRAFL_R { + MRAFL_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Timeout Occurred Interrupt Line"] + #[inline(always)] + pub fn tool(&self) -> TOOL_R { + TOOL_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Message stored to Dedicated Rx Buffer Interrupt Line"] + #[inline(always)] + pub fn drxl(&self) -> DRXL_R { + DRXL_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Bit Error Corrected Interrupt Line"] + #[inline(always)] + pub fn becl(&self) -> BECL_R { + BECL_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Bit Error Uncorrected Interrupt Line"] + #[inline(always)] + pub fn beul(&self) -> BEUL_R { + BEUL_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Error Logging Overflow Interrupt Line"] + #[inline(always)] + pub fn elol(&self) -> ELOL_R { + ELOL_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Error Passive Interrupt Line"] + #[inline(always)] + pub fn epl(&self) -> EPL_R { + EPL_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24 - Warning Status Interrupt Line"] + #[inline(always)] + pub fn ewl(&self) -> EWL_R { + EWL_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Bus_Off Status Interrupt Line"] + #[inline(always)] + pub fn bol(&self) -> BOL_R { + BOL_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Watchdog Interrupt Interrupt Line"] + #[inline(always)] + pub fn wdil(&self) -> WDIL_R { + WDIL_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Protocol Error in Arbitration Phase Line"] + #[inline(always)] + pub fn peal(&self) -> PEAL_R { + PEAL_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28 - Protocol Error in Data Phase Line"] + #[inline(always)] + pub fn pedl(&self) -> PEDL_R { + PEDL_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Access to Reserved Address Line"] + #[inline(always)] + pub fn aral(&self) -> ARAL_R { + ARAL_R::new(((self.bits >> 29) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Rx FIFO 0 New Message Interrupt Line"] + #[inline(always)] + pub fn rf0nl(&mut self) -> RF0NL_W { + RF0NL_W { w: self } + } + #[doc = "Bit 1 - Rx FIFO 0 Watermark Reached Interrupt Line"] + #[inline(always)] + pub fn rf0wl(&mut self) -> RF0WL_W { + RF0WL_W { w: self } + } + #[doc = "Bit 2 - Rx FIFO 0 Full Interrupt Line"] + #[inline(always)] + pub fn rf0fl(&mut self) -> RF0FL_W { + RF0FL_W { w: self } + } + #[doc = "Bit 3 - Rx FIFO 0 Message Lost Interrupt Line"] + #[inline(always)] + pub fn rf0ll(&mut self) -> RF0LL_W { + RF0LL_W { w: self } + } + #[doc = "Bit 4 - Rx FIFO 1 New Message Interrupt Line"] + #[inline(always)] + pub fn rf1nl(&mut self) -> RF1NL_W { + RF1NL_W { w: self } + } + #[doc = "Bit 5 - Rx FIFO 1 Watermark Reached Interrupt Line"] + #[inline(always)] + pub fn rf1wl(&mut self) -> RF1WL_W { + RF1WL_W { w: self } + } + #[doc = "Bit 6 - Rx FIFO 1 FIFO Full Interrupt Line"] + #[inline(always)] + pub fn rf1fl(&mut self) -> RF1FL_W { + RF1FL_W { w: self } + } + #[doc = "Bit 7 - Rx FIFO 1 Message Lost Interrupt Line"] + #[inline(always)] + pub fn rf1ll(&mut self) -> RF1LL_W { + RF1LL_W { w: self } + } + #[doc = "Bit 8 - High Priority Message Interrupt Line"] + #[inline(always)] + pub fn hpml(&mut self) -> HPML_W { + HPML_W { w: self } + } + #[doc = "Bit 9 - Timestamp Completed Interrupt Line"] + #[inline(always)] + pub fn tcl(&mut self) -> TCL_W { + TCL_W { w: self } + } + #[doc = "Bit 10 - Transmission Cancellation Finished Interrupt Line"] + #[inline(always)] + pub fn tcfl(&mut self) -> TCFL_W { + TCFL_W { w: self } + } + #[doc = "Bit 11 - Tx FIFO Empty Interrupt Line"] + #[inline(always)] + pub fn tfel(&mut self) -> TFEL_W { + TFEL_W { w: self } + } + #[doc = "Bit 12 - Tx Event FIFO New Entry Interrupt Line"] + #[inline(always)] + pub fn tefnl(&mut self) -> TEFNL_W { + TEFNL_W { w: self } + } + #[doc = "Bit 13 - Tx Event FIFO Watermark Reached Interrupt Line"] + #[inline(always)] + pub fn tefwl(&mut self) -> TEFWL_W { + TEFWL_W { w: self } + } + #[doc = "Bit 14 - Tx Event FIFO Full Interrupt Line"] + #[inline(always)] + pub fn teffl(&mut self) -> TEFFL_W { + TEFFL_W { w: self } + } + #[doc = "Bit 15 - Tx Event FIFO Element Lost Interrupt Line"] + #[inline(always)] + pub fn tefll(&mut self) -> TEFLL_W { + TEFLL_W { w: self } + } + #[doc = "Bit 16 - Timestamp Wraparound Interrupt Line"] + #[inline(always)] + pub fn tswl(&mut self) -> TSWL_W { + TSWL_W { w: self } + } + #[doc = "Bit 17 - Message RAM Access Failure Interrupt Line"] + #[inline(always)] + pub fn mrafl(&mut self) -> MRAFL_W { + MRAFL_W { w: self } + } + #[doc = "Bit 18 - Timeout Occurred Interrupt Line"] + #[inline(always)] + pub fn tool(&mut self) -> TOOL_W { + TOOL_W { w: self } + } + #[doc = "Bit 19 - Message stored to Dedicated Rx Buffer Interrupt Line"] + #[inline(always)] + pub fn drxl(&mut self) -> DRXL_W { + DRXL_W { w: self } + } + #[doc = "Bit 20 - Bit Error Corrected Interrupt Line"] + #[inline(always)] + pub fn becl(&mut self) -> BECL_W { + BECL_W { w: self } + } + #[doc = "Bit 21 - Bit Error Uncorrected Interrupt Line"] + #[inline(always)] + pub fn beul(&mut self) -> BEUL_W { + BEUL_W { w: self } + } + #[doc = "Bit 22 - Error Logging Overflow Interrupt Line"] + #[inline(always)] + pub fn elol(&mut self) -> ELOL_W { + ELOL_W { w: self } + } + #[doc = "Bit 23 - Error Passive Interrupt Line"] + #[inline(always)] + pub fn epl(&mut self) -> EPL_W { + EPL_W { w: self } + } + #[doc = "Bit 24 - Warning Status Interrupt Line"] + #[inline(always)] + pub fn ewl(&mut self) -> EWL_W { + EWL_W { w: self } + } + #[doc = "Bit 25 - Bus_Off Status Interrupt Line"] + #[inline(always)] + pub fn bol(&mut self) -> BOL_W { + BOL_W { w: self } + } + #[doc = "Bit 26 - Watchdog Interrupt Interrupt Line"] + #[inline(always)] + pub fn wdil(&mut self) -> WDIL_W { + WDIL_W { w: self } + } + #[doc = "Bit 27 - Protocol Error in Arbitration Phase Line"] + #[inline(always)] + pub fn peal(&mut self) -> PEAL_W { + PEAL_W { w: self } + } + #[doc = "Bit 28 - Protocol Error in Data Phase Line"] + #[inline(always)] + pub fn pedl(&mut self) -> PEDL_W { + PEDL_W { w: self } + } + #[doc = "Bit 29 - Access to Reserved Address Line"] + #[inline(always)] + pub fn aral(&mut self) -> ARAL_W { + ARAL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Line Select\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ils](index.html) module"] +pub struct ILS_SPEC; +impl crate::RegisterSpec for ILS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ils::R](R) reader structure"] +impl crate::Readable for ILS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ils::W](W) writer structure"] +impl crate::Writable for ILS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ILS to value 0"] +impl crate::Resettable for ILS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/can0/ir.rs b/pac/atsamc21e/src/can0/ir.rs new file mode 100644 index 000000000000..ae6efc178861 --- /dev/null +++ b/pac/atsamc21e/src/can0/ir.rs @@ -0,0 +1,1476 @@ +#[doc = "Register `IR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `IR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RF0N` reader - Rx FIFO 0 New Message"] +pub struct RF0N_R(crate::FieldReader); +impl RF0N_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF0N_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF0N_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF0N` writer - Rx FIFO 0 New Message"] +pub struct RF0N_W<'a> { + w: &'a mut W, +} +impl<'a> RF0N_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `RF0W` reader - Rx FIFO 0 Watermark Reached"] +pub struct RF0W_R(crate::FieldReader); +impl RF0W_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF0W_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF0W_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF0W` writer - Rx FIFO 0 Watermark Reached"] +pub struct RF0W_W<'a> { + w: &'a mut W, +} +impl<'a> RF0W_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RF0F` reader - Rx FIFO 0 Full"] +pub struct RF0F_R(crate::FieldReader); +impl RF0F_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF0F_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF0F_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF0F` writer - Rx FIFO 0 Full"] +pub struct RF0F_W<'a> { + w: &'a mut W, +} +impl<'a> RF0F_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RF0L` reader - Rx FIFO 0 Message Lost"] +pub struct RF0L_R(crate::FieldReader); +impl RF0L_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF0L_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF0L_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF0L` writer - Rx FIFO 0 Message Lost"] +pub struct RF0L_W<'a> { + w: &'a mut W, +} +impl<'a> RF0L_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `RF1N` reader - Rx FIFO 1 New Message"] +pub struct RF1N_R(crate::FieldReader); +impl RF1N_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF1N_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF1N_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF1N` writer - Rx FIFO 1 New Message"] +pub struct RF1N_W<'a> { + w: &'a mut W, +} +impl<'a> RF1N_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RF1W` reader - Rx FIFO 1 Watermark Reached"] +pub struct RF1W_R(crate::FieldReader); +impl RF1W_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF1W_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF1W_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF1W` writer - Rx FIFO 1 Watermark Reached"] +pub struct RF1W_W<'a> { + w: &'a mut W, +} +impl<'a> RF1W_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `RF1F` reader - Rx FIFO 1 FIFO Full"] +pub struct RF1F_R(crate::FieldReader); +impl RF1F_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF1F_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF1F_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF1F` writer - Rx FIFO 1 FIFO Full"] +pub struct RF1F_W<'a> { + w: &'a mut W, +} +impl<'a> RF1F_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `RF1L` reader - Rx FIFO 1 Message Lost"] +pub struct RF1L_R(crate::FieldReader); +impl RF1L_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF1L_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF1L_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF1L` writer - Rx FIFO 1 Message Lost"] +pub struct RF1L_W<'a> { + w: &'a mut W, +} +impl<'a> RF1L_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `HPM` reader - High Priority Message"] +pub struct HPM_R(crate::FieldReader); +impl HPM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HPM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HPM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HPM` writer - High Priority Message"] +pub struct HPM_W<'a> { + w: &'a mut W, +} +impl<'a> HPM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `TC` reader - Timestamp Completed"] +pub struct TC_R(crate::FieldReader); +impl TC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC` writer - Timestamp Completed"] +pub struct TC_W<'a> { + w: &'a mut W, +} +impl<'a> TC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `TCF` reader - Transmission Cancellation Finished"] +pub struct TCF_R(crate::FieldReader); +impl TCF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCF` writer - Transmission Cancellation Finished"] +pub struct TCF_W<'a> { + w: &'a mut W, +} +impl<'a> TCF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `TFE` reader - Tx FIFO Empty"] +pub struct TFE_R(crate::FieldReader); +impl TFE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TFE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TFE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TFE` writer - Tx FIFO Empty"] +pub struct TFE_W<'a> { + w: &'a mut W, +} +impl<'a> TFE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `TEFN` reader - Tx Event FIFO New Entry"] +pub struct TEFN_R(crate::FieldReader); +impl TEFN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TEFN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TEFN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TEFN` writer - Tx Event FIFO New Entry"] +pub struct TEFN_W<'a> { + w: &'a mut W, +} +impl<'a> TEFN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `TEFW` reader - Tx Event FIFO Watermark Reached"] +pub struct TEFW_R(crate::FieldReader); +impl TEFW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TEFW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TEFW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TEFW` writer - Tx Event FIFO Watermark Reached"] +pub struct TEFW_W<'a> { + w: &'a mut W, +} +impl<'a> TEFW_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `TEFF` reader - Tx Event FIFO Full"] +pub struct TEFF_R(crate::FieldReader); +impl TEFF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TEFF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TEFF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TEFF` writer - Tx Event FIFO Full"] +pub struct TEFF_W<'a> { + w: &'a mut W, +} +impl<'a> TEFF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `TEFL` reader - Tx Event FIFO Element Lost"] +pub struct TEFL_R(crate::FieldReader); +impl TEFL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TEFL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TEFL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TEFL` writer - Tx Event FIFO Element Lost"] +pub struct TEFL_W<'a> { + w: &'a mut W, +} +impl<'a> TEFL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `TSW` reader - Timestamp Wraparound"] +pub struct TSW_R(crate::FieldReader); +impl TSW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSW` writer - Timestamp Wraparound"] +pub struct TSW_W<'a> { + w: &'a mut W, +} +impl<'a> TSW_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `MRAF` reader - Message RAM Access Failure"] +pub struct MRAF_R(crate::FieldReader); +impl MRAF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MRAF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MRAF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MRAF` writer - Message RAM Access Failure"] +pub struct MRAF_W<'a> { + w: &'a mut W, +} +impl<'a> MRAF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `TOO` reader - Timeout Occurred"] +pub struct TOO_R(crate::FieldReader); +impl TOO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TOO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TOO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TOO` writer - Timeout Occurred"] +pub struct TOO_W<'a> { + w: &'a mut W, +} +impl<'a> TOO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `DRX` reader - Message stored to Dedicated Rx Buffer"] +pub struct DRX_R(crate::FieldReader); +impl DRX_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRX_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRX_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRX` writer - Message stored to Dedicated Rx Buffer"] +pub struct DRX_W<'a> { + w: &'a mut W, +} +impl<'a> DRX_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `BEC` reader - Bit Error Corrected"] +pub struct BEC_R(crate::FieldReader); +impl BEC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BEC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BEC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BEC` writer - Bit Error Corrected"] +pub struct BEC_W<'a> { + w: &'a mut W, +} +impl<'a> BEC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `BEU` reader - Bit Error Uncorrected"] +pub struct BEU_R(crate::FieldReader); +impl BEU_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BEU_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BEU_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BEU` writer - Bit Error Uncorrected"] +pub struct BEU_W<'a> { + w: &'a mut W, +} +impl<'a> BEU_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `ELO` reader - Error Logging Overflow"] +pub struct ELO_R(crate::FieldReader); +impl ELO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ELO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ELO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ELO` writer - Error Logging Overflow"] +pub struct ELO_W<'a> { + w: &'a mut W, +} +impl<'a> ELO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `EP` reader - Error Passive"] +pub struct EP_R(crate::FieldReader); +impl EP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EP` writer - Error Passive"] +pub struct EP_W<'a> { + w: &'a mut W, +} +impl<'a> EP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `EW` reader - Warning Status"] +pub struct EW_R(crate::FieldReader); +impl EW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EW` writer - Warning Status"] +pub struct EW_W<'a> { + w: &'a mut W, +} +impl<'a> EW_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `BO` reader - Bus_Off Status"] +pub struct BO_R(crate::FieldReader); +impl BO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BO` writer - Bus_Off Status"] +pub struct BO_W<'a> { + w: &'a mut W, +} +impl<'a> BO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `WDI` reader - Watchdog Interrupt"] +pub struct WDI_R(crate::FieldReader); +impl WDI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WDI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WDI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WDI` writer - Watchdog Interrupt"] +pub struct WDI_W<'a> { + w: &'a mut W, +} +impl<'a> WDI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `PEA` reader - Protocol Error in Arbitration Phase"] +pub struct PEA_R(crate::FieldReader); +impl PEA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEA` writer - Protocol Error in Arbitration Phase"] +pub struct PEA_W<'a> { + w: &'a mut W, +} +impl<'a> PEA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +#[doc = "Field `PED` reader - Protocol Error in Data Phase"] +pub struct PED_R(crate::FieldReader); +impl PED_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PED_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PED` writer - Protocol Error in Data Phase"] +pub struct PED_W<'a> { + w: &'a mut W, +} +impl<'a> PED_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Field `ARA` reader - Access to Reserved Address"] +pub struct ARA_R(crate::FieldReader); +impl ARA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ARA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ARA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ARA` writer - Access to Reserved Address"] +pub struct ARA_W<'a> { + w: &'a mut W, +} +impl<'a> ARA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29); + self.w + } +} +impl R { + #[doc = "Bit 0 - Rx FIFO 0 New Message"] + #[inline(always)] + pub fn rf0n(&self) -> RF0N_R { + RF0N_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Rx FIFO 0 Watermark Reached"] + #[inline(always)] + pub fn rf0w(&self) -> RF0W_R { + RF0W_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Rx FIFO 0 Full"] + #[inline(always)] + pub fn rf0f(&self) -> RF0F_R { + RF0F_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Rx FIFO 0 Message Lost"] + #[inline(always)] + pub fn rf0l(&self) -> RF0L_R { + RF0L_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Rx FIFO 1 New Message"] + #[inline(always)] + pub fn rf1n(&self) -> RF1N_R { + RF1N_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Rx FIFO 1 Watermark Reached"] + #[inline(always)] + pub fn rf1w(&self) -> RF1W_R { + RF1W_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Rx FIFO 1 FIFO Full"] + #[inline(always)] + pub fn rf1f(&self) -> RF1F_R { + RF1F_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Rx FIFO 1 Message Lost"] + #[inline(always)] + pub fn rf1l(&self) -> RF1L_R { + RF1L_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - High Priority Message"] + #[inline(always)] + pub fn hpm(&self) -> HPM_R { + HPM_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Timestamp Completed"] + #[inline(always)] + pub fn tc(&self) -> TC_R { + TC_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Transmission Cancellation Finished"] + #[inline(always)] + pub fn tcf(&self) -> TCF_R { + TCF_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Tx FIFO Empty"] + #[inline(always)] + pub fn tfe(&self) -> TFE_R { + TFE_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Tx Event FIFO New Entry"] + #[inline(always)] + pub fn tefn(&self) -> TEFN_R { + TEFN_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Tx Event FIFO Watermark Reached"] + #[inline(always)] + pub fn tefw(&self) -> TEFW_R { + TEFW_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Tx Event FIFO Full"] + #[inline(always)] + pub fn teff(&self) -> TEFF_R { + TEFF_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Tx Event FIFO Element Lost"] + #[inline(always)] + pub fn tefl(&self) -> TEFL_R { + TEFL_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Timestamp Wraparound"] + #[inline(always)] + pub fn tsw(&self) -> TSW_R { + TSW_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Message RAM Access Failure"] + #[inline(always)] + pub fn mraf(&self) -> MRAF_R { + MRAF_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Timeout Occurred"] + #[inline(always)] + pub fn too(&self) -> TOO_R { + TOO_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Message stored to Dedicated Rx Buffer"] + #[inline(always)] + pub fn drx(&self) -> DRX_R { + DRX_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Bit Error Corrected"] + #[inline(always)] + pub fn bec(&self) -> BEC_R { + BEC_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Bit Error Uncorrected"] + #[inline(always)] + pub fn beu(&self) -> BEU_R { + BEU_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Error Logging Overflow"] + #[inline(always)] + pub fn elo(&self) -> ELO_R { + ELO_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Error Passive"] + #[inline(always)] + pub fn ep(&self) -> EP_R { + EP_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24 - Warning Status"] + #[inline(always)] + pub fn ew(&self) -> EW_R { + EW_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Bus_Off Status"] + #[inline(always)] + pub fn bo(&self) -> BO_R { + BO_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Watchdog Interrupt"] + #[inline(always)] + pub fn wdi(&self) -> WDI_R { + WDI_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Protocol Error in Arbitration Phase"] + #[inline(always)] + pub fn pea(&self) -> PEA_R { + PEA_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28 - Protocol Error in Data Phase"] + #[inline(always)] + pub fn ped(&self) -> PED_R { + PED_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Access to Reserved Address"] + #[inline(always)] + pub fn ara(&self) -> ARA_R { + ARA_R::new(((self.bits >> 29) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Rx FIFO 0 New Message"] + #[inline(always)] + pub fn rf0n(&mut self) -> RF0N_W { + RF0N_W { w: self } + } + #[doc = "Bit 1 - Rx FIFO 0 Watermark Reached"] + #[inline(always)] + pub fn rf0w(&mut self) -> RF0W_W { + RF0W_W { w: self } + } + #[doc = "Bit 2 - Rx FIFO 0 Full"] + #[inline(always)] + pub fn rf0f(&mut self) -> RF0F_W { + RF0F_W { w: self } + } + #[doc = "Bit 3 - Rx FIFO 0 Message Lost"] + #[inline(always)] + pub fn rf0l(&mut self) -> RF0L_W { + RF0L_W { w: self } + } + #[doc = "Bit 4 - Rx FIFO 1 New Message"] + #[inline(always)] + pub fn rf1n(&mut self) -> RF1N_W { + RF1N_W { w: self } + } + #[doc = "Bit 5 - Rx FIFO 1 Watermark Reached"] + #[inline(always)] + pub fn rf1w(&mut self) -> RF1W_W { + RF1W_W { w: self } + } + #[doc = "Bit 6 - Rx FIFO 1 FIFO Full"] + #[inline(always)] + pub fn rf1f(&mut self) -> RF1F_W { + RF1F_W { w: self } + } + #[doc = "Bit 7 - Rx FIFO 1 Message Lost"] + #[inline(always)] + pub fn rf1l(&mut self) -> RF1L_W { + RF1L_W { w: self } + } + #[doc = "Bit 8 - High Priority Message"] + #[inline(always)] + pub fn hpm(&mut self) -> HPM_W { + HPM_W { w: self } + } + #[doc = "Bit 9 - Timestamp Completed"] + #[inline(always)] + pub fn tc(&mut self) -> TC_W { + TC_W { w: self } + } + #[doc = "Bit 10 - Transmission Cancellation Finished"] + #[inline(always)] + pub fn tcf(&mut self) -> TCF_W { + TCF_W { w: self } + } + #[doc = "Bit 11 - Tx FIFO Empty"] + #[inline(always)] + pub fn tfe(&mut self) -> TFE_W { + TFE_W { w: self } + } + #[doc = "Bit 12 - Tx Event FIFO New Entry"] + #[inline(always)] + pub fn tefn(&mut self) -> TEFN_W { + TEFN_W { w: self } + } + #[doc = "Bit 13 - Tx Event FIFO Watermark Reached"] + #[inline(always)] + pub fn tefw(&mut self) -> TEFW_W { + TEFW_W { w: self } + } + #[doc = "Bit 14 - Tx Event FIFO Full"] + #[inline(always)] + pub fn teff(&mut self) -> TEFF_W { + TEFF_W { w: self } + } + #[doc = "Bit 15 - Tx Event FIFO Element Lost"] + #[inline(always)] + pub fn tefl(&mut self) -> TEFL_W { + TEFL_W { w: self } + } + #[doc = "Bit 16 - Timestamp Wraparound"] + #[inline(always)] + pub fn tsw(&mut self) -> TSW_W { + TSW_W { w: self } + } + #[doc = "Bit 17 - Message RAM Access Failure"] + #[inline(always)] + pub fn mraf(&mut self) -> MRAF_W { + MRAF_W { w: self } + } + #[doc = "Bit 18 - Timeout Occurred"] + #[inline(always)] + pub fn too(&mut self) -> TOO_W { + TOO_W { w: self } + } + #[doc = "Bit 19 - Message stored to Dedicated Rx Buffer"] + #[inline(always)] + pub fn drx(&mut self) -> DRX_W { + DRX_W { w: self } + } + #[doc = "Bit 20 - Bit Error Corrected"] + #[inline(always)] + pub fn bec(&mut self) -> BEC_W { + BEC_W { w: self } + } + #[doc = "Bit 21 - Bit Error Uncorrected"] + #[inline(always)] + pub fn beu(&mut self) -> BEU_W { + BEU_W { w: self } + } + #[doc = "Bit 22 - Error Logging Overflow"] + #[inline(always)] + pub fn elo(&mut self) -> ELO_W { + ELO_W { w: self } + } + #[doc = "Bit 23 - Error Passive"] + #[inline(always)] + pub fn ep(&mut self) -> EP_W { + EP_W { w: self } + } + #[doc = "Bit 24 - Warning Status"] + #[inline(always)] + pub fn ew(&mut self) -> EW_W { + EW_W { w: self } + } + #[doc = "Bit 25 - Bus_Off Status"] + #[inline(always)] + pub fn bo(&mut self) -> BO_W { + BO_W { w: self } + } + #[doc = "Bit 26 - Watchdog Interrupt"] + #[inline(always)] + pub fn wdi(&mut self) -> WDI_W { + WDI_W { w: self } + } + #[doc = "Bit 27 - Protocol Error in Arbitration Phase"] + #[inline(always)] + pub fn pea(&mut self) -> PEA_W { + PEA_W { w: self } + } + #[doc = "Bit 28 - Protocol Error in Data Phase"] + #[inline(always)] + pub fn ped(&mut self) -> PED_W { + PED_W { w: self } + } + #[doc = "Bit 29 - Access to Reserved Address"] + #[inline(always)] + pub fn ara(&mut self) -> ARA_W { + ARA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ir](index.html) module"] +pub struct IR_SPEC; +impl crate::RegisterSpec for IR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ir::R](R) reader structure"] +impl crate::Readable for IR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ir::W](W) writer structure"] +impl crate::Writable for IR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets IR to value 0"] +impl crate::Resettable for IR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/can0/mrcfg.rs b/pac/atsamc21e/src/can0/mrcfg.rs new file mode 100644 index 000000000000..7a4b25f0969a --- /dev/null +++ b/pac/atsamc21e/src/can0/mrcfg.rs @@ -0,0 +1,178 @@ +#[doc = "Register `MRCFG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MRCFG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Quality of Service\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum QOS_A { + #[doc = "0: Background (no sensitive operation)"] + DISABLE = 0, + #[doc = "1: Sensitive Bandwidth"] + LOW = 1, + #[doc = "2: Sensitive Latency"] + MEDIUM = 2, + #[doc = "3: Critical Latency"] + HIGH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: QOS_A) -> Self { + variant as _ + } +} +#[doc = "Field `QOS` reader - Quality of Service"] +pub struct QOS_R(crate::FieldReader); +impl QOS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + QOS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> QOS_A { + match self.bits { + 0 => QOS_A::DISABLE, + 1 => QOS_A::LOW, + 2 => QOS_A::MEDIUM, + 3 => QOS_A::HIGH, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == QOS_A::DISABLE + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == QOS_A::LOW + } + #[doc = "Checks if the value of the field is `MEDIUM`"] + #[inline(always)] + pub fn is_medium(&self) -> bool { + **self == QOS_A::MEDIUM + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == QOS_A::HIGH + } +} +impl core::ops::Deref for QOS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `QOS` writer - Quality of Service"] +pub struct QOS_W<'a> { + w: &'a mut W, +} +impl<'a> QOS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: QOS_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Background (no sensitive operation)"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(QOS_A::DISABLE) + } + #[doc = "Sensitive Bandwidth"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(QOS_A::LOW) + } + #[doc = "Sensitive Latency"] + #[inline(always)] + pub fn medium(self) -> &'a mut W { + self.variant(QOS_A::MEDIUM) + } + #[doc = "Critical Latency"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(QOS_A::HIGH) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u32 & 0x03); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Quality of Service"] + #[inline(always)] + pub fn qos(&self) -> QOS_R { + QOS_R::new((self.bits & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Quality of Service"] + #[inline(always)] + pub fn qos(&mut self) -> QOS_W { + QOS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Message RAM Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mrcfg](index.html) module"] +pub struct MRCFG_SPEC; +impl crate::RegisterSpec for MRCFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [mrcfg::R](R) reader structure"] +impl crate::Readable for MRCFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [mrcfg::W](W) writer structure"] +impl crate::Writable for MRCFG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets MRCFG to value 0x02"] +impl crate::Resettable for MRCFG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x02 + } +} diff --git a/pac/atsamc21e/src/can0/nbtp.rs b/pac/atsamc21e/src/can0/nbtp.rs new file mode 100644 index 000000000000..8de06d283b22 --- /dev/null +++ b/pac/atsamc21e/src/can0/nbtp.rs @@ -0,0 +1,214 @@ +#[doc = "Register `NBTP` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `NBTP` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `NTSEG2` reader - Nominal Time segment after sample point"] +pub struct NTSEG2_R(crate::FieldReader); +impl NTSEG2_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + NTSEG2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NTSEG2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NTSEG2` writer - Nominal Time segment after sample point"] +pub struct NTSEG2_W<'a> { + w: &'a mut W, +} +impl<'a> NTSEG2_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x7f) | (value as u32 & 0x7f); + self.w + } +} +#[doc = "Field `NTSEG1` reader - Nominal Time segment before sample point"] +pub struct NTSEG1_R(crate::FieldReader); +impl NTSEG1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + NTSEG1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NTSEG1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NTSEG1` writer - Nominal Time segment before sample point"] +pub struct NTSEG1_W<'a> { + w: &'a mut W, +} +impl<'a> NTSEG1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +#[doc = "Field `NBRP` reader - Nominal Baud Rate Prescaler"] +pub struct NBRP_R(crate::FieldReader); +impl NBRP_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + NBRP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NBRP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NBRP` writer - Nominal Baud Rate Prescaler"] +pub struct NBRP_W<'a> { + w: &'a mut W, +} +impl<'a> NBRP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01ff << 16)) | ((value as u32 & 0x01ff) << 16); + self.w + } +} +#[doc = "Field `NSJW` reader - Nominal (Re)Synchronization Jump Width"] +pub struct NSJW_R(crate::FieldReader); +impl NSJW_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + NSJW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NSJW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NSJW` writer - Nominal (Re)Synchronization Jump Width"] +pub struct NSJW_W<'a> { + w: &'a mut W, +} +impl<'a> NSJW_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x7f << 25)) | ((value as u32 & 0x7f) << 25); + self.w + } +} +impl R { + #[doc = "Bits 0:6 - Nominal Time segment after sample point"] + #[inline(always)] + pub fn ntseg2(&self) -> NTSEG2_R { + NTSEG2_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bits 8:15 - Nominal Time segment before sample point"] + #[inline(always)] + pub fn ntseg1(&self) -> NTSEG1_R { + NTSEG1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:24 - Nominal Baud Rate Prescaler"] + #[inline(always)] + pub fn nbrp(&self) -> NBRP_R { + NBRP_R::new(((self.bits >> 16) & 0x01ff) as u16) + } + #[doc = "Bits 25:31 - Nominal (Re)Synchronization Jump Width"] + #[inline(always)] + pub fn nsjw(&self) -> NSJW_R { + NSJW_R::new(((self.bits >> 25) & 0x7f) as u8) + } +} +impl W { + #[doc = "Bits 0:6 - Nominal Time segment after sample point"] + #[inline(always)] + pub fn ntseg2(&mut self) -> NTSEG2_W { + NTSEG2_W { w: self } + } + #[doc = "Bits 8:15 - Nominal Time segment before sample point"] + #[inline(always)] + pub fn ntseg1(&mut self) -> NTSEG1_W { + NTSEG1_W { w: self } + } + #[doc = "Bits 16:24 - Nominal Baud Rate Prescaler"] + #[inline(always)] + pub fn nbrp(&mut self) -> NBRP_W { + NBRP_W { w: self } + } + #[doc = "Bits 25:31 - Nominal (Re)Synchronization Jump Width"] + #[inline(always)] + pub fn nsjw(&mut self) -> NSJW_W { + NSJW_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Nominal Bit Timing and Prescaler\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [nbtp](index.html) module"] +pub struct NBTP_SPEC; +impl crate::RegisterSpec for NBTP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [nbtp::R](R) reader structure"] +impl crate::Readable for NBTP_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [nbtp::W](W) writer structure"] +impl crate::Writable for NBTP_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets NBTP to value 0x0600_0a03"] +impl crate::Resettable for NBTP_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0600_0a03 + } +} diff --git a/pac/atsamc21e/src/can0/ndat1.rs b/pac/atsamc21e/src/can0/ndat1.rs new file mode 100644 index 000000000000..63da465a27d8 --- /dev/null +++ b/pac/atsamc21e/src/can0/ndat1.rs @@ -0,0 +1,1570 @@ +#[doc = "Register `NDAT1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `NDAT1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ND0` reader - New Data 0"] +pub struct ND0_R(crate::FieldReader); +impl ND0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND0` writer - New Data 0"] +pub struct ND0_W<'a> { + w: &'a mut W, +} +impl<'a> ND0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ND1` reader - New Data 1"] +pub struct ND1_R(crate::FieldReader); +impl ND1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND1` writer - New Data 1"] +pub struct ND1_W<'a> { + w: &'a mut W, +} +impl<'a> ND1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ND2` reader - New Data 2"] +pub struct ND2_R(crate::FieldReader); +impl ND2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND2` writer - New Data 2"] +pub struct ND2_W<'a> { + w: &'a mut W, +} +impl<'a> ND2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `ND3` reader - New Data 3"] +pub struct ND3_R(crate::FieldReader); +impl ND3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND3` writer - New Data 3"] +pub struct ND3_W<'a> { + w: &'a mut W, +} +impl<'a> ND3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ND4` reader - New Data 4"] +pub struct ND4_R(crate::FieldReader); +impl ND4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND4` writer - New Data 4"] +pub struct ND4_W<'a> { + w: &'a mut W, +} +impl<'a> ND4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `ND5` reader - New Data 5"] +pub struct ND5_R(crate::FieldReader); +impl ND5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND5` writer - New Data 5"] +pub struct ND5_W<'a> { + w: &'a mut W, +} +impl<'a> ND5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `ND6` reader - New Data 6"] +pub struct ND6_R(crate::FieldReader); +impl ND6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND6` writer - New Data 6"] +pub struct ND6_W<'a> { + w: &'a mut W, +} +impl<'a> ND6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ND7` reader - New Data 7"] +pub struct ND7_R(crate::FieldReader); +impl ND7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND7` writer - New Data 7"] +pub struct ND7_W<'a> { + w: &'a mut W, +} +impl<'a> ND7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `ND8` reader - New Data 8"] +pub struct ND8_R(crate::FieldReader); +impl ND8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND8` writer - New Data 8"] +pub struct ND8_W<'a> { + w: &'a mut W, +} +impl<'a> ND8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `ND9` reader - New Data 9"] +pub struct ND9_R(crate::FieldReader); +impl ND9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND9` writer - New Data 9"] +pub struct ND9_W<'a> { + w: &'a mut W, +} +impl<'a> ND9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `ND10` reader - New Data 10"] +pub struct ND10_R(crate::FieldReader); +impl ND10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND10` writer - New Data 10"] +pub struct ND10_W<'a> { + w: &'a mut W, +} +impl<'a> ND10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `ND11` reader - New Data 11"] +pub struct ND11_R(crate::FieldReader); +impl ND11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND11` writer - New Data 11"] +pub struct ND11_W<'a> { + w: &'a mut W, +} +impl<'a> ND11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `ND12` reader - New Data 12"] +pub struct ND12_R(crate::FieldReader); +impl ND12_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND12_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND12_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND12` writer - New Data 12"] +pub struct ND12_W<'a> { + w: &'a mut W, +} +impl<'a> ND12_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `ND13` reader - New Data 13"] +pub struct ND13_R(crate::FieldReader); +impl ND13_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND13_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND13_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND13` writer - New Data 13"] +pub struct ND13_W<'a> { + w: &'a mut W, +} +impl<'a> ND13_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `ND14` reader - New Data 14"] +pub struct ND14_R(crate::FieldReader); +impl ND14_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND14_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND14_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND14` writer - New Data 14"] +pub struct ND14_W<'a> { + w: &'a mut W, +} +impl<'a> ND14_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `ND15` reader - New Data 15"] +pub struct ND15_R(crate::FieldReader); +impl ND15_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND15_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND15_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND15` writer - New Data 15"] +pub struct ND15_W<'a> { + w: &'a mut W, +} +impl<'a> ND15_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `ND16` reader - New Data 16"] +pub struct ND16_R(crate::FieldReader); +impl ND16_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND16_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND16_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND16` writer - New Data 16"] +pub struct ND16_W<'a> { + w: &'a mut W, +} +impl<'a> ND16_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `ND17` reader - New Data 17"] +pub struct ND17_R(crate::FieldReader); +impl ND17_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND17_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND17_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND17` writer - New Data 17"] +pub struct ND17_W<'a> { + w: &'a mut W, +} +impl<'a> ND17_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `ND18` reader - New Data 18"] +pub struct ND18_R(crate::FieldReader); +impl ND18_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND18_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND18_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND18` writer - New Data 18"] +pub struct ND18_W<'a> { + w: &'a mut W, +} +impl<'a> ND18_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `ND19` reader - New Data 19"] +pub struct ND19_R(crate::FieldReader); +impl ND19_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND19_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND19_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND19` writer - New Data 19"] +pub struct ND19_W<'a> { + w: &'a mut W, +} +impl<'a> ND19_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `ND20` reader - New Data 20"] +pub struct ND20_R(crate::FieldReader); +impl ND20_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND20_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND20_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND20` writer - New Data 20"] +pub struct ND20_W<'a> { + w: &'a mut W, +} +impl<'a> ND20_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `ND21` reader - New Data 21"] +pub struct ND21_R(crate::FieldReader); +impl ND21_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND21_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND21_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND21` writer - New Data 21"] +pub struct ND21_W<'a> { + w: &'a mut W, +} +impl<'a> ND21_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `ND22` reader - New Data 22"] +pub struct ND22_R(crate::FieldReader); +impl ND22_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND22_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND22_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND22` writer - New Data 22"] +pub struct ND22_W<'a> { + w: &'a mut W, +} +impl<'a> ND22_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `ND23` reader - New Data 23"] +pub struct ND23_R(crate::FieldReader); +impl ND23_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND23_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND23_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND23` writer - New Data 23"] +pub struct ND23_W<'a> { + w: &'a mut W, +} +impl<'a> ND23_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `ND24` reader - New Data 24"] +pub struct ND24_R(crate::FieldReader); +impl ND24_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND24_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND24_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND24` writer - New Data 24"] +pub struct ND24_W<'a> { + w: &'a mut W, +} +impl<'a> ND24_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `ND25` reader - New Data 25"] +pub struct ND25_R(crate::FieldReader); +impl ND25_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND25_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND25_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND25` writer - New Data 25"] +pub struct ND25_W<'a> { + w: &'a mut W, +} +impl<'a> ND25_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `ND26` reader - New Data 26"] +pub struct ND26_R(crate::FieldReader); +impl ND26_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND26_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND26_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND26` writer - New Data 26"] +pub struct ND26_W<'a> { + w: &'a mut W, +} +impl<'a> ND26_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `ND27` reader - New Data 27"] +pub struct ND27_R(crate::FieldReader); +impl ND27_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND27_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND27_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND27` writer - New Data 27"] +pub struct ND27_W<'a> { + w: &'a mut W, +} +impl<'a> ND27_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +#[doc = "Field `ND28` reader - New Data 28"] +pub struct ND28_R(crate::FieldReader); +impl ND28_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND28_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND28_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND28` writer - New Data 28"] +pub struct ND28_W<'a> { + w: &'a mut W, +} +impl<'a> ND28_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Field `ND29` reader - New Data 29"] +pub struct ND29_R(crate::FieldReader); +impl ND29_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND29_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND29_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND29` writer - New Data 29"] +pub struct ND29_W<'a> { + w: &'a mut W, +} +impl<'a> ND29_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29); + self.w + } +} +#[doc = "Field `ND30` reader - New Data 30"] +pub struct ND30_R(crate::FieldReader); +impl ND30_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND30_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND30_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND30` writer - New Data 30"] +pub struct ND30_W<'a> { + w: &'a mut W, +} +impl<'a> ND30_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +#[doc = "Field `ND31` reader - New Data 31"] +pub struct ND31_R(crate::FieldReader); +impl ND31_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND31_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND31_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND31` writer - New Data 31"] +pub struct ND31_W<'a> { + w: &'a mut W, +} +impl<'a> ND31_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bit 0 - New Data 0"] + #[inline(always)] + pub fn nd0(&self) -> ND0_R { + ND0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - New Data 1"] + #[inline(always)] + pub fn nd1(&self) -> ND1_R { + ND1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - New Data 2"] + #[inline(always)] + pub fn nd2(&self) -> ND2_R { + ND2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - New Data 3"] + #[inline(always)] + pub fn nd3(&self) -> ND3_R { + ND3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - New Data 4"] + #[inline(always)] + pub fn nd4(&self) -> ND4_R { + ND4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - New Data 5"] + #[inline(always)] + pub fn nd5(&self) -> ND5_R { + ND5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - New Data 6"] + #[inline(always)] + pub fn nd6(&self) -> ND6_R { + ND6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - New Data 7"] + #[inline(always)] + pub fn nd7(&self) -> ND7_R { + ND7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - New Data 8"] + #[inline(always)] + pub fn nd8(&self) -> ND8_R { + ND8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - New Data 9"] + #[inline(always)] + pub fn nd9(&self) -> ND9_R { + ND9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - New Data 10"] + #[inline(always)] + pub fn nd10(&self) -> ND10_R { + ND10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - New Data 11"] + #[inline(always)] + pub fn nd11(&self) -> ND11_R { + ND11_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - New Data 12"] + #[inline(always)] + pub fn nd12(&self) -> ND12_R { + ND12_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - New Data 13"] + #[inline(always)] + pub fn nd13(&self) -> ND13_R { + ND13_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - New Data 14"] + #[inline(always)] + pub fn nd14(&self) -> ND14_R { + ND14_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - New Data 15"] + #[inline(always)] + pub fn nd15(&self) -> ND15_R { + ND15_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - New Data 16"] + #[inline(always)] + pub fn nd16(&self) -> ND16_R { + ND16_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - New Data 17"] + #[inline(always)] + pub fn nd17(&self) -> ND17_R { + ND17_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - New Data 18"] + #[inline(always)] + pub fn nd18(&self) -> ND18_R { + ND18_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - New Data 19"] + #[inline(always)] + pub fn nd19(&self) -> ND19_R { + ND19_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - New Data 20"] + #[inline(always)] + pub fn nd20(&self) -> ND20_R { + ND20_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - New Data 21"] + #[inline(always)] + pub fn nd21(&self) -> ND21_R { + ND21_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - New Data 22"] + #[inline(always)] + pub fn nd22(&self) -> ND22_R { + ND22_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - New Data 23"] + #[inline(always)] + pub fn nd23(&self) -> ND23_R { + ND23_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24 - New Data 24"] + #[inline(always)] + pub fn nd24(&self) -> ND24_R { + ND24_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - New Data 25"] + #[inline(always)] + pub fn nd25(&self) -> ND25_R { + ND25_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - New Data 26"] + #[inline(always)] + pub fn nd26(&self) -> ND26_R { + ND26_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - New Data 27"] + #[inline(always)] + pub fn nd27(&self) -> ND27_R { + ND27_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28 - New Data 28"] + #[inline(always)] + pub fn nd28(&self) -> ND28_R { + ND28_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - New Data 29"] + #[inline(always)] + pub fn nd29(&self) -> ND29_R { + ND29_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - New Data 30"] + #[inline(always)] + pub fn nd30(&self) -> ND30_R { + ND30_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 31 - New Data 31"] + #[inline(always)] + pub fn nd31(&self) -> ND31_R { + ND31_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - New Data 0"] + #[inline(always)] + pub fn nd0(&mut self) -> ND0_W { + ND0_W { w: self } + } + #[doc = "Bit 1 - New Data 1"] + #[inline(always)] + pub fn nd1(&mut self) -> ND1_W { + ND1_W { w: self } + } + #[doc = "Bit 2 - New Data 2"] + #[inline(always)] + pub fn nd2(&mut self) -> ND2_W { + ND2_W { w: self } + } + #[doc = "Bit 3 - New Data 3"] + #[inline(always)] + pub fn nd3(&mut self) -> ND3_W { + ND3_W { w: self } + } + #[doc = "Bit 4 - New Data 4"] + #[inline(always)] + pub fn nd4(&mut self) -> ND4_W { + ND4_W { w: self } + } + #[doc = "Bit 5 - New Data 5"] + #[inline(always)] + pub fn nd5(&mut self) -> ND5_W { + ND5_W { w: self } + } + #[doc = "Bit 6 - New Data 6"] + #[inline(always)] + pub fn nd6(&mut self) -> ND6_W { + ND6_W { w: self } + } + #[doc = "Bit 7 - New Data 7"] + #[inline(always)] + pub fn nd7(&mut self) -> ND7_W { + ND7_W { w: self } + } + #[doc = "Bit 8 - New Data 8"] + #[inline(always)] + pub fn nd8(&mut self) -> ND8_W { + ND8_W { w: self } + } + #[doc = "Bit 9 - New Data 9"] + #[inline(always)] + pub fn nd9(&mut self) -> ND9_W { + ND9_W { w: self } + } + #[doc = "Bit 10 - New Data 10"] + #[inline(always)] + pub fn nd10(&mut self) -> ND10_W { + ND10_W { w: self } + } + #[doc = "Bit 11 - New Data 11"] + #[inline(always)] + pub fn nd11(&mut self) -> ND11_W { + ND11_W { w: self } + } + #[doc = "Bit 12 - New Data 12"] + #[inline(always)] + pub fn nd12(&mut self) -> ND12_W { + ND12_W { w: self } + } + #[doc = "Bit 13 - New Data 13"] + #[inline(always)] + pub fn nd13(&mut self) -> ND13_W { + ND13_W { w: self } + } + #[doc = "Bit 14 - New Data 14"] + #[inline(always)] + pub fn nd14(&mut self) -> ND14_W { + ND14_W { w: self } + } + #[doc = "Bit 15 - New Data 15"] + #[inline(always)] + pub fn nd15(&mut self) -> ND15_W { + ND15_W { w: self } + } + #[doc = "Bit 16 - New Data 16"] + #[inline(always)] + pub fn nd16(&mut self) -> ND16_W { + ND16_W { w: self } + } + #[doc = "Bit 17 - New Data 17"] + #[inline(always)] + pub fn nd17(&mut self) -> ND17_W { + ND17_W { w: self } + } + #[doc = "Bit 18 - New Data 18"] + #[inline(always)] + pub fn nd18(&mut self) -> ND18_W { + ND18_W { w: self } + } + #[doc = "Bit 19 - New Data 19"] + #[inline(always)] + pub fn nd19(&mut self) -> ND19_W { + ND19_W { w: self } + } + #[doc = "Bit 20 - New Data 20"] + #[inline(always)] + pub fn nd20(&mut self) -> ND20_W { + ND20_W { w: self } + } + #[doc = "Bit 21 - New Data 21"] + #[inline(always)] + pub fn nd21(&mut self) -> ND21_W { + ND21_W { w: self } + } + #[doc = "Bit 22 - New Data 22"] + #[inline(always)] + pub fn nd22(&mut self) -> ND22_W { + ND22_W { w: self } + } + #[doc = "Bit 23 - New Data 23"] + #[inline(always)] + pub fn nd23(&mut self) -> ND23_W { + ND23_W { w: self } + } + #[doc = "Bit 24 - New Data 24"] + #[inline(always)] + pub fn nd24(&mut self) -> ND24_W { + ND24_W { w: self } + } + #[doc = "Bit 25 - New Data 25"] + #[inline(always)] + pub fn nd25(&mut self) -> ND25_W { + ND25_W { w: self } + } + #[doc = "Bit 26 - New Data 26"] + #[inline(always)] + pub fn nd26(&mut self) -> ND26_W { + ND26_W { w: self } + } + #[doc = "Bit 27 - New Data 27"] + #[inline(always)] + pub fn nd27(&mut self) -> ND27_W { + ND27_W { w: self } + } + #[doc = "Bit 28 - New Data 28"] + #[inline(always)] + pub fn nd28(&mut self) -> ND28_W { + ND28_W { w: self } + } + #[doc = "Bit 29 - New Data 29"] + #[inline(always)] + pub fn nd29(&mut self) -> ND29_W { + ND29_W { w: self } + } + #[doc = "Bit 30 - New Data 30"] + #[inline(always)] + pub fn nd30(&mut self) -> ND30_W { + ND30_W { w: self } + } + #[doc = "Bit 31 - New Data 31"] + #[inline(always)] + pub fn nd31(&mut self) -> ND31_W { + ND31_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "New Data 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ndat1](index.html) module"] +pub struct NDAT1_SPEC; +impl crate::RegisterSpec for NDAT1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ndat1::R](R) reader structure"] +impl crate::Readable for NDAT1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ndat1::W](W) writer structure"] +impl crate::Writable for NDAT1_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets NDAT1 to value 0"] +impl crate::Resettable for NDAT1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/can0/ndat2.rs b/pac/atsamc21e/src/can0/ndat2.rs new file mode 100644 index 000000000000..ada8dac123fb --- /dev/null +++ b/pac/atsamc21e/src/can0/ndat2.rs @@ -0,0 +1,1570 @@ +#[doc = "Register `NDAT2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `NDAT2` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ND32` reader - New Data 32"] +pub struct ND32_R(crate::FieldReader); +impl ND32_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND32_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND32_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND32` writer - New Data 32"] +pub struct ND32_W<'a> { + w: &'a mut W, +} +impl<'a> ND32_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ND33` reader - New Data 33"] +pub struct ND33_R(crate::FieldReader); +impl ND33_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND33_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND33_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND33` writer - New Data 33"] +pub struct ND33_W<'a> { + w: &'a mut W, +} +impl<'a> ND33_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ND34` reader - New Data 34"] +pub struct ND34_R(crate::FieldReader); +impl ND34_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND34_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND34_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND34` writer - New Data 34"] +pub struct ND34_W<'a> { + w: &'a mut W, +} +impl<'a> ND34_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `ND35` reader - New Data 35"] +pub struct ND35_R(crate::FieldReader); +impl ND35_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND35_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND35_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND35` writer - New Data 35"] +pub struct ND35_W<'a> { + w: &'a mut W, +} +impl<'a> ND35_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ND36` reader - New Data 36"] +pub struct ND36_R(crate::FieldReader); +impl ND36_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND36_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND36_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND36` writer - New Data 36"] +pub struct ND36_W<'a> { + w: &'a mut W, +} +impl<'a> ND36_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `ND37` reader - New Data 37"] +pub struct ND37_R(crate::FieldReader); +impl ND37_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND37_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND37_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND37` writer - New Data 37"] +pub struct ND37_W<'a> { + w: &'a mut W, +} +impl<'a> ND37_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `ND38` reader - New Data 38"] +pub struct ND38_R(crate::FieldReader); +impl ND38_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND38_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND38_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND38` writer - New Data 38"] +pub struct ND38_W<'a> { + w: &'a mut W, +} +impl<'a> ND38_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ND39` reader - New Data 39"] +pub struct ND39_R(crate::FieldReader); +impl ND39_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND39_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND39_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND39` writer - New Data 39"] +pub struct ND39_W<'a> { + w: &'a mut W, +} +impl<'a> ND39_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `ND40` reader - New Data 40"] +pub struct ND40_R(crate::FieldReader); +impl ND40_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND40_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND40_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND40` writer - New Data 40"] +pub struct ND40_W<'a> { + w: &'a mut W, +} +impl<'a> ND40_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `ND41` reader - New Data 41"] +pub struct ND41_R(crate::FieldReader); +impl ND41_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND41_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND41_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND41` writer - New Data 41"] +pub struct ND41_W<'a> { + w: &'a mut W, +} +impl<'a> ND41_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `ND42` reader - New Data 42"] +pub struct ND42_R(crate::FieldReader); +impl ND42_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND42_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND42_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND42` writer - New Data 42"] +pub struct ND42_W<'a> { + w: &'a mut W, +} +impl<'a> ND42_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `ND43` reader - New Data 43"] +pub struct ND43_R(crate::FieldReader); +impl ND43_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND43_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND43_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND43` writer - New Data 43"] +pub struct ND43_W<'a> { + w: &'a mut W, +} +impl<'a> ND43_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `ND44` reader - New Data 44"] +pub struct ND44_R(crate::FieldReader); +impl ND44_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND44_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND44_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND44` writer - New Data 44"] +pub struct ND44_W<'a> { + w: &'a mut W, +} +impl<'a> ND44_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `ND45` reader - New Data 45"] +pub struct ND45_R(crate::FieldReader); +impl ND45_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND45_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND45_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND45` writer - New Data 45"] +pub struct ND45_W<'a> { + w: &'a mut W, +} +impl<'a> ND45_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `ND46` reader - New Data 46"] +pub struct ND46_R(crate::FieldReader); +impl ND46_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND46_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND46_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND46` writer - New Data 46"] +pub struct ND46_W<'a> { + w: &'a mut W, +} +impl<'a> ND46_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `ND47` reader - New Data 47"] +pub struct ND47_R(crate::FieldReader); +impl ND47_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND47_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND47_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND47` writer - New Data 47"] +pub struct ND47_W<'a> { + w: &'a mut W, +} +impl<'a> ND47_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `ND48` reader - New Data 48"] +pub struct ND48_R(crate::FieldReader); +impl ND48_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND48_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND48_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND48` writer - New Data 48"] +pub struct ND48_W<'a> { + w: &'a mut W, +} +impl<'a> ND48_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `ND49` reader - New Data 49"] +pub struct ND49_R(crate::FieldReader); +impl ND49_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND49_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND49_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND49` writer - New Data 49"] +pub struct ND49_W<'a> { + w: &'a mut W, +} +impl<'a> ND49_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `ND50` reader - New Data 50"] +pub struct ND50_R(crate::FieldReader); +impl ND50_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND50_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND50_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND50` writer - New Data 50"] +pub struct ND50_W<'a> { + w: &'a mut W, +} +impl<'a> ND50_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `ND51` reader - New Data 51"] +pub struct ND51_R(crate::FieldReader); +impl ND51_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND51_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND51_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND51` writer - New Data 51"] +pub struct ND51_W<'a> { + w: &'a mut W, +} +impl<'a> ND51_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `ND52` reader - New Data 52"] +pub struct ND52_R(crate::FieldReader); +impl ND52_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND52_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND52_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND52` writer - New Data 52"] +pub struct ND52_W<'a> { + w: &'a mut W, +} +impl<'a> ND52_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `ND53` reader - New Data 53"] +pub struct ND53_R(crate::FieldReader); +impl ND53_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND53_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND53_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND53` writer - New Data 53"] +pub struct ND53_W<'a> { + w: &'a mut W, +} +impl<'a> ND53_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `ND54` reader - New Data 54"] +pub struct ND54_R(crate::FieldReader); +impl ND54_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND54_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND54_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND54` writer - New Data 54"] +pub struct ND54_W<'a> { + w: &'a mut W, +} +impl<'a> ND54_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `ND55` reader - New Data 55"] +pub struct ND55_R(crate::FieldReader); +impl ND55_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND55_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND55_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND55` writer - New Data 55"] +pub struct ND55_W<'a> { + w: &'a mut W, +} +impl<'a> ND55_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `ND56` reader - New Data 56"] +pub struct ND56_R(crate::FieldReader); +impl ND56_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND56_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND56_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND56` writer - New Data 56"] +pub struct ND56_W<'a> { + w: &'a mut W, +} +impl<'a> ND56_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `ND57` reader - New Data 57"] +pub struct ND57_R(crate::FieldReader); +impl ND57_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND57_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND57_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND57` writer - New Data 57"] +pub struct ND57_W<'a> { + w: &'a mut W, +} +impl<'a> ND57_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `ND58` reader - New Data 58"] +pub struct ND58_R(crate::FieldReader); +impl ND58_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND58_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND58_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND58` writer - New Data 58"] +pub struct ND58_W<'a> { + w: &'a mut W, +} +impl<'a> ND58_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `ND59` reader - New Data 59"] +pub struct ND59_R(crate::FieldReader); +impl ND59_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND59_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND59_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND59` writer - New Data 59"] +pub struct ND59_W<'a> { + w: &'a mut W, +} +impl<'a> ND59_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +#[doc = "Field `ND60` reader - New Data 60"] +pub struct ND60_R(crate::FieldReader); +impl ND60_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND60_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND60_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND60` writer - New Data 60"] +pub struct ND60_W<'a> { + w: &'a mut W, +} +impl<'a> ND60_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Field `ND61` reader - New Data 61"] +pub struct ND61_R(crate::FieldReader); +impl ND61_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND61_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND61_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND61` writer - New Data 61"] +pub struct ND61_W<'a> { + w: &'a mut W, +} +impl<'a> ND61_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29); + self.w + } +} +#[doc = "Field `ND62` reader - New Data 62"] +pub struct ND62_R(crate::FieldReader); +impl ND62_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND62_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND62_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND62` writer - New Data 62"] +pub struct ND62_W<'a> { + w: &'a mut W, +} +impl<'a> ND62_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +#[doc = "Field `ND63` reader - New Data 63"] +pub struct ND63_R(crate::FieldReader); +impl ND63_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND63_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND63_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND63` writer - New Data 63"] +pub struct ND63_W<'a> { + w: &'a mut W, +} +impl<'a> ND63_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bit 0 - New Data 32"] + #[inline(always)] + pub fn nd32(&self) -> ND32_R { + ND32_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - New Data 33"] + #[inline(always)] + pub fn nd33(&self) -> ND33_R { + ND33_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - New Data 34"] + #[inline(always)] + pub fn nd34(&self) -> ND34_R { + ND34_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - New Data 35"] + #[inline(always)] + pub fn nd35(&self) -> ND35_R { + ND35_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - New Data 36"] + #[inline(always)] + pub fn nd36(&self) -> ND36_R { + ND36_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - New Data 37"] + #[inline(always)] + pub fn nd37(&self) -> ND37_R { + ND37_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - New Data 38"] + #[inline(always)] + pub fn nd38(&self) -> ND38_R { + ND38_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - New Data 39"] + #[inline(always)] + pub fn nd39(&self) -> ND39_R { + ND39_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - New Data 40"] + #[inline(always)] + pub fn nd40(&self) -> ND40_R { + ND40_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - New Data 41"] + #[inline(always)] + pub fn nd41(&self) -> ND41_R { + ND41_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - New Data 42"] + #[inline(always)] + pub fn nd42(&self) -> ND42_R { + ND42_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - New Data 43"] + #[inline(always)] + pub fn nd43(&self) -> ND43_R { + ND43_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - New Data 44"] + #[inline(always)] + pub fn nd44(&self) -> ND44_R { + ND44_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - New Data 45"] + #[inline(always)] + pub fn nd45(&self) -> ND45_R { + ND45_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - New Data 46"] + #[inline(always)] + pub fn nd46(&self) -> ND46_R { + ND46_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - New Data 47"] + #[inline(always)] + pub fn nd47(&self) -> ND47_R { + ND47_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - New Data 48"] + #[inline(always)] + pub fn nd48(&self) -> ND48_R { + ND48_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - New Data 49"] + #[inline(always)] + pub fn nd49(&self) -> ND49_R { + ND49_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - New Data 50"] + #[inline(always)] + pub fn nd50(&self) -> ND50_R { + ND50_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - New Data 51"] + #[inline(always)] + pub fn nd51(&self) -> ND51_R { + ND51_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - New Data 52"] + #[inline(always)] + pub fn nd52(&self) -> ND52_R { + ND52_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - New Data 53"] + #[inline(always)] + pub fn nd53(&self) -> ND53_R { + ND53_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - New Data 54"] + #[inline(always)] + pub fn nd54(&self) -> ND54_R { + ND54_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - New Data 55"] + #[inline(always)] + pub fn nd55(&self) -> ND55_R { + ND55_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24 - New Data 56"] + #[inline(always)] + pub fn nd56(&self) -> ND56_R { + ND56_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - New Data 57"] + #[inline(always)] + pub fn nd57(&self) -> ND57_R { + ND57_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - New Data 58"] + #[inline(always)] + pub fn nd58(&self) -> ND58_R { + ND58_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - New Data 59"] + #[inline(always)] + pub fn nd59(&self) -> ND59_R { + ND59_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28 - New Data 60"] + #[inline(always)] + pub fn nd60(&self) -> ND60_R { + ND60_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - New Data 61"] + #[inline(always)] + pub fn nd61(&self) -> ND61_R { + ND61_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - New Data 62"] + #[inline(always)] + pub fn nd62(&self) -> ND62_R { + ND62_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 31 - New Data 63"] + #[inline(always)] + pub fn nd63(&self) -> ND63_R { + ND63_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - New Data 32"] + #[inline(always)] + pub fn nd32(&mut self) -> ND32_W { + ND32_W { w: self } + } + #[doc = "Bit 1 - New Data 33"] + #[inline(always)] + pub fn nd33(&mut self) -> ND33_W { + ND33_W { w: self } + } + #[doc = "Bit 2 - New Data 34"] + #[inline(always)] + pub fn nd34(&mut self) -> ND34_W { + ND34_W { w: self } + } + #[doc = "Bit 3 - New Data 35"] + #[inline(always)] + pub fn nd35(&mut self) -> ND35_W { + ND35_W { w: self } + } + #[doc = "Bit 4 - New Data 36"] + #[inline(always)] + pub fn nd36(&mut self) -> ND36_W { + ND36_W { w: self } + } + #[doc = "Bit 5 - New Data 37"] + #[inline(always)] + pub fn nd37(&mut self) -> ND37_W { + ND37_W { w: self } + } + #[doc = "Bit 6 - New Data 38"] + #[inline(always)] + pub fn nd38(&mut self) -> ND38_W { + ND38_W { w: self } + } + #[doc = "Bit 7 - New Data 39"] + #[inline(always)] + pub fn nd39(&mut self) -> ND39_W { + ND39_W { w: self } + } + #[doc = "Bit 8 - New Data 40"] + #[inline(always)] + pub fn nd40(&mut self) -> ND40_W { + ND40_W { w: self } + } + #[doc = "Bit 9 - New Data 41"] + #[inline(always)] + pub fn nd41(&mut self) -> ND41_W { + ND41_W { w: self } + } + #[doc = "Bit 10 - New Data 42"] + #[inline(always)] + pub fn nd42(&mut self) -> ND42_W { + ND42_W { w: self } + } + #[doc = "Bit 11 - New Data 43"] + #[inline(always)] + pub fn nd43(&mut self) -> ND43_W { + ND43_W { w: self } + } + #[doc = "Bit 12 - New Data 44"] + #[inline(always)] + pub fn nd44(&mut self) -> ND44_W { + ND44_W { w: self } + } + #[doc = "Bit 13 - New Data 45"] + #[inline(always)] + pub fn nd45(&mut self) -> ND45_W { + ND45_W { w: self } + } + #[doc = "Bit 14 - New Data 46"] + #[inline(always)] + pub fn nd46(&mut self) -> ND46_W { + ND46_W { w: self } + } + #[doc = "Bit 15 - New Data 47"] + #[inline(always)] + pub fn nd47(&mut self) -> ND47_W { + ND47_W { w: self } + } + #[doc = "Bit 16 - New Data 48"] + #[inline(always)] + pub fn nd48(&mut self) -> ND48_W { + ND48_W { w: self } + } + #[doc = "Bit 17 - New Data 49"] + #[inline(always)] + pub fn nd49(&mut self) -> ND49_W { + ND49_W { w: self } + } + #[doc = "Bit 18 - New Data 50"] + #[inline(always)] + pub fn nd50(&mut self) -> ND50_W { + ND50_W { w: self } + } + #[doc = "Bit 19 - New Data 51"] + #[inline(always)] + pub fn nd51(&mut self) -> ND51_W { + ND51_W { w: self } + } + #[doc = "Bit 20 - New Data 52"] + #[inline(always)] + pub fn nd52(&mut self) -> ND52_W { + ND52_W { w: self } + } + #[doc = "Bit 21 - New Data 53"] + #[inline(always)] + pub fn nd53(&mut self) -> ND53_W { + ND53_W { w: self } + } + #[doc = "Bit 22 - New Data 54"] + #[inline(always)] + pub fn nd54(&mut self) -> ND54_W { + ND54_W { w: self } + } + #[doc = "Bit 23 - New Data 55"] + #[inline(always)] + pub fn nd55(&mut self) -> ND55_W { + ND55_W { w: self } + } + #[doc = "Bit 24 - New Data 56"] + #[inline(always)] + pub fn nd56(&mut self) -> ND56_W { + ND56_W { w: self } + } + #[doc = "Bit 25 - New Data 57"] + #[inline(always)] + pub fn nd57(&mut self) -> ND57_W { + ND57_W { w: self } + } + #[doc = "Bit 26 - New Data 58"] + #[inline(always)] + pub fn nd58(&mut self) -> ND58_W { + ND58_W { w: self } + } + #[doc = "Bit 27 - New Data 59"] + #[inline(always)] + pub fn nd59(&mut self) -> ND59_W { + ND59_W { w: self } + } + #[doc = "Bit 28 - New Data 60"] + #[inline(always)] + pub fn nd60(&mut self) -> ND60_W { + ND60_W { w: self } + } + #[doc = "Bit 29 - New Data 61"] + #[inline(always)] + pub fn nd61(&mut self) -> ND61_W { + ND61_W { w: self } + } + #[doc = "Bit 30 - New Data 62"] + #[inline(always)] + pub fn nd62(&mut self) -> ND62_W { + ND62_W { w: self } + } + #[doc = "Bit 31 - New Data 63"] + #[inline(always)] + pub fn nd63(&mut self) -> ND63_W { + ND63_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "New Data 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ndat2](index.html) module"] +pub struct NDAT2_SPEC; +impl crate::RegisterSpec for NDAT2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ndat2::R](R) reader structure"] +impl crate::Readable for NDAT2_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ndat2::W](W) writer structure"] +impl crate::Writable for NDAT2_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets NDAT2 to value 0"] +impl crate::Resettable for NDAT2_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/can0/psr.rs b/pac/atsamc21e/src/can0/psr.rs new file mode 100644 index 000000000000..0b5f73b9413b --- /dev/null +++ b/pac/atsamc21e/src/can0/psr.rs @@ -0,0 +1,467 @@ +#[doc = "Register `PSR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Last Error Code\n\nValue on reset: 7"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum LEC_A { + #[doc = "0: No Error"] + NONE = 0, + #[doc = "1: Stuff Error"] + STUFF = 1, + #[doc = "2: Form Error"] + FORM = 2, + #[doc = "3: Ack Error"] + ACK = 3, + #[doc = "4: Bit1 Error"] + BIT1 = 4, + #[doc = "5: Bit0 Error"] + BIT0 = 5, + #[doc = "6: CRC Error"] + CRC = 6, + #[doc = "7: No Change"] + NC = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LEC_A) -> Self { + variant as _ + } +} +#[doc = "Field `LEC` reader - Last Error Code"] +pub struct LEC_R(crate::FieldReader); +impl LEC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LEC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> LEC_A { + match self.bits { + 0 => LEC_A::NONE, + 1 => LEC_A::STUFF, + 2 => LEC_A::FORM, + 3 => LEC_A::ACK, + 4 => LEC_A::BIT1, + 5 => LEC_A::BIT0, + 6 => LEC_A::CRC, + 7 => LEC_A::NC, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == LEC_A::NONE + } + #[doc = "Checks if the value of the field is `STUFF`"] + #[inline(always)] + pub fn is_stuff(&self) -> bool { + **self == LEC_A::STUFF + } + #[doc = "Checks if the value of the field is `FORM`"] + #[inline(always)] + pub fn is_form(&self) -> bool { + **self == LEC_A::FORM + } + #[doc = "Checks if the value of the field is `ACK`"] + #[inline(always)] + pub fn is_ack(&self) -> bool { + **self == LEC_A::ACK + } + #[doc = "Checks if the value of the field is `BIT1`"] + #[inline(always)] + pub fn is_bit1(&self) -> bool { + **self == LEC_A::BIT1 + } + #[doc = "Checks if the value of the field is `BIT0`"] + #[inline(always)] + pub fn is_bit0(&self) -> bool { + **self == LEC_A::BIT0 + } + #[doc = "Checks if the value of the field is `CRC`"] + #[inline(always)] + pub fn is_crc(&self) -> bool { + **self == LEC_A::CRC + } + #[doc = "Checks if the value of the field is `NC`"] + #[inline(always)] + pub fn is_nc(&self) -> bool { + **self == LEC_A::NC + } +} +impl core::ops::Deref for LEC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Activity\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum ACT_A { + #[doc = "0: Node is synchronizing on CAN communication"] + SYNC = 0, + #[doc = "1: Node is neither receiver nor transmitter"] + IDLE = 1, + #[doc = "2: Node is operating as receiver"] + RX = 2, + #[doc = "3: Node is operating as transmitter"] + TX = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: ACT_A) -> Self { + variant as _ + } +} +#[doc = "Field `ACT` reader - Activity"] +pub struct ACT_R(crate::FieldReader); +impl ACT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ACT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ACT_A { + match self.bits { + 0 => ACT_A::SYNC, + 1 => ACT_A::IDLE, + 2 => ACT_A::RX, + 3 => ACT_A::TX, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `SYNC`"] + #[inline(always)] + pub fn is_sync(&self) -> bool { + **self == ACT_A::SYNC + } + #[doc = "Checks if the value of the field is `IDLE`"] + #[inline(always)] + pub fn is_idle(&self) -> bool { + **self == ACT_A::IDLE + } + #[doc = "Checks if the value of the field is `RX`"] + #[inline(always)] + pub fn is_rx(&self) -> bool { + **self == ACT_A::RX + } + #[doc = "Checks if the value of the field is `TX`"] + #[inline(always)] + pub fn is_tx(&self) -> bool { + **self == ACT_A::TX + } +} +impl core::ops::Deref for ACT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EP` reader - Error Passive"] +pub struct EP_R(crate::FieldReader); +impl EP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EW` reader - Warning Status"] +pub struct EW_R(crate::FieldReader); +impl EW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BO` reader - Bus_Off Status"] +pub struct BO_R(crate::FieldReader); +impl BO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Data Phase Last Error Code\n\nValue on reset: 7"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DLEC_A { + #[doc = "0: No Error"] + NONE = 0, + #[doc = "1: Stuff Error"] + STUFF = 1, + #[doc = "2: Form Error"] + FORM = 2, + #[doc = "3: Ack Error"] + ACK = 3, + #[doc = "4: Bit1 Error"] + BIT1 = 4, + #[doc = "5: Bit0 Error"] + BIT0 = 5, + #[doc = "6: CRC Error"] + CRC = 6, + #[doc = "7: No Change"] + NC = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DLEC_A) -> Self { + variant as _ + } +} +#[doc = "Field `DLEC` reader - Data Phase Last Error Code"] +pub struct DLEC_R(crate::FieldReader); +impl DLEC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DLEC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DLEC_A { + match self.bits { + 0 => DLEC_A::NONE, + 1 => DLEC_A::STUFF, + 2 => DLEC_A::FORM, + 3 => DLEC_A::ACK, + 4 => DLEC_A::BIT1, + 5 => DLEC_A::BIT0, + 6 => DLEC_A::CRC, + 7 => DLEC_A::NC, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == DLEC_A::NONE + } + #[doc = "Checks if the value of the field is `STUFF`"] + #[inline(always)] + pub fn is_stuff(&self) -> bool { + **self == DLEC_A::STUFF + } + #[doc = "Checks if the value of the field is `FORM`"] + #[inline(always)] + pub fn is_form(&self) -> bool { + **self == DLEC_A::FORM + } + #[doc = "Checks if the value of the field is `ACK`"] + #[inline(always)] + pub fn is_ack(&self) -> bool { + **self == DLEC_A::ACK + } + #[doc = "Checks if the value of the field is `BIT1`"] + #[inline(always)] + pub fn is_bit1(&self) -> bool { + **self == DLEC_A::BIT1 + } + #[doc = "Checks if the value of the field is `BIT0`"] + #[inline(always)] + pub fn is_bit0(&self) -> bool { + **self == DLEC_A::BIT0 + } + #[doc = "Checks if the value of the field is `CRC`"] + #[inline(always)] + pub fn is_crc(&self) -> bool { + **self == DLEC_A::CRC + } + #[doc = "Checks if the value of the field is `NC`"] + #[inline(always)] + pub fn is_nc(&self) -> bool { + **self == DLEC_A::NC + } +} +impl core::ops::Deref for DLEC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESI` reader - ESI flag of last received CAN FD Message"] +pub struct RESI_R(crate::FieldReader); +impl RESI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RBRS` reader - BRS flag of last received CAN FD Message"] +pub struct RBRS_R(crate::FieldReader); +impl RBRS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RBRS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RBRS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RFDF` reader - Received a CAN FD Message"] +pub struct RFDF_R(crate::FieldReader); +impl RFDF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RFDF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RFDF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PXE` reader - Protocol Exception Event"] +pub struct PXE_R(crate::FieldReader); +impl PXE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PXE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PXE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TDCV` reader - Transmitter Delay Compensation Value"] +pub struct TDCV_R(crate::FieldReader); +impl TDCV_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TDCV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TDCV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:2 - Last Error Code"] + #[inline(always)] + pub fn lec(&self) -> LEC_R { + LEC_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bits 3:4 - Activity"] + #[inline(always)] + pub fn act(&self) -> ACT_R { + ACT_R::new(((self.bits >> 3) & 0x03) as u8) + } + #[doc = "Bit 5 - Error Passive"] + #[inline(always)] + pub fn ep(&self) -> EP_R { + EP_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Warning Status"] + #[inline(always)] + pub fn ew(&self) -> EW_R { + EW_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Bus_Off Status"] + #[inline(always)] + pub fn bo(&self) -> BO_R { + BO_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Data Phase Last Error Code"] + #[inline(always)] + pub fn dlec(&self) -> DLEC_R { + DLEC_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 11 - ESI flag of last received CAN FD Message"] + #[inline(always)] + pub fn resi(&self) -> RESI_R { + RESI_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - BRS flag of last received CAN FD Message"] + #[inline(always)] + pub fn rbrs(&self) -> RBRS_R { + RBRS_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Received a CAN FD Message"] + #[inline(always)] + pub fn rfdf(&self) -> RFDF_R { + RFDF_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Protocol Exception Event"] + #[inline(always)] + pub fn pxe(&self) -> PXE_R { + PXE_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bits 16:22 - Transmitter Delay Compensation Value"] + #[inline(always)] + pub fn tdcv(&self) -> TDCV_R { + TDCV_R::new(((self.bits >> 16) & 0x7f) as u8) + } +} +#[doc = "Protocol Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [psr](index.html) module"] +pub struct PSR_SPEC; +impl crate::RegisterSpec for PSR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [psr::R](R) reader structure"] +impl crate::Readable for PSR_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PSR to value 0x0707"] +impl crate::Resettable for PSR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0707 + } +} diff --git a/pac/atsamc21e/src/can0/rwd.rs b/pac/atsamc21e/src/can0/rwd.rs new file mode 100644 index 000000000000..88f5b86a33f2 --- /dev/null +++ b/pac/atsamc21e/src/can0/rwd.rs @@ -0,0 +1,140 @@ +#[doc = "Register `RWD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RWD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WDC` reader - Watchdog Configuration"] +pub struct WDC_R(crate::FieldReader); +impl WDC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WDC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WDC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WDC` writer - Watchdog Configuration"] +pub struct WDC_W<'a> { + w: &'a mut W, +} +impl<'a> WDC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +#[doc = "Field `WDV` reader - Watchdog Value"] +pub struct WDV_R(crate::FieldReader); +impl WDV_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WDV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WDV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WDV` writer - Watchdog Value"] +pub struct WDV_W<'a> { + w: &'a mut W, +} +impl<'a> WDV_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Watchdog Configuration"] + #[inline(always)] + pub fn wdc(&self) -> WDC_R { + WDC_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Watchdog Value"] + #[inline(always)] + pub fn wdv(&self) -> WDV_R { + WDV_R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Watchdog Configuration"] + #[inline(always)] + pub fn wdc(&mut self) -> WDC_W { + WDC_W { w: self } + } + #[doc = "Bits 8:15 - Watchdog Value"] + #[inline(always)] + pub fn wdv(&mut self) -> WDV_W { + WDV_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "RAM Watchdog\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rwd](index.html) module"] +pub struct RWD_SPEC; +impl crate::RegisterSpec for RWD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rwd::R](R) reader structure"] +impl crate::Readable for RWD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rwd::W](W) writer structure"] +impl crate::Writable for RWD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RWD to value 0"] +impl crate::Resettable for RWD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/can0/rxbc.rs b/pac/atsamc21e/src/can0/rxbc.rs new file mode 100644 index 000000000000..d320ea61f4c2 --- /dev/null +++ b/pac/atsamc21e/src/can0/rxbc.rs @@ -0,0 +1,103 @@ +#[doc = "Register `RXBC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RXBC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RBSA` reader - Rx Buffer Start Address"] +pub struct RBSA_R(crate::FieldReader); +impl RBSA_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + RBSA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RBSA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RBSA` writer - Rx Buffer Start Address"] +pub struct RBSA_W<'a> { + w: &'a mut W, +} +impl<'a> RBSA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Rx Buffer Start Address"] + #[inline(always)] + pub fn rbsa(&self) -> RBSA_R { + RBSA_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Rx Buffer Start Address"] + #[inline(always)] + pub fn rbsa(&mut self) -> RBSA_W { + RBSA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Rx Buffer Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxbc](index.html) module"] +pub struct RXBC_SPEC; +impl crate::RegisterSpec for RXBC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rxbc::R](R) reader structure"] +impl crate::Readable for RXBC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rxbc::W](W) writer structure"] +impl crate::Writable for RXBC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RXBC to value 0"] +impl crate::Resettable for RXBC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/can0/rxesc.rs b/pac/atsamc21e/src/can0/rxesc.rs new file mode 100644 index 000000000000..b0a972eaf1f0 --- /dev/null +++ b/pac/atsamc21e/src/can0/rxesc.rs @@ -0,0 +1,558 @@ +#[doc = "Register `RXESC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RXESC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Rx FIFO 0 Data Field Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum F0DS_A { + #[doc = "0: 8 byte data field"] + DATA8 = 0, + #[doc = "1: 12 byte data field"] + DATA12 = 1, + #[doc = "2: 16 byte data field"] + DATA16 = 2, + #[doc = "3: 20 byte data field"] + DATA20 = 3, + #[doc = "4: 24 byte data field"] + DATA24 = 4, + #[doc = "5: 32 byte data field"] + DATA32 = 5, + #[doc = "6: 48 byte data field"] + DATA48 = 6, + #[doc = "7: 64 byte data field"] + DATA64 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: F0DS_A) -> Self { + variant as _ + } +} +#[doc = "Field `F0DS` reader - Rx FIFO 0 Data Field Size"] +pub struct F0DS_R(crate::FieldReader); +impl F0DS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + F0DS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> F0DS_A { + match self.bits { + 0 => F0DS_A::DATA8, + 1 => F0DS_A::DATA12, + 2 => F0DS_A::DATA16, + 3 => F0DS_A::DATA20, + 4 => F0DS_A::DATA24, + 5 => F0DS_A::DATA32, + 6 => F0DS_A::DATA48, + 7 => F0DS_A::DATA64, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DATA8`"] + #[inline(always)] + pub fn is_data8(&self) -> bool { + **self == F0DS_A::DATA8 + } + #[doc = "Checks if the value of the field is `DATA12`"] + #[inline(always)] + pub fn is_data12(&self) -> bool { + **self == F0DS_A::DATA12 + } + #[doc = "Checks if the value of the field is `DATA16`"] + #[inline(always)] + pub fn is_data16(&self) -> bool { + **self == F0DS_A::DATA16 + } + #[doc = "Checks if the value of the field is `DATA20`"] + #[inline(always)] + pub fn is_data20(&self) -> bool { + **self == F0DS_A::DATA20 + } + #[doc = "Checks if the value of the field is `DATA24`"] + #[inline(always)] + pub fn is_data24(&self) -> bool { + **self == F0DS_A::DATA24 + } + #[doc = "Checks if the value of the field is `DATA32`"] + #[inline(always)] + pub fn is_data32(&self) -> bool { + **self == F0DS_A::DATA32 + } + #[doc = "Checks if the value of the field is `DATA48`"] + #[inline(always)] + pub fn is_data48(&self) -> bool { + **self == F0DS_A::DATA48 + } + #[doc = "Checks if the value of the field is `DATA64`"] + #[inline(always)] + pub fn is_data64(&self) -> bool { + **self == F0DS_A::DATA64 + } +} +impl core::ops::Deref for F0DS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `F0DS` writer - Rx FIFO 0 Data Field Size"] +pub struct F0DS_W<'a> { + w: &'a mut W, +} +impl<'a> F0DS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: F0DS_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "8 byte data field"] + #[inline(always)] + pub fn data8(self) -> &'a mut W { + self.variant(F0DS_A::DATA8) + } + #[doc = "12 byte data field"] + #[inline(always)] + pub fn data12(self) -> &'a mut W { + self.variant(F0DS_A::DATA12) + } + #[doc = "16 byte data field"] + #[inline(always)] + pub fn data16(self) -> &'a mut W { + self.variant(F0DS_A::DATA16) + } + #[doc = "20 byte data field"] + #[inline(always)] + pub fn data20(self) -> &'a mut W { + self.variant(F0DS_A::DATA20) + } + #[doc = "24 byte data field"] + #[inline(always)] + pub fn data24(self) -> &'a mut W { + self.variant(F0DS_A::DATA24) + } + #[doc = "32 byte data field"] + #[inline(always)] + pub fn data32(self) -> &'a mut W { + self.variant(F0DS_A::DATA32) + } + #[doc = "48 byte data field"] + #[inline(always)] + pub fn data48(self) -> &'a mut W { + self.variant(F0DS_A::DATA48) + } + #[doc = "64 byte data field"] + #[inline(always)] + pub fn data64(self) -> &'a mut W { + self.variant(F0DS_A::DATA64) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Rx FIFO 1 Data Field Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum F1DS_A { + #[doc = "0: 8 byte data field"] + DATA8 = 0, + #[doc = "1: 12 byte data field"] + DATA12 = 1, + #[doc = "2: 16 byte data field"] + DATA16 = 2, + #[doc = "3: 20 byte data field"] + DATA20 = 3, + #[doc = "4: 24 byte data field"] + DATA24 = 4, + #[doc = "5: 32 byte data field"] + DATA32 = 5, + #[doc = "6: 48 byte data field"] + DATA48 = 6, + #[doc = "7: 64 byte data field"] + DATA64 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: F1DS_A) -> Self { + variant as _ + } +} +#[doc = "Field `F1DS` reader - Rx FIFO 1 Data Field Size"] +pub struct F1DS_R(crate::FieldReader); +impl F1DS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + F1DS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> F1DS_A { + match self.bits { + 0 => F1DS_A::DATA8, + 1 => F1DS_A::DATA12, + 2 => F1DS_A::DATA16, + 3 => F1DS_A::DATA20, + 4 => F1DS_A::DATA24, + 5 => F1DS_A::DATA32, + 6 => F1DS_A::DATA48, + 7 => F1DS_A::DATA64, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DATA8`"] + #[inline(always)] + pub fn is_data8(&self) -> bool { + **self == F1DS_A::DATA8 + } + #[doc = "Checks if the value of the field is `DATA12`"] + #[inline(always)] + pub fn is_data12(&self) -> bool { + **self == F1DS_A::DATA12 + } + #[doc = "Checks if the value of the field is `DATA16`"] + #[inline(always)] + pub fn is_data16(&self) -> bool { + **self == F1DS_A::DATA16 + } + #[doc = "Checks if the value of the field is `DATA20`"] + #[inline(always)] + pub fn is_data20(&self) -> bool { + **self == F1DS_A::DATA20 + } + #[doc = "Checks if the value of the field is `DATA24`"] + #[inline(always)] + pub fn is_data24(&self) -> bool { + **self == F1DS_A::DATA24 + } + #[doc = "Checks if the value of the field is `DATA32`"] + #[inline(always)] + pub fn is_data32(&self) -> bool { + **self == F1DS_A::DATA32 + } + #[doc = "Checks if the value of the field is `DATA48`"] + #[inline(always)] + pub fn is_data48(&self) -> bool { + **self == F1DS_A::DATA48 + } + #[doc = "Checks if the value of the field is `DATA64`"] + #[inline(always)] + pub fn is_data64(&self) -> bool { + **self == F1DS_A::DATA64 + } +} +impl core::ops::Deref for F1DS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `F1DS` writer - Rx FIFO 1 Data Field Size"] +pub struct F1DS_W<'a> { + w: &'a mut W, +} +impl<'a> F1DS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: F1DS_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "8 byte data field"] + #[inline(always)] + pub fn data8(self) -> &'a mut W { + self.variant(F1DS_A::DATA8) + } + #[doc = "12 byte data field"] + #[inline(always)] + pub fn data12(self) -> &'a mut W { + self.variant(F1DS_A::DATA12) + } + #[doc = "16 byte data field"] + #[inline(always)] + pub fn data16(self) -> &'a mut W { + self.variant(F1DS_A::DATA16) + } + #[doc = "20 byte data field"] + #[inline(always)] + pub fn data20(self) -> &'a mut W { + self.variant(F1DS_A::DATA20) + } + #[doc = "24 byte data field"] + #[inline(always)] + pub fn data24(self) -> &'a mut W { + self.variant(F1DS_A::DATA24) + } + #[doc = "32 byte data field"] + #[inline(always)] + pub fn data32(self) -> &'a mut W { + self.variant(F1DS_A::DATA32) + } + #[doc = "48 byte data field"] + #[inline(always)] + pub fn data48(self) -> &'a mut W { + self.variant(F1DS_A::DATA48) + } + #[doc = "64 byte data field"] + #[inline(always)] + pub fn data64(self) -> &'a mut W { + self.variant(F1DS_A::DATA64) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 4)) | ((value as u32 & 0x07) << 4); + self.w + } +} +#[doc = "Rx Buffer Data Field Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum RBDS_A { + #[doc = "0: 8 byte data field"] + DATA8 = 0, + #[doc = "1: 12 byte data field"] + DATA12 = 1, + #[doc = "2: 16 byte data field"] + DATA16 = 2, + #[doc = "3: 20 byte data field"] + DATA20 = 3, + #[doc = "4: 24 byte data field"] + DATA24 = 4, + #[doc = "5: 32 byte data field"] + DATA32 = 5, + #[doc = "6: 48 byte data field"] + DATA48 = 6, + #[doc = "7: 64 byte data field"] + DATA64 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RBDS_A) -> Self { + variant as _ + } +} +#[doc = "Field `RBDS` reader - Rx Buffer Data Field Size"] +pub struct RBDS_R(crate::FieldReader); +impl RBDS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RBDS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RBDS_A { + match self.bits { + 0 => RBDS_A::DATA8, + 1 => RBDS_A::DATA12, + 2 => RBDS_A::DATA16, + 3 => RBDS_A::DATA20, + 4 => RBDS_A::DATA24, + 5 => RBDS_A::DATA32, + 6 => RBDS_A::DATA48, + 7 => RBDS_A::DATA64, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DATA8`"] + #[inline(always)] + pub fn is_data8(&self) -> bool { + **self == RBDS_A::DATA8 + } + #[doc = "Checks if the value of the field is `DATA12`"] + #[inline(always)] + pub fn is_data12(&self) -> bool { + **self == RBDS_A::DATA12 + } + #[doc = "Checks if the value of the field is `DATA16`"] + #[inline(always)] + pub fn is_data16(&self) -> bool { + **self == RBDS_A::DATA16 + } + #[doc = "Checks if the value of the field is `DATA20`"] + #[inline(always)] + pub fn is_data20(&self) -> bool { + **self == RBDS_A::DATA20 + } + #[doc = "Checks if the value of the field is `DATA24`"] + #[inline(always)] + pub fn is_data24(&self) -> bool { + **self == RBDS_A::DATA24 + } + #[doc = "Checks if the value of the field is `DATA32`"] + #[inline(always)] + pub fn is_data32(&self) -> bool { + **self == RBDS_A::DATA32 + } + #[doc = "Checks if the value of the field is `DATA48`"] + #[inline(always)] + pub fn is_data48(&self) -> bool { + **self == RBDS_A::DATA48 + } + #[doc = "Checks if the value of the field is `DATA64`"] + #[inline(always)] + pub fn is_data64(&self) -> bool { + **self == RBDS_A::DATA64 + } +} +impl core::ops::Deref for RBDS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RBDS` writer - Rx Buffer Data Field Size"] +pub struct RBDS_W<'a> { + w: &'a mut W, +} +impl<'a> RBDS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RBDS_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "8 byte data field"] + #[inline(always)] + pub fn data8(self) -> &'a mut W { + self.variant(RBDS_A::DATA8) + } + #[doc = "12 byte data field"] + #[inline(always)] + pub fn data12(self) -> &'a mut W { + self.variant(RBDS_A::DATA12) + } + #[doc = "16 byte data field"] + #[inline(always)] + pub fn data16(self) -> &'a mut W { + self.variant(RBDS_A::DATA16) + } + #[doc = "20 byte data field"] + #[inline(always)] + pub fn data20(self) -> &'a mut W { + self.variant(RBDS_A::DATA20) + } + #[doc = "24 byte data field"] + #[inline(always)] + pub fn data24(self) -> &'a mut W { + self.variant(RBDS_A::DATA24) + } + #[doc = "32 byte data field"] + #[inline(always)] + pub fn data32(self) -> &'a mut W { + self.variant(RBDS_A::DATA32) + } + #[doc = "48 byte data field"] + #[inline(always)] + pub fn data48(self) -> &'a mut W { + self.variant(RBDS_A::DATA48) + } + #[doc = "64 byte data field"] + #[inline(always)] + pub fn data64(self) -> &'a mut W { + self.variant(RBDS_A::DATA64) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Rx FIFO 0 Data Field Size"] + #[inline(always)] + pub fn f0ds(&self) -> F0DS_R { + F0DS_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bits 4:6 - Rx FIFO 1 Data Field Size"] + #[inline(always)] + pub fn f1ds(&self) -> F1DS_R { + F1DS_R::new(((self.bits >> 4) & 0x07) as u8) + } + #[doc = "Bits 8:10 - Rx Buffer Data Field Size"] + #[inline(always)] + pub fn rbds(&self) -> RBDS_R { + RBDS_R::new(((self.bits >> 8) & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Rx FIFO 0 Data Field Size"] + #[inline(always)] + pub fn f0ds(&mut self) -> F0DS_W { + F0DS_W { w: self } + } + #[doc = "Bits 4:6 - Rx FIFO 1 Data Field Size"] + #[inline(always)] + pub fn f1ds(&mut self) -> F1DS_W { + F1DS_W { w: self } + } + #[doc = "Bits 8:10 - Rx Buffer Data Field Size"] + #[inline(always)] + pub fn rbds(&mut self) -> RBDS_W { + RBDS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Rx Buffer / FIFO Element Size Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxesc](index.html) module"] +pub struct RXESC_SPEC; +impl crate::RegisterSpec for RXESC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rxesc::R](R) reader structure"] +impl crate::Readable for RXESC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rxesc::W](W) writer structure"] +impl crate::Writable for RXESC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RXESC to value 0"] +impl crate::Resettable for RXESC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/can0/rxf0a.rs b/pac/atsamc21e/src/can0/rxf0a.rs new file mode 100644 index 000000000000..568144edf95d --- /dev/null +++ b/pac/atsamc21e/src/can0/rxf0a.rs @@ -0,0 +1,103 @@ +#[doc = "Register `RXF0A` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RXF0A` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `F0AI` reader - Rx FIFO 0 Acknowledge Index"] +pub struct F0AI_R(crate::FieldReader); +impl F0AI_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + F0AI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for F0AI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `F0AI` writer - Rx FIFO 0 Acknowledge Index"] +pub struct F0AI_W<'a> { + w: &'a mut W, +} +impl<'a> F0AI_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Rx FIFO 0 Acknowledge Index"] + #[inline(always)] + pub fn f0ai(&self) -> F0AI_R { + F0AI_R::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - Rx FIFO 0 Acknowledge Index"] + #[inline(always)] + pub fn f0ai(&mut self) -> F0AI_W { + F0AI_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Rx FIFO 0 Acknowledge\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxf0a](index.html) module"] +pub struct RXF0A_SPEC; +impl crate::RegisterSpec for RXF0A_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rxf0a::R](R) reader structure"] +impl crate::Readable for RXF0A_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rxf0a::W](W) writer structure"] +impl crate::Writable for RXF0A_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RXF0A to value 0"] +impl crate::Resettable for RXF0A_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/can0/rxf0c.rs b/pac/atsamc21e/src/can0/rxf0c.rs new file mode 100644 index 000000000000..a1e1def5881a --- /dev/null +++ b/pac/atsamc21e/src/can0/rxf0c.rs @@ -0,0 +1,224 @@ +#[doc = "Register `RXF0C` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RXF0C` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `F0SA` reader - Rx FIFO 0 Start Address"] +pub struct F0SA_R(crate::FieldReader); +impl F0SA_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + F0SA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for F0SA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `F0SA` writer - Rx FIFO 0 Start Address"] +pub struct F0SA_W<'a> { + w: &'a mut W, +} +impl<'a> F0SA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +#[doc = "Field `F0S` reader - Rx FIFO 0 Size"] +pub struct F0S_R(crate::FieldReader); +impl F0S_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + F0S_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for F0S_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `F0S` writer - Rx FIFO 0 Size"] +pub struct F0S_W<'a> { + w: &'a mut W, +} +impl<'a> F0S_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x7f << 16)) | ((value as u32 & 0x7f) << 16); + self.w + } +} +#[doc = "Field `F0WM` reader - Rx FIFO 0 Watermark"] +pub struct F0WM_R(crate::FieldReader); +impl F0WM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + F0WM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for F0WM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `F0WM` writer - Rx FIFO 0 Watermark"] +pub struct F0WM_W<'a> { + w: &'a mut W, +} +impl<'a> F0WM_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x7f << 24)) | ((value as u32 & 0x7f) << 24); + self.w + } +} +#[doc = "Field `F0OM` reader - FIFO 0 Operation Mode"] +pub struct F0OM_R(crate::FieldReader); +impl F0OM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + F0OM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for F0OM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `F0OM` writer - FIFO 0 Operation Mode"] +pub struct F0OM_W<'a> { + w: &'a mut W, +} +impl<'a> F0OM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Rx FIFO 0 Start Address"] + #[inline(always)] + pub fn f0sa(&self) -> F0SA_R { + F0SA_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:22 - Rx FIFO 0 Size"] + #[inline(always)] + pub fn f0s(&self) -> F0S_R { + F0S_R::new(((self.bits >> 16) & 0x7f) as u8) + } + #[doc = "Bits 24:30 - Rx FIFO 0 Watermark"] + #[inline(always)] + pub fn f0wm(&self) -> F0WM_R { + F0WM_R::new(((self.bits >> 24) & 0x7f) as u8) + } + #[doc = "Bit 31 - FIFO 0 Operation Mode"] + #[inline(always)] + pub fn f0om(&self) -> F0OM_R { + F0OM_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Rx FIFO 0 Start Address"] + #[inline(always)] + pub fn f0sa(&mut self) -> F0SA_W { + F0SA_W { w: self } + } + #[doc = "Bits 16:22 - Rx FIFO 0 Size"] + #[inline(always)] + pub fn f0s(&mut self) -> F0S_W { + F0S_W { w: self } + } + #[doc = "Bits 24:30 - Rx FIFO 0 Watermark"] + #[inline(always)] + pub fn f0wm(&mut self) -> F0WM_W { + F0WM_W { w: self } + } + #[doc = "Bit 31 - FIFO 0 Operation Mode"] + #[inline(always)] + pub fn f0om(&mut self) -> F0OM_W { + F0OM_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Rx FIFO 0 Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxf0c](index.html) module"] +pub struct RXF0C_SPEC; +impl crate::RegisterSpec for RXF0C_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rxf0c::R](R) reader structure"] +impl crate::Readable for RXF0C_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rxf0c::W](W) writer structure"] +impl crate::Writable for RXF0C_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RXF0C to value 0"] +impl crate::Resettable for RXF0C_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/can0/rxf0s.rs b/pac/atsamc21e/src/can0/rxf0s.rs new file mode 100644 index 000000000000..c26ef5fed347 --- /dev/null +++ b/pac/atsamc21e/src/can0/rxf0s.rs @@ -0,0 +1,133 @@ +#[doc = "Register `RXF0S` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `F0FL` reader - Rx FIFO 0 Fill Level"] +pub struct F0FL_R(crate::FieldReader); +impl F0FL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + F0FL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for F0FL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `F0GI` reader - Rx FIFO 0 Get Index"] +pub struct F0GI_R(crate::FieldReader); +impl F0GI_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + F0GI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for F0GI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `F0PI` reader - Rx FIFO 0 Put Index"] +pub struct F0PI_R(crate::FieldReader); +impl F0PI_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + F0PI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for F0PI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `F0F` reader - Rx FIFO 0 Full"] +pub struct F0F_R(crate::FieldReader); +impl F0F_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + F0F_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for F0F_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF0L` reader - Rx FIFO 0 Message Lost"] +pub struct RF0L_R(crate::FieldReader); +impl RF0L_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF0L_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF0L_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:6 - Rx FIFO 0 Fill Level"] + #[inline(always)] + pub fn f0fl(&self) -> F0FL_R { + F0FL_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bits 8:13 - Rx FIFO 0 Get Index"] + #[inline(always)] + pub fn f0gi(&self) -> F0GI_R { + F0GI_R::new(((self.bits >> 8) & 0x3f) as u8) + } + #[doc = "Bits 16:21 - Rx FIFO 0 Put Index"] + #[inline(always)] + pub fn f0pi(&self) -> F0PI_R { + F0PI_R::new(((self.bits >> 16) & 0x3f) as u8) + } + #[doc = "Bit 24 - Rx FIFO 0 Full"] + #[inline(always)] + pub fn f0f(&self) -> F0F_R { + F0F_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Rx FIFO 0 Message Lost"] + #[inline(always)] + pub fn rf0l(&self) -> RF0L_R { + RF0L_R::new(((self.bits >> 25) & 0x01) != 0) + } +} +#[doc = "Rx FIFO 0 Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxf0s](index.html) module"] +pub struct RXF0S_SPEC; +impl crate::RegisterSpec for RXF0S_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rxf0s::R](R) reader structure"] +impl crate::Readable for RXF0S_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets RXF0S to value 0"] +impl crate::Resettable for RXF0S_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/can0/rxf1a.rs b/pac/atsamc21e/src/can0/rxf1a.rs new file mode 100644 index 000000000000..56b074f7f444 --- /dev/null +++ b/pac/atsamc21e/src/can0/rxf1a.rs @@ -0,0 +1,103 @@ +#[doc = "Register `RXF1A` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RXF1A` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `F1AI` reader - Rx FIFO 1 Acknowledge Index"] +pub struct F1AI_R(crate::FieldReader); +impl F1AI_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + F1AI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for F1AI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `F1AI` writer - Rx FIFO 1 Acknowledge Index"] +pub struct F1AI_W<'a> { + w: &'a mut W, +} +impl<'a> F1AI_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Rx FIFO 1 Acknowledge Index"] + #[inline(always)] + pub fn f1ai(&self) -> F1AI_R { + F1AI_R::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - Rx FIFO 1 Acknowledge Index"] + #[inline(always)] + pub fn f1ai(&mut self) -> F1AI_W { + F1AI_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Rx FIFO 1 Acknowledge\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxf1a](index.html) module"] +pub struct RXF1A_SPEC; +impl crate::RegisterSpec for RXF1A_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rxf1a::R](R) reader structure"] +impl crate::Readable for RXF1A_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rxf1a::W](W) writer structure"] +impl crate::Writable for RXF1A_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RXF1A to value 0"] +impl crate::Resettable for RXF1A_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/can0/rxf1c.rs b/pac/atsamc21e/src/can0/rxf1c.rs new file mode 100644 index 000000000000..c9e23925c0c8 --- /dev/null +++ b/pac/atsamc21e/src/can0/rxf1c.rs @@ -0,0 +1,224 @@ +#[doc = "Register `RXF1C` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RXF1C` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `F1SA` reader - Rx FIFO 1 Start Address"] +pub struct F1SA_R(crate::FieldReader); +impl F1SA_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + F1SA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for F1SA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `F1SA` writer - Rx FIFO 1 Start Address"] +pub struct F1SA_W<'a> { + w: &'a mut W, +} +impl<'a> F1SA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +#[doc = "Field `F1S` reader - Rx FIFO 1 Size"] +pub struct F1S_R(crate::FieldReader); +impl F1S_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + F1S_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for F1S_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `F1S` writer - Rx FIFO 1 Size"] +pub struct F1S_W<'a> { + w: &'a mut W, +} +impl<'a> F1S_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x7f << 16)) | ((value as u32 & 0x7f) << 16); + self.w + } +} +#[doc = "Field `F1WM` reader - Rx FIFO 1 Watermark"] +pub struct F1WM_R(crate::FieldReader); +impl F1WM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + F1WM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for F1WM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `F1WM` writer - Rx FIFO 1 Watermark"] +pub struct F1WM_W<'a> { + w: &'a mut W, +} +impl<'a> F1WM_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x7f << 24)) | ((value as u32 & 0x7f) << 24); + self.w + } +} +#[doc = "Field `F1OM` reader - FIFO 1 Operation Mode"] +pub struct F1OM_R(crate::FieldReader); +impl F1OM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + F1OM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for F1OM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `F1OM` writer - FIFO 1 Operation Mode"] +pub struct F1OM_W<'a> { + w: &'a mut W, +} +impl<'a> F1OM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Rx FIFO 1 Start Address"] + #[inline(always)] + pub fn f1sa(&self) -> F1SA_R { + F1SA_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:22 - Rx FIFO 1 Size"] + #[inline(always)] + pub fn f1s(&self) -> F1S_R { + F1S_R::new(((self.bits >> 16) & 0x7f) as u8) + } + #[doc = "Bits 24:30 - Rx FIFO 1 Watermark"] + #[inline(always)] + pub fn f1wm(&self) -> F1WM_R { + F1WM_R::new(((self.bits >> 24) & 0x7f) as u8) + } + #[doc = "Bit 31 - FIFO 1 Operation Mode"] + #[inline(always)] + pub fn f1om(&self) -> F1OM_R { + F1OM_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Rx FIFO 1 Start Address"] + #[inline(always)] + pub fn f1sa(&mut self) -> F1SA_W { + F1SA_W { w: self } + } + #[doc = "Bits 16:22 - Rx FIFO 1 Size"] + #[inline(always)] + pub fn f1s(&mut self) -> F1S_W { + F1S_W { w: self } + } + #[doc = "Bits 24:30 - Rx FIFO 1 Watermark"] + #[inline(always)] + pub fn f1wm(&mut self) -> F1WM_W { + F1WM_W { w: self } + } + #[doc = "Bit 31 - FIFO 1 Operation Mode"] + #[inline(always)] + pub fn f1om(&mut self) -> F1OM_W { + F1OM_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Rx FIFO 1 Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxf1c](index.html) module"] +pub struct RXF1C_SPEC; +impl crate::RegisterSpec for RXF1C_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rxf1c::R](R) reader structure"] +impl crate::Readable for RXF1C_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rxf1c::W](W) writer structure"] +impl crate::Writable for RXF1C_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RXF1C to value 0"] +impl crate::Resettable for RXF1C_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/can0/rxf1s.rs b/pac/atsamc21e/src/can0/rxf1s.rs new file mode 100644 index 000000000000..7005a3339afb --- /dev/null +++ b/pac/atsamc21e/src/can0/rxf1s.rs @@ -0,0 +1,203 @@ +#[doc = "Register `RXF1S` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `F1FL` reader - Rx FIFO 1 Fill Level"] +pub struct F1FL_R(crate::FieldReader); +impl F1FL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + F1FL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for F1FL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `F1GI` reader - Rx FIFO 1 Get Index"] +pub struct F1GI_R(crate::FieldReader); +impl F1GI_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + F1GI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for F1GI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `F1PI` reader - Rx FIFO 1 Put Index"] +pub struct F1PI_R(crate::FieldReader); +impl F1PI_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + F1PI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for F1PI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `F1F` reader - Rx FIFO 1 Full"] +pub struct F1F_R(crate::FieldReader); +impl F1F_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + F1F_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for F1F_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF1L` reader - Rx FIFO 1 Message Lost"] +pub struct RF1L_R(crate::FieldReader); +impl RF1L_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF1L_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF1L_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Debug Message Status\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DMS_A { + #[doc = "0: Idle state"] + IDLE = 0, + #[doc = "1: Debug message A received"] + DBGA = 1, + #[doc = "2: Debug message A/B received"] + DBGB = 2, + #[doc = "3: Debug message A/B/C received, DMA request set"] + DBGC = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DMS_A) -> Self { + variant as _ + } +} +#[doc = "Field `DMS` reader - Debug Message Status"] +pub struct DMS_R(crate::FieldReader); +impl DMS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DMS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DMS_A { + match self.bits { + 0 => DMS_A::IDLE, + 1 => DMS_A::DBGA, + 2 => DMS_A::DBGB, + 3 => DMS_A::DBGC, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `IDLE`"] + #[inline(always)] + pub fn is_idle(&self) -> bool { + **self == DMS_A::IDLE + } + #[doc = "Checks if the value of the field is `DBGA`"] + #[inline(always)] + pub fn is_dbga(&self) -> bool { + **self == DMS_A::DBGA + } + #[doc = "Checks if the value of the field is `DBGB`"] + #[inline(always)] + pub fn is_dbgb(&self) -> bool { + **self == DMS_A::DBGB + } + #[doc = "Checks if the value of the field is `DBGC`"] + #[inline(always)] + pub fn is_dbgc(&self) -> bool { + **self == DMS_A::DBGC + } +} +impl core::ops::Deref for DMS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:6 - Rx FIFO 1 Fill Level"] + #[inline(always)] + pub fn f1fl(&self) -> F1FL_R { + F1FL_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bits 8:13 - Rx FIFO 1 Get Index"] + #[inline(always)] + pub fn f1gi(&self) -> F1GI_R { + F1GI_R::new(((self.bits >> 8) & 0x3f) as u8) + } + #[doc = "Bits 16:21 - Rx FIFO 1 Put Index"] + #[inline(always)] + pub fn f1pi(&self) -> F1PI_R { + F1PI_R::new(((self.bits >> 16) & 0x3f) as u8) + } + #[doc = "Bit 24 - Rx FIFO 1 Full"] + #[inline(always)] + pub fn f1f(&self) -> F1F_R { + F1F_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Rx FIFO 1 Message Lost"] + #[inline(always)] + pub fn rf1l(&self) -> RF1L_R { + RF1L_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bits 30:31 - Debug Message Status"] + #[inline(always)] + pub fn dms(&self) -> DMS_R { + DMS_R::new(((self.bits >> 30) & 0x03) as u8) + } +} +#[doc = "Rx FIFO 1 Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxf1s](index.html) module"] +pub struct RXF1S_SPEC; +impl crate::RegisterSpec for RXF1S_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rxf1s::R](R) reader structure"] +impl crate::Readable for RXF1S_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets RXF1S to value 0"] +impl crate::Resettable for RXF1S_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/can0/sidfc.rs b/pac/atsamc21e/src/can0/sidfc.rs new file mode 100644 index 000000000000..95a73efe426a --- /dev/null +++ b/pac/atsamc21e/src/can0/sidfc.rs @@ -0,0 +1,140 @@ +#[doc = "Register `SIDFC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SIDFC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FLSSA` reader - Filter List Standard Start Address"] +pub struct FLSSA_R(crate::FieldReader); +impl FLSSA_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + FLSSA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FLSSA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLSSA` writer - Filter List Standard Start Address"] +pub struct FLSSA_W<'a> { + w: &'a mut W, +} +impl<'a> FLSSA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +#[doc = "Field `LSS` reader - List Size Standard"] +pub struct LSS_R(crate::FieldReader); +impl LSS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LSS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LSS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LSS` writer - List Size Standard"] +pub struct LSS_W<'a> { + w: &'a mut W, +} +impl<'a> LSS_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Filter List Standard Start Address"] + #[inline(always)] + pub fn flssa(&self) -> FLSSA_R { + FLSSA_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:23 - List Size Standard"] + #[inline(always)] + pub fn lss(&self) -> LSS_R { + LSS_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:15 - Filter List Standard Start Address"] + #[inline(always)] + pub fn flssa(&mut self) -> FLSSA_W { + FLSSA_W { w: self } + } + #[doc = "Bits 16:23 - List Size Standard"] + #[inline(always)] + pub fn lss(&mut self) -> LSS_W { + LSS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Standard ID Filter Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sidfc](index.html) module"] +pub struct SIDFC_SPEC; +impl crate::RegisterSpec for SIDFC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [sidfc::R](R) reader structure"] +impl crate::Readable for SIDFC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [sidfc::W](W) writer structure"] +impl crate::Writable for SIDFC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SIDFC to value 0"] +impl crate::Resettable for SIDFC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/can0/tdcr.rs b/pac/atsamc21e/src/can0/tdcr.rs new file mode 100644 index 000000000000..0cec58f98e28 --- /dev/null +++ b/pac/atsamc21e/src/can0/tdcr.rs @@ -0,0 +1,140 @@ +#[doc = "Register `TDCR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TDCR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TDCF` reader - Transmitter Delay Compensation Filter Length"] +pub struct TDCF_R(crate::FieldReader); +impl TDCF_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TDCF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TDCF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TDCF` writer - Transmitter Delay Compensation Filter Length"] +pub struct TDCF_W<'a> { + w: &'a mut W, +} +impl<'a> TDCF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x7f) | (value as u32 & 0x7f); + self.w + } +} +#[doc = "Field `TDCO` reader - Transmitter Delay Compensation Offset"] +pub struct TDCO_R(crate::FieldReader); +impl TDCO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TDCO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TDCO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TDCO` writer - Transmitter Delay Compensation Offset"] +pub struct TDCO_W<'a> { + w: &'a mut W, +} +impl<'a> TDCO_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x7f << 8)) | ((value as u32 & 0x7f) << 8); + self.w + } +} +impl R { + #[doc = "Bits 0:6 - Transmitter Delay Compensation Filter Length"] + #[inline(always)] + pub fn tdcf(&self) -> TDCF_R { + TDCF_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bits 8:14 - Transmitter Delay Compensation Offset"] + #[inline(always)] + pub fn tdco(&self) -> TDCO_R { + TDCO_R::new(((self.bits >> 8) & 0x7f) as u8) + } +} +impl W { + #[doc = "Bits 0:6 - Transmitter Delay Compensation Filter Length"] + #[inline(always)] + pub fn tdcf(&mut self) -> TDCF_W { + TDCF_W { w: self } + } + #[doc = "Bits 8:14 - Transmitter Delay Compensation Offset"] + #[inline(always)] + pub fn tdco(&mut self) -> TDCO_W { + TDCO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Extended ID Filter Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tdcr](index.html) module"] +pub struct TDCR_SPEC; +impl crate::RegisterSpec for TDCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [tdcr::R](R) reader structure"] +impl crate::Readable for TDCR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [tdcr::W](W) writer structure"] +impl crate::Writable for TDCR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TDCR to value 0"] +impl crate::Resettable for TDCR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/can0/test.rs b/pac/atsamc21e/src/can0/test.rs new file mode 100644 index 000000000000..fe1417a03d90 --- /dev/null +++ b/pac/atsamc21e/src/can0/test.rs @@ -0,0 +1,272 @@ +#[doc = "Register `TEST` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TEST` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `LBCK` reader - Loop Back Mode"] +pub struct LBCK_R(crate::FieldReader); +impl LBCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LBCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LBCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LBCK` writer - Loop Back Mode"] +pub struct LBCK_W<'a> { + w: &'a mut W, +} +impl<'a> LBCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Control of Transmit Pin\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum TX_A { + #[doc = "0: TX controlled by CAN core"] + CORE = 0, + #[doc = "1: TX monitoring sample point"] + SAMPLE = 1, + #[doc = "2: Dominant (0) level at pin CAN_TX"] + DOMINANT = 2, + #[doc = "3: Recessive (1) level at pin CAN_TX"] + RECESSIVE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: TX_A) -> Self { + variant as _ + } +} +#[doc = "Field `TX` reader - Control of Transmit Pin"] +pub struct TX_R(crate::FieldReader); +impl TX_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TX_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TX_A { + match self.bits { + 0 => TX_A::CORE, + 1 => TX_A::SAMPLE, + 2 => TX_A::DOMINANT, + 3 => TX_A::RECESSIVE, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `CORE`"] + #[inline(always)] + pub fn is_core(&self) -> bool { + **self == TX_A::CORE + } + #[doc = "Checks if the value of the field is `SAMPLE`"] + #[inline(always)] + pub fn is_sample(&self) -> bool { + **self == TX_A::SAMPLE + } + #[doc = "Checks if the value of the field is `DOMINANT`"] + #[inline(always)] + pub fn is_dominant(&self) -> bool { + **self == TX_A::DOMINANT + } + #[doc = "Checks if the value of the field is `RECESSIVE`"] + #[inline(always)] + pub fn is_recessive(&self) -> bool { + **self == TX_A::RECESSIVE + } +} +impl core::ops::Deref for TX_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TX` writer - Control of Transmit Pin"] +pub struct TX_W<'a> { + w: &'a mut W, +} +impl<'a> TX_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TX_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "TX controlled by CAN core"] + #[inline(always)] + pub fn core(self) -> &'a mut W { + self.variant(TX_A::CORE) + } + #[doc = "TX monitoring sample point"] + #[inline(always)] + pub fn sample(self) -> &'a mut W { + self.variant(TX_A::SAMPLE) + } + #[doc = "Dominant (0) level at pin CAN_TX"] + #[inline(always)] + pub fn dominant(self) -> &'a mut W { + self.variant(TX_A::DOMINANT) + } + #[doc = "Recessive (1) level at pin CAN_TX"] + #[inline(always)] + pub fn recessive(self) -> &'a mut W { + self.variant(TX_A::RECESSIVE) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 5)) | ((value as u32 & 0x03) << 5); + self.w + } +} +#[doc = "Field `RX` reader - Receive Pin"] +pub struct RX_R(crate::FieldReader); +impl RX_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RX_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RX_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RX` writer - Receive Pin"] +pub struct RX_W<'a> { + w: &'a mut W, +} +impl<'a> RX_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 4 - Loop Back Mode"] + #[inline(always)] + pub fn lbck(&self) -> LBCK_R { + LBCK_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bits 5:6 - Control of Transmit Pin"] + #[inline(always)] + pub fn tx(&self) -> TX_R { + TX_R::new(((self.bits >> 5) & 0x03) as u8) + } + #[doc = "Bit 7 - Receive Pin"] + #[inline(always)] + pub fn rx(&self) -> RX_R { + RX_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 4 - Loop Back Mode"] + #[inline(always)] + pub fn lbck(&mut self) -> LBCK_W { + LBCK_W { w: self } + } + #[doc = "Bits 5:6 - Control of Transmit Pin"] + #[inline(always)] + pub fn tx(&mut self) -> TX_W { + TX_W { w: self } + } + #[doc = "Bit 7 - Receive Pin"] + #[inline(always)] + pub fn rx(&mut self) -> RX_W { + RX_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Test\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [test](index.html) module"] +pub struct TEST_SPEC; +impl crate::RegisterSpec for TEST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [test::R](R) reader structure"] +impl crate::Readable for TEST_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [test::W](W) writer structure"] +impl crate::Writable for TEST_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TEST to value 0"] +impl crate::Resettable for TEST_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/can0/tocc.rs b/pac/atsamc21e/src/can0/tocc.rs new file mode 100644 index 000000000000..fa64916ef75f --- /dev/null +++ b/pac/atsamc21e/src/can0/tocc.rs @@ -0,0 +1,262 @@ +#[doc = "Register `TOCC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TOCC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ETOC` reader - Enable Timeout Counter"] +pub struct ETOC_R(crate::FieldReader); +impl ETOC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ETOC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ETOC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ETOC` writer - Enable Timeout Counter"] +pub struct ETOC_W<'a> { + w: &'a mut W, +} +impl<'a> ETOC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Timeout Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum TOS_A { + #[doc = "0: Continuout operation"] + CONT = 0, + #[doc = "1: Timeout controlled by TX Event FIFO"] + TXEF = 1, + #[doc = "2: Timeout controlled by Rx FIFO 0"] + RXF0 = 2, + #[doc = "3: Timeout controlled by Rx FIFO 1"] + RXF1 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: TOS_A) -> Self { + variant as _ + } +} +#[doc = "Field `TOS` reader - Timeout Select"] +pub struct TOS_R(crate::FieldReader); +impl TOS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TOS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TOS_A { + match self.bits { + 0 => TOS_A::CONT, + 1 => TOS_A::TXEF, + 2 => TOS_A::RXF0, + 3 => TOS_A::RXF1, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `CONT`"] + #[inline(always)] + pub fn is_cont(&self) -> bool { + **self == TOS_A::CONT + } + #[doc = "Checks if the value of the field is `TXEF`"] + #[inline(always)] + pub fn is_txef(&self) -> bool { + **self == TOS_A::TXEF + } + #[doc = "Checks if the value of the field is `RXF0`"] + #[inline(always)] + pub fn is_rxf0(&self) -> bool { + **self == TOS_A::RXF0 + } + #[doc = "Checks if the value of the field is `RXF1`"] + #[inline(always)] + pub fn is_rxf1(&self) -> bool { + **self == TOS_A::RXF1 + } +} +impl core::ops::Deref for TOS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TOS` writer - Timeout Select"] +pub struct TOS_W<'a> { + w: &'a mut W, +} +impl<'a> TOS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TOS_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Continuout operation"] + #[inline(always)] + pub fn cont(self) -> &'a mut W { + self.variant(TOS_A::CONT) + } + #[doc = "Timeout controlled by TX Event FIFO"] + #[inline(always)] + pub fn txef(self) -> &'a mut W { + self.variant(TOS_A::TXEF) + } + #[doc = "Timeout controlled by Rx FIFO 0"] + #[inline(always)] + pub fn rxf0(self) -> &'a mut W { + self.variant(TOS_A::RXF0) + } + #[doc = "Timeout controlled by Rx FIFO 1"] + #[inline(always)] + pub fn rxf1(self) -> &'a mut W { + self.variant(TOS_A::RXF1) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 1)) | ((value as u32 & 0x03) << 1); + self.w + } +} +#[doc = "Field `TOP` reader - Timeout Period"] +pub struct TOP_R(crate::FieldReader); +impl TOP_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + TOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TOP` writer - Timeout Period"] +pub struct TOP_W<'a> { + w: &'a mut W, +} +impl<'a> TOP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xffff << 16)) | ((value as u32 & 0xffff) << 16); + self.w + } +} +impl R { + #[doc = "Bit 0 - Enable Timeout Counter"] + #[inline(always)] + pub fn etoc(&self) -> ETOC_R { + ETOC_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bits 1:2 - Timeout Select"] + #[inline(always)] + pub fn tos(&self) -> TOS_R { + TOS_R::new(((self.bits >> 1) & 0x03) as u8) + } + #[doc = "Bits 16:31 - Timeout Period"] + #[inline(always)] + pub fn top(&self) -> TOP_R { + TOP_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bit 0 - Enable Timeout Counter"] + #[inline(always)] + pub fn etoc(&mut self) -> ETOC_W { + ETOC_W { w: self } + } + #[doc = "Bits 1:2 - Timeout Select"] + #[inline(always)] + pub fn tos(&mut self) -> TOS_W { + TOS_W { w: self } + } + #[doc = "Bits 16:31 - Timeout Period"] + #[inline(always)] + pub fn top(&mut self) -> TOP_W { + TOP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Timeout Counter Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tocc](index.html) module"] +pub struct TOCC_SPEC; +impl crate::RegisterSpec for TOCC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [tocc::R](R) reader structure"] +impl crate::Readable for TOCC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [tocc::W](W) writer structure"] +impl crate::Writable for TOCC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TOCC to value 0xffff_0000"] +impl crate::Resettable for TOCC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_0000 + } +} diff --git a/pac/atsamc21e/src/can0/tocv.rs b/pac/atsamc21e/src/can0/tocv.rs new file mode 100644 index 000000000000..f49b24ce65bf --- /dev/null +++ b/pac/atsamc21e/src/can0/tocv.rs @@ -0,0 +1,103 @@ +#[doc = "Register `TOCV` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TOCV` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TOC` reader - Timeout Counter"] +pub struct TOC_R(crate::FieldReader); +impl TOC_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + TOC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TOC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TOC` writer - Timeout Counter"] +pub struct TOC_W<'a> { + w: &'a mut W, +} +impl<'a> TOC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Timeout Counter"] + #[inline(always)] + pub fn toc(&self) -> TOC_R { + TOC_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Timeout Counter"] + #[inline(always)] + pub fn toc(&mut self) -> TOC_W { + TOC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Timeout Counter Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tocv](index.html) module"] +pub struct TOCV_SPEC; +impl crate::RegisterSpec for TOCV_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [tocv::R](R) reader structure"] +impl crate::Readable for TOCV_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [tocv::W](W) writer structure"] +impl crate::Writable for TOCV_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TOCV to value 0xffff"] +impl crate::Resettable for TOCV_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff + } +} diff --git a/pac/atsamc21e/src/can0/tscc.rs b/pac/atsamc21e/src/can0/tscc.rs new file mode 100644 index 000000000000..298084cc06b8 --- /dev/null +++ b/pac/atsamc21e/src/can0/tscc.rs @@ -0,0 +1,202 @@ +#[doc = "Register `TSCC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TSCC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Timestamp Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum TSS_A { + #[doc = "0: Timestamp counter value always 0x0000"] + ZERO = 0, + #[doc = "1: Timestamp counter value incremented by TCP"] + INC = 1, + #[doc = "2: External timestamp counter value used"] + EXT = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: TSS_A) -> Self { + variant as _ + } +} +#[doc = "Field `TSS` reader - Timestamp Select"] +pub struct TSS_R(crate::FieldReader); +impl TSS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TSS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(TSS_A::ZERO), + 1 => Some(TSS_A::INC), + 2 => Some(TSS_A::EXT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `ZERO`"] + #[inline(always)] + pub fn is_zero(&self) -> bool { + **self == TSS_A::ZERO + } + #[doc = "Checks if the value of the field is `INC`"] + #[inline(always)] + pub fn is_inc(&self) -> bool { + **self == TSS_A::INC + } + #[doc = "Checks if the value of the field is `EXT`"] + #[inline(always)] + pub fn is_ext(&self) -> bool { + **self == TSS_A::EXT + } +} +impl core::ops::Deref for TSS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSS` writer - Timestamp Select"] +pub struct TSS_W<'a> { + w: &'a mut W, +} +impl<'a> TSS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TSS_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Timestamp counter value always 0x0000"] + #[inline(always)] + pub fn zero(self) -> &'a mut W { + self.variant(TSS_A::ZERO) + } + #[doc = "Timestamp counter value incremented by TCP"] + #[inline(always)] + pub fn inc(self) -> &'a mut W { + self.variant(TSS_A::INC) + } + #[doc = "External timestamp counter value used"] + #[inline(always)] + pub fn ext(self) -> &'a mut W { + self.variant(TSS_A::EXT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u32 & 0x03); + self.w + } +} +#[doc = "Field `TCP` reader - Timestamp Counter Prescaler"] +pub struct TCP_R(crate::FieldReader); +impl TCP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TCP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCP` writer - Timestamp Counter Prescaler"] +pub struct TCP_W<'a> { + w: &'a mut W, +} +impl<'a> TCP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 16)) | ((value as u32 & 0x0f) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Timestamp Select"] + #[inline(always)] + pub fn tss(&self) -> TSS_R { + TSS_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bits 16:19 - Timestamp Counter Prescaler"] + #[inline(always)] + pub fn tcp(&self) -> TCP_R { + TCP_R::new(((self.bits >> 16) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Timestamp Select"] + #[inline(always)] + pub fn tss(&mut self) -> TSS_W { + TSS_W { w: self } + } + #[doc = "Bits 16:19 - Timestamp Counter Prescaler"] + #[inline(always)] + pub fn tcp(&mut self) -> TCP_W { + TCP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Timestamp Counter Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tscc](index.html) module"] +pub struct TSCC_SPEC; +impl crate::RegisterSpec for TSCC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [tscc::R](R) reader structure"] +impl crate::Readable for TSCC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [tscc::W](W) writer structure"] +impl crate::Writable for TSCC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TSCC to value 0"] +impl crate::Resettable for TSCC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/can0/tscv.rs b/pac/atsamc21e/src/can0/tscv.rs new file mode 100644 index 000000000000..7ba4561d588f --- /dev/null +++ b/pac/atsamc21e/src/can0/tscv.rs @@ -0,0 +1,53 @@ +#[doc = "Register `TSCV` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `TSC` reader - Timestamp Counter"] +pub struct TSC_R(crate::FieldReader); +impl TSC_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + TSC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:15 - Timestamp Counter"] + #[inline(always)] + pub fn tsc(&self) -> TSC_R { + TSC_R::new((self.bits & 0xffff) as u16) + } +} +#[doc = "Timestamp Counter Value\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tscv](index.html) module"] +pub struct TSCV_SPEC; +impl crate::RegisterSpec for TSCV_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [tscv::R](R) reader structure"] +impl crate::Readable for TSCV_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets TSCV to value 0"] +impl crate::Resettable for TSCV_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/can0/txbar.rs b/pac/atsamc21e/src/can0/txbar.rs new file mode 100644 index 000000000000..bd15a3f2bd29 --- /dev/null +++ b/pac/atsamc21e/src/can0/txbar.rs @@ -0,0 +1,1570 @@ +#[doc = "Register `TXBAR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TXBAR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `AR0` reader - Add Request 0"] +pub struct AR0_R(crate::FieldReader); +impl AR0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR0` writer - Add Request 0"] +pub struct AR0_W<'a> { + w: &'a mut W, +} +impl<'a> AR0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `AR1` reader - Add Request 1"] +pub struct AR1_R(crate::FieldReader); +impl AR1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR1` writer - Add Request 1"] +pub struct AR1_W<'a> { + w: &'a mut W, +} +impl<'a> AR1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `AR2` reader - Add Request 2"] +pub struct AR2_R(crate::FieldReader); +impl AR2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR2` writer - Add Request 2"] +pub struct AR2_W<'a> { + w: &'a mut W, +} +impl<'a> AR2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `AR3` reader - Add Request 3"] +pub struct AR3_R(crate::FieldReader); +impl AR3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR3` writer - Add Request 3"] +pub struct AR3_W<'a> { + w: &'a mut W, +} +impl<'a> AR3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `AR4` reader - Add Request 4"] +pub struct AR4_R(crate::FieldReader); +impl AR4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR4` writer - Add Request 4"] +pub struct AR4_W<'a> { + w: &'a mut W, +} +impl<'a> AR4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `AR5` reader - Add Request 5"] +pub struct AR5_R(crate::FieldReader); +impl AR5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR5` writer - Add Request 5"] +pub struct AR5_W<'a> { + w: &'a mut W, +} +impl<'a> AR5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `AR6` reader - Add Request 6"] +pub struct AR6_R(crate::FieldReader); +impl AR6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR6` writer - Add Request 6"] +pub struct AR6_W<'a> { + w: &'a mut W, +} +impl<'a> AR6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `AR7` reader - Add Request 7"] +pub struct AR7_R(crate::FieldReader); +impl AR7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR7` writer - Add Request 7"] +pub struct AR7_W<'a> { + w: &'a mut W, +} +impl<'a> AR7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `AR8` reader - Add Request 8"] +pub struct AR8_R(crate::FieldReader); +impl AR8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR8` writer - Add Request 8"] +pub struct AR8_W<'a> { + w: &'a mut W, +} +impl<'a> AR8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `AR9` reader - Add Request 9"] +pub struct AR9_R(crate::FieldReader); +impl AR9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR9` writer - Add Request 9"] +pub struct AR9_W<'a> { + w: &'a mut W, +} +impl<'a> AR9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `AR10` reader - Add Request 10"] +pub struct AR10_R(crate::FieldReader); +impl AR10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR10` writer - Add Request 10"] +pub struct AR10_W<'a> { + w: &'a mut W, +} +impl<'a> AR10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `AR11` reader - Add Request 11"] +pub struct AR11_R(crate::FieldReader); +impl AR11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR11` writer - Add Request 11"] +pub struct AR11_W<'a> { + w: &'a mut W, +} +impl<'a> AR11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `AR12` reader - Add Request 12"] +pub struct AR12_R(crate::FieldReader); +impl AR12_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR12_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR12_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR12` writer - Add Request 12"] +pub struct AR12_W<'a> { + w: &'a mut W, +} +impl<'a> AR12_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `AR13` reader - Add Request 13"] +pub struct AR13_R(crate::FieldReader); +impl AR13_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR13_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR13_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR13` writer - Add Request 13"] +pub struct AR13_W<'a> { + w: &'a mut W, +} +impl<'a> AR13_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `AR14` reader - Add Request 14"] +pub struct AR14_R(crate::FieldReader); +impl AR14_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR14_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR14_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR14` writer - Add Request 14"] +pub struct AR14_W<'a> { + w: &'a mut W, +} +impl<'a> AR14_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `AR15` reader - Add Request 15"] +pub struct AR15_R(crate::FieldReader); +impl AR15_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR15_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR15_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR15` writer - Add Request 15"] +pub struct AR15_W<'a> { + w: &'a mut W, +} +impl<'a> AR15_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `AR16` reader - Add Request 16"] +pub struct AR16_R(crate::FieldReader); +impl AR16_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR16_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR16_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR16` writer - Add Request 16"] +pub struct AR16_W<'a> { + w: &'a mut W, +} +impl<'a> AR16_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `AR17` reader - Add Request 17"] +pub struct AR17_R(crate::FieldReader); +impl AR17_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR17_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR17_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR17` writer - Add Request 17"] +pub struct AR17_W<'a> { + w: &'a mut W, +} +impl<'a> AR17_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `AR18` reader - Add Request 18"] +pub struct AR18_R(crate::FieldReader); +impl AR18_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR18_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR18_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR18` writer - Add Request 18"] +pub struct AR18_W<'a> { + w: &'a mut W, +} +impl<'a> AR18_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `AR19` reader - Add Request 19"] +pub struct AR19_R(crate::FieldReader); +impl AR19_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR19_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR19_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR19` writer - Add Request 19"] +pub struct AR19_W<'a> { + w: &'a mut W, +} +impl<'a> AR19_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `AR20` reader - Add Request 20"] +pub struct AR20_R(crate::FieldReader); +impl AR20_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR20_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR20_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR20` writer - Add Request 20"] +pub struct AR20_W<'a> { + w: &'a mut W, +} +impl<'a> AR20_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `AR21` reader - Add Request 21"] +pub struct AR21_R(crate::FieldReader); +impl AR21_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR21_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR21_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR21` writer - Add Request 21"] +pub struct AR21_W<'a> { + w: &'a mut W, +} +impl<'a> AR21_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `AR22` reader - Add Request 22"] +pub struct AR22_R(crate::FieldReader); +impl AR22_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR22_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR22_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR22` writer - Add Request 22"] +pub struct AR22_W<'a> { + w: &'a mut W, +} +impl<'a> AR22_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `AR23` reader - Add Request 23"] +pub struct AR23_R(crate::FieldReader); +impl AR23_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR23_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR23_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR23` writer - Add Request 23"] +pub struct AR23_W<'a> { + w: &'a mut W, +} +impl<'a> AR23_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `AR24` reader - Add Request 24"] +pub struct AR24_R(crate::FieldReader); +impl AR24_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR24_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR24_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR24` writer - Add Request 24"] +pub struct AR24_W<'a> { + w: &'a mut W, +} +impl<'a> AR24_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `AR25` reader - Add Request 25"] +pub struct AR25_R(crate::FieldReader); +impl AR25_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR25_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR25_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR25` writer - Add Request 25"] +pub struct AR25_W<'a> { + w: &'a mut W, +} +impl<'a> AR25_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `AR26` reader - Add Request 26"] +pub struct AR26_R(crate::FieldReader); +impl AR26_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR26_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR26_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR26` writer - Add Request 26"] +pub struct AR26_W<'a> { + w: &'a mut W, +} +impl<'a> AR26_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `AR27` reader - Add Request 27"] +pub struct AR27_R(crate::FieldReader); +impl AR27_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR27_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR27_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR27` writer - Add Request 27"] +pub struct AR27_W<'a> { + w: &'a mut W, +} +impl<'a> AR27_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +#[doc = "Field `AR28` reader - Add Request 28"] +pub struct AR28_R(crate::FieldReader); +impl AR28_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR28_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR28_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR28` writer - Add Request 28"] +pub struct AR28_W<'a> { + w: &'a mut W, +} +impl<'a> AR28_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Field `AR29` reader - Add Request 29"] +pub struct AR29_R(crate::FieldReader); +impl AR29_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR29_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR29_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR29` writer - Add Request 29"] +pub struct AR29_W<'a> { + w: &'a mut W, +} +impl<'a> AR29_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29); + self.w + } +} +#[doc = "Field `AR30` reader - Add Request 30"] +pub struct AR30_R(crate::FieldReader); +impl AR30_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR30_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR30_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR30` writer - Add Request 30"] +pub struct AR30_W<'a> { + w: &'a mut W, +} +impl<'a> AR30_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +#[doc = "Field `AR31` reader - Add Request 31"] +pub struct AR31_R(crate::FieldReader); +impl AR31_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR31_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR31_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR31` writer - Add Request 31"] +pub struct AR31_W<'a> { + w: &'a mut W, +} +impl<'a> AR31_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bit 0 - Add Request 0"] + #[inline(always)] + pub fn ar0(&self) -> AR0_R { + AR0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Add Request 1"] + #[inline(always)] + pub fn ar1(&self) -> AR1_R { + AR1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Add Request 2"] + #[inline(always)] + pub fn ar2(&self) -> AR2_R { + AR2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Add Request 3"] + #[inline(always)] + pub fn ar3(&self) -> AR3_R { + AR3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Add Request 4"] + #[inline(always)] + pub fn ar4(&self) -> AR4_R { + AR4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Add Request 5"] + #[inline(always)] + pub fn ar5(&self) -> AR5_R { + AR5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Add Request 6"] + #[inline(always)] + pub fn ar6(&self) -> AR6_R { + AR6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Add Request 7"] + #[inline(always)] + pub fn ar7(&self) -> AR7_R { + AR7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Add Request 8"] + #[inline(always)] + pub fn ar8(&self) -> AR8_R { + AR8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Add Request 9"] + #[inline(always)] + pub fn ar9(&self) -> AR9_R { + AR9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Add Request 10"] + #[inline(always)] + pub fn ar10(&self) -> AR10_R { + AR10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Add Request 11"] + #[inline(always)] + pub fn ar11(&self) -> AR11_R { + AR11_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Add Request 12"] + #[inline(always)] + pub fn ar12(&self) -> AR12_R { + AR12_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Add Request 13"] + #[inline(always)] + pub fn ar13(&self) -> AR13_R { + AR13_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Add Request 14"] + #[inline(always)] + pub fn ar14(&self) -> AR14_R { + AR14_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Add Request 15"] + #[inline(always)] + pub fn ar15(&self) -> AR15_R { + AR15_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Add Request 16"] + #[inline(always)] + pub fn ar16(&self) -> AR16_R { + AR16_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Add Request 17"] + #[inline(always)] + pub fn ar17(&self) -> AR17_R { + AR17_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Add Request 18"] + #[inline(always)] + pub fn ar18(&self) -> AR18_R { + AR18_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Add Request 19"] + #[inline(always)] + pub fn ar19(&self) -> AR19_R { + AR19_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Add Request 20"] + #[inline(always)] + pub fn ar20(&self) -> AR20_R { + AR20_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Add Request 21"] + #[inline(always)] + pub fn ar21(&self) -> AR21_R { + AR21_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Add Request 22"] + #[inline(always)] + pub fn ar22(&self) -> AR22_R { + AR22_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Add Request 23"] + #[inline(always)] + pub fn ar23(&self) -> AR23_R { + AR23_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24 - Add Request 24"] + #[inline(always)] + pub fn ar24(&self) -> AR24_R { + AR24_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Add Request 25"] + #[inline(always)] + pub fn ar25(&self) -> AR25_R { + AR25_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Add Request 26"] + #[inline(always)] + pub fn ar26(&self) -> AR26_R { + AR26_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Add Request 27"] + #[inline(always)] + pub fn ar27(&self) -> AR27_R { + AR27_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28 - Add Request 28"] + #[inline(always)] + pub fn ar28(&self) -> AR28_R { + AR28_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Add Request 29"] + #[inline(always)] + pub fn ar29(&self) -> AR29_R { + AR29_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - Add Request 30"] + #[inline(always)] + pub fn ar30(&self) -> AR30_R { + AR30_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 31 - Add Request 31"] + #[inline(always)] + pub fn ar31(&self) -> AR31_R { + AR31_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Add Request 0"] + #[inline(always)] + pub fn ar0(&mut self) -> AR0_W { + AR0_W { w: self } + } + #[doc = "Bit 1 - Add Request 1"] + #[inline(always)] + pub fn ar1(&mut self) -> AR1_W { + AR1_W { w: self } + } + #[doc = "Bit 2 - Add Request 2"] + #[inline(always)] + pub fn ar2(&mut self) -> AR2_W { + AR2_W { w: self } + } + #[doc = "Bit 3 - Add Request 3"] + #[inline(always)] + pub fn ar3(&mut self) -> AR3_W { + AR3_W { w: self } + } + #[doc = "Bit 4 - Add Request 4"] + #[inline(always)] + pub fn ar4(&mut self) -> AR4_W { + AR4_W { w: self } + } + #[doc = "Bit 5 - Add Request 5"] + #[inline(always)] + pub fn ar5(&mut self) -> AR5_W { + AR5_W { w: self } + } + #[doc = "Bit 6 - Add Request 6"] + #[inline(always)] + pub fn ar6(&mut self) -> AR6_W { + AR6_W { w: self } + } + #[doc = "Bit 7 - Add Request 7"] + #[inline(always)] + pub fn ar7(&mut self) -> AR7_W { + AR7_W { w: self } + } + #[doc = "Bit 8 - Add Request 8"] + #[inline(always)] + pub fn ar8(&mut self) -> AR8_W { + AR8_W { w: self } + } + #[doc = "Bit 9 - Add Request 9"] + #[inline(always)] + pub fn ar9(&mut self) -> AR9_W { + AR9_W { w: self } + } + #[doc = "Bit 10 - Add Request 10"] + #[inline(always)] + pub fn ar10(&mut self) -> AR10_W { + AR10_W { w: self } + } + #[doc = "Bit 11 - Add Request 11"] + #[inline(always)] + pub fn ar11(&mut self) -> AR11_W { + AR11_W { w: self } + } + #[doc = "Bit 12 - Add Request 12"] + #[inline(always)] + pub fn ar12(&mut self) -> AR12_W { + AR12_W { w: self } + } + #[doc = "Bit 13 - Add Request 13"] + #[inline(always)] + pub fn ar13(&mut self) -> AR13_W { + AR13_W { w: self } + } + #[doc = "Bit 14 - Add Request 14"] + #[inline(always)] + pub fn ar14(&mut self) -> AR14_W { + AR14_W { w: self } + } + #[doc = "Bit 15 - Add Request 15"] + #[inline(always)] + pub fn ar15(&mut self) -> AR15_W { + AR15_W { w: self } + } + #[doc = "Bit 16 - Add Request 16"] + #[inline(always)] + pub fn ar16(&mut self) -> AR16_W { + AR16_W { w: self } + } + #[doc = "Bit 17 - Add Request 17"] + #[inline(always)] + pub fn ar17(&mut self) -> AR17_W { + AR17_W { w: self } + } + #[doc = "Bit 18 - Add Request 18"] + #[inline(always)] + pub fn ar18(&mut self) -> AR18_W { + AR18_W { w: self } + } + #[doc = "Bit 19 - Add Request 19"] + #[inline(always)] + pub fn ar19(&mut self) -> AR19_W { + AR19_W { w: self } + } + #[doc = "Bit 20 - Add Request 20"] + #[inline(always)] + pub fn ar20(&mut self) -> AR20_W { + AR20_W { w: self } + } + #[doc = "Bit 21 - Add Request 21"] + #[inline(always)] + pub fn ar21(&mut self) -> AR21_W { + AR21_W { w: self } + } + #[doc = "Bit 22 - Add Request 22"] + #[inline(always)] + pub fn ar22(&mut self) -> AR22_W { + AR22_W { w: self } + } + #[doc = "Bit 23 - Add Request 23"] + #[inline(always)] + pub fn ar23(&mut self) -> AR23_W { + AR23_W { w: self } + } + #[doc = "Bit 24 - Add Request 24"] + #[inline(always)] + pub fn ar24(&mut self) -> AR24_W { + AR24_W { w: self } + } + #[doc = "Bit 25 - Add Request 25"] + #[inline(always)] + pub fn ar25(&mut self) -> AR25_W { + AR25_W { w: self } + } + #[doc = "Bit 26 - Add Request 26"] + #[inline(always)] + pub fn ar26(&mut self) -> AR26_W { + AR26_W { w: self } + } + #[doc = "Bit 27 - Add Request 27"] + #[inline(always)] + pub fn ar27(&mut self) -> AR27_W { + AR27_W { w: self } + } + #[doc = "Bit 28 - Add Request 28"] + #[inline(always)] + pub fn ar28(&mut self) -> AR28_W { + AR28_W { w: self } + } + #[doc = "Bit 29 - Add Request 29"] + #[inline(always)] + pub fn ar29(&mut self) -> AR29_W { + AR29_W { w: self } + } + #[doc = "Bit 30 - Add Request 30"] + #[inline(always)] + pub fn ar30(&mut self) -> AR30_W { + AR30_W { w: self } + } + #[doc = "Bit 31 - Add Request 31"] + #[inline(always)] + pub fn ar31(&mut self) -> AR31_W { + AR31_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Tx Buffer Add Request\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txbar](index.html) module"] +pub struct TXBAR_SPEC; +impl crate::RegisterSpec for TXBAR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [txbar::R](R) reader structure"] +impl crate::Readable for TXBAR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [txbar::W](W) writer structure"] +impl crate::Writable for TXBAR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TXBAR to value 0"] +impl crate::Resettable for TXBAR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/can0/txbc.rs b/pac/atsamc21e/src/can0/txbc.rs new file mode 100644 index 000000000000..9545eaebf91d --- /dev/null +++ b/pac/atsamc21e/src/can0/txbc.rs @@ -0,0 +1,224 @@ +#[doc = "Register `TXBC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TXBC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TBSA` reader - Tx Buffers Start Address"] +pub struct TBSA_R(crate::FieldReader); +impl TBSA_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + TBSA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TBSA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TBSA` writer - Tx Buffers Start Address"] +pub struct TBSA_W<'a> { + w: &'a mut W, +} +impl<'a> TBSA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +#[doc = "Field `NDTB` reader - Number of Dedicated Transmit Buffers"] +pub struct NDTB_R(crate::FieldReader); +impl NDTB_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + NDTB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NDTB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NDTB` writer - Number of Dedicated Transmit Buffers"] +pub struct NDTB_W<'a> { + w: &'a mut W, +} +impl<'a> NDTB_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 16)) | ((value as u32 & 0x3f) << 16); + self.w + } +} +#[doc = "Field `TFQS` reader - Transmit FIFO/Queue Size"] +pub struct TFQS_R(crate::FieldReader); +impl TFQS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TFQS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TFQS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TFQS` writer - Transmit FIFO/Queue Size"] +pub struct TFQS_W<'a> { + w: &'a mut W, +} +impl<'a> TFQS_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 24)) | ((value as u32 & 0x3f) << 24); + self.w + } +} +#[doc = "Field `TFQM` reader - Tx FIFO/Queue Mode"] +pub struct TFQM_R(crate::FieldReader); +impl TFQM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TFQM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TFQM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TFQM` writer - Tx FIFO/Queue Mode"] +pub struct TFQM_W<'a> { + w: &'a mut W, +} +impl<'a> TFQM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Tx Buffers Start Address"] + #[inline(always)] + pub fn tbsa(&self) -> TBSA_R { + TBSA_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:21 - Number of Dedicated Transmit Buffers"] + #[inline(always)] + pub fn ndtb(&self) -> NDTB_R { + NDTB_R::new(((self.bits >> 16) & 0x3f) as u8) + } + #[doc = "Bits 24:29 - Transmit FIFO/Queue Size"] + #[inline(always)] + pub fn tfqs(&self) -> TFQS_R { + TFQS_R::new(((self.bits >> 24) & 0x3f) as u8) + } + #[doc = "Bit 30 - Tx FIFO/Queue Mode"] + #[inline(always)] + pub fn tfqm(&self) -> TFQM_R { + TFQM_R::new(((self.bits >> 30) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Tx Buffers Start Address"] + #[inline(always)] + pub fn tbsa(&mut self) -> TBSA_W { + TBSA_W { w: self } + } + #[doc = "Bits 16:21 - Number of Dedicated Transmit Buffers"] + #[inline(always)] + pub fn ndtb(&mut self) -> NDTB_W { + NDTB_W { w: self } + } + #[doc = "Bits 24:29 - Transmit FIFO/Queue Size"] + #[inline(always)] + pub fn tfqs(&mut self) -> TFQS_W { + TFQS_W { w: self } + } + #[doc = "Bit 30 - Tx FIFO/Queue Mode"] + #[inline(always)] + pub fn tfqm(&mut self) -> TFQM_W { + TFQM_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Tx Buffer Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txbc](index.html) module"] +pub struct TXBC_SPEC; +impl crate::RegisterSpec for TXBC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [txbc::R](R) reader structure"] +impl crate::Readable for TXBC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [txbc::W](W) writer structure"] +impl crate::Writable for TXBC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TXBC to value 0"] +impl crate::Resettable for TXBC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/can0/txbcf.rs b/pac/atsamc21e/src/can0/txbcf.rs new file mode 100644 index 000000000000..e592d4e90bea --- /dev/null +++ b/pac/atsamc21e/src/can0/txbcf.rs @@ -0,0 +1,673 @@ +#[doc = "Register `TXBCF` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `CF0` reader - Tx Buffer Cancellation Finished 0"] +pub struct CF0_R(crate::FieldReader); +impl CF0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF1` reader - Tx Buffer Cancellation Finished 1"] +pub struct CF1_R(crate::FieldReader); +impl CF1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF2` reader - Tx Buffer Cancellation Finished 2"] +pub struct CF2_R(crate::FieldReader); +impl CF2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF3` reader - Tx Buffer Cancellation Finished 3"] +pub struct CF3_R(crate::FieldReader); +impl CF3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF4` reader - Tx Buffer Cancellation Finished 4"] +pub struct CF4_R(crate::FieldReader); +impl CF4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF5` reader - Tx Buffer Cancellation Finished 5"] +pub struct CF5_R(crate::FieldReader); +impl CF5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF6` reader - Tx Buffer Cancellation Finished 6"] +pub struct CF6_R(crate::FieldReader); +impl CF6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF7` reader - Tx Buffer Cancellation Finished 7"] +pub struct CF7_R(crate::FieldReader); +impl CF7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF8` reader - Tx Buffer Cancellation Finished 8"] +pub struct CF8_R(crate::FieldReader); +impl CF8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF9` reader - Tx Buffer Cancellation Finished 9"] +pub struct CF9_R(crate::FieldReader); +impl CF9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF10` reader - Tx Buffer Cancellation Finished 10"] +pub struct CF10_R(crate::FieldReader); +impl CF10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF11` reader - Tx Buffer Cancellation Finished 11"] +pub struct CF11_R(crate::FieldReader); +impl CF11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF12` reader - Tx Buffer Cancellation Finished 12"] +pub struct CF12_R(crate::FieldReader); +impl CF12_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF12_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF12_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF13` reader - Tx Buffer Cancellation Finished 13"] +pub struct CF13_R(crate::FieldReader); +impl CF13_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF13_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF13_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF14` reader - Tx Buffer Cancellation Finished 14"] +pub struct CF14_R(crate::FieldReader); +impl CF14_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF14_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF14_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF15` reader - Tx Buffer Cancellation Finished 15"] +pub struct CF15_R(crate::FieldReader); +impl CF15_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF15_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF15_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF16` reader - Tx Buffer Cancellation Finished 16"] +pub struct CF16_R(crate::FieldReader); +impl CF16_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF16_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF16_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF17` reader - Tx Buffer Cancellation Finished 17"] +pub struct CF17_R(crate::FieldReader); +impl CF17_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF17_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF17_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF18` reader - Tx Buffer Cancellation Finished 18"] +pub struct CF18_R(crate::FieldReader); +impl CF18_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF18_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF18_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF19` reader - Tx Buffer Cancellation Finished 19"] +pub struct CF19_R(crate::FieldReader); +impl CF19_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF19_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF19_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF20` reader - Tx Buffer Cancellation Finished 20"] +pub struct CF20_R(crate::FieldReader); +impl CF20_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF20_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF20_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF21` reader - Tx Buffer Cancellation Finished 21"] +pub struct CF21_R(crate::FieldReader); +impl CF21_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF21_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF21_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF22` reader - Tx Buffer Cancellation Finished 22"] +pub struct CF22_R(crate::FieldReader); +impl CF22_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF22_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF22_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF23` reader - Tx Buffer Cancellation Finished 23"] +pub struct CF23_R(crate::FieldReader); +impl CF23_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF23_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF23_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF24` reader - Tx Buffer Cancellation Finished 24"] +pub struct CF24_R(crate::FieldReader); +impl CF24_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF24_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF24_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF25` reader - Tx Buffer Cancellation Finished 25"] +pub struct CF25_R(crate::FieldReader); +impl CF25_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF25_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF25_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF26` reader - Tx Buffer Cancellation Finished 26"] +pub struct CF26_R(crate::FieldReader); +impl CF26_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF26_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF26_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF27` reader - Tx Buffer Cancellation Finished 27"] +pub struct CF27_R(crate::FieldReader); +impl CF27_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF27_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF27_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF28` reader - Tx Buffer Cancellation Finished 28"] +pub struct CF28_R(crate::FieldReader); +impl CF28_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF28_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF28_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF29` reader - Tx Buffer Cancellation Finished 29"] +pub struct CF29_R(crate::FieldReader); +impl CF29_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF29_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF29_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF30` reader - Tx Buffer Cancellation Finished 30"] +pub struct CF30_R(crate::FieldReader); +impl CF30_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF30_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF30_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF31` reader - Tx Buffer Cancellation Finished 31"] +pub struct CF31_R(crate::FieldReader); +impl CF31_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF31_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF31_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Tx Buffer Cancellation Finished 0"] + #[inline(always)] + pub fn cf0(&self) -> CF0_R { + CF0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Tx Buffer Cancellation Finished 1"] + #[inline(always)] + pub fn cf1(&self) -> CF1_R { + CF1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Tx Buffer Cancellation Finished 2"] + #[inline(always)] + pub fn cf2(&self) -> CF2_R { + CF2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Tx Buffer Cancellation Finished 3"] + #[inline(always)] + pub fn cf3(&self) -> CF3_R { + CF3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Tx Buffer Cancellation Finished 4"] + #[inline(always)] + pub fn cf4(&self) -> CF4_R { + CF4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Tx Buffer Cancellation Finished 5"] + #[inline(always)] + pub fn cf5(&self) -> CF5_R { + CF5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Tx Buffer Cancellation Finished 6"] + #[inline(always)] + pub fn cf6(&self) -> CF6_R { + CF6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Tx Buffer Cancellation Finished 7"] + #[inline(always)] + pub fn cf7(&self) -> CF7_R { + CF7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Tx Buffer Cancellation Finished 8"] + #[inline(always)] + pub fn cf8(&self) -> CF8_R { + CF8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Tx Buffer Cancellation Finished 9"] + #[inline(always)] + pub fn cf9(&self) -> CF9_R { + CF9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Tx Buffer Cancellation Finished 10"] + #[inline(always)] + pub fn cf10(&self) -> CF10_R { + CF10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Tx Buffer Cancellation Finished 11"] + #[inline(always)] + pub fn cf11(&self) -> CF11_R { + CF11_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Tx Buffer Cancellation Finished 12"] + #[inline(always)] + pub fn cf12(&self) -> CF12_R { + CF12_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Tx Buffer Cancellation Finished 13"] + #[inline(always)] + pub fn cf13(&self) -> CF13_R { + CF13_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Tx Buffer Cancellation Finished 14"] + #[inline(always)] + pub fn cf14(&self) -> CF14_R { + CF14_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Tx Buffer Cancellation Finished 15"] + #[inline(always)] + pub fn cf15(&self) -> CF15_R { + CF15_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Tx Buffer Cancellation Finished 16"] + #[inline(always)] + pub fn cf16(&self) -> CF16_R { + CF16_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Tx Buffer Cancellation Finished 17"] + #[inline(always)] + pub fn cf17(&self) -> CF17_R { + CF17_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Tx Buffer Cancellation Finished 18"] + #[inline(always)] + pub fn cf18(&self) -> CF18_R { + CF18_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Tx Buffer Cancellation Finished 19"] + #[inline(always)] + pub fn cf19(&self) -> CF19_R { + CF19_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Tx Buffer Cancellation Finished 20"] + #[inline(always)] + pub fn cf20(&self) -> CF20_R { + CF20_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Tx Buffer Cancellation Finished 21"] + #[inline(always)] + pub fn cf21(&self) -> CF21_R { + CF21_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Tx Buffer Cancellation Finished 22"] + #[inline(always)] + pub fn cf22(&self) -> CF22_R { + CF22_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Tx Buffer Cancellation Finished 23"] + #[inline(always)] + pub fn cf23(&self) -> CF23_R { + CF23_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24 - Tx Buffer Cancellation Finished 24"] + #[inline(always)] + pub fn cf24(&self) -> CF24_R { + CF24_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Tx Buffer Cancellation Finished 25"] + #[inline(always)] + pub fn cf25(&self) -> CF25_R { + CF25_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Tx Buffer Cancellation Finished 26"] + #[inline(always)] + pub fn cf26(&self) -> CF26_R { + CF26_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Tx Buffer Cancellation Finished 27"] + #[inline(always)] + pub fn cf27(&self) -> CF27_R { + CF27_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28 - Tx Buffer Cancellation Finished 28"] + #[inline(always)] + pub fn cf28(&self) -> CF28_R { + CF28_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Tx Buffer Cancellation Finished 29"] + #[inline(always)] + pub fn cf29(&self) -> CF29_R { + CF29_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - Tx Buffer Cancellation Finished 30"] + #[inline(always)] + pub fn cf30(&self) -> CF30_R { + CF30_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 31 - Tx Buffer Cancellation Finished 31"] + #[inline(always)] + pub fn cf31(&self) -> CF31_R { + CF31_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +#[doc = "Tx Buffer Cancellation Finished\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txbcf](index.html) module"] +pub struct TXBCF_SPEC; +impl crate::RegisterSpec for TXBCF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [txbcf::R](R) reader structure"] +impl crate::Readable for TXBCF_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets TXBCF to value 0"] +impl crate::Resettable for TXBCF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/can0/txbcie.rs b/pac/atsamc21e/src/can0/txbcie.rs new file mode 100644 index 000000000000..ca0c9c0a2822 --- /dev/null +++ b/pac/atsamc21e/src/can0/txbcie.rs @@ -0,0 +1,1570 @@ +#[doc = "Register `TXBCIE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TXBCIE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CFIE0` reader - Cancellation Finished Interrupt Enable 0"] +pub struct CFIE0_R(crate::FieldReader); +impl CFIE0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE0` writer - Cancellation Finished Interrupt Enable 0"] +pub struct CFIE0_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `CFIE1` reader - Cancellation Finished Interrupt Enable 1"] +pub struct CFIE1_R(crate::FieldReader); +impl CFIE1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE1` writer - Cancellation Finished Interrupt Enable 1"] +pub struct CFIE1_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CFIE2` reader - Cancellation Finished Interrupt Enable 2"] +pub struct CFIE2_R(crate::FieldReader); +impl CFIE2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE2` writer - Cancellation Finished Interrupt Enable 2"] +pub struct CFIE2_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CFIE3` reader - Cancellation Finished Interrupt Enable 3"] +pub struct CFIE3_R(crate::FieldReader); +impl CFIE3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE3` writer - Cancellation Finished Interrupt Enable 3"] +pub struct CFIE3_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CFIE4` reader - Cancellation Finished Interrupt Enable 4"] +pub struct CFIE4_R(crate::FieldReader); +impl CFIE4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE4` writer - Cancellation Finished Interrupt Enable 4"] +pub struct CFIE4_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `CFIE5` reader - Cancellation Finished Interrupt Enable 5"] +pub struct CFIE5_R(crate::FieldReader); +impl CFIE5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE5` writer - Cancellation Finished Interrupt Enable 5"] +pub struct CFIE5_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `CFIE6` reader - Cancellation Finished Interrupt Enable 6"] +pub struct CFIE6_R(crate::FieldReader); +impl CFIE6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE6` writer - Cancellation Finished Interrupt Enable 6"] +pub struct CFIE6_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `CFIE7` reader - Cancellation Finished Interrupt Enable 7"] +pub struct CFIE7_R(crate::FieldReader); +impl CFIE7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE7` writer - Cancellation Finished Interrupt Enable 7"] +pub struct CFIE7_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CFIE8` reader - Cancellation Finished Interrupt Enable 8"] +pub struct CFIE8_R(crate::FieldReader); +impl CFIE8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE8` writer - Cancellation Finished Interrupt Enable 8"] +pub struct CFIE8_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `CFIE9` reader - Cancellation Finished Interrupt Enable 9"] +pub struct CFIE9_R(crate::FieldReader); +impl CFIE9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE9` writer - Cancellation Finished Interrupt Enable 9"] +pub struct CFIE9_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `CFIE10` reader - Cancellation Finished Interrupt Enable 10"] +pub struct CFIE10_R(crate::FieldReader); +impl CFIE10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE10` writer - Cancellation Finished Interrupt Enable 10"] +pub struct CFIE10_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `CFIE11` reader - Cancellation Finished Interrupt Enable 11"] +pub struct CFIE11_R(crate::FieldReader); +impl CFIE11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE11` writer - Cancellation Finished Interrupt Enable 11"] +pub struct CFIE11_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `CFIE12` reader - Cancellation Finished Interrupt Enable 12"] +pub struct CFIE12_R(crate::FieldReader); +impl CFIE12_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE12_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE12_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE12` writer - Cancellation Finished Interrupt Enable 12"] +pub struct CFIE12_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE12_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `CFIE13` reader - Cancellation Finished Interrupt Enable 13"] +pub struct CFIE13_R(crate::FieldReader); +impl CFIE13_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE13_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE13_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE13` writer - Cancellation Finished Interrupt Enable 13"] +pub struct CFIE13_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE13_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `CFIE14` reader - Cancellation Finished Interrupt Enable 14"] +pub struct CFIE14_R(crate::FieldReader); +impl CFIE14_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE14_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE14_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE14` writer - Cancellation Finished Interrupt Enable 14"] +pub struct CFIE14_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE14_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `CFIE15` reader - Cancellation Finished Interrupt Enable 15"] +pub struct CFIE15_R(crate::FieldReader); +impl CFIE15_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE15_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE15_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE15` writer - Cancellation Finished Interrupt Enable 15"] +pub struct CFIE15_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE15_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `CFIE16` reader - Cancellation Finished Interrupt Enable 16"] +pub struct CFIE16_R(crate::FieldReader); +impl CFIE16_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE16_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE16_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE16` writer - Cancellation Finished Interrupt Enable 16"] +pub struct CFIE16_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE16_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `CFIE17` reader - Cancellation Finished Interrupt Enable 17"] +pub struct CFIE17_R(crate::FieldReader); +impl CFIE17_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE17_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE17_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE17` writer - Cancellation Finished Interrupt Enable 17"] +pub struct CFIE17_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE17_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `CFIE18` reader - Cancellation Finished Interrupt Enable 18"] +pub struct CFIE18_R(crate::FieldReader); +impl CFIE18_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE18_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE18_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE18` writer - Cancellation Finished Interrupt Enable 18"] +pub struct CFIE18_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE18_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `CFIE19` reader - Cancellation Finished Interrupt Enable 19"] +pub struct CFIE19_R(crate::FieldReader); +impl CFIE19_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE19_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE19_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE19` writer - Cancellation Finished Interrupt Enable 19"] +pub struct CFIE19_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE19_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `CFIE20` reader - Cancellation Finished Interrupt Enable 20"] +pub struct CFIE20_R(crate::FieldReader); +impl CFIE20_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE20_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE20_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE20` writer - Cancellation Finished Interrupt Enable 20"] +pub struct CFIE20_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE20_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `CFIE21` reader - Cancellation Finished Interrupt Enable 21"] +pub struct CFIE21_R(crate::FieldReader); +impl CFIE21_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE21_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE21_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE21` writer - Cancellation Finished Interrupt Enable 21"] +pub struct CFIE21_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE21_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `CFIE22` reader - Cancellation Finished Interrupt Enable 22"] +pub struct CFIE22_R(crate::FieldReader); +impl CFIE22_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE22_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE22_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE22` writer - Cancellation Finished Interrupt Enable 22"] +pub struct CFIE22_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE22_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `CFIE23` reader - Cancellation Finished Interrupt Enable 23"] +pub struct CFIE23_R(crate::FieldReader); +impl CFIE23_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE23_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE23_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE23` writer - Cancellation Finished Interrupt Enable 23"] +pub struct CFIE23_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE23_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `CFIE24` reader - Cancellation Finished Interrupt Enable 24"] +pub struct CFIE24_R(crate::FieldReader); +impl CFIE24_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE24_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE24_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE24` writer - Cancellation Finished Interrupt Enable 24"] +pub struct CFIE24_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE24_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `CFIE25` reader - Cancellation Finished Interrupt Enable 25"] +pub struct CFIE25_R(crate::FieldReader); +impl CFIE25_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE25_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE25_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE25` writer - Cancellation Finished Interrupt Enable 25"] +pub struct CFIE25_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE25_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `CFIE26` reader - Cancellation Finished Interrupt Enable 26"] +pub struct CFIE26_R(crate::FieldReader); +impl CFIE26_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE26_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE26_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE26` writer - Cancellation Finished Interrupt Enable 26"] +pub struct CFIE26_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE26_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `CFIE27` reader - Cancellation Finished Interrupt Enable 27"] +pub struct CFIE27_R(crate::FieldReader); +impl CFIE27_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE27_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE27_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE27` writer - Cancellation Finished Interrupt Enable 27"] +pub struct CFIE27_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE27_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +#[doc = "Field `CFIE28` reader - Cancellation Finished Interrupt Enable 28"] +pub struct CFIE28_R(crate::FieldReader); +impl CFIE28_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE28_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE28_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE28` writer - Cancellation Finished Interrupt Enable 28"] +pub struct CFIE28_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE28_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Field `CFIE29` reader - Cancellation Finished Interrupt Enable 29"] +pub struct CFIE29_R(crate::FieldReader); +impl CFIE29_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE29_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE29_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE29` writer - Cancellation Finished Interrupt Enable 29"] +pub struct CFIE29_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE29_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29); + self.w + } +} +#[doc = "Field `CFIE30` reader - Cancellation Finished Interrupt Enable 30"] +pub struct CFIE30_R(crate::FieldReader); +impl CFIE30_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE30_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE30_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE30` writer - Cancellation Finished Interrupt Enable 30"] +pub struct CFIE30_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE30_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +#[doc = "Field `CFIE31` reader - Cancellation Finished Interrupt Enable 31"] +pub struct CFIE31_R(crate::FieldReader); +impl CFIE31_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE31_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE31_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE31` writer - Cancellation Finished Interrupt Enable 31"] +pub struct CFIE31_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE31_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bit 0 - Cancellation Finished Interrupt Enable 0"] + #[inline(always)] + pub fn cfie0(&self) -> CFIE0_R { + CFIE0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Cancellation Finished Interrupt Enable 1"] + #[inline(always)] + pub fn cfie1(&self) -> CFIE1_R { + CFIE1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Cancellation Finished Interrupt Enable 2"] + #[inline(always)] + pub fn cfie2(&self) -> CFIE2_R { + CFIE2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Cancellation Finished Interrupt Enable 3"] + #[inline(always)] + pub fn cfie3(&self) -> CFIE3_R { + CFIE3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Cancellation Finished Interrupt Enable 4"] + #[inline(always)] + pub fn cfie4(&self) -> CFIE4_R { + CFIE4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Cancellation Finished Interrupt Enable 5"] + #[inline(always)] + pub fn cfie5(&self) -> CFIE5_R { + CFIE5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Cancellation Finished Interrupt Enable 6"] + #[inline(always)] + pub fn cfie6(&self) -> CFIE6_R { + CFIE6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Cancellation Finished Interrupt Enable 7"] + #[inline(always)] + pub fn cfie7(&self) -> CFIE7_R { + CFIE7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Cancellation Finished Interrupt Enable 8"] + #[inline(always)] + pub fn cfie8(&self) -> CFIE8_R { + CFIE8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Cancellation Finished Interrupt Enable 9"] + #[inline(always)] + pub fn cfie9(&self) -> CFIE9_R { + CFIE9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Cancellation Finished Interrupt Enable 10"] + #[inline(always)] + pub fn cfie10(&self) -> CFIE10_R { + CFIE10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Cancellation Finished Interrupt Enable 11"] + #[inline(always)] + pub fn cfie11(&self) -> CFIE11_R { + CFIE11_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Cancellation Finished Interrupt Enable 12"] + #[inline(always)] + pub fn cfie12(&self) -> CFIE12_R { + CFIE12_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Cancellation Finished Interrupt Enable 13"] + #[inline(always)] + pub fn cfie13(&self) -> CFIE13_R { + CFIE13_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Cancellation Finished Interrupt Enable 14"] + #[inline(always)] + pub fn cfie14(&self) -> CFIE14_R { + CFIE14_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Cancellation Finished Interrupt Enable 15"] + #[inline(always)] + pub fn cfie15(&self) -> CFIE15_R { + CFIE15_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Cancellation Finished Interrupt Enable 16"] + #[inline(always)] + pub fn cfie16(&self) -> CFIE16_R { + CFIE16_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Cancellation Finished Interrupt Enable 17"] + #[inline(always)] + pub fn cfie17(&self) -> CFIE17_R { + CFIE17_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Cancellation Finished Interrupt Enable 18"] + #[inline(always)] + pub fn cfie18(&self) -> CFIE18_R { + CFIE18_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Cancellation Finished Interrupt Enable 19"] + #[inline(always)] + pub fn cfie19(&self) -> CFIE19_R { + CFIE19_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Cancellation Finished Interrupt Enable 20"] + #[inline(always)] + pub fn cfie20(&self) -> CFIE20_R { + CFIE20_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Cancellation Finished Interrupt Enable 21"] + #[inline(always)] + pub fn cfie21(&self) -> CFIE21_R { + CFIE21_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Cancellation Finished Interrupt Enable 22"] + #[inline(always)] + pub fn cfie22(&self) -> CFIE22_R { + CFIE22_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Cancellation Finished Interrupt Enable 23"] + #[inline(always)] + pub fn cfie23(&self) -> CFIE23_R { + CFIE23_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24 - Cancellation Finished Interrupt Enable 24"] + #[inline(always)] + pub fn cfie24(&self) -> CFIE24_R { + CFIE24_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Cancellation Finished Interrupt Enable 25"] + #[inline(always)] + pub fn cfie25(&self) -> CFIE25_R { + CFIE25_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Cancellation Finished Interrupt Enable 26"] + #[inline(always)] + pub fn cfie26(&self) -> CFIE26_R { + CFIE26_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Cancellation Finished Interrupt Enable 27"] + #[inline(always)] + pub fn cfie27(&self) -> CFIE27_R { + CFIE27_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28 - Cancellation Finished Interrupt Enable 28"] + #[inline(always)] + pub fn cfie28(&self) -> CFIE28_R { + CFIE28_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Cancellation Finished Interrupt Enable 29"] + #[inline(always)] + pub fn cfie29(&self) -> CFIE29_R { + CFIE29_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - Cancellation Finished Interrupt Enable 30"] + #[inline(always)] + pub fn cfie30(&self) -> CFIE30_R { + CFIE30_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 31 - Cancellation Finished Interrupt Enable 31"] + #[inline(always)] + pub fn cfie31(&self) -> CFIE31_R { + CFIE31_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Cancellation Finished Interrupt Enable 0"] + #[inline(always)] + pub fn cfie0(&mut self) -> CFIE0_W { + CFIE0_W { w: self } + } + #[doc = "Bit 1 - Cancellation Finished Interrupt Enable 1"] + #[inline(always)] + pub fn cfie1(&mut self) -> CFIE1_W { + CFIE1_W { w: self } + } + #[doc = "Bit 2 - Cancellation Finished Interrupt Enable 2"] + #[inline(always)] + pub fn cfie2(&mut self) -> CFIE2_W { + CFIE2_W { w: self } + } + #[doc = "Bit 3 - Cancellation Finished Interrupt Enable 3"] + #[inline(always)] + pub fn cfie3(&mut self) -> CFIE3_W { + CFIE3_W { w: self } + } + #[doc = "Bit 4 - Cancellation Finished Interrupt Enable 4"] + #[inline(always)] + pub fn cfie4(&mut self) -> CFIE4_W { + CFIE4_W { w: self } + } + #[doc = "Bit 5 - Cancellation Finished Interrupt Enable 5"] + #[inline(always)] + pub fn cfie5(&mut self) -> CFIE5_W { + CFIE5_W { w: self } + } + #[doc = "Bit 6 - Cancellation Finished Interrupt Enable 6"] + #[inline(always)] + pub fn cfie6(&mut self) -> CFIE6_W { + CFIE6_W { w: self } + } + #[doc = "Bit 7 - Cancellation Finished Interrupt Enable 7"] + #[inline(always)] + pub fn cfie7(&mut self) -> CFIE7_W { + CFIE7_W { w: self } + } + #[doc = "Bit 8 - Cancellation Finished Interrupt Enable 8"] + #[inline(always)] + pub fn cfie8(&mut self) -> CFIE8_W { + CFIE8_W { w: self } + } + #[doc = "Bit 9 - Cancellation Finished Interrupt Enable 9"] + #[inline(always)] + pub fn cfie9(&mut self) -> CFIE9_W { + CFIE9_W { w: self } + } + #[doc = "Bit 10 - Cancellation Finished Interrupt Enable 10"] + #[inline(always)] + pub fn cfie10(&mut self) -> CFIE10_W { + CFIE10_W { w: self } + } + #[doc = "Bit 11 - Cancellation Finished Interrupt Enable 11"] + #[inline(always)] + pub fn cfie11(&mut self) -> CFIE11_W { + CFIE11_W { w: self } + } + #[doc = "Bit 12 - Cancellation Finished Interrupt Enable 12"] + #[inline(always)] + pub fn cfie12(&mut self) -> CFIE12_W { + CFIE12_W { w: self } + } + #[doc = "Bit 13 - Cancellation Finished Interrupt Enable 13"] + #[inline(always)] + pub fn cfie13(&mut self) -> CFIE13_W { + CFIE13_W { w: self } + } + #[doc = "Bit 14 - Cancellation Finished Interrupt Enable 14"] + #[inline(always)] + pub fn cfie14(&mut self) -> CFIE14_W { + CFIE14_W { w: self } + } + #[doc = "Bit 15 - Cancellation Finished Interrupt Enable 15"] + #[inline(always)] + pub fn cfie15(&mut self) -> CFIE15_W { + CFIE15_W { w: self } + } + #[doc = "Bit 16 - Cancellation Finished Interrupt Enable 16"] + #[inline(always)] + pub fn cfie16(&mut self) -> CFIE16_W { + CFIE16_W { w: self } + } + #[doc = "Bit 17 - Cancellation Finished Interrupt Enable 17"] + #[inline(always)] + pub fn cfie17(&mut self) -> CFIE17_W { + CFIE17_W { w: self } + } + #[doc = "Bit 18 - Cancellation Finished Interrupt Enable 18"] + #[inline(always)] + pub fn cfie18(&mut self) -> CFIE18_W { + CFIE18_W { w: self } + } + #[doc = "Bit 19 - Cancellation Finished Interrupt Enable 19"] + #[inline(always)] + pub fn cfie19(&mut self) -> CFIE19_W { + CFIE19_W { w: self } + } + #[doc = "Bit 20 - Cancellation Finished Interrupt Enable 20"] + #[inline(always)] + pub fn cfie20(&mut self) -> CFIE20_W { + CFIE20_W { w: self } + } + #[doc = "Bit 21 - Cancellation Finished Interrupt Enable 21"] + #[inline(always)] + pub fn cfie21(&mut self) -> CFIE21_W { + CFIE21_W { w: self } + } + #[doc = "Bit 22 - Cancellation Finished Interrupt Enable 22"] + #[inline(always)] + pub fn cfie22(&mut self) -> CFIE22_W { + CFIE22_W { w: self } + } + #[doc = "Bit 23 - Cancellation Finished Interrupt Enable 23"] + #[inline(always)] + pub fn cfie23(&mut self) -> CFIE23_W { + CFIE23_W { w: self } + } + #[doc = "Bit 24 - Cancellation Finished Interrupt Enable 24"] + #[inline(always)] + pub fn cfie24(&mut self) -> CFIE24_W { + CFIE24_W { w: self } + } + #[doc = "Bit 25 - Cancellation Finished Interrupt Enable 25"] + #[inline(always)] + pub fn cfie25(&mut self) -> CFIE25_W { + CFIE25_W { w: self } + } + #[doc = "Bit 26 - Cancellation Finished Interrupt Enable 26"] + #[inline(always)] + pub fn cfie26(&mut self) -> CFIE26_W { + CFIE26_W { w: self } + } + #[doc = "Bit 27 - Cancellation Finished Interrupt Enable 27"] + #[inline(always)] + pub fn cfie27(&mut self) -> CFIE27_W { + CFIE27_W { w: self } + } + #[doc = "Bit 28 - Cancellation Finished Interrupt Enable 28"] + #[inline(always)] + pub fn cfie28(&mut self) -> CFIE28_W { + CFIE28_W { w: self } + } + #[doc = "Bit 29 - Cancellation Finished Interrupt Enable 29"] + #[inline(always)] + pub fn cfie29(&mut self) -> CFIE29_W { + CFIE29_W { w: self } + } + #[doc = "Bit 30 - Cancellation Finished Interrupt Enable 30"] + #[inline(always)] + pub fn cfie30(&mut self) -> CFIE30_W { + CFIE30_W { w: self } + } + #[doc = "Bit 31 - Cancellation Finished Interrupt Enable 31"] + #[inline(always)] + pub fn cfie31(&mut self) -> CFIE31_W { + CFIE31_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Tx Buffer Cancellation Finished Interrupt Enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txbcie](index.html) module"] +pub struct TXBCIE_SPEC; +impl crate::RegisterSpec for TXBCIE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [txbcie::R](R) reader structure"] +impl crate::Readable for TXBCIE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [txbcie::W](W) writer structure"] +impl crate::Writable for TXBCIE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TXBCIE to value 0"] +impl crate::Resettable for TXBCIE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/can0/txbcr.rs b/pac/atsamc21e/src/can0/txbcr.rs new file mode 100644 index 000000000000..e5d0e61de8c9 --- /dev/null +++ b/pac/atsamc21e/src/can0/txbcr.rs @@ -0,0 +1,1570 @@ +#[doc = "Register `TXBCR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TXBCR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CR0` reader - Cancellation Request 0"] +pub struct CR0_R(crate::FieldReader); +impl CR0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR0` writer - Cancellation Request 0"] +pub struct CR0_W<'a> { + w: &'a mut W, +} +impl<'a> CR0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `CR1` reader - Cancellation Request 1"] +pub struct CR1_R(crate::FieldReader); +impl CR1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR1` writer - Cancellation Request 1"] +pub struct CR1_W<'a> { + w: &'a mut W, +} +impl<'a> CR1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CR2` reader - Cancellation Request 2"] +pub struct CR2_R(crate::FieldReader); +impl CR2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR2` writer - Cancellation Request 2"] +pub struct CR2_W<'a> { + w: &'a mut W, +} +impl<'a> CR2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CR3` reader - Cancellation Request 3"] +pub struct CR3_R(crate::FieldReader); +impl CR3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR3` writer - Cancellation Request 3"] +pub struct CR3_W<'a> { + w: &'a mut W, +} +impl<'a> CR3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CR4` reader - Cancellation Request 4"] +pub struct CR4_R(crate::FieldReader); +impl CR4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR4` writer - Cancellation Request 4"] +pub struct CR4_W<'a> { + w: &'a mut W, +} +impl<'a> CR4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `CR5` reader - Cancellation Request 5"] +pub struct CR5_R(crate::FieldReader); +impl CR5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR5` writer - Cancellation Request 5"] +pub struct CR5_W<'a> { + w: &'a mut W, +} +impl<'a> CR5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `CR6` reader - Cancellation Request 6"] +pub struct CR6_R(crate::FieldReader); +impl CR6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR6` writer - Cancellation Request 6"] +pub struct CR6_W<'a> { + w: &'a mut W, +} +impl<'a> CR6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `CR7` reader - Cancellation Request 7"] +pub struct CR7_R(crate::FieldReader); +impl CR7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR7` writer - Cancellation Request 7"] +pub struct CR7_W<'a> { + w: &'a mut W, +} +impl<'a> CR7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CR8` reader - Cancellation Request 8"] +pub struct CR8_R(crate::FieldReader); +impl CR8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR8` writer - Cancellation Request 8"] +pub struct CR8_W<'a> { + w: &'a mut W, +} +impl<'a> CR8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `CR9` reader - Cancellation Request 9"] +pub struct CR9_R(crate::FieldReader); +impl CR9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR9` writer - Cancellation Request 9"] +pub struct CR9_W<'a> { + w: &'a mut W, +} +impl<'a> CR9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `CR10` reader - Cancellation Request 10"] +pub struct CR10_R(crate::FieldReader); +impl CR10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR10` writer - Cancellation Request 10"] +pub struct CR10_W<'a> { + w: &'a mut W, +} +impl<'a> CR10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `CR11` reader - Cancellation Request 11"] +pub struct CR11_R(crate::FieldReader); +impl CR11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR11` writer - Cancellation Request 11"] +pub struct CR11_W<'a> { + w: &'a mut W, +} +impl<'a> CR11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `CR12` reader - Cancellation Request 12"] +pub struct CR12_R(crate::FieldReader); +impl CR12_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR12_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR12_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR12` writer - Cancellation Request 12"] +pub struct CR12_W<'a> { + w: &'a mut W, +} +impl<'a> CR12_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `CR13` reader - Cancellation Request 13"] +pub struct CR13_R(crate::FieldReader); +impl CR13_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR13_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR13_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR13` writer - Cancellation Request 13"] +pub struct CR13_W<'a> { + w: &'a mut W, +} +impl<'a> CR13_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `CR14` reader - Cancellation Request 14"] +pub struct CR14_R(crate::FieldReader); +impl CR14_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR14_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR14_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR14` writer - Cancellation Request 14"] +pub struct CR14_W<'a> { + w: &'a mut W, +} +impl<'a> CR14_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `CR15` reader - Cancellation Request 15"] +pub struct CR15_R(crate::FieldReader); +impl CR15_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR15_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR15_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR15` writer - Cancellation Request 15"] +pub struct CR15_W<'a> { + w: &'a mut W, +} +impl<'a> CR15_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `CR16` reader - Cancellation Request 16"] +pub struct CR16_R(crate::FieldReader); +impl CR16_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR16_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR16_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR16` writer - Cancellation Request 16"] +pub struct CR16_W<'a> { + w: &'a mut W, +} +impl<'a> CR16_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `CR17` reader - Cancellation Request 17"] +pub struct CR17_R(crate::FieldReader); +impl CR17_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR17_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR17_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR17` writer - Cancellation Request 17"] +pub struct CR17_W<'a> { + w: &'a mut W, +} +impl<'a> CR17_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `CR18` reader - Cancellation Request 18"] +pub struct CR18_R(crate::FieldReader); +impl CR18_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR18_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR18_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR18` writer - Cancellation Request 18"] +pub struct CR18_W<'a> { + w: &'a mut W, +} +impl<'a> CR18_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `CR19` reader - Cancellation Request 19"] +pub struct CR19_R(crate::FieldReader); +impl CR19_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR19_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR19_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR19` writer - Cancellation Request 19"] +pub struct CR19_W<'a> { + w: &'a mut W, +} +impl<'a> CR19_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `CR20` reader - Cancellation Request 20"] +pub struct CR20_R(crate::FieldReader); +impl CR20_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR20_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR20_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR20` writer - Cancellation Request 20"] +pub struct CR20_W<'a> { + w: &'a mut W, +} +impl<'a> CR20_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `CR21` reader - Cancellation Request 21"] +pub struct CR21_R(crate::FieldReader); +impl CR21_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR21_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR21_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR21` writer - Cancellation Request 21"] +pub struct CR21_W<'a> { + w: &'a mut W, +} +impl<'a> CR21_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `CR22` reader - Cancellation Request 22"] +pub struct CR22_R(crate::FieldReader); +impl CR22_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR22_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR22_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR22` writer - Cancellation Request 22"] +pub struct CR22_W<'a> { + w: &'a mut W, +} +impl<'a> CR22_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `CR23` reader - Cancellation Request 23"] +pub struct CR23_R(crate::FieldReader); +impl CR23_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR23_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR23_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR23` writer - Cancellation Request 23"] +pub struct CR23_W<'a> { + w: &'a mut W, +} +impl<'a> CR23_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `CR24` reader - Cancellation Request 24"] +pub struct CR24_R(crate::FieldReader); +impl CR24_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR24_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR24_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR24` writer - Cancellation Request 24"] +pub struct CR24_W<'a> { + w: &'a mut W, +} +impl<'a> CR24_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `CR25` reader - Cancellation Request 25"] +pub struct CR25_R(crate::FieldReader); +impl CR25_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR25_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR25_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR25` writer - Cancellation Request 25"] +pub struct CR25_W<'a> { + w: &'a mut W, +} +impl<'a> CR25_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `CR26` reader - Cancellation Request 26"] +pub struct CR26_R(crate::FieldReader); +impl CR26_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR26_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR26_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR26` writer - Cancellation Request 26"] +pub struct CR26_W<'a> { + w: &'a mut W, +} +impl<'a> CR26_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `CR27` reader - Cancellation Request 27"] +pub struct CR27_R(crate::FieldReader); +impl CR27_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR27_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR27_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR27` writer - Cancellation Request 27"] +pub struct CR27_W<'a> { + w: &'a mut W, +} +impl<'a> CR27_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +#[doc = "Field `CR28` reader - Cancellation Request 28"] +pub struct CR28_R(crate::FieldReader); +impl CR28_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR28_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR28_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR28` writer - Cancellation Request 28"] +pub struct CR28_W<'a> { + w: &'a mut W, +} +impl<'a> CR28_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Field `CR29` reader - Cancellation Request 29"] +pub struct CR29_R(crate::FieldReader); +impl CR29_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR29_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR29_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR29` writer - Cancellation Request 29"] +pub struct CR29_W<'a> { + w: &'a mut W, +} +impl<'a> CR29_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29); + self.w + } +} +#[doc = "Field `CR30` reader - Cancellation Request 30"] +pub struct CR30_R(crate::FieldReader); +impl CR30_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR30_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR30_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR30` writer - Cancellation Request 30"] +pub struct CR30_W<'a> { + w: &'a mut W, +} +impl<'a> CR30_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +#[doc = "Field `CR31` reader - Cancellation Request 31"] +pub struct CR31_R(crate::FieldReader); +impl CR31_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR31_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR31_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR31` writer - Cancellation Request 31"] +pub struct CR31_W<'a> { + w: &'a mut W, +} +impl<'a> CR31_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bit 0 - Cancellation Request 0"] + #[inline(always)] + pub fn cr0(&self) -> CR0_R { + CR0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Cancellation Request 1"] + #[inline(always)] + pub fn cr1(&self) -> CR1_R { + CR1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Cancellation Request 2"] + #[inline(always)] + pub fn cr2(&self) -> CR2_R { + CR2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Cancellation Request 3"] + #[inline(always)] + pub fn cr3(&self) -> CR3_R { + CR3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Cancellation Request 4"] + #[inline(always)] + pub fn cr4(&self) -> CR4_R { + CR4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Cancellation Request 5"] + #[inline(always)] + pub fn cr5(&self) -> CR5_R { + CR5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Cancellation Request 6"] + #[inline(always)] + pub fn cr6(&self) -> CR6_R { + CR6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Cancellation Request 7"] + #[inline(always)] + pub fn cr7(&self) -> CR7_R { + CR7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Cancellation Request 8"] + #[inline(always)] + pub fn cr8(&self) -> CR8_R { + CR8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Cancellation Request 9"] + #[inline(always)] + pub fn cr9(&self) -> CR9_R { + CR9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Cancellation Request 10"] + #[inline(always)] + pub fn cr10(&self) -> CR10_R { + CR10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Cancellation Request 11"] + #[inline(always)] + pub fn cr11(&self) -> CR11_R { + CR11_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Cancellation Request 12"] + #[inline(always)] + pub fn cr12(&self) -> CR12_R { + CR12_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Cancellation Request 13"] + #[inline(always)] + pub fn cr13(&self) -> CR13_R { + CR13_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Cancellation Request 14"] + #[inline(always)] + pub fn cr14(&self) -> CR14_R { + CR14_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Cancellation Request 15"] + #[inline(always)] + pub fn cr15(&self) -> CR15_R { + CR15_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Cancellation Request 16"] + #[inline(always)] + pub fn cr16(&self) -> CR16_R { + CR16_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Cancellation Request 17"] + #[inline(always)] + pub fn cr17(&self) -> CR17_R { + CR17_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Cancellation Request 18"] + #[inline(always)] + pub fn cr18(&self) -> CR18_R { + CR18_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Cancellation Request 19"] + #[inline(always)] + pub fn cr19(&self) -> CR19_R { + CR19_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Cancellation Request 20"] + #[inline(always)] + pub fn cr20(&self) -> CR20_R { + CR20_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Cancellation Request 21"] + #[inline(always)] + pub fn cr21(&self) -> CR21_R { + CR21_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Cancellation Request 22"] + #[inline(always)] + pub fn cr22(&self) -> CR22_R { + CR22_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Cancellation Request 23"] + #[inline(always)] + pub fn cr23(&self) -> CR23_R { + CR23_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24 - Cancellation Request 24"] + #[inline(always)] + pub fn cr24(&self) -> CR24_R { + CR24_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Cancellation Request 25"] + #[inline(always)] + pub fn cr25(&self) -> CR25_R { + CR25_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Cancellation Request 26"] + #[inline(always)] + pub fn cr26(&self) -> CR26_R { + CR26_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Cancellation Request 27"] + #[inline(always)] + pub fn cr27(&self) -> CR27_R { + CR27_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28 - Cancellation Request 28"] + #[inline(always)] + pub fn cr28(&self) -> CR28_R { + CR28_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Cancellation Request 29"] + #[inline(always)] + pub fn cr29(&self) -> CR29_R { + CR29_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - Cancellation Request 30"] + #[inline(always)] + pub fn cr30(&self) -> CR30_R { + CR30_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 31 - Cancellation Request 31"] + #[inline(always)] + pub fn cr31(&self) -> CR31_R { + CR31_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Cancellation Request 0"] + #[inline(always)] + pub fn cr0(&mut self) -> CR0_W { + CR0_W { w: self } + } + #[doc = "Bit 1 - Cancellation Request 1"] + #[inline(always)] + pub fn cr1(&mut self) -> CR1_W { + CR1_W { w: self } + } + #[doc = "Bit 2 - Cancellation Request 2"] + #[inline(always)] + pub fn cr2(&mut self) -> CR2_W { + CR2_W { w: self } + } + #[doc = "Bit 3 - Cancellation Request 3"] + #[inline(always)] + pub fn cr3(&mut self) -> CR3_W { + CR3_W { w: self } + } + #[doc = "Bit 4 - Cancellation Request 4"] + #[inline(always)] + pub fn cr4(&mut self) -> CR4_W { + CR4_W { w: self } + } + #[doc = "Bit 5 - Cancellation Request 5"] + #[inline(always)] + pub fn cr5(&mut self) -> CR5_W { + CR5_W { w: self } + } + #[doc = "Bit 6 - Cancellation Request 6"] + #[inline(always)] + pub fn cr6(&mut self) -> CR6_W { + CR6_W { w: self } + } + #[doc = "Bit 7 - Cancellation Request 7"] + #[inline(always)] + pub fn cr7(&mut self) -> CR7_W { + CR7_W { w: self } + } + #[doc = "Bit 8 - Cancellation Request 8"] + #[inline(always)] + pub fn cr8(&mut self) -> CR8_W { + CR8_W { w: self } + } + #[doc = "Bit 9 - Cancellation Request 9"] + #[inline(always)] + pub fn cr9(&mut self) -> CR9_W { + CR9_W { w: self } + } + #[doc = "Bit 10 - Cancellation Request 10"] + #[inline(always)] + pub fn cr10(&mut self) -> CR10_W { + CR10_W { w: self } + } + #[doc = "Bit 11 - Cancellation Request 11"] + #[inline(always)] + pub fn cr11(&mut self) -> CR11_W { + CR11_W { w: self } + } + #[doc = "Bit 12 - Cancellation Request 12"] + #[inline(always)] + pub fn cr12(&mut self) -> CR12_W { + CR12_W { w: self } + } + #[doc = "Bit 13 - Cancellation Request 13"] + #[inline(always)] + pub fn cr13(&mut self) -> CR13_W { + CR13_W { w: self } + } + #[doc = "Bit 14 - Cancellation Request 14"] + #[inline(always)] + pub fn cr14(&mut self) -> CR14_W { + CR14_W { w: self } + } + #[doc = "Bit 15 - Cancellation Request 15"] + #[inline(always)] + pub fn cr15(&mut self) -> CR15_W { + CR15_W { w: self } + } + #[doc = "Bit 16 - Cancellation Request 16"] + #[inline(always)] + pub fn cr16(&mut self) -> CR16_W { + CR16_W { w: self } + } + #[doc = "Bit 17 - Cancellation Request 17"] + #[inline(always)] + pub fn cr17(&mut self) -> CR17_W { + CR17_W { w: self } + } + #[doc = "Bit 18 - Cancellation Request 18"] + #[inline(always)] + pub fn cr18(&mut self) -> CR18_W { + CR18_W { w: self } + } + #[doc = "Bit 19 - Cancellation Request 19"] + #[inline(always)] + pub fn cr19(&mut self) -> CR19_W { + CR19_W { w: self } + } + #[doc = "Bit 20 - Cancellation Request 20"] + #[inline(always)] + pub fn cr20(&mut self) -> CR20_W { + CR20_W { w: self } + } + #[doc = "Bit 21 - Cancellation Request 21"] + #[inline(always)] + pub fn cr21(&mut self) -> CR21_W { + CR21_W { w: self } + } + #[doc = "Bit 22 - Cancellation Request 22"] + #[inline(always)] + pub fn cr22(&mut self) -> CR22_W { + CR22_W { w: self } + } + #[doc = "Bit 23 - Cancellation Request 23"] + #[inline(always)] + pub fn cr23(&mut self) -> CR23_W { + CR23_W { w: self } + } + #[doc = "Bit 24 - Cancellation Request 24"] + #[inline(always)] + pub fn cr24(&mut self) -> CR24_W { + CR24_W { w: self } + } + #[doc = "Bit 25 - Cancellation Request 25"] + #[inline(always)] + pub fn cr25(&mut self) -> CR25_W { + CR25_W { w: self } + } + #[doc = "Bit 26 - Cancellation Request 26"] + #[inline(always)] + pub fn cr26(&mut self) -> CR26_W { + CR26_W { w: self } + } + #[doc = "Bit 27 - Cancellation Request 27"] + #[inline(always)] + pub fn cr27(&mut self) -> CR27_W { + CR27_W { w: self } + } + #[doc = "Bit 28 - Cancellation Request 28"] + #[inline(always)] + pub fn cr28(&mut self) -> CR28_W { + CR28_W { w: self } + } + #[doc = "Bit 29 - Cancellation Request 29"] + #[inline(always)] + pub fn cr29(&mut self) -> CR29_W { + CR29_W { w: self } + } + #[doc = "Bit 30 - Cancellation Request 30"] + #[inline(always)] + pub fn cr30(&mut self) -> CR30_W { + CR30_W { w: self } + } + #[doc = "Bit 31 - Cancellation Request 31"] + #[inline(always)] + pub fn cr31(&mut self) -> CR31_W { + CR31_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Tx Buffer Cancellation Request\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txbcr](index.html) module"] +pub struct TXBCR_SPEC; +impl crate::RegisterSpec for TXBCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [txbcr::R](R) reader structure"] +impl crate::Readable for TXBCR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [txbcr::W](W) writer structure"] +impl crate::Writable for TXBCR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TXBCR to value 0"] +impl crate::Resettable for TXBCR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/can0/txbrp.rs b/pac/atsamc21e/src/can0/txbrp.rs new file mode 100644 index 000000000000..9be5da39419d --- /dev/null +++ b/pac/atsamc21e/src/can0/txbrp.rs @@ -0,0 +1,673 @@ +#[doc = "Register `TXBRP` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `TRP0` reader - Transmission Request Pending 0"] +pub struct TRP0_R(crate::FieldReader); +impl TRP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP1` reader - Transmission Request Pending 1"] +pub struct TRP1_R(crate::FieldReader); +impl TRP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP2` reader - Transmission Request Pending 2"] +pub struct TRP2_R(crate::FieldReader); +impl TRP2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP3` reader - Transmission Request Pending 3"] +pub struct TRP3_R(crate::FieldReader); +impl TRP3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP4` reader - Transmission Request Pending 4"] +pub struct TRP4_R(crate::FieldReader); +impl TRP4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP5` reader - Transmission Request Pending 5"] +pub struct TRP5_R(crate::FieldReader); +impl TRP5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP6` reader - Transmission Request Pending 6"] +pub struct TRP6_R(crate::FieldReader); +impl TRP6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP7` reader - Transmission Request Pending 7"] +pub struct TRP7_R(crate::FieldReader); +impl TRP7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP8` reader - Transmission Request Pending 8"] +pub struct TRP8_R(crate::FieldReader); +impl TRP8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP9` reader - Transmission Request Pending 9"] +pub struct TRP9_R(crate::FieldReader); +impl TRP9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP10` reader - Transmission Request Pending 10"] +pub struct TRP10_R(crate::FieldReader); +impl TRP10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP11` reader - Transmission Request Pending 11"] +pub struct TRP11_R(crate::FieldReader); +impl TRP11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP12` reader - Transmission Request Pending 12"] +pub struct TRP12_R(crate::FieldReader); +impl TRP12_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP12_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP12_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP13` reader - Transmission Request Pending 13"] +pub struct TRP13_R(crate::FieldReader); +impl TRP13_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP13_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP13_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP14` reader - Transmission Request Pending 14"] +pub struct TRP14_R(crate::FieldReader); +impl TRP14_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP14_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP14_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP15` reader - Transmission Request Pending 15"] +pub struct TRP15_R(crate::FieldReader); +impl TRP15_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP15_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP15_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP16` reader - Transmission Request Pending 16"] +pub struct TRP16_R(crate::FieldReader); +impl TRP16_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP16_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP16_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP17` reader - Transmission Request Pending 17"] +pub struct TRP17_R(crate::FieldReader); +impl TRP17_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP17_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP17_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP18` reader - Transmission Request Pending 18"] +pub struct TRP18_R(crate::FieldReader); +impl TRP18_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP18_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP18_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP19` reader - Transmission Request Pending 19"] +pub struct TRP19_R(crate::FieldReader); +impl TRP19_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP19_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP19_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP20` reader - Transmission Request Pending 20"] +pub struct TRP20_R(crate::FieldReader); +impl TRP20_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP20_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP20_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP21` reader - Transmission Request Pending 21"] +pub struct TRP21_R(crate::FieldReader); +impl TRP21_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP21_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP21_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP22` reader - Transmission Request Pending 22"] +pub struct TRP22_R(crate::FieldReader); +impl TRP22_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP22_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP22_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP23` reader - Transmission Request Pending 23"] +pub struct TRP23_R(crate::FieldReader); +impl TRP23_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP23_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP23_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP24` reader - Transmission Request Pending 24"] +pub struct TRP24_R(crate::FieldReader); +impl TRP24_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP24_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP24_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP25` reader - Transmission Request Pending 25"] +pub struct TRP25_R(crate::FieldReader); +impl TRP25_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP25_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP25_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP26` reader - Transmission Request Pending 26"] +pub struct TRP26_R(crate::FieldReader); +impl TRP26_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP26_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP26_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP27` reader - Transmission Request Pending 27"] +pub struct TRP27_R(crate::FieldReader); +impl TRP27_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP27_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP27_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP28` reader - Transmission Request Pending 28"] +pub struct TRP28_R(crate::FieldReader); +impl TRP28_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP28_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP28_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP29` reader - Transmission Request Pending 29"] +pub struct TRP29_R(crate::FieldReader); +impl TRP29_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP29_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP29_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP30` reader - Transmission Request Pending 30"] +pub struct TRP30_R(crate::FieldReader); +impl TRP30_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP30_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP30_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP31` reader - Transmission Request Pending 31"] +pub struct TRP31_R(crate::FieldReader); +impl TRP31_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP31_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP31_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Transmission Request Pending 0"] + #[inline(always)] + pub fn trp0(&self) -> TRP0_R { + TRP0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmission Request Pending 1"] + #[inline(always)] + pub fn trp1(&self) -> TRP1_R { + TRP1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Transmission Request Pending 2"] + #[inline(always)] + pub fn trp2(&self) -> TRP2_R { + TRP2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Transmission Request Pending 3"] + #[inline(always)] + pub fn trp3(&self) -> TRP3_R { + TRP3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Transmission Request Pending 4"] + #[inline(always)] + pub fn trp4(&self) -> TRP4_R { + TRP4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Transmission Request Pending 5"] + #[inline(always)] + pub fn trp5(&self) -> TRP5_R { + TRP5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Transmission Request Pending 6"] + #[inline(always)] + pub fn trp6(&self) -> TRP6_R { + TRP6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Transmission Request Pending 7"] + #[inline(always)] + pub fn trp7(&self) -> TRP7_R { + TRP7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Transmission Request Pending 8"] + #[inline(always)] + pub fn trp8(&self) -> TRP8_R { + TRP8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Transmission Request Pending 9"] + #[inline(always)] + pub fn trp9(&self) -> TRP9_R { + TRP9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Transmission Request Pending 10"] + #[inline(always)] + pub fn trp10(&self) -> TRP10_R { + TRP10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Transmission Request Pending 11"] + #[inline(always)] + pub fn trp11(&self) -> TRP11_R { + TRP11_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Transmission Request Pending 12"] + #[inline(always)] + pub fn trp12(&self) -> TRP12_R { + TRP12_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Transmission Request Pending 13"] + #[inline(always)] + pub fn trp13(&self) -> TRP13_R { + TRP13_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Transmission Request Pending 14"] + #[inline(always)] + pub fn trp14(&self) -> TRP14_R { + TRP14_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Transmission Request Pending 15"] + #[inline(always)] + pub fn trp15(&self) -> TRP15_R { + TRP15_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Transmission Request Pending 16"] + #[inline(always)] + pub fn trp16(&self) -> TRP16_R { + TRP16_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Transmission Request Pending 17"] + #[inline(always)] + pub fn trp17(&self) -> TRP17_R { + TRP17_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Transmission Request Pending 18"] + #[inline(always)] + pub fn trp18(&self) -> TRP18_R { + TRP18_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Transmission Request Pending 19"] + #[inline(always)] + pub fn trp19(&self) -> TRP19_R { + TRP19_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Transmission Request Pending 20"] + #[inline(always)] + pub fn trp20(&self) -> TRP20_R { + TRP20_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Transmission Request Pending 21"] + #[inline(always)] + pub fn trp21(&self) -> TRP21_R { + TRP21_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Transmission Request Pending 22"] + #[inline(always)] + pub fn trp22(&self) -> TRP22_R { + TRP22_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Transmission Request Pending 23"] + #[inline(always)] + pub fn trp23(&self) -> TRP23_R { + TRP23_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24 - Transmission Request Pending 24"] + #[inline(always)] + pub fn trp24(&self) -> TRP24_R { + TRP24_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Transmission Request Pending 25"] + #[inline(always)] + pub fn trp25(&self) -> TRP25_R { + TRP25_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Transmission Request Pending 26"] + #[inline(always)] + pub fn trp26(&self) -> TRP26_R { + TRP26_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Transmission Request Pending 27"] + #[inline(always)] + pub fn trp27(&self) -> TRP27_R { + TRP27_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28 - Transmission Request Pending 28"] + #[inline(always)] + pub fn trp28(&self) -> TRP28_R { + TRP28_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Transmission Request Pending 29"] + #[inline(always)] + pub fn trp29(&self) -> TRP29_R { + TRP29_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - Transmission Request Pending 30"] + #[inline(always)] + pub fn trp30(&self) -> TRP30_R { + TRP30_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 31 - Transmission Request Pending 31"] + #[inline(always)] + pub fn trp31(&self) -> TRP31_R { + TRP31_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +#[doc = "Tx Buffer Request Pending\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txbrp](index.html) module"] +pub struct TXBRP_SPEC; +impl crate::RegisterSpec for TXBRP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [txbrp::R](R) reader structure"] +impl crate::Readable for TXBRP_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets TXBRP to value 0"] +impl crate::Resettable for TXBRP_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/can0/txbtie.rs b/pac/atsamc21e/src/can0/txbtie.rs new file mode 100644 index 000000000000..ed808faba7a1 --- /dev/null +++ b/pac/atsamc21e/src/can0/txbtie.rs @@ -0,0 +1,1570 @@ +#[doc = "Register `TXBTIE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TXBTIE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TIE0` reader - Transmission Interrupt Enable 0"] +pub struct TIE0_R(crate::FieldReader); +impl TIE0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE0` writer - Transmission Interrupt Enable 0"] +pub struct TIE0_W<'a> { + w: &'a mut W, +} +impl<'a> TIE0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `TIE1` reader - Transmission Interrupt Enable 1"] +pub struct TIE1_R(crate::FieldReader); +impl TIE1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE1` writer - Transmission Interrupt Enable 1"] +pub struct TIE1_W<'a> { + w: &'a mut W, +} +impl<'a> TIE1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `TIE2` reader - Transmission Interrupt Enable 2"] +pub struct TIE2_R(crate::FieldReader); +impl TIE2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE2` writer - Transmission Interrupt Enable 2"] +pub struct TIE2_W<'a> { + w: &'a mut W, +} +impl<'a> TIE2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `TIE3` reader - Transmission Interrupt Enable 3"] +pub struct TIE3_R(crate::FieldReader); +impl TIE3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE3` writer - Transmission Interrupt Enable 3"] +pub struct TIE3_W<'a> { + w: &'a mut W, +} +impl<'a> TIE3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `TIE4` reader - Transmission Interrupt Enable 4"] +pub struct TIE4_R(crate::FieldReader); +impl TIE4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE4` writer - Transmission Interrupt Enable 4"] +pub struct TIE4_W<'a> { + w: &'a mut W, +} +impl<'a> TIE4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `TIE5` reader - Transmission Interrupt Enable 5"] +pub struct TIE5_R(crate::FieldReader); +impl TIE5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE5` writer - Transmission Interrupt Enable 5"] +pub struct TIE5_W<'a> { + w: &'a mut W, +} +impl<'a> TIE5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `TIE6` reader - Transmission Interrupt Enable 6"] +pub struct TIE6_R(crate::FieldReader); +impl TIE6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE6` writer - Transmission Interrupt Enable 6"] +pub struct TIE6_W<'a> { + w: &'a mut W, +} +impl<'a> TIE6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `TIE7` reader - Transmission Interrupt Enable 7"] +pub struct TIE7_R(crate::FieldReader); +impl TIE7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE7` writer - Transmission Interrupt Enable 7"] +pub struct TIE7_W<'a> { + w: &'a mut W, +} +impl<'a> TIE7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `TIE8` reader - Transmission Interrupt Enable 8"] +pub struct TIE8_R(crate::FieldReader); +impl TIE8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE8` writer - Transmission Interrupt Enable 8"] +pub struct TIE8_W<'a> { + w: &'a mut W, +} +impl<'a> TIE8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `TIE9` reader - Transmission Interrupt Enable 9"] +pub struct TIE9_R(crate::FieldReader); +impl TIE9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE9` writer - Transmission Interrupt Enable 9"] +pub struct TIE9_W<'a> { + w: &'a mut W, +} +impl<'a> TIE9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `TIE10` reader - Transmission Interrupt Enable 10"] +pub struct TIE10_R(crate::FieldReader); +impl TIE10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE10` writer - Transmission Interrupt Enable 10"] +pub struct TIE10_W<'a> { + w: &'a mut W, +} +impl<'a> TIE10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `TIE11` reader - Transmission Interrupt Enable 11"] +pub struct TIE11_R(crate::FieldReader); +impl TIE11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE11` writer - Transmission Interrupt Enable 11"] +pub struct TIE11_W<'a> { + w: &'a mut W, +} +impl<'a> TIE11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `TIE12` reader - Transmission Interrupt Enable 12"] +pub struct TIE12_R(crate::FieldReader); +impl TIE12_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE12_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE12_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE12` writer - Transmission Interrupt Enable 12"] +pub struct TIE12_W<'a> { + w: &'a mut W, +} +impl<'a> TIE12_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `TIE13` reader - Transmission Interrupt Enable 13"] +pub struct TIE13_R(crate::FieldReader); +impl TIE13_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE13_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE13_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE13` writer - Transmission Interrupt Enable 13"] +pub struct TIE13_W<'a> { + w: &'a mut W, +} +impl<'a> TIE13_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `TIE14` reader - Transmission Interrupt Enable 14"] +pub struct TIE14_R(crate::FieldReader); +impl TIE14_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE14_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE14_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE14` writer - Transmission Interrupt Enable 14"] +pub struct TIE14_W<'a> { + w: &'a mut W, +} +impl<'a> TIE14_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `TIE15` reader - Transmission Interrupt Enable 15"] +pub struct TIE15_R(crate::FieldReader); +impl TIE15_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE15_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE15_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE15` writer - Transmission Interrupt Enable 15"] +pub struct TIE15_W<'a> { + w: &'a mut W, +} +impl<'a> TIE15_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `TIE16` reader - Transmission Interrupt Enable 16"] +pub struct TIE16_R(crate::FieldReader); +impl TIE16_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE16_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE16_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE16` writer - Transmission Interrupt Enable 16"] +pub struct TIE16_W<'a> { + w: &'a mut W, +} +impl<'a> TIE16_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `TIE17` reader - Transmission Interrupt Enable 17"] +pub struct TIE17_R(crate::FieldReader); +impl TIE17_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE17_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE17_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE17` writer - Transmission Interrupt Enable 17"] +pub struct TIE17_W<'a> { + w: &'a mut W, +} +impl<'a> TIE17_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `TIE18` reader - Transmission Interrupt Enable 18"] +pub struct TIE18_R(crate::FieldReader); +impl TIE18_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE18_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE18_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE18` writer - Transmission Interrupt Enable 18"] +pub struct TIE18_W<'a> { + w: &'a mut W, +} +impl<'a> TIE18_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `TIE19` reader - Transmission Interrupt Enable 19"] +pub struct TIE19_R(crate::FieldReader); +impl TIE19_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE19_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE19_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE19` writer - Transmission Interrupt Enable 19"] +pub struct TIE19_W<'a> { + w: &'a mut W, +} +impl<'a> TIE19_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `TIE20` reader - Transmission Interrupt Enable 20"] +pub struct TIE20_R(crate::FieldReader); +impl TIE20_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE20_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE20_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE20` writer - Transmission Interrupt Enable 20"] +pub struct TIE20_W<'a> { + w: &'a mut W, +} +impl<'a> TIE20_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `TIE21` reader - Transmission Interrupt Enable 21"] +pub struct TIE21_R(crate::FieldReader); +impl TIE21_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE21_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE21_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE21` writer - Transmission Interrupt Enable 21"] +pub struct TIE21_W<'a> { + w: &'a mut W, +} +impl<'a> TIE21_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `TIE22` reader - Transmission Interrupt Enable 22"] +pub struct TIE22_R(crate::FieldReader); +impl TIE22_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE22_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE22_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE22` writer - Transmission Interrupt Enable 22"] +pub struct TIE22_W<'a> { + w: &'a mut W, +} +impl<'a> TIE22_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `TIE23` reader - Transmission Interrupt Enable 23"] +pub struct TIE23_R(crate::FieldReader); +impl TIE23_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE23_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE23_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE23` writer - Transmission Interrupt Enable 23"] +pub struct TIE23_W<'a> { + w: &'a mut W, +} +impl<'a> TIE23_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `TIE24` reader - Transmission Interrupt Enable 24"] +pub struct TIE24_R(crate::FieldReader); +impl TIE24_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE24_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE24_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE24` writer - Transmission Interrupt Enable 24"] +pub struct TIE24_W<'a> { + w: &'a mut W, +} +impl<'a> TIE24_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `TIE25` reader - Transmission Interrupt Enable 25"] +pub struct TIE25_R(crate::FieldReader); +impl TIE25_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE25_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE25_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE25` writer - Transmission Interrupt Enable 25"] +pub struct TIE25_W<'a> { + w: &'a mut W, +} +impl<'a> TIE25_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `TIE26` reader - Transmission Interrupt Enable 26"] +pub struct TIE26_R(crate::FieldReader); +impl TIE26_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE26_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE26_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE26` writer - Transmission Interrupt Enable 26"] +pub struct TIE26_W<'a> { + w: &'a mut W, +} +impl<'a> TIE26_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `TIE27` reader - Transmission Interrupt Enable 27"] +pub struct TIE27_R(crate::FieldReader); +impl TIE27_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE27_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE27_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE27` writer - Transmission Interrupt Enable 27"] +pub struct TIE27_W<'a> { + w: &'a mut W, +} +impl<'a> TIE27_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +#[doc = "Field `TIE28` reader - Transmission Interrupt Enable 28"] +pub struct TIE28_R(crate::FieldReader); +impl TIE28_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE28_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE28_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE28` writer - Transmission Interrupt Enable 28"] +pub struct TIE28_W<'a> { + w: &'a mut W, +} +impl<'a> TIE28_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Field `TIE29` reader - Transmission Interrupt Enable 29"] +pub struct TIE29_R(crate::FieldReader); +impl TIE29_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE29_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE29_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE29` writer - Transmission Interrupt Enable 29"] +pub struct TIE29_W<'a> { + w: &'a mut W, +} +impl<'a> TIE29_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29); + self.w + } +} +#[doc = "Field `TIE30` reader - Transmission Interrupt Enable 30"] +pub struct TIE30_R(crate::FieldReader); +impl TIE30_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE30_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE30_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE30` writer - Transmission Interrupt Enable 30"] +pub struct TIE30_W<'a> { + w: &'a mut W, +} +impl<'a> TIE30_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +#[doc = "Field `TIE31` reader - Transmission Interrupt Enable 31"] +pub struct TIE31_R(crate::FieldReader); +impl TIE31_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE31_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE31_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE31` writer - Transmission Interrupt Enable 31"] +pub struct TIE31_W<'a> { + w: &'a mut W, +} +impl<'a> TIE31_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bit 0 - Transmission Interrupt Enable 0"] + #[inline(always)] + pub fn tie0(&self) -> TIE0_R { + TIE0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmission Interrupt Enable 1"] + #[inline(always)] + pub fn tie1(&self) -> TIE1_R { + TIE1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Transmission Interrupt Enable 2"] + #[inline(always)] + pub fn tie2(&self) -> TIE2_R { + TIE2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Transmission Interrupt Enable 3"] + #[inline(always)] + pub fn tie3(&self) -> TIE3_R { + TIE3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Transmission Interrupt Enable 4"] + #[inline(always)] + pub fn tie4(&self) -> TIE4_R { + TIE4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Transmission Interrupt Enable 5"] + #[inline(always)] + pub fn tie5(&self) -> TIE5_R { + TIE5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Transmission Interrupt Enable 6"] + #[inline(always)] + pub fn tie6(&self) -> TIE6_R { + TIE6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Transmission Interrupt Enable 7"] + #[inline(always)] + pub fn tie7(&self) -> TIE7_R { + TIE7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Transmission Interrupt Enable 8"] + #[inline(always)] + pub fn tie8(&self) -> TIE8_R { + TIE8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Transmission Interrupt Enable 9"] + #[inline(always)] + pub fn tie9(&self) -> TIE9_R { + TIE9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Transmission Interrupt Enable 10"] + #[inline(always)] + pub fn tie10(&self) -> TIE10_R { + TIE10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Transmission Interrupt Enable 11"] + #[inline(always)] + pub fn tie11(&self) -> TIE11_R { + TIE11_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Transmission Interrupt Enable 12"] + #[inline(always)] + pub fn tie12(&self) -> TIE12_R { + TIE12_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Transmission Interrupt Enable 13"] + #[inline(always)] + pub fn tie13(&self) -> TIE13_R { + TIE13_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Transmission Interrupt Enable 14"] + #[inline(always)] + pub fn tie14(&self) -> TIE14_R { + TIE14_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Transmission Interrupt Enable 15"] + #[inline(always)] + pub fn tie15(&self) -> TIE15_R { + TIE15_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Transmission Interrupt Enable 16"] + #[inline(always)] + pub fn tie16(&self) -> TIE16_R { + TIE16_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Transmission Interrupt Enable 17"] + #[inline(always)] + pub fn tie17(&self) -> TIE17_R { + TIE17_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Transmission Interrupt Enable 18"] + #[inline(always)] + pub fn tie18(&self) -> TIE18_R { + TIE18_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Transmission Interrupt Enable 19"] + #[inline(always)] + pub fn tie19(&self) -> TIE19_R { + TIE19_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Transmission Interrupt Enable 20"] + #[inline(always)] + pub fn tie20(&self) -> TIE20_R { + TIE20_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Transmission Interrupt Enable 21"] + #[inline(always)] + pub fn tie21(&self) -> TIE21_R { + TIE21_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Transmission Interrupt Enable 22"] + #[inline(always)] + pub fn tie22(&self) -> TIE22_R { + TIE22_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Transmission Interrupt Enable 23"] + #[inline(always)] + pub fn tie23(&self) -> TIE23_R { + TIE23_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24 - Transmission Interrupt Enable 24"] + #[inline(always)] + pub fn tie24(&self) -> TIE24_R { + TIE24_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Transmission Interrupt Enable 25"] + #[inline(always)] + pub fn tie25(&self) -> TIE25_R { + TIE25_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Transmission Interrupt Enable 26"] + #[inline(always)] + pub fn tie26(&self) -> TIE26_R { + TIE26_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Transmission Interrupt Enable 27"] + #[inline(always)] + pub fn tie27(&self) -> TIE27_R { + TIE27_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28 - Transmission Interrupt Enable 28"] + #[inline(always)] + pub fn tie28(&self) -> TIE28_R { + TIE28_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Transmission Interrupt Enable 29"] + #[inline(always)] + pub fn tie29(&self) -> TIE29_R { + TIE29_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - Transmission Interrupt Enable 30"] + #[inline(always)] + pub fn tie30(&self) -> TIE30_R { + TIE30_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 31 - Transmission Interrupt Enable 31"] + #[inline(always)] + pub fn tie31(&self) -> TIE31_R { + TIE31_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Transmission Interrupt Enable 0"] + #[inline(always)] + pub fn tie0(&mut self) -> TIE0_W { + TIE0_W { w: self } + } + #[doc = "Bit 1 - Transmission Interrupt Enable 1"] + #[inline(always)] + pub fn tie1(&mut self) -> TIE1_W { + TIE1_W { w: self } + } + #[doc = "Bit 2 - Transmission Interrupt Enable 2"] + #[inline(always)] + pub fn tie2(&mut self) -> TIE2_W { + TIE2_W { w: self } + } + #[doc = "Bit 3 - Transmission Interrupt Enable 3"] + #[inline(always)] + pub fn tie3(&mut self) -> TIE3_W { + TIE3_W { w: self } + } + #[doc = "Bit 4 - Transmission Interrupt Enable 4"] + #[inline(always)] + pub fn tie4(&mut self) -> TIE4_W { + TIE4_W { w: self } + } + #[doc = "Bit 5 - Transmission Interrupt Enable 5"] + #[inline(always)] + pub fn tie5(&mut self) -> TIE5_W { + TIE5_W { w: self } + } + #[doc = "Bit 6 - Transmission Interrupt Enable 6"] + #[inline(always)] + pub fn tie6(&mut self) -> TIE6_W { + TIE6_W { w: self } + } + #[doc = "Bit 7 - Transmission Interrupt Enable 7"] + #[inline(always)] + pub fn tie7(&mut self) -> TIE7_W { + TIE7_W { w: self } + } + #[doc = "Bit 8 - Transmission Interrupt Enable 8"] + #[inline(always)] + pub fn tie8(&mut self) -> TIE8_W { + TIE8_W { w: self } + } + #[doc = "Bit 9 - Transmission Interrupt Enable 9"] + #[inline(always)] + pub fn tie9(&mut self) -> TIE9_W { + TIE9_W { w: self } + } + #[doc = "Bit 10 - Transmission Interrupt Enable 10"] + #[inline(always)] + pub fn tie10(&mut self) -> TIE10_W { + TIE10_W { w: self } + } + #[doc = "Bit 11 - Transmission Interrupt Enable 11"] + #[inline(always)] + pub fn tie11(&mut self) -> TIE11_W { + TIE11_W { w: self } + } + #[doc = "Bit 12 - Transmission Interrupt Enable 12"] + #[inline(always)] + pub fn tie12(&mut self) -> TIE12_W { + TIE12_W { w: self } + } + #[doc = "Bit 13 - Transmission Interrupt Enable 13"] + #[inline(always)] + pub fn tie13(&mut self) -> TIE13_W { + TIE13_W { w: self } + } + #[doc = "Bit 14 - Transmission Interrupt Enable 14"] + #[inline(always)] + pub fn tie14(&mut self) -> TIE14_W { + TIE14_W { w: self } + } + #[doc = "Bit 15 - Transmission Interrupt Enable 15"] + #[inline(always)] + pub fn tie15(&mut self) -> TIE15_W { + TIE15_W { w: self } + } + #[doc = "Bit 16 - Transmission Interrupt Enable 16"] + #[inline(always)] + pub fn tie16(&mut self) -> TIE16_W { + TIE16_W { w: self } + } + #[doc = "Bit 17 - Transmission Interrupt Enable 17"] + #[inline(always)] + pub fn tie17(&mut self) -> TIE17_W { + TIE17_W { w: self } + } + #[doc = "Bit 18 - Transmission Interrupt Enable 18"] + #[inline(always)] + pub fn tie18(&mut self) -> TIE18_W { + TIE18_W { w: self } + } + #[doc = "Bit 19 - Transmission Interrupt Enable 19"] + #[inline(always)] + pub fn tie19(&mut self) -> TIE19_W { + TIE19_W { w: self } + } + #[doc = "Bit 20 - Transmission Interrupt Enable 20"] + #[inline(always)] + pub fn tie20(&mut self) -> TIE20_W { + TIE20_W { w: self } + } + #[doc = "Bit 21 - Transmission Interrupt Enable 21"] + #[inline(always)] + pub fn tie21(&mut self) -> TIE21_W { + TIE21_W { w: self } + } + #[doc = "Bit 22 - Transmission Interrupt Enable 22"] + #[inline(always)] + pub fn tie22(&mut self) -> TIE22_W { + TIE22_W { w: self } + } + #[doc = "Bit 23 - Transmission Interrupt Enable 23"] + #[inline(always)] + pub fn tie23(&mut self) -> TIE23_W { + TIE23_W { w: self } + } + #[doc = "Bit 24 - Transmission Interrupt Enable 24"] + #[inline(always)] + pub fn tie24(&mut self) -> TIE24_W { + TIE24_W { w: self } + } + #[doc = "Bit 25 - Transmission Interrupt Enable 25"] + #[inline(always)] + pub fn tie25(&mut self) -> TIE25_W { + TIE25_W { w: self } + } + #[doc = "Bit 26 - Transmission Interrupt Enable 26"] + #[inline(always)] + pub fn tie26(&mut self) -> TIE26_W { + TIE26_W { w: self } + } + #[doc = "Bit 27 - Transmission Interrupt Enable 27"] + #[inline(always)] + pub fn tie27(&mut self) -> TIE27_W { + TIE27_W { w: self } + } + #[doc = "Bit 28 - Transmission Interrupt Enable 28"] + #[inline(always)] + pub fn tie28(&mut self) -> TIE28_W { + TIE28_W { w: self } + } + #[doc = "Bit 29 - Transmission Interrupt Enable 29"] + #[inline(always)] + pub fn tie29(&mut self) -> TIE29_W { + TIE29_W { w: self } + } + #[doc = "Bit 30 - Transmission Interrupt Enable 30"] + #[inline(always)] + pub fn tie30(&mut self) -> TIE30_W { + TIE30_W { w: self } + } + #[doc = "Bit 31 - Transmission Interrupt Enable 31"] + #[inline(always)] + pub fn tie31(&mut self) -> TIE31_W { + TIE31_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Tx Buffer Transmission Interrupt Enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txbtie](index.html) module"] +pub struct TXBTIE_SPEC; +impl crate::RegisterSpec for TXBTIE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [txbtie::R](R) reader structure"] +impl crate::Readable for TXBTIE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [txbtie::W](W) writer structure"] +impl crate::Writable for TXBTIE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TXBTIE to value 0"] +impl crate::Resettable for TXBTIE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/can0/txbto.rs b/pac/atsamc21e/src/can0/txbto.rs new file mode 100644 index 000000000000..54bc8f1295ad --- /dev/null +++ b/pac/atsamc21e/src/can0/txbto.rs @@ -0,0 +1,673 @@ +#[doc = "Register `TXBTO` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `TO0` reader - Transmission Occurred 0"] +pub struct TO0_R(crate::FieldReader); +impl TO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO1` reader - Transmission Occurred 1"] +pub struct TO1_R(crate::FieldReader); +impl TO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO2` reader - Transmission Occurred 2"] +pub struct TO2_R(crate::FieldReader); +impl TO2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO3` reader - Transmission Occurred 3"] +pub struct TO3_R(crate::FieldReader); +impl TO3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO4` reader - Transmission Occurred 4"] +pub struct TO4_R(crate::FieldReader); +impl TO4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO5` reader - Transmission Occurred 5"] +pub struct TO5_R(crate::FieldReader); +impl TO5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO6` reader - Transmission Occurred 6"] +pub struct TO6_R(crate::FieldReader); +impl TO6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO7` reader - Transmission Occurred 7"] +pub struct TO7_R(crate::FieldReader); +impl TO7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO8` reader - Transmission Occurred 8"] +pub struct TO8_R(crate::FieldReader); +impl TO8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO9` reader - Transmission Occurred 9"] +pub struct TO9_R(crate::FieldReader); +impl TO9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO10` reader - Transmission Occurred 10"] +pub struct TO10_R(crate::FieldReader); +impl TO10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO11` reader - Transmission Occurred 11"] +pub struct TO11_R(crate::FieldReader); +impl TO11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO12` reader - Transmission Occurred 12"] +pub struct TO12_R(crate::FieldReader); +impl TO12_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO12_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO12_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO13` reader - Transmission Occurred 13"] +pub struct TO13_R(crate::FieldReader); +impl TO13_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO13_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO13_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO14` reader - Transmission Occurred 14"] +pub struct TO14_R(crate::FieldReader); +impl TO14_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO14_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO14_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO15` reader - Transmission Occurred 15"] +pub struct TO15_R(crate::FieldReader); +impl TO15_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO15_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO15_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO16` reader - Transmission Occurred 16"] +pub struct TO16_R(crate::FieldReader); +impl TO16_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO16_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO16_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO17` reader - Transmission Occurred 17"] +pub struct TO17_R(crate::FieldReader); +impl TO17_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO17_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO17_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO18` reader - Transmission Occurred 18"] +pub struct TO18_R(crate::FieldReader); +impl TO18_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO18_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO18_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO19` reader - Transmission Occurred 19"] +pub struct TO19_R(crate::FieldReader); +impl TO19_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO19_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO19_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO20` reader - Transmission Occurred 20"] +pub struct TO20_R(crate::FieldReader); +impl TO20_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO20_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO20_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO21` reader - Transmission Occurred 21"] +pub struct TO21_R(crate::FieldReader); +impl TO21_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO21_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO21_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO22` reader - Transmission Occurred 22"] +pub struct TO22_R(crate::FieldReader); +impl TO22_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO22_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO22_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO23` reader - Transmission Occurred 23"] +pub struct TO23_R(crate::FieldReader); +impl TO23_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO23_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO23_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO24` reader - Transmission Occurred 24"] +pub struct TO24_R(crate::FieldReader); +impl TO24_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO24_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO24_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO25` reader - Transmission Occurred 25"] +pub struct TO25_R(crate::FieldReader); +impl TO25_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO25_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO25_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO26` reader - Transmission Occurred 26"] +pub struct TO26_R(crate::FieldReader); +impl TO26_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO26_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO26_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO27` reader - Transmission Occurred 27"] +pub struct TO27_R(crate::FieldReader); +impl TO27_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO27_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO27_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO28` reader - Transmission Occurred 28"] +pub struct TO28_R(crate::FieldReader); +impl TO28_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO28_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO28_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO29` reader - Transmission Occurred 29"] +pub struct TO29_R(crate::FieldReader); +impl TO29_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO29_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO29_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO30` reader - Transmission Occurred 30"] +pub struct TO30_R(crate::FieldReader); +impl TO30_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO30_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO30_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO31` reader - Transmission Occurred 31"] +pub struct TO31_R(crate::FieldReader); +impl TO31_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO31_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO31_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Transmission Occurred 0"] + #[inline(always)] + pub fn to0(&self) -> TO0_R { + TO0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmission Occurred 1"] + #[inline(always)] + pub fn to1(&self) -> TO1_R { + TO1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Transmission Occurred 2"] + #[inline(always)] + pub fn to2(&self) -> TO2_R { + TO2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Transmission Occurred 3"] + #[inline(always)] + pub fn to3(&self) -> TO3_R { + TO3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Transmission Occurred 4"] + #[inline(always)] + pub fn to4(&self) -> TO4_R { + TO4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Transmission Occurred 5"] + #[inline(always)] + pub fn to5(&self) -> TO5_R { + TO5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Transmission Occurred 6"] + #[inline(always)] + pub fn to6(&self) -> TO6_R { + TO6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Transmission Occurred 7"] + #[inline(always)] + pub fn to7(&self) -> TO7_R { + TO7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Transmission Occurred 8"] + #[inline(always)] + pub fn to8(&self) -> TO8_R { + TO8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Transmission Occurred 9"] + #[inline(always)] + pub fn to9(&self) -> TO9_R { + TO9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Transmission Occurred 10"] + #[inline(always)] + pub fn to10(&self) -> TO10_R { + TO10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Transmission Occurred 11"] + #[inline(always)] + pub fn to11(&self) -> TO11_R { + TO11_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Transmission Occurred 12"] + #[inline(always)] + pub fn to12(&self) -> TO12_R { + TO12_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Transmission Occurred 13"] + #[inline(always)] + pub fn to13(&self) -> TO13_R { + TO13_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Transmission Occurred 14"] + #[inline(always)] + pub fn to14(&self) -> TO14_R { + TO14_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Transmission Occurred 15"] + #[inline(always)] + pub fn to15(&self) -> TO15_R { + TO15_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Transmission Occurred 16"] + #[inline(always)] + pub fn to16(&self) -> TO16_R { + TO16_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Transmission Occurred 17"] + #[inline(always)] + pub fn to17(&self) -> TO17_R { + TO17_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Transmission Occurred 18"] + #[inline(always)] + pub fn to18(&self) -> TO18_R { + TO18_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Transmission Occurred 19"] + #[inline(always)] + pub fn to19(&self) -> TO19_R { + TO19_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Transmission Occurred 20"] + #[inline(always)] + pub fn to20(&self) -> TO20_R { + TO20_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Transmission Occurred 21"] + #[inline(always)] + pub fn to21(&self) -> TO21_R { + TO21_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Transmission Occurred 22"] + #[inline(always)] + pub fn to22(&self) -> TO22_R { + TO22_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Transmission Occurred 23"] + #[inline(always)] + pub fn to23(&self) -> TO23_R { + TO23_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24 - Transmission Occurred 24"] + #[inline(always)] + pub fn to24(&self) -> TO24_R { + TO24_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Transmission Occurred 25"] + #[inline(always)] + pub fn to25(&self) -> TO25_R { + TO25_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Transmission Occurred 26"] + #[inline(always)] + pub fn to26(&self) -> TO26_R { + TO26_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Transmission Occurred 27"] + #[inline(always)] + pub fn to27(&self) -> TO27_R { + TO27_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28 - Transmission Occurred 28"] + #[inline(always)] + pub fn to28(&self) -> TO28_R { + TO28_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Transmission Occurred 29"] + #[inline(always)] + pub fn to29(&self) -> TO29_R { + TO29_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - Transmission Occurred 30"] + #[inline(always)] + pub fn to30(&self) -> TO30_R { + TO30_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 31 - Transmission Occurred 31"] + #[inline(always)] + pub fn to31(&self) -> TO31_R { + TO31_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +#[doc = "Tx Buffer Transmission Occurred\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txbto](index.html) module"] +pub struct TXBTO_SPEC; +impl crate::RegisterSpec for TXBTO_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [txbto::R](R) reader structure"] +impl crate::Readable for TXBTO_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets TXBTO to value 0"] +impl crate::Resettable for TXBTO_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/can0/txefa.rs b/pac/atsamc21e/src/can0/txefa.rs new file mode 100644 index 000000000000..c539b8fc3dc0 --- /dev/null +++ b/pac/atsamc21e/src/can0/txefa.rs @@ -0,0 +1,103 @@ +#[doc = "Register `TXEFA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TXEFA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EFAI` reader - Event FIFO Acknowledge Index"] +pub struct EFAI_R(crate::FieldReader); +impl EFAI_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EFAI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EFAI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EFAI` writer - Event FIFO Acknowledge Index"] +pub struct EFAI_W<'a> { + w: &'a mut W, +} +impl<'a> EFAI_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Event FIFO Acknowledge Index"] + #[inline(always)] + pub fn efai(&self) -> EFAI_R { + EFAI_R::new((self.bits & 0x1f) as u8) + } +} +impl W { + #[doc = "Bits 0:4 - Event FIFO Acknowledge Index"] + #[inline(always)] + pub fn efai(&mut self) -> EFAI_W { + EFAI_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Tx Event FIFO Acknowledge\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txefa](index.html) module"] +pub struct TXEFA_SPEC; +impl crate::RegisterSpec for TXEFA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [txefa::R](R) reader structure"] +impl crate::Readable for TXEFA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [txefa::W](W) writer structure"] +impl crate::Writable for TXEFA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TXEFA to value 0"] +impl crate::Resettable for TXEFA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/can0/txefc.rs b/pac/atsamc21e/src/can0/txefc.rs new file mode 100644 index 000000000000..0c9b658d285b --- /dev/null +++ b/pac/atsamc21e/src/can0/txefc.rs @@ -0,0 +1,177 @@ +#[doc = "Register `TXEFC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TXEFC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EFSA` reader - Event FIFO Start Address"] +pub struct EFSA_R(crate::FieldReader); +impl EFSA_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + EFSA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EFSA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EFSA` writer - Event FIFO Start Address"] +pub struct EFSA_W<'a> { + w: &'a mut W, +} +impl<'a> EFSA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +#[doc = "Field `EFS` reader - Event FIFO Size"] +pub struct EFS_R(crate::FieldReader); +impl EFS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EFS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EFS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EFS` writer - Event FIFO Size"] +pub struct EFS_W<'a> { + w: &'a mut W, +} +impl<'a> EFS_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 16)) | ((value as u32 & 0x3f) << 16); + self.w + } +} +#[doc = "Field `EFWM` reader - Event FIFO Watermark"] +pub struct EFWM_R(crate::FieldReader); +impl EFWM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EFWM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EFWM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EFWM` writer - Event FIFO Watermark"] +pub struct EFWM_W<'a> { + w: &'a mut W, +} +impl<'a> EFWM_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 24)) | ((value as u32 & 0x3f) << 24); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Event FIFO Start Address"] + #[inline(always)] + pub fn efsa(&self) -> EFSA_R { + EFSA_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:21 - Event FIFO Size"] + #[inline(always)] + pub fn efs(&self) -> EFS_R { + EFS_R::new(((self.bits >> 16) & 0x3f) as u8) + } + #[doc = "Bits 24:29 - Event FIFO Watermark"] + #[inline(always)] + pub fn efwm(&self) -> EFWM_R { + EFWM_R::new(((self.bits >> 24) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:15 - Event FIFO Start Address"] + #[inline(always)] + pub fn efsa(&mut self) -> EFSA_W { + EFSA_W { w: self } + } + #[doc = "Bits 16:21 - Event FIFO Size"] + #[inline(always)] + pub fn efs(&mut self) -> EFS_W { + EFS_W { w: self } + } + #[doc = "Bits 24:29 - Event FIFO Watermark"] + #[inline(always)] + pub fn efwm(&mut self) -> EFWM_W { + EFWM_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Tx Event FIFO Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txefc](index.html) module"] +pub struct TXEFC_SPEC; +impl crate::RegisterSpec for TXEFC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [txefc::R](R) reader structure"] +impl crate::Readable for TXEFC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [txefc::W](W) writer structure"] +impl crate::Writable for TXEFC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TXEFC to value 0"] +impl crate::Resettable for TXEFC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/can0/txefs.rs b/pac/atsamc21e/src/can0/txefs.rs new file mode 100644 index 000000000000..85cac75a7ad7 --- /dev/null +++ b/pac/atsamc21e/src/can0/txefs.rs @@ -0,0 +1,133 @@ +#[doc = "Register `TXEFS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `EFFL` reader - Event FIFO Fill Level"] +pub struct EFFL_R(crate::FieldReader); +impl EFFL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EFFL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EFFL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EFGI` reader - Event FIFO Get Index"] +pub struct EFGI_R(crate::FieldReader); +impl EFGI_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EFGI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EFGI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EFPI` reader - Event FIFO Put Index"] +pub struct EFPI_R(crate::FieldReader); +impl EFPI_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EFPI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EFPI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EFF` reader - Event FIFO Full"] +pub struct EFF_R(crate::FieldReader); +impl EFF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EFF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EFF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TEFL` reader - Tx Event FIFO Element Lost"] +pub struct TEFL_R(crate::FieldReader); +impl TEFL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TEFL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TEFL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:5 - Event FIFO Fill Level"] + #[inline(always)] + pub fn effl(&self) -> EFFL_R { + EFFL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 8:12 - Event FIFO Get Index"] + #[inline(always)] + pub fn efgi(&self) -> EFGI_R { + EFGI_R::new(((self.bits >> 8) & 0x1f) as u8) + } + #[doc = "Bits 16:20 - Event FIFO Put Index"] + #[inline(always)] + pub fn efpi(&self) -> EFPI_R { + EFPI_R::new(((self.bits >> 16) & 0x1f) as u8) + } + #[doc = "Bit 24 - Event FIFO Full"] + #[inline(always)] + pub fn eff(&self) -> EFF_R { + EFF_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Tx Event FIFO Element Lost"] + #[inline(always)] + pub fn tefl(&self) -> TEFL_R { + TEFL_R::new(((self.bits >> 25) & 0x01) != 0) + } +} +#[doc = "Tx Event FIFO Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txefs](index.html) module"] +pub struct TXEFS_SPEC; +impl crate::RegisterSpec for TXEFS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [txefs::R](R) reader structure"] +impl crate::Readable for TXEFS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets TXEFS to value 0"] +impl crate::Resettable for TXEFS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/can0/txesc.rs b/pac/atsamc21e/src/can0/txesc.rs new file mode 100644 index 000000000000..7d1339f7c1cb --- /dev/null +++ b/pac/atsamc21e/src/can0/txesc.rs @@ -0,0 +1,230 @@ +#[doc = "Register `TXESC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TXESC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Tx Buffer Data Field Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum TBDS_A { + #[doc = "0: 8 byte data field"] + DATA8 = 0, + #[doc = "1: 12 byte data field"] + DATA12 = 1, + #[doc = "2: 16 byte data field"] + DATA16 = 2, + #[doc = "3: 20 byte data field"] + DATA20 = 3, + #[doc = "4: 24 byte data field"] + DATA24 = 4, + #[doc = "5: 32 byte data field"] + DATA32 = 5, + #[doc = "6: 48 byte data field"] + DATA48 = 6, + #[doc = "7: 64 byte data field"] + DATA64 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: TBDS_A) -> Self { + variant as _ + } +} +#[doc = "Field `TBDS` reader - Tx Buffer Data Field Size"] +pub struct TBDS_R(crate::FieldReader); +impl TBDS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TBDS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TBDS_A { + match self.bits { + 0 => TBDS_A::DATA8, + 1 => TBDS_A::DATA12, + 2 => TBDS_A::DATA16, + 3 => TBDS_A::DATA20, + 4 => TBDS_A::DATA24, + 5 => TBDS_A::DATA32, + 6 => TBDS_A::DATA48, + 7 => TBDS_A::DATA64, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DATA8`"] + #[inline(always)] + pub fn is_data8(&self) -> bool { + **self == TBDS_A::DATA8 + } + #[doc = "Checks if the value of the field is `DATA12`"] + #[inline(always)] + pub fn is_data12(&self) -> bool { + **self == TBDS_A::DATA12 + } + #[doc = "Checks if the value of the field is `DATA16`"] + #[inline(always)] + pub fn is_data16(&self) -> bool { + **self == TBDS_A::DATA16 + } + #[doc = "Checks if the value of the field is `DATA20`"] + #[inline(always)] + pub fn is_data20(&self) -> bool { + **self == TBDS_A::DATA20 + } + #[doc = "Checks if the value of the field is `DATA24`"] + #[inline(always)] + pub fn is_data24(&self) -> bool { + **self == TBDS_A::DATA24 + } + #[doc = "Checks if the value of the field is `DATA32`"] + #[inline(always)] + pub fn is_data32(&self) -> bool { + **self == TBDS_A::DATA32 + } + #[doc = "Checks if the value of the field is `DATA48`"] + #[inline(always)] + pub fn is_data48(&self) -> bool { + **self == TBDS_A::DATA48 + } + #[doc = "Checks if the value of the field is `DATA64`"] + #[inline(always)] + pub fn is_data64(&self) -> bool { + **self == TBDS_A::DATA64 + } +} +impl core::ops::Deref for TBDS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TBDS` writer - Tx Buffer Data Field Size"] +pub struct TBDS_W<'a> { + w: &'a mut W, +} +impl<'a> TBDS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TBDS_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "8 byte data field"] + #[inline(always)] + pub fn data8(self) -> &'a mut W { + self.variant(TBDS_A::DATA8) + } + #[doc = "12 byte data field"] + #[inline(always)] + pub fn data12(self) -> &'a mut W { + self.variant(TBDS_A::DATA12) + } + #[doc = "16 byte data field"] + #[inline(always)] + pub fn data16(self) -> &'a mut W { + self.variant(TBDS_A::DATA16) + } + #[doc = "20 byte data field"] + #[inline(always)] + pub fn data20(self) -> &'a mut W { + self.variant(TBDS_A::DATA20) + } + #[doc = "24 byte data field"] + #[inline(always)] + pub fn data24(self) -> &'a mut W { + self.variant(TBDS_A::DATA24) + } + #[doc = "32 byte data field"] + #[inline(always)] + pub fn data32(self) -> &'a mut W { + self.variant(TBDS_A::DATA32) + } + #[doc = "48 byte data field"] + #[inline(always)] + pub fn data48(self) -> &'a mut W { + self.variant(TBDS_A::DATA48) + } + #[doc = "64 byte data field"] + #[inline(always)] + pub fn data64(self) -> &'a mut W { + self.variant(TBDS_A::DATA64) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Tx Buffer Data Field Size"] + #[inline(always)] + pub fn tbds(&self) -> TBDS_R { + TBDS_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Tx Buffer Data Field Size"] + #[inline(always)] + pub fn tbds(&mut self) -> TBDS_W { + TBDS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Tx Buffer Element Size Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txesc](index.html) module"] +pub struct TXESC_SPEC; +impl crate::RegisterSpec for TXESC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [txesc::R](R) reader structure"] +impl crate::Readable for TXESC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [txesc::W](W) writer structure"] +impl crate::Writable for TXESC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TXESC to value 0"] +impl crate::Resettable for TXESC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/can0/txfqs.rs b/pac/atsamc21e/src/can0/txfqs.rs new file mode 100644 index 000000000000..19ef5f5d3fe6 --- /dev/null +++ b/pac/atsamc21e/src/can0/txfqs.rs @@ -0,0 +1,113 @@ +#[doc = "Register `TXFQS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `TFFL` reader - Tx FIFO Free Level"] +pub struct TFFL_R(crate::FieldReader); +impl TFFL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TFFL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TFFL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TFGI` reader - Tx FIFO Get Index"] +pub struct TFGI_R(crate::FieldReader); +impl TFGI_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TFGI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TFGI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TFQPI` reader - Tx FIFO/Queue Put Index"] +pub struct TFQPI_R(crate::FieldReader); +impl TFQPI_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TFQPI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TFQPI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TFQF` reader - Tx FIFO/Queue Full"] +pub struct TFQF_R(crate::FieldReader); +impl TFQF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TFQF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TFQF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:5 - Tx FIFO Free Level"] + #[inline(always)] + pub fn tffl(&self) -> TFFL_R { + TFFL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 8:12 - Tx FIFO Get Index"] + #[inline(always)] + pub fn tfgi(&self) -> TFGI_R { + TFGI_R::new(((self.bits >> 8) & 0x1f) as u8) + } + #[doc = "Bits 16:20 - Tx FIFO/Queue Put Index"] + #[inline(always)] + pub fn tfqpi(&self) -> TFQPI_R { + TFQPI_R::new(((self.bits >> 16) & 0x1f) as u8) + } + #[doc = "Bit 21 - Tx FIFO/Queue Full"] + #[inline(always)] + pub fn tfqf(&self) -> TFQF_R { + TFQF_R::new(((self.bits >> 21) & 0x01) != 0) + } +} +#[doc = "Tx FIFO / Queue Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txfqs](index.html) module"] +pub struct TXFQS_SPEC; +impl crate::RegisterSpec for TXFQS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [txfqs::R](R) reader structure"] +impl crate::Readable for TXFQS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets TXFQS to value 0"] +impl crate::Resettable for TXFQS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/can0/xidam.rs b/pac/atsamc21e/src/can0/xidam.rs new file mode 100644 index 000000000000..8d78879a63be --- /dev/null +++ b/pac/atsamc21e/src/can0/xidam.rs @@ -0,0 +1,103 @@ +#[doc = "Register `XIDAM` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `XIDAM` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EIDM` reader - Extended ID Mask"] +pub struct EIDM_R(crate::FieldReader); +impl EIDM_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + EIDM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EIDM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EIDM` writer - Extended ID Mask"] +pub struct EIDM_W<'a> { + w: &'a mut W, +} +impl<'a> EIDM_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1fff_ffff) | (value as u32 & 0x1fff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:28 - Extended ID Mask"] + #[inline(always)] + pub fn eidm(&self) -> EIDM_R { + EIDM_R::new((self.bits & 0x1fff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:28 - Extended ID Mask"] + #[inline(always)] + pub fn eidm(&mut self) -> EIDM_W { + EIDM_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Extended ID AND Mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [xidam](index.html) module"] +pub struct XIDAM_SPEC; +impl crate::RegisterSpec for XIDAM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [xidam::R](R) reader structure"] +impl crate::Readable for XIDAM_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [xidam::W](W) writer structure"] +impl crate::Writable for XIDAM_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets XIDAM to value 0x1fff_ffff"] +impl crate::Resettable for XIDAM_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x1fff_ffff + } +} diff --git a/pac/atsamc21e/src/can0/xidfc.rs b/pac/atsamc21e/src/can0/xidfc.rs new file mode 100644 index 000000000000..57b31389a71f --- /dev/null +++ b/pac/atsamc21e/src/can0/xidfc.rs @@ -0,0 +1,140 @@ +#[doc = "Register `XIDFC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `XIDFC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FLESA` reader - Filter List Extended Start Address"] +pub struct FLESA_R(crate::FieldReader); +impl FLESA_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + FLESA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FLESA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLESA` writer - Filter List Extended Start Address"] +pub struct FLESA_W<'a> { + w: &'a mut W, +} +impl<'a> FLESA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +#[doc = "Field `LSE` reader - List Size Extended"] +pub struct LSE_R(crate::FieldReader); +impl LSE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LSE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LSE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LSE` writer - List Size Extended"] +pub struct LSE_W<'a> { + w: &'a mut W, +} +impl<'a> LSE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x7f << 16)) | ((value as u32 & 0x7f) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Filter List Extended Start Address"] + #[inline(always)] + pub fn flesa(&self) -> FLESA_R { + FLESA_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:22 - List Size Extended"] + #[inline(always)] + pub fn lse(&self) -> LSE_R { + LSE_R::new(((self.bits >> 16) & 0x7f) as u8) + } +} +impl W { + #[doc = "Bits 0:15 - Filter List Extended Start Address"] + #[inline(always)] + pub fn flesa(&mut self) -> FLESA_W { + FLESA_W { w: self } + } + #[doc = "Bits 16:22 - List Size Extended"] + #[inline(always)] + pub fn lse(&mut self) -> LSE_W { + LSE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Extended ID Filter Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [xidfc](index.html) module"] +pub struct XIDFC_SPEC; +impl crate::RegisterSpec for XIDFC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [xidfc::R](R) reader structure"] +impl crate::Readable for XIDFC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [xidfc::W](W) writer structure"] +impl crate::Writable for XIDFC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets XIDFC to value 0"] +impl crate::Resettable for XIDFC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/ccl.rs b/pac/atsamc21e/src/ccl.rs new file mode 100644 index 000000000000..30b1f41639c1 --- /dev/null +++ b/pac/atsamc21e/src/ccl.rs @@ -0,0 +1,24 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrl: crate::Reg, + _reserved1: [u8; 0x03], + #[doc = "0x04 - SEQ Control x"] + pub seqctrl: [crate::Reg; 2], + _reserved2: [u8; 0x02], + #[doc = "0x08..0x18 - LUT Control x"] + pub lutctrl: [crate::Reg; 4], +} +#[doc = "CTRL register accessor: an alias for `Reg`"] +pub type CTRL = crate::Reg; +#[doc = "Control"] +pub mod ctrl; +#[doc = "SEQCTRL register accessor: an alias for `Reg`"] +pub type SEQCTRL = crate::Reg; +#[doc = "SEQ Control x"] +pub mod seqctrl; +#[doc = "LUTCTRL register accessor: an alias for `Reg`"] +pub type LUTCTRL = crate::Reg; +#[doc = "LUT Control x"] +pub mod lutctrl; diff --git a/pac/atsamc21e/src/ccl/ctrl.rs b/pac/atsamc21e/src/ccl/ctrl.rs new file mode 100644 index 000000000000..5e515fe037ca --- /dev/null +++ b/pac/atsamc21e/src/ccl/ctrl.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"] +pub struct CTRL_SPEC; +impl crate::RegisterSpec for CTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrl::R](R) reader structure"] +impl crate::Readable for CTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"] +impl crate::Writable for CTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/ccl/lutctrl.rs b/pac/atsamc21e/src/ccl/lutctrl.rs new file mode 100644 index 000000000000..530ed34f7c81 --- /dev/null +++ b/pac/atsamc21e/src/ccl/lutctrl.rs @@ -0,0 +1,702 @@ +#[doc = "Register `LUTCTRL[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `LUTCTRL[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - LUT Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - LUT Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Filter Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FILTSEL_A { + #[doc = "0: Filter disabled"] + DISABLE = 0, + #[doc = "1: Synchronizer enabled"] + SYNCH = 1, + #[doc = "2: Filter enabled"] + FILTER = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FILTSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `FILTSEL` reader - Filter Selection"] +pub struct FILTSEL_R(crate::FieldReader); +impl FILTSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FILTSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(FILTSEL_A::DISABLE), + 1 => Some(FILTSEL_A::SYNCH), + 2 => Some(FILTSEL_A::FILTER), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == FILTSEL_A::DISABLE + } + #[doc = "Checks if the value of the field is `SYNCH`"] + #[inline(always)] + pub fn is_synch(&self) -> bool { + **self == FILTSEL_A::SYNCH + } + #[doc = "Checks if the value of the field is `FILTER`"] + #[inline(always)] + pub fn is_filter(&self) -> bool { + **self == FILTSEL_A::FILTER + } +} +impl core::ops::Deref for FILTSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTSEL` writer - Filter Selection"] +pub struct FILTSEL_W<'a> { + w: &'a mut W, +} +impl<'a> FILTSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FILTSEL_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Filter disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(FILTSEL_A::DISABLE) + } + #[doc = "Synchronizer enabled"] + #[inline(always)] + pub fn synch(self) -> &'a mut W { + self.variant(FILTSEL_A::SYNCH) + } + #[doc = "Filter enabled"] + #[inline(always)] + pub fn filter(self) -> &'a mut W { + self.variant(FILTSEL_A::FILTER) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u32 & 0x03) << 4); + self.w + } +} +#[doc = "Field `EDGESEL` reader - Edge Selection"] +pub struct EDGESEL_R(crate::FieldReader); +impl EDGESEL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EDGESEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EDGESEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EDGESEL` writer - Edge Selection"] +pub struct EDGESEL_W<'a> { + w: &'a mut W, +} +impl<'a> EDGESEL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Input Selection 0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum INSEL0_A { + #[doc = "0: Masked input"] + MASK = 0, + #[doc = "1: Feedback input source"] + FEEDBACK = 1, + #[doc = "2: Linked LUT input source"] + LINK = 2, + #[doc = "3: Event in put source"] + EVENT = 3, + #[doc = "4: I/O pin input source"] + IO = 4, + #[doc = "5: AC input source"] + AC = 5, + #[doc = "6: TC input source"] + TC = 6, + #[doc = "7: Alternate TC input source"] + ALTTC = 7, + #[doc = "8: TCC input source"] + TCC = 8, + #[doc = "9: SERCOM inout source"] + SERCOM = 9, +} +impl From for u8 { + #[inline(always)] + fn from(variant: INSEL0_A) -> Self { + variant as _ + } +} +#[doc = "Field `INSEL0` reader - Input Selection 0"] +pub struct INSEL0_R(crate::FieldReader); +impl INSEL0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + INSEL0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(INSEL0_A::MASK), + 1 => Some(INSEL0_A::FEEDBACK), + 2 => Some(INSEL0_A::LINK), + 3 => Some(INSEL0_A::EVENT), + 4 => Some(INSEL0_A::IO), + 5 => Some(INSEL0_A::AC), + 6 => Some(INSEL0_A::TC), + 7 => Some(INSEL0_A::ALTTC), + 8 => Some(INSEL0_A::TCC), + 9 => Some(INSEL0_A::SERCOM), + _ => None, + } + } + #[doc = "Checks if the value of the field is `MASK`"] + #[inline(always)] + pub fn is_mask(&self) -> bool { + **self == INSEL0_A::MASK + } + #[doc = "Checks if the value of the field is `FEEDBACK`"] + #[inline(always)] + pub fn is_feedback(&self) -> bool { + **self == INSEL0_A::FEEDBACK + } + #[doc = "Checks if the value of the field is `LINK`"] + #[inline(always)] + pub fn is_link(&self) -> bool { + **self == INSEL0_A::LINK + } + #[doc = "Checks if the value of the field is `EVENT`"] + #[inline(always)] + pub fn is_event(&self) -> bool { + **self == INSEL0_A::EVENT + } + #[doc = "Checks if the value of the field is `IO`"] + #[inline(always)] + pub fn is_io(&self) -> bool { + **self == INSEL0_A::IO + } + #[doc = "Checks if the value of the field is `AC`"] + #[inline(always)] + pub fn is_ac(&self) -> bool { + **self == INSEL0_A::AC + } + #[doc = "Checks if the value of the field is `TC`"] + #[inline(always)] + pub fn is_tc(&self) -> bool { + **self == INSEL0_A::TC + } + #[doc = "Checks if the value of the field is `ALTTC`"] + #[inline(always)] + pub fn is_alttc(&self) -> bool { + **self == INSEL0_A::ALTTC + } + #[doc = "Checks if the value of the field is `TCC`"] + #[inline(always)] + pub fn is_tcc(&self) -> bool { + **self == INSEL0_A::TCC + } + #[doc = "Checks if the value of the field is `SERCOM`"] + #[inline(always)] + pub fn is_sercom(&self) -> bool { + **self == INSEL0_A::SERCOM + } +} +impl core::ops::Deref for INSEL0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INSEL0` writer - Input Selection 0"] +pub struct INSEL0_W<'a> { + w: &'a mut W, +} +impl<'a> INSEL0_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: INSEL0_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Masked input"] + #[inline(always)] + pub fn mask(self) -> &'a mut W { + self.variant(INSEL0_A::MASK) + } + #[doc = "Feedback input source"] + #[inline(always)] + pub fn feedback(self) -> &'a mut W { + self.variant(INSEL0_A::FEEDBACK) + } + #[doc = "Linked LUT input source"] + #[inline(always)] + pub fn link(self) -> &'a mut W { + self.variant(INSEL0_A::LINK) + } + #[doc = "Event in put source"] + #[inline(always)] + pub fn event(self) -> &'a mut W { + self.variant(INSEL0_A::EVENT) + } + #[doc = "I/O pin input source"] + #[inline(always)] + pub fn io(self) -> &'a mut W { + self.variant(INSEL0_A::IO) + } + #[doc = "AC input source"] + #[inline(always)] + pub fn ac(self) -> &'a mut W { + self.variant(INSEL0_A::AC) + } + #[doc = "TC input source"] + #[inline(always)] + pub fn tc(self) -> &'a mut W { + self.variant(INSEL0_A::TC) + } + #[doc = "Alternate TC input source"] + #[inline(always)] + pub fn alttc(self) -> &'a mut W { + self.variant(INSEL0_A::ALTTC) + } + #[doc = "TCC input source"] + #[inline(always)] + pub fn tcc(self) -> &'a mut W { + self.variant(INSEL0_A::TCC) + } + #[doc = "SERCOM inout source"] + #[inline(always)] + pub fn sercom(self) -> &'a mut W { + self.variant(INSEL0_A::SERCOM) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 8)) | ((value as u32 & 0x0f) << 8); + self.w + } +} +#[doc = "Field `INSEL1` reader - Input Selection 1"] +pub struct INSEL1_R(crate::FieldReader); +impl INSEL1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + INSEL1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INSEL1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INSEL1` writer - Input Selection 1"] +pub struct INSEL1_W<'a> { + w: &'a mut W, +} +impl<'a> INSEL1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 12)) | ((value as u32 & 0x0f) << 12); + self.w + } +} +#[doc = "Field `INSEL2` reader - Input Selection 2"] +pub struct INSEL2_R(crate::FieldReader); +impl INSEL2_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + INSEL2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INSEL2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INSEL2` writer - Input Selection 2"] +pub struct INSEL2_W<'a> { + w: &'a mut W, +} +impl<'a> INSEL2_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 16)) | ((value as u32 & 0x0f) << 16); + self.w + } +} +#[doc = "Field `INVEI` reader - Input Event Invert"] +pub struct INVEI_R(crate::FieldReader); +impl INVEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEI` writer - Input Event Invert"] +pub struct INVEI_W<'a> { + w: &'a mut W, +} +impl<'a> INVEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `LUTEI` reader - Event Input Enable"] +pub struct LUTEI_R(crate::FieldReader); +impl LUTEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LUTEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LUTEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LUTEI` writer - Event Input Enable"] +pub struct LUTEI_W<'a> { + w: &'a mut W, +} +impl<'a> LUTEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `LUTEO` reader - Event Output Enable"] +pub struct LUTEO_R(crate::FieldReader); +impl LUTEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LUTEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LUTEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LUTEO` writer - Event Output Enable"] +pub struct LUTEO_W<'a> { + w: &'a mut W, +} +impl<'a> LUTEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `TRUTH` reader - Truth Value"] +pub struct TRUTH_R(crate::FieldReader); +impl TRUTH_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TRUTH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRUTH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRUTH` writer - Truth Value"] +pub struct TRUTH_W<'a> { + w: &'a mut W, +} +impl<'a> TRUTH_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 24)) | ((value as u32 & 0xff) << 24); + self.w + } +} +impl R { + #[doc = "Bit 1 - LUT Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 4:5 - Filter Selection"] + #[inline(always)] + pub fn filtsel(&self) -> FILTSEL_R { + FILTSEL_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bit 7 - Edge Selection"] + #[inline(always)] + pub fn edgesel(&self) -> EDGESEL_R { + EDGESEL_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:11 - Input Selection 0"] + #[inline(always)] + pub fn insel0(&self) -> INSEL0_R { + INSEL0_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - Input Selection 1"] + #[inline(always)] + pub fn insel1(&self) -> INSEL1_R { + INSEL1_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:19 - Input Selection 2"] + #[inline(always)] + pub fn insel2(&self) -> INSEL2_R { + INSEL2_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Input Event Invert"] + #[inline(always)] + pub fn invei(&self) -> INVEI_R { + INVEI_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Event Input Enable"] + #[inline(always)] + pub fn lutei(&self) -> LUTEI_R { + LUTEI_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Event Output Enable"] + #[inline(always)] + pub fn luteo(&self) -> LUTEO_R { + LUTEO_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bits 24:31 - Truth Value"] + #[inline(always)] + pub fn truth(&self) -> TRUTH_R { + TRUTH_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bit 1 - LUT Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 4:5 - Filter Selection"] + #[inline(always)] + pub fn filtsel(&mut self) -> FILTSEL_W { + FILTSEL_W { w: self } + } + #[doc = "Bit 7 - Edge Selection"] + #[inline(always)] + pub fn edgesel(&mut self) -> EDGESEL_W { + EDGESEL_W { w: self } + } + #[doc = "Bits 8:11 - Input Selection 0"] + #[inline(always)] + pub fn insel0(&mut self) -> INSEL0_W { + INSEL0_W { w: self } + } + #[doc = "Bits 12:15 - Input Selection 1"] + #[inline(always)] + pub fn insel1(&mut self) -> INSEL1_W { + INSEL1_W { w: self } + } + #[doc = "Bits 16:19 - Input Selection 2"] + #[inline(always)] + pub fn insel2(&mut self) -> INSEL2_W { + INSEL2_W { w: self } + } + #[doc = "Bit 20 - Input Event Invert"] + #[inline(always)] + pub fn invei(&mut self) -> INVEI_W { + INVEI_W { w: self } + } + #[doc = "Bit 21 - Event Input Enable"] + #[inline(always)] + pub fn lutei(&mut self) -> LUTEI_W { + LUTEI_W { w: self } + } + #[doc = "Bit 22 - Event Output Enable"] + #[inline(always)] + pub fn luteo(&mut self) -> LUTEO_W { + LUTEO_W { w: self } + } + #[doc = "Bits 24:31 - Truth Value"] + #[inline(always)] + pub fn truth(&mut self) -> TRUTH_W { + TRUTH_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "LUT Control x\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lutctrl](index.html) module"] +pub struct LUTCTRL_SPEC; +impl crate::RegisterSpec for LUTCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [lutctrl::R](R) reader structure"] +impl crate::Readable for LUTCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [lutctrl::W](W) writer structure"] +impl crate::Writable for LUTCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets LUTCTRL[%s] +to value 0"] +impl crate::Resettable for LUTCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/ccl/seqctrl.rs b/pac/atsamc21e/src/ccl/seqctrl.rs new file mode 100644 index 000000000000..e2597a1042f3 --- /dev/null +++ b/pac/atsamc21e/src/ccl/seqctrl.rs @@ -0,0 +1,192 @@ +#[doc = "Register `SEQCTRL[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SEQCTRL[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Sequential Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SEQSEL_A { + #[doc = "0: Sequential logic is disabled"] + DISABLE = 0, + #[doc = "1: D flip flop"] + DFF = 1, + #[doc = "2: JK flip flop"] + JK = 2, + #[doc = "3: D latch"] + LATCH = 3, + #[doc = "4: RS latch"] + RS = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEQSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `SEQSEL` reader - Sequential Selection"] +pub struct SEQSEL_R(crate::FieldReader); +impl SEQSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SEQSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEQSEL_A::DISABLE), + 1 => Some(SEQSEL_A::DFF), + 2 => Some(SEQSEL_A::JK), + 3 => Some(SEQSEL_A::LATCH), + 4 => Some(SEQSEL_A::RS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == SEQSEL_A::DISABLE + } + #[doc = "Checks if the value of the field is `DFF`"] + #[inline(always)] + pub fn is_dff(&self) -> bool { + **self == SEQSEL_A::DFF + } + #[doc = "Checks if the value of the field is `JK`"] + #[inline(always)] + pub fn is_jk(&self) -> bool { + **self == SEQSEL_A::JK + } + #[doc = "Checks if the value of the field is `LATCH`"] + #[inline(always)] + pub fn is_latch(&self) -> bool { + **self == SEQSEL_A::LATCH + } + #[doc = "Checks if the value of the field is `RS`"] + #[inline(always)] + pub fn is_rs(&self) -> bool { + **self == SEQSEL_A::RS + } +} +impl core::ops::Deref for SEQSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEQSEL` writer - Sequential Selection"] +pub struct SEQSEL_W<'a> { + w: &'a mut W, +} +impl<'a> SEQSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SEQSEL_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Sequential logic is disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(SEQSEL_A::DISABLE) + } + #[doc = "D flip flop"] + #[inline(always)] + pub fn dff(self) -> &'a mut W { + self.variant(SEQSEL_A::DFF) + } + #[doc = "JK flip flop"] + #[inline(always)] + pub fn jk(self) -> &'a mut W { + self.variant(SEQSEL_A::JK) + } + #[doc = "D latch"] + #[inline(always)] + pub fn latch(self) -> &'a mut W { + self.variant(SEQSEL_A::LATCH) + } + #[doc = "RS latch"] + #[inline(always)] + pub fn rs(self) -> &'a mut W { + self.variant(SEQSEL_A::RS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Sequential Selection"] + #[inline(always)] + pub fn seqsel(&self) -> SEQSEL_R { + SEQSEL_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Sequential Selection"] + #[inline(always)] + pub fn seqsel(&mut self) -> SEQSEL_W { + SEQSEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SEQ Control x\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [seqctrl](index.html) module"] +pub struct SEQCTRL_SPEC; +impl crate::RegisterSpec for SEQCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [seqctrl::R](R) reader structure"] +impl crate::Readable for SEQCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [seqctrl::W](W) writer structure"] +impl crate::Writable for SEQCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SEQCTRL[%s] +to value 0"] +impl crate::Resettable for SEQCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/dac.rs b/pac/atsamc21e/src/dac.rs new file mode 100644 index 000000000000..255af9263600 --- /dev/null +++ b/pac/atsamc21e/src/dac.rs @@ -0,0 +1,73 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + #[doc = "0x01 - Control B"] + pub ctrlb: crate::Reg, + #[doc = "0x02 - Event Control"] + pub evctrl: crate::Reg, + _reserved3: [u8; 0x01], + #[doc = "0x04 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x05 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x06 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x07 - Status"] + pub status: crate::Reg, + #[doc = "0x08 - Data"] + pub data: crate::Reg, + _reserved8: [u8; 0x02], + #[doc = "0x0c - Data Buffer"] + pub databuf: crate::Reg, + _reserved9: [u8; 0x02], + #[doc = "0x10 - Synchronization Busy"] + pub syncbusy: crate::Reg, + #[doc = "0x14 - Debug Control"] + pub dbgctrl: crate::Reg, +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "Control B"] +pub mod ctrlb; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "Data"] +pub mod data; +#[doc = "DATABUF register accessor: an alias for `Reg`"] +pub type DATABUF = crate::Reg; +#[doc = "Data Buffer"] +pub mod databuf; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Busy"] +pub mod syncbusy; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; diff --git a/pac/atsamc21e/src/dac/ctrla.rs b/pac/atsamc21e/src/dac/ctrla.rs new file mode 100644 index 000000000000..3ff2fbd9c4d5 --- /dev/null +++ b/pac/atsamc21e/src/dac/ctrla.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/dac/ctrlb.rs b/pac/atsamc21e/src/dac/ctrlb.rs new file mode 100644 index 000000000000..ac7d537964e1 --- /dev/null +++ b/pac/atsamc21e/src/dac/ctrlb.rs @@ -0,0 +1,400 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EOEN` reader - External Output Enable"] +pub struct EOEN_R(crate::FieldReader); +impl EOEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EOEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EOEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EOEN` writer - External Output Enable"] +pub struct EOEN_W<'a> { + w: &'a mut W, +} +impl<'a> EOEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `IOEN` reader - Internal Output Enable"] +pub struct IOEN_R(crate::FieldReader); +impl IOEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IOEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IOEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IOEN` writer - Internal Output Enable"] +pub struct IOEN_W<'a> { + w: &'a mut W, +} +impl<'a> IOEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `LEFTADJ` reader - Left Adjusted Data"] +pub struct LEFTADJ_R(crate::FieldReader); +impl LEFTADJ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LEFTADJ_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LEFTADJ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LEFTADJ` writer - Left Adjusted Data"] +pub struct LEFTADJ_W<'a> { + w: &'a mut W, +} +impl<'a> LEFTADJ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `VPD` reader - Voltage Pump Disable"] +pub struct VPD_R(crate::FieldReader); +impl VPD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + VPD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VPD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VPD` writer - Voltage Pump Disable"] +pub struct VPD_W<'a> { + w: &'a mut W, +} +impl<'a> VPD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `DITHER` reader - Dither Enable"] +pub struct DITHER_R(crate::FieldReader); +impl DITHER_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DITHER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHER` writer - Dither Enable"] +pub struct DITHER_W<'a> { + w: &'a mut W, +} +impl<'a> DITHER_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Reference Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum REFSEL_A { + #[doc = "0: Internal 1.0V reference"] + INT1V = 0, + #[doc = "1: AVCC"] + AVCC = 1, + #[doc = "2: External reference"] + VREFP = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: REFSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `REFSEL` reader - Reference Selection"] +pub struct REFSEL_R(crate::FieldReader); +impl REFSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REFSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(REFSEL_A::INT1V), + 1 => Some(REFSEL_A::AVCC), + 2 => Some(REFSEL_A::VREFP), + _ => None, + } + } + #[doc = "Checks if the value of the field is `INT1V`"] + #[inline(always)] + pub fn is_int1v(&self) -> bool { + **self == REFSEL_A::INT1V + } + #[doc = "Checks if the value of the field is `AVCC`"] + #[inline(always)] + pub fn is_avcc(&self) -> bool { + **self == REFSEL_A::AVCC + } + #[doc = "Checks if the value of the field is `VREFP`"] + #[inline(always)] + pub fn is_vrefp(&self) -> bool { + **self == REFSEL_A::VREFP + } +} +impl core::ops::Deref for REFSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REFSEL` writer - Reference Selection"] +pub struct REFSEL_W<'a> { + w: &'a mut W, +} +impl<'a> REFSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: REFSEL_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Internal 1.0V reference"] + #[inline(always)] + pub fn int1v(self) -> &'a mut W { + self.variant(REFSEL_A::INT1V) + } + #[doc = "AVCC"] + #[inline(always)] + pub fn avcc(self) -> &'a mut W { + self.variant(REFSEL_A::AVCC) + } + #[doc = "External reference"] + #[inline(always)] + pub fn vrefp(self) -> &'a mut W { + self.variant(REFSEL_A::VREFP) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 6)) | ((value as u8 & 0x03) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - External Output Enable"] + #[inline(always)] + pub fn eoen(&self) -> EOEN_R { + EOEN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Internal Output Enable"] + #[inline(always)] + pub fn ioen(&self) -> IOEN_R { + IOEN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Left Adjusted Data"] + #[inline(always)] + pub fn leftadj(&self) -> LEFTADJ_R { + LEFTADJ_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Voltage Pump Disable"] + #[inline(always)] + pub fn vpd(&self) -> VPD_R { + VPD_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 5 - Dither Enable"] + #[inline(always)] + pub fn dither(&self) -> DITHER_R { + DITHER_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bits 6:7 - Reference Selection"] + #[inline(always)] + pub fn refsel(&self) -> REFSEL_R { + REFSEL_R::new(((self.bits >> 6) & 0x03) as u8) + } +} +impl W { + #[doc = "Bit 0 - External Output Enable"] + #[inline(always)] + pub fn eoen(&mut self) -> EOEN_W { + EOEN_W { w: self } + } + #[doc = "Bit 1 - Internal Output Enable"] + #[inline(always)] + pub fn ioen(&mut self) -> IOEN_W { + IOEN_W { w: self } + } + #[doc = "Bit 2 - Left Adjusted Data"] + #[inline(always)] + pub fn leftadj(&mut self) -> LEFTADJ_W { + LEFTADJ_W { w: self } + } + #[doc = "Bit 3 - Voltage Pump Disable"] + #[inline(always)] + pub fn vpd(&mut self) -> VPD_W { + VPD_W { w: self } + } + #[doc = "Bit 5 - Dither Enable"] + #[inline(always)] + pub fn dither(&mut self) -> DITHER_W { + DITHER_W { w: self } + } + #[doc = "Bits 6:7 - Reference Selection"] + #[inline(always)] + pub fn refsel(&mut self) -> REFSEL_W { + REFSEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/dac/data.rs b/pac/atsamc21e/src/dac/data.rs new file mode 100644 index 000000000000..d70d1a60e76f --- /dev/null +++ b/pac/atsamc21e/src/dac/data.rs @@ -0,0 +1,62 @@ +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` writer - Data value to be converted"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl W { + #[doc = "Bits 0:15 - Data value to be converted"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u16; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/dac/databuf.rs b/pac/atsamc21e/src/dac/databuf.rs new file mode 100644 index 000000000000..fc2aa61686cd --- /dev/null +++ b/pac/atsamc21e/src/dac/databuf.rs @@ -0,0 +1,62 @@ +#[doc = "Register `DATABUF` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATABUF` writer - Data Buffer"] +pub struct DATABUF_W<'a> { + w: &'a mut W, +} +impl<'a> DATABUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl W { + #[doc = "Bits 0:15 - Data Buffer"] + #[inline(always)] + pub fn databuf(&mut self) -> DATABUF_W { + DATABUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Buffer\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [databuf](index.html) module"] +pub struct DATABUF_SPEC; +impl crate::RegisterSpec for DATABUF_SPEC { + type Ux = u16; +} +#[doc = "`write(|w| ..)` method takes [databuf::W](W) writer structure"] +impl crate::Writable for DATABUF_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATABUF to value 0"] +impl crate::Resettable for DATABUF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/dac/dbgctrl.rs b/pac/atsamc21e/src/dac/dbgctrl.rs new file mode 100644 index 000000000000..53636eb2b339 --- /dev/null +++ b/pac/atsamc21e/src/dac/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Debug Run"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Debug Run"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/dac/evctrl.rs b/pac/atsamc21e/src/dac/evctrl.rs new file mode 100644 index 000000000000..1032a853887d --- /dev/null +++ b/pac/atsamc21e/src/dac/evctrl.rs @@ -0,0 +1,207 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `STARTEI` reader - Start Conversion Event Input"] +pub struct STARTEI_R(crate::FieldReader); +impl STARTEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STARTEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STARTEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STARTEI` writer - Start Conversion Event Input"] +pub struct STARTEI_W<'a> { + w: &'a mut W, +} +impl<'a> STARTEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `EMPTYEO` reader - Data Buffer Empty Event Output"] +pub struct EMPTYEO_R(crate::FieldReader); +impl EMPTYEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EMPTYEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EMPTYEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EMPTYEO` writer - Data Buffer Empty Event Output"] +pub struct EMPTYEO_W<'a> { + w: &'a mut W, +} +impl<'a> EMPTYEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `INVEI` reader - Invert Event Input"] +pub struct INVEI_R(crate::FieldReader); +impl INVEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEI` writer - Invert Event Input"] +pub struct INVEI_W<'a> { + w: &'a mut W, +} +impl<'a> INVEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Start Conversion Event Input"] + #[inline(always)] + pub fn startei(&self) -> STARTEI_R { + STARTEI_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Data Buffer Empty Event Output"] + #[inline(always)] + pub fn emptyeo(&self) -> EMPTYEO_R { + EMPTYEO_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Invert Event Input"] + #[inline(always)] + pub fn invei(&self) -> INVEI_R { + INVEI_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Start Conversion Event Input"] + #[inline(always)] + pub fn startei(&mut self) -> STARTEI_W { + STARTEI_W { w: self } + } + #[doc = "Bit 1 - Data Buffer Empty Event Output"] + #[inline(always)] + pub fn emptyeo(&mut self) -> EMPTYEO_W { + EMPTYEO_W { w: self } + } + #[doc = "Bit 2 - Invert Event Input"] + #[inline(always)] + pub fn invei(&mut self) -> INVEI_W { + INVEI_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/dac/intenclr.rs b/pac/atsamc21e/src/dac/intenclr.rs new file mode 100644 index 000000000000..408feebf63ca --- /dev/null +++ b/pac/atsamc21e/src/dac/intenclr.rs @@ -0,0 +1,160 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `UNDERRUN` reader - Underrun Interrupt Enable"] +pub struct UNDERRUN_R(crate::FieldReader); +impl UNDERRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UNDERRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for UNDERRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `UNDERRUN` writer - Underrun Interrupt Enable"] +pub struct UNDERRUN_W<'a> { + w: &'a mut W, +} +impl<'a> UNDERRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `EMPTY` reader - Data Buffer Empty Interrupt Enable"] +pub struct EMPTY_R(crate::FieldReader); +impl EMPTY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EMPTY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EMPTY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EMPTY` writer - Data Buffer Empty Interrupt Enable"] +pub struct EMPTY_W<'a> { + w: &'a mut W, +} +impl<'a> EMPTY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - Underrun Interrupt Enable"] + #[inline(always)] + pub fn underrun(&self) -> UNDERRUN_R { + UNDERRUN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Data Buffer Empty Interrupt Enable"] + #[inline(always)] + pub fn empty(&self) -> EMPTY_R { + EMPTY_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Underrun Interrupt Enable"] + #[inline(always)] + pub fn underrun(&mut self) -> UNDERRUN_W { + UNDERRUN_W { w: self } + } + #[doc = "Bit 1 - Data Buffer Empty Interrupt Enable"] + #[inline(always)] + pub fn empty(&mut self) -> EMPTY_W { + EMPTY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/dac/intenset.rs b/pac/atsamc21e/src/dac/intenset.rs new file mode 100644 index 000000000000..db38e69ed2e5 --- /dev/null +++ b/pac/atsamc21e/src/dac/intenset.rs @@ -0,0 +1,160 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `UNDERRUN` reader - Underrun Interrupt Enable"] +pub struct UNDERRUN_R(crate::FieldReader); +impl UNDERRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UNDERRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for UNDERRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `UNDERRUN` writer - Underrun Interrupt Enable"] +pub struct UNDERRUN_W<'a> { + w: &'a mut W, +} +impl<'a> UNDERRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `EMPTY` reader - Data Buffer Empty Interrupt Enable"] +pub struct EMPTY_R(crate::FieldReader); +impl EMPTY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EMPTY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EMPTY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EMPTY` writer - Data Buffer Empty Interrupt Enable"] +pub struct EMPTY_W<'a> { + w: &'a mut W, +} +impl<'a> EMPTY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - Underrun Interrupt Enable"] + #[inline(always)] + pub fn underrun(&self) -> UNDERRUN_R { + UNDERRUN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Data Buffer Empty Interrupt Enable"] + #[inline(always)] + pub fn empty(&self) -> EMPTY_R { + EMPTY_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Underrun Interrupt Enable"] + #[inline(always)] + pub fn underrun(&mut self) -> UNDERRUN_W { + UNDERRUN_W { w: self } + } + #[doc = "Bit 1 - Data Buffer Empty Interrupt Enable"] + #[inline(always)] + pub fn empty(&mut self) -> EMPTY_W { + EMPTY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/dac/intflag.rs b/pac/atsamc21e/src/dac/intflag.rs new file mode 100644 index 000000000000..6779ed161d08 --- /dev/null +++ b/pac/atsamc21e/src/dac/intflag.rs @@ -0,0 +1,160 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `UNDERRUN` reader - Underrun"] +pub struct UNDERRUN_R(crate::FieldReader); +impl UNDERRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UNDERRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for UNDERRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `UNDERRUN` writer - Underrun"] +pub struct UNDERRUN_W<'a> { + w: &'a mut W, +} +impl<'a> UNDERRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `EMPTY` reader - Data Buffer Empty"] +pub struct EMPTY_R(crate::FieldReader); +impl EMPTY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EMPTY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EMPTY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EMPTY` writer - Data Buffer Empty"] +pub struct EMPTY_W<'a> { + w: &'a mut W, +} +impl<'a> EMPTY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - Underrun"] + #[inline(always)] + pub fn underrun(&self) -> UNDERRUN_R { + UNDERRUN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Data Buffer Empty"] + #[inline(always)] + pub fn empty(&self) -> EMPTY_R { + EMPTY_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Underrun"] + #[inline(always)] + pub fn underrun(&mut self) -> UNDERRUN_W { + UNDERRUN_W { w: self } + } + #[doc = "Bit 1 - Data Buffer Empty"] + #[inline(always)] + pub fn empty(&mut self) -> EMPTY_W { + EMPTY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/dac/status.rs b/pac/atsamc21e/src/dac/status.rs new file mode 100644 index 000000000000..9b5a27716dab --- /dev/null +++ b/pac/atsamc21e/src/dac/status.rs @@ -0,0 +1,53 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `READY` reader - Ready"] +pub struct READY_R(crate::FieldReader); +impl READY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + READY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for READY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Ready"] + #[inline(always)] + pub fn ready(&self) -> READY_R { + READY_R::new((self.bits & 0x01) != 0) + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/dac/syncbusy.rs b/pac/atsamc21e/src/dac/syncbusy.rs new file mode 100644 index 000000000000..490533dae28e --- /dev/null +++ b/pac/atsamc21e/src/dac/syncbusy.rs @@ -0,0 +1,113 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` reader - Data"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATABUF` reader - Data Buffer"] +pub struct DATABUF_R(crate::FieldReader); +impl DATABUF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DATABUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATABUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Data"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Data Buffer"] + #[inline(always)] + pub fn databuf(&self) -> DATABUF_R { + DATABUF_R::new(((self.bits >> 3) & 0x01) != 0) + } +} +#[doc = "Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/divas.rs b/pac/atsamc21e/src/divas.rs new file mode 100644 index 000000000000..dbc2f5f226da --- /dev/null +++ b/pac/atsamc21e/src/divas.rs @@ -0,0 +1,48 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrla: crate::Reg, + _reserved1: [u8; 0x03], + #[doc = "0x04 - Status"] + pub status: crate::Reg, + _reserved2: [u8; 0x03], + #[doc = "0x08 - Dividend"] + pub dividend: crate::Reg, + #[doc = "0x0c - Divisor"] + pub divisor: crate::Reg, + #[doc = "0x10 - Result"] + pub result: crate::Reg, + #[doc = "0x14 - Remainder"] + pub rem: crate::Reg, + #[doc = "0x18 - Square Root Input"] + pub sqrnum: crate::Reg, +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control"] +pub mod ctrla; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "DIVIDEND register accessor: an alias for `Reg`"] +pub type DIVIDEND = crate::Reg; +#[doc = "Dividend"] +pub mod dividend; +#[doc = "DIVISOR register accessor: an alias for `Reg`"] +pub type DIVISOR = crate::Reg; +#[doc = "Divisor"] +pub mod divisor; +#[doc = "RESULT register accessor: an alias for `Reg`"] +pub type RESULT = crate::Reg; +#[doc = "Result"] +pub mod result; +#[doc = "REM register accessor: an alias for `Reg`"] +pub type REM = crate::Reg; +#[doc = "Remainder"] +pub mod rem; +#[doc = "SQRNUM register accessor: an alias for `Reg`"] +pub type SQRNUM = crate::Reg; +#[doc = "Square Root Input"] +pub mod sqrnum; diff --git a/pac/atsamc21e/src/divas/ctrla.rs b/pac/atsamc21e/src/divas/ctrla.rs new file mode 100644 index 000000000000..7f79349da05c --- /dev/null +++ b/pac/atsamc21e/src/divas/ctrla.rs @@ -0,0 +1,160 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SIGNED` reader - Signed"] +pub struct SIGNED_R(crate::FieldReader); +impl SIGNED_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SIGNED_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SIGNED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SIGNED` writer - Signed"] +pub struct SIGNED_W<'a> { + w: &'a mut W, +} +impl<'a> SIGNED_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `DLZ` reader - Disable Leading Zero Optimization"] +pub struct DLZ_R(crate::FieldReader); +impl DLZ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DLZ_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DLZ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DLZ` writer - Disable Leading Zero Optimization"] +pub struct DLZ_W<'a> { + w: &'a mut W, +} +impl<'a> DLZ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - Signed"] + #[inline(always)] + pub fn signed(&self) -> SIGNED_R { + SIGNED_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Disable Leading Zero Optimization"] + #[inline(always)] + pub fn dlz(&self) -> DLZ_R { + DLZ_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Signed"] + #[inline(always)] + pub fn signed(&mut self) -> SIGNED_W { + SIGNED_W { w: self } + } + #[doc = "Bit 1 - Disable Leading Zero Optimization"] + #[inline(always)] + pub fn dlz(&mut self) -> DLZ_W { + DLZ_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/divas/dividend.rs b/pac/atsamc21e/src/divas/dividend.rs new file mode 100644 index 000000000000..215f44261a6c --- /dev/null +++ b/pac/atsamc21e/src/divas/dividend.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DIVIDEND` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIVIDEND` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIVIDEND` reader - DIVIDEND"] +pub struct DIVIDEND_R(crate::FieldReader); +impl DIVIDEND_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + DIVIDEND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIVIDEND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIVIDEND` writer - DIVIDEND"] +pub struct DIVIDEND_W<'a> { + w: &'a mut W, +} +impl<'a> DIVIDEND_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - DIVIDEND"] + #[inline(always)] + pub fn dividend(&self) -> DIVIDEND_R { + DIVIDEND_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - DIVIDEND"] + #[inline(always)] + pub fn dividend(&mut self) -> DIVIDEND_W { + DIVIDEND_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Dividend\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dividend](index.html) module"] +pub struct DIVIDEND_SPEC; +impl crate::RegisterSpec for DIVIDEND_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dividend::R](R) reader structure"] +impl crate::Readable for DIVIDEND_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dividend::W](W) writer structure"] +impl crate::Writable for DIVIDEND_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DIVIDEND to value 0"] +impl crate::Resettable for DIVIDEND_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/divas/divisor.rs b/pac/atsamc21e/src/divas/divisor.rs new file mode 100644 index 000000000000..b711870a5cd6 --- /dev/null +++ b/pac/atsamc21e/src/divas/divisor.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DIVISOR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIVISOR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIVISOR` reader - DIVISOR"] +pub struct DIVISOR_R(crate::FieldReader); +impl DIVISOR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + DIVISOR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIVISOR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIVISOR` writer - DIVISOR"] +pub struct DIVISOR_W<'a> { + w: &'a mut W, +} +impl<'a> DIVISOR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - DIVISOR"] + #[inline(always)] + pub fn divisor(&self) -> DIVISOR_R { + DIVISOR_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - DIVISOR"] + #[inline(always)] + pub fn divisor(&mut self) -> DIVISOR_W { + DIVISOR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Divisor\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [divisor](index.html) module"] +pub struct DIVISOR_SPEC; +impl crate::RegisterSpec for DIVISOR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [divisor::R](R) reader structure"] +impl crate::Readable for DIVISOR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [divisor::W](W) writer structure"] +impl crate::Writable for DIVISOR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DIVISOR to value 0"] +impl crate::Resettable for DIVISOR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/divas/rem.rs b/pac/atsamc21e/src/divas/rem.rs new file mode 100644 index 000000000000..76f3a90878ed --- /dev/null +++ b/pac/atsamc21e/src/divas/rem.rs @@ -0,0 +1,53 @@ +#[doc = "Register `REM` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `REM` reader - REM"] +pub struct REM_R(crate::FieldReader); +impl REM_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + REM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - REM"] + #[inline(always)] + pub fn rem(&self) -> REM_R { + REM_R::new(self.bits as u32) + } +} +#[doc = "Remainder\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rem](index.html) module"] +pub struct REM_SPEC; +impl crate::RegisterSpec for REM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rem::R](R) reader structure"] +impl crate::Readable for REM_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets REM to value 0"] +impl crate::Resettable for REM_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/divas/result.rs b/pac/atsamc21e/src/divas/result.rs new file mode 100644 index 000000000000..85fc1a025f9e --- /dev/null +++ b/pac/atsamc21e/src/divas/result.rs @@ -0,0 +1,53 @@ +#[doc = "Register `RESULT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `RESULT` reader - RESULT"] +pub struct RESULT_R(crate::FieldReader); +impl RESULT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + RESULT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESULT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - RESULT"] + #[inline(always)] + pub fn result(&self) -> RESULT_R { + RESULT_R::new(self.bits as u32) + } +} +#[doc = "Result\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [result](index.html) module"] +pub struct RESULT_SPEC; +impl crate::RegisterSpec for RESULT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [result::R](R) reader structure"] +impl crate::Readable for RESULT_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets RESULT to value 0"] +impl crate::Resettable for RESULT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/divas/sqrnum.rs b/pac/atsamc21e/src/divas/sqrnum.rs new file mode 100644 index 000000000000..cc0ce6806beb --- /dev/null +++ b/pac/atsamc21e/src/divas/sqrnum.rs @@ -0,0 +1,103 @@ +#[doc = "Register `SQRNUM` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SQRNUM` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SQRNUM` reader - Square Root Input"] +pub struct SQRNUM_R(crate::FieldReader); +impl SQRNUM_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + SQRNUM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SQRNUM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SQRNUM` writer - Square Root Input"] +pub struct SQRNUM_W<'a> { + w: &'a mut W, +} +impl<'a> SQRNUM_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Square Root Input"] + #[inline(always)] + pub fn sqrnum(&self) -> SQRNUM_R { + SQRNUM_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Square Root Input"] + #[inline(always)] + pub fn sqrnum(&mut self) -> SQRNUM_W { + SQRNUM_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Square Root Input\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sqrnum](index.html) module"] +pub struct SQRNUM_SPEC; +impl crate::RegisterSpec for SQRNUM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [sqrnum::R](R) reader structure"] +impl crate::Readable for SQRNUM_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [sqrnum::W](W) writer structure"] +impl crate::Writable for SQRNUM_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SQRNUM to value 0"] +impl crate::Resettable for SQRNUM_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/divas/status.rs b/pac/atsamc21e/src/divas/status.rs new file mode 100644 index 000000000000..feffbccec659 --- /dev/null +++ b/pac/atsamc21e/src/divas/status.rs @@ -0,0 +1,160 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BUSY` reader - DIVAS Accelerator Busy"] +pub struct BUSY_R(crate::FieldReader); +impl BUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSY` writer - DIVAS Accelerator Busy"] +pub struct BUSY_W<'a> { + w: &'a mut W, +} +impl<'a> BUSY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `DBZ` reader - Writing a one to this bit clears DBZ to zero"] +pub struct DBZ_R(crate::FieldReader); +impl DBZ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBZ_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBZ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBZ` writer - Writing a one to this bit clears DBZ to zero"] +pub struct DBZ_W<'a> { + w: &'a mut W, +} +impl<'a> DBZ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - DIVAS Accelerator Busy"] + #[inline(always)] + pub fn busy(&self) -> BUSY_R { + BUSY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Writing a one to this bit clears DBZ to zero"] + #[inline(always)] + pub fn dbz(&self) -> DBZ_R { + DBZ_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - DIVAS Accelerator Busy"] + #[inline(always)] + pub fn busy(&mut self) -> BUSY_W { + BUSY_W { w: self } + } + #[doc = "Bit 1 - Writing a one to this bit clears DBZ to zero"] + #[inline(always)] + pub fn dbz(&mut self) -> DBZ_W { + DBZ_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/dmac.rs b/pac/atsamc21e/src/dmac.rs new file mode 100644 index 000000000000..c23d36697550 --- /dev/null +++ b/pac/atsamc21e/src/dmac.rs @@ -0,0 +1,148 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrl: crate::Reg, + #[doc = "0x02 - CRC Control"] + pub crcctrl: crate::Reg, + #[doc = "0x04 - CRC Data Input"] + pub crcdatain: crate::Reg, + #[doc = "0x08 - CRC Checksum"] + pub crcchksum: crate::Reg, + #[doc = "0x0c - CRC Status"] + pub crcstatus: crate::Reg, + #[doc = "0x0d - Debug Control"] + pub dbgctrl: crate::Reg, + #[doc = "0x0e - QOS Control"] + pub qosctrl: crate::Reg, + _reserved7: [u8; 0x01], + #[doc = "0x10 - Software Trigger Control"] + pub swtrigctrl: crate::Reg, + #[doc = "0x14 - Priority Control 0"] + pub prictrl0: crate::Reg, + _reserved9: [u8; 0x08], + #[doc = "0x20 - Interrupt Pending"] + pub intpend: crate::Reg, + _reserved10: [u8; 0x02], + #[doc = "0x24 - Interrupt Status"] + pub intstatus: crate::Reg, + #[doc = "0x28 - Busy Channels"] + pub busych: crate::Reg, + #[doc = "0x2c - Pending Channels"] + pub pendch: crate::Reg, + #[doc = "0x30 - Active Channel and Levels"] + pub active: crate::Reg, + #[doc = "0x34 - Descriptor Memory Section Base Address"] + pub baseaddr: crate::Reg, + #[doc = "0x38 - Write-Back Memory Section Base Address"] + pub wrbaddr: crate::Reg, + _reserved16: [u8; 0x03], + #[doc = "0x3f - Channel ID"] + pub chid: crate::Reg, + #[doc = "0x40 - Channel Control A"] + pub chctrla: crate::Reg, + _reserved18: [u8; 0x03], + #[doc = "0x44 - Channel Control B"] + pub chctrlb: crate::Reg, + _reserved19: [u8; 0x04], + #[doc = "0x4c - Channel Interrupt Enable Clear"] + pub chintenclr: crate::Reg, + #[doc = "0x4d - Channel Interrupt Enable Set"] + pub chintenset: crate::Reg, + #[doc = "0x4e - Channel Interrupt Flag Status and Clear"] + pub chintflag: crate::Reg, + #[doc = "0x4f - Channel Status"] + pub chstatus: crate::Reg, +} +#[doc = "CTRL register accessor: an alias for `Reg`"] +pub type CTRL = crate::Reg; +#[doc = "Control"] +pub mod ctrl; +#[doc = "CRCCTRL register accessor: an alias for `Reg`"] +pub type CRCCTRL = crate::Reg; +#[doc = "CRC Control"] +pub mod crcctrl; +#[doc = "CRCDATAIN register accessor: an alias for `Reg`"] +pub type CRCDATAIN = crate::Reg; +#[doc = "CRC Data Input"] +pub mod crcdatain; +#[doc = "CRCCHKSUM register accessor: an alias for `Reg`"] +pub type CRCCHKSUM = crate::Reg; +#[doc = "CRC Checksum"] +pub mod crcchksum; +#[doc = "CRCSTATUS register accessor: an alias for `Reg`"] +pub type CRCSTATUS = crate::Reg; +#[doc = "CRC Status"] +pub mod crcstatus; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "QOSCTRL register accessor: an alias for `Reg`"] +pub type QOSCTRL = crate::Reg; +#[doc = "QOS Control"] +pub mod qosctrl; +#[doc = "SWTRIGCTRL register accessor: an alias for `Reg`"] +pub type SWTRIGCTRL = crate::Reg; +#[doc = "Software Trigger Control"] +pub mod swtrigctrl; +#[doc = "PRICTRL0 register accessor: an alias for `Reg`"] +pub type PRICTRL0 = crate::Reg; +#[doc = "Priority Control 0"] +pub mod prictrl0; +#[doc = "INTPEND register accessor: an alias for `Reg`"] +pub type INTPEND = crate::Reg; +#[doc = "Interrupt Pending"] +pub mod intpend; +#[doc = "INTSTATUS register accessor: an alias for `Reg`"] +pub type INTSTATUS = crate::Reg; +#[doc = "Interrupt Status"] +pub mod intstatus; +#[doc = "BUSYCH register accessor: an alias for `Reg`"] +pub type BUSYCH = crate::Reg; +#[doc = "Busy Channels"] +pub mod busych; +#[doc = "PENDCH register accessor: an alias for `Reg`"] +pub type PENDCH = crate::Reg; +#[doc = "Pending Channels"] +pub mod pendch; +#[doc = "ACTIVE register accessor: an alias for `Reg`"] +pub type ACTIVE = crate::Reg; +#[doc = "Active Channel and Levels"] +pub mod active; +#[doc = "BASEADDR register accessor: an alias for `Reg`"] +pub type BASEADDR = crate::Reg; +#[doc = "Descriptor Memory Section Base Address"] +pub mod baseaddr; +#[doc = "WRBADDR register accessor: an alias for `Reg`"] +pub type WRBADDR = crate::Reg; +#[doc = "Write-Back Memory Section Base Address"] +pub mod wrbaddr; +#[doc = "CHID register accessor: an alias for `Reg`"] +pub type CHID = crate::Reg; +#[doc = "Channel ID"] +pub mod chid; +#[doc = "CHCTRLA register accessor: an alias for `Reg`"] +pub type CHCTRLA = crate::Reg; +#[doc = "Channel Control A"] +pub mod chctrla; +#[doc = "CHCTRLB register accessor: an alias for `Reg`"] +pub type CHCTRLB = crate::Reg; +#[doc = "Channel Control B"] +pub mod chctrlb; +#[doc = "CHINTENCLR register accessor: an alias for `Reg`"] +pub type CHINTENCLR = crate::Reg; +#[doc = "Channel Interrupt Enable Clear"] +pub mod chintenclr; +#[doc = "CHINTENSET register accessor: an alias for `Reg`"] +pub type CHINTENSET = crate::Reg; +#[doc = "Channel Interrupt Enable Set"] +pub mod chintenset; +#[doc = "CHINTFLAG register accessor: an alias for `Reg`"] +pub type CHINTFLAG = crate::Reg; +#[doc = "Channel Interrupt Flag Status and Clear"] +pub mod chintflag; +#[doc = "CHSTATUS register accessor: an alias for `Reg`"] +pub type CHSTATUS = crate::Reg; +#[doc = "Channel Status"] +pub mod chstatus; diff --git a/pac/atsamc21e/src/dmac/active.rs b/pac/atsamc21e/src/dmac/active.rs new file mode 100644 index 000000000000..c3cc5a0420bc --- /dev/null +++ b/pac/atsamc21e/src/dmac/active.rs @@ -0,0 +1,173 @@ +#[doc = "Register `ACTIVE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `LVLEX0` reader - Level 0 Channel Trigger Request Executing"] +pub struct LVLEX0_R(crate::FieldReader); +impl LVLEX0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LVLEX0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEX0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLEX1` reader - Level 1 Channel Trigger Request Executing"] +pub struct LVLEX1_R(crate::FieldReader); +impl LVLEX1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LVLEX1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEX1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLEX2` reader - Level 2 Channel Trigger Request Executing"] +pub struct LVLEX2_R(crate::FieldReader); +impl LVLEX2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LVLEX2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEX2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLEX3` reader - Level 3 Channel Trigger Request Executing"] +pub struct LVLEX3_R(crate::FieldReader); +impl LVLEX3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LVLEX3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEX3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ID` reader - Active Channel ID"] +pub struct ID_R(crate::FieldReader); +impl ID_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ID_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ID_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ABUSY` reader - Active Channel Busy"] +pub struct ABUSY_R(crate::FieldReader); +impl ABUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ABUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ABUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BTCNT` reader - Active Channel Block Transfer Count"] +pub struct BTCNT_R(crate::FieldReader); +impl BTCNT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BTCNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BTCNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Level 0 Channel Trigger Request Executing"] + #[inline(always)] + pub fn lvlex0(&self) -> LVLEX0_R { + LVLEX0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Level 1 Channel Trigger Request Executing"] + #[inline(always)] + pub fn lvlex1(&self) -> LVLEX1_R { + LVLEX1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Level 2 Channel Trigger Request Executing"] + #[inline(always)] + pub fn lvlex2(&self) -> LVLEX2_R { + LVLEX2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Level 3 Channel Trigger Request Executing"] + #[inline(always)] + pub fn lvlex3(&self) -> LVLEX3_R { + LVLEX3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bits 8:12 - Active Channel ID"] + #[inline(always)] + pub fn id(&self) -> ID_R { + ID_R::new(((self.bits >> 8) & 0x1f) as u8) + } + #[doc = "Bit 15 - Active Channel Busy"] + #[inline(always)] + pub fn abusy(&self) -> ABUSY_R { + ABUSY_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:31 - Active Channel Block Transfer Count"] + #[inline(always)] + pub fn btcnt(&self) -> BTCNT_R { + BTCNT_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[doc = "Active Channel and Levels\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [active](index.html) module"] +pub struct ACTIVE_SPEC; +impl crate::RegisterSpec for ACTIVE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [active::R](R) reader structure"] +impl crate::Readable for ACTIVE_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets ACTIVE to value 0"] +impl crate::Resettable for ACTIVE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/dmac/baseaddr.rs b/pac/atsamc21e/src/dmac/baseaddr.rs new file mode 100644 index 000000000000..cec8c8cf0777 --- /dev/null +++ b/pac/atsamc21e/src/dmac/baseaddr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `BASEADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BASEADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BASEADDR` reader - Descriptor Memory Base Address"] +pub struct BASEADDR_R(crate::FieldReader); +impl BASEADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + BASEADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BASEADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BASEADDR` writer - Descriptor Memory Base Address"] +pub struct BASEADDR_W<'a> { + w: &'a mut W, +} +impl<'a> BASEADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Descriptor Memory Base Address"] + #[inline(always)] + pub fn baseaddr(&self) -> BASEADDR_R { + BASEADDR_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Descriptor Memory Base Address"] + #[inline(always)] + pub fn baseaddr(&mut self) -> BASEADDR_W { + BASEADDR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Descriptor Memory Section Base Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baseaddr](index.html) module"] +pub struct BASEADDR_SPEC; +impl crate::RegisterSpec for BASEADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [baseaddr::R](R) reader structure"] +impl crate::Readable for BASEADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baseaddr::W](W) writer structure"] +impl crate::Writable for BASEADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BASEADDR to value 0"] +impl crate::Resettable for BASEADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/dmac/busych.rs b/pac/atsamc21e/src/dmac/busych.rs new file mode 100644 index 000000000000..6f9419d5828b --- /dev/null +++ b/pac/atsamc21e/src/dmac/busych.rs @@ -0,0 +1,273 @@ +#[doc = "Register `BUSYCH` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `BUSYCH0` reader - Busy Channel 0"] +pub struct BUSYCH0_R(crate::FieldReader); +impl BUSYCH0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH1` reader - Busy Channel 1"] +pub struct BUSYCH1_R(crate::FieldReader); +impl BUSYCH1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH2` reader - Busy Channel 2"] +pub struct BUSYCH2_R(crate::FieldReader); +impl BUSYCH2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH3` reader - Busy Channel 3"] +pub struct BUSYCH3_R(crate::FieldReader); +impl BUSYCH3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH4` reader - Busy Channel 4"] +pub struct BUSYCH4_R(crate::FieldReader); +impl BUSYCH4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH5` reader - Busy Channel 5"] +pub struct BUSYCH5_R(crate::FieldReader); +impl BUSYCH5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH6` reader - Busy Channel 6"] +pub struct BUSYCH6_R(crate::FieldReader); +impl BUSYCH6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH7` reader - Busy Channel 7"] +pub struct BUSYCH7_R(crate::FieldReader); +impl BUSYCH7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH8` reader - Busy Channel 8"] +pub struct BUSYCH8_R(crate::FieldReader); +impl BUSYCH8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH9` reader - Busy Channel 9"] +pub struct BUSYCH9_R(crate::FieldReader); +impl BUSYCH9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH10` reader - Busy Channel 10"] +pub struct BUSYCH10_R(crate::FieldReader); +impl BUSYCH10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH11` reader - Busy Channel 11"] +pub struct BUSYCH11_R(crate::FieldReader); +impl BUSYCH11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Busy Channel 0"] + #[inline(always)] + pub fn busych0(&self) -> BUSYCH0_R { + BUSYCH0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Busy Channel 1"] + #[inline(always)] + pub fn busych1(&self) -> BUSYCH1_R { + BUSYCH1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Busy Channel 2"] + #[inline(always)] + pub fn busych2(&self) -> BUSYCH2_R { + BUSYCH2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Busy Channel 3"] + #[inline(always)] + pub fn busych3(&self) -> BUSYCH3_R { + BUSYCH3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Busy Channel 4"] + #[inline(always)] + pub fn busych4(&self) -> BUSYCH4_R { + BUSYCH4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Busy Channel 5"] + #[inline(always)] + pub fn busych5(&self) -> BUSYCH5_R { + BUSYCH5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Busy Channel 6"] + #[inline(always)] + pub fn busych6(&self) -> BUSYCH6_R { + BUSYCH6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Busy Channel 7"] + #[inline(always)] + pub fn busych7(&self) -> BUSYCH7_R { + BUSYCH7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Busy Channel 8"] + #[inline(always)] + pub fn busych8(&self) -> BUSYCH8_R { + BUSYCH8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Busy Channel 9"] + #[inline(always)] + pub fn busych9(&self) -> BUSYCH9_R { + BUSYCH9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Busy Channel 10"] + #[inline(always)] + pub fn busych10(&self) -> BUSYCH10_R { + BUSYCH10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Busy Channel 11"] + #[inline(always)] + pub fn busych11(&self) -> BUSYCH11_R { + BUSYCH11_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +#[doc = "Busy Channels\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [busych](index.html) module"] +pub struct BUSYCH_SPEC; +impl crate::RegisterSpec for BUSYCH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [busych::R](R) reader structure"] +impl crate::Readable for BUSYCH_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets BUSYCH to value 0"] +impl crate::Resettable for BUSYCH_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/dmac/chctrla.rs b/pac/atsamc21e/src/dmac/chctrla.rs new file mode 100644 index 000000000000..22e8d456e05c --- /dev/null +++ b/pac/atsamc21e/src/dmac/chctrla.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CHCTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHCTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Channel Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Channel Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Channel Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Channel Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Channel run in standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Channel run in standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - Channel Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 6 - Channel run in standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Channel Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 6 - Channel run in standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chctrla](index.html) module"] +pub struct CHCTRLA_SPEC; +impl crate::RegisterSpec for CHCTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [chctrla::R](R) reader structure"] +impl crate::Readable for CHCTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chctrla::W](W) writer structure"] +impl crate::Writable for CHCTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHCTRLA to value 0"] +impl crate::Resettable for CHCTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/dmac/chctrlb.rs b/pac/atsamc21e/src/dmac/chctrlb.rs new file mode 100644 index 000000000000..9f672e39ab11 --- /dev/null +++ b/pac/atsamc21e/src/dmac/chctrlb.rs @@ -0,0 +1,1253 @@ +#[doc = "Register `CHCTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHCTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Event Input Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EVACT_A { + #[doc = "0: No action"] + NOACT = 0, + #[doc = "1: Transfer and periodic transfer trigger"] + TRIG = 1, + #[doc = "2: Conditional transfer trigger"] + CTRIG = 2, + #[doc = "3: Conditional block transfer"] + CBLOCK = 3, + #[doc = "4: Channel suspend operation"] + SUSPEND = 4, + #[doc = "5: Channel resume operation"] + RESUME = 5, + #[doc = "6: Skip next block suspend action"] + SSKIP = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EVACT_A) -> Self { + variant as _ + } +} +#[doc = "Field `EVACT` reader - Event Input Action"] +pub struct EVACT_R(crate::FieldReader); +impl EVACT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(EVACT_A::NOACT), + 1 => Some(EVACT_A::TRIG), + 2 => Some(EVACT_A::CTRIG), + 3 => Some(EVACT_A::CBLOCK), + 4 => Some(EVACT_A::SUSPEND), + 5 => Some(EVACT_A::RESUME), + 6 => Some(EVACT_A::SSKIP), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NOACT`"] + #[inline(always)] + pub fn is_noact(&self) -> bool { + **self == EVACT_A::NOACT + } + #[doc = "Checks if the value of the field is `TRIG`"] + #[inline(always)] + pub fn is_trig(&self) -> bool { + **self == EVACT_A::TRIG + } + #[doc = "Checks if the value of the field is `CTRIG`"] + #[inline(always)] + pub fn is_ctrig(&self) -> bool { + **self == EVACT_A::CTRIG + } + #[doc = "Checks if the value of the field is `CBLOCK`"] + #[inline(always)] + pub fn is_cblock(&self) -> bool { + **self == EVACT_A::CBLOCK + } + #[doc = "Checks if the value of the field is `SUSPEND`"] + #[inline(always)] + pub fn is_suspend(&self) -> bool { + **self == EVACT_A::SUSPEND + } + #[doc = "Checks if the value of the field is `RESUME`"] + #[inline(always)] + pub fn is_resume(&self) -> bool { + **self == EVACT_A::RESUME + } + #[doc = "Checks if the value of the field is `SSKIP`"] + #[inline(always)] + pub fn is_sskip(&self) -> bool { + **self == EVACT_A::SSKIP + } +} +impl core::ops::Deref for EVACT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT` writer - Event Input Action"] +pub struct EVACT_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EVACT_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn noact(self) -> &'a mut W { + self.variant(EVACT_A::NOACT) + } + #[doc = "Transfer and periodic transfer trigger"] + #[inline(always)] + pub fn trig(self) -> &'a mut W { + self.variant(EVACT_A::TRIG) + } + #[doc = "Conditional transfer trigger"] + #[inline(always)] + pub fn ctrig(self) -> &'a mut W { + self.variant(EVACT_A::CTRIG) + } + #[doc = "Conditional block transfer"] + #[inline(always)] + pub fn cblock(self) -> &'a mut W { + self.variant(EVACT_A::CBLOCK) + } + #[doc = "Channel suspend operation"] + #[inline(always)] + pub fn suspend(self) -> &'a mut W { + self.variant(EVACT_A::SUSPEND) + } + #[doc = "Channel resume operation"] + #[inline(always)] + pub fn resume(self) -> &'a mut W { + self.variant(EVACT_A::RESUME) + } + #[doc = "Skip next block suspend action"] + #[inline(always)] + pub fn sskip(self) -> &'a mut W { + self.variant(EVACT_A::SSKIP) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Field `EVIE` reader - Channel Event Input Enable"] +pub struct EVIE_R(crate::FieldReader); +impl EVIE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVIE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVIE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVIE` writer - Channel Event Input Enable"] +pub struct EVIE_W<'a> { + w: &'a mut W, +} +impl<'a> EVIE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `EVOE` reader - Channel Event Output Enable"] +pub struct EVOE_R(crate::FieldReader); +impl EVOE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVOE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVOE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVOE` writer - Channel Event Output Enable"] +pub struct EVOE_W<'a> { + w: &'a mut W, +} +impl<'a> EVOE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Channel Arbitration Level\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum LVL_A { + #[doc = "0: Channel Priority Level 0"] + LVL0 = 0, + #[doc = "1: Channel Priority Level 1"] + LVL1 = 1, + #[doc = "2: Channel Priority Level 2"] + LVL2 = 2, + #[doc = "3: Channel Priority Level 3"] + LVL3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LVL_A) -> Self { + variant as _ + } +} +#[doc = "Field `LVL` reader - Channel Arbitration Level"] +pub struct LVL_R(crate::FieldReader); +impl LVL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LVL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> LVL_A { + match self.bits { + 0 => LVL_A::LVL0, + 1 => LVL_A::LVL1, + 2 => LVL_A::LVL2, + 3 => LVL_A::LVL3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `LVL0`"] + #[inline(always)] + pub fn is_lvl0(&self) -> bool { + **self == LVL_A::LVL0 + } + #[doc = "Checks if the value of the field is `LVL1`"] + #[inline(always)] + pub fn is_lvl1(&self) -> bool { + **self == LVL_A::LVL1 + } + #[doc = "Checks if the value of the field is `LVL2`"] + #[inline(always)] + pub fn is_lvl2(&self) -> bool { + **self == LVL_A::LVL2 + } + #[doc = "Checks if the value of the field is `LVL3`"] + #[inline(always)] + pub fn is_lvl3(&self) -> bool { + **self == LVL_A::LVL3 + } +} +impl core::ops::Deref for LVL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVL` writer - Channel Arbitration Level"] +pub struct LVL_W<'a> { + w: &'a mut W, +} +impl<'a> LVL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: LVL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Channel Priority Level 0"] + #[inline(always)] + pub fn lvl0(self) -> &'a mut W { + self.variant(LVL_A::LVL0) + } + #[doc = "Channel Priority Level 1"] + #[inline(always)] + pub fn lvl1(self) -> &'a mut W { + self.variant(LVL_A::LVL1) + } + #[doc = "Channel Priority Level 2"] + #[inline(always)] + pub fn lvl2(self) -> &'a mut W { + self.variant(LVL_A::LVL2) + } + #[doc = "Channel Priority Level 3"] + #[inline(always)] + pub fn lvl3(self) -> &'a mut W { + self.variant(LVL_A::LVL3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 5)) | ((value as u32 & 0x03) << 5); + self.w + } +} +#[doc = "Trigger Source\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum TRIGSRC_A { + #[doc = "0: Only software/event triggers"] + DISABLE = 0, + #[doc = "1: TSENS Result Ready Trigger"] + TSENS = 1, + #[doc = "2: SERCOM0 RX Trigger"] + SERCOM0_RX = 2, + #[doc = "3: SERCOM0 TX Trigger"] + SERCOM0_TX = 3, + #[doc = "4: SERCOM1 RX Trigger"] + SERCOM1_RX = 4, + #[doc = "5: SERCOM1 TX Trigger"] + SERCOM1_TX = 5, + #[doc = "6: SERCOM2 RX Trigger"] + SERCOM2_RX = 6, + #[doc = "7: SERCOM2 TX Trigger"] + SERCOM2_TX = 7, + #[doc = "8: SERCOM3 RX Trigger"] + SERCOM3_RX = 8, + #[doc = "9: SERCOM3 TX Trigger"] + SERCOM3_TX = 9, + #[doc = "14: CAN0 Debug Trigger Reserved"] + CAN0_DEBUG = 14, + #[doc = "16: TCC0 Overflow Trigger"] + TCC0_OVF = 16, + #[doc = "17: TCC0 Match/Compare 0 Trigger"] + TCC0_MC0 = 17, + #[doc = "18: TCC0 Match/Compare 1 Trigger"] + TCC0_MC1 = 18, + #[doc = "19: TCC0 Match/Compare 2 Trigger"] + TCC0_MC2 = 19, + #[doc = "20: TCC0 Match/Compare 3 Trigger"] + TCC0_MC3 = 20, + #[doc = "21: TCC1 Overflow Trigger"] + TCC1_OVF = 21, + #[doc = "22: TCC1 Match/Compare 0 Trigger"] + TCC1_MC0 = 22, + #[doc = "23: TCC1 Match/Compare 1 Trigger"] + TCC1_MC1 = 23, + #[doc = "24: TCC2 Overflow Trigger"] + TCC2_OVF = 24, + #[doc = "25: TCC2 Match/Compare 0 Trigger"] + TCC2_MC0 = 25, + #[doc = "26: TCC2 Match/Compare 1 Trigger"] + TCC2_MC1 = 26, + #[doc = "27: TC0 Overflow Trigger"] + TC0_OVF = 27, + #[doc = "28: TC0 Match/Compare 0 Trigger"] + TC0_MC0 = 28, + #[doc = "29: TC0 Match/Compare 1 Trigger"] + TC0_MC1 = 29, + #[doc = "30: TC1 Overflow Trigger"] + TC1_OVF = 30, + #[doc = "31: TC1 Match/Compare 0 Trigger"] + TC1_MC0 = 31, + #[doc = "32: TC1 Match/Compare 1 Trigger"] + TC1_MC1 = 32, + #[doc = "33: TC2 Overflow Trigger"] + TC2_OVF = 33, + #[doc = "34: TC2 Match/Compare 0 Trigger"] + TC2_MC0 = 34, + #[doc = "35: TC2 Match/Compare 1 Trigger"] + TC2_MC1 = 35, + #[doc = "36: TC3 Overflow Trigger"] + TC3_OVF = 36, + #[doc = "37: TC3 Match/Compare 0 Trigger"] + TC3_MC0 = 37, + #[doc = "38: TC3 Match/Compare 1 Trigger"] + TC3_MC1 = 38, + #[doc = "39: TC4 Overflow Trigger"] + TC4_OVF = 39, + #[doc = "40: TC4 Match/Compare 0 Trigger"] + TC4_MC0 = 40, + #[doc = "41: TC4 Match/Compare 1 Trigger"] + TC4_MC1 = 41, + #[doc = "42: ADC0 Result Ready Trigger"] + ADC0_RESRDY = 42, + #[doc = "43: ADC1 Result Ready Trigger"] + ADC1_RESRDY = 43, + #[doc = "44: SDADC Result Ready Trigger"] + SDADC_RESRDY = 44, + #[doc = "45: DAC Empty Trigger"] + DAC_EMPTY = 45, + #[doc = "46: PTC End of Conversion Trigger"] + PTC_EOC = 46, + #[doc = "47: PTC Window Compare Trigger"] + PTC_WCOMP = 47, + #[doc = "48: PTC Sequence Trigger"] + PTC_SEQ = 48, +} +impl From for u8 { + #[inline(always)] + fn from(variant: TRIGSRC_A) -> Self { + variant as _ + } +} +#[doc = "Field `TRIGSRC` reader - Trigger Source"] +pub struct TRIGSRC_R(crate::FieldReader); +impl TRIGSRC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TRIGSRC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(TRIGSRC_A::DISABLE), + 1 => Some(TRIGSRC_A::TSENS), + 2 => Some(TRIGSRC_A::SERCOM0_RX), + 3 => Some(TRIGSRC_A::SERCOM0_TX), + 4 => Some(TRIGSRC_A::SERCOM1_RX), + 5 => Some(TRIGSRC_A::SERCOM1_TX), + 6 => Some(TRIGSRC_A::SERCOM2_RX), + 7 => Some(TRIGSRC_A::SERCOM2_TX), + 8 => Some(TRIGSRC_A::SERCOM3_RX), + 9 => Some(TRIGSRC_A::SERCOM3_TX), + 14 => Some(TRIGSRC_A::CAN0_DEBUG), + 16 => Some(TRIGSRC_A::TCC0_OVF), + 17 => Some(TRIGSRC_A::TCC0_MC0), + 18 => Some(TRIGSRC_A::TCC0_MC1), + 19 => Some(TRIGSRC_A::TCC0_MC2), + 20 => Some(TRIGSRC_A::TCC0_MC3), + 21 => Some(TRIGSRC_A::TCC1_OVF), + 22 => Some(TRIGSRC_A::TCC1_MC0), + 23 => Some(TRIGSRC_A::TCC1_MC1), + 24 => Some(TRIGSRC_A::TCC2_OVF), + 25 => Some(TRIGSRC_A::TCC2_MC0), + 26 => Some(TRIGSRC_A::TCC2_MC1), + 27 => Some(TRIGSRC_A::TC0_OVF), + 28 => Some(TRIGSRC_A::TC0_MC0), + 29 => Some(TRIGSRC_A::TC0_MC1), + 30 => Some(TRIGSRC_A::TC1_OVF), + 31 => Some(TRIGSRC_A::TC1_MC0), + 32 => Some(TRIGSRC_A::TC1_MC1), + 33 => Some(TRIGSRC_A::TC2_OVF), + 34 => Some(TRIGSRC_A::TC2_MC0), + 35 => Some(TRIGSRC_A::TC2_MC1), + 36 => Some(TRIGSRC_A::TC3_OVF), + 37 => Some(TRIGSRC_A::TC3_MC0), + 38 => Some(TRIGSRC_A::TC3_MC1), + 39 => Some(TRIGSRC_A::TC4_OVF), + 40 => Some(TRIGSRC_A::TC4_MC0), + 41 => Some(TRIGSRC_A::TC4_MC1), + 42 => Some(TRIGSRC_A::ADC0_RESRDY), + 43 => Some(TRIGSRC_A::ADC1_RESRDY), + 44 => Some(TRIGSRC_A::SDADC_RESRDY), + 45 => Some(TRIGSRC_A::DAC_EMPTY), + 46 => Some(TRIGSRC_A::PTC_EOC), + 47 => Some(TRIGSRC_A::PTC_WCOMP), + 48 => Some(TRIGSRC_A::PTC_SEQ), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == TRIGSRC_A::DISABLE + } + #[doc = "Checks if the value of the field is `TSENS`"] + #[inline(always)] + pub fn is_tsens(&self) -> bool { + **self == TRIGSRC_A::TSENS + } + #[doc = "Checks if the value of the field is `SERCOM0_RX`"] + #[inline(always)] + pub fn is_sercom0_rx(&self) -> bool { + **self == TRIGSRC_A::SERCOM0_RX + } + #[doc = "Checks if the value of the field is `SERCOM0_TX`"] + #[inline(always)] + pub fn is_sercom0_tx(&self) -> bool { + **self == TRIGSRC_A::SERCOM0_TX + } + #[doc = "Checks if the value of the field is `SERCOM1_RX`"] + #[inline(always)] + pub fn is_sercom1_rx(&self) -> bool { + **self == TRIGSRC_A::SERCOM1_RX + } + #[doc = "Checks if the value of the field is `SERCOM1_TX`"] + #[inline(always)] + pub fn is_sercom1_tx(&self) -> bool { + **self == TRIGSRC_A::SERCOM1_TX + } + #[doc = "Checks if the value of the field is `SERCOM2_RX`"] + #[inline(always)] + pub fn is_sercom2_rx(&self) -> bool { + **self == TRIGSRC_A::SERCOM2_RX + } + #[doc = "Checks if the value of the field is `SERCOM2_TX`"] + #[inline(always)] + pub fn is_sercom2_tx(&self) -> bool { + **self == TRIGSRC_A::SERCOM2_TX + } + #[doc = "Checks if the value of the field is `SERCOM3_RX`"] + #[inline(always)] + pub fn is_sercom3_rx(&self) -> bool { + **self == TRIGSRC_A::SERCOM3_RX + } + #[doc = "Checks if the value of the field is `SERCOM3_TX`"] + #[inline(always)] + pub fn is_sercom3_tx(&self) -> bool { + **self == TRIGSRC_A::SERCOM3_TX + } + #[doc = "Checks if the value of the field is `CAN0_DEBUG`"] + #[inline(always)] + pub fn is_can0_debug(&self) -> bool { + **self == TRIGSRC_A::CAN0_DEBUG + } + #[doc = "Checks if the value of the field is `TCC0_OVF`"] + #[inline(always)] + pub fn is_tcc0_ovf(&self) -> bool { + **self == TRIGSRC_A::TCC0_OVF + } + #[doc = "Checks if the value of the field is `TCC0_MC0`"] + #[inline(always)] + pub fn is_tcc0_mc0(&self) -> bool { + **self == TRIGSRC_A::TCC0_MC0 + } + #[doc = "Checks if the value of the field is `TCC0_MC1`"] + #[inline(always)] + pub fn is_tcc0_mc1(&self) -> bool { + **self == TRIGSRC_A::TCC0_MC1 + } + #[doc = "Checks if the value of the field is `TCC0_MC2`"] + #[inline(always)] + pub fn is_tcc0_mc2(&self) -> bool { + **self == TRIGSRC_A::TCC0_MC2 + } + #[doc = "Checks if the value of the field is `TCC0_MC3`"] + #[inline(always)] + pub fn is_tcc0_mc3(&self) -> bool { + **self == TRIGSRC_A::TCC0_MC3 + } + #[doc = "Checks if the value of the field is `TCC1_OVF`"] + #[inline(always)] + pub fn is_tcc1_ovf(&self) -> bool { + **self == TRIGSRC_A::TCC1_OVF + } + #[doc = "Checks if the value of the field is `TCC1_MC0`"] + #[inline(always)] + pub fn is_tcc1_mc0(&self) -> bool { + **self == TRIGSRC_A::TCC1_MC0 + } + #[doc = "Checks if the value of the field is `TCC1_MC1`"] + #[inline(always)] + pub fn is_tcc1_mc1(&self) -> bool { + **self == TRIGSRC_A::TCC1_MC1 + } + #[doc = "Checks if the value of the field is `TCC2_OVF`"] + #[inline(always)] + pub fn is_tcc2_ovf(&self) -> bool { + **self == TRIGSRC_A::TCC2_OVF + } + #[doc = "Checks if the value of the field is `TCC2_MC0`"] + #[inline(always)] + pub fn is_tcc2_mc0(&self) -> bool { + **self == TRIGSRC_A::TCC2_MC0 + } + #[doc = "Checks if the value of the field is `TCC2_MC1`"] + #[inline(always)] + pub fn is_tcc2_mc1(&self) -> bool { + **self == TRIGSRC_A::TCC2_MC1 + } + #[doc = "Checks if the value of the field is `TC0_OVF`"] + #[inline(always)] + pub fn is_tc0_ovf(&self) -> bool { + **self == TRIGSRC_A::TC0_OVF + } + #[doc = "Checks if the value of the field is `TC0_MC0`"] + #[inline(always)] + pub fn is_tc0_mc0(&self) -> bool { + **self == TRIGSRC_A::TC0_MC0 + } + #[doc = "Checks if the value of the field is `TC0_MC1`"] + #[inline(always)] + pub fn is_tc0_mc1(&self) -> bool { + **self == TRIGSRC_A::TC0_MC1 + } + #[doc = "Checks if the value of the field is `TC1_OVF`"] + #[inline(always)] + pub fn is_tc1_ovf(&self) -> bool { + **self == TRIGSRC_A::TC1_OVF + } + #[doc = "Checks if the value of the field is `TC1_MC0`"] + #[inline(always)] + pub fn is_tc1_mc0(&self) -> bool { + **self == TRIGSRC_A::TC1_MC0 + } + #[doc = "Checks if the value of the field is `TC1_MC1`"] + #[inline(always)] + pub fn is_tc1_mc1(&self) -> bool { + **self == TRIGSRC_A::TC1_MC1 + } + #[doc = "Checks if the value of the field is `TC2_OVF`"] + #[inline(always)] + pub fn is_tc2_ovf(&self) -> bool { + **self == TRIGSRC_A::TC2_OVF + } + #[doc = "Checks if the value of the field is `TC2_MC0`"] + #[inline(always)] + pub fn is_tc2_mc0(&self) -> bool { + **self == TRIGSRC_A::TC2_MC0 + } + #[doc = "Checks if the value of the field is `TC2_MC1`"] + #[inline(always)] + pub fn is_tc2_mc1(&self) -> bool { + **self == TRIGSRC_A::TC2_MC1 + } + #[doc = "Checks if the value of the field is `TC3_OVF`"] + #[inline(always)] + pub fn is_tc3_ovf(&self) -> bool { + **self == TRIGSRC_A::TC3_OVF + } + #[doc = "Checks if the value of the field is `TC3_MC0`"] + #[inline(always)] + pub fn is_tc3_mc0(&self) -> bool { + **self == TRIGSRC_A::TC3_MC0 + } + #[doc = "Checks if the value of the field is `TC3_MC1`"] + #[inline(always)] + pub fn is_tc3_mc1(&self) -> bool { + **self == TRIGSRC_A::TC3_MC1 + } + #[doc = "Checks if the value of the field is `TC4_OVF`"] + #[inline(always)] + pub fn is_tc4_ovf(&self) -> bool { + **self == TRIGSRC_A::TC4_OVF + } + #[doc = "Checks if the value of the field is `TC4_MC0`"] + #[inline(always)] + pub fn is_tc4_mc0(&self) -> bool { + **self == TRIGSRC_A::TC4_MC0 + } + #[doc = "Checks if the value of the field is `TC4_MC1`"] + #[inline(always)] + pub fn is_tc4_mc1(&self) -> bool { + **self == TRIGSRC_A::TC4_MC1 + } + #[doc = "Checks if the value of the field is `ADC0_RESRDY`"] + #[inline(always)] + pub fn is_adc0_resrdy(&self) -> bool { + **self == TRIGSRC_A::ADC0_RESRDY + } + #[doc = "Checks if the value of the field is `ADC1_RESRDY`"] + #[inline(always)] + pub fn is_adc1_resrdy(&self) -> bool { + **self == TRIGSRC_A::ADC1_RESRDY + } + #[doc = "Checks if the value of the field is `SDADC_RESRDY`"] + #[inline(always)] + pub fn is_sdadc_resrdy(&self) -> bool { + **self == TRIGSRC_A::SDADC_RESRDY + } + #[doc = "Checks if the value of the field is `DAC_EMPTY`"] + #[inline(always)] + pub fn is_dac_empty(&self) -> bool { + **self == TRIGSRC_A::DAC_EMPTY + } + #[doc = "Checks if the value of the field is `PTC_EOC`"] + #[inline(always)] + pub fn is_ptc_eoc(&self) -> bool { + **self == TRIGSRC_A::PTC_EOC + } + #[doc = "Checks if the value of the field is `PTC_WCOMP`"] + #[inline(always)] + pub fn is_ptc_wcomp(&self) -> bool { + **self == TRIGSRC_A::PTC_WCOMP + } + #[doc = "Checks if the value of the field is `PTC_SEQ`"] + #[inline(always)] + pub fn is_ptc_seq(&self) -> bool { + **self == TRIGSRC_A::PTC_SEQ + } +} +impl core::ops::Deref for TRIGSRC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRIGSRC` writer - Trigger Source"] +pub struct TRIGSRC_W<'a> { + w: &'a mut W, +} +impl<'a> TRIGSRC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TRIGSRC_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Only software/event triggers"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(TRIGSRC_A::DISABLE) + } + #[doc = "TSENS Result Ready Trigger"] + #[inline(always)] + pub fn tsens(self) -> &'a mut W { + self.variant(TRIGSRC_A::TSENS) + } + #[doc = "SERCOM0 RX Trigger"] + #[inline(always)] + pub fn sercom0_rx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM0_RX) + } + #[doc = "SERCOM0 TX Trigger"] + #[inline(always)] + pub fn sercom0_tx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM0_TX) + } + #[doc = "SERCOM1 RX Trigger"] + #[inline(always)] + pub fn sercom1_rx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM1_RX) + } + #[doc = "SERCOM1 TX Trigger"] + #[inline(always)] + pub fn sercom1_tx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM1_TX) + } + #[doc = "SERCOM2 RX Trigger"] + #[inline(always)] + pub fn sercom2_rx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM2_RX) + } + #[doc = "SERCOM2 TX Trigger"] + #[inline(always)] + pub fn sercom2_tx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM2_TX) + } + #[doc = "SERCOM3 RX Trigger"] + #[inline(always)] + pub fn sercom3_rx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM3_RX) + } + #[doc = "SERCOM3 TX Trigger"] + #[inline(always)] + pub fn sercom3_tx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM3_TX) + } + #[doc = "CAN0 Debug Trigger Reserved"] + #[inline(always)] + pub fn can0_debug(self) -> &'a mut W { + self.variant(TRIGSRC_A::CAN0_DEBUG) + } + #[doc = "TCC0 Overflow Trigger"] + #[inline(always)] + pub fn tcc0_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC0_OVF) + } + #[doc = "TCC0 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tcc0_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC0_MC0) + } + #[doc = "TCC0 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tcc0_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC0_MC1) + } + #[doc = "TCC0 Match/Compare 2 Trigger"] + #[inline(always)] + pub fn tcc0_mc2(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC0_MC2) + } + #[doc = "TCC0 Match/Compare 3 Trigger"] + #[inline(always)] + pub fn tcc0_mc3(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC0_MC3) + } + #[doc = "TCC1 Overflow Trigger"] + #[inline(always)] + pub fn tcc1_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC1_OVF) + } + #[doc = "TCC1 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tcc1_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC1_MC0) + } + #[doc = "TCC1 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tcc1_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC1_MC1) + } + #[doc = "TCC2 Overflow Trigger"] + #[inline(always)] + pub fn tcc2_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC2_OVF) + } + #[doc = "TCC2 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tcc2_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC2_MC0) + } + #[doc = "TCC2 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tcc2_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC2_MC1) + } + #[doc = "TC0 Overflow Trigger"] + #[inline(always)] + pub fn tc0_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC0_OVF) + } + #[doc = "TC0 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tc0_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC0_MC0) + } + #[doc = "TC0 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tc0_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC0_MC1) + } + #[doc = "TC1 Overflow Trigger"] + #[inline(always)] + pub fn tc1_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC1_OVF) + } + #[doc = "TC1 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tc1_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC1_MC0) + } + #[doc = "TC1 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tc1_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC1_MC1) + } + #[doc = "TC2 Overflow Trigger"] + #[inline(always)] + pub fn tc2_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC2_OVF) + } + #[doc = "TC2 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tc2_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC2_MC0) + } + #[doc = "TC2 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tc2_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC2_MC1) + } + #[doc = "TC3 Overflow Trigger"] + #[inline(always)] + pub fn tc3_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC3_OVF) + } + #[doc = "TC3 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tc3_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC3_MC0) + } + #[doc = "TC3 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tc3_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC3_MC1) + } + #[doc = "TC4 Overflow Trigger"] + #[inline(always)] + pub fn tc4_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC4_OVF) + } + #[doc = "TC4 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tc4_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC4_MC0) + } + #[doc = "TC4 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tc4_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC4_MC1) + } + #[doc = "ADC0 Result Ready Trigger"] + #[inline(always)] + pub fn adc0_resrdy(self) -> &'a mut W { + self.variant(TRIGSRC_A::ADC0_RESRDY) + } + #[doc = "ADC1 Result Ready Trigger"] + #[inline(always)] + pub fn adc1_resrdy(self) -> &'a mut W { + self.variant(TRIGSRC_A::ADC1_RESRDY) + } + #[doc = "SDADC Result Ready Trigger"] + #[inline(always)] + pub fn sdadc_resrdy(self) -> &'a mut W { + self.variant(TRIGSRC_A::SDADC_RESRDY) + } + #[doc = "DAC Empty Trigger"] + #[inline(always)] + pub fn dac_empty(self) -> &'a mut W { + self.variant(TRIGSRC_A::DAC_EMPTY) + } + #[doc = "PTC End of Conversion Trigger"] + #[inline(always)] + pub fn ptc_eoc(self) -> &'a mut W { + self.variant(TRIGSRC_A::PTC_EOC) + } + #[doc = "PTC Window Compare Trigger"] + #[inline(always)] + pub fn ptc_wcomp(self) -> &'a mut W { + self.variant(TRIGSRC_A::PTC_WCOMP) + } + #[doc = "PTC Sequence Trigger"] + #[inline(always)] + pub fn ptc_seq(self) -> &'a mut W { + self.variant(TRIGSRC_A::PTC_SEQ) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 8)) | ((value as u32 & 0x3f) << 8); + self.w + } +} +#[doc = "Trigger Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum TRIGACT_A { + #[doc = "0: One trigger required for each block transfer"] + BLOCK = 0, + #[doc = "2: One trigger required for each beat transfer"] + BEAT = 2, + #[doc = "3: One trigger required for each transaction"] + TRANSACTION = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: TRIGACT_A) -> Self { + variant as _ + } +} +#[doc = "Field `TRIGACT` reader - Trigger Action"] +pub struct TRIGACT_R(crate::FieldReader); +impl TRIGACT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TRIGACT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(TRIGACT_A::BLOCK), + 2 => Some(TRIGACT_A::BEAT), + 3 => Some(TRIGACT_A::TRANSACTION), + _ => None, + } + } + #[doc = "Checks if the value of the field is `BLOCK`"] + #[inline(always)] + pub fn is_block(&self) -> bool { + **self == TRIGACT_A::BLOCK + } + #[doc = "Checks if the value of the field is `BEAT`"] + #[inline(always)] + pub fn is_beat(&self) -> bool { + **self == TRIGACT_A::BEAT + } + #[doc = "Checks if the value of the field is `TRANSACTION`"] + #[inline(always)] + pub fn is_transaction(&self) -> bool { + **self == TRIGACT_A::TRANSACTION + } +} +impl core::ops::Deref for TRIGACT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRIGACT` writer - Trigger Action"] +pub struct TRIGACT_W<'a> { + w: &'a mut W, +} +impl<'a> TRIGACT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TRIGACT_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "One trigger required for each block transfer"] + #[inline(always)] + pub fn block(self) -> &'a mut W { + self.variant(TRIGACT_A::BLOCK) + } + #[doc = "One trigger required for each beat transfer"] + #[inline(always)] + pub fn beat(self) -> &'a mut W { + self.variant(TRIGACT_A::BEAT) + } + #[doc = "One trigger required for each transaction"] + #[inline(always)] + pub fn transaction(self) -> &'a mut W { + self.variant(TRIGACT_A::TRANSACTION) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 22)) | ((value as u32 & 0x03) << 22); + self.w + } +} +#[doc = "Software Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NOACT = 0, + #[doc = "1: Channel suspend operation"] + SUSPEND = 1, + #[doc = "2: Channel resume operation"] + RESUME = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Software Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NOACT), + 1 => Some(CMD_A::SUSPEND), + 2 => Some(CMD_A::RESUME), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NOACT`"] + #[inline(always)] + pub fn is_noact(&self) -> bool { + **self == CMD_A::NOACT + } + #[doc = "Checks if the value of the field is `SUSPEND`"] + #[inline(always)] + pub fn is_suspend(&self) -> bool { + **self == CMD_A::SUSPEND + } + #[doc = "Checks if the value of the field is `RESUME`"] + #[inline(always)] + pub fn is_resume(&self) -> bool { + **self == CMD_A::RESUME + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Software Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn noact(self) -> &'a mut W { + self.variant(CMD_A::NOACT) + } + #[doc = "Channel suspend operation"] + #[inline(always)] + pub fn suspend(self) -> &'a mut W { + self.variant(CMD_A::SUSPEND) + } + #[doc = "Channel resume operation"] + #[inline(always)] + pub fn resume(self) -> &'a mut W { + self.variant(CMD_A::RESUME) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 24)) | ((value as u32 & 0x03) << 24); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Event Input Action"] + #[inline(always)] + pub fn evact(&self) -> EVACT_R { + EVACT_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 3 - Channel Event Input Enable"] + #[inline(always)] + pub fn evie(&self) -> EVIE_R { + EVIE_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Channel Event Output Enable"] + #[inline(always)] + pub fn evoe(&self) -> EVOE_R { + EVOE_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bits 5:6 - Channel Arbitration Level"] + #[inline(always)] + pub fn lvl(&self) -> LVL_R { + LVL_R::new(((self.bits >> 5) & 0x03) as u8) + } + #[doc = "Bits 8:13 - Trigger Source"] + #[inline(always)] + pub fn trigsrc(&self) -> TRIGSRC_R { + TRIGSRC_R::new(((self.bits >> 8) & 0x3f) as u8) + } + #[doc = "Bits 22:23 - Trigger Action"] + #[inline(always)] + pub fn trigact(&self) -> TRIGACT_R { + TRIGACT_R::new(((self.bits >> 22) & 0x03) as u8) + } + #[doc = "Bits 24:25 - Software Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 24) & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Event Input Action"] + #[inline(always)] + pub fn evact(&mut self) -> EVACT_W { + EVACT_W { w: self } + } + #[doc = "Bit 3 - Channel Event Input Enable"] + #[inline(always)] + pub fn evie(&mut self) -> EVIE_W { + EVIE_W { w: self } + } + #[doc = "Bit 4 - Channel Event Output Enable"] + #[inline(always)] + pub fn evoe(&mut self) -> EVOE_W { + EVOE_W { w: self } + } + #[doc = "Bits 5:6 - Channel Arbitration Level"] + #[inline(always)] + pub fn lvl(&mut self) -> LVL_W { + LVL_W { w: self } + } + #[doc = "Bits 8:13 - Trigger Source"] + #[inline(always)] + pub fn trigsrc(&mut self) -> TRIGSRC_W { + TRIGSRC_W { w: self } + } + #[doc = "Bits 22:23 - Trigger Action"] + #[inline(always)] + pub fn trigact(&mut self) -> TRIGACT_W { + TRIGACT_W { w: self } + } + #[doc = "Bits 24:25 - Software Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chctrlb](index.html) module"] +pub struct CHCTRLB_SPEC; +impl crate::RegisterSpec for CHCTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [chctrlb::R](R) reader structure"] +impl crate::Readable for CHCTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chctrlb::W](W) writer structure"] +impl crate::Writable for CHCTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHCTRLB to value 0"] +impl crate::Resettable for CHCTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/dmac/chid.rs b/pac/atsamc21e/src/dmac/chid.rs new file mode 100644 index 000000000000..19151d8e10b0 --- /dev/null +++ b/pac/atsamc21e/src/dmac/chid.rs @@ -0,0 +1,103 @@ +#[doc = "Register `CHID` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHID` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ID` reader - Channel ID"] +pub struct ID_R(crate::FieldReader); +impl ID_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ID_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ID_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ID` writer - Channel ID"] +pub struct ID_W<'a> { + w: &'a mut W, +} +impl<'a> ID_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Channel ID"] + #[inline(always)] + pub fn id(&self) -> ID_R { + ID_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Channel ID"] + #[inline(always)] + pub fn id(&mut self) -> ID_W { + ID_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel ID\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chid](index.html) module"] +pub struct CHID_SPEC; +impl crate::RegisterSpec for CHID_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [chid::R](R) reader structure"] +impl crate::Readable for CHID_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chid::W](W) writer structure"] +impl crate::Writable for CHID_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHID to value 0"] +impl crate::Resettable for CHID_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/dmac/chintenclr.rs b/pac/atsamc21e/src/dmac/chintenclr.rs new file mode 100644 index 000000000000..5ae3096f9ab8 --- /dev/null +++ b/pac/atsamc21e/src/dmac/chintenclr.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CHINTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHINTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TERR` reader - Channel Transfer Error Interrupt Enable"] +pub struct TERR_R(crate::FieldReader); +impl TERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TERR` writer - Channel Transfer Error Interrupt Enable"] +pub struct TERR_W<'a> { + w: &'a mut W, +} +impl<'a> TERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TCMPL` reader - Channel Transfer Complete Interrupt Enable"] +pub struct TCMPL_R(crate::FieldReader); +impl TCMPL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCMPL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCMPL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCMPL` writer - Channel Transfer Complete Interrupt Enable"] +pub struct TCMPL_W<'a> { + w: &'a mut W, +} +impl<'a> TCMPL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SUSP` reader - Channel Suspend Interrupt Enable"] +pub struct SUSP_R(crate::FieldReader); +impl SUSP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SUSP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SUSP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SUSP` writer - Channel Suspend Interrupt Enable"] +pub struct SUSP_W<'a> { + w: &'a mut W, +} +impl<'a> SUSP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Channel Transfer Error Interrupt Enable"] + #[inline(always)] + pub fn terr(&self) -> TERR_R { + TERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel Transfer Complete Interrupt Enable"] + #[inline(always)] + pub fn tcmpl(&self) -> TCMPL_R { + TCMPL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel Suspend Interrupt Enable"] + #[inline(always)] + pub fn susp(&self) -> SUSP_R { + SUSP_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel Transfer Error Interrupt Enable"] + #[inline(always)] + pub fn terr(&mut self) -> TERR_W { + TERR_W { w: self } + } + #[doc = "Bit 1 - Channel Transfer Complete Interrupt Enable"] + #[inline(always)] + pub fn tcmpl(&mut self) -> TCMPL_W { + TCMPL_W { w: self } + } + #[doc = "Bit 2 - Channel Suspend Interrupt Enable"] + #[inline(always)] + pub fn susp(&mut self) -> SUSP_W { + SUSP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chintenclr](index.html) module"] +pub struct CHINTENCLR_SPEC; +impl crate::RegisterSpec for CHINTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [chintenclr::R](R) reader structure"] +impl crate::Readable for CHINTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chintenclr::W](W) writer structure"] +impl crate::Writable for CHINTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHINTENCLR to value 0"] +impl crate::Resettable for CHINTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/dmac/chintenset.rs b/pac/atsamc21e/src/dmac/chintenset.rs new file mode 100644 index 000000000000..2e7daef20a6f --- /dev/null +++ b/pac/atsamc21e/src/dmac/chintenset.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CHINTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHINTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TERR` reader - Channel Transfer Error Interrupt Enable"] +pub struct TERR_R(crate::FieldReader); +impl TERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TERR` writer - Channel Transfer Error Interrupt Enable"] +pub struct TERR_W<'a> { + w: &'a mut W, +} +impl<'a> TERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TCMPL` reader - Channel Transfer Complete Interrupt Enable"] +pub struct TCMPL_R(crate::FieldReader); +impl TCMPL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCMPL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCMPL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCMPL` writer - Channel Transfer Complete Interrupt Enable"] +pub struct TCMPL_W<'a> { + w: &'a mut W, +} +impl<'a> TCMPL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SUSP` reader - Channel Suspend Interrupt Enable"] +pub struct SUSP_R(crate::FieldReader); +impl SUSP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SUSP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SUSP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SUSP` writer - Channel Suspend Interrupt Enable"] +pub struct SUSP_W<'a> { + w: &'a mut W, +} +impl<'a> SUSP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Channel Transfer Error Interrupt Enable"] + #[inline(always)] + pub fn terr(&self) -> TERR_R { + TERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel Transfer Complete Interrupt Enable"] + #[inline(always)] + pub fn tcmpl(&self) -> TCMPL_R { + TCMPL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel Suspend Interrupt Enable"] + #[inline(always)] + pub fn susp(&self) -> SUSP_R { + SUSP_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel Transfer Error Interrupt Enable"] + #[inline(always)] + pub fn terr(&mut self) -> TERR_W { + TERR_W { w: self } + } + #[doc = "Bit 1 - Channel Transfer Complete Interrupt Enable"] + #[inline(always)] + pub fn tcmpl(&mut self) -> TCMPL_W { + TCMPL_W { w: self } + } + #[doc = "Bit 2 - Channel Suspend Interrupt Enable"] + #[inline(always)] + pub fn susp(&mut self) -> SUSP_W { + SUSP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chintenset](index.html) module"] +pub struct CHINTENSET_SPEC; +impl crate::RegisterSpec for CHINTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [chintenset::R](R) reader structure"] +impl crate::Readable for CHINTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chintenset::W](W) writer structure"] +impl crate::Writable for CHINTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHINTENSET to value 0"] +impl crate::Resettable for CHINTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/dmac/chintflag.rs b/pac/atsamc21e/src/dmac/chintflag.rs new file mode 100644 index 000000000000..4e61d6510c30 --- /dev/null +++ b/pac/atsamc21e/src/dmac/chintflag.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CHINTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHINTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TERR` reader - Channel Transfer Error"] +pub struct TERR_R(crate::FieldReader); +impl TERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TERR` writer - Channel Transfer Error"] +pub struct TERR_W<'a> { + w: &'a mut W, +} +impl<'a> TERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TCMPL` reader - Channel Transfer Complete"] +pub struct TCMPL_R(crate::FieldReader); +impl TCMPL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCMPL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCMPL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCMPL` writer - Channel Transfer Complete"] +pub struct TCMPL_W<'a> { + w: &'a mut W, +} +impl<'a> TCMPL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SUSP` reader - Channel Suspend"] +pub struct SUSP_R(crate::FieldReader); +impl SUSP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SUSP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SUSP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SUSP` writer - Channel Suspend"] +pub struct SUSP_W<'a> { + w: &'a mut W, +} +impl<'a> SUSP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Channel Transfer Error"] + #[inline(always)] + pub fn terr(&self) -> TERR_R { + TERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel Transfer Complete"] + #[inline(always)] + pub fn tcmpl(&self) -> TCMPL_R { + TCMPL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel Suspend"] + #[inline(always)] + pub fn susp(&self) -> SUSP_R { + SUSP_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel Transfer Error"] + #[inline(always)] + pub fn terr(&mut self) -> TERR_W { + TERR_W { w: self } + } + #[doc = "Bit 1 - Channel Transfer Complete"] + #[inline(always)] + pub fn tcmpl(&mut self) -> TCMPL_W { + TCMPL_W { w: self } + } + #[doc = "Bit 2 - Channel Suspend"] + #[inline(always)] + pub fn susp(&mut self) -> SUSP_W { + SUSP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chintflag](index.html) module"] +pub struct CHINTFLAG_SPEC; +impl crate::RegisterSpec for CHINTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [chintflag::R](R) reader structure"] +impl crate::Readable for CHINTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chintflag::W](W) writer structure"] +impl crate::Writable for CHINTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHINTFLAG to value 0"] +impl crate::Resettable for CHINTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/dmac/chstatus.rs b/pac/atsamc21e/src/dmac/chstatus.rs new file mode 100644 index 000000000000..98a84345d4f7 --- /dev/null +++ b/pac/atsamc21e/src/dmac/chstatus.rs @@ -0,0 +1,93 @@ +#[doc = "Register `CHSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PEND` reader - Channel Pending"] +pub struct PEND_R(crate::FieldReader); +impl PEND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSY` reader - Channel Busy"] +pub struct BUSY_R(crate::FieldReader); +impl BUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FERR` reader - Channel Fetch Error"] +pub struct FERR_R(crate::FieldReader); +impl FERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Channel Pending"] + #[inline(always)] + pub fn pend(&self) -> PEND_R { + PEND_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel Busy"] + #[inline(always)] + pub fn busy(&self) -> BUSY_R { + BUSY_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel Fetch Error"] + #[inline(always)] + pub fn ferr(&self) -> FERR_R { + FERR_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +#[doc = "Channel Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chstatus](index.html) module"] +pub struct CHSTATUS_SPEC; +impl crate::RegisterSpec for CHSTATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [chstatus::R](R) reader structure"] +impl crate::Readable for CHSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CHSTATUS to value 0"] +impl crate::Resettable for CHSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/dmac/crcchksum.rs b/pac/atsamc21e/src/dmac/crcchksum.rs new file mode 100644 index 000000000000..89eb5b38a093 --- /dev/null +++ b/pac/atsamc21e/src/dmac/crcchksum.rs @@ -0,0 +1,103 @@ +#[doc = "Register `CRCCHKSUM` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CRCCHKSUM` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CRCCHKSUM` reader - CRC Checksum"] +pub struct CRCCHKSUM_R(crate::FieldReader); +impl CRCCHKSUM_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CRCCHKSUM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CRCCHKSUM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCCHKSUM` writer - CRC Checksum"] +pub struct CRCCHKSUM_W<'a> { + w: &'a mut W, +} +impl<'a> CRCCHKSUM_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - CRC Checksum"] + #[inline(always)] + pub fn crcchksum(&self) -> CRCCHKSUM_R { + CRCCHKSUM_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - CRC Checksum"] + #[inline(always)] + pub fn crcchksum(&mut self) -> CRCCHKSUM_W { + CRCCHKSUM_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CRC Checksum\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [crcchksum](index.html) module"] +pub struct CRCCHKSUM_SPEC; +impl crate::RegisterSpec for CRCCHKSUM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [crcchksum::R](R) reader structure"] +impl crate::Readable for CRCCHKSUM_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [crcchksum::W](W) writer structure"] +impl crate::Writable for CRCCHKSUM_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CRCCHKSUM to value 0"] +impl crate::Resettable for CRCCHKSUM_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/dmac/crcctrl.rs b/pac/atsamc21e/src/dmac/crcctrl.rs new file mode 100644 index 000000000000..b8daf7b8259d --- /dev/null +++ b/pac/atsamc21e/src/dmac/crcctrl.rs @@ -0,0 +1,337 @@ +#[doc = "Register `CRCCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CRCCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "CRC Beat Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CRCBEATSIZE_A { + #[doc = "0: 8-bit bus transfer"] + BYTE = 0, + #[doc = "1: 16-bit bus transfer"] + HWORD = 1, + #[doc = "2: 32-bit bus transfer"] + WORD = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CRCBEATSIZE_A) -> Self { + variant as _ + } +} +#[doc = "Field `CRCBEATSIZE` reader - CRC Beat Size"] +pub struct CRCBEATSIZE_R(crate::FieldReader); +impl CRCBEATSIZE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CRCBEATSIZE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CRCBEATSIZE_A::BYTE), + 1 => Some(CRCBEATSIZE_A::HWORD), + 2 => Some(CRCBEATSIZE_A::WORD), + _ => None, + } + } + #[doc = "Checks if the value of the field is `BYTE`"] + #[inline(always)] + pub fn is_byte(&self) -> bool { + **self == CRCBEATSIZE_A::BYTE + } + #[doc = "Checks if the value of the field is `HWORD`"] + #[inline(always)] + pub fn is_hword(&self) -> bool { + **self == CRCBEATSIZE_A::HWORD + } + #[doc = "Checks if the value of the field is `WORD`"] + #[inline(always)] + pub fn is_word(&self) -> bool { + **self == CRCBEATSIZE_A::WORD + } +} +impl core::ops::Deref for CRCBEATSIZE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCBEATSIZE` writer - CRC Beat Size"] +pub struct CRCBEATSIZE_W<'a> { + w: &'a mut W, +} +impl<'a> CRCBEATSIZE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CRCBEATSIZE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8-bit bus transfer"] + #[inline(always)] + pub fn byte(self) -> &'a mut W { + self.variant(CRCBEATSIZE_A::BYTE) + } + #[doc = "16-bit bus transfer"] + #[inline(always)] + pub fn hword(self) -> &'a mut W { + self.variant(CRCBEATSIZE_A::HWORD) + } + #[doc = "32-bit bus transfer"] + #[inline(always)] + pub fn word(self) -> &'a mut W { + self.variant(CRCBEATSIZE_A::WORD) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u16 & 0x03); + self.w + } +} +#[doc = "CRC Polynomial Type\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CRCPOLY_A { + #[doc = "0: CRC-16 (CRC-CCITT)"] + CRC16 = 0, + #[doc = "1: CRC32 (IEEE 802.3)"] + CRC32 = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CRCPOLY_A) -> Self { + variant as _ + } +} +#[doc = "Field `CRCPOLY` reader - CRC Polynomial Type"] +pub struct CRCPOLY_R(crate::FieldReader); +impl CRCPOLY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CRCPOLY_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CRCPOLY_A::CRC16), + 1 => Some(CRCPOLY_A::CRC32), + _ => None, + } + } + #[doc = "Checks if the value of the field is `CRC16`"] + #[inline(always)] + pub fn is_crc16(&self) -> bool { + **self == CRCPOLY_A::CRC16 + } + #[doc = "Checks if the value of the field is `CRC32`"] + #[inline(always)] + pub fn is_crc32(&self) -> bool { + **self == CRCPOLY_A::CRC32 + } +} +impl core::ops::Deref for CRCPOLY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCPOLY` writer - CRC Polynomial Type"] +pub struct CRCPOLY_W<'a> { + w: &'a mut W, +} +impl<'a> CRCPOLY_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CRCPOLY_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "CRC-16 (CRC-CCITT)"] + #[inline(always)] + pub fn crc16(self) -> &'a mut W { + self.variant(CRCPOLY_A::CRC16) + } + #[doc = "CRC32 (IEEE 802.3)"] + #[inline(always)] + pub fn crc32(self) -> &'a mut W { + self.variant(CRCPOLY_A::CRC32) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u16 & 0x03) << 2); + self.w + } +} +#[doc = "CRC Input Source\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CRCSRC_A { + #[doc = "0: No action"] + NOACT = 0, + #[doc = "1: I/O interface"] + IO = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CRCSRC_A) -> Self { + variant as _ + } +} +#[doc = "Field `CRCSRC` reader - CRC Input Source"] +pub struct CRCSRC_R(crate::FieldReader); +impl CRCSRC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CRCSRC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CRCSRC_A::NOACT), + 1 => Some(CRCSRC_A::IO), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NOACT`"] + #[inline(always)] + pub fn is_noact(&self) -> bool { + **self == CRCSRC_A::NOACT + } + #[doc = "Checks if the value of the field is `IO`"] + #[inline(always)] + pub fn is_io(&self) -> bool { + **self == CRCSRC_A::IO + } +} +impl core::ops::Deref for CRCSRC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCSRC` writer - CRC Input Source"] +pub struct CRCSRC_W<'a> { + w: &'a mut W, +} +impl<'a> CRCSRC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CRCSRC_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn noact(self) -> &'a mut W { + self.variant(CRCSRC_A::NOACT) + } + #[doc = "I/O interface"] + #[inline(always)] + pub fn io(self) -> &'a mut W { + self.variant(CRCSRC_A::IO) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 8)) | ((value as u16 & 0x3f) << 8); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - CRC Beat Size"] + #[inline(always)] + pub fn crcbeatsize(&self) -> CRCBEATSIZE_R { + CRCBEATSIZE_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bits 2:3 - CRC Polynomial Type"] + #[inline(always)] + pub fn crcpoly(&self) -> CRCPOLY_R { + CRCPOLY_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bits 8:13 - CRC Input Source"] + #[inline(always)] + pub fn crcsrc(&self) -> CRCSRC_R { + CRCSRC_R::new(((self.bits >> 8) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - CRC Beat Size"] + #[inline(always)] + pub fn crcbeatsize(&mut self) -> CRCBEATSIZE_W { + CRCBEATSIZE_W { w: self } + } + #[doc = "Bits 2:3 - CRC Polynomial Type"] + #[inline(always)] + pub fn crcpoly(&mut self) -> CRCPOLY_W { + CRCPOLY_W { w: self } + } + #[doc = "Bits 8:13 - CRC Input Source"] + #[inline(always)] + pub fn crcsrc(&mut self) -> CRCSRC_W { + CRCSRC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CRC Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [crcctrl](index.html) module"] +pub struct CRCCTRL_SPEC; +impl crate::RegisterSpec for CRCCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [crcctrl::R](R) reader structure"] +impl crate::Readable for CRCCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [crcctrl::W](W) writer structure"] +impl crate::Writable for CRCCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CRCCTRL to value 0"] +impl crate::Resettable for CRCCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/dmac/crcdatain.rs b/pac/atsamc21e/src/dmac/crcdatain.rs new file mode 100644 index 000000000000..ca0879a12136 --- /dev/null +++ b/pac/atsamc21e/src/dmac/crcdatain.rs @@ -0,0 +1,103 @@ +#[doc = "Register `CRCDATAIN` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CRCDATAIN` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CRCDATAIN` reader - CRC Data Input"] +pub struct CRCDATAIN_R(crate::FieldReader); +impl CRCDATAIN_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CRCDATAIN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CRCDATAIN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCDATAIN` writer - CRC Data Input"] +pub struct CRCDATAIN_W<'a> { + w: &'a mut W, +} +impl<'a> CRCDATAIN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - CRC Data Input"] + #[inline(always)] + pub fn crcdatain(&self) -> CRCDATAIN_R { + CRCDATAIN_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - CRC Data Input"] + #[inline(always)] + pub fn crcdatain(&mut self) -> CRCDATAIN_W { + CRCDATAIN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CRC Data Input\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [crcdatain](index.html) module"] +pub struct CRCDATAIN_SPEC; +impl crate::RegisterSpec for CRCDATAIN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [crcdatain::R](R) reader structure"] +impl crate::Readable for CRCDATAIN_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [crcdatain::W](W) writer structure"] +impl crate::Writable for CRCDATAIN_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CRCDATAIN to value 0"] +impl crate::Resettable for CRCDATAIN_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/dmac/crcstatus.rs b/pac/atsamc21e/src/dmac/crcstatus.rs new file mode 100644 index 000000000000..a132e9d5cd03 --- /dev/null +++ b/pac/atsamc21e/src/dmac/crcstatus.rs @@ -0,0 +1,160 @@ +#[doc = "Register `CRCSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CRCSTATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CRCBUSY` reader - CRC Module Busy"] +pub struct CRCBUSY_R(crate::FieldReader); +impl CRCBUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CRCBUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CRCBUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCBUSY` writer - CRC Module Busy"] +pub struct CRCBUSY_W<'a> { + w: &'a mut W, +} +impl<'a> CRCBUSY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `CRCZERO` reader - CRC Zero"] +pub struct CRCZERO_R(crate::FieldReader); +impl CRCZERO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CRCZERO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CRCZERO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCZERO` writer - CRC Zero"] +pub struct CRCZERO_W<'a> { + w: &'a mut W, +} +impl<'a> CRCZERO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - CRC Module Busy"] + #[inline(always)] + pub fn crcbusy(&self) -> CRCBUSY_R { + CRCBUSY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - CRC Zero"] + #[inline(always)] + pub fn crczero(&self) -> CRCZERO_R { + CRCZERO_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - CRC Module Busy"] + #[inline(always)] + pub fn crcbusy(&mut self) -> CRCBUSY_W { + CRCBUSY_W { w: self } + } + #[doc = "Bit 1 - CRC Zero"] + #[inline(always)] + pub fn crczero(&mut self) -> CRCZERO_W { + CRCZERO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CRC Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [crcstatus](index.html) module"] +pub struct CRCSTATUS_SPEC; +impl crate::RegisterSpec for CRCSTATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [crcstatus::R](R) reader structure"] +impl crate::Readable for CRCSTATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [crcstatus::W](W) writer structure"] +impl crate::Writable for CRCSTATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CRCSTATUS to value 0"] +impl crate::Resettable for CRCSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/dmac/ctrl.rs b/pac/atsamc21e/src/dmac/ctrl.rs new file mode 100644 index 000000000000..fabae9d82a6c --- /dev/null +++ b/pac/atsamc21e/src/dmac/ctrl.rs @@ -0,0 +1,395 @@ +#[doc = "Register `CTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `DMAENABLE` reader - DMA Enable"] +pub struct DMAENABLE_R(crate::FieldReader); +impl DMAENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DMAENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DMAENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DMAENABLE` writer - DMA Enable"] +pub struct DMAENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> DMAENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CRCENABLE` reader - CRC Enable"] +pub struct CRCENABLE_R(crate::FieldReader); +impl CRCENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CRCENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CRCENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCENABLE` writer - CRC Enable"] +pub struct CRCENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> CRCENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `LVLEN0` reader - Priority Level 0 Enable"] +pub struct LVLEN0_R(crate::FieldReader); +impl LVLEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LVLEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLEN0` writer - Priority Level 0 Enable"] +pub struct LVLEN0_W<'a> { + w: &'a mut W, +} +impl<'a> LVLEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `LVLEN1` reader - Priority Level 1 Enable"] +pub struct LVLEN1_R(crate::FieldReader); +impl LVLEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LVLEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLEN1` writer - Priority Level 1 Enable"] +pub struct LVLEN1_W<'a> { + w: &'a mut W, +} +impl<'a> LVLEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `LVLEN2` reader - Priority Level 2 Enable"] +pub struct LVLEN2_R(crate::FieldReader); +impl LVLEN2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LVLEN2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEN2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLEN2` writer - Priority Level 2 Enable"] +pub struct LVLEN2_W<'a> { + w: &'a mut W, +} +impl<'a> LVLEN2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u16 & 0x01) << 10); + self.w + } +} +#[doc = "Field `LVLEN3` reader - Priority Level 3 Enable"] +pub struct LVLEN3_R(crate::FieldReader); +impl LVLEN3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LVLEN3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEN3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLEN3` writer - Priority Level 3 Enable"] +pub struct LVLEN3_W<'a> { + w: &'a mut W, +} +impl<'a> LVLEN3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u16 & 0x01) << 11); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - DMA Enable"] + #[inline(always)] + pub fn dmaenable(&self) -> DMAENABLE_R { + DMAENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - CRC Enable"] + #[inline(always)] + pub fn crcenable(&self) -> CRCENABLE_R { + CRCENABLE_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 8 - Priority Level 0 Enable"] + #[inline(always)] + pub fn lvlen0(&self) -> LVLEN0_R { + LVLEN0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Priority Level 1 Enable"] + #[inline(always)] + pub fn lvlen1(&self) -> LVLEN1_R { + LVLEN1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Priority Level 2 Enable"] + #[inline(always)] + pub fn lvlen2(&self) -> LVLEN2_R { + LVLEN2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Priority Level 3 Enable"] + #[inline(always)] + pub fn lvlen3(&self) -> LVLEN3_R { + LVLEN3_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - DMA Enable"] + #[inline(always)] + pub fn dmaenable(&mut self) -> DMAENABLE_W { + DMAENABLE_W { w: self } + } + #[doc = "Bit 2 - CRC Enable"] + #[inline(always)] + pub fn crcenable(&mut self) -> CRCENABLE_W { + CRCENABLE_W { w: self } + } + #[doc = "Bit 8 - Priority Level 0 Enable"] + #[inline(always)] + pub fn lvlen0(&mut self) -> LVLEN0_W { + LVLEN0_W { w: self } + } + #[doc = "Bit 9 - Priority Level 1 Enable"] + #[inline(always)] + pub fn lvlen1(&mut self) -> LVLEN1_W { + LVLEN1_W { w: self } + } + #[doc = "Bit 10 - Priority Level 2 Enable"] + #[inline(always)] + pub fn lvlen2(&mut self) -> LVLEN2_W { + LVLEN2_W { w: self } + } + #[doc = "Bit 11 - Priority Level 3 Enable"] + #[inline(always)] + pub fn lvlen3(&mut self) -> LVLEN3_W { + LVLEN3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"] +pub struct CTRL_SPEC; +impl crate::RegisterSpec for CTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrl::R](R) reader structure"] +impl crate::Readable for CTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"] +impl crate::Writable for CTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/dmac/dbgctrl.rs b/pac/atsamc21e/src/dmac/dbgctrl.rs new file mode 100644 index 000000000000..53636eb2b339 --- /dev/null +++ b/pac/atsamc21e/src/dmac/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Debug Run"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Debug Run"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/dmac/intpend.rs b/pac/atsamc21e/src/dmac/intpend.rs new file mode 100644 index 000000000000..a107c4c32e66 --- /dev/null +++ b/pac/atsamc21e/src/dmac/intpend.rs @@ -0,0 +1,385 @@ +#[doc = "Register `INTPEND` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTPEND` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ID` reader - Channel ID"] +pub struct ID_R(crate::FieldReader); +impl ID_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ID_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ID_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ID` writer - Channel ID"] +pub struct ID_W<'a> { + w: &'a mut W, +} +impl<'a> ID_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u16 & 0x0f); + self.w + } +} +#[doc = "Field `TERR` reader - Transfer Error"] +pub struct TERR_R(crate::FieldReader); +impl TERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TERR` writer - Transfer Error"] +pub struct TERR_W<'a> { + w: &'a mut W, +} +impl<'a> TERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `TCMPL` reader - Transfer Complete"] +pub struct TCMPL_R(crate::FieldReader); +impl TCMPL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCMPL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCMPL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCMPL` writer - Transfer Complete"] +pub struct TCMPL_W<'a> { + w: &'a mut W, +} +impl<'a> TCMPL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `SUSP` reader - Channel Suspend"] +pub struct SUSP_R(crate::FieldReader); +impl SUSP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SUSP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SUSP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SUSP` writer - Channel Suspend"] +pub struct SUSP_W<'a> { + w: &'a mut W, +} +impl<'a> SUSP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u16 & 0x01) << 10); + self.w + } +} +#[doc = "Field `FERR` reader - Fetch Error"] +pub struct FERR_R(crate::FieldReader); +impl FERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FERR` writer - Fetch Error"] +pub struct FERR_W<'a> { + w: &'a mut W, +} +impl<'a> FERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u16 & 0x01) << 13); + self.w + } +} +#[doc = "Field `BUSY` reader - Busy"] +pub struct BUSY_R(crate::FieldReader); +impl BUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSY` writer - Busy"] +pub struct BUSY_W<'a> { + w: &'a mut W, +} +impl<'a> BUSY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u16 & 0x01) << 14); + self.w + } +} +#[doc = "Field `PEND` reader - Pending"] +pub struct PEND_R(crate::FieldReader); +impl PEND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEND` writer - Pending"] +pub struct PEND_W<'a> { + w: &'a mut W, +} +impl<'a> PEND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Channel ID"] + #[inline(always)] + pub fn id(&self) -> ID_R { + ID_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 8 - Transfer Error"] + #[inline(always)] + pub fn terr(&self) -> TERR_R { + TERR_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Transfer Complete"] + #[inline(always)] + pub fn tcmpl(&self) -> TCMPL_R { + TCMPL_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Channel Suspend"] + #[inline(always)] + pub fn susp(&self) -> SUSP_R { + SUSP_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 13 - Fetch Error"] + #[inline(always)] + pub fn ferr(&self) -> FERR_R { + FERR_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Busy"] + #[inline(always)] + pub fn busy(&self) -> BUSY_R { + BUSY_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Pending"] + #[inline(always)] + pub fn pend(&self) -> PEND_R { + PEND_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Channel ID"] + #[inline(always)] + pub fn id(&mut self) -> ID_W { + ID_W { w: self } + } + #[doc = "Bit 8 - Transfer Error"] + #[inline(always)] + pub fn terr(&mut self) -> TERR_W { + TERR_W { w: self } + } + #[doc = "Bit 9 - Transfer Complete"] + #[inline(always)] + pub fn tcmpl(&mut self) -> TCMPL_W { + TCMPL_W { w: self } + } + #[doc = "Bit 10 - Channel Suspend"] + #[inline(always)] + pub fn susp(&mut self) -> SUSP_W { + SUSP_W { w: self } + } + #[doc = "Bit 13 - Fetch Error"] + #[inline(always)] + pub fn ferr(&mut self) -> FERR_W { + FERR_W { w: self } + } + #[doc = "Bit 14 - Busy"] + #[inline(always)] + pub fn busy(&mut self) -> BUSY_W { + BUSY_W { w: self } + } + #[doc = "Bit 15 - Pending"] + #[inline(always)] + pub fn pend(&mut self) -> PEND_W { + PEND_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Pending\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intpend](index.html) module"] +pub struct INTPEND_SPEC; +impl crate::RegisterSpec for INTPEND_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intpend::R](R) reader structure"] +impl crate::Readable for INTPEND_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intpend::W](W) writer structure"] +impl crate::Writable for INTPEND_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTPEND to value 0"] +impl crate::Resettable for INTPEND_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/dmac/intstatus.rs b/pac/atsamc21e/src/dmac/intstatus.rs new file mode 100644 index 000000000000..74a836f4a2ff --- /dev/null +++ b/pac/atsamc21e/src/dmac/intstatus.rs @@ -0,0 +1,273 @@ +#[doc = "Register `INTSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `CHINT0` reader - Channel 0 Pending Interrupt"] +pub struct CHINT0_R(crate::FieldReader); +impl CHINT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT1` reader - Channel 1 Pending Interrupt"] +pub struct CHINT1_R(crate::FieldReader); +impl CHINT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT2` reader - Channel 2 Pending Interrupt"] +pub struct CHINT2_R(crate::FieldReader); +impl CHINT2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT3` reader - Channel 3 Pending Interrupt"] +pub struct CHINT3_R(crate::FieldReader); +impl CHINT3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT4` reader - Channel 4 Pending Interrupt"] +pub struct CHINT4_R(crate::FieldReader); +impl CHINT4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT5` reader - Channel 5 Pending Interrupt"] +pub struct CHINT5_R(crate::FieldReader); +impl CHINT5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT6` reader - Channel 6 Pending Interrupt"] +pub struct CHINT6_R(crate::FieldReader); +impl CHINT6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT7` reader - Channel 7 Pending Interrupt"] +pub struct CHINT7_R(crate::FieldReader); +impl CHINT7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT8` reader - Channel 8 Pending Interrupt"] +pub struct CHINT8_R(crate::FieldReader); +impl CHINT8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT9` reader - Channel 9 Pending Interrupt"] +pub struct CHINT9_R(crate::FieldReader); +impl CHINT9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT10` reader - Channel 10 Pending Interrupt"] +pub struct CHINT10_R(crate::FieldReader); +impl CHINT10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT11` reader - Channel 11 Pending Interrupt"] +pub struct CHINT11_R(crate::FieldReader); +impl CHINT11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Channel 0 Pending Interrupt"] + #[inline(always)] + pub fn chint0(&self) -> CHINT0_R { + CHINT0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel 1 Pending Interrupt"] + #[inline(always)] + pub fn chint1(&self) -> CHINT1_R { + CHINT1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel 2 Pending Interrupt"] + #[inline(always)] + pub fn chint2(&self) -> CHINT2_R { + CHINT2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Channel 3 Pending Interrupt"] + #[inline(always)] + pub fn chint3(&self) -> CHINT3_R { + CHINT3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Channel 4 Pending Interrupt"] + #[inline(always)] + pub fn chint4(&self) -> CHINT4_R { + CHINT4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Channel 5 Pending Interrupt"] + #[inline(always)] + pub fn chint5(&self) -> CHINT5_R { + CHINT5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Channel 6 Pending Interrupt"] + #[inline(always)] + pub fn chint6(&self) -> CHINT6_R { + CHINT6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Channel 7 Pending Interrupt"] + #[inline(always)] + pub fn chint7(&self) -> CHINT7_R { + CHINT7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Channel 8 Pending Interrupt"] + #[inline(always)] + pub fn chint8(&self) -> CHINT8_R { + CHINT8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Channel 9 Pending Interrupt"] + #[inline(always)] + pub fn chint9(&self) -> CHINT9_R { + CHINT9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Channel 10 Pending Interrupt"] + #[inline(always)] + pub fn chint10(&self) -> CHINT10_R { + CHINT10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Channel 11 Pending Interrupt"] + #[inline(always)] + pub fn chint11(&self) -> CHINT11_R { + CHINT11_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +#[doc = "Interrupt Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intstatus](index.html) module"] +pub struct INTSTATUS_SPEC; +impl crate::RegisterSpec for INTSTATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intstatus::R](R) reader structure"] +impl crate::Readable for INTSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets INTSTATUS to value 0"] +impl crate::Resettable for INTSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/dmac/pendch.rs b/pac/atsamc21e/src/dmac/pendch.rs new file mode 100644 index 000000000000..8bb68ff8fa5d --- /dev/null +++ b/pac/atsamc21e/src/dmac/pendch.rs @@ -0,0 +1,273 @@ +#[doc = "Register `PENDCH` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PENDCH0` reader - Pending Channel 0"] +pub struct PENDCH0_R(crate::FieldReader); +impl PENDCH0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH1` reader - Pending Channel 1"] +pub struct PENDCH1_R(crate::FieldReader); +impl PENDCH1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH2` reader - Pending Channel 2"] +pub struct PENDCH2_R(crate::FieldReader); +impl PENDCH2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH3` reader - Pending Channel 3"] +pub struct PENDCH3_R(crate::FieldReader); +impl PENDCH3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH4` reader - Pending Channel 4"] +pub struct PENDCH4_R(crate::FieldReader); +impl PENDCH4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH5` reader - Pending Channel 5"] +pub struct PENDCH5_R(crate::FieldReader); +impl PENDCH5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH6` reader - Pending Channel 6"] +pub struct PENDCH6_R(crate::FieldReader); +impl PENDCH6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH7` reader - Pending Channel 7"] +pub struct PENDCH7_R(crate::FieldReader); +impl PENDCH7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH8` reader - Pending Channel 8"] +pub struct PENDCH8_R(crate::FieldReader); +impl PENDCH8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH9` reader - Pending Channel 9"] +pub struct PENDCH9_R(crate::FieldReader); +impl PENDCH9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH10` reader - Pending Channel 10"] +pub struct PENDCH10_R(crate::FieldReader); +impl PENDCH10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH11` reader - Pending Channel 11"] +pub struct PENDCH11_R(crate::FieldReader); +impl PENDCH11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Pending Channel 0"] + #[inline(always)] + pub fn pendch0(&self) -> PENDCH0_R { + PENDCH0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Pending Channel 1"] + #[inline(always)] + pub fn pendch1(&self) -> PENDCH1_R { + PENDCH1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Pending Channel 2"] + #[inline(always)] + pub fn pendch2(&self) -> PENDCH2_R { + PENDCH2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Pending Channel 3"] + #[inline(always)] + pub fn pendch3(&self) -> PENDCH3_R { + PENDCH3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Pending Channel 4"] + #[inline(always)] + pub fn pendch4(&self) -> PENDCH4_R { + PENDCH4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Pending Channel 5"] + #[inline(always)] + pub fn pendch5(&self) -> PENDCH5_R { + PENDCH5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Pending Channel 6"] + #[inline(always)] + pub fn pendch6(&self) -> PENDCH6_R { + PENDCH6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Pending Channel 7"] + #[inline(always)] + pub fn pendch7(&self) -> PENDCH7_R { + PENDCH7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Pending Channel 8"] + #[inline(always)] + pub fn pendch8(&self) -> PENDCH8_R { + PENDCH8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Pending Channel 9"] + #[inline(always)] + pub fn pendch9(&self) -> PENDCH9_R { + PENDCH9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Pending Channel 10"] + #[inline(always)] + pub fn pendch10(&self) -> PENDCH10_R { + PENDCH10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Pending Channel 11"] + #[inline(always)] + pub fn pendch11(&self) -> PENDCH11_R { + PENDCH11_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +#[doc = "Pending Channels\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pendch](index.html) module"] +pub struct PENDCH_SPEC; +impl crate::RegisterSpec for PENDCH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pendch::R](R) reader structure"] +impl crate::Readable for PENDCH_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PENDCH to value 0"] +impl crate::Resettable for PENDCH_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/dmac/prictrl0.rs b/pac/atsamc21e/src/dmac/prictrl0.rs new file mode 100644 index 000000000000..618e54ad23f2 --- /dev/null +++ b/pac/atsamc21e/src/dmac/prictrl0.rs @@ -0,0 +1,449 @@ +#[doc = "Register `PRICTRL0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PRICTRL0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `LVLPRI0` reader - Level 0 Channel Priority Number"] +pub struct LVLPRI0_R(crate::FieldReader); +impl LVLPRI0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LVLPRI0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLPRI0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLPRI0` writer - Level 0 Channel Priority Number"] +pub struct LVLPRI0_W<'a> { + w: &'a mut W, +} +impl<'a> LVLPRI0_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Level 0 Round-Robin Scheduling Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RRLVLEN0_A { + #[doc = "0: Static arbitration scheme for channels with level 3 priority"] + STATIC_LVL = 0, + #[doc = "1: Round-robin arbitration scheme for channels with level 3 priority"] + ROUND_ROBIN_LVL = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RRLVLEN0_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RRLVLEN0` reader - Level 0 Round-Robin Scheduling Enable"] +pub struct RRLVLEN0_R(crate::FieldReader); +impl RRLVLEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RRLVLEN0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RRLVLEN0_A { + match self.bits { + false => RRLVLEN0_A::STATIC_LVL, + true => RRLVLEN0_A::ROUND_ROBIN_LVL, + } + } + #[doc = "Checks if the value of the field is `STATIC_LVL`"] + #[inline(always)] + pub fn is_static_lvl(&self) -> bool { + **self == RRLVLEN0_A::STATIC_LVL + } + #[doc = "Checks if the value of the field is `ROUND_ROBIN_LVL`"] + #[inline(always)] + pub fn is_round_robin_lvl(&self) -> bool { + **self == RRLVLEN0_A::ROUND_ROBIN_LVL + } +} +impl core::ops::Deref for RRLVLEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RRLVLEN0` writer - Level 0 Round-Robin Scheduling Enable"] +pub struct RRLVLEN0_W<'a> { + w: &'a mut W, +} +impl<'a> RRLVLEN0_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RRLVLEN0_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Static arbitration scheme for channels with level 3 priority"] + #[inline(always)] + pub fn static_lvl(self) -> &'a mut W { + self.variant(RRLVLEN0_A::STATIC_LVL) + } + #[doc = "Round-robin arbitration scheme for channels with level 3 priority"] + #[inline(always)] + pub fn round_robin_lvl(self) -> &'a mut W { + self.variant(RRLVLEN0_A::ROUND_ROBIN_LVL) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `LVLPRI1` reader - Level 1 Channel Priority Number"] +pub struct LVLPRI1_R(crate::FieldReader); +impl LVLPRI1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LVLPRI1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLPRI1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLPRI1` writer - Level 1 Channel Priority Number"] +pub struct LVLPRI1_W<'a> { + w: &'a mut W, +} +impl<'a> LVLPRI1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 8)) | ((value as u32 & 0x0f) << 8); + self.w + } +} +#[doc = "Field `RRLVLEN1` reader - Level 1 Round-Robin Scheduling Enable"] +pub struct RRLVLEN1_R(crate::FieldReader); +impl RRLVLEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RRLVLEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RRLVLEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RRLVLEN1` writer - Level 1 Round-Robin Scheduling Enable"] +pub struct RRLVLEN1_W<'a> { + w: &'a mut W, +} +impl<'a> RRLVLEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `LVLPRI2` reader - Level 2 Channel Priority Number"] +pub struct LVLPRI2_R(crate::FieldReader); +impl LVLPRI2_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LVLPRI2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLPRI2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLPRI2` writer - Level 2 Channel Priority Number"] +pub struct LVLPRI2_W<'a> { + w: &'a mut W, +} +impl<'a> LVLPRI2_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 16)) | ((value as u32 & 0x0f) << 16); + self.w + } +} +#[doc = "Field `RRLVLEN2` reader - Level 2 Round-Robin Scheduling Enable"] +pub struct RRLVLEN2_R(crate::FieldReader); +impl RRLVLEN2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RRLVLEN2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RRLVLEN2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RRLVLEN2` writer - Level 2 Round-Robin Scheduling Enable"] +pub struct RRLVLEN2_W<'a> { + w: &'a mut W, +} +impl<'a> RRLVLEN2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `LVLPRI3` reader - Level 3 Channel Priority Number"] +pub struct LVLPRI3_R(crate::FieldReader); +impl LVLPRI3_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LVLPRI3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLPRI3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLPRI3` writer - Level 3 Channel Priority Number"] +pub struct LVLPRI3_W<'a> { + w: &'a mut W, +} +impl<'a> LVLPRI3_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Field `RRLVLEN3` reader - Level 3 Round-Robin Scheduling Enable"] +pub struct RRLVLEN3_R(crate::FieldReader); +impl RRLVLEN3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RRLVLEN3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RRLVLEN3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RRLVLEN3` writer - Level 3 Round-Robin Scheduling Enable"] +pub struct RRLVLEN3_W<'a> { + w: &'a mut W, +} +impl<'a> RRLVLEN3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Level 0 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri0(&self) -> LVLPRI0_R { + LVLPRI0_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 7 - Level 0 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen0(&self) -> RRLVLEN0_R { + RRLVLEN0_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:11 - Level 1 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri1(&self) -> LVLPRI1_R { + LVLPRI1_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 15 - Level 1 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen1(&self) -> RRLVLEN1_R { + RRLVLEN1_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:19 - Level 2 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri2(&self) -> LVLPRI2_R { + LVLPRI2_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 23 - Level 2 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen2(&self) -> RRLVLEN2_R { + RRLVLEN2_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bits 24:27 - Level 3 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri3(&self) -> LVLPRI3_R { + LVLPRI3_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 31 - Level 3 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen3(&self) -> RRLVLEN3_R { + RRLVLEN3_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Level 0 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri0(&mut self) -> LVLPRI0_W { + LVLPRI0_W { w: self } + } + #[doc = "Bit 7 - Level 0 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen0(&mut self) -> RRLVLEN0_W { + RRLVLEN0_W { w: self } + } + #[doc = "Bits 8:11 - Level 1 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri1(&mut self) -> LVLPRI1_W { + LVLPRI1_W { w: self } + } + #[doc = "Bit 15 - Level 1 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen1(&mut self) -> RRLVLEN1_W { + RRLVLEN1_W { w: self } + } + #[doc = "Bits 16:19 - Level 2 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri2(&mut self) -> LVLPRI2_W { + LVLPRI2_W { w: self } + } + #[doc = "Bit 23 - Level 2 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen2(&mut self) -> RRLVLEN2_W { + RRLVLEN2_W { w: self } + } + #[doc = "Bits 24:27 - Level 3 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri3(&mut self) -> LVLPRI3_W { + LVLPRI3_W { w: self } + } + #[doc = "Bit 31 - Level 3 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen3(&mut self) -> RRLVLEN3_W { + RRLVLEN3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Priority Control 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [prictrl0](index.html) module"] +pub struct PRICTRL0_SPEC; +impl crate::RegisterSpec for PRICTRL0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [prictrl0::R](R) reader structure"] +impl crate::Readable for PRICTRL0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [prictrl0::W](W) writer structure"] +impl crate::Writable for PRICTRL0_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PRICTRL0 to value 0"] +impl crate::Resettable for PRICTRL0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/dmac/qosctrl.rs b/pac/atsamc21e/src/dmac/qosctrl.rs new file mode 100644 index 000000000000..016fcaa221ef --- /dev/null +++ b/pac/atsamc21e/src/dmac/qosctrl.rs @@ -0,0 +1,402 @@ +#[doc = "Register `QOSCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `QOSCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Write-Back Quality of Service\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WRBQOS_A { + #[doc = "0: Background (no sensitive operation)"] + DISABLE = 0, + #[doc = "1: Sensitive Bandwidth"] + LOW = 1, + #[doc = "2: Sensitive Latency"] + MEDIUM = 2, + #[doc = "3: Critical Latency"] + HIGH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WRBQOS_A) -> Self { + variant as _ + } +} +#[doc = "Field `WRBQOS` reader - Write-Back Quality of Service"] +pub struct WRBQOS_R(crate::FieldReader); +impl WRBQOS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WRBQOS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> WRBQOS_A { + match self.bits { + 0 => WRBQOS_A::DISABLE, + 1 => WRBQOS_A::LOW, + 2 => WRBQOS_A::MEDIUM, + 3 => WRBQOS_A::HIGH, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == WRBQOS_A::DISABLE + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == WRBQOS_A::LOW + } + #[doc = "Checks if the value of the field is `MEDIUM`"] + #[inline(always)] + pub fn is_medium(&self) -> bool { + **self == WRBQOS_A::MEDIUM + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == WRBQOS_A::HIGH + } +} +impl core::ops::Deref for WRBQOS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WRBQOS` writer - Write-Back Quality of Service"] +pub struct WRBQOS_W<'a> { + w: &'a mut W, +} +impl<'a> WRBQOS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WRBQOS_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Background (no sensitive operation)"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(WRBQOS_A::DISABLE) + } + #[doc = "Sensitive Bandwidth"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(WRBQOS_A::LOW) + } + #[doc = "Sensitive Latency"] + #[inline(always)] + pub fn medium(self) -> &'a mut W { + self.variant(WRBQOS_A::MEDIUM) + } + #[doc = "Critical Latency"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(WRBQOS_A::HIGH) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u8 & 0x03); + self.w + } +} +#[doc = "Fetch Quality of Service\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FQOS_A { + #[doc = "0: Background (no sensitive operation)"] + DISABLE = 0, + #[doc = "1: Sensitive Bandwidth"] + LOW = 1, + #[doc = "2: Sensitive Latency"] + MEDIUM = 2, + #[doc = "3: Critical Latency"] + HIGH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FQOS_A) -> Self { + variant as _ + } +} +#[doc = "Field `FQOS` reader - Fetch Quality of Service"] +pub struct FQOS_R(crate::FieldReader); +impl FQOS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FQOS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FQOS_A { + match self.bits { + 0 => FQOS_A::DISABLE, + 1 => FQOS_A::LOW, + 2 => FQOS_A::MEDIUM, + 3 => FQOS_A::HIGH, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == FQOS_A::DISABLE + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == FQOS_A::LOW + } + #[doc = "Checks if the value of the field is `MEDIUM`"] + #[inline(always)] + pub fn is_medium(&self) -> bool { + **self == FQOS_A::MEDIUM + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == FQOS_A::HIGH + } +} +impl core::ops::Deref for FQOS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FQOS` writer - Fetch Quality of Service"] +pub struct FQOS_W<'a> { + w: &'a mut W, +} +impl<'a> FQOS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FQOS_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Background (no sensitive operation)"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(FQOS_A::DISABLE) + } + #[doc = "Sensitive Bandwidth"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(FQOS_A::LOW) + } + #[doc = "Sensitive Latency"] + #[inline(always)] + pub fn medium(self) -> &'a mut W { + self.variant(FQOS_A::MEDIUM) + } + #[doc = "Critical Latency"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(FQOS_A::HIGH) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u8 & 0x03) << 2); + self.w + } +} +#[doc = "Data Transfer Quality of Service\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DQOS_A { + #[doc = "0: Background (no sensitive operation)"] + DISABLE = 0, + #[doc = "1: Sensitive Bandwidth"] + LOW = 1, + #[doc = "2: Sensitive Latency"] + MEDIUM = 2, + #[doc = "3: Critical Latency"] + HIGH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DQOS_A) -> Self { + variant as _ + } +} +#[doc = "Field `DQOS` reader - Data Transfer Quality of Service"] +pub struct DQOS_R(crate::FieldReader); +impl DQOS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DQOS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DQOS_A { + match self.bits { + 0 => DQOS_A::DISABLE, + 1 => DQOS_A::LOW, + 2 => DQOS_A::MEDIUM, + 3 => DQOS_A::HIGH, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == DQOS_A::DISABLE + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == DQOS_A::LOW + } + #[doc = "Checks if the value of the field is `MEDIUM`"] + #[inline(always)] + pub fn is_medium(&self) -> bool { + **self == DQOS_A::MEDIUM + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == DQOS_A::HIGH + } +} +impl core::ops::Deref for DQOS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DQOS` writer - Data Transfer Quality of Service"] +pub struct DQOS_W<'a> { + w: &'a mut W, +} +impl<'a> DQOS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DQOS_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Background (no sensitive operation)"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(DQOS_A::DISABLE) + } + #[doc = "Sensitive Bandwidth"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(DQOS_A::LOW) + } + #[doc = "Sensitive Latency"] + #[inline(always)] + pub fn medium(self) -> &'a mut W { + self.variant(DQOS_A::MEDIUM) + } + #[doc = "Critical Latency"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(DQOS_A::HIGH) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u8 & 0x03) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Write-Back Quality of Service"] + #[inline(always)] + pub fn wrbqos(&self) -> WRBQOS_R { + WRBQOS_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bits 2:3 - Fetch Quality of Service"] + #[inline(always)] + pub fn fqos(&self) -> FQOS_R { + FQOS_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bits 4:5 - Data Transfer Quality of Service"] + #[inline(always)] + pub fn dqos(&self) -> DQOS_R { + DQOS_R::new(((self.bits >> 4) & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Write-Back Quality of Service"] + #[inline(always)] + pub fn wrbqos(&mut self) -> WRBQOS_W { + WRBQOS_W { w: self } + } + #[doc = "Bits 2:3 - Fetch Quality of Service"] + #[inline(always)] + pub fn fqos(&mut self) -> FQOS_W { + FQOS_W { w: self } + } + #[doc = "Bits 4:5 - Data Transfer Quality of Service"] + #[inline(always)] + pub fn dqos(&mut self) -> DQOS_W { + DQOS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "QOS Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [qosctrl](index.html) module"] +pub struct QOSCTRL_SPEC; +impl crate::RegisterSpec for QOSCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [qosctrl::R](R) reader structure"] +impl crate::Readable for QOSCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [qosctrl::W](W) writer structure"] +impl crate::Writable for QOSCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets QOSCTRL to value 0x2a"] +impl crate::Resettable for QOSCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x2a + } +} diff --git a/pac/atsamc21e/src/dmac/swtrigctrl.rs b/pac/atsamc21e/src/dmac/swtrigctrl.rs new file mode 100644 index 000000000000..8590fef852dc --- /dev/null +++ b/pac/atsamc21e/src/dmac/swtrigctrl.rs @@ -0,0 +1,630 @@ +#[doc = "Register `SWTRIGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SWTRIGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWTRIG0` reader - Channel 0 Software Trigger"] +pub struct SWTRIG0_R(crate::FieldReader); +impl SWTRIG0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG0` writer - Channel 0 Software Trigger"] +pub struct SWTRIG0_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `SWTRIG1` reader - Channel 1 Software Trigger"] +pub struct SWTRIG1_R(crate::FieldReader); +impl SWTRIG1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG1` writer - Channel 1 Software Trigger"] +pub struct SWTRIG1_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SWTRIG2` reader - Channel 2 Software Trigger"] +pub struct SWTRIG2_R(crate::FieldReader); +impl SWTRIG2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG2` writer - Channel 2 Software Trigger"] +pub struct SWTRIG2_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SWTRIG3` reader - Channel 3 Software Trigger"] +pub struct SWTRIG3_R(crate::FieldReader); +impl SWTRIG3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG3` writer - Channel 3 Software Trigger"] +pub struct SWTRIG3_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `SWTRIG4` reader - Channel 4 Software Trigger"] +pub struct SWTRIG4_R(crate::FieldReader); +impl SWTRIG4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG4` writer - Channel 4 Software Trigger"] +pub struct SWTRIG4_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `SWTRIG5` reader - Channel 5 Software Trigger"] +pub struct SWTRIG5_R(crate::FieldReader); +impl SWTRIG5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG5` writer - Channel 5 Software Trigger"] +pub struct SWTRIG5_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `SWTRIG6` reader - Channel 6 Software Trigger"] +pub struct SWTRIG6_R(crate::FieldReader); +impl SWTRIG6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG6` writer - Channel 6 Software Trigger"] +pub struct SWTRIG6_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `SWTRIG7` reader - Channel 7 Software Trigger"] +pub struct SWTRIG7_R(crate::FieldReader); +impl SWTRIG7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG7` writer - Channel 7 Software Trigger"] +pub struct SWTRIG7_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `SWTRIG8` reader - Channel 8 Software Trigger"] +pub struct SWTRIG8_R(crate::FieldReader); +impl SWTRIG8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG8` writer - Channel 8 Software Trigger"] +pub struct SWTRIG8_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `SWTRIG9` reader - Channel 9 Software Trigger"] +pub struct SWTRIG9_R(crate::FieldReader); +impl SWTRIG9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG9` writer - Channel 9 Software Trigger"] +pub struct SWTRIG9_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `SWTRIG10` reader - Channel 10 Software Trigger"] +pub struct SWTRIG10_R(crate::FieldReader); +impl SWTRIG10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG10` writer - Channel 10 Software Trigger"] +pub struct SWTRIG10_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `SWTRIG11` reader - Channel 11 Software Trigger"] +pub struct SWTRIG11_R(crate::FieldReader); +impl SWTRIG11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG11` writer - Channel 11 Software Trigger"] +pub struct SWTRIG11_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +impl R { + #[doc = "Bit 0 - Channel 0 Software Trigger"] + #[inline(always)] + pub fn swtrig0(&self) -> SWTRIG0_R { + SWTRIG0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel 1 Software Trigger"] + #[inline(always)] + pub fn swtrig1(&self) -> SWTRIG1_R { + SWTRIG1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel 2 Software Trigger"] + #[inline(always)] + pub fn swtrig2(&self) -> SWTRIG2_R { + SWTRIG2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Channel 3 Software Trigger"] + #[inline(always)] + pub fn swtrig3(&self) -> SWTRIG3_R { + SWTRIG3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Channel 4 Software Trigger"] + #[inline(always)] + pub fn swtrig4(&self) -> SWTRIG4_R { + SWTRIG4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Channel 5 Software Trigger"] + #[inline(always)] + pub fn swtrig5(&self) -> SWTRIG5_R { + SWTRIG5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Channel 6 Software Trigger"] + #[inline(always)] + pub fn swtrig6(&self) -> SWTRIG6_R { + SWTRIG6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Channel 7 Software Trigger"] + #[inline(always)] + pub fn swtrig7(&self) -> SWTRIG7_R { + SWTRIG7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Channel 8 Software Trigger"] + #[inline(always)] + pub fn swtrig8(&self) -> SWTRIG8_R { + SWTRIG8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Channel 9 Software Trigger"] + #[inline(always)] + pub fn swtrig9(&self) -> SWTRIG9_R { + SWTRIG9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Channel 10 Software Trigger"] + #[inline(always)] + pub fn swtrig10(&self) -> SWTRIG10_R { + SWTRIG10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Channel 11 Software Trigger"] + #[inline(always)] + pub fn swtrig11(&self) -> SWTRIG11_R { + SWTRIG11_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel 0 Software Trigger"] + #[inline(always)] + pub fn swtrig0(&mut self) -> SWTRIG0_W { + SWTRIG0_W { w: self } + } + #[doc = "Bit 1 - Channel 1 Software Trigger"] + #[inline(always)] + pub fn swtrig1(&mut self) -> SWTRIG1_W { + SWTRIG1_W { w: self } + } + #[doc = "Bit 2 - Channel 2 Software Trigger"] + #[inline(always)] + pub fn swtrig2(&mut self) -> SWTRIG2_W { + SWTRIG2_W { w: self } + } + #[doc = "Bit 3 - Channel 3 Software Trigger"] + #[inline(always)] + pub fn swtrig3(&mut self) -> SWTRIG3_W { + SWTRIG3_W { w: self } + } + #[doc = "Bit 4 - Channel 4 Software Trigger"] + #[inline(always)] + pub fn swtrig4(&mut self) -> SWTRIG4_W { + SWTRIG4_W { w: self } + } + #[doc = "Bit 5 - Channel 5 Software Trigger"] + #[inline(always)] + pub fn swtrig5(&mut self) -> SWTRIG5_W { + SWTRIG5_W { w: self } + } + #[doc = "Bit 6 - Channel 6 Software Trigger"] + #[inline(always)] + pub fn swtrig6(&mut self) -> SWTRIG6_W { + SWTRIG6_W { w: self } + } + #[doc = "Bit 7 - Channel 7 Software Trigger"] + #[inline(always)] + pub fn swtrig7(&mut self) -> SWTRIG7_W { + SWTRIG7_W { w: self } + } + #[doc = "Bit 8 - Channel 8 Software Trigger"] + #[inline(always)] + pub fn swtrig8(&mut self) -> SWTRIG8_W { + SWTRIG8_W { w: self } + } + #[doc = "Bit 9 - Channel 9 Software Trigger"] + #[inline(always)] + pub fn swtrig9(&mut self) -> SWTRIG9_W { + SWTRIG9_W { w: self } + } + #[doc = "Bit 10 - Channel 10 Software Trigger"] + #[inline(always)] + pub fn swtrig10(&mut self) -> SWTRIG10_W { + SWTRIG10_W { w: self } + } + #[doc = "Bit 11 - Channel 11 Software Trigger"] + #[inline(always)] + pub fn swtrig11(&mut self) -> SWTRIG11_W { + SWTRIG11_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Software Trigger Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [swtrigctrl](index.html) module"] +pub struct SWTRIGCTRL_SPEC; +impl crate::RegisterSpec for SWTRIGCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [swtrigctrl::R](R) reader structure"] +impl crate::Readable for SWTRIGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [swtrigctrl::W](W) writer structure"] +impl crate::Writable for SWTRIGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SWTRIGCTRL to value 0"] +impl crate::Resettable for SWTRIGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/dmac/wrbaddr.rs b/pac/atsamc21e/src/dmac/wrbaddr.rs new file mode 100644 index 000000000000..ccf2a376b853 --- /dev/null +++ b/pac/atsamc21e/src/dmac/wrbaddr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `WRBADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WRBADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WRBADDR` reader - Write-Back Memory Base Address"] +pub struct WRBADDR_R(crate::FieldReader); +impl WRBADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + WRBADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WRBADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WRBADDR` writer - Write-Back Memory Base Address"] +pub struct WRBADDR_W<'a> { + w: &'a mut W, +} +impl<'a> WRBADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Write-Back Memory Base Address"] + #[inline(always)] + pub fn wrbaddr(&self) -> WRBADDR_R { + WRBADDR_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Write-Back Memory Base Address"] + #[inline(always)] + pub fn wrbaddr(&mut self) -> WRBADDR_W { + WRBADDR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Write-Back Memory Section Base Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wrbaddr](index.html) module"] +pub struct WRBADDR_SPEC; +impl crate::RegisterSpec for WRBADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [wrbaddr::R](R) reader structure"] +impl crate::Readable for WRBADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wrbaddr::W](W) writer structure"] +impl crate::Writable for WRBADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WRBADDR to value 0"] +impl crate::Resettable for WRBADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/dsu.rs b/pac/atsamc21e/src/dsu.rs new file mode 100644 index 000000000000..88324f764961 --- /dev/null +++ b/pac/atsamc21e/src/dsu.rs @@ -0,0 +1,163 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrl: crate::Reg, + #[doc = "0x01 - Status A"] + pub statusa: crate::Reg, + #[doc = "0x02 - Status B"] + pub statusb: crate::Reg, + #[doc = "0x03 - Status C"] + pub statusc: crate::Reg, + #[doc = "0x04 - Address"] + pub addr: crate::Reg, + #[doc = "0x08 - Length"] + pub length: crate::Reg, + #[doc = "0x0c - Data"] + pub data: crate::Reg, + #[doc = "0x10..0x18 - Debug Communication Channel n"] + pub dcc: [crate::Reg; 2], + #[doc = "0x18 - Device Identification"] + pub did: crate::Reg, + _reserved9: [u8; 0xd4], + #[doc = "0xf0..0xf8 - Device Configuration"] + pub dcfg: [crate::Reg; 2], + _reserved10: [u8; 0x0f08], + #[doc = "0x1000 - CoreSight ROM Table Entry 0"] + pub entry0: crate::Reg, + #[doc = "0x1004 - CoreSight ROM Table Entry 1"] + pub entry1: crate::Reg, + #[doc = "0x1008 - CoreSight ROM Table End"] + pub end: crate::Reg, + _reserved13: [u8; 0x0fc0], + #[doc = "0x1fcc - CoreSight ROM Table Memory Type"] + pub memtype: crate::Reg, + #[doc = "0x1fd0 - Peripheral Identification 4"] + pub pid4: crate::Reg, + #[doc = "0x1fd4 - Peripheral Identification 5"] + pub pid5: crate::Reg, + #[doc = "0x1fd8 - Peripheral Identification 6"] + pub pid6: crate::Reg, + #[doc = "0x1fdc - Peripheral Identification 7"] + pub pid7: crate::Reg, + #[doc = "0x1fe0 - Peripheral Identification 0"] + pub pid0: crate::Reg, + #[doc = "0x1fe4 - Peripheral Identification 1"] + pub pid1: crate::Reg, + #[doc = "0x1fe8 - Peripheral Identification 2"] + pub pid2: crate::Reg, + #[doc = "0x1fec - Peripheral Identification 3"] + pub pid3: crate::Reg, + #[doc = "0x1ff0 - Component Identification 0"] + pub cid0: crate::Reg, + #[doc = "0x1ff4 - Component Identification 1"] + pub cid1: crate::Reg, + #[doc = "0x1ff8 - Component Identification 2"] + pub cid2: crate::Reg, + #[doc = "0x1ffc - Component Identification 3"] + pub cid3: crate::Reg, +} +#[doc = "CTRL register accessor: an alias for `Reg`"] +pub type CTRL = crate::Reg; +#[doc = "Control"] +pub mod ctrl; +#[doc = "STATUSA register accessor: an alias for `Reg`"] +pub type STATUSA = crate::Reg; +#[doc = "Status A"] +pub mod statusa; +#[doc = "STATUSB register accessor: an alias for `Reg`"] +pub type STATUSB = crate::Reg; +#[doc = "Status B"] +pub mod statusb; +#[doc = "STATUSC register accessor: an alias for `Reg`"] +pub type STATUSC = crate::Reg; +#[doc = "Status C"] +pub mod statusc; +#[doc = "ADDR register accessor: an alias for `Reg`"] +pub type ADDR = crate::Reg; +#[doc = "Address"] +pub mod addr; +#[doc = "LENGTH register accessor: an alias for `Reg`"] +pub type LENGTH = crate::Reg; +#[doc = "Length"] +pub mod length; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "Data"] +pub mod data; +#[doc = "DCC register accessor: an alias for `Reg`"] +pub type DCC = crate::Reg; +#[doc = "Debug Communication Channel n"] +pub mod dcc; +#[doc = "DID register accessor: an alias for `Reg`"] +pub type DID = crate::Reg; +#[doc = "Device Identification"] +pub mod did; +#[doc = "DCFG register accessor: an alias for `Reg`"] +pub type DCFG = crate::Reg; +#[doc = "Device Configuration"] +pub mod dcfg; +#[doc = "ENTRY0 register accessor: an alias for `Reg`"] +pub type ENTRY0 = crate::Reg; +#[doc = "CoreSight ROM Table Entry 0"] +pub mod entry0; +#[doc = "ENTRY1 register accessor: an alias for `Reg`"] +pub type ENTRY1 = crate::Reg; +#[doc = "CoreSight ROM Table Entry 1"] +pub mod entry1; +#[doc = "END register accessor: an alias for `Reg`"] +pub type END = crate::Reg; +#[doc = "CoreSight ROM Table End"] +pub mod end; +#[doc = "MEMTYPE register accessor: an alias for `Reg`"] +pub type MEMTYPE = crate::Reg; +#[doc = "CoreSight ROM Table Memory Type"] +pub mod memtype; +#[doc = "PID4 register accessor: an alias for `Reg`"] +pub type PID4 = crate::Reg; +#[doc = "Peripheral Identification 4"] +pub mod pid4; +#[doc = "PID5 register accessor: an alias for `Reg`"] +pub type PID5 = crate::Reg; +#[doc = "Peripheral Identification 5"] +pub mod pid5; +#[doc = "PID6 register accessor: an alias for `Reg`"] +pub type PID6 = crate::Reg; +#[doc = "Peripheral Identification 6"] +pub mod pid6; +#[doc = "PID7 register accessor: an alias for `Reg`"] +pub type PID7 = crate::Reg; +#[doc = "Peripheral Identification 7"] +pub mod pid7; +#[doc = "PID0 register accessor: an alias for `Reg`"] +pub type PID0 = crate::Reg; +#[doc = "Peripheral Identification 0"] +pub mod pid0; +#[doc = "PID1 register accessor: an alias for `Reg`"] +pub type PID1 = crate::Reg; +#[doc = "Peripheral Identification 1"] +pub mod pid1; +#[doc = "PID2 register accessor: an alias for `Reg`"] +pub type PID2 = crate::Reg; +#[doc = "Peripheral Identification 2"] +pub mod pid2; +#[doc = "PID3 register accessor: an alias for `Reg`"] +pub type PID3 = crate::Reg; +#[doc = "Peripheral Identification 3"] +pub mod pid3; +#[doc = "CID0 register accessor: an alias for `Reg`"] +pub type CID0 = crate::Reg; +#[doc = "Component Identification 0"] +pub mod cid0; +#[doc = "CID1 register accessor: an alias for `Reg`"] +pub type CID1 = crate::Reg; +#[doc = "Component Identification 1"] +pub mod cid1; +#[doc = "CID2 register accessor: an alias for `Reg`"] +pub type CID2 = crate::Reg; +#[doc = "Component Identification 2"] +pub mod cid2; +#[doc = "CID3 register accessor: an alias for `Reg`"] +pub type CID3 = crate::Reg; +#[doc = "Component Identification 3"] +pub mod cid3; diff --git a/pac/atsamc21e/src/dsu/addr.rs b/pac/atsamc21e/src/dsu/addr.rs new file mode 100644 index 000000000000..412f874d6b15 --- /dev/null +++ b/pac/atsamc21e/src/dsu/addr.rs @@ -0,0 +1,140 @@ +#[doc = "Register `ADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `AMOD` reader - Access Mode"] +pub struct AMOD_R(crate::FieldReader); +impl AMOD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + AMOD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AMOD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AMOD` writer - Access Mode"] +pub struct AMOD_W<'a> { + w: &'a mut W, +} +impl<'a> AMOD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u32 & 0x03); + self.w + } +} +#[doc = "Field `ADDR` reader - Address"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - Address"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3fff_ffff << 2)) | ((value as u32 & 0x3fff_ffff) << 2); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Access Mode"] + #[inline(always)] + pub fn amod(&self) -> AMOD_R { + AMOD_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bits 2:31 - Address"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new(((self.bits >> 2) & 0x3fff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:1 - Access Mode"] + #[inline(always)] + pub fn amod(&mut self) -> AMOD_W { + AMOD_W { w: self } + } + #[doc = "Bits 2:31 - Address"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [addr](index.html) module"] +pub struct ADDR_SPEC; +impl crate::RegisterSpec for ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [addr::R](R) reader structure"] +impl crate::Readable for ADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [addr::W](W) writer structure"] +impl crate::Writable for ADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ADDR to value 0"] +impl crate::Resettable for ADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/dsu/cid0.rs b/pac/atsamc21e/src/dsu/cid0.rs new file mode 100644 index 000000000000..b3c2373dfc99 --- /dev/null +++ b/pac/atsamc21e/src/dsu/cid0.rs @@ -0,0 +1,53 @@ +#[doc = "Register `CID0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PREAMBLEB0` reader - Preamble Byte 0"] +pub struct PREAMBLEB0_R(crate::FieldReader); +impl PREAMBLEB0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PREAMBLEB0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PREAMBLEB0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:7 - Preamble Byte 0"] + #[inline(always)] + pub fn preambleb0(&self) -> PREAMBLEB0_R { + PREAMBLEB0_R::new((self.bits & 0xff) as u8) + } +} +#[doc = "Component Identification 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid0](index.html) module"] +pub struct CID0_SPEC; +impl crate::RegisterSpec for CID0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid0::R](R) reader structure"] +impl crate::Readable for CID0_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID0 to value 0x0d"] +impl crate::Resettable for CID0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0d + } +} diff --git a/pac/atsamc21e/src/dsu/cid1.rs b/pac/atsamc21e/src/dsu/cid1.rs new file mode 100644 index 000000000000..3628ceac64a7 --- /dev/null +++ b/pac/atsamc21e/src/dsu/cid1.rs @@ -0,0 +1,73 @@ +#[doc = "Register `CID1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PREAMBLE` reader - Preamble"] +pub struct PREAMBLE_R(crate::FieldReader); +impl PREAMBLE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PREAMBLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PREAMBLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCLASS` reader - Component Class"] +pub struct CCLASS_R(crate::FieldReader); +impl CCLASS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CCLASS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCLASS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:3 - Preamble"] + #[inline(always)] + pub fn preamble(&self) -> PREAMBLE_R { + PREAMBLE_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Component Class"] + #[inline(always)] + pub fn cclass(&self) -> CCLASS_R { + CCLASS_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +#[doc = "Component Identification 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid1](index.html) module"] +pub struct CID1_SPEC; +impl crate::RegisterSpec for CID1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid1::R](R) reader structure"] +impl crate::Readable for CID1_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID1 to value 0x10"] +impl crate::Resettable for CID1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x10 + } +} diff --git a/pac/atsamc21e/src/dsu/cid2.rs b/pac/atsamc21e/src/dsu/cid2.rs new file mode 100644 index 000000000000..714078d5c430 --- /dev/null +++ b/pac/atsamc21e/src/dsu/cid2.rs @@ -0,0 +1,53 @@ +#[doc = "Register `CID2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PREAMBLEB2` reader - Preamble Byte 2"] +pub struct PREAMBLEB2_R(crate::FieldReader); +impl PREAMBLEB2_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PREAMBLEB2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PREAMBLEB2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:7 - Preamble Byte 2"] + #[inline(always)] + pub fn preambleb2(&self) -> PREAMBLEB2_R { + PREAMBLEB2_R::new((self.bits & 0xff) as u8) + } +} +#[doc = "Component Identification 2\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid2](index.html) module"] +pub struct CID2_SPEC; +impl crate::RegisterSpec for CID2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid2::R](R) reader structure"] +impl crate::Readable for CID2_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID2 to value 0x05"] +impl crate::Resettable for CID2_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x05 + } +} diff --git a/pac/atsamc21e/src/dsu/cid3.rs b/pac/atsamc21e/src/dsu/cid3.rs new file mode 100644 index 000000000000..a345af7b5166 --- /dev/null +++ b/pac/atsamc21e/src/dsu/cid3.rs @@ -0,0 +1,53 @@ +#[doc = "Register `CID3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PREAMBLEB3` reader - Preamble Byte 3"] +pub struct PREAMBLEB3_R(crate::FieldReader); +impl PREAMBLEB3_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PREAMBLEB3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PREAMBLEB3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:7 - Preamble Byte 3"] + #[inline(always)] + pub fn preambleb3(&self) -> PREAMBLEB3_R { + PREAMBLEB3_R::new((self.bits & 0xff) as u8) + } +} +#[doc = "Component Identification 3\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid3](index.html) module"] +pub struct CID3_SPEC; +impl crate::RegisterSpec for CID3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid3::R](R) reader structure"] +impl crate::Readable for CID3_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID3 to value 0xb1"] +impl crate::Resettable for CID3_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xb1 + } +} diff --git a/pac/atsamc21e/src/dsu/ctrl.rs b/pac/atsamc21e/src/dsu/ctrl.rs new file mode 100644 index 000000000000..0a19db5a5239 --- /dev/null +++ b/pac/atsamc21e/src/dsu/ctrl.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `CRC` writer - 32-bit Cyclic Redundancy Code"] +pub struct CRC_W<'a> { + w: &'a mut W, +} +impl<'a> CRC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `MBIST` writer - Memory built-in self-test"] +pub struct MBIST_W<'a> { + w: &'a mut W, +} +impl<'a> MBIST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CE` writer - Chip-Erase"] +pub struct CE_W<'a> { + w: &'a mut W, +} +impl<'a> CE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `ARR` writer - Auxiliary Row Read"] +pub struct ARR_W<'a> { + w: &'a mut W, +} +impl<'a> ARR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +#[doc = "Field `SMSA` writer - Start Memory Stream Access"] +pub struct SMSA_W<'a> { + w: &'a mut W, +} +impl<'a> SMSA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 2 - 32-bit Cyclic Redundancy Code"] + #[inline(always)] + pub fn crc(&mut self) -> CRC_W { + CRC_W { w: self } + } + #[doc = "Bit 3 - Memory built-in self-test"] + #[inline(always)] + pub fn mbist(&mut self) -> MBIST_W { + MBIST_W { w: self } + } + #[doc = "Bit 4 - Chip-Erase"] + #[inline(always)] + pub fn ce(&mut self) -> CE_W { + CE_W { w: self } + } + #[doc = "Bit 6 - Auxiliary Row Read"] + #[inline(always)] + pub fn arr(&mut self) -> ARR_W { + ARR_W { w: self } + } + #[doc = "Bit 7 - Start Memory Stream Access"] + #[inline(always)] + pub fn smsa(&mut self) -> SMSA_W { + SMSA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"] +pub struct CTRL_SPEC; +impl crate::RegisterSpec for CTRL_SPEC { + type Ux = u8; +} +#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"] +impl crate::Writable for CTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/dsu/data.rs b/pac/atsamc21e/src/dsu/data.rs new file mode 100644 index 000000000000..193cc49a07fd --- /dev/null +++ b/pac/atsamc21e/src/dsu/data.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Data"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Data"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/dsu/dcc.rs b/pac/atsamc21e/src/dsu/dcc.rs new file mode 100644 index 000000000000..354323a499ef --- /dev/null +++ b/pac/atsamc21e/src/dsu/dcc.rs @@ -0,0 +1,104 @@ +#[doc = "Register `DCC[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DCC[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Data"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Data"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Communication Channel n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dcc](index.html) module"] +pub struct DCC_SPEC; +impl crate::RegisterSpec for DCC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dcc::R](R) reader structure"] +impl crate::Readable for DCC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dcc::W](W) writer structure"] +impl crate::Writable for DCC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DCC[%s] +to value 0"] +impl crate::Resettable for DCC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/dsu/dcfg.rs b/pac/atsamc21e/src/dsu/dcfg.rs new file mode 100644 index 000000000000..c6d61d0b496e --- /dev/null +++ b/pac/atsamc21e/src/dsu/dcfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `DCFG[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DCFG[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DCFG` reader - Device Configuration"] +pub struct DCFG_R(crate::FieldReader); +impl DCFG_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + DCFG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DCFG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DCFG` writer - Device Configuration"] +pub struct DCFG_W<'a> { + w: &'a mut W, +} +impl<'a> DCFG_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Device Configuration"] + #[inline(always)] + pub fn dcfg(&self) -> DCFG_R { + DCFG_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Device Configuration"] + #[inline(always)] + pub fn dcfg(&mut self) -> DCFG_W { + DCFG_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Device Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dcfg](index.html) module"] +pub struct DCFG_SPEC; +impl crate::RegisterSpec for DCFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dcfg::R](R) reader structure"] +impl crate::Readable for DCFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dcfg::W](W) writer structure"] +impl crate::Writable for DCFG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DCFG[%s] +to value 0"] +impl crate::Resettable for DCFG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/dsu/did.rs b/pac/atsamc21e/src/dsu/did.rs new file mode 100644 index 000000000000..785d232ecac5 --- /dev/null +++ b/pac/atsamc21e/src/dsu/did.rs @@ -0,0 +1,279 @@ +#[doc = "Register `DID` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `DEVSEL` reader - Device Select"] +pub struct DEVSEL_R(crate::FieldReader); +impl DEVSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DEVSEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DEVSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REVISION` reader - Revision Number"] +pub struct REVISION_R(crate::FieldReader); +impl REVISION_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REVISION_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REVISION_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIE` reader - Die Number"] +pub struct DIE_R(crate::FieldReader); +impl DIE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DIE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Series\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SERIES_A { + #[doc = "0: Cortex-M0+ processor, basic feature set"] + _0 = 0, + #[doc = "1: Cortex-M0+ processor, CAN"] + _1 = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SERIES_A) -> Self { + variant as _ + } +} +#[doc = "Field `SERIES` reader - Series"] +pub struct SERIES_R(crate::FieldReader); +impl SERIES_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SERIES_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SERIES_A::_0), + 1 => Some(SERIES_A::_1), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_0`"] + #[inline(always)] + pub fn is_0(&self) -> bool { + **self == SERIES_A::_0 + } + #[doc = "Checks if the value of the field is `_1`"] + #[inline(always)] + pub fn is_1(&self) -> bool { + **self == SERIES_A::_1 + } +} +impl core::ops::Deref for SERIES_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Family\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FAMILY_A { + #[doc = "0: General purpose microcontroller"] + _0 = 0, + #[doc = "1: PicoPower"] + _1 = 1, + #[doc = "2: 5V Industrial"] + _2 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FAMILY_A) -> Self { + variant as _ + } +} +#[doc = "Field `FAMILY` reader - Family"] +pub struct FAMILY_R(crate::FieldReader); +impl FAMILY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FAMILY_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(FAMILY_A::_0), + 1 => Some(FAMILY_A::_1), + 2 => Some(FAMILY_A::_2), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_0`"] + #[inline(always)] + pub fn is_0(&self) -> bool { + **self == FAMILY_A::_0 + } + #[doc = "Checks if the value of the field is `_1`"] + #[inline(always)] + pub fn is_1(&self) -> bool { + **self == FAMILY_A::_1 + } + #[doc = "Checks if the value of the field is `_2`"] + #[inline(always)] + pub fn is_2(&self) -> bool { + **self == FAMILY_A::_2 + } +} +impl core::ops::Deref for FAMILY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Processor\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PROCESSOR_A { + #[doc = "0: Cortex-M0"] + _0 = 0, + #[doc = "1: Cortex-M0+"] + _1 = 1, + #[doc = "2: Cortex-M3"] + _2 = 2, + #[doc = "3: Cortex-M4"] + _3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PROCESSOR_A) -> Self { + variant as _ + } +} +#[doc = "Field `PROCESSOR` reader - Processor"] +pub struct PROCESSOR_R(crate::FieldReader); +impl PROCESSOR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PROCESSOR_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PROCESSOR_A::_0), + 1 => Some(PROCESSOR_A::_1), + 2 => Some(PROCESSOR_A::_2), + 3 => Some(PROCESSOR_A::_3), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_0`"] + #[inline(always)] + pub fn is_0(&self) -> bool { + **self == PROCESSOR_A::_0 + } + #[doc = "Checks if the value of the field is `_1`"] + #[inline(always)] + pub fn is_1(&self) -> bool { + **self == PROCESSOR_A::_1 + } + #[doc = "Checks if the value of the field is `_2`"] + #[inline(always)] + pub fn is_2(&self) -> bool { + **self == PROCESSOR_A::_2 + } + #[doc = "Checks if the value of the field is `_3`"] + #[inline(always)] + pub fn is_3(&self) -> bool { + **self == PROCESSOR_A::_3 + } +} +impl core::ops::Deref for PROCESSOR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:7 - Device Select"] + #[inline(always)] + pub fn devsel(&self) -> DEVSEL_R { + DEVSEL_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:11 - Revision Number"] + #[inline(always)] + pub fn revision(&self) -> REVISION_R { + REVISION_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - Die Number"] + #[inline(always)] + pub fn die(&self) -> DIE_R { + DIE_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:21 - Series"] + #[inline(always)] + pub fn series(&self) -> SERIES_R { + SERIES_R::new(((self.bits >> 16) & 0x3f) as u8) + } + #[doc = "Bits 23:27 - Family"] + #[inline(always)] + pub fn family(&self) -> FAMILY_R { + FAMILY_R::new(((self.bits >> 23) & 0x1f) as u8) + } + #[doc = "Bits 28:31 - Processor"] + #[inline(always)] + pub fn processor(&self) -> PROCESSOR_R { + PROCESSOR_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +#[doc = "Device Identification\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [did](index.html) module"] +pub struct DID_SPEC; +impl crate::RegisterSpec for DID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [did::R](R) reader structure"] +impl crate::Readable for DID_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DID to value 0x1101_050a"] +impl crate::Resettable for DID_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x1101_050a + } +} diff --git a/pac/atsamc21e/src/dsu/end.rs b/pac/atsamc21e/src/dsu/end.rs new file mode 100644 index 000000000000..cce2edea2bce --- /dev/null +++ b/pac/atsamc21e/src/dsu/end.rs @@ -0,0 +1,53 @@ +#[doc = "Register `END` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `END` reader - End Marker"] +pub struct END_R(crate::FieldReader); +impl END_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + END_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for END_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - End Marker"] + #[inline(always)] + pub fn end(&self) -> END_R { + END_R::new(self.bits as u32) + } +} +#[doc = "CoreSight ROM Table End\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [end](index.html) module"] +pub struct END_SPEC; +impl crate::RegisterSpec for END_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [end::R](R) reader structure"] +impl crate::Readable for END_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets END to value 0"] +impl crate::Resettable for END_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/dsu/entry0.rs b/pac/atsamc21e/src/dsu/entry0.rs new file mode 100644 index 000000000000..d8563990e827 --- /dev/null +++ b/pac/atsamc21e/src/dsu/entry0.rs @@ -0,0 +1,93 @@ +#[doc = "Register `ENTRY0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `EPRES` reader - Entry Present"] +pub struct EPRES_R(crate::FieldReader); +impl EPRES_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EPRES_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EPRES_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FMT` reader - Format"] +pub struct FMT_R(crate::FieldReader); +impl FMT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FMT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FMT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDOFF` reader - Address Offset"] +pub struct ADDOFF_R(crate::FieldReader); +impl ADDOFF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + ADDOFF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDOFF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Entry Present"] + #[inline(always)] + pub fn epres(&self) -> EPRES_R { + EPRES_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Format"] + #[inline(always)] + pub fn fmt(&self) -> FMT_R { + FMT_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 12:31 - Address Offset"] + #[inline(always)] + pub fn addoff(&self) -> ADDOFF_R { + ADDOFF_R::new(((self.bits >> 12) & 0x000f_ffff) as u32) + } +} +#[doc = "CoreSight ROM Table Entry 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [entry0](index.html) module"] +pub struct ENTRY0_SPEC; +impl crate::RegisterSpec for ENTRY0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [entry0::R](R) reader structure"] +impl crate::Readable for ENTRY0_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets ENTRY0 to value 0x9f0f_c002"] +impl crate::Resettable for ENTRY0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x9f0f_c002 + } +} diff --git a/pac/atsamc21e/src/dsu/entry1.rs b/pac/atsamc21e/src/dsu/entry1.rs new file mode 100644 index 000000000000..cec8fa367705 --- /dev/null +++ b/pac/atsamc21e/src/dsu/entry1.rs @@ -0,0 +1,31 @@ +#[doc = "Register `ENTRY1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "CoreSight ROM Table Entry 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [entry1](index.html) module"] +pub struct ENTRY1_SPEC; +impl crate::RegisterSpec for ENTRY1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [entry1::R](R) reader structure"] +impl crate::Readable for ENTRY1_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets ENTRY1 to value 0x5002"] +impl crate::Resettable for ENTRY1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x5002 + } +} diff --git a/pac/atsamc21e/src/dsu/length.rs b/pac/atsamc21e/src/dsu/length.rs new file mode 100644 index 000000000000..2dc771f74dfd --- /dev/null +++ b/pac/atsamc21e/src/dsu/length.rs @@ -0,0 +1,103 @@ +#[doc = "Register `LENGTH` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `LENGTH` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `LENGTH` reader - Length"] +pub struct LENGTH_R(crate::FieldReader); +impl LENGTH_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + LENGTH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LENGTH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LENGTH` writer - Length"] +pub struct LENGTH_W<'a> { + w: &'a mut W, +} +impl<'a> LENGTH_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3fff_ffff << 2)) | ((value as u32 & 0x3fff_ffff) << 2); + self.w + } +} +impl R { + #[doc = "Bits 2:31 - Length"] + #[inline(always)] + pub fn length(&self) -> LENGTH_R { + LENGTH_R::new(((self.bits >> 2) & 0x3fff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 2:31 - Length"] + #[inline(always)] + pub fn length(&mut self) -> LENGTH_W { + LENGTH_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Length\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [length](index.html) module"] +pub struct LENGTH_SPEC; +impl crate::RegisterSpec for LENGTH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [length::R](R) reader structure"] +impl crate::Readable for LENGTH_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [length::W](W) writer structure"] +impl crate::Writable for LENGTH_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets LENGTH to value 0"] +impl crate::Resettable for LENGTH_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/dsu/memtype.rs b/pac/atsamc21e/src/dsu/memtype.rs new file mode 100644 index 000000000000..3cc841e2ba78 --- /dev/null +++ b/pac/atsamc21e/src/dsu/memtype.rs @@ -0,0 +1,53 @@ +#[doc = "Register `MEMTYPE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SMEMP` reader - System Memory Present"] +pub struct SMEMP_R(crate::FieldReader); +impl SMEMP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SMEMP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SMEMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - System Memory Present"] + #[inline(always)] + pub fn smemp(&self) -> SMEMP_R { + SMEMP_R::new((self.bits & 0x01) != 0) + } +} +#[doc = "CoreSight ROM Table Memory Type\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [memtype](index.html) module"] +pub struct MEMTYPE_SPEC; +impl crate::RegisterSpec for MEMTYPE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [memtype::R](R) reader structure"] +impl crate::Readable for MEMTYPE_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets MEMTYPE to value 0"] +impl crate::Resettable for MEMTYPE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/dsu/pid0.rs b/pac/atsamc21e/src/dsu/pid0.rs new file mode 100644 index 000000000000..98028ea62838 --- /dev/null +++ b/pac/atsamc21e/src/dsu/pid0.rs @@ -0,0 +1,53 @@ +#[doc = "Register `PID0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PARTNBL` reader - Part Number Low"] +pub struct PARTNBL_R(crate::FieldReader); +impl PARTNBL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PARTNBL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PARTNBL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:7 - Part Number Low"] + #[inline(always)] + pub fn partnbl(&self) -> PARTNBL_R { + PARTNBL_R::new((self.bits & 0xff) as u8) + } +} +#[doc = "Peripheral Identification 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid0](index.html) module"] +pub struct PID0_SPEC; +impl crate::RegisterSpec for PID0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid0::R](R) reader structure"] +impl crate::Readable for PID0_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID0 to value 0xd0"] +impl crate::Resettable for PID0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xd0 + } +} diff --git a/pac/atsamc21e/src/dsu/pid1.rs b/pac/atsamc21e/src/dsu/pid1.rs new file mode 100644 index 000000000000..4f94b853507c --- /dev/null +++ b/pac/atsamc21e/src/dsu/pid1.rs @@ -0,0 +1,73 @@ +#[doc = "Register `PID1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PARTNBH` reader - Part Number High"] +pub struct PARTNBH_R(crate::FieldReader); +impl PARTNBH_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PARTNBH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PARTNBH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `JEPIDCL` reader - Low part of the JEP-106 Identity Code"] +pub struct JEPIDCL_R(crate::FieldReader); +impl JEPIDCL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + JEPIDCL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for JEPIDCL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:3 - Part Number High"] + #[inline(always)] + pub fn partnbh(&self) -> PARTNBH_R { + PARTNBH_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Low part of the JEP-106 Identity Code"] + #[inline(always)] + pub fn jepidcl(&self) -> JEPIDCL_R { + JEPIDCL_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +#[doc = "Peripheral Identification 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid1](index.html) module"] +pub struct PID1_SPEC; +impl crate::RegisterSpec for PID1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid1::R](R) reader structure"] +impl crate::Readable for PID1_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID1 to value 0xfc"] +impl crate::Resettable for PID1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xfc + } +} diff --git a/pac/atsamc21e/src/dsu/pid2.rs b/pac/atsamc21e/src/dsu/pid2.rs new file mode 100644 index 000000000000..d8f8ed10192e --- /dev/null +++ b/pac/atsamc21e/src/dsu/pid2.rs @@ -0,0 +1,93 @@ +#[doc = "Register `PID2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `JEPIDCH` reader - JEP-106 Identity Code High"] +pub struct JEPIDCH_R(crate::FieldReader); +impl JEPIDCH_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + JEPIDCH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for JEPIDCH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `JEPU` reader - JEP-106 Identity Code is used"] +pub struct JEPU_R(crate::FieldReader); +impl JEPU_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + JEPU_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for JEPU_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REVISION` reader - Revision Number"] +pub struct REVISION_R(crate::FieldReader); +impl REVISION_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REVISION_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REVISION_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:2 - JEP-106 Identity Code High"] + #[inline(always)] + pub fn jepidch(&self) -> JEPIDCH_R { + JEPIDCH_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 3 - JEP-106 Identity Code is used"] + #[inline(always)] + pub fn jepu(&self) -> JEPU_R { + JEPU_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bits 4:7 - Revision Number"] + #[inline(always)] + pub fn revision(&self) -> REVISION_R { + REVISION_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +#[doc = "Peripheral Identification 2\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid2](index.html) module"] +pub struct PID2_SPEC; +impl crate::RegisterSpec for PID2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid2::R](R) reader structure"] +impl crate::Readable for PID2_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID2 to value 0x09"] +impl crate::Resettable for PID2_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x09 + } +} diff --git a/pac/atsamc21e/src/dsu/pid3.rs b/pac/atsamc21e/src/dsu/pid3.rs new file mode 100644 index 000000000000..c0a8fb2d7f92 --- /dev/null +++ b/pac/atsamc21e/src/dsu/pid3.rs @@ -0,0 +1,73 @@ +#[doc = "Register `PID3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `CUSMOD` reader - ARM CUSMOD"] +pub struct CUSMOD_R(crate::FieldReader); +impl CUSMOD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CUSMOD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CUSMOD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REVAND` reader - Revision Number"] +pub struct REVAND_R(crate::FieldReader); +impl REVAND_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REVAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REVAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:3 - ARM CUSMOD"] + #[inline(always)] + pub fn cusmod(&self) -> CUSMOD_R { + CUSMOD_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Revision Number"] + #[inline(always)] + pub fn revand(&self) -> REVAND_R { + REVAND_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +#[doc = "Peripheral Identification 3\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid3](index.html) module"] +pub struct PID3_SPEC; +impl crate::RegisterSpec for PID3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid3::R](R) reader structure"] +impl crate::Readable for PID3_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID3 to value 0"] +impl crate::Resettable for PID3_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/dsu/pid4.rs b/pac/atsamc21e/src/dsu/pid4.rs new file mode 100644 index 000000000000..d3a1bd120f0b --- /dev/null +++ b/pac/atsamc21e/src/dsu/pid4.rs @@ -0,0 +1,73 @@ +#[doc = "Register `PID4` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `JEPCC` reader - JEP-106 Continuation Code"] +pub struct JEPCC_R(crate::FieldReader); +impl JEPCC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + JEPCC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for JEPCC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FKBC` reader - 4KB count"] +pub struct FKBC_R(crate::FieldReader); +impl FKBC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FKBC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FKBC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:3 - JEP-106 Continuation Code"] + #[inline(always)] + pub fn jepcc(&self) -> JEPCC_R { + JEPCC_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - 4KB count"] + #[inline(always)] + pub fn fkbc(&self) -> FKBC_R { + FKBC_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +#[doc = "Peripheral Identification 4\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid4](index.html) module"] +pub struct PID4_SPEC; +impl crate::RegisterSpec for PID4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid4::R](R) reader structure"] +impl crate::Readable for PID4_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID4 to value 0"] +impl crate::Resettable for PID4_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/dsu/pid5.rs b/pac/atsamc21e/src/dsu/pid5.rs new file mode 100644 index 000000000000..d343d4800b95 --- /dev/null +++ b/pac/atsamc21e/src/dsu/pid5.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID5` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 5\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid5](index.html) module"] +pub struct PID5_SPEC; +impl crate::RegisterSpec for PID5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid5::R](R) reader structure"] +impl crate::Readable for PID5_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID5 to value 0"] +impl crate::Resettable for PID5_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/dsu/pid6.rs b/pac/atsamc21e/src/dsu/pid6.rs new file mode 100644 index 000000000000..55cc2b8b5861 --- /dev/null +++ b/pac/atsamc21e/src/dsu/pid6.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID6` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 6\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid6](index.html) module"] +pub struct PID6_SPEC; +impl crate::RegisterSpec for PID6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid6::R](R) reader structure"] +impl crate::Readable for PID6_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID6 to value 0"] +impl crate::Resettable for PID6_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/dsu/pid7.rs b/pac/atsamc21e/src/dsu/pid7.rs new file mode 100644 index 000000000000..77664d4f2f95 --- /dev/null +++ b/pac/atsamc21e/src/dsu/pid7.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID7` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 7\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid7](index.html) module"] +pub struct PID7_SPEC; +impl crate::RegisterSpec for PID7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid7::R](R) reader structure"] +impl crate::Readable for PID7_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID7 to value 0"] +impl crate::Resettable for PID7_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/dsu/statusa.rs b/pac/atsamc21e/src/dsu/statusa.rs new file mode 100644 index 000000000000..c7b90a13e491 --- /dev/null +++ b/pac/atsamc21e/src/dsu/statusa.rs @@ -0,0 +1,301 @@ +#[doc = "Register `STATUSA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUSA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DONE` reader - Done"] +pub struct DONE_R(crate::FieldReader); +impl DONE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DONE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DONE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DONE` writer - Done"] +pub struct DONE_W<'a> { + w: &'a mut W, +} +impl<'a> DONE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `CRSTEXT` reader - CPU Reset Phase Extension"] +pub struct CRSTEXT_R(crate::FieldReader); +impl CRSTEXT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CRSTEXT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CRSTEXT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRSTEXT` writer - CPU Reset Phase Extension"] +pub struct CRSTEXT_W<'a> { + w: &'a mut W, +} +impl<'a> CRSTEXT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `BERR` reader - Bus Error"] +pub struct BERR_R(crate::FieldReader); +impl BERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BERR` writer - Bus Error"] +pub struct BERR_W<'a> { + w: &'a mut W, +} +impl<'a> BERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `FAIL` reader - Failure"] +pub struct FAIL_R(crate::FieldReader); +impl FAIL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAIL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAIL` writer - Failure"] +pub struct FAIL_W<'a> { + w: &'a mut W, +} +impl<'a> FAIL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PERR` reader - Protection Error"] +pub struct PERR_R(crate::FieldReader); +impl PERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERR` writer - Protection Error"] +pub struct PERR_W<'a> { + w: &'a mut W, +} +impl<'a> PERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +impl R { + #[doc = "Bit 0 - Done"] + #[inline(always)] + pub fn done(&self) -> DONE_R { + DONE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - CPU Reset Phase Extension"] + #[inline(always)] + pub fn crstext(&self) -> CRSTEXT_R { + CRSTEXT_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Bus Error"] + #[inline(always)] + pub fn berr(&self) -> BERR_R { + BERR_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Failure"] + #[inline(always)] + pub fn fail(&self) -> FAIL_R { + FAIL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Protection Error"] + #[inline(always)] + pub fn perr(&self) -> PERR_R { + PERR_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Done"] + #[inline(always)] + pub fn done(&mut self) -> DONE_W { + DONE_W { w: self } + } + #[doc = "Bit 1 - CPU Reset Phase Extension"] + #[inline(always)] + pub fn crstext(&mut self) -> CRSTEXT_W { + CRSTEXT_W { w: self } + } + #[doc = "Bit 2 - Bus Error"] + #[inline(always)] + pub fn berr(&mut self) -> BERR_W { + BERR_W { w: self } + } + #[doc = "Bit 3 - Failure"] + #[inline(always)] + pub fn fail(&mut self) -> FAIL_W { + FAIL_W { w: self } + } + #[doc = "Bit 4 - Protection Error"] + #[inline(always)] + pub fn perr(&mut self) -> PERR_W { + PERR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [statusa](index.html) module"] +pub struct STATUSA_SPEC; +impl crate::RegisterSpec for STATUSA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [statusa::R](R) reader structure"] +impl crate::Readable for STATUSA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [statusa::W](W) writer structure"] +impl crate::Writable for STATUSA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUSA to value 0"] +impl crate::Resettable for STATUSA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/dsu/statusb.rs b/pac/atsamc21e/src/dsu/statusb.rs new file mode 100644 index 000000000000..1e9374f8deae --- /dev/null +++ b/pac/atsamc21e/src/dsu/statusb.rs @@ -0,0 +1,133 @@ +#[doc = "Register `STATUSB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PROT` reader - Protected"] +pub struct PROT_R(crate::FieldReader); +impl PROT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PROT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PROT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGPRES` reader - Debugger Present"] +pub struct DBGPRES_R(crate::FieldReader); +impl DBGPRES_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGPRES_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGPRES_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DCCD0` reader - Debug Communication Channel 0 Dirty"] +pub struct DCCD0_R(crate::FieldReader); +impl DCCD0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DCCD0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DCCD0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DCCD1` reader - Debug Communication Channel 1 Dirty"] +pub struct DCCD1_R(crate::FieldReader); +impl DCCD1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DCCD1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DCCD1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HPE` reader - Hot-Plugging Enable"] +pub struct HPE_R(crate::FieldReader); +impl HPE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HPE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HPE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Protected"] + #[inline(always)] + pub fn prot(&self) -> PROT_R { + PROT_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Debugger Present"] + #[inline(always)] + pub fn dbgpres(&self) -> DBGPRES_R { + DBGPRES_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Debug Communication Channel 0 Dirty"] + #[inline(always)] + pub fn dccd0(&self) -> DCCD0_R { + DCCD0_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Debug Communication Channel 1 Dirty"] + #[inline(always)] + pub fn dccd1(&self) -> DCCD1_R { + DCCD1_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Hot-Plugging Enable"] + #[inline(always)] + pub fn hpe(&self) -> HPE_R { + HPE_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +#[doc = "Status B\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [statusb](index.html) module"] +pub struct STATUSB_SPEC; +impl crate::RegisterSpec for STATUSB_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [statusb::R](R) reader structure"] +impl crate::Readable for STATUSB_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUSB to value 0"] +impl crate::Resettable for STATUSB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/dsu/statusc.rs b/pac/atsamc21e/src/dsu/statusc.rs new file mode 100644 index 000000000000..14b3f7b1c7e3 --- /dev/null +++ b/pac/atsamc21e/src/dsu/statusc.rs @@ -0,0 +1,53 @@ +#[doc = "Register `STATUSC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `STATE` reader - State"] +pub struct STATE_R(crate::FieldReader); +impl STATE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + STATE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STATE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:2 - State"] + #[inline(always)] + pub fn state(&self) -> STATE_R { + STATE_R::new((self.bits & 0x07) as u8) + } +} +#[doc = "Status C\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [statusc](index.html) module"] +pub struct STATUSC_SPEC; +impl crate::RegisterSpec for STATUSC_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [statusc::R](R) reader structure"] +impl crate::Readable for STATUSC_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUSC to value 0"] +impl crate::Resettable for STATUSC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/eic.rs b/pac/atsamc21e/src/eic.rs new file mode 100644 index 000000000000..606231233f4b --- /dev/null +++ b/pac/atsamc21e/src/eic.rs @@ -0,0 +1,64 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrla: crate::Reg, + #[doc = "0x01 - NMI Control"] + pub nmictrl: crate::Reg, + #[doc = "0x02 - NMI Interrupt Flag"] + pub nmiflag: crate::Reg, + #[doc = "0x04 - Syncbusy register"] + pub syncbusy: crate::Reg, + #[doc = "0x08 - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x0c - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x10 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x14 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x18 - EIC Asynchronous edge Detection Enable"] + pub asynch: crate::Reg, + #[doc = "0x1c..0x24 - Configuration n"] + pub config: [crate::Reg; 2], +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control"] +pub mod ctrla; +#[doc = "NMICTRL register accessor: an alias for `Reg`"] +pub type NMICTRL = crate::Reg; +#[doc = "NMI Control"] +pub mod nmictrl; +#[doc = "NMIFLAG register accessor: an alias for `Reg`"] +pub type NMIFLAG = crate::Reg; +#[doc = "NMI Interrupt Flag"] +pub mod nmiflag; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Syncbusy register"] +pub mod syncbusy; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "ASYNCH register accessor: an alias for `Reg`"] +pub type ASYNCH = crate::Reg; +#[doc = "EIC Asynchronous edge Detection Enable"] +pub mod asynch; +#[doc = "CONFIG register accessor: an alias for `Reg`"] +pub type CONFIG = crate::Reg; +#[doc = "Configuration n"] +pub mod config; diff --git a/pac/atsamc21e/src/eic/asynch.rs b/pac/atsamc21e/src/eic/asynch.rs new file mode 100644 index 000000000000..78a9b5c5f054 --- /dev/null +++ b/pac/atsamc21e/src/eic/asynch.rs @@ -0,0 +1,152 @@ +#[doc = "Register `ASYNCH` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ASYNCH` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "EIC Asynchronous edge Detection Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u16)] +pub enum ASYNCH_A { + #[doc = "0: Edge detection is clock synchronously operated"] + SYNC = 0, + #[doc = "1: Edge detection is clock asynchronously operated"] + ASYNC = 1, +} +impl From for u16 { + #[inline(always)] + fn from(variant: ASYNCH_A) -> Self { + variant as _ + } +} +#[doc = "Field `ASYNCH` reader - EIC Asynchronous edge Detection Enable"] +pub struct ASYNCH_R(crate::FieldReader); +impl ASYNCH_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + ASYNCH_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(ASYNCH_A::SYNC), + 1 => Some(ASYNCH_A::ASYNC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `SYNC`"] + #[inline(always)] + pub fn is_sync(&self) -> bool { + **self == ASYNCH_A::SYNC + } + #[doc = "Checks if the value of the field is `ASYNC`"] + #[inline(always)] + pub fn is_async(&self) -> bool { + **self == ASYNCH_A::ASYNC + } +} +impl core::ops::Deref for ASYNCH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ASYNCH` writer - EIC Asynchronous edge Detection Enable"] +pub struct ASYNCH_W<'a> { + w: &'a mut W, +} +impl<'a> ASYNCH_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: ASYNCH_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Edge detection is clock synchronously operated"] + #[inline(always)] + pub fn sync(self) -> &'a mut W { + self.variant(ASYNCH_A::SYNC) + } + #[doc = "Edge detection is clock asynchronously operated"] + #[inline(always)] + pub fn async_(self) -> &'a mut W { + self.variant(ASYNCH_A::ASYNC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - EIC Asynchronous edge Detection Enable"] + #[inline(always)] + pub fn asynch(&self) -> ASYNCH_R { + ASYNCH_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - EIC Asynchronous edge Detection Enable"] + #[inline(always)] + pub fn asynch(&mut self) -> ASYNCH_W { + ASYNCH_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "EIC Asynchronous edge Detection Enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [asynch](index.html) module"] +pub struct ASYNCH_SPEC; +impl crate::RegisterSpec for ASYNCH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [asynch::R](R) reader structure"] +impl crate::Readable for ASYNCH_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [asynch::W](W) writer structure"] +impl crate::Writable for ASYNCH_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ASYNCH to value 0"] +impl crate::Resettable for ASYNCH_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/eic/config.rs b/pac/atsamc21e/src/eic/config.rs new file mode 100644 index 000000000000..ab2c30950417 --- /dev/null +++ b/pac/atsamc21e/src/eic/config.rs @@ -0,0 +1,1547 @@ +#[doc = "Register `CONFIG[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CONFIG[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Input Sense Configuration 0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE0_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE0_A) -> Self { + variant as _ + } +} +#[doc = "Field `SENSE0` reader - Input Sense Configuration 0"] +pub struct SENSE0_R(crate::FieldReader); +impl SENSE0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SENSE0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE0_A::NONE), + 1 => Some(SENSE0_A::RISE), + 2 => Some(SENSE0_A::FALL), + 3 => Some(SENSE0_A::BOTH), + 4 => Some(SENSE0_A::HIGH), + 5 => Some(SENSE0_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == SENSE0_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == SENSE0_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == SENSE0_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == SENSE0_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SENSE0_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SENSE0_A::LOW + } +} +impl core::ops::Deref for SENSE0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SENSE0` writer - Input Sense Configuration 0"] +pub struct SENSE0_W<'a> { + w: &'a mut W, +} +impl<'a> SENSE0_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SENSE0_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE0_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE0_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE0_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE0_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE0_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE0_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Field `FILTEN0` reader - Filter Enable 0"] +pub struct FILTEN0_R(crate::FieldReader); +impl FILTEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FILTEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTEN0` writer - Filter Enable 0"] +pub struct FILTEN0_W<'a> { + w: &'a mut W, +} +impl<'a> FILTEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Input Sense Configuration 1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE1_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE1_A) -> Self { + variant as _ + } +} +#[doc = "Field `SENSE1` reader - Input Sense Configuration 1"] +pub struct SENSE1_R(crate::FieldReader); +impl SENSE1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SENSE1_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE1_A::NONE), + 1 => Some(SENSE1_A::RISE), + 2 => Some(SENSE1_A::FALL), + 3 => Some(SENSE1_A::BOTH), + 4 => Some(SENSE1_A::HIGH), + 5 => Some(SENSE1_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == SENSE1_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == SENSE1_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == SENSE1_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == SENSE1_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SENSE1_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SENSE1_A::LOW + } +} +impl core::ops::Deref for SENSE1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SENSE1` writer - Input Sense Configuration 1"] +pub struct SENSE1_W<'a> { + w: &'a mut W, +} +impl<'a> SENSE1_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SENSE1_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE1_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE1_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE1_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE1_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE1_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE1_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 4)) | ((value as u32 & 0x07) << 4); + self.w + } +} +#[doc = "Field `FILTEN1` reader - Filter Enable 1"] +pub struct FILTEN1_R(crate::FieldReader); +impl FILTEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FILTEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTEN1` writer - Filter Enable 1"] +pub struct FILTEN1_W<'a> { + w: &'a mut W, +} +impl<'a> FILTEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Input Sense Configuration 2\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE2_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE2_A) -> Self { + variant as _ + } +} +#[doc = "Field `SENSE2` reader - Input Sense Configuration 2"] +pub struct SENSE2_R(crate::FieldReader); +impl SENSE2_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SENSE2_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE2_A::NONE), + 1 => Some(SENSE2_A::RISE), + 2 => Some(SENSE2_A::FALL), + 3 => Some(SENSE2_A::BOTH), + 4 => Some(SENSE2_A::HIGH), + 5 => Some(SENSE2_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == SENSE2_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == SENSE2_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == SENSE2_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == SENSE2_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SENSE2_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SENSE2_A::LOW + } +} +impl core::ops::Deref for SENSE2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SENSE2` writer - Input Sense Configuration 2"] +pub struct SENSE2_W<'a> { + w: &'a mut W, +} +impl<'a> SENSE2_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SENSE2_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE2_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE2_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE2_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE2_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE2_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE2_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +#[doc = "Field `FILTEN2` reader - Filter Enable 2"] +pub struct FILTEN2_R(crate::FieldReader); +impl FILTEN2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FILTEN2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTEN2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTEN2` writer - Filter Enable 2"] +pub struct FILTEN2_W<'a> { + w: &'a mut W, +} +impl<'a> FILTEN2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Input Sense Configuration 3\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE3_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE3_A) -> Self { + variant as _ + } +} +#[doc = "Field `SENSE3` reader - Input Sense Configuration 3"] +pub struct SENSE3_R(crate::FieldReader); +impl SENSE3_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SENSE3_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE3_A::NONE), + 1 => Some(SENSE3_A::RISE), + 2 => Some(SENSE3_A::FALL), + 3 => Some(SENSE3_A::BOTH), + 4 => Some(SENSE3_A::HIGH), + 5 => Some(SENSE3_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == SENSE3_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == SENSE3_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == SENSE3_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == SENSE3_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SENSE3_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SENSE3_A::LOW + } +} +impl core::ops::Deref for SENSE3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SENSE3` writer - Input Sense Configuration 3"] +pub struct SENSE3_W<'a> { + w: &'a mut W, +} +impl<'a> SENSE3_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SENSE3_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE3_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE3_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE3_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE3_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE3_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE3_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 12)) | ((value as u32 & 0x07) << 12); + self.w + } +} +#[doc = "Field `FILTEN3` reader - Filter Enable 3"] +pub struct FILTEN3_R(crate::FieldReader); +impl FILTEN3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FILTEN3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTEN3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTEN3` writer - Filter Enable 3"] +pub struct FILTEN3_W<'a> { + w: &'a mut W, +} +impl<'a> FILTEN3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Input Sense Configuration 4\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE4_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE4_A) -> Self { + variant as _ + } +} +#[doc = "Field `SENSE4` reader - Input Sense Configuration 4"] +pub struct SENSE4_R(crate::FieldReader); +impl SENSE4_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SENSE4_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE4_A::NONE), + 1 => Some(SENSE4_A::RISE), + 2 => Some(SENSE4_A::FALL), + 3 => Some(SENSE4_A::BOTH), + 4 => Some(SENSE4_A::HIGH), + 5 => Some(SENSE4_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == SENSE4_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == SENSE4_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == SENSE4_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == SENSE4_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SENSE4_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SENSE4_A::LOW + } +} +impl core::ops::Deref for SENSE4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SENSE4` writer - Input Sense Configuration 4"] +pub struct SENSE4_W<'a> { + w: &'a mut W, +} +impl<'a> SENSE4_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SENSE4_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE4_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE4_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE4_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE4_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE4_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE4_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 16)) | ((value as u32 & 0x07) << 16); + self.w + } +} +#[doc = "Field `FILTEN4` reader - Filter Enable 4"] +pub struct FILTEN4_R(crate::FieldReader); +impl FILTEN4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FILTEN4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTEN4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTEN4` writer - Filter Enable 4"] +pub struct FILTEN4_W<'a> { + w: &'a mut W, +} +impl<'a> FILTEN4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Input Sense Configuration 5\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE5_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE5_A) -> Self { + variant as _ + } +} +#[doc = "Field `SENSE5` reader - Input Sense Configuration 5"] +pub struct SENSE5_R(crate::FieldReader); +impl SENSE5_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SENSE5_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE5_A::NONE), + 1 => Some(SENSE5_A::RISE), + 2 => Some(SENSE5_A::FALL), + 3 => Some(SENSE5_A::BOTH), + 4 => Some(SENSE5_A::HIGH), + 5 => Some(SENSE5_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == SENSE5_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == SENSE5_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == SENSE5_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == SENSE5_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SENSE5_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SENSE5_A::LOW + } +} +impl core::ops::Deref for SENSE5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SENSE5` writer - Input Sense Configuration 5"] +pub struct SENSE5_W<'a> { + w: &'a mut W, +} +impl<'a> SENSE5_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SENSE5_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE5_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE5_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE5_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE5_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE5_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE5_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 20)) | ((value as u32 & 0x07) << 20); + self.w + } +} +#[doc = "Field `FILTEN5` reader - Filter Enable 5"] +pub struct FILTEN5_R(crate::FieldReader); +impl FILTEN5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FILTEN5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTEN5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTEN5` writer - Filter Enable 5"] +pub struct FILTEN5_W<'a> { + w: &'a mut W, +} +impl<'a> FILTEN5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Input Sense Configuration 6\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE6_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE6_A) -> Self { + variant as _ + } +} +#[doc = "Field `SENSE6` reader - Input Sense Configuration 6"] +pub struct SENSE6_R(crate::FieldReader); +impl SENSE6_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SENSE6_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE6_A::NONE), + 1 => Some(SENSE6_A::RISE), + 2 => Some(SENSE6_A::FALL), + 3 => Some(SENSE6_A::BOTH), + 4 => Some(SENSE6_A::HIGH), + 5 => Some(SENSE6_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == SENSE6_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == SENSE6_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == SENSE6_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == SENSE6_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SENSE6_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SENSE6_A::LOW + } +} +impl core::ops::Deref for SENSE6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SENSE6` writer - Input Sense Configuration 6"] +pub struct SENSE6_W<'a> { + w: &'a mut W, +} +impl<'a> SENSE6_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SENSE6_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE6_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE6_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE6_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE6_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE6_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE6_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 24)) | ((value as u32 & 0x07) << 24); + self.w + } +} +#[doc = "Field `FILTEN6` reader - Filter Enable 6"] +pub struct FILTEN6_R(crate::FieldReader); +impl FILTEN6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FILTEN6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTEN6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTEN6` writer - Filter Enable 6"] +pub struct FILTEN6_W<'a> { + w: &'a mut W, +} +impl<'a> FILTEN6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +#[doc = "Input Sense Configuration 7\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE7_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE7_A) -> Self { + variant as _ + } +} +#[doc = "Field `SENSE7` reader - Input Sense Configuration 7"] +pub struct SENSE7_R(crate::FieldReader); +impl SENSE7_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SENSE7_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE7_A::NONE), + 1 => Some(SENSE7_A::RISE), + 2 => Some(SENSE7_A::FALL), + 3 => Some(SENSE7_A::BOTH), + 4 => Some(SENSE7_A::HIGH), + 5 => Some(SENSE7_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == SENSE7_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == SENSE7_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == SENSE7_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == SENSE7_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SENSE7_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SENSE7_A::LOW + } +} +impl core::ops::Deref for SENSE7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SENSE7` writer - Input Sense Configuration 7"] +pub struct SENSE7_W<'a> { + w: &'a mut W, +} +impl<'a> SENSE7_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SENSE7_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE7_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE7_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE7_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE7_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE7_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE7_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 28)) | ((value as u32 & 0x07) << 28); + self.w + } +} +#[doc = "Field `FILTEN7` reader - Filter Enable 7"] +pub struct FILTEN7_R(crate::FieldReader); +impl FILTEN7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FILTEN7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTEN7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTEN7` writer - Filter Enable 7"] +pub struct FILTEN7_W<'a> { + w: &'a mut W, +} +impl<'a> FILTEN7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Input Sense Configuration 0"] + #[inline(always)] + pub fn sense0(&self) -> SENSE0_R { + SENSE0_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 3 - Filter Enable 0"] + #[inline(always)] + pub fn filten0(&self) -> FILTEN0_R { + FILTEN0_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bits 4:6 - Input Sense Configuration 1"] + #[inline(always)] + pub fn sense1(&self) -> SENSE1_R { + SENSE1_R::new(((self.bits >> 4) & 0x07) as u8) + } + #[doc = "Bit 7 - Filter Enable 1"] + #[inline(always)] + pub fn filten1(&self) -> FILTEN1_R { + FILTEN1_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Input Sense Configuration 2"] + #[inline(always)] + pub fn sense2(&self) -> SENSE2_R { + SENSE2_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 11 - Filter Enable 2"] + #[inline(always)] + pub fn filten2(&self) -> FILTEN2_R { + FILTEN2_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bits 12:14 - Input Sense Configuration 3"] + #[inline(always)] + pub fn sense3(&self) -> SENSE3_R { + SENSE3_R::new(((self.bits >> 12) & 0x07) as u8) + } + #[doc = "Bit 15 - Filter Enable 3"] + #[inline(always)] + pub fn filten3(&self) -> FILTEN3_R { + FILTEN3_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:18 - Input Sense Configuration 4"] + #[inline(always)] + pub fn sense4(&self) -> SENSE4_R { + SENSE4_R::new(((self.bits >> 16) & 0x07) as u8) + } + #[doc = "Bit 19 - Filter Enable 4"] + #[inline(always)] + pub fn filten4(&self) -> FILTEN4_R { + FILTEN4_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bits 20:22 - Input Sense Configuration 5"] + #[inline(always)] + pub fn sense5(&self) -> SENSE5_R { + SENSE5_R::new(((self.bits >> 20) & 0x07) as u8) + } + #[doc = "Bit 23 - Filter Enable 5"] + #[inline(always)] + pub fn filten5(&self) -> FILTEN5_R { + FILTEN5_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bits 24:26 - Input Sense Configuration 6"] + #[inline(always)] + pub fn sense6(&self) -> SENSE6_R { + SENSE6_R::new(((self.bits >> 24) & 0x07) as u8) + } + #[doc = "Bit 27 - Filter Enable 6"] + #[inline(always)] + pub fn filten6(&self) -> FILTEN6_R { + FILTEN6_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bits 28:30 - Input Sense Configuration 7"] + #[inline(always)] + pub fn sense7(&self) -> SENSE7_R { + SENSE7_R::new(((self.bits >> 28) & 0x07) as u8) + } + #[doc = "Bit 31 - Filter Enable 7"] + #[inline(always)] + pub fn filten7(&self) -> FILTEN7_R { + FILTEN7_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Input Sense Configuration 0"] + #[inline(always)] + pub fn sense0(&mut self) -> SENSE0_W { + SENSE0_W { w: self } + } + #[doc = "Bit 3 - Filter Enable 0"] + #[inline(always)] + pub fn filten0(&mut self) -> FILTEN0_W { + FILTEN0_W { w: self } + } + #[doc = "Bits 4:6 - Input Sense Configuration 1"] + #[inline(always)] + pub fn sense1(&mut self) -> SENSE1_W { + SENSE1_W { w: self } + } + #[doc = "Bit 7 - Filter Enable 1"] + #[inline(always)] + pub fn filten1(&mut self) -> FILTEN1_W { + FILTEN1_W { w: self } + } + #[doc = "Bits 8:10 - Input Sense Configuration 2"] + #[inline(always)] + pub fn sense2(&mut self) -> SENSE2_W { + SENSE2_W { w: self } + } + #[doc = "Bit 11 - Filter Enable 2"] + #[inline(always)] + pub fn filten2(&mut self) -> FILTEN2_W { + FILTEN2_W { w: self } + } + #[doc = "Bits 12:14 - Input Sense Configuration 3"] + #[inline(always)] + pub fn sense3(&mut self) -> SENSE3_W { + SENSE3_W { w: self } + } + #[doc = "Bit 15 - Filter Enable 3"] + #[inline(always)] + pub fn filten3(&mut self) -> FILTEN3_W { + FILTEN3_W { w: self } + } + #[doc = "Bits 16:18 - Input Sense Configuration 4"] + #[inline(always)] + pub fn sense4(&mut self) -> SENSE4_W { + SENSE4_W { w: self } + } + #[doc = "Bit 19 - Filter Enable 4"] + #[inline(always)] + pub fn filten4(&mut self) -> FILTEN4_W { + FILTEN4_W { w: self } + } + #[doc = "Bits 20:22 - Input Sense Configuration 5"] + #[inline(always)] + pub fn sense5(&mut self) -> SENSE5_W { + SENSE5_W { w: self } + } + #[doc = "Bit 23 - Filter Enable 5"] + #[inline(always)] + pub fn filten5(&mut self) -> FILTEN5_W { + FILTEN5_W { w: self } + } + #[doc = "Bits 24:26 - Input Sense Configuration 6"] + #[inline(always)] + pub fn sense6(&mut self) -> SENSE6_W { + SENSE6_W { w: self } + } + #[doc = "Bit 27 - Filter Enable 6"] + #[inline(always)] + pub fn filten6(&mut self) -> FILTEN6_W { + FILTEN6_W { w: self } + } + #[doc = "Bits 28:30 - Input Sense Configuration 7"] + #[inline(always)] + pub fn sense7(&mut self) -> SENSE7_W { + SENSE7_W { w: self } + } + #[doc = "Bit 31 - Filter Enable 7"] + #[inline(always)] + pub fn filten7(&mut self) -> FILTEN7_W { + FILTEN7_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Configuration n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [config](index.html) module"] +pub struct CONFIG_SPEC; +impl crate::RegisterSpec for CONFIG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [config::R](R) reader structure"] +impl crate::Readable for CONFIG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [config::W](W) writer structure"] +impl crate::Writable for CONFIG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CONFIG[%s] +to value 0"] +impl crate::Resettable for CONFIG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/eic/ctrla.rs b/pac/atsamc21e/src/eic/ctrla.rs new file mode 100644 index 000000000000..25e701dd3db2 --- /dev/null +++ b/pac/atsamc21e/src/eic/ctrla.rs @@ -0,0 +1,254 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Clock Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CKSEL_A { + #[doc = "0: Clocked by GCLK"] + CLK_GCLK = 0, + #[doc = "1: Clocked by ULP32K"] + CLK_ULP32K = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CKSEL_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CKSEL` reader - Clock Selection"] +pub struct CKSEL_R(crate::FieldReader); +impl CKSEL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CKSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CKSEL_A { + match self.bits { + false => CKSEL_A::CLK_GCLK, + true => CKSEL_A::CLK_ULP32K, + } + } + #[doc = "Checks if the value of the field is `CLK_GCLK`"] + #[inline(always)] + pub fn is_clk_gclk(&self) -> bool { + **self == CKSEL_A::CLK_GCLK + } + #[doc = "Checks if the value of the field is `CLK_ULP32K`"] + #[inline(always)] + pub fn is_clk_ulp32k(&self) -> bool { + **self == CKSEL_A::CLK_ULP32K + } +} +impl core::ops::Deref for CKSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CKSEL` writer - Clock Selection"] +pub struct CKSEL_W<'a> { + w: &'a mut W, +} +impl<'a> CKSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CKSEL_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Clocked by GCLK"] + #[inline(always)] + pub fn clk_gclk(self) -> &'a mut W { + self.variant(CKSEL_A::CLK_GCLK) + } + #[doc = "Clocked by ULP32K"] + #[inline(always)] + pub fn clk_ulp32k(self) -> &'a mut W { + self.variant(CKSEL_A::CLK_ULP32K) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - Clock Selection"] + #[inline(always)] + pub fn cksel(&self) -> CKSEL_R { + CKSEL_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 4 - Clock Selection"] + #[inline(always)] + pub fn cksel(&mut self) -> CKSEL_W { + CKSEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/eic/evctrl.rs b/pac/atsamc21e/src/eic/evctrl.rs new file mode 100644 index 000000000000..25adccf3558e --- /dev/null +++ b/pac/atsamc21e/src/eic/evctrl.rs @@ -0,0 +1,103 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EXTINTEO` reader - External Interrupt Event Output Enable"] +pub struct EXTINTEO_R(crate::FieldReader); +impl EXTINTEO_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + EXTINTEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINTEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINTEO` writer - External Interrupt Event Output Enable"] +pub struct EXTINTEO_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINTEO_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - External Interrupt Event Output Enable"] + #[inline(always)] + pub fn extinteo(&self) -> EXTINTEO_R { + EXTINTEO_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - External Interrupt Event Output Enable"] + #[inline(always)] + pub fn extinteo(&mut self) -> EXTINTEO_W { + EXTINTEO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/eic/intenclr.rs b/pac/atsamc21e/src/eic/intenclr.rs new file mode 100644 index 000000000000..198c3aac9eb1 --- /dev/null +++ b/pac/atsamc21e/src/eic/intenclr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EXTINT` reader - External Interrupt Disable"] +pub struct EXTINT_R(crate::FieldReader); +impl EXTINT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + EXTINT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT` writer - External Interrupt Disable"] +pub struct EXTINT_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - External Interrupt Disable"] + #[inline(always)] + pub fn extint(&self) -> EXTINT_R { + EXTINT_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - External Interrupt Disable"] + #[inline(always)] + pub fn extint(&mut self) -> EXTINT_W { + EXTINT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/eic/intenset.rs b/pac/atsamc21e/src/eic/intenset.rs new file mode 100644 index 000000000000..e2ff6729d71f --- /dev/null +++ b/pac/atsamc21e/src/eic/intenset.rs @@ -0,0 +1,103 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EXTINT` reader - External Interrupt Enable"] +pub struct EXTINT_R(crate::FieldReader); +impl EXTINT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + EXTINT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT` writer - External Interrupt Enable"] +pub struct EXTINT_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - External Interrupt Enable"] + #[inline(always)] + pub fn extint(&self) -> EXTINT_R { + EXTINT_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - External Interrupt Enable"] + #[inline(always)] + pub fn extint(&mut self) -> EXTINT_W { + EXTINT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/eic/intflag.rs b/pac/atsamc21e/src/eic/intflag.rs new file mode 100644 index 000000000000..df2f15490feb --- /dev/null +++ b/pac/atsamc21e/src/eic/intflag.rs @@ -0,0 +1,103 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EXTINT` reader - External Interrupt Flag"] +pub struct EXTINT_R(crate::FieldReader); +impl EXTINT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + EXTINT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT` writer - External Interrupt Flag"] +pub struct EXTINT_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - External Interrupt Flag"] + #[inline(always)] + pub fn extint(&self) -> EXTINT_R { + EXTINT_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - External Interrupt Flag"] + #[inline(always)] + pub fn extint(&mut self) -> EXTINT_W { + EXTINT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/eic/nmictrl.rs b/pac/atsamc21e/src/eic/nmictrl.rs new file mode 100644 index 000000000000..c9b276ea2a29 --- /dev/null +++ b/pac/atsamc21e/src/eic/nmictrl.rs @@ -0,0 +1,345 @@ +#[doc = "Register `NMICTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `NMICTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "NMI Input Sense Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum NMISENSE_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising-edge detection"] + RISE = 1, + #[doc = "2: Falling-edge detection"] + FALL = 2, + #[doc = "3: Both-edges detection"] + BOTH = 3, + #[doc = "4: High-level detection"] + HIGH = 4, + #[doc = "5: Low-level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: NMISENSE_A) -> Self { + variant as _ + } +} +#[doc = "Field `NMISENSE` reader - NMI Input Sense Configuration"] +pub struct NMISENSE_R(crate::FieldReader); +impl NMISENSE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + NMISENSE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(NMISENSE_A::NONE), + 1 => Some(NMISENSE_A::RISE), + 2 => Some(NMISENSE_A::FALL), + 3 => Some(NMISENSE_A::BOTH), + 4 => Some(NMISENSE_A::HIGH), + 5 => Some(NMISENSE_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == NMISENSE_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == NMISENSE_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == NMISENSE_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == NMISENSE_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == NMISENSE_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == NMISENSE_A::LOW + } +} +impl core::ops::Deref for NMISENSE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NMISENSE` writer - NMI Input Sense Configuration"] +pub struct NMISENSE_W<'a> { + w: &'a mut W, +} +impl<'a> NMISENSE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: NMISENSE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(NMISENSE_A::NONE) + } + #[doc = "Rising-edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(NMISENSE_A::RISE) + } + #[doc = "Falling-edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(NMISENSE_A::FALL) + } + #[doc = "Both-edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(NMISENSE_A::BOTH) + } + #[doc = "High-level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(NMISENSE_A::HIGH) + } + #[doc = "Low-level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(NMISENSE_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +#[doc = "Field `NMIFILTEN` reader - NMI Filter Enable"] +pub struct NMIFILTEN_R(crate::FieldReader); +impl NMIFILTEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NMIFILTEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NMIFILTEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NMIFILTEN` writer - NMI Filter Enable"] +pub struct NMIFILTEN_W<'a> { + w: &'a mut W, +} +impl<'a> NMIFILTEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "NMI Asynchronous edge Detection Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum NMIASYNCH_A { + #[doc = "0: Edge detection is clock synchronously operated"] + SYNC = 0, + #[doc = "1: Edge detection is clock asynchronously operated"] + ASYNC = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NMIASYNCH_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NMIASYNCH` reader - NMI Asynchronous edge Detection Enable"] +pub struct NMIASYNCH_R(crate::FieldReader); +impl NMIASYNCH_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NMIASYNCH_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> NMIASYNCH_A { + match self.bits { + false => NMIASYNCH_A::SYNC, + true => NMIASYNCH_A::ASYNC, + } + } + #[doc = "Checks if the value of the field is `SYNC`"] + #[inline(always)] + pub fn is_sync(&self) -> bool { + **self == NMIASYNCH_A::SYNC + } + #[doc = "Checks if the value of the field is `ASYNC`"] + #[inline(always)] + pub fn is_async(&self) -> bool { + **self == NMIASYNCH_A::ASYNC + } +} +impl core::ops::Deref for NMIASYNCH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NMIASYNCH` writer - NMI Asynchronous edge Detection Enable"] +pub struct NMIASYNCH_W<'a> { + w: &'a mut W, +} +impl<'a> NMIASYNCH_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: NMIASYNCH_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Edge detection is clock synchronously operated"] + #[inline(always)] + pub fn sync(self) -> &'a mut W { + self.variant(NMIASYNCH_A::SYNC) + } + #[doc = "Edge detection is clock asynchronously operated"] + #[inline(always)] + pub fn async_(self) -> &'a mut W { + self.variant(NMIASYNCH_A::ASYNC) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - NMI Input Sense Configuration"] + #[inline(always)] + pub fn nmisense(&self) -> NMISENSE_R { + NMISENSE_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 3 - NMI Filter Enable"] + #[inline(always)] + pub fn nmifilten(&self) -> NMIFILTEN_R { + NMIFILTEN_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - NMI Asynchronous edge Detection Enable"] + #[inline(always)] + pub fn nmiasynch(&self) -> NMIASYNCH_R { + NMIASYNCH_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - NMI Input Sense Configuration"] + #[inline(always)] + pub fn nmisense(&mut self) -> NMISENSE_W { + NMISENSE_W { w: self } + } + #[doc = "Bit 3 - NMI Filter Enable"] + #[inline(always)] + pub fn nmifilten(&mut self) -> NMIFILTEN_W { + NMIFILTEN_W { w: self } + } + #[doc = "Bit 4 - NMI Asynchronous edge Detection Enable"] + #[inline(always)] + pub fn nmiasynch(&mut self) -> NMIASYNCH_W { + NMIASYNCH_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "NMI Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [nmictrl](index.html) module"] +pub struct NMICTRL_SPEC; +impl crate::RegisterSpec for NMICTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [nmictrl::R](R) reader structure"] +impl crate::Readable for NMICTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [nmictrl::W](W) writer structure"] +impl crate::Writable for NMICTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets NMICTRL to value 0"] +impl crate::Resettable for NMICTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/eic/nmiflag.rs b/pac/atsamc21e/src/eic/nmiflag.rs new file mode 100644 index 000000000000..97934b501c12 --- /dev/null +++ b/pac/atsamc21e/src/eic/nmiflag.rs @@ -0,0 +1,113 @@ +#[doc = "Register `NMIFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `NMIFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `NMI` reader - NMI Interrupt Flag"] +pub struct NMI_R(crate::FieldReader); +impl NMI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NMI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NMI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NMI` writer - NMI Interrupt Flag"] +pub struct NMI_W<'a> { + w: &'a mut W, +} +impl<'a> NMI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - NMI Interrupt Flag"] + #[inline(always)] + pub fn nmi(&self) -> NMI_R { + NMI_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - NMI Interrupt Flag"] + #[inline(always)] + pub fn nmi(&mut self) -> NMI_W { + NMI_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "NMI Interrupt Flag\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [nmiflag](index.html) module"] +pub struct NMIFLAG_SPEC; +impl crate::RegisterSpec for NMIFLAG_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [nmiflag::R](R) reader structure"] +impl crate::Readable for NMIFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [nmiflag::W](W) writer structure"] +impl crate::Writable for NMIFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets NMIFLAG to value 0"] +impl crate::Resettable for NMIFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/eic/syncbusy.rs b/pac/atsamc21e/src/eic/syncbusy.rs new file mode 100644 index 000000000000..84d125d0acf1 --- /dev/null +++ b/pac/atsamc21e/src/eic/syncbusy.rs @@ -0,0 +1,73 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software reset synchronisation"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - Enable synchronisation"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software reset synchronisation"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable synchronisation"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +#[doc = "Syncbusy register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/evsys.rs b/pac/atsamc21e/src/evsys.rs new file mode 100644 index 000000000000..9e54201975f7 --- /dev/null +++ b/pac/atsamc21e/src/evsys.rs @@ -0,0 +1,54 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrla: crate::Reg, + _reserved1: [u8; 0x0b], + #[doc = "0x0c - Channel Status"] + pub chstatus: crate::Reg, + #[doc = "0x10 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x14 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x18 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x1c - Software Event"] + pub swevt: crate::Reg, + #[doc = "0x20..0x50 - Channel n"] + pub channel: [crate::Reg; 12], + _reserved7: [u8; 0x30], + #[doc = "0x80..0x13c - User Multiplexer n"] + pub user: [crate::Reg; 47], +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control"] +pub mod ctrla; +#[doc = "CHSTATUS register accessor: an alias for `Reg`"] +pub type CHSTATUS = crate::Reg; +#[doc = "Channel Status"] +pub mod chstatus; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "SWEVT register accessor: an alias for `Reg`"] +pub type SWEVT = crate::Reg; +#[doc = "Software Event"] +pub mod swevt; +#[doc = "CHANNEL register accessor: an alias for `Reg`"] +pub type CHANNEL = crate::Reg; +#[doc = "Channel n"] +pub mod channel; +#[doc = "USER register accessor: an alias for `Reg`"] +pub type USER = crate::Reg; +#[doc = "User Multiplexer n"] +pub mod user; diff --git a/pac/atsamc21e/src/evsys/channel.rs b/pac/atsamc21e/src/evsys/channel.rs new file mode 100644 index 000000000000..20e3857da922 --- /dev/null +++ b/pac/atsamc21e/src/evsys/channel.rs @@ -0,0 +1,409 @@ +#[doc = "Register `CHANNEL[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHANNEL[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVGEN` reader - Event Generator Selection"] +pub struct EVGEN_R(crate::FieldReader); +impl EVGEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVGEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVGEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVGEN` writer - Event Generator Selection"] +pub struct EVGEN_W<'a> { + w: &'a mut W, +} +impl<'a> EVGEN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x7f) | (value as u32 & 0x7f); + self.w + } +} +#[doc = "Path Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PATH_A { + #[doc = "0: Synchronous path"] + SYNCHRONOUS = 0, + #[doc = "1: Resynchronized path"] + RESYNCHRONIZED = 1, + #[doc = "2: Asynchronous path"] + ASYNCHRONOUS = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PATH_A) -> Self { + variant as _ + } +} +#[doc = "Field `PATH` reader - Path Selection"] +pub struct PATH_R(crate::FieldReader); +impl PATH_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PATH_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PATH_A::SYNCHRONOUS), + 1 => Some(PATH_A::RESYNCHRONIZED), + 2 => Some(PATH_A::ASYNCHRONOUS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `SYNCHRONOUS`"] + #[inline(always)] + pub fn is_synchronous(&self) -> bool { + **self == PATH_A::SYNCHRONOUS + } + #[doc = "Checks if the value of the field is `RESYNCHRONIZED`"] + #[inline(always)] + pub fn is_resynchronized(&self) -> bool { + **self == PATH_A::RESYNCHRONIZED + } + #[doc = "Checks if the value of the field is `ASYNCHRONOUS`"] + #[inline(always)] + pub fn is_asynchronous(&self) -> bool { + **self == PATH_A::ASYNCHRONOUS + } +} +impl core::ops::Deref for PATH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PATH` writer - Path Selection"] +pub struct PATH_W<'a> { + w: &'a mut W, +} +impl<'a> PATH_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PATH_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Synchronous path"] + #[inline(always)] + pub fn synchronous(self) -> &'a mut W { + self.variant(PATH_A::SYNCHRONOUS) + } + #[doc = "Resynchronized path"] + #[inline(always)] + pub fn resynchronized(self) -> &'a mut W { + self.variant(PATH_A::RESYNCHRONIZED) + } + #[doc = "Asynchronous path"] + #[inline(always)] + pub fn asynchronous(self) -> &'a mut W { + self.variant(PATH_A::ASYNCHRONOUS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 8)) | ((value as u32 & 0x03) << 8); + self.w + } +} +#[doc = "Edge Detection Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EDGSEL_A { + #[doc = "0: No event output when using the resynchronized or synchronous path"] + NO_EVT_OUTPUT = 0, + #[doc = "1: Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path"] + RISING_EDGE = 1, + #[doc = "2: Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path"] + FALLING_EDGE = 2, + #[doc = "3: Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path"] + BOTH_EDGES = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EDGSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `EDGSEL` reader - Edge Detection Selection"] +pub struct EDGSEL_R(crate::FieldReader); +impl EDGSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EDGSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EDGSEL_A { + match self.bits { + 0 => EDGSEL_A::NO_EVT_OUTPUT, + 1 => EDGSEL_A::RISING_EDGE, + 2 => EDGSEL_A::FALLING_EDGE, + 3 => EDGSEL_A::BOTH_EDGES, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NO_EVT_OUTPUT`"] + #[inline(always)] + pub fn is_no_evt_output(&self) -> bool { + **self == EDGSEL_A::NO_EVT_OUTPUT + } + #[doc = "Checks if the value of the field is `RISING_EDGE`"] + #[inline(always)] + pub fn is_rising_edge(&self) -> bool { + **self == EDGSEL_A::RISING_EDGE + } + #[doc = "Checks if the value of the field is `FALLING_EDGE`"] + #[inline(always)] + pub fn is_falling_edge(&self) -> bool { + **self == EDGSEL_A::FALLING_EDGE + } + #[doc = "Checks if the value of the field is `BOTH_EDGES`"] + #[inline(always)] + pub fn is_both_edges(&self) -> bool { + **self == EDGSEL_A::BOTH_EDGES + } +} +impl core::ops::Deref for EDGSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EDGSEL` writer - Edge Detection Selection"] +pub struct EDGSEL_W<'a> { + w: &'a mut W, +} +impl<'a> EDGSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EDGSEL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "No event output when using the resynchronized or synchronous path"] + #[inline(always)] + pub fn no_evt_output(self) -> &'a mut W { + self.variant(EDGSEL_A::NO_EVT_OUTPUT) + } + #[doc = "Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path"] + #[inline(always)] + pub fn rising_edge(self) -> &'a mut W { + self.variant(EDGSEL_A::RISING_EDGE) + } + #[doc = "Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path"] + #[inline(always)] + pub fn falling_edge(self) -> &'a mut W { + self.variant(EDGSEL_A::FALLING_EDGE) + } + #[doc = "Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path"] + #[inline(always)] + pub fn both_edges(self) -> &'a mut W { + self.variant(EDGSEL_A::BOTH_EDGES) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 10)) | ((value as u32 & 0x03) << 10); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - Generic Clock On Demand"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - Generic Clock On Demand"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bits 0:6 - Event Generator Selection"] + #[inline(always)] + pub fn evgen(&self) -> EVGEN_R { + EVGEN_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bits 8:9 - Path Selection"] + #[inline(always)] + pub fn path(&self) -> PATH_R { + PATH_R::new(((self.bits >> 8) & 0x03) as u8) + } + #[doc = "Bits 10:11 - Edge Detection Selection"] + #[inline(always)] + pub fn edgsel(&self) -> EDGSEL_R { + EDGSEL_R::new(((self.bits >> 10) & 0x03) as u8) + } + #[doc = "Bit 14 - Run in standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Generic Clock On Demand"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:6 - Event Generator Selection"] + #[inline(always)] + pub fn evgen(&mut self) -> EVGEN_W { + EVGEN_W { w: self } + } + #[doc = "Bits 8:9 - Path Selection"] + #[inline(always)] + pub fn path(&mut self) -> PATH_W { + PATH_W { w: self } + } + #[doc = "Bits 10:11 - Edge Detection Selection"] + #[inline(always)] + pub fn edgsel(&mut self) -> EDGSEL_W { + EDGSEL_W { w: self } + } + #[doc = "Bit 14 - Run in standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 15 - Generic Clock On Demand"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [channel](index.html) module"] +pub struct CHANNEL_SPEC; +impl crate::RegisterSpec for CHANNEL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [channel::R](R) reader structure"] +impl crate::Readable for CHANNEL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [channel::W](W) writer structure"] +impl crate::Writable for CHANNEL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHANNEL[%s] +to value 0x8000"] +impl crate::Resettable for CHANNEL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x8000 + } +} diff --git a/pac/atsamc21e/src/evsys/chstatus.rs b/pac/atsamc21e/src/evsys/chstatus.rs new file mode 100644 index 000000000000..811089dfdeb8 --- /dev/null +++ b/pac/atsamc21e/src/evsys/chstatus.rs @@ -0,0 +1,513 @@ +#[doc = "Register `CHSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `USRRDY0` reader - Channel 0 User Ready"] +pub struct USRRDY0_R(crate::FieldReader); +impl USRRDY0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY1` reader - Channel 1 User Ready"] +pub struct USRRDY1_R(crate::FieldReader); +impl USRRDY1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY2` reader - Channel 2 User Ready"] +pub struct USRRDY2_R(crate::FieldReader); +impl USRRDY2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY3` reader - Channel 3 User Ready"] +pub struct USRRDY3_R(crate::FieldReader); +impl USRRDY3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY4` reader - Channel 4 User Ready"] +pub struct USRRDY4_R(crate::FieldReader); +impl USRRDY4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY5` reader - Channel 5 User Ready"] +pub struct USRRDY5_R(crate::FieldReader); +impl USRRDY5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY6` reader - Channel 6 User Ready"] +pub struct USRRDY6_R(crate::FieldReader); +impl USRRDY6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY7` reader - Channel 7 User Ready"] +pub struct USRRDY7_R(crate::FieldReader); +impl USRRDY7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY8` reader - Channel 8 User Ready"] +pub struct USRRDY8_R(crate::FieldReader); +impl USRRDY8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY9` reader - Channel 9 User Ready"] +pub struct USRRDY9_R(crate::FieldReader); +impl USRRDY9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY10` reader - Channel 10 User Ready"] +pub struct USRRDY10_R(crate::FieldReader); +impl USRRDY10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY11` reader - Channel 11 User Ready"] +pub struct USRRDY11_R(crate::FieldReader); +impl USRRDY11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY0` reader - Channel 0 Busy"] +pub struct CHBUSY0_R(crate::FieldReader); +impl CHBUSY0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY1` reader - Channel 1 Busy"] +pub struct CHBUSY1_R(crate::FieldReader); +impl CHBUSY1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY2` reader - Channel 2 Busy"] +pub struct CHBUSY2_R(crate::FieldReader); +impl CHBUSY2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY3` reader - Channel 3 Busy"] +pub struct CHBUSY3_R(crate::FieldReader); +impl CHBUSY3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY4` reader - Channel 4 Busy"] +pub struct CHBUSY4_R(crate::FieldReader); +impl CHBUSY4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY5` reader - Channel 5 Busy"] +pub struct CHBUSY5_R(crate::FieldReader); +impl CHBUSY5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY6` reader - Channel 6 Busy"] +pub struct CHBUSY6_R(crate::FieldReader); +impl CHBUSY6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY7` reader - Channel 7 Busy"] +pub struct CHBUSY7_R(crate::FieldReader); +impl CHBUSY7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY8` reader - Channel 8 Busy"] +pub struct CHBUSY8_R(crate::FieldReader); +impl CHBUSY8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY9` reader - Channel 9 Busy"] +pub struct CHBUSY9_R(crate::FieldReader); +impl CHBUSY9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY10` reader - Channel 10 Busy"] +pub struct CHBUSY10_R(crate::FieldReader); +impl CHBUSY10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY11` reader - Channel 11 Busy"] +pub struct CHBUSY11_R(crate::FieldReader); +impl CHBUSY11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Channel 0 User Ready"] + #[inline(always)] + pub fn usrrdy0(&self) -> USRRDY0_R { + USRRDY0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel 1 User Ready"] + #[inline(always)] + pub fn usrrdy1(&self) -> USRRDY1_R { + USRRDY1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel 2 User Ready"] + #[inline(always)] + pub fn usrrdy2(&self) -> USRRDY2_R { + USRRDY2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Channel 3 User Ready"] + #[inline(always)] + pub fn usrrdy3(&self) -> USRRDY3_R { + USRRDY3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Channel 4 User Ready"] + #[inline(always)] + pub fn usrrdy4(&self) -> USRRDY4_R { + USRRDY4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Channel 5 User Ready"] + #[inline(always)] + pub fn usrrdy5(&self) -> USRRDY5_R { + USRRDY5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Channel 6 User Ready"] + #[inline(always)] + pub fn usrrdy6(&self) -> USRRDY6_R { + USRRDY6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Channel 7 User Ready"] + #[inline(always)] + pub fn usrrdy7(&self) -> USRRDY7_R { + USRRDY7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Channel 8 User Ready"] + #[inline(always)] + pub fn usrrdy8(&self) -> USRRDY8_R { + USRRDY8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Channel 9 User Ready"] + #[inline(always)] + pub fn usrrdy9(&self) -> USRRDY9_R { + USRRDY9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Channel 10 User Ready"] + #[inline(always)] + pub fn usrrdy10(&self) -> USRRDY10_R { + USRRDY10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Channel 11 User Ready"] + #[inline(always)] + pub fn usrrdy11(&self) -> USRRDY11_R { + USRRDY11_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 16 - Channel 0 Busy"] + #[inline(always)] + pub fn chbusy0(&self) -> CHBUSY0_R { + CHBUSY0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Channel 1 Busy"] + #[inline(always)] + pub fn chbusy1(&self) -> CHBUSY1_R { + CHBUSY1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Channel 2 Busy"] + #[inline(always)] + pub fn chbusy2(&self) -> CHBUSY2_R { + CHBUSY2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Channel 3 Busy"] + #[inline(always)] + pub fn chbusy3(&self) -> CHBUSY3_R { + CHBUSY3_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Channel 4 Busy"] + #[inline(always)] + pub fn chbusy4(&self) -> CHBUSY4_R { + CHBUSY4_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Channel 5 Busy"] + #[inline(always)] + pub fn chbusy5(&self) -> CHBUSY5_R { + CHBUSY5_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Channel 6 Busy"] + #[inline(always)] + pub fn chbusy6(&self) -> CHBUSY6_R { + CHBUSY6_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Channel 7 Busy"] + #[inline(always)] + pub fn chbusy7(&self) -> CHBUSY7_R { + CHBUSY7_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24 - Channel 8 Busy"] + #[inline(always)] + pub fn chbusy8(&self) -> CHBUSY8_R { + CHBUSY8_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Channel 9 Busy"] + #[inline(always)] + pub fn chbusy9(&self) -> CHBUSY9_R { + CHBUSY9_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Channel 10 Busy"] + #[inline(always)] + pub fn chbusy10(&self) -> CHBUSY10_R { + CHBUSY10_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Channel 11 Busy"] + #[inline(always)] + pub fn chbusy11(&self) -> CHBUSY11_R { + CHBUSY11_R::new(((self.bits >> 27) & 0x01) != 0) + } +} +#[doc = "Channel Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chstatus](index.html) module"] +pub struct CHSTATUS_SPEC; +impl crate::RegisterSpec for CHSTATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [chstatus::R](R) reader structure"] +impl crate::Readable for CHSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CHSTATUS to value 0"] +impl crate::Resettable for CHSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/evsys/ctrla.rs b/pac/atsamc21e/src/evsys/ctrla.rs new file mode 100644 index 000000000000..1c24704395ad --- /dev/null +++ b/pac/atsamc21e/src/evsys/ctrla.rs @@ -0,0 +1,113 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/evsys/intenclr.rs b/pac/atsamc21e/src/evsys/intenclr.rs new file mode 100644 index 000000000000..6a6a0b2b94c5 --- /dev/null +++ b/pac/atsamc21e/src/evsys/intenclr.rs @@ -0,0 +1,1194 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVR0` reader - Channel 0 Overrun Interrupt Enable"] +pub struct OVR0_R(crate::FieldReader); +impl OVR0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR0` writer - Channel 0 Overrun Interrupt Enable"] +pub struct OVR0_W<'a> { + w: &'a mut W, +} +impl<'a> OVR0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `OVR1` reader - Channel 1 Overrun Interrupt Enable"] +pub struct OVR1_R(crate::FieldReader); +impl OVR1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR1` writer - Channel 1 Overrun Interrupt Enable"] +pub struct OVR1_W<'a> { + w: &'a mut W, +} +impl<'a> OVR1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `OVR2` reader - Channel 2 Overrun Interrupt Enable"] +pub struct OVR2_R(crate::FieldReader); +impl OVR2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR2` writer - Channel 2 Overrun Interrupt Enable"] +pub struct OVR2_W<'a> { + w: &'a mut W, +} +impl<'a> OVR2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `OVR3` reader - Channel 3 Overrun Interrupt Enable"] +pub struct OVR3_R(crate::FieldReader); +impl OVR3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR3` writer - Channel 3 Overrun Interrupt Enable"] +pub struct OVR3_W<'a> { + w: &'a mut W, +} +impl<'a> OVR3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `OVR4` reader - Channel 4 Overrun Interrupt Enable"] +pub struct OVR4_R(crate::FieldReader); +impl OVR4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR4` writer - Channel 4 Overrun Interrupt Enable"] +pub struct OVR4_W<'a> { + w: &'a mut W, +} +impl<'a> OVR4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `OVR5` reader - Channel 5 Overrun Interrupt Enable"] +pub struct OVR5_R(crate::FieldReader); +impl OVR5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR5` writer - Channel 5 Overrun Interrupt Enable"] +pub struct OVR5_W<'a> { + w: &'a mut W, +} +impl<'a> OVR5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `OVR6` reader - Channel 6 Overrun Interrupt Enable"] +pub struct OVR6_R(crate::FieldReader); +impl OVR6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR6` writer - Channel 6 Overrun Interrupt Enable"] +pub struct OVR6_W<'a> { + w: &'a mut W, +} +impl<'a> OVR6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `OVR7` reader - Channel 7 Overrun Interrupt Enable"] +pub struct OVR7_R(crate::FieldReader); +impl OVR7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR7` writer - Channel 7 Overrun Interrupt Enable"] +pub struct OVR7_W<'a> { + w: &'a mut W, +} +impl<'a> OVR7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `OVR8` reader - Channel 8 Overrun Interrupt Enable"] +pub struct OVR8_R(crate::FieldReader); +impl OVR8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR8` writer - Channel 8 Overrun Interrupt Enable"] +pub struct OVR8_W<'a> { + w: &'a mut W, +} +impl<'a> OVR8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `OVR9` reader - Channel 9 Overrun Interrupt Enable"] +pub struct OVR9_R(crate::FieldReader); +impl OVR9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR9` writer - Channel 9 Overrun Interrupt Enable"] +pub struct OVR9_W<'a> { + w: &'a mut W, +} +impl<'a> OVR9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `OVR10` reader - Channel 10 Overrun Interrupt Enable"] +pub struct OVR10_R(crate::FieldReader); +impl OVR10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR10` writer - Channel 10 Overrun Interrupt Enable"] +pub struct OVR10_W<'a> { + w: &'a mut W, +} +impl<'a> OVR10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `OVR11` reader - Channel 11 Overrun Interrupt Enable"] +pub struct OVR11_R(crate::FieldReader); +impl OVR11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR11` writer - Channel 11 Overrun Interrupt Enable"] +pub struct OVR11_W<'a> { + w: &'a mut W, +} +impl<'a> OVR11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `EVD0` reader - Channel 0 Event Detection Interrupt Enable"] +pub struct EVD0_R(crate::FieldReader); +impl EVD0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD0` writer - Channel 0 Event Detection Interrupt Enable"] +pub struct EVD0_W<'a> { + w: &'a mut W, +} +impl<'a> EVD0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `EVD1` reader - Channel 1 Event Detection Interrupt Enable"] +pub struct EVD1_R(crate::FieldReader); +impl EVD1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD1` writer - Channel 1 Event Detection Interrupt Enable"] +pub struct EVD1_W<'a> { + w: &'a mut W, +} +impl<'a> EVD1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `EVD2` reader - Channel 2 Event Detection Interrupt Enable"] +pub struct EVD2_R(crate::FieldReader); +impl EVD2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD2` writer - Channel 2 Event Detection Interrupt Enable"] +pub struct EVD2_W<'a> { + w: &'a mut W, +} +impl<'a> EVD2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `EVD3` reader - Channel 3 Event Detection Interrupt Enable"] +pub struct EVD3_R(crate::FieldReader); +impl EVD3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD3` writer - Channel 3 Event Detection Interrupt Enable"] +pub struct EVD3_W<'a> { + w: &'a mut W, +} +impl<'a> EVD3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `EVD4` reader - Channel 4 Event Detection Interrupt Enable"] +pub struct EVD4_R(crate::FieldReader); +impl EVD4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD4` writer - Channel 4 Event Detection Interrupt Enable"] +pub struct EVD4_W<'a> { + w: &'a mut W, +} +impl<'a> EVD4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `EVD5` reader - Channel 5 Event Detection Interrupt Enable"] +pub struct EVD5_R(crate::FieldReader); +impl EVD5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD5` writer - Channel 5 Event Detection Interrupt Enable"] +pub struct EVD5_W<'a> { + w: &'a mut W, +} +impl<'a> EVD5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `EVD6` reader - Channel 6 Event Detection Interrupt Enable"] +pub struct EVD6_R(crate::FieldReader); +impl EVD6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD6` writer - Channel 6 Event Detection Interrupt Enable"] +pub struct EVD6_W<'a> { + w: &'a mut W, +} +impl<'a> EVD6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `EVD7` reader - Channel 7 Event Detection Interrupt Enable"] +pub struct EVD7_R(crate::FieldReader); +impl EVD7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD7` writer - Channel 7 Event Detection Interrupt Enable"] +pub struct EVD7_W<'a> { + w: &'a mut W, +} +impl<'a> EVD7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `EVD8` reader - Channel 8 Event Detection Interrupt Enable"] +pub struct EVD8_R(crate::FieldReader); +impl EVD8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD8` writer - Channel 8 Event Detection Interrupt Enable"] +pub struct EVD8_W<'a> { + w: &'a mut W, +} +impl<'a> EVD8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `EVD9` reader - Channel 9 Event Detection Interrupt Enable"] +pub struct EVD9_R(crate::FieldReader); +impl EVD9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD9` writer - Channel 9 Event Detection Interrupt Enable"] +pub struct EVD9_W<'a> { + w: &'a mut W, +} +impl<'a> EVD9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `EVD10` reader - Channel 10 Event Detection Interrupt Enable"] +pub struct EVD10_R(crate::FieldReader); +impl EVD10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD10` writer - Channel 10 Event Detection Interrupt Enable"] +pub struct EVD10_W<'a> { + w: &'a mut W, +} +impl<'a> EVD10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `EVD11` reader - Channel 11 Event Detection Interrupt Enable"] +pub struct EVD11_R(crate::FieldReader); +impl EVD11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD11` writer - Channel 11 Event Detection Interrupt Enable"] +pub struct EVD11_W<'a> { + w: &'a mut W, +} +impl<'a> EVD11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +impl R { + #[doc = "Bit 0 - Channel 0 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr0(&self) -> OVR0_R { + OVR0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel 1 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr1(&self) -> OVR1_R { + OVR1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel 2 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr2(&self) -> OVR2_R { + OVR2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Channel 3 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr3(&self) -> OVR3_R { + OVR3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Channel 4 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr4(&self) -> OVR4_R { + OVR4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Channel 5 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr5(&self) -> OVR5_R { + OVR5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Channel 6 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr6(&self) -> OVR6_R { + OVR6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Channel 7 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr7(&self) -> OVR7_R { + OVR7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Channel 8 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr8(&self) -> OVR8_R { + OVR8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Channel 9 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr9(&self) -> OVR9_R { + OVR9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Channel 10 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr10(&self) -> OVR10_R { + OVR10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Channel 11 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr11(&self) -> OVR11_R { + OVR11_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 16 - Channel 0 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd0(&self) -> EVD0_R { + EVD0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Channel 1 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd1(&self) -> EVD1_R { + EVD1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Channel 2 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd2(&self) -> EVD2_R { + EVD2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Channel 3 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd3(&self) -> EVD3_R { + EVD3_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Channel 4 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd4(&self) -> EVD4_R { + EVD4_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Channel 5 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd5(&self) -> EVD5_R { + EVD5_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Channel 6 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd6(&self) -> EVD6_R { + EVD6_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Channel 7 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd7(&self) -> EVD7_R { + EVD7_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24 - Channel 8 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd8(&self) -> EVD8_R { + EVD8_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Channel 9 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd9(&self) -> EVD9_R { + EVD9_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Channel 10 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd10(&self) -> EVD10_R { + EVD10_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Channel 11 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd11(&self) -> EVD11_R { + EVD11_R::new(((self.bits >> 27) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel 0 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr0(&mut self) -> OVR0_W { + OVR0_W { w: self } + } + #[doc = "Bit 1 - Channel 1 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr1(&mut self) -> OVR1_W { + OVR1_W { w: self } + } + #[doc = "Bit 2 - Channel 2 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr2(&mut self) -> OVR2_W { + OVR2_W { w: self } + } + #[doc = "Bit 3 - Channel 3 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr3(&mut self) -> OVR3_W { + OVR3_W { w: self } + } + #[doc = "Bit 4 - Channel 4 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr4(&mut self) -> OVR4_W { + OVR4_W { w: self } + } + #[doc = "Bit 5 - Channel 5 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr5(&mut self) -> OVR5_W { + OVR5_W { w: self } + } + #[doc = "Bit 6 - Channel 6 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr6(&mut self) -> OVR6_W { + OVR6_W { w: self } + } + #[doc = "Bit 7 - Channel 7 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr7(&mut self) -> OVR7_W { + OVR7_W { w: self } + } + #[doc = "Bit 8 - Channel 8 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr8(&mut self) -> OVR8_W { + OVR8_W { w: self } + } + #[doc = "Bit 9 - Channel 9 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr9(&mut self) -> OVR9_W { + OVR9_W { w: self } + } + #[doc = "Bit 10 - Channel 10 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr10(&mut self) -> OVR10_W { + OVR10_W { w: self } + } + #[doc = "Bit 11 - Channel 11 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr11(&mut self) -> OVR11_W { + OVR11_W { w: self } + } + #[doc = "Bit 16 - Channel 0 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd0(&mut self) -> EVD0_W { + EVD0_W { w: self } + } + #[doc = "Bit 17 - Channel 1 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd1(&mut self) -> EVD1_W { + EVD1_W { w: self } + } + #[doc = "Bit 18 - Channel 2 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd2(&mut self) -> EVD2_W { + EVD2_W { w: self } + } + #[doc = "Bit 19 - Channel 3 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd3(&mut self) -> EVD3_W { + EVD3_W { w: self } + } + #[doc = "Bit 20 - Channel 4 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd4(&mut self) -> EVD4_W { + EVD4_W { w: self } + } + #[doc = "Bit 21 - Channel 5 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd5(&mut self) -> EVD5_W { + EVD5_W { w: self } + } + #[doc = "Bit 22 - Channel 6 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd6(&mut self) -> EVD6_W { + EVD6_W { w: self } + } + #[doc = "Bit 23 - Channel 7 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd7(&mut self) -> EVD7_W { + EVD7_W { w: self } + } + #[doc = "Bit 24 - Channel 8 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd8(&mut self) -> EVD8_W { + EVD8_W { w: self } + } + #[doc = "Bit 25 - Channel 9 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd9(&mut self) -> EVD9_W { + EVD9_W { w: self } + } + #[doc = "Bit 26 - Channel 10 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd10(&mut self) -> EVD10_W { + EVD10_W { w: self } + } + #[doc = "Bit 27 - Channel 11 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd11(&mut self) -> EVD11_W { + EVD11_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/evsys/intenset.rs b/pac/atsamc21e/src/evsys/intenset.rs new file mode 100644 index 000000000000..d84061297909 --- /dev/null +++ b/pac/atsamc21e/src/evsys/intenset.rs @@ -0,0 +1,1194 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVR0` reader - Channel 0 Overrun Interrupt Enable"] +pub struct OVR0_R(crate::FieldReader); +impl OVR0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR0` writer - Channel 0 Overrun Interrupt Enable"] +pub struct OVR0_W<'a> { + w: &'a mut W, +} +impl<'a> OVR0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `OVR1` reader - Channel 1 Overrun Interrupt Enable"] +pub struct OVR1_R(crate::FieldReader); +impl OVR1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR1` writer - Channel 1 Overrun Interrupt Enable"] +pub struct OVR1_W<'a> { + w: &'a mut W, +} +impl<'a> OVR1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `OVR2` reader - Channel 2 Overrun Interrupt Enable"] +pub struct OVR2_R(crate::FieldReader); +impl OVR2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR2` writer - Channel 2 Overrun Interrupt Enable"] +pub struct OVR2_W<'a> { + w: &'a mut W, +} +impl<'a> OVR2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `OVR3` reader - Channel 3 Overrun Interrupt Enable"] +pub struct OVR3_R(crate::FieldReader); +impl OVR3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR3` writer - Channel 3 Overrun Interrupt Enable"] +pub struct OVR3_W<'a> { + w: &'a mut W, +} +impl<'a> OVR3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `OVR4` reader - Channel 4 Overrun Interrupt Enable"] +pub struct OVR4_R(crate::FieldReader); +impl OVR4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR4` writer - Channel 4 Overrun Interrupt Enable"] +pub struct OVR4_W<'a> { + w: &'a mut W, +} +impl<'a> OVR4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `OVR5` reader - Channel 5 Overrun Interrupt Enable"] +pub struct OVR5_R(crate::FieldReader); +impl OVR5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR5` writer - Channel 5 Overrun Interrupt Enable"] +pub struct OVR5_W<'a> { + w: &'a mut W, +} +impl<'a> OVR5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `OVR6` reader - Channel 6 Overrun Interrupt Enable"] +pub struct OVR6_R(crate::FieldReader); +impl OVR6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR6` writer - Channel 6 Overrun Interrupt Enable"] +pub struct OVR6_W<'a> { + w: &'a mut W, +} +impl<'a> OVR6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `OVR7` reader - Channel 7 Overrun Interrupt Enable"] +pub struct OVR7_R(crate::FieldReader); +impl OVR7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR7` writer - Channel 7 Overrun Interrupt Enable"] +pub struct OVR7_W<'a> { + w: &'a mut W, +} +impl<'a> OVR7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `OVR8` reader - Channel 8 Overrun Interrupt Enable"] +pub struct OVR8_R(crate::FieldReader); +impl OVR8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR8` writer - Channel 8 Overrun Interrupt Enable"] +pub struct OVR8_W<'a> { + w: &'a mut W, +} +impl<'a> OVR8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `OVR9` reader - Channel 9 Overrun Interrupt Enable"] +pub struct OVR9_R(crate::FieldReader); +impl OVR9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR9` writer - Channel 9 Overrun Interrupt Enable"] +pub struct OVR9_W<'a> { + w: &'a mut W, +} +impl<'a> OVR9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `OVR10` reader - Channel 10 Overrun Interrupt Enable"] +pub struct OVR10_R(crate::FieldReader); +impl OVR10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR10` writer - Channel 10 Overrun Interrupt Enable"] +pub struct OVR10_W<'a> { + w: &'a mut W, +} +impl<'a> OVR10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `OVR11` reader - Channel 11 Overrun Interrupt Enable"] +pub struct OVR11_R(crate::FieldReader); +impl OVR11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR11` writer - Channel 11 Overrun Interrupt Enable"] +pub struct OVR11_W<'a> { + w: &'a mut W, +} +impl<'a> OVR11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `EVD0` reader - Channel 0 Event Detection Interrupt Enable"] +pub struct EVD0_R(crate::FieldReader); +impl EVD0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD0` writer - Channel 0 Event Detection Interrupt Enable"] +pub struct EVD0_W<'a> { + w: &'a mut W, +} +impl<'a> EVD0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `EVD1` reader - Channel 1 Event Detection Interrupt Enable"] +pub struct EVD1_R(crate::FieldReader); +impl EVD1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD1` writer - Channel 1 Event Detection Interrupt Enable"] +pub struct EVD1_W<'a> { + w: &'a mut W, +} +impl<'a> EVD1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `EVD2` reader - Channel 2 Event Detection Interrupt Enable"] +pub struct EVD2_R(crate::FieldReader); +impl EVD2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD2` writer - Channel 2 Event Detection Interrupt Enable"] +pub struct EVD2_W<'a> { + w: &'a mut W, +} +impl<'a> EVD2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `EVD3` reader - Channel 3 Event Detection Interrupt Enable"] +pub struct EVD3_R(crate::FieldReader); +impl EVD3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD3` writer - Channel 3 Event Detection Interrupt Enable"] +pub struct EVD3_W<'a> { + w: &'a mut W, +} +impl<'a> EVD3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `EVD4` reader - Channel 4 Event Detection Interrupt Enable"] +pub struct EVD4_R(crate::FieldReader); +impl EVD4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD4` writer - Channel 4 Event Detection Interrupt Enable"] +pub struct EVD4_W<'a> { + w: &'a mut W, +} +impl<'a> EVD4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `EVD5` reader - Channel 5 Event Detection Interrupt Enable"] +pub struct EVD5_R(crate::FieldReader); +impl EVD5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD5` writer - Channel 5 Event Detection Interrupt Enable"] +pub struct EVD5_W<'a> { + w: &'a mut W, +} +impl<'a> EVD5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `EVD6` reader - Channel 6 Event Detection Interrupt Enable"] +pub struct EVD6_R(crate::FieldReader); +impl EVD6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD6` writer - Channel 6 Event Detection Interrupt Enable"] +pub struct EVD6_W<'a> { + w: &'a mut W, +} +impl<'a> EVD6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `EVD7` reader - Channel 7 Event Detection Interrupt Enable"] +pub struct EVD7_R(crate::FieldReader); +impl EVD7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD7` writer - Channel 7 Event Detection Interrupt Enable"] +pub struct EVD7_W<'a> { + w: &'a mut W, +} +impl<'a> EVD7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `EVD8` reader - Channel 8 Event Detection Interrupt Enable"] +pub struct EVD8_R(crate::FieldReader); +impl EVD8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD8` writer - Channel 8 Event Detection Interrupt Enable"] +pub struct EVD8_W<'a> { + w: &'a mut W, +} +impl<'a> EVD8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `EVD9` reader - Channel 9 Event Detection Interrupt Enable"] +pub struct EVD9_R(crate::FieldReader); +impl EVD9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD9` writer - Channel 9 Event Detection Interrupt Enable"] +pub struct EVD9_W<'a> { + w: &'a mut W, +} +impl<'a> EVD9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `EVD10` reader - Channel 10 Event Detection Interrupt Enable"] +pub struct EVD10_R(crate::FieldReader); +impl EVD10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD10` writer - Channel 10 Event Detection Interrupt Enable"] +pub struct EVD10_W<'a> { + w: &'a mut W, +} +impl<'a> EVD10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `EVD11` reader - Channel 11 Event Detection Interrupt Enable"] +pub struct EVD11_R(crate::FieldReader); +impl EVD11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD11` writer - Channel 11 Event Detection Interrupt Enable"] +pub struct EVD11_W<'a> { + w: &'a mut W, +} +impl<'a> EVD11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +impl R { + #[doc = "Bit 0 - Channel 0 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr0(&self) -> OVR0_R { + OVR0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel 1 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr1(&self) -> OVR1_R { + OVR1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel 2 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr2(&self) -> OVR2_R { + OVR2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Channel 3 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr3(&self) -> OVR3_R { + OVR3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Channel 4 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr4(&self) -> OVR4_R { + OVR4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Channel 5 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr5(&self) -> OVR5_R { + OVR5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Channel 6 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr6(&self) -> OVR6_R { + OVR6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Channel 7 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr7(&self) -> OVR7_R { + OVR7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Channel 8 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr8(&self) -> OVR8_R { + OVR8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Channel 9 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr9(&self) -> OVR9_R { + OVR9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Channel 10 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr10(&self) -> OVR10_R { + OVR10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Channel 11 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr11(&self) -> OVR11_R { + OVR11_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 16 - Channel 0 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd0(&self) -> EVD0_R { + EVD0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Channel 1 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd1(&self) -> EVD1_R { + EVD1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Channel 2 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd2(&self) -> EVD2_R { + EVD2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Channel 3 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd3(&self) -> EVD3_R { + EVD3_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Channel 4 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd4(&self) -> EVD4_R { + EVD4_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Channel 5 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd5(&self) -> EVD5_R { + EVD5_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Channel 6 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd6(&self) -> EVD6_R { + EVD6_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Channel 7 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd7(&self) -> EVD7_R { + EVD7_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24 - Channel 8 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd8(&self) -> EVD8_R { + EVD8_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Channel 9 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd9(&self) -> EVD9_R { + EVD9_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Channel 10 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd10(&self) -> EVD10_R { + EVD10_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Channel 11 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd11(&self) -> EVD11_R { + EVD11_R::new(((self.bits >> 27) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel 0 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr0(&mut self) -> OVR0_W { + OVR0_W { w: self } + } + #[doc = "Bit 1 - Channel 1 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr1(&mut self) -> OVR1_W { + OVR1_W { w: self } + } + #[doc = "Bit 2 - Channel 2 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr2(&mut self) -> OVR2_W { + OVR2_W { w: self } + } + #[doc = "Bit 3 - Channel 3 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr3(&mut self) -> OVR3_W { + OVR3_W { w: self } + } + #[doc = "Bit 4 - Channel 4 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr4(&mut self) -> OVR4_W { + OVR4_W { w: self } + } + #[doc = "Bit 5 - Channel 5 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr5(&mut self) -> OVR5_W { + OVR5_W { w: self } + } + #[doc = "Bit 6 - Channel 6 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr6(&mut self) -> OVR6_W { + OVR6_W { w: self } + } + #[doc = "Bit 7 - Channel 7 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr7(&mut self) -> OVR7_W { + OVR7_W { w: self } + } + #[doc = "Bit 8 - Channel 8 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr8(&mut self) -> OVR8_W { + OVR8_W { w: self } + } + #[doc = "Bit 9 - Channel 9 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr9(&mut self) -> OVR9_W { + OVR9_W { w: self } + } + #[doc = "Bit 10 - Channel 10 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr10(&mut self) -> OVR10_W { + OVR10_W { w: self } + } + #[doc = "Bit 11 - Channel 11 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr11(&mut self) -> OVR11_W { + OVR11_W { w: self } + } + #[doc = "Bit 16 - Channel 0 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd0(&mut self) -> EVD0_W { + EVD0_W { w: self } + } + #[doc = "Bit 17 - Channel 1 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd1(&mut self) -> EVD1_W { + EVD1_W { w: self } + } + #[doc = "Bit 18 - Channel 2 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd2(&mut self) -> EVD2_W { + EVD2_W { w: self } + } + #[doc = "Bit 19 - Channel 3 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd3(&mut self) -> EVD3_W { + EVD3_W { w: self } + } + #[doc = "Bit 20 - Channel 4 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd4(&mut self) -> EVD4_W { + EVD4_W { w: self } + } + #[doc = "Bit 21 - Channel 5 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd5(&mut self) -> EVD5_W { + EVD5_W { w: self } + } + #[doc = "Bit 22 - Channel 6 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd6(&mut self) -> EVD6_W { + EVD6_W { w: self } + } + #[doc = "Bit 23 - Channel 7 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd7(&mut self) -> EVD7_W { + EVD7_W { w: self } + } + #[doc = "Bit 24 - Channel 8 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd8(&mut self) -> EVD8_W { + EVD8_W { w: self } + } + #[doc = "Bit 25 - Channel 9 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd9(&mut self) -> EVD9_W { + EVD9_W { w: self } + } + #[doc = "Bit 26 - Channel 10 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd10(&mut self) -> EVD10_W { + EVD10_W { w: self } + } + #[doc = "Bit 27 - Channel 11 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd11(&mut self) -> EVD11_W { + EVD11_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/evsys/intflag.rs b/pac/atsamc21e/src/evsys/intflag.rs new file mode 100644 index 000000000000..4d5cbe3950f6 --- /dev/null +++ b/pac/atsamc21e/src/evsys/intflag.rs @@ -0,0 +1,1194 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVR0` reader - Channel 0 Overrun"] +pub struct OVR0_R(crate::FieldReader); +impl OVR0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR0` writer - Channel 0 Overrun"] +pub struct OVR0_W<'a> { + w: &'a mut W, +} +impl<'a> OVR0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `OVR1` reader - Channel 1 Overrun"] +pub struct OVR1_R(crate::FieldReader); +impl OVR1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR1` writer - Channel 1 Overrun"] +pub struct OVR1_W<'a> { + w: &'a mut W, +} +impl<'a> OVR1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `OVR2` reader - Channel 2 Overrun"] +pub struct OVR2_R(crate::FieldReader); +impl OVR2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR2` writer - Channel 2 Overrun"] +pub struct OVR2_W<'a> { + w: &'a mut W, +} +impl<'a> OVR2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `OVR3` reader - Channel 3 Overrun"] +pub struct OVR3_R(crate::FieldReader); +impl OVR3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR3` writer - Channel 3 Overrun"] +pub struct OVR3_W<'a> { + w: &'a mut W, +} +impl<'a> OVR3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `OVR4` reader - Channel 4 Overrun"] +pub struct OVR4_R(crate::FieldReader); +impl OVR4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR4` writer - Channel 4 Overrun"] +pub struct OVR4_W<'a> { + w: &'a mut W, +} +impl<'a> OVR4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `OVR5` reader - Channel 5 Overrun"] +pub struct OVR5_R(crate::FieldReader); +impl OVR5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR5` writer - Channel 5 Overrun"] +pub struct OVR5_W<'a> { + w: &'a mut W, +} +impl<'a> OVR5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `OVR6` reader - Channel 6 Overrun"] +pub struct OVR6_R(crate::FieldReader); +impl OVR6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR6` writer - Channel 6 Overrun"] +pub struct OVR6_W<'a> { + w: &'a mut W, +} +impl<'a> OVR6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `OVR7` reader - Channel 7 Overrun"] +pub struct OVR7_R(crate::FieldReader); +impl OVR7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR7` writer - Channel 7 Overrun"] +pub struct OVR7_W<'a> { + w: &'a mut W, +} +impl<'a> OVR7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `OVR8` reader - Channel 8 Overrun"] +pub struct OVR8_R(crate::FieldReader); +impl OVR8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR8` writer - Channel 8 Overrun"] +pub struct OVR8_W<'a> { + w: &'a mut W, +} +impl<'a> OVR8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `OVR9` reader - Channel 9 Overrun"] +pub struct OVR9_R(crate::FieldReader); +impl OVR9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR9` writer - Channel 9 Overrun"] +pub struct OVR9_W<'a> { + w: &'a mut W, +} +impl<'a> OVR9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `OVR10` reader - Channel 10 Overrun"] +pub struct OVR10_R(crate::FieldReader); +impl OVR10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR10` writer - Channel 10 Overrun"] +pub struct OVR10_W<'a> { + w: &'a mut W, +} +impl<'a> OVR10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `OVR11` reader - Channel 11 Overrun"] +pub struct OVR11_R(crate::FieldReader); +impl OVR11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR11` writer - Channel 11 Overrun"] +pub struct OVR11_W<'a> { + w: &'a mut W, +} +impl<'a> OVR11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `EVD0` reader - Channel 0 Event Detection"] +pub struct EVD0_R(crate::FieldReader); +impl EVD0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD0` writer - Channel 0 Event Detection"] +pub struct EVD0_W<'a> { + w: &'a mut W, +} +impl<'a> EVD0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `EVD1` reader - Channel 1 Event Detection"] +pub struct EVD1_R(crate::FieldReader); +impl EVD1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD1` writer - Channel 1 Event Detection"] +pub struct EVD1_W<'a> { + w: &'a mut W, +} +impl<'a> EVD1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `EVD2` reader - Channel 2 Event Detection"] +pub struct EVD2_R(crate::FieldReader); +impl EVD2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD2` writer - Channel 2 Event Detection"] +pub struct EVD2_W<'a> { + w: &'a mut W, +} +impl<'a> EVD2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `EVD3` reader - Channel 3 Event Detection"] +pub struct EVD3_R(crate::FieldReader); +impl EVD3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD3` writer - Channel 3 Event Detection"] +pub struct EVD3_W<'a> { + w: &'a mut W, +} +impl<'a> EVD3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `EVD4` reader - Channel 4 Event Detection"] +pub struct EVD4_R(crate::FieldReader); +impl EVD4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD4` writer - Channel 4 Event Detection"] +pub struct EVD4_W<'a> { + w: &'a mut W, +} +impl<'a> EVD4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `EVD5` reader - Channel 5 Event Detection"] +pub struct EVD5_R(crate::FieldReader); +impl EVD5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD5` writer - Channel 5 Event Detection"] +pub struct EVD5_W<'a> { + w: &'a mut W, +} +impl<'a> EVD5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `EVD6` reader - Channel 6 Event Detection"] +pub struct EVD6_R(crate::FieldReader); +impl EVD6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD6` writer - Channel 6 Event Detection"] +pub struct EVD6_W<'a> { + w: &'a mut W, +} +impl<'a> EVD6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `EVD7` reader - Channel 7 Event Detection"] +pub struct EVD7_R(crate::FieldReader); +impl EVD7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD7` writer - Channel 7 Event Detection"] +pub struct EVD7_W<'a> { + w: &'a mut W, +} +impl<'a> EVD7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `EVD8` reader - Channel 8 Event Detection"] +pub struct EVD8_R(crate::FieldReader); +impl EVD8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD8` writer - Channel 8 Event Detection"] +pub struct EVD8_W<'a> { + w: &'a mut W, +} +impl<'a> EVD8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `EVD9` reader - Channel 9 Event Detection"] +pub struct EVD9_R(crate::FieldReader); +impl EVD9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD9` writer - Channel 9 Event Detection"] +pub struct EVD9_W<'a> { + w: &'a mut W, +} +impl<'a> EVD9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `EVD10` reader - Channel 10 Event Detection"] +pub struct EVD10_R(crate::FieldReader); +impl EVD10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD10` writer - Channel 10 Event Detection"] +pub struct EVD10_W<'a> { + w: &'a mut W, +} +impl<'a> EVD10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `EVD11` reader - Channel 11 Event Detection"] +pub struct EVD11_R(crate::FieldReader); +impl EVD11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD11` writer - Channel 11 Event Detection"] +pub struct EVD11_W<'a> { + w: &'a mut W, +} +impl<'a> EVD11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +impl R { + #[doc = "Bit 0 - Channel 0 Overrun"] + #[inline(always)] + pub fn ovr0(&self) -> OVR0_R { + OVR0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel 1 Overrun"] + #[inline(always)] + pub fn ovr1(&self) -> OVR1_R { + OVR1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel 2 Overrun"] + #[inline(always)] + pub fn ovr2(&self) -> OVR2_R { + OVR2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Channel 3 Overrun"] + #[inline(always)] + pub fn ovr3(&self) -> OVR3_R { + OVR3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Channel 4 Overrun"] + #[inline(always)] + pub fn ovr4(&self) -> OVR4_R { + OVR4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Channel 5 Overrun"] + #[inline(always)] + pub fn ovr5(&self) -> OVR5_R { + OVR5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Channel 6 Overrun"] + #[inline(always)] + pub fn ovr6(&self) -> OVR6_R { + OVR6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Channel 7 Overrun"] + #[inline(always)] + pub fn ovr7(&self) -> OVR7_R { + OVR7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Channel 8 Overrun"] + #[inline(always)] + pub fn ovr8(&self) -> OVR8_R { + OVR8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Channel 9 Overrun"] + #[inline(always)] + pub fn ovr9(&self) -> OVR9_R { + OVR9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Channel 10 Overrun"] + #[inline(always)] + pub fn ovr10(&self) -> OVR10_R { + OVR10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Channel 11 Overrun"] + #[inline(always)] + pub fn ovr11(&self) -> OVR11_R { + OVR11_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 16 - Channel 0 Event Detection"] + #[inline(always)] + pub fn evd0(&self) -> EVD0_R { + EVD0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Channel 1 Event Detection"] + #[inline(always)] + pub fn evd1(&self) -> EVD1_R { + EVD1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Channel 2 Event Detection"] + #[inline(always)] + pub fn evd2(&self) -> EVD2_R { + EVD2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Channel 3 Event Detection"] + #[inline(always)] + pub fn evd3(&self) -> EVD3_R { + EVD3_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Channel 4 Event Detection"] + #[inline(always)] + pub fn evd4(&self) -> EVD4_R { + EVD4_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Channel 5 Event Detection"] + #[inline(always)] + pub fn evd5(&self) -> EVD5_R { + EVD5_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Channel 6 Event Detection"] + #[inline(always)] + pub fn evd6(&self) -> EVD6_R { + EVD6_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Channel 7 Event Detection"] + #[inline(always)] + pub fn evd7(&self) -> EVD7_R { + EVD7_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24 - Channel 8 Event Detection"] + #[inline(always)] + pub fn evd8(&self) -> EVD8_R { + EVD8_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Channel 9 Event Detection"] + #[inline(always)] + pub fn evd9(&self) -> EVD9_R { + EVD9_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Channel 10 Event Detection"] + #[inline(always)] + pub fn evd10(&self) -> EVD10_R { + EVD10_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Channel 11 Event Detection"] + #[inline(always)] + pub fn evd11(&self) -> EVD11_R { + EVD11_R::new(((self.bits >> 27) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel 0 Overrun"] + #[inline(always)] + pub fn ovr0(&mut self) -> OVR0_W { + OVR0_W { w: self } + } + #[doc = "Bit 1 - Channel 1 Overrun"] + #[inline(always)] + pub fn ovr1(&mut self) -> OVR1_W { + OVR1_W { w: self } + } + #[doc = "Bit 2 - Channel 2 Overrun"] + #[inline(always)] + pub fn ovr2(&mut self) -> OVR2_W { + OVR2_W { w: self } + } + #[doc = "Bit 3 - Channel 3 Overrun"] + #[inline(always)] + pub fn ovr3(&mut self) -> OVR3_W { + OVR3_W { w: self } + } + #[doc = "Bit 4 - Channel 4 Overrun"] + #[inline(always)] + pub fn ovr4(&mut self) -> OVR4_W { + OVR4_W { w: self } + } + #[doc = "Bit 5 - Channel 5 Overrun"] + #[inline(always)] + pub fn ovr5(&mut self) -> OVR5_W { + OVR5_W { w: self } + } + #[doc = "Bit 6 - Channel 6 Overrun"] + #[inline(always)] + pub fn ovr6(&mut self) -> OVR6_W { + OVR6_W { w: self } + } + #[doc = "Bit 7 - Channel 7 Overrun"] + #[inline(always)] + pub fn ovr7(&mut self) -> OVR7_W { + OVR7_W { w: self } + } + #[doc = "Bit 8 - Channel 8 Overrun"] + #[inline(always)] + pub fn ovr8(&mut self) -> OVR8_W { + OVR8_W { w: self } + } + #[doc = "Bit 9 - Channel 9 Overrun"] + #[inline(always)] + pub fn ovr9(&mut self) -> OVR9_W { + OVR9_W { w: self } + } + #[doc = "Bit 10 - Channel 10 Overrun"] + #[inline(always)] + pub fn ovr10(&mut self) -> OVR10_W { + OVR10_W { w: self } + } + #[doc = "Bit 11 - Channel 11 Overrun"] + #[inline(always)] + pub fn ovr11(&mut self) -> OVR11_W { + OVR11_W { w: self } + } + #[doc = "Bit 16 - Channel 0 Event Detection"] + #[inline(always)] + pub fn evd0(&mut self) -> EVD0_W { + EVD0_W { w: self } + } + #[doc = "Bit 17 - Channel 1 Event Detection"] + #[inline(always)] + pub fn evd1(&mut self) -> EVD1_W { + EVD1_W { w: self } + } + #[doc = "Bit 18 - Channel 2 Event Detection"] + #[inline(always)] + pub fn evd2(&mut self) -> EVD2_W { + EVD2_W { w: self } + } + #[doc = "Bit 19 - Channel 3 Event Detection"] + #[inline(always)] + pub fn evd3(&mut self) -> EVD3_W { + EVD3_W { w: self } + } + #[doc = "Bit 20 - Channel 4 Event Detection"] + #[inline(always)] + pub fn evd4(&mut self) -> EVD4_W { + EVD4_W { w: self } + } + #[doc = "Bit 21 - Channel 5 Event Detection"] + #[inline(always)] + pub fn evd5(&mut self) -> EVD5_W { + EVD5_W { w: self } + } + #[doc = "Bit 22 - Channel 6 Event Detection"] + #[inline(always)] + pub fn evd6(&mut self) -> EVD6_W { + EVD6_W { w: self } + } + #[doc = "Bit 23 - Channel 7 Event Detection"] + #[inline(always)] + pub fn evd7(&mut self) -> EVD7_W { + EVD7_W { w: self } + } + #[doc = "Bit 24 - Channel 8 Event Detection"] + #[inline(always)] + pub fn evd8(&mut self) -> EVD8_W { + EVD8_W { w: self } + } + #[doc = "Bit 25 - Channel 9 Event Detection"] + #[inline(always)] + pub fn evd9(&mut self) -> EVD9_W { + EVD9_W { w: self } + } + #[doc = "Bit 26 - Channel 10 Event Detection"] + #[inline(always)] + pub fn evd10(&mut self) -> EVD10_W { + EVD10_W { w: self } + } + #[doc = "Bit 27 - Channel 11 Event Detection"] + #[inline(always)] + pub fn evd11(&mut self) -> EVD11_W { + EVD11_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/evsys/swevt.rs b/pac/atsamc21e/src/evsys/swevt.rs new file mode 100644 index 000000000000..df58fe290de2 --- /dev/null +++ b/pac/atsamc21e/src/evsys/swevt.rs @@ -0,0 +1,369 @@ +#[doc = "Register `SWEVT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHANNEL0` writer - Channel 0 Software Selection"] +pub struct CHANNEL0_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `CHANNEL1` writer - Channel 1 Software Selection"] +pub struct CHANNEL1_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CHANNEL2` writer - Channel 2 Software Selection"] +pub struct CHANNEL2_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CHANNEL3` writer - Channel 3 Software Selection"] +pub struct CHANNEL3_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CHANNEL4` writer - Channel 4 Software Selection"] +pub struct CHANNEL4_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `CHANNEL5` writer - Channel 5 Software Selection"] +pub struct CHANNEL5_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `CHANNEL6` writer - Channel 6 Software Selection"] +pub struct CHANNEL6_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `CHANNEL7` writer - Channel 7 Software Selection"] +pub struct CHANNEL7_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CHANNEL8` writer - Channel 8 Software Selection"] +pub struct CHANNEL8_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `CHANNEL9` writer - Channel 9 Software Selection"] +pub struct CHANNEL9_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `CHANNEL10` writer - Channel 10 Software Selection"] +pub struct CHANNEL10_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `CHANNEL11` writer - Channel 11 Software Selection"] +pub struct CHANNEL11_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +impl W { + #[doc = "Bit 0 - Channel 0 Software Selection"] + #[inline(always)] + pub fn channel0(&mut self) -> CHANNEL0_W { + CHANNEL0_W { w: self } + } + #[doc = "Bit 1 - Channel 1 Software Selection"] + #[inline(always)] + pub fn channel1(&mut self) -> CHANNEL1_W { + CHANNEL1_W { w: self } + } + #[doc = "Bit 2 - Channel 2 Software Selection"] + #[inline(always)] + pub fn channel2(&mut self) -> CHANNEL2_W { + CHANNEL2_W { w: self } + } + #[doc = "Bit 3 - Channel 3 Software Selection"] + #[inline(always)] + pub fn channel3(&mut self) -> CHANNEL3_W { + CHANNEL3_W { w: self } + } + #[doc = "Bit 4 - Channel 4 Software Selection"] + #[inline(always)] + pub fn channel4(&mut self) -> CHANNEL4_W { + CHANNEL4_W { w: self } + } + #[doc = "Bit 5 - Channel 5 Software Selection"] + #[inline(always)] + pub fn channel5(&mut self) -> CHANNEL5_W { + CHANNEL5_W { w: self } + } + #[doc = "Bit 6 - Channel 6 Software Selection"] + #[inline(always)] + pub fn channel6(&mut self) -> CHANNEL6_W { + CHANNEL6_W { w: self } + } + #[doc = "Bit 7 - Channel 7 Software Selection"] + #[inline(always)] + pub fn channel7(&mut self) -> CHANNEL7_W { + CHANNEL7_W { w: self } + } + #[doc = "Bit 8 - Channel 8 Software Selection"] + #[inline(always)] + pub fn channel8(&mut self) -> CHANNEL8_W { + CHANNEL8_W { w: self } + } + #[doc = "Bit 9 - Channel 9 Software Selection"] + #[inline(always)] + pub fn channel9(&mut self) -> CHANNEL9_W { + CHANNEL9_W { w: self } + } + #[doc = "Bit 10 - Channel 10 Software Selection"] + #[inline(always)] + pub fn channel10(&mut self) -> CHANNEL10_W { + CHANNEL10_W { w: self } + } + #[doc = "Bit 11 - Channel 11 Software Selection"] + #[inline(always)] + pub fn channel11(&mut self) -> CHANNEL11_W { + CHANNEL11_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Software Event\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [swevt](index.html) module"] +pub struct SWEVT_SPEC; +impl crate::RegisterSpec for SWEVT_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [swevt::W](W) writer structure"] +impl crate::Writable for SWEVT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SWEVT to value 0"] +impl crate::Resettable for SWEVT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/evsys/user.rs b/pac/atsamc21e/src/evsys/user.rs new file mode 100644 index 000000000000..848f9f599b79 --- /dev/null +++ b/pac/atsamc21e/src/evsys/user.rs @@ -0,0 +1,104 @@ +#[doc = "Register `USER[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `USER[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHANNEL` reader - Channel Event Selection"] +pub struct CHANNEL_R(crate::FieldReader); +impl CHANNEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CHANNEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHANNEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHANNEL` writer - Channel Event Selection"] +pub struct CHANNEL_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Channel Event Selection"] + #[inline(always)] + pub fn channel(&self) -> CHANNEL_R { + CHANNEL_R::new((self.bits & 0x1f) as u8) + } +} +impl W { + #[doc = "Bits 0:4 - Channel Event Selection"] + #[inline(always)] + pub fn channel(&mut self) -> CHANNEL_W { + CHANNEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "User Multiplexer n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [user](index.html) module"] +pub struct USER_SPEC; +impl crate::RegisterSpec for USER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [user::R](R) reader structure"] +impl crate::Readable for USER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [user::W](W) writer structure"] +impl crate::Writable for USER_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets USER[%s] +to value 0"] +impl crate::Resettable for USER_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/freqm.rs b/pac/atsamc21e/src/freqm.rs new file mode 100644 index 000000000000..f0fc6fda975e --- /dev/null +++ b/pac/atsamc21e/src/freqm.rs @@ -0,0 +1,59 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control A Register"] + pub ctrla: crate::Reg, + #[doc = "0x01 - Control B Register"] + pub ctrlb: crate::Reg, + #[doc = "0x02 - Config A register"] + pub cfga: crate::Reg, + _reserved3: [u8; 0x04], + #[doc = "0x08 - Interrupt Enable Clear Register"] + pub intenclr: crate::Reg, + #[doc = "0x09 - Interrupt Enable Set Register"] + pub intenset: crate::Reg, + #[doc = "0x0a - Interrupt Flag Register"] + pub intflag: crate::Reg, + #[doc = "0x0b - Status Register"] + pub status: crate::Reg, + #[doc = "0x0c - Synchronization Busy Register"] + pub syncbusy: crate::Reg, + #[doc = "0x10 - Count Value Register"] + pub value: crate::Reg, +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A Register"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "Control B Register"] +pub mod ctrlb; +#[doc = "CFGA register accessor: an alias for `Reg`"] +pub type CFGA = crate::Reg; +#[doc = "Config A register"] +pub mod cfga; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear Register"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set Register"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Register"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status Register"] +pub mod status; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Busy Register"] +pub mod syncbusy; +#[doc = "VALUE register accessor: an alias for `Reg`"] +pub type VALUE = crate::Reg; +#[doc = "Count Value Register"] +pub mod value; diff --git a/pac/atsamc21e/src/freqm/cfga.rs b/pac/atsamc21e/src/freqm/cfga.rs new file mode 100644 index 000000000000..573c62964185 --- /dev/null +++ b/pac/atsamc21e/src/freqm/cfga.rs @@ -0,0 +1,103 @@ +#[doc = "Register `CFGA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CFGA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `REFNUM` reader - Number of Reference Clock Cycles"] +pub struct REFNUM_R(crate::FieldReader); +impl REFNUM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REFNUM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REFNUM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REFNUM` writer - Number of Reference Clock Cycles"] +pub struct REFNUM_W<'a> { + w: &'a mut W, +} +impl<'a> REFNUM_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u16 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Number of Reference Clock Cycles"] + #[inline(always)] + pub fn refnum(&self) -> REFNUM_R { + REFNUM_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Number of Reference Clock Cycles"] + #[inline(always)] + pub fn refnum(&mut self) -> REFNUM_W { + REFNUM_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Config A register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cfga](index.html) module"] +pub struct CFGA_SPEC; +impl crate::RegisterSpec for CFGA_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [cfga::R](R) reader structure"] +impl crate::Readable for CFGA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cfga::W](W) writer structure"] +impl crate::Writable for CFGA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CFGA to value 0"] +impl crate::Resettable for CFGA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/freqm/ctrla.rs b/pac/atsamc21e/src/freqm/ctrla.rs new file mode 100644 index 000000000000..b2cefdd45770 --- /dev/null +++ b/pac/atsamc21e/src/freqm/ctrla.rs @@ -0,0 +1,160 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/freqm/ctrlb.rs b/pac/atsamc21e/src/freqm/ctrlb.rs new file mode 100644 index 000000000000..7d350e71fbf3 --- /dev/null +++ b/pac/atsamc21e/src/freqm/ctrlb.rs @@ -0,0 +1,72 @@ +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `START` writer - Start Measurement"] +pub struct START_W<'a> { + w: &'a mut W, +} +impl<'a> START_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0 - Start Measurement"] + #[inline(always)] + pub fn start(&mut self) -> START_W { + START_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u8; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/freqm/intenclr.rs b/pac/atsamc21e/src/freqm/intenclr.rs new file mode 100644 index 000000000000..a224aa5500f6 --- /dev/null +++ b/pac/atsamc21e/src/freqm/intenclr.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DONE` reader - Measurement Done Interrupt Enable"] +pub struct DONE_R(crate::FieldReader); +impl DONE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DONE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DONE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DONE` writer - Measurement Done Interrupt Enable"] +pub struct DONE_W<'a> { + w: &'a mut W, +} +impl<'a> DONE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Measurement Done Interrupt Enable"] + #[inline(always)] + pub fn done(&self) -> DONE_R { + DONE_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Measurement Done Interrupt Enable"] + #[inline(always)] + pub fn done(&mut self) -> DONE_W { + DONE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/freqm/intenset.rs b/pac/atsamc21e/src/freqm/intenset.rs new file mode 100644 index 000000000000..53b3d0bef7c0 --- /dev/null +++ b/pac/atsamc21e/src/freqm/intenset.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DONE` reader - Measurement Done Interrupt Enable"] +pub struct DONE_R(crate::FieldReader); +impl DONE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DONE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DONE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DONE` writer - Measurement Done Interrupt Enable"] +pub struct DONE_W<'a> { + w: &'a mut W, +} +impl<'a> DONE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Measurement Done Interrupt Enable"] + #[inline(always)] + pub fn done(&self) -> DONE_R { + DONE_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Measurement Done Interrupt Enable"] + #[inline(always)] + pub fn done(&mut self) -> DONE_W { + DONE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/freqm/intflag.rs b/pac/atsamc21e/src/freqm/intflag.rs new file mode 100644 index 000000000000..3b8fdab47703 --- /dev/null +++ b/pac/atsamc21e/src/freqm/intflag.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DONE` reader - Measurement Done"] +pub struct DONE_R(crate::FieldReader); +impl DONE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DONE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DONE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DONE` writer - Measurement Done"] +pub struct DONE_W<'a> { + w: &'a mut W, +} +impl<'a> DONE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Measurement Done"] + #[inline(always)] + pub fn done(&self) -> DONE_R { + DONE_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Measurement Done"] + #[inline(always)] + pub fn done(&mut self) -> DONE_W { + DONE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/freqm/status.rs b/pac/atsamc21e/src/freqm/status.rs new file mode 100644 index 000000000000..8a81662f51b0 --- /dev/null +++ b/pac/atsamc21e/src/freqm/status.rs @@ -0,0 +1,160 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BUSY` reader - FREQM Status"] +pub struct BUSY_R(crate::FieldReader); +impl BUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSY` writer - FREQM Status"] +pub struct BUSY_W<'a> { + w: &'a mut W, +} +impl<'a> BUSY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `OVF` reader - Sticky Count Value Overflow"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Sticky Count Value Overflow"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - FREQM Status"] + #[inline(always)] + pub fn busy(&self) -> BUSY_R { + BUSY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Sticky Count Value Overflow"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - FREQM Status"] + #[inline(always)] + pub fn busy(&mut self) -> BUSY_W { + BUSY_W { w: self } + } + #[doc = "Bit 1 - Sticky Count Value Overflow"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/freqm/syncbusy.rs b/pac/atsamc21e/src/freqm/syncbusy.rs new file mode 100644 index 000000000000..54396368e817 --- /dev/null +++ b/pac/atsamc21e/src/freqm/syncbusy.rs @@ -0,0 +1,73 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +#[doc = "Synchronization Busy Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/freqm/value.rs b/pac/atsamc21e/src/freqm/value.rs new file mode 100644 index 000000000000..5b0f5dfd9b67 --- /dev/null +++ b/pac/atsamc21e/src/freqm/value.rs @@ -0,0 +1,53 @@ +#[doc = "Register `VALUE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `VALUE` reader - Measurement Value"] +pub struct VALUE_R(crate::FieldReader); +impl VALUE_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + VALUE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VALUE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:23 - Measurement Value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +#[doc = "Count Value Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [value](index.html) module"] +pub struct VALUE_SPEC; +impl crate::RegisterSpec for VALUE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [value::R](R) reader structure"] +impl crate::Readable for VALUE_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets VALUE to value 0"] +impl crate::Resettable for VALUE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/gclk.rs b/pac/atsamc21e/src/gclk.rs new file mode 100644 index 000000000000..2a37bdedcab3 --- /dev/null +++ b/pac/atsamc21e/src/gclk.rs @@ -0,0 +1,31 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrla: crate::Reg, + _reserved1: [u8; 0x03], + #[doc = "0x04 - Synchronization Busy"] + pub syncbusy: crate::Reg, + _reserved2: [u8; 0x18], + #[doc = "0x20..0x44 - Generic Clock Generator Control"] + pub genctrl: [crate::Reg; 9], + _reserved3: [u8; 0x3c], + #[doc = "0x80..0x124 - Peripheral Clock Control"] + pub pchctrl: [crate::Reg; 41], +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control"] +pub mod ctrla; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Busy"] +pub mod syncbusy; +#[doc = "GENCTRL register accessor: an alias for `Reg`"] +pub type GENCTRL = crate::Reg; +#[doc = "Generic Clock Generator Control"] +pub mod genctrl; +#[doc = "PCHCTRL register accessor: an alias for `Reg`"] +pub type PCHCTRL = crate::Reg; +#[doc = "Peripheral Clock Control"] +pub mod pchctrl; diff --git a/pac/atsamc21e/src/gclk/ctrla.rs b/pac/atsamc21e/src/gclk/ctrla.rs new file mode 100644 index 000000000000..1c24704395ad --- /dev/null +++ b/pac/atsamc21e/src/gclk/ctrla.rs @@ -0,0 +1,113 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/gclk/genctrl.rs b/pac/atsamc21e/src/gclk/genctrl.rs new file mode 100644 index 000000000000..052b2915ca7f --- /dev/null +++ b/pac/atsamc21e/src/gclk/genctrl.rs @@ -0,0 +1,597 @@ +#[doc = "Register `GENCTRL[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GENCTRL[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Source Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SRC_A { + #[doc = "0: XOSC oscillator output"] + XOSC = 0, + #[doc = "1: Generator input pad"] + GCLKIN = 1, + #[doc = "2: Generic clock generator 1 output"] + GCLKGEN1 = 2, + #[doc = "3: OSCULP32K oscillator output"] + OSCULP32K = 3, + #[doc = "4: OSC32K oscillator output"] + OSC32K = 4, + #[doc = "5: XOSC32K oscillator output"] + XOSC32K = 5, + #[doc = "6: OSC48M oscillator output"] + OSC48M = 6, + #[doc = "7: DPLL96M output"] + DPLL96M = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SRC_A) -> Self { + variant as _ + } +} +#[doc = "Field `SRC` reader - Source Select"] +pub struct SRC_R(crate::FieldReader); +impl SRC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SRC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SRC_A { + match self.bits { + 0 => SRC_A::XOSC, + 1 => SRC_A::GCLKIN, + 2 => SRC_A::GCLKGEN1, + 3 => SRC_A::OSCULP32K, + 4 => SRC_A::OSC32K, + 5 => SRC_A::XOSC32K, + 6 => SRC_A::OSC48M, + 7 => SRC_A::DPLL96M, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `XOSC`"] + #[inline(always)] + pub fn is_xosc(&self) -> bool { + **self == SRC_A::XOSC + } + #[doc = "Checks if the value of the field is `GCLKIN`"] + #[inline(always)] + pub fn is_gclkin(&self) -> bool { + **self == SRC_A::GCLKIN + } + #[doc = "Checks if the value of the field is `GCLKGEN1`"] + #[inline(always)] + pub fn is_gclkgen1(&self) -> bool { + **self == SRC_A::GCLKGEN1 + } + #[doc = "Checks if the value of the field is `OSCULP32K`"] + #[inline(always)] + pub fn is_osculp32k(&self) -> bool { + **self == SRC_A::OSCULP32K + } + #[doc = "Checks if the value of the field is `OSC32K`"] + #[inline(always)] + pub fn is_osc32k(&self) -> bool { + **self == SRC_A::OSC32K + } + #[doc = "Checks if the value of the field is `XOSC32K`"] + #[inline(always)] + pub fn is_xosc32k(&self) -> bool { + **self == SRC_A::XOSC32K + } + #[doc = "Checks if the value of the field is `OSC48M`"] + #[inline(always)] + pub fn is_osc48m(&self) -> bool { + **self == SRC_A::OSC48M + } + #[doc = "Checks if the value of the field is `DPLL96M`"] + #[inline(always)] + pub fn is_dpll96m(&self) -> bool { + **self == SRC_A::DPLL96M + } +} +impl core::ops::Deref for SRC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SRC` writer - Source Select"] +pub struct SRC_W<'a> { + w: &'a mut W, +} +impl<'a> SRC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SRC_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "XOSC oscillator output"] + #[inline(always)] + pub fn xosc(self) -> &'a mut W { + self.variant(SRC_A::XOSC) + } + #[doc = "Generator input pad"] + #[inline(always)] + pub fn gclkin(self) -> &'a mut W { + self.variant(SRC_A::GCLKIN) + } + #[doc = "Generic clock generator 1 output"] + #[inline(always)] + pub fn gclkgen1(self) -> &'a mut W { + self.variant(SRC_A::GCLKGEN1) + } + #[doc = "OSCULP32K oscillator output"] + #[inline(always)] + pub fn osculp32k(self) -> &'a mut W { + self.variant(SRC_A::OSCULP32K) + } + #[doc = "OSC32K oscillator output"] + #[inline(always)] + pub fn osc32k(self) -> &'a mut W { + self.variant(SRC_A::OSC32K) + } + #[doc = "XOSC32K oscillator output"] + #[inline(always)] + pub fn xosc32k(self) -> &'a mut W { + self.variant(SRC_A::XOSC32K) + } + #[doc = "OSC48M oscillator output"] + #[inline(always)] + pub fn osc48m(self) -> &'a mut W { + self.variant(SRC_A::OSC48M) + } + #[doc = "DPLL96M output"] + #[inline(always)] + pub fn dpll96m(self) -> &'a mut W { + self.variant(SRC_A::DPLL96M) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Field `GENEN` reader - Generic Clock Generator Enable"] +pub struct GENEN_R(crate::FieldReader); +impl GENEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENEN` writer - Generic Clock Generator Enable"] +pub struct GENEN_W<'a> { + w: &'a mut W, +} +impl<'a> GENEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `IDC` reader - Improve Duty Cycle"] +pub struct IDC_R(crate::FieldReader); +impl IDC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IDC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IDC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IDC` writer - Improve Duty Cycle"] +pub struct IDC_W<'a> { + w: &'a mut W, +} +impl<'a> IDC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `OOV` reader - Output Off Value"] +pub struct OOV_R(crate::FieldReader); +impl OOV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OOV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OOV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OOV` writer - Output Off Value"] +pub struct OOV_W<'a> { + w: &'a mut W, +} +impl<'a> OOV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `OE` reader - Output Enable"] +pub struct OE_R(crate::FieldReader); +impl OE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OE` writer - Output Enable"] +pub struct OE_W<'a> { + w: &'a mut W, +} +impl<'a> OE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Divide Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum DIVSEL_A { + #[doc = "0: Divide input directly by divider factor"] + DIV1 = 0, + #[doc = "1: Divide input by 2^(divider factor+ 1)"] + DIV2 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DIVSEL_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DIVSEL` reader - Divide Selection"] +pub struct DIVSEL_R(crate::FieldReader); +impl DIVSEL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIVSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DIVSEL_A { + match self.bits { + false => DIVSEL_A::DIV1, + true => DIVSEL_A::DIV2, + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == DIVSEL_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == DIVSEL_A::DIV2 + } +} +impl core::ops::Deref for DIVSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIVSEL` writer - Divide Selection"] +pub struct DIVSEL_W<'a> { + w: &'a mut W, +} +impl<'a> DIVSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DIVSEL_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Divide input directly by divider factor"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(DIVSEL_A::DIV1) + } + #[doc = "Divide input by 2^(divider factor+ 1)"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(DIVSEL_A::DIV2) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `DIV` reader - Division Factor"] +pub struct DIV_R(crate::FieldReader); +impl DIV_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + DIV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIV` writer - Division Factor"] +pub struct DIV_W<'a> { + w: &'a mut W, +} +impl<'a> DIV_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xffff << 16)) | ((value as u32 & 0xffff) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Source Select"] + #[inline(always)] + pub fn src(&self) -> SRC_R { + SRC_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 8 - Generic Clock Generator Enable"] + #[inline(always)] + pub fn genen(&self) -> GENEN_R { + GENEN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Improve Duty Cycle"] + #[inline(always)] + pub fn idc(&self) -> IDC_R { + IDC_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Output Off Value"] + #[inline(always)] + pub fn oov(&self) -> OOV_R { + OOV_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Output Enable"] + #[inline(always)] + pub fn oe(&self) -> OE_R { + OE_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Divide Selection"] + #[inline(always)] + pub fn divsel(&self) -> DIVSEL_R { + DIVSEL_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bits 16:31 - Division Factor"] + #[inline(always)] + pub fn div(&self) -> DIV_R { + DIV_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:2 - Source Select"] + #[inline(always)] + pub fn src(&mut self) -> SRC_W { + SRC_W { w: self } + } + #[doc = "Bit 8 - Generic Clock Generator Enable"] + #[inline(always)] + pub fn genen(&mut self) -> GENEN_W { + GENEN_W { w: self } + } + #[doc = "Bit 9 - Improve Duty Cycle"] + #[inline(always)] + pub fn idc(&mut self) -> IDC_W { + IDC_W { w: self } + } + #[doc = "Bit 10 - Output Off Value"] + #[inline(always)] + pub fn oov(&mut self) -> OOV_W { + OOV_W { w: self } + } + #[doc = "Bit 11 - Output Enable"] + #[inline(always)] + pub fn oe(&mut self) -> OE_W { + OE_W { w: self } + } + #[doc = "Bit 12 - Divide Selection"] + #[inline(always)] + pub fn divsel(&mut self) -> DIVSEL_W { + DIVSEL_W { w: self } + } + #[doc = "Bit 13 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bits 16:31 - Division Factor"] + #[inline(always)] + pub fn div(&mut self) -> DIV_W { + DIV_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Generic Clock Generator Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [genctrl](index.html) module"] +pub struct GENCTRL_SPEC; +impl crate::RegisterSpec for GENCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [genctrl::R](R) reader structure"] +impl crate::Readable for GENCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [genctrl::W](W) writer structure"] +impl crate::Writable for GENCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets GENCTRL[%s] +to value 0"] +impl crate::Resettable for GENCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/gclk/pchctrl.rs b/pac/atsamc21e/src/gclk/pchctrl.rs new file mode 100644 index 000000000000..8001ffeaa1ee --- /dev/null +++ b/pac/atsamc21e/src/gclk/pchctrl.rs @@ -0,0 +1,338 @@ +#[doc = "Register `PCHCTRL[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PCHCTRL[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Generic Clock Generator\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum GEN_A { + #[doc = "0: Generic clock generator 0"] + GCLK0 = 0, + #[doc = "1: Generic clock generator 1"] + GCLK1 = 1, + #[doc = "2: Generic clock generator 2"] + GCLK2 = 2, + #[doc = "3: Generic clock generator 3"] + GCLK3 = 3, + #[doc = "4: Generic clock generator 4"] + GCLK4 = 4, + #[doc = "5: Generic clock generator 5"] + GCLK5 = 5, + #[doc = "6: Generic clock generator 6"] + GCLK6 = 6, + #[doc = "7: Generic clock generator 7"] + GCLK7 = 7, + #[doc = "8: Generic clock generator 8"] + GCLK8 = 8, +} +impl From for u8 { + #[inline(always)] + fn from(variant: GEN_A) -> Self { + variant as _ + } +} +#[doc = "Field `GEN` reader - Generic Clock Generator"] +pub struct GEN_R(crate::FieldReader); +impl GEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + GEN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(GEN_A::GCLK0), + 1 => Some(GEN_A::GCLK1), + 2 => Some(GEN_A::GCLK2), + 3 => Some(GEN_A::GCLK3), + 4 => Some(GEN_A::GCLK4), + 5 => Some(GEN_A::GCLK5), + 6 => Some(GEN_A::GCLK6), + 7 => Some(GEN_A::GCLK7), + 8 => Some(GEN_A::GCLK8), + _ => None, + } + } + #[doc = "Checks if the value of the field is `GCLK0`"] + #[inline(always)] + pub fn is_gclk0(&self) -> bool { + **self == GEN_A::GCLK0 + } + #[doc = "Checks if the value of the field is `GCLK1`"] + #[inline(always)] + pub fn is_gclk1(&self) -> bool { + **self == GEN_A::GCLK1 + } + #[doc = "Checks if the value of the field is `GCLK2`"] + #[inline(always)] + pub fn is_gclk2(&self) -> bool { + **self == GEN_A::GCLK2 + } + #[doc = "Checks if the value of the field is `GCLK3`"] + #[inline(always)] + pub fn is_gclk3(&self) -> bool { + **self == GEN_A::GCLK3 + } + #[doc = "Checks if the value of the field is `GCLK4`"] + #[inline(always)] + pub fn is_gclk4(&self) -> bool { + **self == GEN_A::GCLK4 + } + #[doc = "Checks if the value of the field is `GCLK5`"] + #[inline(always)] + pub fn is_gclk5(&self) -> bool { + **self == GEN_A::GCLK5 + } + #[doc = "Checks if the value of the field is `GCLK6`"] + #[inline(always)] + pub fn is_gclk6(&self) -> bool { + **self == GEN_A::GCLK6 + } + #[doc = "Checks if the value of the field is `GCLK7`"] + #[inline(always)] + pub fn is_gclk7(&self) -> bool { + **self == GEN_A::GCLK7 + } + #[doc = "Checks if the value of the field is `GCLK8`"] + #[inline(always)] + pub fn is_gclk8(&self) -> bool { + **self == GEN_A::GCLK8 + } +} +impl core::ops::Deref for GEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GEN` writer - Generic Clock Generator"] +pub struct GEN_W<'a> { + w: &'a mut W, +} +impl<'a> GEN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: GEN_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Generic clock generator 0"] + #[inline(always)] + pub fn gclk0(self) -> &'a mut W { + self.variant(GEN_A::GCLK0) + } + #[doc = "Generic clock generator 1"] + #[inline(always)] + pub fn gclk1(self) -> &'a mut W { + self.variant(GEN_A::GCLK1) + } + #[doc = "Generic clock generator 2"] + #[inline(always)] + pub fn gclk2(self) -> &'a mut W { + self.variant(GEN_A::GCLK2) + } + #[doc = "Generic clock generator 3"] + #[inline(always)] + pub fn gclk3(self) -> &'a mut W { + self.variant(GEN_A::GCLK3) + } + #[doc = "Generic clock generator 4"] + #[inline(always)] + pub fn gclk4(self) -> &'a mut W { + self.variant(GEN_A::GCLK4) + } + #[doc = "Generic clock generator 5"] + #[inline(always)] + pub fn gclk5(self) -> &'a mut W { + self.variant(GEN_A::GCLK5) + } + #[doc = "Generic clock generator 6"] + #[inline(always)] + pub fn gclk6(self) -> &'a mut W { + self.variant(GEN_A::GCLK6) + } + #[doc = "Generic clock generator 7"] + #[inline(always)] + pub fn gclk7(self) -> &'a mut W { + self.variant(GEN_A::GCLK7) + } + #[doc = "Generic clock generator 8"] + #[inline(always)] + pub fn gclk8(self) -> &'a mut W { + self.variant(GEN_A::GCLK8) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Field `CHEN` reader - Channel Enable"] +pub struct CHEN_R(crate::FieldReader); +impl CHEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHEN` writer - Channel Enable"] +pub struct CHEN_W<'a> { + w: &'a mut W, +} +impl<'a> CHEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `WRTLOCK` reader - Write Lock"] +pub struct WRTLOCK_R(crate::FieldReader); +impl WRTLOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WRTLOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WRTLOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WRTLOCK` writer - Write Lock"] +pub struct WRTLOCK_W<'a> { + w: &'a mut W, +} +impl<'a> WRTLOCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Generic Clock Generator"] + #[inline(always)] + pub fn gen(&self) -> GEN_R { + GEN_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 6 - Channel Enable"] + #[inline(always)] + pub fn chen(&self) -> CHEN_R { + CHEN_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&self) -> WRTLOCK_R { + WRTLOCK_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Generic Clock Generator"] + #[inline(always)] + pub fn gen(&mut self) -> GEN_W { + GEN_W { w: self } + } + #[doc = "Bit 6 - Channel Enable"] + #[inline(always)] + pub fn chen(&mut self) -> CHEN_W { + CHEN_W { w: self } + } + #[doc = "Bit 7 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&mut self) -> WRTLOCK_W { + WRTLOCK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Peripheral Clock Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pchctrl](index.html) module"] +pub struct PCHCTRL_SPEC; +impl crate::RegisterSpec for PCHCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pchctrl::R](R) reader structure"] +impl crate::Readable for PCHCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [pchctrl::W](W) writer structure"] +impl crate::Writable for PCHCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PCHCTRL[%s] +to value 0"] +impl crate::Resettable for PCHCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/gclk/syncbusy.rs b/pac/atsamc21e/src/gclk/syncbusy.rs new file mode 100644 index 000000000000..f21640440354 --- /dev/null +++ b/pac/atsamc21e/src/gclk/syncbusy.rs @@ -0,0 +1,233 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchroniation Busy bit"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENCTRL0` reader - Generic Clock Generator Control 0 Synchronization Busy bits"] +pub struct GENCTRL0_R(crate::FieldReader); +impl GENCTRL0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENCTRL0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENCTRL0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENCTRL1` reader - Generic Clock Generator Control 1 Synchronization Busy bits"] +pub struct GENCTRL1_R(crate::FieldReader); +impl GENCTRL1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENCTRL1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENCTRL1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENCTRL2` reader - Generic Clock Generator Control 2 Synchronization Busy bits"] +pub struct GENCTRL2_R(crate::FieldReader); +impl GENCTRL2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENCTRL2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENCTRL2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENCTRL3` reader - Generic Clock Generator Control 3 Synchronization Busy bits"] +pub struct GENCTRL3_R(crate::FieldReader); +impl GENCTRL3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENCTRL3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENCTRL3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENCTRL4` reader - Generic Clock Generator Control 4 Synchronization Busy bits"] +pub struct GENCTRL4_R(crate::FieldReader); +impl GENCTRL4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENCTRL4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENCTRL4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENCTRL5` reader - Generic Clock Generator Control 5 Synchronization Busy bits"] +pub struct GENCTRL5_R(crate::FieldReader); +impl GENCTRL5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENCTRL5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENCTRL5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENCTRL6` reader - Generic Clock Generator Control 6 Synchronization Busy bits"] +pub struct GENCTRL6_R(crate::FieldReader); +impl GENCTRL6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENCTRL6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENCTRL6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENCTRL7` reader - Generic Clock Generator Control 7 Synchronization Busy bits"] +pub struct GENCTRL7_R(crate::FieldReader); +impl GENCTRL7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENCTRL7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENCTRL7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENCTRL8` reader - Generic Clock Generator Control 8 Synchronization Busy bits"] +pub struct GENCTRL8_R(crate::FieldReader); +impl GENCTRL8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENCTRL8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENCTRL8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchroniation Busy bit"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 2 - Generic Clock Generator Control 0 Synchronization Busy bits"] + #[inline(always)] + pub fn genctrl0(&self) -> GENCTRL0_R { + GENCTRL0_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Generic Clock Generator Control 1 Synchronization Busy bits"] + #[inline(always)] + pub fn genctrl1(&self) -> GENCTRL1_R { + GENCTRL1_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Generic Clock Generator Control 2 Synchronization Busy bits"] + #[inline(always)] + pub fn genctrl2(&self) -> GENCTRL2_R { + GENCTRL2_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Generic Clock Generator Control 3 Synchronization Busy bits"] + #[inline(always)] + pub fn genctrl3(&self) -> GENCTRL3_R { + GENCTRL3_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Generic Clock Generator Control 4 Synchronization Busy bits"] + #[inline(always)] + pub fn genctrl4(&self) -> GENCTRL4_R { + GENCTRL4_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Generic Clock Generator Control 5 Synchronization Busy bits"] + #[inline(always)] + pub fn genctrl5(&self) -> GENCTRL5_R { + GENCTRL5_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Generic Clock Generator Control 6 Synchronization Busy bits"] + #[inline(always)] + pub fn genctrl6(&self) -> GENCTRL6_R { + GENCTRL6_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Generic Clock Generator Control 7 Synchronization Busy bits"] + #[inline(always)] + pub fn genctrl7(&self) -> GENCTRL7_R { + GENCTRL7_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Generic Clock Generator Control 8 Synchronization Busy bits"] + #[inline(always)] + pub fn genctrl8(&self) -> GENCTRL8_R { + GENCTRL8_R::new(((self.bits >> 10) & 0x01) != 0) + } +} +#[doc = "Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/generic.rs b/pac/atsamc21e/src/generic.rs new file mode 100644 index 000000000000..76159643acfa --- /dev/null +++ b/pac/atsamc21e/src/generic.rs @@ -0,0 +1,260 @@ +use core::marker; +#[doc = " Raw register type"] +pub trait RegisterSpec { + #[doc = " Raw register type (`u8`, `u16`, `u32`, ...)."] + type Ux: Copy; +} +#[doc = " Trait implemented by readable registers to enable the `read` method."] +#[doc = ""] +#[doc = " Registers marked with `Writable` can be also `modify`'ed."] +pub trait Readable: RegisterSpec { + #[doc = " Result from a call to `read` and argument to `modify`."] + type Reader: From> + core::ops::Deref>; +} +#[doc = " Trait implemented by writeable registers."] +#[doc = ""] +#[doc = " This enables the `write`, `write_with_zero` and `reset` methods."] +#[doc = ""] +#[doc = " Registers marked with `Readable` can be also `modify`'ed."] +pub trait Writable: RegisterSpec { + #[doc = " Writer type argument to `write`, et al."] + type Writer: From> + core::ops::DerefMut>; +} +#[doc = " Reset value of the register."] +#[doc = ""] +#[doc = " This value is the initial value for the `write` method. It can also be directly written to the"] +#[doc = " register by using the `reset` method."] +pub trait Resettable: RegisterSpec { + #[doc = " Reset value of the register."] + fn reset_value() -> Self::Ux; +} +#[doc = " This structure provides volatile access to registers."] +#[repr(transparent)] +pub struct Reg { + register: vcell::VolatileCell, + _marker: marker::PhantomData, +} +unsafe impl Send for Reg where REG::Ux: Send {} +impl Reg { + #[doc = " Returns the underlying memory address of register."] + #[doc = ""] + #[doc = " ```ignore"] + #[doc = " let reg_ptr = periph.reg.as_ptr();"] + #[doc = " ```"] + #[inline(always)] + pub fn as_ptr(&self) -> *mut REG::Ux { + self.register.as_ptr() + } +} +impl Reg { + #[doc = " Reads the contents of a `Readable` register."] + #[doc = ""] + #[doc = " You can read the raw contents of a register by using `bits`:"] + #[doc = " ```ignore"] + #[doc = " let bits = periph.reg.read().bits();"] + #[doc = " ```"] + #[doc = " or get the content of a particular field of a register:"] + #[doc = " ```ignore"] + #[doc = " let reader = periph.reg.read();"] + #[doc = " let bits = reader.field1().bits();"] + #[doc = " let flag = reader.field2().bit_is_set();"] + #[doc = " ```"] + #[inline(always)] + pub fn read(&self) -> REG::Reader { + REG::Reader::from(R { + bits: self.register.get(), + _reg: marker::PhantomData, + }) + } +} +impl Reg { + #[doc = " Writes the reset value to `Writable` register."] + #[doc = ""] + #[doc = " Resets the register to its initial state."] + #[inline(always)] + pub fn reset(&self) { + self.register.set(REG::reset_value()) + } + #[doc = " Writes bits to a `Writable` register."] + #[doc = ""] + #[doc = " You can write raw bits into a register:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.write(|w| unsafe { w.bits(rawbits) });"] + #[doc = " ```"] + #[doc = " or write only the fields you need:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.write(|w| w"] + #[doc = " .field1().bits(newfield1bits)"] + #[doc = " .field2().set_bit()"] + #[doc = " .field3().variant(VARIANT)"] + #[doc = " );"] + #[doc = " ```"] + #[doc = " In the latter case, other fields will be set to their reset value."] + #[inline(always)] + pub fn write(&self, f: F) + where + F: FnOnce(&mut REG::Writer) -> &mut W, + { + self.register.set( + f(&mut REG::Writer::from(W { + bits: REG::reset_value(), + _reg: marker::PhantomData, + })) + .bits, + ); + } +} +impl Reg +where + REG::Ux: Default, +{ + #[doc = " Writes 0 to a `Writable` register."] + #[doc = ""] + #[doc = " Similar to `write`, but unused bits will contain 0."] + #[inline(always)] + pub unsafe fn write_with_zero(&self, f: F) + where + F: FnOnce(&mut REG::Writer) -> &mut W, + { + self.register.set( + (*f(&mut REG::Writer::from(W { + bits: REG::Ux::default(), + _reg: marker::PhantomData, + }))) + .bits, + ); + } +} +impl Reg { + #[doc = " Modifies the contents of the register by reading and then writing it."] + #[doc = ""] + #[doc = " E.g. to do a read-modify-write sequence to change parts of a register:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.modify(|r, w| unsafe { w.bits("] + #[doc = " r.bits() | 3"] + #[doc = " ) });"] + #[doc = " ```"] + #[doc = " or"] + #[doc = " ```ignore"] + #[doc = " periph.reg.modify(|_, w| w"] + #[doc = " .field1().bits(newfield1bits)"] + #[doc = " .field2().set_bit()"] + #[doc = " .field3().variant(VARIANT)"] + #[doc = " );"] + #[doc = " ```"] + #[doc = " Other fields will have the value they had before the call to `modify`."] + #[inline(always)] + pub fn modify(&self, f: F) + where + for<'w> F: FnOnce(®::Reader, &'w mut REG::Writer) -> &'w mut W, + { + let bits = self.register.get(); + self.register.set( + f( + ®::Reader::from(R { + bits, + _reg: marker::PhantomData, + }), + &mut REG::Writer::from(W { + bits, + _reg: marker::PhantomData, + }), + ) + .bits, + ); + } +} +#[doc = " Register reader."] +#[doc = ""] +#[doc = " Result of the `read` methods of registers. Also used as a closure argument in the `modify`"] +#[doc = " method."] +pub struct R { + pub(crate) bits: REG::Ux, + _reg: marker::PhantomData, +} +impl R { + #[doc = " Reads raw bits from register."] + #[inline(always)] + pub fn bits(&self) -> REG::Ux { + self.bits + } +} +impl PartialEq for R +where + REG::Ux: PartialEq, + FI: Copy + Into, +{ + #[inline(always)] + fn eq(&self, other: &FI) -> bool { + self.bits.eq(&(*other).into()) + } +} +#[doc = " Register writer."] +#[doc = ""] +#[doc = " Used as an argument to the closures in the `write` and `modify` methods of the register."] +pub struct W { + #[doc = "Writable bits"] + pub(crate) bits: REG::Ux, + _reg: marker::PhantomData, +} +impl W { + #[doc = " Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = " Field reader."] +#[doc = ""] +#[doc = " Result of the `read` methods of fields."] +pub struct FieldReader { + pub(crate) bits: U, + _reg: marker::PhantomData, +} +impl FieldReader +where + U: Copy, +{ + #[doc = " Creates a new instance of the reader."] + #[allow(unused)] + #[inline(always)] + pub(crate) fn new(bits: U) -> Self { + Self { + bits, + _reg: marker::PhantomData, + } + } + #[doc = " Reads raw bits from field."] + #[inline(always)] + pub fn bits(&self) -> U { + self.bits + } +} +impl PartialEq for FieldReader +where + U: PartialEq, + FI: Copy + Into, +{ + #[inline(always)] + fn eq(&self, other: &FI) -> bool { + self.bits.eq(&(*other).into()) + } +} +impl FieldReader { + #[doc = " Value of the field as raw bits."] + #[inline(always)] + pub fn bit(&self) -> bool { + self.bits + } + #[doc = " Returns `true` if the bit is clear (0)."] + #[inline(always)] + pub fn bit_is_clear(&self) -> bool { + !self.bit() + } + #[doc = " Returns `true` if the bit is set (1)."] + #[inline(always)] + pub fn bit_is_set(&self) -> bool { + self.bit() + } +} diff --git a/pac/atsamc21e/src/hmatrixhs.rs b/pac/atsamc21e/src/hmatrixhs.rs new file mode 100644 index 000000000000..c8129ac89b6f --- /dev/null +++ b/pac/atsamc21e/src/hmatrixhs.rs @@ -0,0 +1,43 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00..0x40 - Master Configuration"] + pub mcfg: [crate::Reg; 16], + #[doc = "0x40..0x80 - Slave Configuration"] + pub scfg: [crate::Reg; 16], + #[doc = "0x80..0xa0 - PRS\\[%s\\]"] + pub prs: [PRS; 4], + _reserved3: [u8; 0x60], + #[doc = "0x100 - Master Remap Control"] + pub mrcr: crate::Reg, + _reserved4: [u8; 0x0c], + #[doc = "0x110..0x150 - Special Function"] + pub sfr: [crate::Reg; 16], +} +#[doc = r"Register block"] +#[repr(C)] +pub struct PRS { + #[doc = "0x00 - Priority A for Slave"] + pub pras: crate::Reg, + #[doc = "0x04 - Priority B for Slave"] + pub prbs: crate::Reg, +} +#[doc = r"Register block"] +#[doc = "PRS\\[%s\\]"] +pub mod prs; +#[doc = "MCFG register accessor: an alias for `Reg`"] +pub type MCFG = crate::Reg; +#[doc = "Master Configuration"] +pub mod mcfg; +#[doc = "SCFG register accessor: an alias for `Reg`"] +pub type SCFG = crate::Reg; +#[doc = "Slave Configuration"] +pub mod scfg; +#[doc = "MRCR register accessor: an alias for `Reg`"] +pub type MRCR = crate::Reg; +#[doc = "Master Remap Control"] +pub mod mrcr; +#[doc = "SFR register accessor: an alias for `Reg`"] +pub type SFR = crate::Reg; +#[doc = "Special Function"] +pub mod sfr; diff --git a/pac/atsamc21e/src/hmatrixhs/mcfg.rs b/pac/atsamc21e/src/hmatrixhs/mcfg.rs new file mode 100644 index 000000000000..454a39fabe13 --- /dev/null +++ b/pac/atsamc21e/src/hmatrixhs/mcfg.rs @@ -0,0 +1,192 @@ +#[doc = "Register `MCFG[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MCFG[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Undefined Length Burst Type\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum ULBT_A { + #[doc = "0: Infinite Length"] + INFINITE = 0, + #[doc = "1: Single Access"] + SINGLE = 1, + #[doc = "2: Four Beat Burst"] + FOUR_BEAT = 2, + #[doc = "3: Eight Beat Burst"] + EIGHT_BEAT = 3, + #[doc = "4: Sixteen Beat Burst"] + SIXTEEN_BEAT = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: ULBT_A) -> Self { + variant as _ + } +} +#[doc = "Field `ULBT` reader - Undefined Length Burst Type"] +pub struct ULBT_R(crate::FieldReader); +impl ULBT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ULBT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(ULBT_A::INFINITE), + 1 => Some(ULBT_A::SINGLE), + 2 => Some(ULBT_A::FOUR_BEAT), + 3 => Some(ULBT_A::EIGHT_BEAT), + 4 => Some(ULBT_A::SIXTEEN_BEAT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `INFINITE`"] + #[inline(always)] + pub fn is_infinite(&self) -> bool { + **self == ULBT_A::INFINITE + } + #[doc = "Checks if the value of the field is `SINGLE`"] + #[inline(always)] + pub fn is_single(&self) -> bool { + **self == ULBT_A::SINGLE + } + #[doc = "Checks if the value of the field is `FOUR_BEAT`"] + #[inline(always)] + pub fn is_four_beat(&self) -> bool { + **self == ULBT_A::FOUR_BEAT + } + #[doc = "Checks if the value of the field is `EIGHT_BEAT`"] + #[inline(always)] + pub fn is_eight_beat(&self) -> bool { + **self == ULBT_A::EIGHT_BEAT + } + #[doc = "Checks if the value of the field is `SIXTEEN_BEAT`"] + #[inline(always)] + pub fn is_sixteen_beat(&self) -> bool { + **self == ULBT_A::SIXTEEN_BEAT + } +} +impl core::ops::Deref for ULBT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ULBT` writer - Undefined Length Burst Type"] +pub struct ULBT_W<'a> { + w: &'a mut W, +} +impl<'a> ULBT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: ULBT_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Infinite Length"] + #[inline(always)] + pub fn infinite(self) -> &'a mut W { + self.variant(ULBT_A::INFINITE) + } + #[doc = "Single Access"] + #[inline(always)] + pub fn single(self) -> &'a mut W { + self.variant(ULBT_A::SINGLE) + } + #[doc = "Four Beat Burst"] + #[inline(always)] + pub fn four_beat(self) -> &'a mut W { + self.variant(ULBT_A::FOUR_BEAT) + } + #[doc = "Eight Beat Burst"] + #[inline(always)] + pub fn eight_beat(self) -> &'a mut W { + self.variant(ULBT_A::EIGHT_BEAT) + } + #[doc = "Sixteen Beat Burst"] + #[inline(always)] + pub fn sixteen_beat(self) -> &'a mut W { + self.variant(ULBT_A::SIXTEEN_BEAT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Undefined Length Burst Type"] + #[inline(always)] + pub fn ulbt(&self) -> ULBT_R { + ULBT_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Undefined Length Burst Type"] + #[inline(always)] + pub fn ulbt(&mut self) -> ULBT_W { + ULBT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Master Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mcfg](index.html) module"] +pub struct MCFG_SPEC; +impl crate::RegisterSpec for MCFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [mcfg::R](R) reader structure"] +impl crate::Readable for MCFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [mcfg::W](W) writer structure"] +impl crate::Writable for MCFG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets MCFG[%s] +to value 0x02"] +impl crate::Resettable for MCFG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x02 + } +} diff --git a/pac/atsamc21e/src/hmatrixhs/mrcr.rs b/pac/atsamc21e/src/hmatrixhs/mrcr.rs new file mode 100644 index 000000000000..0cf2a1fb01be --- /dev/null +++ b/pac/atsamc21e/src/hmatrixhs/mrcr.rs @@ -0,0 +1,1570 @@ +#[doc = "Register `MRCR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MRCR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Remap Command Bit for Master 0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB0_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB0_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB0` reader - Remap Command Bit for Master 0"] +pub struct RCB0_R(crate::FieldReader); +impl RCB0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB0_A { + match self.bits { + false => RCB0_A::DIS, + true => RCB0_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB0_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB0_A::ENA + } +} +impl core::ops::Deref for RCB0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB0` writer - Remap Command Bit for Master 0"] +pub struct RCB0_W<'a> { + w: &'a mut W, +} +impl<'a> RCB0_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB0_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB0_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB0_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Remap Command Bit for Master 1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB1_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB1_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB1` reader - Remap Command Bit for Master 1"] +pub struct RCB1_R(crate::FieldReader); +impl RCB1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB1_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB1_A { + match self.bits { + false => RCB1_A::DIS, + true => RCB1_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB1_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB1_A::ENA + } +} +impl core::ops::Deref for RCB1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB1` writer - Remap Command Bit for Master 1"] +pub struct RCB1_W<'a> { + w: &'a mut W, +} +impl<'a> RCB1_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB1_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB1_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB1_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Remap Command Bit for Master 2\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB2_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB2_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB2` reader - Remap Command Bit for Master 2"] +pub struct RCB2_R(crate::FieldReader); +impl RCB2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB2_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB2_A { + match self.bits { + false => RCB2_A::DIS, + true => RCB2_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB2_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB2_A::ENA + } +} +impl core::ops::Deref for RCB2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB2` writer - Remap Command Bit for Master 2"] +pub struct RCB2_W<'a> { + w: &'a mut W, +} +impl<'a> RCB2_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB2_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB2_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB2_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Remap Command Bit for Master 3\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB3_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB3_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB3` reader - Remap Command Bit for Master 3"] +pub struct RCB3_R(crate::FieldReader); +impl RCB3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB3_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB3_A { + match self.bits { + false => RCB3_A::DIS, + true => RCB3_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB3_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB3_A::ENA + } +} +impl core::ops::Deref for RCB3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB3` writer - Remap Command Bit for Master 3"] +pub struct RCB3_W<'a> { + w: &'a mut W, +} +impl<'a> RCB3_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB3_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB3_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB3_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Remap Command Bit for Master 4\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB4_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB4_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB4` reader - Remap Command Bit for Master 4"] +pub struct RCB4_R(crate::FieldReader); +impl RCB4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB4_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB4_A { + match self.bits { + false => RCB4_A::DIS, + true => RCB4_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB4_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB4_A::ENA + } +} +impl core::ops::Deref for RCB4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB4` writer - Remap Command Bit for Master 4"] +pub struct RCB4_W<'a> { + w: &'a mut W, +} +impl<'a> RCB4_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB4_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB4_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB4_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Remap Command Bit for Master 5\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB5_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB5_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB5` reader - Remap Command Bit for Master 5"] +pub struct RCB5_R(crate::FieldReader); +impl RCB5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB5_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB5_A { + match self.bits { + false => RCB5_A::DIS, + true => RCB5_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB5_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB5_A::ENA + } +} +impl core::ops::Deref for RCB5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB5` writer - Remap Command Bit for Master 5"] +pub struct RCB5_W<'a> { + w: &'a mut W, +} +impl<'a> RCB5_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB5_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB5_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB5_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Remap Command Bit for Master 6\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB6_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB6_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB6` reader - Remap Command Bit for Master 6"] +pub struct RCB6_R(crate::FieldReader); +impl RCB6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB6_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB6_A { + match self.bits { + false => RCB6_A::DIS, + true => RCB6_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB6_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB6_A::ENA + } +} +impl core::ops::Deref for RCB6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB6` writer - Remap Command Bit for Master 6"] +pub struct RCB6_W<'a> { + w: &'a mut W, +} +impl<'a> RCB6_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB6_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB6_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB6_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Remap Command Bit for Master 7\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB7_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB7_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB7` reader - Remap Command Bit for Master 7"] +pub struct RCB7_R(crate::FieldReader); +impl RCB7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB7_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB7_A { + match self.bits { + false => RCB7_A::DIS, + true => RCB7_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB7_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB7_A::ENA + } +} +impl core::ops::Deref for RCB7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB7` writer - Remap Command Bit for Master 7"] +pub struct RCB7_W<'a> { + w: &'a mut W, +} +impl<'a> RCB7_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB7_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB7_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB7_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Remap Command Bit for Master 8\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB8_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB8_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB8` reader - Remap Command Bit for Master 8"] +pub struct RCB8_R(crate::FieldReader); +impl RCB8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB8_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB8_A { + match self.bits { + false => RCB8_A::DIS, + true => RCB8_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB8_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB8_A::ENA + } +} +impl core::ops::Deref for RCB8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB8` writer - Remap Command Bit for Master 8"] +pub struct RCB8_W<'a> { + w: &'a mut W, +} +impl<'a> RCB8_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB8_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB8_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB8_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Remap Command Bit for Master 9\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB9_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB9_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB9` reader - Remap Command Bit for Master 9"] +pub struct RCB9_R(crate::FieldReader); +impl RCB9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB9_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB9_A { + match self.bits { + false => RCB9_A::DIS, + true => RCB9_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB9_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB9_A::ENA + } +} +impl core::ops::Deref for RCB9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB9` writer - Remap Command Bit for Master 9"] +pub struct RCB9_W<'a> { + w: &'a mut W, +} +impl<'a> RCB9_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB9_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB9_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB9_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Remap Command Bit for Master 10\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB10_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB10_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB10` reader - Remap Command Bit for Master 10"] +pub struct RCB10_R(crate::FieldReader); +impl RCB10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB10_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB10_A { + match self.bits { + false => RCB10_A::DIS, + true => RCB10_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB10_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB10_A::ENA + } +} +impl core::ops::Deref for RCB10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB10` writer - Remap Command Bit for Master 10"] +pub struct RCB10_W<'a> { + w: &'a mut W, +} +impl<'a> RCB10_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB10_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB10_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB10_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Remap Command Bit for Master 11\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB11_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB11_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB11` reader - Remap Command Bit for Master 11"] +pub struct RCB11_R(crate::FieldReader); +impl RCB11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB11_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB11_A { + match self.bits { + false => RCB11_A::DIS, + true => RCB11_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB11_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB11_A::ENA + } +} +impl core::ops::Deref for RCB11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB11` writer - Remap Command Bit for Master 11"] +pub struct RCB11_W<'a> { + w: &'a mut W, +} +impl<'a> RCB11_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB11_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB11_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB11_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Remap Command Bit for Master 12\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB12_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB12_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB12` reader - Remap Command Bit for Master 12"] +pub struct RCB12_R(crate::FieldReader); +impl RCB12_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB12_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB12_A { + match self.bits { + false => RCB12_A::DIS, + true => RCB12_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB12_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB12_A::ENA + } +} +impl core::ops::Deref for RCB12_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB12` writer - Remap Command Bit for Master 12"] +pub struct RCB12_W<'a> { + w: &'a mut W, +} +impl<'a> RCB12_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB12_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB12_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB12_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Remap Command Bit for Master 13\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB13_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB13_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB13` reader - Remap Command Bit for Master 13"] +pub struct RCB13_R(crate::FieldReader); +impl RCB13_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB13_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB13_A { + match self.bits { + false => RCB13_A::DIS, + true => RCB13_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB13_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB13_A::ENA + } +} +impl core::ops::Deref for RCB13_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB13` writer - Remap Command Bit for Master 13"] +pub struct RCB13_W<'a> { + w: &'a mut W, +} +impl<'a> RCB13_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB13_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB13_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB13_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Remap Command Bit for Master 14\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB14_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB14_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB14` reader - Remap Command Bit for Master 14"] +pub struct RCB14_R(crate::FieldReader); +impl RCB14_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB14_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB14_A { + match self.bits { + false => RCB14_A::DIS, + true => RCB14_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB14_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB14_A::ENA + } +} +impl core::ops::Deref for RCB14_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB14` writer - Remap Command Bit for Master 14"] +pub struct RCB14_W<'a> { + w: &'a mut W, +} +impl<'a> RCB14_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB14_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB14_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB14_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Remap Command Bit for Master 15\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB15_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB15_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB15` reader - Remap Command Bit for Master 15"] +pub struct RCB15_R(crate::FieldReader); +impl RCB15_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB15_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB15_A { + match self.bits { + false => RCB15_A::DIS, + true => RCB15_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB15_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB15_A::ENA + } +} +impl core::ops::Deref for RCB15_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB15` writer - Remap Command Bit for Master 15"] +pub struct RCB15_W<'a> { + w: &'a mut W, +} +impl<'a> RCB15_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB15_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB15_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB15_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Remap Command Bit for Master 0"] + #[inline(always)] + pub fn rcb0(&self) -> RCB0_R { + RCB0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Remap Command Bit for Master 1"] + #[inline(always)] + pub fn rcb1(&self) -> RCB1_R { + RCB1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Remap Command Bit for Master 2"] + #[inline(always)] + pub fn rcb2(&self) -> RCB2_R { + RCB2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Remap Command Bit for Master 3"] + #[inline(always)] + pub fn rcb3(&self) -> RCB3_R { + RCB3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Remap Command Bit for Master 4"] + #[inline(always)] + pub fn rcb4(&self) -> RCB4_R { + RCB4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Remap Command Bit for Master 5"] + #[inline(always)] + pub fn rcb5(&self) -> RCB5_R { + RCB5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Remap Command Bit for Master 6"] + #[inline(always)] + pub fn rcb6(&self) -> RCB6_R { + RCB6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Remap Command Bit for Master 7"] + #[inline(always)] + pub fn rcb7(&self) -> RCB7_R { + RCB7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Remap Command Bit for Master 8"] + #[inline(always)] + pub fn rcb8(&self) -> RCB8_R { + RCB8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Remap Command Bit for Master 9"] + #[inline(always)] + pub fn rcb9(&self) -> RCB9_R { + RCB9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Remap Command Bit for Master 10"] + #[inline(always)] + pub fn rcb10(&self) -> RCB10_R { + RCB10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Remap Command Bit for Master 11"] + #[inline(always)] + pub fn rcb11(&self) -> RCB11_R { + RCB11_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Remap Command Bit for Master 12"] + #[inline(always)] + pub fn rcb12(&self) -> RCB12_R { + RCB12_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Remap Command Bit for Master 13"] + #[inline(always)] + pub fn rcb13(&self) -> RCB13_R { + RCB13_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Remap Command Bit for Master 14"] + #[inline(always)] + pub fn rcb14(&self) -> RCB14_R { + RCB14_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Remap Command Bit for Master 15"] + #[inline(always)] + pub fn rcb15(&self) -> RCB15_R { + RCB15_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Remap Command Bit for Master 0"] + #[inline(always)] + pub fn rcb0(&mut self) -> RCB0_W { + RCB0_W { w: self } + } + #[doc = "Bit 1 - Remap Command Bit for Master 1"] + #[inline(always)] + pub fn rcb1(&mut self) -> RCB1_W { + RCB1_W { w: self } + } + #[doc = "Bit 2 - Remap Command Bit for Master 2"] + #[inline(always)] + pub fn rcb2(&mut self) -> RCB2_W { + RCB2_W { w: self } + } + #[doc = "Bit 3 - Remap Command Bit for Master 3"] + #[inline(always)] + pub fn rcb3(&mut self) -> RCB3_W { + RCB3_W { w: self } + } + #[doc = "Bit 4 - Remap Command Bit for Master 4"] + #[inline(always)] + pub fn rcb4(&mut self) -> RCB4_W { + RCB4_W { w: self } + } + #[doc = "Bit 5 - Remap Command Bit for Master 5"] + #[inline(always)] + pub fn rcb5(&mut self) -> RCB5_W { + RCB5_W { w: self } + } + #[doc = "Bit 6 - Remap Command Bit for Master 6"] + #[inline(always)] + pub fn rcb6(&mut self) -> RCB6_W { + RCB6_W { w: self } + } + #[doc = "Bit 7 - Remap Command Bit for Master 7"] + #[inline(always)] + pub fn rcb7(&mut self) -> RCB7_W { + RCB7_W { w: self } + } + #[doc = "Bit 8 - Remap Command Bit for Master 8"] + #[inline(always)] + pub fn rcb8(&mut self) -> RCB8_W { + RCB8_W { w: self } + } + #[doc = "Bit 9 - Remap Command Bit for Master 9"] + #[inline(always)] + pub fn rcb9(&mut self) -> RCB9_W { + RCB9_W { w: self } + } + #[doc = "Bit 10 - Remap Command Bit for Master 10"] + #[inline(always)] + pub fn rcb10(&mut self) -> RCB10_W { + RCB10_W { w: self } + } + #[doc = "Bit 11 - Remap Command Bit for Master 11"] + #[inline(always)] + pub fn rcb11(&mut self) -> RCB11_W { + RCB11_W { w: self } + } + #[doc = "Bit 12 - Remap Command Bit for Master 12"] + #[inline(always)] + pub fn rcb12(&mut self) -> RCB12_W { + RCB12_W { w: self } + } + #[doc = "Bit 13 - Remap Command Bit for Master 13"] + #[inline(always)] + pub fn rcb13(&mut self) -> RCB13_W { + RCB13_W { w: self } + } + #[doc = "Bit 14 - Remap Command Bit for Master 14"] + #[inline(always)] + pub fn rcb14(&mut self) -> RCB14_W { + RCB14_W { w: self } + } + #[doc = "Bit 15 - Remap Command Bit for Master 15"] + #[inline(always)] + pub fn rcb15(&mut self) -> RCB15_W { + RCB15_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Master Remap Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mrcr](index.html) module"] +pub struct MRCR_SPEC; +impl crate::RegisterSpec for MRCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [mrcr::R](R) reader structure"] +impl crate::Readable for MRCR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [mrcr::W](W) writer structure"] +impl crate::Writable for MRCR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets MRCR to value 0"] +impl crate::Resettable for MRCR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/hmatrixhs/prs.rs b/pac/atsamc21e/src/hmatrixhs/prs.rs new file mode 100644 index 000000000000..0313f3c4fc20 --- /dev/null +++ b/pac/atsamc21e/src/hmatrixhs/prs.rs @@ -0,0 +1,8 @@ +#[doc = "PRAS register accessor: an alias for `Reg`"] +pub type PRAS = crate::Reg; +#[doc = "Priority A for Slave"] +pub mod pras; +#[doc = "PRBS register accessor: an alias for `Reg`"] +pub type PRBS = crate::Reg; +#[doc = "Priority B for Slave"] +pub mod prbs; diff --git a/pac/atsamc21e/src/hmatrixhs/prs/pras.rs b/pac/atsamc21e/src/hmatrixhs/prs/pras.rs new file mode 100644 index 000000000000..ac4744a9e2a0 --- /dev/null +++ b/pac/atsamc21e/src/hmatrixhs/prs/pras.rs @@ -0,0 +1,362 @@ +#[doc = "Register `PRAS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PRAS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `M0PR` reader - Master 0 Priority"] +pub struct M0PR_R(crate::FieldReader); +impl M0PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M0PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M0PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M0PR` writer - Master 0 Priority"] +pub struct M0PR_W<'a> { + w: &'a mut W, +} +impl<'a> M0PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Field `M1PR` reader - Master 1 Priority"] +pub struct M1PR_R(crate::FieldReader); +impl M1PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M1PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M1PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M1PR` writer - Master 1 Priority"] +pub struct M1PR_W<'a> { + w: &'a mut W, +} +impl<'a> M1PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 4)) | ((value as u32 & 0x0f) << 4); + self.w + } +} +#[doc = "Field `M2PR` reader - Master 2 Priority"] +pub struct M2PR_R(crate::FieldReader); +impl M2PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M2PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M2PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M2PR` writer - Master 2 Priority"] +pub struct M2PR_W<'a> { + w: &'a mut W, +} +impl<'a> M2PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 8)) | ((value as u32 & 0x0f) << 8); + self.w + } +} +#[doc = "Field `M3PR` reader - Master 3 Priority"] +pub struct M3PR_R(crate::FieldReader); +impl M3PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M3PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M3PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M3PR` writer - Master 3 Priority"] +pub struct M3PR_W<'a> { + w: &'a mut W, +} +impl<'a> M3PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 12)) | ((value as u32 & 0x0f) << 12); + self.w + } +} +#[doc = "Field `M4PR` reader - Master 4 Priority"] +pub struct M4PR_R(crate::FieldReader); +impl M4PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M4PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M4PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M4PR` writer - Master 4 Priority"] +pub struct M4PR_W<'a> { + w: &'a mut W, +} +impl<'a> M4PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 16)) | ((value as u32 & 0x0f) << 16); + self.w + } +} +#[doc = "Field `M5PR` reader - Master 5 Priority"] +pub struct M5PR_R(crate::FieldReader); +impl M5PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M5PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M5PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M5PR` writer - Master 5 Priority"] +pub struct M5PR_W<'a> { + w: &'a mut W, +} +impl<'a> M5PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 20)) | ((value as u32 & 0x0f) << 20); + self.w + } +} +#[doc = "Field `M6PR` reader - Master 6 Priority"] +pub struct M6PR_R(crate::FieldReader); +impl M6PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M6PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M6PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M6PR` writer - Master 6 Priority"] +pub struct M6PR_W<'a> { + w: &'a mut W, +} +impl<'a> M6PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Field `M7PR` reader - Master 7 Priority"] +pub struct M7PR_R(crate::FieldReader); +impl M7PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M7PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M7PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M7PR` writer - Master 7 Priority"] +pub struct M7PR_W<'a> { + w: &'a mut W, +} +impl<'a> M7PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 28)) | ((value as u32 & 0x0f) << 28); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Master 0 Priority"] + #[inline(always)] + pub fn m0pr(&self) -> M0PR_R { + M0PR_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Master 1 Priority"] + #[inline(always)] + pub fn m1pr(&self) -> M1PR_R { + M1PR_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 8:11 - Master 2 Priority"] + #[inline(always)] + pub fn m2pr(&self) -> M2PR_R { + M2PR_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - Master 3 Priority"] + #[inline(always)] + pub fn m3pr(&self) -> M3PR_R { + M3PR_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:19 - Master 4 Priority"] + #[inline(always)] + pub fn m4pr(&self) -> M4PR_R { + M4PR_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bits 20:23 - Master 5 Priority"] + #[inline(always)] + pub fn m5pr(&self) -> M5PR_R { + M5PR_R::new(((self.bits >> 20) & 0x0f) as u8) + } + #[doc = "Bits 24:27 - Master 6 Priority"] + #[inline(always)] + pub fn m6pr(&self) -> M6PR_R { + M6PR_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bits 28:31 - Master 7 Priority"] + #[inline(always)] + pub fn m7pr(&self) -> M7PR_R { + M7PR_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Master 0 Priority"] + #[inline(always)] + pub fn m0pr(&mut self) -> M0PR_W { + M0PR_W { w: self } + } + #[doc = "Bits 4:7 - Master 1 Priority"] + #[inline(always)] + pub fn m1pr(&mut self) -> M1PR_W { + M1PR_W { w: self } + } + #[doc = "Bits 8:11 - Master 2 Priority"] + #[inline(always)] + pub fn m2pr(&mut self) -> M2PR_W { + M2PR_W { w: self } + } + #[doc = "Bits 12:15 - Master 3 Priority"] + #[inline(always)] + pub fn m3pr(&mut self) -> M3PR_W { + M3PR_W { w: self } + } + #[doc = "Bits 16:19 - Master 4 Priority"] + #[inline(always)] + pub fn m4pr(&mut self) -> M4PR_W { + M4PR_W { w: self } + } + #[doc = "Bits 20:23 - Master 5 Priority"] + #[inline(always)] + pub fn m5pr(&mut self) -> M5PR_W { + M5PR_W { w: self } + } + #[doc = "Bits 24:27 - Master 6 Priority"] + #[inline(always)] + pub fn m6pr(&mut self) -> M6PR_W { + M6PR_W { w: self } + } + #[doc = "Bits 28:31 - Master 7 Priority"] + #[inline(always)] + pub fn m7pr(&mut self) -> M7PR_W { + M7PR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Priority A for Slave\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pras](index.html) module"] +pub struct PRAS_SPEC; +impl crate::RegisterSpec for PRAS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pras::R](R) reader structure"] +impl crate::Readable for PRAS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [pras::W](W) writer structure"] +impl crate::Writable for PRAS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PRAS to value 0"] +impl crate::Resettable for PRAS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/hmatrixhs/prs/prbs.rs b/pac/atsamc21e/src/hmatrixhs/prs/prbs.rs new file mode 100644 index 000000000000..a2cc6bb9f6b0 --- /dev/null +++ b/pac/atsamc21e/src/hmatrixhs/prs/prbs.rs @@ -0,0 +1,362 @@ +#[doc = "Register `PRBS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PRBS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `M8PR` reader - Master 8 Priority"] +pub struct M8PR_R(crate::FieldReader); +impl M8PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M8PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M8PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M8PR` writer - Master 8 Priority"] +pub struct M8PR_W<'a> { + w: &'a mut W, +} +impl<'a> M8PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Field `M9PR` reader - Master 9 Priority"] +pub struct M9PR_R(crate::FieldReader); +impl M9PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M9PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M9PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M9PR` writer - Master 9 Priority"] +pub struct M9PR_W<'a> { + w: &'a mut W, +} +impl<'a> M9PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 4)) | ((value as u32 & 0x0f) << 4); + self.w + } +} +#[doc = "Field `M10PR` reader - Master 10 Priority"] +pub struct M10PR_R(crate::FieldReader); +impl M10PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M10PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M10PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M10PR` writer - Master 10 Priority"] +pub struct M10PR_W<'a> { + w: &'a mut W, +} +impl<'a> M10PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 8)) | ((value as u32 & 0x0f) << 8); + self.w + } +} +#[doc = "Field `M11PR` reader - Master 11 Priority"] +pub struct M11PR_R(crate::FieldReader); +impl M11PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M11PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M11PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M11PR` writer - Master 11 Priority"] +pub struct M11PR_W<'a> { + w: &'a mut W, +} +impl<'a> M11PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 12)) | ((value as u32 & 0x0f) << 12); + self.w + } +} +#[doc = "Field `M12PR` reader - Master 12 Priority"] +pub struct M12PR_R(crate::FieldReader); +impl M12PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M12PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M12PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M12PR` writer - Master 12 Priority"] +pub struct M12PR_W<'a> { + w: &'a mut W, +} +impl<'a> M12PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 16)) | ((value as u32 & 0x0f) << 16); + self.w + } +} +#[doc = "Field `M13PR` reader - Master 13 Priority"] +pub struct M13PR_R(crate::FieldReader); +impl M13PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M13PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M13PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M13PR` writer - Master 13 Priority"] +pub struct M13PR_W<'a> { + w: &'a mut W, +} +impl<'a> M13PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 20)) | ((value as u32 & 0x0f) << 20); + self.w + } +} +#[doc = "Field `M14PR` reader - Master 14 Priority"] +pub struct M14PR_R(crate::FieldReader); +impl M14PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M14PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M14PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M14PR` writer - Master 14 Priority"] +pub struct M14PR_W<'a> { + w: &'a mut W, +} +impl<'a> M14PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Field `M15PR` reader - Master 15 Priority"] +pub struct M15PR_R(crate::FieldReader); +impl M15PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M15PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M15PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M15PR` writer - Master 15 Priority"] +pub struct M15PR_W<'a> { + w: &'a mut W, +} +impl<'a> M15PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 28)) | ((value as u32 & 0x0f) << 28); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Master 8 Priority"] + #[inline(always)] + pub fn m8pr(&self) -> M8PR_R { + M8PR_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Master 9 Priority"] + #[inline(always)] + pub fn m9pr(&self) -> M9PR_R { + M9PR_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 8:11 - Master 10 Priority"] + #[inline(always)] + pub fn m10pr(&self) -> M10PR_R { + M10PR_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - Master 11 Priority"] + #[inline(always)] + pub fn m11pr(&self) -> M11PR_R { + M11PR_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:19 - Master 12 Priority"] + #[inline(always)] + pub fn m12pr(&self) -> M12PR_R { + M12PR_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bits 20:23 - Master 13 Priority"] + #[inline(always)] + pub fn m13pr(&self) -> M13PR_R { + M13PR_R::new(((self.bits >> 20) & 0x0f) as u8) + } + #[doc = "Bits 24:27 - Master 14 Priority"] + #[inline(always)] + pub fn m14pr(&self) -> M14PR_R { + M14PR_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bits 28:31 - Master 15 Priority"] + #[inline(always)] + pub fn m15pr(&self) -> M15PR_R { + M15PR_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Master 8 Priority"] + #[inline(always)] + pub fn m8pr(&mut self) -> M8PR_W { + M8PR_W { w: self } + } + #[doc = "Bits 4:7 - Master 9 Priority"] + #[inline(always)] + pub fn m9pr(&mut self) -> M9PR_W { + M9PR_W { w: self } + } + #[doc = "Bits 8:11 - Master 10 Priority"] + #[inline(always)] + pub fn m10pr(&mut self) -> M10PR_W { + M10PR_W { w: self } + } + #[doc = "Bits 12:15 - Master 11 Priority"] + #[inline(always)] + pub fn m11pr(&mut self) -> M11PR_W { + M11PR_W { w: self } + } + #[doc = "Bits 16:19 - Master 12 Priority"] + #[inline(always)] + pub fn m12pr(&mut self) -> M12PR_W { + M12PR_W { w: self } + } + #[doc = "Bits 20:23 - Master 13 Priority"] + #[inline(always)] + pub fn m13pr(&mut self) -> M13PR_W { + M13PR_W { w: self } + } + #[doc = "Bits 24:27 - Master 14 Priority"] + #[inline(always)] + pub fn m14pr(&mut self) -> M14PR_W { + M14PR_W { w: self } + } + #[doc = "Bits 28:31 - Master 15 Priority"] + #[inline(always)] + pub fn m15pr(&mut self) -> M15PR_W { + M15PR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Priority B for Slave\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [prbs](index.html) module"] +pub struct PRBS_SPEC; +impl crate::RegisterSpec for PRBS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [prbs::R](R) reader structure"] +impl crate::Readable for PRBS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [prbs::W](W) writer structure"] +impl crate::Writable for PRBS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PRBS to value 0"] +impl crate::Resettable for PRBS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/hmatrixhs/scfg.rs b/pac/atsamc21e/src/hmatrixhs/scfg.rs new file mode 100644 index 000000000000..7180c043195a --- /dev/null +++ b/pac/atsamc21e/src/hmatrixhs/scfg.rs @@ -0,0 +1,334 @@ +#[doc = "Register `SCFG[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SCFG[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SLOT_CYCLE` reader - Maximum Number of Allowed Cycles for a Burst"] +pub struct SLOT_CYCLE_R(crate::FieldReader); +impl SLOT_CYCLE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SLOT_CYCLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SLOT_CYCLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLOT_CYCLE` writer - Maximum Number of Allowed Cycles for a Burst"] +pub struct SLOT_CYCLE_W<'a> { + w: &'a mut W, +} +impl<'a> SLOT_CYCLE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +#[doc = "Default Master Type\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DEFMSTR_TYPE_A { + #[doc = "0: No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst."] + NO_DEFAULT = 0, + #[doc = "1: Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave."] + LAST_DEFAULT = 1, + #[doc = "2: Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave."] + FIXED_DEFAULT = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DEFMSTR_TYPE_A) -> Self { + variant as _ + } +} +#[doc = "Field `DEFMSTR_TYPE` reader - Default Master Type"] +pub struct DEFMSTR_TYPE_R(crate::FieldReader); +impl DEFMSTR_TYPE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DEFMSTR_TYPE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(DEFMSTR_TYPE_A::NO_DEFAULT), + 1 => Some(DEFMSTR_TYPE_A::LAST_DEFAULT), + 2 => Some(DEFMSTR_TYPE_A::FIXED_DEFAULT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NO_DEFAULT`"] + #[inline(always)] + pub fn is_no_default(&self) -> bool { + **self == DEFMSTR_TYPE_A::NO_DEFAULT + } + #[doc = "Checks if the value of the field is `LAST_DEFAULT`"] + #[inline(always)] + pub fn is_last_default(&self) -> bool { + **self == DEFMSTR_TYPE_A::LAST_DEFAULT + } + #[doc = "Checks if the value of the field is `FIXED_DEFAULT`"] + #[inline(always)] + pub fn is_fixed_default(&self) -> bool { + **self == DEFMSTR_TYPE_A::FIXED_DEFAULT + } +} +impl core::ops::Deref for DEFMSTR_TYPE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DEFMSTR_TYPE` writer - Default Master Type"] +pub struct DEFMSTR_TYPE_W<'a> { + w: &'a mut W, +} +impl<'a> DEFMSTR_TYPE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DEFMSTR_TYPE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst."] + #[inline(always)] + pub fn no_default(self) -> &'a mut W { + self.variant(DEFMSTR_TYPE_A::NO_DEFAULT) + } + #[doc = "Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave."] + #[inline(always)] + pub fn last_default(self) -> &'a mut W { + self.variant(DEFMSTR_TYPE_A::LAST_DEFAULT) + } + #[doc = "Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave."] + #[inline(always)] + pub fn fixed_default(self) -> &'a mut W { + self.variant(DEFMSTR_TYPE_A::FIXED_DEFAULT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Field `FIXED_DEFMSTR` reader - Fixed Index of Default Master"] +pub struct FIXED_DEFMSTR_R(crate::FieldReader); +impl FIXED_DEFMSTR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FIXED_DEFMSTR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FIXED_DEFMSTR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FIXED_DEFMSTR` writer - Fixed Index of Default Master"] +pub struct FIXED_DEFMSTR_W<'a> { + w: &'a mut W, +} +impl<'a> FIXED_DEFMSTR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 18)) | ((value as u32 & 0x0f) << 18); + self.w + } +} +#[doc = "Arbitration Type\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ARBT_A { + #[doc = "0: Round-Robin Arbitration"] + ROUND_ROBIN = 0, + #[doc = "1: Fixed Priority Arbitration"] + FIXED_PRIORITY = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ARBT_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ARBT` reader - Arbitration Type"] +pub struct ARBT_R(crate::FieldReader); +impl ARBT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ARBT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ARBT_A { + match self.bits { + false => ARBT_A::ROUND_ROBIN, + true => ARBT_A::FIXED_PRIORITY, + } + } + #[doc = "Checks if the value of the field is `ROUND_ROBIN`"] + #[inline(always)] + pub fn is_round_robin(&self) -> bool { + **self == ARBT_A::ROUND_ROBIN + } + #[doc = "Checks if the value of the field is `FIXED_PRIORITY`"] + #[inline(always)] + pub fn is_fixed_priority(&self) -> bool { + **self == ARBT_A::FIXED_PRIORITY + } +} +impl core::ops::Deref for ARBT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ARBT` writer - Arbitration Type"] +pub struct ARBT_W<'a> { + w: &'a mut W, +} +impl<'a> ARBT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: ARBT_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Round-Robin Arbitration"] + #[inline(always)] + pub fn round_robin(self) -> &'a mut W { + self.variant(ARBT_A::ROUND_ROBIN) + } + #[doc = "Fixed Priority Arbitration"] + #[inline(always)] + pub fn fixed_priority(self) -> &'a mut W { + self.variant(ARBT_A::FIXED_PRIORITY) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Maximum Number of Allowed Cycles for a Burst"] + #[inline(always)] + pub fn slot_cycle(&self) -> SLOT_CYCLE_R { + SLOT_CYCLE_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 16:17 - Default Master Type"] + #[inline(always)] + pub fn defmstr_type(&self) -> DEFMSTR_TYPE_R { + DEFMSTR_TYPE_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bits 18:21 - Fixed Index of Default Master"] + #[inline(always)] + pub fn fixed_defmstr(&self) -> FIXED_DEFMSTR_R { + FIXED_DEFMSTR_R::new(((self.bits >> 18) & 0x0f) as u8) + } + #[doc = "Bit 24 - Arbitration Type"] + #[inline(always)] + pub fn arbt(&self) -> ARBT_R { + ARBT_R::new(((self.bits >> 24) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - Maximum Number of Allowed Cycles for a Burst"] + #[inline(always)] + pub fn slot_cycle(&mut self) -> SLOT_CYCLE_W { + SLOT_CYCLE_W { w: self } + } + #[doc = "Bits 16:17 - Default Master Type"] + #[inline(always)] + pub fn defmstr_type(&mut self) -> DEFMSTR_TYPE_W { + DEFMSTR_TYPE_W { w: self } + } + #[doc = "Bits 18:21 - Fixed Index of Default Master"] + #[inline(always)] + pub fn fixed_defmstr(&mut self) -> FIXED_DEFMSTR_W { + FIXED_DEFMSTR_W { w: self } + } + #[doc = "Bit 24 - Arbitration Type"] + #[inline(always)] + pub fn arbt(&mut self) -> ARBT_W { + ARBT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Slave Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [scfg](index.html) module"] +pub struct SCFG_SPEC; +impl crate::RegisterSpec for SCFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [scfg::R](R) reader structure"] +impl crate::Readable for SCFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [scfg::W](W) writer structure"] +impl crate::Writable for SCFG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SCFG[%s] +to value 0x10"] +impl crate::Resettable for SCFG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x10 + } +} diff --git a/pac/atsamc21e/src/hmatrixhs/sfr.rs b/pac/atsamc21e/src/hmatrixhs/sfr.rs new file mode 100644 index 000000000000..0a7e024f73c8 --- /dev/null +++ b/pac/atsamc21e/src/hmatrixhs/sfr.rs @@ -0,0 +1,104 @@ +#[doc = "Register `SFR[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SFR[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SFR` reader - Special Function Register"] +pub struct SFR_R(crate::FieldReader); +impl SFR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + SFR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SFR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SFR` writer - Special Function Register"] +pub struct SFR_W<'a> { + w: &'a mut W, +} +impl<'a> SFR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Special Function Register"] + #[inline(always)] + pub fn sfr(&self) -> SFR_R { + SFR_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Special Function Register"] + #[inline(always)] + pub fn sfr(&mut self) -> SFR_W { + SFR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Special Function\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sfr](index.html) module"] +pub struct SFR_SPEC; +impl crate::RegisterSpec for SFR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [sfr::R](R) reader structure"] +impl crate::Readable for SFR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [sfr::W](W) writer structure"] +impl crate::Writable for SFR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SFR[%s] +to value 0"] +impl crate::Resettable for SFR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/lib.rs b/pac/atsamc21e/src/lib.rs new file mode 100644 index 000000000000..ffb1e5db2324 --- /dev/null +++ b/pac/atsamc21e/src/lib.rs @@ -0,0 +1,1617 @@ +#![doc = "Peripheral access API for ATSAMC21E microcontrollers (generated using svd2rust v0.20.0 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] +svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.20.0/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"] +#![deny(const_err)] +#![deny(dead_code)] +#![deny(improper_ctypes)] +#![deny(missing_docs)] +#![deny(no_mangle_generic_items)] +#![deny(non_shorthand_field_patterns)] +#![deny(overflowing_literals)] +#![deny(path_statements)] +#![deny(patterns_in_fns_without_body)] +#![deny(private_in_public)] +#![deny(unconditional_recursion)] +#![deny(unused_allocation)] +#![deny(unused_comparisons)] +#![deny(unused_parens)] +#![deny(while_true)] +#![allow(non_camel_case_types)] +#![allow(non_snake_case)] +#![allow(clippy::all)] +#![no_std] +use core::marker::PhantomData; +use core::ops::Deref; +#[doc = r"Number available in the NVIC for configuring priority"] +pub const NVIC_PRIO_BITS: u8 = 2; +#[cfg(feature = "rt")] +pub use self::Interrupt as interrupt; +pub use cortex_m::peripheral::Peripherals as CorePeripherals; +pub use cortex_m::peripheral::{CBP, CPUID, DCB, DWT, FPB, ITM, MPU, NVIC, SCB, SYST, TPIU}; +#[cfg(feature = "rt")] +pub use cortex_m_rt::interrupt; +#[allow(unused_imports)] +use generic::*; +#[doc = r"Common register and bit access and modify traits"] +pub mod generic; +#[cfg(feature = "rt")] +extern "C" { + fn WDT(); + fn RTC(); + fn EIC(); + fn FREQM(); + fn TSENS(); + fn NVMCTRL(); + fn DMAC(); + fn EVSYS(); + fn SERCOM0(); + fn SERCOM1(); + fn SERCOM2(); + fn SERCOM3(); + fn CAN0(); + fn TCC0(); + fn TCC1(); + fn TCC2(); + fn TC0(); + fn TC1(); + fn TC2(); + fn TC3(); + fn TC4(); + fn ADC0(); + fn ADC1(); + fn AC(); + fn DAC(); + fn SDADC(); + fn PTC(); +} +#[doc(hidden)] +pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, +} +#[cfg(feature = "rt")] +#[doc(hidden)] +#[link_section = ".vector_table.interrupts"] +#[no_mangle] +pub static __INTERRUPTS: [Vector; 31] = [ + Vector { _reserved: 0 }, + Vector { _handler: WDT }, + Vector { _handler: RTC }, + Vector { _handler: EIC }, + Vector { _handler: FREQM }, + Vector { _handler: TSENS }, + Vector { _handler: NVMCTRL }, + Vector { _handler: DMAC }, + Vector { _handler: EVSYS }, + Vector { _handler: SERCOM0 }, + Vector { _handler: SERCOM1 }, + Vector { _handler: SERCOM2 }, + Vector { _handler: SERCOM3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: CAN0 }, + Vector { _reserved: 0 }, + Vector { _handler: TCC0 }, + Vector { _handler: TCC1 }, + Vector { _handler: TCC2 }, + Vector { _handler: TC0 }, + Vector { _handler: TC1 }, + Vector { _handler: TC2 }, + Vector { _handler: TC3 }, + Vector { _handler: TC4 }, + Vector { _handler: ADC0 }, + Vector { _handler: ADC1 }, + Vector { _handler: AC }, + Vector { _handler: DAC }, + Vector { _handler: SDADC }, + Vector { _handler: PTC }, +]; +#[doc = r"Enumeration of all the interrupts."] +#[derive(Copy, Clone, Debug, PartialEq, Eq)] +#[repr(u16)] +pub enum Interrupt { + #[doc = "1 - WDT"] + WDT = 1, + #[doc = "2 - RTC"] + RTC = 2, + #[doc = "3 - EIC"] + EIC = 3, + #[doc = "4 - FREQM"] + FREQM = 4, + #[doc = "5 - TSENS"] + TSENS = 5, + #[doc = "6 - NVMCTRL"] + NVMCTRL = 6, + #[doc = "7 - DMAC"] + DMAC = 7, + #[doc = "8 - EVSYS"] + EVSYS = 8, + #[doc = "9 - SERCOM0"] + SERCOM0 = 9, + #[doc = "10 - SERCOM1"] + SERCOM1 = 10, + #[doc = "11 - SERCOM2"] + SERCOM2 = 11, + #[doc = "12 - SERCOM3"] + SERCOM3 = 12, + #[doc = "15 - CAN0"] + CAN0 = 15, + #[doc = "17 - TCC0"] + TCC0 = 17, + #[doc = "18 - TCC1"] + TCC1 = 18, + #[doc = "19 - TCC2"] + TCC2 = 19, + #[doc = "20 - TC0"] + TC0 = 20, + #[doc = "21 - TC1"] + TC1 = 21, + #[doc = "22 - TC2"] + TC2 = 22, + #[doc = "23 - TC3"] + TC3 = 23, + #[doc = "24 - TC4"] + TC4 = 24, + #[doc = "25 - ADC0"] + ADC0 = 25, + #[doc = "26 - ADC1"] + ADC1 = 26, + #[doc = "27 - AC"] + AC = 27, + #[doc = "28 - DAC"] + DAC = 28, + #[doc = "29 - SDADC"] + SDADC = 29, + #[doc = "30 - PTC"] + PTC = 30, +} +unsafe impl cortex_m::interrupt::InterruptNumber for Interrupt { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } +} +#[doc = "Analog Comparators"] +pub struct AC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for AC {} +impl AC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const ac::RegisterBlock = 0x4200_5000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const ac::RegisterBlock { + Self::PTR + } +} +impl Deref for AC { + type Target = ac::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for AC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AC").finish() + } +} +#[doc = "Analog Comparators"] +pub mod ac; +#[doc = "Analog Digital Converter"] +pub struct ADC0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for ADC0 {} +impl ADC0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const adc0::RegisterBlock = 0x4200_4400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const adc0::RegisterBlock { + Self::PTR + } +} +impl Deref for ADC0 { + type Target = adc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for ADC0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ADC0").finish() + } +} +#[doc = "Analog Digital Converter"] +pub mod adc0; +#[doc = "Analog Digital Converter"] +pub struct ADC1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for ADC1 {} +impl ADC1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const adc0::RegisterBlock = 0x4200_4800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const adc0::RegisterBlock { + Self::PTR + } +} +impl Deref for ADC1 { + type Target = adc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for ADC1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ADC1").finish() + } +} +#[doc = "Analog Digital Converter"] +pub use adc0 as adc1; +#[doc = "Control Area Network"] +pub struct CAN0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for CAN0 {} +impl CAN0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const can0::RegisterBlock = 0x4200_1c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const can0::RegisterBlock { + Self::PTR + } +} +impl Deref for CAN0 { + type Target = can0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for CAN0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CAN0").finish() + } +} +#[doc = "Control Area Network"] +pub mod can0; +#[doc = "Configurable Custom Logic"] +pub struct CCL { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for CCL {} +impl CCL { + #[doc = r"Pointer to the register block"] + pub const PTR: *const ccl::RegisterBlock = 0x4200_5c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const ccl::RegisterBlock { + Self::PTR + } +} +impl Deref for CCL { + type Target = ccl::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for CCL { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CCL").finish() + } +} +#[doc = "Configurable Custom Logic"] +pub mod ccl; +#[doc = "Digital Analog Converter"] +pub struct DAC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for DAC {} +impl DAC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const dac::RegisterBlock = 0x4200_5400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const dac::RegisterBlock { + Self::PTR + } +} +impl Deref for DAC { + type Target = dac::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for DAC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DAC").finish() + } +} +#[doc = "Digital Analog Converter"] +pub mod dac; +#[doc = "Divide and Square Root Accelerator"] +pub struct DIVAS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for DIVAS {} +impl DIVAS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const divas::RegisterBlock = 0x4800_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const divas::RegisterBlock { + Self::PTR + } +} +impl Deref for DIVAS { + type Target = divas::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for DIVAS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DIVAS").finish() + } +} +#[doc = "Divide and Square Root Accelerator"] +pub mod divas; +#[doc = "Direct Memory Access Controller"] +pub struct DMAC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for DMAC {} +impl DMAC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const dmac::RegisterBlock = 0x4100_6000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const dmac::RegisterBlock { + Self::PTR + } +} +impl Deref for DMAC { + type Target = dmac::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for DMAC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DMAC").finish() + } +} +#[doc = "Direct Memory Access Controller"] +pub mod dmac; +#[doc = "Device Service Unit"] +pub struct DSU { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for DSU {} +impl DSU { + #[doc = r"Pointer to the register block"] + pub const PTR: *const dsu::RegisterBlock = 0x4100_2000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const dsu::RegisterBlock { + Self::PTR + } +} +impl Deref for DSU { + type Target = dsu::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for DSU { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DSU").finish() + } +} +#[doc = "Device Service Unit"] +pub mod dsu; +#[doc = "External Interrupt Controller"] +pub struct EIC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for EIC {} +impl EIC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const eic::RegisterBlock = 0x4000_2800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const eic::RegisterBlock { + Self::PTR + } +} +impl Deref for EIC { + type Target = eic::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for EIC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EIC").finish() + } +} +#[doc = "External Interrupt Controller"] +pub mod eic; +#[doc = "Event System Interface"] +pub struct EVSYS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for EVSYS {} +impl EVSYS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const evsys::RegisterBlock = 0x4200_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const evsys::RegisterBlock { + Self::PTR + } +} +impl Deref for EVSYS { + type Target = evsys::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for EVSYS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EVSYS").finish() + } +} +#[doc = "Event System Interface"] +pub mod evsys; +#[doc = "Frequency Meter"] +pub struct FREQM { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for FREQM {} +impl FREQM { + #[doc = r"Pointer to the register block"] + pub const PTR: *const freqm::RegisterBlock = 0x4000_2c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const freqm::RegisterBlock { + Self::PTR + } +} +impl Deref for FREQM { + type Target = freqm::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for FREQM { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FREQM").finish() + } +} +#[doc = "Frequency Meter"] +pub mod freqm; +#[doc = "Generic Clock Generator"] +pub struct GCLK { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for GCLK {} +impl GCLK { + #[doc = r"Pointer to the register block"] + pub const PTR: *const gclk::RegisterBlock = 0x4000_1c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const gclk::RegisterBlock { + Self::PTR + } +} +impl Deref for GCLK { + type Target = gclk::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for GCLK { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GCLK").finish() + } +} +#[doc = "Generic Clock Generator"] +pub mod gclk; +#[doc = "HSB Matrix"] +pub struct HMATRIXHS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for HMATRIXHS {} +impl HMATRIXHS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const hmatrixhs::RegisterBlock = 0x4100_a000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const hmatrixhs::RegisterBlock { + Self::PTR + } +} +impl Deref for HMATRIXHS { + type Target = hmatrixhs::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for HMATRIXHS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HMATRIXHS").finish() + } +} +#[doc = "HSB Matrix"] +pub mod hmatrixhs; +#[doc = "Main Clock"] +pub struct MCLK { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for MCLK {} +impl MCLK { + #[doc = r"Pointer to the register block"] + pub const PTR: *const mclk::RegisterBlock = 0x4000_0800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const mclk::RegisterBlock { + Self::PTR + } +} +impl Deref for MCLK { + type Target = mclk::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for MCLK { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MCLK").finish() + } +} +#[doc = "Main Clock"] +pub mod mclk; +#[doc = "Cortex-M0+ Micro-Trace Buffer"] +pub struct MTB { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for MTB {} +impl MTB { + #[doc = r"Pointer to the register block"] + pub const PTR: *const mtb::RegisterBlock = 0x4100_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const mtb::RegisterBlock { + Self::PTR + } +} +impl Deref for MTB { + type Target = mtb::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for MTB { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MTB").finish() + } +} +#[doc = "Cortex-M0+ Micro-Trace Buffer"] +pub mod mtb; +#[doc = "Non-Volatile Memory Controller"] +pub struct NVMCTRL { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for NVMCTRL {} +impl NVMCTRL { + #[doc = r"Pointer to the register block"] + pub const PTR: *const nvmctrl::RegisterBlock = 0x4100_4000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const nvmctrl::RegisterBlock { + Self::PTR + } +} +impl Deref for NVMCTRL { + type Target = nvmctrl::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for NVMCTRL { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("NVMCTRL").finish() + } +} +#[doc = "Non-Volatile Memory Controller"] +pub mod nvmctrl; +#[doc = "Oscillators Control"] +pub struct OSCCTRL { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for OSCCTRL {} +impl OSCCTRL { + #[doc = r"Pointer to the register block"] + pub const PTR: *const oscctrl::RegisterBlock = 0x4000_1000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const oscctrl::RegisterBlock { + Self::PTR + } +} +impl Deref for OSCCTRL { + type Target = oscctrl::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for OSCCTRL { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OSCCTRL").finish() + } +} +#[doc = "Oscillators Control"] +pub mod oscctrl; +#[doc = "32k Oscillators Control"] +pub struct OSC32KCTRL { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for OSC32KCTRL {} +impl OSC32KCTRL { + #[doc = r"Pointer to the register block"] + pub const PTR: *const osc32kctrl::RegisterBlock = 0x4000_1400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const osc32kctrl::RegisterBlock { + Self::PTR + } +} +impl Deref for OSC32KCTRL { + type Target = osc32kctrl::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for OSC32KCTRL { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OSC32KCTRL").finish() + } +} +#[doc = "32k Oscillators Control"] +pub mod osc32kctrl; +#[doc = "Peripheral Access Controller"] +pub struct PAC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PAC {} +impl PAC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const pac::RegisterBlock = 0x4000_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const pac::RegisterBlock { + Self::PTR + } +} +impl Deref for PAC { + type Target = pac::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PAC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PAC").finish() + } +} +#[doc = "Peripheral Access Controller"] +pub mod pac; +#[doc = "Power Manager"] +pub struct PM { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PM {} +impl PM { + #[doc = r"Pointer to the register block"] + pub const PTR: *const pm::RegisterBlock = 0x4000_0400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const pm::RegisterBlock { + Self::PTR + } +} +impl Deref for PM { + type Target = pm::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PM { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PM").finish() + } +} +#[doc = "Power Manager"] +pub mod pm; +#[doc = "Port Module"] +pub struct PORT { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PORT {} +impl PORT { + #[doc = r"Pointer to the register block"] + pub const PTR: *const port::RegisterBlock = 0x4100_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const port::RegisterBlock { + Self::PTR + } +} +impl Deref for PORT { + type Target = port::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PORT { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PORT").finish() + } +} +#[doc = "Port Module"] +pub mod port; +#[doc = "Port Module"] +pub struct PORT_IOBUS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PORT_IOBUS {} +impl PORT_IOBUS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const port::RegisterBlock = 0x6000_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const port::RegisterBlock { + Self::PTR + } +} +impl Deref for PORT_IOBUS { + type Target = port::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PORT_IOBUS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PORT_IOBUS").finish() + } +} +#[doc = "Port Module"] +pub use port as port_iobus; +#[doc = "Reset Controller"] +pub struct RSTC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for RSTC {} +impl RSTC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const rstc::RegisterBlock = 0x4000_0c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const rstc::RegisterBlock { + Self::PTR + } +} +impl Deref for RSTC { + type Target = rstc::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for RSTC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RSTC").finish() + } +} +#[doc = "Reset Controller"] +pub mod rstc; +#[doc = "Real-Time Counter"] +pub struct RTC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for RTC {} +impl RTC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const rtc::RegisterBlock = 0x4000_2400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const rtc::RegisterBlock { + Self::PTR + } +} +impl Deref for RTC { + type Target = rtc::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for RTC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RTC").finish() + } +} +#[doc = "Real-Time Counter"] +pub mod rtc; +#[doc = "Sigma-Delta Analog Digital Converter"] +pub struct SDADC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SDADC {} +impl SDADC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sdadc::RegisterBlock = 0x4200_4c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sdadc::RegisterBlock { + Self::PTR + } +} +impl Deref for SDADC { + type Target = sdadc::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SDADC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SDADC").finish() + } +} +#[doc = "Sigma-Delta Analog Digital Converter"] +pub mod sdadc; +#[doc = "Serial Communication Interface"] +pub struct SERCOM0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SERCOM0 {} +impl SERCOM0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sercom0::RegisterBlock = 0x4200_0400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sercom0::RegisterBlock { + Self::PTR + } +} +impl Deref for SERCOM0 { + type Target = sercom0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SERCOM0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SERCOM0").finish() + } +} +#[doc = "Serial Communication Interface"] +pub mod sercom0; +#[doc = "Serial Communication Interface"] +pub struct SERCOM1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SERCOM1 {} +impl SERCOM1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sercom0::RegisterBlock = 0x4200_0800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sercom0::RegisterBlock { + Self::PTR + } +} +impl Deref for SERCOM1 { + type Target = sercom0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SERCOM1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SERCOM1").finish() + } +} +#[doc = "Serial Communication Interface"] +pub use sercom0 as sercom1; +#[doc = "Serial Communication Interface"] +pub struct SERCOM2 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SERCOM2 {} +impl SERCOM2 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sercom0::RegisterBlock = 0x4200_0c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sercom0::RegisterBlock { + Self::PTR + } +} +impl Deref for SERCOM2 { + type Target = sercom0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SERCOM2 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SERCOM2").finish() + } +} +#[doc = "Serial Communication Interface"] +pub use sercom0 as sercom2; +#[doc = "Serial Communication Interface"] +pub struct SERCOM3 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SERCOM3 {} +impl SERCOM3 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sercom0::RegisterBlock = 0x4200_1000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sercom0::RegisterBlock { + Self::PTR + } +} +impl Deref for SERCOM3 { + type Target = sercom0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SERCOM3 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SERCOM3").finish() + } +} +#[doc = "Serial Communication Interface"] +pub use sercom0 as sercom3; +#[doc = "Supply Controller"] +pub struct SUPC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SUPC {} +impl SUPC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const supc::RegisterBlock = 0x4000_1800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const supc::RegisterBlock { + Self::PTR + } +} +impl Deref for SUPC { + type Target = supc::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SUPC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SUPC").finish() + } +} +#[doc = "Supply Controller"] +pub mod supc; +#[doc = "Basic Timer Counter"] +pub struct TC0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TC0 {} +impl TC0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tc0::RegisterBlock = 0x4200_3000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tc0::RegisterBlock { + Self::PTR + } +} +impl Deref for TC0 { + type Target = tc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TC0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TC0").finish() + } +} +#[doc = "Basic Timer Counter"] +pub mod tc0; +#[doc = "Basic Timer Counter"] +pub struct TC1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TC1 {} +impl TC1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tc0::RegisterBlock = 0x4200_3400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tc0::RegisterBlock { + Self::PTR + } +} +impl Deref for TC1 { + type Target = tc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TC1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TC1").finish() + } +} +#[doc = "Basic Timer Counter"] +pub use tc0 as tc1; +#[doc = "Basic Timer Counter"] +pub struct TC2 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TC2 {} +impl TC2 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tc0::RegisterBlock = 0x4200_3800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tc0::RegisterBlock { + Self::PTR + } +} +impl Deref for TC2 { + type Target = tc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TC2 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TC2").finish() + } +} +#[doc = "Basic Timer Counter"] +pub use tc0 as tc2; +#[doc = "Basic Timer Counter"] +pub struct TC3 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TC3 {} +impl TC3 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tc0::RegisterBlock = 0x4200_3c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tc0::RegisterBlock { + Self::PTR + } +} +impl Deref for TC3 { + type Target = tc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TC3 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TC3").finish() + } +} +#[doc = "Basic Timer Counter"] +pub use tc0 as tc3; +#[doc = "Basic Timer Counter"] +pub struct TC4 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TC4 {} +impl TC4 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tc0::RegisterBlock = 0x4200_4000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tc0::RegisterBlock { + Self::PTR + } +} +impl Deref for TC4 { + type Target = tc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TC4 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TC4").finish() + } +} +#[doc = "Basic Timer Counter"] +pub use tc0 as tc4; +#[doc = "Timer Counter Control"] +pub struct TCC0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TCC0 {} +impl TCC0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tcc0::RegisterBlock = 0x4200_2400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tcc0::RegisterBlock { + Self::PTR + } +} +impl Deref for TCC0 { + type Target = tcc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TCC0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TCC0").finish() + } +} +#[doc = "Timer Counter Control"] +pub mod tcc0; +#[doc = "Timer Counter Control"] +pub struct TCC1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TCC1 {} +impl TCC1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tcc0::RegisterBlock = 0x4200_2800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tcc0::RegisterBlock { + Self::PTR + } +} +impl Deref for TCC1 { + type Target = tcc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TCC1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TCC1").finish() + } +} +#[doc = "Timer Counter Control"] +pub use tcc0 as tcc1; +#[doc = "Timer Counter Control"] +pub struct TCC2 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TCC2 {} +impl TCC2 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tcc0::RegisterBlock = 0x4200_2c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tcc0::RegisterBlock { + Self::PTR + } +} +impl Deref for TCC2 { + type Target = tcc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TCC2 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TCC2").finish() + } +} +#[doc = "Timer Counter Control"] +pub use tcc0 as tcc2; +#[doc = "Temperature Sensor"] +pub struct TSENS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TSENS {} +impl TSENS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tsens::RegisterBlock = 0x4000_3000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tsens::RegisterBlock { + Self::PTR + } +} +impl Deref for TSENS { + type Target = tsens::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TSENS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TSENS").finish() + } +} +#[doc = "Temperature Sensor"] +pub mod tsens; +#[doc = "Watchdog Timer"] +pub struct WDT { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for WDT {} +impl WDT { + #[doc = r"Pointer to the register block"] + pub const PTR: *const wdt::RegisterBlock = 0x4000_2000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const wdt::RegisterBlock { + Self::PTR + } +} +impl Deref for WDT { + type Target = wdt::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for WDT { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("WDT").finish() + } +} +#[doc = "Watchdog Timer"] +pub mod wdt; +#[doc = "System timer"] +pub struct SYSTICK { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SYSTICK {} +impl SYSTICK { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sys_tick::RegisterBlock = 0xe000_e010 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sys_tick::RegisterBlock { + Self::PTR + } +} +impl Deref for SYSTICK { + type Target = sys_tick::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SYSTICK { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SYSTICK").finish() + } +} +#[doc = "System timer"] +pub mod sys_tick; +#[doc = "System Control Registers"] +pub struct SYSTEMCONTROL { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SYSTEMCONTROL {} +impl SYSTEMCONTROL { + #[doc = r"Pointer to the register block"] + pub const PTR: *const system_control::RegisterBlock = 0xe000_e000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const system_control::RegisterBlock { + Self::PTR + } +} +impl Deref for SYSTEMCONTROL { + type Target = system_control::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SYSTEMCONTROL { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SYSTEMCONTROL").finish() + } +} +#[doc = "System Control Registers"] +pub mod system_control; +#[no_mangle] +static mut DEVICE_PERIPHERALS: bool = false; +#[doc = r"All the peripherals"] +#[allow(non_snake_case)] +pub struct Peripherals { + #[doc = "AC"] + pub AC: AC, + #[doc = "ADC0"] + pub ADC0: ADC0, + #[doc = "ADC1"] + pub ADC1: ADC1, + #[doc = "CAN0"] + pub CAN0: CAN0, + #[doc = "CCL"] + pub CCL: CCL, + #[doc = "DAC"] + pub DAC: DAC, + #[doc = "DIVAS"] + pub DIVAS: DIVAS, + #[doc = "DMAC"] + pub DMAC: DMAC, + #[doc = "DSU"] + pub DSU: DSU, + #[doc = "EIC"] + pub EIC: EIC, + #[doc = "EVSYS"] + pub EVSYS: EVSYS, + #[doc = "FREQM"] + pub FREQM: FREQM, + #[doc = "GCLK"] + pub GCLK: GCLK, + #[doc = "HMATRIXHS"] + pub HMATRIXHS: HMATRIXHS, + #[doc = "MCLK"] + pub MCLK: MCLK, + #[doc = "MTB"] + pub MTB: MTB, + #[doc = "NVMCTRL"] + pub NVMCTRL: NVMCTRL, + #[doc = "OSCCTRL"] + pub OSCCTRL: OSCCTRL, + #[doc = "OSC32KCTRL"] + pub OSC32KCTRL: OSC32KCTRL, + #[doc = "PAC"] + pub PAC: PAC, + #[doc = "PM"] + pub PM: PM, + #[doc = "PORT"] + pub PORT: PORT, + #[doc = "PORT_IOBUS"] + pub PORT_IOBUS: PORT_IOBUS, + #[doc = "RSTC"] + pub RSTC: RSTC, + #[doc = "RTC"] + pub RTC: RTC, + #[doc = "SDADC"] + pub SDADC: SDADC, + #[doc = "SERCOM0"] + pub SERCOM0: SERCOM0, + #[doc = "SERCOM1"] + pub SERCOM1: SERCOM1, + #[doc = "SERCOM2"] + pub SERCOM2: SERCOM2, + #[doc = "SERCOM3"] + pub SERCOM3: SERCOM3, + #[doc = "SUPC"] + pub SUPC: SUPC, + #[doc = "TC0"] + pub TC0: TC0, + #[doc = "TC1"] + pub TC1: TC1, + #[doc = "TC2"] + pub TC2: TC2, + #[doc = "TC3"] + pub TC3: TC3, + #[doc = "TC4"] + pub TC4: TC4, + #[doc = "TCC0"] + pub TCC0: TCC0, + #[doc = "TCC1"] + pub TCC1: TCC1, + #[doc = "TCC2"] + pub TCC2: TCC2, + #[doc = "TSENS"] + pub TSENS: TSENS, + #[doc = "WDT"] + pub WDT: WDT, + #[doc = "SYSTICK"] + pub SYSTICK: SYSTICK, + #[doc = "SYSTEMCONTROL"] + pub SYSTEMCONTROL: SYSTEMCONTROL, +} +impl Peripherals { + #[doc = r"Returns all the peripherals *once*"] + #[inline] + pub fn take() -> Option { + cortex_m::interrupt::free(|_| { + if unsafe { DEVICE_PERIPHERALS } { + None + } else { + Some(unsafe { Peripherals::steal() }) + } + }) + } + #[doc = r"Unchecked version of `Peripherals::take`"] + #[inline] + pub unsafe fn steal() -> Self { + DEVICE_PERIPHERALS = true; + Peripherals { + AC: AC { + _marker: PhantomData, + }, + ADC0: ADC0 { + _marker: PhantomData, + }, + ADC1: ADC1 { + _marker: PhantomData, + }, + CAN0: CAN0 { + _marker: PhantomData, + }, + CCL: CCL { + _marker: PhantomData, + }, + DAC: DAC { + _marker: PhantomData, + }, + DIVAS: DIVAS { + _marker: PhantomData, + }, + DMAC: DMAC { + _marker: PhantomData, + }, + DSU: DSU { + _marker: PhantomData, + }, + EIC: EIC { + _marker: PhantomData, + }, + EVSYS: EVSYS { + _marker: PhantomData, + }, + FREQM: FREQM { + _marker: PhantomData, + }, + GCLK: GCLK { + _marker: PhantomData, + }, + HMATRIXHS: HMATRIXHS { + _marker: PhantomData, + }, + MCLK: MCLK { + _marker: PhantomData, + }, + MTB: MTB { + _marker: PhantomData, + }, + NVMCTRL: NVMCTRL { + _marker: PhantomData, + }, + OSCCTRL: OSCCTRL { + _marker: PhantomData, + }, + OSC32KCTRL: OSC32KCTRL { + _marker: PhantomData, + }, + PAC: PAC { + _marker: PhantomData, + }, + PM: PM { + _marker: PhantomData, + }, + PORT: PORT { + _marker: PhantomData, + }, + PORT_IOBUS: PORT_IOBUS { + _marker: PhantomData, + }, + RSTC: RSTC { + _marker: PhantomData, + }, + RTC: RTC { + _marker: PhantomData, + }, + SDADC: SDADC { + _marker: PhantomData, + }, + SERCOM0: SERCOM0 { + _marker: PhantomData, + }, + SERCOM1: SERCOM1 { + _marker: PhantomData, + }, + SERCOM2: SERCOM2 { + _marker: PhantomData, + }, + SERCOM3: SERCOM3 { + _marker: PhantomData, + }, + SUPC: SUPC { + _marker: PhantomData, + }, + TC0: TC0 { + _marker: PhantomData, + }, + TC1: TC1 { + _marker: PhantomData, + }, + TC2: TC2 { + _marker: PhantomData, + }, + TC3: TC3 { + _marker: PhantomData, + }, + TC4: TC4 { + _marker: PhantomData, + }, + TCC0: TCC0 { + _marker: PhantomData, + }, + TCC1: TCC1 { + _marker: PhantomData, + }, + TCC2: TCC2 { + _marker: PhantomData, + }, + TSENS: TSENS { + _marker: PhantomData, + }, + WDT: WDT { + _marker: PhantomData, + }, + SYSTICK: SYSTICK { + _marker: PhantomData, + }, + SYSTEMCONTROL: SYSTEMCONTROL { + _marker: PhantomData, + }, + } + } +} diff --git a/pac/atsamc21e/src/mclk.rs b/pac/atsamc21e/src/mclk.rs new file mode 100644 index 000000000000..fc7efe3a584e --- /dev/null +++ b/pac/atsamc21e/src/mclk.rs @@ -0,0 +1,54 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved0: [u8; 0x01], + #[doc = "0x01 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x02 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x03 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x04 - CPU Clock Division"] + pub cpudiv: crate::Reg, + _reserved4: [u8; 0x0b], + #[doc = "0x10 - AHB Mask"] + pub ahbmask: crate::Reg, + #[doc = "0x14 - APBA Mask"] + pub apbamask: crate::Reg, + #[doc = "0x18 - APBB Mask"] + pub apbbmask: crate::Reg, + #[doc = "0x1c - APBC Mask"] + pub apbcmask: crate::Reg, +} +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "CPUDIV register accessor: an alias for `Reg`"] +pub type CPUDIV = crate::Reg; +#[doc = "CPU Clock Division"] +pub mod cpudiv; +#[doc = "AHBMASK register accessor: an alias for `Reg`"] +pub type AHBMASK = crate::Reg; +#[doc = "AHB Mask"] +pub mod ahbmask; +#[doc = "APBAMASK register accessor: an alias for `Reg`"] +pub type APBAMASK = crate::Reg; +#[doc = "APBA Mask"] +pub mod apbamask; +#[doc = "APBBMASK register accessor: an alias for `Reg`"] +pub type APBBMASK = crate::Reg; +#[doc = "APBB Mask"] +pub mod apbbmask; +#[doc = "APBCMASK register accessor: an alias for `Reg`"] +pub type APBCMASK = crate::Reg; +#[doc = "APBC Mask"] +pub mod apbcmask; diff --git a/pac/atsamc21e/src/mclk/ahbmask.rs b/pac/atsamc21e/src/mclk/ahbmask.rs new file mode 100644 index 000000000000..ae43c484e5f2 --- /dev/null +++ b/pac/atsamc21e/src/mclk/ahbmask.rs @@ -0,0 +1,630 @@ +#[doc = "Register `AHBMASK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `AHBMASK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `HPB0_` reader - HPB0 AHB Clock Mask"] +pub struct HPB0__R(crate::FieldReader); +impl HPB0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HPB0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HPB0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HPB0_` writer - HPB0 AHB Clock Mask"] +pub struct HPB0__W<'a> { + w: &'a mut W, +} +impl<'a> HPB0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `HPB1_` reader - HPB1 AHB Clock Mask"] +pub struct HPB1__R(crate::FieldReader); +impl HPB1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HPB1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HPB1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HPB1_` writer - HPB1 AHB Clock Mask"] +pub struct HPB1__W<'a> { + w: &'a mut W, +} +impl<'a> HPB1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `HPB2_` reader - HPB2 AHB Clock Mask"] +pub struct HPB2__R(crate::FieldReader); +impl HPB2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HPB2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HPB2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HPB2_` writer - HPB2 AHB Clock Mask"] +pub struct HPB2__W<'a> { + w: &'a mut W, +} +impl<'a> HPB2__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `DSU_` reader - DSU AHB Clock Mask"] +pub struct DSU__R(crate::FieldReader); +impl DSU__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DSU__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DSU__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DSU_` writer - DSU AHB Clock Mask"] +pub struct DSU__W<'a> { + w: &'a mut W, +} +impl<'a> DSU__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `HMATRIXHS_` reader - HMATRIXHS AHB Clock Mask"] +pub struct HMATRIXHS__R(crate::FieldReader); +impl HMATRIXHS__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HMATRIXHS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HMATRIXHS__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HMATRIXHS_` writer - HMATRIXHS AHB Clock Mask"] +pub struct HMATRIXHS__W<'a> { + w: &'a mut W, +} +impl<'a> HMATRIXHS__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `NVMCTRL_` reader - NVMCTRL AHB Clock Mask"] +pub struct NVMCTRL__R(crate::FieldReader); +impl NVMCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NVMCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NVMCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NVMCTRL_` writer - NVMCTRL AHB Clock Mask"] +pub struct NVMCTRL__W<'a> { + w: &'a mut W, +} +impl<'a> NVMCTRL__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `HSRAM_` reader - HSRAM AHB Clock Mask"] +pub struct HSRAM__R(crate::FieldReader); +impl HSRAM__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HSRAM__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HSRAM__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HSRAM_` writer - HSRAM AHB Clock Mask"] +pub struct HSRAM__W<'a> { + w: &'a mut W, +} +impl<'a> HSRAM__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `DMAC_` reader - DMAC AHB Clock Mask"] +pub struct DMAC__R(crate::FieldReader); +impl DMAC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DMAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DMAC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DMAC_` writer - DMAC AHB Clock Mask"] +pub struct DMAC__W<'a> { + w: &'a mut W, +} +impl<'a> DMAC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CAN0_` reader - CAN0 AHB Clock Mask"] +pub struct CAN0__R(crate::FieldReader); +impl CAN0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CAN0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CAN0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAN0_` writer - CAN0 AHB Clock Mask"] +pub struct CAN0__W<'a> { + w: &'a mut W, +} +impl<'a> CAN0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `PAC_` reader - PAC AHB Clock Mask"] +pub struct PAC__R(crate::FieldReader); +impl PAC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PAC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PAC_` writer - PAC AHB Clock Mask"] +pub struct PAC__W<'a> { + w: &'a mut W, +} +impl<'a> PAC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `NVMCTRL_PICACHU_` reader - NVMCTRL_PICACHU AHB Clock Mask"] +pub struct NVMCTRL_PICACHU__R(crate::FieldReader); +impl NVMCTRL_PICACHU__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NVMCTRL_PICACHU__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NVMCTRL_PICACHU__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NVMCTRL_PICACHU_` writer - NVMCTRL_PICACHU AHB Clock Mask"] +pub struct NVMCTRL_PICACHU__W<'a> { + w: &'a mut W, +} +impl<'a> NVMCTRL_PICACHU__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `DIVAS_` reader - DIVAS AHB Clock Mask"] +pub struct DIVAS__R(crate::FieldReader); +impl DIVAS__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIVAS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIVAS__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIVAS_` writer - DIVAS AHB Clock Mask"] +pub struct DIVAS__W<'a> { + w: &'a mut W, +} +impl<'a> DIVAS__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +impl R { + #[doc = "Bit 0 - HPB0 AHB Clock Mask"] + #[inline(always)] + pub fn hpb0_(&self) -> HPB0__R { + HPB0__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - HPB1 AHB Clock Mask"] + #[inline(always)] + pub fn hpb1_(&self) -> HPB1__R { + HPB1__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - HPB2 AHB Clock Mask"] + #[inline(always)] + pub fn hpb2_(&self) -> HPB2__R { + HPB2__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - DSU AHB Clock Mask"] + #[inline(always)] + pub fn dsu_(&self) -> DSU__R { + DSU__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - HMATRIXHS AHB Clock Mask"] + #[inline(always)] + pub fn hmatrixhs_(&self) -> HMATRIXHS__R { + HMATRIXHS__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - NVMCTRL AHB Clock Mask"] + #[inline(always)] + pub fn nvmctrl_(&self) -> NVMCTRL__R { + NVMCTRL__R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - HSRAM AHB Clock Mask"] + #[inline(always)] + pub fn hsram_(&self) -> HSRAM__R { + HSRAM__R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - DMAC AHB Clock Mask"] + #[inline(always)] + pub fn dmac_(&self) -> DMAC__R { + DMAC__R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - CAN0 AHB Clock Mask"] + #[inline(always)] + pub fn can0_(&self) -> CAN0__R { + CAN0__R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 10 - PAC AHB Clock Mask"] + #[inline(always)] + pub fn pac_(&self) -> PAC__R { + PAC__R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - NVMCTRL_PICACHU AHB Clock Mask"] + #[inline(always)] + pub fn nvmctrl_picachu_(&self) -> NVMCTRL_PICACHU__R { + NVMCTRL_PICACHU__R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - DIVAS AHB Clock Mask"] + #[inline(always)] + pub fn divas_(&self) -> DIVAS__R { + DIVAS__R::new(((self.bits >> 12) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - HPB0 AHB Clock Mask"] + #[inline(always)] + pub fn hpb0_(&mut self) -> HPB0__W { + HPB0__W { w: self } + } + #[doc = "Bit 1 - HPB1 AHB Clock Mask"] + #[inline(always)] + pub fn hpb1_(&mut self) -> HPB1__W { + HPB1__W { w: self } + } + #[doc = "Bit 2 - HPB2 AHB Clock Mask"] + #[inline(always)] + pub fn hpb2_(&mut self) -> HPB2__W { + HPB2__W { w: self } + } + #[doc = "Bit 3 - DSU AHB Clock Mask"] + #[inline(always)] + pub fn dsu_(&mut self) -> DSU__W { + DSU__W { w: self } + } + #[doc = "Bit 4 - HMATRIXHS AHB Clock Mask"] + #[inline(always)] + pub fn hmatrixhs_(&mut self) -> HMATRIXHS__W { + HMATRIXHS__W { w: self } + } + #[doc = "Bit 5 - NVMCTRL AHB Clock Mask"] + #[inline(always)] + pub fn nvmctrl_(&mut self) -> NVMCTRL__W { + NVMCTRL__W { w: self } + } + #[doc = "Bit 6 - HSRAM AHB Clock Mask"] + #[inline(always)] + pub fn hsram_(&mut self) -> HSRAM__W { + HSRAM__W { w: self } + } + #[doc = "Bit 7 - DMAC AHB Clock Mask"] + #[inline(always)] + pub fn dmac_(&mut self) -> DMAC__W { + DMAC__W { w: self } + } + #[doc = "Bit 8 - CAN0 AHB Clock Mask"] + #[inline(always)] + pub fn can0_(&mut self) -> CAN0__W { + CAN0__W { w: self } + } + #[doc = "Bit 10 - PAC AHB Clock Mask"] + #[inline(always)] + pub fn pac_(&mut self) -> PAC__W { + PAC__W { w: self } + } + #[doc = "Bit 11 - NVMCTRL_PICACHU AHB Clock Mask"] + #[inline(always)] + pub fn nvmctrl_picachu_(&mut self) -> NVMCTRL_PICACHU__W { + NVMCTRL_PICACHU__W { w: self } + } + #[doc = "Bit 12 - DIVAS AHB Clock Mask"] + #[inline(always)] + pub fn divas_(&mut self) -> DIVAS__W { + DIVAS__W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "AHB Mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ahbmask](index.html) module"] +pub struct AHBMASK_SPEC; +impl crate::RegisterSpec for AHBMASK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ahbmask::R](R) reader structure"] +impl crate::Readable for AHBMASK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ahbmask::W](W) writer structure"] +impl crate::Writable for AHBMASK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets AHBMASK to value 0x1cff"] +impl crate::Resettable for AHBMASK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x1cff + } +} diff --git a/pac/atsamc21e/src/mclk/apbamask.rs b/pac/atsamc21e/src/mclk/apbamask.rs new file mode 100644 index 000000000000..144b1163d5cb --- /dev/null +++ b/pac/atsamc21e/src/mclk/apbamask.rs @@ -0,0 +1,677 @@ +#[doc = "Register `APBAMASK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `APBAMASK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PAC_` reader - PAC APB Clock Enable"] +pub struct PAC__R(crate::FieldReader); +impl PAC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PAC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PAC_` writer - PAC APB Clock Enable"] +pub struct PAC__W<'a> { + w: &'a mut W, +} +impl<'a> PAC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `PM_` reader - PM APB Clock Enable"] +pub struct PM__R(crate::FieldReader); +impl PM__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PM__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PM__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PM_` writer - PM APB Clock Enable"] +pub struct PM__W<'a> { + w: &'a mut W, +} +impl<'a> PM__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MCLK_` reader - MCLK APB Clock Enable"] +pub struct MCLK__R(crate::FieldReader); +impl MCLK__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCLK__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCLK__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCLK_` writer - MCLK APB Clock Enable"] +pub struct MCLK__W<'a> { + w: &'a mut W, +} +impl<'a> MCLK__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RSTC_` reader - RSTC APB Clock Enable"] +pub struct RSTC__R(crate::FieldReader); +impl RSTC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RSTC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RSTC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RSTC_` writer - RSTC APB Clock Enable"] +pub struct RSTC__W<'a> { + w: &'a mut W, +} +impl<'a> RSTC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `OSCCTRL_` reader - OSCCTRL APB Clock Enable"] +pub struct OSCCTRL__R(crate::FieldReader); +impl OSCCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSCCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSCCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSCCTRL_` writer - OSCCTRL APB Clock Enable"] +pub struct OSCCTRL__W<'a> { + w: &'a mut W, +} +impl<'a> OSCCTRL__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `OSC32KCTRL_` reader - OSC32KCTRL APB Clock Enable"] +pub struct OSC32KCTRL__R(crate::FieldReader); +impl OSC32KCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC32KCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC32KCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC32KCTRL_` writer - OSC32KCTRL APB Clock Enable"] +pub struct OSC32KCTRL__W<'a> { + w: &'a mut W, +} +impl<'a> OSC32KCTRL__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `SUPC_` reader - SUPC APB Clock Enable"] +pub struct SUPC__R(crate::FieldReader); +impl SUPC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SUPC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SUPC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SUPC_` writer - SUPC APB Clock Enable"] +pub struct SUPC__W<'a> { + w: &'a mut W, +} +impl<'a> SUPC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `GCLK_` reader - GCLK APB Clock Enable"] +pub struct GCLK__R(crate::FieldReader); +impl GCLK__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GCLK__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GCLK__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GCLK_` writer - GCLK APB Clock Enable"] +pub struct GCLK__W<'a> { + w: &'a mut W, +} +impl<'a> GCLK__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `WDT_` reader - WDT APB Clock Enable"] +pub struct WDT__R(crate::FieldReader); +impl WDT__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WDT__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WDT__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WDT_` writer - WDT APB Clock Enable"] +pub struct WDT__W<'a> { + w: &'a mut W, +} +impl<'a> WDT__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `RTC_` reader - RTC APB Clock Enable"] +pub struct RTC__R(crate::FieldReader); +impl RTC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RTC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RTC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RTC_` writer - RTC APB Clock Enable"] +pub struct RTC__W<'a> { + w: &'a mut W, +} +impl<'a> RTC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `EIC_` reader - EIC APB Clock Enable"] +pub struct EIC__R(crate::FieldReader); +impl EIC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EIC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EIC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EIC_` writer - EIC APB Clock Enable"] +pub struct EIC__W<'a> { + w: &'a mut W, +} +impl<'a> EIC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `FREQM_` reader - FREQM APB Clock Enable"] +pub struct FREQM__R(crate::FieldReader); +impl FREQM__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FREQM__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FREQM__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FREQM_` writer - FREQM APB Clock Enable"] +pub struct FREQM__W<'a> { + w: &'a mut W, +} +impl<'a> FREQM__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `TSENS_` reader - TSENS APB Clock Enable"] +pub struct TSENS__R(crate::FieldReader); +impl TSENS__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSENS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSENS__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSENS_` writer - TSENS APB Clock Enable"] +pub struct TSENS__W<'a> { + w: &'a mut W, +} +impl<'a> TSENS__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +impl R { + #[doc = "Bit 0 - PAC APB Clock Enable"] + #[inline(always)] + pub fn pac_(&self) -> PAC__R { + PAC__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - PM APB Clock Enable"] + #[inline(always)] + pub fn pm_(&self) -> PM__R { + PM__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - MCLK APB Clock Enable"] + #[inline(always)] + pub fn mclk_(&self) -> MCLK__R { + MCLK__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - RSTC APB Clock Enable"] + #[inline(always)] + pub fn rstc_(&self) -> RSTC__R { + RSTC__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - OSCCTRL APB Clock Enable"] + #[inline(always)] + pub fn oscctrl_(&self) -> OSCCTRL__R { + OSCCTRL__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - OSC32KCTRL APB Clock Enable"] + #[inline(always)] + pub fn osc32kctrl_(&self) -> OSC32KCTRL__R { + OSC32KCTRL__R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - SUPC APB Clock Enable"] + #[inline(always)] + pub fn supc_(&self) -> SUPC__R { + SUPC__R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - GCLK APB Clock Enable"] + #[inline(always)] + pub fn gclk_(&self) -> GCLK__R { + GCLK__R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - WDT APB Clock Enable"] + #[inline(always)] + pub fn wdt_(&self) -> WDT__R { + WDT__R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - RTC APB Clock Enable"] + #[inline(always)] + pub fn rtc_(&self) -> RTC__R { + RTC__R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - EIC APB Clock Enable"] + #[inline(always)] + pub fn eic_(&self) -> EIC__R { + EIC__R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - FREQM APB Clock Enable"] + #[inline(always)] + pub fn freqm_(&self) -> FREQM__R { + FREQM__R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - TSENS APB Clock Enable"] + #[inline(always)] + pub fn tsens_(&self) -> TSENS__R { + TSENS__R::new(((self.bits >> 12) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - PAC APB Clock Enable"] + #[inline(always)] + pub fn pac_(&mut self) -> PAC__W { + PAC__W { w: self } + } + #[doc = "Bit 1 - PM APB Clock Enable"] + #[inline(always)] + pub fn pm_(&mut self) -> PM__W { + PM__W { w: self } + } + #[doc = "Bit 2 - MCLK APB Clock Enable"] + #[inline(always)] + pub fn mclk_(&mut self) -> MCLK__W { + MCLK__W { w: self } + } + #[doc = "Bit 3 - RSTC APB Clock Enable"] + #[inline(always)] + pub fn rstc_(&mut self) -> RSTC__W { + RSTC__W { w: self } + } + #[doc = "Bit 4 - OSCCTRL APB Clock Enable"] + #[inline(always)] + pub fn oscctrl_(&mut self) -> OSCCTRL__W { + OSCCTRL__W { w: self } + } + #[doc = "Bit 5 - OSC32KCTRL APB Clock Enable"] + #[inline(always)] + pub fn osc32kctrl_(&mut self) -> OSC32KCTRL__W { + OSC32KCTRL__W { w: self } + } + #[doc = "Bit 6 - SUPC APB Clock Enable"] + #[inline(always)] + pub fn supc_(&mut self) -> SUPC__W { + SUPC__W { w: self } + } + #[doc = "Bit 7 - GCLK APB Clock Enable"] + #[inline(always)] + pub fn gclk_(&mut self) -> GCLK__W { + GCLK__W { w: self } + } + #[doc = "Bit 8 - WDT APB Clock Enable"] + #[inline(always)] + pub fn wdt_(&mut self) -> WDT__W { + WDT__W { w: self } + } + #[doc = "Bit 9 - RTC APB Clock Enable"] + #[inline(always)] + pub fn rtc_(&mut self) -> RTC__W { + RTC__W { w: self } + } + #[doc = "Bit 10 - EIC APB Clock Enable"] + #[inline(always)] + pub fn eic_(&mut self) -> EIC__W { + EIC__W { w: self } + } + #[doc = "Bit 11 - FREQM APB Clock Enable"] + #[inline(always)] + pub fn freqm_(&mut self) -> FREQM__W { + FREQM__W { w: self } + } + #[doc = "Bit 12 - TSENS APB Clock Enable"] + #[inline(always)] + pub fn tsens_(&mut self) -> TSENS__W { + TSENS__W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "APBA Mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [apbamask](index.html) module"] +pub struct APBAMASK_SPEC; +impl crate::RegisterSpec for APBAMASK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [apbamask::R](R) reader structure"] +impl crate::Readable for APBAMASK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [apbamask::W](W) writer structure"] +impl crate::Writable for APBAMASK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets APBAMASK to value 0x0fff"] +impl crate::Resettable for APBAMASK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0fff + } +} diff --git a/pac/atsamc21e/src/mclk/apbbmask.rs b/pac/atsamc21e/src/mclk/apbbmask.rs new file mode 100644 index 000000000000..e1ec6b1f2323 --- /dev/null +++ b/pac/atsamc21e/src/mclk/apbbmask.rs @@ -0,0 +1,254 @@ +#[doc = "Register `APBBMASK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `APBBMASK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PORT_` reader - PORT APB Clock Enable"] +pub struct PORT__R(crate::FieldReader); +impl PORT__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PORT__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PORT__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PORT_` writer - PORT APB Clock Enable"] +pub struct PORT__W<'a> { + w: &'a mut W, +} +impl<'a> PORT__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `DSU_` reader - DSU APB Clock Enable"] +pub struct DSU__R(crate::FieldReader); +impl DSU__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DSU__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DSU__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DSU_` writer - DSU APB Clock Enable"] +pub struct DSU__W<'a> { + w: &'a mut W, +} +impl<'a> DSU__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `NVMCTRL_` reader - NVMCTRL APB Clock Enable"] +pub struct NVMCTRL__R(crate::FieldReader); +impl NVMCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NVMCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NVMCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NVMCTRL_` writer - NVMCTRL APB Clock Enable"] +pub struct NVMCTRL__W<'a> { + w: &'a mut W, +} +impl<'a> NVMCTRL__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `HMATRIXHS_` reader - HMATRIXHS APB Clock Enable"] +pub struct HMATRIXHS__R(crate::FieldReader); +impl HMATRIXHS__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HMATRIXHS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HMATRIXHS__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HMATRIXHS_` writer - HMATRIXHS APB Clock Enable"] +pub struct HMATRIXHS__W<'a> { + w: &'a mut W, +} +impl<'a> HMATRIXHS__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - PORT APB Clock Enable"] + #[inline(always)] + pub fn port_(&self) -> PORT__R { + PORT__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - DSU APB Clock Enable"] + #[inline(always)] + pub fn dsu_(&self) -> DSU__R { + DSU__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - NVMCTRL APB Clock Enable"] + #[inline(always)] + pub fn nvmctrl_(&self) -> NVMCTRL__R { + NVMCTRL__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 5 - HMATRIXHS APB Clock Enable"] + #[inline(always)] + pub fn hmatrixhs_(&self) -> HMATRIXHS__R { + HMATRIXHS__R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - PORT APB Clock Enable"] + #[inline(always)] + pub fn port_(&mut self) -> PORT__W { + PORT__W { w: self } + } + #[doc = "Bit 1 - DSU APB Clock Enable"] + #[inline(always)] + pub fn dsu_(&mut self) -> DSU__W { + DSU__W { w: self } + } + #[doc = "Bit 2 - NVMCTRL APB Clock Enable"] + #[inline(always)] + pub fn nvmctrl_(&mut self) -> NVMCTRL__W { + NVMCTRL__W { w: self } + } + #[doc = "Bit 5 - HMATRIXHS APB Clock Enable"] + #[inline(always)] + pub fn hmatrixhs_(&mut self) -> HMATRIXHS__W { + HMATRIXHS__W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "APBB Mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [apbbmask](index.html) module"] +pub struct APBBMASK_SPEC; +impl crate::RegisterSpec for APBBMASK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [apbbmask::R](R) reader structure"] +impl crate::Readable for APBBMASK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [apbbmask::W](W) writer structure"] +impl crate::Writable for APBBMASK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets APBBMASK to value 0x07"] +impl crate::Resettable for APBBMASK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x07 + } +} diff --git a/pac/atsamc21e/src/mclk/apbcmask.rs b/pac/atsamc21e/src/mclk/apbcmask.rs new file mode 100644 index 000000000000..62719751b04b --- /dev/null +++ b/pac/atsamc21e/src/mclk/apbcmask.rs @@ -0,0 +1,1006 @@ +#[doc = "Register `APBCMASK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `APBCMASK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVSYS_` reader - EVSYS APB Clock Enable"] +pub struct EVSYS__R(crate::FieldReader); +impl EVSYS__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVSYS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVSYS__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVSYS_` writer - EVSYS APB Clock Enable"] +pub struct EVSYS__W<'a> { + w: &'a mut W, +} +impl<'a> EVSYS__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `SERCOM0_` reader - SERCOM0 APB Clock Enable"] +pub struct SERCOM0__R(crate::FieldReader); +impl SERCOM0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM0_` writer - SERCOM0 APB Clock Enable"] +pub struct SERCOM0__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SERCOM1_` reader - SERCOM1 APB Clock Enable"] +pub struct SERCOM1__R(crate::FieldReader); +impl SERCOM1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM1_` writer - SERCOM1 APB Clock Enable"] +pub struct SERCOM1__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SERCOM2_` reader - SERCOM2 APB Clock Enable"] +pub struct SERCOM2__R(crate::FieldReader); +impl SERCOM2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM2_` writer - SERCOM2 APB Clock Enable"] +pub struct SERCOM2__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM2__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `SERCOM3_` reader - SERCOM3 APB Clock Enable"] +pub struct SERCOM3__R(crate::FieldReader); +impl SERCOM3__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM3__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM3__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM3_` writer - SERCOM3 APB Clock Enable"] +pub struct SERCOM3__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM3__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `TCC0_` reader - TCC0 APB Clock Enable"] +pub struct TCC0__R(crate::FieldReader); +impl TCC0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCC0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCC0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCC0_` writer - TCC0 APB Clock Enable"] +pub struct TCC0__W<'a> { + w: &'a mut W, +} +impl<'a> TCC0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `TCC1_` reader - TCC1 APB Clock Enable"] +pub struct TCC1__R(crate::FieldReader); +impl TCC1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCC1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCC1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCC1_` writer - TCC1 APB Clock Enable"] +pub struct TCC1__W<'a> { + w: &'a mut W, +} +impl<'a> TCC1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `TCC2_` reader - TCC2 APB Clock Enable"] +pub struct TCC2__R(crate::FieldReader); +impl TCC2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCC2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCC2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCC2_` writer - TCC2 APB Clock Enable"] +pub struct TCC2__W<'a> { + w: &'a mut W, +} +impl<'a> TCC2__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `TC0_` reader - TC0 APB Clock Enable"] +pub struct TC0__R(crate::FieldReader); +impl TC0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC0_` writer - TC0 APB Clock Enable"] +pub struct TC0__W<'a> { + w: &'a mut W, +} +impl<'a> TC0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `TC1_` reader - TC1 APB Clock Enable"] +pub struct TC1__R(crate::FieldReader); +impl TC1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC1_` writer - TC1 APB Clock Enable"] +pub struct TC1__W<'a> { + w: &'a mut W, +} +impl<'a> TC1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `TC2_` reader - TC2 APB Clock Enable"] +pub struct TC2__R(crate::FieldReader); +impl TC2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC2_` writer - TC2 APB Clock Enable"] +pub struct TC2__W<'a> { + w: &'a mut W, +} +impl<'a> TC2__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `TC3_` reader - TC3 APB Clock Enable"] +pub struct TC3__R(crate::FieldReader); +impl TC3__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC3__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC3__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC3_` writer - TC3 APB Clock Enable"] +pub struct TC3__W<'a> { + w: &'a mut W, +} +impl<'a> TC3__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `TC4_` reader - TC4 APB Clock Enable"] +pub struct TC4__R(crate::FieldReader); +impl TC4__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC4__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC4__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC4_` writer - TC4 APB Clock Enable"] +pub struct TC4__W<'a> { + w: &'a mut W, +} +impl<'a> TC4__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `ADC0_` reader - ADC0 APB Clock Enable"] +pub struct ADC0__R(crate::FieldReader); +impl ADC0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ADC0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADC0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADC0_` writer - ADC0 APB Clock Enable"] +pub struct ADC0__W<'a> { + w: &'a mut W, +} +impl<'a> ADC0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `ADC1_` reader - ADC1 APB Clock Enable"] +pub struct ADC1__R(crate::FieldReader); +impl ADC1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ADC1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADC1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADC1_` writer - ADC1 APB Clock Enable"] +pub struct ADC1__W<'a> { + w: &'a mut W, +} +impl<'a> ADC1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `SDADC_` reader - SDADC APB Clock Enable"] +pub struct SDADC__R(crate::FieldReader); +impl SDADC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SDADC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SDADC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SDADC_` writer - SDADC APB Clock Enable"] +pub struct SDADC__W<'a> { + w: &'a mut W, +} +impl<'a> SDADC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `AC_` reader - AC APB Clock Enable"] +pub struct AC__R(crate::FieldReader); +impl AC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AC_` writer - AC APB Clock Enable"] +pub struct AC__W<'a> { + w: &'a mut W, +} +impl<'a> AC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `DAC_` reader - DAC APB Clock Enable"] +pub struct DAC__R(crate::FieldReader); +impl DAC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DAC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DAC_` writer - DAC APB Clock Enable"] +pub struct DAC__W<'a> { + w: &'a mut W, +} +impl<'a> DAC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `PTC_` reader - PTC APB Clock Enable"] +pub struct PTC__R(crate::FieldReader); +impl PTC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PTC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PTC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PTC_` writer - PTC APB Clock Enable"] +pub struct PTC__W<'a> { + w: &'a mut W, +} +impl<'a> PTC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `CCL_` reader - CCL APB Clock Enable"] +pub struct CCL__R(crate::FieldReader); +impl CCL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCL_` writer - CCL APB Clock Enable"] +pub struct CCL__W<'a> { + w: &'a mut W, +} +impl<'a> CCL__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +impl R { + #[doc = "Bit 0 - EVSYS APB Clock Enable"] + #[inline(always)] + pub fn evsys_(&self) -> EVSYS__R { + EVSYS__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM0 APB Clock Enable"] + #[inline(always)] + pub fn sercom0_(&self) -> SERCOM0__R { + SERCOM0__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - SERCOM1 APB Clock Enable"] + #[inline(always)] + pub fn sercom1_(&self) -> SERCOM1__R { + SERCOM1__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - SERCOM2 APB Clock Enable"] + #[inline(always)] + pub fn sercom2_(&self) -> SERCOM2__R { + SERCOM2__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - SERCOM3 APB Clock Enable"] + #[inline(always)] + pub fn sercom3_(&self) -> SERCOM3__R { + SERCOM3__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 9 - TCC0 APB Clock Enable"] + #[inline(always)] + pub fn tcc0_(&self) -> TCC0__R { + TCC0__R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - TCC1 APB Clock Enable"] + #[inline(always)] + pub fn tcc1_(&self) -> TCC1__R { + TCC1__R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - TCC2 APB Clock Enable"] + #[inline(always)] + pub fn tcc2_(&self) -> TCC2__R { + TCC2__R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - TC0 APB Clock Enable"] + #[inline(always)] + pub fn tc0_(&self) -> TC0__R { + TC0__R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - TC1 APB Clock Enable"] + #[inline(always)] + pub fn tc1_(&self) -> TC1__R { + TC1__R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - TC2 APB Clock Enable"] + #[inline(always)] + pub fn tc2_(&self) -> TC2__R { + TC2__R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - TC3 APB Clock Enable"] + #[inline(always)] + pub fn tc3_(&self) -> TC3__R { + TC3__R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - TC4 APB Clock Enable"] + #[inline(always)] + pub fn tc4_(&self) -> TC4__R { + TC4__R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - ADC0 APB Clock Enable"] + #[inline(always)] + pub fn adc0_(&self) -> ADC0__R { + ADC0__R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - ADC1 APB Clock Enable"] + #[inline(always)] + pub fn adc1_(&self) -> ADC1__R { + ADC1__R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - SDADC APB Clock Enable"] + #[inline(always)] + pub fn sdadc_(&self) -> SDADC__R { + SDADC__R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - AC APB Clock Enable"] + #[inline(always)] + pub fn ac_(&self) -> AC__R { + AC__R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - DAC APB Clock Enable"] + #[inline(always)] + pub fn dac_(&self) -> DAC__R { + DAC__R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - PTC APB Clock Enable"] + #[inline(always)] + pub fn ptc_(&self) -> PTC__R { + PTC__R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - CCL APB Clock Enable"] + #[inline(always)] + pub fn ccl_(&self) -> CCL__R { + CCL__R::new(((self.bits >> 23) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - EVSYS APB Clock Enable"] + #[inline(always)] + pub fn evsys_(&mut self) -> EVSYS__W { + EVSYS__W { w: self } + } + #[doc = "Bit 1 - SERCOM0 APB Clock Enable"] + #[inline(always)] + pub fn sercom0_(&mut self) -> SERCOM0__W { + SERCOM0__W { w: self } + } + #[doc = "Bit 2 - SERCOM1 APB Clock Enable"] + #[inline(always)] + pub fn sercom1_(&mut self) -> SERCOM1__W { + SERCOM1__W { w: self } + } + #[doc = "Bit 3 - SERCOM2 APB Clock Enable"] + #[inline(always)] + pub fn sercom2_(&mut self) -> SERCOM2__W { + SERCOM2__W { w: self } + } + #[doc = "Bit 4 - SERCOM3 APB Clock Enable"] + #[inline(always)] + pub fn sercom3_(&mut self) -> SERCOM3__W { + SERCOM3__W { w: self } + } + #[doc = "Bit 9 - TCC0 APB Clock Enable"] + #[inline(always)] + pub fn tcc0_(&mut self) -> TCC0__W { + TCC0__W { w: self } + } + #[doc = "Bit 10 - TCC1 APB Clock Enable"] + #[inline(always)] + pub fn tcc1_(&mut self) -> TCC1__W { + TCC1__W { w: self } + } + #[doc = "Bit 11 - TCC2 APB Clock Enable"] + #[inline(always)] + pub fn tcc2_(&mut self) -> TCC2__W { + TCC2__W { w: self } + } + #[doc = "Bit 12 - TC0 APB Clock Enable"] + #[inline(always)] + pub fn tc0_(&mut self) -> TC0__W { + TC0__W { w: self } + } + #[doc = "Bit 13 - TC1 APB Clock Enable"] + #[inline(always)] + pub fn tc1_(&mut self) -> TC1__W { + TC1__W { w: self } + } + #[doc = "Bit 14 - TC2 APB Clock Enable"] + #[inline(always)] + pub fn tc2_(&mut self) -> TC2__W { + TC2__W { w: self } + } + #[doc = "Bit 15 - TC3 APB Clock Enable"] + #[inline(always)] + pub fn tc3_(&mut self) -> TC3__W { + TC3__W { w: self } + } + #[doc = "Bit 16 - TC4 APB Clock Enable"] + #[inline(always)] + pub fn tc4_(&mut self) -> TC4__W { + TC4__W { w: self } + } + #[doc = "Bit 17 - ADC0 APB Clock Enable"] + #[inline(always)] + pub fn adc0_(&mut self) -> ADC0__W { + ADC0__W { w: self } + } + #[doc = "Bit 18 - ADC1 APB Clock Enable"] + #[inline(always)] + pub fn adc1_(&mut self) -> ADC1__W { + ADC1__W { w: self } + } + #[doc = "Bit 19 - SDADC APB Clock Enable"] + #[inline(always)] + pub fn sdadc_(&mut self) -> SDADC__W { + SDADC__W { w: self } + } + #[doc = "Bit 20 - AC APB Clock Enable"] + #[inline(always)] + pub fn ac_(&mut self) -> AC__W { + AC__W { w: self } + } + #[doc = "Bit 21 - DAC APB Clock Enable"] + #[inline(always)] + pub fn dac_(&mut self) -> DAC__W { + DAC__W { w: self } + } + #[doc = "Bit 22 - PTC APB Clock Enable"] + #[inline(always)] + pub fn ptc_(&mut self) -> PTC__W { + PTC__W { w: self } + } + #[doc = "Bit 23 - CCL APB Clock Enable"] + #[inline(always)] + pub fn ccl_(&mut self) -> CCL__W { + CCL__W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "APBC Mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [apbcmask](index.html) module"] +pub struct APBCMASK_SPEC; +impl crate::RegisterSpec for APBCMASK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [apbcmask::R](R) reader structure"] +impl crate::Readable for APBCMASK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [apbcmask::W](W) writer structure"] +impl crate::Writable for APBCMASK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets APBCMASK to value 0"] +impl crate::Resettable for APBCMASK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/mclk/cpudiv.rs b/pac/atsamc21e/src/mclk/cpudiv.rs new file mode 100644 index 000000000000..a21fdae21357 --- /dev/null +++ b/pac/atsamc21e/src/mclk/cpudiv.rs @@ -0,0 +1,230 @@ +#[doc = "Register `CPUDIV` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CPUDIV` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "CPU Clock Division Factor\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CPUDIV_A { + #[doc = "1: Divide by 1"] + DIV1 = 1, + #[doc = "2: Divide by 2"] + DIV2 = 2, + #[doc = "4: Divide by 4"] + DIV4 = 4, + #[doc = "8: Divide by 8"] + DIV8 = 8, + #[doc = "16: Divide by 16"] + DIV16 = 16, + #[doc = "32: Divide by 32"] + DIV32 = 32, + #[doc = "64: Divide by 64"] + DIV64 = 64, + #[doc = "128: Divide by 128"] + DIV128 = 128, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CPUDIV_A) -> Self { + variant as _ + } +} +#[doc = "Field `CPUDIV` reader - CPU Clock Division Factor"] +pub struct CPUDIV_R(crate::FieldReader); +impl CPUDIV_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CPUDIV_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 1 => Some(CPUDIV_A::DIV1), + 2 => Some(CPUDIV_A::DIV2), + 4 => Some(CPUDIV_A::DIV4), + 8 => Some(CPUDIV_A::DIV8), + 16 => Some(CPUDIV_A::DIV16), + 32 => Some(CPUDIV_A::DIV32), + 64 => Some(CPUDIV_A::DIV64), + 128 => Some(CPUDIV_A::DIV128), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == CPUDIV_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == CPUDIV_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == CPUDIV_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == CPUDIV_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == CPUDIV_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == CPUDIV_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == CPUDIV_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == CPUDIV_A::DIV128 + } +} +impl core::ops::Deref for CPUDIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPUDIV` writer - CPU Clock Division Factor"] +pub struct CPUDIV_W<'a> { + w: &'a mut W, +} +impl<'a> CPUDIV_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CPUDIV_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Divide by 1"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV1) + } + #[doc = "Divide by 2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV2) + } + #[doc = "Divide by 4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV4) + } + #[doc = "Divide by 8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV8) + } + #[doc = "Divide by 16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV16) + } + #[doc = "Divide by 32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV32) + } + #[doc = "Divide by 64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV64) + } + #[doc = "Divide by 128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV128) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - CPU Clock Division Factor"] + #[inline(always)] + pub fn cpudiv(&self) -> CPUDIV_R { + CPUDIV_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - CPU Clock Division Factor"] + #[inline(always)] + pub fn cpudiv(&mut self) -> CPUDIV_W { + CPUDIV_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CPU Clock Division\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cpudiv](index.html) module"] +pub struct CPUDIV_SPEC; +impl crate::RegisterSpec for CPUDIV_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [cpudiv::R](R) reader structure"] +impl crate::Readable for CPUDIV_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cpudiv::W](W) writer structure"] +impl crate::Writable for CPUDIV_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CPUDIV to value 0x01"] +impl crate::Resettable for CPUDIV_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pac/atsamc21e/src/mclk/intenclr.rs b/pac/atsamc21e/src/mclk/intenclr.rs new file mode 100644 index 000000000000..14feb632dbb7 --- /dev/null +++ b/pac/atsamc21e/src/mclk/intenclr.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CKRDY` reader - Clock Ready Interrupt Enable"] +pub struct CKRDY_R(crate::FieldReader); +impl CKRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CKRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CKRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CKRDY` writer - Clock Ready Interrupt Enable"] +pub struct CKRDY_W<'a> { + w: &'a mut W, +} +impl<'a> CKRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Clock Ready Interrupt Enable"] + #[inline(always)] + pub fn ckrdy(&self) -> CKRDY_R { + CKRDY_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Clock Ready Interrupt Enable"] + #[inline(always)] + pub fn ckrdy(&mut self) -> CKRDY_W { + CKRDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/mclk/intenset.rs b/pac/atsamc21e/src/mclk/intenset.rs new file mode 100644 index 000000000000..f01fcc316d93 --- /dev/null +++ b/pac/atsamc21e/src/mclk/intenset.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CKRDY` reader - Clock Ready Interrupt Enable"] +pub struct CKRDY_R(crate::FieldReader); +impl CKRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CKRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CKRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CKRDY` writer - Clock Ready Interrupt Enable"] +pub struct CKRDY_W<'a> { + w: &'a mut W, +} +impl<'a> CKRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Clock Ready Interrupt Enable"] + #[inline(always)] + pub fn ckrdy(&self) -> CKRDY_R { + CKRDY_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Clock Ready Interrupt Enable"] + #[inline(always)] + pub fn ckrdy(&mut self) -> CKRDY_W { + CKRDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/mclk/intflag.rs b/pac/atsamc21e/src/mclk/intflag.rs new file mode 100644 index 000000000000..cf421d4ac61a --- /dev/null +++ b/pac/atsamc21e/src/mclk/intflag.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CKRDY` reader - Clock Ready"] +pub struct CKRDY_R(crate::FieldReader); +impl CKRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CKRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CKRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CKRDY` writer - Clock Ready"] +pub struct CKRDY_W<'a> { + w: &'a mut W, +} +impl<'a> CKRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Clock Ready"] + #[inline(always)] + pub fn ckrdy(&self) -> CKRDY_R { + CKRDY_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Clock Ready"] + #[inline(always)] + pub fn ckrdy(&mut self) -> CKRDY_W { + CKRDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0x01"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pac/atsamc21e/src/mtb.rs b/pac/atsamc21e/src/mtb.rs new file mode 100644 index 000000000000..01be005c0fb9 --- /dev/null +++ b/pac/atsamc21e/src/mtb.rs @@ -0,0 +1,158 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - MTB Position"] + pub position: crate::Reg, + #[doc = "0x04 - MTB Master"] + pub master: crate::Reg, + #[doc = "0x08 - MTB Flow"] + pub flow: crate::Reg, + #[doc = "0x0c - MTB Base"] + pub base: crate::Reg, + _reserved4: [u8; 0x0ef0], + #[doc = "0xf00 - MTB Integration Mode Control"] + pub itctrl: crate::Reg, + _reserved5: [u8; 0x9c], + #[doc = "0xfa0 - MTB Claim Set"] + pub claimset: crate::Reg, + #[doc = "0xfa4 - MTB Claim Clear"] + pub claimclr: crate::Reg, + _reserved7: [u8; 0x08], + #[doc = "0xfb0 - MTB Lock Access"] + pub lockaccess: crate::Reg, + #[doc = "0xfb4 - MTB Lock Status"] + pub lockstatus: crate::Reg, + #[doc = "0xfb8 - MTB Authentication Status"] + pub authstatus: crate::Reg, + #[doc = "0xfbc - MTB Device Architecture"] + pub devarch: crate::Reg, + _reserved11: [u8; 0x08], + #[doc = "0xfc8 - MTB Device Configuration"] + pub devid: crate::Reg, + #[doc = "0xfcc - MTB Device Type"] + pub devtype: crate::Reg, + #[doc = "0xfd0 - Peripheral Identification 4"] + pub pid4: crate::Reg, + #[doc = "0xfd4 - Peripheral Identification 5"] + pub pid5: crate::Reg, + #[doc = "0xfd8 - Peripheral Identification 6"] + pub pid6: crate::Reg, + #[doc = "0xfdc - Peripheral Identification 7"] + pub pid7: crate::Reg, + #[doc = "0xfe0 - Peripheral Identification 0"] + pub pid0: crate::Reg, + #[doc = "0xfe4 - Peripheral Identification 1"] + pub pid1: crate::Reg, + #[doc = "0xfe8 - Peripheral Identification 2"] + pub pid2: crate::Reg, + #[doc = "0xfec - Peripheral Identification 3"] + pub pid3: crate::Reg, + #[doc = "0xff0 - Component Identification 0"] + pub cid0: crate::Reg, + #[doc = "0xff4 - Component Identification 1"] + pub cid1: crate::Reg, + #[doc = "0xff8 - Component Identification 2"] + pub cid2: crate::Reg, + #[doc = "0xffc - Component Identification 3"] + pub cid3: crate::Reg, +} +#[doc = "POSITION register accessor: an alias for `Reg`"] +pub type POSITION = crate::Reg; +#[doc = "MTB Position"] +pub mod position; +#[doc = "MASTER register accessor: an alias for `Reg`"] +pub type MASTER = crate::Reg; +#[doc = "MTB Master"] +pub mod master; +#[doc = "FLOW register accessor: an alias for `Reg`"] +pub type FLOW = crate::Reg; +#[doc = "MTB Flow"] +pub mod flow; +#[doc = "BASE register accessor: an alias for `Reg`"] +pub type BASE = crate::Reg; +#[doc = "MTB Base"] +pub mod base; +#[doc = "ITCTRL register accessor: an alias for `Reg`"] +pub type ITCTRL = crate::Reg; +#[doc = "MTB Integration Mode Control"] +pub mod itctrl; +#[doc = "CLAIMSET register accessor: an alias for `Reg`"] +pub type CLAIMSET = crate::Reg; +#[doc = "MTB Claim Set"] +pub mod claimset; +#[doc = "CLAIMCLR register accessor: an alias for `Reg`"] +pub type CLAIMCLR = crate::Reg; +#[doc = "MTB Claim Clear"] +pub mod claimclr; +#[doc = "LOCKACCESS register accessor: an alias for `Reg`"] +pub type LOCKACCESS = crate::Reg; +#[doc = "MTB Lock Access"] +pub mod lockaccess; +#[doc = "LOCKSTATUS register accessor: an alias for `Reg`"] +pub type LOCKSTATUS = crate::Reg; +#[doc = "MTB Lock Status"] +pub mod lockstatus; +#[doc = "AUTHSTATUS register accessor: an alias for `Reg`"] +pub type AUTHSTATUS = crate::Reg; +#[doc = "MTB Authentication Status"] +pub mod authstatus; +#[doc = "DEVARCH register accessor: an alias for `Reg`"] +pub type DEVARCH = crate::Reg; +#[doc = "MTB Device Architecture"] +pub mod devarch; +#[doc = "DEVID register accessor: an alias for `Reg`"] +pub type DEVID = crate::Reg; +#[doc = "MTB Device Configuration"] +pub mod devid; +#[doc = "DEVTYPE register accessor: an alias for `Reg`"] +pub type DEVTYPE = crate::Reg; +#[doc = "MTB Device Type"] +pub mod devtype; +#[doc = "PID4 register accessor: an alias for `Reg`"] +pub type PID4 = crate::Reg; +#[doc = "Peripheral Identification 4"] +pub mod pid4; +#[doc = "PID5 register accessor: an alias for `Reg`"] +pub type PID5 = crate::Reg; +#[doc = "Peripheral Identification 5"] +pub mod pid5; +#[doc = "PID6 register accessor: an alias for `Reg`"] +pub type PID6 = crate::Reg; +#[doc = "Peripheral Identification 6"] +pub mod pid6; +#[doc = "PID7 register accessor: an alias for `Reg`"] +pub type PID7 = crate::Reg; +#[doc = "Peripheral Identification 7"] +pub mod pid7; +#[doc = "PID0 register accessor: an alias for `Reg`"] +pub type PID0 = crate::Reg; +#[doc = "Peripheral Identification 0"] +pub mod pid0; +#[doc = "PID1 register accessor: an alias for `Reg`"] +pub type PID1 = crate::Reg; +#[doc = "Peripheral Identification 1"] +pub mod pid1; +#[doc = "PID2 register accessor: an alias for `Reg`"] +pub type PID2 = crate::Reg; +#[doc = "Peripheral Identification 2"] +pub mod pid2; +#[doc = "PID3 register accessor: an alias for `Reg`"] +pub type PID3 = crate::Reg; +#[doc = "Peripheral Identification 3"] +pub mod pid3; +#[doc = "CID0 register accessor: an alias for `Reg`"] +pub type CID0 = crate::Reg; +#[doc = "Component Identification 0"] +pub mod cid0; +#[doc = "CID1 register accessor: an alias for `Reg`"] +pub type CID1 = crate::Reg; +#[doc = "Component Identification 1"] +pub mod cid1; +#[doc = "CID2 register accessor: an alias for `Reg`"] +pub type CID2 = crate::Reg; +#[doc = "Component Identification 2"] +pub mod cid2; +#[doc = "CID3 register accessor: an alias for `Reg`"] +pub type CID3 = crate::Reg; +#[doc = "Component Identification 3"] +pub mod cid3; diff --git a/pac/atsamc21e/src/mtb/authstatus.rs b/pac/atsamc21e/src/mtb/authstatus.rs new file mode 100644 index 000000000000..6fe441e0554d --- /dev/null +++ b/pac/atsamc21e/src/mtb/authstatus.rs @@ -0,0 +1,31 @@ +#[doc = "Register `AUTHSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "MTB Authentication Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [authstatus](index.html) module"] +pub struct AUTHSTATUS_SPEC; +impl crate::RegisterSpec for AUTHSTATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [authstatus::R](R) reader structure"] +impl crate::Readable for AUTHSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets AUTHSTATUS to value 0"] +impl crate::Resettable for AUTHSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/mtb/base.rs b/pac/atsamc21e/src/mtb/base.rs new file mode 100644 index 000000000000..f59b5a97a398 --- /dev/null +++ b/pac/atsamc21e/src/mtb/base.rs @@ -0,0 +1,31 @@ +#[doc = "Register `BASE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "MTB Base\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [base](index.html) module"] +pub struct BASE_SPEC; +impl crate::RegisterSpec for BASE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [base::R](R) reader structure"] +impl crate::Readable for BASE_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets BASE to value 0"] +impl crate::Resettable for BASE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/mtb/cid0.rs b/pac/atsamc21e/src/mtb/cid0.rs new file mode 100644 index 000000000000..e03bd35fa470 --- /dev/null +++ b/pac/atsamc21e/src/mtb/cid0.rs @@ -0,0 +1,31 @@ +#[doc = "Register `CID0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Component Identification 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid0](index.html) module"] +pub struct CID0_SPEC; +impl crate::RegisterSpec for CID0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid0::R](R) reader structure"] +impl crate::Readable for CID0_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID0 to value 0"] +impl crate::Resettable for CID0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/mtb/cid1.rs b/pac/atsamc21e/src/mtb/cid1.rs new file mode 100644 index 000000000000..1cafc8e0fb9a --- /dev/null +++ b/pac/atsamc21e/src/mtb/cid1.rs @@ -0,0 +1,31 @@ +#[doc = "Register `CID1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Component Identification 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid1](index.html) module"] +pub struct CID1_SPEC; +impl crate::RegisterSpec for CID1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid1::R](R) reader structure"] +impl crate::Readable for CID1_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID1 to value 0"] +impl crate::Resettable for CID1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/mtb/cid2.rs b/pac/atsamc21e/src/mtb/cid2.rs new file mode 100644 index 000000000000..6a91e4e23206 --- /dev/null +++ b/pac/atsamc21e/src/mtb/cid2.rs @@ -0,0 +1,31 @@ +#[doc = "Register `CID2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Component Identification 2\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid2](index.html) module"] +pub struct CID2_SPEC; +impl crate::RegisterSpec for CID2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid2::R](R) reader structure"] +impl crate::Readable for CID2_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID2 to value 0"] +impl crate::Resettable for CID2_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/mtb/cid3.rs b/pac/atsamc21e/src/mtb/cid3.rs new file mode 100644 index 000000000000..726290f4ffed --- /dev/null +++ b/pac/atsamc21e/src/mtb/cid3.rs @@ -0,0 +1,31 @@ +#[doc = "Register `CID3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Component Identification 3\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid3](index.html) module"] +pub struct CID3_SPEC; +impl crate::RegisterSpec for CID3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid3::R](R) reader structure"] +impl crate::Readable for CID3_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID3 to value 0"] +impl crate::Resettable for CID3_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/mtb/claimclr.rs b/pac/atsamc21e/src/mtb/claimclr.rs new file mode 100644 index 000000000000..7d0fa5d487b2 --- /dev/null +++ b/pac/atsamc21e/src/mtb/claimclr.rs @@ -0,0 +1,64 @@ +#[doc = "Register `CLAIMCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CLAIMCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MTB Claim Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [claimclr](index.html) module"] +pub struct CLAIMCLR_SPEC; +impl crate::RegisterSpec for CLAIMCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [claimclr::R](R) reader structure"] +impl crate::Readable for CLAIMCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [claimclr::W](W) writer structure"] +impl crate::Writable for CLAIMCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CLAIMCLR to value 0"] +impl crate::Resettable for CLAIMCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/mtb/claimset.rs b/pac/atsamc21e/src/mtb/claimset.rs new file mode 100644 index 000000000000..d5e8ffaa4846 --- /dev/null +++ b/pac/atsamc21e/src/mtb/claimset.rs @@ -0,0 +1,64 @@ +#[doc = "Register `CLAIMSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CLAIMSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MTB Claim Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [claimset](index.html) module"] +pub struct CLAIMSET_SPEC; +impl crate::RegisterSpec for CLAIMSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [claimset::R](R) reader structure"] +impl crate::Readable for CLAIMSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [claimset::W](W) writer structure"] +impl crate::Writable for CLAIMSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CLAIMSET to value 0"] +impl crate::Resettable for CLAIMSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/mtb/devarch.rs b/pac/atsamc21e/src/mtb/devarch.rs new file mode 100644 index 000000000000..b79480753d5e --- /dev/null +++ b/pac/atsamc21e/src/mtb/devarch.rs @@ -0,0 +1,31 @@ +#[doc = "Register `DEVARCH` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "MTB Device Architecture\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [devarch](index.html) module"] +pub struct DEVARCH_SPEC; +impl crate::RegisterSpec for DEVARCH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [devarch::R](R) reader structure"] +impl crate::Readable for DEVARCH_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DEVARCH to value 0"] +impl crate::Resettable for DEVARCH_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/mtb/devid.rs b/pac/atsamc21e/src/mtb/devid.rs new file mode 100644 index 000000000000..21c15d952032 --- /dev/null +++ b/pac/atsamc21e/src/mtb/devid.rs @@ -0,0 +1,31 @@ +#[doc = "Register `DEVID` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "MTB Device Configuration\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [devid](index.html) module"] +pub struct DEVID_SPEC; +impl crate::RegisterSpec for DEVID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [devid::R](R) reader structure"] +impl crate::Readable for DEVID_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DEVID to value 0"] +impl crate::Resettable for DEVID_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/mtb/devtype.rs b/pac/atsamc21e/src/mtb/devtype.rs new file mode 100644 index 000000000000..c00d66b98a2f --- /dev/null +++ b/pac/atsamc21e/src/mtb/devtype.rs @@ -0,0 +1,31 @@ +#[doc = "Register `DEVTYPE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "MTB Device Type\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [devtype](index.html) module"] +pub struct DEVTYPE_SPEC; +impl crate::RegisterSpec for DEVTYPE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [devtype::R](R) reader structure"] +impl crate::Readable for DEVTYPE_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DEVTYPE to value 0"] +impl crate::Resettable for DEVTYPE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/mtb/flow.rs b/pac/atsamc21e/src/mtb/flow.rs new file mode 100644 index 000000000000..1b94efdb89b8 --- /dev/null +++ b/pac/atsamc21e/src/mtb/flow.rs @@ -0,0 +1,197 @@ +#[doc = "Register `FLOW` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FLOW` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `AUTOSTOP` reader - Auto Stop Tracing"] +pub struct AUTOSTOP_R(crate::FieldReader); +impl AUTOSTOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AUTOSTOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AUTOSTOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AUTOSTOP` writer - Auto Stop Tracing"] +pub struct AUTOSTOP_W<'a> { + w: &'a mut W, +} +impl<'a> AUTOSTOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `AUTOHALT` reader - Auto Halt Request"] +pub struct AUTOHALT_R(crate::FieldReader); +impl AUTOHALT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AUTOHALT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AUTOHALT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AUTOHALT` writer - Auto Halt Request"] +pub struct AUTOHALT_W<'a> { + w: &'a mut W, +} +impl<'a> AUTOHALT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WATERMARK` reader - Watermark value"] +pub struct WATERMARK_R(crate::FieldReader); +impl WATERMARK_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + WATERMARK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WATERMARK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WATERMARK` writer - Watermark value"] +pub struct WATERMARK_W<'a> { + w: &'a mut W, +} +impl<'a> WATERMARK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1fff_ffff << 3)) | ((value as u32 & 0x1fff_ffff) << 3); + self.w + } +} +impl R { + #[doc = "Bit 0 - Auto Stop Tracing"] + #[inline(always)] + pub fn autostop(&self) -> AUTOSTOP_R { + AUTOSTOP_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Auto Halt Request"] + #[inline(always)] + pub fn autohalt(&self) -> AUTOHALT_R { + AUTOHALT_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 3:31 - Watermark value"] + #[inline(always)] + pub fn watermark(&self) -> WATERMARK_R { + WATERMARK_R::new(((self.bits >> 3) & 0x1fff_ffff) as u32) + } +} +impl W { + #[doc = "Bit 0 - Auto Stop Tracing"] + #[inline(always)] + pub fn autostop(&mut self) -> AUTOSTOP_W { + AUTOSTOP_W { w: self } + } + #[doc = "Bit 1 - Auto Halt Request"] + #[inline(always)] + pub fn autohalt(&mut self) -> AUTOHALT_W { + AUTOHALT_W { w: self } + } + #[doc = "Bits 3:31 - Watermark value"] + #[inline(always)] + pub fn watermark(&mut self) -> WATERMARK_W { + WATERMARK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MTB Flow\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [flow](index.html) module"] +pub struct FLOW_SPEC; +impl crate::RegisterSpec for FLOW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [flow::R](R) reader structure"] +impl crate::Readable for FLOW_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [flow::W](W) writer structure"] +impl crate::Writable for FLOW_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets FLOW to value 0"] +impl crate::Resettable for FLOW_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/mtb/itctrl.rs b/pac/atsamc21e/src/mtb/itctrl.rs new file mode 100644 index 000000000000..a48364e0b062 --- /dev/null +++ b/pac/atsamc21e/src/mtb/itctrl.rs @@ -0,0 +1,64 @@ +#[doc = "Register `ITCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ITCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MTB Integration Mode Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [itctrl](index.html) module"] +pub struct ITCTRL_SPEC; +impl crate::RegisterSpec for ITCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [itctrl::R](R) reader structure"] +impl crate::Readable for ITCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [itctrl::W](W) writer structure"] +impl crate::Writable for ITCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ITCTRL to value 0"] +impl crate::Resettable for ITCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/mtb/lockaccess.rs b/pac/atsamc21e/src/mtb/lockaccess.rs new file mode 100644 index 000000000000..0400690beade --- /dev/null +++ b/pac/atsamc21e/src/mtb/lockaccess.rs @@ -0,0 +1,64 @@ +#[doc = "Register `LOCKACCESS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `LOCKACCESS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MTB Lock Access\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lockaccess](index.html) module"] +pub struct LOCKACCESS_SPEC; +impl crate::RegisterSpec for LOCKACCESS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [lockaccess::R](R) reader structure"] +impl crate::Readable for LOCKACCESS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [lockaccess::W](W) writer structure"] +impl crate::Writable for LOCKACCESS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets LOCKACCESS to value 0"] +impl crate::Resettable for LOCKACCESS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/mtb/lockstatus.rs b/pac/atsamc21e/src/mtb/lockstatus.rs new file mode 100644 index 000000000000..0c68410c6944 --- /dev/null +++ b/pac/atsamc21e/src/mtb/lockstatus.rs @@ -0,0 +1,31 @@ +#[doc = "Register `LOCKSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "MTB Lock Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lockstatus](index.html) module"] +pub struct LOCKSTATUS_SPEC; +impl crate::RegisterSpec for LOCKSTATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [lockstatus::R](R) reader structure"] +impl crate::Readable for LOCKSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets LOCKSTATUS to value 0"] +impl crate::Resettable for LOCKSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/mtb/master.rs b/pac/atsamc21e/src/mtb/master.rs new file mode 100644 index 000000000000..0190ca1ce909 --- /dev/null +++ b/pac/atsamc21e/src/mtb/master.rs @@ -0,0 +1,385 @@ +#[doc = "Register `MASTER` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MASTER` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MASK` reader - Maximum Value of the Trace Buffer in SRAM"] +pub struct MASK_R(crate::FieldReader); +impl MASK_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MASK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MASK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MASK` writer - Maximum Value of the Trace Buffer in SRAM"] +pub struct MASK_W<'a> { + w: &'a mut W, +} +impl<'a> MASK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f); + self.w + } +} +#[doc = "Field `TSTARTEN` reader - Trace Start Input Enable"] +pub struct TSTARTEN_R(crate::FieldReader); +impl TSTARTEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSTARTEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSTARTEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSTARTEN` writer - Trace Start Input Enable"] +pub struct TSTARTEN_W<'a> { + w: &'a mut W, +} +impl<'a> TSTARTEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `TSTOPEN` reader - Trace Stop Input Enable"] +pub struct TSTOPEN_R(crate::FieldReader); +impl TSTOPEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSTOPEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSTOPEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSTOPEN` writer - Trace Stop Input Enable"] +pub struct TSTOPEN_W<'a> { + w: &'a mut W, +} +impl<'a> TSTOPEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `SFRWPRIV` reader - Special Function Register Write Privilege"] +pub struct SFRWPRIV_R(crate::FieldReader); +impl SFRWPRIV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SFRWPRIV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SFRWPRIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SFRWPRIV` writer - Special Function Register Write Privilege"] +pub struct SFRWPRIV_W<'a> { + w: &'a mut W, +} +impl<'a> SFRWPRIV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `RAMPRIV` reader - SRAM Privilege"] +pub struct RAMPRIV_R(crate::FieldReader); +impl RAMPRIV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RAMPRIV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RAMPRIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RAMPRIV` writer - SRAM Privilege"] +pub struct RAMPRIV_W<'a> { + w: &'a mut W, +} +impl<'a> RAMPRIV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `HALTREQ` reader - Halt Request"] +pub struct HALTREQ_R(crate::FieldReader); +impl HALTREQ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HALTREQ_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HALTREQ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HALTREQ` writer - Halt Request"] +pub struct HALTREQ_W<'a> { + w: &'a mut W, +} +impl<'a> HALTREQ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `EN` reader - Main Trace Enable"] +pub struct EN_R(crate::FieldReader); +impl EN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EN` writer - Main Trace Enable"] +pub struct EN_W<'a> { + w: &'a mut W, +} +impl<'a> EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Maximum Value of the Trace Buffer in SRAM"] + #[inline(always)] + pub fn mask(&self) -> MASK_R { + MASK_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bit 5 - Trace Start Input Enable"] + #[inline(always)] + pub fn tstarten(&self) -> TSTARTEN_R { + TSTARTEN_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Trace Stop Input Enable"] + #[inline(always)] + pub fn tstopen(&self) -> TSTOPEN_R { + TSTOPEN_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Special Function Register Write Privilege"] + #[inline(always)] + pub fn sfrwpriv(&self) -> SFRWPRIV_R { + SFRWPRIV_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - SRAM Privilege"] + #[inline(always)] + pub fn rampriv(&self) -> RAMPRIV_R { + RAMPRIV_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Halt Request"] + #[inline(always)] + pub fn haltreq(&self) -> HALTREQ_R { + HALTREQ_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 31 - Main Trace Enable"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Maximum Value of the Trace Buffer in SRAM"] + #[inline(always)] + pub fn mask(&mut self) -> MASK_W { + MASK_W { w: self } + } + #[doc = "Bit 5 - Trace Start Input Enable"] + #[inline(always)] + pub fn tstarten(&mut self) -> TSTARTEN_W { + TSTARTEN_W { w: self } + } + #[doc = "Bit 6 - Trace Stop Input Enable"] + #[inline(always)] + pub fn tstopen(&mut self) -> TSTOPEN_W { + TSTOPEN_W { w: self } + } + #[doc = "Bit 7 - Special Function Register Write Privilege"] + #[inline(always)] + pub fn sfrwpriv(&mut self) -> SFRWPRIV_W { + SFRWPRIV_W { w: self } + } + #[doc = "Bit 8 - SRAM Privilege"] + #[inline(always)] + pub fn rampriv(&mut self) -> RAMPRIV_W { + RAMPRIV_W { w: self } + } + #[doc = "Bit 9 - Halt Request"] + #[inline(always)] + pub fn haltreq(&mut self) -> HALTREQ_W { + HALTREQ_W { w: self } + } + #[doc = "Bit 31 - Main Trace Enable"] + #[inline(always)] + pub fn en(&mut self) -> EN_W { + EN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MTB Master\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [master](index.html) module"] +pub struct MASTER_SPEC; +impl crate::RegisterSpec for MASTER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [master::R](R) reader structure"] +impl crate::Readable for MASTER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [master::W](W) writer structure"] +impl crate::Writable for MASTER_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets MASTER to value 0"] +impl crate::Resettable for MASTER_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/mtb/pid0.rs b/pac/atsamc21e/src/mtb/pid0.rs new file mode 100644 index 000000000000..0a7183189fe5 --- /dev/null +++ b/pac/atsamc21e/src/mtb/pid0.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid0](index.html) module"] +pub struct PID0_SPEC; +impl crate::RegisterSpec for PID0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid0::R](R) reader structure"] +impl crate::Readable for PID0_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID0 to value 0"] +impl crate::Resettable for PID0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/mtb/pid1.rs b/pac/atsamc21e/src/mtb/pid1.rs new file mode 100644 index 000000000000..7d6381917f5d --- /dev/null +++ b/pac/atsamc21e/src/mtb/pid1.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid1](index.html) module"] +pub struct PID1_SPEC; +impl crate::RegisterSpec for PID1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid1::R](R) reader structure"] +impl crate::Readable for PID1_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID1 to value 0"] +impl crate::Resettable for PID1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/mtb/pid2.rs b/pac/atsamc21e/src/mtb/pid2.rs new file mode 100644 index 000000000000..74c230346b4c --- /dev/null +++ b/pac/atsamc21e/src/mtb/pid2.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 2\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid2](index.html) module"] +pub struct PID2_SPEC; +impl crate::RegisterSpec for PID2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid2::R](R) reader structure"] +impl crate::Readable for PID2_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID2 to value 0"] +impl crate::Resettable for PID2_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/mtb/pid3.rs b/pac/atsamc21e/src/mtb/pid3.rs new file mode 100644 index 000000000000..e9e922aa2f21 --- /dev/null +++ b/pac/atsamc21e/src/mtb/pid3.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 3\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid3](index.html) module"] +pub struct PID3_SPEC; +impl crate::RegisterSpec for PID3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid3::R](R) reader structure"] +impl crate::Readable for PID3_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID3 to value 0"] +impl crate::Resettable for PID3_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/mtb/pid4.rs b/pac/atsamc21e/src/mtb/pid4.rs new file mode 100644 index 000000000000..89074d3c2692 --- /dev/null +++ b/pac/atsamc21e/src/mtb/pid4.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID4` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 4\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid4](index.html) module"] +pub struct PID4_SPEC; +impl crate::RegisterSpec for PID4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid4::R](R) reader structure"] +impl crate::Readable for PID4_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID4 to value 0"] +impl crate::Resettable for PID4_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/mtb/pid5.rs b/pac/atsamc21e/src/mtb/pid5.rs new file mode 100644 index 000000000000..d343d4800b95 --- /dev/null +++ b/pac/atsamc21e/src/mtb/pid5.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID5` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 5\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid5](index.html) module"] +pub struct PID5_SPEC; +impl crate::RegisterSpec for PID5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid5::R](R) reader structure"] +impl crate::Readable for PID5_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID5 to value 0"] +impl crate::Resettable for PID5_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/mtb/pid6.rs b/pac/atsamc21e/src/mtb/pid6.rs new file mode 100644 index 000000000000..55cc2b8b5861 --- /dev/null +++ b/pac/atsamc21e/src/mtb/pid6.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID6` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 6\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid6](index.html) module"] +pub struct PID6_SPEC; +impl crate::RegisterSpec for PID6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid6::R](R) reader structure"] +impl crate::Readable for PID6_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID6 to value 0"] +impl crate::Resettable for PID6_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/mtb/pid7.rs b/pac/atsamc21e/src/mtb/pid7.rs new file mode 100644 index 000000000000..77664d4f2f95 --- /dev/null +++ b/pac/atsamc21e/src/mtb/pid7.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID7` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 7\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid7](index.html) module"] +pub struct PID7_SPEC; +impl crate::RegisterSpec for PID7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid7::R](R) reader structure"] +impl crate::Readable for PID7_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID7 to value 0"] +impl crate::Resettable for PID7_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/mtb/position.rs b/pac/atsamc21e/src/mtb/position.rs new file mode 100644 index 000000000000..4bab0425b142 --- /dev/null +++ b/pac/atsamc21e/src/mtb/position.rs @@ -0,0 +1,150 @@ +#[doc = "Register `POSITION` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `POSITION` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WRAP` reader - Pointer Value Wraps"] +pub struct WRAP_R(crate::FieldReader); +impl WRAP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WRAP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WRAP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WRAP` writer - Pointer Value Wraps"] +pub struct WRAP_W<'a> { + w: &'a mut W, +} +impl<'a> WRAP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `POINTER` reader - Trace Packet Location Pointer"] +pub struct POINTER_R(crate::FieldReader); +impl POINTER_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + POINTER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for POINTER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `POINTER` writer - Trace Packet Location Pointer"] +pub struct POINTER_W<'a> { + w: &'a mut W, +} +impl<'a> POINTER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1fff_ffff << 3)) | ((value as u32 & 0x1fff_ffff) << 3); + self.w + } +} +impl R { + #[doc = "Bit 2 - Pointer Value Wraps"] + #[inline(always)] + pub fn wrap(&self) -> WRAP_R { + WRAP_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 3:31 - Trace Packet Location Pointer"] + #[inline(always)] + pub fn pointer(&self) -> POINTER_R { + POINTER_R::new(((self.bits >> 3) & 0x1fff_ffff) as u32) + } +} +impl W { + #[doc = "Bit 2 - Pointer Value Wraps"] + #[inline(always)] + pub fn wrap(&mut self) -> WRAP_W { + WRAP_W { w: self } + } + #[doc = "Bits 3:31 - Trace Packet Location Pointer"] + #[inline(always)] + pub fn pointer(&mut self) -> POINTER_W { + POINTER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MTB Position\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [position](index.html) module"] +pub struct POSITION_SPEC; +impl crate::RegisterSpec for POSITION_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [position::R](R) reader structure"] +impl crate::Readable for POSITION_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [position::W](W) writer structure"] +impl crate::Writable for POSITION_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets POSITION to value 0"] +impl crate::Resettable for POSITION_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/nvmctrl.rs b/pac/atsamc21e/src/nvmctrl.rs new file mode 100644 index 000000000000..2c017caaef9c --- /dev/null +++ b/pac/atsamc21e/src/nvmctrl.rs @@ -0,0 +1,76 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + _reserved1: [u8; 0x02], + #[doc = "0x04 - Control B"] + pub ctrlb: crate::Reg, + #[doc = "0x08 - NVM Parameter"] + pub param: crate::Reg, + #[doc = "0x0c - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + _reserved4: [u8; 0x03], + #[doc = "0x10 - Interrupt Enable Set"] + pub intenset: crate::Reg, + _reserved5: [u8; 0x03], + #[doc = "0x14 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved6: [u8; 0x03], + #[doc = "0x18 - Status"] + pub status: crate::Reg, + _reserved7: [u8; 0x02], + #[doc = "0x1c - Address"] + pub addr: crate::Reg, + #[doc = "0x20 - Lock Section"] + pub lock: crate::Reg, + _reserved9: [u8; 0x06], + #[doc = "0x28 - Page Buffer Load Data 0"] + pub pbldata0: crate::Reg, + #[doc = "0x2c - Page Buffer Load Data 1"] + pub pbldata1: crate::Reg, +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "Control B"] +pub mod ctrlb; +#[doc = "PARAM register accessor: an alias for `Reg`"] +pub type PARAM = crate::Reg; +#[doc = "NVM Parameter"] +pub mod param; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "ADDR register accessor: an alias for `Reg`"] +pub type ADDR = crate::Reg; +#[doc = "Address"] +pub mod addr; +#[doc = "LOCK register accessor: an alias for `Reg`"] +pub type LOCK = crate::Reg; +#[doc = "Lock Section"] +pub mod lock; +#[doc = "PBLDATA0 register accessor: an alias for `Reg`"] +pub type PBLDATA0 = crate::Reg; +#[doc = "Page Buffer Load Data 0"] +pub mod pbldata0; +#[doc = "PBLDATA1 register accessor: an alias for `Reg`"] +pub type PBLDATA1 = crate::Reg; +#[doc = "Page Buffer Load Data 1"] +pub mod pbldata1; diff --git a/pac/atsamc21e/src/nvmctrl/addr.rs b/pac/atsamc21e/src/nvmctrl/addr.rs new file mode 100644 index 000000000000..74ed27736dac --- /dev/null +++ b/pac/atsamc21e/src/nvmctrl/addr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `ADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ADDR` reader - NVM Address"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - NVM Address"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x003f_ffff) | (value as u32 & 0x003f_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:21 - NVM Address"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new((self.bits & 0x003f_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:21 - NVM Address"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [addr](index.html) module"] +pub struct ADDR_SPEC; +impl crate::RegisterSpec for ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [addr::R](R) reader structure"] +impl crate::Readable for ADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [addr::W](W) writer structure"] +impl crate::Writable for ADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ADDR to value 0"] +impl crate::Resettable for ADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/nvmctrl/ctrla.rs b/pac/atsamc21e/src/nvmctrl/ctrla.rs new file mode 100644 index 000000000000..89f175771e4d --- /dev/null +++ b/pac/atsamc21e/src/nvmctrl/ctrla.rs @@ -0,0 +1,394 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "2: Erase Row - Erases the row addressed by the ADDR register."] + ER = 2, + #[doc = "4: Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register."] + WP = 4, + #[doc = "5: Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row."] + EAR = 5, + #[doc = "6: Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row."] + WAP = 6, + #[doc = "10: Security Flow Command"] + SF = 10, + #[doc = "15: Write lockbits"] + WL = 15, + #[doc = "26: RWW EEPROM area Erase Row - Erases the row addressed by the ADDR register."] + RWWEEER = 26, + #[doc = "28: RWW EEPROM Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register."] + RWWEEWP = 28, + #[doc = "64: Lock Region - Locks the region containing the address location in the ADDR register."] + LR = 64, + #[doc = "65: Unlock Region - Unlocks the region containing the address location in the ADDR register."] + UR = 65, + #[doc = "66: Sets the power reduction mode."] + SPRM = 66, + #[doc = "67: Clears the power reduction mode."] + CPRM = 67, + #[doc = "68: Page Buffer Clear - Clears the page buffer."] + PBC = 68, + #[doc = "69: Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row."] + SSB = 69, + #[doc = "70: Invalidate all cache lines."] + INVALL = 70, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 2 => Some(CMD_A::ER), + 4 => Some(CMD_A::WP), + 5 => Some(CMD_A::EAR), + 6 => Some(CMD_A::WAP), + 10 => Some(CMD_A::SF), + 15 => Some(CMD_A::WL), + 26 => Some(CMD_A::RWWEEER), + 28 => Some(CMD_A::RWWEEWP), + 64 => Some(CMD_A::LR), + 65 => Some(CMD_A::UR), + 66 => Some(CMD_A::SPRM), + 67 => Some(CMD_A::CPRM), + 68 => Some(CMD_A::PBC), + 69 => Some(CMD_A::SSB), + 70 => Some(CMD_A::INVALL), + _ => None, + } + } + #[doc = "Checks if the value of the field is `ER`"] + #[inline(always)] + pub fn is_er(&self) -> bool { + **self == CMD_A::ER + } + #[doc = "Checks if the value of the field is `WP`"] + #[inline(always)] + pub fn is_wp(&self) -> bool { + **self == CMD_A::WP + } + #[doc = "Checks if the value of the field is `EAR`"] + #[inline(always)] + pub fn is_ear(&self) -> bool { + **self == CMD_A::EAR + } + #[doc = "Checks if the value of the field is `WAP`"] + #[inline(always)] + pub fn is_wap(&self) -> bool { + **self == CMD_A::WAP + } + #[doc = "Checks if the value of the field is `SF`"] + #[inline(always)] + pub fn is_sf(&self) -> bool { + **self == CMD_A::SF + } + #[doc = "Checks if the value of the field is `WL`"] + #[inline(always)] + pub fn is_wl(&self) -> bool { + **self == CMD_A::WL + } + #[doc = "Checks if the value of the field is `RWWEEER`"] + #[inline(always)] + pub fn is_rwweeer(&self) -> bool { + **self == CMD_A::RWWEEER + } + #[doc = "Checks if the value of the field is `RWWEEWP`"] + #[inline(always)] + pub fn is_rwweewp(&self) -> bool { + **self == CMD_A::RWWEEWP + } + #[doc = "Checks if the value of the field is `LR`"] + #[inline(always)] + pub fn is_lr(&self) -> bool { + **self == CMD_A::LR + } + #[doc = "Checks if the value of the field is `UR`"] + #[inline(always)] + pub fn is_ur(&self) -> bool { + **self == CMD_A::UR + } + #[doc = "Checks if the value of the field is `SPRM`"] + #[inline(always)] + pub fn is_sprm(&self) -> bool { + **self == CMD_A::SPRM + } + #[doc = "Checks if the value of the field is `CPRM`"] + #[inline(always)] + pub fn is_cprm(&self) -> bool { + **self == CMD_A::CPRM + } + #[doc = "Checks if the value of the field is `PBC`"] + #[inline(always)] + pub fn is_pbc(&self) -> bool { + **self == CMD_A::PBC + } + #[doc = "Checks if the value of the field is `SSB`"] + #[inline(always)] + pub fn is_ssb(&self) -> bool { + **self == CMD_A::SSB + } + #[doc = "Checks if the value of the field is `INVALL`"] + #[inline(always)] + pub fn is_invall(&self) -> bool { + **self == CMD_A::INVALL + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Erase Row - Erases the row addressed by the ADDR register."] + #[inline(always)] + pub fn er(self) -> &'a mut W { + self.variant(CMD_A::ER) + } + #[doc = "Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register."] + #[inline(always)] + pub fn wp(self) -> &'a mut W { + self.variant(CMD_A::WP) + } + #[doc = "Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row."] + #[inline(always)] + pub fn ear(self) -> &'a mut W { + self.variant(CMD_A::EAR) + } + #[doc = "Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row."] + #[inline(always)] + pub fn wap(self) -> &'a mut W { + self.variant(CMD_A::WAP) + } + #[doc = "Security Flow Command"] + #[inline(always)] + pub fn sf(self) -> &'a mut W { + self.variant(CMD_A::SF) + } + #[doc = "Write lockbits"] + #[inline(always)] + pub fn wl(self) -> &'a mut W { + self.variant(CMD_A::WL) + } + #[doc = "RWW EEPROM area Erase Row - Erases the row addressed by the ADDR register."] + #[inline(always)] + pub fn rwweeer(self) -> &'a mut W { + self.variant(CMD_A::RWWEEER) + } + #[doc = "RWW EEPROM Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register."] + #[inline(always)] + pub fn rwweewp(self) -> &'a mut W { + self.variant(CMD_A::RWWEEWP) + } + #[doc = "Lock Region - Locks the region containing the address location in the ADDR register."] + #[inline(always)] + pub fn lr(self) -> &'a mut W { + self.variant(CMD_A::LR) + } + #[doc = "Unlock Region - Unlocks the region containing the address location in the ADDR register."] + #[inline(always)] + pub fn ur(self) -> &'a mut W { + self.variant(CMD_A::UR) + } + #[doc = "Sets the power reduction mode."] + #[inline(always)] + pub fn sprm(self) -> &'a mut W { + self.variant(CMD_A::SPRM) + } + #[doc = "Clears the power reduction mode."] + #[inline(always)] + pub fn cprm(self) -> &'a mut W { + self.variant(CMD_A::CPRM) + } + #[doc = "Page Buffer Clear - Clears the page buffer."] + #[inline(always)] + pub fn pbc(self) -> &'a mut W { + self.variant(CMD_A::PBC) + } + #[doc = "Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row."] + #[inline(always)] + pub fn ssb(self) -> &'a mut W { + self.variant(CMD_A::SSB) + } + #[doc = "Invalidate all cache lines."] + #[inline(always)] + pub fn invall(self) -> &'a mut W { + self.variant(CMD_A::INVALL) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x7f) | (value as u16 & 0x7f); + self.w + } +} +#[doc = "Command Execution\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMDEX_A { + #[doc = "165: Execution Key"] + KEY = 165, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMDEX_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMDEX` reader - Command Execution"] +pub struct CMDEX_R(crate::FieldReader); +impl CMDEX_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMDEX_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 165 => Some(CMDEX_A::KEY), + _ => None, + } + } + #[doc = "Checks if the value of the field is `KEY`"] + #[inline(always)] + pub fn is_key(&self) -> bool { + **self == CMDEX_A::KEY + } +} +impl core::ops::Deref for CMDEX_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMDEX` writer - Command Execution"] +pub struct CMDEX_W<'a> { + w: &'a mut W, +} +impl<'a> CMDEX_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMDEX_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Execution Key"] + #[inline(always)] + pub fn key(self) -> &'a mut W { + self.variant(CMDEX_A::KEY) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u16 & 0xff) << 8); + self.w + } +} +impl R { + #[doc = "Bits 0:6 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bits 8:15 - Command Execution"] + #[inline(always)] + pub fn cmdex(&self) -> CMDEX_R { + CMDEX_R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:6 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Bits 8:15 - Command Execution"] + #[inline(always)] + pub fn cmdex(&mut self) -> CMDEX_W { + CMDEX_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/nvmctrl/ctrlb.rs b/pac/atsamc21e/src/nvmctrl/ctrlb.rs new file mode 100644 index 000000000000..6162d0d4ade0 --- /dev/null +++ b/pac/atsamc21e/src/nvmctrl/ctrlb.rs @@ -0,0 +1,447 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "NVM Read Wait States\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum RWS_A { + #[doc = "0: Single Auto Wait State"] + SINGLE = 0, + #[doc = "1: Half Auto Wait State"] + HALF = 1, + #[doc = "2: Dual Auto Wait State"] + DUAL = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RWS_A) -> Self { + variant as _ + } +} +#[doc = "Field `RWS` reader - NVM Read Wait States"] +pub struct RWS_R(crate::FieldReader); +impl RWS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RWS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(RWS_A::SINGLE), + 1 => Some(RWS_A::HALF), + 2 => Some(RWS_A::DUAL), + _ => None, + } + } + #[doc = "Checks if the value of the field is `SINGLE`"] + #[inline(always)] + pub fn is_single(&self) -> bool { + **self == RWS_A::SINGLE + } + #[doc = "Checks if the value of the field is `HALF`"] + #[inline(always)] + pub fn is_half(&self) -> bool { + **self == RWS_A::HALF + } + #[doc = "Checks if the value of the field is `DUAL`"] + #[inline(always)] + pub fn is_dual(&self) -> bool { + **self == RWS_A::DUAL + } +} +impl core::ops::Deref for RWS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RWS` writer - NVM Read Wait States"] +pub struct RWS_W<'a> { + w: &'a mut W, +} +impl<'a> RWS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RWS_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Single Auto Wait State"] + #[inline(always)] + pub fn single(self) -> &'a mut W { + self.variant(RWS_A::SINGLE) + } + #[doc = "Half Auto Wait State"] + #[inline(always)] + pub fn half(self) -> &'a mut W { + self.variant(RWS_A::HALF) + } + #[doc = "Dual Auto Wait State"] + #[inline(always)] + pub fn dual(self) -> &'a mut W { + self.variant(RWS_A::DUAL) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 1)) | ((value as u32 & 0x0f) << 1); + self.w + } +} +#[doc = "Field `MANW` reader - Manual Write"] +pub struct MANW_R(crate::FieldReader); +impl MANW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MANW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MANW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MANW` writer - Manual Write"] +pub struct MANW_W<'a> { + w: &'a mut W, +} +impl<'a> MANW_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Power Reduction Mode during Sleep\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SLEEPPRM_A { + #[doc = "0: NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access."] + WAKEONACCESS = 0, + #[doc = "1: NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep."] + WAKEUPINSTANT = 1, + #[doc = "3: Auto power reduction disabled."] + DISABLED = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SLEEPPRM_A) -> Self { + variant as _ + } +} +#[doc = "Field `SLEEPPRM` reader - Power Reduction Mode during Sleep"] +pub struct SLEEPPRM_R(crate::FieldReader); +impl SLEEPPRM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SLEEPPRM_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SLEEPPRM_A::WAKEONACCESS), + 1 => Some(SLEEPPRM_A::WAKEUPINSTANT), + 3 => Some(SLEEPPRM_A::DISABLED), + _ => None, + } + } + #[doc = "Checks if the value of the field is `WAKEONACCESS`"] + #[inline(always)] + pub fn is_wakeonaccess(&self) -> bool { + **self == SLEEPPRM_A::WAKEONACCESS + } + #[doc = "Checks if the value of the field is `WAKEUPINSTANT`"] + #[inline(always)] + pub fn is_wakeupinstant(&self) -> bool { + **self == SLEEPPRM_A::WAKEUPINSTANT + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + **self == SLEEPPRM_A::DISABLED + } +} +impl core::ops::Deref for SLEEPPRM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLEEPPRM` writer - Power Reduction Mode during Sleep"] +pub struct SLEEPPRM_W<'a> { + w: &'a mut W, +} +impl<'a> SLEEPPRM_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SLEEPPRM_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access."] + #[inline(always)] + pub fn wakeonaccess(self) -> &'a mut W { + self.variant(SLEEPPRM_A::WAKEONACCESS) + } + #[doc = "NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep."] + #[inline(always)] + pub fn wakeupinstant(self) -> &'a mut W { + self.variant(SLEEPPRM_A::WAKEUPINSTANT) + } + #[doc = "Auto power reduction disabled."] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(SLEEPPRM_A::DISABLED) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 8)) | ((value as u32 & 0x03) << 8); + self.w + } +} +#[doc = "NVMCTRL Read Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum READMODE_A { + #[doc = "0: The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance."] + NO_MISS_PENALTY = 0, + #[doc = "1: Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time."] + LOW_POWER = 1, + #[doc = "2: The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings."] + DETERMINISTIC = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: READMODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `READMODE` reader - NVMCTRL Read Mode"] +pub struct READMODE_R(crate::FieldReader); +impl READMODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + READMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(READMODE_A::NO_MISS_PENALTY), + 1 => Some(READMODE_A::LOW_POWER), + 2 => Some(READMODE_A::DETERMINISTIC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NO_MISS_PENALTY`"] + #[inline(always)] + pub fn is_no_miss_penalty(&self) -> bool { + **self == READMODE_A::NO_MISS_PENALTY + } + #[doc = "Checks if the value of the field is `LOW_POWER`"] + #[inline(always)] + pub fn is_low_power(&self) -> bool { + **self == READMODE_A::LOW_POWER + } + #[doc = "Checks if the value of the field is `DETERMINISTIC`"] + #[inline(always)] + pub fn is_deterministic(&self) -> bool { + **self == READMODE_A::DETERMINISTIC + } +} +impl core::ops::Deref for READMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `READMODE` writer - NVMCTRL Read Mode"] +pub struct READMODE_W<'a> { + w: &'a mut W, +} +impl<'a> READMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: READMODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance."] + #[inline(always)] + pub fn no_miss_penalty(self) -> &'a mut W { + self.variant(READMODE_A::NO_MISS_PENALTY) + } + #[doc = "Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time."] + #[inline(always)] + pub fn low_power(self) -> &'a mut W { + self.variant(READMODE_A::LOW_POWER) + } + #[doc = "The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings."] + #[inline(always)] + pub fn deterministic(self) -> &'a mut W { + self.variant(READMODE_A::DETERMINISTIC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Field `CACHEDIS` reader - Cache Disable"] +pub struct CACHEDIS_R(crate::FieldReader); +impl CACHEDIS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CACHEDIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CACHEDIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CACHEDIS` writer - Cache Disable"] +pub struct CACHEDIS_W<'a> { + w: &'a mut W, +} +impl<'a> CACHEDIS_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 18)) | ((value as u32 & 0x03) << 18); + self.w + } +} +impl R { + #[doc = "Bits 1:4 - NVM Read Wait States"] + #[inline(always)] + pub fn rws(&self) -> RWS_R { + RWS_R::new(((self.bits >> 1) & 0x0f) as u8) + } + #[doc = "Bit 7 - Manual Write"] + #[inline(always)] + pub fn manw(&self) -> MANW_R { + MANW_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:9 - Power Reduction Mode during Sleep"] + #[inline(always)] + pub fn sleepprm(&self) -> SLEEPPRM_R { + SLEEPPRM_R::new(((self.bits >> 8) & 0x03) as u8) + } + #[doc = "Bits 16:17 - NVMCTRL Read Mode"] + #[inline(always)] + pub fn readmode(&self) -> READMODE_R { + READMODE_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bits 18:19 - Cache Disable"] + #[inline(always)] + pub fn cachedis(&self) -> CACHEDIS_R { + CACHEDIS_R::new(((self.bits >> 18) & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 1:4 - NVM Read Wait States"] + #[inline(always)] + pub fn rws(&mut self) -> RWS_W { + RWS_W { w: self } + } + #[doc = "Bit 7 - Manual Write"] + #[inline(always)] + pub fn manw(&mut self) -> MANW_W { + MANW_W { w: self } + } + #[doc = "Bits 8:9 - Power Reduction Mode during Sleep"] + #[inline(always)] + pub fn sleepprm(&mut self) -> SLEEPPRM_W { + SLEEPPRM_W { w: self } + } + #[doc = "Bits 16:17 - NVMCTRL Read Mode"] + #[inline(always)] + pub fn readmode(&mut self) -> READMODE_W { + READMODE_W { w: self } + } + #[doc = "Bits 18:19 - Cache Disable"] + #[inline(always)] + pub fn cachedis(&mut self) -> CACHEDIS_W { + CACHEDIS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0x80"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x80 + } +} diff --git a/pac/atsamc21e/src/nvmctrl/intenclr.rs b/pac/atsamc21e/src/nvmctrl/intenclr.rs new file mode 100644 index 000000000000..6e7db4b52c9d --- /dev/null +++ b/pac/atsamc21e/src/nvmctrl/intenclr.rs @@ -0,0 +1,160 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `READY` reader - NVM Ready Interrupt Enable"] +pub struct READY_R(crate::FieldReader); +impl READY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + READY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for READY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `READY` writer - NVM Ready Interrupt Enable"] +pub struct READY_W<'a> { + w: &'a mut W, +} +impl<'a> READY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERROR` reader - Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - NVM Ready Interrupt Enable"] + #[inline(always)] + pub fn ready(&self) -> READY_R { + READY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - NVM Ready Interrupt Enable"] + #[inline(always)] + pub fn ready(&mut self) -> READY_W { + READY_W { w: self } + } + #[doc = "Bit 1 - Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/nvmctrl/intenset.rs b/pac/atsamc21e/src/nvmctrl/intenset.rs new file mode 100644 index 000000000000..ba8698e86c3e --- /dev/null +++ b/pac/atsamc21e/src/nvmctrl/intenset.rs @@ -0,0 +1,160 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `READY` reader - NVM Ready Interrupt Enable"] +pub struct READY_R(crate::FieldReader); +impl READY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + READY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for READY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `READY` writer - NVM Ready Interrupt Enable"] +pub struct READY_W<'a> { + w: &'a mut W, +} +impl<'a> READY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERROR` reader - Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - NVM Ready Interrupt Enable"] + #[inline(always)] + pub fn ready(&self) -> READY_R { + READY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - NVM Ready Interrupt Enable"] + #[inline(always)] + pub fn ready(&mut self) -> READY_W { + READY_W { w: self } + } + #[doc = "Bit 1 - Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/nvmctrl/intflag.rs b/pac/atsamc21e/src/nvmctrl/intflag.rs new file mode 100644 index 000000000000..1b30cdddf25d --- /dev/null +++ b/pac/atsamc21e/src/nvmctrl/intflag.rs @@ -0,0 +1,160 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `READY` reader - NVM Ready"] +pub struct READY_R(crate::FieldReader); +impl READY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + READY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for READY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `READY` writer - NVM Ready"] +pub struct READY_W<'a> { + w: &'a mut W, +} +impl<'a> READY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERROR` reader - Error"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Error"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - NVM Ready"] + #[inline(always)] + pub fn ready(&self) -> READY_R { + READY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Error"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - NVM Ready"] + #[inline(always)] + pub fn ready(&mut self) -> READY_W { + READY_W { w: self } + } + #[doc = "Bit 1 - Error"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/nvmctrl/lock.rs b/pac/atsamc21e/src/nvmctrl/lock.rs new file mode 100644 index 000000000000..dbcf37a8107f --- /dev/null +++ b/pac/atsamc21e/src/nvmctrl/lock.rs @@ -0,0 +1,103 @@ +#[doc = "Register `LOCK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `LOCK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `LOCK` reader - Region Lock Bits"] +pub struct LOCK_R(crate::FieldReader); +impl LOCK_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + LOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LOCK` writer - Region Lock Bits"] +pub struct LOCK_W<'a> { + w: &'a mut W, +} +impl<'a> LOCK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Region Lock Bits"] + #[inline(always)] + pub fn lock(&self) -> LOCK_R { + LOCK_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Region Lock Bits"] + #[inline(always)] + pub fn lock(&mut self) -> LOCK_W { + LOCK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Lock Section\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lock](index.html) module"] +pub struct LOCK_SPEC; +impl crate::RegisterSpec for LOCK_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [lock::R](R) reader structure"] +impl crate::Readable for LOCK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [lock::W](W) writer structure"] +impl crate::Writable for LOCK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets LOCK to value 0"] +impl crate::Resettable for LOCK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/nvmctrl/param.rs b/pac/atsamc21e/src/nvmctrl/param.rs new file mode 100644 index 000000000000..d9197cf16de4 --- /dev/null +++ b/pac/atsamc21e/src/nvmctrl/param.rs @@ -0,0 +1,304 @@ +#[doc = "Register `PARAM` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PARAM` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `NVMP` reader - NVM Pages"] +pub struct NVMP_R(crate::FieldReader); +impl NVMP_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + NVMP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NVMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NVMP` writer - NVM Pages"] +pub struct NVMP_W<'a> { + w: &'a mut W, +} +impl<'a> NVMP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +#[doc = "Page Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PSZ_A { + #[doc = "0: 8 bytes"] + _8 = 0, + #[doc = "1: 16 bytes"] + _16 = 1, + #[doc = "2: 32 bytes"] + _32 = 2, + #[doc = "3: 64 bytes"] + _64 = 3, + #[doc = "4: 128 bytes"] + _128 = 4, + #[doc = "5: 256 bytes"] + _256 = 5, + #[doc = "6: 512 bytes"] + _512 = 6, + #[doc = "7: 1024 bytes"] + _1024 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PSZ_A) -> Self { + variant as _ + } +} +#[doc = "Field `PSZ` reader - Page Size"] +pub struct PSZ_R(crate::FieldReader); +impl PSZ_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PSZ_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PSZ_A { + match self.bits { + 0 => PSZ_A::_8, + 1 => PSZ_A::_16, + 2 => PSZ_A::_32, + 3 => PSZ_A::_64, + 4 => PSZ_A::_128, + 5 => PSZ_A::_256, + 6 => PSZ_A::_512, + 7 => PSZ_A::_1024, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `_8`"] + #[inline(always)] + pub fn is_8(&self) -> bool { + **self == PSZ_A::_8 + } + #[doc = "Checks if the value of the field is `_16`"] + #[inline(always)] + pub fn is_16(&self) -> bool { + **self == PSZ_A::_16 + } + #[doc = "Checks if the value of the field is `_32`"] + #[inline(always)] + pub fn is_32(&self) -> bool { + **self == PSZ_A::_32 + } + #[doc = "Checks if the value of the field is `_64`"] + #[inline(always)] + pub fn is_64(&self) -> bool { + **self == PSZ_A::_64 + } + #[doc = "Checks if the value of the field is `_128`"] + #[inline(always)] + pub fn is_128(&self) -> bool { + **self == PSZ_A::_128 + } + #[doc = "Checks if the value of the field is `_256`"] + #[inline(always)] + pub fn is_256(&self) -> bool { + **self == PSZ_A::_256 + } + #[doc = "Checks if the value of the field is `_512`"] + #[inline(always)] + pub fn is_512(&self) -> bool { + **self == PSZ_A::_512 + } + #[doc = "Checks if the value of the field is `_1024`"] + #[inline(always)] + pub fn is_1024(&self) -> bool { + **self == PSZ_A::_1024 + } +} +impl core::ops::Deref for PSZ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PSZ` writer - Page Size"] +pub struct PSZ_W<'a> { + w: &'a mut W, +} +impl<'a> PSZ_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PSZ_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "8 bytes"] + #[inline(always)] + pub fn _8(self) -> &'a mut W { + self.variant(PSZ_A::_8) + } + #[doc = "16 bytes"] + #[inline(always)] + pub fn _16(self) -> &'a mut W { + self.variant(PSZ_A::_16) + } + #[doc = "32 bytes"] + #[inline(always)] + pub fn _32(self) -> &'a mut W { + self.variant(PSZ_A::_32) + } + #[doc = "64 bytes"] + #[inline(always)] + pub fn _64(self) -> &'a mut W { + self.variant(PSZ_A::_64) + } + #[doc = "128 bytes"] + #[inline(always)] + pub fn _128(self) -> &'a mut W { + self.variant(PSZ_A::_128) + } + #[doc = "256 bytes"] + #[inline(always)] + pub fn _256(self) -> &'a mut W { + self.variant(PSZ_A::_256) + } + #[doc = "512 bytes"] + #[inline(always)] + pub fn _512(self) -> &'a mut W { + self.variant(PSZ_A::_512) + } + #[doc = "1024 bytes"] + #[inline(always)] + pub fn _1024(self) -> &'a mut W { + self.variant(PSZ_A::_1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 16)) | ((value as u32 & 0x07) << 16); + self.w + } +} +#[doc = "Field `RWWEEP` reader - RWW EEPROM Pages"] +pub struct RWWEEP_R(crate::FieldReader); +impl RWWEEP_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + RWWEEP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RWWEEP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RWWEEP` writer - RWW EEPROM Pages"] +pub struct RWWEEP_W<'a> { + w: &'a mut W, +} +impl<'a> RWWEEP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0fff << 20)) | ((value as u32 & 0x0fff) << 20); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - NVM Pages"] + #[inline(always)] + pub fn nvmp(&self) -> NVMP_R { + NVMP_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:18 - Page Size"] + #[inline(always)] + pub fn psz(&self) -> PSZ_R { + PSZ_R::new(((self.bits >> 16) & 0x07) as u8) + } + #[doc = "Bits 20:31 - RWW EEPROM Pages"] + #[inline(always)] + pub fn rwweep(&self) -> RWWEEP_R { + RWWEEP_R::new(((self.bits >> 20) & 0x0fff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - NVM Pages"] + #[inline(always)] + pub fn nvmp(&mut self) -> NVMP_W { + NVMP_W { w: self } + } + #[doc = "Bits 16:18 - Page Size"] + #[inline(always)] + pub fn psz(&mut self) -> PSZ_W { + PSZ_W { w: self } + } + #[doc = "Bits 20:31 - RWW EEPROM Pages"] + #[inline(always)] + pub fn rwweep(&mut self) -> RWWEEP_W { + RWWEEP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "NVM Parameter\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [param](index.html) module"] +pub struct PARAM_SPEC; +impl crate::RegisterSpec for PARAM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [param::R](R) reader structure"] +impl crate::Readable for PARAM_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [param::W](W) writer structure"] +impl crate::Writable for PARAM_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PARAM to value 0"] +impl crate::Resettable for PARAM_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/nvmctrl/pbldata0.rs b/pac/atsamc21e/src/nvmctrl/pbldata0.rs new file mode 100644 index 000000000000..ff2effaf4d89 --- /dev/null +++ b/pac/atsamc21e/src/nvmctrl/pbldata0.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PBLDATA0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Page Buffer Load Data 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pbldata0](index.html) module"] +pub struct PBLDATA0_SPEC; +impl crate::RegisterSpec for PBLDATA0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pbldata0::R](R) reader structure"] +impl crate::Readable for PBLDATA0_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PBLDATA0 to value 0"] +impl crate::Resettable for PBLDATA0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/nvmctrl/pbldata1.rs b/pac/atsamc21e/src/nvmctrl/pbldata1.rs new file mode 100644 index 000000000000..9fc6404691c5 --- /dev/null +++ b/pac/atsamc21e/src/nvmctrl/pbldata1.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PBLDATA1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Page Buffer Load Data 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pbldata1](index.html) module"] +pub struct PBLDATA1_SPEC; +impl crate::RegisterSpec for PBLDATA1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pbldata1::R](R) reader structure"] +impl crate::Readable for PBLDATA1_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PBLDATA1 to value 0"] +impl crate::Resettable for PBLDATA1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/nvmctrl/status.rs b/pac/atsamc21e/src/nvmctrl/status.rs new file mode 100644 index 000000000000..ce849015560e --- /dev/null +++ b/pac/atsamc21e/src/nvmctrl/status.rs @@ -0,0 +1,348 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PRM` reader - Power Reduction Mode"] +pub struct PRM_R(crate::FieldReader); +impl PRM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PRM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PRM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRM` writer - Power Reduction Mode"] +pub struct PRM_W<'a> { + w: &'a mut W, +} +impl<'a> PRM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `LOAD` reader - NVM Page Buffer Active Loading"] +pub struct LOAD_R(crate::FieldReader); +impl LOAD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LOAD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOAD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LOAD` writer - NVM Page Buffer Active Loading"] +pub struct LOAD_W<'a> { + w: &'a mut W, +} +impl<'a> LOAD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PROGE` reader - Programming Error Status"] +pub struct PROGE_R(crate::FieldReader); +impl PROGE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PROGE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PROGE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PROGE` writer - Programming Error Status"] +pub struct PROGE_W<'a> { + w: &'a mut W, +} +impl<'a> PROGE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `LOCKE` reader - Lock Error Status"] +pub struct LOCKE_R(crate::FieldReader); +impl LOCKE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LOCKE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOCKE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LOCKE` writer - Lock Error Status"] +pub struct LOCKE_W<'a> { + w: &'a mut W, +} +impl<'a> LOCKE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `NVME` reader - NVM Error"] +pub struct NVME_R(crate::FieldReader); +impl NVME_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NVME_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NVME_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NVME` writer - NVM Error"] +pub struct NVME_W<'a> { + w: &'a mut W, +} +impl<'a> NVME_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `SB` reader - Security Bit Status"] +pub struct SB_R(crate::FieldReader); +impl SB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SB` writer - Security Bit Status"] +pub struct SB_W<'a> { + w: &'a mut W, +} +impl<'a> SB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +impl R { + #[doc = "Bit 0 - Power Reduction Mode"] + #[inline(always)] + pub fn prm(&self) -> PRM_R { + PRM_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - NVM Page Buffer Active Loading"] + #[inline(always)] + pub fn load(&self) -> LOAD_R { + LOAD_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Programming Error Status"] + #[inline(always)] + pub fn proge(&self) -> PROGE_R { + PROGE_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Lock Error Status"] + #[inline(always)] + pub fn locke(&self) -> LOCKE_R { + LOCKE_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - NVM Error"] + #[inline(always)] + pub fn nvme(&self) -> NVME_R { + NVME_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 8 - Security Bit Status"] + #[inline(always)] + pub fn sb(&self) -> SB_R { + SB_R::new(((self.bits >> 8) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Power Reduction Mode"] + #[inline(always)] + pub fn prm(&mut self) -> PRM_W { + PRM_W { w: self } + } + #[doc = "Bit 1 - NVM Page Buffer Active Loading"] + #[inline(always)] + pub fn load(&mut self) -> LOAD_W { + LOAD_W { w: self } + } + #[doc = "Bit 2 - Programming Error Status"] + #[inline(always)] + pub fn proge(&mut self) -> PROGE_W { + PROGE_W { w: self } + } + #[doc = "Bit 3 - Lock Error Status"] + #[inline(always)] + pub fn locke(&mut self) -> LOCKE_W { + LOCKE_W { w: self } + } + #[doc = "Bit 4 - NVM Error"] + #[inline(always)] + pub fn nvme(&mut self) -> NVME_W { + NVME_W { w: self } + } + #[doc = "Bit 8 - Security Bit Status"] + #[inline(always)] + pub fn sb(&mut self) -> SB_W { + SB_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/osc32kctrl.rs b/pac/atsamc21e/src/osc32kctrl.rs new file mode 100644 index 000000000000..263cd2f61d59 --- /dev/null +++ b/pac/atsamc21e/src/osc32kctrl.rs @@ -0,0 +1,64 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x04 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x08 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x0c - Power and Clocks Status"] + pub status: crate::Reg, + #[doc = "0x10 - Clock selection"] + pub rtcctrl: crate::Reg, + #[doc = "0x14 - 32kHz External Crystal Oscillator (XOSC32K) Control"] + pub xosc32k: crate::Reg, + #[doc = "0x16 - Clock Failure Detector Control"] + pub cfdctrl: crate::Reg, + #[doc = "0x17 - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x18 - 32kHz Internal Oscillator (OSC32K) Control"] + pub osc32k: crate::Reg, + #[doc = "0x1c - 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control"] + pub osculp32k: crate::Reg, +} +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Power and Clocks Status"] +pub mod status; +#[doc = "RTCCTRL register accessor: an alias for `Reg`"] +pub type RTCCTRL = crate::Reg; +#[doc = "Clock selection"] +pub mod rtcctrl; +#[doc = "XOSC32K register accessor: an alias for `Reg`"] +pub type XOSC32K = crate::Reg; +#[doc = "32kHz External Crystal Oscillator (XOSC32K) Control"] +pub mod xosc32k; +#[doc = "CFDCTRL register accessor: an alias for `Reg`"] +pub type CFDCTRL = crate::Reg; +#[doc = "Clock Failure Detector Control"] +pub mod cfdctrl; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "OSC32K register accessor: an alias for `Reg`"] +pub type OSC32K = crate::Reg; +#[doc = "32kHz Internal Oscillator (OSC32K) Control"] +pub mod osc32k; +#[doc = "OSCULP32K register accessor: an alias for `Reg`"] +pub type OSCULP32K = crate::Reg; +#[doc = "32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control"] +pub mod osculp32k; diff --git a/pac/atsamc21e/src/osc32kctrl/cfdctrl.rs b/pac/atsamc21e/src/osc32kctrl/cfdctrl.rs new file mode 100644 index 000000000000..492a86e1a5a7 --- /dev/null +++ b/pac/atsamc21e/src/osc32kctrl/cfdctrl.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CFDCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CFDCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CFDEN` reader - Clock Failure Detector Enable"] +pub struct CFDEN_R(crate::FieldReader); +impl CFDEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFDEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFDEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFDEN` writer - Clock Failure Detector Enable"] +pub struct CFDEN_W<'a> { + w: &'a mut W, +} +impl<'a> CFDEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SWBACK` reader - Clock Switch Back"] +pub struct SWBACK_R(crate::FieldReader); +impl SWBACK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWBACK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWBACK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWBACK` writer - Clock Switch Back"] +pub struct SWBACK_W<'a> { + w: &'a mut W, +} +impl<'a> SWBACK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CFDPRESC` reader - Clock Failure Detector Prescaler"] +pub struct CFDPRESC_R(crate::FieldReader); +impl CFDPRESC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFDPRESC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFDPRESC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFDPRESC` writer - Clock Failure Detector Prescaler"] +pub struct CFDPRESC_W<'a> { + w: &'a mut W, +} +impl<'a> CFDPRESC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Clock Failure Detector Enable"] + #[inline(always)] + pub fn cfden(&self) -> CFDEN_R { + CFDEN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Clock Switch Back"] + #[inline(always)] + pub fn swback(&self) -> SWBACK_R { + SWBACK_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Clock Failure Detector Prescaler"] + #[inline(always)] + pub fn cfdpresc(&self) -> CFDPRESC_R { + CFDPRESC_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Clock Failure Detector Enable"] + #[inline(always)] + pub fn cfden(&mut self) -> CFDEN_W { + CFDEN_W { w: self } + } + #[doc = "Bit 1 - Clock Switch Back"] + #[inline(always)] + pub fn swback(&mut self) -> SWBACK_W { + SWBACK_W { w: self } + } + #[doc = "Bit 2 - Clock Failure Detector Prescaler"] + #[inline(always)] + pub fn cfdpresc(&mut self) -> CFDPRESC_W { + CFDPRESC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Clock Failure Detector Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cfdctrl](index.html) module"] +pub struct CFDCTRL_SPEC; +impl crate::RegisterSpec for CFDCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [cfdctrl::R](R) reader structure"] +impl crate::Readable for CFDCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cfdctrl::W](W) writer structure"] +impl crate::Writable for CFDCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CFDCTRL to value 0"] +impl crate::Resettable for CFDCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/osc32kctrl/evctrl.rs b/pac/atsamc21e/src/osc32kctrl/evctrl.rs new file mode 100644 index 000000000000..e22ba62f0fe2 --- /dev/null +++ b/pac/atsamc21e/src/osc32kctrl/evctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CFDEO` reader - Clock Failure Detector Event Output Enable"] +pub struct CFDEO_R(crate::FieldReader); +impl CFDEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFDEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFDEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFDEO` writer - Clock Failure Detector Event Output Enable"] +pub struct CFDEO_W<'a> { + w: &'a mut W, +} +impl<'a> CFDEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Clock Failure Detector Event Output Enable"] + #[inline(always)] + pub fn cfdeo(&self) -> CFDEO_R { + CFDEO_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Clock Failure Detector Event Output Enable"] + #[inline(always)] + pub fn cfdeo(&mut self) -> CFDEO_W { + CFDEO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/osc32kctrl/intenclr.rs b/pac/atsamc21e/src/osc32kctrl/intenclr.rs new file mode 100644 index 000000000000..7e330c8de495 --- /dev/null +++ b/pac/atsamc21e/src/osc32kctrl/intenclr.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XOSC32KRDY` reader - XOSC32K Ready Interrupt Enable"] +pub struct XOSC32KRDY_R(crate::FieldReader); +impl XOSC32KRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSC32KRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSC32KRDY` writer - XOSC32K Ready Interrupt Enable"] +pub struct XOSC32KRDY_W<'a> { + w: &'a mut W, +} +impl<'a> XOSC32KRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `OSC32KRDY` reader - OSC32K Ready Interrupt Enable"] +pub struct OSC32KRDY_R(crate::FieldReader); +impl OSC32KRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC32KRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC32KRDY` writer - OSC32K Ready Interrupt Enable"] +pub struct OSC32KRDY_W<'a> { + w: &'a mut W, +} +impl<'a> OSC32KRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CLKFAIL` reader - XOSC32K Clock Failure Detector Interrupt Enable"] +pub struct CLKFAIL_R(crate::FieldReader); +impl CLKFAIL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKFAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKFAIL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKFAIL` writer - XOSC32K Clock Failure Detector Interrupt Enable"] +pub struct CLKFAIL_W<'a> { + w: &'a mut W, +} +impl<'a> CLKFAIL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - XOSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn xosc32krdy(&self) -> XOSC32KRDY_R { + XOSC32KRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - OSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn osc32krdy(&self) -> OSC32KRDY_R { + OSC32KRDY_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - XOSC32K Clock Failure Detector Interrupt Enable"] + #[inline(always)] + pub fn clkfail(&self) -> CLKFAIL_R { + CLKFAIL_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - XOSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn xosc32krdy(&mut self) -> XOSC32KRDY_W { + XOSC32KRDY_W { w: self } + } + #[doc = "Bit 1 - OSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn osc32krdy(&mut self) -> OSC32KRDY_W { + OSC32KRDY_W { w: self } + } + #[doc = "Bit 2 - XOSC32K Clock Failure Detector Interrupt Enable"] + #[inline(always)] + pub fn clkfail(&mut self) -> CLKFAIL_W { + CLKFAIL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/osc32kctrl/intenset.rs b/pac/atsamc21e/src/osc32kctrl/intenset.rs new file mode 100644 index 000000000000..e853d40049f2 --- /dev/null +++ b/pac/atsamc21e/src/osc32kctrl/intenset.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XOSC32KRDY` reader - XOSC32K Ready Interrupt Enable"] +pub struct XOSC32KRDY_R(crate::FieldReader); +impl XOSC32KRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSC32KRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSC32KRDY` writer - XOSC32K Ready Interrupt Enable"] +pub struct XOSC32KRDY_W<'a> { + w: &'a mut W, +} +impl<'a> XOSC32KRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `OSC32KRDY` reader - OSC32K Ready Interrupt Enable"] +pub struct OSC32KRDY_R(crate::FieldReader); +impl OSC32KRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC32KRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC32KRDY` writer - OSC32K Ready Interrupt Enable"] +pub struct OSC32KRDY_W<'a> { + w: &'a mut W, +} +impl<'a> OSC32KRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CLKFAIL` reader - XOSC32K Clock Failure Detector Interrupt Enable"] +pub struct CLKFAIL_R(crate::FieldReader); +impl CLKFAIL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKFAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKFAIL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKFAIL` writer - XOSC32K Clock Failure Detector Interrupt Enable"] +pub struct CLKFAIL_W<'a> { + w: &'a mut W, +} +impl<'a> CLKFAIL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - XOSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn xosc32krdy(&self) -> XOSC32KRDY_R { + XOSC32KRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - OSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn osc32krdy(&self) -> OSC32KRDY_R { + OSC32KRDY_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - XOSC32K Clock Failure Detector Interrupt Enable"] + #[inline(always)] + pub fn clkfail(&self) -> CLKFAIL_R { + CLKFAIL_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - XOSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn xosc32krdy(&mut self) -> XOSC32KRDY_W { + XOSC32KRDY_W { w: self } + } + #[doc = "Bit 1 - OSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn osc32krdy(&mut self) -> OSC32KRDY_W { + OSC32KRDY_W { w: self } + } + #[doc = "Bit 2 - XOSC32K Clock Failure Detector Interrupt Enable"] + #[inline(always)] + pub fn clkfail(&mut self) -> CLKFAIL_W { + CLKFAIL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/osc32kctrl/intflag.rs b/pac/atsamc21e/src/osc32kctrl/intflag.rs new file mode 100644 index 000000000000..9ca42439429d --- /dev/null +++ b/pac/atsamc21e/src/osc32kctrl/intflag.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XOSC32KRDY` reader - XOSC32K Ready"] +pub struct XOSC32KRDY_R(crate::FieldReader); +impl XOSC32KRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSC32KRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSC32KRDY` writer - XOSC32K Ready"] +pub struct XOSC32KRDY_W<'a> { + w: &'a mut W, +} +impl<'a> XOSC32KRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `OSC32KRDY` reader - OSC32K Ready"] +pub struct OSC32KRDY_R(crate::FieldReader); +impl OSC32KRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC32KRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC32KRDY` writer - OSC32K Ready"] +pub struct OSC32KRDY_W<'a> { + w: &'a mut W, +} +impl<'a> OSC32KRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CLKFAIL` reader - XOSC32K Clock Failure Detector"] +pub struct CLKFAIL_R(crate::FieldReader); +impl CLKFAIL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKFAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKFAIL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKFAIL` writer - XOSC32K Clock Failure Detector"] +pub struct CLKFAIL_W<'a> { + w: &'a mut W, +} +impl<'a> CLKFAIL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - XOSC32K Ready"] + #[inline(always)] + pub fn xosc32krdy(&self) -> XOSC32KRDY_R { + XOSC32KRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - OSC32K Ready"] + #[inline(always)] + pub fn osc32krdy(&self) -> OSC32KRDY_R { + OSC32KRDY_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - XOSC32K Clock Failure Detector"] + #[inline(always)] + pub fn clkfail(&self) -> CLKFAIL_R { + CLKFAIL_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - XOSC32K Ready"] + #[inline(always)] + pub fn xosc32krdy(&mut self) -> XOSC32KRDY_W { + XOSC32KRDY_W { w: self } + } + #[doc = "Bit 1 - OSC32K Ready"] + #[inline(always)] + pub fn osc32krdy(&mut self) -> OSC32KRDY_W { + OSC32KRDY_W { w: self } + } + #[doc = "Bit 2 - XOSC32K Clock Failure Detector"] + #[inline(always)] + pub fn clkfail(&mut self) -> CLKFAIL_W { + CLKFAIL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/osc32kctrl/osc32k.rs b/pac/atsamc21e/src/osc32kctrl/osc32k.rs new file mode 100644 index 000000000000..aa32cb287aa7 --- /dev/null +++ b/pac/atsamc21e/src/osc32kctrl/osc32k.rs @@ -0,0 +1,549 @@ +#[doc = "Register `OSC32K` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OSC32K` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Oscillator Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Oscillator Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `EN32K` reader - 32kHz Output Enable"] +pub struct EN32K_R(crate::FieldReader); +impl EN32K_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EN32K_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EN32K_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EN32K` writer - 32kHz Output Enable"] +pub struct EN32K_W<'a> { + w: &'a mut W, +} +impl<'a> EN32K_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `EN1K` reader - 1kHz Output Enable"] +pub struct EN1K_R(crate::FieldReader); +impl EN1K_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EN1K_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EN1K_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EN1K` writer - 1kHz Output Enable"] +pub struct EN1K_W<'a> { + w: &'a mut W, +} +impl<'a> EN1K_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - On Demand Control"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - On Demand Control"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Oscillator Start-Up Time\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum STARTUP_A { + #[doc = "0: 0.092 ms"] + CYCLE3 = 0, + #[doc = "1: 0.122 ms"] + CYCLE4 = 1, + #[doc = "2: 0.183 ms"] + CYCLE6 = 2, + #[doc = "3: 0.305 ms"] + CYCLE10 = 3, + #[doc = "4: 0.549 ms"] + CYCLE18 = 4, + #[doc = "5: 1.038 ms"] + CYCLE34 = 5, + #[doc = "6: 2.014 ms"] + CYCLE66 = 6, + #[doc = "7: 3.967 ms"] + CYCLE130 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: STARTUP_A) -> Self { + variant as _ + } +} +#[doc = "Field `STARTUP` reader - Oscillator Start-Up Time"] +pub struct STARTUP_R(crate::FieldReader); +impl STARTUP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + STARTUP_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STARTUP_A { + match self.bits { + 0 => STARTUP_A::CYCLE3, + 1 => STARTUP_A::CYCLE4, + 2 => STARTUP_A::CYCLE6, + 3 => STARTUP_A::CYCLE10, + 4 => STARTUP_A::CYCLE18, + 5 => STARTUP_A::CYCLE34, + 6 => STARTUP_A::CYCLE66, + 7 => STARTUP_A::CYCLE130, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `CYCLE3`"] + #[inline(always)] + pub fn is_cycle3(&self) -> bool { + **self == STARTUP_A::CYCLE3 + } + #[doc = "Checks if the value of the field is `CYCLE4`"] + #[inline(always)] + pub fn is_cycle4(&self) -> bool { + **self == STARTUP_A::CYCLE4 + } + #[doc = "Checks if the value of the field is `CYCLE6`"] + #[inline(always)] + pub fn is_cycle6(&self) -> bool { + **self == STARTUP_A::CYCLE6 + } + #[doc = "Checks if the value of the field is `CYCLE10`"] + #[inline(always)] + pub fn is_cycle10(&self) -> bool { + **self == STARTUP_A::CYCLE10 + } + #[doc = "Checks if the value of the field is `CYCLE18`"] + #[inline(always)] + pub fn is_cycle18(&self) -> bool { + **self == STARTUP_A::CYCLE18 + } + #[doc = "Checks if the value of the field is `CYCLE34`"] + #[inline(always)] + pub fn is_cycle34(&self) -> bool { + **self == STARTUP_A::CYCLE34 + } + #[doc = "Checks if the value of the field is `CYCLE66`"] + #[inline(always)] + pub fn is_cycle66(&self) -> bool { + **self == STARTUP_A::CYCLE66 + } + #[doc = "Checks if the value of the field is `CYCLE130`"] + #[inline(always)] + pub fn is_cycle130(&self) -> bool { + **self == STARTUP_A::CYCLE130 + } +} +impl core::ops::Deref for STARTUP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STARTUP` writer - Oscillator Start-Up Time"] +pub struct STARTUP_W<'a> { + w: &'a mut W, +} +impl<'a> STARTUP_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: STARTUP_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "0.092 ms"] + #[inline(always)] + pub fn cycle3(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE3) + } + #[doc = "0.122 ms"] + #[inline(always)] + pub fn cycle4(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE4) + } + #[doc = "0.183 ms"] + #[inline(always)] + pub fn cycle6(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE6) + } + #[doc = "0.305 ms"] + #[inline(always)] + pub fn cycle10(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE10) + } + #[doc = "0.549 ms"] + #[inline(always)] + pub fn cycle18(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE18) + } + #[doc = "1.038 ms"] + #[inline(always)] + pub fn cycle34(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE34) + } + #[doc = "2.014 ms"] + #[inline(always)] + pub fn cycle66(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE66) + } + #[doc = "3.967 ms"] + #[inline(always)] + pub fn cycle130(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE130) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +#[doc = "Field `WRTLOCK` reader - Write Lock"] +pub struct WRTLOCK_R(crate::FieldReader); +impl WRTLOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WRTLOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WRTLOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WRTLOCK` writer - Write Lock"] +pub struct WRTLOCK_W<'a> { + w: &'a mut W, +} +impl<'a> WRTLOCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `CALIB` reader - Oscillator Calibration"] +pub struct CALIB_R(crate::FieldReader); +impl CALIB_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CALIB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CALIB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CALIB` writer - Oscillator Calibration"] +pub struct CALIB_W<'a> { + w: &'a mut W, +} +impl<'a> CALIB_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x7f << 16)) | ((value as u32 & 0x7f) << 16); + self.w + } +} +impl R { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - 32kHz Output Enable"] + #[inline(always)] + pub fn en32k(&self) -> EN32K_R { + EN32K_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - 1kHz Output Enable"] + #[inline(always)] + pub fn en1k(&self) -> EN1K_R { + EN1K_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Oscillator Start-Up Time"] + #[inline(always)] + pub fn startup(&self) -> STARTUP_R { + STARTUP_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 12 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&self) -> WRTLOCK_R { + WRTLOCK_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bits 16:22 - Oscillator Calibration"] + #[inline(always)] + pub fn calib(&self) -> CALIB_R { + CALIB_R::new(((self.bits >> 16) & 0x7f) as u8) + } +} +impl W { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - 32kHz Output Enable"] + #[inline(always)] + pub fn en32k(&mut self) -> EN32K_W { + EN32K_W { w: self } + } + #[doc = "Bit 3 - 1kHz Output Enable"] + #[inline(always)] + pub fn en1k(&mut self) -> EN1K_W { + EN1K_W { w: self } + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Bits 8:10 - Oscillator Start-Up Time"] + #[inline(always)] + pub fn startup(&mut self) -> STARTUP_W { + STARTUP_W { w: self } + } + #[doc = "Bit 12 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&mut self) -> WRTLOCK_W { + WRTLOCK_W { w: self } + } + #[doc = "Bits 16:22 - Oscillator Calibration"] + #[inline(always)] + pub fn calib(&mut self) -> CALIB_W { + CALIB_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "32kHz Internal Oscillator (OSC32K) Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [osc32k](index.html) module"] +pub struct OSC32K_SPEC; +impl crate::RegisterSpec for OSC32K_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [osc32k::R](R) reader structure"] +impl crate::Readable for OSC32K_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [osc32k::W](W) writer structure"] +impl crate::Writable for OSC32K_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OSC32K to value 0x003f_0080"] +impl crate::Resettable for OSC32K_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x003f_0080 + } +} diff --git a/pac/atsamc21e/src/osc32kctrl/osculp32k.rs b/pac/atsamc21e/src/osc32kctrl/osculp32k.rs new file mode 100644 index 000000000000..1c351c406e59 --- /dev/null +++ b/pac/atsamc21e/src/osc32kctrl/osculp32k.rs @@ -0,0 +1,150 @@ +#[doc = "Register `OSCULP32K` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OSCULP32K` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CALIB` reader - Oscillator Calibration"] +pub struct CALIB_R(crate::FieldReader); +impl CALIB_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CALIB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CALIB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CALIB` writer - Oscillator Calibration"] +pub struct CALIB_W<'a> { + w: &'a mut W, +} +impl<'a> CALIB_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 8)) | ((value as u32 & 0x1f) << 8); + self.w + } +} +#[doc = "Field `WRTLOCK` reader - Write Lock"] +pub struct WRTLOCK_R(crate::FieldReader); +impl WRTLOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WRTLOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WRTLOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WRTLOCK` writer - Write Lock"] +pub struct WRTLOCK_W<'a> { + w: &'a mut W, +} +impl<'a> WRTLOCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bits 8:12 - Oscillator Calibration"] + #[inline(always)] + pub fn calib(&self) -> CALIB_R { + CALIB_R::new(((self.bits >> 8) & 0x1f) as u8) + } + #[doc = "Bit 15 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&self) -> WRTLOCK_R { + WRTLOCK_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 8:12 - Oscillator Calibration"] + #[inline(always)] + pub fn calib(&mut self) -> CALIB_W { + CALIB_W { w: self } + } + #[doc = "Bit 15 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&mut self) -> WRTLOCK_W { + WRTLOCK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [osculp32k](index.html) module"] +pub struct OSCULP32K_SPEC; +impl crate::RegisterSpec for OSCULP32K_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [osculp32k::R](R) reader structure"] +impl crate::Readable for OSCULP32K_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [osculp32k::W](W) writer structure"] +impl crate::Writable for OSCULP32K_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OSCULP32K to value 0"] +impl crate::Resettable for OSCULP32K_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/osc32kctrl/rtcctrl.rs b/pac/atsamc21e/src/osc32kctrl/rtcctrl.rs new file mode 100644 index 000000000000..1248024a03b9 --- /dev/null +++ b/pac/atsamc21e/src/osc32kctrl/rtcctrl.rs @@ -0,0 +1,204 @@ +#[doc = "Register `RTCCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RTCCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "RTC Clock Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum RTCSEL_A { + #[doc = "0: 1.024kHz from 32kHz internal ULP oscillator"] + ULP1K = 0, + #[doc = "1: 32.768kHz from 32kHz internal ULP oscillator"] + ULP32K = 1, + #[doc = "2: 1.024kHz from 32.768kHz internal oscillator"] + OSC1K = 2, + #[doc = "3: 32.768kHz from 32.768kHz internal oscillator"] + OSC32K = 3, + #[doc = "4: 1.024kHz from 32.768kHz internal oscillator"] + XOSC1K = 4, + #[doc = "5: 32.768kHz from 32.768kHz external crystal oscillator"] + XOSC32K = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RTCSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `RTCSEL` reader - RTC Clock Selection"] +pub struct RTCSEL_R(crate::FieldReader); +impl RTCSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RTCSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(RTCSEL_A::ULP1K), + 1 => Some(RTCSEL_A::ULP32K), + 2 => Some(RTCSEL_A::OSC1K), + 3 => Some(RTCSEL_A::OSC32K), + 4 => Some(RTCSEL_A::XOSC1K), + 5 => Some(RTCSEL_A::XOSC32K), + _ => None, + } + } + #[doc = "Checks if the value of the field is `ULP1K`"] + #[inline(always)] + pub fn is_ulp1k(&self) -> bool { + **self == RTCSEL_A::ULP1K + } + #[doc = "Checks if the value of the field is `ULP32K`"] + #[inline(always)] + pub fn is_ulp32k(&self) -> bool { + **self == RTCSEL_A::ULP32K + } + #[doc = "Checks if the value of the field is `OSC1K`"] + #[inline(always)] + pub fn is_osc1k(&self) -> bool { + **self == RTCSEL_A::OSC1K + } + #[doc = "Checks if the value of the field is `OSC32K`"] + #[inline(always)] + pub fn is_osc32k(&self) -> bool { + **self == RTCSEL_A::OSC32K + } + #[doc = "Checks if the value of the field is `XOSC1K`"] + #[inline(always)] + pub fn is_xosc1k(&self) -> bool { + **self == RTCSEL_A::XOSC1K + } + #[doc = "Checks if the value of the field is `XOSC32K`"] + #[inline(always)] + pub fn is_xosc32k(&self) -> bool { + **self == RTCSEL_A::XOSC32K + } +} +impl core::ops::Deref for RTCSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RTCSEL` writer - RTC Clock Selection"] +pub struct RTCSEL_W<'a> { + w: &'a mut W, +} +impl<'a> RTCSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RTCSEL_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "1.024kHz from 32kHz internal ULP oscillator"] + #[inline(always)] + pub fn ulp1k(self) -> &'a mut W { + self.variant(RTCSEL_A::ULP1K) + } + #[doc = "32.768kHz from 32kHz internal ULP oscillator"] + #[inline(always)] + pub fn ulp32k(self) -> &'a mut W { + self.variant(RTCSEL_A::ULP32K) + } + #[doc = "1.024kHz from 32.768kHz internal oscillator"] + #[inline(always)] + pub fn osc1k(self) -> &'a mut W { + self.variant(RTCSEL_A::OSC1K) + } + #[doc = "32.768kHz from 32.768kHz internal oscillator"] + #[inline(always)] + pub fn osc32k(self) -> &'a mut W { + self.variant(RTCSEL_A::OSC32K) + } + #[doc = "1.024kHz from 32.768kHz internal oscillator"] + #[inline(always)] + pub fn xosc1k(self) -> &'a mut W { + self.variant(RTCSEL_A::XOSC1K) + } + #[doc = "32.768kHz from 32.768kHz external crystal oscillator"] + #[inline(always)] + pub fn xosc32k(self) -> &'a mut W { + self.variant(RTCSEL_A::XOSC32K) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - RTC Clock Selection"] + #[inline(always)] + pub fn rtcsel(&self) -> RTCSEL_R { + RTCSEL_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - RTC Clock Selection"] + #[inline(always)] + pub fn rtcsel(&mut self) -> RTCSEL_W { + RTCSEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Clock selection\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rtcctrl](index.html) module"] +pub struct RTCCTRL_SPEC; +impl crate::RegisterSpec for RTCCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rtcctrl::R](R) reader structure"] +impl crate::Readable for RTCCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rtcctrl::W](W) writer structure"] +impl crate::Writable for RTCCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RTCCTRL to value 0"] +impl crate::Resettable for RTCCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/osc32kctrl/status.rs b/pac/atsamc21e/src/osc32kctrl/status.rs new file mode 100644 index 000000000000..f1f1483ac4e8 --- /dev/null +++ b/pac/atsamc21e/src/osc32kctrl/status.rs @@ -0,0 +1,113 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `XOSC32KRDY` reader - XOSC32K Ready"] +pub struct XOSC32KRDY_R(crate::FieldReader); +impl XOSC32KRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSC32KRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC32KRDY` reader - OSC32K Ready"] +pub struct OSC32KRDY_R(crate::FieldReader); +impl OSC32KRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC32KRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKFAIL` reader - XOSC32K Clock Failure Detector"] +pub struct CLKFAIL_R(crate::FieldReader); +impl CLKFAIL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKFAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKFAIL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKSW` reader - XOSC32K Clock switch"] +pub struct CLKSW_R(crate::FieldReader); +impl CLKSW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKSW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKSW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - XOSC32K Ready"] + #[inline(always)] + pub fn xosc32krdy(&self) -> XOSC32KRDY_R { + XOSC32KRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - OSC32K Ready"] + #[inline(always)] + pub fn osc32krdy(&self) -> OSC32KRDY_R { + OSC32KRDY_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - XOSC32K Clock Failure Detector"] + #[inline(always)] + pub fn clkfail(&self) -> CLKFAIL_R { + CLKFAIL_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - XOSC32K Clock switch"] + #[inline(always)] + pub fn clksw(&self) -> CLKSW_R { + CLKSW_R::new(((self.bits >> 3) & 0x01) != 0) + } +} +#[doc = "Power and Clocks Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/osc32kctrl/xosc32k.rs b/pac/atsamc21e/src/osc32kctrl/xosc32k.rs new file mode 100644 index 000000000000..93e42bba3c0e --- /dev/null +++ b/pac/atsamc21e/src/osc32kctrl/xosc32k.rs @@ -0,0 +1,559 @@ +#[doc = "Register `XOSC32K` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `XOSC32K` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Oscillator Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Oscillator Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `XTALEN` reader - Crystal Oscillator Enable"] +pub struct XTALEN_R(crate::FieldReader); +impl XTALEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XTALEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XTALEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XTALEN` writer - Crystal Oscillator Enable"] +pub struct XTALEN_W<'a> { + w: &'a mut W, +} +impl<'a> XTALEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `EN32K` reader - 32kHz Output Enable"] +pub struct EN32K_R(crate::FieldReader); +impl EN32K_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EN32K_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EN32K_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EN32K` writer - 32kHz Output Enable"] +pub struct EN32K_W<'a> { + w: &'a mut W, +} +impl<'a> EN32K_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `EN1K` reader - 1kHz Output Enable"] +pub struct EN1K_R(crate::FieldReader); +impl EN1K_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EN1K_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EN1K_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EN1K` writer - 1kHz Output Enable"] +pub struct EN1K_W<'a> { + w: &'a mut W, +} +impl<'a> EN1K_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - On Demand Control"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - On Demand Control"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Oscillator Start-Up Time\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum STARTUP_A { + #[doc = "0: 0.122 ms"] + CYCLE1 = 0, + #[doc = "1: 1.068 ms"] + CYCLE32 = 1, + #[doc = "2: 62.6 ms"] + CYCLE2048 = 2, + #[doc = "3: 125 ms"] + CYCLE4096 = 3, + #[doc = "4: 500 ms"] + CYCLE16384 = 4, + #[doc = "5: 1000 ms"] + CYCLE32768 = 5, + #[doc = "6: 2000 ms"] + CYCLE65536 = 6, + #[doc = "7: 4000 ms"] + CYCLE131072 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: STARTUP_A) -> Self { + variant as _ + } +} +#[doc = "Field `STARTUP` reader - Oscillator Start-Up Time"] +pub struct STARTUP_R(crate::FieldReader); +impl STARTUP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + STARTUP_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STARTUP_A { + match self.bits { + 0 => STARTUP_A::CYCLE1, + 1 => STARTUP_A::CYCLE32, + 2 => STARTUP_A::CYCLE2048, + 3 => STARTUP_A::CYCLE4096, + 4 => STARTUP_A::CYCLE16384, + 5 => STARTUP_A::CYCLE32768, + 6 => STARTUP_A::CYCLE65536, + 7 => STARTUP_A::CYCLE131072, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `CYCLE1`"] + #[inline(always)] + pub fn is_cycle1(&self) -> bool { + **self == STARTUP_A::CYCLE1 + } + #[doc = "Checks if the value of the field is `CYCLE32`"] + #[inline(always)] + pub fn is_cycle32(&self) -> bool { + **self == STARTUP_A::CYCLE32 + } + #[doc = "Checks if the value of the field is `CYCLE2048`"] + #[inline(always)] + pub fn is_cycle2048(&self) -> bool { + **self == STARTUP_A::CYCLE2048 + } + #[doc = "Checks if the value of the field is `CYCLE4096`"] + #[inline(always)] + pub fn is_cycle4096(&self) -> bool { + **self == STARTUP_A::CYCLE4096 + } + #[doc = "Checks if the value of the field is `CYCLE16384`"] + #[inline(always)] + pub fn is_cycle16384(&self) -> bool { + **self == STARTUP_A::CYCLE16384 + } + #[doc = "Checks if the value of the field is `CYCLE32768`"] + #[inline(always)] + pub fn is_cycle32768(&self) -> bool { + **self == STARTUP_A::CYCLE32768 + } + #[doc = "Checks if the value of the field is `CYCLE65536`"] + #[inline(always)] + pub fn is_cycle65536(&self) -> bool { + **self == STARTUP_A::CYCLE65536 + } + #[doc = "Checks if the value of the field is `CYCLE131072`"] + #[inline(always)] + pub fn is_cycle131072(&self) -> bool { + **self == STARTUP_A::CYCLE131072 + } +} +impl core::ops::Deref for STARTUP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STARTUP` writer - Oscillator Start-Up Time"] +pub struct STARTUP_W<'a> { + w: &'a mut W, +} +impl<'a> STARTUP_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: STARTUP_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "0.122 ms"] + #[inline(always)] + pub fn cycle1(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE1) + } + #[doc = "1.068 ms"] + #[inline(always)] + pub fn cycle32(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE32) + } + #[doc = "62.6 ms"] + #[inline(always)] + pub fn cycle2048(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE2048) + } + #[doc = "125 ms"] + #[inline(always)] + pub fn cycle4096(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE4096) + } + #[doc = "500 ms"] + #[inline(always)] + pub fn cycle16384(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE16384) + } + #[doc = "1000 ms"] + #[inline(always)] + pub fn cycle32768(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE32768) + } + #[doc = "2000 ms"] + #[inline(always)] + pub fn cycle65536(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE65536) + } + #[doc = "4000 ms"] + #[inline(always)] + pub fn cycle131072(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE131072) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u16 & 0x07) << 8); + self.w + } +} +#[doc = "Field `WRTLOCK` reader - Write Lock"] +pub struct WRTLOCK_R(crate::FieldReader); +impl WRTLOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WRTLOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WRTLOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WRTLOCK` writer - Write Lock"] +pub struct WRTLOCK_W<'a> { + w: &'a mut W, +} +impl<'a> WRTLOCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u16 & 0x01) << 12); + self.w + } +} +impl R { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Crystal Oscillator Enable"] + #[inline(always)] + pub fn xtalen(&self) -> XTALEN_R { + XTALEN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - 32kHz Output Enable"] + #[inline(always)] + pub fn en32k(&self) -> EN32K_R { + EN32K_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - 1kHz Output Enable"] + #[inline(always)] + pub fn en1k(&self) -> EN1K_R { + EN1K_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Oscillator Start-Up Time"] + #[inline(always)] + pub fn startup(&self) -> STARTUP_R { + STARTUP_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 12 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&self) -> WRTLOCK_R { + WRTLOCK_R::new(((self.bits >> 12) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - Crystal Oscillator Enable"] + #[inline(always)] + pub fn xtalen(&mut self) -> XTALEN_W { + XTALEN_W { w: self } + } + #[doc = "Bit 3 - 32kHz Output Enable"] + #[inline(always)] + pub fn en32k(&mut self) -> EN32K_W { + EN32K_W { w: self } + } + #[doc = "Bit 4 - 1kHz Output Enable"] + #[inline(always)] + pub fn en1k(&mut self) -> EN1K_W { + EN1K_W { w: self } + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Bits 8:10 - Oscillator Start-Up Time"] + #[inline(always)] + pub fn startup(&mut self) -> STARTUP_W { + STARTUP_W { w: self } + } + #[doc = "Bit 12 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&mut self) -> WRTLOCK_W { + WRTLOCK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "32kHz External Crystal Oscillator (XOSC32K) Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [xosc32k](index.html) module"] +pub struct XOSC32K_SPEC; +impl crate::RegisterSpec for XOSC32K_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [xosc32k::R](R) reader structure"] +impl crate::Readable for XOSC32K_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [xosc32k::W](W) writer structure"] +impl crate::Writable for XOSC32K_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets XOSC32K to value 0x80"] +impl crate::Resettable for XOSC32K_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x80 + } +} diff --git a/pac/atsamc21e/src/oscctrl.rs b/pac/atsamc21e/src/oscctrl.rs new file mode 100644 index 000000000000..e6dd0929927c --- /dev/null +++ b/pac/atsamc21e/src/oscctrl.rs @@ -0,0 +1,117 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x04 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x08 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x0c - Power and Clocks Status"] + pub status: crate::Reg, + #[doc = "0x10 - External Multipurpose Crystal Oscillator (XOSC) Control"] + pub xoscctrl: crate::Reg, + #[doc = "0x12 - Clock Failure Detector Prescaler"] + pub cfdpresc: crate::Reg, + #[doc = "0x13 - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x14 - 48MHz Internal Oscillator (OSC48M) Control"] + pub osc48mctrl: crate::Reg, + #[doc = "0x15 - OSC48M Divider"] + pub osc48mdiv: crate::Reg, + #[doc = "0x16 - OSC48M Startup Time"] + pub osc48mstup: crate::Reg, + _reserved10: [u8; 0x01], + #[doc = "0x18 - OSC48M Synchronization Busy"] + pub osc48msyncbusy: crate::Reg, + #[doc = "0x1c - DPLL Control"] + pub dpllctrla: crate::Reg, + _reserved12: [u8; 0x03], + #[doc = "0x20 - DPLL Ratio Control"] + pub dpllratio: crate::Reg, + #[doc = "0x24 - Digital Core Configuration"] + pub dpllctrlb: crate::Reg, + #[doc = "0x28 - DPLL Prescaler"] + pub dpllpresc: crate::Reg, + _reserved15: [u8; 0x03], + #[doc = "0x2c - DPLL Synchronization Busy"] + pub dpllsyncbusy: crate::Reg, + _reserved16: [u8; 0x03], + #[doc = "0x30 - DPLL Status"] + pub dpllstatus: crate::Reg, + _reserved17: [u8; 0x07], + #[doc = "0x38 - 48MHz Oscillator Calibration"] + pub cal48m: crate::Reg, +} +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Power and Clocks Status"] +pub mod status; +#[doc = "XOSCCTRL register accessor: an alias for `Reg`"] +pub type XOSCCTRL = crate::Reg; +#[doc = "External Multipurpose Crystal Oscillator (XOSC) Control"] +pub mod xoscctrl; +#[doc = "CFDPRESC register accessor: an alias for `Reg`"] +pub type CFDPRESC = crate::Reg; +#[doc = "Clock Failure Detector Prescaler"] +pub mod cfdpresc; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "OSC48MCTRL register accessor: an alias for `Reg`"] +pub type OSC48MCTRL = crate::Reg; +#[doc = "48MHz Internal Oscillator (OSC48M) Control"] +pub mod osc48mctrl; +#[doc = "OSC48MDIV register accessor: an alias for `Reg`"] +pub type OSC48MDIV = crate::Reg; +#[doc = "OSC48M Divider"] +pub mod osc48mdiv; +#[doc = "OSC48MSTUP register accessor: an alias for `Reg`"] +pub type OSC48MSTUP = crate::Reg; +#[doc = "OSC48M Startup Time"] +pub mod osc48mstup; +#[doc = "OSC48MSYNCBUSY register accessor: an alias for `Reg`"] +pub type OSC48MSYNCBUSY = crate::Reg; +#[doc = "OSC48M Synchronization Busy"] +pub mod osc48msyncbusy; +#[doc = "DPLLCTRLA register accessor: an alias for `Reg`"] +pub type DPLLCTRLA = crate::Reg; +#[doc = "DPLL Control"] +pub mod dpllctrla; +#[doc = "DPLLRATIO register accessor: an alias for `Reg`"] +pub type DPLLRATIO = crate::Reg; +#[doc = "DPLL Ratio Control"] +pub mod dpllratio; +#[doc = "DPLLCTRLB register accessor: an alias for `Reg`"] +pub type DPLLCTRLB = crate::Reg; +#[doc = "Digital Core Configuration"] +pub mod dpllctrlb; +#[doc = "DPLLPRESC register accessor: an alias for `Reg`"] +pub type DPLLPRESC = crate::Reg; +#[doc = "DPLL Prescaler"] +pub mod dpllpresc; +#[doc = "DPLLSYNCBUSY register accessor: an alias for `Reg`"] +pub type DPLLSYNCBUSY = crate::Reg; +#[doc = "DPLL Synchronization Busy"] +pub mod dpllsyncbusy; +#[doc = "DPLLSTATUS register accessor: an alias for `Reg`"] +pub type DPLLSTATUS = crate::Reg; +#[doc = "DPLL Status"] +pub mod dpllstatus; +#[doc = "CAL48M register accessor: an alias for `Reg`"] +pub type CAL48M = crate::Reg; +#[doc = "48MHz Oscillator Calibration"] +pub mod cal48m; diff --git a/pac/atsamc21e/src/oscctrl/cal48m.rs b/pac/atsamc21e/src/oscctrl/cal48m.rs new file mode 100644 index 000000000000..05d5cd2bbc92 --- /dev/null +++ b/pac/atsamc21e/src/oscctrl/cal48m.rs @@ -0,0 +1,177 @@ +#[doc = "Register `CAL48M` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CAL48M` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FCAL` reader - Frequency Calibration (48MHz)"] +pub struct FCAL_R(crate::FieldReader); +impl FCAL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FCAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FCAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FCAL` writer - Frequency Calibration (48MHz)"] +pub struct FCAL_W<'a> { + w: &'a mut W, +} +impl<'a> FCAL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +#[doc = "Field `FRANGE` reader - Frequency Range (48MHz)"] +pub struct FRANGE_R(crate::FieldReader); +impl FRANGE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FRANGE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FRANGE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FRANGE` writer - Frequency Range (48MHz)"] +pub struct FRANGE_W<'a> { + w: &'a mut W, +} +impl<'a> FRANGE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 8)) | ((value as u32 & 0x03) << 8); + self.w + } +} +#[doc = "Field `TCAL` reader - Temperature Calibration (48MHz)"] +pub struct TCAL_R(crate::FieldReader); +impl TCAL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TCAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCAL` writer - Temperature Calibration (48MHz)"] +pub struct TCAL_W<'a> { + w: &'a mut W, +} +impl<'a> TCAL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 16)) | ((value as u32 & 0x3f) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Frequency Calibration (48MHz)"] + #[inline(always)] + pub fn fcal(&self) -> FCAL_R { + FCAL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 8:9 - Frequency Range (48MHz)"] + #[inline(always)] + pub fn frange(&self) -> FRANGE_R { + FRANGE_R::new(((self.bits >> 8) & 0x03) as u8) + } + #[doc = "Bits 16:21 - Temperature Calibration (48MHz)"] + #[inline(always)] + pub fn tcal(&self) -> TCAL_R { + TCAL_R::new(((self.bits >> 16) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - Frequency Calibration (48MHz)"] + #[inline(always)] + pub fn fcal(&mut self) -> FCAL_W { + FCAL_W { w: self } + } + #[doc = "Bits 8:9 - Frequency Range (48MHz)"] + #[inline(always)] + pub fn frange(&mut self) -> FRANGE_W { + FRANGE_W { w: self } + } + #[doc = "Bits 16:21 - Temperature Calibration (48MHz)"] + #[inline(always)] + pub fn tcal(&mut self) -> TCAL_W { + TCAL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "48MHz Oscillator Calibration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cal48m](index.html) module"] +pub struct CAL48M_SPEC; +impl crate::RegisterSpec for CAL48M_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cal48m::R](R) reader structure"] +impl crate::Readable for CAL48M_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cal48m::W](W) writer structure"] +impl crate::Writable for CAL48M_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CAL48M to value 0"] +impl crate::Resettable for CAL48M_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/oscctrl/cfdpresc.rs b/pac/atsamc21e/src/oscctrl/cfdpresc.rs new file mode 100644 index 000000000000..029ae541eec5 --- /dev/null +++ b/pac/atsamc21e/src/oscctrl/cfdpresc.rs @@ -0,0 +1,230 @@ +#[doc = "Register `CFDPRESC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CFDPRESC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Clock Failure Detector Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CFDPRESC_A { + #[doc = "0: 48 MHz"] + DIV1 = 0, + #[doc = "1: 24 MHz"] + DIV2 = 1, + #[doc = "2: 12 MHz"] + DIV4 = 2, + #[doc = "3: 6 MHz"] + DIV8 = 3, + #[doc = "4: 3 MHz"] + DIV16 = 4, + #[doc = "5: 1.5 MHz"] + DIV32 = 5, + #[doc = "6: 0.75 MHz"] + DIV64 = 6, + #[doc = "7: 0.3125 MHz"] + DIV128 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CFDPRESC_A) -> Self { + variant as _ + } +} +#[doc = "Field `CFDPRESC` reader - Clock Failure Detector Prescaler"] +pub struct CFDPRESC_R(crate::FieldReader); +impl CFDPRESC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CFDPRESC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CFDPRESC_A { + match self.bits { + 0 => CFDPRESC_A::DIV1, + 1 => CFDPRESC_A::DIV2, + 2 => CFDPRESC_A::DIV4, + 3 => CFDPRESC_A::DIV8, + 4 => CFDPRESC_A::DIV16, + 5 => CFDPRESC_A::DIV32, + 6 => CFDPRESC_A::DIV64, + 7 => CFDPRESC_A::DIV128, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == CFDPRESC_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == CFDPRESC_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == CFDPRESC_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == CFDPRESC_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == CFDPRESC_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == CFDPRESC_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == CFDPRESC_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == CFDPRESC_A::DIV128 + } +} +impl core::ops::Deref for CFDPRESC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFDPRESC` writer - Clock Failure Detector Prescaler"] +pub struct CFDPRESC_W<'a> { + w: &'a mut W, +} +impl<'a> CFDPRESC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CFDPRESC_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "48 MHz"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(CFDPRESC_A::DIV1) + } + #[doc = "24 MHz"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(CFDPRESC_A::DIV2) + } + #[doc = "12 MHz"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(CFDPRESC_A::DIV4) + } + #[doc = "6 MHz"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(CFDPRESC_A::DIV8) + } + #[doc = "3 MHz"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(CFDPRESC_A::DIV16) + } + #[doc = "1.5 MHz"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(CFDPRESC_A::DIV32) + } + #[doc = "0.75 MHz"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(CFDPRESC_A::DIV64) + } + #[doc = "0.3125 MHz"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(CFDPRESC_A::DIV128) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Clock Failure Detector Prescaler"] + #[inline(always)] + pub fn cfdpresc(&self) -> CFDPRESC_R { + CFDPRESC_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Clock Failure Detector Prescaler"] + #[inline(always)] + pub fn cfdpresc(&mut self) -> CFDPRESC_W { + CFDPRESC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Clock Failure Detector Prescaler\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cfdpresc](index.html) module"] +pub struct CFDPRESC_SPEC; +impl crate::RegisterSpec for CFDPRESC_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [cfdpresc::R](R) reader structure"] +impl crate::Readable for CFDPRESC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cfdpresc::W](W) writer structure"] +impl crate::Writable for CFDPRESC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CFDPRESC to value 0"] +impl crate::Resettable for CFDPRESC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/oscctrl/dpllctrla.rs b/pac/atsamc21e/src/oscctrl/dpllctrla.rs new file mode 100644 index 000000000000..5a60a5087002 --- /dev/null +++ b/pac/atsamc21e/src/oscctrl/dpllctrla.rs @@ -0,0 +1,207 @@ +#[doc = "Register `DPLLCTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DPLLCTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - On Demand"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - On Demand"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - On Demand"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - On Demand"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DPLL Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dpllctrla](index.html) module"] +pub struct DPLLCTRLA_SPEC; +impl crate::RegisterSpec for DPLLCTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dpllctrla::R](R) reader structure"] +impl crate::Readable for DPLLCTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dpllctrla::W](W) writer structure"] +impl crate::Writable for DPLLCTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DPLLCTRLA to value 0x80"] +impl crate::Resettable for DPLLCTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x80 + } +} diff --git a/pac/atsamc21e/src/oscctrl/dpllctrlb.rs b/pac/atsamc21e/src/oscctrl/dpllctrlb.rs new file mode 100644 index 000000000000..8400b0572dd0 --- /dev/null +++ b/pac/atsamc21e/src/oscctrl/dpllctrlb.rs @@ -0,0 +1,580 @@ +#[doc = "Register `DPLLCTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DPLLCTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Proportional Integral Filter Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FILTER_A { + #[doc = "0: Default filter mode"] + DEFAULT = 0, + #[doc = "1: Low bandwidth filter"] + LBFILT = 1, + #[doc = "2: High bandwidth filter"] + HBFILT = 2, + #[doc = "3: High damping filter"] + HDFILT = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FILTER_A) -> Self { + variant as _ + } +} +#[doc = "Field `FILTER` reader - Proportional Integral Filter Selection"] +pub struct FILTER_R(crate::FieldReader); +impl FILTER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FILTER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FILTER_A { + match self.bits { + 0 => FILTER_A::DEFAULT, + 1 => FILTER_A::LBFILT, + 2 => FILTER_A::HBFILT, + 3 => FILTER_A::HDFILT, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DEFAULT`"] + #[inline(always)] + pub fn is_default(&self) -> bool { + **self == FILTER_A::DEFAULT + } + #[doc = "Checks if the value of the field is `LBFILT`"] + #[inline(always)] + pub fn is_lbfilt(&self) -> bool { + **self == FILTER_A::LBFILT + } + #[doc = "Checks if the value of the field is `HBFILT`"] + #[inline(always)] + pub fn is_hbfilt(&self) -> bool { + **self == FILTER_A::HBFILT + } + #[doc = "Checks if the value of the field is `HDFILT`"] + #[inline(always)] + pub fn is_hdfilt(&self) -> bool { + **self == FILTER_A::HDFILT + } +} +impl core::ops::Deref for FILTER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTER` writer - Proportional Integral Filter Selection"] +pub struct FILTER_W<'a> { + w: &'a mut W, +} +impl<'a> FILTER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FILTER_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Default filter mode"] + #[inline(always)] + pub fn default(self) -> &'a mut W { + self.variant(FILTER_A::DEFAULT) + } + #[doc = "Low bandwidth filter"] + #[inline(always)] + pub fn lbfilt(self) -> &'a mut W { + self.variant(FILTER_A::LBFILT) + } + #[doc = "High bandwidth filter"] + #[inline(always)] + pub fn hbfilt(self) -> &'a mut W { + self.variant(FILTER_A::HBFILT) + } + #[doc = "High damping filter"] + #[inline(always)] + pub fn hdfilt(self) -> &'a mut W { + self.variant(FILTER_A::HDFILT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u32 & 0x03); + self.w + } +} +#[doc = "Field `LPEN` reader - Low-Power Enable"] +pub struct LPEN_R(crate::FieldReader); +impl LPEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LPEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LPEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LPEN` writer - Low-Power Enable"] +pub struct LPEN_W<'a> { + w: &'a mut W, +} +impl<'a> LPEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `WUF` reader - Wake Up Fast"] +pub struct WUF_R(crate::FieldReader); +impl WUF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WUF` writer - Wake Up Fast"] +pub struct WUF_W<'a> { + w: &'a mut W, +} +impl<'a> WUF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Reference Clock Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum REFCLK_A { + #[doc = "0: XOSC32K clock reference"] + XOSC32K = 0, + #[doc = "1: XOSC clock reference"] + XOSC = 1, + #[doc = "2: GCLK clock reference"] + GCLK = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: REFCLK_A) -> Self { + variant as _ + } +} +#[doc = "Field `REFCLK` reader - Reference Clock Selection"] +pub struct REFCLK_R(crate::FieldReader); +impl REFCLK_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REFCLK_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(REFCLK_A::XOSC32K), + 1 => Some(REFCLK_A::XOSC), + 2 => Some(REFCLK_A::GCLK), + _ => None, + } + } + #[doc = "Checks if the value of the field is `XOSC32K`"] + #[inline(always)] + pub fn is_xosc32k(&self) -> bool { + **self == REFCLK_A::XOSC32K + } + #[doc = "Checks if the value of the field is `XOSC`"] + #[inline(always)] + pub fn is_xosc(&self) -> bool { + **self == REFCLK_A::XOSC + } + #[doc = "Checks if the value of the field is `GCLK`"] + #[inline(always)] + pub fn is_gclk(&self) -> bool { + **self == REFCLK_A::GCLK + } +} +impl core::ops::Deref for REFCLK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REFCLK` writer - Reference Clock Selection"] +pub struct REFCLK_W<'a> { + w: &'a mut W, +} +impl<'a> REFCLK_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: REFCLK_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "XOSC32K clock reference"] + #[inline(always)] + pub fn xosc32k(self) -> &'a mut W { + self.variant(REFCLK_A::XOSC32K) + } + #[doc = "XOSC clock reference"] + #[inline(always)] + pub fn xosc(self) -> &'a mut W { + self.variant(REFCLK_A::XOSC) + } + #[doc = "GCLK clock reference"] + #[inline(always)] + pub fn gclk(self) -> &'a mut W { + self.variant(REFCLK_A::GCLK) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u32 & 0x03) << 4); + self.w + } +} +#[doc = "Lock Time\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum LTIME_A { + #[doc = "0: No time-out. Automatic lock."] + DEFAULT = 0, + #[doc = "4: Time-out if no lock within 8ms"] + _8MS = 4, + #[doc = "5: Time-out if no lock within 9ms"] + _9MS = 5, + #[doc = "6: Time-out if no lock within 10ms"] + _10MS = 6, + #[doc = "7: Time-out if no lock within 11ms"] + _11MS = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LTIME_A) -> Self { + variant as _ + } +} +#[doc = "Field `LTIME` reader - Lock Time"] +pub struct LTIME_R(crate::FieldReader); +impl LTIME_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LTIME_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(LTIME_A::DEFAULT), + 4 => Some(LTIME_A::_8MS), + 5 => Some(LTIME_A::_9MS), + 6 => Some(LTIME_A::_10MS), + 7 => Some(LTIME_A::_11MS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DEFAULT`"] + #[inline(always)] + pub fn is_default(&self) -> bool { + **self == LTIME_A::DEFAULT + } + #[doc = "Checks if the value of the field is `_8MS`"] + #[inline(always)] + pub fn is_8ms(&self) -> bool { + **self == LTIME_A::_8MS + } + #[doc = "Checks if the value of the field is `_9MS`"] + #[inline(always)] + pub fn is_9ms(&self) -> bool { + **self == LTIME_A::_9MS + } + #[doc = "Checks if the value of the field is `_10MS`"] + #[inline(always)] + pub fn is_10ms(&self) -> bool { + **self == LTIME_A::_10MS + } + #[doc = "Checks if the value of the field is `_11MS`"] + #[inline(always)] + pub fn is_11ms(&self) -> bool { + **self == LTIME_A::_11MS + } +} +impl core::ops::Deref for LTIME_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LTIME` writer - Lock Time"] +pub struct LTIME_W<'a> { + w: &'a mut W, +} +impl<'a> LTIME_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: LTIME_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No time-out. Automatic lock."] + #[inline(always)] + pub fn default(self) -> &'a mut W { + self.variant(LTIME_A::DEFAULT) + } + #[doc = "Time-out if no lock within 8ms"] + #[inline(always)] + pub fn _8ms(self) -> &'a mut W { + self.variant(LTIME_A::_8MS) + } + #[doc = "Time-out if no lock within 9ms"] + #[inline(always)] + pub fn _9ms(self) -> &'a mut W { + self.variant(LTIME_A::_9MS) + } + #[doc = "Time-out if no lock within 10ms"] + #[inline(always)] + pub fn _10ms(self) -> &'a mut W { + self.variant(LTIME_A::_10MS) + } + #[doc = "Time-out if no lock within 11ms"] + #[inline(always)] + pub fn _11ms(self) -> &'a mut W { + self.variant(LTIME_A::_11MS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +#[doc = "Field `LBYPASS` reader - Lock Bypass"] +pub struct LBYPASS_R(crate::FieldReader); +impl LBYPASS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LBYPASS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LBYPASS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LBYPASS` writer - Lock Bypass"] +pub struct LBYPASS_W<'a> { + w: &'a mut W, +} +impl<'a> LBYPASS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `DIV` reader - Clock Divider"] +pub struct DIV_R(crate::FieldReader); +impl DIV_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + DIV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIV` writer - Clock Divider"] +pub struct DIV_W<'a> { + w: &'a mut W, +} +impl<'a> DIV_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07ff << 16)) | ((value as u32 & 0x07ff) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Proportional Integral Filter Selection"] + #[inline(always)] + pub fn filter(&self) -> FILTER_R { + FILTER_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bit 2 - Low-Power Enable"] + #[inline(always)] + pub fn lpen(&self) -> LPEN_R { + LPEN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Wake Up Fast"] + #[inline(always)] + pub fn wuf(&self) -> WUF_R { + WUF_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bits 4:5 - Reference Clock Selection"] + #[inline(always)] + pub fn refclk(&self) -> REFCLK_R { + REFCLK_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bits 8:10 - Lock Time"] + #[inline(always)] + pub fn ltime(&self) -> LTIME_R { + LTIME_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 12 - Lock Bypass"] + #[inline(always)] + pub fn lbypass(&self) -> LBYPASS_R { + LBYPASS_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bits 16:26 - Clock Divider"] + #[inline(always)] + pub fn div(&self) -> DIV_R { + DIV_R::new(((self.bits >> 16) & 0x07ff) as u16) + } +} +impl W { + #[doc = "Bits 0:1 - Proportional Integral Filter Selection"] + #[inline(always)] + pub fn filter(&mut self) -> FILTER_W { + FILTER_W { w: self } + } + #[doc = "Bit 2 - Low-Power Enable"] + #[inline(always)] + pub fn lpen(&mut self) -> LPEN_W { + LPEN_W { w: self } + } + #[doc = "Bit 3 - Wake Up Fast"] + #[inline(always)] + pub fn wuf(&mut self) -> WUF_W { + WUF_W { w: self } + } + #[doc = "Bits 4:5 - Reference Clock Selection"] + #[inline(always)] + pub fn refclk(&mut self) -> REFCLK_W { + REFCLK_W { w: self } + } + #[doc = "Bits 8:10 - Lock Time"] + #[inline(always)] + pub fn ltime(&mut self) -> LTIME_W { + LTIME_W { w: self } + } + #[doc = "Bit 12 - Lock Bypass"] + #[inline(always)] + pub fn lbypass(&mut self) -> LBYPASS_W { + LBYPASS_W { w: self } + } + #[doc = "Bits 16:26 - Clock Divider"] + #[inline(always)] + pub fn div(&mut self) -> DIV_W { + DIV_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Digital Core Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dpllctrlb](index.html) module"] +pub struct DPLLCTRLB_SPEC; +impl crate::RegisterSpec for DPLLCTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dpllctrlb::R](R) reader structure"] +impl crate::Readable for DPLLCTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dpllctrlb::W](W) writer structure"] +impl crate::Writable for DPLLCTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DPLLCTRLB to value 0"] +impl crate::Resettable for DPLLCTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/oscctrl/dpllpresc.rs b/pac/atsamc21e/src/oscctrl/dpllpresc.rs new file mode 100644 index 000000000000..9de662161f99 --- /dev/null +++ b/pac/atsamc21e/src/oscctrl/dpllpresc.rs @@ -0,0 +1,165 @@ +#[doc = "Register `DPLLPRESC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DPLLPRESC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Output Clock Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESC_A { + #[doc = "0: DPLL output is divided by 1"] + DIV1 = 0, + #[doc = "1: DPLL output is divided by 2"] + DIV2 = 1, + #[doc = "2: DPLL output is divided by 4"] + DIV4 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESC_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESC` reader - Output Clock Prescaler"] +pub struct PRESC_R(crate::FieldReader); +impl PRESC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESC_A::DIV1), + 1 => Some(PRESC_A::DIV2), + 2 => Some(PRESC_A::DIV4), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == PRESC_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESC_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESC_A::DIV4 + } +} +impl core::ops::Deref for PRESC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESC` writer - Output Clock Prescaler"] +pub struct PRESC_W<'a> { + w: &'a mut W, +} +impl<'a> PRESC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESC_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "DPLL output is divided by 1"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESC_A::DIV1) + } + #[doc = "DPLL output is divided by 2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESC_A::DIV2) + } + #[doc = "DPLL output is divided by 4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESC_A::DIV4) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u8 & 0x03); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Output Clock Prescaler"] + #[inline(always)] + pub fn presc(&self) -> PRESC_R { + PRESC_R::new((self.bits & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Output Clock Prescaler"] + #[inline(always)] + pub fn presc(&mut self) -> PRESC_W { + PRESC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DPLL Prescaler\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dpllpresc](index.html) module"] +pub struct DPLLPRESC_SPEC; +impl crate::RegisterSpec for DPLLPRESC_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dpllpresc::R](R) reader structure"] +impl crate::Readable for DPLLPRESC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dpllpresc::W](W) writer structure"] +impl crate::Writable for DPLLPRESC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DPLLPRESC to value 0"] +impl crate::Resettable for DPLLPRESC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/oscctrl/dpllratio.rs b/pac/atsamc21e/src/oscctrl/dpllratio.rs new file mode 100644 index 000000000000..93b39e30f1a5 --- /dev/null +++ b/pac/atsamc21e/src/oscctrl/dpllratio.rs @@ -0,0 +1,140 @@ +#[doc = "Register `DPLLRATIO` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DPLLRATIO` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `LDR` reader - Loop Divider Ratio"] +pub struct LDR_R(crate::FieldReader); +impl LDR_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + LDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LDR` writer - Loop Divider Ratio"] +pub struct LDR_W<'a> { + w: &'a mut W, +} +impl<'a> LDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0fff) | (value as u32 & 0x0fff); + self.w + } +} +#[doc = "Field `LDRFRAC` reader - Loop Divider Ratio Fractional Part"] +pub struct LDRFRAC_R(crate::FieldReader); +impl LDRFRAC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LDRFRAC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LDRFRAC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LDRFRAC` writer - Loop Divider Ratio Fractional Part"] +pub struct LDRFRAC_W<'a> { + w: &'a mut W, +} +impl<'a> LDRFRAC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 16)) | ((value as u32 & 0x0f) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:11 - Loop Divider Ratio"] + #[inline(always)] + pub fn ldr(&self) -> LDR_R { + LDR_R::new((self.bits & 0x0fff) as u16) + } + #[doc = "Bits 16:19 - Loop Divider Ratio Fractional Part"] + #[inline(always)] + pub fn ldrfrac(&self) -> LDRFRAC_R { + LDRFRAC_R::new(((self.bits >> 16) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:11 - Loop Divider Ratio"] + #[inline(always)] + pub fn ldr(&mut self) -> LDR_W { + LDR_W { w: self } + } + #[doc = "Bits 16:19 - Loop Divider Ratio Fractional Part"] + #[inline(always)] + pub fn ldrfrac(&mut self) -> LDRFRAC_W { + LDRFRAC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DPLL Ratio Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dpllratio](index.html) module"] +pub struct DPLLRATIO_SPEC; +impl crate::RegisterSpec for DPLLRATIO_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dpllratio::R](R) reader structure"] +impl crate::Readable for DPLLRATIO_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dpllratio::W](W) writer structure"] +impl crate::Writable for DPLLRATIO_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DPLLRATIO to value 0"] +impl crate::Resettable for DPLLRATIO_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/oscctrl/dpllstatus.rs b/pac/atsamc21e/src/oscctrl/dpllstatus.rs new file mode 100644 index 000000000000..931900212816 --- /dev/null +++ b/pac/atsamc21e/src/oscctrl/dpllstatus.rs @@ -0,0 +1,73 @@ +#[doc = "Register `DPLLSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `LOCK` reader - DPLL Lock Status"] +pub struct LOCK_R(crate::FieldReader); +impl LOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKRDY` reader - DPLL Clock Ready"] +pub struct CLKRDY_R(crate::FieldReader); +impl CLKRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - DPLL Lock Status"] + #[inline(always)] + pub fn lock(&self) -> LOCK_R { + LOCK_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - DPLL Clock Ready"] + #[inline(always)] + pub fn clkrdy(&self) -> CLKRDY_R { + CLKRDY_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +#[doc = "DPLL Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dpllstatus](index.html) module"] +pub struct DPLLSTATUS_SPEC; +impl crate::RegisterSpec for DPLLSTATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dpllstatus::R](R) reader structure"] +impl crate::Readable for DPLLSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DPLLSTATUS to value 0"] +impl crate::Resettable for DPLLSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/oscctrl/dpllsyncbusy.rs b/pac/atsamc21e/src/oscctrl/dpllsyncbusy.rs new file mode 100644 index 000000000000..f9fb880a5a59 --- /dev/null +++ b/pac/atsamc21e/src/oscctrl/dpllsyncbusy.rs @@ -0,0 +1,93 @@ +#[doc = "Register `DPLLSYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `ENABLE` reader - DPLL Enable Synchronization Status"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLRATIO` reader - DPLL Ratio Synchronization Status"] +pub struct DPLLRATIO_R(crate::FieldReader); +impl DPLLRATIO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLRATIO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLRATIO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLPRESC` reader - DPLL Prescaler Synchronization Status"] +pub struct DPLLPRESC_R(crate::FieldReader); +impl DPLLPRESC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLPRESC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLPRESC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 1 - DPLL Enable Synchronization Status"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - DPLL Ratio Synchronization Status"] + #[inline(always)] + pub fn dpllratio(&self) -> DPLLRATIO_R { + DPLLRATIO_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - DPLL Prescaler Synchronization Status"] + #[inline(always)] + pub fn dpllpresc(&self) -> DPLLPRESC_R { + DPLLPRESC_R::new(((self.bits >> 3) & 0x01) != 0) + } +} +#[doc = "DPLL Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dpllsyncbusy](index.html) module"] +pub struct DPLLSYNCBUSY_SPEC; +impl crate::RegisterSpec for DPLLSYNCBUSY_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dpllsyncbusy::R](R) reader structure"] +impl crate::Readable for DPLLSYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DPLLSYNCBUSY to value 0"] +impl crate::Resettable for DPLLSYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/oscctrl/evctrl.rs b/pac/atsamc21e/src/oscctrl/evctrl.rs new file mode 100644 index 000000000000..e22ba62f0fe2 --- /dev/null +++ b/pac/atsamc21e/src/oscctrl/evctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CFDEO` reader - Clock Failure Detector Event Output Enable"] +pub struct CFDEO_R(crate::FieldReader); +impl CFDEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFDEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFDEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFDEO` writer - Clock Failure Detector Event Output Enable"] +pub struct CFDEO_W<'a> { + w: &'a mut W, +} +impl<'a> CFDEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Clock Failure Detector Event Output Enable"] + #[inline(always)] + pub fn cfdeo(&self) -> CFDEO_R { + CFDEO_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Clock Failure Detector Event Output Enable"] + #[inline(always)] + pub fn cfdeo(&mut self) -> CFDEO_W { + CFDEO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/oscctrl/intenclr.rs b/pac/atsamc21e/src/oscctrl/intenclr.rs new file mode 100644 index 000000000000..0ea0034a0c02 --- /dev/null +++ b/pac/atsamc21e/src/oscctrl/intenclr.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XOSCRDY` reader - XOSC Ready Interrupt Enable"] +pub struct XOSCRDY_R(crate::FieldReader); +impl XOSCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSCRDY` writer - XOSC Ready Interrupt Enable"] +pub struct XOSCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> XOSCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `XOSCFAIL` reader - XOSC Clock Failure Detector Interrupt Enable"] +pub struct XOSCFAIL_R(crate::FieldReader); +impl XOSCFAIL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSCFAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCFAIL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSCFAIL` writer - XOSC Clock Failure Detector Interrupt Enable"] +pub struct XOSCFAIL_W<'a> { + w: &'a mut W, +} +impl<'a> XOSCFAIL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `OSC48MRDY` reader - OSC48M Ready Interrupt Enable"] +pub struct OSC48MRDY_R(crate::FieldReader); +impl OSC48MRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC48MRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC48MRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC48MRDY` writer - OSC48M Ready Interrupt Enable"] +pub struct OSC48MRDY_W<'a> { + w: &'a mut W, +} +impl<'a> OSC48MRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `DPLLLCKR` reader - DPLL Lock Rise Interrupt Enable"] +pub struct DPLLLCKR_R(crate::FieldReader); +impl DPLLLCKR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKR` writer - DPLL Lock Rise Interrupt Enable"] +pub struct DPLLLCKR_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLCKR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `DPLLLCKF` reader - DPLL Lock Fall Interrupt Enable"] +pub struct DPLLLCKF_R(crate::FieldReader); +impl DPLLLCKF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKF` writer - DPLL Lock Fall Interrupt Enable"] +pub struct DPLLLCKF_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLCKF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `DPLLLTO` reader - DPLL Time Out Interrupt Enable"] +pub struct DPLLLTO_R(crate::FieldReader); +impl DPLLLTO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLTO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLTO` writer - DPLL Time Out Interrupt Enable"] +pub struct DPLLLTO_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLTO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `DPLLLDRTO` reader - DPLL Ratio Ready Interrupt Enable"] +pub struct DPLLLDRTO_R(crate::FieldReader); +impl DPLLLDRTO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLDRTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLDRTO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLDRTO` writer - DPLL Ratio Ready Interrupt Enable"] +pub struct DPLLLDRTO_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLDRTO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +impl R { + #[doc = "Bit 0 - XOSC Ready Interrupt Enable"] + #[inline(always)] + pub fn xoscrdy(&self) -> XOSCRDY_R { + XOSCRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - XOSC Clock Failure Detector Interrupt Enable"] + #[inline(always)] + pub fn xoscfail(&self) -> XOSCFAIL_R { + XOSCFAIL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - OSC48M Ready Interrupt Enable"] + #[inline(always)] + pub fn osc48mrdy(&self) -> OSC48MRDY_R { + OSC48MRDY_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 8 - DPLL Lock Rise Interrupt Enable"] + #[inline(always)] + pub fn dplllckr(&self) -> DPLLLCKR_R { + DPLLLCKR_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - DPLL Lock Fall Interrupt Enable"] + #[inline(always)] + pub fn dplllckf(&self) -> DPLLLCKF_R { + DPLLLCKF_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - DPLL Time Out Interrupt Enable"] + #[inline(always)] + pub fn dplllto(&self) -> DPLLLTO_R { + DPLLLTO_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - DPLL Ratio Ready Interrupt Enable"] + #[inline(always)] + pub fn dpllldrto(&self) -> DPLLLDRTO_R { + DPLLLDRTO_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - XOSC Ready Interrupt Enable"] + #[inline(always)] + pub fn xoscrdy(&mut self) -> XOSCRDY_W { + XOSCRDY_W { w: self } + } + #[doc = "Bit 1 - XOSC Clock Failure Detector Interrupt Enable"] + #[inline(always)] + pub fn xoscfail(&mut self) -> XOSCFAIL_W { + XOSCFAIL_W { w: self } + } + #[doc = "Bit 4 - OSC48M Ready Interrupt Enable"] + #[inline(always)] + pub fn osc48mrdy(&mut self) -> OSC48MRDY_W { + OSC48MRDY_W { w: self } + } + #[doc = "Bit 8 - DPLL Lock Rise Interrupt Enable"] + #[inline(always)] + pub fn dplllckr(&mut self) -> DPLLLCKR_W { + DPLLLCKR_W { w: self } + } + #[doc = "Bit 9 - DPLL Lock Fall Interrupt Enable"] + #[inline(always)] + pub fn dplllckf(&mut self) -> DPLLLCKF_W { + DPLLLCKF_W { w: self } + } + #[doc = "Bit 10 - DPLL Time Out Interrupt Enable"] + #[inline(always)] + pub fn dplllto(&mut self) -> DPLLLTO_W { + DPLLLTO_W { w: self } + } + #[doc = "Bit 11 - DPLL Ratio Ready Interrupt Enable"] + #[inline(always)] + pub fn dpllldrto(&mut self) -> DPLLLDRTO_W { + DPLLLDRTO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/oscctrl/intenset.rs b/pac/atsamc21e/src/oscctrl/intenset.rs new file mode 100644 index 000000000000..2890541e4414 --- /dev/null +++ b/pac/atsamc21e/src/oscctrl/intenset.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XOSCRDY` reader - XOSC Ready Interrupt Enable"] +pub struct XOSCRDY_R(crate::FieldReader); +impl XOSCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSCRDY` writer - XOSC Ready Interrupt Enable"] +pub struct XOSCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> XOSCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `XOSCFAIL` reader - XOSC Clock Failure Detector Interrupt Enable"] +pub struct XOSCFAIL_R(crate::FieldReader); +impl XOSCFAIL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSCFAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCFAIL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSCFAIL` writer - XOSC Clock Failure Detector Interrupt Enable"] +pub struct XOSCFAIL_W<'a> { + w: &'a mut W, +} +impl<'a> XOSCFAIL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `OSC48MRDY` reader - OSC48M Ready Interrupt Enable"] +pub struct OSC48MRDY_R(crate::FieldReader); +impl OSC48MRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC48MRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC48MRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC48MRDY` writer - OSC48M Ready Interrupt Enable"] +pub struct OSC48MRDY_W<'a> { + w: &'a mut W, +} +impl<'a> OSC48MRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `DPLLLCKR` reader - DPLL Lock Rise Interrupt Enable"] +pub struct DPLLLCKR_R(crate::FieldReader); +impl DPLLLCKR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKR` writer - DPLL Lock Rise Interrupt Enable"] +pub struct DPLLLCKR_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLCKR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `DPLLLCKF` reader - DPLL Lock Fall Interrupt Enable"] +pub struct DPLLLCKF_R(crate::FieldReader); +impl DPLLLCKF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKF` writer - DPLL Lock Fall Interrupt Enable"] +pub struct DPLLLCKF_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLCKF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `DPLLLTO` reader - DPLL Time Out Interrupt Enable"] +pub struct DPLLLTO_R(crate::FieldReader); +impl DPLLLTO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLTO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLTO` writer - DPLL Time Out Interrupt Enable"] +pub struct DPLLLTO_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLTO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `DPLLLDRTO` reader - DPLL Ratio Ready Interrupt Enable"] +pub struct DPLLLDRTO_R(crate::FieldReader); +impl DPLLLDRTO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLDRTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLDRTO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLDRTO` writer - DPLL Ratio Ready Interrupt Enable"] +pub struct DPLLLDRTO_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLDRTO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +impl R { + #[doc = "Bit 0 - XOSC Ready Interrupt Enable"] + #[inline(always)] + pub fn xoscrdy(&self) -> XOSCRDY_R { + XOSCRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - XOSC Clock Failure Detector Interrupt Enable"] + #[inline(always)] + pub fn xoscfail(&self) -> XOSCFAIL_R { + XOSCFAIL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - OSC48M Ready Interrupt Enable"] + #[inline(always)] + pub fn osc48mrdy(&self) -> OSC48MRDY_R { + OSC48MRDY_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 8 - DPLL Lock Rise Interrupt Enable"] + #[inline(always)] + pub fn dplllckr(&self) -> DPLLLCKR_R { + DPLLLCKR_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - DPLL Lock Fall Interrupt Enable"] + #[inline(always)] + pub fn dplllckf(&self) -> DPLLLCKF_R { + DPLLLCKF_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - DPLL Time Out Interrupt Enable"] + #[inline(always)] + pub fn dplllto(&self) -> DPLLLTO_R { + DPLLLTO_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - DPLL Ratio Ready Interrupt Enable"] + #[inline(always)] + pub fn dpllldrto(&self) -> DPLLLDRTO_R { + DPLLLDRTO_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - XOSC Ready Interrupt Enable"] + #[inline(always)] + pub fn xoscrdy(&mut self) -> XOSCRDY_W { + XOSCRDY_W { w: self } + } + #[doc = "Bit 1 - XOSC Clock Failure Detector Interrupt Enable"] + #[inline(always)] + pub fn xoscfail(&mut self) -> XOSCFAIL_W { + XOSCFAIL_W { w: self } + } + #[doc = "Bit 4 - OSC48M Ready Interrupt Enable"] + #[inline(always)] + pub fn osc48mrdy(&mut self) -> OSC48MRDY_W { + OSC48MRDY_W { w: self } + } + #[doc = "Bit 8 - DPLL Lock Rise Interrupt Enable"] + #[inline(always)] + pub fn dplllckr(&mut self) -> DPLLLCKR_W { + DPLLLCKR_W { w: self } + } + #[doc = "Bit 9 - DPLL Lock Fall Interrupt Enable"] + #[inline(always)] + pub fn dplllckf(&mut self) -> DPLLLCKF_W { + DPLLLCKF_W { w: self } + } + #[doc = "Bit 10 - DPLL Time Out Interrupt Enable"] + #[inline(always)] + pub fn dplllto(&mut self) -> DPLLLTO_W { + DPLLLTO_W { w: self } + } + #[doc = "Bit 11 - DPLL Ratio Ready Interrupt Enable"] + #[inline(always)] + pub fn dpllldrto(&mut self) -> DPLLLDRTO_W { + DPLLLDRTO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/oscctrl/intflag.rs b/pac/atsamc21e/src/oscctrl/intflag.rs new file mode 100644 index 000000000000..71e452a1b571 --- /dev/null +++ b/pac/atsamc21e/src/oscctrl/intflag.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XOSCRDY` reader - XOSC Ready"] +pub struct XOSCRDY_R(crate::FieldReader); +impl XOSCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSCRDY` writer - XOSC Ready"] +pub struct XOSCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> XOSCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `XOSCFAIL` reader - XOSC Clock Failure Detector"] +pub struct XOSCFAIL_R(crate::FieldReader); +impl XOSCFAIL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSCFAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCFAIL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSCFAIL` writer - XOSC Clock Failure Detector"] +pub struct XOSCFAIL_W<'a> { + w: &'a mut W, +} +impl<'a> XOSCFAIL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `OSC48MRDY` reader - OSC48M Ready"] +pub struct OSC48MRDY_R(crate::FieldReader); +impl OSC48MRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC48MRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC48MRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC48MRDY` writer - OSC48M Ready"] +pub struct OSC48MRDY_W<'a> { + w: &'a mut W, +} +impl<'a> OSC48MRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `DPLLLCKR` reader - DPLL Lock Rise"] +pub struct DPLLLCKR_R(crate::FieldReader); +impl DPLLLCKR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKR` writer - DPLL Lock Rise"] +pub struct DPLLLCKR_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLCKR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `DPLLLCKF` reader - DPLL Lock Fall"] +pub struct DPLLLCKF_R(crate::FieldReader); +impl DPLLLCKF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKF` writer - DPLL Lock Fall"] +pub struct DPLLLCKF_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLCKF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `DPLLLTO` reader - DPLL Timeout"] +pub struct DPLLLTO_R(crate::FieldReader); +impl DPLLLTO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLTO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLTO` writer - DPLL Timeout"] +pub struct DPLLLTO_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLTO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `DPLLLDRTO` reader - DPLL Ratio Ready"] +pub struct DPLLLDRTO_R(crate::FieldReader); +impl DPLLLDRTO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLDRTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLDRTO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLDRTO` writer - DPLL Ratio Ready"] +pub struct DPLLLDRTO_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLDRTO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +impl R { + #[doc = "Bit 0 - XOSC Ready"] + #[inline(always)] + pub fn xoscrdy(&self) -> XOSCRDY_R { + XOSCRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - XOSC Clock Failure Detector"] + #[inline(always)] + pub fn xoscfail(&self) -> XOSCFAIL_R { + XOSCFAIL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - OSC48M Ready"] + #[inline(always)] + pub fn osc48mrdy(&self) -> OSC48MRDY_R { + OSC48MRDY_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 8 - DPLL Lock Rise"] + #[inline(always)] + pub fn dplllckr(&self) -> DPLLLCKR_R { + DPLLLCKR_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - DPLL Lock Fall"] + #[inline(always)] + pub fn dplllckf(&self) -> DPLLLCKF_R { + DPLLLCKF_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - DPLL Timeout"] + #[inline(always)] + pub fn dplllto(&self) -> DPLLLTO_R { + DPLLLTO_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - DPLL Ratio Ready"] + #[inline(always)] + pub fn dpllldrto(&self) -> DPLLLDRTO_R { + DPLLLDRTO_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - XOSC Ready"] + #[inline(always)] + pub fn xoscrdy(&mut self) -> XOSCRDY_W { + XOSCRDY_W { w: self } + } + #[doc = "Bit 1 - XOSC Clock Failure Detector"] + #[inline(always)] + pub fn xoscfail(&mut self) -> XOSCFAIL_W { + XOSCFAIL_W { w: self } + } + #[doc = "Bit 4 - OSC48M Ready"] + #[inline(always)] + pub fn osc48mrdy(&mut self) -> OSC48MRDY_W { + OSC48MRDY_W { w: self } + } + #[doc = "Bit 8 - DPLL Lock Rise"] + #[inline(always)] + pub fn dplllckr(&mut self) -> DPLLLCKR_W { + DPLLLCKR_W { w: self } + } + #[doc = "Bit 9 - DPLL Lock Fall"] + #[inline(always)] + pub fn dplllckf(&mut self) -> DPLLLCKF_W { + DPLLLCKF_W { w: self } + } + #[doc = "Bit 10 - DPLL Timeout"] + #[inline(always)] + pub fn dplllto(&mut self) -> DPLLLTO_W { + DPLLLTO_W { w: self } + } + #[doc = "Bit 11 - DPLL Ratio Ready"] + #[inline(always)] + pub fn dpllldrto(&mut self) -> DPLLLDRTO_W { + DPLLLDRTO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/oscctrl/osc48mctrl.rs b/pac/atsamc21e/src/oscctrl/osc48mctrl.rs new file mode 100644 index 000000000000..8314e21e5775 --- /dev/null +++ b/pac/atsamc21e/src/oscctrl/osc48mctrl.rs @@ -0,0 +1,207 @@ +#[doc = "Register `OSC48MCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OSC48MCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Oscillator Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Oscillator Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - On Demand Control"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - On Demand Control"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "48MHz Internal Oscillator (OSC48M) Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [osc48mctrl](index.html) module"] +pub struct OSC48MCTRL_SPEC; +impl crate::RegisterSpec for OSC48MCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [osc48mctrl::R](R) reader structure"] +impl crate::Readable for OSC48MCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [osc48mctrl::W](W) writer structure"] +impl crate::Writable for OSC48MCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OSC48MCTRL to value 0x82"] +impl crate::Resettable for OSC48MCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x82 + } +} diff --git a/pac/atsamc21e/src/oscctrl/osc48mdiv.rs b/pac/atsamc21e/src/oscctrl/osc48mdiv.rs new file mode 100644 index 000000000000..4ed854b09284 --- /dev/null +++ b/pac/atsamc21e/src/oscctrl/osc48mdiv.rs @@ -0,0 +1,334 @@ +#[doc = "Register `OSC48MDIV` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OSC48MDIV` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "OSC48M Division Factor\n\nValue on reset: 11"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DIV_A { + #[doc = "0: 48 MHz"] + DIV1 = 0, + #[doc = "1: 24 MHz"] + DIV2 = 1, + #[doc = "2: 16 MHz"] + DIV3 = 2, + #[doc = "3: 12 MHz"] + DIV4 = 3, + #[doc = "4: 9.6 MHz"] + DIV5 = 4, + #[doc = "5: 8 MHz"] + DIV6 = 5, + #[doc = "6: 6.86 MHz"] + DIV7 = 6, + #[doc = "7: 6 MHz"] + DIV8 = 7, + #[doc = "8: 5.33 MHz"] + DIV9 = 8, + #[doc = "9: 4.8 MHz"] + DIV10 = 9, + #[doc = "10: 4.36 MHz"] + DIV11 = 10, + #[doc = "11: 4 MHz"] + DIV12 = 11, + #[doc = "12: 3.69 MHz"] + DIV13 = 12, + #[doc = "13: 3.43 MHz"] + DIV14 = 13, + #[doc = "14: 3.2 MHz"] + DIV15 = 14, + #[doc = "15: 3 MHz"] + DIV16 = 15, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DIV_A) -> Self { + variant as _ + } +} +#[doc = "Field `DIV` reader - OSC48M Division Factor"] +pub struct DIV_R(crate::FieldReader); +impl DIV_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DIV_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DIV_A { + match self.bits { + 0 => DIV_A::DIV1, + 1 => DIV_A::DIV2, + 2 => DIV_A::DIV3, + 3 => DIV_A::DIV4, + 4 => DIV_A::DIV5, + 5 => DIV_A::DIV6, + 6 => DIV_A::DIV7, + 7 => DIV_A::DIV8, + 8 => DIV_A::DIV9, + 9 => DIV_A::DIV10, + 10 => DIV_A::DIV11, + 11 => DIV_A::DIV12, + 12 => DIV_A::DIV13, + 13 => DIV_A::DIV14, + 14 => DIV_A::DIV15, + 15 => DIV_A::DIV16, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == DIV_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == DIV_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV3`"] + #[inline(always)] + pub fn is_div3(&self) -> bool { + **self == DIV_A::DIV3 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == DIV_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV5`"] + #[inline(always)] + pub fn is_div5(&self) -> bool { + **self == DIV_A::DIV5 + } + #[doc = "Checks if the value of the field is `DIV6`"] + #[inline(always)] + pub fn is_div6(&self) -> bool { + **self == DIV_A::DIV6 + } + #[doc = "Checks if the value of the field is `DIV7`"] + #[inline(always)] + pub fn is_div7(&self) -> bool { + **self == DIV_A::DIV7 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == DIV_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV9`"] + #[inline(always)] + pub fn is_div9(&self) -> bool { + **self == DIV_A::DIV9 + } + #[doc = "Checks if the value of the field is `DIV10`"] + #[inline(always)] + pub fn is_div10(&self) -> bool { + **self == DIV_A::DIV10 + } + #[doc = "Checks if the value of the field is `DIV11`"] + #[inline(always)] + pub fn is_div11(&self) -> bool { + **self == DIV_A::DIV11 + } + #[doc = "Checks if the value of the field is `DIV12`"] + #[inline(always)] + pub fn is_div12(&self) -> bool { + **self == DIV_A::DIV12 + } + #[doc = "Checks if the value of the field is `DIV13`"] + #[inline(always)] + pub fn is_div13(&self) -> bool { + **self == DIV_A::DIV13 + } + #[doc = "Checks if the value of the field is `DIV14`"] + #[inline(always)] + pub fn is_div14(&self) -> bool { + **self == DIV_A::DIV14 + } + #[doc = "Checks if the value of the field is `DIV15`"] + #[inline(always)] + pub fn is_div15(&self) -> bool { + **self == DIV_A::DIV15 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == DIV_A::DIV16 + } +} +impl core::ops::Deref for DIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIV` writer - OSC48M Division Factor"] +pub struct DIV_W<'a> { + w: &'a mut W, +} +impl<'a> DIV_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DIV_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "48 MHz"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(DIV_A::DIV1) + } + #[doc = "24 MHz"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(DIV_A::DIV2) + } + #[doc = "16 MHz"] + #[inline(always)] + pub fn div3(self) -> &'a mut W { + self.variant(DIV_A::DIV3) + } + #[doc = "12 MHz"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(DIV_A::DIV4) + } + #[doc = "9.6 MHz"] + #[inline(always)] + pub fn div5(self) -> &'a mut W { + self.variant(DIV_A::DIV5) + } + #[doc = "8 MHz"] + #[inline(always)] + pub fn div6(self) -> &'a mut W { + self.variant(DIV_A::DIV6) + } + #[doc = "6.86 MHz"] + #[inline(always)] + pub fn div7(self) -> &'a mut W { + self.variant(DIV_A::DIV7) + } + #[doc = "6 MHz"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(DIV_A::DIV8) + } + #[doc = "5.33 MHz"] + #[inline(always)] + pub fn div9(self) -> &'a mut W { + self.variant(DIV_A::DIV9) + } + #[doc = "4.8 MHz"] + #[inline(always)] + pub fn div10(self) -> &'a mut W { + self.variant(DIV_A::DIV10) + } + #[doc = "4.36 MHz"] + #[inline(always)] + pub fn div11(self) -> &'a mut W { + self.variant(DIV_A::DIV11) + } + #[doc = "4 MHz"] + #[inline(always)] + pub fn div12(self) -> &'a mut W { + self.variant(DIV_A::DIV12) + } + #[doc = "3.69 MHz"] + #[inline(always)] + pub fn div13(self) -> &'a mut W { + self.variant(DIV_A::DIV13) + } + #[doc = "3.43 MHz"] + #[inline(always)] + pub fn div14(self) -> &'a mut W { + self.variant(DIV_A::DIV14) + } + #[doc = "3.2 MHz"] + #[inline(always)] + pub fn div15(self) -> &'a mut W { + self.variant(DIV_A::DIV15) + } + #[doc = "3 MHz"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(DIV_A::DIV16) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - OSC48M Division Factor"] + #[inline(always)] + pub fn div(&self) -> DIV_R { + DIV_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - OSC48M Division Factor"] + #[inline(always)] + pub fn div(&mut self) -> DIV_W { + DIV_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OSC48M Divider\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [osc48mdiv](index.html) module"] +pub struct OSC48MDIV_SPEC; +impl crate::RegisterSpec for OSC48MDIV_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [osc48mdiv::R](R) reader structure"] +impl crate::Readable for OSC48MDIV_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [osc48mdiv::W](W) writer structure"] +impl crate::Writable for OSC48MDIV_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OSC48MDIV to value 0x0b"] +impl crate::Resettable for OSC48MDIV_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0b + } +} diff --git a/pac/atsamc21e/src/oscctrl/osc48mstup.rs b/pac/atsamc21e/src/oscctrl/osc48mstup.rs new file mode 100644 index 000000000000..34da6bb7ef11 --- /dev/null +++ b/pac/atsamc21e/src/oscctrl/osc48mstup.rs @@ -0,0 +1,230 @@ +#[doc = "Register `OSC48MSTUP` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OSC48MSTUP` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Startup Time\n\nValue on reset: 7"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum STARTUP_A { + #[doc = "0: 166 ns"] + CYCLE8 = 0, + #[doc = "1: 333 ns"] + CYCLE16 = 1, + #[doc = "2: 667 ns"] + CYCLE32 = 2, + #[doc = "3: 1.333 us"] + CYCLE64 = 3, + #[doc = "4: 2.667 us"] + CYCLE128 = 4, + #[doc = "5: 5.333 us"] + CYCLE256 = 5, + #[doc = "6: 10.667 us"] + CYCLE512 = 6, + #[doc = "7: 21.333 us"] + CYCLE1024 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: STARTUP_A) -> Self { + variant as _ + } +} +#[doc = "Field `STARTUP` reader - Startup Time"] +pub struct STARTUP_R(crate::FieldReader); +impl STARTUP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + STARTUP_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STARTUP_A { + match self.bits { + 0 => STARTUP_A::CYCLE8, + 1 => STARTUP_A::CYCLE16, + 2 => STARTUP_A::CYCLE32, + 3 => STARTUP_A::CYCLE64, + 4 => STARTUP_A::CYCLE128, + 5 => STARTUP_A::CYCLE256, + 6 => STARTUP_A::CYCLE512, + 7 => STARTUP_A::CYCLE1024, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `CYCLE8`"] + #[inline(always)] + pub fn is_cycle8(&self) -> bool { + **self == STARTUP_A::CYCLE8 + } + #[doc = "Checks if the value of the field is `CYCLE16`"] + #[inline(always)] + pub fn is_cycle16(&self) -> bool { + **self == STARTUP_A::CYCLE16 + } + #[doc = "Checks if the value of the field is `CYCLE32`"] + #[inline(always)] + pub fn is_cycle32(&self) -> bool { + **self == STARTUP_A::CYCLE32 + } + #[doc = "Checks if the value of the field is `CYCLE64`"] + #[inline(always)] + pub fn is_cycle64(&self) -> bool { + **self == STARTUP_A::CYCLE64 + } + #[doc = "Checks if the value of the field is `CYCLE128`"] + #[inline(always)] + pub fn is_cycle128(&self) -> bool { + **self == STARTUP_A::CYCLE128 + } + #[doc = "Checks if the value of the field is `CYCLE256`"] + #[inline(always)] + pub fn is_cycle256(&self) -> bool { + **self == STARTUP_A::CYCLE256 + } + #[doc = "Checks if the value of the field is `CYCLE512`"] + #[inline(always)] + pub fn is_cycle512(&self) -> bool { + **self == STARTUP_A::CYCLE512 + } + #[doc = "Checks if the value of the field is `CYCLE1024`"] + #[inline(always)] + pub fn is_cycle1024(&self) -> bool { + **self == STARTUP_A::CYCLE1024 + } +} +impl core::ops::Deref for STARTUP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STARTUP` writer - Startup Time"] +pub struct STARTUP_W<'a> { + w: &'a mut W, +} +impl<'a> STARTUP_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: STARTUP_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "166 ns"] + #[inline(always)] + pub fn cycle8(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE8) + } + #[doc = "333 ns"] + #[inline(always)] + pub fn cycle16(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE16) + } + #[doc = "667 ns"] + #[inline(always)] + pub fn cycle32(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE32) + } + #[doc = "1.333 us"] + #[inline(always)] + pub fn cycle64(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE64) + } + #[doc = "2.667 us"] + #[inline(always)] + pub fn cycle128(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE128) + } + #[doc = "5.333 us"] + #[inline(always)] + pub fn cycle256(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE256) + } + #[doc = "10.667 us"] + #[inline(always)] + pub fn cycle512(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE512) + } + #[doc = "21.333 us"] + #[inline(always)] + pub fn cycle1024(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Startup Time"] + #[inline(always)] + pub fn startup(&self) -> STARTUP_R { + STARTUP_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Startup Time"] + #[inline(always)] + pub fn startup(&mut self) -> STARTUP_W { + STARTUP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OSC48M Startup Time\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [osc48mstup](index.html) module"] +pub struct OSC48MSTUP_SPEC; +impl crate::RegisterSpec for OSC48MSTUP_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [osc48mstup::R](R) reader structure"] +impl crate::Readable for OSC48MSTUP_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [osc48mstup::W](W) writer structure"] +impl crate::Writable for OSC48MSTUP_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OSC48MSTUP to value 0x07"] +impl crate::Resettable for OSC48MSTUP_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x07 + } +} diff --git a/pac/atsamc21e/src/oscctrl/osc48msyncbusy.rs b/pac/atsamc21e/src/oscctrl/osc48msyncbusy.rs new file mode 100644 index 000000000000..8d4410ae630a --- /dev/null +++ b/pac/atsamc21e/src/oscctrl/osc48msyncbusy.rs @@ -0,0 +1,53 @@ +#[doc = "Register `OSC48MSYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `OSC48MDIV` reader - OSC48MDIV Synchronization Status"] +pub struct OSC48MDIV_R(crate::FieldReader); +impl OSC48MDIV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC48MDIV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC48MDIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 2 - OSC48MDIV Synchronization Status"] + #[inline(always)] + pub fn osc48mdiv(&self) -> OSC48MDIV_R { + OSC48MDIV_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +#[doc = "OSC48M Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [osc48msyncbusy](index.html) module"] +pub struct OSC48MSYNCBUSY_SPEC; +impl crate::RegisterSpec for OSC48MSYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [osc48msyncbusy::R](R) reader structure"] +impl crate::Readable for OSC48MSYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets OSC48MSYNCBUSY to value 0"] +impl crate::Resettable for OSC48MSYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/oscctrl/status.rs b/pac/atsamc21e/src/oscctrl/status.rs new file mode 100644 index 000000000000..3025966192a3 --- /dev/null +++ b/pac/atsamc21e/src/oscctrl/status.rs @@ -0,0 +1,193 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `XOSCRDY` reader - XOSC Ready"] +pub struct XOSCRDY_R(crate::FieldReader); +impl XOSCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSCFAIL` reader - XOSC Clock Failure Detector"] +pub struct XOSCFAIL_R(crate::FieldReader); +impl XOSCFAIL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSCFAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCFAIL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSCCKSW` reader - XOSC Clock Switch"] +pub struct XOSCCKSW_R(crate::FieldReader); +impl XOSCCKSW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSCCKSW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCCKSW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC48MRDY` reader - OSC48M Ready"] +pub struct OSC48MRDY_R(crate::FieldReader); +impl OSC48MRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC48MRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC48MRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKR` reader - DPLL Lock Rise"] +pub struct DPLLLCKR_R(crate::FieldReader); +impl DPLLLCKR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKF` reader - DPLL Lock Fall"] +pub struct DPLLLCKF_R(crate::FieldReader); +impl DPLLLCKF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLTO` reader - DPLL Timeout"] +pub struct DPLLTO_R(crate::FieldReader); +impl DPLLTO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLTO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLDRTO` reader - DPLL Ratio Ready"] +pub struct DPLLLDRTO_R(crate::FieldReader); +impl DPLLLDRTO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLDRTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLDRTO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - XOSC Ready"] + #[inline(always)] + pub fn xoscrdy(&self) -> XOSCRDY_R { + XOSCRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - XOSC Clock Failure Detector"] + #[inline(always)] + pub fn xoscfail(&self) -> XOSCFAIL_R { + XOSCFAIL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - XOSC Clock Switch"] + #[inline(always)] + pub fn xosccksw(&self) -> XOSCCKSW_R { + XOSCCKSW_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 4 - OSC48M Ready"] + #[inline(always)] + pub fn osc48mrdy(&self) -> OSC48MRDY_R { + OSC48MRDY_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 8 - DPLL Lock Rise"] + #[inline(always)] + pub fn dplllckr(&self) -> DPLLLCKR_R { + DPLLLCKR_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - DPLL Lock Fall"] + #[inline(always)] + pub fn dplllckf(&self) -> DPLLLCKF_R { + DPLLLCKF_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - DPLL Timeout"] + #[inline(always)] + pub fn dpllto(&self) -> DPLLTO_R { + DPLLTO_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - DPLL Ratio Ready"] + #[inline(always)] + pub fn dpllldrto(&self) -> DPLLLDRTO_R { + DPLLLDRTO_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +#[doc = "Power and Clocks Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/oscctrl/xoscctrl.rs b/pac/atsamc21e/src/oscctrl/xoscctrl.rs new file mode 100644 index 000000000000..3a5319565c10 --- /dev/null +++ b/pac/atsamc21e/src/oscctrl/xoscctrl.rs @@ -0,0 +1,788 @@ +#[doc = "Register `XOSCCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `XOSCCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Oscillator Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Oscillator Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `XTALEN` reader - Crystal Oscillator Enable"] +pub struct XTALEN_R(crate::FieldReader); +impl XTALEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XTALEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XTALEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XTALEN` writer - Crystal Oscillator Enable"] +pub struct XTALEN_W<'a> { + w: &'a mut W, +} +impl<'a> XTALEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CFDEN` reader - Xosc Clock Failure Detector Enable"] +pub struct CFDEN_R(crate::FieldReader); +impl CFDEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFDEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFDEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFDEN` writer - Xosc Clock Failure Detector Enable"] +pub struct CFDEN_W<'a> { + w: &'a mut W, +} +impl<'a> CFDEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `SWBEN` reader - Xosc Clock Switch Enable"] +pub struct SWBEN_R(crate::FieldReader); +impl SWBEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWBEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWBEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWBEN` writer - Xosc Clock Switch Enable"] +pub struct SWBEN_W<'a> { + w: &'a mut W, +} +impl<'a> SWBEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - On Demand Control"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - On Demand Control"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Oscillator Gain\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum GAIN_A { + #[doc = "0: 2 MHz"] + GAIN2 = 0, + #[doc = "1: 4 MHz"] + GAIN4 = 1, + #[doc = "2: 8 MHz"] + GAIN8 = 2, + #[doc = "3: 16 MHz"] + GAIN16 = 3, + #[doc = "4: 30 MHz"] + GAIN30 = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: GAIN_A) -> Self { + variant as _ + } +} +#[doc = "Field `GAIN` reader - Oscillator Gain"] +pub struct GAIN_R(crate::FieldReader); +impl GAIN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + GAIN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(GAIN_A::GAIN2), + 1 => Some(GAIN_A::GAIN4), + 2 => Some(GAIN_A::GAIN8), + 3 => Some(GAIN_A::GAIN16), + 4 => Some(GAIN_A::GAIN30), + _ => None, + } + } + #[doc = "Checks if the value of the field is `GAIN2`"] + #[inline(always)] + pub fn is_gain2(&self) -> bool { + **self == GAIN_A::GAIN2 + } + #[doc = "Checks if the value of the field is `GAIN4`"] + #[inline(always)] + pub fn is_gain4(&self) -> bool { + **self == GAIN_A::GAIN4 + } + #[doc = "Checks if the value of the field is `GAIN8`"] + #[inline(always)] + pub fn is_gain8(&self) -> bool { + **self == GAIN_A::GAIN8 + } + #[doc = "Checks if the value of the field is `GAIN16`"] + #[inline(always)] + pub fn is_gain16(&self) -> bool { + **self == GAIN_A::GAIN16 + } + #[doc = "Checks if the value of the field is `GAIN30`"] + #[inline(always)] + pub fn is_gain30(&self) -> bool { + **self == GAIN_A::GAIN30 + } +} +impl core::ops::Deref for GAIN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GAIN` writer - Oscillator Gain"] +pub struct GAIN_W<'a> { + w: &'a mut W, +} +impl<'a> GAIN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: GAIN_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "2 MHz"] + #[inline(always)] + pub fn gain2(self) -> &'a mut W { + self.variant(GAIN_A::GAIN2) + } + #[doc = "4 MHz"] + #[inline(always)] + pub fn gain4(self) -> &'a mut W { + self.variant(GAIN_A::GAIN4) + } + #[doc = "8 MHz"] + #[inline(always)] + pub fn gain8(self) -> &'a mut W { + self.variant(GAIN_A::GAIN8) + } + #[doc = "16 MHz"] + #[inline(always)] + pub fn gain16(self) -> &'a mut W { + self.variant(GAIN_A::GAIN16) + } + #[doc = "30 MHz"] + #[inline(always)] + pub fn gain30(self) -> &'a mut W { + self.variant(GAIN_A::GAIN30) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u16 & 0x07) << 8); + self.w + } +} +#[doc = "Field `AMPGC` reader - Automatic Amplitude Gain Control"] +pub struct AMPGC_R(crate::FieldReader); +impl AMPGC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AMPGC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AMPGC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AMPGC` writer - Automatic Amplitude Gain Control"] +pub struct AMPGC_W<'a> { + w: &'a mut W, +} +impl<'a> AMPGC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u16 & 0x01) << 11); + self.w + } +} +#[doc = "Start-Up Time\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum STARTUP_A { + #[doc = "0: 31 us"] + CYCLE1 = 0, + #[doc = "1: 61 us"] + CYCLE2 = 1, + #[doc = "2: 122 us"] + CYCLE4 = 2, + #[doc = "3: 244 us"] + CYCLE8 = 3, + #[doc = "4: 488 us"] + CYCLE16 = 4, + #[doc = "5: 977 us"] + CYCLE32 = 5, + #[doc = "6: 1953 us"] + CYCLE64 = 6, + #[doc = "7: 3906 us"] + CYCLE128 = 7, + #[doc = "8: 7813 us"] + CYCLE256 = 8, + #[doc = "9: 15625 us"] + CYCLE512 = 9, + #[doc = "10: 31250 us"] + CYCLE1024 = 10, + #[doc = "11: 62500 us"] + CYCLE2048 = 11, + #[doc = "12: 125000 us"] + CYCLE4096 = 12, + #[doc = "13: 250000 us"] + CYCLE8192 = 13, + #[doc = "14: 500000 us"] + CYCLE16384 = 14, + #[doc = "15: 1000000 us"] + CYCLE32768 = 15, +} +impl From for u8 { + #[inline(always)] + fn from(variant: STARTUP_A) -> Self { + variant as _ + } +} +#[doc = "Field `STARTUP` reader - Start-Up Time"] +pub struct STARTUP_R(crate::FieldReader); +impl STARTUP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + STARTUP_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STARTUP_A { + match self.bits { + 0 => STARTUP_A::CYCLE1, + 1 => STARTUP_A::CYCLE2, + 2 => STARTUP_A::CYCLE4, + 3 => STARTUP_A::CYCLE8, + 4 => STARTUP_A::CYCLE16, + 5 => STARTUP_A::CYCLE32, + 6 => STARTUP_A::CYCLE64, + 7 => STARTUP_A::CYCLE128, + 8 => STARTUP_A::CYCLE256, + 9 => STARTUP_A::CYCLE512, + 10 => STARTUP_A::CYCLE1024, + 11 => STARTUP_A::CYCLE2048, + 12 => STARTUP_A::CYCLE4096, + 13 => STARTUP_A::CYCLE8192, + 14 => STARTUP_A::CYCLE16384, + 15 => STARTUP_A::CYCLE32768, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `CYCLE1`"] + #[inline(always)] + pub fn is_cycle1(&self) -> bool { + **self == STARTUP_A::CYCLE1 + } + #[doc = "Checks if the value of the field is `CYCLE2`"] + #[inline(always)] + pub fn is_cycle2(&self) -> bool { + **self == STARTUP_A::CYCLE2 + } + #[doc = "Checks if the value of the field is `CYCLE4`"] + #[inline(always)] + pub fn is_cycle4(&self) -> bool { + **self == STARTUP_A::CYCLE4 + } + #[doc = "Checks if the value of the field is `CYCLE8`"] + #[inline(always)] + pub fn is_cycle8(&self) -> bool { + **self == STARTUP_A::CYCLE8 + } + #[doc = "Checks if the value of the field is `CYCLE16`"] + #[inline(always)] + pub fn is_cycle16(&self) -> bool { + **self == STARTUP_A::CYCLE16 + } + #[doc = "Checks if the value of the field is `CYCLE32`"] + #[inline(always)] + pub fn is_cycle32(&self) -> bool { + **self == STARTUP_A::CYCLE32 + } + #[doc = "Checks if the value of the field is `CYCLE64`"] + #[inline(always)] + pub fn is_cycle64(&self) -> bool { + **self == STARTUP_A::CYCLE64 + } + #[doc = "Checks if the value of the field is `CYCLE128`"] + #[inline(always)] + pub fn is_cycle128(&self) -> bool { + **self == STARTUP_A::CYCLE128 + } + #[doc = "Checks if the value of the field is `CYCLE256`"] + #[inline(always)] + pub fn is_cycle256(&self) -> bool { + **self == STARTUP_A::CYCLE256 + } + #[doc = "Checks if the value of the field is `CYCLE512`"] + #[inline(always)] + pub fn is_cycle512(&self) -> bool { + **self == STARTUP_A::CYCLE512 + } + #[doc = "Checks if the value of the field is `CYCLE1024`"] + #[inline(always)] + pub fn is_cycle1024(&self) -> bool { + **self == STARTUP_A::CYCLE1024 + } + #[doc = "Checks if the value of the field is `CYCLE2048`"] + #[inline(always)] + pub fn is_cycle2048(&self) -> bool { + **self == STARTUP_A::CYCLE2048 + } + #[doc = "Checks if the value of the field is `CYCLE4096`"] + #[inline(always)] + pub fn is_cycle4096(&self) -> bool { + **self == STARTUP_A::CYCLE4096 + } + #[doc = "Checks if the value of the field is `CYCLE8192`"] + #[inline(always)] + pub fn is_cycle8192(&self) -> bool { + **self == STARTUP_A::CYCLE8192 + } + #[doc = "Checks if the value of the field is `CYCLE16384`"] + #[inline(always)] + pub fn is_cycle16384(&self) -> bool { + **self == STARTUP_A::CYCLE16384 + } + #[doc = "Checks if the value of the field is `CYCLE32768`"] + #[inline(always)] + pub fn is_cycle32768(&self) -> bool { + **self == STARTUP_A::CYCLE32768 + } +} +impl core::ops::Deref for STARTUP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STARTUP` writer - Start-Up Time"] +pub struct STARTUP_W<'a> { + w: &'a mut W, +} +impl<'a> STARTUP_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: STARTUP_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "31 us"] + #[inline(always)] + pub fn cycle1(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE1) + } + #[doc = "61 us"] + #[inline(always)] + pub fn cycle2(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE2) + } + #[doc = "122 us"] + #[inline(always)] + pub fn cycle4(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE4) + } + #[doc = "244 us"] + #[inline(always)] + pub fn cycle8(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE8) + } + #[doc = "488 us"] + #[inline(always)] + pub fn cycle16(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE16) + } + #[doc = "977 us"] + #[inline(always)] + pub fn cycle32(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE32) + } + #[doc = "1953 us"] + #[inline(always)] + pub fn cycle64(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE64) + } + #[doc = "3906 us"] + #[inline(always)] + pub fn cycle128(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE128) + } + #[doc = "7813 us"] + #[inline(always)] + pub fn cycle256(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE256) + } + #[doc = "15625 us"] + #[inline(always)] + pub fn cycle512(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE512) + } + #[doc = "31250 us"] + #[inline(always)] + pub fn cycle1024(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE1024) + } + #[doc = "62500 us"] + #[inline(always)] + pub fn cycle2048(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE2048) + } + #[doc = "125000 us"] + #[inline(always)] + pub fn cycle4096(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE4096) + } + #[doc = "250000 us"] + #[inline(always)] + pub fn cycle8192(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE8192) + } + #[doc = "500000 us"] + #[inline(always)] + pub fn cycle16384(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE16384) + } + #[doc = "1000000 us"] + #[inline(always)] + pub fn cycle32768(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE32768) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 12)) | ((value as u16 & 0x0f) << 12); + self.w + } +} +impl R { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Crystal Oscillator Enable"] + #[inline(always)] + pub fn xtalen(&self) -> XTALEN_R { + XTALEN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Xosc Clock Failure Detector Enable"] + #[inline(always)] + pub fn cfden(&self) -> CFDEN_R { + CFDEN_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Xosc Clock Switch Enable"] + #[inline(always)] + pub fn swben(&self) -> SWBEN_R { + SWBEN_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Oscillator Gain"] + #[inline(always)] + pub fn gain(&self) -> GAIN_R { + GAIN_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 11 - Automatic Amplitude Gain Control"] + #[inline(always)] + pub fn ampgc(&self) -> AMPGC_R { + AMPGC_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bits 12:15 - Start-Up Time"] + #[inline(always)] + pub fn startup(&self) -> STARTUP_R { + STARTUP_R::new(((self.bits >> 12) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - Crystal Oscillator Enable"] + #[inline(always)] + pub fn xtalen(&mut self) -> XTALEN_W { + XTALEN_W { w: self } + } + #[doc = "Bit 3 - Xosc Clock Failure Detector Enable"] + #[inline(always)] + pub fn cfden(&mut self) -> CFDEN_W { + CFDEN_W { w: self } + } + #[doc = "Bit 4 - Xosc Clock Switch Enable"] + #[inline(always)] + pub fn swben(&mut self) -> SWBEN_W { + SWBEN_W { w: self } + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Bits 8:10 - Oscillator Gain"] + #[inline(always)] + pub fn gain(&mut self) -> GAIN_W { + GAIN_W { w: self } + } + #[doc = "Bit 11 - Automatic Amplitude Gain Control"] + #[inline(always)] + pub fn ampgc(&mut self) -> AMPGC_W { + AMPGC_W { w: self } + } + #[doc = "Bits 12:15 - Start-Up Time"] + #[inline(always)] + pub fn startup(&mut self) -> STARTUP_W { + STARTUP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "External Multipurpose Crystal Oscillator (XOSC) Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [xoscctrl](index.html) module"] +pub struct XOSCCTRL_SPEC; +impl crate::RegisterSpec for XOSCCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [xoscctrl::R](R) reader structure"] +impl crate::Readable for XOSCCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [xoscctrl::W](W) writer structure"] +impl crate::Writable for XOSCCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets XOSCCTRL to value 0x80"] +impl crate::Resettable for XOSCCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x80 + } +} diff --git a/pac/atsamc21e/src/pac.rs b/pac/atsamc21e/src/pac.rs new file mode 100644 index 000000000000..3e365e081945 --- /dev/null +++ b/pac/atsamc21e/src/pac.rs @@ -0,0 +1,73 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Write control"] + pub wrctrl: crate::Reg, + #[doc = "0x04 - Event control"] + pub evctrl: crate::Reg, + _reserved2: [u8; 0x03], + #[doc = "0x08 - Interrupt enable clear"] + pub intenclr: crate::Reg, + #[doc = "0x09 - Interrupt enable set"] + pub intenset: crate::Reg, + _reserved4: [u8; 0x06], + #[doc = "0x10 - Bridge interrupt flag status"] + pub intflagahb: crate::Reg, + #[doc = "0x14 - Peripheral interrupt flag status - Bridge A"] + pub intflaga: crate::Reg, + #[doc = "0x18 - Peripheral interrupt flag status - Bridge B"] + pub intflagb: crate::Reg, + #[doc = "0x1c - Peripheral interrupt flag status - Bridge C"] + pub intflagc: crate::Reg, + _reserved8: [u8; 0x14], + #[doc = "0x34 - Peripheral write protection status - Bridge A"] + pub statusa: crate::Reg, + #[doc = "0x38 - Peripheral write protection status - Bridge B"] + pub statusb: crate::Reg, + #[doc = "0x3c - Peripheral write protection status - Bridge C"] + pub statusc: crate::Reg, +} +#[doc = "WRCTRL register accessor: an alias for `Reg`"] +pub type WRCTRL = crate::Reg; +#[doc = "Write control"] +pub mod wrctrl; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt enable clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt enable set"] +pub mod intenset; +#[doc = "INTFLAGAHB register accessor: an alias for `Reg`"] +pub type INTFLAGAHB = crate::Reg; +#[doc = "Bridge interrupt flag status"] +pub mod intflagahb; +#[doc = "INTFLAGA register accessor: an alias for `Reg`"] +pub type INTFLAGA = crate::Reg; +#[doc = "Peripheral interrupt flag status - Bridge A"] +pub mod intflaga; +#[doc = "INTFLAGB register accessor: an alias for `Reg`"] +pub type INTFLAGB = crate::Reg; +#[doc = "Peripheral interrupt flag status - Bridge B"] +pub mod intflagb; +#[doc = "INTFLAGC register accessor: an alias for `Reg`"] +pub type INTFLAGC = crate::Reg; +#[doc = "Peripheral interrupt flag status - Bridge C"] +pub mod intflagc; +#[doc = "STATUSA register accessor: an alias for `Reg`"] +pub type STATUSA = crate::Reg; +#[doc = "Peripheral write protection status - Bridge A"] +pub mod statusa; +#[doc = "STATUSB register accessor: an alias for `Reg`"] +pub type STATUSB = crate::Reg; +#[doc = "Peripheral write protection status - Bridge B"] +pub mod statusb; +#[doc = "STATUSC register accessor: an alias for `Reg`"] +pub type STATUSC = crate::Reg; +#[doc = "Peripheral write protection status - Bridge C"] +pub mod statusc; diff --git a/pac/atsamc21e/src/pac/evctrl.rs b/pac/atsamc21e/src/pac/evctrl.rs new file mode 100644 index 000000000000..630581b98c85 --- /dev/null +++ b/pac/atsamc21e/src/pac/evctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ERREO` reader - Peripheral acess error event output"] +pub struct ERREO_R(crate::FieldReader); +impl ERREO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERREO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERREO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERREO` writer - Peripheral acess error event output"] +pub struct ERREO_W<'a> { + w: &'a mut W, +} +impl<'a> ERREO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Peripheral acess error event output"] + #[inline(always)] + pub fn erreo(&self) -> ERREO_R { + ERREO_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Peripheral acess error event output"] + #[inline(always)] + pub fn erreo(&mut self) -> ERREO_W { + ERREO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/pac/intenclr.rs b/pac/atsamc21e/src/pac/intenclr.rs new file mode 100644 index 000000000000..609fe0fcf628 --- /dev/null +++ b/pac/atsamc21e/src/pac/intenclr.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ERR` reader - Peripheral access error interrupt disable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - Peripheral access error interrupt disable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Peripheral access error interrupt disable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Peripheral access error interrupt disable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt enable clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/pac/intenset.rs b/pac/atsamc21e/src/pac/intenset.rs new file mode 100644 index 000000000000..390545b588de --- /dev/null +++ b/pac/atsamc21e/src/pac/intenset.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ERR` reader - Peripheral access error interrupt enable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - Peripheral access error interrupt enable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Peripheral access error interrupt enable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Peripheral access error interrupt enable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt enable set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/pac/intflaga.rs b/pac/atsamc21e/src/pac/intflaga.rs new file mode 100644 index 000000000000..a1603451ad72 --- /dev/null +++ b/pac/atsamc21e/src/pac/intflaga.rs @@ -0,0 +1,677 @@ +#[doc = "Register `INTFLAGA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAGA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PAC_` reader - PAC"] +pub struct PAC__R(crate::FieldReader); +impl PAC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PAC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PAC_` writer - PAC"] +pub struct PAC__W<'a> { + w: &'a mut W, +} +impl<'a> PAC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `PM_` reader - PM"] +pub struct PM__R(crate::FieldReader); +impl PM__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PM__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PM__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PM_` writer - PM"] +pub struct PM__W<'a> { + w: &'a mut W, +} +impl<'a> PM__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MCLK_` reader - MCLK"] +pub struct MCLK__R(crate::FieldReader); +impl MCLK__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCLK__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCLK__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCLK_` writer - MCLK"] +pub struct MCLK__W<'a> { + w: &'a mut W, +} +impl<'a> MCLK__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RSTC_` reader - RSTC"] +pub struct RSTC__R(crate::FieldReader); +impl RSTC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RSTC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RSTC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RSTC_` writer - RSTC"] +pub struct RSTC__W<'a> { + w: &'a mut W, +} +impl<'a> RSTC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `OSCCTRL_` reader - OSCCTRL"] +pub struct OSCCTRL__R(crate::FieldReader); +impl OSCCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSCCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSCCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSCCTRL_` writer - OSCCTRL"] +pub struct OSCCTRL__W<'a> { + w: &'a mut W, +} +impl<'a> OSCCTRL__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `OSC32KCTRL_` reader - OSC32KCTRL"] +pub struct OSC32KCTRL__R(crate::FieldReader); +impl OSC32KCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC32KCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC32KCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC32KCTRL_` writer - OSC32KCTRL"] +pub struct OSC32KCTRL__W<'a> { + w: &'a mut W, +} +impl<'a> OSC32KCTRL__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `SUPC_` reader - SUPC"] +pub struct SUPC__R(crate::FieldReader); +impl SUPC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SUPC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SUPC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SUPC_` writer - SUPC"] +pub struct SUPC__W<'a> { + w: &'a mut W, +} +impl<'a> SUPC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `GCLK_` reader - GCLK"] +pub struct GCLK__R(crate::FieldReader); +impl GCLK__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GCLK__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GCLK__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GCLK_` writer - GCLK"] +pub struct GCLK__W<'a> { + w: &'a mut W, +} +impl<'a> GCLK__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `WDT_` reader - WDT"] +pub struct WDT__R(crate::FieldReader); +impl WDT__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WDT__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WDT__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WDT_` writer - WDT"] +pub struct WDT__W<'a> { + w: &'a mut W, +} +impl<'a> WDT__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `RTC_` reader - RTC"] +pub struct RTC__R(crate::FieldReader); +impl RTC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RTC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RTC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RTC_` writer - RTC"] +pub struct RTC__W<'a> { + w: &'a mut W, +} +impl<'a> RTC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `EIC_` reader - EIC"] +pub struct EIC__R(crate::FieldReader); +impl EIC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EIC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EIC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EIC_` writer - EIC"] +pub struct EIC__W<'a> { + w: &'a mut W, +} +impl<'a> EIC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `FREQM_` reader - FREQM"] +pub struct FREQM__R(crate::FieldReader); +impl FREQM__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FREQM__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FREQM__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FREQM_` writer - FREQM"] +pub struct FREQM__W<'a> { + w: &'a mut W, +} +impl<'a> FREQM__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `TSENS_` reader - TSENS"] +pub struct TSENS__R(crate::FieldReader); +impl TSENS__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSENS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSENS__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSENS_` writer - TSENS"] +pub struct TSENS__W<'a> { + w: &'a mut W, +} +impl<'a> TSENS__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +impl R { + #[doc = "Bit 0 - PAC"] + #[inline(always)] + pub fn pac_(&self) -> PAC__R { + PAC__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - PM"] + #[inline(always)] + pub fn pm_(&self) -> PM__R { + PM__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - MCLK"] + #[inline(always)] + pub fn mclk_(&self) -> MCLK__R { + MCLK__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - RSTC"] + #[inline(always)] + pub fn rstc_(&self) -> RSTC__R { + RSTC__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - OSCCTRL"] + #[inline(always)] + pub fn oscctrl_(&self) -> OSCCTRL__R { + OSCCTRL__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - OSC32KCTRL"] + #[inline(always)] + pub fn osc32kctrl_(&self) -> OSC32KCTRL__R { + OSC32KCTRL__R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - SUPC"] + #[inline(always)] + pub fn supc_(&self) -> SUPC__R { + SUPC__R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - GCLK"] + #[inline(always)] + pub fn gclk_(&self) -> GCLK__R { + GCLK__R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - WDT"] + #[inline(always)] + pub fn wdt_(&self) -> WDT__R { + WDT__R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - RTC"] + #[inline(always)] + pub fn rtc_(&self) -> RTC__R { + RTC__R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - EIC"] + #[inline(always)] + pub fn eic_(&self) -> EIC__R { + EIC__R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - FREQM"] + #[inline(always)] + pub fn freqm_(&self) -> FREQM__R { + FREQM__R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - TSENS"] + #[inline(always)] + pub fn tsens_(&self) -> TSENS__R { + TSENS__R::new(((self.bits >> 12) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - PAC"] + #[inline(always)] + pub fn pac_(&mut self) -> PAC__W { + PAC__W { w: self } + } + #[doc = "Bit 1 - PM"] + #[inline(always)] + pub fn pm_(&mut self) -> PM__W { + PM__W { w: self } + } + #[doc = "Bit 2 - MCLK"] + #[inline(always)] + pub fn mclk_(&mut self) -> MCLK__W { + MCLK__W { w: self } + } + #[doc = "Bit 3 - RSTC"] + #[inline(always)] + pub fn rstc_(&mut self) -> RSTC__W { + RSTC__W { w: self } + } + #[doc = "Bit 4 - OSCCTRL"] + #[inline(always)] + pub fn oscctrl_(&mut self) -> OSCCTRL__W { + OSCCTRL__W { w: self } + } + #[doc = "Bit 5 - OSC32KCTRL"] + #[inline(always)] + pub fn osc32kctrl_(&mut self) -> OSC32KCTRL__W { + OSC32KCTRL__W { w: self } + } + #[doc = "Bit 6 - SUPC"] + #[inline(always)] + pub fn supc_(&mut self) -> SUPC__W { + SUPC__W { w: self } + } + #[doc = "Bit 7 - GCLK"] + #[inline(always)] + pub fn gclk_(&mut self) -> GCLK__W { + GCLK__W { w: self } + } + #[doc = "Bit 8 - WDT"] + #[inline(always)] + pub fn wdt_(&mut self) -> WDT__W { + WDT__W { w: self } + } + #[doc = "Bit 9 - RTC"] + #[inline(always)] + pub fn rtc_(&mut self) -> RTC__W { + RTC__W { w: self } + } + #[doc = "Bit 10 - EIC"] + #[inline(always)] + pub fn eic_(&mut self) -> EIC__W { + EIC__W { w: self } + } + #[doc = "Bit 11 - FREQM"] + #[inline(always)] + pub fn freqm_(&mut self) -> FREQM__W { + FREQM__W { w: self } + } + #[doc = "Bit 12 - TSENS"] + #[inline(always)] + pub fn tsens_(&mut self) -> TSENS__W { + TSENS__W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Peripheral interrupt flag status - Bridge A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflaga](index.html) module"] +pub struct INTFLAGA_SPEC; +impl crate::RegisterSpec for INTFLAGA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflaga::R](R) reader structure"] +impl crate::Readable for INTFLAGA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflaga::W](W) writer structure"] +impl crate::Writable for INTFLAGA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAGA to value 0"] +impl crate::Resettable for INTFLAGA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/pac/intflagahb.rs b/pac/atsamc21e/src/pac/intflagahb.rs new file mode 100644 index 000000000000..4b7f7377e25e --- /dev/null +++ b/pac/atsamc21e/src/pac/intflagahb.rs @@ -0,0 +1,442 @@ +#[doc = "Register `INTFLAGAHB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAGAHB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FLASH_` reader - FLASH"] +pub struct FLASH__R(crate::FieldReader); +impl FLASH__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FLASH__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FLASH__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLASH_` writer - FLASH"] +pub struct FLASH__W<'a> { + w: &'a mut W, +} +impl<'a> FLASH__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `HSRAMCM0P_` reader - HSRAMCM0P"] +pub struct HSRAMCM0P__R(crate::FieldReader); +impl HSRAMCM0P__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HSRAMCM0P__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HSRAMCM0P__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HSRAMCM0P_` writer - HSRAMCM0P"] +pub struct HSRAMCM0P__W<'a> { + w: &'a mut W, +} +impl<'a> HSRAMCM0P__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `HSRAMDSU_` reader - HSRAMDSU"] +pub struct HSRAMDSU__R(crate::FieldReader); +impl HSRAMDSU__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HSRAMDSU__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HSRAMDSU__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HSRAMDSU_` writer - HSRAMDSU"] +pub struct HSRAMDSU__W<'a> { + w: &'a mut W, +} +impl<'a> HSRAMDSU__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `HPB1_` reader - HPB1"] +pub struct HPB1__R(crate::FieldReader); +impl HPB1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HPB1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HPB1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HPB1_` writer - HPB1"] +pub struct HPB1__W<'a> { + w: &'a mut W, +} +impl<'a> HPB1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `HPB0_` reader - HPB0"] +pub struct HPB0__R(crate::FieldReader); +impl HPB0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HPB0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HPB0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HPB0_` writer - HPB0"] +pub struct HPB0__W<'a> { + w: &'a mut W, +} +impl<'a> HPB0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `HPB2_` reader - HPB2"] +pub struct HPB2__R(crate::FieldReader); +impl HPB2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HPB2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HPB2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HPB2_` writer - HPB2"] +pub struct HPB2__W<'a> { + w: &'a mut W, +} +impl<'a> HPB2__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `LPRAMDMAC_` reader - LPRAMDMAC"] +pub struct LPRAMDMAC__R(crate::FieldReader); +impl LPRAMDMAC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LPRAMDMAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LPRAMDMAC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LPRAMDMAC_` writer - LPRAMDMAC"] +pub struct LPRAMDMAC__W<'a> { + w: &'a mut W, +} +impl<'a> LPRAMDMAC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `DIVAS_` reader - DIVAS"] +pub struct DIVAS__R(crate::FieldReader); +impl DIVAS__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIVAS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIVAS__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIVAS_` writer - DIVAS"] +pub struct DIVAS__W<'a> { + w: &'a mut W, +} +impl<'a> DIVAS__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - FLASH"] + #[inline(always)] + pub fn flash_(&self) -> FLASH__R { + FLASH__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - HSRAMCM0P"] + #[inline(always)] + pub fn hsramcm0p_(&self) -> HSRAMCM0P__R { + HSRAMCM0P__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - HSRAMDSU"] + #[inline(always)] + pub fn hsramdsu_(&self) -> HSRAMDSU__R { + HSRAMDSU__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - HPB1"] + #[inline(always)] + pub fn hpb1_(&self) -> HPB1__R { + HPB1__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - HPB0"] + #[inline(always)] + pub fn hpb0_(&self) -> HPB0__R { + HPB0__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - HPB2"] + #[inline(always)] + pub fn hpb2_(&self) -> HPB2__R { + HPB2__R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - LPRAMDMAC"] + #[inline(always)] + pub fn lpramdmac_(&self) -> LPRAMDMAC__R { + LPRAMDMAC__R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - DIVAS"] + #[inline(always)] + pub fn divas_(&self) -> DIVAS__R { + DIVAS__R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - FLASH"] + #[inline(always)] + pub fn flash_(&mut self) -> FLASH__W { + FLASH__W { w: self } + } + #[doc = "Bit 1 - HSRAMCM0P"] + #[inline(always)] + pub fn hsramcm0p_(&mut self) -> HSRAMCM0P__W { + HSRAMCM0P__W { w: self } + } + #[doc = "Bit 2 - HSRAMDSU"] + #[inline(always)] + pub fn hsramdsu_(&mut self) -> HSRAMDSU__W { + HSRAMDSU__W { w: self } + } + #[doc = "Bit 3 - HPB1"] + #[inline(always)] + pub fn hpb1_(&mut self) -> HPB1__W { + HPB1__W { w: self } + } + #[doc = "Bit 4 - HPB0"] + #[inline(always)] + pub fn hpb0_(&mut self) -> HPB0__W { + HPB0__W { w: self } + } + #[doc = "Bit 5 - HPB2"] + #[inline(always)] + pub fn hpb2_(&mut self) -> HPB2__W { + HPB2__W { w: self } + } + #[doc = "Bit 6 - LPRAMDMAC"] + #[inline(always)] + pub fn lpramdmac_(&mut self) -> LPRAMDMAC__W { + LPRAMDMAC__W { w: self } + } + #[doc = "Bit 7 - DIVAS"] + #[inline(always)] + pub fn divas_(&mut self) -> DIVAS__W { + DIVAS__W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Bridge interrupt flag status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflagahb](index.html) module"] +pub struct INTFLAGAHB_SPEC; +impl crate::RegisterSpec for INTFLAGAHB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflagahb::R](R) reader structure"] +impl crate::Readable for INTFLAGAHB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflagahb::W](W) writer structure"] +impl crate::Writable for INTFLAGAHB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAGAHB to value 0"] +impl crate::Resettable for INTFLAGAHB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/pac/intflagb.rs b/pac/atsamc21e/src/pac/intflagb.rs new file mode 100644 index 000000000000..8359f7e11f30 --- /dev/null +++ b/pac/atsamc21e/src/pac/intflagb.rs @@ -0,0 +1,348 @@ +#[doc = "Register `INTFLAGB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAGB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PORT_` reader - PORT"] +pub struct PORT__R(crate::FieldReader); +impl PORT__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PORT__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PORT__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PORT_` writer - PORT"] +pub struct PORT__W<'a> { + w: &'a mut W, +} +impl<'a> PORT__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `DSU_` reader - DSU"] +pub struct DSU__R(crate::FieldReader); +impl DSU__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DSU__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DSU__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DSU_` writer - DSU"] +pub struct DSU__W<'a> { + w: &'a mut W, +} +impl<'a> DSU__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `NVMCTRL_` reader - NVMCTRL"] +pub struct NVMCTRL__R(crate::FieldReader); +impl NVMCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NVMCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NVMCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NVMCTRL_` writer - NVMCTRL"] +pub struct NVMCTRL__W<'a> { + w: &'a mut W, +} +impl<'a> NVMCTRL__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `DMAC_` reader - DMAC"] +pub struct DMAC__R(crate::FieldReader); +impl DMAC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DMAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DMAC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DMAC_` writer - DMAC"] +pub struct DMAC__W<'a> { + w: &'a mut W, +} +impl<'a> DMAC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `MTB_` reader - MTB"] +pub struct MTB__R(crate::FieldReader); +impl MTB__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MTB__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MTB__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MTB_` writer - MTB"] +pub struct MTB__W<'a> { + w: &'a mut W, +} +impl<'a> MTB__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `HMATRIXHS_` reader - HMATRIXHS"] +pub struct HMATRIXHS__R(crate::FieldReader); +impl HMATRIXHS__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HMATRIXHS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HMATRIXHS__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HMATRIXHS_` writer - HMATRIXHS"] +pub struct HMATRIXHS__W<'a> { + w: &'a mut W, +} +impl<'a> HMATRIXHS__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - PORT"] + #[inline(always)] + pub fn port_(&self) -> PORT__R { + PORT__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - DSU"] + #[inline(always)] + pub fn dsu_(&self) -> DSU__R { + DSU__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - NVMCTRL"] + #[inline(always)] + pub fn nvmctrl_(&self) -> NVMCTRL__R { + NVMCTRL__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - DMAC"] + #[inline(always)] + pub fn dmac_(&self) -> DMAC__R { + DMAC__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - MTB"] + #[inline(always)] + pub fn mtb_(&self) -> MTB__R { + MTB__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - HMATRIXHS"] + #[inline(always)] + pub fn hmatrixhs_(&self) -> HMATRIXHS__R { + HMATRIXHS__R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - PORT"] + #[inline(always)] + pub fn port_(&mut self) -> PORT__W { + PORT__W { w: self } + } + #[doc = "Bit 1 - DSU"] + #[inline(always)] + pub fn dsu_(&mut self) -> DSU__W { + DSU__W { w: self } + } + #[doc = "Bit 2 - NVMCTRL"] + #[inline(always)] + pub fn nvmctrl_(&mut self) -> NVMCTRL__W { + NVMCTRL__W { w: self } + } + #[doc = "Bit 3 - DMAC"] + #[inline(always)] + pub fn dmac_(&mut self) -> DMAC__W { + DMAC__W { w: self } + } + #[doc = "Bit 4 - MTB"] + #[inline(always)] + pub fn mtb_(&mut self) -> MTB__W { + MTB__W { w: self } + } + #[doc = "Bit 5 - HMATRIXHS"] + #[inline(always)] + pub fn hmatrixhs_(&mut self) -> HMATRIXHS__W { + HMATRIXHS__W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Peripheral interrupt flag status - Bridge B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflagb](index.html) module"] +pub struct INTFLAGB_SPEC; +impl crate::RegisterSpec for INTFLAGB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflagb::R](R) reader structure"] +impl crate::Readable for INTFLAGB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflagb::W](W) writer structure"] +impl crate::Writable for INTFLAGB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAGB to value 0"] +impl crate::Resettable for INTFLAGB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/pac/intflagc.rs b/pac/atsamc21e/src/pac/intflagc.rs new file mode 100644 index 000000000000..e6ac8c460c92 --- /dev/null +++ b/pac/atsamc21e/src/pac/intflagc.rs @@ -0,0 +1,1053 @@ +#[doc = "Register `INTFLAGC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAGC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVSYS_` reader - EVSYS"] +pub struct EVSYS__R(crate::FieldReader); +impl EVSYS__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVSYS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVSYS__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVSYS_` writer - EVSYS"] +pub struct EVSYS__W<'a> { + w: &'a mut W, +} +impl<'a> EVSYS__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `SERCOM0_` reader - SERCOM0"] +pub struct SERCOM0__R(crate::FieldReader); +impl SERCOM0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM0_` writer - SERCOM0"] +pub struct SERCOM0__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SERCOM1_` reader - SERCOM1"] +pub struct SERCOM1__R(crate::FieldReader); +impl SERCOM1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM1_` writer - SERCOM1"] +pub struct SERCOM1__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SERCOM2_` reader - SERCOM2"] +pub struct SERCOM2__R(crate::FieldReader); +impl SERCOM2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM2_` writer - SERCOM2"] +pub struct SERCOM2__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM2__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `SERCOM3_` reader - SERCOM3"] +pub struct SERCOM3__R(crate::FieldReader); +impl SERCOM3__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM3__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM3__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM3_` writer - SERCOM3"] +pub struct SERCOM3__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM3__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `CAN0_` reader - CAN0"] +pub struct CAN0__R(crate::FieldReader); +impl CAN0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CAN0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CAN0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAN0_` writer - CAN0"] +pub struct CAN0__W<'a> { + w: &'a mut W, +} +impl<'a> CAN0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `TCC0_` reader - TCC0"] +pub struct TCC0__R(crate::FieldReader); +impl TCC0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCC0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCC0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCC0_` writer - TCC0"] +pub struct TCC0__W<'a> { + w: &'a mut W, +} +impl<'a> TCC0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `TCC1_` reader - TCC1"] +pub struct TCC1__R(crate::FieldReader); +impl TCC1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCC1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCC1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCC1_` writer - TCC1"] +pub struct TCC1__W<'a> { + w: &'a mut W, +} +impl<'a> TCC1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `TCC2_` reader - TCC2"] +pub struct TCC2__R(crate::FieldReader); +impl TCC2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCC2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCC2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCC2_` writer - TCC2"] +pub struct TCC2__W<'a> { + w: &'a mut W, +} +impl<'a> TCC2__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `TC0_` reader - TC0"] +pub struct TC0__R(crate::FieldReader); +impl TC0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC0_` writer - TC0"] +pub struct TC0__W<'a> { + w: &'a mut W, +} +impl<'a> TC0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `TC1_` reader - TC1"] +pub struct TC1__R(crate::FieldReader); +impl TC1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC1_` writer - TC1"] +pub struct TC1__W<'a> { + w: &'a mut W, +} +impl<'a> TC1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `TC2_` reader - TC2"] +pub struct TC2__R(crate::FieldReader); +impl TC2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC2_` writer - TC2"] +pub struct TC2__W<'a> { + w: &'a mut W, +} +impl<'a> TC2__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `TC3_` reader - TC3"] +pub struct TC3__R(crate::FieldReader); +impl TC3__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC3__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC3__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC3_` writer - TC3"] +pub struct TC3__W<'a> { + w: &'a mut W, +} +impl<'a> TC3__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `TC4_` reader - TC4"] +pub struct TC4__R(crate::FieldReader); +impl TC4__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC4__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC4__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC4_` writer - TC4"] +pub struct TC4__W<'a> { + w: &'a mut W, +} +impl<'a> TC4__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `ADC0_` reader - ADC0"] +pub struct ADC0__R(crate::FieldReader); +impl ADC0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ADC0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADC0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADC0_` writer - ADC0"] +pub struct ADC0__W<'a> { + w: &'a mut W, +} +impl<'a> ADC0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `ADC1_` reader - ADC1"] +pub struct ADC1__R(crate::FieldReader); +impl ADC1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ADC1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADC1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADC1_` writer - ADC1"] +pub struct ADC1__W<'a> { + w: &'a mut W, +} +impl<'a> ADC1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `SDADC_` reader - SDADC"] +pub struct SDADC__R(crate::FieldReader); +impl SDADC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SDADC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SDADC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SDADC_` writer - SDADC"] +pub struct SDADC__W<'a> { + w: &'a mut W, +} +impl<'a> SDADC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `AC_` reader - AC"] +pub struct AC__R(crate::FieldReader); +impl AC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AC_` writer - AC"] +pub struct AC__W<'a> { + w: &'a mut W, +} +impl<'a> AC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `DAC_` reader - DAC"] +pub struct DAC__R(crate::FieldReader); +impl DAC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DAC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DAC_` writer - DAC"] +pub struct DAC__W<'a> { + w: &'a mut W, +} +impl<'a> DAC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `PTC_` reader - PTC"] +pub struct PTC__R(crate::FieldReader); +impl PTC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PTC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PTC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PTC_` writer - PTC"] +pub struct PTC__W<'a> { + w: &'a mut W, +} +impl<'a> PTC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `CCL_` reader - CCL"] +pub struct CCL__R(crate::FieldReader); +impl CCL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCL_` writer - CCL"] +pub struct CCL__W<'a> { + w: &'a mut W, +} +impl<'a> CCL__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +impl R { + #[doc = "Bit 0 - EVSYS"] + #[inline(always)] + pub fn evsys_(&self) -> EVSYS__R { + EVSYS__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM0"] + #[inline(always)] + pub fn sercom0_(&self) -> SERCOM0__R { + SERCOM0__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - SERCOM1"] + #[inline(always)] + pub fn sercom1_(&self) -> SERCOM1__R { + SERCOM1__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - SERCOM2"] + #[inline(always)] + pub fn sercom2_(&self) -> SERCOM2__R { + SERCOM2__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - SERCOM3"] + #[inline(always)] + pub fn sercom3_(&self) -> SERCOM3__R { + SERCOM3__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 7 - CAN0"] + #[inline(always)] + pub fn can0_(&self) -> CAN0__R { + CAN0__R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 9 - TCC0"] + #[inline(always)] + pub fn tcc0_(&self) -> TCC0__R { + TCC0__R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - TCC1"] + #[inline(always)] + pub fn tcc1_(&self) -> TCC1__R { + TCC1__R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - TCC2"] + #[inline(always)] + pub fn tcc2_(&self) -> TCC2__R { + TCC2__R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - TC0"] + #[inline(always)] + pub fn tc0_(&self) -> TC0__R { + TC0__R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - TC1"] + #[inline(always)] + pub fn tc1_(&self) -> TC1__R { + TC1__R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - TC2"] + #[inline(always)] + pub fn tc2_(&self) -> TC2__R { + TC2__R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - TC3"] + #[inline(always)] + pub fn tc3_(&self) -> TC3__R { + TC3__R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - TC4"] + #[inline(always)] + pub fn tc4_(&self) -> TC4__R { + TC4__R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - ADC0"] + #[inline(always)] + pub fn adc0_(&self) -> ADC0__R { + ADC0__R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - ADC1"] + #[inline(always)] + pub fn adc1_(&self) -> ADC1__R { + ADC1__R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - SDADC"] + #[inline(always)] + pub fn sdadc_(&self) -> SDADC__R { + SDADC__R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - AC"] + #[inline(always)] + pub fn ac_(&self) -> AC__R { + AC__R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - DAC"] + #[inline(always)] + pub fn dac_(&self) -> DAC__R { + DAC__R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - PTC"] + #[inline(always)] + pub fn ptc_(&self) -> PTC__R { + PTC__R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - CCL"] + #[inline(always)] + pub fn ccl_(&self) -> CCL__R { + CCL__R::new(((self.bits >> 23) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - EVSYS"] + #[inline(always)] + pub fn evsys_(&mut self) -> EVSYS__W { + EVSYS__W { w: self } + } + #[doc = "Bit 1 - SERCOM0"] + #[inline(always)] + pub fn sercom0_(&mut self) -> SERCOM0__W { + SERCOM0__W { w: self } + } + #[doc = "Bit 2 - SERCOM1"] + #[inline(always)] + pub fn sercom1_(&mut self) -> SERCOM1__W { + SERCOM1__W { w: self } + } + #[doc = "Bit 3 - SERCOM2"] + #[inline(always)] + pub fn sercom2_(&mut self) -> SERCOM2__W { + SERCOM2__W { w: self } + } + #[doc = "Bit 4 - SERCOM3"] + #[inline(always)] + pub fn sercom3_(&mut self) -> SERCOM3__W { + SERCOM3__W { w: self } + } + #[doc = "Bit 7 - CAN0"] + #[inline(always)] + pub fn can0_(&mut self) -> CAN0__W { + CAN0__W { w: self } + } + #[doc = "Bit 9 - TCC0"] + #[inline(always)] + pub fn tcc0_(&mut self) -> TCC0__W { + TCC0__W { w: self } + } + #[doc = "Bit 10 - TCC1"] + #[inline(always)] + pub fn tcc1_(&mut self) -> TCC1__W { + TCC1__W { w: self } + } + #[doc = "Bit 11 - TCC2"] + #[inline(always)] + pub fn tcc2_(&mut self) -> TCC2__W { + TCC2__W { w: self } + } + #[doc = "Bit 12 - TC0"] + #[inline(always)] + pub fn tc0_(&mut self) -> TC0__W { + TC0__W { w: self } + } + #[doc = "Bit 13 - TC1"] + #[inline(always)] + pub fn tc1_(&mut self) -> TC1__W { + TC1__W { w: self } + } + #[doc = "Bit 14 - TC2"] + #[inline(always)] + pub fn tc2_(&mut self) -> TC2__W { + TC2__W { w: self } + } + #[doc = "Bit 15 - TC3"] + #[inline(always)] + pub fn tc3_(&mut self) -> TC3__W { + TC3__W { w: self } + } + #[doc = "Bit 16 - TC4"] + #[inline(always)] + pub fn tc4_(&mut self) -> TC4__W { + TC4__W { w: self } + } + #[doc = "Bit 17 - ADC0"] + #[inline(always)] + pub fn adc0_(&mut self) -> ADC0__W { + ADC0__W { w: self } + } + #[doc = "Bit 18 - ADC1"] + #[inline(always)] + pub fn adc1_(&mut self) -> ADC1__W { + ADC1__W { w: self } + } + #[doc = "Bit 19 - SDADC"] + #[inline(always)] + pub fn sdadc_(&mut self) -> SDADC__W { + SDADC__W { w: self } + } + #[doc = "Bit 20 - AC"] + #[inline(always)] + pub fn ac_(&mut self) -> AC__W { + AC__W { w: self } + } + #[doc = "Bit 21 - DAC"] + #[inline(always)] + pub fn dac_(&mut self) -> DAC__W { + DAC__W { w: self } + } + #[doc = "Bit 22 - PTC"] + #[inline(always)] + pub fn ptc_(&mut self) -> PTC__W { + PTC__W { w: self } + } + #[doc = "Bit 23 - CCL"] + #[inline(always)] + pub fn ccl_(&mut self) -> CCL__W { + CCL__W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Peripheral interrupt flag status - Bridge C\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflagc](index.html) module"] +pub struct INTFLAGC_SPEC; +impl crate::RegisterSpec for INTFLAGC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflagc::R](R) reader structure"] +impl crate::Readable for INTFLAGC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflagc::W](W) writer structure"] +impl crate::Writable for INTFLAGC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAGC to value 0"] +impl crate::Resettable for INTFLAGC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/pac/statusa.rs b/pac/atsamc21e/src/pac/statusa.rs new file mode 100644 index 000000000000..ca22aef2f1ce --- /dev/null +++ b/pac/atsamc21e/src/pac/statusa.rs @@ -0,0 +1,293 @@ +#[doc = "Register `STATUSA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PAC_` reader - PAC APB Protect Enable"] +pub struct PAC__R(crate::FieldReader); +impl PAC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PAC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PM_` reader - PM APB Protect Enable"] +pub struct PM__R(crate::FieldReader); +impl PM__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PM__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PM__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCLK_` reader - MCLK APB Protect Enable"] +pub struct MCLK__R(crate::FieldReader); +impl MCLK__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCLK__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCLK__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RSTC_` reader - RSTC APB Protect Enable"] +pub struct RSTC__R(crate::FieldReader); +impl RSTC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RSTC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RSTC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSCCTRL_` reader - OSCCTRL APB Protect Enable"] +pub struct OSCCTRL__R(crate::FieldReader); +impl OSCCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSCCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSCCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC32KCTRL_` reader - OSC32KCTRL APB Protect Enable"] +pub struct OSC32KCTRL__R(crate::FieldReader); +impl OSC32KCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC32KCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC32KCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SUPC_` reader - SUPC APB Protect Enable"] +pub struct SUPC__R(crate::FieldReader); +impl SUPC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SUPC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SUPC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GCLK_` reader - GCLK APB Protect Enable"] +pub struct GCLK__R(crate::FieldReader); +impl GCLK__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GCLK__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GCLK__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WDT_` reader - WDT APB Protect Enable"] +pub struct WDT__R(crate::FieldReader); +impl WDT__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WDT__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WDT__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RTC_` reader - RTC APB Protect Enable"] +pub struct RTC__R(crate::FieldReader); +impl RTC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RTC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RTC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EIC_` reader - EIC APB Protect Enable"] +pub struct EIC__R(crate::FieldReader); +impl EIC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EIC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EIC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FREQM_` reader - FREQM APB Protect Enable"] +pub struct FREQM__R(crate::FieldReader); +impl FREQM__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FREQM__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FREQM__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSENS_` reader - TSENS APB Protect Enable"] +pub struct TSENS__R(crate::FieldReader); +impl TSENS__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSENS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSENS__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - PAC APB Protect Enable"] + #[inline(always)] + pub fn pac_(&self) -> PAC__R { + PAC__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - PM APB Protect Enable"] + #[inline(always)] + pub fn pm_(&self) -> PM__R { + PM__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - MCLK APB Protect Enable"] + #[inline(always)] + pub fn mclk_(&self) -> MCLK__R { + MCLK__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - RSTC APB Protect Enable"] + #[inline(always)] + pub fn rstc_(&self) -> RSTC__R { + RSTC__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - OSCCTRL APB Protect Enable"] + #[inline(always)] + pub fn oscctrl_(&self) -> OSCCTRL__R { + OSCCTRL__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - OSC32KCTRL APB Protect Enable"] + #[inline(always)] + pub fn osc32kctrl_(&self) -> OSC32KCTRL__R { + OSC32KCTRL__R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - SUPC APB Protect Enable"] + #[inline(always)] + pub fn supc_(&self) -> SUPC__R { + SUPC__R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - GCLK APB Protect Enable"] + #[inline(always)] + pub fn gclk_(&self) -> GCLK__R { + GCLK__R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - WDT APB Protect Enable"] + #[inline(always)] + pub fn wdt_(&self) -> WDT__R { + WDT__R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - RTC APB Protect Enable"] + #[inline(always)] + pub fn rtc_(&self) -> RTC__R { + RTC__R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - EIC APB Protect Enable"] + #[inline(always)] + pub fn eic_(&self) -> EIC__R { + EIC__R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - FREQM APB Protect Enable"] + #[inline(always)] + pub fn freqm_(&self) -> FREQM__R { + FREQM__R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - TSENS APB Protect Enable"] + #[inline(always)] + pub fn tsens_(&self) -> TSENS__R { + TSENS__R::new(((self.bits >> 12) & 0x01) != 0) + } +} +#[doc = "Peripheral write protection status - Bridge A\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [statusa](index.html) module"] +pub struct STATUSA_SPEC; +impl crate::RegisterSpec for STATUSA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [statusa::R](R) reader structure"] +impl crate::Readable for STATUSA_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUSA to value 0"] +impl crate::Resettable for STATUSA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/pac/statusb.rs b/pac/atsamc21e/src/pac/statusb.rs new file mode 100644 index 000000000000..a022cc2f1d54 --- /dev/null +++ b/pac/atsamc21e/src/pac/statusb.rs @@ -0,0 +1,153 @@ +#[doc = "Register `STATUSB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PORT_` reader - PORT APB Protect Enable"] +pub struct PORT__R(crate::FieldReader); +impl PORT__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PORT__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PORT__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DSU_` reader - DSU APB Protect Enable"] +pub struct DSU__R(crate::FieldReader); +impl DSU__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DSU__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DSU__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NVMCTRL_` reader - NVMCTRL APB Protect Enable"] +pub struct NVMCTRL__R(crate::FieldReader); +impl NVMCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NVMCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NVMCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DMAC_` reader - DMAC APB Protect Enable"] +pub struct DMAC__R(crate::FieldReader); +impl DMAC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DMAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DMAC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MTB_` reader - MTB APB Protect Enable"] +pub struct MTB__R(crate::FieldReader); +impl MTB__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MTB__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MTB__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HMATRIXHS_` reader - HMATRIXHS APB Protect Enable"] +pub struct HMATRIXHS__R(crate::FieldReader); +impl HMATRIXHS__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HMATRIXHS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HMATRIXHS__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - PORT APB Protect Enable"] + #[inline(always)] + pub fn port_(&self) -> PORT__R { + PORT__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - DSU APB Protect Enable"] + #[inline(always)] + pub fn dsu_(&self) -> DSU__R { + DSU__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - NVMCTRL APB Protect Enable"] + #[inline(always)] + pub fn nvmctrl_(&self) -> NVMCTRL__R { + NVMCTRL__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - DMAC APB Protect Enable"] + #[inline(always)] + pub fn dmac_(&self) -> DMAC__R { + DMAC__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - MTB APB Protect Enable"] + #[inline(always)] + pub fn mtb_(&self) -> MTB__R { + MTB__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - HMATRIXHS APB Protect Enable"] + #[inline(always)] + pub fn hmatrixhs_(&self) -> HMATRIXHS__R { + HMATRIXHS__R::new(((self.bits >> 5) & 0x01) != 0) + } +} +#[doc = "Peripheral write protection status - Bridge B\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [statusb](index.html) module"] +pub struct STATUSB_SPEC; +impl crate::RegisterSpec for STATUSB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [statusb::R](R) reader structure"] +impl crate::Readable for STATUSB_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUSB to value 0x02"] +impl crate::Resettable for STATUSB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x02 + } +} diff --git a/pac/atsamc21e/src/pac/statusc.rs b/pac/atsamc21e/src/pac/statusc.rs new file mode 100644 index 000000000000..ba2d91ba5c8e --- /dev/null +++ b/pac/atsamc21e/src/pac/statusc.rs @@ -0,0 +1,453 @@ +#[doc = "Register `STATUSC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `EVSYS_` reader - EVSYS APB Protect Enable"] +pub struct EVSYS__R(crate::FieldReader); +impl EVSYS__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVSYS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVSYS__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM0_` reader - SERCOM0 APB Protect Enable"] +pub struct SERCOM0__R(crate::FieldReader); +impl SERCOM0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM1_` reader - SERCOM1 APB Protect Enable"] +pub struct SERCOM1__R(crate::FieldReader); +impl SERCOM1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM2_` reader - SERCOM2 APB Protect Enable"] +pub struct SERCOM2__R(crate::FieldReader); +impl SERCOM2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM3_` reader - SERCOM3 APB Protect Enable"] +pub struct SERCOM3__R(crate::FieldReader); +impl SERCOM3__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM3__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM3__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAN0_` reader - CAN0 APB Protect Enable"] +pub struct CAN0__R(crate::FieldReader); +impl CAN0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CAN0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CAN0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCC0_` reader - TCC0 APB Protect Enable"] +pub struct TCC0__R(crate::FieldReader); +impl TCC0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCC0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCC0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCC1_` reader - TCC1 APB Protect Enable"] +pub struct TCC1__R(crate::FieldReader); +impl TCC1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCC1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCC1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCC2_` reader - TCC2 APB Protect Enable"] +pub struct TCC2__R(crate::FieldReader); +impl TCC2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCC2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCC2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC0_` reader - TC0 APB Protect Enable"] +pub struct TC0__R(crate::FieldReader); +impl TC0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC1_` reader - TC1 APB Protect Enable"] +pub struct TC1__R(crate::FieldReader); +impl TC1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC2_` reader - TC2 APB Protect Enable"] +pub struct TC2__R(crate::FieldReader); +impl TC2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC3_` reader - TC3 APB Protect Enable"] +pub struct TC3__R(crate::FieldReader); +impl TC3__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC3__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC3__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC4_` reader - TC4 APB Protect Enable"] +pub struct TC4__R(crate::FieldReader); +impl TC4__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC4__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC4__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADC0_` reader - ADC0 APB Protect Enable"] +pub struct ADC0__R(crate::FieldReader); +impl ADC0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ADC0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADC0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADC1_` reader - ADC1 APB Protect Enable"] +pub struct ADC1__R(crate::FieldReader); +impl ADC1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ADC1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADC1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SDADC_` reader - SDADC APB Protect Enable"] +pub struct SDADC__R(crate::FieldReader); +impl SDADC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SDADC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SDADC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AC_` reader - AC APB Protect Enable"] +pub struct AC__R(crate::FieldReader); +impl AC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DAC_` reader - DAC APB Protect Enable"] +pub struct DAC__R(crate::FieldReader); +impl DAC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DAC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PTC_` reader - PTC APB Protect Enable"] +pub struct PTC__R(crate::FieldReader); +impl PTC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PTC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PTC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCL_` reader - CCL APB Protect Enable"] +pub struct CCL__R(crate::FieldReader); +impl CCL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - EVSYS APB Protect Enable"] + #[inline(always)] + pub fn evsys_(&self) -> EVSYS__R { + EVSYS__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM0 APB Protect Enable"] + #[inline(always)] + pub fn sercom0_(&self) -> SERCOM0__R { + SERCOM0__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - SERCOM1 APB Protect Enable"] + #[inline(always)] + pub fn sercom1_(&self) -> SERCOM1__R { + SERCOM1__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - SERCOM2 APB Protect Enable"] + #[inline(always)] + pub fn sercom2_(&self) -> SERCOM2__R { + SERCOM2__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - SERCOM3 APB Protect Enable"] + #[inline(always)] + pub fn sercom3_(&self) -> SERCOM3__R { + SERCOM3__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 7 - CAN0 APB Protect Enable"] + #[inline(always)] + pub fn can0_(&self) -> CAN0__R { + CAN0__R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 9 - TCC0 APB Protect Enable"] + #[inline(always)] + pub fn tcc0_(&self) -> TCC0__R { + TCC0__R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - TCC1 APB Protect Enable"] + #[inline(always)] + pub fn tcc1_(&self) -> TCC1__R { + TCC1__R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - TCC2 APB Protect Enable"] + #[inline(always)] + pub fn tcc2_(&self) -> TCC2__R { + TCC2__R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - TC0 APB Protect Enable"] + #[inline(always)] + pub fn tc0_(&self) -> TC0__R { + TC0__R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - TC1 APB Protect Enable"] + #[inline(always)] + pub fn tc1_(&self) -> TC1__R { + TC1__R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - TC2 APB Protect Enable"] + #[inline(always)] + pub fn tc2_(&self) -> TC2__R { + TC2__R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - TC3 APB Protect Enable"] + #[inline(always)] + pub fn tc3_(&self) -> TC3__R { + TC3__R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - TC4 APB Protect Enable"] + #[inline(always)] + pub fn tc4_(&self) -> TC4__R { + TC4__R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - ADC0 APB Protect Enable"] + #[inline(always)] + pub fn adc0_(&self) -> ADC0__R { + ADC0__R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - ADC1 APB Protect Enable"] + #[inline(always)] + pub fn adc1_(&self) -> ADC1__R { + ADC1__R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - SDADC APB Protect Enable"] + #[inline(always)] + pub fn sdadc_(&self) -> SDADC__R { + SDADC__R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - AC APB Protect Enable"] + #[inline(always)] + pub fn ac_(&self) -> AC__R { + AC__R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - DAC APB Protect Enable"] + #[inline(always)] + pub fn dac_(&self) -> DAC__R { + DAC__R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - PTC APB Protect Enable"] + #[inline(always)] + pub fn ptc_(&self) -> PTC__R { + PTC__R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - CCL APB Protect Enable"] + #[inline(always)] + pub fn ccl_(&self) -> CCL__R { + CCL__R::new(((self.bits >> 23) & 0x01) != 0) + } +} +#[doc = "Peripheral write protection status - Bridge C\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [statusc](index.html) module"] +pub struct STATUSC_SPEC; +impl crate::RegisterSpec for STATUSC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [statusc::R](R) reader structure"] +impl crate::Readable for STATUSC_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUSC to value 0x0200_0000"] +impl crate::Resettable for STATUSC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0200_0000 + } +} diff --git a/pac/atsamc21e/src/pac/wrctrl.rs b/pac/atsamc21e/src/pac/wrctrl.rs new file mode 100644 index 000000000000..65773ea08d64 --- /dev/null +++ b/pac/atsamc21e/src/pac/wrctrl.rs @@ -0,0 +1,215 @@ +#[doc = "Register `WRCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WRCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PERID` reader - Peripheral identifier"] +pub struct PERID_R(crate::FieldReader); +impl PERID_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + PERID_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERID_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERID` writer - Peripheral identifier"] +pub struct PERID_W<'a> { + w: &'a mut W, +} +impl<'a> PERID_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +#[doc = "Peripheral access control key\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum KEY_A { + #[doc = "0: No action"] + OFF = 0, + #[doc = "1: Clear protection"] + CLR = 1, + #[doc = "2: Set protection"] + SET = 2, + #[doc = "3: Set and lock protection"] + SETLCK = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: KEY_A) -> Self { + variant as _ + } +} +#[doc = "Field `KEY` reader - Peripheral access control key"] +pub struct KEY_R(crate::FieldReader); +impl KEY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + KEY_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(KEY_A::OFF), + 1 => Some(KEY_A::CLR), + 2 => Some(KEY_A::SET), + 3 => Some(KEY_A::SETLCK), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == KEY_A::OFF + } + #[doc = "Checks if the value of the field is `CLR`"] + #[inline(always)] + pub fn is_clr(&self) -> bool { + **self == KEY_A::CLR + } + #[doc = "Checks if the value of the field is `SET`"] + #[inline(always)] + pub fn is_set(&self) -> bool { + **self == KEY_A::SET + } + #[doc = "Checks if the value of the field is `SETLCK`"] + #[inline(always)] + pub fn is_setlck(&self) -> bool { + **self == KEY_A::SETLCK + } +} +impl core::ops::Deref for KEY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `KEY` writer - Peripheral access control key"] +pub struct KEY_W<'a> { + w: &'a mut W, +} +impl<'a> KEY_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: KEY_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(KEY_A::OFF) + } + #[doc = "Clear protection"] + #[inline(always)] + pub fn clr(self) -> &'a mut W { + self.variant(KEY_A::CLR) + } + #[doc = "Set protection"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(KEY_A::SET) + } + #[doc = "Set and lock protection"] + #[inline(always)] + pub fn setlck(self) -> &'a mut W { + self.variant(KEY_A::SETLCK) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Peripheral identifier"] + #[inline(always)] + pub fn perid(&self) -> PERID_R { + PERID_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:23 - Peripheral access control key"] + #[inline(always)] + pub fn key(&self) -> KEY_R { + KEY_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:15 - Peripheral identifier"] + #[inline(always)] + pub fn perid(&mut self) -> PERID_W { + PERID_W { w: self } + } + #[doc = "Bits 16:23 - Peripheral access control key"] + #[inline(always)] + pub fn key(&mut self) -> KEY_W { + KEY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Write control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wrctrl](index.html) module"] +pub struct WRCTRL_SPEC; +impl crate::RegisterSpec for WRCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [wrctrl::R](R) reader structure"] +impl crate::Readable for WRCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wrctrl::W](W) writer structure"] +impl crate::Writable for WRCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WRCTRL to value 0"] +impl crate::Resettable for WRCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/pm.rs b/pac/atsamc21e/src/pm.rs new file mode 100644 index 000000000000..9da2b0e13288 --- /dev/null +++ b/pac/atsamc21e/src/pm.rs @@ -0,0 +1,18 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved0: [u8; 0x01], + #[doc = "0x01 - Sleep Configuration"] + pub sleepcfg: crate::Reg, + _reserved1: [u8; 0x06], + #[doc = "0x08 - Standby Configuration"] + pub stdbycfg: crate::Reg, +} +#[doc = "SLEEPCFG register accessor: an alias for `Reg`"] +pub type SLEEPCFG = crate::Reg; +#[doc = "Sleep Configuration"] +pub mod sleepcfg; +#[doc = "STDBYCFG register accessor: an alias for `Reg`"] +pub type STDBYCFG = crate::Reg; +#[doc = "Standby Configuration"] +pub mod stdbycfg; diff --git a/pac/atsamc21e/src/pm/sleepcfg.rs b/pac/atsamc21e/src/pm/sleepcfg.rs new file mode 100644 index 000000000000..ef643311a059 --- /dev/null +++ b/pac/atsamc21e/src/pm/sleepcfg.rs @@ -0,0 +1,178 @@ +#[doc = "Register `SLEEPCFG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SLEEPCFG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Sleep Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SLEEPMODE_A { + #[doc = "0: CPU clock is OFF"] + IDLE0 = 0, + #[doc = "1: AHB clock is OFF"] + IDLE1 = 1, + #[doc = "2: APB clock are OFF"] + IDLE2 = 2, + #[doc = "4: All Clocks are OFF"] + STANDBY = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SLEEPMODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `SLEEPMODE` reader - Sleep Mode"] +pub struct SLEEPMODE_R(crate::FieldReader); +impl SLEEPMODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SLEEPMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SLEEPMODE_A::IDLE0), + 1 => Some(SLEEPMODE_A::IDLE1), + 2 => Some(SLEEPMODE_A::IDLE2), + 4 => Some(SLEEPMODE_A::STANDBY), + _ => None, + } + } + #[doc = "Checks if the value of the field is `IDLE0`"] + #[inline(always)] + pub fn is_idle0(&self) -> bool { + **self == SLEEPMODE_A::IDLE0 + } + #[doc = "Checks if the value of the field is `IDLE1`"] + #[inline(always)] + pub fn is_idle1(&self) -> bool { + **self == SLEEPMODE_A::IDLE1 + } + #[doc = "Checks if the value of the field is `IDLE2`"] + #[inline(always)] + pub fn is_idle2(&self) -> bool { + **self == SLEEPMODE_A::IDLE2 + } + #[doc = "Checks if the value of the field is `STANDBY`"] + #[inline(always)] + pub fn is_standby(&self) -> bool { + **self == SLEEPMODE_A::STANDBY + } +} +impl core::ops::Deref for SLEEPMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLEEPMODE` writer - Sleep Mode"] +pub struct SLEEPMODE_W<'a> { + w: &'a mut W, +} +impl<'a> SLEEPMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SLEEPMODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "CPU clock is OFF"] + #[inline(always)] + pub fn idle0(self) -> &'a mut W { + self.variant(SLEEPMODE_A::IDLE0) + } + #[doc = "AHB clock is OFF"] + #[inline(always)] + pub fn idle1(self) -> &'a mut W { + self.variant(SLEEPMODE_A::IDLE1) + } + #[doc = "APB clock are OFF"] + #[inline(always)] + pub fn idle2(self) -> &'a mut W { + self.variant(SLEEPMODE_A::IDLE2) + } + #[doc = "All Clocks are OFF"] + #[inline(always)] + pub fn standby(self) -> &'a mut W { + self.variant(SLEEPMODE_A::STANDBY) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Sleep Mode"] + #[inline(always)] + pub fn sleepmode(&self) -> SLEEPMODE_R { + SLEEPMODE_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Sleep Mode"] + #[inline(always)] + pub fn sleepmode(&mut self) -> SLEEPMODE_W { + SLEEPMODE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Sleep Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sleepcfg](index.html) module"] +pub struct SLEEPCFG_SPEC; +impl crate::RegisterSpec for SLEEPCFG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [sleepcfg::R](R) reader structure"] +impl crate::Readable for SLEEPCFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [sleepcfg::W](W) writer structure"] +impl crate::Writable for SLEEPCFG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SLEEPCFG to value 0"] +impl crate::Resettable for SLEEPCFG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/pm/stdbycfg.rs b/pac/atsamc21e/src/pm/stdbycfg.rs new file mode 100644 index 000000000000..9780f2b001f5 --- /dev/null +++ b/pac/atsamc21e/src/pm/stdbycfg.rs @@ -0,0 +1,212 @@ +#[doc = "Register `STDBYCFG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STDBYCFG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Voltage Regulator Standby mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum VREGSMOD_A { + #[doc = "0: Automatic mode"] + AUTO = 0, + #[doc = "1: Performance oriented"] + PERFORMANCE = 1, + #[doc = "2: Low Power oriented"] + LP = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: VREGSMOD_A) -> Self { + variant as _ + } +} +#[doc = "Field `VREGSMOD` reader - Voltage Regulator Standby mode"] +pub struct VREGSMOD_R(crate::FieldReader); +impl VREGSMOD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + VREGSMOD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(VREGSMOD_A::AUTO), + 1 => Some(VREGSMOD_A::PERFORMANCE), + 2 => Some(VREGSMOD_A::LP), + _ => None, + } + } + #[doc = "Checks if the value of the field is `AUTO`"] + #[inline(always)] + pub fn is_auto(&self) -> bool { + **self == VREGSMOD_A::AUTO + } + #[doc = "Checks if the value of the field is `PERFORMANCE`"] + #[inline(always)] + pub fn is_performance(&self) -> bool { + **self == VREGSMOD_A::PERFORMANCE + } + #[doc = "Checks if the value of the field is `LP`"] + #[inline(always)] + pub fn is_lp(&self) -> bool { + **self == VREGSMOD_A::LP + } +} +impl core::ops::Deref for VREGSMOD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VREGSMOD` writer - Voltage Regulator Standby mode"] +pub struct VREGSMOD_W<'a> { + w: &'a mut W, +} +impl<'a> VREGSMOD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: VREGSMOD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Automatic mode"] + #[inline(always)] + pub fn auto(self) -> &'a mut W { + self.variant(VREGSMOD_A::AUTO) + } + #[doc = "Performance oriented"] + #[inline(always)] + pub fn performance(self) -> &'a mut W { + self.variant(VREGSMOD_A::PERFORMANCE) + } + #[doc = "Low Power oriented"] + #[inline(always)] + pub fn lp(self) -> &'a mut W { + self.variant(VREGSMOD_A::LP) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 6)) | ((value as u16 & 0x03) << 6); + self.w + } +} +#[doc = "Field `BBIASHS` reader - Back Bias for HMCRAMCHS"] +pub struct BBIASHS_R(crate::FieldReader); +impl BBIASHS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BBIASHS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BBIASHS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BBIASHS` writer - Back Bias for HMCRAMCHS"] +pub struct BBIASHS_W<'a> { + w: &'a mut W, +} +impl<'a> BBIASHS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u16 & 0x01) << 10); + self.w + } +} +impl R { + #[doc = "Bits 6:7 - Voltage Regulator Standby mode"] + #[inline(always)] + pub fn vregsmod(&self) -> VREGSMOD_R { + VREGSMOD_R::new(((self.bits >> 6) & 0x03) as u8) + } + #[doc = "Bit 10 - Back Bias for HMCRAMCHS"] + #[inline(always)] + pub fn bbiashs(&self) -> BBIASHS_R { + BBIASHS_R::new(((self.bits >> 10) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 6:7 - Voltage Regulator Standby mode"] + #[inline(always)] + pub fn vregsmod(&mut self) -> VREGSMOD_W { + VREGSMOD_W { w: self } + } + #[doc = "Bit 10 - Back Bias for HMCRAMCHS"] + #[inline(always)] + pub fn bbiashs(&mut self) -> BBIASHS_W { + BBIASHS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Standby Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [stdbycfg](index.html) module"] +pub struct STDBYCFG_SPEC; +impl crate::RegisterSpec for STDBYCFG_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [stdbycfg::R](R) reader structure"] +impl crate::Readable for STDBYCFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [stdbycfg::W](W) writer structure"] +impl crate::Writable for STDBYCFG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STDBYCFG to value 0x0400"] +impl crate::Resettable for STDBYCFG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0400 + } +} diff --git a/pac/atsamc21e/src/port.rs b/pac/atsamc21e/src/port.rs new file mode 100644 index 000000000000..0ca09e672d24 --- /dev/null +++ b/pac/atsamc21e/src/port.rs @@ -0,0 +1,41 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00..0x60 - GROUP\\[%s\\]"] + pub group0: GROUP, +} +#[doc = r"Register block"] +#[repr(C)] +pub struct GROUP { + #[doc = "0x00 - Data Direction"] + pub dir: crate::Reg, + #[doc = "0x04 - Data Direction Clear"] + pub dirclr: crate::Reg, + #[doc = "0x08 - Data Direction Set"] + pub dirset: crate::Reg, + #[doc = "0x0c - Data Direction Toggle"] + pub dirtgl: crate::Reg, + #[doc = "0x10 - Data Output Value"] + pub out: crate::Reg, + #[doc = "0x14 - Data Output Value Clear"] + pub outclr: crate::Reg, + #[doc = "0x18 - Data Output Value Set"] + pub outset: crate::Reg, + #[doc = "0x1c - Data Output Value Toggle"] + pub outtgl: crate::Reg, + #[doc = "0x20 - Data Input Value"] + pub in_: crate::Reg, + #[doc = "0x24 - Control"] + pub ctrl: crate::Reg, + #[doc = "0x28 - Write Configuration"] + pub wrconfig: crate::Reg, + #[doc = "0x2c - Event Input Control"] + pub evctrl: crate::Reg, + #[doc = "0x30..0x40 - Peripheral Multiplexing n"] + pub pmux: [crate::Reg; 16], + #[doc = "0x40..0x60 - Pin Configuration n"] + pub pincfg: [crate::Reg; 32], +} +#[doc = r"Register block"] +#[doc = "GROUP\\[%s\\]"] +pub mod group; diff --git a/pac/atsamc21e/src/port/group.rs b/pac/atsamc21e/src/port/group.rs new file mode 100644 index 000000000000..d1aabcd73380 --- /dev/null +++ b/pac/atsamc21e/src/port/group.rs @@ -0,0 +1,56 @@ +#[doc = "DIR register accessor: an alias for `Reg`"] +pub type DIR = crate::Reg; +#[doc = "Data Direction"] +pub mod dir; +#[doc = "DIRCLR register accessor: an alias for `Reg`"] +pub type DIRCLR = crate::Reg; +#[doc = "Data Direction Clear"] +pub mod dirclr; +#[doc = "DIRSET register accessor: an alias for `Reg`"] +pub type DIRSET = crate::Reg; +#[doc = "Data Direction Set"] +pub mod dirset; +#[doc = "DIRTGL register accessor: an alias for `Reg`"] +pub type DIRTGL = crate::Reg; +#[doc = "Data Direction Toggle"] +pub mod dirtgl; +#[doc = "OUT register accessor: an alias for `Reg`"] +pub type OUT = crate::Reg; +#[doc = "Data Output Value"] +pub mod out; +#[doc = "OUTCLR register accessor: an alias for `Reg`"] +pub type OUTCLR = crate::Reg; +#[doc = "Data Output Value Clear"] +pub mod outclr; +#[doc = "OUTSET register accessor: an alias for `Reg`"] +pub type OUTSET = crate::Reg; +#[doc = "Data Output Value Set"] +pub mod outset; +#[doc = "OUTTGL register accessor: an alias for `Reg`"] +pub type OUTTGL = crate::Reg; +#[doc = "Data Output Value Toggle"] +pub mod outtgl; +#[doc = "IN register accessor: an alias for `Reg`"] +pub type IN = crate::Reg; +#[doc = "Data Input Value"] +pub mod in_; +#[doc = "CTRL register accessor: an alias for `Reg`"] +pub type CTRL = crate::Reg; +#[doc = "Control"] +pub mod ctrl; +#[doc = "WRCONFIG register accessor: an alias for `Reg`"] +pub type WRCONFIG = crate::Reg; +#[doc = "Write Configuration"] +pub mod wrconfig; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Input Control"] +pub mod evctrl; +#[doc = "PMUX register accessor: an alias for `Reg`"] +pub type PMUX = crate::Reg; +#[doc = "Peripheral Multiplexing n"] +pub mod pmux; +#[doc = "PINCFG register accessor: an alias for `Reg`"] +pub type PINCFG = crate::Reg; +#[doc = "Pin Configuration n"] +pub mod pincfg; diff --git a/pac/atsamc21e/src/port/group/ctrl.rs b/pac/atsamc21e/src/port/group/ctrl.rs new file mode 100644 index 000000000000..4b57cd6fcd2b --- /dev/null +++ b/pac/atsamc21e/src/port/group/ctrl.rs @@ -0,0 +1,103 @@ +#[doc = "Register `CTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SAMPLING` reader - Input Sampling Mode"] +pub struct SAMPLING_R(crate::FieldReader); +impl SAMPLING_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + SAMPLING_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SAMPLING_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SAMPLING` writer - Input Sampling Mode"] +pub struct SAMPLING_W<'a> { + w: &'a mut W, +} +impl<'a> SAMPLING_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Input Sampling Mode"] + #[inline(always)] + pub fn sampling(&self) -> SAMPLING_R { + SAMPLING_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Input Sampling Mode"] + #[inline(always)] + pub fn sampling(&mut self) -> SAMPLING_W { + SAMPLING_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"] +pub struct CTRL_SPEC; +impl crate::RegisterSpec for CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrl::R](R) reader structure"] +impl crate::Readable for CTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"] +impl crate::Writable for CTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/port/group/dir.rs b/pac/atsamc21e/src/port/group/dir.rs new file mode 100644 index 000000000000..e04452fb5d35 --- /dev/null +++ b/pac/atsamc21e/src/port/group/dir.rs @@ -0,0 +1,64 @@ +#[doc = "Register `DIR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Direction\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dir](index.html) module"] +pub struct DIR_SPEC; +impl crate::RegisterSpec for DIR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dir::R](R) reader structure"] +impl crate::Readable for DIR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dir::W](W) writer structure"] +impl crate::Writable for DIR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DIR to value 0"] +impl crate::Resettable for DIR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/port/group/dirclr.rs b/pac/atsamc21e/src/port/group/dirclr.rs new file mode 100644 index 000000000000..5e6d73d032b2 --- /dev/null +++ b/pac/atsamc21e/src/port/group/dirclr.rs @@ -0,0 +1,64 @@ +#[doc = "Register `DIRCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIRCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Direction Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dirclr](index.html) module"] +pub struct DIRCLR_SPEC; +impl crate::RegisterSpec for DIRCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dirclr::R](R) reader structure"] +impl crate::Readable for DIRCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dirclr::W](W) writer structure"] +impl crate::Writable for DIRCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DIRCLR to value 0"] +impl crate::Resettable for DIRCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/port/group/dirset.rs b/pac/atsamc21e/src/port/group/dirset.rs new file mode 100644 index 000000000000..eaa86e14f15d --- /dev/null +++ b/pac/atsamc21e/src/port/group/dirset.rs @@ -0,0 +1,64 @@ +#[doc = "Register `DIRSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIRSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Direction Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dirset](index.html) module"] +pub struct DIRSET_SPEC; +impl crate::RegisterSpec for DIRSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dirset::R](R) reader structure"] +impl crate::Readable for DIRSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dirset::W](W) writer structure"] +impl crate::Writable for DIRSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DIRSET to value 0"] +impl crate::Resettable for DIRSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/port/group/dirtgl.rs b/pac/atsamc21e/src/port/group/dirtgl.rs new file mode 100644 index 000000000000..fbd021438b1b --- /dev/null +++ b/pac/atsamc21e/src/port/group/dirtgl.rs @@ -0,0 +1,64 @@ +#[doc = "Register `DIRTGL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIRTGL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Direction Toggle\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dirtgl](index.html) module"] +pub struct DIRTGL_SPEC; +impl crate::RegisterSpec for DIRTGL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dirtgl::R](R) reader structure"] +impl crate::Readable for DIRTGL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dirtgl::W](W) writer structure"] +impl crate::Writable for DIRTGL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DIRTGL to value 0"] +impl crate::Resettable for DIRTGL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/port/group/evctrl.rs b/pac/atsamc21e/src/port/group/evctrl.rs new file mode 100644 index 000000000000..ef0a35987f3d --- /dev/null +++ b/pac/atsamc21e/src/port/group/evctrl.rs @@ -0,0 +1,625 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PID0` reader - Port Event Pin Identifier 0"] +pub struct PID0_R(crate::FieldReader); +impl PID0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PID0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PID0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PID0` writer - Port Event Pin Identifier 0"] +pub struct PID0_W<'a> { + w: &'a mut W, +} +impl<'a> PID0_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f); + self.w + } +} +#[doc = "Port Event Action 0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EVACT0_A { + #[doc = "0: Event output to pin"] + OUT = 0, + #[doc = "1: Set output register of pin on event"] + SET = 1, + #[doc = "2: Clear output register of pin on event"] + CLR = 2, + #[doc = "3: Toggle output register of pin on event"] + TGL = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EVACT0_A) -> Self { + variant as _ + } +} +#[doc = "Field `EVACT0` reader - Port Event Action 0"] +pub struct EVACT0_R(crate::FieldReader); +impl EVACT0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVACT0_A { + match self.bits { + 0 => EVACT0_A::OUT, + 1 => EVACT0_A::SET, + 2 => EVACT0_A::CLR, + 3 => EVACT0_A::TGL, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `OUT`"] + #[inline(always)] + pub fn is_out(&self) -> bool { + **self == EVACT0_A::OUT + } + #[doc = "Checks if the value of the field is `SET`"] + #[inline(always)] + pub fn is_set(&self) -> bool { + **self == EVACT0_A::SET + } + #[doc = "Checks if the value of the field is `CLR`"] + #[inline(always)] + pub fn is_clr(&self) -> bool { + **self == EVACT0_A::CLR + } + #[doc = "Checks if the value of the field is `TGL`"] + #[inline(always)] + pub fn is_tgl(&self) -> bool { + **self == EVACT0_A::TGL + } +} +impl core::ops::Deref for EVACT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT0` writer - Port Event Action 0"] +pub struct EVACT0_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT0_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EVACT0_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Event output to pin"] + #[inline(always)] + pub fn out(self) -> &'a mut W { + self.variant(EVACT0_A::OUT) + } + #[doc = "Set output register of pin on event"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(EVACT0_A::SET) + } + #[doc = "Clear output register of pin on event"] + #[inline(always)] + pub fn clr(self) -> &'a mut W { + self.variant(EVACT0_A::CLR) + } + #[doc = "Toggle output register of pin on event"] + #[inline(always)] + pub fn tgl(self) -> &'a mut W { + self.variant(EVACT0_A::TGL) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 5)) | ((value as u32 & 0x03) << 5); + self.w + } +} +#[doc = "Field `PORTEI0` reader - Port Event Enable Input 0"] +pub struct PORTEI0_R(crate::FieldReader); +impl PORTEI0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PORTEI0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PORTEI0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PORTEI0` writer - Port Event Enable Input 0"] +pub struct PORTEI0_W<'a> { + w: &'a mut W, +} +impl<'a> PORTEI0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `PID1` reader - Port Event Pin Identifier 1"] +pub struct PID1_R(crate::FieldReader); +impl PID1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PID1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PID1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PID1` writer - Port Event Pin Identifier 1"] +pub struct PID1_W<'a> { + w: &'a mut W, +} +impl<'a> PID1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 8)) | ((value as u32 & 0x1f) << 8); + self.w + } +} +#[doc = "Field `EVACT1` reader - Port Event Action 1"] +pub struct EVACT1_R(crate::FieldReader); +impl EVACT1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVACT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT1` writer - Port Event Action 1"] +pub struct EVACT1_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 13)) | ((value as u32 & 0x03) << 13); + self.w + } +} +#[doc = "Field `PORTEI1` reader - Port Event Enable Input 1"] +pub struct PORTEI1_R(crate::FieldReader); +impl PORTEI1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PORTEI1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PORTEI1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PORTEI1` writer - Port Event Enable Input 1"] +pub struct PORTEI1_W<'a> { + w: &'a mut W, +} +impl<'a> PORTEI1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `PID2` reader - Port Event Pin Identifier 2"] +pub struct PID2_R(crate::FieldReader); +impl PID2_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PID2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PID2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PID2` writer - Port Event Pin Identifier 2"] +pub struct PID2_W<'a> { + w: &'a mut W, +} +impl<'a> PID2_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 16)) | ((value as u32 & 0x1f) << 16); + self.w + } +} +#[doc = "Field `EVACT2` reader - Port Event Action 2"] +pub struct EVACT2_R(crate::FieldReader); +impl EVACT2_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVACT2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT2` writer - Port Event Action 2"] +pub struct EVACT2_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT2_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 21)) | ((value as u32 & 0x03) << 21); + self.w + } +} +#[doc = "Field `PORTEI2` reader - Port Event Enable Input 2"] +pub struct PORTEI2_R(crate::FieldReader); +impl PORTEI2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PORTEI2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PORTEI2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PORTEI2` writer - Port Event Enable Input 2"] +pub struct PORTEI2_W<'a> { + w: &'a mut W, +} +impl<'a> PORTEI2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `PID3` reader - Port Event Pin Identifier 3"] +pub struct PID3_R(crate::FieldReader); +impl PID3_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PID3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PID3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PID3` writer - Port Event Pin Identifier 3"] +pub struct PID3_W<'a> { + w: &'a mut W, +} +impl<'a> PID3_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 24)) | ((value as u32 & 0x1f) << 24); + self.w + } +} +#[doc = "Field `EVACT3` reader - Port Event Action 3"] +pub struct EVACT3_R(crate::FieldReader); +impl EVACT3_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVACT3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT3` writer - Port Event Action 3"] +pub struct EVACT3_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT3_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 29)) | ((value as u32 & 0x03) << 29); + self.w + } +} +#[doc = "Field `PORTEI3` reader - Port Event Enable Input 3"] +pub struct PORTEI3_R(crate::FieldReader); +impl PORTEI3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PORTEI3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PORTEI3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PORTEI3` writer - Port Event Enable Input 3"] +pub struct PORTEI3_W<'a> { + w: &'a mut W, +} +impl<'a> PORTEI3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Port Event Pin Identifier 0"] + #[inline(always)] + pub fn pid0(&self) -> PID0_R { + PID0_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:6 - Port Event Action 0"] + #[inline(always)] + pub fn evact0(&self) -> EVACT0_R { + EVACT0_R::new(((self.bits >> 5) & 0x03) as u8) + } + #[doc = "Bit 7 - Port Event Enable Input 0"] + #[inline(always)] + pub fn portei0(&self) -> PORTEI0_R { + PORTEI0_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:12 - Port Event Pin Identifier 1"] + #[inline(always)] + pub fn pid1(&self) -> PID1_R { + PID1_R::new(((self.bits >> 8) & 0x1f) as u8) + } + #[doc = "Bits 13:14 - Port Event Action 1"] + #[inline(always)] + pub fn evact1(&self) -> EVACT1_R { + EVACT1_R::new(((self.bits >> 13) & 0x03) as u8) + } + #[doc = "Bit 15 - Port Event Enable Input 1"] + #[inline(always)] + pub fn portei1(&self) -> PORTEI1_R { + PORTEI1_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:20 - Port Event Pin Identifier 2"] + #[inline(always)] + pub fn pid2(&self) -> PID2_R { + PID2_R::new(((self.bits >> 16) & 0x1f) as u8) + } + #[doc = "Bits 21:22 - Port Event Action 2"] + #[inline(always)] + pub fn evact2(&self) -> EVACT2_R { + EVACT2_R::new(((self.bits >> 21) & 0x03) as u8) + } + #[doc = "Bit 23 - Port Event Enable Input 2"] + #[inline(always)] + pub fn portei2(&self) -> PORTEI2_R { + PORTEI2_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bits 24:28 - Port Event Pin Identifier 3"] + #[inline(always)] + pub fn pid3(&self) -> PID3_R { + PID3_R::new(((self.bits >> 24) & 0x1f) as u8) + } + #[doc = "Bits 29:30 - Port Event Action 3"] + #[inline(always)] + pub fn evact3(&self) -> EVACT3_R { + EVACT3_R::new(((self.bits >> 29) & 0x03) as u8) + } + #[doc = "Bit 31 - Port Event Enable Input 3"] + #[inline(always)] + pub fn portei3(&self) -> PORTEI3_R { + PORTEI3_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Port Event Pin Identifier 0"] + #[inline(always)] + pub fn pid0(&mut self) -> PID0_W { + PID0_W { w: self } + } + #[doc = "Bits 5:6 - Port Event Action 0"] + #[inline(always)] + pub fn evact0(&mut self) -> EVACT0_W { + EVACT0_W { w: self } + } + #[doc = "Bit 7 - Port Event Enable Input 0"] + #[inline(always)] + pub fn portei0(&mut self) -> PORTEI0_W { + PORTEI0_W { w: self } + } + #[doc = "Bits 8:12 - Port Event Pin Identifier 1"] + #[inline(always)] + pub fn pid1(&mut self) -> PID1_W { + PID1_W { w: self } + } + #[doc = "Bits 13:14 - Port Event Action 1"] + #[inline(always)] + pub fn evact1(&mut self) -> EVACT1_W { + EVACT1_W { w: self } + } + #[doc = "Bit 15 - Port Event Enable Input 1"] + #[inline(always)] + pub fn portei1(&mut self) -> PORTEI1_W { + PORTEI1_W { w: self } + } + #[doc = "Bits 16:20 - Port Event Pin Identifier 2"] + #[inline(always)] + pub fn pid2(&mut self) -> PID2_W { + PID2_W { w: self } + } + #[doc = "Bits 21:22 - Port Event Action 2"] + #[inline(always)] + pub fn evact2(&mut self) -> EVACT2_W { + EVACT2_W { w: self } + } + #[doc = "Bit 23 - Port Event Enable Input 2"] + #[inline(always)] + pub fn portei2(&mut self) -> PORTEI2_W { + PORTEI2_W { w: self } + } + #[doc = "Bits 24:28 - Port Event Pin Identifier 3"] + #[inline(always)] + pub fn pid3(&mut self) -> PID3_W { + PID3_W { w: self } + } + #[doc = "Bits 29:30 - Port Event Action 3"] + #[inline(always)] + pub fn evact3(&mut self) -> EVACT3_W { + EVACT3_W { w: self } + } + #[doc = "Bit 31 - Port Event Enable Input 3"] + #[inline(always)] + pub fn portei3(&mut self) -> PORTEI3_W { + PORTEI3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Input Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/port/group/in_.rs b/pac/atsamc21e/src/port/group/in_.rs new file mode 100644 index 000000000000..1c8e7396a83e --- /dev/null +++ b/pac/atsamc21e/src/port/group/in_.rs @@ -0,0 +1,31 @@ +#[doc = "Register `IN` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Data Input Value\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [in_](index.html) module"] +pub struct IN_SPEC; +impl crate::RegisterSpec for IN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [in_::R](R) reader structure"] +impl crate::Readable for IN_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets IN to value 0"] +impl crate::Resettable for IN_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/port/group/out.rs b/pac/atsamc21e/src/port/group/out.rs new file mode 100644 index 000000000000..092e8dbd8023 --- /dev/null +++ b/pac/atsamc21e/src/port/group/out.rs @@ -0,0 +1,64 @@ +#[doc = "Register `OUT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OUT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Output Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [out](index.html) module"] +pub struct OUT_SPEC; +impl crate::RegisterSpec for OUT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [out::R](R) reader structure"] +impl crate::Readable for OUT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [out::W](W) writer structure"] +impl crate::Writable for OUT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OUT to value 0"] +impl crate::Resettable for OUT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/port/group/outclr.rs b/pac/atsamc21e/src/port/group/outclr.rs new file mode 100644 index 000000000000..6e734396601f --- /dev/null +++ b/pac/atsamc21e/src/port/group/outclr.rs @@ -0,0 +1,64 @@ +#[doc = "Register `OUTCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OUTCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Output Value Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [outclr](index.html) module"] +pub struct OUTCLR_SPEC; +impl crate::RegisterSpec for OUTCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [outclr::R](R) reader structure"] +impl crate::Readable for OUTCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [outclr::W](W) writer structure"] +impl crate::Writable for OUTCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OUTCLR to value 0"] +impl crate::Resettable for OUTCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/port/group/outset.rs b/pac/atsamc21e/src/port/group/outset.rs new file mode 100644 index 000000000000..6d39122deb4b --- /dev/null +++ b/pac/atsamc21e/src/port/group/outset.rs @@ -0,0 +1,64 @@ +#[doc = "Register `OUTSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OUTSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Output Value Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [outset](index.html) module"] +pub struct OUTSET_SPEC; +impl crate::RegisterSpec for OUTSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [outset::R](R) reader structure"] +impl crate::Readable for OUTSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [outset::W](W) writer structure"] +impl crate::Writable for OUTSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OUTSET to value 0"] +impl crate::Resettable for OUTSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/port/group/outtgl.rs b/pac/atsamc21e/src/port/group/outtgl.rs new file mode 100644 index 000000000000..0f3d87d6476d --- /dev/null +++ b/pac/atsamc21e/src/port/group/outtgl.rs @@ -0,0 +1,64 @@ +#[doc = "Register `OUTTGL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OUTTGL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Output Value Toggle\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [outtgl](index.html) module"] +pub struct OUTTGL_SPEC; +impl crate::RegisterSpec for OUTTGL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [outtgl::R](R) reader structure"] +impl crate::Readable for OUTTGL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [outtgl::W](W) writer structure"] +impl crate::Writable for OUTTGL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OUTTGL to value 0"] +impl crate::Resettable for OUTTGL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/port/group/pincfg.rs b/pac/atsamc21e/src/port/group/pincfg.rs new file mode 100644 index 000000000000..920af6550361 --- /dev/null +++ b/pac/atsamc21e/src/port/group/pincfg.rs @@ -0,0 +1,255 @@ +#[doc = "Register `PINCFG[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PINCFG[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PMUXEN` reader - Select Peripheral Multiplexer"] +pub struct PMUXEN_R(crate::FieldReader); +impl PMUXEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PMUXEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PMUXEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PMUXEN` writer - Select Peripheral Multiplexer"] +pub struct PMUXEN_W<'a> { + w: &'a mut W, +} +impl<'a> PMUXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `INEN` reader - Input Enable"] +pub struct INEN_R(crate::FieldReader); +impl INEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INEN` writer - Input Enable"] +pub struct INEN_W<'a> { + w: &'a mut W, +} +impl<'a> INEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PULLEN` reader - Pull Enable"] +pub struct PULLEN_R(crate::FieldReader); +impl PULLEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PULLEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PULLEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PULLEN` writer - Pull Enable"] +pub struct PULLEN_W<'a> { + w: &'a mut W, +} +impl<'a> PULLEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `DRVSTR` reader - Output Driver Strength Selection"] +pub struct DRVSTR_R(crate::FieldReader); +impl DRVSTR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRVSTR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRVSTR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRVSTR` writer - Output Driver Strength Selection"] +pub struct DRVSTR_W<'a> { + w: &'a mut W, +} +impl<'a> DRVSTR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - Select Peripheral Multiplexer"] + #[inline(always)] + pub fn pmuxen(&self) -> PMUXEN_R { + PMUXEN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Input Enable"] + #[inline(always)] + pub fn inen(&self) -> INEN_R { + INEN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Pull Enable"] + #[inline(always)] + pub fn pullen(&self) -> PULLEN_R { + PULLEN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 6 - Output Driver Strength Selection"] + #[inline(always)] + pub fn drvstr(&self) -> DRVSTR_R { + DRVSTR_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Select Peripheral Multiplexer"] + #[inline(always)] + pub fn pmuxen(&mut self) -> PMUXEN_W { + PMUXEN_W { w: self } + } + #[doc = "Bit 1 - Input Enable"] + #[inline(always)] + pub fn inen(&mut self) -> INEN_W { + INEN_W { w: self } + } + #[doc = "Bit 2 - Pull Enable"] + #[inline(always)] + pub fn pullen(&mut self) -> PULLEN_W { + PULLEN_W { w: self } + } + #[doc = "Bit 6 - Output Driver Strength Selection"] + #[inline(always)] + pub fn drvstr(&mut self) -> DRVSTR_W { + DRVSTR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Pin Configuration n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pincfg](index.html) module"] +pub struct PINCFG_SPEC; +impl crate::RegisterSpec for PINCFG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [pincfg::R](R) reader structure"] +impl crate::Readable for PINCFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [pincfg::W](W) writer structure"] +impl crate::Writable for PINCFG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PINCFG[%s] +to value 0"] +impl crate::Resettable for PINCFG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/port/group/pmux.rs b/pac/atsamc21e/src/port/group/pmux.rs new file mode 100644 index 000000000000..79c991a99daf --- /dev/null +++ b/pac/atsamc21e/src/port/group/pmux.rs @@ -0,0 +1,141 @@ +#[doc = "Register `PMUX[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PMUX[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PMUXE` reader - Peripheral Multiplexing for Even-Numbered Pin"] +pub struct PMUXE_R(crate::FieldReader); +impl PMUXE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PMUXE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PMUXE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PMUXE` writer - Peripheral Multiplexing for Even-Numbered Pin"] +pub struct PMUXE_W<'a> { + w: &'a mut W, +} +impl<'a> PMUXE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +#[doc = "Field `PMUXO` reader - Peripheral Multiplexing for Odd-Numbered Pin"] +pub struct PMUXO_R(crate::FieldReader); +impl PMUXO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PMUXO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PMUXO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PMUXO` writer - Peripheral Multiplexing for Odd-Numbered Pin"] +pub struct PMUXO_W<'a> { + w: &'a mut W, +} +impl<'a> PMUXO_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 4)) | ((value as u8 & 0x0f) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Peripheral Multiplexing for Even-Numbered Pin"] + #[inline(always)] + pub fn pmuxe(&self) -> PMUXE_R { + PMUXE_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Peripheral Multiplexing for Odd-Numbered Pin"] + #[inline(always)] + pub fn pmuxo(&self) -> PMUXO_R { + PMUXO_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Peripheral Multiplexing for Even-Numbered Pin"] + #[inline(always)] + pub fn pmuxe(&mut self) -> PMUXE_W { + PMUXE_W { w: self } + } + #[doc = "Bits 4:7 - Peripheral Multiplexing for Odd-Numbered Pin"] + #[inline(always)] + pub fn pmuxo(&mut self) -> PMUXO_W { + PMUXO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Peripheral Multiplexing n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pmux](index.html) module"] +pub struct PMUX_SPEC; +impl crate::RegisterSpec for PMUX_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [pmux::R](R) reader structure"] +impl crate::Readable for PMUX_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [pmux::W](W) writer structure"] +impl crate::Writable for PMUX_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PMUX[%s] +to value 0"] +impl crate::Resettable for PMUX_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/port/group/wrconfig.rs b/pac/atsamc21e/src/port/group/wrconfig.rs new file mode 100644 index 000000000000..c87e4f174728 --- /dev/null +++ b/pac/atsamc21e/src/port/group/wrconfig.rs @@ -0,0 +1,268 @@ +#[doc = "Register `WRCONFIG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PINMASK` writer - Pin Mask for Multiple Pin Configuration"] +pub struct PINMASK_W<'a> { + w: &'a mut W, +} +impl<'a> PINMASK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +#[doc = "Field `PMUXEN` writer - Select Peripheral Multiplexer"] +pub struct PMUXEN_W<'a> { + w: &'a mut W, +} +impl<'a> PMUXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `INEN` writer - Input Enable"] +pub struct INEN_W<'a> { + w: &'a mut W, +} +impl<'a> INEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `PULLEN` writer - Pull Enable"] +pub struct PULLEN_W<'a> { + w: &'a mut W, +} +impl<'a> PULLEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `DRVSTR` writer - Output Driver Strength Selection"] +pub struct DRVSTR_W<'a> { + w: &'a mut W, +} +impl<'a> DRVSTR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `PMUX` writer - Peripheral Multiplexing Template"] +pub struct PMUX_W<'a> { + w: &'a mut W, +} +impl<'a> PMUX_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Field `WRPMUX` writer - Write PMUX Registers"] +pub struct WRPMUX_W<'a> { + w: &'a mut W, +} +impl<'a> WRPMUX_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Field `WRPINCFG` writer - Write PINCFG Registers"] +pub struct WRPINCFG_W<'a> { + w: &'a mut W, +} +impl<'a> WRPINCFG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +#[doc = "Field `HWSEL` writer - Half-Word Select"] +pub struct HWSEL_W<'a> { + w: &'a mut W, +} +impl<'a> HWSEL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl W { + #[doc = "Bits 0:15 - Pin Mask for Multiple Pin Configuration"] + #[inline(always)] + pub fn pinmask(&mut self) -> PINMASK_W { + PINMASK_W { w: self } + } + #[doc = "Bit 16 - Select Peripheral Multiplexer"] + #[inline(always)] + pub fn pmuxen(&mut self) -> PMUXEN_W { + PMUXEN_W { w: self } + } + #[doc = "Bit 17 - Input Enable"] + #[inline(always)] + pub fn inen(&mut self) -> INEN_W { + INEN_W { w: self } + } + #[doc = "Bit 18 - Pull Enable"] + #[inline(always)] + pub fn pullen(&mut self) -> PULLEN_W { + PULLEN_W { w: self } + } + #[doc = "Bit 22 - Output Driver Strength Selection"] + #[inline(always)] + pub fn drvstr(&mut self) -> DRVSTR_W { + DRVSTR_W { w: self } + } + #[doc = "Bits 24:27 - Peripheral Multiplexing Template"] + #[inline(always)] + pub fn pmux(&mut self) -> PMUX_W { + PMUX_W { w: self } + } + #[doc = "Bit 28 - Write PMUX Registers"] + #[inline(always)] + pub fn wrpmux(&mut self) -> WRPMUX_W { + WRPMUX_W { w: self } + } + #[doc = "Bit 30 - Write PINCFG Registers"] + #[inline(always)] + pub fn wrpincfg(&mut self) -> WRPINCFG_W { + WRPINCFG_W { w: self } + } + #[doc = "Bit 31 - Half-Word Select"] + #[inline(always)] + pub fn hwsel(&mut self) -> HWSEL_W { + HWSEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Write Configuration\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wrconfig](index.html) module"] +pub struct WRCONFIG_SPEC; +impl crate::RegisterSpec for WRCONFIG_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [wrconfig::W](W) writer structure"] +impl crate::Writable for WRCONFIG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WRCONFIG to value 0"] +impl crate::Resettable for WRCONFIG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/rstc.rs b/pac/atsamc21e/src/rstc.rs new file mode 100644 index 000000000000..327b511df28a --- /dev/null +++ b/pac/atsamc21e/src/rstc.rs @@ -0,0 +1,10 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Reset Cause"] + pub rcause: crate::Reg, +} +#[doc = "RCAUSE register accessor: an alias for `Reg`"] +pub type RCAUSE = crate::Reg; +#[doc = "Reset Cause"] +pub mod rcause; diff --git a/pac/atsamc21e/src/rstc/rcause.rs b/pac/atsamc21e/src/rstc/rcause.rs new file mode 100644 index 000000000000..3dc13496e74b --- /dev/null +++ b/pac/atsamc21e/src/rstc/rcause.rs @@ -0,0 +1,153 @@ +#[doc = "Register `RCAUSE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `POR` reader - Power On Reset"] +pub struct POR_R(crate::FieldReader); +impl POR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + POR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for POR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODCORE` reader - Brown Out CORE Detector Reset"] +pub struct BODCORE_R(crate::FieldReader); +impl BODCORE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODCORE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODCORE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODVDD` reader - Brown Out VDD Detector Reset"] +pub struct BODVDD_R(crate::FieldReader); +impl BODVDD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODVDD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODVDD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXT` reader - External Reset"] +pub struct EXT_R(crate::FieldReader); +impl EXT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WDT` reader - Watchdog Reset"] +pub struct WDT_R(crate::FieldReader); +impl WDT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WDT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WDT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYST` reader - System Reset Request"] +pub struct SYST_R(crate::FieldReader); +impl SYST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Power On Reset"] + #[inline(always)] + pub fn por(&self) -> POR_R { + POR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Brown Out CORE Detector Reset"] + #[inline(always)] + pub fn bodcore(&self) -> BODCORE_R { + BODCORE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Brown Out VDD Detector Reset"] + #[inline(always)] + pub fn bodvdd(&self) -> BODVDD_R { + BODVDD_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 4 - External Reset"] + #[inline(always)] + pub fn ext(&self) -> EXT_R { + EXT_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Watchdog Reset"] + #[inline(always)] + pub fn wdt(&self) -> WDT_R { + WDT_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - System Reset Request"] + #[inline(always)] + pub fn syst(&self) -> SYST_R { + SYST_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +#[doc = "Reset Cause\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rcause](index.html) module"] +pub struct RCAUSE_SPEC; +impl crate::RegisterSpec for RCAUSE_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [rcause::R](R) reader structure"] +impl crate::Readable for RCAUSE_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets RCAUSE to value 0"] +impl crate::Resettable for RCAUSE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/rtc.rs b/pac/atsamc21e/src/rtc.rs new file mode 100644 index 000000000000..62f424cb1a8e --- /dev/null +++ b/pac/atsamc21e/src/rtc.rs @@ -0,0 +1,120 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved_0_mode0: [u8; 0x25], +} +impl RegisterBlock { + #[doc = "0x00..0x25 - Clock/Calendar with Alarm"] + #[inline(always)] + pub fn mode2(&self) -> &MODE2 { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const MODE2) } + } + #[doc = "0x00..0x24 - 16-bit Counter with Two 16-bit Compares"] + #[inline(always)] + pub fn mode1(&self) -> &MODE1 { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const MODE1) } + } + #[doc = "0x00..0x24 - 32-bit Counter with Single 32-bit Compare"] + #[inline(always)] + pub fn mode0(&self) -> &MODE0 { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const MODE0) } + } +} +#[doc = r"Register block"] +#[repr(C)] +pub struct MODE0 { + #[doc = "0x00 - MODE0 Control A"] + pub ctrla: crate::Reg, + _reserved1: [u8; 0x02], + #[doc = "0x04 - MODE0 Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x08 - MODE0 Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x0a - MODE0 Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x0c - MODE0 Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x0e - Debug Control"] + pub dbgctrl: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x10 - MODE0 Synchronization Busy Status"] + pub syncbusy: crate::Reg, + #[doc = "0x14 - Frequency Correction"] + pub freqcorr: crate::Reg, + _reserved8: [u8; 0x03], + #[doc = "0x18 - MODE0 Counter Value"] + pub count: crate::Reg, + _reserved9: [u8; 0x04], + #[doc = "0x20 - MODE0 Compare n Value"] + pub comp: crate::Reg, +} +#[doc = r"Register block"] +#[doc = "32-bit Counter with Single 32-bit Compare"] +pub mod mode0; +#[doc = r"Register block"] +#[repr(C)] +pub struct MODE1 { + #[doc = "0x00 - MODE1 Control A"] + pub ctrla: crate::Reg, + _reserved1: [u8; 0x02], + #[doc = "0x04 - MODE1 Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x08 - MODE1 Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x0a - MODE1 Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x0c - MODE1 Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x0e - Debug Control"] + pub dbgctrl: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x10 - MODE1 Synchronization Busy Status"] + pub syncbusy: crate::Reg, + #[doc = "0x14 - Frequency Correction"] + pub freqcorr: crate::Reg, + _reserved8: [u8; 0x03], + #[doc = "0x18 - MODE1 Counter Value"] + pub count: crate::Reg, + _reserved9: [u8; 0x02], + #[doc = "0x1c - MODE1 Counter Period"] + pub per: crate::Reg, + _reserved10: [u8; 0x02], + #[doc = "0x20 - MODE1 Compare n Value"] + pub comp: [crate::Reg; 2], +} +#[doc = r"Register block"] +#[doc = "16-bit Counter with Two 16-bit Compares"] +pub mod mode1; +#[doc = r"Register block"] +#[repr(C)] +pub struct MODE2 { + #[doc = "0x00 - MODE2 Control A"] + pub ctrla: crate::Reg, + _reserved1: [u8; 0x02], + #[doc = "0x04 - MODE2 Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x08 - MODE2 Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x0a - MODE2 Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x0c - MODE2 Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x0e - Debug Control"] + pub dbgctrl: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x10 - MODE2 Synchronization Busy Status"] + pub syncbusy: crate::Reg, + #[doc = "0x14 - Frequency Correction"] + pub freqcorr: crate::Reg, + _reserved8: [u8; 0x03], + #[doc = "0x18 - MODE2 Clock Value"] + pub clock: crate::Reg, + _reserved9: [u8; 0x04], + #[doc = "0x20 - MODE2_ALARM Alarm n Value"] + pub alarm: crate::Reg, + #[doc = "0x24 - MODE2_ALARM Alarm n Mask"] + pub mask: crate::Reg, +} +#[doc = r"Register block"] +#[doc = "Clock/Calendar with Alarm"] +pub mod mode2; diff --git a/pac/atsamc21e/src/rtc/mode0.rs b/pac/atsamc21e/src/rtc/mode0.rs new file mode 100644 index 000000000000..9ce5c3808169 --- /dev/null +++ b/pac/atsamc21e/src/rtc/mode0.rs @@ -0,0 +1,40 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "MODE0 Control A"] +pub mod ctrla; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "MODE0 Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "MODE0 Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "MODE0 Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "MODE0 Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "MODE0 Synchronization Busy Status"] +pub mod syncbusy; +#[doc = "FREQCORR register accessor: an alias for `Reg`"] +pub type FREQCORR = crate::Reg; +#[doc = "Frequency Correction"] +pub mod freqcorr; +#[doc = "COUNT register accessor: an alias for `Reg`"] +pub type COUNT = crate::Reg; +#[doc = "MODE0 Counter Value"] +pub mod count; +#[doc = "COMP register accessor: an alias for `Reg`"] +pub type COMP = crate::Reg; +#[doc = "MODE0 Compare n Value"] +pub mod comp; diff --git a/pac/atsamc21e/src/rtc/mode0/comp.rs b/pac/atsamc21e/src/rtc/mode0/comp.rs new file mode 100644 index 000000000000..a909d3cea2d3 --- /dev/null +++ b/pac/atsamc21e/src/rtc/mode0/comp.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COMP` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COMP` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COMP` reader - Compare Value"] +pub struct COMP_R(crate::FieldReader); +impl COMP_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COMP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP` writer - Compare Value"] +pub struct COMP_W<'a> { + w: &'a mut W, +} +impl<'a> COMP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Compare Value"] + #[inline(always)] + pub fn comp(&self) -> COMP_R { + COMP_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Compare Value"] + #[inline(always)] + pub fn comp(&mut self) -> COMP_W { + COMP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE0 Compare n Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [comp](index.html) module"] +pub struct COMP_SPEC; +impl crate::RegisterSpec for COMP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [comp::R](R) reader structure"] +impl crate::Readable for COMP_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [comp::W](W) writer structure"] +impl crate::Writable for COMP_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COMP to value 0"] +impl crate::Resettable for COMP_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/rtc/mode0/count.rs b/pac/atsamc21e/src/rtc/mode0/count.rs new file mode 100644 index 000000000000..cf880b5e77a6 --- /dev/null +++ b/pac/atsamc21e/src/rtc/mode0/count.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE0 Counter Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count](index.html) module"] +pub struct COUNT_SPEC; +impl crate::RegisterSpec for COUNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [count::R](R) reader structure"] +impl crate::Readable for COUNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count::W](W) writer structure"] +impl crate::Writable for COUNT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT to value 0"] +impl crate::Resettable for COUNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/rtc/mode0/ctrla.rs b/pac/atsamc21e/src/rtc/mode0/ctrla.rs new file mode 100644 index 000000000000..423877bd087d --- /dev/null +++ b/pac/atsamc21e/src/rtc/mode0/ctrla.rs @@ -0,0 +1,569 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: Mode 0: 32-bit Counter"] + COUNT32 = 0, + #[doc = "1: Mode 1: 16-bit Counter"] + COUNT16 = 1, + #[doc = "2: Mode 2: Clock/Calendar"] + CLOCK = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::COUNT32), + 1 => Some(MODE_A::COUNT16), + 2 => Some(MODE_A::CLOCK), + _ => None, + } + } + #[doc = "Checks if the value of the field is `COUNT32`"] + #[inline(always)] + pub fn is_count32(&self) -> bool { + **self == MODE_A::COUNT32 + } + #[doc = "Checks if the value of the field is `COUNT16`"] + #[inline(always)] + pub fn is_count16(&self) -> bool { + **self == MODE_A::COUNT16 + } + #[doc = "Checks if the value of the field is `CLOCK`"] + #[inline(always)] + pub fn is_clock(&self) -> bool { + **self == MODE_A::CLOCK + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Mode 0: 32-bit Counter"] + #[inline(always)] + pub fn count32(self) -> &'a mut W { + self.variant(MODE_A::COUNT32) + } + #[doc = "Mode 1: 16-bit Counter"] + #[inline(always)] + pub fn count16(self) -> &'a mut W { + self.variant(MODE_A::COUNT16) + } + #[doc = "Mode 2: Clock/Calendar"] + #[inline(always)] + pub fn clock(self) -> &'a mut W { + self.variant(MODE_A::CLOCK) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u16 & 0x03) << 2); + self.w + } +} +#[doc = "Field `MATCHCLR` reader - Clear on Match"] +pub struct MATCHCLR_R(crate::FieldReader); +impl MATCHCLR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MATCHCLR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MATCHCLR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MATCHCLR` writer - Clear on Match"] +pub struct MATCHCLR_W<'a> { + w: &'a mut W, +} +impl<'a> MATCHCLR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: CLK_RTC_CNT = GCLK_RTC/1"] + OFF = 0, + #[doc = "1: CLK_RTC_CNT = GCLK_RTC/1"] + DIV1 = 1, + #[doc = "2: CLK_RTC_CNT = GCLK_RTC/2"] + DIV2 = 2, + #[doc = "3: CLK_RTC_CNT = GCLK_RTC/4"] + DIV4 = 3, + #[doc = "4: CLK_RTC_CNT = GCLK_RTC/8"] + DIV8 = 4, + #[doc = "5: CLK_RTC_CNT = GCLK_RTC/16"] + DIV16 = 5, + #[doc = "6: CLK_RTC_CNT = GCLK_RTC/32"] + DIV32 = 6, + #[doc = "7: CLK_RTC_CNT = GCLK_RTC/64"] + DIV64 = 7, + #[doc = "8: CLK_RTC_CNT = GCLK_RTC/128"] + DIV128 = 8, + #[doc = "9: CLK_RTC_CNT = GCLK_RTC/256"] + DIV256 = 9, + #[doc = "10: CLK_RTC_CNT = GCLK_RTC/512"] + DIV512 = 10, + #[doc = "11: CLK_RTC_CNT = GCLK_RTC/1024"] + DIV1024 = 11, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCALER_A::OFF), + 1 => Some(PRESCALER_A::DIV1), + 2 => Some(PRESCALER_A::DIV2), + 3 => Some(PRESCALER_A::DIV4), + 4 => Some(PRESCALER_A::DIV8), + 5 => Some(PRESCALER_A::DIV16), + 6 => Some(PRESCALER_A::DIV32), + 7 => Some(PRESCALER_A::DIV64), + 8 => Some(PRESCALER_A::DIV128), + 9 => Some(PRESCALER_A::DIV256), + 10 => Some(PRESCALER_A::DIV512), + 11 => Some(PRESCALER_A::DIV1024), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == PRESCALER_A::OFF + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == PRESCALER_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == PRESCALER_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == PRESCALER_A::DIV128 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV512`"] + #[inline(always)] + pub fn is_div512(&self) -> bool { + **self == PRESCALER_A::DIV512 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PRESCALER_A::DIV1024 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(PRESCALER_A::OFF) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV32) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV128) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/512"] + #[inline(always)] + pub fn div512(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV512) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 8)) | ((value as u16 & 0x0f) << 8); + self.w + } +} +#[doc = "Field `COUNTSYNC` reader - Count Read Synchronization Enable"] +pub struct COUNTSYNC_R(crate::FieldReader); +impl COUNTSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNTSYNC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNTSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNTSYNC` writer - Count Read Synchronization Enable"] +pub struct COUNTSYNC_W<'a> { + w: &'a mut W, +} +impl<'a> COUNTSYNC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:3 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bit 7 - Clear on Match"] + #[inline(always)] + pub fn matchclr(&self) -> MATCHCLR_R { + MATCHCLR_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:11 - Prescaler"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 15 - Count Read Synchronization Enable"] + #[inline(always)] + pub fn countsync(&self) -> COUNTSYNC_R { + COUNTSYNC_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:3 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 7 - Clear on Match"] + #[inline(always)] + pub fn matchclr(&mut self) -> MATCHCLR_W { + MATCHCLR_W { w: self } + } + #[doc = "Bits 8:11 - Prescaler"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Bit 15 - Count Read Synchronization Enable"] + #[inline(always)] + pub fn countsync(&mut self) -> COUNTSYNC_W { + COUNTSYNC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE0 Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/rtc/mode0/dbgctrl.rs b/pac/atsamc21e/src/rtc/mode0/dbgctrl.rs new file mode 100644 index 000000000000..0383e70d0429 --- /dev/null +++ b/pac/atsamc21e/src/rtc/mode0/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Run During Debug"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Run During Debug"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/rtc/mode0/evctrl.rs b/pac/atsamc21e/src/rtc/mode0/evctrl.rs new file mode 100644 index 000000000000..c73647759dbe --- /dev/null +++ b/pac/atsamc21e/src/rtc/mode0/evctrl.rs @@ -0,0 +1,536 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PEREO0` reader - Periodic Interval 0 Event Output Enable"] +pub struct PEREO0_R(crate::FieldReader); +impl PEREO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO0` writer - Periodic Interval 0 Event Output Enable"] +pub struct PEREO0_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `PEREO1` reader - Periodic Interval 1 Event Output Enable"] +pub struct PEREO1_R(crate::FieldReader); +impl PEREO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO1` writer - Periodic Interval 1 Event Output Enable"] +pub struct PEREO1_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PEREO2` reader - Periodic Interval 2 Event Output Enable"] +pub struct PEREO2_R(crate::FieldReader); +impl PEREO2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO2` writer - Periodic Interval 2 Event Output Enable"] +pub struct PEREO2_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PEREO3` reader - Periodic Interval 3 Event Output Enable"] +pub struct PEREO3_R(crate::FieldReader); +impl PEREO3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO3` writer - Periodic Interval 3 Event Output Enable"] +pub struct PEREO3_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PEREO4` reader - Periodic Interval 4 Event Output Enable"] +pub struct PEREO4_R(crate::FieldReader); +impl PEREO4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO4` writer - Periodic Interval 4 Event Output Enable"] +pub struct PEREO4_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PEREO5` reader - Periodic Interval 5 Event Output Enable"] +pub struct PEREO5_R(crate::FieldReader); +impl PEREO5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO5` writer - Periodic Interval 5 Event Output Enable"] +pub struct PEREO5_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PEREO6` reader - Periodic Interval 6 Event Output Enable"] +pub struct PEREO6_R(crate::FieldReader); +impl PEREO6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO6` writer - Periodic Interval 6 Event Output Enable"] +pub struct PEREO6_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PEREO7` reader - Periodic Interval 7 Event Output Enable"] +pub struct PEREO7_R(crate::FieldReader); +impl PEREO7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO7` writer - Periodic Interval 7 Event Output Enable"] +pub struct PEREO7_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CMPEO0` reader - Compare 0 Event Output Enable"] +pub struct CMPEO0_R(crate::FieldReader); +impl CMPEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMPEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMPEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMPEO0` writer - Compare 0 Event Output Enable"] +pub struct CMPEO0_W<'a> { + w: &'a mut W, +} +impl<'a> CMPEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `OVFEO` reader - Overflow Event Output Enable"] +pub struct OVFEO_R(crate::FieldReader); +impl OVFEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVFEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVFEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVFEO` writer - Overflow Event Output Enable"] +pub struct OVFEO_W<'a> { + w: &'a mut W, +} +impl<'a> OVFEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Event Output Enable"] + #[inline(always)] + pub fn pereo0(&self) -> PEREO0_R { + PEREO0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Event Output Enable"] + #[inline(always)] + pub fn pereo1(&self) -> PEREO1_R { + PEREO1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Event Output Enable"] + #[inline(always)] + pub fn pereo2(&self) -> PEREO2_R { + PEREO2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Event Output Enable"] + #[inline(always)] + pub fn pereo3(&self) -> PEREO3_R { + PEREO3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Event Output Enable"] + #[inline(always)] + pub fn pereo4(&self) -> PEREO4_R { + PEREO4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Event Output Enable"] + #[inline(always)] + pub fn pereo5(&self) -> PEREO5_R { + PEREO5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Event Output Enable"] + #[inline(always)] + pub fn pereo6(&self) -> PEREO6_R { + PEREO6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Event Output Enable"] + #[inline(always)] + pub fn pereo7(&self) -> PEREO7_R { + PEREO7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Compare 0 Event Output Enable"] + #[inline(always)] + pub fn cmpeo0(&self) -> CMPEO0_R { + CMPEO0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&self) -> OVFEO_R { + OVFEO_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Event Output Enable"] + #[inline(always)] + pub fn pereo0(&mut self) -> PEREO0_W { + PEREO0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1 Event Output Enable"] + #[inline(always)] + pub fn pereo1(&mut self) -> PEREO1_W { + PEREO1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2 Event Output Enable"] + #[inline(always)] + pub fn pereo2(&mut self) -> PEREO2_W { + PEREO2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3 Event Output Enable"] + #[inline(always)] + pub fn pereo3(&mut self) -> PEREO3_W { + PEREO3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4 Event Output Enable"] + #[inline(always)] + pub fn pereo4(&mut self) -> PEREO4_W { + PEREO4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5 Event Output Enable"] + #[inline(always)] + pub fn pereo5(&mut self) -> PEREO5_W { + PEREO5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6 Event Output Enable"] + #[inline(always)] + pub fn pereo6(&mut self) -> PEREO6_W { + PEREO6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7 Event Output Enable"] + #[inline(always)] + pub fn pereo7(&mut self) -> PEREO7_W { + PEREO7_W { w: self } + } + #[doc = "Bit 8 - Compare 0 Event Output Enable"] + #[inline(always)] + pub fn cmpeo0(&mut self) -> CMPEO0_W { + CMPEO0_W { w: self } + } + #[doc = "Bit 15 - Overflow Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&mut self) -> OVFEO_W { + OVFEO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE0 Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/rtc/mode0/freqcorr.rs b/pac/atsamc21e/src/rtc/mode0/freqcorr.rs new file mode 100644 index 000000000000..043ba6f88eb2 --- /dev/null +++ b/pac/atsamc21e/src/rtc/mode0/freqcorr.rs @@ -0,0 +1,150 @@ +#[doc = "Register `FREQCORR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FREQCORR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `VALUE` reader - Correction Value"] +pub struct VALUE_R(crate::FieldReader); +impl VALUE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + VALUE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VALUE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VALUE` writer - Correction Value"] +pub struct VALUE_W<'a> { + w: &'a mut W, +} +impl<'a> VALUE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x7f) | (value as u8 & 0x7f); + self.w + } +} +#[doc = "Field `SIGN` reader - Correction Sign"] +pub struct SIGN_R(crate::FieldReader); +impl SIGN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SIGN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SIGN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SIGN` writer - Correction Sign"] +pub struct SIGN_W<'a> { + w: &'a mut W, +} +impl<'a> SIGN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bits 0:6 - Correction Value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bit 7 - Correction Sign"] + #[inline(always)] + pub fn sign(&self) -> SIGN_R { + SIGN_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:6 - Correction Value"] + #[inline(always)] + pub fn value(&mut self) -> VALUE_W { + VALUE_W { w: self } + } + #[doc = "Bit 7 - Correction Sign"] + #[inline(always)] + pub fn sign(&mut self) -> SIGN_W { + SIGN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Frequency Correction\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [freqcorr](index.html) module"] +pub struct FREQCORR_SPEC; +impl crate::RegisterSpec for FREQCORR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [freqcorr::R](R) reader structure"] +impl crate::Readable for FREQCORR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [freqcorr::W](W) writer structure"] +impl crate::Writable for FREQCORR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets FREQCORR to value 0"] +impl crate::Resettable for FREQCORR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/rtc/mode0/intenclr.rs b/pac/atsamc21e/src/rtc/mode0/intenclr.rs new file mode 100644 index 000000000000..8be5e2c3920b --- /dev/null +++ b/pac/atsamc21e/src/rtc/mode0/intenclr.rs @@ -0,0 +1,536 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER0` reader - Periodic Interval 0 Interrupt Enable"] +pub struct PER0_R(crate::FieldReader); +impl PER0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER0` writer - Periodic Interval 0 Interrupt Enable"] +pub struct PER0_W<'a> { + w: &'a mut W, +} +impl<'a> PER0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PER1` reader - Periodic Interval 1 Interrupt Enable"] +pub struct PER1_R(crate::FieldReader); +impl PER1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER1` writer - Periodic Interval 1 Interrupt Enable"] +pub struct PER1_W<'a> { + w: &'a mut W, +} +impl<'a> PER1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PER2` reader - Periodic Interval 2 Interrupt Enable"] +pub struct PER2_R(crate::FieldReader); +impl PER2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER2` writer - Periodic Interval 2 Interrupt Enable"] +pub struct PER2_W<'a> { + w: &'a mut W, +} +impl<'a> PER2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PER3` reader - Periodic Interval 3 Interrupt Enable"] +pub struct PER3_R(crate::FieldReader); +impl PER3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER3` writer - Periodic Interval 3 Interrupt Enable"] +pub struct PER3_W<'a> { + w: &'a mut W, +} +impl<'a> PER3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PER4` reader - Periodic Interval 4 Interrupt Enable"] +pub struct PER4_R(crate::FieldReader); +impl PER4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER4` writer - Periodic Interval 4 Interrupt Enable"] +pub struct PER4_W<'a> { + w: &'a mut W, +} +impl<'a> PER4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PER5` reader - Periodic Interval 5 Interrupt Enable"] +pub struct PER5_R(crate::FieldReader); +impl PER5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER5` writer - Periodic Interval 5 Interrupt Enable"] +pub struct PER5_W<'a> { + w: &'a mut W, +} +impl<'a> PER5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PER6` reader - Periodic Interval 6 Interrupt Enable"] +pub struct PER6_R(crate::FieldReader); +impl PER6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER6` writer - Periodic Interval 6 Interrupt Enable"] +pub struct PER6_W<'a> { + w: &'a mut W, +} +impl<'a> PER6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PER7` reader - Periodic Interval 7 Interrupt Enable"] +pub struct PER7_R(crate::FieldReader); +impl PER7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER7` writer - Periodic Interval 7 Interrupt Enable"] +pub struct PER7_W<'a> { + w: &'a mut W, +} +impl<'a> PER7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CMP0` reader - Compare 0 Interrupt Enable"] +pub struct CMP0_R(crate::FieldReader); +impl CMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP0` writer - Compare 0 Interrupt Enable"] +pub struct CMP0_W<'a> { + w: &'a mut W, +} +impl<'a> CMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + pub fn per0(&self) -> PER0_R { + PER0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + pub fn per1(&self) -> PER1_R { + PER1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + pub fn per2(&self) -> PER2_R { + PER2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + pub fn per3(&self) -> PER3_R { + PER3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + pub fn per4(&self) -> PER4_R { + PER4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + pub fn per5(&self) -> PER5_R { + PER5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + pub fn per6(&self) -> PER6_R { + PER6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + pub fn per7(&self) -> PER7_R { + PER7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&self) -> CMP0_R { + CMP0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + pub fn per0(&mut self) -> PER0_W { + PER0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + pub fn per1(&mut self) -> PER1_W { + PER1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + pub fn per2(&mut self) -> PER2_W { + PER2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + pub fn per3(&mut self) -> PER3_W { + PER3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + pub fn per4(&mut self) -> PER4_W { + PER4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + pub fn per5(&mut self) -> PER5_W { + PER5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + pub fn per6(&mut self) -> PER6_W { + PER6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + pub fn per7(&mut self) -> PER7_W { + PER7_W { w: self } + } + #[doc = "Bit 8 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&mut self) -> CMP0_W { + CMP0_W { w: self } + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE0 Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/rtc/mode0/intenset.rs b/pac/atsamc21e/src/rtc/mode0/intenset.rs new file mode 100644 index 000000000000..7228f5d486f5 --- /dev/null +++ b/pac/atsamc21e/src/rtc/mode0/intenset.rs @@ -0,0 +1,536 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER0` reader - Periodic Interval 0 Interrupt Enable"] +pub struct PER0_R(crate::FieldReader); +impl PER0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER0` writer - Periodic Interval 0 Interrupt Enable"] +pub struct PER0_W<'a> { + w: &'a mut W, +} +impl<'a> PER0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PER1` reader - Periodic Interval 1 Interrupt Enable"] +pub struct PER1_R(crate::FieldReader); +impl PER1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER1` writer - Periodic Interval 1 Interrupt Enable"] +pub struct PER1_W<'a> { + w: &'a mut W, +} +impl<'a> PER1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PER2` reader - Periodic Interval 2 Interrupt Enable"] +pub struct PER2_R(crate::FieldReader); +impl PER2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER2` writer - Periodic Interval 2 Interrupt Enable"] +pub struct PER2_W<'a> { + w: &'a mut W, +} +impl<'a> PER2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PER3` reader - Periodic Interval 3 Interrupt Enable"] +pub struct PER3_R(crate::FieldReader); +impl PER3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER3` writer - Periodic Interval 3 Interrupt Enable"] +pub struct PER3_W<'a> { + w: &'a mut W, +} +impl<'a> PER3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PER4` reader - Periodic Interval 4 Interrupt Enable"] +pub struct PER4_R(crate::FieldReader); +impl PER4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER4` writer - Periodic Interval 4 Interrupt Enable"] +pub struct PER4_W<'a> { + w: &'a mut W, +} +impl<'a> PER4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PER5` reader - Periodic Interval 5 Interrupt Enable"] +pub struct PER5_R(crate::FieldReader); +impl PER5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER5` writer - Periodic Interval 5 Interrupt Enable"] +pub struct PER5_W<'a> { + w: &'a mut W, +} +impl<'a> PER5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PER6` reader - Periodic Interval 6 Interrupt Enable"] +pub struct PER6_R(crate::FieldReader); +impl PER6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER6` writer - Periodic Interval 6 Interrupt Enable"] +pub struct PER6_W<'a> { + w: &'a mut W, +} +impl<'a> PER6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PER7` reader - Periodic Interval 7 Interrupt Enable"] +pub struct PER7_R(crate::FieldReader); +impl PER7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER7` writer - Periodic Interval 7 Interrupt Enable"] +pub struct PER7_W<'a> { + w: &'a mut W, +} +impl<'a> PER7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CMP0` reader - Compare 0 Interrupt Enable"] +pub struct CMP0_R(crate::FieldReader); +impl CMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP0` writer - Compare 0 Interrupt Enable"] +pub struct CMP0_W<'a> { + w: &'a mut W, +} +impl<'a> CMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + pub fn per0(&self) -> PER0_R { + PER0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + pub fn per1(&self) -> PER1_R { + PER1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + pub fn per2(&self) -> PER2_R { + PER2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + pub fn per3(&self) -> PER3_R { + PER3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + pub fn per4(&self) -> PER4_R { + PER4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + pub fn per5(&self) -> PER5_R { + PER5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + pub fn per6(&self) -> PER6_R { + PER6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + pub fn per7(&self) -> PER7_R { + PER7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&self) -> CMP0_R { + CMP0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + pub fn per0(&mut self) -> PER0_W { + PER0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + pub fn per1(&mut self) -> PER1_W { + PER1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + pub fn per2(&mut self) -> PER2_W { + PER2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + pub fn per3(&mut self) -> PER3_W { + PER3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + pub fn per4(&mut self) -> PER4_W { + PER4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + pub fn per5(&mut self) -> PER5_W { + PER5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + pub fn per6(&mut self) -> PER6_W { + PER6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + pub fn per7(&mut self) -> PER7_W { + PER7_W { w: self } + } + #[doc = "Bit 8 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&mut self) -> CMP0_W { + CMP0_W { w: self } + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE0 Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/rtc/mode0/intflag.rs b/pac/atsamc21e/src/rtc/mode0/intflag.rs new file mode 100644 index 000000000000..f2dccdb04aa4 --- /dev/null +++ b/pac/atsamc21e/src/rtc/mode0/intflag.rs @@ -0,0 +1,536 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER0` reader - Periodic Interval 0"] +pub struct PER0_R(crate::FieldReader); +impl PER0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER0` writer - Periodic Interval 0"] +pub struct PER0_W<'a> { + w: &'a mut W, +} +impl<'a> PER0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PER1` reader - Periodic Interval 1"] +pub struct PER1_R(crate::FieldReader); +impl PER1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER1` writer - Periodic Interval 1"] +pub struct PER1_W<'a> { + w: &'a mut W, +} +impl<'a> PER1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PER2` reader - Periodic Interval 2"] +pub struct PER2_R(crate::FieldReader); +impl PER2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER2` writer - Periodic Interval 2"] +pub struct PER2_W<'a> { + w: &'a mut W, +} +impl<'a> PER2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PER3` reader - Periodic Interval 3"] +pub struct PER3_R(crate::FieldReader); +impl PER3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER3` writer - Periodic Interval 3"] +pub struct PER3_W<'a> { + w: &'a mut W, +} +impl<'a> PER3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PER4` reader - Periodic Interval 4"] +pub struct PER4_R(crate::FieldReader); +impl PER4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER4` writer - Periodic Interval 4"] +pub struct PER4_W<'a> { + w: &'a mut W, +} +impl<'a> PER4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PER5` reader - Periodic Interval 5"] +pub struct PER5_R(crate::FieldReader); +impl PER5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER5` writer - Periodic Interval 5"] +pub struct PER5_W<'a> { + w: &'a mut W, +} +impl<'a> PER5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PER6` reader - Periodic Interval 6"] +pub struct PER6_R(crate::FieldReader); +impl PER6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER6` writer - Periodic Interval 6"] +pub struct PER6_W<'a> { + w: &'a mut W, +} +impl<'a> PER6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PER7` reader - Periodic Interval 7"] +pub struct PER7_R(crate::FieldReader); +impl PER7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER7` writer - Periodic Interval 7"] +pub struct PER7_W<'a> { + w: &'a mut W, +} +impl<'a> PER7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CMP0` reader - Compare 0"] +pub struct CMP0_R(crate::FieldReader); +impl CMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP0` writer - Compare 0"] +pub struct CMP0_W<'a> { + w: &'a mut W, +} +impl<'a> CMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0"] + #[inline(always)] + pub fn per0(&self) -> PER0_R { + PER0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1"] + #[inline(always)] + pub fn per1(&self) -> PER1_R { + PER1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2"] + #[inline(always)] + pub fn per2(&self) -> PER2_R { + PER2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3"] + #[inline(always)] + pub fn per3(&self) -> PER3_R { + PER3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4"] + #[inline(always)] + pub fn per4(&self) -> PER4_R { + PER4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5"] + #[inline(always)] + pub fn per5(&self) -> PER5_R { + PER5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6"] + #[inline(always)] + pub fn per6(&self) -> PER6_R { + PER6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7"] + #[inline(always)] + pub fn per7(&self) -> PER7_R { + PER7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Compare 0"] + #[inline(always)] + pub fn cmp0(&self) -> CMP0_R { + CMP0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0"] + #[inline(always)] + pub fn per0(&mut self) -> PER0_W { + PER0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1"] + #[inline(always)] + pub fn per1(&mut self) -> PER1_W { + PER1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2"] + #[inline(always)] + pub fn per2(&mut self) -> PER2_W { + PER2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3"] + #[inline(always)] + pub fn per3(&mut self) -> PER3_W { + PER3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4"] + #[inline(always)] + pub fn per4(&mut self) -> PER4_W { + PER4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5"] + #[inline(always)] + pub fn per5(&mut self) -> PER5_W { + PER5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6"] + #[inline(always)] + pub fn per6(&mut self) -> PER6_W { + PER6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7"] + #[inline(always)] + pub fn per7(&mut self) -> PER7_W { + PER7_W { w: self } + } + #[doc = "Bit 8 - Compare 0"] + #[inline(always)] + pub fn cmp0(&mut self) -> CMP0_W { + CMP0_W { w: self } + } + #[doc = "Bit 15 - Overflow"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE0 Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/rtc/mode0/syncbusy.rs b/pac/atsamc21e/src/rtc/mode0/syncbusy.rs new file mode 100644 index 000000000000..518dea115a18 --- /dev/null +++ b/pac/atsamc21e/src/rtc/mode0/syncbusy.rs @@ -0,0 +1,153 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - Enable Bit Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FREQCORR` reader - FREQCORR Register Busy"] +pub struct FREQCORR_R(crate::FieldReader); +impl FREQCORR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FREQCORR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FREQCORR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` reader - COUNT Register Busy"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP0` reader - COMP 0 Register Busy"] +pub struct COMP0_R(crate::FieldReader); +impl COMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNTSYNC` reader - Count Read Synchronization Enable Bit Busy"] +pub struct COUNTSYNC_R(crate::FieldReader); +impl COUNTSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNTSYNC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNTSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable Bit Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - FREQCORR Register Busy"] + #[inline(always)] + pub fn freqcorr(&self) -> FREQCORR_R { + FREQCORR_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - COUNT Register Busy"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 5 - COMP 0 Register Busy"] + #[inline(always)] + pub fn comp0(&self) -> COMP0_R { + COMP0_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 15 - Count Read Synchronization Enable Bit Busy"] + #[inline(always)] + pub fn countsync(&self) -> COUNTSYNC_R { + COUNTSYNC_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +#[doc = "MODE0 Synchronization Busy Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/rtc/mode1.rs b/pac/atsamc21e/src/rtc/mode1.rs new file mode 100644 index 000000000000..9ea1bc17497c --- /dev/null +++ b/pac/atsamc21e/src/rtc/mode1.rs @@ -0,0 +1,44 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "MODE1 Control A"] +pub mod ctrla; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "MODE1 Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "MODE1 Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "MODE1 Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "MODE1 Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "MODE1 Synchronization Busy Status"] +pub mod syncbusy; +#[doc = "FREQCORR register accessor: an alias for `Reg`"] +pub type FREQCORR = crate::Reg; +#[doc = "Frequency Correction"] +pub mod freqcorr; +#[doc = "COUNT register accessor: an alias for `Reg`"] +pub type COUNT = crate::Reg; +#[doc = "MODE1 Counter Value"] +pub mod count; +#[doc = "PER register accessor: an alias for `Reg`"] +pub type PER = crate::Reg; +#[doc = "MODE1 Counter Period"] +pub mod per; +#[doc = "COMP register accessor: an alias for `Reg`"] +pub type COMP = crate::Reg; +#[doc = "MODE1 Compare n Value"] +pub mod comp; diff --git a/pac/atsamc21e/src/rtc/mode1/comp.rs b/pac/atsamc21e/src/rtc/mode1/comp.rs new file mode 100644 index 000000000000..6935385840f1 --- /dev/null +++ b/pac/atsamc21e/src/rtc/mode1/comp.rs @@ -0,0 +1,104 @@ +#[doc = "Register `COMP[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COMP[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COMP` reader - Compare Value"] +pub struct COMP_R(crate::FieldReader); +impl COMP_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + COMP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP` writer - Compare Value"] +pub struct COMP_W<'a> { + w: &'a mut W, +} +impl<'a> COMP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Compare Value"] + #[inline(always)] + pub fn comp(&self) -> COMP_R { + COMP_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Compare Value"] + #[inline(always)] + pub fn comp(&mut self) -> COMP_W { + COMP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Compare n Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [comp](index.html) module"] +pub struct COMP_SPEC; +impl crate::RegisterSpec for COMP_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [comp::R](R) reader structure"] +impl crate::Readable for COMP_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [comp::W](W) writer structure"] +impl crate::Writable for COMP_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COMP[%s] +to value 0"] +impl crate::Resettable for COMP_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/rtc/mode1/count.rs b/pac/atsamc21e/src/rtc/mode1/count.rs new file mode 100644 index 000000000000..2c41937b189c --- /dev/null +++ b/pac/atsamc21e/src/rtc/mode1/count.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Counter Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count](index.html) module"] +pub struct COUNT_SPEC; +impl crate::RegisterSpec for COUNT_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [count::R](R) reader structure"] +impl crate::Readable for COUNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count::W](W) writer structure"] +impl crate::Writable for COUNT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT to value 0"] +impl crate::Resettable for COUNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/rtc/mode1/ctrla.rs b/pac/atsamc21e/src/rtc/mode1/ctrla.rs new file mode 100644 index 000000000000..6e3e2042a9c4 --- /dev/null +++ b/pac/atsamc21e/src/rtc/mode1/ctrla.rs @@ -0,0 +1,522 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: Mode 0: 32-bit Counter"] + COUNT32 = 0, + #[doc = "1: Mode 1: 16-bit Counter"] + COUNT16 = 1, + #[doc = "2: Mode 2: Clock/Calendar"] + CLOCK = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::COUNT32), + 1 => Some(MODE_A::COUNT16), + 2 => Some(MODE_A::CLOCK), + _ => None, + } + } + #[doc = "Checks if the value of the field is `COUNT32`"] + #[inline(always)] + pub fn is_count32(&self) -> bool { + **self == MODE_A::COUNT32 + } + #[doc = "Checks if the value of the field is `COUNT16`"] + #[inline(always)] + pub fn is_count16(&self) -> bool { + **self == MODE_A::COUNT16 + } + #[doc = "Checks if the value of the field is `CLOCK`"] + #[inline(always)] + pub fn is_clock(&self) -> bool { + **self == MODE_A::CLOCK + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Mode 0: 32-bit Counter"] + #[inline(always)] + pub fn count32(self) -> &'a mut W { + self.variant(MODE_A::COUNT32) + } + #[doc = "Mode 1: 16-bit Counter"] + #[inline(always)] + pub fn count16(self) -> &'a mut W { + self.variant(MODE_A::COUNT16) + } + #[doc = "Mode 2: Clock/Calendar"] + #[inline(always)] + pub fn clock(self) -> &'a mut W { + self.variant(MODE_A::CLOCK) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u16 & 0x03) << 2); + self.w + } +} +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: CLK_RTC_CNT = GCLK_RTC/1"] + OFF = 0, + #[doc = "1: CLK_RTC_CNT = GCLK_RTC/1"] + DIV1 = 1, + #[doc = "2: CLK_RTC_CNT = GCLK_RTC/2"] + DIV2 = 2, + #[doc = "3: CLK_RTC_CNT = GCLK_RTC/4"] + DIV4 = 3, + #[doc = "4: CLK_RTC_CNT = GCLK_RTC/8"] + DIV8 = 4, + #[doc = "5: CLK_RTC_CNT = GCLK_RTC/16"] + DIV16 = 5, + #[doc = "6: CLK_RTC_CNT = GCLK_RTC/32"] + DIV32 = 6, + #[doc = "7: CLK_RTC_CNT = GCLK_RTC/64"] + DIV64 = 7, + #[doc = "8: CLK_RTC_CNT = GCLK_RTC/128"] + DIV128 = 8, + #[doc = "9: CLK_RTC_CNT = GCLK_RTC/256"] + DIV256 = 9, + #[doc = "10: CLK_RTC_CNT = GCLK_RTC/512"] + DIV512 = 10, + #[doc = "11: CLK_RTC_CNT = GCLK_RTC/1024"] + DIV1024 = 11, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCALER_A::OFF), + 1 => Some(PRESCALER_A::DIV1), + 2 => Some(PRESCALER_A::DIV2), + 3 => Some(PRESCALER_A::DIV4), + 4 => Some(PRESCALER_A::DIV8), + 5 => Some(PRESCALER_A::DIV16), + 6 => Some(PRESCALER_A::DIV32), + 7 => Some(PRESCALER_A::DIV64), + 8 => Some(PRESCALER_A::DIV128), + 9 => Some(PRESCALER_A::DIV256), + 10 => Some(PRESCALER_A::DIV512), + 11 => Some(PRESCALER_A::DIV1024), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == PRESCALER_A::OFF + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == PRESCALER_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == PRESCALER_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == PRESCALER_A::DIV128 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV512`"] + #[inline(always)] + pub fn is_div512(&self) -> bool { + **self == PRESCALER_A::DIV512 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PRESCALER_A::DIV1024 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(PRESCALER_A::OFF) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV32) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV128) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/512"] + #[inline(always)] + pub fn div512(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV512) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 8)) | ((value as u16 & 0x0f) << 8); + self.w + } +} +#[doc = "Field `COUNTSYNC` reader - Count Read Synchronization Enable"] +pub struct COUNTSYNC_R(crate::FieldReader); +impl COUNTSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNTSYNC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNTSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNTSYNC` writer - Count Read Synchronization Enable"] +pub struct COUNTSYNC_W<'a> { + w: &'a mut W, +} +impl<'a> COUNTSYNC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:3 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bits 8:11 - Prescaler"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 15 - Count Read Synchronization Enable"] + #[inline(always)] + pub fn countsync(&self) -> COUNTSYNC_R { + COUNTSYNC_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:3 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bits 8:11 - Prescaler"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Bit 15 - Count Read Synchronization Enable"] + #[inline(always)] + pub fn countsync(&mut self) -> COUNTSYNC_W { + COUNTSYNC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/rtc/mode1/dbgctrl.rs b/pac/atsamc21e/src/rtc/mode1/dbgctrl.rs new file mode 100644 index 000000000000..0383e70d0429 --- /dev/null +++ b/pac/atsamc21e/src/rtc/mode1/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Run During Debug"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Run During Debug"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/rtc/mode1/evctrl.rs b/pac/atsamc21e/src/rtc/mode1/evctrl.rs new file mode 100644 index 000000000000..e15624f828c7 --- /dev/null +++ b/pac/atsamc21e/src/rtc/mode1/evctrl.rs @@ -0,0 +1,583 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PEREO0` reader - Periodic Interval 0 Event Output Enable"] +pub struct PEREO0_R(crate::FieldReader); +impl PEREO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO0` writer - Periodic Interval 0 Event Output Enable"] +pub struct PEREO0_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `PEREO1` reader - Periodic Interval 1 Event Output Enable"] +pub struct PEREO1_R(crate::FieldReader); +impl PEREO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO1` writer - Periodic Interval 1 Event Output Enable"] +pub struct PEREO1_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PEREO2` reader - Periodic Interval 2 Event Output Enable"] +pub struct PEREO2_R(crate::FieldReader); +impl PEREO2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO2` writer - Periodic Interval 2 Event Output Enable"] +pub struct PEREO2_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PEREO3` reader - Periodic Interval 3 Event Output Enable"] +pub struct PEREO3_R(crate::FieldReader); +impl PEREO3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO3` writer - Periodic Interval 3 Event Output Enable"] +pub struct PEREO3_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PEREO4` reader - Periodic Interval 4 Event Output Enable"] +pub struct PEREO4_R(crate::FieldReader); +impl PEREO4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO4` writer - Periodic Interval 4 Event Output Enable"] +pub struct PEREO4_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PEREO5` reader - Periodic Interval 5 Event Output Enable"] +pub struct PEREO5_R(crate::FieldReader); +impl PEREO5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO5` writer - Periodic Interval 5 Event Output Enable"] +pub struct PEREO5_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PEREO6` reader - Periodic Interval 6 Event Output Enable"] +pub struct PEREO6_R(crate::FieldReader); +impl PEREO6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO6` writer - Periodic Interval 6 Event Output Enable"] +pub struct PEREO6_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PEREO7` reader - Periodic Interval 7 Event Output Enable"] +pub struct PEREO7_R(crate::FieldReader); +impl PEREO7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO7` writer - Periodic Interval 7 Event Output Enable"] +pub struct PEREO7_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CMPEO0` reader - Compare 0 Event Output Enable"] +pub struct CMPEO0_R(crate::FieldReader); +impl CMPEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMPEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMPEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMPEO0` writer - Compare 0 Event Output Enable"] +pub struct CMPEO0_W<'a> { + w: &'a mut W, +} +impl<'a> CMPEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `CMPEO1` reader - Compare 1 Event Output Enable"] +pub struct CMPEO1_R(crate::FieldReader); +impl CMPEO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMPEO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMPEO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMPEO1` writer - Compare 1 Event Output Enable"] +pub struct CMPEO1_W<'a> { + w: &'a mut W, +} +impl<'a> CMPEO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `OVFEO` reader - Overflow Event Output Enable"] +pub struct OVFEO_R(crate::FieldReader); +impl OVFEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVFEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVFEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVFEO` writer - Overflow Event Output Enable"] +pub struct OVFEO_W<'a> { + w: &'a mut W, +} +impl<'a> OVFEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Event Output Enable"] + #[inline(always)] + pub fn pereo0(&self) -> PEREO0_R { + PEREO0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Event Output Enable"] + #[inline(always)] + pub fn pereo1(&self) -> PEREO1_R { + PEREO1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Event Output Enable"] + #[inline(always)] + pub fn pereo2(&self) -> PEREO2_R { + PEREO2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Event Output Enable"] + #[inline(always)] + pub fn pereo3(&self) -> PEREO3_R { + PEREO3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Event Output Enable"] + #[inline(always)] + pub fn pereo4(&self) -> PEREO4_R { + PEREO4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Event Output Enable"] + #[inline(always)] + pub fn pereo5(&self) -> PEREO5_R { + PEREO5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Event Output Enable"] + #[inline(always)] + pub fn pereo6(&self) -> PEREO6_R { + PEREO6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Event Output Enable"] + #[inline(always)] + pub fn pereo7(&self) -> PEREO7_R { + PEREO7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Compare 0 Event Output Enable"] + #[inline(always)] + pub fn cmpeo0(&self) -> CMPEO0_R { + CMPEO0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Compare 1 Event Output Enable"] + #[inline(always)] + pub fn cmpeo1(&self) -> CMPEO1_R { + CMPEO1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&self) -> OVFEO_R { + OVFEO_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Event Output Enable"] + #[inline(always)] + pub fn pereo0(&mut self) -> PEREO0_W { + PEREO0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1 Event Output Enable"] + #[inline(always)] + pub fn pereo1(&mut self) -> PEREO1_W { + PEREO1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2 Event Output Enable"] + #[inline(always)] + pub fn pereo2(&mut self) -> PEREO2_W { + PEREO2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3 Event Output Enable"] + #[inline(always)] + pub fn pereo3(&mut self) -> PEREO3_W { + PEREO3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4 Event Output Enable"] + #[inline(always)] + pub fn pereo4(&mut self) -> PEREO4_W { + PEREO4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5 Event Output Enable"] + #[inline(always)] + pub fn pereo5(&mut self) -> PEREO5_W { + PEREO5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6 Event Output Enable"] + #[inline(always)] + pub fn pereo6(&mut self) -> PEREO6_W { + PEREO6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7 Event Output Enable"] + #[inline(always)] + pub fn pereo7(&mut self) -> PEREO7_W { + PEREO7_W { w: self } + } + #[doc = "Bit 8 - Compare 0 Event Output Enable"] + #[inline(always)] + pub fn cmpeo0(&mut self) -> CMPEO0_W { + CMPEO0_W { w: self } + } + #[doc = "Bit 9 - Compare 1 Event Output Enable"] + #[inline(always)] + pub fn cmpeo1(&mut self) -> CMPEO1_W { + CMPEO1_W { w: self } + } + #[doc = "Bit 15 - Overflow Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&mut self) -> OVFEO_W { + OVFEO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/rtc/mode1/freqcorr.rs b/pac/atsamc21e/src/rtc/mode1/freqcorr.rs new file mode 100644 index 000000000000..043ba6f88eb2 --- /dev/null +++ b/pac/atsamc21e/src/rtc/mode1/freqcorr.rs @@ -0,0 +1,150 @@ +#[doc = "Register `FREQCORR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FREQCORR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `VALUE` reader - Correction Value"] +pub struct VALUE_R(crate::FieldReader); +impl VALUE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + VALUE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VALUE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VALUE` writer - Correction Value"] +pub struct VALUE_W<'a> { + w: &'a mut W, +} +impl<'a> VALUE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x7f) | (value as u8 & 0x7f); + self.w + } +} +#[doc = "Field `SIGN` reader - Correction Sign"] +pub struct SIGN_R(crate::FieldReader); +impl SIGN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SIGN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SIGN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SIGN` writer - Correction Sign"] +pub struct SIGN_W<'a> { + w: &'a mut W, +} +impl<'a> SIGN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bits 0:6 - Correction Value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bit 7 - Correction Sign"] + #[inline(always)] + pub fn sign(&self) -> SIGN_R { + SIGN_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:6 - Correction Value"] + #[inline(always)] + pub fn value(&mut self) -> VALUE_W { + VALUE_W { w: self } + } + #[doc = "Bit 7 - Correction Sign"] + #[inline(always)] + pub fn sign(&mut self) -> SIGN_W { + SIGN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Frequency Correction\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [freqcorr](index.html) module"] +pub struct FREQCORR_SPEC; +impl crate::RegisterSpec for FREQCORR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [freqcorr::R](R) reader structure"] +impl crate::Readable for FREQCORR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [freqcorr::W](W) writer structure"] +impl crate::Writable for FREQCORR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets FREQCORR to value 0"] +impl crate::Resettable for FREQCORR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/rtc/mode1/intenclr.rs b/pac/atsamc21e/src/rtc/mode1/intenclr.rs new file mode 100644 index 000000000000..d3fc5b3df34b --- /dev/null +++ b/pac/atsamc21e/src/rtc/mode1/intenclr.rs @@ -0,0 +1,583 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER0` reader - Periodic Interval 0 Interrupt Enable"] +pub struct PER0_R(crate::FieldReader); +impl PER0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER0` writer - Periodic Interval 0 Interrupt Enable"] +pub struct PER0_W<'a> { + w: &'a mut W, +} +impl<'a> PER0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PER1` reader - Periodic Interval 1 Interrupt Enable"] +pub struct PER1_R(crate::FieldReader); +impl PER1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER1` writer - Periodic Interval 1 Interrupt Enable"] +pub struct PER1_W<'a> { + w: &'a mut W, +} +impl<'a> PER1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PER2` reader - Periodic Interval 2 Interrupt Enable"] +pub struct PER2_R(crate::FieldReader); +impl PER2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER2` writer - Periodic Interval 2 Interrupt Enable"] +pub struct PER2_W<'a> { + w: &'a mut W, +} +impl<'a> PER2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PER3` reader - Periodic Interval 3 Interrupt Enable"] +pub struct PER3_R(crate::FieldReader); +impl PER3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER3` writer - Periodic Interval 3 Interrupt Enable"] +pub struct PER3_W<'a> { + w: &'a mut W, +} +impl<'a> PER3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PER4` reader - Periodic Interval 4 Interrupt Enable"] +pub struct PER4_R(crate::FieldReader); +impl PER4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER4` writer - Periodic Interval 4 Interrupt Enable"] +pub struct PER4_W<'a> { + w: &'a mut W, +} +impl<'a> PER4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PER5` reader - Periodic Interval 5 Interrupt Enable"] +pub struct PER5_R(crate::FieldReader); +impl PER5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER5` writer - Periodic Interval 5 Interrupt Enable"] +pub struct PER5_W<'a> { + w: &'a mut W, +} +impl<'a> PER5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PER6` reader - Periodic Interval 6 Interrupt Enable"] +pub struct PER6_R(crate::FieldReader); +impl PER6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER6` writer - Periodic Interval 6 Interrupt Enable"] +pub struct PER6_W<'a> { + w: &'a mut W, +} +impl<'a> PER6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PER7` reader - Periodic Interval 7 Interrupt Enable"] +pub struct PER7_R(crate::FieldReader); +impl PER7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER7` writer - Periodic Interval 7 Interrupt Enable"] +pub struct PER7_W<'a> { + w: &'a mut W, +} +impl<'a> PER7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CMP0` reader - Compare 0 Interrupt Enable"] +pub struct CMP0_R(crate::FieldReader); +impl CMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP0` writer - Compare 0 Interrupt Enable"] +pub struct CMP0_W<'a> { + w: &'a mut W, +} +impl<'a> CMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `CMP1` reader - Compare 1 Interrupt Enable"] +pub struct CMP1_R(crate::FieldReader); +impl CMP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP1` writer - Compare 1 Interrupt Enable"] +pub struct CMP1_W<'a> { + w: &'a mut W, +} +impl<'a> CMP1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + pub fn per0(&self) -> PER0_R { + PER0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + pub fn per1(&self) -> PER1_R { + PER1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + pub fn per2(&self) -> PER2_R { + PER2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + pub fn per3(&self) -> PER3_R { + PER3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + pub fn per4(&self) -> PER4_R { + PER4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + pub fn per5(&self) -> PER5_R { + PER5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + pub fn per6(&self) -> PER6_R { + PER6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + pub fn per7(&self) -> PER7_R { + PER7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&self) -> CMP0_R { + CMP0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Compare 1 Interrupt Enable"] + #[inline(always)] + pub fn cmp1(&self) -> CMP1_R { + CMP1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + pub fn per0(&mut self) -> PER0_W { + PER0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + pub fn per1(&mut self) -> PER1_W { + PER1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + pub fn per2(&mut self) -> PER2_W { + PER2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + pub fn per3(&mut self) -> PER3_W { + PER3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + pub fn per4(&mut self) -> PER4_W { + PER4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + pub fn per5(&mut self) -> PER5_W { + PER5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + pub fn per6(&mut self) -> PER6_W { + PER6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + pub fn per7(&mut self) -> PER7_W { + PER7_W { w: self } + } + #[doc = "Bit 8 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&mut self) -> CMP0_W { + CMP0_W { w: self } + } + #[doc = "Bit 9 - Compare 1 Interrupt Enable"] + #[inline(always)] + pub fn cmp1(&mut self) -> CMP1_W { + CMP1_W { w: self } + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/rtc/mode1/intenset.rs b/pac/atsamc21e/src/rtc/mode1/intenset.rs new file mode 100644 index 000000000000..074cb377926a --- /dev/null +++ b/pac/atsamc21e/src/rtc/mode1/intenset.rs @@ -0,0 +1,583 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER0` reader - Periodic Interval 0 Interrupt Enable"] +pub struct PER0_R(crate::FieldReader); +impl PER0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER0` writer - Periodic Interval 0 Interrupt Enable"] +pub struct PER0_W<'a> { + w: &'a mut W, +} +impl<'a> PER0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PER1` reader - Periodic Interval 1 Interrupt Enable"] +pub struct PER1_R(crate::FieldReader); +impl PER1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER1` writer - Periodic Interval 1 Interrupt Enable"] +pub struct PER1_W<'a> { + w: &'a mut W, +} +impl<'a> PER1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PER2` reader - Periodic Interval 2 Interrupt Enable"] +pub struct PER2_R(crate::FieldReader); +impl PER2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER2` writer - Periodic Interval 2 Interrupt Enable"] +pub struct PER2_W<'a> { + w: &'a mut W, +} +impl<'a> PER2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PER3` reader - Periodic Interval 3 Interrupt Enable"] +pub struct PER3_R(crate::FieldReader); +impl PER3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER3` writer - Periodic Interval 3 Interrupt Enable"] +pub struct PER3_W<'a> { + w: &'a mut W, +} +impl<'a> PER3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PER4` reader - Periodic Interval 4 Interrupt Enable"] +pub struct PER4_R(crate::FieldReader); +impl PER4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER4` writer - Periodic Interval 4 Interrupt Enable"] +pub struct PER4_W<'a> { + w: &'a mut W, +} +impl<'a> PER4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PER5` reader - Periodic Interval 5 Interrupt Enable"] +pub struct PER5_R(crate::FieldReader); +impl PER5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER5` writer - Periodic Interval 5 Interrupt Enable"] +pub struct PER5_W<'a> { + w: &'a mut W, +} +impl<'a> PER5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PER6` reader - Periodic Interval 6 Interrupt Enable"] +pub struct PER6_R(crate::FieldReader); +impl PER6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER6` writer - Periodic Interval 6 Interrupt Enable"] +pub struct PER6_W<'a> { + w: &'a mut W, +} +impl<'a> PER6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PER7` reader - Periodic Interval 7 Interrupt Enable"] +pub struct PER7_R(crate::FieldReader); +impl PER7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER7` writer - Periodic Interval 7 Interrupt Enable"] +pub struct PER7_W<'a> { + w: &'a mut W, +} +impl<'a> PER7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CMP0` reader - Compare 0 Interrupt Enable"] +pub struct CMP0_R(crate::FieldReader); +impl CMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP0` writer - Compare 0 Interrupt Enable"] +pub struct CMP0_W<'a> { + w: &'a mut W, +} +impl<'a> CMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `CMP1` reader - Compare 1 Interrupt Enable"] +pub struct CMP1_R(crate::FieldReader); +impl CMP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP1` writer - Compare 1 Interrupt Enable"] +pub struct CMP1_W<'a> { + w: &'a mut W, +} +impl<'a> CMP1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + pub fn per0(&self) -> PER0_R { + PER0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + pub fn per1(&self) -> PER1_R { + PER1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + pub fn per2(&self) -> PER2_R { + PER2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + pub fn per3(&self) -> PER3_R { + PER3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + pub fn per4(&self) -> PER4_R { + PER4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + pub fn per5(&self) -> PER5_R { + PER5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + pub fn per6(&self) -> PER6_R { + PER6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + pub fn per7(&self) -> PER7_R { + PER7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&self) -> CMP0_R { + CMP0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Compare 1 Interrupt Enable"] + #[inline(always)] + pub fn cmp1(&self) -> CMP1_R { + CMP1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + pub fn per0(&mut self) -> PER0_W { + PER0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + pub fn per1(&mut self) -> PER1_W { + PER1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + pub fn per2(&mut self) -> PER2_W { + PER2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + pub fn per3(&mut self) -> PER3_W { + PER3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + pub fn per4(&mut self) -> PER4_W { + PER4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + pub fn per5(&mut self) -> PER5_W { + PER5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + pub fn per6(&mut self) -> PER6_W { + PER6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + pub fn per7(&mut self) -> PER7_W { + PER7_W { w: self } + } + #[doc = "Bit 8 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&mut self) -> CMP0_W { + CMP0_W { w: self } + } + #[doc = "Bit 9 - Compare 1 Interrupt Enable"] + #[inline(always)] + pub fn cmp1(&mut self) -> CMP1_W { + CMP1_W { w: self } + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/rtc/mode1/intflag.rs b/pac/atsamc21e/src/rtc/mode1/intflag.rs new file mode 100644 index 000000000000..25bce956f46b --- /dev/null +++ b/pac/atsamc21e/src/rtc/mode1/intflag.rs @@ -0,0 +1,583 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER0` reader - Periodic Interval 0"] +pub struct PER0_R(crate::FieldReader); +impl PER0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER0` writer - Periodic Interval 0"] +pub struct PER0_W<'a> { + w: &'a mut W, +} +impl<'a> PER0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PER1` reader - Periodic Interval 1"] +pub struct PER1_R(crate::FieldReader); +impl PER1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER1` writer - Periodic Interval 1"] +pub struct PER1_W<'a> { + w: &'a mut W, +} +impl<'a> PER1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PER2` reader - Periodic Interval 2"] +pub struct PER2_R(crate::FieldReader); +impl PER2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER2` writer - Periodic Interval 2"] +pub struct PER2_W<'a> { + w: &'a mut W, +} +impl<'a> PER2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PER3` reader - Periodic Interval 3"] +pub struct PER3_R(crate::FieldReader); +impl PER3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER3` writer - Periodic Interval 3"] +pub struct PER3_W<'a> { + w: &'a mut W, +} +impl<'a> PER3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PER4` reader - Periodic Interval 4"] +pub struct PER4_R(crate::FieldReader); +impl PER4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER4` writer - Periodic Interval 4"] +pub struct PER4_W<'a> { + w: &'a mut W, +} +impl<'a> PER4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PER5` reader - Periodic Interval 5"] +pub struct PER5_R(crate::FieldReader); +impl PER5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER5` writer - Periodic Interval 5"] +pub struct PER5_W<'a> { + w: &'a mut W, +} +impl<'a> PER5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PER6` reader - Periodic Interval 6"] +pub struct PER6_R(crate::FieldReader); +impl PER6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER6` writer - Periodic Interval 6"] +pub struct PER6_W<'a> { + w: &'a mut W, +} +impl<'a> PER6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PER7` reader - Periodic Interval 7"] +pub struct PER7_R(crate::FieldReader); +impl PER7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER7` writer - Periodic Interval 7"] +pub struct PER7_W<'a> { + w: &'a mut W, +} +impl<'a> PER7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CMP0` reader - Compare 0"] +pub struct CMP0_R(crate::FieldReader); +impl CMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP0` writer - Compare 0"] +pub struct CMP0_W<'a> { + w: &'a mut W, +} +impl<'a> CMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `CMP1` reader - Compare 1"] +pub struct CMP1_R(crate::FieldReader); +impl CMP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP1` writer - Compare 1"] +pub struct CMP1_W<'a> { + w: &'a mut W, +} +impl<'a> CMP1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0"] + #[inline(always)] + pub fn per0(&self) -> PER0_R { + PER0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1"] + #[inline(always)] + pub fn per1(&self) -> PER1_R { + PER1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2"] + #[inline(always)] + pub fn per2(&self) -> PER2_R { + PER2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3"] + #[inline(always)] + pub fn per3(&self) -> PER3_R { + PER3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4"] + #[inline(always)] + pub fn per4(&self) -> PER4_R { + PER4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5"] + #[inline(always)] + pub fn per5(&self) -> PER5_R { + PER5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6"] + #[inline(always)] + pub fn per6(&self) -> PER6_R { + PER6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7"] + #[inline(always)] + pub fn per7(&self) -> PER7_R { + PER7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Compare 0"] + #[inline(always)] + pub fn cmp0(&self) -> CMP0_R { + CMP0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Compare 1"] + #[inline(always)] + pub fn cmp1(&self) -> CMP1_R { + CMP1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0"] + #[inline(always)] + pub fn per0(&mut self) -> PER0_W { + PER0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1"] + #[inline(always)] + pub fn per1(&mut self) -> PER1_W { + PER1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2"] + #[inline(always)] + pub fn per2(&mut self) -> PER2_W { + PER2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3"] + #[inline(always)] + pub fn per3(&mut self) -> PER3_W { + PER3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4"] + #[inline(always)] + pub fn per4(&mut self) -> PER4_W { + PER4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5"] + #[inline(always)] + pub fn per5(&mut self) -> PER5_W { + PER5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6"] + #[inline(always)] + pub fn per6(&mut self) -> PER6_W { + PER6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7"] + #[inline(always)] + pub fn per7(&mut self) -> PER7_W { + PER7_W { w: self } + } + #[doc = "Bit 8 - Compare 0"] + #[inline(always)] + pub fn cmp0(&mut self) -> CMP0_W { + CMP0_W { w: self } + } + #[doc = "Bit 9 - Compare 1"] + #[inline(always)] + pub fn cmp1(&mut self) -> CMP1_W { + CMP1_W { w: self } + } + #[doc = "Bit 15 - Overflow"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/rtc/mode1/per.rs b/pac/atsamc21e/src/rtc/mode1/per.rs new file mode 100644 index 000000000000..c09b31fa30dd --- /dev/null +++ b/pac/atsamc21e/src/rtc/mode1/per.rs @@ -0,0 +1,103 @@ +#[doc = "Register `PER` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PER` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER` reader - Counter Period"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` writer - Counter Period"] +pub struct PER_W<'a> { + w: &'a mut W, +} +impl<'a> PER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Counter Period"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Counter Period"] + #[inline(always)] + pub fn per(&mut self) -> PER_W { + PER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Counter Period\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [per](index.html) module"] +pub struct PER_SPEC; +impl crate::RegisterSpec for PER_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [per::R](R) reader structure"] +impl crate::Readable for PER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [per::W](W) writer structure"] +impl crate::Writable for PER_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PER to value 0"] +impl crate::Resettable for PER_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/rtc/mode1/syncbusy.rs b/pac/atsamc21e/src/rtc/mode1/syncbusy.rs new file mode 100644 index 000000000000..b64c973bafff --- /dev/null +++ b/pac/atsamc21e/src/rtc/mode1/syncbusy.rs @@ -0,0 +1,193 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Bit Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - Enable Bit Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FREQCORR` reader - FREQCORR Register Busy"] +pub struct FREQCORR_R(crate::FieldReader); +impl FREQCORR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FREQCORR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FREQCORR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` reader - COUNT Register Busy"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` reader - PER Register Busy"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP0` reader - COMP 0 Register Busy"] +pub struct COMP0_R(crate::FieldReader); +impl COMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP1` reader - COMP 1 Register Busy"] +pub struct COMP1_R(crate::FieldReader); +impl COMP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNTSYNC` reader - Count Read Synchronization Enable Bit Busy"] +pub struct COUNTSYNC_R(crate::FieldReader); +impl COUNTSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNTSYNC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNTSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Bit Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable Bit Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - FREQCORR Register Busy"] + #[inline(always)] + pub fn freqcorr(&self) -> FREQCORR_R { + FREQCORR_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - COUNT Register Busy"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - PER Register Busy"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - COMP 0 Register Busy"] + #[inline(always)] + pub fn comp0(&self) -> COMP0_R { + COMP0_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - COMP 1 Register Busy"] + #[inline(always)] + pub fn comp1(&self) -> COMP1_R { + COMP1_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 15 - Count Read Synchronization Enable Bit Busy"] + #[inline(always)] + pub fn countsync(&self) -> COUNTSYNC_R { + COUNTSYNC_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +#[doc = "MODE1 Synchronization Busy Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/rtc/mode2.rs b/pac/atsamc21e/src/rtc/mode2.rs new file mode 100644 index 000000000000..b0bc13e81dbc --- /dev/null +++ b/pac/atsamc21e/src/rtc/mode2.rs @@ -0,0 +1,44 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "MODE2 Control A"] +pub mod ctrla; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "MODE2 Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "MODE2 Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "MODE2 Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "MODE2 Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "MODE2 Synchronization Busy Status"] +pub mod syncbusy; +#[doc = "FREQCORR register accessor: an alias for `Reg`"] +pub type FREQCORR = crate::Reg; +#[doc = "Frequency Correction"] +pub mod freqcorr; +#[doc = "CLOCK register accessor: an alias for `Reg`"] +pub type CLOCK = crate::Reg; +#[doc = "MODE2 Clock Value"] +pub mod clock; +#[doc = "ALARM register accessor: an alias for `Reg`"] +pub type ALARM = crate::Reg; +#[doc = "MODE2_ALARM Alarm n Value"] +pub mod alarm; +#[doc = "MASK register accessor: an alias for `Reg`"] +pub type MASK = crate::Reg; +#[doc = "MODE2_ALARM Alarm n Mask"] +pub mod mask; diff --git a/pac/atsamc21e/src/rtc/mode2/alarm.rs b/pac/atsamc21e/src/rtc/mode2/alarm.rs new file mode 100644 index 000000000000..1242477ea69f --- /dev/null +++ b/pac/atsamc21e/src/rtc/mode2/alarm.rs @@ -0,0 +1,337 @@ +#[doc = "Register `ALARM` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ALARM` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SECOND` reader - Second"] +pub struct SECOND_R(crate::FieldReader); +impl SECOND_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SECOND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SECOND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SECOND` writer - Second"] +pub struct SECOND_W<'a> { + w: &'a mut W, +} +impl<'a> SECOND_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +#[doc = "Field `MINUTE` reader - Minute"] +pub struct MINUTE_R(crate::FieldReader); +impl MINUTE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MINUTE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MINUTE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MINUTE` writer - Minute"] +pub struct MINUTE_W<'a> { + w: &'a mut W, +} +impl<'a> MINUTE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 6)) | ((value as u32 & 0x3f) << 6); + self.w + } +} +#[doc = "Hour\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum HOUR_A { + #[doc = "0: Morning hour"] + AM = 0, + #[doc = "16: Afternoon hour"] + PM = 16, +} +impl From for u8 { + #[inline(always)] + fn from(variant: HOUR_A) -> Self { + variant as _ + } +} +#[doc = "Field `HOUR` reader - Hour"] +pub struct HOUR_R(crate::FieldReader); +impl HOUR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + HOUR_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(HOUR_A::AM), + 16 => Some(HOUR_A::PM), + _ => None, + } + } + #[doc = "Checks if the value of the field is `AM`"] + #[inline(always)] + pub fn is_am(&self) -> bool { + **self == HOUR_A::AM + } + #[doc = "Checks if the value of the field is `PM`"] + #[inline(always)] + pub fn is_pm(&self) -> bool { + **self == HOUR_A::PM + } +} +impl core::ops::Deref for HOUR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HOUR` writer - Hour"] +pub struct HOUR_W<'a> { + w: &'a mut W, +} +impl<'a> HOUR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: HOUR_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Morning hour"] + #[inline(always)] + pub fn am(self) -> &'a mut W { + self.variant(HOUR_A::AM) + } + #[doc = "Afternoon hour"] + #[inline(always)] + pub fn pm(self) -> &'a mut W { + self.variant(HOUR_A::PM) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 12)) | ((value as u32 & 0x1f) << 12); + self.w + } +} +#[doc = "Field `DAY` reader - Day"] +pub struct DAY_R(crate::FieldReader); +impl DAY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DAY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DAY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DAY` writer - Day"] +pub struct DAY_W<'a> { + w: &'a mut W, +} +impl<'a> DAY_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 17)) | ((value as u32 & 0x1f) << 17); + self.w + } +} +#[doc = "Field `MONTH` reader - Month"] +pub struct MONTH_R(crate::FieldReader); +impl MONTH_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MONTH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MONTH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MONTH` writer - Month"] +pub struct MONTH_W<'a> { + w: &'a mut W, +} +impl<'a> MONTH_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 22)) | ((value as u32 & 0x0f) << 22); + self.w + } +} +#[doc = "Field `YEAR` reader - Year"] +pub struct YEAR_R(crate::FieldReader); +impl YEAR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + YEAR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for YEAR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `YEAR` writer - Year"] +pub struct YEAR_W<'a> { + w: &'a mut W, +} +impl<'a> YEAR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 26)) | ((value as u32 & 0x3f) << 26); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Second"] + #[inline(always)] + pub fn second(&self) -> SECOND_R { + SECOND_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:11 - Minute"] + #[inline(always)] + pub fn minute(&self) -> MINUTE_R { + MINUTE_R::new(((self.bits >> 6) & 0x3f) as u8) + } + #[doc = "Bits 12:16 - Hour"] + #[inline(always)] + pub fn hour(&self) -> HOUR_R { + HOUR_R::new(((self.bits >> 12) & 0x1f) as u8) + } + #[doc = "Bits 17:21 - Day"] + #[inline(always)] + pub fn day(&self) -> DAY_R { + DAY_R::new(((self.bits >> 17) & 0x1f) as u8) + } + #[doc = "Bits 22:25 - Month"] + #[inline(always)] + pub fn month(&self) -> MONTH_R { + MONTH_R::new(((self.bits >> 22) & 0x0f) as u8) + } + #[doc = "Bits 26:31 - Year"] + #[inline(always)] + pub fn year(&self) -> YEAR_R { + YEAR_R::new(((self.bits >> 26) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - Second"] + #[inline(always)] + pub fn second(&mut self) -> SECOND_W { + SECOND_W { w: self } + } + #[doc = "Bits 6:11 - Minute"] + #[inline(always)] + pub fn minute(&mut self) -> MINUTE_W { + MINUTE_W { w: self } + } + #[doc = "Bits 12:16 - Hour"] + #[inline(always)] + pub fn hour(&mut self) -> HOUR_W { + HOUR_W { w: self } + } + #[doc = "Bits 17:21 - Day"] + #[inline(always)] + pub fn day(&mut self) -> DAY_W { + DAY_W { w: self } + } + #[doc = "Bits 22:25 - Month"] + #[inline(always)] + pub fn month(&mut self) -> MONTH_W { + MONTH_W { w: self } + } + #[doc = "Bits 26:31 - Year"] + #[inline(always)] + pub fn year(&mut self) -> YEAR_W { + YEAR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2_ALARM Alarm n Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [alarm](index.html) module"] +pub struct ALARM_SPEC; +impl crate::RegisterSpec for ALARM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [alarm::R](R) reader structure"] +impl crate::Readable for ALARM_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [alarm::W](W) writer structure"] +impl crate::Writable for ALARM_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ALARM to value 0"] +impl crate::Resettable for ALARM_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/rtc/mode2/clock.rs b/pac/atsamc21e/src/rtc/mode2/clock.rs new file mode 100644 index 000000000000..3f364ff8e57b --- /dev/null +++ b/pac/atsamc21e/src/rtc/mode2/clock.rs @@ -0,0 +1,337 @@ +#[doc = "Register `CLOCK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CLOCK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SECOND` reader - Second"] +pub struct SECOND_R(crate::FieldReader); +impl SECOND_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SECOND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SECOND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SECOND` writer - Second"] +pub struct SECOND_W<'a> { + w: &'a mut W, +} +impl<'a> SECOND_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +#[doc = "Field `MINUTE` reader - Minute"] +pub struct MINUTE_R(crate::FieldReader); +impl MINUTE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MINUTE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MINUTE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MINUTE` writer - Minute"] +pub struct MINUTE_W<'a> { + w: &'a mut W, +} +impl<'a> MINUTE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 6)) | ((value as u32 & 0x3f) << 6); + self.w + } +} +#[doc = "Hour\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum HOUR_A { + #[doc = "0: AM when CLKREP in 12-hour"] + AM = 0, + #[doc = "16: PM when CLKREP in 12-hour"] + PM = 16, +} +impl From for u8 { + #[inline(always)] + fn from(variant: HOUR_A) -> Self { + variant as _ + } +} +#[doc = "Field `HOUR` reader - Hour"] +pub struct HOUR_R(crate::FieldReader); +impl HOUR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + HOUR_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(HOUR_A::AM), + 16 => Some(HOUR_A::PM), + _ => None, + } + } + #[doc = "Checks if the value of the field is `AM`"] + #[inline(always)] + pub fn is_am(&self) -> bool { + **self == HOUR_A::AM + } + #[doc = "Checks if the value of the field is `PM`"] + #[inline(always)] + pub fn is_pm(&self) -> bool { + **self == HOUR_A::PM + } +} +impl core::ops::Deref for HOUR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HOUR` writer - Hour"] +pub struct HOUR_W<'a> { + w: &'a mut W, +} +impl<'a> HOUR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: HOUR_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "AM when CLKREP in 12-hour"] + #[inline(always)] + pub fn am(self) -> &'a mut W { + self.variant(HOUR_A::AM) + } + #[doc = "PM when CLKREP in 12-hour"] + #[inline(always)] + pub fn pm(self) -> &'a mut W { + self.variant(HOUR_A::PM) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 12)) | ((value as u32 & 0x1f) << 12); + self.w + } +} +#[doc = "Field `DAY` reader - Day"] +pub struct DAY_R(crate::FieldReader); +impl DAY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DAY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DAY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DAY` writer - Day"] +pub struct DAY_W<'a> { + w: &'a mut W, +} +impl<'a> DAY_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 17)) | ((value as u32 & 0x1f) << 17); + self.w + } +} +#[doc = "Field `MONTH` reader - Month"] +pub struct MONTH_R(crate::FieldReader); +impl MONTH_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MONTH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MONTH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MONTH` writer - Month"] +pub struct MONTH_W<'a> { + w: &'a mut W, +} +impl<'a> MONTH_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 22)) | ((value as u32 & 0x0f) << 22); + self.w + } +} +#[doc = "Field `YEAR` reader - Year"] +pub struct YEAR_R(crate::FieldReader); +impl YEAR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + YEAR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for YEAR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `YEAR` writer - Year"] +pub struct YEAR_W<'a> { + w: &'a mut W, +} +impl<'a> YEAR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 26)) | ((value as u32 & 0x3f) << 26); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Second"] + #[inline(always)] + pub fn second(&self) -> SECOND_R { + SECOND_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:11 - Minute"] + #[inline(always)] + pub fn minute(&self) -> MINUTE_R { + MINUTE_R::new(((self.bits >> 6) & 0x3f) as u8) + } + #[doc = "Bits 12:16 - Hour"] + #[inline(always)] + pub fn hour(&self) -> HOUR_R { + HOUR_R::new(((self.bits >> 12) & 0x1f) as u8) + } + #[doc = "Bits 17:21 - Day"] + #[inline(always)] + pub fn day(&self) -> DAY_R { + DAY_R::new(((self.bits >> 17) & 0x1f) as u8) + } + #[doc = "Bits 22:25 - Month"] + #[inline(always)] + pub fn month(&self) -> MONTH_R { + MONTH_R::new(((self.bits >> 22) & 0x0f) as u8) + } + #[doc = "Bits 26:31 - Year"] + #[inline(always)] + pub fn year(&self) -> YEAR_R { + YEAR_R::new(((self.bits >> 26) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - Second"] + #[inline(always)] + pub fn second(&mut self) -> SECOND_W { + SECOND_W { w: self } + } + #[doc = "Bits 6:11 - Minute"] + #[inline(always)] + pub fn minute(&mut self) -> MINUTE_W { + MINUTE_W { w: self } + } + #[doc = "Bits 12:16 - Hour"] + #[inline(always)] + pub fn hour(&mut self) -> HOUR_W { + HOUR_W { w: self } + } + #[doc = "Bits 17:21 - Day"] + #[inline(always)] + pub fn day(&mut self) -> DAY_W { + DAY_W { w: self } + } + #[doc = "Bits 22:25 - Month"] + #[inline(always)] + pub fn month(&mut self) -> MONTH_W { + MONTH_W { w: self } + } + #[doc = "Bits 26:31 - Year"] + #[inline(always)] + pub fn year(&mut self) -> YEAR_W { + YEAR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2 Clock Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clock](index.html) module"] +pub struct CLOCK_SPEC; +impl crate::RegisterSpec for CLOCK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [clock::R](R) reader structure"] +impl crate::Readable for CLOCK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [clock::W](W) writer structure"] +impl crate::Writable for CLOCK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CLOCK to value 0"] +impl crate::Resettable for CLOCK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/rtc/mode2/ctrla.rs b/pac/atsamc21e/src/rtc/mode2/ctrla.rs new file mode 100644 index 000000000000..fc4bfda16bd8 --- /dev/null +++ b/pac/atsamc21e/src/rtc/mode2/ctrla.rs @@ -0,0 +1,616 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: Mode 0: 32-bit Counter"] + COUNT32 = 0, + #[doc = "1: Mode 1: 16-bit Counter"] + COUNT16 = 1, + #[doc = "2: Mode 2: Clock/Calendar"] + CLOCK = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::COUNT32), + 1 => Some(MODE_A::COUNT16), + 2 => Some(MODE_A::CLOCK), + _ => None, + } + } + #[doc = "Checks if the value of the field is `COUNT32`"] + #[inline(always)] + pub fn is_count32(&self) -> bool { + **self == MODE_A::COUNT32 + } + #[doc = "Checks if the value of the field is `COUNT16`"] + #[inline(always)] + pub fn is_count16(&self) -> bool { + **self == MODE_A::COUNT16 + } + #[doc = "Checks if the value of the field is `CLOCK`"] + #[inline(always)] + pub fn is_clock(&self) -> bool { + **self == MODE_A::CLOCK + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Mode 0: 32-bit Counter"] + #[inline(always)] + pub fn count32(self) -> &'a mut W { + self.variant(MODE_A::COUNT32) + } + #[doc = "Mode 1: 16-bit Counter"] + #[inline(always)] + pub fn count16(self) -> &'a mut W { + self.variant(MODE_A::COUNT16) + } + #[doc = "Mode 2: Clock/Calendar"] + #[inline(always)] + pub fn clock(self) -> &'a mut W { + self.variant(MODE_A::CLOCK) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u16 & 0x03) << 2); + self.w + } +} +#[doc = "Field `CLKREP` reader - Clock Representation"] +pub struct CLKREP_R(crate::FieldReader); +impl CLKREP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKREP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKREP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKREP` writer - Clock Representation"] +pub struct CLKREP_W<'a> { + w: &'a mut W, +} +impl<'a> CLKREP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `MATCHCLR` reader - Clear on Match"] +pub struct MATCHCLR_R(crate::FieldReader); +impl MATCHCLR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MATCHCLR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MATCHCLR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MATCHCLR` writer - Clear on Match"] +pub struct MATCHCLR_W<'a> { + w: &'a mut W, +} +impl<'a> MATCHCLR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: CLK_RTC_CNT = GCLK_RTC/1"] + OFF = 0, + #[doc = "1: CLK_RTC_CNT = GCLK_RTC/1"] + DIV1 = 1, + #[doc = "2: CLK_RTC_CNT = GCLK_RTC/2"] + DIV2 = 2, + #[doc = "3: CLK_RTC_CNT = GCLK_RTC/4"] + DIV4 = 3, + #[doc = "4: CLK_RTC_CNT = GCLK_RTC/8"] + DIV8 = 4, + #[doc = "5: CLK_RTC_CNT = GCLK_RTC/16"] + DIV16 = 5, + #[doc = "6: CLK_RTC_CNT = GCLK_RTC/32"] + DIV32 = 6, + #[doc = "7: CLK_RTC_CNT = GCLK_RTC/64"] + DIV64 = 7, + #[doc = "8: CLK_RTC_CNT = GCLK_RTC/128"] + DIV128 = 8, + #[doc = "9: CLK_RTC_CNT = GCLK_RTC/256"] + DIV256 = 9, + #[doc = "10: CLK_RTC_CNT = GCLK_RTC/512"] + DIV512 = 10, + #[doc = "11: CLK_RTC_CNT = GCLK_RTC/1024"] + DIV1024 = 11, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCALER_A::OFF), + 1 => Some(PRESCALER_A::DIV1), + 2 => Some(PRESCALER_A::DIV2), + 3 => Some(PRESCALER_A::DIV4), + 4 => Some(PRESCALER_A::DIV8), + 5 => Some(PRESCALER_A::DIV16), + 6 => Some(PRESCALER_A::DIV32), + 7 => Some(PRESCALER_A::DIV64), + 8 => Some(PRESCALER_A::DIV128), + 9 => Some(PRESCALER_A::DIV256), + 10 => Some(PRESCALER_A::DIV512), + 11 => Some(PRESCALER_A::DIV1024), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == PRESCALER_A::OFF + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == PRESCALER_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == PRESCALER_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == PRESCALER_A::DIV128 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV512`"] + #[inline(always)] + pub fn is_div512(&self) -> bool { + **self == PRESCALER_A::DIV512 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PRESCALER_A::DIV1024 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(PRESCALER_A::OFF) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV32) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV128) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/512"] + #[inline(always)] + pub fn div512(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV512) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 8)) | ((value as u16 & 0x0f) << 8); + self.w + } +} +#[doc = "Field `CLOCKSYNC` reader - Clock Read Synchronization Enable"] +pub struct CLOCKSYNC_R(crate::FieldReader); +impl CLOCKSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLOCKSYNC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLOCKSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLOCKSYNC` writer - Clock Read Synchronization Enable"] +pub struct CLOCKSYNC_W<'a> { + w: &'a mut W, +} +impl<'a> CLOCKSYNC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:3 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bit 6 - Clock Representation"] + #[inline(always)] + pub fn clkrep(&self) -> CLKREP_R { + CLKREP_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Clear on Match"] + #[inline(always)] + pub fn matchclr(&self) -> MATCHCLR_R { + MATCHCLR_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:11 - Prescaler"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 15 - Clock Read Synchronization Enable"] + #[inline(always)] + pub fn clocksync(&self) -> CLOCKSYNC_R { + CLOCKSYNC_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:3 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 6 - Clock Representation"] + #[inline(always)] + pub fn clkrep(&mut self) -> CLKREP_W { + CLKREP_W { w: self } + } + #[doc = "Bit 7 - Clear on Match"] + #[inline(always)] + pub fn matchclr(&mut self) -> MATCHCLR_W { + MATCHCLR_W { w: self } + } + #[doc = "Bits 8:11 - Prescaler"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Bit 15 - Clock Read Synchronization Enable"] + #[inline(always)] + pub fn clocksync(&mut self) -> CLOCKSYNC_W { + CLOCKSYNC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2 Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/rtc/mode2/dbgctrl.rs b/pac/atsamc21e/src/rtc/mode2/dbgctrl.rs new file mode 100644 index 000000000000..0383e70d0429 --- /dev/null +++ b/pac/atsamc21e/src/rtc/mode2/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Run During Debug"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Run During Debug"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/rtc/mode2/evctrl.rs b/pac/atsamc21e/src/rtc/mode2/evctrl.rs new file mode 100644 index 000000000000..17bc3da4a79e --- /dev/null +++ b/pac/atsamc21e/src/rtc/mode2/evctrl.rs @@ -0,0 +1,536 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PEREO0` reader - Periodic Interval 0 Event Output Enable"] +pub struct PEREO0_R(crate::FieldReader); +impl PEREO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO0` writer - Periodic Interval 0 Event Output Enable"] +pub struct PEREO0_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `PEREO1` reader - Periodic Interval 1 Event Output Enable"] +pub struct PEREO1_R(crate::FieldReader); +impl PEREO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO1` writer - Periodic Interval 1 Event Output Enable"] +pub struct PEREO1_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PEREO2` reader - Periodic Interval 2 Event Output Enable"] +pub struct PEREO2_R(crate::FieldReader); +impl PEREO2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO2` writer - Periodic Interval 2 Event Output Enable"] +pub struct PEREO2_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PEREO3` reader - Periodic Interval 3 Event Output Enable"] +pub struct PEREO3_R(crate::FieldReader); +impl PEREO3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO3` writer - Periodic Interval 3 Event Output Enable"] +pub struct PEREO3_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PEREO4` reader - Periodic Interval 4 Event Output Enable"] +pub struct PEREO4_R(crate::FieldReader); +impl PEREO4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO4` writer - Periodic Interval 4 Event Output Enable"] +pub struct PEREO4_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PEREO5` reader - Periodic Interval 5 Event Output Enable"] +pub struct PEREO5_R(crate::FieldReader); +impl PEREO5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO5` writer - Periodic Interval 5 Event Output Enable"] +pub struct PEREO5_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PEREO6` reader - Periodic Interval 6 Event Output Enable"] +pub struct PEREO6_R(crate::FieldReader); +impl PEREO6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO6` writer - Periodic Interval 6 Event Output Enable"] +pub struct PEREO6_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PEREO7` reader - Periodic Interval 7 Event Output Enable"] +pub struct PEREO7_R(crate::FieldReader); +impl PEREO7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO7` writer - Periodic Interval 7 Event Output Enable"] +pub struct PEREO7_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `ALARMEO0` reader - Alarm 0 Event Output Enable"] +pub struct ALARMEO0_R(crate::FieldReader); +impl ALARMEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALARMEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALARMEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALARMEO0` writer - Alarm 0 Event Output Enable"] +pub struct ALARMEO0_W<'a> { + w: &'a mut W, +} +impl<'a> ALARMEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `OVFEO` reader - Overflow Event Output Enable"] +pub struct OVFEO_R(crate::FieldReader); +impl OVFEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVFEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVFEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVFEO` writer - Overflow Event Output Enable"] +pub struct OVFEO_W<'a> { + w: &'a mut W, +} +impl<'a> OVFEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Event Output Enable"] + #[inline(always)] + pub fn pereo0(&self) -> PEREO0_R { + PEREO0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Event Output Enable"] + #[inline(always)] + pub fn pereo1(&self) -> PEREO1_R { + PEREO1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Event Output Enable"] + #[inline(always)] + pub fn pereo2(&self) -> PEREO2_R { + PEREO2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Event Output Enable"] + #[inline(always)] + pub fn pereo3(&self) -> PEREO3_R { + PEREO3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Event Output Enable"] + #[inline(always)] + pub fn pereo4(&self) -> PEREO4_R { + PEREO4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Event Output Enable"] + #[inline(always)] + pub fn pereo5(&self) -> PEREO5_R { + PEREO5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Event Output Enable"] + #[inline(always)] + pub fn pereo6(&self) -> PEREO6_R { + PEREO6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Event Output Enable"] + #[inline(always)] + pub fn pereo7(&self) -> PEREO7_R { + PEREO7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Alarm 0 Event Output Enable"] + #[inline(always)] + pub fn alarmeo0(&self) -> ALARMEO0_R { + ALARMEO0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&self) -> OVFEO_R { + OVFEO_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Event Output Enable"] + #[inline(always)] + pub fn pereo0(&mut self) -> PEREO0_W { + PEREO0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1 Event Output Enable"] + #[inline(always)] + pub fn pereo1(&mut self) -> PEREO1_W { + PEREO1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2 Event Output Enable"] + #[inline(always)] + pub fn pereo2(&mut self) -> PEREO2_W { + PEREO2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3 Event Output Enable"] + #[inline(always)] + pub fn pereo3(&mut self) -> PEREO3_W { + PEREO3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4 Event Output Enable"] + #[inline(always)] + pub fn pereo4(&mut self) -> PEREO4_W { + PEREO4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5 Event Output Enable"] + #[inline(always)] + pub fn pereo5(&mut self) -> PEREO5_W { + PEREO5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6 Event Output Enable"] + #[inline(always)] + pub fn pereo6(&mut self) -> PEREO6_W { + PEREO6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7 Event Output Enable"] + #[inline(always)] + pub fn pereo7(&mut self) -> PEREO7_W { + PEREO7_W { w: self } + } + #[doc = "Bit 8 - Alarm 0 Event Output Enable"] + #[inline(always)] + pub fn alarmeo0(&mut self) -> ALARMEO0_W { + ALARMEO0_W { w: self } + } + #[doc = "Bit 15 - Overflow Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&mut self) -> OVFEO_W { + OVFEO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2 Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/rtc/mode2/freqcorr.rs b/pac/atsamc21e/src/rtc/mode2/freqcorr.rs new file mode 100644 index 000000000000..043ba6f88eb2 --- /dev/null +++ b/pac/atsamc21e/src/rtc/mode2/freqcorr.rs @@ -0,0 +1,150 @@ +#[doc = "Register `FREQCORR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FREQCORR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `VALUE` reader - Correction Value"] +pub struct VALUE_R(crate::FieldReader); +impl VALUE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + VALUE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VALUE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VALUE` writer - Correction Value"] +pub struct VALUE_W<'a> { + w: &'a mut W, +} +impl<'a> VALUE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x7f) | (value as u8 & 0x7f); + self.w + } +} +#[doc = "Field `SIGN` reader - Correction Sign"] +pub struct SIGN_R(crate::FieldReader); +impl SIGN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SIGN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SIGN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SIGN` writer - Correction Sign"] +pub struct SIGN_W<'a> { + w: &'a mut W, +} +impl<'a> SIGN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bits 0:6 - Correction Value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bit 7 - Correction Sign"] + #[inline(always)] + pub fn sign(&self) -> SIGN_R { + SIGN_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:6 - Correction Value"] + #[inline(always)] + pub fn value(&mut self) -> VALUE_W { + VALUE_W { w: self } + } + #[doc = "Bit 7 - Correction Sign"] + #[inline(always)] + pub fn sign(&mut self) -> SIGN_W { + SIGN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Frequency Correction\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [freqcorr](index.html) module"] +pub struct FREQCORR_SPEC; +impl crate::RegisterSpec for FREQCORR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [freqcorr::R](R) reader structure"] +impl crate::Readable for FREQCORR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [freqcorr::W](W) writer structure"] +impl crate::Writable for FREQCORR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets FREQCORR to value 0"] +impl crate::Resettable for FREQCORR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/rtc/mode2/intenclr.rs b/pac/atsamc21e/src/rtc/mode2/intenclr.rs new file mode 100644 index 000000000000..84aa17f78a0e --- /dev/null +++ b/pac/atsamc21e/src/rtc/mode2/intenclr.rs @@ -0,0 +1,536 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER0` reader - Periodic Interval 0 Interrupt Enable"] +pub struct PER0_R(crate::FieldReader); +impl PER0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER0` writer - Periodic Interval 0 Interrupt Enable"] +pub struct PER0_W<'a> { + w: &'a mut W, +} +impl<'a> PER0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PER1` reader - Periodic Interval 1 Interrupt Enable"] +pub struct PER1_R(crate::FieldReader); +impl PER1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER1` writer - Periodic Interval 1 Interrupt Enable"] +pub struct PER1_W<'a> { + w: &'a mut W, +} +impl<'a> PER1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PER2` reader - Periodic Interval 2 Interrupt Enable"] +pub struct PER2_R(crate::FieldReader); +impl PER2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER2` writer - Periodic Interval 2 Interrupt Enable"] +pub struct PER2_W<'a> { + w: &'a mut W, +} +impl<'a> PER2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PER3` reader - Periodic Interval 3 Interrupt Enable"] +pub struct PER3_R(crate::FieldReader); +impl PER3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER3` writer - Periodic Interval 3 Interrupt Enable"] +pub struct PER3_W<'a> { + w: &'a mut W, +} +impl<'a> PER3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PER4` reader - Periodic Interval 4 Interrupt Enable"] +pub struct PER4_R(crate::FieldReader); +impl PER4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER4` writer - Periodic Interval 4 Interrupt Enable"] +pub struct PER4_W<'a> { + w: &'a mut W, +} +impl<'a> PER4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PER5` reader - Periodic Interval 5 Interrupt Enable"] +pub struct PER5_R(crate::FieldReader); +impl PER5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER5` writer - Periodic Interval 5 Interrupt Enable"] +pub struct PER5_W<'a> { + w: &'a mut W, +} +impl<'a> PER5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PER6` reader - Periodic Interval 6 Interrupt Enable"] +pub struct PER6_R(crate::FieldReader); +impl PER6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER6` writer - Periodic Interval 6 Interrupt Enable"] +pub struct PER6_W<'a> { + w: &'a mut W, +} +impl<'a> PER6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PER7` reader - Periodic Interval 7 Interrupt Enable"] +pub struct PER7_R(crate::FieldReader); +impl PER7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER7` writer - Periodic Interval 7 Interrupt Enable"] +pub struct PER7_W<'a> { + w: &'a mut W, +} +impl<'a> PER7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `ALARM0` reader - Alarm 0 Interrupt Enable"] +pub struct ALARM0_R(crate::FieldReader); +impl ALARM0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALARM0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALARM0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALARM0` writer - Alarm 0 Interrupt Enable"] +pub struct ALARM0_W<'a> { + w: &'a mut W, +} +impl<'a> ALARM0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + pub fn per0(&self) -> PER0_R { + PER0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + pub fn per1(&self) -> PER1_R { + PER1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + pub fn per2(&self) -> PER2_R { + PER2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + pub fn per3(&self) -> PER3_R { + PER3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + pub fn per4(&self) -> PER4_R { + PER4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + pub fn per5(&self) -> PER5_R { + PER5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + pub fn per6(&self) -> PER6_R { + PER6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + pub fn per7(&self) -> PER7_R { + PER7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Alarm 0 Interrupt Enable"] + #[inline(always)] + pub fn alarm0(&self) -> ALARM0_R { + ALARM0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + pub fn per0(&mut self) -> PER0_W { + PER0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + pub fn per1(&mut self) -> PER1_W { + PER1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + pub fn per2(&mut self) -> PER2_W { + PER2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + pub fn per3(&mut self) -> PER3_W { + PER3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + pub fn per4(&mut self) -> PER4_W { + PER4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + pub fn per5(&mut self) -> PER5_W { + PER5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + pub fn per6(&mut self) -> PER6_W { + PER6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + pub fn per7(&mut self) -> PER7_W { + PER7_W { w: self } + } + #[doc = "Bit 8 - Alarm 0 Interrupt Enable"] + #[inline(always)] + pub fn alarm0(&mut self) -> ALARM0_W { + ALARM0_W { w: self } + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2 Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/rtc/mode2/intenset.rs b/pac/atsamc21e/src/rtc/mode2/intenset.rs new file mode 100644 index 000000000000..a41687fa1ee5 --- /dev/null +++ b/pac/atsamc21e/src/rtc/mode2/intenset.rs @@ -0,0 +1,536 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER0` reader - Periodic Interval 0 Enable"] +pub struct PER0_R(crate::FieldReader); +impl PER0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER0` writer - Periodic Interval 0 Enable"] +pub struct PER0_W<'a> { + w: &'a mut W, +} +impl<'a> PER0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PER1` reader - Periodic Interval 1 Enable"] +pub struct PER1_R(crate::FieldReader); +impl PER1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER1` writer - Periodic Interval 1 Enable"] +pub struct PER1_W<'a> { + w: &'a mut W, +} +impl<'a> PER1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PER2` reader - Periodic Interval 2 Enable"] +pub struct PER2_R(crate::FieldReader); +impl PER2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER2` writer - Periodic Interval 2 Enable"] +pub struct PER2_W<'a> { + w: &'a mut W, +} +impl<'a> PER2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PER3` reader - Periodic Interval 3 Enable"] +pub struct PER3_R(crate::FieldReader); +impl PER3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER3` writer - Periodic Interval 3 Enable"] +pub struct PER3_W<'a> { + w: &'a mut W, +} +impl<'a> PER3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PER4` reader - Periodic Interval 4 Enable"] +pub struct PER4_R(crate::FieldReader); +impl PER4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER4` writer - Periodic Interval 4 Enable"] +pub struct PER4_W<'a> { + w: &'a mut W, +} +impl<'a> PER4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PER5` reader - Periodic Interval 5 Enable"] +pub struct PER5_R(crate::FieldReader); +impl PER5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER5` writer - Periodic Interval 5 Enable"] +pub struct PER5_W<'a> { + w: &'a mut W, +} +impl<'a> PER5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PER6` reader - Periodic Interval 6 Enable"] +pub struct PER6_R(crate::FieldReader); +impl PER6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER6` writer - Periodic Interval 6 Enable"] +pub struct PER6_W<'a> { + w: &'a mut W, +} +impl<'a> PER6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PER7` reader - Periodic Interval 7 Enable"] +pub struct PER7_R(crate::FieldReader); +impl PER7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER7` writer - Periodic Interval 7 Enable"] +pub struct PER7_W<'a> { + w: &'a mut W, +} +impl<'a> PER7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `ALARM0` reader - Alarm 0 Interrupt Enable"] +pub struct ALARM0_R(crate::FieldReader); +impl ALARM0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALARM0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALARM0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALARM0` writer - Alarm 0 Interrupt Enable"] +pub struct ALARM0_W<'a> { + w: &'a mut W, +} +impl<'a> ALARM0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Enable"] + #[inline(always)] + pub fn per0(&self) -> PER0_R { + PER0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Enable"] + #[inline(always)] + pub fn per1(&self) -> PER1_R { + PER1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Enable"] + #[inline(always)] + pub fn per2(&self) -> PER2_R { + PER2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Enable"] + #[inline(always)] + pub fn per3(&self) -> PER3_R { + PER3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Enable"] + #[inline(always)] + pub fn per4(&self) -> PER4_R { + PER4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Enable"] + #[inline(always)] + pub fn per5(&self) -> PER5_R { + PER5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Enable"] + #[inline(always)] + pub fn per6(&self) -> PER6_R { + PER6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Enable"] + #[inline(always)] + pub fn per7(&self) -> PER7_R { + PER7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Alarm 0 Interrupt Enable"] + #[inline(always)] + pub fn alarm0(&self) -> ALARM0_R { + ALARM0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Enable"] + #[inline(always)] + pub fn per0(&mut self) -> PER0_W { + PER0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1 Enable"] + #[inline(always)] + pub fn per1(&mut self) -> PER1_W { + PER1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2 Enable"] + #[inline(always)] + pub fn per2(&mut self) -> PER2_W { + PER2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3 Enable"] + #[inline(always)] + pub fn per3(&mut self) -> PER3_W { + PER3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4 Enable"] + #[inline(always)] + pub fn per4(&mut self) -> PER4_W { + PER4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5 Enable"] + #[inline(always)] + pub fn per5(&mut self) -> PER5_W { + PER5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6 Enable"] + #[inline(always)] + pub fn per6(&mut self) -> PER6_W { + PER6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7 Enable"] + #[inline(always)] + pub fn per7(&mut self) -> PER7_W { + PER7_W { w: self } + } + #[doc = "Bit 8 - Alarm 0 Interrupt Enable"] + #[inline(always)] + pub fn alarm0(&mut self) -> ALARM0_W { + ALARM0_W { w: self } + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2 Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/rtc/mode2/intflag.rs b/pac/atsamc21e/src/rtc/mode2/intflag.rs new file mode 100644 index 000000000000..8de0f3efd1d0 --- /dev/null +++ b/pac/atsamc21e/src/rtc/mode2/intflag.rs @@ -0,0 +1,536 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER0` reader - Periodic Interval 0"] +pub struct PER0_R(crate::FieldReader); +impl PER0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER0` writer - Periodic Interval 0"] +pub struct PER0_W<'a> { + w: &'a mut W, +} +impl<'a> PER0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PER1` reader - Periodic Interval 1"] +pub struct PER1_R(crate::FieldReader); +impl PER1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER1` writer - Periodic Interval 1"] +pub struct PER1_W<'a> { + w: &'a mut W, +} +impl<'a> PER1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PER2` reader - Periodic Interval 2"] +pub struct PER2_R(crate::FieldReader); +impl PER2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER2` writer - Periodic Interval 2"] +pub struct PER2_W<'a> { + w: &'a mut W, +} +impl<'a> PER2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PER3` reader - Periodic Interval 3"] +pub struct PER3_R(crate::FieldReader); +impl PER3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER3` writer - Periodic Interval 3"] +pub struct PER3_W<'a> { + w: &'a mut W, +} +impl<'a> PER3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PER4` reader - Periodic Interval 4"] +pub struct PER4_R(crate::FieldReader); +impl PER4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER4` writer - Periodic Interval 4"] +pub struct PER4_W<'a> { + w: &'a mut W, +} +impl<'a> PER4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PER5` reader - Periodic Interval 5"] +pub struct PER5_R(crate::FieldReader); +impl PER5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER5` writer - Periodic Interval 5"] +pub struct PER5_W<'a> { + w: &'a mut W, +} +impl<'a> PER5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PER6` reader - Periodic Interval 6"] +pub struct PER6_R(crate::FieldReader); +impl PER6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER6` writer - Periodic Interval 6"] +pub struct PER6_W<'a> { + w: &'a mut W, +} +impl<'a> PER6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PER7` reader - Periodic Interval 7"] +pub struct PER7_R(crate::FieldReader); +impl PER7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER7` writer - Periodic Interval 7"] +pub struct PER7_W<'a> { + w: &'a mut W, +} +impl<'a> PER7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `ALARM0` reader - Alarm 0"] +pub struct ALARM0_R(crate::FieldReader); +impl ALARM0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALARM0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALARM0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALARM0` writer - Alarm 0"] +pub struct ALARM0_W<'a> { + w: &'a mut W, +} +impl<'a> ALARM0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0"] + #[inline(always)] + pub fn per0(&self) -> PER0_R { + PER0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1"] + #[inline(always)] + pub fn per1(&self) -> PER1_R { + PER1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2"] + #[inline(always)] + pub fn per2(&self) -> PER2_R { + PER2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3"] + #[inline(always)] + pub fn per3(&self) -> PER3_R { + PER3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4"] + #[inline(always)] + pub fn per4(&self) -> PER4_R { + PER4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5"] + #[inline(always)] + pub fn per5(&self) -> PER5_R { + PER5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6"] + #[inline(always)] + pub fn per6(&self) -> PER6_R { + PER6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7"] + #[inline(always)] + pub fn per7(&self) -> PER7_R { + PER7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Alarm 0"] + #[inline(always)] + pub fn alarm0(&self) -> ALARM0_R { + ALARM0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0"] + #[inline(always)] + pub fn per0(&mut self) -> PER0_W { + PER0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1"] + #[inline(always)] + pub fn per1(&mut self) -> PER1_W { + PER1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2"] + #[inline(always)] + pub fn per2(&mut self) -> PER2_W { + PER2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3"] + #[inline(always)] + pub fn per3(&mut self) -> PER3_W { + PER3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4"] + #[inline(always)] + pub fn per4(&mut self) -> PER4_W { + PER4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5"] + #[inline(always)] + pub fn per5(&mut self) -> PER5_W { + PER5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6"] + #[inline(always)] + pub fn per6(&mut self) -> PER6_W { + PER6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7"] + #[inline(always)] + pub fn per7(&mut self) -> PER7_W { + PER7_W { w: self } + } + #[doc = "Bit 8 - Alarm 0"] + #[inline(always)] + pub fn alarm0(&mut self) -> ALARM0_W { + ALARM0_W { w: self } + } + #[doc = "Bit 15 - Overflow"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2 Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/rtc/mode2/mask.rs b/pac/atsamc21e/src/rtc/mode2/mask.rs new file mode 100644 index 000000000000..53e0bb491a62 --- /dev/null +++ b/pac/atsamc21e/src/rtc/mode2/mask.rs @@ -0,0 +1,217 @@ +#[doc = "Register `MASK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MASK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Alarm Mask Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SEL_A { + #[doc = "0: Alarm Disabled"] + OFF = 0, + #[doc = "1: Match seconds only"] + SS = 1, + #[doc = "2: Match seconds and minutes only"] + MMSS = 2, + #[doc = "3: Match seconds, minutes, and hours only"] + HHMMSS = 3, + #[doc = "4: Match seconds, minutes, hours, and days only"] + DDHHMMSS = 4, + #[doc = "5: Match seconds, minutes, hours, days, and months only"] + MMDDHHMMSS = 5, + #[doc = "6: Match seconds, minutes, hours, days, months, and years"] + YYMMDDHHMMSS = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `SEL` reader - Alarm Mask Selection"] +pub struct SEL_R(crate::FieldReader); +impl SEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEL_A::OFF), + 1 => Some(SEL_A::SS), + 2 => Some(SEL_A::MMSS), + 3 => Some(SEL_A::HHMMSS), + 4 => Some(SEL_A::DDHHMMSS), + 5 => Some(SEL_A::MMDDHHMMSS), + 6 => Some(SEL_A::YYMMDDHHMMSS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == SEL_A::OFF + } + #[doc = "Checks if the value of the field is `SS`"] + #[inline(always)] + pub fn is_ss(&self) -> bool { + **self == SEL_A::SS + } + #[doc = "Checks if the value of the field is `MMSS`"] + #[inline(always)] + pub fn is_mmss(&self) -> bool { + **self == SEL_A::MMSS + } + #[doc = "Checks if the value of the field is `HHMMSS`"] + #[inline(always)] + pub fn is_hhmmss(&self) -> bool { + **self == SEL_A::HHMMSS + } + #[doc = "Checks if the value of the field is `DDHHMMSS`"] + #[inline(always)] + pub fn is_ddhhmmss(&self) -> bool { + **self == SEL_A::DDHHMMSS + } + #[doc = "Checks if the value of the field is `MMDDHHMMSS`"] + #[inline(always)] + pub fn is_mmddhhmmss(&self) -> bool { + **self == SEL_A::MMDDHHMMSS + } + #[doc = "Checks if the value of the field is `YYMMDDHHMMSS`"] + #[inline(always)] + pub fn is_yymmddhhmmss(&self) -> bool { + **self == SEL_A::YYMMDDHHMMSS + } +} +impl core::ops::Deref for SEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEL` writer - Alarm Mask Selection"] +pub struct SEL_W<'a> { + w: &'a mut W, +} +impl<'a> SEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SEL_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Alarm Disabled"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(SEL_A::OFF) + } + #[doc = "Match seconds only"] + #[inline(always)] + pub fn ss(self) -> &'a mut W { + self.variant(SEL_A::SS) + } + #[doc = "Match seconds and minutes only"] + #[inline(always)] + pub fn mmss(self) -> &'a mut W { + self.variant(SEL_A::MMSS) + } + #[doc = "Match seconds, minutes, and hours only"] + #[inline(always)] + pub fn hhmmss(self) -> &'a mut W { + self.variant(SEL_A::HHMMSS) + } + #[doc = "Match seconds, minutes, hours, and days only"] + #[inline(always)] + pub fn ddhhmmss(self) -> &'a mut W { + self.variant(SEL_A::DDHHMMSS) + } + #[doc = "Match seconds, minutes, hours, days, and months only"] + #[inline(always)] + pub fn mmddhhmmss(self) -> &'a mut W { + self.variant(SEL_A::MMDDHHMMSS) + } + #[doc = "Match seconds, minutes, hours, days, months, and years"] + #[inline(always)] + pub fn yymmddhhmmss(self) -> &'a mut W { + self.variant(SEL_A::YYMMDDHHMMSS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Alarm Mask Selection"] + #[inline(always)] + pub fn sel(&self) -> SEL_R { + SEL_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Alarm Mask Selection"] + #[inline(always)] + pub fn sel(&mut self) -> SEL_W { + SEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2_ALARM Alarm n Mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mask](index.html) module"] +pub struct MASK_SPEC; +impl crate::RegisterSpec for MASK_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [mask::R](R) reader structure"] +impl crate::Readable for MASK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [mask::W](W) writer structure"] +impl crate::Writable for MASK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets MASK to value 0"] +impl crate::Resettable for MASK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/rtc/mode2/syncbusy.rs b/pac/atsamc21e/src/rtc/mode2/syncbusy.rs new file mode 100644 index 000000000000..b517ee5ae8b2 --- /dev/null +++ b/pac/atsamc21e/src/rtc/mode2/syncbusy.rs @@ -0,0 +1,173 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Bit Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - Enable Bit Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FREQCORR` reader - FREQCORR Register Busy"] +pub struct FREQCORR_R(crate::FieldReader); +impl FREQCORR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FREQCORR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FREQCORR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLOCK` reader - CLOCK Register Busy"] +pub struct CLOCK_R(crate::FieldReader); +impl CLOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALARM0` reader - ALARM 0 Register Busy"] +pub struct ALARM0_R(crate::FieldReader); +impl ALARM0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALARM0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALARM0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MASK0` reader - MASK 0 Register Busy"] +pub struct MASK0_R(crate::FieldReader); +impl MASK0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MASK0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MASK0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLOCKSYNC` reader - Clock Read Synchronization Enable Bit Busy"] +pub struct CLOCKSYNC_R(crate::FieldReader); +impl CLOCKSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLOCKSYNC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLOCKSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Bit Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable Bit Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - FREQCORR Register Busy"] + #[inline(always)] + pub fn freqcorr(&self) -> FREQCORR_R { + FREQCORR_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - CLOCK Register Busy"] + #[inline(always)] + pub fn clock(&self) -> CLOCK_R { + CLOCK_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 5 - ALARM 0 Register Busy"] + #[inline(always)] + pub fn alarm0(&self) -> ALARM0_R { + ALARM0_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 11 - MASK 0 Register Busy"] + #[inline(always)] + pub fn mask0(&self) -> MASK0_R { + MASK0_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 15 - Clock Read Synchronization Enable Bit Busy"] + #[inline(always)] + pub fn clocksync(&self) -> CLOCKSYNC_R { + CLOCKSYNC_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +#[doc = "MODE2 Synchronization Busy Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sdadc.rs b/pac/atsamc21e/src/sdadc.rs new file mode 100644 index 000000000000..11e926a1d2de --- /dev/null +++ b/pac/atsamc21e/src/sdadc.rs @@ -0,0 +1,140 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + #[doc = "0x01 - Reference Control"] + pub refctrl: crate::Reg, + #[doc = "0x02 - Control B"] + pub ctrlb: crate::Reg, + #[doc = "0x04 - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x05 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x06 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x07 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x08 - Sequence Status"] + pub seqstatus: crate::Reg, + #[doc = "0x09 - Input Control"] + pub inputctrl: crate::Reg, + #[doc = "0x0a - Control C"] + pub ctrlc: crate::Reg, + #[doc = "0x0b - Window Monitor Control"] + pub winctrl: crate::Reg, + #[doc = "0x0c - Window Monitor Lower Threshold"] + pub winlt: crate::Reg, + #[doc = "0x10 - Window Monitor Upper Threshold"] + pub winut: crate::Reg, + #[doc = "0x14 - Offset Correction"] + pub offsetcorr: crate::Reg, + #[doc = "0x18 - Gain Correction"] + pub gaincorr: crate::Reg, + #[doc = "0x1a - Shift Correction"] + pub shiftcorr: crate::Reg, + _reserved16: [u8; 0x01], + #[doc = "0x1c - Software Trigger"] + pub swtrig: crate::Reg, + _reserved17: [u8; 0x03], + #[doc = "0x20 - Synchronization Busy"] + pub syncbusy: crate::Reg, + #[doc = "0x24 - Result"] + pub result: crate::Reg, + #[doc = "0x28 - Sequence Control"] + pub seqctrl: crate::Reg, + _reserved20: [u8; 0x03], + #[doc = "0x2c - Analog Control"] + pub anactrl: crate::Reg, + _reserved21: [u8; 0x01], + #[doc = "0x2e - Debug Control"] + pub dbgctrl: crate::Reg, +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "REFCTRL register accessor: an alias for `Reg`"] +pub type REFCTRL = crate::Reg; +#[doc = "Reference Control"] +pub mod refctrl; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "Control B"] +pub mod ctrlb; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "SEQSTATUS register accessor: an alias for `Reg`"] +pub type SEQSTATUS = crate::Reg; +#[doc = "Sequence Status"] +pub mod seqstatus; +#[doc = "INPUTCTRL register accessor: an alias for `Reg`"] +pub type INPUTCTRL = crate::Reg; +#[doc = "Input Control"] +pub mod inputctrl; +#[doc = "CTRLC register accessor: an alias for `Reg`"] +pub type CTRLC = crate::Reg; +#[doc = "Control C"] +pub mod ctrlc; +#[doc = "WINCTRL register accessor: an alias for `Reg`"] +pub type WINCTRL = crate::Reg; +#[doc = "Window Monitor Control"] +pub mod winctrl; +#[doc = "WINLT register accessor: an alias for `Reg`"] +pub type WINLT = crate::Reg; +#[doc = "Window Monitor Lower Threshold"] +pub mod winlt; +#[doc = "WINUT register accessor: an alias for `Reg`"] +pub type WINUT = crate::Reg; +#[doc = "Window Monitor Upper Threshold"] +pub mod winut; +#[doc = "OFFSETCORR register accessor: an alias for `Reg`"] +pub type OFFSETCORR = crate::Reg; +#[doc = "Offset Correction"] +pub mod offsetcorr; +#[doc = "GAINCORR register accessor: an alias for `Reg`"] +pub type GAINCORR = crate::Reg; +#[doc = "Gain Correction"] +pub mod gaincorr; +#[doc = "SHIFTCORR register accessor: an alias for `Reg`"] +pub type SHIFTCORR = crate::Reg; +#[doc = "Shift Correction"] +pub mod shiftcorr; +#[doc = "SWTRIG register accessor: an alias for `Reg`"] +pub type SWTRIG = crate::Reg; +#[doc = "Software Trigger"] +pub mod swtrig; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Busy"] +pub mod syncbusy; +#[doc = "RESULT register accessor: an alias for `Reg`"] +pub type RESULT = crate::Reg; +#[doc = "Result"] +pub mod result; +#[doc = "SEQCTRL register accessor: an alias for `Reg`"] +pub type SEQCTRL = crate::Reg; +#[doc = "Sequence Control"] +pub mod seqctrl; +#[doc = "ANACTRL register accessor: an alias for `Reg`"] +pub type ANACTRL = crate::Reg; +#[doc = "Analog Control"] +pub mod anactrl; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; diff --git a/pac/atsamc21e/src/sdadc/anactrl.rs b/pac/atsamc21e/src/sdadc/anactrl.rs new file mode 100644 index 000000000000..3261811c0348 --- /dev/null +++ b/pac/atsamc21e/src/sdadc/anactrl.rs @@ -0,0 +1,197 @@ +#[doc = "Register `ANACTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ANACTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CTRSDADC` reader - SDADC Control"] +pub struct CTRSDADC_R(crate::FieldReader); +impl CTRSDADC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CTRSDADC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRSDADC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRSDADC` writer - SDADC Control"] +pub struct CTRSDADC_W<'a> { + w: &'a mut W, +} +impl<'a> CTRSDADC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u8 & 0x3f); + self.w + } +} +#[doc = "Field `ONCHOP` reader - Chopper"] +pub struct ONCHOP_R(crate::FieldReader); +impl ONCHOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONCHOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONCHOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONCHOP` writer - Chopper"] +pub struct ONCHOP_W<'a> { + w: &'a mut W, +} +impl<'a> ONCHOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +#[doc = "Field `BUFTEST` reader - BUFTEST"] +pub struct BUFTEST_R(crate::FieldReader); +impl BUFTEST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUFTEST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUFTEST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUFTEST` writer - BUFTEST"] +pub struct BUFTEST_W<'a> { + w: &'a mut W, +} +impl<'a> BUFTEST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - SDADC Control"] + #[inline(always)] + pub fn ctrsdadc(&self) -> CTRSDADC_R { + CTRSDADC_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - Chopper"] + #[inline(always)] + pub fn onchop(&self) -> ONCHOP_R { + ONCHOP_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - BUFTEST"] + #[inline(always)] + pub fn buftest(&self) -> BUFTEST_R { + BUFTEST_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:5 - SDADC Control"] + #[inline(always)] + pub fn ctrsdadc(&mut self) -> CTRSDADC_W { + CTRSDADC_W { w: self } + } + #[doc = "Bit 6 - Chopper"] + #[inline(always)] + pub fn onchop(&mut self) -> ONCHOP_W { + ONCHOP_W { w: self } + } + #[doc = "Bit 7 - BUFTEST"] + #[inline(always)] + pub fn buftest(&mut self) -> BUFTEST_W { + BUFTEST_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Analog Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [anactrl](index.html) module"] +pub struct ANACTRL_SPEC; +impl crate::RegisterSpec for ANACTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [anactrl::R](R) reader structure"] +impl crate::Readable for ANACTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [anactrl::W](W) writer structure"] +impl crate::Writable for ANACTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ANACTRL to value 0"] +impl crate::Resettable for ANACTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sdadc/ctrla.rs b/pac/atsamc21e/src/sdadc/ctrla.rs new file mode 100644 index 000000000000..8fccdcb93995 --- /dev/null +++ b/pac/atsamc21e/src/sdadc/ctrla.rs @@ -0,0 +1,254 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - On Demand Control"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - On Demand Control"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sdadc/ctrlb.rs b/pac/atsamc21e/src/sdadc/ctrlb.rs new file mode 100644 index 000000000000..ee0dce613bc4 --- /dev/null +++ b/pac/atsamc21e/src/sdadc/ctrlb.rs @@ -0,0 +1,392 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Prescaler Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: Peripheral clock divided by 2"] + DIV2 = 0, + #[doc = "1: Peripheral clock divided by 4"] + DIV4 = 1, + #[doc = "2: Peripheral clock divided by 8"] + DIV8 = 2, + #[doc = "3: Peripheral clock divided by 16"] + DIV16 = 3, + #[doc = "4: Peripheral clock divided by 32"] + DIV32 = 4, + #[doc = "5: Peripheral clock divided by 64"] + DIV64 = 5, + #[doc = "6: Peripheral clock divided by 128"] + DIV128 = 6, + #[doc = "7: Peripheral clock divided by 256"] + DIV256 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler Configuration"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCALER_A::DIV2), + 1 => Some(PRESCALER_A::DIV4), + 2 => Some(PRESCALER_A::DIV8), + 3 => Some(PRESCALER_A::DIV16), + 4 => Some(PRESCALER_A::DIV32), + 5 => Some(PRESCALER_A::DIV64), + 6 => Some(PRESCALER_A::DIV128), + 7 => Some(PRESCALER_A::DIV256), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == PRESCALER_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == PRESCALER_A::DIV128 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler Configuration"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Peripheral clock divided by 2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "Peripheral clock divided by 4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "Peripheral clock divided by 8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "Peripheral clock divided by 16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "Peripheral clock divided by 32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV32) + } + #[doc = "Peripheral clock divided by 64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "Peripheral clock divided by 128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV128) + } + #[doc = "Peripheral clock divided by 256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u16 & 0xff); + self.w + } +} +#[doc = "Over Sampling Ratio\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum OSR_A { + #[doc = "0: Over Sampling Ratio is 64"] + OSR64 = 0, + #[doc = "1: Over Sampling Ratio is 128"] + OSR128 = 1, + #[doc = "2: Over Sampling Ratio is 256"] + OSR256 = 2, + #[doc = "3: Over Sampling Ratio is 512"] + OSR512 = 3, + #[doc = "4: Over Sampling Ratio is 1024"] + OSR1024 = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: OSR_A) -> Self { + variant as _ + } +} +#[doc = "Field `OSR` reader - Over Sampling Ratio"] +pub struct OSR_R(crate::FieldReader); +impl OSR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + OSR_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(OSR_A::OSR64), + 1 => Some(OSR_A::OSR128), + 2 => Some(OSR_A::OSR256), + 3 => Some(OSR_A::OSR512), + 4 => Some(OSR_A::OSR1024), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OSR64`"] + #[inline(always)] + pub fn is_osr64(&self) -> bool { + **self == OSR_A::OSR64 + } + #[doc = "Checks if the value of the field is `OSR128`"] + #[inline(always)] + pub fn is_osr128(&self) -> bool { + **self == OSR_A::OSR128 + } + #[doc = "Checks if the value of the field is `OSR256`"] + #[inline(always)] + pub fn is_osr256(&self) -> bool { + **self == OSR_A::OSR256 + } + #[doc = "Checks if the value of the field is `OSR512`"] + #[inline(always)] + pub fn is_osr512(&self) -> bool { + **self == OSR_A::OSR512 + } + #[doc = "Checks if the value of the field is `OSR1024`"] + #[inline(always)] + pub fn is_osr1024(&self) -> bool { + **self == OSR_A::OSR1024 + } +} +impl core::ops::Deref for OSR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSR` writer - Over Sampling Ratio"] +pub struct OSR_W<'a> { + w: &'a mut W, +} +impl<'a> OSR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: OSR_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Over Sampling Ratio is 64"] + #[inline(always)] + pub fn osr64(self) -> &'a mut W { + self.variant(OSR_A::OSR64) + } + #[doc = "Over Sampling Ratio is 128"] + #[inline(always)] + pub fn osr128(self) -> &'a mut W { + self.variant(OSR_A::OSR128) + } + #[doc = "Over Sampling Ratio is 256"] + #[inline(always)] + pub fn osr256(self) -> &'a mut W { + self.variant(OSR_A::OSR256) + } + #[doc = "Over Sampling Ratio is 512"] + #[inline(always)] + pub fn osr512(self) -> &'a mut W { + self.variant(OSR_A::OSR512) + } + #[doc = "Over Sampling Ratio is 1024"] + #[inline(always)] + pub fn osr1024(self) -> &'a mut W { + self.variant(OSR_A::OSR1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u16 & 0x07) << 8); + self.w + } +} +#[doc = "Field `SKPCNT` reader - Skip Sample Count"] +pub struct SKPCNT_R(crate::FieldReader); +impl SKPCNT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SKPCNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SKPCNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SKPCNT` writer - Skip Sample Count"] +pub struct SKPCNT_W<'a> { + w: &'a mut W, +} +impl<'a> SKPCNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 12)) | ((value as u16 & 0x0f) << 12); + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Prescaler Configuration"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:10 - Over Sampling Ratio"] + #[inline(always)] + pub fn osr(&self) -> OSR_R { + OSR_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bits 12:15 - Skip Sample Count"] + #[inline(always)] + pub fn skpcnt(&self) -> SKPCNT_R { + SKPCNT_R::new(((self.bits >> 12) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Prescaler Configuration"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Bits 8:10 - Over Sampling Ratio"] + #[inline(always)] + pub fn osr(&mut self) -> OSR_W { + OSR_W { w: self } + } + #[doc = "Bits 12:15 - Skip Sample Count"] + #[inline(always)] + pub fn skpcnt(&mut self) -> SKPCNT_W { + SKPCNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0x2000"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x2000 + } +} diff --git a/pac/atsamc21e/src/sdadc/ctrlc.rs b/pac/atsamc21e/src/sdadc/ctrlc.rs new file mode 100644 index 000000000000..320cfe4ec4aa --- /dev/null +++ b/pac/atsamc21e/src/sdadc/ctrlc.rs @@ -0,0 +1,113 @@ +#[doc = "Register `CTRLC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FREERUN` reader - Free Running Mode"] +pub struct FREERUN_R(crate::FieldReader); +impl FREERUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FREERUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FREERUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FREERUN` writer - Free Running Mode"] +pub struct FREERUN_W<'a> { + w: &'a mut W, +} +impl<'a> FREERUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Free Running Mode"] + #[inline(always)] + pub fn freerun(&self) -> FREERUN_R { + FREERUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Free Running Mode"] + #[inline(always)] + pub fn freerun(&mut self) -> FREERUN_W { + FREERUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control C\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlc](index.html) module"] +pub struct CTRLC_SPEC; +impl crate::RegisterSpec for CTRLC_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlc::R](R) reader structure"] +impl crate::Readable for CTRLC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlc::W](W) writer structure"] +impl crate::Writable for CTRLC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLC to value 0"] +impl crate::Resettable for CTRLC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sdadc/dbgctrl.rs b/pac/atsamc21e/src/sdadc/dbgctrl.rs new file mode 100644 index 000000000000..53636eb2b339 --- /dev/null +++ b/pac/atsamc21e/src/sdadc/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Debug Run"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Debug Run"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sdadc/evctrl.rs b/pac/atsamc21e/src/sdadc/evctrl.rs new file mode 100644 index 000000000000..2c50a979c544 --- /dev/null +++ b/pac/atsamc21e/src/sdadc/evctrl.rs @@ -0,0 +1,348 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FLUSHEI` reader - Flush Event Input Enable"] +pub struct FLUSHEI_R(crate::FieldReader); +impl FLUSHEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FLUSHEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FLUSHEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLUSHEI` writer - Flush Event Input Enable"] +pub struct FLUSHEI_W<'a> { + w: &'a mut W, +} +impl<'a> FLUSHEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `STARTEI` reader - Start Conversion Event Input Enable"] +pub struct STARTEI_R(crate::FieldReader); +impl STARTEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STARTEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STARTEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STARTEI` writer - Start Conversion Event Input Enable"] +pub struct STARTEI_W<'a> { + w: &'a mut W, +} +impl<'a> STARTEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `FLUSHINV` reader - Flush Event Invert Enable"] +pub struct FLUSHINV_R(crate::FieldReader); +impl FLUSHINV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FLUSHINV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FLUSHINV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLUSHINV` writer - Flush Event Invert Enable"] +pub struct FLUSHINV_W<'a> { + w: &'a mut W, +} +impl<'a> FLUSHINV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `STARTINV` reader - Satrt Event Invert Enable"] +pub struct STARTINV_R(crate::FieldReader); +impl STARTINV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STARTINV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STARTINV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STARTINV` writer - Satrt Event Invert Enable"] +pub struct STARTINV_W<'a> { + w: &'a mut W, +} +impl<'a> STARTINV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `RESRDYEO` reader - Result Ready Event Out"] +pub struct RESRDYEO_R(crate::FieldReader); +impl RESRDYEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESRDYEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESRDYEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESRDYEO` writer - Result Ready Event Out"] +pub struct RESRDYEO_W<'a> { + w: &'a mut W, +} +impl<'a> RESRDYEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `WINMONEO` reader - Window Monitor Event Out"] +pub struct WINMONEO_R(crate::FieldReader); +impl WINMONEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINMONEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINMONEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMONEO` writer - Window Monitor Event Out"] +pub struct WINMONEO_W<'a> { + w: &'a mut W, +} +impl<'a> WINMONEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Flush Event Input Enable"] + #[inline(always)] + pub fn flushei(&self) -> FLUSHEI_R { + FLUSHEI_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Start Conversion Event Input Enable"] + #[inline(always)] + pub fn startei(&self) -> STARTEI_R { + STARTEI_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Flush Event Invert Enable"] + #[inline(always)] + pub fn flushinv(&self) -> FLUSHINV_R { + FLUSHINV_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Satrt Event Invert Enable"] + #[inline(always)] + pub fn startinv(&self) -> STARTINV_R { + STARTINV_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Result Ready Event Out"] + #[inline(always)] + pub fn resrdyeo(&self) -> RESRDYEO_R { + RESRDYEO_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Window Monitor Event Out"] + #[inline(always)] + pub fn winmoneo(&self) -> WINMONEO_R { + WINMONEO_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Flush Event Input Enable"] + #[inline(always)] + pub fn flushei(&mut self) -> FLUSHEI_W { + FLUSHEI_W { w: self } + } + #[doc = "Bit 1 - Start Conversion Event Input Enable"] + #[inline(always)] + pub fn startei(&mut self) -> STARTEI_W { + STARTEI_W { w: self } + } + #[doc = "Bit 2 - Flush Event Invert Enable"] + #[inline(always)] + pub fn flushinv(&mut self) -> FLUSHINV_W { + FLUSHINV_W { w: self } + } + #[doc = "Bit 3 - Satrt Event Invert Enable"] + #[inline(always)] + pub fn startinv(&mut self) -> STARTINV_W { + STARTINV_W { w: self } + } + #[doc = "Bit 4 - Result Ready Event Out"] + #[inline(always)] + pub fn resrdyeo(&mut self) -> RESRDYEO_W { + RESRDYEO_W { w: self } + } + #[doc = "Bit 5 - Window Monitor Event Out"] + #[inline(always)] + pub fn winmoneo(&mut self) -> WINMONEO_W { + WINMONEO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sdadc/gaincorr.rs b/pac/atsamc21e/src/sdadc/gaincorr.rs new file mode 100644 index 000000000000..0f20d1cdef86 --- /dev/null +++ b/pac/atsamc21e/src/sdadc/gaincorr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `GAINCORR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GAINCORR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `GAINCORR` reader - Gain Correction Value"] +pub struct GAINCORR_R(crate::FieldReader); +impl GAINCORR_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + GAINCORR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GAINCORR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GAINCORR` writer - Gain Correction Value"] +pub struct GAINCORR_W<'a> { + w: &'a mut W, +} +impl<'a> GAINCORR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3fff) | (value as u16 & 0x3fff); + self.w + } +} +impl R { + #[doc = "Bits 0:13 - Gain Correction Value"] + #[inline(always)] + pub fn gaincorr(&self) -> GAINCORR_R { + GAINCORR_R::new((self.bits & 0x3fff) as u16) + } +} +impl W { + #[doc = "Bits 0:13 - Gain Correction Value"] + #[inline(always)] + pub fn gaincorr(&mut self) -> GAINCORR_W { + GAINCORR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Gain Correction\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gaincorr](index.html) module"] +pub struct GAINCORR_SPEC; +impl crate::RegisterSpec for GAINCORR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [gaincorr::R](R) reader structure"] +impl crate::Readable for GAINCORR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gaincorr::W](W) writer structure"] +impl crate::Writable for GAINCORR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets GAINCORR to value 0x01"] +impl crate::Resettable for GAINCORR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pac/atsamc21e/src/sdadc/inputctrl.rs b/pac/atsamc21e/src/sdadc/inputctrl.rs new file mode 100644 index 000000000000..e256cd3bbfc1 --- /dev/null +++ b/pac/atsamc21e/src/sdadc/inputctrl.rs @@ -0,0 +1,165 @@ +#[doc = "Register `INPUTCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INPUTCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "SDADC Input Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MUXSEL_A { + #[doc = "0: SDADC AIN0 Pin"] + AIN0 = 0, + #[doc = "1: SDADC AIN1 Pin"] + AIN1 = 1, + #[doc = "2: SDADC AIN2 Pin"] + AIN2 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MUXSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `MUXSEL` reader - SDADC Input Selection"] +pub struct MUXSEL_R(crate::FieldReader); +impl MUXSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MUXSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MUXSEL_A::AIN0), + 1 => Some(MUXSEL_A::AIN1), + 2 => Some(MUXSEL_A::AIN2), + _ => None, + } + } + #[doc = "Checks if the value of the field is `AIN0`"] + #[inline(always)] + pub fn is_ain0(&self) -> bool { + **self == MUXSEL_A::AIN0 + } + #[doc = "Checks if the value of the field is `AIN1`"] + #[inline(always)] + pub fn is_ain1(&self) -> bool { + **self == MUXSEL_A::AIN1 + } + #[doc = "Checks if the value of the field is `AIN2`"] + #[inline(always)] + pub fn is_ain2(&self) -> bool { + **self == MUXSEL_A::AIN2 + } +} +impl core::ops::Deref for MUXSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MUXSEL` writer - SDADC Input Selection"] +pub struct MUXSEL_W<'a> { + w: &'a mut W, +} +impl<'a> MUXSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MUXSEL_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "SDADC AIN0 Pin"] + #[inline(always)] + pub fn ain0(self) -> &'a mut W { + self.variant(MUXSEL_A::AIN0) + } + #[doc = "SDADC AIN1 Pin"] + #[inline(always)] + pub fn ain1(self) -> &'a mut W { + self.variant(MUXSEL_A::AIN1) + } + #[doc = "SDADC AIN2 Pin"] + #[inline(always)] + pub fn ain2(self) -> &'a mut W { + self.variant(MUXSEL_A::AIN2) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - SDADC Input Selection"] + #[inline(always)] + pub fn muxsel(&self) -> MUXSEL_R { + MUXSEL_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - SDADC Input Selection"] + #[inline(always)] + pub fn muxsel(&mut self) -> MUXSEL_W { + MUXSEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Input Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [inputctrl](index.html) module"] +pub struct INPUTCTRL_SPEC; +impl crate::RegisterSpec for INPUTCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [inputctrl::R](R) reader structure"] +impl crate::Readable for INPUTCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [inputctrl::W](W) writer structure"] +impl crate::Writable for INPUTCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INPUTCTRL to value 0"] +impl crate::Resettable for INPUTCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sdadc/intenclr.rs b/pac/atsamc21e/src/sdadc/intenclr.rs new file mode 100644 index 000000000000..b10f428d30b1 --- /dev/null +++ b/pac/atsamc21e/src/sdadc/intenclr.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RESRDY` reader - Result Ready Interrupt Disable"] +pub struct RESRDY_R(crate::FieldReader); +impl RESRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESRDY` writer - Result Ready Interrupt Disable"] +pub struct RESRDY_W<'a> { + w: &'a mut W, +} +impl<'a> RESRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `OVERRUN` reader - Overrun Interrupt Disable"] +pub struct OVERRUN_R(crate::FieldReader); +impl OVERRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVERRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVERRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVERRUN` writer - Overrun Interrupt Disable"] +pub struct OVERRUN_W<'a> { + w: &'a mut W, +} +impl<'a> OVERRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WINMON` reader - Window Monitor Interrupt Disable"] +pub struct WINMON_R(crate::FieldReader); +impl WINMON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINMON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINMON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMON` writer - Window Monitor Interrupt Disable"] +pub struct WINMON_W<'a> { + w: &'a mut W, +} +impl<'a> WINMON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Result Ready Interrupt Disable"] + #[inline(always)] + pub fn resrdy(&self) -> RESRDY_R { + RESRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Overrun Interrupt Disable"] + #[inline(always)] + pub fn overrun(&self) -> OVERRUN_R { + OVERRUN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Window Monitor Interrupt Disable"] + #[inline(always)] + pub fn winmon(&self) -> WINMON_R { + WINMON_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Result Ready Interrupt Disable"] + #[inline(always)] + pub fn resrdy(&mut self) -> RESRDY_W { + RESRDY_W { w: self } + } + #[doc = "Bit 1 - Overrun Interrupt Disable"] + #[inline(always)] + pub fn overrun(&mut self) -> OVERRUN_W { + OVERRUN_W { w: self } + } + #[doc = "Bit 2 - Window Monitor Interrupt Disable"] + #[inline(always)] + pub fn winmon(&mut self) -> WINMON_W { + WINMON_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sdadc/intenset.rs b/pac/atsamc21e/src/sdadc/intenset.rs new file mode 100644 index 000000000000..5ca93b05b859 --- /dev/null +++ b/pac/atsamc21e/src/sdadc/intenset.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RESRDY` reader - Result Ready Interrupt Enable"] +pub struct RESRDY_R(crate::FieldReader); +impl RESRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESRDY` writer - Result Ready Interrupt Enable"] +pub struct RESRDY_W<'a> { + w: &'a mut W, +} +impl<'a> RESRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `OVERRUN` reader - Overrun Interrupt Enable"] +pub struct OVERRUN_R(crate::FieldReader); +impl OVERRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVERRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVERRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVERRUN` writer - Overrun Interrupt Enable"] +pub struct OVERRUN_W<'a> { + w: &'a mut W, +} +impl<'a> OVERRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WINMON` reader - Window Monitor Interrupt Enable"] +pub struct WINMON_R(crate::FieldReader); +impl WINMON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINMON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINMON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMON` writer - Window Monitor Interrupt Enable"] +pub struct WINMON_W<'a> { + w: &'a mut W, +} +impl<'a> WINMON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Result Ready Interrupt Enable"] + #[inline(always)] + pub fn resrdy(&self) -> RESRDY_R { + RESRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Overrun Interrupt Enable"] + #[inline(always)] + pub fn overrun(&self) -> OVERRUN_R { + OVERRUN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Window Monitor Interrupt Enable"] + #[inline(always)] + pub fn winmon(&self) -> WINMON_R { + WINMON_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Result Ready Interrupt Enable"] + #[inline(always)] + pub fn resrdy(&mut self) -> RESRDY_W { + RESRDY_W { w: self } + } + #[doc = "Bit 1 - Overrun Interrupt Enable"] + #[inline(always)] + pub fn overrun(&mut self) -> OVERRUN_W { + OVERRUN_W { w: self } + } + #[doc = "Bit 2 - Window Monitor Interrupt Enable"] + #[inline(always)] + pub fn winmon(&mut self) -> WINMON_W { + WINMON_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sdadc/intflag.rs b/pac/atsamc21e/src/sdadc/intflag.rs new file mode 100644 index 000000000000..3cd74788b226 --- /dev/null +++ b/pac/atsamc21e/src/sdadc/intflag.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RESRDY` reader - Result Ready Interrupt Flag"] +pub struct RESRDY_R(crate::FieldReader); +impl RESRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESRDY` writer - Result Ready Interrupt Flag"] +pub struct RESRDY_W<'a> { + w: &'a mut W, +} +impl<'a> RESRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `OVERRUN` reader - Overrun Interrupt Flag"] +pub struct OVERRUN_R(crate::FieldReader); +impl OVERRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVERRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVERRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVERRUN` writer - Overrun Interrupt Flag"] +pub struct OVERRUN_W<'a> { + w: &'a mut W, +} +impl<'a> OVERRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WINMON` reader - Window Monitor Interrupt Flag"] +pub struct WINMON_R(crate::FieldReader); +impl WINMON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINMON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINMON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMON` writer - Window Monitor Interrupt Flag"] +pub struct WINMON_W<'a> { + w: &'a mut W, +} +impl<'a> WINMON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Result Ready Interrupt Flag"] + #[inline(always)] + pub fn resrdy(&self) -> RESRDY_R { + RESRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Overrun Interrupt Flag"] + #[inline(always)] + pub fn overrun(&self) -> OVERRUN_R { + OVERRUN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Window Monitor Interrupt Flag"] + #[inline(always)] + pub fn winmon(&self) -> WINMON_R { + WINMON_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Result Ready Interrupt Flag"] + #[inline(always)] + pub fn resrdy(&mut self) -> RESRDY_W { + RESRDY_W { w: self } + } + #[doc = "Bit 1 - Overrun Interrupt Flag"] + #[inline(always)] + pub fn overrun(&mut self) -> OVERRUN_W { + OVERRUN_W { w: self } + } + #[doc = "Bit 2 - Window Monitor Interrupt Flag"] + #[inline(always)] + pub fn winmon(&mut self) -> WINMON_W { + WINMON_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sdadc/offsetcorr.rs b/pac/atsamc21e/src/sdadc/offsetcorr.rs new file mode 100644 index 000000000000..7bda80d6fbfc --- /dev/null +++ b/pac/atsamc21e/src/sdadc/offsetcorr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `OFFSETCORR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OFFSETCORR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OFFSETCORR` reader - Offset Correction Value"] +pub struct OFFSETCORR_R(crate::FieldReader); +impl OFFSETCORR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + OFFSETCORR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OFFSETCORR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OFFSETCORR` writer - Offset Correction Value"] +pub struct OFFSETCORR_W<'a> { + w: &'a mut W, +} +impl<'a> OFFSETCORR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Offset Correction Value"] + #[inline(always)] + pub fn offsetcorr(&self) -> OFFSETCORR_R { + OFFSETCORR_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Offset Correction Value"] + #[inline(always)] + pub fn offsetcorr(&mut self) -> OFFSETCORR_W { + OFFSETCORR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Offset Correction\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [offsetcorr](index.html) module"] +pub struct OFFSETCORR_SPEC; +impl crate::RegisterSpec for OFFSETCORR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [offsetcorr::R](R) reader structure"] +impl crate::Readable for OFFSETCORR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [offsetcorr::W](W) writer structure"] +impl crate::Writable for OFFSETCORR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OFFSETCORR to value 0"] +impl crate::Resettable for OFFSETCORR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sdadc/refctrl.rs b/pac/atsamc21e/src/sdadc/refctrl.rs new file mode 100644 index 000000000000..89449071a49b --- /dev/null +++ b/pac/atsamc21e/src/sdadc/refctrl.rs @@ -0,0 +1,262 @@ +#[doc = "Register `REFCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `REFCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Reference Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum REFSEL_A { + #[doc = "0: Internal Bandgap Reference"] + INTREF = 0, + #[doc = "1: External Reference"] + AREFB = 1, + #[doc = "2: Internal DAC Output"] + DAC = 2, + #[doc = "3: VDDANA"] + INTVCC = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: REFSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `REFSEL` reader - Reference Selection"] +pub struct REFSEL_R(crate::FieldReader); +impl REFSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REFSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> REFSEL_A { + match self.bits { + 0 => REFSEL_A::INTREF, + 1 => REFSEL_A::AREFB, + 2 => REFSEL_A::DAC, + 3 => REFSEL_A::INTVCC, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INTREF`"] + #[inline(always)] + pub fn is_intref(&self) -> bool { + **self == REFSEL_A::INTREF + } + #[doc = "Checks if the value of the field is `AREFB`"] + #[inline(always)] + pub fn is_arefb(&self) -> bool { + **self == REFSEL_A::AREFB + } + #[doc = "Checks if the value of the field is `DAC`"] + #[inline(always)] + pub fn is_dac(&self) -> bool { + **self == REFSEL_A::DAC + } + #[doc = "Checks if the value of the field is `INTVCC`"] + #[inline(always)] + pub fn is_intvcc(&self) -> bool { + **self == REFSEL_A::INTVCC + } +} +impl core::ops::Deref for REFSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REFSEL` writer - Reference Selection"] +pub struct REFSEL_W<'a> { + w: &'a mut W, +} +impl<'a> REFSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: REFSEL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Internal Bandgap Reference"] + #[inline(always)] + pub fn intref(self) -> &'a mut W { + self.variant(REFSEL_A::INTREF) + } + #[doc = "External Reference"] + #[inline(always)] + pub fn arefb(self) -> &'a mut W { + self.variant(REFSEL_A::AREFB) + } + #[doc = "Internal DAC Output"] + #[inline(always)] + pub fn dac(self) -> &'a mut W { + self.variant(REFSEL_A::DAC) + } + #[doc = "VDDANA"] + #[inline(always)] + pub fn intvcc(self) -> &'a mut W { + self.variant(REFSEL_A::INTVCC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u8 & 0x03); + self.w + } +} +#[doc = "Field `REFRANGE` reader - Reference Range"] +pub struct REFRANGE_R(crate::FieldReader); +impl REFRANGE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REFRANGE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REFRANGE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REFRANGE` writer - Reference Range"] +pub struct REFRANGE_W<'a> { + w: &'a mut W, +} +impl<'a> REFRANGE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u8 & 0x03) << 4); + self.w + } +} +#[doc = "Field `ONREFBUF` reader - Reference Buffer"] +pub struct ONREFBUF_R(crate::FieldReader); +impl ONREFBUF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONREFBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONREFBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONREFBUF` writer - Reference Buffer"] +pub struct ONREFBUF_W<'a> { + w: &'a mut W, +} +impl<'a> ONREFBUF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Reference Selection"] + #[inline(always)] + pub fn refsel(&self) -> REFSEL_R { + REFSEL_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bits 4:5 - Reference Range"] + #[inline(always)] + pub fn refrange(&self) -> REFRANGE_R { + REFRANGE_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bit 7 - Reference Buffer"] + #[inline(always)] + pub fn onrefbuf(&self) -> ONREFBUF_R { + ONREFBUF_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:1 - Reference Selection"] + #[inline(always)] + pub fn refsel(&mut self) -> REFSEL_W { + REFSEL_W { w: self } + } + #[doc = "Bits 4:5 - Reference Range"] + #[inline(always)] + pub fn refrange(&mut self) -> REFRANGE_W { + REFRANGE_W { w: self } + } + #[doc = "Bit 7 - Reference Buffer"] + #[inline(always)] + pub fn onrefbuf(&mut self) -> ONREFBUF_W { + ONREFBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Reference Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [refctrl](index.html) module"] +pub struct REFCTRL_SPEC; +impl crate::RegisterSpec for REFCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [refctrl::R](R) reader structure"] +impl crate::Readable for REFCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [refctrl::W](W) writer structure"] +impl crate::Writable for REFCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets REFCTRL to value 0"] +impl crate::Resettable for REFCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sdadc/result.rs b/pac/atsamc21e/src/sdadc/result.rs new file mode 100644 index 000000000000..3f88d8b60ca6 --- /dev/null +++ b/pac/atsamc21e/src/sdadc/result.rs @@ -0,0 +1,53 @@ +#[doc = "Register `RESULT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `RESULT` reader - Result Value"] +pub struct RESULT_R(crate::FieldReader); +impl RESULT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + RESULT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESULT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:23 - Result Value"] + #[inline(always)] + pub fn result(&self) -> RESULT_R { + RESULT_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +#[doc = "Result\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [result](index.html) module"] +pub struct RESULT_SPEC; +impl crate::RegisterSpec for RESULT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [result::R](R) reader structure"] +impl crate::Readable for RESULT_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets RESULT to value 0"] +impl crate::Resettable for RESULT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sdadc/seqctrl.rs b/pac/atsamc21e/src/sdadc/seqctrl.rs new file mode 100644 index 000000000000..c8d1103959ee --- /dev/null +++ b/pac/atsamc21e/src/sdadc/seqctrl.rs @@ -0,0 +1,103 @@ +#[doc = "Register `SEQCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SEQCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SEQEN` reader - Enable Positive Input in the Sequence"] +pub struct SEQEN_R(crate::FieldReader); +impl SEQEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SEQEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEQEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEQEN` writer - Enable Positive Input in the Sequence"] +pub struct SEQEN_W<'a> { + w: &'a mut W, +} +impl<'a> SEQEN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Enable Positive Input in the Sequence"] + #[inline(always)] + pub fn seqen(&self) -> SEQEN_R { + SEQEN_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Enable Positive Input in the Sequence"] + #[inline(always)] + pub fn seqen(&mut self) -> SEQEN_W { + SEQEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Sequence Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [seqctrl](index.html) module"] +pub struct SEQCTRL_SPEC; +impl crate::RegisterSpec for SEQCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [seqctrl::R](R) reader structure"] +impl crate::Readable for SEQCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [seqctrl::W](W) writer structure"] +impl crate::Writable for SEQCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SEQCTRL to value 0"] +impl crate::Resettable for SEQCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sdadc/seqstatus.rs b/pac/atsamc21e/src/sdadc/seqstatus.rs new file mode 100644 index 000000000000..db10e7ca448e --- /dev/null +++ b/pac/atsamc21e/src/sdadc/seqstatus.rs @@ -0,0 +1,73 @@ +#[doc = "Register `SEQSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SEQSTATE` reader - Sequence State"] +pub struct SEQSTATE_R(crate::FieldReader); +impl SEQSTATE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SEQSTATE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEQSTATE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEQBUSY` reader - Sequence Busy"] +pub struct SEQBUSY_R(crate::FieldReader); +impl SEQBUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SEQBUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEQBUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:3 - Sequence State"] + #[inline(always)] + pub fn seqstate(&self) -> SEQSTATE_R { + SEQSTATE_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 7 - Sequence Busy"] + #[inline(always)] + pub fn seqbusy(&self) -> SEQBUSY_R { + SEQBUSY_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +#[doc = "Sequence Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [seqstatus](index.html) module"] +pub struct SEQSTATUS_SPEC; +impl crate::RegisterSpec for SEQSTATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [seqstatus::R](R) reader structure"] +impl crate::Readable for SEQSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SEQSTATUS to value 0"] +impl crate::Resettable for SEQSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sdadc/shiftcorr.rs b/pac/atsamc21e/src/sdadc/shiftcorr.rs new file mode 100644 index 000000000000..a5940537700e --- /dev/null +++ b/pac/atsamc21e/src/sdadc/shiftcorr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `SHIFTCORR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SHIFTCORR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SHIFTCORR` reader - Shift Correction Value"] +pub struct SHIFTCORR_R(crate::FieldReader); +impl SHIFTCORR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SHIFTCORR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SHIFTCORR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SHIFTCORR` writer - Shift Correction Value"] +pub struct SHIFTCORR_W<'a> { + w: &'a mut W, +} +impl<'a> SHIFTCORR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Shift Correction Value"] + #[inline(always)] + pub fn shiftcorr(&self) -> SHIFTCORR_R { + SHIFTCORR_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Shift Correction Value"] + #[inline(always)] + pub fn shiftcorr(&mut self) -> SHIFTCORR_W { + SHIFTCORR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Shift Correction\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [shiftcorr](index.html) module"] +pub struct SHIFTCORR_SPEC; +impl crate::RegisterSpec for SHIFTCORR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [shiftcorr::R](R) reader structure"] +impl crate::Readable for SHIFTCORR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [shiftcorr::W](W) writer structure"] +impl crate::Writable for SHIFTCORR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SHIFTCORR to value 0"] +impl crate::Resettable for SHIFTCORR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sdadc/swtrig.rs b/pac/atsamc21e/src/sdadc/swtrig.rs new file mode 100644 index 000000000000..7656a614dd67 --- /dev/null +++ b/pac/atsamc21e/src/sdadc/swtrig.rs @@ -0,0 +1,160 @@ +#[doc = "Register `SWTRIG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SWTRIG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FLUSH` reader - SDADC Flush"] +pub struct FLUSH_R(crate::FieldReader); +impl FLUSH_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FLUSH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FLUSH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLUSH` writer - SDADC Flush"] +pub struct FLUSH_W<'a> { + w: &'a mut W, +} +impl<'a> FLUSH_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `START` reader - Start SDADC Conversion"] +pub struct START_R(crate::FieldReader); +impl START_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + START_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for START_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `START` writer - Start SDADC Conversion"] +pub struct START_W<'a> { + w: &'a mut W, +} +impl<'a> START_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - SDADC Flush"] + #[inline(always)] + pub fn flush(&self) -> FLUSH_R { + FLUSH_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Start SDADC Conversion"] + #[inline(always)] + pub fn start(&self) -> START_R { + START_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - SDADC Flush"] + #[inline(always)] + pub fn flush(&mut self) -> FLUSH_W { + FLUSH_W { w: self } + } + #[doc = "Bit 1 - Start SDADC Conversion"] + #[inline(always)] + pub fn start(&mut self) -> START_W { + START_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Software Trigger\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [swtrig](index.html) module"] +pub struct SWTRIG_SPEC; +impl crate::RegisterSpec for SWTRIG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [swtrig::R](R) reader structure"] +impl crate::Readable for SWTRIG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [swtrig::W](W) writer structure"] +impl crate::Writable for SWTRIG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SWTRIG to value 0"] +impl crate::Resettable for SWTRIG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sdadc/syncbusy.rs b/pac/atsamc21e/src/sdadc/syncbusy.rs new file mode 100644 index 000000000000..519fa5e8a57f --- /dev/null +++ b/pac/atsamc21e/src/sdadc/syncbusy.rs @@ -0,0 +1,273 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - SWRST Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - ENABLE Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLC` reader - CTRLC Synchronization Busy"] +pub struct CTRLC_R(crate::FieldReader); +impl CTRLC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INPUTCTRL` reader - INPUTCTRL Synchronization Busy"] +pub struct INPUTCTRL_R(crate::FieldReader); +impl INPUTCTRL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INPUTCTRL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INPUTCTRL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINCTRL` reader - WINCTRL Synchronization Busy"] +pub struct WINCTRL_R(crate::FieldReader); +impl WINCTRL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINCTRL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINCTRL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINLT` reader - WINLT Synchronization Busy"] +pub struct WINLT_R(crate::FieldReader); +impl WINLT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINLT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINLT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINUT` reader - WINUT Synchronization Busy"] +pub struct WINUT_R(crate::FieldReader); +impl WINUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OFFSETCORR` reader - OFFSETCTRL Synchronization Busy"] +pub struct OFFSETCORR_R(crate::FieldReader); +impl OFFSETCORR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OFFSETCORR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OFFSETCORR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GAINCORR` reader - GAINCORR Synchronization Busy"] +pub struct GAINCORR_R(crate::FieldReader); +impl GAINCORR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GAINCORR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GAINCORR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SHIFTCORR` reader - SHIFTCORR Synchronization Busy"] +pub struct SHIFTCORR_R(crate::FieldReader); +impl SHIFTCORR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SHIFTCORR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SHIFTCORR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG` reader - SWTRG Synchronization Busy"] +pub struct SWTRIG_R(crate::FieldReader); +impl SWTRIG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ANACTRL` reader - ANACTRL Synchronization Busy"] +pub struct ANACTRL_R(crate::FieldReader); +impl ANACTRL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ANACTRL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ANACTRL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - SWRST Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ENABLE Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - CTRLC Synchronization Busy"] + #[inline(always)] + pub fn ctrlc(&self) -> CTRLC_R { + CTRLC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - INPUTCTRL Synchronization Busy"] + #[inline(always)] + pub fn inputctrl(&self) -> INPUTCTRL_R { + INPUTCTRL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - WINCTRL Synchronization Busy"] + #[inline(always)] + pub fn winctrl(&self) -> WINCTRL_R { + WINCTRL_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - WINLT Synchronization Busy"] + #[inline(always)] + pub fn winlt(&self) -> WINLT_R { + WINLT_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - WINUT Synchronization Busy"] + #[inline(always)] + pub fn winut(&self) -> WINUT_R { + WINUT_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - OFFSETCTRL Synchronization Busy"] + #[inline(always)] + pub fn offsetcorr(&self) -> OFFSETCORR_R { + OFFSETCORR_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - GAINCORR Synchronization Busy"] + #[inline(always)] + pub fn gaincorr(&self) -> GAINCORR_R { + GAINCORR_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - SHIFTCORR Synchronization Busy"] + #[inline(always)] + pub fn shiftcorr(&self) -> SHIFTCORR_R { + SHIFTCORR_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - SWTRG Synchronization Busy"] + #[inline(always)] + pub fn swtrig(&self) -> SWTRIG_R { + SWTRIG_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - ANACTRL Synchronization Busy"] + #[inline(always)] + pub fn anactrl(&self) -> ANACTRL_R { + ANACTRL_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +#[doc = "Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sdadc/winctrl.rs b/pac/atsamc21e/src/sdadc/winctrl.rs new file mode 100644 index 000000000000..ed0d2d4fe006 --- /dev/null +++ b/pac/atsamc21e/src/sdadc/winctrl.rs @@ -0,0 +1,103 @@ +#[doc = "Register `WINCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WINCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WINMODE` reader - Window Monitor Mode"] +pub struct WINMODE_R(crate::FieldReader); +impl WINMODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WINMODE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMODE` writer - Window Monitor Mode"] +pub struct WINMODE_W<'a> { + w: &'a mut W, +} +impl<'a> WINMODE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Window Monitor Mode"] + #[inline(always)] + pub fn winmode(&self) -> WINMODE_R { + WINMODE_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Window Monitor Mode"] + #[inline(always)] + pub fn winmode(&mut self) -> WINMODE_W { + WINMODE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Window Monitor Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [winctrl](index.html) module"] +pub struct WINCTRL_SPEC; +impl crate::RegisterSpec for WINCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [winctrl::R](R) reader structure"] +impl crate::Readable for WINCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [winctrl::W](W) writer structure"] +impl crate::Writable for WINCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WINCTRL to value 0"] +impl crate::Resettable for WINCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sdadc/winlt.rs b/pac/atsamc21e/src/sdadc/winlt.rs new file mode 100644 index 000000000000..be16283e9e36 --- /dev/null +++ b/pac/atsamc21e/src/sdadc/winlt.rs @@ -0,0 +1,103 @@ +#[doc = "Register `WINLT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WINLT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WINLT` reader - Window Lower Threshold"] +pub struct WINLT_R(crate::FieldReader); +impl WINLT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + WINLT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINLT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINLT` writer - Window Lower Threshold"] +pub struct WINLT_W<'a> { + w: &'a mut W, +} +impl<'a> WINLT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Window Lower Threshold"] + #[inline(always)] + pub fn winlt(&self) -> WINLT_R { + WINLT_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Window Lower Threshold"] + #[inline(always)] + pub fn winlt(&mut self) -> WINLT_W { + WINLT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Window Monitor Lower Threshold\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [winlt](index.html) module"] +pub struct WINLT_SPEC; +impl crate::RegisterSpec for WINLT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [winlt::R](R) reader structure"] +impl crate::Readable for WINLT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [winlt::W](W) writer structure"] +impl crate::Writable for WINLT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WINLT to value 0"] +impl crate::Resettable for WINLT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sdadc/winut.rs b/pac/atsamc21e/src/sdadc/winut.rs new file mode 100644 index 000000000000..7dc20e7c5f9e --- /dev/null +++ b/pac/atsamc21e/src/sdadc/winut.rs @@ -0,0 +1,103 @@ +#[doc = "Register `WINUT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WINUT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WINUT` reader - Window Upper Threshold"] +pub struct WINUT_R(crate::FieldReader); +impl WINUT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + WINUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINUT` writer - Window Upper Threshold"] +pub struct WINUT_W<'a> { + w: &'a mut W, +} +impl<'a> WINUT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Window Upper Threshold"] + #[inline(always)] + pub fn winut(&self) -> WINUT_R { + WINUT_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Window Upper Threshold"] + #[inline(always)] + pub fn winut(&mut self) -> WINUT_W { + WINUT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Window Monitor Upper Threshold\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [winut](index.html) module"] +pub struct WINUT_SPEC; +impl crate::RegisterSpec for WINUT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [winut::R](R) reader structure"] +impl crate::Readable for WINUT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [winut::W](W) writer structure"] +impl crate::Writable for WINUT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WINUT to value 0"] +impl crate::Resettable for WINUT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sercom0.rs b/pac/atsamc21e/src/sercom0.rs new file mode 100644 index 000000000000..da7b62f750c6 --- /dev/null +++ b/pac/atsamc21e/src/sercom0.rs @@ -0,0 +1,327 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved_0_i2cm: [u8; 0x31], +} +impl RegisterBlock { + #[doc = "0x00..0x31 - USART INTERNAL CLOCK Mode"] + #[inline(always)] + pub fn usart_int(&self) -> &USART_INT { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const USART_INT) } + } + #[doc = "0x00..0x31 - USART EXTERNAL CLOCK Mode"] + #[inline(always)] + pub fn usart_ext(&self) -> &USART_EXT { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const USART_EXT) } + } + #[doc = "0x00..0x31 - SPI Master Mode"] + #[inline(always)] + pub fn spim(&self) -> &SPIM { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const SPIM) } + } + #[doc = "0x00..0x31 - SPI Slave Mode"] + #[inline(always)] + pub fn spis(&self) -> &SPIS { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const SPIS) } + } + #[doc = "0x00..0x29 - I2C Slave Mode"] + #[inline(always)] + pub fn i2cs(&self) -> &I2CS { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const I2CS) } + } + #[doc = "0x00..0x31 - I2C Master Mode"] + #[inline(always)] + pub fn i2cm(&self) -> &I2CM { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const I2CM) } + } +} +#[doc = r"Register block"] +#[repr(C)] +pub struct I2CM { + #[doc = "0x00 - I2CM Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - I2CM Control B"] + pub ctrlb: crate::Reg, + _reserved2: [u8; 0x04], + #[doc = "0x0c - I2CM Baud Rate"] + pub baud: crate::Reg, + _reserved3: [u8; 0x04], + #[doc = "0x14 - I2CM Interrupt Enable Clear"] + pub intenclr: crate::Reg, + _reserved4: [u8; 0x01], + #[doc = "0x16 - I2CM Interrupt Enable Set"] + pub intenset: crate::Reg, + _reserved5: [u8; 0x01], + #[doc = "0x18 - I2CM Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x1a - I2CM Status"] + pub status: crate::Reg, + #[doc = "0x1c - I2CM Synchronization Busy"] + pub syncbusy: crate::Reg, + _reserved8: [u8; 0x04], + #[doc = "0x24 - I2CM Address"] + pub addr: crate::Reg, + #[doc = "0x28 - I2CM Data"] + pub data: crate::Reg, + _reserved10: [u8; 0x07], + #[doc = "0x30 - I2CM Debug Control"] + pub dbgctrl: crate::Reg, +} +#[doc = r"Register block"] +#[doc = "I2C Master Mode"] +pub mod i2cm; +#[doc = r"Register block"] +#[repr(C)] +pub struct I2CS { + #[doc = "0x00 - I2CS Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - I2CS Control B"] + pub ctrlb: crate::Reg, + _reserved2: [u8; 0x0c], + #[doc = "0x14 - I2CS Interrupt Enable Clear"] + pub intenclr: crate::Reg, + _reserved3: [u8; 0x01], + #[doc = "0x16 - I2CS Interrupt Enable Set"] + pub intenset: crate::Reg, + _reserved4: [u8; 0x01], + #[doc = "0x18 - I2CS Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved5: [u8; 0x01], + #[doc = "0x1a - I2CS Status"] + pub status: crate::Reg, + #[doc = "0x1c - I2CS Synchronization Busy"] + pub syncbusy: crate::Reg, + _reserved7: [u8; 0x04], + #[doc = "0x24 - I2CS Address"] + pub addr: crate::Reg, + #[doc = "0x28 - I2CS Data"] + pub data: crate::Reg, +} +#[doc = r"Register block"] +#[doc = "I2C Slave Mode"] +pub mod i2cs; +#[doc = r"Register block"] +#[repr(C)] +pub struct SPIS { + #[doc = "0x00 - SPIS Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - SPIS Control B"] + pub ctrlb: crate::Reg, + _reserved2: [u8; 0x04], + #[doc = "0x0c - SPIS Baud Rate"] + pub baud: crate::Reg, + _reserved3: [u8; 0x07], + #[doc = "0x14 - SPIS Interrupt Enable Clear"] + pub intenclr: crate::Reg, + _reserved4: [u8; 0x01], + #[doc = "0x16 - SPIS Interrupt Enable Set"] + pub intenset: crate::Reg, + _reserved5: [u8; 0x01], + #[doc = "0x18 - SPIS Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x1a - SPIS Status"] + pub status: crate::Reg, + #[doc = "0x1c - SPIS Synchronization Busy"] + pub syncbusy: crate::Reg, + _reserved8: [u8; 0x04], + #[doc = "0x24 - SPIS Address"] + pub addr: crate::Reg, + #[doc = "0x28 - SPIS Data"] + pub data: crate::Reg, + _reserved10: [u8; 0x04], + #[doc = "0x30 - SPIS Debug Control"] + pub dbgctrl: crate::Reg, +} +#[doc = r"Register block"] +#[doc = "SPI Slave Mode"] +pub mod spis; +#[doc = r"Register block"] +#[repr(C)] +pub struct SPIM { + #[doc = "0x00 - SPIM Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - SPIM Control B"] + pub ctrlb: crate::Reg, + _reserved2: [u8; 0x04], + #[doc = "0x0c - SPIM Baud Rate"] + pub baud: crate::Reg, + _reserved3: [u8; 0x07], + #[doc = "0x14 - SPIM Interrupt Enable Clear"] + pub intenclr: crate::Reg, + _reserved4: [u8; 0x01], + #[doc = "0x16 - SPIM Interrupt Enable Set"] + pub intenset: crate::Reg, + _reserved5: [u8; 0x01], + #[doc = "0x18 - SPIM Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x1a - SPIM Status"] + pub status: crate::Reg, + #[doc = "0x1c - SPIM Synchronization Busy"] + pub syncbusy: crate::Reg, + _reserved8: [u8; 0x04], + #[doc = "0x24 - SPIM Address"] + pub addr: crate::Reg, + #[doc = "0x28 - SPIM Data"] + pub data: crate::Reg, + _reserved10: [u8; 0x04], + #[doc = "0x30 - SPIM Debug Control"] + pub dbgctrl: crate::Reg, +} +#[doc = r"Register block"] +#[doc = "SPI Master Mode"] +pub mod spim; +#[doc = r"Register block"] +#[repr(C)] +pub struct USART_EXT { + #[doc = "0x00 - USART_EXT Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - USART_EXT Control B"] + pub ctrlb: crate::Reg, + #[doc = "0x08 - USART_EXT Control C"] + pub ctrlc: crate::Reg, + _reserved_3_baud: [u8; 0x02], + #[doc = "0x0e - USART_EXT Receive Pulse Length"] + pub rxpl: crate::Reg, + _reserved5: [u8; 0x05], + #[doc = "0x14 - USART_EXT Interrupt Enable Clear"] + pub intenclr: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x16 - USART_EXT Interrupt Enable Set"] + pub intenset: crate::Reg, + _reserved7: [u8; 0x01], + #[doc = "0x18 - USART_EXT Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved8: [u8; 0x01], + #[doc = "0x1a - USART_EXT Status"] + pub status: crate::Reg, + #[doc = "0x1c - USART_EXT Synchronization Busy"] + pub syncbusy: crate::Reg, + _reserved10: [u8; 0x08], + #[doc = "0x28 - USART_EXT Data"] + pub data: crate::Reg, + _reserved11: [u8; 0x06], + #[doc = "0x30 - USART_EXT Debug Control"] + pub dbgctrl: crate::Reg, +} +impl USART_EXT { + #[doc = "0x0c - USART_EXT Baud Rate"] + #[inline(always)] + pub fn baud_usartfp_mode( + &self, + ) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } + #[doc = "0x0c - USART_EXT Baud Rate"] + #[inline(always)] + pub fn baud_fracfp_mode( + &self, + ) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } + #[doc = "0x0c - USART_EXT Baud Rate"] + #[inline(always)] + pub fn baud_frac_mode( + &self, + ) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } + #[doc = "0x0c - USART_EXT Baud Rate"] + #[inline(always)] + pub fn baud(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } +} +#[doc = r"Register block"] +#[doc = "USART EXTERNAL CLOCK Mode"] +pub mod usart_ext; +#[doc = r"Register block"] +#[repr(C)] +pub struct USART_INT { + #[doc = "0x00 - USART_INT Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - USART_INT Control B"] + pub ctrlb: crate::Reg, + #[doc = "0x08 - USART_INT Control C"] + pub ctrlc: crate::Reg, + _reserved_3_baud: [u8; 0x02], + #[doc = "0x0e - USART_INT Receive Pulse Length"] + pub rxpl: crate::Reg, + _reserved5: [u8; 0x05], + #[doc = "0x14 - USART_INT Interrupt Enable Clear"] + pub intenclr: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x16 - USART_INT Interrupt Enable Set"] + pub intenset: crate::Reg, + _reserved7: [u8; 0x01], + #[doc = "0x18 - USART_INT Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved8: [u8; 0x01], + #[doc = "0x1a - USART_INT Status"] + pub status: crate::Reg, + #[doc = "0x1c - USART_INT Synchronization Busy"] + pub syncbusy: crate::Reg, + _reserved10: [u8; 0x08], + #[doc = "0x28 - USART_INT Data"] + pub data: crate::Reg, + _reserved11: [u8; 0x06], + #[doc = "0x30 - USART_INT Debug Control"] + pub dbgctrl: crate::Reg, +} +impl USART_INT { + #[doc = "0x0c - USART_INT Baud Rate"] + #[inline(always)] + pub fn baud_usartfp_mode( + &self, + ) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } + #[doc = "0x0c - USART_INT Baud Rate"] + #[inline(always)] + pub fn baud_fracfp_mode( + &self, + ) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } + #[doc = "0x0c - USART_INT Baud Rate"] + #[inline(always)] + pub fn baud_frac_mode( + &self, + ) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } + #[doc = "0x0c - USART_INT Baud Rate"] + #[inline(always)] + pub fn baud(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } +} +#[doc = r"Register block"] +#[doc = "USART INTERNAL CLOCK Mode"] +pub mod usart_int; diff --git a/pac/atsamc21e/src/sercom0/i2cm.rs b/pac/atsamc21e/src/sercom0/i2cm.rs new file mode 100644 index 000000000000..8aa217da8b18 --- /dev/null +++ b/pac/atsamc21e/src/sercom0/i2cm.rs @@ -0,0 +1,44 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "I2CM Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "I2CM Control B"] +pub mod ctrlb; +#[doc = "BAUD register accessor: an alias for `Reg`"] +pub type BAUD = crate::Reg; +#[doc = "I2CM Baud Rate"] +pub mod baud; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "I2CM Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "I2CM Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "I2CM Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "I2CM Status"] +pub mod status; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "I2CM Synchronization Busy"] +pub mod syncbusy; +#[doc = "ADDR register accessor: an alias for `Reg`"] +pub type ADDR = crate::Reg; +#[doc = "I2CM Address"] +pub mod addr; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "I2CM Data"] +pub mod data; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "I2CM Debug Control"] +pub mod dbgctrl; diff --git a/pac/atsamc21e/src/sercom0/i2cm/addr.rs b/pac/atsamc21e/src/sercom0/i2cm/addr.rs new file mode 100644 index 000000000000..4efd19e824c6 --- /dev/null +++ b/pac/atsamc21e/src/sercom0/i2cm/addr.rs @@ -0,0 +1,281 @@ +#[doc = "Register `ADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ADDR` reader - Address Value"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - Address Value"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07ff) | (value as u32 & 0x07ff); + self.w + } +} +#[doc = "Field `LENEN` reader - Length Enable"] +pub struct LENEN_R(crate::FieldReader); +impl LENEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LENEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LENEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LENEN` writer - Length Enable"] +pub struct LENEN_W<'a> { + w: &'a mut W, +} +impl<'a> LENEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `HS` reader - High Speed Mode"] +pub struct HS_R(crate::FieldReader); +impl HS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HS` writer - High Speed Mode"] +pub struct HS_W<'a> { + w: &'a mut W, +} +impl<'a> HS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `TENBITEN` reader - Ten Bit Addressing Enable"] +pub struct TENBITEN_R(crate::FieldReader); +impl TENBITEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TENBITEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TENBITEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TENBITEN` writer - Ten Bit Addressing Enable"] +pub struct TENBITEN_W<'a> { + w: &'a mut W, +} +impl<'a> TENBITEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `LEN` reader - Length"] +pub struct LEN_R(crate::FieldReader); +impl LEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LEN` writer - Length"] +pub struct LEN_W<'a> { + w: &'a mut W, +} +impl<'a> LEN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:10 - Address Value"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new((self.bits & 0x07ff) as u16) + } + #[doc = "Bit 13 - Length Enable"] + #[inline(always)] + pub fn lenen(&self) -> LENEN_R { + LENEN_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - High Speed Mode"] + #[inline(always)] + pub fn hs(&self) -> HS_R { + HS_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Ten Bit Addressing Enable"] + #[inline(always)] + pub fn tenbiten(&self) -> TENBITEN_R { + TENBITEN_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:23 - Length"] + #[inline(always)] + pub fn len(&self) -> LEN_R { + LEN_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:10 - Address Value"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Bit 13 - Length Enable"] + #[inline(always)] + pub fn lenen(&mut self) -> LENEN_W { + LENEN_W { w: self } + } + #[doc = "Bit 14 - High Speed Mode"] + #[inline(always)] + pub fn hs(&mut self) -> HS_W { + HS_W { w: self } + } + #[doc = "Bit 15 - Ten Bit Addressing Enable"] + #[inline(always)] + pub fn tenbiten(&mut self) -> TENBITEN_W { + TENBITEN_W { w: self } + } + #[doc = "Bits 16:23 - Length"] + #[inline(always)] + pub fn len(&mut self) -> LEN_W { + LEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [addr](index.html) module"] +pub struct ADDR_SPEC; +impl crate::RegisterSpec for ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [addr::R](R) reader structure"] +impl crate::Readable for ADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [addr::W](W) writer structure"] +impl crate::Writable for ADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ADDR to value 0"] +impl crate::Resettable for ADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sercom0/i2cm/baud.rs b/pac/atsamc21e/src/sercom0/i2cm/baud.rs new file mode 100644 index 000000000000..7c98d3b5b0de --- /dev/null +++ b/pac/atsamc21e/src/sercom0/i2cm/baud.rs @@ -0,0 +1,214 @@ +#[doc = "Register `BAUD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +#[doc = "Field `BAUDLOW` reader - Baud Rate Value Low"] +pub struct BAUDLOW_R(crate::FieldReader); +impl BAUDLOW_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BAUDLOW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUDLOW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUDLOW` writer - Baud Rate Value Low"] +pub struct BAUDLOW_W<'a> { + w: &'a mut W, +} +impl<'a> BAUDLOW_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +#[doc = "Field `HSBAUD` reader - High Speed Baud Rate Value"] +pub struct HSBAUD_R(crate::FieldReader); +impl HSBAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + HSBAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HSBAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HSBAUD` writer - High Speed Baud Rate Value"] +pub struct HSBAUD_W<'a> { + w: &'a mut W, +} +impl<'a> HSBAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +#[doc = "Field `HSBAUDLOW` reader - High Speed Baud Rate Value Low"] +pub struct HSBAUDLOW_R(crate::FieldReader); +impl HSBAUDLOW_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + HSBAUDLOW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HSBAUDLOW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HSBAUDLOW` writer - High Speed Baud Rate Value Low"] +pub struct HSBAUDLOW_W<'a> { + w: &'a mut W, +} +impl<'a> HSBAUDLOW_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 24)) | ((value as u32 & 0xff) << 24); + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Baud Rate Value Low"] + #[inline(always)] + pub fn baudlow(&self) -> BAUDLOW_R { + BAUDLOW_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - High Speed Baud Rate Value"] + #[inline(always)] + pub fn hsbaud(&self) -> HSBAUD_R { + HSBAUD_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - High Speed Baud Rate Value Low"] + #[inline(always)] + pub fn hsbaudlow(&self) -> HSBAUDLOW_R { + HSBAUDLOW_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Bits 8:15 - Baud Rate Value Low"] + #[inline(always)] + pub fn baudlow(&mut self) -> BAUDLOW_W { + BAUDLOW_W { w: self } + } + #[doc = "Bits 16:23 - High Speed Baud Rate Value"] + #[inline(always)] + pub fn hsbaud(&mut self) -> HSBAUD_W { + HSBAUD_W { w: self } + } + #[doc = "Bits 24:31 - High Speed Baud Rate Value Low"] + #[inline(always)] + pub fn hsbaudlow(&mut self) -> HSBAUDLOW_W { + HSBAUDLOW_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud](index.html) module"] +pub struct BAUD_SPEC; +impl crate::RegisterSpec for BAUD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [baud::R](R) reader structure"] +impl crate::Readable for BAUD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud::W](W) writer structure"] +impl crate::Writable for BAUD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD to value 0"] +impl crate::Resettable for BAUD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sercom0/i2cm/ctrla.rs b/pac/atsamc21e/src/sercom0/i2cm/ctrla.rs new file mode 100644 index 000000000000..34fa668b7967 --- /dev/null +++ b/pac/atsamc21e/src/sercom0/i2cm/ctrla.rs @@ -0,0 +1,903 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: USART with external clock"] + USART_EXT_CLK = 0, + #[doc = "1: USART with internal clock"] + USART_INT_CLK = 1, + #[doc = "2: SPI in slave operation"] + SPI_SLAVE = 2, + #[doc = "3: SPI in master operation"] + SPI_MASTER = 3, + #[doc = "4: I2C slave operation"] + I2C_SLAVE = 4, + #[doc = "5: I2C master operation"] + I2C_MASTER = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::USART_EXT_CLK), + 1 => Some(MODE_A::USART_INT_CLK), + 2 => Some(MODE_A::SPI_SLAVE), + 3 => Some(MODE_A::SPI_MASTER), + 4 => Some(MODE_A::I2C_SLAVE), + 5 => Some(MODE_A::I2C_MASTER), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_EXT_CLK`"] + #[inline(always)] + pub fn is_usart_ext_clk(&self) -> bool { + **self == MODE_A::USART_EXT_CLK + } + #[doc = "Checks if the value of the field is `USART_INT_CLK`"] + #[inline(always)] + pub fn is_usart_int_clk(&self) -> bool { + **self == MODE_A::USART_INT_CLK + } + #[doc = "Checks if the value of the field is `SPI_SLAVE`"] + #[inline(always)] + pub fn is_spi_slave(&self) -> bool { + **self == MODE_A::SPI_SLAVE + } + #[doc = "Checks if the value of the field is `SPI_MASTER`"] + #[inline(always)] + pub fn is_spi_master(&self) -> bool { + **self == MODE_A::SPI_MASTER + } + #[doc = "Checks if the value of the field is `I2C_SLAVE`"] + #[inline(always)] + pub fn is_i2c_slave(&self) -> bool { + **self == MODE_A::I2C_SLAVE + } + #[doc = "Checks if the value of the field is `I2C_MASTER`"] + #[inline(always)] + pub fn is_i2c_master(&self) -> bool { + **self == MODE_A::I2C_MASTER + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART with external clock"] + #[inline(always)] + pub fn usart_ext_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_EXT_CLK) + } + #[doc = "USART with internal clock"] + #[inline(always)] + pub fn usart_int_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_INT_CLK) + } + #[doc = "SPI in slave operation"] + #[inline(always)] + pub fn spi_slave(self) -> &'a mut W { + self.variant(MODE_A::SPI_SLAVE) + } + #[doc = "SPI in master operation"] + #[inline(always)] + pub fn spi_master(self) -> &'a mut W { + self.variant(MODE_A::SPI_MASTER) + } + #[doc = "I2C slave operation"] + #[inline(always)] + pub fn i2c_slave(self) -> &'a mut W { + self.variant(MODE_A::I2C_SLAVE) + } + #[doc = "I2C master operation"] + #[inline(always)] + pub fn i2c_master(self) -> &'a mut W { + self.variant(MODE_A::I2C_MASTER) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 2)) | ((value as u32 & 0x07) << 2); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `PINOUT` reader - Pin Usage"] +pub struct PINOUT_R(crate::FieldReader); +impl PINOUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PINOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PINOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PINOUT` writer - Pin Usage"] +pub struct PINOUT_W<'a> { + w: &'a mut W, +} +impl<'a> PINOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "SDA Hold Time\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SDAHOLD_A { + #[doc = "0: Disabled"] + DISABLE = 0, + #[doc = "1: 50-100ns hold time"] + _75NS = 1, + #[doc = "2: 300-600ns hold time"] + _450NS = 2, + #[doc = "3: 400-800ns hold time"] + _600NS = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SDAHOLD_A) -> Self { + variant as _ + } +} +#[doc = "Field `SDAHOLD` reader - SDA Hold Time"] +pub struct SDAHOLD_R(crate::FieldReader); +impl SDAHOLD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SDAHOLD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SDAHOLD_A { + match self.bits { + 0 => SDAHOLD_A::DISABLE, + 1 => SDAHOLD_A::_75NS, + 2 => SDAHOLD_A::_450NS, + 3 => SDAHOLD_A::_600NS, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == SDAHOLD_A::DISABLE + } + #[doc = "Checks if the value of the field is `_75NS`"] + #[inline(always)] + pub fn is_75ns(&self) -> bool { + **self == SDAHOLD_A::_75NS + } + #[doc = "Checks if the value of the field is `_450NS`"] + #[inline(always)] + pub fn is_450ns(&self) -> bool { + **self == SDAHOLD_A::_450NS + } + #[doc = "Checks if the value of the field is `_600NS`"] + #[inline(always)] + pub fn is_600ns(&self) -> bool { + **self == SDAHOLD_A::_600NS + } +} +impl core::ops::Deref for SDAHOLD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SDAHOLD` writer - SDA Hold Time"] +pub struct SDAHOLD_W<'a> { + w: &'a mut W, +} +impl<'a> SDAHOLD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SDAHOLD_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(SDAHOLD_A::DISABLE) + } + #[doc = "50-100ns hold time"] + #[inline(always)] + pub fn _75ns(self) -> &'a mut W { + self.variant(SDAHOLD_A::_75NS) + } + #[doc = "300-600ns hold time"] + #[inline(always)] + pub fn _450ns(self) -> &'a mut W { + self.variant(SDAHOLD_A::_450NS) + } + #[doc = "400-800ns hold time"] + #[inline(always)] + pub fn _600ns(self) -> &'a mut W { + self.variant(SDAHOLD_A::_600NS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 20)) | ((value as u32 & 0x03) << 20); + self.w + } +} +#[doc = "Field `MEXTTOEN` reader - Master SCL Low Extend Timeout"] +pub struct MEXTTOEN_R(crate::FieldReader); +impl MEXTTOEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MEXTTOEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MEXTTOEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MEXTTOEN` writer - Master SCL Low Extend Timeout"] +pub struct MEXTTOEN_W<'a> { + w: &'a mut W, +} +impl<'a> MEXTTOEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `SEXTTOEN` reader - Slave SCL Low Extend Timeout"] +pub struct SEXTTOEN_R(crate::FieldReader); +impl SEXTTOEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SEXTTOEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEXTTOEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEXTTOEN` writer - Slave SCL Low Extend Timeout"] +pub struct SEXTTOEN_W<'a> { + w: &'a mut W, +} +impl<'a> SEXTTOEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Transfer Speed\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SPEED_A { + #[doc = "0: Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz"] + STANDARD_AND_FAST_MODE = 0, + #[doc = "1: Fast-mode Plus Upto 1MHz"] + FASTPLUS_MODE = 1, + #[doc = "2: High-speed mode Upto 3.4MHz"] + HIGH_SPEED_MODE = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SPEED_A) -> Self { + variant as _ + } +} +#[doc = "Field `SPEED` reader - Transfer Speed"] +pub struct SPEED_R(crate::FieldReader); +impl SPEED_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SPEED_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SPEED_A::STANDARD_AND_FAST_MODE), + 1 => Some(SPEED_A::FASTPLUS_MODE), + 2 => Some(SPEED_A::HIGH_SPEED_MODE), + _ => None, + } + } + #[doc = "Checks if the value of the field is `STANDARD_AND_FAST_MODE`"] + #[inline(always)] + pub fn is_standard_and_fast_mode(&self) -> bool { + **self == SPEED_A::STANDARD_AND_FAST_MODE + } + #[doc = "Checks if the value of the field is `FASTPLUS_MODE`"] + #[inline(always)] + pub fn is_fastplus_mode(&self) -> bool { + **self == SPEED_A::FASTPLUS_MODE + } + #[doc = "Checks if the value of the field is `HIGH_SPEED_MODE`"] + #[inline(always)] + pub fn is_high_speed_mode(&self) -> bool { + **self == SPEED_A::HIGH_SPEED_MODE + } +} +impl core::ops::Deref for SPEED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SPEED` writer - Transfer Speed"] +pub struct SPEED_W<'a> { + w: &'a mut W, +} +impl<'a> SPEED_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SPEED_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz"] + #[inline(always)] + pub fn standard_and_fast_mode(self) -> &'a mut W { + self.variant(SPEED_A::STANDARD_AND_FAST_MODE) + } + #[doc = "Fast-mode Plus Upto 1MHz"] + #[inline(always)] + pub fn fastplus_mode(self) -> &'a mut W { + self.variant(SPEED_A::FASTPLUS_MODE) + } + #[doc = "High-speed mode Upto 3.4MHz"] + #[inline(always)] + pub fn high_speed_mode(self) -> &'a mut W { + self.variant(SPEED_A::HIGH_SPEED_MODE) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 24)) | ((value as u32 & 0x03) << 24); + self.w + } +} +#[doc = "Field `SCLSM` reader - SCL Clock Stretch Mode"] +pub struct SCLSM_R(crate::FieldReader); +impl SCLSM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SCLSM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SCLSM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SCLSM` writer - SCL Clock Stretch Mode"] +pub struct SCLSM_W<'a> { + w: &'a mut W, +} +impl<'a> SCLSM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +#[doc = "Inactive Time-Out\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum INACTOUT_A { + #[doc = "0: Disabled"] + DISABLE = 0, + #[doc = "1: 5-6 SCL Time-Out(50-60us)"] + _55US = 1, + #[doc = "2: 10-11 SCL Time-Out(100-110us)"] + _105US = 2, + #[doc = "3: 20-21 SCL Time-Out(200-210us)"] + _205US = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: INACTOUT_A) -> Self { + variant as _ + } +} +#[doc = "Field `INACTOUT` reader - Inactive Time-Out"] +pub struct INACTOUT_R(crate::FieldReader); +impl INACTOUT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + INACTOUT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INACTOUT_A { + match self.bits { + 0 => INACTOUT_A::DISABLE, + 1 => INACTOUT_A::_55US, + 2 => INACTOUT_A::_105US, + 3 => INACTOUT_A::_205US, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == INACTOUT_A::DISABLE + } + #[doc = "Checks if the value of the field is `_55US`"] + #[inline(always)] + pub fn is_55us(&self) -> bool { + **self == INACTOUT_A::_55US + } + #[doc = "Checks if the value of the field is `_105US`"] + #[inline(always)] + pub fn is_105us(&self) -> bool { + **self == INACTOUT_A::_105US + } + #[doc = "Checks if the value of the field is `_205US`"] + #[inline(always)] + pub fn is_205us(&self) -> bool { + **self == INACTOUT_A::_205US + } +} +impl core::ops::Deref for INACTOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INACTOUT` writer - Inactive Time-Out"] +pub struct INACTOUT_W<'a> { + w: &'a mut W, +} +impl<'a> INACTOUT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: INACTOUT_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(INACTOUT_A::DISABLE) + } + #[doc = "5-6 SCL Time-Out(50-60us)"] + #[inline(always)] + pub fn _55us(self) -> &'a mut W { + self.variant(INACTOUT_A::_55US) + } + #[doc = "10-11 SCL Time-Out(100-110us)"] + #[inline(always)] + pub fn _105us(self) -> &'a mut W { + self.variant(INACTOUT_A::_105US) + } + #[doc = "20-21 SCL Time-Out(200-210us)"] + #[inline(always)] + pub fn _205us(self) -> &'a mut W { + self.variant(INACTOUT_A::_205US) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 28)) | ((value as u32 & 0x03) << 28); + self.w + } +} +#[doc = "Field `LOWTOUTEN` reader - SCL Low Timeout Enable"] +pub struct LOWTOUTEN_R(crate::FieldReader); +impl LOWTOUTEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LOWTOUTEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOWTOUTEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LOWTOUTEN` writer - SCL Low Timeout Enable"] +pub struct LOWTOUTEN_W<'a> { + w: &'a mut W, +} +impl<'a> LOWTOUTEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x07) as u8) + } + #[doc = "Bit 7 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 16 - Pin Usage"] + #[inline(always)] + pub fn pinout(&self) -> PINOUT_R { + PINOUT_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bits 20:21 - SDA Hold Time"] + #[inline(always)] + pub fn sdahold(&self) -> SDAHOLD_R { + SDAHOLD_R::new(((self.bits >> 20) & 0x03) as u8) + } + #[doc = "Bit 22 - Master SCL Low Extend Timeout"] + #[inline(always)] + pub fn mexttoen(&self) -> MEXTTOEN_R { + MEXTTOEN_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttoen(&self) -> SEXTTOEN_R { + SEXTTOEN_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bits 24:25 - Transfer Speed"] + #[inline(always)] + pub fn speed(&self) -> SPEED_R { + SPEED_R::new(((self.bits >> 24) & 0x03) as u8) + } + #[doc = "Bit 27 - SCL Clock Stretch Mode"] + #[inline(always)] + pub fn sclsm(&self) -> SCLSM_R { + SCLSM_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bits 28:29 - Inactive Time-Out"] + #[inline(always)] + pub fn inactout(&self) -> INACTOUT_R { + INACTOUT_R::new(((self.bits >> 28) & 0x03) as u8) + } + #[doc = "Bit 30 - SCL Low Timeout Enable"] + #[inline(always)] + pub fn lowtouten(&self) -> LOWTOUTEN_R { + LOWTOUTEN_R::new(((self.bits >> 30) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 7 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 16 - Pin Usage"] + #[inline(always)] + pub fn pinout(&mut self) -> PINOUT_W { + PINOUT_W { w: self } + } + #[doc = "Bits 20:21 - SDA Hold Time"] + #[inline(always)] + pub fn sdahold(&mut self) -> SDAHOLD_W { + SDAHOLD_W { w: self } + } + #[doc = "Bit 22 - Master SCL Low Extend Timeout"] + #[inline(always)] + pub fn mexttoen(&mut self) -> MEXTTOEN_W { + MEXTTOEN_W { w: self } + } + #[doc = "Bit 23 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttoen(&mut self) -> SEXTTOEN_W { + SEXTTOEN_W { w: self } + } + #[doc = "Bits 24:25 - Transfer Speed"] + #[inline(always)] + pub fn speed(&mut self) -> SPEED_W { + SPEED_W { w: self } + } + #[doc = "Bit 27 - SCL Clock Stretch Mode"] + #[inline(always)] + pub fn sclsm(&mut self) -> SCLSM_W { + SCLSM_W { w: self } + } + #[doc = "Bits 28:29 - Inactive Time-Out"] + #[inline(always)] + pub fn inactout(&mut self) -> INACTOUT_W { + INACTOUT_W { w: self } + } + #[doc = "Bit 30 - SCL Low Timeout Enable"] + #[inline(always)] + pub fn lowtouten(&mut self) -> LOWTOUTEN_W { + LOWTOUTEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sercom0/i2cm/ctrlb.rs b/pac/atsamc21e/src/sercom0/i2cm/ctrlb.rs new file mode 100644 index 000000000000..ce534463c0da --- /dev/null +++ b/pac/atsamc21e/src/sercom0/i2cm/ctrlb.rs @@ -0,0 +1,244 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SMEN` reader - Smart Mode Enable"] +pub struct SMEN_R(crate::FieldReader); +impl SMEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SMEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SMEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SMEN` writer - Smart Mode Enable"] +pub struct SMEN_W<'a> { + w: &'a mut W, +} +impl<'a> SMEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `QCEN` reader - Quick Command Enable"] +pub struct QCEN_R(crate::FieldReader); +impl QCEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + QCEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for QCEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `QCEN` writer - Quick Command Enable"] +pub struct QCEN_W<'a> { + w: &'a mut W, +} +impl<'a> QCEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Field `ACKACT` reader - Acknowledge Action"] +pub struct ACKACT_R(crate::FieldReader); +impl ACKACT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ACKACT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ACKACT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ACKACT` writer - Acknowledge Action"] +pub struct ACKACT_W<'a> { + w: &'a mut W, +} +impl<'a> ACKACT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +impl R { + #[doc = "Bit 8 - Smart Mode Enable"] + #[inline(always)] + pub fn smen(&self) -> SMEN_R { + SMEN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Quick Command Enable"] + #[inline(always)] + pub fn qcen(&self) -> QCEN_R { + QCEN_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bits 16:17 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bit 18 - Acknowledge Action"] + #[inline(always)] + pub fn ackact(&self) -> ACKACT_R { + ACKACT_R::new(((self.bits >> 18) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 8 - Smart Mode Enable"] + #[inline(always)] + pub fn smen(&mut self) -> SMEN_W { + SMEN_W { w: self } + } + #[doc = "Bit 9 - Quick Command Enable"] + #[inline(always)] + pub fn qcen(&mut self) -> QCEN_W { + QCEN_W { w: self } + } + #[doc = "Bits 16:17 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Bit 18 - Acknowledge Action"] + #[inline(always)] + pub fn ackact(&mut self) -> ACKACT_W { + ACKACT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sercom0/i2cm/data.rs b/pac/atsamc21e/src/sercom0/i2cm/data.rs new file mode 100644 index 000000000000..cf204596d3a6 --- /dev/null +++ b/pac/atsamc21e/src/sercom0/i2cm/data.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data Value"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data Value"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Data Value"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Value"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sercom0/i2cm/dbgctrl.rs b/pac/atsamc21e/src/sercom0/i2cm/dbgctrl.rs new file mode 100644 index 000000000000..0fffdb4c6e39 --- /dev/null +++ b/pac/atsamc21e/src/sercom0/i2cm/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGSTOP` reader - Debug Mode"] +pub struct DBGSTOP_R(crate::FieldReader); +impl DBGSTOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGSTOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGSTOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGSTOP` writer - Debug Mode"] +pub struct DBGSTOP_W<'a> { + w: &'a mut W, +} +impl<'a> DBGSTOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&self) -> DBGSTOP_R { + DBGSTOP_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&mut self) -> DBGSTOP_W { + DBGSTOP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sercom0/i2cm/intenclr.rs b/pac/atsamc21e/src/sercom0/i2cm/intenclr.rs new file mode 100644 index 000000000000..17f067a55656 --- /dev/null +++ b/pac/atsamc21e/src/sercom0/i2cm/intenclr.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MB` reader - Master On Bus Interrupt Disable"] +pub struct MB_R(crate::FieldReader); +impl MB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MB` writer - Master On Bus Interrupt Disable"] +pub struct MB_W<'a> { + w: &'a mut W, +} +impl<'a> MB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SB` reader - Slave On Bus Interrupt Disable"] +pub struct SB_R(crate::FieldReader); +impl SB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SB` writer - Slave On Bus Interrupt Disable"] +pub struct SB_W<'a> { + w: &'a mut W, +} +impl<'a> SB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Disable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Disable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Master On Bus Interrupt Disable"] + #[inline(always)] + pub fn mb(&self) -> MB_R { + MB_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Slave On Bus Interrupt Disable"] + #[inline(always)] + pub fn sb(&self) -> SB_R { + SB_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Master On Bus Interrupt Disable"] + #[inline(always)] + pub fn mb(&mut self) -> MB_W { + MB_W { w: self } + } + #[doc = "Bit 1 - Slave On Bus Interrupt Disable"] + #[inline(always)] + pub fn sb(&mut self) -> SB_W { + SB_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sercom0/i2cm/intenset.rs b/pac/atsamc21e/src/sercom0/i2cm/intenset.rs new file mode 100644 index 000000000000..a0cbf96b3aa0 --- /dev/null +++ b/pac/atsamc21e/src/sercom0/i2cm/intenset.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MB` reader - Master On Bus Interrupt Enable"] +pub struct MB_R(crate::FieldReader); +impl MB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MB` writer - Master On Bus Interrupt Enable"] +pub struct MB_W<'a> { + w: &'a mut W, +} +impl<'a> MB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SB` reader - Slave On Bus Interrupt Enable"] +pub struct SB_R(crate::FieldReader); +impl SB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SB` writer - Slave On Bus Interrupt Enable"] +pub struct SB_W<'a> { + w: &'a mut W, +} +impl<'a> SB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Master On Bus Interrupt Enable"] + #[inline(always)] + pub fn mb(&self) -> MB_R { + MB_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Slave On Bus Interrupt Enable"] + #[inline(always)] + pub fn sb(&self) -> SB_R { + SB_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Master On Bus Interrupt Enable"] + #[inline(always)] + pub fn mb(&mut self) -> MB_W { + MB_W { w: self } + } + #[doc = "Bit 1 - Slave On Bus Interrupt Enable"] + #[inline(always)] + pub fn sb(&mut self) -> SB_W { + SB_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sercom0/i2cm/intflag.rs b/pac/atsamc21e/src/sercom0/i2cm/intflag.rs new file mode 100644 index 000000000000..0fb0d2b9060c --- /dev/null +++ b/pac/atsamc21e/src/sercom0/i2cm/intflag.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MB` reader - Master On Bus Interrupt"] +pub struct MB_R(crate::FieldReader); +impl MB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MB` writer - Master On Bus Interrupt"] +pub struct MB_W<'a> { + w: &'a mut W, +} +impl<'a> MB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SB` reader - Slave On Bus Interrupt"] +pub struct SB_R(crate::FieldReader); +impl SB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SB` writer - Slave On Bus Interrupt"] +pub struct SB_W<'a> { + w: &'a mut W, +} +impl<'a> SB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Master On Bus Interrupt"] + #[inline(always)] + pub fn mb(&self) -> MB_R { + MB_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Slave On Bus Interrupt"] + #[inline(always)] + pub fn sb(&self) -> SB_R { + SB_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Master On Bus Interrupt"] + #[inline(always)] + pub fn mb(&mut self) -> MB_W { + MB_W { w: self } + } + #[doc = "Bit 1 - Slave On Bus Interrupt"] + #[inline(always)] + pub fn sb(&mut self) -> SB_W { + SB_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sercom0/i2cm/status.rs b/pac/atsamc21e/src/sercom0/i2cm/status.rs new file mode 100644 index 000000000000..95af23673ec4 --- /dev/null +++ b/pac/atsamc21e/src/sercom0/i2cm/status.rs @@ -0,0 +1,479 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BUSERR` reader - Bus Error"] +pub struct BUSERR_R(crate::FieldReader); +impl BUSERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSERR` writer - Bus Error"] +pub struct BUSERR_W<'a> { + w: &'a mut W, +} +impl<'a> BUSERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `ARBLOST` reader - Arbitration Lost"] +pub struct ARBLOST_R(crate::FieldReader); +impl ARBLOST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ARBLOST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ARBLOST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ARBLOST` writer - Arbitration Lost"] +pub struct ARBLOST_W<'a> { + w: &'a mut W, +} +impl<'a> ARBLOST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXNACK` reader - Received Not Acknowledge"] +pub struct RXNACK_R(crate::FieldReader); +impl RXNACK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXNACK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXNACK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXNACK` writer - Received Not Acknowledge"] +pub struct RXNACK_W<'a> { + w: &'a mut W, +} +impl<'a> RXNACK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `BUSSTATE` reader - Bus State"] +pub struct BUSSTATE_R(crate::FieldReader); +impl BUSSTATE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BUSSTATE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSSTATE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSSTATE` writer - Bus State"] +pub struct BUSSTATE_W<'a> { + w: &'a mut W, +} +impl<'a> BUSSTATE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u16 & 0x03) << 4); + self.w + } +} +#[doc = "Field `LOWTOUT` reader - SCL Low Timeout"] +pub struct LOWTOUT_R(crate::FieldReader); +impl LOWTOUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LOWTOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOWTOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LOWTOUT` writer - SCL Low Timeout"] +pub struct LOWTOUT_W<'a> { + w: &'a mut W, +} +impl<'a> LOWTOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `CLKHOLD` reader - Clock Hold"] +pub struct CLKHOLD_R(crate::FieldReader); +impl CLKHOLD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKHOLD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKHOLD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKHOLD` writer - Clock Hold"] +pub struct CLKHOLD_W<'a> { + w: &'a mut W, +} +impl<'a> CLKHOLD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `MEXTTOUT` reader - Master SCL Low Extend Timeout"] +pub struct MEXTTOUT_R(crate::FieldReader); +impl MEXTTOUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MEXTTOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MEXTTOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MEXTTOUT` writer - Master SCL Low Extend Timeout"] +pub struct MEXTTOUT_W<'a> { + w: &'a mut W, +} +impl<'a> MEXTTOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `SEXTTOUT` reader - Slave SCL Low Extend Timeout"] +pub struct SEXTTOUT_R(crate::FieldReader); +impl SEXTTOUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SEXTTOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEXTTOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEXTTOUT` writer - Slave SCL Low Extend Timeout"] +pub struct SEXTTOUT_W<'a> { + w: &'a mut W, +} +impl<'a> SEXTTOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `LENERR` reader - Length Error"] +pub struct LENERR_R(crate::FieldReader); +impl LENERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LENERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LENERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LENERR` writer - Length Error"] +pub struct LENERR_W<'a> { + w: &'a mut W, +} +impl<'a> LENERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u16 & 0x01) << 10); + self.w + } +} +impl R { + #[doc = "Bit 0 - Bus Error"] + #[inline(always)] + pub fn buserr(&self) -> BUSERR_R { + BUSERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Arbitration Lost"] + #[inline(always)] + pub fn arblost(&self) -> ARBLOST_R { + ARBLOST_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Received Not Acknowledge"] + #[inline(always)] + pub fn rxnack(&self) -> RXNACK_R { + RXNACK_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 4:5 - Bus State"] + #[inline(always)] + pub fn busstate(&self) -> BUSSTATE_R { + BUSSTATE_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bit 6 - SCL Low Timeout"] + #[inline(always)] + pub fn lowtout(&self) -> LOWTOUT_R { + LOWTOUT_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Clock Hold"] + #[inline(always)] + pub fn clkhold(&self) -> CLKHOLD_R { + CLKHOLD_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Master SCL Low Extend Timeout"] + #[inline(always)] + pub fn mexttout(&self) -> MEXTTOUT_R { + MEXTTOUT_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttout(&self) -> SEXTTOUT_R { + SEXTTOUT_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Length Error"] + #[inline(always)] + pub fn lenerr(&self) -> LENERR_R { + LENERR_R::new(((self.bits >> 10) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Bus Error"] + #[inline(always)] + pub fn buserr(&mut self) -> BUSERR_W { + BUSERR_W { w: self } + } + #[doc = "Bit 1 - Arbitration Lost"] + #[inline(always)] + pub fn arblost(&mut self) -> ARBLOST_W { + ARBLOST_W { w: self } + } + #[doc = "Bit 2 - Received Not Acknowledge"] + #[inline(always)] + pub fn rxnack(&mut self) -> RXNACK_W { + RXNACK_W { w: self } + } + #[doc = "Bits 4:5 - Bus State"] + #[inline(always)] + pub fn busstate(&mut self) -> BUSSTATE_W { + BUSSTATE_W { w: self } + } + #[doc = "Bit 6 - SCL Low Timeout"] + #[inline(always)] + pub fn lowtout(&mut self) -> LOWTOUT_W { + LOWTOUT_W { w: self } + } + #[doc = "Bit 7 - Clock Hold"] + #[inline(always)] + pub fn clkhold(&mut self) -> CLKHOLD_W { + CLKHOLD_W { w: self } + } + #[doc = "Bit 8 - Master SCL Low Extend Timeout"] + #[inline(always)] + pub fn mexttout(&mut self) -> MEXTTOUT_W { + MEXTTOUT_W { w: self } + } + #[doc = "Bit 9 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttout(&mut self) -> SEXTTOUT_W { + SEXTTOUT_W { w: self } + } + #[doc = "Bit 10 - Length Error"] + #[inline(always)] + pub fn lenerr(&mut self) -> LENERR_W { + LENERR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sercom0/i2cm/syncbusy.rs b/pac/atsamc21e/src/sercom0/i2cm/syncbusy.rs new file mode 100644 index 000000000000..87dd418d1cd3 --- /dev/null +++ b/pac/atsamc21e/src/sercom0/i2cm/syncbusy.rs @@ -0,0 +1,93 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - SERCOM Enable Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYSOP` reader - System Operation Synchronization Busy"] +pub struct SYSOP_R(crate::FieldReader); +impl SYSOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYSOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYSOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM Enable Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - System Operation Synchronization Busy"] + #[inline(always)] + pub fn sysop(&self) -> SYSOP_R { + SYSOP_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +#[doc = "I2CM Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sercom0/i2cs.rs b/pac/atsamc21e/src/sercom0/i2cs.rs new file mode 100644 index 000000000000..baf9513c6cc1 --- /dev/null +++ b/pac/atsamc21e/src/sercom0/i2cs.rs @@ -0,0 +1,36 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "I2CS Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "I2CS Control B"] +pub mod ctrlb; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "I2CS Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "I2CS Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "I2CS Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "I2CS Status"] +pub mod status; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "I2CS Synchronization Busy"] +pub mod syncbusy; +#[doc = "ADDR register accessor: an alias for `Reg`"] +pub type ADDR = crate::Reg; +#[doc = "I2CS Address"] +pub mod addr; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "I2CS Data"] +pub mod data; diff --git a/pac/atsamc21e/src/sercom0/i2cs/addr.rs b/pac/atsamc21e/src/sercom0/i2cs/addr.rs new file mode 100644 index 000000000000..c1b69ee22891 --- /dev/null +++ b/pac/atsamc21e/src/sercom0/i2cs/addr.rs @@ -0,0 +1,234 @@ +#[doc = "Register `ADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `GENCEN` reader - General Call Address Enable"] +pub struct GENCEN_R(crate::FieldReader); +impl GENCEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENCEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENCEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENCEN` writer - General Call Address Enable"] +pub struct GENCEN_W<'a> { + w: &'a mut W, +} +impl<'a> GENCEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ADDR` reader - Address Value"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - Address Value"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03ff << 1)) | ((value as u32 & 0x03ff) << 1); + self.w + } +} +#[doc = "Field `TENBITEN` reader - Ten Bit Addressing Enable"] +pub struct TENBITEN_R(crate::FieldReader); +impl TENBITEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TENBITEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TENBITEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TENBITEN` writer - Ten Bit Addressing Enable"] +pub struct TENBITEN_W<'a> { + w: &'a mut W, +} +impl<'a> TENBITEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `ADDRMASK` reader - Address Mask"] +pub struct ADDRMASK_R(crate::FieldReader); +impl ADDRMASK_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + ADDRMASK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDRMASK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDRMASK` writer - Address Mask"] +pub struct ADDRMASK_W<'a> { + w: &'a mut W, +} +impl<'a> ADDRMASK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03ff << 17)) | ((value as u32 & 0x03ff) << 17); + self.w + } +} +impl R { + #[doc = "Bit 0 - General Call Address Enable"] + #[inline(always)] + pub fn gencen(&self) -> GENCEN_R { + GENCEN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bits 1:10 - Address Value"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new(((self.bits >> 1) & 0x03ff) as u16) + } + #[doc = "Bit 15 - Ten Bit Addressing Enable"] + #[inline(always)] + pub fn tenbiten(&self) -> TENBITEN_R { + TENBITEN_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 17:26 - Address Mask"] + #[inline(always)] + pub fn addrmask(&self) -> ADDRMASK_R { + ADDRMASK_R::new(((self.bits >> 17) & 0x03ff) as u16) + } +} +impl W { + #[doc = "Bit 0 - General Call Address Enable"] + #[inline(always)] + pub fn gencen(&mut self) -> GENCEN_W { + GENCEN_W { w: self } + } + #[doc = "Bits 1:10 - Address Value"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Bit 15 - Ten Bit Addressing Enable"] + #[inline(always)] + pub fn tenbiten(&mut self) -> TENBITEN_W { + TENBITEN_W { w: self } + } + #[doc = "Bits 17:26 - Address Mask"] + #[inline(always)] + pub fn addrmask(&mut self) -> ADDRMASK_W { + ADDRMASK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [addr](index.html) module"] +pub struct ADDR_SPEC; +impl crate::RegisterSpec for ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [addr::R](R) reader structure"] +impl crate::Readable for ADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [addr::W](W) writer structure"] +impl crate::Writable for ADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ADDR to value 0"] +impl crate::Resettable for ADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sercom0/i2cs/ctrla.rs b/pac/atsamc21e/src/sercom0/i2cs/ctrla.rs new file mode 100644 index 000000000000..ec93812b004f --- /dev/null +++ b/pac/atsamc21e/src/sercom0/i2cs/ctrla.rs @@ -0,0 +1,744 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: USART with external clock"] + USART_EXT_CLK = 0, + #[doc = "1: USART with internal clock"] + USART_INT_CLK = 1, + #[doc = "2: SPI in slave operation"] + SPI_SLAVE = 2, + #[doc = "3: SPI in master operation"] + SPI_MASTER = 3, + #[doc = "4: I2C slave operation"] + I2C_SLAVE = 4, + #[doc = "5: I2C master operation"] + I2C_MASTER = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::USART_EXT_CLK), + 1 => Some(MODE_A::USART_INT_CLK), + 2 => Some(MODE_A::SPI_SLAVE), + 3 => Some(MODE_A::SPI_MASTER), + 4 => Some(MODE_A::I2C_SLAVE), + 5 => Some(MODE_A::I2C_MASTER), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_EXT_CLK`"] + #[inline(always)] + pub fn is_usart_ext_clk(&self) -> bool { + **self == MODE_A::USART_EXT_CLK + } + #[doc = "Checks if the value of the field is `USART_INT_CLK`"] + #[inline(always)] + pub fn is_usart_int_clk(&self) -> bool { + **self == MODE_A::USART_INT_CLK + } + #[doc = "Checks if the value of the field is `SPI_SLAVE`"] + #[inline(always)] + pub fn is_spi_slave(&self) -> bool { + **self == MODE_A::SPI_SLAVE + } + #[doc = "Checks if the value of the field is `SPI_MASTER`"] + #[inline(always)] + pub fn is_spi_master(&self) -> bool { + **self == MODE_A::SPI_MASTER + } + #[doc = "Checks if the value of the field is `I2C_SLAVE`"] + #[inline(always)] + pub fn is_i2c_slave(&self) -> bool { + **self == MODE_A::I2C_SLAVE + } + #[doc = "Checks if the value of the field is `I2C_MASTER`"] + #[inline(always)] + pub fn is_i2c_master(&self) -> bool { + **self == MODE_A::I2C_MASTER + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART with external clock"] + #[inline(always)] + pub fn usart_ext_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_EXT_CLK) + } + #[doc = "USART with internal clock"] + #[inline(always)] + pub fn usart_int_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_INT_CLK) + } + #[doc = "SPI in slave operation"] + #[inline(always)] + pub fn spi_slave(self) -> &'a mut W { + self.variant(MODE_A::SPI_SLAVE) + } + #[doc = "SPI in master operation"] + #[inline(always)] + pub fn spi_master(self) -> &'a mut W { + self.variant(MODE_A::SPI_MASTER) + } + #[doc = "I2C slave operation"] + #[inline(always)] + pub fn i2c_slave(self) -> &'a mut W { + self.variant(MODE_A::I2C_SLAVE) + } + #[doc = "I2C master operation"] + #[inline(always)] + pub fn i2c_master(self) -> &'a mut W { + self.variant(MODE_A::I2C_MASTER) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 2)) | ((value as u32 & 0x07) << 2); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `PINOUT` reader - Pin Usage"] +pub struct PINOUT_R(crate::FieldReader); +impl PINOUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PINOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PINOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PINOUT` writer - Pin Usage"] +pub struct PINOUT_W<'a> { + w: &'a mut W, +} +impl<'a> PINOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "SDA Hold Time\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SDAHOLD_A { + #[doc = "0: Disabled"] + DISABLE = 0, + #[doc = "1: 50-100ns hold time"] + _75NS = 1, + #[doc = "2: 300-600ns hold time"] + _450NS = 2, + #[doc = "3: 400-800ns hold time"] + _600NS = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SDAHOLD_A) -> Self { + variant as _ + } +} +#[doc = "Field `SDAHOLD` reader - SDA Hold Time"] +pub struct SDAHOLD_R(crate::FieldReader); +impl SDAHOLD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SDAHOLD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SDAHOLD_A { + match self.bits { + 0 => SDAHOLD_A::DISABLE, + 1 => SDAHOLD_A::_75NS, + 2 => SDAHOLD_A::_450NS, + 3 => SDAHOLD_A::_600NS, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == SDAHOLD_A::DISABLE + } + #[doc = "Checks if the value of the field is `_75NS`"] + #[inline(always)] + pub fn is_75ns(&self) -> bool { + **self == SDAHOLD_A::_75NS + } + #[doc = "Checks if the value of the field is `_450NS`"] + #[inline(always)] + pub fn is_450ns(&self) -> bool { + **self == SDAHOLD_A::_450NS + } + #[doc = "Checks if the value of the field is `_600NS`"] + #[inline(always)] + pub fn is_600ns(&self) -> bool { + **self == SDAHOLD_A::_600NS + } +} +impl core::ops::Deref for SDAHOLD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SDAHOLD` writer - SDA Hold Time"] +pub struct SDAHOLD_W<'a> { + w: &'a mut W, +} +impl<'a> SDAHOLD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SDAHOLD_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(SDAHOLD_A::DISABLE) + } + #[doc = "50-100ns hold time"] + #[inline(always)] + pub fn _75ns(self) -> &'a mut W { + self.variant(SDAHOLD_A::_75NS) + } + #[doc = "300-600ns hold time"] + #[inline(always)] + pub fn _450ns(self) -> &'a mut W { + self.variant(SDAHOLD_A::_450NS) + } + #[doc = "400-800ns hold time"] + #[inline(always)] + pub fn _600ns(self) -> &'a mut W { + self.variant(SDAHOLD_A::_600NS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 20)) | ((value as u32 & 0x03) << 20); + self.w + } +} +#[doc = "Field `SEXTTOEN` reader - Slave SCL Low Extend Timeout"] +pub struct SEXTTOEN_R(crate::FieldReader); +impl SEXTTOEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SEXTTOEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEXTTOEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEXTTOEN` writer - Slave SCL Low Extend Timeout"] +pub struct SEXTTOEN_W<'a> { + w: &'a mut W, +} +impl<'a> SEXTTOEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Transfer Speed\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SPEED_A { + #[doc = "0: Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz"] + STANDARD_AND_FAST_MODE = 0, + #[doc = "1: Fast-mode Plus Upto 1MHz"] + FASTPLUS_MODE = 1, + #[doc = "2: High-speed mode Upto 3.4MHz"] + HIGH_SPEED_MODE = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SPEED_A) -> Self { + variant as _ + } +} +#[doc = "Field `SPEED` reader - Transfer Speed"] +pub struct SPEED_R(crate::FieldReader); +impl SPEED_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SPEED_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SPEED_A::STANDARD_AND_FAST_MODE), + 1 => Some(SPEED_A::FASTPLUS_MODE), + 2 => Some(SPEED_A::HIGH_SPEED_MODE), + _ => None, + } + } + #[doc = "Checks if the value of the field is `STANDARD_AND_FAST_MODE`"] + #[inline(always)] + pub fn is_standard_and_fast_mode(&self) -> bool { + **self == SPEED_A::STANDARD_AND_FAST_MODE + } + #[doc = "Checks if the value of the field is `FASTPLUS_MODE`"] + #[inline(always)] + pub fn is_fastplus_mode(&self) -> bool { + **self == SPEED_A::FASTPLUS_MODE + } + #[doc = "Checks if the value of the field is `HIGH_SPEED_MODE`"] + #[inline(always)] + pub fn is_high_speed_mode(&self) -> bool { + **self == SPEED_A::HIGH_SPEED_MODE + } +} +impl core::ops::Deref for SPEED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SPEED` writer - Transfer Speed"] +pub struct SPEED_W<'a> { + w: &'a mut W, +} +impl<'a> SPEED_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SPEED_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz"] + #[inline(always)] + pub fn standard_and_fast_mode(self) -> &'a mut W { + self.variant(SPEED_A::STANDARD_AND_FAST_MODE) + } + #[doc = "Fast-mode Plus Upto 1MHz"] + #[inline(always)] + pub fn fastplus_mode(self) -> &'a mut W { + self.variant(SPEED_A::FASTPLUS_MODE) + } + #[doc = "High-speed mode Upto 3.4MHz"] + #[inline(always)] + pub fn high_speed_mode(self) -> &'a mut W { + self.variant(SPEED_A::HIGH_SPEED_MODE) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 24)) | ((value as u32 & 0x03) << 24); + self.w + } +} +#[doc = "Field `SCLSM` reader - SCL Clock Stretch Mode"] +pub struct SCLSM_R(crate::FieldReader); +impl SCLSM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SCLSM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SCLSM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SCLSM` writer - SCL Clock Stretch Mode"] +pub struct SCLSM_W<'a> { + w: &'a mut W, +} +impl<'a> SCLSM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +#[doc = "Field `LOWTOUTEN` reader - SCL Low Timeout Enable"] +pub struct LOWTOUTEN_R(crate::FieldReader); +impl LOWTOUTEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LOWTOUTEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOWTOUTEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LOWTOUTEN` writer - SCL Low Timeout Enable"] +pub struct LOWTOUTEN_W<'a> { + w: &'a mut W, +} +impl<'a> LOWTOUTEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x07) as u8) + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 16 - Pin Usage"] + #[inline(always)] + pub fn pinout(&self) -> PINOUT_R { + PINOUT_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bits 20:21 - SDA Hold Time"] + #[inline(always)] + pub fn sdahold(&self) -> SDAHOLD_R { + SDAHOLD_R::new(((self.bits >> 20) & 0x03) as u8) + } + #[doc = "Bit 23 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttoen(&self) -> SEXTTOEN_R { + SEXTTOEN_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bits 24:25 - Transfer Speed"] + #[inline(always)] + pub fn speed(&self) -> SPEED_R { + SPEED_R::new(((self.bits >> 24) & 0x03) as u8) + } + #[doc = "Bit 27 - SCL Clock Stretch Mode"] + #[inline(always)] + pub fn sclsm(&self) -> SCLSM_R { + SCLSM_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 30 - SCL Low Timeout Enable"] + #[inline(always)] + pub fn lowtouten(&self) -> LOWTOUTEN_R { + LOWTOUTEN_R::new(((self.bits >> 30) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 16 - Pin Usage"] + #[inline(always)] + pub fn pinout(&mut self) -> PINOUT_W { + PINOUT_W { w: self } + } + #[doc = "Bits 20:21 - SDA Hold Time"] + #[inline(always)] + pub fn sdahold(&mut self) -> SDAHOLD_W { + SDAHOLD_W { w: self } + } + #[doc = "Bit 23 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttoen(&mut self) -> SEXTTOEN_W { + SEXTTOEN_W { w: self } + } + #[doc = "Bits 24:25 - Transfer Speed"] + #[inline(always)] + pub fn speed(&mut self) -> SPEED_W { + SPEED_W { w: self } + } + #[doc = "Bit 27 - SCL Clock Stretch Mode"] + #[inline(always)] + pub fn sclsm(&mut self) -> SCLSM_W { + SCLSM_W { w: self } + } + #[doc = "Bit 30 - SCL Low Timeout Enable"] + #[inline(always)] + pub fn lowtouten(&mut self) -> LOWTOUTEN_W { + LOWTOUTEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sercom0/i2cs/ctrlb.rs b/pac/atsamc21e/src/sercom0/i2cs/ctrlb.rs new file mode 100644 index 000000000000..b20f48581ed5 --- /dev/null +++ b/pac/atsamc21e/src/sercom0/i2cs/ctrlb.rs @@ -0,0 +1,328 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SMEN` reader - Smart Mode Enable"] +pub struct SMEN_R(crate::FieldReader); +impl SMEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SMEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SMEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SMEN` writer - Smart Mode Enable"] +pub struct SMEN_W<'a> { + w: &'a mut W, +} +impl<'a> SMEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `GCMD` reader - PMBus Group Command"] +pub struct GCMD_R(crate::FieldReader); +impl GCMD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GCMD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GCMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GCMD` writer - PMBus Group Command"] +pub struct GCMD_W<'a> { + w: &'a mut W, +} +impl<'a> GCMD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `AACKEN` reader - Automatic Address Acknowledge"] +pub struct AACKEN_R(crate::FieldReader); +impl AACKEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AACKEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AACKEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AACKEN` writer - Automatic Address Acknowledge"] +pub struct AACKEN_W<'a> { + w: &'a mut W, +} +impl<'a> AACKEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `AMODE` reader - Address Mode"] +pub struct AMODE_R(crate::FieldReader); +impl AMODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + AMODE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AMODE` writer - Address Mode"] +pub struct AMODE_W<'a> { + w: &'a mut W, +} +impl<'a> AMODE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 14)) | ((value as u32 & 0x03) << 14); + self.w + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Field `ACKACT` reader - Acknowledge Action"] +pub struct ACKACT_R(crate::FieldReader); +impl ACKACT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ACKACT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ACKACT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ACKACT` writer - Acknowledge Action"] +pub struct ACKACT_W<'a> { + w: &'a mut W, +} +impl<'a> ACKACT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +impl R { + #[doc = "Bit 8 - Smart Mode Enable"] + #[inline(always)] + pub fn smen(&self) -> SMEN_R { + SMEN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - PMBus Group Command"] + #[inline(always)] + pub fn gcmd(&self) -> GCMD_R { + GCMD_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Automatic Address Acknowledge"] + #[inline(always)] + pub fn aacken(&self) -> AACKEN_R { + AACKEN_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bits 14:15 - Address Mode"] + #[inline(always)] + pub fn amode(&self) -> AMODE_R { + AMODE_R::new(((self.bits >> 14) & 0x03) as u8) + } + #[doc = "Bits 16:17 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bit 18 - Acknowledge Action"] + #[inline(always)] + pub fn ackact(&self) -> ACKACT_R { + ACKACT_R::new(((self.bits >> 18) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 8 - Smart Mode Enable"] + #[inline(always)] + pub fn smen(&mut self) -> SMEN_W { + SMEN_W { w: self } + } + #[doc = "Bit 9 - PMBus Group Command"] + #[inline(always)] + pub fn gcmd(&mut self) -> GCMD_W { + GCMD_W { w: self } + } + #[doc = "Bit 10 - Automatic Address Acknowledge"] + #[inline(always)] + pub fn aacken(&mut self) -> AACKEN_W { + AACKEN_W { w: self } + } + #[doc = "Bits 14:15 - Address Mode"] + #[inline(always)] + pub fn amode(&mut self) -> AMODE_W { + AMODE_W { w: self } + } + #[doc = "Bits 16:17 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Bit 18 - Acknowledge Action"] + #[inline(always)] + pub fn ackact(&mut self) -> ACKACT_W { + ACKACT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sercom0/i2cs/data.rs b/pac/atsamc21e/src/sercom0/i2cs/data.rs new file mode 100644 index 000000000000..d8bfe070431a --- /dev/null +++ b/pac/atsamc21e/src/sercom0/i2cs/data.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data Value"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data Value"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Data Value"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Value"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sercom0/i2cs/intenclr.rs b/pac/atsamc21e/src/sercom0/i2cs/intenclr.rs new file mode 100644 index 000000000000..49f5191c8d63 --- /dev/null +++ b/pac/atsamc21e/src/sercom0/i2cs/intenclr.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PREC` reader - Stop Received Interrupt Disable"] +pub struct PREC_R(crate::FieldReader); +impl PREC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PREC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PREC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PREC` writer - Stop Received Interrupt Disable"] +pub struct PREC_W<'a> { + w: &'a mut W, +} +impl<'a> PREC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `AMATCH` reader - Address Match Interrupt Disable"] +pub struct AMATCH_R(crate::FieldReader); +impl AMATCH_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AMATCH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AMATCH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AMATCH` writer - Address Match Interrupt Disable"] +pub struct AMATCH_W<'a> { + w: &'a mut W, +} +impl<'a> AMATCH_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `DRDY` reader - Data Interrupt Disable"] +pub struct DRDY_R(crate::FieldReader); +impl DRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRDY` writer - Data Interrupt Disable"] +pub struct DRDY_W<'a> { + w: &'a mut W, +} +impl<'a> DRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Disable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Disable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Stop Received Interrupt Disable"] + #[inline(always)] + pub fn prec(&self) -> PREC_R { + PREC_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Address Match Interrupt Disable"] + #[inline(always)] + pub fn amatch(&self) -> AMATCH_R { + AMATCH_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Data Interrupt Disable"] + #[inline(always)] + pub fn drdy(&self) -> DRDY_R { + DRDY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Stop Received Interrupt Disable"] + #[inline(always)] + pub fn prec(&mut self) -> PREC_W { + PREC_W { w: self } + } + #[doc = "Bit 1 - Address Match Interrupt Disable"] + #[inline(always)] + pub fn amatch(&mut self) -> AMATCH_W { + AMATCH_W { w: self } + } + #[doc = "Bit 2 - Data Interrupt Disable"] + #[inline(always)] + pub fn drdy(&mut self) -> DRDY_W { + DRDY_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sercom0/i2cs/intenset.rs b/pac/atsamc21e/src/sercom0/i2cs/intenset.rs new file mode 100644 index 000000000000..97ea784d7476 --- /dev/null +++ b/pac/atsamc21e/src/sercom0/i2cs/intenset.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PREC` reader - Stop Received Interrupt Enable"] +pub struct PREC_R(crate::FieldReader); +impl PREC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PREC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PREC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PREC` writer - Stop Received Interrupt Enable"] +pub struct PREC_W<'a> { + w: &'a mut W, +} +impl<'a> PREC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `AMATCH` reader - Address Match Interrupt Enable"] +pub struct AMATCH_R(crate::FieldReader); +impl AMATCH_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AMATCH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AMATCH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AMATCH` writer - Address Match Interrupt Enable"] +pub struct AMATCH_W<'a> { + w: &'a mut W, +} +impl<'a> AMATCH_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `DRDY` reader - Data Interrupt Enable"] +pub struct DRDY_R(crate::FieldReader); +impl DRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRDY` writer - Data Interrupt Enable"] +pub struct DRDY_W<'a> { + w: &'a mut W, +} +impl<'a> DRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Stop Received Interrupt Enable"] + #[inline(always)] + pub fn prec(&self) -> PREC_R { + PREC_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Address Match Interrupt Enable"] + #[inline(always)] + pub fn amatch(&self) -> AMATCH_R { + AMATCH_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Data Interrupt Enable"] + #[inline(always)] + pub fn drdy(&self) -> DRDY_R { + DRDY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Stop Received Interrupt Enable"] + #[inline(always)] + pub fn prec(&mut self) -> PREC_W { + PREC_W { w: self } + } + #[doc = "Bit 1 - Address Match Interrupt Enable"] + #[inline(always)] + pub fn amatch(&mut self) -> AMATCH_W { + AMATCH_W { w: self } + } + #[doc = "Bit 2 - Data Interrupt Enable"] + #[inline(always)] + pub fn drdy(&mut self) -> DRDY_W { + DRDY_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sercom0/i2cs/intflag.rs b/pac/atsamc21e/src/sercom0/i2cs/intflag.rs new file mode 100644 index 000000000000..2eee333e4e59 --- /dev/null +++ b/pac/atsamc21e/src/sercom0/i2cs/intflag.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PREC` reader - Stop Received Interrupt"] +pub struct PREC_R(crate::FieldReader); +impl PREC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PREC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PREC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PREC` writer - Stop Received Interrupt"] +pub struct PREC_W<'a> { + w: &'a mut W, +} +impl<'a> PREC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `AMATCH` reader - Address Match Interrupt"] +pub struct AMATCH_R(crate::FieldReader); +impl AMATCH_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AMATCH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AMATCH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AMATCH` writer - Address Match Interrupt"] +pub struct AMATCH_W<'a> { + w: &'a mut W, +} +impl<'a> AMATCH_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `DRDY` reader - Data Interrupt"] +pub struct DRDY_R(crate::FieldReader); +impl DRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRDY` writer - Data Interrupt"] +pub struct DRDY_W<'a> { + w: &'a mut W, +} +impl<'a> DRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Stop Received Interrupt"] + #[inline(always)] + pub fn prec(&self) -> PREC_R { + PREC_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Address Match Interrupt"] + #[inline(always)] + pub fn amatch(&self) -> AMATCH_R { + AMATCH_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Data Interrupt"] + #[inline(always)] + pub fn drdy(&self) -> DRDY_R { + DRDY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Stop Received Interrupt"] + #[inline(always)] + pub fn prec(&mut self) -> PREC_W { + PREC_W { w: self } + } + #[doc = "Bit 1 - Address Match Interrupt"] + #[inline(always)] + pub fn amatch(&mut self) -> AMATCH_W { + AMATCH_W { w: self } + } + #[doc = "Bit 2 - Data Interrupt"] + #[inline(always)] + pub fn drdy(&mut self) -> DRDY_W { + DRDY_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sercom0/i2cs/status.rs b/pac/atsamc21e/src/sercom0/i2cs/status.rs new file mode 100644 index 000000000000..b3f6d218fa66 --- /dev/null +++ b/pac/atsamc21e/src/sercom0/i2cs/status.rs @@ -0,0 +1,489 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BUSERR` reader - Bus Error"] +pub struct BUSERR_R(crate::FieldReader); +impl BUSERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSERR` writer - Bus Error"] +pub struct BUSERR_W<'a> { + w: &'a mut W, +} +impl<'a> BUSERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `COLL` reader - Transmit Collision"] +pub struct COLL_R(crate::FieldReader); +impl COLL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COLL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COLL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COLL` writer - Transmit Collision"] +pub struct COLL_W<'a> { + w: &'a mut W, +} +impl<'a> COLL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXNACK` reader - Received Not Acknowledge"] +pub struct RXNACK_R(crate::FieldReader); +impl RXNACK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXNACK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXNACK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXNACK` writer - Received Not Acknowledge"] +pub struct RXNACK_W<'a> { + w: &'a mut W, +} +impl<'a> RXNACK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `DIR` reader - Read/Write Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Read/Write Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `SR` reader - Repeated Start"] +pub struct SR_R(crate::FieldReader); +impl SR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SR` writer - Repeated Start"] +pub struct SR_W<'a> { + w: &'a mut W, +} +impl<'a> SR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `LOWTOUT` reader - SCL Low Timeout"] +pub struct LOWTOUT_R(crate::FieldReader); +impl LOWTOUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LOWTOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOWTOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LOWTOUT` writer - SCL Low Timeout"] +pub struct LOWTOUT_W<'a> { + w: &'a mut W, +} +impl<'a> LOWTOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `CLKHOLD` reader - Clock Hold"] +pub struct CLKHOLD_R(crate::FieldReader); +impl CLKHOLD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKHOLD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKHOLD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKHOLD` writer - Clock Hold"] +pub struct CLKHOLD_W<'a> { + w: &'a mut W, +} +impl<'a> CLKHOLD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `SEXTTOUT` reader - Slave SCL Low Extend Timeout"] +pub struct SEXTTOUT_R(crate::FieldReader); +impl SEXTTOUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SEXTTOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEXTTOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEXTTOUT` writer - Slave SCL Low Extend Timeout"] +pub struct SEXTTOUT_W<'a> { + w: &'a mut W, +} +impl<'a> SEXTTOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `HS` reader - High Speed"] +pub struct HS_R(crate::FieldReader); +impl HS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HS` writer - High Speed"] +pub struct HS_W<'a> { + w: &'a mut W, +} +impl<'a> HS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u16 & 0x01) << 10); + self.w + } +} +impl R { + #[doc = "Bit 0 - Bus Error"] + #[inline(always)] + pub fn buserr(&self) -> BUSERR_R { + BUSERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Collision"] + #[inline(always)] + pub fn coll(&self) -> COLL_R { + COLL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Received Not Acknowledge"] + #[inline(always)] + pub fn rxnack(&self) -> RXNACK_R { + RXNACK_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Read/Write Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Repeated Start"] + #[inline(always)] + pub fn sr(&self) -> SR_R { + SR_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 6 - SCL Low Timeout"] + #[inline(always)] + pub fn lowtout(&self) -> LOWTOUT_R { + LOWTOUT_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Clock Hold"] + #[inline(always)] + pub fn clkhold(&self) -> CLKHOLD_R { + CLKHOLD_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 9 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttout(&self) -> SEXTTOUT_R { + SEXTTOUT_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - High Speed"] + #[inline(always)] + pub fn hs(&self) -> HS_R { + HS_R::new(((self.bits >> 10) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Bus Error"] + #[inline(always)] + pub fn buserr(&mut self) -> BUSERR_W { + BUSERR_W { w: self } + } + #[doc = "Bit 1 - Transmit Collision"] + #[inline(always)] + pub fn coll(&mut self) -> COLL_W { + COLL_W { w: self } + } + #[doc = "Bit 2 - Received Not Acknowledge"] + #[inline(always)] + pub fn rxnack(&mut self) -> RXNACK_W { + RXNACK_W { w: self } + } + #[doc = "Bit 3 - Read/Write Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 4 - Repeated Start"] + #[inline(always)] + pub fn sr(&mut self) -> SR_W { + SR_W { w: self } + } + #[doc = "Bit 6 - SCL Low Timeout"] + #[inline(always)] + pub fn lowtout(&mut self) -> LOWTOUT_W { + LOWTOUT_W { w: self } + } + #[doc = "Bit 7 - Clock Hold"] + #[inline(always)] + pub fn clkhold(&mut self) -> CLKHOLD_W { + CLKHOLD_W { w: self } + } + #[doc = "Bit 9 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttout(&mut self) -> SEXTTOUT_W { + SEXTTOUT_W { w: self } + } + #[doc = "Bit 10 - High Speed"] + #[inline(always)] + pub fn hs(&mut self) -> HS_W { + HS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sercom0/i2cs/syncbusy.rs b/pac/atsamc21e/src/sercom0/i2cs/syncbusy.rs new file mode 100644 index 000000000000..38e2509d9666 --- /dev/null +++ b/pac/atsamc21e/src/sercom0/i2cs/syncbusy.rs @@ -0,0 +1,73 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - SERCOM Enable Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM Enable Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +#[doc = "I2CS Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sercom0/spim.rs b/pac/atsamc21e/src/sercom0/spim.rs new file mode 100644 index 000000000000..528e38e1b811 --- /dev/null +++ b/pac/atsamc21e/src/sercom0/spim.rs @@ -0,0 +1,44 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "SPIM Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "SPIM Control B"] +pub mod ctrlb; +#[doc = "BAUD register accessor: an alias for `Reg`"] +pub type BAUD = crate::Reg; +#[doc = "SPIM Baud Rate"] +pub mod baud; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "SPIM Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "SPIM Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "SPIM Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "SPIM Status"] +pub mod status; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "SPIM Synchronization Busy"] +pub mod syncbusy; +#[doc = "ADDR register accessor: an alias for `Reg`"] +pub type ADDR = crate::Reg; +#[doc = "SPIM Address"] +pub mod addr; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "SPIM Data"] +pub mod data; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "SPIM Debug Control"] +pub mod dbgctrl; diff --git a/pac/atsamc21e/src/sercom0/spim/addr.rs b/pac/atsamc21e/src/sercom0/spim/addr.rs new file mode 100644 index 000000000000..7c25cd522ea2 --- /dev/null +++ b/pac/atsamc21e/src/sercom0/spim/addr.rs @@ -0,0 +1,140 @@ +#[doc = "Register `ADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ADDR` reader - Address Value"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - Address Value"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +#[doc = "Field `ADDRMASK` reader - Address Mask"] +pub struct ADDRMASK_R(crate::FieldReader); +impl ADDRMASK_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ADDRMASK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDRMASK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDRMASK` writer - Address Mask"] +pub struct ADDRMASK_W<'a> { + w: &'a mut W, +} +impl<'a> ADDRMASK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Address Value"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 16:23 - Address Mask"] + #[inline(always)] + pub fn addrmask(&self) -> ADDRMASK_R { + ADDRMASK_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Address Value"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Bits 16:23 - Address Mask"] + #[inline(always)] + pub fn addrmask(&mut self) -> ADDRMASK_W { + ADDRMASK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [addr](index.html) module"] +pub struct ADDR_SPEC; +impl crate::RegisterSpec for ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [addr::R](R) reader structure"] +impl crate::Readable for ADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [addr::W](W) writer structure"] +impl crate::Writable for ADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ADDR to value 0"] +impl crate::Resettable for ADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sercom0/spim/baud.rs b/pac/atsamc21e/src/sercom0/spim/baud.rs new file mode 100644 index 000000000000..6bec9ca74355 --- /dev/null +++ b/pac/atsamc21e/src/sercom0/spim/baud.rs @@ -0,0 +1,103 @@ +#[doc = "Register `BAUD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud](index.html) module"] +pub struct BAUD_SPEC; +impl crate::RegisterSpec for BAUD_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [baud::R](R) reader structure"] +impl crate::Readable for BAUD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud::W](W) writer structure"] +impl crate::Writable for BAUD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD to value 0"] +impl crate::Resettable for BAUD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sercom0/spim/ctrla.rs b/pac/atsamc21e/src/sercom0/spim/ctrla.rs new file mode 100644 index 000000000000..44028f8cbdd7 --- /dev/null +++ b/pac/atsamc21e/src/sercom0/spim/ctrla.rs @@ -0,0 +1,992 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: USART with external clock"] + USART_EXT_CLK = 0, + #[doc = "1: USART with internal clock"] + USART_INT_CLK = 1, + #[doc = "2: SPI in slave operation"] + SPI_SLAVE = 2, + #[doc = "3: SPI in master operation"] + SPI_MASTER = 3, + #[doc = "4: I2C slave operation"] + I2C_SLAVE = 4, + #[doc = "5: I2C master operation"] + I2C_MASTER = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::USART_EXT_CLK), + 1 => Some(MODE_A::USART_INT_CLK), + 2 => Some(MODE_A::SPI_SLAVE), + 3 => Some(MODE_A::SPI_MASTER), + 4 => Some(MODE_A::I2C_SLAVE), + 5 => Some(MODE_A::I2C_MASTER), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_EXT_CLK`"] + #[inline(always)] + pub fn is_usart_ext_clk(&self) -> bool { + **self == MODE_A::USART_EXT_CLK + } + #[doc = "Checks if the value of the field is `USART_INT_CLK`"] + #[inline(always)] + pub fn is_usart_int_clk(&self) -> bool { + **self == MODE_A::USART_INT_CLK + } + #[doc = "Checks if the value of the field is `SPI_SLAVE`"] + #[inline(always)] + pub fn is_spi_slave(&self) -> bool { + **self == MODE_A::SPI_SLAVE + } + #[doc = "Checks if the value of the field is `SPI_MASTER`"] + #[inline(always)] + pub fn is_spi_master(&self) -> bool { + **self == MODE_A::SPI_MASTER + } + #[doc = "Checks if the value of the field is `I2C_SLAVE`"] + #[inline(always)] + pub fn is_i2c_slave(&self) -> bool { + **self == MODE_A::I2C_SLAVE + } + #[doc = "Checks if the value of the field is `I2C_MASTER`"] + #[inline(always)] + pub fn is_i2c_master(&self) -> bool { + **self == MODE_A::I2C_MASTER + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART with external clock"] + #[inline(always)] + pub fn usart_ext_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_EXT_CLK) + } + #[doc = "USART with internal clock"] + #[inline(always)] + pub fn usart_int_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_INT_CLK) + } + #[doc = "SPI in slave operation"] + #[inline(always)] + pub fn spi_slave(self) -> &'a mut W { + self.variant(MODE_A::SPI_SLAVE) + } + #[doc = "SPI in master operation"] + #[inline(always)] + pub fn spi_master(self) -> &'a mut W { + self.variant(MODE_A::SPI_MASTER) + } + #[doc = "I2C slave operation"] + #[inline(always)] + pub fn i2c_slave(self) -> &'a mut W { + self.variant(MODE_A::I2C_SLAVE) + } + #[doc = "I2C master operation"] + #[inline(always)] + pub fn i2c_master(self) -> &'a mut W { + self.variant(MODE_A::I2C_MASTER) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 2)) | ((value as u32 & 0x07) << 2); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `IBON` reader - Immediate Buffer Overflow Notification"] +pub struct IBON_R(crate::FieldReader); +impl IBON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IBON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IBON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IBON` writer - Immediate Buffer Overflow Notification"] +pub struct IBON_W<'a> { + w: &'a mut W, +} +impl<'a> IBON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Data Out Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DOPO_A { + #[doc = "0: DO on PAD\\[0\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + PAD0 = 0, + #[doc = "1: DO on PAD\\[2\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + PAD1 = 1, + #[doc = "2: DO on PAD\\[3\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + PAD2 = 2, + #[doc = "3: DO on PAD\\[0\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + PAD3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DOPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `DOPO` reader - Data Out Pinout"] +pub struct DOPO_R(crate::FieldReader); +impl DOPO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DOPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DOPO_A { + match self.bits { + 0 => DOPO_A::PAD0, + 1 => DOPO_A::PAD1, + 2 => DOPO_A::PAD2, + 3 => DOPO_A::PAD3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == DOPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD1`"] + #[inline(always)] + pub fn is_pad1(&self) -> bool { + **self == DOPO_A::PAD1 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == DOPO_A::PAD2 + } + #[doc = "Checks if the value of the field is `PAD3`"] + #[inline(always)] + pub fn is_pad3(&self) -> bool { + **self == DOPO_A::PAD3 + } +} +impl core::ops::Deref for DOPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DOPO` writer - Data Out Pinout"] +pub struct DOPO_W<'a> { + w: &'a mut W, +} +impl<'a> DOPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DOPO_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "DO on PAD\\[0\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(DOPO_A::PAD0) + } + #[doc = "DO on PAD\\[2\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + #[inline(always)] + pub fn pad1(self) -> &'a mut W { + self.variant(DOPO_A::PAD1) + } + #[doc = "DO on PAD\\[3\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(DOPO_A::PAD2) + } + #[doc = "DO on PAD\\[0\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + #[inline(always)] + pub fn pad3(self) -> &'a mut W { + self.variant(DOPO_A::PAD3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Data In Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DIPO_A { + #[doc = "0: SERCOM PAD\\[0\\]"] + PAD0 = 0, + #[doc = "1: SERCOM PAD\\[1\\]"] + PAD1 = 1, + #[doc = "2: SERCOM PAD\\[2\\]"] + PAD2 = 2, + #[doc = "3: SERCOM PAD\\[3\\]"] + PAD3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DIPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `DIPO` reader - Data In Pinout"] +pub struct DIPO_R(crate::FieldReader); +impl DIPO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DIPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DIPO_A { + match self.bits { + 0 => DIPO_A::PAD0, + 1 => DIPO_A::PAD1, + 2 => DIPO_A::PAD2, + 3 => DIPO_A::PAD3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == DIPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD1`"] + #[inline(always)] + pub fn is_pad1(&self) -> bool { + **self == DIPO_A::PAD1 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == DIPO_A::PAD2 + } + #[doc = "Checks if the value of the field is `PAD3`"] + #[inline(always)] + pub fn is_pad3(&self) -> bool { + **self == DIPO_A::PAD3 + } +} +impl core::ops::Deref for DIPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIPO` writer - Data In Pinout"] +pub struct DIPO_W<'a> { + w: &'a mut W, +} +impl<'a> DIPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DIPO_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "SERCOM PAD\\[0\\]"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(DIPO_A::PAD0) + } + #[doc = "SERCOM PAD\\[1\\]"] + #[inline(always)] + pub fn pad1(self) -> &'a mut W { + self.variant(DIPO_A::PAD1) + } + #[doc = "SERCOM PAD\\[2\\]"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(DIPO_A::PAD2) + } + #[doc = "SERCOM PAD\\[3\\]"] + #[inline(always)] + pub fn pad3(self) -> &'a mut W { + self.variant(DIPO_A::PAD3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 20)) | ((value as u32 & 0x03) << 20); + self.w + } +} +#[doc = "Frame Format\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FORM_A { + #[doc = "0: SPI Frame"] + SPI_FRAME = 0, + #[doc = "2: SPI Frame with Addr"] + SPI_FRAME_WITH_ADDR = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FORM_A) -> Self { + variant as _ + } +} +#[doc = "Field `FORM` reader - Frame Format"] +pub struct FORM_R(crate::FieldReader); +impl FORM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FORM_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(FORM_A::SPI_FRAME), + 2 => Some(FORM_A::SPI_FRAME_WITH_ADDR), + _ => None, + } + } + #[doc = "Checks if the value of the field is `SPI_FRAME`"] + #[inline(always)] + pub fn is_spi_frame(&self) -> bool { + **self == FORM_A::SPI_FRAME + } + #[doc = "Checks if the value of the field is `SPI_FRAME_WITH_ADDR`"] + #[inline(always)] + pub fn is_spi_frame_with_addr(&self) -> bool { + **self == FORM_A::SPI_FRAME_WITH_ADDR + } +} +impl core::ops::Deref for FORM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FORM` writer - Frame Format"] +pub struct FORM_W<'a> { + w: &'a mut W, +} +impl<'a> FORM_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FORM_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "SPI Frame"] + #[inline(always)] + pub fn spi_frame(self) -> &'a mut W { + self.variant(FORM_A::SPI_FRAME) + } + #[doc = "SPI Frame with Addr"] + #[inline(always)] + pub fn spi_frame_with_addr(self) -> &'a mut W { + self.variant(FORM_A::SPI_FRAME_WITH_ADDR) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Clock Phase\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CPHA_A { + #[doc = "0: The data is sampled on a leading SCK edge and changed on a trailing SCK edge"] + LEADING_EDGE = 0, + #[doc = "1: The data is sampled on a trailing SCK edge and changed on a leading SCK edge"] + TRAILING_EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CPHA_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CPHA` reader - Clock Phase"] +pub struct CPHA_R(crate::FieldReader); +impl CPHA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPHA_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CPHA_A { + match self.bits { + false => CPHA_A::LEADING_EDGE, + true => CPHA_A::TRAILING_EDGE, + } + } + #[doc = "Checks if the value of the field is `LEADING_EDGE`"] + #[inline(always)] + pub fn is_leading_edge(&self) -> bool { + **self == CPHA_A::LEADING_EDGE + } + #[doc = "Checks if the value of the field is `TRAILING_EDGE`"] + #[inline(always)] + pub fn is_trailing_edge(&self) -> bool { + **self == CPHA_A::TRAILING_EDGE + } +} +impl core::ops::Deref for CPHA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPHA` writer - Clock Phase"] +pub struct CPHA_W<'a> { + w: &'a mut W, +} +impl<'a> CPHA_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CPHA_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "The data is sampled on a leading SCK edge and changed on a trailing SCK edge"] + #[inline(always)] + pub fn leading_edge(self) -> &'a mut W { + self.variant(CPHA_A::LEADING_EDGE) + } + #[doc = "The data is sampled on a trailing SCK edge and changed on a leading SCK edge"] + #[inline(always)] + pub fn trailing_edge(self) -> &'a mut W { + self.variant(CPHA_A::TRAILING_EDGE) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Clock Polarity\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CPOL_A { + #[doc = "0: SCK is low when idle"] + IDLE_LOW = 0, + #[doc = "1: SCK is high when idle"] + IDLE_HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CPOL_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CPOL` reader - Clock Polarity"] +pub struct CPOL_R(crate::FieldReader); +impl CPOL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPOL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CPOL_A { + match self.bits { + false => CPOL_A::IDLE_LOW, + true => CPOL_A::IDLE_HIGH, + } + } + #[doc = "Checks if the value of the field is `IDLE_LOW`"] + #[inline(always)] + pub fn is_idle_low(&self) -> bool { + **self == CPOL_A::IDLE_LOW + } + #[doc = "Checks if the value of the field is `IDLE_HIGH`"] + #[inline(always)] + pub fn is_idle_high(&self) -> bool { + **self == CPOL_A::IDLE_HIGH + } +} +impl core::ops::Deref for CPOL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPOL` writer - Clock Polarity"] +pub struct CPOL_W<'a> { + w: &'a mut W, +} +impl<'a> CPOL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CPOL_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "SCK is low when idle"] + #[inline(always)] + pub fn idle_low(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_LOW) + } + #[doc = "SCK is high when idle"] + #[inline(always)] + pub fn idle_high(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_HIGH) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29); + self.w + } +} +#[doc = "Data Order\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum DORD_A { + #[doc = "0: MSB is transferred first"] + MSB = 0, + #[doc = "1: LSB is transferred first"] + LSB = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DORD_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DORD` reader - Data Order"] +pub struct DORD_R(crate::FieldReader); +impl DORD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DORD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DORD_A { + match self.bits { + false => DORD_A::MSB, + true => DORD_A::LSB, + } + } + #[doc = "Checks if the value of the field is `MSB`"] + #[inline(always)] + pub fn is_msb(&self) -> bool { + **self == DORD_A::MSB + } + #[doc = "Checks if the value of the field is `LSB`"] + #[inline(always)] + pub fn is_lsb(&self) -> bool { + **self == DORD_A::LSB + } +} +impl core::ops::Deref for DORD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DORD` writer - Data Order"] +pub struct DORD_W<'a> { + w: &'a mut W, +} +impl<'a> DORD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DORD_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "MSB is transferred first"] + #[inline(always)] + pub fn msb(self) -> &'a mut W { + self.variant(DORD_A::MSB) + } + #[doc = "LSB is transferred first"] + #[inline(always)] + pub fn lsb(self) -> &'a mut W { + self.variant(DORD_A::LSB) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x07) as u8) + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&self) -> IBON_R { + IBON_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bits 16:17 - Data Out Pinout"] + #[inline(always)] + pub fn dopo(&self) -> DOPO_R { + DOPO_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bits 20:21 - Data In Pinout"] + #[inline(always)] + pub fn dipo(&self) -> DIPO_R { + DIPO_R::new(((self.bits >> 20) & 0x03) as u8) + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&self) -> FORM_R { + FORM_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 28 - Clock Phase"] + #[inline(always)] + pub fn cpha(&self) -> CPHA_R { + CPHA_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&self) -> CPOL_R { + CPOL_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&self) -> DORD_R { + DORD_R::new(((self.bits >> 30) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&mut self) -> IBON_W { + IBON_W { w: self } + } + #[doc = "Bits 16:17 - Data Out Pinout"] + #[inline(always)] + pub fn dopo(&mut self) -> DOPO_W { + DOPO_W { w: self } + } + #[doc = "Bits 20:21 - Data In Pinout"] + #[inline(always)] + pub fn dipo(&mut self) -> DIPO_W { + DIPO_W { w: self } + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&mut self) -> FORM_W { + FORM_W { w: self } + } + #[doc = "Bit 28 - Clock Phase"] + #[inline(always)] + pub fn cpha(&mut self) -> CPHA_W { + CPHA_W { w: self } + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&mut self) -> CPOL_W { + CPOL_W { w: self } + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&mut self) -> DORD_W { + DORD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sercom0/spim/ctrlb.rs b/pac/atsamc21e/src/sercom0/spim/ctrlb.rs new file mode 100644 index 000000000000..3d94f824ce83 --- /dev/null +++ b/pac/atsamc21e/src/sercom0/spim/ctrlb.rs @@ -0,0 +1,439 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Character Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CHSIZE_A { + #[doc = "0: 8 bits"] + _8_BIT = 0, + #[doc = "1: 9 bits"] + _9_BIT = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CHSIZE_A) -> Self { + variant as _ + } +} +#[doc = "Field `CHSIZE` reader - Character Size"] +pub struct CHSIZE_R(crate::FieldReader); +impl CHSIZE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CHSIZE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CHSIZE_A::_8_BIT), + 1 => Some(CHSIZE_A::_9_BIT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_8_BIT`"] + #[inline(always)] + pub fn is_8_bit(&self) -> bool { + **self == CHSIZE_A::_8_BIT + } + #[doc = "Checks if the value of the field is `_9_BIT`"] + #[inline(always)] + pub fn is_9_bit(&self) -> bool { + **self == CHSIZE_A::_9_BIT + } +} +impl core::ops::Deref for CHSIZE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHSIZE` writer - Character Size"] +pub struct CHSIZE_W<'a> { + w: &'a mut W, +} +impl<'a> CHSIZE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CHSIZE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8 bits"] + #[inline(always)] + pub fn _8_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_8_BIT) + } + #[doc = "9 bits"] + #[inline(always)] + pub fn _9_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_9_BIT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Field `PLOADEN` reader - Data Preload Enable"] +pub struct PLOADEN_R(crate::FieldReader); +impl PLOADEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PLOADEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PLOADEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PLOADEN` writer - Data Preload Enable"] +pub struct PLOADEN_W<'a> { + w: &'a mut W, +} +impl<'a> PLOADEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `SSDE` reader - Slave Select Low Detect Enable"] +pub struct SSDE_R(crate::FieldReader); +impl SSDE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SSDE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSDE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSDE` writer - Slave Select Low Detect Enable"] +pub struct SSDE_W<'a> { + w: &'a mut W, +} +impl<'a> SSDE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `MSSEN` reader - Master Slave Select Enable"] +pub struct MSSEN_R(crate::FieldReader); +impl MSSEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MSSEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MSSEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MSSEN` writer - Master Slave Select Enable"] +pub struct MSSEN_W<'a> { + w: &'a mut W, +} +impl<'a> MSSEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Address Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum AMODE_A { + #[doc = "0: SPI Address mask"] + MASK = 0, + #[doc = "1: Two unique Addressess"] + _2_ADDRESSES = 1, + #[doc = "2: Address Range"] + RANGE = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: AMODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `AMODE` reader - Address Mode"] +pub struct AMODE_R(crate::FieldReader); +impl AMODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + AMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(AMODE_A::MASK), + 1 => Some(AMODE_A::_2_ADDRESSES), + 2 => Some(AMODE_A::RANGE), + _ => None, + } + } + #[doc = "Checks if the value of the field is `MASK`"] + #[inline(always)] + pub fn is_mask(&self) -> bool { + **self == AMODE_A::MASK + } + #[doc = "Checks if the value of the field is `_2_ADDRESSES`"] + #[inline(always)] + pub fn is_2_addresses(&self) -> bool { + **self == AMODE_A::_2_ADDRESSES + } + #[doc = "Checks if the value of the field is `RANGE`"] + #[inline(always)] + pub fn is_range(&self) -> bool { + **self == AMODE_A::RANGE + } +} +impl core::ops::Deref for AMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AMODE` writer - Address Mode"] +pub struct AMODE_W<'a> { + w: &'a mut W, +} +impl<'a> AMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: AMODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "SPI Address mask"] + #[inline(always)] + pub fn mask(self) -> &'a mut W { + self.variant(AMODE_A::MASK) + } + #[doc = "Two unique Addressess"] + #[inline(always)] + pub fn _2_addresses(self) -> &'a mut W { + self.variant(AMODE_A::_2_ADDRESSES) + } + #[doc = "Address Range"] + #[inline(always)] + pub fn range(self) -> &'a mut W { + self.variant(AMODE_A::RANGE) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 14)) | ((value as u32 & 0x03) << 14); + self.w + } +} +#[doc = "Field `RXEN` reader - Receiver Enable"] +pub struct RXEN_R(crate::FieldReader); +impl RXEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXEN` writer - Receiver Enable"] +pub struct RXEN_W<'a> { + w: &'a mut W, +} +impl<'a> RXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&self) -> CHSIZE_R { + CHSIZE_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 6 - Data Preload Enable"] + #[inline(always)] + pub fn ploaden(&self) -> PLOADEN_R { + PLOADEN_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 9 - Slave Select Low Detect Enable"] + #[inline(always)] + pub fn ssde(&self) -> SSDE_R { + SSDE_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 13 - Master Slave Select Enable"] + #[inline(always)] + pub fn mssen(&self) -> MSSEN_R { + MSSEN_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bits 14:15 - Address Mode"] + #[inline(always)] + pub fn amode(&self) -> AMODE_R { + AMODE_R::new(((self.bits >> 14) & 0x03) as u8) + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&self) -> RXEN_R { + RXEN_R::new(((self.bits >> 17) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&mut self) -> CHSIZE_W { + CHSIZE_W { w: self } + } + #[doc = "Bit 6 - Data Preload Enable"] + #[inline(always)] + pub fn ploaden(&mut self) -> PLOADEN_W { + PLOADEN_W { w: self } + } + #[doc = "Bit 9 - Slave Select Low Detect Enable"] + #[inline(always)] + pub fn ssde(&mut self) -> SSDE_W { + SSDE_W { w: self } + } + #[doc = "Bit 13 - Master Slave Select Enable"] + #[inline(always)] + pub fn mssen(&mut self) -> MSSEN_W { + MSSEN_W { w: self } + } + #[doc = "Bits 14:15 - Address Mode"] + #[inline(always)] + pub fn amode(&mut self) -> AMODE_W { + AMODE_W { w: self } + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&mut self) -> RXEN_W { + RXEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sercom0/spim/data.rs b/pac/atsamc21e/src/sercom0/spim/data.rs new file mode 100644 index 000000000000..dc9cd020d2a5 --- /dev/null +++ b/pac/atsamc21e/src/sercom0/spim/data.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data Value"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data Value"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01ff) | (value as u32 & 0x01ff); + self.w + } +} +impl R { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new((self.bits & 0x01ff) as u16) + } +} +impl W { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sercom0/spim/dbgctrl.rs b/pac/atsamc21e/src/sercom0/spim/dbgctrl.rs new file mode 100644 index 000000000000..d9aa7495940c --- /dev/null +++ b/pac/atsamc21e/src/sercom0/spim/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGSTOP` reader - Debug Mode"] +pub struct DBGSTOP_R(crate::FieldReader); +impl DBGSTOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGSTOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGSTOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGSTOP` writer - Debug Mode"] +pub struct DBGSTOP_W<'a> { + w: &'a mut W, +} +impl<'a> DBGSTOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&self) -> DBGSTOP_R { + DBGSTOP_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&mut self) -> DBGSTOP_W { + DBGSTOP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sercom0/spim/intenclr.rs b/pac/atsamc21e/src/sercom0/spim/intenclr.rs new file mode 100644 index 000000000000..ccab3de4348d --- /dev/null +++ b/pac/atsamc21e/src/sercom0/spim/intenclr.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Disable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Disable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Disable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Disable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Disable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Disable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SSL` reader - Slave Select Low Interrupt Disable"] +pub struct SSL_R(crate::FieldReader); +impl SSL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SSL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSL` writer - Slave Select Low Interrupt Disable"] +pub struct SSL_W<'a> { + w: &'a mut W, +} +impl<'a> SSL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Disable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Disable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Slave Select Low Interrupt Disable"] + #[inline(always)] + pub fn ssl(&self) -> SSL_R { + SSL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Slave Select Low Interrupt Disable"] + #[inline(always)] + pub fn ssl(&mut self) -> SSL_W { + SSL_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sercom0/spim/intenset.rs b/pac/atsamc21e/src/sercom0/spim/intenset.rs new file mode 100644 index 000000000000..d9779cf897c2 --- /dev/null +++ b/pac/atsamc21e/src/sercom0/spim/intenset.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Enable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Enable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Enable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Enable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Enable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Enable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SSL` reader - Slave Select Low Interrupt Enable"] +pub struct SSL_R(crate::FieldReader); +impl SSL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SSL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSL` writer - Slave Select Low Interrupt Enable"] +pub struct SSL_W<'a> { + w: &'a mut W, +} +impl<'a> SSL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Slave Select Low Interrupt Enable"] + #[inline(always)] + pub fn ssl(&self) -> SSL_R { + SSL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Slave Select Low Interrupt Enable"] + #[inline(always)] + pub fn ssl(&mut self) -> SSL_W { + SSL_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sercom0/spim/intflag.rs b/pac/atsamc21e/src/sercom0/spim/intflag.rs new file mode 100644 index 000000000000..e9bc10c271b8 --- /dev/null +++ b/pac/atsamc21e/src/sercom0/spim/intflag.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SSL` reader - Slave Select Low Interrupt Flag"] +pub struct SSL_R(crate::FieldReader); +impl SSL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SSL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSL` writer - Slave Select Low Interrupt Flag"] +pub struct SSL_W<'a> { + w: &'a mut W, +} +impl<'a> SSL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Slave Select Low Interrupt Flag"] + #[inline(always)] + pub fn ssl(&self) -> SSL_R { + SSL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Slave Select Low Interrupt Flag"] + #[inline(always)] + pub fn ssl(&mut self) -> SSL_W { + SSL_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sercom0/spim/status.rs b/pac/atsamc21e/src/sercom0/spim/status.rs new file mode 100644 index 000000000000..9919460bf0e2 --- /dev/null +++ b/pac/atsamc21e/src/sercom0/spim/status.rs @@ -0,0 +1,113 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BUFOVF` reader - Buffer Overflow"] +pub struct BUFOVF_R(crate::FieldReader); +impl BUFOVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUFOVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUFOVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUFOVF` writer - Buffer Overflow"] +pub struct BUFOVF_W<'a> { + w: &'a mut W, +} +impl<'a> BUFOVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&self) -> BUFOVF_R { + BUFOVF_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&mut self) -> BUFOVF_W { + BUFOVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sercom0/spim/syncbusy.rs b/pac/atsamc21e/src/sercom0/spim/syncbusy.rs new file mode 100644 index 000000000000..bee13adf7084 --- /dev/null +++ b/pac/atsamc21e/src/sercom0/spim/syncbusy.rs @@ -0,0 +1,93 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - SERCOM Enable Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLB` reader - CTRLB Synchronization Busy"] +pub struct CTRLB_R(crate::FieldReader); +impl CTRLB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM Enable Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - CTRLB Synchronization Busy"] + #[inline(always)] + pub fn ctrlb(&self) -> CTRLB_R { + CTRLB_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +#[doc = "SPIM Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sercom0/spis.rs b/pac/atsamc21e/src/sercom0/spis.rs new file mode 100644 index 000000000000..eed10c90c460 --- /dev/null +++ b/pac/atsamc21e/src/sercom0/spis.rs @@ -0,0 +1,44 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "SPIS Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "SPIS Control B"] +pub mod ctrlb; +#[doc = "BAUD register accessor: an alias for `Reg`"] +pub type BAUD = crate::Reg; +#[doc = "SPIS Baud Rate"] +pub mod baud; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "SPIS Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "SPIS Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "SPIS Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "SPIS Status"] +pub mod status; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "SPIS Synchronization Busy"] +pub mod syncbusy; +#[doc = "ADDR register accessor: an alias for `Reg`"] +pub type ADDR = crate::Reg; +#[doc = "SPIS Address"] +pub mod addr; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "SPIS Data"] +pub mod data; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "SPIS Debug Control"] +pub mod dbgctrl; diff --git a/pac/atsamc21e/src/sercom0/spis/addr.rs b/pac/atsamc21e/src/sercom0/spis/addr.rs new file mode 100644 index 000000000000..5fca0a698bfe --- /dev/null +++ b/pac/atsamc21e/src/sercom0/spis/addr.rs @@ -0,0 +1,140 @@ +#[doc = "Register `ADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ADDR` reader - Address Value"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - Address Value"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +#[doc = "Field `ADDRMASK` reader - Address Mask"] +pub struct ADDRMASK_R(crate::FieldReader); +impl ADDRMASK_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ADDRMASK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDRMASK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDRMASK` writer - Address Mask"] +pub struct ADDRMASK_W<'a> { + w: &'a mut W, +} +impl<'a> ADDRMASK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Address Value"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 16:23 - Address Mask"] + #[inline(always)] + pub fn addrmask(&self) -> ADDRMASK_R { + ADDRMASK_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Address Value"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Bits 16:23 - Address Mask"] + #[inline(always)] + pub fn addrmask(&mut self) -> ADDRMASK_W { + ADDRMASK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [addr](index.html) module"] +pub struct ADDR_SPEC; +impl crate::RegisterSpec for ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [addr::R](R) reader structure"] +impl crate::Readable for ADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [addr::W](W) writer structure"] +impl crate::Writable for ADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ADDR to value 0"] +impl crate::Resettable for ADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sercom0/spis/baud.rs b/pac/atsamc21e/src/sercom0/spis/baud.rs new file mode 100644 index 000000000000..eeee4cf633e5 --- /dev/null +++ b/pac/atsamc21e/src/sercom0/spis/baud.rs @@ -0,0 +1,103 @@ +#[doc = "Register `BAUD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud](index.html) module"] +pub struct BAUD_SPEC; +impl crate::RegisterSpec for BAUD_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [baud::R](R) reader structure"] +impl crate::Readable for BAUD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud::W](W) writer structure"] +impl crate::Writable for BAUD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD to value 0"] +impl crate::Resettable for BAUD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sercom0/spis/ctrla.rs b/pac/atsamc21e/src/sercom0/spis/ctrla.rs new file mode 100644 index 000000000000..6151433a8529 --- /dev/null +++ b/pac/atsamc21e/src/sercom0/spis/ctrla.rs @@ -0,0 +1,992 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: USART with external clock"] + USART_EXT_CLK = 0, + #[doc = "1: USART with internal clock"] + USART_INT_CLK = 1, + #[doc = "2: SPI in slave operation"] + SPI_SLAVE = 2, + #[doc = "3: SPI in master operation"] + SPI_MASTER = 3, + #[doc = "4: I2C slave operation"] + I2C_SLAVE = 4, + #[doc = "5: I2C master operation"] + I2C_MASTER = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::USART_EXT_CLK), + 1 => Some(MODE_A::USART_INT_CLK), + 2 => Some(MODE_A::SPI_SLAVE), + 3 => Some(MODE_A::SPI_MASTER), + 4 => Some(MODE_A::I2C_SLAVE), + 5 => Some(MODE_A::I2C_MASTER), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_EXT_CLK`"] + #[inline(always)] + pub fn is_usart_ext_clk(&self) -> bool { + **self == MODE_A::USART_EXT_CLK + } + #[doc = "Checks if the value of the field is `USART_INT_CLK`"] + #[inline(always)] + pub fn is_usart_int_clk(&self) -> bool { + **self == MODE_A::USART_INT_CLK + } + #[doc = "Checks if the value of the field is `SPI_SLAVE`"] + #[inline(always)] + pub fn is_spi_slave(&self) -> bool { + **self == MODE_A::SPI_SLAVE + } + #[doc = "Checks if the value of the field is `SPI_MASTER`"] + #[inline(always)] + pub fn is_spi_master(&self) -> bool { + **self == MODE_A::SPI_MASTER + } + #[doc = "Checks if the value of the field is `I2C_SLAVE`"] + #[inline(always)] + pub fn is_i2c_slave(&self) -> bool { + **self == MODE_A::I2C_SLAVE + } + #[doc = "Checks if the value of the field is `I2C_MASTER`"] + #[inline(always)] + pub fn is_i2c_master(&self) -> bool { + **self == MODE_A::I2C_MASTER + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART with external clock"] + #[inline(always)] + pub fn usart_ext_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_EXT_CLK) + } + #[doc = "USART with internal clock"] + #[inline(always)] + pub fn usart_int_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_INT_CLK) + } + #[doc = "SPI in slave operation"] + #[inline(always)] + pub fn spi_slave(self) -> &'a mut W { + self.variant(MODE_A::SPI_SLAVE) + } + #[doc = "SPI in master operation"] + #[inline(always)] + pub fn spi_master(self) -> &'a mut W { + self.variant(MODE_A::SPI_MASTER) + } + #[doc = "I2C slave operation"] + #[inline(always)] + pub fn i2c_slave(self) -> &'a mut W { + self.variant(MODE_A::I2C_SLAVE) + } + #[doc = "I2C master operation"] + #[inline(always)] + pub fn i2c_master(self) -> &'a mut W { + self.variant(MODE_A::I2C_MASTER) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 2)) | ((value as u32 & 0x07) << 2); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `IBON` reader - Immediate Buffer Overflow Notification"] +pub struct IBON_R(crate::FieldReader); +impl IBON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IBON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IBON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IBON` writer - Immediate Buffer Overflow Notification"] +pub struct IBON_W<'a> { + w: &'a mut W, +} +impl<'a> IBON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Data Out Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DOPO_A { + #[doc = "0: DO on PAD\\[0\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + PAD0 = 0, + #[doc = "1: DO on PAD\\[2\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + PAD1 = 1, + #[doc = "2: DO on PAD\\[3\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + PAD2 = 2, + #[doc = "3: DO on PAD\\[0\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + PAD3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DOPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `DOPO` reader - Data Out Pinout"] +pub struct DOPO_R(crate::FieldReader); +impl DOPO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DOPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DOPO_A { + match self.bits { + 0 => DOPO_A::PAD0, + 1 => DOPO_A::PAD1, + 2 => DOPO_A::PAD2, + 3 => DOPO_A::PAD3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == DOPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD1`"] + #[inline(always)] + pub fn is_pad1(&self) -> bool { + **self == DOPO_A::PAD1 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == DOPO_A::PAD2 + } + #[doc = "Checks if the value of the field is `PAD3`"] + #[inline(always)] + pub fn is_pad3(&self) -> bool { + **self == DOPO_A::PAD3 + } +} +impl core::ops::Deref for DOPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DOPO` writer - Data Out Pinout"] +pub struct DOPO_W<'a> { + w: &'a mut W, +} +impl<'a> DOPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DOPO_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "DO on PAD\\[0\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(DOPO_A::PAD0) + } + #[doc = "DO on PAD\\[2\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + #[inline(always)] + pub fn pad1(self) -> &'a mut W { + self.variant(DOPO_A::PAD1) + } + #[doc = "DO on PAD\\[3\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(DOPO_A::PAD2) + } + #[doc = "DO on PAD\\[0\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + #[inline(always)] + pub fn pad3(self) -> &'a mut W { + self.variant(DOPO_A::PAD3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Data In Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DIPO_A { + #[doc = "0: SERCOM PAD\\[0\\]"] + PAD0 = 0, + #[doc = "1: SERCOM PAD\\[1\\]"] + PAD1 = 1, + #[doc = "2: SERCOM PAD\\[2\\]"] + PAD2 = 2, + #[doc = "3: SERCOM PAD\\[3\\]"] + PAD3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DIPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `DIPO` reader - Data In Pinout"] +pub struct DIPO_R(crate::FieldReader); +impl DIPO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DIPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DIPO_A { + match self.bits { + 0 => DIPO_A::PAD0, + 1 => DIPO_A::PAD1, + 2 => DIPO_A::PAD2, + 3 => DIPO_A::PAD3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == DIPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD1`"] + #[inline(always)] + pub fn is_pad1(&self) -> bool { + **self == DIPO_A::PAD1 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == DIPO_A::PAD2 + } + #[doc = "Checks if the value of the field is `PAD3`"] + #[inline(always)] + pub fn is_pad3(&self) -> bool { + **self == DIPO_A::PAD3 + } +} +impl core::ops::Deref for DIPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIPO` writer - Data In Pinout"] +pub struct DIPO_W<'a> { + w: &'a mut W, +} +impl<'a> DIPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DIPO_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "SERCOM PAD\\[0\\]"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(DIPO_A::PAD0) + } + #[doc = "SERCOM PAD\\[1\\]"] + #[inline(always)] + pub fn pad1(self) -> &'a mut W { + self.variant(DIPO_A::PAD1) + } + #[doc = "SERCOM PAD\\[2\\]"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(DIPO_A::PAD2) + } + #[doc = "SERCOM PAD\\[3\\]"] + #[inline(always)] + pub fn pad3(self) -> &'a mut W { + self.variant(DIPO_A::PAD3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 20)) | ((value as u32 & 0x03) << 20); + self.w + } +} +#[doc = "Frame Format\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FORM_A { + #[doc = "0: SPI Frame"] + SPI_FRAME = 0, + #[doc = "2: SPI Frame with Addr"] + SPI_FRAME_WITH_ADDR = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FORM_A) -> Self { + variant as _ + } +} +#[doc = "Field `FORM` reader - Frame Format"] +pub struct FORM_R(crate::FieldReader); +impl FORM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FORM_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(FORM_A::SPI_FRAME), + 2 => Some(FORM_A::SPI_FRAME_WITH_ADDR), + _ => None, + } + } + #[doc = "Checks if the value of the field is `SPI_FRAME`"] + #[inline(always)] + pub fn is_spi_frame(&self) -> bool { + **self == FORM_A::SPI_FRAME + } + #[doc = "Checks if the value of the field is `SPI_FRAME_WITH_ADDR`"] + #[inline(always)] + pub fn is_spi_frame_with_addr(&self) -> bool { + **self == FORM_A::SPI_FRAME_WITH_ADDR + } +} +impl core::ops::Deref for FORM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FORM` writer - Frame Format"] +pub struct FORM_W<'a> { + w: &'a mut W, +} +impl<'a> FORM_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FORM_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "SPI Frame"] + #[inline(always)] + pub fn spi_frame(self) -> &'a mut W { + self.variant(FORM_A::SPI_FRAME) + } + #[doc = "SPI Frame with Addr"] + #[inline(always)] + pub fn spi_frame_with_addr(self) -> &'a mut W { + self.variant(FORM_A::SPI_FRAME_WITH_ADDR) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Clock Phase\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CPHA_A { + #[doc = "0: The data is sampled on a leading SCK edge and changed on a trailing SCK edge"] + LEADING_EDGE = 0, + #[doc = "1: The data is sampled on a trailing SCK edge and changed on a leading SCK edge"] + TRAILING_EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CPHA_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CPHA` reader - Clock Phase"] +pub struct CPHA_R(crate::FieldReader); +impl CPHA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPHA_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CPHA_A { + match self.bits { + false => CPHA_A::LEADING_EDGE, + true => CPHA_A::TRAILING_EDGE, + } + } + #[doc = "Checks if the value of the field is `LEADING_EDGE`"] + #[inline(always)] + pub fn is_leading_edge(&self) -> bool { + **self == CPHA_A::LEADING_EDGE + } + #[doc = "Checks if the value of the field is `TRAILING_EDGE`"] + #[inline(always)] + pub fn is_trailing_edge(&self) -> bool { + **self == CPHA_A::TRAILING_EDGE + } +} +impl core::ops::Deref for CPHA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPHA` writer - Clock Phase"] +pub struct CPHA_W<'a> { + w: &'a mut W, +} +impl<'a> CPHA_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CPHA_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "The data is sampled on a leading SCK edge and changed on a trailing SCK edge"] + #[inline(always)] + pub fn leading_edge(self) -> &'a mut W { + self.variant(CPHA_A::LEADING_EDGE) + } + #[doc = "The data is sampled on a trailing SCK edge and changed on a leading SCK edge"] + #[inline(always)] + pub fn trailing_edge(self) -> &'a mut W { + self.variant(CPHA_A::TRAILING_EDGE) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Clock Polarity\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CPOL_A { + #[doc = "0: SCK is low when idle"] + IDLE_LOW = 0, + #[doc = "1: SCK is high when idle"] + IDLE_HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CPOL_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CPOL` reader - Clock Polarity"] +pub struct CPOL_R(crate::FieldReader); +impl CPOL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPOL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CPOL_A { + match self.bits { + false => CPOL_A::IDLE_LOW, + true => CPOL_A::IDLE_HIGH, + } + } + #[doc = "Checks if the value of the field is `IDLE_LOW`"] + #[inline(always)] + pub fn is_idle_low(&self) -> bool { + **self == CPOL_A::IDLE_LOW + } + #[doc = "Checks if the value of the field is `IDLE_HIGH`"] + #[inline(always)] + pub fn is_idle_high(&self) -> bool { + **self == CPOL_A::IDLE_HIGH + } +} +impl core::ops::Deref for CPOL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPOL` writer - Clock Polarity"] +pub struct CPOL_W<'a> { + w: &'a mut W, +} +impl<'a> CPOL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CPOL_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "SCK is low when idle"] + #[inline(always)] + pub fn idle_low(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_LOW) + } + #[doc = "SCK is high when idle"] + #[inline(always)] + pub fn idle_high(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_HIGH) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29); + self.w + } +} +#[doc = "Data Order\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum DORD_A { + #[doc = "0: MSB is transferred first"] + MSB = 0, + #[doc = "1: LSB is transferred first"] + LSB = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DORD_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DORD` reader - Data Order"] +pub struct DORD_R(crate::FieldReader); +impl DORD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DORD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DORD_A { + match self.bits { + false => DORD_A::MSB, + true => DORD_A::LSB, + } + } + #[doc = "Checks if the value of the field is `MSB`"] + #[inline(always)] + pub fn is_msb(&self) -> bool { + **self == DORD_A::MSB + } + #[doc = "Checks if the value of the field is `LSB`"] + #[inline(always)] + pub fn is_lsb(&self) -> bool { + **self == DORD_A::LSB + } +} +impl core::ops::Deref for DORD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DORD` writer - Data Order"] +pub struct DORD_W<'a> { + w: &'a mut W, +} +impl<'a> DORD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DORD_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "MSB is transferred first"] + #[inline(always)] + pub fn msb(self) -> &'a mut W { + self.variant(DORD_A::MSB) + } + #[doc = "LSB is transferred first"] + #[inline(always)] + pub fn lsb(self) -> &'a mut W { + self.variant(DORD_A::LSB) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x07) as u8) + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&self) -> IBON_R { + IBON_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bits 16:17 - Data Out Pinout"] + #[inline(always)] + pub fn dopo(&self) -> DOPO_R { + DOPO_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bits 20:21 - Data In Pinout"] + #[inline(always)] + pub fn dipo(&self) -> DIPO_R { + DIPO_R::new(((self.bits >> 20) & 0x03) as u8) + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&self) -> FORM_R { + FORM_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 28 - Clock Phase"] + #[inline(always)] + pub fn cpha(&self) -> CPHA_R { + CPHA_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&self) -> CPOL_R { + CPOL_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&self) -> DORD_R { + DORD_R::new(((self.bits >> 30) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&mut self) -> IBON_W { + IBON_W { w: self } + } + #[doc = "Bits 16:17 - Data Out Pinout"] + #[inline(always)] + pub fn dopo(&mut self) -> DOPO_W { + DOPO_W { w: self } + } + #[doc = "Bits 20:21 - Data In Pinout"] + #[inline(always)] + pub fn dipo(&mut self) -> DIPO_W { + DIPO_W { w: self } + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&mut self) -> FORM_W { + FORM_W { w: self } + } + #[doc = "Bit 28 - Clock Phase"] + #[inline(always)] + pub fn cpha(&mut self) -> CPHA_W { + CPHA_W { w: self } + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&mut self) -> CPOL_W { + CPOL_W { w: self } + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&mut self) -> DORD_W { + DORD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sercom0/spis/ctrlb.rs b/pac/atsamc21e/src/sercom0/spis/ctrlb.rs new file mode 100644 index 000000000000..ccb70582cf34 --- /dev/null +++ b/pac/atsamc21e/src/sercom0/spis/ctrlb.rs @@ -0,0 +1,439 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Character Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CHSIZE_A { + #[doc = "0: 8 bits"] + _8_BIT = 0, + #[doc = "1: 9 bits"] + _9_BIT = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CHSIZE_A) -> Self { + variant as _ + } +} +#[doc = "Field `CHSIZE` reader - Character Size"] +pub struct CHSIZE_R(crate::FieldReader); +impl CHSIZE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CHSIZE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CHSIZE_A::_8_BIT), + 1 => Some(CHSIZE_A::_9_BIT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_8_BIT`"] + #[inline(always)] + pub fn is_8_bit(&self) -> bool { + **self == CHSIZE_A::_8_BIT + } + #[doc = "Checks if the value of the field is `_9_BIT`"] + #[inline(always)] + pub fn is_9_bit(&self) -> bool { + **self == CHSIZE_A::_9_BIT + } +} +impl core::ops::Deref for CHSIZE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHSIZE` writer - Character Size"] +pub struct CHSIZE_W<'a> { + w: &'a mut W, +} +impl<'a> CHSIZE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CHSIZE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8 bits"] + #[inline(always)] + pub fn _8_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_8_BIT) + } + #[doc = "9 bits"] + #[inline(always)] + pub fn _9_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_9_BIT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Field `PLOADEN` reader - Data Preload Enable"] +pub struct PLOADEN_R(crate::FieldReader); +impl PLOADEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PLOADEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PLOADEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PLOADEN` writer - Data Preload Enable"] +pub struct PLOADEN_W<'a> { + w: &'a mut W, +} +impl<'a> PLOADEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `SSDE` reader - Slave Select Low Detect Enable"] +pub struct SSDE_R(crate::FieldReader); +impl SSDE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SSDE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSDE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSDE` writer - Slave Select Low Detect Enable"] +pub struct SSDE_W<'a> { + w: &'a mut W, +} +impl<'a> SSDE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `MSSEN` reader - Master Slave Select Enable"] +pub struct MSSEN_R(crate::FieldReader); +impl MSSEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MSSEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MSSEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MSSEN` writer - Master Slave Select Enable"] +pub struct MSSEN_W<'a> { + w: &'a mut W, +} +impl<'a> MSSEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Address Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum AMODE_A { + #[doc = "0: SPI Address mask"] + MASK = 0, + #[doc = "1: Two unique Addressess"] + _2_ADDRESSES = 1, + #[doc = "2: Address Range"] + RANGE = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: AMODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `AMODE` reader - Address Mode"] +pub struct AMODE_R(crate::FieldReader); +impl AMODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + AMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(AMODE_A::MASK), + 1 => Some(AMODE_A::_2_ADDRESSES), + 2 => Some(AMODE_A::RANGE), + _ => None, + } + } + #[doc = "Checks if the value of the field is `MASK`"] + #[inline(always)] + pub fn is_mask(&self) -> bool { + **self == AMODE_A::MASK + } + #[doc = "Checks if the value of the field is `_2_ADDRESSES`"] + #[inline(always)] + pub fn is_2_addresses(&self) -> bool { + **self == AMODE_A::_2_ADDRESSES + } + #[doc = "Checks if the value of the field is `RANGE`"] + #[inline(always)] + pub fn is_range(&self) -> bool { + **self == AMODE_A::RANGE + } +} +impl core::ops::Deref for AMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AMODE` writer - Address Mode"] +pub struct AMODE_W<'a> { + w: &'a mut W, +} +impl<'a> AMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: AMODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "SPI Address mask"] + #[inline(always)] + pub fn mask(self) -> &'a mut W { + self.variant(AMODE_A::MASK) + } + #[doc = "Two unique Addressess"] + #[inline(always)] + pub fn _2_addresses(self) -> &'a mut W { + self.variant(AMODE_A::_2_ADDRESSES) + } + #[doc = "Address Range"] + #[inline(always)] + pub fn range(self) -> &'a mut W { + self.variant(AMODE_A::RANGE) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 14)) | ((value as u32 & 0x03) << 14); + self.w + } +} +#[doc = "Field `RXEN` reader - Receiver Enable"] +pub struct RXEN_R(crate::FieldReader); +impl RXEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXEN` writer - Receiver Enable"] +pub struct RXEN_W<'a> { + w: &'a mut W, +} +impl<'a> RXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&self) -> CHSIZE_R { + CHSIZE_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 6 - Data Preload Enable"] + #[inline(always)] + pub fn ploaden(&self) -> PLOADEN_R { + PLOADEN_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 9 - Slave Select Low Detect Enable"] + #[inline(always)] + pub fn ssde(&self) -> SSDE_R { + SSDE_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 13 - Master Slave Select Enable"] + #[inline(always)] + pub fn mssen(&self) -> MSSEN_R { + MSSEN_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bits 14:15 - Address Mode"] + #[inline(always)] + pub fn amode(&self) -> AMODE_R { + AMODE_R::new(((self.bits >> 14) & 0x03) as u8) + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&self) -> RXEN_R { + RXEN_R::new(((self.bits >> 17) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&mut self) -> CHSIZE_W { + CHSIZE_W { w: self } + } + #[doc = "Bit 6 - Data Preload Enable"] + #[inline(always)] + pub fn ploaden(&mut self) -> PLOADEN_W { + PLOADEN_W { w: self } + } + #[doc = "Bit 9 - Slave Select Low Detect Enable"] + #[inline(always)] + pub fn ssde(&mut self) -> SSDE_W { + SSDE_W { w: self } + } + #[doc = "Bit 13 - Master Slave Select Enable"] + #[inline(always)] + pub fn mssen(&mut self) -> MSSEN_W { + MSSEN_W { w: self } + } + #[doc = "Bits 14:15 - Address Mode"] + #[inline(always)] + pub fn amode(&mut self) -> AMODE_W { + AMODE_W { w: self } + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&mut self) -> RXEN_W { + RXEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sercom0/spis/data.rs b/pac/atsamc21e/src/sercom0/spis/data.rs new file mode 100644 index 000000000000..4edf8089b29f --- /dev/null +++ b/pac/atsamc21e/src/sercom0/spis/data.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data Value"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data Value"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01ff) | (value as u32 & 0x01ff); + self.w + } +} +impl R { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new((self.bits & 0x01ff) as u16) + } +} +impl W { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sercom0/spis/dbgctrl.rs b/pac/atsamc21e/src/sercom0/spis/dbgctrl.rs new file mode 100644 index 000000000000..ec36bbd26057 --- /dev/null +++ b/pac/atsamc21e/src/sercom0/spis/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGSTOP` reader - Debug Mode"] +pub struct DBGSTOP_R(crate::FieldReader); +impl DBGSTOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGSTOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGSTOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGSTOP` writer - Debug Mode"] +pub struct DBGSTOP_W<'a> { + w: &'a mut W, +} +impl<'a> DBGSTOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&self) -> DBGSTOP_R { + DBGSTOP_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&mut self) -> DBGSTOP_W { + DBGSTOP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sercom0/spis/intenclr.rs b/pac/atsamc21e/src/sercom0/spis/intenclr.rs new file mode 100644 index 000000000000..e4c9ee0d506d --- /dev/null +++ b/pac/atsamc21e/src/sercom0/spis/intenclr.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Disable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Disable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Disable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Disable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Disable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Disable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SSL` reader - Slave Select Low Interrupt Disable"] +pub struct SSL_R(crate::FieldReader); +impl SSL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SSL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSL` writer - Slave Select Low Interrupt Disable"] +pub struct SSL_W<'a> { + w: &'a mut W, +} +impl<'a> SSL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Disable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Disable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Slave Select Low Interrupt Disable"] + #[inline(always)] + pub fn ssl(&self) -> SSL_R { + SSL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Slave Select Low Interrupt Disable"] + #[inline(always)] + pub fn ssl(&mut self) -> SSL_W { + SSL_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sercom0/spis/intenset.rs b/pac/atsamc21e/src/sercom0/spis/intenset.rs new file mode 100644 index 000000000000..99582a624ebc --- /dev/null +++ b/pac/atsamc21e/src/sercom0/spis/intenset.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Enable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Enable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Enable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Enable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Enable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Enable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SSL` reader - Slave Select Low Interrupt Enable"] +pub struct SSL_R(crate::FieldReader); +impl SSL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SSL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSL` writer - Slave Select Low Interrupt Enable"] +pub struct SSL_W<'a> { + w: &'a mut W, +} +impl<'a> SSL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Slave Select Low Interrupt Enable"] + #[inline(always)] + pub fn ssl(&self) -> SSL_R { + SSL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Slave Select Low Interrupt Enable"] + #[inline(always)] + pub fn ssl(&mut self) -> SSL_W { + SSL_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sercom0/spis/intflag.rs b/pac/atsamc21e/src/sercom0/spis/intflag.rs new file mode 100644 index 000000000000..589e73c2329f --- /dev/null +++ b/pac/atsamc21e/src/sercom0/spis/intflag.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SSL` reader - Slave Select Low Interrupt Flag"] +pub struct SSL_R(crate::FieldReader); +impl SSL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SSL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSL` writer - Slave Select Low Interrupt Flag"] +pub struct SSL_W<'a> { + w: &'a mut W, +} +impl<'a> SSL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Slave Select Low Interrupt Flag"] + #[inline(always)] + pub fn ssl(&self) -> SSL_R { + SSL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Slave Select Low Interrupt Flag"] + #[inline(always)] + pub fn ssl(&mut self) -> SSL_W { + SSL_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sercom0/spis/status.rs b/pac/atsamc21e/src/sercom0/spis/status.rs new file mode 100644 index 000000000000..55c39c1a709f --- /dev/null +++ b/pac/atsamc21e/src/sercom0/spis/status.rs @@ -0,0 +1,113 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BUFOVF` reader - Buffer Overflow"] +pub struct BUFOVF_R(crate::FieldReader); +impl BUFOVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUFOVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUFOVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUFOVF` writer - Buffer Overflow"] +pub struct BUFOVF_W<'a> { + w: &'a mut W, +} +impl<'a> BUFOVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&self) -> BUFOVF_R { + BUFOVF_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&mut self) -> BUFOVF_W { + BUFOVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sercom0/spis/syncbusy.rs b/pac/atsamc21e/src/sercom0/spis/syncbusy.rs new file mode 100644 index 000000000000..ac2f2e2c27ec --- /dev/null +++ b/pac/atsamc21e/src/sercom0/spis/syncbusy.rs @@ -0,0 +1,93 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - SERCOM Enable Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLB` reader - CTRLB Synchronization Busy"] +pub struct CTRLB_R(crate::FieldReader); +impl CTRLB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM Enable Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - CTRLB Synchronization Busy"] + #[inline(always)] + pub fn ctrlb(&self) -> CTRLB_R { + CTRLB_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +#[doc = "SPIS Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sercom0/usart_ext.rs b/pac/atsamc21e/src/sercom0/usart_ext.rs new file mode 100644 index 000000000000..8c08b9efc1d5 --- /dev/null +++ b/pac/atsamc21e/src/sercom0/usart_ext.rs @@ -0,0 +1,60 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "USART_EXT Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "USART_EXT Control B"] +pub mod ctrlb; +#[doc = "CTRLC register accessor: an alias for `Reg`"] +pub type CTRLC = crate::Reg; +#[doc = "USART_EXT Control C"] +pub mod ctrlc; +#[doc = "BAUD register accessor: an alias for `Reg`"] +pub type BAUD = crate::Reg; +#[doc = "USART_EXT Baud Rate"] +pub mod baud; +#[doc = "BAUD_FRAC_MODE register accessor: an alias for `Reg`"] +pub type BAUD_FRAC_MODE = crate::Reg; +#[doc = "USART_EXT Baud Rate"] +pub mod baud_frac_mode; +#[doc = "BAUD_FRACFP_MODE register accessor: an alias for `Reg`"] +pub type BAUD_FRACFP_MODE = crate::Reg; +#[doc = "USART_EXT Baud Rate"] +pub mod baud_fracfp_mode; +#[doc = "BAUD_USARTFP_MODE register accessor: an alias for `Reg`"] +pub type BAUD_USARTFP_MODE = crate::Reg; +#[doc = "USART_EXT Baud Rate"] +pub mod baud_usartfp_mode; +#[doc = "RXPL register accessor: an alias for `Reg`"] +pub type RXPL = crate::Reg; +#[doc = "USART_EXT Receive Pulse Length"] +pub mod rxpl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "USART_EXT Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "USART_EXT Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "USART_EXT Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "USART_EXT Status"] +pub mod status; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "USART_EXT Synchronization Busy"] +pub mod syncbusy; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "USART_EXT Data"] +pub mod data; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "USART_EXT Debug Control"] +pub mod dbgctrl; diff --git a/pac/atsamc21e/src/sercom0/usart_ext/baud.rs b/pac/atsamc21e/src/sercom0/usart_ext/baud.rs new file mode 100644 index 000000000000..9558a8e1a52d --- /dev/null +++ b/pac/atsamc21e/src/sercom0/usart_ext/baud.rs @@ -0,0 +1,103 @@ +#[doc = "Register `BAUD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud](index.html) module"] +pub struct BAUD_SPEC; +impl crate::RegisterSpec for BAUD_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud::R](R) reader structure"] +impl crate::Readable for BAUD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud::W](W) writer structure"] +impl crate::Writable for BAUD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD to value 0"] +impl crate::Resettable for BAUD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sercom0/usart_ext/baud_frac_mode.rs b/pac/atsamc21e/src/sercom0/usart_ext/baud_frac_mode.rs new file mode 100644 index 000000000000..d7cdd4570e26 --- /dev/null +++ b/pac/atsamc21e/src/sercom0/usart_ext/baud_frac_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `BAUD_FRAC_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD_FRAC_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1fff) | (value as u16 & 0x1fff); + self.w + } +} +#[doc = "Field `FP` reader - Fractional Part"] +pub struct FP_R(crate::FieldReader); +impl FP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FP` writer - Fractional Part"] +pub struct FP_W<'a> { + w: &'a mut W, +} +impl<'a> FP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 13)) | ((value as u16 & 0x07) << 13); + self.w + } +} +impl R { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new((self.bits & 0x1fff) as u16) + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&self) -> FP_R { + FP_R::new(((self.bits >> 13) & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&mut self) -> FP_W { + FP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud_frac_mode](index.html) module"] +pub struct BAUD_FRAC_MODE_SPEC; +impl crate::RegisterSpec for BAUD_FRAC_MODE_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud_frac_mode::R](R) reader structure"] +impl crate::Readable for BAUD_FRAC_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud_frac_mode::W](W) writer structure"] +impl crate::Writable for BAUD_FRAC_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD_FRAC_MODE to value 0"] +impl crate::Resettable for BAUD_FRAC_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sercom0/usart_ext/baud_fracfp_mode.rs b/pac/atsamc21e/src/sercom0/usart_ext/baud_fracfp_mode.rs new file mode 100644 index 000000000000..c1dc50807677 --- /dev/null +++ b/pac/atsamc21e/src/sercom0/usart_ext/baud_fracfp_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `BAUD_FRACFP_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD_FRACFP_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1fff) | (value as u16 & 0x1fff); + self.w + } +} +#[doc = "Field `FP` reader - Fractional Part"] +pub struct FP_R(crate::FieldReader); +impl FP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FP` writer - Fractional Part"] +pub struct FP_W<'a> { + w: &'a mut W, +} +impl<'a> FP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 13)) | ((value as u16 & 0x07) << 13); + self.w + } +} +impl R { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new((self.bits & 0x1fff) as u16) + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&self) -> FP_R { + FP_R::new(((self.bits >> 13) & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&mut self) -> FP_W { + FP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud_fracfp_mode](index.html) module"] +pub struct BAUD_FRACFP_MODE_SPEC; +impl crate::RegisterSpec for BAUD_FRACFP_MODE_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud_fracfp_mode::R](R) reader structure"] +impl crate::Readable for BAUD_FRACFP_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud_fracfp_mode::W](W) writer structure"] +impl crate::Writable for BAUD_FRACFP_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD_FRACFP_MODE to value 0"] +impl crate::Resettable for BAUD_FRACFP_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sercom0/usart_ext/baud_usartfp_mode.rs b/pac/atsamc21e/src/sercom0/usart_ext/baud_usartfp_mode.rs new file mode 100644 index 000000000000..8d4db16e0245 --- /dev/null +++ b/pac/atsamc21e/src/sercom0/usart_ext/baud_usartfp_mode.rs @@ -0,0 +1,103 @@ +#[doc = "Register `BAUD_USARTFP_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD_USARTFP_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud_usartfp_mode](index.html) module"] +pub struct BAUD_USARTFP_MODE_SPEC; +impl crate::RegisterSpec for BAUD_USARTFP_MODE_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud_usartfp_mode::R](R) reader structure"] +impl crate::Readable for BAUD_USARTFP_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud_usartfp_mode::W](W) writer structure"] +impl crate::Writable for BAUD_USARTFP_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD_USARTFP_MODE to value 0"] +impl crate::Resettable for BAUD_USARTFP_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sercom0/usart_ext/ctrla.rs b/pac/atsamc21e/src/sercom0/usart_ext/ctrla.rs new file mode 100644 index 000000000000..535875ac8b25 --- /dev/null +++ b/pac/atsamc21e/src/sercom0/usart_ext/ctrla.rs @@ -0,0 +1,1171 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: USART with external clock"] + USART_EXT_CLK = 0, + #[doc = "1: USART with internal clock"] + USART_INT_CLK = 1, + #[doc = "2: SPI in slave operation"] + SPI_SLAVE = 2, + #[doc = "3: SPI in master operation"] + SPI_MASTER = 3, + #[doc = "4: I2C slave operation"] + I2C_SLAVE = 4, + #[doc = "5: I2C master operation"] + I2C_MASTER = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::USART_EXT_CLK), + 1 => Some(MODE_A::USART_INT_CLK), + 2 => Some(MODE_A::SPI_SLAVE), + 3 => Some(MODE_A::SPI_MASTER), + 4 => Some(MODE_A::I2C_SLAVE), + 5 => Some(MODE_A::I2C_MASTER), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_EXT_CLK`"] + #[inline(always)] + pub fn is_usart_ext_clk(&self) -> bool { + **self == MODE_A::USART_EXT_CLK + } + #[doc = "Checks if the value of the field is `USART_INT_CLK`"] + #[inline(always)] + pub fn is_usart_int_clk(&self) -> bool { + **self == MODE_A::USART_INT_CLK + } + #[doc = "Checks if the value of the field is `SPI_SLAVE`"] + #[inline(always)] + pub fn is_spi_slave(&self) -> bool { + **self == MODE_A::SPI_SLAVE + } + #[doc = "Checks if the value of the field is `SPI_MASTER`"] + #[inline(always)] + pub fn is_spi_master(&self) -> bool { + **self == MODE_A::SPI_MASTER + } + #[doc = "Checks if the value of the field is `I2C_SLAVE`"] + #[inline(always)] + pub fn is_i2c_slave(&self) -> bool { + **self == MODE_A::I2C_SLAVE + } + #[doc = "Checks if the value of the field is `I2C_MASTER`"] + #[inline(always)] + pub fn is_i2c_master(&self) -> bool { + **self == MODE_A::I2C_MASTER + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART with external clock"] + #[inline(always)] + pub fn usart_ext_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_EXT_CLK) + } + #[doc = "USART with internal clock"] + #[inline(always)] + pub fn usart_int_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_INT_CLK) + } + #[doc = "SPI in slave operation"] + #[inline(always)] + pub fn spi_slave(self) -> &'a mut W { + self.variant(MODE_A::SPI_SLAVE) + } + #[doc = "SPI in master operation"] + #[inline(always)] + pub fn spi_master(self) -> &'a mut W { + self.variant(MODE_A::SPI_MASTER) + } + #[doc = "I2C slave operation"] + #[inline(always)] + pub fn i2c_slave(self) -> &'a mut W { + self.variant(MODE_A::I2C_SLAVE) + } + #[doc = "I2C master operation"] + #[inline(always)] + pub fn i2c_master(self) -> &'a mut W { + self.variant(MODE_A::I2C_MASTER) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 2)) | ((value as u32 & 0x07) << 2); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `IBON` reader - Immediate Buffer Overflow Notification"] +pub struct IBON_R(crate::FieldReader); +impl IBON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IBON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IBON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IBON` writer - Immediate Buffer Overflow Notification"] +pub struct IBON_W<'a> { + w: &'a mut W, +} +impl<'a> IBON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Sample\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SAMPR_A { + #[doc = "0: 16x over-sampling using arithmetic baudrate generation"] + _16X_ARITHMETIC = 0, + #[doc = "1: 16x over-sampling using fractional baudrate generation"] + _16X_FRACTIONAL = 1, + #[doc = "2: 8x over-sampling using arithmetic baudrate generation"] + _8X_ARITHMETIC = 2, + #[doc = "3: 8x over-sampling using fractional baudrate generation"] + _8X_FRACTIONAL = 3, + #[doc = "4: 3x over-sampling using arithmetic baudrate generation"] + _3X_ARITHMETIC = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SAMPR_A) -> Self { + variant as _ + } +} +#[doc = "Field `SAMPR` reader - Sample"] +pub struct SAMPR_R(crate::FieldReader); +impl SAMPR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SAMPR_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SAMPR_A::_16X_ARITHMETIC), + 1 => Some(SAMPR_A::_16X_FRACTIONAL), + 2 => Some(SAMPR_A::_8X_ARITHMETIC), + 3 => Some(SAMPR_A::_8X_FRACTIONAL), + 4 => Some(SAMPR_A::_3X_ARITHMETIC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_16X_ARITHMETIC`"] + #[inline(always)] + pub fn is_16x_arithmetic(&self) -> bool { + **self == SAMPR_A::_16X_ARITHMETIC + } + #[doc = "Checks if the value of the field is `_16X_FRACTIONAL`"] + #[inline(always)] + pub fn is_16x_fractional(&self) -> bool { + **self == SAMPR_A::_16X_FRACTIONAL + } + #[doc = "Checks if the value of the field is `_8X_ARITHMETIC`"] + #[inline(always)] + pub fn is_8x_arithmetic(&self) -> bool { + **self == SAMPR_A::_8X_ARITHMETIC + } + #[doc = "Checks if the value of the field is `_8X_FRACTIONAL`"] + #[inline(always)] + pub fn is_8x_fractional(&self) -> bool { + **self == SAMPR_A::_8X_FRACTIONAL + } + #[doc = "Checks if the value of the field is `_3X_ARITHMETIC`"] + #[inline(always)] + pub fn is_3x_arithmetic(&self) -> bool { + **self == SAMPR_A::_3X_ARITHMETIC + } +} +impl core::ops::Deref for SAMPR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SAMPR` writer - Sample"] +pub struct SAMPR_W<'a> { + w: &'a mut W, +} +impl<'a> SAMPR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SAMPR_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "16x over-sampling using arithmetic baudrate generation"] + #[inline(always)] + pub fn _16x_arithmetic(self) -> &'a mut W { + self.variant(SAMPR_A::_16X_ARITHMETIC) + } + #[doc = "16x over-sampling using fractional baudrate generation"] + #[inline(always)] + pub fn _16x_fractional(self) -> &'a mut W { + self.variant(SAMPR_A::_16X_FRACTIONAL) + } + #[doc = "8x over-sampling using arithmetic baudrate generation"] + #[inline(always)] + pub fn _8x_arithmetic(self) -> &'a mut W { + self.variant(SAMPR_A::_8X_ARITHMETIC) + } + #[doc = "8x over-sampling using fractional baudrate generation"] + #[inline(always)] + pub fn _8x_fractional(self) -> &'a mut W { + self.variant(SAMPR_A::_8X_FRACTIONAL) + } + #[doc = "3x over-sampling using arithmetic baudrate generation"] + #[inline(always)] + pub fn _3x_arithmetic(self) -> &'a mut W { + self.variant(SAMPR_A::_3X_ARITHMETIC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 13)) | ((value as u32 & 0x07) << 13); + self.w + } +} +#[doc = "Transmit Data Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum TXPO_A { + #[doc = "0: SERCOM PAD\\[0\\] +is used for data transmission"] + PAD0 = 0, + #[doc = "1: SERCOM PAD\\[2\\] +is used for data transmission"] + PAD2 = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: TXPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `TXPO` reader - Transmit Data Pinout"] +pub struct TXPO_R(crate::FieldReader); +impl TXPO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TXPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(TXPO_A::PAD0), + 1 => Some(TXPO_A::PAD2), + _ => None, + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == TXPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == TXPO_A::PAD2 + } +} +impl core::ops::Deref for TXPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXPO` writer - Transmit Data Pinout"] +pub struct TXPO_W<'a> { + w: &'a mut W, +} +impl<'a> TXPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TXPO_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "SERCOM PAD\\[0\\] +is used for data transmission"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(TXPO_A::PAD0) + } + #[doc = "SERCOM PAD\\[2\\] +is used for data transmission"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(TXPO_A::PAD2) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Receive Data Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum RXPO_A { + #[doc = "0: SERCOM PAD\\[0\\] +is used for data reception"] + PAD0 = 0, + #[doc = "1: SERCOM PAD\\[1\\] +is used for data reception"] + PAD1 = 1, + #[doc = "2: SERCOM PAD\\[2\\] +is used for data reception"] + PAD2 = 2, + #[doc = "3: SERCOM PAD\\[3\\] +is used for data reception"] + PAD3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RXPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `RXPO` reader - Receive Data Pinout"] +pub struct RXPO_R(crate::FieldReader); +impl RXPO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RXPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RXPO_A { + match self.bits { + 0 => RXPO_A::PAD0, + 1 => RXPO_A::PAD1, + 2 => RXPO_A::PAD2, + 3 => RXPO_A::PAD3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == RXPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD1`"] + #[inline(always)] + pub fn is_pad1(&self) -> bool { + **self == RXPO_A::PAD1 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == RXPO_A::PAD2 + } + #[doc = "Checks if the value of the field is `PAD3`"] + #[inline(always)] + pub fn is_pad3(&self) -> bool { + **self == RXPO_A::PAD3 + } +} +impl core::ops::Deref for RXPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXPO` writer - Receive Data Pinout"] +pub struct RXPO_W<'a> { + w: &'a mut W, +} +impl<'a> RXPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RXPO_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "SERCOM PAD\\[0\\] +is used for data reception"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(RXPO_A::PAD0) + } + #[doc = "SERCOM PAD\\[1\\] +is used for data reception"] + #[inline(always)] + pub fn pad1(self) -> &'a mut W { + self.variant(RXPO_A::PAD1) + } + #[doc = "SERCOM PAD\\[2\\] +is used for data reception"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(RXPO_A::PAD2) + } + #[doc = "SERCOM PAD\\[3\\] +is used for data reception"] + #[inline(always)] + pub fn pad3(self) -> &'a mut W { + self.variant(RXPO_A::PAD3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 20)) | ((value as u32 & 0x03) << 20); + self.w + } +} +#[doc = "Field `SAMPA` reader - Sample Adjustment"] +pub struct SAMPA_R(crate::FieldReader); +impl SAMPA_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SAMPA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SAMPA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SAMPA` writer - Sample Adjustment"] +pub struct SAMPA_W<'a> { + w: &'a mut W, +} +impl<'a> SAMPA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 22)) | ((value as u32 & 0x03) << 22); + self.w + } +} +#[doc = "Frame Format\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FORM_A { + #[doc = "0: USART frame"] + USART_FRAME_NO_PARITY = 0, + #[doc = "1: USART frame with parity"] + USART_FRAME_WITH_PARITY = 1, + #[doc = "2: LIN Master - Break and sync generation"] + USART_FRAME_LIN_MASTER_MODE = 2, + #[doc = "4: Auto-baud - break detection and auto-baud"] + USART_FRAME_AUTO_BAUD_NO_PARITY = 4, + #[doc = "5: Auto-baud - break detection and auto-baud with parity"] + USART_FRAME_AUTO_BAUD_WITH_PARITY = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FORM_A) -> Self { + variant as _ + } +} +#[doc = "Field `FORM` reader - Frame Format"] +pub struct FORM_R(crate::FieldReader); +impl FORM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FORM_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(FORM_A::USART_FRAME_NO_PARITY), + 1 => Some(FORM_A::USART_FRAME_WITH_PARITY), + 2 => Some(FORM_A::USART_FRAME_LIN_MASTER_MODE), + 4 => Some(FORM_A::USART_FRAME_AUTO_BAUD_NO_PARITY), + 5 => Some(FORM_A::USART_FRAME_AUTO_BAUD_WITH_PARITY), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_FRAME_NO_PARITY`"] + #[inline(always)] + pub fn is_usart_frame_no_parity(&self) -> bool { + **self == FORM_A::USART_FRAME_NO_PARITY + } + #[doc = "Checks if the value of the field is `USART_FRAME_WITH_PARITY`"] + #[inline(always)] + pub fn is_usart_frame_with_parity(&self) -> bool { + **self == FORM_A::USART_FRAME_WITH_PARITY + } + #[doc = "Checks if the value of the field is `USART_FRAME_LIN_MASTER_MODE`"] + #[inline(always)] + pub fn is_usart_frame_lin_master_mode(&self) -> bool { + **self == FORM_A::USART_FRAME_LIN_MASTER_MODE + } + #[doc = "Checks if the value of the field is `USART_FRAME_AUTO_BAUD_NO_PARITY`"] + #[inline(always)] + pub fn is_usart_frame_auto_baud_no_parity(&self) -> bool { + **self == FORM_A::USART_FRAME_AUTO_BAUD_NO_PARITY + } + #[doc = "Checks if the value of the field is `USART_FRAME_AUTO_BAUD_WITH_PARITY`"] + #[inline(always)] + pub fn is_usart_frame_auto_baud_with_parity(&self) -> bool { + **self == FORM_A::USART_FRAME_AUTO_BAUD_WITH_PARITY + } +} +impl core::ops::Deref for FORM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FORM` writer - Frame Format"] +pub struct FORM_W<'a> { + w: &'a mut W, +} +impl<'a> FORM_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FORM_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART frame"] + #[inline(always)] + pub fn usart_frame_no_parity(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_NO_PARITY) + } + #[doc = "USART frame with parity"] + #[inline(always)] + pub fn usart_frame_with_parity(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_WITH_PARITY) + } + #[doc = "LIN Master - Break and sync generation"] + #[inline(always)] + pub fn usart_frame_lin_master_mode(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_LIN_MASTER_MODE) + } + #[doc = "Auto-baud - break detection and auto-baud"] + #[inline(always)] + pub fn usart_frame_auto_baud_no_parity(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_AUTO_BAUD_NO_PARITY) + } + #[doc = "Auto-baud - break detection and auto-baud with parity"] + #[inline(always)] + pub fn usart_frame_auto_baud_with_parity(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_AUTO_BAUD_WITH_PARITY) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Communication Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CMODE_A { + #[doc = "0: Asynchronous Communication"] + ASYNC = 0, + #[doc = "1: Synchronous Communication"] + SYNC = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CMODE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CMODE` reader - Communication Mode"] +pub struct CMODE_R(crate::FieldReader); +impl CMODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CMODE_A { + match self.bits { + false => CMODE_A::ASYNC, + true => CMODE_A::SYNC, + } + } + #[doc = "Checks if the value of the field is `ASYNC`"] + #[inline(always)] + pub fn is_async(&self) -> bool { + **self == CMODE_A::ASYNC + } + #[doc = "Checks if the value of the field is `SYNC`"] + #[inline(always)] + pub fn is_sync(&self) -> bool { + **self == CMODE_A::SYNC + } +} +impl core::ops::Deref for CMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMODE` writer - Communication Mode"] +pub struct CMODE_W<'a> { + w: &'a mut W, +} +impl<'a> CMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMODE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Asynchronous Communication"] + #[inline(always)] + pub fn async_(self) -> &'a mut W { + self.variant(CMODE_A::ASYNC) + } + #[doc = "Synchronous Communication"] + #[inline(always)] + pub fn sync(self) -> &'a mut W { + self.variant(CMODE_A::SYNC) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Clock Polarity\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CPOL_A { + #[doc = "0: TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge"] + IDLE_LOW = 0, + #[doc = "1: TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge"] + IDLE_HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CPOL_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CPOL` reader - Clock Polarity"] +pub struct CPOL_R(crate::FieldReader); +impl CPOL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPOL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CPOL_A { + match self.bits { + false => CPOL_A::IDLE_LOW, + true => CPOL_A::IDLE_HIGH, + } + } + #[doc = "Checks if the value of the field is `IDLE_LOW`"] + #[inline(always)] + pub fn is_idle_low(&self) -> bool { + **self == CPOL_A::IDLE_LOW + } + #[doc = "Checks if the value of the field is `IDLE_HIGH`"] + #[inline(always)] + pub fn is_idle_high(&self) -> bool { + **self == CPOL_A::IDLE_HIGH + } +} +impl core::ops::Deref for CPOL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPOL` writer - Clock Polarity"] +pub struct CPOL_W<'a> { + w: &'a mut W, +} +impl<'a> CPOL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CPOL_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge"] + #[inline(always)] + pub fn idle_low(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_LOW) + } + #[doc = "TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge"] + #[inline(always)] + pub fn idle_high(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_HIGH) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29); + self.w + } +} +#[doc = "Data Order\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum DORD_A { + #[doc = "0: MSB is transmitted first"] + MSB = 0, + #[doc = "1: LSB is transmitted first"] + LSB = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DORD_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DORD` reader - Data Order"] +pub struct DORD_R(crate::FieldReader); +impl DORD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DORD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DORD_A { + match self.bits { + false => DORD_A::MSB, + true => DORD_A::LSB, + } + } + #[doc = "Checks if the value of the field is `MSB`"] + #[inline(always)] + pub fn is_msb(&self) -> bool { + **self == DORD_A::MSB + } + #[doc = "Checks if the value of the field is `LSB`"] + #[inline(always)] + pub fn is_lsb(&self) -> bool { + **self == DORD_A::LSB + } +} +impl core::ops::Deref for DORD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DORD` writer - Data Order"] +pub struct DORD_W<'a> { + w: &'a mut W, +} +impl<'a> DORD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DORD_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "MSB is transmitted first"] + #[inline(always)] + pub fn msb(self) -> &'a mut W { + self.variant(DORD_A::MSB) + } + #[doc = "LSB is transmitted first"] + #[inline(always)] + pub fn lsb(self) -> &'a mut W { + self.variant(DORD_A::LSB) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x07) as u8) + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&self) -> IBON_R { + IBON_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bits 13:15 - Sample"] + #[inline(always)] + pub fn sampr(&self) -> SAMPR_R { + SAMPR_R::new(((self.bits >> 13) & 0x07) as u8) + } + #[doc = "Bits 16:17 - Transmit Data Pinout"] + #[inline(always)] + pub fn txpo(&self) -> TXPO_R { + TXPO_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bits 20:21 - Receive Data Pinout"] + #[inline(always)] + pub fn rxpo(&self) -> RXPO_R { + RXPO_R::new(((self.bits >> 20) & 0x03) as u8) + } + #[doc = "Bits 22:23 - Sample Adjustment"] + #[inline(always)] + pub fn sampa(&self) -> SAMPA_R { + SAMPA_R::new(((self.bits >> 22) & 0x03) as u8) + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&self) -> FORM_R { + FORM_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 28 - Communication Mode"] + #[inline(always)] + pub fn cmode(&self) -> CMODE_R { + CMODE_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&self) -> CPOL_R { + CPOL_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&self) -> DORD_R { + DORD_R::new(((self.bits >> 30) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&mut self) -> IBON_W { + IBON_W { w: self } + } + #[doc = "Bits 13:15 - Sample"] + #[inline(always)] + pub fn sampr(&mut self) -> SAMPR_W { + SAMPR_W { w: self } + } + #[doc = "Bits 16:17 - Transmit Data Pinout"] + #[inline(always)] + pub fn txpo(&mut self) -> TXPO_W { + TXPO_W { w: self } + } + #[doc = "Bits 20:21 - Receive Data Pinout"] + #[inline(always)] + pub fn rxpo(&mut self) -> RXPO_W { + RXPO_W { w: self } + } + #[doc = "Bits 22:23 - Sample Adjustment"] + #[inline(always)] + pub fn sampa(&mut self) -> SAMPA_W { + SAMPA_W { w: self } + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&mut self) -> FORM_W { + FORM_W { w: self } + } + #[doc = "Bit 28 - Communication Mode"] + #[inline(always)] + pub fn cmode(&mut self) -> CMODE_W { + CMODE_W { w: self } + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&mut self) -> CPOL_W { + CPOL_W { w: self } + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&mut self) -> DORD_W { + DORD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sercom0/usart_ext/ctrlb.rs b/pac/atsamc21e/src/sercom0/usart_ext/ctrlb.rs new file mode 100644 index 000000000000..37567555e842 --- /dev/null +++ b/pac/atsamc21e/src/sercom0/usart_ext/ctrlb.rs @@ -0,0 +1,651 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Character Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CHSIZE_A { + #[doc = "0: 8 Bits"] + _8_BIT = 0, + #[doc = "1: 9 Bits"] + _9_BIT = 1, + #[doc = "5: 5 Bits"] + _5_BIT = 5, + #[doc = "6: 6 Bits"] + _6_BIT = 6, + #[doc = "7: 7 Bits"] + _7_BIT = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CHSIZE_A) -> Self { + variant as _ + } +} +#[doc = "Field `CHSIZE` reader - Character Size"] +pub struct CHSIZE_R(crate::FieldReader); +impl CHSIZE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CHSIZE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CHSIZE_A::_8_BIT), + 1 => Some(CHSIZE_A::_9_BIT), + 5 => Some(CHSIZE_A::_5_BIT), + 6 => Some(CHSIZE_A::_6_BIT), + 7 => Some(CHSIZE_A::_7_BIT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_8_BIT`"] + #[inline(always)] + pub fn is_8_bit(&self) -> bool { + **self == CHSIZE_A::_8_BIT + } + #[doc = "Checks if the value of the field is `_9_BIT`"] + #[inline(always)] + pub fn is_9_bit(&self) -> bool { + **self == CHSIZE_A::_9_BIT + } + #[doc = "Checks if the value of the field is `_5_BIT`"] + #[inline(always)] + pub fn is_5_bit(&self) -> bool { + **self == CHSIZE_A::_5_BIT + } + #[doc = "Checks if the value of the field is `_6_BIT`"] + #[inline(always)] + pub fn is_6_bit(&self) -> bool { + **self == CHSIZE_A::_6_BIT + } + #[doc = "Checks if the value of the field is `_7_BIT`"] + #[inline(always)] + pub fn is_7_bit(&self) -> bool { + **self == CHSIZE_A::_7_BIT + } +} +impl core::ops::Deref for CHSIZE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHSIZE` writer - Character Size"] +pub struct CHSIZE_W<'a> { + w: &'a mut W, +} +impl<'a> CHSIZE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CHSIZE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8 Bits"] + #[inline(always)] + pub fn _8_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_8_BIT) + } + #[doc = "9 Bits"] + #[inline(always)] + pub fn _9_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_9_BIT) + } + #[doc = "5 Bits"] + #[inline(always)] + pub fn _5_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_5_BIT) + } + #[doc = "6 Bits"] + #[inline(always)] + pub fn _6_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_6_BIT) + } + #[doc = "7 Bits"] + #[inline(always)] + pub fn _7_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_7_BIT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Stop Bit Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SBMODE_A { + #[doc = "0: One Stop Bit"] + _1_BIT = 0, + #[doc = "1: Two Stop Bits"] + _2_BIT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SBMODE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SBMODE` reader - Stop Bit Mode"] +pub struct SBMODE_R(crate::FieldReader); +impl SBMODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SBMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SBMODE_A { + match self.bits { + false => SBMODE_A::_1_BIT, + true => SBMODE_A::_2_BIT, + } + } + #[doc = "Checks if the value of the field is `_1_BIT`"] + #[inline(always)] + pub fn is_1_bit(&self) -> bool { + **self == SBMODE_A::_1_BIT + } + #[doc = "Checks if the value of the field is `_2_BIT`"] + #[inline(always)] + pub fn is_2_bit(&self) -> bool { + **self == SBMODE_A::_2_BIT + } +} +impl core::ops::Deref for SBMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SBMODE` writer - Stop Bit Mode"] +pub struct SBMODE_W<'a> { + w: &'a mut W, +} +impl<'a> SBMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SBMODE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "One Stop Bit"] + #[inline(always)] + pub fn _1_bit(self) -> &'a mut W { + self.variant(SBMODE_A::_1_BIT) + } + #[doc = "Two Stop Bits"] + #[inline(always)] + pub fn _2_bit(self) -> &'a mut W { + self.variant(SBMODE_A::_2_BIT) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `COLDEN` reader - Collision Detection Enable"] +pub struct COLDEN_R(crate::FieldReader); +impl COLDEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COLDEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COLDEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COLDEN` writer - Collision Detection Enable"] +pub struct COLDEN_W<'a> { + w: &'a mut W, +} +impl<'a> COLDEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `SFDE` reader - Start of Frame Detection Enable"] +pub struct SFDE_R(crate::FieldReader); +impl SFDE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SFDE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SFDE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SFDE` writer - Start of Frame Detection Enable"] +pub struct SFDE_W<'a> { + w: &'a mut W, +} +impl<'a> SFDE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `ENC` reader - Encoding Format"] +pub struct ENC_R(crate::FieldReader); +impl ENC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENC` writer - Encoding Format"] +pub struct ENC_W<'a> { + w: &'a mut W, +} +impl<'a> ENC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Parity Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PMODE_A { + #[doc = "0: Even Parity"] + EVEN = 0, + #[doc = "1: Odd Parity"] + ODD = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PMODE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PMODE` reader - Parity Mode"] +pub struct PMODE_R(crate::FieldReader); +impl PMODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PMODE_A { + match self.bits { + false => PMODE_A::EVEN, + true => PMODE_A::ODD, + } + } + #[doc = "Checks if the value of the field is `EVEN`"] + #[inline(always)] + pub fn is_even(&self) -> bool { + **self == PMODE_A::EVEN + } + #[doc = "Checks if the value of the field is `ODD`"] + #[inline(always)] + pub fn is_odd(&self) -> bool { + **self == PMODE_A::ODD + } +} +impl core::ops::Deref for PMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PMODE` writer - Parity Mode"] +pub struct PMODE_W<'a> { + w: &'a mut W, +} +impl<'a> PMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PMODE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Even Parity"] + #[inline(always)] + pub fn even(self) -> &'a mut W { + self.variant(PMODE_A::EVEN) + } + #[doc = "Odd Parity"] + #[inline(always)] + pub fn odd(self) -> &'a mut W { + self.variant(PMODE_A::ODD) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `TXEN` reader - Transmitter Enable"] +pub struct TXEN_R(crate::FieldReader); +impl TXEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXEN` writer - Transmitter Enable"] +pub struct TXEN_W<'a> { + w: &'a mut W, +} +impl<'a> TXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `RXEN` reader - Receiver Enable"] +pub struct RXEN_R(crate::FieldReader); +impl RXEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXEN` writer - Receiver Enable"] +pub struct RXEN_W<'a> { + w: &'a mut W, +} +impl<'a> RXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `LINCMD` reader - LIN Command"] +pub struct LINCMD_R(crate::FieldReader); +impl LINCMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LINCMD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LINCMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LINCMD` writer - LIN Command"] +pub struct LINCMD_W<'a> { + w: &'a mut W, +} +impl<'a> LINCMD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 24)) | ((value as u32 & 0x03) << 24); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&self) -> CHSIZE_R { + CHSIZE_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 6 - Stop Bit Mode"] + #[inline(always)] + pub fn sbmode(&self) -> SBMODE_R { + SBMODE_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 8 - Collision Detection Enable"] + #[inline(always)] + pub fn colden(&self) -> COLDEN_R { + COLDEN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Start of Frame Detection Enable"] + #[inline(always)] + pub fn sfde(&self) -> SFDE_R { + SFDE_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Encoding Format"] + #[inline(always)] + pub fn enc(&self) -> ENC_R { + ENC_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 13 - Parity Mode"] + #[inline(always)] + pub fn pmode(&self) -> PMODE_R { + PMODE_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 16 - Transmitter Enable"] + #[inline(always)] + pub fn txen(&self) -> TXEN_R { + TXEN_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&self) -> RXEN_R { + RXEN_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bits 24:25 - LIN Command"] + #[inline(always)] + pub fn lincmd(&self) -> LINCMD_R { + LINCMD_R::new(((self.bits >> 24) & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&mut self) -> CHSIZE_W { + CHSIZE_W { w: self } + } + #[doc = "Bit 6 - Stop Bit Mode"] + #[inline(always)] + pub fn sbmode(&mut self) -> SBMODE_W { + SBMODE_W { w: self } + } + #[doc = "Bit 8 - Collision Detection Enable"] + #[inline(always)] + pub fn colden(&mut self) -> COLDEN_W { + COLDEN_W { w: self } + } + #[doc = "Bit 9 - Start of Frame Detection Enable"] + #[inline(always)] + pub fn sfde(&mut self) -> SFDE_W { + SFDE_W { w: self } + } + #[doc = "Bit 10 - Encoding Format"] + #[inline(always)] + pub fn enc(&mut self) -> ENC_W { + ENC_W { w: self } + } + #[doc = "Bit 13 - Parity Mode"] + #[inline(always)] + pub fn pmode(&mut self) -> PMODE_W { + PMODE_W { w: self } + } + #[doc = "Bit 16 - Transmitter Enable"] + #[inline(always)] + pub fn txen(&mut self) -> TXEN_W { + TXEN_W { w: self } + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&mut self) -> RXEN_W { + RXEN_W { w: self } + } + #[doc = "Bits 24:25 - LIN Command"] + #[inline(always)] + pub fn lincmd(&mut self) -> LINCMD_W { + LINCMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sercom0/usart_ext/ctrlc.rs b/pac/atsamc21e/src/sercom0/usart_ext/ctrlc.rs new file mode 100644 index 000000000000..5840d5c3bd06 --- /dev/null +++ b/pac/atsamc21e/src/sercom0/usart_ext/ctrlc.rs @@ -0,0 +1,177 @@ +#[doc = "Register `CTRLC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `GTIME` reader - RS485 Guard Time"] +pub struct GTIME_R(crate::FieldReader); +impl GTIME_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + GTIME_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GTIME_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GTIME` writer - RS485 Guard Time"] +pub struct GTIME_W<'a> { + w: &'a mut W, +} +impl<'a> GTIME_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Field `BRKLEN` reader - LIN Master Break Length"] +pub struct BRKLEN_R(crate::FieldReader); +impl BRKLEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BRKLEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BRKLEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BRKLEN` writer - LIN Master Break Length"] +pub struct BRKLEN_W<'a> { + w: &'a mut W, +} +impl<'a> BRKLEN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 8)) | ((value as u32 & 0x03) << 8); + self.w + } +} +#[doc = "Field `HDRDLY` reader - LIN Master Header Delay"] +pub struct HDRDLY_R(crate::FieldReader); +impl HDRDLY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + HDRDLY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HDRDLY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HDRDLY` writer - LIN Master Header Delay"] +pub struct HDRDLY_W<'a> { + w: &'a mut W, +} +impl<'a> HDRDLY_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 10)) | ((value as u32 & 0x03) << 10); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - RS485 Guard Time"] + #[inline(always)] + pub fn gtime(&self) -> GTIME_R { + GTIME_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bits 8:9 - LIN Master Break Length"] + #[inline(always)] + pub fn brklen(&self) -> BRKLEN_R { + BRKLEN_R::new(((self.bits >> 8) & 0x03) as u8) + } + #[doc = "Bits 10:11 - LIN Master Header Delay"] + #[inline(always)] + pub fn hdrdly(&self) -> HDRDLY_R { + HDRDLY_R::new(((self.bits >> 10) & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - RS485 Guard Time"] + #[inline(always)] + pub fn gtime(&mut self) -> GTIME_W { + GTIME_W { w: self } + } + #[doc = "Bits 8:9 - LIN Master Break Length"] + #[inline(always)] + pub fn brklen(&mut self) -> BRKLEN_W { + BRKLEN_W { w: self } + } + #[doc = "Bits 10:11 - LIN Master Header Delay"] + #[inline(always)] + pub fn hdrdly(&mut self) -> HDRDLY_W { + HDRDLY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Control C\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlc](index.html) module"] +pub struct CTRLC_SPEC; +impl crate::RegisterSpec for CTRLC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlc::R](R) reader structure"] +impl crate::Readable for CTRLC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlc::W](W) writer structure"] +impl crate::Writable for CTRLC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLC to value 0"] +impl crate::Resettable for CTRLC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sercom0/usart_ext/data.rs b/pac/atsamc21e/src/sercom0/usart_ext/data.rs new file mode 100644 index 000000000000..a54152c9571a --- /dev/null +++ b/pac/atsamc21e/src/sercom0/usart_ext/data.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data Value"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data Value"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01ff) | (value as u16 & 0x01ff); + self.w + } +} +impl R { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new((self.bits & 0x01ff) as u16) + } +} +impl W { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sercom0/usart_ext/dbgctrl.rs b/pac/atsamc21e/src/sercom0/usart_ext/dbgctrl.rs new file mode 100644 index 000000000000..6c844f3fe40d --- /dev/null +++ b/pac/atsamc21e/src/sercom0/usart_ext/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGSTOP` reader - Debug Mode"] +pub struct DBGSTOP_R(crate::FieldReader); +impl DBGSTOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGSTOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGSTOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGSTOP` writer - Debug Mode"] +pub struct DBGSTOP_W<'a> { + w: &'a mut W, +} +impl<'a> DBGSTOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&self) -> DBGSTOP_R { + DBGSTOP_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&mut self) -> DBGSTOP_W { + DBGSTOP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sercom0/usart_ext/intenclr.rs b/pac/atsamc21e/src/sercom0/usart_ext/intenclr.rs new file mode 100644 index 000000000000..a815553ce666 --- /dev/null +++ b/pac/atsamc21e/src/sercom0/usart_ext/intenclr.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Disable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Disable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Disable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Disable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Disable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Disable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RXS` reader - Receive Start Interrupt Disable"] +pub struct RXS_R(crate::FieldReader); +impl RXS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXS` writer - Receive Start Interrupt Disable"] +pub struct RXS_W<'a> { + w: &'a mut W, +} +impl<'a> RXS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CTSIC` reader - Clear To Send Input Change Interrupt Disable"] +pub struct CTSIC_R(crate::FieldReader); +impl CTSIC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTSIC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTSIC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTSIC` writer - Clear To Send Input Change Interrupt Disable"] +pub struct CTSIC_W<'a> { + w: &'a mut W, +} +impl<'a> CTSIC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RXBRK` reader - Break Received Interrupt Disable"] +pub struct RXBRK_R(crate::FieldReader); +impl RXBRK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXBRK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXBRK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXBRK` writer - Break Received Interrupt Disable"] +pub struct RXBRK_W<'a> { + w: &'a mut W, +} +impl<'a> RXBRK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Disable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Disable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Receive Start Interrupt Disable"] + #[inline(always)] + pub fn rxs(&self) -> RXS_R { + RXS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Disable"] + #[inline(always)] + pub fn ctsic(&self) -> CTSIC_R { + CTSIC_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Break Received Interrupt Disable"] + #[inline(always)] + pub fn rxbrk(&self) -> RXBRK_R { + RXBRK_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Receive Start Interrupt Disable"] + #[inline(always)] + pub fn rxs(&mut self) -> RXS_W { + RXS_W { w: self } + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Disable"] + #[inline(always)] + pub fn ctsic(&mut self) -> CTSIC_W { + CTSIC_W { w: self } + } + #[doc = "Bit 5 - Break Received Interrupt Disable"] + #[inline(always)] + pub fn rxbrk(&mut self) -> RXBRK_W { + RXBRK_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sercom0/usart_ext/intenset.rs b/pac/atsamc21e/src/sercom0/usart_ext/intenset.rs new file mode 100644 index 000000000000..e800681cf423 --- /dev/null +++ b/pac/atsamc21e/src/sercom0/usart_ext/intenset.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Enable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Enable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Enable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Enable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Enable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Enable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RXS` reader - Receive Start Interrupt Enable"] +pub struct RXS_R(crate::FieldReader); +impl RXS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXS` writer - Receive Start Interrupt Enable"] +pub struct RXS_W<'a> { + w: &'a mut W, +} +impl<'a> RXS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CTSIC` reader - Clear To Send Input Change Interrupt Enable"] +pub struct CTSIC_R(crate::FieldReader); +impl CTSIC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTSIC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTSIC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTSIC` writer - Clear To Send Input Change Interrupt Enable"] +pub struct CTSIC_W<'a> { + w: &'a mut W, +} +impl<'a> CTSIC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RXBRK` reader - Break Received Interrupt Enable"] +pub struct RXBRK_R(crate::FieldReader); +impl RXBRK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXBRK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXBRK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXBRK` writer - Break Received Interrupt Enable"] +pub struct RXBRK_W<'a> { + w: &'a mut W, +} +impl<'a> RXBRK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Receive Start Interrupt Enable"] + #[inline(always)] + pub fn rxs(&self) -> RXS_R { + RXS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Enable"] + #[inline(always)] + pub fn ctsic(&self) -> CTSIC_R { + CTSIC_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Break Received Interrupt Enable"] + #[inline(always)] + pub fn rxbrk(&self) -> RXBRK_R { + RXBRK_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Receive Start Interrupt Enable"] + #[inline(always)] + pub fn rxs(&mut self) -> RXS_W { + RXS_W { w: self } + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Enable"] + #[inline(always)] + pub fn ctsic(&mut self) -> CTSIC_W { + CTSIC_W { w: self } + } + #[doc = "Bit 5 - Break Received Interrupt Enable"] + #[inline(always)] + pub fn rxbrk(&mut self) -> RXBRK_W { + RXBRK_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sercom0/usart_ext/intflag.rs b/pac/atsamc21e/src/sercom0/usart_ext/intflag.rs new file mode 100644 index 000000000000..4b0be279a9ae --- /dev/null +++ b/pac/atsamc21e/src/sercom0/usart_ext/intflag.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RXS` reader - Receive Start Interrupt"] +pub struct RXS_R(crate::FieldReader); +impl RXS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXS` writer - Receive Start Interrupt"] +pub struct RXS_W<'a> { + w: &'a mut W, +} +impl<'a> RXS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CTSIC` reader - Clear To Send Input Change Interrupt"] +pub struct CTSIC_R(crate::FieldReader); +impl CTSIC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTSIC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTSIC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTSIC` writer - Clear To Send Input Change Interrupt"] +pub struct CTSIC_W<'a> { + w: &'a mut W, +} +impl<'a> CTSIC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RXBRK` reader - Break Received Interrupt"] +pub struct RXBRK_R(crate::FieldReader); +impl RXBRK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXBRK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXBRK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXBRK` writer - Break Received Interrupt"] +pub struct RXBRK_W<'a> { + w: &'a mut W, +} +impl<'a> RXBRK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Receive Start Interrupt"] + #[inline(always)] + pub fn rxs(&self) -> RXS_R { + RXS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt"] + #[inline(always)] + pub fn ctsic(&self) -> CTSIC_R { + CTSIC_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Break Received Interrupt"] + #[inline(always)] + pub fn rxbrk(&self) -> RXBRK_R { + RXBRK_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Receive Start Interrupt"] + #[inline(always)] + pub fn rxs(&mut self) -> RXS_W { + RXS_W { w: self } + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt"] + #[inline(always)] + pub fn ctsic(&mut self) -> CTSIC_W { + CTSIC_W { w: self } + } + #[doc = "Bit 5 - Break Received Interrupt"] + #[inline(always)] + pub fn rxbrk(&mut self) -> RXBRK_W { + RXBRK_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sercom0/usart_ext/rxpl.rs b/pac/atsamc21e/src/sercom0/usart_ext/rxpl.rs new file mode 100644 index 000000000000..174464dc16b5 --- /dev/null +++ b/pac/atsamc21e/src/sercom0/usart_ext/rxpl.rs @@ -0,0 +1,103 @@ +#[doc = "Register `RXPL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RXPL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RXPL` reader - Receive Pulse Length"] +pub struct RXPL_R(crate::FieldReader); +impl RXPL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RXPL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXPL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXPL` writer - Receive Pulse Length"] +pub struct RXPL_W<'a> { + w: &'a mut W, +} +impl<'a> RXPL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Receive Pulse Length"] + #[inline(always)] + pub fn rxpl(&self) -> RXPL_R { + RXPL_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Receive Pulse Length"] + #[inline(always)] + pub fn rxpl(&mut self) -> RXPL_W { + RXPL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Receive Pulse Length\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxpl](index.html) module"] +pub struct RXPL_SPEC; +impl crate::RegisterSpec for RXPL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [rxpl::R](R) reader structure"] +impl crate::Readable for RXPL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rxpl::W](W) writer structure"] +impl crate::Writable for RXPL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RXPL to value 0"] +impl crate::Resettable for RXPL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sercom0/usart_ext/status.rs b/pac/atsamc21e/src/sercom0/usart_ext/status.rs new file mode 100644 index 000000000000..a0c50c1bc2cf --- /dev/null +++ b/pac/atsamc21e/src/sercom0/usart_ext/status.rs @@ -0,0 +1,395 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PERR` reader - Parity Error"] +pub struct PERR_R(crate::FieldReader); +impl PERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERR` writer - Parity Error"] +pub struct PERR_W<'a> { + w: &'a mut W, +} +impl<'a> PERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `FERR` reader - Frame Error"] +pub struct FERR_R(crate::FieldReader); +impl FERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FERR` writer - Frame Error"] +pub struct FERR_W<'a> { + w: &'a mut W, +} +impl<'a> FERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `BUFOVF` reader - Buffer Overflow"] +pub struct BUFOVF_R(crate::FieldReader); +impl BUFOVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUFOVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUFOVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUFOVF` writer - Buffer Overflow"] +pub struct BUFOVF_W<'a> { + w: &'a mut W, +} +impl<'a> BUFOVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CTS` reader - Clear To Send"] +pub struct CTS_R(crate::FieldReader); +impl CTS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTS` writer - Clear To Send"] +pub struct CTS_W<'a> { + w: &'a mut W, +} +impl<'a> CTS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ISF` reader - Inconsistent Sync Field"] +pub struct ISF_R(crate::FieldReader); +impl ISF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ISF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ISF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ISF` writer - Inconsistent Sync Field"] +pub struct ISF_W<'a> { + w: &'a mut W, +} +impl<'a> ISF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `COLL` reader - Collision Detected"] +pub struct COLL_R(crate::FieldReader); +impl COLL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COLL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COLL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COLL` writer - Collision Detected"] +pub struct COLL_W<'a> { + w: &'a mut W, +} +impl<'a> COLL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `TXE` reader - Transmitter Empty"] +pub struct TXE_R(crate::FieldReader); +impl TXE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXE` writer - Transmitter Empty"] +pub struct TXE_W<'a> { + w: &'a mut W, +} +impl<'a> TXE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - Parity Error"] + #[inline(always)] + pub fn perr(&self) -> PERR_R { + PERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Frame Error"] + #[inline(always)] + pub fn ferr(&self) -> FERR_R { + FERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&self) -> BUFOVF_R { + BUFOVF_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Clear To Send"] + #[inline(always)] + pub fn cts(&self) -> CTS_R { + CTS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Inconsistent Sync Field"] + #[inline(always)] + pub fn isf(&self) -> ISF_R { + ISF_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Collision Detected"] + #[inline(always)] + pub fn coll(&self) -> COLL_R { + COLL_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Transmitter Empty"] + #[inline(always)] + pub fn txe(&self) -> TXE_R { + TXE_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Parity Error"] + #[inline(always)] + pub fn perr(&mut self) -> PERR_W { + PERR_W { w: self } + } + #[doc = "Bit 1 - Frame Error"] + #[inline(always)] + pub fn ferr(&mut self) -> FERR_W { + FERR_W { w: self } + } + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&mut self) -> BUFOVF_W { + BUFOVF_W { w: self } + } + #[doc = "Bit 3 - Clear To Send"] + #[inline(always)] + pub fn cts(&mut self) -> CTS_W { + CTS_W { w: self } + } + #[doc = "Bit 4 - Inconsistent Sync Field"] + #[inline(always)] + pub fn isf(&mut self) -> ISF_W { + ISF_W { w: self } + } + #[doc = "Bit 5 - Collision Detected"] + #[inline(always)] + pub fn coll(&mut self) -> COLL_W { + COLL_W { w: self } + } + #[doc = "Bit 6 - Transmitter Empty"] + #[inline(always)] + pub fn txe(&mut self) -> TXE_W { + TXE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sercom0/usart_ext/syncbusy.rs b/pac/atsamc21e/src/sercom0/usart_ext/syncbusy.rs new file mode 100644 index 000000000000..7c3b817bbb04 --- /dev/null +++ b/pac/atsamc21e/src/sercom0/usart_ext/syncbusy.rs @@ -0,0 +1,93 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - SERCOM Enable Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLB` reader - CTRLB Synchronization Busy"] +pub struct CTRLB_R(crate::FieldReader); +impl CTRLB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM Enable Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - CTRLB Synchronization Busy"] + #[inline(always)] + pub fn ctrlb(&self) -> CTRLB_R { + CTRLB_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +#[doc = "USART_EXT Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sercom0/usart_int.rs b/pac/atsamc21e/src/sercom0/usart_int.rs new file mode 100644 index 000000000000..157c8c4b4fdc --- /dev/null +++ b/pac/atsamc21e/src/sercom0/usart_int.rs @@ -0,0 +1,60 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "USART_INT Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "USART_INT Control B"] +pub mod ctrlb; +#[doc = "CTRLC register accessor: an alias for `Reg`"] +pub type CTRLC = crate::Reg; +#[doc = "USART_INT Control C"] +pub mod ctrlc; +#[doc = "BAUD register accessor: an alias for `Reg`"] +pub type BAUD = crate::Reg; +#[doc = "USART_INT Baud Rate"] +pub mod baud; +#[doc = "BAUD_FRAC_MODE register accessor: an alias for `Reg`"] +pub type BAUD_FRAC_MODE = crate::Reg; +#[doc = "USART_INT Baud Rate"] +pub mod baud_frac_mode; +#[doc = "BAUD_FRACFP_MODE register accessor: an alias for `Reg`"] +pub type BAUD_FRACFP_MODE = crate::Reg; +#[doc = "USART_INT Baud Rate"] +pub mod baud_fracfp_mode; +#[doc = "BAUD_USARTFP_MODE register accessor: an alias for `Reg`"] +pub type BAUD_USARTFP_MODE = crate::Reg; +#[doc = "USART_INT Baud Rate"] +pub mod baud_usartfp_mode; +#[doc = "RXPL register accessor: an alias for `Reg`"] +pub type RXPL = crate::Reg; +#[doc = "USART_INT Receive Pulse Length"] +pub mod rxpl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "USART_INT Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "USART_INT Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "USART_INT Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "USART_INT Status"] +pub mod status; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "USART_INT Synchronization Busy"] +pub mod syncbusy; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "USART_INT Data"] +pub mod data; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "USART_INT Debug Control"] +pub mod dbgctrl; diff --git a/pac/atsamc21e/src/sercom0/usart_int/baud.rs b/pac/atsamc21e/src/sercom0/usart_int/baud.rs new file mode 100644 index 000000000000..a82df20712b3 --- /dev/null +++ b/pac/atsamc21e/src/sercom0/usart_int/baud.rs @@ -0,0 +1,103 @@ +#[doc = "Register `BAUD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud](index.html) module"] +pub struct BAUD_SPEC; +impl crate::RegisterSpec for BAUD_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud::R](R) reader structure"] +impl crate::Readable for BAUD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud::W](W) writer structure"] +impl crate::Writable for BAUD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD to value 0"] +impl crate::Resettable for BAUD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sercom0/usart_int/baud_frac_mode.rs b/pac/atsamc21e/src/sercom0/usart_int/baud_frac_mode.rs new file mode 100644 index 000000000000..b9c7fa4c4b2a --- /dev/null +++ b/pac/atsamc21e/src/sercom0/usart_int/baud_frac_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `BAUD_FRAC_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD_FRAC_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1fff) | (value as u16 & 0x1fff); + self.w + } +} +#[doc = "Field `FP` reader - Fractional Part"] +pub struct FP_R(crate::FieldReader); +impl FP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FP` writer - Fractional Part"] +pub struct FP_W<'a> { + w: &'a mut W, +} +impl<'a> FP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 13)) | ((value as u16 & 0x07) << 13); + self.w + } +} +impl R { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new((self.bits & 0x1fff) as u16) + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&self) -> FP_R { + FP_R::new(((self.bits >> 13) & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&mut self) -> FP_W { + FP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud_frac_mode](index.html) module"] +pub struct BAUD_FRAC_MODE_SPEC; +impl crate::RegisterSpec for BAUD_FRAC_MODE_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud_frac_mode::R](R) reader structure"] +impl crate::Readable for BAUD_FRAC_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud_frac_mode::W](W) writer structure"] +impl crate::Writable for BAUD_FRAC_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD_FRAC_MODE to value 0"] +impl crate::Resettable for BAUD_FRAC_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sercom0/usart_int/baud_fracfp_mode.rs b/pac/atsamc21e/src/sercom0/usart_int/baud_fracfp_mode.rs new file mode 100644 index 000000000000..0671db99cc9d --- /dev/null +++ b/pac/atsamc21e/src/sercom0/usart_int/baud_fracfp_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `BAUD_FRACFP_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD_FRACFP_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1fff) | (value as u16 & 0x1fff); + self.w + } +} +#[doc = "Field `FP` reader - Fractional Part"] +pub struct FP_R(crate::FieldReader); +impl FP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FP` writer - Fractional Part"] +pub struct FP_W<'a> { + w: &'a mut W, +} +impl<'a> FP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 13)) | ((value as u16 & 0x07) << 13); + self.w + } +} +impl R { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new((self.bits & 0x1fff) as u16) + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&self) -> FP_R { + FP_R::new(((self.bits >> 13) & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&mut self) -> FP_W { + FP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud_fracfp_mode](index.html) module"] +pub struct BAUD_FRACFP_MODE_SPEC; +impl crate::RegisterSpec for BAUD_FRACFP_MODE_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud_fracfp_mode::R](R) reader structure"] +impl crate::Readable for BAUD_FRACFP_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud_fracfp_mode::W](W) writer structure"] +impl crate::Writable for BAUD_FRACFP_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD_FRACFP_MODE to value 0"] +impl crate::Resettable for BAUD_FRACFP_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sercom0/usart_int/baud_usartfp_mode.rs b/pac/atsamc21e/src/sercom0/usart_int/baud_usartfp_mode.rs new file mode 100644 index 000000000000..b49a7ef5b84c --- /dev/null +++ b/pac/atsamc21e/src/sercom0/usart_int/baud_usartfp_mode.rs @@ -0,0 +1,103 @@ +#[doc = "Register `BAUD_USARTFP_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD_USARTFP_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud_usartfp_mode](index.html) module"] +pub struct BAUD_USARTFP_MODE_SPEC; +impl crate::RegisterSpec for BAUD_USARTFP_MODE_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud_usartfp_mode::R](R) reader structure"] +impl crate::Readable for BAUD_USARTFP_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud_usartfp_mode::W](W) writer structure"] +impl crate::Writable for BAUD_USARTFP_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD_USARTFP_MODE to value 0"] +impl crate::Resettable for BAUD_USARTFP_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sercom0/usart_int/ctrla.rs b/pac/atsamc21e/src/sercom0/usart_int/ctrla.rs new file mode 100644 index 000000000000..19d10ecf8e8f --- /dev/null +++ b/pac/atsamc21e/src/sercom0/usart_int/ctrla.rs @@ -0,0 +1,1171 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: USART with external clock"] + USART_EXT_CLK = 0, + #[doc = "1: USART with internal clock"] + USART_INT_CLK = 1, + #[doc = "2: SPI in slave operation"] + SPI_SLAVE = 2, + #[doc = "3: SPI in master operation"] + SPI_MASTER = 3, + #[doc = "4: I2C slave operation"] + I2C_SLAVE = 4, + #[doc = "5: I2C master operation"] + I2C_MASTER = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::USART_EXT_CLK), + 1 => Some(MODE_A::USART_INT_CLK), + 2 => Some(MODE_A::SPI_SLAVE), + 3 => Some(MODE_A::SPI_MASTER), + 4 => Some(MODE_A::I2C_SLAVE), + 5 => Some(MODE_A::I2C_MASTER), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_EXT_CLK`"] + #[inline(always)] + pub fn is_usart_ext_clk(&self) -> bool { + **self == MODE_A::USART_EXT_CLK + } + #[doc = "Checks if the value of the field is `USART_INT_CLK`"] + #[inline(always)] + pub fn is_usart_int_clk(&self) -> bool { + **self == MODE_A::USART_INT_CLK + } + #[doc = "Checks if the value of the field is `SPI_SLAVE`"] + #[inline(always)] + pub fn is_spi_slave(&self) -> bool { + **self == MODE_A::SPI_SLAVE + } + #[doc = "Checks if the value of the field is `SPI_MASTER`"] + #[inline(always)] + pub fn is_spi_master(&self) -> bool { + **self == MODE_A::SPI_MASTER + } + #[doc = "Checks if the value of the field is `I2C_SLAVE`"] + #[inline(always)] + pub fn is_i2c_slave(&self) -> bool { + **self == MODE_A::I2C_SLAVE + } + #[doc = "Checks if the value of the field is `I2C_MASTER`"] + #[inline(always)] + pub fn is_i2c_master(&self) -> bool { + **self == MODE_A::I2C_MASTER + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART with external clock"] + #[inline(always)] + pub fn usart_ext_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_EXT_CLK) + } + #[doc = "USART with internal clock"] + #[inline(always)] + pub fn usart_int_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_INT_CLK) + } + #[doc = "SPI in slave operation"] + #[inline(always)] + pub fn spi_slave(self) -> &'a mut W { + self.variant(MODE_A::SPI_SLAVE) + } + #[doc = "SPI in master operation"] + #[inline(always)] + pub fn spi_master(self) -> &'a mut W { + self.variant(MODE_A::SPI_MASTER) + } + #[doc = "I2C slave operation"] + #[inline(always)] + pub fn i2c_slave(self) -> &'a mut W { + self.variant(MODE_A::I2C_SLAVE) + } + #[doc = "I2C master operation"] + #[inline(always)] + pub fn i2c_master(self) -> &'a mut W { + self.variant(MODE_A::I2C_MASTER) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 2)) | ((value as u32 & 0x07) << 2); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `IBON` reader - Immediate Buffer Overflow Notification"] +pub struct IBON_R(crate::FieldReader); +impl IBON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IBON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IBON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IBON` writer - Immediate Buffer Overflow Notification"] +pub struct IBON_W<'a> { + w: &'a mut W, +} +impl<'a> IBON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Sample\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SAMPR_A { + #[doc = "0: 16x over-sampling using arithmetic baudrate generation"] + _16X_ARITHMETIC = 0, + #[doc = "1: 16x over-sampling using fractional baudrate generation"] + _16X_FRACTIONAL = 1, + #[doc = "2: 8x over-sampling using arithmetic baudrate generation"] + _8X_ARITHMETIC = 2, + #[doc = "3: 8x over-sampling using fractional baudrate generation"] + _8X_FRACTIONAL = 3, + #[doc = "4: 3x over-sampling using arithmetic baudrate generation"] + _3X_ARITHMETIC = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SAMPR_A) -> Self { + variant as _ + } +} +#[doc = "Field `SAMPR` reader - Sample"] +pub struct SAMPR_R(crate::FieldReader); +impl SAMPR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SAMPR_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SAMPR_A::_16X_ARITHMETIC), + 1 => Some(SAMPR_A::_16X_FRACTIONAL), + 2 => Some(SAMPR_A::_8X_ARITHMETIC), + 3 => Some(SAMPR_A::_8X_FRACTIONAL), + 4 => Some(SAMPR_A::_3X_ARITHMETIC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_16X_ARITHMETIC`"] + #[inline(always)] + pub fn is_16x_arithmetic(&self) -> bool { + **self == SAMPR_A::_16X_ARITHMETIC + } + #[doc = "Checks if the value of the field is `_16X_FRACTIONAL`"] + #[inline(always)] + pub fn is_16x_fractional(&self) -> bool { + **self == SAMPR_A::_16X_FRACTIONAL + } + #[doc = "Checks if the value of the field is `_8X_ARITHMETIC`"] + #[inline(always)] + pub fn is_8x_arithmetic(&self) -> bool { + **self == SAMPR_A::_8X_ARITHMETIC + } + #[doc = "Checks if the value of the field is `_8X_FRACTIONAL`"] + #[inline(always)] + pub fn is_8x_fractional(&self) -> bool { + **self == SAMPR_A::_8X_FRACTIONAL + } + #[doc = "Checks if the value of the field is `_3X_ARITHMETIC`"] + #[inline(always)] + pub fn is_3x_arithmetic(&self) -> bool { + **self == SAMPR_A::_3X_ARITHMETIC + } +} +impl core::ops::Deref for SAMPR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SAMPR` writer - Sample"] +pub struct SAMPR_W<'a> { + w: &'a mut W, +} +impl<'a> SAMPR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SAMPR_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "16x over-sampling using arithmetic baudrate generation"] + #[inline(always)] + pub fn _16x_arithmetic(self) -> &'a mut W { + self.variant(SAMPR_A::_16X_ARITHMETIC) + } + #[doc = "16x over-sampling using fractional baudrate generation"] + #[inline(always)] + pub fn _16x_fractional(self) -> &'a mut W { + self.variant(SAMPR_A::_16X_FRACTIONAL) + } + #[doc = "8x over-sampling using arithmetic baudrate generation"] + #[inline(always)] + pub fn _8x_arithmetic(self) -> &'a mut W { + self.variant(SAMPR_A::_8X_ARITHMETIC) + } + #[doc = "8x over-sampling using fractional baudrate generation"] + #[inline(always)] + pub fn _8x_fractional(self) -> &'a mut W { + self.variant(SAMPR_A::_8X_FRACTIONAL) + } + #[doc = "3x over-sampling using arithmetic baudrate generation"] + #[inline(always)] + pub fn _3x_arithmetic(self) -> &'a mut W { + self.variant(SAMPR_A::_3X_ARITHMETIC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 13)) | ((value as u32 & 0x07) << 13); + self.w + } +} +#[doc = "Transmit Data Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum TXPO_A { + #[doc = "0: SERCOM PAD\\[0\\] +is used for data transmission"] + PAD0 = 0, + #[doc = "1: SERCOM PAD\\[2\\] +is used for data transmission"] + PAD2 = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: TXPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `TXPO` reader - Transmit Data Pinout"] +pub struct TXPO_R(crate::FieldReader); +impl TXPO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TXPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(TXPO_A::PAD0), + 1 => Some(TXPO_A::PAD2), + _ => None, + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == TXPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == TXPO_A::PAD2 + } +} +impl core::ops::Deref for TXPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXPO` writer - Transmit Data Pinout"] +pub struct TXPO_W<'a> { + w: &'a mut W, +} +impl<'a> TXPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TXPO_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "SERCOM PAD\\[0\\] +is used for data transmission"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(TXPO_A::PAD0) + } + #[doc = "SERCOM PAD\\[2\\] +is used for data transmission"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(TXPO_A::PAD2) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Receive Data Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum RXPO_A { + #[doc = "0: SERCOM PAD\\[0\\] +is used for data reception"] + PAD0 = 0, + #[doc = "1: SERCOM PAD\\[1\\] +is used for data reception"] + PAD1 = 1, + #[doc = "2: SERCOM PAD\\[2\\] +is used for data reception"] + PAD2 = 2, + #[doc = "3: SERCOM PAD\\[3\\] +is used for data reception"] + PAD3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RXPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `RXPO` reader - Receive Data Pinout"] +pub struct RXPO_R(crate::FieldReader); +impl RXPO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RXPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RXPO_A { + match self.bits { + 0 => RXPO_A::PAD0, + 1 => RXPO_A::PAD1, + 2 => RXPO_A::PAD2, + 3 => RXPO_A::PAD3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == RXPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD1`"] + #[inline(always)] + pub fn is_pad1(&self) -> bool { + **self == RXPO_A::PAD1 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == RXPO_A::PAD2 + } + #[doc = "Checks if the value of the field is `PAD3`"] + #[inline(always)] + pub fn is_pad3(&self) -> bool { + **self == RXPO_A::PAD3 + } +} +impl core::ops::Deref for RXPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXPO` writer - Receive Data Pinout"] +pub struct RXPO_W<'a> { + w: &'a mut W, +} +impl<'a> RXPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RXPO_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "SERCOM PAD\\[0\\] +is used for data reception"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(RXPO_A::PAD0) + } + #[doc = "SERCOM PAD\\[1\\] +is used for data reception"] + #[inline(always)] + pub fn pad1(self) -> &'a mut W { + self.variant(RXPO_A::PAD1) + } + #[doc = "SERCOM PAD\\[2\\] +is used for data reception"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(RXPO_A::PAD2) + } + #[doc = "SERCOM PAD\\[3\\] +is used for data reception"] + #[inline(always)] + pub fn pad3(self) -> &'a mut W { + self.variant(RXPO_A::PAD3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 20)) | ((value as u32 & 0x03) << 20); + self.w + } +} +#[doc = "Field `SAMPA` reader - Sample Adjustment"] +pub struct SAMPA_R(crate::FieldReader); +impl SAMPA_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SAMPA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SAMPA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SAMPA` writer - Sample Adjustment"] +pub struct SAMPA_W<'a> { + w: &'a mut W, +} +impl<'a> SAMPA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 22)) | ((value as u32 & 0x03) << 22); + self.w + } +} +#[doc = "Frame Format\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FORM_A { + #[doc = "0: USART frame"] + USART_FRAME_NO_PARITY = 0, + #[doc = "1: USART frame with parity"] + USART_FRAME_WITH_PARITY = 1, + #[doc = "2: LIN Master - Break and sync generation"] + USART_FRAME_LIN_MASTER_MODE = 2, + #[doc = "4: Auto-baud - break detection and auto-baud"] + USART_FRAME_AUTO_BAUD_NO_PARITY = 4, + #[doc = "5: Auto-baud - break detection and auto-baud with parity"] + USART_FRAME_AUTO_BAUD_WITH_PARITY = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FORM_A) -> Self { + variant as _ + } +} +#[doc = "Field `FORM` reader - Frame Format"] +pub struct FORM_R(crate::FieldReader); +impl FORM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FORM_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(FORM_A::USART_FRAME_NO_PARITY), + 1 => Some(FORM_A::USART_FRAME_WITH_PARITY), + 2 => Some(FORM_A::USART_FRAME_LIN_MASTER_MODE), + 4 => Some(FORM_A::USART_FRAME_AUTO_BAUD_NO_PARITY), + 5 => Some(FORM_A::USART_FRAME_AUTO_BAUD_WITH_PARITY), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_FRAME_NO_PARITY`"] + #[inline(always)] + pub fn is_usart_frame_no_parity(&self) -> bool { + **self == FORM_A::USART_FRAME_NO_PARITY + } + #[doc = "Checks if the value of the field is `USART_FRAME_WITH_PARITY`"] + #[inline(always)] + pub fn is_usart_frame_with_parity(&self) -> bool { + **self == FORM_A::USART_FRAME_WITH_PARITY + } + #[doc = "Checks if the value of the field is `USART_FRAME_LIN_MASTER_MODE`"] + #[inline(always)] + pub fn is_usart_frame_lin_master_mode(&self) -> bool { + **self == FORM_A::USART_FRAME_LIN_MASTER_MODE + } + #[doc = "Checks if the value of the field is `USART_FRAME_AUTO_BAUD_NO_PARITY`"] + #[inline(always)] + pub fn is_usart_frame_auto_baud_no_parity(&self) -> bool { + **self == FORM_A::USART_FRAME_AUTO_BAUD_NO_PARITY + } + #[doc = "Checks if the value of the field is `USART_FRAME_AUTO_BAUD_WITH_PARITY`"] + #[inline(always)] + pub fn is_usart_frame_auto_baud_with_parity(&self) -> bool { + **self == FORM_A::USART_FRAME_AUTO_BAUD_WITH_PARITY + } +} +impl core::ops::Deref for FORM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FORM` writer - Frame Format"] +pub struct FORM_W<'a> { + w: &'a mut W, +} +impl<'a> FORM_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FORM_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART frame"] + #[inline(always)] + pub fn usart_frame_no_parity(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_NO_PARITY) + } + #[doc = "USART frame with parity"] + #[inline(always)] + pub fn usart_frame_with_parity(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_WITH_PARITY) + } + #[doc = "LIN Master - Break and sync generation"] + #[inline(always)] + pub fn usart_frame_lin_master_mode(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_LIN_MASTER_MODE) + } + #[doc = "Auto-baud - break detection and auto-baud"] + #[inline(always)] + pub fn usart_frame_auto_baud_no_parity(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_AUTO_BAUD_NO_PARITY) + } + #[doc = "Auto-baud - break detection and auto-baud with parity"] + #[inline(always)] + pub fn usart_frame_auto_baud_with_parity(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_AUTO_BAUD_WITH_PARITY) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Communication Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CMODE_A { + #[doc = "0: Asynchronous Communication"] + ASYNC = 0, + #[doc = "1: Synchronous Communication"] + SYNC = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CMODE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CMODE` reader - Communication Mode"] +pub struct CMODE_R(crate::FieldReader); +impl CMODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CMODE_A { + match self.bits { + false => CMODE_A::ASYNC, + true => CMODE_A::SYNC, + } + } + #[doc = "Checks if the value of the field is `ASYNC`"] + #[inline(always)] + pub fn is_async(&self) -> bool { + **self == CMODE_A::ASYNC + } + #[doc = "Checks if the value of the field is `SYNC`"] + #[inline(always)] + pub fn is_sync(&self) -> bool { + **self == CMODE_A::SYNC + } +} +impl core::ops::Deref for CMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMODE` writer - Communication Mode"] +pub struct CMODE_W<'a> { + w: &'a mut W, +} +impl<'a> CMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMODE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Asynchronous Communication"] + #[inline(always)] + pub fn async_(self) -> &'a mut W { + self.variant(CMODE_A::ASYNC) + } + #[doc = "Synchronous Communication"] + #[inline(always)] + pub fn sync(self) -> &'a mut W { + self.variant(CMODE_A::SYNC) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Clock Polarity\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CPOL_A { + #[doc = "0: TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge"] + IDLE_LOW = 0, + #[doc = "1: TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge"] + IDLE_HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CPOL_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CPOL` reader - Clock Polarity"] +pub struct CPOL_R(crate::FieldReader); +impl CPOL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPOL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CPOL_A { + match self.bits { + false => CPOL_A::IDLE_LOW, + true => CPOL_A::IDLE_HIGH, + } + } + #[doc = "Checks if the value of the field is `IDLE_LOW`"] + #[inline(always)] + pub fn is_idle_low(&self) -> bool { + **self == CPOL_A::IDLE_LOW + } + #[doc = "Checks if the value of the field is `IDLE_HIGH`"] + #[inline(always)] + pub fn is_idle_high(&self) -> bool { + **self == CPOL_A::IDLE_HIGH + } +} +impl core::ops::Deref for CPOL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPOL` writer - Clock Polarity"] +pub struct CPOL_W<'a> { + w: &'a mut W, +} +impl<'a> CPOL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CPOL_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge"] + #[inline(always)] + pub fn idle_low(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_LOW) + } + #[doc = "TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge"] + #[inline(always)] + pub fn idle_high(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_HIGH) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29); + self.w + } +} +#[doc = "Data Order\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum DORD_A { + #[doc = "0: MSB is transmitted first"] + MSB = 0, + #[doc = "1: LSB is transmitted first"] + LSB = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DORD_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DORD` reader - Data Order"] +pub struct DORD_R(crate::FieldReader); +impl DORD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DORD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DORD_A { + match self.bits { + false => DORD_A::MSB, + true => DORD_A::LSB, + } + } + #[doc = "Checks if the value of the field is `MSB`"] + #[inline(always)] + pub fn is_msb(&self) -> bool { + **self == DORD_A::MSB + } + #[doc = "Checks if the value of the field is `LSB`"] + #[inline(always)] + pub fn is_lsb(&self) -> bool { + **self == DORD_A::LSB + } +} +impl core::ops::Deref for DORD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DORD` writer - Data Order"] +pub struct DORD_W<'a> { + w: &'a mut W, +} +impl<'a> DORD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DORD_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "MSB is transmitted first"] + #[inline(always)] + pub fn msb(self) -> &'a mut W { + self.variant(DORD_A::MSB) + } + #[doc = "LSB is transmitted first"] + #[inline(always)] + pub fn lsb(self) -> &'a mut W { + self.variant(DORD_A::LSB) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x07) as u8) + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&self) -> IBON_R { + IBON_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bits 13:15 - Sample"] + #[inline(always)] + pub fn sampr(&self) -> SAMPR_R { + SAMPR_R::new(((self.bits >> 13) & 0x07) as u8) + } + #[doc = "Bits 16:17 - Transmit Data Pinout"] + #[inline(always)] + pub fn txpo(&self) -> TXPO_R { + TXPO_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bits 20:21 - Receive Data Pinout"] + #[inline(always)] + pub fn rxpo(&self) -> RXPO_R { + RXPO_R::new(((self.bits >> 20) & 0x03) as u8) + } + #[doc = "Bits 22:23 - Sample Adjustment"] + #[inline(always)] + pub fn sampa(&self) -> SAMPA_R { + SAMPA_R::new(((self.bits >> 22) & 0x03) as u8) + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&self) -> FORM_R { + FORM_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 28 - Communication Mode"] + #[inline(always)] + pub fn cmode(&self) -> CMODE_R { + CMODE_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&self) -> CPOL_R { + CPOL_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&self) -> DORD_R { + DORD_R::new(((self.bits >> 30) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&mut self) -> IBON_W { + IBON_W { w: self } + } + #[doc = "Bits 13:15 - Sample"] + #[inline(always)] + pub fn sampr(&mut self) -> SAMPR_W { + SAMPR_W { w: self } + } + #[doc = "Bits 16:17 - Transmit Data Pinout"] + #[inline(always)] + pub fn txpo(&mut self) -> TXPO_W { + TXPO_W { w: self } + } + #[doc = "Bits 20:21 - Receive Data Pinout"] + #[inline(always)] + pub fn rxpo(&mut self) -> RXPO_W { + RXPO_W { w: self } + } + #[doc = "Bits 22:23 - Sample Adjustment"] + #[inline(always)] + pub fn sampa(&mut self) -> SAMPA_W { + SAMPA_W { w: self } + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&mut self) -> FORM_W { + FORM_W { w: self } + } + #[doc = "Bit 28 - Communication Mode"] + #[inline(always)] + pub fn cmode(&mut self) -> CMODE_W { + CMODE_W { w: self } + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&mut self) -> CPOL_W { + CPOL_W { w: self } + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&mut self) -> DORD_W { + DORD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sercom0/usart_int/ctrlb.rs b/pac/atsamc21e/src/sercom0/usart_int/ctrlb.rs new file mode 100644 index 000000000000..d556e0c3cfc2 --- /dev/null +++ b/pac/atsamc21e/src/sercom0/usart_int/ctrlb.rs @@ -0,0 +1,651 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Character Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CHSIZE_A { + #[doc = "0: 8 Bits"] + _8_BIT = 0, + #[doc = "1: 9 Bits"] + _9_BIT = 1, + #[doc = "5: 5 Bits"] + _5_BIT = 5, + #[doc = "6: 6 Bits"] + _6_BIT = 6, + #[doc = "7: 7 Bits"] + _7_BIT = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CHSIZE_A) -> Self { + variant as _ + } +} +#[doc = "Field `CHSIZE` reader - Character Size"] +pub struct CHSIZE_R(crate::FieldReader); +impl CHSIZE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CHSIZE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CHSIZE_A::_8_BIT), + 1 => Some(CHSIZE_A::_9_BIT), + 5 => Some(CHSIZE_A::_5_BIT), + 6 => Some(CHSIZE_A::_6_BIT), + 7 => Some(CHSIZE_A::_7_BIT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_8_BIT`"] + #[inline(always)] + pub fn is_8_bit(&self) -> bool { + **self == CHSIZE_A::_8_BIT + } + #[doc = "Checks if the value of the field is `_9_BIT`"] + #[inline(always)] + pub fn is_9_bit(&self) -> bool { + **self == CHSIZE_A::_9_BIT + } + #[doc = "Checks if the value of the field is `_5_BIT`"] + #[inline(always)] + pub fn is_5_bit(&self) -> bool { + **self == CHSIZE_A::_5_BIT + } + #[doc = "Checks if the value of the field is `_6_BIT`"] + #[inline(always)] + pub fn is_6_bit(&self) -> bool { + **self == CHSIZE_A::_6_BIT + } + #[doc = "Checks if the value of the field is `_7_BIT`"] + #[inline(always)] + pub fn is_7_bit(&self) -> bool { + **self == CHSIZE_A::_7_BIT + } +} +impl core::ops::Deref for CHSIZE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHSIZE` writer - Character Size"] +pub struct CHSIZE_W<'a> { + w: &'a mut W, +} +impl<'a> CHSIZE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CHSIZE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8 Bits"] + #[inline(always)] + pub fn _8_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_8_BIT) + } + #[doc = "9 Bits"] + #[inline(always)] + pub fn _9_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_9_BIT) + } + #[doc = "5 Bits"] + #[inline(always)] + pub fn _5_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_5_BIT) + } + #[doc = "6 Bits"] + #[inline(always)] + pub fn _6_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_6_BIT) + } + #[doc = "7 Bits"] + #[inline(always)] + pub fn _7_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_7_BIT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Stop Bit Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SBMODE_A { + #[doc = "0: One Stop Bit"] + _1_BIT = 0, + #[doc = "1: Two Stop Bits"] + _2_BIT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SBMODE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SBMODE` reader - Stop Bit Mode"] +pub struct SBMODE_R(crate::FieldReader); +impl SBMODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SBMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SBMODE_A { + match self.bits { + false => SBMODE_A::_1_BIT, + true => SBMODE_A::_2_BIT, + } + } + #[doc = "Checks if the value of the field is `_1_BIT`"] + #[inline(always)] + pub fn is_1_bit(&self) -> bool { + **self == SBMODE_A::_1_BIT + } + #[doc = "Checks if the value of the field is `_2_BIT`"] + #[inline(always)] + pub fn is_2_bit(&self) -> bool { + **self == SBMODE_A::_2_BIT + } +} +impl core::ops::Deref for SBMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SBMODE` writer - Stop Bit Mode"] +pub struct SBMODE_W<'a> { + w: &'a mut W, +} +impl<'a> SBMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SBMODE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "One Stop Bit"] + #[inline(always)] + pub fn _1_bit(self) -> &'a mut W { + self.variant(SBMODE_A::_1_BIT) + } + #[doc = "Two Stop Bits"] + #[inline(always)] + pub fn _2_bit(self) -> &'a mut W { + self.variant(SBMODE_A::_2_BIT) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `COLDEN` reader - Collision Detection Enable"] +pub struct COLDEN_R(crate::FieldReader); +impl COLDEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COLDEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COLDEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COLDEN` writer - Collision Detection Enable"] +pub struct COLDEN_W<'a> { + w: &'a mut W, +} +impl<'a> COLDEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `SFDE` reader - Start of Frame Detection Enable"] +pub struct SFDE_R(crate::FieldReader); +impl SFDE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SFDE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SFDE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SFDE` writer - Start of Frame Detection Enable"] +pub struct SFDE_W<'a> { + w: &'a mut W, +} +impl<'a> SFDE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `ENC` reader - Encoding Format"] +pub struct ENC_R(crate::FieldReader); +impl ENC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENC` writer - Encoding Format"] +pub struct ENC_W<'a> { + w: &'a mut W, +} +impl<'a> ENC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Parity Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PMODE_A { + #[doc = "0: Even Parity"] + EVEN = 0, + #[doc = "1: Odd Parity"] + ODD = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PMODE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PMODE` reader - Parity Mode"] +pub struct PMODE_R(crate::FieldReader); +impl PMODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PMODE_A { + match self.bits { + false => PMODE_A::EVEN, + true => PMODE_A::ODD, + } + } + #[doc = "Checks if the value of the field is `EVEN`"] + #[inline(always)] + pub fn is_even(&self) -> bool { + **self == PMODE_A::EVEN + } + #[doc = "Checks if the value of the field is `ODD`"] + #[inline(always)] + pub fn is_odd(&self) -> bool { + **self == PMODE_A::ODD + } +} +impl core::ops::Deref for PMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PMODE` writer - Parity Mode"] +pub struct PMODE_W<'a> { + w: &'a mut W, +} +impl<'a> PMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PMODE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Even Parity"] + #[inline(always)] + pub fn even(self) -> &'a mut W { + self.variant(PMODE_A::EVEN) + } + #[doc = "Odd Parity"] + #[inline(always)] + pub fn odd(self) -> &'a mut W { + self.variant(PMODE_A::ODD) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `TXEN` reader - Transmitter Enable"] +pub struct TXEN_R(crate::FieldReader); +impl TXEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXEN` writer - Transmitter Enable"] +pub struct TXEN_W<'a> { + w: &'a mut W, +} +impl<'a> TXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `RXEN` reader - Receiver Enable"] +pub struct RXEN_R(crate::FieldReader); +impl RXEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXEN` writer - Receiver Enable"] +pub struct RXEN_W<'a> { + w: &'a mut W, +} +impl<'a> RXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `LINCMD` reader - LIN Command"] +pub struct LINCMD_R(crate::FieldReader); +impl LINCMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LINCMD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LINCMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LINCMD` writer - LIN Command"] +pub struct LINCMD_W<'a> { + w: &'a mut W, +} +impl<'a> LINCMD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 24)) | ((value as u32 & 0x03) << 24); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&self) -> CHSIZE_R { + CHSIZE_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 6 - Stop Bit Mode"] + #[inline(always)] + pub fn sbmode(&self) -> SBMODE_R { + SBMODE_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 8 - Collision Detection Enable"] + #[inline(always)] + pub fn colden(&self) -> COLDEN_R { + COLDEN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Start of Frame Detection Enable"] + #[inline(always)] + pub fn sfde(&self) -> SFDE_R { + SFDE_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Encoding Format"] + #[inline(always)] + pub fn enc(&self) -> ENC_R { + ENC_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 13 - Parity Mode"] + #[inline(always)] + pub fn pmode(&self) -> PMODE_R { + PMODE_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 16 - Transmitter Enable"] + #[inline(always)] + pub fn txen(&self) -> TXEN_R { + TXEN_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&self) -> RXEN_R { + RXEN_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bits 24:25 - LIN Command"] + #[inline(always)] + pub fn lincmd(&self) -> LINCMD_R { + LINCMD_R::new(((self.bits >> 24) & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&mut self) -> CHSIZE_W { + CHSIZE_W { w: self } + } + #[doc = "Bit 6 - Stop Bit Mode"] + #[inline(always)] + pub fn sbmode(&mut self) -> SBMODE_W { + SBMODE_W { w: self } + } + #[doc = "Bit 8 - Collision Detection Enable"] + #[inline(always)] + pub fn colden(&mut self) -> COLDEN_W { + COLDEN_W { w: self } + } + #[doc = "Bit 9 - Start of Frame Detection Enable"] + #[inline(always)] + pub fn sfde(&mut self) -> SFDE_W { + SFDE_W { w: self } + } + #[doc = "Bit 10 - Encoding Format"] + #[inline(always)] + pub fn enc(&mut self) -> ENC_W { + ENC_W { w: self } + } + #[doc = "Bit 13 - Parity Mode"] + #[inline(always)] + pub fn pmode(&mut self) -> PMODE_W { + PMODE_W { w: self } + } + #[doc = "Bit 16 - Transmitter Enable"] + #[inline(always)] + pub fn txen(&mut self) -> TXEN_W { + TXEN_W { w: self } + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&mut self) -> RXEN_W { + RXEN_W { w: self } + } + #[doc = "Bits 24:25 - LIN Command"] + #[inline(always)] + pub fn lincmd(&mut self) -> LINCMD_W { + LINCMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sercom0/usart_int/ctrlc.rs b/pac/atsamc21e/src/sercom0/usart_int/ctrlc.rs new file mode 100644 index 000000000000..e2182cc7f768 --- /dev/null +++ b/pac/atsamc21e/src/sercom0/usart_int/ctrlc.rs @@ -0,0 +1,177 @@ +#[doc = "Register `CTRLC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `GTIME` reader - RS485 Guard Time"] +pub struct GTIME_R(crate::FieldReader); +impl GTIME_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + GTIME_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GTIME_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GTIME` writer - RS485 Guard Time"] +pub struct GTIME_W<'a> { + w: &'a mut W, +} +impl<'a> GTIME_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Field `BRKLEN` reader - LIN Master Break Length"] +pub struct BRKLEN_R(crate::FieldReader); +impl BRKLEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BRKLEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BRKLEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BRKLEN` writer - LIN Master Break Length"] +pub struct BRKLEN_W<'a> { + w: &'a mut W, +} +impl<'a> BRKLEN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 8)) | ((value as u32 & 0x03) << 8); + self.w + } +} +#[doc = "Field `HDRDLY` reader - LIN Master Header Delay"] +pub struct HDRDLY_R(crate::FieldReader); +impl HDRDLY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + HDRDLY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HDRDLY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HDRDLY` writer - LIN Master Header Delay"] +pub struct HDRDLY_W<'a> { + w: &'a mut W, +} +impl<'a> HDRDLY_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 10)) | ((value as u32 & 0x03) << 10); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - RS485 Guard Time"] + #[inline(always)] + pub fn gtime(&self) -> GTIME_R { + GTIME_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bits 8:9 - LIN Master Break Length"] + #[inline(always)] + pub fn brklen(&self) -> BRKLEN_R { + BRKLEN_R::new(((self.bits >> 8) & 0x03) as u8) + } + #[doc = "Bits 10:11 - LIN Master Header Delay"] + #[inline(always)] + pub fn hdrdly(&self) -> HDRDLY_R { + HDRDLY_R::new(((self.bits >> 10) & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - RS485 Guard Time"] + #[inline(always)] + pub fn gtime(&mut self) -> GTIME_W { + GTIME_W { w: self } + } + #[doc = "Bits 8:9 - LIN Master Break Length"] + #[inline(always)] + pub fn brklen(&mut self) -> BRKLEN_W { + BRKLEN_W { w: self } + } + #[doc = "Bits 10:11 - LIN Master Header Delay"] + #[inline(always)] + pub fn hdrdly(&mut self) -> HDRDLY_W { + HDRDLY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Control C\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlc](index.html) module"] +pub struct CTRLC_SPEC; +impl crate::RegisterSpec for CTRLC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlc::R](R) reader structure"] +impl crate::Readable for CTRLC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlc::W](W) writer structure"] +impl crate::Writable for CTRLC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLC to value 0"] +impl crate::Resettable for CTRLC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sercom0/usart_int/data.rs b/pac/atsamc21e/src/sercom0/usart_int/data.rs new file mode 100644 index 000000000000..19d74c337d44 --- /dev/null +++ b/pac/atsamc21e/src/sercom0/usart_int/data.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data Value"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data Value"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01ff) | (value as u16 & 0x01ff); + self.w + } +} +impl R { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new((self.bits & 0x01ff) as u16) + } +} +impl W { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sercom0/usart_int/dbgctrl.rs b/pac/atsamc21e/src/sercom0/usart_int/dbgctrl.rs new file mode 100644 index 000000000000..0ac5b9c7b902 --- /dev/null +++ b/pac/atsamc21e/src/sercom0/usart_int/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGSTOP` reader - Debug Mode"] +pub struct DBGSTOP_R(crate::FieldReader); +impl DBGSTOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGSTOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGSTOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGSTOP` writer - Debug Mode"] +pub struct DBGSTOP_W<'a> { + w: &'a mut W, +} +impl<'a> DBGSTOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&self) -> DBGSTOP_R { + DBGSTOP_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&mut self) -> DBGSTOP_W { + DBGSTOP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sercom0/usart_int/intenclr.rs b/pac/atsamc21e/src/sercom0/usart_int/intenclr.rs new file mode 100644 index 000000000000..5ad23ad15636 --- /dev/null +++ b/pac/atsamc21e/src/sercom0/usart_int/intenclr.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Disable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Disable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Disable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Disable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Disable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Disable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RXS` reader - Receive Start Interrupt Disable"] +pub struct RXS_R(crate::FieldReader); +impl RXS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXS` writer - Receive Start Interrupt Disable"] +pub struct RXS_W<'a> { + w: &'a mut W, +} +impl<'a> RXS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CTSIC` reader - Clear To Send Input Change Interrupt Disable"] +pub struct CTSIC_R(crate::FieldReader); +impl CTSIC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTSIC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTSIC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTSIC` writer - Clear To Send Input Change Interrupt Disable"] +pub struct CTSIC_W<'a> { + w: &'a mut W, +} +impl<'a> CTSIC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RXBRK` reader - Break Received Interrupt Disable"] +pub struct RXBRK_R(crate::FieldReader); +impl RXBRK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXBRK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXBRK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXBRK` writer - Break Received Interrupt Disable"] +pub struct RXBRK_W<'a> { + w: &'a mut W, +} +impl<'a> RXBRK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Disable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Disable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Receive Start Interrupt Disable"] + #[inline(always)] + pub fn rxs(&self) -> RXS_R { + RXS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Disable"] + #[inline(always)] + pub fn ctsic(&self) -> CTSIC_R { + CTSIC_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Break Received Interrupt Disable"] + #[inline(always)] + pub fn rxbrk(&self) -> RXBRK_R { + RXBRK_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Receive Start Interrupt Disable"] + #[inline(always)] + pub fn rxs(&mut self) -> RXS_W { + RXS_W { w: self } + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Disable"] + #[inline(always)] + pub fn ctsic(&mut self) -> CTSIC_W { + CTSIC_W { w: self } + } + #[doc = "Bit 5 - Break Received Interrupt Disable"] + #[inline(always)] + pub fn rxbrk(&mut self) -> RXBRK_W { + RXBRK_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sercom0/usart_int/intenset.rs b/pac/atsamc21e/src/sercom0/usart_int/intenset.rs new file mode 100644 index 000000000000..457f440e13e9 --- /dev/null +++ b/pac/atsamc21e/src/sercom0/usart_int/intenset.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Enable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Enable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Enable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Enable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Enable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Enable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RXS` reader - Receive Start Interrupt Enable"] +pub struct RXS_R(crate::FieldReader); +impl RXS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXS` writer - Receive Start Interrupt Enable"] +pub struct RXS_W<'a> { + w: &'a mut W, +} +impl<'a> RXS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CTSIC` reader - Clear To Send Input Change Interrupt Enable"] +pub struct CTSIC_R(crate::FieldReader); +impl CTSIC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTSIC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTSIC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTSIC` writer - Clear To Send Input Change Interrupt Enable"] +pub struct CTSIC_W<'a> { + w: &'a mut W, +} +impl<'a> CTSIC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RXBRK` reader - Break Received Interrupt Enable"] +pub struct RXBRK_R(crate::FieldReader); +impl RXBRK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXBRK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXBRK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXBRK` writer - Break Received Interrupt Enable"] +pub struct RXBRK_W<'a> { + w: &'a mut W, +} +impl<'a> RXBRK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Receive Start Interrupt Enable"] + #[inline(always)] + pub fn rxs(&self) -> RXS_R { + RXS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Enable"] + #[inline(always)] + pub fn ctsic(&self) -> CTSIC_R { + CTSIC_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Break Received Interrupt Enable"] + #[inline(always)] + pub fn rxbrk(&self) -> RXBRK_R { + RXBRK_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Receive Start Interrupt Enable"] + #[inline(always)] + pub fn rxs(&mut self) -> RXS_W { + RXS_W { w: self } + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Enable"] + #[inline(always)] + pub fn ctsic(&mut self) -> CTSIC_W { + CTSIC_W { w: self } + } + #[doc = "Bit 5 - Break Received Interrupt Enable"] + #[inline(always)] + pub fn rxbrk(&mut self) -> RXBRK_W { + RXBRK_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sercom0/usart_int/intflag.rs b/pac/atsamc21e/src/sercom0/usart_int/intflag.rs new file mode 100644 index 000000000000..a6a26321b8c4 --- /dev/null +++ b/pac/atsamc21e/src/sercom0/usart_int/intflag.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RXS` reader - Receive Start Interrupt"] +pub struct RXS_R(crate::FieldReader); +impl RXS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXS` writer - Receive Start Interrupt"] +pub struct RXS_W<'a> { + w: &'a mut W, +} +impl<'a> RXS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CTSIC` reader - Clear To Send Input Change Interrupt"] +pub struct CTSIC_R(crate::FieldReader); +impl CTSIC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTSIC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTSIC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTSIC` writer - Clear To Send Input Change Interrupt"] +pub struct CTSIC_W<'a> { + w: &'a mut W, +} +impl<'a> CTSIC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RXBRK` reader - Break Received Interrupt"] +pub struct RXBRK_R(crate::FieldReader); +impl RXBRK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXBRK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXBRK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXBRK` writer - Break Received Interrupt"] +pub struct RXBRK_W<'a> { + w: &'a mut W, +} +impl<'a> RXBRK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Receive Start Interrupt"] + #[inline(always)] + pub fn rxs(&self) -> RXS_R { + RXS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt"] + #[inline(always)] + pub fn ctsic(&self) -> CTSIC_R { + CTSIC_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Break Received Interrupt"] + #[inline(always)] + pub fn rxbrk(&self) -> RXBRK_R { + RXBRK_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Receive Start Interrupt"] + #[inline(always)] + pub fn rxs(&mut self) -> RXS_W { + RXS_W { w: self } + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt"] + #[inline(always)] + pub fn ctsic(&mut self) -> CTSIC_W { + CTSIC_W { w: self } + } + #[doc = "Bit 5 - Break Received Interrupt"] + #[inline(always)] + pub fn rxbrk(&mut self) -> RXBRK_W { + RXBRK_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sercom0/usart_int/rxpl.rs b/pac/atsamc21e/src/sercom0/usart_int/rxpl.rs new file mode 100644 index 000000000000..324cbac371c1 --- /dev/null +++ b/pac/atsamc21e/src/sercom0/usart_int/rxpl.rs @@ -0,0 +1,103 @@ +#[doc = "Register `RXPL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RXPL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RXPL` reader - Receive Pulse Length"] +pub struct RXPL_R(crate::FieldReader); +impl RXPL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RXPL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXPL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXPL` writer - Receive Pulse Length"] +pub struct RXPL_W<'a> { + w: &'a mut W, +} +impl<'a> RXPL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Receive Pulse Length"] + #[inline(always)] + pub fn rxpl(&self) -> RXPL_R { + RXPL_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Receive Pulse Length"] + #[inline(always)] + pub fn rxpl(&mut self) -> RXPL_W { + RXPL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Receive Pulse Length\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxpl](index.html) module"] +pub struct RXPL_SPEC; +impl crate::RegisterSpec for RXPL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [rxpl::R](R) reader structure"] +impl crate::Readable for RXPL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rxpl::W](W) writer structure"] +impl crate::Writable for RXPL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RXPL to value 0"] +impl crate::Resettable for RXPL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sercom0/usart_int/status.rs b/pac/atsamc21e/src/sercom0/usart_int/status.rs new file mode 100644 index 000000000000..1a92018a359b --- /dev/null +++ b/pac/atsamc21e/src/sercom0/usart_int/status.rs @@ -0,0 +1,395 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PERR` reader - Parity Error"] +pub struct PERR_R(crate::FieldReader); +impl PERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERR` writer - Parity Error"] +pub struct PERR_W<'a> { + w: &'a mut W, +} +impl<'a> PERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `FERR` reader - Frame Error"] +pub struct FERR_R(crate::FieldReader); +impl FERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FERR` writer - Frame Error"] +pub struct FERR_W<'a> { + w: &'a mut W, +} +impl<'a> FERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `BUFOVF` reader - Buffer Overflow"] +pub struct BUFOVF_R(crate::FieldReader); +impl BUFOVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUFOVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUFOVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUFOVF` writer - Buffer Overflow"] +pub struct BUFOVF_W<'a> { + w: &'a mut W, +} +impl<'a> BUFOVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CTS` reader - Clear To Send"] +pub struct CTS_R(crate::FieldReader); +impl CTS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTS` writer - Clear To Send"] +pub struct CTS_W<'a> { + w: &'a mut W, +} +impl<'a> CTS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ISF` reader - Inconsistent Sync Field"] +pub struct ISF_R(crate::FieldReader); +impl ISF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ISF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ISF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ISF` writer - Inconsistent Sync Field"] +pub struct ISF_W<'a> { + w: &'a mut W, +} +impl<'a> ISF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `COLL` reader - Collision Detected"] +pub struct COLL_R(crate::FieldReader); +impl COLL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COLL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COLL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COLL` writer - Collision Detected"] +pub struct COLL_W<'a> { + w: &'a mut W, +} +impl<'a> COLL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `TXE` reader - Transmitter Empty"] +pub struct TXE_R(crate::FieldReader); +impl TXE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXE` writer - Transmitter Empty"] +pub struct TXE_W<'a> { + w: &'a mut W, +} +impl<'a> TXE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - Parity Error"] + #[inline(always)] + pub fn perr(&self) -> PERR_R { + PERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Frame Error"] + #[inline(always)] + pub fn ferr(&self) -> FERR_R { + FERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&self) -> BUFOVF_R { + BUFOVF_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Clear To Send"] + #[inline(always)] + pub fn cts(&self) -> CTS_R { + CTS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Inconsistent Sync Field"] + #[inline(always)] + pub fn isf(&self) -> ISF_R { + ISF_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Collision Detected"] + #[inline(always)] + pub fn coll(&self) -> COLL_R { + COLL_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Transmitter Empty"] + #[inline(always)] + pub fn txe(&self) -> TXE_R { + TXE_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Parity Error"] + #[inline(always)] + pub fn perr(&mut self) -> PERR_W { + PERR_W { w: self } + } + #[doc = "Bit 1 - Frame Error"] + #[inline(always)] + pub fn ferr(&mut self) -> FERR_W { + FERR_W { w: self } + } + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&mut self) -> BUFOVF_W { + BUFOVF_W { w: self } + } + #[doc = "Bit 3 - Clear To Send"] + #[inline(always)] + pub fn cts(&mut self) -> CTS_W { + CTS_W { w: self } + } + #[doc = "Bit 4 - Inconsistent Sync Field"] + #[inline(always)] + pub fn isf(&mut self) -> ISF_W { + ISF_W { w: self } + } + #[doc = "Bit 5 - Collision Detected"] + #[inline(always)] + pub fn coll(&mut self) -> COLL_W { + COLL_W { w: self } + } + #[doc = "Bit 6 - Transmitter Empty"] + #[inline(always)] + pub fn txe(&mut self) -> TXE_W { + TXE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sercom0/usart_int/syncbusy.rs b/pac/atsamc21e/src/sercom0/usart_int/syncbusy.rs new file mode 100644 index 000000000000..5dea9a5a7bab --- /dev/null +++ b/pac/atsamc21e/src/sercom0/usart_int/syncbusy.rs @@ -0,0 +1,93 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - SERCOM Enable Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLB` reader - CTRLB Synchronization Busy"] +pub struct CTRLB_R(crate::FieldReader); +impl CTRLB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM Enable Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - CTRLB Synchronization Busy"] + #[inline(always)] + pub fn ctrlb(&self) -> CTRLB_R { + CTRLB_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +#[doc = "USART_INT Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/supc.rs b/pac/atsamc21e/src/supc.rs new file mode 100644 index 000000000000..452d8f3f9613 --- /dev/null +++ b/pac/atsamc21e/src/supc.rs @@ -0,0 +1,52 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x04 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x08 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x0c - Power and Clocks Status"] + pub status: crate::Reg, + #[doc = "0x10 - BODVDD Control"] + pub bodvdd: crate::Reg, + #[doc = "0x14 - BODCORE Control"] + pub bodcore: crate::Reg, + #[doc = "0x18 - VREG Control"] + pub vreg: crate::Reg, + #[doc = "0x1c - VREF Control"] + pub vref: crate::Reg, +} +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Power and Clocks Status"] +pub mod status; +#[doc = "BODVDD register accessor: an alias for `Reg`"] +pub type BODVDD = crate::Reg; +#[doc = "BODVDD Control"] +pub mod bodvdd; +#[doc = "BODCORE register accessor: an alias for `Reg`"] +pub type BODCORE = crate::Reg; +#[doc = "BODCORE Control"] +pub mod bodcore; +#[doc = "VREG register accessor: an alias for `Reg`"] +pub type VREG = crate::Reg; +#[doc = "VREG Control"] +pub mod vreg; +#[doc = "VREF register accessor: an alias for `Reg`"] +pub type VREF = crate::Reg; +#[doc = "VREF Control"] +pub mod vref; diff --git a/pac/atsamc21e/src/supc/bodcore.rs b/pac/atsamc21e/src/supc/bodcore.rs new file mode 100644 index 000000000000..670dec8e048c --- /dev/null +++ b/pac/atsamc21e/src/supc/bodcore.rs @@ -0,0 +1,705 @@ +#[doc = "Register `BODCORE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BODCORE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `HYST` reader - Hysteresis Enable"] +pub struct HYST_R(crate::FieldReader); +impl HYST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HYST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HYST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HYST` writer - Hysteresis Enable"] +pub struct HYST_W<'a> { + w: &'a mut W, +} +impl<'a> HYST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Action when Threshold Crossed\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum ACTION_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: The BODCORE generates a reset"] + RESET = 1, + #[doc = "2: The BODCORE generates an interrupt"] + INT = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: ACTION_A) -> Self { + variant as _ + } +} +#[doc = "Field `ACTION` reader - Action when Threshold Crossed"] +pub struct ACTION_R(crate::FieldReader); +impl ACTION_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ACTION_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(ACTION_A::NONE), + 1 => Some(ACTION_A::RESET), + 2 => Some(ACTION_A::INT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == ACTION_A::NONE + } + #[doc = "Checks if the value of the field is `RESET`"] + #[inline(always)] + pub fn is_reset(&self) -> bool { + **self == ACTION_A::RESET + } + #[doc = "Checks if the value of the field is `INT`"] + #[inline(always)] + pub fn is_int(&self) -> bool { + **self == ACTION_A::INT + } +} +impl core::ops::Deref for ACTION_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ACTION` writer - Action when Threshold Crossed"] +pub struct ACTION_W<'a> { + w: &'a mut W, +} +impl<'a> ACTION_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: ACTION_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(ACTION_A::NONE) + } + #[doc = "The BODCORE generates a reset"] + #[inline(always)] + pub fn reset(self) -> &'a mut W { + self.variant(ACTION_A::RESET) + } + #[doc = "The BODCORE generates an interrupt"] + #[inline(always)] + pub fn int(self) -> &'a mut W { + self.variant(ACTION_A::INT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 3)) | ((value as u32 & 0x03) << 3); + self.w + } +} +#[doc = "Field `STDBYCFG` reader - Configuration in Standby mode"] +pub struct STDBYCFG_R(crate::FieldReader); +impl STDBYCFG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STDBYCFG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STDBYCFG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STDBYCFG` writer - Configuration in Standby mode"] +pub struct STDBYCFG_W<'a> { + w: &'a mut W, +} +impl<'a> STDBYCFG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ACTCFG` reader - Configuration in Active mode"] +pub struct ACTCFG_R(crate::FieldReader); +impl ACTCFG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ACTCFG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ACTCFG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ACTCFG` writer - Configuration in Active mode"] +pub struct ACTCFG_W<'a> { + w: &'a mut W, +} +impl<'a> ACTCFG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Prescaler Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PSEL_A { + #[doc = "0: Divide clock by 2"] + DIV2 = 0, + #[doc = "1: Divide clock by 4"] + DIV4 = 1, + #[doc = "2: Divide clock by 8"] + DIV8 = 2, + #[doc = "3: Divide clock by 16"] + DIV16 = 3, + #[doc = "4: Divide clock by 32"] + DIV32 = 4, + #[doc = "5: Divide clock by 64"] + DIV64 = 5, + #[doc = "6: Divide clock by 128"] + DIV128 = 6, + #[doc = "7: Divide clock by 256"] + DIV256 = 7, + #[doc = "8: Divide clock by 512"] + DIV512 = 8, + #[doc = "9: Divide clock by 1024"] + DIV1024 = 9, + #[doc = "10: Divide clock by 2048"] + DIV2048 = 10, + #[doc = "11: Divide clock by 4096"] + DIV4096 = 11, + #[doc = "12: Divide clock by 8192"] + DIV8192 = 12, + #[doc = "13: Divide clock by 16384"] + DIV16384 = 13, + #[doc = "14: Divide clock by 32768"] + DIV32768 = 14, + #[doc = "15: Divide clock by 65536"] + DIV65536 = 15, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `PSEL` reader - Prescaler Select"] +pub struct PSEL_R(crate::FieldReader); +impl PSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PSEL_A { + match self.bits { + 0 => PSEL_A::DIV2, + 1 => PSEL_A::DIV4, + 2 => PSEL_A::DIV8, + 3 => PSEL_A::DIV16, + 4 => PSEL_A::DIV32, + 5 => PSEL_A::DIV64, + 6 => PSEL_A::DIV128, + 7 => PSEL_A::DIV256, + 8 => PSEL_A::DIV512, + 9 => PSEL_A::DIV1024, + 10 => PSEL_A::DIV2048, + 11 => PSEL_A::DIV4096, + 12 => PSEL_A::DIV8192, + 13 => PSEL_A::DIV16384, + 14 => PSEL_A::DIV32768, + 15 => PSEL_A::DIV65536, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PSEL_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PSEL_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PSEL_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PSEL_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == PSEL_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PSEL_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == PSEL_A::DIV128 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PSEL_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV512`"] + #[inline(always)] + pub fn is_div512(&self) -> bool { + **self == PSEL_A::DIV512 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PSEL_A::DIV1024 + } + #[doc = "Checks if the value of the field is `DIV2048`"] + #[inline(always)] + pub fn is_div2048(&self) -> bool { + **self == PSEL_A::DIV2048 + } + #[doc = "Checks if the value of the field is `DIV4096`"] + #[inline(always)] + pub fn is_div4096(&self) -> bool { + **self == PSEL_A::DIV4096 + } + #[doc = "Checks if the value of the field is `DIV8192`"] + #[inline(always)] + pub fn is_div8192(&self) -> bool { + **self == PSEL_A::DIV8192 + } + #[doc = "Checks if the value of the field is `DIV16384`"] + #[inline(always)] + pub fn is_div16384(&self) -> bool { + **self == PSEL_A::DIV16384 + } + #[doc = "Checks if the value of the field is `DIV32768`"] + #[inline(always)] + pub fn is_div32768(&self) -> bool { + **self == PSEL_A::DIV32768 + } + #[doc = "Checks if the value of the field is `DIV65536`"] + #[inline(always)] + pub fn is_div65536(&self) -> bool { + **self == PSEL_A::DIV65536 + } +} +impl core::ops::Deref for PSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PSEL` writer - Prescaler Select"] +pub struct PSEL_W<'a> { + w: &'a mut W, +} +impl<'a> PSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PSEL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Divide clock by 2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PSEL_A::DIV2) + } + #[doc = "Divide clock by 4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PSEL_A::DIV4) + } + #[doc = "Divide clock by 8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PSEL_A::DIV8) + } + #[doc = "Divide clock by 16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PSEL_A::DIV16) + } + #[doc = "Divide clock by 32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(PSEL_A::DIV32) + } + #[doc = "Divide clock by 64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PSEL_A::DIV64) + } + #[doc = "Divide clock by 128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(PSEL_A::DIV128) + } + #[doc = "Divide clock by 256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PSEL_A::DIV256) + } + #[doc = "Divide clock by 512"] + #[inline(always)] + pub fn div512(self) -> &'a mut W { + self.variant(PSEL_A::DIV512) + } + #[doc = "Divide clock by 1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PSEL_A::DIV1024) + } + #[doc = "Divide clock by 2048"] + #[inline(always)] + pub fn div2048(self) -> &'a mut W { + self.variant(PSEL_A::DIV2048) + } + #[doc = "Divide clock by 4096"] + #[inline(always)] + pub fn div4096(self) -> &'a mut W { + self.variant(PSEL_A::DIV4096) + } + #[doc = "Divide clock by 8192"] + #[inline(always)] + pub fn div8192(self) -> &'a mut W { + self.variant(PSEL_A::DIV8192) + } + #[doc = "Divide clock by 16384"] + #[inline(always)] + pub fn div16384(self) -> &'a mut W { + self.variant(PSEL_A::DIV16384) + } + #[doc = "Divide clock by 32768"] + #[inline(always)] + pub fn div32768(self) -> &'a mut W { + self.variant(PSEL_A::DIV32768) + } + #[doc = "Divide clock by 65536"] + #[inline(always)] + pub fn div65536(self) -> &'a mut W { + self.variant(PSEL_A::DIV65536) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 12)) | ((value as u32 & 0x0f) << 12); + self.w + } +} +#[doc = "Field `LEVEL` reader - Threshold Level"] +pub struct LEVEL_R(crate::FieldReader); +impl LEVEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LEVEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LEVEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LEVEL` writer - Threshold Level"] +pub struct LEVEL_W<'a> { + w: &'a mut W, +} +impl<'a> LEVEL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 16)) | ((value as u32 & 0x3f) << 16); + self.w + } +} +impl R { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Hysteresis Enable"] + #[inline(always)] + pub fn hyst(&self) -> HYST_R { + HYST_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 3:4 - Action when Threshold Crossed"] + #[inline(always)] + pub fn action(&self) -> ACTION_R { + ACTION_R::new(((self.bits >> 3) & 0x03) as u8) + } + #[doc = "Bit 5 - Configuration in Standby mode"] + #[inline(always)] + pub fn stdbycfg(&self) -> STDBYCFG_R { + STDBYCFG_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 8 - Configuration in Active mode"] + #[inline(always)] + pub fn actcfg(&self) -> ACTCFG_R { + ACTCFG_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bits 12:15 - Prescaler Select"] + #[inline(always)] + pub fn psel(&self) -> PSEL_R { + PSEL_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:21 - Threshold Level"] + #[inline(always)] + pub fn level(&self) -> LEVEL_R { + LEVEL_R::new(((self.bits >> 16) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - Hysteresis Enable"] + #[inline(always)] + pub fn hyst(&mut self) -> HYST_W { + HYST_W { w: self } + } + #[doc = "Bits 3:4 - Action when Threshold Crossed"] + #[inline(always)] + pub fn action(&mut self) -> ACTION_W { + ACTION_W { w: self } + } + #[doc = "Bit 5 - Configuration in Standby mode"] + #[inline(always)] + pub fn stdbycfg(&mut self) -> STDBYCFG_W { + STDBYCFG_W { w: self } + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 8 - Configuration in Active mode"] + #[inline(always)] + pub fn actcfg(&mut self) -> ACTCFG_W { + ACTCFG_W { w: self } + } + #[doc = "Bits 12:15 - Prescaler Select"] + #[inline(always)] + pub fn psel(&mut self) -> PSEL_W { + PSEL_W { w: self } + } + #[doc = "Bits 16:21 - Threshold Level"] + #[inline(always)] + pub fn level(&mut self) -> LEVEL_W { + LEVEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "BODCORE Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [bodcore](index.html) module"] +pub struct BODCORE_SPEC; +impl crate::RegisterSpec for BODCORE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [bodcore::R](R) reader structure"] +impl crate::Readable for BODCORE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [bodcore::W](W) writer structure"] +impl crate::Writable for BODCORE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BODCORE to value 0"] +impl crate::Resettable for BODCORE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/supc/bodvdd.rs b/pac/atsamc21e/src/supc/bodvdd.rs new file mode 100644 index 000000000000..f5cbfffb6453 --- /dev/null +++ b/pac/atsamc21e/src/supc/bodvdd.rs @@ -0,0 +1,705 @@ +#[doc = "Register `BODVDD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BODVDD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `HYST` reader - Hysteresis Enable"] +pub struct HYST_R(crate::FieldReader); +impl HYST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HYST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HYST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HYST` writer - Hysteresis Enable"] +pub struct HYST_W<'a> { + w: &'a mut W, +} +impl<'a> HYST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Action when Threshold Crossed\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum ACTION_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: The BODVDD generates a reset"] + RESET = 1, + #[doc = "2: The BODVDD generates an interrupt"] + INT = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: ACTION_A) -> Self { + variant as _ + } +} +#[doc = "Field `ACTION` reader - Action when Threshold Crossed"] +pub struct ACTION_R(crate::FieldReader); +impl ACTION_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ACTION_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(ACTION_A::NONE), + 1 => Some(ACTION_A::RESET), + 2 => Some(ACTION_A::INT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == ACTION_A::NONE + } + #[doc = "Checks if the value of the field is `RESET`"] + #[inline(always)] + pub fn is_reset(&self) -> bool { + **self == ACTION_A::RESET + } + #[doc = "Checks if the value of the field is `INT`"] + #[inline(always)] + pub fn is_int(&self) -> bool { + **self == ACTION_A::INT + } +} +impl core::ops::Deref for ACTION_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ACTION` writer - Action when Threshold Crossed"] +pub struct ACTION_W<'a> { + w: &'a mut W, +} +impl<'a> ACTION_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: ACTION_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(ACTION_A::NONE) + } + #[doc = "The BODVDD generates a reset"] + #[inline(always)] + pub fn reset(self) -> &'a mut W { + self.variant(ACTION_A::RESET) + } + #[doc = "The BODVDD generates an interrupt"] + #[inline(always)] + pub fn int(self) -> &'a mut W { + self.variant(ACTION_A::INT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 3)) | ((value as u32 & 0x03) << 3); + self.w + } +} +#[doc = "Field `STDBYCFG` reader - Configuration in Standby mode"] +pub struct STDBYCFG_R(crate::FieldReader); +impl STDBYCFG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STDBYCFG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STDBYCFG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STDBYCFG` writer - Configuration in Standby mode"] +pub struct STDBYCFG_W<'a> { + w: &'a mut W, +} +impl<'a> STDBYCFG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ACTCFG` reader - Configuration in Active mode"] +pub struct ACTCFG_R(crate::FieldReader); +impl ACTCFG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ACTCFG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ACTCFG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ACTCFG` writer - Configuration in Active mode"] +pub struct ACTCFG_W<'a> { + w: &'a mut W, +} +impl<'a> ACTCFG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Prescaler Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PSEL_A { + #[doc = "0: Divide clock by 2"] + DIV2 = 0, + #[doc = "1: Divide clock by 4"] + DIV4 = 1, + #[doc = "2: Divide clock by 8"] + DIV8 = 2, + #[doc = "3: Divide clock by 16"] + DIV16 = 3, + #[doc = "4: Divide clock by 32"] + DIV32 = 4, + #[doc = "5: Divide clock by 64"] + DIV64 = 5, + #[doc = "6: Divide clock by 128"] + DIV128 = 6, + #[doc = "7: Divide clock by 256"] + DIV256 = 7, + #[doc = "8: Divide clock by 512"] + DIV512 = 8, + #[doc = "9: Divide clock by 1024"] + DIV1024 = 9, + #[doc = "10: Divide clock by 2048"] + DIV2048 = 10, + #[doc = "11: Divide clock by 4096"] + DIV4096 = 11, + #[doc = "12: Divide clock by 8192"] + DIV8192 = 12, + #[doc = "13: Divide clock by 16384"] + DIV16384 = 13, + #[doc = "14: Divide clock by 32768"] + DIV32768 = 14, + #[doc = "15: Divide clock by 65536"] + DIV65536 = 15, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `PSEL` reader - Prescaler Select"] +pub struct PSEL_R(crate::FieldReader); +impl PSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PSEL_A { + match self.bits { + 0 => PSEL_A::DIV2, + 1 => PSEL_A::DIV4, + 2 => PSEL_A::DIV8, + 3 => PSEL_A::DIV16, + 4 => PSEL_A::DIV32, + 5 => PSEL_A::DIV64, + 6 => PSEL_A::DIV128, + 7 => PSEL_A::DIV256, + 8 => PSEL_A::DIV512, + 9 => PSEL_A::DIV1024, + 10 => PSEL_A::DIV2048, + 11 => PSEL_A::DIV4096, + 12 => PSEL_A::DIV8192, + 13 => PSEL_A::DIV16384, + 14 => PSEL_A::DIV32768, + 15 => PSEL_A::DIV65536, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PSEL_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PSEL_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PSEL_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PSEL_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == PSEL_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PSEL_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == PSEL_A::DIV128 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PSEL_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV512`"] + #[inline(always)] + pub fn is_div512(&self) -> bool { + **self == PSEL_A::DIV512 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PSEL_A::DIV1024 + } + #[doc = "Checks if the value of the field is `DIV2048`"] + #[inline(always)] + pub fn is_div2048(&self) -> bool { + **self == PSEL_A::DIV2048 + } + #[doc = "Checks if the value of the field is `DIV4096`"] + #[inline(always)] + pub fn is_div4096(&self) -> bool { + **self == PSEL_A::DIV4096 + } + #[doc = "Checks if the value of the field is `DIV8192`"] + #[inline(always)] + pub fn is_div8192(&self) -> bool { + **self == PSEL_A::DIV8192 + } + #[doc = "Checks if the value of the field is `DIV16384`"] + #[inline(always)] + pub fn is_div16384(&self) -> bool { + **self == PSEL_A::DIV16384 + } + #[doc = "Checks if the value of the field is `DIV32768`"] + #[inline(always)] + pub fn is_div32768(&self) -> bool { + **self == PSEL_A::DIV32768 + } + #[doc = "Checks if the value of the field is `DIV65536`"] + #[inline(always)] + pub fn is_div65536(&self) -> bool { + **self == PSEL_A::DIV65536 + } +} +impl core::ops::Deref for PSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PSEL` writer - Prescaler Select"] +pub struct PSEL_W<'a> { + w: &'a mut W, +} +impl<'a> PSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PSEL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Divide clock by 2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PSEL_A::DIV2) + } + #[doc = "Divide clock by 4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PSEL_A::DIV4) + } + #[doc = "Divide clock by 8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PSEL_A::DIV8) + } + #[doc = "Divide clock by 16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PSEL_A::DIV16) + } + #[doc = "Divide clock by 32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(PSEL_A::DIV32) + } + #[doc = "Divide clock by 64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PSEL_A::DIV64) + } + #[doc = "Divide clock by 128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(PSEL_A::DIV128) + } + #[doc = "Divide clock by 256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PSEL_A::DIV256) + } + #[doc = "Divide clock by 512"] + #[inline(always)] + pub fn div512(self) -> &'a mut W { + self.variant(PSEL_A::DIV512) + } + #[doc = "Divide clock by 1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PSEL_A::DIV1024) + } + #[doc = "Divide clock by 2048"] + #[inline(always)] + pub fn div2048(self) -> &'a mut W { + self.variant(PSEL_A::DIV2048) + } + #[doc = "Divide clock by 4096"] + #[inline(always)] + pub fn div4096(self) -> &'a mut W { + self.variant(PSEL_A::DIV4096) + } + #[doc = "Divide clock by 8192"] + #[inline(always)] + pub fn div8192(self) -> &'a mut W { + self.variant(PSEL_A::DIV8192) + } + #[doc = "Divide clock by 16384"] + #[inline(always)] + pub fn div16384(self) -> &'a mut W { + self.variant(PSEL_A::DIV16384) + } + #[doc = "Divide clock by 32768"] + #[inline(always)] + pub fn div32768(self) -> &'a mut W { + self.variant(PSEL_A::DIV32768) + } + #[doc = "Divide clock by 65536"] + #[inline(always)] + pub fn div65536(self) -> &'a mut W { + self.variant(PSEL_A::DIV65536) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 12)) | ((value as u32 & 0x0f) << 12); + self.w + } +} +#[doc = "Field `LEVEL` reader - Threshold Level for VDD"] +pub struct LEVEL_R(crate::FieldReader); +impl LEVEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LEVEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LEVEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LEVEL` writer - Threshold Level for VDD"] +pub struct LEVEL_W<'a> { + w: &'a mut W, +} +impl<'a> LEVEL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 16)) | ((value as u32 & 0x3f) << 16); + self.w + } +} +impl R { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Hysteresis Enable"] + #[inline(always)] + pub fn hyst(&self) -> HYST_R { + HYST_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 3:4 - Action when Threshold Crossed"] + #[inline(always)] + pub fn action(&self) -> ACTION_R { + ACTION_R::new(((self.bits >> 3) & 0x03) as u8) + } + #[doc = "Bit 5 - Configuration in Standby mode"] + #[inline(always)] + pub fn stdbycfg(&self) -> STDBYCFG_R { + STDBYCFG_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 8 - Configuration in Active mode"] + #[inline(always)] + pub fn actcfg(&self) -> ACTCFG_R { + ACTCFG_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bits 12:15 - Prescaler Select"] + #[inline(always)] + pub fn psel(&self) -> PSEL_R { + PSEL_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:21 - Threshold Level for VDD"] + #[inline(always)] + pub fn level(&self) -> LEVEL_R { + LEVEL_R::new(((self.bits >> 16) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - Hysteresis Enable"] + #[inline(always)] + pub fn hyst(&mut self) -> HYST_W { + HYST_W { w: self } + } + #[doc = "Bits 3:4 - Action when Threshold Crossed"] + #[inline(always)] + pub fn action(&mut self) -> ACTION_W { + ACTION_W { w: self } + } + #[doc = "Bit 5 - Configuration in Standby mode"] + #[inline(always)] + pub fn stdbycfg(&mut self) -> STDBYCFG_W { + STDBYCFG_W { w: self } + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 8 - Configuration in Active mode"] + #[inline(always)] + pub fn actcfg(&mut self) -> ACTCFG_W { + ACTCFG_W { w: self } + } + #[doc = "Bits 12:15 - Prescaler Select"] + #[inline(always)] + pub fn psel(&mut self) -> PSEL_W { + PSEL_W { w: self } + } + #[doc = "Bits 16:21 - Threshold Level for VDD"] + #[inline(always)] + pub fn level(&mut self) -> LEVEL_W { + LEVEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "BODVDD Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [bodvdd](index.html) module"] +pub struct BODVDD_SPEC; +impl crate::RegisterSpec for BODVDD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [bodvdd::R](R) reader structure"] +impl crate::Readable for BODVDD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [bodvdd::W](W) writer structure"] +impl crate::Writable for BODVDD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BODVDD to value 0"] +impl crate::Resettable for BODVDD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/supc/intenclr.rs b/pac/atsamc21e/src/supc/intenclr.rs new file mode 100644 index 000000000000..7b399544fafd --- /dev/null +++ b/pac/atsamc21e/src/supc/intenclr.rs @@ -0,0 +1,348 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BODVDDRDY` reader - BODVDD Ready"] +pub struct BODVDDRDY_R(crate::FieldReader); +impl BODVDDRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODVDDRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODVDDRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODVDDRDY` writer - BODVDD Ready"] +pub struct BODVDDRDY_W<'a> { + w: &'a mut W, +} +impl<'a> BODVDDRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `BODVDDDET` reader - BODVDD Detection"] +pub struct BODVDDDET_R(crate::FieldReader); +impl BODVDDDET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODVDDDET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODVDDDET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODVDDDET` writer - BODVDD Detection"] +pub struct BODVDDDET_W<'a> { + w: &'a mut W, +} +impl<'a> BODVDDDET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `BVDDSRDY` reader - BODVDD Synchronization Ready"] +pub struct BVDDSRDY_R(crate::FieldReader); +impl BVDDSRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BVDDSRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BVDDSRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BVDDSRDY` writer - BODVDD Synchronization Ready"] +pub struct BVDDSRDY_W<'a> { + w: &'a mut W, +} +impl<'a> BVDDSRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `BODCORERDY` reader - BODCORE Ready"] +pub struct BODCORERDY_R(crate::FieldReader); +impl BODCORERDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODCORERDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODCORERDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODCORERDY` writer - BODCORE Ready"] +pub struct BODCORERDY_W<'a> { + w: &'a mut W, +} +impl<'a> BODCORERDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `BODCOREDET` reader - BODCORE Detection"] +pub struct BODCOREDET_R(crate::FieldReader); +impl BODCOREDET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODCOREDET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODCOREDET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODCOREDET` writer - BODCORE Detection"] +pub struct BODCOREDET_W<'a> { + w: &'a mut W, +} +impl<'a> BODCOREDET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `BCORESRDY` reader - BODCORE Synchronization Ready"] +pub struct BCORESRDY_R(crate::FieldReader); +impl BCORESRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BCORESRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BCORESRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BCORESRDY` writer - BODCORE Synchronization Ready"] +pub struct BCORESRDY_W<'a> { + w: &'a mut W, +} +impl<'a> BCORESRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - BODVDD Ready"] + #[inline(always)] + pub fn bodvddrdy(&self) -> BODVDDRDY_R { + BODVDDRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - BODVDD Detection"] + #[inline(always)] + pub fn bodvdddet(&self) -> BODVDDDET_R { + BODVDDDET_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - BODVDD Synchronization Ready"] + #[inline(always)] + pub fn bvddsrdy(&self) -> BVDDSRDY_R { + BVDDSRDY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - BODCORE Ready"] + #[inline(always)] + pub fn bodcorerdy(&self) -> BODCORERDY_R { + BODCORERDY_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - BODCORE Detection"] + #[inline(always)] + pub fn bodcoredet(&self) -> BODCOREDET_R { + BODCOREDET_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - BODCORE Synchronization Ready"] + #[inline(always)] + pub fn bcoresrdy(&self) -> BCORESRDY_R { + BCORESRDY_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - BODVDD Ready"] + #[inline(always)] + pub fn bodvddrdy(&mut self) -> BODVDDRDY_W { + BODVDDRDY_W { w: self } + } + #[doc = "Bit 1 - BODVDD Detection"] + #[inline(always)] + pub fn bodvdddet(&mut self) -> BODVDDDET_W { + BODVDDDET_W { w: self } + } + #[doc = "Bit 2 - BODVDD Synchronization Ready"] + #[inline(always)] + pub fn bvddsrdy(&mut self) -> BVDDSRDY_W { + BVDDSRDY_W { w: self } + } + #[doc = "Bit 3 - BODCORE Ready"] + #[inline(always)] + pub fn bodcorerdy(&mut self) -> BODCORERDY_W { + BODCORERDY_W { w: self } + } + #[doc = "Bit 4 - BODCORE Detection"] + #[inline(always)] + pub fn bodcoredet(&mut self) -> BODCOREDET_W { + BODCOREDET_W { w: self } + } + #[doc = "Bit 5 - BODCORE Synchronization Ready"] + #[inline(always)] + pub fn bcoresrdy(&mut self) -> BCORESRDY_W { + BCORESRDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/supc/intenset.rs b/pac/atsamc21e/src/supc/intenset.rs new file mode 100644 index 000000000000..9e86a6e5b772 --- /dev/null +++ b/pac/atsamc21e/src/supc/intenset.rs @@ -0,0 +1,348 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BODVDDRDY` reader - BODVDD Ready"] +pub struct BODVDDRDY_R(crate::FieldReader); +impl BODVDDRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODVDDRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODVDDRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODVDDRDY` writer - BODVDD Ready"] +pub struct BODVDDRDY_W<'a> { + w: &'a mut W, +} +impl<'a> BODVDDRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `BODVDDDET` reader - BODVDD Detection"] +pub struct BODVDDDET_R(crate::FieldReader); +impl BODVDDDET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODVDDDET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODVDDDET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODVDDDET` writer - BODVDD Detection"] +pub struct BODVDDDET_W<'a> { + w: &'a mut W, +} +impl<'a> BODVDDDET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `BVDDSRDY` reader - BODVDD Synchronization Ready"] +pub struct BVDDSRDY_R(crate::FieldReader); +impl BVDDSRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BVDDSRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BVDDSRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BVDDSRDY` writer - BODVDD Synchronization Ready"] +pub struct BVDDSRDY_W<'a> { + w: &'a mut W, +} +impl<'a> BVDDSRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `BODCORERDY` reader - BODCORE Ready"] +pub struct BODCORERDY_R(crate::FieldReader); +impl BODCORERDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODCORERDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODCORERDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODCORERDY` writer - BODCORE Ready"] +pub struct BODCORERDY_W<'a> { + w: &'a mut W, +} +impl<'a> BODCORERDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `BODCOREDET` reader - BODCORE Detection"] +pub struct BODCOREDET_R(crate::FieldReader); +impl BODCOREDET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODCOREDET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODCOREDET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODCOREDET` writer - BODCORE Detection"] +pub struct BODCOREDET_W<'a> { + w: &'a mut W, +} +impl<'a> BODCOREDET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `BCORESRDY` reader - BODCORE Synchronization Ready"] +pub struct BCORESRDY_R(crate::FieldReader); +impl BCORESRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BCORESRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BCORESRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BCORESRDY` writer - BODCORE Synchronization Ready"] +pub struct BCORESRDY_W<'a> { + w: &'a mut W, +} +impl<'a> BCORESRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - BODVDD Ready"] + #[inline(always)] + pub fn bodvddrdy(&self) -> BODVDDRDY_R { + BODVDDRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - BODVDD Detection"] + #[inline(always)] + pub fn bodvdddet(&self) -> BODVDDDET_R { + BODVDDDET_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - BODVDD Synchronization Ready"] + #[inline(always)] + pub fn bvddsrdy(&self) -> BVDDSRDY_R { + BVDDSRDY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - BODCORE Ready"] + #[inline(always)] + pub fn bodcorerdy(&self) -> BODCORERDY_R { + BODCORERDY_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - BODCORE Detection"] + #[inline(always)] + pub fn bodcoredet(&self) -> BODCOREDET_R { + BODCOREDET_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - BODCORE Synchronization Ready"] + #[inline(always)] + pub fn bcoresrdy(&self) -> BCORESRDY_R { + BCORESRDY_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - BODVDD Ready"] + #[inline(always)] + pub fn bodvddrdy(&mut self) -> BODVDDRDY_W { + BODVDDRDY_W { w: self } + } + #[doc = "Bit 1 - BODVDD Detection"] + #[inline(always)] + pub fn bodvdddet(&mut self) -> BODVDDDET_W { + BODVDDDET_W { w: self } + } + #[doc = "Bit 2 - BODVDD Synchronization Ready"] + #[inline(always)] + pub fn bvddsrdy(&mut self) -> BVDDSRDY_W { + BVDDSRDY_W { w: self } + } + #[doc = "Bit 3 - BODCORE Ready"] + #[inline(always)] + pub fn bodcorerdy(&mut self) -> BODCORERDY_W { + BODCORERDY_W { w: self } + } + #[doc = "Bit 4 - BODCORE Detection"] + #[inline(always)] + pub fn bodcoredet(&mut self) -> BODCOREDET_W { + BODCOREDET_W { w: self } + } + #[doc = "Bit 5 - BODCORE Synchronization Ready"] + #[inline(always)] + pub fn bcoresrdy(&mut self) -> BCORESRDY_W { + BCORESRDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/supc/intflag.rs b/pac/atsamc21e/src/supc/intflag.rs new file mode 100644 index 000000000000..46b4b52add2d --- /dev/null +++ b/pac/atsamc21e/src/supc/intflag.rs @@ -0,0 +1,348 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BODVDDRDY` reader - BODVDD Ready"] +pub struct BODVDDRDY_R(crate::FieldReader); +impl BODVDDRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODVDDRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODVDDRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODVDDRDY` writer - BODVDD Ready"] +pub struct BODVDDRDY_W<'a> { + w: &'a mut W, +} +impl<'a> BODVDDRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `BODVDDDET` reader - BODVDD Detection"] +pub struct BODVDDDET_R(crate::FieldReader); +impl BODVDDDET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODVDDDET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODVDDDET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODVDDDET` writer - BODVDD Detection"] +pub struct BODVDDDET_W<'a> { + w: &'a mut W, +} +impl<'a> BODVDDDET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `BVDDSRDY` reader - BODVDD Synchronization Ready"] +pub struct BVDDSRDY_R(crate::FieldReader); +impl BVDDSRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BVDDSRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BVDDSRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BVDDSRDY` writer - BODVDD Synchronization Ready"] +pub struct BVDDSRDY_W<'a> { + w: &'a mut W, +} +impl<'a> BVDDSRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `BODCORERDY` reader - BODCORE Ready"] +pub struct BODCORERDY_R(crate::FieldReader); +impl BODCORERDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODCORERDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODCORERDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODCORERDY` writer - BODCORE Ready"] +pub struct BODCORERDY_W<'a> { + w: &'a mut W, +} +impl<'a> BODCORERDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `BODCOREDET` reader - BODCORE Detection"] +pub struct BODCOREDET_R(crate::FieldReader); +impl BODCOREDET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODCOREDET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODCOREDET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODCOREDET` writer - BODCORE Detection"] +pub struct BODCOREDET_W<'a> { + w: &'a mut W, +} +impl<'a> BODCOREDET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `BCORESRDY` reader - BODCORE Synchronization Ready"] +pub struct BCORESRDY_R(crate::FieldReader); +impl BCORESRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BCORESRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BCORESRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BCORESRDY` writer - BODCORE Synchronization Ready"] +pub struct BCORESRDY_W<'a> { + w: &'a mut W, +} +impl<'a> BCORESRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - BODVDD Ready"] + #[inline(always)] + pub fn bodvddrdy(&self) -> BODVDDRDY_R { + BODVDDRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - BODVDD Detection"] + #[inline(always)] + pub fn bodvdddet(&self) -> BODVDDDET_R { + BODVDDDET_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - BODVDD Synchronization Ready"] + #[inline(always)] + pub fn bvddsrdy(&self) -> BVDDSRDY_R { + BVDDSRDY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - BODCORE Ready"] + #[inline(always)] + pub fn bodcorerdy(&self) -> BODCORERDY_R { + BODCORERDY_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - BODCORE Detection"] + #[inline(always)] + pub fn bodcoredet(&self) -> BODCOREDET_R { + BODCOREDET_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - BODCORE Synchronization Ready"] + #[inline(always)] + pub fn bcoresrdy(&self) -> BCORESRDY_R { + BCORESRDY_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - BODVDD Ready"] + #[inline(always)] + pub fn bodvddrdy(&mut self) -> BODVDDRDY_W { + BODVDDRDY_W { w: self } + } + #[doc = "Bit 1 - BODVDD Detection"] + #[inline(always)] + pub fn bodvdddet(&mut self) -> BODVDDDET_W { + BODVDDDET_W { w: self } + } + #[doc = "Bit 2 - BODVDD Synchronization Ready"] + #[inline(always)] + pub fn bvddsrdy(&mut self) -> BVDDSRDY_W { + BVDDSRDY_W { w: self } + } + #[doc = "Bit 3 - BODCORE Ready"] + #[inline(always)] + pub fn bodcorerdy(&mut self) -> BODCORERDY_W { + BODCORERDY_W { w: self } + } + #[doc = "Bit 4 - BODCORE Detection"] + #[inline(always)] + pub fn bodcoredet(&mut self) -> BODCOREDET_W { + BODCOREDET_W { w: self } + } + #[doc = "Bit 5 - BODCORE Synchronization Ready"] + #[inline(always)] + pub fn bcoresrdy(&mut self) -> BCORESRDY_W { + BCORESRDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/supc/status.rs b/pac/atsamc21e/src/supc/status.rs new file mode 100644 index 000000000000..0fc1de3635b5 --- /dev/null +++ b/pac/atsamc21e/src/supc/status.rs @@ -0,0 +1,153 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `BODVDDRDY` reader - BODVDD Ready"] +pub struct BODVDDRDY_R(crate::FieldReader); +impl BODVDDRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODVDDRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODVDDRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODVDDDET` reader - BODVDD Detection"] +pub struct BODVDDDET_R(crate::FieldReader); +impl BODVDDDET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODVDDDET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODVDDDET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BVDDSRDY` reader - BODVDD Synchronization Ready"] +pub struct BVDDSRDY_R(crate::FieldReader); +impl BVDDSRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BVDDSRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BVDDSRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODCORERDY` reader - BODCORE Ready"] +pub struct BODCORERDY_R(crate::FieldReader); +impl BODCORERDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODCORERDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODCORERDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODCOREDET` reader - BODCORE Detection"] +pub struct BODCOREDET_R(crate::FieldReader); +impl BODCOREDET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODCOREDET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODCOREDET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BCORESRDY` reader - BODCORE Synchronization Ready"] +pub struct BCORESRDY_R(crate::FieldReader); +impl BCORESRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BCORESRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BCORESRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - BODVDD Ready"] + #[inline(always)] + pub fn bodvddrdy(&self) -> BODVDDRDY_R { + BODVDDRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - BODVDD Detection"] + #[inline(always)] + pub fn bodvdddet(&self) -> BODVDDDET_R { + BODVDDDET_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - BODVDD Synchronization Ready"] + #[inline(always)] + pub fn bvddsrdy(&self) -> BVDDSRDY_R { + BVDDSRDY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - BODCORE Ready"] + #[inline(always)] + pub fn bodcorerdy(&self) -> BODCORERDY_R { + BODCORERDY_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - BODCORE Detection"] + #[inline(always)] + pub fn bodcoredet(&self) -> BODCOREDET_R { + BODCOREDET_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - BODCORE Synchronization Ready"] + #[inline(always)] + pub fn bcoresrdy(&self) -> BCORESRDY_R { + BCORESRDY_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +#[doc = "Power and Clocks Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/supc/vref.rs b/pac/atsamc21e/src/supc/vref.rs new file mode 100644 index 000000000000..2d5b1381885e --- /dev/null +++ b/pac/atsamc21e/src/supc/vref.rs @@ -0,0 +1,353 @@ +#[doc = "Register `VREF` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `VREF` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TSEN` reader - Temperature Sensor Output Enable"] +pub struct TSEN_R(crate::FieldReader); +impl TSEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSEN` writer - Temperature Sensor Output Enable"] +pub struct TSEN_W<'a> { + w: &'a mut W, +} +impl<'a> TSEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `VREFOE` reader - Voltage Reference Output Enable"] +pub struct VREFOE_R(crate::FieldReader); +impl VREFOE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + VREFOE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VREFOE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VREFOE` writer - Voltage Reference Output Enable"] +pub struct VREFOE_W<'a> { + w: &'a mut W, +} +impl<'a> VREFOE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - On Demand Contrl"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - On Demand Contrl"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Voltage Reference Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SEL_A { + #[doc = "0: 1.024V voltage reference typical value"] + _1V024 = 0, + #[doc = "2: 2.048V voltage reference typical value"] + _2V048 = 2, + #[doc = "3: 4.096V voltage reference typical value"] + _4V096 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `SEL` reader - Voltage Reference Selection"] +pub struct SEL_R(crate::FieldReader); +impl SEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEL_A::_1V024), + 2 => Some(SEL_A::_2V048), + 3 => Some(SEL_A::_4V096), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_1V024`"] + #[inline(always)] + pub fn is_1v024(&self) -> bool { + **self == SEL_A::_1V024 + } + #[doc = "Checks if the value of the field is `_2V048`"] + #[inline(always)] + pub fn is_2v048(&self) -> bool { + **self == SEL_A::_2V048 + } + #[doc = "Checks if the value of the field is `_4V096`"] + #[inline(always)] + pub fn is_4v096(&self) -> bool { + **self == SEL_A::_4V096 + } +} +impl core::ops::Deref for SEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEL` writer - Voltage Reference Selection"] +pub struct SEL_W<'a> { + w: &'a mut W, +} +impl<'a> SEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SEL_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "1.024V voltage reference typical value"] + #[inline(always)] + pub fn _1v024(self) -> &'a mut W { + self.variant(SEL_A::_1V024) + } + #[doc = "2.048V voltage reference typical value"] + #[inline(always)] + pub fn _2v048(self) -> &'a mut W { + self.variant(SEL_A::_2V048) + } + #[doc = "4.096V voltage reference typical value"] + #[inline(always)] + pub fn _4v096(self) -> &'a mut W { + self.variant(SEL_A::_4V096) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 16)) | ((value as u32 & 0x0f) << 16); + self.w + } +} +impl R { + #[doc = "Bit 1 - Temperature Sensor Output Enable"] + #[inline(always)] + pub fn tsen(&self) -> TSEN_R { + TSEN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Voltage Reference Output Enable"] + #[inline(always)] + pub fn vrefoe(&self) -> VREFOE_R { + VREFOE_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - On Demand Contrl"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 16:19 - Voltage Reference Selection"] + #[inline(always)] + pub fn sel(&self) -> SEL_R { + SEL_R::new(((self.bits >> 16) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bit 1 - Temperature Sensor Output Enable"] + #[inline(always)] + pub fn tsen(&mut self) -> TSEN_W { + TSEN_W { w: self } + } + #[doc = "Bit 2 - Voltage Reference Output Enable"] + #[inline(always)] + pub fn vrefoe(&mut self) -> VREFOE_W { + VREFOE_W { w: self } + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - On Demand Contrl"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Bits 16:19 - Voltage Reference Selection"] + #[inline(always)] + pub fn sel(&mut self) -> SEL_W { + SEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "VREF Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [vref](index.html) module"] +pub struct VREF_SPEC; +impl crate::RegisterSpec for VREF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [vref::R](R) reader structure"] +impl crate::Readable for VREF_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [vref::W](W) writer structure"] +impl crate::Writable for VREF_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets VREF to value 0"] +impl crate::Resettable for VREF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/supc/vreg.rs b/pac/atsamc21e/src/supc/vreg.rs new file mode 100644 index 000000000000..fb5b12a185cf --- /dev/null +++ b/pac/atsamc21e/src/supc/vreg.rs @@ -0,0 +1,160 @@ +#[doc = "Register `VREG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `VREG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "VREG Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [vreg](index.html) module"] +pub struct VREG_SPEC; +impl crate::RegisterSpec for VREG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [vreg::R](R) reader structure"] +impl crate::Readable for VREG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [vreg::W](W) writer structure"] +impl crate::Writable for VREG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets VREG to value 0"] +impl crate::Resettable for VREG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sys_tick.rs b/pac/atsamc21e/src/sys_tick.rs new file mode 100644 index 000000000000..b0fe7a59e5ed --- /dev/null +++ b/pac/atsamc21e/src/sys_tick.rs @@ -0,0 +1,28 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - SysTick Control and Status Register"] + pub csr: crate::Reg, + #[doc = "0x04 - SysTick Reload Value Register"] + pub rvr: crate::Reg, + #[doc = "0x08 - SysTick Current Value Register"] + pub cvr: crate::Reg, + #[doc = "0x0c - SysTick Calibration Value Register"] + pub calib: crate::Reg, +} +#[doc = "CSR register accessor: an alias for `Reg`"] +pub type CSR = crate::Reg; +#[doc = "SysTick Control and Status Register"] +pub mod csr; +#[doc = "RVR register accessor: an alias for `Reg`"] +pub type RVR = crate::Reg; +#[doc = "SysTick Reload Value Register"] +pub mod rvr; +#[doc = "CVR register accessor: an alias for `Reg`"] +pub type CVR = crate::Reg; +#[doc = "SysTick Current Value Register"] +pub mod cvr; +#[doc = "CALIB register accessor: an alias for `Reg`"] +pub type CALIB = crate::Reg; +#[doc = "SysTick Calibration Value Register"] +pub mod calib; diff --git a/pac/atsamc21e/src/sys_tick/calib.rs b/pac/atsamc21e/src/sys_tick/calib.rs new file mode 100644 index 000000000000..df7fd80f773a --- /dev/null +++ b/pac/atsamc21e/src/sys_tick/calib.rs @@ -0,0 +1,157 @@ +#[doc = "Register `CALIB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `TENMS` reader - Reload value to use for 10ms timing"] +pub struct TENMS_R(crate::FieldReader); +impl TENMS_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + TENMS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TENMS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "TENMS is rounded from non-integer ratio\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SKEW_A { + #[doc = "0: 10ms calibration value is exact"] + VALUE_0 = 0, + #[doc = "1: 10ms calibration value is inexact, because of the clock frequency"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SKEW_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SKEW` reader - TENMS is rounded from non-integer ratio"] +pub struct SKEW_R(crate::FieldReader); +impl SKEW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SKEW_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SKEW_A { + match self.bits { + false => SKEW_A::VALUE_0, + true => SKEW_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == SKEW_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == SKEW_A::VALUE_1 + } +} +impl core::ops::Deref for SKEW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "No Separate Reference Clock\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum NOREF_A { + #[doc = "0: The reference clock is provided"] + VALUE_0 = 0, + #[doc = "1: The reference clock is not provided"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NOREF_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NOREF` reader - No Separate Reference Clock"] +pub struct NOREF_R(crate::FieldReader); +impl NOREF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NOREF_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> NOREF_A { + match self.bits { + false => NOREF_A::VALUE_0, + true => NOREF_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == NOREF_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == NOREF_A::VALUE_1 + } +} +impl core::ops::Deref for NOREF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:23 - Reload value to use for 10ms timing"] + #[inline(always)] + pub fn tenms(&self) -> TENMS_R { + TENMS_R::new((self.bits & 0x00ff_ffff) as u32) + } + #[doc = "Bit 30 - TENMS is rounded from non-integer ratio"] + #[inline(always)] + pub fn skew(&self) -> SKEW_R { + SKEW_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 31 - No Separate Reference Clock"] + #[inline(always)] + pub fn noref(&self) -> NOREF_R { + NOREF_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +#[doc = "SysTick Calibration Value Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [calib](index.html) module"] +pub struct CALIB_SPEC; +impl crate::RegisterSpec for CALIB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [calib::R](R) reader structure"] +impl crate::Readable for CALIB_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CALIB to value 0"] +impl crate::Resettable for CALIB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sys_tick/csr.rs b/pac/atsamc21e/src/sys_tick/csr.rs new file mode 100644 index 000000000000..872d637f5a86 --- /dev/null +++ b/pac/atsamc21e/src/sys_tick/csr.rs @@ -0,0 +1,395 @@ +#[doc = "Register `CSR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CSR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "SysTick Counter Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ENABLE_A { + #[doc = "0: Counter disabled"] + VALUE_0 = 0, + #[doc = "1: Counter enabled"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ENABLE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ENABLE` reader - SysTick Counter Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ENABLE_A { + match self.bits { + false => ENABLE_A::VALUE_0, + true => ENABLE_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == ENABLE_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == ENABLE_A::VALUE_1 + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - SysTick Counter Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: ENABLE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Counter disabled"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(ENABLE_A::VALUE_0) + } + #[doc = "Counter enabled"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(ENABLE_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "SysTick Exception Request Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TICKINT_A { + #[doc = "0: Counting down to 0 does not assert the SysTick exception request"] + VALUE_0 = 0, + #[doc = "1: Counting down to 0 asserts the SysTick exception request"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TICKINT_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TICKINT` reader - SysTick Exception Request Enable"] +pub struct TICKINT_R(crate::FieldReader); +impl TICKINT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TICKINT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TICKINT_A { + match self.bits { + false => TICKINT_A::VALUE_0, + true => TICKINT_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == TICKINT_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == TICKINT_A::VALUE_1 + } +} +impl core::ops::Deref for TICKINT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TICKINT` writer - SysTick Exception Request Enable"] +pub struct TICKINT_W<'a> { + w: &'a mut W, +} +impl<'a> TICKINT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TICKINT_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Counting down to 0 does not assert the SysTick exception request"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(TICKINT_A::VALUE_0) + } + #[doc = "Counting down to 0 asserts the SysTick exception request"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(TICKINT_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Clock Source 0=external, 1=processor\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CLKSOURCE_A { + #[doc = "0: External clock"] + VALUE_0 = 0, + #[doc = "1: Processor clock"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CLKSOURCE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CLKSOURCE` reader - Clock Source 0=external, 1=processor"] +pub struct CLKSOURCE_R(crate::FieldReader); +impl CLKSOURCE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKSOURCE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CLKSOURCE_A { + match self.bits { + false => CLKSOURCE_A::VALUE_0, + true => CLKSOURCE_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == CLKSOURCE_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == CLKSOURCE_A::VALUE_1 + } +} +impl core::ops::Deref for CLKSOURCE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKSOURCE` writer - Clock Source 0=external, 1=processor"] +pub struct CLKSOURCE_W<'a> { + w: &'a mut W, +} +impl<'a> CLKSOURCE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CLKSOURCE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "External clock"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(CLKSOURCE_A::VALUE_0) + } + #[doc = "Processor clock"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(CLKSOURCE_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `COUNTFLAG` reader - Timer counted to 0 since last read of register"] +pub struct COUNTFLAG_R(crate::FieldReader); +impl COUNTFLAG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNTFLAG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNTFLAG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNTFLAG` writer - Timer counted to 0 since last read of register"] +pub struct COUNTFLAG_W<'a> { + w: &'a mut W, +} +impl<'a> COUNTFLAG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +impl R { + #[doc = "Bit 0 - SysTick Counter Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SysTick Exception Request Enable"] + #[inline(always)] + pub fn tickint(&self) -> TICKINT_R { + TICKINT_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Clock Source 0=external, 1=processor"] + #[inline(always)] + pub fn clksource(&self) -> CLKSOURCE_R { + CLKSOURCE_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 16 - Timer counted to 0 since last read of register"] + #[inline(always)] + pub fn countflag(&self) -> COUNTFLAG_R { + COUNTFLAG_R::new(((self.bits >> 16) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - SysTick Counter Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 1 - SysTick Exception Request Enable"] + #[inline(always)] + pub fn tickint(&mut self) -> TICKINT_W { + TICKINT_W { w: self } + } + #[doc = "Bit 2 - Clock Source 0=external, 1=processor"] + #[inline(always)] + pub fn clksource(&mut self) -> CLKSOURCE_W { + CLKSOURCE_W { w: self } + } + #[doc = "Bit 16 - Timer counted to 0 since last read of register"] + #[inline(always)] + pub fn countflag(&mut self) -> COUNTFLAG_W { + COUNTFLAG_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SysTick Control and Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [csr](index.html) module"] +pub struct CSR_SPEC; +impl crate::RegisterSpec for CSR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [csr::R](R) reader structure"] +impl crate::Readable for CSR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [csr::W](W) writer structure"] +impl crate::Writable for CSR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CSR to value 0x04"] +impl crate::Resettable for CSR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x04 + } +} diff --git a/pac/atsamc21e/src/sys_tick/cvr.rs b/pac/atsamc21e/src/sys_tick/cvr.rs new file mode 100644 index 000000000000..8a40b5f43b3a --- /dev/null +++ b/pac/atsamc21e/src/sys_tick/cvr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `CVR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CVR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CURRENT` reader - Current value at the time the register is accessed"] +pub struct CURRENT_R(crate::FieldReader); +impl CURRENT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CURRENT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CURRENT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CURRENT` writer - Current value at the time the register is accessed"] +pub struct CURRENT_W<'a> { + w: &'a mut W, +} +impl<'a> CURRENT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Current value at the time the register is accessed"] + #[inline(always)] + pub fn current(&self) -> CURRENT_R { + CURRENT_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Current value at the time the register is accessed"] + #[inline(always)] + pub fn current(&mut self) -> CURRENT_W { + CURRENT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SysTick Current Value Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cvr](index.html) module"] +pub struct CVR_SPEC; +impl crate::RegisterSpec for CVR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cvr::R](R) reader structure"] +impl crate::Readable for CVR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cvr::W](W) writer structure"] +impl crate::Writable for CVR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CVR to value 0"] +impl crate::Resettable for CVR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/sys_tick/rvr.rs b/pac/atsamc21e/src/sys_tick/rvr.rs new file mode 100644 index 000000000000..ac023ff75f36 --- /dev/null +++ b/pac/atsamc21e/src/sys_tick/rvr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `RVR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RVR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RELOAD` reader - Value to load into the SysTick Current Value Register when the counter reaches 0"] +pub struct RELOAD_R(crate::FieldReader); +impl RELOAD_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + RELOAD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RELOAD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RELOAD` writer - Value to load into the SysTick Current Value Register when the counter reaches 0"] +pub struct RELOAD_W<'a> { + w: &'a mut W, +} +impl<'a> RELOAD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Value to load into the SysTick Current Value Register when the counter reaches 0"] + #[inline(always)] + pub fn reload(&self) -> RELOAD_R { + RELOAD_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Value to load into the SysTick Current Value Register when the counter reaches 0"] + #[inline(always)] + pub fn reload(&mut self) -> RELOAD_W { + RELOAD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SysTick Reload Value Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rvr](index.html) module"] +pub struct RVR_SPEC; +impl crate::RegisterSpec for RVR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rvr::R](R) reader structure"] +impl crate::Readable for RVR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rvr::W](W) writer structure"] +impl crate::Writable for RVR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RVR to value 0"] +impl crate::Resettable for RVR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/system_control.rs b/pac/atsamc21e/src/system_control.rs new file mode 100644 index 000000000000..4894b22b258f --- /dev/null +++ b/pac/atsamc21e/src/system_control.rs @@ -0,0 +1,67 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved0: [u8; 0x0d00], + #[doc = "0xd00 - CPUID Base Register"] + pub cpuid: crate::Reg, + #[doc = "0xd04 - Interrupt Control and State Register"] + pub icsr: crate::Reg, + #[doc = "0xd08 - Vector Table Offset Register"] + pub vtor: crate::Reg, + #[doc = "0xd0c - Application Interrupt and Reset Control Register"] + pub aircr: crate::Reg, + #[doc = "0xd10 - System Control Register"] + pub scr: crate::Reg, + #[doc = "0xd14 - Configuration and Control Register"] + pub ccr: crate::Reg, + _reserved6: [u8; 0x04], + #[doc = "0xd1c - System Handler Priority Register 2"] + pub shpr2: crate::Reg, + #[doc = "0xd20 - System Handler Priority Register 3"] + pub shpr3: crate::Reg, + #[doc = "0xd24 - System Handler Control and State Register"] + pub shcsr: crate::Reg, + _reserved9: [u8; 0x08], + #[doc = "0xd30 - Debug Fault Status Register"] + pub dfsr: crate::Reg, +} +#[doc = "CPUID register accessor: an alias for `Reg`"] +pub type CPUID = crate::Reg; +#[doc = "CPUID Base Register"] +pub mod cpuid; +#[doc = "ICSR register accessor: an alias for `Reg`"] +pub type ICSR = crate::Reg; +#[doc = "Interrupt Control and State Register"] +pub mod icsr; +#[doc = "VTOR register accessor: an alias for `Reg`"] +pub type VTOR = crate::Reg; +#[doc = "Vector Table Offset Register"] +pub mod vtor; +#[doc = "AIRCR register accessor: an alias for `Reg`"] +pub type AIRCR = crate::Reg; +#[doc = "Application Interrupt and Reset Control Register"] +pub mod aircr; +#[doc = "SCR register accessor: an alias for `Reg`"] +pub type SCR = crate::Reg; +#[doc = "System Control Register"] +pub mod scr; +#[doc = "CCR register accessor: an alias for `Reg`"] +pub type CCR = crate::Reg; +#[doc = "Configuration and Control Register"] +pub mod ccr; +#[doc = "SHPR2 register accessor: an alias for `Reg`"] +pub type SHPR2 = crate::Reg; +#[doc = "System Handler Priority Register 2"] +pub mod shpr2; +#[doc = "SHPR3 register accessor: an alias for `Reg`"] +pub type SHPR3 = crate::Reg; +#[doc = "System Handler Priority Register 3"] +pub mod shpr3; +#[doc = "SHCSR register accessor: an alias for `Reg`"] +pub type SHCSR = crate::Reg; +#[doc = "System Handler Control and State Register"] +pub mod shcsr; +#[doc = "DFSR register accessor: an alias for `Reg`"] +pub type DFSR = crate::Reg; +#[doc = "Debug Fault Status Register"] +pub mod dfsr; diff --git a/pac/atsamc21e/src/system_control/aircr.rs b/pac/atsamc21e/src/system_control/aircr.rs new file mode 100644 index 000000000000..9453cc6f30bc --- /dev/null +++ b/pac/atsamc21e/src/system_control/aircr.rs @@ -0,0 +1,338 @@ +#[doc = "Register `AIRCR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `AIRCR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `VECTCLRACTIVE` reader - Debug: Clear state information"] +pub struct VECTCLRACTIVE_R(crate::FieldReader); +impl VECTCLRACTIVE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + VECTCLRACTIVE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VECTCLRACTIVE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VECTCLRACTIVE` writer - Debug: Clear state information"] +pub struct VECTCLRACTIVE_W<'a> { + w: &'a mut W, +} +impl<'a> VECTCLRACTIVE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "System Reset Request\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SYSRESETREQ_A { + #[doc = "0: No system reset request"] + VALUE_0 = 0, + #[doc = "1: Asserts a signal to the outer system that requests a reset"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SYSRESETREQ_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SYSRESETREQ` reader - System Reset Request"] +pub struct SYSRESETREQ_R(crate::FieldReader); +impl SYSRESETREQ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYSRESETREQ_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SYSRESETREQ_A { + match self.bits { + false => SYSRESETREQ_A::VALUE_0, + true => SYSRESETREQ_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == SYSRESETREQ_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == SYSRESETREQ_A::VALUE_1 + } +} +impl core::ops::Deref for SYSRESETREQ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYSRESETREQ` writer - System Reset Request"] +pub struct SYSRESETREQ_W<'a> { + w: &'a mut W, +} +impl<'a> SYSRESETREQ_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SYSRESETREQ_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "No system reset request"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(SYSRESETREQ_A::VALUE_0) + } + #[doc = "Asserts a signal to the outer system that requests a reset"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(SYSRESETREQ_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Data Endianness, 0=little, 1=big\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ENDIANNESS_A { + #[doc = "0: Little-endian"] + VALUE_0 = 0, + #[doc = "1: Big-endian"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ENDIANNESS_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ENDIANNESS` reader - Data Endianness, 0=little, 1=big"] +pub struct ENDIANNESS_R(crate::FieldReader); +impl ENDIANNESS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENDIANNESS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ENDIANNESS_A { + match self.bits { + false => ENDIANNESS_A::VALUE_0, + true => ENDIANNESS_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == ENDIANNESS_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == ENDIANNESS_A::VALUE_1 + } +} +impl core::ops::Deref for ENDIANNESS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENDIANNESS` writer - Data Endianness, 0=little, 1=big"] +pub struct ENDIANNESS_W<'a> { + w: &'a mut W, +} +impl<'a> ENDIANNESS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: ENDIANNESS_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Little-endian"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(ENDIANNESS_A::VALUE_0) + } + #[doc = "Big-endian"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(ENDIANNESS_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `VECTKEY` reader - Register key (0x05FA)"] +pub struct VECTKEY_R(crate::FieldReader); +impl VECTKEY_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + VECTKEY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VECTKEY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VECTKEY` writer - Register key (0x05FA)"] +pub struct VECTKEY_W<'a> { + w: &'a mut W, +} +impl<'a> VECTKEY_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xffff << 16)) | ((value as u32 & 0xffff) << 16); + self.w + } +} +impl R { + #[doc = "Bit 1 - Debug: Clear state information"] + #[inline(always)] + pub fn vectclractive(&self) -> VECTCLRACTIVE_R { + VECTCLRACTIVE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - System Reset Request"] + #[inline(always)] + pub fn sysresetreq(&self) -> SYSRESETREQ_R { + SYSRESETREQ_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 15 - Data Endianness, 0=little, 1=big"] + #[inline(always)] + pub fn endianness(&self) -> ENDIANNESS_R { + ENDIANNESS_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:31 - Register key (0x05FA)"] + #[inline(always)] + pub fn vectkey(&self) -> VECTKEY_R { + VECTKEY_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bit 1 - Debug: Clear state information"] + #[inline(always)] + pub fn vectclractive(&mut self) -> VECTCLRACTIVE_W { + VECTCLRACTIVE_W { w: self } + } + #[doc = "Bit 2 - System Reset Request"] + #[inline(always)] + pub fn sysresetreq(&mut self) -> SYSRESETREQ_W { + SYSRESETREQ_W { w: self } + } + #[doc = "Bit 15 - Data Endianness, 0=little, 1=big"] + #[inline(always)] + pub fn endianness(&mut self) -> ENDIANNESS_W { + ENDIANNESS_W { w: self } + } + #[doc = "Bits 16:31 - Register key (0x05FA)"] + #[inline(always)] + pub fn vectkey(&mut self) -> VECTKEY_W { + VECTKEY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Application Interrupt and Reset Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [aircr](index.html) module"] +pub struct AIRCR_SPEC; +impl crate::RegisterSpec for AIRCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [aircr::R](R) reader structure"] +impl crate::Readable for AIRCR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [aircr::W](W) writer structure"] +impl crate::Writable for AIRCR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets AIRCR to value 0"] +impl crate::Resettable for AIRCR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/system_control/ccr.rs b/pac/atsamc21e/src/system_control/ccr.rs new file mode 100644 index 000000000000..62516a7b60c8 --- /dev/null +++ b/pac/atsamc21e/src/system_control/ccr.rs @@ -0,0 +1,137 @@ +#[doc = "Register `CCR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Unaligned accesses generates a Hard Fault\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum UNALIGN_TRP_A { + #[doc = "0: Do not trap unaligned halfword and word accesses"] + VALUE_0 = 0, + #[doc = "1: Trap unaligned halfword and word accesses"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: UNALIGN_TRP_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `UNALIGN_TRP` reader - Unaligned accesses generates a Hard Fault"] +pub struct UNALIGN_TRP_R(crate::FieldReader); +impl UNALIGN_TRP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UNALIGN_TRP_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> UNALIGN_TRP_A { + match self.bits { + false => UNALIGN_TRP_A::VALUE_0, + true => UNALIGN_TRP_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == UNALIGN_TRP_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == UNALIGN_TRP_A::VALUE_1 + } +} +impl core::ops::Deref for UNALIGN_TRP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Stack 8-byte aligned on exception entry\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum STKALIGN_A { + #[doc = "0: 4-byte aligned"] + VALUE_0 = 0, + #[doc = "1: 8-byte aligned"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: STKALIGN_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STKALIGN` reader - Stack 8-byte aligned on exception entry"] +pub struct STKALIGN_R(crate::FieldReader); +impl STKALIGN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STKALIGN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STKALIGN_A { + match self.bits { + false => STKALIGN_A::VALUE_0, + true => STKALIGN_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == STKALIGN_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == STKALIGN_A::VALUE_1 + } +} +impl core::ops::Deref for STKALIGN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 3 - Unaligned accesses generates a Hard Fault"] + #[inline(always)] + pub fn unalign_trp(&self) -> UNALIGN_TRP_R { + UNALIGN_TRP_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 9 - Stack 8-byte aligned on exception entry"] + #[inline(always)] + pub fn stkalign(&self) -> STKALIGN_R { + STKALIGN_R::new(((self.bits >> 9) & 0x01) != 0) + } +} +#[doc = "Configuration and Control Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccr](index.html) module"] +pub struct CCR_SPEC; +impl crate::RegisterSpec for CCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ccr::R](R) reader structure"] +impl crate::Readable for CCR_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CCR to value 0x0204"] +impl crate::Resettable for CCR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0204 + } +} diff --git a/pac/atsamc21e/src/system_control/cpuid.rs b/pac/atsamc21e/src/system_control/cpuid.rs new file mode 100644 index 000000000000..4157d7a94e97 --- /dev/null +++ b/pac/atsamc21e/src/system_control/cpuid.rs @@ -0,0 +1,133 @@ +#[doc = "Register `CPUID` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `REVISION` reader - Minor revision number"] +pub struct REVISION_R(crate::FieldReader); +impl REVISION_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REVISION_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REVISION_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PARTNO` reader - Processor Part Number, 0xC60=Cortex-M0+"] +pub struct PARTNO_R(crate::FieldReader); +impl PARTNO_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + PARTNO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PARTNO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ARCHITECTURE` reader - Processor Architecture, 0xC=ARMv6-M"] +pub struct ARCHITECTURE_R(crate::FieldReader); +impl ARCHITECTURE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ARCHITECTURE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ARCHITECTURE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VARIANT` reader - Major revision number"] +pub struct VARIANT_R(crate::FieldReader); +impl VARIANT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + VARIANT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VARIANT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IMPLEMENTER` reader - Implementer code, ARM=0x41"] +pub struct IMPLEMENTER_R(crate::FieldReader); +impl IMPLEMENTER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + IMPLEMENTER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IMPLEMENTER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:3 - Minor revision number"] + #[inline(always)] + pub fn revision(&self) -> REVISION_R { + REVISION_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:15 - Processor Part Number, 0xC60=Cortex-M0+"] + #[inline(always)] + pub fn partno(&self) -> PARTNO_R { + PARTNO_R::new(((self.bits >> 4) & 0x0fff) as u16) + } + #[doc = "Bits 16:19 - Processor Architecture, 0xC=ARMv6-M"] + #[inline(always)] + pub fn architecture(&self) -> ARCHITECTURE_R { + ARCHITECTURE_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bits 20:23 - Major revision number"] + #[inline(always)] + pub fn variant(&self) -> VARIANT_R { + VARIANT_R::new(((self.bits >> 20) & 0x0f) as u8) + } + #[doc = "Bits 24:31 - Implementer code, ARM=0x41"] + #[inline(always)] + pub fn implementer(&self) -> IMPLEMENTER_R { + IMPLEMENTER_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[doc = "CPUID Base Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cpuid](index.html) module"] +pub struct CPUID_SPEC; +impl crate::RegisterSpec for CPUID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cpuid::R](R) reader structure"] +impl crate::Readable for CPUID_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CPUID to value 0x410c_c601"] +impl crate::Resettable for CPUID_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x410c_c601 + } +} diff --git a/pac/atsamc21e/src/system_control/dfsr.rs b/pac/atsamc21e/src/system_control/dfsr.rs new file mode 100644 index 000000000000..948899af0905 --- /dev/null +++ b/pac/atsamc21e/src/system_control/dfsr.rs @@ -0,0 +1,301 @@ +#[doc = "Register `DFSR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DFSR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `HALTED` reader - Halt request debug event active"] +pub struct HALTED_R(crate::FieldReader); +impl HALTED_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HALTED_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HALTED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HALTED` writer - Halt request debug event active"] +pub struct HALTED_W<'a> { + w: &'a mut W, +} +impl<'a> HALTED_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `BKPT` reader - Breakpoint debug event"] +pub struct BKPT_R(crate::FieldReader); +impl BKPT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BKPT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BKPT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BKPT` writer - Breakpoint debug event"] +pub struct BKPT_W<'a> { + w: &'a mut W, +} +impl<'a> BKPT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `DWTTRAP` reader - DWT debug event"] +pub struct DWTTRAP_R(crate::FieldReader); +impl DWTTRAP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DWTTRAP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DWTTRAP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DWTTRAP` writer - DWT debug event"] +pub struct DWTTRAP_W<'a> { + w: &'a mut W, +} +impl<'a> DWTTRAP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `VCATCH` reader - Vector catch debug event"] +pub struct VCATCH_R(crate::FieldReader); +impl VCATCH_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + VCATCH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VCATCH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VCATCH` writer - Vector catch debug event"] +pub struct VCATCH_W<'a> { + w: &'a mut W, +} +impl<'a> VCATCH_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `EXTERNAL` reader - EDBGRQ debug event"] +pub struct EXTERNAL_R(crate::FieldReader); +impl EXTERNAL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTERNAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTERNAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTERNAL` writer - EDBGRQ debug event"] +pub struct EXTERNAL_W<'a> { + w: &'a mut W, +} +impl<'a> EXTERNAL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +impl R { + #[doc = "Bit 0 - Halt request debug event active"] + #[inline(always)] + pub fn halted(&self) -> HALTED_R { + HALTED_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Breakpoint debug event"] + #[inline(always)] + pub fn bkpt(&self) -> BKPT_R { + BKPT_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - DWT debug event"] + #[inline(always)] + pub fn dwttrap(&self) -> DWTTRAP_R { + DWTTRAP_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Vector catch debug event"] + #[inline(always)] + pub fn vcatch(&self) -> VCATCH_R { + VCATCH_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - EDBGRQ debug event"] + #[inline(always)] + pub fn external(&self) -> EXTERNAL_R { + EXTERNAL_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Halt request debug event active"] + #[inline(always)] + pub fn halted(&mut self) -> HALTED_W { + HALTED_W { w: self } + } + #[doc = "Bit 1 - Breakpoint debug event"] + #[inline(always)] + pub fn bkpt(&mut self) -> BKPT_W { + BKPT_W { w: self } + } + #[doc = "Bit 2 - DWT debug event"] + #[inline(always)] + pub fn dwttrap(&mut self) -> DWTTRAP_W { + DWTTRAP_W { w: self } + } + #[doc = "Bit 3 - Vector catch debug event"] + #[inline(always)] + pub fn vcatch(&mut self) -> VCATCH_W { + VCATCH_W { w: self } + } + #[doc = "Bit 4 - EDBGRQ debug event"] + #[inline(always)] + pub fn external(&mut self) -> EXTERNAL_W { + EXTERNAL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Fault Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dfsr](index.html) module"] +pub struct DFSR_SPEC; +impl crate::RegisterSpec for DFSR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dfsr::R](R) reader structure"] +impl crate::Readable for DFSR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dfsr::W](W) writer structure"] +impl crate::Writable for DFSR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DFSR to value 0"] +impl crate::Resettable for DFSR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/system_control/icsr.rs b/pac/atsamc21e/src/system_control/icsr.rs new file mode 100644 index 000000000000..7fe5fd412116 --- /dev/null +++ b/pac/atsamc21e/src/system_control/icsr.rs @@ -0,0 +1,704 @@ +#[doc = "Register `ICSR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ICSR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `VECTACTIVE` reader - Debug: Exception number of currently executing exception, or 0 if thread mode"] +pub struct VECTACTIVE_R(crate::FieldReader); +impl VECTACTIVE_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + VECTACTIVE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VECTACTIVE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VECTACTIVE` writer - Debug: Exception number of currently executing exception, or 0 if thread mode"] +pub struct VECTACTIVE_W<'a> { + w: &'a mut W, +} +impl<'a> VECTACTIVE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01ff) | (value as u32 & 0x01ff); + self.w + } +} +#[doc = "Field `VECTPENDING` reader - Exception number of the highest priority pending enabled exception"] +pub struct VECTPENDING_R(crate::FieldReader); +impl VECTPENDING_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + VECTPENDING_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VECTPENDING_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VECTPENDING` writer - Exception number of the highest priority pending enabled exception"] +pub struct VECTPENDING_W<'a> { + w: &'a mut W, +} +impl<'a> VECTPENDING_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01ff << 12)) | ((value as u32 & 0x01ff) << 12); + self.w + } +} +#[doc = "Field `ISRPENDING` reader - Debug: NVIC interrupt pending"] +pub struct ISRPENDING_R(crate::FieldReader); +impl ISRPENDING_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ISRPENDING_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ISRPENDING_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ISRPENDING` writer - Debug: NVIC interrupt pending"] +pub struct ISRPENDING_W<'a> { + w: &'a mut W, +} +impl<'a> ISRPENDING_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `ISRPREEMPT` reader - Debug: Pending exception serviced on exit from debug halt"] +pub struct ISRPREEMPT_R(crate::FieldReader); +impl ISRPREEMPT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ISRPREEMPT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ISRPREEMPT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ISRPREEMPT` writer - Debug: Pending exception serviced on exit from debug halt"] +pub struct ISRPREEMPT_W<'a> { + w: &'a mut W, +} +impl<'a> ISRPREEMPT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "SysTick exception clear-pending bit\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PENDSTCLR_A { + #[doc = "0: No effect"] + VALUE_0 = 0, + #[doc = "1: Removes the pending state from the SysTick exception"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PENDSTCLR_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PENDSTCLR` reader - SysTick exception clear-pending bit"] +pub struct PENDSTCLR_R(crate::FieldReader); +impl PENDSTCLR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDSTCLR_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PENDSTCLR_A { + match self.bits { + false => PENDSTCLR_A::VALUE_0, + true => PENDSTCLR_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == PENDSTCLR_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == PENDSTCLR_A::VALUE_1 + } +} +impl core::ops::Deref for PENDSTCLR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDSTCLR` writer - SysTick exception clear-pending bit"] +pub struct PENDSTCLR_W<'a> { + w: &'a mut W, +} +impl<'a> PENDSTCLR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PENDSTCLR_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "No effect"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(PENDSTCLR_A::VALUE_0) + } + #[doc = "Removes the pending state from the SysTick exception"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(PENDSTCLR_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "SysTick exception set-pending bit\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PENDSTSET_A { + #[doc = "0: Write: no effect; read: SysTick exception is not pending"] + VALUE_0 = 0, + #[doc = "1: Write: changes SysTick exception state to pending; read: SysTick exception is pending"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PENDSTSET_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PENDSTSET` reader - SysTick exception set-pending bit"] +pub struct PENDSTSET_R(crate::FieldReader); +impl PENDSTSET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDSTSET_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PENDSTSET_A { + match self.bits { + false => PENDSTSET_A::VALUE_0, + true => PENDSTSET_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == PENDSTSET_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == PENDSTSET_A::VALUE_1 + } +} +impl core::ops::Deref for PENDSTSET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDSTSET` writer - SysTick exception set-pending bit"] +pub struct PENDSTSET_W<'a> { + w: &'a mut W, +} +impl<'a> PENDSTSET_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PENDSTSET_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Write: no effect; read: SysTick exception is not pending"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(PENDSTSET_A::VALUE_0) + } + #[doc = "Write: changes SysTick exception state to pending; read: SysTick exception is pending"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(PENDSTSET_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "PendSV clear-pending bit\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PENDSVCLR_A { + #[doc = "0: No effect"] + VALUE_0 = 0, + #[doc = "1: Removes the pending state from the PendSV exception"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PENDSVCLR_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PENDSVCLR` reader - PendSV clear-pending bit"] +pub struct PENDSVCLR_R(crate::FieldReader); +impl PENDSVCLR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDSVCLR_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PENDSVCLR_A { + match self.bits { + false => PENDSVCLR_A::VALUE_0, + true => PENDSVCLR_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == PENDSVCLR_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == PENDSVCLR_A::VALUE_1 + } +} +impl core::ops::Deref for PENDSVCLR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDSVCLR` writer - PendSV clear-pending bit"] +pub struct PENDSVCLR_W<'a> { + w: &'a mut W, +} +impl<'a> PENDSVCLR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PENDSVCLR_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "No effect"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(PENDSVCLR_A::VALUE_0) + } + #[doc = "Removes the pending state from the PendSV exception"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(PENDSVCLR_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +#[doc = "PendSV set-pending bit\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PENDSVSET_A { + #[doc = "0: Write: no effect; read: PendSV exception is not pending"] + VALUE_0 = 0, + #[doc = "1: Write: changes PendSV exception state to pending; read: PendSV exception is pending"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PENDSVSET_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PENDSVSET` reader - PendSV set-pending bit"] +pub struct PENDSVSET_R(crate::FieldReader); +impl PENDSVSET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDSVSET_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PENDSVSET_A { + match self.bits { + false => PENDSVSET_A::VALUE_0, + true => PENDSVSET_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == PENDSVSET_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == PENDSVSET_A::VALUE_1 + } +} +impl core::ops::Deref for PENDSVSET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDSVSET` writer - PendSV set-pending bit"] +pub struct PENDSVSET_W<'a> { + w: &'a mut W, +} +impl<'a> PENDSVSET_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PENDSVSET_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Write: no effect; read: PendSV exception is not pending"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(PENDSVSET_A::VALUE_0) + } + #[doc = "Write: changes PendSV exception state to pending; read: PendSV exception is pending"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(PENDSVSET_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "NMI set-pending bit\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum NMIPENDSET_A { + #[doc = "0: Write: no effect; read: NMI exception is not pending"] + VALUE_0 = 0, + #[doc = "1: Write: changes NMI exception state to pending; read: NMI exception is pending"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NMIPENDSET_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NMIPENDSET` reader - NMI set-pending bit"] +pub struct NMIPENDSET_R(crate::FieldReader); +impl NMIPENDSET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NMIPENDSET_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> NMIPENDSET_A { + match self.bits { + false => NMIPENDSET_A::VALUE_0, + true => NMIPENDSET_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == NMIPENDSET_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == NMIPENDSET_A::VALUE_1 + } +} +impl core::ops::Deref for NMIPENDSET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NMIPENDSET` writer - NMI set-pending bit"] +pub struct NMIPENDSET_W<'a> { + w: &'a mut W, +} +impl<'a> NMIPENDSET_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: NMIPENDSET_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Write: no effect; read: NMI exception is not pending"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(NMIPENDSET_A::VALUE_0) + } + #[doc = "Write: changes NMI exception state to pending; read: NMI exception is pending"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(NMIPENDSET_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bits 0:8 - Debug: Exception number of currently executing exception, or 0 if thread mode"] + #[inline(always)] + pub fn vectactive(&self) -> VECTACTIVE_R { + VECTACTIVE_R::new((self.bits & 0x01ff) as u16) + } + #[doc = "Bits 12:20 - Exception number of the highest priority pending enabled exception"] + #[inline(always)] + pub fn vectpending(&self) -> VECTPENDING_R { + VECTPENDING_R::new(((self.bits >> 12) & 0x01ff) as u16) + } + #[doc = "Bit 22 - Debug: NVIC interrupt pending"] + #[inline(always)] + pub fn isrpending(&self) -> ISRPENDING_R { + ISRPENDING_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Debug: Pending exception serviced on exit from debug halt"] + #[inline(always)] + pub fn isrpreempt(&self) -> ISRPREEMPT_R { + ISRPREEMPT_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 25 - SysTick exception clear-pending bit"] + #[inline(always)] + pub fn pendstclr(&self) -> PENDSTCLR_R { + PENDSTCLR_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - SysTick exception set-pending bit"] + #[inline(always)] + pub fn pendstset(&self) -> PENDSTSET_R { + PENDSTSET_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - PendSV clear-pending bit"] + #[inline(always)] + pub fn pendsvclr(&self) -> PENDSVCLR_R { + PENDSVCLR_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28 - PendSV set-pending bit"] + #[inline(always)] + pub fn pendsvset(&self) -> PENDSVSET_R { + PENDSVSET_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 31 - NMI set-pending bit"] + #[inline(always)] + pub fn nmipendset(&self) -> NMIPENDSET_R { + NMIPENDSET_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:8 - Debug: Exception number of currently executing exception, or 0 if thread mode"] + #[inline(always)] + pub fn vectactive(&mut self) -> VECTACTIVE_W { + VECTACTIVE_W { w: self } + } + #[doc = "Bits 12:20 - Exception number of the highest priority pending enabled exception"] + #[inline(always)] + pub fn vectpending(&mut self) -> VECTPENDING_W { + VECTPENDING_W { w: self } + } + #[doc = "Bit 22 - Debug: NVIC interrupt pending"] + #[inline(always)] + pub fn isrpending(&mut self) -> ISRPENDING_W { + ISRPENDING_W { w: self } + } + #[doc = "Bit 23 - Debug: Pending exception serviced on exit from debug halt"] + #[inline(always)] + pub fn isrpreempt(&mut self) -> ISRPREEMPT_W { + ISRPREEMPT_W { w: self } + } + #[doc = "Bit 25 - SysTick exception clear-pending bit"] + #[inline(always)] + pub fn pendstclr(&mut self) -> PENDSTCLR_W { + PENDSTCLR_W { w: self } + } + #[doc = "Bit 26 - SysTick exception set-pending bit"] + #[inline(always)] + pub fn pendstset(&mut self) -> PENDSTSET_W { + PENDSTSET_W { w: self } + } + #[doc = "Bit 27 - PendSV clear-pending bit"] + #[inline(always)] + pub fn pendsvclr(&mut self) -> PENDSVCLR_W { + PENDSVCLR_W { w: self } + } + #[doc = "Bit 28 - PendSV set-pending bit"] + #[inline(always)] + pub fn pendsvset(&mut self) -> PENDSVSET_W { + PENDSVSET_W { w: self } + } + #[doc = "Bit 31 - NMI set-pending bit"] + #[inline(always)] + pub fn nmipendset(&mut self) -> NMIPENDSET_W { + NMIPENDSET_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Control and State Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [icsr](index.html) module"] +pub struct ICSR_SPEC; +impl crate::RegisterSpec for ICSR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [icsr::R](R) reader structure"] +impl crate::Readable for ICSR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [icsr::W](W) writer structure"] +impl crate::Writable for ICSR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ICSR to value 0"] +impl crate::Resettable for ICSR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/system_control/scr.rs b/pac/atsamc21e/src/system_control/scr.rs new file mode 100644 index 000000000000..db9c54fe6f6f --- /dev/null +++ b/pac/atsamc21e/src/system_control/scr.rs @@ -0,0 +1,348 @@ +#[doc = "Register `SCR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SCR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Sleep-On-Exit when exiting Handler mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SLEEPONEXIT_A { + #[doc = "0: O not sleep when returning to Thread mode"] + VALUE_0 = 0, + #[doc = "1: Enter sleep, or deep sleep, on return from an ISR"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SLEEPONEXIT_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SLEEPONEXIT` reader - Sleep-On-Exit when exiting Handler mode"] +pub struct SLEEPONEXIT_R(crate::FieldReader); +impl SLEEPONEXIT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLEEPONEXIT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SLEEPONEXIT_A { + match self.bits { + false => SLEEPONEXIT_A::VALUE_0, + true => SLEEPONEXIT_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == SLEEPONEXIT_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == SLEEPONEXIT_A::VALUE_1 + } +} +impl core::ops::Deref for SLEEPONEXIT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLEEPONEXIT` writer - Sleep-On-Exit when exiting Handler mode"] +pub struct SLEEPONEXIT_W<'a> { + w: &'a mut W, +} +impl<'a> SLEEPONEXIT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SLEEPONEXIT_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "O not sleep when returning to Thread mode"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(SLEEPONEXIT_A::VALUE_0) + } + #[doc = "Enter sleep, or deep sleep, on return from an ISR"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(SLEEPONEXIT_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Uses Deep Sleep as low power mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SLEEPDEEP_A { + #[doc = "0: Sleep"] + VALUE_0 = 0, + #[doc = "1: Deep sleep"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SLEEPDEEP_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SLEEPDEEP` reader - Uses Deep Sleep as low power mode"] +pub struct SLEEPDEEP_R(crate::FieldReader); +impl SLEEPDEEP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLEEPDEEP_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SLEEPDEEP_A { + match self.bits { + false => SLEEPDEEP_A::VALUE_0, + true => SLEEPDEEP_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == SLEEPDEEP_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == SLEEPDEEP_A::VALUE_1 + } +} +impl core::ops::Deref for SLEEPDEEP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLEEPDEEP` writer - Uses Deep Sleep as low power mode"] +pub struct SLEEPDEEP_W<'a> { + w: &'a mut W, +} +impl<'a> SLEEPDEEP_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SLEEPDEEP_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Sleep"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(SLEEPDEEP_A::VALUE_0) + } + #[doc = "Deep sleep"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(SLEEPDEEP_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Send Event on Pending bit\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SEVONPEND_A { + #[doc = "0: Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded"] + VALUE_0 = 0, + #[doc = "1: Enabled events and all interrupts, including disabled interrupts, can wakeup the processor"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SEVONPEND_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SEVONPEND` reader - Send Event on Pending bit"] +pub struct SEVONPEND_R(crate::FieldReader); +impl SEVONPEND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SEVONPEND_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SEVONPEND_A { + match self.bits { + false => SEVONPEND_A::VALUE_0, + true => SEVONPEND_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == SEVONPEND_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == SEVONPEND_A::VALUE_1 + } +} +impl core::ops::Deref for SEVONPEND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEVONPEND` writer - Send Event on Pending bit"] +pub struct SEVONPEND_W<'a> { + w: &'a mut W, +} +impl<'a> SEVONPEND_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SEVONPEND_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(SEVONPEND_A::VALUE_0) + } + #[doc = "Enabled events and all interrupts, including disabled interrupts, can wakeup the processor"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(SEVONPEND_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +impl R { + #[doc = "Bit 1 - Sleep-On-Exit when exiting Handler mode"] + #[inline(always)] + pub fn sleeponexit(&self) -> SLEEPONEXIT_R { + SLEEPONEXIT_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Uses Deep Sleep as low power mode"] + #[inline(always)] + pub fn sleepdeep(&self) -> SLEEPDEEP_R { + SLEEPDEEP_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 4 - Send Event on Pending bit"] + #[inline(always)] + pub fn sevonpend(&self) -> SEVONPEND_R { + SEVONPEND_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 1 - Sleep-On-Exit when exiting Handler mode"] + #[inline(always)] + pub fn sleeponexit(&mut self) -> SLEEPONEXIT_W { + SLEEPONEXIT_W { w: self } + } + #[doc = "Bit 2 - Uses Deep Sleep as low power mode"] + #[inline(always)] + pub fn sleepdeep(&mut self) -> SLEEPDEEP_W { + SLEEPDEEP_W { w: self } + } + #[doc = "Bit 4 - Send Event on Pending bit"] + #[inline(always)] + pub fn sevonpend(&mut self) -> SEVONPEND_W { + SEVONPEND_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "System Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [scr](index.html) module"] +pub struct SCR_SPEC; +impl crate::RegisterSpec for SCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [scr::R](R) reader structure"] +impl crate::Readable for SCR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [scr::W](W) writer structure"] +impl crate::Writable for SCR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SCR to value 0"] +impl crate::Resettable for SCR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/system_control/shcsr.rs b/pac/atsamc21e/src/system_control/shcsr.rs new file mode 100644 index 000000000000..bfba26ac06ad --- /dev/null +++ b/pac/atsamc21e/src/system_control/shcsr.rs @@ -0,0 +1,113 @@ +#[doc = "Register `SHCSR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SHCSR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SVCALLPENDED` reader - "] +pub struct SVCALLPENDED_R(crate::FieldReader); +impl SVCALLPENDED_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SVCALLPENDED_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SVCALLPENDED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SVCALLPENDED` writer - "] +pub struct SVCALLPENDED_W<'a> { + w: &'a mut W, +} +impl<'a> SVCALLPENDED_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 15"] + #[inline(always)] + pub fn svcallpended(&self) -> SVCALLPENDED_R { + SVCALLPENDED_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 15"] + #[inline(always)] + pub fn svcallpended(&mut self) -> SVCALLPENDED_W { + SVCALLPENDED_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "System Handler Control and State Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [shcsr](index.html) module"] +pub struct SHCSR_SPEC; +impl crate::RegisterSpec for SHCSR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [shcsr::R](R) reader structure"] +impl crate::Readable for SHCSR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [shcsr::W](W) writer structure"] +impl crate::Writable for SHCSR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SHCSR to value 0"] +impl crate::Resettable for SHCSR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/system_control/shpr2.rs b/pac/atsamc21e/src/system_control/shpr2.rs new file mode 100644 index 000000000000..5665d6a5e8a9 --- /dev/null +++ b/pac/atsamc21e/src/system_control/shpr2.rs @@ -0,0 +1,103 @@ +#[doc = "Register `SHPR2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SHPR2` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PRI_11` reader - Priority of system handler 11, SVCall"] +pub struct PRI_11_R(crate::FieldReader); +impl PRI_11_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRI_11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PRI_11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRI_11` writer - Priority of system handler 11, SVCall"] +pub struct PRI_11_W<'a> { + w: &'a mut W, +} +impl<'a> PRI_11_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 24)) | ((value as u32 & 0xff) << 24); + self.w + } +} +impl R { + #[doc = "Bits 24:31 - Priority of system handler 11, SVCall"] + #[inline(always)] + pub fn pri_11(&self) -> PRI_11_R { + PRI_11_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 24:31 - Priority of system handler 11, SVCall"] + #[inline(always)] + pub fn pri_11(&mut self) -> PRI_11_W { + PRI_11_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "System Handler Priority Register 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [shpr2](index.html) module"] +pub struct SHPR2_SPEC; +impl crate::RegisterSpec for SHPR2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [shpr2::R](R) reader structure"] +impl crate::Readable for SHPR2_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [shpr2::W](W) writer structure"] +impl crate::Writable for SHPR2_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SHPR2 to value 0"] +impl crate::Resettable for SHPR2_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/system_control/shpr3.rs b/pac/atsamc21e/src/system_control/shpr3.rs new file mode 100644 index 000000000000..cb5a92c53503 --- /dev/null +++ b/pac/atsamc21e/src/system_control/shpr3.rs @@ -0,0 +1,140 @@ +#[doc = "Register `SHPR3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SHPR3` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PRI_14` reader - Priority of system handler 14, PendSV"] +pub struct PRI_14_R(crate::FieldReader); +impl PRI_14_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRI_14_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PRI_14_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRI_14` writer - Priority of system handler 14, PendSV"] +pub struct PRI_14_W<'a> { + w: &'a mut W, +} +impl<'a> PRI_14_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +#[doc = "Field `PRI_15` reader - Priority of system handler 15, SysTick exception"] +pub struct PRI_15_R(crate::FieldReader); +impl PRI_15_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRI_15_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PRI_15_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRI_15` writer - Priority of system handler 15, SysTick exception"] +pub struct PRI_15_W<'a> { + w: &'a mut W, +} +impl<'a> PRI_15_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 24)) | ((value as u32 & 0xff) << 24); + self.w + } +} +impl R { + #[doc = "Bits 16:23 - Priority of system handler 14, PendSV"] + #[inline(always)] + pub fn pri_14(&self) -> PRI_14_R { + PRI_14_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Priority of system handler 15, SysTick exception"] + #[inline(always)] + pub fn pri_15(&self) -> PRI_15_R { + PRI_15_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 16:23 - Priority of system handler 14, PendSV"] + #[inline(always)] + pub fn pri_14(&mut self) -> PRI_14_W { + PRI_14_W { w: self } + } + #[doc = "Bits 24:31 - Priority of system handler 15, SysTick exception"] + #[inline(always)] + pub fn pri_15(&mut self) -> PRI_15_W { + PRI_15_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "System Handler Priority Register 3\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [shpr3](index.html) module"] +pub struct SHPR3_SPEC; +impl crate::RegisterSpec for SHPR3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [shpr3::R](R) reader structure"] +impl crate::Readable for SHPR3_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [shpr3::W](W) writer structure"] +impl crate::Writable for SHPR3_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SHPR3 to value 0"] +impl crate::Resettable for SHPR3_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/system_control/vtor.rs b/pac/atsamc21e/src/system_control/vtor.rs new file mode 100644 index 000000000000..0ee4c7817817 --- /dev/null +++ b/pac/atsamc21e/src/system_control/vtor.rs @@ -0,0 +1,103 @@ +#[doc = "Register `VTOR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `VTOR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TBLOFF` reader - Vector table base offset"] +pub struct TBLOFF_R(crate::FieldReader); +impl TBLOFF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + TBLOFF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TBLOFF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TBLOFF` writer - Vector table base offset"] +pub struct TBLOFF_W<'a> { + w: &'a mut W, +} +impl<'a> TBLOFF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01ff_ffff << 7)) | ((value as u32 & 0x01ff_ffff) << 7); + self.w + } +} +impl R { + #[doc = "Bits 7:31 - Vector table base offset"] + #[inline(always)] + pub fn tbloff(&self) -> TBLOFF_R { + TBLOFF_R::new(((self.bits >> 7) & 0x01ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 7:31 - Vector table base offset"] + #[inline(always)] + pub fn tbloff(&mut self) -> TBLOFF_W { + TBLOFF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Vector Table Offset Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [vtor](index.html) module"] +pub struct VTOR_SPEC; +impl crate::RegisterSpec for VTOR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [vtor::R](R) reader structure"] +impl crate::Readable for VTOR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [vtor::W](W) writer structure"] +impl crate::Writable for VTOR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets VTOR to value 0"] +impl crate::Resettable for VTOR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/tc0.rs b/pac/atsamc21e/src/tc0.rs new file mode 100644 index 000000000000..86e973b276e7 --- /dev/null +++ b/pac/atsamc21e/src/tc0.rs @@ -0,0 +1,146 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved_0_count8: [u8; 0x38], +} +impl RegisterBlock { + #[doc = "0x00..0x38 - 32-bit Counter Mode"] + #[inline(always)] + pub fn count32(&self) -> &COUNT32 { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const COUNT32) } + } + #[doc = "0x00..0x34 - 16-bit Counter Mode"] + #[inline(always)] + pub fn count16(&self) -> &COUNT16 { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const COUNT16) } + } + #[doc = "0x00..0x32 - 8-bit Counter Mode"] + #[inline(always)] + pub fn count8(&self) -> &COUNT8 { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const COUNT8) } + } +} +#[doc = r"Register block"] +#[repr(C)] +pub struct COUNT8 { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - Control B Clear"] + pub ctrlbclr: crate::Reg, + #[doc = "0x05 - Control B Set"] + pub ctrlbset: crate::Reg, + #[doc = "0x06 - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x08 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x09 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x0a - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x0b - Status"] + pub status: crate::Reg, + #[doc = "0x0c - Waveform Generation Control"] + pub wave: crate::Reg, + #[doc = "0x0d - Control C"] + pub drvctrl: crate::Reg, + _reserved10: [u8; 0x01], + #[doc = "0x0f - Debug Control"] + pub dbgctrl: crate::Reg, + #[doc = "0x10 - Synchronization Status"] + pub syncbusy: crate::Reg, + #[doc = "0x14 - COUNT8 Count"] + pub count: crate::Reg, + _reserved13: [u8; 0x06], + #[doc = "0x1b - COUNT8 Period"] + pub per: crate::Reg, + #[doc = "0x1c - COUNT8 Compare and Capture"] + pub cc: [crate::Reg; 2], + _reserved15: [u8; 0x11], + #[doc = "0x2f - COUNT8 Period Buffer"] + pub perbuf: crate::Reg, + #[doc = "0x30 - COUNT8 Compare and Capture Buffer"] + pub ccbuf: [crate::Reg; 2], +} +#[doc = r"Register block"] +#[doc = "8-bit Counter Mode"] +pub mod count8; +#[doc = r"Register block"] +#[repr(C)] +pub struct COUNT16 { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - Control B Clear"] + pub ctrlbclr: crate::Reg, + #[doc = "0x05 - Control B Set"] + pub ctrlbset: crate::Reg, + #[doc = "0x06 - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x08 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x09 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x0a - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x0b - Status"] + pub status: crate::Reg, + #[doc = "0x0c - Waveform Generation Control"] + pub wave: crate::Reg, + #[doc = "0x0d - Control C"] + pub drvctrl: crate::Reg, + _reserved10: [u8; 0x01], + #[doc = "0x0f - Debug Control"] + pub dbgctrl: crate::Reg, + #[doc = "0x10 - Synchronization Status"] + pub syncbusy: crate::Reg, + #[doc = "0x14 - COUNT16 Count"] + pub count: crate::Reg, + _reserved13: [u8; 0x06], + #[doc = "0x1c - COUNT16 Compare and Capture"] + pub cc: [crate::Reg; 2], + _reserved14: [u8; 0x10], + #[doc = "0x30 - COUNT16 Compare and Capture Buffer"] + pub ccbuf: [crate::Reg; 2], +} +#[doc = r"Register block"] +#[doc = "16-bit Counter Mode"] +pub mod count16; +#[doc = r"Register block"] +#[repr(C)] +pub struct COUNT32 { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - Control B Clear"] + pub ctrlbclr: crate::Reg, + #[doc = "0x05 - Control B Set"] + pub ctrlbset: crate::Reg, + #[doc = "0x06 - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x08 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x09 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x0a - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x0b - Status"] + pub status: crate::Reg, + #[doc = "0x0c - Waveform Generation Control"] + pub wave: crate::Reg, + #[doc = "0x0d - Control C"] + pub drvctrl: crate::Reg, + _reserved10: [u8; 0x01], + #[doc = "0x0f - Debug Control"] + pub dbgctrl: crate::Reg, + #[doc = "0x10 - Synchronization Status"] + pub syncbusy: crate::Reg, + #[doc = "0x14 - COUNT32 Count"] + pub count: crate::Reg, + _reserved13: [u8; 0x04], + #[doc = "0x1c..0x24 - COUNT32 Compare and Capture"] + pub cc: [crate::Reg; 2], + _reserved14: [u8; 0x0c], + #[doc = "0x30..0x38 - COUNT32 Compare and Capture Buffer"] + pub ccbuf: [crate::Reg; 2], +} +#[doc = r"Register block"] +#[doc = "32-bit Counter Mode"] +pub mod count32; diff --git a/pac/atsamc21e/src/tc0/count16.rs b/pac/atsamc21e/src/tc0/count16.rs new file mode 100644 index 000000000000..5bd1e88c7efb --- /dev/null +++ b/pac/atsamc21e/src/tc0/count16.rs @@ -0,0 +1,60 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "CTRLBCLR register accessor: an alias for `Reg`"] +pub type CTRLBCLR = crate::Reg; +#[doc = "Control B Clear"] +pub mod ctrlbclr; +#[doc = "CTRLBSET register accessor: an alias for `Reg`"] +pub type CTRLBSET = crate::Reg; +#[doc = "Control B Set"] +pub mod ctrlbset; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "WAVE register accessor: an alias for `Reg`"] +pub type WAVE = crate::Reg; +#[doc = "Waveform Generation Control"] +pub mod wave; +#[doc = "DRVCTRL register accessor: an alias for `Reg`"] +pub type DRVCTRL = crate::Reg; +#[doc = "Control C"] +pub mod drvctrl; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Status"] +pub mod syncbusy; +#[doc = "COUNT register accessor: an alias for `Reg`"] +pub type COUNT = crate::Reg; +#[doc = "COUNT16 Count"] +pub mod count; +#[doc = "CC register accessor: an alias for `Reg`"] +pub type CC = crate::Reg; +#[doc = "COUNT16 Compare and Capture"] +pub mod cc; +#[doc = "CCBUF register accessor: an alias for `Reg`"] +pub type CCBUF = crate::Reg; +#[doc = "COUNT16 Compare and Capture Buffer"] +pub mod ccbuf; diff --git a/pac/atsamc21e/src/tc0/count16/cc.rs b/pac/atsamc21e/src/tc0/count16/cc.rs new file mode 100644 index 000000000000..b6f975905e31 --- /dev/null +++ b/pac/atsamc21e/src/tc0/count16/cc.rs @@ -0,0 +1,104 @@ +#[doc = "Register `CC[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CC[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CC` reader - Counter/Compare Value"] +pub struct CC_R(crate::FieldReader); +impl CC_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + CC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC` writer - Counter/Compare Value"] +pub struct CC_W<'a> { + w: &'a mut W, +} +impl<'a> CC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Counter/Compare Value"] + #[inline(always)] + pub fn cc(&self) -> CC_R { + CC_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Counter/Compare Value"] + #[inline(always)] + pub fn cc(&mut self) -> CC_W { + CC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT16 Compare and Capture\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc](index.html) module"] +pub struct CC_SPEC; +impl crate::RegisterSpec for CC_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [cc::R](R) reader structure"] +impl crate::Readable for CC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cc::W](W) writer structure"] +impl crate::Writable for CC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CC[%s] +to value 0"] +impl crate::Resettable for CC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/tc0/count16/ccbuf.rs b/pac/atsamc21e/src/tc0/count16/ccbuf.rs new file mode 100644 index 000000000000..2f922bba8d31 --- /dev/null +++ b/pac/atsamc21e/src/tc0/count16/ccbuf.rs @@ -0,0 +1,104 @@ +#[doc = "Register `CCBUF[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CCBUF[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CCBUF` reader - Counter/Compare Buffer Value"] +pub struct CCBUF_R(crate::FieldReader); +impl CCBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + CCBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUF` writer - Counter/Compare Buffer Value"] +pub struct CCBUF_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Counter/Compare Buffer Value"] + #[inline(always)] + pub fn ccbuf(&self) -> CCBUF_R { + CCBUF_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Counter/Compare Buffer Value"] + #[inline(always)] + pub fn ccbuf(&mut self) -> CCBUF_W { + CCBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT16 Compare and Capture Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccbuf](index.html) module"] +pub struct CCBUF_SPEC; +impl crate::RegisterSpec for CCBUF_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ccbuf::R](R) reader structure"] +impl crate::Readable for CCBUF_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ccbuf::W](W) writer structure"] +impl crate::Writable for CCBUF_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CCBUF[%s] +to value 0"] +impl crate::Resettable for CCBUF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/tc0/count16/count.rs b/pac/atsamc21e/src/tc0/count16/count.rs new file mode 100644 index 000000000000..5d26b509abb1 --- /dev/null +++ b/pac/atsamc21e/src/tc0/count16/count.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT16 Count\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count](index.html) module"] +pub struct COUNT_SPEC; +impl crate::RegisterSpec for COUNT_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [count::R](R) reader structure"] +impl crate::Readable for COUNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count::W](W) writer structure"] +impl crate::Writable for COUNT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT to value 0"] +impl crate::Resettable for COUNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/tc0/count16/ctrla.rs b/pac/atsamc21e/src/tc0/count16/ctrla.rs new file mode 100644 index 000000000000..cadcddaaead8 --- /dev/null +++ b/pac/atsamc21e/src/tc0/count16/ctrla.rs @@ -0,0 +1,851 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Timer Counter Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: Counter in 16-bit mode"] + COUNT16 = 0, + #[doc = "1: Counter in 8-bit mode"] + COUNT8 = 1, + #[doc = "2: Counter in 32-bit mode"] + COUNT32 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Timer Counter Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::COUNT16), + 1 => Some(MODE_A::COUNT8), + 2 => Some(MODE_A::COUNT32), + _ => None, + } + } + #[doc = "Checks if the value of the field is `COUNT16`"] + #[inline(always)] + pub fn is_count16(&self) -> bool { + **self == MODE_A::COUNT16 + } + #[doc = "Checks if the value of the field is `COUNT8`"] + #[inline(always)] + pub fn is_count8(&self) -> bool { + **self == MODE_A::COUNT8 + } + #[doc = "Checks if the value of the field is `COUNT32`"] + #[inline(always)] + pub fn is_count32(&self) -> bool { + **self == MODE_A::COUNT32 + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Timer Counter Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Counter in 16-bit mode"] + #[inline(always)] + pub fn count16(self) -> &'a mut W { + self.variant(MODE_A::COUNT16) + } + #[doc = "Counter in 8-bit mode"] + #[inline(always)] + pub fn count8(self) -> &'a mut W { + self.variant(MODE_A::COUNT8) + } + #[doc = "Counter in 32-bit mode"] + #[inline(always)] + pub fn count32(self) -> &'a mut W { + self.variant(MODE_A::COUNT32) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u32 & 0x03) << 2); + self.w + } +} +#[doc = "Prescaler and Counter Synchronization\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCSYNC_A { + #[doc = "0: Reload or reset the counter on next generic clock"] + GCLK = 0, + #[doc = "1: Reload or reset the counter on next prescaler clock"] + PRESC = 1, + #[doc = "2: Reload or reset the counter on next generic clock and reset the prescaler counter"] + RESYNC = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCSYNC_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCSYNC` reader - Prescaler and Counter Synchronization"] +pub struct PRESCSYNC_R(crate::FieldReader); +impl PRESCSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCSYNC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCSYNC_A::GCLK), + 1 => Some(PRESCSYNC_A::PRESC), + 2 => Some(PRESCSYNC_A::RESYNC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `GCLK`"] + #[inline(always)] + pub fn is_gclk(&self) -> bool { + **self == PRESCSYNC_A::GCLK + } + #[doc = "Checks if the value of the field is `PRESC`"] + #[inline(always)] + pub fn is_presc(&self) -> bool { + **self == PRESCSYNC_A::PRESC + } + #[doc = "Checks if the value of the field is `RESYNC`"] + #[inline(always)] + pub fn is_resync(&self) -> bool { + **self == PRESCSYNC_A::RESYNC + } +} +impl core::ops::Deref for PRESCSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCSYNC` writer - Prescaler and Counter Synchronization"] +pub struct PRESCSYNC_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCSYNC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCSYNC_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Reload or reset the counter on next generic clock"] + #[inline(always)] + pub fn gclk(self) -> &'a mut W { + self.variant(PRESCSYNC_A::GCLK) + } + #[doc = "Reload or reset the counter on next prescaler clock"] + #[inline(always)] + pub fn presc(self) -> &'a mut W { + self.variant(PRESCSYNC_A::PRESC) + } + #[doc = "Reload or reset the counter on next generic clock and reset the prescaler counter"] + #[inline(always)] + pub fn resync(self) -> &'a mut W { + self.variant(PRESCSYNC_A::RESYNC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u32 & 0x03) << 4); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - Clock On Demand"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - Clock On Demand"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: Prescaler: GCLK_TC"] + DIV1 = 0, + #[doc = "1: Prescaler: GCLK_TC/2"] + DIV2 = 1, + #[doc = "2: Prescaler: GCLK_TC/4"] + DIV4 = 2, + #[doc = "3: Prescaler: GCLK_TC/8"] + DIV8 = 3, + #[doc = "4: Prescaler: GCLK_TC/16"] + DIV16 = 4, + #[doc = "5: Prescaler: GCLK_TC/64"] + DIV64 = 5, + #[doc = "6: Prescaler: GCLK_TC/256"] + DIV256 = 6, + #[doc = "7: Prescaler: GCLK_TC/1024"] + DIV1024 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PRESCALER_A { + match self.bits { + 0 => PRESCALER_A::DIV1, + 1 => PRESCALER_A::DIV2, + 2 => PRESCALER_A::DIV4, + 3 => PRESCALER_A::DIV8, + 4 => PRESCALER_A::DIV16, + 5 => PRESCALER_A::DIV64, + 6 => PRESCALER_A::DIV256, + 7 => PRESCALER_A::DIV1024, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == PRESCALER_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PRESCALER_A::DIV1024 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Prescaler: GCLK_TC"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1) + } + #[doc = "Prescaler: GCLK_TC/2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "Prescaler: GCLK_TC/4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "Prescaler: GCLK_TC/8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "Prescaler: GCLK_TC/16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "Prescaler: GCLK_TC/64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "Prescaler: GCLK_TC/256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = "Prescaler: GCLK_TC/1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +#[doc = "Field `ALOCK` reader - Auto Lock"] +pub struct ALOCK_R(crate::FieldReader); +impl ALOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALOCK` writer - Auto Lock"] +pub struct ALOCK_W<'a> { + w: &'a mut W, +} +impl<'a> ALOCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `CAPTEN0` reader - Capture Channel 0 Enable"] +pub struct CAPTEN0_R(crate::FieldReader); +impl CAPTEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CAPTEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CAPTEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAPTEN0` writer - Capture Channel 0 Enable"] +pub struct CAPTEN0_W<'a> { + w: &'a mut W, +} +impl<'a> CAPTEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `CAPTEN1` reader - Capture Channel 1 Enable"] +pub struct CAPTEN1_R(crate::FieldReader); +impl CAPTEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CAPTEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CAPTEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAPTEN1` writer - Capture Channel 1 Enable"] +pub struct CAPTEN1_W<'a> { + w: &'a mut W, +} +impl<'a> CAPTEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `COPEN0` reader - Capture On Pin 0 Enable"] +pub struct COPEN0_R(crate::FieldReader); +impl COPEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COPEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COPEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COPEN0` writer - Capture On Pin 0 Enable"] +pub struct COPEN0_W<'a> { + w: &'a mut W, +} +impl<'a> COPEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `COPEN1` reader - Capture On Pin 1 Enable"] +pub struct COPEN1_R(crate::FieldReader); +impl COPEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COPEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COPEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COPEN1` writer - Capture On Pin 1 Enable"] +pub struct COPEN1_W<'a> { + w: &'a mut W, +} +impl<'a> COPEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:3 - Timer Counter Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bits 4:5 - Prescaler and Counter Synchronization"] + #[inline(always)] + pub fn prescsync(&self) -> PRESCSYNC_R { + PRESCSYNC_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Clock On Demand"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 11 - Auto Lock"] + #[inline(always)] + pub fn alock(&self) -> ALOCK_R { + ALOCK_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 16 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn capten0(&self) -> CAPTEN0_R { + CAPTEN0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn capten1(&self) -> CAPTEN1_R { + CAPTEN1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 20 - Capture On Pin 0 Enable"] + #[inline(always)] + pub fn copen0(&self) -> COPEN0_R { + COPEN0_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Capture On Pin 1 Enable"] + #[inline(always)] + pub fn copen1(&self) -> COPEN1_R { + COPEN1_R::new(((self.bits >> 21) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:3 - Timer Counter Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bits 4:5 - Prescaler and Counter Synchronization"] + #[inline(always)] + pub fn prescsync(&mut self) -> PRESCSYNC_W { + PRESCSYNC_W { w: self } + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - Clock On Demand"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Bit 11 - Auto Lock"] + #[inline(always)] + pub fn alock(&mut self) -> ALOCK_W { + ALOCK_W { w: self } + } + #[doc = "Bit 16 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn capten0(&mut self) -> CAPTEN0_W { + CAPTEN0_W { w: self } + } + #[doc = "Bit 17 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn capten1(&mut self) -> CAPTEN1_W { + CAPTEN1_W { w: self } + } + #[doc = "Bit 20 - Capture On Pin 0 Enable"] + #[inline(always)] + pub fn copen0(&mut self) -> COPEN0_W { + COPEN0_W { w: self } + } + #[doc = "Bit 21 - Capture On Pin 1 Enable"] + #[inline(always)] + pub fn copen1(&mut self) -> COPEN1_W { + COPEN1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/tc0/count16/ctrlbclr.rs b/pac/atsamc21e/src/tc0/count16/ctrlbclr.rs new file mode 100644 index 000000000000..76265674036a --- /dev/null +++ b/pac/atsamc21e/src/tc0/count16/ctrlbclr.rs @@ -0,0 +1,345 @@ +#[doc = "Register `CTRLBCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Counter Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `LUPD` reader - Lock Update"] +pub struct LUPD_R(crate::FieldReader); +impl LUPD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LUPD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LUPD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LUPD` writer - Lock Update"] +pub struct LUPD_W<'a> { + w: &'a mut W, +} +impl<'a> LUPD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ONESHOT` reader - One-Shot on Counter"] +pub struct ONESHOT_R(crate::FieldReader); +impl ONESHOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONESHOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONESHOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONESHOT` writer - One-Shot on Counter"] +pub struct ONESHOT_W<'a> { + w: &'a mut W, +} +impl<'a> ONESHOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Force a start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force a stop"] + STOP = 2, + #[doc = "3: Force update of double-buffered register"] + UPDATE = 3, + #[doc = "4: Force a read synchronization of COUNT"] + READSYNC = 4, + #[doc = "5: One-shot DMA trigger"] + DMAOS = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NONE), + 1 => Some(CMD_A::RETRIGGER), + 2 => Some(CMD_A::STOP), + 3 => Some(CMD_A::UPDATE), + 4 => Some(CMD_A::READSYNC), + 5 => Some(CMD_A::DMAOS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == CMD_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == CMD_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == CMD_A::STOP + } + #[doc = "Checks if the value of the field is `UPDATE`"] + #[inline(always)] + pub fn is_update(&self) -> bool { + **self == CMD_A::UPDATE + } + #[doc = "Checks if the value of the field is `READSYNC`"] + #[inline(always)] + pub fn is_readsync(&self) -> bool { + **self == CMD_A::READSYNC + } + #[doc = "Checks if the value of the field is `DMAOS`"] + #[inline(always)] + pub fn is_dmaos(&self) -> bool { + **self == CMD_A::DMAOS + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMD_A::NONE) + } + #[doc = "Force a start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMD_A::RETRIGGER) + } + #[doc = "Force a stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMD_A::STOP) + } + #[doc = "Force update of double-buffered register"] + #[inline(always)] + pub fn update(self) -> &'a mut W { + self.variant(CMD_A::UPDATE) + } + #[doc = "Force a read synchronization of COUNT"] + #[inline(always)] + pub fn readsync(self) -> &'a mut W { + self.variant(CMD_A::READSYNC) + } + #[doc = "One-shot DMA trigger"] + #[inline(always)] + pub fn dmaos(self) -> &'a mut W { + self.variant(CMD_A::DMAOS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 5)) | ((value as u8 & 0x07) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&self) -> LUPD_R { + LUPD_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 5) & 0x07) as u8) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&mut self) -> LUPD_W { + LUPD_W { w: self } + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&mut self) -> ONESHOT_W { + ONESHOT_W { w: self } + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbclr](index.html) module"] +pub struct CTRLBCLR_SPEC; +impl crate::RegisterSpec for CTRLBCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbclr::R](R) reader structure"] +impl crate::Readable for CTRLBCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbclr::W](W) writer structure"] +impl crate::Writable for CTRLBCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLBCLR to value 0"] +impl crate::Resettable for CTRLBCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/tc0/count16/ctrlbset.rs b/pac/atsamc21e/src/tc0/count16/ctrlbset.rs new file mode 100644 index 000000000000..610914c9c7c8 --- /dev/null +++ b/pac/atsamc21e/src/tc0/count16/ctrlbset.rs @@ -0,0 +1,345 @@ +#[doc = "Register `CTRLBSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Counter Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `LUPD` reader - Lock Update"] +pub struct LUPD_R(crate::FieldReader); +impl LUPD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LUPD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LUPD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LUPD` writer - Lock Update"] +pub struct LUPD_W<'a> { + w: &'a mut W, +} +impl<'a> LUPD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ONESHOT` reader - One-Shot on Counter"] +pub struct ONESHOT_R(crate::FieldReader); +impl ONESHOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONESHOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONESHOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONESHOT` writer - One-Shot on Counter"] +pub struct ONESHOT_W<'a> { + w: &'a mut W, +} +impl<'a> ONESHOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Force a start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force a stop"] + STOP = 2, + #[doc = "3: Force update of double-buffered register"] + UPDATE = 3, + #[doc = "4: Force a read synchronization of COUNT"] + READSYNC = 4, + #[doc = "5: One-shot DMA trigger"] + DMAOS = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NONE), + 1 => Some(CMD_A::RETRIGGER), + 2 => Some(CMD_A::STOP), + 3 => Some(CMD_A::UPDATE), + 4 => Some(CMD_A::READSYNC), + 5 => Some(CMD_A::DMAOS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == CMD_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == CMD_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == CMD_A::STOP + } + #[doc = "Checks if the value of the field is `UPDATE`"] + #[inline(always)] + pub fn is_update(&self) -> bool { + **self == CMD_A::UPDATE + } + #[doc = "Checks if the value of the field is `READSYNC`"] + #[inline(always)] + pub fn is_readsync(&self) -> bool { + **self == CMD_A::READSYNC + } + #[doc = "Checks if the value of the field is `DMAOS`"] + #[inline(always)] + pub fn is_dmaos(&self) -> bool { + **self == CMD_A::DMAOS + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMD_A::NONE) + } + #[doc = "Force a start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMD_A::RETRIGGER) + } + #[doc = "Force a stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMD_A::STOP) + } + #[doc = "Force update of double-buffered register"] + #[inline(always)] + pub fn update(self) -> &'a mut W { + self.variant(CMD_A::UPDATE) + } + #[doc = "Force a read synchronization of COUNT"] + #[inline(always)] + pub fn readsync(self) -> &'a mut W { + self.variant(CMD_A::READSYNC) + } + #[doc = "One-shot DMA trigger"] + #[inline(always)] + pub fn dmaos(self) -> &'a mut W { + self.variant(CMD_A::DMAOS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 5)) | ((value as u8 & 0x07) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&self) -> LUPD_R { + LUPD_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 5) & 0x07) as u8) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&mut self) -> LUPD_W { + LUPD_W { w: self } + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&mut self) -> ONESHOT_W { + ONESHOT_W { w: self } + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbset](index.html) module"] +pub struct CTRLBSET_SPEC; +impl crate::RegisterSpec for CTRLBSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbset::R](R) reader structure"] +impl crate::Readable for CTRLBSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbset::W](W) writer structure"] +impl crate::Writable for CTRLBSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLBSET to value 0"] +impl crate::Resettable for CTRLBSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/tc0/count16/dbgctrl.rs b/pac/atsamc21e/src/tc0/count16/dbgctrl.rs new file mode 100644 index 000000000000..0383e70d0429 --- /dev/null +++ b/pac/atsamc21e/src/tc0/count16/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Run During Debug"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Run During Debug"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/tc0/count16/drvctrl.rs b/pac/atsamc21e/src/tc0/count16/drvctrl.rs new file mode 100644 index 000000000000..323926b4b22d --- /dev/null +++ b/pac/atsamc21e/src/tc0/count16/drvctrl.rs @@ -0,0 +1,160 @@ +#[doc = "Register `DRVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DRVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INVEN0` reader - Output Waveform Invert Enable 0"] +pub struct INVEN0_R(crate::FieldReader); +impl INVEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN0` writer - Output Waveform Invert Enable 0"] +pub struct INVEN0_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `INVEN1` reader - Output Waveform Invert Enable 1"] +pub struct INVEN1_R(crate::FieldReader); +impl INVEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN1` writer - Output Waveform Invert Enable 1"] +pub struct INVEN1_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - Output Waveform Invert Enable 0"] + #[inline(always)] + pub fn inven0(&self) -> INVEN0_R { + INVEN0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Output Waveform Invert Enable 1"] + #[inline(always)] + pub fn inven1(&self) -> INVEN1_R { + INVEN1_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Output Waveform Invert Enable 0"] + #[inline(always)] + pub fn inven0(&mut self) -> INVEN0_W { + INVEN0_W { w: self } + } + #[doc = "Bit 1 - Output Waveform Invert Enable 1"] + #[inline(always)] + pub fn inven1(&mut self) -> INVEN1_W { + INVEN1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control C\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [drvctrl](index.html) module"] +pub struct DRVCTRL_SPEC; +impl crate::RegisterSpec for DRVCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [drvctrl::R](R) reader structure"] +impl crate::Readable for DRVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [drvctrl::W](W) writer structure"] +impl crate::Writable for DRVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DRVCTRL to value 0"] +impl crate::Resettable for DRVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/tc0/count16/evctrl.rs b/pac/atsamc21e/src/tc0/count16/evctrl.rs new file mode 100644 index 000000000000..7d4c38d486c1 --- /dev/null +++ b/pac/atsamc21e/src/tc0/count16/evctrl.rs @@ -0,0 +1,465 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Event Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EVACT_A { + #[doc = "0: Event action disabled"] + OFF = 0, + #[doc = "1: Start, restart or retrigger TC on event"] + RETRIGGER = 1, + #[doc = "2: Count on event"] + COUNT = 2, + #[doc = "3: Start TC on event"] + START = 3, + #[doc = "4: Time stamp capture"] + STAMP = 4, + #[doc = "5: Period catured in CC0, pulse width in CC1"] + PPW = 5, + #[doc = "6: Period catured in CC1, pulse width in CC0"] + PWP = 6, + #[doc = "7: Pulse width capture"] + PW = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EVACT_A) -> Self { + variant as _ + } +} +#[doc = "Field `EVACT` reader - Event Action"] +pub struct EVACT_R(crate::FieldReader); +impl EVACT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVACT_A { + match self.bits { + 0 => EVACT_A::OFF, + 1 => EVACT_A::RETRIGGER, + 2 => EVACT_A::COUNT, + 3 => EVACT_A::START, + 4 => EVACT_A::STAMP, + 5 => EVACT_A::PPW, + 6 => EVACT_A::PWP, + 7 => EVACT_A::PW, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == EVACT_A::OFF + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == EVACT_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `COUNT`"] + #[inline(always)] + pub fn is_count(&self) -> bool { + **self == EVACT_A::COUNT + } + #[doc = "Checks if the value of the field is `START`"] + #[inline(always)] + pub fn is_start(&self) -> bool { + **self == EVACT_A::START + } + #[doc = "Checks if the value of the field is `STAMP`"] + #[inline(always)] + pub fn is_stamp(&self) -> bool { + **self == EVACT_A::STAMP + } + #[doc = "Checks if the value of the field is `PPW`"] + #[inline(always)] + pub fn is_ppw(&self) -> bool { + **self == EVACT_A::PPW + } + #[doc = "Checks if the value of the field is `PWP`"] + #[inline(always)] + pub fn is_pwp(&self) -> bool { + **self == EVACT_A::PWP + } + #[doc = "Checks if the value of the field is `PW`"] + #[inline(always)] + pub fn is_pw(&self) -> bool { + **self == EVACT_A::PW + } +} +impl core::ops::Deref for EVACT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT` writer - Event Action"] +pub struct EVACT_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EVACT_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Event action disabled"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(EVACT_A::OFF) + } + #[doc = "Start, restart or retrigger TC on event"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(EVACT_A::RETRIGGER) + } + #[doc = "Count on event"] + #[inline(always)] + pub fn count(self) -> &'a mut W { + self.variant(EVACT_A::COUNT) + } + #[doc = "Start TC on event"] + #[inline(always)] + pub fn start(self) -> &'a mut W { + self.variant(EVACT_A::START) + } + #[doc = "Time stamp capture"] + #[inline(always)] + pub fn stamp(self) -> &'a mut W { + self.variant(EVACT_A::STAMP) + } + #[doc = "Period catured in CC0, pulse width in CC1"] + #[inline(always)] + pub fn ppw(self) -> &'a mut W { + self.variant(EVACT_A::PPW) + } + #[doc = "Period catured in CC1, pulse width in CC0"] + #[inline(always)] + pub fn pwp(self) -> &'a mut W { + self.variant(EVACT_A::PWP) + } + #[doc = "Pulse width capture"] + #[inline(always)] + pub fn pw(self) -> &'a mut W { + self.variant(EVACT_A::PW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u16 & 0x07); + self.w + } +} +#[doc = "Field `TCINV` reader - TC Event Input Polarity"] +pub struct TCINV_R(crate::FieldReader); +impl TCINV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCINV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCINV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCINV` writer - TC Event Input Polarity"] +pub struct TCINV_W<'a> { + w: &'a mut W, +} +impl<'a> TCINV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `TCEI` reader - TC Event Enable"] +pub struct TCEI_R(crate::FieldReader); +impl TCEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCEI` writer - TC Event Enable"] +pub struct TCEI_W<'a> { + w: &'a mut W, +} +impl<'a> TCEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `OVFEO` reader - Event Output Enable"] +pub struct OVFEO_R(crate::FieldReader); +impl OVFEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVFEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVFEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVFEO` writer - Event Output Enable"] +pub struct OVFEO_W<'a> { + w: &'a mut W, +} +impl<'a> OVFEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `MCEO0` reader - MC Event Output Enable 0"] +pub struct MCEO0_R(crate::FieldReader); +impl MCEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO0` writer - MC Event Output Enable 0"] +pub struct MCEO0_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u16 & 0x01) << 12); + self.w + } +} +#[doc = "Field `MCEO1` reader - MC Event Output Enable 1"] +pub struct MCEO1_R(crate::FieldReader); +impl MCEO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO1` writer - MC Event Output Enable 1"] +pub struct MCEO1_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u16 & 0x01) << 13); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Event Action"] + #[inline(always)] + pub fn evact(&self) -> EVACT_R { + EVACT_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 4 - TC Event Input Polarity"] + #[inline(always)] + pub fn tcinv(&self) -> TCINV_R { + TCINV_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - TC Event Enable"] + #[inline(always)] + pub fn tcei(&self) -> TCEI_R { + TCEI_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 8 - Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&self) -> OVFEO_R { + OVFEO_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 12 - MC Event Output Enable 0"] + #[inline(always)] + pub fn mceo0(&self) -> MCEO0_R { + MCEO0_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - MC Event Output Enable 1"] + #[inline(always)] + pub fn mceo1(&self) -> MCEO1_R { + MCEO1_R::new(((self.bits >> 13) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Event Action"] + #[inline(always)] + pub fn evact(&mut self) -> EVACT_W { + EVACT_W { w: self } + } + #[doc = "Bit 4 - TC Event Input Polarity"] + #[inline(always)] + pub fn tcinv(&mut self) -> TCINV_W { + TCINV_W { w: self } + } + #[doc = "Bit 5 - TC Event Enable"] + #[inline(always)] + pub fn tcei(&mut self) -> TCEI_W { + TCEI_W { w: self } + } + #[doc = "Bit 8 - Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&mut self) -> OVFEO_W { + OVFEO_W { w: self } + } + #[doc = "Bit 12 - MC Event Output Enable 0"] + #[inline(always)] + pub fn mceo0(&mut self) -> MCEO0_W { + MCEO0_W { w: self } + } + #[doc = "Bit 13 - MC Event Output Enable 1"] + #[inline(always)] + pub fn mceo1(&mut self) -> MCEO1_W { + MCEO1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/tc0/count16/intenclr.rs b/pac/atsamc21e/src/tc0/count16/intenclr.rs new file mode 100644 index 000000000000..af01ef5b7dca --- /dev/null +++ b/pac/atsamc21e/src/tc0/count16/intenclr.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - OVF Interrupt Disable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - OVF Interrupt Disable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - ERR Interrupt Disable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - ERR Interrupt Disable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MC0` reader - MC Interrupt Disable 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - MC Interrupt Disable 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - MC Interrupt Disable 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - MC Interrupt Disable 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - OVF Interrupt Disable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ERR Interrupt Disable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - MC Interrupt Disable 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - MC Interrupt Disable 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - OVF Interrupt Disable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - ERR Interrupt Disable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 4 - MC Interrupt Disable 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - MC Interrupt Disable 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/tc0/count16/intenset.rs b/pac/atsamc21e/src/tc0/count16/intenset.rs new file mode 100644 index 000000000000..0e1883a2f20a --- /dev/null +++ b/pac/atsamc21e/src/tc0/count16/intenset.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - OVF Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - OVF Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - ERR Interrupt Enable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - ERR Interrupt Enable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MC0` reader - MC Interrupt Enable 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - MC Interrupt Enable 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - MC Interrupt Enable 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - MC Interrupt Enable 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - OVF Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ERR Interrupt Enable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - MC Interrupt Enable 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - MC Interrupt Enable 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - OVF Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - ERR Interrupt Enable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 4 - MC Interrupt Enable 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - MC Interrupt Enable 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/tc0/count16/intflag.rs b/pac/atsamc21e/src/tc0/count16/intflag.rs new file mode 100644 index 000000000000..1dddffaf8e7f --- /dev/null +++ b/pac/atsamc21e/src/tc0/count16/intflag.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - OVF Interrupt Flag"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - OVF Interrupt Flag"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - ERR Interrupt Flag"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - ERR Interrupt Flag"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MC0` reader - MC Interrupt Flag 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - MC Interrupt Flag 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - MC Interrupt Flag 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - MC Interrupt Flag 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - OVF Interrupt Flag"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ERR Interrupt Flag"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - MC Interrupt Flag 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - MC Interrupt Flag 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - OVF Interrupt Flag"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - ERR Interrupt Flag"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 4 - MC Interrupt Flag 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - MC Interrupt Flag 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/tc0/count16/status.rs b/pac/atsamc21e/src/tc0/count16/status.rs new file mode 100644 index 000000000000..5088af446830 --- /dev/null +++ b/pac/atsamc21e/src/tc0/count16/status.rs @@ -0,0 +1,301 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `STOP` reader - Stop Status Flag"] +pub struct STOP_R(crate::FieldReader); +impl STOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STOP` writer - Stop Status Flag"] +pub struct STOP_W<'a> { + w: &'a mut W, +} +impl<'a> STOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SLAVE` reader - Slave Status Flag"] +pub struct SLAVE_R(crate::FieldReader); +impl SLAVE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLAVE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SLAVE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLAVE` writer - Slave Status Flag"] +pub struct SLAVE_W<'a> { + w: &'a mut W, +} +impl<'a> SLAVE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PERBUFV` reader - Synchronization Busy Status"] +pub struct PERBUFV_R(crate::FieldReader); +impl PERBUFV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PERBUFV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERBUFV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERBUFV` writer - Synchronization Busy Status"] +pub struct PERBUFV_W<'a> { + w: &'a mut W, +} +impl<'a> PERBUFV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CCBUFV0` reader - Compare channel buffer 0 valid"] +pub struct CCBUFV0_R(crate::FieldReader); +impl CCBUFV0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBUFV0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUFV0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUFV0` writer - Compare channel buffer 0 valid"] +pub struct CCBUFV0_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUFV0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `CCBUFV1` reader - Compare channel buffer 1 valid"] +pub struct CCBUFV1_R(crate::FieldReader); +impl CCBUFV1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBUFV1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUFV1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUFV1` writer - Compare channel buffer 1 valid"] +pub struct CCBUFV1_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUFV1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Stop Status Flag"] + #[inline(always)] + pub fn stop(&self) -> STOP_R { + STOP_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Slave Status Flag"] + #[inline(always)] + pub fn slave(&self) -> SLAVE_R { + SLAVE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 3 - Synchronization Busy Status"] + #[inline(always)] + pub fn perbufv(&self) -> PERBUFV_R { + PERBUFV_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Compare channel buffer 0 valid"] + #[inline(always)] + pub fn ccbufv0(&self) -> CCBUFV0_R { + CCBUFV0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Compare channel buffer 1 valid"] + #[inline(always)] + pub fn ccbufv1(&self) -> CCBUFV1_R { + CCBUFV1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Stop Status Flag"] + #[inline(always)] + pub fn stop(&mut self) -> STOP_W { + STOP_W { w: self } + } + #[doc = "Bit 1 - Slave Status Flag"] + #[inline(always)] + pub fn slave(&mut self) -> SLAVE_W { + SLAVE_W { w: self } + } + #[doc = "Bit 3 - Synchronization Busy Status"] + #[inline(always)] + pub fn perbufv(&mut self) -> PERBUFV_W { + PERBUFV_W { w: self } + } + #[doc = "Bit 4 - Compare channel buffer 0 valid"] + #[inline(always)] + pub fn ccbufv0(&mut self) -> CCBUFV0_W { + CCBUFV0_W { w: self } + } + #[doc = "Bit 5 - Compare channel buffer 1 valid"] + #[inline(always)] + pub fn ccbufv1(&mut self) -> CCBUFV1_W { + CCBUFV1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0x01"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pac/atsamc21e/src/tc0/count16/syncbusy.rs b/pac/atsamc21e/src/tc0/count16/syncbusy.rs new file mode 100644 index 000000000000..7ad8d91a84de --- /dev/null +++ b/pac/atsamc21e/src/tc0/count16/syncbusy.rs @@ -0,0 +1,193 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - swrst"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLB` reader - CTRLB"] +pub struct CTRLB_R(crate::FieldReader); +impl CTRLB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STATUS` reader - STATUS"] +pub struct STATUS_R(crate::FieldReader); +impl STATUS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STATUS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STATUS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` reader - Counter"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` reader - Period"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC0` reader - Compare Channel 0"] +pub struct CC0_R(crate::FieldReader); +impl CC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC1` reader - Compare Channel 1"] +pub struct CC1_R(crate::FieldReader); +impl CC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - swrst"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - CTRLB"] + #[inline(always)] + pub fn ctrlb(&self) -> CTRLB_R { + CTRLB_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - STATUS"] + #[inline(always)] + pub fn status(&self) -> STATUS_R { + STATUS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Counter"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Period"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Compare Channel 0"] + #[inline(always)] + pub fn cc0(&self) -> CC0_R { + CC0_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Compare Channel 1"] + #[inline(always)] + pub fn cc1(&self) -> CC1_R { + CC1_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +#[doc = "Synchronization Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/tc0/count16/wave.rs b/pac/atsamc21e/src/tc0/count16/wave.rs new file mode 100644 index 000000000000..46061b24b75d --- /dev/null +++ b/pac/atsamc21e/src/tc0/count16/wave.rs @@ -0,0 +1,178 @@ +#[doc = "Register `WAVE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WAVE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Waveform Generation Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WAVEGEN_A { + #[doc = "0: Normal frequency"] + NFRQ = 0, + #[doc = "1: Match frequency"] + MFRQ = 1, + #[doc = "2: Normal PWM"] + NPWM = 2, + #[doc = "3: Match PWM"] + MPWM = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WAVEGEN_A) -> Self { + variant as _ + } +} +#[doc = "Field `WAVEGEN` reader - Waveform Generation Mode"] +pub struct WAVEGEN_R(crate::FieldReader); +impl WAVEGEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WAVEGEN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> WAVEGEN_A { + match self.bits { + 0 => WAVEGEN_A::NFRQ, + 1 => WAVEGEN_A::MFRQ, + 2 => WAVEGEN_A::NPWM, + 3 => WAVEGEN_A::MPWM, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NFRQ`"] + #[inline(always)] + pub fn is_nfrq(&self) -> bool { + **self == WAVEGEN_A::NFRQ + } + #[doc = "Checks if the value of the field is `MFRQ`"] + #[inline(always)] + pub fn is_mfrq(&self) -> bool { + **self == WAVEGEN_A::MFRQ + } + #[doc = "Checks if the value of the field is `NPWM`"] + #[inline(always)] + pub fn is_npwm(&self) -> bool { + **self == WAVEGEN_A::NPWM + } + #[doc = "Checks if the value of the field is `MPWM`"] + #[inline(always)] + pub fn is_mpwm(&self) -> bool { + **self == WAVEGEN_A::MPWM + } +} +impl core::ops::Deref for WAVEGEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAVEGEN` writer - Waveform Generation Mode"] +pub struct WAVEGEN_W<'a> { + w: &'a mut W, +} +impl<'a> WAVEGEN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WAVEGEN_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Normal frequency"] + #[inline(always)] + pub fn nfrq(self) -> &'a mut W { + self.variant(WAVEGEN_A::NFRQ) + } + #[doc = "Match frequency"] + #[inline(always)] + pub fn mfrq(self) -> &'a mut W { + self.variant(WAVEGEN_A::MFRQ) + } + #[doc = "Normal PWM"] + #[inline(always)] + pub fn npwm(self) -> &'a mut W { + self.variant(WAVEGEN_A::NPWM) + } + #[doc = "Match PWM"] + #[inline(always)] + pub fn mpwm(self) -> &'a mut W { + self.variant(WAVEGEN_A::MPWM) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u8 & 0x03); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Waveform Generation Mode"] + #[inline(always)] + pub fn wavegen(&self) -> WAVEGEN_R { + WAVEGEN_R::new((self.bits & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Waveform Generation Mode"] + #[inline(always)] + pub fn wavegen(&mut self) -> WAVEGEN_W { + WAVEGEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Waveform Generation Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wave](index.html) module"] +pub struct WAVE_SPEC; +impl crate::RegisterSpec for WAVE_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [wave::R](R) reader structure"] +impl crate::Readable for WAVE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wave::W](W) writer structure"] +impl crate::Writable for WAVE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WAVE to value 0"] +impl crate::Resettable for WAVE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/tc0/count32.rs b/pac/atsamc21e/src/tc0/count32.rs new file mode 100644 index 000000000000..9062acfbbd7f --- /dev/null +++ b/pac/atsamc21e/src/tc0/count32.rs @@ -0,0 +1,60 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "CTRLBCLR register accessor: an alias for `Reg`"] +pub type CTRLBCLR = crate::Reg; +#[doc = "Control B Clear"] +pub mod ctrlbclr; +#[doc = "CTRLBSET register accessor: an alias for `Reg`"] +pub type CTRLBSET = crate::Reg; +#[doc = "Control B Set"] +pub mod ctrlbset; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "WAVE register accessor: an alias for `Reg`"] +pub type WAVE = crate::Reg; +#[doc = "Waveform Generation Control"] +pub mod wave; +#[doc = "DRVCTRL register accessor: an alias for `Reg`"] +pub type DRVCTRL = crate::Reg; +#[doc = "Control C"] +pub mod drvctrl; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Status"] +pub mod syncbusy; +#[doc = "COUNT register accessor: an alias for `Reg`"] +pub type COUNT = crate::Reg; +#[doc = "COUNT32 Count"] +pub mod count; +#[doc = "CC register accessor: an alias for `Reg`"] +pub type CC = crate::Reg; +#[doc = "COUNT32 Compare and Capture"] +pub mod cc; +#[doc = "CCBUF register accessor: an alias for `Reg`"] +pub type CCBUF = crate::Reg; +#[doc = "COUNT32 Compare and Capture Buffer"] +pub mod ccbuf; diff --git a/pac/atsamc21e/src/tc0/count32/cc.rs b/pac/atsamc21e/src/tc0/count32/cc.rs new file mode 100644 index 000000000000..512a1e01ffd4 --- /dev/null +++ b/pac/atsamc21e/src/tc0/count32/cc.rs @@ -0,0 +1,104 @@ +#[doc = "Register `CC[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CC[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CC` reader - Counter/Compare Value"] +pub struct CC_R(crate::FieldReader); +impl CC_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC` writer - Counter/Compare Value"] +pub struct CC_W<'a> { + w: &'a mut W, +} +impl<'a> CC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Counter/Compare Value"] + #[inline(always)] + pub fn cc(&self) -> CC_R { + CC_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Counter/Compare Value"] + #[inline(always)] + pub fn cc(&mut self) -> CC_W { + CC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT32 Compare and Capture\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc](index.html) module"] +pub struct CC_SPEC; +impl crate::RegisterSpec for CC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cc::R](R) reader structure"] +impl crate::Readable for CC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cc::W](W) writer structure"] +impl crate::Writable for CC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CC[%s] +to value 0"] +impl crate::Resettable for CC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/tc0/count32/ccbuf.rs b/pac/atsamc21e/src/tc0/count32/ccbuf.rs new file mode 100644 index 000000000000..9fb2d9f8f66c --- /dev/null +++ b/pac/atsamc21e/src/tc0/count32/ccbuf.rs @@ -0,0 +1,104 @@ +#[doc = "Register `CCBUF[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CCBUF[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CCBUF` reader - Counter/Compare Buffer Value"] +pub struct CCBUF_R(crate::FieldReader); +impl CCBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CCBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUF` writer - Counter/Compare Buffer Value"] +pub struct CCBUF_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Counter/Compare Buffer Value"] + #[inline(always)] + pub fn ccbuf(&self) -> CCBUF_R { + CCBUF_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Counter/Compare Buffer Value"] + #[inline(always)] + pub fn ccbuf(&mut self) -> CCBUF_W { + CCBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT32 Compare and Capture Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccbuf](index.html) module"] +pub struct CCBUF_SPEC; +impl crate::RegisterSpec for CCBUF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ccbuf::R](R) reader structure"] +impl crate::Readable for CCBUF_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ccbuf::W](W) writer structure"] +impl crate::Writable for CCBUF_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CCBUF[%s] +to value 0"] +impl crate::Resettable for CCBUF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/tc0/count32/count.rs b/pac/atsamc21e/src/tc0/count32/count.rs new file mode 100644 index 000000000000..9aea527a8b3c --- /dev/null +++ b/pac/atsamc21e/src/tc0/count32/count.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT32 Count\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count](index.html) module"] +pub struct COUNT_SPEC; +impl crate::RegisterSpec for COUNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [count::R](R) reader structure"] +impl crate::Readable for COUNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count::W](W) writer structure"] +impl crate::Writable for COUNT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT to value 0"] +impl crate::Resettable for COUNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/tc0/count32/ctrla.rs b/pac/atsamc21e/src/tc0/count32/ctrla.rs new file mode 100644 index 000000000000..cadcddaaead8 --- /dev/null +++ b/pac/atsamc21e/src/tc0/count32/ctrla.rs @@ -0,0 +1,851 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Timer Counter Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: Counter in 16-bit mode"] + COUNT16 = 0, + #[doc = "1: Counter in 8-bit mode"] + COUNT8 = 1, + #[doc = "2: Counter in 32-bit mode"] + COUNT32 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Timer Counter Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::COUNT16), + 1 => Some(MODE_A::COUNT8), + 2 => Some(MODE_A::COUNT32), + _ => None, + } + } + #[doc = "Checks if the value of the field is `COUNT16`"] + #[inline(always)] + pub fn is_count16(&self) -> bool { + **self == MODE_A::COUNT16 + } + #[doc = "Checks if the value of the field is `COUNT8`"] + #[inline(always)] + pub fn is_count8(&self) -> bool { + **self == MODE_A::COUNT8 + } + #[doc = "Checks if the value of the field is `COUNT32`"] + #[inline(always)] + pub fn is_count32(&self) -> bool { + **self == MODE_A::COUNT32 + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Timer Counter Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Counter in 16-bit mode"] + #[inline(always)] + pub fn count16(self) -> &'a mut W { + self.variant(MODE_A::COUNT16) + } + #[doc = "Counter in 8-bit mode"] + #[inline(always)] + pub fn count8(self) -> &'a mut W { + self.variant(MODE_A::COUNT8) + } + #[doc = "Counter in 32-bit mode"] + #[inline(always)] + pub fn count32(self) -> &'a mut W { + self.variant(MODE_A::COUNT32) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u32 & 0x03) << 2); + self.w + } +} +#[doc = "Prescaler and Counter Synchronization\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCSYNC_A { + #[doc = "0: Reload or reset the counter on next generic clock"] + GCLK = 0, + #[doc = "1: Reload or reset the counter on next prescaler clock"] + PRESC = 1, + #[doc = "2: Reload or reset the counter on next generic clock and reset the prescaler counter"] + RESYNC = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCSYNC_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCSYNC` reader - Prescaler and Counter Synchronization"] +pub struct PRESCSYNC_R(crate::FieldReader); +impl PRESCSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCSYNC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCSYNC_A::GCLK), + 1 => Some(PRESCSYNC_A::PRESC), + 2 => Some(PRESCSYNC_A::RESYNC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `GCLK`"] + #[inline(always)] + pub fn is_gclk(&self) -> bool { + **self == PRESCSYNC_A::GCLK + } + #[doc = "Checks if the value of the field is `PRESC`"] + #[inline(always)] + pub fn is_presc(&self) -> bool { + **self == PRESCSYNC_A::PRESC + } + #[doc = "Checks if the value of the field is `RESYNC`"] + #[inline(always)] + pub fn is_resync(&self) -> bool { + **self == PRESCSYNC_A::RESYNC + } +} +impl core::ops::Deref for PRESCSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCSYNC` writer - Prescaler and Counter Synchronization"] +pub struct PRESCSYNC_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCSYNC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCSYNC_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Reload or reset the counter on next generic clock"] + #[inline(always)] + pub fn gclk(self) -> &'a mut W { + self.variant(PRESCSYNC_A::GCLK) + } + #[doc = "Reload or reset the counter on next prescaler clock"] + #[inline(always)] + pub fn presc(self) -> &'a mut W { + self.variant(PRESCSYNC_A::PRESC) + } + #[doc = "Reload or reset the counter on next generic clock and reset the prescaler counter"] + #[inline(always)] + pub fn resync(self) -> &'a mut W { + self.variant(PRESCSYNC_A::RESYNC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u32 & 0x03) << 4); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - Clock On Demand"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - Clock On Demand"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: Prescaler: GCLK_TC"] + DIV1 = 0, + #[doc = "1: Prescaler: GCLK_TC/2"] + DIV2 = 1, + #[doc = "2: Prescaler: GCLK_TC/4"] + DIV4 = 2, + #[doc = "3: Prescaler: GCLK_TC/8"] + DIV8 = 3, + #[doc = "4: Prescaler: GCLK_TC/16"] + DIV16 = 4, + #[doc = "5: Prescaler: GCLK_TC/64"] + DIV64 = 5, + #[doc = "6: Prescaler: GCLK_TC/256"] + DIV256 = 6, + #[doc = "7: Prescaler: GCLK_TC/1024"] + DIV1024 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PRESCALER_A { + match self.bits { + 0 => PRESCALER_A::DIV1, + 1 => PRESCALER_A::DIV2, + 2 => PRESCALER_A::DIV4, + 3 => PRESCALER_A::DIV8, + 4 => PRESCALER_A::DIV16, + 5 => PRESCALER_A::DIV64, + 6 => PRESCALER_A::DIV256, + 7 => PRESCALER_A::DIV1024, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == PRESCALER_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PRESCALER_A::DIV1024 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Prescaler: GCLK_TC"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1) + } + #[doc = "Prescaler: GCLK_TC/2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "Prescaler: GCLK_TC/4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "Prescaler: GCLK_TC/8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "Prescaler: GCLK_TC/16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "Prescaler: GCLK_TC/64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "Prescaler: GCLK_TC/256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = "Prescaler: GCLK_TC/1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +#[doc = "Field `ALOCK` reader - Auto Lock"] +pub struct ALOCK_R(crate::FieldReader); +impl ALOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALOCK` writer - Auto Lock"] +pub struct ALOCK_W<'a> { + w: &'a mut W, +} +impl<'a> ALOCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `CAPTEN0` reader - Capture Channel 0 Enable"] +pub struct CAPTEN0_R(crate::FieldReader); +impl CAPTEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CAPTEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CAPTEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAPTEN0` writer - Capture Channel 0 Enable"] +pub struct CAPTEN0_W<'a> { + w: &'a mut W, +} +impl<'a> CAPTEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `CAPTEN1` reader - Capture Channel 1 Enable"] +pub struct CAPTEN1_R(crate::FieldReader); +impl CAPTEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CAPTEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CAPTEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAPTEN1` writer - Capture Channel 1 Enable"] +pub struct CAPTEN1_W<'a> { + w: &'a mut W, +} +impl<'a> CAPTEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `COPEN0` reader - Capture On Pin 0 Enable"] +pub struct COPEN0_R(crate::FieldReader); +impl COPEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COPEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COPEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COPEN0` writer - Capture On Pin 0 Enable"] +pub struct COPEN0_W<'a> { + w: &'a mut W, +} +impl<'a> COPEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `COPEN1` reader - Capture On Pin 1 Enable"] +pub struct COPEN1_R(crate::FieldReader); +impl COPEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COPEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COPEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COPEN1` writer - Capture On Pin 1 Enable"] +pub struct COPEN1_W<'a> { + w: &'a mut W, +} +impl<'a> COPEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:3 - Timer Counter Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bits 4:5 - Prescaler and Counter Synchronization"] + #[inline(always)] + pub fn prescsync(&self) -> PRESCSYNC_R { + PRESCSYNC_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Clock On Demand"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 11 - Auto Lock"] + #[inline(always)] + pub fn alock(&self) -> ALOCK_R { + ALOCK_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 16 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn capten0(&self) -> CAPTEN0_R { + CAPTEN0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn capten1(&self) -> CAPTEN1_R { + CAPTEN1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 20 - Capture On Pin 0 Enable"] + #[inline(always)] + pub fn copen0(&self) -> COPEN0_R { + COPEN0_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Capture On Pin 1 Enable"] + #[inline(always)] + pub fn copen1(&self) -> COPEN1_R { + COPEN1_R::new(((self.bits >> 21) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:3 - Timer Counter Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bits 4:5 - Prescaler and Counter Synchronization"] + #[inline(always)] + pub fn prescsync(&mut self) -> PRESCSYNC_W { + PRESCSYNC_W { w: self } + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - Clock On Demand"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Bit 11 - Auto Lock"] + #[inline(always)] + pub fn alock(&mut self) -> ALOCK_W { + ALOCK_W { w: self } + } + #[doc = "Bit 16 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn capten0(&mut self) -> CAPTEN0_W { + CAPTEN0_W { w: self } + } + #[doc = "Bit 17 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn capten1(&mut self) -> CAPTEN1_W { + CAPTEN1_W { w: self } + } + #[doc = "Bit 20 - Capture On Pin 0 Enable"] + #[inline(always)] + pub fn copen0(&mut self) -> COPEN0_W { + COPEN0_W { w: self } + } + #[doc = "Bit 21 - Capture On Pin 1 Enable"] + #[inline(always)] + pub fn copen1(&mut self) -> COPEN1_W { + COPEN1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/tc0/count32/ctrlbclr.rs b/pac/atsamc21e/src/tc0/count32/ctrlbclr.rs new file mode 100644 index 000000000000..76265674036a --- /dev/null +++ b/pac/atsamc21e/src/tc0/count32/ctrlbclr.rs @@ -0,0 +1,345 @@ +#[doc = "Register `CTRLBCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Counter Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `LUPD` reader - Lock Update"] +pub struct LUPD_R(crate::FieldReader); +impl LUPD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LUPD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LUPD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LUPD` writer - Lock Update"] +pub struct LUPD_W<'a> { + w: &'a mut W, +} +impl<'a> LUPD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ONESHOT` reader - One-Shot on Counter"] +pub struct ONESHOT_R(crate::FieldReader); +impl ONESHOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONESHOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONESHOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONESHOT` writer - One-Shot on Counter"] +pub struct ONESHOT_W<'a> { + w: &'a mut W, +} +impl<'a> ONESHOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Force a start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force a stop"] + STOP = 2, + #[doc = "3: Force update of double-buffered register"] + UPDATE = 3, + #[doc = "4: Force a read synchronization of COUNT"] + READSYNC = 4, + #[doc = "5: One-shot DMA trigger"] + DMAOS = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NONE), + 1 => Some(CMD_A::RETRIGGER), + 2 => Some(CMD_A::STOP), + 3 => Some(CMD_A::UPDATE), + 4 => Some(CMD_A::READSYNC), + 5 => Some(CMD_A::DMAOS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == CMD_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == CMD_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == CMD_A::STOP + } + #[doc = "Checks if the value of the field is `UPDATE`"] + #[inline(always)] + pub fn is_update(&self) -> bool { + **self == CMD_A::UPDATE + } + #[doc = "Checks if the value of the field is `READSYNC`"] + #[inline(always)] + pub fn is_readsync(&self) -> bool { + **self == CMD_A::READSYNC + } + #[doc = "Checks if the value of the field is `DMAOS`"] + #[inline(always)] + pub fn is_dmaos(&self) -> bool { + **self == CMD_A::DMAOS + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMD_A::NONE) + } + #[doc = "Force a start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMD_A::RETRIGGER) + } + #[doc = "Force a stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMD_A::STOP) + } + #[doc = "Force update of double-buffered register"] + #[inline(always)] + pub fn update(self) -> &'a mut W { + self.variant(CMD_A::UPDATE) + } + #[doc = "Force a read synchronization of COUNT"] + #[inline(always)] + pub fn readsync(self) -> &'a mut W { + self.variant(CMD_A::READSYNC) + } + #[doc = "One-shot DMA trigger"] + #[inline(always)] + pub fn dmaos(self) -> &'a mut W { + self.variant(CMD_A::DMAOS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 5)) | ((value as u8 & 0x07) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&self) -> LUPD_R { + LUPD_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 5) & 0x07) as u8) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&mut self) -> LUPD_W { + LUPD_W { w: self } + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&mut self) -> ONESHOT_W { + ONESHOT_W { w: self } + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbclr](index.html) module"] +pub struct CTRLBCLR_SPEC; +impl crate::RegisterSpec for CTRLBCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbclr::R](R) reader structure"] +impl crate::Readable for CTRLBCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbclr::W](W) writer structure"] +impl crate::Writable for CTRLBCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLBCLR to value 0"] +impl crate::Resettable for CTRLBCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/tc0/count32/ctrlbset.rs b/pac/atsamc21e/src/tc0/count32/ctrlbset.rs new file mode 100644 index 000000000000..610914c9c7c8 --- /dev/null +++ b/pac/atsamc21e/src/tc0/count32/ctrlbset.rs @@ -0,0 +1,345 @@ +#[doc = "Register `CTRLBSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Counter Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `LUPD` reader - Lock Update"] +pub struct LUPD_R(crate::FieldReader); +impl LUPD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LUPD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LUPD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LUPD` writer - Lock Update"] +pub struct LUPD_W<'a> { + w: &'a mut W, +} +impl<'a> LUPD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ONESHOT` reader - One-Shot on Counter"] +pub struct ONESHOT_R(crate::FieldReader); +impl ONESHOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONESHOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONESHOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONESHOT` writer - One-Shot on Counter"] +pub struct ONESHOT_W<'a> { + w: &'a mut W, +} +impl<'a> ONESHOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Force a start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force a stop"] + STOP = 2, + #[doc = "3: Force update of double-buffered register"] + UPDATE = 3, + #[doc = "4: Force a read synchronization of COUNT"] + READSYNC = 4, + #[doc = "5: One-shot DMA trigger"] + DMAOS = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NONE), + 1 => Some(CMD_A::RETRIGGER), + 2 => Some(CMD_A::STOP), + 3 => Some(CMD_A::UPDATE), + 4 => Some(CMD_A::READSYNC), + 5 => Some(CMD_A::DMAOS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == CMD_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == CMD_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == CMD_A::STOP + } + #[doc = "Checks if the value of the field is `UPDATE`"] + #[inline(always)] + pub fn is_update(&self) -> bool { + **self == CMD_A::UPDATE + } + #[doc = "Checks if the value of the field is `READSYNC`"] + #[inline(always)] + pub fn is_readsync(&self) -> bool { + **self == CMD_A::READSYNC + } + #[doc = "Checks if the value of the field is `DMAOS`"] + #[inline(always)] + pub fn is_dmaos(&self) -> bool { + **self == CMD_A::DMAOS + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMD_A::NONE) + } + #[doc = "Force a start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMD_A::RETRIGGER) + } + #[doc = "Force a stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMD_A::STOP) + } + #[doc = "Force update of double-buffered register"] + #[inline(always)] + pub fn update(self) -> &'a mut W { + self.variant(CMD_A::UPDATE) + } + #[doc = "Force a read synchronization of COUNT"] + #[inline(always)] + pub fn readsync(self) -> &'a mut W { + self.variant(CMD_A::READSYNC) + } + #[doc = "One-shot DMA trigger"] + #[inline(always)] + pub fn dmaos(self) -> &'a mut W { + self.variant(CMD_A::DMAOS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 5)) | ((value as u8 & 0x07) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&self) -> LUPD_R { + LUPD_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 5) & 0x07) as u8) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&mut self) -> LUPD_W { + LUPD_W { w: self } + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&mut self) -> ONESHOT_W { + ONESHOT_W { w: self } + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbset](index.html) module"] +pub struct CTRLBSET_SPEC; +impl crate::RegisterSpec for CTRLBSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbset::R](R) reader structure"] +impl crate::Readable for CTRLBSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbset::W](W) writer structure"] +impl crate::Writable for CTRLBSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLBSET to value 0"] +impl crate::Resettable for CTRLBSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/tc0/count32/dbgctrl.rs b/pac/atsamc21e/src/tc0/count32/dbgctrl.rs new file mode 100644 index 000000000000..0383e70d0429 --- /dev/null +++ b/pac/atsamc21e/src/tc0/count32/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Run During Debug"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Run During Debug"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/tc0/count32/drvctrl.rs b/pac/atsamc21e/src/tc0/count32/drvctrl.rs new file mode 100644 index 000000000000..323926b4b22d --- /dev/null +++ b/pac/atsamc21e/src/tc0/count32/drvctrl.rs @@ -0,0 +1,160 @@ +#[doc = "Register `DRVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DRVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INVEN0` reader - Output Waveform Invert Enable 0"] +pub struct INVEN0_R(crate::FieldReader); +impl INVEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN0` writer - Output Waveform Invert Enable 0"] +pub struct INVEN0_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `INVEN1` reader - Output Waveform Invert Enable 1"] +pub struct INVEN1_R(crate::FieldReader); +impl INVEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN1` writer - Output Waveform Invert Enable 1"] +pub struct INVEN1_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - Output Waveform Invert Enable 0"] + #[inline(always)] + pub fn inven0(&self) -> INVEN0_R { + INVEN0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Output Waveform Invert Enable 1"] + #[inline(always)] + pub fn inven1(&self) -> INVEN1_R { + INVEN1_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Output Waveform Invert Enable 0"] + #[inline(always)] + pub fn inven0(&mut self) -> INVEN0_W { + INVEN0_W { w: self } + } + #[doc = "Bit 1 - Output Waveform Invert Enable 1"] + #[inline(always)] + pub fn inven1(&mut self) -> INVEN1_W { + INVEN1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control C\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [drvctrl](index.html) module"] +pub struct DRVCTRL_SPEC; +impl crate::RegisterSpec for DRVCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [drvctrl::R](R) reader structure"] +impl crate::Readable for DRVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [drvctrl::W](W) writer structure"] +impl crate::Writable for DRVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DRVCTRL to value 0"] +impl crate::Resettable for DRVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/tc0/count32/evctrl.rs b/pac/atsamc21e/src/tc0/count32/evctrl.rs new file mode 100644 index 000000000000..7d4c38d486c1 --- /dev/null +++ b/pac/atsamc21e/src/tc0/count32/evctrl.rs @@ -0,0 +1,465 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Event Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EVACT_A { + #[doc = "0: Event action disabled"] + OFF = 0, + #[doc = "1: Start, restart or retrigger TC on event"] + RETRIGGER = 1, + #[doc = "2: Count on event"] + COUNT = 2, + #[doc = "3: Start TC on event"] + START = 3, + #[doc = "4: Time stamp capture"] + STAMP = 4, + #[doc = "5: Period catured in CC0, pulse width in CC1"] + PPW = 5, + #[doc = "6: Period catured in CC1, pulse width in CC0"] + PWP = 6, + #[doc = "7: Pulse width capture"] + PW = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EVACT_A) -> Self { + variant as _ + } +} +#[doc = "Field `EVACT` reader - Event Action"] +pub struct EVACT_R(crate::FieldReader); +impl EVACT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVACT_A { + match self.bits { + 0 => EVACT_A::OFF, + 1 => EVACT_A::RETRIGGER, + 2 => EVACT_A::COUNT, + 3 => EVACT_A::START, + 4 => EVACT_A::STAMP, + 5 => EVACT_A::PPW, + 6 => EVACT_A::PWP, + 7 => EVACT_A::PW, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == EVACT_A::OFF + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == EVACT_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `COUNT`"] + #[inline(always)] + pub fn is_count(&self) -> bool { + **self == EVACT_A::COUNT + } + #[doc = "Checks if the value of the field is `START`"] + #[inline(always)] + pub fn is_start(&self) -> bool { + **self == EVACT_A::START + } + #[doc = "Checks if the value of the field is `STAMP`"] + #[inline(always)] + pub fn is_stamp(&self) -> bool { + **self == EVACT_A::STAMP + } + #[doc = "Checks if the value of the field is `PPW`"] + #[inline(always)] + pub fn is_ppw(&self) -> bool { + **self == EVACT_A::PPW + } + #[doc = "Checks if the value of the field is `PWP`"] + #[inline(always)] + pub fn is_pwp(&self) -> bool { + **self == EVACT_A::PWP + } + #[doc = "Checks if the value of the field is `PW`"] + #[inline(always)] + pub fn is_pw(&self) -> bool { + **self == EVACT_A::PW + } +} +impl core::ops::Deref for EVACT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT` writer - Event Action"] +pub struct EVACT_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EVACT_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Event action disabled"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(EVACT_A::OFF) + } + #[doc = "Start, restart or retrigger TC on event"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(EVACT_A::RETRIGGER) + } + #[doc = "Count on event"] + #[inline(always)] + pub fn count(self) -> &'a mut W { + self.variant(EVACT_A::COUNT) + } + #[doc = "Start TC on event"] + #[inline(always)] + pub fn start(self) -> &'a mut W { + self.variant(EVACT_A::START) + } + #[doc = "Time stamp capture"] + #[inline(always)] + pub fn stamp(self) -> &'a mut W { + self.variant(EVACT_A::STAMP) + } + #[doc = "Period catured in CC0, pulse width in CC1"] + #[inline(always)] + pub fn ppw(self) -> &'a mut W { + self.variant(EVACT_A::PPW) + } + #[doc = "Period catured in CC1, pulse width in CC0"] + #[inline(always)] + pub fn pwp(self) -> &'a mut W { + self.variant(EVACT_A::PWP) + } + #[doc = "Pulse width capture"] + #[inline(always)] + pub fn pw(self) -> &'a mut W { + self.variant(EVACT_A::PW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u16 & 0x07); + self.w + } +} +#[doc = "Field `TCINV` reader - TC Event Input Polarity"] +pub struct TCINV_R(crate::FieldReader); +impl TCINV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCINV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCINV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCINV` writer - TC Event Input Polarity"] +pub struct TCINV_W<'a> { + w: &'a mut W, +} +impl<'a> TCINV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `TCEI` reader - TC Event Enable"] +pub struct TCEI_R(crate::FieldReader); +impl TCEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCEI` writer - TC Event Enable"] +pub struct TCEI_W<'a> { + w: &'a mut W, +} +impl<'a> TCEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `OVFEO` reader - Event Output Enable"] +pub struct OVFEO_R(crate::FieldReader); +impl OVFEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVFEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVFEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVFEO` writer - Event Output Enable"] +pub struct OVFEO_W<'a> { + w: &'a mut W, +} +impl<'a> OVFEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `MCEO0` reader - MC Event Output Enable 0"] +pub struct MCEO0_R(crate::FieldReader); +impl MCEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO0` writer - MC Event Output Enable 0"] +pub struct MCEO0_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u16 & 0x01) << 12); + self.w + } +} +#[doc = "Field `MCEO1` reader - MC Event Output Enable 1"] +pub struct MCEO1_R(crate::FieldReader); +impl MCEO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO1` writer - MC Event Output Enable 1"] +pub struct MCEO1_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u16 & 0x01) << 13); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Event Action"] + #[inline(always)] + pub fn evact(&self) -> EVACT_R { + EVACT_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 4 - TC Event Input Polarity"] + #[inline(always)] + pub fn tcinv(&self) -> TCINV_R { + TCINV_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - TC Event Enable"] + #[inline(always)] + pub fn tcei(&self) -> TCEI_R { + TCEI_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 8 - Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&self) -> OVFEO_R { + OVFEO_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 12 - MC Event Output Enable 0"] + #[inline(always)] + pub fn mceo0(&self) -> MCEO0_R { + MCEO0_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - MC Event Output Enable 1"] + #[inline(always)] + pub fn mceo1(&self) -> MCEO1_R { + MCEO1_R::new(((self.bits >> 13) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Event Action"] + #[inline(always)] + pub fn evact(&mut self) -> EVACT_W { + EVACT_W { w: self } + } + #[doc = "Bit 4 - TC Event Input Polarity"] + #[inline(always)] + pub fn tcinv(&mut self) -> TCINV_W { + TCINV_W { w: self } + } + #[doc = "Bit 5 - TC Event Enable"] + #[inline(always)] + pub fn tcei(&mut self) -> TCEI_W { + TCEI_W { w: self } + } + #[doc = "Bit 8 - Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&mut self) -> OVFEO_W { + OVFEO_W { w: self } + } + #[doc = "Bit 12 - MC Event Output Enable 0"] + #[inline(always)] + pub fn mceo0(&mut self) -> MCEO0_W { + MCEO0_W { w: self } + } + #[doc = "Bit 13 - MC Event Output Enable 1"] + #[inline(always)] + pub fn mceo1(&mut self) -> MCEO1_W { + MCEO1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/tc0/count32/intenclr.rs b/pac/atsamc21e/src/tc0/count32/intenclr.rs new file mode 100644 index 000000000000..af01ef5b7dca --- /dev/null +++ b/pac/atsamc21e/src/tc0/count32/intenclr.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - OVF Interrupt Disable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - OVF Interrupt Disable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - ERR Interrupt Disable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - ERR Interrupt Disable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MC0` reader - MC Interrupt Disable 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - MC Interrupt Disable 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - MC Interrupt Disable 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - MC Interrupt Disable 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - OVF Interrupt Disable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ERR Interrupt Disable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - MC Interrupt Disable 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - MC Interrupt Disable 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - OVF Interrupt Disable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - ERR Interrupt Disable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 4 - MC Interrupt Disable 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - MC Interrupt Disable 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/tc0/count32/intenset.rs b/pac/atsamc21e/src/tc0/count32/intenset.rs new file mode 100644 index 000000000000..0e1883a2f20a --- /dev/null +++ b/pac/atsamc21e/src/tc0/count32/intenset.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - OVF Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - OVF Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - ERR Interrupt Enable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - ERR Interrupt Enable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MC0` reader - MC Interrupt Enable 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - MC Interrupt Enable 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - MC Interrupt Enable 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - MC Interrupt Enable 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - OVF Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ERR Interrupt Enable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - MC Interrupt Enable 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - MC Interrupt Enable 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - OVF Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - ERR Interrupt Enable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 4 - MC Interrupt Enable 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - MC Interrupt Enable 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/tc0/count32/intflag.rs b/pac/atsamc21e/src/tc0/count32/intflag.rs new file mode 100644 index 000000000000..1dddffaf8e7f --- /dev/null +++ b/pac/atsamc21e/src/tc0/count32/intflag.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - OVF Interrupt Flag"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - OVF Interrupt Flag"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - ERR Interrupt Flag"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - ERR Interrupt Flag"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MC0` reader - MC Interrupt Flag 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - MC Interrupt Flag 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - MC Interrupt Flag 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - MC Interrupt Flag 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - OVF Interrupt Flag"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ERR Interrupt Flag"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - MC Interrupt Flag 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - MC Interrupt Flag 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - OVF Interrupt Flag"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - ERR Interrupt Flag"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 4 - MC Interrupt Flag 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - MC Interrupt Flag 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/tc0/count32/status.rs b/pac/atsamc21e/src/tc0/count32/status.rs new file mode 100644 index 000000000000..5088af446830 --- /dev/null +++ b/pac/atsamc21e/src/tc0/count32/status.rs @@ -0,0 +1,301 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `STOP` reader - Stop Status Flag"] +pub struct STOP_R(crate::FieldReader); +impl STOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STOP` writer - Stop Status Flag"] +pub struct STOP_W<'a> { + w: &'a mut W, +} +impl<'a> STOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SLAVE` reader - Slave Status Flag"] +pub struct SLAVE_R(crate::FieldReader); +impl SLAVE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLAVE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SLAVE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLAVE` writer - Slave Status Flag"] +pub struct SLAVE_W<'a> { + w: &'a mut W, +} +impl<'a> SLAVE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PERBUFV` reader - Synchronization Busy Status"] +pub struct PERBUFV_R(crate::FieldReader); +impl PERBUFV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PERBUFV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERBUFV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERBUFV` writer - Synchronization Busy Status"] +pub struct PERBUFV_W<'a> { + w: &'a mut W, +} +impl<'a> PERBUFV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CCBUFV0` reader - Compare channel buffer 0 valid"] +pub struct CCBUFV0_R(crate::FieldReader); +impl CCBUFV0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBUFV0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUFV0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUFV0` writer - Compare channel buffer 0 valid"] +pub struct CCBUFV0_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUFV0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `CCBUFV1` reader - Compare channel buffer 1 valid"] +pub struct CCBUFV1_R(crate::FieldReader); +impl CCBUFV1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBUFV1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUFV1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUFV1` writer - Compare channel buffer 1 valid"] +pub struct CCBUFV1_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUFV1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Stop Status Flag"] + #[inline(always)] + pub fn stop(&self) -> STOP_R { + STOP_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Slave Status Flag"] + #[inline(always)] + pub fn slave(&self) -> SLAVE_R { + SLAVE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 3 - Synchronization Busy Status"] + #[inline(always)] + pub fn perbufv(&self) -> PERBUFV_R { + PERBUFV_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Compare channel buffer 0 valid"] + #[inline(always)] + pub fn ccbufv0(&self) -> CCBUFV0_R { + CCBUFV0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Compare channel buffer 1 valid"] + #[inline(always)] + pub fn ccbufv1(&self) -> CCBUFV1_R { + CCBUFV1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Stop Status Flag"] + #[inline(always)] + pub fn stop(&mut self) -> STOP_W { + STOP_W { w: self } + } + #[doc = "Bit 1 - Slave Status Flag"] + #[inline(always)] + pub fn slave(&mut self) -> SLAVE_W { + SLAVE_W { w: self } + } + #[doc = "Bit 3 - Synchronization Busy Status"] + #[inline(always)] + pub fn perbufv(&mut self) -> PERBUFV_W { + PERBUFV_W { w: self } + } + #[doc = "Bit 4 - Compare channel buffer 0 valid"] + #[inline(always)] + pub fn ccbufv0(&mut self) -> CCBUFV0_W { + CCBUFV0_W { w: self } + } + #[doc = "Bit 5 - Compare channel buffer 1 valid"] + #[inline(always)] + pub fn ccbufv1(&mut self) -> CCBUFV1_W { + CCBUFV1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0x01"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pac/atsamc21e/src/tc0/count32/syncbusy.rs b/pac/atsamc21e/src/tc0/count32/syncbusy.rs new file mode 100644 index 000000000000..7ad8d91a84de --- /dev/null +++ b/pac/atsamc21e/src/tc0/count32/syncbusy.rs @@ -0,0 +1,193 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - swrst"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLB` reader - CTRLB"] +pub struct CTRLB_R(crate::FieldReader); +impl CTRLB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STATUS` reader - STATUS"] +pub struct STATUS_R(crate::FieldReader); +impl STATUS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STATUS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STATUS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` reader - Counter"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` reader - Period"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC0` reader - Compare Channel 0"] +pub struct CC0_R(crate::FieldReader); +impl CC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC1` reader - Compare Channel 1"] +pub struct CC1_R(crate::FieldReader); +impl CC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - swrst"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - CTRLB"] + #[inline(always)] + pub fn ctrlb(&self) -> CTRLB_R { + CTRLB_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - STATUS"] + #[inline(always)] + pub fn status(&self) -> STATUS_R { + STATUS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Counter"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Period"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Compare Channel 0"] + #[inline(always)] + pub fn cc0(&self) -> CC0_R { + CC0_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Compare Channel 1"] + #[inline(always)] + pub fn cc1(&self) -> CC1_R { + CC1_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +#[doc = "Synchronization Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/tc0/count32/wave.rs b/pac/atsamc21e/src/tc0/count32/wave.rs new file mode 100644 index 000000000000..46061b24b75d --- /dev/null +++ b/pac/atsamc21e/src/tc0/count32/wave.rs @@ -0,0 +1,178 @@ +#[doc = "Register `WAVE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WAVE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Waveform Generation Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WAVEGEN_A { + #[doc = "0: Normal frequency"] + NFRQ = 0, + #[doc = "1: Match frequency"] + MFRQ = 1, + #[doc = "2: Normal PWM"] + NPWM = 2, + #[doc = "3: Match PWM"] + MPWM = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WAVEGEN_A) -> Self { + variant as _ + } +} +#[doc = "Field `WAVEGEN` reader - Waveform Generation Mode"] +pub struct WAVEGEN_R(crate::FieldReader); +impl WAVEGEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WAVEGEN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> WAVEGEN_A { + match self.bits { + 0 => WAVEGEN_A::NFRQ, + 1 => WAVEGEN_A::MFRQ, + 2 => WAVEGEN_A::NPWM, + 3 => WAVEGEN_A::MPWM, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NFRQ`"] + #[inline(always)] + pub fn is_nfrq(&self) -> bool { + **self == WAVEGEN_A::NFRQ + } + #[doc = "Checks if the value of the field is `MFRQ`"] + #[inline(always)] + pub fn is_mfrq(&self) -> bool { + **self == WAVEGEN_A::MFRQ + } + #[doc = "Checks if the value of the field is `NPWM`"] + #[inline(always)] + pub fn is_npwm(&self) -> bool { + **self == WAVEGEN_A::NPWM + } + #[doc = "Checks if the value of the field is `MPWM`"] + #[inline(always)] + pub fn is_mpwm(&self) -> bool { + **self == WAVEGEN_A::MPWM + } +} +impl core::ops::Deref for WAVEGEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAVEGEN` writer - Waveform Generation Mode"] +pub struct WAVEGEN_W<'a> { + w: &'a mut W, +} +impl<'a> WAVEGEN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WAVEGEN_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Normal frequency"] + #[inline(always)] + pub fn nfrq(self) -> &'a mut W { + self.variant(WAVEGEN_A::NFRQ) + } + #[doc = "Match frequency"] + #[inline(always)] + pub fn mfrq(self) -> &'a mut W { + self.variant(WAVEGEN_A::MFRQ) + } + #[doc = "Normal PWM"] + #[inline(always)] + pub fn npwm(self) -> &'a mut W { + self.variant(WAVEGEN_A::NPWM) + } + #[doc = "Match PWM"] + #[inline(always)] + pub fn mpwm(self) -> &'a mut W { + self.variant(WAVEGEN_A::MPWM) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u8 & 0x03); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Waveform Generation Mode"] + #[inline(always)] + pub fn wavegen(&self) -> WAVEGEN_R { + WAVEGEN_R::new((self.bits & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Waveform Generation Mode"] + #[inline(always)] + pub fn wavegen(&mut self) -> WAVEGEN_W { + WAVEGEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Waveform Generation Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wave](index.html) module"] +pub struct WAVE_SPEC; +impl crate::RegisterSpec for WAVE_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [wave::R](R) reader structure"] +impl crate::Readable for WAVE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wave::W](W) writer structure"] +impl crate::Writable for WAVE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WAVE to value 0"] +impl crate::Resettable for WAVE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/tc0/count8.rs b/pac/atsamc21e/src/tc0/count8.rs new file mode 100644 index 000000000000..777da5744358 --- /dev/null +++ b/pac/atsamc21e/src/tc0/count8.rs @@ -0,0 +1,68 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "CTRLBCLR register accessor: an alias for `Reg`"] +pub type CTRLBCLR = crate::Reg; +#[doc = "Control B Clear"] +pub mod ctrlbclr; +#[doc = "CTRLBSET register accessor: an alias for `Reg`"] +pub type CTRLBSET = crate::Reg; +#[doc = "Control B Set"] +pub mod ctrlbset; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "WAVE register accessor: an alias for `Reg`"] +pub type WAVE = crate::Reg; +#[doc = "Waveform Generation Control"] +pub mod wave; +#[doc = "DRVCTRL register accessor: an alias for `Reg`"] +pub type DRVCTRL = crate::Reg; +#[doc = "Control C"] +pub mod drvctrl; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Status"] +pub mod syncbusy; +#[doc = "COUNT register accessor: an alias for `Reg`"] +pub type COUNT = crate::Reg; +#[doc = "COUNT8 Count"] +pub mod count; +#[doc = "PER register accessor: an alias for `Reg`"] +pub type PER = crate::Reg; +#[doc = "COUNT8 Period"] +pub mod per; +#[doc = "CC register accessor: an alias for `Reg`"] +pub type CC = crate::Reg; +#[doc = "COUNT8 Compare and Capture"] +pub mod cc; +#[doc = "PERBUF register accessor: an alias for `Reg`"] +pub type PERBUF = crate::Reg; +#[doc = "COUNT8 Period Buffer"] +pub mod perbuf; +#[doc = "CCBUF register accessor: an alias for `Reg`"] +pub type CCBUF = crate::Reg; +#[doc = "COUNT8 Compare and Capture Buffer"] +pub mod ccbuf; diff --git a/pac/atsamc21e/src/tc0/count8/cc.rs b/pac/atsamc21e/src/tc0/count8/cc.rs new file mode 100644 index 000000000000..45f5c29c89af --- /dev/null +++ b/pac/atsamc21e/src/tc0/count8/cc.rs @@ -0,0 +1,104 @@ +#[doc = "Register `CC[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CC[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CC` reader - Counter/Compare Value"] +pub struct CC_R(crate::FieldReader); +impl CC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC` writer - Counter/Compare Value"] +pub struct CC_W<'a> { + w: &'a mut W, +} +impl<'a> CC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Counter/Compare Value"] + #[inline(always)] + pub fn cc(&self) -> CC_R { + CC_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Counter/Compare Value"] + #[inline(always)] + pub fn cc(&mut self) -> CC_W { + CC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT8 Compare and Capture\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc](index.html) module"] +pub struct CC_SPEC; +impl crate::RegisterSpec for CC_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [cc::R](R) reader structure"] +impl crate::Readable for CC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cc::W](W) writer structure"] +impl crate::Writable for CC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CC[%s] +to value 0"] +impl crate::Resettable for CC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/tc0/count8/ccbuf.rs b/pac/atsamc21e/src/tc0/count8/ccbuf.rs new file mode 100644 index 000000000000..cd81b1219860 --- /dev/null +++ b/pac/atsamc21e/src/tc0/count8/ccbuf.rs @@ -0,0 +1,104 @@ +#[doc = "Register `CCBUF[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CCBUF[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CCBUF` reader - Counter/Compare Buffer Value"] +pub struct CCBUF_R(crate::FieldReader); +impl CCBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CCBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUF` writer - Counter/Compare Buffer Value"] +pub struct CCBUF_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Counter/Compare Buffer Value"] + #[inline(always)] + pub fn ccbuf(&self) -> CCBUF_R { + CCBUF_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Counter/Compare Buffer Value"] + #[inline(always)] + pub fn ccbuf(&mut self) -> CCBUF_W { + CCBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT8 Compare and Capture Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccbuf](index.html) module"] +pub struct CCBUF_SPEC; +impl crate::RegisterSpec for CCBUF_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ccbuf::R](R) reader structure"] +impl crate::Readable for CCBUF_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ccbuf::W](W) writer structure"] +impl crate::Writable for CCBUF_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CCBUF[%s] +to value 0"] +impl crate::Resettable for CCBUF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/tc0/count8/count.rs b/pac/atsamc21e/src/tc0/count8/count.rs new file mode 100644 index 000000000000..0edbb0f17bb7 --- /dev/null +++ b/pac/atsamc21e/src/tc0/count8/count.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT8 Count\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count](index.html) module"] +pub struct COUNT_SPEC; +impl crate::RegisterSpec for COUNT_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [count::R](R) reader structure"] +impl crate::Readable for COUNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count::W](W) writer structure"] +impl crate::Writable for COUNT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT to value 0"] +impl crate::Resettable for COUNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/tc0/count8/ctrla.rs b/pac/atsamc21e/src/tc0/count8/ctrla.rs new file mode 100644 index 000000000000..cadcddaaead8 --- /dev/null +++ b/pac/atsamc21e/src/tc0/count8/ctrla.rs @@ -0,0 +1,851 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Timer Counter Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: Counter in 16-bit mode"] + COUNT16 = 0, + #[doc = "1: Counter in 8-bit mode"] + COUNT8 = 1, + #[doc = "2: Counter in 32-bit mode"] + COUNT32 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Timer Counter Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::COUNT16), + 1 => Some(MODE_A::COUNT8), + 2 => Some(MODE_A::COUNT32), + _ => None, + } + } + #[doc = "Checks if the value of the field is `COUNT16`"] + #[inline(always)] + pub fn is_count16(&self) -> bool { + **self == MODE_A::COUNT16 + } + #[doc = "Checks if the value of the field is `COUNT8`"] + #[inline(always)] + pub fn is_count8(&self) -> bool { + **self == MODE_A::COUNT8 + } + #[doc = "Checks if the value of the field is `COUNT32`"] + #[inline(always)] + pub fn is_count32(&self) -> bool { + **self == MODE_A::COUNT32 + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Timer Counter Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Counter in 16-bit mode"] + #[inline(always)] + pub fn count16(self) -> &'a mut W { + self.variant(MODE_A::COUNT16) + } + #[doc = "Counter in 8-bit mode"] + #[inline(always)] + pub fn count8(self) -> &'a mut W { + self.variant(MODE_A::COUNT8) + } + #[doc = "Counter in 32-bit mode"] + #[inline(always)] + pub fn count32(self) -> &'a mut W { + self.variant(MODE_A::COUNT32) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u32 & 0x03) << 2); + self.w + } +} +#[doc = "Prescaler and Counter Synchronization\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCSYNC_A { + #[doc = "0: Reload or reset the counter on next generic clock"] + GCLK = 0, + #[doc = "1: Reload or reset the counter on next prescaler clock"] + PRESC = 1, + #[doc = "2: Reload or reset the counter on next generic clock and reset the prescaler counter"] + RESYNC = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCSYNC_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCSYNC` reader - Prescaler and Counter Synchronization"] +pub struct PRESCSYNC_R(crate::FieldReader); +impl PRESCSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCSYNC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCSYNC_A::GCLK), + 1 => Some(PRESCSYNC_A::PRESC), + 2 => Some(PRESCSYNC_A::RESYNC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `GCLK`"] + #[inline(always)] + pub fn is_gclk(&self) -> bool { + **self == PRESCSYNC_A::GCLK + } + #[doc = "Checks if the value of the field is `PRESC`"] + #[inline(always)] + pub fn is_presc(&self) -> bool { + **self == PRESCSYNC_A::PRESC + } + #[doc = "Checks if the value of the field is `RESYNC`"] + #[inline(always)] + pub fn is_resync(&self) -> bool { + **self == PRESCSYNC_A::RESYNC + } +} +impl core::ops::Deref for PRESCSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCSYNC` writer - Prescaler and Counter Synchronization"] +pub struct PRESCSYNC_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCSYNC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCSYNC_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Reload or reset the counter on next generic clock"] + #[inline(always)] + pub fn gclk(self) -> &'a mut W { + self.variant(PRESCSYNC_A::GCLK) + } + #[doc = "Reload or reset the counter on next prescaler clock"] + #[inline(always)] + pub fn presc(self) -> &'a mut W { + self.variant(PRESCSYNC_A::PRESC) + } + #[doc = "Reload or reset the counter on next generic clock and reset the prescaler counter"] + #[inline(always)] + pub fn resync(self) -> &'a mut W { + self.variant(PRESCSYNC_A::RESYNC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u32 & 0x03) << 4); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - Clock On Demand"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - Clock On Demand"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: Prescaler: GCLK_TC"] + DIV1 = 0, + #[doc = "1: Prescaler: GCLK_TC/2"] + DIV2 = 1, + #[doc = "2: Prescaler: GCLK_TC/4"] + DIV4 = 2, + #[doc = "3: Prescaler: GCLK_TC/8"] + DIV8 = 3, + #[doc = "4: Prescaler: GCLK_TC/16"] + DIV16 = 4, + #[doc = "5: Prescaler: GCLK_TC/64"] + DIV64 = 5, + #[doc = "6: Prescaler: GCLK_TC/256"] + DIV256 = 6, + #[doc = "7: Prescaler: GCLK_TC/1024"] + DIV1024 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PRESCALER_A { + match self.bits { + 0 => PRESCALER_A::DIV1, + 1 => PRESCALER_A::DIV2, + 2 => PRESCALER_A::DIV4, + 3 => PRESCALER_A::DIV8, + 4 => PRESCALER_A::DIV16, + 5 => PRESCALER_A::DIV64, + 6 => PRESCALER_A::DIV256, + 7 => PRESCALER_A::DIV1024, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == PRESCALER_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PRESCALER_A::DIV1024 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Prescaler: GCLK_TC"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1) + } + #[doc = "Prescaler: GCLK_TC/2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "Prescaler: GCLK_TC/4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "Prescaler: GCLK_TC/8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "Prescaler: GCLK_TC/16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "Prescaler: GCLK_TC/64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "Prescaler: GCLK_TC/256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = "Prescaler: GCLK_TC/1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +#[doc = "Field `ALOCK` reader - Auto Lock"] +pub struct ALOCK_R(crate::FieldReader); +impl ALOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALOCK` writer - Auto Lock"] +pub struct ALOCK_W<'a> { + w: &'a mut W, +} +impl<'a> ALOCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `CAPTEN0` reader - Capture Channel 0 Enable"] +pub struct CAPTEN0_R(crate::FieldReader); +impl CAPTEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CAPTEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CAPTEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAPTEN0` writer - Capture Channel 0 Enable"] +pub struct CAPTEN0_W<'a> { + w: &'a mut W, +} +impl<'a> CAPTEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `CAPTEN1` reader - Capture Channel 1 Enable"] +pub struct CAPTEN1_R(crate::FieldReader); +impl CAPTEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CAPTEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CAPTEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAPTEN1` writer - Capture Channel 1 Enable"] +pub struct CAPTEN1_W<'a> { + w: &'a mut W, +} +impl<'a> CAPTEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `COPEN0` reader - Capture On Pin 0 Enable"] +pub struct COPEN0_R(crate::FieldReader); +impl COPEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COPEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COPEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COPEN0` writer - Capture On Pin 0 Enable"] +pub struct COPEN0_W<'a> { + w: &'a mut W, +} +impl<'a> COPEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `COPEN1` reader - Capture On Pin 1 Enable"] +pub struct COPEN1_R(crate::FieldReader); +impl COPEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COPEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COPEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COPEN1` writer - Capture On Pin 1 Enable"] +pub struct COPEN1_W<'a> { + w: &'a mut W, +} +impl<'a> COPEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:3 - Timer Counter Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bits 4:5 - Prescaler and Counter Synchronization"] + #[inline(always)] + pub fn prescsync(&self) -> PRESCSYNC_R { + PRESCSYNC_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Clock On Demand"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 11 - Auto Lock"] + #[inline(always)] + pub fn alock(&self) -> ALOCK_R { + ALOCK_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 16 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn capten0(&self) -> CAPTEN0_R { + CAPTEN0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn capten1(&self) -> CAPTEN1_R { + CAPTEN1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 20 - Capture On Pin 0 Enable"] + #[inline(always)] + pub fn copen0(&self) -> COPEN0_R { + COPEN0_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Capture On Pin 1 Enable"] + #[inline(always)] + pub fn copen1(&self) -> COPEN1_R { + COPEN1_R::new(((self.bits >> 21) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:3 - Timer Counter Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bits 4:5 - Prescaler and Counter Synchronization"] + #[inline(always)] + pub fn prescsync(&mut self) -> PRESCSYNC_W { + PRESCSYNC_W { w: self } + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - Clock On Demand"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Bit 11 - Auto Lock"] + #[inline(always)] + pub fn alock(&mut self) -> ALOCK_W { + ALOCK_W { w: self } + } + #[doc = "Bit 16 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn capten0(&mut self) -> CAPTEN0_W { + CAPTEN0_W { w: self } + } + #[doc = "Bit 17 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn capten1(&mut self) -> CAPTEN1_W { + CAPTEN1_W { w: self } + } + #[doc = "Bit 20 - Capture On Pin 0 Enable"] + #[inline(always)] + pub fn copen0(&mut self) -> COPEN0_W { + COPEN0_W { w: self } + } + #[doc = "Bit 21 - Capture On Pin 1 Enable"] + #[inline(always)] + pub fn copen1(&mut self) -> COPEN1_W { + COPEN1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/tc0/count8/ctrlbclr.rs b/pac/atsamc21e/src/tc0/count8/ctrlbclr.rs new file mode 100644 index 000000000000..76265674036a --- /dev/null +++ b/pac/atsamc21e/src/tc0/count8/ctrlbclr.rs @@ -0,0 +1,345 @@ +#[doc = "Register `CTRLBCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Counter Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `LUPD` reader - Lock Update"] +pub struct LUPD_R(crate::FieldReader); +impl LUPD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LUPD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LUPD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LUPD` writer - Lock Update"] +pub struct LUPD_W<'a> { + w: &'a mut W, +} +impl<'a> LUPD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ONESHOT` reader - One-Shot on Counter"] +pub struct ONESHOT_R(crate::FieldReader); +impl ONESHOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONESHOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONESHOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONESHOT` writer - One-Shot on Counter"] +pub struct ONESHOT_W<'a> { + w: &'a mut W, +} +impl<'a> ONESHOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Force a start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force a stop"] + STOP = 2, + #[doc = "3: Force update of double-buffered register"] + UPDATE = 3, + #[doc = "4: Force a read synchronization of COUNT"] + READSYNC = 4, + #[doc = "5: One-shot DMA trigger"] + DMAOS = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NONE), + 1 => Some(CMD_A::RETRIGGER), + 2 => Some(CMD_A::STOP), + 3 => Some(CMD_A::UPDATE), + 4 => Some(CMD_A::READSYNC), + 5 => Some(CMD_A::DMAOS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == CMD_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == CMD_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == CMD_A::STOP + } + #[doc = "Checks if the value of the field is `UPDATE`"] + #[inline(always)] + pub fn is_update(&self) -> bool { + **self == CMD_A::UPDATE + } + #[doc = "Checks if the value of the field is `READSYNC`"] + #[inline(always)] + pub fn is_readsync(&self) -> bool { + **self == CMD_A::READSYNC + } + #[doc = "Checks if the value of the field is `DMAOS`"] + #[inline(always)] + pub fn is_dmaos(&self) -> bool { + **self == CMD_A::DMAOS + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMD_A::NONE) + } + #[doc = "Force a start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMD_A::RETRIGGER) + } + #[doc = "Force a stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMD_A::STOP) + } + #[doc = "Force update of double-buffered register"] + #[inline(always)] + pub fn update(self) -> &'a mut W { + self.variant(CMD_A::UPDATE) + } + #[doc = "Force a read synchronization of COUNT"] + #[inline(always)] + pub fn readsync(self) -> &'a mut W { + self.variant(CMD_A::READSYNC) + } + #[doc = "One-shot DMA trigger"] + #[inline(always)] + pub fn dmaos(self) -> &'a mut W { + self.variant(CMD_A::DMAOS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 5)) | ((value as u8 & 0x07) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&self) -> LUPD_R { + LUPD_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 5) & 0x07) as u8) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&mut self) -> LUPD_W { + LUPD_W { w: self } + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&mut self) -> ONESHOT_W { + ONESHOT_W { w: self } + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbclr](index.html) module"] +pub struct CTRLBCLR_SPEC; +impl crate::RegisterSpec for CTRLBCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbclr::R](R) reader structure"] +impl crate::Readable for CTRLBCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbclr::W](W) writer structure"] +impl crate::Writable for CTRLBCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLBCLR to value 0"] +impl crate::Resettable for CTRLBCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/tc0/count8/ctrlbset.rs b/pac/atsamc21e/src/tc0/count8/ctrlbset.rs new file mode 100644 index 000000000000..610914c9c7c8 --- /dev/null +++ b/pac/atsamc21e/src/tc0/count8/ctrlbset.rs @@ -0,0 +1,345 @@ +#[doc = "Register `CTRLBSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Counter Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `LUPD` reader - Lock Update"] +pub struct LUPD_R(crate::FieldReader); +impl LUPD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LUPD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LUPD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LUPD` writer - Lock Update"] +pub struct LUPD_W<'a> { + w: &'a mut W, +} +impl<'a> LUPD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ONESHOT` reader - One-Shot on Counter"] +pub struct ONESHOT_R(crate::FieldReader); +impl ONESHOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONESHOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONESHOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONESHOT` writer - One-Shot on Counter"] +pub struct ONESHOT_W<'a> { + w: &'a mut W, +} +impl<'a> ONESHOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Force a start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force a stop"] + STOP = 2, + #[doc = "3: Force update of double-buffered register"] + UPDATE = 3, + #[doc = "4: Force a read synchronization of COUNT"] + READSYNC = 4, + #[doc = "5: One-shot DMA trigger"] + DMAOS = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NONE), + 1 => Some(CMD_A::RETRIGGER), + 2 => Some(CMD_A::STOP), + 3 => Some(CMD_A::UPDATE), + 4 => Some(CMD_A::READSYNC), + 5 => Some(CMD_A::DMAOS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == CMD_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == CMD_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == CMD_A::STOP + } + #[doc = "Checks if the value of the field is `UPDATE`"] + #[inline(always)] + pub fn is_update(&self) -> bool { + **self == CMD_A::UPDATE + } + #[doc = "Checks if the value of the field is `READSYNC`"] + #[inline(always)] + pub fn is_readsync(&self) -> bool { + **self == CMD_A::READSYNC + } + #[doc = "Checks if the value of the field is `DMAOS`"] + #[inline(always)] + pub fn is_dmaos(&self) -> bool { + **self == CMD_A::DMAOS + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMD_A::NONE) + } + #[doc = "Force a start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMD_A::RETRIGGER) + } + #[doc = "Force a stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMD_A::STOP) + } + #[doc = "Force update of double-buffered register"] + #[inline(always)] + pub fn update(self) -> &'a mut W { + self.variant(CMD_A::UPDATE) + } + #[doc = "Force a read synchronization of COUNT"] + #[inline(always)] + pub fn readsync(self) -> &'a mut W { + self.variant(CMD_A::READSYNC) + } + #[doc = "One-shot DMA trigger"] + #[inline(always)] + pub fn dmaos(self) -> &'a mut W { + self.variant(CMD_A::DMAOS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 5)) | ((value as u8 & 0x07) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&self) -> LUPD_R { + LUPD_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 5) & 0x07) as u8) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&mut self) -> LUPD_W { + LUPD_W { w: self } + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&mut self) -> ONESHOT_W { + ONESHOT_W { w: self } + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbset](index.html) module"] +pub struct CTRLBSET_SPEC; +impl crate::RegisterSpec for CTRLBSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbset::R](R) reader structure"] +impl crate::Readable for CTRLBSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbset::W](W) writer structure"] +impl crate::Writable for CTRLBSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLBSET to value 0"] +impl crate::Resettable for CTRLBSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/tc0/count8/dbgctrl.rs b/pac/atsamc21e/src/tc0/count8/dbgctrl.rs new file mode 100644 index 000000000000..0383e70d0429 --- /dev/null +++ b/pac/atsamc21e/src/tc0/count8/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Run During Debug"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Run During Debug"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/tc0/count8/drvctrl.rs b/pac/atsamc21e/src/tc0/count8/drvctrl.rs new file mode 100644 index 000000000000..323926b4b22d --- /dev/null +++ b/pac/atsamc21e/src/tc0/count8/drvctrl.rs @@ -0,0 +1,160 @@ +#[doc = "Register `DRVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DRVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INVEN0` reader - Output Waveform Invert Enable 0"] +pub struct INVEN0_R(crate::FieldReader); +impl INVEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN0` writer - Output Waveform Invert Enable 0"] +pub struct INVEN0_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `INVEN1` reader - Output Waveform Invert Enable 1"] +pub struct INVEN1_R(crate::FieldReader); +impl INVEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN1` writer - Output Waveform Invert Enable 1"] +pub struct INVEN1_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - Output Waveform Invert Enable 0"] + #[inline(always)] + pub fn inven0(&self) -> INVEN0_R { + INVEN0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Output Waveform Invert Enable 1"] + #[inline(always)] + pub fn inven1(&self) -> INVEN1_R { + INVEN1_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Output Waveform Invert Enable 0"] + #[inline(always)] + pub fn inven0(&mut self) -> INVEN0_W { + INVEN0_W { w: self } + } + #[doc = "Bit 1 - Output Waveform Invert Enable 1"] + #[inline(always)] + pub fn inven1(&mut self) -> INVEN1_W { + INVEN1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control C\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [drvctrl](index.html) module"] +pub struct DRVCTRL_SPEC; +impl crate::RegisterSpec for DRVCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [drvctrl::R](R) reader structure"] +impl crate::Readable for DRVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [drvctrl::W](W) writer structure"] +impl crate::Writable for DRVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DRVCTRL to value 0"] +impl crate::Resettable for DRVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/tc0/count8/evctrl.rs b/pac/atsamc21e/src/tc0/count8/evctrl.rs new file mode 100644 index 000000000000..7d4c38d486c1 --- /dev/null +++ b/pac/atsamc21e/src/tc0/count8/evctrl.rs @@ -0,0 +1,465 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Event Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EVACT_A { + #[doc = "0: Event action disabled"] + OFF = 0, + #[doc = "1: Start, restart or retrigger TC on event"] + RETRIGGER = 1, + #[doc = "2: Count on event"] + COUNT = 2, + #[doc = "3: Start TC on event"] + START = 3, + #[doc = "4: Time stamp capture"] + STAMP = 4, + #[doc = "5: Period catured in CC0, pulse width in CC1"] + PPW = 5, + #[doc = "6: Period catured in CC1, pulse width in CC0"] + PWP = 6, + #[doc = "7: Pulse width capture"] + PW = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EVACT_A) -> Self { + variant as _ + } +} +#[doc = "Field `EVACT` reader - Event Action"] +pub struct EVACT_R(crate::FieldReader); +impl EVACT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVACT_A { + match self.bits { + 0 => EVACT_A::OFF, + 1 => EVACT_A::RETRIGGER, + 2 => EVACT_A::COUNT, + 3 => EVACT_A::START, + 4 => EVACT_A::STAMP, + 5 => EVACT_A::PPW, + 6 => EVACT_A::PWP, + 7 => EVACT_A::PW, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == EVACT_A::OFF + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == EVACT_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `COUNT`"] + #[inline(always)] + pub fn is_count(&self) -> bool { + **self == EVACT_A::COUNT + } + #[doc = "Checks if the value of the field is `START`"] + #[inline(always)] + pub fn is_start(&self) -> bool { + **self == EVACT_A::START + } + #[doc = "Checks if the value of the field is `STAMP`"] + #[inline(always)] + pub fn is_stamp(&self) -> bool { + **self == EVACT_A::STAMP + } + #[doc = "Checks if the value of the field is `PPW`"] + #[inline(always)] + pub fn is_ppw(&self) -> bool { + **self == EVACT_A::PPW + } + #[doc = "Checks if the value of the field is `PWP`"] + #[inline(always)] + pub fn is_pwp(&self) -> bool { + **self == EVACT_A::PWP + } + #[doc = "Checks if the value of the field is `PW`"] + #[inline(always)] + pub fn is_pw(&self) -> bool { + **self == EVACT_A::PW + } +} +impl core::ops::Deref for EVACT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT` writer - Event Action"] +pub struct EVACT_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EVACT_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Event action disabled"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(EVACT_A::OFF) + } + #[doc = "Start, restart or retrigger TC on event"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(EVACT_A::RETRIGGER) + } + #[doc = "Count on event"] + #[inline(always)] + pub fn count(self) -> &'a mut W { + self.variant(EVACT_A::COUNT) + } + #[doc = "Start TC on event"] + #[inline(always)] + pub fn start(self) -> &'a mut W { + self.variant(EVACT_A::START) + } + #[doc = "Time stamp capture"] + #[inline(always)] + pub fn stamp(self) -> &'a mut W { + self.variant(EVACT_A::STAMP) + } + #[doc = "Period catured in CC0, pulse width in CC1"] + #[inline(always)] + pub fn ppw(self) -> &'a mut W { + self.variant(EVACT_A::PPW) + } + #[doc = "Period catured in CC1, pulse width in CC0"] + #[inline(always)] + pub fn pwp(self) -> &'a mut W { + self.variant(EVACT_A::PWP) + } + #[doc = "Pulse width capture"] + #[inline(always)] + pub fn pw(self) -> &'a mut W { + self.variant(EVACT_A::PW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u16 & 0x07); + self.w + } +} +#[doc = "Field `TCINV` reader - TC Event Input Polarity"] +pub struct TCINV_R(crate::FieldReader); +impl TCINV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCINV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCINV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCINV` writer - TC Event Input Polarity"] +pub struct TCINV_W<'a> { + w: &'a mut W, +} +impl<'a> TCINV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `TCEI` reader - TC Event Enable"] +pub struct TCEI_R(crate::FieldReader); +impl TCEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCEI` writer - TC Event Enable"] +pub struct TCEI_W<'a> { + w: &'a mut W, +} +impl<'a> TCEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `OVFEO` reader - Event Output Enable"] +pub struct OVFEO_R(crate::FieldReader); +impl OVFEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVFEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVFEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVFEO` writer - Event Output Enable"] +pub struct OVFEO_W<'a> { + w: &'a mut W, +} +impl<'a> OVFEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `MCEO0` reader - MC Event Output Enable 0"] +pub struct MCEO0_R(crate::FieldReader); +impl MCEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO0` writer - MC Event Output Enable 0"] +pub struct MCEO0_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u16 & 0x01) << 12); + self.w + } +} +#[doc = "Field `MCEO1` reader - MC Event Output Enable 1"] +pub struct MCEO1_R(crate::FieldReader); +impl MCEO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO1` writer - MC Event Output Enable 1"] +pub struct MCEO1_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u16 & 0x01) << 13); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Event Action"] + #[inline(always)] + pub fn evact(&self) -> EVACT_R { + EVACT_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 4 - TC Event Input Polarity"] + #[inline(always)] + pub fn tcinv(&self) -> TCINV_R { + TCINV_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - TC Event Enable"] + #[inline(always)] + pub fn tcei(&self) -> TCEI_R { + TCEI_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 8 - Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&self) -> OVFEO_R { + OVFEO_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 12 - MC Event Output Enable 0"] + #[inline(always)] + pub fn mceo0(&self) -> MCEO0_R { + MCEO0_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - MC Event Output Enable 1"] + #[inline(always)] + pub fn mceo1(&self) -> MCEO1_R { + MCEO1_R::new(((self.bits >> 13) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Event Action"] + #[inline(always)] + pub fn evact(&mut self) -> EVACT_W { + EVACT_W { w: self } + } + #[doc = "Bit 4 - TC Event Input Polarity"] + #[inline(always)] + pub fn tcinv(&mut self) -> TCINV_W { + TCINV_W { w: self } + } + #[doc = "Bit 5 - TC Event Enable"] + #[inline(always)] + pub fn tcei(&mut self) -> TCEI_W { + TCEI_W { w: self } + } + #[doc = "Bit 8 - Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&mut self) -> OVFEO_W { + OVFEO_W { w: self } + } + #[doc = "Bit 12 - MC Event Output Enable 0"] + #[inline(always)] + pub fn mceo0(&mut self) -> MCEO0_W { + MCEO0_W { w: self } + } + #[doc = "Bit 13 - MC Event Output Enable 1"] + #[inline(always)] + pub fn mceo1(&mut self) -> MCEO1_W { + MCEO1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/tc0/count8/intenclr.rs b/pac/atsamc21e/src/tc0/count8/intenclr.rs new file mode 100644 index 000000000000..af01ef5b7dca --- /dev/null +++ b/pac/atsamc21e/src/tc0/count8/intenclr.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - OVF Interrupt Disable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - OVF Interrupt Disable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - ERR Interrupt Disable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - ERR Interrupt Disable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MC0` reader - MC Interrupt Disable 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - MC Interrupt Disable 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - MC Interrupt Disable 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - MC Interrupt Disable 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - OVF Interrupt Disable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ERR Interrupt Disable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - MC Interrupt Disable 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - MC Interrupt Disable 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - OVF Interrupt Disable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - ERR Interrupt Disable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 4 - MC Interrupt Disable 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - MC Interrupt Disable 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/tc0/count8/intenset.rs b/pac/atsamc21e/src/tc0/count8/intenset.rs new file mode 100644 index 000000000000..0e1883a2f20a --- /dev/null +++ b/pac/atsamc21e/src/tc0/count8/intenset.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - OVF Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - OVF Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - ERR Interrupt Enable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - ERR Interrupt Enable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MC0` reader - MC Interrupt Enable 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - MC Interrupt Enable 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - MC Interrupt Enable 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - MC Interrupt Enable 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - OVF Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ERR Interrupt Enable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - MC Interrupt Enable 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - MC Interrupt Enable 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - OVF Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - ERR Interrupt Enable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 4 - MC Interrupt Enable 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - MC Interrupt Enable 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/tc0/count8/intflag.rs b/pac/atsamc21e/src/tc0/count8/intflag.rs new file mode 100644 index 000000000000..1dddffaf8e7f --- /dev/null +++ b/pac/atsamc21e/src/tc0/count8/intflag.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - OVF Interrupt Flag"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - OVF Interrupt Flag"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - ERR Interrupt Flag"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - ERR Interrupt Flag"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MC0` reader - MC Interrupt Flag 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - MC Interrupt Flag 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - MC Interrupt Flag 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - MC Interrupt Flag 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - OVF Interrupt Flag"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ERR Interrupt Flag"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - MC Interrupt Flag 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - MC Interrupt Flag 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - OVF Interrupt Flag"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - ERR Interrupt Flag"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 4 - MC Interrupt Flag 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - MC Interrupt Flag 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/tc0/count8/per.rs b/pac/atsamc21e/src/tc0/count8/per.rs new file mode 100644 index 000000000000..c9ab52e247d8 --- /dev/null +++ b/pac/atsamc21e/src/tc0/count8/per.rs @@ -0,0 +1,103 @@ +#[doc = "Register `PER` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PER` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER` reader - Period Value"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` writer - Period Value"] +pub struct PER_W<'a> { + w: &'a mut W, +} +impl<'a> PER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Period Value"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Period Value"] + #[inline(always)] + pub fn per(&mut self) -> PER_W { + PER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT8 Period\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [per](index.html) module"] +pub struct PER_SPEC; +impl crate::RegisterSpec for PER_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [per::R](R) reader structure"] +impl crate::Readable for PER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [per::W](W) writer structure"] +impl crate::Writable for PER_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PER to value 0xff"] +impl crate::Resettable for PER_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xff + } +} diff --git a/pac/atsamc21e/src/tc0/count8/perbuf.rs b/pac/atsamc21e/src/tc0/count8/perbuf.rs new file mode 100644 index 000000000000..cbd500e2bbe1 --- /dev/null +++ b/pac/atsamc21e/src/tc0/count8/perbuf.rs @@ -0,0 +1,103 @@ +#[doc = "Register `PERBUF` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PERBUF` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PERBUF` reader - Period Buffer Value"] +pub struct PERBUF_R(crate::FieldReader); +impl PERBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PERBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERBUF` writer - Period Buffer Value"] +pub struct PERBUF_W<'a> { + w: &'a mut W, +} +impl<'a> PERBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Period Buffer Value"] + #[inline(always)] + pub fn perbuf(&self) -> PERBUF_R { + PERBUF_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Period Buffer Value"] + #[inline(always)] + pub fn perbuf(&mut self) -> PERBUF_W { + PERBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT8 Period Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [perbuf](index.html) module"] +pub struct PERBUF_SPEC; +impl crate::RegisterSpec for PERBUF_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [perbuf::R](R) reader structure"] +impl crate::Readable for PERBUF_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [perbuf::W](W) writer structure"] +impl crate::Writable for PERBUF_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PERBUF to value 0xff"] +impl crate::Resettable for PERBUF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xff + } +} diff --git a/pac/atsamc21e/src/tc0/count8/status.rs b/pac/atsamc21e/src/tc0/count8/status.rs new file mode 100644 index 000000000000..5088af446830 --- /dev/null +++ b/pac/atsamc21e/src/tc0/count8/status.rs @@ -0,0 +1,301 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `STOP` reader - Stop Status Flag"] +pub struct STOP_R(crate::FieldReader); +impl STOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STOP` writer - Stop Status Flag"] +pub struct STOP_W<'a> { + w: &'a mut W, +} +impl<'a> STOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SLAVE` reader - Slave Status Flag"] +pub struct SLAVE_R(crate::FieldReader); +impl SLAVE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLAVE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SLAVE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLAVE` writer - Slave Status Flag"] +pub struct SLAVE_W<'a> { + w: &'a mut W, +} +impl<'a> SLAVE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PERBUFV` reader - Synchronization Busy Status"] +pub struct PERBUFV_R(crate::FieldReader); +impl PERBUFV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PERBUFV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERBUFV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERBUFV` writer - Synchronization Busy Status"] +pub struct PERBUFV_W<'a> { + w: &'a mut W, +} +impl<'a> PERBUFV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CCBUFV0` reader - Compare channel buffer 0 valid"] +pub struct CCBUFV0_R(crate::FieldReader); +impl CCBUFV0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBUFV0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUFV0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUFV0` writer - Compare channel buffer 0 valid"] +pub struct CCBUFV0_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUFV0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `CCBUFV1` reader - Compare channel buffer 1 valid"] +pub struct CCBUFV1_R(crate::FieldReader); +impl CCBUFV1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBUFV1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUFV1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUFV1` writer - Compare channel buffer 1 valid"] +pub struct CCBUFV1_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUFV1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Stop Status Flag"] + #[inline(always)] + pub fn stop(&self) -> STOP_R { + STOP_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Slave Status Flag"] + #[inline(always)] + pub fn slave(&self) -> SLAVE_R { + SLAVE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 3 - Synchronization Busy Status"] + #[inline(always)] + pub fn perbufv(&self) -> PERBUFV_R { + PERBUFV_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Compare channel buffer 0 valid"] + #[inline(always)] + pub fn ccbufv0(&self) -> CCBUFV0_R { + CCBUFV0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Compare channel buffer 1 valid"] + #[inline(always)] + pub fn ccbufv1(&self) -> CCBUFV1_R { + CCBUFV1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Stop Status Flag"] + #[inline(always)] + pub fn stop(&mut self) -> STOP_W { + STOP_W { w: self } + } + #[doc = "Bit 1 - Slave Status Flag"] + #[inline(always)] + pub fn slave(&mut self) -> SLAVE_W { + SLAVE_W { w: self } + } + #[doc = "Bit 3 - Synchronization Busy Status"] + #[inline(always)] + pub fn perbufv(&mut self) -> PERBUFV_W { + PERBUFV_W { w: self } + } + #[doc = "Bit 4 - Compare channel buffer 0 valid"] + #[inline(always)] + pub fn ccbufv0(&mut self) -> CCBUFV0_W { + CCBUFV0_W { w: self } + } + #[doc = "Bit 5 - Compare channel buffer 1 valid"] + #[inline(always)] + pub fn ccbufv1(&mut self) -> CCBUFV1_W { + CCBUFV1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0x01"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pac/atsamc21e/src/tc0/count8/syncbusy.rs b/pac/atsamc21e/src/tc0/count8/syncbusy.rs new file mode 100644 index 000000000000..7ad8d91a84de --- /dev/null +++ b/pac/atsamc21e/src/tc0/count8/syncbusy.rs @@ -0,0 +1,193 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - swrst"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLB` reader - CTRLB"] +pub struct CTRLB_R(crate::FieldReader); +impl CTRLB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STATUS` reader - STATUS"] +pub struct STATUS_R(crate::FieldReader); +impl STATUS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STATUS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STATUS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` reader - Counter"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` reader - Period"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC0` reader - Compare Channel 0"] +pub struct CC0_R(crate::FieldReader); +impl CC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC1` reader - Compare Channel 1"] +pub struct CC1_R(crate::FieldReader); +impl CC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - swrst"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - CTRLB"] + #[inline(always)] + pub fn ctrlb(&self) -> CTRLB_R { + CTRLB_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - STATUS"] + #[inline(always)] + pub fn status(&self) -> STATUS_R { + STATUS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Counter"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Period"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Compare Channel 0"] + #[inline(always)] + pub fn cc0(&self) -> CC0_R { + CC0_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Compare Channel 1"] + #[inline(always)] + pub fn cc1(&self) -> CC1_R { + CC1_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +#[doc = "Synchronization Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/tc0/count8/wave.rs b/pac/atsamc21e/src/tc0/count8/wave.rs new file mode 100644 index 000000000000..46061b24b75d --- /dev/null +++ b/pac/atsamc21e/src/tc0/count8/wave.rs @@ -0,0 +1,178 @@ +#[doc = "Register `WAVE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WAVE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Waveform Generation Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WAVEGEN_A { + #[doc = "0: Normal frequency"] + NFRQ = 0, + #[doc = "1: Match frequency"] + MFRQ = 1, + #[doc = "2: Normal PWM"] + NPWM = 2, + #[doc = "3: Match PWM"] + MPWM = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WAVEGEN_A) -> Self { + variant as _ + } +} +#[doc = "Field `WAVEGEN` reader - Waveform Generation Mode"] +pub struct WAVEGEN_R(crate::FieldReader); +impl WAVEGEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WAVEGEN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> WAVEGEN_A { + match self.bits { + 0 => WAVEGEN_A::NFRQ, + 1 => WAVEGEN_A::MFRQ, + 2 => WAVEGEN_A::NPWM, + 3 => WAVEGEN_A::MPWM, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NFRQ`"] + #[inline(always)] + pub fn is_nfrq(&self) -> bool { + **self == WAVEGEN_A::NFRQ + } + #[doc = "Checks if the value of the field is `MFRQ`"] + #[inline(always)] + pub fn is_mfrq(&self) -> bool { + **self == WAVEGEN_A::MFRQ + } + #[doc = "Checks if the value of the field is `NPWM`"] + #[inline(always)] + pub fn is_npwm(&self) -> bool { + **self == WAVEGEN_A::NPWM + } + #[doc = "Checks if the value of the field is `MPWM`"] + #[inline(always)] + pub fn is_mpwm(&self) -> bool { + **self == WAVEGEN_A::MPWM + } +} +impl core::ops::Deref for WAVEGEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAVEGEN` writer - Waveform Generation Mode"] +pub struct WAVEGEN_W<'a> { + w: &'a mut W, +} +impl<'a> WAVEGEN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WAVEGEN_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Normal frequency"] + #[inline(always)] + pub fn nfrq(self) -> &'a mut W { + self.variant(WAVEGEN_A::NFRQ) + } + #[doc = "Match frequency"] + #[inline(always)] + pub fn mfrq(self) -> &'a mut W { + self.variant(WAVEGEN_A::MFRQ) + } + #[doc = "Normal PWM"] + #[inline(always)] + pub fn npwm(self) -> &'a mut W { + self.variant(WAVEGEN_A::NPWM) + } + #[doc = "Match PWM"] + #[inline(always)] + pub fn mpwm(self) -> &'a mut W { + self.variant(WAVEGEN_A::MPWM) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u8 & 0x03); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Waveform Generation Mode"] + #[inline(always)] + pub fn wavegen(&self) -> WAVEGEN_R { + WAVEGEN_R::new((self.bits & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Waveform Generation Mode"] + #[inline(always)] + pub fn wavegen(&mut self) -> WAVEGEN_W { + WAVEGEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Waveform Generation Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wave](index.html) module"] +pub struct WAVE_SPEC; +impl crate::RegisterSpec for WAVE_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [wave::R](R) reader structure"] +impl crate::Readable for WAVE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wave::W](W) writer structure"] +impl crate::Writable for WAVE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WAVE to value 0"] +impl crate::Resettable for WAVE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/tcc0.rs b/pac/atsamc21e/src/tcc0.rs new file mode 100644 index 000000000000..6ce813a9e3d5 --- /dev/null +++ b/pac/atsamc21e/src/tcc0.rs @@ -0,0 +1,359 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - Control B Clear"] + pub ctrlbclr: crate::Reg, + #[doc = "0x05 - Control B Set"] + pub ctrlbset: crate::Reg, + _reserved3: [u8; 0x02], + #[doc = "0x08 - Synchronization Busy"] + pub syncbusy: crate::Reg, + #[doc = "0x0c - Recoverable Fault A Configuration"] + pub fctrla: crate::Reg, + #[doc = "0x10 - Recoverable Fault B Configuration"] + pub fctrlb: crate::Reg, + #[doc = "0x14 - Waveform Extension Configuration"] + pub wexctrl: crate::Reg, + #[doc = "0x18 - Driver Control"] + pub drvctrl: crate::Reg, + _reserved8: [u8; 0x02], + #[doc = "0x1e - Debug Control"] + pub dbgctrl: crate::Reg, + _reserved9: [u8; 0x01], + #[doc = "0x20 - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x24 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x28 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x2c - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x30 - Status"] + pub status: crate::Reg, + _reserved_14_count: [u8; 0x04], + #[doc = "0x38 - Pattern"] + pub patt: crate::Reg, + _reserved16: [u8; 0x02], + #[doc = "0x3c - Waveform Control"] + pub wave: crate::Reg, + _reserved_17_per: [u8; 0x04], + _reserved_18_cc: [u8; 0x10], + _reserved19: [u8; 0x10], + #[doc = "0x64 - Pattern Buffer"] + pub pattbuf: crate::Reg, + _reserved20: [u8; 0x06], + _reserved_20_perbuf: [u8; 0x04], + _reserved_21_ccbuf: [u8; 0x10], +} +impl RegisterBlock { + #[doc = "0x34 - Count"] + #[inline(always)] + pub fn count_dith6_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(52usize) + as *const crate::Reg) + } + } + #[doc = "0x34 - Count"] + #[inline(always)] + pub fn count_dith5_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(52usize) + as *const crate::Reg) + } + } + #[doc = "0x34 - Count"] + #[inline(always)] + pub fn count_dith4_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(52usize) + as *const crate::Reg) + } + } + #[doc = "0x34 - Count"] + #[inline(always)] + pub fn count(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(52usize) + as *const crate::Reg) + } + } + #[doc = "0x40 - Period"] + #[inline(always)] + pub fn per_dith6_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(64usize) + as *const crate::Reg) + } + } + #[doc = "0x40 - Period"] + #[inline(always)] + pub fn per_dith5_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(64usize) + as *const crate::Reg) + } + } + #[doc = "0x40 - Period"] + #[inline(always)] + pub fn per_dith4_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(64usize) + as *const crate::Reg) + } + } + #[doc = "0x40 - Period"] + #[inline(always)] + pub fn per(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(64usize) + as *const crate::Reg) + } + } + #[doc = "0x44..0x54 - Compare and Capture"] + #[inline(always)] + pub fn cc_dith6_mode(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(68usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x44..0x54 - Compare and Capture"] + #[inline(always)] + pub fn cc_dith5_mode(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(68usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x44..0x54 - Compare and Capture"] + #[inline(always)] + pub fn cc_dith4_mode(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(68usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x44..0x54 - Compare and Capture"] + #[inline(always)] + pub fn cc(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(68usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x6c - Period Buffer"] + #[inline(always)] + pub fn perbuf_dith6_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(108usize) + as *const crate::Reg) + } + } + #[doc = "0x6c - Period Buffer"] + #[inline(always)] + pub fn perbuf_dith5_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(108usize) + as *const crate::Reg) + } + } + #[doc = "0x6c - Period Buffer"] + #[inline(always)] + pub fn perbuf_dith4_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(108usize) + as *const crate::Reg) + } + } + #[doc = "0x6c - Period Buffer"] + #[inline(always)] + pub fn perbuf(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(108usize) + as *const crate::Reg) + } + } + #[doc = "0x70..0x80 - Compare and Capture Buffer"] + #[inline(always)] + pub fn ccbuf_dith6_mode(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(112usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x70..0x80 - Compare and Capture Buffer"] + #[inline(always)] + pub fn ccbuf_dith5_mode(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(112usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x70..0x80 - Compare and Capture Buffer"] + #[inline(always)] + pub fn ccbuf_dith4_mode(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(112usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x70..0x80 - Compare and Capture Buffer"] + #[inline(always)] + pub fn ccbuf(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(112usize) + as *const [crate::Reg; 4]) + } + } +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "CTRLBCLR register accessor: an alias for `Reg`"] +pub type CTRLBCLR = crate::Reg; +#[doc = "Control B Clear"] +pub mod ctrlbclr; +#[doc = "CTRLBSET register accessor: an alias for `Reg`"] +pub type CTRLBSET = crate::Reg; +#[doc = "Control B Set"] +pub mod ctrlbset; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Busy"] +pub mod syncbusy; +#[doc = "FCTRLA register accessor: an alias for `Reg`"] +pub type FCTRLA = crate::Reg; +#[doc = "Recoverable Fault A Configuration"] +pub mod fctrla; +#[doc = "FCTRLB register accessor: an alias for `Reg`"] +pub type FCTRLB = crate::Reg; +#[doc = "Recoverable Fault B Configuration"] +pub mod fctrlb; +#[doc = "WEXCTRL register accessor: an alias for `Reg`"] +pub type WEXCTRL = crate::Reg; +#[doc = "Waveform Extension Configuration"] +pub mod wexctrl; +#[doc = "DRVCTRL register accessor: an alias for `Reg`"] +pub type DRVCTRL = crate::Reg; +#[doc = "Driver Control"] +pub mod drvctrl; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "COUNT register accessor: an alias for `Reg`"] +pub type COUNT = crate::Reg; +#[doc = "Count"] +pub mod count; +#[doc = "COUNT_DITH4_MODE register accessor: an alias for `Reg`"] +pub type COUNT_DITH4_MODE = crate::Reg; +#[doc = "Count"] +pub mod count_dith4_mode; +#[doc = "COUNT_DITH5_MODE register accessor: an alias for `Reg`"] +pub type COUNT_DITH5_MODE = crate::Reg; +#[doc = "Count"] +pub mod count_dith5_mode; +#[doc = "COUNT_DITH6_MODE register accessor: an alias for `Reg`"] +pub type COUNT_DITH6_MODE = crate::Reg; +#[doc = "Count"] +pub mod count_dith6_mode; +#[doc = "PATT register accessor: an alias for `Reg`"] +pub type PATT = crate::Reg; +#[doc = "Pattern"] +pub mod patt; +#[doc = "WAVE register accessor: an alias for `Reg`"] +pub type WAVE = crate::Reg; +#[doc = "Waveform Control"] +pub mod wave; +#[doc = "PER register accessor: an alias for `Reg`"] +pub type PER = crate::Reg; +#[doc = "Period"] +pub mod per; +#[doc = "PER_DITH4_MODE register accessor: an alias for `Reg`"] +pub type PER_DITH4_MODE = crate::Reg; +#[doc = "Period"] +pub mod per_dith4_mode; +#[doc = "PER_DITH5_MODE register accessor: an alias for `Reg`"] +pub type PER_DITH5_MODE = crate::Reg; +#[doc = "Period"] +pub mod per_dith5_mode; +#[doc = "PER_DITH6_MODE register accessor: an alias for `Reg`"] +pub type PER_DITH6_MODE = crate::Reg; +#[doc = "Period"] +pub mod per_dith6_mode; +#[doc = "CC register accessor: an alias for `Reg`"] +pub type CC = crate::Reg; +#[doc = "Compare and Capture"] +pub mod cc; +#[doc = "CC_DITH4_MODE register accessor: an alias for `Reg`"] +pub type CC_DITH4_MODE = crate::Reg; +#[doc = "Compare and Capture"] +pub mod cc_dith4_mode; +#[doc = "CC_DITH5_MODE register accessor: an alias for `Reg`"] +pub type CC_DITH5_MODE = crate::Reg; +#[doc = "Compare and Capture"] +pub mod cc_dith5_mode; +#[doc = "CC_DITH6_MODE register accessor: an alias for `Reg`"] +pub type CC_DITH6_MODE = crate::Reg; +#[doc = "Compare and Capture"] +pub mod cc_dith6_mode; +#[doc = "PATTBUF register accessor: an alias for `Reg`"] +pub type PATTBUF = crate::Reg; +#[doc = "Pattern Buffer"] +pub mod pattbuf; +#[doc = "PERBUF register accessor: an alias for `Reg`"] +pub type PERBUF = crate::Reg; +#[doc = "Period Buffer"] +pub mod perbuf; +#[doc = "PERBUF_DITH4_MODE register accessor: an alias for `Reg`"] +pub type PERBUF_DITH4_MODE = crate::Reg; +#[doc = "Period Buffer"] +pub mod perbuf_dith4_mode; +#[doc = "PERBUF_DITH5_MODE register accessor: an alias for `Reg`"] +pub type PERBUF_DITH5_MODE = crate::Reg; +#[doc = "Period Buffer"] +pub mod perbuf_dith5_mode; +#[doc = "PERBUF_DITH6_MODE register accessor: an alias for `Reg`"] +pub type PERBUF_DITH6_MODE = crate::Reg; +#[doc = "Period Buffer"] +pub mod perbuf_dith6_mode; +#[doc = "CCBUF register accessor: an alias for `Reg`"] +pub type CCBUF = crate::Reg; +#[doc = "Compare and Capture Buffer"] +pub mod ccbuf; +#[doc = "CCBUF_DITH4_MODE register accessor: an alias for `Reg`"] +pub type CCBUF_DITH4_MODE = crate::Reg; +#[doc = "Compare and Capture Buffer"] +pub mod ccbuf_dith4_mode; +#[doc = "CCBUF_DITH5_MODE register accessor: an alias for `Reg`"] +pub type CCBUF_DITH5_MODE = crate::Reg; +#[doc = "Compare and Capture Buffer"] +pub mod ccbuf_dith5_mode; +#[doc = "CCBUF_DITH6_MODE register accessor: an alias for `Reg`"] +pub type CCBUF_DITH6_MODE = crate::Reg; +#[doc = "Compare and Capture Buffer"] +pub mod ccbuf_dith6_mode; diff --git a/pac/atsamc21e/src/tcc0/cc.rs b/pac/atsamc21e/src/tcc0/cc.rs new file mode 100644 index 000000000000..c4d6df7a9a20 --- /dev/null +++ b/pac/atsamc21e/src/tcc0/cc.rs @@ -0,0 +1,104 @@ +#[doc = "Register `CC[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CC[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CC` reader - Channel Compare/Capture Value"] +pub struct CC_R(crate::FieldReader); +impl CC_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC` writer - Channel Compare/Capture Value"] +pub struct CC_W<'a> { + w: &'a mut W, +} +impl<'a> CC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&self) -> CC_R { + CC_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&mut self) -> CC_W { + CC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc](index.html) module"] +pub struct CC_SPEC; +impl crate::RegisterSpec for CC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cc::R](R) reader structure"] +impl crate::Readable for CC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cc::W](W) writer structure"] +impl crate::Writable for CC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CC[%s] +to value 0"] +impl crate::Resettable for CC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/tcc0/cc_dith4_mode.rs b/pac/atsamc21e/src/tcc0/cc_dith4_mode.rs new file mode 100644 index 000000000000..c45d8b6bac41 --- /dev/null +++ b/pac/atsamc21e/src/tcc0/cc_dith4_mode.rs @@ -0,0 +1,141 @@ +#[doc = "Register `CC_DITH4_MODE[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CC_DITH4_MODE[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHER` reader - Dithering Cycle Number"] +pub struct DITHER_R(crate::FieldReader); +impl DITHER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHER` writer - Dithering Cycle Number"] +pub struct DITHER_W<'a> { + w: &'a mut W, +} +impl<'a> DITHER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Field `CC` reader - Channel Compare/Capture Value"] +pub struct CC_R(crate::FieldReader); +impl CC_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC` writer - Channel Compare/Capture Value"] +pub struct CC_W<'a> { + w: &'a mut W, +} +impl<'a> CC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x000f_ffff << 4)) | ((value as u32 & 0x000f_ffff) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&self) -> DITHER_R { + DITHER_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&self) -> CC_R { + CC_R::new(((self.bits >> 4) & 0x000f_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:3 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&mut self) -> DITHER_W { + DITHER_W { w: self } + } + #[doc = "Bits 4:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&mut self) -> CC_W { + CC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc_dith4_mode](index.html) module"] +pub struct CC_DITH4_MODE_SPEC; +impl crate::RegisterSpec for CC_DITH4_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cc_dith4_mode::R](R) reader structure"] +impl crate::Readable for CC_DITH4_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cc_dith4_mode::W](W) writer structure"] +impl crate::Writable for CC_DITH4_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CC_DITH4_MODE[%s] +to value 0"] +impl crate::Resettable for CC_DITH4_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/tcc0/cc_dith5_mode.rs b/pac/atsamc21e/src/tcc0/cc_dith5_mode.rs new file mode 100644 index 000000000000..0592b923051a --- /dev/null +++ b/pac/atsamc21e/src/tcc0/cc_dith5_mode.rs @@ -0,0 +1,141 @@ +#[doc = "Register `CC_DITH5_MODE[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CC_DITH5_MODE[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHER` reader - Dithering Cycle Number"] +pub struct DITHER_R(crate::FieldReader); +impl DITHER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHER` writer - Dithering Cycle Number"] +pub struct DITHER_W<'a> { + w: &'a mut W, +} +impl<'a> DITHER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f); + self.w + } +} +#[doc = "Field `CC` reader - Channel Compare/Capture Value"] +pub struct CC_R(crate::FieldReader); +impl CC_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC` writer - Channel Compare/Capture Value"] +pub struct CC_W<'a> { + w: &'a mut W, +} +impl<'a> CC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0007_ffff << 5)) | ((value as u32 & 0x0007_ffff) << 5); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&self) -> DITHER_R { + DITHER_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&self) -> CC_R { + CC_R::new(((self.bits >> 5) & 0x0007_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:4 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&mut self) -> DITHER_W { + DITHER_W { w: self } + } + #[doc = "Bits 5:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&mut self) -> CC_W { + CC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc_dith5_mode](index.html) module"] +pub struct CC_DITH5_MODE_SPEC; +impl crate::RegisterSpec for CC_DITH5_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cc_dith5_mode::R](R) reader structure"] +impl crate::Readable for CC_DITH5_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cc_dith5_mode::W](W) writer structure"] +impl crate::Writable for CC_DITH5_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CC_DITH5_MODE[%s] +to value 0"] +impl crate::Resettable for CC_DITH5_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/tcc0/cc_dith6_mode.rs b/pac/atsamc21e/src/tcc0/cc_dith6_mode.rs new file mode 100644 index 000000000000..62a82a872426 --- /dev/null +++ b/pac/atsamc21e/src/tcc0/cc_dith6_mode.rs @@ -0,0 +1,141 @@ +#[doc = "Register `CC_DITH6_MODE[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CC_DITH6_MODE[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHER` reader - Dithering Cycle Number"] +pub struct DITHER_R(crate::FieldReader); +impl DITHER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHER` writer - Dithering Cycle Number"] +pub struct DITHER_W<'a> { + w: &'a mut W, +} +impl<'a> DITHER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +#[doc = "Field `CC` reader - Channel Compare/Capture Value"] +pub struct CC_R(crate::FieldReader); +impl CC_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC` writer - Channel Compare/Capture Value"] +pub struct CC_W<'a> { + w: &'a mut W, +} +impl<'a> CC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0003_ffff << 6)) | ((value as u32 & 0x0003_ffff) << 6); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&self) -> DITHER_R { + DITHER_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&self) -> CC_R { + CC_R::new(((self.bits >> 6) & 0x0003_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:5 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&mut self) -> DITHER_W { + DITHER_W { w: self } + } + #[doc = "Bits 6:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&mut self) -> CC_W { + CC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc_dith6_mode](index.html) module"] +pub struct CC_DITH6_MODE_SPEC; +impl crate::RegisterSpec for CC_DITH6_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cc_dith6_mode::R](R) reader structure"] +impl crate::Readable for CC_DITH6_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cc_dith6_mode::W](W) writer structure"] +impl crate::Writable for CC_DITH6_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CC_DITH6_MODE[%s] +to value 0"] +impl crate::Resettable for CC_DITH6_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/tcc0/ccbuf.rs b/pac/atsamc21e/src/tcc0/ccbuf.rs new file mode 100644 index 000000000000..a4db1135f095 --- /dev/null +++ b/pac/atsamc21e/src/tcc0/ccbuf.rs @@ -0,0 +1,104 @@ +#[doc = "Register `CCBUF[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CCBUF[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CCBUF` reader - Channel Compare/Capture Buffer Value"] +pub struct CCBUF_R(crate::FieldReader); +impl CCBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CCBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUF` writer - Channel Compare/Capture Buffer Value"] +pub struct CCBUF_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccbuf(&self) -> CCBUF_R { + CCBUF_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccbuf(&mut self) -> CCBUF_W { + CCBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccbuf](index.html) module"] +pub struct CCBUF_SPEC; +impl crate::RegisterSpec for CCBUF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ccbuf::R](R) reader structure"] +impl crate::Readable for CCBUF_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ccbuf::W](W) writer structure"] +impl crate::Writable for CCBUF_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CCBUF[%s] +to value 0"] +impl crate::Resettable for CCBUF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/tcc0/ccbuf_dith4_mode.rs b/pac/atsamc21e/src/tcc0/ccbuf_dith4_mode.rs new file mode 100644 index 000000000000..dfa16e936175 --- /dev/null +++ b/pac/atsamc21e/src/tcc0/ccbuf_dith4_mode.rs @@ -0,0 +1,141 @@ +#[doc = "Register `CCBUF_DITH4_MODE[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CCBUF_DITH4_MODE[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CCBUF` reader - Channel Compare/Capture Buffer Value"] +pub struct CCBUF_R(crate::FieldReader); +impl CCBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CCBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUF` writer - Channel Compare/Capture Buffer Value"] +pub struct CCBUF_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Field `DITHERBUF` reader - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_R(crate::FieldReader); +impl DITHERBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + DITHERBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHERBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHERBUF` writer - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_W<'a> { + w: &'a mut W, +} +impl<'a> DITHERBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x000f_ffff << 4)) | ((value as u32 & 0x000f_ffff) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccbuf(&self) -> CCBUF_R { + CCBUF_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:23 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&self) -> DITHERBUF_R { + DITHERBUF_R::new(((self.bits >> 4) & 0x000f_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:3 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccbuf(&mut self) -> CCBUF_W { + CCBUF_W { w: self } + } + #[doc = "Bits 4:23 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&mut self) -> DITHERBUF_W { + DITHERBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccbuf_dith4_mode](index.html) module"] +pub struct CCBUF_DITH4_MODE_SPEC; +impl crate::RegisterSpec for CCBUF_DITH4_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ccbuf_dith4_mode::R](R) reader structure"] +impl crate::Readable for CCBUF_DITH4_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ccbuf_dith4_mode::W](W) writer structure"] +impl crate::Writable for CCBUF_DITH4_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CCBUF_DITH4_MODE[%s] +to value 0"] +impl crate::Resettable for CCBUF_DITH4_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/tcc0/ccbuf_dith5_mode.rs b/pac/atsamc21e/src/tcc0/ccbuf_dith5_mode.rs new file mode 100644 index 000000000000..0c78ba3303c0 --- /dev/null +++ b/pac/atsamc21e/src/tcc0/ccbuf_dith5_mode.rs @@ -0,0 +1,141 @@ +#[doc = "Register `CCBUF_DITH5_MODE[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CCBUF_DITH5_MODE[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHERBUF` reader - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_R(crate::FieldReader); +impl DITHERBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHERBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHERBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHERBUF` writer - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_W<'a> { + w: &'a mut W, +} +impl<'a> DITHERBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f); + self.w + } +} +#[doc = "Field `CCBUF` reader - Channel Compare/Capture Buffer Value"] +pub struct CCBUF_R(crate::FieldReader); +impl CCBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CCBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUF` writer - Channel Compare/Capture Buffer Value"] +pub struct CCBUF_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0007_ffff << 5)) | ((value as u32 & 0x0007_ffff) << 5); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&self) -> DITHERBUF_R { + DITHERBUF_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:23 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccbuf(&self) -> CCBUF_R { + CCBUF_R::new(((self.bits >> 5) & 0x0007_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:4 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&mut self) -> DITHERBUF_W { + DITHERBUF_W { w: self } + } + #[doc = "Bits 5:23 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccbuf(&mut self) -> CCBUF_W { + CCBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccbuf_dith5_mode](index.html) module"] +pub struct CCBUF_DITH5_MODE_SPEC; +impl crate::RegisterSpec for CCBUF_DITH5_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ccbuf_dith5_mode::R](R) reader structure"] +impl crate::Readable for CCBUF_DITH5_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ccbuf_dith5_mode::W](W) writer structure"] +impl crate::Writable for CCBUF_DITH5_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CCBUF_DITH5_MODE[%s] +to value 0"] +impl crate::Resettable for CCBUF_DITH5_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/tcc0/ccbuf_dith6_mode.rs b/pac/atsamc21e/src/tcc0/ccbuf_dith6_mode.rs new file mode 100644 index 000000000000..8d19b8a9e595 --- /dev/null +++ b/pac/atsamc21e/src/tcc0/ccbuf_dith6_mode.rs @@ -0,0 +1,141 @@ +#[doc = "Register `CCBUF_DITH6_MODE[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CCBUF_DITH6_MODE[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHERBUF` reader - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_R(crate::FieldReader); +impl DITHERBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHERBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHERBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHERBUF` writer - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_W<'a> { + w: &'a mut W, +} +impl<'a> DITHERBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +#[doc = "Field `CCBUF` reader - Channel Compare/Capture Buffer Value"] +pub struct CCBUF_R(crate::FieldReader); +impl CCBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CCBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUF` writer - Channel Compare/Capture Buffer Value"] +pub struct CCBUF_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0003_ffff << 6)) | ((value as u32 & 0x0003_ffff) << 6); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&self) -> DITHERBUF_R { + DITHERBUF_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:23 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccbuf(&self) -> CCBUF_R { + CCBUF_R::new(((self.bits >> 6) & 0x0003_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:5 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&mut self) -> DITHERBUF_W { + DITHERBUF_W { w: self } + } + #[doc = "Bits 6:23 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccbuf(&mut self) -> CCBUF_W { + CCBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccbuf_dith6_mode](index.html) module"] +pub struct CCBUF_DITH6_MODE_SPEC; +impl crate::RegisterSpec for CCBUF_DITH6_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ccbuf_dith6_mode::R](R) reader structure"] +impl crate::Readable for CCBUF_DITH6_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ccbuf_dith6_mode::W](W) writer structure"] +impl crate::Writable for CCBUF_DITH6_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CCBUF_DITH6_MODE[%s] +to value 0"] +impl crate::Resettable for CCBUF_DITH6_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/tcc0/count.rs b/pac/atsamc21e/src/tcc0/count.rs new file mode 100644 index 000000000000..7628f2c0d5e1 --- /dev/null +++ b/pac/atsamc21e/src/tcc0/count.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Count\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count](index.html) module"] +pub struct COUNT_SPEC; +impl crate::RegisterSpec for COUNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [count::R](R) reader structure"] +impl crate::Readable for COUNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count::W](W) writer structure"] +impl crate::Writable for COUNT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT to value 0"] +impl crate::Resettable for COUNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/tcc0/count_dith4_mode.rs b/pac/atsamc21e/src/tcc0/count_dith4_mode.rs new file mode 100644 index 000000000000..fc058ae5efd5 --- /dev/null +++ b/pac/atsamc21e/src/tcc0/count_dith4_mode.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT_DITH4_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT_DITH4_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x000f_ffff << 4)) | ((value as u32 & 0x000f_ffff) << 4); + self.w + } +} +impl R { + #[doc = "Bits 4:23 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 4) & 0x000f_ffff) as u32) + } +} +impl W { + #[doc = "Bits 4:23 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Count\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count_dith4_mode](index.html) module"] +pub struct COUNT_DITH4_MODE_SPEC; +impl crate::RegisterSpec for COUNT_DITH4_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [count_dith4_mode::R](R) reader structure"] +impl crate::Readable for COUNT_DITH4_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count_dith4_mode::W](W) writer structure"] +impl crate::Writable for COUNT_DITH4_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT_DITH4_MODE to value 0"] +impl crate::Resettable for COUNT_DITH4_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/tcc0/count_dith5_mode.rs b/pac/atsamc21e/src/tcc0/count_dith5_mode.rs new file mode 100644 index 000000000000..e66e20310726 --- /dev/null +++ b/pac/atsamc21e/src/tcc0/count_dith5_mode.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT_DITH5_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT_DITH5_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0007_ffff << 5)) | ((value as u32 & 0x0007_ffff) << 5); + self.w + } +} +impl R { + #[doc = "Bits 5:23 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 5) & 0x0007_ffff) as u32) + } +} +impl W { + #[doc = "Bits 5:23 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Count\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count_dith5_mode](index.html) module"] +pub struct COUNT_DITH5_MODE_SPEC; +impl crate::RegisterSpec for COUNT_DITH5_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [count_dith5_mode::R](R) reader structure"] +impl crate::Readable for COUNT_DITH5_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count_dith5_mode::W](W) writer structure"] +impl crate::Writable for COUNT_DITH5_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT_DITH5_MODE to value 0"] +impl crate::Resettable for COUNT_DITH5_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/tcc0/count_dith6_mode.rs b/pac/atsamc21e/src/tcc0/count_dith6_mode.rs new file mode 100644 index 000000000000..5410fc6c9459 --- /dev/null +++ b/pac/atsamc21e/src/tcc0/count_dith6_mode.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT_DITH6_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT_DITH6_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0003_ffff << 6)) | ((value as u32 & 0x0003_ffff) << 6); + self.w + } +} +impl R { + #[doc = "Bits 6:23 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 6) & 0x0003_ffff) as u32) + } +} +impl W { + #[doc = "Bits 6:23 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Count\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count_dith6_mode](index.html) module"] +pub struct COUNT_DITH6_MODE_SPEC; +impl crate::RegisterSpec for COUNT_DITH6_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [count_dith6_mode::R](R) reader structure"] +impl crate::Readable for COUNT_DITH6_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count_dith6_mode::W](W) writer structure"] +impl crate::Writable for COUNT_DITH6_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT_DITH6_MODE to value 0"] +impl crate::Resettable for COUNT_DITH6_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/tcc0/ctrla.rs b/pac/atsamc21e/src/tcc0/ctrla.rs new file mode 100644 index 000000000000..b717d1ac6ae0 --- /dev/null +++ b/pac/atsamc21e/src/tcc0/ctrla.rs @@ -0,0 +1,911 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Enhanced Resolution\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum RESOLUTION_A { + #[doc = "0: Dithering is disabled"] + NONE = 0, + #[doc = "1: Dithering is done every 16 PWM frames"] + DITH4 = 1, + #[doc = "2: Dithering is done every 32 PWM frames"] + DITH5 = 2, + #[doc = "3: Dithering is done every 64 PWM frames"] + DITH6 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RESOLUTION_A) -> Self { + variant as _ + } +} +#[doc = "Field `RESOLUTION` reader - Enhanced Resolution"] +pub struct RESOLUTION_R(crate::FieldReader); +impl RESOLUTION_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RESOLUTION_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RESOLUTION_A { + match self.bits { + 0 => RESOLUTION_A::NONE, + 1 => RESOLUTION_A::DITH4, + 2 => RESOLUTION_A::DITH5, + 3 => RESOLUTION_A::DITH6, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == RESOLUTION_A::NONE + } + #[doc = "Checks if the value of the field is `DITH4`"] + #[inline(always)] + pub fn is_dith4(&self) -> bool { + **self == RESOLUTION_A::DITH4 + } + #[doc = "Checks if the value of the field is `DITH5`"] + #[inline(always)] + pub fn is_dith5(&self) -> bool { + **self == RESOLUTION_A::DITH5 + } + #[doc = "Checks if the value of the field is `DITH6`"] + #[inline(always)] + pub fn is_dith6(&self) -> bool { + **self == RESOLUTION_A::DITH6 + } +} +impl core::ops::Deref for RESOLUTION_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESOLUTION` writer - Enhanced Resolution"] +pub struct RESOLUTION_W<'a> { + w: &'a mut W, +} +impl<'a> RESOLUTION_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RESOLUTION_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Dithering is disabled"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(RESOLUTION_A::NONE) + } + #[doc = "Dithering is done every 16 PWM frames"] + #[inline(always)] + pub fn dith4(self) -> &'a mut W { + self.variant(RESOLUTION_A::DITH4) + } + #[doc = "Dithering is done every 32 PWM frames"] + #[inline(always)] + pub fn dith5(self) -> &'a mut W { + self.variant(RESOLUTION_A::DITH5) + } + #[doc = "Dithering is done every 64 PWM frames"] + #[inline(always)] + pub fn dith6(self) -> &'a mut W { + self.variant(RESOLUTION_A::DITH6) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 5)) | ((value as u32 & 0x03) << 5); + self.w + } +} +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: No division"] + DIV1 = 0, + #[doc = "1: Divide by 2"] + DIV2 = 1, + #[doc = "2: Divide by 4"] + DIV4 = 2, + #[doc = "3: Divide by 8"] + DIV8 = 3, + #[doc = "4: Divide by 16"] + DIV16 = 4, + #[doc = "5: Divide by 64"] + DIV64 = 5, + #[doc = "6: Divide by 256"] + DIV256 = 6, + #[doc = "7: Divide by 1024"] + DIV1024 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PRESCALER_A { + match self.bits { + 0 => PRESCALER_A::DIV1, + 1 => PRESCALER_A::DIV2, + 2 => PRESCALER_A::DIV4, + 3 => PRESCALER_A::DIV8, + 4 => PRESCALER_A::DIV16, + 5 => PRESCALER_A::DIV64, + 6 => PRESCALER_A::DIV256, + 7 => PRESCALER_A::DIV1024, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == PRESCALER_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PRESCALER_A::DIV1024 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "No division"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1) + } + #[doc = "Divide by 2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "Divide by 4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "Divide by 8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "Divide by 16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "Divide by 64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "Divide by 256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = "Divide by 1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Prescaler and Counter Synchronization Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCSYNC_A { + #[doc = "0: Reload or reset counter on next GCLK"] + GCLK = 0, + #[doc = "1: Reload or reset counter on next prescaler clock"] + PRESC = 1, + #[doc = "2: Reload or reset counter on next GCLK and reset prescaler counter"] + RESYNC = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCSYNC_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCSYNC` reader - Prescaler and Counter Synchronization Selection"] +pub struct PRESCSYNC_R(crate::FieldReader); +impl PRESCSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCSYNC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCSYNC_A::GCLK), + 1 => Some(PRESCSYNC_A::PRESC), + 2 => Some(PRESCSYNC_A::RESYNC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `GCLK`"] + #[inline(always)] + pub fn is_gclk(&self) -> bool { + **self == PRESCSYNC_A::GCLK + } + #[doc = "Checks if the value of the field is `PRESC`"] + #[inline(always)] + pub fn is_presc(&self) -> bool { + **self == PRESCSYNC_A::PRESC + } + #[doc = "Checks if the value of the field is `RESYNC`"] + #[inline(always)] + pub fn is_resync(&self) -> bool { + **self == PRESCSYNC_A::RESYNC + } +} +impl core::ops::Deref for PRESCSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCSYNC` writer - Prescaler and Counter Synchronization Selection"] +pub struct PRESCSYNC_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCSYNC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCSYNC_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Reload or reset counter on next GCLK"] + #[inline(always)] + pub fn gclk(self) -> &'a mut W { + self.variant(PRESCSYNC_A::GCLK) + } + #[doc = "Reload or reset counter on next prescaler clock"] + #[inline(always)] + pub fn presc(self) -> &'a mut W { + self.variant(PRESCSYNC_A::PRESC) + } + #[doc = "Reload or reset counter on next GCLK and reset prescaler counter"] + #[inline(always)] + pub fn resync(self) -> &'a mut W { + self.variant(PRESCSYNC_A::RESYNC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 12)) | ((value as u32 & 0x03) << 12); + self.w + } +} +#[doc = "Field `ALOCK` reader - Auto Lock"] +pub struct ALOCK_R(crate::FieldReader); +impl ALOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALOCK` writer - Auto Lock"] +pub struct ALOCK_W<'a> { + w: &'a mut W, +} +impl<'a> ALOCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `MSYNC` reader - Master Synchronization (only for TCC Slave Instance)"] +pub struct MSYNC_R(crate::FieldReader); +impl MSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MSYNC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MSYNC` writer - Master Synchronization (only for TCC Slave Instance)"] +pub struct MSYNC_W<'a> { + w: &'a mut W, +} +impl<'a> MSYNC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `DMAOS` reader - DMA One-shot Trigger Mode"] +pub struct DMAOS_R(crate::FieldReader); +impl DMAOS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DMAOS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DMAOS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DMAOS` writer - DMA One-shot Trigger Mode"] +pub struct DMAOS_W<'a> { + w: &'a mut W, +} +impl<'a> DMAOS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `CPTEN0` reader - Capture Channel 0 Enable"] +pub struct CPTEN0_R(crate::FieldReader); +impl CPTEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPTEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CPTEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPTEN0` writer - Capture Channel 0 Enable"] +pub struct CPTEN0_W<'a> { + w: &'a mut W, +} +impl<'a> CPTEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `CPTEN1` reader - Capture Channel 1 Enable"] +pub struct CPTEN1_R(crate::FieldReader); +impl CPTEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPTEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CPTEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPTEN1` writer - Capture Channel 1 Enable"] +pub struct CPTEN1_W<'a> { + w: &'a mut W, +} +impl<'a> CPTEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `CPTEN2` reader - Capture Channel 2 Enable"] +pub struct CPTEN2_R(crate::FieldReader); +impl CPTEN2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPTEN2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CPTEN2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPTEN2` writer - Capture Channel 2 Enable"] +pub struct CPTEN2_W<'a> { + w: &'a mut W, +} +impl<'a> CPTEN2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `CPTEN3` reader - Capture Channel 3 Enable"] +pub struct CPTEN3_R(crate::FieldReader); +impl CPTEN3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPTEN3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CPTEN3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPTEN3` writer - Capture Channel 3 Enable"] +pub struct CPTEN3_W<'a> { + w: &'a mut W, +} +impl<'a> CPTEN3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 5:6 - Enhanced Resolution"] + #[inline(always)] + pub fn resolution(&self) -> RESOLUTION_R { + RESOLUTION_R::new(((self.bits >> 5) & 0x03) as u8) + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 11 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bits 12:13 - Prescaler and Counter Synchronization Selection"] + #[inline(always)] + pub fn prescsync(&self) -> PRESCSYNC_R { + PRESCSYNC_R::new(((self.bits >> 12) & 0x03) as u8) + } + #[doc = "Bit 14 - Auto Lock"] + #[inline(always)] + pub fn alock(&self) -> ALOCK_R { + ALOCK_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Master Synchronization (only for TCC Slave Instance)"] + #[inline(always)] + pub fn msync(&self) -> MSYNC_R { + MSYNC_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 23 - DMA One-shot Trigger Mode"] + #[inline(always)] + pub fn dmaos(&self) -> DMAOS_R { + DMAOS_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn cpten0(&self) -> CPTEN0_R { + CPTEN0_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn cpten1(&self) -> CPTEN1_R { + CPTEN1_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Capture Channel 2 Enable"] + #[inline(always)] + pub fn cpten2(&self) -> CPTEN2_R { + CPTEN2_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Capture Channel 3 Enable"] + #[inline(always)] + pub fn cpten3(&self) -> CPTEN3_R { + CPTEN3_R::new(((self.bits >> 27) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 5:6 - Enhanced Resolution"] + #[inline(always)] + pub fn resolution(&mut self) -> RESOLUTION_W { + RESOLUTION_W { w: self } + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Bit 11 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bits 12:13 - Prescaler and Counter Synchronization Selection"] + #[inline(always)] + pub fn prescsync(&mut self) -> PRESCSYNC_W { + PRESCSYNC_W { w: self } + } + #[doc = "Bit 14 - Auto Lock"] + #[inline(always)] + pub fn alock(&mut self) -> ALOCK_W { + ALOCK_W { w: self } + } + #[doc = "Bit 15 - Master Synchronization (only for TCC Slave Instance)"] + #[inline(always)] + pub fn msync(&mut self) -> MSYNC_W { + MSYNC_W { w: self } + } + #[doc = "Bit 23 - DMA One-shot Trigger Mode"] + #[inline(always)] + pub fn dmaos(&mut self) -> DMAOS_W { + DMAOS_W { w: self } + } + #[doc = "Bit 24 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn cpten0(&mut self) -> CPTEN0_W { + CPTEN0_W { w: self } + } + #[doc = "Bit 25 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn cpten1(&mut self) -> CPTEN1_W { + CPTEN1_W { w: self } + } + #[doc = "Bit 26 - Capture Channel 2 Enable"] + #[inline(always)] + pub fn cpten2(&mut self) -> CPTEN2_W { + CPTEN2_W { w: self } + } + #[doc = "Bit 27 - Capture Channel 3 Enable"] + #[inline(always)] + pub fn cpten3(&mut self) -> CPTEN3_W { + CPTEN3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/tcc0/ctrlbclr.rs b/pac/atsamc21e/src/tcc0/ctrlbclr.rs new file mode 100644 index 000000000000..f96ce81ffde3 --- /dev/null +++ b/pac/atsamc21e/src/tcc0/ctrlbclr.rs @@ -0,0 +1,457 @@ +#[doc = "Register `CTRLBCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Counter Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `LUPD` reader - Lock Update"] +pub struct LUPD_R(crate::FieldReader); +impl LUPD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LUPD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LUPD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LUPD` writer - Lock Update"] +pub struct LUPD_W<'a> { + w: &'a mut W, +} +impl<'a> LUPD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ONESHOT` reader - One-Shot"] +pub struct ONESHOT_R(crate::FieldReader); +impl ONESHOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONESHOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONESHOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONESHOT` writer - One-Shot"] +pub struct ONESHOT_W<'a> { + w: &'a mut W, +} +impl<'a> ONESHOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Ramp Index Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum IDXCMD_A { + #[doc = "0: Command disabled: Index toggles between cycles A and B"] + DISABLE = 0, + #[doc = "1: Set index: cycle B will be forced in the next cycle"] + SET = 1, + #[doc = "2: Clear index: cycle A will be forced in the next cycle"] + CLEAR = 2, + #[doc = "3: Hold index: the next cycle will be the same as the current cycle"] + HOLD = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: IDXCMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `IDXCMD` reader - Ramp Index Command"] +pub struct IDXCMD_R(crate::FieldReader); +impl IDXCMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + IDXCMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> IDXCMD_A { + match self.bits { + 0 => IDXCMD_A::DISABLE, + 1 => IDXCMD_A::SET, + 2 => IDXCMD_A::CLEAR, + 3 => IDXCMD_A::HOLD, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == IDXCMD_A::DISABLE + } + #[doc = "Checks if the value of the field is `SET`"] + #[inline(always)] + pub fn is_set(&self) -> bool { + **self == IDXCMD_A::SET + } + #[doc = "Checks if the value of the field is `CLEAR`"] + #[inline(always)] + pub fn is_clear(&self) -> bool { + **self == IDXCMD_A::CLEAR + } + #[doc = "Checks if the value of the field is `HOLD`"] + #[inline(always)] + pub fn is_hold(&self) -> bool { + **self == IDXCMD_A::HOLD + } +} +impl core::ops::Deref for IDXCMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IDXCMD` writer - Ramp Index Command"] +pub struct IDXCMD_W<'a> { + w: &'a mut W, +} +impl<'a> IDXCMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: IDXCMD_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Command disabled: Index toggles between cycles A and B"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(IDXCMD_A::DISABLE) + } + #[doc = "Set index: cycle B will be forced in the next cycle"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(IDXCMD_A::SET) + } + #[doc = "Clear index: cycle A will be forced in the next cycle"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(IDXCMD_A::CLEAR) + } + #[doc = "Hold index: the next cycle will be the same as the current cycle"] + #[inline(always)] + pub fn hold(self) -> &'a mut W { + self.variant(IDXCMD_A::HOLD) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 3)) | ((value as u8 & 0x03) << 3); + self.w + } +} +#[doc = "TCC Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Clear start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force stop"] + STOP = 2, + #[doc = "3: Force update or double buffered registers"] + UPDATE = 3, + #[doc = "4: Force COUNT read synchronization"] + READSYNC = 4, + #[doc = "5: One-shot DMA trigger"] + DMAOS = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - TCC Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NONE), + 1 => Some(CMD_A::RETRIGGER), + 2 => Some(CMD_A::STOP), + 3 => Some(CMD_A::UPDATE), + 4 => Some(CMD_A::READSYNC), + 5 => Some(CMD_A::DMAOS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == CMD_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == CMD_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == CMD_A::STOP + } + #[doc = "Checks if the value of the field is `UPDATE`"] + #[inline(always)] + pub fn is_update(&self) -> bool { + **self == CMD_A::UPDATE + } + #[doc = "Checks if the value of the field is `READSYNC`"] + #[inline(always)] + pub fn is_readsync(&self) -> bool { + **self == CMD_A::READSYNC + } + #[doc = "Checks if the value of the field is `DMAOS`"] + #[inline(always)] + pub fn is_dmaos(&self) -> bool { + **self == CMD_A::DMAOS + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - TCC Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMD_A::NONE) + } + #[doc = "Clear start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMD_A::RETRIGGER) + } + #[doc = "Force stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMD_A::STOP) + } + #[doc = "Force update or double buffered registers"] + #[inline(always)] + pub fn update(self) -> &'a mut W { + self.variant(CMD_A::UPDATE) + } + #[doc = "Force COUNT read synchronization"] + #[inline(always)] + pub fn readsync(self) -> &'a mut W { + self.variant(CMD_A::READSYNC) + } + #[doc = "One-shot DMA trigger"] + #[inline(always)] + pub fn dmaos(self) -> &'a mut W { + self.variant(CMD_A::DMAOS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 5)) | ((value as u8 & 0x07) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&self) -> LUPD_R { + LUPD_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - One-Shot"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 3:4 - Ramp Index Command"] + #[inline(always)] + pub fn idxcmd(&self) -> IDXCMD_R { + IDXCMD_R::new(((self.bits >> 3) & 0x03) as u8) + } + #[doc = "Bits 5:7 - TCC Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 5) & 0x07) as u8) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&mut self) -> LUPD_W { + LUPD_W { w: self } + } + #[doc = "Bit 2 - One-Shot"] + #[inline(always)] + pub fn oneshot(&mut self) -> ONESHOT_W { + ONESHOT_W { w: self } + } + #[doc = "Bits 3:4 - Ramp Index Command"] + #[inline(always)] + pub fn idxcmd(&mut self) -> IDXCMD_W { + IDXCMD_W { w: self } + } + #[doc = "Bits 5:7 - TCC Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbclr](index.html) module"] +pub struct CTRLBCLR_SPEC; +impl crate::RegisterSpec for CTRLBCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbclr::R](R) reader structure"] +impl crate::Readable for CTRLBCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbclr::W](W) writer structure"] +impl crate::Writable for CTRLBCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLBCLR to value 0"] +impl crate::Resettable for CTRLBCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/tcc0/ctrlbset.rs b/pac/atsamc21e/src/tcc0/ctrlbset.rs new file mode 100644 index 000000000000..7002dd71efe7 --- /dev/null +++ b/pac/atsamc21e/src/tcc0/ctrlbset.rs @@ -0,0 +1,457 @@ +#[doc = "Register `CTRLBSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Counter Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `LUPD` reader - Lock Update"] +pub struct LUPD_R(crate::FieldReader); +impl LUPD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LUPD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LUPD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LUPD` writer - Lock Update"] +pub struct LUPD_W<'a> { + w: &'a mut W, +} +impl<'a> LUPD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ONESHOT` reader - One-Shot"] +pub struct ONESHOT_R(crate::FieldReader); +impl ONESHOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONESHOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONESHOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONESHOT` writer - One-Shot"] +pub struct ONESHOT_W<'a> { + w: &'a mut W, +} +impl<'a> ONESHOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Ramp Index Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum IDXCMD_A { + #[doc = "0: Command disabled: Index toggles between cycles A and B"] + DISABLE = 0, + #[doc = "1: Set index: cycle B will be forced in the next cycle"] + SET = 1, + #[doc = "2: Clear index: cycle A will be forced in the next cycle"] + CLEAR = 2, + #[doc = "3: Hold index: the next cycle will be the same as the current cycle"] + HOLD = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: IDXCMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `IDXCMD` reader - Ramp Index Command"] +pub struct IDXCMD_R(crate::FieldReader); +impl IDXCMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + IDXCMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> IDXCMD_A { + match self.bits { + 0 => IDXCMD_A::DISABLE, + 1 => IDXCMD_A::SET, + 2 => IDXCMD_A::CLEAR, + 3 => IDXCMD_A::HOLD, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == IDXCMD_A::DISABLE + } + #[doc = "Checks if the value of the field is `SET`"] + #[inline(always)] + pub fn is_set(&self) -> bool { + **self == IDXCMD_A::SET + } + #[doc = "Checks if the value of the field is `CLEAR`"] + #[inline(always)] + pub fn is_clear(&self) -> bool { + **self == IDXCMD_A::CLEAR + } + #[doc = "Checks if the value of the field is `HOLD`"] + #[inline(always)] + pub fn is_hold(&self) -> bool { + **self == IDXCMD_A::HOLD + } +} +impl core::ops::Deref for IDXCMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IDXCMD` writer - Ramp Index Command"] +pub struct IDXCMD_W<'a> { + w: &'a mut W, +} +impl<'a> IDXCMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: IDXCMD_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Command disabled: Index toggles between cycles A and B"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(IDXCMD_A::DISABLE) + } + #[doc = "Set index: cycle B will be forced in the next cycle"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(IDXCMD_A::SET) + } + #[doc = "Clear index: cycle A will be forced in the next cycle"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(IDXCMD_A::CLEAR) + } + #[doc = "Hold index: the next cycle will be the same as the current cycle"] + #[inline(always)] + pub fn hold(self) -> &'a mut W { + self.variant(IDXCMD_A::HOLD) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 3)) | ((value as u8 & 0x03) << 3); + self.w + } +} +#[doc = "TCC Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Clear start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force stop"] + STOP = 2, + #[doc = "3: Force update or double buffered registers"] + UPDATE = 3, + #[doc = "4: Force COUNT read synchronization"] + READSYNC = 4, + #[doc = "5: One-shot DMA trigger"] + DMAOS = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - TCC Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NONE), + 1 => Some(CMD_A::RETRIGGER), + 2 => Some(CMD_A::STOP), + 3 => Some(CMD_A::UPDATE), + 4 => Some(CMD_A::READSYNC), + 5 => Some(CMD_A::DMAOS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == CMD_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == CMD_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == CMD_A::STOP + } + #[doc = "Checks if the value of the field is `UPDATE`"] + #[inline(always)] + pub fn is_update(&self) -> bool { + **self == CMD_A::UPDATE + } + #[doc = "Checks if the value of the field is `READSYNC`"] + #[inline(always)] + pub fn is_readsync(&self) -> bool { + **self == CMD_A::READSYNC + } + #[doc = "Checks if the value of the field is `DMAOS`"] + #[inline(always)] + pub fn is_dmaos(&self) -> bool { + **self == CMD_A::DMAOS + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - TCC Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMD_A::NONE) + } + #[doc = "Clear start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMD_A::RETRIGGER) + } + #[doc = "Force stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMD_A::STOP) + } + #[doc = "Force update or double buffered registers"] + #[inline(always)] + pub fn update(self) -> &'a mut W { + self.variant(CMD_A::UPDATE) + } + #[doc = "Force COUNT read synchronization"] + #[inline(always)] + pub fn readsync(self) -> &'a mut W { + self.variant(CMD_A::READSYNC) + } + #[doc = "One-shot DMA trigger"] + #[inline(always)] + pub fn dmaos(self) -> &'a mut W { + self.variant(CMD_A::DMAOS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 5)) | ((value as u8 & 0x07) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&self) -> LUPD_R { + LUPD_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - One-Shot"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 3:4 - Ramp Index Command"] + #[inline(always)] + pub fn idxcmd(&self) -> IDXCMD_R { + IDXCMD_R::new(((self.bits >> 3) & 0x03) as u8) + } + #[doc = "Bits 5:7 - TCC Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 5) & 0x07) as u8) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&mut self) -> LUPD_W { + LUPD_W { w: self } + } + #[doc = "Bit 2 - One-Shot"] + #[inline(always)] + pub fn oneshot(&mut self) -> ONESHOT_W { + ONESHOT_W { w: self } + } + #[doc = "Bits 3:4 - Ramp Index Command"] + #[inline(always)] + pub fn idxcmd(&mut self) -> IDXCMD_W { + IDXCMD_W { w: self } + } + #[doc = "Bits 5:7 - TCC Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbset](index.html) module"] +pub struct CTRLBSET_SPEC; +impl crate::RegisterSpec for CTRLBSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbset::R](R) reader structure"] +impl crate::Readable for CTRLBSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbset::W](W) writer structure"] +impl crate::Writable for CTRLBSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLBSET to value 0"] +impl crate::Resettable for CTRLBSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/tcc0/dbgctrl.rs b/pac/atsamc21e/src/tcc0/dbgctrl.rs new file mode 100644 index 000000000000..313ebe3f5c18 --- /dev/null +++ b/pac/atsamc21e/src/tcc0/dbgctrl.rs @@ -0,0 +1,160 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Debug Running Mode"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Debug Running Mode"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `FDDBD` reader - Fault Detection on Debug Break Detection"] +pub struct FDDBD_R(crate::FieldReader); +impl FDDBD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FDDBD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FDDBD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FDDBD` writer - Fault Detection on Debug Break Detection"] +pub struct FDDBD_W<'a> { + w: &'a mut W, +} +impl<'a> FDDBD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Running Mode"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 2 - Fault Detection on Debug Break Detection"] + #[inline(always)] + pub fn fddbd(&self) -> FDDBD_R { + FDDBD_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Running Mode"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Bit 2 - Fault Detection on Debug Break Detection"] + #[inline(always)] + pub fn fddbd(&mut self) -> FDDBD_W { + FDDBD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/tcc0/drvctrl.rs b/pac/atsamc21e/src/tcc0/drvctrl.rs new file mode 100644 index 000000000000..316041e1e3be --- /dev/null +++ b/pac/atsamc21e/src/tcc0/drvctrl.rs @@ -0,0 +1,1268 @@ +#[doc = "Register `DRVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DRVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `NRE0` reader - Non-Recoverable State 0 Output Enable"] +pub struct NRE0_R(crate::FieldReader); +impl NRE0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRE0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRE0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRE0` writer - Non-Recoverable State 0 Output Enable"] +pub struct NRE0_W<'a> { + w: &'a mut W, +} +impl<'a> NRE0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `NRE1` reader - Non-Recoverable State 1 Output Enable"] +pub struct NRE1_R(crate::FieldReader); +impl NRE1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRE1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRE1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRE1` writer - Non-Recoverable State 1 Output Enable"] +pub struct NRE1_W<'a> { + w: &'a mut W, +} +impl<'a> NRE1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `NRE2` reader - Non-Recoverable State 2 Output Enable"] +pub struct NRE2_R(crate::FieldReader); +impl NRE2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRE2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRE2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRE2` writer - Non-Recoverable State 2 Output Enable"] +pub struct NRE2_W<'a> { + w: &'a mut W, +} +impl<'a> NRE2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `NRE3` reader - Non-Recoverable State 3 Output Enable"] +pub struct NRE3_R(crate::FieldReader); +impl NRE3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRE3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRE3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRE3` writer - Non-Recoverable State 3 Output Enable"] +pub struct NRE3_W<'a> { + w: &'a mut W, +} +impl<'a> NRE3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `NRE4` reader - Non-Recoverable State 4 Output Enable"] +pub struct NRE4_R(crate::FieldReader); +impl NRE4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRE4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRE4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRE4` writer - Non-Recoverable State 4 Output Enable"] +pub struct NRE4_W<'a> { + w: &'a mut W, +} +impl<'a> NRE4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `NRE5` reader - Non-Recoverable State 5 Output Enable"] +pub struct NRE5_R(crate::FieldReader); +impl NRE5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRE5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRE5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRE5` writer - Non-Recoverable State 5 Output Enable"] +pub struct NRE5_W<'a> { + w: &'a mut W, +} +impl<'a> NRE5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `NRE6` reader - Non-Recoverable State 6 Output Enable"] +pub struct NRE6_R(crate::FieldReader); +impl NRE6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRE6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRE6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRE6` writer - Non-Recoverable State 6 Output Enable"] +pub struct NRE6_W<'a> { + w: &'a mut W, +} +impl<'a> NRE6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `NRE7` reader - Non-Recoverable State 7 Output Enable"] +pub struct NRE7_R(crate::FieldReader); +impl NRE7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRE7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRE7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRE7` writer - Non-Recoverable State 7 Output Enable"] +pub struct NRE7_W<'a> { + w: &'a mut W, +} +impl<'a> NRE7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `NRV0` reader - Non-Recoverable State 0 Output Value"] +pub struct NRV0_R(crate::FieldReader); +impl NRV0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRV0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRV0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRV0` writer - Non-Recoverable State 0 Output Value"] +pub struct NRV0_W<'a> { + w: &'a mut W, +} +impl<'a> NRV0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `NRV1` reader - Non-Recoverable State 1 Output Value"] +pub struct NRV1_R(crate::FieldReader); +impl NRV1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRV1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRV1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRV1` writer - Non-Recoverable State 1 Output Value"] +pub struct NRV1_W<'a> { + w: &'a mut W, +} +impl<'a> NRV1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `NRV2` reader - Non-Recoverable State 2 Output Value"] +pub struct NRV2_R(crate::FieldReader); +impl NRV2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRV2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRV2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRV2` writer - Non-Recoverable State 2 Output Value"] +pub struct NRV2_W<'a> { + w: &'a mut W, +} +impl<'a> NRV2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `NRV3` reader - Non-Recoverable State 3 Output Value"] +pub struct NRV3_R(crate::FieldReader); +impl NRV3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRV3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRV3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRV3` writer - Non-Recoverable State 3 Output Value"] +pub struct NRV3_W<'a> { + w: &'a mut W, +} +impl<'a> NRV3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `NRV4` reader - Non-Recoverable State 4 Output Value"] +pub struct NRV4_R(crate::FieldReader); +impl NRV4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRV4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRV4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRV4` writer - Non-Recoverable State 4 Output Value"] +pub struct NRV4_W<'a> { + w: &'a mut W, +} +impl<'a> NRV4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `NRV5` reader - Non-Recoverable State 5 Output Value"] +pub struct NRV5_R(crate::FieldReader); +impl NRV5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRV5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRV5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRV5` writer - Non-Recoverable State 5 Output Value"] +pub struct NRV5_W<'a> { + w: &'a mut W, +} +impl<'a> NRV5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `NRV6` reader - Non-Recoverable State 6 Output Value"] +pub struct NRV6_R(crate::FieldReader); +impl NRV6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRV6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRV6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRV6` writer - Non-Recoverable State 6 Output Value"] +pub struct NRV6_W<'a> { + w: &'a mut W, +} +impl<'a> NRV6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `NRV7` reader - Non-Recoverable State 7 Output Value"] +pub struct NRV7_R(crate::FieldReader); +impl NRV7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRV7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRV7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRV7` writer - Non-Recoverable State 7 Output Value"] +pub struct NRV7_W<'a> { + w: &'a mut W, +} +impl<'a> NRV7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `INVEN0` reader - Output Waveform 0 Inversion"] +pub struct INVEN0_R(crate::FieldReader); +impl INVEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN0` writer - Output Waveform 0 Inversion"] +pub struct INVEN0_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `INVEN1` reader - Output Waveform 1 Inversion"] +pub struct INVEN1_R(crate::FieldReader); +impl INVEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN1` writer - Output Waveform 1 Inversion"] +pub struct INVEN1_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `INVEN2` reader - Output Waveform 2 Inversion"] +pub struct INVEN2_R(crate::FieldReader); +impl INVEN2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN2` writer - Output Waveform 2 Inversion"] +pub struct INVEN2_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `INVEN3` reader - Output Waveform 3 Inversion"] +pub struct INVEN3_R(crate::FieldReader); +impl INVEN3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN3` writer - Output Waveform 3 Inversion"] +pub struct INVEN3_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `INVEN4` reader - Output Waveform 4 Inversion"] +pub struct INVEN4_R(crate::FieldReader); +impl INVEN4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN4` writer - Output Waveform 4 Inversion"] +pub struct INVEN4_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `INVEN5` reader - Output Waveform 5 Inversion"] +pub struct INVEN5_R(crate::FieldReader); +impl INVEN5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN5` writer - Output Waveform 5 Inversion"] +pub struct INVEN5_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `INVEN6` reader - Output Waveform 6 Inversion"] +pub struct INVEN6_R(crate::FieldReader); +impl INVEN6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN6` writer - Output Waveform 6 Inversion"] +pub struct INVEN6_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `INVEN7` reader - Output Waveform 7 Inversion"] +pub struct INVEN7_R(crate::FieldReader); +impl INVEN7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN7` writer - Output Waveform 7 Inversion"] +pub struct INVEN7_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `FILTERVAL0` reader - Non-Recoverable Fault Input 0 Filter Value"] +pub struct FILTERVAL0_R(crate::FieldReader); +impl FILTERVAL0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FILTERVAL0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTERVAL0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTERVAL0` writer - Non-Recoverable Fault Input 0 Filter Value"] +pub struct FILTERVAL0_W<'a> { + w: &'a mut W, +} +impl<'a> FILTERVAL0_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Field `FILTERVAL1` reader - Non-Recoverable Fault Input 1 Filter Value"] +pub struct FILTERVAL1_R(crate::FieldReader); +impl FILTERVAL1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FILTERVAL1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTERVAL1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTERVAL1` writer - Non-Recoverable Fault Input 1 Filter Value"] +pub struct FILTERVAL1_W<'a> { + w: &'a mut W, +} +impl<'a> FILTERVAL1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 28)) | ((value as u32 & 0x0f) << 28); + self.w + } +} +impl R { + #[doc = "Bit 0 - Non-Recoverable State 0 Output Enable"] + #[inline(always)] + pub fn nre0(&self) -> NRE0_R { + NRE0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Non-Recoverable State 1 Output Enable"] + #[inline(always)] + pub fn nre1(&self) -> NRE1_R { + NRE1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Non-Recoverable State 2 Output Enable"] + #[inline(always)] + pub fn nre2(&self) -> NRE2_R { + NRE2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Non-Recoverable State 3 Output Enable"] + #[inline(always)] + pub fn nre3(&self) -> NRE3_R { + NRE3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Non-Recoverable State 4 Output Enable"] + #[inline(always)] + pub fn nre4(&self) -> NRE4_R { + NRE4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Non-Recoverable State 5 Output Enable"] + #[inline(always)] + pub fn nre5(&self) -> NRE5_R { + NRE5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Non-Recoverable State 6 Output Enable"] + #[inline(always)] + pub fn nre6(&self) -> NRE6_R { + NRE6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Non-Recoverable State 7 Output Enable"] + #[inline(always)] + pub fn nre7(&self) -> NRE7_R { + NRE7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Non-Recoverable State 0 Output Value"] + #[inline(always)] + pub fn nrv0(&self) -> NRV0_R { + NRV0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Non-Recoverable State 1 Output Value"] + #[inline(always)] + pub fn nrv1(&self) -> NRV1_R { + NRV1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Non-Recoverable State 2 Output Value"] + #[inline(always)] + pub fn nrv2(&self) -> NRV2_R { + NRV2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Non-Recoverable State 3 Output Value"] + #[inline(always)] + pub fn nrv3(&self) -> NRV3_R { + NRV3_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Non-Recoverable State 4 Output Value"] + #[inline(always)] + pub fn nrv4(&self) -> NRV4_R { + NRV4_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Non-Recoverable State 5 Output Value"] + #[inline(always)] + pub fn nrv5(&self) -> NRV5_R { + NRV5_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Non-Recoverable State 6 Output Value"] + #[inline(always)] + pub fn nrv6(&self) -> NRV6_R { + NRV6_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Non-Recoverable State 7 Output Value"] + #[inline(always)] + pub fn nrv7(&self) -> NRV7_R { + NRV7_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Output Waveform 0 Inversion"] + #[inline(always)] + pub fn inven0(&self) -> INVEN0_R { + INVEN0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Output Waveform 1 Inversion"] + #[inline(always)] + pub fn inven1(&self) -> INVEN1_R { + INVEN1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Output Waveform 2 Inversion"] + #[inline(always)] + pub fn inven2(&self) -> INVEN2_R { + INVEN2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Output Waveform 3 Inversion"] + #[inline(always)] + pub fn inven3(&self) -> INVEN3_R { + INVEN3_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Output Waveform 4 Inversion"] + #[inline(always)] + pub fn inven4(&self) -> INVEN4_R { + INVEN4_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Output Waveform 5 Inversion"] + #[inline(always)] + pub fn inven5(&self) -> INVEN5_R { + INVEN5_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Output Waveform 6 Inversion"] + #[inline(always)] + pub fn inven6(&self) -> INVEN6_R { + INVEN6_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Output Waveform 7 Inversion"] + #[inline(always)] + pub fn inven7(&self) -> INVEN7_R { + INVEN7_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bits 24:27 - Non-Recoverable Fault Input 0 Filter Value"] + #[inline(always)] + pub fn filterval0(&self) -> FILTERVAL0_R { + FILTERVAL0_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bits 28:31 - Non-Recoverable Fault Input 1 Filter Value"] + #[inline(always)] + pub fn filterval1(&self) -> FILTERVAL1_R { + FILTERVAL1_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bit 0 - Non-Recoverable State 0 Output Enable"] + #[inline(always)] + pub fn nre0(&mut self) -> NRE0_W { + NRE0_W { w: self } + } + #[doc = "Bit 1 - Non-Recoverable State 1 Output Enable"] + #[inline(always)] + pub fn nre1(&mut self) -> NRE1_W { + NRE1_W { w: self } + } + #[doc = "Bit 2 - Non-Recoverable State 2 Output Enable"] + #[inline(always)] + pub fn nre2(&mut self) -> NRE2_W { + NRE2_W { w: self } + } + #[doc = "Bit 3 - Non-Recoverable State 3 Output Enable"] + #[inline(always)] + pub fn nre3(&mut self) -> NRE3_W { + NRE3_W { w: self } + } + #[doc = "Bit 4 - Non-Recoverable State 4 Output Enable"] + #[inline(always)] + pub fn nre4(&mut self) -> NRE4_W { + NRE4_W { w: self } + } + #[doc = "Bit 5 - Non-Recoverable State 5 Output Enable"] + #[inline(always)] + pub fn nre5(&mut self) -> NRE5_W { + NRE5_W { w: self } + } + #[doc = "Bit 6 - Non-Recoverable State 6 Output Enable"] + #[inline(always)] + pub fn nre6(&mut self) -> NRE6_W { + NRE6_W { w: self } + } + #[doc = "Bit 7 - Non-Recoverable State 7 Output Enable"] + #[inline(always)] + pub fn nre7(&mut self) -> NRE7_W { + NRE7_W { w: self } + } + #[doc = "Bit 8 - Non-Recoverable State 0 Output Value"] + #[inline(always)] + pub fn nrv0(&mut self) -> NRV0_W { + NRV0_W { w: self } + } + #[doc = "Bit 9 - Non-Recoverable State 1 Output Value"] + #[inline(always)] + pub fn nrv1(&mut self) -> NRV1_W { + NRV1_W { w: self } + } + #[doc = "Bit 10 - Non-Recoverable State 2 Output Value"] + #[inline(always)] + pub fn nrv2(&mut self) -> NRV2_W { + NRV2_W { w: self } + } + #[doc = "Bit 11 - Non-Recoverable State 3 Output Value"] + #[inline(always)] + pub fn nrv3(&mut self) -> NRV3_W { + NRV3_W { w: self } + } + #[doc = "Bit 12 - Non-Recoverable State 4 Output Value"] + #[inline(always)] + pub fn nrv4(&mut self) -> NRV4_W { + NRV4_W { w: self } + } + #[doc = "Bit 13 - Non-Recoverable State 5 Output Value"] + #[inline(always)] + pub fn nrv5(&mut self) -> NRV5_W { + NRV5_W { w: self } + } + #[doc = "Bit 14 - Non-Recoverable State 6 Output Value"] + #[inline(always)] + pub fn nrv6(&mut self) -> NRV6_W { + NRV6_W { w: self } + } + #[doc = "Bit 15 - Non-Recoverable State 7 Output Value"] + #[inline(always)] + pub fn nrv7(&mut self) -> NRV7_W { + NRV7_W { w: self } + } + #[doc = "Bit 16 - Output Waveform 0 Inversion"] + #[inline(always)] + pub fn inven0(&mut self) -> INVEN0_W { + INVEN0_W { w: self } + } + #[doc = "Bit 17 - Output Waveform 1 Inversion"] + #[inline(always)] + pub fn inven1(&mut self) -> INVEN1_W { + INVEN1_W { w: self } + } + #[doc = "Bit 18 - Output Waveform 2 Inversion"] + #[inline(always)] + pub fn inven2(&mut self) -> INVEN2_W { + INVEN2_W { w: self } + } + #[doc = "Bit 19 - Output Waveform 3 Inversion"] + #[inline(always)] + pub fn inven3(&mut self) -> INVEN3_W { + INVEN3_W { w: self } + } + #[doc = "Bit 20 - Output Waveform 4 Inversion"] + #[inline(always)] + pub fn inven4(&mut self) -> INVEN4_W { + INVEN4_W { w: self } + } + #[doc = "Bit 21 - Output Waveform 5 Inversion"] + #[inline(always)] + pub fn inven5(&mut self) -> INVEN5_W { + INVEN5_W { w: self } + } + #[doc = "Bit 22 - Output Waveform 6 Inversion"] + #[inline(always)] + pub fn inven6(&mut self) -> INVEN6_W { + INVEN6_W { w: self } + } + #[doc = "Bit 23 - Output Waveform 7 Inversion"] + #[inline(always)] + pub fn inven7(&mut self) -> INVEN7_W { + INVEN7_W { w: self } + } + #[doc = "Bits 24:27 - Non-Recoverable Fault Input 0 Filter Value"] + #[inline(always)] + pub fn filterval0(&mut self) -> FILTERVAL0_W { + FILTERVAL0_W { w: self } + } + #[doc = "Bits 28:31 - Non-Recoverable Fault Input 1 Filter Value"] + #[inline(always)] + pub fn filterval1(&mut self) -> FILTERVAL1_W { + FILTERVAL1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Driver Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [drvctrl](index.html) module"] +pub struct DRVCTRL_SPEC; +impl crate::RegisterSpec for DRVCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [drvctrl::R](R) reader structure"] +impl crate::Readable for DRVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [drvctrl::W](W) writer structure"] +impl crate::Writable for DRVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DRVCTRL to value 0"] +impl crate::Resettable for DRVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/tcc0/evctrl.rs b/pac/atsamc21e/src/tcc0/evctrl.rs new file mode 100644 index 000000000000..334a53924d61 --- /dev/null +++ b/pac/atsamc21e/src/tcc0/evctrl.rs @@ -0,0 +1,1211 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Timer/counter Input Event0 Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EVACT0_A { + #[doc = "0: Event action disabled"] + OFF = 0, + #[doc = "1: Start, restart or re-trigger counter on event"] + RETRIGGER = 1, + #[doc = "2: Count on event"] + COUNTEV = 2, + #[doc = "3: Start counter on event"] + START = 3, + #[doc = "4: Increment counter on event"] + INC = 4, + #[doc = "5: Count on active state of asynchronous event"] + COUNT = 5, + #[doc = "6: Stamp capture"] + STAMP = 6, + #[doc = "7: Non-recoverable fault"] + FAULT = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EVACT0_A) -> Self { + variant as _ + } +} +#[doc = "Field `EVACT0` reader - Timer/counter Input Event0 Action"] +pub struct EVACT0_R(crate::FieldReader); +impl EVACT0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVACT0_A { + match self.bits { + 0 => EVACT0_A::OFF, + 1 => EVACT0_A::RETRIGGER, + 2 => EVACT0_A::COUNTEV, + 3 => EVACT0_A::START, + 4 => EVACT0_A::INC, + 5 => EVACT0_A::COUNT, + 6 => EVACT0_A::STAMP, + 7 => EVACT0_A::FAULT, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == EVACT0_A::OFF + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == EVACT0_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `COUNTEV`"] + #[inline(always)] + pub fn is_countev(&self) -> bool { + **self == EVACT0_A::COUNTEV + } + #[doc = "Checks if the value of the field is `START`"] + #[inline(always)] + pub fn is_start(&self) -> bool { + **self == EVACT0_A::START + } + #[doc = "Checks if the value of the field is `INC`"] + #[inline(always)] + pub fn is_inc(&self) -> bool { + **self == EVACT0_A::INC + } + #[doc = "Checks if the value of the field is `COUNT`"] + #[inline(always)] + pub fn is_count(&self) -> bool { + **self == EVACT0_A::COUNT + } + #[doc = "Checks if the value of the field is `STAMP`"] + #[inline(always)] + pub fn is_stamp(&self) -> bool { + **self == EVACT0_A::STAMP + } + #[doc = "Checks if the value of the field is `FAULT`"] + #[inline(always)] + pub fn is_fault(&self) -> bool { + **self == EVACT0_A::FAULT + } +} +impl core::ops::Deref for EVACT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT0` writer - Timer/counter Input Event0 Action"] +pub struct EVACT0_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT0_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EVACT0_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Event action disabled"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(EVACT0_A::OFF) + } + #[doc = "Start, restart or re-trigger counter on event"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(EVACT0_A::RETRIGGER) + } + #[doc = "Count on event"] + #[inline(always)] + pub fn countev(self) -> &'a mut W { + self.variant(EVACT0_A::COUNTEV) + } + #[doc = "Start counter on event"] + #[inline(always)] + pub fn start(self) -> &'a mut W { + self.variant(EVACT0_A::START) + } + #[doc = "Increment counter on event"] + #[inline(always)] + pub fn inc(self) -> &'a mut W { + self.variant(EVACT0_A::INC) + } + #[doc = "Count on active state of asynchronous event"] + #[inline(always)] + pub fn count(self) -> &'a mut W { + self.variant(EVACT0_A::COUNT) + } + #[doc = "Stamp capture"] + #[inline(always)] + pub fn stamp(self) -> &'a mut W { + self.variant(EVACT0_A::STAMP) + } + #[doc = "Non-recoverable fault"] + #[inline(always)] + pub fn fault(self) -> &'a mut W { + self.variant(EVACT0_A::FAULT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Timer/counter Input Event1 Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EVACT1_A { + #[doc = "0: Event action disabled"] + OFF = 0, + #[doc = "1: Re-trigger counter on event"] + RETRIGGER = 1, + #[doc = "2: Direction control"] + DIR = 2, + #[doc = "3: Stop counter on event"] + STOP = 3, + #[doc = "4: Decrement counter on event"] + DEC = 4, + #[doc = "5: Period capture value in CC0 register, pulse width capture value in CC1 register"] + PPW = 5, + #[doc = "6: Period capture value in CC1 register, pulse width capture value in CC0 register"] + PWP = 6, + #[doc = "7: Non-recoverable fault"] + FAULT = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EVACT1_A) -> Self { + variant as _ + } +} +#[doc = "Field `EVACT1` reader - Timer/counter Input Event1 Action"] +pub struct EVACT1_R(crate::FieldReader); +impl EVACT1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT1_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVACT1_A { + match self.bits { + 0 => EVACT1_A::OFF, + 1 => EVACT1_A::RETRIGGER, + 2 => EVACT1_A::DIR, + 3 => EVACT1_A::STOP, + 4 => EVACT1_A::DEC, + 5 => EVACT1_A::PPW, + 6 => EVACT1_A::PWP, + 7 => EVACT1_A::FAULT, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == EVACT1_A::OFF + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == EVACT1_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `DIR`"] + #[inline(always)] + pub fn is_dir(&self) -> bool { + **self == EVACT1_A::DIR + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == EVACT1_A::STOP + } + #[doc = "Checks if the value of the field is `DEC`"] + #[inline(always)] + pub fn is_dec(&self) -> bool { + **self == EVACT1_A::DEC + } + #[doc = "Checks if the value of the field is `PPW`"] + #[inline(always)] + pub fn is_ppw(&self) -> bool { + **self == EVACT1_A::PPW + } + #[doc = "Checks if the value of the field is `PWP`"] + #[inline(always)] + pub fn is_pwp(&self) -> bool { + **self == EVACT1_A::PWP + } + #[doc = "Checks if the value of the field is `FAULT`"] + #[inline(always)] + pub fn is_fault(&self) -> bool { + **self == EVACT1_A::FAULT + } +} +impl core::ops::Deref for EVACT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT1` writer - Timer/counter Input Event1 Action"] +pub struct EVACT1_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT1_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EVACT1_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Event action disabled"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(EVACT1_A::OFF) + } + #[doc = "Re-trigger counter on event"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(EVACT1_A::RETRIGGER) + } + #[doc = "Direction control"] + #[inline(always)] + pub fn dir(self) -> &'a mut W { + self.variant(EVACT1_A::DIR) + } + #[doc = "Stop counter on event"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(EVACT1_A::STOP) + } + #[doc = "Decrement counter on event"] + #[inline(always)] + pub fn dec(self) -> &'a mut W { + self.variant(EVACT1_A::DEC) + } + #[doc = "Period capture value in CC0 register, pulse width capture value in CC1 register"] + #[inline(always)] + pub fn ppw(self) -> &'a mut W { + self.variant(EVACT1_A::PPW) + } + #[doc = "Period capture value in CC1 register, pulse width capture value in CC0 register"] + #[inline(always)] + pub fn pwp(self) -> &'a mut W { + self.variant(EVACT1_A::PWP) + } + #[doc = "Non-recoverable fault"] + #[inline(always)] + pub fn fault(self) -> &'a mut W { + self.variant(EVACT1_A::FAULT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 3)) | ((value as u32 & 0x07) << 3); + self.w + } +} +#[doc = "Timer/counter Output Event Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CNTSEL_A { + #[doc = "0: An interrupt/event is generated when a new counter cycle starts"] + START = 0, + #[doc = "1: An interrupt/event is generated when a counter cycle ends"] + END = 1, + #[doc = "2: An interrupt/event is generated when a counter cycle ends, except for the first and last cycles"] + BETWEEN = 2, + #[doc = "3: An interrupt/event is generated when a new counter cycle starts or a counter cycle ends"] + BOUNDARY = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CNTSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `CNTSEL` reader - Timer/counter Output Event Mode"] +pub struct CNTSEL_R(crate::FieldReader); +impl CNTSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CNTSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CNTSEL_A { + match self.bits { + 0 => CNTSEL_A::START, + 1 => CNTSEL_A::END, + 2 => CNTSEL_A::BETWEEN, + 3 => CNTSEL_A::BOUNDARY, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `START`"] + #[inline(always)] + pub fn is_start(&self) -> bool { + **self == CNTSEL_A::START + } + #[doc = "Checks if the value of the field is `END`"] + #[inline(always)] + pub fn is_end(&self) -> bool { + **self == CNTSEL_A::END + } + #[doc = "Checks if the value of the field is `BETWEEN`"] + #[inline(always)] + pub fn is_between(&self) -> bool { + **self == CNTSEL_A::BETWEEN + } + #[doc = "Checks if the value of the field is `BOUNDARY`"] + #[inline(always)] + pub fn is_boundary(&self) -> bool { + **self == CNTSEL_A::BOUNDARY + } +} +impl core::ops::Deref for CNTSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CNTSEL` writer - Timer/counter Output Event Mode"] +pub struct CNTSEL_W<'a> { + w: &'a mut W, +} +impl<'a> CNTSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CNTSEL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "An interrupt/event is generated when a new counter cycle starts"] + #[inline(always)] + pub fn start(self) -> &'a mut W { + self.variant(CNTSEL_A::START) + } + #[doc = "An interrupt/event is generated when a counter cycle ends"] + #[inline(always)] + pub fn end(self) -> &'a mut W { + self.variant(CNTSEL_A::END) + } + #[doc = "An interrupt/event is generated when a counter cycle ends, except for the first and last cycles"] + #[inline(always)] + pub fn between(self) -> &'a mut W { + self.variant(CNTSEL_A::BETWEEN) + } + #[doc = "An interrupt/event is generated when a new counter cycle starts or a counter cycle ends"] + #[inline(always)] + pub fn boundary(self) -> &'a mut W { + self.variant(CNTSEL_A::BOUNDARY) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 6)) | ((value as u32 & 0x03) << 6); + self.w + } +} +#[doc = "Field `OVFEO` reader - Overflow/Underflow Output Event Enable"] +pub struct OVFEO_R(crate::FieldReader); +impl OVFEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVFEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVFEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVFEO` writer - Overflow/Underflow Output Event Enable"] +pub struct OVFEO_W<'a> { + w: &'a mut W, +} +impl<'a> OVFEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `TRGEO` reader - Retrigger Output Event Enable"] +pub struct TRGEO_R(crate::FieldReader); +impl TRGEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRGEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRGEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRGEO` writer - Retrigger Output Event Enable"] +pub struct TRGEO_W<'a> { + w: &'a mut W, +} +impl<'a> TRGEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `CNTEO` reader - Timer/counter Output Event Enable"] +pub struct CNTEO_R(crate::FieldReader); +impl CNTEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CNTEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CNTEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CNTEO` writer - Timer/counter Output Event Enable"] +pub struct CNTEO_W<'a> { + w: &'a mut W, +} +impl<'a> CNTEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `TCINV0` reader - Inverted Event 0 Input Enable"] +pub struct TCINV0_R(crate::FieldReader); +impl TCINV0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCINV0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCINV0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCINV0` writer - Inverted Event 0 Input Enable"] +pub struct TCINV0_W<'a> { + w: &'a mut W, +} +impl<'a> TCINV0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `TCINV1` reader - Inverted Event 1 Input Enable"] +pub struct TCINV1_R(crate::FieldReader); +impl TCINV1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCINV1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCINV1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCINV1` writer - Inverted Event 1 Input Enable"] +pub struct TCINV1_W<'a> { + w: &'a mut W, +} +impl<'a> TCINV1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `TCEI0` reader - Timer/counter Event 0 Input Enable"] +pub struct TCEI0_R(crate::FieldReader); +impl TCEI0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCEI0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCEI0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCEI0` writer - Timer/counter Event 0 Input Enable"] +pub struct TCEI0_W<'a> { + w: &'a mut W, +} +impl<'a> TCEI0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `TCEI1` reader - Timer/counter Event 1 Input Enable"] +pub struct TCEI1_R(crate::FieldReader); +impl TCEI1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCEI1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCEI1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCEI1` writer - Timer/counter Event 1 Input Enable"] +pub struct TCEI1_W<'a> { + w: &'a mut W, +} +impl<'a> TCEI1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `MCEI0` reader - Match or Capture Channel 0 Event Input Enable"] +pub struct MCEI0_R(crate::FieldReader); +impl MCEI0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEI0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEI0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEI0` writer - Match or Capture Channel 0 Event Input Enable"] +pub struct MCEI0_W<'a> { + w: &'a mut W, +} +impl<'a> MCEI0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `MCEI1` reader - Match or Capture Channel 1 Event Input Enable"] +pub struct MCEI1_R(crate::FieldReader); +impl MCEI1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEI1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEI1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEI1` writer - Match or Capture Channel 1 Event Input Enable"] +pub struct MCEI1_W<'a> { + w: &'a mut W, +} +impl<'a> MCEI1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `MCEI2` reader - Match or Capture Channel 2 Event Input Enable"] +pub struct MCEI2_R(crate::FieldReader); +impl MCEI2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEI2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEI2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEI2` writer - Match or Capture Channel 2 Event Input Enable"] +pub struct MCEI2_W<'a> { + w: &'a mut W, +} +impl<'a> MCEI2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `MCEI3` reader - Match or Capture Channel 3 Event Input Enable"] +pub struct MCEI3_R(crate::FieldReader); +impl MCEI3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEI3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEI3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEI3` writer - Match or Capture Channel 3 Event Input Enable"] +pub struct MCEI3_W<'a> { + w: &'a mut W, +} +impl<'a> MCEI3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `MCEO0` reader - Match or Capture Channel 0 Event Output Enable"] +pub struct MCEO0_R(crate::FieldReader); +impl MCEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO0` writer - Match or Capture Channel 0 Event Output Enable"] +pub struct MCEO0_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `MCEO1` reader - Match or Capture Channel 1 Event Output Enable"] +pub struct MCEO1_R(crate::FieldReader); +impl MCEO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO1` writer - Match or Capture Channel 1 Event Output Enable"] +pub struct MCEO1_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `MCEO2` reader - Match or Capture Channel 2 Event Output Enable"] +pub struct MCEO2_R(crate::FieldReader); +impl MCEO2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO2` writer - Match or Capture Channel 2 Event Output Enable"] +pub struct MCEO2_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `MCEO3` reader - Match or Capture Channel 3 Event Output Enable"] +pub struct MCEO3_R(crate::FieldReader); +impl MCEO3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO3` writer - Match or Capture Channel 3 Event Output Enable"] +pub struct MCEO3_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Timer/counter Input Event0 Action"] + #[inline(always)] + pub fn evact0(&self) -> EVACT0_R { + EVACT0_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bits 3:5 - Timer/counter Input Event1 Action"] + #[inline(always)] + pub fn evact1(&self) -> EVACT1_R { + EVACT1_R::new(((self.bits >> 3) & 0x07) as u8) + } + #[doc = "Bits 6:7 - Timer/counter Output Event Mode"] + #[inline(always)] + pub fn cntsel(&self) -> CNTSEL_R { + CNTSEL_R::new(((self.bits >> 6) & 0x03) as u8) + } + #[doc = "Bit 8 - Overflow/Underflow Output Event Enable"] + #[inline(always)] + pub fn ovfeo(&self) -> OVFEO_R { + OVFEO_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Retrigger Output Event Enable"] + #[inline(always)] + pub fn trgeo(&self) -> TRGEO_R { + TRGEO_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Timer/counter Output Event Enable"] + #[inline(always)] + pub fn cnteo(&self) -> CNTEO_R { + CNTEO_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 12 - Inverted Event 0 Input Enable"] + #[inline(always)] + pub fn tcinv0(&self) -> TCINV0_R { + TCINV0_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Inverted Event 1 Input Enable"] + #[inline(always)] + pub fn tcinv1(&self) -> TCINV1_R { + TCINV1_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Timer/counter Event 0 Input Enable"] + #[inline(always)] + pub fn tcei0(&self) -> TCEI0_R { + TCEI0_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Timer/counter Event 1 Input Enable"] + #[inline(always)] + pub fn tcei1(&self) -> TCEI1_R { + TCEI1_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Match or Capture Channel 0 Event Input Enable"] + #[inline(always)] + pub fn mcei0(&self) -> MCEI0_R { + MCEI0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Match or Capture Channel 1 Event Input Enable"] + #[inline(always)] + pub fn mcei1(&self) -> MCEI1_R { + MCEI1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Match or Capture Channel 2 Event Input Enable"] + #[inline(always)] + pub fn mcei2(&self) -> MCEI2_R { + MCEI2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Match or Capture Channel 3 Event Input Enable"] + #[inline(always)] + pub fn mcei3(&self) -> MCEI3_R { + MCEI3_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 24 - Match or Capture Channel 0 Event Output Enable"] + #[inline(always)] + pub fn mceo0(&self) -> MCEO0_R { + MCEO0_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Match or Capture Channel 1 Event Output Enable"] + #[inline(always)] + pub fn mceo1(&self) -> MCEO1_R { + MCEO1_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Match or Capture Channel 2 Event Output Enable"] + #[inline(always)] + pub fn mceo2(&self) -> MCEO2_R { + MCEO2_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Match or Capture Channel 3 Event Output Enable"] + #[inline(always)] + pub fn mceo3(&self) -> MCEO3_R { + MCEO3_R::new(((self.bits >> 27) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Timer/counter Input Event0 Action"] + #[inline(always)] + pub fn evact0(&mut self) -> EVACT0_W { + EVACT0_W { w: self } + } + #[doc = "Bits 3:5 - Timer/counter Input Event1 Action"] + #[inline(always)] + pub fn evact1(&mut self) -> EVACT1_W { + EVACT1_W { w: self } + } + #[doc = "Bits 6:7 - Timer/counter Output Event Mode"] + #[inline(always)] + pub fn cntsel(&mut self) -> CNTSEL_W { + CNTSEL_W { w: self } + } + #[doc = "Bit 8 - Overflow/Underflow Output Event Enable"] + #[inline(always)] + pub fn ovfeo(&mut self) -> OVFEO_W { + OVFEO_W { w: self } + } + #[doc = "Bit 9 - Retrigger Output Event Enable"] + #[inline(always)] + pub fn trgeo(&mut self) -> TRGEO_W { + TRGEO_W { w: self } + } + #[doc = "Bit 10 - Timer/counter Output Event Enable"] + #[inline(always)] + pub fn cnteo(&mut self) -> CNTEO_W { + CNTEO_W { w: self } + } + #[doc = "Bit 12 - Inverted Event 0 Input Enable"] + #[inline(always)] + pub fn tcinv0(&mut self) -> TCINV0_W { + TCINV0_W { w: self } + } + #[doc = "Bit 13 - Inverted Event 1 Input Enable"] + #[inline(always)] + pub fn tcinv1(&mut self) -> TCINV1_W { + TCINV1_W { w: self } + } + #[doc = "Bit 14 - Timer/counter Event 0 Input Enable"] + #[inline(always)] + pub fn tcei0(&mut self) -> TCEI0_W { + TCEI0_W { w: self } + } + #[doc = "Bit 15 - Timer/counter Event 1 Input Enable"] + #[inline(always)] + pub fn tcei1(&mut self) -> TCEI1_W { + TCEI1_W { w: self } + } + #[doc = "Bit 16 - Match or Capture Channel 0 Event Input Enable"] + #[inline(always)] + pub fn mcei0(&mut self) -> MCEI0_W { + MCEI0_W { w: self } + } + #[doc = "Bit 17 - Match or Capture Channel 1 Event Input Enable"] + #[inline(always)] + pub fn mcei1(&mut self) -> MCEI1_W { + MCEI1_W { w: self } + } + #[doc = "Bit 18 - Match or Capture Channel 2 Event Input Enable"] + #[inline(always)] + pub fn mcei2(&mut self) -> MCEI2_W { + MCEI2_W { w: self } + } + #[doc = "Bit 19 - Match or Capture Channel 3 Event Input Enable"] + #[inline(always)] + pub fn mcei3(&mut self) -> MCEI3_W { + MCEI3_W { w: self } + } + #[doc = "Bit 24 - Match or Capture Channel 0 Event Output Enable"] + #[inline(always)] + pub fn mceo0(&mut self) -> MCEO0_W { + MCEO0_W { w: self } + } + #[doc = "Bit 25 - Match or Capture Channel 1 Event Output Enable"] + #[inline(always)] + pub fn mceo1(&mut self) -> MCEO1_W { + MCEO1_W { w: self } + } + #[doc = "Bit 26 - Match or Capture Channel 2 Event Output Enable"] + #[inline(always)] + pub fn mceo2(&mut self) -> MCEO2_W { + MCEO2_W { w: self } + } + #[doc = "Bit 27 - Match or Capture Channel 3 Event Output Enable"] + #[inline(always)] + pub fn mceo3(&mut self) -> MCEO3_W { + MCEO3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/tcc0/fctrla.rs b/pac/atsamc21e/src/tcc0/fctrla.rs new file mode 100644 index 000000000000..77c7276fee23 --- /dev/null +++ b/pac/atsamc21e/src/tcc0/fctrla.rs @@ -0,0 +1,940 @@ +#[doc = "Register `FCTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FCTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Fault A Source\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SRC_A { + #[doc = "0: Fault input disabled"] + DISABLE = 0, + #[doc = "1: MCEx (x=0,1) event input"] + ENABLE = 1, + #[doc = "2: Inverted MCEx (x=0,1) event input"] + INVERT = 2, + #[doc = "3: Alternate fault (A or B) state at the end of the previous period"] + ALTFAULT = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SRC_A) -> Self { + variant as _ + } +} +#[doc = "Field `SRC` reader - Fault A Source"] +pub struct SRC_R(crate::FieldReader); +impl SRC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SRC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SRC_A { + match self.bits { + 0 => SRC_A::DISABLE, + 1 => SRC_A::ENABLE, + 2 => SRC_A::INVERT, + 3 => SRC_A::ALTFAULT, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == SRC_A::DISABLE + } + #[doc = "Checks if the value of the field is `ENABLE`"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + **self == SRC_A::ENABLE + } + #[doc = "Checks if the value of the field is `INVERT`"] + #[inline(always)] + pub fn is_invert(&self) -> bool { + **self == SRC_A::INVERT + } + #[doc = "Checks if the value of the field is `ALTFAULT`"] + #[inline(always)] + pub fn is_altfault(&self) -> bool { + **self == SRC_A::ALTFAULT + } +} +impl core::ops::Deref for SRC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SRC` writer - Fault A Source"] +pub struct SRC_W<'a> { + w: &'a mut W, +} +impl<'a> SRC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SRC_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Fault input disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(SRC_A::DISABLE) + } + #[doc = "MCEx (x=0,1) event input"] + #[inline(always)] + pub fn enable(self) -> &'a mut W { + self.variant(SRC_A::ENABLE) + } + #[doc = "Inverted MCEx (x=0,1) event input"] + #[inline(always)] + pub fn invert(self) -> &'a mut W { + self.variant(SRC_A::INVERT) + } + #[doc = "Alternate fault (A or B) state at the end of the previous period"] + #[inline(always)] + pub fn altfault(self) -> &'a mut W { + self.variant(SRC_A::ALTFAULT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u32 & 0x03); + self.w + } +} +#[doc = "Field `KEEP` reader - Fault A Keeper"] +pub struct KEEP_R(crate::FieldReader); +impl KEEP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + KEEP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for KEEP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `KEEP` writer - Fault A Keeper"] +pub struct KEEP_W<'a> { + w: &'a mut W, +} +impl<'a> KEEP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `QUAL` reader - Fault A Qualification"] +pub struct QUAL_R(crate::FieldReader); +impl QUAL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + QUAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for QUAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `QUAL` writer - Fault A Qualification"] +pub struct QUAL_W<'a> { + w: &'a mut W, +} +impl<'a> QUAL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Fault A Blanking Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum BLANK_A { + #[doc = "0: Blanking applied from start of the ramp"] + START = 0, + #[doc = "1: Blanking applied from rising edge of the output waveform"] + RISE = 1, + #[doc = "2: Blanking applied from falling edge of the output waveform"] + FALL = 2, + #[doc = "3: Blanking applied from each toggle of the output waveform"] + BOTH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: BLANK_A) -> Self { + variant as _ + } +} +#[doc = "Field `BLANK` reader - Fault A Blanking Mode"] +pub struct BLANK_R(crate::FieldReader); +impl BLANK_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BLANK_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> BLANK_A { + match self.bits { + 0 => BLANK_A::START, + 1 => BLANK_A::RISE, + 2 => BLANK_A::FALL, + 3 => BLANK_A::BOTH, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `START`"] + #[inline(always)] + pub fn is_start(&self) -> bool { + **self == BLANK_A::START + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == BLANK_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == BLANK_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == BLANK_A::BOTH + } +} +impl core::ops::Deref for BLANK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BLANK` writer - Fault A Blanking Mode"] +pub struct BLANK_W<'a> { + w: &'a mut W, +} +impl<'a> BLANK_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: BLANK_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Blanking applied from start of the ramp"] + #[inline(always)] + pub fn start(self) -> &'a mut W { + self.variant(BLANK_A::START) + } + #[doc = "Blanking applied from rising edge of the output waveform"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(BLANK_A::RISE) + } + #[doc = "Blanking applied from falling edge of the output waveform"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(BLANK_A::FALL) + } + #[doc = "Blanking applied from each toggle of the output waveform"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(BLANK_A::BOTH) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 5)) | ((value as u32 & 0x03) << 5); + self.w + } +} +#[doc = "Field `RESTART` reader - Fault A Restart"] +pub struct RESTART_R(crate::FieldReader); +impl RESTART_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESTART_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESTART_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESTART` writer - Fault A Restart"] +pub struct RESTART_W<'a> { + w: &'a mut W, +} +impl<'a> RESTART_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Fault A Halt Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum HALT_A { + #[doc = "0: Halt action disabled"] + DISABLE = 0, + #[doc = "1: Hardware halt action"] + HW = 1, + #[doc = "2: Software halt action"] + SW = 2, + #[doc = "3: Non-recoverable fault"] + NR = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: HALT_A) -> Self { + variant as _ + } +} +#[doc = "Field `HALT` reader - Fault A Halt Mode"] +pub struct HALT_R(crate::FieldReader); +impl HALT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + HALT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> HALT_A { + match self.bits { + 0 => HALT_A::DISABLE, + 1 => HALT_A::HW, + 2 => HALT_A::SW, + 3 => HALT_A::NR, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == HALT_A::DISABLE + } + #[doc = "Checks if the value of the field is `HW`"] + #[inline(always)] + pub fn is_hw(&self) -> bool { + **self == HALT_A::HW + } + #[doc = "Checks if the value of the field is `SW`"] + #[inline(always)] + pub fn is_sw(&self) -> bool { + **self == HALT_A::SW + } + #[doc = "Checks if the value of the field is `NR`"] + #[inline(always)] + pub fn is_nr(&self) -> bool { + **self == HALT_A::NR + } +} +impl core::ops::Deref for HALT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HALT` writer - Fault A Halt Mode"] +pub struct HALT_W<'a> { + w: &'a mut W, +} +impl<'a> HALT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: HALT_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Halt action disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(HALT_A::DISABLE) + } + #[doc = "Hardware halt action"] + #[inline(always)] + pub fn hw(self) -> &'a mut W { + self.variant(HALT_A::HW) + } + #[doc = "Software halt action"] + #[inline(always)] + pub fn sw(self) -> &'a mut W { + self.variant(HALT_A::SW) + } + #[doc = "Non-recoverable fault"] + #[inline(always)] + pub fn nr(self) -> &'a mut W { + self.variant(HALT_A::NR) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 8)) | ((value as u32 & 0x03) << 8); + self.w + } +} +#[doc = "Fault A Capture Channel\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CHSEL_A { + #[doc = "0: Capture value stored in channel 0"] + CC0 = 0, + #[doc = "1: Capture value stored in channel 1"] + CC1 = 1, + #[doc = "2: Capture value stored in channel 2"] + CC2 = 2, + #[doc = "3: Capture value stored in channel 3"] + CC3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CHSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `CHSEL` reader - Fault A Capture Channel"] +pub struct CHSEL_R(crate::FieldReader); +impl CHSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CHSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CHSEL_A { + match self.bits { + 0 => CHSEL_A::CC0, + 1 => CHSEL_A::CC1, + 2 => CHSEL_A::CC2, + 3 => CHSEL_A::CC3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `CC0`"] + #[inline(always)] + pub fn is_cc0(&self) -> bool { + **self == CHSEL_A::CC0 + } + #[doc = "Checks if the value of the field is `CC1`"] + #[inline(always)] + pub fn is_cc1(&self) -> bool { + **self == CHSEL_A::CC1 + } + #[doc = "Checks if the value of the field is `CC2`"] + #[inline(always)] + pub fn is_cc2(&self) -> bool { + **self == CHSEL_A::CC2 + } + #[doc = "Checks if the value of the field is `CC3`"] + #[inline(always)] + pub fn is_cc3(&self) -> bool { + **self == CHSEL_A::CC3 + } +} +impl core::ops::Deref for CHSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHSEL` writer - Fault A Capture Channel"] +pub struct CHSEL_W<'a> { + w: &'a mut W, +} +impl<'a> CHSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CHSEL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Capture value stored in channel 0"] + #[inline(always)] + pub fn cc0(self) -> &'a mut W { + self.variant(CHSEL_A::CC0) + } + #[doc = "Capture value stored in channel 1"] + #[inline(always)] + pub fn cc1(self) -> &'a mut W { + self.variant(CHSEL_A::CC1) + } + #[doc = "Capture value stored in channel 2"] + #[inline(always)] + pub fn cc2(self) -> &'a mut W { + self.variant(CHSEL_A::CC2) + } + #[doc = "Capture value stored in channel 3"] + #[inline(always)] + pub fn cc3(self) -> &'a mut W { + self.variant(CHSEL_A::CC3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 10)) | ((value as u32 & 0x03) << 10); + self.w + } +} +#[doc = "Fault A Capture Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CAPTURE_A { + #[doc = "0: No capture"] + DISABLE = 0, + #[doc = "1: Capture on fault"] + CAPT = 1, + #[doc = "2: Minimum capture"] + CAPTMIN = 2, + #[doc = "3: Maximum capture"] + CAPTMAX = 3, + #[doc = "4: Minimum local detection"] + LOCMIN = 4, + #[doc = "5: Maximum local detection"] + LOCMAX = 5, + #[doc = "6: Minimum and maximum local detection"] + DERIV0 = 6, + #[doc = "7: Capture with ramp index as MSB value"] + CAPTMARK = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CAPTURE_A) -> Self { + variant as _ + } +} +#[doc = "Field `CAPTURE` reader - Fault A Capture Action"] +pub struct CAPTURE_R(crate::FieldReader); +impl CAPTURE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CAPTURE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CAPTURE_A { + match self.bits { + 0 => CAPTURE_A::DISABLE, + 1 => CAPTURE_A::CAPT, + 2 => CAPTURE_A::CAPTMIN, + 3 => CAPTURE_A::CAPTMAX, + 4 => CAPTURE_A::LOCMIN, + 5 => CAPTURE_A::LOCMAX, + 6 => CAPTURE_A::DERIV0, + 7 => CAPTURE_A::CAPTMARK, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == CAPTURE_A::DISABLE + } + #[doc = "Checks if the value of the field is `CAPT`"] + #[inline(always)] + pub fn is_capt(&self) -> bool { + **self == CAPTURE_A::CAPT + } + #[doc = "Checks if the value of the field is `CAPTMIN`"] + #[inline(always)] + pub fn is_captmin(&self) -> bool { + **self == CAPTURE_A::CAPTMIN + } + #[doc = "Checks if the value of the field is `CAPTMAX`"] + #[inline(always)] + pub fn is_captmax(&self) -> bool { + **self == CAPTURE_A::CAPTMAX + } + #[doc = "Checks if the value of the field is `LOCMIN`"] + #[inline(always)] + pub fn is_locmin(&self) -> bool { + **self == CAPTURE_A::LOCMIN + } + #[doc = "Checks if the value of the field is `LOCMAX`"] + #[inline(always)] + pub fn is_locmax(&self) -> bool { + **self == CAPTURE_A::LOCMAX + } + #[doc = "Checks if the value of the field is `DERIV0`"] + #[inline(always)] + pub fn is_deriv0(&self) -> bool { + **self == CAPTURE_A::DERIV0 + } + #[doc = "Checks if the value of the field is `CAPTMARK`"] + #[inline(always)] + pub fn is_captmark(&self) -> bool { + **self == CAPTURE_A::CAPTMARK + } +} +impl core::ops::Deref for CAPTURE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAPTURE` writer - Fault A Capture Action"] +pub struct CAPTURE_W<'a> { + w: &'a mut W, +} +impl<'a> CAPTURE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CAPTURE_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "No capture"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(CAPTURE_A::DISABLE) + } + #[doc = "Capture on fault"] + #[inline(always)] + pub fn capt(self) -> &'a mut W { + self.variant(CAPTURE_A::CAPT) + } + #[doc = "Minimum capture"] + #[inline(always)] + pub fn captmin(self) -> &'a mut W { + self.variant(CAPTURE_A::CAPTMIN) + } + #[doc = "Maximum capture"] + #[inline(always)] + pub fn captmax(self) -> &'a mut W { + self.variant(CAPTURE_A::CAPTMAX) + } + #[doc = "Minimum local detection"] + #[inline(always)] + pub fn locmin(self) -> &'a mut W { + self.variant(CAPTURE_A::LOCMIN) + } + #[doc = "Maximum local detection"] + #[inline(always)] + pub fn locmax(self) -> &'a mut W { + self.variant(CAPTURE_A::LOCMAX) + } + #[doc = "Minimum and maximum local detection"] + #[inline(always)] + pub fn deriv0(self) -> &'a mut W { + self.variant(CAPTURE_A::DERIV0) + } + #[doc = "Capture with ramp index as MSB value"] + #[inline(always)] + pub fn captmark(self) -> &'a mut W { + self.variant(CAPTURE_A::CAPTMARK) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 12)) | ((value as u32 & 0x07) << 12); + self.w + } +} +#[doc = "Field `BLANKPRESC` reader - Fault A Blanking Prescaler"] +pub struct BLANKPRESC_R(crate::FieldReader); +impl BLANKPRESC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BLANKPRESC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BLANKPRESC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BLANKPRESC` writer - Fault A Blanking Prescaler"] +pub struct BLANKPRESC_W<'a> { + w: &'a mut W, +} +impl<'a> BLANKPRESC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `BLANKVAL` reader - Fault A Blanking Time"] +pub struct BLANKVAL_R(crate::FieldReader); +impl BLANKVAL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BLANKVAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BLANKVAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BLANKVAL` writer - Fault A Blanking Time"] +pub struct BLANKVAL_W<'a> { + w: &'a mut W, +} +impl<'a> BLANKVAL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +#[doc = "Field `FILTERVAL` reader - Fault A Filter Value"] +pub struct FILTERVAL_R(crate::FieldReader); +impl FILTERVAL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FILTERVAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTERVAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTERVAL` writer - Fault A Filter Value"] +pub struct FILTERVAL_W<'a> { + w: &'a mut W, +} +impl<'a> FILTERVAL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Fault A Source"] + #[inline(always)] + pub fn src(&self) -> SRC_R { + SRC_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bit 3 - Fault A Keeper"] + #[inline(always)] + pub fn keep(&self) -> KEEP_R { + KEEP_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Fault A Qualification"] + #[inline(always)] + pub fn qual(&self) -> QUAL_R { + QUAL_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bits 5:6 - Fault A Blanking Mode"] + #[inline(always)] + pub fn blank(&self) -> BLANK_R { + BLANK_R::new(((self.bits >> 5) & 0x03) as u8) + } + #[doc = "Bit 7 - Fault A Restart"] + #[inline(always)] + pub fn restart(&self) -> RESTART_R { + RESTART_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:9 - Fault A Halt Mode"] + #[inline(always)] + pub fn halt(&self) -> HALT_R { + HALT_R::new(((self.bits >> 8) & 0x03) as u8) + } + #[doc = "Bits 10:11 - Fault A Capture Channel"] + #[inline(always)] + pub fn chsel(&self) -> CHSEL_R { + CHSEL_R::new(((self.bits >> 10) & 0x03) as u8) + } + #[doc = "Bits 12:14 - Fault A Capture Action"] + #[inline(always)] + pub fn capture(&self) -> CAPTURE_R { + CAPTURE_R::new(((self.bits >> 12) & 0x07) as u8) + } + #[doc = "Bit 15 - Fault A Blanking Prescaler"] + #[inline(always)] + pub fn blankpresc(&self) -> BLANKPRESC_R { + BLANKPRESC_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:23 - Fault A Blanking Time"] + #[inline(always)] + pub fn blankval(&self) -> BLANKVAL_R { + BLANKVAL_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:27 - Fault A Filter Value"] + #[inline(always)] + pub fn filterval(&self) -> FILTERVAL_R { + FILTERVAL_R::new(((self.bits >> 24) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Fault A Source"] + #[inline(always)] + pub fn src(&mut self) -> SRC_W { + SRC_W { w: self } + } + #[doc = "Bit 3 - Fault A Keeper"] + #[inline(always)] + pub fn keep(&mut self) -> KEEP_W { + KEEP_W { w: self } + } + #[doc = "Bit 4 - Fault A Qualification"] + #[inline(always)] + pub fn qual(&mut self) -> QUAL_W { + QUAL_W { w: self } + } + #[doc = "Bits 5:6 - Fault A Blanking Mode"] + #[inline(always)] + pub fn blank(&mut self) -> BLANK_W { + BLANK_W { w: self } + } + #[doc = "Bit 7 - Fault A Restart"] + #[inline(always)] + pub fn restart(&mut self) -> RESTART_W { + RESTART_W { w: self } + } + #[doc = "Bits 8:9 - Fault A Halt Mode"] + #[inline(always)] + pub fn halt(&mut self) -> HALT_W { + HALT_W { w: self } + } + #[doc = "Bits 10:11 - Fault A Capture Channel"] + #[inline(always)] + pub fn chsel(&mut self) -> CHSEL_W { + CHSEL_W { w: self } + } + #[doc = "Bits 12:14 - Fault A Capture Action"] + #[inline(always)] + pub fn capture(&mut self) -> CAPTURE_W { + CAPTURE_W { w: self } + } + #[doc = "Bit 15 - Fault A Blanking Prescaler"] + #[inline(always)] + pub fn blankpresc(&mut self) -> BLANKPRESC_W { + BLANKPRESC_W { w: self } + } + #[doc = "Bits 16:23 - Fault A Blanking Time"] + #[inline(always)] + pub fn blankval(&mut self) -> BLANKVAL_W { + BLANKVAL_W { w: self } + } + #[doc = "Bits 24:27 - Fault A Filter Value"] + #[inline(always)] + pub fn filterval(&mut self) -> FILTERVAL_W { + FILTERVAL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Recoverable Fault A Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fctrla](index.html) module"] +pub struct FCTRLA_SPEC; +impl crate::RegisterSpec for FCTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [fctrla::R](R) reader structure"] +impl crate::Readable for FCTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [fctrla::W](W) writer structure"] +impl crate::Writable for FCTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets FCTRLA to value 0"] +impl crate::Resettable for FCTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/tcc0/fctrlb.rs b/pac/atsamc21e/src/tcc0/fctrlb.rs new file mode 100644 index 000000000000..4c1dfd1af93d --- /dev/null +++ b/pac/atsamc21e/src/tcc0/fctrlb.rs @@ -0,0 +1,940 @@ +#[doc = "Register `FCTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FCTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Fault B Source\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SRC_A { + #[doc = "0: Fault input disabled"] + DISABLE = 0, + #[doc = "1: MCEx (x=0,1) event input"] + ENABLE = 1, + #[doc = "2: Inverted MCEx (x=0,1) event input"] + INVERT = 2, + #[doc = "3: Alternate fault (A or B) state at the end of the previous period"] + ALTFAULT = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SRC_A) -> Self { + variant as _ + } +} +#[doc = "Field `SRC` reader - Fault B Source"] +pub struct SRC_R(crate::FieldReader); +impl SRC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SRC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SRC_A { + match self.bits { + 0 => SRC_A::DISABLE, + 1 => SRC_A::ENABLE, + 2 => SRC_A::INVERT, + 3 => SRC_A::ALTFAULT, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == SRC_A::DISABLE + } + #[doc = "Checks if the value of the field is `ENABLE`"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + **self == SRC_A::ENABLE + } + #[doc = "Checks if the value of the field is `INVERT`"] + #[inline(always)] + pub fn is_invert(&self) -> bool { + **self == SRC_A::INVERT + } + #[doc = "Checks if the value of the field is `ALTFAULT`"] + #[inline(always)] + pub fn is_altfault(&self) -> bool { + **self == SRC_A::ALTFAULT + } +} +impl core::ops::Deref for SRC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SRC` writer - Fault B Source"] +pub struct SRC_W<'a> { + w: &'a mut W, +} +impl<'a> SRC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SRC_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Fault input disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(SRC_A::DISABLE) + } + #[doc = "MCEx (x=0,1) event input"] + #[inline(always)] + pub fn enable(self) -> &'a mut W { + self.variant(SRC_A::ENABLE) + } + #[doc = "Inverted MCEx (x=0,1) event input"] + #[inline(always)] + pub fn invert(self) -> &'a mut W { + self.variant(SRC_A::INVERT) + } + #[doc = "Alternate fault (A or B) state at the end of the previous period"] + #[inline(always)] + pub fn altfault(self) -> &'a mut W { + self.variant(SRC_A::ALTFAULT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u32 & 0x03); + self.w + } +} +#[doc = "Field `KEEP` reader - Fault B Keeper"] +pub struct KEEP_R(crate::FieldReader); +impl KEEP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + KEEP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for KEEP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `KEEP` writer - Fault B Keeper"] +pub struct KEEP_W<'a> { + w: &'a mut W, +} +impl<'a> KEEP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `QUAL` reader - Fault B Qualification"] +pub struct QUAL_R(crate::FieldReader); +impl QUAL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + QUAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for QUAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `QUAL` writer - Fault B Qualification"] +pub struct QUAL_W<'a> { + w: &'a mut W, +} +impl<'a> QUAL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Fault B Blanking Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum BLANK_A { + #[doc = "0: Blanking applied from start of the ramp"] + START = 0, + #[doc = "1: Blanking applied from rising edge of the output waveform"] + RISE = 1, + #[doc = "2: Blanking applied from falling edge of the output waveform"] + FALL = 2, + #[doc = "3: Blanking applied from each toggle of the output waveform"] + BOTH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: BLANK_A) -> Self { + variant as _ + } +} +#[doc = "Field `BLANK` reader - Fault B Blanking Mode"] +pub struct BLANK_R(crate::FieldReader); +impl BLANK_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BLANK_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> BLANK_A { + match self.bits { + 0 => BLANK_A::START, + 1 => BLANK_A::RISE, + 2 => BLANK_A::FALL, + 3 => BLANK_A::BOTH, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `START`"] + #[inline(always)] + pub fn is_start(&self) -> bool { + **self == BLANK_A::START + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == BLANK_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == BLANK_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == BLANK_A::BOTH + } +} +impl core::ops::Deref for BLANK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BLANK` writer - Fault B Blanking Mode"] +pub struct BLANK_W<'a> { + w: &'a mut W, +} +impl<'a> BLANK_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: BLANK_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Blanking applied from start of the ramp"] + #[inline(always)] + pub fn start(self) -> &'a mut W { + self.variant(BLANK_A::START) + } + #[doc = "Blanking applied from rising edge of the output waveform"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(BLANK_A::RISE) + } + #[doc = "Blanking applied from falling edge of the output waveform"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(BLANK_A::FALL) + } + #[doc = "Blanking applied from each toggle of the output waveform"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(BLANK_A::BOTH) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 5)) | ((value as u32 & 0x03) << 5); + self.w + } +} +#[doc = "Field `RESTART` reader - Fault B Restart"] +pub struct RESTART_R(crate::FieldReader); +impl RESTART_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESTART_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESTART_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESTART` writer - Fault B Restart"] +pub struct RESTART_W<'a> { + w: &'a mut W, +} +impl<'a> RESTART_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Fault B Halt Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum HALT_A { + #[doc = "0: Halt action disabled"] + DISABLE = 0, + #[doc = "1: Hardware halt action"] + HW = 1, + #[doc = "2: Software halt action"] + SW = 2, + #[doc = "3: Non-recoverable fault"] + NR = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: HALT_A) -> Self { + variant as _ + } +} +#[doc = "Field `HALT` reader - Fault B Halt Mode"] +pub struct HALT_R(crate::FieldReader); +impl HALT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + HALT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> HALT_A { + match self.bits { + 0 => HALT_A::DISABLE, + 1 => HALT_A::HW, + 2 => HALT_A::SW, + 3 => HALT_A::NR, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == HALT_A::DISABLE + } + #[doc = "Checks if the value of the field is `HW`"] + #[inline(always)] + pub fn is_hw(&self) -> bool { + **self == HALT_A::HW + } + #[doc = "Checks if the value of the field is `SW`"] + #[inline(always)] + pub fn is_sw(&self) -> bool { + **self == HALT_A::SW + } + #[doc = "Checks if the value of the field is `NR`"] + #[inline(always)] + pub fn is_nr(&self) -> bool { + **self == HALT_A::NR + } +} +impl core::ops::Deref for HALT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HALT` writer - Fault B Halt Mode"] +pub struct HALT_W<'a> { + w: &'a mut W, +} +impl<'a> HALT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: HALT_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Halt action disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(HALT_A::DISABLE) + } + #[doc = "Hardware halt action"] + #[inline(always)] + pub fn hw(self) -> &'a mut W { + self.variant(HALT_A::HW) + } + #[doc = "Software halt action"] + #[inline(always)] + pub fn sw(self) -> &'a mut W { + self.variant(HALT_A::SW) + } + #[doc = "Non-recoverable fault"] + #[inline(always)] + pub fn nr(self) -> &'a mut W { + self.variant(HALT_A::NR) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 8)) | ((value as u32 & 0x03) << 8); + self.w + } +} +#[doc = "Fault B Capture Channel\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CHSEL_A { + #[doc = "0: Capture value stored in channel 0"] + CC0 = 0, + #[doc = "1: Capture value stored in channel 1"] + CC1 = 1, + #[doc = "2: Capture value stored in channel 2"] + CC2 = 2, + #[doc = "3: Capture value stored in channel 3"] + CC3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CHSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `CHSEL` reader - Fault B Capture Channel"] +pub struct CHSEL_R(crate::FieldReader); +impl CHSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CHSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CHSEL_A { + match self.bits { + 0 => CHSEL_A::CC0, + 1 => CHSEL_A::CC1, + 2 => CHSEL_A::CC2, + 3 => CHSEL_A::CC3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `CC0`"] + #[inline(always)] + pub fn is_cc0(&self) -> bool { + **self == CHSEL_A::CC0 + } + #[doc = "Checks if the value of the field is `CC1`"] + #[inline(always)] + pub fn is_cc1(&self) -> bool { + **self == CHSEL_A::CC1 + } + #[doc = "Checks if the value of the field is `CC2`"] + #[inline(always)] + pub fn is_cc2(&self) -> bool { + **self == CHSEL_A::CC2 + } + #[doc = "Checks if the value of the field is `CC3`"] + #[inline(always)] + pub fn is_cc3(&self) -> bool { + **self == CHSEL_A::CC3 + } +} +impl core::ops::Deref for CHSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHSEL` writer - Fault B Capture Channel"] +pub struct CHSEL_W<'a> { + w: &'a mut W, +} +impl<'a> CHSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CHSEL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Capture value stored in channel 0"] + #[inline(always)] + pub fn cc0(self) -> &'a mut W { + self.variant(CHSEL_A::CC0) + } + #[doc = "Capture value stored in channel 1"] + #[inline(always)] + pub fn cc1(self) -> &'a mut W { + self.variant(CHSEL_A::CC1) + } + #[doc = "Capture value stored in channel 2"] + #[inline(always)] + pub fn cc2(self) -> &'a mut W { + self.variant(CHSEL_A::CC2) + } + #[doc = "Capture value stored in channel 3"] + #[inline(always)] + pub fn cc3(self) -> &'a mut W { + self.variant(CHSEL_A::CC3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 10)) | ((value as u32 & 0x03) << 10); + self.w + } +} +#[doc = "Fault B Capture Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CAPTURE_A { + #[doc = "0: No capture"] + DISABLE = 0, + #[doc = "1: Capture on fault"] + CAPT = 1, + #[doc = "2: Minimum capture"] + CAPTMIN = 2, + #[doc = "3: Maximum capture"] + CAPTMAX = 3, + #[doc = "4: Minimum local detection"] + LOCMIN = 4, + #[doc = "5: Maximum local detection"] + LOCMAX = 5, + #[doc = "6: Minimum and maximum local detection"] + DERIV0 = 6, + #[doc = "7: Capture with ramp index as MSB value"] + CAPTMARK = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CAPTURE_A) -> Self { + variant as _ + } +} +#[doc = "Field `CAPTURE` reader - Fault B Capture Action"] +pub struct CAPTURE_R(crate::FieldReader); +impl CAPTURE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CAPTURE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CAPTURE_A { + match self.bits { + 0 => CAPTURE_A::DISABLE, + 1 => CAPTURE_A::CAPT, + 2 => CAPTURE_A::CAPTMIN, + 3 => CAPTURE_A::CAPTMAX, + 4 => CAPTURE_A::LOCMIN, + 5 => CAPTURE_A::LOCMAX, + 6 => CAPTURE_A::DERIV0, + 7 => CAPTURE_A::CAPTMARK, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == CAPTURE_A::DISABLE + } + #[doc = "Checks if the value of the field is `CAPT`"] + #[inline(always)] + pub fn is_capt(&self) -> bool { + **self == CAPTURE_A::CAPT + } + #[doc = "Checks if the value of the field is `CAPTMIN`"] + #[inline(always)] + pub fn is_captmin(&self) -> bool { + **self == CAPTURE_A::CAPTMIN + } + #[doc = "Checks if the value of the field is `CAPTMAX`"] + #[inline(always)] + pub fn is_captmax(&self) -> bool { + **self == CAPTURE_A::CAPTMAX + } + #[doc = "Checks if the value of the field is `LOCMIN`"] + #[inline(always)] + pub fn is_locmin(&self) -> bool { + **self == CAPTURE_A::LOCMIN + } + #[doc = "Checks if the value of the field is `LOCMAX`"] + #[inline(always)] + pub fn is_locmax(&self) -> bool { + **self == CAPTURE_A::LOCMAX + } + #[doc = "Checks if the value of the field is `DERIV0`"] + #[inline(always)] + pub fn is_deriv0(&self) -> bool { + **self == CAPTURE_A::DERIV0 + } + #[doc = "Checks if the value of the field is `CAPTMARK`"] + #[inline(always)] + pub fn is_captmark(&self) -> bool { + **self == CAPTURE_A::CAPTMARK + } +} +impl core::ops::Deref for CAPTURE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAPTURE` writer - Fault B Capture Action"] +pub struct CAPTURE_W<'a> { + w: &'a mut W, +} +impl<'a> CAPTURE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CAPTURE_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "No capture"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(CAPTURE_A::DISABLE) + } + #[doc = "Capture on fault"] + #[inline(always)] + pub fn capt(self) -> &'a mut W { + self.variant(CAPTURE_A::CAPT) + } + #[doc = "Minimum capture"] + #[inline(always)] + pub fn captmin(self) -> &'a mut W { + self.variant(CAPTURE_A::CAPTMIN) + } + #[doc = "Maximum capture"] + #[inline(always)] + pub fn captmax(self) -> &'a mut W { + self.variant(CAPTURE_A::CAPTMAX) + } + #[doc = "Minimum local detection"] + #[inline(always)] + pub fn locmin(self) -> &'a mut W { + self.variant(CAPTURE_A::LOCMIN) + } + #[doc = "Maximum local detection"] + #[inline(always)] + pub fn locmax(self) -> &'a mut W { + self.variant(CAPTURE_A::LOCMAX) + } + #[doc = "Minimum and maximum local detection"] + #[inline(always)] + pub fn deriv0(self) -> &'a mut W { + self.variant(CAPTURE_A::DERIV0) + } + #[doc = "Capture with ramp index as MSB value"] + #[inline(always)] + pub fn captmark(self) -> &'a mut W { + self.variant(CAPTURE_A::CAPTMARK) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 12)) | ((value as u32 & 0x07) << 12); + self.w + } +} +#[doc = "Field `BLANKPRESC` reader - Fault B Blanking Prescaler"] +pub struct BLANKPRESC_R(crate::FieldReader); +impl BLANKPRESC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BLANKPRESC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BLANKPRESC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BLANKPRESC` writer - Fault B Blanking Prescaler"] +pub struct BLANKPRESC_W<'a> { + w: &'a mut W, +} +impl<'a> BLANKPRESC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `BLANKVAL` reader - Fault B Blanking Time"] +pub struct BLANKVAL_R(crate::FieldReader); +impl BLANKVAL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BLANKVAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BLANKVAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BLANKVAL` writer - Fault B Blanking Time"] +pub struct BLANKVAL_W<'a> { + w: &'a mut W, +} +impl<'a> BLANKVAL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +#[doc = "Field `FILTERVAL` reader - Fault B Filter Value"] +pub struct FILTERVAL_R(crate::FieldReader); +impl FILTERVAL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FILTERVAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTERVAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTERVAL` writer - Fault B Filter Value"] +pub struct FILTERVAL_W<'a> { + w: &'a mut W, +} +impl<'a> FILTERVAL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Fault B Source"] + #[inline(always)] + pub fn src(&self) -> SRC_R { + SRC_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bit 3 - Fault B Keeper"] + #[inline(always)] + pub fn keep(&self) -> KEEP_R { + KEEP_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Fault B Qualification"] + #[inline(always)] + pub fn qual(&self) -> QUAL_R { + QUAL_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bits 5:6 - Fault B Blanking Mode"] + #[inline(always)] + pub fn blank(&self) -> BLANK_R { + BLANK_R::new(((self.bits >> 5) & 0x03) as u8) + } + #[doc = "Bit 7 - Fault B Restart"] + #[inline(always)] + pub fn restart(&self) -> RESTART_R { + RESTART_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:9 - Fault B Halt Mode"] + #[inline(always)] + pub fn halt(&self) -> HALT_R { + HALT_R::new(((self.bits >> 8) & 0x03) as u8) + } + #[doc = "Bits 10:11 - Fault B Capture Channel"] + #[inline(always)] + pub fn chsel(&self) -> CHSEL_R { + CHSEL_R::new(((self.bits >> 10) & 0x03) as u8) + } + #[doc = "Bits 12:14 - Fault B Capture Action"] + #[inline(always)] + pub fn capture(&self) -> CAPTURE_R { + CAPTURE_R::new(((self.bits >> 12) & 0x07) as u8) + } + #[doc = "Bit 15 - Fault B Blanking Prescaler"] + #[inline(always)] + pub fn blankpresc(&self) -> BLANKPRESC_R { + BLANKPRESC_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:23 - Fault B Blanking Time"] + #[inline(always)] + pub fn blankval(&self) -> BLANKVAL_R { + BLANKVAL_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:27 - Fault B Filter Value"] + #[inline(always)] + pub fn filterval(&self) -> FILTERVAL_R { + FILTERVAL_R::new(((self.bits >> 24) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Fault B Source"] + #[inline(always)] + pub fn src(&mut self) -> SRC_W { + SRC_W { w: self } + } + #[doc = "Bit 3 - Fault B Keeper"] + #[inline(always)] + pub fn keep(&mut self) -> KEEP_W { + KEEP_W { w: self } + } + #[doc = "Bit 4 - Fault B Qualification"] + #[inline(always)] + pub fn qual(&mut self) -> QUAL_W { + QUAL_W { w: self } + } + #[doc = "Bits 5:6 - Fault B Blanking Mode"] + #[inline(always)] + pub fn blank(&mut self) -> BLANK_W { + BLANK_W { w: self } + } + #[doc = "Bit 7 - Fault B Restart"] + #[inline(always)] + pub fn restart(&mut self) -> RESTART_W { + RESTART_W { w: self } + } + #[doc = "Bits 8:9 - Fault B Halt Mode"] + #[inline(always)] + pub fn halt(&mut self) -> HALT_W { + HALT_W { w: self } + } + #[doc = "Bits 10:11 - Fault B Capture Channel"] + #[inline(always)] + pub fn chsel(&mut self) -> CHSEL_W { + CHSEL_W { w: self } + } + #[doc = "Bits 12:14 - Fault B Capture Action"] + #[inline(always)] + pub fn capture(&mut self) -> CAPTURE_W { + CAPTURE_W { w: self } + } + #[doc = "Bit 15 - Fault B Blanking Prescaler"] + #[inline(always)] + pub fn blankpresc(&mut self) -> BLANKPRESC_W { + BLANKPRESC_W { w: self } + } + #[doc = "Bits 16:23 - Fault B Blanking Time"] + #[inline(always)] + pub fn blankval(&mut self) -> BLANKVAL_W { + BLANKVAL_W { w: self } + } + #[doc = "Bits 24:27 - Fault B Filter Value"] + #[inline(always)] + pub fn filterval(&mut self) -> FILTERVAL_W { + FILTERVAL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Recoverable Fault B Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fctrlb](index.html) module"] +pub struct FCTRLB_SPEC; +impl crate::RegisterSpec for FCTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [fctrlb::R](R) reader structure"] +impl crate::Readable for FCTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [fctrlb::W](W) writer structure"] +impl crate::Writable for FCTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets FCTRLB to value 0"] +impl crate::Resettable for FCTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/tcc0/intenclr.rs b/pac/atsamc21e/src/tcc0/intenclr.rs new file mode 100644 index 000000000000..a227a8405a3c --- /dev/null +++ b/pac/atsamc21e/src/tcc0/intenclr.rs @@ -0,0 +1,724 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `TRG` reader - Retrigger Interrupt Enable"] +pub struct TRG_R(crate::FieldReader); +impl TRG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRG` writer - Retrigger Interrupt Enable"] +pub struct TRG_W<'a> { + w: &'a mut W, +} +impl<'a> TRG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CNT` reader - Counter Interrupt Enable"] +pub struct CNT_R(crate::FieldReader); +impl CNT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CNT` writer - Counter Interrupt Enable"] +pub struct CNT_W<'a> { + w: &'a mut W, +} +impl<'a> CNT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `ERR` reader - Error Interrupt Enable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - Error Interrupt Enable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `UFS` reader - Non-Recoverable Update Fault Interrupt Enable"] +pub struct UFS_R(crate::FieldReader); +impl UFS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UFS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for UFS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `UFS` writer - Non-Recoverable Update Fault Interrupt Enable"] +pub struct UFS_W<'a> { + w: &'a mut W, +} +impl<'a> UFS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `DFS` reader - Non-Recoverable Debug Fault Interrupt Enable"] +pub struct DFS_R(crate::FieldReader); +impl DFS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFS` writer - Non-Recoverable Debug Fault Interrupt Enable"] +pub struct DFS_W<'a> { + w: &'a mut W, +} +impl<'a> DFS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `FAULTA` reader - Recoverable Fault A Interrupt Enable"] +pub struct FAULTA_R(crate::FieldReader); +impl FAULTA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTA` writer - Recoverable Fault A Interrupt Enable"] +pub struct FAULTA_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `FAULTB` reader - Recoverable Fault B Interrupt Enable"] +pub struct FAULTB_R(crate::FieldReader); +impl FAULTB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTB` writer - Recoverable Fault B Interrupt Enable"] +pub struct FAULTB_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `FAULT0` reader - Non-Recoverable Fault 0 Interrupt Enable"] +pub struct FAULT0_R(crate::FieldReader); +impl FAULT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT0` writer - Non-Recoverable Fault 0 Interrupt Enable"] +pub struct FAULT0_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `FAULT1` reader - Non-Recoverable Fault 1 Interrupt Enable"] +pub struct FAULT1_R(crate::FieldReader); +impl FAULT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT1` writer - Non-Recoverable Fault 1 Interrupt Enable"] +pub struct FAULT1_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `MC0` reader - Match or Capture Channel 0 Interrupt Enable"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - Match or Capture Channel 0 Interrupt Enable"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `MC1` reader - Match or Capture Channel 1 Interrupt Enable"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - Match or Capture Channel 1 Interrupt Enable"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `MC2` reader - Match or Capture Channel 2 Interrupt Enable"] +pub struct MC2_R(crate::FieldReader); +impl MC2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC2` writer - Match or Capture Channel 2 Interrupt Enable"] +pub struct MC2_W<'a> { + w: &'a mut W, +} +impl<'a> MC2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `MC3` reader - Match or Capture Channel 3 Interrupt Enable"] +pub struct MC3_R(crate::FieldReader); +impl MC3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC3` writer - Match or Capture Channel 3 Interrupt Enable"] +pub struct MC3_W<'a> { + w: &'a mut W, +} +impl<'a> MC3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +impl R { + #[doc = "Bit 0 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Retrigger Interrupt Enable"] + #[inline(always)] + pub fn trg(&self) -> TRG_R { + TRG_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Counter Interrupt Enable"] + #[inline(always)] + pub fn cnt(&self) -> CNT_R { + CNT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Error Interrupt Enable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 10 - Non-Recoverable Update Fault Interrupt Enable"] + #[inline(always)] + pub fn ufs(&self) -> UFS_R { + UFS_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Non-Recoverable Debug Fault Interrupt Enable"] + #[inline(always)] + pub fn dfs(&self) -> DFS_R { + DFS_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Recoverable Fault A Interrupt Enable"] + #[inline(always)] + pub fn faulta(&self) -> FAULTA_R { + FAULTA_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Recoverable Fault B Interrupt Enable"] + #[inline(always)] + pub fn faultb(&self) -> FAULTB_R { + FAULTB_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Non-Recoverable Fault 0 Interrupt Enable"] + #[inline(always)] + pub fn fault0(&self) -> FAULT0_R { + FAULT0_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Non-Recoverable Fault 1 Interrupt Enable"] + #[inline(always)] + pub fn fault1(&self) -> FAULT1_R { + FAULT1_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Match or Capture Channel 0 Interrupt Enable"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Match or Capture Channel 1 Interrupt Enable"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Match or Capture Channel 2 Interrupt Enable"] + #[inline(always)] + pub fn mc2(&self) -> MC2_R { + MC2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Match or Capture Channel 3 Interrupt Enable"] + #[inline(always)] + pub fn mc3(&self) -> MC3_R { + MC3_R::new(((self.bits >> 19) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - Retrigger Interrupt Enable"] + #[inline(always)] + pub fn trg(&mut self) -> TRG_W { + TRG_W { w: self } + } + #[doc = "Bit 2 - Counter Interrupt Enable"] + #[inline(always)] + pub fn cnt(&mut self) -> CNT_W { + CNT_W { w: self } + } + #[doc = "Bit 3 - Error Interrupt Enable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 10 - Non-Recoverable Update Fault Interrupt Enable"] + #[inline(always)] + pub fn ufs(&mut self) -> UFS_W { + UFS_W { w: self } + } + #[doc = "Bit 11 - Non-Recoverable Debug Fault Interrupt Enable"] + #[inline(always)] + pub fn dfs(&mut self) -> DFS_W { + DFS_W { w: self } + } + #[doc = "Bit 12 - Recoverable Fault A Interrupt Enable"] + #[inline(always)] + pub fn faulta(&mut self) -> FAULTA_W { + FAULTA_W { w: self } + } + #[doc = "Bit 13 - Recoverable Fault B Interrupt Enable"] + #[inline(always)] + pub fn faultb(&mut self) -> FAULTB_W { + FAULTB_W { w: self } + } + #[doc = "Bit 14 - Non-Recoverable Fault 0 Interrupt Enable"] + #[inline(always)] + pub fn fault0(&mut self) -> FAULT0_W { + FAULT0_W { w: self } + } + #[doc = "Bit 15 - Non-Recoverable Fault 1 Interrupt Enable"] + #[inline(always)] + pub fn fault1(&mut self) -> FAULT1_W { + FAULT1_W { w: self } + } + #[doc = "Bit 16 - Match or Capture Channel 0 Interrupt Enable"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 17 - Match or Capture Channel 1 Interrupt Enable"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Bit 18 - Match or Capture Channel 2 Interrupt Enable"] + #[inline(always)] + pub fn mc2(&mut self) -> MC2_W { + MC2_W { w: self } + } + #[doc = "Bit 19 - Match or Capture Channel 3 Interrupt Enable"] + #[inline(always)] + pub fn mc3(&mut self) -> MC3_W { + MC3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/tcc0/intenset.rs b/pac/atsamc21e/src/tcc0/intenset.rs new file mode 100644 index 000000000000..0125a220bd02 --- /dev/null +++ b/pac/atsamc21e/src/tcc0/intenset.rs @@ -0,0 +1,724 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `TRG` reader - Retrigger Interrupt Enable"] +pub struct TRG_R(crate::FieldReader); +impl TRG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRG` writer - Retrigger Interrupt Enable"] +pub struct TRG_W<'a> { + w: &'a mut W, +} +impl<'a> TRG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CNT` reader - Counter Interrupt Enable"] +pub struct CNT_R(crate::FieldReader); +impl CNT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CNT` writer - Counter Interrupt Enable"] +pub struct CNT_W<'a> { + w: &'a mut W, +} +impl<'a> CNT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `ERR` reader - Error Interrupt Enable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - Error Interrupt Enable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `UFS` reader - Non-Recoverable Update Fault Interrupt Enable"] +pub struct UFS_R(crate::FieldReader); +impl UFS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UFS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for UFS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `UFS` writer - Non-Recoverable Update Fault Interrupt Enable"] +pub struct UFS_W<'a> { + w: &'a mut W, +} +impl<'a> UFS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `DFS` reader - Non-Recoverable Debug Fault Interrupt Enable"] +pub struct DFS_R(crate::FieldReader); +impl DFS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFS` writer - Non-Recoverable Debug Fault Interrupt Enable"] +pub struct DFS_W<'a> { + w: &'a mut W, +} +impl<'a> DFS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `FAULTA` reader - Recoverable Fault A Interrupt Enable"] +pub struct FAULTA_R(crate::FieldReader); +impl FAULTA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTA` writer - Recoverable Fault A Interrupt Enable"] +pub struct FAULTA_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `FAULTB` reader - Recoverable Fault B Interrupt Enable"] +pub struct FAULTB_R(crate::FieldReader); +impl FAULTB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTB` writer - Recoverable Fault B Interrupt Enable"] +pub struct FAULTB_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `FAULT0` reader - Non-Recoverable Fault 0 Interrupt Enable"] +pub struct FAULT0_R(crate::FieldReader); +impl FAULT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT0` writer - Non-Recoverable Fault 0 Interrupt Enable"] +pub struct FAULT0_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `FAULT1` reader - Non-Recoverable Fault 1 Interrupt Enable"] +pub struct FAULT1_R(crate::FieldReader); +impl FAULT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT1` writer - Non-Recoverable Fault 1 Interrupt Enable"] +pub struct FAULT1_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `MC0` reader - Match or Capture Channel 0 Interrupt Enable"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - Match or Capture Channel 0 Interrupt Enable"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `MC1` reader - Match or Capture Channel 1 Interrupt Enable"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - Match or Capture Channel 1 Interrupt Enable"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `MC2` reader - Match or Capture Channel 2 Interrupt Enable"] +pub struct MC2_R(crate::FieldReader); +impl MC2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC2` writer - Match or Capture Channel 2 Interrupt Enable"] +pub struct MC2_W<'a> { + w: &'a mut W, +} +impl<'a> MC2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `MC3` reader - Match or Capture Channel 3 Interrupt Enable"] +pub struct MC3_R(crate::FieldReader); +impl MC3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC3` writer - Match or Capture Channel 3 Interrupt Enable"] +pub struct MC3_W<'a> { + w: &'a mut W, +} +impl<'a> MC3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +impl R { + #[doc = "Bit 0 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Retrigger Interrupt Enable"] + #[inline(always)] + pub fn trg(&self) -> TRG_R { + TRG_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Counter Interrupt Enable"] + #[inline(always)] + pub fn cnt(&self) -> CNT_R { + CNT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Error Interrupt Enable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 10 - Non-Recoverable Update Fault Interrupt Enable"] + #[inline(always)] + pub fn ufs(&self) -> UFS_R { + UFS_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Non-Recoverable Debug Fault Interrupt Enable"] + #[inline(always)] + pub fn dfs(&self) -> DFS_R { + DFS_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Recoverable Fault A Interrupt Enable"] + #[inline(always)] + pub fn faulta(&self) -> FAULTA_R { + FAULTA_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Recoverable Fault B Interrupt Enable"] + #[inline(always)] + pub fn faultb(&self) -> FAULTB_R { + FAULTB_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Non-Recoverable Fault 0 Interrupt Enable"] + #[inline(always)] + pub fn fault0(&self) -> FAULT0_R { + FAULT0_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Non-Recoverable Fault 1 Interrupt Enable"] + #[inline(always)] + pub fn fault1(&self) -> FAULT1_R { + FAULT1_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Match or Capture Channel 0 Interrupt Enable"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Match or Capture Channel 1 Interrupt Enable"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Match or Capture Channel 2 Interrupt Enable"] + #[inline(always)] + pub fn mc2(&self) -> MC2_R { + MC2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Match or Capture Channel 3 Interrupt Enable"] + #[inline(always)] + pub fn mc3(&self) -> MC3_R { + MC3_R::new(((self.bits >> 19) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - Retrigger Interrupt Enable"] + #[inline(always)] + pub fn trg(&mut self) -> TRG_W { + TRG_W { w: self } + } + #[doc = "Bit 2 - Counter Interrupt Enable"] + #[inline(always)] + pub fn cnt(&mut self) -> CNT_W { + CNT_W { w: self } + } + #[doc = "Bit 3 - Error Interrupt Enable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 10 - Non-Recoverable Update Fault Interrupt Enable"] + #[inline(always)] + pub fn ufs(&mut self) -> UFS_W { + UFS_W { w: self } + } + #[doc = "Bit 11 - Non-Recoverable Debug Fault Interrupt Enable"] + #[inline(always)] + pub fn dfs(&mut self) -> DFS_W { + DFS_W { w: self } + } + #[doc = "Bit 12 - Recoverable Fault A Interrupt Enable"] + #[inline(always)] + pub fn faulta(&mut self) -> FAULTA_W { + FAULTA_W { w: self } + } + #[doc = "Bit 13 - Recoverable Fault B Interrupt Enable"] + #[inline(always)] + pub fn faultb(&mut self) -> FAULTB_W { + FAULTB_W { w: self } + } + #[doc = "Bit 14 - Non-Recoverable Fault 0 Interrupt Enable"] + #[inline(always)] + pub fn fault0(&mut self) -> FAULT0_W { + FAULT0_W { w: self } + } + #[doc = "Bit 15 - Non-Recoverable Fault 1 Interrupt Enable"] + #[inline(always)] + pub fn fault1(&mut self) -> FAULT1_W { + FAULT1_W { w: self } + } + #[doc = "Bit 16 - Match or Capture Channel 0 Interrupt Enable"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 17 - Match or Capture Channel 1 Interrupt Enable"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Bit 18 - Match or Capture Channel 2 Interrupt Enable"] + #[inline(always)] + pub fn mc2(&mut self) -> MC2_W { + MC2_W { w: self } + } + #[doc = "Bit 19 - Match or Capture Channel 3 Interrupt Enable"] + #[inline(always)] + pub fn mc3(&mut self) -> MC3_W { + MC3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/tcc0/intflag.rs b/pac/atsamc21e/src/tcc0/intflag.rs new file mode 100644 index 000000000000..b2d5088f4087 --- /dev/null +++ b/pac/atsamc21e/src/tcc0/intflag.rs @@ -0,0 +1,724 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - Overflow"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `TRG` reader - Retrigger"] +pub struct TRG_R(crate::FieldReader); +impl TRG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRG` writer - Retrigger"] +pub struct TRG_W<'a> { + w: &'a mut W, +} +impl<'a> TRG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CNT` reader - Counter"] +pub struct CNT_R(crate::FieldReader); +impl CNT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CNT` writer - Counter"] +pub struct CNT_W<'a> { + w: &'a mut W, +} +impl<'a> CNT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `ERR` reader - Error"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - Error"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `UFS` reader - Non-Recoverable Update Fault"] +pub struct UFS_R(crate::FieldReader); +impl UFS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UFS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for UFS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `UFS` writer - Non-Recoverable Update Fault"] +pub struct UFS_W<'a> { + w: &'a mut W, +} +impl<'a> UFS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `DFS` reader - Non-Recoverable Debug Fault"] +pub struct DFS_R(crate::FieldReader); +impl DFS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFS` writer - Non-Recoverable Debug Fault"] +pub struct DFS_W<'a> { + w: &'a mut W, +} +impl<'a> DFS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `FAULTA` reader - Recoverable Fault A"] +pub struct FAULTA_R(crate::FieldReader); +impl FAULTA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTA` writer - Recoverable Fault A"] +pub struct FAULTA_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `FAULTB` reader - Recoverable Fault B"] +pub struct FAULTB_R(crate::FieldReader); +impl FAULTB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTB` writer - Recoverable Fault B"] +pub struct FAULTB_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `FAULT0` reader - Non-Recoverable Fault 0"] +pub struct FAULT0_R(crate::FieldReader); +impl FAULT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT0` writer - Non-Recoverable Fault 0"] +pub struct FAULT0_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `FAULT1` reader - Non-Recoverable Fault 1"] +pub struct FAULT1_R(crate::FieldReader); +impl FAULT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT1` writer - Non-Recoverable Fault 1"] +pub struct FAULT1_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `MC0` reader - Match or Capture 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - Match or Capture 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `MC1` reader - Match or Capture 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - Match or Capture 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `MC2` reader - Match or Capture 2"] +pub struct MC2_R(crate::FieldReader); +impl MC2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC2` writer - Match or Capture 2"] +pub struct MC2_W<'a> { + w: &'a mut W, +} +impl<'a> MC2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `MC3` reader - Match or Capture 3"] +pub struct MC3_R(crate::FieldReader); +impl MC3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC3` writer - Match or Capture 3"] +pub struct MC3_W<'a> { + w: &'a mut W, +} +impl<'a> MC3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +impl R { + #[doc = "Bit 0 - Overflow"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Retrigger"] + #[inline(always)] + pub fn trg(&self) -> TRG_R { + TRG_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Counter"] + #[inline(always)] + pub fn cnt(&self) -> CNT_R { + CNT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Error"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 10 - Non-Recoverable Update Fault"] + #[inline(always)] + pub fn ufs(&self) -> UFS_R { + UFS_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Non-Recoverable Debug Fault"] + #[inline(always)] + pub fn dfs(&self) -> DFS_R { + DFS_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Recoverable Fault A"] + #[inline(always)] + pub fn faulta(&self) -> FAULTA_R { + FAULTA_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Recoverable Fault B"] + #[inline(always)] + pub fn faultb(&self) -> FAULTB_R { + FAULTB_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Non-Recoverable Fault 0"] + #[inline(always)] + pub fn fault0(&self) -> FAULT0_R { + FAULT0_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Non-Recoverable Fault 1"] + #[inline(always)] + pub fn fault1(&self) -> FAULT1_R { + FAULT1_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Match or Capture 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Match or Capture 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Match or Capture 2"] + #[inline(always)] + pub fn mc2(&self) -> MC2_R { + MC2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Match or Capture 3"] + #[inline(always)] + pub fn mc3(&self) -> MC3_R { + MC3_R::new(((self.bits >> 19) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Overflow"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - Retrigger"] + #[inline(always)] + pub fn trg(&mut self) -> TRG_W { + TRG_W { w: self } + } + #[doc = "Bit 2 - Counter"] + #[inline(always)] + pub fn cnt(&mut self) -> CNT_W { + CNT_W { w: self } + } + #[doc = "Bit 3 - Error"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 10 - Non-Recoverable Update Fault"] + #[inline(always)] + pub fn ufs(&mut self) -> UFS_W { + UFS_W { w: self } + } + #[doc = "Bit 11 - Non-Recoverable Debug Fault"] + #[inline(always)] + pub fn dfs(&mut self) -> DFS_W { + DFS_W { w: self } + } + #[doc = "Bit 12 - Recoverable Fault A"] + #[inline(always)] + pub fn faulta(&mut self) -> FAULTA_W { + FAULTA_W { w: self } + } + #[doc = "Bit 13 - Recoverable Fault B"] + #[inline(always)] + pub fn faultb(&mut self) -> FAULTB_W { + FAULTB_W { w: self } + } + #[doc = "Bit 14 - Non-Recoverable Fault 0"] + #[inline(always)] + pub fn fault0(&mut self) -> FAULT0_W { + FAULT0_W { w: self } + } + #[doc = "Bit 15 - Non-Recoverable Fault 1"] + #[inline(always)] + pub fn fault1(&mut self) -> FAULT1_W { + FAULT1_W { w: self } + } + #[doc = "Bit 16 - Match or Capture 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 17 - Match or Capture 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Bit 18 - Match or Capture 2"] + #[inline(always)] + pub fn mc2(&mut self) -> MC2_W { + MC2_W { w: self } + } + #[doc = "Bit 19 - Match or Capture 3"] + #[inline(always)] + pub fn mc3(&mut self) -> MC3_W { + MC3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/tcc0/patt.rs b/pac/atsamc21e/src/tcc0/patt.rs new file mode 100644 index 000000000000..ea458642b182 --- /dev/null +++ b/pac/atsamc21e/src/tcc0/patt.rs @@ -0,0 +1,818 @@ +#[doc = "Register `PATT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PATT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PGE0` reader - Pattern Generator 0 Output Enable"] +pub struct PGE0_R(crate::FieldReader); +impl PGE0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGE0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGE0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGE0` writer - Pattern Generator 0 Output Enable"] +pub struct PGE0_W<'a> { + w: &'a mut W, +} +impl<'a> PGE0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PGE1` reader - Pattern Generator 1 Output Enable"] +pub struct PGE1_R(crate::FieldReader); +impl PGE1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGE1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGE1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGE1` writer - Pattern Generator 1 Output Enable"] +pub struct PGE1_W<'a> { + w: &'a mut W, +} +impl<'a> PGE1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PGE2` reader - Pattern Generator 2 Output Enable"] +pub struct PGE2_R(crate::FieldReader); +impl PGE2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGE2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGE2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGE2` writer - Pattern Generator 2 Output Enable"] +pub struct PGE2_W<'a> { + w: &'a mut W, +} +impl<'a> PGE2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PGE3` reader - Pattern Generator 3 Output Enable"] +pub struct PGE3_R(crate::FieldReader); +impl PGE3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGE3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGE3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGE3` writer - Pattern Generator 3 Output Enable"] +pub struct PGE3_W<'a> { + w: &'a mut W, +} +impl<'a> PGE3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PGE4` reader - Pattern Generator 4 Output Enable"] +pub struct PGE4_R(crate::FieldReader); +impl PGE4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGE4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGE4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGE4` writer - Pattern Generator 4 Output Enable"] +pub struct PGE4_W<'a> { + w: &'a mut W, +} +impl<'a> PGE4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PGE5` reader - Pattern Generator 5 Output Enable"] +pub struct PGE5_R(crate::FieldReader); +impl PGE5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGE5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGE5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGE5` writer - Pattern Generator 5 Output Enable"] +pub struct PGE5_W<'a> { + w: &'a mut W, +} +impl<'a> PGE5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PGE6` reader - Pattern Generator 6 Output Enable"] +pub struct PGE6_R(crate::FieldReader); +impl PGE6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGE6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGE6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGE6` writer - Pattern Generator 6 Output Enable"] +pub struct PGE6_W<'a> { + w: &'a mut W, +} +impl<'a> PGE6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PGE7` reader - Pattern Generator 7 Output Enable"] +pub struct PGE7_R(crate::FieldReader); +impl PGE7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGE7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGE7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGE7` writer - Pattern Generator 7 Output Enable"] +pub struct PGE7_W<'a> { + w: &'a mut W, +} +impl<'a> PGE7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `PGV0` reader - Pattern Generator 0 Output Value"] +pub struct PGV0_R(crate::FieldReader); +impl PGV0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGV0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGV0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGV0` writer - Pattern Generator 0 Output Value"] +pub struct PGV0_W<'a> { + w: &'a mut W, +} +impl<'a> PGV0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `PGV1` reader - Pattern Generator 1 Output Value"] +pub struct PGV1_R(crate::FieldReader); +impl PGV1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGV1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGV1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGV1` writer - Pattern Generator 1 Output Value"] +pub struct PGV1_W<'a> { + w: &'a mut W, +} +impl<'a> PGV1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `PGV2` reader - Pattern Generator 2 Output Value"] +pub struct PGV2_R(crate::FieldReader); +impl PGV2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGV2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGV2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGV2` writer - Pattern Generator 2 Output Value"] +pub struct PGV2_W<'a> { + w: &'a mut W, +} +impl<'a> PGV2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u16 & 0x01) << 10); + self.w + } +} +#[doc = "Field `PGV3` reader - Pattern Generator 3 Output Value"] +pub struct PGV3_R(crate::FieldReader); +impl PGV3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGV3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGV3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGV3` writer - Pattern Generator 3 Output Value"] +pub struct PGV3_W<'a> { + w: &'a mut W, +} +impl<'a> PGV3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u16 & 0x01) << 11); + self.w + } +} +#[doc = "Field `PGV4` reader - Pattern Generator 4 Output Value"] +pub struct PGV4_R(crate::FieldReader); +impl PGV4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGV4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGV4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGV4` writer - Pattern Generator 4 Output Value"] +pub struct PGV4_W<'a> { + w: &'a mut W, +} +impl<'a> PGV4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u16 & 0x01) << 12); + self.w + } +} +#[doc = "Field `PGV5` reader - Pattern Generator 5 Output Value"] +pub struct PGV5_R(crate::FieldReader); +impl PGV5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGV5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGV5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGV5` writer - Pattern Generator 5 Output Value"] +pub struct PGV5_W<'a> { + w: &'a mut W, +} +impl<'a> PGV5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u16 & 0x01) << 13); + self.w + } +} +#[doc = "Field `PGV6` reader - Pattern Generator 6 Output Value"] +pub struct PGV6_R(crate::FieldReader); +impl PGV6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGV6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGV6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGV6` writer - Pattern Generator 6 Output Value"] +pub struct PGV6_W<'a> { + w: &'a mut W, +} +impl<'a> PGV6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u16 & 0x01) << 14); + self.w + } +} +#[doc = "Field `PGV7` reader - Pattern Generator 7 Output Value"] +pub struct PGV7_R(crate::FieldReader); +impl PGV7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGV7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGV7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGV7` writer - Pattern Generator 7 Output Value"] +pub struct PGV7_W<'a> { + w: &'a mut W, +} +impl<'a> PGV7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Pattern Generator 0 Output Enable"] + #[inline(always)] + pub fn pge0(&self) -> PGE0_R { + PGE0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Pattern Generator 1 Output Enable"] + #[inline(always)] + pub fn pge1(&self) -> PGE1_R { + PGE1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Pattern Generator 2 Output Enable"] + #[inline(always)] + pub fn pge2(&self) -> PGE2_R { + PGE2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Pattern Generator 3 Output Enable"] + #[inline(always)] + pub fn pge3(&self) -> PGE3_R { + PGE3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Pattern Generator 4 Output Enable"] + #[inline(always)] + pub fn pge4(&self) -> PGE4_R { + PGE4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Pattern Generator 5 Output Enable"] + #[inline(always)] + pub fn pge5(&self) -> PGE5_R { + PGE5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Pattern Generator 6 Output Enable"] + #[inline(always)] + pub fn pge6(&self) -> PGE6_R { + PGE6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Pattern Generator 7 Output Enable"] + #[inline(always)] + pub fn pge7(&self) -> PGE7_R { + PGE7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Pattern Generator 0 Output Value"] + #[inline(always)] + pub fn pgv0(&self) -> PGV0_R { + PGV0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Pattern Generator 1 Output Value"] + #[inline(always)] + pub fn pgv1(&self) -> PGV1_R { + PGV1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Pattern Generator 2 Output Value"] + #[inline(always)] + pub fn pgv2(&self) -> PGV2_R { + PGV2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Pattern Generator 3 Output Value"] + #[inline(always)] + pub fn pgv3(&self) -> PGV3_R { + PGV3_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Pattern Generator 4 Output Value"] + #[inline(always)] + pub fn pgv4(&self) -> PGV4_R { + PGV4_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Pattern Generator 5 Output Value"] + #[inline(always)] + pub fn pgv5(&self) -> PGV5_R { + PGV5_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Pattern Generator 6 Output Value"] + #[inline(always)] + pub fn pgv6(&self) -> PGV6_R { + PGV6_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Pattern Generator 7 Output Value"] + #[inline(always)] + pub fn pgv7(&self) -> PGV7_R { + PGV7_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pattern Generator 0 Output Enable"] + #[inline(always)] + pub fn pge0(&mut self) -> PGE0_W { + PGE0_W { w: self } + } + #[doc = "Bit 1 - Pattern Generator 1 Output Enable"] + #[inline(always)] + pub fn pge1(&mut self) -> PGE1_W { + PGE1_W { w: self } + } + #[doc = "Bit 2 - Pattern Generator 2 Output Enable"] + #[inline(always)] + pub fn pge2(&mut self) -> PGE2_W { + PGE2_W { w: self } + } + #[doc = "Bit 3 - Pattern Generator 3 Output Enable"] + #[inline(always)] + pub fn pge3(&mut self) -> PGE3_W { + PGE3_W { w: self } + } + #[doc = "Bit 4 - Pattern Generator 4 Output Enable"] + #[inline(always)] + pub fn pge4(&mut self) -> PGE4_W { + PGE4_W { w: self } + } + #[doc = "Bit 5 - Pattern Generator 5 Output Enable"] + #[inline(always)] + pub fn pge5(&mut self) -> PGE5_W { + PGE5_W { w: self } + } + #[doc = "Bit 6 - Pattern Generator 6 Output Enable"] + #[inline(always)] + pub fn pge6(&mut self) -> PGE6_W { + PGE6_W { w: self } + } + #[doc = "Bit 7 - Pattern Generator 7 Output Enable"] + #[inline(always)] + pub fn pge7(&mut self) -> PGE7_W { + PGE7_W { w: self } + } + #[doc = "Bit 8 - Pattern Generator 0 Output Value"] + #[inline(always)] + pub fn pgv0(&mut self) -> PGV0_W { + PGV0_W { w: self } + } + #[doc = "Bit 9 - Pattern Generator 1 Output Value"] + #[inline(always)] + pub fn pgv1(&mut self) -> PGV1_W { + PGV1_W { w: self } + } + #[doc = "Bit 10 - Pattern Generator 2 Output Value"] + #[inline(always)] + pub fn pgv2(&mut self) -> PGV2_W { + PGV2_W { w: self } + } + #[doc = "Bit 11 - Pattern Generator 3 Output Value"] + #[inline(always)] + pub fn pgv3(&mut self) -> PGV3_W { + PGV3_W { w: self } + } + #[doc = "Bit 12 - Pattern Generator 4 Output Value"] + #[inline(always)] + pub fn pgv4(&mut self) -> PGV4_W { + PGV4_W { w: self } + } + #[doc = "Bit 13 - Pattern Generator 5 Output Value"] + #[inline(always)] + pub fn pgv5(&mut self) -> PGV5_W { + PGV5_W { w: self } + } + #[doc = "Bit 14 - Pattern Generator 6 Output Value"] + #[inline(always)] + pub fn pgv6(&mut self) -> PGV6_W { + PGV6_W { w: self } + } + #[doc = "Bit 15 - Pattern Generator 7 Output Value"] + #[inline(always)] + pub fn pgv7(&mut self) -> PGV7_W { + PGV7_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Pattern\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [patt](index.html) module"] +pub struct PATT_SPEC; +impl crate::RegisterSpec for PATT_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [patt::R](R) reader structure"] +impl crate::Readable for PATT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [patt::W](W) writer structure"] +impl crate::Writable for PATT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PATT to value 0"] +impl crate::Resettable for PATT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/tcc0/pattbuf.rs b/pac/atsamc21e/src/tcc0/pattbuf.rs new file mode 100644 index 000000000000..c9375e27645c --- /dev/null +++ b/pac/atsamc21e/src/tcc0/pattbuf.rs @@ -0,0 +1,818 @@ +#[doc = "Register `PATTBUF` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PATTBUF` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PGEB0` reader - Pattern Generator 0 Output Enable Buffer"] +pub struct PGEB0_R(crate::FieldReader); +impl PGEB0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGEB0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGEB0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGEB0` writer - Pattern Generator 0 Output Enable Buffer"] +pub struct PGEB0_W<'a> { + w: &'a mut W, +} +impl<'a> PGEB0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PGEB1` reader - Pattern Generator 1 Output Enable Buffer"] +pub struct PGEB1_R(crate::FieldReader); +impl PGEB1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGEB1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGEB1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGEB1` writer - Pattern Generator 1 Output Enable Buffer"] +pub struct PGEB1_W<'a> { + w: &'a mut W, +} +impl<'a> PGEB1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PGEB2` reader - Pattern Generator 2 Output Enable Buffer"] +pub struct PGEB2_R(crate::FieldReader); +impl PGEB2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGEB2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGEB2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGEB2` writer - Pattern Generator 2 Output Enable Buffer"] +pub struct PGEB2_W<'a> { + w: &'a mut W, +} +impl<'a> PGEB2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PGEB3` reader - Pattern Generator 3 Output Enable Buffer"] +pub struct PGEB3_R(crate::FieldReader); +impl PGEB3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGEB3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGEB3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGEB3` writer - Pattern Generator 3 Output Enable Buffer"] +pub struct PGEB3_W<'a> { + w: &'a mut W, +} +impl<'a> PGEB3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PGEB4` reader - Pattern Generator 4 Output Enable Buffer"] +pub struct PGEB4_R(crate::FieldReader); +impl PGEB4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGEB4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGEB4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGEB4` writer - Pattern Generator 4 Output Enable Buffer"] +pub struct PGEB4_W<'a> { + w: &'a mut W, +} +impl<'a> PGEB4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PGEB5` reader - Pattern Generator 5 Output Enable Buffer"] +pub struct PGEB5_R(crate::FieldReader); +impl PGEB5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGEB5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGEB5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGEB5` writer - Pattern Generator 5 Output Enable Buffer"] +pub struct PGEB5_W<'a> { + w: &'a mut W, +} +impl<'a> PGEB5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PGEB6` reader - Pattern Generator 6 Output Enable Buffer"] +pub struct PGEB6_R(crate::FieldReader); +impl PGEB6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGEB6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGEB6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGEB6` writer - Pattern Generator 6 Output Enable Buffer"] +pub struct PGEB6_W<'a> { + w: &'a mut W, +} +impl<'a> PGEB6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PGEB7` reader - Pattern Generator 7 Output Enable Buffer"] +pub struct PGEB7_R(crate::FieldReader); +impl PGEB7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGEB7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGEB7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGEB7` writer - Pattern Generator 7 Output Enable Buffer"] +pub struct PGEB7_W<'a> { + w: &'a mut W, +} +impl<'a> PGEB7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `PGVB0` reader - Pattern Generator 0 Output Enable"] +pub struct PGVB0_R(crate::FieldReader); +impl PGVB0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGVB0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGVB0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGVB0` writer - Pattern Generator 0 Output Enable"] +pub struct PGVB0_W<'a> { + w: &'a mut W, +} +impl<'a> PGVB0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `PGVB1` reader - Pattern Generator 1 Output Enable"] +pub struct PGVB1_R(crate::FieldReader); +impl PGVB1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGVB1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGVB1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGVB1` writer - Pattern Generator 1 Output Enable"] +pub struct PGVB1_W<'a> { + w: &'a mut W, +} +impl<'a> PGVB1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `PGVB2` reader - Pattern Generator 2 Output Enable"] +pub struct PGVB2_R(crate::FieldReader); +impl PGVB2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGVB2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGVB2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGVB2` writer - Pattern Generator 2 Output Enable"] +pub struct PGVB2_W<'a> { + w: &'a mut W, +} +impl<'a> PGVB2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u16 & 0x01) << 10); + self.w + } +} +#[doc = "Field `PGVB3` reader - Pattern Generator 3 Output Enable"] +pub struct PGVB3_R(crate::FieldReader); +impl PGVB3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGVB3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGVB3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGVB3` writer - Pattern Generator 3 Output Enable"] +pub struct PGVB3_W<'a> { + w: &'a mut W, +} +impl<'a> PGVB3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u16 & 0x01) << 11); + self.w + } +} +#[doc = "Field `PGVB4` reader - Pattern Generator 4 Output Enable"] +pub struct PGVB4_R(crate::FieldReader); +impl PGVB4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGVB4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGVB4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGVB4` writer - Pattern Generator 4 Output Enable"] +pub struct PGVB4_W<'a> { + w: &'a mut W, +} +impl<'a> PGVB4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u16 & 0x01) << 12); + self.w + } +} +#[doc = "Field `PGVB5` reader - Pattern Generator 5 Output Enable"] +pub struct PGVB5_R(crate::FieldReader); +impl PGVB5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGVB5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGVB5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGVB5` writer - Pattern Generator 5 Output Enable"] +pub struct PGVB5_W<'a> { + w: &'a mut W, +} +impl<'a> PGVB5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u16 & 0x01) << 13); + self.w + } +} +#[doc = "Field `PGVB6` reader - Pattern Generator 6 Output Enable"] +pub struct PGVB6_R(crate::FieldReader); +impl PGVB6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGVB6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGVB6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGVB6` writer - Pattern Generator 6 Output Enable"] +pub struct PGVB6_W<'a> { + w: &'a mut W, +} +impl<'a> PGVB6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u16 & 0x01) << 14); + self.w + } +} +#[doc = "Field `PGVB7` reader - Pattern Generator 7 Output Enable"] +pub struct PGVB7_R(crate::FieldReader); +impl PGVB7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGVB7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGVB7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGVB7` writer - Pattern Generator 7 Output Enable"] +pub struct PGVB7_W<'a> { + w: &'a mut W, +} +impl<'a> PGVB7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Pattern Generator 0 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb0(&self) -> PGEB0_R { + PGEB0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Pattern Generator 1 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb1(&self) -> PGEB1_R { + PGEB1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Pattern Generator 2 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb2(&self) -> PGEB2_R { + PGEB2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Pattern Generator 3 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb3(&self) -> PGEB3_R { + PGEB3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Pattern Generator 4 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb4(&self) -> PGEB4_R { + PGEB4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Pattern Generator 5 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb5(&self) -> PGEB5_R { + PGEB5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Pattern Generator 6 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb6(&self) -> PGEB6_R { + PGEB6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Pattern Generator 7 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb7(&self) -> PGEB7_R { + PGEB7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Pattern Generator 0 Output Enable"] + #[inline(always)] + pub fn pgvb0(&self) -> PGVB0_R { + PGVB0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Pattern Generator 1 Output Enable"] + #[inline(always)] + pub fn pgvb1(&self) -> PGVB1_R { + PGVB1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Pattern Generator 2 Output Enable"] + #[inline(always)] + pub fn pgvb2(&self) -> PGVB2_R { + PGVB2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Pattern Generator 3 Output Enable"] + #[inline(always)] + pub fn pgvb3(&self) -> PGVB3_R { + PGVB3_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Pattern Generator 4 Output Enable"] + #[inline(always)] + pub fn pgvb4(&self) -> PGVB4_R { + PGVB4_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Pattern Generator 5 Output Enable"] + #[inline(always)] + pub fn pgvb5(&self) -> PGVB5_R { + PGVB5_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Pattern Generator 6 Output Enable"] + #[inline(always)] + pub fn pgvb6(&self) -> PGVB6_R { + PGVB6_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Pattern Generator 7 Output Enable"] + #[inline(always)] + pub fn pgvb7(&self) -> PGVB7_R { + PGVB7_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pattern Generator 0 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb0(&mut self) -> PGEB0_W { + PGEB0_W { w: self } + } + #[doc = "Bit 1 - Pattern Generator 1 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb1(&mut self) -> PGEB1_W { + PGEB1_W { w: self } + } + #[doc = "Bit 2 - Pattern Generator 2 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb2(&mut self) -> PGEB2_W { + PGEB2_W { w: self } + } + #[doc = "Bit 3 - Pattern Generator 3 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb3(&mut self) -> PGEB3_W { + PGEB3_W { w: self } + } + #[doc = "Bit 4 - Pattern Generator 4 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb4(&mut self) -> PGEB4_W { + PGEB4_W { w: self } + } + #[doc = "Bit 5 - Pattern Generator 5 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb5(&mut self) -> PGEB5_W { + PGEB5_W { w: self } + } + #[doc = "Bit 6 - Pattern Generator 6 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb6(&mut self) -> PGEB6_W { + PGEB6_W { w: self } + } + #[doc = "Bit 7 - Pattern Generator 7 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb7(&mut self) -> PGEB7_W { + PGEB7_W { w: self } + } + #[doc = "Bit 8 - Pattern Generator 0 Output Enable"] + #[inline(always)] + pub fn pgvb0(&mut self) -> PGVB0_W { + PGVB0_W { w: self } + } + #[doc = "Bit 9 - Pattern Generator 1 Output Enable"] + #[inline(always)] + pub fn pgvb1(&mut self) -> PGVB1_W { + PGVB1_W { w: self } + } + #[doc = "Bit 10 - Pattern Generator 2 Output Enable"] + #[inline(always)] + pub fn pgvb2(&mut self) -> PGVB2_W { + PGVB2_W { w: self } + } + #[doc = "Bit 11 - Pattern Generator 3 Output Enable"] + #[inline(always)] + pub fn pgvb3(&mut self) -> PGVB3_W { + PGVB3_W { w: self } + } + #[doc = "Bit 12 - Pattern Generator 4 Output Enable"] + #[inline(always)] + pub fn pgvb4(&mut self) -> PGVB4_W { + PGVB4_W { w: self } + } + #[doc = "Bit 13 - Pattern Generator 5 Output Enable"] + #[inline(always)] + pub fn pgvb5(&mut self) -> PGVB5_W { + PGVB5_W { w: self } + } + #[doc = "Bit 14 - Pattern Generator 6 Output Enable"] + #[inline(always)] + pub fn pgvb6(&mut self) -> PGVB6_W { + PGVB6_W { w: self } + } + #[doc = "Bit 15 - Pattern Generator 7 Output Enable"] + #[inline(always)] + pub fn pgvb7(&mut self) -> PGVB7_W { + PGVB7_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Pattern Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pattbuf](index.html) module"] +pub struct PATTBUF_SPEC; +impl crate::RegisterSpec for PATTBUF_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [pattbuf::R](R) reader structure"] +impl crate::Readable for PATTBUF_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [pattbuf::W](W) writer structure"] +impl crate::Writable for PATTBUF_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PATTBUF to value 0"] +impl crate::Resettable for PATTBUF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/tcc0/per.rs b/pac/atsamc21e/src/tcc0/per.rs new file mode 100644 index 000000000000..9d8618631650 --- /dev/null +++ b/pac/atsamc21e/src/tcc0/per.rs @@ -0,0 +1,103 @@ +#[doc = "Register `PER` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PER` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER` reader - Period Value"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` writer - Period Value"] +pub struct PER_W<'a> { + w: &'a mut W, +} +impl<'a> PER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Period Value"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Period Value"] + #[inline(always)] + pub fn per(&mut self) -> PER_W { + PER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [per](index.html) module"] +pub struct PER_SPEC; +impl crate::RegisterSpec for PER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [per::R](R) reader structure"] +impl crate::Readable for PER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [per::W](W) writer structure"] +impl crate::Writable for PER_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PER to value 0xffff_ffff"] +impl crate::Resettable for PER_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pac/atsamc21e/src/tcc0/per_dith4_mode.rs b/pac/atsamc21e/src/tcc0/per_dith4_mode.rs new file mode 100644 index 000000000000..2f600552db84 --- /dev/null +++ b/pac/atsamc21e/src/tcc0/per_dith4_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PER_DITH4_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PER_DITH4_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHER` reader - Dithering Cycle Number"] +pub struct DITHER_R(crate::FieldReader); +impl DITHER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHER` writer - Dithering Cycle Number"] +pub struct DITHER_W<'a> { + w: &'a mut W, +} +impl<'a> DITHER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Field `PER` reader - Period Value"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` writer - Period Value"] +pub struct PER_W<'a> { + w: &'a mut W, +} +impl<'a> PER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x000f_ffff << 4)) | ((value as u32 & 0x000f_ffff) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&self) -> DITHER_R { + DITHER_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:23 - Period Value"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(((self.bits >> 4) & 0x000f_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:3 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&mut self) -> DITHER_W { + DITHER_W { w: self } + } + #[doc = "Bits 4:23 - Period Value"] + #[inline(always)] + pub fn per(&mut self) -> PER_W { + PER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [per_dith4_mode](index.html) module"] +pub struct PER_DITH4_MODE_SPEC; +impl crate::RegisterSpec for PER_DITH4_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [per_dith4_mode::R](R) reader structure"] +impl crate::Readable for PER_DITH4_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [per_dith4_mode::W](W) writer structure"] +impl crate::Writable for PER_DITH4_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PER_DITH4_MODE to value 0xffff_ffff"] +impl crate::Resettable for PER_DITH4_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pac/atsamc21e/src/tcc0/per_dith5_mode.rs b/pac/atsamc21e/src/tcc0/per_dith5_mode.rs new file mode 100644 index 000000000000..1906582e4c95 --- /dev/null +++ b/pac/atsamc21e/src/tcc0/per_dith5_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PER_DITH5_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PER_DITH5_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHER` reader - Dithering Cycle Number"] +pub struct DITHER_R(crate::FieldReader); +impl DITHER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHER` writer - Dithering Cycle Number"] +pub struct DITHER_W<'a> { + w: &'a mut W, +} +impl<'a> DITHER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f); + self.w + } +} +#[doc = "Field `PER` reader - Period Value"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` writer - Period Value"] +pub struct PER_W<'a> { + w: &'a mut W, +} +impl<'a> PER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0007_ffff << 5)) | ((value as u32 & 0x0007_ffff) << 5); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&self) -> DITHER_R { + DITHER_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:23 - Period Value"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(((self.bits >> 5) & 0x0007_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:4 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&mut self) -> DITHER_W { + DITHER_W { w: self } + } + #[doc = "Bits 5:23 - Period Value"] + #[inline(always)] + pub fn per(&mut self) -> PER_W { + PER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [per_dith5_mode](index.html) module"] +pub struct PER_DITH5_MODE_SPEC; +impl crate::RegisterSpec for PER_DITH5_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [per_dith5_mode::R](R) reader structure"] +impl crate::Readable for PER_DITH5_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [per_dith5_mode::W](W) writer structure"] +impl crate::Writable for PER_DITH5_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PER_DITH5_MODE to value 0xffff_ffff"] +impl crate::Resettable for PER_DITH5_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pac/atsamc21e/src/tcc0/per_dith6_mode.rs b/pac/atsamc21e/src/tcc0/per_dith6_mode.rs new file mode 100644 index 000000000000..67880e220a9c --- /dev/null +++ b/pac/atsamc21e/src/tcc0/per_dith6_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PER_DITH6_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PER_DITH6_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHER` reader - Dithering Cycle Number"] +pub struct DITHER_R(crate::FieldReader); +impl DITHER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHER` writer - Dithering Cycle Number"] +pub struct DITHER_W<'a> { + w: &'a mut W, +} +impl<'a> DITHER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +#[doc = "Field `PER` reader - Period Value"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` writer - Period Value"] +pub struct PER_W<'a> { + w: &'a mut W, +} +impl<'a> PER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0003_ffff << 6)) | ((value as u32 & 0x0003_ffff) << 6); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&self) -> DITHER_R { + DITHER_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:23 - Period Value"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(((self.bits >> 6) & 0x0003_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:5 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&mut self) -> DITHER_W { + DITHER_W { w: self } + } + #[doc = "Bits 6:23 - Period Value"] + #[inline(always)] + pub fn per(&mut self) -> PER_W { + PER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [per_dith6_mode](index.html) module"] +pub struct PER_DITH6_MODE_SPEC; +impl crate::RegisterSpec for PER_DITH6_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [per_dith6_mode::R](R) reader structure"] +impl crate::Readable for PER_DITH6_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [per_dith6_mode::W](W) writer structure"] +impl crate::Writable for PER_DITH6_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PER_DITH6_MODE to value 0xffff_ffff"] +impl crate::Resettable for PER_DITH6_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pac/atsamc21e/src/tcc0/perbuf.rs b/pac/atsamc21e/src/tcc0/perbuf.rs new file mode 100644 index 000000000000..169f17479616 --- /dev/null +++ b/pac/atsamc21e/src/tcc0/perbuf.rs @@ -0,0 +1,103 @@ +#[doc = "Register `PERBUF` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PERBUF` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PERBUF` reader - Period Buffer Value"] +pub struct PERBUF_R(crate::FieldReader); +impl PERBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + PERBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERBUF` writer - Period Buffer Value"] +pub struct PERBUF_W<'a> { + w: &'a mut W, +} +impl<'a> PERBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Period Buffer Value"] + #[inline(always)] + pub fn perbuf(&self) -> PERBUF_R { + PERBUF_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Period Buffer Value"] + #[inline(always)] + pub fn perbuf(&mut self) -> PERBUF_W { + PERBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [perbuf](index.html) module"] +pub struct PERBUF_SPEC; +impl crate::RegisterSpec for PERBUF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [perbuf::R](R) reader structure"] +impl crate::Readable for PERBUF_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [perbuf::W](W) writer structure"] +impl crate::Writable for PERBUF_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PERBUF to value 0xffff_ffff"] +impl crate::Resettable for PERBUF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pac/atsamc21e/src/tcc0/perbuf_dith4_mode.rs b/pac/atsamc21e/src/tcc0/perbuf_dith4_mode.rs new file mode 100644 index 000000000000..ccf96ecef185 --- /dev/null +++ b/pac/atsamc21e/src/tcc0/perbuf_dith4_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PERBUF_DITH4_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PERBUF_DITH4_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHERBUF` reader - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_R(crate::FieldReader); +impl DITHERBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHERBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHERBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHERBUF` writer - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_W<'a> { + w: &'a mut W, +} +impl<'a> DITHERBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Field `PERBUF` reader - Period Buffer Value"] +pub struct PERBUF_R(crate::FieldReader); +impl PERBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + PERBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERBUF` writer - Period Buffer Value"] +pub struct PERBUF_W<'a> { + w: &'a mut W, +} +impl<'a> PERBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x000f_ffff << 4)) | ((value as u32 & 0x000f_ffff) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&self) -> DITHERBUF_R { + DITHERBUF_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:23 - Period Buffer Value"] + #[inline(always)] + pub fn perbuf(&self) -> PERBUF_R { + PERBUF_R::new(((self.bits >> 4) & 0x000f_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:3 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&mut self) -> DITHERBUF_W { + DITHERBUF_W { w: self } + } + #[doc = "Bits 4:23 - Period Buffer Value"] + #[inline(always)] + pub fn perbuf(&mut self) -> PERBUF_W { + PERBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [perbuf_dith4_mode](index.html) module"] +pub struct PERBUF_DITH4_MODE_SPEC; +impl crate::RegisterSpec for PERBUF_DITH4_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [perbuf_dith4_mode::R](R) reader structure"] +impl crate::Readable for PERBUF_DITH4_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [perbuf_dith4_mode::W](W) writer structure"] +impl crate::Writable for PERBUF_DITH4_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PERBUF_DITH4_MODE to value 0xffff_ffff"] +impl crate::Resettable for PERBUF_DITH4_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pac/atsamc21e/src/tcc0/perbuf_dith5_mode.rs b/pac/atsamc21e/src/tcc0/perbuf_dith5_mode.rs new file mode 100644 index 000000000000..d55f6d52c5ba --- /dev/null +++ b/pac/atsamc21e/src/tcc0/perbuf_dith5_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PERBUF_DITH5_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PERBUF_DITH5_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHERBUF` reader - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_R(crate::FieldReader); +impl DITHERBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHERBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHERBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHERBUF` writer - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_W<'a> { + w: &'a mut W, +} +impl<'a> DITHERBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f); + self.w + } +} +#[doc = "Field `PERBUF` reader - Period Buffer Value"] +pub struct PERBUF_R(crate::FieldReader); +impl PERBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + PERBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERBUF` writer - Period Buffer Value"] +pub struct PERBUF_W<'a> { + w: &'a mut W, +} +impl<'a> PERBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0007_ffff << 5)) | ((value as u32 & 0x0007_ffff) << 5); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&self) -> DITHERBUF_R { + DITHERBUF_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:23 - Period Buffer Value"] + #[inline(always)] + pub fn perbuf(&self) -> PERBUF_R { + PERBUF_R::new(((self.bits >> 5) & 0x0007_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:4 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&mut self) -> DITHERBUF_W { + DITHERBUF_W { w: self } + } + #[doc = "Bits 5:23 - Period Buffer Value"] + #[inline(always)] + pub fn perbuf(&mut self) -> PERBUF_W { + PERBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [perbuf_dith5_mode](index.html) module"] +pub struct PERBUF_DITH5_MODE_SPEC; +impl crate::RegisterSpec for PERBUF_DITH5_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [perbuf_dith5_mode::R](R) reader structure"] +impl crate::Readable for PERBUF_DITH5_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [perbuf_dith5_mode::W](W) writer structure"] +impl crate::Writable for PERBUF_DITH5_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PERBUF_DITH5_MODE to value 0xffff_ffff"] +impl crate::Resettable for PERBUF_DITH5_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pac/atsamc21e/src/tcc0/perbuf_dith6_mode.rs b/pac/atsamc21e/src/tcc0/perbuf_dith6_mode.rs new file mode 100644 index 000000000000..983c849f9073 --- /dev/null +++ b/pac/atsamc21e/src/tcc0/perbuf_dith6_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PERBUF_DITH6_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PERBUF_DITH6_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHERBUF` reader - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_R(crate::FieldReader); +impl DITHERBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHERBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHERBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHERBUF` writer - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_W<'a> { + w: &'a mut W, +} +impl<'a> DITHERBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +#[doc = "Field `PERBUF` reader - Period Buffer Value"] +pub struct PERBUF_R(crate::FieldReader); +impl PERBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + PERBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERBUF` writer - Period Buffer Value"] +pub struct PERBUF_W<'a> { + w: &'a mut W, +} +impl<'a> PERBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0003_ffff << 6)) | ((value as u32 & 0x0003_ffff) << 6); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&self) -> DITHERBUF_R { + DITHERBUF_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:23 - Period Buffer Value"] + #[inline(always)] + pub fn perbuf(&self) -> PERBUF_R { + PERBUF_R::new(((self.bits >> 6) & 0x0003_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:5 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&mut self) -> DITHERBUF_W { + DITHERBUF_W { w: self } + } + #[doc = "Bits 6:23 - Period Buffer Value"] + #[inline(always)] + pub fn perbuf(&mut self) -> PERBUF_W { + PERBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [perbuf_dith6_mode](index.html) module"] +pub struct PERBUF_DITH6_MODE_SPEC; +impl crate::RegisterSpec for PERBUF_DITH6_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [perbuf_dith6_mode::R](R) reader structure"] +impl crate::Readable for PERBUF_DITH6_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [perbuf_dith6_mode::W](W) writer structure"] +impl crate::Writable for PERBUF_DITH6_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PERBUF_DITH6_MODE to value 0xffff_ffff"] +impl crate::Resettable for PERBUF_DITH6_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pac/atsamc21e/src/tcc0/status.rs b/pac/atsamc21e/src/tcc0/status.rs new file mode 100644 index 000000000000..eecd909e6093 --- /dev/null +++ b/pac/atsamc21e/src/tcc0/status.rs @@ -0,0 +1,1147 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `STOP` reader - Stop"] +pub struct STOP_R(crate::FieldReader); +impl STOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STOP` writer - Stop"] +pub struct STOP_W<'a> { + w: &'a mut W, +} +impl<'a> STOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `IDX` reader - Ramp"] +pub struct IDX_R(crate::FieldReader); +impl IDX_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IDX_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IDX_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IDX` writer - Ramp"] +pub struct IDX_W<'a> { + w: &'a mut W, +} +impl<'a> IDX_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `UFS` reader - Non-recoverable Update Fault State"] +pub struct UFS_R(crate::FieldReader); +impl UFS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UFS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for UFS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `UFS` writer - Non-recoverable Update Fault State"] +pub struct UFS_W<'a> { + w: &'a mut W, +} +impl<'a> UFS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `DFS` reader - Non-Recoverable Debug Fault State"] +pub struct DFS_R(crate::FieldReader); +impl DFS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFS` writer - Non-Recoverable Debug Fault State"] +pub struct DFS_W<'a> { + w: &'a mut W, +} +impl<'a> DFS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `SLAVE` reader - Slave"] +pub struct SLAVE_R(crate::FieldReader); +impl SLAVE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLAVE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SLAVE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLAVE` writer - Slave"] +pub struct SLAVE_W<'a> { + w: &'a mut W, +} +impl<'a> SLAVE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PATTBUFV` reader - Pattern Buffer Valid"] +pub struct PATTBUFV_R(crate::FieldReader); +impl PATTBUFV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PATTBUFV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PATTBUFV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PATTBUFV` writer - Pattern Buffer Valid"] +pub struct PATTBUFV_W<'a> { + w: &'a mut W, +} +impl<'a> PATTBUFV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PERBUFV` reader - Period Buffer Valid"] +pub struct PERBUFV_R(crate::FieldReader); +impl PERBUFV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PERBUFV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERBUFV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERBUFV` writer - Period Buffer Valid"] +pub struct PERBUFV_W<'a> { + w: &'a mut W, +} +impl<'a> PERBUFV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `FAULTAIN` reader - Recoverable Fault A Input"] +pub struct FAULTAIN_R(crate::FieldReader); +impl FAULTAIN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTAIN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTAIN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTAIN` writer - Recoverable Fault A Input"] +pub struct FAULTAIN_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTAIN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `FAULTBIN` reader - Recoverable Fault B Input"] +pub struct FAULTBIN_R(crate::FieldReader); +impl FAULTBIN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTBIN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTBIN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTBIN` writer - Recoverable Fault B Input"] +pub struct FAULTBIN_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTBIN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `FAULT0IN` reader - Non-Recoverable Fault0 Input"] +pub struct FAULT0IN_R(crate::FieldReader); +impl FAULT0IN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT0IN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT0IN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT0IN` writer - Non-Recoverable Fault0 Input"] +pub struct FAULT0IN_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT0IN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `FAULT1IN` reader - Non-Recoverable Fault1 Input"] +pub struct FAULT1IN_R(crate::FieldReader); +impl FAULT1IN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT1IN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT1IN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT1IN` writer - Non-Recoverable Fault1 Input"] +pub struct FAULT1IN_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT1IN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `FAULTA` reader - Recoverable Fault A State"] +pub struct FAULTA_R(crate::FieldReader); +impl FAULTA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTA` writer - Recoverable Fault A State"] +pub struct FAULTA_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `FAULTB` reader - Recoverable Fault B State"] +pub struct FAULTB_R(crate::FieldReader); +impl FAULTB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTB` writer - Recoverable Fault B State"] +pub struct FAULTB_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `FAULT0` reader - Non-Recoverable Fault 0 State"] +pub struct FAULT0_R(crate::FieldReader); +impl FAULT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT0` writer - Non-Recoverable Fault 0 State"] +pub struct FAULT0_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `FAULT1` reader - Non-Recoverable Fault 1 State"] +pub struct FAULT1_R(crate::FieldReader); +impl FAULT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT1` writer - Non-Recoverable Fault 1 State"] +pub struct FAULT1_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `CCBUFV0` reader - Compare Channel 0 Buffer Valid"] +pub struct CCBUFV0_R(crate::FieldReader); +impl CCBUFV0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBUFV0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUFV0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUFV0` writer - Compare Channel 0 Buffer Valid"] +pub struct CCBUFV0_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUFV0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `CCBUFV1` reader - Compare Channel 1 Buffer Valid"] +pub struct CCBUFV1_R(crate::FieldReader); +impl CCBUFV1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBUFV1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUFV1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUFV1` writer - Compare Channel 1 Buffer Valid"] +pub struct CCBUFV1_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUFV1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `CCBUFV2` reader - Compare Channel 2 Buffer Valid"] +pub struct CCBUFV2_R(crate::FieldReader); +impl CCBUFV2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBUFV2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUFV2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUFV2` writer - Compare Channel 2 Buffer Valid"] +pub struct CCBUFV2_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUFV2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `CCBUFV3` reader - Compare Channel 3 Buffer Valid"] +pub struct CCBUFV3_R(crate::FieldReader); +impl CCBUFV3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBUFV3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUFV3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUFV3` writer - Compare Channel 3 Buffer Valid"] +pub struct CCBUFV3_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUFV3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `CMP0` reader - Compare Channel 0 Value"] +pub struct CMP0_R(crate::FieldReader); +impl CMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP0` writer - Compare Channel 0 Value"] +pub struct CMP0_W<'a> { + w: &'a mut W, +} +impl<'a> CMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `CMP1` reader - Compare Channel 1 Value"] +pub struct CMP1_R(crate::FieldReader); +impl CMP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP1` writer - Compare Channel 1 Value"] +pub struct CMP1_W<'a> { + w: &'a mut W, +} +impl<'a> CMP1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `CMP2` reader - Compare Channel 2 Value"] +pub struct CMP2_R(crate::FieldReader); +impl CMP2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP2` writer - Compare Channel 2 Value"] +pub struct CMP2_W<'a> { + w: &'a mut W, +} +impl<'a> CMP2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `CMP3` reader - Compare Channel 3 Value"] +pub struct CMP3_R(crate::FieldReader); +impl CMP3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP3` writer - Compare Channel 3 Value"] +pub struct CMP3_W<'a> { + w: &'a mut W, +} +impl<'a> CMP3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +impl R { + #[doc = "Bit 0 - Stop"] + #[inline(always)] + pub fn stop(&self) -> STOP_R { + STOP_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Ramp"] + #[inline(always)] + pub fn idx(&self) -> IDX_R { + IDX_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Non-recoverable Update Fault State"] + #[inline(always)] + pub fn ufs(&self) -> UFS_R { + UFS_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Non-Recoverable Debug Fault State"] + #[inline(always)] + pub fn dfs(&self) -> DFS_R { + DFS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Slave"] + #[inline(always)] + pub fn slave(&self) -> SLAVE_R { + SLAVE_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Pattern Buffer Valid"] + #[inline(always)] + pub fn pattbufv(&self) -> PATTBUFV_R { + PATTBUFV_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 7 - Period Buffer Valid"] + #[inline(always)] + pub fn perbufv(&self) -> PERBUFV_R { + PERBUFV_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Recoverable Fault A Input"] + #[inline(always)] + pub fn faultain(&self) -> FAULTAIN_R { + FAULTAIN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Recoverable Fault B Input"] + #[inline(always)] + pub fn faultbin(&self) -> FAULTBIN_R { + FAULTBIN_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Non-Recoverable Fault0 Input"] + #[inline(always)] + pub fn fault0in(&self) -> FAULT0IN_R { + FAULT0IN_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Non-Recoverable Fault1 Input"] + #[inline(always)] + pub fn fault1in(&self) -> FAULT1IN_R { + FAULT1IN_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Recoverable Fault A State"] + #[inline(always)] + pub fn faulta(&self) -> FAULTA_R { + FAULTA_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Recoverable Fault B State"] + #[inline(always)] + pub fn faultb(&self) -> FAULTB_R { + FAULTB_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Non-Recoverable Fault 0 State"] + #[inline(always)] + pub fn fault0(&self) -> FAULT0_R { + FAULT0_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Non-Recoverable Fault 1 State"] + #[inline(always)] + pub fn fault1(&self) -> FAULT1_R { + FAULT1_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Compare Channel 0 Buffer Valid"] + #[inline(always)] + pub fn ccbufv0(&self) -> CCBUFV0_R { + CCBUFV0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Compare Channel 1 Buffer Valid"] + #[inline(always)] + pub fn ccbufv1(&self) -> CCBUFV1_R { + CCBUFV1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Compare Channel 2 Buffer Valid"] + #[inline(always)] + pub fn ccbufv2(&self) -> CCBUFV2_R { + CCBUFV2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Compare Channel 3 Buffer Valid"] + #[inline(always)] + pub fn ccbufv3(&self) -> CCBUFV3_R { + CCBUFV3_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 24 - Compare Channel 0 Value"] + #[inline(always)] + pub fn cmp0(&self) -> CMP0_R { + CMP0_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Compare Channel 1 Value"] + #[inline(always)] + pub fn cmp1(&self) -> CMP1_R { + CMP1_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Compare Channel 2 Value"] + #[inline(always)] + pub fn cmp2(&self) -> CMP2_R { + CMP2_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Compare Channel 3 Value"] + #[inline(always)] + pub fn cmp3(&self) -> CMP3_R { + CMP3_R::new(((self.bits >> 27) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Stop"] + #[inline(always)] + pub fn stop(&mut self) -> STOP_W { + STOP_W { w: self } + } + #[doc = "Bit 1 - Ramp"] + #[inline(always)] + pub fn idx(&mut self) -> IDX_W { + IDX_W { w: self } + } + #[doc = "Bit 2 - Non-recoverable Update Fault State"] + #[inline(always)] + pub fn ufs(&mut self) -> UFS_W { + UFS_W { w: self } + } + #[doc = "Bit 3 - Non-Recoverable Debug Fault State"] + #[inline(always)] + pub fn dfs(&mut self) -> DFS_W { + DFS_W { w: self } + } + #[doc = "Bit 4 - Slave"] + #[inline(always)] + pub fn slave(&mut self) -> SLAVE_W { + SLAVE_W { w: self } + } + #[doc = "Bit 5 - Pattern Buffer Valid"] + #[inline(always)] + pub fn pattbufv(&mut self) -> PATTBUFV_W { + PATTBUFV_W { w: self } + } + #[doc = "Bit 7 - Period Buffer Valid"] + #[inline(always)] + pub fn perbufv(&mut self) -> PERBUFV_W { + PERBUFV_W { w: self } + } + #[doc = "Bit 8 - Recoverable Fault A Input"] + #[inline(always)] + pub fn faultain(&mut self) -> FAULTAIN_W { + FAULTAIN_W { w: self } + } + #[doc = "Bit 9 - Recoverable Fault B Input"] + #[inline(always)] + pub fn faultbin(&mut self) -> FAULTBIN_W { + FAULTBIN_W { w: self } + } + #[doc = "Bit 10 - Non-Recoverable Fault0 Input"] + #[inline(always)] + pub fn fault0in(&mut self) -> FAULT0IN_W { + FAULT0IN_W { w: self } + } + #[doc = "Bit 11 - Non-Recoverable Fault1 Input"] + #[inline(always)] + pub fn fault1in(&mut self) -> FAULT1IN_W { + FAULT1IN_W { w: self } + } + #[doc = "Bit 12 - Recoverable Fault A State"] + #[inline(always)] + pub fn faulta(&mut self) -> FAULTA_W { + FAULTA_W { w: self } + } + #[doc = "Bit 13 - Recoverable Fault B State"] + #[inline(always)] + pub fn faultb(&mut self) -> FAULTB_W { + FAULTB_W { w: self } + } + #[doc = "Bit 14 - Non-Recoverable Fault 0 State"] + #[inline(always)] + pub fn fault0(&mut self) -> FAULT0_W { + FAULT0_W { w: self } + } + #[doc = "Bit 15 - Non-Recoverable Fault 1 State"] + #[inline(always)] + pub fn fault1(&mut self) -> FAULT1_W { + FAULT1_W { w: self } + } + #[doc = "Bit 16 - Compare Channel 0 Buffer Valid"] + #[inline(always)] + pub fn ccbufv0(&mut self) -> CCBUFV0_W { + CCBUFV0_W { w: self } + } + #[doc = "Bit 17 - Compare Channel 1 Buffer Valid"] + #[inline(always)] + pub fn ccbufv1(&mut self) -> CCBUFV1_W { + CCBUFV1_W { w: self } + } + #[doc = "Bit 18 - Compare Channel 2 Buffer Valid"] + #[inline(always)] + pub fn ccbufv2(&mut self) -> CCBUFV2_W { + CCBUFV2_W { w: self } + } + #[doc = "Bit 19 - Compare Channel 3 Buffer Valid"] + #[inline(always)] + pub fn ccbufv3(&mut self) -> CCBUFV3_W { + CCBUFV3_W { w: self } + } + #[doc = "Bit 24 - Compare Channel 0 Value"] + #[inline(always)] + pub fn cmp0(&mut self) -> CMP0_W { + CMP0_W { w: self } + } + #[doc = "Bit 25 - Compare Channel 1 Value"] + #[inline(always)] + pub fn cmp1(&mut self) -> CMP1_W { + CMP1_W { w: self } + } + #[doc = "Bit 26 - Compare Channel 2 Value"] + #[inline(always)] + pub fn cmp2(&mut self) -> CMP2_W { + CMP2_W { w: self } + } + #[doc = "Bit 27 - Compare Channel 3 Value"] + #[inline(always)] + pub fn cmp3(&mut self) -> CMP3_W { + CMP3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0x01"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pac/atsamc21e/src/tcc0/syncbusy.rs b/pac/atsamc21e/src/tcc0/syncbusy.rs new file mode 100644 index 000000000000..db0788c3f206 --- /dev/null +++ b/pac/atsamc21e/src/tcc0/syncbusy.rs @@ -0,0 +1,273 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Swrst Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - Enable Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLB` reader - Ctrlb Busy"] +pub struct CTRLB_R(crate::FieldReader); +impl CTRLB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STATUS` reader - Status Busy"] +pub struct STATUS_R(crate::FieldReader); +impl STATUS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STATUS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STATUS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` reader - Count Busy"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PATT` reader - Pattern Busy"] +pub struct PATT_R(crate::FieldReader); +impl PATT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PATT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PATT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAVE` reader - Wave Busy"] +pub struct WAVE_R(crate::FieldReader); +impl WAVE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAVE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAVE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` reader - Period Busy"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC0` reader - Compare Channel 0 Busy"] +pub struct CC0_R(crate::FieldReader); +impl CC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC1` reader - Compare Channel 1 Busy"] +pub struct CC1_R(crate::FieldReader); +impl CC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC2` reader - Compare Channel 2 Busy"] +pub struct CC2_R(crate::FieldReader); +impl CC2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC3` reader - Compare Channel 3 Busy"] +pub struct CC3_R(crate::FieldReader); +impl CC3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Swrst Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Ctrlb Busy"] + #[inline(always)] + pub fn ctrlb(&self) -> CTRLB_R { + CTRLB_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Status Busy"] + #[inline(always)] + pub fn status(&self) -> STATUS_R { + STATUS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Count Busy"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Pattern Busy"] + #[inline(always)] + pub fn patt(&self) -> PATT_R { + PATT_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Wave Busy"] + #[inline(always)] + pub fn wave(&self) -> WAVE_R { + WAVE_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Period Busy"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Compare Channel 0 Busy"] + #[inline(always)] + pub fn cc0(&self) -> CC0_R { + CC0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Compare Channel 1 Busy"] + #[inline(always)] + pub fn cc1(&self) -> CC1_R { + CC1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Compare Channel 2 Busy"] + #[inline(always)] + pub fn cc2(&self) -> CC2_R { + CC2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Compare Channel 3 Busy"] + #[inline(always)] + pub fn cc3(&self) -> CC3_R { + CC3_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +#[doc = "Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/tcc0/wave.rs b/pac/atsamc21e/src/tcc0/wave.rs new file mode 100644 index 000000000000..8d092d429a91 --- /dev/null +++ b/pac/atsamc21e/src/tcc0/wave.rs @@ -0,0 +1,940 @@ +#[doc = "Register `WAVE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WAVE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Waveform Generation\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WAVEGEN_A { + #[doc = "0: Normal frequency"] + NFRQ = 0, + #[doc = "1: Match frequency"] + MFRQ = 1, + #[doc = "2: Normal PWM"] + NPWM = 2, + #[doc = "4: Dual-slope critical"] + DSCRITICAL = 4, + #[doc = "5: Dual-slope with interrupt/event condition when COUNT reaches ZERO"] + DSBOTTOM = 5, + #[doc = "6: Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP"] + DSBOTH = 6, + #[doc = "7: Dual-slope with interrupt/event condition when COUNT reaches TOP"] + DSTOP = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WAVEGEN_A) -> Self { + variant as _ + } +} +#[doc = "Field `WAVEGEN` reader - Waveform Generation"] +pub struct WAVEGEN_R(crate::FieldReader); +impl WAVEGEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WAVEGEN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(WAVEGEN_A::NFRQ), + 1 => Some(WAVEGEN_A::MFRQ), + 2 => Some(WAVEGEN_A::NPWM), + 4 => Some(WAVEGEN_A::DSCRITICAL), + 5 => Some(WAVEGEN_A::DSBOTTOM), + 6 => Some(WAVEGEN_A::DSBOTH), + 7 => Some(WAVEGEN_A::DSTOP), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NFRQ`"] + #[inline(always)] + pub fn is_nfrq(&self) -> bool { + **self == WAVEGEN_A::NFRQ + } + #[doc = "Checks if the value of the field is `MFRQ`"] + #[inline(always)] + pub fn is_mfrq(&self) -> bool { + **self == WAVEGEN_A::MFRQ + } + #[doc = "Checks if the value of the field is `NPWM`"] + #[inline(always)] + pub fn is_npwm(&self) -> bool { + **self == WAVEGEN_A::NPWM + } + #[doc = "Checks if the value of the field is `DSCRITICAL`"] + #[inline(always)] + pub fn is_dscritical(&self) -> bool { + **self == WAVEGEN_A::DSCRITICAL + } + #[doc = "Checks if the value of the field is `DSBOTTOM`"] + #[inline(always)] + pub fn is_dsbottom(&self) -> bool { + **self == WAVEGEN_A::DSBOTTOM + } + #[doc = "Checks if the value of the field is `DSBOTH`"] + #[inline(always)] + pub fn is_dsboth(&self) -> bool { + **self == WAVEGEN_A::DSBOTH + } + #[doc = "Checks if the value of the field is `DSTOP`"] + #[inline(always)] + pub fn is_dstop(&self) -> bool { + **self == WAVEGEN_A::DSTOP + } +} +impl core::ops::Deref for WAVEGEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAVEGEN` writer - Waveform Generation"] +pub struct WAVEGEN_W<'a> { + w: &'a mut W, +} +impl<'a> WAVEGEN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WAVEGEN_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Normal frequency"] + #[inline(always)] + pub fn nfrq(self) -> &'a mut W { + self.variant(WAVEGEN_A::NFRQ) + } + #[doc = "Match frequency"] + #[inline(always)] + pub fn mfrq(self) -> &'a mut W { + self.variant(WAVEGEN_A::MFRQ) + } + #[doc = "Normal PWM"] + #[inline(always)] + pub fn npwm(self) -> &'a mut W { + self.variant(WAVEGEN_A::NPWM) + } + #[doc = "Dual-slope critical"] + #[inline(always)] + pub fn dscritical(self) -> &'a mut W { + self.variant(WAVEGEN_A::DSCRITICAL) + } + #[doc = "Dual-slope with interrupt/event condition when COUNT reaches ZERO"] + #[inline(always)] + pub fn dsbottom(self) -> &'a mut W { + self.variant(WAVEGEN_A::DSBOTTOM) + } + #[doc = "Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP"] + #[inline(always)] + pub fn dsboth(self) -> &'a mut W { + self.variant(WAVEGEN_A::DSBOTH) + } + #[doc = "Dual-slope with interrupt/event condition when COUNT reaches TOP"] + #[inline(always)] + pub fn dstop(self) -> &'a mut W { + self.variant(WAVEGEN_A::DSTOP) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Ramp Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum RAMP_A { + #[doc = "0: RAMP1 operation"] + RAMP1 = 0, + #[doc = "1: Alternative RAMP2 operation"] + RAMP2A = 1, + #[doc = "2: RAMP2 operation"] + RAMP2 = 2, + #[doc = "3: Critical RAMP2 operation"] + RAMP2C = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RAMP_A) -> Self { + variant as _ + } +} +#[doc = "Field `RAMP` reader - Ramp Mode"] +pub struct RAMP_R(crate::FieldReader); +impl RAMP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RAMP_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RAMP_A { + match self.bits { + 0 => RAMP_A::RAMP1, + 1 => RAMP_A::RAMP2A, + 2 => RAMP_A::RAMP2, + 3 => RAMP_A::RAMP2C, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `RAMP1`"] + #[inline(always)] + pub fn is_ramp1(&self) -> bool { + **self == RAMP_A::RAMP1 + } + #[doc = "Checks if the value of the field is `RAMP2A`"] + #[inline(always)] + pub fn is_ramp2a(&self) -> bool { + **self == RAMP_A::RAMP2A + } + #[doc = "Checks if the value of the field is `RAMP2`"] + #[inline(always)] + pub fn is_ramp2(&self) -> bool { + **self == RAMP_A::RAMP2 + } + #[doc = "Checks if the value of the field is `RAMP2C`"] + #[inline(always)] + pub fn is_ramp2c(&self) -> bool { + **self == RAMP_A::RAMP2C + } +} +impl core::ops::Deref for RAMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RAMP` writer - Ramp Mode"] +pub struct RAMP_W<'a> { + w: &'a mut W, +} +impl<'a> RAMP_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RAMP_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "RAMP1 operation"] + #[inline(always)] + pub fn ramp1(self) -> &'a mut W { + self.variant(RAMP_A::RAMP1) + } + #[doc = "Alternative RAMP2 operation"] + #[inline(always)] + pub fn ramp2a(self) -> &'a mut W { + self.variant(RAMP_A::RAMP2A) + } + #[doc = "RAMP2 operation"] + #[inline(always)] + pub fn ramp2(self) -> &'a mut W { + self.variant(RAMP_A::RAMP2) + } + #[doc = "Critical RAMP2 operation"] + #[inline(always)] + pub fn ramp2c(self) -> &'a mut W { + self.variant(RAMP_A::RAMP2C) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u32 & 0x03) << 4); + self.w + } +} +#[doc = "Field `CIPEREN` reader - Circular period Enable"] +pub struct CIPEREN_R(crate::FieldReader); +impl CIPEREN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CIPEREN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CIPEREN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CIPEREN` writer - Circular period Enable"] +pub struct CIPEREN_W<'a> { + w: &'a mut W, +} +impl<'a> CIPEREN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CICCEN0` reader - Circular Channel 0 Enable"] +pub struct CICCEN0_R(crate::FieldReader); +impl CICCEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CICCEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CICCEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CICCEN0` writer - Circular Channel 0 Enable"] +pub struct CICCEN0_W<'a> { + w: &'a mut W, +} +impl<'a> CICCEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `CICCEN1` reader - Circular Channel 1 Enable"] +pub struct CICCEN1_R(crate::FieldReader); +impl CICCEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CICCEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CICCEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CICCEN1` writer - Circular Channel 1 Enable"] +pub struct CICCEN1_W<'a> { + w: &'a mut W, +} +impl<'a> CICCEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `CICCEN2` reader - Circular Channel 2 Enable"] +pub struct CICCEN2_R(crate::FieldReader); +impl CICCEN2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CICCEN2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CICCEN2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CICCEN2` writer - Circular Channel 2 Enable"] +pub struct CICCEN2_W<'a> { + w: &'a mut W, +} +impl<'a> CICCEN2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `CICCEN3` reader - Circular Channel 3 Enable"] +pub struct CICCEN3_R(crate::FieldReader); +impl CICCEN3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CICCEN3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CICCEN3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CICCEN3` writer - Circular Channel 3 Enable"] +pub struct CICCEN3_W<'a> { + w: &'a mut W, +} +impl<'a> CICCEN3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `POL0` reader - Channel 0 Polarity"] +pub struct POL0_R(crate::FieldReader); +impl POL0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + POL0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for POL0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `POL0` writer - Channel 0 Polarity"] +pub struct POL0_W<'a> { + w: &'a mut W, +} +impl<'a> POL0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `POL1` reader - Channel 1 Polarity"] +pub struct POL1_R(crate::FieldReader); +impl POL1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + POL1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for POL1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `POL1` writer - Channel 1 Polarity"] +pub struct POL1_W<'a> { + w: &'a mut W, +} +impl<'a> POL1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `POL2` reader - Channel 2 Polarity"] +pub struct POL2_R(crate::FieldReader); +impl POL2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + POL2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for POL2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `POL2` writer - Channel 2 Polarity"] +pub struct POL2_W<'a> { + w: &'a mut W, +} +impl<'a> POL2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `POL3` reader - Channel 3 Polarity"] +pub struct POL3_R(crate::FieldReader); +impl POL3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + POL3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for POL3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `POL3` writer - Channel 3 Polarity"] +pub struct POL3_W<'a> { + w: &'a mut W, +} +impl<'a> POL3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `SWAP0` reader - Swap DTI Output Pair 0"] +pub struct SWAP0_R(crate::FieldReader); +impl SWAP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWAP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWAP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWAP0` writer - Swap DTI Output Pair 0"] +pub struct SWAP0_W<'a> { + w: &'a mut W, +} +impl<'a> SWAP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `SWAP1` reader - Swap DTI Output Pair 1"] +pub struct SWAP1_R(crate::FieldReader); +impl SWAP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWAP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWAP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWAP1` writer - Swap DTI Output Pair 1"] +pub struct SWAP1_W<'a> { + w: &'a mut W, +} +impl<'a> SWAP1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `SWAP2` reader - Swap DTI Output Pair 2"] +pub struct SWAP2_R(crate::FieldReader); +impl SWAP2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWAP2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWAP2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWAP2` writer - Swap DTI Output Pair 2"] +pub struct SWAP2_W<'a> { + w: &'a mut W, +} +impl<'a> SWAP2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `SWAP3` reader - Swap DTI Output Pair 3"] +pub struct SWAP3_R(crate::FieldReader); +impl SWAP3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWAP3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWAP3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWAP3` writer - Swap DTI Output Pair 3"] +pub struct SWAP3_W<'a> { + w: &'a mut W, +} +impl<'a> SWAP3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Waveform Generation"] + #[inline(always)] + pub fn wavegen(&self) -> WAVEGEN_R { + WAVEGEN_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bits 4:5 - Ramp Mode"] + #[inline(always)] + pub fn ramp(&self) -> RAMP_R { + RAMP_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bit 7 - Circular period Enable"] + #[inline(always)] + pub fn ciperen(&self) -> CIPEREN_R { + CIPEREN_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Circular Channel 0 Enable"] + #[inline(always)] + pub fn ciccen0(&self) -> CICCEN0_R { + CICCEN0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Circular Channel 1 Enable"] + #[inline(always)] + pub fn ciccen1(&self) -> CICCEN1_R { + CICCEN1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Circular Channel 2 Enable"] + #[inline(always)] + pub fn ciccen2(&self) -> CICCEN2_R { + CICCEN2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Circular Channel 3 Enable"] + #[inline(always)] + pub fn ciccen3(&self) -> CICCEN3_R { + CICCEN3_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 16 - Channel 0 Polarity"] + #[inline(always)] + pub fn pol0(&self) -> POL0_R { + POL0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Channel 1 Polarity"] + #[inline(always)] + pub fn pol1(&self) -> POL1_R { + POL1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Channel 2 Polarity"] + #[inline(always)] + pub fn pol2(&self) -> POL2_R { + POL2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Channel 3 Polarity"] + #[inline(always)] + pub fn pol3(&self) -> POL3_R { + POL3_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 24 - Swap DTI Output Pair 0"] + #[inline(always)] + pub fn swap0(&self) -> SWAP0_R { + SWAP0_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Swap DTI Output Pair 1"] + #[inline(always)] + pub fn swap1(&self) -> SWAP1_R { + SWAP1_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Swap DTI Output Pair 2"] + #[inline(always)] + pub fn swap2(&self) -> SWAP2_R { + SWAP2_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Swap DTI Output Pair 3"] + #[inline(always)] + pub fn swap3(&self) -> SWAP3_R { + SWAP3_R::new(((self.bits >> 27) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Waveform Generation"] + #[inline(always)] + pub fn wavegen(&mut self) -> WAVEGEN_W { + WAVEGEN_W { w: self } + } + #[doc = "Bits 4:5 - Ramp Mode"] + #[inline(always)] + pub fn ramp(&mut self) -> RAMP_W { + RAMP_W { w: self } + } + #[doc = "Bit 7 - Circular period Enable"] + #[inline(always)] + pub fn ciperen(&mut self) -> CIPEREN_W { + CIPEREN_W { w: self } + } + #[doc = "Bit 8 - Circular Channel 0 Enable"] + #[inline(always)] + pub fn ciccen0(&mut self) -> CICCEN0_W { + CICCEN0_W { w: self } + } + #[doc = "Bit 9 - Circular Channel 1 Enable"] + #[inline(always)] + pub fn ciccen1(&mut self) -> CICCEN1_W { + CICCEN1_W { w: self } + } + #[doc = "Bit 10 - Circular Channel 2 Enable"] + #[inline(always)] + pub fn ciccen2(&mut self) -> CICCEN2_W { + CICCEN2_W { w: self } + } + #[doc = "Bit 11 - Circular Channel 3 Enable"] + #[inline(always)] + pub fn ciccen3(&mut self) -> CICCEN3_W { + CICCEN3_W { w: self } + } + #[doc = "Bit 16 - Channel 0 Polarity"] + #[inline(always)] + pub fn pol0(&mut self) -> POL0_W { + POL0_W { w: self } + } + #[doc = "Bit 17 - Channel 1 Polarity"] + #[inline(always)] + pub fn pol1(&mut self) -> POL1_W { + POL1_W { w: self } + } + #[doc = "Bit 18 - Channel 2 Polarity"] + #[inline(always)] + pub fn pol2(&mut self) -> POL2_W { + POL2_W { w: self } + } + #[doc = "Bit 19 - Channel 3 Polarity"] + #[inline(always)] + pub fn pol3(&mut self) -> POL3_W { + POL3_W { w: self } + } + #[doc = "Bit 24 - Swap DTI Output Pair 0"] + #[inline(always)] + pub fn swap0(&mut self) -> SWAP0_W { + SWAP0_W { w: self } + } + #[doc = "Bit 25 - Swap DTI Output Pair 1"] + #[inline(always)] + pub fn swap1(&mut self) -> SWAP1_W { + SWAP1_W { w: self } + } + #[doc = "Bit 26 - Swap DTI Output Pair 2"] + #[inline(always)] + pub fn swap2(&mut self) -> SWAP2_W { + SWAP2_W { w: self } + } + #[doc = "Bit 27 - Swap DTI Output Pair 3"] + #[inline(always)] + pub fn swap3(&mut self) -> SWAP3_W { + SWAP3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Waveform Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wave](index.html) module"] +pub struct WAVE_SPEC; +impl crate::RegisterSpec for WAVE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [wave::R](R) reader structure"] +impl crate::Readable for WAVE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wave::W](W) writer structure"] +impl crate::Writable for WAVE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WAVE to value 0"] +impl crate::Resettable for WAVE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/tcc0/wexctrl.rs b/pac/atsamc21e/src/tcc0/wexctrl.rs new file mode 100644 index 000000000000..8eb0d29cbee5 --- /dev/null +++ b/pac/atsamc21e/src/tcc0/wexctrl.rs @@ -0,0 +1,365 @@ +#[doc = "Register `WEXCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WEXCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OTMX` reader - Output Matrix"] +pub struct OTMX_R(crate::FieldReader); +impl OTMX_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + OTMX_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OTMX_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OTMX` writer - Output Matrix"] +pub struct OTMX_W<'a> { + w: &'a mut W, +} +impl<'a> OTMX_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u32 & 0x03); + self.w + } +} +#[doc = "Field `DTIEN0` reader - Dead-time Insertion Generator 0 Enable"] +pub struct DTIEN0_R(crate::FieldReader); +impl DTIEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DTIEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DTIEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DTIEN0` writer - Dead-time Insertion Generator 0 Enable"] +pub struct DTIEN0_W<'a> { + w: &'a mut W, +} +impl<'a> DTIEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `DTIEN1` reader - Dead-time Insertion Generator 1 Enable"] +pub struct DTIEN1_R(crate::FieldReader); +impl DTIEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DTIEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DTIEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DTIEN1` writer - Dead-time Insertion Generator 1 Enable"] +pub struct DTIEN1_W<'a> { + w: &'a mut W, +} +impl<'a> DTIEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `DTIEN2` reader - Dead-time Insertion Generator 2 Enable"] +pub struct DTIEN2_R(crate::FieldReader); +impl DTIEN2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DTIEN2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DTIEN2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DTIEN2` writer - Dead-time Insertion Generator 2 Enable"] +pub struct DTIEN2_W<'a> { + w: &'a mut W, +} +impl<'a> DTIEN2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `DTIEN3` reader - Dead-time Insertion Generator 3 Enable"] +pub struct DTIEN3_R(crate::FieldReader); +impl DTIEN3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DTIEN3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DTIEN3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DTIEN3` writer - Dead-time Insertion Generator 3 Enable"] +pub struct DTIEN3_W<'a> { + w: &'a mut W, +} +impl<'a> DTIEN3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `DTLS` reader - Dead-time Low Side Outputs Value"] +pub struct DTLS_R(crate::FieldReader); +impl DTLS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DTLS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DTLS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DTLS` writer - Dead-time Low Side Outputs Value"] +pub struct DTLS_W<'a> { + w: &'a mut W, +} +impl<'a> DTLS_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +#[doc = "Field `DTHS` reader - Dead-time High Side Outputs Value"] +pub struct DTHS_R(crate::FieldReader); +impl DTHS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DTHS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DTHS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DTHS` writer - Dead-time High Side Outputs Value"] +pub struct DTHS_W<'a> { + w: &'a mut W, +} +impl<'a> DTHS_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 24)) | ((value as u32 & 0xff) << 24); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Output Matrix"] + #[inline(always)] + pub fn otmx(&self) -> OTMX_R { + OTMX_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bit 8 - Dead-time Insertion Generator 0 Enable"] + #[inline(always)] + pub fn dtien0(&self) -> DTIEN0_R { + DTIEN0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Dead-time Insertion Generator 1 Enable"] + #[inline(always)] + pub fn dtien1(&self) -> DTIEN1_R { + DTIEN1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Dead-time Insertion Generator 2 Enable"] + #[inline(always)] + pub fn dtien2(&self) -> DTIEN2_R { + DTIEN2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Dead-time Insertion Generator 3 Enable"] + #[inline(always)] + pub fn dtien3(&self) -> DTIEN3_R { + DTIEN3_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bits 16:23 - Dead-time Low Side Outputs Value"] + #[inline(always)] + pub fn dtls(&self) -> DTLS_R { + DTLS_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Dead-time High Side Outputs Value"] + #[inline(always)] + pub fn dths(&self) -> DTHS_R { + DTHS_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Output Matrix"] + #[inline(always)] + pub fn otmx(&mut self) -> OTMX_W { + OTMX_W { w: self } + } + #[doc = "Bit 8 - Dead-time Insertion Generator 0 Enable"] + #[inline(always)] + pub fn dtien0(&mut self) -> DTIEN0_W { + DTIEN0_W { w: self } + } + #[doc = "Bit 9 - Dead-time Insertion Generator 1 Enable"] + #[inline(always)] + pub fn dtien1(&mut self) -> DTIEN1_W { + DTIEN1_W { w: self } + } + #[doc = "Bit 10 - Dead-time Insertion Generator 2 Enable"] + #[inline(always)] + pub fn dtien2(&mut self) -> DTIEN2_W { + DTIEN2_W { w: self } + } + #[doc = "Bit 11 - Dead-time Insertion Generator 3 Enable"] + #[inline(always)] + pub fn dtien3(&mut self) -> DTIEN3_W { + DTIEN3_W { w: self } + } + #[doc = "Bits 16:23 - Dead-time Low Side Outputs Value"] + #[inline(always)] + pub fn dtls(&mut self) -> DTLS_W { + DTLS_W { w: self } + } + #[doc = "Bits 24:31 - Dead-time High Side Outputs Value"] + #[inline(always)] + pub fn dths(&mut self) -> DTHS_W { + DTHS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Waveform Extension Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wexctrl](index.html) module"] +pub struct WEXCTRL_SPEC; +impl crate::RegisterSpec for WEXCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [wexctrl::R](R) reader structure"] +impl crate::Readable for WEXCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wexctrl::W](W) writer structure"] +impl crate::Writable for WEXCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WEXCTRL to value 0"] +impl crate::Resettable for WEXCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/tsens.rs b/pac/atsamc21e/src/tsens.rs new file mode 100644 index 000000000000..3156dee6d87f --- /dev/null +++ b/pac/atsamc21e/src/tsens.rs @@ -0,0 +1,100 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control A Register"] + pub ctrla: crate::Reg, + #[doc = "0x01 - Control B Register"] + pub ctrlb: crate::Reg, + #[doc = "0x02 - Control C Register"] + pub ctrlc: crate::Reg, + #[doc = "0x03 - Event Control Register"] + pub evctrl: crate::Reg, + #[doc = "0x04 - Interrupt Enable Clear Register"] + pub intenclr: crate::Reg, + #[doc = "0x05 - Interrupt Enable Set Register"] + pub intenset: crate::Reg, + #[doc = "0x06 - Interrupt Flag Status and Clear Register"] + pub intflag: crate::Reg, + #[doc = "0x07 - Status Register"] + pub status: crate::Reg, + #[doc = "0x08 - Synchronization Busy Register"] + pub syncbusy: crate::Reg, + #[doc = "0x0c - Value Register"] + pub value: crate::Reg, + #[doc = "0x10 - Window Monitor Lower Threshold Register"] + pub winlt: crate::Reg, + #[doc = "0x14 - Window Monitor Upper Threshold Register"] + pub winut: crate::Reg, + #[doc = "0x18 - Gain Register"] + pub gain: crate::Reg, + #[doc = "0x1c - Offset Register"] + pub offset: crate::Reg, + #[doc = "0x20 - Calibration Register"] + pub cal: crate::Reg, + #[doc = "0x24 - Debug Control Register"] + pub dbgctrl: crate::Reg, +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A Register"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "Control B Register"] +pub mod ctrlb; +#[doc = "CTRLC register accessor: an alias for `Reg`"] +pub type CTRLC = crate::Reg; +#[doc = "Control C Register"] +pub mod ctrlc; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control Register"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear Register"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set Register"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear Register"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status Register"] +pub mod status; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Busy Register"] +pub mod syncbusy; +#[doc = "VALUE register accessor: an alias for `Reg`"] +pub type VALUE = crate::Reg; +#[doc = "Value Register"] +pub mod value; +#[doc = "WINLT register accessor: an alias for `Reg`"] +pub type WINLT = crate::Reg; +#[doc = "Window Monitor Lower Threshold Register"] +pub mod winlt; +#[doc = "WINUT register accessor: an alias for `Reg`"] +pub type WINUT = crate::Reg; +#[doc = "Window Monitor Upper Threshold Register"] +pub mod winut; +#[doc = "GAIN register accessor: an alias for `Reg`"] +pub type GAIN = crate::Reg; +#[doc = "Gain Register"] +pub mod gain; +#[doc = "OFFSET register accessor: an alias for `Reg`"] +pub type OFFSET = crate::Reg; +#[doc = "Offset Register"] +pub mod offset; +#[doc = "CAL register accessor: an alias for `Reg`"] +pub type CAL = crate::Reg; +#[doc = "Calibration Register"] +pub mod cal; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control Register"] +pub mod dbgctrl; diff --git a/pac/atsamc21e/src/tsens/cal.rs b/pac/atsamc21e/src/tsens/cal.rs new file mode 100644 index 000000000000..9b0d76eef9eb --- /dev/null +++ b/pac/atsamc21e/src/tsens/cal.rs @@ -0,0 +1,140 @@ +#[doc = "Register `CAL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CAL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FCAL` reader - Frequency Calibration"] +pub struct FCAL_R(crate::FieldReader); +impl FCAL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FCAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FCAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FCAL` writer - Frequency Calibration"] +pub struct FCAL_W<'a> { + w: &'a mut W, +} +impl<'a> FCAL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +#[doc = "Field `TCAL` reader - Temperature Calibration"] +pub struct TCAL_R(crate::FieldReader); +impl TCAL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TCAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCAL` writer - Temperature Calibration"] +pub struct TCAL_W<'a> { + w: &'a mut W, +} +impl<'a> TCAL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 8)) | ((value as u32 & 0x3f) << 8); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Frequency Calibration"] + #[inline(always)] + pub fn fcal(&self) -> FCAL_R { + FCAL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 8:13 - Temperature Calibration"] + #[inline(always)] + pub fn tcal(&self) -> TCAL_R { + TCAL_R::new(((self.bits >> 8) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - Frequency Calibration"] + #[inline(always)] + pub fn fcal(&mut self) -> FCAL_W { + FCAL_W { w: self } + } + #[doc = "Bits 8:13 - Temperature Calibration"] + #[inline(always)] + pub fn tcal(&mut self) -> TCAL_W { + TCAL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Calibration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cal](index.html) module"] +pub struct CAL_SPEC; +impl crate::RegisterSpec for CAL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cal::R](R) reader structure"] +impl crate::Readable for CAL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cal::W](W) writer structure"] +impl crate::Writable for CAL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CAL to value 0"] +impl crate::Resettable for CAL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/tsens/ctrla.rs b/pac/atsamc21e/src/tsens/ctrla.rs new file mode 100644 index 000000000000..6be7f2fc82f2 --- /dev/null +++ b/pac/atsamc21e/src/tsens/ctrla.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/tsens/ctrlb.rs b/pac/atsamc21e/src/tsens/ctrlb.rs new file mode 100644 index 000000000000..7d350e71fbf3 --- /dev/null +++ b/pac/atsamc21e/src/tsens/ctrlb.rs @@ -0,0 +1,72 @@ +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `START` writer - Start Measurement"] +pub struct START_W<'a> { + w: &'a mut W, +} +impl<'a> START_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0 - Start Measurement"] + #[inline(always)] + pub fn start(&mut self) -> START_W { + START_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u8; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/tsens/ctrlc.rs b/pac/atsamc21e/src/tsens/ctrlc.rs new file mode 100644 index 000000000000..82390cea825d --- /dev/null +++ b/pac/atsamc21e/src/tsens/ctrlc.rs @@ -0,0 +1,264 @@ +#[doc = "Register `CTRLC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Window Monitor Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WINMODE_A { + #[doc = "0: No window mode (default)"] + DISABLE = 0, + #[doc = "1: VALUE greater than WINLT"] + ABOVE = 1, + #[doc = "2: VALUE less than WINUT"] + BELOW = 2, + #[doc = "3: VALUE greater than WINLT and VALUE less than WINUT"] + INSIDE = 3, + #[doc = "4: VALUE less than WINLT or VALUE greater than WINUT"] + OUTSIDE = 4, + #[doc = "5: VALUE greater than WINUT with hysteresis to WINLT"] + HYST_ABOVE = 5, + #[doc = "6: VALUE less than WINLST with hysteresis to WINUT"] + HYST_BELOW = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WINMODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `WINMODE` reader - Window Monitor Mode"] +pub struct WINMODE_R(crate::FieldReader); +impl WINMODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WINMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(WINMODE_A::DISABLE), + 1 => Some(WINMODE_A::ABOVE), + 2 => Some(WINMODE_A::BELOW), + 3 => Some(WINMODE_A::INSIDE), + 4 => Some(WINMODE_A::OUTSIDE), + 5 => Some(WINMODE_A::HYST_ABOVE), + 6 => Some(WINMODE_A::HYST_BELOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == WINMODE_A::DISABLE + } + #[doc = "Checks if the value of the field is `ABOVE`"] + #[inline(always)] + pub fn is_above(&self) -> bool { + **self == WINMODE_A::ABOVE + } + #[doc = "Checks if the value of the field is `BELOW`"] + #[inline(always)] + pub fn is_below(&self) -> bool { + **self == WINMODE_A::BELOW + } + #[doc = "Checks if the value of the field is `INSIDE`"] + #[inline(always)] + pub fn is_inside(&self) -> bool { + **self == WINMODE_A::INSIDE + } + #[doc = "Checks if the value of the field is `OUTSIDE`"] + #[inline(always)] + pub fn is_outside(&self) -> bool { + **self == WINMODE_A::OUTSIDE + } + #[doc = "Checks if the value of the field is `HYST_ABOVE`"] + #[inline(always)] + pub fn is_hyst_above(&self) -> bool { + **self == WINMODE_A::HYST_ABOVE + } + #[doc = "Checks if the value of the field is `HYST_BELOW`"] + #[inline(always)] + pub fn is_hyst_below(&self) -> bool { + **self == WINMODE_A::HYST_BELOW + } +} +impl core::ops::Deref for WINMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMODE` writer - Window Monitor Mode"] +pub struct WINMODE_W<'a> { + w: &'a mut W, +} +impl<'a> WINMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WINMODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No window mode (default)"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(WINMODE_A::DISABLE) + } + #[doc = "VALUE greater than WINLT"] + #[inline(always)] + pub fn above(self) -> &'a mut W { + self.variant(WINMODE_A::ABOVE) + } + #[doc = "VALUE less than WINUT"] + #[inline(always)] + pub fn below(self) -> &'a mut W { + self.variant(WINMODE_A::BELOW) + } + #[doc = "VALUE greater than WINLT and VALUE less than WINUT"] + #[inline(always)] + pub fn inside(self) -> &'a mut W { + self.variant(WINMODE_A::INSIDE) + } + #[doc = "VALUE less than WINLT or VALUE greater than WINUT"] + #[inline(always)] + pub fn outside(self) -> &'a mut W { + self.variant(WINMODE_A::OUTSIDE) + } + #[doc = "VALUE greater than WINUT with hysteresis to WINLT"] + #[inline(always)] + pub fn hyst_above(self) -> &'a mut W { + self.variant(WINMODE_A::HYST_ABOVE) + } + #[doc = "VALUE less than WINLST with hysteresis to WINUT"] + #[inline(always)] + pub fn hyst_below(self) -> &'a mut W { + self.variant(WINMODE_A::HYST_BELOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +#[doc = "Field `FREERUN` reader - Free Running Measurement"] +pub struct FREERUN_R(crate::FieldReader); +impl FREERUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FREERUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FREERUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FREERUN` writer - Free Running Measurement"] +pub struct FREERUN_W<'a> { + w: &'a mut W, +} +impl<'a> FREERUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Window Monitor Mode"] + #[inline(always)] + pub fn winmode(&self) -> WINMODE_R { + WINMODE_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 4 - Free Running Measurement"] + #[inline(always)] + pub fn freerun(&self) -> FREERUN_R { + FREERUN_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Window Monitor Mode"] + #[inline(always)] + pub fn winmode(&mut self) -> WINMODE_W { + WINMODE_W { w: self } + } + #[doc = "Bit 4 - Free Running Measurement"] + #[inline(always)] + pub fn freerun(&mut self) -> FREERUN_W { + FREERUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control C Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlc](index.html) module"] +pub struct CTRLC_SPEC; +impl crate::RegisterSpec for CTRLC_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlc::R](R) reader structure"] +impl crate::Readable for CTRLC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlc::W](W) writer structure"] +impl crate::Writable for CTRLC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLC to value 0"] +impl crate::Resettable for CTRLC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/tsens/dbgctrl.rs b/pac/atsamc21e/src/tsens/dbgctrl.rs new file mode 100644 index 000000000000..dd129a857202 --- /dev/null +++ b/pac/atsamc21e/src/tsens/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Debug Run"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Debug Run"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/tsens/evctrl.rs b/pac/atsamc21e/src/tsens/evctrl.rs new file mode 100644 index 000000000000..20d0f3497e37 --- /dev/null +++ b/pac/atsamc21e/src/tsens/evctrl.rs @@ -0,0 +1,207 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `STARTEI` reader - Start Conversion Event Input Enable"] +pub struct STARTEI_R(crate::FieldReader); +impl STARTEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STARTEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STARTEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STARTEI` writer - Start Conversion Event Input Enable"] +pub struct STARTEI_W<'a> { + w: &'a mut W, +} +impl<'a> STARTEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `STARTINV` reader - Start Conversion Event Invert Enable"] +pub struct STARTINV_R(crate::FieldReader); +impl STARTINV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STARTINV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STARTINV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STARTINV` writer - Start Conversion Event Invert Enable"] +pub struct STARTINV_W<'a> { + w: &'a mut W, +} +impl<'a> STARTINV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WINEO` reader - Window Monitor Event Out"] +pub struct WINEO_R(crate::FieldReader); +impl WINEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINEO` writer - Window Monitor Event Out"] +pub struct WINEO_W<'a> { + w: &'a mut W, +} +impl<'a> WINEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Start Conversion Event Input Enable"] + #[inline(always)] + pub fn startei(&self) -> STARTEI_R { + STARTEI_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Start Conversion Event Invert Enable"] + #[inline(always)] + pub fn startinv(&self) -> STARTINV_R { + STARTINV_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Window Monitor Event Out"] + #[inline(always)] + pub fn wineo(&self) -> WINEO_R { + WINEO_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Start Conversion Event Input Enable"] + #[inline(always)] + pub fn startei(&mut self) -> STARTEI_W { + STARTEI_W { w: self } + } + #[doc = "Bit 1 - Start Conversion Event Invert Enable"] + #[inline(always)] + pub fn startinv(&mut self) -> STARTINV_W { + STARTINV_W { w: self } + } + #[doc = "Bit 2 - Window Monitor Event Out"] + #[inline(always)] + pub fn wineo(&mut self) -> WINEO_W { + WINEO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/tsens/gain.rs b/pac/atsamc21e/src/tsens/gain.rs new file mode 100644 index 000000000000..785bbef3b6a4 --- /dev/null +++ b/pac/atsamc21e/src/tsens/gain.rs @@ -0,0 +1,103 @@ +#[doc = "Register `GAIN` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GAIN` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `GAIN` reader - Time Amplifier Gain"] +pub struct GAIN_R(crate::FieldReader); +impl GAIN_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + GAIN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GAIN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GAIN` writer - Time Amplifier Gain"] +pub struct GAIN_W<'a> { + w: &'a mut W, +} +impl<'a> GAIN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Time Amplifier Gain"] + #[inline(always)] + pub fn gain(&self) -> GAIN_R { + GAIN_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Time Amplifier Gain"] + #[inline(always)] + pub fn gain(&mut self) -> GAIN_W { + GAIN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Gain Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gain](index.html) module"] +pub struct GAIN_SPEC; +impl crate::RegisterSpec for GAIN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gain::R](R) reader structure"] +impl crate::Readable for GAIN_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gain::W](W) writer structure"] +impl crate::Writable for GAIN_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets GAIN to value 0"] +impl crate::Resettable for GAIN_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/tsens/intenclr.rs b/pac/atsamc21e/src/tsens/intenclr.rs new file mode 100644 index 000000000000..2362cf7b512b --- /dev/null +++ b/pac/atsamc21e/src/tsens/intenclr.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RESRDY` reader - Result Ready Interrupt Enable"] +pub struct RESRDY_R(crate::FieldReader); +impl RESRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESRDY` writer - Result Ready Interrupt Enable"] +pub struct RESRDY_W<'a> { + w: &'a mut W, +} +impl<'a> RESRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `OVERRUN` reader - Overrun Interrupt Enable"] +pub struct OVERRUN_R(crate::FieldReader); +impl OVERRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVERRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVERRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVERRUN` writer - Overrun Interrupt Enable"] +pub struct OVERRUN_W<'a> { + w: &'a mut W, +} +impl<'a> OVERRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WINMON` reader - Window Monitor Interrupt Enable"] +pub struct WINMON_R(crate::FieldReader); +impl WINMON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINMON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINMON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMON` writer - Window Monitor Interrupt Enable"] +pub struct WINMON_W<'a> { + w: &'a mut W, +} +impl<'a> WINMON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +impl R { + #[doc = "Bit 0 - Result Ready Interrupt Enable"] + #[inline(always)] + pub fn resrdy(&self) -> RESRDY_R { + RESRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Overrun Interrupt Enable"] + #[inline(always)] + pub fn overrun(&self) -> OVERRUN_R { + OVERRUN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Window Monitor Interrupt Enable"] + #[inline(always)] + pub fn winmon(&self) -> WINMON_R { + WINMON_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 3) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Result Ready Interrupt Enable"] + #[inline(always)] + pub fn resrdy(&mut self) -> RESRDY_W { + RESRDY_W { w: self } + } + #[doc = "Bit 1 - Overrun Interrupt Enable"] + #[inline(always)] + pub fn overrun(&mut self) -> OVERRUN_W { + OVERRUN_W { w: self } + } + #[doc = "Bit 2 - Window Monitor Interrupt Enable"] + #[inline(always)] + pub fn winmon(&mut self) -> WINMON_W { + WINMON_W { w: self } + } + #[doc = "Bit 3 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/tsens/intenset.rs b/pac/atsamc21e/src/tsens/intenset.rs new file mode 100644 index 000000000000..51df8bb668f2 --- /dev/null +++ b/pac/atsamc21e/src/tsens/intenset.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RESRDY` reader - Result Ready Interrupt Enable"] +pub struct RESRDY_R(crate::FieldReader); +impl RESRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESRDY` writer - Result Ready Interrupt Enable"] +pub struct RESRDY_W<'a> { + w: &'a mut W, +} +impl<'a> RESRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `OVERRUN` reader - Overrun Interrupt Enable"] +pub struct OVERRUN_R(crate::FieldReader); +impl OVERRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVERRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVERRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVERRUN` writer - Overrun Interrupt Enable"] +pub struct OVERRUN_W<'a> { + w: &'a mut W, +} +impl<'a> OVERRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WINMON` reader - Window Monitor Interrupt Enable"] +pub struct WINMON_R(crate::FieldReader); +impl WINMON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINMON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINMON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMON` writer - Window Monitor Interrupt Enable"] +pub struct WINMON_W<'a> { + w: &'a mut W, +} +impl<'a> WINMON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +impl R { + #[doc = "Bit 0 - Result Ready Interrupt Enable"] + #[inline(always)] + pub fn resrdy(&self) -> RESRDY_R { + RESRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Overrun Interrupt Enable"] + #[inline(always)] + pub fn overrun(&self) -> OVERRUN_R { + OVERRUN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Window Monitor Interrupt Enable"] + #[inline(always)] + pub fn winmon(&self) -> WINMON_R { + WINMON_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 3) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Result Ready Interrupt Enable"] + #[inline(always)] + pub fn resrdy(&mut self) -> RESRDY_W { + RESRDY_W { w: self } + } + #[doc = "Bit 1 - Overrun Interrupt Enable"] + #[inline(always)] + pub fn overrun(&mut self) -> OVERRUN_W { + OVERRUN_W { w: self } + } + #[doc = "Bit 2 - Window Monitor Interrupt Enable"] + #[inline(always)] + pub fn winmon(&mut self) -> WINMON_W { + WINMON_W { w: self } + } + #[doc = "Bit 3 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/tsens/intflag.rs b/pac/atsamc21e/src/tsens/intflag.rs new file mode 100644 index 000000000000..5058a4f8712c --- /dev/null +++ b/pac/atsamc21e/src/tsens/intflag.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RESRDY` reader - Result Ready"] +pub struct RESRDY_R(crate::FieldReader); +impl RESRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESRDY` writer - Result Ready"] +pub struct RESRDY_W<'a> { + w: &'a mut W, +} +impl<'a> RESRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `OVERRUN` reader - Overrun"] +pub struct OVERRUN_R(crate::FieldReader); +impl OVERRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVERRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVERRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVERRUN` writer - Overrun"] +pub struct OVERRUN_W<'a> { + w: &'a mut W, +} +impl<'a> OVERRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WINMON` reader - Window Monitor"] +pub struct WINMON_R(crate::FieldReader); +impl WINMON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINMON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINMON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMON` writer - Window Monitor"] +pub struct WINMON_W<'a> { + w: &'a mut W, +} +impl<'a> WINMON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +impl R { + #[doc = "Bit 0 - Result Ready"] + #[inline(always)] + pub fn resrdy(&self) -> RESRDY_R { + RESRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Overrun"] + #[inline(always)] + pub fn overrun(&self) -> OVERRUN_R { + OVERRUN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Window Monitor"] + #[inline(always)] + pub fn winmon(&self) -> WINMON_R { + WINMON_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Overflow"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 3) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Result Ready"] + #[inline(always)] + pub fn resrdy(&mut self) -> RESRDY_W { + RESRDY_W { w: self } + } + #[doc = "Bit 1 - Overrun"] + #[inline(always)] + pub fn overrun(&mut self) -> OVERRUN_W { + OVERRUN_W { w: self } + } + #[doc = "Bit 2 - Window Monitor"] + #[inline(always)] + pub fn winmon(&mut self) -> WINMON_W { + WINMON_W { w: self } + } + #[doc = "Bit 3 - Overflow"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/tsens/offset.rs b/pac/atsamc21e/src/tsens/offset.rs new file mode 100644 index 000000000000..1796ac252c12 --- /dev/null +++ b/pac/atsamc21e/src/tsens/offset.rs @@ -0,0 +1,103 @@ +#[doc = "Register `OFFSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OFFSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OFFSETC` reader - Offset Correction"] +pub struct OFFSETC_R(crate::FieldReader); +impl OFFSETC_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + OFFSETC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OFFSETC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OFFSETC` writer - Offset Correction"] +pub struct OFFSETC_W<'a> { + w: &'a mut W, +} +impl<'a> OFFSETC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Offset Correction"] + #[inline(always)] + pub fn offsetc(&self) -> OFFSETC_R { + OFFSETC_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Offset Correction"] + #[inline(always)] + pub fn offsetc(&mut self) -> OFFSETC_W { + OFFSETC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Offset Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [offset](index.html) module"] +pub struct OFFSET_SPEC; +impl crate::RegisterSpec for OFFSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [offset::R](R) reader structure"] +impl crate::Readable for OFFSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [offset::W](W) writer structure"] +impl crate::Writable for OFFSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OFFSET to value 0"] +impl crate::Resettable for OFFSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/tsens/status.rs b/pac/atsamc21e/src/tsens/status.rs new file mode 100644 index 000000000000..42309f7dcb4c --- /dev/null +++ b/pac/atsamc21e/src/tsens/status.rs @@ -0,0 +1,53 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `OVF` reader - Result Overflow"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Result Overflow"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } +} +#[doc = "Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/tsens/syncbusy.rs b/pac/atsamc21e/src/tsens/syncbusy.rs new file mode 100644 index 000000000000..e4492e16ad3c --- /dev/null +++ b/pac/atsamc21e/src/tsens/syncbusy.rs @@ -0,0 +1,73 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - Enable Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +#[doc = "Synchronization Busy Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/tsens/value.rs b/pac/atsamc21e/src/tsens/value.rs new file mode 100644 index 000000000000..54232a992edf --- /dev/null +++ b/pac/atsamc21e/src/tsens/value.rs @@ -0,0 +1,53 @@ +#[doc = "Register `VALUE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `VALUE` reader - Measurement Value"] +pub struct VALUE_R(crate::FieldReader); +impl VALUE_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + VALUE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VALUE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:23 - Measurement Value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +#[doc = "Value Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [value](index.html) module"] +pub struct VALUE_SPEC; +impl crate::RegisterSpec for VALUE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [value::R](R) reader structure"] +impl crate::Readable for VALUE_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets VALUE to value 0"] +impl crate::Resettable for VALUE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/tsens/winlt.rs b/pac/atsamc21e/src/tsens/winlt.rs new file mode 100644 index 000000000000..85a1d01b4b34 --- /dev/null +++ b/pac/atsamc21e/src/tsens/winlt.rs @@ -0,0 +1,103 @@ +#[doc = "Register `WINLT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WINLT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WINLT` reader - Window Lower Threshold"] +pub struct WINLT_R(crate::FieldReader); +impl WINLT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + WINLT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINLT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINLT` writer - Window Lower Threshold"] +pub struct WINLT_W<'a> { + w: &'a mut W, +} +impl<'a> WINLT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Window Lower Threshold"] + #[inline(always)] + pub fn winlt(&self) -> WINLT_R { + WINLT_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Window Lower Threshold"] + #[inline(always)] + pub fn winlt(&mut self) -> WINLT_W { + WINLT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Window Monitor Lower Threshold Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [winlt](index.html) module"] +pub struct WINLT_SPEC; +impl crate::RegisterSpec for WINLT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [winlt::R](R) reader structure"] +impl crate::Readable for WINLT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [winlt::W](W) writer structure"] +impl crate::Writable for WINLT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WINLT to value 0"] +impl crate::Resettable for WINLT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/tsens/winut.rs b/pac/atsamc21e/src/tsens/winut.rs new file mode 100644 index 000000000000..7da0850f8e50 --- /dev/null +++ b/pac/atsamc21e/src/tsens/winut.rs @@ -0,0 +1,103 @@ +#[doc = "Register `WINUT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WINUT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WINUT` reader - Window Upper Threshold"] +pub struct WINUT_R(crate::FieldReader); +impl WINUT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + WINUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINUT` writer - Window Upper Threshold"] +pub struct WINUT_W<'a> { + w: &'a mut W, +} +impl<'a> WINUT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Window Upper Threshold"] + #[inline(always)] + pub fn winut(&self) -> WINUT_R { + WINUT_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Window Upper Threshold"] + #[inline(always)] + pub fn winut(&mut self) -> WINUT_W { + WINUT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Window Monitor Upper Threshold Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [winut](index.html) module"] +pub struct WINUT_SPEC; +impl crate::RegisterSpec for WINUT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [winut::R](R) reader structure"] +impl crate::Readable for WINUT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [winut::W](W) writer structure"] +impl crate::Writable for WINUT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WINUT to value 0"] +impl crate::Resettable for WINUT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/wdt.rs b/pac/atsamc21e/src/wdt.rs new file mode 100644 index 000000000000..22b5c2bb706f --- /dev/null +++ b/pac/atsamc21e/src/wdt.rs @@ -0,0 +1,54 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrla: crate::Reg, + #[doc = "0x01 - Configuration"] + pub config: crate::Reg, + #[doc = "0x02 - Early Warning Interrupt Control"] + pub ewctrl: crate::Reg, + _reserved3: [u8; 0x01], + #[doc = "0x04 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x05 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x06 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x08 - Synchronization Busy"] + pub syncbusy: crate::Reg, + #[doc = "0x0c - Clear"] + pub clear: crate::Reg, +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control"] +pub mod ctrla; +#[doc = "CONFIG register accessor: an alias for `Reg`"] +pub type CONFIG = crate::Reg; +#[doc = "Configuration"] +pub mod config; +#[doc = "EWCTRL register accessor: an alias for `Reg`"] +pub type EWCTRL = crate::Reg; +#[doc = "Early Warning Interrupt Control"] +pub mod ewctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Busy"] +pub mod syncbusy; +#[doc = "CLEAR register accessor: an alias for `Reg`"] +pub type CLEAR = crate::Reg; +#[doc = "Clear"] +pub mod clear; diff --git a/pac/atsamc21e/src/wdt/clear.rs b/pac/atsamc21e/src/wdt/clear.rs new file mode 100644 index 000000000000..61ee21f3246a --- /dev/null +++ b/pac/atsamc21e/src/wdt/clear.rs @@ -0,0 +1,85 @@ +#[doc = "Register `CLEAR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Watchdog Clear\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CLEAR_AW { + #[doc = "165: Clear Key"] + KEY = 165, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CLEAR_AW) -> Self { + variant as _ + } +} +#[doc = "Field `CLEAR` writer - Watchdog Clear"] +pub struct CLEAR_W<'a> { + w: &'a mut W, +} +impl<'a> CLEAR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CLEAR_AW) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Clear Key"] + #[inline(always)] + pub fn key(self) -> &'a mut W { + self.variant(CLEAR_AW::KEY) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl W { + #[doc = "Bits 0:7 - Watchdog Clear"] + #[inline(always)] + pub fn clear(&mut self) -> CLEAR_W { + CLEAR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Clear\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clear](index.html) module"] +pub struct CLEAR_SPEC; +impl crate::RegisterSpec for CLEAR_SPEC { + type Ux = u8; +} +#[doc = "`write(|w| ..)` method takes [clear::W](W) writer structure"] +impl crate::Writable for CLEAR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CLEAR to value 0"] +impl crate::Resettable for CLEAR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/wdt/config.rs b/pac/atsamc21e/src/wdt/config.rs new file mode 100644 index 000000000000..c90f062b01f0 --- /dev/null +++ b/pac/atsamc21e/src/wdt/config.rs @@ -0,0 +1,498 @@ +#[doc = "Register `CONFIG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CONFIG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Time-Out Period\n\nValue on reset: 11"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PER_A { + #[doc = "0: 8 clock cycles"] + CYC8 = 0, + #[doc = "1: 16 clock cycles"] + CYC16 = 1, + #[doc = "2: 32 clock cycles"] + CYC32 = 2, + #[doc = "3: 64 clock cycles"] + CYC64 = 3, + #[doc = "4: 128 clock cycles"] + CYC128 = 4, + #[doc = "5: 256 clock cycles"] + CYC256 = 5, + #[doc = "6: 512 clock cycles"] + CYC512 = 6, + #[doc = "7: 1024 clock cycles"] + CYC1024 = 7, + #[doc = "8: 2048 clock cycles"] + CYC2048 = 8, + #[doc = "9: 4096 clock cycles"] + CYC4096 = 9, + #[doc = "10: 8192 clock cycles"] + CYC8192 = 10, + #[doc = "11: 16384 clock cycles"] + CYC16384 = 11, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PER` reader - Time-Out Period"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PER_A::CYC8), + 1 => Some(PER_A::CYC16), + 2 => Some(PER_A::CYC32), + 3 => Some(PER_A::CYC64), + 4 => Some(PER_A::CYC128), + 5 => Some(PER_A::CYC256), + 6 => Some(PER_A::CYC512), + 7 => Some(PER_A::CYC1024), + 8 => Some(PER_A::CYC2048), + 9 => Some(PER_A::CYC4096), + 10 => Some(PER_A::CYC8192), + 11 => Some(PER_A::CYC16384), + _ => None, + } + } + #[doc = "Checks if the value of the field is `CYC8`"] + #[inline(always)] + pub fn is_cyc8(&self) -> bool { + **self == PER_A::CYC8 + } + #[doc = "Checks if the value of the field is `CYC16`"] + #[inline(always)] + pub fn is_cyc16(&self) -> bool { + **self == PER_A::CYC16 + } + #[doc = "Checks if the value of the field is `CYC32`"] + #[inline(always)] + pub fn is_cyc32(&self) -> bool { + **self == PER_A::CYC32 + } + #[doc = "Checks if the value of the field is `CYC64`"] + #[inline(always)] + pub fn is_cyc64(&self) -> bool { + **self == PER_A::CYC64 + } + #[doc = "Checks if the value of the field is `CYC128`"] + #[inline(always)] + pub fn is_cyc128(&self) -> bool { + **self == PER_A::CYC128 + } + #[doc = "Checks if the value of the field is `CYC256`"] + #[inline(always)] + pub fn is_cyc256(&self) -> bool { + **self == PER_A::CYC256 + } + #[doc = "Checks if the value of the field is `CYC512`"] + #[inline(always)] + pub fn is_cyc512(&self) -> bool { + **self == PER_A::CYC512 + } + #[doc = "Checks if the value of the field is `CYC1024`"] + #[inline(always)] + pub fn is_cyc1024(&self) -> bool { + **self == PER_A::CYC1024 + } + #[doc = "Checks if the value of the field is `CYC2048`"] + #[inline(always)] + pub fn is_cyc2048(&self) -> bool { + **self == PER_A::CYC2048 + } + #[doc = "Checks if the value of the field is `CYC4096`"] + #[inline(always)] + pub fn is_cyc4096(&self) -> bool { + **self == PER_A::CYC4096 + } + #[doc = "Checks if the value of the field is `CYC8192`"] + #[inline(always)] + pub fn is_cyc8192(&self) -> bool { + **self == PER_A::CYC8192 + } + #[doc = "Checks if the value of the field is `CYC16384`"] + #[inline(always)] + pub fn is_cyc16384(&self) -> bool { + **self == PER_A::CYC16384 + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` writer - Time-Out Period"] +pub struct PER_W<'a> { + w: &'a mut W, +} +impl<'a> PER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PER_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8 clock cycles"] + #[inline(always)] + pub fn cyc8(self) -> &'a mut W { + self.variant(PER_A::CYC8) + } + #[doc = "16 clock cycles"] + #[inline(always)] + pub fn cyc16(self) -> &'a mut W { + self.variant(PER_A::CYC16) + } + #[doc = "32 clock cycles"] + #[inline(always)] + pub fn cyc32(self) -> &'a mut W { + self.variant(PER_A::CYC32) + } + #[doc = "64 clock cycles"] + #[inline(always)] + pub fn cyc64(self) -> &'a mut W { + self.variant(PER_A::CYC64) + } + #[doc = "128 clock cycles"] + #[inline(always)] + pub fn cyc128(self) -> &'a mut W { + self.variant(PER_A::CYC128) + } + #[doc = "256 clock cycles"] + #[inline(always)] + pub fn cyc256(self) -> &'a mut W { + self.variant(PER_A::CYC256) + } + #[doc = "512 clock cycles"] + #[inline(always)] + pub fn cyc512(self) -> &'a mut W { + self.variant(PER_A::CYC512) + } + #[doc = "1024 clock cycles"] + #[inline(always)] + pub fn cyc1024(self) -> &'a mut W { + self.variant(PER_A::CYC1024) + } + #[doc = "2048 clock cycles"] + #[inline(always)] + pub fn cyc2048(self) -> &'a mut W { + self.variant(PER_A::CYC2048) + } + #[doc = "4096 clock cycles"] + #[inline(always)] + pub fn cyc4096(self) -> &'a mut W { + self.variant(PER_A::CYC4096) + } + #[doc = "8192 clock cycles"] + #[inline(always)] + pub fn cyc8192(self) -> &'a mut W { + self.variant(PER_A::CYC8192) + } + #[doc = "16384 clock cycles"] + #[inline(always)] + pub fn cyc16384(self) -> &'a mut W { + self.variant(PER_A::CYC16384) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +#[doc = "Window Mode Time-Out Period\n\nValue on reset: 11"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WINDOW_A { + #[doc = "0: 8 clock cycles"] + CYC8 = 0, + #[doc = "1: 16 clock cycles"] + CYC16 = 1, + #[doc = "2: 32 clock cycles"] + CYC32 = 2, + #[doc = "3: 64 clock cycles"] + CYC64 = 3, + #[doc = "4: 128 clock cycles"] + CYC128 = 4, + #[doc = "5: 256 clock cycles"] + CYC256 = 5, + #[doc = "6: 512 clock cycles"] + CYC512 = 6, + #[doc = "7: 1024 clock cycles"] + CYC1024 = 7, + #[doc = "8: 2048 clock cycles"] + CYC2048 = 8, + #[doc = "9: 4096 clock cycles"] + CYC4096 = 9, + #[doc = "10: 8192 clock cycles"] + CYC8192 = 10, + #[doc = "11: 16384 clock cycles"] + CYC16384 = 11, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WINDOW_A) -> Self { + variant as _ + } +} +#[doc = "Field `WINDOW` reader - Window Mode Time-Out Period"] +pub struct WINDOW_R(crate::FieldReader); +impl WINDOW_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WINDOW_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(WINDOW_A::CYC8), + 1 => Some(WINDOW_A::CYC16), + 2 => Some(WINDOW_A::CYC32), + 3 => Some(WINDOW_A::CYC64), + 4 => Some(WINDOW_A::CYC128), + 5 => Some(WINDOW_A::CYC256), + 6 => Some(WINDOW_A::CYC512), + 7 => Some(WINDOW_A::CYC1024), + 8 => Some(WINDOW_A::CYC2048), + 9 => Some(WINDOW_A::CYC4096), + 10 => Some(WINDOW_A::CYC8192), + 11 => Some(WINDOW_A::CYC16384), + _ => None, + } + } + #[doc = "Checks if the value of the field is `CYC8`"] + #[inline(always)] + pub fn is_cyc8(&self) -> bool { + **self == WINDOW_A::CYC8 + } + #[doc = "Checks if the value of the field is `CYC16`"] + #[inline(always)] + pub fn is_cyc16(&self) -> bool { + **self == WINDOW_A::CYC16 + } + #[doc = "Checks if the value of the field is `CYC32`"] + #[inline(always)] + pub fn is_cyc32(&self) -> bool { + **self == WINDOW_A::CYC32 + } + #[doc = "Checks if the value of the field is `CYC64`"] + #[inline(always)] + pub fn is_cyc64(&self) -> bool { + **self == WINDOW_A::CYC64 + } + #[doc = "Checks if the value of the field is `CYC128`"] + #[inline(always)] + pub fn is_cyc128(&self) -> bool { + **self == WINDOW_A::CYC128 + } + #[doc = "Checks if the value of the field is `CYC256`"] + #[inline(always)] + pub fn is_cyc256(&self) -> bool { + **self == WINDOW_A::CYC256 + } + #[doc = "Checks if the value of the field is `CYC512`"] + #[inline(always)] + pub fn is_cyc512(&self) -> bool { + **self == WINDOW_A::CYC512 + } + #[doc = "Checks if the value of the field is `CYC1024`"] + #[inline(always)] + pub fn is_cyc1024(&self) -> bool { + **self == WINDOW_A::CYC1024 + } + #[doc = "Checks if the value of the field is `CYC2048`"] + #[inline(always)] + pub fn is_cyc2048(&self) -> bool { + **self == WINDOW_A::CYC2048 + } + #[doc = "Checks if the value of the field is `CYC4096`"] + #[inline(always)] + pub fn is_cyc4096(&self) -> bool { + **self == WINDOW_A::CYC4096 + } + #[doc = "Checks if the value of the field is `CYC8192`"] + #[inline(always)] + pub fn is_cyc8192(&self) -> bool { + **self == WINDOW_A::CYC8192 + } + #[doc = "Checks if the value of the field is `CYC16384`"] + #[inline(always)] + pub fn is_cyc16384(&self) -> bool { + **self == WINDOW_A::CYC16384 + } +} +impl core::ops::Deref for WINDOW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINDOW` writer - Window Mode Time-Out Period"] +pub struct WINDOW_W<'a> { + w: &'a mut W, +} +impl<'a> WINDOW_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WINDOW_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8 clock cycles"] + #[inline(always)] + pub fn cyc8(self) -> &'a mut W { + self.variant(WINDOW_A::CYC8) + } + #[doc = "16 clock cycles"] + #[inline(always)] + pub fn cyc16(self) -> &'a mut W { + self.variant(WINDOW_A::CYC16) + } + #[doc = "32 clock cycles"] + #[inline(always)] + pub fn cyc32(self) -> &'a mut W { + self.variant(WINDOW_A::CYC32) + } + #[doc = "64 clock cycles"] + #[inline(always)] + pub fn cyc64(self) -> &'a mut W { + self.variant(WINDOW_A::CYC64) + } + #[doc = "128 clock cycles"] + #[inline(always)] + pub fn cyc128(self) -> &'a mut W { + self.variant(WINDOW_A::CYC128) + } + #[doc = "256 clock cycles"] + #[inline(always)] + pub fn cyc256(self) -> &'a mut W { + self.variant(WINDOW_A::CYC256) + } + #[doc = "512 clock cycles"] + #[inline(always)] + pub fn cyc512(self) -> &'a mut W { + self.variant(WINDOW_A::CYC512) + } + #[doc = "1024 clock cycles"] + #[inline(always)] + pub fn cyc1024(self) -> &'a mut W { + self.variant(WINDOW_A::CYC1024) + } + #[doc = "2048 clock cycles"] + #[inline(always)] + pub fn cyc2048(self) -> &'a mut W { + self.variant(WINDOW_A::CYC2048) + } + #[doc = "4096 clock cycles"] + #[inline(always)] + pub fn cyc4096(self) -> &'a mut W { + self.variant(WINDOW_A::CYC4096) + } + #[doc = "8192 clock cycles"] + #[inline(always)] + pub fn cyc8192(self) -> &'a mut W { + self.variant(WINDOW_A::CYC8192) + } + #[doc = "16384 clock cycles"] + #[inline(always)] + pub fn cyc16384(self) -> &'a mut W { + self.variant(WINDOW_A::CYC16384) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 4)) | ((value as u8 & 0x0f) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Time-Out Period"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Window Mode Time-Out Period"] + #[inline(always)] + pub fn window(&self) -> WINDOW_R { + WINDOW_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Time-Out Period"] + #[inline(always)] + pub fn per(&mut self) -> PER_W { + PER_W { w: self } + } + #[doc = "Bits 4:7 - Window Mode Time-Out Period"] + #[inline(always)] + pub fn window(&mut self) -> WINDOW_W { + WINDOW_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [config](index.html) module"] +pub struct CONFIG_SPEC; +impl crate::RegisterSpec for CONFIG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [config::R](R) reader structure"] +impl crate::Readable for CONFIG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [config::W](W) writer structure"] +impl crate::Writable for CONFIG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CONFIG to value 0xbb"] +impl crate::Resettable for CONFIG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xbb + } +} diff --git a/pac/atsamc21e/src/wdt/ctrla.rs b/pac/atsamc21e/src/wdt/ctrla.rs new file mode 100644 index 000000000000..895169d36aeb --- /dev/null +++ b/pac/atsamc21e/src/wdt/ctrla.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WEN` reader - Watchdog Timer Window Mode Enable"] +pub struct WEN_R(crate::FieldReader); +impl WEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WEN` writer - Watchdog Timer Window Mode Enable"] +pub struct WEN_W<'a> { + w: &'a mut W, +} +impl<'a> WEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `ALWAYSON` reader - Always-On"] +pub struct ALWAYSON_R(crate::FieldReader); +impl ALWAYSON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALWAYSON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALWAYSON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALWAYSON` writer - Always-On"] +pub struct ALWAYSON_W<'a> { + w: &'a mut W, +} +impl<'a> ALWAYSON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Watchdog Timer Window Mode Enable"] + #[inline(always)] + pub fn wen(&self) -> WEN_R { + WEN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 7 - Always-On"] + #[inline(always)] + pub fn alwayson(&self) -> ALWAYSON_R { + ALWAYSON_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - Watchdog Timer Window Mode Enable"] + #[inline(always)] + pub fn wen(&mut self) -> WEN_W { + WEN_W { w: self } + } + #[doc = "Bit 7 - Always-On"] + #[inline(always)] + pub fn alwayson(&mut self) -> ALWAYSON_W { + ALWAYSON_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/wdt/ewctrl.rs b/pac/atsamc21e/src/wdt/ewctrl.rs new file mode 100644 index 000000000000..94542e9897a9 --- /dev/null +++ b/pac/atsamc21e/src/wdt/ewctrl.rs @@ -0,0 +1,282 @@ +#[doc = "Register `EWCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EWCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Early Warning Interrupt Time Offset\n\nValue on reset: 11"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EWOFFSET_A { + #[doc = "0: 8 clock cycles"] + CYC8 = 0, + #[doc = "1: 16 clock cycles"] + CYC16 = 1, + #[doc = "2: 32 clock cycles"] + CYC32 = 2, + #[doc = "3: 64 clock cycles"] + CYC64 = 3, + #[doc = "4: 128 clock cycles"] + CYC128 = 4, + #[doc = "5: 256 clock cycles"] + CYC256 = 5, + #[doc = "6: 512 clock cycles"] + CYC512 = 6, + #[doc = "7: 1024 clock cycles"] + CYC1024 = 7, + #[doc = "8: 2048 clock cycles"] + CYC2048 = 8, + #[doc = "9: 4096 clock cycles"] + CYC4096 = 9, + #[doc = "10: 8192 clock cycles"] + CYC8192 = 10, + #[doc = "11: 16384 clock cycles"] + CYC16384 = 11, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EWOFFSET_A) -> Self { + variant as _ + } +} +#[doc = "Field `EWOFFSET` reader - Early Warning Interrupt Time Offset"] +pub struct EWOFFSET_R(crate::FieldReader); +impl EWOFFSET_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EWOFFSET_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(EWOFFSET_A::CYC8), + 1 => Some(EWOFFSET_A::CYC16), + 2 => Some(EWOFFSET_A::CYC32), + 3 => Some(EWOFFSET_A::CYC64), + 4 => Some(EWOFFSET_A::CYC128), + 5 => Some(EWOFFSET_A::CYC256), + 6 => Some(EWOFFSET_A::CYC512), + 7 => Some(EWOFFSET_A::CYC1024), + 8 => Some(EWOFFSET_A::CYC2048), + 9 => Some(EWOFFSET_A::CYC4096), + 10 => Some(EWOFFSET_A::CYC8192), + 11 => Some(EWOFFSET_A::CYC16384), + _ => None, + } + } + #[doc = "Checks if the value of the field is `CYC8`"] + #[inline(always)] + pub fn is_cyc8(&self) -> bool { + **self == EWOFFSET_A::CYC8 + } + #[doc = "Checks if the value of the field is `CYC16`"] + #[inline(always)] + pub fn is_cyc16(&self) -> bool { + **self == EWOFFSET_A::CYC16 + } + #[doc = "Checks if the value of the field is `CYC32`"] + #[inline(always)] + pub fn is_cyc32(&self) -> bool { + **self == EWOFFSET_A::CYC32 + } + #[doc = "Checks if the value of the field is `CYC64`"] + #[inline(always)] + pub fn is_cyc64(&self) -> bool { + **self == EWOFFSET_A::CYC64 + } + #[doc = "Checks if the value of the field is `CYC128`"] + #[inline(always)] + pub fn is_cyc128(&self) -> bool { + **self == EWOFFSET_A::CYC128 + } + #[doc = "Checks if the value of the field is `CYC256`"] + #[inline(always)] + pub fn is_cyc256(&self) -> bool { + **self == EWOFFSET_A::CYC256 + } + #[doc = "Checks if the value of the field is `CYC512`"] + #[inline(always)] + pub fn is_cyc512(&self) -> bool { + **self == EWOFFSET_A::CYC512 + } + #[doc = "Checks if the value of the field is `CYC1024`"] + #[inline(always)] + pub fn is_cyc1024(&self) -> bool { + **self == EWOFFSET_A::CYC1024 + } + #[doc = "Checks if the value of the field is `CYC2048`"] + #[inline(always)] + pub fn is_cyc2048(&self) -> bool { + **self == EWOFFSET_A::CYC2048 + } + #[doc = "Checks if the value of the field is `CYC4096`"] + #[inline(always)] + pub fn is_cyc4096(&self) -> bool { + **self == EWOFFSET_A::CYC4096 + } + #[doc = "Checks if the value of the field is `CYC8192`"] + #[inline(always)] + pub fn is_cyc8192(&self) -> bool { + **self == EWOFFSET_A::CYC8192 + } + #[doc = "Checks if the value of the field is `CYC16384`"] + #[inline(always)] + pub fn is_cyc16384(&self) -> bool { + **self == EWOFFSET_A::CYC16384 + } +} +impl core::ops::Deref for EWOFFSET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EWOFFSET` writer - Early Warning Interrupt Time Offset"] +pub struct EWOFFSET_W<'a> { + w: &'a mut W, +} +impl<'a> EWOFFSET_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EWOFFSET_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8 clock cycles"] + #[inline(always)] + pub fn cyc8(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC8) + } + #[doc = "16 clock cycles"] + #[inline(always)] + pub fn cyc16(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC16) + } + #[doc = "32 clock cycles"] + #[inline(always)] + pub fn cyc32(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC32) + } + #[doc = "64 clock cycles"] + #[inline(always)] + pub fn cyc64(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC64) + } + #[doc = "128 clock cycles"] + #[inline(always)] + pub fn cyc128(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC128) + } + #[doc = "256 clock cycles"] + #[inline(always)] + pub fn cyc256(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC256) + } + #[doc = "512 clock cycles"] + #[inline(always)] + pub fn cyc512(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC512) + } + #[doc = "1024 clock cycles"] + #[inline(always)] + pub fn cyc1024(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC1024) + } + #[doc = "2048 clock cycles"] + #[inline(always)] + pub fn cyc2048(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC2048) + } + #[doc = "4096 clock cycles"] + #[inline(always)] + pub fn cyc4096(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC4096) + } + #[doc = "8192 clock cycles"] + #[inline(always)] + pub fn cyc8192(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC8192) + } + #[doc = "16384 clock cycles"] + #[inline(always)] + pub fn cyc16384(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC16384) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Early Warning Interrupt Time Offset"] + #[inline(always)] + pub fn ewoffset(&self) -> EWOFFSET_R { + EWOFFSET_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Early Warning Interrupt Time Offset"] + #[inline(always)] + pub fn ewoffset(&mut self) -> EWOFFSET_W { + EWOFFSET_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Early Warning Interrupt Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ewctrl](index.html) module"] +pub struct EWCTRL_SPEC; +impl crate::RegisterSpec for EWCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ewctrl::R](R) reader structure"] +impl crate::Readable for EWCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ewctrl::W](W) writer structure"] +impl crate::Writable for EWCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EWCTRL to value 0x0b"] +impl crate::Resettable for EWCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0b + } +} diff --git a/pac/atsamc21e/src/wdt/intenclr.rs b/pac/atsamc21e/src/wdt/intenclr.rs new file mode 100644 index 000000000000..ed4021f96cce --- /dev/null +++ b/pac/atsamc21e/src/wdt/intenclr.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EW` reader - Early Warning Interrupt Enable"] +pub struct EW_R(crate::FieldReader); +impl EW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EW` writer - Early Warning Interrupt Enable"] +pub struct EW_W<'a> { + w: &'a mut W, +} +impl<'a> EW_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Early Warning Interrupt Enable"] + #[inline(always)] + pub fn ew(&self) -> EW_R { + EW_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Early Warning Interrupt Enable"] + #[inline(always)] + pub fn ew(&mut self) -> EW_W { + EW_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/wdt/intenset.rs b/pac/atsamc21e/src/wdt/intenset.rs new file mode 100644 index 000000000000..5a0928ff0532 --- /dev/null +++ b/pac/atsamc21e/src/wdt/intenset.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EW` reader - Early Warning Interrupt Enable"] +pub struct EW_R(crate::FieldReader); +impl EW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EW` writer - Early Warning Interrupt Enable"] +pub struct EW_W<'a> { + w: &'a mut W, +} +impl<'a> EW_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Early Warning Interrupt Enable"] + #[inline(always)] + pub fn ew(&self) -> EW_R { + EW_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Early Warning Interrupt Enable"] + #[inline(always)] + pub fn ew(&mut self) -> EW_W { + EW_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/wdt/intflag.rs b/pac/atsamc21e/src/wdt/intflag.rs new file mode 100644 index 000000000000..f2c9b858a199 --- /dev/null +++ b/pac/atsamc21e/src/wdt/intflag.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EW` reader - Early Warning"] +pub struct EW_R(crate::FieldReader); +impl EW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EW` writer - Early Warning"] +pub struct EW_W<'a> { + w: &'a mut W, +} +impl<'a> EW_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Early Warning"] + #[inline(always)] + pub fn ew(&self) -> EW_R { + EW_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Early Warning"] + #[inline(always)] + pub fn ew(&mut self) -> EW_W { + EW_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21e/src/wdt/syncbusy.rs b/pac/atsamc21e/src/wdt/syncbusy.rs new file mode 100644 index 000000000000..a3ecf7fbdb8a --- /dev/null +++ b/pac/atsamc21e/src/wdt/syncbusy.rs @@ -0,0 +1,113 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `ENABLE` reader - Enable Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WEN` reader - Window Enable Busy"] +pub struct WEN_R(crate::FieldReader); +impl WEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALWAYSON` reader - Always-On Busy"] +pub struct ALWAYSON_R(crate::FieldReader); +impl ALWAYSON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALWAYSON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALWAYSON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLEAR` reader - Clear Busy"] +pub struct CLEAR_R(crate::FieldReader); +impl CLEAR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLEAR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLEAR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 1 - Enable Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Window Enable Busy"] + #[inline(always)] + pub fn wen(&self) -> WEN_R { + WEN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Always-On Busy"] + #[inline(always)] + pub fn alwayson(&self) -> ALWAYSON_R { + ALWAYSON_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Clear Busy"] + #[inline(always)] + pub fn clear(&self) -> CLEAR_R { + CLEAR_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +#[doc = "Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/CHANGELOG.md b/pac/atsamc21g/CHANGELOG.md new file mode 100644 index 000000000000..e28d85f63b31 --- /dev/null +++ b/pac/atsamc21g/CHANGELOG.md @@ -0,0 +1,6 @@ +# Unreleased + +- Initial version +--- + +Changelog tracking started at v0.0.1 diff --git a/pac/atsamc21g/Cargo.toml b/pac/atsamc21g/Cargo.toml new file mode 100644 index 000000000000..2892770767c3 --- /dev/null +++ b/pac/atsamc21g/Cargo.toml @@ -0,0 +1,22 @@ +[package] +name = "atsamc21g" +description = "Peripheral access API for ATSAMC21G microcontrollers (generated using svd2rust)" +version = "0.0.1" +authors = ["Jeremy Boynes "] +keywords = ["no-std", "arm", "cortex-m"] +categories = ["embedded", "hardware-support", "no-std"] +license = "MIT OR Apache-2.0" +repository = "https://github.com/atsamd-rs/atsamd" +readme = "README.md" +edition = "2021" + +[dependencies] +cortex-m = "0.7" +vcell = "0.1" + +[dependencies.cortex-m-rt] +version = "0.7" +optional = true + +[features] +rt = ["cortex-m-rt/device"] diff --git a/pac/atsamc21g/README.md b/pac/atsamc21g/README.md new file mode 100644 index 000000000000..bd6b34db86e4 --- /dev/null +++ b/pac/atsamc21g/README.md @@ -0,0 +1,26 @@ +# ATSAMC21G + +A peripheral access crate for the ATSAMC20E chip from Microchip (née Atmel) for Rust Embedded projects. + +[![Build Status](https://travis-ci.org/atsamd-rs/atsamd.svg?branch=master)](https://travis-ci.org/atsamd-rs/atsamd) +[![Crates.io](https://img.shields.io/crates/v/atsamc21g.svg)](https://crates.io/crates/atsamc21g) + +## [Documentation](https://docs.rs/atsamc21g) + +This source was automatically generated using `svd2rust`, split into smaller pieces using `form` and formatted via `rustfmt`. + +## License + +Licensed under either of: + +- Apache License, Version 2.0 ([LICENSE-APACHE](https://github.com/atsamd-rs/atsamd/blob/master/LICENSE-APACHE) or + http://www.apache.org/licenses/LICENSE-2.0) +- MIT license ([LICENSE-MIT](https://github.com/atsamd-rs/atsamd/blob/master/LICENSE-MIT) or http://opensource.org/licenses/MIT) + +at your option. + +### Contribution + +Unless you explicitly state otherwise, any contribution intentionally submitted +for inclusion in the work by you, as defined in the Apache-2.0 license, shall +be dual licensed as above, without any additional terms or conditions. diff --git a/pac/atsamc21g/build.rs b/pac/atsamc21g/build.rs new file mode 100644 index 000000000000..597923f50892 --- /dev/null +++ b/pac/atsamc21g/build.rs @@ -0,0 +1,16 @@ +use std::env; +use std::fs::File; +use std::io::Write; +use std::path::PathBuf; +fn main() { + if env::var_os("CARGO_FEATURE_RT").is_some() { + let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap()); + File::create(out.join("device.x")) + .unwrap() + .write_all(include_bytes!("device.x")) + .unwrap(); + println!("cargo:rustc-link-search={}", out.display()); + println!("cargo:rerun-if-changed=device.x"); + } + println!("cargo:rerun-if-changed=build.rs"); +} diff --git a/pac/atsamc21g/device.x b/pac/atsamc21g/device.x new file mode 100644 index 000000000000..54baa7b6516c --- /dev/null +++ b/pac/atsamc21g/device.x @@ -0,0 +1,31 @@ +PROVIDE(WDT = DefaultHandler); +PROVIDE(RTC = DefaultHandler); +PROVIDE(EIC = DefaultHandler); +PROVIDE(FREQM = DefaultHandler); +PROVIDE(TSENS = DefaultHandler); +PROVIDE(NVMCTRL = DefaultHandler); +PROVIDE(DMAC = DefaultHandler); +PROVIDE(EVSYS = DefaultHandler); +PROVIDE(SERCOM0 = DefaultHandler); +PROVIDE(SERCOM1 = DefaultHandler); +PROVIDE(SERCOM2 = DefaultHandler); +PROVIDE(SERCOM3 = DefaultHandler); +PROVIDE(SERCOM4 = DefaultHandler); +PROVIDE(SERCOM5 = DefaultHandler); +PROVIDE(CAN0 = DefaultHandler); +PROVIDE(CAN1 = DefaultHandler); +PROVIDE(TCC0 = DefaultHandler); +PROVIDE(TCC1 = DefaultHandler); +PROVIDE(TCC2 = DefaultHandler); +PROVIDE(TC0 = DefaultHandler); +PROVIDE(TC1 = DefaultHandler); +PROVIDE(TC2 = DefaultHandler); +PROVIDE(TC3 = DefaultHandler); +PROVIDE(TC4 = DefaultHandler); +PROVIDE(ADC0 = DefaultHandler); +PROVIDE(ADC1 = DefaultHandler); +PROVIDE(AC = DefaultHandler); +PROVIDE(DAC = DefaultHandler); +PROVIDE(SDADC = DefaultHandler); +PROVIDE(PTC = DefaultHandler); + diff --git a/pac/atsamc21g/src/ac.rs b/pac/atsamc21g/src/ac.rs new file mode 100644 index 000000000000..b66620475572 --- /dev/null +++ b/pac/atsamc21g/src/ac.rs @@ -0,0 +1,83 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + #[doc = "0x01 - Control B"] + pub ctrlb: crate::Reg, + #[doc = "0x02 - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x04 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x05 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x06 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x07 - Status A"] + pub statusa: crate::Reg, + #[doc = "0x08 - Status B"] + pub statusb: crate::Reg, + #[doc = "0x09 - Debug Control"] + pub dbgctrl: crate::Reg, + #[doc = "0x0a - Window Control"] + pub winctrl: crate::Reg, + _reserved10: [u8; 0x01], + #[doc = "0x0c - Scaler n"] + pub scaler: [crate::Reg; 4], + #[doc = "0x10..0x20 - Comparator Control n"] + pub compctrl: [crate::Reg; 4], + #[doc = "0x20 - Synchronization Busy"] + pub syncbusy: crate::Reg, +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "Control B"] +pub mod ctrlb; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUSA register accessor: an alias for `Reg`"] +pub type STATUSA = crate::Reg; +#[doc = "Status A"] +pub mod statusa; +#[doc = "STATUSB register accessor: an alias for `Reg`"] +pub type STATUSB = crate::Reg; +#[doc = "Status B"] +pub mod statusb; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "WINCTRL register accessor: an alias for `Reg`"] +pub type WINCTRL = crate::Reg; +#[doc = "Window Control"] +pub mod winctrl; +#[doc = "SCALER register accessor: an alias for `Reg`"] +pub type SCALER = crate::Reg; +#[doc = "Scaler n"] +pub mod scaler; +#[doc = "COMPCTRL register accessor: an alias for `Reg`"] +pub type COMPCTRL = crate::Reg; +#[doc = "Comparator Control n"] +pub mod compctrl; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Busy"] +pub mod syncbusy; diff --git a/pac/atsamc21g/src/ac/compctrl.rs b/pac/atsamc21g/src/ac/compctrl.rs new file mode 100644 index 000000000000..791525fd7407 --- /dev/null +++ b/pac/atsamc21g/src/ac/compctrl.rs @@ -0,0 +1,987 @@ +#[doc = "Register `COMPCTRL[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COMPCTRL[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SINGLE` reader - Single-Shot Mode"] +pub struct SINGLE_R(crate::FieldReader); +impl SINGLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SINGLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SINGLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SINGLE` writer - Single-Shot Mode"] +pub struct SINGLE_W<'a> { + w: &'a mut W, +} +impl<'a> SINGLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Interrupt Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum INTSEL_A { + #[doc = "0: Interrupt on comparator output toggle"] + TOGGLE = 0, + #[doc = "1: Interrupt on comparator output rising"] + RISING = 1, + #[doc = "2: Interrupt on comparator output falling"] + FALLING = 2, + #[doc = "3: Interrupt on end of comparison (single-shot mode only)"] + EOC = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: INTSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `INTSEL` reader - Interrupt Selection"] +pub struct INTSEL_R(crate::FieldReader); +impl INTSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + INTSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INTSEL_A { + match self.bits { + 0 => INTSEL_A::TOGGLE, + 1 => INTSEL_A::RISING, + 2 => INTSEL_A::FALLING, + 3 => INTSEL_A::EOC, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `TOGGLE`"] + #[inline(always)] + pub fn is_toggle(&self) -> bool { + **self == INTSEL_A::TOGGLE + } + #[doc = "Checks if the value of the field is `RISING`"] + #[inline(always)] + pub fn is_rising(&self) -> bool { + **self == INTSEL_A::RISING + } + #[doc = "Checks if the value of the field is `FALLING`"] + #[inline(always)] + pub fn is_falling(&self) -> bool { + **self == INTSEL_A::FALLING + } + #[doc = "Checks if the value of the field is `EOC`"] + #[inline(always)] + pub fn is_eoc(&self) -> bool { + **self == INTSEL_A::EOC + } +} +impl core::ops::Deref for INTSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INTSEL` writer - Interrupt Selection"] +pub struct INTSEL_W<'a> { + w: &'a mut W, +} +impl<'a> INTSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: INTSEL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Interrupt on comparator output toggle"] + #[inline(always)] + pub fn toggle(self) -> &'a mut W { + self.variant(INTSEL_A::TOGGLE) + } + #[doc = "Interrupt on comparator output rising"] + #[inline(always)] + pub fn rising(self) -> &'a mut W { + self.variant(INTSEL_A::RISING) + } + #[doc = "Interrupt on comparator output falling"] + #[inline(always)] + pub fn falling(self) -> &'a mut W { + self.variant(INTSEL_A::FALLING) + } + #[doc = "Interrupt on end of comparison (single-shot mode only)"] + #[inline(always)] + pub fn eoc(self) -> &'a mut W { + self.variant(INTSEL_A::EOC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 3)) | ((value as u32 & 0x03) << 3); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Negative Input Mux Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MUXNEG_A { + #[doc = "0: I/O pin 0"] + PIN0 = 0, + #[doc = "1: I/O pin 1"] + PIN1 = 1, + #[doc = "2: I/O pin 2"] + PIN2 = 2, + #[doc = "3: I/O pin 3"] + PIN3 = 3, + #[doc = "4: Ground"] + GND = 4, + #[doc = "5: VDD scaler"] + VSCALE = 5, + #[doc = "6: Internal bandgap voltage"] + BANDGAP = 6, + #[doc = "7: DAC output"] + DAC = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MUXNEG_A) -> Self { + variant as _ + } +} +#[doc = "Field `MUXNEG` reader - Negative Input Mux Selection"] +pub struct MUXNEG_R(crate::FieldReader); +impl MUXNEG_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MUXNEG_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> MUXNEG_A { + match self.bits { + 0 => MUXNEG_A::PIN0, + 1 => MUXNEG_A::PIN1, + 2 => MUXNEG_A::PIN2, + 3 => MUXNEG_A::PIN3, + 4 => MUXNEG_A::GND, + 5 => MUXNEG_A::VSCALE, + 6 => MUXNEG_A::BANDGAP, + 7 => MUXNEG_A::DAC, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `PIN0`"] + #[inline(always)] + pub fn is_pin0(&self) -> bool { + **self == MUXNEG_A::PIN0 + } + #[doc = "Checks if the value of the field is `PIN1`"] + #[inline(always)] + pub fn is_pin1(&self) -> bool { + **self == MUXNEG_A::PIN1 + } + #[doc = "Checks if the value of the field is `PIN2`"] + #[inline(always)] + pub fn is_pin2(&self) -> bool { + **self == MUXNEG_A::PIN2 + } + #[doc = "Checks if the value of the field is `PIN3`"] + #[inline(always)] + pub fn is_pin3(&self) -> bool { + **self == MUXNEG_A::PIN3 + } + #[doc = "Checks if the value of the field is `GND`"] + #[inline(always)] + pub fn is_gnd(&self) -> bool { + **self == MUXNEG_A::GND + } + #[doc = "Checks if the value of the field is `VSCALE`"] + #[inline(always)] + pub fn is_vscale(&self) -> bool { + **self == MUXNEG_A::VSCALE + } + #[doc = "Checks if the value of the field is `BANDGAP`"] + #[inline(always)] + pub fn is_bandgap(&self) -> bool { + **self == MUXNEG_A::BANDGAP + } + #[doc = "Checks if the value of the field is `DAC`"] + #[inline(always)] + pub fn is_dac(&self) -> bool { + **self == MUXNEG_A::DAC + } +} +impl core::ops::Deref for MUXNEG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MUXNEG` writer - Negative Input Mux Selection"] +pub struct MUXNEG_W<'a> { + w: &'a mut W, +} +impl<'a> MUXNEG_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MUXNEG_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "I/O pin 0"] + #[inline(always)] + pub fn pin0(self) -> &'a mut W { + self.variant(MUXNEG_A::PIN0) + } + #[doc = "I/O pin 1"] + #[inline(always)] + pub fn pin1(self) -> &'a mut W { + self.variant(MUXNEG_A::PIN1) + } + #[doc = "I/O pin 2"] + #[inline(always)] + pub fn pin2(self) -> &'a mut W { + self.variant(MUXNEG_A::PIN2) + } + #[doc = "I/O pin 3"] + #[inline(always)] + pub fn pin3(self) -> &'a mut W { + self.variant(MUXNEG_A::PIN3) + } + #[doc = "Ground"] + #[inline(always)] + pub fn gnd(self) -> &'a mut W { + self.variant(MUXNEG_A::GND) + } + #[doc = "VDD scaler"] + #[inline(always)] + pub fn vscale(self) -> &'a mut W { + self.variant(MUXNEG_A::VSCALE) + } + #[doc = "Internal bandgap voltage"] + #[inline(always)] + pub fn bandgap(self) -> &'a mut W { + self.variant(MUXNEG_A::BANDGAP) + } + #[doc = "DAC output"] + #[inline(always)] + pub fn dac(self) -> &'a mut W { + self.variant(MUXNEG_A::DAC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +#[doc = "Positive Input Mux Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MUXPOS_A { + #[doc = "0: I/O pin 0"] + PIN0 = 0, + #[doc = "1: I/O pin 1"] + PIN1 = 1, + #[doc = "2: I/O pin 2"] + PIN2 = 2, + #[doc = "3: I/O pin 3"] + PIN3 = 3, + #[doc = "4: VDD Scaler"] + VSCALE = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MUXPOS_A) -> Self { + variant as _ + } +} +#[doc = "Field `MUXPOS` reader - Positive Input Mux Selection"] +pub struct MUXPOS_R(crate::FieldReader); +impl MUXPOS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MUXPOS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MUXPOS_A::PIN0), + 1 => Some(MUXPOS_A::PIN1), + 2 => Some(MUXPOS_A::PIN2), + 3 => Some(MUXPOS_A::PIN3), + 4 => Some(MUXPOS_A::VSCALE), + _ => None, + } + } + #[doc = "Checks if the value of the field is `PIN0`"] + #[inline(always)] + pub fn is_pin0(&self) -> bool { + **self == MUXPOS_A::PIN0 + } + #[doc = "Checks if the value of the field is `PIN1`"] + #[inline(always)] + pub fn is_pin1(&self) -> bool { + **self == MUXPOS_A::PIN1 + } + #[doc = "Checks if the value of the field is `PIN2`"] + #[inline(always)] + pub fn is_pin2(&self) -> bool { + **self == MUXPOS_A::PIN2 + } + #[doc = "Checks if the value of the field is `PIN3`"] + #[inline(always)] + pub fn is_pin3(&self) -> bool { + **self == MUXPOS_A::PIN3 + } + #[doc = "Checks if the value of the field is `VSCALE`"] + #[inline(always)] + pub fn is_vscale(&self) -> bool { + **self == MUXPOS_A::VSCALE + } +} +impl core::ops::Deref for MUXPOS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MUXPOS` writer - Positive Input Mux Selection"] +pub struct MUXPOS_W<'a> { + w: &'a mut W, +} +impl<'a> MUXPOS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MUXPOS_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "I/O pin 0"] + #[inline(always)] + pub fn pin0(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN0) + } + #[doc = "I/O pin 1"] + #[inline(always)] + pub fn pin1(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN1) + } + #[doc = "I/O pin 2"] + #[inline(always)] + pub fn pin2(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN2) + } + #[doc = "I/O pin 3"] + #[inline(always)] + pub fn pin3(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN3) + } + #[doc = "VDD Scaler"] + #[inline(always)] + pub fn vscale(self) -> &'a mut W { + self.variant(MUXPOS_A::VSCALE) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 12)) | ((value as u32 & 0x07) << 12); + self.w + } +} +#[doc = "Field `SWAP` reader - Swap Inputs and Invert"] +pub struct SWAP_R(crate::FieldReader); +impl SWAP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWAP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWAP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWAP` writer - Swap Inputs and Invert"] +pub struct SWAP_W<'a> { + w: &'a mut W, +} +impl<'a> SWAP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Speed Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SPEED_A { + #[doc = "0: Low speed"] + LOW = 0, + #[doc = "3: High speed"] + HIGH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SPEED_A) -> Self { + variant as _ + } +} +#[doc = "Field `SPEED` reader - Speed Selection"] +pub struct SPEED_R(crate::FieldReader); +impl SPEED_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SPEED_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SPEED_A::LOW), + 3 => Some(SPEED_A::HIGH), + _ => None, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SPEED_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SPEED_A::HIGH + } +} +impl core::ops::Deref for SPEED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SPEED` writer - Speed Selection"] +pub struct SPEED_W<'a> { + w: &'a mut W, +} +impl<'a> SPEED_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SPEED_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Low speed"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SPEED_A::LOW) + } + #[doc = "High speed"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SPEED_A::HIGH) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Field `HYSTEN` reader - Hysteresis Enable"] +pub struct HYSTEN_R(crate::FieldReader); +impl HYSTEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HYSTEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HYSTEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HYSTEN` writer - Hysteresis Enable"] +pub struct HYSTEN_W<'a> { + w: &'a mut W, +} +impl<'a> HYSTEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Filter Length\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FLEN_A { + #[doc = "0: No filtering"] + OFF = 0, + #[doc = "1: 3-bit majority function (2 of 3)"] + MAJ3 = 1, + #[doc = "2: 5-bit majority function (3 of 5)"] + MAJ5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FLEN_A) -> Self { + variant as _ + } +} +#[doc = "Field `FLEN` reader - Filter Length"] +pub struct FLEN_R(crate::FieldReader); +impl FLEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FLEN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(FLEN_A::OFF), + 1 => Some(FLEN_A::MAJ3), + 2 => Some(FLEN_A::MAJ5), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == FLEN_A::OFF + } + #[doc = "Checks if the value of the field is `MAJ3`"] + #[inline(always)] + pub fn is_maj3(&self) -> bool { + **self == FLEN_A::MAJ3 + } + #[doc = "Checks if the value of the field is `MAJ5`"] + #[inline(always)] + pub fn is_maj5(&self) -> bool { + **self == FLEN_A::MAJ5 + } +} +impl core::ops::Deref for FLEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLEN` writer - Filter Length"] +pub struct FLEN_W<'a> { + w: &'a mut W, +} +impl<'a> FLEN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FLEN_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No filtering"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(FLEN_A::OFF) + } + #[doc = "3-bit majority function (2 of 3)"] + #[inline(always)] + pub fn maj3(self) -> &'a mut W { + self.variant(FLEN_A::MAJ3) + } + #[doc = "5-bit majority function (3 of 5)"] + #[inline(always)] + pub fn maj5(self) -> &'a mut W { + self.variant(FLEN_A::MAJ5) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 24)) | ((value as u32 & 0x07) << 24); + self.w + } +} +#[doc = "Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum OUT_A { + #[doc = "0: The output of COMPn is not routed to the COMPn I/O port"] + OFF = 0, + #[doc = "1: The asynchronous output of COMPn is routed to the COMPn I/O port"] + ASYNC = 1, + #[doc = "2: The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port"] + SYNC = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: OUT_A) -> Self { + variant as _ + } +} +#[doc = "Field `OUT` reader - Output"] +pub struct OUT_R(crate::FieldReader); +impl OUT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + OUT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(OUT_A::OFF), + 1 => Some(OUT_A::ASYNC), + 2 => Some(OUT_A::SYNC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == OUT_A::OFF + } + #[doc = "Checks if the value of the field is `ASYNC`"] + #[inline(always)] + pub fn is_async(&self) -> bool { + **self == OUT_A::ASYNC + } + #[doc = "Checks if the value of the field is `SYNC`"] + #[inline(always)] + pub fn is_sync(&self) -> bool { + **self == OUT_A::SYNC + } +} +impl core::ops::Deref for OUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OUT` writer - Output"] +pub struct OUT_W<'a> { + w: &'a mut W, +} +impl<'a> OUT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: OUT_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "The output of COMPn is not routed to the COMPn I/O port"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(OUT_A::OFF) + } + #[doc = "The asynchronous output of COMPn is routed to the COMPn I/O port"] + #[inline(always)] + pub fn async_(self) -> &'a mut W { + self.variant(OUT_A::ASYNC) + } + #[doc = "The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port"] + #[inline(always)] + pub fn sync(self) -> &'a mut W { + self.variant(OUT_A::SYNC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 28)) | ((value as u32 & 0x03) << 28); + self.w + } +} +impl R { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Single-Shot Mode"] + #[inline(always)] + pub fn single(&self) -> SINGLE_R { + SINGLE_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 3:4 - Interrupt Selection"] + #[inline(always)] + pub fn intsel(&self) -> INTSEL_R { + INTSEL_R::new(((self.bits >> 3) & 0x03) as u8) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Negative Input Mux Selection"] + #[inline(always)] + pub fn muxneg(&self) -> MUXNEG_R { + MUXNEG_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bits 12:14 - Positive Input Mux Selection"] + #[inline(always)] + pub fn muxpos(&self) -> MUXPOS_R { + MUXPOS_R::new(((self.bits >> 12) & 0x07) as u8) + } + #[doc = "Bit 15 - Swap Inputs and Invert"] + #[inline(always)] + pub fn swap(&self) -> SWAP_R { + SWAP_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:17 - Speed Selection"] + #[inline(always)] + pub fn speed(&self) -> SPEED_R { + SPEED_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bit 19 - Hysteresis Enable"] + #[inline(always)] + pub fn hysten(&self) -> HYSTEN_R { + HYSTEN_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bits 24:26 - Filter Length"] + #[inline(always)] + pub fn flen(&self) -> FLEN_R { + FLEN_R::new(((self.bits >> 24) & 0x07) as u8) + } + #[doc = "Bits 28:29 - Output"] + #[inline(always)] + pub fn out(&self) -> OUT_R { + OUT_R::new(((self.bits >> 28) & 0x03) as u8) + } +} +impl W { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - Single-Shot Mode"] + #[inline(always)] + pub fn single(&mut self) -> SINGLE_W { + SINGLE_W { w: self } + } + #[doc = "Bits 3:4 - Interrupt Selection"] + #[inline(always)] + pub fn intsel(&mut self) -> INTSEL_W { + INTSEL_W { w: self } + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bits 8:10 - Negative Input Mux Selection"] + #[inline(always)] + pub fn muxneg(&mut self) -> MUXNEG_W { + MUXNEG_W { w: self } + } + #[doc = "Bits 12:14 - Positive Input Mux Selection"] + #[inline(always)] + pub fn muxpos(&mut self) -> MUXPOS_W { + MUXPOS_W { w: self } + } + #[doc = "Bit 15 - Swap Inputs and Invert"] + #[inline(always)] + pub fn swap(&mut self) -> SWAP_W { + SWAP_W { w: self } + } + #[doc = "Bits 16:17 - Speed Selection"] + #[inline(always)] + pub fn speed(&mut self) -> SPEED_W { + SPEED_W { w: self } + } + #[doc = "Bit 19 - Hysteresis Enable"] + #[inline(always)] + pub fn hysten(&mut self) -> HYSTEN_W { + HYSTEN_W { w: self } + } + #[doc = "Bits 24:26 - Filter Length"] + #[inline(always)] + pub fn flen(&mut self) -> FLEN_W { + FLEN_W { w: self } + } + #[doc = "Bits 28:29 - Output"] + #[inline(always)] + pub fn out(&mut self) -> OUT_W { + OUT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Comparator Control n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [compctrl](index.html) module"] +pub struct COMPCTRL_SPEC; +impl crate::RegisterSpec for COMPCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [compctrl::R](R) reader structure"] +impl crate::Readable for COMPCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [compctrl::W](W) writer structure"] +impl crate::Writable for COMPCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COMPCTRL[%s] +to value 0"] +impl crate::Resettable for COMPCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/ac/ctrla.rs b/pac/atsamc21g/src/ac/ctrla.rs new file mode 100644 index 000000000000..5f2c406226f4 --- /dev/null +++ b/pac/atsamc21g/src/ac/ctrla.rs @@ -0,0 +1,160 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/ac/ctrlb.rs b/pac/atsamc21g/src/ac/ctrlb.rs new file mode 100644 index 000000000000..fa9d604101c2 --- /dev/null +++ b/pac/atsamc21g/src/ac/ctrlb.rs @@ -0,0 +1,153 @@ +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `START0` writer - Comparator 0 Start Comparison"] +pub struct START0_W<'a> { + w: &'a mut W, +} +impl<'a> START0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `START1` writer - Comparator 1 Start Comparison"] +pub struct START1_W<'a> { + w: &'a mut W, +} +impl<'a> START1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `START2` writer - Comparator 2 Start Comparison"] +pub struct START2_W<'a> { + w: &'a mut W, +} +impl<'a> START2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `START3` writer - Comparator 3 Start Comparison"] +pub struct START3_W<'a> { + w: &'a mut W, +} +impl<'a> START3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +impl W { + #[doc = "Bit 0 - Comparator 0 Start Comparison"] + #[inline(always)] + pub fn start0(&mut self) -> START0_W { + START0_W { w: self } + } + #[doc = "Bit 1 - Comparator 1 Start Comparison"] + #[inline(always)] + pub fn start1(&mut self) -> START1_W { + START1_W { w: self } + } + #[doc = "Bit 2 - Comparator 2 Start Comparison"] + #[inline(always)] + pub fn start2(&mut self) -> START2_W { + START2_W { w: self } + } + #[doc = "Bit 3 - Comparator 3 Start Comparison"] + #[inline(always)] + pub fn start3(&mut self) -> START3_W { + START3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u8; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/ac/dbgctrl.rs b/pac/atsamc21g/src/ac/dbgctrl.rs new file mode 100644 index 000000000000..53636eb2b339 --- /dev/null +++ b/pac/atsamc21g/src/ac/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Debug Run"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Debug Run"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/ac/evctrl.rs b/pac/atsamc21g/src/ac/evctrl.rs new file mode 100644 index 000000000000..b2f64ee12108 --- /dev/null +++ b/pac/atsamc21g/src/ac/evctrl.rs @@ -0,0 +1,724 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COMPEO0` reader - Comparator 0 Event Output Enable"] +pub struct COMPEO0_R(crate::FieldReader); +impl COMPEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPEO0` writer - Comparator 0 Event Output Enable"] +pub struct COMPEO0_W<'a> { + w: &'a mut W, +} +impl<'a> COMPEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `COMPEO1` reader - Comparator 1 Event Output Enable"] +pub struct COMPEO1_R(crate::FieldReader); +impl COMPEO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPEO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPEO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPEO1` writer - Comparator 1 Event Output Enable"] +pub struct COMPEO1_W<'a> { + w: &'a mut W, +} +impl<'a> COMPEO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `COMPEO2` reader - Comparator 2 Event Output Enable"] +pub struct COMPEO2_R(crate::FieldReader); +impl COMPEO2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPEO2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPEO2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPEO2` writer - Comparator 2 Event Output Enable"] +pub struct COMPEO2_W<'a> { + w: &'a mut W, +} +impl<'a> COMPEO2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `COMPEO3` reader - Comparator 3 Event Output Enable"] +pub struct COMPEO3_R(crate::FieldReader); +impl COMPEO3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPEO3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPEO3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPEO3` writer - Comparator 3 Event Output Enable"] +pub struct COMPEO3_W<'a> { + w: &'a mut W, +} +impl<'a> COMPEO3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `WINEO0` reader - Window 0 Event Output Enable"] +pub struct WINEO0_R(crate::FieldReader); +impl WINEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINEO0` writer - Window 0 Event Output Enable"] +pub struct WINEO0_W<'a> { + w: &'a mut W, +} +impl<'a> WINEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `WINEO1` reader - Window 1 Event Output Enable"] +pub struct WINEO1_R(crate::FieldReader); +impl WINEO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINEO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINEO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINEO1` writer - Window 1 Event Output Enable"] +pub struct WINEO1_W<'a> { + w: &'a mut W, +} +impl<'a> WINEO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `COMPEI0` reader - Comparator 0 Event Input Enable"] +pub struct COMPEI0_R(crate::FieldReader); +impl COMPEI0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPEI0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPEI0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPEI0` writer - Comparator 0 Event Input Enable"] +pub struct COMPEI0_W<'a> { + w: &'a mut W, +} +impl<'a> COMPEI0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `COMPEI1` reader - Comparator 1 Event Input Enable"] +pub struct COMPEI1_R(crate::FieldReader); +impl COMPEI1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPEI1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPEI1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPEI1` writer - Comparator 1 Event Input Enable"] +pub struct COMPEI1_W<'a> { + w: &'a mut W, +} +impl<'a> COMPEI1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `COMPEI2` reader - Comparator 2 Event Input Enable"] +pub struct COMPEI2_R(crate::FieldReader); +impl COMPEI2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPEI2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPEI2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPEI2` writer - Comparator 2 Event Input Enable"] +pub struct COMPEI2_W<'a> { + w: &'a mut W, +} +impl<'a> COMPEI2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u16 & 0x01) << 10); + self.w + } +} +#[doc = "Field `COMPEI3` reader - Comparator 3 Event Input Enable"] +pub struct COMPEI3_R(crate::FieldReader); +impl COMPEI3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPEI3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPEI3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPEI3` writer - Comparator 3 Event Input Enable"] +pub struct COMPEI3_W<'a> { + w: &'a mut W, +} +impl<'a> COMPEI3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u16 & 0x01) << 11); + self.w + } +} +#[doc = "Field `INVEI0` reader - Comparator 0 Input Event Invert Enable"] +pub struct INVEI0_R(crate::FieldReader); +impl INVEI0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEI0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEI0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEI0` writer - Comparator 0 Input Event Invert Enable"] +pub struct INVEI0_W<'a> { + w: &'a mut W, +} +impl<'a> INVEI0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u16 & 0x01) << 12); + self.w + } +} +#[doc = "Field `INVEI1` reader - Comparator 1 Input Event Invert Enable"] +pub struct INVEI1_R(crate::FieldReader); +impl INVEI1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEI1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEI1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEI1` writer - Comparator 1 Input Event Invert Enable"] +pub struct INVEI1_W<'a> { + w: &'a mut W, +} +impl<'a> INVEI1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u16 & 0x01) << 13); + self.w + } +} +#[doc = "Field `INVEI2` reader - Comparator 2 Input Event Invert Enable"] +pub struct INVEI2_R(crate::FieldReader); +impl INVEI2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEI2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEI2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEI2` writer - Comparator 2 Input Event Invert Enable"] +pub struct INVEI2_W<'a> { + w: &'a mut W, +} +impl<'a> INVEI2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u16 & 0x01) << 14); + self.w + } +} +#[doc = "Field `INVEI3` reader - Comparator 3 Input Event Invert Enable"] +pub struct INVEI3_R(crate::FieldReader); +impl INVEI3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEI3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEI3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEI3` writer - Comparator 3 Input Event Invert Enable"] +pub struct INVEI3_W<'a> { + w: &'a mut W, +} +impl<'a> INVEI3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Comparator 0 Event Output Enable"] + #[inline(always)] + pub fn compeo0(&self) -> COMPEO0_R { + COMPEO0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Comparator 1 Event Output Enable"] + #[inline(always)] + pub fn compeo1(&self) -> COMPEO1_R { + COMPEO1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Comparator 2 Event Output Enable"] + #[inline(always)] + pub fn compeo2(&self) -> COMPEO2_R { + COMPEO2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Comparator 3 Event Output Enable"] + #[inline(always)] + pub fn compeo3(&self) -> COMPEO3_R { + COMPEO3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Window 0 Event Output Enable"] + #[inline(always)] + pub fn wineo0(&self) -> WINEO0_R { + WINEO0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Window 1 Event Output Enable"] + #[inline(always)] + pub fn wineo1(&self) -> WINEO1_R { + WINEO1_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 8 - Comparator 0 Event Input Enable"] + #[inline(always)] + pub fn compei0(&self) -> COMPEI0_R { + COMPEI0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Comparator 1 Event Input Enable"] + #[inline(always)] + pub fn compei1(&self) -> COMPEI1_R { + COMPEI1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Comparator 2 Event Input Enable"] + #[inline(always)] + pub fn compei2(&self) -> COMPEI2_R { + COMPEI2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Comparator 3 Event Input Enable"] + #[inline(always)] + pub fn compei3(&self) -> COMPEI3_R { + COMPEI3_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Comparator 0 Input Event Invert Enable"] + #[inline(always)] + pub fn invei0(&self) -> INVEI0_R { + INVEI0_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Comparator 1 Input Event Invert Enable"] + #[inline(always)] + pub fn invei1(&self) -> INVEI1_R { + INVEI1_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Comparator 2 Input Event Invert Enable"] + #[inline(always)] + pub fn invei2(&self) -> INVEI2_R { + INVEI2_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Comparator 3 Input Event Invert Enable"] + #[inline(always)] + pub fn invei3(&self) -> INVEI3_R { + INVEI3_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Comparator 0 Event Output Enable"] + #[inline(always)] + pub fn compeo0(&mut self) -> COMPEO0_W { + COMPEO0_W { w: self } + } + #[doc = "Bit 1 - Comparator 1 Event Output Enable"] + #[inline(always)] + pub fn compeo1(&mut self) -> COMPEO1_W { + COMPEO1_W { w: self } + } + #[doc = "Bit 2 - Comparator 2 Event Output Enable"] + #[inline(always)] + pub fn compeo2(&mut self) -> COMPEO2_W { + COMPEO2_W { w: self } + } + #[doc = "Bit 3 - Comparator 3 Event Output Enable"] + #[inline(always)] + pub fn compeo3(&mut self) -> COMPEO3_W { + COMPEO3_W { w: self } + } + #[doc = "Bit 4 - Window 0 Event Output Enable"] + #[inline(always)] + pub fn wineo0(&mut self) -> WINEO0_W { + WINEO0_W { w: self } + } + #[doc = "Bit 5 - Window 1 Event Output Enable"] + #[inline(always)] + pub fn wineo1(&mut self) -> WINEO1_W { + WINEO1_W { w: self } + } + #[doc = "Bit 8 - Comparator 0 Event Input Enable"] + #[inline(always)] + pub fn compei0(&mut self) -> COMPEI0_W { + COMPEI0_W { w: self } + } + #[doc = "Bit 9 - Comparator 1 Event Input Enable"] + #[inline(always)] + pub fn compei1(&mut self) -> COMPEI1_W { + COMPEI1_W { w: self } + } + #[doc = "Bit 10 - Comparator 2 Event Input Enable"] + #[inline(always)] + pub fn compei2(&mut self) -> COMPEI2_W { + COMPEI2_W { w: self } + } + #[doc = "Bit 11 - Comparator 3 Event Input Enable"] + #[inline(always)] + pub fn compei3(&mut self) -> COMPEI3_W { + COMPEI3_W { w: self } + } + #[doc = "Bit 12 - Comparator 0 Input Event Invert Enable"] + #[inline(always)] + pub fn invei0(&mut self) -> INVEI0_W { + INVEI0_W { w: self } + } + #[doc = "Bit 13 - Comparator 1 Input Event Invert Enable"] + #[inline(always)] + pub fn invei1(&mut self) -> INVEI1_W { + INVEI1_W { w: self } + } + #[doc = "Bit 14 - Comparator 2 Input Event Invert Enable"] + #[inline(always)] + pub fn invei2(&mut self) -> INVEI2_W { + INVEI2_W { w: self } + } + #[doc = "Bit 15 - Comparator 3 Input Event Invert Enable"] + #[inline(always)] + pub fn invei3(&mut self) -> INVEI3_W { + INVEI3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/ac/intenclr.rs b/pac/atsamc21g/src/ac/intenclr.rs new file mode 100644 index 000000000000..e948bee83d3f --- /dev/null +++ b/pac/atsamc21g/src/ac/intenclr.rs @@ -0,0 +1,348 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COMP0` reader - Comparator 0 Interrupt Enable"] +pub struct COMP0_R(crate::FieldReader); +impl COMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP0` writer - Comparator 0 Interrupt Enable"] +pub struct COMP0_W<'a> { + w: &'a mut W, +} +impl<'a> COMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `COMP1` reader - Comparator 1 Interrupt Enable"] +pub struct COMP1_R(crate::FieldReader); +impl COMP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP1` writer - Comparator 1 Interrupt Enable"] +pub struct COMP1_W<'a> { + w: &'a mut W, +} +impl<'a> COMP1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `COMP2` reader - Comparator 2 Interrupt Enable"] +pub struct COMP2_R(crate::FieldReader); +impl COMP2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP2` writer - Comparator 2 Interrupt Enable"] +pub struct COMP2_W<'a> { + w: &'a mut W, +} +impl<'a> COMP2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `COMP3` reader - Comparator 3 Interrupt Enable"] +pub struct COMP3_R(crate::FieldReader); +impl COMP3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP3` writer - Comparator 3 Interrupt Enable"] +pub struct COMP3_W<'a> { + w: &'a mut W, +} +impl<'a> COMP3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `WIN0` reader - Window 0 Interrupt Enable"] +pub struct WIN0_R(crate::FieldReader); +impl WIN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WIN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WIN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WIN0` writer - Window 0 Interrupt Enable"] +pub struct WIN0_W<'a> { + w: &'a mut W, +} +impl<'a> WIN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `WIN1` reader - Window 1 Interrupt Enable"] +pub struct WIN1_R(crate::FieldReader); +impl WIN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WIN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WIN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WIN1` writer - Window 1 Interrupt Enable"] +pub struct WIN1_W<'a> { + w: &'a mut W, +} +impl<'a> WIN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Comparator 0 Interrupt Enable"] + #[inline(always)] + pub fn comp0(&self) -> COMP0_R { + COMP0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Comparator 1 Interrupt Enable"] + #[inline(always)] + pub fn comp1(&self) -> COMP1_R { + COMP1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Comparator 2 Interrupt Enable"] + #[inline(always)] + pub fn comp2(&self) -> COMP2_R { + COMP2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Comparator 3 Interrupt Enable"] + #[inline(always)] + pub fn comp3(&self) -> COMP3_R { + COMP3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Window 0 Interrupt Enable"] + #[inline(always)] + pub fn win0(&self) -> WIN0_R { + WIN0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Window 1 Interrupt Enable"] + #[inline(always)] + pub fn win1(&self) -> WIN1_R { + WIN1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Comparator 0 Interrupt Enable"] + #[inline(always)] + pub fn comp0(&mut self) -> COMP0_W { + COMP0_W { w: self } + } + #[doc = "Bit 1 - Comparator 1 Interrupt Enable"] + #[inline(always)] + pub fn comp1(&mut self) -> COMP1_W { + COMP1_W { w: self } + } + #[doc = "Bit 2 - Comparator 2 Interrupt Enable"] + #[inline(always)] + pub fn comp2(&mut self) -> COMP2_W { + COMP2_W { w: self } + } + #[doc = "Bit 3 - Comparator 3 Interrupt Enable"] + #[inline(always)] + pub fn comp3(&mut self) -> COMP3_W { + COMP3_W { w: self } + } + #[doc = "Bit 4 - Window 0 Interrupt Enable"] + #[inline(always)] + pub fn win0(&mut self) -> WIN0_W { + WIN0_W { w: self } + } + #[doc = "Bit 5 - Window 1 Interrupt Enable"] + #[inline(always)] + pub fn win1(&mut self) -> WIN1_W { + WIN1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/ac/intenset.rs b/pac/atsamc21g/src/ac/intenset.rs new file mode 100644 index 000000000000..b631f5136fb6 --- /dev/null +++ b/pac/atsamc21g/src/ac/intenset.rs @@ -0,0 +1,348 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COMP0` reader - Comparator 0 Interrupt Enable"] +pub struct COMP0_R(crate::FieldReader); +impl COMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP0` writer - Comparator 0 Interrupt Enable"] +pub struct COMP0_W<'a> { + w: &'a mut W, +} +impl<'a> COMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `COMP1` reader - Comparator 1 Interrupt Enable"] +pub struct COMP1_R(crate::FieldReader); +impl COMP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP1` writer - Comparator 1 Interrupt Enable"] +pub struct COMP1_W<'a> { + w: &'a mut W, +} +impl<'a> COMP1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `COMP2` reader - Comparator 2 Interrupt Enable"] +pub struct COMP2_R(crate::FieldReader); +impl COMP2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP2` writer - Comparator 2 Interrupt Enable"] +pub struct COMP2_W<'a> { + w: &'a mut W, +} +impl<'a> COMP2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `COMP3` reader - Comparator 3 Interrupt Enable"] +pub struct COMP3_R(crate::FieldReader); +impl COMP3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP3` writer - Comparator 3 Interrupt Enable"] +pub struct COMP3_W<'a> { + w: &'a mut W, +} +impl<'a> COMP3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `WIN0` reader - Window 0 Interrupt Enable"] +pub struct WIN0_R(crate::FieldReader); +impl WIN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WIN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WIN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WIN0` writer - Window 0 Interrupt Enable"] +pub struct WIN0_W<'a> { + w: &'a mut W, +} +impl<'a> WIN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `WIN1` reader - Window 1 Interrupt Enable"] +pub struct WIN1_R(crate::FieldReader); +impl WIN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WIN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WIN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WIN1` writer - Window 1 Interrupt Enable"] +pub struct WIN1_W<'a> { + w: &'a mut W, +} +impl<'a> WIN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Comparator 0 Interrupt Enable"] + #[inline(always)] + pub fn comp0(&self) -> COMP0_R { + COMP0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Comparator 1 Interrupt Enable"] + #[inline(always)] + pub fn comp1(&self) -> COMP1_R { + COMP1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Comparator 2 Interrupt Enable"] + #[inline(always)] + pub fn comp2(&self) -> COMP2_R { + COMP2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Comparator 3 Interrupt Enable"] + #[inline(always)] + pub fn comp3(&self) -> COMP3_R { + COMP3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Window 0 Interrupt Enable"] + #[inline(always)] + pub fn win0(&self) -> WIN0_R { + WIN0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Window 1 Interrupt Enable"] + #[inline(always)] + pub fn win1(&self) -> WIN1_R { + WIN1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Comparator 0 Interrupt Enable"] + #[inline(always)] + pub fn comp0(&mut self) -> COMP0_W { + COMP0_W { w: self } + } + #[doc = "Bit 1 - Comparator 1 Interrupt Enable"] + #[inline(always)] + pub fn comp1(&mut self) -> COMP1_W { + COMP1_W { w: self } + } + #[doc = "Bit 2 - Comparator 2 Interrupt Enable"] + #[inline(always)] + pub fn comp2(&mut self) -> COMP2_W { + COMP2_W { w: self } + } + #[doc = "Bit 3 - Comparator 3 Interrupt Enable"] + #[inline(always)] + pub fn comp3(&mut self) -> COMP3_W { + COMP3_W { w: self } + } + #[doc = "Bit 4 - Window 0 Interrupt Enable"] + #[inline(always)] + pub fn win0(&mut self) -> WIN0_W { + WIN0_W { w: self } + } + #[doc = "Bit 5 - Window 1 Interrupt Enable"] + #[inline(always)] + pub fn win1(&mut self) -> WIN1_W { + WIN1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/ac/intflag.rs b/pac/atsamc21g/src/ac/intflag.rs new file mode 100644 index 000000000000..6557a5e48464 --- /dev/null +++ b/pac/atsamc21g/src/ac/intflag.rs @@ -0,0 +1,348 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COMP0` reader - Comparator 0"] +pub struct COMP0_R(crate::FieldReader); +impl COMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP0` writer - Comparator 0"] +pub struct COMP0_W<'a> { + w: &'a mut W, +} +impl<'a> COMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `COMP1` reader - Comparator 1"] +pub struct COMP1_R(crate::FieldReader); +impl COMP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP1` writer - Comparator 1"] +pub struct COMP1_W<'a> { + w: &'a mut W, +} +impl<'a> COMP1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `COMP2` reader - Comparator 2"] +pub struct COMP2_R(crate::FieldReader); +impl COMP2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP2` writer - Comparator 2"] +pub struct COMP2_W<'a> { + w: &'a mut W, +} +impl<'a> COMP2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `COMP3` reader - Comparator 3"] +pub struct COMP3_R(crate::FieldReader); +impl COMP3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP3` writer - Comparator 3"] +pub struct COMP3_W<'a> { + w: &'a mut W, +} +impl<'a> COMP3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `WIN0` reader - Window 0"] +pub struct WIN0_R(crate::FieldReader); +impl WIN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WIN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WIN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WIN0` writer - Window 0"] +pub struct WIN0_W<'a> { + w: &'a mut W, +} +impl<'a> WIN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `WIN1` reader - Window 1"] +pub struct WIN1_R(crate::FieldReader); +impl WIN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WIN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WIN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WIN1` writer - Window 1"] +pub struct WIN1_W<'a> { + w: &'a mut W, +} +impl<'a> WIN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Comparator 0"] + #[inline(always)] + pub fn comp0(&self) -> COMP0_R { + COMP0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Comparator 1"] + #[inline(always)] + pub fn comp1(&self) -> COMP1_R { + COMP1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Comparator 2"] + #[inline(always)] + pub fn comp2(&self) -> COMP2_R { + COMP2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Comparator 3"] + #[inline(always)] + pub fn comp3(&self) -> COMP3_R { + COMP3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Window 0"] + #[inline(always)] + pub fn win0(&self) -> WIN0_R { + WIN0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Window 1"] + #[inline(always)] + pub fn win1(&self) -> WIN1_R { + WIN1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Comparator 0"] + #[inline(always)] + pub fn comp0(&mut self) -> COMP0_W { + COMP0_W { w: self } + } + #[doc = "Bit 1 - Comparator 1"] + #[inline(always)] + pub fn comp1(&mut self) -> COMP1_W { + COMP1_W { w: self } + } + #[doc = "Bit 2 - Comparator 2"] + #[inline(always)] + pub fn comp2(&mut self) -> COMP2_W { + COMP2_W { w: self } + } + #[doc = "Bit 3 - Comparator 3"] + #[inline(always)] + pub fn comp3(&mut self) -> COMP3_W { + COMP3_W { w: self } + } + #[doc = "Bit 4 - Window 0"] + #[inline(always)] + pub fn win0(&mut self) -> WIN0_W { + WIN0_W { w: self } + } + #[doc = "Bit 5 - Window 1"] + #[inline(always)] + pub fn win1(&mut self) -> WIN1_W { + WIN1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/ac/scaler.rs b/pac/atsamc21g/src/ac/scaler.rs new file mode 100644 index 000000000000..091cacfaeb4b --- /dev/null +++ b/pac/atsamc21g/src/ac/scaler.rs @@ -0,0 +1,104 @@ +#[doc = "Register `SCALER[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SCALER[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `VALUE` reader - Scaler Value"] +pub struct VALUE_R(crate::FieldReader); +impl VALUE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + VALUE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VALUE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VALUE` writer - Scaler Value"] +pub struct VALUE_W<'a> { + w: &'a mut W, +} +impl<'a> VALUE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u8 & 0x3f); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Scaler Value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - Scaler Value"] + #[inline(always)] + pub fn value(&mut self) -> VALUE_W { + VALUE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Scaler n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [scaler](index.html) module"] +pub struct SCALER_SPEC; +impl crate::RegisterSpec for SCALER_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [scaler::R](R) reader structure"] +impl crate::Readable for SCALER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [scaler::W](W) writer structure"] +impl crate::Writable for SCALER_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SCALER[%s] +to value 0"] +impl crate::Resettable for SCALER_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/ac/statusa.rs b/pac/atsamc21g/src/ac/statusa.rs new file mode 100644 index 000000000000..f79619555497 --- /dev/null +++ b/pac/atsamc21g/src/ac/statusa.rs @@ -0,0 +1,237 @@ +#[doc = "Register `STATUSA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `STATE0` reader - Comparator 0 Current State"] +pub struct STATE0_R(crate::FieldReader); +impl STATE0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STATE0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STATE0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STATE1` reader - Comparator 1 Current State"] +pub struct STATE1_R(crate::FieldReader); +impl STATE1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STATE1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STATE1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STATE2` reader - Comparator 2 Current State"] +pub struct STATE2_R(crate::FieldReader); +impl STATE2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STATE2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STATE2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STATE3` reader - Comparator 3 Current State"] +pub struct STATE3_R(crate::FieldReader); +impl STATE3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STATE3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STATE3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Window 0 Current State\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WSTATE0_A { + #[doc = "0: Signal is above window"] + ABOVE = 0, + #[doc = "1: Signal is inside window"] + INSIDE = 1, + #[doc = "2: Signal is below window"] + BELOW = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WSTATE0_A) -> Self { + variant as _ + } +} +#[doc = "Field `WSTATE0` reader - Window 0 Current State"] +pub struct WSTATE0_R(crate::FieldReader); +impl WSTATE0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WSTATE0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(WSTATE0_A::ABOVE), + 1 => Some(WSTATE0_A::INSIDE), + 2 => Some(WSTATE0_A::BELOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `ABOVE`"] + #[inline(always)] + pub fn is_above(&self) -> bool { + **self == WSTATE0_A::ABOVE + } + #[doc = "Checks if the value of the field is `INSIDE`"] + #[inline(always)] + pub fn is_inside(&self) -> bool { + **self == WSTATE0_A::INSIDE + } + #[doc = "Checks if the value of the field is `BELOW`"] + #[inline(always)] + pub fn is_below(&self) -> bool { + **self == WSTATE0_A::BELOW + } +} +impl core::ops::Deref for WSTATE0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Window 1 Current State\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WSTATE1_A { + #[doc = "0: Signal is above window"] + ABOVE = 0, + #[doc = "1: Signal is inside window"] + INSIDE = 1, + #[doc = "2: Signal is below window"] + BELOW = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WSTATE1_A) -> Self { + variant as _ + } +} +#[doc = "Field `WSTATE1` reader - Window 1 Current State"] +pub struct WSTATE1_R(crate::FieldReader); +impl WSTATE1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WSTATE1_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(WSTATE1_A::ABOVE), + 1 => Some(WSTATE1_A::INSIDE), + 2 => Some(WSTATE1_A::BELOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `ABOVE`"] + #[inline(always)] + pub fn is_above(&self) -> bool { + **self == WSTATE1_A::ABOVE + } + #[doc = "Checks if the value of the field is `INSIDE`"] + #[inline(always)] + pub fn is_inside(&self) -> bool { + **self == WSTATE1_A::INSIDE + } + #[doc = "Checks if the value of the field is `BELOW`"] + #[inline(always)] + pub fn is_below(&self) -> bool { + **self == WSTATE1_A::BELOW + } +} +impl core::ops::Deref for WSTATE1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Comparator 0 Current State"] + #[inline(always)] + pub fn state0(&self) -> STATE0_R { + STATE0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Comparator 1 Current State"] + #[inline(always)] + pub fn state1(&self) -> STATE1_R { + STATE1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Comparator 2 Current State"] + #[inline(always)] + pub fn state2(&self) -> STATE2_R { + STATE2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Comparator 3 Current State"] + #[inline(always)] + pub fn state3(&self) -> STATE3_R { + STATE3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bits 4:5 - Window 0 Current State"] + #[inline(always)] + pub fn wstate0(&self) -> WSTATE0_R { + WSTATE0_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bits 6:7 - Window 1 Current State"] + #[inline(always)] + pub fn wstate1(&self) -> WSTATE1_R { + WSTATE1_R::new(((self.bits >> 6) & 0x03) as u8) + } +} +#[doc = "Status A\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [statusa](index.html) module"] +pub struct STATUSA_SPEC; +impl crate::RegisterSpec for STATUSA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [statusa::R](R) reader structure"] +impl crate::Readable for STATUSA_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUSA to value 0"] +impl crate::Resettable for STATUSA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/ac/statusb.rs b/pac/atsamc21g/src/ac/statusb.rs new file mode 100644 index 000000000000..1f7035958bd8 --- /dev/null +++ b/pac/atsamc21g/src/ac/statusb.rs @@ -0,0 +1,113 @@ +#[doc = "Register `STATUSB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `READY0` reader - Comparator 0 Ready"] +pub struct READY0_R(crate::FieldReader); +impl READY0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + READY0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for READY0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `READY1` reader - Comparator 1 Ready"] +pub struct READY1_R(crate::FieldReader); +impl READY1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + READY1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for READY1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `READY2` reader - Comparator 2 Ready"] +pub struct READY2_R(crate::FieldReader); +impl READY2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + READY2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for READY2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `READY3` reader - Comparator 3 Ready"] +pub struct READY3_R(crate::FieldReader); +impl READY3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + READY3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for READY3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Comparator 0 Ready"] + #[inline(always)] + pub fn ready0(&self) -> READY0_R { + READY0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Comparator 1 Ready"] + #[inline(always)] + pub fn ready1(&self) -> READY1_R { + READY1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Comparator 2 Ready"] + #[inline(always)] + pub fn ready2(&self) -> READY2_R { + READY2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Comparator 3 Ready"] + #[inline(always)] + pub fn ready3(&self) -> READY3_R { + READY3_R::new(((self.bits >> 3) & 0x01) != 0) + } +} +#[doc = "Status B\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [statusb](index.html) module"] +pub struct STATUSB_SPEC; +impl crate::RegisterSpec for STATUSB_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [statusb::R](R) reader structure"] +impl crate::Readable for STATUSB_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUSB to value 0"] +impl crate::Resettable for STATUSB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/ac/syncbusy.rs b/pac/atsamc21g/src/ac/syncbusy.rs new file mode 100644 index 000000000000..bbd5b5cbe18f --- /dev/null +++ b/pac/atsamc21g/src/ac/syncbusy.rs @@ -0,0 +1,173 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - Enable Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINCTRL` reader - WINCTRL Synchronization Busy"] +pub struct WINCTRL_R(crate::FieldReader); +impl WINCTRL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINCTRL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINCTRL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPCTRL0` reader - COMPCTRL 0 Synchronization Busy"] +pub struct COMPCTRL0_R(crate::FieldReader); +impl COMPCTRL0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPCTRL0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPCTRL0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPCTRL1` reader - COMPCTRL 1 Synchronization Busy"] +pub struct COMPCTRL1_R(crate::FieldReader); +impl COMPCTRL1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPCTRL1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPCTRL1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPCTRL2` reader - COMPCTRL 2 Synchronization Busy"] +pub struct COMPCTRL2_R(crate::FieldReader); +impl COMPCTRL2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPCTRL2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPCTRL2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPCTRL3` reader - COMPCTRL 3 Synchronization Busy"] +pub struct COMPCTRL3_R(crate::FieldReader); +impl COMPCTRL3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPCTRL3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPCTRL3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - WINCTRL Synchronization Busy"] + #[inline(always)] + pub fn winctrl(&self) -> WINCTRL_R { + WINCTRL_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - COMPCTRL 0 Synchronization Busy"] + #[inline(always)] + pub fn compctrl0(&self) -> COMPCTRL0_R { + COMPCTRL0_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - COMPCTRL 1 Synchronization Busy"] + #[inline(always)] + pub fn compctrl1(&self) -> COMPCTRL1_R { + COMPCTRL1_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - COMPCTRL 2 Synchronization Busy"] + #[inline(always)] + pub fn compctrl2(&self) -> COMPCTRL2_R { + COMPCTRL2_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - COMPCTRL 3 Synchronization Busy"] + #[inline(always)] + pub fn compctrl3(&self) -> COMPCTRL3_R { + COMPCTRL3_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +#[doc = "Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/ac/winctrl.rs b/pac/atsamc21g/src/ac/winctrl.rs new file mode 100644 index 000000000000..e3fe941f07bd --- /dev/null +++ b/pac/atsamc21g/src/ac/winctrl.rs @@ -0,0 +1,384 @@ +#[doc = "Register `WINCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WINCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WEN0` reader - Window 0 Mode Enable"] +pub struct WEN0_R(crate::FieldReader); +impl WEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WEN0` writer - Window 0 Mode Enable"] +pub struct WEN0_W<'a> { + w: &'a mut W, +} +impl<'a> WEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Window 0 Interrupt Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WINTSEL0_A { + #[doc = "0: Interrupt on signal above window"] + ABOVE = 0, + #[doc = "1: Interrupt on signal inside window"] + INSIDE = 1, + #[doc = "2: Interrupt on signal below window"] + BELOW = 2, + #[doc = "3: Interrupt on signal outside window"] + OUTSIDE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WINTSEL0_A) -> Self { + variant as _ + } +} +#[doc = "Field `WINTSEL0` reader - Window 0 Interrupt Selection"] +pub struct WINTSEL0_R(crate::FieldReader); +impl WINTSEL0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WINTSEL0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> WINTSEL0_A { + match self.bits { + 0 => WINTSEL0_A::ABOVE, + 1 => WINTSEL0_A::INSIDE, + 2 => WINTSEL0_A::BELOW, + 3 => WINTSEL0_A::OUTSIDE, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `ABOVE`"] + #[inline(always)] + pub fn is_above(&self) -> bool { + **self == WINTSEL0_A::ABOVE + } + #[doc = "Checks if the value of the field is `INSIDE`"] + #[inline(always)] + pub fn is_inside(&self) -> bool { + **self == WINTSEL0_A::INSIDE + } + #[doc = "Checks if the value of the field is `BELOW`"] + #[inline(always)] + pub fn is_below(&self) -> bool { + **self == WINTSEL0_A::BELOW + } + #[doc = "Checks if the value of the field is `OUTSIDE`"] + #[inline(always)] + pub fn is_outside(&self) -> bool { + **self == WINTSEL0_A::OUTSIDE + } +} +impl core::ops::Deref for WINTSEL0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINTSEL0` writer - Window 0 Interrupt Selection"] +pub struct WINTSEL0_W<'a> { + w: &'a mut W, +} +impl<'a> WINTSEL0_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WINTSEL0_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Interrupt on signal above window"] + #[inline(always)] + pub fn above(self) -> &'a mut W { + self.variant(WINTSEL0_A::ABOVE) + } + #[doc = "Interrupt on signal inside window"] + #[inline(always)] + pub fn inside(self) -> &'a mut W { + self.variant(WINTSEL0_A::INSIDE) + } + #[doc = "Interrupt on signal below window"] + #[inline(always)] + pub fn below(self) -> &'a mut W { + self.variant(WINTSEL0_A::BELOW) + } + #[doc = "Interrupt on signal outside window"] + #[inline(always)] + pub fn outside(self) -> &'a mut W { + self.variant(WINTSEL0_A::OUTSIDE) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 1)) | ((value as u8 & 0x03) << 1); + self.w + } +} +#[doc = "Field `WEN1` reader - Window 1 Mode Enable"] +pub struct WEN1_R(crate::FieldReader); +impl WEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WEN1` writer - Window 1 Mode Enable"] +pub struct WEN1_W<'a> { + w: &'a mut W, +} +impl<'a> WEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Window 1 Interrupt Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WINTSEL1_A { + #[doc = "0: Interrupt on signal above window"] + ABOVE = 0, + #[doc = "1: Interrupt on signal inside window"] + INSIDE = 1, + #[doc = "2: Interrupt on signal below window"] + BELOW = 2, + #[doc = "3: Interrupt on signal outside window"] + OUTSIDE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WINTSEL1_A) -> Self { + variant as _ + } +} +#[doc = "Field `WINTSEL1` reader - Window 1 Interrupt Selection"] +pub struct WINTSEL1_R(crate::FieldReader); +impl WINTSEL1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WINTSEL1_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> WINTSEL1_A { + match self.bits { + 0 => WINTSEL1_A::ABOVE, + 1 => WINTSEL1_A::INSIDE, + 2 => WINTSEL1_A::BELOW, + 3 => WINTSEL1_A::OUTSIDE, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `ABOVE`"] + #[inline(always)] + pub fn is_above(&self) -> bool { + **self == WINTSEL1_A::ABOVE + } + #[doc = "Checks if the value of the field is `INSIDE`"] + #[inline(always)] + pub fn is_inside(&self) -> bool { + **self == WINTSEL1_A::INSIDE + } + #[doc = "Checks if the value of the field is `BELOW`"] + #[inline(always)] + pub fn is_below(&self) -> bool { + **self == WINTSEL1_A::BELOW + } + #[doc = "Checks if the value of the field is `OUTSIDE`"] + #[inline(always)] + pub fn is_outside(&self) -> bool { + **self == WINTSEL1_A::OUTSIDE + } +} +impl core::ops::Deref for WINTSEL1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINTSEL1` writer - Window 1 Interrupt Selection"] +pub struct WINTSEL1_W<'a> { + w: &'a mut W, +} +impl<'a> WINTSEL1_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WINTSEL1_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Interrupt on signal above window"] + #[inline(always)] + pub fn above(self) -> &'a mut W { + self.variant(WINTSEL1_A::ABOVE) + } + #[doc = "Interrupt on signal inside window"] + #[inline(always)] + pub fn inside(self) -> &'a mut W { + self.variant(WINTSEL1_A::INSIDE) + } + #[doc = "Interrupt on signal below window"] + #[inline(always)] + pub fn below(self) -> &'a mut W { + self.variant(WINTSEL1_A::BELOW) + } + #[doc = "Interrupt on signal outside window"] + #[inline(always)] + pub fn outside(self) -> &'a mut W { + self.variant(WINTSEL1_A::OUTSIDE) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 5)) | ((value as u8 & 0x03) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Window 0 Mode Enable"] + #[inline(always)] + pub fn wen0(&self) -> WEN0_R { + WEN0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bits 1:2 - Window 0 Interrupt Selection"] + #[inline(always)] + pub fn wintsel0(&self) -> WINTSEL0_R { + WINTSEL0_R::new(((self.bits >> 1) & 0x03) as u8) + } + #[doc = "Bit 4 - Window 1 Mode Enable"] + #[inline(always)] + pub fn wen1(&self) -> WEN1_R { + WEN1_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bits 5:6 - Window 1 Interrupt Selection"] + #[inline(always)] + pub fn wintsel1(&self) -> WINTSEL1_R { + WINTSEL1_R::new(((self.bits >> 5) & 0x03) as u8) + } +} +impl W { + #[doc = "Bit 0 - Window 0 Mode Enable"] + #[inline(always)] + pub fn wen0(&mut self) -> WEN0_W { + WEN0_W { w: self } + } + #[doc = "Bits 1:2 - Window 0 Interrupt Selection"] + #[inline(always)] + pub fn wintsel0(&mut self) -> WINTSEL0_W { + WINTSEL0_W { w: self } + } + #[doc = "Bit 4 - Window 1 Mode Enable"] + #[inline(always)] + pub fn wen1(&mut self) -> WEN1_W { + WEN1_W { w: self } + } + #[doc = "Bits 5:6 - Window 1 Interrupt Selection"] + #[inline(always)] + pub fn wintsel1(&mut self) -> WINTSEL1_W { + WINTSEL1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Window Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [winctrl](index.html) module"] +pub struct WINCTRL_SPEC; +impl crate::RegisterSpec for WINCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [winctrl::R](R) reader structure"] +impl crate::Readable for WINCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [winctrl::W](W) writer structure"] +impl crate::Writable for WINCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WINCTRL to value 0"] +impl crate::Resettable for WINCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/adc0.rs b/pac/atsamc21g/src/adc0.rs new file mode 100644 index 000000000000..453f56ed28c8 --- /dev/null +++ b/pac/atsamc21g/src/adc0.rs @@ -0,0 +1,141 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + #[doc = "0x01 - Control B"] + pub ctrlb: crate::Reg, + #[doc = "0x02 - Reference Control"] + pub refctrl: crate::Reg, + #[doc = "0x03 - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x04 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x05 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x06 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x07 - Sequence Status"] + pub seqstatus: crate::Reg, + #[doc = "0x08 - Input Control"] + pub inputctrl: crate::Reg, + #[doc = "0x0a - Control C"] + pub ctrlc: crate::Reg, + #[doc = "0x0c - Average Control"] + pub avgctrl: crate::Reg, + #[doc = "0x0d - Sample Time Control"] + pub sampctrl: crate::Reg, + #[doc = "0x0e - Window Monitor Lower Threshold"] + pub winlt: crate::Reg, + #[doc = "0x10 - Window Monitor Upper Threshold"] + pub winut: crate::Reg, + #[doc = "0x12 - Gain Correction"] + pub gaincorr: crate::Reg, + #[doc = "0x14 - Offset Correction"] + pub offsetcorr: crate::Reg, + _reserved16: [u8; 0x02], + #[doc = "0x18 - Software Trigger"] + pub swtrig: crate::Reg, + _reserved17: [u8; 0x03], + #[doc = "0x1c - Debug Control"] + pub dbgctrl: crate::Reg, + _reserved18: [u8; 0x03], + #[doc = "0x20 - Synchronization Busy"] + pub syncbusy: crate::Reg, + _reserved19: [u8; 0x02], + #[doc = "0x24 - Result"] + pub result: crate::Reg, + _reserved20: [u8; 0x02], + #[doc = "0x28 - Sequence Control"] + pub seqctrl: crate::Reg, + #[doc = "0x2c - Calibration"] + pub calib: crate::Reg, +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "Control B"] +pub mod ctrlb; +#[doc = "REFCTRL register accessor: an alias for `Reg`"] +pub type REFCTRL = crate::Reg; +#[doc = "Reference Control"] +pub mod refctrl; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "SEQSTATUS register accessor: an alias for `Reg`"] +pub type SEQSTATUS = crate::Reg; +#[doc = "Sequence Status"] +pub mod seqstatus; +#[doc = "INPUTCTRL register accessor: an alias for `Reg`"] +pub type INPUTCTRL = crate::Reg; +#[doc = "Input Control"] +pub mod inputctrl; +#[doc = "CTRLC register accessor: an alias for `Reg`"] +pub type CTRLC = crate::Reg; +#[doc = "Control C"] +pub mod ctrlc; +#[doc = "AVGCTRL register accessor: an alias for `Reg`"] +pub type AVGCTRL = crate::Reg; +#[doc = "Average Control"] +pub mod avgctrl; +#[doc = "SAMPCTRL register accessor: an alias for `Reg`"] +pub type SAMPCTRL = crate::Reg; +#[doc = "Sample Time Control"] +pub mod sampctrl; +#[doc = "WINLT register accessor: an alias for `Reg`"] +pub type WINLT = crate::Reg; +#[doc = "Window Monitor Lower Threshold"] +pub mod winlt; +#[doc = "WINUT register accessor: an alias for `Reg`"] +pub type WINUT = crate::Reg; +#[doc = "Window Monitor Upper Threshold"] +pub mod winut; +#[doc = "GAINCORR register accessor: an alias for `Reg`"] +pub type GAINCORR = crate::Reg; +#[doc = "Gain Correction"] +pub mod gaincorr; +#[doc = "OFFSETCORR register accessor: an alias for `Reg`"] +pub type OFFSETCORR = crate::Reg; +#[doc = "Offset Correction"] +pub mod offsetcorr; +#[doc = "SWTRIG register accessor: an alias for `Reg`"] +pub type SWTRIG = crate::Reg; +#[doc = "Software Trigger"] +pub mod swtrig; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Busy"] +pub mod syncbusy; +#[doc = "RESULT register accessor: an alias for `Reg`"] +pub type RESULT = crate::Reg; +#[doc = "Result"] +pub mod result; +#[doc = "SEQCTRL register accessor: an alias for `Reg`"] +pub type SEQCTRL = crate::Reg; +#[doc = "Sequence Control"] +pub mod seqctrl; +#[doc = "CALIB register accessor: an alias for `Reg`"] +pub type CALIB = crate::Reg; +#[doc = "Calibration"] +pub mod calib; diff --git a/pac/atsamc21g/src/adc0/avgctrl.rs b/pac/atsamc21g/src/adc0/avgctrl.rs new file mode 100644 index 000000000000..ddb735715c98 --- /dev/null +++ b/pac/atsamc21g/src/adc0/avgctrl.rs @@ -0,0 +1,306 @@ +#[doc = "Register `AVGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `AVGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Number of Samples to be Collected\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SAMPLENUM_A { + #[doc = "0: 1 sample"] + _1 = 0, + #[doc = "1: 2 samples"] + _2 = 1, + #[doc = "2: 4 samples"] + _4 = 2, + #[doc = "3: 8 samples"] + _8 = 3, + #[doc = "4: 16 samples"] + _16 = 4, + #[doc = "5: 32 samples"] + _32 = 5, + #[doc = "6: 64 samples"] + _64 = 6, + #[doc = "7: 128 samples"] + _128 = 7, + #[doc = "8: 256 samples"] + _256 = 8, + #[doc = "9: 512 samples"] + _512 = 9, + #[doc = "10: 1024 samples"] + _1024 = 10, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SAMPLENUM_A) -> Self { + variant as _ + } +} +#[doc = "Field `SAMPLENUM` reader - Number of Samples to be Collected"] +pub struct SAMPLENUM_R(crate::FieldReader); +impl SAMPLENUM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SAMPLENUM_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SAMPLENUM_A::_1), + 1 => Some(SAMPLENUM_A::_2), + 2 => Some(SAMPLENUM_A::_4), + 3 => Some(SAMPLENUM_A::_8), + 4 => Some(SAMPLENUM_A::_16), + 5 => Some(SAMPLENUM_A::_32), + 6 => Some(SAMPLENUM_A::_64), + 7 => Some(SAMPLENUM_A::_128), + 8 => Some(SAMPLENUM_A::_256), + 9 => Some(SAMPLENUM_A::_512), + 10 => Some(SAMPLENUM_A::_1024), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_1`"] + #[inline(always)] + pub fn is_1(&self) -> bool { + **self == SAMPLENUM_A::_1 + } + #[doc = "Checks if the value of the field is `_2`"] + #[inline(always)] + pub fn is_2(&self) -> bool { + **self == SAMPLENUM_A::_2 + } + #[doc = "Checks if the value of the field is `_4`"] + #[inline(always)] + pub fn is_4(&self) -> bool { + **self == SAMPLENUM_A::_4 + } + #[doc = "Checks if the value of the field is `_8`"] + #[inline(always)] + pub fn is_8(&self) -> bool { + **self == SAMPLENUM_A::_8 + } + #[doc = "Checks if the value of the field is `_16`"] + #[inline(always)] + pub fn is_16(&self) -> bool { + **self == SAMPLENUM_A::_16 + } + #[doc = "Checks if the value of the field is `_32`"] + #[inline(always)] + pub fn is_32(&self) -> bool { + **self == SAMPLENUM_A::_32 + } + #[doc = "Checks if the value of the field is `_64`"] + #[inline(always)] + pub fn is_64(&self) -> bool { + **self == SAMPLENUM_A::_64 + } + #[doc = "Checks if the value of the field is `_128`"] + #[inline(always)] + pub fn is_128(&self) -> bool { + **self == SAMPLENUM_A::_128 + } + #[doc = "Checks if the value of the field is `_256`"] + #[inline(always)] + pub fn is_256(&self) -> bool { + **self == SAMPLENUM_A::_256 + } + #[doc = "Checks if the value of the field is `_512`"] + #[inline(always)] + pub fn is_512(&self) -> bool { + **self == SAMPLENUM_A::_512 + } + #[doc = "Checks if the value of the field is `_1024`"] + #[inline(always)] + pub fn is_1024(&self) -> bool { + **self == SAMPLENUM_A::_1024 + } +} +impl core::ops::Deref for SAMPLENUM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SAMPLENUM` writer - Number of Samples to be Collected"] +pub struct SAMPLENUM_W<'a> { + w: &'a mut W, +} +impl<'a> SAMPLENUM_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SAMPLENUM_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "1 sample"] + #[inline(always)] + pub fn _1(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_1) + } + #[doc = "2 samples"] + #[inline(always)] + pub fn _2(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_2) + } + #[doc = "4 samples"] + #[inline(always)] + pub fn _4(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_4) + } + #[doc = "8 samples"] + #[inline(always)] + pub fn _8(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_8) + } + #[doc = "16 samples"] + #[inline(always)] + pub fn _16(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_16) + } + #[doc = "32 samples"] + #[inline(always)] + pub fn _32(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_32) + } + #[doc = "64 samples"] + #[inline(always)] + pub fn _64(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_64) + } + #[doc = "128 samples"] + #[inline(always)] + pub fn _128(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_128) + } + #[doc = "256 samples"] + #[inline(always)] + pub fn _256(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_256) + } + #[doc = "512 samples"] + #[inline(always)] + pub fn _512(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_512) + } + #[doc = "1024 samples"] + #[inline(always)] + pub fn _1024(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +#[doc = "Field `ADJRES` reader - Adjusting Result / Division Coefficient"] +pub struct ADJRES_R(crate::FieldReader); +impl ADJRES_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ADJRES_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADJRES_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADJRES` writer - Adjusting Result / Division Coefficient"] +pub struct ADJRES_W<'a> { + w: &'a mut W, +} +impl<'a> ADJRES_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 4)) | ((value as u8 & 0x07) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Number of Samples to be Collected"] + #[inline(always)] + pub fn samplenum(&self) -> SAMPLENUM_R { + SAMPLENUM_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:6 - Adjusting Result / Division Coefficient"] + #[inline(always)] + pub fn adjres(&self) -> ADJRES_R { + ADJRES_R::new(((self.bits >> 4) & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Number of Samples to be Collected"] + #[inline(always)] + pub fn samplenum(&mut self) -> SAMPLENUM_W { + SAMPLENUM_W { w: self } + } + #[doc = "Bits 4:6 - Adjusting Result / Division Coefficient"] + #[inline(always)] + pub fn adjres(&mut self) -> ADJRES_W { + ADJRES_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Average Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [avgctrl](index.html) module"] +pub struct AVGCTRL_SPEC; +impl crate::RegisterSpec for AVGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [avgctrl::R](R) reader structure"] +impl crate::Readable for AVGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [avgctrl::W](W) writer structure"] +impl crate::Writable for AVGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets AVGCTRL to value 0"] +impl crate::Resettable for AVGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/adc0/calib.rs b/pac/atsamc21g/src/adc0/calib.rs new file mode 100644 index 000000000000..8a1a99b8c47d --- /dev/null +++ b/pac/atsamc21g/src/adc0/calib.rs @@ -0,0 +1,140 @@ +#[doc = "Register `CALIB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CALIB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BIASCOMP` reader - Bias Comparator Scaling"] +pub struct BIASCOMP_R(crate::FieldReader); +impl BIASCOMP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BIASCOMP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BIASCOMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BIASCOMP` writer - Bias Comparator Scaling"] +pub struct BIASCOMP_W<'a> { + w: &'a mut W, +} +impl<'a> BIASCOMP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u16 & 0x07); + self.w + } +} +#[doc = "Field `BIASREFBUF` reader - Bias Reference Buffer Scaling"] +pub struct BIASREFBUF_R(crate::FieldReader); +impl BIASREFBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BIASREFBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BIASREFBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BIASREFBUF` writer - Bias Reference Buffer Scaling"] +pub struct BIASREFBUF_W<'a> { + w: &'a mut W, +} +impl<'a> BIASREFBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u16 & 0x07) << 8); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Bias Comparator Scaling"] + #[inline(always)] + pub fn biascomp(&self) -> BIASCOMP_R { + BIASCOMP_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bits 8:10 - Bias Reference Buffer Scaling"] + #[inline(always)] + pub fn biasrefbuf(&self) -> BIASREFBUF_R { + BIASREFBUF_R::new(((self.bits >> 8) & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Bias Comparator Scaling"] + #[inline(always)] + pub fn biascomp(&mut self) -> BIASCOMP_W { + BIASCOMP_W { w: self } + } + #[doc = "Bits 8:10 - Bias Reference Buffer Scaling"] + #[inline(always)] + pub fn biasrefbuf(&mut self) -> BIASREFBUF_W { + BIASREFBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Calibration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [calib](index.html) module"] +pub struct CALIB_SPEC; +impl crate::RegisterSpec for CALIB_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [calib::R](R) reader structure"] +impl crate::Readable for CALIB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [calib::W](W) writer structure"] +impl crate::Writable for CALIB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CALIB to value 0"] +impl crate::Resettable for CALIB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/adc0/ctrla.rs b/pac/atsamc21g/src/adc0/ctrla.rs new file mode 100644 index 000000000000..47c681045f95 --- /dev/null +++ b/pac/atsamc21g/src/adc0/ctrla.rs @@ -0,0 +1,301 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SLAVEEN` reader - Slave Enable"] +pub struct SLAVEEN_R(crate::FieldReader); +impl SLAVEEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLAVEEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SLAVEEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLAVEEN` writer - Slave Enable"] +pub struct SLAVEEN_W<'a> { + w: &'a mut W, +} +impl<'a> SLAVEEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run During Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run During Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - On Demand Control"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - On Demand Control"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 5 - Slave Enable"] + #[inline(always)] + pub fn slaveen(&self) -> SLAVEEN_R { + SLAVEEN_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Run During Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 5 - Slave Enable"] + #[inline(always)] + pub fn slaveen(&mut self) -> SLAVEEN_W { + SLAVEEN_W { w: self } + } + #[doc = "Bit 6 - Run During Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/adc0/ctrlb.rs b/pac/atsamc21g/src/adc0/ctrlb.rs new file mode 100644 index 000000000000..4d39688fc975 --- /dev/null +++ b/pac/atsamc21g/src/adc0/ctrlb.rs @@ -0,0 +1,230 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Prescaler Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: Peripheral clock / 2"] + DIV2 = 0, + #[doc = "1: Peripheral clock / 4"] + DIV4 = 1, + #[doc = "2: Peripheral clock / 8"] + DIV8 = 2, + #[doc = "3: Peripheral clock / 16"] + DIV16 = 3, + #[doc = "4: Peripheral clock / 32"] + DIV32 = 4, + #[doc = "5: Peripheral clock / 64"] + DIV64 = 5, + #[doc = "6: Peripheral clock / 128"] + DIV128 = 6, + #[doc = "7: Peripheral clock / 256"] + DIV256 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler Configuration"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PRESCALER_A { + match self.bits { + 0 => PRESCALER_A::DIV2, + 1 => PRESCALER_A::DIV4, + 2 => PRESCALER_A::DIV8, + 3 => PRESCALER_A::DIV16, + 4 => PRESCALER_A::DIV32, + 5 => PRESCALER_A::DIV64, + 6 => PRESCALER_A::DIV128, + 7 => PRESCALER_A::DIV256, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == PRESCALER_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == PRESCALER_A::DIV128 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler Configuration"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Peripheral clock / 2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "Peripheral clock / 4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "Peripheral clock / 8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "Peripheral clock / 16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "Peripheral clock / 32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV32) + } + #[doc = "Peripheral clock / 64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "Peripheral clock / 128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV128) + } + #[doc = "Peripheral clock / 256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Prescaler Configuration"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Prescaler Configuration"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/adc0/ctrlc.rs b/pac/atsamc21g/src/adc0/ctrlc.rs new file mode 100644 index 000000000000..1b6ac5a6ea17 --- /dev/null +++ b/pac/atsamc21g/src/adc0/ctrlc.rs @@ -0,0 +1,624 @@ +#[doc = "Register `CTRLC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIFFMODE` reader - Differential Mode"] +pub struct DIFFMODE_R(crate::FieldReader); +impl DIFFMODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIFFMODE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIFFMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIFFMODE` writer - Differential Mode"] +pub struct DIFFMODE_W<'a> { + w: &'a mut W, +} +impl<'a> DIFFMODE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `LEFTADJ` reader - Left-Adjusted Result"] +pub struct LEFTADJ_R(crate::FieldReader); +impl LEFTADJ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LEFTADJ_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LEFTADJ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LEFTADJ` writer - Left-Adjusted Result"] +pub struct LEFTADJ_W<'a> { + w: &'a mut W, +} +impl<'a> LEFTADJ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `FREERUN` reader - Free Running Mode"] +pub struct FREERUN_R(crate::FieldReader); +impl FREERUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FREERUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FREERUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FREERUN` writer - Free Running Mode"] +pub struct FREERUN_W<'a> { + w: &'a mut W, +} +impl<'a> FREERUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CORREN` reader - Digital Correction Logic Enable"] +pub struct CORREN_R(crate::FieldReader); +impl CORREN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CORREN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CORREN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CORREN` writer - Digital Correction Logic Enable"] +pub struct CORREN_W<'a> { + w: &'a mut W, +} +impl<'a> CORREN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Conversion Result Resolution\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum RESSEL_A { + #[doc = "0: 12-bit"] + _12BIT = 0, + #[doc = "1: 16-bit averaging mode"] + _16BIT = 1, + #[doc = "2: 10-bit"] + _10BIT = 2, + #[doc = "3: 8-bit"] + _8BIT = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RESSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `RESSEL` reader - Conversion Result Resolution"] +pub struct RESSEL_R(crate::FieldReader); +impl RESSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RESSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RESSEL_A { + match self.bits { + 0 => RESSEL_A::_12BIT, + 1 => RESSEL_A::_16BIT, + 2 => RESSEL_A::_10BIT, + 3 => RESSEL_A::_8BIT, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `_12BIT`"] + #[inline(always)] + pub fn is_12bit(&self) -> bool { + **self == RESSEL_A::_12BIT + } + #[doc = "Checks if the value of the field is `_16BIT`"] + #[inline(always)] + pub fn is_16bit(&self) -> bool { + **self == RESSEL_A::_16BIT + } + #[doc = "Checks if the value of the field is `_10BIT`"] + #[inline(always)] + pub fn is_10bit(&self) -> bool { + **self == RESSEL_A::_10BIT + } + #[doc = "Checks if the value of the field is `_8BIT`"] + #[inline(always)] + pub fn is_8bit(&self) -> bool { + **self == RESSEL_A::_8BIT + } +} +impl core::ops::Deref for RESSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESSEL` writer - Conversion Result Resolution"] +pub struct RESSEL_W<'a> { + w: &'a mut W, +} +impl<'a> RESSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RESSEL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "12-bit"] + #[inline(always)] + pub fn _12bit(self) -> &'a mut W { + self.variant(RESSEL_A::_12BIT) + } + #[doc = "16-bit averaging mode"] + #[inline(always)] + pub fn _16bit(self) -> &'a mut W { + self.variant(RESSEL_A::_16BIT) + } + #[doc = "10-bit"] + #[inline(always)] + pub fn _10bit(self) -> &'a mut W { + self.variant(RESSEL_A::_10BIT) + } + #[doc = "8-bit"] + #[inline(always)] + pub fn _8bit(self) -> &'a mut W { + self.variant(RESSEL_A::_8BIT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u16 & 0x03) << 4); + self.w + } +} +#[doc = "Field `R2R` reader - Rail-to-Rail mode enable"] +pub struct R2R_R(crate::FieldReader); +impl R2R_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + R2R_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for R2R_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `R2R` writer - Rail-to-Rail mode enable"] +pub struct R2R_W<'a> { + w: &'a mut W, +} +impl<'a> R2R_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Window Monitor Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WINMODE_A { + #[doc = "0: No window mode (default)"] + DISABLE = 0, + #[doc = "1: RESULT > WINLT"] + MODE1 = 1, + #[doc = "2: RESULT < WINUT"] + MODE2 = 2, + #[doc = "3: WINLT < RESULT < WINUT"] + MODE3 = 3, + #[doc = "4: !(WINLT < RESULT < WINUT)"] + MODE4 = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WINMODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `WINMODE` reader - Window Monitor Mode"] +pub struct WINMODE_R(crate::FieldReader); +impl WINMODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WINMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(WINMODE_A::DISABLE), + 1 => Some(WINMODE_A::MODE1), + 2 => Some(WINMODE_A::MODE2), + 3 => Some(WINMODE_A::MODE3), + 4 => Some(WINMODE_A::MODE4), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == WINMODE_A::DISABLE + } + #[doc = "Checks if the value of the field is `MODE1`"] + #[inline(always)] + pub fn is_mode1(&self) -> bool { + **self == WINMODE_A::MODE1 + } + #[doc = "Checks if the value of the field is `MODE2`"] + #[inline(always)] + pub fn is_mode2(&self) -> bool { + **self == WINMODE_A::MODE2 + } + #[doc = "Checks if the value of the field is `MODE3`"] + #[inline(always)] + pub fn is_mode3(&self) -> bool { + **self == WINMODE_A::MODE3 + } + #[doc = "Checks if the value of the field is `MODE4`"] + #[inline(always)] + pub fn is_mode4(&self) -> bool { + **self == WINMODE_A::MODE4 + } +} +impl core::ops::Deref for WINMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMODE` writer - Window Monitor Mode"] +pub struct WINMODE_W<'a> { + w: &'a mut W, +} +impl<'a> WINMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WINMODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No window mode (default)"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(WINMODE_A::DISABLE) + } + #[doc = "RESULT > WINLT"] + #[inline(always)] + pub fn mode1(self) -> &'a mut W { + self.variant(WINMODE_A::MODE1) + } + #[doc = "RESULT < WINUT"] + #[inline(always)] + pub fn mode2(self) -> &'a mut W { + self.variant(WINMODE_A::MODE2) + } + #[doc = "WINLT < RESULT < WINUT"] + #[inline(always)] + pub fn mode3(self) -> &'a mut W { + self.variant(WINMODE_A::MODE3) + } + #[doc = "!(WINLT < RESULT < WINUT)"] + #[inline(always)] + pub fn mode4(self) -> &'a mut W { + self.variant(WINMODE_A::MODE4) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u16 & 0x07) << 8); + self.w + } +} +#[doc = "Dual Mode Trigger Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DUALSEL_A { + #[doc = "0: Start event or software trigger will start a conversion on both ADCs"] + BOTH = 0, + #[doc = "1: START event or software trigger will alternately start a conversion on ADC0 and ADC1"] + INTERLEAVE = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DUALSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `DUALSEL` reader - Dual Mode Trigger Selection"] +pub struct DUALSEL_R(crate::FieldReader); +impl DUALSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DUALSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(DUALSEL_A::BOTH), + 1 => Some(DUALSEL_A::INTERLEAVE), + _ => None, + } + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == DUALSEL_A::BOTH + } + #[doc = "Checks if the value of the field is `INTERLEAVE`"] + #[inline(always)] + pub fn is_interleave(&self) -> bool { + **self == DUALSEL_A::INTERLEAVE + } +} +impl core::ops::Deref for DUALSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DUALSEL` writer - Dual Mode Trigger Selection"] +pub struct DUALSEL_W<'a> { + w: &'a mut W, +} +impl<'a> DUALSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DUALSEL_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Start event or software trigger will start a conversion on both ADCs"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(DUALSEL_A::BOTH) + } + #[doc = "START event or software trigger will alternately start a conversion on ADC0 and ADC1"] + #[inline(always)] + pub fn interleave(self) -> &'a mut W { + self.variant(DUALSEL_A::INTERLEAVE) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 12)) | ((value as u16 & 0x03) << 12); + self.w + } +} +impl R { + #[doc = "Bit 0 - Differential Mode"] + #[inline(always)] + pub fn diffmode(&self) -> DIFFMODE_R { + DIFFMODE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Left-Adjusted Result"] + #[inline(always)] + pub fn leftadj(&self) -> LEFTADJ_R { + LEFTADJ_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Free Running Mode"] + #[inline(always)] + pub fn freerun(&self) -> FREERUN_R { + FREERUN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Digital Correction Logic Enable"] + #[inline(always)] + pub fn corren(&self) -> CORREN_R { + CORREN_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bits 4:5 - Conversion Result Resolution"] + #[inline(always)] + pub fn ressel(&self) -> RESSEL_R { + RESSEL_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bit 7 - Rail-to-Rail mode enable"] + #[inline(always)] + pub fn r2r(&self) -> R2R_R { + R2R_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Window Monitor Mode"] + #[inline(always)] + pub fn winmode(&self) -> WINMODE_R { + WINMODE_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bits 12:13 - Dual Mode Trigger Selection"] + #[inline(always)] + pub fn dualsel(&self) -> DUALSEL_R { + DUALSEL_R::new(((self.bits >> 12) & 0x03) as u8) + } +} +impl W { + #[doc = "Bit 0 - Differential Mode"] + #[inline(always)] + pub fn diffmode(&mut self) -> DIFFMODE_W { + DIFFMODE_W { w: self } + } + #[doc = "Bit 1 - Left-Adjusted Result"] + #[inline(always)] + pub fn leftadj(&mut self) -> LEFTADJ_W { + LEFTADJ_W { w: self } + } + #[doc = "Bit 2 - Free Running Mode"] + #[inline(always)] + pub fn freerun(&mut self) -> FREERUN_W { + FREERUN_W { w: self } + } + #[doc = "Bit 3 - Digital Correction Logic Enable"] + #[inline(always)] + pub fn corren(&mut self) -> CORREN_W { + CORREN_W { w: self } + } + #[doc = "Bits 4:5 - Conversion Result Resolution"] + #[inline(always)] + pub fn ressel(&mut self) -> RESSEL_W { + RESSEL_W { w: self } + } + #[doc = "Bit 7 - Rail-to-Rail mode enable"] + #[inline(always)] + pub fn r2r(&mut self) -> R2R_W { + R2R_W { w: self } + } + #[doc = "Bits 8:10 - Window Monitor Mode"] + #[inline(always)] + pub fn winmode(&mut self) -> WINMODE_W { + WINMODE_W { w: self } + } + #[doc = "Bits 12:13 - Dual Mode Trigger Selection"] + #[inline(always)] + pub fn dualsel(&mut self) -> DUALSEL_W { + DUALSEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control C\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlc](index.html) module"] +pub struct CTRLC_SPEC; +impl crate::RegisterSpec for CTRLC_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrlc::R](R) reader structure"] +impl crate::Readable for CTRLC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlc::W](W) writer structure"] +impl crate::Writable for CTRLC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLC to value 0"] +impl crate::Resettable for CTRLC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/adc0/dbgctrl.rs b/pac/atsamc21g/src/adc0/dbgctrl.rs new file mode 100644 index 000000000000..53636eb2b339 --- /dev/null +++ b/pac/atsamc21g/src/adc0/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Debug Run"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Debug Run"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/adc0/evctrl.rs b/pac/atsamc21g/src/adc0/evctrl.rs new file mode 100644 index 000000000000..295508f82de3 --- /dev/null +++ b/pac/atsamc21g/src/adc0/evctrl.rs @@ -0,0 +1,348 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FLUSHEI` reader - Flush Event Input Enable"] +pub struct FLUSHEI_R(crate::FieldReader); +impl FLUSHEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FLUSHEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FLUSHEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLUSHEI` writer - Flush Event Input Enable"] +pub struct FLUSHEI_W<'a> { + w: &'a mut W, +} +impl<'a> FLUSHEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `STARTEI` reader - Start Conversion Event Input Enable"] +pub struct STARTEI_R(crate::FieldReader); +impl STARTEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STARTEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STARTEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STARTEI` writer - Start Conversion Event Input Enable"] +pub struct STARTEI_W<'a> { + w: &'a mut W, +} +impl<'a> STARTEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `FLUSHINV` reader - Flush Event Invert Enable"] +pub struct FLUSHINV_R(crate::FieldReader); +impl FLUSHINV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FLUSHINV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FLUSHINV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLUSHINV` writer - Flush Event Invert Enable"] +pub struct FLUSHINV_W<'a> { + w: &'a mut W, +} +impl<'a> FLUSHINV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `STARTINV` reader - Start Event Invert Enable"] +pub struct STARTINV_R(crate::FieldReader); +impl STARTINV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STARTINV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STARTINV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STARTINV` writer - Start Event Invert Enable"] +pub struct STARTINV_W<'a> { + w: &'a mut W, +} +impl<'a> STARTINV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `RESRDYEO` reader - Result Ready Event Out"] +pub struct RESRDYEO_R(crate::FieldReader); +impl RESRDYEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESRDYEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESRDYEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESRDYEO` writer - Result Ready Event Out"] +pub struct RESRDYEO_W<'a> { + w: &'a mut W, +} +impl<'a> RESRDYEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `WINMONEO` reader - Window Monitor Event Out"] +pub struct WINMONEO_R(crate::FieldReader); +impl WINMONEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINMONEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINMONEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMONEO` writer - Window Monitor Event Out"] +pub struct WINMONEO_W<'a> { + w: &'a mut W, +} +impl<'a> WINMONEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Flush Event Input Enable"] + #[inline(always)] + pub fn flushei(&self) -> FLUSHEI_R { + FLUSHEI_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Start Conversion Event Input Enable"] + #[inline(always)] + pub fn startei(&self) -> STARTEI_R { + STARTEI_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Flush Event Invert Enable"] + #[inline(always)] + pub fn flushinv(&self) -> FLUSHINV_R { + FLUSHINV_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Start Event Invert Enable"] + #[inline(always)] + pub fn startinv(&self) -> STARTINV_R { + STARTINV_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Result Ready Event Out"] + #[inline(always)] + pub fn resrdyeo(&self) -> RESRDYEO_R { + RESRDYEO_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Window Monitor Event Out"] + #[inline(always)] + pub fn winmoneo(&self) -> WINMONEO_R { + WINMONEO_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Flush Event Input Enable"] + #[inline(always)] + pub fn flushei(&mut self) -> FLUSHEI_W { + FLUSHEI_W { w: self } + } + #[doc = "Bit 1 - Start Conversion Event Input Enable"] + #[inline(always)] + pub fn startei(&mut self) -> STARTEI_W { + STARTEI_W { w: self } + } + #[doc = "Bit 2 - Flush Event Invert Enable"] + #[inline(always)] + pub fn flushinv(&mut self) -> FLUSHINV_W { + FLUSHINV_W { w: self } + } + #[doc = "Bit 3 - Start Event Invert Enable"] + #[inline(always)] + pub fn startinv(&mut self) -> STARTINV_W { + STARTINV_W { w: self } + } + #[doc = "Bit 4 - Result Ready Event Out"] + #[inline(always)] + pub fn resrdyeo(&mut self) -> RESRDYEO_W { + RESRDYEO_W { w: self } + } + #[doc = "Bit 5 - Window Monitor Event Out"] + #[inline(always)] + pub fn winmoneo(&mut self) -> WINMONEO_W { + WINMONEO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/adc0/gaincorr.rs b/pac/atsamc21g/src/adc0/gaincorr.rs new file mode 100644 index 000000000000..496cb8c6021c --- /dev/null +++ b/pac/atsamc21g/src/adc0/gaincorr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `GAINCORR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GAINCORR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `GAINCORR` reader - Gain Correction Value"] +pub struct GAINCORR_R(crate::FieldReader); +impl GAINCORR_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + GAINCORR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GAINCORR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GAINCORR` writer - Gain Correction Value"] +pub struct GAINCORR_W<'a> { + w: &'a mut W, +} +impl<'a> GAINCORR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0fff) | (value as u16 & 0x0fff); + self.w + } +} +impl R { + #[doc = "Bits 0:11 - Gain Correction Value"] + #[inline(always)] + pub fn gaincorr(&self) -> GAINCORR_R { + GAINCORR_R::new((self.bits & 0x0fff) as u16) + } +} +impl W { + #[doc = "Bits 0:11 - Gain Correction Value"] + #[inline(always)] + pub fn gaincorr(&mut self) -> GAINCORR_W { + GAINCORR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Gain Correction\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gaincorr](index.html) module"] +pub struct GAINCORR_SPEC; +impl crate::RegisterSpec for GAINCORR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [gaincorr::R](R) reader structure"] +impl crate::Readable for GAINCORR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gaincorr::W](W) writer structure"] +impl crate::Writable for GAINCORR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets GAINCORR to value 0"] +impl crate::Resettable for GAINCORR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/adc0/inputctrl.rs b/pac/atsamc21g/src/adc0/inputctrl.rs new file mode 100644 index 000000000000..82367a5d38c7 --- /dev/null +++ b/pac/atsamc21g/src/adc0/inputctrl.rs @@ -0,0 +1,485 @@ +#[doc = "Register `INPUTCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INPUTCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Positive Mux Input Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MUXPOS_A { + #[doc = "0: ADC AIN0 Pin"] + AIN0 = 0, + #[doc = "1: ADC AIN1 Pin"] + AIN1 = 1, + #[doc = "2: ADC AIN2 Pin"] + AIN2 = 2, + #[doc = "3: ADC AIN3 Pin"] + AIN3 = 3, + #[doc = "4: ADC AIN4 Pin"] + AIN4 = 4, + #[doc = "5: ADC AIN5 Pin"] + AIN5 = 5, + #[doc = "6: ADC AIN6 Pin"] + AIN6 = 6, + #[doc = "7: ADC AIN7 Pin"] + AIN7 = 7, + #[doc = "8: ADC AIN8 Pin"] + AIN8 = 8, + #[doc = "9: ADC AIN9 Pin"] + AIN9 = 9, + #[doc = "10: ADC AIN10 Pin"] + AIN10 = 10, + #[doc = "11: ADC AIN11 Pin"] + AIN11 = 11, + #[doc = "25: Bandgap Voltage"] + BANDGAP = 25, + #[doc = "26: 1/4 Scaled Core Supply"] + SCALEDCOREVCC = 26, + #[doc = "27: 1/4 Scaled I/O Supply"] + SCALEDIOVCC = 27, + #[doc = "28: DAC Output"] + DAC = 28, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MUXPOS_A) -> Self { + variant as _ + } +} +#[doc = "Field `MUXPOS` reader - Positive Mux Input Selection"] +pub struct MUXPOS_R(crate::FieldReader); +impl MUXPOS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MUXPOS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MUXPOS_A::AIN0), + 1 => Some(MUXPOS_A::AIN1), + 2 => Some(MUXPOS_A::AIN2), + 3 => Some(MUXPOS_A::AIN3), + 4 => Some(MUXPOS_A::AIN4), + 5 => Some(MUXPOS_A::AIN5), + 6 => Some(MUXPOS_A::AIN6), + 7 => Some(MUXPOS_A::AIN7), + 8 => Some(MUXPOS_A::AIN8), + 9 => Some(MUXPOS_A::AIN9), + 10 => Some(MUXPOS_A::AIN10), + 11 => Some(MUXPOS_A::AIN11), + 25 => Some(MUXPOS_A::BANDGAP), + 26 => Some(MUXPOS_A::SCALEDCOREVCC), + 27 => Some(MUXPOS_A::SCALEDIOVCC), + 28 => Some(MUXPOS_A::DAC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `AIN0`"] + #[inline(always)] + pub fn is_ain0(&self) -> bool { + **self == MUXPOS_A::AIN0 + } + #[doc = "Checks if the value of the field is `AIN1`"] + #[inline(always)] + pub fn is_ain1(&self) -> bool { + **self == MUXPOS_A::AIN1 + } + #[doc = "Checks if the value of the field is `AIN2`"] + #[inline(always)] + pub fn is_ain2(&self) -> bool { + **self == MUXPOS_A::AIN2 + } + #[doc = "Checks if the value of the field is `AIN3`"] + #[inline(always)] + pub fn is_ain3(&self) -> bool { + **self == MUXPOS_A::AIN3 + } + #[doc = "Checks if the value of the field is `AIN4`"] + #[inline(always)] + pub fn is_ain4(&self) -> bool { + **self == MUXPOS_A::AIN4 + } + #[doc = "Checks if the value of the field is `AIN5`"] + #[inline(always)] + pub fn is_ain5(&self) -> bool { + **self == MUXPOS_A::AIN5 + } + #[doc = "Checks if the value of the field is `AIN6`"] + #[inline(always)] + pub fn is_ain6(&self) -> bool { + **self == MUXPOS_A::AIN6 + } + #[doc = "Checks if the value of the field is `AIN7`"] + #[inline(always)] + pub fn is_ain7(&self) -> bool { + **self == MUXPOS_A::AIN7 + } + #[doc = "Checks if the value of the field is `AIN8`"] + #[inline(always)] + pub fn is_ain8(&self) -> bool { + **self == MUXPOS_A::AIN8 + } + #[doc = "Checks if the value of the field is `AIN9`"] + #[inline(always)] + pub fn is_ain9(&self) -> bool { + **self == MUXPOS_A::AIN9 + } + #[doc = "Checks if the value of the field is `AIN10`"] + #[inline(always)] + pub fn is_ain10(&self) -> bool { + **self == MUXPOS_A::AIN10 + } + #[doc = "Checks if the value of the field is `AIN11`"] + #[inline(always)] + pub fn is_ain11(&self) -> bool { + **self == MUXPOS_A::AIN11 + } + #[doc = "Checks if the value of the field is `BANDGAP`"] + #[inline(always)] + pub fn is_bandgap(&self) -> bool { + **self == MUXPOS_A::BANDGAP + } + #[doc = "Checks if the value of the field is `SCALEDCOREVCC`"] + #[inline(always)] + pub fn is_scaledcorevcc(&self) -> bool { + **self == MUXPOS_A::SCALEDCOREVCC + } + #[doc = "Checks if the value of the field is `SCALEDIOVCC`"] + #[inline(always)] + pub fn is_scalediovcc(&self) -> bool { + **self == MUXPOS_A::SCALEDIOVCC + } + #[doc = "Checks if the value of the field is `DAC`"] + #[inline(always)] + pub fn is_dac(&self) -> bool { + **self == MUXPOS_A::DAC + } +} +impl core::ops::Deref for MUXPOS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MUXPOS` writer - Positive Mux Input Selection"] +pub struct MUXPOS_W<'a> { + w: &'a mut W, +} +impl<'a> MUXPOS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MUXPOS_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "ADC AIN0 Pin"] + #[inline(always)] + pub fn ain0(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN0) + } + #[doc = "ADC AIN1 Pin"] + #[inline(always)] + pub fn ain1(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN1) + } + #[doc = "ADC AIN2 Pin"] + #[inline(always)] + pub fn ain2(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN2) + } + #[doc = "ADC AIN3 Pin"] + #[inline(always)] + pub fn ain3(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN3) + } + #[doc = "ADC AIN4 Pin"] + #[inline(always)] + pub fn ain4(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN4) + } + #[doc = "ADC AIN5 Pin"] + #[inline(always)] + pub fn ain5(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN5) + } + #[doc = "ADC AIN6 Pin"] + #[inline(always)] + pub fn ain6(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN6) + } + #[doc = "ADC AIN7 Pin"] + #[inline(always)] + pub fn ain7(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN7) + } + #[doc = "ADC AIN8 Pin"] + #[inline(always)] + pub fn ain8(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN8) + } + #[doc = "ADC AIN9 Pin"] + #[inline(always)] + pub fn ain9(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN9) + } + #[doc = "ADC AIN10 Pin"] + #[inline(always)] + pub fn ain10(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN10) + } + #[doc = "ADC AIN11 Pin"] + #[inline(always)] + pub fn ain11(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN11) + } + #[doc = "Bandgap Voltage"] + #[inline(always)] + pub fn bandgap(self) -> &'a mut W { + self.variant(MUXPOS_A::BANDGAP) + } + #[doc = "1/4 Scaled Core Supply"] + #[inline(always)] + pub fn scaledcorevcc(self) -> &'a mut W { + self.variant(MUXPOS_A::SCALEDCOREVCC) + } + #[doc = "1/4 Scaled I/O Supply"] + #[inline(always)] + pub fn scalediovcc(self) -> &'a mut W { + self.variant(MUXPOS_A::SCALEDIOVCC) + } + #[doc = "DAC Output"] + #[inline(always)] + pub fn dac(self) -> &'a mut W { + self.variant(MUXPOS_A::DAC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u16 & 0x1f); + self.w + } +} +#[doc = "Negative Mux Input Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MUXNEG_A { + #[doc = "0: ADC AIN0 Pin"] + AIN0 = 0, + #[doc = "1: ADC AIN1 Pin"] + AIN1 = 1, + #[doc = "2: ADC AIN2 Pin"] + AIN2 = 2, + #[doc = "3: ADC AIN3 Pin"] + AIN3 = 3, + #[doc = "4: ADC AIN4 Pin"] + AIN4 = 4, + #[doc = "5: ADC AIN5 Pin"] + AIN5 = 5, + #[doc = "24: Internal Ground"] + GND = 24, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MUXNEG_A) -> Self { + variant as _ + } +} +#[doc = "Field `MUXNEG` reader - Negative Mux Input Selection"] +pub struct MUXNEG_R(crate::FieldReader); +impl MUXNEG_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MUXNEG_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MUXNEG_A::AIN0), + 1 => Some(MUXNEG_A::AIN1), + 2 => Some(MUXNEG_A::AIN2), + 3 => Some(MUXNEG_A::AIN3), + 4 => Some(MUXNEG_A::AIN4), + 5 => Some(MUXNEG_A::AIN5), + 24 => Some(MUXNEG_A::GND), + _ => None, + } + } + #[doc = "Checks if the value of the field is `AIN0`"] + #[inline(always)] + pub fn is_ain0(&self) -> bool { + **self == MUXNEG_A::AIN0 + } + #[doc = "Checks if the value of the field is `AIN1`"] + #[inline(always)] + pub fn is_ain1(&self) -> bool { + **self == MUXNEG_A::AIN1 + } + #[doc = "Checks if the value of the field is `AIN2`"] + #[inline(always)] + pub fn is_ain2(&self) -> bool { + **self == MUXNEG_A::AIN2 + } + #[doc = "Checks if the value of the field is `AIN3`"] + #[inline(always)] + pub fn is_ain3(&self) -> bool { + **self == MUXNEG_A::AIN3 + } + #[doc = "Checks if the value of the field is `AIN4`"] + #[inline(always)] + pub fn is_ain4(&self) -> bool { + **self == MUXNEG_A::AIN4 + } + #[doc = "Checks if the value of the field is `AIN5`"] + #[inline(always)] + pub fn is_ain5(&self) -> bool { + **self == MUXNEG_A::AIN5 + } + #[doc = "Checks if the value of the field is `GND`"] + #[inline(always)] + pub fn is_gnd(&self) -> bool { + **self == MUXNEG_A::GND + } +} +impl core::ops::Deref for MUXNEG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MUXNEG` writer - Negative Mux Input Selection"] +pub struct MUXNEG_W<'a> { + w: &'a mut W, +} +impl<'a> MUXNEG_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MUXNEG_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "ADC AIN0 Pin"] + #[inline(always)] + pub fn ain0(self) -> &'a mut W { + self.variant(MUXNEG_A::AIN0) + } + #[doc = "ADC AIN1 Pin"] + #[inline(always)] + pub fn ain1(self) -> &'a mut W { + self.variant(MUXNEG_A::AIN1) + } + #[doc = "ADC AIN2 Pin"] + #[inline(always)] + pub fn ain2(self) -> &'a mut W { + self.variant(MUXNEG_A::AIN2) + } + #[doc = "ADC AIN3 Pin"] + #[inline(always)] + pub fn ain3(self) -> &'a mut W { + self.variant(MUXNEG_A::AIN3) + } + #[doc = "ADC AIN4 Pin"] + #[inline(always)] + pub fn ain4(self) -> &'a mut W { + self.variant(MUXNEG_A::AIN4) + } + #[doc = "ADC AIN5 Pin"] + #[inline(always)] + pub fn ain5(self) -> &'a mut W { + self.variant(MUXNEG_A::AIN5) + } + #[doc = "Internal Ground"] + #[inline(always)] + pub fn gnd(self) -> &'a mut W { + self.variant(MUXNEG_A::GND) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 8)) | ((value as u16 & 0x1f) << 8); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Positive Mux Input Selection"] + #[inline(always)] + pub fn muxpos(&self) -> MUXPOS_R { + MUXPOS_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 8:12 - Negative Mux Input Selection"] + #[inline(always)] + pub fn muxneg(&self) -> MUXNEG_R { + MUXNEG_R::new(((self.bits >> 8) & 0x1f) as u8) + } +} +impl W { + #[doc = "Bits 0:4 - Positive Mux Input Selection"] + #[inline(always)] + pub fn muxpos(&mut self) -> MUXPOS_W { + MUXPOS_W { w: self } + } + #[doc = "Bits 8:12 - Negative Mux Input Selection"] + #[inline(always)] + pub fn muxneg(&mut self) -> MUXNEG_W { + MUXNEG_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Input Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [inputctrl](index.html) module"] +pub struct INPUTCTRL_SPEC; +impl crate::RegisterSpec for INPUTCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [inputctrl::R](R) reader structure"] +impl crate::Readable for INPUTCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [inputctrl::W](W) writer structure"] +impl crate::Writable for INPUTCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INPUTCTRL to value 0"] +impl crate::Resettable for INPUTCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/adc0/intenclr.rs b/pac/atsamc21g/src/adc0/intenclr.rs new file mode 100644 index 000000000000..b10f428d30b1 --- /dev/null +++ b/pac/atsamc21g/src/adc0/intenclr.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RESRDY` reader - Result Ready Interrupt Disable"] +pub struct RESRDY_R(crate::FieldReader); +impl RESRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESRDY` writer - Result Ready Interrupt Disable"] +pub struct RESRDY_W<'a> { + w: &'a mut W, +} +impl<'a> RESRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `OVERRUN` reader - Overrun Interrupt Disable"] +pub struct OVERRUN_R(crate::FieldReader); +impl OVERRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVERRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVERRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVERRUN` writer - Overrun Interrupt Disable"] +pub struct OVERRUN_W<'a> { + w: &'a mut W, +} +impl<'a> OVERRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WINMON` reader - Window Monitor Interrupt Disable"] +pub struct WINMON_R(crate::FieldReader); +impl WINMON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINMON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINMON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMON` writer - Window Monitor Interrupt Disable"] +pub struct WINMON_W<'a> { + w: &'a mut W, +} +impl<'a> WINMON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Result Ready Interrupt Disable"] + #[inline(always)] + pub fn resrdy(&self) -> RESRDY_R { + RESRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Overrun Interrupt Disable"] + #[inline(always)] + pub fn overrun(&self) -> OVERRUN_R { + OVERRUN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Window Monitor Interrupt Disable"] + #[inline(always)] + pub fn winmon(&self) -> WINMON_R { + WINMON_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Result Ready Interrupt Disable"] + #[inline(always)] + pub fn resrdy(&mut self) -> RESRDY_W { + RESRDY_W { w: self } + } + #[doc = "Bit 1 - Overrun Interrupt Disable"] + #[inline(always)] + pub fn overrun(&mut self) -> OVERRUN_W { + OVERRUN_W { w: self } + } + #[doc = "Bit 2 - Window Monitor Interrupt Disable"] + #[inline(always)] + pub fn winmon(&mut self) -> WINMON_W { + WINMON_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/adc0/intenset.rs b/pac/atsamc21g/src/adc0/intenset.rs new file mode 100644 index 000000000000..5ca93b05b859 --- /dev/null +++ b/pac/atsamc21g/src/adc0/intenset.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RESRDY` reader - Result Ready Interrupt Enable"] +pub struct RESRDY_R(crate::FieldReader); +impl RESRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESRDY` writer - Result Ready Interrupt Enable"] +pub struct RESRDY_W<'a> { + w: &'a mut W, +} +impl<'a> RESRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `OVERRUN` reader - Overrun Interrupt Enable"] +pub struct OVERRUN_R(crate::FieldReader); +impl OVERRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVERRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVERRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVERRUN` writer - Overrun Interrupt Enable"] +pub struct OVERRUN_W<'a> { + w: &'a mut W, +} +impl<'a> OVERRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WINMON` reader - Window Monitor Interrupt Enable"] +pub struct WINMON_R(crate::FieldReader); +impl WINMON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINMON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINMON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMON` writer - Window Monitor Interrupt Enable"] +pub struct WINMON_W<'a> { + w: &'a mut W, +} +impl<'a> WINMON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Result Ready Interrupt Enable"] + #[inline(always)] + pub fn resrdy(&self) -> RESRDY_R { + RESRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Overrun Interrupt Enable"] + #[inline(always)] + pub fn overrun(&self) -> OVERRUN_R { + OVERRUN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Window Monitor Interrupt Enable"] + #[inline(always)] + pub fn winmon(&self) -> WINMON_R { + WINMON_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Result Ready Interrupt Enable"] + #[inline(always)] + pub fn resrdy(&mut self) -> RESRDY_W { + RESRDY_W { w: self } + } + #[doc = "Bit 1 - Overrun Interrupt Enable"] + #[inline(always)] + pub fn overrun(&mut self) -> OVERRUN_W { + OVERRUN_W { w: self } + } + #[doc = "Bit 2 - Window Monitor Interrupt Enable"] + #[inline(always)] + pub fn winmon(&mut self) -> WINMON_W { + WINMON_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/adc0/intflag.rs b/pac/atsamc21g/src/adc0/intflag.rs new file mode 100644 index 000000000000..3cd74788b226 --- /dev/null +++ b/pac/atsamc21g/src/adc0/intflag.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RESRDY` reader - Result Ready Interrupt Flag"] +pub struct RESRDY_R(crate::FieldReader); +impl RESRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESRDY` writer - Result Ready Interrupt Flag"] +pub struct RESRDY_W<'a> { + w: &'a mut W, +} +impl<'a> RESRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `OVERRUN` reader - Overrun Interrupt Flag"] +pub struct OVERRUN_R(crate::FieldReader); +impl OVERRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVERRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVERRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVERRUN` writer - Overrun Interrupt Flag"] +pub struct OVERRUN_W<'a> { + w: &'a mut W, +} +impl<'a> OVERRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WINMON` reader - Window Monitor Interrupt Flag"] +pub struct WINMON_R(crate::FieldReader); +impl WINMON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINMON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINMON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMON` writer - Window Monitor Interrupt Flag"] +pub struct WINMON_W<'a> { + w: &'a mut W, +} +impl<'a> WINMON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Result Ready Interrupt Flag"] + #[inline(always)] + pub fn resrdy(&self) -> RESRDY_R { + RESRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Overrun Interrupt Flag"] + #[inline(always)] + pub fn overrun(&self) -> OVERRUN_R { + OVERRUN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Window Monitor Interrupt Flag"] + #[inline(always)] + pub fn winmon(&self) -> WINMON_R { + WINMON_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Result Ready Interrupt Flag"] + #[inline(always)] + pub fn resrdy(&mut self) -> RESRDY_W { + RESRDY_W { w: self } + } + #[doc = "Bit 1 - Overrun Interrupt Flag"] + #[inline(always)] + pub fn overrun(&mut self) -> OVERRUN_W { + OVERRUN_W { w: self } + } + #[doc = "Bit 2 - Window Monitor Interrupt Flag"] + #[inline(always)] + pub fn winmon(&mut self) -> WINMON_W { + WINMON_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/adc0/offsetcorr.rs b/pac/atsamc21g/src/adc0/offsetcorr.rs new file mode 100644 index 000000000000..24a97427c64e --- /dev/null +++ b/pac/atsamc21g/src/adc0/offsetcorr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `OFFSETCORR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OFFSETCORR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OFFSETCORR` reader - Offset Correction Value"] +pub struct OFFSETCORR_R(crate::FieldReader); +impl OFFSETCORR_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + OFFSETCORR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OFFSETCORR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OFFSETCORR` writer - Offset Correction Value"] +pub struct OFFSETCORR_W<'a> { + w: &'a mut W, +} +impl<'a> OFFSETCORR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0fff) | (value as u16 & 0x0fff); + self.w + } +} +impl R { + #[doc = "Bits 0:11 - Offset Correction Value"] + #[inline(always)] + pub fn offsetcorr(&self) -> OFFSETCORR_R { + OFFSETCORR_R::new((self.bits & 0x0fff) as u16) + } +} +impl W { + #[doc = "Bits 0:11 - Offset Correction Value"] + #[inline(always)] + pub fn offsetcorr(&mut self) -> OFFSETCORR_W { + OFFSETCORR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Offset Correction\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [offsetcorr](index.html) module"] +pub struct OFFSETCORR_SPEC; +impl crate::RegisterSpec for OFFSETCORR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [offsetcorr::R](R) reader structure"] +impl crate::Readable for OFFSETCORR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [offsetcorr::W](W) writer structure"] +impl crate::Writable for OFFSETCORR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OFFSETCORR to value 0"] +impl crate::Resettable for OFFSETCORR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/adc0/refctrl.rs b/pac/atsamc21g/src/adc0/refctrl.rs new file mode 100644 index 000000000000..007d86e306bc --- /dev/null +++ b/pac/atsamc21g/src/adc0/refctrl.rs @@ -0,0 +1,251 @@ +#[doc = "Register `REFCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `REFCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Reference Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum REFSEL_A { + #[doc = "0: Internal Bandgap Reference"] + INTREF = 0, + #[doc = "1: 1/1.6 VDDANA"] + INTVCC0 = 1, + #[doc = "2: 1/2 VDDANA"] + INTVCC1 = 2, + #[doc = "3: External Reference"] + AREFA = 3, + #[doc = "4: DAC"] + DAC = 4, + #[doc = "5: VDDANA"] + INTVCC2 = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: REFSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `REFSEL` reader - Reference Selection"] +pub struct REFSEL_R(crate::FieldReader); +impl REFSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REFSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(REFSEL_A::INTREF), + 1 => Some(REFSEL_A::INTVCC0), + 2 => Some(REFSEL_A::INTVCC1), + 3 => Some(REFSEL_A::AREFA), + 4 => Some(REFSEL_A::DAC), + 5 => Some(REFSEL_A::INTVCC2), + _ => None, + } + } + #[doc = "Checks if the value of the field is `INTREF`"] + #[inline(always)] + pub fn is_intref(&self) -> bool { + **self == REFSEL_A::INTREF + } + #[doc = "Checks if the value of the field is `INTVCC0`"] + #[inline(always)] + pub fn is_intvcc0(&self) -> bool { + **self == REFSEL_A::INTVCC0 + } + #[doc = "Checks if the value of the field is `INTVCC1`"] + #[inline(always)] + pub fn is_intvcc1(&self) -> bool { + **self == REFSEL_A::INTVCC1 + } + #[doc = "Checks if the value of the field is `AREFA`"] + #[inline(always)] + pub fn is_arefa(&self) -> bool { + **self == REFSEL_A::AREFA + } + #[doc = "Checks if the value of the field is `DAC`"] + #[inline(always)] + pub fn is_dac(&self) -> bool { + **self == REFSEL_A::DAC + } + #[doc = "Checks if the value of the field is `INTVCC2`"] + #[inline(always)] + pub fn is_intvcc2(&self) -> bool { + **self == REFSEL_A::INTVCC2 + } +} +impl core::ops::Deref for REFSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REFSEL` writer - Reference Selection"] +pub struct REFSEL_W<'a> { + w: &'a mut W, +} +impl<'a> REFSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: REFSEL_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Internal Bandgap Reference"] + #[inline(always)] + pub fn intref(self) -> &'a mut W { + self.variant(REFSEL_A::INTREF) + } + #[doc = "1/1.6 VDDANA"] + #[inline(always)] + pub fn intvcc0(self) -> &'a mut W { + self.variant(REFSEL_A::INTVCC0) + } + #[doc = "1/2 VDDANA"] + #[inline(always)] + pub fn intvcc1(self) -> &'a mut W { + self.variant(REFSEL_A::INTVCC1) + } + #[doc = "External Reference"] + #[inline(always)] + pub fn arefa(self) -> &'a mut W { + self.variant(REFSEL_A::AREFA) + } + #[doc = "DAC"] + #[inline(always)] + pub fn dac(self) -> &'a mut W { + self.variant(REFSEL_A::DAC) + } + #[doc = "VDDANA"] + #[inline(always)] + pub fn intvcc2(self) -> &'a mut W { + self.variant(REFSEL_A::INTVCC2) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +#[doc = "Field `REFCOMP` reader - Reference Buffer Offset Compensation Enable"] +pub struct REFCOMP_R(crate::FieldReader); +impl REFCOMP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + REFCOMP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REFCOMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REFCOMP` writer - Reference Buffer Offset Compensation Enable"] +pub struct REFCOMP_W<'a> { + w: &'a mut W, +} +impl<'a> REFCOMP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Reference Selection"] + #[inline(always)] + pub fn refsel(&self) -> REFSEL_R { + REFSEL_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 7 - Reference Buffer Offset Compensation Enable"] + #[inline(always)] + pub fn refcomp(&self) -> REFCOMP_R { + REFCOMP_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Reference Selection"] + #[inline(always)] + pub fn refsel(&mut self) -> REFSEL_W { + REFSEL_W { w: self } + } + #[doc = "Bit 7 - Reference Buffer Offset Compensation Enable"] + #[inline(always)] + pub fn refcomp(&mut self) -> REFCOMP_W { + REFCOMP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Reference Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [refctrl](index.html) module"] +pub struct REFCTRL_SPEC; +impl crate::RegisterSpec for REFCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [refctrl::R](R) reader structure"] +impl crate::Readable for REFCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [refctrl::W](W) writer structure"] +impl crate::Writable for REFCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets REFCTRL to value 0"] +impl crate::Resettable for REFCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/adc0/result.rs b/pac/atsamc21g/src/adc0/result.rs new file mode 100644 index 000000000000..b63b08cc72b9 --- /dev/null +++ b/pac/atsamc21g/src/adc0/result.rs @@ -0,0 +1,53 @@ +#[doc = "Register `RESULT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `RESULT` reader - Result Value"] +pub struct RESULT_R(crate::FieldReader); +impl RESULT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + RESULT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESULT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:15 - Result Value"] + #[inline(always)] + pub fn result(&self) -> RESULT_R { + RESULT_R::new(self.bits as u16) + } +} +#[doc = "Result\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [result](index.html) module"] +pub struct RESULT_SPEC; +impl crate::RegisterSpec for RESULT_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [result::R](R) reader structure"] +impl crate::Readable for RESULT_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets RESULT to value 0"] +impl crate::Resettable for RESULT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/adc0/sampctrl.rs b/pac/atsamc21g/src/adc0/sampctrl.rs new file mode 100644 index 000000000000..be4b77a80410 --- /dev/null +++ b/pac/atsamc21g/src/adc0/sampctrl.rs @@ -0,0 +1,150 @@ +#[doc = "Register `SAMPCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SAMPCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SAMPLEN` reader - Sampling Time Length"] +pub struct SAMPLEN_R(crate::FieldReader); +impl SAMPLEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SAMPLEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SAMPLEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SAMPLEN` writer - Sampling Time Length"] +pub struct SAMPLEN_W<'a> { + w: &'a mut W, +} +impl<'a> SAMPLEN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u8 & 0x3f); + self.w + } +} +#[doc = "Field `OFFCOMP` reader - Comparator Offset Compensation Enable"] +pub struct OFFCOMP_R(crate::FieldReader); +impl OFFCOMP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OFFCOMP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OFFCOMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OFFCOMP` writer - Comparator Offset Compensation Enable"] +pub struct OFFCOMP_W<'a> { + w: &'a mut W, +} +impl<'a> OFFCOMP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Sampling Time Length"] + #[inline(always)] + pub fn samplen(&self) -> SAMPLEN_R { + SAMPLEN_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 7 - Comparator Offset Compensation Enable"] + #[inline(always)] + pub fn offcomp(&self) -> OFFCOMP_R { + OFFCOMP_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:5 - Sampling Time Length"] + #[inline(always)] + pub fn samplen(&mut self) -> SAMPLEN_W { + SAMPLEN_W { w: self } + } + #[doc = "Bit 7 - Comparator Offset Compensation Enable"] + #[inline(always)] + pub fn offcomp(&mut self) -> OFFCOMP_W { + OFFCOMP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Sample Time Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sampctrl](index.html) module"] +pub struct SAMPCTRL_SPEC; +impl crate::RegisterSpec for SAMPCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [sampctrl::R](R) reader structure"] +impl crate::Readable for SAMPCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [sampctrl::W](W) writer structure"] +impl crate::Writable for SAMPCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SAMPCTRL to value 0"] +impl crate::Resettable for SAMPCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/adc0/seqctrl.rs b/pac/atsamc21g/src/adc0/seqctrl.rs new file mode 100644 index 000000000000..c8388c9a393f --- /dev/null +++ b/pac/atsamc21g/src/adc0/seqctrl.rs @@ -0,0 +1,103 @@ +#[doc = "Register `SEQCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SEQCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SEQEN` reader - Enable Positive Input in the Sequence"] +pub struct SEQEN_R(crate::FieldReader); +impl SEQEN_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + SEQEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEQEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEQEN` writer - Enable Positive Input in the Sequence"] +pub struct SEQEN_W<'a> { + w: &'a mut W, +} +impl<'a> SEQEN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Enable Positive Input in the Sequence"] + #[inline(always)] + pub fn seqen(&self) -> SEQEN_R { + SEQEN_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Enable Positive Input in the Sequence"] + #[inline(always)] + pub fn seqen(&mut self) -> SEQEN_W { + SEQEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Sequence Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [seqctrl](index.html) module"] +pub struct SEQCTRL_SPEC; +impl crate::RegisterSpec for SEQCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [seqctrl::R](R) reader structure"] +impl crate::Readable for SEQCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [seqctrl::W](W) writer structure"] +impl crate::Writable for SEQCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SEQCTRL to value 0"] +impl crate::Resettable for SEQCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/adc0/seqstatus.rs b/pac/atsamc21g/src/adc0/seqstatus.rs new file mode 100644 index 000000000000..42c820892e9a --- /dev/null +++ b/pac/atsamc21g/src/adc0/seqstatus.rs @@ -0,0 +1,73 @@ +#[doc = "Register `SEQSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SEQSTATE` reader - Sequence State"] +pub struct SEQSTATE_R(crate::FieldReader); +impl SEQSTATE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SEQSTATE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEQSTATE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEQBUSY` reader - Sequence Busy"] +pub struct SEQBUSY_R(crate::FieldReader); +impl SEQBUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SEQBUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEQBUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:4 - Sequence State"] + #[inline(always)] + pub fn seqstate(&self) -> SEQSTATE_R { + SEQSTATE_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bit 7 - Sequence Busy"] + #[inline(always)] + pub fn seqbusy(&self) -> SEQBUSY_R { + SEQBUSY_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +#[doc = "Sequence Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [seqstatus](index.html) module"] +pub struct SEQSTATUS_SPEC; +impl crate::RegisterSpec for SEQSTATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [seqstatus::R](R) reader structure"] +impl crate::Readable for SEQSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SEQSTATUS to value 0"] +impl crate::Resettable for SEQSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/adc0/swtrig.rs b/pac/atsamc21g/src/adc0/swtrig.rs new file mode 100644 index 000000000000..5e23ed7865ed --- /dev/null +++ b/pac/atsamc21g/src/adc0/swtrig.rs @@ -0,0 +1,160 @@ +#[doc = "Register `SWTRIG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SWTRIG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FLUSH` reader - ADC Flush"] +pub struct FLUSH_R(crate::FieldReader); +impl FLUSH_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FLUSH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FLUSH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLUSH` writer - ADC Flush"] +pub struct FLUSH_W<'a> { + w: &'a mut W, +} +impl<'a> FLUSH_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `START` reader - Start ADC Conversion"] +pub struct START_R(crate::FieldReader); +impl START_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + START_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for START_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `START` writer - Start ADC Conversion"] +pub struct START_W<'a> { + w: &'a mut W, +} +impl<'a> START_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - ADC Flush"] + #[inline(always)] + pub fn flush(&self) -> FLUSH_R { + FLUSH_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Start ADC Conversion"] + #[inline(always)] + pub fn start(&self) -> START_R { + START_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - ADC Flush"] + #[inline(always)] + pub fn flush(&mut self) -> FLUSH_W { + FLUSH_W { w: self } + } + #[doc = "Bit 1 - Start ADC Conversion"] + #[inline(always)] + pub fn start(&mut self) -> START_W { + START_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Software Trigger\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [swtrig](index.html) module"] +pub struct SWTRIG_SPEC; +impl crate::RegisterSpec for SWTRIG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [swtrig::R](R) reader structure"] +impl crate::Readable for SWTRIG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [swtrig::W](W) writer structure"] +impl crate::Writable for SWTRIG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SWTRIG to value 0"] +impl crate::Resettable for SWTRIG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/adc0/syncbusy.rs b/pac/atsamc21g/src/adc0/syncbusy.rs new file mode 100644 index 000000000000..9c92da8a7c74 --- /dev/null +++ b/pac/atsamc21g/src/adc0/syncbusy.rs @@ -0,0 +1,253 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - SWRST Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - ENABLE Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INPUTCTRL` reader - INPUTCTRL Synchronization Busy"] +pub struct INPUTCTRL_R(crate::FieldReader); +impl INPUTCTRL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INPUTCTRL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INPUTCTRL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLC` reader - CTRLC Synchronization Busy"] +pub struct CTRLC_R(crate::FieldReader); +impl CTRLC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AVGCTRL` reader - AVGCTRL Synchronization Busy"] +pub struct AVGCTRL_R(crate::FieldReader); +impl AVGCTRL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AVGCTRL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AVGCTRL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SAMPCTRL` reader - SAMPCTRL Synchronization Busy"] +pub struct SAMPCTRL_R(crate::FieldReader); +impl SAMPCTRL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SAMPCTRL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SAMPCTRL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINLT` reader - WINLT Synchronization Busy"] +pub struct WINLT_R(crate::FieldReader); +impl WINLT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINLT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINLT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINUT` reader - WINUT Synchronization Busy"] +pub struct WINUT_R(crate::FieldReader); +impl WINUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GAINCORR` reader - GAINCORR Synchronization Busy"] +pub struct GAINCORR_R(crate::FieldReader); +impl GAINCORR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GAINCORR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GAINCORR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OFFSETCORR` reader - OFFSETCTRL Synchronization Busy"] +pub struct OFFSETCORR_R(crate::FieldReader); +impl OFFSETCORR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OFFSETCORR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OFFSETCORR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG` reader - SWTRG Synchronization Busy"] +pub struct SWTRIG_R(crate::FieldReader); +impl SWTRIG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - SWRST Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ENABLE Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - INPUTCTRL Synchronization Busy"] + #[inline(always)] + pub fn inputctrl(&self) -> INPUTCTRL_R { + INPUTCTRL_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - CTRLC Synchronization Busy"] + #[inline(always)] + pub fn ctrlc(&self) -> CTRLC_R { + CTRLC_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - AVGCTRL Synchronization Busy"] + #[inline(always)] + pub fn avgctrl(&self) -> AVGCTRL_R { + AVGCTRL_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - SAMPCTRL Synchronization Busy"] + #[inline(always)] + pub fn sampctrl(&self) -> SAMPCTRL_R { + SAMPCTRL_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - WINLT Synchronization Busy"] + #[inline(always)] + pub fn winlt(&self) -> WINLT_R { + WINLT_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - WINUT Synchronization Busy"] + #[inline(always)] + pub fn winut(&self) -> WINUT_R { + WINUT_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - GAINCORR Synchronization Busy"] + #[inline(always)] + pub fn gaincorr(&self) -> GAINCORR_R { + GAINCORR_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - OFFSETCTRL Synchronization Busy"] + #[inline(always)] + pub fn offsetcorr(&self) -> OFFSETCORR_R { + OFFSETCORR_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - SWTRG Synchronization Busy"] + #[inline(always)] + pub fn swtrig(&self) -> SWTRIG_R { + SWTRIG_R::new(((self.bits >> 10) & 0x01) != 0) + } +} +#[doc = "Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/adc0/winlt.rs b/pac/atsamc21g/src/adc0/winlt.rs new file mode 100644 index 000000000000..2a3397684767 --- /dev/null +++ b/pac/atsamc21g/src/adc0/winlt.rs @@ -0,0 +1,103 @@ +#[doc = "Register `WINLT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WINLT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WINLT` reader - Window Lower Threshold"] +pub struct WINLT_R(crate::FieldReader); +impl WINLT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + WINLT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINLT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINLT` writer - Window Lower Threshold"] +pub struct WINLT_W<'a> { + w: &'a mut W, +} +impl<'a> WINLT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Window Lower Threshold"] + #[inline(always)] + pub fn winlt(&self) -> WINLT_R { + WINLT_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Window Lower Threshold"] + #[inline(always)] + pub fn winlt(&mut self) -> WINLT_W { + WINLT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Window Monitor Lower Threshold\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [winlt](index.html) module"] +pub struct WINLT_SPEC; +impl crate::RegisterSpec for WINLT_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [winlt::R](R) reader structure"] +impl crate::Readable for WINLT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [winlt::W](W) writer structure"] +impl crate::Writable for WINLT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WINLT to value 0"] +impl crate::Resettable for WINLT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/adc0/winut.rs b/pac/atsamc21g/src/adc0/winut.rs new file mode 100644 index 000000000000..0ea123174937 --- /dev/null +++ b/pac/atsamc21g/src/adc0/winut.rs @@ -0,0 +1,103 @@ +#[doc = "Register `WINUT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WINUT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WINUT` reader - Window Upper Threshold"] +pub struct WINUT_R(crate::FieldReader); +impl WINUT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + WINUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINUT` writer - Window Upper Threshold"] +pub struct WINUT_W<'a> { + w: &'a mut W, +} +impl<'a> WINUT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Window Upper Threshold"] + #[inline(always)] + pub fn winut(&self) -> WINUT_R { + WINUT_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Window Upper Threshold"] + #[inline(always)] + pub fn winut(&mut self) -> WINUT_W { + WINUT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Window Monitor Upper Threshold\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [winut](index.html) module"] +pub struct WINUT_SPEC; +impl crate::RegisterSpec for WINUT_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [winut::R](R) reader structure"] +impl crate::Readable for WINUT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [winut::W](W) writer structure"] +impl crate::Writable for WINUT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WINUT to value 0"] +impl crate::Resettable for WINUT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/can0.rs b/pac/atsamc21g/src/can0.rs new file mode 100644 index 000000000000..96ccd4c5970c --- /dev/null +++ b/pac/atsamc21g/src/can0.rs @@ -0,0 +1,291 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Core Release"] + pub crel: crate::Reg, + #[doc = "0x04 - Endian"] + pub endn: crate::Reg, + #[doc = "0x08 - Message RAM Configuration"] + pub mrcfg: crate::Reg, + #[doc = "0x0c - Fast Bit Timing and Prescaler"] + pub dbtp: crate::Reg, + #[doc = "0x10 - Test"] + pub test: crate::Reg, + #[doc = "0x14 - RAM Watchdog"] + pub rwd: crate::Reg, + #[doc = "0x18 - CC Control"] + pub cccr: crate::Reg, + #[doc = "0x1c - Nominal Bit Timing and Prescaler"] + pub nbtp: crate::Reg, + #[doc = "0x20 - Timestamp Counter Configuration"] + pub tscc: crate::Reg, + #[doc = "0x24 - Timestamp Counter Value"] + pub tscv: crate::Reg, + #[doc = "0x28 - Timeout Counter Configuration"] + pub tocc: crate::Reg, + #[doc = "0x2c - Timeout Counter Value"] + pub tocv: crate::Reg, + _reserved12: [u8; 0x10], + #[doc = "0x40 - Error Counter"] + pub ecr: crate::Reg, + #[doc = "0x44 - Protocol Status"] + pub psr: crate::Reg, + #[doc = "0x48 - Extended ID Filter Configuration"] + pub tdcr: crate::Reg, + _reserved15: [u8; 0x04], + #[doc = "0x50 - Interrupt"] + pub ir: crate::Reg, + #[doc = "0x54 - Interrupt Enable"] + pub ie: crate::Reg, + #[doc = "0x58 - Interrupt Line Select"] + pub ils: crate::Reg, + #[doc = "0x5c - Interrupt Line Enable"] + pub ile: crate::Reg, + _reserved19: [u8; 0x20], + #[doc = "0x80 - Global Filter Configuration"] + pub gfc: crate::Reg, + #[doc = "0x84 - Standard ID Filter Configuration"] + pub sidfc: crate::Reg, + #[doc = "0x88 - Extended ID Filter Configuration"] + pub xidfc: crate::Reg, + _reserved22: [u8; 0x04], + #[doc = "0x90 - Extended ID AND Mask"] + pub xidam: crate::Reg, + #[doc = "0x94 - High Priority Message Status"] + pub hpms: crate::Reg, + #[doc = "0x98 - New Data 1"] + pub ndat1: crate::Reg, + #[doc = "0x9c - New Data 2"] + pub ndat2: crate::Reg, + #[doc = "0xa0 - Rx FIFO 0 Configuration"] + pub rxf0c: crate::Reg, + #[doc = "0xa4 - Rx FIFO 0 Status"] + pub rxf0s: crate::Reg, + #[doc = "0xa8 - Rx FIFO 0 Acknowledge"] + pub rxf0a: crate::Reg, + #[doc = "0xac - Rx Buffer Configuration"] + pub rxbc: crate::Reg, + #[doc = "0xb0 - Rx FIFO 1 Configuration"] + pub rxf1c: crate::Reg, + #[doc = "0xb4 - Rx FIFO 1 Status"] + pub rxf1s: crate::Reg, + #[doc = "0xb8 - Rx FIFO 1 Acknowledge"] + pub rxf1a: crate::Reg, + #[doc = "0xbc - Rx Buffer / FIFO Element Size Configuration"] + pub rxesc: crate::Reg, + #[doc = "0xc0 - Tx Buffer Configuration"] + pub txbc: crate::Reg, + #[doc = "0xc4 - Tx FIFO / Queue Status"] + pub txfqs: crate::Reg, + #[doc = "0xc8 - Tx Buffer Element Size Configuration"] + pub txesc: crate::Reg, + #[doc = "0xcc - Tx Buffer Request Pending"] + pub txbrp: crate::Reg, + #[doc = "0xd0 - Tx Buffer Add Request"] + pub txbar: crate::Reg, + #[doc = "0xd4 - Tx Buffer Cancellation Request"] + pub txbcr: crate::Reg, + #[doc = "0xd8 - Tx Buffer Transmission Occurred"] + pub txbto: crate::Reg, + #[doc = "0xdc - Tx Buffer Cancellation Finished"] + pub txbcf: crate::Reg, + #[doc = "0xe0 - Tx Buffer Transmission Interrupt Enable"] + pub txbtie: crate::Reg, + #[doc = "0xe4 - Tx Buffer Cancellation Finished Interrupt Enable"] + pub txbcie: crate::Reg, + _reserved44: [u8; 0x08], + #[doc = "0xf0 - Tx Event FIFO Configuration"] + pub txefc: crate::Reg, + #[doc = "0xf4 - Tx Event FIFO Status"] + pub txefs: crate::Reg, + #[doc = "0xf8 - Tx Event FIFO Acknowledge"] + pub txefa: crate::Reg, +} +#[doc = "CREL register accessor: an alias for `Reg`"] +pub type CREL = crate::Reg; +#[doc = "Core Release"] +pub mod crel; +#[doc = "ENDN register accessor: an alias for `Reg`"] +pub type ENDN = crate::Reg; +#[doc = "Endian"] +pub mod endn; +#[doc = "MRCFG register accessor: an alias for `Reg`"] +pub type MRCFG = crate::Reg; +#[doc = "Message RAM Configuration"] +pub mod mrcfg; +#[doc = "DBTP register accessor: an alias for `Reg`"] +pub type DBTP = crate::Reg; +#[doc = "Fast Bit Timing and Prescaler"] +pub mod dbtp; +#[doc = "TEST register accessor: an alias for `Reg`"] +pub type TEST = crate::Reg; +#[doc = "Test"] +pub mod test; +#[doc = "RWD register accessor: an alias for `Reg`"] +pub type RWD = crate::Reg; +#[doc = "RAM Watchdog"] +pub mod rwd; +#[doc = "CCCR register accessor: an alias for `Reg`"] +pub type CCCR = crate::Reg; +#[doc = "CC Control"] +pub mod cccr; +#[doc = "NBTP register accessor: an alias for `Reg`"] +pub type NBTP = crate::Reg; +#[doc = "Nominal Bit Timing and Prescaler"] +pub mod nbtp; +#[doc = "TSCC register accessor: an alias for `Reg`"] +pub type TSCC = crate::Reg; +#[doc = "Timestamp Counter Configuration"] +pub mod tscc; +#[doc = "TSCV register accessor: an alias for `Reg`"] +pub type TSCV = crate::Reg; +#[doc = "Timestamp Counter Value"] +pub mod tscv; +#[doc = "TOCC register accessor: an alias for `Reg`"] +pub type TOCC = crate::Reg; +#[doc = "Timeout Counter Configuration"] +pub mod tocc; +#[doc = "TOCV register accessor: an alias for `Reg`"] +pub type TOCV = crate::Reg; +#[doc = "Timeout Counter Value"] +pub mod tocv; +#[doc = "ECR register accessor: an alias for `Reg`"] +pub type ECR = crate::Reg; +#[doc = "Error Counter"] +pub mod ecr; +#[doc = "PSR register accessor: an alias for `Reg`"] +pub type PSR = crate::Reg; +#[doc = "Protocol Status"] +pub mod psr; +#[doc = "TDCR register accessor: an alias for `Reg`"] +pub type TDCR = crate::Reg; +#[doc = "Extended ID Filter Configuration"] +pub mod tdcr; +#[doc = "IR register accessor: an alias for `Reg`"] +pub type IR = crate::Reg; +#[doc = "Interrupt"] +pub mod ir; +#[doc = "IE register accessor: an alias for `Reg`"] +pub type IE = crate::Reg; +#[doc = "Interrupt Enable"] +pub mod ie; +#[doc = "ILS register accessor: an alias for `Reg`"] +pub type ILS = crate::Reg; +#[doc = "Interrupt Line Select"] +pub mod ils; +#[doc = "ILE register accessor: an alias for `Reg`"] +pub type ILE = crate::Reg; +#[doc = "Interrupt Line Enable"] +pub mod ile; +#[doc = "GFC register accessor: an alias for `Reg`"] +pub type GFC = crate::Reg; +#[doc = "Global Filter Configuration"] +pub mod gfc; +#[doc = "SIDFC register accessor: an alias for `Reg`"] +pub type SIDFC = crate::Reg; +#[doc = "Standard ID Filter Configuration"] +pub mod sidfc; +#[doc = "XIDFC register accessor: an alias for `Reg`"] +pub type XIDFC = crate::Reg; +#[doc = "Extended ID Filter Configuration"] +pub mod xidfc; +#[doc = "XIDAM register accessor: an alias for `Reg`"] +pub type XIDAM = crate::Reg; +#[doc = "Extended ID AND Mask"] +pub mod xidam; +#[doc = "HPMS register accessor: an alias for `Reg`"] +pub type HPMS = crate::Reg; +#[doc = "High Priority Message Status"] +pub mod hpms; +#[doc = "NDAT1 register accessor: an alias for `Reg`"] +pub type NDAT1 = crate::Reg; +#[doc = "New Data 1"] +pub mod ndat1; +#[doc = "NDAT2 register accessor: an alias for `Reg`"] +pub type NDAT2 = crate::Reg; +#[doc = "New Data 2"] +pub mod ndat2; +#[doc = "RXF0C register accessor: an alias for `Reg`"] +pub type RXF0C = crate::Reg; +#[doc = "Rx FIFO 0 Configuration"] +pub mod rxf0c; +#[doc = "RXF0S register accessor: an alias for `Reg`"] +pub type RXF0S = crate::Reg; +#[doc = "Rx FIFO 0 Status"] +pub mod rxf0s; +#[doc = "RXF0A register accessor: an alias for `Reg`"] +pub type RXF0A = crate::Reg; +#[doc = "Rx FIFO 0 Acknowledge"] +pub mod rxf0a; +#[doc = "RXBC register accessor: an alias for `Reg`"] +pub type RXBC = crate::Reg; +#[doc = "Rx Buffer Configuration"] +pub mod rxbc; +#[doc = "RXF1C register accessor: an alias for `Reg`"] +pub type RXF1C = crate::Reg; +#[doc = "Rx FIFO 1 Configuration"] +pub mod rxf1c; +#[doc = "RXF1S register accessor: an alias for `Reg`"] +pub type RXF1S = crate::Reg; +#[doc = "Rx FIFO 1 Status"] +pub mod rxf1s; +#[doc = "RXF1A register accessor: an alias for `Reg`"] +pub type RXF1A = crate::Reg; +#[doc = "Rx FIFO 1 Acknowledge"] +pub mod rxf1a; +#[doc = "RXESC register accessor: an alias for `Reg`"] +pub type RXESC = crate::Reg; +#[doc = "Rx Buffer / FIFO Element Size Configuration"] +pub mod rxesc; +#[doc = "TXBC register accessor: an alias for `Reg`"] +pub type TXBC = crate::Reg; +#[doc = "Tx Buffer Configuration"] +pub mod txbc; +#[doc = "TXFQS register accessor: an alias for `Reg`"] +pub type TXFQS = crate::Reg; +#[doc = "Tx FIFO / Queue Status"] +pub mod txfqs; +#[doc = "TXESC register accessor: an alias for `Reg`"] +pub type TXESC = crate::Reg; +#[doc = "Tx Buffer Element Size Configuration"] +pub mod txesc; +#[doc = "TXBRP register accessor: an alias for `Reg`"] +pub type TXBRP = crate::Reg; +#[doc = "Tx Buffer Request Pending"] +pub mod txbrp; +#[doc = "TXBAR register accessor: an alias for `Reg`"] +pub type TXBAR = crate::Reg; +#[doc = "Tx Buffer Add Request"] +pub mod txbar; +#[doc = "TXBCR register accessor: an alias for `Reg`"] +pub type TXBCR = crate::Reg; +#[doc = "Tx Buffer Cancellation Request"] +pub mod txbcr; +#[doc = "TXBTO register accessor: an alias for `Reg`"] +pub type TXBTO = crate::Reg; +#[doc = "Tx Buffer Transmission Occurred"] +pub mod txbto; +#[doc = "TXBCF register accessor: an alias for `Reg`"] +pub type TXBCF = crate::Reg; +#[doc = "Tx Buffer Cancellation Finished"] +pub mod txbcf; +#[doc = "TXBTIE register accessor: an alias for `Reg`"] +pub type TXBTIE = crate::Reg; +#[doc = "Tx Buffer Transmission Interrupt Enable"] +pub mod txbtie; +#[doc = "TXBCIE register accessor: an alias for `Reg`"] +pub type TXBCIE = crate::Reg; +#[doc = "Tx Buffer Cancellation Finished Interrupt Enable"] +pub mod txbcie; +#[doc = "TXEFC register accessor: an alias for `Reg`"] +pub type TXEFC = crate::Reg; +#[doc = "Tx Event FIFO Configuration"] +pub mod txefc; +#[doc = "TXEFS register accessor: an alias for `Reg`"] +pub type TXEFS = crate::Reg; +#[doc = "Tx Event FIFO Status"] +pub mod txefs; +#[doc = "TXEFA register accessor: an alias for `Reg`"] +pub type TXEFA = crate::Reg; +#[doc = "Tx Event FIFO Acknowledge"] +pub mod txefa; diff --git a/pac/atsamc21g/src/can0/cccr.rs b/pac/atsamc21g/src/can0/cccr.rs new file mode 100644 index 000000000000..c2ff17d123cf --- /dev/null +++ b/pac/atsamc21g/src/can0/cccr.rs @@ -0,0 +1,724 @@ +#[doc = "Register `CCCR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CCCR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INIT` reader - Initialization"] +pub struct INIT_R(crate::FieldReader); +impl INIT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INIT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INIT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INIT` writer - Initialization"] +pub struct INIT_W<'a> { + w: &'a mut W, +} +impl<'a> INIT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `CCE` reader - Configuration Change Enable"] +pub struct CCE_R(crate::FieldReader); +impl CCE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCE` writer - Configuration Change Enable"] +pub struct CCE_W<'a> { + w: &'a mut W, +} +impl<'a> CCE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ASM` reader - ASM Restricted Operation Mode"] +pub struct ASM_R(crate::FieldReader); +impl ASM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ASM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ASM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ASM` writer - ASM Restricted Operation Mode"] +pub struct ASM_W<'a> { + w: &'a mut W, +} +impl<'a> ASM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CSA` reader - Clock Stop Acknowledge"] +pub struct CSA_R(crate::FieldReader); +impl CSA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CSA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CSA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CSA` writer - Clock Stop Acknowledge"] +pub struct CSA_W<'a> { + w: &'a mut W, +} +impl<'a> CSA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CSR` reader - Clock Stop Request"] +pub struct CSR_R(crate::FieldReader); +impl CSR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CSR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CSR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CSR` writer - Clock Stop Request"] +pub struct CSR_W<'a> { + w: &'a mut W, +} +impl<'a> CSR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MON` reader - Bus Monitoring Mode"] +pub struct MON_R(crate::FieldReader); +impl MON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MON` writer - Bus Monitoring Mode"] +pub struct MON_W<'a> { + w: &'a mut W, +} +impl<'a> MON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `DAR` reader - Disable Automatic Retransmission"] +pub struct DAR_R(crate::FieldReader); +impl DAR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DAR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DAR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DAR` writer - Disable Automatic Retransmission"] +pub struct DAR_W<'a> { + w: &'a mut W, +} +impl<'a> DAR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `TEST` reader - Test Mode Enable"] +pub struct TEST_R(crate::FieldReader); +impl TEST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TEST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TEST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TEST` writer - Test Mode Enable"] +pub struct TEST_W<'a> { + w: &'a mut W, +} +impl<'a> TEST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `FDOE` reader - FD Operation Enable"] +pub struct FDOE_R(crate::FieldReader); +impl FDOE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FDOE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FDOE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FDOE` writer - FD Operation Enable"] +pub struct FDOE_W<'a> { + w: &'a mut W, +} +impl<'a> FDOE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `BRSE` reader - Bit Rate Switch Enable"] +pub struct BRSE_R(crate::FieldReader); +impl BRSE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BRSE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BRSE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BRSE` writer - Bit Rate Switch Enable"] +pub struct BRSE_W<'a> { + w: &'a mut W, +} +impl<'a> BRSE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `PXHD` reader - Protocol Exception Handling Disable"] +pub struct PXHD_R(crate::FieldReader); +impl PXHD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PXHD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PXHD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PXHD` writer - Protocol Exception Handling Disable"] +pub struct PXHD_W<'a> { + w: &'a mut W, +} +impl<'a> PXHD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `EFBI` reader - Edge Filtering during Bus Integration"] +pub struct EFBI_R(crate::FieldReader); +impl EFBI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EFBI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EFBI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EFBI` writer - Edge Filtering during Bus Integration"] +pub struct EFBI_W<'a> { + w: &'a mut W, +} +impl<'a> EFBI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `TXP` reader - Transmit Pause"] +pub struct TXP_R(crate::FieldReader); +impl TXP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXP` writer - Transmit Pause"] +pub struct TXP_W<'a> { + w: &'a mut W, +} +impl<'a> TXP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `NISO` reader - Non ISO Operation"] +pub struct NISO_R(crate::FieldReader); +impl NISO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NISO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NISO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NISO` writer - Non ISO Operation"] +pub struct NISO_W<'a> { + w: &'a mut W, +} +impl<'a> NISO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Initialization"] + #[inline(always)] + pub fn init(&self) -> INIT_R { + INIT_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Configuration Change Enable"] + #[inline(always)] + pub fn cce(&self) -> CCE_R { + CCE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - ASM Restricted Operation Mode"] + #[inline(always)] + pub fn asm(&self) -> ASM_R { + ASM_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Clock Stop Acknowledge"] + #[inline(always)] + pub fn csa(&self) -> CSA_R { + CSA_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Clock Stop Request"] + #[inline(always)] + pub fn csr(&self) -> CSR_R { + CSR_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Bus Monitoring Mode"] + #[inline(always)] + pub fn mon(&self) -> MON_R { + MON_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Disable Automatic Retransmission"] + #[inline(always)] + pub fn dar(&self) -> DAR_R { + DAR_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Test Mode Enable"] + #[inline(always)] + pub fn test(&self) -> TEST_R { + TEST_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - FD Operation Enable"] + #[inline(always)] + pub fn fdoe(&self) -> FDOE_R { + FDOE_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Bit Rate Switch Enable"] + #[inline(always)] + pub fn brse(&self) -> BRSE_R { + BRSE_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 12 - Protocol Exception Handling Disable"] + #[inline(always)] + pub fn pxhd(&self) -> PXHD_R { + PXHD_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Edge Filtering during Bus Integration"] + #[inline(always)] + pub fn efbi(&self) -> EFBI_R { + EFBI_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Transmit Pause"] + #[inline(always)] + pub fn txp(&self) -> TXP_R { + TXP_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Non ISO Operation"] + #[inline(always)] + pub fn niso(&self) -> NISO_R { + NISO_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Initialization"] + #[inline(always)] + pub fn init(&mut self) -> INIT_W { + INIT_W { w: self } + } + #[doc = "Bit 1 - Configuration Change Enable"] + #[inline(always)] + pub fn cce(&mut self) -> CCE_W { + CCE_W { w: self } + } + #[doc = "Bit 2 - ASM Restricted Operation Mode"] + #[inline(always)] + pub fn asm(&mut self) -> ASM_W { + ASM_W { w: self } + } + #[doc = "Bit 3 - Clock Stop Acknowledge"] + #[inline(always)] + pub fn csa(&mut self) -> CSA_W { + CSA_W { w: self } + } + #[doc = "Bit 4 - Clock Stop Request"] + #[inline(always)] + pub fn csr(&mut self) -> CSR_W { + CSR_W { w: self } + } + #[doc = "Bit 5 - Bus Monitoring Mode"] + #[inline(always)] + pub fn mon(&mut self) -> MON_W { + MON_W { w: self } + } + #[doc = "Bit 6 - Disable Automatic Retransmission"] + #[inline(always)] + pub fn dar(&mut self) -> DAR_W { + DAR_W { w: self } + } + #[doc = "Bit 7 - Test Mode Enable"] + #[inline(always)] + pub fn test(&mut self) -> TEST_W { + TEST_W { w: self } + } + #[doc = "Bit 8 - FD Operation Enable"] + #[inline(always)] + pub fn fdoe(&mut self) -> FDOE_W { + FDOE_W { w: self } + } + #[doc = "Bit 9 - Bit Rate Switch Enable"] + #[inline(always)] + pub fn brse(&mut self) -> BRSE_W { + BRSE_W { w: self } + } + #[doc = "Bit 12 - Protocol Exception Handling Disable"] + #[inline(always)] + pub fn pxhd(&mut self) -> PXHD_W { + PXHD_W { w: self } + } + #[doc = "Bit 13 - Edge Filtering during Bus Integration"] + #[inline(always)] + pub fn efbi(&mut self) -> EFBI_W { + EFBI_W { w: self } + } + #[doc = "Bit 14 - Transmit Pause"] + #[inline(always)] + pub fn txp(&mut self) -> TXP_W { + TXP_W { w: self } + } + #[doc = "Bit 15 - Non ISO Operation"] + #[inline(always)] + pub fn niso(&mut self) -> NISO_W { + NISO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CC Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cccr](index.html) module"] +pub struct CCCR_SPEC; +impl crate::RegisterSpec for CCCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cccr::R](R) reader structure"] +impl crate::Readable for CCCR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cccr::W](W) writer structure"] +impl crate::Writable for CCCR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CCCR to value 0x01"] +impl crate::Resettable for CCCR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pac/atsamc21g/src/can0/crel.rs b/pac/atsamc21g/src/can0/crel.rs new file mode 100644 index 000000000000..4e9dcdbf5f03 --- /dev/null +++ b/pac/atsamc21g/src/can0/crel.rs @@ -0,0 +1,93 @@ +#[doc = "Register `CREL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SUBSTEP` reader - Sub-step of Core Release"] +pub struct SUBSTEP_R(crate::FieldReader); +impl SUBSTEP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SUBSTEP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SUBSTEP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STEP` reader - Step of Core Release"] +pub struct STEP_R(crate::FieldReader); +impl STEP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + STEP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STEP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REL` reader - Core Release"] +pub struct REL_R(crate::FieldReader); +impl REL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 20:23 - Sub-step of Core Release"] + #[inline(always)] + pub fn substep(&self) -> SUBSTEP_R { + SUBSTEP_R::new(((self.bits >> 20) & 0x0f) as u8) + } + #[doc = "Bits 24:27 - Step of Core Release"] + #[inline(always)] + pub fn step(&self) -> STEP_R { + STEP_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bits 28:31 - Core Release"] + #[inline(always)] + pub fn rel(&self) -> REL_R { + REL_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +#[doc = "Core Release\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [crel](index.html) module"] +pub struct CREL_SPEC; +impl crate::RegisterSpec for CREL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [crel::R](R) reader structure"] +impl crate::Readable for CREL_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CREL to value 0x3210_0000"] +impl crate::Resettable for CREL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x3210_0000 + } +} diff --git a/pac/atsamc21g/src/can0/dbtp.rs b/pac/atsamc21g/src/can0/dbtp.rs new file mode 100644 index 000000000000..5c1d2bc7ccdd --- /dev/null +++ b/pac/atsamc21g/src/can0/dbtp.rs @@ -0,0 +1,261 @@ +#[doc = "Register `DBTP` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBTP` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DSJW` reader - Data (Re)Synchronization Jump Width"] +pub struct DSJW_R(crate::FieldReader); +impl DSJW_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DSJW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DSJW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DSJW` writer - Data (Re)Synchronization Jump Width"] +pub struct DSJW_W<'a> { + w: &'a mut W, +} +impl<'a> DSJW_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Field `DTSEG2` reader - Data time segment after sample point"] +pub struct DTSEG2_R(crate::FieldReader); +impl DTSEG2_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DTSEG2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DTSEG2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DTSEG2` writer - Data time segment after sample point"] +pub struct DTSEG2_W<'a> { + w: &'a mut W, +} +impl<'a> DTSEG2_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 4)) | ((value as u32 & 0x0f) << 4); + self.w + } +} +#[doc = "Field `DTSEG1` reader - Data time segment before sample point"] +pub struct DTSEG1_R(crate::FieldReader); +impl DTSEG1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DTSEG1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DTSEG1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DTSEG1` writer - Data time segment before sample point"] +pub struct DTSEG1_W<'a> { + w: &'a mut W, +} +impl<'a> DTSEG1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 8)) | ((value as u32 & 0x1f) << 8); + self.w + } +} +#[doc = "Field `DBRP` reader - Data Baud Rate Prescaler"] +pub struct DBRP_R(crate::FieldReader); +impl DBRP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DBRP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBRP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBRP` writer - Data Baud Rate Prescaler"] +pub struct DBRP_W<'a> { + w: &'a mut W, +} +impl<'a> DBRP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 16)) | ((value as u32 & 0x1f) << 16); + self.w + } +} +#[doc = "Field `TDC` reader - Tranceiver Delay Compensation"] +pub struct TDC_R(crate::FieldReader); +impl TDC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TDC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TDC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TDC` writer - Tranceiver Delay Compensation"] +pub struct TDC_W<'a> { + w: &'a mut W, +} +impl<'a> TDC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Data (Re)Synchronization Jump Width"] + #[inline(always)] + pub fn dsjw(&self) -> DSJW_R { + DSJW_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Data time segment after sample point"] + #[inline(always)] + pub fn dtseg2(&self) -> DTSEG2_R { + DTSEG2_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 8:12 - Data time segment before sample point"] + #[inline(always)] + pub fn dtseg1(&self) -> DTSEG1_R { + DTSEG1_R::new(((self.bits >> 8) & 0x1f) as u8) + } + #[doc = "Bits 16:20 - Data Baud Rate Prescaler"] + #[inline(always)] + pub fn dbrp(&self) -> DBRP_R { + DBRP_R::new(((self.bits >> 16) & 0x1f) as u8) + } + #[doc = "Bit 23 - Tranceiver Delay Compensation"] + #[inline(always)] + pub fn tdc(&self) -> TDC_R { + TDC_R::new(((self.bits >> 23) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Data (Re)Synchronization Jump Width"] + #[inline(always)] + pub fn dsjw(&mut self) -> DSJW_W { + DSJW_W { w: self } + } + #[doc = "Bits 4:7 - Data time segment after sample point"] + #[inline(always)] + pub fn dtseg2(&mut self) -> DTSEG2_W { + DTSEG2_W { w: self } + } + #[doc = "Bits 8:12 - Data time segment before sample point"] + #[inline(always)] + pub fn dtseg1(&mut self) -> DTSEG1_W { + DTSEG1_W { w: self } + } + #[doc = "Bits 16:20 - Data Baud Rate Prescaler"] + #[inline(always)] + pub fn dbrp(&mut self) -> DBRP_W { + DBRP_W { w: self } + } + #[doc = "Bit 23 - Tranceiver Delay Compensation"] + #[inline(always)] + pub fn tdc(&mut self) -> TDC_W { + TDC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Fast Bit Timing and Prescaler\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbtp](index.html) module"] +pub struct DBTP_SPEC; +impl crate::RegisterSpec for DBTP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dbtp::R](R) reader structure"] +impl crate::Readable for DBTP_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbtp::W](W) writer structure"] +impl crate::Writable for DBTP_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBTP to value 0x0a33"] +impl crate::Resettable for DBTP_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0a33 + } +} diff --git a/pac/atsamc21g/src/can0/ecr.rs b/pac/atsamc21g/src/can0/ecr.rs new file mode 100644 index 000000000000..044085d7706d --- /dev/null +++ b/pac/atsamc21g/src/can0/ecr.rs @@ -0,0 +1,113 @@ +#[doc = "Register `ECR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `TEC` reader - Transmit Error Counter"] +pub struct TEC_R(crate::FieldReader); +impl TEC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TEC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TEC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REC` reader - Receive Error Counter"] +pub struct REC_R(crate::FieldReader); +impl REC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RP` reader - Receive Error Passive"] +pub struct RP_R(crate::FieldReader); +impl RP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CEL` reader - CAN Error Logging"] +pub struct CEL_R(crate::FieldReader); +impl CEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:7 - Transmit Error Counter"] + #[inline(always)] + pub fn tec(&self) -> TEC_R { + TEC_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:14 - Receive Error Counter"] + #[inline(always)] + pub fn rec(&self) -> REC_R { + REC_R::new(((self.bits >> 8) & 0x7f) as u8) + } + #[doc = "Bit 15 - Receive Error Passive"] + #[inline(always)] + pub fn rp(&self) -> RP_R { + RP_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:23 - CAN Error Logging"] + #[inline(always)] + pub fn cel(&self) -> CEL_R { + CEL_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +#[doc = "Error Counter\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ecr](index.html) module"] +pub struct ECR_SPEC; +impl crate::RegisterSpec for ECR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ecr::R](R) reader structure"] +impl crate::Readable for ECR_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets ECR to value 0"] +impl crate::Resettable for ECR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/can0/endn.rs b/pac/atsamc21g/src/can0/endn.rs new file mode 100644 index 000000000000..9628fa2a3f48 --- /dev/null +++ b/pac/atsamc21g/src/can0/endn.rs @@ -0,0 +1,53 @@ +#[doc = "Register `ENDN` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `ETV` reader - Endianness Test Value"] +pub struct ETV_R(crate::FieldReader); +impl ETV_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + ETV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ETV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - Endianness Test Value"] + #[inline(always)] + pub fn etv(&self) -> ETV_R { + ETV_R::new(self.bits as u32) + } +} +#[doc = "Endian\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [endn](index.html) module"] +pub struct ENDN_SPEC; +impl crate::RegisterSpec for ENDN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [endn::R](R) reader structure"] +impl crate::Readable for ENDN_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets ENDN to value 0x8765_4321"] +impl crate::Resettable for ENDN_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x8765_4321 + } +} diff --git a/pac/atsamc21g/src/can0/gfc.rs b/pac/atsamc21g/src/can0/gfc.rs new file mode 100644 index 000000000000..a9e7a8cc9f62 --- /dev/null +++ b/pac/atsamc21g/src/can0/gfc.rs @@ -0,0 +1,358 @@ +#[doc = "Register `GFC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GFC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RRFE` reader - Reject Remote Frames Extended"] +pub struct RRFE_R(crate::FieldReader); +impl RRFE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RRFE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RRFE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RRFE` writer - Reject Remote Frames Extended"] +pub struct RRFE_W<'a> { + w: &'a mut W, +} +impl<'a> RRFE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `RRFS` reader - Reject Remote Frames Standard"] +pub struct RRFS_R(crate::FieldReader); +impl RRFS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RRFS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RRFS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RRFS` writer - Reject Remote Frames Standard"] +pub struct RRFS_W<'a> { + w: &'a mut W, +} +impl<'a> RRFS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Accept Non-matching Frames Extended\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum ANFE_A { + #[doc = "0: Accept in Rx FIFO 0"] + RXF0 = 0, + #[doc = "1: Accept in Rx FIFO 1"] + RXF1 = 1, + #[doc = "2: Reject"] + REJECT = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: ANFE_A) -> Self { + variant as _ + } +} +#[doc = "Field `ANFE` reader - Accept Non-matching Frames Extended"] +pub struct ANFE_R(crate::FieldReader); +impl ANFE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ANFE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(ANFE_A::RXF0), + 1 => Some(ANFE_A::RXF1), + 2 => Some(ANFE_A::REJECT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `RXF0`"] + #[inline(always)] + pub fn is_rxf0(&self) -> bool { + **self == ANFE_A::RXF0 + } + #[doc = "Checks if the value of the field is `RXF1`"] + #[inline(always)] + pub fn is_rxf1(&self) -> bool { + **self == ANFE_A::RXF1 + } + #[doc = "Checks if the value of the field is `REJECT`"] + #[inline(always)] + pub fn is_reject(&self) -> bool { + **self == ANFE_A::REJECT + } +} +impl core::ops::Deref for ANFE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ANFE` writer - Accept Non-matching Frames Extended"] +pub struct ANFE_W<'a> { + w: &'a mut W, +} +impl<'a> ANFE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: ANFE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Accept in Rx FIFO 0"] + #[inline(always)] + pub fn rxf0(self) -> &'a mut W { + self.variant(ANFE_A::RXF0) + } + #[doc = "Accept in Rx FIFO 1"] + #[inline(always)] + pub fn rxf1(self) -> &'a mut W { + self.variant(ANFE_A::RXF1) + } + #[doc = "Reject"] + #[inline(always)] + pub fn reject(self) -> &'a mut W { + self.variant(ANFE_A::REJECT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u32 & 0x03) << 2); + self.w + } +} +#[doc = "Accept Non-matching Frames Standard\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum ANFS_A { + #[doc = "0: Accept in Rx FIFO 0"] + RXF0 = 0, + #[doc = "1: Accept in Rx FIFO 1"] + RXF1 = 1, + #[doc = "2: Reject"] + REJECT = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: ANFS_A) -> Self { + variant as _ + } +} +#[doc = "Field `ANFS` reader - Accept Non-matching Frames Standard"] +pub struct ANFS_R(crate::FieldReader); +impl ANFS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ANFS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(ANFS_A::RXF0), + 1 => Some(ANFS_A::RXF1), + 2 => Some(ANFS_A::REJECT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `RXF0`"] + #[inline(always)] + pub fn is_rxf0(&self) -> bool { + **self == ANFS_A::RXF0 + } + #[doc = "Checks if the value of the field is `RXF1`"] + #[inline(always)] + pub fn is_rxf1(&self) -> bool { + **self == ANFS_A::RXF1 + } + #[doc = "Checks if the value of the field is `REJECT`"] + #[inline(always)] + pub fn is_reject(&self) -> bool { + **self == ANFS_A::REJECT + } +} +impl core::ops::Deref for ANFS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ANFS` writer - Accept Non-matching Frames Standard"] +pub struct ANFS_W<'a> { + w: &'a mut W, +} +impl<'a> ANFS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: ANFS_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Accept in Rx FIFO 0"] + #[inline(always)] + pub fn rxf0(self) -> &'a mut W { + self.variant(ANFS_A::RXF0) + } + #[doc = "Accept in Rx FIFO 1"] + #[inline(always)] + pub fn rxf1(self) -> &'a mut W { + self.variant(ANFS_A::RXF1) + } + #[doc = "Reject"] + #[inline(always)] + pub fn reject(self) -> &'a mut W { + self.variant(ANFS_A::REJECT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u32 & 0x03) << 4); + self.w + } +} +impl R { + #[doc = "Bit 0 - Reject Remote Frames Extended"] + #[inline(always)] + pub fn rrfe(&self) -> RRFE_R { + RRFE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Reject Remote Frames Standard"] + #[inline(always)] + pub fn rrfs(&self) -> RRFS_R { + RRFS_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:3 - Accept Non-matching Frames Extended"] + #[inline(always)] + pub fn anfe(&self) -> ANFE_R { + ANFE_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bits 4:5 - Accept Non-matching Frames Standard"] + #[inline(always)] + pub fn anfs(&self) -> ANFS_R { + ANFS_R::new(((self.bits >> 4) & 0x03) as u8) + } +} +impl W { + #[doc = "Bit 0 - Reject Remote Frames Extended"] + #[inline(always)] + pub fn rrfe(&mut self) -> RRFE_W { + RRFE_W { w: self } + } + #[doc = "Bit 1 - Reject Remote Frames Standard"] + #[inline(always)] + pub fn rrfs(&mut self) -> RRFS_W { + RRFS_W { w: self } + } + #[doc = "Bits 2:3 - Accept Non-matching Frames Extended"] + #[inline(always)] + pub fn anfe(&mut self) -> ANFE_W { + ANFE_W { w: self } + } + #[doc = "Bits 4:5 - Accept Non-matching Frames Standard"] + #[inline(always)] + pub fn anfs(&mut self) -> ANFS_W { + ANFS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Global Filter Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gfc](index.html) module"] +pub struct GFC_SPEC; +impl crate::RegisterSpec for GFC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gfc::R](R) reader structure"] +impl crate::Readable for GFC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gfc::W](W) writer structure"] +impl crate::Writable for GFC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets GFC to value 0"] +impl crate::Resettable for GFC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/can0/hpms.rs b/pac/atsamc21g/src/can0/hpms.rs new file mode 100644 index 000000000000..ff26a312fb47 --- /dev/null +++ b/pac/atsamc21g/src/can0/hpms.rs @@ -0,0 +1,163 @@ +#[doc = "Register `HPMS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `BIDX` reader - Buffer Index"] +pub struct BIDX_R(crate::FieldReader); +impl BIDX_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BIDX_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BIDX_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Message Storage Indicator\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MSI_A { + #[doc = "0: No FIFO selected"] + NONE = 0, + #[doc = "1: FIFO message lost"] + LOST = 1, + #[doc = "2: Message stored in FIFO 0"] + FIFO0 = 2, + #[doc = "3: Message stored in FIFO 1"] + FIFO1 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MSI_A) -> Self { + variant as _ + } +} +#[doc = "Field `MSI` reader - Message Storage Indicator"] +pub struct MSI_R(crate::FieldReader); +impl MSI_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MSI_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> MSI_A { + match self.bits { + 0 => MSI_A::NONE, + 1 => MSI_A::LOST, + 2 => MSI_A::FIFO0, + 3 => MSI_A::FIFO1, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == MSI_A::NONE + } + #[doc = "Checks if the value of the field is `LOST`"] + #[inline(always)] + pub fn is_lost(&self) -> bool { + **self == MSI_A::LOST + } + #[doc = "Checks if the value of the field is `FIFO0`"] + #[inline(always)] + pub fn is_fifo0(&self) -> bool { + **self == MSI_A::FIFO0 + } + #[doc = "Checks if the value of the field is `FIFO1`"] + #[inline(always)] + pub fn is_fifo1(&self) -> bool { + **self == MSI_A::FIFO1 + } +} +impl core::ops::Deref for MSI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FIDX` reader - Filter Index"] +pub struct FIDX_R(crate::FieldReader); +impl FIDX_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FIDX_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FIDX_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLST` reader - Filter List"] +pub struct FLST_R(crate::FieldReader); +impl FLST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FLST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FLST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:5 - Buffer Index"] + #[inline(always)] + pub fn bidx(&self) -> BIDX_R { + BIDX_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:7 - Message Storage Indicator"] + #[inline(always)] + pub fn msi(&self) -> MSI_R { + MSI_R::new(((self.bits >> 6) & 0x03) as u8) + } + #[doc = "Bits 8:14 - Filter Index"] + #[inline(always)] + pub fn fidx(&self) -> FIDX_R { + FIDX_R::new(((self.bits >> 8) & 0x7f) as u8) + } + #[doc = "Bit 15 - Filter List"] + #[inline(always)] + pub fn flst(&self) -> FLST_R { + FLST_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +#[doc = "High Priority Message Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hpms](index.html) module"] +pub struct HPMS_SPEC; +impl crate::RegisterSpec for HPMS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [hpms::R](R) reader structure"] +impl crate::Readable for HPMS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets HPMS to value 0"] +impl crate::Resettable for HPMS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/can0/ie.rs b/pac/atsamc21g/src/can0/ie.rs new file mode 100644 index 000000000000..c773ba115329 --- /dev/null +++ b/pac/atsamc21g/src/can0/ie.rs @@ -0,0 +1,1476 @@ +#[doc = "Register `IE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `IE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RF0NE` reader - Rx FIFO 0 New Message Interrupt Enable"] +pub struct RF0NE_R(crate::FieldReader); +impl RF0NE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF0NE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF0NE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF0NE` writer - Rx FIFO 0 New Message Interrupt Enable"] +pub struct RF0NE_W<'a> { + w: &'a mut W, +} +impl<'a> RF0NE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `RF0WE` reader - Rx FIFO 0 Watermark Reached Interrupt Enable"] +pub struct RF0WE_R(crate::FieldReader); +impl RF0WE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF0WE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF0WE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF0WE` writer - Rx FIFO 0 Watermark Reached Interrupt Enable"] +pub struct RF0WE_W<'a> { + w: &'a mut W, +} +impl<'a> RF0WE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RF0FE` reader - Rx FIFO 0 Full Interrupt Enable"] +pub struct RF0FE_R(crate::FieldReader); +impl RF0FE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF0FE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF0FE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF0FE` writer - Rx FIFO 0 Full Interrupt Enable"] +pub struct RF0FE_W<'a> { + w: &'a mut W, +} +impl<'a> RF0FE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RF0LE` reader - Rx FIFO 0 Message Lost Interrupt Enable"] +pub struct RF0LE_R(crate::FieldReader); +impl RF0LE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF0LE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF0LE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF0LE` writer - Rx FIFO 0 Message Lost Interrupt Enable"] +pub struct RF0LE_W<'a> { + w: &'a mut W, +} +impl<'a> RF0LE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `RF1NE` reader - Rx FIFO 1 New Message Interrupt Enable"] +pub struct RF1NE_R(crate::FieldReader); +impl RF1NE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF1NE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF1NE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF1NE` writer - Rx FIFO 1 New Message Interrupt Enable"] +pub struct RF1NE_W<'a> { + w: &'a mut W, +} +impl<'a> RF1NE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RF1WE` reader - Rx FIFO 1 Watermark Reached Interrupt Enable"] +pub struct RF1WE_R(crate::FieldReader); +impl RF1WE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF1WE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF1WE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF1WE` writer - Rx FIFO 1 Watermark Reached Interrupt Enable"] +pub struct RF1WE_W<'a> { + w: &'a mut W, +} +impl<'a> RF1WE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `RF1FE` reader - Rx FIFO 1 FIFO Full Interrupt Enable"] +pub struct RF1FE_R(crate::FieldReader); +impl RF1FE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF1FE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF1FE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF1FE` writer - Rx FIFO 1 FIFO Full Interrupt Enable"] +pub struct RF1FE_W<'a> { + w: &'a mut W, +} +impl<'a> RF1FE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `RF1LE` reader - Rx FIFO 1 Message Lost Interrupt Enable"] +pub struct RF1LE_R(crate::FieldReader); +impl RF1LE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF1LE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF1LE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF1LE` writer - Rx FIFO 1 Message Lost Interrupt Enable"] +pub struct RF1LE_W<'a> { + w: &'a mut W, +} +impl<'a> RF1LE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `HPME` reader - High Priority Message Interrupt Enable"] +pub struct HPME_R(crate::FieldReader); +impl HPME_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HPME_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HPME_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HPME` writer - High Priority Message Interrupt Enable"] +pub struct HPME_W<'a> { + w: &'a mut W, +} +impl<'a> HPME_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `TCE` reader - Timestamp Completed Interrupt Enable"] +pub struct TCE_R(crate::FieldReader); +impl TCE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCE` writer - Timestamp Completed Interrupt Enable"] +pub struct TCE_W<'a> { + w: &'a mut W, +} +impl<'a> TCE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `TCFE` reader - Transmission Cancellation Finished Interrupt Enable"] +pub struct TCFE_R(crate::FieldReader); +impl TCFE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCFE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCFE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCFE` writer - Transmission Cancellation Finished Interrupt Enable"] +pub struct TCFE_W<'a> { + w: &'a mut W, +} +impl<'a> TCFE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `TFEE` reader - Tx FIFO Empty Interrupt Enable"] +pub struct TFEE_R(crate::FieldReader); +impl TFEE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TFEE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TFEE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TFEE` writer - Tx FIFO Empty Interrupt Enable"] +pub struct TFEE_W<'a> { + w: &'a mut W, +} +impl<'a> TFEE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `TEFNE` reader - Tx Event FIFO New Entry Interrupt Enable"] +pub struct TEFNE_R(crate::FieldReader); +impl TEFNE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TEFNE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TEFNE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TEFNE` writer - Tx Event FIFO New Entry Interrupt Enable"] +pub struct TEFNE_W<'a> { + w: &'a mut W, +} +impl<'a> TEFNE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `TEFWE` reader - Tx Event FIFO Watermark Reached Interrupt Enable"] +pub struct TEFWE_R(crate::FieldReader); +impl TEFWE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TEFWE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TEFWE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TEFWE` writer - Tx Event FIFO Watermark Reached Interrupt Enable"] +pub struct TEFWE_W<'a> { + w: &'a mut W, +} +impl<'a> TEFWE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `TEFFE` reader - Tx Event FIFO Full Interrupt Enable"] +pub struct TEFFE_R(crate::FieldReader); +impl TEFFE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TEFFE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TEFFE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TEFFE` writer - Tx Event FIFO Full Interrupt Enable"] +pub struct TEFFE_W<'a> { + w: &'a mut W, +} +impl<'a> TEFFE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `TEFLE` reader - Tx Event FIFO Element Lost Interrupt Enable"] +pub struct TEFLE_R(crate::FieldReader); +impl TEFLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TEFLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TEFLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TEFLE` writer - Tx Event FIFO Element Lost Interrupt Enable"] +pub struct TEFLE_W<'a> { + w: &'a mut W, +} +impl<'a> TEFLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `TSWE` reader - Timestamp Wraparound Interrupt Enable"] +pub struct TSWE_R(crate::FieldReader); +impl TSWE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSWE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSWE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSWE` writer - Timestamp Wraparound Interrupt Enable"] +pub struct TSWE_W<'a> { + w: &'a mut W, +} +impl<'a> TSWE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `MRAFE` reader - Message RAM Access Failure Interrupt Enable"] +pub struct MRAFE_R(crate::FieldReader); +impl MRAFE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MRAFE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MRAFE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MRAFE` writer - Message RAM Access Failure Interrupt Enable"] +pub struct MRAFE_W<'a> { + w: &'a mut W, +} +impl<'a> MRAFE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `TOOE` reader - Timeout Occurred Interrupt Enable"] +pub struct TOOE_R(crate::FieldReader); +impl TOOE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TOOE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TOOE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TOOE` writer - Timeout Occurred Interrupt Enable"] +pub struct TOOE_W<'a> { + w: &'a mut W, +} +impl<'a> TOOE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `DRXE` reader - Message stored to Dedicated Rx Buffer Interrupt Enable"] +pub struct DRXE_R(crate::FieldReader); +impl DRXE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRXE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRXE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRXE` writer - Message stored to Dedicated Rx Buffer Interrupt Enable"] +pub struct DRXE_W<'a> { + w: &'a mut W, +} +impl<'a> DRXE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `BECE` reader - Bit Error Corrected Interrupt Enable"] +pub struct BECE_R(crate::FieldReader); +impl BECE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BECE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BECE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BECE` writer - Bit Error Corrected Interrupt Enable"] +pub struct BECE_W<'a> { + w: &'a mut W, +} +impl<'a> BECE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `BEUE` reader - Bit Error Uncorrected Interrupt Enable"] +pub struct BEUE_R(crate::FieldReader); +impl BEUE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BEUE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BEUE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BEUE` writer - Bit Error Uncorrected Interrupt Enable"] +pub struct BEUE_W<'a> { + w: &'a mut W, +} +impl<'a> BEUE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `ELOE` reader - Error Logging Overflow Interrupt Enable"] +pub struct ELOE_R(crate::FieldReader); +impl ELOE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ELOE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ELOE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ELOE` writer - Error Logging Overflow Interrupt Enable"] +pub struct ELOE_W<'a> { + w: &'a mut W, +} +impl<'a> ELOE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `EPE` reader - Error Passive Interrupt Enable"] +pub struct EPE_R(crate::FieldReader); +impl EPE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EPE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EPE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EPE` writer - Error Passive Interrupt Enable"] +pub struct EPE_W<'a> { + w: &'a mut W, +} +impl<'a> EPE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `EWE` reader - Warning Status Interrupt Enable"] +pub struct EWE_R(crate::FieldReader); +impl EWE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EWE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EWE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EWE` writer - Warning Status Interrupt Enable"] +pub struct EWE_W<'a> { + w: &'a mut W, +} +impl<'a> EWE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `BOE` reader - Bus_Off Status Interrupt Enable"] +pub struct BOE_R(crate::FieldReader); +impl BOE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BOE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BOE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BOE` writer - Bus_Off Status Interrupt Enable"] +pub struct BOE_W<'a> { + w: &'a mut W, +} +impl<'a> BOE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `WDIE` reader - Watchdog Interrupt Interrupt Enable"] +pub struct WDIE_R(crate::FieldReader); +impl WDIE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WDIE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WDIE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WDIE` writer - Watchdog Interrupt Interrupt Enable"] +pub struct WDIE_W<'a> { + w: &'a mut W, +} +impl<'a> WDIE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `PEAE` reader - Protocol Error in Arbitration Phase Enable"] +pub struct PEAE_R(crate::FieldReader); +impl PEAE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEAE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEAE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEAE` writer - Protocol Error in Arbitration Phase Enable"] +pub struct PEAE_W<'a> { + w: &'a mut W, +} +impl<'a> PEAE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +#[doc = "Field `PEDE` reader - Protocol Error in Data Phase Enable"] +pub struct PEDE_R(crate::FieldReader); +impl PEDE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEDE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEDE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEDE` writer - Protocol Error in Data Phase Enable"] +pub struct PEDE_W<'a> { + w: &'a mut W, +} +impl<'a> PEDE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Field `ARAE` reader - Access to Reserved Address Enable"] +pub struct ARAE_R(crate::FieldReader); +impl ARAE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ARAE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ARAE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ARAE` writer - Access to Reserved Address Enable"] +pub struct ARAE_W<'a> { + w: &'a mut W, +} +impl<'a> ARAE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29); + self.w + } +} +impl R { + #[doc = "Bit 0 - Rx FIFO 0 New Message Interrupt Enable"] + #[inline(always)] + pub fn rf0ne(&self) -> RF0NE_R { + RF0NE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Rx FIFO 0 Watermark Reached Interrupt Enable"] + #[inline(always)] + pub fn rf0we(&self) -> RF0WE_R { + RF0WE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Rx FIFO 0 Full Interrupt Enable"] + #[inline(always)] + pub fn rf0fe(&self) -> RF0FE_R { + RF0FE_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Rx FIFO 0 Message Lost Interrupt Enable"] + #[inline(always)] + pub fn rf0le(&self) -> RF0LE_R { + RF0LE_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Rx FIFO 1 New Message Interrupt Enable"] + #[inline(always)] + pub fn rf1ne(&self) -> RF1NE_R { + RF1NE_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Rx FIFO 1 Watermark Reached Interrupt Enable"] + #[inline(always)] + pub fn rf1we(&self) -> RF1WE_R { + RF1WE_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Rx FIFO 1 FIFO Full Interrupt Enable"] + #[inline(always)] + pub fn rf1fe(&self) -> RF1FE_R { + RF1FE_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Rx FIFO 1 Message Lost Interrupt Enable"] + #[inline(always)] + pub fn rf1le(&self) -> RF1LE_R { + RF1LE_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - High Priority Message Interrupt Enable"] + #[inline(always)] + pub fn hpme(&self) -> HPME_R { + HPME_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Timestamp Completed Interrupt Enable"] + #[inline(always)] + pub fn tce(&self) -> TCE_R { + TCE_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Transmission Cancellation Finished Interrupt Enable"] + #[inline(always)] + pub fn tcfe(&self) -> TCFE_R { + TCFE_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Tx FIFO Empty Interrupt Enable"] + #[inline(always)] + pub fn tfee(&self) -> TFEE_R { + TFEE_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Tx Event FIFO New Entry Interrupt Enable"] + #[inline(always)] + pub fn tefne(&self) -> TEFNE_R { + TEFNE_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Tx Event FIFO Watermark Reached Interrupt Enable"] + #[inline(always)] + pub fn tefwe(&self) -> TEFWE_R { + TEFWE_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Tx Event FIFO Full Interrupt Enable"] + #[inline(always)] + pub fn teffe(&self) -> TEFFE_R { + TEFFE_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Tx Event FIFO Element Lost Interrupt Enable"] + #[inline(always)] + pub fn tefle(&self) -> TEFLE_R { + TEFLE_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Timestamp Wraparound Interrupt Enable"] + #[inline(always)] + pub fn tswe(&self) -> TSWE_R { + TSWE_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Message RAM Access Failure Interrupt Enable"] + #[inline(always)] + pub fn mrafe(&self) -> MRAFE_R { + MRAFE_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Timeout Occurred Interrupt Enable"] + #[inline(always)] + pub fn tooe(&self) -> TOOE_R { + TOOE_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Message stored to Dedicated Rx Buffer Interrupt Enable"] + #[inline(always)] + pub fn drxe(&self) -> DRXE_R { + DRXE_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Bit Error Corrected Interrupt Enable"] + #[inline(always)] + pub fn bece(&self) -> BECE_R { + BECE_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Bit Error Uncorrected Interrupt Enable"] + #[inline(always)] + pub fn beue(&self) -> BEUE_R { + BEUE_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Error Logging Overflow Interrupt Enable"] + #[inline(always)] + pub fn eloe(&self) -> ELOE_R { + ELOE_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Error Passive Interrupt Enable"] + #[inline(always)] + pub fn epe(&self) -> EPE_R { + EPE_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24 - Warning Status Interrupt Enable"] + #[inline(always)] + pub fn ewe(&self) -> EWE_R { + EWE_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Bus_Off Status Interrupt Enable"] + #[inline(always)] + pub fn boe(&self) -> BOE_R { + BOE_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Watchdog Interrupt Interrupt Enable"] + #[inline(always)] + pub fn wdie(&self) -> WDIE_R { + WDIE_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Protocol Error in Arbitration Phase Enable"] + #[inline(always)] + pub fn peae(&self) -> PEAE_R { + PEAE_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28 - Protocol Error in Data Phase Enable"] + #[inline(always)] + pub fn pede(&self) -> PEDE_R { + PEDE_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Access to Reserved Address Enable"] + #[inline(always)] + pub fn arae(&self) -> ARAE_R { + ARAE_R::new(((self.bits >> 29) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Rx FIFO 0 New Message Interrupt Enable"] + #[inline(always)] + pub fn rf0ne(&mut self) -> RF0NE_W { + RF0NE_W { w: self } + } + #[doc = "Bit 1 - Rx FIFO 0 Watermark Reached Interrupt Enable"] + #[inline(always)] + pub fn rf0we(&mut self) -> RF0WE_W { + RF0WE_W { w: self } + } + #[doc = "Bit 2 - Rx FIFO 0 Full Interrupt Enable"] + #[inline(always)] + pub fn rf0fe(&mut self) -> RF0FE_W { + RF0FE_W { w: self } + } + #[doc = "Bit 3 - Rx FIFO 0 Message Lost Interrupt Enable"] + #[inline(always)] + pub fn rf0le(&mut self) -> RF0LE_W { + RF0LE_W { w: self } + } + #[doc = "Bit 4 - Rx FIFO 1 New Message Interrupt Enable"] + #[inline(always)] + pub fn rf1ne(&mut self) -> RF1NE_W { + RF1NE_W { w: self } + } + #[doc = "Bit 5 - Rx FIFO 1 Watermark Reached Interrupt Enable"] + #[inline(always)] + pub fn rf1we(&mut self) -> RF1WE_W { + RF1WE_W { w: self } + } + #[doc = "Bit 6 - Rx FIFO 1 FIFO Full Interrupt Enable"] + #[inline(always)] + pub fn rf1fe(&mut self) -> RF1FE_W { + RF1FE_W { w: self } + } + #[doc = "Bit 7 - Rx FIFO 1 Message Lost Interrupt Enable"] + #[inline(always)] + pub fn rf1le(&mut self) -> RF1LE_W { + RF1LE_W { w: self } + } + #[doc = "Bit 8 - High Priority Message Interrupt Enable"] + #[inline(always)] + pub fn hpme(&mut self) -> HPME_W { + HPME_W { w: self } + } + #[doc = "Bit 9 - Timestamp Completed Interrupt Enable"] + #[inline(always)] + pub fn tce(&mut self) -> TCE_W { + TCE_W { w: self } + } + #[doc = "Bit 10 - Transmission Cancellation Finished Interrupt Enable"] + #[inline(always)] + pub fn tcfe(&mut self) -> TCFE_W { + TCFE_W { w: self } + } + #[doc = "Bit 11 - Tx FIFO Empty Interrupt Enable"] + #[inline(always)] + pub fn tfee(&mut self) -> TFEE_W { + TFEE_W { w: self } + } + #[doc = "Bit 12 - Tx Event FIFO New Entry Interrupt Enable"] + #[inline(always)] + pub fn tefne(&mut self) -> TEFNE_W { + TEFNE_W { w: self } + } + #[doc = "Bit 13 - Tx Event FIFO Watermark Reached Interrupt Enable"] + #[inline(always)] + pub fn tefwe(&mut self) -> TEFWE_W { + TEFWE_W { w: self } + } + #[doc = "Bit 14 - Tx Event FIFO Full Interrupt Enable"] + #[inline(always)] + pub fn teffe(&mut self) -> TEFFE_W { + TEFFE_W { w: self } + } + #[doc = "Bit 15 - Tx Event FIFO Element Lost Interrupt Enable"] + #[inline(always)] + pub fn tefle(&mut self) -> TEFLE_W { + TEFLE_W { w: self } + } + #[doc = "Bit 16 - Timestamp Wraparound Interrupt Enable"] + #[inline(always)] + pub fn tswe(&mut self) -> TSWE_W { + TSWE_W { w: self } + } + #[doc = "Bit 17 - Message RAM Access Failure Interrupt Enable"] + #[inline(always)] + pub fn mrafe(&mut self) -> MRAFE_W { + MRAFE_W { w: self } + } + #[doc = "Bit 18 - Timeout Occurred Interrupt Enable"] + #[inline(always)] + pub fn tooe(&mut self) -> TOOE_W { + TOOE_W { w: self } + } + #[doc = "Bit 19 - Message stored to Dedicated Rx Buffer Interrupt Enable"] + #[inline(always)] + pub fn drxe(&mut self) -> DRXE_W { + DRXE_W { w: self } + } + #[doc = "Bit 20 - Bit Error Corrected Interrupt Enable"] + #[inline(always)] + pub fn bece(&mut self) -> BECE_W { + BECE_W { w: self } + } + #[doc = "Bit 21 - Bit Error Uncorrected Interrupt Enable"] + #[inline(always)] + pub fn beue(&mut self) -> BEUE_W { + BEUE_W { w: self } + } + #[doc = "Bit 22 - Error Logging Overflow Interrupt Enable"] + #[inline(always)] + pub fn eloe(&mut self) -> ELOE_W { + ELOE_W { w: self } + } + #[doc = "Bit 23 - Error Passive Interrupt Enable"] + #[inline(always)] + pub fn epe(&mut self) -> EPE_W { + EPE_W { w: self } + } + #[doc = "Bit 24 - Warning Status Interrupt Enable"] + #[inline(always)] + pub fn ewe(&mut self) -> EWE_W { + EWE_W { w: self } + } + #[doc = "Bit 25 - Bus_Off Status Interrupt Enable"] + #[inline(always)] + pub fn boe(&mut self) -> BOE_W { + BOE_W { w: self } + } + #[doc = "Bit 26 - Watchdog Interrupt Interrupt Enable"] + #[inline(always)] + pub fn wdie(&mut self) -> WDIE_W { + WDIE_W { w: self } + } + #[doc = "Bit 27 - Protocol Error in Arbitration Phase Enable"] + #[inline(always)] + pub fn peae(&mut self) -> PEAE_W { + PEAE_W { w: self } + } + #[doc = "Bit 28 - Protocol Error in Data Phase Enable"] + #[inline(always)] + pub fn pede(&mut self) -> PEDE_W { + PEDE_W { w: self } + } + #[doc = "Bit 29 - Access to Reserved Address Enable"] + #[inline(always)] + pub fn arae(&mut self) -> ARAE_W { + ARAE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ie](index.html) module"] +pub struct IE_SPEC; +impl crate::RegisterSpec for IE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ie::R](R) reader structure"] +impl crate::Readable for IE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ie::W](W) writer structure"] +impl crate::Writable for IE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets IE to value 0"] +impl crate::Resettable for IE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/can0/ile.rs b/pac/atsamc21g/src/can0/ile.rs new file mode 100644 index 000000000000..3284b08f7d4c --- /dev/null +++ b/pac/atsamc21g/src/can0/ile.rs @@ -0,0 +1,160 @@ +#[doc = "Register `ILE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ILE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EINT0` reader - Enable Interrupt Line 0"] +pub struct EINT0_R(crate::FieldReader); +impl EINT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EINT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EINT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EINT0` writer - Enable Interrupt Line 0"] +pub struct EINT0_W<'a> { + w: &'a mut W, +} +impl<'a> EINT0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `EINT1` reader - Enable Interrupt Line 1"] +pub struct EINT1_R(crate::FieldReader); +impl EINT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EINT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EINT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EINT1` writer - Enable Interrupt Line 1"] +pub struct EINT1_W<'a> { + w: &'a mut W, +} +impl<'a> EINT1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - Enable Interrupt Line 0"] + #[inline(always)] + pub fn eint0(&self) -> EINT0_R { + EINT0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable Interrupt Line 1"] + #[inline(always)] + pub fn eint1(&self) -> EINT1_R { + EINT1_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Enable Interrupt Line 0"] + #[inline(always)] + pub fn eint0(&mut self) -> EINT0_W { + EINT0_W { w: self } + } + #[doc = "Bit 1 - Enable Interrupt Line 1"] + #[inline(always)] + pub fn eint1(&mut self) -> EINT1_W { + EINT1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Line Enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ile](index.html) module"] +pub struct ILE_SPEC; +impl crate::RegisterSpec for ILE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ile::R](R) reader structure"] +impl crate::Readable for ILE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ile::W](W) writer structure"] +impl crate::Writable for ILE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ILE to value 0"] +impl crate::Resettable for ILE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/can0/ils.rs b/pac/atsamc21g/src/can0/ils.rs new file mode 100644 index 000000000000..14ac6de68d59 --- /dev/null +++ b/pac/atsamc21g/src/can0/ils.rs @@ -0,0 +1,1476 @@ +#[doc = "Register `ILS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ILS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RF0NL` reader - Rx FIFO 0 New Message Interrupt Line"] +pub struct RF0NL_R(crate::FieldReader); +impl RF0NL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF0NL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF0NL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF0NL` writer - Rx FIFO 0 New Message Interrupt Line"] +pub struct RF0NL_W<'a> { + w: &'a mut W, +} +impl<'a> RF0NL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `RF0WL` reader - Rx FIFO 0 Watermark Reached Interrupt Line"] +pub struct RF0WL_R(crate::FieldReader); +impl RF0WL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF0WL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF0WL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF0WL` writer - Rx FIFO 0 Watermark Reached Interrupt Line"] +pub struct RF0WL_W<'a> { + w: &'a mut W, +} +impl<'a> RF0WL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RF0FL` reader - Rx FIFO 0 Full Interrupt Line"] +pub struct RF0FL_R(crate::FieldReader); +impl RF0FL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF0FL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF0FL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF0FL` writer - Rx FIFO 0 Full Interrupt Line"] +pub struct RF0FL_W<'a> { + w: &'a mut W, +} +impl<'a> RF0FL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RF0LL` reader - Rx FIFO 0 Message Lost Interrupt Line"] +pub struct RF0LL_R(crate::FieldReader); +impl RF0LL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF0LL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF0LL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF0LL` writer - Rx FIFO 0 Message Lost Interrupt Line"] +pub struct RF0LL_W<'a> { + w: &'a mut W, +} +impl<'a> RF0LL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `RF1NL` reader - Rx FIFO 1 New Message Interrupt Line"] +pub struct RF1NL_R(crate::FieldReader); +impl RF1NL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF1NL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF1NL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF1NL` writer - Rx FIFO 1 New Message Interrupt Line"] +pub struct RF1NL_W<'a> { + w: &'a mut W, +} +impl<'a> RF1NL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RF1WL` reader - Rx FIFO 1 Watermark Reached Interrupt Line"] +pub struct RF1WL_R(crate::FieldReader); +impl RF1WL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF1WL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF1WL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF1WL` writer - Rx FIFO 1 Watermark Reached Interrupt Line"] +pub struct RF1WL_W<'a> { + w: &'a mut W, +} +impl<'a> RF1WL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `RF1FL` reader - Rx FIFO 1 FIFO Full Interrupt Line"] +pub struct RF1FL_R(crate::FieldReader); +impl RF1FL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF1FL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF1FL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF1FL` writer - Rx FIFO 1 FIFO Full Interrupt Line"] +pub struct RF1FL_W<'a> { + w: &'a mut W, +} +impl<'a> RF1FL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `RF1LL` reader - Rx FIFO 1 Message Lost Interrupt Line"] +pub struct RF1LL_R(crate::FieldReader); +impl RF1LL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF1LL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF1LL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF1LL` writer - Rx FIFO 1 Message Lost Interrupt Line"] +pub struct RF1LL_W<'a> { + w: &'a mut W, +} +impl<'a> RF1LL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `HPML` reader - High Priority Message Interrupt Line"] +pub struct HPML_R(crate::FieldReader); +impl HPML_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HPML_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HPML_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HPML` writer - High Priority Message Interrupt Line"] +pub struct HPML_W<'a> { + w: &'a mut W, +} +impl<'a> HPML_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `TCL` reader - Timestamp Completed Interrupt Line"] +pub struct TCL_R(crate::FieldReader); +impl TCL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCL` writer - Timestamp Completed Interrupt Line"] +pub struct TCL_W<'a> { + w: &'a mut W, +} +impl<'a> TCL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `TCFL` reader - Transmission Cancellation Finished Interrupt Line"] +pub struct TCFL_R(crate::FieldReader); +impl TCFL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCFL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCFL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCFL` writer - Transmission Cancellation Finished Interrupt Line"] +pub struct TCFL_W<'a> { + w: &'a mut W, +} +impl<'a> TCFL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `TFEL` reader - Tx FIFO Empty Interrupt Line"] +pub struct TFEL_R(crate::FieldReader); +impl TFEL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TFEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TFEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TFEL` writer - Tx FIFO Empty Interrupt Line"] +pub struct TFEL_W<'a> { + w: &'a mut W, +} +impl<'a> TFEL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `TEFNL` reader - Tx Event FIFO New Entry Interrupt Line"] +pub struct TEFNL_R(crate::FieldReader); +impl TEFNL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TEFNL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TEFNL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TEFNL` writer - Tx Event FIFO New Entry Interrupt Line"] +pub struct TEFNL_W<'a> { + w: &'a mut W, +} +impl<'a> TEFNL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `TEFWL` reader - Tx Event FIFO Watermark Reached Interrupt Line"] +pub struct TEFWL_R(crate::FieldReader); +impl TEFWL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TEFWL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TEFWL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TEFWL` writer - Tx Event FIFO Watermark Reached Interrupt Line"] +pub struct TEFWL_W<'a> { + w: &'a mut W, +} +impl<'a> TEFWL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `TEFFL` reader - Tx Event FIFO Full Interrupt Line"] +pub struct TEFFL_R(crate::FieldReader); +impl TEFFL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TEFFL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TEFFL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TEFFL` writer - Tx Event FIFO Full Interrupt Line"] +pub struct TEFFL_W<'a> { + w: &'a mut W, +} +impl<'a> TEFFL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `TEFLL` reader - Tx Event FIFO Element Lost Interrupt Line"] +pub struct TEFLL_R(crate::FieldReader); +impl TEFLL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TEFLL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TEFLL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TEFLL` writer - Tx Event FIFO Element Lost Interrupt Line"] +pub struct TEFLL_W<'a> { + w: &'a mut W, +} +impl<'a> TEFLL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `TSWL` reader - Timestamp Wraparound Interrupt Line"] +pub struct TSWL_R(crate::FieldReader); +impl TSWL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSWL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSWL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSWL` writer - Timestamp Wraparound Interrupt Line"] +pub struct TSWL_W<'a> { + w: &'a mut W, +} +impl<'a> TSWL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `MRAFL` reader - Message RAM Access Failure Interrupt Line"] +pub struct MRAFL_R(crate::FieldReader); +impl MRAFL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MRAFL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MRAFL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MRAFL` writer - Message RAM Access Failure Interrupt Line"] +pub struct MRAFL_W<'a> { + w: &'a mut W, +} +impl<'a> MRAFL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `TOOL` reader - Timeout Occurred Interrupt Line"] +pub struct TOOL_R(crate::FieldReader); +impl TOOL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TOOL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TOOL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TOOL` writer - Timeout Occurred Interrupt Line"] +pub struct TOOL_W<'a> { + w: &'a mut W, +} +impl<'a> TOOL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `DRXL` reader - Message stored to Dedicated Rx Buffer Interrupt Line"] +pub struct DRXL_R(crate::FieldReader); +impl DRXL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRXL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRXL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRXL` writer - Message stored to Dedicated Rx Buffer Interrupt Line"] +pub struct DRXL_W<'a> { + w: &'a mut W, +} +impl<'a> DRXL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `BECL` reader - Bit Error Corrected Interrupt Line"] +pub struct BECL_R(crate::FieldReader); +impl BECL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BECL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BECL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BECL` writer - Bit Error Corrected Interrupt Line"] +pub struct BECL_W<'a> { + w: &'a mut W, +} +impl<'a> BECL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `BEUL` reader - Bit Error Uncorrected Interrupt Line"] +pub struct BEUL_R(crate::FieldReader); +impl BEUL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BEUL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BEUL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BEUL` writer - Bit Error Uncorrected Interrupt Line"] +pub struct BEUL_W<'a> { + w: &'a mut W, +} +impl<'a> BEUL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `ELOL` reader - Error Logging Overflow Interrupt Line"] +pub struct ELOL_R(crate::FieldReader); +impl ELOL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ELOL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ELOL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ELOL` writer - Error Logging Overflow Interrupt Line"] +pub struct ELOL_W<'a> { + w: &'a mut W, +} +impl<'a> ELOL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `EPL` reader - Error Passive Interrupt Line"] +pub struct EPL_R(crate::FieldReader); +impl EPL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EPL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EPL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EPL` writer - Error Passive Interrupt Line"] +pub struct EPL_W<'a> { + w: &'a mut W, +} +impl<'a> EPL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `EWL` reader - Warning Status Interrupt Line"] +pub struct EWL_R(crate::FieldReader); +impl EWL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EWL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EWL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EWL` writer - Warning Status Interrupt Line"] +pub struct EWL_W<'a> { + w: &'a mut W, +} +impl<'a> EWL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `BOL` reader - Bus_Off Status Interrupt Line"] +pub struct BOL_R(crate::FieldReader); +impl BOL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BOL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BOL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BOL` writer - Bus_Off Status Interrupt Line"] +pub struct BOL_W<'a> { + w: &'a mut W, +} +impl<'a> BOL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `WDIL` reader - Watchdog Interrupt Interrupt Line"] +pub struct WDIL_R(crate::FieldReader); +impl WDIL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WDIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WDIL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WDIL` writer - Watchdog Interrupt Interrupt Line"] +pub struct WDIL_W<'a> { + w: &'a mut W, +} +impl<'a> WDIL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `PEAL` reader - Protocol Error in Arbitration Phase Line"] +pub struct PEAL_R(crate::FieldReader); +impl PEAL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEAL` writer - Protocol Error in Arbitration Phase Line"] +pub struct PEAL_W<'a> { + w: &'a mut W, +} +impl<'a> PEAL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +#[doc = "Field `PEDL` reader - Protocol Error in Data Phase Line"] +pub struct PEDL_R(crate::FieldReader); +impl PEDL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEDL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEDL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEDL` writer - Protocol Error in Data Phase Line"] +pub struct PEDL_W<'a> { + w: &'a mut W, +} +impl<'a> PEDL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Field `ARAL` reader - Access to Reserved Address Line"] +pub struct ARAL_R(crate::FieldReader); +impl ARAL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ARAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ARAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ARAL` writer - Access to Reserved Address Line"] +pub struct ARAL_W<'a> { + w: &'a mut W, +} +impl<'a> ARAL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29); + self.w + } +} +impl R { + #[doc = "Bit 0 - Rx FIFO 0 New Message Interrupt Line"] + #[inline(always)] + pub fn rf0nl(&self) -> RF0NL_R { + RF0NL_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Rx FIFO 0 Watermark Reached Interrupt Line"] + #[inline(always)] + pub fn rf0wl(&self) -> RF0WL_R { + RF0WL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Rx FIFO 0 Full Interrupt Line"] + #[inline(always)] + pub fn rf0fl(&self) -> RF0FL_R { + RF0FL_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Rx FIFO 0 Message Lost Interrupt Line"] + #[inline(always)] + pub fn rf0ll(&self) -> RF0LL_R { + RF0LL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Rx FIFO 1 New Message Interrupt Line"] + #[inline(always)] + pub fn rf1nl(&self) -> RF1NL_R { + RF1NL_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Rx FIFO 1 Watermark Reached Interrupt Line"] + #[inline(always)] + pub fn rf1wl(&self) -> RF1WL_R { + RF1WL_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Rx FIFO 1 FIFO Full Interrupt Line"] + #[inline(always)] + pub fn rf1fl(&self) -> RF1FL_R { + RF1FL_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Rx FIFO 1 Message Lost Interrupt Line"] + #[inline(always)] + pub fn rf1ll(&self) -> RF1LL_R { + RF1LL_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - High Priority Message Interrupt Line"] + #[inline(always)] + pub fn hpml(&self) -> HPML_R { + HPML_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Timestamp Completed Interrupt Line"] + #[inline(always)] + pub fn tcl(&self) -> TCL_R { + TCL_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Transmission Cancellation Finished Interrupt Line"] + #[inline(always)] + pub fn tcfl(&self) -> TCFL_R { + TCFL_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Tx FIFO Empty Interrupt Line"] + #[inline(always)] + pub fn tfel(&self) -> TFEL_R { + TFEL_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Tx Event FIFO New Entry Interrupt Line"] + #[inline(always)] + pub fn tefnl(&self) -> TEFNL_R { + TEFNL_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Tx Event FIFO Watermark Reached Interrupt Line"] + #[inline(always)] + pub fn tefwl(&self) -> TEFWL_R { + TEFWL_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Tx Event FIFO Full Interrupt Line"] + #[inline(always)] + pub fn teffl(&self) -> TEFFL_R { + TEFFL_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Tx Event FIFO Element Lost Interrupt Line"] + #[inline(always)] + pub fn tefll(&self) -> TEFLL_R { + TEFLL_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Timestamp Wraparound Interrupt Line"] + #[inline(always)] + pub fn tswl(&self) -> TSWL_R { + TSWL_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Message RAM Access Failure Interrupt Line"] + #[inline(always)] + pub fn mrafl(&self) -> MRAFL_R { + MRAFL_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Timeout Occurred Interrupt Line"] + #[inline(always)] + pub fn tool(&self) -> TOOL_R { + TOOL_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Message stored to Dedicated Rx Buffer Interrupt Line"] + #[inline(always)] + pub fn drxl(&self) -> DRXL_R { + DRXL_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Bit Error Corrected Interrupt Line"] + #[inline(always)] + pub fn becl(&self) -> BECL_R { + BECL_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Bit Error Uncorrected Interrupt Line"] + #[inline(always)] + pub fn beul(&self) -> BEUL_R { + BEUL_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Error Logging Overflow Interrupt Line"] + #[inline(always)] + pub fn elol(&self) -> ELOL_R { + ELOL_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Error Passive Interrupt Line"] + #[inline(always)] + pub fn epl(&self) -> EPL_R { + EPL_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24 - Warning Status Interrupt Line"] + #[inline(always)] + pub fn ewl(&self) -> EWL_R { + EWL_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Bus_Off Status Interrupt Line"] + #[inline(always)] + pub fn bol(&self) -> BOL_R { + BOL_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Watchdog Interrupt Interrupt Line"] + #[inline(always)] + pub fn wdil(&self) -> WDIL_R { + WDIL_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Protocol Error in Arbitration Phase Line"] + #[inline(always)] + pub fn peal(&self) -> PEAL_R { + PEAL_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28 - Protocol Error in Data Phase Line"] + #[inline(always)] + pub fn pedl(&self) -> PEDL_R { + PEDL_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Access to Reserved Address Line"] + #[inline(always)] + pub fn aral(&self) -> ARAL_R { + ARAL_R::new(((self.bits >> 29) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Rx FIFO 0 New Message Interrupt Line"] + #[inline(always)] + pub fn rf0nl(&mut self) -> RF0NL_W { + RF0NL_W { w: self } + } + #[doc = "Bit 1 - Rx FIFO 0 Watermark Reached Interrupt Line"] + #[inline(always)] + pub fn rf0wl(&mut self) -> RF0WL_W { + RF0WL_W { w: self } + } + #[doc = "Bit 2 - Rx FIFO 0 Full Interrupt Line"] + #[inline(always)] + pub fn rf0fl(&mut self) -> RF0FL_W { + RF0FL_W { w: self } + } + #[doc = "Bit 3 - Rx FIFO 0 Message Lost Interrupt Line"] + #[inline(always)] + pub fn rf0ll(&mut self) -> RF0LL_W { + RF0LL_W { w: self } + } + #[doc = "Bit 4 - Rx FIFO 1 New Message Interrupt Line"] + #[inline(always)] + pub fn rf1nl(&mut self) -> RF1NL_W { + RF1NL_W { w: self } + } + #[doc = "Bit 5 - Rx FIFO 1 Watermark Reached Interrupt Line"] + #[inline(always)] + pub fn rf1wl(&mut self) -> RF1WL_W { + RF1WL_W { w: self } + } + #[doc = "Bit 6 - Rx FIFO 1 FIFO Full Interrupt Line"] + #[inline(always)] + pub fn rf1fl(&mut self) -> RF1FL_W { + RF1FL_W { w: self } + } + #[doc = "Bit 7 - Rx FIFO 1 Message Lost Interrupt Line"] + #[inline(always)] + pub fn rf1ll(&mut self) -> RF1LL_W { + RF1LL_W { w: self } + } + #[doc = "Bit 8 - High Priority Message Interrupt Line"] + #[inline(always)] + pub fn hpml(&mut self) -> HPML_W { + HPML_W { w: self } + } + #[doc = "Bit 9 - Timestamp Completed Interrupt Line"] + #[inline(always)] + pub fn tcl(&mut self) -> TCL_W { + TCL_W { w: self } + } + #[doc = "Bit 10 - Transmission Cancellation Finished Interrupt Line"] + #[inline(always)] + pub fn tcfl(&mut self) -> TCFL_W { + TCFL_W { w: self } + } + #[doc = "Bit 11 - Tx FIFO Empty Interrupt Line"] + #[inline(always)] + pub fn tfel(&mut self) -> TFEL_W { + TFEL_W { w: self } + } + #[doc = "Bit 12 - Tx Event FIFO New Entry Interrupt Line"] + #[inline(always)] + pub fn tefnl(&mut self) -> TEFNL_W { + TEFNL_W { w: self } + } + #[doc = "Bit 13 - Tx Event FIFO Watermark Reached Interrupt Line"] + #[inline(always)] + pub fn tefwl(&mut self) -> TEFWL_W { + TEFWL_W { w: self } + } + #[doc = "Bit 14 - Tx Event FIFO Full Interrupt Line"] + #[inline(always)] + pub fn teffl(&mut self) -> TEFFL_W { + TEFFL_W { w: self } + } + #[doc = "Bit 15 - Tx Event FIFO Element Lost Interrupt Line"] + #[inline(always)] + pub fn tefll(&mut self) -> TEFLL_W { + TEFLL_W { w: self } + } + #[doc = "Bit 16 - Timestamp Wraparound Interrupt Line"] + #[inline(always)] + pub fn tswl(&mut self) -> TSWL_W { + TSWL_W { w: self } + } + #[doc = "Bit 17 - Message RAM Access Failure Interrupt Line"] + #[inline(always)] + pub fn mrafl(&mut self) -> MRAFL_W { + MRAFL_W { w: self } + } + #[doc = "Bit 18 - Timeout Occurred Interrupt Line"] + #[inline(always)] + pub fn tool(&mut self) -> TOOL_W { + TOOL_W { w: self } + } + #[doc = "Bit 19 - Message stored to Dedicated Rx Buffer Interrupt Line"] + #[inline(always)] + pub fn drxl(&mut self) -> DRXL_W { + DRXL_W { w: self } + } + #[doc = "Bit 20 - Bit Error Corrected Interrupt Line"] + #[inline(always)] + pub fn becl(&mut self) -> BECL_W { + BECL_W { w: self } + } + #[doc = "Bit 21 - Bit Error Uncorrected Interrupt Line"] + #[inline(always)] + pub fn beul(&mut self) -> BEUL_W { + BEUL_W { w: self } + } + #[doc = "Bit 22 - Error Logging Overflow Interrupt Line"] + #[inline(always)] + pub fn elol(&mut self) -> ELOL_W { + ELOL_W { w: self } + } + #[doc = "Bit 23 - Error Passive Interrupt Line"] + #[inline(always)] + pub fn epl(&mut self) -> EPL_W { + EPL_W { w: self } + } + #[doc = "Bit 24 - Warning Status Interrupt Line"] + #[inline(always)] + pub fn ewl(&mut self) -> EWL_W { + EWL_W { w: self } + } + #[doc = "Bit 25 - Bus_Off Status Interrupt Line"] + #[inline(always)] + pub fn bol(&mut self) -> BOL_W { + BOL_W { w: self } + } + #[doc = "Bit 26 - Watchdog Interrupt Interrupt Line"] + #[inline(always)] + pub fn wdil(&mut self) -> WDIL_W { + WDIL_W { w: self } + } + #[doc = "Bit 27 - Protocol Error in Arbitration Phase Line"] + #[inline(always)] + pub fn peal(&mut self) -> PEAL_W { + PEAL_W { w: self } + } + #[doc = "Bit 28 - Protocol Error in Data Phase Line"] + #[inline(always)] + pub fn pedl(&mut self) -> PEDL_W { + PEDL_W { w: self } + } + #[doc = "Bit 29 - Access to Reserved Address Line"] + #[inline(always)] + pub fn aral(&mut self) -> ARAL_W { + ARAL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Line Select\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ils](index.html) module"] +pub struct ILS_SPEC; +impl crate::RegisterSpec for ILS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ils::R](R) reader structure"] +impl crate::Readable for ILS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ils::W](W) writer structure"] +impl crate::Writable for ILS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ILS to value 0"] +impl crate::Resettable for ILS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/can0/ir.rs b/pac/atsamc21g/src/can0/ir.rs new file mode 100644 index 000000000000..ae6efc178861 --- /dev/null +++ b/pac/atsamc21g/src/can0/ir.rs @@ -0,0 +1,1476 @@ +#[doc = "Register `IR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `IR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RF0N` reader - Rx FIFO 0 New Message"] +pub struct RF0N_R(crate::FieldReader); +impl RF0N_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF0N_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF0N_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF0N` writer - Rx FIFO 0 New Message"] +pub struct RF0N_W<'a> { + w: &'a mut W, +} +impl<'a> RF0N_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `RF0W` reader - Rx FIFO 0 Watermark Reached"] +pub struct RF0W_R(crate::FieldReader); +impl RF0W_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF0W_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF0W_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF0W` writer - Rx FIFO 0 Watermark Reached"] +pub struct RF0W_W<'a> { + w: &'a mut W, +} +impl<'a> RF0W_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RF0F` reader - Rx FIFO 0 Full"] +pub struct RF0F_R(crate::FieldReader); +impl RF0F_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF0F_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF0F_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF0F` writer - Rx FIFO 0 Full"] +pub struct RF0F_W<'a> { + w: &'a mut W, +} +impl<'a> RF0F_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RF0L` reader - Rx FIFO 0 Message Lost"] +pub struct RF0L_R(crate::FieldReader); +impl RF0L_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF0L_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF0L_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF0L` writer - Rx FIFO 0 Message Lost"] +pub struct RF0L_W<'a> { + w: &'a mut W, +} +impl<'a> RF0L_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `RF1N` reader - Rx FIFO 1 New Message"] +pub struct RF1N_R(crate::FieldReader); +impl RF1N_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF1N_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF1N_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF1N` writer - Rx FIFO 1 New Message"] +pub struct RF1N_W<'a> { + w: &'a mut W, +} +impl<'a> RF1N_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RF1W` reader - Rx FIFO 1 Watermark Reached"] +pub struct RF1W_R(crate::FieldReader); +impl RF1W_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF1W_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF1W_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF1W` writer - Rx FIFO 1 Watermark Reached"] +pub struct RF1W_W<'a> { + w: &'a mut W, +} +impl<'a> RF1W_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `RF1F` reader - Rx FIFO 1 FIFO Full"] +pub struct RF1F_R(crate::FieldReader); +impl RF1F_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF1F_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF1F_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF1F` writer - Rx FIFO 1 FIFO Full"] +pub struct RF1F_W<'a> { + w: &'a mut W, +} +impl<'a> RF1F_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `RF1L` reader - Rx FIFO 1 Message Lost"] +pub struct RF1L_R(crate::FieldReader); +impl RF1L_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF1L_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF1L_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF1L` writer - Rx FIFO 1 Message Lost"] +pub struct RF1L_W<'a> { + w: &'a mut W, +} +impl<'a> RF1L_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `HPM` reader - High Priority Message"] +pub struct HPM_R(crate::FieldReader); +impl HPM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HPM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HPM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HPM` writer - High Priority Message"] +pub struct HPM_W<'a> { + w: &'a mut W, +} +impl<'a> HPM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `TC` reader - Timestamp Completed"] +pub struct TC_R(crate::FieldReader); +impl TC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC` writer - Timestamp Completed"] +pub struct TC_W<'a> { + w: &'a mut W, +} +impl<'a> TC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `TCF` reader - Transmission Cancellation Finished"] +pub struct TCF_R(crate::FieldReader); +impl TCF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCF` writer - Transmission Cancellation Finished"] +pub struct TCF_W<'a> { + w: &'a mut W, +} +impl<'a> TCF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `TFE` reader - Tx FIFO Empty"] +pub struct TFE_R(crate::FieldReader); +impl TFE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TFE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TFE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TFE` writer - Tx FIFO Empty"] +pub struct TFE_W<'a> { + w: &'a mut W, +} +impl<'a> TFE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `TEFN` reader - Tx Event FIFO New Entry"] +pub struct TEFN_R(crate::FieldReader); +impl TEFN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TEFN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TEFN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TEFN` writer - Tx Event FIFO New Entry"] +pub struct TEFN_W<'a> { + w: &'a mut W, +} +impl<'a> TEFN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `TEFW` reader - Tx Event FIFO Watermark Reached"] +pub struct TEFW_R(crate::FieldReader); +impl TEFW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TEFW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TEFW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TEFW` writer - Tx Event FIFO Watermark Reached"] +pub struct TEFW_W<'a> { + w: &'a mut W, +} +impl<'a> TEFW_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `TEFF` reader - Tx Event FIFO Full"] +pub struct TEFF_R(crate::FieldReader); +impl TEFF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TEFF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TEFF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TEFF` writer - Tx Event FIFO Full"] +pub struct TEFF_W<'a> { + w: &'a mut W, +} +impl<'a> TEFF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `TEFL` reader - Tx Event FIFO Element Lost"] +pub struct TEFL_R(crate::FieldReader); +impl TEFL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TEFL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TEFL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TEFL` writer - Tx Event FIFO Element Lost"] +pub struct TEFL_W<'a> { + w: &'a mut W, +} +impl<'a> TEFL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `TSW` reader - Timestamp Wraparound"] +pub struct TSW_R(crate::FieldReader); +impl TSW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSW` writer - Timestamp Wraparound"] +pub struct TSW_W<'a> { + w: &'a mut W, +} +impl<'a> TSW_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `MRAF` reader - Message RAM Access Failure"] +pub struct MRAF_R(crate::FieldReader); +impl MRAF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MRAF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MRAF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MRAF` writer - Message RAM Access Failure"] +pub struct MRAF_W<'a> { + w: &'a mut W, +} +impl<'a> MRAF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `TOO` reader - Timeout Occurred"] +pub struct TOO_R(crate::FieldReader); +impl TOO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TOO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TOO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TOO` writer - Timeout Occurred"] +pub struct TOO_W<'a> { + w: &'a mut W, +} +impl<'a> TOO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `DRX` reader - Message stored to Dedicated Rx Buffer"] +pub struct DRX_R(crate::FieldReader); +impl DRX_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRX_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRX_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRX` writer - Message stored to Dedicated Rx Buffer"] +pub struct DRX_W<'a> { + w: &'a mut W, +} +impl<'a> DRX_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `BEC` reader - Bit Error Corrected"] +pub struct BEC_R(crate::FieldReader); +impl BEC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BEC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BEC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BEC` writer - Bit Error Corrected"] +pub struct BEC_W<'a> { + w: &'a mut W, +} +impl<'a> BEC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `BEU` reader - Bit Error Uncorrected"] +pub struct BEU_R(crate::FieldReader); +impl BEU_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BEU_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BEU_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BEU` writer - Bit Error Uncorrected"] +pub struct BEU_W<'a> { + w: &'a mut W, +} +impl<'a> BEU_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `ELO` reader - Error Logging Overflow"] +pub struct ELO_R(crate::FieldReader); +impl ELO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ELO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ELO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ELO` writer - Error Logging Overflow"] +pub struct ELO_W<'a> { + w: &'a mut W, +} +impl<'a> ELO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `EP` reader - Error Passive"] +pub struct EP_R(crate::FieldReader); +impl EP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EP` writer - Error Passive"] +pub struct EP_W<'a> { + w: &'a mut W, +} +impl<'a> EP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `EW` reader - Warning Status"] +pub struct EW_R(crate::FieldReader); +impl EW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EW` writer - Warning Status"] +pub struct EW_W<'a> { + w: &'a mut W, +} +impl<'a> EW_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `BO` reader - Bus_Off Status"] +pub struct BO_R(crate::FieldReader); +impl BO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BO` writer - Bus_Off Status"] +pub struct BO_W<'a> { + w: &'a mut W, +} +impl<'a> BO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `WDI` reader - Watchdog Interrupt"] +pub struct WDI_R(crate::FieldReader); +impl WDI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WDI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WDI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WDI` writer - Watchdog Interrupt"] +pub struct WDI_W<'a> { + w: &'a mut W, +} +impl<'a> WDI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `PEA` reader - Protocol Error in Arbitration Phase"] +pub struct PEA_R(crate::FieldReader); +impl PEA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEA` writer - Protocol Error in Arbitration Phase"] +pub struct PEA_W<'a> { + w: &'a mut W, +} +impl<'a> PEA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +#[doc = "Field `PED` reader - Protocol Error in Data Phase"] +pub struct PED_R(crate::FieldReader); +impl PED_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PED_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PED` writer - Protocol Error in Data Phase"] +pub struct PED_W<'a> { + w: &'a mut W, +} +impl<'a> PED_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Field `ARA` reader - Access to Reserved Address"] +pub struct ARA_R(crate::FieldReader); +impl ARA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ARA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ARA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ARA` writer - Access to Reserved Address"] +pub struct ARA_W<'a> { + w: &'a mut W, +} +impl<'a> ARA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29); + self.w + } +} +impl R { + #[doc = "Bit 0 - Rx FIFO 0 New Message"] + #[inline(always)] + pub fn rf0n(&self) -> RF0N_R { + RF0N_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Rx FIFO 0 Watermark Reached"] + #[inline(always)] + pub fn rf0w(&self) -> RF0W_R { + RF0W_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Rx FIFO 0 Full"] + #[inline(always)] + pub fn rf0f(&self) -> RF0F_R { + RF0F_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Rx FIFO 0 Message Lost"] + #[inline(always)] + pub fn rf0l(&self) -> RF0L_R { + RF0L_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Rx FIFO 1 New Message"] + #[inline(always)] + pub fn rf1n(&self) -> RF1N_R { + RF1N_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Rx FIFO 1 Watermark Reached"] + #[inline(always)] + pub fn rf1w(&self) -> RF1W_R { + RF1W_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Rx FIFO 1 FIFO Full"] + #[inline(always)] + pub fn rf1f(&self) -> RF1F_R { + RF1F_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Rx FIFO 1 Message Lost"] + #[inline(always)] + pub fn rf1l(&self) -> RF1L_R { + RF1L_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - High Priority Message"] + #[inline(always)] + pub fn hpm(&self) -> HPM_R { + HPM_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Timestamp Completed"] + #[inline(always)] + pub fn tc(&self) -> TC_R { + TC_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Transmission Cancellation Finished"] + #[inline(always)] + pub fn tcf(&self) -> TCF_R { + TCF_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Tx FIFO Empty"] + #[inline(always)] + pub fn tfe(&self) -> TFE_R { + TFE_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Tx Event FIFO New Entry"] + #[inline(always)] + pub fn tefn(&self) -> TEFN_R { + TEFN_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Tx Event FIFO Watermark Reached"] + #[inline(always)] + pub fn tefw(&self) -> TEFW_R { + TEFW_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Tx Event FIFO Full"] + #[inline(always)] + pub fn teff(&self) -> TEFF_R { + TEFF_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Tx Event FIFO Element Lost"] + #[inline(always)] + pub fn tefl(&self) -> TEFL_R { + TEFL_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Timestamp Wraparound"] + #[inline(always)] + pub fn tsw(&self) -> TSW_R { + TSW_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Message RAM Access Failure"] + #[inline(always)] + pub fn mraf(&self) -> MRAF_R { + MRAF_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Timeout Occurred"] + #[inline(always)] + pub fn too(&self) -> TOO_R { + TOO_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Message stored to Dedicated Rx Buffer"] + #[inline(always)] + pub fn drx(&self) -> DRX_R { + DRX_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Bit Error Corrected"] + #[inline(always)] + pub fn bec(&self) -> BEC_R { + BEC_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Bit Error Uncorrected"] + #[inline(always)] + pub fn beu(&self) -> BEU_R { + BEU_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Error Logging Overflow"] + #[inline(always)] + pub fn elo(&self) -> ELO_R { + ELO_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Error Passive"] + #[inline(always)] + pub fn ep(&self) -> EP_R { + EP_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24 - Warning Status"] + #[inline(always)] + pub fn ew(&self) -> EW_R { + EW_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Bus_Off Status"] + #[inline(always)] + pub fn bo(&self) -> BO_R { + BO_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Watchdog Interrupt"] + #[inline(always)] + pub fn wdi(&self) -> WDI_R { + WDI_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Protocol Error in Arbitration Phase"] + #[inline(always)] + pub fn pea(&self) -> PEA_R { + PEA_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28 - Protocol Error in Data Phase"] + #[inline(always)] + pub fn ped(&self) -> PED_R { + PED_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Access to Reserved Address"] + #[inline(always)] + pub fn ara(&self) -> ARA_R { + ARA_R::new(((self.bits >> 29) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Rx FIFO 0 New Message"] + #[inline(always)] + pub fn rf0n(&mut self) -> RF0N_W { + RF0N_W { w: self } + } + #[doc = "Bit 1 - Rx FIFO 0 Watermark Reached"] + #[inline(always)] + pub fn rf0w(&mut self) -> RF0W_W { + RF0W_W { w: self } + } + #[doc = "Bit 2 - Rx FIFO 0 Full"] + #[inline(always)] + pub fn rf0f(&mut self) -> RF0F_W { + RF0F_W { w: self } + } + #[doc = "Bit 3 - Rx FIFO 0 Message Lost"] + #[inline(always)] + pub fn rf0l(&mut self) -> RF0L_W { + RF0L_W { w: self } + } + #[doc = "Bit 4 - Rx FIFO 1 New Message"] + #[inline(always)] + pub fn rf1n(&mut self) -> RF1N_W { + RF1N_W { w: self } + } + #[doc = "Bit 5 - Rx FIFO 1 Watermark Reached"] + #[inline(always)] + pub fn rf1w(&mut self) -> RF1W_W { + RF1W_W { w: self } + } + #[doc = "Bit 6 - Rx FIFO 1 FIFO Full"] + #[inline(always)] + pub fn rf1f(&mut self) -> RF1F_W { + RF1F_W { w: self } + } + #[doc = "Bit 7 - Rx FIFO 1 Message Lost"] + #[inline(always)] + pub fn rf1l(&mut self) -> RF1L_W { + RF1L_W { w: self } + } + #[doc = "Bit 8 - High Priority Message"] + #[inline(always)] + pub fn hpm(&mut self) -> HPM_W { + HPM_W { w: self } + } + #[doc = "Bit 9 - Timestamp Completed"] + #[inline(always)] + pub fn tc(&mut self) -> TC_W { + TC_W { w: self } + } + #[doc = "Bit 10 - Transmission Cancellation Finished"] + #[inline(always)] + pub fn tcf(&mut self) -> TCF_W { + TCF_W { w: self } + } + #[doc = "Bit 11 - Tx FIFO Empty"] + #[inline(always)] + pub fn tfe(&mut self) -> TFE_W { + TFE_W { w: self } + } + #[doc = "Bit 12 - Tx Event FIFO New Entry"] + #[inline(always)] + pub fn tefn(&mut self) -> TEFN_W { + TEFN_W { w: self } + } + #[doc = "Bit 13 - Tx Event FIFO Watermark Reached"] + #[inline(always)] + pub fn tefw(&mut self) -> TEFW_W { + TEFW_W { w: self } + } + #[doc = "Bit 14 - Tx Event FIFO Full"] + #[inline(always)] + pub fn teff(&mut self) -> TEFF_W { + TEFF_W { w: self } + } + #[doc = "Bit 15 - Tx Event FIFO Element Lost"] + #[inline(always)] + pub fn tefl(&mut self) -> TEFL_W { + TEFL_W { w: self } + } + #[doc = "Bit 16 - Timestamp Wraparound"] + #[inline(always)] + pub fn tsw(&mut self) -> TSW_W { + TSW_W { w: self } + } + #[doc = "Bit 17 - Message RAM Access Failure"] + #[inline(always)] + pub fn mraf(&mut self) -> MRAF_W { + MRAF_W { w: self } + } + #[doc = "Bit 18 - Timeout Occurred"] + #[inline(always)] + pub fn too(&mut self) -> TOO_W { + TOO_W { w: self } + } + #[doc = "Bit 19 - Message stored to Dedicated Rx Buffer"] + #[inline(always)] + pub fn drx(&mut self) -> DRX_W { + DRX_W { w: self } + } + #[doc = "Bit 20 - Bit Error Corrected"] + #[inline(always)] + pub fn bec(&mut self) -> BEC_W { + BEC_W { w: self } + } + #[doc = "Bit 21 - Bit Error Uncorrected"] + #[inline(always)] + pub fn beu(&mut self) -> BEU_W { + BEU_W { w: self } + } + #[doc = "Bit 22 - Error Logging Overflow"] + #[inline(always)] + pub fn elo(&mut self) -> ELO_W { + ELO_W { w: self } + } + #[doc = "Bit 23 - Error Passive"] + #[inline(always)] + pub fn ep(&mut self) -> EP_W { + EP_W { w: self } + } + #[doc = "Bit 24 - Warning Status"] + #[inline(always)] + pub fn ew(&mut self) -> EW_W { + EW_W { w: self } + } + #[doc = "Bit 25 - Bus_Off Status"] + #[inline(always)] + pub fn bo(&mut self) -> BO_W { + BO_W { w: self } + } + #[doc = "Bit 26 - Watchdog Interrupt"] + #[inline(always)] + pub fn wdi(&mut self) -> WDI_W { + WDI_W { w: self } + } + #[doc = "Bit 27 - Protocol Error in Arbitration Phase"] + #[inline(always)] + pub fn pea(&mut self) -> PEA_W { + PEA_W { w: self } + } + #[doc = "Bit 28 - Protocol Error in Data Phase"] + #[inline(always)] + pub fn ped(&mut self) -> PED_W { + PED_W { w: self } + } + #[doc = "Bit 29 - Access to Reserved Address"] + #[inline(always)] + pub fn ara(&mut self) -> ARA_W { + ARA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ir](index.html) module"] +pub struct IR_SPEC; +impl crate::RegisterSpec for IR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ir::R](R) reader structure"] +impl crate::Readable for IR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ir::W](W) writer structure"] +impl crate::Writable for IR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets IR to value 0"] +impl crate::Resettable for IR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/can0/mrcfg.rs b/pac/atsamc21g/src/can0/mrcfg.rs new file mode 100644 index 000000000000..7a4b25f0969a --- /dev/null +++ b/pac/atsamc21g/src/can0/mrcfg.rs @@ -0,0 +1,178 @@ +#[doc = "Register `MRCFG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MRCFG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Quality of Service\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum QOS_A { + #[doc = "0: Background (no sensitive operation)"] + DISABLE = 0, + #[doc = "1: Sensitive Bandwidth"] + LOW = 1, + #[doc = "2: Sensitive Latency"] + MEDIUM = 2, + #[doc = "3: Critical Latency"] + HIGH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: QOS_A) -> Self { + variant as _ + } +} +#[doc = "Field `QOS` reader - Quality of Service"] +pub struct QOS_R(crate::FieldReader); +impl QOS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + QOS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> QOS_A { + match self.bits { + 0 => QOS_A::DISABLE, + 1 => QOS_A::LOW, + 2 => QOS_A::MEDIUM, + 3 => QOS_A::HIGH, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == QOS_A::DISABLE + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == QOS_A::LOW + } + #[doc = "Checks if the value of the field is `MEDIUM`"] + #[inline(always)] + pub fn is_medium(&self) -> bool { + **self == QOS_A::MEDIUM + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == QOS_A::HIGH + } +} +impl core::ops::Deref for QOS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `QOS` writer - Quality of Service"] +pub struct QOS_W<'a> { + w: &'a mut W, +} +impl<'a> QOS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: QOS_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Background (no sensitive operation)"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(QOS_A::DISABLE) + } + #[doc = "Sensitive Bandwidth"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(QOS_A::LOW) + } + #[doc = "Sensitive Latency"] + #[inline(always)] + pub fn medium(self) -> &'a mut W { + self.variant(QOS_A::MEDIUM) + } + #[doc = "Critical Latency"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(QOS_A::HIGH) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u32 & 0x03); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Quality of Service"] + #[inline(always)] + pub fn qos(&self) -> QOS_R { + QOS_R::new((self.bits & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Quality of Service"] + #[inline(always)] + pub fn qos(&mut self) -> QOS_W { + QOS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Message RAM Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mrcfg](index.html) module"] +pub struct MRCFG_SPEC; +impl crate::RegisterSpec for MRCFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [mrcfg::R](R) reader structure"] +impl crate::Readable for MRCFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [mrcfg::W](W) writer structure"] +impl crate::Writable for MRCFG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets MRCFG to value 0x02"] +impl crate::Resettable for MRCFG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x02 + } +} diff --git a/pac/atsamc21g/src/can0/nbtp.rs b/pac/atsamc21g/src/can0/nbtp.rs new file mode 100644 index 000000000000..8de06d283b22 --- /dev/null +++ b/pac/atsamc21g/src/can0/nbtp.rs @@ -0,0 +1,214 @@ +#[doc = "Register `NBTP` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `NBTP` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `NTSEG2` reader - Nominal Time segment after sample point"] +pub struct NTSEG2_R(crate::FieldReader); +impl NTSEG2_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + NTSEG2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NTSEG2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NTSEG2` writer - Nominal Time segment after sample point"] +pub struct NTSEG2_W<'a> { + w: &'a mut W, +} +impl<'a> NTSEG2_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x7f) | (value as u32 & 0x7f); + self.w + } +} +#[doc = "Field `NTSEG1` reader - Nominal Time segment before sample point"] +pub struct NTSEG1_R(crate::FieldReader); +impl NTSEG1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + NTSEG1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NTSEG1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NTSEG1` writer - Nominal Time segment before sample point"] +pub struct NTSEG1_W<'a> { + w: &'a mut W, +} +impl<'a> NTSEG1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +#[doc = "Field `NBRP` reader - Nominal Baud Rate Prescaler"] +pub struct NBRP_R(crate::FieldReader); +impl NBRP_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + NBRP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NBRP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NBRP` writer - Nominal Baud Rate Prescaler"] +pub struct NBRP_W<'a> { + w: &'a mut W, +} +impl<'a> NBRP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01ff << 16)) | ((value as u32 & 0x01ff) << 16); + self.w + } +} +#[doc = "Field `NSJW` reader - Nominal (Re)Synchronization Jump Width"] +pub struct NSJW_R(crate::FieldReader); +impl NSJW_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + NSJW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NSJW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NSJW` writer - Nominal (Re)Synchronization Jump Width"] +pub struct NSJW_W<'a> { + w: &'a mut W, +} +impl<'a> NSJW_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x7f << 25)) | ((value as u32 & 0x7f) << 25); + self.w + } +} +impl R { + #[doc = "Bits 0:6 - Nominal Time segment after sample point"] + #[inline(always)] + pub fn ntseg2(&self) -> NTSEG2_R { + NTSEG2_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bits 8:15 - Nominal Time segment before sample point"] + #[inline(always)] + pub fn ntseg1(&self) -> NTSEG1_R { + NTSEG1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:24 - Nominal Baud Rate Prescaler"] + #[inline(always)] + pub fn nbrp(&self) -> NBRP_R { + NBRP_R::new(((self.bits >> 16) & 0x01ff) as u16) + } + #[doc = "Bits 25:31 - Nominal (Re)Synchronization Jump Width"] + #[inline(always)] + pub fn nsjw(&self) -> NSJW_R { + NSJW_R::new(((self.bits >> 25) & 0x7f) as u8) + } +} +impl W { + #[doc = "Bits 0:6 - Nominal Time segment after sample point"] + #[inline(always)] + pub fn ntseg2(&mut self) -> NTSEG2_W { + NTSEG2_W { w: self } + } + #[doc = "Bits 8:15 - Nominal Time segment before sample point"] + #[inline(always)] + pub fn ntseg1(&mut self) -> NTSEG1_W { + NTSEG1_W { w: self } + } + #[doc = "Bits 16:24 - Nominal Baud Rate Prescaler"] + #[inline(always)] + pub fn nbrp(&mut self) -> NBRP_W { + NBRP_W { w: self } + } + #[doc = "Bits 25:31 - Nominal (Re)Synchronization Jump Width"] + #[inline(always)] + pub fn nsjw(&mut self) -> NSJW_W { + NSJW_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Nominal Bit Timing and Prescaler\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [nbtp](index.html) module"] +pub struct NBTP_SPEC; +impl crate::RegisterSpec for NBTP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [nbtp::R](R) reader structure"] +impl crate::Readable for NBTP_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [nbtp::W](W) writer structure"] +impl crate::Writable for NBTP_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets NBTP to value 0x0600_0a03"] +impl crate::Resettable for NBTP_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0600_0a03 + } +} diff --git a/pac/atsamc21g/src/can0/ndat1.rs b/pac/atsamc21g/src/can0/ndat1.rs new file mode 100644 index 000000000000..63da465a27d8 --- /dev/null +++ b/pac/atsamc21g/src/can0/ndat1.rs @@ -0,0 +1,1570 @@ +#[doc = "Register `NDAT1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `NDAT1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ND0` reader - New Data 0"] +pub struct ND0_R(crate::FieldReader); +impl ND0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND0` writer - New Data 0"] +pub struct ND0_W<'a> { + w: &'a mut W, +} +impl<'a> ND0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ND1` reader - New Data 1"] +pub struct ND1_R(crate::FieldReader); +impl ND1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND1` writer - New Data 1"] +pub struct ND1_W<'a> { + w: &'a mut W, +} +impl<'a> ND1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ND2` reader - New Data 2"] +pub struct ND2_R(crate::FieldReader); +impl ND2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND2` writer - New Data 2"] +pub struct ND2_W<'a> { + w: &'a mut W, +} +impl<'a> ND2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `ND3` reader - New Data 3"] +pub struct ND3_R(crate::FieldReader); +impl ND3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND3` writer - New Data 3"] +pub struct ND3_W<'a> { + w: &'a mut W, +} +impl<'a> ND3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ND4` reader - New Data 4"] +pub struct ND4_R(crate::FieldReader); +impl ND4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND4` writer - New Data 4"] +pub struct ND4_W<'a> { + w: &'a mut W, +} +impl<'a> ND4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `ND5` reader - New Data 5"] +pub struct ND5_R(crate::FieldReader); +impl ND5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND5` writer - New Data 5"] +pub struct ND5_W<'a> { + w: &'a mut W, +} +impl<'a> ND5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `ND6` reader - New Data 6"] +pub struct ND6_R(crate::FieldReader); +impl ND6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND6` writer - New Data 6"] +pub struct ND6_W<'a> { + w: &'a mut W, +} +impl<'a> ND6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ND7` reader - New Data 7"] +pub struct ND7_R(crate::FieldReader); +impl ND7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND7` writer - New Data 7"] +pub struct ND7_W<'a> { + w: &'a mut W, +} +impl<'a> ND7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `ND8` reader - New Data 8"] +pub struct ND8_R(crate::FieldReader); +impl ND8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND8` writer - New Data 8"] +pub struct ND8_W<'a> { + w: &'a mut W, +} +impl<'a> ND8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `ND9` reader - New Data 9"] +pub struct ND9_R(crate::FieldReader); +impl ND9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND9` writer - New Data 9"] +pub struct ND9_W<'a> { + w: &'a mut W, +} +impl<'a> ND9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `ND10` reader - New Data 10"] +pub struct ND10_R(crate::FieldReader); +impl ND10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND10` writer - New Data 10"] +pub struct ND10_W<'a> { + w: &'a mut W, +} +impl<'a> ND10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `ND11` reader - New Data 11"] +pub struct ND11_R(crate::FieldReader); +impl ND11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND11` writer - New Data 11"] +pub struct ND11_W<'a> { + w: &'a mut W, +} +impl<'a> ND11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `ND12` reader - New Data 12"] +pub struct ND12_R(crate::FieldReader); +impl ND12_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND12_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND12_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND12` writer - New Data 12"] +pub struct ND12_W<'a> { + w: &'a mut W, +} +impl<'a> ND12_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `ND13` reader - New Data 13"] +pub struct ND13_R(crate::FieldReader); +impl ND13_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND13_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND13_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND13` writer - New Data 13"] +pub struct ND13_W<'a> { + w: &'a mut W, +} +impl<'a> ND13_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `ND14` reader - New Data 14"] +pub struct ND14_R(crate::FieldReader); +impl ND14_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND14_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND14_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND14` writer - New Data 14"] +pub struct ND14_W<'a> { + w: &'a mut W, +} +impl<'a> ND14_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `ND15` reader - New Data 15"] +pub struct ND15_R(crate::FieldReader); +impl ND15_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND15_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND15_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND15` writer - New Data 15"] +pub struct ND15_W<'a> { + w: &'a mut W, +} +impl<'a> ND15_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `ND16` reader - New Data 16"] +pub struct ND16_R(crate::FieldReader); +impl ND16_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND16_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND16_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND16` writer - New Data 16"] +pub struct ND16_W<'a> { + w: &'a mut W, +} +impl<'a> ND16_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `ND17` reader - New Data 17"] +pub struct ND17_R(crate::FieldReader); +impl ND17_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND17_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND17_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND17` writer - New Data 17"] +pub struct ND17_W<'a> { + w: &'a mut W, +} +impl<'a> ND17_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `ND18` reader - New Data 18"] +pub struct ND18_R(crate::FieldReader); +impl ND18_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND18_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND18_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND18` writer - New Data 18"] +pub struct ND18_W<'a> { + w: &'a mut W, +} +impl<'a> ND18_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `ND19` reader - New Data 19"] +pub struct ND19_R(crate::FieldReader); +impl ND19_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND19_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND19_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND19` writer - New Data 19"] +pub struct ND19_W<'a> { + w: &'a mut W, +} +impl<'a> ND19_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `ND20` reader - New Data 20"] +pub struct ND20_R(crate::FieldReader); +impl ND20_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND20_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND20_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND20` writer - New Data 20"] +pub struct ND20_W<'a> { + w: &'a mut W, +} +impl<'a> ND20_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `ND21` reader - New Data 21"] +pub struct ND21_R(crate::FieldReader); +impl ND21_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND21_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND21_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND21` writer - New Data 21"] +pub struct ND21_W<'a> { + w: &'a mut W, +} +impl<'a> ND21_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `ND22` reader - New Data 22"] +pub struct ND22_R(crate::FieldReader); +impl ND22_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND22_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND22_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND22` writer - New Data 22"] +pub struct ND22_W<'a> { + w: &'a mut W, +} +impl<'a> ND22_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `ND23` reader - New Data 23"] +pub struct ND23_R(crate::FieldReader); +impl ND23_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND23_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND23_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND23` writer - New Data 23"] +pub struct ND23_W<'a> { + w: &'a mut W, +} +impl<'a> ND23_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `ND24` reader - New Data 24"] +pub struct ND24_R(crate::FieldReader); +impl ND24_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND24_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND24_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND24` writer - New Data 24"] +pub struct ND24_W<'a> { + w: &'a mut W, +} +impl<'a> ND24_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `ND25` reader - New Data 25"] +pub struct ND25_R(crate::FieldReader); +impl ND25_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND25_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND25_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND25` writer - New Data 25"] +pub struct ND25_W<'a> { + w: &'a mut W, +} +impl<'a> ND25_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `ND26` reader - New Data 26"] +pub struct ND26_R(crate::FieldReader); +impl ND26_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND26_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND26_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND26` writer - New Data 26"] +pub struct ND26_W<'a> { + w: &'a mut W, +} +impl<'a> ND26_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `ND27` reader - New Data 27"] +pub struct ND27_R(crate::FieldReader); +impl ND27_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND27_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND27_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND27` writer - New Data 27"] +pub struct ND27_W<'a> { + w: &'a mut W, +} +impl<'a> ND27_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +#[doc = "Field `ND28` reader - New Data 28"] +pub struct ND28_R(crate::FieldReader); +impl ND28_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND28_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND28_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND28` writer - New Data 28"] +pub struct ND28_W<'a> { + w: &'a mut W, +} +impl<'a> ND28_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Field `ND29` reader - New Data 29"] +pub struct ND29_R(crate::FieldReader); +impl ND29_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND29_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND29_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND29` writer - New Data 29"] +pub struct ND29_W<'a> { + w: &'a mut W, +} +impl<'a> ND29_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29); + self.w + } +} +#[doc = "Field `ND30` reader - New Data 30"] +pub struct ND30_R(crate::FieldReader); +impl ND30_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND30_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND30_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND30` writer - New Data 30"] +pub struct ND30_W<'a> { + w: &'a mut W, +} +impl<'a> ND30_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +#[doc = "Field `ND31` reader - New Data 31"] +pub struct ND31_R(crate::FieldReader); +impl ND31_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND31_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND31_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND31` writer - New Data 31"] +pub struct ND31_W<'a> { + w: &'a mut W, +} +impl<'a> ND31_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bit 0 - New Data 0"] + #[inline(always)] + pub fn nd0(&self) -> ND0_R { + ND0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - New Data 1"] + #[inline(always)] + pub fn nd1(&self) -> ND1_R { + ND1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - New Data 2"] + #[inline(always)] + pub fn nd2(&self) -> ND2_R { + ND2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - New Data 3"] + #[inline(always)] + pub fn nd3(&self) -> ND3_R { + ND3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - New Data 4"] + #[inline(always)] + pub fn nd4(&self) -> ND4_R { + ND4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - New Data 5"] + #[inline(always)] + pub fn nd5(&self) -> ND5_R { + ND5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - New Data 6"] + #[inline(always)] + pub fn nd6(&self) -> ND6_R { + ND6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - New Data 7"] + #[inline(always)] + pub fn nd7(&self) -> ND7_R { + ND7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - New Data 8"] + #[inline(always)] + pub fn nd8(&self) -> ND8_R { + ND8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - New Data 9"] + #[inline(always)] + pub fn nd9(&self) -> ND9_R { + ND9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - New Data 10"] + #[inline(always)] + pub fn nd10(&self) -> ND10_R { + ND10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - New Data 11"] + #[inline(always)] + pub fn nd11(&self) -> ND11_R { + ND11_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - New Data 12"] + #[inline(always)] + pub fn nd12(&self) -> ND12_R { + ND12_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - New Data 13"] + #[inline(always)] + pub fn nd13(&self) -> ND13_R { + ND13_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - New Data 14"] + #[inline(always)] + pub fn nd14(&self) -> ND14_R { + ND14_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - New Data 15"] + #[inline(always)] + pub fn nd15(&self) -> ND15_R { + ND15_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - New Data 16"] + #[inline(always)] + pub fn nd16(&self) -> ND16_R { + ND16_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - New Data 17"] + #[inline(always)] + pub fn nd17(&self) -> ND17_R { + ND17_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - New Data 18"] + #[inline(always)] + pub fn nd18(&self) -> ND18_R { + ND18_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - New Data 19"] + #[inline(always)] + pub fn nd19(&self) -> ND19_R { + ND19_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - New Data 20"] + #[inline(always)] + pub fn nd20(&self) -> ND20_R { + ND20_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - New Data 21"] + #[inline(always)] + pub fn nd21(&self) -> ND21_R { + ND21_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - New Data 22"] + #[inline(always)] + pub fn nd22(&self) -> ND22_R { + ND22_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - New Data 23"] + #[inline(always)] + pub fn nd23(&self) -> ND23_R { + ND23_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24 - New Data 24"] + #[inline(always)] + pub fn nd24(&self) -> ND24_R { + ND24_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - New Data 25"] + #[inline(always)] + pub fn nd25(&self) -> ND25_R { + ND25_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - New Data 26"] + #[inline(always)] + pub fn nd26(&self) -> ND26_R { + ND26_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - New Data 27"] + #[inline(always)] + pub fn nd27(&self) -> ND27_R { + ND27_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28 - New Data 28"] + #[inline(always)] + pub fn nd28(&self) -> ND28_R { + ND28_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - New Data 29"] + #[inline(always)] + pub fn nd29(&self) -> ND29_R { + ND29_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - New Data 30"] + #[inline(always)] + pub fn nd30(&self) -> ND30_R { + ND30_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 31 - New Data 31"] + #[inline(always)] + pub fn nd31(&self) -> ND31_R { + ND31_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - New Data 0"] + #[inline(always)] + pub fn nd0(&mut self) -> ND0_W { + ND0_W { w: self } + } + #[doc = "Bit 1 - New Data 1"] + #[inline(always)] + pub fn nd1(&mut self) -> ND1_W { + ND1_W { w: self } + } + #[doc = "Bit 2 - New Data 2"] + #[inline(always)] + pub fn nd2(&mut self) -> ND2_W { + ND2_W { w: self } + } + #[doc = "Bit 3 - New Data 3"] + #[inline(always)] + pub fn nd3(&mut self) -> ND3_W { + ND3_W { w: self } + } + #[doc = "Bit 4 - New Data 4"] + #[inline(always)] + pub fn nd4(&mut self) -> ND4_W { + ND4_W { w: self } + } + #[doc = "Bit 5 - New Data 5"] + #[inline(always)] + pub fn nd5(&mut self) -> ND5_W { + ND5_W { w: self } + } + #[doc = "Bit 6 - New Data 6"] + #[inline(always)] + pub fn nd6(&mut self) -> ND6_W { + ND6_W { w: self } + } + #[doc = "Bit 7 - New Data 7"] + #[inline(always)] + pub fn nd7(&mut self) -> ND7_W { + ND7_W { w: self } + } + #[doc = "Bit 8 - New Data 8"] + #[inline(always)] + pub fn nd8(&mut self) -> ND8_W { + ND8_W { w: self } + } + #[doc = "Bit 9 - New Data 9"] + #[inline(always)] + pub fn nd9(&mut self) -> ND9_W { + ND9_W { w: self } + } + #[doc = "Bit 10 - New Data 10"] + #[inline(always)] + pub fn nd10(&mut self) -> ND10_W { + ND10_W { w: self } + } + #[doc = "Bit 11 - New Data 11"] + #[inline(always)] + pub fn nd11(&mut self) -> ND11_W { + ND11_W { w: self } + } + #[doc = "Bit 12 - New Data 12"] + #[inline(always)] + pub fn nd12(&mut self) -> ND12_W { + ND12_W { w: self } + } + #[doc = "Bit 13 - New Data 13"] + #[inline(always)] + pub fn nd13(&mut self) -> ND13_W { + ND13_W { w: self } + } + #[doc = "Bit 14 - New Data 14"] + #[inline(always)] + pub fn nd14(&mut self) -> ND14_W { + ND14_W { w: self } + } + #[doc = "Bit 15 - New Data 15"] + #[inline(always)] + pub fn nd15(&mut self) -> ND15_W { + ND15_W { w: self } + } + #[doc = "Bit 16 - New Data 16"] + #[inline(always)] + pub fn nd16(&mut self) -> ND16_W { + ND16_W { w: self } + } + #[doc = "Bit 17 - New Data 17"] + #[inline(always)] + pub fn nd17(&mut self) -> ND17_W { + ND17_W { w: self } + } + #[doc = "Bit 18 - New Data 18"] + #[inline(always)] + pub fn nd18(&mut self) -> ND18_W { + ND18_W { w: self } + } + #[doc = "Bit 19 - New Data 19"] + #[inline(always)] + pub fn nd19(&mut self) -> ND19_W { + ND19_W { w: self } + } + #[doc = "Bit 20 - New Data 20"] + #[inline(always)] + pub fn nd20(&mut self) -> ND20_W { + ND20_W { w: self } + } + #[doc = "Bit 21 - New Data 21"] + #[inline(always)] + pub fn nd21(&mut self) -> ND21_W { + ND21_W { w: self } + } + #[doc = "Bit 22 - New Data 22"] + #[inline(always)] + pub fn nd22(&mut self) -> ND22_W { + ND22_W { w: self } + } + #[doc = "Bit 23 - New Data 23"] + #[inline(always)] + pub fn nd23(&mut self) -> ND23_W { + ND23_W { w: self } + } + #[doc = "Bit 24 - New Data 24"] + #[inline(always)] + pub fn nd24(&mut self) -> ND24_W { + ND24_W { w: self } + } + #[doc = "Bit 25 - New Data 25"] + #[inline(always)] + pub fn nd25(&mut self) -> ND25_W { + ND25_W { w: self } + } + #[doc = "Bit 26 - New Data 26"] + #[inline(always)] + pub fn nd26(&mut self) -> ND26_W { + ND26_W { w: self } + } + #[doc = "Bit 27 - New Data 27"] + #[inline(always)] + pub fn nd27(&mut self) -> ND27_W { + ND27_W { w: self } + } + #[doc = "Bit 28 - New Data 28"] + #[inline(always)] + pub fn nd28(&mut self) -> ND28_W { + ND28_W { w: self } + } + #[doc = "Bit 29 - New Data 29"] + #[inline(always)] + pub fn nd29(&mut self) -> ND29_W { + ND29_W { w: self } + } + #[doc = "Bit 30 - New Data 30"] + #[inline(always)] + pub fn nd30(&mut self) -> ND30_W { + ND30_W { w: self } + } + #[doc = "Bit 31 - New Data 31"] + #[inline(always)] + pub fn nd31(&mut self) -> ND31_W { + ND31_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "New Data 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ndat1](index.html) module"] +pub struct NDAT1_SPEC; +impl crate::RegisterSpec for NDAT1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ndat1::R](R) reader structure"] +impl crate::Readable for NDAT1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ndat1::W](W) writer structure"] +impl crate::Writable for NDAT1_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets NDAT1 to value 0"] +impl crate::Resettable for NDAT1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/can0/ndat2.rs b/pac/atsamc21g/src/can0/ndat2.rs new file mode 100644 index 000000000000..ada8dac123fb --- /dev/null +++ b/pac/atsamc21g/src/can0/ndat2.rs @@ -0,0 +1,1570 @@ +#[doc = "Register `NDAT2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `NDAT2` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ND32` reader - New Data 32"] +pub struct ND32_R(crate::FieldReader); +impl ND32_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND32_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND32_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND32` writer - New Data 32"] +pub struct ND32_W<'a> { + w: &'a mut W, +} +impl<'a> ND32_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ND33` reader - New Data 33"] +pub struct ND33_R(crate::FieldReader); +impl ND33_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND33_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND33_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND33` writer - New Data 33"] +pub struct ND33_W<'a> { + w: &'a mut W, +} +impl<'a> ND33_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ND34` reader - New Data 34"] +pub struct ND34_R(crate::FieldReader); +impl ND34_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND34_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND34_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND34` writer - New Data 34"] +pub struct ND34_W<'a> { + w: &'a mut W, +} +impl<'a> ND34_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `ND35` reader - New Data 35"] +pub struct ND35_R(crate::FieldReader); +impl ND35_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND35_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND35_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND35` writer - New Data 35"] +pub struct ND35_W<'a> { + w: &'a mut W, +} +impl<'a> ND35_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ND36` reader - New Data 36"] +pub struct ND36_R(crate::FieldReader); +impl ND36_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND36_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND36_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND36` writer - New Data 36"] +pub struct ND36_W<'a> { + w: &'a mut W, +} +impl<'a> ND36_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `ND37` reader - New Data 37"] +pub struct ND37_R(crate::FieldReader); +impl ND37_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND37_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND37_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND37` writer - New Data 37"] +pub struct ND37_W<'a> { + w: &'a mut W, +} +impl<'a> ND37_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `ND38` reader - New Data 38"] +pub struct ND38_R(crate::FieldReader); +impl ND38_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND38_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND38_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND38` writer - New Data 38"] +pub struct ND38_W<'a> { + w: &'a mut W, +} +impl<'a> ND38_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ND39` reader - New Data 39"] +pub struct ND39_R(crate::FieldReader); +impl ND39_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND39_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND39_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND39` writer - New Data 39"] +pub struct ND39_W<'a> { + w: &'a mut W, +} +impl<'a> ND39_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `ND40` reader - New Data 40"] +pub struct ND40_R(crate::FieldReader); +impl ND40_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND40_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND40_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND40` writer - New Data 40"] +pub struct ND40_W<'a> { + w: &'a mut W, +} +impl<'a> ND40_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `ND41` reader - New Data 41"] +pub struct ND41_R(crate::FieldReader); +impl ND41_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND41_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND41_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND41` writer - New Data 41"] +pub struct ND41_W<'a> { + w: &'a mut W, +} +impl<'a> ND41_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `ND42` reader - New Data 42"] +pub struct ND42_R(crate::FieldReader); +impl ND42_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND42_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND42_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND42` writer - New Data 42"] +pub struct ND42_W<'a> { + w: &'a mut W, +} +impl<'a> ND42_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `ND43` reader - New Data 43"] +pub struct ND43_R(crate::FieldReader); +impl ND43_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND43_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND43_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND43` writer - New Data 43"] +pub struct ND43_W<'a> { + w: &'a mut W, +} +impl<'a> ND43_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `ND44` reader - New Data 44"] +pub struct ND44_R(crate::FieldReader); +impl ND44_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND44_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND44_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND44` writer - New Data 44"] +pub struct ND44_W<'a> { + w: &'a mut W, +} +impl<'a> ND44_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `ND45` reader - New Data 45"] +pub struct ND45_R(crate::FieldReader); +impl ND45_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND45_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND45_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND45` writer - New Data 45"] +pub struct ND45_W<'a> { + w: &'a mut W, +} +impl<'a> ND45_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `ND46` reader - New Data 46"] +pub struct ND46_R(crate::FieldReader); +impl ND46_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND46_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND46_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND46` writer - New Data 46"] +pub struct ND46_W<'a> { + w: &'a mut W, +} +impl<'a> ND46_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `ND47` reader - New Data 47"] +pub struct ND47_R(crate::FieldReader); +impl ND47_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND47_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND47_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND47` writer - New Data 47"] +pub struct ND47_W<'a> { + w: &'a mut W, +} +impl<'a> ND47_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `ND48` reader - New Data 48"] +pub struct ND48_R(crate::FieldReader); +impl ND48_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND48_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND48_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND48` writer - New Data 48"] +pub struct ND48_W<'a> { + w: &'a mut W, +} +impl<'a> ND48_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `ND49` reader - New Data 49"] +pub struct ND49_R(crate::FieldReader); +impl ND49_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND49_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND49_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND49` writer - New Data 49"] +pub struct ND49_W<'a> { + w: &'a mut W, +} +impl<'a> ND49_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `ND50` reader - New Data 50"] +pub struct ND50_R(crate::FieldReader); +impl ND50_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND50_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND50_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND50` writer - New Data 50"] +pub struct ND50_W<'a> { + w: &'a mut W, +} +impl<'a> ND50_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `ND51` reader - New Data 51"] +pub struct ND51_R(crate::FieldReader); +impl ND51_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND51_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND51_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND51` writer - New Data 51"] +pub struct ND51_W<'a> { + w: &'a mut W, +} +impl<'a> ND51_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `ND52` reader - New Data 52"] +pub struct ND52_R(crate::FieldReader); +impl ND52_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND52_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND52_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND52` writer - New Data 52"] +pub struct ND52_W<'a> { + w: &'a mut W, +} +impl<'a> ND52_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `ND53` reader - New Data 53"] +pub struct ND53_R(crate::FieldReader); +impl ND53_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND53_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND53_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND53` writer - New Data 53"] +pub struct ND53_W<'a> { + w: &'a mut W, +} +impl<'a> ND53_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `ND54` reader - New Data 54"] +pub struct ND54_R(crate::FieldReader); +impl ND54_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND54_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND54_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND54` writer - New Data 54"] +pub struct ND54_W<'a> { + w: &'a mut W, +} +impl<'a> ND54_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `ND55` reader - New Data 55"] +pub struct ND55_R(crate::FieldReader); +impl ND55_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND55_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND55_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND55` writer - New Data 55"] +pub struct ND55_W<'a> { + w: &'a mut W, +} +impl<'a> ND55_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `ND56` reader - New Data 56"] +pub struct ND56_R(crate::FieldReader); +impl ND56_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND56_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND56_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND56` writer - New Data 56"] +pub struct ND56_W<'a> { + w: &'a mut W, +} +impl<'a> ND56_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `ND57` reader - New Data 57"] +pub struct ND57_R(crate::FieldReader); +impl ND57_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND57_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND57_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND57` writer - New Data 57"] +pub struct ND57_W<'a> { + w: &'a mut W, +} +impl<'a> ND57_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `ND58` reader - New Data 58"] +pub struct ND58_R(crate::FieldReader); +impl ND58_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND58_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND58_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND58` writer - New Data 58"] +pub struct ND58_W<'a> { + w: &'a mut W, +} +impl<'a> ND58_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `ND59` reader - New Data 59"] +pub struct ND59_R(crate::FieldReader); +impl ND59_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND59_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND59_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND59` writer - New Data 59"] +pub struct ND59_W<'a> { + w: &'a mut W, +} +impl<'a> ND59_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +#[doc = "Field `ND60` reader - New Data 60"] +pub struct ND60_R(crate::FieldReader); +impl ND60_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND60_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND60_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND60` writer - New Data 60"] +pub struct ND60_W<'a> { + w: &'a mut W, +} +impl<'a> ND60_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Field `ND61` reader - New Data 61"] +pub struct ND61_R(crate::FieldReader); +impl ND61_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND61_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND61_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND61` writer - New Data 61"] +pub struct ND61_W<'a> { + w: &'a mut W, +} +impl<'a> ND61_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29); + self.w + } +} +#[doc = "Field `ND62` reader - New Data 62"] +pub struct ND62_R(crate::FieldReader); +impl ND62_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND62_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND62_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND62` writer - New Data 62"] +pub struct ND62_W<'a> { + w: &'a mut W, +} +impl<'a> ND62_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +#[doc = "Field `ND63` reader - New Data 63"] +pub struct ND63_R(crate::FieldReader); +impl ND63_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND63_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND63_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND63` writer - New Data 63"] +pub struct ND63_W<'a> { + w: &'a mut W, +} +impl<'a> ND63_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bit 0 - New Data 32"] + #[inline(always)] + pub fn nd32(&self) -> ND32_R { + ND32_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - New Data 33"] + #[inline(always)] + pub fn nd33(&self) -> ND33_R { + ND33_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - New Data 34"] + #[inline(always)] + pub fn nd34(&self) -> ND34_R { + ND34_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - New Data 35"] + #[inline(always)] + pub fn nd35(&self) -> ND35_R { + ND35_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - New Data 36"] + #[inline(always)] + pub fn nd36(&self) -> ND36_R { + ND36_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - New Data 37"] + #[inline(always)] + pub fn nd37(&self) -> ND37_R { + ND37_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - New Data 38"] + #[inline(always)] + pub fn nd38(&self) -> ND38_R { + ND38_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - New Data 39"] + #[inline(always)] + pub fn nd39(&self) -> ND39_R { + ND39_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - New Data 40"] + #[inline(always)] + pub fn nd40(&self) -> ND40_R { + ND40_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - New Data 41"] + #[inline(always)] + pub fn nd41(&self) -> ND41_R { + ND41_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - New Data 42"] + #[inline(always)] + pub fn nd42(&self) -> ND42_R { + ND42_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - New Data 43"] + #[inline(always)] + pub fn nd43(&self) -> ND43_R { + ND43_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - New Data 44"] + #[inline(always)] + pub fn nd44(&self) -> ND44_R { + ND44_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - New Data 45"] + #[inline(always)] + pub fn nd45(&self) -> ND45_R { + ND45_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - New Data 46"] + #[inline(always)] + pub fn nd46(&self) -> ND46_R { + ND46_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - New Data 47"] + #[inline(always)] + pub fn nd47(&self) -> ND47_R { + ND47_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - New Data 48"] + #[inline(always)] + pub fn nd48(&self) -> ND48_R { + ND48_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - New Data 49"] + #[inline(always)] + pub fn nd49(&self) -> ND49_R { + ND49_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - New Data 50"] + #[inline(always)] + pub fn nd50(&self) -> ND50_R { + ND50_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - New Data 51"] + #[inline(always)] + pub fn nd51(&self) -> ND51_R { + ND51_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - New Data 52"] + #[inline(always)] + pub fn nd52(&self) -> ND52_R { + ND52_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - New Data 53"] + #[inline(always)] + pub fn nd53(&self) -> ND53_R { + ND53_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - New Data 54"] + #[inline(always)] + pub fn nd54(&self) -> ND54_R { + ND54_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - New Data 55"] + #[inline(always)] + pub fn nd55(&self) -> ND55_R { + ND55_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24 - New Data 56"] + #[inline(always)] + pub fn nd56(&self) -> ND56_R { + ND56_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - New Data 57"] + #[inline(always)] + pub fn nd57(&self) -> ND57_R { + ND57_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - New Data 58"] + #[inline(always)] + pub fn nd58(&self) -> ND58_R { + ND58_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - New Data 59"] + #[inline(always)] + pub fn nd59(&self) -> ND59_R { + ND59_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28 - New Data 60"] + #[inline(always)] + pub fn nd60(&self) -> ND60_R { + ND60_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - New Data 61"] + #[inline(always)] + pub fn nd61(&self) -> ND61_R { + ND61_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - New Data 62"] + #[inline(always)] + pub fn nd62(&self) -> ND62_R { + ND62_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 31 - New Data 63"] + #[inline(always)] + pub fn nd63(&self) -> ND63_R { + ND63_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - New Data 32"] + #[inline(always)] + pub fn nd32(&mut self) -> ND32_W { + ND32_W { w: self } + } + #[doc = "Bit 1 - New Data 33"] + #[inline(always)] + pub fn nd33(&mut self) -> ND33_W { + ND33_W { w: self } + } + #[doc = "Bit 2 - New Data 34"] + #[inline(always)] + pub fn nd34(&mut self) -> ND34_W { + ND34_W { w: self } + } + #[doc = "Bit 3 - New Data 35"] + #[inline(always)] + pub fn nd35(&mut self) -> ND35_W { + ND35_W { w: self } + } + #[doc = "Bit 4 - New Data 36"] + #[inline(always)] + pub fn nd36(&mut self) -> ND36_W { + ND36_W { w: self } + } + #[doc = "Bit 5 - New Data 37"] + #[inline(always)] + pub fn nd37(&mut self) -> ND37_W { + ND37_W { w: self } + } + #[doc = "Bit 6 - New Data 38"] + #[inline(always)] + pub fn nd38(&mut self) -> ND38_W { + ND38_W { w: self } + } + #[doc = "Bit 7 - New Data 39"] + #[inline(always)] + pub fn nd39(&mut self) -> ND39_W { + ND39_W { w: self } + } + #[doc = "Bit 8 - New Data 40"] + #[inline(always)] + pub fn nd40(&mut self) -> ND40_W { + ND40_W { w: self } + } + #[doc = "Bit 9 - New Data 41"] + #[inline(always)] + pub fn nd41(&mut self) -> ND41_W { + ND41_W { w: self } + } + #[doc = "Bit 10 - New Data 42"] + #[inline(always)] + pub fn nd42(&mut self) -> ND42_W { + ND42_W { w: self } + } + #[doc = "Bit 11 - New Data 43"] + #[inline(always)] + pub fn nd43(&mut self) -> ND43_W { + ND43_W { w: self } + } + #[doc = "Bit 12 - New Data 44"] + #[inline(always)] + pub fn nd44(&mut self) -> ND44_W { + ND44_W { w: self } + } + #[doc = "Bit 13 - New Data 45"] + #[inline(always)] + pub fn nd45(&mut self) -> ND45_W { + ND45_W { w: self } + } + #[doc = "Bit 14 - New Data 46"] + #[inline(always)] + pub fn nd46(&mut self) -> ND46_W { + ND46_W { w: self } + } + #[doc = "Bit 15 - New Data 47"] + #[inline(always)] + pub fn nd47(&mut self) -> ND47_W { + ND47_W { w: self } + } + #[doc = "Bit 16 - New Data 48"] + #[inline(always)] + pub fn nd48(&mut self) -> ND48_W { + ND48_W { w: self } + } + #[doc = "Bit 17 - New Data 49"] + #[inline(always)] + pub fn nd49(&mut self) -> ND49_W { + ND49_W { w: self } + } + #[doc = "Bit 18 - New Data 50"] + #[inline(always)] + pub fn nd50(&mut self) -> ND50_W { + ND50_W { w: self } + } + #[doc = "Bit 19 - New Data 51"] + #[inline(always)] + pub fn nd51(&mut self) -> ND51_W { + ND51_W { w: self } + } + #[doc = "Bit 20 - New Data 52"] + #[inline(always)] + pub fn nd52(&mut self) -> ND52_W { + ND52_W { w: self } + } + #[doc = "Bit 21 - New Data 53"] + #[inline(always)] + pub fn nd53(&mut self) -> ND53_W { + ND53_W { w: self } + } + #[doc = "Bit 22 - New Data 54"] + #[inline(always)] + pub fn nd54(&mut self) -> ND54_W { + ND54_W { w: self } + } + #[doc = "Bit 23 - New Data 55"] + #[inline(always)] + pub fn nd55(&mut self) -> ND55_W { + ND55_W { w: self } + } + #[doc = "Bit 24 - New Data 56"] + #[inline(always)] + pub fn nd56(&mut self) -> ND56_W { + ND56_W { w: self } + } + #[doc = "Bit 25 - New Data 57"] + #[inline(always)] + pub fn nd57(&mut self) -> ND57_W { + ND57_W { w: self } + } + #[doc = "Bit 26 - New Data 58"] + #[inline(always)] + pub fn nd58(&mut self) -> ND58_W { + ND58_W { w: self } + } + #[doc = "Bit 27 - New Data 59"] + #[inline(always)] + pub fn nd59(&mut self) -> ND59_W { + ND59_W { w: self } + } + #[doc = "Bit 28 - New Data 60"] + #[inline(always)] + pub fn nd60(&mut self) -> ND60_W { + ND60_W { w: self } + } + #[doc = "Bit 29 - New Data 61"] + #[inline(always)] + pub fn nd61(&mut self) -> ND61_W { + ND61_W { w: self } + } + #[doc = "Bit 30 - New Data 62"] + #[inline(always)] + pub fn nd62(&mut self) -> ND62_W { + ND62_W { w: self } + } + #[doc = "Bit 31 - New Data 63"] + #[inline(always)] + pub fn nd63(&mut self) -> ND63_W { + ND63_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "New Data 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ndat2](index.html) module"] +pub struct NDAT2_SPEC; +impl crate::RegisterSpec for NDAT2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ndat2::R](R) reader structure"] +impl crate::Readable for NDAT2_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ndat2::W](W) writer structure"] +impl crate::Writable for NDAT2_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets NDAT2 to value 0"] +impl crate::Resettable for NDAT2_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/can0/psr.rs b/pac/atsamc21g/src/can0/psr.rs new file mode 100644 index 000000000000..0b5f73b9413b --- /dev/null +++ b/pac/atsamc21g/src/can0/psr.rs @@ -0,0 +1,467 @@ +#[doc = "Register `PSR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Last Error Code\n\nValue on reset: 7"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum LEC_A { + #[doc = "0: No Error"] + NONE = 0, + #[doc = "1: Stuff Error"] + STUFF = 1, + #[doc = "2: Form Error"] + FORM = 2, + #[doc = "3: Ack Error"] + ACK = 3, + #[doc = "4: Bit1 Error"] + BIT1 = 4, + #[doc = "5: Bit0 Error"] + BIT0 = 5, + #[doc = "6: CRC Error"] + CRC = 6, + #[doc = "7: No Change"] + NC = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LEC_A) -> Self { + variant as _ + } +} +#[doc = "Field `LEC` reader - Last Error Code"] +pub struct LEC_R(crate::FieldReader); +impl LEC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LEC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> LEC_A { + match self.bits { + 0 => LEC_A::NONE, + 1 => LEC_A::STUFF, + 2 => LEC_A::FORM, + 3 => LEC_A::ACK, + 4 => LEC_A::BIT1, + 5 => LEC_A::BIT0, + 6 => LEC_A::CRC, + 7 => LEC_A::NC, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == LEC_A::NONE + } + #[doc = "Checks if the value of the field is `STUFF`"] + #[inline(always)] + pub fn is_stuff(&self) -> bool { + **self == LEC_A::STUFF + } + #[doc = "Checks if the value of the field is `FORM`"] + #[inline(always)] + pub fn is_form(&self) -> bool { + **self == LEC_A::FORM + } + #[doc = "Checks if the value of the field is `ACK`"] + #[inline(always)] + pub fn is_ack(&self) -> bool { + **self == LEC_A::ACK + } + #[doc = "Checks if the value of the field is `BIT1`"] + #[inline(always)] + pub fn is_bit1(&self) -> bool { + **self == LEC_A::BIT1 + } + #[doc = "Checks if the value of the field is `BIT0`"] + #[inline(always)] + pub fn is_bit0(&self) -> bool { + **self == LEC_A::BIT0 + } + #[doc = "Checks if the value of the field is `CRC`"] + #[inline(always)] + pub fn is_crc(&self) -> bool { + **self == LEC_A::CRC + } + #[doc = "Checks if the value of the field is `NC`"] + #[inline(always)] + pub fn is_nc(&self) -> bool { + **self == LEC_A::NC + } +} +impl core::ops::Deref for LEC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Activity\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum ACT_A { + #[doc = "0: Node is synchronizing on CAN communication"] + SYNC = 0, + #[doc = "1: Node is neither receiver nor transmitter"] + IDLE = 1, + #[doc = "2: Node is operating as receiver"] + RX = 2, + #[doc = "3: Node is operating as transmitter"] + TX = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: ACT_A) -> Self { + variant as _ + } +} +#[doc = "Field `ACT` reader - Activity"] +pub struct ACT_R(crate::FieldReader); +impl ACT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ACT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ACT_A { + match self.bits { + 0 => ACT_A::SYNC, + 1 => ACT_A::IDLE, + 2 => ACT_A::RX, + 3 => ACT_A::TX, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `SYNC`"] + #[inline(always)] + pub fn is_sync(&self) -> bool { + **self == ACT_A::SYNC + } + #[doc = "Checks if the value of the field is `IDLE`"] + #[inline(always)] + pub fn is_idle(&self) -> bool { + **self == ACT_A::IDLE + } + #[doc = "Checks if the value of the field is `RX`"] + #[inline(always)] + pub fn is_rx(&self) -> bool { + **self == ACT_A::RX + } + #[doc = "Checks if the value of the field is `TX`"] + #[inline(always)] + pub fn is_tx(&self) -> bool { + **self == ACT_A::TX + } +} +impl core::ops::Deref for ACT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EP` reader - Error Passive"] +pub struct EP_R(crate::FieldReader); +impl EP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EW` reader - Warning Status"] +pub struct EW_R(crate::FieldReader); +impl EW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BO` reader - Bus_Off Status"] +pub struct BO_R(crate::FieldReader); +impl BO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Data Phase Last Error Code\n\nValue on reset: 7"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DLEC_A { + #[doc = "0: No Error"] + NONE = 0, + #[doc = "1: Stuff Error"] + STUFF = 1, + #[doc = "2: Form Error"] + FORM = 2, + #[doc = "3: Ack Error"] + ACK = 3, + #[doc = "4: Bit1 Error"] + BIT1 = 4, + #[doc = "5: Bit0 Error"] + BIT0 = 5, + #[doc = "6: CRC Error"] + CRC = 6, + #[doc = "7: No Change"] + NC = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DLEC_A) -> Self { + variant as _ + } +} +#[doc = "Field `DLEC` reader - Data Phase Last Error Code"] +pub struct DLEC_R(crate::FieldReader); +impl DLEC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DLEC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DLEC_A { + match self.bits { + 0 => DLEC_A::NONE, + 1 => DLEC_A::STUFF, + 2 => DLEC_A::FORM, + 3 => DLEC_A::ACK, + 4 => DLEC_A::BIT1, + 5 => DLEC_A::BIT0, + 6 => DLEC_A::CRC, + 7 => DLEC_A::NC, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == DLEC_A::NONE + } + #[doc = "Checks if the value of the field is `STUFF`"] + #[inline(always)] + pub fn is_stuff(&self) -> bool { + **self == DLEC_A::STUFF + } + #[doc = "Checks if the value of the field is `FORM`"] + #[inline(always)] + pub fn is_form(&self) -> bool { + **self == DLEC_A::FORM + } + #[doc = "Checks if the value of the field is `ACK`"] + #[inline(always)] + pub fn is_ack(&self) -> bool { + **self == DLEC_A::ACK + } + #[doc = "Checks if the value of the field is `BIT1`"] + #[inline(always)] + pub fn is_bit1(&self) -> bool { + **self == DLEC_A::BIT1 + } + #[doc = "Checks if the value of the field is `BIT0`"] + #[inline(always)] + pub fn is_bit0(&self) -> bool { + **self == DLEC_A::BIT0 + } + #[doc = "Checks if the value of the field is `CRC`"] + #[inline(always)] + pub fn is_crc(&self) -> bool { + **self == DLEC_A::CRC + } + #[doc = "Checks if the value of the field is `NC`"] + #[inline(always)] + pub fn is_nc(&self) -> bool { + **self == DLEC_A::NC + } +} +impl core::ops::Deref for DLEC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESI` reader - ESI flag of last received CAN FD Message"] +pub struct RESI_R(crate::FieldReader); +impl RESI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RBRS` reader - BRS flag of last received CAN FD Message"] +pub struct RBRS_R(crate::FieldReader); +impl RBRS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RBRS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RBRS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RFDF` reader - Received a CAN FD Message"] +pub struct RFDF_R(crate::FieldReader); +impl RFDF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RFDF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RFDF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PXE` reader - Protocol Exception Event"] +pub struct PXE_R(crate::FieldReader); +impl PXE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PXE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PXE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TDCV` reader - Transmitter Delay Compensation Value"] +pub struct TDCV_R(crate::FieldReader); +impl TDCV_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TDCV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TDCV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:2 - Last Error Code"] + #[inline(always)] + pub fn lec(&self) -> LEC_R { + LEC_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bits 3:4 - Activity"] + #[inline(always)] + pub fn act(&self) -> ACT_R { + ACT_R::new(((self.bits >> 3) & 0x03) as u8) + } + #[doc = "Bit 5 - Error Passive"] + #[inline(always)] + pub fn ep(&self) -> EP_R { + EP_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Warning Status"] + #[inline(always)] + pub fn ew(&self) -> EW_R { + EW_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Bus_Off Status"] + #[inline(always)] + pub fn bo(&self) -> BO_R { + BO_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Data Phase Last Error Code"] + #[inline(always)] + pub fn dlec(&self) -> DLEC_R { + DLEC_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 11 - ESI flag of last received CAN FD Message"] + #[inline(always)] + pub fn resi(&self) -> RESI_R { + RESI_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - BRS flag of last received CAN FD Message"] + #[inline(always)] + pub fn rbrs(&self) -> RBRS_R { + RBRS_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Received a CAN FD Message"] + #[inline(always)] + pub fn rfdf(&self) -> RFDF_R { + RFDF_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Protocol Exception Event"] + #[inline(always)] + pub fn pxe(&self) -> PXE_R { + PXE_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bits 16:22 - Transmitter Delay Compensation Value"] + #[inline(always)] + pub fn tdcv(&self) -> TDCV_R { + TDCV_R::new(((self.bits >> 16) & 0x7f) as u8) + } +} +#[doc = "Protocol Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [psr](index.html) module"] +pub struct PSR_SPEC; +impl crate::RegisterSpec for PSR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [psr::R](R) reader structure"] +impl crate::Readable for PSR_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PSR to value 0x0707"] +impl crate::Resettable for PSR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0707 + } +} diff --git a/pac/atsamc21g/src/can0/rwd.rs b/pac/atsamc21g/src/can0/rwd.rs new file mode 100644 index 000000000000..88f5b86a33f2 --- /dev/null +++ b/pac/atsamc21g/src/can0/rwd.rs @@ -0,0 +1,140 @@ +#[doc = "Register `RWD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RWD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WDC` reader - Watchdog Configuration"] +pub struct WDC_R(crate::FieldReader); +impl WDC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WDC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WDC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WDC` writer - Watchdog Configuration"] +pub struct WDC_W<'a> { + w: &'a mut W, +} +impl<'a> WDC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +#[doc = "Field `WDV` reader - Watchdog Value"] +pub struct WDV_R(crate::FieldReader); +impl WDV_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WDV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WDV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WDV` writer - Watchdog Value"] +pub struct WDV_W<'a> { + w: &'a mut W, +} +impl<'a> WDV_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Watchdog Configuration"] + #[inline(always)] + pub fn wdc(&self) -> WDC_R { + WDC_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Watchdog Value"] + #[inline(always)] + pub fn wdv(&self) -> WDV_R { + WDV_R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Watchdog Configuration"] + #[inline(always)] + pub fn wdc(&mut self) -> WDC_W { + WDC_W { w: self } + } + #[doc = "Bits 8:15 - Watchdog Value"] + #[inline(always)] + pub fn wdv(&mut self) -> WDV_W { + WDV_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "RAM Watchdog\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rwd](index.html) module"] +pub struct RWD_SPEC; +impl crate::RegisterSpec for RWD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rwd::R](R) reader structure"] +impl crate::Readable for RWD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rwd::W](W) writer structure"] +impl crate::Writable for RWD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RWD to value 0"] +impl crate::Resettable for RWD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/can0/rxbc.rs b/pac/atsamc21g/src/can0/rxbc.rs new file mode 100644 index 000000000000..d320ea61f4c2 --- /dev/null +++ b/pac/atsamc21g/src/can0/rxbc.rs @@ -0,0 +1,103 @@ +#[doc = "Register `RXBC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RXBC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RBSA` reader - Rx Buffer Start Address"] +pub struct RBSA_R(crate::FieldReader); +impl RBSA_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + RBSA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RBSA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RBSA` writer - Rx Buffer Start Address"] +pub struct RBSA_W<'a> { + w: &'a mut W, +} +impl<'a> RBSA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Rx Buffer Start Address"] + #[inline(always)] + pub fn rbsa(&self) -> RBSA_R { + RBSA_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Rx Buffer Start Address"] + #[inline(always)] + pub fn rbsa(&mut self) -> RBSA_W { + RBSA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Rx Buffer Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxbc](index.html) module"] +pub struct RXBC_SPEC; +impl crate::RegisterSpec for RXBC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rxbc::R](R) reader structure"] +impl crate::Readable for RXBC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rxbc::W](W) writer structure"] +impl crate::Writable for RXBC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RXBC to value 0"] +impl crate::Resettable for RXBC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/can0/rxesc.rs b/pac/atsamc21g/src/can0/rxesc.rs new file mode 100644 index 000000000000..b0a972eaf1f0 --- /dev/null +++ b/pac/atsamc21g/src/can0/rxesc.rs @@ -0,0 +1,558 @@ +#[doc = "Register `RXESC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RXESC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Rx FIFO 0 Data Field Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum F0DS_A { + #[doc = "0: 8 byte data field"] + DATA8 = 0, + #[doc = "1: 12 byte data field"] + DATA12 = 1, + #[doc = "2: 16 byte data field"] + DATA16 = 2, + #[doc = "3: 20 byte data field"] + DATA20 = 3, + #[doc = "4: 24 byte data field"] + DATA24 = 4, + #[doc = "5: 32 byte data field"] + DATA32 = 5, + #[doc = "6: 48 byte data field"] + DATA48 = 6, + #[doc = "7: 64 byte data field"] + DATA64 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: F0DS_A) -> Self { + variant as _ + } +} +#[doc = "Field `F0DS` reader - Rx FIFO 0 Data Field Size"] +pub struct F0DS_R(crate::FieldReader); +impl F0DS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + F0DS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> F0DS_A { + match self.bits { + 0 => F0DS_A::DATA8, + 1 => F0DS_A::DATA12, + 2 => F0DS_A::DATA16, + 3 => F0DS_A::DATA20, + 4 => F0DS_A::DATA24, + 5 => F0DS_A::DATA32, + 6 => F0DS_A::DATA48, + 7 => F0DS_A::DATA64, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DATA8`"] + #[inline(always)] + pub fn is_data8(&self) -> bool { + **self == F0DS_A::DATA8 + } + #[doc = "Checks if the value of the field is `DATA12`"] + #[inline(always)] + pub fn is_data12(&self) -> bool { + **self == F0DS_A::DATA12 + } + #[doc = "Checks if the value of the field is `DATA16`"] + #[inline(always)] + pub fn is_data16(&self) -> bool { + **self == F0DS_A::DATA16 + } + #[doc = "Checks if the value of the field is `DATA20`"] + #[inline(always)] + pub fn is_data20(&self) -> bool { + **self == F0DS_A::DATA20 + } + #[doc = "Checks if the value of the field is `DATA24`"] + #[inline(always)] + pub fn is_data24(&self) -> bool { + **self == F0DS_A::DATA24 + } + #[doc = "Checks if the value of the field is `DATA32`"] + #[inline(always)] + pub fn is_data32(&self) -> bool { + **self == F0DS_A::DATA32 + } + #[doc = "Checks if the value of the field is `DATA48`"] + #[inline(always)] + pub fn is_data48(&self) -> bool { + **self == F0DS_A::DATA48 + } + #[doc = "Checks if the value of the field is `DATA64`"] + #[inline(always)] + pub fn is_data64(&self) -> bool { + **self == F0DS_A::DATA64 + } +} +impl core::ops::Deref for F0DS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `F0DS` writer - Rx FIFO 0 Data Field Size"] +pub struct F0DS_W<'a> { + w: &'a mut W, +} +impl<'a> F0DS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: F0DS_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "8 byte data field"] + #[inline(always)] + pub fn data8(self) -> &'a mut W { + self.variant(F0DS_A::DATA8) + } + #[doc = "12 byte data field"] + #[inline(always)] + pub fn data12(self) -> &'a mut W { + self.variant(F0DS_A::DATA12) + } + #[doc = "16 byte data field"] + #[inline(always)] + pub fn data16(self) -> &'a mut W { + self.variant(F0DS_A::DATA16) + } + #[doc = "20 byte data field"] + #[inline(always)] + pub fn data20(self) -> &'a mut W { + self.variant(F0DS_A::DATA20) + } + #[doc = "24 byte data field"] + #[inline(always)] + pub fn data24(self) -> &'a mut W { + self.variant(F0DS_A::DATA24) + } + #[doc = "32 byte data field"] + #[inline(always)] + pub fn data32(self) -> &'a mut W { + self.variant(F0DS_A::DATA32) + } + #[doc = "48 byte data field"] + #[inline(always)] + pub fn data48(self) -> &'a mut W { + self.variant(F0DS_A::DATA48) + } + #[doc = "64 byte data field"] + #[inline(always)] + pub fn data64(self) -> &'a mut W { + self.variant(F0DS_A::DATA64) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Rx FIFO 1 Data Field Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum F1DS_A { + #[doc = "0: 8 byte data field"] + DATA8 = 0, + #[doc = "1: 12 byte data field"] + DATA12 = 1, + #[doc = "2: 16 byte data field"] + DATA16 = 2, + #[doc = "3: 20 byte data field"] + DATA20 = 3, + #[doc = "4: 24 byte data field"] + DATA24 = 4, + #[doc = "5: 32 byte data field"] + DATA32 = 5, + #[doc = "6: 48 byte data field"] + DATA48 = 6, + #[doc = "7: 64 byte data field"] + DATA64 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: F1DS_A) -> Self { + variant as _ + } +} +#[doc = "Field `F1DS` reader - Rx FIFO 1 Data Field Size"] +pub struct F1DS_R(crate::FieldReader); +impl F1DS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + F1DS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> F1DS_A { + match self.bits { + 0 => F1DS_A::DATA8, + 1 => F1DS_A::DATA12, + 2 => F1DS_A::DATA16, + 3 => F1DS_A::DATA20, + 4 => F1DS_A::DATA24, + 5 => F1DS_A::DATA32, + 6 => F1DS_A::DATA48, + 7 => F1DS_A::DATA64, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DATA8`"] + #[inline(always)] + pub fn is_data8(&self) -> bool { + **self == F1DS_A::DATA8 + } + #[doc = "Checks if the value of the field is `DATA12`"] + #[inline(always)] + pub fn is_data12(&self) -> bool { + **self == F1DS_A::DATA12 + } + #[doc = "Checks if the value of the field is `DATA16`"] + #[inline(always)] + pub fn is_data16(&self) -> bool { + **self == F1DS_A::DATA16 + } + #[doc = "Checks if the value of the field is `DATA20`"] + #[inline(always)] + pub fn is_data20(&self) -> bool { + **self == F1DS_A::DATA20 + } + #[doc = "Checks if the value of the field is `DATA24`"] + #[inline(always)] + pub fn is_data24(&self) -> bool { + **self == F1DS_A::DATA24 + } + #[doc = "Checks if the value of the field is `DATA32`"] + #[inline(always)] + pub fn is_data32(&self) -> bool { + **self == F1DS_A::DATA32 + } + #[doc = "Checks if the value of the field is `DATA48`"] + #[inline(always)] + pub fn is_data48(&self) -> bool { + **self == F1DS_A::DATA48 + } + #[doc = "Checks if the value of the field is `DATA64`"] + #[inline(always)] + pub fn is_data64(&self) -> bool { + **self == F1DS_A::DATA64 + } +} +impl core::ops::Deref for F1DS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `F1DS` writer - Rx FIFO 1 Data Field Size"] +pub struct F1DS_W<'a> { + w: &'a mut W, +} +impl<'a> F1DS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: F1DS_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "8 byte data field"] + #[inline(always)] + pub fn data8(self) -> &'a mut W { + self.variant(F1DS_A::DATA8) + } + #[doc = "12 byte data field"] + #[inline(always)] + pub fn data12(self) -> &'a mut W { + self.variant(F1DS_A::DATA12) + } + #[doc = "16 byte data field"] + #[inline(always)] + pub fn data16(self) -> &'a mut W { + self.variant(F1DS_A::DATA16) + } + #[doc = "20 byte data field"] + #[inline(always)] + pub fn data20(self) -> &'a mut W { + self.variant(F1DS_A::DATA20) + } + #[doc = "24 byte data field"] + #[inline(always)] + pub fn data24(self) -> &'a mut W { + self.variant(F1DS_A::DATA24) + } + #[doc = "32 byte data field"] + #[inline(always)] + pub fn data32(self) -> &'a mut W { + self.variant(F1DS_A::DATA32) + } + #[doc = "48 byte data field"] + #[inline(always)] + pub fn data48(self) -> &'a mut W { + self.variant(F1DS_A::DATA48) + } + #[doc = "64 byte data field"] + #[inline(always)] + pub fn data64(self) -> &'a mut W { + self.variant(F1DS_A::DATA64) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 4)) | ((value as u32 & 0x07) << 4); + self.w + } +} +#[doc = "Rx Buffer Data Field Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum RBDS_A { + #[doc = "0: 8 byte data field"] + DATA8 = 0, + #[doc = "1: 12 byte data field"] + DATA12 = 1, + #[doc = "2: 16 byte data field"] + DATA16 = 2, + #[doc = "3: 20 byte data field"] + DATA20 = 3, + #[doc = "4: 24 byte data field"] + DATA24 = 4, + #[doc = "5: 32 byte data field"] + DATA32 = 5, + #[doc = "6: 48 byte data field"] + DATA48 = 6, + #[doc = "7: 64 byte data field"] + DATA64 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RBDS_A) -> Self { + variant as _ + } +} +#[doc = "Field `RBDS` reader - Rx Buffer Data Field Size"] +pub struct RBDS_R(crate::FieldReader); +impl RBDS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RBDS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RBDS_A { + match self.bits { + 0 => RBDS_A::DATA8, + 1 => RBDS_A::DATA12, + 2 => RBDS_A::DATA16, + 3 => RBDS_A::DATA20, + 4 => RBDS_A::DATA24, + 5 => RBDS_A::DATA32, + 6 => RBDS_A::DATA48, + 7 => RBDS_A::DATA64, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DATA8`"] + #[inline(always)] + pub fn is_data8(&self) -> bool { + **self == RBDS_A::DATA8 + } + #[doc = "Checks if the value of the field is `DATA12`"] + #[inline(always)] + pub fn is_data12(&self) -> bool { + **self == RBDS_A::DATA12 + } + #[doc = "Checks if the value of the field is `DATA16`"] + #[inline(always)] + pub fn is_data16(&self) -> bool { + **self == RBDS_A::DATA16 + } + #[doc = "Checks if the value of the field is `DATA20`"] + #[inline(always)] + pub fn is_data20(&self) -> bool { + **self == RBDS_A::DATA20 + } + #[doc = "Checks if the value of the field is `DATA24`"] + #[inline(always)] + pub fn is_data24(&self) -> bool { + **self == RBDS_A::DATA24 + } + #[doc = "Checks if the value of the field is `DATA32`"] + #[inline(always)] + pub fn is_data32(&self) -> bool { + **self == RBDS_A::DATA32 + } + #[doc = "Checks if the value of the field is `DATA48`"] + #[inline(always)] + pub fn is_data48(&self) -> bool { + **self == RBDS_A::DATA48 + } + #[doc = "Checks if the value of the field is `DATA64`"] + #[inline(always)] + pub fn is_data64(&self) -> bool { + **self == RBDS_A::DATA64 + } +} +impl core::ops::Deref for RBDS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RBDS` writer - Rx Buffer Data Field Size"] +pub struct RBDS_W<'a> { + w: &'a mut W, +} +impl<'a> RBDS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RBDS_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "8 byte data field"] + #[inline(always)] + pub fn data8(self) -> &'a mut W { + self.variant(RBDS_A::DATA8) + } + #[doc = "12 byte data field"] + #[inline(always)] + pub fn data12(self) -> &'a mut W { + self.variant(RBDS_A::DATA12) + } + #[doc = "16 byte data field"] + #[inline(always)] + pub fn data16(self) -> &'a mut W { + self.variant(RBDS_A::DATA16) + } + #[doc = "20 byte data field"] + #[inline(always)] + pub fn data20(self) -> &'a mut W { + self.variant(RBDS_A::DATA20) + } + #[doc = "24 byte data field"] + #[inline(always)] + pub fn data24(self) -> &'a mut W { + self.variant(RBDS_A::DATA24) + } + #[doc = "32 byte data field"] + #[inline(always)] + pub fn data32(self) -> &'a mut W { + self.variant(RBDS_A::DATA32) + } + #[doc = "48 byte data field"] + #[inline(always)] + pub fn data48(self) -> &'a mut W { + self.variant(RBDS_A::DATA48) + } + #[doc = "64 byte data field"] + #[inline(always)] + pub fn data64(self) -> &'a mut W { + self.variant(RBDS_A::DATA64) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Rx FIFO 0 Data Field Size"] + #[inline(always)] + pub fn f0ds(&self) -> F0DS_R { + F0DS_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bits 4:6 - Rx FIFO 1 Data Field Size"] + #[inline(always)] + pub fn f1ds(&self) -> F1DS_R { + F1DS_R::new(((self.bits >> 4) & 0x07) as u8) + } + #[doc = "Bits 8:10 - Rx Buffer Data Field Size"] + #[inline(always)] + pub fn rbds(&self) -> RBDS_R { + RBDS_R::new(((self.bits >> 8) & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Rx FIFO 0 Data Field Size"] + #[inline(always)] + pub fn f0ds(&mut self) -> F0DS_W { + F0DS_W { w: self } + } + #[doc = "Bits 4:6 - Rx FIFO 1 Data Field Size"] + #[inline(always)] + pub fn f1ds(&mut self) -> F1DS_W { + F1DS_W { w: self } + } + #[doc = "Bits 8:10 - Rx Buffer Data Field Size"] + #[inline(always)] + pub fn rbds(&mut self) -> RBDS_W { + RBDS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Rx Buffer / FIFO Element Size Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxesc](index.html) module"] +pub struct RXESC_SPEC; +impl crate::RegisterSpec for RXESC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rxesc::R](R) reader structure"] +impl crate::Readable for RXESC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rxesc::W](W) writer structure"] +impl crate::Writable for RXESC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RXESC to value 0"] +impl crate::Resettable for RXESC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/can0/rxf0a.rs b/pac/atsamc21g/src/can0/rxf0a.rs new file mode 100644 index 000000000000..568144edf95d --- /dev/null +++ b/pac/atsamc21g/src/can0/rxf0a.rs @@ -0,0 +1,103 @@ +#[doc = "Register `RXF0A` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RXF0A` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `F0AI` reader - Rx FIFO 0 Acknowledge Index"] +pub struct F0AI_R(crate::FieldReader); +impl F0AI_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + F0AI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for F0AI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `F0AI` writer - Rx FIFO 0 Acknowledge Index"] +pub struct F0AI_W<'a> { + w: &'a mut W, +} +impl<'a> F0AI_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Rx FIFO 0 Acknowledge Index"] + #[inline(always)] + pub fn f0ai(&self) -> F0AI_R { + F0AI_R::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - Rx FIFO 0 Acknowledge Index"] + #[inline(always)] + pub fn f0ai(&mut self) -> F0AI_W { + F0AI_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Rx FIFO 0 Acknowledge\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxf0a](index.html) module"] +pub struct RXF0A_SPEC; +impl crate::RegisterSpec for RXF0A_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rxf0a::R](R) reader structure"] +impl crate::Readable for RXF0A_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rxf0a::W](W) writer structure"] +impl crate::Writable for RXF0A_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RXF0A to value 0"] +impl crate::Resettable for RXF0A_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/can0/rxf0c.rs b/pac/atsamc21g/src/can0/rxf0c.rs new file mode 100644 index 000000000000..a1e1def5881a --- /dev/null +++ b/pac/atsamc21g/src/can0/rxf0c.rs @@ -0,0 +1,224 @@ +#[doc = "Register `RXF0C` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RXF0C` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `F0SA` reader - Rx FIFO 0 Start Address"] +pub struct F0SA_R(crate::FieldReader); +impl F0SA_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + F0SA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for F0SA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `F0SA` writer - Rx FIFO 0 Start Address"] +pub struct F0SA_W<'a> { + w: &'a mut W, +} +impl<'a> F0SA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +#[doc = "Field `F0S` reader - Rx FIFO 0 Size"] +pub struct F0S_R(crate::FieldReader); +impl F0S_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + F0S_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for F0S_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `F0S` writer - Rx FIFO 0 Size"] +pub struct F0S_W<'a> { + w: &'a mut W, +} +impl<'a> F0S_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x7f << 16)) | ((value as u32 & 0x7f) << 16); + self.w + } +} +#[doc = "Field `F0WM` reader - Rx FIFO 0 Watermark"] +pub struct F0WM_R(crate::FieldReader); +impl F0WM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + F0WM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for F0WM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `F0WM` writer - Rx FIFO 0 Watermark"] +pub struct F0WM_W<'a> { + w: &'a mut W, +} +impl<'a> F0WM_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x7f << 24)) | ((value as u32 & 0x7f) << 24); + self.w + } +} +#[doc = "Field `F0OM` reader - FIFO 0 Operation Mode"] +pub struct F0OM_R(crate::FieldReader); +impl F0OM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + F0OM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for F0OM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `F0OM` writer - FIFO 0 Operation Mode"] +pub struct F0OM_W<'a> { + w: &'a mut W, +} +impl<'a> F0OM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Rx FIFO 0 Start Address"] + #[inline(always)] + pub fn f0sa(&self) -> F0SA_R { + F0SA_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:22 - Rx FIFO 0 Size"] + #[inline(always)] + pub fn f0s(&self) -> F0S_R { + F0S_R::new(((self.bits >> 16) & 0x7f) as u8) + } + #[doc = "Bits 24:30 - Rx FIFO 0 Watermark"] + #[inline(always)] + pub fn f0wm(&self) -> F0WM_R { + F0WM_R::new(((self.bits >> 24) & 0x7f) as u8) + } + #[doc = "Bit 31 - FIFO 0 Operation Mode"] + #[inline(always)] + pub fn f0om(&self) -> F0OM_R { + F0OM_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Rx FIFO 0 Start Address"] + #[inline(always)] + pub fn f0sa(&mut self) -> F0SA_W { + F0SA_W { w: self } + } + #[doc = "Bits 16:22 - Rx FIFO 0 Size"] + #[inline(always)] + pub fn f0s(&mut self) -> F0S_W { + F0S_W { w: self } + } + #[doc = "Bits 24:30 - Rx FIFO 0 Watermark"] + #[inline(always)] + pub fn f0wm(&mut self) -> F0WM_W { + F0WM_W { w: self } + } + #[doc = "Bit 31 - FIFO 0 Operation Mode"] + #[inline(always)] + pub fn f0om(&mut self) -> F0OM_W { + F0OM_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Rx FIFO 0 Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxf0c](index.html) module"] +pub struct RXF0C_SPEC; +impl crate::RegisterSpec for RXF0C_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rxf0c::R](R) reader structure"] +impl crate::Readable for RXF0C_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rxf0c::W](W) writer structure"] +impl crate::Writable for RXF0C_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RXF0C to value 0"] +impl crate::Resettable for RXF0C_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/can0/rxf0s.rs b/pac/atsamc21g/src/can0/rxf0s.rs new file mode 100644 index 000000000000..c26ef5fed347 --- /dev/null +++ b/pac/atsamc21g/src/can0/rxf0s.rs @@ -0,0 +1,133 @@ +#[doc = "Register `RXF0S` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `F0FL` reader - Rx FIFO 0 Fill Level"] +pub struct F0FL_R(crate::FieldReader); +impl F0FL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + F0FL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for F0FL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `F0GI` reader - Rx FIFO 0 Get Index"] +pub struct F0GI_R(crate::FieldReader); +impl F0GI_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + F0GI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for F0GI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `F0PI` reader - Rx FIFO 0 Put Index"] +pub struct F0PI_R(crate::FieldReader); +impl F0PI_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + F0PI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for F0PI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `F0F` reader - Rx FIFO 0 Full"] +pub struct F0F_R(crate::FieldReader); +impl F0F_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + F0F_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for F0F_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF0L` reader - Rx FIFO 0 Message Lost"] +pub struct RF0L_R(crate::FieldReader); +impl RF0L_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF0L_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF0L_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:6 - Rx FIFO 0 Fill Level"] + #[inline(always)] + pub fn f0fl(&self) -> F0FL_R { + F0FL_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bits 8:13 - Rx FIFO 0 Get Index"] + #[inline(always)] + pub fn f0gi(&self) -> F0GI_R { + F0GI_R::new(((self.bits >> 8) & 0x3f) as u8) + } + #[doc = "Bits 16:21 - Rx FIFO 0 Put Index"] + #[inline(always)] + pub fn f0pi(&self) -> F0PI_R { + F0PI_R::new(((self.bits >> 16) & 0x3f) as u8) + } + #[doc = "Bit 24 - Rx FIFO 0 Full"] + #[inline(always)] + pub fn f0f(&self) -> F0F_R { + F0F_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Rx FIFO 0 Message Lost"] + #[inline(always)] + pub fn rf0l(&self) -> RF0L_R { + RF0L_R::new(((self.bits >> 25) & 0x01) != 0) + } +} +#[doc = "Rx FIFO 0 Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxf0s](index.html) module"] +pub struct RXF0S_SPEC; +impl crate::RegisterSpec for RXF0S_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rxf0s::R](R) reader structure"] +impl crate::Readable for RXF0S_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets RXF0S to value 0"] +impl crate::Resettable for RXF0S_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/can0/rxf1a.rs b/pac/atsamc21g/src/can0/rxf1a.rs new file mode 100644 index 000000000000..56b074f7f444 --- /dev/null +++ b/pac/atsamc21g/src/can0/rxf1a.rs @@ -0,0 +1,103 @@ +#[doc = "Register `RXF1A` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RXF1A` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `F1AI` reader - Rx FIFO 1 Acknowledge Index"] +pub struct F1AI_R(crate::FieldReader); +impl F1AI_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + F1AI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for F1AI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `F1AI` writer - Rx FIFO 1 Acknowledge Index"] +pub struct F1AI_W<'a> { + w: &'a mut W, +} +impl<'a> F1AI_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Rx FIFO 1 Acknowledge Index"] + #[inline(always)] + pub fn f1ai(&self) -> F1AI_R { + F1AI_R::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - Rx FIFO 1 Acknowledge Index"] + #[inline(always)] + pub fn f1ai(&mut self) -> F1AI_W { + F1AI_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Rx FIFO 1 Acknowledge\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxf1a](index.html) module"] +pub struct RXF1A_SPEC; +impl crate::RegisterSpec for RXF1A_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rxf1a::R](R) reader structure"] +impl crate::Readable for RXF1A_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rxf1a::W](W) writer structure"] +impl crate::Writable for RXF1A_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RXF1A to value 0"] +impl crate::Resettable for RXF1A_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/can0/rxf1c.rs b/pac/atsamc21g/src/can0/rxf1c.rs new file mode 100644 index 000000000000..c9e23925c0c8 --- /dev/null +++ b/pac/atsamc21g/src/can0/rxf1c.rs @@ -0,0 +1,224 @@ +#[doc = "Register `RXF1C` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RXF1C` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `F1SA` reader - Rx FIFO 1 Start Address"] +pub struct F1SA_R(crate::FieldReader); +impl F1SA_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + F1SA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for F1SA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `F1SA` writer - Rx FIFO 1 Start Address"] +pub struct F1SA_W<'a> { + w: &'a mut W, +} +impl<'a> F1SA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +#[doc = "Field `F1S` reader - Rx FIFO 1 Size"] +pub struct F1S_R(crate::FieldReader); +impl F1S_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + F1S_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for F1S_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `F1S` writer - Rx FIFO 1 Size"] +pub struct F1S_W<'a> { + w: &'a mut W, +} +impl<'a> F1S_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x7f << 16)) | ((value as u32 & 0x7f) << 16); + self.w + } +} +#[doc = "Field `F1WM` reader - Rx FIFO 1 Watermark"] +pub struct F1WM_R(crate::FieldReader); +impl F1WM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + F1WM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for F1WM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `F1WM` writer - Rx FIFO 1 Watermark"] +pub struct F1WM_W<'a> { + w: &'a mut W, +} +impl<'a> F1WM_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x7f << 24)) | ((value as u32 & 0x7f) << 24); + self.w + } +} +#[doc = "Field `F1OM` reader - FIFO 1 Operation Mode"] +pub struct F1OM_R(crate::FieldReader); +impl F1OM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + F1OM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for F1OM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `F1OM` writer - FIFO 1 Operation Mode"] +pub struct F1OM_W<'a> { + w: &'a mut W, +} +impl<'a> F1OM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Rx FIFO 1 Start Address"] + #[inline(always)] + pub fn f1sa(&self) -> F1SA_R { + F1SA_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:22 - Rx FIFO 1 Size"] + #[inline(always)] + pub fn f1s(&self) -> F1S_R { + F1S_R::new(((self.bits >> 16) & 0x7f) as u8) + } + #[doc = "Bits 24:30 - Rx FIFO 1 Watermark"] + #[inline(always)] + pub fn f1wm(&self) -> F1WM_R { + F1WM_R::new(((self.bits >> 24) & 0x7f) as u8) + } + #[doc = "Bit 31 - FIFO 1 Operation Mode"] + #[inline(always)] + pub fn f1om(&self) -> F1OM_R { + F1OM_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Rx FIFO 1 Start Address"] + #[inline(always)] + pub fn f1sa(&mut self) -> F1SA_W { + F1SA_W { w: self } + } + #[doc = "Bits 16:22 - Rx FIFO 1 Size"] + #[inline(always)] + pub fn f1s(&mut self) -> F1S_W { + F1S_W { w: self } + } + #[doc = "Bits 24:30 - Rx FIFO 1 Watermark"] + #[inline(always)] + pub fn f1wm(&mut self) -> F1WM_W { + F1WM_W { w: self } + } + #[doc = "Bit 31 - FIFO 1 Operation Mode"] + #[inline(always)] + pub fn f1om(&mut self) -> F1OM_W { + F1OM_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Rx FIFO 1 Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxf1c](index.html) module"] +pub struct RXF1C_SPEC; +impl crate::RegisterSpec for RXF1C_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rxf1c::R](R) reader structure"] +impl crate::Readable for RXF1C_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rxf1c::W](W) writer structure"] +impl crate::Writable for RXF1C_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RXF1C to value 0"] +impl crate::Resettable for RXF1C_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/can0/rxf1s.rs b/pac/atsamc21g/src/can0/rxf1s.rs new file mode 100644 index 000000000000..7005a3339afb --- /dev/null +++ b/pac/atsamc21g/src/can0/rxf1s.rs @@ -0,0 +1,203 @@ +#[doc = "Register `RXF1S` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `F1FL` reader - Rx FIFO 1 Fill Level"] +pub struct F1FL_R(crate::FieldReader); +impl F1FL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + F1FL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for F1FL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `F1GI` reader - Rx FIFO 1 Get Index"] +pub struct F1GI_R(crate::FieldReader); +impl F1GI_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + F1GI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for F1GI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `F1PI` reader - Rx FIFO 1 Put Index"] +pub struct F1PI_R(crate::FieldReader); +impl F1PI_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + F1PI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for F1PI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `F1F` reader - Rx FIFO 1 Full"] +pub struct F1F_R(crate::FieldReader); +impl F1F_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + F1F_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for F1F_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF1L` reader - Rx FIFO 1 Message Lost"] +pub struct RF1L_R(crate::FieldReader); +impl RF1L_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF1L_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF1L_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Debug Message Status\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DMS_A { + #[doc = "0: Idle state"] + IDLE = 0, + #[doc = "1: Debug message A received"] + DBGA = 1, + #[doc = "2: Debug message A/B received"] + DBGB = 2, + #[doc = "3: Debug message A/B/C received, DMA request set"] + DBGC = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DMS_A) -> Self { + variant as _ + } +} +#[doc = "Field `DMS` reader - Debug Message Status"] +pub struct DMS_R(crate::FieldReader); +impl DMS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DMS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DMS_A { + match self.bits { + 0 => DMS_A::IDLE, + 1 => DMS_A::DBGA, + 2 => DMS_A::DBGB, + 3 => DMS_A::DBGC, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `IDLE`"] + #[inline(always)] + pub fn is_idle(&self) -> bool { + **self == DMS_A::IDLE + } + #[doc = "Checks if the value of the field is `DBGA`"] + #[inline(always)] + pub fn is_dbga(&self) -> bool { + **self == DMS_A::DBGA + } + #[doc = "Checks if the value of the field is `DBGB`"] + #[inline(always)] + pub fn is_dbgb(&self) -> bool { + **self == DMS_A::DBGB + } + #[doc = "Checks if the value of the field is `DBGC`"] + #[inline(always)] + pub fn is_dbgc(&self) -> bool { + **self == DMS_A::DBGC + } +} +impl core::ops::Deref for DMS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:6 - Rx FIFO 1 Fill Level"] + #[inline(always)] + pub fn f1fl(&self) -> F1FL_R { + F1FL_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bits 8:13 - Rx FIFO 1 Get Index"] + #[inline(always)] + pub fn f1gi(&self) -> F1GI_R { + F1GI_R::new(((self.bits >> 8) & 0x3f) as u8) + } + #[doc = "Bits 16:21 - Rx FIFO 1 Put Index"] + #[inline(always)] + pub fn f1pi(&self) -> F1PI_R { + F1PI_R::new(((self.bits >> 16) & 0x3f) as u8) + } + #[doc = "Bit 24 - Rx FIFO 1 Full"] + #[inline(always)] + pub fn f1f(&self) -> F1F_R { + F1F_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Rx FIFO 1 Message Lost"] + #[inline(always)] + pub fn rf1l(&self) -> RF1L_R { + RF1L_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bits 30:31 - Debug Message Status"] + #[inline(always)] + pub fn dms(&self) -> DMS_R { + DMS_R::new(((self.bits >> 30) & 0x03) as u8) + } +} +#[doc = "Rx FIFO 1 Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxf1s](index.html) module"] +pub struct RXF1S_SPEC; +impl crate::RegisterSpec for RXF1S_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rxf1s::R](R) reader structure"] +impl crate::Readable for RXF1S_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets RXF1S to value 0"] +impl crate::Resettable for RXF1S_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/can0/sidfc.rs b/pac/atsamc21g/src/can0/sidfc.rs new file mode 100644 index 000000000000..95a73efe426a --- /dev/null +++ b/pac/atsamc21g/src/can0/sidfc.rs @@ -0,0 +1,140 @@ +#[doc = "Register `SIDFC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SIDFC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FLSSA` reader - Filter List Standard Start Address"] +pub struct FLSSA_R(crate::FieldReader); +impl FLSSA_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + FLSSA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FLSSA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLSSA` writer - Filter List Standard Start Address"] +pub struct FLSSA_W<'a> { + w: &'a mut W, +} +impl<'a> FLSSA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +#[doc = "Field `LSS` reader - List Size Standard"] +pub struct LSS_R(crate::FieldReader); +impl LSS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LSS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LSS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LSS` writer - List Size Standard"] +pub struct LSS_W<'a> { + w: &'a mut W, +} +impl<'a> LSS_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Filter List Standard Start Address"] + #[inline(always)] + pub fn flssa(&self) -> FLSSA_R { + FLSSA_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:23 - List Size Standard"] + #[inline(always)] + pub fn lss(&self) -> LSS_R { + LSS_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:15 - Filter List Standard Start Address"] + #[inline(always)] + pub fn flssa(&mut self) -> FLSSA_W { + FLSSA_W { w: self } + } + #[doc = "Bits 16:23 - List Size Standard"] + #[inline(always)] + pub fn lss(&mut self) -> LSS_W { + LSS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Standard ID Filter Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sidfc](index.html) module"] +pub struct SIDFC_SPEC; +impl crate::RegisterSpec for SIDFC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [sidfc::R](R) reader structure"] +impl crate::Readable for SIDFC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [sidfc::W](W) writer structure"] +impl crate::Writable for SIDFC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SIDFC to value 0"] +impl crate::Resettable for SIDFC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/can0/tdcr.rs b/pac/atsamc21g/src/can0/tdcr.rs new file mode 100644 index 000000000000..0cec58f98e28 --- /dev/null +++ b/pac/atsamc21g/src/can0/tdcr.rs @@ -0,0 +1,140 @@ +#[doc = "Register `TDCR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TDCR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TDCF` reader - Transmitter Delay Compensation Filter Length"] +pub struct TDCF_R(crate::FieldReader); +impl TDCF_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TDCF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TDCF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TDCF` writer - Transmitter Delay Compensation Filter Length"] +pub struct TDCF_W<'a> { + w: &'a mut W, +} +impl<'a> TDCF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x7f) | (value as u32 & 0x7f); + self.w + } +} +#[doc = "Field `TDCO` reader - Transmitter Delay Compensation Offset"] +pub struct TDCO_R(crate::FieldReader); +impl TDCO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TDCO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TDCO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TDCO` writer - Transmitter Delay Compensation Offset"] +pub struct TDCO_W<'a> { + w: &'a mut W, +} +impl<'a> TDCO_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x7f << 8)) | ((value as u32 & 0x7f) << 8); + self.w + } +} +impl R { + #[doc = "Bits 0:6 - Transmitter Delay Compensation Filter Length"] + #[inline(always)] + pub fn tdcf(&self) -> TDCF_R { + TDCF_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bits 8:14 - Transmitter Delay Compensation Offset"] + #[inline(always)] + pub fn tdco(&self) -> TDCO_R { + TDCO_R::new(((self.bits >> 8) & 0x7f) as u8) + } +} +impl W { + #[doc = "Bits 0:6 - Transmitter Delay Compensation Filter Length"] + #[inline(always)] + pub fn tdcf(&mut self) -> TDCF_W { + TDCF_W { w: self } + } + #[doc = "Bits 8:14 - Transmitter Delay Compensation Offset"] + #[inline(always)] + pub fn tdco(&mut self) -> TDCO_W { + TDCO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Extended ID Filter Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tdcr](index.html) module"] +pub struct TDCR_SPEC; +impl crate::RegisterSpec for TDCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [tdcr::R](R) reader structure"] +impl crate::Readable for TDCR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [tdcr::W](W) writer structure"] +impl crate::Writable for TDCR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TDCR to value 0"] +impl crate::Resettable for TDCR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/can0/test.rs b/pac/atsamc21g/src/can0/test.rs new file mode 100644 index 000000000000..fe1417a03d90 --- /dev/null +++ b/pac/atsamc21g/src/can0/test.rs @@ -0,0 +1,272 @@ +#[doc = "Register `TEST` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TEST` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `LBCK` reader - Loop Back Mode"] +pub struct LBCK_R(crate::FieldReader); +impl LBCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LBCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LBCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LBCK` writer - Loop Back Mode"] +pub struct LBCK_W<'a> { + w: &'a mut W, +} +impl<'a> LBCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Control of Transmit Pin\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum TX_A { + #[doc = "0: TX controlled by CAN core"] + CORE = 0, + #[doc = "1: TX monitoring sample point"] + SAMPLE = 1, + #[doc = "2: Dominant (0) level at pin CAN_TX"] + DOMINANT = 2, + #[doc = "3: Recessive (1) level at pin CAN_TX"] + RECESSIVE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: TX_A) -> Self { + variant as _ + } +} +#[doc = "Field `TX` reader - Control of Transmit Pin"] +pub struct TX_R(crate::FieldReader); +impl TX_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TX_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TX_A { + match self.bits { + 0 => TX_A::CORE, + 1 => TX_A::SAMPLE, + 2 => TX_A::DOMINANT, + 3 => TX_A::RECESSIVE, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `CORE`"] + #[inline(always)] + pub fn is_core(&self) -> bool { + **self == TX_A::CORE + } + #[doc = "Checks if the value of the field is `SAMPLE`"] + #[inline(always)] + pub fn is_sample(&self) -> bool { + **self == TX_A::SAMPLE + } + #[doc = "Checks if the value of the field is `DOMINANT`"] + #[inline(always)] + pub fn is_dominant(&self) -> bool { + **self == TX_A::DOMINANT + } + #[doc = "Checks if the value of the field is `RECESSIVE`"] + #[inline(always)] + pub fn is_recessive(&self) -> bool { + **self == TX_A::RECESSIVE + } +} +impl core::ops::Deref for TX_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TX` writer - Control of Transmit Pin"] +pub struct TX_W<'a> { + w: &'a mut W, +} +impl<'a> TX_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TX_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "TX controlled by CAN core"] + #[inline(always)] + pub fn core(self) -> &'a mut W { + self.variant(TX_A::CORE) + } + #[doc = "TX monitoring sample point"] + #[inline(always)] + pub fn sample(self) -> &'a mut W { + self.variant(TX_A::SAMPLE) + } + #[doc = "Dominant (0) level at pin CAN_TX"] + #[inline(always)] + pub fn dominant(self) -> &'a mut W { + self.variant(TX_A::DOMINANT) + } + #[doc = "Recessive (1) level at pin CAN_TX"] + #[inline(always)] + pub fn recessive(self) -> &'a mut W { + self.variant(TX_A::RECESSIVE) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 5)) | ((value as u32 & 0x03) << 5); + self.w + } +} +#[doc = "Field `RX` reader - Receive Pin"] +pub struct RX_R(crate::FieldReader); +impl RX_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RX_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RX_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RX` writer - Receive Pin"] +pub struct RX_W<'a> { + w: &'a mut W, +} +impl<'a> RX_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 4 - Loop Back Mode"] + #[inline(always)] + pub fn lbck(&self) -> LBCK_R { + LBCK_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bits 5:6 - Control of Transmit Pin"] + #[inline(always)] + pub fn tx(&self) -> TX_R { + TX_R::new(((self.bits >> 5) & 0x03) as u8) + } + #[doc = "Bit 7 - Receive Pin"] + #[inline(always)] + pub fn rx(&self) -> RX_R { + RX_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 4 - Loop Back Mode"] + #[inline(always)] + pub fn lbck(&mut self) -> LBCK_W { + LBCK_W { w: self } + } + #[doc = "Bits 5:6 - Control of Transmit Pin"] + #[inline(always)] + pub fn tx(&mut self) -> TX_W { + TX_W { w: self } + } + #[doc = "Bit 7 - Receive Pin"] + #[inline(always)] + pub fn rx(&mut self) -> RX_W { + RX_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Test\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [test](index.html) module"] +pub struct TEST_SPEC; +impl crate::RegisterSpec for TEST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [test::R](R) reader structure"] +impl crate::Readable for TEST_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [test::W](W) writer structure"] +impl crate::Writable for TEST_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TEST to value 0"] +impl crate::Resettable for TEST_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/can0/tocc.rs b/pac/atsamc21g/src/can0/tocc.rs new file mode 100644 index 000000000000..fa64916ef75f --- /dev/null +++ b/pac/atsamc21g/src/can0/tocc.rs @@ -0,0 +1,262 @@ +#[doc = "Register `TOCC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TOCC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ETOC` reader - Enable Timeout Counter"] +pub struct ETOC_R(crate::FieldReader); +impl ETOC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ETOC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ETOC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ETOC` writer - Enable Timeout Counter"] +pub struct ETOC_W<'a> { + w: &'a mut W, +} +impl<'a> ETOC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Timeout Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum TOS_A { + #[doc = "0: Continuout operation"] + CONT = 0, + #[doc = "1: Timeout controlled by TX Event FIFO"] + TXEF = 1, + #[doc = "2: Timeout controlled by Rx FIFO 0"] + RXF0 = 2, + #[doc = "3: Timeout controlled by Rx FIFO 1"] + RXF1 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: TOS_A) -> Self { + variant as _ + } +} +#[doc = "Field `TOS` reader - Timeout Select"] +pub struct TOS_R(crate::FieldReader); +impl TOS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TOS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TOS_A { + match self.bits { + 0 => TOS_A::CONT, + 1 => TOS_A::TXEF, + 2 => TOS_A::RXF0, + 3 => TOS_A::RXF1, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `CONT`"] + #[inline(always)] + pub fn is_cont(&self) -> bool { + **self == TOS_A::CONT + } + #[doc = "Checks if the value of the field is `TXEF`"] + #[inline(always)] + pub fn is_txef(&self) -> bool { + **self == TOS_A::TXEF + } + #[doc = "Checks if the value of the field is `RXF0`"] + #[inline(always)] + pub fn is_rxf0(&self) -> bool { + **self == TOS_A::RXF0 + } + #[doc = "Checks if the value of the field is `RXF1`"] + #[inline(always)] + pub fn is_rxf1(&self) -> bool { + **self == TOS_A::RXF1 + } +} +impl core::ops::Deref for TOS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TOS` writer - Timeout Select"] +pub struct TOS_W<'a> { + w: &'a mut W, +} +impl<'a> TOS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TOS_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Continuout operation"] + #[inline(always)] + pub fn cont(self) -> &'a mut W { + self.variant(TOS_A::CONT) + } + #[doc = "Timeout controlled by TX Event FIFO"] + #[inline(always)] + pub fn txef(self) -> &'a mut W { + self.variant(TOS_A::TXEF) + } + #[doc = "Timeout controlled by Rx FIFO 0"] + #[inline(always)] + pub fn rxf0(self) -> &'a mut W { + self.variant(TOS_A::RXF0) + } + #[doc = "Timeout controlled by Rx FIFO 1"] + #[inline(always)] + pub fn rxf1(self) -> &'a mut W { + self.variant(TOS_A::RXF1) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 1)) | ((value as u32 & 0x03) << 1); + self.w + } +} +#[doc = "Field `TOP` reader - Timeout Period"] +pub struct TOP_R(crate::FieldReader); +impl TOP_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + TOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TOP` writer - Timeout Period"] +pub struct TOP_W<'a> { + w: &'a mut W, +} +impl<'a> TOP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xffff << 16)) | ((value as u32 & 0xffff) << 16); + self.w + } +} +impl R { + #[doc = "Bit 0 - Enable Timeout Counter"] + #[inline(always)] + pub fn etoc(&self) -> ETOC_R { + ETOC_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bits 1:2 - Timeout Select"] + #[inline(always)] + pub fn tos(&self) -> TOS_R { + TOS_R::new(((self.bits >> 1) & 0x03) as u8) + } + #[doc = "Bits 16:31 - Timeout Period"] + #[inline(always)] + pub fn top(&self) -> TOP_R { + TOP_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bit 0 - Enable Timeout Counter"] + #[inline(always)] + pub fn etoc(&mut self) -> ETOC_W { + ETOC_W { w: self } + } + #[doc = "Bits 1:2 - Timeout Select"] + #[inline(always)] + pub fn tos(&mut self) -> TOS_W { + TOS_W { w: self } + } + #[doc = "Bits 16:31 - Timeout Period"] + #[inline(always)] + pub fn top(&mut self) -> TOP_W { + TOP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Timeout Counter Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tocc](index.html) module"] +pub struct TOCC_SPEC; +impl crate::RegisterSpec for TOCC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [tocc::R](R) reader structure"] +impl crate::Readable for TOCC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [tocc::W](W) writer structure"] +impl crate::Writable for TOCC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TOCC to value 0xffff_0000"] +impl crate::Resettable for TOCC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_0000 + } +} diff --git a/pac/atsamc21g/src/can0/tocv.rs b/pac/atsamc21g/src/can0/tocv.rs new file mode 100644 index 000000000000..f49b24ce65bf --- /dev/null +++ b/pac/atsamc21g/src/can0/tocv.rs @@ -0,0 +1,103 @@ +#[doc = "Register `TOCV` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TOCV` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TOC` reader - Timeout Counter"] +pub struct TOC_R(crate::FieldReader); +impl TOC_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + TOC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TOC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TOC` writer - Timeout Counter"] +pub struct TOC_W<'a> { + w: &'a mut W, +} +impl<'a> TOC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Timeout Counter"] + #[inline(always)] + pub fn toc(&self) -> TOC_R { + TOC_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Timeout Counter"] + #[inline(always)] + pub fn toc(&mut self) -> TOC_W { + TOC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Timeout Counter Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tocv](index.html) module"] +pub struct TOCV_SPEC; +impl crate::RegisterSpec for TOCV_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [tocv::R](R) reader structure"] +impl crate::Readable for TOCV_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [tocv::W](W) writer structure"] +impl crate::Writable for TOCV_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TOCV to value 0xffff"] +impl crate::Resettable for TOCV_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff + } +} diff --git a/pac/atsamc21g/src/can0/tscc.rs b/pac/atsamc21g/src/can0/tscc.rs new file mode 100644 index 000000000000..298084cc06b8 --- /dev/null +++ b/pac/atsamc21g/src/can0/tscc.rs @@ -0,0 +1,202 @@ +#[doc = "Register `TSCC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TSCC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Timestamp Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum TSS_A { + #[doc = "0: Timestamp counter value always 0x0000"] + ZERO = 0, + #[doc = "1: Timestamp counter value incremented by TCP"] + INC = 1, + #[doc = "2: External timestamp counter value used"] + EXT = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: TSS_A) -> Self { + variant as _ + } +} +#[doc = "Field `TSS` reader - Timestamp Select"] +pub struct TSS_R(crate::FieldReader); +impl TSS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TSS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(TSS_A::ZERO), + 1 => Some(TSS_A::INC), + 2 => Some(TSS_A::EXT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `ZERO`"] + #[inline(always)] + pub fn is_zero(&self) -> bool { + **self == TSS_A::ZERO + } + #[doc = "Checks if the value of the field is `INC`"] + #[inline(always)] + pub fn is_inc(&self) -> bool { + **self == TSS_A::INC + } + #[doc = "Checks if the value of the field is `EXT`"] + #[inline(always)] + pub fn is_ext(&self) -> bool { + **self == TSS_A::EXT + } +} +impl core::ops::Deref for TSS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSS` writer - Timestamp Select"] +pub struct TSS_W<'a> { + w: &'a mut W, +} +impl<'a> TSS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TSS_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Timestamp counter value always 0x0000"] + #[inline(always)] + pub fn zero(self) -> &'a mut W { + self.variant(TSS_A::ZERO) + } + #[doc = "Timestamp counter value incremented by TCP"] + #[inline(always)] + pub fn inc(self) -> &'a mut W { + self.variant(TSS_A::INC) + } + #[doc = "External timestamp counter value used"] + #[inline(always)] + pub fn ext(self) -> &'a mut W { + self.variant(TSS_A::EXT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u32 & 0x03); + self.w + } +} +#[doc = "Field `TCP` reader - Timestamp Counter Prescaler"] +pub struct TCP_R(crate::FieldReader); +impl TCP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TCP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCP` writer - Timestamp Counter Prescaler"] +pub struct TCP_W<'a> { + w: &'a mut W, +} +impl<'a> TCP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 16)) | ((value as u32 & 0x0f) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Timestamp Select"] + #[inline(always)] + pub fn tss(&self) -> TSS_R { + TSS_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bits 16:19 - Timestamp Counter Prescaler"] + #[inline(always)] + pub fn tcp(&self) -> TCP_R { + TCP_R::new(((self.bits >> 16) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Timestamp Select"] + #[inline(always)] + pub fn tss(&mut self) -> TSS_W { + TSS_W { w: self } + } + #[doc = "Bits 16:19 - Timestamp Counter Prescaler"] + #[inline(always)] + pub fn tcp(&mut self) -> TCP_W { + TCP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Timestamp Counter Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tscc](index.html) module"] +pub struct TSCC_SPEC; +impl crate::RegisterSpec for TSCC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [tscc::R](R) reader structure"] +impl crate::Readable for TSCC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [tscc::W](W) writer structure"] +impl crate::Writable for TSCC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TSCC to value 0"] +impl crate::Resettable for TSCC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/can0/tscv.rs b/pac/atsamc21g/src/can0/tscv.rs new file mode 100644 index 000000000000..7ba4561d588f --- /dev/null +++ b/pac/atsamc21g/src/can0/tscv.rs @@ -0,0 +1,53 @@ +#[doc = "Register `TSCV` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `TSC` reader - Timestamp Counter"] +pub struct TSC_R(crate::FieldReader); +impl TSC_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + TSC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:15 - Timestamp Counter"] + #[inline(always)] + pub fn tsc(&self) -> TSC_R { + TSC_R::new((self.bits & 0xffff) as u16) + } +} +#[doc = "Timestamp Counter Value\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tscv](index.html) module"] +pub struct TSCV_SPEC; +impl crate::RegisterSpec for TSCV_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [tscv::R](R) reader structure"] +impl crate::Readable for TSCV_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets TSCV to value 0"] +impl crate::Resettable for TSCV_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/can0/txbar.rs b/pac/atsamc21g/src/can0/txbar.rs new file mode 100644 index 000000000000..bd15a3f2bd29 --- /dev/null +++ b/pac/atsamc21g/src/can0/txbar.rs @@ -0,0 +1,1570 @@ +#[doc = "Register `TXBAR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TXBAR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `AR0` reader - Add Request 0"] +pub struct AR0_R(crate::FieldReader); +impl AR0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR0` writer - Add Request 0"] +pub struct AR0_W<'a> { + w: &'a mut W, +} +impl<'a> AR0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `AR1` reader - Add Request 1"] +pub struct AR1_R(crate::FieldReader); +impl AR1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR1` writer - Add Request 1"] +pub struct AR1_W<'a> { + w: &'a mut W, +} +impl<'a> AR1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `AR2` reader - Add Request 2"] +pub struct AR2_R(crate::FieldReader); +impl AR2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR2` writer - Add Request 2"] +pub struct AR2_W<'a> { + w: &'a mut W, +} +impl<'a> AR2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `AR3` reader - Add Request 3"] +pub struct AR3_R(crate::FieldReader); +impl AR3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR3` writer - Add Request 3"] +pub struct AR3_W<'a> { + w: &'a mut W, +} +impl<'a> AR3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `AR4` reader - Add Request 4"] +pub struct AR4_R(crate::FieldReader); +impl AR4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR4` writer - Add Request 4"] +pub struct AR4_W<'a> { + w: &'a mut W, +} +impl<'a> AR4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `AR5` reader - Add Request 5"] +pub struct AR5_R(crate::FieldReader); +impl AR5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR5` writer - Add Request 5"] +pub struct AR5_W<'a> { + w: &'a mut W, +} +impl<'a> AR5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `AR6` reader - Add Request 6"] +pub struct AR6_R(crate::FieldReader); +impl AR6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR6` writer - Add Request 6"] +pub struct AR6_W<'a> { + w: &'a mut W, +} +impl<'a> AR6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `AR7` reader - Add Request 7"] +pub struct AR7_R(crate::FieldReader); +impl AR7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR7` writer - Add Request 7"] +pub struct AR7_W<'a> { + w: &'a mut W, +} +impl<'a> AR7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `AR8` reader - Add Request 8"] +pub struct AR8_R(crate::FieldReader); +impl AR8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR8` writer - Add Request 8"] +pub struct AR8_W<'a> { + w: &'a mut W, +} +impl<'a> AR8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `AR9` reader - Add Request 9"] +pub struct AR9_R(crate::FieldReader); +impl AR9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR9` writer - Add Request 9"] +pub struct AR9_W<'a> { + w: &'a mut W, +} +impl<'a> AR9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `AR10` reader - Add Request 10"] +pub struct AR10_R(crate::FieldReader); +impl AR10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR10` writer - Add Request 10"] +pub struct AR10_W<'a> { + w: &'a mut W, +} +impl<'a> AR10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `AR11` reader - Add Request 11"] +pub struct AR11_R(crate::FieldReader); +impl AR11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR11` writer - Add Request 11"] +pub struct AR11_W<'a> { + w: &'a mut W, +} +impl<'a> AR11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `AR12` reader - Add Request 12"] +pub struct AR12_R(crate::FieldReader); +impl AR12_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR12_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR12_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR12` writer - Add Request 12"] +pub struct AR12_W<'a> { + w: &'a mut W, +} +impl<'a> AR12_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `AR13` reader - Add Request 13"] +pub struct AR13_R(crate::FieldReader); +impl AR13_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR13_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR13_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR13` writer - Add Request 13"] +pub struct AR13_W<'a> { + w: &'a mut W, +} +impl<'a> AR13_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `AR14` reader - Add Request 14"] +pub struct AR14_R(crate::FieldReader); +impl AR14_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR14_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR14_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR14` writer - Add Request 14"] +pub struct AR14_W<'a> { + w: &'a mut W, +} +impl<'a> AR14_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `AR15` reader - Add Request 15"] +pub struct AR15_R(crate::FieldReader); +impl AR15_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR15_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR15_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR15` writer - Add Request 15"] +pub struct AR15_W<'a> { + w: &'a mut W, +} +impl<'a> AR15_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `AR16` reader - Add Request 16"] +pub struct AR16_R(crate::FieldReader); +impl AR16_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR16_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR16_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR16` writer - Add Request 16"] +pub struct AR16_W<'a> { + w: &'a mut W, +} +impl<'a> AR16_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `AR17` reader - Add Request 17"] +pub struct AR17_R(crate::FieldReader); +impl AR17_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR17_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR17_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR17` writer - Add Request 17"] +pub struct AR17_W<'a> { + w: &'a mut W, +} +impl<'a> AR17_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `AR18` reader - Add Request 18"] +pub struct AR18_R(crate::FieldReader); +impl AR18_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR18_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR18_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR18` writer - Add Request 18"] +pub struct AR18_W<'a> { + w: &'a mut W, +} +impl<'a> AR18_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `AR19` reader - Add Request 19"] +pub struct AR19_R(crate::FieldReader); +impl AR19_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR19_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR19_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR19` writer - Add Request 19"] +pub struct AR19_W<'a> { + w: &'a mut W, +} +impl<'a> AR19_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `AR20` reader - Add Request 20"] +pub struct AR20_R(crate::FieldReader); +impl AR20_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR20_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR20_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR20` writer - Add Request 20"] +pub struct AR20_W<'a> { + w: &'a mut W, +} +impl<'a> AR20_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `AR21` reader - Add Request 21"] +pub struct AR21_R(crate::FieldReader); +impl AR21_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR21_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR21_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR21` writer - Add Request 21"] +pub struct AR21_W<'a> { + w: &'a mut W, +} +impl<'a> AR21_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `AR22` reader - Add Request 22"] +pub struct AR22_R(crate::FieldReader); +impl AR22_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR22_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR22_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR22` writer - Add Request 22"] +pub struct AR22_W<'a> { + w: &'a mut W, +} +impl<'a> AR22_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `AR23` reader - Add Request 23"] +pub struct AR23_R(crate::FieldReader); +impl AR23_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR23_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR23_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR23` writer - Add Request 23"] +pub struct AR23_W<'a> { + w: &'a mut W, +} +impl<'a> AR23_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `AR24` reader - Add Request 24"] +pub struct AR24_R(crate::FieldReader); +impl AR24_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR24_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR24_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR24` writer - Add Request 24"] +pub struct AR24_W<'a> { + w: &'a mut W, +} +impl<'a> AR24_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `AR25` reader - Add Request 25"] +pub struct AR25_R(crate::FieldReader); +impl AR25_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR25_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR25_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR25` writer - Add Request 25"] +pub struct AR25_W<'a> { + w: &'a mut W, +} +impl<'a> AR25_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `AR26` reader - Add Request 26"] +pub struct AR26_R(crate::FieldReader); +impl AR26_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR26_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR26_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR26` writer - Add Request 26"] +pub struct AR26_W<'a> { + w: &'a mut W, +} +impl<'a> AR26_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `AR27` reader - Add Request 27"] +pub struct AR27_R(crate::FieldReader); +impl AR27_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR27_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR27_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR27` writer - Add Request 27"] +pub struct AR27_W<'a> { + w: &'a mut W, +} +impl<'a> AR27_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +#[doc = "Field `AR28` reader - Add Request 28"] +pub struct AR28_R(crate::FieldReader); +impl AR28_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR28_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR28_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR28` writer - Add Request 28"] +pub struct AR28_W<'a> { + w: &'a mut W, +} +impl<'a> AR28_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Field `AR29` reader - Add Request 29"] +pub struct AR29_R(crate::FieldReader); +impl AR29_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR29_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR29_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR29` writer - Add Request 29"] +pub struct AR29_W<'a> { + w: &'a mut W, +} +impl<'a> AR29_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29); + self.w + } +} +#[doc = "Field `AR30` reader - Add Request 30"] +pub struct AR30_R(crate::FieldReader); +impl AR30_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR30_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR30_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR30` writer - Add Request 30"] +pub struct AR30_W<'a> { + w: &'a mut W, +} +impl<'a> AR30_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +#[doc = "Field `AR31` reader - Add Request 31"] +pub struct AR31_R(crate::FieldReader); +impl AR31_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR31_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR31_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR31` writer - Add Request 31"] +pub struct AR31_W<'a> { + w: &'a mut W, +} +impl<'a> AR31_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bit 0 - Add Request 0"] + #[inline(always)] + pub fn ar0(&self) -> AR0_R { + AR0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Add Request 1"] + #[inline(always)] + pub fn ar1(&self) -> AR1_R { + AR1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Add Request 2"] + #[inline(always)] + pub fn ar2(&self) -> AR2_R { + AR2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Add Request 3"] + #[inline(always)] + pub fn ar3(&self) -> AR3_R { + AR3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Add Request 4"] + #[inline(always)] + pub fn ar4(&self) -> AR4_R { + AR4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Add Request 5"] + #[inline(always)] + pub fn ar5(&self) -> AR5_R { + AR5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Add Request 6"] + #[inline(always)] + pub fn ar6(&self) -> AR6_R { + AR6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Add Request 7"] + #[inline(always)] + pub fn ar7(&self) -> AR7_R { + AR7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Add Request 8"] + #[inline(always)] + pub fn ar8(&self) -> AR8_R { + AR8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Add Request 9"] + #[inline(always)] + pub fn ar9(&self) -> AR9_R { + AR9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Add Request 10"] + #[inline(always)] + pub fn ar10(&self) -> AR10_R { + AR10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Add Request 11"] + #[inline(always)] + pub fn ar11(&self) -> AR11_R { + AR11_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Add Request 12"] + #[inline(always)] + pub fn ar12(&self) -> AR12_R { + AR12_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Add Request 13"] + #[inline(always)] + pub fn ar13(&self) -> AR13_R { + AR13_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Add Request 14"] + #[inline(always)] + pub fn ar14(&self) -> AR14_R { + AR14_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Add Request 15"] + #[inline(always)] + pub fn ar15(&self) -> AR15_R { + AR15_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Add Request 16"] + #[inline(always)] + pub fn ar16(&self) -> AR16_R { + AR16_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Add Request 17"] + #[inline(always)] + pub fn ar17(&self) -> AR17_R { + AR17_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Add Request 18"] + #[inline(always)] + pub fn ar18(&self) -> AR18_R { + AR18_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Add Request 19"] + #[inline(always)] + pub fn ar19(&self) -> AR19_R { + AR19_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Add Request 20"] + #[inline(always)] + pub fn ar20(&self) -> AR20_R { + AR20_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Add Request 21"] + #[inline(always)] + pub fn ar21(&self) -> AR21_R { + AR21_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Add Request 22"] + #[inline(always)] + pub fn ar22(&self) -> AR22_R { + AR22_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Add Request 23"] + #[inline(always)] + pub fn ar23(&self) -> AR23_R { + AR23_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24 - Add Request 24"] + #[inline(always)] + pub fn ar24(&self) -> AR24_R { + AR24_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Add Request 25"] + #[inline(always)] + pub fn ar25(&self) -> AR25_R { + AR25_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Add Request 26"] + #[inline(always)] + pub fn ar26(&self) -> AR26_R { + AR26_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Add Request 27"] + #[inline(always)] + pub fn ar27(&self) -> AR27_R { + AR27_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28 - Add Request 28"] + #[inline(always)] + pub fn ar28(&self) -> AR28_R { + AR28_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Add Request 29"] + #[inline(always)] + pub fn ar29(&self) -> AR29_R { + AR29_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - Add Request 30"] + #[inline(always)] + pub fn ar30(&self) -> AR30_R { + AR30_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 31 - Add Request 31"] + #[inline(always)] + pub fn ar31(&self) -> AR31_R { + AR31_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Add Request 0"] + #[inline(always)] + pub fn ar0(&mut self) -> AR0_W { + AR0_W { w: self } + } + #[doc = "Bit 1 - Add Request 1"] + #[inline(always)] + pub fn ar1(&mut self) -> AR1_W { + AR1_W { w: self } + } + #[doc = "Bit 2 - Add Request 2"] + #[inline(always)] + pub fn ar2(&mut self) -> AR2_W { + AR2_W { w: self } + } + #[doc = "Bit 3 - Add Request 3"] + #[inline(always)] + pub fn ar3(&mut self) -> AR3_W { + AR3_W { w: self } + } + #[doc = "Bit 4 - Add Request 4"] + #[inline(always)] + pub fn ar4(&mut self) -> AR4_W { + AR4_W { w: self } + } + #[doc = "Bit 5 - Add Request 5"] + #[inline(always)] + pub fn ar5(&mut self) -> AR5_W { + AR5_W { w: self } + } + #[doc = "Bit 6 - Add Request 6"] + #[inline(always)] + pub fn ar6(&mut self) -> AR6_W { + AR6_W { w: self } + } + #[doc = "Bit 7 - Add Request 7"] + #[inline(always)] + pub fn ar7(&mut self) -> AR7_W { + AR7_W { w: self } + } + #[doc = "Bit 8 - Add Request 8"] + #[inline(always)] + pub fn ar8(&mut self) -> AR8_W { + AR8_W { w: self } + } + #[doc = "Bit 9 - Add Request 9"] + #[inline(always)] + pub fn ar9(&mut self) -> AR9_W { + AR9_W { w: self } + } + #[doc = "Bit 10 - Add Request 10"] + #[inline(always)] + pub fn ar10(&mut self) -> AR10_W { + AR10_W { w: self } + } + #[doc = "Bit 11 - Add Request 11"] + #[inline(always)] + pub fn ar11(&mut self) -> AR11_W { + AR11_W { w: self } + } + #[doc = "Bit 12 - Add Request 12"] + #[inline(always)] + pub fn ar12(&mut self) -> AR12_W { + AR12_W { w: self } + } + #[doc = "Bit 13 - Add Request 13"] + #[inline(always)] + pub fn ar13(&mut self) -> AR13_W { + AR13_W { w: self } + } + #[doc = "Bit 14 - Add Request 14"] + #[inline(always)] + pub fn ar14(&mut self) -> AR14_W { + AR14_W { w: self } + } + #[doc = "Bit 15 - Add Request 15"] + #[inline(always)] + pub fn ar15(&mut self) -> AR15_W { + AR15_W { w: self } + } + #[doc = "Bit 16 - Add Request 16"] + #[inline(always)] + pub fn ar16(&mut self) -> AR16_W { + AR16_W { w: self } + } + #[doc = "Bit 17 - Add Request 17"] + #[inline(always)] + pub fn ar17(&mut self) -> AR17_W { + AR17_W { w: self } + } + #[doc = "Bit 18 - Add Request 18"] + #[inline(always)] + pub fn ar18(&mut self) -> AR18_W { + AR18_W { w: self } + } + #[doc = "Bit 19 - Add Request 19"] + #[inline(always)] + pub fn ar19(&mut self) -> AR19_W { + AR19_W { w: self } + } + #[doc = "Bit 20 - Add Request 20"] + #[inline(always)] + pub fn ar20(&mut self) -> AR20_W { + AR20_W { w: self } + } + #[doc = "Bit 21 - Add Request 21"] + #[inline(always)] + pub fn ar21(&mut self) -> AR21_W { + AR21_W { w: self } + } + #[doc = "Bit 22 - Add Request 22"] + #[inline(always)] + pub fn ar22(&mut self) -> AR22_W { + AR22_W { w: self } + } + #[doc = "Bit 23 - Add Request 23"] + #[inline(always)] + pub fn ar23(&mut self) -> AR23_W { + AR23_W { w: self } + } + #[doc = "Bit 24 - Add Request 24"] + #[inline(always)] + pub fn ar24(&mut self) -> AR24_W { + AR24_W { w: self } + } + #[doc = "Bit 25 - Add Request 25"] + #[inline(always)] + pub fn ar25(&mut self) -> AR25_W { + AR25_W { w: self } + } + #[doc = "Bit 26 - Add Request 26"] + #[inline(always)] + pub fn ar26(&mut self) -> AR26_W { + AR26_W { w: self } + } + #[doc = "Bit 27 - Add Request 27"] + #[inline(always)] + pub fn ar27(&mut self) -> AR27_W { + AR27_W { w: self } + } + #[doc = "Bit 28 - Add Request 28"] + #[inline(always)] + pub fn ar28(&mut self) -> AR28_W { + AR28_W { w: self } + } + #[doc = "Bit 29 - Add Request 29"] + #[inline(always)] + pub fn ar29(&mut self) -> AR29_W { + AR29_W { w: self } + } + #[doc = "Bit 30 - Add Request 30"] + #[inline(always)] + pub fn ar30(&mut self) -> AR30_W { + AR30_W { w: self } + } + #[doc = "Bit 31 - Add Request 31"] + #[inline(always)] + pub fn ar31(&mut self) -> AR31_W { + AR31_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Tx Buffer Add Request\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txbar](index.html) module"] +pub struct TXBAR_SPEC; +impl crate::RegisterSpec for TXBAR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [txbar::R](R) reader structure"] +impl crate::Readable for TXBAR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [txbar::W](W) writer structure"] +impl crate::Writable for TXBAR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TXBAR to value 0"] +impl crate::Resettable for TXBAR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/can0/txbc.rs b/pac/atsamc21g/src/can0/txbc.rs new file mode 100644 index 000000000000..9545eaebf91d --- /dev/null +++ b/pac/atsamc21g/src/can0/txbc.rs @@ -0,0 +1,224 @@ +#[doc = "Register `TXBC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TXBC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TBSA` reader - Tx Buffers Start Address"] +pub struct TBSA_R(crate::FieldReader); +impl TBSA_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + TBSA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TBSA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TBSA` writer - Tx Buffers Start Address"] +pub struct TBSA_W<'a> { + w: &'a mut W, +} +impl<'a> TBSA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +#[doc = "Field `NDTB` reader - Number of Dedicated Transmit Buffers"] +pub struct NDTB_R(crate::FieldReader); +impl NDTB_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + NDTB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NDTB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NDTB` writer - Number of Dedicated Transmit Buffers"] +pub struct NDTB_W<'a> { + w: &'a mut W, +} +impl<'a> NDTB_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 16)) | ((value as u32 & 0x3f) << 16); + self.w + } +} +#[doc = "Field `TFQS` reader - Transmit FIFO/Queue Size"] +pub struct TFQS_R(crate::FieldReader); +impl TFQS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TFQS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TFQS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TFQS` writer - Transmit FIFO/Queue Size"] +pub struct TFQS_W<'a> { + w: &'a mut W, +} +impl<'a> TFQS_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 24)) | ((value as u32 & 0x3f) << 24); + self.w + } +} +#[doc = "Field `TFQM` reader - Tx FIFO/Queue Mode"] +pub struct TFQM_R(crate::FieldReader); +impl TFQM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TFQM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TFQM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TFQM` writer - Tx FIFO/Queue Mode"] +pub struct TFQM_W<'a> { + w: &'a mut W, +} +impl<'a> TFQM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Tx Buffers Start Address"] + #[inline(always)] + pub fn tbsa(&self) -> TBSA_R { + TBSA_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:21 - Number of Dedicated Transmit Buffers"] + #[inline(always)] + pub fn ndtb(&self) -> NDTB_R { + NDTB_R::new(((self.bits >> 16) & 0x3f) as u8) + } + #[doc = "Bits 24:29 - Transmit FIFO/Queue Size"] + #[inline(always)] + pub fn tfqs(&self) -> TFQS_R { + TFQS_R::new(((self.bits >> 24) & 0x3f) as u8) + } + #[doc = "Bit 30 - Tx FIFO/Queue Mode"] + #[inline(always)] + pub fn tfqm(&self) -> TFQM_R { + TFQM_R::new(((self.bits >> 30) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Tx Buffers Start Address"] + #[inline(always)] + pub fn tbsa(&mut self) -> TBSA_W { + TBSA_W { w: self } + } + #[doc = "Bits 16:21 - Number of Dedicated Transmit Buffers"] + #[inline(always)] + pub fn ndtb(&mut self) -> NDTB_W { + NDTB_W { w: self } + } + #[doc = "Bits 24:29 - Transmit FIFO/Queue Size"] + #[inline(always)] + pub fn tfqs(&mut self) -> TFQS_W { + TFQS_W { w: self } + } + #[doc = "Bit 30 - Tx FIFO/Queue Mode"] + #[inline(always)] + pub fn tfqm(&mut self) -> TFQM_W { + TFQM_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Tx Buffer Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txbc](index.html) module"] +pub struct TXBC_SPEC; +impl crate::RegisterSpec for TXBC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [txbc::R](R) reader structure"] +impl crate::Readable for TXBC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [txbc::W](W) writer structure"] +impl crate::Writable for TXBC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TXBC to value 0"] +impl crate::Resettable for TXBC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/can0/txbcf.rs b/pac/atsamc21g/src/can0/txbcf.rs new file mode 100644 index 000000000000..e592d4e90bea --- /dev/null +++ b/pac/atsamc21g/src/can0/txbcf.rs @@ -0,0 +1,673 @@ +#[doc = "Register `TXBCF` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `CF0` reader - Tx Buffer Cancellation Finished 0"] +pub struct CF0_R(crate::FieldReader); +impl CF0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF1` reader - Tx Buffer Cancellation Finished 1"] +pub struct CF1_R(crate::FieldReader); +impl CF1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF2` reader - Tx Buffer Cancellation Finished 2"] +pub struct CF2_R(crate::FieldReader); +impl CF2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF3` reader - Tx Buffer Cancellation Finished 3"] +pub struct CF3_R(crate::FieldReader); +impl CF3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF4` reader - Tx Buffer Cancellation Finished 4"] +pub struct CF4_R(crate::FieldReader); +impl CF4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF5` reader - Tx Buffer Cancellation Finished 5"] +pub struct CF5_R(crate::FieldReader); +impl CF5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF6` reader - Tx Buffer Cancellation Finished 6"] +pub struct CF6_R(crate::FieldReader); +impl CF6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF7` reader - Tx Buffer Cancellation Finished 7"] +pub struct CF7_R(crate::FieldReader); +impl CF7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF8` reader - Tx Buffer Cancellation Finished 8"] +pub struct CF8_R(crate::FieldReader); +impl CF8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF9` reader - Tx Buffer Cancellation Finished 9"] +pub struct CF9_R(crate::FieldReader); +impl CF9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF10` reader - Tx Buffer Cancellation Finished 10"] +pub struct CF10_R(crate::FieldReader); +impl CF10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF11` reader - Tx Buffer Cancellation Finished 11"] +pub struct CF11_R(crate::FieldReader); +impl CF11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF12` reader - Tx Buffer Cancellation Finished 12"] +pub struct CF12_R(crate::FieldReader); +impl CF12_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF12_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF12_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF13` reader - Tx Buffer Cancellation Finished 13"] +pub struct CF13_R(crate::FieldReader); +impl CF13_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF13_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF13_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF14` reader - Tx Buffer Cancellation Finished 14"] +pub struct CF14_R(crate::FieldReader); +impl CF14_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF14_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF14_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF15` reader - Tx Buffer Cancellation Finished 15"] +pub struct CF15_R(crate::FieldReader); +impl CF15_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF15_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF15_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF16` reader - Tx Buffer Cancellation Finished 16"] +pub struct CF16_R(crate::FieldReader); +impl CF16_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF16_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF16_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF17` reader - Tx Buffer Cancellation Finished 17"] +pub struct CF17_R(crate::FieldReader); +impl CF17_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF17_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF17_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF18` reader - Tx Buffer Cancellation Finished 18"] +pub struct CF18_R(crate::FieldReader); +impl CF18_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF18_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF18_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF19` reader - Tx Buffer Cancellation Finished 19"] +pub struct CF19_R(crate::FieldReader); +impl CF19_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF19_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF19_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF20` reader - Tx Buffer Cancellation Finished 20"] +pub struct CF20_R(crate::FieldReader); +impl CF20_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF20_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF20_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF21` reader - Tx Buffer Cancellation Finished 21"] +pub struct CF21_R(crate::FieldReader); +impl CF21_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF21_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF21_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF22` reader - Tx Buffer Cancellation Finished 22"] +pub struct CF22_R(crate::FieldReader); +impl CF22_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF22_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF22_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF23` reader - Tx Buffer Cancellation Finished 23"] +pub struct CF23_R(crate::FieldReader); +impl CF23_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF23_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF23_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF24` reader - Tx Buffer Cancellation Finished 24"] +pub struct CF24_R(crate::FieldReader); +impl CF24_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF24_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF24_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF25` reader - Tx Buffer Cancellation Finished 25"] +pub struct CF25_R(crate::FieldReader); +impl CF25_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF25_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF25_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF26` reader - Tx Buffer Cancellation Finished 26"] +pub struct CF26_R(crate::FieldReader); +impl CF26_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF26_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF26_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF27` reader - Tx Buffer Cancellation Finished 27"] +pub struct CF27_R(crate::FieldReader); +impl CF27_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF27_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF27_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF28` reader - Tx Buffer Cancellation Finished 28"] +pub struct CF28_R(crate::FieldReader); +impl CF28_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF28_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF28_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF29` reader - Tx Buffer Cancellation Finished 29"] +pub struct CF29_R(crate::FieldReader); +impl CF29_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF29_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF29_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF30` reader - Tx Buffer Cancellation Finished 30"] +pub struct CF30_R(crate::FieldReader); +impl CF30_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF30_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF30_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF31` reader - Tx Buffer Cancellation Finished 31"] +pub struct CF31_R(crate::FieldReader); +impl CF31_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF31_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF31_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Tx Buffer Cancellation Finished 0"] + #[inline(always)] + pub fn cf0(&self) -> CF0_R { + CF0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Tx Buffer Cancellation Finished 1"] + #[inline(always)] + pub fn cf1(&self) -> CF1_R { + CF1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Tx Buffer Cancellation Finished 2"] + #[inline(always)] + pub fn cf2(&self) -> CF2_R { + CF2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Tx Buffer Cancellation Finished 3"] + #[inline(always)] + pub fn cf3(&self) -> CF3_R { + CF3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Tx Buffer Cancellation Finished 4"] + #[inline(always)] + pub fn cf4(&self) -> CF4_R { + CF4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Tx Buffer Cancellation Finished 5"] + #[inline(always)] + pub fn cf5(&self) -> CF5_R { + CF5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Tx Buffer Cancellation Finished 6"] + #[inline(always)] + pub fn cf6(&self) -> CF6_R { + CF6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Tx Buffer Cancellation Finished 7"] + #[inline(always)] + pub fn cf7(&self) -> CF7_R { + CF7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Tx Buffer Cancellation Finished 8"] + #[inline(always)] + pub fn cf8(&self) -> CF8_R { + CF8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Tx Buffer Cancellation Finished 9"] + #[inline(always)] + pub fn cf9(&self) -> CF9_R { + CF9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Tx Buffer Cancellation Finished 10"] + #[inline(always)] + pub fn cf10(&self) -> CF10_R { + CF10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Tx Buffer Cancellation Finished 11"] + #[inline(always)] + pub fn cf11(&self) -> CF11_R { + CF11_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Tx Buffer Cancellation Finished 12"] + #[inline(always)] + pub fn cf12(&self) -> CF12_R { + CF12_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Tx Buffer Cancellation Finished 13"] + #[inline(always)] + pub fn cf13(&self) -> CF13_R { + CF13_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Tx Buffer Cancellation Finished 14"] + #[inline(always)] + pub fn cf14(&self) -> CF14_R { + CF14_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Tx Buffer Cancellation Finished 15"] + #[inline(always)] + pub fn cf15(&self) -> CF15_R { + CF15_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Tx Buffer Cancellation Finished 16"] + #[inline(always)] + pub fn cf16(&self) -> CF16_R { + CF16_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Tx Buffer Cancellation Finished 17"] + #[inline(always)] + pub fn cf17(&self) -> CF17_R { + CF17_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Tx Buffer Cancellation Finished 18"] + #[inline(always)] + pub fn cf18(&self) -> CF18_R { + CF18_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Tx Buffer Cancellation Finished 19"] + #[inline(always)] + pub fn cf19(&self) -> CF19_R { + CF19_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Tx Buffer Cancellation Finished 20"] + #[inline(always)] + pub fn cf20(&self) -> CF20_R { + CF20_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Tx Buffer Cancellation Finished 21"] + #[inline(always)] + pub fn cf21(&self) -> CF21_R { + CF21_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Tx Buffer Cancellation Finished 22"] + #[inline(always)] + pub fn cf22(&self) -> CF22_R { + CF22_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Tx Buffer Cancellation Finished 23"] + #[inline(always)] + pub fn cf23(&self) -> CF23_R { + CF23_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24 - Tx Buffer Cancellation Finished 24"] + #[inline(always)] + pub fn cf24(&self) -> CF24_R { + CF24_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Tx Buffer Cancellation Finished 25"] + #[inline(always)] + pub fn cf25(&self) -> CF25_R { + CF25_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Tx Buffer Cancellation Finished 26"] + #[inline(always)] + pub fn cf26(&self) -> CF26_R { + CF26_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Tx Buffer Cancellation Finished 27"] + #[inline(always)] + pub fn cf27(&self) -> CF27_R { + CF27_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28 - Tx Buffer Cancellation Finished 28"] + #[inline(always)] + pub fn cf28(&self) -> CF28_R { + CF28_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Tx Buffer Cancellation Finished 29"] + #[inline(always)] + pub fn cf29(&self) -> CF29_R { + CF29_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - Tx Buffer Cancellation Finished 30"] + #[inline(always)] + pub fn cf30(&self) -> CF30_R { + CF30_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 31 - Tx Buffer Cancellation Finished 31"] + #[inline(always)] + pub fn cf31(&self) -> CF31_R { + CF31_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +#[doc = "Tx Buffer Cancellation Finished\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txbcf](index.html) module"] +pub struct TXBCF_SPEC; +impl crate::RegisterSpec for TXBCF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [txbcf::R](R) reader structure"] +impl crate::Readable for TXBCF_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets TXBCF to value 0"] +impl crate::Resettable for TXBCF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/can0/txbcie.rs b/pac/atsamc21g/src/can0/txbcie.rs new file mode 100644 index 000000000000..ca0c9c0a2822 --- /dev/null +++ b/pac/atsamc21g/src/can0/txbcie.rs @@ -0,0 +1,1570 @@ +#[doc = "Register `TXBCIE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TXBCIE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CFIE0` reader - Cancellation Finished Interrupt Enable 0"] +pub struct CFIE0_R(crate::FieldReader); +impl CFIE0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE0` writer - Cancellation Finished Interrupt Enable 0"] +pub struct CFIE0_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `CFIE1` reader - Cancellation Finished Interrupt Enable 1"] +pub struct CFIE1_R(crate::FieldReader); +impl CFIE1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE1` writer - Cancellation Finished Interrupt Enable 1"] +pub struct CFIE1_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CFIE2` reader - Cancellation Finished Interrupt Enable 2"] +pub struct CFIE2_R(crate::FieldReader); +impl CFIE2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE2` writer - Cancellation Finished Interrupt Enable 2"] +pub struct CFIE2_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CFIE3` reader - Cancellation Finished Interrupt Enable 3"] +pub struct CFIE3_R(crate::FieldReader); +impl CFIE3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE3` writer - Cancellation Finished Interrupt Enable 3"] +pub struct CFIE3_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CFIE4` reader - Cancellation Finished Interrupt Enable 4"] +pub struct CFIE4_R(crate::FieldReader); +impl CFIE4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE4` writer - Cancellation Finished Interrupt Enable 4"] +pub struct CFIE4_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `CFIE5` reader - Cancellation Finished Interrupt Enable 5"] +pub struct CFIE5_R(crate::FieldReader); +impl CFIE5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE5` writer - Cancellation Finished Interrupt Enable 5"] +pub struct CFIE5_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `CFIE6` reader - Cancellation Finished Interrupt Enable 6"] +pub struct CFIE6_R(crate::FieldReader); +impl CFIE6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE6` writer - Cancellation Finished Interrupt Enable 6"] +pub struct CFIE6_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `CFIE7` reader - Cancellation Finished Interrupt Enable 7"] +pub struct CFIE7_R(crate::FieldReader); +impl CFIE7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE7` writer - Cancellation Finished Interrupt Enable 7"] +pub struct CFIE7_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CFIE8` reader - Cancellation Finished Interrupt Enable 8"] +pub struct CFIE8_R(crate::FieldReader); +impl CFIE8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE8` writer - Cancellation Finished Interrupt Enable 8"] +pub struct CFIE8_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `CFIE9` reader - Cancellation Finished Interrupt Enable 9"] +pub struct CFIE9_R(crate::FieldReader); +impl CFIE9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE9` writer - Cancellation Finished Interrupt Enable 9"] +pub struct CFIE9_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `CFIE10` reader - Cancellation Finished Interrupt Enable 10"] +pub struct CFIE10_R(crate::FieldReader); +impl CFIE10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE10` writer - Cancellation Finished Interrupt Enable 10"] +pub struct CFIE10_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `CFIE11` reader - Cancellation Finished Interrupt Enable 11"] +pub struct CFIE11_R(crate::FieldReader); +impl CFIE11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE11` writer - Cancellation Finished Interrupt Enable 11"] +pub struct CFIE11_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `CFIE12` reader - Cancellation Finished Interrupt Enable 12"] +pub struct CFIE12_R(crate::FieldReader); +impl CFIE12_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE12_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE12_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE12` writer - Cancellation Finished Interrupt Enable 12"] +pub struct CFIE12_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE12_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `CFIE13` reader - Cancellation Finished Interrupt Enable 13"] +pub struct CFIE13_R(crate::FieldReader); +impl CFIE13_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE13_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE13_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE13` writer - Cancellation Finished Interrupt Enable 13"] +pub struct CFIE13_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE13_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `CFIE14` reader - Cancellation Finished Interrupt Enable 14"] +pub struct CFIE14_R(crate::FieldReader); +impl CFIE14_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE14_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE14_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE14` writer - Cancellation Finished Interrupt Enable 14"] +pub struct CFIE14_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE14_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `CFIE15` reader - Cancellation Finished Interrupt Enable 15"] +pub struct CFIE15_R(crate::FieldReader); +impl CFIE15_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE15_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE15_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE15` writer - Cancellation Finished Interrupt Enable 15"] +pub struct CFIE15_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE15_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `CFIE16` reader - Cancellation Finished Interrupt Enable 16"] +pub struct CFIE16_R(crate::FieldReader); +impl CFIE16_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE16_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE16_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE16` writer - Cancellation Finished Interrupt Enable 16"] +pub struct CFIE16_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE16_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `CFIE17` reader - Cancellation Finished Interrupt Enable 17"] +pub struct CFIE17_R(crate::FieldReader); +impl CFIE17_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE17_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE17_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE17` writer - Cancellation Finished Interrupt Enable 17"] +pub struct CFIE17_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE17_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `CFIE18` reader - Cancellation Finished Interrupt Enable 18"] +pub struct CFIE18_R(crate::FieldReader); +impl CFIE18_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE18_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE18_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE18` writer - Cancellation Finished Interrupt Enable 18"] +pub struct CFIE18_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE18_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `CFIE19` reader - Cancellation Finished Interrupt Enable 19"] +pub struct CFIE19_R(crate::FieldReader); +impl CFIE19_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE19_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE19_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE19` writer - Cancellation Finished Interrupt Enable 19"] +pub struct CFIE19_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE19_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `CFIE20` reader - Cancellation Finished Interrupt Enable 20"] +pub struct CFIE20_R(crate::FieldReader); +impl CFIE20_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE20_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE20_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE20` writer - Cancellation Finished Interrupt Enable 20"] +pub struct CFIE20_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE20_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `CFIE21` reader - Cancellation Finished Interrupt Enable 21"] +pub struct CFIE21_R(crate::FieldReader); +impl CFIE21_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE21_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE21_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE21` writer - Cancellation Finished Interrupt Enable 21"] +pub struct CFIE21_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE21_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `CFIE22` reader - Cancellation Finished Interrupt Enable 22"] +pub struct CFIE22_R(crate::FieldReader); +impl CFIE22_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE22_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE22_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE22` writer - Cancellation Finished Interrupt Enable 22"] +pub struct CFIE22_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE22_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `CFIE23` reader - Cancellation Finished Interrupt Enable 23"] +pub struct CFIE23_R(crate::FieldReader); +impl CFIE23_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE23_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE23_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE23` writer - Cancellation Finished Interrupt Enable 23"] +pub struct CFIE23_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE23_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `CFIE24` reader - Cancellation Finished Interrupt Enable 24"] +pub struct CFIE24_R(crate::FieldReader); +impl CFIE24_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE24_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE24_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE24` writer - Cancellation Finished Interrupt Enable 24"] +pub struct CFIE24_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE24_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `CFIE25` reader - Cancellation Finished Interrupt Enable 25"] +pub struct CFIE25_R(crate::FieldReader); +impl CFIE25_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE25_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE25_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE25` writer - Cancellation Finished Interrupt Enable 25"] +pub struct CFIE25_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE25_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `CFIE26` reader - Cancellation Finished Interrupt Enable 26"] +pub struct CFIE26_R(crate::FieldReader); +impl CFIE26_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE26_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE26_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE26` writer - Cancellation Finished Interrupt Enable 26"] +pub struct CFIE26_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE26_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `CFIE27` reader - Cancellation Finished Interrupt Enable 27"] +pub struct CFIE27_R(crate::FieldReader); +impl CFIE27_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE27_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE27_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE27` writer - Cancellation Finished Interrupt Enable 27"] +pub struct CFIE27_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE27_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +#[doc = "Field `CFIE28` reader - Cancellation Finished Interrupt Enable 28"] +pub struct CFIE28_R(crate::FieldReader); +impl CFIE28_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE28_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE28_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE28` writer - Cancellation Finished Interrupt Enable 28"] +pub struct CFIE28_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE28_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Field `CFIE29` reader - Cancellation Finished Interrupt Enable 29"] +pub struct CFIE29_R(crate::FieldReader); +impl CFIE29_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE29_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE29_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE29` writer - Cancellation Finished Interrupt Enable 29"] +pub struct CFIE29_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE29_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29); + self.w + } +} +#[doc = "Field `CFIE30` reader - Cancellation Finished Interrupt Enable 30"] +pub struct CFIE30_R(crate::FieldReader); +impl CFIE30_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE30_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE30_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE30` writer - Cancellation Finished Interrupt Enable 30"] +pub struct CFIE30_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE30_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +#[doc = "Field `CFIE31` reader - Cancellation Finished Interrupt Enable 31"] +pub struct CFIE31_R(crate::FieldReader); +impl CFIE31_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE31_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE31_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE31` writer - Cancellation Finished Interrupt Enable 31"] +pub struct CFIE31_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE31_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bit 0 - Cancellation Finished Interrupt Enable 0"] + #[inline(always)] + pub fn cfie0(&self) -> CFIE0_R { + CFIE0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Cancellation Finished Interrupt Enable 1"] + #[inline(always)] + pub fn cfie1(&self) -> CFIE1_R { + CFIE1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Cancellation Finished Interrupt Enable 2"] + #[inline(always)] + pub fn cfie2(&self) -> CFIE2_R { + CFIE2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Cancellation Finished Interrupt Enable 3"] + #[inline(always)] + pub fn cfie3(&self) -> CFIE3_R { + CFIE3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Cancellation Finished Interrupt Enable 4"] + #[inline(always)] + pub fn cfie4(&self) -> CFIE4_R { + CFIE4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Cancellation Finished Interrupt Enable 5"] + #[inline(always)] + pub fn cfie5(&self) -> CFIE5_R { + CFIE5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Cancellation Finished Interrupt Enable 6"] + #[inline(always)] + pub fn cfie6(&self) -> CFIE6_R { + CFIE6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Cancellation Finished Interrupt Enable 7"] + #[inline(always)] + pub fn cfie7(&self) -> CFIE7_R { + CFIE7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Cancellation Finished Interrupt Enable 8"] + #[inline(always)] + pub fn cfie8(&self) -> CFIE8_R { + CFIE8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Cancellation Finished Interrupt Enable 9"] + #[inline(always)] + pub fn cfie9(&self) -> CFIE9_R { + CFIE9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Cancellation Finished Interrupt Enable 10"] + #[inline(always)] + pub fn cfie10(&self) -> CFIE10_R { + CFIE10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Cancellation Finished Interrupt Enable 11"] + #[inline(always)] + pub fn cfie11(&self) -> CFIE11_R { + CFIE11_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Cancellation Finished Interrupt Enable 12"] + #[inline(always)] + pub fn cfie12(&self) -> CFIE12_R { + CFIE12_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Cancellation Finished Interrupt Enable 13"] + #[inline(always)] + pub fn cfie13(&self) -> CFIE13_R { + CFIE13_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Cancellation Finished Interrupt Enable 14"] + #[inline(always)] + pub fn cfie14(&self) -> CFIE14_R { + CFIE14_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Cancellation Finished Interrupt Enable 15"] + #[inline(always)] + pub fn cfie15(&self) -> CFIE15_R { + CFIE15_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Cancellation Finished Interrupt Enable 16"] + #[inline(always)] + pub fn cfie16(&self) -> CFIE16_R { + CFIE16_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Cancellation Finished Interrupt Enable 17"] + #[inline(always)] + pub fn cfie17(&self) -> CFIE17_R { + CFIE17_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Cancellation Finished Interrupt Enable 18"] + #[inline(always)] + pub fn cfie18(&self) -> CFIE18_R { + CFIE18_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Cancellation Finished Interrupt Enable 19"] + #[inline(always)] + pub fn cfie19(&self) -> CFIE19_R { + CFIE19_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Cancellation Finished Interrupt Enable 20"] + #[inline(always)] + pub fn cfie20(&self) -> CFIE20_R { + CFIE20_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Cancellation Finished Interrupt Enable 21"] + #[inline(always)] + pub fn cfie21(&self) -> CFIE21_R { + CFIE21_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Cancellation Finished Interrupt Enable 22"] + #[inline(always)] + pub fn cfie22(&self) -> CFIE22_R { + CFIE22_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Cancellation Finished Interrupt Enable 23"] + #[inline(always)] + pub fn cfie23(&self) -> CFIE23_R { + CFIE23_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24 - Cancellation Finished Interrupt Enable 24"] + #[inline(always)] + pub fn cfie24(&self) -> CFIE24_R { + CFIE24_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Cancellation Finished Interrupt Enable 25"] + #[inline(always)] + pub fn cfie25(&self) -> CFIE25_R { + CFIE25_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Cancellation Finished Interrupt Enable 26"] + #[inline(always)] + pub fn cfie26(&self) -> CFIE26_R { + CFIE26_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Cancellation Finished Interrupt Enable 27"] + #[inline(always)] + pub fn cfie27(&self) -> CFIE27_R { + CFIE27_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28 - Cancellation Finished Interrupt Enable 28"] + #[inline(always)] + pub fn cfie28(&self) -> CFIE28_R { + CFIE28_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Cancellation Finished Interrupt Enable 29"] + #[inline(always)] + pub fn cfie29(&self) -> CFIE29_R { + CFIE29_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - Cancellation Finished Interrupt Enable 30"] + #[inline(always)] + pub fn cfie30(&self) -> CFIE30_R { + CFIE30_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 31 - Cancellation Finished Interrupt Enable 31"] + #[inline(always)] + pub fn cfie31(&self) -> CFIE31_R { + CFIE31_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Cancellation Finished Interrupt Enable 0"] + #[inline(always)] + pub fn cfie0(&mut self) -> CFIE0_W { + CFIE0_W { w: self } + } + #[doc = "Bit 1 - Cancellation Finished Interrupt Enable 1"] + #[inline(always)] + pub fn cfie1(&mut self) -> CFIE1_W { + CFIE1_W { w: self } + } + #[doc = "Bit 2 - Cancellation Finished Interrupt Enable 2"] + #[inline(always)] + pub fn cfie2(&mut self) -> CFIE2_W { + CFIE2_W { w: self } + } + #[doc = "Bit 3 - Cancellation Finished Interrupt Enable 3"] + #[inline(always)] + pub fn cfie3(&mut self) -> CFIE3_W { + CFIE3_W { w: self } + } + #[doc = "Bit 4 - Cancellation Finished Interrupt Enable 4"] + #[inline(always)] + pub fn cfie4(&mut self) -> CFIE4_W { + CFIE4_W { w: self } + } + #[doc = "Bit 5 - Cancellation Finished Interrupt Enable 5"] + #[inline(always)] + pub fn cfie5(&mut self) -> CFIE5_W { + CFIE5_W { w: self } + } + #[doc = "Bit 6 - Cancellation Finished Interrupt Enable 6"] + #[inline(always)] + pub fn cfie6(&mut self) -> CFIE6_W { + CFIE6_W { w: self } + } + #[doc = "Bit 7 - Cancellation Finished Interrupt Enable 7"] + #[inline(always)] + pub fn cfie7(&mut self) -> CFIE7_W { + CFIE7_W { w: self } + } + #[doc = "Bit 8 - Cancellation Finished Interrupt Enable 8"] + #[inline(always)] + pub fn cfie8(&mut self) -> CFIE8_W { + CFIE8_W { w: self } + } + #[doc = "Bit 9 - Cancellation Finished Interrupt Enable 9"] + #[inline(always)] + pub fn cfie9(&mut self) -> CFIE9_W { + CFIE9_W { w: self } + } + #[doc = "Bit 10 - Cancellation Finished Interrupt Enable 10"] + #[inline(always)] + pub fn cfie10(&mut self) -> CFIE10_W { + CFIE10_W { w: self } + } + #[doc = "Bit 11 - Cancellation Finished Interrupt Enable 11"] + #[inline(always)] + pub fn cfie11(&mut self) -> CFIE11_W { + CFIE11_W { w: self } + } + #[doc = "Bit 12 - Cancellation Finished Interrupt Enable 12"] + #[inline(always)] + pub fn cfie12(&mut self) -> CFIE12_W { + CFIE12_W { w: self } + } + #[doc = "Bit 13 - Cancellation Finished Interrupt Enable 13"] + #[inline(always)] + pub fn cfie13(&mut self) -> CFIE13_W { + CFIE13_W { w: self } + } + #[doc = "Bit 14 - Cancellation Finished Interrupt Enable 14"] + #[inline(always)] + pub fn cfie14(&mut self) -> CFIE14_W { + CFIE14_W { w: self } + } + #[doc = "Bit 15 - Cancellation Finished Interrupt Enable 15"] + #[inline(always)] + pub fn cfie15(&mut self) -> CFIE15_W { + CFIE15_W { w: self } + } + #[doc = "Bit 16 - Cancellation Finished Interrupt Enable 16"] + #[inline(always)] + pub fn cfie16(&mut self) -> CFIE16_W { + CFIE16_W { w: self } + } + #[doc = "Bit 17 - Cancellation Finished Interrupt Enable 17"] + #[inline(always)] + pub fn cfie17(&mut self) -> CFIE17_W { + CFIE17_W { w: self } + } + #[doc = "Bit 18 - Cancellation Finished Interrupt Enable 18"] + #[inline(always)] + pub fn cfie18(&mut self) -> CFIE18_W { + CFIE18_W { w: self } + } + #[doc = "Bit 19 - Cancellation Finished Interrupt Enable 19"] + #[inline(always)] + pub fn cfie19(&mut self) -> CFIE19_W { + CFIE19_W { w: self } + } + #[doc = "Bit 20 - Cancellation Finished Interrupt Enable 20"] + #[inline(always)] + pub fn cfie20(&mut self) -> CFIE20_W { + CFIE20_W { w: self } + } + #[doc = "Bit 21 - Cancellation Finished Interrupt Enable 21"] + #[inline(always)] + pub fn cfie21(&mut self) -> CFIE21_W { + CFIE21_W { w: self } + } + #[doc = "Bit 22 - Cancellation Finished Interrupt Enable 22"] + #[inline(always)] + pub fn cfie22(&mut self) -> CFIE22_W { + CFIE22_W { w: self } + } + #[doc = "Bit 23 - Cancellation Finished Interrupt Enable 23"] + #[inline(always)] + pub fn cfie23(&mut self) -> CFIE23_W { + CFIE23_W { w: self } + } + #[doc = "Bit 24 - Cancellation Finished Interrupt Enable 24"] + #[inline(always)] + pub fn cfie24(&mut self) -> CFIE24_W { + CFIE24_W { w: self } + } + #[doc = "Bit 25 - Cancellation Finished Interrupt Enable 25"] + #[inline(always)] + pub fn cfie25(&mut self) -> CFIE25_W { + CFIE25_W { w: self } + } + #[doc = "Bit 26 - Cancellation Finished Interrupt Enable 26"] + #[inline(always)] + pub fn cfie26(&mut self) -> CFIE26_W { + CFIE26_W { w: self } + } + #[doc = "Bit 27 - Cancellation Finished Interrupt Enable 27"] + #[inline(always)] + pub fn cfie27(&mut self) -> CFIE27_W { + CFIE27_W { w: self } + } + #[doc = "Bit 28 - Cancellation Finished Interrupt Enable 28"] + #[inline(always)] + pub fn cfie28(&mut self) -> CFIE28_W { + CFIE28_W { w: self } + } + #[doc = "Bit 29 - Cancellation Finished Interrupt Enable 29"] + #[inline(always)] + pub fn cfie29(&mut self) -> CFIE29_W { + CFIE29_W { w: self } + } + #[doc = "Bit 30 - Cancellation Finished Interrupt Enable 30"] + #[inline(always)] + pub fn cfie30(&mut self) -> CFIE30_W { + CFIE30_W { w: self } + } + #[doc = "Bit 31 - Cancellation Finished Interrupt Enable 31"] + #[inline(always)] + pub fn cfie31(&mut self) -> CFIE31_W { + CFIE31_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Tx Buffer Cancellation Finished Interrupt Enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txbcie](index.html) module"] +pub struct TXBCIE_SPEC; +impl crate::RegisterSpec for TXBCIE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [txbcie::R](R) reader structure"] +impl crate::Readable for TXBCIE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [txbcie::W](W) writer structure"] +impl crate::Writable for TXBCIE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TXBCIE to value 0"] +impl crate::Resettable for TXBCIE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/can0/txbcr.rs b/pac/atsamc21g/src/can0/txbcr.rs new file mode 100644 index 000000000000..e5d0e61de8c9 --- /dev/null +++ b/pac/atsamc21g/src/can0/txbcr.rs @@ -0,0 +1,1570 @@ +#[doc = "Register `TXBCR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TXBCR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CR0` reader - Cancellation Request 0"] +pub struct CR0_R(crate::FieldReader); +impl CR0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR0` writer - Cancellation Request 0"] +pub struct CR0_W<'a> { + w: &'a mut W, +} +impl<'a> CR0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `CR1` reader - Cancellation Request 1"] +pub struct CR1_R(crate::FieldReader); +impl CR1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR1` writer - Cancellation Request 1"] +pub struct CR1_W<'a> { + w: &'a mut W, +} +impl<'a> CR1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CR2` reader - Cancellation Request 2"] +pub struct CR2_R(crate::FieldReader); +impl CR2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR2` writer - Cancellation Request 2"] +pub struct CR2_W<'a> { + w: &'a mut W, +} +impl<'a> CR2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CR3` reader - Cancellation Request 3"] +pub struct CR3_R(crate::FieldReader); +impl CR3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR3` writer - Cancellation Request 3"] +pub struct CR3_W<'a> { + w: &'a mut W, +} +impl<'a> CR3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CR4` reader - Cancellation Request 4"] +pub struct CR4_R(crate::FieldReader); +impl CR4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR4` writer - Cancellation Request 4"] +pub struct CR4_W<'a> { + w: &'a mut W, +} +impl<'a> CR4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `CR5` reader - Cancellation Request 5"] +pub struct CR5_R(crate::FieldReader); +impl CR5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR5` writer - Cancellation Request 5"] +pub struct CR5_W<'a> { + w: &'a mut W, +} +impl<'a> CR5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `CR6` reader - Cancellation Request 6"] +pub struct CR6_R(crate::FieldReader); +impl CR6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR6` writer - Cancellation Request 6"] +pub struct CR6_W<'a> { + w: &'a mut W, +} +impl<'a> CR6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `CR7` reader - Cancellation Request 7"] +pub struct CR7_R(crate::FieldReader); +impl CR7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR7` writer - Cancellation Request 7"] +pub struct CR7_W<'a> { + w: &'a mut W, +} +impl<'a> CR7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CR8` reader - Cancellation Request 8"] +pub struct CR8_R(crate::FieldReader); +impl CR8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR8` writer - Cancellation Request 8"] +pub struct CR8_W<'a> { + w: &'a mut W, +} +impl<'a> CR8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `CR9` reader - Cancellation Request 9"] +pub struct CR9_R(crate::FieldReader); +impl CR9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR9` writer - Cancellation Request 9"] +pub struct CR9_W<'a> { + w: &'a mut W, +} +impl<'a> CR9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `CR10` reader - Cancellation Request 10"] +pub struct CR10_R(crate::FieldReader); +impl CR10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR10` writer - Cancellation Request 10"] +pub struct CR10_W<'a> { + w: &'a mut W, +} +impl<'a> CR10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `CR11` reader - Cancellation Request 11"] +pub struct CR11_R(crate::FieldReader); +impl CR11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR11` writer - Cancellation Request 11"] +pub struct CR11_W<'a> { + w: &'a mut W, +} +impl<'a> CR11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `CR12` reader - Cancellation Request 12"] +pub struct CR12_R(crate::FieldReader); +impl CR12_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR12_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR12_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR12` writer - Cancellation Request 12"] +pub struct CR12_W<'a> { + w: &'a mut W, +} +impl<'a> CR12_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `CR13` reader - Cancellation Request 13"] +pub struct CR13_R(crate::FieldReader); +impl CR13_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR13_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR13_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR13` writer - Cancellation Request 13"] +pub struct CR13_W<'a> { + w: &'a mut W, +} +impl<'a> CR13_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `CR14` reader - Cancellation Request 14"] +pub struct CR14_R(crate::FieldReader); +impl CR14_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR14_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR14_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR14` writer - Cancellation Request 14"] +pub struct CR14_W<'a> { + w: &'a mut W, +} +impl<'a> CR14_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `CR15` reader - Cancellation Request 15"] +pub struct CR15_R(crate::FieldReader); +impl CR15_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR15_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR15_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR15` writer - Cancellation Request 15"] +pub struct CR15_W<'a> { + w: &'a mut W, +} +impl<'a> CR15_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `CR16` reader - Cancellation Request 16"] +pub struct CR16_R(crate::FieldReader); +impl CR16_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR16_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR16_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR16` writer - Cancellation Request 16"] +pub struct CR16_W<'a> { + w: &'a mut W, +} +impl<'a> CR16_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `CR17` reader - Cancellation Request 17"] +pub struct CR17_R(crate::FieldReader); +impl CR17_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR17_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR17_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR17` writer - Cancellation Request 17"] +pub struct CR17_W<'a> { + w: &'a mut W, +} +impl<'a> CR17_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `CR18` reader - Cancellation Request 18"] +pub struct CR18_R(crate::FieldReader); +impl CR18_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR18_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR18_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR18` writer - Cancellation Request 18"] +pub struct CR18_W<'a> { + w: &'a mut W, +} +impl<'a> CR18_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `CR19` reader - Cancellation Request 19"] +pub struct CR19_R(crate::FieldReader); +impl CR19_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR19_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR19_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR19` writer - Cancellation Request 19"] +pub struct CR19_W<'a> { + w: &'a mut W, +} +impl<'a> CR19_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `CR20` reader - Cancellation Request 20"] +pub struct CR20_R(crate::FieldReader); +impl CR20_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR20_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR20_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR20` writer - Cancellation Request 20"] +pub struct CR20_W<'a> { + w: &'a mut W, +} +impl<'a> CR20_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `CR21` reader - Cancellation Request 21"] +pub struct CR21_R(crate::FieldReader); +impl CR21_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR21_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR21_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR21` writer - Cancellation Request 21"] +pub struct CR21_W<'a> { + w: &'a mut W, +} +impl<'a> CR21_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `CR22` reader - Cancellation Request 22"] +pub struct CR22_R(crate::FieldReader); +impl CR22_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR22_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR22_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR22` writer - Cancellation Request 22"] +pub struct CR22_W<'a> { + w: &'a mut W, +} +impl<'a> CR22_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `CR23` reader - Cancellation Request 23"] +pub struct CR23_R(crate::FieldReader); +impl CR23_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR23_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR23_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR23` writer - Cancellation Request 23"] +pub struct CR23_W<'a> { + w: &'a mut W, +} +impl<'a> CR23_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `CR24` reader - Cancellation Request 24"] +pub struct CR24_R(crate::FieldReader); +impl CR24_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR24_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR24_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR24` writer - Cancellation Request 24"] +pub struct CR24_W<'a> { + w: &'a mut W, +} +impl<'a> CR24_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `CR25` reader - Cancellation Request 25"] +pub struct CR25_R(crate::FieldReader); +impl CR25_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR25_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR25_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR25` writer - Cancellation Request 25"] +pub struct CR25_W<'a> { + w: &'a mut W, +} +impl<'a> CR25_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `CR26` reader - Cancellation Request 26"] +pub struct CR26_R(crate::FieldReader); +impl CR26_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR26_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR26_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR26` writer - Cancellation Request 26"] +pub struct CR26_W<'a> { + w: &'a mut W, +} +impl<'a> CR26_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `CR27` reader - Cancellation Request 27"] +pub struct CR27_R(crate::FieldReader); +impl CR27_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR27_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR27_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR27` writer - Cancellation Request 27"] +pub struct CR27_W<'a> { + w: &'a mut W, +} +impl<'a> CR27_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +#[doc = "Field `CR28` reader - Cancellation Request 28"] +pub struct CR28_R(crate::FieldReader); +impl CR28_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR28_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR28_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR28` writer - Cancellation Request 28"] +pub struct CR28_W<'a> { + w: &'a mut W, +} +impl<'a> CR28_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Field `CR29` reader - Cancellation Request 29"] +pub struct CR29_R(crate::FieldReader); +impl CR29_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR29_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR29_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR29` writer - Cancellation Request 29"] +pub struct CR29_W<'a> { + w: &'a mut W, +} +impl<'a> CR29_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29); + self.w + } +} +#[doc = "Field `CR30` reader - Cancellation Request 30"] +pub struct CR30_R(crate::FieldReader); +impl CR30_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR30_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR30_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR30` writer - Cancellation Request 30"] +pub struct CR30_W<'a> { + w: &'a mut W, +} +impl<'a> CR30_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +#[doc = "Field `CR31` reader - Cancellation Request 31"] +pub struct CR31_R(crate::FieldReader); +impl CR31_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR31_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR31_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR31` writer - Cancellation Request 31"] +pub struct CR31_W<'a> { + w: &'a mut W, +} +impl<'a> CR31_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bit 0 - Cancellation Request 0"] + #[inline(always)] + pub fn cr0(&self) -> CR0_R { + CR0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Cancellation Request 1"] + #[inline(always)] + pub fn cr1(&self) -> CR1_R { + CR1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Cancellation Request 2"] + #[inline(always)] + pub fn cr2(&self) -> CR2_R { + CR2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Cancellation Request 3"] + #[inline(always)] + pub fn cr3(&self) -> CR3_R { + CR3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Cancellation Request 4"] + #[inline(always)] + pub fn cr4(&self) -> CR4_R { + CR4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Cancellation Request 5"] + #[inline(always)] + pub fn cr5(&self) -> CR5_R { + CR5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Cancellation Request 6"] + #[inline(always)] + pub fn cr6(&self) -> CR6_R { + CR6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Cancellation Request 7"] + #[inline(always)] + pub fn cr7(&self) -> CR7_R { + CR7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Cancellation Request 8"] + #[inline(always)] + pub fn cr8(&self) -> CR8_R { + CR8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Cancellation Request 9"] + #[inline(always)] + pub fn cr9(&self) -> CR9_R { + CR9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Cancellation Request 10"] + #[inline(always)] + pub fn cr10(&self) -> CR10_R { + CR10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Cancellation Request 11"] + #[inline(always)] + pub fn cr11(&self) -> CR11_R { + CR11_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Cancellation Request 12"] + #[inline(always)] + pub fn cr12(&self) -> CR12_R { + CR12_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Cancellation Request 13"] + #[inline(always)] + pub fn cr13(&self) -> CR13_R { + CR13_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Cancellation Request 14"] + #[inline(always)] + pub fn cr14(&self) -> CR14_R { + CR14_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Cancellation Request 15"] + #[inline(always)] + pub fn cr15(&self) -> CR15_R { + CR15_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Cancellation Request 16"] + #[inline(always)] + pub fn cr16(&self) -> CR16_R { + CR16_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Cancellation Request 17"] + #[inline(always)] + pub fn cr17(&self) -> CR17_R { + CR17_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Cancellation Request 18"] + #[inline(always)] + pub fn cr18(&self) -> CR18_R { + CR18_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Cancellation Request 19"] + #[inline(always)] + pub fn cr19(&self) -> CR19_R { + CR19_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Cancellation Request 20"] + #[inline(always)] + pub fn cr20(&self) -> CR20_R { + CR20_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Cancellation Request 21"] + #[inline(always)] + pub fn cr21(&self) -> CR21_R { + CR21_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Cancellation Request 22"] + #[inline(always)] + pub fn cr22(&self) -> CR22_R { + CR22_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Cancellation Request 23"] + #[inline(always)] + pub fn cr23(&self) -> CR23_R { + CR23_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24 - Cancellation Request 24"] + #[inline(always)] + pub fn cr24(&self) -> CR24_R { + CR24_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Cancellation Request 25"] + #[inline(always)] + pub fn cr25(&self) -> CR25_R { + CR25_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Cancellation Request 26"] + #[inline(always)] + pub fn cr26(&self) -> CR26_R { + CR26_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Cancellation Request 27"] + #[inline(always)] + pub fn cr27(&self) -> CR27_R { + CR27_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28 - Cancellation Request 28"] + #[inline(always)] + pub fn cr28(&self) -> CR28_R { + CR28_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Cancellation Request 29"] + #[inline(always)] + pub fn cr29(&self) -> CR29_R { + CR29_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - Cancellation Request 30"] + #[inline(always)] + pub fn cr30(&self) -> CR30_R { + CR30_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 31 - Cancellation Request 31"] + #[inline(always)] + pub fn cr31(&self) -> CR31_R { + CR31_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Cancellation Request 0"] + #[inline(always)] + pub fn cr0(&mut self) -> CR0_W { + CR0_W { w: self } + } + #[doc = "Bit 1 - Cancellation Request 1"] + #[inline(always)] + pub fn cr1(&mut self) -> CR1_W { + CR1_W { w: self } + } + #[doc = "Bit 2 - Cancellation Request 2"] + #[inline(always)] + pub fn cr2(&mut self) -> CR2_W { + CR2_W { w: self } + } + #[doc = "Bit 3 - Cancellation Request 3"] + #[inline(always)] + pub fn cr3(&mut self) -> CR3_W { + CR3_W { w: self } + } + #[doc = "Bit 4 - Cancellation Request 4"] + #[inline(always)] + pub fn cr4(&mut self) -> CR4_W { + CR4_W { w: self } + } + #[doc = "Bit 5 - Cancellation Request 5"] + #[inline(always)] + pub fn cr5(&mut self) -> CR5_W { + CR5_W { w: self } + } + #[doc = "Bit 6 - Cancellation Request 6"] + #[inline(always)] + pub fn cr6(&mut self) -> CR6_W { + CR6_W { w: self } + } + #[doc = "Bit 7 - Cancellation Request 7"] + #[inline(always)] + pub fn cr7(&mut self) -> CR7_W { + CR7_W { w: self } + } + #[doc = "Bit 8 - Cancellation Request 8"] + #[inline(always)] + pub fn cr8(&mut self) -> CR8_W { + CR8_W { w: self } + } + #[doc = "Bit 9 - Cancellation Request 9"] + #[inline(always)] + pub fn cr9(&mut self) -> CR9_W { + CR9_W { w: self } + } + #[doc = "Bit 10 - Cancellation Request 10"] + #[inline(always)] + pub fn cr10(&mut self) -> CR10_W { + CR10_W { w: self } + } + #[doc = "Bit 11 - Cancellation Request 11"] + #[inline(always)] + pub fn cr11(&mut self) -> CR11_W { + CR11_W { w: self } + } + #[doc = "Bit 12 - Cancellation Request 12"] + #[inline(always)] + pub fn cr12(&mut self) -> CR12_W { + CR12_W { w: self } + } + #[doc = "Bit 13 - Cancellation Request 13"] + #[inline(always)] + pub fn cr13(&mut self) -> CR13_W { + CR13_W { w: self } + } + #[doc = "Bit 14 - Cancellation Request 14"] + #[inline(always)] + pub fn cr14(&mut self) -> CR14_W { + CR14_W { w: self } + } + #[doc = "Bit 15 - Cancellation Request 15"] + #[inline(always)] + pub fn cr15(&mut self) -> CR15_W { + CR15_W { w: self } + } + #[doc = "Bit 16 - Cancellation Request 16"] + #[inline(always)] + pub fn cr16(&mut self) -> CR16_W { + CR16_W { w: self } + } + #[doc = "Bit 17 - Cancellation Request 17"] + #[inline(always)] + pub fn cr17(&mut self) -> CR17_W { + CR17_W { w: self } + } + #[doc = "Bit 18 - Cancellation Request 18"] + #[inline(always)] + pub fn cr18(&mut self) -> CR18_W { + CR18_W { w: self } + } + #[doc = "Bit 19 - Cancellation Request 19"] + #[inline(always)] + pub fn cr19(&mut self) -> CR19_W { + CR19_W { w: self } + } + #[doc = "Bit 20 - Cancellation Request 20"] + #[inline(always)] + pub fn cr20(&mut self) -> CR20_W { + CR20_W { w: self } + } + #[doc = "Bit 21 - Cancellation Request 21"] + #[inline(always)] + pub fn cr21(&mut self) -> CR21_W { + CR21_W { w: self } + } + #[doc = "Bit 22 - Cancellation Request 22"] + #[inline(always)] + pub fn cr22(&mut self) -> CR22_W { + CR22_W { w: self } + } + #[doc = "Bit 23 - Cancellation Request 23"] + #[inline(always)] + pub fn cr23(&mut self) -> CR23_W { + CR23_W { w: self } + } + #[doc = "Bit 24 - Cancellation Request 24"] + #[inline(always)] + pub fn cr24(&mut self) -> CR24_W { + CR24_W { w: self } + } + #[doc = "Bit 25 - Cancellation Request 25"] + #[inline(always)] + pub fn cr25(&mut self) -> CR25_W { + CR25_W { w: self } + } + #[doc = "Bit 26 - Cancellation Request 26"] + #[inline(always)] + pub fn cr26(&mut self) -> CR26_W { + CR26_W { w: self } + } + #[doc = "Bit 27 - Cancellation Request 27"] + #[inline(always)] + pub fn cr27(&mut self) -> CR27_W { + CR27_W { w: self } + } + #[doc = "Bit 28 - Cancellation Request 28"] + #[inline(always)] + pub fn cr28(&mut self) -> CR28_W { + CR28_W { w: self } + } + #[doc = "Bit 29 - Cancellation Request 29"] + #[inline(always)] + pub fn cr29(&mut self) -> CR29_W { + CR29_W { w: self } + } + #[doc = "Bit 30 - Cancellation Request 30"] + #[inline(always)] + pub fn cr30(&mut self) -> CR30_W { + CR30_W { w: self } + } + #[doc = "Bit 31 - Cancellation Request 31"] + #[inline(always)] + pub fn cr31(&mut self) -> CR31_W { + CR31_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Tx Buffer Cancellation Request\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txbcr](index.html) module"] +pub struct TXBCR_SPEC; +impl crate::RegisterSpec for TXBCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [txbcr::R](R) reader structure"] +impl crate::Readable for TXBCR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [txbcr::W](W) writer structure"] +impl crate::Writable for TXBCR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TXBCR to value 0"] +impl crate::Resettable for TXBCR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/can0/txbrp.rs b/pac/atsamc21g/src/can0/txbrp.rs new file mode 100644 index 000000000000..9be5da39419d --- /dev/null +++ b/pac/atsamc21g/src/can0/txbrp.rs @@ -0,0 +1,673 @@ +#[doc = "Register `TXBRP` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `TRP0` reader - Transmission Request Pending 0"] +pub struct TRP0_R(crate::FieldReader); +impl TRP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP1` reader - Transmission Request Pending 1"] +pub struct TRP1_R(crate::FieldReader); +impl TRP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP2` reader - Transmission Request Pending 2"] +pub struct TRP2_R(crate::FieldReader); +impl TRP2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP3` reader - Transmission Request Pending 3"] +pub struct TRP3_R(crate::FieldReader); +impl TRP3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP4` reader - Transmission Request Pending 4"] +pub struct TRP4_R(crate::FieldReader); +impl TRP4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP5` reader - Transmission Request Pending 5"] +pub struct TRP5_R(crate::FieldReader); +impl TRP5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP6` reader - Transmission Request Pending 6"] +pub struct TRP6_R(crate::FieldReader); +impl TRP6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP7` reader - Transmission Request Pending 7"] +pub struct TRP7_R(crate::FieldReader); +impl TRP7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP8` reader - Transmission Request Pending 8"] +pub struct TRP8_R(crate::FieldReader); +impl TRP8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP9` reader - Transmission Request Pending 9"] +pub struct TRP9_R(crate::FieldReader); +impl TRP9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP10` reader - Transmission Request Pending 10"] +pub struct TRP10_R(crate::FieldReader); +impl TRP10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP11` reader - Transmission Request Pending 11"] +pub struct TRP11_R(crate::FieldReader); +impl TRP11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP12` reader - Transmission Request Pending 12"] +pub struct TRP12_R(crate::FieldReader); +impl TRP12_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP12_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP12_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP13` reader - Transmission Request Pending 13"] +pub struct TRP13_R(crate::FieldReader); +impl TRP13_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP13_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP13_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP14` reader - Transmission Request Pending 14"] +pub struct TRP14_R(crate::FieldReader); +impl TRP14_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP14_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP14_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP15` reader - Transmission Request Pending 15"] +pub struct TRP15_R(crate::FieldReader); +impl TRP15_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP15_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP15_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP16` reader - Transmission Request Pending 16"] +pub struct TRP16_R(crate::FieldReader); +impl TRP16_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP16_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP16_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP17` reader - Transmission Request Pending 17"] +pub struct TRP17_R(crate::FieldReader); +impl TRP17_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP17_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP17_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP18` reader - Transmission Request Pending 18"] +pub struct TRP18_R(crate::FieldReader); +impl TRP18_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP18_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP18_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP19` reader - Transmission Request Pending 19"] +pub struct TRP19_R(crate::FieldReader); +impl TRP19_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP19_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP19_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP20` reader - Transmission Request Pending 20"] +pub struct TRP20_R(crate::FieldReader); +impl TRP20_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP20_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP20_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP21` reader - Transmission Request Pending 21"] +pub struct TRP21_R(crate::FieldReader); +impl TRP21_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP21_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP21_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP22` reader - Transmission Request Pending 22"] +pub struct TRP22_R(crate::FieldReader); +impl TRP22_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP22_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP22_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP23` reader - Transmission Request Pending 23"] +pub struct TRP23_R(crate::FieldReader); +impl TRP23_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP23_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP23_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP24` reader - Transmission Request Pending 24"] +pub struct TRP24_R(crate::FieldReader); +impl TRP24_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP24_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP24_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP25` reader - Transmission Request Pending 25"] +pub struct TRP25_R(crate::FieldReader); +impl TRP25_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP25_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP25_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP26` reader - Transmission Request Pending 26"] +pub struct TRP26_R(crate::FieldReader); +impl TRP26_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP26_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP26_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP27` reader - Transmission Request Pending 27"] +pub struct TRP27_R(crate::FieldReader); +impl TRP27_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP27_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP27_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP28` reader - Transmission Request Pending 28"] +pub struct TRP28_R(crate::FieldReader); +impl TRP28_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP28_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP28_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP29` reader - Transmission Request Pending 29"] +pub struct TRP29_R(crate::FieldReader); +impl TRP29_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP29_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP29_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP30` reader - Transmission Request Pending 30"] +pub struct TRP30_R(crate::FieldReader); +impl TRP30_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP30_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP30_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP31` reader - Transmission Request Pending 31"] +pub struct TRP31_R(crate::FieldReader); +impl TRP31_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP31_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP31_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Transmission Request Pending 0"] + #[inline(always)] + pub fn trp0(&self) -> TRP0_R { + TRP0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmission Request Pending 1"] + #[inline(always)] + pub fn trp1(&self) -> TRP1_R { + TRP1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Transmission Request Pending 2"] + #[inline(always)] + pub fn trp2(&self) -> TRP2_R { + TRP2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Transmission Request Pending 3"] + #[inline(always)] + pub fn trp3(&self) -> TRP3_R { + TRP3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Transmission Request Pending 4"] + #[inline(always)] + pub fn trp4(&self) -> TRP4_R { + TRP4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Transmission Request Pending 5"] + #[inline(always)] + pub fn trp5(&self) -> TRP5_R { + TRP5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Transmission Request Pending 6"] + #[inline(always)] + pub fn trp6(&self) -> TRP6_R { + TRP6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Transmission Request Pending 7"] + #[inline(always)] + pub fn trp7(&self) -> TRP7_R { + TRP7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Transmission Request Pending 8"] + #[inline(always)] + pub fn trp8(&self) -> TRP8_R { + TRP8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Transmission Request Pending 9"] + #[inline(always)] + pub fn trp9(&self) -> TRP9_R { + TRP9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Transmission Request Pending 10"] + #[inline(always)] + pub fn trp10(&self) -> TRP10_R { + TRP10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Transmission Request Pending 11"] + #[inline(always)] + pub fn trp11(&self) -> TRP11_R { + TRP11_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Transmission Request Pending 12"] + #[inline(always)] + pub fn trp12(&self) -> TRP12_R { + TRP12_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Transmission Request Pending 13"] + #[inline(always)] + pub fn trp13(&self) -> TRP13_R { + TRP13_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Transmission Request Pending 14"] + #[inline(always)] + pub fn trp14(&self) -> TRP14_R { + TRP14_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Transmission Request Pending 15"] + #[inline(always)] + pub fn trp15(&self) -> TRP15_R { + TRP15_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Transmission Request Pending 16"] + #[inline(always)] + pub fn trp16(&self) -> TRP16_R { + TRP16_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Transmission Request Pending 17"] + #[inline(always)] + pub fn trp17(&self) -> TRP17_R { + TRP17_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Transmission Request Pending 18"] + #[inline(always)] + pub fn trp18(&self) -> TRP18_R { + TRP18_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Transmission Request Pending 19"] + #[inline(always)] + pub fn trp19(&self) -> TRP19_R { + TRP19_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Transmission Request Pending 20"] + #[inline(always)] + pub fn trp20(&self) -> TRP20_R { + TRP20_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Transmission Request Pending 21"] + #[inline(always)] + pub fn trp21(&self) -> TRP21_R { + TRP21_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Transmission Request Pending 22"] + #[inline(always)] + pub fn trp22(&self) -> TRP22_R { + TRP22_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Transmission Request Pending 23"] + #[inline(always)] + pub fn trp23(&self) -> TRP23_R { + TRP23_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24 - Transmission Request Pending 24"] + #[inline(always)] + pub fn trp24(&self) -> TRP24_R { + TRP24_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Transmission Request Pending 25"] + #[inline(always)] + pub fn trp25(&self) -> TRP25_R { + TRP25_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Transmission Request Pending 26"] + #[inline(always)] + pub fn trp26(&self) -> TRP26_R { + TRP26_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Transmission Request Pending 27"] + #[inline(always)] + pub fn trp27(&self) -> TRP27_R { + TRP27_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28 - Transmission Request Pending 28"] + #[inline(always)] + pub fn trp28(&self) -> TRP28_R { + TRP28_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Transmission Request Pending 29"] + #[inline(always)] + pub fn trp29(&self) -> TRP29_R { + TRP29_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - Transmission Request Pending 30"] + #[inline(always)] + pub fn trp30(&self) -> TRP30_R { + TRP30_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 31 - Transmission Request Pending 31"] + #[inline(always)] + pub fn trp31(&self) -> TRP31_R { + TRP31_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +#[doc = "Tx Buffer Request Pending\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txbrp](index.html) module"] +pub struct TXBRP_SPEC; +impl crate::RegisterSpec for TXBRP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [txbrp::R](R) reader structure"] +impl crate::Readable for TXBRP_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets TXBRP to value 0"] +impl crate::Resettable for TXBRP_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/can0/txbtie.rs b/pac/atsamc21g/src/can0/txbtie.rs new file mode 100644 index 000000000000..ed808faba7a1 --- /dev/null +++ b/pac/atsamc21g/src/can0/txbtie.rs @@ -0,0 +1,1570 @@ +#[doc = "Register `TXBTIE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TXBTIE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TIE0` reader - Transmission Interrupt Enable 0"] +pub struct TIE0_R(crate::FieldReader); +impl TIE0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE0` writer - Transmission Interrupt Enable 0"] +pub struct TIE0_W<'a> { + w: &'a mut W, +} +impl<'a> TIE0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `TIE1` reader - Transmission Interrupt Enable 1"] +pub struct TIE1_R(crate::FieldReader); +impl TIE1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE1` writer - Transmission Interrupt Enable 1"] +pub struct TIE1_W<'a> { + w: &'a mut W, +} +impl<'a> TIE1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `TIE2` reader - Transmission Interrupt Enable 2"] +pub struct TIE2_R(crate::FieldReader); +impl TIE2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE2` writer - Transmission Interrupt Enable 2"] +pub struct TIE2_W<'a> { + w: &'a mut W, +} +impl<'a> TIE2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `TIE3` reader - Transmission Interrupt Enable 3"] +pub struct TIE3_R(crate::FieldReader); +impl TIE3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE3` writer - Transmission Interrupt Enable 3"] +pub struct TIE3_W<'a> { + w: &'a mut W, +} +impl<'a> TIE3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `TIE4` reader - Transmission Interrupt Enable 4"] +pub struct TIE4_R(crate::FieldReader); +impl TIE4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE4` writer - Transmission Interrupt Enable 4"] +pub struct TIE4_W<'a> { + w: &'a mut W, +} +impl<'a> TIE4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `TIE5` reader - Transmission Interrupt Enable 5"] +pub struct TIE5_R(crate::FieldReader); +impl TIE5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE5` writer - Transmission Interrupt Enable 5"] +pub struct TIE5_W<'a> { + w: &'a mut W, +} +impl<'a> TIE5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `TIE6` reader - Transmission Interrupt Enable 6"] +pub struct TIE6_R(crate::FieldReader); +impl TIE6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE6` writer - Transmission Interrupt Enable 6"] +pub struct TIE6_W<'a> { + w: &'a mut W, +} +impl<'a> TIE6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `TIE7` reader - Transmission Interrupt Enable 7"] +pub struct TIE7_R(crate::FieldReader); +impl TIE7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE7` writer - Transmission Interrupt Enable 7"] +pub struct TIE7_W<'a> { + w: &'a mut W, +} +impl<'a> TIE7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `TIE8` reader - Transmission Interrupt Enable 8"] +pub struct TIE8_R(crate::FieldReader); +impl TIE8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE8` writer - Transmission Interrupt Enable 8"] +pub struct TIE8_W<'a> { + w: &'a mut W, +} +impl<'a> TIE8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `TIE9` reader - Transmission Interrupt Enable 9"] +pub struct TIE9_R(crate::FieldReader); +impl TIE9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE9` writer - Transmission Interrupt Enable 9"] +pub struct TIE9_W<'a> { + w: &'a mut W, +} +impl<'a> TIE9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `TIE10` reader - Transmission Interrupt Enable 10"] +pub struct TIE10_R(crate::FieldReader); +impl TIE10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE10` writer - Transmission Interrupt Enable 10"] +pub struct TIE10_W<'a> { + w: &'a mut W, +} +impl<'a> TIE10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `TIE11` reader - Transmission Interrupt Enable 11"] +pub struct TIE11_R(crate::FieldReader); +impl TIE11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE11` writer - Transmission Interrupt Enable 11"] +pub struct TIE11_W<'a> { + w: &'a mut W, +} +impl<'a> TIE11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `TIE12` reader - Transmission Interrupt Enable 12"] +pub struct TIE12_R(crate::FieldReader); +impl TIE12_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE12_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE12_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE12` writer - Transmission Interrupt Enable 12"] +pub struct TIE12_W<'a> { + w: &'a mut W, +} +impl<'a> TIE12_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `TIE13` reader - Transmission Interrupt Enable 13"] +pub struct TIE13_R(crate::FieldReader); +impl TIE13_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE13_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE13_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE13` writer - Transmission Interrupt Enable 13"] +pub struct TIE13_W<'a> { + w: &'a mut W, +} +impl<'a> TIE13_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `TIE14` reader - Transmission Interrupt Enable 14"] +pub struct TIE14_R(crate::FieldReader); +impl TIE14_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE14_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE14_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE14` writer - Transmission Interrupt Enable 14"] +pub struct TIE14_W<'a> { + w: &'a mut W, +} +impl<'a> TIE14_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `TIE15` reader - Transmission Interrupt Enable 15"] +pub struct TIE15_R(crate::FieldReader); +impl TIE15_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE15_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE15_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE15` writer - Transmission Interrupt Enable 15"] +pub struct TIE15_W<'a> { + w: &'a mut W, +} +impl<'a> TIE15_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `TIE16` reader - Transmission Interrupt Enable 16"] +pub struct TIE16_R(crate::FieldReader); +impl TIE16_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE16_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE16_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE16` writer - Transmission Interrupt Enable 16"] +pub struct TIE16_W<'a> { + w: &'a mut W, +} +impl<'a> TIE16_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `TIE17` reader - Transmission Interrupt Enable 17"] +pub struct TIE17_R(crate::FieldReader); +impl TIE17_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE17_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE17_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE17` writer - Transmission Interrupt Enable 17"] +pub struct TIE17_W<'a> { + w: &'a mut W, +} +impl<'a> TIE17_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `TIE18` reader - Transmission Interrupt Enable 18"] +pub struct TIE18_R(crate::FieldReader); +impl TIE18_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE18_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE18_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE18` writer - Transmission Interrupt Enable 18"] +pub struct TIE18_W<'a> { + w: &'a mut W, +} +impl<'a> TIE18_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `TIE19` reader - Transmission Interrupt Enable 19"] +pub struct TIE19_R(crate::FieldReader); +impl TIE19_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE19_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE19_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE19` writer - Transmission Interrupt Enable 19"] +pub struct TIE19_W<'a> { + w: &'a mut W, +} +impl<'a> TIE19_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `TIE20` reader - Transmission Interrupt Enable 20"] +pub struct TIE20_R(crate::FieldReader); +impl TIE20_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE20_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE20_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE20` writer - Transmission Interrupt Enable 20"] +pub struct TIE20_W<'a> { + w: &'a mut W, +} +impl<'a> TIE20_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `TIE21` reader - Transmission Interrupt Enable 21"] +pub struct TIE21_R(crate::FieldReader); +impl TIE21_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE21_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE21_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE21` writer - Transmission Interrupt Enable 21"] +pub struct TIE21_W<'a> { + w: &'a mut W, +} +impl<'a> TIE21_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `TIE22` reader - Transmission Interrupt Enable 22"] +pub struct TIE22_R(crate::FieldReader); +impl TIE22_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE22_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE22_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE22` writer - Transmission Interrupt Enable 22"] +pub struct TIE22_W<'a> { + w: &'a mut W, +} +impl<'a> TIE22_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `TIE23` reader - Transmission Interrupt Enable 23"] +pub struct TIE23_R(crate::FieldReader); +impl TIE23_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE23_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE23_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE23` writer - Transmission Interrupt Enable 23"] +pub struct TIE23_W<'a> { + w: &'a mut W, +} +impl<'a> TIE23_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `TIE24` reader - Transmission Interrupt Enable 24"] +pub struct TIE24_R(crate::FieldReader); +impl TIE24_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE24_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE24_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE24` writer - Transmission Interrupt Enable 24"] +pub struct TIE24_W<'a> { + w: &'a mut W, +} +impl<'a> TIE24_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `TIE25` reader - Transmission Interrupt Enable 25"] +pub struct TIE25_R(crate::FieldReader); +impl TIE25_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE25_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE25_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE25` writer - Transmission Interrupt Enable 25"] +pub struct TIE25_W<'a> { + w: &'a mut W, +} +impl<'a> TIE25_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `TIE26` reader - Transmission Interrupt Enable 26"] +pub struct TIE26_R(crate::FieldReader); +impl TIE26_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE26_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE26_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE26` writer - Transmission Interrupt Enable 26"] +pub struct TIE26_W<'a> { + w: &'a mut W, +} +impl<'a> TIE26_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `TIE27` reader - Transmission Interrupt Enable 27"] +pub struct TIE27_R(crate::FieldReader); +impl TIE27_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE27_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE27_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE27` writer - Transmission Interrupt Enable 27"] +pub struct TIE27_W<'a> { + w: &'a mut W, +} +impl<'a> TIE27_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +#[doc = "Field `TIE28` reader - Transmission Interrupt Enable 28"] +pub struct TIE28_R(crate::FieldReader); +impl TIE28_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE28_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE28_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE28` writer - Transmission Interrupt Enable 28"] +pub struct TIE28_W<'a> { + w: &'a mut W, +} +impl<'a> TIE28_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Field `TIE29` reader - Transmission Interrupt Enable 29"] +pub struct TIE29_R(crate::FieldReader); +impl TIE29_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE29_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE29_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE29` writer - Transmission Interrupt Enable 29"] +pub struct TIE29_W<'a> { + w: &'a mut W, +} +impl<'a> TIE29_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29); + self.w + } +} +#[doc = "Field `TIE30` reader - Transmission Interrupt Enable 30"] +pub struct TIE30_R(crate::FieldReader); +impl TIE30_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE30_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE30_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE30` writer - Transmission Interrupt Enable 30"] +pub struct TIE30_W<'a> { + w: &'a mut W, +} +impl<'a> TIE30_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +#[doc = "Field `TIE31` reader - Transmission Interrupt Enable 31"] +pub struct TIE31_R(crate::FieldReader); +impl TIE31_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE31_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE31_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE31` writer - Transmission Interrupt Enable 31"] +pub struct TIE31_W<'a> { + w: &'a mut W, +} +impl<'a> TIE31_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bit 0 - Transmission Interrupt Enable 0"] + #[inline(always)] + pub fn tie0(&self) -> TIE0_R { + TIE0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmission Interrupt Enable 1"] + #[inline(always)] + pub fn tie1(&self) -> TIE1_R { + TIE1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Transmission Interrupt Enable 2"] + #[inline(always)] + pub fn tie2(&self) -> TIE2_R { + TIE2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Transmission Interrupt Enable 3"] + #[inline(always)] + pub fn tie3(&self) -> TIE3_R { + TIE3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Transmission Interrupt Enable 4"] + #[inline(always)] + pub fn tie4(&self) -> TIE4_R { + TIE4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Transmission Interrupt Enable 5"] + #[inline(always)] + pub fn tie5(&self) -> TIE5_R { + TIE5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Transmission Interrupt Enable 6"] + #[inline(always)] + pub fn tie6(&self) -> TIE6_R { + TIE6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Transmission Interrupt Enable 7"] + #[inline(always)] + pub fn tie7(&self) -> TIE7_R { + TIE7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Transmission Interrupt Enable 8"] + #[inline(always)] + pub fn tie8(&self) -> TIE8_R { + TIE8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Transmission Interrupt Enable 9"] + #[inline(always)] + pub fn tie9(&self) -> TIE9_R { + TIE9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Transmission Interrupt Enable 10"] + #[inline(always)] + pub fn tie10(&self) -> TIE10_R { + TIE10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Transmission Interrupt Enable 11"] + #[inline(always)] + pub fn tie11(&self) -> TIE11_R { + TIE11_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Transmission Interrupt Enable 12"] + #[inline(always)] + pub fn tie12(&self) -> TIE12_R { + TIE12_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Transmission Interrupt Enable 13"] + #[inline(always)] + pub fn tie13(&self) -> TIE13_R { + TIE13_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Transmission Interrupt Enable 14"] + #[inline(always)] + pub fn tie14(&self) -> TIE14_R { + TIE14_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Transmission Interrupt Enable 15"] + #[inline(always)] + pub fn tie15(&self) -> TIE15_R { + TIE15_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Transmission Interrupt Enable 16"] + #[inline(always)] + pub fn tie16(&self) -> TIE16_R { + TIE16_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Transmission Interrupt Enable 17"] + #[inline(always)] + pub fn tie17(&self) -> TIE17_R { + TIE17_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Transmission Interrupt Enable 18"] + #[inline(always)] + pub fn tie18(&self) -> TIE18_R { + TIE18_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Transmission Interrupt Enable 19"] + #[inline(always)] + pub fn tie19(&self) -> TIE19_R { + TIE19_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Transmission Interrupt Enable 20"] + #[inline(always)] + pub fn tie20(&self) -> TIE20_R { + TIE20_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Transmission Interrupt Enable 21"] + #[inline(always)] + pub fn tie21(&self) -> TIE21_R { + TIE21_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Transmission Interrupt Enable 22"] + #[inline(always)] + pub fn tie22(&self) -> TIE22_R { + TIE22_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Transmission Interrupt Enable 23"] + #[inline(always)] + pub fn tie23(&self) -> TIE23_R { + TIE23_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24 - Transmission Interrupt Enable 24"] + #[inline(always)] + pub fn tie24(&self) -> TIE24_R { + TIE24_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Transmission Interrupt Enable 25"] + #[inline(always)] + pub fn tie25(&self) -> TIE25_R { + TIE25_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Transmission Interrupt Enable 26"] + #[inline(always)] + pub fn tie26(&self) -> TIE26_R { + TIE26_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Transmission Interrupt Enable 27"] + #[inline(always)] + pub fn tie27(&self) -> TIE27_R { + TIE27_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28 - Transmission Interrupt Enable 28"] + #[inline(always)] + pub fn tie28(&self) -> TIE28_R { + TIE28_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Transmission Interrupt Enable 29"] + #[inline(always)] + pub fn tie29(&self) -> TIE29_R { + TIE29_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - Transmission Interrupt Enable 30"] + #[inline(always)] + pub fn tie30(&self) -> TIE30_R { + TIE30_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 31 - Transmission Interrupt Enable 31"] + #[inline(always)] + pub fn tie31(&self) -> TIE31_R { + TIE31_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Transmission Interrupt Enable 0"] + #[inline(always)] + pub fn tie0(&mut self) -> TIE0_W { + TIE0_W { w: self } + } + #[doc = "Bit 1 - Transmission Interrupt Enable 1"] + #[inline(always)] + pub fn tie1(&mut self) -> TIE1_W { + TIE1_W { w: self } + } + #[doc = "Bit 2 - Transmission Interrupt Enable 2"] + #[inline(always)] + pub fn tie2(&mut self) -> TIE2_W { + TIE2_W { w: self } + } + #[doc = "Bit 3 - Transmission Interrupt Enable 3"] + #[inline(always)] + pub fn tie3(&mut self) -> TIE3_W { + TIE3_W { w: self } + } + #[doc = "Bit 4 - Transmission Interrupt Enable 4"] + #[inline(always)] + pub fn tie4(&mut self) -> TIE4_W { + TIE4_W { w: self } + } + #[doc = "Bit 5 - Transmission Interrupt Enable 5"] + #[inline(always)] + pub fn tie5(&mut self) -> TIE5_W { + TIE5_W { w: self } + } + #[doc = "Bit 6 - Transmission Interrupt Enable 6"] + #[inline(always)] + pub fn tie6(&mut self) -> TIE6_W { + TIE6_W { w: self } + } + #[doc = "Bit 7 - Transmission Interrupt Enable 7"] + #[inline(always)] + pub fn tie7(&mut self) -> TIE7_W { + TIE7_W { w: self } + } + #[doc = "Bit 8 - Transmission Interrupt Enable 8"] + #[inline(always)] + pub fn tie8(&mut self) -> TIE8_W { + TIE8_W { w: self } + } + #[doc = "Bit 9 - Transmission Interrupt Enable 9"] + #[inline(always)] + pub fn tie9(&mut self) -> TIE9_W { + TIE9_W { w: self } + } + #[doc = "Bit 10 - Transmission Interrupt Enable 10"] + #[inline(always)] + pub fn tie10(&mut self) -> TIE10_W { + TIE10_W { w: self } + } + #[doc = "Bit 11 - Transmission Interrupt Enable 11"] + #[inline(always)] + pub fn tie11(&mut self) -> TIE11_W { + TIE11_W { w: self } + } + #[doc = "Bit 12 - Transmission Interrupt Enable 12"] + #[inline(always)] + pub fn tie12(&mut self) -> TIE12_W { + TIE12_W { w: self } + } + #[doc = "Bit 13 - Transmission Interrupt Enable 13"] + #[inline(always)] + pub fn tie13(&mut self) -> TIE13_W { + TIE13_W { w: self } + } + #[doc = "Bit 14 - Transmission Interrupt Enable 14"] + #[inline(always)] + pub fn tie14(&mut self) -> TIE14_W { + TIE14_W { w: self } + } + #[doc = "Bit 15 - Transmission Interrupt Enable 15"] + #[inline(always)] + pub fn tie15(&mut self) -> TIE15_W { + TIE15_W { w: self } + } + #[doc = "Bit 16 - Transmission Interrupt Enable 16"] + #[inline(always)] + pub fn tie16(&mut self) -> TIE16_W { + TIE16_W { w: self } + } + #[doc = "Bit 17 - Transmission Interrupt Enable 17"] + #[inline(always)] + pub fn tie17(&mut self) -> TIE17_W { + TIE17_W { w: self } + } + #[doc = "Bit 18 - Transmission Interrupt Enable 18"] + #[inline(always)] + pub fn tie18(&mut self) -> TIE18_W { + TIE18_W { w: self } + } + #[doc = "Bit 19 - Transmission Interrupt Enable 19"] + #[inline(always)] + pub fn tie19(&mut self) -> TIE19_W { + TIE19_W { w: self } + } + #[doc = "Bit 20 - Transmission Interrupt Enable 20"] + #[inline(always)] + pub fn tie20(&mut self) -> TIE20_W { + TIE20_W { w: self } + } + #[doc = "Bit 21 - Transmission Interrupt Enable 21"] + #[inline(always)] + pub fn tie21(&mut self) -> TIE21_W { + TIE21_W { w: self } + } + #[doc = "Bit 22 - Transmission Interrupt Enable 22"] + #[inline(always)] + pub fn tie22(&mut self) -> TIE22_W { + TIE22_W { w: self } + } + #[doc = "Bit 23 - Transmission Interrupt Enable 23"] + #[inline(always)] + pub fn tie23(&mut self) -> TIE23_W { + TIE23_W { w: self } + } + #[doc = "Bit 24 - Transmission Interrupt Enable 24"] + #[inline(always)] + pub fn tie24(&mut self) -> TIE24_W { + TIE24_W { w: self } + } + #[doc = "Bit 25 - Transmission Interrupt Enable 25"] + #[inline(always)] + pub fn tie25(&mut self) -> TIE25_W { + TIE25_W { w: self } + } + #[doc = "Bit 26 - Transmission Interrupt Enable 26"] + #[inline(always)] + pub fn tie26(&mut self) -> TIE26_W { + TIE26_W { w: self } + } + #[doc = "Bit 27 - Transmission Interrupt Enable 27"] + #[inline(always)] + pub fn tie27(&mut self) -> TIE27_W { + TIE27_W { w: self } + } + #[doc = "Bit 28 - Transmission Interrupt Enable 28"] + #[inline(always)] + pub fn tie28(&mut self) -> TIE28_W { + TIE28_W { w: self } + } + #[doc = "Bit 29 - Transmission Interrupt Enable 29"] + #[inline(always)] + pub fn tie29(&mut self) -> TIE29_W { + TIE29_W { w: self } + } + #[doc = "Bit 30 - Transmission Interrupt Enable 30"] + #[inline(always)] + pub fn tie30(&mut self) -> TIE30_W { + TIE30_W { w: self } + } + #[doc = "Bit 31 - Transmission Interrupt Enable 31"] + #[inline(always)] + pub fn tie31(&mut self) -> TIE31_W { + TIE31_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Tx Buffer Transmission Interrupt Enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txbtie](index.html) module"] +pub struct TXBTIE_SPEC; +impl crate::RegisterSpec for TXBTIE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [txbtie::R](R) reader structure"] +impl crate::Readable for TXBTIE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [txbtie::W](W) writer structure"] +impl crate::Writable for TXBTIE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TXBTIE to value 0"] +impl crate::Resettable for TXBTIE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/can0/txbto.rs b/pac/atsamc21g/src/can0/txbto.rs new file mode 100644 index 000000000000..54bc8f1295ad --- /dev/null +++ b/pac/atsamc21g/src/can0/txbto.rs @@ -0,0 +1,673 @@ +#[doc = "Register `TXBTO` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `TO0` reader - Transmission Occurred 0"] +pub struct TO0_R(crate::FieldReader); +impl TO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO1` reader - Transmission Occurred 1"] +pub struct TO1_R(crate::FieldReader); +impl TO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO2` reader - Transmission Occurred 2"] +pub struct TO2_R(crate::FieldReader); +impl TO2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO3` reader - Transmission Occurred 3"] +pub struct TO3_R(crate::FieldReader); +impl TO3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO4` reader - Transmission Occurred 4"] +pub struct TO4_R(crate::FieldReader); +impl TO4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO5` reader - Transmission Occurred 5"] +pub struct TO5_R(crate::FieldReader); +impl TO5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO6` reader - Transmission Occurred 6"] +pub struct TO6_R(crate::FieldReader); +impl TO6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO7` reader - Transmission Occurred 7"] +pub struct TO7_R(crate::FieldReader); +impl TO7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO8` reader - Transmission Occurred 8"] +pub struct TO8_R(crate::FieldReader); +impl TO8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO9` reader - Transmission Occurred 9"] +pub struct TO9_R(crate::FieldReader); +impl TO9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO10` reader - Transmission Occurred 10"] +pub struct TO10_R(crate::FieldReader); +impl TO10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO11` reader - Transmission Occurred 11"] +pub struct TO11_R(crate::FieldReader); +impl TO11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO12` reader - Transmission Occurred 12"] +pub struct TO12_R(crate::FieldReader); +impl TO12_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO12_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO12_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO13` reader - Transmission Occurred 13"] +pub struct TO13_R(crate::FieldReader); +impl TO13_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO13_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO13_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO14` reader - Transmission Occurred 14"] +pub struct TO14_R(crate::FieldReader); +impl TO14_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO14_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO14_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO15` reader - Transmission Occurred 15"] +pub struct TO15_R(crate::FieldReader); +impl TO15_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO15_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO15_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO16` reader - Transmission Occurred 16"] +pub struct TO16_R(crate::FieldReader); +impl TO16_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO16_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO16_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO17` reader - Transmission Occurred 17"] +pub struct TO17_R(crate::FieldReader); +impl TO17_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO17_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO17_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO18` reader - Transmission Occurred 18"] +pub struct TO18_R(crate::FieldReader); +impl TO18_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO18_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO18_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO19` reader - Transmission Occurred 19"] +pub struct TO19_R(crate::FieldReader); +impl TO19_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO19_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO19_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO20` reader - Transmission Occurred 20"] +pub struct TO20_R(crate::FieldReader); +impl TO20_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO20_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO20_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO21` reader - Transmission Occurred 21"] +pub struct TO21_R(crate::FieldReader); +impl TO21_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO21_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO21_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO22` reader - Transmission Occurred 22"] +pub struct TO22_R(crate::FieldReader); +impl TO22_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO22_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO22_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO23` reader - Transmission Occurred 23"] +pub struct TO23_R(crate::FieldReader); +impl TO23_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO23_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO23_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO24` reader - Transmission Occurred 24"] +pub struct TO24_R(crate::FieldReader); +impl TO24_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO24_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO24_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO25` reader - Transmission Occurred 25"] +pub struct TO25_R(crate::FieldReader); +impl TO25_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO25_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO25_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO26` reader - Transmission Occurred 26"] +pub struct TO26_R(crate::FieldReader); +impl TO26_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO26_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO26_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO27` reader - Transmission Occurred 27"] +pub struct TO27_R(crate::FieldReader); +impl TO27_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO27_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO27_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO28` reader - Transmission Occurred 28"] +pub struct TO28_R(crate::FieldReader); +impl TO28_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO28_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO28_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO29` reader - Transmission Occurred 29"] +pub struct TO29_R(crate::FieldReader); +impl TO29_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO29_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO29_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO30` reader - Transmission Occurred 30"] +pub struct TO30_R(crate::FieldReader); +impl TO30_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO30_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO30_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO31` reader - Transmission Occurred 31"] +pub struct TO31_R(crate::FieldReader); +impl TO31_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO31_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO31_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Transmission Occurred 0"] + #[inline(always)] + pub fn to0(&self) -> TO0_R { + TO0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmission Occurred 1"] + #[inline(always)] + pub fn to1(&self) -> TO1_R { + TO1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Transmission Occurred 2"] + #[inline(always)] + pub fn to2(&self) -> TO2_R { + TO2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Transmission Occurred 3"] + #[inline(always)] + pub fn to3(&self) -> TO3_R { + TO3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Transmission Occurred 4"] + #[inline(always)] + pub fn to4(&self) -> TO4_R { + TO4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Transmission Occurred 5"] + #[inline(always)] + pub fn to5(&self) -> TO5_R { + TO5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Transmission Occurred 6"] + #[inline(always)] + pub fn to6(&self) -> TO6_R { + TO6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Transmission Occurred 7"] + #[inline(always)] + pub fn to7(&self) -> TO7_R { + TO7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Transmission Occurred 8"] + #[inline(always)] + pub fn to8(&self) -> TO8_R { + TO8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Transmission Occurred 9"] + #[inline(always)] + pub fn to9(&self) -> TO9_R { + TO9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Transmission Occurred 10"] + #[inline(always)] + pub fn to10(&self) -> TO10_R { + TO10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Transmission Occurred 11"] + #[inline(always)] + pub fn to11(&self) -> TO11_R { + TO11_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Transmission Occurred 12"] + #[inline(always)] + pub fn to12(&self) -> TO12_R { + TO12_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Transmission Occurred 13"] + #[inline(always)] + pub fn to13(&self) -> TO13_R { + TO13_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Transmission Occurred 14"] + #[inline(always)] + pub fn to14(&self) -> TO14_R { + TO14_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Transmission Occurred 15"] + #[inline(always)] + pub fn to15(&self) -> TO15_R { + TO15_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Transmission Occurred 16"] + #[inline(always)] + pub fn to16(&self) -> TO16_R { + TO16_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Transmission Occurred 17"] + #[inline(always)] + pub fn to17(&self) -> TO17_R { + TO17_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Transmission Occurred 18"] + #[inline(always)] + pub fn to18(&self) -> TO18_R { + TO18_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Transmission Occurred 19"] + #[inline(always)] + pub fn to19(&self) -> TO19_R { + TO19_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Transmission Occurred 20"] + #[inline(always)] + pub fn to20(&self) -> TO20_R { + TO20_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Transmission Occurred 21"] + #[inline(always)] + pub fn to21(&self) -> TO21_R { + TO21_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Transmission Occurred 22"] + #[inline(always)] + pub fn to22(&self) -> TO22_R { + TO22_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Transmission Occurred 23"] + #[inline(always)] + pub fn to23(&self) -> TO23_R { + TO23_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24 - Transmission Occurred 24"] + #[inline(always)] + pub fn to24(&self) -> TO24_R { + TO24_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Transmission Occurred 25"] + #[inline(always)] + pub fn to25(&self) -> TO25_R { + TO25_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Transmission Occurred 26"] + #[inline(always)] + pub fn to26(&self) -> TO26_R { + TO26_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Transmission Occurred 27"] + #[inline(always)] + pub fn to27(&self) -> TO27_R { + TO27_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28 - Transmission Occurred 28"] + #[inline(always)] + pub fn to28(&self) -> TO28_R { + TO28_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Transmission Occurred 29"] + #[inline(always)] + pub fn to29(&self) -> TO29_R { + TO29_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - Transmission Occurred 30"] + #[inline(always)] + pub fn to30(&self) -> TO30_R { + TO30_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 31 - Transmission Occurred 31"] + #[inline(always)] + pub fn to31(&self) -> TO31_R { + TO31_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +#[doc = "Tx Buffer Transmission Occurred\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txbto](index.html) module"] +pub struct TXBTO_SPEC; +impl crate::RegisterSpec for TXBTO_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [txbto::R](R) reader structure"] +impl crate::Readable for TXBTO_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets TXBTO to value 0"] +impl crate::Resettable for TXBTO_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/can0/txefa.rs b/pac/atsamc21g/src/can0/txefa.rs new file mode 100644 index 000000000000..c539b8fc3dc0 --- /dev/null +++ b/pac/atsamc21g/src/can0/txefa.rs @@ -0,0 +1,103 @@ +#[doc = "Register `TXEFA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TXEFA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EFAI` reader - Event FIFO Acknowledge Index"] +pub struct EFAI_R(crate::FieldReader); +impl EFAI_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EFAI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EFAI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EFAI` writer - Event FIFO Acknowledge Index"] +pub struct EFAI_W<'a> { + w: &'a mut W, +} +impl<'a> EFAI_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Event FIFO Acknowledge Index"] + #[inline(always)] + pub fn efai(&self) -> EFAI_R { + EFAI_R::new((self.bits & 0x1f) as u8) + } +} +impl W { + #[doc = "Bits 0:4 - Event FIFO Acknowledge Index"] + #[inline(always)] + pub fn efai(&mut self) -> EFAI_W { + EFAI_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Tx Event FIFO Acknowledge\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txefa](index.html) module"] +pub struct TXEFA_SPEC; +impl crate::RegisterSpec for TXEFA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [txefa::R](R) reader structure"] +impl crate::Readable for TXEFA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [txefa::W](W) writer structure"] +impl crate::Writable for TXEFA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TXEFA to value 0"] +impl crate::Resettable for TXEFA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/can0/txefc.rs b/pac/atsamc21g/src/can0/txefc.rs new file mode 100644 index 000000000000..0c9b658d285b --- /dev/null +++ b/pac/atsamc21g/src/can0/txefc.rs @@ -0,0 +1,177 @@ +#[doc = "Register `TXEFC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TXEFC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EFSA` reader - Event FIFO Start Address"] +pub struct EFSA_R(crate::FieldReader); +impl EFSA_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + EFSA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EFSA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EFSA` writer - Event FIFO Start Address"] +pub struct EFSA_W<'a> { + w: &'a mut W, +} +impl<'a> EFSA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +#[doc = "Field `EFS` reader - Event FIFO Size"] +pub struct EFS_R(crate::FieldReader); +impl EFS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EFS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EFS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EFS` writer - Event FIFO Size"] +pub struct EFS_W<'a> { + w: &'a mut W, +} +impl<'a> EFS_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 16)) | ((value as u32 & 0x3f) << 16); + self.w + } +} +#[doc = "Field `EFWM` reader - Event FIFO Watermark"] +pub struct EFWM_R(crate::FieldReader); +impl EFWM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EFWM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EFWM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EFWM` writer - Event FIFO Watermark"] +pub struct EFWM_W<'a> { + w: &'a mut W, +} +impl<'a> EFWM_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 24)) | ((value as u32 & 0x3f) << 24); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Event FIFO Start Address"] + #[inline(always)] + pub fn efsa(&self) -> EFSA_R { + EFSA_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:21 - Event FIFO Size"] + #[inline(always)] + pub fn efs(&self) -> EFS_R { + EFS_R::new(((self.bits >> 16) & 0x3f) as u8) + } + #[doc = "Bits 24:29 - Event FIFO Watermark"] + #[inline(always)] + pub fn efwm(&self) -> EFWM_R { + EFWM_R::new(((self.bits >> 24) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:15 - Event FIFO Start Address"] + #[inline(always)] + pub fn efsa(&mut self) -> EFSA_W { + EFSA_W { w: self } + } + #[doc = "Bits 16:21 - Event FIFO Size"] + #[inline(always)] + pub fn efs(&mut self) -> EFS_W { + EFS_W { w: self } + } + #[doc = "Bits 24:29 - Event FIFO Watermark"] + #[inline(always)] + pub fn efwm(&mut self) -> EFWM_W { + EFWM_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Tx Event FIFO Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txefc](index.html) module"] +pub struct TXEFC_SPEC; +impl crate::RegisterSpec for TXEFC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [txefc::R](R) reader structure"] +impl crate::Readable for TXEFC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [txefc::W](W) writer structure"] +impl crate::Writable for TXEFC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TXEFC to value 0"] +impl crate::Resettable for TXEFC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/can0/txefs.rs b/pac/atsamc21g/src/can0/txefs.rs new file mode 100644 index 000000000000..85cac75a7ad7 --- /dev/null +++ b/pac/atsamc21g/src/can0/txefs.rs @@ -0,0 +1,133 @@ +#[doc = "Register `TXEFS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `EFFL` reader - Event FIFO Fill Level"] +pub struct EFFL_R(crate::FieldReader); +impl EFFL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EFFL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EFFL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EFGI` reader - Event FIFO Get Index"] +pub struct EFGI_R(crate::FieldReader); +impl EFGI_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EFGI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EFGI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EFPI` reader - Event FIFO Put Index"] +pub struct EFPI_R(crate::FieldReader); +impl EFPI_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EFPI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EFPI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EFF` reader - Event FIFO Full"] +pub struct EFF_R(crate::FieldReader); +impl EFF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EFF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EFF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TEFL` reader - Tx Event FIFO Element Lost"] +pub struct TEFL_R(crate::FieldReader); +impl TEFL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TEFL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TEFL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:5 - Event FIFO Fill Level"] + #[inline(always)] + pub fn effl(&self) -> EFFL_R { + EFFL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 8:12 - Event FIFO Get Index"] + #[inline(always)] + pub fn efgi(&self) -> EFGI_R { + EFGI_R::new(((self.bits >> 8) & 0x1f) as u8) + } + #[doc = "Bits 16:20 - Event FIFO Put Index"] + #[inline(always)] + pub fn efpi(&self) -> EFPI_R { + EFPI_R::new(((self.bits >> 16) & 0x1f) as u8) + } + #[doc = "Bit 24 - Event FIFO Full"] + #[inline(always)] + pub fn eff(&self) -> EFF_R { + EFF_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Tx Event FIFO Element Lost"] + #[inline(always)] + pub fn tefl(&self) -> TEFL_R { + TEFL_R::new(((self.bits >> 25) & 0x01) != 0) + } +} +#[doc = "Tx Event FIFO Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txefs](index.html) module"] +pub struct TXEFS_SPEC; +impl crate::RegisterSpec for TXEFS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [txefs::R](R) reader structure"] +impl crate::Readable for TXEFS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets TXEFS to value 0"] +impl crate::Resettable for TXEFS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/can0/txesc.rs b/pac/atsamc21g/src/can0/txesc.rs new file mode 100644 index 000000000000..7d1339f7c1cb --- /dev/null +++ b/pac/atsamc21g/src/can0/txesc.rs @@ -0,0 +1,230 @@ +#[doc = "Register `TXESC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TXESC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Tx Buffer Data Field Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum TBDS_A { + #[doc = "0: 8 byte data field"] + DATA8 = 0, + #[doc = "1: 12 byte data field"] + DATA12 = 1, + #[doc = "2: 16 byte data field"] + DATA16 = 2, + #[doc = "3: 20 byte data field"] + DATA20 = 3, + #[doc = "4: 24 byte data field"] + DATA24 = 4, + #[doc = "5: 32 byte data field"] + DATA32 = 5, + #[doc = "6: 48 byte data field"] + DATA48 = 6, + #[doc = "7: 64 byte data field"] + DATA64 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: TBDS_A) -> Self { + variant as _ + } +} +#[doc = "Field `TBDS` reader - Tx Buffer Data Field Size"] +pub struct TBDS_R(crate::FieldReader); +impl TBDS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TBDS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TBDS_A { + match self.bits { + 0 => TBDS_A::DATA8, + 1 => TBDS_A::DATA12, + 2 => TBDS_A::DATA16, + 3 => TBDS_A::DATA20, + 4 => TBDS_A::DATA24, + 5 => TBDS_A::DATA32, + 6 => TBDS_A::DATA48, + 7 => TBDS_A::DATA64, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DATA8`"] + #[inline(always)] + pub fn is_data8(&self) -> bool { + **self == TBDS_A::DATA8 + } + #[doc = "Checks if the value of the field is `DATA12`"] + #[inline(always)] + pub fn is_data12(&self) -> bool { + **self == TBDS_A::DATA12 + } + #[doc = "Checks if the value of the field is `DATA16`"] + #[inline(always)] + pub fn is_data16(&self) -> bool { + **self == TBDS_A::DATA16 + } + #[doc = "Checks if the value of the field is `DATA20`"] + #[inline(always)] + pub fn is_data20(&self) -> bool { + **self == TBDS_A::DATA20 + } + #[doc = "Checks if the value of the field is `DATA24`"] + #[inline(always)] + pub fn is_data24(&self) -> bool { + **self == TBDS_A::DATA24 + } + #[doc = "Checks if the value of the field is `DATA32`"] + #[inline(always)] + pub fn is_data32(&self) -> bool { + **self == TBDS_A::DATA32 + } + #[doc = "Checks if the value of the field is `DATA48`"] + #[inline(always)] + pub fn is_data48(&self) -> bool { + **self == TBDS_A::DATA48 + } + #[doc = "Checks if the value of the field is `DATA64`"] + #[inline(always)] + pub fn is_data64(&self) -> bool { + **self == TBDS_A::DATA64 + } +} +impl core::ops::Deref for TBDS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TBDS` writer - Tx Buffer Data Field Size"] +pub struct TBDS_W<'a> { + w: &'a mut W, +} +impl<'a> TBDS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TBDS_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "8 byte data field"] + #[inline(always)] + pub fn data8(self) -> &'a mut W { + self.variant(TBDS_A::DATA8) + } + #[doc = "12 byte data field"] + #[inline(always)] + pub fn data12(self) -> &'a mut W { + self.variant(TBDS_A::DATA12) + } + #[doc = "16 byte data field"] + #[inline(always)] + pub fn data16(self) -> &'a mut W { + self.variant(TBDS_A::DATA16) + } + #[doc = "20 byte data field"] + #[inline(always)] + pub fn data20(self) -> &'a mut W { + self.variant(TBDS_A::DATA20) + } + #[doc = "24 byte data field"] + #[inline(always)] + pub fn data24(self) -> &'a mut W { + self.variant(TBDS_A::DATA24) + } + #[doc = "32 byte data field"] + #[inline(always)] + pub fn data32(self) -> &'a mut W { + self.variant(TBDS_A::DATA32) + } + #[doc = "48 byte data field"] + #[inline(always)] + pub fn data48(self) -> &'a mut W { + self.variant(TBDS_A::DATA48) + } + #[doc = "64 byte data field"] + #[inline(always)] + pub fn data64(self) -> &'a mut W { + self.variant(TBDS_A::DATA64) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Tx Buffer Data Field Size"] + #[inline(always)] + pub fn tbds(&self) -> TBDS_R { + TBDS_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Tx Buffer Data Field Size"] + #[inline(always)] + pub fn tbds(&mut self) -> TBDS_W { + TBDS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Tx Buffer Element Size Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txesc](index.html) module"] +pub struct TXESC_SPEC; +impl crate::RegisterSpec for TXESC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [txesc::R](R) reader structure"] +impl crate::Readable for TXESC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [txesc::W](W) writer structure"] +impl crate::Writable for TXESC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TXESC to value 0"] +impl crate::Resettable for TXESC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/can0/txfqs.rs b/pac/atsamc21g/src/can0/txfqs.rs new file mode 100644 index 000000000000..19ef5f5d3fe6 --- /dev/null +++ b/pac/atsamc21g/src/can0/txfqs.rs @@ -0,0 +1,113 @@ +#[doc = "Register `TXFQS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `TFFL` reader - Tx FIFO Free Level"] +pub struct TFFL_R(crate::FieldReader); +impl TFFL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TFFL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TFFL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TFGI` reader - Tx FIFO Get Index"] +pub struct TFGI_R(crate::FieldReader); +impl TFGI_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TFGI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TFGI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TFQPI` reader - Tx FIFO/Queue Put Index"] +pub struct TFQPI_R(crate::FieldReader); +impl TFQPI_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TFQPI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TFQPI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TFQF` reader - Tx FIFO/Queue Full"] +pub struct TFQF_R(crate::FieldReader); +impl TFQF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TFQF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TFQF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:5 - Tx FIFO Free Level"] + #[inline(always)] + pub fn tffl(&self) -> TFFL_R { + TFFL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 8:12 - Tx FIFO Get Index"] + #[inline(always)] + pub fn tfgi(&self) -> TFGI_R { + TFGI_R::new(((self.bits >> 8) & 0x1f) as u8) + } + #[doc = "Bits 16:20 - Tx FIFO/Queue Put Index"] + #[inline(always)] + pub fn tfqpi(&self) -> TFQPI_R { + TFQPI_R::new(((self.bits >> 16) & 0x1f) as u8) + } + #[doc = "Bit 21 - Tx FIFO/Queue Full"] + #[inline(always)] + pub fn tfqf(&self) -> TFQF_R { + TFQF_R::new(((self.bits >> 21) & 0x01) != 0) + } +} +#[doc = "Tx FIFO / Queue Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txfqs](index.html) module"] +pub struct TXFQS_SPEC; +impl crate::RegisterSpec for TXFQS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [txfqs::R](R) reader structure"] +impl crate::Readable for TXFQS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets TXFQS to value 0"] +impl crate::Resettable for TXFQS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/can0/xidam.rs b/pac/atsamc21g/src/can0/xidam.rs new file mode 100644 index 000000000000..8d78879a63be --- /dev/null +++ b/pac/atsamc21g/src/can0/xidam.rs @@ -0,0 +1,103 @@ +#[doc = "Register `XIDAM` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `XIDAM` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EIDM` reader - Extended ID Mask"] +pub struct EIDM_R(crate::FieldReader); +impl EIDM_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + EIDM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EIDM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EIDM` writer - Extended ID Mask"] +pub struct EIDM_W<'a> { + w: &'a mut W, +} +impl<'a> EIDM_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1fff_ffff) | (value as u32 & 0x1fff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:28 - Extended ID Mask"] + #[inline(always)] + pub fn eidm(&self) -> EIDM_R { + EIDM_R::new((self.bits & 0x1fff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:28 - Extended ID Mask"] + #[inline(always)] + pub fn eidm(&mut self) -> EIDM_W { + EIDM_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Extended ID AND Mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [xidam](index.html) module"] +pub struct XIDAM_SPEC; +impl crate::RegisterSpec for XIDAM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [xidam::R](R) reader structure"] +impl crate::Readable for XIDAM_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [xidam::W](W) writer structure"] +impl crate::Writable for XIDAM_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets XIDAM to value 0x1fff_ffff"] +impl crate::Resettable for XIDAM_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x1fff_ffff + } +} diff --git a/pac/atsamc21g/src/can0/xidfc.rs b/pac/atsamc21g/src/can0/xidfc.rs new file mode 100644 index 000000000000..57b31389a71f --- /dev/null +++ b/pac/atsamc21g/src/can0/xidfc.rs @@ -0,0 +1,140 @@ +#[doc = "Register `XIDFC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `XIDFC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FLESA` reader - Filter List Extended Start Address"] +pub struct FLESA_R(crate::FieldReader); +impl FLESA_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + FLESA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FLESA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLESA` writer - Filter List Extended Start Address"] +pub struct FLESA_W<'a> { + w: &'a mut W, +} +impl<'a> FLESA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +#[doc = "Field `LSE` reader - List Size Extended"] +pub struct LSE_R(crate::FieldReader); +impl LSE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LSE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LSE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LSE` writer - List Size Extended"] +pub struct LSE_W<'a> { + w: &'a mut W, +} +impl<'a> LSE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x7f << 16)) | ((value as u32 & 0x7f) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Filter List Extended Start Address"] + #[inline(always)] + pub fn flesa(&self) -> FLESA_R { + FLESA_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:22 - List Size Extended"] + #[inline(always)] + pub fn lse(&self) -> LSE_R { + LSE_R::new(((self.bits >> 16) & 0x7f) as u8) + } +} +impl W { + #[doc = "Bits 0:15 - Filter List Extended Start Address"] + #[inline(always)] + pub fn flesa(&mut self) -> FLESA_W { + FLESA_W { w: self } + } + #[doc = "Bits 16:22 - List Size Extended"] + #[inline(always)] + pub fn lse(&mut self) -> LSE_W { + LSE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Extended ID Filter Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [xidfc](index.html) module"] +pub struct XIDFC_SPEC; +impl crate::RegisterSpec for XIDFC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [xidfc::R](R) reader structure"] +impl crate::Readable for XIDFC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [xidfc::W](W) writer structure"] +impl crate::Writable for XIDFC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets XIDFC to value 0"] +impl crate::Resettable for XIDFC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/ccl.rs b/pac/atsamc21g/src/ccl.rs new file mode 100644 index 000000000000..30b1f41639c1 --- /dev/null +++ b/pac/atsamc21g/src/ccl.rs @@ -0,0 +1,24 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrl: crate::Reg, + _reserved1: [u8; 0x03], + #[doc = "0x04 - SEQ Control x"] + pub seqctrl: [crate::Reg; 2], + _reserved2: [u8; 0x02], + #[doc = "0x08..0x18 - LUT Control x"] + pub lutctrl: [crate::Reg; 4], +} +#[doc = "CTRL register accessor: an alias for `Reg`"] +pub type CTRL = crate::Reg; +#[doc = "Control"] +pub mod ctrl; +#[doc = "SEQCTRL register accessor: an alias for `Reg`"] +pub type SEQCTRL = crate::Reg; +#[doc = "SEQ Control x"] +pub mod seqctrl; +#[doc = "LUTCTRL register accessor: an alias for `Reg`"] +pub type LUTCTRL = crate::Reg; +#[doc = "LUT Control x"] +pub mod lutctrl; diff --git a/pac/atsamc21g/src/ccl/ctrl.rs b/pac/atsamc21g/src/ccl/ctrl.rs new file mode 100644 index 000000000000..5e515fe037ca --- /dev/null +++ b/pac/atsamc21g/src/ccl/ctrl.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"] +pub struct CTRL_SPEC; +impl crate::RegisterSpec for CTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrl::R](R) reader structure"] +impl crate::Readable for CTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"] +impl crate::Writable for CTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/ccl/lutctrl.rs b/pac/atsamc21g/src/ccl/lutctrl.rs new file mode 100644 index 000000000000..530ed34f7c81 --- /dev/null +++ b/pac/atsamc21g/src/ccl/lutctrl.rs @@ -0,0 +1,702 @@ +#[doc = "Register `LUTCTRL[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `LUTCTRL[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - LUT Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - LUT Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Filter Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FILTSEL_A { + #[doc = "0: Filter disabled"] + DISABLE = 0, + #[doc = "1: Synchronizer enabled"] + SYNCH = 1, + #[doc = "2: Filter enabled"] + FILTER = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FILTSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `FILTSEL` reader - Filter Selection"] +pub struct FILTSEL_R(crate::FieldReader); +impl FILTSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FILTSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(FILTSEL_A::DISABLE), + 1 => Some(FILTSEL_A::SYNCH), + 2 => Some(FILTSEL_A::FILTER), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == FILTSEL_A::DISABLE + } + #[doc = "Checks if the value of the field is `SYNCH`"] + #[inline(always)] + pub fn is_synch(&self) -> bool { + **self == FILTSEL_A::SYNCH + } + #[doc = "Checks if the value of the field is `FILTER`"] + #[inline(always)] + pub fn is_filter(&self) -> bool { + **self == FILTSEL_A::FILTER + } +} +impl core::ops::Deref for FILTSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTSEL` writer - Filter Selection"] +pub struct FILTSEL_W<'a> { + w: &'a mut W, +} +impl<'a> FILTSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FILTSEL_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Filter disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(FILTSEL_A::DISABLE) + } + #[doc = "Synchronizer enabled"] + #[inline(always)] + pub fn synch(self) -> &'a mut W { + self.variant(FILTSEL_A::SYNCH) + } + #[doc = "Filter enabled"] + #[inline(always)] + pub fn filter(self) -> &'a mut W { + self.variant(FILTSEL_A::FILTER) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u32 & 0x03) << 4); + self.w + } +} +#[doc = "Field `EDGESEL` reader - Edge Selection"] +pub struct EDGESEL_R(crate::FieldReader); +impl EDGESEL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EDGESEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EDGESEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EDGESEL` writer - Edge Selection"] +pub struct EDGESEL_W<'a> { + w: &'a mut W, +} +impl<'a> EDGESEL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Input Selection 0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum INSEL0_A { + #[doc = "0: Masked input"] + MASK = 0, + #[doc = "1: Feedback input source"] + FEEDBACK = 1, + #[doc = "2: Linked LUT input source"] + LINK = 2, + #[doc = "3: Event in put source"] + EVENT = 3, + #[doc = "4: I/O pin input source"] + IO = 4, + #[doc = "5: AC input source"] + AC = 5, + #[doc = "6: TC input source"] + TC = 6, + #[doc = "7: Alternate TC input source"] + ALTTC = 7, + #[doc = "8: TCC input source"] + TCC = 8, + #[doc = "9: SERCOM inout source"] + SERCOM = 9, +} +impl From for u8 { + #[inline(always)] + fn from(variant: INSEL0_A) -> Self { + variant as _ + } +} +#[doc = "Field `INSEL0` reader - Input Selection 0"] +pub struct INSEL0_R(crate::FieldReader); +impl INSEL0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + INSEL0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(INSEL0_A::MASK), + 1 => Some(INSEL0_A::FEEDBACK), + 2 => Some(INSEL0_A::LINK), + 3 => Some(INSEL0_A::EVENT), + 4 => Some(INSEL0_A::IO), + 5 => Some(INSEL0_A::AC), + 6 => Some(INSEL0_A::TC), + 7 => Some(INSEL0_A::ALTTC), + 8 => Some(INSEL0_A::TCC), + 9 => Some(INSEL0_A::SERCOM), + _ => None, + } + } + #[doc = "Checks if the value of the field is `MASK`"] + #[inline(always)] + pub fn is_mask(&self) -> bool { + **self == INSEL0_A::MASK + } + #[doc = "Checks if the value of the field is `FEEDBACK`"] + #[inline(always)] + pub fn is_feedback(&self) -> bool { + **self == INSEL0_A::FEEDBACK + } + #[doc = "Checks if the value of the field is `LINK`"] + #[inline(always)] + pub fn is_link(&self) -> bool { + **self == INSEL0_A::LINK + } + #[doc = "Checks if the value of the field is `EVENT`"] + #[inline(always)] + pub fn is_event(&self) -> bool { + **self == INSEL0_A::EVENT + } + #[doc = "Checks if the value of the field is `IO`"] + #[inline(always)] + pub fn is_io(&self) -> bool { + **self == INSEL0_A::IO + } + #[doc = "Checks if the value of the field is `AC`"] + #[inline(always)] + pub fn is_ac(&self) -> bool { + **self == INSEL0_A::AC + } + #[doc = "Checks if the value of the field is `TC`"] + #[inline(always)] + pub fn is_tc(&self) -> bool { + **self == INSEL0_A::TC + } + #[doc = "Checks if the value of the field is `ALTTC`"] + #[inline(always)] + pub fn is_alttc(&self) -> bool { + **self == INSEL0_A::ALTTC + } + #[doc = "Checks if the value of the field is `TCC`"] + #[inline(always)] + pub fn is_tcc(&self) -> bool { + **self == INSEL0_A::TCC + } + #[doc = "Checks if the value of the field is `SERCOM`"] + #[inline(always)] + pub fn is_sercom(&self) -> bool { + **self == INSEL0_A::SERCOM + } +} +impl core::ops::Deref for INSEL0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INSEL0` writer - Input Selection 0"] +pub struct INSEL0_W<'a> { + w: &'a mut W, +} +impl<'a> INSEL0_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: INSEL0_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Masked input"] + #[inline(always)] + pub fn mask(self) -> &'a mut W { + self.variant(INSEL0_A::MASK) + } + #[doc = "Feedback input source"] + #[inline(always)] + pub fn feedback(self) -> &'a mut W { + self.variant(INSEL0_A::FEEDBACK) + } + #[doc = "Linked LUT input source"] + #[inline(always)] + pub fn link(self) -> &'a mut W { + self.variant(INSEL0_A::LINK) + } + #[doc = "Event in put source"] + #[inline(always)] + pub fn event(self) -> &'a mut W { + self.variant(INSEL0_A::EVENT) + } + #[doc = "I/O pin input source"] + #[inline(always)] + pub fn io(self) -> &'a mut W { + self.variant(INSEL0_A::IO) + } + #[doc = "AC input source"] + #[inline(always)] + pub fn ac(self) -> &'a mut W { + self.variant(INSEL0_A::AC) + } + #[doc = "TC input source"] + #[inline(always)] + pub fn tc(self) -> &'a mut W { + self.variant(INSEL0_A::TC) + } + #[doc = "Alternate TC input source"] + #[inline(always)] + pub fn alttc(self) -> &'a mut W { + self.variant(INSEL0_A::ALTTC) + } + #[doc = "TCC input source"] + #[inline(always)] + pub fn tcc(self) -> &'a mut W { + self.variant(INSEL0_A::TCC) + } + #[doc = "SERCOM inout source"] + #[inline(always)] + pub fn sercom(self) -> &'a mut W { + self.variant(INSEL0_A::SERCOM) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 8)) | ((value as u32 & 0x0f) << 8); + self.w + } +} +#[doc = "Field `INSEL1` reader - Input Selection 1"] +pub struct INSEL1_R(crate::FieldReader); +impl INSEL1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + INSEL1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INSEL1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INSEL1` writer - Input Selection 1"] +pub struct INSEL1_W<'a> { + w: &'a mut W, +} +impl<'a> INSEL1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 12)) | ((value as u32 & 0x0f) << 12); + self.w + } +} +#[doc = "Field `INSEL2` reader - Input Selection 2"] +pub struct INSEL2_R(crate::FieldReader); +impl INSEL2_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + INSEL2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INSEL2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INSEL2` writer - Input Selection 2"] +pub struct INSEL2_W<'a> { + w: &'a mut W, +} +impl<'a> INSEL2_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 16)) | ((value as u32 & 0x0f) << 16); + self.w + } +} +#[doc = "Field `INVEI` reader - Input Event Invert"] +pub struct INVEI_R(crate::FieldReader); +impl INVEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEI` writer - Input Event Invert"] +pub struct INVEI_W<'a> { + w: &'a mut W, +} +impl<'a> INVEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `LUTEI` reader - Event Input Enable"] +pub struct LUTEI_R(crate::FieldReader); +impl LUTEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LUTEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LUTEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LUTEI` writer - Event Input Enable"] +pub struct LUTEI_W<'a> { + w: &'a mut W, +} +impl<'a> LUTEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `LUTEO` reader - Event Output Enable"] +pub struct LUTEO_R(crate::FieldReader); +impl LUTEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LUTEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LUTEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LUTEO` writer - Event Output Enable"] +pub struct LUTEO_W<'a> { + w: &'a mut W, +} +impl<'a> LUTEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `TRUTH` reader - Truth Value"] +pub struct TRUTH_R(crate::FieldReader); +impl TRUTH_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TRUTH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRUTH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRUTH` writer - Truth Value"] +pub struct TRUTH_W<'a> { + w: &'a mut W, +} +impl<'a> TRUTH_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 24)) | ((value as u32 & 0xff) << 24); + self.w + } +} +impl R { + #[doc = "Bit 1 - LUT Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 4:5 - Filter Selection"] + #[inline(always)] + pub fn filtsel(&self) -> FILTSEL_R { + FILTSEL_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bit 7 - Edge Selection"] + #[inline(always)] + pub fn edgesel(&self) -> EDGESEL_R { + EDGESEL_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:11 - Input Selection 0"] + #[inline(always)] + pub fn insel0(&self) -> INSEL0_R { + INSEL0_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - Input Selection 1"] + #[inline(always)] + pub fn insel1(&self) -> INSEL1_R { + INSEL1_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:19 - Input Selection 2"] + #[inline(always)] + pub fn insel2(&self) -> INSEL2_R { + INSEL2_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Input Event Invert"] + #[inline(always)] + pub fn invei(&self) -> INVEI_R { + INVEI_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Event Input Enable"] + #[inline(always)] + pub fn lutei(&self) -> LUTEI_R { + LUTEI_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Event Output Enable"] + #[inline(always)] + pub fn luteo(&self) -> LUTEO_R { + LUTEO_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bits 24:31 - Truth Value"] + #[inline(always)] + pub fn truth(&self) -> TRUTH_R { + TRUTH_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bit 1 - LUT Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 4:5 - Filter Selection"] + #[inline(always)] + pub fn filtsel(&mut self) -> FILTSEL_W { + FILTSEL_W { w: self } + } + #[doc = "Bit 7 - Edge Selection"] + #[inline(always)] + pub fn edgesel(&mut self) -> EDGESEL_W { + EDGESEL_W { w: self } + } + #[doc = "Bits 8:11 - Input Selection 0"] + #[inline(always)] + pub fn insel0(&mut self) -> INSEL0_W { + INSEL0_W { w: self } + } + #[doc = "Bits 12:15 - Input Selection 1"] + #[inline(always)] + pub fn insel1(&mut self) -> INSEL1_W { + INSEL1_W { w: self } + } + #[doc = "Bits 16:19 - Input Selection 2"] + #[inline(always)] + pub fn insel2(&mut self) -> INSEL2_W { + INSEL2_W { w: self } + } + #[doc = "Bit 20 - Input Event Invert"] + #[inline(always)] + pub fn invei(&mut self) -> INVEI_W { + INVEI_W { w: self } + } + #[doc = "Bit 21 - Event Input Enable"] + #[inline(always)] + pub fn lutei(&mut self) -> LUTEI_W { + LUTEI_W { w: self } + } + #[doc = "Bit 22 - Event Output Enable"] + #[inline(always)] + pub fn luteo(&mut self) -> LUTEO_W { + LUTEO_W { w: self } + } + #[doc = "Bits 24:31 - Truth Value"] + #[inline(always)] + pub fn truth(&mut self) -> TRUTH_W { + TRUTH_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "LUT Control x\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lutctrl](index.html) module"] +pub struct LUTCTRL_SPEC; +impl crate::RegisterSpec for LUTCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [lutctrl::R](R) reader structure"] +impl crate::Readable for LUTCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [lutctrl::W](W) writer structure"] +impl crate::Writable for LUTCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets LUTCTRL[%s] +to value 0"] +impl crate::Resettable for LUTCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/ccl/seqctrl.rs b/pac/atsamc21g/src/ccl/seqctrl.rs new file mode 100644 index 000000000000..e2597a1042f3 --- /dev/null +++ b/pac/atsamc21g/src/ccl/seqctrl.rs @@ -0,0 +1,192 @@ +#[doc = "Register `SEQCTRL[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SEQCTRL[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Sequential Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SEQSEL_A { + #[doc = "0: Sequential logic is disabled"] + DISABLE = 0, + #[doc = "1: D flip flop"] + DFF = 1, + #[doc = "2: JK flip flop"] + JK = 2, + #[doc = "3: D latch"] + LATCH = 3, + #[doc = "4: RS latch"] + RS = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEQSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `SEQSEL` reader - Sequential Selection"] +pub struct SEQSEL_R(crate::FieldReader); +impl SEQSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SEQSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEQSEL_A::DISABLE), + 1 => Some(SEQSEL_A::DFF), + 2 => Some(SEQSEL_A::JK), + 3 => Some(SEQSEL_A::LATCH), + 4 => Some(SEQSEL_A::RS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == SEQSEL_A::DISABLE + } + #[doc = "Checks if the value of the field is `DFF`"] + #[inline(always)] + pub fn is_dff(&self) -> bool { + **self == SEQSEL_A::DFF + } + #[doc = "Checks if the value of the field is `JK`"] + #[inline(always)] + pub fn is_jk(&self) -> bool { + **self == SEQSEL_A::JK + } + #[doc = "Checks if the value of the field is `LATCH`"] + #[inline(always)] + pub fn is_latch(&self) -> bool { + **self == SEQSEL_A::LATCH + } + #[doc = "Checks if the value of the field is `RS`"] + #[inline(always)] + pub fn is_rs(&self) -> bool { + **self == SEQSEL_A::RS + } +} +impl core::ops::Deref for SEQSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEQSEL` writer - Sequential Selection"] +pub struct SEQSEL_W<'a> { + w: &'a mut W, +} +impl<'a> SEQSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SEQSEL_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Sequential logic is disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(SEQSEL_A::DISABLE) + } + #[doc = "D flip flop"] + #[inline(always)] + pub fn dff(self) -> &'a mut W { + self.variant(SEQSEL_A::DFF) + } + #[doc = "JK flip flop"] + #[inline(always)] + pub fn jk(self) -> &'a mut W { + self.variant(SEQSEL_A::JK) + } + #[doc = "D latch"] + #[inline(always)] + pub fn latch(self) -> &'a mut W { + self.variant(SEQSEL_A::LATCH) + } + #[doc = "RS latch"] + #[inline(always)] + pub fn rs(self) -> &'a mut W { + self.variant(SEQSEL_A::RS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Sequential Selection"] + #[inline(always)] + pub fn seqsel(&self) -> SEQSEL_R { + SEQSEL_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Sequential Selection"] + #[inline(always)] + pub fn seqsel(&mut self) -> SEQSEL_W { + SEQSEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SEQ Control x\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [seqctrl](index.html) module"] +pub struct SEQCTRL_SPEC; +impl crate::RegisterSpec for SEQCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [seqctrl::R](R) reader structure"] +impl crate::Readable for SEQCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [seqctrl::W](W) writer structure"] +impl crate::Writable for SEQCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SEQCTRL[%s] +to value 0"] +impl crate::Resettable for SEQCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/dac.rs b/pac/atsamc21g/src/dac.rs new file mode 100644 index 000000000000..255af9263600 --- /dev/null +++ b/pac/atsamc21g/src/dac.rs @@ -0,0 +1,73 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + #[doc = "0x01 - Control B"] + pub ctrlb: crate::Reg, + #[doc = "0x02 - Event Control"] + pub evctrl: crate::Reg, + _reserved3: [u8; 0x01], + #[doc = "0x04 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x05 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x06 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x07 - Status"] + pub status: crate::Reg, + #[doc = "0x08 - Data"] + pub data: crate::Reg, + _reserved8: [u8; 0x02], + #[doc = "0x0c - Data Buffer"] + pub databuf: crate::Reg, + _reserved9: [u8; 0x02], + #[doc = "0x10 - Synchronization Busy"] + pub syncbusy: crate::Reg, + #[doc = "0x14 - Debug Control"] + pub dbgctrl: crate::Reg, +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "Control B"] +pub mod ctrlb; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "Data"] +pub mod data; +#[doc = "DATABUF register accessor: an alias for `Reg`"] +pub type DATABUF = crate::Reg; +#[doc = "Data Buffer"] +pub mod databuf; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Busy"] +pub mod syncbusy; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; diff --git a/pac/atsamc21g/src/dac/ctrla.rs b/pac/atsamc21g/src/dac/ctrla.rs new file mode 100644 index 000000000000..3ff2fbd9c4d5 --- /dev/null +++ b/pac/atsamc21g/src/dac/ctrla.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/dac/ctrlb.rs b/pac/atsamc21g/src/dac/ctrlb.rs new file mode 100644 index 000000000000..ac7d537964e1 --- /dev/null +++ b/pac/atsamc21g/src/dac/ctrlb.rs @@ -0,0 +1,400 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EOEN` reader - External Output Enable"] +pub struct EOEN_R(crate::FieldReader); +impl EOEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EOEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EOEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EOEN` writer - External Output Enable"] +pub struct EOEN_W<'a> { + w: &'a mut W, +} +impl<'a> EOEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `IOEN` reader - Internal Output Enable"] +pub struct IOEN_R(crate::FieldReader); +impl IOEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IOEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IOEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IOEN` writer - Internal Output Enable"] +pub struct IOEN_W<'a> { + w: &'a mut W, +} +impl<'a> IOEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `LEFTADJ` reader - Left Adjusted Data"] +pub struct LEFTADJ_R(crate::FieldReader); +impl LEFTADJ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LEFTADJ_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LEFTADJ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LEFTADJ` writer - Left Adjusted Data"] +pub struct LEFTADJ_W<'a> { + w: &'a mut W, +} +impl<'a> LEFTADJ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `VPD` reader - Voltage Pump Disable"] +pub struct VPD_R(crate::FieldReader); +impl VPD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + VPD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VPD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VPD` writer - Voltage Pump Disable"] +pub struct VPD_W<'a> { + w: &'a mut W, +} +impl<'a> VPD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `DITHER` reader - Dither Enable"] +pub struct DITHER_R(crate::FieldReader); +impl DITHER_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DITHER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHER` writer - Dither Enable"] +pub struct DITHER_W<'a> { + w: &'a mut W, +} +impl<'a> DITHER_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Reference Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum REFSEL_A { + #[doc = "0: Internal 1.0V reference"] + INT1V = 0, + #[doc = "1: AVCC"] + AVCC = 1, + #[doc = "2: External reference"] + VREFP = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: REFSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `REFSEL` reader - Reference Selection"] +pub struct REFSEL_R(crate::FieldReader); +impl REFSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REFSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(REFSEL_A::INT1V), + 1 => Some(REFSEL_A::AVCC), + 2 => Some(REFSEL_A::VREFP), + _ => None, + } + } + #[doc = "Checks if the value of the field is `INT1V`"] + #[inline(always)] + pub fn is_int1v(&self) -> bool { + **self == REFSEL_A::INT1V + } + #[doc = "Checks if the value of the field is `AVCC`"] + #[inline(always)] + pub fn is_avcc(&self) -> bool { + **self == REFSEL_A::AVCC + } + #[doc = "Checks if the value of the field is `VREFP`"] + #[inline(always)] + pub fn is_vrefp(&self) -> bool { + **self == REFSEL_A::VREFP + } +} +impl core::ops::Deref for REFSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REFSEL` writer - Reference Selection"] +pub struct REFSEL_W<'a> { + w: &'a mut W, +} +impl<'a> REFSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: REFSEL_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Internal 1.0V reference"] + #[inline(always)] + pub fn int1v(self) -> &'a mut W { + self.variant(REFSEL_A::INT1V) + } + #[doc = "AVCC"] + #[inline(always)] + pub fn avcc(self) -> &'a mut W { + self.variant(REFSEL_A::AVCC) + } + #[doc = "External reference"] + #[inline(always)] + pub fn vrefp(self) -> &'a mut W { + self.variant(REFSEL_A::VREFP) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 6)) | ((value as u8 & 0x03) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - External Output Enable"] + #[inline(always)] + pub fn eoen(&self) -> EOEN_R { + EOEN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Internal Output Enable"] + #[inline(always)] + pub fn ioen(&self) -> IOEN_R { + IOEN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Left Adjusted Data"] + #[inline(always)] + pub fn leftadj(&self) -> LEFTADJ_R { + LEFTADJ_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Voltage Pump Disable"] + #[inline(always)] + pub fn vpd(&self) -> VPD_R { + VPD_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 5 - Dither Enable"] + #[inline(always)] + pub fn dither(&self) -> DITHER_R { + DITHER_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bits 6:7 - Reference Selection"] + #[inline(always)] + pub fn refsel(&self) -> REFSEL_R { + REFSEL_R::new(((self.bits >> 6) & 0x03) as u8) + } +} +impl W { + #[doc = "Bit 0 - External Output Enable"] + #[inline(always)] + pub fn eoen(&mut self) -> EOEN_W { + EOEN_W { w: self } + } + #[doc = "Bit 1 - Internal Output Enable"] + #[inline(always)] + pub fn ioen(&mut self) -> IOEN_W { + IOEN_W { w: self } + } + #[doc = "Bit 2 - Left Adjusted Data"] + #[inline(always)] + pub fn leftadj(&mut self) -> LEFTADJ_W { + LEFTADJ_W { w: self } + } + #[doc = "Bit 3 - Voltage Pump Disable"] + #[inline(always)] + pub fn vpd(&mut self) -> VPD_W { + VPD_W { w: self } + } + #[doc = "Bit 5 - Dither Enable"] + #[inline(always)] + pub fn dither(&mut self) -> DITHER_W { + DITHER_W { w: self } + } + #[doc = "Bits 6:7 - Reference Selection"] + #[inline(always)] + pub fn refsel(&mut self) -> REFSEL_W { + REFSEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/dac/data.rs b/pac/atsamc21g/src/dac/data.rs new file mode 100644 index 000000000000..d70d1a60e76f --- /dev/null +++ b/pac/atsamc21g/src/dac/data.rs @@ -0,0 +1,62 @@ +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` writer - Data value to be converted"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl W { + #[doc = "Bits 0:15 - Data value to be converted"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u16; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/dac/databuf.rs b/pac/atsamc21g/src/dac/databuf.rs new file mode 100644 index 000000000000..fc2aa61686cd --- /dev/null +++ b/pac/atsamc21g/src/dac/databuf.rs @@ -0,0 +1,62 @@ +#[doc = "Register `DATABUF` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATABUF` writer - Data Buffer"] +pub struct DATABUF_W<'a> { + w: &'a mut W, +} +impl<'a> DATABUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl W { + #[doc = "Bits 0:15 - Data Buffer"] + #[inline(always)] + pub fn databuf(&mut self) -> DATABUF_W { + DATABUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Buffer\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [databuf](index.html) module"] +pub struct DATABUF_SPEC; +impl crate::RegisterSpec for DATABUF_SPEC { + type Ux = u16; +} +#[doc = "`write(|w| ..)` method takes [databuf::W](W) writer structure"] +impl crate::Writable for DATABUF_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATABUF to value 0"] +impl crate::Resettable for DATABUF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/dac/dbgctrl.rs b/pac/atsamc21g/src/dac/dbgctrl.rs new file mode 100644 index 000000000000..53636eb2b339 --- /dev/null +++ b/pac/atsamc21g/src/dac/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Debug Run"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Debug Run"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/dac/evctrl.rs b/pac/atsamc21g/src/dac/evctrl.rs new file mode 100644 index 000000000000..1032a853887d --- /dev/null +++ b/pac/atsamc21g/src/dac/evctrl.rs @@ -0,0 +1,207 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `STARTEI` reader - Start Conversion Event Input"] +pub struct STARTEI_R(crate::FieldReader); +impl STARTEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STARTEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STARTEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STARTEI` writer - Start Conversion Event Input"] +pub struct STARTEI_W<'a> { + w: &'a mut W, +} +impl<'a> STARTEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `EMPTYEO` reader - Data Buffer Empty Event Output"] +pub struct EMPTYEO_R(crate::FieldReader); +impl EMPTYEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EMPTYEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EMPTYEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EMPTYEO` writer - Data Buffer Empty Event Output"] +pub struct EMPTYEO_W<'a> { + w: &'a mut W, +} +impl<'a> EMPTYEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `INVEI` reader - Invert Event Input"] +pub struct INVEI_R(crate::FieldReader); +impl INVEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEI` writer - Invert Event Input"] +pub struct INVEI_W<'a> { + w: &'a mut W, +} +impl<'a> INVEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Start Conversion Event Input"] + #[inline(always)] + pub fn startei(&self) -> STARTEI_R { + STARTEI_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Data Buffer Empty Event Output"] + #[inline(always)] + pub fn emptyeo(&self) -> EMPTYEO_R { + EMPTYEO_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Invert Event Input"] + #[inline(always)] + pub fn invei(&self) -> INVEI_R { + INVEI_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Start Conversion Event Input"] + #[inline(always)] + pub fn startei(&mut self) -> STARTEI_W { + STARTEI_W { w: self } + } + #[doc = "Bit 1 - Data Buffer Empty Event Output"] + #[inline(always)] + pub fn emptyeo(&mut self) -> EMPTYEO_W { + EMPTYEO_W { w: self } + } + #[doc = "Bit 2 - Invert Event Input"] + #[inline(always)] + pub fn invei(&mut self) -> INVEI_W { + INVEI_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/dac/intenclr.rs b/pac/atsamc21g/src/dac/intenclr.rs new file mode 100644 index 000000000000..408feebf63ca --- /dev/null +++ b/pac/atsamc21g/src/dac/intenclr.rs @@ -0,0 +1,160 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `UNDERRUN` reader - Underrun Interrupt Enable"] +pub struct UNDERRUN_R(crate::FieldReader); +impl UNDERRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UNDERRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for UNDERRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `UNDERRUN` writer - Underrun Interrupt Enable"] +pub struct UNDERRUN_W<'a> { + w: &'a mut W, +} +impl<'a> UNDERRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `EMPTY` reader - Data Buffer Empty Interrupt Enable"] +pub struct EMPTY_R(crate::FieldReader); +impl EMPTY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EMPTY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EMPTY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EMPTY` writer - Data Buffer Empty Interrupt Enable"] +pub struct EMPTY_W<'a> { + w: &'a mut W, +} +impl<'a> EMPTY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - Underrun Interrupt Enable"] + #[inline(always)] + pub fn underrun(&self) -> UNDERRUN_R { + UNDERRUN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Data Buffer Empty Interrupt Enable"] + #[inline(always)] + pub fn empty(&self) -> EMPTY_R { + EMPTY_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Underrun Interrupt Enable"] + #[inline(always)] + pub fn underrun(&mut self) -> UNDERRUN_W { + UNDERRUN_W { w: self } + } + #[doc = "Bit 1 - Data Buffer Empty Interrupt Enable"] + #[inline(always)] + pub fn empty(&mut self) -> EMPTY_W { + EMPTY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/dac/intenset.rs b/pac/atsamc21g/src/dac/intenset.rs new file mode 100644 index 000000000000..db38e69ed2e5 --- /dev/null +++ b/pac/atsamc21g/src/dac/intenset.rs @@ -0,0 +1,160 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `UNDERRUN` reader - Underrun Interrupt Enable"] +pub struct UNDERRUN_R(crate::FieldReader); +impl UNDERRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UNDERRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for UNDERRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `UNDERRUN` writer - Underrun Interrupt Enable"] +pub struct UNDERRUN_W<'a> { + w: &'a mut W, +} +impl<'a> UNDERRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `EMPTY` reader - Data Buffer Empty Interrupt Enable"] +pub struct EMPTY_R(crate::FieldReader); +impl EMPTY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EMPTY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EMPTY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EMPTY` writer - Data Buffer Empty Interrupt Enable"] +pub struct EMPTY_W<'a> { + w: &'a mut W, +} +impl<'a> EMPTY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - Underrun Interrupt Enable"] + #[inline(always)] + pub fn underrun(&self) -> UNDERRUN_R { + UNDERRUN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Data Buffer Empty Interrupt Enable"] + #[inline(always)] + pub fn empty(&self) -> EMPTY_R { + EMPTY_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Underrun Interrupt Enable"] + #[inline(always)] + pub fn underrun(&mut self) -> UNDERRUN_W { + UNDERRUN_W { w: self } + } + #[doc = "Bit 1 - Data Buffer Empty Interrupt Enable"] + #[inline(always)] + pub fn empty(&mut self) -> EMPTY_W { + EMPTY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/dac/intflag.rs b/pac/atsamc21g/src/dac/intflag.rs new file mode 100644 index 000000000000..6779ed161d08 --- /dev/null +++ b/pac/atsamc21g/src/dac/intflag.rs @@ -0,0 +1,160 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `UNDERRUN` reader - Underrun"] +pub struct UNDERRUN_R(crate::FieldReader); +impl UNDERRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UNDERRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for UNDERRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `UNDERRUN` writer - Underrun"] +pub struct UNDERRUN_W<'a> { + w: &'a mut W, +} +impl<'a> UNDERRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `EMPTY` reader - Data Buffer Empty"] +pub struct EMPTY_R(crate::FieldReader); +impl EMPTY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EMPTY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EMPTY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EMPTY` writer - Data Buffer Empty"] +pub struct EMPTY_W<'a> { + w: &'a mut W, +} +impl<'a> EMPTY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - Underrun"] + #[inline(always)] + pub fn underrun(&self) -> UNDERRUN_R { + UNDERRUN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Data Buffer Empty"] + #[inline(always)] + pub fn empty(&self) -> EMPTY_R { + EMPTY_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Underrun"] + #[inline(always)] + pub fn underrun(&mut self) -> UNDERRUN_W { + UNDERRUN_W { w: self } + } + #[doc = "Bit 1 - Data Buffer Empty"] + #[inline(always)] + pub fn empty(&mut self) -> EMPTY_W { + EMPTY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/dac/status.rs b/pac/atsamc21g/src/dac/status.rs new file mode 100644 index 000000000000..9b5a27716dab --- /dev/null +++ b/pac/atsamc21g/src/dac/status.rs @@ -0,0 +1,53 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `READY` reader - Ready"] +pub struct READY_R(crate::FieldReader); +impl READY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + READY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for READY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Ready"] + #[inline(always)] + pub fn ready(&self) -> READY_R { + READY_R::new((self.bits & 0x01) != 0) + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/dac/syncbusy.rs b/pac/atsamc21g/src/dac/syncbusy.rs new file mode 100644 index 000000000000..490533dae28e --- /dev/null +++ b/pac/atsamc21g/src/dac/syncbusy.rs @@ -0,0 +1,113 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` reader - Data"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATABUF` reader - Data Buffer"] +pub struct DATABUF_R(crate::FieldReader); +impl DATABUF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DATABUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATABUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Data"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Data Buffer"] + #[inline(always)] + pub fn databuf(&self) -> DATABUF_R { + DATABUF_R::new(((self.bits >> 3) & 0x01) != 0) + } +} +#[doc = "Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/divas.rs b/pac/atsamc21g/src/divas.rs new file mode 100644 index 000000000000..dbc2f5f226da --- /dev/null +++ b/pac/atsamc21g/src/divas.rs @@ -0,0 +1,48 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrla: crate::Reg, + _reserved1: [u8; 0x03], + #[doc = "0x04 - Status"] + pub status: crate::Reg, + _reserved2: [u8; 0x03], + #[doc = "0x08 - Dividend"] + pub dividend: crate::Reg, + #[doc = "0x0c - Divisor"] + pub divisor: crate::Reg, + #[doc = "0x10 - Result"] + pub result: crate::Reg, + #[doc = "0x14 - Remainder"] + pub rem: crate::Reg, + #[doc = "0x18 - Square Root Input"] + pub sqrnum: crate::Reg, +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control"] +pub mod ctrla; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "DIVIDEND register accessor: an alias for `Reg`"] +pub type DIVIDEND = crate::Reg; +#[doc = "Dividend"] +pub mod dividend; +#[doc = "DIVISOR register accessor: an alias for `Reg`"] +pub type DIVISOR = crate::Reg; +#[doc = "Divisor"] +pub mod divisor; +#[doc = "RESULT register accessor: an alias for `Reg`"] +pub type RESULT = crate::Reg; +#[doc = "Result"] +pub mod result; +#[doc = "REM register accessor: an alias for `Reg`"] +pub type REM = crate::Reg; +#[doc = "Remainder"] +pub mod rem; +#[doc = "SQRNUM register accessor: an alias for `Reg`"] +pub type SQRNUM = crate::Reg; +#[doc = "Square Root Input"] +pub mod sqrnum; diff --git a/pac/atsamc21g/src/divas/ctrla.rs b/pac/atsamc21g/src/divas/ctrla.rs new file mode 100644 index 000000000000..7f79349da05c --- /dev/null +++ b/pac/atsamc21g/src/divas/ctrla.rs @@ -0,0 +1,160 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SIGNED` reader - Signed"] +pub struct SIGNED_R(crate::FieldReader); +impl SIGNED_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SIGNED_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SIGNED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SIGNED` writer - Signed"] +pub struct SIGNED_W<'a> { + w: &'a mut W, +} +impl<'a> SIGNED_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `DLZ` reader - Disable Leading Zero Optimization"] +pub struct DLZ_R(crate::FieldReader); +impl DLZ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DLZ_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DLZ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DLZ` writer - Disable Leading Zero Optimization"] +pub struct DLZ_W<'a> { + w: &'a mut W, +} +impl<'a> DLZ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - Signed"] + #[inline(always)] + pub fn signed(&self) -> SIGNED_R { + SIGNED_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Disable Leading Zero Optimization"] + #[inline(always)] + pub fn dlz(&self) -> DLZ_R { + DLZ_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Signed"] + #[inline(always)] + pub fn signed(&mut self) -> SIGNED_W { + SIGNED_W { w: self } + } + #[doc = "Bit 1 - Disable Leading Zero Optimization"] + #[inline(always)] + pub fn dlz(&mut self) -> DLZ_W { + DLZ_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/divas/dividend.rs b/pac/atsamc21g/src/divas/dividend.rs new file mode 100644 index 000000000000..215f44261a6c --- /dev/null +++ b/pac/atsamc21g/src/divas/dividend.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DIVIDEND` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIVIDEND` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIVIDEND` reader - DIVIDEND"] +pub struct DIVIDEND_R(crate::FieldReader); +impl DIVIDEND_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + DIVIDEND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIVIDEND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIVIDEND` writer - DIVIDEND"] +pub struct DIVIDEND_W<'a> { + w: &'a mut W, +} +impl<'a> DIVIDEND_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - DIVIDEND"] + #[inline(always)] + pub fn dividend(&self) -> DIVIDEND_R { + DIVIDEND_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - DIVIDEND"] + #[inline(always)] + pub fn dividend(&mut self) -> DIVIDEND_W { + DIVIDEND_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Dividend\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dividend](index.html) module"] +pub struct DIVIDEND_SPEC; +impl crate::RegisterSpec for DIVIDEND_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dividend::R](R) reader structure"] +impl crate::Readable for DIVIDEND_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dividend::W](W) writer structure"] +impl crate::Writable for DIVIDEND_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DIVIDEND to value 0"] +impl crate::Resettable for DIVIDEND_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/divas/divisor.rs b/pac/atsamc21g/src/divas/divisor.rs new file mode 100644 index 000000000000..b711870a5cd6 --- /dev/null +++ b/pac/atsamc21g/src/divas/divisor.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DIVISOR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIVISOR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIVISOR` reader - DIVISOR"] +pub struct DIVISOR_R(crate::FieldReader); +impl DIVISOR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + DIVISOR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIVISOR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIVISOR` writer - DIVISOR"] +pub struct DIVISOR_W<'a> { + w: &'a mut W, +} +impl<'a> DIVISOR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - DIVISOR"] + #[inline(always)] + pub fn divisor(&self) -> DIVISOR_R { + DIVISOR_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - DIVISOR"] + #[inline(always)] + pub fn divisor(&mut self) -> DIVISOR_W { + DIVISOR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Divisor\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [divisor](index.html) module"] +pub struct DIVISOR_SPEC; +impl crate::RegisterSpec for DIVISOR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [divisor::R](R) reader structure"] +impl crate::Readable for DIVISOR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [divisor::W](W) writer structure"] +impl crate::Writable for DIVISOR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DIVISOR to value 0"] +impl crate::Resettable for DIVISOR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/divas/rem.rs b/pac/atsamc21g/src/divas/rem.rs new file mode 100644 index 000000000000..76f3a90878ed --- /dev/null +++ b/pac/atsamc21g/src/divas/rem.rs @@ -0,0 +1,53 @@ +#[doc = "Register `REM` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `REM` reader - REM"] +pub struct REM_R(crate::FieldReader); +impl REM_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + REM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - REM"] + #[inline(always)] + pub fn rem(&self) -> REM_R { + REM_R::new(self.bits as u32) + } +} +#[doc = "Remainder\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rem](index.html) module"] +pub struct REM_SPEC; +impl crate::RegisterSpec for REM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rem::R](R) reader structure"] +impl crate::Readable for REM_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets REM to value 0"] +impl crate::Resettable for REM_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/divas/result.rs b/pac/atsamc21g/src/divas/result.rs new file mode 100644 index 000000000000..85fc1a025f9e --- /dev/null +++ b/pac/atsamc21g/src/divas/result.rs @@ -0,0 +1,53 @@ +#[doc = "Register `RESULT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `RESULT` reader - RESULT"] +pub struct RESULT_R(crate::FieldReader); +impl RESULT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + RESULT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESULT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - RESULT"] + #[inline(always)] + pub fn result(&self) -> RESULT_R { + RESULT_R::new(self.bits as u32) + } +} +#[doc = "Result\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [result](index.html) module"] +pub struct RESULT_SPEC; +impl crate::RegisterSpec for RESULT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [result::R](R) reader structure"] +impl crate::Readable for RESULT_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets RESULT to value 0"] +impl crate::Resettable for RESULT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/divas/sqrnum.rs b/pac/atsamc21g/src/divas/sqrnum.rs new file mode 100644 index 000000000000..cc0ce6806beb --- /dev/null +++ b/pac/atsamc21g/src/divas/sqrnum.rs @@ -0,0 +1,103 @@ +#[doc = "Register `SQRNUM` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SQRNUM` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SQRNUM` reader - Square Root Input"] +pub struct SQRNUM_R(crate::FieldReader); +impl SQRNUM_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + SQRNUM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SQRNUM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SQRNUM` writer - Square Root Input"] +pub struct SQRNUM_W<'a> { + w: &'a mut W, +} +impl<'a> SQRNUM_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Square Root Input"] + #[inline(always)] + pub fn sqrnum(&self) -> SQRNUM_R { + SQRNUM_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Square Root Input"] + #[inline(always)] + pub fn sqrnum(&mut self) -> SQRNUM_W { + SQRNUM_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Square Root Input\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sqrnum](index.html) module"] +pub struct SQRNUM_SPEC; +impl crate::RegisterSpec for SQRNUM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [sqrnum::R](R) reader structure"] +impl crate::Readable for SQRNUM_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [sqrnum::W](W) writer structure"] +impl crate::Writable for SQRNUM_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SQRNUM to value 0"] +impl crate::Resettable for SQRNUM_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/divas/status.rs b/pac/atsamc21g/src/divas/status.rs new file mode 100644 index 000000000000..feffbccec659 --- /dev/null +++ b/pac/atsamc21g/src/divas/status.rs @@ -0,0 +1,160 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BUSY` reader - DIVAS Accelerator Busy"] +pub struct BUSY_R(crate::FieldReader); +impl BUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSY` writer - DIVAS Accelerator Busy"] +pub struct BUSY_W<'a> { + w: &'a mut W, +} +impl<'a> BUSY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `DBZ` reader - Writing a one to this bit clears DBZ to zero"] +pub struct DBZ_R(crate::FieldReader); +impl DBZ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBZ_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBZ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBZ` writer - Writing a one to this bit clears DBZ to zero"] +pub struct DBZ_W<'a> { + w: &'a mut W, +} +impl<'a> DBZ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - DIVAS Accelerator Busy"] + #[inline(always)] + pub fn busy(&self) -> BUSY_R { + BUSY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Writing a one to this bit clears DBZ to zero"] + #[inline(always)] + pub fn dbz(&self) -> DBZ_R { + DBZ_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - DIVAS Accelerator Busy"] + #[inline(always)] + pub fn busy(&mut self) -> BUSY_W { + BUSY_W { w: self } + } + #[doc = "Bit 1 - Writing a one to this bit clears DBZ to zero"] + #[inline(always)] + pub fn dbz(&mut self) -> DBZ_W { + DBZ_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/dmac.rs b/pac/atsamc21g/src/dmac.rs new file mode 100644 index 000000000000..c23d36697550 --- /dev/null +++ b/pac/atsamc21g/src/dmac.rs @@ -0,0 +1,148 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrl: crate::Reg, + #[doc = "0x02 - CRC Control"] + pub crcctrl: crate::Reg, + #[doc = "0x04 - CRC Data Input"] + pub crcdatain: crate::Reg, + #[doc = "0x08 - CRC Checksum"] + pub crcchksum: crate::Reg, + #[doc = "0x0c - CRC Status"] + pub crcstatus: crate::Reg, + #[doc = "0x0d - Debug Control"] + pub dbgctrl: crate::Reg, + #[doc = "0x0e - QOS Control"] + pub qosctrl: crate::Reg, + _reserved7: [u8; 0x01], + #[doc = "0x10 - Software Trigger Control"] + pub swtrigctrl: crate::Reg, + #[doc = "0x14 - Priority Control 0"] + pub prictrl0: crate::Reg, + _reserved9: [u8; 0x08], + #[doc = "0x20 - Interrupt Pending"] + pub intpend: crate::Reg, + _reserved10: [u8; 0x02], + #[doc = "0x24 - Interrupt Status"] + pub intstatus: crate::Reg, + #[doc = "0x28 - Busy Channels"] + pub busych: crate::Reg, + #[doc = "0x2c - Pending Channels"] + pub pendch: crate::Reg, + #[doc = "0x30 - Active Channel and Levels"] + pub active: crate::Reg, + #[doc = "0x34 - Descriptor Memory Section Base Address"] + pub baseaddr: crate::Reg, + #[doc = "0x38 - Write-Back Memory Section Base Address"] + pub wrbaddr: crate::Reg, + _reserved16: [u8; 0x03], + #[doc = "0x3f - Channel ID"] + pub chid: crate::Reg, + #[doc = "0x40 - Channel Control A"] + pub chctrla: crate::Reg, + _reserved18: [u8; 0x03], + #[doc = "0x44 - Channel Control B"] + pub chctrlb: crate::Reg, + _reserved19: [u8; 0x04], + #[doc = "0x4c - Channel Interrupt Enable Clear"] + pub chintenclr: crate::Reg, + #[doc = "0x4d - Channel Interrupt Enable Set"] + pub chintenset: crate::Reg, + #[doc = "0x4e - Channel Interrupt Flag Status and Clear"] + pub chintflag: crate::Reg, + #[doc = "0x4f - Channel Status"] + pub chstatus: crate::Reg, +} +#[doc = "CTRL register accessor: an alias for `Reg`"] +pub type CTRL = crate::Reg; +#[doc = "Control"] +pub mod ctrl; +#[doc = "CRCCTRL register accessor: an alias for `Reg`"] +pub type CRCCTRL = crate::Reg; +#[doc = "CRC Control"] +pub mod crcctrl; +#[doc = "CRCDATAIN register accessor: an alias for `Reg`"] +pub type CRCDATAIN = crate::Reg; +#[doc = "CRC Data Input"] +pub mod crcdatain; +#[doc = "CRCCHKSUM register accessor: an alias for `Reg`"] +pub type CRCCHKSUM = crate::Reg; +#[doc = "CRC Checksum"] +pub mod crcchksum; +#[doc = "CRCSTATUS register accessor: an alias for `Reg`"] +pub type CRCSTATUS = crate::Reg; +#[doc = "CRC Status"] +pub mod crcstatus; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "QOSCTRL register accessor: an alias for `Reg`"] +pub type QOSCTRL = crate::Reg; +#[doc = "QOS Control"] +pub mod qosctrl; +#[doc = "SWTRIGCTRL register accessor: an alias for `Reg`"] +pub type SWTRIGCTRL = crate::Reg; +#[doc = "Software Trigger Control"] +pub mod swtrigctrl; +#[doc = "PRICTRL0 register accessor: an alias for `Reg`"] +pub type PRICTRL0 = crate::Reg; +#[doc = "Priority Control 0"] +pub mod prictrl0; +#[doc = "INTPEND register accessor: an alias for `Reg`"] +pub type INTPEND = crate::Reg; +#[doc = "Interrupt Pending"] +pub mod intpend; +#[doc = "INTSTATUS register accessor: an alias for `Reg`"] +pub type INTSTATUS = crate::Reg; +#[doc = "Interrupt Status"] +pub mod intstatus; +#[doc = "BUSYCH register accessor: an alias for `Reg`"] +pub type BUSYCH = crate::Reg; +#[doc = "Busy Channels"] +pub mod busych; +#[doc = "PENDCH register accessor: an alias for `Reg`"] +pub type PENDCH = crate::Reg; +#[doc = "Pending Channels"] +pub mod pendch; +#[doc = "ACTIVE register accessor: an alias for `Reg`"] +pub type ACTIVE = crate::Reg; +#[doc = "Active Channel and Levels"] +pub mod active; +#[doc = "BASEADDR register accessor: an alias for `Reg`"] +pub type BASEADDR = crate::Reg; +#[doc = "Descriptor Memory Section Base Address"] +pub mod baseaddr; +#[doc = "WRBADDR register accessor: an alias for `Reg`"] +pub type WRBADDR = crate::Reg; +#[doc = "Write-Back Memory Section Base Address"] +pub mod wrbaddr; +#[doc = "CHID register accessor: an alias for `Reg`"] +pub type CHID = crate::Reg; +#[doc = "Channel ID"] +pub mod chid; +#[doc = "CHCTRLA register accessor: an alias for `Reg`"] +pub type CHCTRLA = crate::Reg; +#[doc = "Channel Control A"] +pub mod chctrla; +#[doc = "CHCTRLB register accessor: an alias for `Reg`"] +pub type CHCTRLB = crate::Reg; +#[doc = "Channel Control B"] +pub mod chctrlb; +#[doc = "CHINTENCLR register accessor: an alias for `Reg`"] +pub type CHINTENCLR = crate::Reg; +#[doc = "Channel Interrupt Enable Clear"] +pub mod chintenclr; +#[doc = "CHINTENSET register accessor: an alias for `Reg`"] +pub type CHINTENSET = crate::Reg; +#[doc = "Channel Interrupt Enable Set"] +pub mod chintenset; +#[doc = "CHINTFLAG register accessor: an alias for `Reg`"] +pub type CHINTFLAG = crate::Reg; +#[doc = "Channel Interrupt Flag Status and Clear"] +pub mod chintflag; +#[doc = "CHSTATUS register accessor: an alias for `Reg`"] +pub type CHSTATUS = crate::Reg; +#[doc = "Channel Status"] +pub mod chstatus; diff --git a/pac/atsamc21g/src/dmac/active.rs b/pac/atsamc21g/src/dmac/active.rs new file mode 100644 index 000000000000..c3cc5a0420bc --- /dev/null +++ b/pac/atsamc21g/src/dmac/active.rs @@ -0,0 +1,173 @@ +#[doc = "Register `ACTIVE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `LVLEX0` reader - Level 0 Channel Trigger Request Executing"] +pub struct LVLEX0_R(crate::FieldReader); +impl LVLEX0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LVLEX0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEX0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLEX1` reader - Level 1 Channel Trigger Request Executing"] +pub struct LVLEX1_R(crate::FieldReader); +impl LVLEX1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LVLEX1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEX1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLEX2` reader - Level 2 Channel Trigger Request Executing"] +pub struct LVLEX2_R(crate::FieldReader); +impl LVLEX2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LVLEX2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEX2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLEX3` reader - Level 3 Channel Trigger Request Executing"] +pub struct LVLEX3_R(crate::FieldReader); +impl LVLEX3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LVLEX3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEX3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ID` reader - Active Channel ID"] +pub struct ID_R(crate::FieldReader); +impl ID_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ID_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ID_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ABUSY` reader - Active Channel Busy"] +pub struct ABUSY_R(crate::FieldReader); +impl ABUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ABUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ABUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BTCNT` reader - Active Channel Block Transfer Count"] +pub struct BTCNT_R(crate::FieldReader); +impl BTCNT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BTCNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BTCNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Level 0 Channel Trigger Request Executing"] + #[inline(always)] + pub fn lvlex0(&self) -> LVLEX0_R { + LVLEX0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Level 1 Channel Trigger Request Executing"] + #[inline(always)] + pub fn lvlex1(&self) -> LVLEX1_R { + LVLEX1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Level 2 Channel Trigger Request Executing"] + #[inline(always)] + pub fn lvlex2(&self) -> LVLEX2_R { + LVLEX2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Level 3 Channel Trigger Request Executing"] + #[inline(always)] + pub fn lvlex3(&self) -> LVLEX3_R { + LVLEX3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bits 8:12 - Active Channel ID"] + #[inline(always)] + pub fn id(&self) -> ID_R { + ID_R::new(((self.bits >> 8) & 0x1f) as u8) + } + #[doc = "Bit 15 - Active Channel Busy"] + #[inline(always)] + pub fn abusy(&self) -> ABUSY_R { + ABUSY_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:31 - Active Channel Block Transfer Count"] + #[inline(always)] + pub fn btcnt(&self) -> BTCNT_R { + BTCNT_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[doc = "Active Channel and Levels\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [active](index.html) module"] +pub struct ACTIVE_SPEC; +impl crate::RegisterSpec for ACTIVE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [active::R](R) reader structure"] +impl crate::Readable for ACTIVE_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets ACTIVE to value 0"] +impl crate::Resettable for ACTIVE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/dmac/baseaddr.rs b/pac/atsamc21g/src/dmac/baseaddr.rs new file mode 100644 index 000000000000..cec8c8cf0777 --- /dev/null +++ b/pac/atsamc21g/src/dmac/baseaddr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `BASEADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BASEADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BASEADDR` reader - Descriptor Memory Base Address"] +pub struct BASEADDR_R(crate::FieldReader); +impl BASEADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + BASEADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BASEADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BASEADDR` writer - Descriptor Memory Base Address"] +pub struct BASEADDR_W<'a> { + w: &'a mut W, +} +impl<'a> BASEADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Descriptor Memory Base Address"] + #[inline(always)] + pub fn baseaddr(&self) -> BASEADDR_R { + BASEADDR_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Descriptor Memory Base Address"] + #[inline(always)] + pub fn baseaddr(&mut self) -> BASEADDR_W { + BASEADDR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Descriptor Memory Section Base Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baseaddr](index.html) module"] +pub struct BASEADDR_SPEC; +impl crate::RegisterSpec for BASEADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [baseaddr::R](R) reader structure"] +impl crate::Readable for BASEADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baseaddr::W](W) writer structure"] +impl crate::Writable for BASEADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BASEADDR to value 0"] +impl crate::Resettable for BASEADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/dmac/busych.rs b/pac/atsamc21g/src/dmac/busych.rs new file mode 100644 index 000000000000..6f9419d5828b --- /dev/null +++ b/pac/atsamc21g/src/dmac/busych.rs @@ -0,0 +1,273 @@ +#[doc = "Register `BUSYCH` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `BUSYCH0` reader - Busy Channel 0"] +pub struct BUSYCH0_R(crate::FieldReader); +impl BUSYCH0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH1` reader - Busy Channel 1"] +pub struct BUSYCH1_R(crate::FieldReader); +impl BUSYCH1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH2` reader - Busy Channel 2"] +pub struct BUSYCH2_R(crate::FieldReader); +impl BUSYCH2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH3` reader - Busy Channel 3"] +pub struct BUSYCH3_R(crate::FieldReader); +impl BUSYCH3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH4` reader - Busy Channel 4"] +pub struct BUSYCH4_R(crate::FieldReader); +impl BUSYCH4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH5` reader - Busy Channel 5"] +pub struct BUSYCH5_R(crate::FieldReader); +impl BUSYCH5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH6` reader - Busy Channel 6"] +pub struct BUSYCH6_R(crate::FieldReader); +impl BUSYCH6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH7` reader - Busy Channel 7"] +pub struct BUSYCH7_R(crate::FieldReader); +impl BUSYCH7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH8` reader - Busy Channel 8"] +pub struct BUSYCH8_R(crate::FieldReader); +impl BUSYCH8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH9` reader - Busy Channel 9"] +pub struct BUSYCH9_R(crate::FieldReader); +impl BUSYCH9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH10` reader - Busy Channel 10"] +pub struct BUSYCH10_R(crate::FieldReader); +impl BUSYCH10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH11` reader - Busy Channel 11"] +pub struct BUSYCH11_R(crate::FieldReader); +impl BUSYCH11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Busy Channel 0"] + #[inline(always)] + pub fn busych0(&self) -> BUSYCH0_R { + BUSYCH0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Busy Channel 1"] + #[inline(always)] + pub fn busych1(&self) -> BUSYCH1_R { + BUSYCH1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Busy Channel 2"] + #[inline(always)] + pub fn busych2(&self) -> BUSYCH2_R { + BUSYCH2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Busy Channel 3"] + #[inline(always)] + pub fn busych3(&self) -> BUSYCH3_R { + BUSYCH3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Busy Channel 4"] + #[inline(always)] + pub fn busych4(&self) -> BUSYCH4_R { + BUSYCH4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Busy Channel 5"] + #[inline(always)] + pub fn busych5(&self) -> BUSYCH5_R { + BUSYCH5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Busy Channel 6"] + #[inline(always)] + pub fn busych6(&self) -> BUSYCH6_R { + BUSYCH6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Busy Channel 7"] + #[inline(always)] + pub fn busych7(&self) -> BUSYCH7_R { + BUSYCH7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Busy Channel 8"] + #[inline(always)] + pub fn busych8(&self) -> BUSYCH8_R { + BUSYCH8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Busy Channel 9"] + #[inline(always)] + pub fn busych9(&self) -> BUSYCH9_R { + BUSYCH9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Busy Channel 10"] + #[inline(always)] + pub fn busych10(&self) -> BUSYCH10_R { + BUSYCH10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Busy Channel 11"] + #[inline(always)] + pub fn busych11(&self) -> BUSYCH11_R { + BUSYCH11_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +#[doc = "Busy Channels\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [busych](index.html) module"] +pub struct BUSYCH_SPEC; +impl crate::RegisterSpec for BUSYCH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [busych::R](R) reader structure"] +impl crate::Readable for BUSYCH_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets BUSYCH to value 0"] +impl crate::Resettable for BUSYCH_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/dmac/chctrla.rs b/pac/atsamc21g/src/dmac/chctrla.rs new file mode 100644 index 000000000000..22e8d456e05c --- /dev/null +++ b/pac/atsamc21g/src/dmac/chctrla.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CHCTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHCTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Channel Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Channel Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Channel Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Channel Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Channel run in standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Channel run in standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - Channel Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 6 - Channel run in standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Channel Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 6 - Channel run in standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chctrla](index.html) module"] +pub struct CHCTRLA_SPEC; +impl crate::RegisterSpec for CHCTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [chctrla::R](R) reader structure"] +impl crate::Readable for CHCTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chctrla::W](W) writer structure"] +impl crate::Writable for CHCTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHCTRLA to value 0"] +impl crate::Resettable for CHCTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/dmac/chctrlb.rs b/pac/atsamc21g/src/dmac/chctrlb.rs new file mode 100644 index 000000000000..6299733fed6d --- /dev/null +++ b/pac/atsamc21g/src/dmac/chctrlb.rs @@ -0,0 +1,1318 @@ +#[doc = "Register `CHCTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHCTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Event Input Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EVACT_A { + #[doc = "0: No action"] + NOACT = 0, + #[doc = "1: Transfer and periodic transfer trigger"] + TRIG = 1, + #[doc = "2: Conditional transfer trigger"] + CTRIG = 2, + #[doc = "3: Conditional block transfer"] + CBLOCK = 3, + #[doc = "4: Channel suspend operation"] + SUSPEND = 4, + #[doc = "5: Channel resume operation"] + RESUME = 5, + #[doc = "6: Skip next block suspend action"] + SSKIP = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EVACT_A) -> Self { + variant as _ + } +} +#[doc = "Field `EVACT` reader - Event Input Action"] +pub struct EVACT_R(crate::FieldReader); +impl EVACT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(EVACT_A::NOACT), + 1 => Some(EVACT_A::TRIG), + 2 => Some(EVACT_A::CTRIG), + 3 => Some(EVACT_A::CBLOCK), + 4 => Some(EVACT_A::SUSPEND), + 5 => Some(EVACT_A::RESUME), + 6 => Some(EVACT_A::SSKIP), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NOACT`"] + #[inline(always)] + pub fn is_noact(&self) -> bool { + **self == EVACT_A::NOACT + } + #[doc = "Checks if the value of the field is `TRIG`"] + #[inline(always)] + pub fn is_trig(&self) -> bool { + **self == EVACT_A::TRIG + } + #[doc = "Checks if the value of the field is `CTRIG`"] + #[inline(always)] + pub fn is_ctrig(&self) -> bool { + **self == EVACT_A::CTRIG + } + #[doc = "Checks if the value of the field is `CBLOCK`"] + #[inline(always)] + pub fn is_cblock(&self) -> bool { + **self == EVACT_A::CBLOCK + } + #[doc = "Checks if the value of the field is `SUSPEND`"] + #[inline(always)] + pub fn is_suspend(&self) -> bool { + **self == EVACT_A::SUSPEND + } + #[doc = "Checks if the value of the field is `RESUME`"] + #[inline(always)] + pub fn is_resume(&self) -> bool { + **self == EVACT_A::RESUME + } + #[doc = "Checks if the value of the field is `SSKIP`"] + #[inline(always)] + pub fn is_sskip(&self) -> bool { + **self == EVACT_A::SSKIP + } +} +impl core::ops::Deref for EVACT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT` writer - Event Input Action"] +pub struct EVACT_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EVACT_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn noact(self) -> &'a mut W { + self.variant(EVACT_A::NOACT) + } + #[doc = "Transfer and periodic transfer trigger"] + #[inline(always)] + pub fn trig(self) -> &'a mut W { + self.variant(EVACT_A::TRIG) + } + #[doc = "Conditional transfer trigger"] + #[inline(always)] + pub fn ctrig(self) -> &'a mut W { + self.variant(EVACT_A::CTRIG) + } + #[doc = "Conditional block transfer"] + #[inline(always)] + pub fn cblock(self) -> &'a mut W { + self.variant(EVACT_A::CBLOCK) + } + #[doc = "Channel suspend operation"] + #[inline(always)] + pub fn suspend(self) -> &'a mut W { + self.variant(EVACT_A::SUSPEND) + } + #[doc = "Channel resume operation"] + #[inline(always)] + pub fn resume(self) -> &'a mut W { + self.variant(EVACT_A::RESUME) + } + #[doc = "Skip next block suspend action"] + #[inline(always)] + pub fn sskip(self) -> &'a mut W { + self.variant(EVACT_A::SSKIP) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Field `EVIE` reader - Channel Event Input Enable"] +pub struct EVIE_R(crate::FieldReader); +impl EVIE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVIE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVIE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVIE` writer - Channel Event Input Enable"] +pub struct EVIE_W<'a> { + w: &'a mut W, +} +impl<'a> EVIE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `EVOE` reader - Channel Event Output Enable"] +pub struct EVOE_R(crate::FieldReader); +impl EVOE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVOE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVOE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVOE` writer - Channel Event Output Enable"] +pub struct EVOE_W<'a> { + w: &'a mut W, +} +impl<'a> EVOE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Channel Arbitration Level\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum LVL_A { + #[doc = "0: Channel Priority Level 0"] + LVL0 = 0, + #[doc = "1: Channel Priority Level 1"] + LVL1 = 1, + #[doc = "2: Channel Priority Level 2"] + LVL2 = 2, + #[doc = "3: Channel Priority Level 3"] + LVL3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LVL_A) -> Self { + variant as _ + } +} +#[doc = "Field `LVL` reader - Channel Arbitration Level"] +pub struct LVL_R(crate::FieldReader); +impl LVL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LVL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> LVL_A { + match self.bits { + 0 => LVL_A::LVL0, + 1 => LVL_A::LVL1, + 2 => LVL_A::LVL2, + 3 => LVL_A::LVL3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `LVL0`"] + #[inline(always)] + pub fn is_lvl0(&self) -> bool { + **self == LVL_A::LVL0 + } + #[doc = "Checks if the value of the field is `LVL1`"] + #[inline(always)] + pub fn is_lvl1(&self) -> bool { + **self == LVL_A::LVL1 + } + #[doc = "Checks if the value of the field is `LVL2`"] + #[inline(always)] + pub fn is_lvl2(&self) -> bool { + **self == LVL_A::LVL2 + } + #[doc = "Checks if the value of the field is `LVL3`"] + #[inline(always)] + pub fn is_lvl3(&self) -> bool { + **self == LVL_A::LVL3 + } +} +impl core::ops::Deref for LVL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVL` writer - Channel Arbitration Level"] +pub struct LVL_W<'a> { + w: &'a mut W, +} +impl<'a> LVL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: LVL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Channel Priority Level 0"] + #[inline(always)] + pub fn lvl0(self) -> &'a mut W { + self.variant(LVL_A::LVL0) + } + #[doc = "Channel Priority Level 1"] + #[inline(always)] + pub fn lvl1(self) -> &'a mut W { + self.variant(LVL_A::LVL1) + } + #[doc = "Channel Priority Level 2"] + #[inline(always)] + pub fn lvl2(self) -> &'a mut W { + self.variant(LVL_A::LVL2) + } + #[doc = "Channel Priority Level 3"] + #[inline(always)] + pub fn lvl3(self) -> &'a mut W { + self.variant(LVL_A::LVL3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 5)) | ((value as u32 & 0x03) << 5); + self.w + } +} +#[doc = "Trigger Source\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum TRIGSRC_A { + #[doc = "0: Only software/event triggers"] + DISABLE = 0, + #[doc = "1: TSENS Result Ready Trigger"] + TSENS = 1, + #[doc = "2: SERCOM0 RX Trigger"] + SERCOM0_RX = 2, + #[doc = "3: SERCOM0 TX Trigger"] + SERCOM0_TX = 3, + #[doc = "4: SERCOM1 RX Trigger"] + SERCOM1_RX = 4, + #[doc = "5: SERCOM1 TX Trigger"] + SERCOM1_TX = 5, + #[doc = "6: SERCOM2 RX Trigger"] + SERCOM2_RX = 6, + #[doc = "7: SERCOM2 TX Trigger"] + SERCOM2_TX = 7, + #[doc = "8: SERCOM3 RX Trigger"] + SERCOM3_RX = 8, + #[doc = "9: SERCOM3 TX Trigger"] + SERCOM3_TX = 9, + #[doc = "10: SERCOM4 RX Trigger"] + SERCOM4_RX = 10, + #[doc = "11: SERCOM4 TX Trigger"] + SERCOM4_TX = 11, + #[doc = "12: SERCOM5 RX Trigger"] + SERCOM5_RX = 12, + #[doc = "13: SERCOM5 TX Trigger"] + SERCOM5_TX = 13, + #[doc = "14: CAN0 Debug Trigger Reserved"] + CAN0_DEBUG = 14, + #[doc = "15: CAN1 Debug Trigger Reserved"] + CAN1_DEBUG = 15, + #[doc = "16: TCC0 Overflow Trigger"] + TCC0_OVF = 16, + #[doc = "17: TCC0 Match/Compare 0 Trigger"] + TCC0_MC0 = 17, + #[doc = "18: TCC0 Match/Compare 1 Trigger"] + TCC0_MC1 = 18, + #[doc = "19: TCC0 Match/Compare 2 Trigger"] + TCC0_MC2 = 19, + #[doc = "20: TCC0 Match/Compare 3 Trigger"] + TCC0_MC3 = 20, + #[doc = "21: TCC1 Overflow Trigger"] + TCC1_OVF = 21, + #[doc = "22: TCC1 Match/Compare 0 Trigger"] + TCC1_MC0 = 22, + #[doc = "23: TCC1 Match/Compare 1 Trigger"] + TCC1_MC1 = 23, + #[doc = "24: TCC2 Overflow Trigger"] + TCC2_OVF = 24, + #[doc = "25: TCC2 Match/Compare 0 Trigger"] + TCC2_MC0 = 25, + #[doc = "26: TCC2 Match/Compare 1 Trigger"] + TCC2_MC1 = 26, + #[doc = "27: TC0 Overflow Trigger"] + TC0_OVF = 27, + #[doc = "28: TC0 Match/Compare 0 Trigger"] + TC0_MC0 = 28, + #[doc = "29: TC0 Match/Compare 1 Trigger"] + TC0_MC1 = 29, + #[doc = "30: TC1 Overflow Trigger"] + TC1_OVF = 30, + #[doc = "31: TC1 Match/Compare 0 Trigger"] + TC1_MC0 = 31, + #[doc = "32: TC1 Match/Compare 1 Trigger"] + TC1_MC1 = 32, + #[doc = "33: TC2 Overflow Trigger"] + TC2_OVF = 33, + #[doc = "34: TC2 Match/Compare 0 Trigger"] + TC2_MC0 = 34, + #[doc = "35: TC2 Match/Compare 1 Trigger"] + TC2_MC1 = 35, + #[doc = "36: TC3 Overflow Trigger"] + TC3_OVF = 36, + #[doc = "37: TC3 Match/Compare 0 Trigger"] + TC3_MC0 = 37, + #[doc = "38: TC3 Match/Compare 1 Trigger"] + TC3_MC1 = 38, + #[doc = "39: TC4 Overflow Trigger"] + TC4_OVF = 39, + #[doc = "40: TC4 Match/Compare 0 Trigger"] + TC4_MC0 = 40, + #[doc = "41: TC4 Match/Compare 1 Trigger"] + TC4_MC1 = 41, + #[doc = "42: ADC0 Result Ready Trigger"] + ADC0_RESRDY = 42, + #[doc = "43: ADC1 Result Ready Trigger"] + ADC1_RESRDY = 43, + #[doc = "44: SDADC Result Ready Trigger"] + SDADC_RESRDY = 44, + #[doc = "45: DAC Empty Trigger"] + DAC_EMPTY = 45, + #[doc = "46: PTC End of Conversion Trigger"] + PTC_EOC = 46, + #[doc = "47: PTC Window Compare Trigger"] + PTC_WCOMP = 47, + #[doc = "48: PTC Sequence Trigger"] + PTC_SEQ = 48, +} +impl From for u8 { + #[inline(always)] + fn from(variant: TRIGSRC_A) -> Self { + variant as _ + } +} +#[doc = "Field `TRIGSRC` reader - Trigger Source"] +pub struct TRIGSRC_R(crate::FieldReader); +impl TRIGSRC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TRIGSRC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(TRIGSRC_A::DISABLE), + 1 => Some(TRIGSRC_A::TSENS), + 2 => Some(TRIGSRC_A::SERCOM0_RX), + 3 => Some(TRIGSRC_A::SERCOM0_TX), + 4 => Some(TRIGSRC_A::SERCOM1_RX), + 5 => Some(TRIGSRC_A::SERCOM1_TX), + 6 => Some(TRIGSRC_A::SERCOM2_RX), + 7 => Some(TRIGSRC_A::SERCOM2_TX), + 8 => Some(TRIGSRC_A::SERCOM3_RX), + 9 => Some(TRIGSRC_A::SERCOM3_TX), + 10 => Some(TRIGSRC_A::SERCOM4_RX), + 11 => Some(TRIGSRC_A::SERCOM4_TX), + 12 => Some(TRIGSRC_A::SERCOM5_RX), + 13 => Some(TRIGSRC_A::SERCOM5_TX), + 14 => Some(TRIGSRC_A::CAN0_DEBUG), + 15 => Some(TRIGSRC_A::CAN1_DEBUG), + 16 => Some(TRIGSRC_A::TCC0_OVF), + 17 => Some(TRIGSRC_A::TCC0_MC0), + 18 => Some(TRIGSRC_A::TCC0_MC1), + 19 => Some(TRIGSRC_A::TCC0_MC2), + 20 => Some(TRIGSRC_A::TCC0_MC3), + 21 => Some(TRIGSRC_A::TCC1_OVF), + 22 => Some(TRIGSRC_A::TCC1_MC0), + 23 => Some(TRIGSRC_A::TCC1_MC1), + 24 => Some(TRIGSRC_A::TCC2_OVF), + 25 => Some(TRIGSRC_A::TCC2_MC0), + 26 => Some(TRIGSRC_A::TCC2_MC1), + 27 => Some(TRIGSRC_A::TC0_OVF), + 28 => Some(TRIGSRC_A::TC0_MC0), + 29 => Some(TRIGSRC_A::TC0_MC1), + 30 => Some(TRIGSRC_A::TC1_OVF), + 31 => Some(TRIGSRC_A::TC1_MC0), + 32 => Some(TRIGSRC_A::TC1_MC1), + 33 => Some(TRIGSRC_A::TC2_OVF), + 34 => Some(TRIGSRC_A::TC2_MC0), + 35 => Some(TRIGSRC_A::TC2_MC1), + 36 => Some(TRIGSRC_A::TC3_OVF), + 37 => Some(TRIGSRC_A::TC3_MC0), + 38 => Some(TRIGSRC_A::TC3_MC1), + 39 => Some(TRIGSRC_A::TC4_OVF), + 40 => Some(TRIGSRC_A::TC4_MC0), + 41 => Some(TRIGSRC_A::TC4_MC1), + 42 => Some(TRIGSRC_A::ADC0_RESRDY), + 43 => Some(TRIGSRC_A::ADC1_RESRDY), + 44 => Some(TRIGSRC_A::SDADC_RESRDY), + 45 => Some(TRIGSRC_A::DAC_EMPTY), + 46 => Some(TRIGSRC_A::PTC_EOC), + 47 => Some(TRIGSRC_A::PTC_WCOMP), + 48 => Some(TRIGSRC_A::PTC_SEQ), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == TRIGSRC_A::DISABLE + } + #[doc = "Checks if the value of the field is `TSENS`"] + #[inline(always)] + pub fn is_tsens(&self) -> bool { + **self == TRIGSRC_A::TSENS + } + #[doc = "Checks if the value of the field is `SERCOM0_RX`"] + #[inline(always)] + pub fn is_sercom0_rx(&self) -> bool { + **self == TRIGSRC_A::SERCOM0_RX + } + #[doc = "Checks if the value of the field is `SERCOM0_TX`"] + #[inline(always)] + pub fn is_sercom0_tx(&self) -> bool { + **self == TRIGSRC_A::SERCOM0_TX + } + #[doc = "Checks if the value of the field is `SERCOM1_RX`"] + #[inline(always)] + pub fn is_sercom1_rx(&self) -> bool { + **self == TRIGSRC_A::SERCOM1_RX + } + #[doc = "Checks if the value of the field is `SERCOM1_TX`"] + #[inline(always)] + pub fn is_sercom1_tx(&self) -> bool { + **self == TRIGSRC_A::SERCOM1_TX + } + #[doc = "Checks if the value of the field is `SERCOM2_RX`"] + #[inline(always)] + pub fn is_sercom2_rx(&self) -> bool { + **self == TRIGSRC_A::SERCOM2_RX + } + #[doc = "Checks if the value of the field is `SERCOM2_TX`"] + #[inline(always)] + pub fn is_sercom2_tx(&self) -> bool { + **self == TRIGSRC_A::SERCOM2_TX + } + #[doc = "Checks if the value of the field is `SERCOM3_RX`"] + #[inline(always)] + pub fn is_sercom3_rx(&self) -> bool { + **self == TRIGSRC_A::SERCOM3_RX + } + #[doc = "Checks if the value of the field is `SERCOM3_TX`"] + #[inline(always)] + pub fn is_sercom3_tx(&self) -> bool { + **self == TRIGSRC_A::SERCOM3_TX + } + #[doc = "Checks if the value of the field is `SERCOM4_RX`"] + #[inline(always)] + pub fn is_sercom4_rx(&self) -> bool { + **self == TRIGSRC_A::SERCOM4_RX + } + #[doc = "Checks if the value of the field is `SERCOM4_TX`"] + #[inline(always)] + pub fn is_sercom4_tx(&self) -> bool { + **self == TRIGSRC_A::SERCOM4_TX + } + #[doc = "Checks if the value of the field is `SERCOM5_RX`"] + #[inline(always)] + pub fn is_sercom5_rx(&self) -> bool { + **self == TRIGSRC_A::SERCOM5_RX + } + #[doc = "Checks if the value of the field is `SERCOM5_TX`"] + #[inline(always)] + pub fn is_sercom5_tx(&self) -> bool { + **self == TRIGSRC_A::SERCOM5_TX + } + #[doc = "Checks if the value of the field is `CAN0_DEBUG`"] + #[inline(always)] + pub fn is_can0_debug(&self) -> bool { + **self == TRIGSRC_A::CAN0_DEBUG + } + #[doc = "Checks if the value of the field is `CAN1_DEBUG`"] + #[inline(always)] + pub fn is_can1_debug(&self) -> bool { + **self == TRIGSRC_A::CAN1_DEBUG + } + #[doc = "Checks if the value of the field is `TCC0_OVF`"] + #[inline(always)] + pub fn is_tcc0_ovf(&self) -> bool { + **self == TRIGSRC_A::TCC0_OVF + } + #[doc = "Checks if the value of the field is `TCC0_MC0`"] + #[inline(always)] + pub fn is_tcc0_mc0(&self) -> bool { + **self == TRIGSRC_A::TCC0_MC0 + } + #[doc = "Checks if the value of the field is `TCC0_MC1`"] + #[inline(always)] + pub fn is_tcc0_mc1(&self) -> bool { + **self == TRIGSRC_A::TCC0_MC1 + } + #[doc = "Checks if the value of the field is `TCC0_MC2`"] + #[inline(always)] + pub fn is_tcc0_mc2(&self) -> bool { + **self == TRIGSRC_A::TCC0_MC2 + } + #[doc = "Checks if the value of the field is `TCC0_MC3`"] + #[inline(always)] + pub fn is_tcc0_mc3(&self) -> bool { + **self == TRIGSRC_A::TCC0_MC3 + } + #[doc = "Checks if the value of the field is `TCC1_OVF`"] + #[inline(always)] + pub fn is_tcc1_ovf(&self) -> bool { + **self == TRIGSRC_A::TCC1_OVF + } + #[doc = "Checks if the value of the field is `TCC1_MC0`"] + #[inline(always)] + pub fn is_tcc1_mc0(&self) -> bool { + **self == TRIGSRC_A::TCC1_MC0 + } + #[doc = "Checks if the value of the field is `TCC1_MC1`"] + #[inline(always)] + pub fn is_tcc1_mc1(&self) -> bool { + **self == TRIGSRC_A::TCC1_MC1 + } + #[doc = "Checks if the value of the field is `TCC2_OVF`"] + #[inline(always)] + pub fn is_tcc2_ovf(&self) -> bool { + **self == TRIGSRC_A::TCC2_OVF + } + #[doc = "Checks if the value of the field is `TCC2_MC0`"] + #[inline(always)] + pub fn is_tcc2_mc0(&self) -> bool { + **self == TRIGSRC_A::TCC2_MC0 + } + #[doc = "Checks if the value of the field is `TCC2_MC1`"] + #[inline(always)] + pub fn is_tcc2_mc1(&self) -> bool { + **self == TRIGSRC_A::TCC2_MC1 + } + #[doc = "Checks if the value of the field is `TC0_OVF`"] + #[inline(always)] + pub fn is_tc0_ovf(&self) -> bool { + **self == TRIGSRC_A::TC0_OVF + } + #[doc = "Checks if the value of the field is `TC0_MC0`"] + #[inline(always)] + pub fn is_tc0_mc0(&self) -> bool { + **self == TRIGSRC_A::TC0_MC0 + } + #[doc = "Checks if the value of the field is `TC0_MC1`"] + #[inline(always)] + pub fn is_tc0_mc1(&self) -> bool { + **self == TRIGSRC_A::TC0_MC1 + } + #[doc = "Checks if the value of the field is `TC1_OVF`"] + #[inline(always)] + pub fn is_tc1_ovf(&self) -> bool { + **self == TRIGSRC_A::TC1_OVF + } + #[doc = "Checks if the value of the field is `TC1_MC0`"] + #[inline(always)] + pub fn is_tc1_mc0(&self) -> bool { + **self == TRIGSRC_A::TC1_MC0 + } + #[doc = "Checks if the value of the field is `TC1_MC1`"] + #[inline(always)] + pub fn is_tc1_mc1(&self) -> bool { + **self == TRIGSRC_A::TC1_MC1 + } + #[doc = "Checks if the value of the field is `TC2_OVF`"] + #[inline(always)] + pub fn is_tc2_ovf(&self) -> bool { + **self == TRIGSRC_A::TC2_OVF + } + #[doc = "Checks if the value of the field is `TC2_MC0`"] + #[inline(always)] + pub fn is_tc2_mc0(&self) -> bool { + **self == TRIGSRC_A::TC2_MC0 + } + #[doc = "Checks if the value of the field is `TC2_MC1`"] + #[inline(always)] + pub fn is_tc2_mc1(&self) -> bool { + **self == TRIGSRC_A::TC2_MC1 + } + #[doc = "Checks if the value of the field is `TC3_OVF`"] + #[inline(always)] + pub fn is_tc3_ovf(&self) -> bool { + **self == TRIGSRC_A::TC3_OVF + } + #[doc = "Checks if the value of the field is `TC3_MC0`"] + #[inline(always)] + pub fn is_tc3_mc0(&self) -> bool { + **self == TRIGSRC_A::TC3_MC0 + } + #[doc = "Checks if the value of the field is `TC3_MC1`"] + #[inline(always)] + pub fn is_tc3_mc1(&self) -> bool { + **self == TRIGSRC_A::TC3_MC1 + } + #[doc = "Checks if the value of the field is `TC4_OVF`"] + #[inline(always)] + pub fn is_tc4_ovf(&self) -> bool { + **self == TRIGSRC_A::TC4_OVF + } + #[doc = "Checks if the value of the field is `TC4_MC0`"] + #[inline(always)] + pub fn is_tc4_mc0(&self) -> bool { + **self == TRIGSRC_A::TC4_MC0 + } + #[doc = "Checks if the value of the field is `TC4_MC1`"] + #[inline(always)] + pub fn is_tc4_mc1(&self) -> bool { + **self == TRIGSRC_A::TC4_MC1 + } + #[doc = "Checks if the value of the field is `ADC0_RESRDY`"] + #[inline(always)] + pub fn is_adc0_resrdy(&self) -> bool { + **self == TRIGSRC_A::ADC0_RESRDY + } + #[doc = "Checks if the value of the field is `ADC1_RESRDY`"] + #[inline(always)] + pub fn is_adc1_resrdy(&self) -> bool { + **self == TRIGSRC_A::ADC1_RESRDY + } + #[doc = "Checks if the value of the field is `SDADC_RESRDY`"] + #[inline(always)] + pub fn is_sdadc_resrdy(&self) -> bool { + **self == TRIGSRC_A::SDADC_RESRDY + } + #[doc = "Checks if the value of the field is `DAC_EMPTY`"] + #[inline(always)] + pub fn is_dac_empty(&self) -> bool { + **self == TRIGSRC_A::DAC_EMPTY + } + #[doc = "Checks if the value of the field is `PTC_EOC`"] + #[inline(always)] + pub fn is_ptc_eoc(&self) -> bool { + **self == TRIGSRC_A::PTC_EOC + } + #[doc = "Checks if the value of the field is `PTC_WCOMP`"] + #[inline(always)] + pub fn is_ptc_wcomp(&self) -> bool { + **self == TRIGSRC_A::PTC_WCOMP + } + #[doc = "Checks if the value of the field is `PTC_SEQ`"] + #[inline(always)] + pub fn is_ptc_seq(&self) -> bool { + **self == TRIGSRC_A::PTC_SEQ + } +} +impl core::ops::Deref for TRIGSRC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRIGSRC` writer - Trigger Source"] +pub struct TRIGSRC_W<'a> { + w: &'a mut W, +} +impl<'a> TRIGSRC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TRIGSRC_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Only software/event triggers"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(TRIGSRC_A::DISABLE) + } + #[doc = "TSENS Result Ready Trigger"] + #[inline(always)] + pub fn tsens(self) -> &'a mut W { + self.variant(TRIGSRC_A::TSENS) + } + #[doc = "SERCOM0 RX Trigger"] + #[inline(always)] + pub fn sercom0_rx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM0_RX) + } + #[doc = "SERCOM0 TX Trigger"] + #[inline(always)] + pub fn sercom0_tx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM0_TX) + } + #[doc = "SERCOM1 RX Trigger"] + #[inline(always)] + pub fn sercom1_rx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM1_RX) + } + #[doc = "SERCOM1 TX Trigger"] + #[inline(always)] + pub fn sercom1_tx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM1_TX) + } + #[doc = "SERCOM2 RX Trigger"] + #[inline(always)] + pub fn sercom2_rx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM2_RX) + } + #[doc = "SERCOM2 TX Trigger"] + #[inline(always)] + pub fn sercom2_tx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM2_TX) + } + #[doc = "SERCOM3 RX Trigger"] + #[inline(always)] + pub fn sercom3_rx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM3_RX) + } + #[doc = "SERCOM3 TX Trigger"] + #[inline(always)] + pub fn sercom3_tx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM3_TX) + } + #[doc = "SERCOM4 RX Trigger"] + #[inline(always)] + pub fn sercom4_rx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM4_RX) + } + #[doc = "SERCOM4 TX Trigger"] + #[inline(always)] + pub fn sercom4_tx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM4_TX) + } + #[doc = "SERCOM5 RX Trigger"] + #[inline(always)] + pub fn sercom5_rx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM5_RX) + } + #[doc = "SERCOM5 TX Trigger"] + #[inline(always)] + pub fn sercom5_tx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM5_TX) + } + #[doc = "CAN0 Debug Trigger Reserved"] + #[inline(always)] + pub fn can0_debug(self) -> &'a mut W { + self.variant(TRIGSRC_A::CAN0_DEBUG) + } + #[doc = "CAN1 Debug Trigger Reserved"] + #[inline(always)] + pub fn can1_debug(self) -> &'a mut W { + self.variant(TRIGSRC_A::CAN1_DEBUG) + } + #[doc = "TCC0 Overflow Trigger"] + #[inline(always)] + pub fn tcc0_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC0_OVF) + } + #[doc = "TCC0 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tcc0_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC0_MC0) + } + #[doc = "TCC0 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tcc0_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC0_MC1) + } + #[doc = "TCC0 Match/Compare 2 Trigger"] + #[inline(always)] + pub fn tcc0_mc2(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC0_MC2) + } + #[doc = "TCC0 Match/Compare 3 Trigger"] + #[inline(always)] + pub fn tcc0_mc3(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC0_MC3) + } + #[doc = "TCC1 Overflow Trigger"] + #[inline(always)] + pub fn tcc1_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC1_OVF) + } + #[doc = "TCC1 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tcc1_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC1_MC0) + } + #[doc = "TCC1 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tcc1_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC1_MC1) + } + #[doc = "TCC2 Overflow Trigger"] + #[inline(always)] + pub fn tcc2_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC2_OVF) + } + #[doc = "TCC2 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tcc2_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC2_MC0) + } + #[doc = "TCC2 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tcc2_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC2_MC1) + } + #[doc = "TC0 Overflow Trigger"] + #[inline(always)] + pub fn tc0_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC0_OVF) + } + #[doc = "TC0 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tc0_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC0_MC0) + } + #[doc = "TC0 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tc0_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC0_MC1) + } + #[doc = "TC1 Overflow Trigger"] + #[inline(always)] + pub fn tc1_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC1_OVF) + } + #[doc = "TC1 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tc1_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC1_MC0) + } + #[doc = "TC1 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tc1_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC1_MC1) + } + #[doc = "TC2 Overflow Trigger"] + #[inline(always)] + pub fn tc2_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC2_OVF) + } + #[doc = "TC2 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tc2_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC2_MC0) + } + #[doc = "TC2 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tc2_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC2_MC1) + } + #[doc = "TC3 Overflow Trigger"] + #[inline(always)] + pub fn tc3_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC3_OVF) + } + #[doc = "TC3 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tc3_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC3_MC0) + } + #[doc = "TC3 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tc3_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC3_MC1) + } + #[doc = "TC4 Overflow Trigger"] + #[inline(always)] + pub fn tc4_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC4_OVF) + } + #[doc = "TC4 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tc4_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC4_MC0) + } + #[doc = "TC4 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tc4_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC4_MC1) + } + #[doc = "ADC0 Result Ready Trigger"] + #[inline(always)] + pub fn adc0_resrdy(self) -> &'a mut W { + self.variant(TRIGSRC_A::ADC0_RESRDY) + } + #[doc = "ADC1 Result Ready Trigger"] + #[inline(always)] + pub fn adc1_resrdy(self) -> &'a mut W { + self.variant(TRIGSRC_A::ADC1_RESRDY) + } + #[doc = "SDADC Result Ready Trigger"] + #[inline(always)] + pub fn sdadc_resrdy(self) -> &'a mut W { + self.variant(TRIGSRC_A::SDADC_RESRDY) + } + #[doc = "DAC Empty Trigger"] + #[inline(always)] + pub fn dac_empty(self) -> &'a mut W { + self.variant(TRIGSRC_A::DAC_EMPTY) + } + #[doc = "PTC End of Conversion Trigger"] + #[inline(always)] + pub fn ptc_eoc(self) -> &'a mut W { + self.variant(TRIGSRC_A::PTC_EOC) + } + #[doc = "PTC Window Compare Trigger"] + #[inline(always)] + pub fn ptc_wcomp(self) -> &'a mut W { + self.variant(TRIGSRC_A::PTC_WCOMP) + } + #[doc = "PTC Sequence Trigger"] + #[inline(always)] + pub fn ptc_seq(self) -> &'a mut W { + self.variant(TRIGSRC_A::PTC_SEQ) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 8)) | ((value as u32 & 0x3f) << 8); + self.w + } +} +#[doc = "Trigger Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum TRIGACT_A { + #[doc = "0: One trigger required for each block transfer"] + BLOCK = 0, + #[doc = "2: One trigger required for each beat transfer"] + BEAT = 2, + #[doc = "3: One trigger required for each transaction"] + TRANSACTION = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: TRIGACT_A) -> Self { + variant as _ + } +} +#[doc = "Field `TRIGACT` reader - Trigger Action"] +pub struct TRIGACT_R(crate::FieldReader); +impl TRIGACT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TRIGACT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(TRIGACT_A::BLOCK), + 2 => Some(TRIGACT_A::BEAT), + 3 => Some(TRIGACT_A::TRANSACTION), + _ => None, + } + } + #[doc = "Checks if the value of the field is `BLOCK`"] + #[inline(always)] + pub fn is_block(&self) -> bool { + **self == TRIGACT_A::BLOCK + } + #[doc = "Checks if the value of the field is `BEAT`"] + #[inline(always)] + pub fn is_beat(&self) -> bool { + **self == TRIGACT_A::BEAT + } + #[doc = "Checks if the value of the field is `TRANSACTION`"] + #[inline(always)] + pub fn is_transaction(&self) -> bool { + **self == TRIGACT_A::TRANSACTION + } +} +impl core::ops::Deref for TRIGACT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRIGACT` writer - Trigger Action"] +pub struct TRIGACT_W<'a> { + w: &'a mut W, +} +impl<'a> TRIGACT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TRIGACT_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "One trigger required for each block transfer"] + #[inline(always)] + pub fn block(self) -> &'a mut W { + self.variant(TRIGACT_A::BLOCK) + } + #[doc = "One trigger required for each beat transfer"] + #[inline(always)] + pub fn beat(self) -> &'a mut W { + self.variant(TRIGACT_A::BEAT) + } + #[doc = "One trigger required for each transaction"] + #[inline(always)] + pub fn transaction(self) -> &'a mut W { + self.variant(TRIGACT_A::TRANSACTION) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 22)) | ((value as u32 & 0x03) << 22); + self.w + } +} +#[doc = "Software Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NOACT = 0, + #[doc = "1: Channel suspend operation"] + SUSPEND = 1, + #[doc = "2: Channel resume operation"] + RESUME = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Software Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NOACT), + 1 => Some(CMD_A::SUSPEND), + 2 => Some(CMD_A::RESUME), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NOACT`"] + #[inline(always)] + pub fn is_noact(&self) -> bool { + **self == CMD_A::NOACT + } + #[doc = "Checks if the value of the field is `SUSPEND`"] + #[inline(always)] + pub fn is_suspend(&self) -> bool { + **self == CMD_A::SUSPEND + } + #[doc = "Checks if the value of the field is `RESUME`"] + #[inline(always)] + pub fn is_resume(&self) -> bool { + **self == CMD_A::RESUME + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Software Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn noact(self) -> &'a mut W { + self.variant(CMD_A::NOACT) + } + #[doc = "Channel suspend operation"] + #[inline(always)] + pub fn suspend(self) -> &'a mut W { + self.variant(CMD_A::SUSPEND) + } + #[doc = "Channel resume operation"] + #[inline(always)] + pub fn resume(self) -> &'a mut W { + self.variant(CMD_A::RESUME) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 24)) | ((value as u32 & 0x03) << 24); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Event Input Action"] + #[inline(always)] + pub fn evact(&self) -> EVACT_R { + EVACT_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 3 - Channel Event Input Enable"] + #[inline(always)] + pub fn evie(&self) -> EVIE_R { + EVIE_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Channel Event Output Enable"] + #[inline(always)] + pub fn evoe(&self) -> EVOE_R { + EVOE_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bits 5:6 - Channel Arbitration Level"] + #[inline(always)] + pub fn lvl(&self) -> LVL_R { + LVL_R::new(((self.bits >> 5) & 0x03) as u8) + } + #[doc = "Bits 8:13 - Trigger Source"] + #[inline(always)] + pub fn trigsrc(&self) -> TRIGSRC_R { + TRIGSRC_R::new(((self.bits >> 8) & 0x3f) as u8) + } + #[doc = "Bits 22:23 - Trigger Action"] + #[inline(always)] + pub fn trigact(&self) -> TRIGACT_R { + TRIGACT_R::new(((self.bits >> 22) & 0x03) as u8) + } + #[doc = "Bits 24:25 - Software Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 24) & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Event Input Action"] + #[inline(always)] + pub fn evact(&mut self) -> EVACT_W { + EVACT_W { w: self } + } + #[doc = "Bit 3 - Channel Event Input Enable"] + #[inline(always)] + pub fn evie(&mut self) -> EVIE_W { + EVIE_W { w: self } + } + #[doc = "Bit 4 - Channel Event Output Enable"] + #[inline(always)] + pub fn evoe(&mut self) -> EVOE_W { + EVOE_W { w: self } + } + #[doc = "Bits 5:6 - Channel Arbitration Level"] + #[inline(always)] + pub fn lvl(&mut self) -> LVL_W { + LVL_W { w: self } + } + #[doc = "Bits 8:13 - Trigger Source"] + #[inline(always)] + pub fn trigsrc(&mut self) -> TRIGSRC_W { + TRIGSRC_W { w: self } + } + #[doc = "Bits 22:23 - Trigger Action"] + #[inline(always)] + pub fn trigact(&mut self) -> TRIGACT_W { + TRIGACT_W { w: self } + } + #[doc = "Bits 24:25 - Software Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chctrlb](index.html) module"] +pub struct CHCTRLB_SPEC; +impl crate::RegisterSpec for CHCTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [chctrlb::R](R) reader structure"] +impl crate::Readable for CHCTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chctrlb::W](W) writer structure"] +impl crate::Writable for CHCTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHCTRLB to value 0"] +impl crate::Resettable for CHCTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/dmac/chid.rs b/pac/atsamc21g/src/dmac/chid.rs new file mode 100644 index 000000000000..19151d8e10b0 --- /dev/null +++ b/pac/atsamc21g/src/dmac/chid.rs @@ -0,0 +1,103 @@ +#[doc = "Register `CHID` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHID` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ID` reader - Channel ID"] +pub struct ID_R(crate::FieldReader); +impl ID_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ID_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ID_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ID` writer - Channel ID"] +pub struct ID_W<'a> { + w: &'a mut W, +} +impl<'a> ID_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Channel ID"] + #[inline(always)] + pub fn id(&self) -> ID_R { + ID_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Channel ID"] + #[inline(always)] + pub fn id(&mut self) -> ID_W { + ID_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel ID\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chid](index.html) module"] +pub struct CHID_SPEC; +impl crate::RegisterSpec for CHID_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [chid::R](R) reader structure"] +impl crate::Readable for CHID_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chid::W](W) writer structure"] +impl crate::Writable for CHID_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHID to value 0"] +impl crate::Resettable for CHID_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/dmac/chintenclr.rs b/pac/atsamc21g/src/dmac/chintenclr.rs new file mode 100644 index 000000000000..5ae3096f9ab8 --- /dev/null +++ b/pac/atsamc21g/src/dmac/chintenclr.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CHINTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHINTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TERR` reader - Channel Transfer Error Interrupt Enable"] +pub struct TERR_R(crate::FieldReader); +impl TERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TERR` writer - Channel Transfer Error Interrupt Enable"] +pub struct TERR_W<'a> { + w: &'a mut W, +} +impl<'a> TERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TCMPL` reader - Channel Transfer Complete Interrupt Enable"] +pub struct TCMPL_R(crate::FieldReader); +impl TCMPL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCMPL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCMPL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCMPL` writer - Channel Transfer Complete Interrupt Enable"] +pub struct TCMPL_W<'a> { + w: &'a mut W, +} +impl<'a> TCMPL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SUSP` reader - Channel Suspend Interrupt Enable"] +pub struct SUSP_R(crate::FieldReader); +impl SUSP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SUSP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SUSP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SUSP` writer - Channel Suspend Interrupt Enable"] +pub struct SUSP_W<'a> { + w: &'a mut W, +} +impl<'a> SUSP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Channel Transfer Error Interrupt Enable"] + #[inline(always)] + pub fn terr(&self) -> TERR_R { + TERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel Transfer Complete Interrupt Enable"] + #[inline(always)] + pub fn tcmpl(&self) -> TCMPL_R { + TCMPL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel Suspend Interrupt Enable"] + #[inline(always)] + pub fn susp(&self) -> SUSP_R { + SUSP_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel Transfer Error Interrupt Enable"] + #[inline(always)] + pub fn terr(&mut self) -> TERR_W { + TERR_W { w: self } + } + #[doc = "Bit 1 - Channel Transfer Complete Interrupt Enable"] + #[inline(always)] + pub fn tcmpl(&mut self) -> TCMPL_W { + TCMPL_W { w: self } + } + #[doc = "Bit 2 - Channel Suspend Interrupt Enable"] + #[inline(always)] + pub fn susp(&mut self) -> SUSP_W { + SUSP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chintenclr](index.html) module"] +pub struct CHINTENCLR_SPEC; +impl crate::RegisterSpec for CHINTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [chintenclr::R](R) reader structure"] +impl crate::Readable for CHINTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chintenclr::W](W) writer structure"] +impl crate::Writable for CHINTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHINTENCLR to value 0"] +impl crate::Resettable for CHINTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/dmac/chintenset.rs b/pac/atsamc21g/src/dmac/chintenset.rs new file mode 100644 index 000000000000..2e7daef20a6f --- /dev/null +++ b/pac/atsamc21g/src/dmac/chintenset.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CHINTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHINTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TERR` reader - Channel Transfer Error Interrupt Enable"] +pub struct TERR_R(crate::FieldReader); +impl TERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TERR` writer - Channel Transfer Error Interrupt Enable"] +pub struct TERR_W<'a> { + w: &'a mut W, +} +impl<'a> TERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TCMPL` reader - Channel Transfer Complete Interrupt Enable"] +pub struct TCMPL_R(crate::FieldReader); +impl TCMPL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCMPL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCMPL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCMPL` writer - Channel Transfer Complete Interrupt Enable"] +pub struct TCMPL_W<'a> { + w: &'a mut W, +} +impl<'a> TCMPL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SUSP` reader - Channel Suspend Interrupt Enable"] +pub struct SUSP_R(crate::FieldReader); +impl SUSP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SUSP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SUSP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SUSP` writer - Channel Suspend Interrupt Enable"] +pub struct SUSP_W<'a> { + w: &'a mut W, +} +impl<'a> SUSP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Channel Transfer Error Interrupt Enable"] + #[inline(always)] + pub fn terr(&self) -> TERR_R { + TERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel Transfer Complete Interrupt Enable"] + #[inline(always)] + pub fn tcmpl(&self) -> TCMPL_R { + TCMPL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel Suspend Interrupt Enable"] + #[inline(always)] + pub fn susp(&self) -> SUSP_R { + SUSP_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel Transfer Error Interrupt Enable"] + #[inline(always)] + pub fn terr(&mut self) -> TERR_W { + TERR_W { w: self } + } + #[doc = "Bit 1 - Channel Transfer Complete Interrupt Enable"] + #[inline(always)] + pub fn tcmpl(&mut self) -> TCMPL_W { + TCMPL_W { w: self } + } + #[doc = "Bit 2 - Channel Suspend Interrupt Enable"] + #[inline(always)] + pub fn susp(&mut self) -> SUSP_W { + SUSP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chintenset](index.html) module"] +pub struct CHINTENSET_SPEC; +impl crate::RegisterSpec for CHINTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [chintenset::R](R) reader structure"] +impl crate::Readable for CHINTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chintenset::W](W) writer structure"] +impl crate::Writable for CHINTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHINTENSET to value 0"] +impl crate::Resettable for CHINTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/dmac/chintflag.rs b/pac/atsamc21g/src/dmac/chintflag.rs new file mode 100644 index 000000000000..4e61d6510c30 --- /dev/null +++ b/pac/atsamc21g/src/dmac/chintflag.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CHINTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHINTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TERR` reader - Channel Transfer Error"] +pub struct TERR_R(crate::FieldReader); +impl TERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TERR` writer - Channel Transfer Error"] +pub struct TERR_W<'a> { + w: &'a mut W, +} +impl<'a> TERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TCMPL` reader - Channel Transfer Complete"] +pub struct TCMPL_R(crate::FieldReader); +impl TCMPL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCMPL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCMPL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCMPL` writer - Channel Transfer Complete"] +pub struct TCMPL_W<'a> { + w: &'a mut W, +} +impl<'a> TCMPL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SUSP` reader - Channel Suspend"] +pub struct SUSP_R(crate::FieldReader); +impl SUSP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SUSP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SUSP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SUSP` writer - Channel Suspend"] +pub struct SUSP_W<'a> { + w: &'a mut W, +} +impl<'a> SUSP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Channel Transfer Error"] + #[inline(always)] + pub fn terr(&self) -> TERR_R { + TERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel Transfer Complete"] + #[inline(always)] + pub fn tcmpl(&self) -> TCMPL_R { + TCMPL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel Suspend"] + #[inline(always)] + pub fn susp(&self) -> SUSP_R { + SUSP_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel Transfer Error"] + #[inline(always)] + pub fn terr(&mut self) -> TERR_W { + TERR_W { w: self } + } + #[doc = "Bit 1 - Channel Transfer Complete"] + #[inline(always)] + pub fn tcmpl(&mut self) -> TCMPL_W { + TCMPL_W { w: self } + } + #[doc = "Bit 2 - Channel Suspend"] + #[inline(always)] + pub fn susp(&mut self) -> SUSP_W { + SUSP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chintflag](index.html) module"] +pub struct CHINTFLAG_SPEC; +impl crate::RegisterSpec for CHINTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [chintflag::R](R) reader structure"] +impl crate::Readable for CHINTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chintflag::W](W) writer structure"] +impl crate::Writable for CHINTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHINTFLAG to value 0"] +impl crate::Resettable for CHINTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/dmac/chstatus.rs b/pac/atsamc21g/src/dmac/chstatus.rs new file mode 100644 index 000000000000..98a84345d4f7 --- /dev/null +++ b/pac/atsamc21g/src/dmac/chstatus.rs @@ -0,0 +1,93 @@ +#[doc = "Register `CHSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PEND` reader - Channel Pending"] +pub struct PEND_R(crate::FieldReader); +impl PEND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSY` reader - Channel Busy"] +pub struct BUSY_R(crate::FieldReader); +impl BUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FERR` reader - Channel Fetch Error"] +pub struct FERR_R(crate::FieldReader); +impl FERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Channel Pending"] + #[inline(always)] + pub fn pend(&self) -> PEND_R { + PEND_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel Busy"] + #[inline(always)] + pub fn busy(&self) -> BUSY_R { + BUSY_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel Fetch Error"] + #[inline(always)] + pub fn ferr(&self) -> FERR_R { + FERR_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +#[doc = "Channel Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chstatus](index.html) module"] +pub struct CHSTATUS_SPEC; +impl crate::RegisterSpec for CHSTATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [chstatus::R](R) reader structure"] +impl crate::Readable for CHSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CHSTATUS to value 0"] +impl crate::Resettable for CHSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/dmac/crcchksum.rs b/pac/atsamc21g/src/dmac/crcchksum.rs new file mode 100644 index 000000000000..89eb5b38a093 --- /dev/null +++ b/pac/atsamc21g/src/dmac/crcchksum.rs @@ -0,0 +1,103 @@ +#[doc = "Register `CRCCHKSUM` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CRCCHKSUM` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CRCCHKSUM` reader - CRC Checksum"] +pub struct CRCCHKSUM_R(crate::FieldReader); +impl CRCCHKSUM_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CRCCHKSUM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CRCCHKSUM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCCHKSUM` writer - CRC Checksum"] +pub struct CRCCHKSUM_W<'a> { + w: &'a mut W, +} +impl<'a> CRCCHKSUM_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - CRC Checksum"] + #[inline(always)] + pub fn crcchksum(&self) -> CRCCHKSUM_R { + CRCCHKSUM_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - CRC Checksum"] + #[inline(always)] + pub fn crcchksum(&mut self) -> CRCCHKSUM_W { + CRCCHKSUM_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CRC Checksum\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [crcchksum](index.html) module"] +pub struct CRCCHKSUM_SPEC; +impl crate::RegisterSpec for CRCCHKSUM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [crcchksum::R](R) reader structure"] +impl crate::Readable for CRCCHKSUM_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [crcchksum::W](W) writer structure"] +impl crate::Writable for CRCCHKSUM_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CRCCHKSUM to value 0"] +impl crate::Resettable for CRCCHKSUM_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/dmac/crcctrl.rs b/pac/atsamc21g/src/dmac/crcctrl.rs new file mode 100644 index 000000000000..b8daf7b8259d --- /dev/null +++ b/pac/atsamc21g/src/dmac/crcctrl.rs @@ -0,0 +1,337 @@ +#[doc = "Register `CRCCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CRCCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "CRC Beat Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CRCBEATSIZE_A { + #[doc = "0: 8-bit bus transfer"] + BYTE = 0, + #[doc = "1: 16-bit bus transfer"] + HWORD = 1, + #[doc = "2: 32-bit bus transfer"] + WORD = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CRCBEATSIZE_A) -> Self { + variant as _ + } +} +#[doc = "Field `CRCBEATSIZE` reader - CRC Beat Size"] +pub struct CRCBEATSIZE_R(crate::FieldReader); +impl CRCBEATSIZE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CRCBEATSIZE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CRCBEATSIZE_A::BYTE), + 1 => Some(CRCBEATSIZE_A::HWORD), + 2 => Some(CRCBEATSIZE_A::WORD), + _ => None, + } + } + #[doc = "Checks if the value of the field is `BYTE`"] + #[inline(always)] + pub fn is_byte(&self) -> bool { + **self == CRCBEATSIZE_A::BYTE + } + #[doc = "Checks if the value of the field is `HWORD`"] + #[inline(always)] + pub fn is_hword(&self) -> bool { + **self == CRCBEATSIZE_A::HWORD + } + #[doc = "Checks if the value of the field is `WORD`"] + #[inline(always)] + pub fn is_word(&self) -> bool { + **self == CRCBEATSIZE_A::WORD + } +} +impl core::ops::Deref for CRCBEATSIZE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCBEATSIZE` writer - CRC Beat Size"] +pub struct CRCBEATSIZE_W<'a> { + w: &'a mut W, +} +impl<'a> CRCBEATSIZE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CRCBEATSIZE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8-bit bus transfer"] + #[inline(always)] + pub fn byte(self) -> &'a mut W { + self.variant(CRCBEATSIZE_A::BYTE) + } + #[doc = "16-bit bus transfer"] + #[inline(always)] + pub fn hword(self) -> &'a mut W { + self.variant(CRCBEATSIZE_A::HWORD) + } + #[doc = "32-bit bus transfer"] + #[inline(always)] + pub fn word(self) -> &'a mut W { + self.variant(CRCBEATSIZE_A::WORD) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u16 & 0x03); + self.w + } +} +#[doc = "CRC Polynomial Type\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CRCPOLY_A { + #[doc = "0: CRC-16 (CRC-CCITT)"] + CRC16 = 0, + #[doc = "1: CRC32 (IEEE 802.3)"] + CRC32 = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CRCPOLY_A) -> Self { + variant as _ + } +} +#[doc = "Field `CRCPOLY` reader - CRC Polynomial Type"] +pub struct CRCPOLY_R(crate::FieldReader); +impl CRCPOLY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CRCPOLY_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CRCPOLY_A::CRC16), + 1 => Some(CRCPOLY_A::CRC32), + _ => None, + } + } + #[doc = "Checks if the value of the field is `CRC16`"] + #[inline(always)] + pub fn is_crc16(&self) -> bool { + **self == CRCPOLY_A::CRC16 + } + #[doc = "Checks if the value of the field is `CRC32`"] + #[inline(always)] + pub fn is_crc32(&self) -> bool { + **self == CRCPOLY_A::CRC32 + } +} +impl core::ops::Deref for CRCPOLY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCPOLY` writer - CRC Polynomial Type"] +pub struct CRCPOLY_W<'a> { + w: &'a mut W, +} +impl<'a> CRCPOLY_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CRCPOLY_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "CRC-16 (CRC-CCITT)"] + #[inline(always)] + pub fn crc16(self) -> &'a mut W { + self.variant(CRCPOLY_A::CRC16) + } + #[doc = "CRC32 (IEEE 802.3)"] + #[inline(always)] + pub fn crc32(self) -> &'a mut W { + self.variant(CRCPOLY_A::CRC32) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u16 & 0x03) << 2); + self.w + } +} +#[doc = "CRC Input Source\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CRCSRC_A { + #[doc = "0: No action"] + NOACT = 0, + #[doc = "1: I/O interface"] + IO = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CRCSRC_A) -> Self { + variant as _ + } +} +#[doc = "Field `CRCSRC` reader - CRC Input Source"] +pub struct CRCSRC_R(crate::FieldReader); +impl CRCSRC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CRCSRC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CRCSRC_A::NOACT), + 1 => Some(CRCSRC_A::IO), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NOACT`"] + #[inline(always)] + pub fn is_noact(&self) -> bool { + **self == CRCSRC_A::NOACT + } + #[doc = "Checks if the value of the field is `IO`"] + #[inline(always)] + pub fn is_io(&self) -> bool { + **self == CRCSRC_A::IO + } +} +impl core::ops::Deref for CRCSRC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCSRC` writer - CRC Input Source"] +pub struct CRCSRC_W<'a> { + w: &'a mut W, +} +impl<'a> CRCSRC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CRCSRC_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn noact(self) -> &'a mut W { + self.variant(CRCSRC_A::NOACT) + } + #[doc = "I/O interface"] + #[inline(always)] + pub fn io(self) -> &'a mut W { + self.variant(CRCSRC_A::IO) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 8)) | ((value as u16 & 0x3f) << 8); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - CRC Beat Size"] + #[inline(always)] + pub fn crcbeatsize(&self) -> CRCBEATSIZE_R { + CRCBEATSIZE_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bits 2:3 - CRC Polynomial Type"] + #[inline(always)] + pub fn crcpoly(&self) -> CRCPOLY_R { + CRCPOLY_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bits 8:13 - CRC Input Source"] + #[inline(always)] + pub fn crcsrc(&self) -> CRCSRC_R { + CRCSRC_R::new(((self.bits >> 8) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - CRC Beat Size"] + #[inline(always)] + pub fn crcbeatsize(&mut self) -> CRCBEATSIZE_W { + CRCBEATSIZE_W { w: self } + } + #[doc = "Bits 2:3 - CRC Polynomial Type"] + #[inline(always)] + pub fn crcpoly(&mut self) -> CRCPOLY_W { + CRCPOLY_W { w: self } + } + #[doc = "Bits 8:13 - CRC Input Source"] + #[inline(always)] + pub fn crcsrc(&mut self) -> CRCSRC_W { + CRCSRC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CRC Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [crcctrl](index.html) module"] +pub struct CRCCTRL_SPEC; +impl crate::RegisterSpec for CRCCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [crcctrl::R](R) reader structure"] +impl crate::Readable for CRCCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [crcctrl::W](W) writer structure"] +impl crate::Writable for CRCCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CRCCTRL to value 0"] +impl crate::Resettable for CRCCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/dmac/crcdatain.rs b/pac/atsamc21g/src/dmac/crcdatain.rs new file mode 100644 index 000000000000..ca0879a12136 --- /dev/null +++ b/pac/atsamc21g/src/dmac/crcdatain.rs @@ -0,0 +1,103 @@ +#[doc = "Register `CRCDATAIN` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CRCDATAIN` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CRCDATAIN` reader - CRC Data Input"] +pub struct CRCDATAIN_R(crate::FieldReader); +impl CRCDATAIN_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CRCDATAIN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CRCDATAIN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCDATAIN` writer - CRC Data Input"] +pub struct CRCDATAIN_W<'a> { + w: &'a mut W, +} +impl<'a> CRCDATAIN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - CRC Data Input"] + #[inline(always)] + pub fn crcdatain(&self) -> CRCDATAIN_R { + CRCDATAIN_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - CRC Data Input"] + #[inline(always)] + pub fn crcdatain(&mut self) -> CRCDATAIN_W { + CRCDATAIN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CRC Data Input\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [crcdatain](index.html) module"] +pub struct CRCDATAIN_SPEC; +impl crate::RegisterSpec for CRCDATAIN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [crcdatain::R](R) reader structure"] +impl crate::Readable for CRCDATAIN_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [crcdatain::W](W) writer structure"] +impl crate::Writable for CRCDATAIN_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CRCDATAIN to value 0"] +impl crate::Resettable for CRCDATAIN_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/dmac/crcstatus.rs b/pac/atsamc21g/src/dmac/crcstatus.rs new file mode 100644 index 000000000000..a132e9d5cd03 --- /dev/null +++ b/pac/atsamc21g/src/dmac/crcstatus.rs @@ -0,0 +1,160 @@ +#[doc = "Register `CRCSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CRCSTATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CRCBUSY` reader - CRC Module Busy"] +pub struct CRCBUSY_R(crate::FieldReader); +impl CRCBUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CRCBUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CRCBUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCBUSY` writer - CRC Module Busy"] +pub struct CRCBUSY_W<'a> { + w: &'a mut W, +} +impl<'a> CRCBUSY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `CRCZERO` reader - CRC Zero"] +pub struct CRCZERO_R(crate::FieldReader); +impl CRCZERO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CRCZERO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CRCZERO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCZERO` writer - CRC Zero"] +pub struct CRCZERO_W<'a> { + w: &'a mut W, +} +impl<'a> CRCZERO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - CRC Module Busy"] + #[inline(always)] + pub fn crcbusy(&self) -> CRCBUSY_R { + CRCBUSY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - CRC Zero"] + #[inline(always)] + pub fn crczero(&self) -> CRCZERO_R { + CRCZERO_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - CRC Module Busy"] + #[inline(always)] + pub fn crcbusy(&mut self) -> CRCBUSY_W { + CRCBUSY_W { w: self } + } + #[doc = "Bit 1 - CRC Zero"] + #[inline(always)] + pub fn crczero(&mut self) -> CRCZERO_W { + CRCZERO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CRC Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [crcstatus](index.html) module"] +pub struct CRCSTATUS_SPEC; +impl crate::RegisterSpec for CRCSTATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [crcstatus::R](R) reader structure"] +impl crate::Readable for CRCSTATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [crcstatus::W](W) writer structure"] +impl crate::Writable for CRCSTATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CRCSTATUS to value 0"] +impl crate::Resettable for CRCSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/dmac/ctrl.rs b/pac/atsamc21g/src/dmac/ctrl.rs new file mode 100644 index 000000000000..fabae9d82a6c --- /dev/null +++ b/pac/atsamc21g/src/dmac/ctrl.rs @@ -0,0 +1,395 @@ +#[doc = "Register `CTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `DMAENABLE` reader - DMA Enable"] +pub struct DMAENABLE_R(crate::FieldReader); +impl DMAENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DMAENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DMAENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DMAENABLE` writer - DMA Enable"] +pub struct DMAENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> DMAENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CRCENABLE` reader - CRC Enable"] +pub struct CRCENABLE_R(crate::FieldReader); +impl CRCENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CRCENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CRCENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCENABLE` writer - CRC Enable"] +pub struct CRCENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> CRCENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `LVLEN0` reader - Priority Level 0 Enable"] +pub struct LVLEN0_R(crate::FieldReader); +impl LVLEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LVLEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLEN0` writer - Priority Level 0 Enable"] +pub struct LVLEN0_W<'a> { + w: &'a mut W, +} +impl<'a> LVLEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `LVLEN1` reader - Priority Level 1 Enable"] +pub struct LVLEN1_R(crate::FieldReader); +impl LVLEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LVLEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLEN1` writer - Priority Level 1 Enable"] +pub struct LVLEN1_W<'a> { + w: &'a mut W, +} +impl<'a> LVLEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `LVLEN2` reader - Priority Level 2 Enable"] +pub struct LVLEN2_R(crate::FieldReader); +impl LVLEN2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LVLEN2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEN2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLEN2` writer - Priority Level 2 Enable"] +pub struct LVLEN2_W<'a> { + w: &'a mut W, +} +impl<'a> LVLEN2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u16 & 0x01) << 10); + self.w + } +} +#[doc = "Field `LVLEN3` reader - Priority Level 3 Enable"] +pub struct LVLEN3_R(crate::FieldReader); +impl LVLEN3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LVLEN3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEN3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLEN3` writer - Priority Level 3 Enable"] +pub struct LVLEN3_W<'a> { + w: &'a mut W, +} +impl<'a> LVLEN3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u16 & 0x01) << 11); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - DMA Enable"] + #[inline(always)] + pub fn dmaenable(&self) -> DMAENABLE_R { + DMAENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - CRC Enable"] + #[inline(always)] + pub fn crcenable(&self) -> CRCENABLE_R { + CRCENABLE_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 8 - Priority Level 0 Enable"] + #[inline(always)] + pub fn lvlen0(&self) -> LVLEN0_R { + LVLEN0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Priority Level 1 Enable"] + #[inline(always)] + pub fn lvlen1(&self) -> LVLEN1_R { + LVLEN1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Priority Level 2 Enable"] + #[inline(always)] + pub fn lvlen2(&self) -> LVLEN2_R { + LVLEN2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Priority Level 3 Enable"] + #[inline(always)] + pub fn lvlen3(&self) -> LVLEN3_R { + LVLEN3_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - DMA Enable"] + #[inline(always)] + pub fn dmaenable(&mut self) -> DMAENABLE_W { + DMAENABLE_W { w: self } + } + #[doc = "Bit 2 - CRC Enable"] + #[inline(always)] + pub fn crcenable(&mut self) -> CRCENABLE_W { + CRCENABLE_W { w: self } + } + #[doc = "Bit 8 - Priority Level 0 Enable"] + #[inline(always)] + pub fn lvlen0(&mut self) -> LVLEN0_W { + LVLEN0_W { w: self } + } + #[doc = "Bit 9 - Priority Level 1 Enable"] + #[inline(always)] + pub fn lvlen1(&mut self) -> LVLEN1_W { + LVLEN1_W { w: self } + } + #[doc = "Bit 10 - Priority Level 2 Enable"] + #[inline(always)] + pub fn lvlen2(&mut self) -> LVLEN2_W { + LVLEN2_W { w: self } + } + #[doc = "Bit 11 - Priority Level 3 Enable"] + #[inline(always)] + pub fn lvlen3(&mut self) -> LVLEN3_W { + LVLEN3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"] +pub struct CTRL_SPEC; +impl crate::RegisterSpec for CTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrl::R](R) reader structure"] +impl crate::Readable for CTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"] +impl crate::Writable for CTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/dmac/dbgctrl.rs b/pac/atsamc21g/src/dmac/dbgctrl.rs new file mode 100644 index 000000000000..53636eb2b339 --- /dev/null +++ b/pac/atsamc21g/src/dmac/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Debug Run"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Debug Run"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/dmac/intpend.rs b/pac/atsamc21g/src/dmac/intpend.rs new file mode 100644 index 000000000000..a107c4c32e66 --- /dev/null +++ b/pac/atsamc21g/src/dmac/intpend.rs @@ -0,0 +1,385 @@ +#[doc = "Register `INTPEND` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTPEND` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ID` reader - Channel ID"] +pub struct ID_R(crate::FieldReader); +impl ID_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ID_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ID_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ID` writer - Channel ID"] +pub struct ID_W<'a> { + w: &'a mut W, +} +impl<'a> ID_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u16 & 0x0f); + self.w + } +} +#[doc = "Field `TERR` reader - Transfer Error"] +pub struct TERR_R(crate::FieldReader); +impl TERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TERR` writer - Transfer Error"] +pub struct TERR_W<'a> { + w: &'a mut W, +} +impl<'a> TERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `TCMPL` reader - Transfer Complete"] +pub struct TCMPL_R(crate::FieldReader); +impl TCMPL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCMPL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCMPL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCMPL` writer - Transfer Complete"] +pub struct TCMPL_W<'a> { + w: &'a mut W, +} +impl<'a> TCMPL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `SUSP` reader - Channel Suspend"] +pub struct SUSP_R(crate::FieldReader); +impl SUSP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SUSP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SUSP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SUSP` writer - Channel Suspend"] +pub struct SUSP_W<'a> { + w: &'a mut W, +} +impl<'a> SUSP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u16 & 0x01) << 10); + self.w + } +} +#[doc = "Field `FERR` reader - Fetch Error"] +pub struct FERR_R(crate::FieldReader); +impl FERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FERR` writer - Fetch Error"] +pub struct FERR_W<'a> { + w: &'a mut W, +} +impl<'a> FERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u16 & 0x01) << 13); + self.w + } +} +#[doc = "Field `BUSY` reader - Busy"] +pub struct BUSY_R(crate::FieldReader); +impl BUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSY` writer - Busy"] +pub struct BUSY_W<'a> { + w: &'a mut W, +} +impl<'a> BUSY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u16 & 0x01) << 14); + self.w + } +} +#[doc = "Field `PEND` reader - Pending"] +pub struct PEND_R(crate::FieldReader); +impl PEND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEND` writer - Pending"] +pub struct PEND_W<'a> { + w: &'a mut W, +} +impl<'a> PEND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Channel ID"] + #[inline(always)] + pub fn id(&self) -> ID_R { + ID_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 8 - Transfer Error"] + #[inline(always)] + pub fn terr(&self) -> TERR_R { + TERR_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Transfer Complete"] + #[inline(always)] + pub fn tcmpl(&self) -> TCMPL_R { + TCMPL_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Channel Suspend"] + #[inline(always)] + pub fn susp(&self) -> SUSP_R { + SUSP_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 13 - Fetch Error"] + #[inline(always)] + pub fn ferr(&self) -> FERR_R { + FERR_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Busy"] + #[inline(always)] + pub fn busy(&self) -> BUSY_R { + BUSY_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Pending"] + #[inline(always)] + pub fn pend(&self) -> PEND_R { + PEND_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Channel ID"] + #[inline(always)] + pub fn id(&mut self) -> ID_W { + ID_W { w: self } + } + #[doc = "Bit 8 - Transfer Error"] + #[inline(always)] + pub fn terr(&mut self) -> TERR_W { + TERR_W { w: self } + } + #[doc = "Bit 9 - Transfer Complete"] + #[inline(always)] + pub fn tcmpl(&mut self) -> TCMPL_W { + TCMPL_W { w: self } + } + #[doc = "Bit 10 - Channel Suspend"] + #[inline(always)] + pub fn susp(&mut self) -> SUSP_W { + SUSP_W { w: self } + } + #[doc = "Bit 13 - Fetch Error"] + #[inline(always)] + pub fn ferr(&mut self) -> FERR_W { + FERR_W { w: self } + } + #[doc = "Bit 14 - Busy"] + #[inline(always)] + pub fn busy(&mut self) -> BUSY_W { + BUSY_W { w: self } + } + #[doc = "Bit 15 - Pending"] + #[inline(always)] + pub fn pend(&mut self) -> PEND_W { + PEND_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Pending\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intpend](index.html) module"] +pub struct INTPEND_SPEC; +impl crate::RegisterSpec for INTPEND_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intpend::R](R) reader structure"] +impl crate::Readable for INTPEND_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intpend::W](W) writer structure"] +impl crate::Writable for INTPEND_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTPEND to value 0"] +impl crate::Resettable for INTPEND_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/dmac/intstatus.rs b/pac/atsamc21g/src/dmac/intstatus.rs new file mode 100644 index 000000000000..74a836f4a2ff --- /dev/null +++ b/pac/atsamc21g/src/dmac/intstatus.rs @@ -0,0 +1,273 @@ +#[doc = "Register `INTSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `CHINT0` reader - Channel 0 Pending Interrupt"] +pub struct CHINT0_R(crate::FieldReader); +impl CHINT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT1` reader - Channel 1 Pending Interrupt"] +pub struct CHINT1_R(crate::FieldReader); +impl CHINT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT2` reader - Channel 2 Pending Interrupt"] +pub struct CHINT2_R(crate::FieldReader); +impl CHINT2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT3` reader - Channel 3 Pending Interrupt"] +pub struct CHINT3_R(crate::FieldReader); +impl CHINT3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT4` reader - Channel 4 Pending Interrupt"] +pub struct CHINT4_R(crate::FieldReader); +impl CHINT4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT5` reader - Channel 5 Pending Interrupt"] +pub struct CHINT5_R(crate::FieldReader); +impl CHINT5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT6` reader - Channel 6 Pending Interrupt"] +pub struct CHINT6_R(crate::FieldReader); +impl CHINT6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT7` reader - Channel 7 Pending Interrupt"] +pub struct CHINT7_R(crate::FieldReader); +impl CHINT7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT8` reader - Channel 8 Pending Interrupt"] +pub struct CHINT8_R(crate::FieldReader); +impl CHINT8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT9` reader - Channel 9 Pending Interrupt"] +pub struct CHINT9_R(crate::FieldReader); +impl CHINT9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT10` reader - Channel 10 Pending Interrupt"] +pub struct CHINT10_R(crate::FieldReader); +impl CHINT10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT11` reader - Channel 11 Pending Interrupt"] +pub struct CHINT11_R(crate::FieldReader); +impl CHINT11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Channel 0 Pending Interrupt"] + #[inline(always)] + pub fn chint0(&self) -> CHINT0_R { + CHINT0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel 1 Pending Interrupt"] + #[inline(always)] + pub fn chint1(&self) -> CHINT1_R { + CHINT1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel 2 Pending Interrupt"] + #[inline(always)] + pub fn chint2(&self) -> CHINT2_R { + CHINT2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Channel 3 Pending Interrupt"] + #[inline(always)] + pub fn chint3(&self) -> CHINT3_R { + CHINT3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Channel 4 Pending Interrupt"] + #[inline(always)] + pub fn chint4(&self) -> CHINT4_R { + CHINT4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Channel 5 Pending Interrupt"] + #[inline(always)] + pub fn chint5(&self) -> CHINT5_R { + CHINT5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Channel 6 Pending Interrupt"] + #[inline(always)] + pub fn chint6(&self) -> CHINT6_R { + CHINT6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Channel 7 Pending Interrupt"] + #[inline(always)] + pub fn chint7(&self) -> CHINT7_R { + CHINT7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Channel 8 Pending Interrupt"] + #[inline(always)] + pub fn chint8(&self) -> CHINT8_R { + CHINT8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Channel 9 Pending Interrupt"] + #[inline(always)] + pub fn chint9(&self) -> CHINT9_R { + CHINT9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Channel 10 Pending Interrupt"] + #[inline(always)] + pub fn chint10(&self) -> CHINT10_R { + CHINT10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Channel 11 Pending Interrupt"] + #[inline(always)] + pub fn chint11(&self) -> CHINT11_R { + CHINT11_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +#[doc = "Interrupt Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intstatus](index.html) module"] +pub struct INTSTATUS_SPEC; +impl crate::RegisterSpec for INTSTATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intstatus::R](R) reader structure"] +impl crate::Readable for INTSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets INTSTATUS to value 0"] +impl crate::Resettable for INTSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/dmac/pendch.rs b/pac/atsamc21g/src/dmac/pendch.rs new file mode 100644 index 000000000000..8bb68ff8fa5d --- /dev/null +++ b/pac/atsamc21g/src/dmac/pendch.rs @@ -0,0 +1,273 @@ +#[doc = "Register `PENDCH` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PENDCH0` reader - Pending Channel 0"] +pub struct PENDCH0_R(crate::FieldReader); +impl PENDCH0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH1` reader - Pending Channel 1"] +pub struct PENDCH1_R(crate::FieldReader); +impl PENDCH1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH2` reader - Pending Channel 2"] +pub struct PENDCH2_R(crate::FieldReader); +impl PENDCH2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH3` reader - Pending Channel 3"] +pub struct PENDCH3_R(crate::FieldReader); +impl PENDCH3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH4` reader - Pending Channel 4"] +pub struct PENDCH4_R(crate::FieldReader); +impl PENDCH4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH5` reader - Pending Channel 5"] +pub struct PENDCH5_R(crate::FieldReader); +impl PENDCH5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH6` reader - Pending Channel 6"] +pub struct PENDCH6_R(crate::FieldReader); +impl PENDCH6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH7` reader - Pending Channel 7"] +pub struct PENDCH7_R(crate::FieldReader); +impl PENDCH7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH8` reader - Pending Channel 8"] +pub struct PENDCH8_R(crate::FieldReader); +impl PENDCH8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH9` reader - Pending Channel 9"] +pub struct PENDCH9_R(crate::FieldReader); +impl PENDCH9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH10` reader - Pending Channel 10"] +pub struct PENDCH10_R(crate::FieldReader); +impl PENDCH10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH11` reader - Pending Channel 11"] +pub struct PENDCH11_R(crate::FieldReader); +impl PENDCH11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Pending Channel 0"] + #[inline(always)] + pub fn pendch0(&self) -> PENDCH0_R { + PENDCH0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Pending Channel 1"] + #[inline(always)] + pub fn pendch1(&self) -> PENDCH1_R { + PENDCH1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Pending Channel 2"] + #[inline(always)] + pub fn pendch2(&self) -> PENDCH2_R { + PENDCH2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Pending Channel 3"] + #[inline(always)] + pub fn pendch3(&self) -> PENDCH3_R { + PENDCH3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Pending Channel 4"] + #[inline(always)] + pub fn pendch4(&self) -> PENDCH4_R { + PENDCH4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Pending Channel 5"] + #[inline(always)] + pub fn pendch5(&self) -> PENDCH5_R { + PENDCH5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Pending Channel 6"] + #[inline(always)] + pub fn pendch6(&self) -> PENDCH6_R { + PENDCH6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Pending Channel 7"] + #[inline(always)] + pub fn pendch7(&self) -> PENDCH7_R { + PENDCH7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Pending Channel 8"] + #[inline(always)] + pub fn pendch8(&self) -> PENDCH8_R { + PENDCH8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Pending Channel 9"] + #[inline(always)] + pub fn pendch9(&self) -> PENDCH9_R { + PENDCH9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Pending Channel 10"] + #[inline(always)] + pub fn pendch10(&self) -> PENDCH10_R { + PENDCH10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Pending Channel 11"] + #[inline(always)] + pub fn pendch11(&self) -> PENDCH11_R { + PENDCH11_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +#[doc = "Pending Channels\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pendch](index.html) module"] +pub struct PENDCH_SPEC; +impl crate::RegisterSpec for PENDCH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pendch::R](R) reader structure"] +impl crate::Readable for PENDCH_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PENDCH to value 0"] +impl crate::Resettable for PENDCH_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/dmac/prictrl0.rs b/pac/atsamc21g/src/dmac/prictrl0.rs new file mode 100644 index 000000000000..618e54ad23f2 --- /dev/null +++ b/pac/atsamc21g/src/dmac/prictrl0.rs @@ -0,0 +1,449 @@ +#[doc = "Register `PRICTRL0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PRICTRL0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `LVLPRI0` reader - Level 0 Channel Priority Number"] +pub struct LVLPRI0_R(crate::FieldReader); +impl LVLPRI0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LVLPRI0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLPRI0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLPRI0` writer - Level 0 Channel Priority Number"] +pub struct LVLPRI0_W<'a> { + w: &'a mut W, +} +impl<'a> LVLPRI0_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Level 0 Round-Robin Scheduling Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RRLVLEN0_A { + #[doc = "0: Static arbitration scheme for channels with level 3 priority"] + STATIC_LVL = 0, + #[doc = "1: Round-robin arbitration scheme for channels with level 3 priority"] + ROUND_ROBIN_LVL = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RRLVLEN0_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RRLVLEN0` reader - Level 0 Round-Robin Scheduling Enable"] +pub struct RRLVLEN0_R(crate::FieldReader); +impl RRLVLEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RRLVLEN0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RRLVLEN0_A { + match self.bits { + false => RRLVLEN0_A::STATIC_LVL, + true => RRLVLEN0_A::ROUND_ROBIN_LVL, + } + } + #[doc = "Checks if the value of the field is `STATIC_LVL`"] + #[inline(always)] + pub fn is_static_lvl(&self) -> bool { + **self == RRLVLEN0_A::STATIC_LVL + } + #[doc = "Checks if the value of the field is `ROUND_ROBIN_LVL`"] + #[inline(always)] + pub fn is_round_robin_lvl(&self) -> bool { + **self == RRLVLEN0_A::ROUND_ROBIN_LVL + } +} +impl core::ops::Deref for RRLVLEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RRLVLEN0` writer - Level 0 Round-Robin Scheduling Enable"] +pub struct RRLVLEN0_W<'a> { + w: &'a mut W, +} +impl<'a> RRLVLEN0_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RRLVLEN0_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Static arbitration scheme for channels with level 3 priority"] + #[inline(always)] + pub fn static_lvl(self) -> &'a mut W { + self.variant(RRLVLEN0_A::STATIC_LVL) + } + #[doc = "Round-robin arbitration scheme for channels with level 3 priority"] + #[inline(always)] + pub fn round_robin_lvl(self) -> &'a mut W { + self.variant(RRLVLEN0_A::ROUND_ROBIN_LVL) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `LVLPRI1` reader - Level 1 Channel Priority Number"] +pub struct LVLPRI1_R(crate::FieldReader); +impl LVLPRI1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LVLPRI1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLPRI1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLPRI1` writer - Level 1 Channel Priority Number"] +pub struct LVLPRI1_W<'a> { + w: &'a mut W, +} +impl<'a> LVLPRI1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 8)) | ((value as u32 & 0x0f) << 8); + self.w + } +} +#[doc = "Field `RRLVLEN1` reader - Level 1 Round-Robin Scheduling Enable"] +pub struct RRLVLEN1_R(crate::FieldReader); +impl RRLVLEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RRLVLEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RRLVLEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RRLVLEN1` writer - Level 1 Round-Robin Scheduling Enable"] +pub struct RRLVLEN1_W<'a> { + w: &'a mut W, +} +impl<'a> RRLVLEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `LVLPRI2` reader - Level 2 Channel Priority Number"] +pub struct LVLPRI2_R(crate::FieldReader); +impl LVLPRI2_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LVLPRI2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLPRI2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLPRI2` writer - Level 2 Channel Priority Number"] +pub struct LVLPRI2_W<'a> { + w: &'a mut W, +} +impl<'a> LVLPRI2_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 16)) | ((value as u32 & 0x0f) << 16); + self.w + } +} +#[doc = "Field `RRLVLEN2` reader - Level 2 Round-Robin Scheduling Enable"] +pub struct RRLVLEN2_R(crate::FieldReader); +impl RRLVLEN2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RRLVLEN2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RRLVLEN2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RRLVLEN2` writer - Level 2 Round-Robin Scheduling Enable"] +pub struct RRLVLEN2_W<'a> { + w: &'a mut W, +} +impl<'a> RRLVLEN2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `LVLPRI3` reader - Level 3 Channel Priority Number"] +pub struct LVLPRI3_R(crate::FieldReader); +impl LVLPRI3_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LVLPRI3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLPRI3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLPRI3` writer - Level 3 Channel Priority Number"] +pub struct LVLPRI3_W<'a> { + w: &'a mut W, +} +impl<'a> LVLPRI3_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Field `RRLVLEN3` reader - Level 3 Round-Robin Scheduling Enable"] +pub struct RRLVLEN3_R(crate::FieldReader); +impl RRLVLEN3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RRLVLEN3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RRLVLEN3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RRLVLEN3` writer - Level 3 Round-Robin Scheduling Enable"] +pub struct RRLVLEN3_W<'a> { + w: &'a mut W, +} +impl<'a> RRLVLEN3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Level 0 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri0(&self) -> LVLPRI0_R { + LVLPRI0_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 7 - Level 0 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen0(&self) -> RRLVLEN0_R { + RRLVLEN0_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:11 - Level 1 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri1(&self) -> LVLPRI1_R { + LVLPRI1_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 15 - Level 1 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen1(&self) -> RRLVLEN1_R { + RRLVLEN1_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:19 - Level 2 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri2(&self) -> LVLPRI2_R { + LVLPRI2_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 23 - Level 2 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen2(&self) -> RRLVLEN2_R { + RRLVLEN2_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bits 24:27 - Level 3 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri3(&self) -> LVLPRI3_R { + LVLPRI3_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 31 - Level 3 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen3(&self) -> RRLVLEN3_R { + RRLVLEN3_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Level 0 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri0(&mut self) -> LVLPRI0_W { + LVLPRI0_W { w: self } + } + #[doc = "Bit 7 - Level 0 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen0(&mut self) -> RRLVLEN0_W { + RRLVLEN0_W { w: self } + } + #[doc = "Bits 8:11 - Level 1 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri1(&mut self) -> LVLPRI1_W { + LVLPRI1_W { w: self } + } + #[doc = "Bit 15 - Level 1 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen1(&mut self) -> RRLVLEN1_W { + RRLVLEN1_W { w: self } + } + #[doc = "Bits 16:19 - Level 2 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri2(&mut self) -> LVLPRI2_W { + LVLPRI2_W { w: self } + } + #[doc = "Bit 23 - Level 2 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen2(&mut self) -> RRLVLEN2_W { + RRLVLEN2_W { w: self } + } + #[doc = "Bits 24:27 - Level 3 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri3(&mut self) -> LVLPRI3_W { + LVLPRI3_W { w: self } + } + #[doc = "Bit 31 - Level 3 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen3(&mut self) -> RRLVLEN3_W { + RRLVLEN3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Priority Control 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [prictrl0](index.html) module"] +pub struct PRICTRL0_SPEC; +impl crate::RegisterSpec for PRICTRL0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [prictrl0::R](R) reader structure"] +impl crate::Readable for PRICTRL0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [prictrl0::W](W) writer structure"] +impl crate::Writable for PRICTRL0_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PRICTRL0 to value 0"] +impl crate::Resettable for PRICTRL0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/dmac/qosctrl.rs b/pac/atsamc21g/src/dmac/qosctrl.rs new file mode 100644 index 000000000000..016fcaa221ef --- /dev/null +++ b/pac/atsamc21g/src/dmac/qosctrl.rs @@ -0,0 +1,402 @@ +#[doc = "Register `QOSCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `QOSCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Write-Back Quality of Service\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WRBQOS_A { + #[doc = "0: Background (no sensitive operation)"] + DISABLE = 0, + #[doc = "1: Sensitive Bandwidth"] + LOW = 1, + #[doc = "2: Sensitive Latency"] + MEDIUM = 2, + #[doc = "3: Critical Latency"] + HIGH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WRBQOS_A) -> Self { + variant as _ + } +} +#[doc = "Field `WRBQOS` reader - Write-Back Quality of Service"] +pub struct WRBQOS_R(crate::FieldReader); +impl WRBQOS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WRBQOS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> WRBQOS_A { + match self.bits { + 0 => WRBQOS_A::DISABLE, + 1 => WRBQOS_A::LOW, + 2 => WRBQOS_A::MEDIUM, + 3 => WRBQOS_A::HIGH, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == WRBQOS_A::DISABLE + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == WRBQOS_A::LOW + } + #[doc = "Checks if the value of the field is `MEDIUM`"] + #[inline(always)] + pub fn is_medium(&self) -> bool { + **self == WRBQOS_A::MEDIUM + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == WRBQOS_A::HIGH + } +} +impl core::ops::Deref for WRBQOS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WRBQOS` writer - Write-Back Quality of Service"] +pub struct WRBQOS_W<'a> { + w: &'a mut W, +} +impl<'a> WRBQOS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WRBQOS_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Background (no sensitive operation)"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(WRBQOS_A::DISABLE) + } + #[doc = "Sensitive Bandwidth"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(WRBQOS_A::LOW) + } + #[doc = "Sensitive Latency"] + #[inline(always)] + pub fn medium(self) -> &'a mut W { + self.variant(WRBQOS_A::MEDIUM) + } + #[doc = "Critical Latency"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(WRBQOS_A::HIGH) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u8 & 0x03); + self.w + } +} +#[doc = "Fetch Quality of Service\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FQOS_A { + #[doc = "0: Background (no sensitive operation)"] + DISABLE = 0, + #[doc = "1: Sensitive Bandwidth"] + LOW = 1, + #[doc = "2: Sensitive Latency"] + MEDIUM = 2, + #[doc = "3: Critical Latency"] + HIGH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FQOS_A) -> Self { + variant as _ + } +} +#[doc = "Field `FQOS` reader - Fetch Quality of Service"] +pub struct FQOS_R(crate::FieldReader); +impl FQOS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FQOS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FQOS_A { + match self.bits { + 0 => FQOS_A::DISABLE, + 1 => FQOS_A::LOW, + 2 => FQOS_A::MEDIUM, + 3 => FQOS_A::HIGH, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == FQOS_A::DISABLE + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == FQOS_A::LOW + } + #[doc = "Checks if the value of the field is `MEDIUM`"] + #[inline(always)] + pub fn is_medium(&self) -> bool { + **self == FQOS_A::MEDIUM + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == FQOS_A::HIGH + } +} +impl core::ops::Deref for FQOS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FQOS` writer - Fetch Quality of Service"] +pub struct FQOS_W<'a> { + w: &'a mut W, +} +impl<'a> FQOS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FQOS_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Background (no sensitive operation)"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(FQOS_A::DISABLE) + } + #[doc = "Sensitive Bandwidth"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(FQOS_A::LOW) + } + #[doc = "Sensitive Latency"] + #[inline(always)] + pub fn medium(self) -> &'a mut W { + self.variant(FQOS_A::MEDIUM) + } + #[doc = "Critical Latency"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(FQOS_A::HIGH) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u8 & 0x03) << 2); + self.w + } +} +#[doc = "Data Transfer Quality of Service\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DQOS_A { + #[doc = "0: Background (no sensitive operation)"] + DISABLE = 0, + #[doc = "1: Sensitive Bandwidth"] + LOW = 1, + #[doc = "2: Sensitive Latency"] + MEDIUM = 2, + #[doc = "3: Critical Latency"] + HIGH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DQOS_A) -> Self { + variant as _ + } +} +#[doc = "Field `DQOS` reader - Data Transfer Quality of Service"] +pub struct DQOS_R(crate::FieldReader); +impl DQOS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DQOS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DQOS_A { + match self.bits { + 0 => DQOS_A::DISABLE, + 1 => DQOS_A::LOW, + 2 => DQOS_A::MEDIUM, + 3 => DQOS_A::HIGH, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == DQOS_A::DISABLE + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == DQOS_A::LOW + } + #[doc = "Checks if the value of the field is `MEDIUM`"] + #[inline(always)] + pub fn is_medium(&self) -> bool { + **self == DQOS_A::MEDIUM + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == DQOS_A::HIGH + } +} +impl core::ops::Deref for DQOS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DQOS` writer - Data Transfer Quality of Service"] +pub struct DQOS_W<'a> { + w: &'a mut W, +} +impl<'a> DQOS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DQOS_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Background (no sensitive operation)"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(DQOS_A::DISABLE) + } + #[doc = "Sensitive Bandwidth"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(DQOS_A::LOW) + } + #[doc = "Sensitive Latency"] + #[inline(always)] + pub fn medium(self) -> &'a mut W { + self.variant(DQOS_A::MEDIUM) + } + #[doc = "Critical Latency"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(DQOS_A::HIGH) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u8 & 0x03) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Write-Back Quality of Service"] + #[inline(always)] + pub fn wrbqos(&self) -> WRBQOS_R { + WRBQOS_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bits 2:3 - Fetch Quality of Service"] + #[inline(always)] + pub fn fqos(&self) -> FQOS_R { + FQOS_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bits 4:5 - Data Transfer Quality of Service"] + #[inline(always)] + pub fn dqos(&self) -> DQOS_R { + DQOS_R::new(((self.bits >> 4) & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Write-Back Quality of Service"] + #[inline(always)] + pub fn wrbqos(&mut self) -> WRBQOS_W { + WRBQOS_W { w: self } + } + #[doc = "Bits 2:3 - Fetch Quality of Service"] + #[inline(always)] + pub fn fqos(&mut self) -> FQOS_W { + FQOS_W { w: self } + } + #[doc = "Bits 4:5 - Data Transfer Quality of Service"] + #[inline(always)] + pub fn dqos(&mut self) -> DQOS_W { + DQOS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "QOS Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [qosctrl](index.html) module"] +pub struct QOSCTRL_SPEC; +impl crate::RegisterSpec for QOSCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [qosctrl::R](R) reader structure"] +impl crate::Readable for QOSCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [qosctrl::W](W) writer structure"] +impl crate::Writable for QOSCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets QOSCTRL to value 0x2a"] +impl crate::Resettable for QOSCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x2a + } +} diff --git a/pac/atsamc21g/src/dmac/swtrigctrl.rs b/pac/atsamc21g/src/dmac/swtrigctrl.rs new file mode 100644 index 000000000000..8590fef852dc --- /dev/null +++ b/pac/atsamc21g/src/dmac/swtrigctrl.rs @@ -0,0 +1,630 @@ +#[doc = "Register `SWTRIGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SWTRIGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWTRIG0` reader - Channel 0 Software Trigger"] +pub struct SWTRIG0_R(crate::FieldReader); +impl SWTRIG0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG0` writer - Channel 0 Software Trigger"] +pub struct SWTRIG0_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `SWTRIG1` reader - Channel 1 Software Trigger"] +pub struct SWTRIG1_R(crate::FieldReader); +impl SWTRIG1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG1` writer - Channel 1 Software Trigger"] +pub struct SWTRIG1_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SWTRIG2` reader - Channel 2 Software Trigger"] +pub struct SWTRIG2_R(crate::FieldReader); +impl SWTRIG2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG2` writer - Channel 2 Software Trigger"] +pub struct SWTRIG2_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SWTRIG3` reader - Channel 3 Software Trigger"] +pub struct SWTRIG3_R(crate::FieldReader); +impl SWTRIG3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG3` writer - Channel 3 Software Trigger"] +pub struct SWTRIG3_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `SWTRIG4` reader - Channel 4 Software Trigger"] +pub struct SWTRIG4_R(crate::FieldReader); +impl SWTRIG4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG4` writer - Channel 4 Software Trigger"] +pub struct SWTRIG4_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `SWTRIG5` reader - Channel 5 Software Trigger"] +pub struct SWTRIG5_R(crate::FieldReader); +impl SWTRIG5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG5` writer - Channel 5 Software Trigger"] +pub struct SWTRIG5_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `SWTRIG6` reader - Channel 6 Software Trigger"] +pub struct SWTRIG6_R(crate::FieldReader); +impl SWTRIG6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG6` writer - Channel 6 Software Trigger"] +pub struct SWTRIG6_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `SWTRIG7` reader - Channel 7 Software Trigger"] +pub struct SWTRIG7_R(crate::FieldReader); +impl SWTRIG7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG7` writer - Channel 7 Software Trigger"] +pub struct SWTRIG7_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `SWTRIG8` reader - Channel 8 Software Trigger"] +pub struct SWTRIG8_R(crate::FieldReader); +impl SWTRIG8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG8` writer - Channel 8 Software Trigger"] +pub struct SWTRIG8_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `SWTRIG9` reader - Channel 9 Software Trigger"] +pub struct SWTRIG9_R(crate::FieldReader); +impl SWTRIG9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG9` writer - Channel 9 Software Trigger"] +pub struct SWTRIG9_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `SWTRIG10` reader - Channel 10 Software Trigger"] +pub struct SWTRIG10_R(crate::FieldReader); +impl SWTRIG10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG10` writer - Channel 10 Software Trigger"] +pub struct SWTRIG10_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `SWTRIG11` reader - Channel 11 Software Trigger"] +pub struct SWTRIG11_R(crate::FieldReader); +impl SWTRIG11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG11` writer - Channel 11 Software Trigger"] +pub struct SWTRIG11_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +impl R { + #[doc = "Bit 0 - Channel 0 Software Trigger"] + #[inline(always)] + pub fn swtrig0(&self) -> SWTRIG0_R { + SWTRIG0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel 1 Software Trigger"] + #[inline(always)] + pub fn swtrig1(&self) -> SWTRIG1_R { + SWTRIG1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel 2 Software Trigger"] + #[inline(always)] + pub fn swtrig2(&self) -> SWTRIG2_R { + SWTRIG2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Channel 3 Software Trigger"] + #[inline(always)] + pub fn swtrig3(&self) -> SWTRIG3_R { + SWTRIG3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Channel 4 Software Trigger"] + #[inline(always)] + pub fn swtrig4(&self) -> SWTRIG4_R { + SWTRIG4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Channel 5 Software Trigger"] + #[inline(always)] + pub fn swtrig5(&self) -> SWTRIG5_R { + SWTRIG5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Channel 6 Software Trigger"] + #[inline(always)] + pub fn swtrig6(&self) -> SWTRIG6_R { + SWTRIG6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Channel 7 Software Trigger"] + #[inline(always)] + pub fn swtrig7(&self) -> SWTRIG7_R { + SWTRIG7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Channel 8 Software Trigger"] + #[inline(always)] + pub fn swtrig8(&self) -> SWTRIG8_R { + SWTRIG8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Channel 9 Software Trigger"] + #[inline(always)] + pub fn swtrig9(&self) -> SWTRIG9_R { + SWTRIG9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Channel 10 Software Trigger"] + #[inline(always)] + pub fn swtrig10(&self) -> SWTRIG10_R { + SWTRIG10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Channel 11 Software Trigger"] + #[inline(always)] + pub fn swtrig11(&self) -> SWTRIG11_R { + SWTRIG11_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel 0 Software Trigger"] + #[inline(always)] + pub fn swtrig0(&mut self) -> SWTRIG0_W { + SWTRIG0_W { w: self } + } + #[doc = "Bit 1 - Channel 1 Software Trigger"] + #[inline(always)] + pub fn swtrig1(&mut self) -> SWTRIG1_W { + SWTRIG1_W { w: self } + } + #[doc = "Bit 2 - Channel 2 Software Trigger"] + #[inline(always)] + pub fn swtrig2(&mut self) -> SWTRIG2_W { + SWTRIG2_W { w: self } + } + #[doc = "Bit 3 - Channel 3 Software Trigger"] + #[inline(always)] + pub fn swtrig3(&mut self) -> SWTRIG3_W { + SWTRIG3_W { w: self } + } + #[doc = "Bit 4 - Channel 4 Software Trigger"] + #[inline(always)] + pub fn swtrig4(&mut self) -> SWTRIG4_W { + SWTRIG4_W { w: self } + } + #[doc = "Bit 5 - Channel 5 Software Trigger"] + #[inline(always)] + pub fn swtrig5(&mut self) -> SWTRIG5_W { + SWTRIG5_W { w: self } + } + #[doc = "Bit 6 - Channel 6 Software Trigger"] + #[inline(always)] + pub fn swtrig6(&mut self) -> SWTRIG6_W { + SWTRIG6_W { w: self } + } + #[doc = "Bit 7 - Channel 7 Software Trigger"] + #[inline(always)] + pub fn swtrig7(&mut self) -> SWTRIG7_W { + SWTRIG7_W { w: self } + } + #[doc = "Bit 8 - Channel 8 Software Trigger"] + #[inline(always)] + pub fn swtrig8(&mut self) -> SWTRIG8_W { + SWTRIG8_W { w: self } + } + #[doc = "Bit 9 - Channel 9 Software Trigger"] + #[inline(always)] + pub fn swtrig9(&mut self) -> SWTRIG9_W { + SWTRIG9_W { w: self } + } + #[doc = "Bit 10 - Channel 10 Software Trigger"] + #[inline(always)] + pub fn swtrig10(&mut self) -> SWTRIG10_W { + SWTRIG10_W { w: self } + } + #[doc = "Bit 11 - Channel 11 Software Trigger"] + #[inline(always)] + pub fn swtrig11(&mut self) -> SWTRIG11_W { + SWTRIG11_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Software Trigger Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [swtrigctrl](index.html) module"] +pub struct SWTRIGCTRL_SPEC; +impl crate::RegisterSpec for SWTRIGCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [swtrigctrl::R](R) reader structure"] +impl crate::Readable for SWTRIGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [swtrigctrl::W](W) writer structure"] +impl crate::Writable for SWTRIGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SWTRIGCTRL to value 0"] +impl crate::Resettable for SWTRIGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/dmac/wrbaddr.rs b/pac/atsamc21g/src/dmac/wrbaddr.rs new file mode 100644 index 000000000000..ccf2a376b853 --- /dev/null +++ b/pac/atsamc21g/src/dmac/wrbaddr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `WRBADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WRBADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WRBADDR` reader - Write-Back Memory Base Address"] +pub struct WRBADDR_R(crate::FieldReader); +impl WRBADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + WRBADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WRBADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WRBADDR` writer - Write-Back Memory Base Address"] +pub struct WRBADDR_W<'a> { + w: &'a mut W, +} +impl<'a> WRBADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Write-Back Memory Base Address"] + #[inline(always)] + pub fn wrbaddr(&self) -> WRBADDR_R { + WRBADDR_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Write-Back Memory Base Address"] + #[inline(always)] + pub fn wrbaddr(&mut self) -> WRBADDR_W { + WRBADDR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Write-Back Memory Section Base Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wrbaddr](index.html) module"] +pub struct WRBADDR_SPEC; +impl crate::RegisterSpec for WRBADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [wrbaddr::R](R) reader structure"] +impl crate::Readable for WRBADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wrbaddr::W](W) writer structure"] +impl crate::Writable for WRBADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WRBADDR to value 0"] +impl crate::Resettable for WRBADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/dsu.rs b/pac/atsamc21g/src/dsu.rs new file mode 100644 index 000000000000..88324f764961 --- /dev/null +++ b/pac/atsamc21g/src/dsu.rs @@ -0,0 +1,163 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrl: crate::Reg, + #[doc = "0x01 - Status A"] + pub statusa: crate::Reg, + #[doc = "0x02 - Status B"] + pub statusb: crate::Reg, + #[doc = "0x03 - Status C"] + pub statusc: crate::Reg, + #[doc = "0x04 - Address"] + pub addr: crate::Reg, + #[doc = "0x08 - Length"] + pub length: crate::Reg, + #[doc = "0x0c - Data"] + pub data: crate::Reg, + #[doc = "0x10..0x18 - Debug Communication Channel n"] + pub dcc: [crate::Reg; 2], + #[doc = "0x18 - Device Identification"] + pub did: crate::Reg, + _reserved9: [u8; 0xd4], + #[doc = "0xf0..0xf8 - Device Configuration"] + pub dcfg: [crate::Reg; 2], + _reserved10: [u8; 0x0f08], + #[doc = "0x1000 - CoreSight ROM Table Entry 0"] + pub entry0: crate::Reg, + #[doc = "0x1004 - CoreSight ROM Table Entry 1"] + pub entry1: crate::Reg, + #[doc = "0x1008 - CoreSight ROM Table End"] + pub end: crate::Reg, + _reserved13: [u8; 0x0fc0], + #[doc = "0x1fcc - CoreSight ROM Table Memory Type"] + pub memtype: crate::Reg, + #[doc = "0x1fd0 - Peripheral Identification 4"] + pub pid4: crate::Reg, + #[doc = "0x1fd4 - Peripheral Identification 5"] + pub pid5: crate::Reg, + #[doc = "0x1fd8 - Peripheral Identification 6"] + pub pid6: crate::Reg, + #[doc = "0x1fdc - Peripheral Identification 7"] + pub pid7: crate::Reg, + #[doc = "0x1fe0 - Peripheral Identification 0"] + pub pid0: crate::Reg, + #[doc = "0x1fe4 - Peripheral Identification 1"] + pub pid1: crate::Reg, + #[doc = "0x1fe8 - Peripheral Identification 2"] + pub pid2: crate::Reg, + #[doc = "0x1fec - Peripheral Identification 3"] + pub pid3: crate::Reg, + #[doc = "0x1ff0 - Component Identification 0"] + pub cid0: crate::Reg, + #[doc = "0x1ff4 - Component Identification 1"] + pub cid1: crate::Reg, + #[doc = "0x1ff8 - Component Identification 2"] + pub cid2: crate::Reg, + #[doc = "0x1ffc - Component Identification 3"] + pub cid3: crate::Reg, +} +#[doc = "CTRL register accessor: an alias for `Reg`"] +pub type CTRL = crate::Reg; +#[doc = "Control"] +pub mod ctrl; +#[doc = "STATUSA register accessor: an alias for `Reg`"] +pub type STATUSA = crate::Reg; +#[doc = "Status A"] +pub mod statusa; +#[doc = "STATUSB register accessor: an alias for `Reg`"] +pub type STATUSB = crate::Reg; +#[doc = "Status B"] +pub mod statusb; +#[doc = "STATUSC register accessor: an alias for `Reg`"] +pub type STATUSC = crate::Reg; +#[doc = "Status C"] +pub mod statusc; +#[doc = "ADDR register accessor: an alias for `Reg`"] +pub type ADDR = crate::Reg; +#[doc = "Address"] +pub mod addr; +#[doc = "LENGTH register accessor: an alias for `Reg`"] +pub type LENGTH = crate::Reg; +#[doc = "Length"] +pub mod length; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "Data"] +pub mod data; +#[doc = "DCC register accessor: an alias for `Reg`"] +pub type DCC = crate::Reg; +#[doc = "Debug Communication Channel n"] +pub mod dcc; +#[doc = "DID register accessor: an alias for `Reg`"] +pub type DID = crate::Reg; +#[doc = "Device Identification"] +pub mod did; +#[doc = "DCFG register accessor: an alias for `Reg`"] +pub type DCFG = crate::Reg; +#[doc = "Device Configuration"] +pub mod dcfg; +#[doc = "ENTRY0 register accessor: an alias for `Reg`"] +pub type ENTRY0 = crate::Reg; +#[doc = "CoreSight ROM Table Entry 0"] +pub mod entry0; +#[doc = "ENTRY1 register accessor: an alias for `Reg`"] +pub type ENTRY1 = crate::Reg; +#[doc = "CoreSight ROM Table Entry 1"] +pub mod entry1; +#[doc = "END register accessor: an alias for `Reg`"] +pub type END = crate::Reg; +#[doc = "CoreSight ROM Table End"] +pub mod end; +#[doc = "MEMTYPE register accessor: an alias for `Reg`"] +pub type MEMTYPE = crate::Reg; +#[doc = "CoreSight ROM Table Memory Type"] +pub mod memtype; +#[doc = "PID4 register accessor: an alias for `Reg`"] +pub type PID4 = crate::Reg; +#[doc = "Peripheral Identification 4"] +pub mod pid4; +#[doc = "PID5 register accessor: an alias for `Reg`"] +pub type PID5 = crate::Reg; +#[doc = "Peripheral Identification 5"] +pub mod pid5; +#[doc = "PID6 register accessor: an alias for `Reg`"] +pub type PID6 = crate::Reg; +#[doc = "Peripheral Identification 6"] +pub mod pid6; +#[doc = "PID7 register accessor: an alias for `Reg`"] +pub type PID7 = crate::Reg; +#[doc = "Peripheral Identification 7"] +pub mod pid7; +#[doc = "PID0 register accessor: an alias for `Reg`"] +pub type PID0 = crate::Reg; +#[doc = "Peripheral Identification 0"] +pub mod pid0; +#[doc = "PID1 register accessor: an alias for `Reg`"] +pub type PID1 = crate::Reg; +#[doc = "Peripheral Identification 1"] +pub mod pid1; +#[doc = "PID2 register accessor: an alias for `Reg`"] +pub type PID2 = crate::Reg; +#[doc = "Peripheral Identification 2"] +pub mod pid2; +#[doc = "PID3 register accessor: an alias for `Reg`"] +pub type PID3 = crate::Reg; +#[doc = "Peripheral Identification 3"] +pub mod pid3; +#[doc = "CID0 register accessor: an alias for `Reg`"] +pub type CID0 = crate::Reg; +#[doc = "Component Identification 0"] +pub mod cid0; +#[doc = "CID1 register accessor: an alias for `Reg`"] +pub type CID1 = crate::Reg; +#[doc = "Component Identification 1"] +pub mod cid1; +#[doc = "CID2 register accessor: an alias for `Reg`"] +pub type CID2 = crate::Reg; +#[doc = "Component Identification 2"] +pub mod cid2; +#[doc = "CID3 register accessor: an alias for `Reg`"] +pub type CID3 = crate::Reg; +#[doc = "Component Identification 3"] +pub mod cid3; diff --git a/pac/atsamc21g/src/dsu/addr.rs b/pac/atsamc21g/src/dsu/addr.rs new file mode 100644 index 000000000000..412f874d6b15 --- /dev/null +++ b/pac/atsamc21g/src/dsu/addr.rs @@ -0,0 +1,140 @@ +#[doc = "Register `ADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `AMOD` reader - Access Mode"] +pub struct AMOD_R(crate::FieldReader); +impl AMOD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + AMOD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AMOD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AMOD` writer - Access Mode"] +pub struct AMOD_W<'a> { + w: &'a mut W, +} +impl<'a> AMOD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u32 & 0x03); + self.w + } +} +#[doc = "Field `ADDR` reader - Address"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - Address"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3fff_ffff << 2)) | ((value as u32 & 0x3fff_ffff) << 2); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Access Mode"] + #[inline(always)] + pub fn amod(&self) -> AMOD_R { + AMOD_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bits 2:31 - Address"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new(((self.bits >> 2) & 0x3fff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:1 - Access Mode"] + #[inline(always)] + pub fn amod(&mut self) -> AMOD_W { + AMOD_W { w: self } + } + #[doc = "Bits 2:31 - Address"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [addr](index.html) module"] +pub struct ADDR_SPEC; +impl crate::RegisterSpec for ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [addr::R](R) reader structure"] +impl crate::Readable for ADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [addr::W](W) writer structure"] +impl crate::Writable for ADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ADDR to value 0"] +impl crate::Resettable for ADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/dsu/cid0.rs b/pac/atsamc21g/src/dsu/cid0.rs new file mode 100644 index 000000000000..b3c2373dfc99 --- /dev/null +++ b/pac/atsamc21g/src/dsu/cid0.rs @@ -0,0 +1,53 @@ +#[doc = "Register `CID0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PREAMBLEB0` reader - Preamble Byte 0"] +pub struct PREAMBLEB0_R(crate::FieldReader); +impl PREAMBLEB0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PREAMBLEB0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PREAMBLEB0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:7 - Preamble Byte 0"] + #[inline(always)] + pub fn preambleb0(&self) -> PREAMBLEB0_R { + PREAMBLEB0_R::new((self.bits & 0xff) as u8) + } +} +#[doc = "Component Identification 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid0](index.html) module"] +pub struct CID0_SPEC; +impl crate::RegisterSpec for CID0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid0::R](R) reader structure"] +impl crate::Readable for CID0_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID0 to value 0x0d"] +impl crate::Resettable for CID0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0d + } +} diff --git a/pac/atsamc21g/src/dsu/cid1.rs b/pac/atsamc21g/src/dsu/cid1.rs new file mode 100644 index 000000000000..3628ceac64a7 --- /dev/null +++ b/pac/atsamc21g/src/dsu/cid1.rs @@ -0,0 +1,73 @@ +#[doc = "Register `CID1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PREAMBLE` reader - Preamble"] +pub struct PREAMBLE_R(crate::FieldReader); +impl PREAMBLE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PREAMBLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PREAMBLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCLASS` reader - Component Class"] +pub struct CCLASS_R(crate::FieldReader); +impl CCLASS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CCLASS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCLASS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:3 - Preamble"] + #[inline(always)] + pub fn preamble(&self) -> PREAMBLE_R { + PREAMBLE_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Component Class"] + #[inline(always)] + pub fn cclass(&self) -> CCLASS_R { + CCLASS_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +#[doc = "Component Identification 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid1](index.html) module"] +pub struct CID1_SPEC; +impl crate::RegisterSpec for CID1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid1::R](R) reader structure"] +impl crate::Readable for CID1_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID1 to value 0x10"] +impl crate::Resettable for CID1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x10 + } +} diff --git a/pac/atsamc21g/src/dsu/cid2.rs b/pac/atsamc21g/src/dsu/cid2.rs new file mode 100644 index 000000000000..714078d5c430 --- /dev/null +++ b/pac/atsamc21g/src/dsu/cid2.rs @@ -0,0 +1,53 @@ +#[doc = "Register `CID2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PREAMBLEB2` reader - Preamble Byte 2"] +pub struct PREAMBLEB2_R(crate::FieldReader); +impl PREAMBLEB2_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PREAMBLEB2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PREAMBLEB2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:7 - Preamble Byte 2"] + #[inline(always)] + pub fn preambleb2(&self) -> PREAMBLEB2_R { + PREAMBLEB2_R::new((self.bits & 0xff) as u8) + } +} +#[doc = "Component Identification 2\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid2](index.html) module"] +pub struct CID2_SPEC; +impl crate::RegisterSpec for CID2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid2::R](R) reader structure"] +impl crate::Readable for CID2_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID2 to value 0x05"] +impl crate::Resettable for CID2_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x05 + } +} diff --git a/pac/atsamc21g/src/dsu/cid3.rs b/pac/atsamc21g/src/dsu/cid3.rs new file mode 100644 index 000000000000..a345af7b5166 --- /dev/null +++ b/pac/atsamc21g/src/dsu/cid3.rs @@ -0,0 +1,53 @@ +#[doc = "Register `CID3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PREAMBLEB3` reader - Preamble Byte 3"] +pub struct PREAMBLEB3_R(crate::FieldReader); +impl PREAMBLEB3_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PREAMBLEB3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PREAMBLEB3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:7 - Preamble Byte 3"] + #[inline(always)] + pub fn preambleb3(&self) -> PREAMBLEB3_R { + PREAMBLEB3_R::new((self.bits & 0xff) as u8) + } +} +#[doc = "Component Identification 3\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid3](index.html) module"] +pub struct CID3_SPEC; +impl crate::RegisterSpec for CID3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid3::R](R) reader structure"] +impl crate::Readable for CID3_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID3 to value 0xb1"] +impl crate::Resettable for CID3_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xb1 + } +} diff --git a/pac/atsamc21g/src/dsu/ctrl.rs b/pac/atsamc21g/src/dsu/ctrl.rs new file mode 100644 index 000000000000..0a19db5a5239 --- /dev/null +++ b/pac/atsamc21g/src/dsu/ctrl.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `CRC` writer - 32-bit Cyclic Redundancy Code"] +pub struct CRC_W<'a> { + w: &'a mut W, +} +impl<'a> CRC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `MBIST` writer - Memory built-in self-test"] +pub struct MBIST_W<'a> { + w: &'a mut W, +} +impl<'a> MBIST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CE` writer - Chip-Erase"] +pub struct CE_W<'a> { + w: &'a mut W, +} +impl<'a> CE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `ARR` writer - Auxiliary Row Read"] +pub struct ARR_W<'a> { + w: &'a mut W, +} +impl<'a> ARR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +#[doc = "Field `SMSA` writer - Start Memory Stream Access"] +pub struct SMSA_W<'a> { + w: &'a mut W, +} +impl<'a> SMSA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 2 - 32-bit Cyclic Redundancy Code"] + #[inline(always)] + pub fn crc(&mut self) -> CRC_W { + CRC_W { w: self } + } + #[doc = "Bit 3 - Memory built-in self-test"] + #[inline(always)] + pub fn mbist(&mut self) -> MBIST_W { + MBIST_W { w: self } + } + #[doc = "Bit 4 - Chip-Erase"] + #[inline(always)] + pub fn ce(&mut self) -> CE_W { + CE_W { w: self } + } + #[doc = "Bit 6 - Auxiliary Row Read"] + #[inline(always)] + pub fn arr(&mut self) -> ARR_W { + ARR_W { w: self } + } + #[doc = "Bit 7 - Start Memory Stream Access"] + #[inline(always)] + pub fn smsa(&mut self) -> SMSA_W { + SMSA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"] +pub struct CTRL_SPEC; +impl crate::RegisterSpec for CTRL_SPEC { + type Ux = u8; +} +#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"] +impl crate::Writable for CTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/dsu/data.rs b/pac/atsamc21g/src/dsu/data.rs new file mode 100644 index 000000000000..193cc49a07fd --- /dev/null +++ b/pac/atsamc21g/src/dsu/data.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Data"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Data"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/dsu/dcc.rs b/pac/atsamc21g/src/dsu/dcc.rs new file mode 100644 index 000000000000..354323a499ef --- /dev/null +++ b/pac/atsamc21g/src/dsu/dcc.rs @@ -0,0 +1,104 @@ +#[doc = "Register `DCC[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DCC[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Data"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Data"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Communication Channel n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dcc](index.html) module"] +pub struct DCC_SPEC; +impl crate::RegisterSpec for DCC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dcc::R](R) reader structure"] +impl crate::Readable for DCC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dcc::W](W) writer structure"] +impl crate::Writable for DCC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DCC[%s] +to value 0"] +impl crate::Resettable for DCC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/dsu/dcfg.rs b/pac/atsamc21g/src/dsu/dcfg.rs new file mode 100644 index 000000000000..c6d61d0b496e --- /dev/null +++ b/pac/atsamc21g/src/dsu/dcfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `DCFG[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DCFG[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DCFG` reader - Device Configuration"] +pub struct DCFG_R(crate::FieldReader); +impl DCFG_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + DCFG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DCFG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DCFG` writer - Device Configuration"] +pub struct DCFG_W<'a> { + w: &'a mut W, +} +impl<'a> DCFG_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Device Configuration"] + #[inline(always)] + pub fn dcfg(&self) -> DCFG_R { + DCFG_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Device Configuration"] + #[inline(always)] + pub fn dcfg(&mut self) -> DCFG_W { + DCFG_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Device Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dcfg](index.html) module"] +pub struct DCFG_SPEC; +impl crate::RegisterSpec for DCFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dcfg::R](R) reader structure"] +impl crate::Readable for DCFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dcfg::W](W) writer structure"] +impl crate::Writable for DCFG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DCFG[%s] +to value 0"] +impl crate::Resettable for DCFG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/dsu/did.rs b/pac/atsamc21g/src/dsu/did.rs new file mode 100644 index 000000000000..6effc7b0f281 --- /dev/null +++ b/pac/atsamc21g/src/dsu/did.rs @@ -0,0 +1,279 @@ +#[doc = "Register `DID` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `DEVSEL` reader - Device Select"] +pub struct DEVSEL_R(crate::FieldReader); +impl DEVSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DEVSEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DEVSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REVISION` reader - Revision Number"] +pub struct REVISION_R(crate::FieldReader); +impl REVISION_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REVISION_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REVISION_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIE` reader - Die Number"] +pub struct DIE_R(crate::FieldReader); +impl DIE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DIE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Series\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SERIES_A { + #[doc = "0: Cortex-M0+ processor, basic feature set"] + _0 = 0, + #[doc = "1: Cortex-M0+ processor, CAN"] + _1 = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SERIES_A) -> Self { + variant as _ + } +} +#[doc = "Field `SERIES` reader - Series"] +pub struct SERIES_R(crate::FieldReader); +impl SERIES_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SERIES_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SERIES_A::_0), + 1 => Some(SERIES_A::_1), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_0`"] + #[inline(always)] + pub fn is_0(&self) -> bool { + **self == SERIES_A::_0 + } + #[doc = "Checks if the value of the field is `_1`"] + #[inline(always)] + pub fn is_1(&self) -> bool { + **self == SERIES_A::_1 + } +} +impl core::ops::Deref for SERIES_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Family\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FAMILY_A { + #[doc = "0: General purpose microcontroller"] + _0 = 0, + #[doc = "1: PicoPower"] + _1 = 1, + #[doc = "2: 5V Industrial"] + _2 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FAMILY_A) -> Self { + variant as _ + } +} +#[doc = "Field `FAMILY` reader - Family"] +pub struct FAMILY_R(crate::FieldReader); +impl FAMILY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FAMILY_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(FAMILY_A::_0), + 1 => Some(FAMILY_A::_1), + 2 => Some(FAMILY_A::_2), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_0`"] + #[inline(always)] + pub fn is_0(&self) -> bool { + **self == FAMILY_A::_0 + } + #[doc = "Checks if the value of the field is `_1`"] + #[inline(always)] + pub fn is_1(&self) -> bool { + **self == FAMILY_A::_1 + } + #[doc = "Checks if the value of the field is `_2`"] + #[inline(always)] + pub fn is_2(&self) -> bool { + **self == FAMILY_A::_2 + } +} +impl core::ops::Deref for FAMILY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Processor\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PROCESSOR_A { + #[doc = "0: Cortex-M0"] + _0 = 0, + #[doc = "1: Cortex-M0+"] + _1 = 1, + #[doc = "2: Cortex-M3"] + _2 = 2, + #[doc = "3: Cortex-M4"] + _3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PROCESSOR_A) -> Self { + variant as _ + } +} +#[doc = "Field `PROCESSOR` reader - Processor"] +pub struct PROCESSOR_R(crate::FieldReader); +impl PROCESSOR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PROCESSOR_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PROCESSOR_A::_0), + 1 => Some(PROCESSOR_A::_1), + 2 => Some(PROCESSOR_A::_2), + 3 => Some(PROCESSOR_A::_3), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_0`"] + #[inline(always)] + pub fn is_0(&self) -> bool { + **self == PROCESSOR_A::_0 + } + #[doc = "Checks if the value of the field is `_1`"] + #[inline(always)] + pub fn is_1(&self) -> bool { + **self == PROCESSOR_A::_1 + } + #[doc = "Checks if the value of the field is `_2`"] + #[inline(always)] + pub fn is_2(&self) -> bool { + **self == PROCESSOR_A::_2 + } + #[doc = "Checks if the value of the field is `_3`"] + #[inline(always)] + pub fn is_3(&self) -> bool { + **self == PROCESSOR_A::_3 + } +} +impl core::ops::Deref for PROCESSOR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:7 - Device Select"] + #[inline(always)] + pub fn devsel(&self) -> DEVSEL_R { + DEVSEL_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:11 - Revision Number"] + #[inline(always)] + pub fn revision(&self) -> REVISION_R { + REVISION_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - Die Number"] + #[inline(always)] + pub fn die(&self) -> DIE_R { + DIE_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:21 - Series"] + #[inline(always)] + pub fn series(&self) -> SERIES_R { + SERIES_R::new(((self.bits >> 16) & 0x3f) as u8) + } + #[doc = "Bits 23:27 - Family"] + #[inline(always)] + pub fn family(&self) -> FAMILY_R { + FAMILY_R::new(((self.bits >> 23) & 0x1f) as u8) + } + #[doc = "Bits 28:31 - Processor"] + #[inline(always)] + pub fn processor(&self) -> PROCESSOR_R { + PROCESSOR_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +#[doc = "Device Identification\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [did](index.html) module"] +pub struct DID_SPEC; +impl crate::RegisterSpec for DID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [did::R](R) reader structure"] +impl crate::Readable for DID_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DID to value 0x1101_0505"] +impl crate::Resettable for DID_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x1101_0505 + } +} diff --git a/pac/atsamc21g/src/dsu/end.rs b/pac/atsamc21g/src/dsu/end.rs new file mode 100644 index 000000000000..cce2edea2bce --- /dev/null +++ b/pac/atsamc21g/src/dsu/end.rs @@ -0,0 +1,53 @@ +#[doc = "Register `END` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `END` reader - End Marker"] +pub struct END_R(crate::FieldReader); +impl END_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + END_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for END_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - End Marker"] + #[inline(always)] + pub fn end(&self) -> END_R { + END_R::new(self.bits as u32) + } +} +#[doc = "CoreSight ROM Table End\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [end](index.html) module"] +pub struct END_SPEC; +impl crate::RegisterSpec for END_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [end::R](R) reader structure"] +impl crate::Readable for END_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets END to value 0"] +impl crate::Resettable for END_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/dsu/entry0.rs b/pac/atsamc21g/src/dsu/entry0.rs new file mode 100644 index 000000000000..d8563990e827 --- /dev/null +++ b/pac/atsamc21g/src/dsu/entry0.rs @@ -0,0 +1,93 @@ +#[doc = "Register `ENTRY0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `EPRES` reader - Entry Present"] +pub struct EPRES_R(crate::FieldReader); +impl EPRES_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EPRES_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EPRES_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FMT` reader - Format"] +pub struct FMT_R(crate::FieldReader); +impl FMT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FMT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FMT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDOFF` reader - Address Offset"] +pub struct ADDOFF_R(crate::FieldReader); +impl ADDOFF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + ADDOFF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDOFF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Entry Present"] + #[inline(always)] + pub fn epres(&self) -> EPRES_R { + EPRES_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Format"] + #[inline(always)] + pub fn fmt(&self) -> FMT_R { + FMT_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 12:31 - Address Offset"] + #[inline(always)] + pub fn addoff(&self) -> ADDOFF_R { + ADDOFF_R::new(((self.bits >> 12) & 0x000f_ffff) as u32) + } +} +#[doc = "CoreSight ROM Table Entry 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [entry0](index.html) module"] +pub struct ENTRY0_SPEC; +impl crate::RegisterSpec for ENTRY0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [entry0::R](R) reader structure"] +impl crate::Readable for ENTRY0_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets ENTRY0 to value 0x9f0f_c002"] +impl crate::Resettable for ENTRY0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x9f0f_c002 + } +} diff --git a/pac/atsamc21g/src/dsu/entry1.rs b/pac/atsamc21g/src/dsu/entry1.rs new file mode 100644 index 000000000000..cec8fa367705 --- /dev/null +++ b/pac/atsamc21g/src/dsu/entry1.rs @@ -0,0 +1,31 @@ +#[doc = "Register `ENTRY1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "CoreSight ROM Table Entry 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [entry1](index.html) module"] +pub struct ENTRY1_SPEC; +impl crate::RegisterSpec for ENTRY1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [entry1::R](R) reader structure"] +impl crate::Readable for ENTRY1_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets ENTRY1 to value 0x5002"] +impl crate::Resettable for ENTRY1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x5002 + } +} diff --git a/pac/atsamc21g/src/dsu/length.rs b/pac/atsamc21g/src/dsu/length.rs new file mode 100644 index 000000000000..2dc771f74dfd --- /dev/null +++ b/pac/atsamc21g/src/dsu/length.rs @@ -0,0 +1,103 @@ +#[doc = "Register `LENGTH` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `LENGTH` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `LENGTH` reader - Length"] +pub struct LENGTH_R(crate::FieldReader); +impl LENGTH_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + LENGTH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LENGTH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LENGTH` writer - Length"] +pub struct LENGTH_W<'a> { + w: &'a mut W, +} +impl<'a> LENGTH_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3fff_ffff << 2)) | ((value as u32 & 0x3fff_ffff) << 2); + self.w + } +} +impl R { + #[doc = "Bits 2:31 - Length"] + #[inline(always)] + pub fn length(&self) -> LENGTH_R { + LENGTH_R::new(((self.bits >> 2) & 0x3fff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 2:31 - Length"] + #[inline(always)] + pub fn length(&mut self) -> LENGTH_W { + LENGTH_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Length\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [length](index.html) module"] +pub struct LENGTH_SPEC; +impl crate::RegisterSpec for LENGTH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [length::R](R) reader structure"] +impl crate::Readable for LENGTH_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [length::W](W) writer structure"] +impl crate::Writable for LENGTH_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets LENGTH to value 0"] +impl crate::Resettable for LENGTH_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/dsu/memtype.rs b/pac/atsamc21g/src/dsu/memtype.rs new file mode 100644 index 000000000000..3cc841e2ba78 --- /dev/null +++ b/pac/atsamc21g/src/dsu/memtype.rs @@ -0,0 +1,53 @@ +#[doc = "Register `MEMTYPE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SMEMP` reader - System Memory Present"] +pub struct SMEMP_R(crate::FieldReader); +impl SMEMP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SMEMP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SMEMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - System Memory Present"] + #[inline(always)] + pub fn smemp(&self) -> SMEMP_R { + SMEMP_R::new((self.bits & 0x01) != 0) + } +} +#[doc = "CoreSight ROM Table Memory Type\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [memtype](index.html) module"] +pub struct MEMTYPE_SPEC; +impl crate::RegisterSpec for MEMTYPE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [memtype::R](R) reader structure"] +impl crate::Readable for MEMTYPE_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets MEMTYPE to value 0"] +impl crate::Resettable for MEMTYPE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/dsu/pid0.rs b/pac/atsamc21g/src/dsu/pid0.rs new file mode 100644 index 000000000000..98028ea62838 --- /dev/null +++ b/pac/atsamc21g/src/dsu/pid0.rs @@ -0,0 +1,53 @@ +#[doc = "Register `PID0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PARTNBL` reader - Part Number Low"] +pub struct PARTNBL_R(crate::FieldReader); +impl PARTNBL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PARTNBL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PARTNBL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:7 - Part Number Low"] + #[inline(always)] + pub fn partnbl(&self) -> PARTNBL_R { + PARTNBL_R::new((self.bits & 0xff) as u8) + } +} +#[doc = "Peripheral Identification 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid0](index.html) module"] +pub struct PID0_SPEC; +impl crate::RegisterSpec for PID0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid0::R](R) reader structure"] +impl crate::Readable for PID0_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID0 to value 0xd0"] +impl crate::Resettable for PID0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xd0 + } +} diff --git a/pac/atsamc21g/src/dsu/pid1.rs b/pac/atsamc21g/src/dsu/pid1.rs new file mode 100644 index 000000000000..4f94b853507c --- /dev/null +++ b/pac/atsamc21g/src/dsu/pid1.rs @@ -0,0 +1,73 @@ +#[doc = "Register `PID1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PARTNBH` reader - Part Number High"] +pub struct PARTNBH_R(crate::FieldReader); +impl PARTNBH_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PARTNBH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PARTNBH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `JEPIDCL` reader - Low part of the JEP-106 Identity Code"] +pub struct JEPIDCL_R(crate::FieldReader); +impl JEPIDCL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + JEPIDCL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for JEPIDCL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:3 - Part Number High"] + #[inline(always)] + pub fn partnbh(&self) -> PARTNBH_R { + PARTNBH_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Low part of the JEP-106 Identity Code"] + #[inline(always)] + pub fn jepidcl(&self) -> JEPIDCL_R { + JEPIDCL_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +#[doc = "Peripheral Identification 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid1](index.html) module"] +pub struct PID1_SPEC; +impl crate::RegisterSpec for PID1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid1::R](R) reader structure"] +impl crate::Readable for PID1_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID1 to value 0xfc"] +impl crate::Resettable for PID1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xfc + } +} diff --git a/pac/atsamc21g/src/dsu/pid2.rs b/pac/atsamc21g/src/dsu/pid2.rs new file mode 100644 index 000000000000..d8f8ed10192e --- /dev/null +++ b/pac/atsamc21g/src/dsu/pid2.rs @@ -0,0 +1,93 @@ +#[doc = "Register `PID2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `JEPIDCH` reader - JEP-106 Identity Code High"] +pub struct JEPIDCH_R(crate::FieldReader); +impl JEPIDCH_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + JEPIDCH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for JEPIDCH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `JEPU` reader - JEP-106 Identity Code is used"] +pub struct JEPU_R(crate::FieldReader); +impl JEPU_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + JEPU_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for JEPU_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REVISION` reader - Revision Number"] +pub struct REVISION_R(crate::FieldReader); +impl REVISION_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REVISION_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REVISION_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:2 - JEP-106 Identity Code High"] + #[inline(always)] + pub fn jepidch(&self) -> JEPIDCH_R { + JEPIDCH_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 3 - JEP-106 Identity Code is used"] + #[inline(always)] + pub fn jepu(&self) -> JEPU_R { + JEPU_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bits 4:7 - Revision Number"] + #[inline(always)] + pub fn revision(&self) -> REVISION_R { + REVISION_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +#[doc = "Peripheral Identification 2\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid2](index.html) module"] +pub struct PID2_SPEC; +impl crate::RegisterSpec for PID2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid2::R](R) reader structure"] +impl crate::Readable for PID2_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID2 to value 0x09"] +impl crate::Resettable for PID2_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x09 + } +} diff --git a/pac/atsamc21g/src/dsu/pid3.rs b/pac/atsamc21g/src/dsu/pid3.rs new file mode 100644 index 000000000000..c0a8fb2d7f92 --- /dev/null +++ b/pac/atsamc21g/src/dsu/pid3.rs @@ -0,0 +1,73 @@ +#[doc = "Register `PID3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `CUSMOD` reader - ARM CUSMOD"] +pub struct CUSMOD_R(crate::FieldReader); +impl CUSMOD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CUSMOD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CUSMOD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REVAND` reader - Revision Number"] +pub struct REVAND_R(crate::FieldReader); +impl REVAND_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REVAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REVAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:3 - ARM CUSMOD"] + #[inline(always)] + pub fn cusmod(&self) -> CUSMOD_R { + CUSMOD_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Revision Number"] + #[inline(always)] + pub fn revand(&self) -> REVAND_R { + REVAND_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +#[doc = "Peripheral Identification 3\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid3](index.html) module"] +pub struct PID3_SPEC; +impl crate::RegisterSpec for PID3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid3::R](R) reader structure"] +impl crate::Readable for PID3_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID3 to value 0"] +impl crate::Resettable for PID3_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/dsu/pid4.rs b/pac/atsamc21g/src/dsu/pid4.rs new file mode 100644 index 000000000000..d3a1bd120f0b --- /dev/null +++ b/pac/atsamc21g/src/dsu/pid4.rs @@ -0,0 +1,73 @@ +#[doc = "Register `PID4` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `JEPCC` reader - JEP-106 Continuation Code"] +pub struct JEPCC_R(crate::FieldReader); +impl JEPCC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + JEPCC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for JEPCC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FKBC` reader - 4KB count"] +pub struct FKBC_R(crate::FieldReader); +impl FKBC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FKBC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FKBC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:3 - JEP-106 Continuation Code"] + #[inline(always)] + pub fn jepcc(&self) -> JEPCC_R { + JEPCC_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - 4KB count"] + #[inline(always)] + pub fn fkbc(&self) -> FKBC_R { + FKBC_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +#[doc = "Peripheral Identification 4\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid4](index.html) module"] +pub struct PID4_SPEC; +impl crate::RegisterSpec for PID4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid4::R](R) reader structure"] +impl crate::Readable for PID4_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID4 to value 0"] +impl crate::Resettable for PID4_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/dsu/pid5.rs b/pac/atsamc21g/src/dsu/pid5.rs new file mode 100644 index 000000000000..d343d4800b95 --- /dev/null +++ b/pac/atsamc21g/src/dsu/pid5.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID5` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 5\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid5](index.html) module"] +pub struct PID5_SPEC; +impl crate::RegisterSpec for PID5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid5::R](R) reader structure"] +impl crate::Readable for PID5_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID5 to value 0"] +impl crate::Resettable for PID5_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/dsu/pid6.rs b/pac/atsamc21g/src/dsu/pid6.rs new file mode 100644 index 000000000000..55cc2b8b5861 --- /dev/null +++ b/pac/atsamc21g/src/dsu/pid6.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID6` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 6\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid6](index.html) module"] +pub struct PID6_SPEC; +impl crate::RegisterSpec for PID6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid6::R](R) reader structure"] +impl crate::Readable for PID6_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID6 to value 0"] +impl crate::Resettable for PID6_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/dsu/pid7.rs b/pac/atsamc21g/src/dsu/pid7.rs new file mode 100644 index 000000000000..77664d4f2f95 --- /dev/null +++ b/pac/atsamc21g/src/dsu/pid7.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID7` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 7\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid7](index.html) module"] +pub struct PID7_SPEC; +impl crate::RegisterSpec for PID7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid7::R](R) reader structure"] +impl crate::Readable for PID7_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID7 to value 0"] +impl crate::Resettable for PID7_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/dsu/statusa.rs b/pac/atsamc21g/src/dsu/statusa.rs new file mode 100644 index 000000000000..c7b90a13e491 --- /dev/null +++ b/pac/atsamc21g/src/dsu/statusa.rs @@ -0,0 +1,301 @@ +#[doc = "Register `STATUSA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUSA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DONE` reader - Done"] +pub struct DONE_R(crate::FieldReader); +impl DONE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DONE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DONE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DONE` writer - Done"] +pub struct DONE_W<'a> { + w: &'a mut W, +} +impl<'a> DONE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `CRSTEXT` reader - CPU Reset Phase Extension"] +pub struct CRSTEXT_R(crate::FieldReader); +impl CRSTEXT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CRSTEXT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CRSTEXT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRSTEXT` writer - CPU Reset Phase Extension"] +pub struct CRSTEXT_W<'a> { + w: &'a mut W, +} +impl<'a> CRSTEXT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `BERR` reader - Bus Error"] +pub struct BERR_R(crate::FieldReader); +impl BERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BERR` writer - Bus Error"] +pub struct BERR_W<'a> { + w: &'a mut W, +} +impl<'a> BERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `FAIL` reader - Failure"] +pub struct FAIL_R(crate::FieldReader); +impl FAIL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAIL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAIL` writer - Failure"] +pub struct FAIL_W<'a> { + w: &'a mut W, +} +impl<'a> FAIL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PERR` reader - Protection Error"] +pub struct PERR_R(crate::FieldReader); +impl PERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERR` writer - Protection Error"] +pub struct PERR_W<'a> { + w: &'a mut W, +} +impl<'a> PERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +impl R { + #[doc = "Bit 0 - Done"] + #[inline(always)] + pub fn done(&self) -> DONE_R { + DONE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - CPU Reset Phase Extension"] + #[inline(always)] + pub fn crstext(&self) -> CRSTEXT_R { + CRSTEXT_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Bus Error"] + #[inline(always)] + pub fn berr(&self) -> BERR_R { + BERR_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Failure"] + #[inline(always)] + pub fn fail(&self) -> FAIL_R { + FAIL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Protection Error"] + #[inline(always)] + pub fn perr(&self) -> PERR_R { + PERR_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Done"] + #[inline(always)] + pub fn done(&mut self) -> DONE_W { + DONE_W { w: self } + } + #[doc = "Bit 1 - CPU Reset Phase Extension"] + #[inline(always)] + pub fn crstext(&mut self) -> CRSTEXT_W { + CRSTEXT_W { w: self } + } + #[doc = "Bit 2 - Bus Error"] + #[inline(always)] + pub fn berr(&mut self) -> BERR_W { + BERR_W { w: self } + } + #[doc = "Bit 3 - Failure"] + #[inline(always)] + pub fn fail(&mut self) -> FAIL_W { + FAIL_W { w: self } + } + #[doc = "Bit 4 - Protection Error"] + #[inline(always)] + pub fn perr(&mut self) -> PERR_W { + PERR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [statusa](index.html) module"] +pub struct STATUSA_SPEC; +impl crate::RegisterSpec for STATUSA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [statusa::R](R) reader structure"] +impl crate::Readable for STATUSA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [statusa::W](W) writer structure"] +impl crate::Writable for STATUSA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUSA to value 0"] +impl crate::Resettable for STATUSA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/dsu/statusb.rs b/pac/atsamc21g/src/dsu/statusb.rs new file mode 100644 index 000000000000..1e9374f8deae --- /dev/null +++ b/pac/atsamc21g/src/dsu/statusb.rs @@ -0,0 +1,133 @@ +#[doc = "Register `STATUSB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PROT` reader - Protected"] +pub struct PROT_R(crate::FieldReader); +impl PROT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PROT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PROT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGPRES` reader - Debugger Present"] +pub struct DBGPRES_R(crate::FieldReader); +impl DBGPRES_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGPRES_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGPRES_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DCCD0` reader - Debug Communication Channel 0 Dirty"] +pub struct DCCD0_R(crate::FieldReader); +impl DCCD0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DCCD0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DCCD0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DCCD1` reader - Debug Communication Channel 1 Dirty"] +pub struct DCCD1_R(crate::FieldReader); +impl DCCD1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DCCD1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DCCD1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HPE` reader - Hot-Plugging Enable"] +pub struct HPE_R(crate::FieldReader); +impl HPE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HPE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HPE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Protected"] + #[inline(always)] + pub fn prot(&self) -> PROT_R { + PROT_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Debugger Present"] + #[inline(always)] + pub fn dbgpres(&self) -> DBGPRES_R { + DBGPRES_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Debug Communication Channel 0 Dirty"] + #[inline(always)] + pub fn dccd0(&self) -> DCCD0_R { + DCCD0_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Debug Communication Channel 1 Dirty"] + #[inline(always)] + pub fn dccd1(&self) -> DCCD1_R { + DCCD1_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Hot-Plugging Enable"] + #[inline(always)] + pub fn hpe(&self) -> HPE_R { + HPE_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +#[doc = "Status B\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [statusb](index.html) module"] +pub struct STATUSB_SPEC; +impl crate::RegisterSpec for STATUSB_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [statusb::R](R) reader structure"] +impl crate::Readable for STATUSB_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUSB to value 0"] +impl crate::Resettable for STATUSB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/dsu/statusc.rs b/pac/atsamc21g/src/dsu/statusc.rs new file mode 100644 index 000000000000..14b3f7b1c7e3 --- /dev/null +++ b/pac/atsamc21g/src/dsu/statusc.rs @@ -0,0 +1,53 @@ +#[doc = "Register `STATUSC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `STATE` reader - State"] +pub struct STATE_R(crate::FieldReader); +impl STATE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + STATE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STATE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:2 - State"] + #[inline(always)] + pub fn state(&self) -> STATE_R { + STATE_R::new((self.bits & 0x07) as u8) + } +} +#[doc = "Status C\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [statusc](index.html) module"] +pub struct STATUSC_SPEC; +impl crate::RegisterSpec for STATUSC_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [statusc::R](R) reader structure"] +impl crate::Readable for STATUSC_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUSC to value 0"] +impl crate::Resettable for STATUSC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/eic.rs b/pac/atsamc21g/src/eic.rs new file mode 100644 index 000000000000..606231233f4b --- /dev/null +++ b/pac/atsamc21g/src/eic.rs @@ -0,0 +1,64 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrla: crate::Reg, + #[doc = "0x01 - NMI Control"] + pub nmictrl: crate::Reg, + #[doc = "0x02 - NMI Interrupt Flag"] + pub nmiflag: crate::Reg, + #[doc = "0x04 - Syncbusy register"] + pub syncbusy: crate::Reg, + #[doc = "0x08 - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x0c - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x10 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x14 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x18 - EIC Asynchronous edge Detection Enable"] + pub asynch: crate::Reg, + #[doc = "0x1c..0x24 - Configuration n"] + pub config: [crate::Reg; 2], +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control"] +pub mod ctrla; +#[doc = "NMICTRL register accessor: an alias for `Reg`"] +pub type NMICTRL = crate::Reg; +#[doc = "NMI Control"] +pub mod nmictrl; +#[doc = "NMIFLAG register accessor: an alias for `Reg`"] +pub type NMIFLAG = crate::Reg; +#[doc = "NMI Interrupt Flag"] +pub mod nmiflag; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Syncbusy register"] +pub mod syncbusy; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "ASYNCH register accessor: an alias for `Reg`"] +pub type ASYNCH = crate::Reg; +#[doc = "EIC Asynchronous edge Detection Enable"] +pub mod asynch; +#[doc = "CONFIG register accessor: an alias for `Reg`"] +pub type CONFIG = crate::Reg; +#[doc = "Configuration n"] +pub mod config; diff --git a/pac/atsamc21g/src/eic/asynch.rs b/pac/atsamc21g/src/eic/asynch.rs new file mode 100644 index 000000000000..78a9b5c5f054 --- /dev/null +++ b/pac/atsamc21g/src/eic/asynch.rs @@ -0,0 +1,152 @@ +#[doc = "Register `ASYNCH` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ASYNCH` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "EIC Asynchronous edge Detection Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u16)] +pub enum ASYNCH_A { + #[doc = "0: Edge detection is clock synchronously operated"] + SYNC = 0, + #[doc = "1: Edge detection is clock asynchronously operated"] + ASYNC = 1, +} +impl From for u16 { + #[inline(always)] + fn from(variant: ASYNCH_A) -> Self { + variant as _ + } +} +#[doc = "Field `ASYNCH` reader - EIC Asynchronous edge Detection Enable"] +pub struct ASYNCH_R(crate::FieldReader); +impl ASYNCH_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + ASYNCH_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(ASYNCH_A::SYNC), + 1 => Some(ASYNCH_A::ASYNC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `SYNC`"] + #[inline(always)] + pub fn is_sync(&self) -> bool { + **self == ASYNCH_A::SYNC + } + #[doc = "Checks if the value of the field is `ASYNC`"] + #[inline(always)] + pub fn is_async(&self) -> bool { + **self == ASYNCH_A::ASYNC + } +} +impl core::ops::Deref for ASYNCH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ASYNCH` writer - EIC Asynchronous edge Detection Enable"] +pub struct ASYNCH_W<'a> { + w: &'a mut W, +} +impl<'a> ASYNCH_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: ASYNCH_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Edge detection is clock synchronously operated"] + #[inline(always)] + pub fn sync(self) -> &'a mut W { + self.variant(ASYNCH_A::SYNC) + } + #[doc = "Edge detection is clock asynchronously operated"] + #[inline(always)] + pub fn async_(self) -> &'a mut W { + self.variant(ASYNCH_A::ASYNC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - EIC Asynchronous edge Detection Enable"] + #[inline(always)] + pub fn asynch(&self) -> ASYNCH_R { + ASYNCH_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - EIC Asynchronous edge Detection Enable"] + #[inline(always)] + pub fn asynch(&mut self) -> ASYNCH_W { + ASYNCH_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "EIC Asynchronous edge Detection Enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [asynch](index.html) module"] +pub struct ASYNCH_SPEC; +impl crate::RegisterSpec for ASYNCH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [asynch::R](R) reader structure"] +impl crate::Readable for ASYNCH_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [asynch::W](W) writer structure"] +impl crate::Writable for ASYNCH_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ASYNCH to value 0"] +impl crate::Resettable for ASYNCH_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/eic/config.rs b/pac/atsamc21g/src/eic/config.rs new file mode 100644 index 000000000000..ab2c30950417 --- /dev/null +++ b/pac/atsamc21g/src/eic/config.rs @@ -0,0 +1,1547 @@ +#[doc = "Register `CONFIG[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CONFIG[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Input Sense Configuration 0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE0_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE0_A) -> Self { + variant as _ + } +} +#[doc = "Field `SENSE0` reader - Input Sense Configuration 0"] +pub struct SENSE0_R(crate::FieldReader); +impl SENSE0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SENSE0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE0_A::NONE), + 1 => Some(SENSE0_A::RISE), + 2 => Some(SENSE0_A::FALL), + 3 => Some(SENSE0_A::BOTH), + 4 => Some(SENSE0_A::HIGH), + 5 => Some(SENSE0_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == SENSE0_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == SENSE0_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == SENSE0_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == SENSE0_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SENSE0_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SENSE0_A::LOW + } +} +impl core::ops::Deref for SENSE0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SENSE0` writer - Input Sense Configuration 0"] +pub struct SENSE0_W<'a> { + w: &'a mut W, +} +impl<'a> SENSE0_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SENSE0_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE0_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE0_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE0_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE0_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE0_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE0_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Field `FILTEN0` reader - Filter Enable 0"] +pub struct FILTEN0_R(crate::FieldReader); +impl FILTEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FILTEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTEN0` writer - Filter Enable 0"] +pub struct FILTEN0_W<'a> { + w: &'a mut W, +} +impl<'a> FILTEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Input Sense Configuration 1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE1_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE1_A) -> Self { + variant as _ + } +} +#[doc = "Field `SENSE1` reader - Input Sense Configuration 1"] +pub struct SENSE1_R(crate::FieldReader); +impl SENSE1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SENSE1_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE1_A::NONE), + 1 => Some(SENSE1_A::RISE), + 2 => Some(SENSE1_A::FALL), + 3 => Some(SENSE1_A::BOTH), + 4 => Some(SENSE1_A::HIGH), + 5 => Some(SENSE1_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == SENSE1_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == SENSE1_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == SENSE1_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == SENSE1_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SENSE1_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SENSE1_A::LOW + } +} +impl core::ops::Deref for SENSE1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SENSE1` writer - Input Sense Configuration 1"] +pub struct SENSE1_W<'a> { + w: &'a mut W, +} +impl<'a> SENSE1_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SENSE1_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE1_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE1_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE1_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE1_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE1_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE1_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 4)) | ((value as u32 & 0x07) << 4); + self.w + } +} +#[doc = "Field `FILTEN1` reader - Filter Enable 1"] +pub struct FILTEN1_R(crate::FieldReader); +impl FILTEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FILTEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTEN1` writer - Filter Enable 1"] +pub struct FILTEN1_W<'a> { + w: &'a mut W, +} +impl<'a> FILTEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Input Sense Configuration 2\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE2_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE2_A) -> Self { + variant as _ + } +} +#[doc = "Field `SENSE2` reader - Input Sense Configuration 2"] +pub struct SENSE2_R(crate::FieldReader); +impl SENSE2_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SENSE2_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE2_A::NONE), + 1 => Some(SENSE2_A::RISE), + 2 => Some(SENSE2_A::FALL), + 3 => Some(SENSE2_A::BOTH), + 4 => Some(SENSE2_A::HIGH), + 5 => Some(SENSE2_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == SENSE2_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == SENSE2_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == SENSE2_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == SENSE2_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SENSE2_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SENSE2_A::LOW + } +} +impl core::ops::Deref for SENSE2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SENSE2` writer - Input Sense Configuration 2"] +pub struct SENSE2_W<'a> { + w: &'a mut W, +} +impl<'a> SENSE2_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SENSE2_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE2_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE2_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE2_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE2_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE2_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE2_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +#[doc = "Field `FILTEN2` reader - Filter Enable 2"] +pub struct FILTEN2_R(crate::FieldReader); +impl FILTEN2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FILTEN2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTEN2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTEN2` writer - Filter Enable 2"] +pub struct FILTEN2_W<'a> { + w: &'a mut W, +} +impl<'a> FILTEN2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Input Sense Configuration 3\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE3_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE3_A) -> Self { + variant as _ + } +} +#[doc = "Field `SENSE3` reader - Input Sense Configuration 3"] +pub struct SENSE3_R(crate::FieldReader); +impl SENSE3_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SENSE3_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE3_A::NONE), + 1 => Some(SENSE3_A::RISE), + 2 => Some(SENSE3_A::FALL), + 3 => Some(SENSE3_A::BOTH), + 4 => Some(SENSE3_A::HIGH), + 5 => Some(SENSE3_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == SENSE3_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == SENSE3_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == SENSE3_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == SENSE3_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SENSE3_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SENSE3_A::LOW + } +} +impl core::ops::Deref for SENSE3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SENSE3` writer - Input Sense Configuration 3"] +pub struct SENSE3_W<'a> { + w: &'a mut W, +} +impl<'a> SENSE3_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SENSE3_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE3_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE3_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE3_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE3_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE3_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE3_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 12)) | ((value as u32 & 0x07) << 12); + self.w + } +} +#[doc = "Field `FILTEN3` reader - Filter Enable 3"] +pub struct FILTEN3_R(crate::FieldReader); +impl FILTEN3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FILTEN3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTEN3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTEN3` writer - Filter Enable 3"] +pub struct FILTEN3_W<'a> { + w: &'a mut W, +} +impl<'a> FILTEN3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Input Sense Configuration 4\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE4_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE4_A) -> Self { + variant as _ + } +} +#[doc = "Field `SENSE4` reader - Input Sense Configuration 4"] +pub struct SENSE4_R(crate::FieldReader); +impl SENSE4_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SENSE4_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE4_A::NONE), + 1 => Some(SENSE4_A::RISE), + 2 => Some(SENSE4_A::FALL), + 3 => Some(SENSE4_A::BOTH), + 4 => Some(SENSE4_A::HIGH), + 5 => Some(SENSE4_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == SENSE4_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == SENSE4_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == SENSE4_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == SENSE4_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SENSE4_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SENSE4_A::LOW + } +} +impl core::ops::Deref for SENSE4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SENSE4` writer - Input Sense Configuration 4"] +pub struct SENSE4_W<'a> { + w: &'a mut W, +} +impl<'a> SENSE4_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SENSE4_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE4_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE4_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE4_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE4_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE4_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE4_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 16)) | ((value as u32 & 0x07) << 16); + self.w + } +} +#[doc = "Field `FILTEN4` reader - Filter Enable 4"] +pub struct FILTEN4_R(crate::FieldReader); +impl FILTEN4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FILTEN4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTEN4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTEN4` writer - Filter Enable 4"] +pub struct FILTEN4_W<'a> { + w: &'a mut W, +} +impl<'a> FILTEN4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Input Sense Configuration 5\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE5_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE5_A) -> Self { + variant as _ + } +} +#[doc = "Field `SENSE5` reader - Input Sense Configuration 5"] +pub struct SENSE5_R(crate::FieldReader); +impl SENSE5_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SENSE5_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE5_A::NONE), + 1 => Some(SENSE5_A::RISE), + 2 => Some(SENSE5_A::FALL), + 3 => Some(SENSE5_A::BOTH), + 4 => Some(SENSE5_A::HIGH), + 5 => Some(SENSE5_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == SENSE5_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == SENSE5_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == SENSE5_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == SENSE5_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SENSE5_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SENSE5_A::LOW + } +} +impl core::ops::Deref for SENSE5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SENSE5` writer - Input Sense Configuration 5"] +pub struct SENSE5_W<'a> { + w: &'a mut W, +} +impl<'a> SENSE5_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SENSE5_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE5_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE5_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE5_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE5_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE5_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE5_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 20)) | ((value as u32 & 0x07) << 20); + self.w + } +} +#[doc = "Field `FILTEN5` reader - Filter Enable 5"] +pub struct FILTEN5_R(crate::FieldReader); +impl FILTEN5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FILTEN5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTEN5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTEN5` writer - Filter Enable 5"] +pub struct FILTEN5_W<'a> { + w: &'a mut W, +} +impl<'a> FILTEN5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Input Sense Configuration 6\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE6_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE6_A) -> Self { + variant as _ + } +} +#[doc = "Field `SENSE6` reader - Input Sense Configuration 6"] +pub struct SENSE6_R(crate::FieldReader); +impl SENSE6_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SENSE6_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE6_A::NONE), + 1 => Some(SENSE6_A::RISE), + 2 => Some(SENSE6_A::FALL), + 3 => Some(SENSE6_A::BOTH), + 4 => Some(SENSE6_A::HIGH), + 5 => Some(SENSE6_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == SENSE6_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == SENSE6_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == SENSE6_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == SENSE6_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SENSE6_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SENSE6_A::LOW + } +} +impl core::ops::Deref for SENSE6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SENSE6` writer - Input Sense Configuration 6"] +pub struct SENSE6_W<'a> { + w: &'a mut W, +} +impl<'a> SENSE6_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SENSE6_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE6_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE6_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE6_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE6_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE6_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE6_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 24)) | ((value as u32 & 0x07) << 24); + self.w + } +} +#[doc = "Field `FILTEN6` reader - Filter Enable 6"] +pub struct FILTEN6_R(crate::FieldReader); +impl FILTEN6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FILTEN6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTEN6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTEN6` writer - Filter Enable 6"] +pub struct FILTEN6_W<'a> { + w: &'a mut W, +} +impl<'a> FILTEN6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +#[doc = "Input Sense Configuration 7\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE7_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE7_A) -> Self { + variant as _ + } +} +#[doc = "Field `SENSE7` reader - Input Sense Configuration 7"] +pub struct SENSE7_R(crate::FieldReader); +impl SENSE7_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SENSE7_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE7_A::NONE), + 1 => Some(SENSE7_A::RISE), + 2 => Some(SENSE7_A::FALL), + 3 => Some(SENSE7_A::BOTH), + 4 => Some(SENSE7_A::HIGH), + 5 => Some(SENSE7_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == SENSE7_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == SENSE7_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == SENSE7_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == SENSE7_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SENSE7_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SENSE7_A::LOW + } +} +impl core::ops::Deref for SENSE7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SENSE7` writer - Input Sense Configuration 7"] +pub struct SENSE7_W<'a> { + w: &'a mut W, +} +impl<'a> SENSE7_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SENSE7_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE7_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE7_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE7_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE7_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE7_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE7_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 28)) | ((value as u32 & 0x07) << 28); + self.w + } +} +#[doc = "Field `FILTEN7` reader - Filter Enable 7"] +pub struct FILTEN7_R(crate::FieldReader); +impl FILTEN7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FILTEN7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTEN7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTEN7` writer - Filter Enable 7"] +pub struct FILTEN7_W<'a> { + w: &'a mut W, +} +impl<'a> FILTEN7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Input Sense Configuration 0"] + #[inline(always)] + pub fn sense0(&self) -> SENSE0_R { + SENSE0_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 3 - Filter Enable 0"] + #[inline(always)] + pub fn filten0(&self) -> FILTEN0_R { + FILTEN0_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bits 4:6 - Input Sense Configuration 1"] + #[inline(always)] + pub fn sense1(&self) -> SENSE1_R { + SENSE1_R::new(((self.bits >> 4) & 0x07) as u8) + } + #[doc = "Bit 7 - Filter Enable 1"] + #[inline(always)] + pub fn filten1(&self) -> FILTEN1_R { + FILTEN1_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Input Sense Configuration 2"] + #[inline(always)] + pub fn sense2(&self) -> SENSE2_R { + SENSE2_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 11 - Filter Enable 2"] + #[inline(always)] + pub fn filten2(&self) -> FILTEN2_R { + FILTEN2_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bits 12:14 - Input Sense Configuration 3"] + #[inline(always)] + pub fn sense3(&self) -> SENSE3_R { + SENSE3_R::new(((self.bits >> 12) & 0x07) as u8) + } + #[doc = "Bit 15 - Filter Enable 3"] + #[inline(always)] + pub fn filten3(&self) -> FILTEN3_R { + FILTEN3_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:18 - Input Sense Configuration 4"] + #[inline(always)] + pub fn sense4(&self) -> SENSE4_R { + SENSE4_R::new(((self.bits >> 16) & 0x07) as u8) + } + #[doc = "Bit 19 - Filter Enable 4"] + #[inline(always)] + pub fn filten4(&self) -> FILTEN4_R { + FILTEN4_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bits 20:22 - Input Sense Configuration 5"] + #[inline(always)] + pub fn sense5(&self) -> SENSE5_R { + SENSE5_R::new(((self.bits >> 20) & 0x07) as u8) + } + #[doc = "Bit 23 - Filter Enable 5"] + #[inline(always)] + pub fn filten5(&self) -> FILTEN5_R { + FILTEN5_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bits 24:26 - Input Sense Configuration 6"] + #[inline(always)] + pub fn sense6(&self) -> SENSE6_R { + SENSE6_R::new(((self.bits >> 24) & 0x07) as u8) + } + #[doc = "Bit 27 - Filter Enable 6"] + #[inline(always)] + pub fn filten6(&self) -> FILTEN6_R { + FILTEN6_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bits 28:30 - Input Sense Configuration 7"] + #[inline(always)] + pub fn sense7(&self) -> SENSE7_R { + SENSE7_R::new(((self.bits >> 28) & 0x07) as u8) + } + #[doc = "Bit 31 - Filter Enable 7"] + #[inline(always)] + pub fn filten7(&self) -> FILTEN7_R { + FILTEN7_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Input Sense Configuration 0"] + #[inline(always)] + pub fn sense0(&mut self) -> SENSE0_W { + SENSE0_W { w: self } + } + #[doc = "Bit 3 - Filter Enable 0"] + #[inline(always)] + pub fn filten0(&mut self) -> FILTEN0_W { + FILTEN0_W { w: self } + } + #[doc = "Bits 4:6 - Input Sense Configuration 1"] + #[inline(always)] + pub fn sense1(&mut self) -> SENSE1_W { + SENSE1_W { w: self } + } + #[doc = "Bit 7 - Filter Enable 1"] + #[inline(always)] + pub fn filten1(&mut self) -> FILTEN1_W { + FILTEN1_W { w: self } + } + #[doc = "Bits 8:10 - Input Sense Configuration 2"] + #[inline(always)] + pub fn sense2(&mut self) -> SENSE2_W { + SENSE2_W { w: self } + } + #[doc = "Bit 11 - Filter Enable 2"] + #[inline(always)] + pub fn filten2(&mut self) -> FILTEN2_W { + FILTEN2_W { w: self } + } + #[doc = "Bits 12:14 - Input Sense Configuration 3"] + #[inline(always)] + pub fn sense3(&mut self) -> SENSE3_W { + SENSE3_W { w: self } + } + #[doc = "Bit 15 - Filter Enable 3"] + #[inline(always)] + pub fn filten3(&mut self) -> FILTEN3_W { + FILTEN3_W { w: self } + } + #[doc = "Bits 16:18 - Input Sense Configuration 4"] + #[inline(always)] + pub fn sense4(&mut self) -> SENSE4_W { + SENSE4_W { w: self } + } + #[doc = "Bit 19 - Filter Enable 4"] + #[inline(always)] + pub fn filten4(&mut self) -> FILTEN4_W { + FILTEN4_W { w: self } + } + #[doc = "Bits 20:22 - Input Sense Configuration 5"] + #[inline(always)] + pub fn sense5(&mut self) -> SENSE5_W { + SENSE5_W { w: self } + } + #[doc = "Bit 23 - Filter Enable 5"] + #[inline(always)] + pub fn filten5(&mut self) -> FILTEN5_W { + FILTEN5_W { w: self } + } + #[doc = "Bits 24:26 - Input Sense Configuration 6"] + #[inline(always)] + pub fn sense6(&mut self) -> SENSE6_W { + SENSE6_W { w: self } + } + #[doc = "Bit 27 - Filter Enable 6"] + #[inline(always)] + pub fn filten6(&mut self) -> FILTEN6_W { + FILTEN6_W { w: self } + } + #[doc = "Bits 28:30 - Input Sense Configuration 7"] + #[inline(always)] + pub fn sense7(&mut self) -> SENSE7_W { + SENSE7_W { w: self } + } + #[doc = "Bit 31 - Filter Enable 7"] + #[inline(always)] + pub fn filten7(&mut self) -> FILTEN7_W { + FILTEN7_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Configuration n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [config](index.html) module"] +pub struct CONFIG_SPEC; +impl crate::RegisterSpec for CONFIG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [config::R](R) reader structure"] +impl crate::Readable for CONFIG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [config::W](W) writer structure"] +impl crate::Writable for CONFIG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CONFIG[%s] +to value 0"] +impl crate::Resettable for CONFIG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/eic/ctrla.rs b/pac/atsamc21g/src/eic/ctrla.rs new file mode 100644 index 000000000000..25e701dd3db2 --- /dev/null +++ b/pac/atsamc21g/src/eic/ctrla.rs @@ -0,0 +1,254 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Clock Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CKSEL_A { + #[doc = "0: Clocked by GCLK"] + CLK_GCLK = 0, + #[doc = "1: Clocked by ULP32K"] + CLK_ULP32K = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CKSEL_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CKSEL` reader - Clock Selection"] +pub struct CKSEL_R(crate::FieldReader); +impl CKSEL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CKSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CKSEL_A { + match self.bits { + false => CKSEL_A::CLK_GCLK, + true => CKSEL_A::CLK_ULP32K, + } + } + #[doc = "Checks if the value of the field is `CLK_GCLK`"] + #[inline(always)] + pub fn is_clk_gclk(&self) -> bool { + **self == CKSEL_A::CLK_GCLK + } + #[doc = "Checks if the value of the field is `CLK_ULP32K`"] + #[inline(always)] + pub fn is_clk_ulp32k(&self) -> bool { + **self == CKSEL_A::CLK_ULP32K + } +} +impl core::ops::Deref for CKSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CKSEL` writer - Clock Selection"] +pub struct CKSEL_W<'a> { + w: &'a mut W, +} +impl<'a> CKSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CKSEL_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Clocked by GCLK"] + #[inline(always)] + pub fn clk_gclk(self) -> &'a mut W { + self.variant(CKSEL_A::CLK_GCLK) + } + #[doc = "Clocked by ULP32K"] + #[inline(always)] + pub fn clk_ulp32k(self) -> &'a mut W { + self.variant(CKSEL_A::CLK_ULP32K) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - Clock Selection"] + #[inline(always)] + pub fn cksel(&self) -> CKSEL_R { + CKSEL_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 4 - Clock Selection"] + #[inline(always)] + pub fn cksel(&mut self) -> CKSEL_W { + CKSEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/eic/evctrl.rs b/pac/atsamc21g/src/eic/evctrl.rs new file mode 100644 index 000000000000..25adccf3558e --- /dev/null +++ b/pac/atsamc21g/src/eic/evctrl.rs @@ -0,0 +1,103 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EXTINTEO` reader - External Interrupt Event Output Enable"] +pub struct EXTINTEO_R(crate::FieldReader); +impl EXTINTEO_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + EXTINTEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINTEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINTEO` writer - External Interrupt Event Output Enable"] +pub struct EXTINTEO_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINTEO_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - External Interrupt Event Output Enable"] + #[inline(always)] + pub fn extinteo(&self) -> EXTINTEO_R { + EXTINTEO_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - External Interrupt Event Output Enable"] + #[inline(always)] + pub fn extinteo(&mut self) -> EXTINTEO_W { + EXTINTEO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/eic/intenclr.rs b/pac/atsamc21g/src/eic/intenclr.rs new file mode 100644 index 000000000000..198c3aac9eb1 --- /dev/null +++ b/pac/atsamc21g/src/eic/intenclr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EXTINT` reader - External Interrupt Disable"] +pub struct EXTINT_R(crate::FieldReader); +impl EXTINT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + EXTINT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT` writer - External Interrupt Disable"] +pub struct EXTINT_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - External Interrupt Disable"] + #[inline(always)] + pub fn extint(&self) -> EXTINT_R { + EXTINT_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - External Interrupt Disable"] + #[inline(always)] + pub fn extint(&mut self) -> EXTINT_W { + EXTINT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/eic/intenset.rs b/pac/atsamc21g/src/eic/intenset.rs new file mode 100644 index 000000000000..e2ff6729d71f --- /dev/null +++ b/pac/atsamc21g/src/eic/intenset.rs @@ -0,0 +1,103 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EXTINT` reader - External Interrupt Enable"] +pub struct EXTINT_R(crate::FieldReader); +impl EXTINT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + EXTINT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT` writer - External Interrupt Enable"] +pub struct EXTINT_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - External Interrupt Enable"] + #[inline(always)] + pub fn extint(&self) -> EXTINT_R { + EXTINT_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - External Interrupt Enable"] + #[inline(always)] + pub fn extint(&mut self) -> EXTINT_W { + EXTINT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/eic/intflag.rs b/pac/atsamc21g/src/eic/intflag.rs new file mode 100644 index 000000000000..df2f15490feb --- /dev/null +++ b/pac/atsamc21g/src/eic/intflag.rs @@ -0,0 +1,103 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EXTINT` reader - External Interrupt Flag"] +pub struct EXTINT_R(crate::FieldReader); +impl EXTINT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + EXTINT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT` writer - External Interrupt Flag"] +pub struct EXTINT_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - External Interrupt Flag"] + #[inline(always)] + pub fn extint(&self) -> EXTINT_R { + EXTINT_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - External Interrupt Flag"] + #[inline(always)] + pub fn extint(&mut self) -> EXTINT_W { + EXTINT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/eic/nmictrl.rs b/pac/atsamc21g/src/eic/nmictrl.rs new file mode 100644 index 000000000000..c9b276ea2a29 --- /dev/null +++ b/pac/atsamc21g/src/eic/nmictrl.rs @@ -0,0 +1,345 @@ +#[doc = "Register `NMICTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `NMICTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "NMI Input Sense Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum NMISENSE_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising-edge detection"] + RISE = 1, + #[doc = "2: Falling-edge detection"] + FALL = 2, + #[doc = "3: Both-edges detection"] + BOTH = 3, + #[doc = "4: High-level detection"] + HIGH = 4, + #[doc = "5: Low-level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: NMISENSE_A) -> Self { + variant as _ + } +} +#[doc = "Field `NMISENSE` reader - NMI Input Sense Configuration"] +pub struct NMISENSE_R(crate::FieldReader); +impl NMISENSE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + NMISENSE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(NMISENSE_A::NONE), + 1 => Some(NMISENSE_A::RISE), + 2 => Some(NMISENSE_A::FALL), + 3 => Some(NMISENSE_A::BOTH), + 4 => Some(NMISENSE_A::HIGH), + 5 => Some(NMISENSE_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == NMISENSE_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == NMISENSE_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == NMISENSE_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == NMISENSE_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == NMISENSE_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == NMISENSE_A::LOW + } +} +impl core::ops::Deref for NMISENSE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NMISENSE` writer - NMI Input Sense Configuration"] +pub struct NMISENSE_W<'a> { + w: &'a mut W, +} +impl<'a> NMISENSE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: NMISENSE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(NMISENSE_A::NONE) + } + #[doc = "Rising-edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(NMISENSE_A::RISE) + } + #[doc = "Falling-edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(NMISENSE_A::FALL) + } + #[doc = "Both-edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(NMISENSE_A::BOTH) + } + #[doc = "High-level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(NMISENSE_A::HIGH) + } + #[doc = "Low-level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(NMISENSE_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +#[doc = "Field `NMIFILTEN` reader - NMI Filter Enable"] +pub struct NMIFILTEN_R(crate::FieldReader); +impl NMIFILTEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NMIFILTEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NMIFILTEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NMIFILTEN` writer - NMI Filter Enable"] +pub struct NMIFILTEN_W<'a> { + w: &'a mut W, +} +impl<'a> NMIFILTEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "NMI Asynchronous edge Detection Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum NMIASYNCH_A { + #[doc = "0: Edge detection is clock synchronously operated"] + SYNC = 0, + #[doc = "1: Edge detection is clock asynchronously operated"] + ASYNC = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NMIASYNCH_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NMIASYNCH` reader - NMI Asynchronous edge Detection Enable"] +pub struct NMIASYNCH_R(crate::FieldReader); +impl NMIASYNCH_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NMIASYNCH_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> NMIASYNCH_A { + match self.bits { + false => NMIASYNCH_A::SYNC, + true => NMIASYNCH_A::ASYNC, + } + } + #[doc = "Checks if the value of the field is `SYNC`"] + #[inline(always)] + pub fn is_sync(&self) -> bool { + **self == NMIASYNCH_A::SYNC + } + #[doc = "Checks if the value of the field is `ASYNC`"] + #[inline(always)] + pub fn is_async(&self) -> bool { + **self == NMIASYNCH_A::ASYNC + } +} +impl core::ops::Deref for NMIASYNCH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NMIASYNCH` writer - NMI Asynchronous edge Detection Enable"] +pub struct NMIASYNCH_W<'a> { + w: &'a mut W, +} +impl<'a> NMIASYNCH_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: NMIASYNCH_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Edge detection is clock synchronously operated"] + #[inline(always)] + pub fn sync(self) -> &'a mut W { + self.variant(NMIASYNCH_A::SYNC) + } + #[doc = "Edge detection is clock asynchronously operated"] + #[inline(always)] + pub fn async_(self) -> &'a mut W { + self.variant(NMIASYNCH_A::ASYNC) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - NMI Input Sense Configuration"] + #[inline(always)] + pub fn nmisense(&self) -> NMISENSE_R { + NMISENSE_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 3 - NMI Filter Enable"] + #[inline(always)] + pub fn nmifilten(&self) -> NMIFILTEN_R { + NMIFILTEN_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - NMI Asynchronous edge Detection Enable"] + #[inline(always)] + pub fn nmiasynch(&self) -> NMIASYNCH_R { + NMIASYNCH_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - NMI Input Sense Configuration"] + #[inline(always)] + pub fn nmisense(&mut self) -> NMISENSE_W { + NMISENSE_W { w: self } + } + #[doc = "Bit 3 - NMI Filter Enable"] + #[inline(always)] + pub fn nmifilten(&mut self) -> NMIFILTEN_W { + NMIFILTEN_W { w: self } + } + #[doc = "Bit 4 - NMI Asynchronous edge Detection Enable"] + #[inline(always)] + pub fn nmiasynch(&mut self) -> NMIASYNCH_W { + NMIASYNCH_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "NMI Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [nmictrl](index.html) module"] +pub struct NMICTRL_SPEC; +impl crate::RegisterSpec for NMICTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [nmictrl::R](R) reader structure"] +impl crate::Readable for NMICTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [nmictrl::W](W) writer structure"] +impl crate::Writable for NMICTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets NMICTRL to value 0"] +impl crate::Resettable for NMICTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/eic/nmiflag.rs b/pac/atsamc21g/src/eic/nmiflag.rs new file mode 100644 index 000000000000..97934b501c12 --- /dev/null +++ b/pac/atsamc21g/src/eic/nmiflag.rs @@ -0,0 +1,113 @@ +#[doc = "Register `NMIFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `NMIFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `NMI` reader - NMI Interrupt Flag"] +pub struct NMI_R(crate::FieldReader); +impl NMI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NMI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NMI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NMI` writer - NMI Interrupt Flag"] +pub struct NMI_W<'a> { + w: &'a mut W, +} +impl<'a> NMI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - NMI Interrupt Flag"] + #[inline(always)] + pub fn nmi(&self) -> NMI_R { + NMI_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - NMI Interrupt Flag"] + #[inline(always)] + pub fn nmi(&mut self) -> NMI_W { + NMI_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "NMI Interrupt Flag\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [nmiflag](index.html) module"] +pub struct NMIFLAG_SPEC; +impl crate::RegisterSpec for NMIFLAG_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [nmiflag::R](R) reader structure"] +impl crate::Readable for NMIFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [nmiflag::W](W) writer structure"] +impl crate::Writable for NMIFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets NMIFLAG to value 0"] +impl crate::Resettable for NMIFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/eic/syncbusy.rs b/pac/atsamc21g/src/eic/syncbusy.rs new file mode 100644 index 000000000000..84d125d0acf1 --- /dev/null +++ b/pac/atsamc21g/src/eic/syncbusy.rs @@ -0,0 +1,73 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software reset synchronisation"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - Enable synchronisation"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software reset synchronisation"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable synchronisation"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +#[doc = "Syncbusy register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/evsys.rs b/pac/atsamc21g/src/evsys.rs new file mode 100644 index 000000000000..9e54201975f7 --- /dev/null +++ b/pac/atsamc21g/src/evsys.rs @@ -0,0 +1,54 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrla: crate::Reg, + _reserved1: [u8; 0x0b], + #[doc = "0x0c - Channel Status"] + pub chstatus: crate::Reg, + #[doc = "0x10 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x14 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x18 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x1c - Software Event"] + pub swevt: crate::Reg, + #[doc = "0x20..0x50 - Channel n"] + pub channel: [crate::Reg; 12], + _reserved7: [u8; 0x30], + #[doc = "0x80..0x13c - User Multiplexer n"] + pub user: [crate::Reg; 47], +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control"] +pub mod ctrla; +#[doc = "CHSTATUS register accessor: an alias for `Reg`"] +pub type CHSTATUS = crate::Reg; +#[doc = "Channel Status"] +pub mod chstatus; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "SWEVT register accessor: an alias for `Reg`"] +pub type SWEVT = crate::Reg; +#[doc = "Software Event"] +pub mod swevt; +#[doc = "CHANNEL register accessor: an alias for `Reg`"] +pub type CHANNEL = crate::Reg; +#[doc = "Channel n"] +pub mod channel; +#[doc = "USER register accessor: an alias for `Reg`"] +pub type USER = crate::Reg; +#[doc = "User Multiplexer n"] +pub mod user; diff --git a/pac/atsamc21g/src/evsys/channel.rs b/pac/atsamc21g/src/evsys/channel.rs new file mode 100644 index 000000000000..20e3857da922 --- /dev/null +++ b/pac/atsamc21g/src/evsys/channel.rs @@ -0,0 +1,409 @@ +#[doc = "Register `CHANNEL[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHANNEL[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVGEN` reader - Event Generator Selection"] +pub struct EVGEN_R(crate::FieldReader); +impl EVGEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVGEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVGEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVGEN` writer - Event Generator Selection"] +pub struct EVGEN_W<'a> { + w: &'a mut W, +} +impl<'a> EVGEN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x7f) | (value as u32 & 0x7f); + self.w + } +} +#[doc = "Path Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PATH_A { + #[doc = "0: Synchronous path"] + SYNCHRONOUS = 0, + #[doc = "1: Resynchronized path"] + RESYNCHRONIZED = 1, + #[doc = "2: Asynchronous path"] + ASYNCHRONOUS = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PATH_A) -> Self { + variant as _ + } +} +#[doc = "Field `PATH` reader - Path Selection"] +pub struct PATH_R(crate::FieldReader); +impl PATH_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PATH_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PATH_A::SYNCHRONOUS), + 1 => Some(PATH_A::RESYNCHRONIZED), + 2 => Some(PATH_A::ASYNCHRONOUS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `SYNCHRONOUS`"] + #[inline(always)] + pub fn is_synchronous(&self) -> bool { + **self == PATH_A::SYNCHRONOUS + } + #[doc = "Checks if the value of the field is `RESYNCHRONIZED`"] + #[inline(always)] + pub fn is_resynchronized(&self) -> bool { + **self == PATH_A::RESYNCHRONIZED + } + #[doc = "Checks if the value of the field is `ASYNCHRONOUS`"] + #[inline(always)] + pub fn is_asynchronous(&self) -> bool { + **self == PATH_A::ASYNCHRONOUS + } +} +impl core::ops::Deref for PATH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PATH` writer - Path Selection"] +pub struct PATH_W<'a> { + w: &'a mut W, +} +impl<'a> PATH_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PATH_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Synchronous path"] + #[inline(always)] + pub fn synchronous(self) -> &'a mut W { + self.variant(PATH_A::SYNCHRONOUS) + } + #[doc = "Resynchronized path"] + #[inline(always)] + pub fn resynchronized(self) -> &'a mut W { + self.variant(PATH_A::RESYNCHRONIZED) + } + #[doc = "Asynchronous path"] + #[inline(always)] + pub fn asynchronous(self) -> &'a mut W { + self.variant(PATH_A::ASYNCHRONOUS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 8)) | ((value as u32 & 0x03) << 8); + self.w + } +} +#[doc = "Edge Detection Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EDGSEL_A { + #[doc = "0: No event output when using the resynchronized or synchronous path"] + NO_EVT_OUTPUT = 0, + #[doc = "1: Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path"] + RISING_EDGE = 1, + #[doc = "2: Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path"] + FALLING_EDGE = 2, + #[doc = "3: Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path"] + BOTH_EDGES = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EDGSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `EDGSEL` reader - Edge Detection Selection"] +pub struct EDGSEL_R(crate::FieldReader); +impl EDGSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EDGSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EDGSEL_A { + match self.bits { + 0 => EDGSEL_A::NO_EVT_OUTPUT, + 1 => EDGSEL_A::RISING_EDGE, + 2 => EDGSEL_A::FALLING_EDGE, + 3 => EDGSEL_A::BOTH_EDGES, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NO_EVT_OUTPUT`"] + #[inline(always)] + pub fn is_no_evt_output(&self) -> bool { + **self == EDGSEL_A::NO_EVT_OUTPUT + } + #[doc = "Checks if the value of the field is `RISING_EDGE`"] + #[inline(always)] + pub fn is_rising_edge(&self) -> bool { + **self == EDGSEL_A::RISING_EDGE + } + #[doc = "Checks if the value of the field is `FALLING_EDGE`"] + #[inline(always)] + pub fn is_falling_edge(&self) -> bool { + **self == EDGSEL_A::FALLING_EDGE + } + #[doc = "Checks if the value of the field is `BOTH_EDGES`"] + #[inline(always)] + pub fn is_both_edges(&self) -> bool { + **self == EDGSEL_A::BOTH_EDGES + } +} +impl core::ops::Deref for EDGSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EDGSEL` writer - Edge Detection Selection"] +pub struct EDGSEL_W<'a> { + w: &'a mut W, +} +impl<'a> EDGSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EDGSEL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "No event output when using the resynchronized or synchronous path"] + #[inline(always)] + pub fn no_evt_output(self) -> &'a mut W { + self.variant(EDGSEL_A::NO_EVT_OUTPUT) + } + #[doc = "Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path"] + #[inline(always)] + pub fn rising_edge(self) -> &'a mut W { + self.variant(EDGSEL_A::RISING_EDGE) + } + #[doc = "Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path"] + #[inline(always)] + pub fn falling_edge(self) -> &'a mut W { + self.variant(EDGSEL_A::FALLING_EDGE) + } + #[doc = "Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path"] + #[inline(always)] + pub fn both_edges(self) -> &'a mut W { + self.variant(EDGSEL_A::BOTH_EDGES) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 10)) | ((value as u32 & 0x03) << 10); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - Generic Clock On Demand"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - Generic Clock On Demand"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bits 0:6 - Event Generator Selection"] + #[inline(always)] + pub fn evgen(&self) -> EVGEN_R { + EVGEN_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bits 8:9 - Path Selection"] + #[inline(always)] + pub fn path(&self) -> PATH_R { + PATH_R::new(((self.bits >> 8) & 0x03) as u8) + } + #[doc = "Bits 10:11 - Edge Detection Selection"] + #[inline(always)] + pub fn edgsel(&self) -> EDGSEL_R { + EDGSEL_R::new(((self.bits >> 10) & 0x03) as u8) + } + #[doc = "Bit 14 - Run in standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Generic Clock On Demand"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:6 - Event Generator Selection"] + #[inline(always)] + pub fn evgen(&mut self) -> EVGEN_W { + EVGEN_W { w: self } + } + #[doc = "Bits 8:9 - Path Selection"] + #[inline(always)] + pub fn path(&mut self) -> PATH_W { + PATH_W { w: self } + } + #[doc = "Bits 10:11 - Edge Detection Selection"] + #[inline(always)] + pub fn edgsel(&mut self) -> EDGSEL_W { + EDGSEL_W { w: self } + } + #[doc = "Bit 14 - Run in standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 15 - Generic Clock On Demand"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [channel](index.html) module"] +pub struct CHANNEL_SPEC; +impl crate::RegisterSpec for CHANNEL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [channel::R](R) reader structure"] +impl crate::Readable for CHANNEL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [channel::W](W) writer structure"] +impl crate::Writable for CHANNEL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHANNEL[%s] +to value 0x8000"] +impl crate::Resettable for CHANNEL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x8000 + } +} diff --git a/pac/atsamc21g/src/evsys/chstatus.rs b/pac/atsamc21g/src/evsys/chstatus.rs new file mode 100644 index 000000000000..811089dfdeb8 --- /dev/null +++ b/pac/atsamc21g/src/evsys/chstatus.rs @@ -0,0 +1,513 @@ +#[doc = "Register `CHSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `USRRDY0` reader - Channel 0 User Ready"] +pub struct USRRDY0_R(crate::FieldReader); +impl USRRDY0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY1` reader - Channel 1 User Ready"] +pub struct USRRDY1_R(crate::FieldReader); +impl USRRDY1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY2` reader - Channel 2 User Ready"] +pub struct USRRDY2_R(crate::FieldReader); +impl USRRDY2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY3` reader - Channel 3 User Ready"] +pub struct USRRDY3_R(crate::FieldReader); +impl USRRDY3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY4` reader - Channel 4 User Ready"] +pub struct USRRDY4_R(crate::FieldReader); +impl USRRDY4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY5` reader - Channel 5 User Ready"] +pub struct USRRDY5_R(crate::FieldReader); +impl USRRDY5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY6` reader - Channel 6 User Ready"] +pub struct USRRDY6_R(crate::FieldReader); +impl USRRDY6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY7` reader - Channel 7 User Ready"] +pub struct USRRDY7_R(crate::FieldReader); +impl USRRDY7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY8` reader - Channel 8 User Ready"] +pub struct USRRDY8_R(crate::FieldReader); +impl USRRDY8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY9` reader - Channel 9 User Ready"] +pub struct USRRDY9_R(crate::FieldReader); +impl USRRDY9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY10` reader - Channel 10 User Ready"] +pub struct USRRDY10_R(crate::FieldReader); +impl USRRDY10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY11` reader - Channel 11 User Ready"] +pub struct USRRDY11_R(crate::FieldReader); +impl USRRDY11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY0` reader - Channel 0 Busy"] +pub struct CHBUSY0_R(crate::FieldReader); +impl CHBUSY0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY1` reader - Channel 1 Busy"] +pub struct CHBUSY1_R(crate::FieldReader); +impl CHBUSY1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY2` reader - Channel 2 Busy"] +pub struct CHBUSY2_R(crate::FieldReader); +impl CHBUSY2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY3` reader - Channel 3 Busy"] +pub struct CHBUSY3_R(crate::FieldReader); +impl CHBUSY3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY4` reader - Channel 4 Busy"] +pub struct CHBUSY4_R(crate::FieldReader); +impl CHBUSY4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY5` reader - Channel 5 Busy"] +pub struct CHBUSY5_R(crate::FieldReader); +impl CHBUSY5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY6` reader - Channel 6 Busy"] +pub struct CHBUSY6_R(crate::FieldReader); +impl CHBUSY6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY7` reader - Channel 7 Busy"] +pub struct CHBUSY7_R(crate::FieldReader); +impl CHBUSY7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY8` reader - Channel 8 Busy"] +pub struct CHBUSY8_R(crate::FieldReader); +impl CHBUSY8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY9` reader - Channel 9 Busy"] +pub struct CHBUSY9_R(crate::FieldReader); +impl CHBUSY9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY10` reader - Channel 10 Busy"] +pub struct CHBUSY10_R(crate::FieldReader); +impl CHBUSY10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY11` reader - Channel 11 Busy"] +pub struct CHBUSY11_R(crate::FieldReader); +impl CHBUSY11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Channel 0 User Ready"] + #[inline(always)] + pub fn usrrdy0(&self) -> USRRDY0_R { + USRRDY0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel 1 User Ready"] + #[inline(always)] + pub fn usrrdy1(&self) -> USRRDY1_R { + USRRDY1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel 2 User Ready"] + #[inline(always)] + pub fn usrrdy2(&self) -> USRRDY2_R { + USRRDY2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Channel 3 User Ready"] + #[inline(always)] + pub fn usrrdy3(&self) -> USRRDY3_R { + USRRDY3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Channel 4 User Ready"] + #[inline(always)] + pub fn usrrdy4(&self) -> USRRDY4_R { + USRRDY4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Channel 5 User Ready"] + #[inline(always)] + pub fn usrrdy5(&self) -> USRRDY5_R { + USRRDY5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Channel 6 User Ready"] + #[inline(always)] + pub fn usrrdy6(&self) -> USRRDY6_R { + USRRDY6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Channel 7 User Ready"] + #[inline(always)] + pub fn usrrdy7(&self) -> USRRDY7_R { + USRRDY7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Channel 8 User Ready"] + #[inline(always)] + pub fn usrrdy8(&self) -> USRRDY8_R { + USRRDY8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Channel 9 User Ready"] + #[inline(always)] + pub fn usrrdy9(&self) -> USRRDY9_R { + USRRDY9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Channel 10 User Ready"] + #[inline(always)] + pub fn usrrdy10(&self) -> USRRDY10_R { + USRRDY10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Channel 11 User Ready"] + #[inline(always)] + pub fn usrrdy11(&self) -> USRRDY11_R { + USRRDY11_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 16 - Channel 0 Busy"] + #[inline(always)] + pub fn chbusy0(&self) -> CHBUSY0_R { + CHBUSY0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Channel 1 Busy"] + #[inline(always)] + pub fn chbusy1(&self) -> CHBUSY1_R { + CHBUSY1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Channel 2 Busy"] + #[inline(always)] + pub fn chbusy2(&self) -> CHBUSY2_R { + CHBUSY2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Channel 3 Busy"] + #[inline(always)] + pub fn chbusy3(&self) -> CHBUSY3_R { + CHBUSY3_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Channel 4 Busy"] + #[inline(always)] + pub fn chbusy4(&self) -> CHBUSY4_R { + CHBUSY4_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Channel 5 Busy"] + #[inline(always)] + pub fn chbusy5(&self) -> CHBUSY5_R { + CHBUSY5_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Channel 6 Busy"] + #[inline(always)] + pub fn chbusy6(&self) -> CHBUSY6_R { + CHBUSY6_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Channel 7 Busy"] + #[inline(always)] + pub fn chbusy7(&self) -> CHBUSY7_R { + CHBUSY7_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24 - Channel 8 Busy"] + #[inline(always)] + pub fn chbusy8(&self) -> CHBUSY8_R { + CHBUSY8_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Channel 9 Busy"] + #[inline(always)] + pub fn chbusy9(&self) -> CHBUSY9_R { + CHBUSY9_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Channel 10 Busy"] + #[inline(always)] + pub fn chbusy10(&self) -> CHBUSY10_R { + CHBUSY10_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Channel 11 Busy"] + #[inline(always)] + pub fn chbusy11(&self) -> CHBUSY11_R { + CHBUSY11_R::new(((self.bits >> 27) & 0x01) != 0) + } +} +#[doc = "Channel Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chstatus](index.html) module"] +pub struct CHSTATUS_SPEC; +impl crate::RegisterSpec for CHSTATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [chstatus::R](R) reader structure"] +impl crate::Readable for CHSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CHSTATUS to value 0"] +impl crate::Resettable for CHSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/evsys/ctrla.rs b/pac/atsamc21g/src/evsys/ctrla.rs new file mode 100644 index 000000000000..1c24704395ad --- /dev/null +++ b/pac/atsamc21g/src/evsys/ctrla.rs @@ -0,0 +1,113 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/evsys/intenclr.rs b/pac/atsamc21g/src/evsys/intenclr.rs new file mode 100644 index 000000000000..6a6a0b2b94c5 --- /dev/null +++ b/pac/atsamc21g/src/evsys/intenclr.rs @@ -0,0 +1,1194 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVR0` reader - Channel 0 Overrun Interrupt Enable"] +pub struct OVR0_R(crate::FieldReader); +impl OVR0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR0` writer - Channel 0 Overrun Interrupt Enable"] +pub struct OVR0_W<'a> { + w: &'a mut W, +} +impl<'a> OVR0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `OVR1` reader - Channel 1 Overrun Interrupt Enable"] +pub struct OVR1_R(crate::FieldReader); +impl OVR1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR1` writer - Channel 1 Overrun Interrupt Enable"] +pub struct OVR1_W<'a> { + w: &'a mut W, +} +impl<'a> OVR1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `OVR2` reader - Channel 2 Overrun Interrupt Enable"] +pub struct OVR2_R(crate::FieldReader); +impl OVR2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR2` writer - Channel 2 Overrun Interrupt Enable"] +pub struct OVR2_W<'a> { + w: &'a mut W, +} +impl<'a> OVR2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `OVR3` reader - Channel 3 Overrun Interrupt Enable"] +pub struct OVR3_R(crate::FieldReader); +impl OVR3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR3` writer - Channel 3 Overrun Interrupt Enable"] +pub struct OVR3_W<'a> { + w: &'a mut W, +} +impl<'a> OVR3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `OVR4` reader - Channel 4 Overrun Interrupt Enable"] +pub struct OVR4_R(crate::FieldReader); +impl OVR4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR4` writer - Channel 4 Overrun Interrupt Enable"] +pub struct OVR4_W<'a> { + w: &'a mut W, +} +impl<'a> OVR4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `OVR5` reader - Channel 5 Overrun Interrupt Enable"] +pub struct OVR5_R(crate::FieldReader); +impl OVR5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR5` writer - Channel 5 Overrun Interrupt Enable"] +pub struct OVR5_W<'a> { + w: &'a mut W, +} +impl<'a> OVR5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `OVR6` reader - Channel 6 Overrun Interrupt Enable"] +pub struct OVR6_R(crate::FieldReader); +impl OVR6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR6` writer - Channel 6 Overrun Interrupt Enable"] +pub struct OVR6_W<'a> { + w: &'a mut W, +} +impl<'a> OVR6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `OVR7` reader - Channel 7 Overrun Interrupt Enable"] +pub struct OVR7_R(crate::FieldReader); +impl OVR7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR7` writer - Channel 7 Overrun Interrupt Enable"] +pub struct OVR7_W<'a> { + w: &'a mut W, +} +impl<'a> OVR7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `OVR8` reader - Channel 8 Overrun Interrupt Enable"] +pub struct OVR8_R(crate::FieldReader); +impl OVR8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR8` writer - Channel 8 Overrun Interrupt Enable"] +pub struct OVR8_W<'a> { + w: &'a mut W, +} +impl<'a> OVR8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `OVR9` reader - Channel 9 Overrun Interrupt Enable"] +pub struct OVR9_R(crate::FieldReader); +impl OVR9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR9` writer - Channel 9 Overrun Interrupt Enable"] +pub struct OVR9_W<'a> { + w: &'a mut W, +} +impl<'a> OVR9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `OVR10` reader - Channel 10 Overrun Interrupt Enable"] +pub struct OVR10_R(crate::FieldReader); +impl OVR10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR10` writer - Channel 10 Overrun Interrupt Enable"] +pub struct OVR10_W<'a> { + w: &'a mut W, +} +impl<'a> OVR10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `OVR11` reader - Channel 11 Overrun Interrupt Enable"] +pub struct OVR11_R(crate::FieldReader); +impl OVR11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR11` writer - Channel 11 Overrun Interrupt Enable"] +pub struct OVR11_W<'a> { + w: &'a mut W, +} +impl<'a> OVR11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `EVD0` reader - Channel 0 Event Detection Interrupt Enable"] +pub struct EVD0_R(crate::FieldReader); +impl EVD0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD0` writer - Channel 0 Event Detection Interrupt Enable"] +pub struct EVD0_W<'a> { + w: &'a mut W, +} +impl<'a> EVD0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `EVD1` reader - Channel 1 Event Detection Interrupt Enable"] +pub struct EVD1_R(crate::FieldReader); +impl EVD1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD1` writer - Channel 1 Event Detection Interrupt Enable"] +pub struct EVD1_W<'a> { + w: &'a mut W, +} +impl<'a> EVD1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `EVD2` reader - Channel 2 Event Detection Interrupt Enable"] +pub struct EVD2_R(crate::FieldReader); +impl EVD2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD2` writer - Channel 2 Event Detection Interrupt Enable"] +pub struct EVD2_W<'a> { + w: &'a mut W, +} +impl<'a> EVD2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `EVD3` reader - Channel 3 Event Detection Interrupt Enable"] +pub struct EVD3_R(crate::FieldReader); +impl EVD3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD3` writer - Channel 3 Event Detection Interrupt Enable"] +pub struct EVD3_W<'a> { + w: &'a mut W, +} +impl<'a> EVD3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `EVD4` reader - Channel 4 Event Detection Interrupt Enable"] +pub struct EVD4_R(crate::FieldReader); +impl EVD4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD4` writer - Channel 4 Event Detection Interrupt Enable"] +pub struct EVD4_W<'a> { + w: &'a mut W, +} +impl<'a> EVD4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `EVD5` reader - Channel 5 Event Detection Interrupt Enable"] +pub struct EVD5_R(crate::FieldReader); +impl EVD5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD5` writer - Channel 5 Event Detection Interrupt Enable"] +pub struct EVD5_W<'a> { + w: &'a mut W, +} +impl<'a> EVD5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `EVD6` reader - Channel 6 Event Detection Interrupt Enable"] +pub struct EVD6_R(crate::FieldReader); +impl EVD6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD6` writer - Channel 6 Event Detection Interrupt Enable"] +pub struct EVD6_W<'a> { + w: &'a mut W, +} +impl<'a> EVD6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `EVD7` reader - Channel 7 Event Detection Interrupt Enable"] +pub struct EVD7_R(crate::FieldReader); +impl EVD7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD7` writer - Channel 7 Event Detection Interrupt Enable"] +pub struct EVD7_W<'a> { + w: &'a mut W, +} +impl<'a> EVD7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `EVD8` reader - Channel 8 Event Detection Interrupt Enable"] +pub struct EVD8_R(crate::FieldReader); +impl EVD8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD8` writer - Channel 8 Event Detection Interrupt Enable"] +pub struct EVD8_W<'a> { + w: &'a mut W, +} +impl<'a> EVD8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `EVD9` reader - Channel 9 Event Detection Interrupt Enable"] +pub struct EVD9_R(crate::FieldReader); +impl EVD9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD9` writer - Channel 9 Event Detection Interrupt Enable"] +pub struct EVD9_W<'a> { + w: &'a mut W, +} +impl<'a> EVD9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `EVD10` reader - Channel 10 Event Detection Interrupt Enable"] +pub struct EVD10_R(crate::FieldReader); +impl EVD10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD10` writer - Channel 10 Event Detection Interrupt Enable"] +pub struct EVD10_W<'a> { + w: &'a mut W, +} +impl<'a> EVD10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `EVD11` reader - Channel 11 Event Detection Interrupt Enable"] +pub struct EVD11_R(crate::FieldReader); +impl EVD11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD11` writer - Channel 11 Event Detection Interrupt Enable"] +pub struct EVD11_W<'a> { + w: &'a mut W, +} +impl<'a> EVD11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +impl R { + #[doc = "Bit 0 - Channel 0 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr0(&self) -> OVR0_R { + OVR0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel 1 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr1(&self) -> OVR1_R { + OVR1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel 2 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr2(&self) -> OVR2_R { + OVR2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Channel 3 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr3(&self) -> OVR3_R { + OVR3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Channel 4 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr4(&self) -> OVR4_R { + OVR4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Channel 5 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr5(&self) -> OVR5_R { + OVR5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Channel 6 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr6(&self) -> OVR6_R { + OVR6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Channel 7 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr7(&self) -> OVR7_R { + OVR7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Channel 8 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr8(&self) -> OVR8_R { + OVR8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Channel 9 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr9(&self) -> OVR9_R { + OVR9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Channel 10 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr10(&self) -> OVR10_R { + OVR10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Channel 11 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr11(&self) -> OVR11_R { + OVR11_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 16 - Channel 0 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd0(&self) -> EVD0_R { + EVD0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Channel 1 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd1(&self) -> EVD1_R { + EVD1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Channel 2 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd2(&self) -> EVD2_R { + EVD2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Channel 3 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd3(&self) -> EVD3_R { + EVD3_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Channel 4 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd4(&self) -> EVD4_R { + EVD4_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Channel 5 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd5(&self) -> EVD5_R { + EVD5_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Channel 6 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd6(&self) -> EVD6_R { + EVD6_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Channel 7 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd7(&self) -> EVD7_R { + EVD7_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24 - Channel 8 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd8(&self) -> EVD8_R { + EVD8_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Channel 9 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd9(&self) -> EVD9_R { + EVD9_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Channel 10 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd10(&self) -> EVD10_R { + EVD10_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Channel 11 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd11(&self) -> EVD11_R { + EVD11_R::new(((self.bits >> 27) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel 0 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr0(&mut self) -> OVR0_W { + OVR0_W { w: self } + } + #[doc = "Bit 1 - Channel 1 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr1(&mut self) -> OVR1_W { + OVR1_W { w: self } + } + #[doc = "Bit 2 - Channel 2 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr2(&mut self) -> OVR2_W { + OVR2_W { w: self } + } + #[doc = "Bit 3 - Channel 3 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr3(&mut self) -> OVR3_W { + OVR3_W { w: self } + } + #[doc = "Bit 4 - Channel 4 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr4(&mut self) -> OVR4_W { + OVR4_W { w: self } + } + #[doc = "Bit 5 - Channel 5 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr5(&mut self) -> OVR5_W { + OVR5_W { w: self } + } + #[doc = "Bit 6 - Channel 6 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr6(&mut self) -> OVR6_W { + OVR6_W { w: self } + } + #[doc = "Bit 7 - Channel 7 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr7(&mut self) -> OVR7_W { + OVR7_W { w: self } + } + #[doc = "Bit 8 - Channel 8 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr8(&mut self) -> OVR8_W { + OVR8_W { w: self } + } + #[doc = "Bit 9 - Channel 9 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr9(&mut self) -> OVR9_W { + OVR9_W { w: self } + } + #[doc = "Bit 10 - Channel 10 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr10(&mut self) -> OVR10_W { + OVR10_W { w: self } + } + #[doc = "Bit 11 - Channel 11 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr11(&mut self) -> OVR11_W { + OVR11_W { w: self } + } + #[doc = "Bit 16 - Channel 0 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd0(&mut self) -> EVD0_W { + EVD0_W { w: self } + } + #[doc = "Bit 17 - Channel 1 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd1(&mut self) -> EVD1_W { + EVD1_W { w: self } + } + #[doc = "Bit 18 - Channel 2 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd2(&mut self) -> EVD2_W { + EVD2_W { w: self } + } + #[doc = "Bit 19 - Channel 3 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd3(&mut self) -> EVD3_W { + EVD3_W { w: self } + } + #[doc = "Bit 20 - Channel 4 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd4(&mut self) -> EVD4_W { + EVD4_W { w: self } + } + #[doc = "Bit 21 - Channel 5 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd5(&mut self) -> EVD5_W { + EVD5_W { w: self } + } + #[doc = "Bit 22 - Channel 6 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd6(&mut self) -> EVD6_W { + EVD6_W { w: self } + } + #[doc = "Bit 23 - Channel 7 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd7(&mut self) -> EVD7_W { + EVD7_W { w: self } + } + #[doc = "Bit 24 - Channel 8 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd8(&mut self) -> EVD8_W { + EVD8_W { w: self } + } + #[doc = "Bit 25 - Channel 9 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd9(&mut self) -> EVD9_W { + EVD9_W { w: self } + } + #[doc = "Bit 26 - Channel 10 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd10(&mut self) -> EVD10_W { + EVD10_W { w: self } + } + #[doc = "Bit 27 - Channel 11 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd11(&mut self) -> EVD11_W { + EVD11_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/evsys/intenset.rs b/pac/atsamc21g/src/evsys/intenset.rs new file mode 100644 index 000000000000..d84061297909 --- /dev/null +++ b/pac/atsamc21g/src/evsys/intenset.rs @@ -0,0 +1,1194 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVR0` reader - Channel 0 Overrun Interrupt Enable"] +pub struct OVR0_R(crate::FieldReader); +impl OVR0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR0` writer - Channel 0 Overrun Interrupt Enable"] +pub struct OVR0_W<'a> { + w: &'a mut W, +} +impl<'a> OVR0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `OVR1` reader - Channel 1 Overrun Interrupt Enable"] +pub struct OVR1_R(crate::FieldReader); +impl OVR1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR1` writer - Channel 1 Overrun Interrupt Enable"] +pub struct OVR1_W<'a> { + w: &'a mut W, +} +impl<'a> OVR1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `OVR2` reader - Channel 2 Overrun Interrupt Enable"] +pub struct OVR2_R(crate::FieldReader); +impl OVR2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR2` writer - Channel 2 Overrun Interrupt Enable"] +pub struct OVR2_W<'a> { + w: &'a mut W, +} +impl<'a> OVR2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `OVR3` reader - Channel 3 Overrun Interrupt Enable"] +pub struct OVR3_R(crate::FieldReader); +impl OVR3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR3` writer - Channel 3 Overrun Interrupt Enable"] +pub struct OVR3_W<'a> { + w: &'a mut W, +} +impl<'a> OVR3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `OVR4` reader - Channel 4 Overrun Interrupt Enable"] +pub struct OVR4_R(crate::FieldReader); +impl OVR4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR4` writer - Channel 4 Overrun Interrupt Enable"] +pub struct OVR4_W<'a> { + w: &'a mut W, +} +impl<'a> OVR4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `OVR5` reader - Channel 5 Overrun Interrupt Enable"] +pub struct OVR5_R(crate::FieldReader); +impl OVR5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR5` writer - Channel 5 Overrun Interrupt Enable"] +pub struct OVR5_W<'a> { + w: &'a mut W, +} +impl<'a> OVR5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `OVR6` reader - Channel 6 Overrun Interrupt Enable"] +pub struct OVR6_R(crate::FieldReader); +impl OVR6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR6` writer - Channel 6 Overrun Interrupt Enable"] +pub struct OVR6_W<'a> { + w: &'a mut W, +} +impl<'a> OVR6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `OVR7` reader - Channel 7 Overrun Interrupt Enable"] +pub struct OVR7_R(crate::FieldReader); +impl OVR7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR7` writer - Channel 7 Overrun Interrupt Enable"] +pub struct OVR7_W<'a> { + w: &'a mut W, +} +impl<'a> OVR7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `OVR8` reader - Channel 8 Overrun Interrupt Enable"] +pub struct OVR8_R(crate::FieldReader); +impl OVR8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR8` writer - Channel 8 Overrun Interrupt Enable"] +pub struct OVR8_W<'a> { + w: &'a mut W, +} +impl<'a> OVR8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `OVR9` reader - Channel 9 Overrun Interrupt Enable"] +pub struct OVR9_R(crate::FieldReader); +impl OVR9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR9` writer - Channel 9 Overrun Interrupt Enable"] +pub struct OVR9_W<'a> { + w: &'a mut W, +} +impl<'a> OVR9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `OVR10` reader - Channel 10 Overrun Interrupt Enable"] +pub struct OVR10_R(crate::FieldReader); +impl OVR10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR10` writer - Channel 10 Overrun Interrupt Enable"] +pub struct OVR10_W<'a> { + w: &'a mut W, +} +impl<'a> OVR10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `OVR11` reader - Channel 11 Overrun Interrupt Enable"] +pub struct OVR11_R(crate::FieldReader); +impl OVR11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR11` writer - Channel 11 Overrun Interrupt Enable"] +pub struct OVR11_W<'a> { + w: &'a mut W, +} +impl<'a> OVR11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `EVD0` reader - Channel 0 Event Detection Interrupt Enable"] +pub struct EVD0_R(crate::FieldReader); +impl EVD0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD0` writer - Channel 0 Event Detection Interrupt Enable"] +pub struct EVD0_W<'a> { + w: &'a mut W, +} +impl<'a> EVD0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `EVD1` reader - Channel 1 Event Detection Interrupt Enable"] +pub struct EVD1_R(crate::FieldReader); +impl EVD1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD1` writer - Channel 1 Event Detection Interrupt Enable"] +pub struct EVD1_W<'a> { + w: &'a mut W, +} +impl<'a> EVD1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `EVD2` reader - Channel 2 Event Detection Interrupt Enable"] +pub struct EVD2_R(crate::FieldReader); +impl EVD2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD2` writer - Channel 2 Event Detection Interrupt Enable"] +pub struct EVD2_W<'a> { + w: &'a mut W, +} +impl<'a> EVD2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `EVD3` reader - Channel 3 Event Detection Interrupt Enable"] +pub struct EVD3_R(crate::FieldReader); +impl EVD3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD3` writer - Channel 3 Event Detection Interrupt Enable"] +pub struct EVD3_W<'a> { + w: &'a mut W, +} +impl<'a> EVD3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `EVD4` reader - Channel 4 Event Detection Interrupt Enable"] +pub struct EVD4_R(crate::FieldReader); +impl EVD4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD4` writer - Channel 4 Event Detection Interrupt Enable"] +pub struct EVD4_W<'a> { + w: &'a mut W, +} +impl<'a> EVD4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `EVD5` reader - Channel 5 Event Detection Interrupt Enable"] +pub struct EVD5_R(crate::FieldReader); +impl EVD5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD5` writer - Channel 5 Event Detection Interrupt Enable"] +pub struct EVD5_W<'a> { + w: &'a mut W, +} +impl<'a> EVD5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `EVD6` reader - Channel 6 Event Detection Interrupt Enable"] +pub struct EVD6_R(crate::FieldReader); +impl EVD6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD6` writer - Channel 6 Event Detection Interrupt Enable"] +pub struct EVD6_W<'a> { + w: &'a mut W, +} +impl<'a> EVD6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `EVD7` reader - Channel 7 Event Detection Interrupt Enable"] +pub struct EVD7_R(crate::FieldReader); +impl EVD7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD7` writer - Channel 7 Event Detection Interrupt Enable"] +pub struct EVD7_W<'a> { + w: &'a mut W, +} +impl<'a> EVD7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `EVD8` reader - Channel 8 Event Detection Interrupt Enable"] +pub struct EVD8_R(crate::FieldReader); +impl EVD8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD8` writer - Channel 8 Event Detection Interrupt Enable"] +pub struct EVD8_W<'a> { + w: &'a mut W, +} +impl<'a> EVD8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `EVD9` reader - Channel 9 Event Detection Interrupt Enable"] +pub struct EVD9_R(crate::FieldReader); +impl EVD9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD9` writer - Channel 9 Event Detection Interrupt Enable"] +pub struct EVD9_W<'a> { + w: &'a mut W, +} +impl<'a> EVD9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `EVD10` reader - Channel 10 Event Detection Interrupt Enable"] +pub struct EVD10_R(crate::FieldReader); +impl EVD10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD10` writer - Channel 10 Event Detection Interrupt Enable"] +pub struct EVD10_W<'a> { + w: &'a mut W, +} +impl<'a> EVD10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `EVD11` reader - Channel 11 Event Detection Interrupt Enable"] +pub struct EVD11_R(crate::FieldReader); +impl EVD11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD11` writer - Channel 11 Event Detection Interrupt Enable"] +pub struct EVD11_W<'a> { + w: &'a mut W, +} +impl<'a> EVD11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +impl R { + #[doc = "Bit 0 - Channel 0 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr0(&self) -> OVR0_R { + OVR0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel 1 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr1(&self) -> OVR1_R { + OVR1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel 2 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr2(&self) -> OVR2_R { + OVR2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Channel 3 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr3(&self) -> OVR3_R { + OVR3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Channel 4 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr4(&self) -> OVR4_R { + OVR4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Channel 5 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr5(&self) -> OVR5_R { + OVR5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Channel 6 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr6(&self) -> OVR6_R { + OVR6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Channel 7 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr7(&self) -> OVR7_R { + OVR7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Channel 8 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr8(&self) -> OVR8_R { + OVR8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Channel 9 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr9(&self) -> OVR9_R { + OVR9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Channel 10 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr10(&self) -> OVR10_R { + OVR10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Channel 11 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr11(&self) -> OVR11_R { + OVR11_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 16 - Channel 0 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd0(&self) -> EVD0_R { + EVD0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Channel 1 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd1(&self) -> EVD1_R { + EVD1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Channel 2 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd2(&self) -> EVD2_R { + EVD2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Channel 3 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd3(&self) -> EVD3_R { + EVD3_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Channel 4 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd4(&self) -> EVD4_R { + EVD4_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Channel 5 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd5(&self) -> EVD5_R { + EVD5_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Channel 6 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd6(&self) -> EVD6_R { + EVD6_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Channel 7 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd7(&self) -> EVD7_R { + EVD7_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24 - Channel 8 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd8(&self) -> EVD8_R { + EVD8_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Channel 9 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd9(&self) -> EVD9_R { + EVD9_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Channel 10 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd10(&self) -> EVD10_R { + EVD10_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Channel 11 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd11(&self) -> EVD11_R { + EVD11_R::new(((self.bits >> 27) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel 0 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr0(&mut self) -> OVR0_W { + OVR0_W { w: self } + } + #[doc = "Bit 1 - Channel 1 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr1(&mut self) -> OVR1_W { + OVR1_W { w: self } + } + #[doc = "Bit 2 - Channel 2 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr2(&mut self) -> OVR2_W { + OVR2_W { w: self } + } + #[doc = "Bit 3 - Channel 3 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr3(&mut self) -> OVR3_W { + OVR3_W { w: self } + } + #[doc = "Bit 4 - Channel 4 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr4(&mut self) -> OVR4_W { + OVR4_W { w: self } + } + #[doc = "Bit 5 - Channel 5 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr5(&mut self) -> OVR5_W { + OVR5_W { w: self } + } + #[doc = "Bit 6 - Channel 6 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr6(&mut self) -> OVR6_W { + OVR6_W { w: self } + } + #[doc = "Bit 7 - Channel 7 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr7(&mut self) -> OVR7_W { + OVR7_W { w: self } + } + #[doc = "Bit 8 - Channel 8 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr8(&mut self) -> OVR8_W { + OVR8_W { w: self } + } + #[doc = "Bit 9 - Channel 9 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr9(&mut self) -> OVR9_W { + OVR9_W { w: self } + } + #[doc = "Bit 10 - Channel 10 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr10(&mut self) -> OVR10_W { + OVR10_W { w: self } + } + #[doc = "Bit 11 - Channel 11 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr11(&mut self) -> OVR11_W { + OVR11_W { w: self } + } + #[doc = "Bit 16 - Channel 0 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd0(&mut self) -> EVD0_W { + EVD0_W { w: self } + } + #[doc = "Bit 17 - Channel 1 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd1(&mut self) -> EVD1_W { + EVD1_W { w: self } + } + #[doc = "Bit 18 - Channel 2 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd2(&mut self) -> EVD2_W { + EVD2_W { w: self } + } + #[doc = "Bit 19 - Channel 3 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd3(&mut self) -> EVD3_W { + EVD3_W { w: self } + } + #[doc = "Bit 20 - Channel 4 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd4(&mut self) -> EVD4_W { + EVD4_W { w: self } + } + #[doc = "Bit 21 - Channel 5 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd5(&mut self) -> EVD5_W { + EVD5_W { w: self } + } + #[doc = "Bit 22 - Channel 6 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd6(&mut self) -> EVD6_W { + EVD6_W { w: self } + } + #[doc = "Bit 23 - Channel 7 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd7(&mut self) -> EVD7_W { + EVD7_W { w: self } + } + #[doc = "Bit 24 - Channel 8 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd8(&mut self) -> EVD8_W { + EVD8_W { w: self } + } + #[doc = "Bit 25 - Channel 9 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd9(&mut self) -> EVD9_W { + EVD9_W { w: self } + } + #[doc = "Bit 26 - Channel 10 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd10(&mut self) -> EVD10_W { + EVD10_W { w: self } + } + #[doc = "Bit 27 - Channel 11 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd11(&mut self) -> EVD11_W { + EVD11_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/evsys/intflag.rs b/pac/atsamc21g/src/evsys/intflag.rs new file mode 100644 index 000000000000..4d5cbe3950f6 --- /dev/null +++ b/pac/atsamc21g/src/evsys/intflag.rs @@ -0,0 +1,1194 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVR0` reader - Channel 0 Overrun"] +pub struct OVR0_R(crate::FieldReader); +impl OVR0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR0` writer - Channel 0 Overrun"] +pub struct OVR0_W<'a> { + w: &'a mut W, +} +impl<'a> OVR0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `OVR1` reader - Channel 1 Overrun"] +pub struct OVR1_R(crate::FieldReader); +impl OVR1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR1` writer - Channel 1 Overrun"] +pub struct OVR1_W<'a> { + w: &'a mut W, +} +impl<'a> OVR1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `OVR2` reader - Channel 2 Overrun"] +pub struct OVR2_R(crate::FieldReader); +impl OVR2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR2` writer - Channel 2 Overrun"] +pub struct OVR2_W<'a> { + w: &'a mut W, +} +impl<'a> OVR2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `OVR3` reader - Channel 3 Overrun"] +pub struct OVR3_R(crate::FieldReader); +impl OVR3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR3` writer - Channel 3 Overrun"] +pub struct OVR3_W<'a> { + w: &'a mut W, +} +impl<'a> OVR3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `OVR4` reader - Channel 4 Overrun"] +pub struct OVR4_R(crate::FieldReader); +impl OVR4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR4` writer - Channel 4 Overrun"] +pub struct OVR4_W<'a> { + w: &'a mut W, +} +impl<'a> OVR4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `OVR5` reader - Channel 5 Overrun"] +pub struct OVR5_R(crate::FieldReader); +impl OVR5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR5` writer - Channel 5 Overrun"] +pub struct OVR5_W<'a> { + w: &'a mut W, +} +impl<'a> OVR5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `OVR6` reader - Channel 6 Overrun"] +pub struct OVR6_R(crate::FieldReader); +impl OVR6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR6` writer - Channel 6 Overrun"] +pub struct OVR6_W<'a> { + w: &'a mut W, +} +impl<'a> OVR6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `OVR7` reader - Channel 7 Overrun"] +pub struct OVR7_R(crate::FieldReader); +impl OVR7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR7` writer - Channel 7 Overrun"] +pub struct OVR7_W<'a> { + w: &'a mut W, +} +impl<'a> OVR7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `OVR8` reader - Channel 8 Overrun"] +pub struct OVR8_R(crate::FieldReader); +impl OVR8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR8` writer - Channel 8 Overrun"] +pub struct OVR8_W<'a> { + w: &'a mut W, +} +impl<'a> OVR8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `OVR9` reader - Channel 9 Overrun"] +pub struct OVR9_R(crate::FieldReader); +impl OVR9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR9` writer - Channel 9 Overrun"] +pub struct OVR9_W<'a> { + w: &'a mut W, +} +impl<'a> OVR9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `OVR10` reader - Channel 10 Overrun"] +pub struct OVR10_R(crate::FieldReader); +impl OVR10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR10` writer - Channel 10 Overrun"] +pub struct OVR10_W<'a> { + w: &'a mut W, +} +impl<'a> OVR10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `OVR11` reader - Channel 11 Overrun"] +pub struct OVR11_R(crate::FieldReader); +impl OVR11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR11` writer - Channel 11 Overrun"] +pub struct OVR11_W<'a> { + w: &'a mut W, +} +impl<'a> OVR11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `EVD0` reader - Channel 0 Event Detection"] +pub struct EVD0_R(crate::FieldReader); +impl EVD0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD0` writer - Channel 0 Event Detection"] +pub struct EVD0_W<'a> { + w: &'a mut W, +} +impl<'a> EVD0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `EVD1` reader - Channel 1 Event Detection"] +pub struct EVD1_R(crate::FieldReader); +impl EVD1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD1` writer - Channel 1 Event Detection"] +pub struct EVD1_W<'a> { + w: &'a mut W, +} +impl<'a> EVD1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `EVD2` reader - Channel 2 Event Detection"] +pub struct EVD2_R(crate::FieldReader); +impl EVD2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD2` writer - Channel 2 Event Detection"] +pub struct EVD2_W<'a> { + w: &'a mut W, +} +impl<'a> EVD2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `EVD3` reader - Channel 3 Event Detection"] +pub struct EVD3_R(crate::FieldReader); +impl EVD3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD3` writer - Channel 3 Event Detection"] +pub struct EVD3_W<'a> { + w: &'a mut W, +} +impl<'a> EVD3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `EVD4` reader - Channel 4 Event Detection"] +pub struct EVD4_R(crate::FieldReader); +impl EVD4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD4` writer - Channel 4 Event Detection"] +pub struct EVD4_W<'a> { + w: &'a mut W, +} +impl<'a> EVD4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `EVD5` reader - Channel 5 Event Detection"] +pub struct EVD5_R(crate::FieldReader); +impl EVD5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD5` writer - Channel 5 Event Detection"] +pub struct EVD5_W<'a> { + w: &'a mut W, +} +impl<'a> EVD5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `EVD6` reader - Channel 6 Event Detection"] +pub struct EVD6_R(crate::FieldReader); +impl EVD6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD6` writer - Channel 6 Event Detection"] +pub struct EVD6_W<'a> { + w: &'a mut W, +} +impl<'a> EVD6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `EVD7` reader - Channel 7 Event Detection"] +pub struct EVD7_R(crate::FieldReader); +impl EVD7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD7` writer - Channel 7 Event Detection"] +pub struct EVD7_W<'a> { + w: &'a mut W, +} +impl<'a> EVD7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `EVD8` reader - Channel 8 Event Detection"] +pub struct EVD8_R(crate::FieldReader); +impl EVD8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD8` writer - Channel 8 Event Detection"] +pub struct EVD8_W<'a> { + w: &'a mut W, +} +impl<'a> EVD8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `EVD9` reader - Channel 9 Event Detection"] +pub struct EVD9_R(crate::FieldReader); +impl EVD9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD9` writer - Channel 9 Event Detection"] +pub struct EVD9_W<'a> { + w: &'a mut W, +} +impl<'a> EVD9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `EVD10` reader - Channel 10 Event Detection"] +pub struct EVD10_R(crate::FieldReader); +impl EVD10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD10` writer - Channel 10 Event Detection"] +pub struct EVD10_W<'a> { + w: &'a mut W, +} +impl<'a> EVD10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `EVD11` reader - Channel 11 Event Detection"] +pub struct EVD11_R(crate::FieldReader); +impl EVD11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD11` writer - Channel 11 Event Detection"] +pub struct EVD11_W<'a> { + w: &'a mut W, +} +impl<'a> EVD11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +impl R { + #[doc = "Bit 0 - Channel 0 Overrun"] + #[inline(always)] + pub fn ovr0(&self) -> OVR0_R { + OVR0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel 1 Overrun"] + #[inline(always)] + pub fn ovr1(&self) -> OVR1_R { + OVR1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel 2 Overrun"] + #[inline(always)] + pub fn ovr2(&self) -> OVR2_R { + OVR2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Channel 3 Overrun"] + #[inline(always)] + pub fn ovr3(&self) -> OVR3_R { + OVR3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Channel 4 Overrun"] + #[inline(always)] + pub fn ovr4(&self) -> OVR4_R { + OVR4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Channel 5 Overrun"] + #[inline(always)] + pub fn ovr5(&self) -> OVR5_R { + OVR5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Channel 6 Overrun"] + #[inline(always)] + pub fn ovr6(&self) -> OVR6_R { + OVR6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Channel 7 Overrun"] + #[inline(always)] + pub fn ovr7(&self) -> OVR7_R { + OVR7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Channel 8 Overrun"] + #[inline(always)] + pub fn ovr8(&self) -> OVR8_R { + OVR8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Channel 9 Overrun"] + #[inline(always)] + pub fn ovr9(&self) -> OVR9_R { + OVR9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Channel 10 Overrun"] + #[inline(always)] + pub fn ovr10(&self) -> OVR10_R { + OVR10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Channel 11 Overrun"] + #[inline(always)] + pub fn ovr11(&self) -> OVR11_R { + OVR11_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 16 - Channel 0 Event Detection"] + #[inline(always)] + pub fn evd0(&self) -> EVD0_R { + EVD0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Channel 1 Event Detection"] + #[inline(always)] + pub fn evd1(&self) -> EVD1_R { + EVD1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Channel 2 Event Detection"] + #[inline(always)] + pub fn evd2(&self) -> EVD2_R { + EVD2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Channel 3 Event Detection"] + #[inline(always)] + pub fn evd3(&self) -> EVD3_R { + EVD3_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Channel 4 Event Detection"] + #[inline(always)] + pub fn evd4(&self) -> EVD4_R { + EVD4_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Channel 5 Event Detection"] + #[inline(always)] + pub fn evd5(&self) -> EVD5_R { + EVD5_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Channel 6 Event Detection"] + #[inline(always)] + pub fn evd6(&self) -> EVD6_R { + EVD6_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Channel 7 Event Detection"] + #[inline(always)] + pub fn evd7(&self) -> EVD7_R { + EVD7_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24 - Channel 8 Event Detection"] + #[inline(always)] + pub fn evd8(&self) -> EVD8_R { + EVD8_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Channel 9 Event Detection"] + #[inline(always)] + pub fn evd9(&self) -> EVD9_R { + EVD9_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Channel 10 Event Detection"] + #[inline(always)] + pub fn evd10(&self) -> EVD10_R { + EVD10_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Channel 11 Event Detection"] + #[inline(always)] + pub fn evd11(&self) -> EVD11_R { + EVD11_R::new(((self.bits >> 27) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel 0 Overrun"] + #[inline(always)] + pub fn ovr0(&mut self) -> OVR0_W { + OVR0_W { w: self } + } + #[doc = "Bit 1 - Channel 1 Overrun"] + #[inline(always)] + pub fn ovr1(&mut self) -> OVR1_W { + OVR1_W { w: self } + } + #[doc = "Bit 2 - Channel 2 Overrun"] + #[inline(always)] + pub fn ovr2(&mut self) -> OVR2_W { + OVR2_W { w: self } + } + #[doc = "Bit 3 - Channel 3 Overrun"] + #[inline(always)] + pub fn ovr3(&mut self) -> OVR3_W { + OVR3_W { w: self } + } + #[doc = "Bit 4 - Channel 4 Overrun"] + #[inline(always)] + pub fn ovr4(&mut self) -> OVR4_W { + OVR4_W { w: self } + } + #[doc = "Bit 5 - Channel 5 Overrun"] + #[inline(always)] + pub fn ovr5(&mut self) -> OVR5_W { + OVR5_W { w: self } + } + #[doc = "Bit 6 - Channel 6 Overrun"] + #[inline(always)] + pub fn ovr6(&mut self) -> OVR6_W { + OVR6_W { w: self } + } + #[doc = "Bit 7 - Channel 7 Overrun"] + #[inline(always)] + pub fn ovr7(&mut self) -> OVR7_W { + OVR7_W { w: self } + } + #[doc = "Bit 8 - Channel 8 Overrun"] + #[inline(always)] + pub fn ovr8(&mut self) -> OVR8_W { + OVR8_W { w: self } + } + #[doc = "Bit 9 - Channel 9 Overrun"] + #[inline(always)] + pub fn ovr9(&mut self) -> OVR9_W { + OVR9_W { w: self } + } + #[doc = "Bit 10 - Channel 10 Overrun"] + #[inline(always)] + pub fn ovr10(&mut self) -> OVR10_W { + OVR10_W { w: self } + } + #[doc = "Bit 11 - Channel 11 Overrun"] + #[inline(always)] + pub fn ovr11(&mut self) -> OVR11_W { + OVR11_W { w: self } + } + #[doc = "Bit 16 - Channel 0 Event Detection"] + #[inline(always)] + pub fn evd0(&mut self) -> EVD0_W { + EVD0_W { w: self } + } + #[doc = "Bit 17 - Channel 1 Event Detection"] + #[inline(always)] + pub fn evd1(&mut self) -> EVD1_W { + EVD1_W { w: self } + } + #[doc = "Bit 18 - Channel 2 Event Detection"] + #[inline(always)] + pub fn evd2(&mut self) -> EVD2_W { + EVD2_W { w: self } + } + #[doc = "Bit 19 - Channel 3 Event Detection"] + #[inline(always)] + pub fn evd3(&mut self) -> EVD3_W { + EVD3_W { w: self } + } + #[doc = "Bit 20 - Channel 4 Event Detection"] + #[inline(always)] + pub fn evd4(&mut self) -> EVD4_W { + EVD4_W { w: self } + } + #[doc = "Bit 21 - Channel 5 Event Detection"] + #[inline(always)] + pub fn evd5(&mut self) -> EVD5_W { + EVD5_W { w: self } + } + #[doc = "Bit 22 - Channel 6 Event Detection"] + #[inline(always)] + pub fn evd6(&mut self) -> EVD6_W { + EVD6_W { w: self } + } + #[doc = "Bit 23 - Channel 7 Event Detection"] + #[inline(always)] + pub fn evd7(&mut self) -> EVD7_W { + EVD7_W { w: self } + } + #[doc = "Bit 24 - Channel 8 Event Detection"] + #[inline(always)] + pub fn evd8(&mut self) -> EVD8_W { + EVD8_W { w: self } + } + #[doc = "Bit 25 - Channel 9 Event Detection"] + #[inline(always)] + pub fn evd9(&mut self) -> EVD9_W { + EVD9_W { w: self } + } + #[doc = "Bit 26 - Channel 10 Event Detection"] + #[inline(always)] + pub fn evd10(&mut self) -> EVD10_W { + EVD10_W { w: self } + } + #[doc = "Bit 27 - Channel 11 Event Detection"] + #[inline(always)] + pub fn evd11(&mut self) -> EVD11_W { + EVD11_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/evsys/swevt.rs b/pac/atsamc21g/src/evsys/swevt.rs new file mode 100644 index 000000000000..df58fe290de2 --- /dev/null +++ b/pac/atsamc21g/src/evsys/swevt.rs @@ -0,0 +1,369 @@ +#[doc = "Register `SWEVT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHANNEL0` writer - Channel 0 Software Selection"] +pub struct CHANNEL0_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `CHANNEL1` writer - Channel 1 Software Selection"] +pub struct CHANNEL1_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CHANNEL2` writer - Channel 2 Software Selection"] +pub struct CHANNEL2_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CHANNEL3` writer - Channel 3 Software Selection"] +pub struct CHANNEL3_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CHANNEL4` writer - Channel 4 Software Selection"] +pub struct CHANNEL4_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `CHANNEL5` writer - Channel 5 Software Selection"] +pub struct CHANNEL5_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `CHANNEL6` writer - Channel 6 Software Selection"] +pub struct CHANNEL6_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `CHANNEL7` writer - Channel 7 Software Selection"] +pub struct CHANNEL7_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CHANNEL8` writer - Channel 8 Software Selection"] +pub struct CHANNEL8_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `CHANNEL9` writer - Channel 9 Software Selection"] +pub struct CHANNEL9_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `CHANNEL10` writer - Channel 10 Software Selection"] +pub struct CHANNEL10_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `CHANNEL11` writer - Channel 11 Software Selection"] +pub struct CHANNEL11_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +impl W { + #[doc = "Bit 0 - Channel 0 Software Selection"] + #[inline(always)] + pub fn channel0(&mut self) -> CHANNEL0_W { + CHANNEL0_W { w: self } + } + #[doc = "Bit 1 - Channel 1 Software Selection"] + #[inline(always)] + pub fn channel1(&mut self) -> CHANNEL1_W { + CHANNEL1_W { w: self } + } + #[doc = "Bit 2 - Channel 2 Software Selection"] + #[inline(always)] + pub fn channel2(&mut self) -> CHANNEL2_W { + CHANNEL2_W { w: self } + } + #[doc = "Bit 3 - Channel 3 Software Selection"] + #[inline(always)] + pub fn channel3(&mut self) -> CHANNEL3_W { + CHANNEL3_W { w: self } + } + #[doc = "Bit 4 - Channel 4 Software Selection"] + #[inline(always)] + pub fn channel4(&mut self) -> CHANNEL4_W { + CHANNEL4_W { w: self } + } + #[doc = "Bit 5 - Channel 5 Software Selection"] + #[inline(always)] + pub fn channel5(&mut self) -> CHANNEL5_W { + CHANNEL5_W { w: self } + } + #[doc = "Bit 6 - Channel 6 Software Selection"] + #[inline(always)] + pub fn channel6(&mut self) -> CHANNEL6_W { + CHANNEL6_W { w: self } + } + #[doc = "Bit 7 - Channel 7 Software Selection"] + #[inline(always)] + pub fn channel7(&mut self) -> CHANNEL7_W { + CHANNEL7_W { w: self } + } + #[doc = "Bit 8 - Channel 8 Software Selection"] + #[inline(always)] + pub fn channel8(&mut self) -> CHANNEL8_W { + CHANNEL8_W { w: self } + } + #[doc = "Bit 9 - Channel 9 Software Selection"] + #[inline(always)] + pub fn channel9(&mut self) -> CHANNEL9_W { + CHANNEL9_W { w: self } + } + #[doc = "Bit 10 - Channel 10 Software Selection"] + #[inline(always)] + pub fn channel10(&mut self) -> CHANNEL10_W { + CHANNEL10_W { w: self } + } + #[doc = "Bit 11 - Channel 11 Software Selection"] + #[inline(always)] + pub fn channel11(&mut self) -> CHANNEL11_W { + CHANNEL11_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Software Event\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [swevt](index.html) module"] +pub struct SWEVT_SPEC; +impl crate::RegisterSpec for SWEVT_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [swevt::W](W) writer structure"] +impl crate::Writable for SWEVT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SWEVT to value 0"] +impl crate::Resettable for SWEVT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/evsys/user.rs b/pac/atsamc21g/src/evsys/user.rs new file mode 100644 index 000000000000..848f9f599b79 --- /dev/null +++ b/pac/atsamc21g/src/evsys/user.rs @@ -0,0 +1,104 @@ +#[doc = "Register `USER[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `USER[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHANNEL` reader - Channel Event Selection"] +pub struct CHANNEL_R(crate::FieldReader); +impl CHANNEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CHANNEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHANNEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHANNEL` writer - Channel Event Selection"] +pub struct CHANNEL_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Channel Event Selection"] + #[inline(always)] + pub fn channel(&self) -> CHANNEL_R { + CHANNEL_R::new((self.bits & 0x1f) as u8) + } +} +impl W { + #[doc = "Bits 0:4 - Channel Event Selection"] + #[inline(always)] + pub fn channel(&mut self) -> CHANNEL_W { + CHANNEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "User Multiplexer n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [user](index.html) module"] +pub struct USER_SPEC; +impl crate::RegisterSpec for USER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [user::R](R) reader structure"] +impl crate::Readable for USER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [user::W](W) writer structure"] +impl crate::Writable for USER_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets USER[%s] +to value 0"] +impl crate::Resettable for USER_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/freqm.rs b/pac/atsamc21g/src/freqm.rs new file mode 100644 index 000000000000..f0fc6fda975e --- /dev/null +++ b/pac/atsamc21g/src/freqm.rs @@ -0,0 +1,59 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control A Register"] + pub ctrla: crate::Reg, + #[doc = "0x01 - Control B Register"] + pub ctrlb: crate::Reg, + #[doc = "0x02 - Config A register"] + pub cfga: crate::Reg, + _reserved3: [u8; 0x04], + #[doc = "0x08 - Interrupt Enable Clear Register"] + pub intenclr: crate::Reg, + #[doc = "0x09 - Interrupt Enable Set Register"] + pub intenset: crate::Reg, + #[doc = "0x0a - Interrupt Flag Register"] + pub intflag: crate::Reg, + #[doc = "0x0b - Status Register"] + pub status: crate::Reg, + #[doc = "0x0c - Synchronization Busy Register"] + pub syncbusy: crate::Reg, + #[doc = "0x10 - Count Value Register"] + pub value: crate::Reg, +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A Register"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "Control B Register"] +pub mod ctrlb; +#[doc = "CFGA register accessor: an alias for `Reg`"] +pub type CFGA = crate::Reg; +#[doc = "Config A register"] +pub mod cfga; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear Register"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set Register"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Register"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status Register"] +pub mod status; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Busy Register"] +pub mod syncbusy; +#[doc = "VALUE register accessor: an alias for `Reg`"] +pub type VALUE = crate::Reg; +#[doc = "Count Value Register"] +pub mod value; diff --git a/pac/atsamc21g/src/freqm/cfga.rs b/pac/atsamc21g/src/freqm/cfga.rs new file mode 100644 index 000000000000..573c62964185 --- /dev/null +++ b/pac/atsamc21g/src/freqm/cfga.rs @@ -0,0 +1,103 @@ +#[doc = "Register `CFGA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CFGA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `REFNUM` reader - Number of Reference Clock Cycles"] +pub struct REFNUM_R(crate::FieldReader); +impl REFNUM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REFNUM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REFNUM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REFNUM` writer - Number of Reference Clock Cycles"] +pub struct REFNUM_W<'a> { + w: &'a mut W, +} +impl<'a> REFNUM_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u16 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Number of Reference Clock Cycles"] + #[inline(always)] + pub fn refnum(&self) -> REFNUM_R { + REFNUM_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Number of Reference Clock Cycles"] + #[inline(always)] + pub fn refnum(&mut self) -> REFNUM_W { + REFNUM_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Config A register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cfga](index.html) module"] +pub struct CFGA_SPEC; +impl crate::RegisterSpec for CFGA_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [cfga::R](R) reader structure"] +impl crate::Readable for CFGA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cfga::W](W) writer structure"] +impl crate::Writable for CFGA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CFGA to value 0"] +impl crate::Resettable for CFGA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/freqm/ctrla.rs b/pac/atsamc21g/src/freqm/ctrla.rs new file mode 100644 index 000000000000..b2cefdd45770 --- /dev/null +++ b/pac/atsamc21g/src/freqm/ctrla.rs @@ -0,0 +1,160 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/freqm/ctrlb.rs b/pac/atsamc21g/src/freqm/ctrlb.rs new file mode 100644 index 000000000000..7d350e71fbf3 --- /dev/null +++ b/pac/atsamc21g/src/freqm/ctrlb.rs @@ -0,0 +1,72 @@ +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `START` writer - Start Measurement"] +pub struct START_W<'a> { + w: &'a mut W, +} +impl<'a> START_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0 - Start Measurement"] + #[inline(always)] + pub fn start(&mut self) -> START_W { + START_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u8; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/freqm/intenclr.rs b/pac/atsamc21g/src/freqm/intenclr.rs new file mode 100644 index 000000000000..a224aa5500f6 --- /dev/null +++ b/pac/atsamc21g/src/freqm/intenclr.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DONE` reader - Measurement Done Interrupt Enable"] +pub struct DONE_R(crate::FieldReader); +impl DONE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DONE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DONE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DONE` writer - Measurement Done Interrupt Enable"] +pub struct DONE_W<'a> { + w: &'a mut W, +} +impl<'a> DONE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Measurement Done Interrupt Enable"] + #[inline(always)] + pub fn done(&self) -> DONE_R { + DONE_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Measurement Done Interrupt Enable"] + #[inline(always)] + pub fn done(&mut self) -> DONE_W { + DONE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/freqm/intenset.rs b/pac/atsamc21g/src/freqm/intenset.rs new file mode 100644 index 000000000000..53b3d0bef7c0 --- /dev/null +++ b/pac/atsamc21g/src/freqm/intenset.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DONE` reader - Measurement Done Interrupt Enable"] +pub struct DONE_R(crate::FieldReader); +impl DONE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DONE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DONE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DONE` writer - Measurement Done Interrupt Enable"] +pub struct DONE_W<'a> { + w: &'a mut W, +} +impl<'a> DONE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Measurement Done Interrupt Enable"] + #[inline(always)] + pub fn done(&self) -> DONE_R { + DONE_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Measurement Done Interrupt Enable"] + #[inline(always)] + pub fn done(&mut self) -> DONE_W { + DONE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/freqm/intflag.rs b/pac/atsamc21g/src/freqm/intflag.rs new file mode 100644 index 000000000000..3b8fdab47703 --- /dev/null +++ b/pac/atsamc21g/src/freqm/intflag.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DONE` reader - Measurement Done"] +pub struct DONE_R(crate::FieldReader); +impl DONE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DONE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DONE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DONE` writer - Measurement Done"] +pub struct DONE_W<'a> { + w: &'a mut W, +} +impl<'a> DONE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Measurement Done"] + #[inline(always)] + pub fn done(&self) -> DONE_R { + DONE_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Measurement Done"] + #[inline(always)] + pub fn done(&mut self) -> DONE_W { + DONE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/freqm/status.rs b/pac/atsamc21g/src/freqm/status.rs new file mode 100644 index 000000000000..8a81662f51b0 --- /dev/null +++ b/pac/atsamc21g/src/freqm/status.rs @@ -0,0 +1,160 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BUSY` reader - FREQM Status"] +pub struct BUSY_R(crate::FieldReader); +impl BUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSY` writer - FREQM Status"] +pub struct BUSY_W<'a> { + w: &'a mut W, +} +impl<'a> BUSY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `OVF` reader - Sticky Count Value Overflow"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Sticky Count Value Overflow"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - FREQM Status"] + #[inline(always)] + pub fn busy(&self) -> BUSY_R { + BUSY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Sticky Count Value Overflow"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - FREQM Status"] + #[inline(always)] + pub fn busy(&mut self) -> BUSY_W { + BUSY_W { w: self } + } + #[doc = "Bit 1 - Sticky Count Value Overflow"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/freqm/syncbusy.rs b/pac/atsamc21g/src/freqm/syncbusy.rs new file mode 100644 index 000000000000..54396368e817 --- /dev/null +++ b/pac/atsamc21g/src/freqm/syncbusy.rs @@ -0,0 +1,73 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +#[doc = "Synchronization Busy Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/freqm/value.rs b/pac/atsamc21g/src/freqm/value.rs new file mode 100644 index 000000000000..5b0f5dfd9b67 --- /dev/null +++ b/pac/atsamc21g/src/freqm/value.rs @@ -0,0 +1,53 @@ +#[doc = "Register `VALUE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `VALUE` reader - Measurement Value"] +pub struct VALUE_R(crate::FieldReader); +impl VALUE_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + VALUE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VALUE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:23 - Measurement Value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +#[doc = "Count Value Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [value](index.html) module"] +pub struct VALUE_SPEC; +impl crate::RegisterSpec for VALUE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [value::R](R) reader structure"] +impl crate::Readable for VALUE_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets VALUE to value 0"] +impl crate::Resettable for VALUE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/gclk.rs b/pac/atsamc21g/src/gclk.rs new file mode 100644 index 000000000000..2a37bdedcab3 --- /dev/null +++ b/pac/atsamc21g/src/gclk.rs @@ -0,0 +1,31 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrla: crate::Reg, + _reserved1: [u8; 0x03], + #[doc = "0x04 - Synchronization Busy"] + pub syncbusy: crate::Reg, + _reserved2: [u8; 0x18], + #[doc = "0x20..0x44 - Generic Clock Generator Control"] + pub genctrl: [crate::Reg; 9], + _reserved3: [u8; 0x3c], + #[doc = "0x80..0x124 - Peripheral Clock Control"] + pub pchctrl: [crate::Reg; 41], +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control"] +pub mod ctrla; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Busy"] +pub mod syncbusy; +#[doc = "GENCTRL register accessor: an alias for `Reg`"] +pub type GENCTRL = crate::Reg; +#[doc = "Generic Clock Generator Control"] +pub mod genctrl; +#[doc = "PCHCTRL register accessor: an alias for `Reg`"] +pub type PCHCTRL = crate::Reg; +#[doc = "Peripheral Clock Control"] +pub mod pchctrl; diff --git a/pac/atsamc21g/src/gclk/ctrla.rs b/pac/atsamc21g/src/gclk/ctrla.rs new file mode 100644 index 000000000000..1c24704395ad --- /dev/null +++ b/pac/atsamc21g/src/gclk/ctrla.rs @@ -0,0 +1,113 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/gclk/genctrl.rs b/pac/atsamc21g/src/gclk/genctrl.rs new file mode 100644 index 000000000000..052b2915ca7f --- /dev/null +++ b/pac/atsamc21g/src/gclk/genctrl.rs @@ -0,0 +1,597 @@ +#[doc = "Register `GENCTRL[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GENCTRL[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Source Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SRC_A { + #[doc = "0: XOSC oscillator output"] + XOSC = 0, + #[doc = "1: Generator input pad"] + GCLKIN = 1, + #[doc = "2: Generic clock generator 1 output"] + GCLKGEN1 = 2, + #[doc = "3: OSCULP32K oscillator output"] + OSCULP32K = 3, + #[doc = "4: OSC32K oscillator output"] + OSC32K = 4, + #[doc = "5: XOSC32K oscillator output"] + XOSC32K = 5, + #[doc = "6: OSC48M oscillator output"] + OSC48M = 6, + #[doc = "7: DPLL96M output"] + DPLL96M = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SRC_A) -> Self { + variant as _ + } +} +#[doc = "Field `SRC` reader - Source Select"] +pub struct SRC_R(crate::FieldReader); +impl SRC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SRC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SRC_A { + match self.bits { + 0 => SRC_A::XOSC, + 1 => SRC_A::GCLKIN, + 2 => SRC_A::GCLKGEN1, + 3 => SRC_A::OSCULP32K, + 4 => SRC_A::OSC32K, + 5 => SRC_A::XOSC32K, + 6 => SRC_A::OSC48M, + 7 => SRC_A::DPLL96M, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `XOSC`"] + #[inline(always)] + pub fn is_xosc(&self) -> bool { + **self == SRC_A::XOSC + } + #[doc = "Checks if the value of the field is `GCLKIN`"] + #[inline(always)] + pub fn is_gclkin(&self) -> bool { + **self == SRC_A::GCLKIN + } + #[doc = "Checks if the value of the field is `GCLKGEN1`"] + #[inline(always)] + pub fn is_gclkgen1(&self) -> bool { + **self == SRC_A::GCLKGEN1 + } + #[doc = "Checks if the value of the field is `OSCULP32K`"] + #[inline(always)] + pub fn is_osculp32k(&self) -> bool { + **self == SRC_A::OSCULP32K + } + #[doc = "Checks if the value of the field is `OSC32K`"] + #[inline(always)] + pub fn is_osc32k(&self) -> bool { + **self == SRC_A::OSC32K + } + #[doc = "Checks if the value of the field is `XOSC32K`"] + #[inline(always)] + pub fn is_xosc32k(&self) -> bool { + **self == SRC_A::XOSC32K + } + #[doc = "Checks if the value of the field is `OSC48M`"] + #[inline(always)] + pub fn is_osc48m(&self) -> bool { + **self == SRC_A::OSC48M + } + #[doc = "Checks if the value of the field is `DPLL96M`"] + #[inline(always)] + pub fn is_dpll96m(&self) -> bool { + **self == SRC_A::DPLL96M + } +} +impl core::ops::Deref for SRC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SRC` writer - Source Select"] +pub struct SRC_W<'a> { + w: &'a mut W, +} +impl<'a> SRC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SRC_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "XOSC oscillator output"] + #[inline(always)] + pub fn xosc(self) -> &'a mut W { + self.variant(SRC_A::XOSC) + } + #[doc = "Generator input pad"] + #[inline(always)] + pub fn gclkin(self) -> &'a mut W { + self.variant(SRC_A::GCLKIN) + } + #[doc = "Generic clock generator 1 output"] + #[inline(always)] + pub fn gclkgen1(self) -> &'a mut W { + self.variant(SRC_A::GCLKGEN1) + } + #[doc = "OSCULP32K oscillator output"] + #[inline(always)] + pub fn osculp32k(self) -> &'a mut W { + self.variant(SRC_A::OSCULP32K) + } + #[doc = "OSC32K oscillator output"] + #[inline(always)] + pub fn osc32k(self) -> &'a mut W { + self.variant(SRC_A::OSC32K) + } + #[doc = "XOSC32K oscillator output"] + #[inline(always)] + pub fn xosc32k(self) -> &'a mut W { + self.variant(SRC_A::XOSC32K) + } + #[doc = "OSC48M oscillator output"] + #[inline(always)] + pub fn osc48m(self) -> &'a mut W { + self.variant(SRC_A::OSC48M) + } + #[doc = "DPLL96M output"] + #[inline(always)] + pub fn dpll96m(self) -> &'a mut W { + self.variant(SRC_A::DPLL96M) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Field `GENEN` reader - Generic Clock Generator Enable"] +pub struct GENEN_R(crate::FieldReader); +impl GENEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENEN` writer - Generic Clock Generator Enable"] +pub struct GENEN_W<'a> { + w: &'a mut W, +} +impl<'a> GENEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `IDC` reader - Improve Duty Cycle"] +pub struct IDC_R(crate::FieldReader); +impl IDC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IDC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IDC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IDC` writer - Improve Duty Cycle"] +pub struct IDC_W<'a> { + w: &'a mut W, +} +impl<'a> IDC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `OOV` reader - Output Off Value"] +pub struct OOV_R(crate::FieldReader); +impl OOV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OOV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OOV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OOV` writer - Output Off Value"] +pub struct OOV_W<'a> { + w: &'a mut W, +} +impl<'a> OOV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `OE` reader - Output Enable"] +pub struct OE_R(crate::FieldReader); +impl OE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OE` writer - Output Enable"] +pub struct OE_W<'a> { + w: &'a mut W, +} +impl<'a> OE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Divide Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum DIVSEL_A { + #[doc = "0: Divide input directly by divider factor"] + DIV1 = 0, + #[doc = "1: Divide input by 2^(divider factor+ 1)"] + DIV2 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DIVSEL_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DIVSEL` reader - Divide Selection"] +pub struct DIVSEL_R(crate::FieldReader); +impl DIVSEL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIVSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DIVSEL_A { + match self.bits { + false => DIVSEL_A::DIV1, + true => DIVSEL_A::DIV2, + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == DIVSEL_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == DIVSEL_A::DIV2 + } +} +impl core::ops::Deref for DIVSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIVSEL` writer - Divide Selection"] +pub struct DIVSEL_W<'a> { + w: &'a mut W, +} +impl<'a> DIVSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DIVSEL_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Divide input directly by divider factor"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(DIVSEL_A::DIV1) + } + #[doc = "Divide input by 2^(divider factor+ 1)"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(DIVSEL_A::DIV2) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `DIV` reader - Division Factor"] +pub struct DIV_R(crate::FieldReader); +impl DIV_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + DIV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIV` writer - Division Factor"] +pub struct DIV_W<'a> { + w: &'a mut W, +} +impl<'a> DIV_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xffff << 16)) | ((value as u32 & 0xffff) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Source Select"] + #[inline(always)] + pub fn src(&self) -> SRC_R { + SRC_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 8 - Generic Clock Generator Enable"] + #[inline(always)] + pub fn genen(&self) -> GENEN_R { + GENEN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Improve Duty Cycle"] + #[inline(always)] + pub fn idc(&self) -> IDC_R { + IDC_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Output Off Value"] + #[inline(always)] + pub fn oov(&self) -> OOV_R { + OOV_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Output Enable"] + #[inline(always)] + pub fn oe(&self) -> OE_R { + OE_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Divide Selection"] + #[inline(always)] + pub fn divsel(&self) -> DIVSEL_R { + DIVSEL_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bits 16:31 - Division Factor"] + #[inline(always)] + pub fn div(&self) -> DIV_R { + DIV_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:2 - Source Select"] + #[inline(always)] + pub fn src(&mut self) -> SRC_W { + SRC_W { w: self } + } + #[doc = "Bit 8 - Generic Clock Generator Enable"] + #[inline(always)] + pub fn genen(&mut self) -> GENEN_W { + GENEN_W { w: self } + } + #[doc = "Bit 9 - Improve Duty Cycle"] + #[inline(always)] + pub fn idc(&mut self) -> IDC_W { + IDC_W { w: self } + } + #[doc = "Bit 10 - Output Off Value"] + #[inline(always)] + pub fn oov(&mut self) -> OOV_W { + OOV_W { w: self } + } + #[doc = "Bit 11 - Output Enable"] + #[inline(always)] + pub fn oe(&mut self) -> OE_W { + OE_W { w: self } + } + #[doc = "Bit 12 - Divide Selection"] + #[inline(always)] + pub fn divsel(&mut self) -> DIVSEL_W { + DIVSEL_W { w: self } + } + #[doc = "Bit 13 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bits 16:31 - Division Factor"] + #[inline(always)] + pub fn div(&mut self) -> DIV_W { + DIV_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Generic Clock Generator Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [genctrl](index.html) module"] +pub struct GENCTRL_SPEC; +impl crate::RegisterSpec for GENCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [genctrl::R](R) reader structure"] +impl crate::Readable for GENCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [genctrl::W](W) writer structure"] +impl crate::Writable for GENCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets GENCTRL[%s] +to value 0"] +impl crate::Resettable for GENCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/gclk/pchctrl.rs b/pac/atsamc21g/src/gclk/pchctrl.rs new file mode 100644 index 000000000000..8001ffeaa1ee --- /dev/null +++ b/pac/atsamc21g/src/gclk/pchctrl.rs @@ -0,0 +1,338 @@ +#[doc = "Register `PCHCTRL[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PCHCTRL[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Generic Clock Generator\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum GEN_A { + #[doc = "0: Generic clock generator 0"] + GCLK0 = 0, + #[doc = "1: Generic clock generator 1"] + GCLK1 = 1, + #[doc = "2: Generic clock generator 2"] + GCLK2 = 2, + #[doc = "3: Generic clock generator 3"] + GCLK3 = 3, + #[doc = "4: Generic clock generator 4"] + GCLK4 = 4, + #[doc = "5: Generic clock generator 5"] + GCLK5 = 5, + #[doc = "6: Generic clock generator 6"] + GCLK6 = 6, + #[doc = "7: Generic clock generator 7"] + GCLK7 = 7, + #[doc = "8: Generic clock generator 8"] + GCLK8 = 8, +} +impl From for u8 { + #[inline(always)] + fn from(variant: GEN_A) -> Self { + variant as _ + } +} +#[doc = "Field `GEN` reader - Generic Clock Generator"] +pub struct GEN_R(crate::FieldReader); +impl GEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + GEN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(GEN_A::GCLK0), + 1 => Some(GEN_A::GCLK1), + 2 => Some(GEN_A::GCLK2), + 3 => Some(GEN_A::GCLK3), + 4 => Some(GEN_A::GCLK4), + 5 => Some(GEN_A::GCLK5), + 6 => Some(GEN_A::GCLK6), + 7 => Some(GEN_A::GCLK7), + 8 => Some(GEN_A::GCLK8), + _ => None, + } + } + #[doc = "Checks if the value of the field is `GCLK0`"] + #[inline(always)] + pub fn is_gclk0(&self) -> bool { + **self == GEN_A::GCLK0 + } + #[doc = "Checks if the value of the field is `GCLK1`"] + #[inline(always)] + pub fn is_gclk1(&self) -> bool { + **self == GEN_A::GCLK1 + } + #[doc = "Checks if the value of the field is `GCLK2`"] + #[inline(always)] + pub fn is_gclk2(&self) -> bool { + **self == GEN_A::GCLK2 + } + #[doc = "Checks if the value of the field is `GCLK3`"] + #[inline(always)] + pub fn is_gclk3(&self) -> bool { + **self == GEN_A::GCLK3 + } + #[doc = "Checks if the value of the field is `GCLK4`"] + #[inline(always)] + pub fn is_gclk4(&self) -> bool { + **self == GEN_A::GCLK4 + } + #[doc = "Checks if the value of the field is `GCLK5`"] + #[inline(always)] + pub fn is_gclk5(&self) -> bool { + **self == GEN_A::GCLK5 + } + #[doc = "Checks if the value of the field is `GCLK6`"] + #[inline(always)] + pub fn is_gclk6(&self) -> bool { + **self == GEN_A::GCLK6 + } + #[doc = "Checks if the value of the field is `GCLK7`"] + #[inline(always)] + pub fn is_gclk7(&self) -> bool { + **self == GEN_A::GCLK7 + } + #[doc = "Checks if the value of the field is `GCLK8`"] + #[inline(always)] + pub fn is_gclk8(&self) -> bool { + **self == GEN_A::GCLK8 + } +} +impl core::ops::Deref for GEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GEN` writer - Generic Clock Generator"] +pub struct GEN_W<'a> { + w: &'a mut W, +} +impl<'a> GEN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: GEN_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Generic clock generator 0"] + #[inline(always)] + pub fn gclk0(self) -> &'a mut W { + self.variant(GEN_A::GCLK0) + } + #[doc = "Generic clock generator 1"] + #[inline(always)] + pub fn gclk1(self) -> &'a mut W { + self.variant(GEN_A::GCLK1) + } + #[doc = "Generic clock generator 2"] + #[inline(always)] + pub fn gclk2(self) -> &'a mut W { + self.variant(GEN_A::GCLK2) + } + #[doc = "Generic clock generator 3"] + #[inline(always)] + pub fn gclk3(self) -> &'a mut W { + self.variant(GEN_A::GCLK3) + } + #[doc = "Generic clock generator 4"] + #[inline(always)] + pub fn gclk4(self) -> &'a mut W { + self.variant(GEN_A::GCLK4) + } + #[doc = "Generic clock generator 5"] + #[inline(always)] + pub fn gclk5(self) -> &'a mut W { + self.variant(GEN_A::GCLK5) + } + #[doc = "Generic clock generator 6"] + #[inline(always)] + pub fn gclk6(self) -> &'a mut W { + self.variant(GEN_A::GCLK6) + } + #[doc = "Generic clock generator 7"] + #[inline(always)] + pub fn gclk7(self) -> &'a mut W { + self.variant(GEN_A::GCLK7) + } + #[doc = "Generic clock generator 8"] + #[inline(always)] + pub fn gclk8(self) -> &'a mut W { + self.variant(GEN_A::GCLK8) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Field `CHEN` reader - Channel Enable"] +pub struct CHEN_R(crate::FieldReader); +impl CHEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHEN` writer - Channel Enable"] +pub struct CHEN_W<'a> { + w: &'a mut W, +} +impl<'a> CHEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `WRTLOCK` reader - Write Lock"] +pub struct WRTLOCK_R(crate::FieldReader); +impl WRTLOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WRTLOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WRTLOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WRTLOCK` writer - Write Lock"] +pub struct WRTLOCK_W<'a> { + w: &'a mut W, +} +impl<'a> WRTLOCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Generic Clock Generator"] + #[inline(always)] + pub fn gen(&self) -> GEN_R { + GEN_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 6 - Channel Enable"] + #[inline(always)] + pub fn chen(&self) -> CHEN_R { + CHEN_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&self) -> WRTLOCK_R { + WRTLOCK_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Generic Clock Generator"] + #[inline(always)] + pub fn gen(&mut self) -> GEN_W { + GEN_W { w: self } + } + #[doc = "Bit 6 - Channel Enable"] + #[inline(always)] + pub fn chen(&mut self) -> CHEN_W { + CHEN_W { w: self } + } + #[doc = "Bit 7 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&mut self) -> WRTLOCK_W { + WRTLOCK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Peripheral Clock Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pchctrl](index.html) module"] +pub struct PCHCTRL_SPEC; +impl crate::RegisterSpec for PCHCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pchctrl::R](R) reader structure"] +impl crate::Readable for PCHCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [pchctrl::W](W) writer structure"] +impl crate::Writable for PCHCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PCHCTRL[%s] +to value 0"] +impl crate::Resettable for PCHCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/gclk/syncbusy.rs b/pac/atsamc21g/src/gclk/syncbusy.rs new file mode 100644 index 000000000000..f21640440354 --- /dev/null +++ b/pac/atsamc21g/src/gclk/syncbusy.rs @@ -0,0 +1,233 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchroniation Busy bit"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENCTRL0` reader - Generic Clock Generator Control 0 Synchronization Busy bits"] +pub struct GENCTRL0_R(crate::FieldReader); +impl GENCTRL0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENCTRL0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENCTRL0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENCTRL1` reader - Generic Clock Generator Control 1 Synchronization Busy bits"] +pub struct GENCTRL1_R(crate::FieldReader); +impl GENCTRL1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENCTRL1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENCTRL1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENCTRL2` reader - Generic Clock Generator Control 2 Synchronization Busy bits"] +pub struct GENCTRL2_R(crate::FieldReader); +impl GENCTRL2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENCTRL2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENCTRL2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENCTRL3` reader - Generic Clock Generator Control 3 Synchronization Busy bits"] +pub struct GENCTRL3_R(crate::FieldReader); +impl GENCTRL3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENCTRL3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENCTRL3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENCTRL4` reader - Generic Clock Generator Control 4 Synchronization Busy bits"] +pub struct GENCTRL4_R(crate::FieldReader); +impl GENCTRL4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENCTRL4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENCTRL4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENCTRL5` reader - Generic Clock Generator Control 5 Synchronization Busy bits"] +pub struct GENCTRL5_R(crate::FieldReader); +impl GENCTRL5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENCTRL5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENCTRL5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENCTRL6` reader - Generic Clock Generator Control 6 Synchronization Busy bits"] +pub struct GENCTRL6_R(crate::FieldReader); +impl GENCTRL6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENCTRL6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENCTRL6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENCTRL7` reader - Generic Clock Generator Control 7 Synchronization Busy bits"] +pub struct GENCTRL7_R(crate::FieldReader); +impl GENCTRL7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENCTRL7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENCTRL7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENCTRL8` reader - Generic Clock Generator Control 8 Synchronization Busy bits"] +pub struct GENCTRL8_R(crate::FieldReader); +impl GENCTRL8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENCTRL8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENCTRL8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchroniation Busy bit"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 2 - Generic Clock Generator Control 0 Synchronization Busy bits"] + #[inline(always)] + pub fn genctrl0(&self) -> GENCTRL0_R { + GENCTRL0_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Generic Clock Generator Control 1 Synchronization Busy bits"] + #[inline(always)] + pub fn genctrl1(&self) -> GENCTRL1_R { + GENCTRL1_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Generic Clock Generator Control 2 Synchronization Busy bits"] + #[inline(always)] + pub fn genctrl2(&self) -> GENCTRL2_R { + GENCTRL2_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Generic Clock Generator Control 3 Synchronization Busy bits"] + #[inline(always)] + pub fn genctrl3(&self) -> GENCTRL3_R { + GENCTRL3_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Generic Clock Generator Control 4 Synchronization Busy bits"] + #[inline(always)] + pub fn genctrl4(&self) -> GENCTRL4_R { + GENCTRL4_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Generic Clock Generator Control 5 Synchronization Busy bits"] + #[inline(always)] + pub fn genctrl5(&self) -> GENCTRL5_R { + GENCTRL5_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Generic Clock Generator Control 6 Synchronization Busy bits"] + #[inline(always)] + pub fn genctrl6(&self) -> GENCTRL6_R { + GENCTRL6_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Generic Clock Generator Control 7 Synchronization Busy bits"] + #[inline(always)] + pub fn genctrl7(&self) -> GENCTRL7_R { + GENCTRL7_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Generic Clock Generator Control 8 Synchronization Busy bits"] + #[inline(always)] + pub fn genctrl8(&self) -> GENCTRL8_R { + GENCTRL8_R::new(((self.bits >> 10) & 0x01) != 0) + } +} +#[doc = "Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/generic.rs b/pac/atsamc21g/src/generic.rs new file mode 100644 index 000000000000..76159643acfa --- /dev/null +++ b/pac/atsamc21g/src/generic.rs @@ -0,0 +1,260 @@ +use core::marker; +#[doc = " Raw register type"] +pub trait RegisterSpec { + #[doc = " Raw register type (`u8`, `u16`, `u32`, ...)."] + type Ux: Copy; +} +#[doc = " Trait implemented by readable registers to enable the `read` method."] +#[doc = ""] +#[doc = " Registers marked with `Writable` can be also `modify`'ed."] +pub trait Readable: RegisterSpec { + #[doc = " Result from a call to `read` and argument to `modify`."] + type Reader: From> + core::ops::Deref>; +} +#[doc = " Trait implemented by writeable registers."] +#[doc = ""] +#[doc = " This enables the `write`, `write_with_zero` and `reset` methods."] +#[doc = ""] +#[doc = " Registers marked with `Readable` can be also `modify`'ed."] +pub trait Writable: RegisterSpec { + #[doc = " Writer type argument to `write`, et al."] + type Writer: From> + core::ops::DerefMut>; +} +#[doc = " Reset value of the register."] +#[doc = ""] +#[doc = " This value is the initial value for the `write` method. It can also be directly written to the"] +#[doc = " register by using the `reset` method."] +pub trait Resettable: RegisterSpec { + #[doc = " Reset value of the register."] + fn reset_value() -> Self::Ux; +} +#[doc = " This structure provides volatile access to registers."] +#[repr(transparent)] +pub struct Reg { + register: vcell::VolatileCell, + _marker: marker::PhantomData, +} +unsafe impl Send for Reg where REG::Ux: Send {} +impl Reg { + #[doc = " Returns the underlying memory address of register."] + #[doc = ""] + #[doc = " ```ignore"] + #[doc = " let reg_ptr = periph.reg.as_ptr();"] + #[doc = " ```"] + #[inline(always)] + pub fn as_ptr(&self) -> *mut REG::Ux { + self.register.as_ptr() + } +} +impl Reg { + #[doc = " Reads the contents of a `Readable` register."] + #[doc = ""] + #[doc = " You can read the raw contents of a register by using `bits`:"] + #[doc = " ```ignore"] + #[doc = " let bits = periph.reg.read().bits();"] + #[doc = " ```"] + #[doc = " or get the content of a particular field of a register:"] + #[doc = " ```ignore"] + #[doc = " let reader = periph.reg.read();"] + #[doc = " let bits = reader.field1().bits();"] + #[doc = " let flag = reader.field2().bit_is_set();"] + #[doc = " ```"] + #[inline(always)] + pub fn read(&self) -> REG::Reader { + REG::Reader::from(R { + bits: self.register.get(), + _reg: marker::PhantomData, + }) + } +} +impl Reg { + #[doc = " Writes the reset value to `Writable` register."] + #[doc = ""] + #[doc = " Resets the register to its initial state."] + #[inline(always)] + pub fn reset(&self) { + self.register.set(REG::reset_value()) + } + #[doc = " Writes bits to a `Writable` register."] + #[doc = ""] + #[doc = " You can write raw bits into a register:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.write(|w| unsafe { w.bits(rawbits) });"] + #[doc = " ```"] + #[doc = " or write only the fields you need:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.write(|w| w"] + #[doc = " .field1().bits(newfield1bits)"] + #[doc = " .field2().set_bit()"] + #[doc = " .field3().variant(VARIANT)"] + #[doc = " );"] + #[doc = " ```"] + #[doc = " In the latter case, other fields will be set to their reset value."] + #[inline(always)] + pub fn write(&self, f: F) + where + F: FnOnce(&mut REG::Writer) -> &mut W, + { + self.register.set( + f(&mut REG::Writer::from(W { + bits: REG::reset_value(), + _reg: marker::PhantomData, + })) + .bits, + ); + } +} +impl Reg +where + REG::Ux: Default, +{ + #[doc = " Writes 0 to a `Writable` register."] + #[doc = ""] + #[doc = " Similar to `write`, but unused bits will contain 0."] + #[inline(always)] + pub unsafe fn write_with_zero(&self, f: F) + where + F: FnOnce(&mut REG::Writer) -> &mut W, + { + self.register.set( + (*f(&mut REG::Writer::from(W { + bits: REG::Ux::default(), + _reg: marker::PhantomData, + }))) + .bits, + ); + } +} +impl Reg { + #[doc = " Modifies the contents of the register by reading and then writing it."] + #[doc = ""] + #[doc = " E.g. to do a read-modify-write sequence to change parts of a register:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.modify(|r, w| unsafe { w.bits("] + #[doc = " r.bits() | 3"] + #[doc = " ) });"] + #[doc = " ```"] + #[doc = " or"] + #[doc = " ```ignore"] + #[doc = " periph.reg.modify(|_, w| w"] + #[doc = " .field1().bits(newfield1bits)"] + #[doc = " .field2().set_bit()"] + #[doc = " .field3().variant(VARIANT)"] + #[doc = " );"] + #[doc = " ```"] + #[doc = " Other fields will have the value they had before the call to `modify`."] + #[inline(always)] + pub fn modify(&self, f: F) + where + for<'w> F: FnOnce(®::Reader, &'w mut REG::Writer) -> &'w mut W, + { + let bits = self.register.get(); + self.register.set( + f( + ®::Reader::from(R { + bits, + _reg: marker::PhantomData, + }), + &mut REG::Writer::from(W { + bits, + _reg: marker::PhantomData, + }), + ) + .bits, + ); + } +} +#[doc = " Register reader."] +#[doc = ""] +#[doc = " Result of the `read` methods of registers. Also used as a closure argument in the `modify`"] +#[doc = " method."] +pub struct R { + pub(crate) bits: REG::Ux, + _reg: marker::PhantomData, +} +impl R { + #[doc = " Reads raw bits from register."] + #[inline(always)] + pub fn bits(&self) -> REG::Ux { + self.bits + } +} +impl PartialEq for R +where + REG::Ux: PartialEq, + FI: Copy + Into, +{ + #[inline(always)] + fn eq(&self, other: &FI) -> bool { + self.bits.eq(&(*other).into()) + } +} +#[doc = " Register writer."] +#[doc = ""] +#[doc = " Used as an argument to the closures in the `write` and `modify` methods of the register."] +pub struct W { + #[doc = "Writable bits"] + pub(crate) bits: REG::Ux, + _reg: marker::PhantomData, +} +impl W { + #[doc = " Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = " Field reader."] +#[doc = ""] +#[doc = " Result of the `read` methods of fields."] +pub struct FieldReader { + pub(crate) bits: U, + _reg: marker::PhantomData, +} +impl FieldReader +where + U: Copy, +{ + #[doc = " Creates a new instance of the reader."] + #[allow(unused)] + #[inline(always)] + pub(crate) fn new(bits: U) -> Self { + Self { + bits, + _reg: marker::PhantomData, + } + } + #[doc = " Reads raw bits from field."] + #[inline(always)] + pub fn bits(&self) -> U { + self.bits + } +} +impl PartialEq for FieldReader +where + U: PartialEq, + FI: Copy + Into, +{ + #[inline(always)] + fn eq(&self, other: &FI) -> bool { + self.bits.eq(&(*other).into()) + } +} +impl FieldReader { + #[doc = " Value of the field as raw bits."] + #[inline(always)] + pub fn bit(&self) -> bool { + self.bits + } + #[doc = " Returns `true` if the bit is clear (0)."] + #[inline(always)] + pub fn bit_is_clear(&self) -> bool { + !self.bit() + } + #[doc = " Returns `true` if the bit is set (1)."] + #[inline(always)] + pub fn bit_is_set(&self) -> bool { + self.bit() + } +} diff --git a/pac/atsamc21g/src/hmatrixhs.rs b/pac/atsamc21g/src/hmatrixhs.rs new file mode 100644 index 000000000000..c8129ac89b6f --- /dev/null +++ b/pac/atsamc21g/src/hmatrixhs.rs @@ -0,0 +1,43 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00..0x40 - Master Configuration"] + pub mcfg: [crate::Reg; 16], + #[doc = "0x40..0x80 - Slave Configuration"] + pub scfg: [crate::Reg; 16], + #[doc = "0x80..0xa0 - PRS\\[%s\\]"] + pub prs: [PRS; 4], + _reserved3: [u8; 0x60], + #[doc = "0x100 - Master Remap Control"] + pub mrcr: crate::Reg, + _reserved4: [u8; 0x0c], + #[doc = "0x110..0x150 - Special Function"] + pub sfr: [crate::Reg; 16], +} +#[doc = r"Register block"] +#[repr(C)] +pub struct PRS { + #[doc = "0x00 - Priority A for Slave"] + pub pras: crate::Reg, + #[doc = "0x04 - Priority B for Slave"] + pub prbs: crate::Reg, +} +#[doc = r"Register block"] +#[doc = "PRS\\[%s\\]"] +pub mod prs; +#[doc = "MCFG register accessor: an alias for `Reg`"] +pub type MCFG = crate::Reg; +#[doc = "Master Configuration"] +pub mod mcfg; +#[doc = "SCFG register accessor: an alias for `Reg`"] +pub type SCFG = crate::Reg; +#[doc = "Slave Configuration"] +pub mod scfg; +#[doc = "MRCR register accessor: an alias for `Reg`"] +pub type MRCR = crate::Reg; +#[doc = "Master Remap Control"] +pub mod mrcr; +#[doc = "SFR register accessor: an alias for `Reg`"] +pub type SFR = crate::Reg; +#[doc = "Special Function"] +pub mod sfr; diff --git a/pac/atsamc21g/src/hmatrixhs/mcfg.rs b/pac/atsamc21g/src/hmatrixhs/mcfg.rs new file mode 100644 index 000000000000..454a39fabe13 --- /dev/null +++ b/pac/atsamc21g/src/hmatrixhs/mcfg.rs @@ -0,0 +1,192 @@ +#[doc = "Register `MCFG[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MCFG[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Undefined Length Burst Type\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum ULBT_A { + #[doc = "0: Infinite Length"] + INFINITE = 0, + #[doc = "1: Single Access"] + SINGLE = 1, + #[doc = "2: Four Beat Burst"] + FOUR_BEAT = 2, + #[doc = "3: Eight Beat Burst"] + EIGHT_BEAT = 3, + #[doc = "4: Sixteen Beat Burst"] + SIXTEEN_BEAT = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: ULBT_A) -> Self { + variant as _ + } +} +#[doc = "Field `ULBT` reader - Undefined Length Burst Type"] +pub struct ULBT_R(crate::FieldReader); +impl ULBT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ULBT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(ULBT_A::INFINITE), + 1 => Some(ULBT_A::SINGLE), + 2 => Some(ULBT_A::FOUR_BEAT), + 3 => Some(ULBT_A::EIGHT_BEAT), + 4 => Some(ULBT_A::SIXTEEN_BEAT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `INFINITE`"] + #[inline(always)] + pub fn is_infinite(&self) -> bool { + **self == ULBT_A::INFINITE + } + #[doc = "Checks if the value of the field is `SINGLE`"] + #[inline(always)] + pub fn is_single(&self) -> bool { + **self == ULBT_A::SINGLE + } + #[doc = "Checks if the value of the field is `FOUR_BEAT`"] + #[inline(always)] + pub fn is_four_beat(&self) -> bool { + **self == ULBT_A::FOUR_BEAT + } + #[doc = "Checks if the value of the field is `EIGHT_BEAT`"] + #[inline(always)] + pub fn is_eight_beat(&self) -> bool { + **self == ULBT_A::EIGHT_BEAT + } + #[doc = "Checks if the value of the field is `SIXTEEN_BEAT`"] + #[inline(always)] + pub fn is_sixteen_beat(&self) -> bool { + **self == ULBT_A::SIXTEEN_BEAT + } +} +impl core::ops::Deref for ULBT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ULBT` writer - Undefined Length Burst Type"] +pub struct ULBT_W<'a> { + w: &'a mut W, +} +impl<'a> ULBT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: ULBT_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Infinite Length"] + #[inline(always)] + pub fn infinite(self) -> &'a mut W { + self.variant(ULBT_A::INFINITE) + } + #[doc = "Single Access"] + #[inline(always)] + pub fn single(self) -> &'a mut W { + self.variant(ULBT_A::SINGLE) + } + #[doc = "Four Beat Burst"] + #[inline(always)] + pub fn four_beat(self) -> &'a mut W { + self.variant(ULBT_A::FOUR_BEAT) + } + #[doc = "Eight Beat Burst"] + #[inline(always)] + pub fn eight_beat(self) -> &'a mut W { + self.variant(ULBT_A::EIGHT_BEAT) + } + #[doc = "Sixteen Beat Burst"] + #[inline(always)] + pub fn sixteen_beat(self) -> &'a mut W { + self.variant(ULBT_A::SIXTEEN_BEAT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Undefined Length Burst Type"] + #[inline(always)] + pub fn ulbt(&self) -> ULBT_R { + ULBT_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Undefined Length Burst Type"] + #[inline(always)] + pub fn ulbt(&mut self) -> ULBT_W { + ULBT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Master Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mcfg](index.html) module"] +pub struct MCFG_SPEC; +impl crate::RegisterSpec for MCFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [mcfg::R](R) reader structure"] +impl crate::Readable for MCFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [mcfg::W](W) writer structure"] +impl crate::Writable for MCFG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets MCFG[%s] +to value 0x02"] +impl crate::Resettable for MCFG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x02 + } +} diff --git a/pac/atsamc21g/src/hmatrixhs/mrcr.rs b/pac/atsamc21g/src/hmatrixhs/mrcr.rs new file mode 100644 index 000000000000..0cf2a1fb01be --- /dev/null +++ b/pac/atsamc21g/src/hmatrixhs/mrcr.rs @@ -0,0 +1,1570 @@ +#[doc = "Register `MRCR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MRCR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Remap Command Bit for Master 0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB0_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB0_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB0` reader - Remap Command Bit for Master 0"] +pub struct RCB0_R(crate::FieldReader); +impl RCB0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB0_A { + match self.bits { + false => RCB0_A::DIS, + true => RCB0_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB0_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB0_A::ENA + } +} +impl core::ops::Deref for RCB0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB0` writer - Remap Command Bit for Master 0"] +pub struct RCB0_W<'a> { + w: &'a mut W, +} +impl<'a> RCB0_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB0_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB0_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB0_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Remap Command Bit for Master 1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB1_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB1_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB1` reader - Remap Command Bit for Master 1"] +pub struct RCB1_R(crate::FieldReader); +impl RCB1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB1_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB1_A { + match self.bits { + false => RCB1_A::DIS, + true => RCB1_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB1_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB1_A::ENA + } +} +impl core::ops::Deref for RCB1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB1` writer - Remap Command Bit for Master 1"] +pub struct RCB1_W<'a> { + w: &'a mut W, +} +impl<'a> RCB1_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB1_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB1_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB1_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Remap Command Bit for Master 2\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB2_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB2_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB2` reader - Remap Command Bit for Master 2"] +pub struct RCB2_R(crate::FieldReader); +impl RCB2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB2_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB2_A { + match self.bits { + false => RCB2_A::DIS, + true => RCB2_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB2_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB2_A::ENA + } +} +impl core::ops::Deref for RCB2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB2` writer - Remap Command Bit for Master 2"] +pub struct RCB2_W<'a> { + w: &'a mut W, +} +impl<'a> RCB2_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB2_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB2_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB2_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Remap Command Bit for Master 3\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB3_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB3_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB3` reader - Remap Command Bit for Master 3"] +pub struct RCB3_R(crate::FieldReader); +impl RCB3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB3_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB3_A { + match self.bits { + false => RCB3_A::DIS, + true => RCB3_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB3_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB3_A::ENA + } +} +impl core::ops::Deref for RCB3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB3` writer - Remap Command Bit for Master 3"] +pub struct RCB3_W<'a> { + w: &'a mut W, +} +impl<'a> RCB3_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB3_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB3_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB3_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Remap Command Bit for Master 4\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB4_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB4_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB4` reader - Remap Command Bit for Master 4"] +pub struct RCB4_R(crate::FieldReader); +impl RCB4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB4_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB4_A { + match self.bits { + false => RCB4_A::DIS, + true => RCB4_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB4_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB4_A::ENA + } +} +impl core::ops::Deref for RCB4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB4` writer - Remap Command Bit for Master 4"] +pub struct RCB4_W<'a> { + w: &'a mut W, +} +impl<'a> RCB4_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB4_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB4_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB4_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Remap Command Bit for Master 5\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB5_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB5_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB5` reader - Remap Command Bit for Master 5"] +pub struct RCB5_R(crate::FieldReader); +impl RCB5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB5_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB5_A { + match self.bits { + false => RCB5_A::DIS, + true => RCB5_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB5_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB5_A::ENA + } +} +impl core::ops::Deref for RCB5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB5` writer - Remap Command Bit for Master 5"] +pub struct RCB5_W<'a> { + w: &'a mut W, +} +impl<'a> RCB5_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB5_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB5_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB5_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Remap Command Bit for Master 6\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB6_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB6_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB6` reader - Remap Command Bit for Master 6"] +pub struct RCB6_R(crate::FieldReader); +impl RCB6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB6_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB6_A { + match self.bits { + false => RCB6_A::DIS, + true => RCB6_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB6_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB6_A::ENA + } +} +impl core::ops::Deref for RCB6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB6` writer - Remap Command Bit for Master 6"] +pub struct RCB6_W<'a> { + w: &'a mut W, +} +impl<'a> RCB6_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB6_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB6_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB6_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Remap Command Bit for Master 7\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB7_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB7_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB7` reader - Remap Command Bit for Master 7"] +pub struct RCB7_R(crate::FieldReader); +impl RCB7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB7_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB7_A { + match self.bits { + false => RCB7_A::DIS, + true => RCB7_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB7_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB7_A::ENA + } +} +impl core::ops::Deref for RCB7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB7` writer - Remap Command Bit for Master 7"] +pub struct RCB7_W<'a> { + w: &'a mut W, +} +impl<'a> RCB7_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB7_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB7_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB7_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Remap Command Bit for Master 8\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB8_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB8_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB8` reader - Remap Command Bit for Master 8"] +pub struct RCB8_R(crate::FieldReader); +impl RCB8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB8_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB8_A { + match self.bits { + false => RCB8_A::DIS, + true => RCB8_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB8_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB8_A::ENA + } +} +impl core::ops::Deref for RCB8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB8` writer - Remap Command Bit for Master 8"] +pub struct RCB8_W<'a> { + w: &'a mut W, +} +impl<'a> RCB8_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB8_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB8_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB8_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Remap Command Bit for Master 9\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB9_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB9_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB9` reader - Remap Command Bit for Master 9"] +pub struct RCB9_R(crate::FieldReader); +impl RCB9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB9_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB9_A { + match self.bits { + false => RCB9_A::DIS, + true => RCB9_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB9_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB9_A::ENA + } +} +impl core::ops::Deref for RCB9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB9` writer - Remap Command Bit for Master 9"] +pub struct RCB9_W<'a> { + w: &'a mut W, +} +impl<'a> RCB9_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB9_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB9_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB9_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Remap Command Bit for Master 10\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB10_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB10_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB10` reader - Remap Command Bit for Master 10"] +pub struct RCB10_R(crate::FieldReader); +impl RCB10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB10_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB10_A { + match self.bits { + false => RCB10_A::DIS, + true => RCB10_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB10_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB10_A::ENA + } +} +impl core::ops::Deref for RCB10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB10` writer - Remap Command Bit for Master 10"] +pub struct RCB10_W<'a> { + w: &'a mut W, +} +impl<'a> RCB10_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB10_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB10_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB10_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Remap Command Bit for Master 11\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB11_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB11_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB11` reader - Remap Command Bit for Master 11"] +pub struct RCB11_R(crate::FieldReader); +impl RCB11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB11_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB11_A { + match self.bits { + false => RCB11_A::DIS, + true => RCB11_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB11_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB11_A::ENA + } +} +impl core::ops::Deref for RCB11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB11` writer - Remap Command Bit for Master 11"] +pub struct RCB11_W<'a> { + w: &'a mut W, +} +impl<'a> RCB11_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB11_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB11_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB11_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Remap Command Bit for Master 12\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB12_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB12_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB12` reader - Remap Command Bit for Master 12"] +pub struct RCB12_R(crate::FieldReader); +impl RCB12_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB12_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB12_A { + match self.bits { + false => RCB12_A::DIS, + true => RCB12_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB12_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB12_A::ENA + } +} +impl core::ops::Deref for RCB12_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB12` writer - Remap Command Bit for Master 12"] +pub struct RCB12_W<'a> { + w: &'a mut W, +} +impl<'a> RCB12_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB12_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB12_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB12_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Remap Command Bit for Master 13\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB13_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB13_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB13` reader - Remap Command Bit for Master 13"] +pub struct RCB13_R(crate::FieldReader); +impl RCB13_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB13_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB13_A { + match self.bits { + false => RCB13_A::DIS, + true => RCB13_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB13_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB13_A::ENA + } +} +impl core::ops::Deref for RCB13_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB13` writer - Remap Command Bit for Master 13"] +pub struct RCB13_W<'a> { + w: &'a mut W, +} +impl<'a> RCB13_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB13_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB13_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB13_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Remap Command Bit for Master 14\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB14_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB14_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB14` reader - Remap Command Bit for Master 14"] +pub struct RCB14_R(crate::FieldReader); +impl RCB14_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB14_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB14_A { + match self.bits { + false => RCB14_A::DIS, + true => RCB14_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB14_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB14_A::ENA + } +} +impl core::ops::Deref for RCB14_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB14` writer - Remap Command Bit for Master 14"] +pub struct RCB14_W<'a> { + w: &'a mut W, +} +impl<'a> RCB14_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB14_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB14_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB14_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Remap Command Bit for Master 15\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB15_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB15_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB15` reader - Remap Command Bit for Master 15"] +pub struct RCB15_R(crate::FieldReader); +impl RCB15_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB15_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB15_A { + match self.bits { + false => RCB15_A::DIS, + true => RCB15_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB15_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB15_A::ENA + } +} +impl core::ops::Deref for RCB15_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB15` writer - Remap Command Bit for Master 15"] +pub struct RCB15_W<'a> { + w: &'a mut W, +} +impl<'a> RCB15_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB15_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB15_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB15_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Remap Command Bit for Master 0"] + #[inline(always)] + pub fn rcb0(&self) -> RCB0_R { + RCB0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Remap Command Bit for Master 1"] + #[inline(always)] + pub fn rcb1(&self) -> RCB1_R { + RCB1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Remap Command Bit for Master 2"] + #[inline(always)] + pub fn rcb2(&self) -> RCB2_R { + RCB2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Remap Command Bit for Master 3"] + #[inline(always)] + pub fn rcb3(&self) -> RCB3_R { + RCB3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Remap Command Bit for Master 4"] + #[inline(always)] + pub fn rcb4(&self) -> RCB4_R { + RCB4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Remap Command Bit for Master 5"] + #[inline(always)] + pub fn rcb5(&self) -> RCB5_R { + RCB5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Remap Command Bit for Master 6"] + #[inline(always)] + pub fn rcb6(&self) -> RCB6_R { + RCB6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Remap Command Bit for Master 7"] + #[inline(always)] + pub fn rcb7(&self) -> RCB7_R { + RCB7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Remap Command Bit for Master 8"] + #[inline(always)] + pub fn rcb8(&self) -> RCB8_R { + RCB8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Remap Command Bit for Master 9"] + #[inline(always)] + pub fn rcb9(&self) -> RCB9_R { + RCB9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Remap Command Bit for Master 10"] + #[inline(always)] + pub fn rcb10(&self) -> RCB10_R { + RCB10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Remap Command Bit for Master 11"] + #[inline(always)] + pub fn rcb11(&self) -> RCB11_R { + RCB11_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Remap Command Bit for Master 12"] + #[inline(always)] + pub fn rcb12(&self) -> RCB12_R { + RCB12_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Remap Command Bit for Master 13"] + #[inline(always)] + pub fn rcb13(&self) -> RCB13_R { + RCB13_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Remap Command Bit for Master 14"] + #[inline(always)] + pub fn rcb14(&self) -> RCB14_R { + RCB14_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Remap Command Bit for Master 15"] + #[inline(always)] + pub fn rcb15(&self) -> RCB15_R { + RCB15_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Remap Command Bit for Master 0"] + #[inline(always)] + pub fn rcb0(&mut self) -> RCB0_W { + RCB0_W { w: self } + } + #[doc = "Bit 1 - Remap Command Bit for Master 1"] + #[inline(always)] + pub fn rcb1(&mut self) -> RCB1_W { + RCB1_W { w: self } + } + #[doc = "Bit 2 - Remap Command Bit for Master 2"] + #[inline(always)] + pub fn rcb2(&mut self) -> RCB2_W { + RCB2_W { w: self } + } + #[doc = "Bit 3 - Remap Command Bit for Master 3"] + #[inline(always)] + pub fn rcb3(&mut self) -> RCB3_W { + RCB3_W { w: self } + } + #[doc = "Bit 4 - Remap Command Bit for Master 4"] + #[inline(always)] + pub fn rcb4(&mut self) -> RCB4_W { + RCB4_W { w: self } + } + #[doc = "Bit 5 - Remap Command Bit for Master 5"] + #[inline(always)] + pub fn rcb5(&mut self) -> RCB5_W { + RCB5_W { w: self } + } + #[doc = "Bit 6 - Remap Command Bit for Master 6"] + #[inline(always)] + pub fn rcb6(&mut self) -> RCB6_W { + RCB6_W { w: self } + } + #[doc = "Bit 7 - Remap Command Bit for Master 7"] + #[inline(always)] + pub fn rcb7(&mut self) -> RCB7_W { + RCB7_W { w: self } + } + #[doc = "Bit 8 - Remap Command Bit for Master 8"] + #[inline(always)] + pub fn rcb8(&mut self) -> RCB8_W { + RCB8_W { w: self } + } + #[doc = "Bit 9 - Remap Command Bit for Master 9"] + #[inline(always)] + pub fn rcb9(&mut self) -> RCB9_W { + RCB9_W { w: self } + } + #[doc = "Bit 10 - Remap Command Bit for Master 10"] + #[inline(always)] + pub fn rcb10(&mut self) -> RCB10_W { + RCB10_W { w: self } + } + #[doc = "Bit 11 - Remap Command Bit for Master 11"] + #[inline(always)] + pub fn rcb11(&mut self) -> RCB11_W { + RCB11_W { w: self } + } + #[doc = "Bit 12 - Remap Command Bit for Master 12"] + #[inline(always)] + pub fn rcb12(&mut self) -> RCB12_W { + RCB12_W { w: self } + } + #[doc = "Bit 13 - Remap Command Bit for Master 13"] + #[inline(always)] + pub fn rcb13(&mut self) -> RCB13_W { + RCB13_W { w: self } + } + #[doc = "Bit 14 - Remap Command Bit for Master 14"] + #[inline(always)] + pub fn rcb14(&mut self) -> RCB14_W { + RCB14_W { w: self } + } + #[doc = "Bit 15 - Remap Command Bit for Master 15"] + #[inline(always)] + pub fn rcb15(&mut self) -> RCB15_W { + RCB15_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Master Remap Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mrcr](index.html) module"] +pub struct MRCR_SPEC; +impl crate::RegisterSpec for MRCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [mrcr::R](R) reader structure"] +impl crate::Readable for MRCR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [mrcr::W](W) writer structure"] +impl crate::Writable for MRCR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets MRCR to value 0"] +impl crate::Resettable for MRCR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/hmatrixhs/prs.rs b/pac/atsamc21g/src/hmatrixhs/prs.rs new file mode 100644 index 000000000000..0313f3c4fc20 --- /dev/null +++ b/pac/atsamc21g/src/hmatrixhs/prs.rs @@ -0,0 +1,8 @@ +#[doc = "PRAS register accessor: an alias for `Reg`"] +pub type PRAS = crate::Reg; +#[doc = "Priority A for Slave"] +pub mod pras; +#[doc = "PRBS register accessor: an alias for `Reg`"] +pub type PRBS = crate::Reg; +#[doc = "Priority B for Slave"] +pub mod prbs; diff --git a/pac/atsamc21g/src/hmatrixhs/prs/pras.rs b/pac/atsamc21g/src/hmatrixhs/prs/pras.rs new file mode 100644 index 000000000000..ac4744a9e2a0 --- /dev/null +++ b/pac/atsamc21g/src/hmatrixhs/prs/pras.rs @@ -0,0 +1,362 @@ +#[doc = "Register `PRAS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PRAS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `M0PR` reader - Master 0 Priority"] +pub struct M0PR_R(crate::FieldReader); +impl M0PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M0PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M0PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M0PR` writer - Master 0 Priority"] +pub struct M0PR_W<'a> { + w: &'a mut W, +} +impl<'a> M0PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Field `M1PR` reader - Master 1 Priority"] +pub struct M1PR_R(crate::FieldReader); +impl M1PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M1PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M1PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M1PR` writer - Master 1 Priority"] +pub struct M1PR_W<'a> { + w: &'a mut W, +} +impl<'a> M1PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 4)) | ((value as u32 & 0x0f) << 4); + self.w + } +} +#[doc = "Field `M2PR` reader - Master 2 Priority"] +pub struct M2PR_R(crate::FieldReader); +impl M2PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M2PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M2PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M2PR` writer - Master 2 Priority"] +pub struct M2PR_W<'a> { + w: &'a mut W, +} +impl<'a> M2PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 8)) | ((value as u32 & 0x0f) << 8); + self.w + } +} +#[doc = "Field `M3PR` reader - Master 3 Priority"] +pub struct M3PR_R(crate::FieldReader); +impl M3PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M3PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M3PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M3PR` writer - Master 3 Priority"] +pub struct M3PR_W<'a> { + w: &'a mut W, +} +impl<'a> M3PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 12)) | ((value as u32 & 0x0f) << 12); + self.w + } +} +#[doc = "Field `M4PR` reader - Master 4 Priority"] +pub struct M4PR_R(crate::FieldReader); +impl M4PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M4PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M4PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M4PR` writer - Master 4 Priority"] +pub struct M4PR_W<'a> { + w: &'a mut W, +} +impl<'a> M4PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 16)) | ((value as u32 & 0x0f) << 16); + self.w + } +} +#[doc = "Field `M5PR` reader - Master 5 Priority"] +pub struct M5PR_R(crate::FieldReader); +impl M5PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M5PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M5PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M5PR` writer - Master 5 Priority"] +pub struct M5PR_W<'a> { + w: &'a mut W, +} +impl<'a> M5PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 20)) | ((value as u32 & 0x0f) << 20); + self.w + } +} +#[doc = "Field `M6PR` reader - Master 6 Priority"] +pub struct M6PR_R(crate::FieldReader); +impl M6PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M6PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M6PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M6PR` writer - Master 6 Priority"] +pub struct M6PR_W<'a> { + w: &'a mut W, +} +impl<'a> M6PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Field `M7PR` reader - Master 7 Priority"] +pub struct M7PR_R(crate::FieldReader); +impl M7PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M7PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M7PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M7PR` writer - Master 7 Priority"] +pub struct M7PR_W<'a> { + w: &'a mut W, +} +impl<'a> M7PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 28)) | ((value as u32 & 0x0f) << 28); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Master 0 Priority"] + #[inline(always)] + pub fn m0pr(&self) -> M0PR_R { + M0PR_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Master 1 Priority"] + #[inline(always)] + pub fn m1pr(&self) -> M1PR_R { + M1PR_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 8:11 - Master 2 Priority"] + #[inline(always)] + pub fn m2pr(&self) -> M2PR_R { + M2PR_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - Master 3 Priority"] + #[inline(always)] + pub fn m3pr(&self) -> M3PR_R { + M3PR_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:19 - Master 4 Priority"] + #[inline(always)] + pub fn m4pr(&self) -> M4PR_R { + M4PR_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bits 20:23 - Master 5 Priority"] + #[inline(always)] + pub fn m5pr(&self) -> M5PR_R { + M5PR_R::new(((self.bits >> 20) & 0x0f) as u8) + } + #[doc = "Bits 24:27 - Master 6 Priority"] + #[inline(always)] + pub fn m6pr(&self) -> M6PR_R { + M6PR_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bits 28:31 - Master 7 Priority"] + #[inline(always)] + pub fn m7pr(&self) -> M7PR_R { + M7PR_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Master 0 Priority"] + #[inline(always)] + pub fn m0pr(&mut self) -> M0PR_W { + M0PR_W { w: self } + } + #[doc = "Bits 4:7 - Master 1 Priority"] + #[inline(always)] + pub fn m1pr(&mut self) -> M1PR_W { + M1PR_W { w: self } + } + #[doc = "Bits 8:11 - Master 2 Priority"] + #[inline(always)] + pub fn m2pr(&mut self) -> M2PR_W { + M2PR_W { w: self } + } + #[doc = "Bits 12:15 - Master 3 Priority"] + #[inline(always)] + pub fn m3pr(&mut self) -> M3PR_W { + M3PR_W { w: self } + } + #[doc = "Bits 16:19 - Master 4 Priority"] + #[inline(always)] + pub fn m4pr(&mut self) -> M4PR_W { + M4PR_W { w: self } + } + #[doc = "Bits 20:23 - Master 5 Priority"] + #[inline(always)] + pub fn m5pr(&mut self) -> M5PR_W { + M5PR_W { w: self } + } + #[doc = "Bits 24:27 - Master 6 Priority"] + #[inline(always)] + pub fn m6pr(&mut self) -> M6PR_W { + M6PR_W { w: self } + } + #[doc = "Bits 28:31 - Master 7 Priority"] + #[inline(always)] + pub fn m7pr(&mut self) -> M7PR_W { + M7PR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Priority A for Slave\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pras](index.html) module"] +pub struct PRAS_SPEC; +impl crate::RegisterSpec for PRAS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pras::R](R) reader structure"] +impl crate::Readable for PRAS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [pras::W](W) writer structure"] +impl crate::Writable for PRAS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PRAS to value 0"] +impl crate::Resettable for PRAS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/hmatrixhs/prs/prbs.rs b/pac/atsamc21g/src/hmatrixhs/prs/prbs.rs new file mode 100644 index 000000000000..a2cc6bb9f6b0 --- /dev/null +++ b/pac/atsamc21g/src/hmatrixhs/prs/prbs.rs @@ -0,0 +1,362 @@ +#[doc = "Register `PRBS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PRBS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `M8PR` reader - Master 8 Priority"] +pub struct M8PR_R(crate::FieldReader); +impl M8PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M8PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M8PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M8PR` writer - Master 8 Priority"] +pub struct M8PR_W<'a> { + w: &'a mut W, +} +impl<'a> M8PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Field `M9PR` reader - Master 9 Priority"] +pub struct M9PR_R(crate::FieldReader); +impl M9PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M9PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M9PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M9PR` writer - Master 9 Priority"] +pub struct M9PR_W<'a> { + w: &'a mut W, +} +impl<'a> M9PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 4)) | ((value as u32 & 0x0f) << 4); + self.w + } +} +#[doc = "Field `M10PR` reader - Master 10 Priority"] +pub struct M10PR_R(crate::FieldReader); +impl M10PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M10PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M10PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M10PR` writer - Master 10 Priority"] +pub struct M10PR_W<'a> { + w: &'a mut W, +} +impl<'a> M10PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 8)) | ((value as u32 & 0x0f) << 8); + self.w + } +} +#[doc = "Field `M11PR` reader - Master 11 Priority"] +pub struct M11PR_R(crate::FieldReader); +impl M11PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M11PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M11PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M11PR` writer - Master 11 Priority"] +pub struct M11PR_W<'a> { + w: &'a mut W, +} +impl<'a> M11PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 12)) | ((value as u32 & 0x0f) << 12); + self.w + } +} +#[doc = "Field `M12PR` reader - Master 12 Priority"] +pub struct M12PR_R(crate::FieldReader); +impl M12PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M12PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M12PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M12PR` writer - Master 12 Priority"] +pub struct M12PR_W<'a> { + w: &'a mut W, +} +impl<'a> M12PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 16)) | ((value as u32 & 0x0f) << 16); + self.w + } +} +#[doc = "Field `M13PR` reader - Master 13 Priority"] +pub struct M13PR_R(crate::FieldReader); +impl M13PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M13PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M13PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M13PR` writer - Master 13 Priority"] +pub struct M13PR_W<'a> { + w: &'a mut W, +} +impl<'a> M13PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 20)) | ((value as u32 & 0x0f) << 20); + self.w + } +} +#[doc = "Field `M14PR` reader - Master 14 Priority"] +pub struct M14PR_R(crate::FieldReader); +impl M14PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M14PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M14PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M14PR` writer - Master 14 Priority"] +pub struct M14PR_W<'a> { + w: &'a mut W, +} +impl<'a> M14PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Field `M15PR` reader - Master 15 Priority"] +pub struct M15PR_R(crate::FieldReader); +impl M15PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M15PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M15PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M15PR` writer - Master 15 Priority"] +pub struct M15PR_W<'a> { + w: &'a mut W, +} +impl<'a> M15PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 28)) | ((value as u32 & 0x0f) << 28); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Master 8 Priority"] + #[inline(always)] + pub fn m8pr(&self) -> M8PR_R { + M8PR_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Master 9 Priority"] + #[inline(always)] + pub fn m9pr(&self) -> M9PR_R { + M9PR_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 8:11 - Master 10 Priority"] + #[inline(always)] + pub fn m10pr(&self) -> M10PR_R { + M10PR_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - Master 11 Priority"] + #[inline(always)] + pub fn m11pr(&self) -> M11PR_R { + M11PR_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:19 - Master 12 Priority"] + #[inline(always)] + pub fn m12pr(&self) -> M12PR_R { + M12PR_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bits 20:23 - Master 13 Priority"] + #[inline(always)] + pub fn m13pr(&self) -> M13PR_R { + M13PR_R::new(((self.bits >> 20) & 0x0f) as u8) + } + #[doc = "Bits 24:27 - Master 14 Priority"] + #[inline(always)] + pub fn m14pr(&self) -> M14PR_R { + M14PR_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bits 28:31 - Master 15 Priority"] + #[inline(always)] + pub fn m15pr(&self) -> M15PR_R { + M15PR_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Master 8 Priority"] + #[inline(always)] + pub fn m8pr(&mut self) -> M8PR_W { + M8PR_W { w: self } + } + #[doc = "Bits 4:7 - Master 9 Priority"] + #[inline(always)] + pub fn m9pr(&mut self) -> M9PR_W { + M9PR_W { w: self } + } + #[doc = "Bits 8:11 - Master 10 Priority"] + #[inline(always)] + pub fn m10pr(&mut self) -> M10PR_W { + M10PR_W { w: self } + } + #[doc = "Bits 12:15 - Master 11 Priority"] + #[inline(always)] + pub fn m11pr(&mut self) -> M11PR_W { + M11PR_W { w: self } + } + #[doc = "Bits 16:19 - Master 12 Priority"] + #[inline(always)] + pub fn m12pr(&mut self) -> M12PR_W { + M12PR_W { w: self } + } + #[doc = "Bits 20:23 - Master 13 Priority"] + #[inline(always)] + pub fn m13pr(&mut self) -> M13PR_W { + M13PR_W { w: self } + } + #[doc = "Bits 24:27 - Master 14 Priority"] + #[inline(always)] + pub fn m14pr(&mut self) -> M14PR_W { + M14PR_W { w: self } + } + #[doc = "Bits 28:31 - Master 15 Priority"] + #[inline(always)] + pub fn m15pr(&mut self) -> M15PR_W { + M15PR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Priority B for Slave\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [prbs](index.html) module"] +pub struct PRBS_SPEC; +impl crate::RegisterSpec for PRBS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [prbs::R](R) reader structure"] +impl crate::Readable for PRBS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [prbs::W](W) writer structure"] +impl crate::Writable for PRBS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PRBS to value 0"] +impl crate::Resettable for PRBS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/hmatrixhs/scfg.rs b/pac/atsamc21g/src/hmatrixhs/scfg.rs new file mode 100644 index 000000000000..7180c043195a --- /dev/null +++ b/pac/atsamc21g/src/hmatrixhs/scfg.rs @@ -0,0 +1,334 @@ +#[doc = "Register `SCFG[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SCFG[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SLOT_CYCLE` reader - Maximum Number of Allowed Cycles for a Burst"] +pub struct SLOT_CYCLE_R(crate::FieldReader); +impl SLOT_CYCLE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SLOT_CYCLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SLOT_CYCLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLOT_CYCLE` writer - Maximum Number of Allowed Cycles for a Burst"] +pub struct SLOT_CYCLE_W<'a> { + w: &'a mut W, +} +impl<'a> SLOT_CYCLE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +#[doc = "Default Master Type\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DEFMSTR_TYPE_A { + #[doc = "0: No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst."] + NO_DEFAULT = 0, + #[doc = "1: Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave."] + LAST_DEFAULT = 1, + #[doc = "2: Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave."] + FIXED_DEFAULT = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DEFMSTR_TYPE_A) -> Self { + variant as _ + } +} +#[doc = "Field `DEFMSTR_TYPE` reader - Default Master Type"] +pub struct DEFMSTR_TYPE_R(crate::FieldReader); +impl DEFMSTR_TYPE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DEFMSTR_TYPE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(DEFMSTR_TYPE_A::NO_DEFAULT), + 1 => Some(DEFMSTR_TYPE_A::LAST_DEFAULT), + 2 => Some(DEFMSTR_TYPE_A::FIXED_DEFAULT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NO_DEFAULT`"] + #[inline(always)] + pub fn is_no_default(&self) -> bool { + **self == DEFMSTR_TYPE_A::NO_DEFAULT + } + #[doc = "Checks if the value of the field is `LAST_DEFAULT`"] + #[inline(always)] + pub fn is_last_default(&self) -> bool { + **self == DEFMSTR_TYPE_A::LAST_DEFAULT + } + #[doc = "Checks if the value of the field is `FIXED_DEFAULT`"] + #[inline(always)] + pub fn is_fixed_default(&self) -> bool { + **self == DEFMSTR_TYPE_A::FIXED_DEFAULT + } +} +impl core::ops::Deref for DEFMSTR_TYPE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DEFMSTR_TYPE` writer - Default Master Type"] +pub struct DEFMSTR_TYPE_W<'a> { + w: &'a mut W, +} +impl<'a> DEFMSTR_TYPE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DEFMSTR_TYPE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst."] + #[inline(always)] + pub fn no_default(self) -> &'a mut W { + self.variant(DEFMSTR_TYPE_A::NO_DEFAULT) + } + #[doc = "Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave."] + #[inline(always)] + pub fn last_default(self) -> &'a mut W { + self.variant(DEFMSTR_TYPE_A::LAST_DEFAULT) + } + #[doc = "Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave."] + #[inline(always)] + pub fn fixed_default(self) -> &'a mut W { + self.variant(DEFMSTR_TYPE_A::FIXED_DEFAULT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Field `FIXED_DEFMSTR` reader - Fixed Index of Default Master"] +pub struct FIXED_DEFMSTR_R(crate::FieldReader); +impl FIXED_DEFMSTR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FIXED_DEFMSTR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FIXED_DEFMSTR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FIXED_DEFMSTR` writer - Fixed Index of Default Master"] +pub struct FIXED_DEFMSTR_W<'a> { + w: &'a mut W, +} +impl<'a> FIXED_DEFMSTR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 18)) | ((value as u32 & 0x0f) << 18); + self.w + } +} +#[doc = "Arbitration Type\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ARBT_A { + #[doc = "0: Round-Robin Arbitration"] + ROUND_ROBIN = 0, + #[doc = "1: Fixed Priority Arbitration"] + FIXED_PRIORITY = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ARBT_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ARBT` reader - Arbitration Type"] +pub struct ARBT_R(crate::FieldReader); +impl ARBT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ARBT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ARBT_A { + match self.bits { + false => ARBT_A::ROUND_ROBIN, + true => ARBT_A::FIXED_PRIORITY, + } + } + #[doc = "Checks if the value of the field is `ROUND_ROBIN`"] + #[inline(always)] + pub fn is_round_robin(&self) -> bool { + **self == ARBT_A::ROUND_ROBIN + } + #[doc = "Checks if the value of the field is `FIXED_PRIORITY`"] + #[inline(always)] + pub fn is_fixed_priority(&self) -> bool { + **self == ARBT_A::FIXED_PRIORITY + } +} +impl core::ops::Deref for ARBT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ARBT` writer - Arbitration Type"] +pub struct ARBT_W<'a> { + w: &'a mut W, +} +impl<'a> ARBT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: ARBT_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Round-Robin Arbitration"] + #[inline(always)] + pub fn round_robin(self) -> &'a mut W { + self.variant(ARBT_A::ROUND_ROBIN) + } + #[doc = "Fixed Priority Arbitration"] + #[inline(always)] + pub fn fixed_priority(self) -> &'a mut W { + self.variant(ARBT_A::FIXED_PRIORITY) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Maximum Number of Allowed Cycles for a Burst"] + #[inline(always)] + pub fn slot_cycle(&self) -> SLOT_CYCLE_R { + SLOT_CYCLE_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 16:17 - Default Master Type"] + #[inline(always)] + pub fn defmstr_type(&self) -> DEFMSTR_TYPE_R { + DEFMSTR_TYPE_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bits 18:21 - Fixed Index of Default Master"] + #[inline(always)] + pub fn fixed_defmstr(&self) -> FIXED_DEFMSTR_R { + FIXED_DEFMSTR_R::new(((self.bits >> 18) & 0x0f) as u8) + } + #[doc = "Bit 24 - Arbitration Type"] + #[inline(always)] + pub fn arbt(&self) -> ARBT_R { + ARBT_R::new(((self.bits >> 24) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - Maximum Number of Allowed Cycles for a Burst"] + #[inline(always)] + pub fn slot_cycle(&mut self) -> SLOT_CYCLE_W { + SLOT_CYCLE_W { w: self } + } + #[doc = "Bits 16:17 - Default Master Type"] + #[inline(always)] + pub fn defmstr_type(&mut self) -> DEFMSTR_TYPE_W { + DEFMSTR_TYPE_W { w: self } + } + #[doc = "Bits 18:21 - Fixed Index of Default Master"] + #[inline(always)] + pub fn fixed_defmstr(&mut self) -> FIXED_DEFMSTR_W { + FIXED_DEFMSTR_W { w: self } + } + #[doc = "Bit 24 - Arbitration Type"] + #[inline(always)] + pub fn arbt(&mut self) -> ARBT_W { + ARBT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Slave Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [scfg](index.html) module"] +pub struct SCFG_SPEC; +impl crate::RegisterSpec for SCFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [scfg::R](R) reader structure"] +impl crate::Readable for SCFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [scfg::W](W) writer structure"] +impl crate::Writable for SCFG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SCFG[%s] +to value 0x10"] +impl crate::Resettable for SCFG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x10 + } +} diff --git a/pac/atsamc21g/src/hmatrixhs/sfr.rs b/pac/atsamc21g/src/hmatrixhs/sfr.rs new file mode 100644 index 000000000000..0a7e024f73c8 --- /dev/null +++ b/pac/atsamc21g/src/hmatrixhs/sfr.rs @@ -0,0 +1,104 @@ +#[doc = "Register `SFR[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SFR[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SFR` reader - Special Function Register"] +pub struct SFR_R(crate::FieldReader); +impl SFR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + SFR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SFR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SFR` writer - Special Function Register"] +pub struct SFR_W<'a> { + w: &'a mut W, +} +impl<'a> SFR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Special Function Register"] + #[inline(always)] + pub fn sfr(&self) -> SFR_R { + SFR_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Special Function Register"] + #[inline(always)] + pub fn sfr(&mut self) -> SFR_W { + SFR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Special Function\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sfr](index.html) module"] +pub struct SFR_SPEC; +impl crate::RegisterSpec for SFR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [sfr::R](R) reader structure"] +impl crate::Readable for SFR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [sfr::W](W) writer structure"] +impl crate::Writable for SFR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SFR[%s] +to value 0"] +impl crate::Resettable for SFR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/lib.rs b/pac/atsamc21g/src/lib.rs new file mode 100644 index 000000000000..8969f3d2cfd9 --- /dev/null +++ b/pac/atsamc21g/src/lib.rs @@ -0,0 +1,1725 @@ +#![doc = "Peripheral access API for ATSAMC21G microcontrollers (generated using svd2rust v0.20.0 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] +svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.20.0/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"] +#![deny(const_err)] +#![deny(dead_code)] +#![deny(improper_ctypes)] +#![deny(missing_docs)] +#![deny(no_mangle_generic_items)] +#![deny(non_shorthand_field_patterns)] +#![deny(overflowing_literals)] +#![deny(path_statements)] +#![deny(patterns_in_fns_without_body)] +#![deny(private_in_public)] +#![deny(unconditional_recursion)] +#![deny(unused_allocation)] +#![deny(unused_comparisons)] +#![deny(unused_parens)] +#![deny(while_true)] +#![allow(non_camel_case_types)] +#![allow(non_snake_case)] +#![allow(clippy::all)] +#![no_std] +use core::marker::PhantomData; +use core::ops::Deref; +#[doc = r"Number available in the NVIC for configuring priority"] +pub const NVIC_PRIO_BITS: u8 = 2; +#[cfg(feature = "rt")] +pub use self::Interrupt as interrupt; +pub use cortex_m::peripheral::Peripherals as CorePeripherals; +pub use cortex_m::peripheral::{CBP, CPUID, DCB, DWT, FPB, ITM, MPU, NVIC, SCB, SYST, TPIU}; +#[cfg(feature = "rt")] +pub use cortex_m_rt::interrupt; +#[allow(unused_imports)] +use generic::*; +#[doc = r"Common register and bit access and modify traits"] +pub mod generic; +#[cfg(feature = "rt")] +extern "C" { + fn WDT(); + fn RTC(); + fn EIC(); + fn FREQM(); + fn TSENS(); + fn NVMCTRL(); + fn DMAC(); + fn EVSYS(); + fn SERCOM0(); + fn SERCOM1(); + fn SERCOM2(); + fn SERCOM3(); + fn SERCOM4(); + fn SERCOM5(); + fn CAN0(); + fn CAN1(); + fn TCC0(); + fn TCC1(); + fn TCC2(); + fn TC0(); + fn TC1(); + fn TC2(); + fn TC3(); + fn TC4(); + fn ADC0(); + fn ADC1(); + fn AC(); + fn DAC(); + fn SDADC(); + fn PTC(); +} +#[doc(hidden)] +pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, +} +#[cfg(feature = "rt")] +#[doc(hidden)] +#[link_section = ".vector_table.interrupts"] +#[no_mangle] +pub static __INTERRUPTS: [Vector; 31] = [ + Vector { _reserved: 0 }, + Vector { _handler: WDT }, + Vector { _handler: RTC }, + Vector { _handler: EIC }, + Vector { _handler: FREQM }, + Vector { _handler: TSENS }, + Vector { _handler: NVMCTRL }, + Vector { _handler: DMAC }, + Vector { _handler: EVSYS }, + Vector { _handler: SERCOM0 }, + Vector { _handler: SERCOM1 }, + Vector { _handler: SERCOM2 }, + Vector { _handler: SERCOM3 }, + Vector { _handler: SERCOM4 }, + Vector { _handler: SERCOM5 }, + Vector { _handler: CAN0 }, + Vector { _handler: CAN1 }, + Vector { _handler: TCC0 }, + Vector { _handler: TCC1 }, + Vector { _handler: TCC2 }, + Vector { _handler: TC0 }, + Vector { _handler: TC1 }, + Vector { _handler: TC2 }, + Vector { _handler: TC3 }, + Vector { _handler: TC4 }, + Vector { _handler: ADC0 }, + Vector { _handler: ADC1 }, + Vector { _handler: AC }, + Vector { _handler: DAC }, + Vector { _handler: SDADC }, + Vector { _handler: PTC }, +]; +#[doc = r"Enumeration of all the interrupts."] +#[derive(Copy, Clone, Debug, PartialEq, Eq)] +#[repr(u16)] +pub enum Interrupt { + #[doc = "1 - WDT"] + WDT = 1, + #[doc = "2 - RTC"] + RTC = 2, + #[doc = "3 - EIC"] + EIC = 3, + #[doc = "4 - FREQM"] + FREQM = 4, + #[doc = "5 - TSENS"] + TSENS = 5, + #[doc = "6 - NVMCTRL"] + NVMCTRL = 6, + #[doc = "7 - DMAC"] + DMAC = 7, + #[doc = "8 - EVSYS"] + EVSYS = 8, + #[doc = "9 - SERCOM0"] + SERCOM0 = 9, + #[doc = "10 - SERCOM1"] + SERCOM1 = 10, + #[doc = "11 - SERCOM2"] + SERCOM2 = 11, + #[doc = "12 - SERCOM3"] + SERCOM3 = 12, + #[doc = "13 - SERCOM4"] + SERCOM4 = 13, + #[doc = "14 - SERCOM5"] + SERCOM5 = 14, + #[doc = "15 - CAN0"] + CAN0 = 15, + #[doc = "16 - CAN1"] + CAN1 = 16, + #[doc = "17 - TCC0"] + TCC0 = 17, + #[doc = "18 - TCC1"] + TCC1 = 18, + #[doc = "19 - TCC2"] + TCC2 = 19, + #[doc = "20 - TC0"] + TC0 = 20, + #[doc = "21 - TC1"] + TC1 = 21, + #[doc = "22 - TC2"] + TC2 = 22, + #[doc = "23 - TC3"] + TC3 = 23, + #[doc = "24 - TC4"] + TC4 = 24, + #[doc = "25 - ADC0"] + ADC0 = 25, + #[doc = "26 - ADC1"] + ADC1 = 26, + #[doc = "27 - AC"] + AC = 27, + #[doc = "28 - DAC"] + DAC = 28, + #[doc = "29 - SDADC"] + SDADC = 29, + #[doc = "30 - PTC"] + PTC = 30, +} +unsafe impl cortex_m::interrupt::InterruptNumber for Interrupt { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } +} +#[doc = "Analog Comparators"] +pub struct AC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for AC {} +impl AC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const ac::RegisterBlock = 0x4200_5000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const ac::RegisterBlock { + Self::PTR + } +} +impl Deref for AC { + type Target = ac::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for AC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AC").finish() + } +} +#[doc = "Analog Comparators"] +pub mod ac; +#[doc = "Analog Digital Converter"] +pub struct ADC0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for ADC0 {} +impl ADC0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const adc0::RegisterBlock = 0x4200_4400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const adc0::RegisterBlock { + Self::PTR + } +} +impl Deref for ADC0 { + type Target = adc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for ADC0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ADC0").finish() + } +} +#[doc = "Analog Digital Converter"] +pub mod adc0; +#[doc = "Analog Digital Converter"] +pub struct ADC1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for ADC1 {} +impl ADC1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const adc0::RegisterBlock = 0x4200_4800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const adc0::RegisterBlock { + Self::PTR + } +} +impl Deref for ADC1 { + type Target = adc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for ADC1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ADC1").finish() + } +} +#[doc = "Analog Digital Converter"] +pub use adc0 as adc1; +#[doc = "Control Area Network"] +pub struct CAN0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for CAN0 {} +impl CAN0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const can0::RegisterBlock = 0x4200_1c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const can0::RegisterBlock { + Self::PTR + } +} +impl Deref for CAN0 { + type Target = can0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for CAN0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CAN0").finish() + } +} +#[doc = "Control Area Network"] +pub mod can0; +#[doc = "Control Area Network"] +pub struct CAN1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for CAN1 {} +impl CAN1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const can0::RegisterBlock = 0x4200_2000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const can0::RegisterBlock { + Self::PTR + } +} +impl Deref for CAN1 { + type Target = can0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for CAN1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CAN1").finish() + } +} +#[doc = "Control Area Network"] +pub use can0 as can1; +#[doc = "Configurable Custom Logic"] +pub struct CCL { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for CCL {} +impl CCL { + #[doc = r"Pointer to the register block"] + pub const PTR: *const ccl::RegisterBlock = 0x4200_5c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const ccl::RegisterBlock { + Self::PTR + } +} +impl Deref for CCL { + type Target = ccl::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for CCL { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CCL").finish() + } +} +#[doc = "Configurable Custom Logic"] +pub mod ccl; +#[doc = "Digital Analog Converter"] +pub struct DAC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for DAC {} +impl DAC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const dac::RegisterBlock = 0x4200_5400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const dac::RegisterBlock { + Self::PTR + } +} +impl Deref for DAC { + type Target = dac::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for DAC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DAC").finish() + } +} +#[doc = "Digital Analog Converter"] +pub mod dac; +#[doc = "Divide and Square Root Accelerator"] +pub struct DIVAS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for DIVAS {} +impl DIVAS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const divas::RegisterBlock = 0x4800_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const divas::RegisterBlock { + Self::PTR + } +} +impl Deref for DIVAS { + type Target = divas::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for DIVAS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DIVAS").finish() + } +} +#[doc = "Divide and Square Root Accelerator"] +pub mod divas; +#[doc = "Direct Memory Access Controller"] +pub struct DMAC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for DMAC {} +impl DMAC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const dmac::RegisterBlock = 0x4100_6000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const dmac::RegisterBlock { + Self::PTR + } +} +impl Deref for DMAC { + type Target = dmac::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for DMAC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DMAC").finish() + } +} +#[doc = "Direct Memory Access Controller"] +pub mod dmac; +#[doc = "Device Service Unit"] +pub struct DSU { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for DSU {} +impl DSU { + #[doc = r"Pointer to the register block"] + pub const PTR: *const dsu::RegisterBlock = 0x4100_2000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const dsu::RegisterBlock { + Self::PTR + } +} +impl Deref for DSU { + type Target = dsu::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for DSU { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DSU").finish() + } +} +#[doc = "Device Service Unit"] +pub mod dsu; +#[doc = "External Interrupt Controller"] +pub struct EIC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for EIC {} +impl EIC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const eic::RegisterBlock = 0x4000_2800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const eic::RegisterBlock { + Self::PTR + } +} +impl Deref for EIC { + type Target = eic::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for EIC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EIC").finish() + } +} +#[doc = "External Interrupt Controller"] +pub mod eic; +#[doc = "Event System Interface"] +pub struct EVSYS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for EVSYS {} +impl EVSYS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const evsys::RegisterBlock = 0x4200_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const evsys::RegisterBlock { + Self::PTR + } +} +impl Deref for EVSYS { + type Target = evsys::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for EVSYS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EVSYS").finish() + } +} +#[doc = "Event System Interface"] +pub mod evsys; +#[doc = "Frequency Meter"] +pub struct FREQM { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for FREQM {} +impl FREQM { + #[doc = r"Pointer to the register block"] + pub const PTR: *const freqm::RegisterBlock = 0x4000_2c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const freqm::RegisterBlock { + Self::PTR + } +} +impl Deref for FREQM { + type Target = freqm::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for FREQM { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FREQM").finish() + } +} +#[doc = "Frequency Meter"] +pub mod freqm; +#[doc = "Generic Clock Generator"] +pub struct GCLK { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for GCLK {} +impl GCLK { + #[doc = r"Pointer to the register block"] + pub const PTR: *const gclk::RegisterBlock = 0x4000_1c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const gclk::RegisterBlock { + Self::PTR + } +} +impl Deref for GCLK { + type Target = gclk::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for GCLK { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GCLK").finish() + } +} +#[doc = "Generic Clock Generator"] +pub mod gclk; +#[doc = "HSB Matrix"] +pub struct HMATRIXHS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for HMATRIXHS {} +impl HMATRIXHS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const hmatrixhs::RegisterBlock = 0x4100_a000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const hmatrixhs::RegisterBlock { + Self::PTR + } +} +impl Deref for HMATRIXHS { + type Target = hmatrixhs::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for HMATRIXHS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HMATRIXHS").finish() + } +} +#[doc = "HSB Matrix"] +pub mod hmatrixhs; +#[doc = "Main Clock"] +pub struct MCLK { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for MCLK {} +impl MCLK { + #[doc = r"Pointer to the register block"] + pub const PTR: *const mclk::RegisterBlock = 0x4000_0800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const mclk::RegisterBlock { + Self::PTR + } +} +impl Deref for MCLK { + type Target = mclk::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for MCLK { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MCLK").finish() + } +} +#[doc = "Main Clock"] +pub mod mclk; +#[doc = "Cortex-M0+ Micro-Trace Buffer"] +pub struct MTB { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for MTB {} +impl MTB { + #[doc = r"Pointer to the register block"] + pub const PTR: *const mtb::RegisterBlock = 0x4100_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const mtb::RegisterBlock { + Self::PTR + } +} +impl Deref for MTB { + type Target = mtb::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for MTB { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MTB").finish() + } +} +#[doc = "Cortex-M0+ Micro-Trace Buffer"] +pub mod mtb; +#[doc = "Non-Volatile Memory Controller"] +pub struct NVMCTRL { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for NVMCTRL {} +impl NVMCTRL { + #[doc = r"Pointer to the register block"] + pub const PTR: *const nvmctrl::RegisterBlock = 0x4100_4000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const nvmctrl::RegisterBlock { + Self::PTR + } +} +impl Deref for NVMCTRL { + type Target = nvmctrl::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for NVMCTRL { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("NVMCTRL").finish() + } +} +#[doc = "Non-Volatile Memory Controller"] +pub mod nvmctrl; +#[doc = "Oscillators Control"] +pub struct OSCCTRL { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for OSCCTRL {} +impl OSCCTRL { + #[doc = r"Pointer to the register block"] + pub const PTR: *const oscctrl::RegisterBlock = 0x4000_1000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const oscctrl::RegisterBlock { + Self::PTR + } +} +impl Deref for OSCCTRL { + type Target = oscctrl::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for OSCCTRL { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OSCCTRL").finish() + } +} +#[doc = "Oscillators Control"] +pub mod oscctrl; +#[doc = "32k Oscillators Control"] +pub struct OSC32KCTRL { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for OSC32KCTRL {} +impl OSC32KCTRL { + #[doc = r"Pointer to the register block"] + pub const PTR: *const osc32kctrl::RegisterBlock = 0x4000_1400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const osc32kctrl::RegisterBlock { + Self::PTR + } +} +impl Deref for OSC32KCTRL { + type Target = osc32kctrl::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for OSC32KCTRL { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OSC32KCTRL").finish() + } +} +#[doc = "32k Oscillators Control"] +pub mod osc32kctrl; +#[doc = "Peripheral Access Controller"] +pub struct PAC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PAC {} +impl PAC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const pac::RegisterBlock = 0x4000_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const pac::RegisterBlock { + Self::PTR + } +} +impl Deref for PAC { + type Target = pac::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PAC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PAC").finish() + } +} +#[doc = "Peripheral Access Controller"] +pub mod pac; +#[doc = "Power Manager"] +pub struct PM { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PM {} +impl PM { + #[doc = r"Pointer to the register block"] + pub const PTR: *const pm::RegisterBlock = 0x4000_0400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const pm::RegisterBlock { + Self::PTR + } +} +impl Deref for PM { + type Target = pm::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PM { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PM").finish() + } +} +#[doc = "Power Manager"] +pub mod pm; +#[doc = "Port Module"] +pub struct PORT { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PORT {} +impl PORT { + #[doc = r"Pointer to the register block"] + pub const PTR: *const port::RegisterBlock = 0x4100_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const port::RegisterBlock { + Self::PTR + } +} +impl Deref for PORT { + type Target = port::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PORT { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PORT").finish() + } +} +#[doc = "Port Module"] +pub mod port; +#[doc = "Port Module"] +pub struct PORT_IOBUS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PORT_IOBUS {} +impl PORT_IOBUS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const port::RegisterBlock = 0x6000_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const port::RegisterBlock { + Self::PTR + } +} +impl Deref for PORT_IOBUS { + type Target = port::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PORT_IOBUS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PORT_IOBUS").finish() + } +} +#[doc = "Port Module"] +pub use port as port_iobus; +#[doc = "Reset Controller"] +pub struct RSTC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for RSTC {} +impl RSTC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const rstc::RegisterBlock = 0x4000_0c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const rstc::RegisterBlock { + Self::PTR + } +} +impl Deref for RSTC { + type Target = rstc::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for RSTC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RSTC").finish() + } +} +#[doc = "Reset Controller"] +pub mod rstc; +#[doc = "Real-Time Counter"] +pub struct RTC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for RTC {} +impl RTC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const rtc::RegisterBlock = 0x4000_2400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const rtc::RegisterBlock { + Self::PTR + } +} +impl Deref for RTC { + type Target = rtc::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for RTC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RTC").finish() + } +} +#[doc = "Real-Time Counter"] +pub mod rtc; +#[doc = "Sigma-Delta Analog Digital Converter"] +pub struct SDADC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SDADC {} +impl SDADC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sdadc::RegisterBlock = 0x4200_4c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sdadc::RegisterBlock { + Self::PTR + } +} +impl Deref for SDADC { + type Target = sdadc::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SDADC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SDADC").finish() + } +} +#[doc = "Sigma-Delta Analog Digital Converter"] +pub mod sdadc; +#[doc = "Serial Communication Interface"] +pub struct SERCOM0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SERCOM0 {} +impl SERCOM0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sercom0::RegisterBlock = 0x4200_0400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sercom0::RegisterBlock { + Self::PTR + } +} +impl Deref for SERCOM0 { + type Target = sercom0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SERCOM0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SERCOM0").finish() + } +} +#[doc = "Serial Communication Interface"] +pub mod sercom0; +#[doc = "Serial Communication Interface"] +pub struct SERCOM1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SERCOM1 {} +impl SERCOM1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sercom0::RegisterBlock = 0x4200_0800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sercom0::RegisterBlock { + Self::PTR + } +} +impl Deref for SERCOM1 { + type Target = sercom0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SERCOM1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SERCOM1").finish() + } +} +#[doc = "Serial Communication Interface"] +pub use sercom0 as sercom1; +#[doc = "Serial Communication Interface"] +pub struct SERCOM2 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SERCOM2 {} +impl SERCOM2 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sercom0::RegisterBlock = 0x4200_0c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sercom0::RegisterBlock { + Self::PTR + } +} +impl Deref for SERCOM2 { + type Target = sercom0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SERCOM2 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SERCOM2").finish() + } +} +#[doc = "Serial Communication Interface"] +pub use sercom0 as sercom2; +#[doc = "Serial Communication Interface"] +pub struct SERCOM3 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SERCOM3 {} +impl SERCOM3 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sercom0::RegisterBlock = 0x4200_1000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sercom0::RegisterBlock { + Self::PTR + } +} +impl Deref for SERCOM3 { + type Target = sercom0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SERCOM3 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SERCOM3").finish() + } +} +#[doc = "Serial Communication Interface"] +pub use sercom0 as sercom3; +#[doc = "Serial Communication Interface"] +pub struct SERCOM4 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SERCOM4 {} +impl SERCOM4 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sercom0::RegisterBlock = 0x4200_1400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sercom0::RegisterBlock { + Self::PTR + } +} +impl Deref for SERCOM4 { + type Target = sercom0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SERCOM4 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SERCOM4").finish() + } +} +#[doc = "Serial Communication Interface"] +pub use sercom0 as sercom4; +#[doc = "Serial Communication Interface"] +pub struct SERCOM5 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SERCOM5 {} +impl SERCOM5 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sercom0::RegisterBlock = 0x4200_1800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sercom0::RegisterBlock { + Self::PTR + } +} +impl Deref for SERCOM5 { + type Target = sercom0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SERCOM5 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SERCOM5").finish() + } +} +#[doc = "Serial Communication Interface"] +pub use sercom0 as sercom5; +#[doc = "Supply Controller"] +pub struct SUPC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SUPC {} +impl SUPC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const supc::RegisterBlock = 0x4000_1800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const supc::RegisterBlock { + Self::PTR + } +} +impl Deref for SUPC { + type Target = supc::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SUPC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SUPC").finish() + } +} +#[doc = "Supply Controller"] +pub mod supc; +#[doc = "Basic Timer Counter"] +pub struct TC0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TC0 {} +impl TC0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tc0::RegisterBlock = 0x4200_3000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tc0::RegisterBlock { + Self::PTR + } +} +impl Deref for TC0 { + type Target = tc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TC0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TC0").finish() + } +} +#[doc = "Basic Timer Counter"] +pub mod tc0; +#[doc = "Basic Timer Counter"] +pub struct TC1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TC1 {} +impl TC1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tc0::RegisterBlock = 0x4200_3400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tc0::RegisterBlock { + Self::PTR + } +} +impl Deref for TC1 { + type Target = tc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TC1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TC1").finish() + } +} +#[doc = "Basic Timer Counter"] +pub use tc0 as tc1; +#[doc = "Basic Timer Counter"] +pub struct TC2 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TC2 {} +impl TC2 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tc0::RegisterBlock = 0x4200_3800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tc0::RegisterBlock { + Self::PTR + } +} +impl Deref for TC2 { + type Target = tc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TC2 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TC2").finish() + } +} +#[doc = "Basic Timer Counter"] +pub use tc0 as tc2; +#[doc = "Basic Timer Counter"] +pub struct TC3 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TC3 {} +impl TC3 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tc0::RegisterBlock = 0x4200_3c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tc0::RegisterBlock { + Self::PTR + } +} +impl Deref for TC3 { + type Target = tc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TC3 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TC3").finish() + } +} +#[doc = "Basic Timer Counter"] +pub use tc0 as tc3; +#[doc = "Basic Timer Counter"] +pub struct TC4 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TC4 {} +impl TC4 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tc0::RegisterBlock = 0x4200_4000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tc0::RegisterBlock { + Self::PTR + } +} +impl Deref for TC4 { + type Target = tc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TC4 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TC4").finish() + } +} +#[doc = "Basic Timer Counter"] +pub use tc0 as tc4; +#[doc = "Timer Counter Control"] +pub struct TCC0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TCC0 {} +impl TCC0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tcc0::RegisterBlock = 0x4200_2400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tcc0::RegisterBlock { + Self::PTR + } +} +impl Deref for TCC0 { + type Target = tcc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TCC0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TCC0").finish() + } +} +#[doc = "Timer Counter Control"] +pub mod tcc0; +#[doc = "Timer Counter Control"] +pub struct TCC1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TCC1 {} +impl TCC1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tcc0::RegisterBlock = 0x4200_2800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tcc0::RegisterBlock { + Self::PTR + } +} +impl Deref for TCC1 { + type Target = tcc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TCC1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TCC1").finish() + } +} +#[doc = "Timer Counter Control"] +pub use tcc0 as tcc1; +#[doc = "Timer Counter Control"] +pub struct TCC2 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TCC2 {} +impl TCC2 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tcc0::RegisterBlock = 0x4200_2c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tcc0::RegisterBlock { + Self::PTR + } +} +impl Deref for TCC2 { + type Target = tcc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TCC2 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TCC2").finish() + } +} +#[doc = "Timer Counter Control"] +pub use tcc0 as tcc2; +#[doc = "Temperature Sensor"] +pub struct TSENS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TSENS {} +impl TSENS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tsens::RegisterBlock = 0x4000_3000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tsens::RegisterBlock { + Self::PTR + } +} +impl Deref for TSENS { + type Target = tsens::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TSENS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TSENS").finish() + } +} +#[doc = "Temperature Sensor"] +pub mod tsens; +#[doc = "Watchdog Timer"] +pub struct WDT { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for WDT {} +impl WDT { + #[doc = r"Pointer to the register block"] + pub const PTR: *const wdt::RegisterBlock = 0x4000_2000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const wdt::RegisterBlock { + Self::PTR + } +} +impl Deref for WDT { + type Target = wdt::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for WDT { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("WDT").finish() + } +} +#[doc = "Watchdog Timer"] +pub mod wdt; +#[doc = "System timer"] +pub struct SYSTICK { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SYSTICK {} +impl SYSTICK { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sys_tick::RegisterBlock = 0xe000_e010 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sys_tick::RegisterBlock { + Self::PTR + } +} +impl Deref for SYSTICK { + type Target = sys_tick::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SYSTICK { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SYSTICK").finish() + } +} +#[doc = "System timer"] +pub mod sys_tick; +#[doc = "System Control Registers"] +pub struct SYSTEMCONTROL { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SYSTEMCONTROL {} +impl SYSTEMCONTROL { + #[doc = r"Pointer to the register block"] + pub const PTR: *const system_control::RegisterBlock = 0xe000_e000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const system_control::RegisterBlock { + Self::PTR + } +} +impl Deref for SYSTEMCONTROL { + type Target = system_control::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SYSTEMCONTROL { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SYSTEMCONTROL").finish() + } +} +#[doc = "System Control Registers"] +pub mod system_control; +#[no_mangle] +static mut DEVICE_PERIPHERALS: bool = false; +#[doc = r"All the peripherals"] +#[allow(non_snake_case)] +pub struct Peripherals { + #[doc = "AC"] + pub AC: AC, + #[doc = "ADC0"] + pub ADC0: ADC0, + #[doc = "ADC1"] + pub ADC1: ADC1, + #[doc = "CAN0"] + pub CAN0: CAN0, + #[doc = "CAN1"] + pub CAN1: CAN1, + #[doc = "CCL"] + pub CCL: CCL, + #[doc = "DAC"] + pub DAC: DAC, + #[doc = "DIVAS"] + pub DIVAS: DIVAS, + #[doc = "DMAC"] + pub DMAC: DMAC, + #[doc = "DSU"] + pub DSU: DSU, + #[doc = "EIC"] + pub EIC: EIC, + #[doc = "EVSYS"] + pub EVSYS: EVSYS, + #[doc = "FREQM"] + pub FREQM: FREQM, + #[doc = "GCLK"] + pub GCLK: GCLK, + #[doc = "HMATRIXHS"] + pub HMATRIXHS: HMATRIXHS, + #[doc = "MCLK"] + pub MCLK: MCLK, + #[doc = "MTB"] + pub MTB: MTB, + #[doc = "NVMCTRL"] + pub NVMCTRL: NVMCTRL, + #[doc = "OSCCTRL"] + pub OSCCTRL: OSCCTRL, + #[doc = "OSC32KCTRL"] + pub OSC32KCTRL: OSC32KCTRL, + #[doc = "PAC"] + pub PAC: PAC, + #[doc = "PM"] + pub PM: PM, + #[doc = "PORT"] + pub PORT: PORT, + #[doc = "PORT_IOBUS"] + pub PORT_IOBUS: PORT_IOBUS, + #[doc = "RSTC"] + pub RSTC: RSTC, + #[doc = "RTC"] + pub RTC: RTC, + #[doc = "SDADC"] + pub SDADC: SDADC, + #[doc = "SERCOM0"] + pub SERCOM0: SERCOM0, + #[doc = "SERCOM1"] + pub SERCOM1: SERCOM1, + #[doc = "SERCOM2"] + pub SERCOM2: SERCOM2, + #[doc = "SERCOM3"] + pub SERCOM3: SERCOM3, + #[doc = "SERCOM4"] + pub SERCOM4: SERCOM4, + #[doc = "SERCOM5"] + pub SERCOM5: SERCOM5, + #[doc = "SUPC"] + pub SUPC: SUPC, + #[doc = "TC0"] + pub TC0: TC0, + #[doc = "TC1"] + pub TC1: TC1, + #[doc = "TC2"] + pub TC2: TC2, + #[doc = "TC3"] + pub TC3: TC3, + #[doc = "TC4"] + pub TC4: TC4, + #[doc = "TCC0"] + pub TCC0: TCC0, + #[doc = "TCC1"] + pub TCC1: TCC1, + #[doc = "TCC2"] + pub TCC2: TCC2, + #[doc = "TSENS"] + pub TSENS: TSENS, + #[doc = "WDT"] + pub WDT: WDT, + #[doc = "SYSTICK"] + pub SYSTICK: SYSTICK, + #[doc = "SYSTEMCONTROL"] + pub SYSTEMCONTROL: SYSTEMCONTROL, +} +impl Peripherals { + #[doc = r"Returns all the peripherals *once*"] + #[inline] + pub fn take() -> Option { + cortex_m::interrupt::free(|_| { + if unsafe { DEVICE_PERIPHERALS } { + None + } else { + Some(unsafe { Peripherals::steal() }) + } + }) + } + #[doc = r"Unchecked version of `Peripherals::take`"] + #[inline] + pub unsafe fn steal() -> Self { + DEVICE_PERIPHERALS = true; + Peripherals { + AC: AC { + _marker: PhantomData, + }, + ADC0: ADC0 { + _marker: PhantomData, + }, + ADC1: ADC1 { + _marker: PhantomData, + }, + CAN0: CAN0 { + _marker: PhantomData, + }, + CAN1: CAN1 { + _marker: PhantomData, + }, + CCL: CCL { + _marker: PhantomData, + }, + DAC: DAC { + _marker: PhantomData, + }, + DIVAS: DIVAS { + _marker: PhantomData, + }, + DMAC: DMAC { + _marker: PhantomData, + }, + DSU: DSU { + _marker: PhantomData, + }, + EIC: EIC { + _marker: PhantomData, + }, + EVSYS: EVSYS { + _marker: PhantomData, + }, + FREQM: FREQM { + _marker: PhantomData, + }, + GCLK: GCLK { + _marker: PhantomData, + }, + HMATRIXHS: HMATRIXHS { + _marker: PhantomData, + }, + MCLK: MCLK { + _marker: PhantomData, + }, + MTB: MTB { + _marker: PhantomData, + }, + NVMCTRL: NVMCTRL { + _marker: PhantomData, + }, + OSCCTRL: OSCCTRL { + _marker: PhantomData, + }, + OSC32KCTRL: OSC32KCTRL { + _marker: PhantomData, + }, + PAC: PAC { + _marker: PhantomData, + }, + PM: PM { + _marker: PhantomData, + }, + PORT: PORT { + _marker: PhantomData, + }, + PORT_IOBUS: PORT_IOBUS { + _marker: PhantomData, + }, + RSTC: RSTC { + _marker: PhantomData, + }, + RTC: RTC { + _marker: PhantomData, + }, + SDADC: SDADC { + _marker: PhantomData, + }, + SERCOM0: SERCOM0 { + _marker: PhantomData, + }, + SERCOM1: SERCOM1 { + _marker: PhantomData, + }, + SERCOM2: SERCOM2 { + _marker: PhantomData, + }, + SERCOM3: SERCOM3 { + _marker: PhantomData, + }, + SERCOM4: SERCOM4 { + _marker: PhantomData, + }, + SERCOM5: SERCOM5 { + _marker: PhantomData, + }, + SUPC: SUPC { + _marker: PhantomData, + }, + TC0: TC0 { + _marker: PhantomData, + }, + TC1: TC1 { + _marker: PhantomData, + }, + TC2: TC2 { + _marker: PhantomData, + }, + TC3: TC3 { + _marker: PhantomData, + }, + TC4: TC4 { + _marker: PhantomData, + }, + TCC0: TCC0 { + _marker: PhantomData, + }, + TCC1: TCC1 { + _marker: PhantomData, + }, + TCC2: TCC2 { + _marker: PhantomData, + }, + TSENS: TSENS { + _marker: PhantomData, + }, + WDT: WDT { + _marker: PhantomData, + }, + SYSTICK: SYSTICK { + _marker: PhantomData, + }, + SYSTEMCONTROL: SYSTEMCONTROL { + _marker: PhantomData, + }, + } + } +} diff --git a/pac/atsamc21g/src/mclk.rs b/pac/atsamc21g/src/mclk.rs new file mode 100644 index 000000000000..fc7efe3a584e --- /dev/null +++ b/pac/atsamc21g/src/mclk.rs @@ -0,0 +1,54 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved0: [u8; 0x01], + #[doc = "0x01 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x02 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x03 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x04 - CPU Clock Division"] + pub cpudiv: crate::Reg, + _reserved4: [u8; 0x0b], + #[doc = "0x10 - AHB Mask"] + pub ahbmask: crate::Reg, + #[doc = "0x14 - APBA Mask"] + pub apbamask: crate::Reg, + #[doc = "0x18 - APBB Mask"] + pub apbbmask: crate::Reg, + #[doc = "0x1c - APBC Mask"] + pub apbcmask: crate::Reg, +} +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "CPUDIV register accessor: an alias for `Reg`"] +pub type CPUDIV = crate::Reg; +#[doc = "CPU Clock Division"] +pub mod cpudiv; +#[doc = "AHBMASK register accessor: an alias for `Reg`"] +pub type AHBMASK = crate::Reg; +#[doc = "AHB Mask"] +pub mod ahbmask; +#[doc = "APBAMASK register accessor: an alias for `Reg`"] +pub type APBAMASK = crate::Reg; +#[doc = "APBA Mask"] +pub mod apbamask; +#[doc = "APBBMASK register accessor: an alias for `Reg`"] +pub type APBBMASK = crate::Reg; +#[doc = "APBB Mask"] +pub mod apbbmask; +#[doc = "APBCMASK register accessor: an alias for `Reg`"] +pub type APBCMASK = crate::Reg; +#[doc = "APBC Mask"] +pub mod apbcmask; diff --git a/pac/atsamc21g/src/mclk/ahbmask.rs b/pac/atsamc21g/src/mclk/ahbmask.rs new file mode 100644 index 000000000000..1e21340e0b11 --- /dev/null +++ b/pac/atsamc21g/src/mclk/ahbmask.rs @@ -0,0 +1,677 @@ +#[doc = "Register `AHBMASK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `AHBMASK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `HPB0_` reader - HPB0 AHB Clock Mask"] +pub struct HPB0__R(crate::FieldReader); +impl HPB0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HPB0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HPB0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HPB0_` writer - HPB0 AHB Clock Mask"] +pub struct HPB0__W<'a> { + w: &'a mut W, +} +impl<'a> HPB0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `HPB1_` reader - HPB1 AHB Clock Mask"] +pub struct HPB1__R(crate::FieldReader); +impl HPB1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HPB1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HPB1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HPB1_` writer - HPB1 AHB Clock Mask"] +pub struct HPB1__W<'a> { + w: &'a mut W, +} +impl<'a> HPB1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `HPB2_` reader - HPB2 AHB Clock Mask"] +pub struct HPB2__R(crate::FieldReader); +impl HPB2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HPB2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HPB2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HPB2_` writer - HPB2 AHB Clock Mask"] +pub struct HPB2__W<'a> { + w: &'a mut W, +} +impl<'a> HPB2__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `DSU_` reader - DSU AHB Clock Mask"] +pub struct DSU__R(crate::FieldReader); +impl DSU__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DSU__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DSU__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DSU_` writer - DSU AHB Clock Mask"] +pub struct DSU__W<'a> { + w: &'a mut W, +} +impl<'a> DSU__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `HMATRIXHS_` reader - HMATRIXHS AHB Clock Mask"] +pub struct HMATRIXHS__R(crate::FieldReader); +impl HMATRIXHS__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HMATRIXHS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HMATRIXHS__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HMATRIXHS_` writer - HMATRIXHS AHB Clock Mask"] +pub struct HMATRIXHS__W<'a> { + w: &'a mut W, +} +impl<'a> HMATRIXHS__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `NVMCTRL_` reader - NVMCTRL AHB Clock Mask"] +pub struct NVMCTRL__R(crate::FieldReader); +impl NVMCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NVMCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NVMCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NVMCTRL_` writer - NVMCTRL AHB Clock Mask"] +pub struct NVMCTRL__W<'a> { + w: &'a mut W, +} +impl<'a> NVMCTRL__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `HSRAM_` reader - HSRAM AHB Clock Mask"] +pub struct HSRAM__R(crate::FieldReader); +impl HSRAM__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HSRAM__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HSRAM__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HSRAM_` writer - HSRAM AHB Clock Mask"] +pub struct HSRAM__W<'a> { + w: &'a mut W, +} +impl<'a> HSRAM__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `DMAC_` reader - DMAC AHB Clock Mask"] +pub struct DMAC__R(crate::FieldReader); +impl DMAC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DMAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DMAC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DMAC_` writer - DMAC AHB Clock Mask"] +pub struct DMAC__W<'a> { + w: &'a mut W, +} +impl<'a> DMAC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CAN0_` reader - CAN0 AHB Clock Mask"] +pub struct CAN0__R(crate::FieldReader); +impl CAN0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CAN0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CAN0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAN0_` writer - CAN0 AHB Clock Mask"] +pub struct CAN0__W<'a> { + w: &'a mut W, +} +impl<'a> CAN0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `CAN1_` reader - CAN1 AHB Clock Mask"] +pub struct CAN1__R(crate::FieldReader); +impl CAN1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CAN1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CAN1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAN1_` writer - CAN1 AHB Clock Mask"] +pub struct CAN1__W<'a> { + w: &'a mut W, +} +impl<'a> CAN1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `PAC_` reader - PAC AHB Clock Mask"] +pub struct PAC__R(crate::FieldReader); +impl PAC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PAC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PAC_` writer - PAC AHB Clock Mask"] +pub struct PAC__W<'a> { + w: &'a mut W, +} +impl<'a> PAC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `NVMCTRL_PICACHU_` reader - NVMCTRL_PICACHU AHB Clock Mask"] +pub struct NVMCTRL_PICACHU__R(crate::FieldReader); +impl NVMCTRL_PICACHU__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NVMCTRL_PICACHU__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NVMCTRL_PICACHU__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NVMCTRL_PICACHU_` writer - NVMCTRL_PICACHU AHB Clock Mask"] +pub struct NVMCTRL_PICACHU__W<'a> { + w: &'a mut W, +} +impl<'a> NVMCTRL_PICACHU__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `DIVAS_` reader - DIVAS AHB Clock Mask"] +pub struct DIVAS__R(crate::FieldReader); +impl DIVAS__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIVAS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIVAS__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIVAS_` writer - DIVAS AHB Clock Mask"] +pub struct DIVAS__W<'a> { + w: &'a mut W, +} +impl<'a> DIVAS__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +impl R { + #[doc = "Bit 0 - HPB0 AHB Clock Mask"] + #[inline(always)] + pub fn hpb0_(&self) -> HPB0__R { + HPB0__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - HPB1 AHB Clock Mask"] + #[inline(always)] + pub fn hpb1_(&self) -> HPB1__R { + HPB1__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - HPB2 AHB Clock Mask"] + #[inline(always)] + pub fn hpb2_(&self) -> HPB2__R { + HPB2__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - DSU AHB Clock Mask"] + #[inline(always)] + pub fn dsu_(&self) -> DSU__R { + DSU__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - HMATRIXHS AHB Clock Mask"] + #[inline(always)] + pub fn hmatrixhs_(&self) -> HMATRIXHS__R { + HMATRIXHS__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - NVMCTRL AHB Clock Mask"] + #[inline(always)] + pub fn nvmctrl_(&self) -> NVMCTRL__R { + NVMCTRL__R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - HSRAM AHB Clock Mask"] + #[inline(always)] + pub fn hsram_(&self) -> HSRAM__R { + HSRAM__R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - DMAC AHB Clock Mask"] + #[inline(always)] + pub fn dmac_(&self) -> DMAC__R { + DMAC__R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - CAN0 AHB Clock Mask"] + #[inline(always)] + pub fn can0_(&self) -> CAN0__R { + CAN0__R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - CAN1 AHB Clock Mask"] + #[inline(always)] + pub fn can1_(&self) -> CAN1__R { + CAN1__R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - PAC AHB Clock Mask"] + #[inline(always)] + pub fn pac_(&self) -> PAC__R { + PAC__R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - NVMCTRL_PICACHU AHB Clock Mask"] + #[inline(always)] + pub fn nvmctrl_picachu_(&self) -> NVMCTRL_PICACHU__R { + NVMCTRL_PICACHU__R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - DIVAS AHB Clock Mask"] + #[inline(always)] + pub fn divas_(&self) -> DIVAS__R { + DIVAS__R::new(((self.bits >> 12) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - HPB0 AHB Clock Mask"] + #[inline(always)] + pub fn hpb0_(&mut self) -> HPB0__W { + HPB0__W { w: self } + } + #[doc = "Bit 1 - HPB1 AHB Clock Mask"] + #[inline(always)] + pub fn hpb1_(&mut self) -> HPB1__W { + HPB1__W { w: self } + } + #[doc = "Bit 2 - HPB2 AHB Clock Mask"] + #[inline(always)] + pub fn hpb2_(&mut self) -> HPB2__W { + HPB2__W { w: self } + } + #[doc = "Bit 3 - DSU AHB Clock Mask"] + #[inline(always)] + pub fn dsu_(&mut self) -> DSU__W { + DSU__W { w: self } + } + #[doc = "Bit 4 - HMATRIXHS AHB Clock Mask"] + #[inline(always)] + pub fn hmatrixhs_(&mut self) -> HMATRIXHS__W { + HMATRIXHS__W { w: self } + } + #[doc = "Bit 5 - NVMCTRL AHB Clock Mask"] + #[inline(always)] + pub fn nvmctrl_(&mut self) -> NVMCTRL__W { + NVMCTRL__W { w: self } + } + #[doc = "Bit 6 - HSRAM AHB Clock Mask"] + #[inline(always)] + pub fn hsram_(&mut self) -> HSRAM__W { + HSRAM__W { w: self } + } + #[doc = "Bit 7 - DMAC AHB Clock Mask"] + #[inline(always)] + pub fn dmac_(&mut self) -> DMAC__W { + DMAC__W { w: self } + } + #[doc = "Bit 8 - CAN0 AHB Clock Mask"] + #[inline(always)] + pub fn can0_(&mut self) -> CAN0__W { + CAN0__W { w: self } + } + #[doc = "Bit 9 - CAN1 AHB Clock Mask"] + #[inline(always)] + pub fn can1_(&mut self) -> CAN1__W { + CAN1__W { w: self } + } + #[doc = "Bit 10 - PAC AHB Clock Mask"] + #[inline(always)] + pub fn pac_(&mut self) -> PAC__W { + PAC__W { w: self } + } + #[doc = "Bit 11 - NVMCTRL_PICACHU AHB Clock Mask"] + #[inline(always)] + pub fn nvmctrl_picachu_(&mut self) -> NVMCTRL_PICACHU__W { + NVMCTRL_PICACHU__W { w: self } + } + #[doc = "Bit 12 - DIVAS AHB Clock Mask"] + #[inline(always)] + pub fn divas_(&mut self) -> DIVAS__W { + DIVAS__W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "AHB Mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ahbmask](index.html) module"] +pub struct AHBMASK_SPEC; +impl crate::RegisterSpec for AHBMASK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ahbmask::R](R) reader structure"] +impl crate::Readable for AHBMASK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ahbmask::W](W) writer structure"] +impl crate::Writable for AHBMASK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets AHBMASK to value 0x1cff"] +impl crate::Resettable for AHBMASK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x1cff + } +} diff --git a/pac/atsamc21g/src/mclk/apbamask.rs b/pac/atsamc21g/src/mclk/apbamask.rs new file mode 100644 index 000000000000..144b1163d5cb --- /dev/null +++ b/pac/atsamc21g/src/mclk/apbamask.rs @@ -0,0 +1,677 @@ +#[doc = "Register `APBAMASK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `APBAMASK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PAC_` reader - PAC APB Clock Enable"] +pub struct PAC__R(crate::FieldReader); +impl PAC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PAC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PAC_` writer - PAC APB Clock Enable"] +pub struct PAC__W<'a> { + w: &'a mut W, +} +impl<'a> PAC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `PM_` reader - PM APB Clock Enable"] +pub struct PM__R(crate::FieldReader); +impl PM__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PM__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PM__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PM_` writer - PM APB Clock Enable"] +pub struct PM__W<'a> { + w: &'a mut W, +} +impl<'a> PM__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MCLK_` reader - MCLK APB Clock Enable"] +pub struct MCLK__R(crate::FieldReader); +impl MCLK__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCLK__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCLK__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCLK_` writer - MCLK APB Clock Enable"] +pub struct MCLK__W<'a> { + w: &'a mut W, +} +impl<'a> MCLK__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RSTC_` reader - RSTC APB Clock Enable"] +pub struct RSTC__R(crate::FieldReader); +impl RSTC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RSTC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RSTC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RSTC_` writer - RSTC APB Clock Enable"] +pub struct RSTC__W<'a> { + w: &'a mut W, +} +impl<'a> RSTC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `OSCCTRL_` reader - OSCCTRL APB Clock Enable"] +pub struct OSCCTRL__R(crate::FieldReader); +impl OSCCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSCCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSCCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSCCTRL_` writer - OSCCTRL APB Clock Enable"] +pub struct OSCCTRL__W<'a> { + w: &'a mut W, +} +impl<'a> OSCCTRL__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `OSC32KCTRL_` reader - OSC32KCTRL APB Clock Enable"] +pub struct OSC32KCTRL__R(crate::FieldReader); +impl OSC32KCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC32KCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC32KCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC32KCTRL_` writer - OSC32KCTRL APB Clock Enable"] +pub struct OSC32KCTRL__W<'a> { + w: &'a mut W, +} +impl<'a> OSC32KCTRL__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `SUPC_` reader - SUPC APB Clock Enable"] +pub struct SUPC__R(crate::FieldReader); +impl SUPC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SUPC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SUPC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SUPC_` writer - SUPC APB Clock Enable"] +pub struct SUPC__W<'a> { + w: &'a mut W, +} +impl<'a> SUPC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `GCLK_` reader - GCLK APB Clock Enable"] +pub struct GCLK__R(crate::FieldReader); +impl GCLK__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GCLK__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GCLK__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GCLK_` writer - GCLK APB Clock Enable"] +pub struct GCLK__W<'a> { + w: &'a mut W, +} +impl<'a> GCLK__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `WDT_` reader - WDT APB Clock Enable"] +pub struct WDT__R(crate::FieldReader); +impl WDT__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WDT__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WDT__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WDT_` writer - WDT APB Clock Enable"] +pub struct WDT__W<'a> { + w: &'a mut W, +} +impl<'a> WDT__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `RTC_` reader - RTC APB Clock Enable"] +pub struct RTC__R(crate::FieldReader); +impl RTC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RTC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RTC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RTC_` writer - RTC APB Clock Enable"] +pub struct RTC__W<'a> { + w: &'a mut W, +} +impl<'a> RTC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `EIC_` reader - EIC APB Clock Enable"] +pub struct EIC__R(crate::FieldReader); +impl EIC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EIC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EIC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EIC_` writer - EIC APB Clock Enable"] +pub struct EIC__W<'a> { + w: &'a mut W, +} +impl<'a> EIC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `FREQM_` reader - FREQM APB Clock Enable"] +pub struct FREQM__R(crate::FieldReader); +impl FREQM__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FREQM__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FREQM__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FREQM_` writer - FREQM APB Clock Enable"] +pub struct FREQM__W<'a> { + w: &'a mut W, +} +impl<'a> FREQM__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `TSENS_` reader - TSENS APB Clock Enable"] +pub struct TSENS__R(crate::FieldReader); +impl TSENS__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSENS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSENS__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSENS_` writer - TSENS APB Clock Enable"] +pub struct TSENS__W<'a> { + w: &'a mut W, +} +impl<'a> TSENS__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +impl R { + #[doc = "Bit 0 - PAC APB Clock Enable"] + #[inline(always)] + pub fn pac_(&self) -> PAC__R { + PAC__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - PM APB Clock Enable"] + #[inline(always)] + pub fn pm_(&self) -> PM__R { + PM__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - MCLK APB Clock Enable"] + #[inline(always)] + pub fn mclk_(&self) -> MCLK__R { + MCLK__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - RSTC APB Clock Enable"] + #[inline(always)] + pub fn rstc_(&self) -> RSTC__R { + RSTC__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - OSCCTRL APB Clock Enable"] + #[inline(always)] + pub fn oscctrl_(&self) -> OSCCTRL__R { + OSCCTRL__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - OSC32KCTRL APB Clock Enable"] + #[inline(always)] + pub fn osc32kctrl_(&self) -> OSC32KCTRL__R { + OSC32KCTRL__R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - SUPC APB Clock Enable"] + #[inline(always)] + pub fn supc_(&self) -> SUPC__R { + SUPC__R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - GCLK APB Clock Enable"] + #[inline(always)] + pub fn gclk_(&self) -> GCLK__R { + GCLK__R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - WDT APB Clock Enable"] + #[inline(always)] + pub fn wdt_(&self) -> WDT__R { + WDT__R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - RTC APB Clock Enable"] + #[inline(always)] + pub fn rtc_(&self) -> RTC__R { + RTC__R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - EIC APB Clock Enable"] + #[inline(always)] + pub fn eic_(&self) -> EIC__R { + EIC__R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - FREQM APB Clock Enable"] + #[inline(always)] + pub fn freqm_(&self) -> FREQM__R { + FREQM__R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - TSENS APB Clock Enable"] + #[inline(always)] + pub fn tsens_(&self) -> TSENS__R { + TSENS__R::new(((self.bits >> 12) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - PAC APB Clock Enable"] + #[inline(always)] + pub fn pac_(&mut self) -> PAC__W { + PAC__W { w: self } + } + #[doc = "Bit 1 - PM APB Clock Enable"] + #[inline(always)] + pub fn pm_(&mut self) -> PM__W { + PM__W { w: self } + } + #[doc = "Bit 2 - MCLK APB Clock Enable"] + #[inline(always)] + pub fn mclk_(&mut self) -> MCLK__W { + MCLK__W { w: self } + } + #[doc = "Bit 3 - RSTC APB Clock Enable"] + #[inline(always)] + pub fn rstc_(&mut self) -> RSTC__W { + RSTC__W { w: self } + } + #[doc = "Bit 4 - OSCCTRL APB Clock Enable"] + #[inline(always)] + pub fn oscctrl_(&mut self) -> OSCCTRL__W { + OSCCTRL__W { w: self } + } + #[doc = "Bit 5 - OSC32KCTRL APB Clock Enable"] + #[inline(always)] + pub fn osc32kctrl_(&mut self) -> OSC32KCTRL__W { + OSC32KCTRL__W { w: self } + } + #[doc = "Bit 6 - SUPC APB Clock Enable"] + #[inline(always)] + pub fn supc_(&mut self) -> SUPC__W { + SUPC__W { w: self } + } + #[doc = "Bit 7 - GCLK APB Clock Enable"] + #[inline(always)] + pub fn gclk_(&mut self) -> GCLK__W { + GCLK__W { w: self } + } + #[doc = "Bit 8 - WDT APB Clock Enable"] + #[inline(always)] + pub fn wdt_(&mut self) -> WDT__W { + WDT__W { w: self } + } + #[doc = "Bit 9 - RTC APB Clock Enable"] + #[inline(always)] + pub fn rtc_(&mut self) -> RTC__W { + RTC__W { w: self } + } + #[doc = "Bit 10 - EIC APB Clock Enable"] + #[inline(always)] + pub fn eic_(&mut self) -> EIC__W { + EIC__W { w: self } + } + #[doc = "Bit 11 - FREQM APB Clock Enable"] + #[inline(always)] + pub fn freqm_(&mut self) -> FREQM__W { + FREQM__W { w: self } + } + #[doc = "Bit 12 - TSENS APB Clock Enable"] + #[inline(always)] + pub fn tsens_(&mut self) -> TSENS__W { + TSENS__W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "APBA Mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [apbamask](index.html) module"] +pub struct APBAMASK_SPEC; +impl crate::RegisterSpec for APBAMASK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [apbamask::R](R) reader structure"] +impl crate::Readable for APBAMASK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [apbamask::W](W) writer structure"] +impl crate::Writable for APBAMASK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets APBAMASK to value 0x0fff"] +impl crate::Resettable for APBAMASK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0fff + } +} diff --git a/pac/atsamc21g/src/mclk/apbbmask.rs b/pac/atsamc21g/src/mclk/apbbmask.rs new file mode 100644 index 000000000000..e1ec6b1f2323 --- /dev/null +++ b/pac/atsamc21g/src/mclk/apbbmask.rs @@ -0,0 +1,254 @@ +#[doc = "Register `APBBMASK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `APBBMASK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PORT_` reader - PORT APB Clock Enable"] +pub struct PORT__R(crate::FieldReader); +impl PORT__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PORT__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PORT__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PORT_` writer - PORT APB Clock Enable"] +pub struct PORT__W<'a> { + w: &'a mut W, +} +impl<'a> PORT__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `DSU_` reader - DSU APB Clock Enable"] +pub struct DSU__R(crate::FieldReader); +impl DSU__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DSU__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DSU__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DSU_` writer - DSU APB Clock Enable"] +pub struct DSU__W<'a> { + w: &'a mut W, +} +impl<'a> DSU__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `NVMCTRL_` reader - NVMCTRL APB Clock Enable"] +pub struct NVMCTRL__R(crate::FieldReader); +impl NVMCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NVMCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NVMCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NVMCTRL_` writer - NVMCTRL APB Clock Enable"] +pub struct NVMCTRL__W<'a> { + w: &'a mut W, +} +impl<'a> NVMCTRL__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `HMATRIXHS_` reader - HMATRIXHS APB Clock Enable"] +pub struct HMATRIXHS__R(crate::FieldReader); +impl HMATRIXHS__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HMATRIXHS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HMATRIXHS__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HMATRIXHS_` writer - HMATRIXHS APB Clock Enable"] +pub struct HMATRIXHS__W<'a> { + w: &'a mut W, +} +impl<'a> HMATRIXHS__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - PORT APB Clock Enable"] + #[inline(always)] + pub fn port_(&self) -> PORT__R { + PORT__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - DSU APB Clock Enable"] + #[inline(always)] + pub fn dsu_(&self) -> DSU__R { + DSU__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - NVMCTRL APB Clock Enable"] + #[inline(always)] + pub fn nvmctrl_(&self) -> NVMCTRL__R { + NVMCTRL__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 5 - HMATRIXHS APB Clock Enable"] + #[inline(always)] + pub fn hmatrixhs_(&self) -> HMATRIXHS__R { + HMATRIXHS__R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - PORT APB Clock Enable"] + #[inline(always)] + pub fn port_(&mut self) -> PORT__W { + PORT__W { w: self } + } + #[doc = "Bit 1 - DSU APB Clock Enable"] + #[inline(always)] + pub fn dsu_(&mut self) -> DSU__W { + DSU__W { w: self } + } + #[doc = "Bit 2 - NVMCTRL APB Clock Enable"] + #[inline(always)] + pub fn nvmctrl_(&mut self) -> NVMCTRL__W { + NVMCTRL__W { w: self } + } + #[doc = "Bit 5 - HMATRIXHS APB Clock Enable"] + #[inline(always)] + pub fn hmatrixhs_(&mut self) -> HMATRIXHS__W { + HMATRIXHS__W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "APBB Mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [apbbmask](index.html) module"] +pub struct APBBMASK_SPEC; +impl crate::RegisterSpec for APBBMASK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [apbbmask::R](R) reader structure"] +impl crate::Readable for APBBMASK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [apbbmask::W](W) writer structure"] +impl crate::Writable for APBBMASK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets APBBMASK to value 0x07"] +impl crate::Resettable for APBBMASK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x07 + } +} diff --git a/pac/atsamc21g/src/mclk/apbcmask.rs b/pac/atsamc21g/src/mclk/apbcmask.rs new file mode 100644 index 000000000000..04e63311c88e --- /dev/null +++ b/pac/atsamc21g/src/mclk/apbcmask.rs @@ -0,0 +1,1100 @@ +#[doc = "Register `APBCMASK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `APBCMASK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVSYS_` reader - EVSYS APB Clock Enable"] +pub struct EVSYS__R(crate::FieldReader); +impl EVSYS__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVSYS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVSYS__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVSYS_` writer - EVSYS APB Clock Enable"] +pub struct EVSYS__W<'a> { + w: &'a mut W, +} +impl<'a> EVSYS__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `SERCOM0_` reader - SERCOM0 APB Clock Enable"] +pub struct SERCOM0__R(crate::FieldReader); +impl SERCOM0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM0_` writer - SERCOM0 APB Clock Enable"] +pub struct SERCOM0__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SERCOM1_` reader - SERCOM1 APB Clock Enable"] +pub struct SERCOM1__R(crate::FieldReader); +impl SERCOM1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM1_` writer - SERCOM1 APB Clock Enable"] +pub struct SERCOM1__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SERCOM2_` reader - SERCOM2 APB Clock Enable"] +pub struct SERCOM2__R(crate::FieldReader); +impl SERCOM2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM2_` writer - SERCOM2 APB Clock Enable"] +pub struct SERCOM2__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM2__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `SERCOM3_` reader - SERCOM3 APB Clock Enable"] +pub struct SERCOM3__R(crate::FieldReader); +impl SERCOM3__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM3__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM3__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM3_` writer - SERCOM3 APB Clock Enable"] +pub struct SERCOM3__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM3__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `SERCOM4_` reader - SERCOM4 APB Clock Enable"] +pub struct SERCOM4__R(crate::FieldReader); +impl SERCOM4__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM4__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM4__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM4_` writer - SERCOM4 APB Clock Enable"] +pub struct SERCOM4__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM4__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `SERCOM5_` reader - SERCOM5 APB Clock Enable"] +pub struct SERCOM5__R(crate::FieldReader); +impl SERCOM5__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM5__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM5__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM5_` writer - SERCOM5 APB Clock Enable"] +pub struct SERCOM5__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM5__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `TCC0_` reader - TCC0 APB Clock Enable"] +pub struct TCC0__R(crate::FieldReader); +impl TCC0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCC0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCC0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCC0_` writer - TCC0 APB Clock Enable"] +pub struct TCC0__W<'a> { + w: &'a mut W, +} +impl<'a> TCC0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `TCC1_` reader - TCC1 APB Clock Enable"] +pub struct TCC1__R(crate::FieldReader); +impl TCC1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCC1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCC1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCC1_` writer - TCC1 APB Clock Enable"] +pub struct TCC1__W<'a> { + w: &'a mut W, +} +impl<'a> TCC1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `TCC2_` reader - TCC2 APB Clock Enable"] +pub struct TCC2__R(crate::FieldReader); +impl TCC2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCC2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCC2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCC2_` writer - TCC2 APB Clock Enable"] +pub struct TCC2__W<'a> { + w: &'a mut W, +} +impl<'a> TCC2__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `TC0_` reader - TC0 APB Clock Enable"] +pub struct TC0__R(crate::FieldReader); +impl TC0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC0_` writer - TC0 APB Clock Enable"] +pub struct TC0__W<'a> { + w: &'a mut W, +} +impl<'a> TC0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `TC1_` reader - TC1 APB Clock Enable"] +pub struct TC1__R(crate::FieldReader); +impl TC1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC1_` writer - TC1 APB Clock Enable"] +pub struct TC1__W<'a> { + w: &'a mut W, +} +impl<'a> TC1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `TC2_` reader - TC2 APB Clock Enable"] +pub struct TC2__R(crate::FieldReader); +impl TC2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC2_` writer - TC2 APB Clock Enable"] +pub struct TC2__W<'a> { + w: &'a mut W, +} +impl<'a> TC2__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `TC3_` reader - TC3 APB Clock Enable"] +pub struct TC3__R(crate::FieldReader); +impl TC3__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC3__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC3__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC3_` writer - TC3 APB Clock Enable"] +pub struct TC3__W<'a> { + w: &'a mut W, +} +impl<'a> TC3__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `TC4_` reader - TC4 APB Clock Enable"] +pub struct TC4__R(crate::FieldReader); +impl TC4__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC4__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC4__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC4_` writer - TC4 APB Clock Enable"] +pub struct TC4__W<'a> { + w: &'a mut W, +} +impl<'a> TC4__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `ADC0_` reader - ADC0 APB Clock Enable"] +pub struct ADC0__R(crate::FieldReader); +impl ADC0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ADC0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADC0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADC0_` writer - ADC0 APB Clock Enable"] +pub struct ADC0__W<'a> { + w: &'a mut W, +} +impl<'a> ADC0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `ADC1_` reader - ADC1 APB Clock Enable"] +pub struct ADC1__R(crate::FieldReader); +impl ADC1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ADC1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADC1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADC1_` writer - ADC1 APB Clock Enable"] +pub struct ADC1__W<'a> { + w: &'a mut W, +} +impl<'a> ADC1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `SDADC_` reader - SDADC APB Clock Enable"] +pub struct SDADC__R(crate::FieldReader); +impl SDADC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SDADC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SDADC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SDADC_` writer - SDADC APB Clock Enable"] +pub struct SDADC__W<'a> { + w: &'a mut W, +} +impl<'a> SDADC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `AC_` reader - AC APB Clock Enable"] +pub struct AC__R(crate::FieldReader); +impl AC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AC_` writer - AC APB Clock Enable"] +pub struct AC__W<'a> { + w: &'a mut W, +} +impl<'a> AC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `DAC_` reader - DAC APB Clock Enable"] +pub struct DAC__R(crate::FieldReader); +impl DAC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DAC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DAC_` writer - DAC APB Clock Enable"] +pub struct DAC__W<'a> { + w: &'a mut W, +} +impl<'a> DAC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `PTC_` reader - PTC APB Clock Enable"] +pub struct PTC__R(crate::FieldReader); +impl PTC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PTC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PTC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PTC_` writer - PTC APB Clock Enable"] +pub struct PTC__W<'a> { + w: &'a mut W, +} +impl<'a> PTC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `CCL_` reader - CCL APB Clock Enable"] +pub struct CCL__R(crate::FieldReader); +impl CCL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCL_` writer - CCL APB Clock Enable"] +pub struct CCL__W<'a> { + w: &'a mut W, +} +impl<'a> CCL__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +impl R { + #[doc = "Bit 0 - EVSYS APB Clock Enable"] + #[inline(always)] + pub fn evsys_(&self) -> EVSYS__R { + EVSYS__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM0 APB Clock Enable"] + #[inline(always)] + pub fn sercom0_(&self) -> SERCOM0__R { + SERCOM0__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - SERCOM1 APB Clock Enable"] + #[inline(always)] + pub fn sercom1_(&self) -> SERCOM1__R { + SERCOM1__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - SERCOM2 APB Clock Enable"] + #[inline(always)] + pub fn sercom2_(&self) -> SERCOM2__R { + SERCOM2__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - SERCOM3 APB Clock Enable"] + #[inline(always)] + pub fn sercom3_(&self) -> SERCOM3__R { + SERCOM3__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - SERCOM4 APB Clock Enable"] + #[inline(always)] + pub fn sercom4_(&self) -> SERCOM4__R { + SERCOM4__R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - SERCOM5 APB Clock Enable"] + #[inline(always)] + pub fn sercom5_(&self) -> SERCOM5__R { + SERCOM5__R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 9 - TCC0 APB Clock Enable"] + #[inline(always)] + pub fn tcc0_(&self) -> TCC0__R { + TCC0__R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - TCC1 APB Clock Enable"] + #[inline(always)] + pub fn tcc1_(&self) -> TCC1__R { + TCC1__R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - TCC2 APB Clock Enable"] + #[inline(always)] + pub fn tcc2_(&self) -> TCC2__R { + TCC2__R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - TC0 APB Clock Enable"] + #[inline(always)] + pub fn tc0_(&self) -> TC0__R { + TC0__R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - TC1 APB Clock Enable"] + #[inline(always)] + pub fn tc1_(&self) -> TC1__R { + TC1__R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - TC2 APB Clock Enable"] + #[inline(always)] + pub fn tc2_(&self) -> TC2__R { + TC2__R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - TC3 APB Clock Enable"] + #[inline(always)] + pub fn tc3_(&self) -> TC3__R { + TC3__R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - TC4 APB Clock Enable"] + #[inline(always)] + pub fn tc4_(&self) -> TC4__R { + TC4__R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - ADC0 APB Clock Enable"] + #[inline(always)] + pub fn adc0_(&self) -> ADC0__R { + ADC0__R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - ADC1 APB Clock Enable"] + #[inline(always)] + pub fn adc1_(&self) -> ADC1__R { + ADC1__R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - SDADC APB Clock Enable"] + #[inline(always)] + pub fn sdadc_(&self) -> SDADC__R { + SDADC__R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - AC APB Clock Enable"] + #[inline(always)] + pub fn ac_(&self) -> AC__R { + AC__R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - DAC APB Clock Enable"] + #[inline(always)] + pub fn dac_(&self) -> DAC__R { + DAC__R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - PTC APB Clock Enable"] + #[inline(always)] + pub fn ptc_(&self) -> PTC__R { + PTC__R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - CCL APB Clock Enable"] + #[inline(always)] + pub fn ccl_(&self) -> CCL__R { + CCL__R::new(((self.bits >> 23) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - EVSYS APB Clock Enable"] + #[inline(always)] + pub fn evsys_(&mut self) -> EVSYS__W { + EVSYS__W { w: self } + } + #[doc = "Bit 1 - SERCOM0 APB Clock Enable"] + #[inline(always)] + pub fn sercom0_(&mut self) -> SERCOM0__W { + SERCOM0__W { w: self } + } + #[doc = "Bit 2 - SERCOM1 APB Clock Enable"] + #[inline(always)] + pub fn sercom1_(&mut self) -> SERCOM1__W { + SERCOM1__W { w: self } + } + #[doc = "Bit 3 - SERCOM2 APB Clock Enable"] + #[inline(always)] + pub fn sercom2_(&mut self) -> SERCOM2__W { + SERCOM2__W { w: self } + } + #[doc = "Bit 4 - SERCOM3 APB Clock Enable"] + #[inline(always)] + pub fn sercom3_(&mut self) -> SERCOM3__W { + SERCOM3__W { w: self } + } + #[doc = "Bit 5 - SERCOM4 APB Clock Enable"] + #[inline(always)] + pub fn sercom4_(&mut self) -> SERCOM4__W { + SERCOM4__W { w: self } + } + #[doc = "Bit 6 - SERCOM5 APB Clock Enable"] + #[inline(always)] + pub fn sercom5_(&mut self) -> SERCOM5__W { + SERCOM5__W { w: self } + } + #[doc = "Bit 9 - TCC0 APB Clock Enable"] + #[inline(always)] + pub fn tcc0_(&mut self) -> TCC0__W { + TCC0__W { w: self } + } + #[doc = "Bit 10 - TCC1 APB Clock Enable"] + #[inline(always)] + pub fn tcc1_(&mut self) -> TCC1__W { + TCC1__W { w: self } + } + #[doc = "Bit 11 - TCC2 APB Clock Enable"] + #[inline(always)] + pub fn tcc2_(&mut self) -> TCC2__W { + TCC2__W { w: self } + } + #[doc = "Bit 12 - TC0 APB Clock Enable"] + #[inline(always)] + pub fn tc0_(&mut self) -> TC0__W { + TC0__W { w: self } + } + #[doc = "Bit 13 - TC1 APB Clock Enable"] + #[inline(always)] + pub fn tc1_(&mut self) -> TC1__W { + TC1__W { w: self } + } + #[doc = "Bit 14 - TC2 APB Clock Enable"] + #[inline(always)] + pub fn tc2_(&mut self) -> TC2__W { + TC2__W { w: self } + } + #[doc = "Bit 15 - TC3 APB Clock Enable"] + #[inline(always)] + pub fn tc3_(&mut self) -> TC3__W { + TC3__W { w: self } + } + #[doc = "Bit 16 - TC4 APB Clock Enable"] + #[inline(always)] + pub fn tc4_(&mut self) -> TC4__W { + TC4__W { w: self } + } + #[doc = "Bit 17 - ADC0 APB Clock Enable"] + #[inline(always)] + pub fn adc0_(&mut self) -> ADC0__W { + ADC0__W { w: self } + } + #[doc = "Bit 18 - ADC1 APB Clock Enable"] + #[inline(always)] + pub fn adc1_(&mut self) -> ADC1__W { + ADC1__W { w: self } + } + #[doc = "Bit 19 - SDADC APB Clock Enable"] + #[inline(always)] + pub fn sdadc_(&mut self) -> SDADC__W { + SDADC__W { w: self } + } + #[doc = "Bit 20 - AC APB Clock Enable"] + #[inline(always)] + pub fn ac_(&mut self) -> AC__W { + AC__W { w: self } + } + #[doc = "Bit 21 - DAC APB Clock Enable"] + #[inline(always)] + pub fn dac_(&mut self) -> DAC__W { + DAC__W { w: self } + } + #[doc = "Bit 22 - PTC APB Clock Enable"] + #[inline(always)] + pub fn ptc_(&mut self) -> PTC__W { + PTC__W { w: self } + } + #[doc = "Bit 23 - CCL APB Clock Enable"] + #[inline(always)] + pub fn ccl_(&mut self) -> CCL__W { + CCL__W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "APBC Mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [apbcmask](index.html) module"] +pub struct APBCMASK_SPEC; +impl crate::RegisterSpec for APBCMASK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [apbcmask::R](R) reader structure"] +impl crate::Readable for APBCMASK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [apbcmask::W](W) writer structure"] +impl crate::Writable for APBCMASK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets APBCMASK to value 0"] +impl crate::Resettable for APBCMASK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/mclk/cpudiv.rs b/pac/atsamc21g/src/mclk/cpudiv.rs new file mode 100644 index 000000000000..a21fdae21357 --- /dev/null +++ b/pac/atsamc21g/src/mclk/cpudiv.rs @@ -0,0 +1,230 @@ +#[doc = "Register `CPUDIV` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CPUDIV` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "CPU Clock Division Factor\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CPUDIV_A { + #[doc = "1: Divide by 1"] + DIV1 = 1, + #[doc = "2: Divide by 2"] + DIV2 = 2, + #[doc = "4: Divide by 4"] + DIV4 = 4, + #[doc = "8: Divide by 8"] + DIV8 = 8, + #[doc = "16: Divide by 16"] + DIV16 = 16, + #[doc = "32: Divide by 32"] + DIV32 = 32, + #[doc = "64: Divide by 64"] + DIV64 = 64, + #[doc = "128: Divide by 128"] + DIV128 = 128, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CPUDIV_A) -> Self { + variant as _ + } +} +#[doc = "Field `CPUDIV` reader - CPU Clock Division Factor"] +pub struct CPUDIV_R(crate::FieldReader); +impl CPUDIV_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CPUDIV_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 1 => Some(CPUDIV_A::DIV1), + 2 => Some(CPUDIV_A::DIV2), + 4 => Some(CPUDIV_A::DIV4), + 8 => Some(CPUDIV_A::DIV8), + 16 => Some(CPUDIV_A::DIV16), + 32 => Some(CPUDIV_A::DIV32), + 64 => Some(CPUDIV_A::DIV64), + 128 => Some(CPUDIV_A::DIV128), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == CPUDIV_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == CPUDIV_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == CPUDIV_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == CPUDIV_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == CPUDIV_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == CPUDIV_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == CPUDIV_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == CPUDIV_A::DIV128 + } +} +impl core::ops::Deref for CPUDIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPUDIV` writer - CPU Clock Division Factor"] +pub struct CPUDIV_W<'a> { + w: &'a mut W, +} +impl<'a> CPUDIV_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CPUDIV_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Divide by 1"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV1) + } + #[doc = "Divide by 2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV2) + } + #[doc = "Divide by 4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV4) + } + #[doc = "Divide by 8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV8) + } + #[doc = "Divide by 16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV16) + } + #[doc = "Divide by 32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV32) + } + #[doc = "Divide by 64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV64) + } + #[doc = "Divide by 128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV128) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - CPU Clock Division Factor"] + #[inline(always)] + pub fn cpudiv(&self) -> CPUDIV_R { + CPUDIV_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - CPU Clock Division Factor"] + #[inline(always)] + pub fn cpudiv(&mut self) -> CPUDIV_W { + CPUDIV_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CPU Clock Division\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cpudiv](index.html) module"] +pub struct CPUDIV_SPEC; +impl crate::RegisterSpec for CPUDIV_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [cpudiv::R](R) reader structure"] +impl crate::Readable for CPUDIV_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cpudiv::W](W) writer structure"] +impl crate::Writable for CPUDIV_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CPUDIV to value 0x01"] +impl crate::Resettable for CPUDIV_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pac/atsamc21g/src/mclk/intenclr.rs b/pac/atsamc21g/src/mclk/intenclr.rs new file mode 100644 index 000000000000..14feb632dbb7 --- /dev/null +++ b/pac/atsamc21g/src/mclk/intenclr.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CKRDY` reader - Clock Ready Interrupt Enable"] +pub struct CKRDY_R(crate::FieldReader); +impl CKRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CKRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CKRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CKRDY` writer - Clock Ready Interrupt Enable"] +pub struct CKRDY_W<'a> { + w: &'a mut W, +} +impl<'a> CKRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Clock Ready Interrupt Enable"] + #[inline(always)] + pub fn ckrdy(&self) -> CKRDY_R { + CKRDY_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Clock Ready Interrupt Enable"] + #[inline(always)] + pub fn ckrdy(&mut self) -> CKRDY_W { + CKRDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/mclk/intenset.rs b/pac/atsamc21g/src/mclk/intenset.rs new file mode 100644 index 000000000000..f01fcc316d93 --- /dev/null +++ b/pac/atsamc21g/src/mclk/intenset.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CKRDY` reader - Clock Ready Interrupt Enable"] +pub struct CKRDY_R(crate::FieldReader); +impl CKRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CKRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CKRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CKRDY` writer - Clock Ready Interrupt Enable"] +pub struct CKRDY_W<'a> { + w: &'a mut W, +} +impl<'a> CKRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Clock Ready Interrupt Enable"] + #[inline(always)] + pub fn ckrdy(&self) -> CKRDY_R { + CKRDY_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Clock Ready Interrupt Enable"] + #[inline(always)] + pub fn ckrdy(&mut self) -> CKRDY_W { + CKRDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/mclk/intflag.rs b/pac/atsamc21g/src/mclk/intflag.rs new file mode 100644 index 000000000000..cf421d4ac61a --- /dev/null +++ b/pac/atsamc21g/src/mclk/intflag.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CKRDY` reader - Clock Ready"] +pub struct CKRDY_R(crate::FieldReader); +impl CKRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CKRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CKRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CKRDY` writer - Clock Ready"] +pub struct CKRDY_W<'a> { + w: &'a mut W, +} +impl<'a> CKRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Clock Ready"] + #[inline(always)] + pub fn ckrdy(&self) -> CKRDY_R { + CKRDY_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Clock Ready"] + #[inline(always)] + pub fn ckrdy(&mut self) -> CKRDY_W { + CKRDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0x01"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pac/atsamc21g/src/mtb.rs b/pac/atsamc21g/src/mtb.rs new file mode 100644 index 000000000000..01be005c0fb9 --- /dev/null +++ b/pac/atsamc21g/src/mtb.rs @@ -0,0 +1,158 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - MTB Position"] + pub position: crate::Reg, + #[doc = "0x04 - MTB Master"] + pub master: crate::Reg, + #[doc = "0x08 - MTB Flow"] + pub flow: crate::Reg, + #[doc = "0x0c - MTB Base"] + pub base: crate::Reg, + _reserved4: [u8; 0x0ef0], + #[doc = "0xf00 - MTB Integration Mode Control"] + pub itctrl: crate::Reg, + _reserved5: [u8; 0x9c], + #[doc = "0xfa0 - MTB Claim Set"] + pub claimset: crate::Reg, + #[doc = "0xfa4 - MTB Claim Clear"] + pub claimclr: crate::Reg, + _reserved7: [u8; 0x08], + #[doc = "0xfb0 - MTB Lock Access"] + pub lockaccess: crate::Reg, + #[doc = "0xfb4 - MTB Lock Status"] + pub lockstatus: crate::Reg, + #[doc = "0xfb8 - MTB Authentication Status"] + pub authstatus: crate::Reg, + #[doc = "0xfbc - MTB Device Architecture"] + pub devarch: crate::Reg, + _reserved11: [u8; 0x08], + #[doc = "0xfc8 - MTB Device Configuration"] + pub devid: crate::Reg, + #[doc = "0xfcc - MTB Device Type"] + pub devtype: crate::Reg, + #[doc = "0xfd0 - Peripheral Identification 4"] + pub pid4: crate::Reg, + #[doc = "0xfd4 - Peripheral Identification 5"] + pub pid5: crate::Reg, + #[doc = "0xfd8 - Peripheral Identification 6"] + pub pid6: crate::Reg, + #[doc = "0xfdc - Peripheral Identification 7"] + pub pid7: crate::Reg, + #[doc = "0xfe0 - Peripheral Identification 0"] + pub pid0: crate::Reg, + #[doc = "0xfe4 - Peripheral Identification 1"] + pub pid1: crate::Reg, + #[doc = "0xfe8 - Peripheral Identification 2"] + pub pid2: crate::Reg, + #[doc = "0xfec - Peripheral Identification 3"] + pub pid3: crate::Reg, + #[doc = "0xff0 - Component Identification 0"] + pub cid0: crate::Reg, + #[doc = "0xff4 - Component Identification 1"] + pub cid1: crate::Reg, + #[doc = "0xff8 - Component Identification 2"] + pub cid2: crate::Reg, + #[doc = "0xffc - Component Identification 3"] + pub cid3: crate::Reg, +} +#[doc = "POSITION register accessor: an alias for `Reg`"] +pub type POSITION = crate::Reg; +#[doc = "MTB Position"] +pub mod position; +#[doc = "MASTER register accessor: an alias for `Reg`"] +pub type MASTER = crate::Reg; +#[doc = "MTB Master"] +pub mod master; +#[doc = "FLOW register accessor: an alias for `Reg`"] +pub type FLOW = crate::Reg; +#[doc = "MTB Flow"] +pub mod flow; +#[doc = "BASE register accessor: an alias for `Reg`"] +pub type BASE = crate::Reg; +#[doc = "MTB Base"] +pub mod base; +#[doc = "ITCTRL register accessor: an alias for `Reg`"] +pub type ITCTRL = crate::Reg; +#[doc = "MTB Integration Mode Control"] +pub mod itctrl; +#[doc = "CLAIMSET register accessor: an alias for `Reg`"] +pub type CLAIMSET = crate::Reg; +#[doc = "MTB Claim Set"] +pub mod claimset; +#[doc = "CLAIMCLR register accessor: an alias for `Reg`"] +pub type CLAIMCLR = crate::Reg; +#[doc = "MTB Claim Clear"] +pub mod claimclr; +#[doc = "LOCKACCESS register accessor: an alias for `Reg`"] +pub type LOCKACCESS = crate::Reg; +#[doc = "MTB Lock Access"] +pub mod lockaccess; +#[doc = "LOCKSTATUS register accessor: an alias for `Reg`"] +pub type LOCKSTATUS = crate::Reg; +#[doc = "MTB Lock Status"] +pub mod lockstatus; +#[doc = "AUTHSTATUS register accessor: an alias for `Reg`"] +pub type AUTHSTATUS = crate::Reg; +#[doc = "MTB Authentication Status"] +pub mod authstatus; +#[doc = "DEVARCH register accessor: an alias for `Reg`"] +pub type DEVARCH = crate::Reg; +#[doc = "MTB Device Architecture"] +pub mod devarch; +#[doc = "DEVID register accessor: an alias for `Reg`"] +pub type DEVID = crate::Reg; +#[doc = "MTB Device Configuration"] +pub mod devid; +#[doc = "DEVTYPE register accessor: an alias for `Reg`"] +pub type DEVTYPE = crate::Reg; +#[doc = "MTB Device Type"] +pub mod devtype; +#[doc = "PID4 register accessor: an alias for `Reg`"] +pub type PID4 = crate::Reg; +#[doc = "Peripheral Identification 4"] +pub mod pid4; +#[doc = "PID5 register accessor: an alias for `Reg`"] +pub type PID5 = crate::Reg; +#[doc = "Peripheral Identification 5"] +pub mod pid5; +#[doc = "PID6 register accessor: an alias for `Reg`"] +pub type PID6 = crate::Reg; +#[doc = "Peripheral Identification 6"] +pub mod pid6; +#[doc = "PID7 register accessor: an alias for `Reg`"] +pub type PID7 = crate::Reg; +#[doc = "Peripheral Identification 7"] +pub mod pid7; +#[doc = "PID0 register accessor: an alias for `Reg`"] +pub type PID0 = crate::Reg; +#[doc = "Peripheral Identification 0"] +pub mod pid0; +#[doc = "PID1 register accessor: an alias for `Reg`"] +pub type PID1 = crate::Reg; +#[doc = "Peripheral Identification 1"] +pub mod pid1; +#[doc = "PID2 register accessor: an alias for `Reg`"] +pub type PID2 = crate::Reg; +#[doc = "Peripheral Identification 2"] +pub mod pid2; +#[doc = "PID3 register accessor: an alias for `Reg`"] +pub type PID3 = crate::Reg; +#[doc = "Peripheral Identification 3"] +pub mod pid3; +#[doc = "CID0 register accessor: an alias for `Reg`"] +pub type CID0 = crate::Reg; +#[doc = "Component Identification 0"] +pub mod cid0; +#[doc = "CID1 register accessor: an alias for `Reg`"] +pub type CID1 = crate::Reg; +#[doc = "Component Identification 1"] +pub mod cid1; +#[doc = "CID2 register accessor: an alias for `Reg`"] +pub type CID2 = crate::Reg; +#[doc = "Component Identification 2"] +pub mod cid2; +#[doc = "CID3 register accessor: an alias for `Reg`"] +pub type CID3 = crate::Reg; +#[doc = "Component Identification 3"] +pub mod cid3; diff --git a/pac/atsamc21g/src/mtb/authstatus.rs b/pac/atsamc21g/src/mtb/authstatus.rs new file mode 100644 index 000000000000..6fe441e0554d --- /dev/null +++ b/pac/atsamc21g/src/mtb/authstatus.rs @@ -0,0 +1,31 @@ +#[doc = "Register `AUTHSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "MTB Authentication Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [authstatus](index.html) module"] +pub struct AUTHSTATUS_SPEC; +impl crate::RegisterSpec for AUTHSTATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [authstatus::R](R) reader structure"] +impl crate::Readable for AUTHSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets AUTHSTATUS to value 0"] +impl crate::Resettable for AUTHSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/mtb/base.rs b/pac/atsamc21g/src/mtb/base.rs new file mode 100644 index 000000000000..f59b5a97a398 --- /dev/null +++ b/pac/atsamc21g/src/mtb/base.rs @@ -0,0 +1,31 @@ +#[doc = "Register `BASE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "MTB Base\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [base](index.html) module"] +pub struct BASE_SPEC; +impl crate::RegisterSpec for BASE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [base::R](R) reader structure"] +impl crate::Readable for BASE_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets BASE to value 0"] +impl crate::Resettable for BASE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/mtb/cid0.rs b/pac/atsamc21g/src/mtb/cid0.rs new file mode 100644 index 000000000000..e03bd35fa470 --- /dev/null +++ b/pac/atsamc21g/src/mtb/cid0.rs @@ -0,0 +1,31 @@ +#[doc = "Register `CID0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Component Identification 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid0](index.html) module"] +pub struct CID0_SPEC; +impl crate::RegisterSpec for CID0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid0::R](R) reader structure"] +impl crate::Readable for CID0_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID0 to value 0"] +impl crate::Resettable for CID0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/mtb/cid1.rs b/pac/atsamc21g/src/mtb/cid1.rs new file mode 100644 index 000000000000..1cafc8e0fb9a --- /dev/null +++ b/pac/atsamc21g/src/mtb/cid1.rs @@ -0,0 +1,31 @@ +#[doc = "Register `CID1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Component Identification 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid1](index.html) module"] +pub struct CID1_SPEC; +impl crate::RegisterSpec for CID1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid1::R](R) reader structure"] +impl crate::Readable for CID1_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID1 to value 0"] +impl crate::Resettable for CID1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/mtb/cid2.rs b/pac/atsamc21g/src/mtb/cid2.rs new file mode 100644 index 000000000000..6a91e4e23206 --- /dev/null +++ b/pac/atsamc21g/src/mtb/cid2.rs @@ -0,0 +1,31 @@ +#[doc = "Register `CID2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Component Identification 2\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid2](index.html) module"] +pub struct CID2_SPEC; +impl crate::RegisterSpec for CID2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid2::R](R) reader structure"] +impl crate::Readable for CID2_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID2 to value 0"] +impl crate::Resettable for CID2_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/mtb/cid3.rs b/pac/atsamc21g/src/mtb/cid3.rs new file mode 100644 index 000000000000..726290f4ffed --- /dev/null +++ b/pac/atsamc21g/src/mtb/cid3.rs @@ -0,0 +1,31 @@ +#[doc = "Register `CID3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Component Identification 3\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid3](index.html) module"] +pub struct CID3_SPEC; +impl crate::RegisterSpec for CID3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid3::R](R) reader structure"] +impl crate::Readable for CID3_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID3 to value 0"] +impl crate::Resettable for CID3_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/mtb/claimclr.rs b/pac/atsamc21g/src/mtb/claimclr.rs new file mode 100644 index 000000000000..7d0fa5d487b2 --- /dev/null +++ b/pac/atsamc21g/src/mtb/claimclr.rs @@ -0,0 +1,64 @@ +#[doc = "Register `CLAIMCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CLAIMCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MTB Claim Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [claimclr](index.html) module"] +pub struct CLAIMCLR_SPEC; +impl crate::RegisterSpec for CLAIMCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [claimclr::R](R) reader structure"] +impl crate::Readable for CLAIMCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [claimclr::W](W) writer structure"] +impl crate::Writable for CLAIMCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CLAIMCLR to value 0"] +impl crate::Resettable for CLAIMCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/mtb/claimset.rs b/pac/atsamc21g/src/mtb/claimset.rs new file mode 100644 index 000000000000..d5e8ffaa4846 --- /dev/null +++ b/pac/atsamc21g/src/mtb/claimset.rs @@ -0,0 +1,64 @@ +#[doc = "Register `CLAIMSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CLAIMSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MTB Claim Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [claimset](index.html) module"] +pub struct CLAIMSET_SPEC; +impl crate::RegisterSpec for CLAIMSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [claimset::R](R) reader structure"] +impl crate::Readable for CLAIMSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [claimset::W](W) writer structure"] +impl crate::Writable for CLAIMSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CLAIMSET to value 0"] +impl crate::Resettable for CLAIMSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/mtb/devarch.rs b/pac/atsamc21g/src/mtb/devarch.rs new file mode 100644 index 000000000000..b79480753d5e --- /dev/null +++ b/pac/atsamc21g/src/mtb/devarch.rs @@ -0,0 +1,31 @@ +#[doc = "Register `DEVARCH` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "MTB Device Architecture\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [devarch](index.html) module"] +pub struct DEVARCH_SPEC; +impl crate::RegisterSpec for DEVARCH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [devarch::R](R) reader structure"] +impl crate::Readable for DEVARCH_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DEVARCH to value 0"] +impl crate::Resettable for DEVARCH_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/mtb/devid.rs b/pac/atsamc21g/src/mtb/devid.rs new file mode 100644 index 000000000000..21c15d952032 --- /dev/null +++ b/pac/atsamc21g/src/mtb/devid.rs @@ -0,0 +1,31 @@ +#[doc = "Register `DEVID` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "MTB Device Configuration\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [devid](index.html) module"] +pub struct DEVID_SPEC; +impl crate::RegisterSpec for DEVID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [devid::R](R) reader structure"] +impl crate::Readable for DEVID_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DEVID to value 0"] +impl crate::Resettable for DEVID_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/mtb/devtype.rs b/pac/atsamc21g/src/mtb/devtype.rs new file mode 100644 index 000000000000..c00d66b98a2f --- /dev/null +++ b/pac/atsamc21g/src/mtb/devtype.rs @@ -0,0 +1,31 @@ +#[doc = "Register `DEVTYPE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "MTB Device Type\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [devtype](index.html) module"] +pub struct DEVTYPE_SPEC; +impl crate::RegisterSpec for DEVTYPE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [devtype::R](R) reader structure"] +impl crate::Readable for DEVTYPE_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DEVTYPE to value 0"] +impl crate::Resettable for DEVTYPE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/mtb/flow.rs b/pac/atsamc21g/src/mtb/flow.rs new file mode 100644 index 000000000000..1b94efdb89b8 --- /dev/null +++ b/pac/atsamc21g/src/mtb/flow.rs @@ -0,0 +1,197 @@ +#[doc = "Register `FLOW` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FLOW` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `AUTOSTOP` reader - Auto Stop Tracing"] +pub struct AUTOSTOP_R(crate::FieldReader); +impl AUTOSTOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AUTOSTOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AUTOSTOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AUTOSTOP` writer - Auto Stop Tracing"] +pub struct AUTOSTOP_W<'a> { + w: &'a mut W, +} +impl<'a> AUTOSTOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `AUTOHALT` reader - Auto Halt Request"] +pub struct AUTOHALT_R(crate::FieldReader); +impl AUTOHALT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AUTOHALT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AUTOHALT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AUTOHALT` writer - Auto Halt Request"] +pub struct AUTOHALT_W<'a> { + w: &'a mut W, +} +impl<'a> AUTOHALT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WATERMARK` reader - Watermark value"] +pub struct WATERMARK_R(crate::FieldReader); +impl WATERMARK_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + WATERMARK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WATERMARK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WATERMARK` writer - Watermark value"] +pub struct WATERMARK_W<'a> { + w: &'a mut W, +} +impl<'a> WATERMARK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1fff_ffff << 3)) | ((value as u32 & 0x1fff_ffff) << 3); + self.w + } +} +impl R { + #[doc = "Bit 0 - Auto Stop Tracing"] + #[inline(always)] + pub fn autostop(&self) -> AUTOSTOP_R { + AUTOSTOP_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Auto Halt Request"] + #[inline(always)] + pub fn autohalt(&self) -> AUTOHALT_R { + AUTOHALT_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 3:31 - Watermark value"] + #[inline(always)] + pub fn watermark(&self) -> WATERMARK_R { + WATERMARK_R::new(((self.bits >> 3) & 0x1fff_ffff) as u32) + } +} +impl W { + #[doc = "Bit 0 - Auto Stop Tracing"] + #[inline(always)] + pub fn autostop(&mut self) -> AUTOSTOP_W { + AUTOSTOP_W { w: self } + } + #[doc = "Bit 1 - Auto Halt Request"] + #[inline(always)] + pub fn autohalt(&mut self) -> AUTOHALT_W { + AUTOHALT_W { w: self } + } + #[doc = "Bits 3:31 - Watermark value"] + #[inline(always)] + pub fn watermark(&mut self) -> WATERMARK_W { + WATERMARK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MTB Flow\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [flow](index.html) module"] +pub struct FLOW_SPEC; +impl crate::RegisterSpec for FLOW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [flow::R](R) reader structure"] +impl crate::Readable for FLOW_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [flow::W](W) writer structure"] +impl crate::Writable for FLOW_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets FLOW to value 0"] +impl crate::Resettable for FLOW_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/mtb/itctrl.rs b/pac/atsamc21g/src/mtb/itctrl.rs new file mode 100644 index 000000000000..a48364e0b062 --- /dev/null +++ b/pac/atsamc21g/src/mtb/itctrl.rs @@ -0,0 +1,64 @@ +#[doc = "Register `ITCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ITCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MTB Integration Mode Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [itctrl](index.html) module"] +pub struct ITCTRL_SPEC; +impl crate::RegisterSpec for ITCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [itctrl::R](R) reader structure"] +impl crate::Readable for ITCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [itctrl::W](W) writer structure"] +impl crate::Writable for ITCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ITCTRL to value 0"] +impl crate::Resettable for ITCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/mtb/lockaccess.rs b/pac/atsamc21g/src/mtb/lockaccess.rs new file mode 100644 index 000000000000..0400690beade --- /dev/null +++ b/pac/atsamc21g/src/mtb/lockaccess.rs @@ -0,0 +1,64 @@ +#[doc = "Register `LOCKACCESS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `LOCKACCESS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MTB Lock Access\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lockaccess](index.html) module"] +pub struct LOCKACCESS_SPEC; +impl crate::RegisterSpec for LOCKACCESS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [lockaccess::R](R) reader structure"] +impl crate::Readable for LOCKACCESS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [lockaccess::W](W) writer structure"] +impl crate::Writable for LOCKACCESS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets LOCKACCESS to value 0"] +impl crate::Resettable for LOCKACCESS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/mtb/lockstatus.rs b/pac/atsamc21g/src/mtb/lockstatus.rs new file mode 100644 index 000000000000..0c68410c6944 --- /dev/null +++ b/pac/atsamc21g/src/mtb/lockstatus.rs @@ -0,0 +1,31 @@ +#[doc = "Register `LOCKSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "MTB Lock Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lockstatus](index.html) module"] +pub struct LOCKSTATUS_SPEC; +impl crate::RegisterSpec for LOCKSTATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [lockstatus::R](R) reader structure"] +impl crate::Readable for LOCKSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets LOCKSTATUS to value 0"] +impl crate::Resettable for LOCKSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/mtb/master.rs b/pac/atsamc21g/src/mtb/master.rs new file mode 100644 index 000000000000..0190ca1ce909 --- /dev/null +++ b/pac/atsamc21g/src/mtb/master.rs @@ -0,0 +1,385 @@ +#[doc = "Register `MASTER` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MASTER` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MASK` reader - Maximum Value of the Trace Buffer in SRAM"] +pub struct MASK_R(crate::FieldReader); +impl MASK_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MASK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MASK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MASK` writer - Maximum Value of the Trace Buffer in SRAM"] +pub struct MASK_W<'a> { + w: &'a mut W, +} +impl<'a> MASK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f); + self.w + } +} +#[doc = "Field `TSTARTEN` reader - Trace Start Input Enable"] +pub struct TSTARTEN_R(crate::FieldReader); +impl TSTARTEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSTARTEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSTARTEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSTARTEN` writer - Trace Start Input Enable"] +pub struct TSTARTEN_W<'a> { + w: &'a mut W, +} +impl<'a> TSTARTEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `TSTOPEN` reader - Trace Stop Input Enable"] +pub struct TSTOPEN_R(crate::FieldReader); +impl TSTOPEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSTOPEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSTOPEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSTOPEN` writer - Trace Stop Input Enable"] +pub struct TSTOPEN_W<'a> { + w: &'a mut W, +} +impl<'a> TSTOPEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `SFRWPRIV` reader - Special Function Register Write Privilege"] +pub struct SFRWPRIV_R(crate::FieldReader); +impl SFRWPRIV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SFRWPRIV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SFRWPRIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SFRWPRIV` writer - Special Function Register Write Privilege"] +pub struct SFRWPRIV_W<'a> { + w: &'a mut W, +} +impl<'a> SFRWPRIV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `RAMPRIV` reader - SRAM Privilege"] +pub struct RAMPRIV_R(crate::FieldReader); +impl RAMPRIV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RAMPRIV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RAMPRIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RAMPRIV` writer - SRAM Privilege"] +pub struct RAMPRIV_W<'a> { + w: &'a mut W, +} +impl<'a> RAMPRIV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `HALTREQ` reader - Halt Request"] +pub struct HALTREQ_R(crate::FieldReader); +impl HALTREQ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HALTREQ_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HALTREQ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HALTREQ` writer - Halt Request"] +pub struct HALTREQ_W<'a> { + w: &'a mut W, +} +impl<'a> HALTREQ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `EN` reader - Main Trace Enable"] +pub struct EN_R(crate::FieldReader); +impl EN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EN` writer - Main Trace Enable"] +pub struct EN_W<'a> { + w: &'a mut W, +} +impl<'a> EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Maximum Value of the Trace Buffer in SRAM"] + #[inline(always)] + pub fn mask(&self) -> MASK_R { + MASK_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bit 5 - Trace Start Input Enable"] + #[inline(always)] + pub fn tstarten(&self) -> TSTARTEN_R { + TSTARTEN_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Trace Stop Input Enable"] + #[inline(always)] + pub fn tstopen(&self) -> TSTOPEN_R { + TSTOPEN_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Special Function Register Write Privilege"] + #[inline(always)] + pub fn sfrwpriv(&self) -> SFRWPRIV_R { + SFRWPRIV_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - SRAM Privilege"] + #[inline(always)] + pub fn rampriv(&self) -> RAMPRIV_R { + RAMPRIV_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Halt Request"] + #[inline(always)] + pub fn haltreq(&self) -> HALTREQ_R { + HALTREQ_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 31 - Main Trace Enable"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Maximum Value of the Trace Buffer in SRAM"] + #[inline(always)] + pub fn mask(&mut self) -> MASK_W { + MASK_W { w: self } + } + #[doc = "Bit 5 - Trace Start Input Enable"] + #[inline(always)] + pub fn tstarten(&mut self) -> TSTARTEN_W { + TSTARTEN_W { w: self } + } + #[doc = "Bit 6 - Trace Stop Input Enable"] + #[inline(always)] + pub fn tstopen(&mut self) -> TSTOPEN_W { + TSTOPEN_W { w: self } + } + #[doc = "Bit 7 - Special Function Register Write Privilege"] + #[inline(always)] + pub fn sfrwpriv(&mut self) -> SFRWPRIV_W { + SFRWPRIV_W { w: self } + } + #[doc = "Bit 8 - SRAM Privilege"] + #[inline(always)] + pub fn rampriv(&mut self) -> RAMPRIV_W { + RAMPRIV_W { w: self } + } + #[doc = "Bit 9 - Halt Request"] + #[inline(always)] + pub fn haltreq(&mut self) -> HALTREQ_W { + HALTREQ_W { w: self } + } + #[doc = "Bit 31 - Main Trace Enable"] + #[inline(always)] + pub fn en(&mut self) -> EN_W { + EN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MTB Master\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [master](index.html) module"] +pub struct MASTER_SPEC; +impl crate::RegisterSpec for MASTER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [master::R](R) reader structure"] +impl crate::Readable for MASTER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [master::W](W) writer structure"] +impl crate::Writable for MASTER_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets MASTER to value 0"] +impl crate::Resettable for MASTER_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/mtb/pid0.rs b/pac/atsamc21g/src/mtb/pid0.rs new file mode 100644 index 000000000000..0a7183189fe5 --- /dev/null +++ b/pac/atsamc21g/src/mtb/pid0.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid0](index.html) module"] +pub struct PID0_SPEC; +impl crate::RegisterSpec for PID0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid0::R](R) reader structure"] +impl crate::Readable for PID0_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID0 to value 0"] +impl crate::Resettable for PID0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/mtb/pid1.rs b/pac/atsamc21g/src/mtb/pid1.rs new file mode 100644 index 000000000000..7d6381917f5d --- /dev/null +++ b/pac/atsamc21g/src/mtb/pid1.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid1](index.html) module"] +pub struct PID1_SPEC; +impl crate::RegisterSpec for PID1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid1::R](R) reader structure"] +impl crate::Readable for PID1_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID1 to value 0"] +impl crate::Resettable for PID1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/mtb/pid2.rs b/pac/atsamc21g/src/mtb/pid2.rs new file mode 100644 index 000000000000..74c230346b4c --- /dev/null +++ b/pac/atsamc21g/src/mtb/pid2.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 2\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid2](index.html) module"] +pub struct PID2_SPEC; +impl crate::RegisterSpec for PID2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid2::R](R) reader structure"] +impl crate::Readable for PID2_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID2 to value 0"] +impl crate::Resettable for PID2_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/mtb/pid3.rs b/pac/atsamc21g/src/mtb/pid3.rs new file mode 100644 index 000000000000..e9e922aa2f21 --- /dev/null +++ b/pac/atsamc21g/src/mtb/pid3.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 3\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid3](index.html) module"] +pub struct PID3_SPEC; +impl crate::RegisterSpec for PID3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid3::R](R) reader structure"] +impl crate::Readable for PID3_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID3 to value 0"] +impl crate::Resettable for PID3_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/mtb/pid4.rs b/pac/atsamc21g/src/mtb/pid4.rs new file mode 100644 index 000000000000..89074d3c2692 --- /dev/null +++ b/pac/atsamc21g/src/mtb/pid4.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID4` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 4\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid4](index.html) module"] +pub struct PID4_SPEC; +impl crate::RegisterSpec for PID4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid4::R](R) reader structure"] +impl crate::Readable for PID4_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID4 to value 0"] +impl crate::Resettable for PID4_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/mtb/pid5.rs b/pac/atsamc21g/src/mtb/pid5.rs new file mode 100644 index 000000000000..d343d4800b95 --- /dev/null +++ b/pac/atsamc21g/src/mtb/pid5.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID5` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 5\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid5](index.html) module"] +pub struct PID5_SPEC; +impl crate::RegisterSpec for PID5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid5::R](R) reader structure"] +impl crate::Readable for PID5_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID5 to value 0"] +impl crate::Resettable for PID5_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/mtb/pid6.rs b/pac/atsamc21g/src/mtb/pid6.rs new file mode 100644 index 000000000000..55cc2b8b5861 --- /dev/null +++ b/pac/atsamc21g/src/mtb/pid6.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID6` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 6\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid6](index.html) module"] +pub struct PID6_SPEC; +impl crate::RegisterSpec for PID6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid6::R](R) reader structure"] +impl crate::Readable for PID6_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID6 to value 0"] +impl crate::Resettable for PID6_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/mtb/pid7.rs b/pac/atsamc21g/src/mtb/pid7.rs new file mode 100644 index 000000000000..77664d4f2f95 --- /dev/null +++ b/pac/atsamc21g/src/mtb/pid7.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID7` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 7\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid7](index.html) module"] +pub struct PID7_SPEC; +impl crate::RegisterSpec for PID7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid7::R](R) reader structure"] +impl crate::Readable for PID7_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID7 to value 0"] +impl crate::Resettable for PID7_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/mtb/position.rs b/pac/atsamc21g/src/mtb/position.rs new file mode 100644 index 000000000000..4bab0425b142 --- /dev/null +++ b/pac/atsamc21g/src/mtb/position.rs @@ -0,0 +1,150 @@ +#[doc = "Register `POSITION` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `POSITION` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WRAP` reader - Pointer Value Wraps"] +pub struct WRAP_R(crate::FieldReader); +impl WRAP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WRAP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WRAP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WRAP` writer - Pointer Value Wraps"] +pub struct WRAP_W<'a> { + w: &'a mut W, +} +impl<'a> WRAP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `POINTER` reader - Trace Packet Location Pointer"] +pub struct POINTER_R(crate::FieldReader); +impl POINTER_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + POINTER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for POINTER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `POINTER` writer - Trace Packet Location Pointer"] +pub struct POINTER_W<'a> { + w: &'a mut W, +} +impl<'a> POINTER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1fff_ffff << 3)) | ((value as u32 & 0x1fff_ffff) << 3); + self.w + } +} +impl R { + #[doc = "Bit 2 - Pointer Value Wraps"] + #[inline(always)] + pub fn wrap(&self) -> WRAP_R { + WRAP_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 3:31 - Trace Packet Location Pointer"] + #[inline(always)] + pub fn pointer(&self) -> POINTER_R { + POINTER_R::new(((self.bits >> 3) & 0x1fff_ffff) as u32) + } +} +impl W { + #[doc = "Bit 2 - Pointer Value Wraps"] + #[inline(always)] + pub fn wrap(&mut self) -> WRAP_W { + WRAP_W { w: self } + } + #[doc = "Bits 3:31 - Trace Packet Location Pointer"] + #[inline(always)] + pub fn pointer(&mut self) -> POINTER_W { + POINTER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MTB Position\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [position](index.html) module"] +pub struct POSITION_SPEC; +impl crate::RegisterSpec for POSITION_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [position::R](R) reader structure"] +impl crate::Readable for POSITION_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [position::W](W) writer structure"] +impl crate::Writable for POSITION_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets POSITION to value 0"] +impl crate::Resettable for POSITION_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/nvmctrl.rs b/pac/atsamc21g/src/nvmctrl.rs new file mode 100644 index 000000000000..2c017caaef9c --- /dev/null +++ b/pac/atsamc21g/src/nvmctrl.rs @@ -0,0 +1,76 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + _reserved1: [u8; 0x02], + #[doc = "0x04 - Control B"] + pub ctrlb: crate::Reg, + #[doc = "0x08 - NVM Parameter"] + pub param: crate::Reg, + #[doc = "0x0c - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + _reserved4: [u8; 0x03], + #[doc = "0x10 - Interrupt Enable Set"] + pub intenset: crate::Reg, + _reserved5: [u8; 0x03], + #[doc = "0x14 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved6: [u8; 0x03], + #[doc = "0x18 - Status"] + pub status: crate::Reg, + _reserved7: [u8; 0x02], + #[doc = "0x1c - Address"] + pub addr: crate::Reg, + #[doc = "0x20 - Lock Section"] + pub lock: crate::Reg, + _reserved9: [u8; 0x06], + #[doc = "0x28 - Page Buffer Load Data 0"] + pub pbldata0: crate::Reg, + #[doc = "0x2c - Page Buffer Load Data 1"] + pub pbldata1: crate::Reg, +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "Control B"] +pub mod ctrlb; +#[doc = "PARAM register accessor: an alias for `Reg`"] +pub type PARAM = crate::Reg; +#[doc = "NVM Parameter"] +pub mod param; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "ADDR register accessor: an alias for `Reg`"] +pub type ADDR = crate::Reg; +#[doc = "Address"] +pub mod addr; +#[doc = "LOCK register accessor: an alias for `Reg`"] +pub type LOCK = crate::Reg; +#[doc = "Lock Section"] +pub mod lock; +#[doc = "PBLDATA0 register accessor: an alias for `Reg`"] +pub type PBLDATA0 = crate::Reg; +#[doc = "Page Buffer Load Data 0"] +pub mod pbldata0; +#[doc = "PBLDATA1 register accessor: an alias for `Reg`"] +pub type PBLDATA1 = crate::Reg; +#[doc = "Page Buffer Load Data 1"] +pub mod pbldata1; diff --git a/pac/atsamc21g/src/nvmctrl/addr.rs b/pac/atsamc21g/src/nvmctrl/addr.rs new file mode 100644 index 000000000000..74ed27736dac --- /dev/null +++ b/pac/atsamc21g/src/nvmctrl/addr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `ADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ADDR` reader - NVM Address"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - NVM Address"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x003f_ffff) | (value as u32 & 0x003f_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:21 - NVM Address"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new((self.bits & 0x003f_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:21 - NVM Address"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [addr](index.html) module"] +pub struct ADDR_SPEC; +impl crate::RegisterSpec for ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [addr::R](R) reader structure"] +impl crate::Readable for ADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [addr::W](W) writer structure"] +impl crate::Writable for ADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ADDR to value 0"] +impl crate::Resettable for ADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/nvmctrl/ctrla.rs b/pac/atsamc21g/src/nvmctrl/ctrla.rs new file mode 100644 index 000000000000..89f175771e4d --- /dev/null +++ b/pac/atsamc21g/src/nvmctrl/ctrla.rs @@ -0,0 +1,394 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "2: Erase Row - Erases the row addressed by the ADDR register."] + ER = 2, + #[doc = "4: Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register."] + WP = 4, + #[doc = "5: Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row."] + EAR = 5, + #[doc = "6: Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row."] + WAP = 6, + #[doc = "10: Security Flow Command"] + SF = 10, + #[doc = "15: Write lockbits"] + WL = 15, + #[doc = "26: RWW EEPROM area Erase Row - Erases the row addressed by the ADDR register."] + RWWEEER = 26, + #[doc = "28: RWW EEPROM Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register."] + RWWEEWP = 28, + #[doc = "64: Lock Region - Locks the region containing the address location in the ADDR register."] + LR = 64, + #[doc = "65: Unlock Region - Unlocks the region containing the address location in the ADDR register."] + UR = 65, + #[doc = "66: Sets the power reduction mode."] + SPRM = 66, + #[doc = "67: Clears the power reduction mode."] + CPRM = 67, + #[doc = "68: Page Buffer Clear - Clears the page buffer."] + PBC = 68, + #[doc = "69: Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row."] + SSB = 69, + #[doc = "70: Invalidate all cache lines."] + INVALL = 70, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 2 => Some(CMD_A::ER), + 4 => Some(CMD_A::WP), + 5 => Some(CMD_A::EAR), + 6 => Some(CMD_A::WAP), + 10 => Some(CMD_A::SF), + 15 => Some(CMD_A::WL), + 26 => Some(CMD_A::RWWEEER), + 28 => Some(CMD_A::RWWEEWP), + 64 => Some(CMD_A::LR), + 65 => Some(CMD_A::UR), + 66 => Some(CMD_A::SPRM), + 67 => Some(CMD_A::CPRM), + 68 => Some(CMD_A::PBC), + 69 => Some(CMD_A::SSB), + 70 => Some(CMD_A::INVALL), + _ => None, + } + } + #[doc = "Checks if the value of the field is `ER`"] + #[inline(always)] + pub fn is_er(&self) -> bool { + **self == CMD_A::ER + } + #[doc = "Checks if the value of the field is `WP`"] + #[inline(always)] + pub fn is_wp(&self) -> bool { + **self == CMD_A::WP + } + #[doc = "Checks if the value of the field is `EAR`"] + #[inline(always)] + pub fn is_ear(&self) -> bool { + **self == CMD_A::EAR + } + #[doc = "Checks if the value of the field is `WAP`"] + #[inline(always)] + pub fn is_wap(&self) -> bool { + **self == CMD_A::WAP + } + #[doc = "Checks if the value of the field is `SF`"] + #[inline(always)] + pub fn is_sf(&self) -> bool { + **self == CMD_A::SF + } + #[doc = "Checks if the value of the field is `WL`"] + #[inline(always)] + pub fn is_wl(&self) -> bool { + **self == CMD_A::WL + } + #[doc = "Checks if the value of the field is `RWWEEER`"] + #[inline(always)] + pub fn is_rwweeer(&self) -> bool { + **self == CMD_A::RWWEEER + } + #[doc = "Checks if the value of the field is `RWWEEWP`"] + #[inline(always)] + pub fn is_rwweewp(&self) -> bool { + **self == CMD_A::RWWEEWP + } + #[doc = "Checks if the value of the field is `LR`"] + #[inline(always)] + pub fn is_lr(&self) -> bool { + **self == CMD_A::LR + } + #[doc = "Checks if the value of the field is `UR`"] + #[inline(always)] + pub fn is_ur(&self) -> bool { + **self == CMD_A::UR + } + #[doc = "Checks if the value of the field is `SPRM`"] + #[inline(always)] + pub fn is_sprm(&self) -> bool { + **self == CMD_A::SPRM + } + #[doc = "Checks if the value of the field is `CPRM`"] + #[inline(always)] + pub fn is_cprm(&self) -> bool { + **self == CMD_A::CPRM + } + #[doc = "Checks if the value of the field is `PBC`"] + #[inline(always)] + pub fn is_pbc(&self) -> bool { + **self == CMD_A::PBC + } + #[doc = "Checks if the value of the field is `SSB`"] + #[inline(always)] + pub fn is_ssb(&self) -> bool { + **self == CMD_A::SSB + } + #[doc = "Checks if the value of the field is `INVALL`"] + #[inline(always)] + pub fn is_invall(&self) -> bool { + **self == CMD_A::INVALL + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Erase Row - Erases the row addressed by the ADDR register."] + #[inline(always)] + pub fn er(self) -> &'a mut W { + self.variant(CMD_A::ER) + } + #[doc = "Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register."] + #[inline(always)] + pub fn wp(self) -> &'a mut W { + self.variant(CMD_A::WP) + } + #[doc = "Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row."] + #[inline(always)] + pub fn ear(self) -> &'a mut W { + self.variant(CMD_A::EAR) + } + #[doc = "Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row."] + #[inline(always)] + pub fn wap(self) -> &'a mut W { + self.variant(CMD_A::WAP) + } + #[doc = "Security Flow Command"] + #[inline(always)] + pub fn sf(self) -> &'a mut W { + self.variant(CMD_A::SF) + } + #[doc = "Write lockbits"] + #[inline(always)] + pub fn wl(self) -> &'a mut W { + self.variant(CMD_A::WL) + } + #[doc = "RWW EEPROM area Erase Row - Erases the row addressed by the ADDR register."] + #[inline(always)] + pub fn rwweeer(self) -> &'a mut W { + self.variant(CMD_A::RWWEEER) + } + #[doc = "RWW EEPROM Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register."] + #[inline(always)] + pub fn rwweewp(self) -> &'a mut W { + self.variant(CMD_A::RWWEEWP) + } + #[doc = "Lock Region - Locks the region containing the address location in the ADDR register."] + #[inline(always)] + pub fn lr(self) -> &'a mut W { + self.variant(CMD_A::LR) + } + #[doc = "Unlock Region - Unlocks the region containing the address location in the ADDR register."] + #[inline(always)] + pub fn ur(self) -> &'a mut W { + self.variant(CMD_A::UR) + } + #[doc = "Sets the power reduction mode."] + #[inline(always)] + pub fn sprm(self) -> &'a mut W { + self.variant(CMD_A::SPRM) + } + #[doc = "Clears the power reduction mode."] + #[inline(always)] + pub fn cprm(self) -> &'a mut W { + self.variant(CMD_A::CPRM) + } + #[doc = "Page Buffer Clear - Clears the page buffer."] + #[inline(always)] + pub fn pbc(self) -> &'a mut W { + self.variant(CMD_A::PBC) + } + #[doc = "Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row."] + #[inline(always)] + pub fn ssb(self) -> &'a mut W { + self.variant(CMD_A::SSB) + } + #[doc = "Invalidate all cache lines."] + #[inline(always)] + pub fn invall(self) -> &'a mut W { + self.variant(CMD_A::INVALL) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x7f) | (value as u16 & 0x7f); + self.w + } +} +#[doc = "Command Execution\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMDEX_A { + #[doc = "165: Execution Key"] + KEY = 165, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMDEX_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMDEX` reader - Command Execution"] +pub struct CMDEX_R(crate::FieldReader); +impl CMDEX_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMDEX_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 165 => Some(CMDEX_A::KEY), + _ => None, + } + } + #[doc = "Checks if the value of the field is `KEY`"] + #[inline(always)] + pub fn is_key(&self) -> bool { + **self == CMDEX_A::KEY + } +} +impl core::ops::Deref for CMDEX_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMDEX` writer - Command Execution"] +pub struct CMDEX_W<'a> { + w: &'a mut W, +} +impl<'a> CMDEX_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMDEX_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Execution Key"] + #[inline(always)] + pub fn key(self) -> &'a mut W { + self.variant(CMDEX_A::KEY) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u16 & 0xff) << 8); + self.w + } +} +impl R { + #[doc = "Bits 0:6 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bits 8:15 - Command Execution"] + #[inline(always)] + pub fn cmdex(&self) -> CMDEX_R { + CMDEX_R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:6 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Bits 8:15 - Command Execution"] + #[inline(always)] + pub fn cmdex(&mut self) -> CMDEX_W { + CMDEX_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/nvmctrl/ctrlb.rs b/pac/atsamc21g/src/nvmctrl/ctrlb.rs new file mode 100644 index 000000000000..6162d0d4ade0 --- /dev/null +++ b/pac/atsamc21g/src/nvmctrl/ctrlb.rs @@ -0,0 +1,447 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "NVM Read Wait States\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum RWS_A { + #[doc = "0: Single Auto Wait State"] + SINGLE = 0, + #[doc = "1: Half Auto Wait State"] + HALF = 1, + #[doc = "2: Dual Auto Wait State"] + DUAL = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RWS_A) -> Self { + variant as _ + } +} +#[doc = "Field `RWS` reader - NVM Read Wait States"] +pub struct RWS_R(crate::FieldReader); +impl RWS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RWS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(RWS_A::SINGLE), + 1 => Some(RWS_A::HALF), + 2 => Some(RWS_A::DUAL), + _ => None, + } + } + #[doc = "Checks if the value of the field is `SINGLE`"] + #[inline(always)] + pub fn is_single(&self) -> bool { + **self == RWS_A::SINGLE + } + #[doc = "Checks if the value of the field is `HALF`"] + #[inline(always)] + pub fn is_half(&self) -> bool { + **self == RWS_A::HALF + } + #[doc = "Checks if the value of the field is `DUAL`"] + #[inline(always)] + pub fn is_dual(&self) -> bool { + **self == RWS_A::DUAL + } +} +impl core::ops::Deref for RWS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RWS` writer - NVM Read Wait States"] +pub struct RWS_W<'a> { + w: &'a mut W, +} +impl<'a> RWS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RWS_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Single Auto Wait State"] + #[inline(always)] + pub fn single(self) -> &'a mut W { + self.variant(RWS_A::SINGLE) + } + #[doc = "Half Auto Wait State"] + #[inline(always)] + pub fn half(self) -> &'a mut W { + self.variant(RWS_A::HALF) + } + #[doc = "Dual Auto Wait State"] + #[inline(always)] + pub fn dual(self) -> &'a mut W { + self.variant(RWS_A::DUAL) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 1)) | ((value as u32 & 0x0f) << 1); + self.w + } +} +#[doc = "Field `MANW` reader - Manual Write"] +pub struct MANW_R(crate::FieldReader); +impl MANW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MANW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MANW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MANW` writer - Manual Write"] +pub struct MANW_W<'a> { + w: &'a mut W, +} +impl<'a> MANW_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Power Reduction Mode during Sleep\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SLEEPPRM_A { + #[doc = "0: NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access."] + WAKEONACCESS = 0, + #[doc = "1: NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep."] + WAKEUPINSTANT = 1, + #[doc = "3: Auto power reduction disabled."] + DISABLED = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SLEEPPRM_A) -> Self { + variant as _ + } +} +#[doc = "Field `SLEEPPRM` reader - Power Reduction Mode during Sleep"] +pub struct SLEEPPRM_R(crate::FieldReader); +impl SLEEPPRM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SLEEPPRM_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SLEEPPRM_A::WAKEONACCESS), + 1 => Some(SLEEPPRM_A::WAKEUPINSTANT), + 3 => Some(SLEEPPRM_A::DISABLED), + _ => None, + } + } + #[doc = "Checks if the value of the field is `WAKEONACCESS`"] + #[inline(always)] + pub fn is_wakeonaccess(&self) -> bool { + **self == SLEEPPRM_A::WAKEONACCESS + } + #[doc = "Checks if the value of the field is `WAKEUPINSTANT`"] + #[inline(always)] + pub fn is_wakeupinstant(&self) -> bool { + **self == SLEEPPRM_A::WAKEUPINSTANT + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + **self == SLEEPPRM_A::DISABLED + } +} +impl core::ops::Deref for SLEEPPRM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLEEPPRM` writer - Power Reduction Mode during Sleep"] +pub struct SLEEPPRM_W<'a> { + w: &'a mut W, +} +impl<'a> SLEEPPRM_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SLEEPPRM_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access."] + #[inline(always)] + pub fn wakeonaccess(self) -> &'a mut W { + self.variant(SLEEPPRM_A::WAKEONACCESS) + } + #[doc = "NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep."] + #[inline(always)] + pub fn wakeupinstant(self) -> &'a mut W { + self.variant(SLEEPPRM_A::WAKEUPINSTANT) + } + #[doc = "Auto power reduction disabled."] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(SLEEPPRM_A::DISABLED) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 8)) | ((value as u32 & 0x03) << 8); + self.w + } +} +#[doc = "NVMCTRL Read Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum READMODE_A { + #[doc = "0: The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance."] + NO_MISS_PENALTY = 0, + #[doc = "1: Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time."] + LOW_POWER = 1, + #[doc = "2: The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings."] + DETERMINISTIC = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: READMODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `READMODE` reader - NVMCTRL Read Mode"] +pub struct READMODE_R(crate::FieldReader); +impl READMODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + READMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(READMODE_A::NO_MISS_PENALTY), + 1 => Some(READMODE_A::LOW_POWER), + 2 => Some(READMODE_A::DETERMINISTIC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NO_MISS_PENALTY`"] + #[inline(always)] + pub fn is_no_miss_penalty(&self) -> bool { + **self == READMODE_A::NO_MISS_PENALTY + } + #[doc = "Checks if the value of the field is `LOW_POWER`"] + #[inline(always)] + pub fn is_low_power(&self) -> bool { + **self == READMODE_A::LOW_POWER + } + #[doc = "Checks if the value of the field is `DETERMINISTIC`"] + #[inline(always)] + pub fn is_deterministic(&self) -> bool { + **self == READMODE_A::DETERMINISTIC + } +} +impl core::ops::Deref for READMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `READMODE` writer - NVMCTRL Read Mode"] +pub struct READMODE_W<'a> { + w: &'a mut W, +} +impl<'a> READMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: READMODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance."] + #[inline(always)] + pub fn no_miss_penalty(self) -> &'a mut W { + self.variant(READMODE_A::NO_MISS_PENALTY) + } + #[doc = "Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time."] + #[inline(always)] + pub fn low_power(self) -> &'a mut W { + self.variant(READMODE_A::LOW_POWER) + } + #[doc = "The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings."] + #[inline(always)] + pub fn deterministic(self) -> &'a mut W { + self.variant(READMODE_A::DETERMINISTIC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Field `CACHEDIS` reader - Cache Disable"] +pub struct CACHEDIS_R(crate::FieldReader); +impl CACHEDIS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CACHEDIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CACHEDIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CACHEDIS` writer - Cache Disable"] +pub struct CACHEDIS_W<'a> { + w: &'a mut W, +} +impl<'a> CACHEDIS_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 18)) | ((value as u32 & 0x03) << 18); + self.w + } +} +impl R { + #[doc = "Bits 1:4 - NVM Read Wait States"] + #[inline(always)] + pub fn rws(&self) -> RWS_R { + RWS_R::new(((self.bits >> 1) & 0x0f) as u8) + } + #[doc = "Bit 7 - Manual Write"] + #[inline(always)] + pub fn manw(&self) -> MANW_R { + MANW_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:9 - Power Reduction Mode during Sleep"] + #[inline(always)] + pub fn sleepprm(&self) -> SLEEPPRM_R { + SLEEPPRM_R::new(((self.bits >> 8) & 0x03) as u8) + } + #[doc = "Bits 16:17 - NVMCTRL Read Mode"] + #[inline(always)] + pub fn readmode(&self) -> READMODE_R { + READMODE_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bits 18:19 - Cache Disable"] + #[inline(always)] + pub fn cachedis(&self) -> CACHEDIS_R { + CACHEDIS_R::new(((self.bits >> 18) & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 1:4 - NVM Read Wait States"] + #[inline(always)] + pub fn rws(&mut self) -> RWS_W { + RWS_W { w: self } + } + #[doc = "Bit 7 - Manual Write"] + #[inline(always)] + pub fn manw(&mut self) -> MANW_W { + MANW_W { w: self } + } + #[doc = "Bits 8:9 - Power Reduction Mode during Sleep"] + #[inline(always)] + pub fn sleepprm(&mut self) -> SLEEPPRM_W { + SLEEPPRM_W { w: self } + } + #[doc = "Bits 16:17 - NVMCTRL Read Mode"] + #[inline(always)] + pub fn readmode(&mut self) -> READMODE_W { + READMODE_W { w: self } + } + #[doc = "Bits 18:19 - Cache Disable"] + #[inline(always)] + pub fn cachedis(&mut self) -> CACHEDIS_W { + CACHEDIS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0x80"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x80 + } +} diff --git a/pac/atsamc21g/src/nvmctrl/intenclr.rs b/pac/atsamc21g/src/nvmctrl/intenclr.rs new file mode 100644 index 000000000000..6e7db4b52c9d --- /dev/null +++ b/pac/atsamc21g/src/nvmctrl/intenclr.rs @@ -0,0 +1,160 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `READY` reader - NVM Ready Interrupt Enable"] +pub struct READY_R(crate::FieldReader); +impl READY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + READY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for READY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `READY` writer - NVM Ready Interrupt Enable"] +pub struct READY_W<'a> { + w: &'a mut W, +} +impl<'a> READY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERROR` reader - Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - NVM Ready Interrupt Enable"] + #[inline(always)] + pub fn ready(&self) -> READY_R { + READY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - NVM Ready Interrupt Enable"] + #[inline(always)] + pub fn ready(&mut self) -> READY_W { + READY_W { w: self } + } + #[doc = "Bit 1 - Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/nvmctrl/intenset.rs b/pac/atsamc21g/src/nvmctrl/intenset.rs new file mode 100644 index 000000000000..ba8698e86c3e --- /dev/null +++ b/pac/atsamc21g/src/nvmctrl/intenset.rs @@ -0,0 +1,160 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `READY` reader - NVM Ready Interrupt Enable"] +pub struct READY_R(crate::FieldReader); +impl READY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + READY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for READY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `READY` writer - NVM Ready Interrupt Enable"] +pub struct READY_W<'a> { + w: &'a mut W, +} +impl<'a> READY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERROR` reader - Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - NVM Ready Interrupt Enable"] + #[inline(always)] + pub fn ready(&self) -> READY_R { + READY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - NVM Ready Interrupt Enable"] + #[inline(always)] + pub fn ready(&mut self) -> READY_W { + READY_W { w: self } + } + #[doc = "Bit 1 - Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/nvmctrl/intflag.rs b/pac/atsamc21g/src/nvmctrl/intflag.rs new file mode 100644 index 000000000000..1b30cdddf25d --- /dev/null +++ b/pac/atsamc21g/src/nvmctrl/intflag.rs @@ -0,0 +1,160 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `READY` reader - NVM Ready"] +pub struct READY_R(crate::FieldReader); +impl READY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + READY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for READY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `READY` writer - NVM Ready"] +pub struct READY_W<'a> { + w: &'a mut W, +} +impl<'a> READY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERROR` reader - Error"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Error"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - NVM Ready"] + #[inline(always)] + pub fn ready(&self) -> READY_R { + READY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Error"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - NVM Ready"] + #[inline(always)] + pub fn ready(&mut self) -> READY_W { + READY_W { w: self } + } + #[doc = "Bit 1 - Error"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/nvmctrl/lock.rs b/pac/atsamc21g/src/nvmctrl/lock.rs new file mode 100644 index 000000000000..dbcf37a8107f --- /dev/null +++ b/pac/atsamc21g/src/nvmctrl/lock.rs @@ -0,0 +1,103 @@ +#[doc = "Register `LOCK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `LOCK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `LOCK` reader - Region Lock Bits"] +pub struct LOCK_R(crate::FieldReader); +impl LOCK_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + LOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LOCK` writer - Region Lock Bits"] +pub struct LOCK_W<'a> { + w: &'a mut W, +} +impl<'a> LOCK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Region Lock Bits"] + #[inline(always)] + pub fn lock(&self) -> LOCK_R { + LOCK_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Region Lock Bits"] + #[inline(always)] + pub fn lock(&mut self) -> LOCK_W { + LOCK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Lock Section\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lock](index.html) module"] +pub struct LOCK_SPEC; +impl crate::RegisterSpec for LOCK_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [lock::R](R) reader structure"] +impl crate::Readable for LOCK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [lock::W](W) writer structure"] +impl crate::Writable for LOCK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets LOCK to value 0"] +impl crate::Resettable for LOCK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/nvmctrl/param.rs b/pac/atsamc21g/src/nvmctrl/param.rs new file mode 100644 index 000000000000..d9197cf16de4 --- /dev/null +++ b/pac/atsamc21g/src/nvmctrl/param.rs @@ -0,0 +1,304 @@ +#[doc = "Register `PARAM` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PARAM` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `NVMP` reader - NVM Pages"] +pub struct NVMP_R(crate::FieldReader); +impl NVMP_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + NVMP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NVMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NVMP` writer - NVM Pages"] +pub struct NVMP_W<'a> { + w: &'a mut W, +} +impl<'a> NVMP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +#[doc = "Page Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PSZ_A { + #[doc = "0: 8 bytes"] + _8 = 0, + #[doc = "1: 16 bytes"] + _16 = 1, + #[doc = "2: 32 bytes"] + _32 = 2, + #[doc = "3: 64 bytes"] + _64 = 3, + #[doc = "4: 128 bytes"] + _128 = 4, + #[doc = "5: 256 bytes"] + _256 = 5, + #[doc = "6: 512 bytes"] + _512 = 6, + #[doc = "7: 1024 bytes"] + _1024 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PSZ_A) -> Self { + variant as _ + } +} +#[doc = "Field `PSZ` reader - Page Size"] +pub struct PSZ_R(crate::FieldReader); +impl PSZ_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PSZ_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PSZ_A { + match self.bits { + 0 => PSZ_A::_8, + 1 => PSZ_A::_16, + 2 => PSZ_A::_32, + 3 => PSZ_A::_64, + 4 => PSZ_A::_128, + 5 => PSZ_A::_256, + 6 => PSZ_A::_512, + 7 => PSZ_A::_1024, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `_8`"] + #[inline(always)] + pub fn is_8(&self) -> bool { + **self == PSZ_A::_8 + } + #[doc = "Checks if the value of the field is `_16`"] + #[inline(always)] + pub fn is_16(&self) -> bool { + **self == PSZ_A::_16 + } + #[doc = "Checks if the value of the field is `_32`"] + #[inline(always)] + pub fn is_32(&self) -> bool { + **self == PSZ_A::_32 + } + #[doc = "Checks if the value of the field is `_64`"] + #[inline(always)] + pub fn is_64(&self) -> bool { + **self == PSZ_A::_64 + } + #[doc = "Checks if the value of the field is `_128`"] + #[inline(always)] + pub fn is_128(&self) -> bool { + **self == PSZ_A::_128 + } + #[doc = "Checks if the value of the field is `_256`"] + #[inline(always)] + pub fn is_256(&self) -> bool { + **self == PSZ_A::_256 + } + #[doc = "Checks if the value of the field is `_512`"] + #[inline(always)] + pub fn is_512(&self) -> bool { + **self == PSZ_A::_512 + } + #[doc = "Checks if the value of the field is `_1024`"] + #[inline(always)] + pub fn is_1024(&self) -> bool { + **self == PSZ_A::_1024 + } +} +impl core::ops::Deref for PSZ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PSZ` writer - Page Size"] +pub struct PSZ_W<'a> { + w: &'a mut W, +} +impl<'a> PSZ_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PSZ_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "8 bytes"] + #[inline(always)] + pub fn _8(self) -> &'a mut W { + self.variant(PSZ_A::_8) + } + #[doc = "16 bytes"] + #[inline(always)] + pub fn _16(self) -> &'a mut W { + self.variant(PSZ_A::_16) + } + #[doc = "32 bytes"] + #[inline(always)] + pub fn _32(self) -> &'a mut W { + self.variant(PSZ_A::_32) + } + #[doc = "64 bytes"] + #[inline(always)] + pub fn _64(self) -> &'a mut W { + self.variant(PSZ_A::_64) + } + #[doc = "128 bytes"] + #[inline(always)] + pub fn _128(self) -> &'a mut W { + self.variant(PSZ_A::_128) + } + #[doc = "256 bytes"] + #[inline(always)] + pub fn _256(self) -> &'a mut W { + self.variant(PSZ_A::_256) + } + #[doc = "512 bytes"] + #[inline(always)] + pub fn _512(self) -> &'a mut W { + self.variant(PSZ_A::_512) + } + #[doc = "1024 bytes"] + #[inline(always)] + pub fn _1024(self) -> &'a mut W { + self.variant(PSZ_A::_1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 16)) | ((value as u32 & 0x07) << 16); + self.w + } +} +#[doc = "Field `RWWEEP` reader - RWW EEPROM Pages"] +pub struct RWWEEP_R(crate::FieldReader); +impl RWWEEP_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + RWWEEP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RWWEEP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RWWEEP` writer - RWW EEPROM Pages"] +pub struct RWWEEP_W<'a> { + w: &'a mut W, +} +impl<'a> RWWEEP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0fff << 20)) | ((value as u32 & 0x0fff) << 20); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - NVM Pages"] + #[inline(always)] + pub fn nvmp(&self) -> NVMP_R { + NVMP_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:18 - Page Size"] + #[inline(always)] + pub fn psz(&self) -> PSZ_R { + PSZ_R::new(((self.bits >> 16) & 0x07) as u8) + } + #[doc = "Bits 20:31 - RWW EEPROM Pages"] + #[inline(always)] + pub fn rwweep(&self) -> RWWEEP_R { + RWWEEP_R::new(((self.bits >> 20) & 0x0fff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - NVM Pages"] + #[inline(always)] + pub fn nvmp(&mut self) -> NVMP_W { + NVMP_W { w: self } + } + #[doc = "Bits 16:18 - Page Size"] + #[inline(always)] + pub fn psz(&mut self) -> PSZ_W { + PSZ_W { w: self } + } + #[doc = "Bits 20:31 - RWW EEPROM Pages"] + #[inline(always)] + pub fn rwweep(&mut self) -> RWWEEP_W { + RWWEEP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "NVM Parameter\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [param](index.html) module"] +pub struct PARAM_SPEC; +impl crate::RegisterSpec for PARAM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [param::R](R) reader structure"] +impl crate::Readable for PARAM_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [param::W](W) writer structure"] +impl crate::Writable for PARAM_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PARAM to value 0"] +impl crate::Resettable for PARAM_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/nvmctrl/pbldata0.rs b/pac/atsamc21g/src/nvmctrl/pbldata0.rs new file mode 100644 index 000000000000..ff2effaf4d89 --- /dev/null +++ b/pac/atsamc21g/src/nvmctrl/pbldata0.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PBLDATA0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Page Buffer Load Data 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pbldata0](index.html) module"] +pub struct PBLDATA0_SPEC; +impl crate::RegisterSpec for PBLDATA0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pbldata0::R](R) reader structure"] +impl crate::Readable for PBLDATA0_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PBLDATA0 to value 0"] +impl crate::Resettable for PBLDATA0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/nvmctrl/pbldata1.rs b/pac/atsamc21g/src/nvmctrl/pbldata1.rs new file mode 100644 index 000000000000..9fc6404691c5 --- /dev/null +++ b/pac/atsamc21g/src/nvmctrl/pbldata1.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PBLDATA1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Page Buffer Load Data 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pbldata1](index.html) module"] +pub struct PBLDATA1_SPEC; +impl crate::RegisterSpec for PBLDATA1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pbldata1::R](R) reader structure"] +impl crate::Readable for PBLDATA1_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PBLDATA1 to value 0"] +impl crate::Resettable for PBLDATA1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/nvmctrl/status.rs b/pac/atsamc21g/src/nvmctrl/status.rs new file mode 100644 index 000000000000..ce849015560e --- /dev/null +++ b/pac/atsamc21g/src/nvmctrl/status.rs @@ -0,0 +1,348 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PRM` reader - Power Reduction Mode"] +pub struct PRM_R(crate::FieldReader); +impl PRM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PRM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PRM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRM` writer - Power Reduction Mode"] +pub struct PRM_W<'a> { + w: &'a mut W, +} +impl<'a> PRM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `LOAD` reader - NVM Page Buffer Active Loading"] +pub struct LOAD_R(crate::FieldReader); +impl LOAD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LOAD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOAD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LOAD` writer - NVM Page Buffer Active Loading"] +pub struct LOAD_W<'a> { + w: &'a mut W, +} +impl<'a> LOAD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PROGE` reader - Programming Error Status"] +pub struct PROGE_R(crate::FieldReader); +impl PROGE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PROGE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PROGE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PROGE` writer - Programming Error Status"] +pub struct PROGE_W<'a> { + w: &'a mut W, +} +impl<'a> PROGE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `LOCKE` reader - Lock Error Status"] +pub struct LOCKE_R(crate::FieldReader); +impl LOCKE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LOCKE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOCKE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LOCKE` writer - Lock Error Status"] +pub struct LOCKE_W<'a> { + w: &'a mut W, +} +impl<'a> LOCKE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `NVME` reader - NVM Error"] +pub struct NVME_R(crate::FieldReader); +impl NVME_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NVME_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NVME_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NVME` writer - NVM Error"] +pub struct NVME_W<'a> { + w: &'a mut W, +} +impl<'a> NVME_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `SB` reader - Security Bit Status"] +pub struct SB_R(crate::FieldReader); +impl SB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SB` writer - Security Bit Status"] +pub struct SB_W<'a> { + w: &'a mut W, +} +impl<'a> SB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +impl R { + #[doc = "Bit 0 - Power Reduction Mode"] + #[inline(always)] + pub fn prm(&self) -> PRM_R { + PRM_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - NVM Page Buffer Active Loading"] + #[inline(always)] + pub fn load(&self) -> LOAD_R { + LOAD_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Programming Error Status"] + #[inline(always)] + pub fn proge(&self) -> PROGE_R { + PROGE_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Lock Error Status"] + #[inline(always)] + pub fn locke(&self) -> LOCKE_R { + LOCKE_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - NVM Error"] + #[inline(always)] + pub fn nvme(&self) -> NVME_R { + NVME_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 8 - Security Bit Status"] + #[inline(always)] + pub fn sb(&self) -> SB_R { + SB_R::new(((self.bits >> 8) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Power Reduction Mode"] + #[inline(always)] + pub fn prm(&mut self) -> PRM_W { + PRM_W { w: self } + } + #[doc = "Bit 1 - NVM Page Buffer Active Loading"] + #[inline(always)] + pub fn load(&mut self) -> LOAD_W { + LOAD_W { w: self } + } + #[doc = "Bit 2 - Programming Error Status"] + #[inline(always)] + pub fn proge(&mut self) -> PROGE_W { + PROGE_W { w: self } + } + #[doc = "Bit 3 - Lock Error Status"] + #[inline(always)] + pub fn locke(&mut self) -> LOCKE_W { + LOCKE_W { w: self } + } + #[doc = "Bit 4 - NVM Error"] + #[inline(always)] + pub fn nvme(&mut self) -> NVME_W { + NVME_W { w: self } + } + #[doc = "Bit 8 - Security Bit Status"] + #[inline(always)] + pub fn sb(&mut self) -> SB_W { + SB_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/osc32kctrl.rs b/pac/atsamc21g/src/osc32kctrl.rs new file mode 100644 index 000000000000..263cd2f61d59 --- /dev/null +++ b/pac/atsamc21g/src/osc32kctrl.rs @@ -0,0 +1,64 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x04 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x08 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x0c - Power and Clocks Status"] + pub status: crate::Reg, + #[doc = "0x10 - Clock selection"] + pub rtcctrl: crate::Reg, + #[doc = "0x14 - 32kHz External Crystal Oscillator (XOSC32K) Control"] + pub xosc32k: crate::Reg, + #[doc = "0x16 - Clock Failure Detector Control"] + pub cfdctrl: crate::Reg, + #[doc = "0x17 - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x18 - 32kHz Internal Oscillator (OSC32K) Control"] + pub osc32k: crate::Reg, + #[doc = "0x1c - 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control"] + pub osculp32k: crate::Reg, +} +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Power and Clocks Status"] +pub mod status; +#[doc = "RTCCTRL register accessor: an alias for `Reg`"] +pub type RTCCTRL = crate::Reg; +#[doc = "Clock selection"] +pub mod rtcctrl; +#[doc = "XOSC32K register accessor: an alias for `Reg`"] +pub type XOSC32K = crate::Reg; +#[doc = "32kHz External Crystal Oscillator (XOSC32K) Control"] +pub mod xosc32k; +#[doc = "CFDCTRL register accessor: an alias for `Reg`"] +pub type CFDCTRL = crate::Reg; +#[doc = "Clock Failure Detector Control"] +pub mod cfdctrl; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "OSC32K register accessor: an alias for `Reg`"] +pub type OSC32K = crate::Reg; +#[doc = "32kHz Internal Oscillator (OSC32K) Control"] +pub mod osc32k; +#[doc = "OSCULP32K register accessor: an alias for `Reg`"] +pub type OSCULP32K = crate::Reg; +#[doc = "32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control"] +pub mod osculp32k; diff --git a/pac/atsamc21g/src/osc32kctrl/cfdctrl.rs b/pac/atsamc21g/src/osc32kctrl/cfdctrl.rs new file mode 100644 index 000000000000..492a86e1a5a7 --- /dev/null +++ b/pac/atsamc21g/src/osc32kctrl/cfdctrl.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CFDCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CFDCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CFDEN` reader - Clock Failure Detector Enable"] +pub struct CFDEN_R(crate::FieldReader); +impl CFDEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFDEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFDEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFDEN` writer - Clock Failure Detector Enable"] +pub struct CFDEN_W<'a> { + w: &'a mut W, +} +impl<'a> CFDEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SWBACK` reader - Clock Switch Back"] +pub struct SWBACK_R(crate::FieldReader); +impl SWBACK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWBACK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWBACK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWBACK` writer - Clock Switch Back"] +pub struct SWBACK_W<'a> { + w: &'a mut W, +} +impl<'a> SWBACK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CFDPRESC` reader - Clock Failure Detector Prescaler"] +pub struct CFDPRESC_R(crate::FieldReader); +impl CFDPRESC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFDPRESC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFDPRESC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFDPRESC` writer - Clock Failure Detector Prescaler"] +pub struct CFDPRESC_W<'a> { + w: &'a mut W, +} +impl<'a> CFDPRESC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Clock Failure Detector Enable"] + #[inline(always)] + pub fn cfden(&self) -> CFDEN_R { + CFDEN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Clock Switch Back"] + #[inline(always)] + pub fn swback(&self) -> SWBACK_R { + SWBACK_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Clock Failure Detector Prescaler"] + #[inline(always)] + pub fn cfdpresc(&self) -> CFDPRESC_R { + CFDPRESC_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Clock Failure Detector Enable"] + #[inline(always)] + pub fn cfden(&mut self) -> CFDEN_W { + CFDEN_W { w: self } + } + #[doc = "Bit 1 - Clock Switch Back"] + #[inline(always)] + pub fn swback(&mut self) -> SWBACK_W { + SWBACK_W { w: self } + } + #[doc = "Bit 2 - Clock Failure Detector Prescaler"] + #[inline(always)] + pub fn cfdpresc(&mut self) -> CFDPRESC_W { + CFDPRESC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Clock Failure Detector Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cfdctrl](index.html) module"] +pub struct CFDCTRL_SPEC; +impl crate::RegisterSpec for CFDCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [cfdctrl::R](R) reader structure"] +impl crate::Readable for CFDCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cfdctrl::W](W) writer structure"] +impl crate::Writable for CFDCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CFDCTRL to value 0"] +impl crate::Resettable for CFDCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/osc32kctrl/evctrl.rs b/pac/atsamc21g/src/osc32kctrl/evctrl.rs new file mode 100644 index 000000000000..e22ba62f0fe2 --- /dev/null +++ b/pac/atsamc21g/src/osc32kctrl/evctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CFDEO` reader - Clock Failure Detector Event Output Enable"] +pub struct CFDEO_R(crate::FieldReader); +impl CFDEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFDEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFDEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFDEO` writer - Clock Failure Detector Event Output Enable"] +pub struct CFDEO_W<'a> { + w: &'a mut W, +} +impl<'a> CFDEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Clock Failure Detector Event Output Enable"] + #[inline(always)] + pub fn cfdeo(&self) -> CFDEO_R { + CFDEO_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Clock Failure Detector Event Output Enable"] + #[inline(always)] + pub fn cfdeo(&mut self) -> CFDEO_W { + CFDEO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/osc32kctrl/intenclr.rs b/pac/atsamc21g/src/osc32kctrl/intenclr.rs new file mode 100644 index 000000000000..7e330c8de495 --- /dev/null +++ b/pac/atsamc21g/src/osc32kctrl/intenclr.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XOSC32KRDY` reader - XOSC32K Ready Interrupt Enable"] +pub struct XOSC32KRDY_R(crate::FieldReader); +impl XOSC32KRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSC32KRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSC32KRDY` writer - XOSC32K Ready Interrupt Enable"] +pub struct XOSC32KRDY_W<'a> { + w: &'a mut W, +} +impl<'a> XOSC32KRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `OSC32KRDY` reader - OSC32K Ready Interrupt Enable"] +pub struct OSC32KRDY_R(crate::FieldReader); +impl OSC32KRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC32KRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC32KRDY` writer - OSC32K Ready Interrupt Enable"] +pub struct OSC32KRDY_W<'a> { + w: &'a mut W, +} +impl<'a> OSC32KRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CLKFAIL` reader - XOSC32K Clock Failure Detector Interrupt Enable"] +pub struct CLKFAIL_R(crate::FieldReader); +impl CLKFAIL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKFAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKFAIL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKFAIL` writer - XOSC32K Clock Failure Detector Interrupt Enable"] +pub struct CLKFAIL_W<'a> { + w: &'a mut W, +} +impl<'a> CLKFAIL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - XOSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn xosc32krdy(&self) -> XOSC32KRDY_R { + XOSC32KRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - OSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn osc32krdy(&self) -> OSC32KRDY_R { + OSC32KRDY_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - XOSC32K Clock Failure Detector Interrupt Enable"] + #[inline(always)] + pub fn clkfail(&self) -> CLKFAIL_R { + CLKFAIL_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - XOSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn xosc32krdy(&mut self) -> XOSC32KRDY_W { + XOSC32KRDY_W { w: self } + } + #[doc = "Bit 1 - OSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn osc32krdy(&mut self) -> OSC32KRDY_W { + OSC32KRDY_W { w: self } + } + #[doc = "Bit 2 - XOSC32K Clock Failure Detector Interrupt Enable"] + #[inline(always)] + pub fn clkfail(&mut self) -> CLKFAIL_W { + CLKFAIL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/osc32kctrl/intenset.rs b/pac/atsamc21g/src/osc32kctrl/intenset.rs new file mode 100644 index 000000000000..e853d40049f2 --- /dev/null +++ b/pac/atsamc21g/src/osc32kctrl/intenset.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XOSC32KRDY` reader - XOSC32K Ready Interrupt Enable"] +pub struct XOSC32KRDY_R(crate::FieldReader); +impl XOSC32KRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSC32KRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSC32KRDY` writer - XOSC32K Ready Interrupt Enable"] +pub struct XOSC32KRDY_W<'a> { + w: &'a mut W, +} +impl<'a> XOSC32KRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `OSC32KRDY` reader - OSC32K Ready Interrupt Enable"] +pub struct OSC32KRDY_R(crate::FieldReader); +impl OSC32KRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC32KRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC32KRDY` writer - OSC32K Ready Interrupt Enable"] +pub struct OSC32KRDY_W<'a> { + w: &'a mut W, +} +impl<'a> OSC32KRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CLKFAIL` reader - XOSC32K Clock Failure Detector Interrupt Enable"] +pub struct CLKFAIL_R(crate::FieldReader); +impl CLKFAIL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKFAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKFAIL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKFAIL` writer - XOSC32K Clock Failure Detector Interrupt Enable"] +pub struct CLKFAIL_W<'a> { + w: &'a mut W, +} +impl<'a> CLKFAIL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - XOSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn xosc32krdy(&self) -> XOSC32KRDY_R { + XOSC32KRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - OSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn osc32krdy(&self) -> OSC32KRDY_R { + OSC32KRDY_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - XOSC32K Clock Failure Detector Interrupt Enable"] + #[inline(always)] + pub fn clkfail(&self) -> CLKFAIL_R { + CLKFAIL_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - XOSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn xosc32krdy(&mut self) -> XOSC32KRDY_W { + XOSC32KRDY_W { w: self } + } + #[doc = "Bit 1 - OSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn osc32krdy(&mut self) -> OSC32KRDY_W { + OSC32KRDY_W { w: self } + } + #[doc = "Bit 2 - XOSC32K Clock Failure Detector Interrupt Enable"] + #[inline(always)] + pub fn clkfail(&mut self) -> CLKFAIL_W { + CLKFAIL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/osc32kctrl/intflag.rs b/pac/atsamc21g/src/osc32kctrl/intflag.rs new file mode 100644 index 000000000000..9ca42439429d --- /dev/null +++ b/pac/atsamc21g/src/osc32kctrl/intflag.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XOSC32KRDY` reader - XOSC32K Ready"] +pub struct XOSC32KRDY_R(crate::FieldReader); +impl XOSC32KRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSC32KRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSC32KRDY` writer - XOSC32K Ready"] +pub struct XOSC32KRDY_W<'a> { + w: &'a mut W, +} +impl<'a> XOSC32KRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `OSC32KRDY` reader - OSC32K Ready"] +pub struct OSC32KRDY_R(crate::FieldReader); +impl OSC32KRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC32KRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC32KRDY` writer - OSC32K Ready"] +pub struct OSC32KRDY_W<'a> { + w: &'a mut W, +} +impl<'a> OSC32KRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CLKFAIL` reader - XOSC32K Clock Failure Detector"] +pub struct CLKFAIL_R(crate::FieldReader); +impl CLKFAIL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKFAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKFAIL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKFAIL` writer - XOSC32K Clock Failure Detector"] +pub struct CLKFAIL_W<'a> { + w: &'a mut W, +} +impl<'a> CLKFAIL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - XOSC32K Ready"] + #[inline(always)] + pub fn xosc32krdy(&self) -> XOSC32KRDY_R { + XOSC32KRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - OSC32K Ready"] + #[inline(always)] + pub fn osc32krdy(&self) -> OSC32KRDY_R { + OSC32KRDY_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - XOSC32K Clock Failure Detector"] + #[inline(always)] + pub fn clkfail(&self) -> CLKFAIL_R { + CLKFAIL_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - XOSC32K Ready"] + #[inline(always)] + pub fn xosc32krdy(&mut self) -> XOSC32KRDY_W { + XOSC32KRDY_W { w: self } + } + #[doc = "Bit 1 - OSC32K Ready"] + #[inline(always)] + pub fn osc32krdy(&mut self) -> OSC32KRDY_W { + OSC32KRDY_W { w: self } + } + #[doc = "Bit 2 - XOSC32K Clock Failure Detector"] + #[inline(always)] + pub fn clkfail(&mut self) -> CLKFAIL_W { + CLKFAIL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/osc32kctrl/osc32k.rs b/pac/atsamc21g/src/osc32kctrl/osc32k.rs new file mode 100644 index 000000000000..aa32cb287aa7 --- /dev/null +++ b/pac/atsamc21g/src/osc32kctrl/osc32k.rs @@ -0,0 +1,549 @@ +#[doc = "Register `OSC32K` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OSC32K` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Oscillator Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Oscillator Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `EN32K` reader - 32kHz Output Enable"] +pub struct EN32K_R(crate::FieldReader); +impl EN32K_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EN32K_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EN32K_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EN32K` writer - 32kHz Output Enable"] +pub struct EN32K_W<'a> { + w: &'a mut W, +} +impl<'a> EN32K_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `EN1K` reader - 1kHz Output Enable"] +pub struct EN1K_R(crate::FieldReader); +impl EN1K_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EN1K_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EN1K_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EN1K` writer - 1kHz Output Enable"] +pub struct EN1K_W<'a> { + w: &'a mut W, +} +impl<'a> EN1K_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - On Demand Control"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - On Demand Control"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Oscillator Start-Up Time\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum STARTUP_A { + #[doc = "0: 0.092 ms"] + CYCLE3 = 0, + #[doc = "1: 0.122 ms"] + CYCLE4 = 1, + #[doc = "2: 0.183 ms"] + CYCLE6 = 2, + #[doc = "3: 0.305 ms"] + CYCLE10 = 3, + #[doc = "4: 0.549 ms"] + CYCLE18 = 4, + #[doc = "5: 1.038 ms"] + CYCLE34 = 5, + #[doc = "6: 2.014 ms"] + CYCLE66 = 6, + #[doc = "7: 3.967 ms"] + CYCLE130 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: STARTUP_A) -> Self { + variant as _ + } +} +#[doc = "Field `STARTUP` reader - Oscillator Start-Up Time"] +pub struct STARTUP_R(crate::FieldReader); +impl STARTUP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + STARTUP_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STARTUP_A { + match self.bits { + 0 => STARTUP_A::CYCLE3, + 1 => STARTUP_A::CYCLE4, + 2 => STARTUP_A::CYCLE6, + 3 => STARTUP_A::CYCLE10, + 4 => STARTUP_A::CYCLE18, + 5 => STARTUP_A::CYCLE34, + 6 => STARTUP_A::CYCLE66, + 7 => STARTUP_A::CYCLE130, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `CYCLE3`"] + #[inline(always)] + pub fn is_cycle3(&self) -> bool { + **self == STARTUP_A::CYCLE3 + } + #[doc = "Checks if the value of the field is `CYCLE4`"] + #[inline(always)] + pub fn is_cycle4(&self) -> bool { + **self == STARTUP_A::CYCLE4 + } + #[doc = "Checks if the value of the field is `CYCLE6`"] + #[inline(always)] + pub fn is_cycle6(&self) -> bool { + **self == STARTUP_A::CYCLE6 + } + #[doc = "Checks if the value of the field is `CYCLE10`"] + #[inline(always)] + pub fn is_cycle10(&self) -> bool { + **self == STARTUP_A::CYCLE10 + } + #[doc = "Checks if the value of the field is `CYCLE18`"] + #[inline(always)] + pub fn is_cycle18(&self) -> bool { + **self == STARTUP_A::CYCLE18 + } + #[doc = "Checks if the value of the field is `CYCLE34`"] + #[inline(always)] + pub fn is_cycle34(&self) -> bool { + **self == STARTUP_A::CYCLE34 + } + #[doc = "Checks if the value of the field is `CYCLE66`"] + #[inline(always)] + pub fn is_cycle66(&self) -> bool { + **self == STARTUP_A::CYCLE66 + } + #[doc = "Checks if the value of the field is `CYCLE130`"] + #[inline(always)] + pub fn is_cycle130(&self) -> bool { + **self == STARTUP_A::CYCLE130 + } +} +impl core::ops::Deref for STARTUP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STARTUP` writer - Oscillator Start-Up Time"] +pub struct STARTUP_W<'a> { + w: &'a mut W, +} +impl<'a> STARTUP_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: STARTUP_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "0.092 ms"] + #[inline(always)] + pub fn cycle3(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE3) + } + #[doc = "0.122 ms"] + #[inline(always)] + pub fn cycle4(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE4) + } + #[doc = "0.183 ms"] + #[inline(always)] + pub fn cycle6(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE6) + } + #[doc = "0.305 ms"] + #[inline(always)] + pub fn cycle10(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE10) + } + #[doc = "0.549 ms"] + #[inline(always)] + pub fn cycle18(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE18) + } + #[doc = "1.038 ms"] + #[inline(always)] + pub fn cycle34(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE34) + } + #[doc = "2.014 ms"] + #[inline(always)] + pub fn cycle66(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE66) + } + #[doc = "3.967 ms"] + #[inline(always)] + pub fn cycle130(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE130) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +#[doc = "Field `WRTLOCK` reader - Write Lock"] +pub struct WRTLOCK_R(crate::FieldReader); +impl WRTLOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WRTLOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WRTLOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WRTLOCK` writer - Write Lock"] +pub struct WRTLOCK_W<'a> { + w: &'a mut W, +} +impl<'a> WRTLOCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `CALIB` reader - Oscillator Calibration"] +pub struct CALIB_R(crate::FieldReader); +impl CALIB_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CALIB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CALIB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CALIB` writer - Oscillator Calibration"] +pub struct CALIB_W<'a> { + w: &'a mut W, +} +impl<'a> CALIB_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x7f << 16)) | ((value as u32 & 0x7f) << 16); + self.w + } +} +impl R { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - 32kHz Output Enable"] + #[inline(always)] + pub fn en32k(&self) -> EN32K_R { + EN32K_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - 1kHz Output Enable"] + #[inline(always)] + pub fn en1k(&self) -> EN1K_R { + EN1K_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Oscillator Start-Up Time"] + #[inline(always)] + pub fn startup(&self) -> STARTUP_R { + STARTUP_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 12 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&self) -> WRTLOCK_R { + WRTLOCK_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bits 16:22 - Oscillator Calibration"] + #[inline(always)] + pub fn calib(&self) -> CALIB_R { + CALIB_R::new(((self.bits >> 16) & 0x7f) as u8) + } +} +impl W { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - 32kHz Output Enable"] + #[inline(always)] + pub fn en32k(&mut self) -> EN32K_W { + EN32K_W { w: self } + } + #[doc = "Bit 3 - 1kHz Output Enable"] + #[inline(always)] + pub fn en1k(&mut self) -> EN1K_W { + EN1K_W { w: self } + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Bits 8:10 - Oscillator Start-Up Time"] + #[inline(always)] + pub fn startup(&mut self) -> STARTUP_W { + STARTUP_W { w: self } + } + #[doc = "Bit 12 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&mut self) -> WRTLOCK_W { + WRTLOCK_W { w: self } + } + #[doc = "Bits 16:22 - Oscillator Calibration"] + #[inline(always)] + pub fn calib(&mut self) -> CALIB_W { + CALIB_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "32kHz Internal Oscillator (OSC32K) Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [osc32k](index.html) module"] +pub struct OSC32K_SPEC; +impl crate::RegisterSpec for OSC32K_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [osc32k::R](R) reader structure"] +impl crate::Readable for OSC32K_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [osc32k::W](W) writer structure"] +impl crate::Writable for OSC32K_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OSC32K to value 0x003f_0080"] +impl crate::Resettable for OSC32K_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x003f_0080 + } +} diff --git a/pac/atsamc21g/src/osc32kctrl/osculp32k.rs b/pac/atsamc21g/src/osc32kctrl/osculp32k.rs new file mode 100644 index 000000000000..1c351c406e59 --- /dev/null +++ b/pac/atsamc21g/src/osc32kctrl/osculp32k.rs @@ -0,0 +1,150 @@ +#[doc = "Register `OSCULP32K` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OSCULP32K` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CALIB` reader - Oscillator Calibration"] +pub struct CALIB_R(crate::FieldReader); +impl CALIB_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CALIB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CALIB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CALIB` writer - Oscillator Calibration"] +pub struct CALIB_W<'a> { + w: &'a mut W, +} +impl<'a> CALIB_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 8)) | ((value as u32 & 0x1f) << 8); + self.w + } +} +#[doc = "Field `WRTLOCK` reader - Write Lock"] +pub struct WRTLOCK_R(crate::FieldReader); +impl WRTLOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WRTLOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WRTLOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WRTLOCK` writer - Write Lock"] +pub struct WRTLOCK_W<'a> { + w: &'a mut W, +} +impl<'a> WRTLOCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bits 8:12 - Oscillator Calibration"] + #[inline(always)] + pub fn calib(&self) -> CALIB_R { + CALIB_R::new(((self.bits >> 8) & 0x1f) as u8) + } + #[doc = "Bit 15 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&self) -> WRTLOCK_R { + WRTLOCK_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 8:12 - Oscillator Calibration"] + #[inline(always)] + pub fn calib(&mut self) -> CALIB_W { + CALIB_W { w: self } + } + #[doc = "Bit 15 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&mut self) -> WRTLOCK_W { + WRTLOCK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [osculp32k](index.html) module"] +pub struct OSCULP32K_SPEC; +impl crate::RegisterSpec for OSCULP32K_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [osculp32k::R](R) reader structure"] +impl crate::Readable for OSCULP32K_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [osculp32k::W](W) writer structure"] +impl crate::Writable for OSCULP32K_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OSCULP32K to value 0"] +impl crate::Resettable for OSCULP32K_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/osc32kctrl/rtcctrl.rs b/pac/atsamc21g/src/osc32kctrl/rtcctrl.rs new file mode 100644 index 000000000000..1248024a03b9 --- /dev/null +++ b/pac/atsamc21g/src/osc32kctrl/rtcctrl.rs @@ -0,0 +1,204 @@ +#[doc = "Register `RTCCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RTCCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "RTC Clock Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum RTCSEL_A { + #[doc = "0: 1.024kHz from 32kHz internal ULP oscillator"] + ULP1K = 0, + #[doc = "1: 32.768kHz from 32kHz internal ULP oscillator"] + ULP32K = 1, + #[doc = "2: 1.024kHz from 32.768kHz internal oscillator"] + OSC1K = 2, + #[doc = "3: 32.768kHz from 32.768kHz internal oscillator"] + OSC32K = 3, + #[doc = "4: 1.024kHz from 32.768kHz internal oscillator"] + XOSC1K = 4, + #[doc = "5: 32.768kHz from 32.768kHz external crystal oscillator"] + XOSC32K = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RTCSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `RTCSEL` reader - RTC Clock Selection"] +pub struct RTCSEL_R(crate::FieldReader); +impl RTCSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RTCSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(RTCSEL_A::ULP1K), + 1 => Some(RTCSEL_A::ULP32K), + 2 => Some(RTCSEL_A::OSC1K), + 3 => Some(RTCSEL_A::OSC32K), + 4 => Some(RTCSEL_A::XOSC1K), + 5 => Some(RTCSEL_A::XOSC32K), + _ => None, + } + } + #[doc = "Checks if the value of the field is `ULP1K`"] + #[inline(always)] + pub fn is_ulp1k(&self) -> bool { + **self == RTCSEL_A::ULP1K + } + #[doc = "Checks if the value of the field is `ULP32K`"] + #[inline(always)] + pub fn is_ulp32k(&self) -> bool { + **self == RTCSEL_A::ULP32K + } + #[doc = "Checks if the value of the field is `OSC1K`"] + #[inline(always)] + pub fn is_osc1k(&self) -> bool { + **self == RTCSEL_A::OSC1K + } + #[doc = "Checks if the value of the field is `OSC32K`"] + #[inline(always)] + pub fn is_osc32k(&self) -> bool { + **self == RTCSEL_A::OSC32K + } + #[doc = "Checks if the value of the field is `XOSC1K`"] + #[inline(always)] + pub fn is_xosc1k(&self) -> bool { + **self == RTCSEL_A::XOSC1K + } + #[doc = "Checks if the value of the field is `XOSC32K`"] + #[inline(always)] + pub fn is_xosc32k(&self) -> bool { + **self == RTCSEL_A::XOSC32K + } +} +impl core::ops::Deref for RTCSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RTCSEL` writer - RTC Clock Selection"] +pub struct RTCSEL_W<'a> { + w: &'a mut W, +} +impl<'a> RTCSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RTCSEL_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "1.024kHz from 32kHz internal ULP oscillator"] + #[inline(always)] + pub fn ulp1k(self) -> &'a mut W { + self.variant(RTCSEL_A::ULP1K) + } + #[doc = "32.768kHz from 32kHz internal ULP oscillator"] + #[inline(always)] + pub fn ulp32k(self) -> &'a mut W { + self.variant(RTCSEL_A::ULP32K) + } + #[doc = "1.024kHz from 32.768kHz internal oscillator"] + #[inline(always)] + pub fn osc1k(self) -> &'a mut W { + self.variant(RTCSEL_A::OSC1K) + } + #[doc = "32.768kHz from 32.768kHz internal oscillator"] + #[inline(always)] + pub fn osc32k(self) -> &'a mut W { + self.variant(RTCSEL_A::OSC32K) + } + #[doc = "1.024kHz from 32.768kHz internal oscillator"] + #[inline(always)] + pub fn xosc1k(self) -> &'a mut W { + self.variant(RTCSEL_A::XOSC1K) + } + #[doc = "32.768kHz from 32.768kHz external crystal oscillator"] + #[inline(always)] + pub fn xosc32k(self) -> &'a mut W { + self.variant(RTCSEL_A::XOSC32K) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - RTC Clock Selection"] + #[inline(always)] + pub fn rtcsel(&self) -> RTCSEL_R { + RTCSEL_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - RTC Clock Selection"] + #[inline(always)] + pub fn rtcsel(&mut self) -> RTCSEL_W { + RTCSEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Clock selection\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rtcctrl](index.html) module"] +pub struct RTCCTRL_SPEC; +impl crate::RegisterSpec for RTCCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rtcctrl::R](R) reader structure"] +impl crate::Readable for RTCCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rtcctrl::W](W) writer structure"] +impl crate::Writable for RTCCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RTCCTRL to value 0"] +impl crate::Resettable for RTCCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/osc32kctrl/status.rs b/pac/atsamc21g/src/osc32kctrl/status.rs new file mode 100644 index 000000000000..f1f1483ac4e8 --- /dev/null +++ b/pac/atsamc21g/src/osc32kctrl/status.rs @@ -0,0 +1,113 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `XOSC32KRDY` reader - XOSC32K Ready"] +pub struct XOSC32KRDY_R(crate::FieldReader); +impl XOSC32KRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSC32KRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC32KRDY` reader - OSC32K Ready"] +pub struct OSC32KRDY_R(crate::FieldReader); +impl OSC32KRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC32KRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKFAIL` reader - XOSC32K Clock Failure Detector"] +pub struct CLKFAIL_R(crate::FieldReader); +impl CLKFAIL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKFAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKFAIL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKSW` reader - XOSC32K Clock switch"] +pub struct CLKSW_R(crate::FieldReader); +impl CLKSW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKSW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKSW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - XOSC32K Ready"] + #[inline(always)] + pub fn xosc32krdy(&self) -> XOSC32KRDY_R { + XOSC32KRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - OSC32K Ready"] + #[inline(always)] + pub fn osc32krdy(&self) -> OSC32KRDY_R { + OSC32KRDY_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - XOSC32K Clock Failure Detector"] + #[inline(always)] + pub fn clkfail(&self) -> CLKFAIL_R { + CLKFAIL_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - XOSC32K Clock switch"] + #[inline(always)] + pub fn clksw(&self) -> CLKSW_R { + CLKSW_R::new(((self.bits >> 3) & 0x01) != 0) + } +} +#[doc = "Power and Clocks Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/osc32kctrl/xosc32k.rs b/pac/atsamc21g/src/osc32kctrl/xosc32k.rs new file mode 100644 index 000000000000..93e42bba3c0e --- /dev/null +++ b/pac/atsamc21g/src/osc32kctrl/xosc32k.rs @@ -0,0 +1,559 @@ +#[doc = "Register `XOSC32K` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `XOSC32K` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Oscillator Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Oscillator Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `XTALEN` reader - Crystal Oscillator Enable"] +pub struct XTALEN_R(crate::FieldReader); +impl XTALEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XTALEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XTALEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XTALEN` writer - Crystal Oscillator Enable"] +pub struct XTALEN_W<'a> { + w: &'a mut W, +} +impl<'a> XTALEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `EN32K` reader - 32kHz Output Enable"] +pub struct EN32K_R(crate::FieldReader); +impl EN32K_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EN32K_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EN32K_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EN32K` writer - 32kHz Output Enable"] +pub struct EN32K_W<'a> { + w: &'a mut W, +} +impl<'a> EN32K_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `EN1K` reader - 1kHz Output Enable"] +pub struct EN1K_R(crate::FieldReader); +impl EN1K_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EN1K_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EN1K_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EN1K` writer - 1kHz Output Enable"] +pub struct EN1K_W<'a> { + w: &'a mut W, +} +impl<'a> EN1K_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - On Demand Control"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - On Demand Control"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Oscillator Start-Up Time\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum STARTUP_A { + #[doc = "0: 0.122 ms"] + CYCLE1 = 0, + #[doc = "1: 1.068 ms"] + CYCLE32 = 1, + #[doc = "2: 62.6 ms"] + CYCLE2048 = 2, + #[doc = "3: 125 ms"] + CYCLE4096 = 3, + #[doc = "4: 500 ms"] + CYCLE16384 = 4, + #[doc = "5: 1000 ms"] + CYCLE32768 = 5, + #[doc = "6: 2000 ms"] + CYCLE65536 = 6, + #[doc = "7: 4000 ms"] + CYCLE131072 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: STARTUP_A) -> Self { + variant as _ + } +} +#[doc = "Field `STARTUP` reader - Oscillator Start-Up Time"] +pub struct STARTUP_R(crate::FieldReader); +impl STARTUP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + STARTUP_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STARTUP_A { + match self.bits { + 0 => STARTUP_A::CYCLE1, + 1 => STARTUP_A::CYCLE32, + 2 => STARTUP_A::CYCLE2048, + 3 => STARTUP_A::CYCLE4096, + 4 => STARTUP_A::CYCLE16384, + 5 => STARTUP_A::CYCLE32768, + 6 => STARTUP_A::CYCLE65536, + 7 => STARTUP_A::CYCLE131072, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `CYCLE1`"] + #[inline(always)] + pub fn is_cycle1(&self) -> bool { + **self == STARTUP_A::CYCLE1 + } + #[doc = "Checks if the value of the field is `CYCLE32`"] + #[inline(always)] + pub fn is_cycle32(&self) -> bool { + **self == STARTUP_A::CYCLE32 + } + #[doc = "Checks if the value of the field is `CYCLE2048`"] + #[inline(always)] + pub fn is_cycle2048(&self) -> bool { + **self == STARTUP_A::CYCLE2048 + } + #[doc = "Checks if the value of the field is `CYCLE4096`"] + #[inline(always)] + pub fn is_cycle4096(&self) -> bool { + **self == STARTUP_A::CYCLE4096 + } + #[doc = "Checks if the value of the field is `CYCLE16384`"] + #[inline(always)] + pub fn is_cycle16384(&self) -> bool { + **self == STARTUP_A::CYCLE16384 + } + #[doc = "Checks if the value of the field is `CYCLE32768`"] + #[inline(always)] + pub fn is_cycle32768(&self) -> bool { + **self == STARTUP_A::CYCLE32768 + } + #[doc = "Checks if the value of the field is `CYCLE65536`"] + #[inline(always)] + pub fn is_cycle65536(&self) -> bool { + **self == STARTUP_A::CYCLE65536 + } + #[doc = "Checks if the value of the field is `CYCLE131072`"] + #[inline(always)] + pub fn is_cycle131072(&self) -> bool { + **self == STARTUP_A::CYCLE131072 + } +} +impl core::ops::Deref for STARTUP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STARTUP` writer - Oscillator Start-Up Time"] +pub struct STARTUP_W<'a> { + w: &'a mut W, +} +impl<'a> STARTUP_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: STARTUP_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "0.122 ms"] + #[inline(always)] + pub fn cycle1(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE1) + } + #[doc = "1.068 ms"] + #[inline(always)] + pub fn cycle32(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE32) + } + #[doc = "62.6 ms"] + #[inline(always)] + pub fn cycle2048(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE2048) + } + #[doc = "125 ms"] + #[inline(always)] + pub fn cycle4096(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE4096) + } + #[doc = "500 ms"] + #[inline(always)] + pub fn cycle16384(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE16384) + } + #[doc = "1000 ms"] + #[inline(always)] + pub fn cycle32768(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE32768) + } + #[doc = "2000 ms"] + #[inline(always)] + pub fn cycle65536(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE65536) + } + #[doc = "4000 ms"] + #[inline(always)] + pub fn cycle131072(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE131072) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u16 & 0x07) << 8); + self.w + } +} +#[doc = "Field `WRTLOCK` reader - Write Lock"] +pub struct WRTLOCK_R(crate::FieldReader); +impl WRTLOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WRTLOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WRTLOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WRTLOCK` writer - Write Lock"] +pub struct WRTLOCK_W<'a> { + w: &'a mut W, +} +impl<'a> WRTLOCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u16 & 0x01) << 12); + self.w + } +} +impl R { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Crystal Oscillator Enable"] + #[inline(always)] + pub fn xtalen(&self) -> XTALEN_R { + XTALEN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - 32kHz Output Enable"] + #[inline(always)] + pub fn en32k(&self) -> EN32K_R { + EN32K_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - 1kHz Output Enable"] + #[inline(always)] + pub fn en1k(&self) -> EN1K_R { + EN1K_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Oscillator Start-Up Time"] + #[inline(always)] + pub fn startup(&self) -> STARTUP_R { + STARTUP_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 12 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&self) -> WRTLOCK_R { + WRTLOCK_R::new(((self.bits >> 12) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - Crystal Oscillator Enable"] + #[inline(always)] + pub fn xtalen(&mut self) -> XTALEN_W { + XTALEN_W { w: self } + } + #[doc = "Bit 3 - 32kHz Output Enable"] + #[inline(always)] + pub fn en32k(&mut self) -> EN32K_W { + EN32K_W { w: self } + } + #[doc = "Bit 4 - 1kHz Output Enable"] + #[inline(always)] + pub fn en1k(&mut self) -> EN1K_W { + EN1K_W { w: self } + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Bits 8:10 - Oscillator Start-Up Time"] + #[inline(always)] + pub fn startup(&mut self) -> STARTUP_W { + STARTUP_W { w: self } + } + #[doc = "Bit 12 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&mut self) -> WRTLOCK_W { + WRTLOCK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "32kHz External Crystal Oscillator (XOSC32K) Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [xosc32k](index.html) module"] +pub struct XOSC32K_SPEC; +impl crate::RegisterSpec for XOSC32K_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [xosc32k::R](R) reader structure"] +impl crate::Readable for XOSC32K_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [xosc32k::W](W) writer structure"] +impl crate::Writable for XOSC32K_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets XOSC32K to value 0x80"] +impl crate::Resettable for XOSC32K_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x80 + } +} diff --git a/pac/atsamc21g/src/oscctrl.rs b/pac/atsamc21g/src/oscctrl.rs new file mode 100644 index 000000000000..e6dd0929927c --- /dev/null +++ b/pac/atsamc21g/src/oscctrl.rs @@ -0,0 +1,117 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x04 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x08 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x0c - Power and Clocks Status"] + pub status: crate::Reg, + #[doc = "0x10 - External Multipurpose Crystal Oscillator (XOSC) Control"] + pub xoscctrl: crate::Reg, + #[doc = "0x12 - Clock Failure Detector Prescaler"] + pub cfdpresc: crate::Reg, + #[doc = "0x13 - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x14 - 48MHz Internal Oscillator (OSC48M) Control"] + pub osc48mctrl: crate::Reg, + #[doc = "0x15 - OSC48M Divider"] + pub osc48mdiv: crate::Reg, + #[doc = "0x16 - OSC48M Startup Time"] + pub osc48mstup: crate::Reg, + _reserved10: [u8; 0x01], + #[doc = "0x18 - OSC48M Synchronization Busy"] + pub osc48msyncbusy: crate::Reg, + #[doc = "0x1c - DPLL Control"] + pub dpllctrla: crate::Reg, + _reserved12: [u8; 0x03], + #[doc = "0x20 - DPLL Ratio Control"] + pub dpllratio: crate::Reg, + #[doc = "0x24 - Digital Core Configuration"] + pub dpllctrlb: crate::Reg, + #[doc = "0x28 - DPLL Prescaler"] + pub dpllpresc: crate::Reg, + _reserved15: [u8; 0x03], + #[doc = "0x2c - DPLL Synchronization Busy"] + pub dpllsyncbusy: crate::Reg, + _reserved16: [u8; 0x03], + #[doc = "0x30 - DPLL Status"] + pub dpllstatus: crate::Reg, + _reserved17: [u8; 0x07], + #[doc = "0x38 - 48MHz Oscillator Calibration"] + pub cal48m: crate::Reg, +} +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Power and Clocks Status"] +pub mod status; +#[doc = "XOSCCTRL register accessor: an alias for `Reg`"] +pub type XOSCCTRL = crate::Reg; +#[doc = "External Multipurpose Crystal Oscillator (XOSC) Control"] +pub mod xoscctrl; +#[doc = "CFDPRESC register accessor: an alias for `Reg`"] +pub type CFDPRESC = crate::Reg; +#[doc = "Clock Failure Detector Prescaler"] +pub mod cfdpresc; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "OSC48MCTRL register accessor: an alias for `Reg`"] +pub type OSC48MCTRL = crate::Reg; +#[doc = "48MHz Internal Oscillator (OSC48M) Control"] +pub mod osc48mctrl; +#[doc = "OSC48MDIV register accessor: an alias for `Reg`"] +pub type OSC48MDIV = crate::Reg; +#[doc = "OSC48M Divider"] +pub mod osc48mdiv; +#[doc = "OSC48MSTUP register accessor: an alias for `Reg`"] +pub type OSC48MSTUP = crate::Reg; +#[doc = "OSC48M Startup Time"] +pub mod osc48mstup; +#[doc = "OSC48MSYNCBUSY register accessor: an alias for `Reg`"] +pub type OSC48MSYNCBUSY = crate::Reg; +#[doc = "OSC48M Synchronization Busy"] +pub mod osc48msyncbusy; +#[doc = "DPLLCTRLA register accessor: an alias for `Reg`"] +pub type DPLLCTRLA = crate::Reg; +#[doc = "DPLL Control"] +pub mod dpllctrla; +#[doc = "DPLLRATIO register accessor: an alias for `Reg`"] +pub type DPLLRATIO = crate::Reg; +#[doc = "DPLL Ratio Control"] +pub mod dpllratio; +#[doc = "DPLLCTRLB register accessor: an alias for `Reg`"] +pub type DPLLCTRLB = crate::Reg; +#[doc = "Digital Core Configuration"] +pub mod dpllctrlb; +#[doc = "DPLLPRESC register accessor: an alias for `Reg`"] +pub type DPLLPRESC = crate::Reg; +#[doc = "DPLL Prescaler"] +pub mod dpllpresc; +#[doc = "DPLLSYNCBUSY register accessor: an alias for `Reg`"] +pub type DPLLSYNCBUSY = crate::Reg; +#[doc = "DPLL Synchronization Busy"] +pub mod dpllsyncbusy; +#[doc = "DPLLSTATUS register accessor: an alias for `Reg`"] +pub type DPLLSTATUS = crate::Reg; +#[doc = "DPLL Status"] +pub mod dpllstatus; +#[doc = "CAL48M register accessor: an alias for `Reg`"] +pub type CAL48M = crate::Reg; +#[doc = "48MHz Oscillator Calibration"] +pub mod cal48m; diff --git a/pac/atsamc21g/src/oscctrl/cal48m.rs b/pac/atsamc21g/src/oscctrl/cal48m.rs new file mode 100644 index 000000000000..05d5cd2bbc92 --- /dev/null +++ b/pac/atsamc21g/src/oscctrl/cal48m.rs @@ -0,0 +1,177 @@ +#[doc = "Register `CAL48M` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CAL48M` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FCAL` reader - Frequency Calibration (48MHz)"] +pub struct FCAL_R(crate::FieldReader); +impl FCAL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FCAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FCAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FCAL` writer - Frequency Calibration (48MHz)"] +pub struct FCAL_W<'a> { + w: &'a mut W, +} +impl<'a> FCAL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +#[doc = "Field `FRANGE` reader - Frequency Range (48MHz)"] +pub struct FRANGE_R(crate::FieldReader); +impl FRANGE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FRANGE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FRANGE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FRANGE` writer - Frequency Range (48MHz)"] +pub struct FRANGE_W<'a> { + w: &'a mut W, +} +impl<'a> FRANGE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 8)) | ((value as u32 & 0x03) << 8); + self.w + } +} +#[doc = "Field `TCAL` reader - Temperature Calibration (48MHz)"] +pub struct TCAL_R(crate::FieldReader); +impl TCAL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TCAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCAL` writer - Temperature Calibration (48MHz)"] +pub struct TCAL_W<'a> { + w: &'a mut W, +} +impl<'a> TCAL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 16)) | ((value as u32 & 0x3f) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Frequency Calibration (48MHz)"] + #[inline(always)] + pub fn fcal(&self) -> FCAL_R { + FCAL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 8:9 - Frequency Range (48MHz)"] + #[inline(always)] + pub fn frange(&self) -> FRANGE_R { + FRANGE_R::new(((self.bits >> 8) & 0x03) as u8) + } + #[doc = "Bits 16:21 - Temperature Calibration (48MHz)"] + #[inline(always)] + pub fn tcal(&self) -> TCAL_R { + TCAL_R::new(((self.bits >> 16) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - Frequency Calibration (48MHz)"] + #[inline(always)] + pub fn fcal(&mut self) -> FCAL_W { + FCAL_W { w: self } + } + #[doc = "Bits 8:9 - Frequency Range (48MHz)"] + #[inline(always)] + pub fn frange(&mut self) -> FRANGE_W { + FRANGE_W { w: self } + } + #[doc = "Bits 16:21 - Temperature Calibration (48MHz)"] + #[inline(always)] + pub fn tcal(&mut self) -> TCAL_W { + TCAL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "48MHz Oscillator Calibration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cal48m](index.html) module"] +pub struct CAL48M_SPEC; +impl crate::RegisterSpec for CAL48M_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cal48m::R](R) reader structure"] +impl crate::Readable for CAL48M_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cal48m::W](W) writer structure"] +impl crate::Writable for CAL48M_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CAL48M to value 0"] +impl crate::Resettable for CAL48M_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/oscctrl/cfdpresc.rs b/pac/atsamc21g/src/oscctrl/cfdpresc.rs new file mode 100644 index 000000000000..029ae541eec5 --- /dev/null +++ b/pac/atsamc21g/src/oscctrl/cfdpresc.rs @@ -0,0 +1,230 @@ +#[doc = "Register `CFDPRESC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CFDPRESC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Clock Failure Detector Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CFDPRESC_A { + #[doc = "0: 48 MHz"] + DIV1 = 0, + #[doc = "1: 24 MHz"] + DIV2 = 1, + #[doc = "2: 12 MHz"] + DIV4 = 2, + #[doc = "3: 6 MHz"] + DIV8 = 3, + #[doc = "4: 3 MHz"] + DIV16 = 4, + #[doc = "5: 1.5 MHz"] + DIV32 = 5, + #[doc = "6: 0.75 MHz"] + DIV64 = 6, + #[doc = "7: 0.3125 MHz"] + DIV128 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CFDPRESC_A) -> Self { + variant as _ + } +} +#[doc = "Field `CFDPRESC` reader - Clock Failure Detector Prescaler"] +pub struct CFDPRESC_R(crate::FieldReader); +impl CFDPRESC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CFDPRESC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CFDPRESC_A { + match self.bits { + 0 => CFDPRESC_A::DIV1, + 1 => CFDPRESC_A::DIV2, + 2 => CFDPRESC_A::DIV4, + 3 => CFDPRESC_A::DIV8, + 4 => CFDPRESC_A::DIV16, + 5 => CFDPRESC_A::DIV32, + 6 => CFDPRESC_A::DIV64, + 7 => CFDPRESC_A::DIV128, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == CFDPRESC_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == CFDPRESC_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == CFDPRESC_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == CFDPRESC_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == CFDPRESC_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == CFDPRESC_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == CFDPRESC_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == CFDPRESC_A::DIV128 + } +} +impl core::ops::Deref for CFDPRESC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFDPRESC` writer - Clock Failure Detector Prescaler"] +pub struct CFDPRESC_W<'a> { + w: &'a mut W, +} +impl<'a> CFDPRESC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CFDPRESC_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "48 MHz"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(CFDPRESC_A::DIV1) + } + #[doc = "24 MHz"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(CFDPRESC_A::DIV2) + } + #[doc = "12 MHz"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(CFDPRESC_A::DIV4) + } + #[doc = "6 MHz"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(CFDPRESC_A::DIV8) + } + #[doc = "3 MHz"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(CFDPRESC_A::DIV16) + } + #[doc = "1.5 MHz"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(CFDPRESC_A::DIV32) + } + #[doc = "0.75 MHz"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(CFDPRESC_A::DIV64) + } + #[doc = "0.3125 MHz"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(CFDPRESC_A::DIV128) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Clock Failure Detector Prescaler"] + #[inline(always)] + pub fn cfdpresc(&self) -> CFDPRESC_R { + CFDPRESC_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Clock Failure Detector Prescaler"] + #[inline(always)] + pub fn cfdpresc(&mut self) -> CFDPRESC_W { + CFDPRESC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Clock Failure Detector Prescaler\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cfdpresc](index.html) module"] +pub struct CFDPRESC_SPEC; +impl crate::RegisterSpec for CFDPRESC_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [cfdpresc::R](R) reader structure"] +impl crate::Readable for CFDPRESC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cfdpresc::W](W) writer structure"] +impl crate::Writable for CFDPRESC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CFDPRESC to value 0"] +impl crate::Resettable for CFDPRESC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/oscctrl/dpllctrla.rs b/pac/atsamc21g/src/oscctrl/dpllctrla.rs new file mode 100644 index 000000000000..5a60a5087002 --- /dev/null +++ b/pac/atsamc21g/src/oscctrl/dpllctrla.rs @@ -0,0 +1,207 @@ +#[doc = "Register `DPLLCTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DPLLCTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - On Demand"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - On Demand"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - On Demand"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - On Demand"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DPLL Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dpllctrla](index.html) module"] +pub struct DPLLCTRLA_SPEC; +impl crate::RegisterSpec for DPLLCTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dpllctrla::R](R) reader structure"] +impl crate::Readable for DPLLCTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dpllctrla::W](W) writer structure"] +impl crate::Writable for DPLLCTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DPLLCTRLA to value 0x80"] +impl crate::Resettable for DPLLCTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x80 + } +} diff --git a/pac/atsamc21g/src/oscctrl/dpllctrlb.rs b/pac/atsamc21g/src/oscctrl/dpllctrlb.rs new file mode 100644 index 000000000000..8400b0572dd0 --- /dev/null +++ b/pac/atsamc21g/src/oscctrl/dpllctrlb.rs @@ -0,0 +1,580 @@ +#[doc = "Register `DPLLCTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DPLLCTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Proportional Integral Filter Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FILTER_A { + #[doc = "0: Default filter mode"] + DEFAULT = 0, + #[doc = "1: Low bandwidth filter"] + LBFILT = 1, + #[doc = "2: High bandwidth filter"] + HBFILT = 2, + #[doc = "3: High damping filter"] + HDFILT = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FILTER_A) -> Self { + variant as _ + } +} +#[doc = "Field `FILTER` reader - Proportional Integral Filter Selection"] +pub struct FILTER_R(crate::FieldReader); +impl FILTER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FILTER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FILTER_A { + match self.bits { + 0 => FILTER_A::DEFAULT, + 1 => FILTER_A::LBFILT, + 2 => FILTER_A::HBFILT, + 3 => FILTER_A::HDFILT, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DEFAULT`"] + #[inline(always)] + pub fn is_default(&self) -> bool { + **self == FILTER_A::DEFAULT + } + #[doc = "Checks if the value of the field is `LBFILT`"] + #[inline(always)] + pub fn is_lbfilt(&self) -> bool { + **self == FILTER_A::LBFILT + } + #[doc = "Checks if the value of the field is `HBFILT`"] + #[inline(always)] + pub fn is_hbfilt(&self) -> bool { + **self == FILTER_A::HBFILT + } + #[doc = "Checks if the value of the field is `HDFILT`"] + #[inline(always)] + pub fn is_hdfilt(&self) -> bool { + **self == FILTER_A::HDFILT + } +} +impl core::ops::Deref for FILTER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTER` writer - Proportional Integral Filter Selection"] +pub struct FILTER_W<'a> { + w: &'a mut W, +} +impl<'a> FILTER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FILTER_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Default filter mode"] + #[inline(always)] + pub fn default(self) -> &'a mut W { + self.variant(FILTER_A::DEFAULT) + } + #[doc = "Low bandwidth filter"] + #[inline(always)] + pub fn lbfilt(self) -> &'a mut W { + self.variant(FILTER_A::LBFILT) + } + #[doc = "High bandwidth filter"] + #[inline(always)] + pub fn hbfilt(self) -> &'a mut W { + self.variant(FILTER_A::HBFILT) + } + #[doc = "High damping filter"] + #[inline(always)] + pub fn hdfilt(self) -> &'a mut W { + self.variant(FILTER_A::HDFILT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u32 & 0x03); + self.w + } +} +#[doc = "Field `LPEN` reader - Low-Power Enable"] +pub struct LPEN_R(crate::FieldReader); +impl LPEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LPEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LPEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LPEN` writer - Low-Power Enable"] +pub struct LPEN_W<'a> { + w: &'a mut W, +} +impl<'a> LPEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `WUF` reader - Wake Up Fast"] +pub struct WUF_R(crate::FieldReader); +impl WUF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WUF` writer - Wake Up Fast"] +pub struct WUF_W<'a> { + w: &'a mut W, +} +impl<'a> WUF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Reference Clock Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum REFCLK_A { + #[doc = "0: XOSC32K clock reference"] + XOSC32K = 0, + #[doc = "1: XOSC clock reference"] + XOSC = 1, + #[doc = "2: GCLK clock reference"] + GCLK = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: REFCLK_A) -> Self { + variant as _ + } +} +#[doc = "Field `REFCLK` reader - Reference Clock Selection"] +pub struct REFCLK_R(crate::FieldReader); +impl REFCLK_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REFCLK_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(REFCLK_A::XOSC32K), + 1 => Some(REFCLK_A::XOSC), + 2 => Some(REFCLK_A::GCLK), + _ => None, + } + } + #[doc = "Checks if the value of the field is `XOSC32K`"] + #[inline(always)] + pub fn is_xosc32k(&self) -> bool { + **self == REFCLK_A::XOSC32K + } + #[doc = "Checks if the value of the field is `XOSC`"] + #[inline(always)] + pub fn is_xosc(&self) -> bool { + **self == REFCLK_A::XOSC + } + #[doc = "Checks if the value of the field is `GCLK`"] + #[inline(always)] + pub fn is_gclk(&self) -> bool { + **self == REFCLK_A::GCLK + } +} +impl core::ops::Deref for REFCLK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REFCLK` writer - Reference Clock Selection"] +pub struct REFCLK_W<'a> { + w: &'a mut W, +} +impl<'a> REFCLK_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: REFCLK_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "XOSC32K clock reference"] + #[inline(always)] + pub fn xosc32k(self) -> &'a mut W { + self.variant(REFCLK_A::XOSC32K) + } + #[doc = "XOSC clock reference"] + #[inline(always)] + pub fn xosc(self) -> &'a mut W { + self.variant(REFCLK_A::XOSC) + } + #[doc = "GCLK clock reference"] + #[inline(always)] + pub fn gclk(self) -> &'a mut W { + self.variant(REFCLK_A::GCLK) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u32 & 0x03) << 4); + self.w + } +} +#[doc = "Lock Time\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum LTIME_A { + #[doc = "0: No time-out. Automatic lock."] + DEFAULT = 0, + #[doc = "4: Time-out if no lock within 8ms"] + _8MS = 4, + #[doc = "5: Time-out if no lock within 9ms"] + _9MS = 5, + #[doc = "6: Time-out if no lock within 10ms"] + _10MS = 6, + #[doc = "7: Time-out if no lock within 11ms"] + _11MS = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LTIME_A) -> Self { + variant as _ + } +} +#[doc = "Field `LTIME` reader - Lock Time"] +pub struct LTIME_R(crate::FieldReader); +impl LTIME_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LTIME_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(LTIME_A::DEFAULT), + 4 => Some(LTIME_A::_8MS), + 5 => Some(LTIME_A::_9MS), + 6 => Some(LTIME_A::_10MS), + 7 => Some(LTIME_A::_11MS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DEFAULT`"] + #[inline(always)] + pub fn is_default(&self) -> bool { + **self == LTIME_A::DEFAULT + } + #[doc = "Checks if the value of the field is `_8MS`"] + #[inline(always)] + pub fn is_8ms(&self) -> bool { + **self == LTIME_A::_8MS + } + #[doc = "Checks if the value of the field is `_9MS`"] + #[inline(always)] + pub fn is_9ms(&self) -> bool { + **self == LTIME_A::_9MS + } + #[doc = "Checks if the value of the field is `_10MS`"] + #[inline(always)] + pub fn is_10ms(&self) -> bool { + **self == LTIME_A::_10MS + } + #[doc = "Checks if the value of the field is `_11MS`"] + #[inline(always)] + pub fn is_11ms(&self) -> bool { + **self == LTIME_A::_11MS + } +} +impl core::ops::Deref for LTIME_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LTIME` writer - Lock Time"] +pub struct LTIME_W<'a> { + w: &'a mut W, +} +impl<'a> LTIME_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: LTIME_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No time-out. Automatic lock."] + #[inline(always)] + pub fn default(self) -> &'a mut W { + self.variant(LTIME_A::DEFAULT) + } + #[doc = "Time-out if no lock within 8ms"] + #[inline(always)] + pub fn _8ms(self) -> &'a mut W { + self.variant(LTIME_A::_8MS) + } + #[doc = "Time-out if no lock within 9ms"] + #[inline(always)] + pub fn _9ms(self) -> &'a mut W { + self.variant(LTIME_A::_9MS) + } + #[doc = "Time-out if no lock within 10ms"] + #[inline(always)] + pub fn _10ms(self) -> &'a mut W { + self.variant(LTIME_A::_10MS) + } + #[doc = "Time-out if no lock within 11ms"] + #[inline(always)] + pub fn _11ms(self) -> &'a mut W { + self.variant(LTIME_A::_11MS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +#[doc = "Field `LBYPASS` reader - Lock Bypass"] +pub struct LBYPASS_R(crate::FieldReader); +impl LBYPASS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LBYPASS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LBYPASS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LBYPASS` writer - Lock Bypass"] +pub struct LBYPASS_W<'a> { + w: &'a mut W, +} +impl<'a> LBYPASS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `DIV` reader - Clock Divider"] +pub struct DIV_R(crate::FieldReader); +impl DIV_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + DIV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIV` writer - Clock Divider"] +pub struct DIV_W<'a> { + w: &'a mut W, +} +impl<'a> DIV_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07ff << 16)) | ((value as u32 & 0x07ff) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Proportional Integral Filter Selection"] + #[inline(always)] + pub fn filter(&self) -> FILTER_R { + FILTER_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bit 2 - Low-Power Enable"] + #[inline(always)] + pub fn lpen(&self) -> LPEN_R { + LPEN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Wake Up Fast"] + #[inline(always)] + pub fn wuf(&self) -> WUF_R { + WUF_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bits 4:5 - Reference Clock Selection"] + #[inline(always)] + pub fn refclk(&self) -> REFCLK_R { + REFCLK_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bits 8:10 - Lock Time"] + #[inline(always)] + pub fn ltime(&self) -> LTIME_R { + LTIME_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 12 - Lock Bypass"] + #[inline(always)] + pub fn lbypass(&self) -> LBYPASS_R { + LBYPASS_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bits 16:26 - Clock Divider"] + #[inline(always)] + pub fn div(&self) -> DIV_R { + DIV_R::new(((self.bits >> 16) & 0x07ff) as u16) + } +} +impl W { + #[doc = "Bits 0:1 - Proportional Integral Filter Selection"] + #[inline(always)] + pub fn filter(&mut self) -> FILTER_W { + FILTER_W { w: self } + } + #[doc = "Bit 2 - Low-Power Enable"] + #[inline(always)] + pub fn lpen(&mut self) -> LPEN_W { + LPEN_W { w: self } + } + #[doc = "Bit 3 - Wake Up Fast"] + #[inline(always)] + pub fn wuf(&mut self) -> WUF_W { + WUF_W { w: self } + } + #[doc = "Bits 4:5 - Reference Clock Selection"] + #[inline(always)] + pub fn refclk(&mut self) -> REFCLK_W { + REFCLK_W { w: self } + } + #[doc = "Bits 8:10 - Lock Time"] + #[inline(always)] + pub fn ltime(&mut self) -> LTIME_W { + LTIME_W { w: self } + } + #[doc = "Bit 12 - Lock Bypass"] + #[inline(always)] + pub fn lbypass(&mut self) -> LBYPASS_W { + LBYPASS_W { w: self } + } + #[doc = "Bits 16:26 - Clock Divider"] + #[inline(always)] + pub fn div(&mut self) -> DIV_W { + DIV_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Digital Core Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dpllctrlb](index.html) module"] +pub struct DPLLCTRLB_SPEC; +impl crate::RegisterSpec for DPLLCTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dpllctrlb::R](R) reader structure"] +impl crate::Readable for DPLLCTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dpllctrlb::W](W) writer structure"] +impl crate::Writable for DPLLCTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DPLLCTRLB to value 0"] +impl crate::Resettable for DPLLCTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/oscctrl/dpllpresc.rs b/pac/atsamc21g/src/oscctrl/dpllpresc.rs new file mode 100644 index 000000000000..9de662161f99 --- /dev/null +++ b/pac/atsamc21g/src/oscctrl/dpllpresc.rs @@ -0,0 +1,165 @@ +#[doc = "Register `DPLLPRESC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DPLLPRESC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Output Clock Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESC_A { + #[doc = "0: DPLL output is divided by 1"] + DIV1 = 0, + #[doc = "1: DPLL output is divided by 2"] + DIV2 = 1, + #[doc = "2: DPLL output is divided by 4"] + DIV4 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESC_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESC` reader - Output Clock Prescaler"] +pub struct PRESC_R(crate::FieldReader); +impl PRESC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESC_A::DIV1), + 1 => Some(PRESC_A::DIV2), + 2 => Some(PRESC_A::DIV4), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == PRESC_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESC_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESC_A::DIV4 + } +} +impl core::ops::Deref for PRESC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESC` writer - Output Clock Prescaler"] +pub struct PRESC_W<'a> { + w: &'a mut W, +} +impl<'a> PRESC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESC_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "DPLL output is divided by 1"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESC_A::DIV1) + } + #[doc = "DPLL output is divided by 2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESC_A::DIV2) + } + #[doc = "DPLL output is divided by 4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESC_A::DIV4) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u8 & 0x03); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Output Clock Prescaler"] + #[inline(always)] + pub fn presc(&self) -> PRESC_R { + PRESC_R::new((self.bits & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Output Clock Prescaler"] + #[inline(always)] + pub fn presc(&mut self) -> PRESC_W { + PRESC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DPLL Prescaler\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dpllpresc](index.html) module"] +pub struct DPLLPRESC_SPEC; +impl crate::RegisterSpec for DPLLPRESC_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dpllpresc::R](R) reader structure"] +impl crate::Readable for DPLLPRESC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dpllpresc::W](W) writer structure"] +impl crate::Writable for DPLLPRESC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DPLLPRESC to value 0"] +impl crate::Resettable for DPLLPRESC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/oscctrl/dpllratio.rs b/pac/atsamc21g/src/oscctrl/dpllratio.rs new file mode 100644 index 000000000000..93b39e30f1a5 --- /dev/null +++ b/pac/atsamc21g/src/oscctrl/dpllratio.rs @@ -0,0 +1,140 @@ +#[doc = "Register `DPLLRATIO` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DPLLRATIO` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `LDR` reader - Loop Divider Ratio"] +pub struct LDR_R(crate::FieldReader); +impl LDR_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + LDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LDR` writer - Loop Divider Ratio"] +pub struct LDR_W<'a> { + w: &'a mut W, +} +impl<'a> LDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0fff) | (value as u32 & 0x0fff); + self.w + } +} +#[doc = "Field `LDRFRAC` reader - Loop Divider Ratio Fractional Part"] +pub struct LDRFRAC_R(crate::FieldReader); +impl LDRFRAC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LDRFRAC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LDRFRAC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LDRFRAC` writer - Loop Divider Ratio Fractional Part"] +pub struct LDRFRAC_W<'a> { + w: &'a mut W, +} +impl<'a> LDRFRAC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 16)) | ((value as u32 & 0x0f) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:11 - Loop Divider Ratio"] + #[inline(always)] + pub fn ldr(&self) -> LDR_R { + LDR_R::new((self.bits & 0x0fff) as u16) + } + #[doc = "Bits 16:19 - Loop Divider Ratio Fractional Part"] + #[inline(always)] + pub fn ldrfrac(&self) -> LDRFRAC_R { + LDRFRAC_R::new(((self.bits >> 16) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:11 - Loop Divider Ratio"] + #[inline(always)] + pub fn ldr(&mut self) -> LDR_W { + LDR_W { w: self } + } + #[doc = "Bits 16:19 - Loop Divider Ratio Fractional Part"] + #[inline(always)] + pub fn ldrfrac(&mut self) -> LDRFRAC_W { + LDRFRAC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DPLL Ratio Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dpllratio](index.html) module"] +pub struct DPLLRATIO_SPEC; +impl crate::RegisterSpec for DPLLRATIO_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dpllratio::R](R) reader structure"] +impl crate::Readable for DPLLRATIO_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dpllratio::W](W) writer structure"] +impl crate::Writable for DPLLRATIO_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DPLLRATIO to value 0"] +impl crate::Resettable for DPLLRATIO_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/oscctrl/dpllstatus.rs b/pac/atsamc21g/src/oscctrl/dpllstatus.rs new file mode 100644 index 000000000000..931900212816 --- /dev/null +++ b/pac/atsamc21g/src/oscctrl/dpllstatus.rs @@ -0,0 +1,73 @@ +#[doc = "Register `DPLLSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `LOCK` reader - DPLL Lock Status"] +pub struct LOCK_R(crate::FieldReader); +impl LOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKRDY` reader - DPLL Clock Ready"] +pub struct CLKRDY_R(crate::FieldReader); +impl CLKRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - DPLL Lock Status"] + #[inline(always)] + pub fn lock(&self) -> LOCK_R { + LOCK_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - DPLL Clock Ready"] + #[inline(always)] + pub fn clkrdy(&self) -> CLKRDY_R { + CLKRDY_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +#[doc = "DPLL Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dpllstatus](index.html) module"] +pub struct DPLLSTATUS_SPEC; +impl crate::RegisterSpec for DPLLSTATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dpllstatus::R](R) reader structure"] +impl crate::Readable for DPLLSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DPLLSTATUS to value 0"] +impl crate::Resettable for DPLLSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/oscctrl/dpllsyncbusy.rs b/pac/atsamc21g/src/oscctrl/dpllsyncbusy.rs new file mode 100644 index 000000000000..f9fb880a5a59 --- /dev/null +++ b/pac/atsamc21g/src/oscctrl/dpllsyncbusy.rs @@ -0,0 +1,93 @@ +#[doc = "Register `DPLLSYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `ENABLE` reader - DPLL Enable Synchronization Status"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLRATIO` reader - DPLL Ratio Synchronization Status"] +pub struct DPLLRATIO_R(crate::FieldReader); +impl DPLLRATIO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLRATIO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLRATIO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLPRESC` reader - DPLL Prescaler Synchronization Status"] +pub struct DPLLPRESC_R(crate::FieldReader); +impl DPLLPRESC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLPRESC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLPRESC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 1 - DPLL Enable Synchronization Status"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - DPLL Ratio Synchronization Status"] + #[inline(always)] + pub fn dpllratio(&self) -> DPLLRATIO_R { + DPLLRATIO_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - DPLL Prescaler Synchronization Status"] + #[inline(always)] + pub fn dpllpresc(&self) -> DPLLPRESC_R { + DPLLPRESC_R::new(((self.bits >> 3) & 0x01) != 0) + } +} +#[doc = "DPLL Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dpllsyncbusy](index.html) module"] +pub struct DPLLSYNCBUSY_SPEC; +impl crate::RegisterSpec for DPLLSYNCBUSY_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dpllsyncbusy::R](R) reader structure"] +impl crate::Readable for DPLLSYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DPLLSYNCBUSY to value 0"] +impl crate::Resettable for DPLLSYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/oscctrl/evctrl.rs b/pac/atsamc21g/src/oscctrl/evctrl.rs new file mode 100644 index 000000000000..e22ba62f0fe2 --- /dev/null +++ b/pac/atsamc21g/src/oscctrl/evctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CFDEO` reader - Clock Failure Detector Event Output Enable"] +pub struct CFDEO_R(crate::FieldReader); +impl CFDEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFDEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFDEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFDEO` writer - Clock Failure Detector Event Output Enable"] +pub struct CFDEO_W<'a> { + w: &'a mut W, +} +impl<'a> CFDEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Clock Failure Detector Event Output Enable"] + #[inline(always)] + pub fn cfdeo(&self) -> CFDEO_R { + CFDEO_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Clock Failure Detector Event Output Enable"] + #[inline(always)] + pub fn cfdeo(&mut self) -> CFDEO_W { + CFDEO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/oscctrl/intenclr.rs b/pac/atsamc21g/src/oscctrl/intenclr.rs new file mode 100644 index 000000000000..0ea0034a0c02 --- /dev/null +++ b/pac/atsamc21g/src/oscctrl/intenclr.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XOSCRDY` reader - XOSC Ready Interrupt Enable"] +pub struct XOSCRDY_R(crate::FieldReader); +impl XOSCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSCRDY` writer - XOSC Ready Interrupt Enable"] +pub struct XOSCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> XOSCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `XOSCFAIL` reader - XOSC Clock Failure Detector Interrupt Enable"] +pub struct XOSCFAIL_R(crate::FieldReader); +impl XOSCFAIL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSCFAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCFAIL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSCFAIL` writer - XOSC Clock Failure Detector Interrupt Enable"] +pub struct XOSCFAIL_W<'a> { + w: &'a mut W, +} +impl<'a> XOSCFAIL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `OSC48MRDY` reader - OSC48M Ready Interrupt Enable"] +pub struct OSC48MRDY_R(crate::FieldReader); +impl OSC48MRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC48MRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC48MRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC48MRDY` writer - OSC48M Ready Interrupt Enable"] +pub struct OSC48MRDY_W<'a> { + w: &'a mut W, +} +impl<'a> OSC48MRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `DPLLLCKR` reader - DPLL Lock Rise Interrupt Enable"] +pub struct DPLLLCKR_R(crate::FieldReader); +impl DPLLLCKR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKR` writer - DPLL Lock Rise Interrupt Enable"] +pub struct DPLLLCKR_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLCKR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `DPLLLCKF` reader - DPLL Lock Fall Interrupt Enable"] +pub struct DPLLLCKF_R(crate::FieldReader); +impl DPLLLCKF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKF` writer - DPLL Lock Fall Interrupt Enable"] +pub struct DPLLLCKF_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLCKF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `DPLLLTO` reader - DPLL Time Out Interrupt Enable"] +pub struct DPLLLTO_R(crate::FieldReader); +impl DPLLLTO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLTO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLTO` writer - DPLL Time Out Interrupt Enable"] +pub struct DPLLLTO_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLTO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `DPLLLDRTO` reader - DPLL Ratio Ready Interrupt Enable"] +pub struct DPLLLDRTO_R(crate::FieldReader); +impl DPLLLDRTO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLDRTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLDRTO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLDRTO` writer - DPLL Ratio Ready Interrupt Enable"] +pub struct DPLLLDRTO_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLDRTO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +impl R { + #[doc = "Bit 0 - XOSC Ready Interrupt Enable"] + #[inline(always)] + pub fn xoscrdy(&self) -> XOSCRDY_R { + XOSCRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - XOSC Clock Failure Detector Interrupt Enable"] + #[inline(always)] + pub fn xoscfail(&self) -> XOSCFAIL_R { + XOSCFAIL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - OSC48M Ready Interrupt Enable"] + #[inline(always)] + pub fn osc48mrdy(&self) -> OSC48MRDY_R { + OSC48MRDY_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 8 - DPLL Lock Rise Interrupt Enable"] + #[inline(always)] + pub fn dplllckr(&self) -> DPLLLCKR_R { + DPLLLCKR_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - DPLL Lock Fall Interrupt Enable"] + #[inline(always)] + pub fn dplllckf(&self) -> DPLLLCKF_R { + DPLLLCKF_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - DPLL Time Out Interrupt Enable"] + #[inline(always)] + pub fn dplllto(&self) -> DPLLLTO_R { + DPLLLTO_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - DPLL Ratio Ready Interrupt Enable"] + #[inline(always)] + pub fn dpllldrto(&self) -> DPLLLDRTO_R { + DPLLLDRTO_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - XOSC Ready Interrupt Enable"] + #[inline(always)] + pub fn xoscrdy(&mut self) -> XOSCRDY_W { + XOSCRDY_W { w: self } + } + #[doc = "Bit 1 - XOSC Clock Failure Detector Interrupt Enable"] + #[inline(always)] + pub fn xoscfail(&mut self) -> XOSCFAIL_W { + XOSCFAIL_W { w: self } + } + #[doc = "Bit 4 - OSC48M Ready Interrupt Enable"] + #[inline(always)] + pub fn osc48mrdy(&mut self) -> OSC48MRDY_W { + OSC48MRDY_W { w: self } + } + #[doc = "Bit 8 - DPLL Lock Rise Interrupt Enable"] + #[inline(always)] + pub fn dplllckr(&mut self) -> DPLLLCKR_W { + DPLLLCKR_W { w: self } + } + #[doc = "Bit 9 - DPLL Lock Fall Interrupt Enable"] + #[inline(always)] + pub fn dplllckf(&mut self) -> DPLLLCKF_W { + DPLLLCKF_W { w: self } + } + #[doc = "Bit 10 - DPLL Time Out Interrupt Enable"] + #[inline(always)] + pub fn dplllto(&mut self) -> DPLLLTO_W { + DPLLLTO_W { w: self } + } + #[doc = "Bit 11 - DPLL Ratio Ready Interrupt Enable"] + #[inline(always)] + pub fn dpllldrto(&mut self) -> DPLLLDRTO_W { + DPLLLDRTO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/oscctrl/intenset.rs b/pac/atsamc21g/src/oscctrl/intenset.rs new file mode 100644 index 000000000000..2890541e4414 --- /dev/null +++ b/pac/atsamc21g/src/oscctrl/intenset.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XOSCRDY` reader - XOSC Ready Interrupt Enable"] +pub struct XOSCRDY_R(crate::FieldReader); +impl XOSCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSCRDY` writer - XOSC Ready Interrupt Enable"] +pub struct XOSCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> XOSCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `XOSCFAIL` reader - XOSC Clock Failure Detector Interrupt Enable"] +pub struct XOSCFAIL_R(crate::FieldReader); +impl XOSCFAIL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSCFAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCFAIL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSCFAIL` writer - XOSC Clock Failure Detector Interrupt Enable"] +pub struct XOSCFAIL_W<'a> { + w: &'a mut W, +} +impl<'a> XOSCFAIL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `OSC48MRDY` reader - OSC48M Ready Interrupt Enable"] +pub struct OSC48MRDY_R(crate::FieldReader); +impl OSC48MRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC48MRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC48MRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC48MRDY` writer - OSC48M Ready Interrupt Enable"] +pub struct OSC48MRDY_W<'a> { + w: &'a mut W, +} +impl<'a> OSC48MRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `DPLLLCKR` reader - DPLL Lock Rise Interrupt Enable"] +pub struct DPLLLCKR_R(crate::FieldReader); +impl DPLLLCKR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKR` writer - DPLL Lock Rise Interrupt Enable"] +pub struct DPLLLCKR_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLCKR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `DPLLLCKF` reader - DPLL Lock Fall Interrupt Enable"] +pub struct DPLLLCKF_R(crate::FieldReader); +impl DPLLLCKF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKF` writer - DPLL Lock Fall Interrupt Enable"] +pub struct DPLLLCKF_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLCKF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `DPLLLTO` reader - DPLL Time Out Interrupt Enable"] +pub struct DPLLLTO_R(crate::FieldReader); +impl DPLLLTO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLTO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLTO` writer - DPLL Time Out Interrupt Enable"] +pub struct DPLLLTO_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLTO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `DPLLLDRTO` reader - DPLL Ratio Ready Interrupt Enable"] +pub struct DPLLLDRTO_R(crate::FieldReader); +impl DPLLLDRTO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLDRTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLDRTO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLDRTO` writer - DPLL Ratio Ready Interrupt Enable"] +pub struct DPLLLDRTO_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLDRTO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +impl R { + #[doc = "Bit 0 - XOSC Ready Interrupt Enable"] + #[inline(always)] + pub fn xoscrdy(&self) -> XOSCRDY_R { + XOSCRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - XOSC Clock Failure Detector Interrupt Enable"] + #[inline(always)] + pub fn xoscfail(&self) -> XOSCFAIL_R { + XOSCFAIL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - OSC48M Ready Interrupt Enable"] + #[inline(always)] + pub fn osc48mrdy(&self) -> OSC48MRDY_R { + OSC48MRDY_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 8 - DPLL Lock Rise Interrupt Enable"] + #[inline(always)] + pub fn dplllckr(&self) -> DPLLLCKR_R { + DPLLLCKR_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - DPLL Lock Fall Interrupt Enable"] + #[inline(always)] + pub fn dplllckf(&self) -> DPLLLCKF_R { + DPLLLCKF_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - DPLL Time Out Interrupt Enable"] + #[inline(always)] + pub fn dplllto(&self) -> DPLLLTO_R { + DPLLLTO_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - DPLL Ratio Ready Interrupt Enable"] + #[inline(always)] + pub fn dpllldrto(&self) -> DPLLLDRTO_R { + DPLLLDRTO_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - XOSC Ready Interrupt Enable"] + #[inline(always)] + pub fn xoscrdy(&mut self) -> XOSCRDY_W { + XOSCRDY_W { w: self } + } + #[doc = "Bit 1 - XOSC Clock Failure Detector Interrupt Enable"] + #[inline(always)] + pub fn xoscfail(&mut self) -> XOSCFAIL_W { + XOSCFAIL_W { w: self } + } + #[doc = "Bit 4 - OSC48M Ready Interrupt Enable"] + #[inline(always)] + pub fn osc48mrdy(&mut self) -> OSC48MRDY_W { + OSC48MRDY_W { w: self } + } + #[doc = "Bit 8 - DPLL Lock Rise Interrupt Enable"] + #[inline(always)] + pub fn dplllckr(&mut self) -> DPLLLCKR_W { + DPLLLCKR_W { w: self } + } + #[doc = "Bit 9 - DPLL Lock Fall Interrupt Enable"] + #[inline(always)] + pub fn dplllckf(&mut self) -> DPLLLCKF_W { + DPLLLCKF_W { w: self } + } + #[doc = "Bit 10 - DPLL Time Out Interrupt Enable"] + #[inline(always)] + pub fn dplllto(&mut self) -> DPLLLTO_W { + DPLLLTO_W { w: self } + } + #[doc = "Bit 11 - DPLL Ratio Ready Interrupt Enable"] + #[inline(always)] + pub fn dpllldrto(&mut self) -> DPLLLDRTO_W { + DPLLLDRTO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/oscctrl/intflag.rs b/pac/atsamc21g/src/oscctrl/intflag.rs new file mode 100644 index 000000000000..71e452a1b571 --- /dev/null +++ b/pac/atsamc21g/src/oscctrl/intflag.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XOSCRDY` reader - XOSC Ready"] +pub struct XOSCRDY_R(crate::FieldReader); +impl XOSCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSCRDY` writer - XOSC Ready"] +pub struct XOSCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> XOSCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `XOSCFAIL` reader - XOSC Clock Failure Detector"] +pub struct XOSCFAIL_R(crate::FieldReader); +impl XOSCFAIL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSCFAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCFAIL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSCFAIL` writer - XOSC Clock Failure Detector"] +pub struct XOSCFAIL_W<'a> { + w: &'a mut W, +} +impl<'a> XOSCFAIL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `OSC48MRDY` reader - OSC48M Ready"] +pub struct OSC48MRDY_R(crate::FieldReader); +impl OSC48MRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC48MRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC48MRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC48MRDY` writer - OSC48M Ready"] +pub struct OSC48MRDY_W<'a> { + w: &'a mut W, +} +impl<'a> OSC48MRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `DPLLLCKR` reader - DPLL Lock Rise"] +pub struct DPLLLCKR_R(crate::FieldReader); +impl DPLLLCKR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKR` writer - DPLL Lock Rise"] +pub struct DPLLLCKR_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLCKR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `DPLLLCKF` reader - DPLL Lock Fall"] +pub struct DPLLLCKF_R(crate::FieldReader); +impl DPLLLCKF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKF` writer - DPLL Lock Fall"] +pub struct DPLLLCKF_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLCKF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `DPLLLTO` reader - DPLL Timeout"] +pub struct DPLLLTO_R(crate::FieldReader); +impl DPLLLTO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLTO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLTO` writer - DPLL Timeout"] +pub struct DPLLLTO_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLTO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `DPLLLDRTO` reader - DPLL Ratio Ready"] +pub struct DPLLLDRTO_R(crate::FieldReader); +impl DPLLLDRTO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLDRTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLDRTO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLDRTO` writer - DPLL Ratio Ready"] +pub struct DPLLLDRTO_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLDRTO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +impl R { + #[doc = "Bit 0 - XOSC Ready"] + #[inline(always)] + pub fn xoscrdy(&self) -> XOSCRDY_R { + XOSCRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - XOSC Clock Failure Detector"] + #[inline(always)] + pub fn xoscfail(&self) -> XOSCFAIL_R { + XOSCFAIL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - OSC48M Ready"] + #[inline(always)] + pub fn osc48mrdy(&self) -> OSC48MRDY_R { + OSC48MRDY_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 8 - DPLL Lock Rise"] + #[inline(always)] + pub fn dplllckr(&self) -> DPLLLCKR_R { + DPLLLCKR_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - DPLL Lock Fall"] + #[inline(always)] + pub fn dplllckf(&self) -> DPLLLCKF_R { + DPLLLCKF_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - DPLL Timeout"] + #[inline(always)] + pub fn dplllto(&self) -> DPLLLTO_R { + DPLLLTO_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - DPLL Ratio Ready"] + #[inline(always)] + pub fn dpllldrto(&self) -> DPLLLDRTO_R { + DPLLLDRTO_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - XOSC Ready"] + #[inline(always)] + pub fn xoscrdy(&mut self) -> XOSCRDY_W { + XOSCRDY_W { w: self } + } + #[doc = "Bit 1 - XOSC Clock Failure Detector"] + #[inline(always)] + pub fn xoscfail(&mut self) -> XOSCFAIL_W { + XOSCFAIL_W { w: self } + } + #[doc = "Bit 4 - OSC48M Ready"] + #[inline(always)] + pub fn osc48mrdy(&mut self) -> OSC48MRDY_W { + OSC48MRDY_W { w: self } + } + #[doc = "Bit 8 - DPLL Lock Rise"] + #[inline(always)] + pub fn dplllckr(&mut self) -> DPLLLCKR_W { + DPLLLCKR_W { w: self } + } + #[doc = "Bit 9 - DPLL Lock Fall"] + #[inline(always)] + pub fn dplllckf(&mut self) -> DPLLLCKF_W { + DPLLLCKF_W { w: self } + } + #[doc = "Bit 10 - DPLL Timeout"] + #[inline(always)] + pub fn dplllto(&mut self) -> DPLLLTO_W { + DPLLLTO_W { w: self } + } + #[doc = "Bit 11 - DPLL Ratio Ready"] + #[inline(always)] + pub fn dpllldrto(&mut self) -> DPLLLDRTO_W { + DPLLLDRTO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/oscctrl/osc48mctrl.rs b/pac/atsamc21g/src/oscctrl/osc48mctrl.rs new file mode 100644 index 000000000000..8314e21e5775 --- /dev/null +++ b/pac/atsamc21g/src/oscctrl/osc48mctrl.rs @@ -0,0 +1,207 @@ +#[doc = "Register `OSC48MCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OSC48MCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Oscillator Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Oscillator Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - On Demand Control"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - On Demand Control"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "48MHz Internal Oscillator (OSC48M) Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [osc48mctrl](index.html) module"] +pub struct OSC48MCTRL_SPEC; +impl crate::RegisterSpec for OSC48MCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [osc48mctrl::R](R) reader structure"] +impl crate::Readable for OSC48MCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [osc48mctrl::W](W) writer structure"] +impl crate::Writable for OSC48MCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OSC48MCTRL to value 0x82"] +impl crate::Resettable for OSC48MCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x82 + } +} diff --git a/pac/atsamc21g/src/oscctrl/osc48mdiv.rs b/pac/atsamc21g/src/oscctrl/osc48mdiv.rs new file mode 100644 index 000000000000..4ed854b09284 --- /dev/null +++ b/pac/atsamc21g/src/oscctrl/osc48mdiv.rs @@ -0,0 +1,334 @@ +#[doc = "Register `OSC48MDIV` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OSC48MDIV` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "OSC48M Division Factor\n\nValue on reset: 11"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DIV_A { + #[doc = "0: 48 MHz"] + DIV1 = 0, + #[doc = "1: 24 MHz"] + DIV2 = 1, + #[doc = "2: 16 MHz"] + DIV3 = 2, + #[doc = "3: 12 MHz"] + DIV4 = 3, + #[doc = "4: 9.6 MHz"] + DIV5 = 4, + #[doc = "5: 8 MHz"] + DIV6 = 5, + #[doc = "6: 6.86 MHz"] + DIV7 = 6, + #[doc = "7: 6 MHz"] + DIV8 = 7, + #[doc = "8: 5.33 MHz"] + DIV9 = 8, + #[doc = "9: 4.8 MHz"] + DIV10 = 9, + #[doc = "10: 4.36 MHz"] + DIV11 = 10, + #[doc = "11: 4 MHz"] + DIV12 = 11, + #[doc = "12: 3.69 MHz"] + DIV13 = 12, + #[doc = "13: 3.43 MHz"] + DIV14 = 13, + #[doc = "14: 3.2 MHz"] + DIV15 = 14, + #[doc = "15: 3 MHz"] + DIV16 = 15, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DIV_A) -> Self { + variant as _ + } +} +#[doc = "Field `DIV` reader - OSC48M Division Factor"] +pub struct DIV_R(crate::FieldReader); +impl DIV_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DIV_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DIV_A { + match self.bits { + 0 => DIV_A::DIV1, + 1 => DIV_A::DIV2, + 2 => DIV_A::DIV3, + 3 => DIV_A::DIV4, + 4 => DIV_A::DIV5, + 5 => DIV_A::DIV6, + 6 => DIV_A::DIV7, + 7 => DIV_A::DIV8, + 8 => DIV_A::DIV9, + 9 => DIV_A::DIV10, + 10 => DIV_A::DIV11, + 11 => DIV_A::DIV12, + 12 => DIV_A::DIV13, + 13 => DIV_A::DIV14, + 14 => DIV_A::DIV15, + 15 => DIV_A::DIV16, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == DIV_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == DIV_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV3`"] + #[inline(always)] + pub fn is_div3(&self) -> bool { + **self == DIV_A::DIV3 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == DIV_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV5`"] + #[inline(always)] + pub fn is_div5(&self) -> bool { + **self == DIV_A::DIV5 + } + #[doc = "Checks if the value of the field is `DIV6`"] + #[inline(always)] + pub fn is_div6(&self) -> bool { + **self == DIV_A::DIV6 + } + #[doc = "Checks if the value of the field is `DIV7`"] + #[inline(always)] + pub fn is_div7(&self) -> bool { + **self == DIV_A::DIV7 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == DIV_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV9`"] + #[inline(always)] + pub fn is_div9(&self) -> bool { + **self == DIV_A::DIV9 + } + #[doc = "Checks if the value of the field is `DIV10`"] + #[inline(always)] + pub fn is_div10(&self) -> bool { + **self == DIV_A::DIV10 + } + #[doc = "Checks if the value of the field is `DIV11`"] + #[inline(always)] + pub fn is_div11(&self) -> bool { + **self == DIV_A::DIV11 + } + #[doc = "Checks if the value of the field is `DIV12`"] + #[inline(always)] + pub fn is_div12(&self) -> bool { + **self == DIV_A::DIV12 + } + #[doc = "Checks if the value of the field is `DIV13`"] + #[inline(always)] + pub fn is_div13(&self) -> bool { + **self == DIV_A::DIV13 + } + #[doc = "Checks if the value of the field is `DIV14`"] + #[inline(always)] + pub fn is_div14(&self) -> bool { + **self == DIV_A::DIV14 + } + #[doc = "Checks if the value of the field is `DIV15`"] + #[inline(always)] + pub fn is_div15(&self) -> bool { + **self == DIV_A::DIV15 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == DIV_A::DIV16 + } +} +impl core::ops::Deref for DIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIV` writer - OSC48M Division Factor"] +pub struct DIV_W<'a> { + w: &'a mut W, +} +impl<'a> DIV_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DIV_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "48 MHz"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(DIV_A::DIV1) + } + #[doc = "24 MHz"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(DIV_A::DIV2) + } + #[doc = "16 MHz"] + #[inline(always)] + pub fn div3(self) -> &'a mut W { + self.variant(DIV_A::DIV3) + } + #[doc = "12 MHz"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(DIV_A::DIV4) + } + #[doc = "9.6 MHz"] + #[inline(always)] + pub fn div5(self) -> &'a mut W { + self.variant(DIV_A::DIV5) + } + #[doc = "8 MHz"] + #[inline(always)] + pub fn div6(self) -> &'a mut W { + self.variant(DIV_A::DIV6) + } + #[doc = "6.86 MHz"] + #[inline(always)] + pub fn div7(self) -> &'a mut W { + self.variant(DIV_A::DIV7) + } + #[doc = "6 MHz"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(DIV_A::DIV8) + } + #[doc = "5.33 MHz"] + #[inline(always)] + pub fn div9(self) -> &'a mut W { + self.variant(DIV_A::DIV9) + } + #[doc = "4.8 MHz"] + #[inline(always)] + pub fn div10(self) -> &'a mut W { + self.variant(DIV_A::DIV10) + } + #[doc = "4.36 MHz"] + #[inline(always)] + pub fn div11(self) -> &'a mut W { + self.variant(DIV_A::DIV11) + } + #[doc = "4 MHz"] + #[inline(always)] + pub fn div12(self) -> &'a mut W { + self.variant(DIV_A::DIV12) + } + #[doc = "3.69 MHz"] + #[inline(always)] + pub fn div13(self) -> &'a mut W { + self.variant(DIV_A::DIV13) + } + #[doc = "3.43 MHz"] + #[inline(always)] + pub fn div14(self) -> &'a mut W { + self.variant(DIV_A::DIV14) + } + #[doc = "3.2 MHz"] + #[inline(always)] + pub fn div15(self) -> &'a mut W { + self.variant(DIV_A::DIV15) + } + #[doc = "3 MHz"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(DIV_A::DIV16) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - OSC48M Division Factor"] + #[inline(always)] + pub fn div(&self) -> DIV_R { + DIV_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - OSC48M Division Factor"] + #[inline(always)] + pub fn div(&mut self) -> DIV_W { + DIV_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OSC48M Divider\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [osc48mdiv](index.html) module"] +pub struct OSC48MDIV_SPEC; +impl crate::RegisterSpec for OSC48MDIV_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [osc48mdiv::R](R) reader structure"] +impl crate::Readable for OSC48MDIV_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [osc48mdiv::W](W) writer structure"] +impl crate::Writable for OSC48MDIV_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OSC48MDIV to value 0x0b"] +impl crate::Resettable for OSC48MDIV_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0b + } +} diff --git a/pac/atsamc21g/src/oscctrl/osc48mstup.rs b/pac/atsamc21g/src/oscctrl/osc48mstup.rs new file mode 100644 index 000000000000..34da6bb7ef11 --- /dev/null +++ b/pac/atsamc21g/src/oscctrl/osc48mstup.rs @@ -0,0 +1,230 @@ +#[doc = "Register `OSC48MSTUP` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OSC48MSTUP` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Startup Time\n\nValue on reset: 7"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum STARTUP_A { + #[doc = "0: 166 ns"] + CYCLE8 = 0, + #[doc = "1: 333 ns"] + CYCLE16 = 1, + #[doc = "2: 667 ns"] + CYCLE32 = 2, + #[doc = "3: 1.333 us"] + CYCLE64 = 3, + #[doc = "4: 2.667 us"] + CYCLE128 = 4, + #[doc = "5: 5.333 us"] + CYCLE256 = 5, + #[doc = "6: 10.667 us"] + CYCLE512 = 6, + #[doc = "7: 21.333 us"] + CYCLE1024 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: STARTUP_A) -> Self { + variant as _ + } +} +#[doc = "Field `STARTUP` reader - Startup Time"] +pub struct STARTUP_R(crate::FieldReader); +impl STARTUP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + STARTUP_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STARTUP_A { + match self.bits { + 0 => STARTUP_A::CYCLE8, + 1 => STARTUP_A::CYCLE16, + 2 => STARTUP_A::CYCLE32, + 3 => STARTUP_A::CYCLE64, + 4 => STARTUP_A::CYCLE128, + 5 => STARTUP_A::CYCLE256, + 6 => STARTUP_A::CYCLE512, + 7 => STARTUP_A::CYCLE1024, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `CYCLE8`"] + #[inline(always)] + pub fn is_cycle8(&self) -> bool { + **self == STARTUP_A::CYCLE8 + } + #[doc = "Checks if the value of the field is `CYCLE16`"] + #[inline(always)] + pub fn is_cycle16(&self) -> bool { + **self == STARTUP_A::CYCLE16 + } + #[doc = "Checks if the value of the field is `CYCLE32`"] + #[inline(always)] + pub fn is_cycle32(&self) -> bool { + **self == STARTUP_A::CYCLE32 + } + #[doc = "Checks if the value of the field is `CYCLE64`"] + #[inline(always)] + pub fn is_cycle64(&self) -> bool { + **self == STARTUP_A::CYCLE64 + } + #[doc = "Checks if the value of the field is `CYCLE128`"] + #[inline(always)] + pub fn is_cycle128(&self) -> bool { + **self == STARTUP_A::CYCLE128 + } + #[doc = "Checks if the value of the field is `CYCLE256`"] + #[inline(always)] + pub fn is_cycle256(&self) -> bool { + **self == STARTUP_A::CYCLE256 + } + #[doc = "Checks if the value of the field is `CYCLE512`"] + #[inline(always)] + pub fn is_cycle512(&self) -> bool { + **self == STARTUP_A::CYCLE512 + } + #[doc = "Checks if the value of the field is `CYCLE1024`"] + #[inline(always)] + pub fn is_cycle1024(&self) -> bool { + **self == STARTUP_A::CYCLE1024 + } +} +impl core::ops::Deref for STARTUP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STARTUP` writer - Startup Time"] +pub struct STARTUP_W<'a> { + w: &'a mut W, +} +impl<'a> STARTUP_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: STARTUP_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "166 ns"] + #[inline(always)] + pub fn cycle8(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE8) + } + #[doc = "333 ns"] + #[inline(always)] + pub fn cycle16(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE16) + } + #[doc = "667 ns"] + #[inline(always)] + pub fn cycle32(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE32) + } + #[doc = "1.333 us"] + #[inline(always)] + pub fn cycle64(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE64) + } + #[doc = "2.667 us"] + #[inline(always)] + pub fn cycle128(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE128) + } + #[doc = "5.333 us"] + #[inline(always)] + pub fn cycle256(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE256) + } + #[doc = "10.667 us"] + #[inline(always)] + pub fn cycle512(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE512) + } + #[doc = "21.333 us"] + #[inline(always)] + pub fn cycle1024(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Startup Time"] + #[inline(always)] + pub fn startup(&self) -> STARTUP_R { + STARTUP_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Startup Time"] + #[inline(always)] + pub fn startup(&mut self) -> STARTUP_W { + STARTUP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OSC48M Startup Time\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [osc48mstup](index.html) module"] +pub struct OSC48MSTUP_SPEC; +impl crate::RegisterSpec for OSC48MSTUP_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [osc48mstup::R](R) reader structure"] +impl crate::Readable for OSC48MSTUP_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [osc48mstup::W](W) writer structure"] +impl crate::Writable for OSC48MSTUP_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OSC48MSTUP to value 0x07"] +impl crate::Resettable for OSC48MSTUP_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x07 + } +} diff --git a/pac/atsamc21g/src/oscctrl/osc48msyncbusy.rs b/pac/atsamc21g/src/oscctrl/osc48msyncbusy.rs new file mode 100644 index 000000000000..8d4410ae630a --- /dev/null +++ b/pac/atsamc21g/src/oscctrl/osc48msyncbusy.rs @@ -0,0 +1,53 @@ +#[doc = "Register `OSC48MSYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `OSC48MDIV` reader - OSC48MDIV Synchronization Status"] +pub struct OSC48MDIV_R(crate::FieldReader); +impl OSC48MDIV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC48MDIV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC48MDIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 2 - OSC48MDIV Synchronization Status"] + #[inline(always)] + pub fn osc48mdiv(&self) -> OSC48MDIV_R { + OSC48MDIV_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +#[doc = "OSC48M Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [osc48msyncbusy](index.html) module"] +pub struct OSC48MSYNCBUSY_SPEC; +impl crate::RegisterSpec for OSC48MSYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [osc48msyncbusy::R](R) reader structure"] +impl crate::Readable for OSC48MSYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets OSC48MSYNCBUSY to value 0"] +impl crate::Resettable for OSC48MSYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/oscctrl/status.rs b/pac/atsamc21g/src/oscctrl/status.rs new file mode 100644 index 000000000000..3025966192a3 --- /dev/null +++ b/pac/atsamc21g/src/oscctrl/status.rs @@ -0,0 +1,193 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `XOSCRDY` reader - XOSC Ready"] +pub struct XOSCRDY_R(crate::FieldReader); +impl XOSCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSCFAIL` reader - XOSC Clock Failure Detector"] +pub struct XOSCFAIL_R(crate::FieldReader); +impl XOSCFAIL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSCFAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCFAIL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSCCKSW` reader - XOSC Clock Switch"] +pub struct XOSCCKSW_R(crate::FieldReader); +impl XOSCCKSW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSCCKSW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCCKSW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC48MRDY` reader - OSC48M Ready"] +pub struct OSC48MRDY_R(crate::FieldReader); +impl OSC48MRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC48MRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC48MRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKR` reader - DPLL Lock Rise"] +pub struct DPLLLCKR_R(crate::FieldReader); +impl DPLLLCKR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKF` reader - DPLL Lock Fall"] +pub struct DPLLLCKF_R(crate::FieldReader); +impl DPLLLCKF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLTO` reader - DPLL Timeout"] +pub struct DPLLTO_R(crate::FieldReader); +impl DPLLTO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLTO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLDRTO` reader - DPLL Ratio Ready"] +pub struct DPLLLDRTO_R(crate::FieldReader); +impl DPLLLDRTO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLDRTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLDRTO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - XOSC Ready"] + #[inline(always)] + pub fn xoscrdy(&self) -> XOSCRDY_R { + XOSCRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - XOSC Clock Failure Detector"] + #[inline(always)] + pub fn xoscfail(&self) -> XOSCFAIL_R { + XOSCFAIL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - XOSC Clock Switch"] + #[inline(always)] + pub fn xosccksw(&self) -> XOSCCKSW_R { + XOSCCKSW_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 4 - OSC48M Ready"] + #[inline(always)] + pub fn osc48mrdy(&self) -> OSC48MRDY_R { + OSC48MRDY_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 8 - DPLL Lock Rise"] + #[inline(always)] + pub fn dplllckr(&self) -> DPLLLCKR_R { + DPLLLCKR_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - DPLL Lock Fall"] + #[inline(always)] + pub fn dplllckf(&self) -> DPLLLCKF_R { + DPLLLCKF_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - DPLL Timeout"] + #[inline(always)] + pub fn dpllto(&self) -> DPLLTO_R { + DPLLTO_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - DPLL Ratio Ready"] + #[inline(always)] + pub fn dpllldrto(&self) -> DPLLLDRTO_R { + DPLLLDRTO_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +#[doc = "Power and Clocks Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/oscctrl/xoscctrl.rs b/pac/atsamc21g/src/oscctrl/xoscctrl.rs new file mode 100644 index 000000000000..3a5319565c10 --- /dev/null +++ b/pac/atsamc21g/src/oscctrl/xoscctrl.rs @@ -0,0 +1,788 @@ +#[doc = "Register `XOSCCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `XOSCCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Oscillator Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Oscillator Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `XTALEN` reader - Crystal Oscillator Enable"] +pub struct XTALEN_R(crate::FieldReader); +impl XTALEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XTALEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XTALEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XTALEN` writer - Crystal Oscillator Enable"] +pub struct XTALEN_W<'a> { + w: &'a mut W, +} +impl<'a> XTALEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CFDEN` reader - Xosc Clock Failure Detector Enable"] +pub struct CFDEN_R(crate::FieldReader); +impl CFDEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFDEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFDEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFDEN` writer - Xosc Clock Failure Detector Enable"] +pub struct CFDEN_W<'a> { + w: &'a mut W, +} +impl<'a> CFDEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `SWBEN` reader - Xosc Clock Switch Enable"] +pub struct SWBEN_R(crate::FieldReader); +impl SWBEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWBEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWBEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWBEN` writer - Xosc Clock Switch Enable"] +pub struct SWBEN_W<'a> { + w: &'a mut W, +} +impl<'a> SWBEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - On Demand Control"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - On Demand Control"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Oscillator Gain\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum GAIN_A { + #[doc = "0: 2 MHz"] + GAIN2 = 0, + #[doc = "1: 4 MHz"] + GAIN4 = 1, + #[doc = "2: 8 MHz"] + GAIN8 = 2, + #[doc = "3: 16 MHz"] + GAIN16 = 3, + #[doc = "4: 30 MHz"] + GAIN30 = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: GAIN_A) -> Self { + variant as _ + } +} +#[doc = "Field `GAIN` reader - Oscillator Gain"] +pub struct GAIN_R(crate::FieldReader); +impl GAIN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + GAIN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(GAIN_A::GAIN2), + 1 => Some(GAIN_A::GAIN4), + 2 => Some(GAIN_A::GAIN8), + 3 => Some(GAIN_A::GAIN16), + 4 => Some(GAIN_A::GAIN30), + _ => None, + } + } + #[doc = "Checks if the value of the field is `GAIN2`"] + #[inline(always)] + pub fn is_gain2(&self) -> bool { + **self == GAIN_A::GAIN2 + } + #[doc = "Checks if the value of the field is `GAIN4`"] + #[inline(always)] + pub fn is_gain4(&self) -> bool { + **self == GAIN_A::GAIN4 + } + #[doc = "Checks if the value of the field is `GAIN8`"] + #[inline(always)] + pub fn is_gain8(&self) -> bool { + **self == GAIN_A::GAIN8 + } + #[doc = "Checks if the value of the field is `GAIN16`"] + #[inline(always)] + pub fn is_gain16(&self) -> bool { + **self == GAIN_A::GAIN16 + } + #[doc = "Checks if the value of the field is `GAIN30`"] + #[inline(always)] + pub fn is_gain30(&self) -> bool { + **self == GAIN_A::GAIN30 + } +} +impl core::ops::Deref for GAIN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GAIN` writer - Oscillator Gain"] +pub struct GAIN_W<'a> { + w: &'a mut W, +} +impl<'a> GAIN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: GAIN_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "2 MHz"] + #[inline(always)] + pub fn gain2(self) -> &'a mut W { + self.variant(GAIN_A::GAIN2) + } + #[doc = "4 MHz"] + #[inline(always)] + pub fn gain4(self) -> &'a mut W { + self.variant(GAIN_A::GAIN4) + } + #[doc = "8 MHz"] + #[inline(always)] + pub fn gain8(self) -> &'a mut W { + self.variant(GAIN_A::GAIN8) + } + #[doc = "16 MHz"] + #[inline(always)] + pub fn gain16(self) -> &'a mut W { + self.variant(GAIN_A::GAIN16) + } + #[doc = "30 MHz"] + #[inline(always)] + pub fn gain30(self) -> &'a mut W { + self.variant(GAIN_A::GAIN30) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u16 & 0x07) << 8); + self.w + } +} +#[doc = "Field `AMPGC` reader - Automatic Amplitude Gain Control"] +pub struct AMPGC_R(crate::FieldReader); +impl AMPGC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AMPGC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AMPGC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AMPGC` writer - Automatic Amplitude Gain Control"] +pub struct AMPGC_W<'a> { + w: &'a mut W, +} +impl<'a> AMPGC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u16 & 0x01) << 11); + self.w + } +} +#[doc = "Start-Up Time\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum STARTUP_A { + #[doc = "0: 31 us"] + CYCLE1 = 0, + #[doc = "1: 61 us"] + CYCLE2 = 1, + #[doc = "2: 122 us"] + CYCLE4 = 2, + #[doc = "3: 244 us"] + CYCLE8 = 3, + #[doc = "4: 488 us"] + CYCLE16 = 4, + #[doc = "5: 977 us"] + CYCLE32 = 5, + #[doc = "6: 1953 us"] + CYCLE64 = 6, + #[doc = "7: 3906 us"] + CYCLE128 = 7, + #[doc = "8: 7813 us"] + CYCLE256 = 8, + #[doc = "9: 15625 us"] + CYCLE512 = 9, + #[doc = "10: 31250 us"] + CYCLE1024 = 10, + #[doc = "11: 62500 us"] + CYCLE2048 = 11, + #[doc = "12: 125000 us"] + CYCLE4096 = 12, + #[doc = "13: 250000 us"] + CYCLE8192 = 13, + #[doc = "14: 500000 us"] + CYCLE16384 = 14, + #[doc = "15: 1000000 us"] + CYCLE32768 = 15, +} +impl From for u8 { + #[inline(always)] + fn from(variant: STARTUP_A) -> Self { + variant as _ + } +} +#[doc = "Field `STARTUP` reader - Start-Up Time"] +pub struct STARTUP_R(crate::FieldReader); +impl STARTUP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + STARTUP_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STARTUP_A { + match self.bits { + 0 => STARTUP_A::CYCLE1, + 1 => STARTUP_A::CYCLE2, + 2 => STARTUP_A::CYCLE4, + 3 => STARTUP_A::CYCLE8, + 4 => STARTUP_A::CYCLE16, + 5 => STARTUP_A::CYCLE32, + 6 => STARTUP_A::CYCLE64, + 7 => STARTUP_A::CYCLE128, + 8 => STARTUP_A::CYCLE256, + 9 => STARTUP_A::CYCLE512, + 10 => STARTUP_A::CYCLE1024, + 11 => STARTUP_A::CYCLE2048, + 12 => STARTUP_A::CYCLE4096, + 13 => STARTUP_A::CYCLE8192, + 14 => STARTUP_A::CYCLE16384, + 15 => STARTUP_A::CYCLE32768, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `CYCLE1`"] + #[inline(always)] + pub fn is_cycle1(&self) -> bool { + **self == STARTUP_A::CYCLE1 + } + #[doc = "Checks if the value of the field is `CYCLE2`"] + #[inline(always)] + pub fn is_cycle2(&self) -> bool { + **self == STARTUP_A::CYCLE2 + } + #[doc = "Checks if the value of the field is `CYCLE4`"] + #[inline(always)] + pub fn is_cycle4(&self) -> bool { + **self == STARTUP_A::CYCLE4 + } + #[doc = "Checks if the value of the field is `CYCLE8`"] + #[inline(always)] + pub fn is_cycle8(&self) -> bool { + **self == STARTUP_A::CYCLE8 + } + #[doc = "Checks if the value of the field is `CYCLE16`"] + #[inline(always)] + pub fn is_cycle16(&self) -> bool { + **self == STARTUP_A::CYCLE16 + } + #[doc = "Checks if the value of the field is `CYCLE32`"] + #[inline(always)] + pub fn is_cycle32(&self) -> bool { + **self == STARTUP_A::CYCLE32 + } + #[doc = "Checks if the value of the field is `CYCLE64`"] + #[inline(always)] + pub fn is_cycle64(&self) -> bool { + **self == STARTUP_A::CYCLE64 + } + #[doc = "Checks if the value of the field is `CYCLE128`"] + #[inline(always)] + pub fn is_cycle128(&self) -> bool { + **self == STARTUP_A::CYCLE128 + } + #[doc = "Checks if the value of the field is `CYCLE256`"] + #[inline(always)] + pub fn is_cycle256(&self) -> bool { + **self == STARTUP_A::CYCLE256 + } + #[doc = "Checks if the value of the field is `CYCLE512`"] + #[inline(always)] + pub fn is_cycle512(&self) -> bool { + **self == STARTUP_A::CYCLE512 + } + #[doc = "Checks if the value of the field is `CYCLE1024`"] + #[inline(always)] + pub fn is_cycle1024(&self) -> bool { + **self == STARTUP_A::CYCLE1024 + } + #[doc = "Checks if the value of the field is `CYCLE2048`"] + #[inline(always)] + pub fn is_cycle2048(&self) -> bool { + **self == STARTUP_A::CYCLE2048 + } + #[doc = "Checks if the value of the field is `CYCLE4096`"] + #[inline(always)] + pub fn is_cycle4096(&self) -> bool { + **self == STARTUP_A::CYCLE4096 + } + #[doc = "Checks if the value of the field is `CYCLE8192`"] + #[inline(always)] + pub fn is_cycle8192(&self) -> bool { + **self == STARTUP_A::CYCLE8192 + } + #[doc = "Checks if the value of the field is `CYCLE16384`"] + #[inline(always)] + pub fn is_cycle16384(&self) -> bool { + **self == STARTUP_A::CYCLE16384 + } + #[doc = "Checks if the value of the field is `CYCLE32768`"] + #[inline(always)] + pub fn is_cycle32768(&self) -> bool { + **self == STARTUP_A::CYCLE32768 + } +} +impl core::ops::Deref for STARTUP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STARTUP` writer - Start-Up Time"] +pub struct STARTUP_W<'a> { + w: &'a mut W, +} +impl<'a> STARTUP_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: STARTUP_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "31 us"] + #[inline(always)] + pub fn cycle1(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE1) + } + #[doc = "61 us"] + #[inline(always)] + pub fn cycle2(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE2) + } + #[doc = "122 us"] + #[inline(always)] + pub fn cycle4(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE4) + } + #[doc = "244 us"] + #[inline(always)] + pub fn cycle8(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE8) + } + #[doc = "488 us"] + #[inline(always)] + pub fn cycle16(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE16) + } + #[doc = "977 us"] + #[inline(always)] + pub fn cycle32(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE32) + } + #[doc = "1953 us"] + #[inline(always)] + pub fn cycle64(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE64) + } + #[doc = "3906 us"] + #[inline(always)] + pub fn cycle128(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE128) + } + #[doc = "7813 us"] + #[inline(always)] + pub fn cycle256(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE256) + } + #[doc = "15625 us"] + #[inline(always)] + pub fn cycle512(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE512) + } + #[doc = "31250 us"] + #[inline(always)] + pub fn cycle1024(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE1024) + } + #[doc = "62500 us"] + #[inline(always)] + pub fn cycle2048(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE2048) + } + #[doc = "125000 us"] + #[inline(always)] + pub fn cycle4096(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE4096) + } + #[doc = "250000 us"] + #[inline(always)] + pub fn cycle8192(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE8192) + } + #[doc = "500000 us"] + #[inline(always)] + pub fn cycle16384(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE16384) + } + #[doc = "1000000 us"] + #[inline(always)] + pub fn cycle32768(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE32768) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 12)) | ((value as u16 & 0x0f) << 12); + self.w + } +} +impl R { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Crystal Oscillator Enable"] + #[inline(always)] + pub fn xtalen(&self) -> XTALEN_R { + XTALEN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Xosc Clock Failure Detector Enable"] + #[inline(always)] + pub fn cfden(&self) -> CFDEN_R { + CFDEN_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Xosc Clock Switch Enable"] + #[inline(always)] + pub fn swben(&self) -> SWBEN_R { + SWBEN_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Oscillator Gain"] + #[inline(always)] + pub fn gain(&self) -> GAIN_R { + GAIN_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 11 - Automatic Amplitude Gain Control"] + #[inline(always)] + pub fn ampgc(&self) -> AMPGC_R { + AMPGC_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bits 12:15 - Start-Up Time"] + #[inline(always)] + pub fn startup(&self) -> STARTUP_R { + STARTUP_R::new(((self.bits >> 12) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - Crystal Oscillator Enable"] + #[inline(always)] + pub fn xtalen(&mut self) -> XTALEN_W { + XTALEN_W { w: self } + } + #[doc = "Bit 3 - Xosc Clock Failure Detector Enable"] + #[inline(always)] + pub fn cfden(&mut self) -> CFDEN_W { + CFDEN_W { w: self } + } + #[doc = "Bit 4 - Xosc Clock Switch Enable"] + #[inline(always)] + pub fn swben(&mut self) -> SWBEN_W { + SWBEN_W { w: self } + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Bits 8:10 - Oscillator Gain"] + #[inline(always)] + pub fn gain(&mut self) -> GAIN_W { + GAIN_W { w: self } + } + #[doc = "Bit 11 - Automatic Amplitude Gain Control"] + #[inline(always)] + pub fn ampgc(&mut self) -> AMPGC_W { + AMPGC_W { w: self } + } + #[doc = "Bits 12:15 - Start-Up Time"] + #[inline(always)] + pub fn startup(&mut self) -> STARTUP_W { + STARTUP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "External Multipurpose Crystal Oscillator (XOSC) Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [xoscctrl](index.html) module"] +pub struct XOSCCTRL_SPEC; +impl crate::RegisterSpec for XOSCCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [xoscctrl::R](R) reader structure"] +impl crate::Readable for XOSCCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [xoscctrl::W](W) writer structure"] +impl crate::Writable for XOSCCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets XOSCCTRL to value 0x80"] +impl crate::Resettable for XOSCCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x80 + } +} diff --git a/pac/atsamc21g/src/pac.rs b/pac/atsamc21g/src/pac.rs new file mode 100644 index 000000000000..3e365e081945 --- /dev/null +++ b/pac/atsamc21g/src/pac.rs @@ -0,0 +1,73 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Write control"] + pub wrctrl: crate::Reg, + #[doc = "0x04 - Event control"] + pub evctrl: crate::Reg, + _reserved2: [u8; 0x03], + #[doc = "0x08 - Interrupt enable clear"] + pub intenclr: crate::Reg, + #[doc = "0x09 - Interrupt enable set"] + pub intenset: crate::Reg, + _reserved4: [u8; 0x06], + #[doc = "0x10 - Bridge interrupt flag status"] + pub intflagahb: crate::Reg, + #[doc = "0x14 - Peripheral interrupt flag status - Bridge A"] + pub intflaga: crate::Reg, + #[doc = "0x18 - Peripheral interrupt flag status - Bridge B"] + pub intflagb: crate::Reg, + #[doc = "0x1c - Peripheral interrupt flag status - Bridge C"] + pub intflagc: crate::Reg, + _reserved8: [u8; 0x14], + #[doc = "0x34 - Peripheral write protection status - Bridge A"] + pub statusa: crate::Reg, + #[doc = "0x38 - Peripheral write protection status - Bridge B"] + pub statusb: crate::Reg, + #[doc = "0x3c - Peripheral write protection status - Bridge C"] + pub statusc: crate::Reg, +} +#[doc = "WRCTRL register accessor: an alias for `Reg`"] +pub type WRCTRL = crate::Reg; +#[doc = "Write control"] +pub mod wrctrl; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt enable clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt enable set"] +pub mod intenset; +#[doc = "INTFLAGAHB register accessor: an alias for `Reg`"] +pub type INTFLAGAHB = crate::Reg; +#[doc = "Bridge interrupt flag status"] +pub mod intflagahb; +#[doc = "INTFLAGA register accessor: an alias for `Reg`"] +pub type INTFLAGA = crate::Reg; +#[doc = "Peripheral interrupt flag status - Bridge A"] +pub mod intflaga; +#[doc = "INTFLAGB register accessor: an alias for `Reg`"] +pub type INTFLAGB = crate::Reg; +#[doc = "Peripheral interrupt flag status - Bridge B"] +pub mod intflagb; +#[doc = "INTFLAGC register accessor: an alias for `Reg`"] +pub type INTFLAGC = crate::Reg; +#[doc = "Peripheral interrupt flag status - Bridge C"] +pub mod intflagc; +#[doc = "STATUSA register accessor: an alias for `Reg`"] +pub type STATUSA = crate::Reg; +#[doc = "Peripheral write protection status - Bridge A"] +pub mod statusa; +#[doc = "STATUSB register accessor: an alias for `Reg`"] +pub type STATUSB = crate::Reg; +#[doc = "Peripheral write protection status - Bridge B"] +pub mod statusb; +#[doc = "STATUSC register accessor: an alias for `Reg`"] +pub type STATUSC = crate::Reg; +#[doc = "Peripheral write protection status - Bridge C"] +pub mod statusc; diff --git a/pac/atsamc21g/src/pac/evctrl.rs b/pac/atsamc21g/src/pac/evctrl.rs new file mode 100644 index 000000000000..630581b98c85 --- /dev/null +++ b/pac/atsamc21g/src/pac/evctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ERREO` reader - Peripheral acess error event output"] +pub struct ERREO_R(crate::FieldReader); +impl ERREO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERREO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERREO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERREO` writer - Peripheral acess error event output"] +pub struct ERREO_W<'a> { + w: &'a mut W, +} +impl<'a> ERREO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Peripheral acess error event output"] + #[inline(always)] + pub fn erreo(&self) -> ERREO_R { + ERREO_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Peripheral acess error event output"] + #[inline(always)] + pub fn erreo(&mut self) -> ERREO_W { + ERREO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/pac/intenclr.rs b/pac/atsamc21g/src/pac/intenclr.rs new file mode 100644 index 000000000000..609fe0fcf628 --- /dev/null +++ b/pac/atsamc21g/src/pac/intenclr.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ERR` reader - Peripheral access error interrupt disable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - Peripheral access error interrupt disable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Peripheral access error interrupt disable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Peripheral access error interrupt disable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt enable clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/pac/intenset.rs b/pac/atsamc21g/src/pac/intenset.rs new file mode 100644 index 000000000000..390545b588de --- /dev/null +++ b/pac/atsamc21g/src/pac/intenset.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ERR` reader - Peripheral access error interrupt enable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - Peripheral access error interrupt enable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Peripheral access error interrupt enable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Peripheral access error interrupt enable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt enable set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/pac/intflaga.rs b/pac/atsamc21g/src/pac/intflaga.rs new file mode 100644 index 000000000000..a1603451ad72 --- /dev/null +++ b/pac/atsamc21g/src/pac/intflaga.rs @@ -0,0 +1,677 @@ +#[doc = "Register `INTFLAGA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAGA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PAC_` reader - PAC"] +pub struct PAC__R(crate::FieldReader); +impl PAC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PAC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PAC_` writer - PAC"] +pub struct PAC__W<'a> { + w: &'a mut W, +} +impl<'a> PAC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `PM_` reader - PM"] +pub struct PM__R(crate::FieldReader); +impl PM__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PM__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PM__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PM_` writer - PM"] +pub struct PM__W<'a> { + w: &'a mut W, +} +impl<'a> PM__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MCLK_` reader - MCLK"] +pub struct MCLK__R(crate::FieldReader); +impl MCLK__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCLK__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCLK__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCLK_` writer - MCLK"] +pub struct MCLK__W<'a> { + w: &'a mut W, +} +impl<'a> MCLK__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RSTC_` reader - RSTC"] +pub struct RSTC__R(crate::FieldReader); +impl RSTC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RSTC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RSTC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RSTC_` writer - RSTC"] +pub struct RSTC__W<'a> { + w: &'a mut W, +} +impl<'a> RSTC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `OSCCTRL_` reader - OSCCTRL"] +pub struct OSCCTRL__R(crate::FieldReader); +impl OSCCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSCCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSCCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSCCTRL_` writer - OSCCTRL"] +pub struct OSCCTRL__W<'a> { + w: &'a mut W, +} +impl<'a> OSCCTRL__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `OSC32KCTRL_` reader - OSC32KCTRL"] +pub struct OSC32KCTRL__R(crate::FieldReader); +impl OSC32KCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC32KCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC32KCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC32KCTRL_` writer - OSC32KCTRL"] +pub struct OSC32KCTRL__W<'a> { + w: &'a mut W, +} +impl<'a> OSC32KCTRL__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `SUPC_` reader - SUPC"] +pub struct SUPC__R(crate::FieldReader); +impl SUPC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SUPC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SUPC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SUPC_` writer - SUPC"] +pub struct SUPC__W<'a> { + w: &'a mut W, +} +impl<'a> SUPC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `GCLK_` reader - GCLK"] +pub struct GCLK__R(crate::FieldReader); +impl GCLK__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GCLK__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GCLK__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GCLK_` writer - GCLK"] +pub struct GCLK__W<'a> { + w: &'a mut W, +} +impl<'a> GCLK__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `WDT_` reader - WDT"] +pub struct WDT__R(crate::FieldReader); +impl WDT__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WDT__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WDT__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WDT_` writer - WDT"] +pub struct WDT__W<'a> { + w: &'a mut W, +} +impl<'a> WDT__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `RTC_` reader - RTC"] +pub struct RTC__R(crate::FieldReader); +impl RTC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RTC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RTC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RTC_` writer - RTC"] +pub struct RTC__W<'a> { + w: &'a mut W, +} +impl<'a> RTC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `EIC_` reader - EIC"] +pub struct EIC__R(crate::FieldReader); +impl EIC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EIC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EIC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EIC_` writer - EIC"] +pub struct EIC__W<'a> { + w: &'a mut W, +} +impl<'a> EIC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `FREQM_` reader - FREQM"] +pub struct FREQM__R(crate::FieldReader); +impl FREQM__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FREQM__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FREQM__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FREQM_` writer - FREQM"] +pub struct FREQM__W<'a> { + w: &'a mut W, +} +impl<'a> FREQM__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `TSENS_` reader - TSENS"] +pub struct TSENS__R(crate::FieldReader); +impl TSENS__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSENS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSENS__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSENS_` writer - TSENS"] +pub struct TSENS__W<'a> { + w: &'a mut W, +} +impl<'a> TSENS__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +impl R { + #[doc = "Bit 0 - PAC"] + #[inline(always)] + pub fn pac_(&self) -> PAC__R { + PAC__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - PM"] + #[inline(always)] + pub fn pm_(&self) -> PM__R { + PM__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - MCLK"] + #[inline(always)] + pub fn mclk_(&self) -> MCLK__R { + MCLK__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - RSTC"] + #[inline(always)] + pub fn rstc_(&self) -> RSTC__R { + RSTC__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - OSCCTRL"] + #[inline(always)] + pub fn oscctrl_(&self) -> OSCCTRL__R { + OSCCTRL__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - OSC32KCTRL"] + #[inline(always)] + pub fn osc32kctrl_(&self) -> OSC32KCTRL__R { + OSC32KCTRL__R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - SUPC"] + #[inline(always)] + pub fn supc_(&self) -> SUPC__R { + SUPC__R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - GCLK"] + #[inline(always)] + pub fn gclk_(&self) -> GCLK__R { + GCLK__R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - WDT"] + #[inline(always)] + pub fn wdt_(&self) -> WDT__R { + WDT__R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - RTC"] + #[inline(always)] + pub fn rtc_(&self) -> RTC__R { + RTC__R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - EIC"] + #[inline(always)] + pub fn eic_(&self) -> EIC__R { + EIC__R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - FREQM"] + #[inline(always)] + pub fn freqm_(&self) -> FREQM__R { + FREQM__R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - TSENS"] + #[inline(always)] + pub fn tsens_(&self) -> TSENS__R { + TSENS__R::new(((self.bits >> 12) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - PAC"] + #[inline(always)] + pub fn pac_(&mut self) -> PAC__W { + PAC__W { w: self } + } + #[doc = "Bit 1 - PM"] + #[inline(always)] + pub fn pm_(&mut self) -> PM__W { + PM__W { w: self } + } + #[doc = "Bit 2 - MCLK"] + #[inline(always)] + pub fn mclk_(&mut self) -> MCLK__W { + MCLK__W { w: self } + } + #[doc = "Bit 3 - RSTC"] + #[inline(always)] + pub fn rstc_(&mut self) -> RSTC__W { + RSTC__W { w: self } + } + #[doc = "Bit 4 - OSCCTRL"] + #[inline(always)] + pub fn oscctrl_(&mut self) -> OSCCTRL__W { + OSCCTRL__W { w: self } + } + #[doc = "Bit 5 - OSC32KCTRL"] + #[inline(always)] + pub fn osc32kctrl_(&mut self) -> OSC32KCTRL__W { + OSC32KCTRL__W { w: self } + } + #[doc = "Bit 6 - SUPC"] + #[inline(always)] + pub fn supc_(&mut self) -> SUPC__W { + SUPC__W { w: self } + } + #[doc = "Bit 7 - GCLK"] + #[inline(always)] + pub fn gclk_(&mut self) -> GCLK__W { + GCLK__W { w: self } + } + #[doc = "Bit 8 - WDT"] + #[inline(always)] + pub fn wdt_(&mut self) -> WDT__W { + WDT__W { w: self } + } + #[doc = "Bit 9 - RTC"] + #[inline(always)] + pub fn rtc_(&mut self) -> RTC__W { + RTC__W { w: self } + } + #[doc = "Bit 10 - EIC"] + #[inline(always)] + pub fn eic_(&mut self) -> EIC__W { + EIC__W { w: self } + } + #[doc = "Bit 11 - FREQM"] + #[inline(always)] + pub fn freqm_(&mut self) -> FREQM__W { + FREQM__W { w: self } + } + #[doc = "Bit 12 - TSENS"] + #[inline(always)] + pub fn tsens_(&mut self) -> TSENS__W { + TSENS__W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Peripheral interrupt flag status - Bridge A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflaga](index.html) module"] +pub struct INTFLAGA_SPEC; +impl crate::RegisterSpec for INTFLAGA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflaga::R](R) reader structure"] +impl crate::Readable for INTFLAGA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflaga::W](W) writer structure"] +impl crate::Writable for INTFLAGA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAGA to value 0"] +impl crate::Resettable for INTFLAGA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/pac/intflagahb.rs b/pac/atsamc21g/src/pac/intflagahb.rs new file mode 100644 index 000000000000..4b7f7377e25e --- /dev/null +++ b/pac/atsamc21g/src/pac/intflagahb.rs @@ -0,0 +1,442 @@ +#[doc = "Register `INTFLAGAHB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAGAHB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FLASH_` reader - FLASH"] +pub struct FLASH__R(crate::FieldReader); +impl FLASH__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FLASH__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FLASH__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLASH_` writer - FLASH"] +pub struct FLASH__W<'a> { + w: &'a mut W, +} +impl<'a> FLASH__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `HSRAMCM0P_` reader - HSRAMCM0P"] +pub struct HSRAMCM0P__R(crate::FieldReader); +impl HSRAMCM0P__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HSRAMCM0P__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HSRAMCM0P__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HSRAMCM0P_` writer - HSRAMCM0P"] +pub struct HSRAMCM0P__W<'a> { + w: &'a mut W, +} +impl<'a> HSRAMCM0P__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `HSRAMDSU_` reader - HSRAMDSU"] +pub struct HSRAMDSU__R(crate::FieldReader); +impl HSRAMDSU__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HSRAMDSU__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HSRAMDSU__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HSRAMDSU_` writer - HSRAMDSU"] +pub struct HSRAMDSU__W<'a> { + w: &'a mut W, +} +impl<'a> HSRAMDSU__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `HPB1_` reader - HPB1"] +pub struct HPB1__R(crate::FieldReader); +impl HPB1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HPB1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HPB1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HPB1_` writer - HPB1"] +pub struct HPB1__W<'a> { + w: &'a mut W, +} +impl<'a> HPB1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `HPB0_` reader - HPB0"] +pub struct HPB0__R(crate::FieldReader); +impl HPB0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HPB0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HPB0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HPB0_` writer - HPB0"] +pub struct HPB0__W<'a> { + w: &'a mut W, +} +impl<'a> HPB0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `HPB2_` reader - HPB2"] +pub struct HPB2__R(crate::FieldReader); +impl HPB2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HPB2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HPB2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HPB2_` writer - HPB2"] +pub struct HPB2__W<'a> { + w: &'a mut W, +} +impl<'a> HPB2__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `LPRAMDMAC_` reader - LPRAMDMAC"] +pub struct LPRAMDMAC__R(crate::FieldReader); +impl LPRAMDMAC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LPRAMDMAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LPRAMDMAC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LPRAMDMAC_` writer - LPRAMDMAC"] +pub struct LPRAMDMAC__W<'a> { + w: &'a mut W, +} +impl<'a> LPRAMDMAC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `DIVAS_` reader - DIVAS"] +pub struct DIVAS__R(crate::FieldReader); +impl DIVAS__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIVAS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIVAS__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIVAS_` writer - DIVAS"] +pub struct DIVAS__W<'a> { + w: &'a mut W, +} +impl<'a> DIVAS__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - FLASH"] + #[inline(always)] + pub fn flash_(&self) -> FLASH__R { + FLASH__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - HSRAMCM0P"] + #[inline(always)] + pub fn hsramcm0p_(&self) -> HSRAMCM0P__R { + HSRAMCM0P__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - HSRAMDSU"] + #[inline(always)] + pub fn hsramdsu_(&self) -> HSRAMDSU__R { + HSRAMDSU__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - HPB1"] + #[inline(always)] + pub fn hpb1_(&self) -> HPB1__R { + HPB1__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - HPB0"] + #[inline(always)] + pub fn hpb0_(&self) -> HPB0__R { + HPB0__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - HPB2"] + #[inline(always)] + pub fn hpb2_(&self) -> HPB2__R { + HPB2__R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - LPRAMDMAC"] + #[inline(always)] + pub fn lpramdmac_(&self) -> LPRAMDMAC__R { + LPRAMDMAC__R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - DIVAS"] + #[inline(always)] + pub fn divas_(&self) -> DIVAS__R { + DIVAS__R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - FLASH"] + #[inline(always)] + pub fn flash_(&mut self) -> FLASH__W { + FLASH__W { w: self } + } + #[doc = "Bit 1 - HSRAMCM0P"] + #[inline(always)] + pub fn hsramcm0p_(&mut self) -> HSRAMCM0P__W { + HSRAMCM0P__W { w: self } + } + #[doc = "Bit 2 - HSRAMDSU"] + #[inline(always)] + pub fn hsramdsu_(&mut self) -> HSRAMDSU__W { + HSRAMDSU__W { w: self } + } + #[doc = "Bit 3 - HPB1"] + #[inline(always)] + pub fn hpb1_(&mut self) -> HPB1__W { + HPB1__W { w: self } + } + #[doc = "Bit 4 - HPB0"] + #[inline(always)] + pub fn hpb0_(&mut self) -> HPB0__W { + HPB0__W { w: self } + } + #[doc = "Bit 5 - HPB2"] + #[inline(always)] + pub fn hpb2_(&mut self) -> HPB2__W { + HPB2__W { w: self } + } + #[doc = "Bit 6 - LPRAMDMAC"] + #[inline(always)] + pub fn lpramdmac_(&mut self) -> LPRAMDMAC__W { + LPRAMDMAC__W { w: self } + } + #[doc = "Bit 7 - DIVAS"] + #[inline(always)] + pub fn divas_(&mut self) -> DIVAS__W { + DIVAS__W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Bridge interrupt flag status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflagahb](index.html) module"] +pub struct INTFLAGAHB_SPEC; +impl crate::RegisterSpec for INTFLAGAHB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflagahb::R](R) reader structure"] +impl crate::Readable for INTFLAGAHB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflagahb::W](W) writer structure"] +impl crate::Writable for INTFLAGAHB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAGAHB to value 0"] +impl crate::Resettable for INTFLAGAHB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/pac/intflagb.rs b/pac/atsamc21g/src/pac/intflagb.rs new file mode 100644 index 000000000000..8359f7e11f30 --- /dev/null +++ b/pac/atsamc21g/src/pac/intflagb.rs @@ -0,0 +1,348 @@ +#[doc = "Register `INTFLAGB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAGB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PORT_` reader - PORT"] +pub struct PORT__R(crate::FieldReader); +impl PORT__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PORT__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PORT__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PORT_` writer - PORT"] +pub struct PORT__W<'a> { + w: &'a mut W, +} +impl<'a> PORT__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `DSU_` reader - DSU"] +pub struct DSU__R(crate::FieldReader); +impl DSU__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DSU__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DSU__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DSU_` writer - DSU"] +pub struct DSU__W<'a> { + w: &'a mut W, +} +impl<'a> DSU__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `NVMCTRL_` reader - NVMCTRL"] +pub struct NVMCTRL__R(crate::FieldReader); +impl NVMCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NVMCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NVMCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NVMCTRL_` writer - NVMCTRL"] +pub struct NVMCTRL__W<'a> { + w: &'a mut W, +} +impl<'a> NVMCTRL__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `DMAC_` reader - DMAC"] +pub struct DMAC__R(crate::FieldReader); +impl DMAC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DMAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DMAC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DMAC_` writer - DMAC"] +pub struct DMAC__W<'a> { + w: &'a mut W, +} +impl<'a> DMAC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `MTB_` reader - MTB"] +pub struct MTB__R(crate::FieldReader); +impl MTB__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MTB__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MTB__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MTB_` writer - MTB"] +pub struct MTB__W<'a> { + w: &'a mut W, +} +impl<'a> MTB__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `HMATRIXHS_` reader - HMATRIXHS"] +pub struct HMATRIXHS__R(crate::FieldReader); +impl HMATRIXHS__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HMATRIXHS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HMATRIXHS__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HMATRIXHS_` writer - HMATRIXHS"] +pub struct HMATRIXHS__W<'a> { + w: &'a mut W, +} +impl<'a> HMATRIXHS__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - PORT"] + #[inline(always)] + pub fn port_(&self) -> PORT__R { + PORT__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - DSU"] + #[inline(always)] + pub fn dsu_(&self) -> DSU__R { + DSU__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - NVMCTRL"] + #[inline(always)] + pub fn nvmctrl_(&self) -> NVMCTRL__R { + NVMCTRL__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - DMAC"] + #[inline(always)] + pub fn dmac_(&self) -> DMAC__R { + DMAC__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - MTB"] + #[inline(always)] + pub fn mtb_(&self) -> MTB__R { + MTB__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - HMATRIXHS"] + #[inline(always)] + pub fn hmatrixhs_(&self) -> HMATRIXHS__R { + HMATRIXHS__R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - PORT"] + #[inline(always)] + pub fn port_(&mut self) -> PORT__W { + PORT__W { w: self } + } + #[doc = "Bit 1 - DSU"] + #[inline(always)] + pub fn dsu_(&mut self) -> DSU__W { + DSU__W { w: self } + } + #[doc = "Bit 2 - NVMCTRL"] + #[inline(always)] + pub fn nvmctrl_(&mut self) -> NVMCTRL__W { + NVMCTRL__W { w: self } + } + #[doc = "Bit 3 - DMAC"] + #[inline(always)] + pub fn dmac_(&mut self) -> DMAC__W { + DMAC__W { w: self } + } + #[doc = "Bit 4 - MTB"] + #[inline(always)] + pub fn mtb_(&mut self) -> MTB__W { + MTB__W { w: self } + } + #[doc = "Bit 5 - HMATRIXHS"] + #[inline(always)] + pub fn hmatrixhs_(&mut self) -> HMATRIXHS__W { + HMATRIXHS__W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Peripheral interrupt flag status - Bridge B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflagb](index.html) module"] +pub struct INTFLAGB_SPEC; +impl crate::RegisterSpec for INTFLAGB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflagb::R](R) reader structure"] +impl crate::Readable for INTFLAGB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflagb::W](W) writer structure"] +impl crate::Writable for INTFLAGB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAGB to value 0"] +impl crate::Resettable for INTFLAGB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/pac/intflagc.rs b/pac/atsamc21g/src/pac/intflagc.rs new file mode 100644 index 000000000000..80ee48da5eeb --- /dev/null +++ b/pac/atsamc21g/src/pac/intflagc.rs @@ -0,0 +1,1194 @@ +#[doc = "Register `INTFLAGC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAGC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVSYS_` reader - EVSYS"] +pub struct EVSYS__R(crate::FieldReader); +impl EVSYS__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVSYS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVSYS__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVSYS_` writer - EVSYS"] +pub struct EVSYS__W<'a> { + w: &'a mut W, +} +impl<'a> EVSYS__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `SERCOM0_` reader - SERCOM0"] +pub struct SERCOM0__R(crate::FieldReader); +impl SERCOM0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM0_` writer - SERCOM0"] +pub struct SERCOM0__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SERCOM1_` reader - SERCOM1"] +pub struct SERCOM1__R(crate::FieldReader); +impl SERCOM1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM1_` writer - SERCOM1"] +pub struct SERCOM1__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SERCOM2_` reader - SERCOM2"] +pub struct SERCOM2__R(crate::FieldReader); +impl SERCOM2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM2_` writer - SERCOM2"] +pub struct SERCOM2__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM2__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `SERCOM3_` reader - SERCOM3"] +pub struct SERCOM3__R(crate::FieldReader); +impl SERCOM3__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM3__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM3__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM3_` writer - SERCOM3"] +pub struct SERCOM3__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM3__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `SERCOM4_` reader - SERCOM4"] +pub struct SERCOM4__R(crate::FieldReader); +impl SERCOM4__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM4__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM4__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM4_` writer - SERCOM4"] +pub struct SERCOM4__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM4__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `SERCOM5_` reader - SERCOM5"] +pub struct SERCOM5__R(crate::FieldReader); +impl SERCOM5__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM5__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM5__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM5_` writer - SERCOM5"] +pub struct SERCOM5__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM5__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `CAN0_` reader - CAN0"] +pub struct CAN0__R(crate::FieldReader); +impl CAN0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CAN0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CAN0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAN0_` writer - CAN0"] +pub struct CAN0__W<'a> { + w: &'a mut W, +} +impl<'a> CAN0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CAN1_` reader - CAN1"] +pub struct CAN1__R(crate::FieldReader); +impl CAN1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CAN1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CAN1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAN1_` writer - CAN1"] +pub struct CAN1__W<'a> { + w: &'a mut W, +} +impl<'a> CAN1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `TCC0_` reader - TCC0"] +pub struct TCC0__R(crate::FieldReader); +impl TCC0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCC0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCC0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCC0_` writer - TCC0"] +pub struct TCC0__W<'a> { + w: &'a mut W, +} +impl<'a> TCC0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `TCC1_` reader - TCC1"] +pub struct TCC1__R(crate::FieldReader); +impl TCC1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCC1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCC1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCC1_` writer - TCC1"] +pub struct TCC1__W<'a> { + w: &'a mut W, +} +impl<'a> TCC1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `TCC2_` reader - TCC2"] +pub struct TCC2__R(crate::FieldReader); +impl TCC2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCC2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCC2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCC2_` writer - TCC2"] +pub struct TCC2__W<'a> { + w: &'a mut W, +} +impl<'a> TCC2__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `TC0_` reader - TC0"] +pub struct TC0__R(crate::FieldReader); +impl TC0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC0_` writer - TC0"] +pub struct TC0__W<'a> { + w: &'a mut W, +} +impl<'a> TC0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `TC1_` reader - TC1"] +pub struct TC1__R(crate::FieldReader); +impl TC1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC1_` writer - TC1"] +pub struct TC1__W<'a> { + w: &'a mut W, +} +impl<'a> TC1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `TC2_` reader - TC2"] +pub struct TC2__R(crate::FieldReader); +impl TC2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC2_` writer - TC2"] +pub struct TC2__W<'a> { + w: &'a mut W, +} +impl<'a> TC2__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `TC3_` reader - TC3"] +pub struct TC3__R(crate::FieldReader); +impl TC3__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC3__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC3__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC3_` writer - TC3"] +pub struct TC3__W<'a> { + w: &'a mut W, +} +impl<'a> TC3__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `TC4_` reader - TC4"] +pub struct TC4__R(crate::FieldReader); +impl TC4__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC4__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC4__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC4_` writer - TC4"] +pub struct TC4__W<'a> { + w: &'a mut W, +} +impl<'a> TC4__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `ADC0_` reader - ADC0"] +pub struct ADC0__R(crate::FieldReader); +impl ADC0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ADC0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADC0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADC0_` writer - ADC0"] +pub struct ADC0__W<'a> { + w: &'a mut W, +} +impl<'a> ADC0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `ADC1_` reader - ADC1"] +pub struct ADC1__R(crate::FieldReader); +impl ADC1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ADC1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADC1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADC1_` writer - ADC1"] +pub struct ADC1__W<'a> { + w: &'a mut W, +} +impl<'a> ADC1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `SDADC_` reader - SDADC"] +pub struct SDADC__R(crate::FieldReader); +impl SDADC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SDADC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SDADC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SDADC_` writer - SDADC"] +pub struct SDADC__W<'a> { + w: &'a mut W, +} +impl<'a> SDADC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `AC_` reader - AC"] +pub struct AC__R(crate::FieldReader); +impl AC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AC_` writer - AC"] +pub struct AC__W<'a> { + w: &'a mut W, +} +impl<'a> AC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `DAC_` reader - DAC"] +pub struct DAC__R(crate::FieldReader); +impl DAC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DAC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DAC_` writer - DAC"] +pub struct DAC__W<'a> { + w: &'a mut W, +} +impl<'a> DAC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `PTC_` reader - PTC"] +pub struct PTC__R(crate::FieldReader); +impl PTC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PTC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PTC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PTC_` writer - PTC"] +pub struct PTC__W<'a> { + w: &'a mut W, +} +impl<'a> PTC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `CCL_` reader - CCL"] +pub struct CCL__R(crate::FieldReader); +impl CCL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCL_` writer - CCL"] +pub struct CCL__W<'a> { + w: &'a mut W, +} +impl<'a> CCL__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +impl R { + #[doc = "Bit 0 - EVSYS"] + #[inline(always)] + pub fn evsys_(&self) -> EVSYS__R { + EVSYS__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM0"] + #[inline(always)] + pub fn sercom0_(&self) -> SERCOM0__R { + SERCOM0__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - SERCOM1"] + #[inline(always)] + pub fn sercom1_(&self) -> SERCOM1__R { + SERCOM1__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - SERCOM2"] + #[inline(always)] + pub fn sercom2_(&self) -> SERCOM2__R { + SERCOM2__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - SERCOM3"] + #[inline(always)] + pub fn sercom3_(&self) -> SERCOM3__R { + SERCOM3__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - SERCOM4"] + #[inline(always)] + pub fn sercom4_(&self) -> SERCOM4__R { + SERCOM4__R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - SERCOM5"] + #[inline(always)] + pub fn sercom5_(&self) -> SERCOM5__R { + SERCOM5__R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - CAN0"] + #[inline(always)] + pub fn can0_(&self) -> CAN0__R { + CAN0__R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - CAN1"] + #[inline(always)] + pub fn can1_(&self) -> CAN1__R { + CAN1__R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - TCC0"] + #[inline(always)] + pub fn tcc0_(&self) -> TCC0__R { + TCC0__R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - TCC1"] + #[inline(always)] + pub fn tcc1_(&self) -> TCC1__R { + TCC1__R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - TCC2"] + #[inline(always)] + pub fn tcc2_(&self) -> TCC2__R { + TCC2__R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - TC0"] + #[inline(always)] + pub fn tc0_(&self) -> TC0__R { + TC0__R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - TC1"] + #[inline(always)] + pub fn tc1_(&self) -> TC1__R { + TC1__R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - TC2"] + #[inline(always)] + pub fn tc2_(&self) -> TC2__R { + TC2__R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - TC3"] + #[inline(always)] + pub fn tc3_(&self) -> TC3__R { + TC3__R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - TC4"] + #[inline(always)] + pub fn tc4_(&self) -> TC4__R { + TC4__R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - ADC0"] + #[inline(always)] + pub fn adc0_(&self) -> ADC0__R { + ADC0__R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - ADC1"] + #[inline(always)] + pub fn adc1_(&self) -> ADC1__R { + ADC1__R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - SDADC"] + #[inline(always)] + pub fn sdadc_(&self) -> SDADC__R { + SDADC__R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - AC"] + #[inline(always)] + pub fn ac_(&self) -> AC__R { + AC__R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - DAC"] + #[inline(always)] + pub fn dac_(&self) -> DAC__R { + DAC__R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - PTC"] + #[inline(always)] + pub fn ptc_(&self) -> PTC__R { + PTC__R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - CCL"] + #[inline(always)] + pub fn ccl_(&self) -> CCL__R { + CCL__R::new(((self.bits >> 23) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - EVSYS"] + #[inline(always)] + pub fn evsys_(&mut self) -> EVSYS__W { + EVSYS__W { w: self } + } + #[doc = "Bit 1 - SERCOM0"] + #[inline(always)] + pub fn sercom0_(&mut self) -> SERCOM0__W { + SERCOM0__W { w: self } + } + #[doc = "Bit 2 - SERCOM1"] + #[inline(always)] + pub fn sercom1_(&mut self) -> SERCOM1__W { + SERCOM1__W { w: self } + } + #[doc = "Bit 3 - SERCOM2"] + #[inline(always)] + pub fn sercom2_(&mut self) -> SERCOM2__W { + SERCOM2__W { w: self } + } + #[doc = "Bit 4 - SERCOM3"] + #[inline(always)] + pub fn sercom3_(&mut self) -> SERCOM3__W { + SERCOM3__W { w: self } + } + #[doc = "Bit 5 - SERCOM4"] + #[inline(always)] + pub fn sercom4_(&mut self) -> SERCOM4__W { + SERCOM4__W { w: self } + } + #[doc = "Bit 6 - SERCOM5"] + #[inline(always)] + pub fn sercom5_(&mut self) -> SERCOM5__W { + SERCOM5__W { w: self } + } + #[doc = "Bit 7 - CAN0"] + #[inline(always)] + pub fn can0_(&mut self) -> CAN0__W { + CAN0__W { w: self } + } + #[doc = "Bit 8 - CAN1"] + #[inline(always)] + pub fn can1_(&mut self) -> CAN1__W { + CAN1__W { w: self } + } + #[doc = "Bit 9 - TCC0"] + #[inline(always)] + pub fn tcc0_(&mut self) -> TCC0__W { + TCC0__W { w: self } + } + #[doc = "Bit 10 - TCC1"] + #[inline(always)] + pub fn tcc1_(&mut self) -> TCC1__W { + TCC1__W { w: self } + } + #[doc = "Bit 11 - TCC2"] + #[inline(always)] + pub fn tcc2_(&mut self) -> TCC2__W { + TCC2__W { w: self } + } + #[doc = "Bit 12 - TC0"] + #[inline(always)] + pub fn tc0_(&mut self) -> TC0__W { + TC0__W { w: self } + } + #[doc = "Bit 13 - TC1"] + #[inline(always)] + pub fn tc1_(&mut self) -> TC1__W { + TC1__W { w: self } + } + #[doc = "Bit 14 - TC2"] + #[inline(always)] + pub fn tc2_(&mut self) -> TC2__W { + TC2__W { w: self } + } + #[doc = "Bit 15 - TC3"] + #[inline(always)] + pub fn tc3_(&mut self) -> TC3__W { + TC3__W { w: self } + } + #[doc = "Bit 16 - TC4"] + #[inline(always)] + pub fn tc4_(&mut self) -> TC4__W { + TC4__W { w: self } + } + #[doc = "Bit 17 - ADC0"] + #[inline(always)] + pub fn adc0_(&mut self) -> ADC0__W { + ADC0__W { w: self } + } + #[doc = "Bit 18 - ADC1"] + #[inline(always)] + pub fn adc1_(&mut self) -> ADC1__W { + ADC1__W { w: self } + } + #[doc = "Bit 19 - SDADC"] + #[inline(always)] + pub fn sdadc_(&mut self) -> SDADC__W { + SDADC__W { w: self } + } + #[doc = "Bit 20 - AC"] + #[inline(always)] + pub fn ac_(&mut self) -> AC__W { + AC__W { w: self } + } + #[doc = "Bit 21 - DAC"] + #[inline(always)] + pub fn dac_(&mut self) -> DAC__W { + DAC__W { w: self } + } + #[doc = "Bit 22 - PTC"] + #[inline(always)] + pub fn ptc_(&mut self) -> PTC__W { + PTC__W { w: self } + } + #[doc = "Bit 23 - CCL"] + #[inline(always)] + pub fn ccl_(&mut self) -> CCL__W { + CCL__W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Peripheral interrupt flag status - Bridge C\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflagc](index.html) module"] +pub struct INTFLAGC_SPEC; +impl crate::RegisterSpec for INTFLAGC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflagc::R](R) reader structure"] +impl crate::Readable for INTFLAGC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflagc::W](W) writer structure"] +impl crate::Writable for INTFLAGC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAGC to value 0"] +impl crate::Resettable for INTFLAGC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/pac/statusa.rs b/pac/atsamc21g/src/pac/statusa.rs new file mode 100644 index 000000000000..ca22aef2f1ce --- /dev/null +++ b/pac/atsamc21g/src/pac/statusa.rs @@ -0,0 +1,293 @@ +#[doc = "Register `STATUSA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PAC_` reader - PAC APB Protect Enable"] +pub struct PAC__R(crate::FieldReader); +impl PAC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PAC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PM_` reader - PM APB Protect Enable"] +pub struct PM__R(crate::FieldReader); +impl PM__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PM__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PM__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCLK_` reader - MCLK APB Protect Enable"] +pub struct MCLK__R(crate::FieldReader); +impl MCLK__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCLK__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCLK__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RSTC_` reader - RSTC APB Protect Enable"] +pub struct RSTC__R(crate::FieldReader); +impl RSTC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RSTC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RSTC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSCCTRL_` reader - OSCCTRL APB Protect Enable"] +pub struct OSCCTRL__R(crate::FieldReader); +impl OSCCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSCCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSCCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC32KCTRL_` reader - OSC32KCTRL APB Protect Enable"] +pub struct OSC32KCTRL__R(crate::FieldReader); +impl OSC32KCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC32KCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC32KCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SUPC_` reader - SUPC APB Protect Enable"] +pub struct SUPC__R(crate::FieldReader); +impl SUPC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SUPC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SUPC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GCLK_` reader - GCLK APB Protect Enable"] +pub struct GCLK__R(crate::FieldReader); +impl GCLK__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GCLK__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GCLK__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WDT_` reader - WDT APB Protect Enable"] +pub struct WDT__R(crate::FieldReader); +impl WDT__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WDT__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WDT__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RTC_` reader - RTC APB Protect Enable"] +pub struct RTC__R(crate::FieldReader); +impl RTC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RTC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RTC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EIC_` reader - EIC APB Protect Enable"] +pub struct EIC__R(crate::FieldReader); +impl EIC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EIC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EIC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FREQM_` reader - FREQM APB Protect Enable"] +pub struct FREQM__R(crate::FieldReader); +impl FREQM__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FREQM__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FREQM__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSENS_` reader - TSENS APB Protect Enable"] +pub struct TSENS__R(crate::FieldReader); +impl TSENS__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSENS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSENS__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - PAC APB Protect Enable"] + #[inline(always)] + pub fn pac_(&self) -> PAC__R { + PAC__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - PM APB Protect Enable"] + #[inline(always)] + pub fn pm_(&self) -> PM__R { + PM__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - MCLK APB Protect Enable"] + #[inline(always)] + pub fn mclk_(&self) -> MCLK__R { + MCLK__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - RSTC APB Protect Enable"] + #[inline(always)] + pub fn rstc_(&self) -> RSTC__R { + RSTC__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - OSCCTRL APB Protect Enable"] + #[inline(always)] + pub fn oscctrl_(&self) -> OSCCTRL__R { + OSCCTRL__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - OSC32KCTRL APB Protect Enable"] + #[inline(always)] + pub fn osc32kctrl_(&self) -> OSC32KCTRL__R { + OSC32KCTRL__R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - SUPC APB Protect Enable"] + #[inline(always)] + pub fn supc_(&self) -> SUPC__R { + SUPC__R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - GCLK APB Protect Enable"] + #[inline(always)] + pub fn gclk_(&self) -> GCLK__R { + GCLK__R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - WDT APB Protect Enable"] + #[inline(always)] + pub fn wdt_(&self) -> WDT__R { + WDT__R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - RTC APB Protect Enable"] + #[inline(always)] + pub fn rtc_(&self) -> RTC__R { + RTC__R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - EIC APB Protect Enable"] + #[inline(always)] + pub fn eic_(&self) -> EIC__R { + EIC__R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - FREQM APB Protect Enable"] + #[inline(always)] + pub fn freqm_(&self) -> FREQM__R { + FREQM__R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - TSENS APB Protect Enable"] + #[inline(always)] + pub fn tsens_(&self) -> TSENS__R { + TSENS__R::new(((self.bits >> 12) & 0x01) != 0) + } +} +#[doc = "Peripheral write protection status - Bridge A\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [statusa](index.html) module"] +pub struct STATUSA_SPEC; +impl crate::RegisterSpec for STATUSA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [statusa::R](R) reader structure"] +impl crate::Readable for STATUSA_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUSA to value 0"] +impl crate::Resettable for STATUSA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/pac/statusb.rs b/pac/atsamc21g/src/pac/statusb.rs new file mode 100644 index 000000000000..a022cc2f1d54 --- /dev/null +++ b/pac/atsamc21g/src/pac/statusb.rs @@ -0,0 +1,153 @@ +#[doc = "Register `STATUSB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PORT_` reader - PORT APB Protect Enable"] +pub struct PORT__R(crate::FieldReader); +impl PORT__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PORT__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PORT__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DSU_` reader - DSU APB Protect Enable"] +pub struct DSU__R(crate::FieldReader); +impl DSU__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DSU__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DSU__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NVMCTRL_` reader - NVMCTRL APB Protect Enable"] +pub struct NVMCTRL__R(crate::FieldReader); +impl NVMCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NVMCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NVMCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DMAC_` reader - DMAC APB Protect Enable"] +pub struct DMAC__R(crate::FieldReader); +impl DMAC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DMAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DMAC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MTB_` reader - MTB APB Protect Enable"] +pub struct MTB__R(crate::FieldReader); +impl MTB__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MTB__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MTB__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HMATRIXHS_` reader - HMATRIXHS APB Protect Enable"] +pub struct HMATRIXHS__R(crate::FieldReader); +impl HMATRIXHS__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HMATRIXHS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HMATRIXHS__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - PORT APB Protect Enable"] + #[inline(always)] + pub fn port_(&self) -> PORT__R { + PORT__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - DSU APB Protect Enable"] + #[inline(always)] + pub fn dsu_(&self) -> DSU__R { + DSU__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - NVMCTRL APB Protect Enable"] + #[inline(always)] + pub fn nvmctrl_(&self) -> NVMCTRL__R { + NVMCTRL__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - DMAC APB Protect Enable"] + #[inline(always)] + pub fn dmac_(&self) -> DMAC__R { + DMAC__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - MTB APB Protect Enable"] + #[inline(always)] + pub fn mtb_(&self) -> MTB__R { + MTB__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - HMATRIXHS APB Protect Enable"] + #[inline(always)] + pub fn hmatrixhs_(&self) -> HMATRIXHS__R { + HMATRIXHS__R::new(((self.bits >> 5) & 0x01) != 0) + } +} +#[doc = "Peripheral write protection status - Bridge B\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [statusb](index.html) module"] +pub struct STATUSB_SPEC; +impl crate::RegisterSpec for STATUSB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [statusb::R](R) reader structure"] +impl crate::Readable for STATUSB_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUSB to value 0x02"] +impl crate::Resettable for STATUSB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x02 + } +} diff --git a/pac/atsamc21g/src/pac/statusc.rs b/pac/atsamc21g/src/pac/statusc.rs new file mode 100644 index 000000000000..8c986ef451bb --- /dev/null +++ b/pac/atsamc21g/src/pac/statusc.rs @@ -0,0 +1,513 @@ +#[doc = "Register `STATUSC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `EVSYS_` reader - EVSYS APB Protect Enable"] +pub struct EVSYS__R(crate::FieldReader); +impl EVSYS__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVSYS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVSYS__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM0_` reader - SERCOM0 APB Protect Enable"] +pub struct SERCOM0__R(crate::FieldReader); +impl SERCOM0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM1_` reader - SERCOM1 APB Protect Enable"] +pub struct SERCOM1__R(crate::FieldReader); +impl SERCOM1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM2_` reader - SERCOM2 APB Protect Enable"] +pub struct SERCOM2__R(crate::FieldReader); +impl SERCOM2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM3_` reader - SERCOM3 APB Protect Enable"] +pub struct SERCOM3__R(crate::FieldReader); +impl SERCOM3__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM3__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM3__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM4_` reader - SERCOM4 APB Protect Enable"] +pub struct SERCOM4__R(crate::FieldReader); +impl SERCOM4__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM4__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM4__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM5_` reader - SERCOM5 APB Protect Enable"] +pub struct SERCOM5__R(crate::FieldReader); +impl SERCOM5__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM5__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM5__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAN0_` reader - CAN0 APB Protect Enable"] +pub struct CAN0__R(crate::FieldReader); +impl CAN0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CAN0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CAN0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAN1_` reader - CAN1 APB Protect Enable"] +pub struct CAN1__R(crate::FieldReader); +impl CAN1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CAN1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CAN1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCC0_` reader - TCC0 APB Protect Enable"] +pub struct TCC0__R(crate::FieldReader); +impl TCC0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCC0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCC0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCC1_` reader - TCC1 APB Protect Enable"] +pub struct TCC1__R(crate::FieldReader); +impl TCC1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCC1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCC1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCC2_` reader - TCC2 APB Protect Enable"] +pub struct TCC2__R(crate::FieldReader); +impl TCC2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCC2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCC2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC0_` reader - TC0 APB Protect Enable"] +pub struct TC0__R(crate::FieldReader); +impl TC0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC1_` reader - TC1 APB Protect Enable"] +pub struct TC1__R(crate::FieldReader); +impl TC1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC2_` reader - TC2 APB Protect Enable"] +pub struct TC2__R(crate::FieldReader); +impl TC2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC3_` reader - TC3 APB Protect Enable"] +pub struct TC3__R(crate::FieldReader); +impl TC3__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC3__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC3__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC4_` reader - TC4 APB Protect Enable"] +pub struct TC4__R(crate::FieldReader); +impl TC4__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC4__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC4__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADC0_` reader - ADC0 APB Protect Enable"] +pub struct ADC0__R(crate::FieldReader); +impl ADC0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ADC0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADC0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADC1_` reader - ADC1 APB Protect Enable"] +pub struct ADC1__R(crate::FieldReader); +impl ADC1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ADC1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADC1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SDADC_` reader - SDADC APB Protect Enable"] +pub struct SDADC__R(crate::FieldReader); +impl SDADC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SDADC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SDADC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AC_` reader - AC APB Protect Enable"] +pub struct AC__R(crate::FieldReader); +impl AC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DAC_` reader - DAC APB Protect Enable"] +pub struct DAC__R(crate::FieldReader); +impl DAC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DAC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PTC_` reader - PTC APB Protect Enable"] +pub struct PTC__R(crate::FieldReader); +impl PTC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PTC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PTC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCL_` reader - CCL APB Protect Enable"] +pub struct CCL__R(crate::FieldReader); +impl CCL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - EVSYS APB Protect Enable"] + #[inline(always)] + pub fn evsys_(&self) -> EVSYS__R { + EVSYS__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM0 APB Protect Enable"] + #[inline(always)] + pub fn sercom0_(&self) -> SERCOM0__R { + SERCOM0__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - SERCOM1 APB Protect Enable"] + #[inline(always)] + pub fn sercom1_(&self) -> SERCOM1__R { + SERCOM1__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - SERCOM2 APB Protect Enable"] + #[inline(always)] + pub fn sercom2_(&self) -> SERCOM2__R { + SERCOM2__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - SERCOM3 APB Protect Enable"] + #[inline(always)] + pub fn sercom3_(&self) -> SERCOM3__R { + SERCOM3__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - SERCOM4 APB Protect Enable"] + #[inline(always)] + pub fn sercom4_(&self) -> SERCOM4__R { + SERCOM4__R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - SERCOM5 APB Protect Enable"] + #[inline(always)] + pub fn sercom5_(&self) -> SERCOM5__R { + SERCOM5__R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - CAN0 APB Protect Enable"] + #[inline(always)] + pub fn can0_(&self) -> CAN0__R { + CAN0__R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - CAN1 APB Protect Enable"] + #[inline(always)] + pub fn can1_(&self) -> CAN1__R { + CAN1__R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - TCC0 APB Protect Enable"] + #[inline(always)] + pub fn tcc0_(&self) -> TCC0__R { + TCC0__R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - TCC1 APB Protect Enable"] + #[inline(always)] + pub fn tcc1_(&self) -> TCC1__R { + TCC1__R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - TCC2 APB Protect Enable"] + #[inline(always)] + pub fn tcc2_(&self) -> TCC2__R { + TCC2__R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - TC0 APB Protect Enable"] + #[inline(always)] + pub fn tc0_(&self) -> TC0__R { + TC0__R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - TC1 APB Protect Enable"] + #[inline(always)] + pub fn tc1_(&self) -> TC1__R { + TC1__R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - TC2 APB Protect Enable"] + #[inline(always)] + pub fn tc2_(&self) -> TC2__R { + TC2__R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - TC3 APB Protect Enable"] + #[inline(always)] + pub fn tc3_(&self) -> TC3__R { + TC3__R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - TC4 APB Protect Enable"] + #[inline(always)] + pub fn tc4_(&self) -> TC4__R { + TC4__R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - ADC0 APB Protect Enable"] + #[inline(always)] + pub fn adc0_(&self) -> ADC0__R { + ADC0__R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - ADC1 APB Protect Enable"] + #[inline(always)] + pub fn adc1_(&self) -> ADC1__R { + ADC1__R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - SDADC APB Protect Enable"] + #[inline(always)] + pub fn sdadc_(&self) -> SDADC__R { + SDADC__R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - AC APB Protect Enable"] + #[inline(always)] + pub fn ac_(&self) -> AC__R { + AC__R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - DAC APB Protect Enable"] + #[inline(always)] + pub fn dac_(&self) -> DAC__R { + DAC__R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - PTC APB Protect Enable"] + #[inline(always)] + pub fn ptc_(&self) -> PTC__R { + PTC__R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - CCL APB Protect Enable"] + #[inline(always)] + pub fn ccl_(&self) -> CCL__R { + CCL__R::new(((self.bits >> 23) & 0x01) != 0) + } +} +#[doc = "Peripheral write protection status - Bridge C\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [statusc](index.html) module"] +pub struct STATUSC_SPEC; +impl crate::RegisterSpec for STATUSC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [statusc::R](R) reader structure"] +impl crate::Readable for STATUSC_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUSC to value 0x0200_0000"] +impl crate::Resettable for STATUSC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0200_0000 + } +} diff --git a/pac/atsamc21g/src/pac/wrctrl.rs b/pac/atsamc21g/src/pac/wrctrl.rs new file mode 100644 index 000000000000..65773ea08d64 --- /dev/null +++ b/pac/atsamc21g/src/pac/wrctrl.rs @@ -0,0 +1,215 @@ +#[doc = "Register `WRCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WRCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PERID` reader - Peripheral identifier"] +pub struct PERID_R(crate::FieldReader); +impl PERID_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + PERID_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERID_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERID` writer - Peripheral identifier"] +pub struct PERID_W<'a> { + w: &'a mut W, +} +impl<'a> PERID_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +#[doc = "Peripheral access control key\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum KEY_A { + #[doc = "0: No action"] + OFF = 0, + #[doc = "1: Clear protection"] + CLR = 1, + #[doc = "2: Set protection"] + SET = 2, + #[doc = "3: Set and lock protection"] + SETLCK = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: KEY_A) -> Self { + variant as _ + } +} +#[doc = "Field `KEY` reader - Peripheral access control key"] +pub struct KEY_R(crate::FieldReader); +impl KEY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + KEY_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(KEY_A::OFF), + 1 => Some(KEY_A::CLR), + 2 => Some(KEY_A::SET), + 3 => Some(KEY_A::SETLCK), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == KEY_A::OFF + } + #[doc = "Checks if the value of the field is `CLR`"] + #[inline(always)] + pub fn is_clr(&self) -> bool { + **self == KEY_A::CLR + } + #[doc = "Checks if the value of the field is `SET`"] + #[inline(always)] + pub fn is_set(&self) -> bool { + **self == KEY_A::SET + } + #[doc = "Checks if the value of the field is `SETLCK`"] + #[inline(always)] + pub fn is_setlck(&self) -> bool { + **self == KEY_A::SETLCK + } +} +impl core::ops::Deref for KEY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `KEY` writer - Peripheral access control key"] +pub struct KEY_W<'a> { + w: &'a mut W, +} +impl<'a> KEY_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: KEY_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(KEY_A::OFF) + } + #[doc = "Clear protection"] + #[inline(always)] + pub fn clr(self) -> &'a mut W { + self.variant(KEY_A::CLR) + } + #[doc = "Set protection"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(KEY_A::SET) + } + #[doc = "Set and lock protection"] + #[inline(always)] + pub fn setlck(self) -> &'a mut W { + self.variant(KEY_A::SETLCK) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Peripheral identifier"] + #[inline(always)] + pub fn perid(&self) -> PERID_R { + PERID_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:23 - Peripheral access control key"] + #[inline(always)] + pub fn key(&self) -> KEY_R { + KEY_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:15 - Peripheral identifier"] + #[inline(always)] + pub fn perid(&mut self) -> PERID_W { + PERID_W { w: self } + } + #[doc = "Bits 16:23 - Peripheral access control key"] + #[inline(always)] + pub fn key(&mut self) -> KEY_W { + KEY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Write control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wrctrl](index.html) module"] +pub struct WRCTRL_SPEC; +impl crate::RegisterSpec for WRCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [wrctrl::R](R) reader structure"] +impl crate::Readable for WRCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wrctrl::W](W) writer structure"] +impl crate::Writable for WRCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WRCTRL to value 0"] +impl crate::Resettable for WRCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/pm.rs b/pac/atsamc21g/src/pm.rs new file mode 100644 index 000000000000..9da2b0e13288 --- /dev/null +++ b/pac/atsamc21g/src/pm.rs @@ -0,0 +1,18 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved0: [u8; 0x01], + #[doc = "0x01 - Sleep Configuration"] + pub sleepcfg: crate::Reg, + _reserved1: [u8; 0x06], + #[doc = "0x08 - Standby Configuration"] + pub stdbycfg: crate::Reg, +} +#[doc = "SLEEPCFG register accessor: an alias for `Reg`"] +pub type SLEEPCFG = crate::Reg; +#[doc = "Sleep Configuration"] +pub mod sleepcfg; +#[doc = "STDBYCFG register accessor: an alias for `Reg`"] +pub type STDBYCFG = crate::Reg; +#[doc = "Standby Configuration"] +pub mod stdbycfg; diff --git a/pac/atsamc21g/src/pm/sleepcfg.rs b/pac/atsamc21g/src/pm/sleepcfg.rs new file mode 100644 index 000000000000..ef643311a059 --- /dev/null +++ b/pac/atsamc21g/src/pm/sleepcfg.rs @@ -0,0 +1,178 @@ +#[doc = "Register `SLEEPCFG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SLEEPCFG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Sleep Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SLEEPMODE_A { + #[doc = "0: CPU clock is OFF"] + IDLE0 = 0, + #[doc = "1: AHB clock is OFF"] + IDLE1 = 1, + #[doc = "2: APB clock are OFF"] + IDLE2 = 2, + #[doc = "4: All Clocks are OFF"] + STANDBY = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SLEEPMODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `SLEEPMODE` reader - Sleep Mode"] +pub struct SLEEPMODE_R(crate::FieldReader); +impl SLEEPMODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SLEEPMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SLEEPMODE_A::IDLE0), + 1 => Some(SLEEPMODE_A::IDLE1), + 2 => Some(SLEEPMODE_A::IDLE2), + 4 => Some(SLEEPMODE_A::STANDBY), + _ => None, + } + } + #[doc = "Checks if the value of the field is `IDLE0`"] + #[inline(always)] + pub fn is_idle0(&self) -> bool { + **self == SLEEPMODE_A::IDLE0 + } + #[doc = "Checks if the value of the field is `IDLE1`"] + #[inline(always)] + pub fn is_idle1(&self) -> bool { + **self == SLEEPMODE_A::IDLE1 + } + #[doc = "Checks if the value of the field is `IDLE2`"] + #[inline(always)] + pub fn is_idle2(&self) -> bool { + **self == SLEEPMODE_A::IDLE2 + } + #[doc = "Checks if the value of the field is `STANDBY`"] + #[inline(always)] + pub fn is_standby(&self) -> bool { + **self == SLEEPMODE_A::STANDBY + } +} +impl core::ops::Deref for SLEEPMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLEEPMODE` writer - Sleep Mode"] +pub struct SLEEPMODE_W<'a> { + w: &'a mut W, +} +impl<'a> SLEEPMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SLEEPMODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "CPU clock is OFF"] + #[inline(always)] + pub fn idle0(self) -> &'a mut W { + self.variant(SLEEPMODE_A::IDLE0) + } + #[doc = "AHB clock is OFF"] + #[inline(always)] + pub fn idle1(self) -> &'a mut W { + self.variant(SLEEPMODE_A::IDLE1) + } + #[doc = "APB clock are OFF"] + #[inline(always)] + pub fn idle2(self) -> &'a mut W { + self.variant(SLEEPMODE_A::IDLE2) + } + #[doc = "All Clocks are OFF"] + #[inline(always)] + pub fn standby(self) -> &'a mut W { + self.variant(SLEEPMODE_A::STANDBY) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Sleep Mode"] + #[inline(always)] + pub fn sleepmode(&self) -> SLEEPMODE_R { + SLEEPMODE_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Sleep Mode"] + #[inline(always)] + pub fn sleepmode(&mut self) -> SLEEPMODE_W { + SLEEPMODE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Sleep Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sleepcfg](index.html) module"] +pub struct SLEEPCFG_SPEC; +impl crate::RegisterSpec for SLEEPCFG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [sleepcfg::R](R) reader structure"] +impl crate::Readable for SLEEPCFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [sleepcfg::W](W) writer structure"] +impl crate::Writable for SLEEPCFG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SLEEPCFG to value 0"] +impl crate::Resettable for SLEEPCFG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/pm/stdbycfg.rs b/pac/atsamc21g/src/pm/stdbycfg.rs new file mode 100644 index 000000000000..9780f2b001f5 --- /dev/null +++ b/pac/atsamc21g/src/pm/stdbycfg.rs @@ -0,0 +1,212 @@ +#[doc = "Register `STDBYCFG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STDBYCFG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Voltage Regulator Standby mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum VREGSMOD_A { + #[doc = "0: Automatic mode"] + AUTO = 0, + #[doc = "1: Performance oriented"] + PERFORMANCE = 1, + #[doc = "2: Low Power oriented"] + LP = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: VREGSMOD_A) -> Self { + variant as _ + } +} +#[doc = "Field `VREGSMOD` reader - Voltage Regulator Standby mode"] +pub struct VREGSMOD_R(crate::FieldReader); +impl VREGSMOD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + VREGSMOD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(VREGSMOD_A::AUTO), + 1 => Some(VREGSMOD_A::PERFORMANCE), + 2 => Some(VREGSMOD_A::LP), + _ => None, + } + } + #[doc = "Checks if the value of the field is `AUTO`"] + #[inline(always)] + pub fn is_auto(&self) -> bool { + **self == VREGSMOD_A::AUTO + } + #[doc = "Checks if the value of the field is `PERFORMANCE`"] + #[inline(always)] + pub fn is_performance(&self) -> bool { + **self == VREGSMOD_A::PERFORMANCE + } + #[doc = "Checks if the value of the field is `LP`"] + #[inline(always)] + pub fn is_lp(&self) -> bool { + **self == VREGSMOD_A::LP + } +} +impl core::ops::Deref for VREGSMOD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VREGSMOD` writer - Voltage Regulator Standby mode"] +pub struct VREGSMOD_W<'a> { + w: &'a mut W, +} +impl<'a> VREGSMOD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: VREGSMOD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Automatic mode"] + #[inline(always)] + pub fn auto(self) -> &'a mut W { + self.variant(VREGSMOD_A::AUTO) + } + #[doc = "Performance oriented"] + #[inline(always)] + pub fn performance(self) -> &'a mut W { + self.variant(VREGSMOD_A::PERFORMANCE) + } + #[doc = "Low Power oriented"] + #[inline(always)] + pub fn lp(self) -> &'a mut W { + self.variant(VREGSMOD_A::LP) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 6)) | ((value as u16 & 0x03) << 6); + self.w + } +} +#[doc = "Field `BBIASHS` reader - Back Bias for HMCRAMCHS"] +pub struct BBIASHS_R(crate::FieldReader); +impl BBIASHS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BBIASHS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BBIASHS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BBIASHS` writer - Back Bias for HMCRAMCHS"] +pub struct BBIASHS_W<'a> { + w: &'a mut W, +} +impl<'a> BBIASHS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u16 & 0x01) << 10); + self.w + } +} +impl R { + #[doc = "Bits 6:7 - Voltage Regulator Standby mode"] + #[inline(always)] + pub fn vregsmod(&self) -> VREGSMOD_R { + VREGSMOD_R::new(((self.bits >> 6) & 0x03) as u8) + } + #[doc = "Bit 10 - Back Bias for HMCRAMCHS"] + #[inline(always)] + pub fn bbiashs(&self) -> BBIASHS_R { + BBIASHS_R::new(((self.bits >> 10) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 6:7 - Voltage Regulator Standby mode"] + #[inline(always)] + pub fn vregsmod(&mut self) -> VREGSMOD_W { + VREGSMOD_W { w: self } + } + #[doc = "Bit 10 - Back Bias for HMCRAMCHS"] + #[inline(always)] + pub fn bbiashs(&mut self) -> BBIASHS_W { + BBIASHS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Standby Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [stdbycfg](index.html) module"] +pub struct STDBYCFG_SPEC; +impl crate::RegisterSpec for STDBYCFG_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [stdbycfg::R](R) reader structure"] +impl crate::Readable for STDBYCFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [stdbycfg::W](W) writer structure"] +impl crate::Writable for STDBYCFG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STDBYCFG to value 0x0400"] +impl crate::Resettable for STDBYCFG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0400 + } +} diff --git a/pac/atsamc21g/src/port.rs b/pac/atsamc21g/src/port.rs new file mode 100644 index 000000000000..08c16491ba07 --- /dev/null +++ b/pac/atsamc21g/src/port.rs @@ -0,0 +1,44 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00..0x60 - GROUP\\[%s\\]"] + pub group0: GROUP, + _reserved1: [u8; 0x20], + #[doc = "0x80..0xe0 - GROUP\\[%s\\]"] + pub group1: GROUP, +} +#[doc = r"Register block"] +#[repr(C)] +pub struct GROUP { + #[doc = "0x00 - Data Direction"] + pub dir: crate::Reg, + #[doc = "0x04 - Data Direction Clear"] + pub dirclr: crate::Reg, + #[doc = "0x08 - Data Direction Set"] + pub dirset: crate::Reg, + #[doc = "0x0c - Data Direction Toggle"] + pub dirtgl: crate::Reg, + #[doc = "0x10 - Data Output Value"] + pub out: crate::Reg, + #[doc = "0x14 - Data Output Value Clear"] + pub outclr: crate::Reg, + #[doc = "0x18 - Data Output Value Set"] + pub outset: crate::Reg, + #[doc = "0x1c - Data Output Value Toggle"] + pub outtgl: crate::Reg, + #[doc = "0x20 - Data Input Value"] + pub in_: crate::Reg, + #[doc = "0x24 - Control"] + pub ctrl: crate::Reg, + #[doc = "0x28 - Write Configuration"] + pub wrconfig: crate::Reg, + #[doc = "0x2c - Event Input Control"] + pub evctrl: crate::Reg, + #[doc = "0x30..0x40 - Peripheral Multiplexing n"] + pub pmux: [crate::Reg; 16], + #[doc = "0x40..0x60 - Pin Configuration n"] + pub pincfg: [crate::Reg; 32], +} +#[doc = r"Register block"] +#[doc = "GROUP\\[%s\\]"] +pub mod group; diff --git a/pac/atsamc21g/src/port/group.rs b/pac/atsamc21g/src/port/group.rs new file mode 100644 index 000000000000..d1aabcd73380 --- /dev/null +++ b/pac/atsamc21g/src/port/group.rs @@ -0,0 +1,56 @@ +#[doc = "DIR register accessor: an alias for `Reg`"] +pub type DIR = crate::Reg; +#[doc = "Data Direction"] +pub mod dir; +#[doc = "DIRCLR register accessor: an alias for `Reg`"] +pub type DIRCLR = crate::Reg; +#[doc = "Data Direction Clear"] +pub mod dirclr; +#[doc = "DIRSET register accessor: an alias for `Reg`"] +pub type DIRSET = crate::Reg; +#[doc = "Data Direction Set"] +pub mod dirset; +#[doc = "DIRTGL register accessor: an alias for `Reg`"] +pub type DIRTGL = crate::Reg; +#[doc = "Data Direction Toggle"] +pub mod dirtgl; +#[doc = "OUT register accessor: an alias for `Reg`"] +pub type OUT = crate::Reg; +#[doc = "Data Output Value"] +pub mod out; +#[doc = "OUTCLR register accessor: an alias for `Reg`"] +pub type OUTCLR = crate::Reg; +#[doc = "Data Output Value Clear"] +pub mod outclr; +#[doc = "OUTSET register accessor: an alias for `Reg`"] +pub type OUTSET = crate::Reg; +#[doc = "Data Output Value Set"] +pub mod outset; +#[doc = "OUTTGL register accessor: an alias for `Reg`"] +pub type OUTTGL = crate::Reg; +#[doc = "Data Output Value Toggle"] +pub mod outtgl; +#[doc = "IN register accessor: an alias for `Reg`"] +pub type IN = crate::Reg; +#[doc = "Data Input Value"] +pub mod in_; +#[doc = "CTRL register accessor: an alias for `Reg`"] +pub type CTRL = crate::Reg; +#[doc = "Control"] +pub mod ctrl; +#[doc = "WRCONFIG register accessor: an alias for `Reg`"] +pub type WRCONFIG = crate::Reg; +#[doc = "Write Configuration"] +pub mod wrconfig; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Input Control"] +pub mod evctrl; +#[doc = "PMUX register accessor: an alias for `Reg`"] +pub type PMUX = crate::Reg; +#[doc = "Peripheral Multiplexing n"] +pub mod pmux; +#[doc = "PINCFG register accessor: an alias for `Reg`"] +pub type PINCFG = crate::Reg; +#[doc = "Pin Configuration n"] +pub mod pincfg; diff --git a/pac/atsamc21g/src/port/group/ctrl.rs b/pac/atsamc21g/src/port/group/ctrl.rs new file mode 100644 index 000000000000..4b57cd6fcd2b --- /dev/null +++ b/pac/atsamc21g/src/port/group/ctrl.rs @@ -0,0 +1,103 @@ +#[doc = "Register `CTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SAMPLING` reader - Input Sampling Mode"] +pub struct SAMPLING_R(crate::FieldReader); +impl SAMPLING_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + SAMPLING_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SAMPLING_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SAMPLING` writer - Input Sampling Mode"] +pub struct SAMPLING_W<'a> { + w: &'a mut W, +} +impl<'a> SAMPLING_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Input Sampling Mode"] + #[inline(always)] + pub fn sampling(&self) -> SAMPLING_R { + SAMPLING_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Input Sampling Mode"] + #[inline(always)] + pub fn sampling(&mut self) -> SAMPLING_W { + SAMPLING_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"] +pub struct CTRL_SPEC; +impl crate::RegisterSpec for CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrl::R](R) reader structure"] +impl crate::Readable for CTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"] +impl crate::Writable for CTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/port/group/dir.rs b/pac/atsamc21g/src/port/group/dir.rs new file mode 100644 index 000000000000..e04452fb5d35 --- /dev/null +++ b/pac/atsamc21g/src/port/group/dir.rs @@ -0,0 +1,64 @@ +#[doc = "Register `DIR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Direction\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dir](index.html) module"] +pub struct DIR_SPEC; +impl crate::RegisterSpec for DIR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dir::R](R) reader structure"] +impl crate::Readable for DIR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dir::W](W) writer structure"] +impl crate::Writable for DIR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DIR to value 0"] +impl crate::Resettable for DIR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/port/group/dirclr.rs b/pac/atsamc21g/src/port/group/dirclr.rs new file mode 100644 index 000000000000..5e6d73d032b2 --- /dev/null +++ b/pac/atsamc21g/src/port/group/dirclr.rs @@ -0,0 +1,64 @@ +#[doc = "Register `DIRCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIRCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Direction Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dirclr](index.html) module"] +pub struct DIRCLR_SPEC; +impl crate::RegisterSpec for DIRCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dirclr::R](R) reader structure"] +impl crate::Readable for DIRCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dirclr::W](W) writer structure"] +impl crate::Writable for DIRCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DIRCLR to value 0"] +impl crate::Resettable for DIRCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/port/group/dirset.rs b/pac/atsamc21g/src/port/group/dirset.rs new file mode 100644 index 000000000000..eaa86e14f15d --- /dev/null +++ b/pac/atsamc21g/src/port/group/dirset.rs @@ -0,0 +1,64 @@ +#[doc = "Register `DIRSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIRSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Direction Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dirset](index.html) module"] +pub struct DIRSET_SPEC; +impl crate::RegisterSpec for DIRSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dirset::R](R) reader structure"] +impl crate::Readable for DIRSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dirset::W](W) writer structure"] +impl crate::Writable for DIRSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DIRSET to value 0"] +impl crate::Resettable for DIRSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/port/group/dirtgl.rs b/pac/atsamc21g/src/port/group/dirtgl.rs new file mode 100644 index 000000000000..fbd021438b1b --- /dev/null +++ b/pac/atsamc21g/src/port/group/dirtgl.rs @@ -0,0 +1,64 @@ +#[doc = "Register `DIRTGL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIRTGL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Direction Toggle\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dirtgl](index.html) module"] +pub struct DIRTGL_SPEC; +impl crate::RegisterSpec for DIRTGL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dirtgl::R](R) reader structure"] +impl crate::Readable for DIRTGL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dirtgl::W](W) writer structure"] +impl crate::Writable for DIRTGL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DIRTGL to value 0"] +impl crate::Resettable for DIRTGL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/port/group/evctrl.rs b/pac/atsamc21g/src/port/group/evctrl.rs new file mode 100644 index 000000000000..ef0a35987f3d --- /dev/null +++ b/pac/atsamc21g/src/port/group/evctrl.rs @@ -0,0 +1,625 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PID0` reader - Port Event Pin Identifier 0"] +pub struct PID0_R(crate::FieldReader); +impl PID0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PID0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PID0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PID0` writer - Port Event Pin Identifier 0"] +pub struct PID0_W<'a> { + w: &'a mut W, +} +impl<'a> PID0_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f); + self.w + } +} +#[doc = "Port Event Action 0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EVACT0_A { + #[doc = "0: Event output to pin"] + OUT = 0, + #[doc = "1: Set output register of pin on event"] + SET = 1, + #[doc = "2: Clear output register of pin on event"] + CLR = 2, + #[doc = "3: Toggle output register of pin on event"] + TGL = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EVACT0_A) -> Self { + variant as _ + } +} +#[doc = "Field `EVACT0` reader - Port Event Action 0"] +pub struct EVACT0_R(crate::FieldReader); +impl EVACT0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVACT0_A { + match self.bits { + 0 => EVACT0_A::OUT, + 1 => EVACT0_A::SET, + 2 => EVACT0_A::CLR, + 3 => EVACT0_A::TGL, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `OUT`"] + #[inline(always)] + pub fn is_out(&self) -> bool { + **self == EVACT0_A::OUT + } + #[doc = "Checks if the value of the field is `SET`"] + #[inline(always)] + pub fn is_set(&self) -> bool { + **self == EVACT0_A::SET + } + #[doc = "Checks if the value of the field is `CLR`"] + #[inline(always)] + pub fn is_clr(&self) -> bool { + **self == EVACT0_A::CLR + } + #[doc = "Checks if the value of the field is `TGL`"] + #[inline(always)] + pub fn is_tgl(&self) -> bool { + **self == EVACT0_A::TGL + } +} +impl core::ops::Deref for EVACT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT0` writer - Port Event Action 0"] +pub struct EVACT0_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT0_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EVACT0_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Event output to pin"] + #[inline(always)] + pub fn out(self) -> &'a mut W { + self.variant(EVACT0_A::OUT) + } + #[doc = "Set output register of pin on event"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(EVACT0_A::SET) + } + #[doc = "Clear output register of pin on event"] + #[inline(always)] + pub fn clr(self) -> &'a mut W { + self.variant(EVACT0_A::CLR) + } + #[doc = "Toggle output register of pin on event"] + #[inline(always)] + pub fn tgl(self) -> &'a mut W { + self.variant(EVACT0_A::TGL) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 5)) | ((value as u32 & 0x03) << 5); + self.w + } +} +#[doc = "Field `PORTEI0` reader - Port Event Enable Input 0"] +pub struct PORTEI0_R(crate::FieldReader); +impl PORTEI0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PORTEI0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PORTEI0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PORTEI0` writer - Port Event Enable Input 0"] +pub struct PORTEI0_W<'a> { + w: &'a mut W, +} +impl<'a> PORTEI0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `PID1` reader - Port Event Pin Identifier 1"] +pub struct PID1_R(crate::FieldReader); +impl PID1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PID1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PID1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PID1` writer - Port Event Pin Identifier 1"] +pub struct PID1_W<'a> { + w: &'a mut W, +} +impl<'a> PID1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 8)) | ((value as u32 & 0x1f) << 8); + self.w + } +} +#[doc = "Field `EVACT1` reader - Port Event Action 1"] +pub struct EVACT1_R(crate::FieldReader); +impl EVACT1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVACT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT1` writer - Port Event Action 1"] +pub struct EVACT1_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 13)) | ((value as u32 & 0x03) << 13); + self.w + } +} +#[doc = "Field `PORTEI1` reader - Port Event Enable Input 1"] +pub struct PORTEI1_R(crate::FieldReader); +impl PORTEI1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PORTEI1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PORTEI1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PORTEI1` writer - Port Event Enable Input 1"] +pub struct PORTEI1_W<'a> { + w: &'a mut W, +} +impl<'a> PORTEI1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `PID2` reader - Port Event Pin Identifier 2"] +pub struct PID2_R(crate::FieldReader); +impl PID2_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PID2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PID2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PID2` writer - Port Event Pin Identifier 2"] +pub struct PID2_W<'a> { + w: &'a mut W, +} +impl<'a> PID2_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 16)) | ((value as u32 & 0x1f) << 16); + self.w + } +} +#[doc = "Field `EVACT2` reader - Port Event Action 2"] +pub struct EVACT2_R(crate::FieldReader); +impl EVACT2_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVACT2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT2` writer - Port Event Action 2"] +pub struct EVACT2_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT2_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 21)) | ((value as u32 & 0x03) << 21); + self.w + } +} +#[doc = "Field `PORTEI2` reader - Port Event Enable Input 2"] +pub struct PORTEI2_R(crate::FieldReader); +impl PORTEI2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PORTEI2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PORTEI2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PORTEI2` writer - Port Event Enable Input 2"] +pub struct PORTEI2_W<'a> { + w: &'a mut W, +} +impl<'a> PORTEI2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `PID3` reader - Port Event Pin Identifier 3"] +pub struct PID3_R(crate::FieldReader); +impl PID3_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PID3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PID3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PID3` writer - Port Event Pin Identifier 3"] +pub struct PID3_W<'a> { + w: &'a mut W, +} +impl<'a> PID3_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 24)) | ((value as u32 & 0x1f) << 24); + self.w + } +} +#[doc = "Field `EVACT3` reader - Port Event Action 3"] +pub struct EVACT3_R(crate::FieldReader); +impl EVACT3_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVACT3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT3` writer - Port Event Action 3"] +pub struct EVACT3_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT3_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 29)) | ((value as u32 & 0x03) << 29); + self.w + } +} +#[doc = "Field `PORTEI3` reader - Port Event Enable Input 3"] +pub struct PORTEI3_R(crate::FieldReader); +impl PORTEI3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PORTEI3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PORTEI3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PORTEI3` writer - Port Event Enable Input 3"] +pub struct PORTEI3_W<'a> { + w: &'a mut W, +} +impl<'a> PORTEI3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Port Event Pin Identifier 0"] + #[inline(always)] + pub fn pid0(&self) -> PID0_R { + PID0_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:6 - Port Event Action 0"] + #[inline(always)] + pub fn evact0(&self) -> EVACT0_R { + EVACT0_R::new(((self.bits >> 5) & 0x03) as u8) + } + #[doc = "Bit 7 - Port Event Enable Input 0"] + #[inline(always)] + pub fn portei0(&self) -> PORTEI0_R { + PORTEI0_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:12 - Port Event Pin Identifier 1"] + #[inline(always)] + pub fn pid1(&self) -> PID1_R { + PID1_R::new(((self.bits >> 8) & 0x1f) as u8) + } + #[doc = "Bits 13:14 - Port Event Action 1"] + #[inline(always)] + pub fn evact1(&self) -> EVACT1_R { + EVACT1_R::new(((self.bits >> 13) & 0x03) as u8) + } + #[doc = "Bit 15 - Port Event Enable Input 1"] + #[inline(always)] + pub fn portei1(&self) -> PORTEI1_R { + PORTEI1_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:20 - Port Event Pin Identifier 2"] + #[inline(always)] + pub fn pid2(&self) -> PID2_R { + PID2_R::new(((self.bits >> 16) & 0x1f) as u8) + } + #[doc = "Bits 21:22 - Port Event Action 2"] + #[inline(always)] + pub fn evact2(&self) -> EVACT2_R { + EVACT2_R::new(((self.bits >> 21) & 0x03) as u8) + } + #[doc = "Bit 23 - Port Event Enable Input 2"] + #[inline(always)] + pub fn portei2(&self) -> PORTEI2_R { + PORTEI2_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bits 24:28 - Port Event Pin Identifier 3"] + #[inline(always)] + pub fn pid3(&self) -> PID3_R { + PID3_R::new(((self.bits >> 24) & 0x1f) as u8) + } + #[doc = "Bits 29:30 - Port Event Action 3"] + #[inline(always)] + pub fn evact3(&self) -> EVACT3_R { + EVACT3_R::new(((self.bits >> 29) & 0x03) as u8) + } + #[doc = "Bit 31 - Port Event Enable Input 3"] + #[inline(always)] + pub fn portei3(&self) -> PORTEI3_R { + PORTEI3_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Port Event Pin Identifier 0"] + #[inline(always)] + pub fn pid0(&mut self) -> PID0_W { + PID0_W { w: self } + } + #[doc = "Bits 5:6 - Port Event Action 0"] + #[inline(always)] + pub fn evact0(&mut self) -> EVACT0_W { + EVACT0_W { w: self } + } + #[doc = "Bit 7 - Port Event Enable Input 0"] + #[inline(always)] + pub fn portei0(&mut self) -> PORTEI0_W { + PORTEI0_W { w: self } + } + #[doc = "Bits 8:12 - Port Event Pin Identifier 1"] + #[inline(always)] + pub fn pid1(&mut self) -> PID1_W { + PID1_W { w: self } + } + #[doc = "Bits 13:14 - Port Event Action 1"] + #[inline(always)] + pub fn evact1(&mut self) -> EVACT1_W { + EVACT1_W { w: self } + } + #[doc = "Bit 15 - Port Event Enable Input 1"] + #[inline(always)] + pub fn portei1(&mut self) -> PORTEI1_W { + PORTEI1_W { w: self } + } + #[doc = "Bits 16:20 - Port Event Pin Identifier 2"] + #[inline(always)] + pub fn pid2(&mut self) -> PID2_W { + PID2_W { w: self } + } + #[doc = "Bits 21:22 - Port Event Action 2"] + #[inline(always)] + pub fn evact2(&mut self) -> EVACT2_W { + EVACT2_W { w: self } + } + #[doc = "Bit 23 - Port Event Enable Input 2"] + #[inline(always)] + pub fn portei2(&mut self) -> PORTEI2_W { + PORTEI2_W { w: self } + } + #[doc = "Bits 24:28 - Port Event Pin Identifier 3"] + #[inline(always)] + pub fn pid3(&mut self) -> PID3_W { + PID3_W { w: self } + } + #[doc = "Bits 29:30 - Port Event Action 3"] + #[inline(always)] + pub fn evact3(&mut self) -> EVACT3_W { + EVACT3_W { w: self } + } + #[doc = "Bit 31 - Port Event Enable Input 3"] + #[inline(always)] + pub fn portei3(&mut self) -> PORTEI3_W { + PORTEI3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Input Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/port/group/in_.rs b/pac/atsamc21g/src/port/group/in_.rs new file mode 100644 index 000000000000..1c8e7396a83e --- /dev/null +++ b/pac/atsamc21g/src/port/group/in_.rs @@ -0,0 +1,31 @@ +#[doc = "Register `IN` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Data Input Value\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [in_](index.html) module"] +pub struct IN_SPEC; +impl crate::RegisterSpec for IN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [in_::R](R) reader structure"] +impl crate::Readable for IN_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets IN to value 0"] +impl crate::Resettable for IN_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/port/group/out.rs b/pac/atsamc21g/src/port/group/out.rs new file mode 100644 index 000000000000..092e8dbd8023 --- /dev/null +++ b/pac/atsamc21g/src/port/group/out.rs @@ -0,0 +1,64 @@ +#[doc = "Register `OUT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OUT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Output Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [out](index.html) module"] +pub struct OUT_SPEC; +impl crate::RegisterSpec for OUT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [out::R](R) reader structure"] +impl crate::Readable for OUT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [out::W](W) writer structure"] +impl crate::Writable for OUT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OUT to value 0"] +impl crate::Resettable for OUT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/port/group/outclr.rs b/pac/atsamc21g/src/port/group/outclr.rs new file mode 100644 index 000000000000..6e734396601f --- /dev/null +++ b/pac/atsamc21g/src/port/group/outclr.rs @@ -0,0 +1,64 @@ +#[doc = "Register `OUTCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OUTCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Output Value Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [outclr](index.html) module"] +pub struct OUTCLR_SPEC; +impl crate::RegisterSpec for OUTCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [outclr::R](R) reader structure"] +impl crate::Readable for OUTCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [outclr::W](W) writer structure"] +impl crate::Writable for OUTCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OUTCLR to value 0"] +impl crate::Resettable for OUTCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/port/group/outset.rs b/pac/atsamc21g/src/port/group/outset.rs new file mode 100644 index 000000000000..6d39122deb4b --- /dev/null +++ b/pac/atsamc21g/src/port/group/outset.rs @@ -0,0 +1,64 @@ +#[doc = "Register `OUTSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OUTSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Output Value Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [outset](index.html) module"] +pub struct OUTSET_SPEC; +impl crate::RegisterSpec for OUTSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [outset::R](R) reader structure"] +impl crate::Readable for OUTSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [outset::W](W) writer structure"] +impl crate::Writable for OUTSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OUTSET to value 0"] +impl crate::Resettable for OUTSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/port/group/outtgl.rs b/pac/atsamc21g/src/port/group/outtgl.rs new file mode 100644 index 000000000000..0f3d87d6476d --- /dev/null +++ b/pac/atsamc21g/src/port/group/outtgl.rs @@ -0,0 +1,64 @@ +#[doc = "Register `OUTTGL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OUTTGL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Output Value Toggle\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [outtgl](index.html) module"] +pub struct OUTTGL_SPEC; +impl crate::RegisterSpec for OUTTGL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [outtgl::R](R) reader structure"] +impl crate::Readable for OUTTGL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [outtgl::W](W) writer structure"] +impl crate::Writable for OUTTGL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OUTTGL to value 0"] +impl crate::Resettable for OUTTGL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/port/group/pincfg.rs b/pac/atsamc21g/src/port/group/pincfg.rs new file mode 100644 index 000000000000..920af6550361 --- /dev/null +++ b/pac/atsamc21g/src/port/group/pincfg.rs @@ -0,0 +1,255 @@ +#[doc = "Register `PINCFG[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PINCFG[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PMUXEN` reader - Select Peripheral Multiplexer"] +pub struct PMUXEN_R(crate::FieldReader); +impl PMUXEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PMUXEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PMUXEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PMUXEN` writer - Select Peripheral Multiplexer"] +pub struct PMUXEN_W<'a> { + w: &'a mut W, +} +impl<'a> PMUXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `INEN` reader - Input Enable"] +pub struct INEN_R(crate::FieldReader); +impl INEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INEN` writer - Input Enable"] +pub struct INEN_W<'a> { + w: &'a mut W, +} +impl<'a> INEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PULLEN` reader - Pull Enable"] +pub struct PULLEN_R(crate::FieldReader); +impl PULLEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PULLEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PULLEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PULLEN` writer - Pull Enable"] +pub struct PULLEN_W<'a> { + w: &'a mut W, +} +impl<'a> PULLEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `DRVSTR` reader - Output Driver Strength Selection"] +pub struct DRVSTR_R(crate::FieldReader); +impl DRVSTR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRVSTR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRVSTR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRVSTR` writer - Output Driver Strength Selection"] +pub struct DRVSTR_W<'a> { + w: &'a mut W, +} +impl<'a> DRVSTR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - Select Peripheral Multiplexer"] + #[inline(always)] + pub fn pmuxen(&self) -> PMUXEN_R { + PMUXEN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Input Enable"] + #[inline(always)] + pub fn inen(&self) -> INEN_R { + INEN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Pull Enable"] + #[inline(always)] + pub fn pullen(&self) -> PULLEN_R { + PULLEN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 6 - Output Driver Strength Selection"] + #[inline(always)] + pub fn drvstr(&self) -> DRVSTR_R { + DRVSTR_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Select Peripheral Multiplexer"] + #[inline(always)] + pub fn pmuxen(&mut self) -> PMUXEN_W { + PMUXEN_W { w: self } + } + #[doc = "Bit 1 - Input Enable"] + #[inline(always)] + pub fn inen(&mut self) -> INEN_W { + INEN_W { w: self } + } + #[doc = "Bit 2 - Pull Enable"] + #[inline(always)] + pub fn pullen(&mut self) -> PULLEN_W { + PULLEN_W { w: self } + } + #[doc = "Bit 6 - Output Driver Strength Selection"] + #[inline(always)] + pub fn drvstr(&mut self) -> DRVSTR_W { + DRVSTR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Pin Configuration n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pincfg](index.html) module"] +pub struct PINCFG_SPEC; +impl crate::RegisterSpec for PINCFG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [pincfg::R](R) reader structure"] +impl crate::Readable for PINCFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [pincfg::W](W) writer structure"] +impl crate::Writable for PINCFG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PINCFG[%s] +to value 0"] +impl crate::Resettable for PINCFG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/port/group/pmux.rs b/pac/atsamc21g/src/port/group/pmux.rs new file mode 100644 index 000000000000..79c991a99daf --- /dev/null +++ b/pac/atsamc21g/src/port/group/pmux.rs @@ -0,0 +1,141 @@ +#[doc = "Register `PMUX[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PMUX[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PMUXE` reader - Peripheral Multiplexing for Even-Numbered Pin"] +pub struct PMUXE_R(crate::FieldReader); +impl PMUXE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PMUXE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PMUXE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PMUXE` writer - Peripheral Multiplexing for Even-Numbered Pin"] +pub struct PMUXE_W<'a> { + w: &'a mut W, +} +impl<'a> PMUXE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +#[doc = "Field `PMUXO` reader - Peripheral Multiplexing for Odd-Numbered Pin"] +pub struct PMUXO_R(crate::FieldReader); +impl PMUXO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PMUXO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PMUXO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PMUXO` writer - Peripheral Multiplexing for Odd-Numbered Pin"] +pub struct PMUXO_W<'a> { + w: &'a mut W, +} +impl<'a> PMUXO_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 4)) | ((value as u8 & 0x0f) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Peripheral Multiplexing for Even-Numbered Pin"] + #[inline(always)] + pub fn pmuxe(&self) -> PMUXE_R { + PMUXE_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Peripheral Multiplexing for Odd-Numbered Pin"] + #[inline(always)] + pub fn pmuxo(&self) -> PMUXO_R { + PMUXO_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Peripheral Multiplexing for Even-Numbered Pin"] + #[inline(always)] + pub fn pmuxe(&mut self) -> PMUXE_W { + PMUXE_W { w: self } + } + #[doc = "Bits 4:7 - Peripheral Multiplexing for Odd-Numbered Pin"] + #[inline(always)] + pub fn pmuxo(&mut self) -> PMUXO_W { + PMUXO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Peripheral Multiplexing n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pmux](index.html) module"] +pub struct PMUX_SPEC; +impl crate::RegisterSpec for PMUX_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [pmux::R](R) reader structure"] +impl crate::Readable for PMUX_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [pmux::W](W) writer structure"] +impl crate::Writable for PMUX_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PMUX[%s] +to value 0"] +impl crate::Resettable for PMUX_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/port/group/wrconfig.rs b/pac/atsamc21g/src/port/group/wrconfig.rs new file mode 100644 index 000000000000..c87e4f174728 --- /dev/null +++ b/pac/atsamc21g/src/port/group/wrconfig.rs @@ -0,0 +1,268 @@ +#[doc = "Register `WRCONFIG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PINMASK` writer - Pin Mask for Multiple Pin Configuration"] +pub struct PINMASK_W<'a> { + w: &'a mut W, +} +impl<'a> PINMASK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +#[doc = "Field `PMUXEN` writer - Select Peripheral Multiplexer"] +pub struct PMUXEN_W<'a> { + w: &'a mut W, +} +impl<'a> PMUXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `INEN` writer - Input Enable"] +pub struct INEN_W<'a> { + w: &'a mut W, +} +impl<'a> INEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `PULLEN` writer - Pull Enable"] +pub struct PULLEN_W<'a> { + w: &'a mut W, +} +impl<'a> PULLEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `DRVSTR` writer - Output Driver Strength Selection"] +pub struct DRVSTR_W<'a> { + w: &'a mut W, +} +impl<'a> DRVSTR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `PMUX` writer - Peripheral Multiplexing Template"] +pub struct PMUX_W<'a> { + w: &'a mut W, +} +impl<'a> PMUX_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Field `WRPMUX` writer - Write PMUX Registers"] +pub struct WRPMUX_W<'a> { + w: &'a mut W, +} +impl<'a> WRPMUX_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Field `WRPINCFG` writer - Write PINCFG Registers"] +pub struct WRPINCFG_W<'a> { + w: &'a mut W, +} +impl<'a> WRPINCFG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +#[doc = "Field `HWSEL` writer - Half-Word Select"] +pub struct HWSEL_W<'a> { + w: &'a mut W, +} +impl<'a> HWSEL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl W { + #[doc = "Bits 0:15 - Pin Mask for Multiple Pin Configuration"] + #[inline(always)] + pub fn pinmask(&mut self) -> PINMASK_W { + PINMASK_W { w: self } + } + #[doc = "Bit 16 - Select Peripheral Multiplexer"] + #[inline(always)] + pub fn pmuxen(&mut self) -> PMUXEN_W { + PMUXEN_W { w: self } + } + #[doc = "Bit 17 - Input Enable"] + #[inline(always)] + pub fn inen(&mut self) -> INEN_W { + INEN_W { w: self } + } + #[doc = "Bit 18 - Pull Enable"] + #[inline(always)] + pub fn pullen(&mut self) -> PULLEN_W { + PULLEN_W { w: self } + } + #[doc = "Bit 22 - Output Driver Strength Selection"] + #[inline(always)] + pub fn drvstr(&mut self) -> DRVSTR_W { + DRVSTR_W { w: self } + } + #[doc = "Bits 24:27 - Peripheral Multiplexing Template"] + #[inline(always)] + pub fn pmux(&mut self) -> PMUX_W { + PMUX_W { w: self } + } + #[doc = "Bit 28 - Write PMUX Registers"] + #[inline(always)] + pub fn wrpmux(&mut self) -> WRPMUX_W { + WRPMUX_W { w: self } + } + #[doc = "Bit 30 - Write PINCFG Registers"] + #[inline(always)] + pub fn wrpincfg(&mut self) -> WRPINCFG_W { + WRPINCFG_W { w: self } + } + #[doc = "Bit 31 - Half-Word Select"] + #[inline(always)] + pub fn hwsel(&mut self) -> HWSEL_W { + HWSEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Write Configuration\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wrconfig](index.html) module"] +pub struct WRCONFIG_SPEC; +impl crate::RegisterSpec for WRCONFIG_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [wrconfig::W](W) writer structure"] +impl crate::Writable for WRCONFIG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WRCONFIG to value 0"] +impl crate::Resettable for WRCONFIG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/rstc.rs b/pac/atsamc21g/src/rstc.rs new file mode 100644 index 000000000000..327b511df28a --- /dev/null +++ b/pac/atsamc21g/src/rstc.rs @@ -0,0 +1,10 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Reset Cause"] + pub rcause: crate::Reg, +} +#[doc = "RCAUSE register accessor: an alias for `Reg`"] +pub type RCAUSE = crate::Reg; +#[doc = "Reset Cause"] +pub mod rcause; diff --git a/pac/atsamc21g/src/rstc/rcause.rs b/pac/atsamc21g/src/rstc/rcause.rs new file mode 100644 index 000000000000..3dc13496e74b --- /dev/null +++ b/pac/atsamc21g/src/rstc/rcause.rs @@ -0,0 +1,153 @@ +#[doc = "Register `RCAUSE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `POR` reader - Power On Reset"] +pub struct POR_R(crate::FieldReader); +impl POR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + POR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for POR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODCORE` reader - Brown Out CORE Detector Reset"] +pub struct BODCORE_R(crate::FieldReader); +impl BODCORE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODCORE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODCORE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODVDD` reader - Brown Out VDD Detector Reset"] +pub struct BODVDD_R(crate::FieldReader); +impl BODVDD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODVDD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODVDD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXT` reader - External Reset"] +pub struct EXT_R(crate::FieldReader); +impl EXT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WDT` reader - Watchdog Reset"] +pub struct WDT_R(crate::FieldReader); +impl WDT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WDT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WDT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYST` reader - System Reset Request"] +pub struct SYST_R(crate::FieldReader); +impl SYST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Power On Reset"] + #[inline(always)] + pub fn por(&self) -> POR_R { + POR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Brown Out CORE Detector Reset"] + #[inline(always)] + pub fn bodcore(&self) -> BODCORE_R { + BODCORE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Brown Out VDD Detector Reset"] + #[inline(always)] + pub fn bodvdd(&self) -> BODVDD_R { + BODVDD_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 4 - External Reset"] + #[inline(always)] + pub fn ext(&self) -> EXT_R { + EXT_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Watchdog Reset"] + #[inline(always)] + pub fn wdt(&self) -> WDT_R { + WDT_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - System Reset Request"] + #[inline(always)] + pub fn syst(&self) -> SYST_R { + SYST_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +#[doc = "Reset Cause\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rcause](index.html) module"] +pub struct RCAUSE_SPEC; +impl crate::RegisterSpec for RCAUSE_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [rcause::R](R) reader structure"] +impl crate::Readable for RCAUSE_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets RCAUSE to value 0"] +impl crate::Resettable for RCAUSE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/rtc.rs b/pac/atsamc21g/src/rtc.rs new file mode 100644 index 000000000000..62f424cb1a8e --- /dev/null +++ b/pac/atsamc21g/src/rtc.rs @@ -0,0 +1,120 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved_0_mode0: [u8; 0x25], +} +impl RegisterBlock { + #[doc = "0x00..0x25 - Clock/Calendar with Alarm"] + #[inline(always)] + pub fn mode2(&self) -> &MODE2 { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const MODE2) } + } + #[doc = "0x00..0x24 - 16-bit Counter with Two 16-bit Compares"] + #[inline(always)] + pub fn mode1(&self) -> &MODE1 { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const MODE1) } + } + #[doc = "0x00..0x24 - 32-bit Counter with Single 32-bit Compare"] + #[inline(always)] + pub fn mode0(&self) -> &MODE0 { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const MODE0) } + } +} +#[doc = r"Register block"] +#[repr(C)] +pub struct MODE0 { + #[doc = "0x00 - MODE0 Control A"] + pub ctrla: crate::Reg, + _reserved1: [u8; 0x02], + #[doc = "0x04 - MODE0 Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x08 - MODE0 Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x0a - MODE0 Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x0c - MODE0 Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x0e - Debug Control"] + pub dbgctrl: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x10 - MODE0 Synchronization Busy Status"] + pub syncbusy: crate::Reg, + #[doc = "0x14 - Frequency Correction"] + pub freqcorr: crate::Reg, + _reserved8: [u8; 0x03], + #[doc = "0x18 - MODE0 Counter Value"] + pub count: crate::Reg, + _reserved9: [u8; 0x04], + #[doc = "0x20 - MODE0 Compare n Value"] + pub comp: crate::Reg, +} +#[doc = r"Register block"] +#[doc = "32-bit Counter with Single 32-bit Compare"] +pub mod mode0; +#[doc = r"Register block"] +#[repr(C)] +pub struct MODE1 { + #[doc = "0x00 - MODE1 Control A"] + pub ctrla: crate::Reg, + _reserved1: [u8; 0x02], + #[doc = "0x04 - MODE1 Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x08 - MODE1 Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x0a - MODE1 Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x0c - MODE1 Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x0e - Debug Control"] + pub dbgctrl: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x10 - MODE1 Synchronization Busy Status"] + pub syncbusy: crate::Reg, + #[doc = "0x14 - Frequency Correction"] + pub freqcorr: crate::Reg, + _reserved8: [u8; 0x03], + #[doc = "0x18 - MODE1 Counter Value"] + pub count: crate::Reg, + _reserved9: [u8; 0x02], + #[doc = "0x1c - MODE1 Counter Period"] + pub per: crate::Reg, + _reserved10: [u8; 0x02], + #[doc = "0x20 - MODE1 Compare n Value"] + pub comp: [crate::Reg; 2], +} +#[doc = r"Register block"] +#[doc = "16-bit Counter with Two 16-bit Compares"] +pub mod mode1; +#[doc = r"Register block"] +#[repr(C)] +pub struct MODE2 { + #[doc = "0x00 - MODE2 Control A"] + pub ctrla: crate::Reg, + _reserved1: [u8; 0x02], + #[doc = "0x04 - MODE2 Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x08 - MODE2 Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x0a - MODE2 Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x0c - MODE2 Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x0e - Debug Control"] + pub dbgctrl: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x10 - MODE2 Synchronization Busy Status"] + pub syncbusy: crate::Reg, + #[doc = "0x14 - Frequency Correction"] + pub freqcorr: crate::Reg, + _reserved8: [u8; 0x03], + #[doc = "0x18 - MODE2 Clock Value"] + pub clock: crate::Reg, + _reserved9: [u8; 0x04], + #[doc = "0x20 - MODE2_ALARM Alarm n Value"] + pub alarm: crate::Reg, + #[doc = "0x24 - MODE2_ALARM Alarm n Mask"] + pub mask: crate::Reg, +} +#[doc = r"Register block"] +#[doc = "Clock/Calendar with Alarm"] +pub mod mode2; diff --git a/pac/atsamc21g/src/rtc/mode0.rs b/pac/atsamc21g/src/rtc/mode0.rs new file mode 100644 index 000000000000..9ce5c3808169 --- /dev/null +++ b/pac/atsamc21g/src/rtc/mode0.rs @@ -0,0 +1,40 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "MODE0 Control A"] +pub mod ctrla; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "MODE0 Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "MODE0 Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "MODE0 Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "MODE0 Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "MODE0 Synchronization Busy Status"] +pub mod syncbusy; +#[doc = "FREQCORR register accessor: an alias for `Reg`"] +pub type FREQCORR = crate::Reg; +#[doc = "Frequency Correction"] +pub mod freqcorr; +#[doc = "COUNT register accessor: an alias for `Reg`"] +pub type COUNT = crate::Reg; +#[doc = "MODE0 Counter Value"] +pub mod count; +#[doc = "COMP register accessor: an alias for `Reg`"] +pub type COMP = crate::Reg; +#[doc = "MODE0 Compare n Value"] +pub mod comp; diff --git a/pac/atsamc21g/src/rtc/mode0/comp.rs b/pac/atsamc21g/src/rtc/mode0/comp.rs new file mode 100644 index 000000000000..a909d3cea2d3 --- /dev/null +++ b/pac/atsamc21g/src/rtc/mode0/comp.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COMP` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COMP` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COMP` reader - Compare Value"] +pub struct COMP_R(crate::FieldReader); +impl COMP_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COMP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP` writer - Compare Value"] +pub struct COMP_W<'a> { + w: &'a mut W, +} +impl<'a> COMP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Compare Value"] + #[inline(always)] + pub fn comp(&self) -> COMP_R { + COMP_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Compare Value"] + #[inline(always)] + pub fn comp(&mut self) -> COMP_W { + COMP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE0 Compare n Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [comp](index.html) module"] +pub struct COMP_SPEC; +impl crate::RegisterSpec for COMP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [comp::R](R) reader structure"] +impl crate::Readable for COMP_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [comp::W](W) writer structure"] +impl crate::Writable for COMP_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COMP to value 0"] +impl crate::Resettable for COMP_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/rtc/mode0/count.rs b/pac/atsamc21g/src/rtc/mode0/count.rs new file mode 100644 index 000000000000..cf880b5e77a6 --- /dev/null +++ b/pac/atsamc21g/src/rtc/mode0/count.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE0 Counter Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count](index.html) module"] +pub struct COUNT_SPEC; +impl crate::RegisterSpec for COUNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [count::R](R) reader structure"] +impl crate::Readable for COUNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count::W](W) writer structure"] +impl crate::Writable for COUNT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT to value 0"] +impl crate::Resettable for COUNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/rtc/mode0/ctrla.rs b/pac/atsamc21g/src/rtc/mode0/ctrla.rs new file mode 100644 index 000000000000..423877bd087d --- /dev/null +++ b/pac/atsamc21g/src/rtc/mode0/ctrla.rs @@ -0,0 +1,569 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: Mode 0: 32-bit Counter"] + COUNT32 = 0, + #[doc = "1: Mode 1: 16-bit Counter"] + COUNT16 = 1, + #[doc = "2: Mode 2: Clock/Calendar"] + CLOCK = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::COUNT32), + 1 => Some(MODE_A::COUNT16), + 2 => Some(MODE_A::CLOCK), + _ => None, + } + } + #[doc = "Checks if the value of the field is `COUNT32`"] + #[inline(always)] + pub fn is_count32(&self) -> bool { + **self == MODE_A::COUNT32 + } + #[doc = "Checks if the value of the field is `COUNT16`"] + #[inline(always)] + pub fn is_count16(&self) -> bool { + **self == MODE_A::COUNT16 + } + #[doc = "Checks if the value of the field is `CLOCK`"] + #[inline(always)] + pub fn is_clock(&self) -> bool { + **self == MODE_A::CLOCK + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Mode 0: 32-bit Counter"] + #[inline(always)] + pub fn count32(self) -> &'a mut W { + self.variant(MODE_A::COUNT32) + } + #[doc = "Mode 1: 16-bit Counter"] + #[inline(always)] + pub fn count16(self) -> &'a mut W { + self.variant(MODE_A::COUNT16) + } + #[doc = "Mode 2: Clock/Calendar"] + #[inline(always)] + pub fn clock(self) -> &'a mut W { + self.variant(MODE_A::CLOCK) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u16 & 0x03) << 2); + self.w + } +} +#[doc = "Field `MATCHCLR` reader - Clear on Match"] +pub struct MATCHCLR_R(crate::FieldReader); +impl MATCHCLR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MATCHCLR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MATCHCLR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MATCHCLR` writer - Clear on Match"] +pub struct MATCHCLR_W<'a> { + w: &'a mut W, +} +impl<'a> MATCHCLR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: CLK_RTC_CNT = GCLK_RTC/1"] + OFF = 0, + #[doc = "1: CLK_RTC_CNT = GCLK_RTC/1"] + DIV1 = 1, + #[doc = "2: CLK_RTC_CNT = GCLK_RTC/2"] + DIV2 = 2, + #[doc = "3: CLK_RTC_CNT = GCLK_RTC/4"] + DIV4 = 3, + #[doc = "4: CLK_RTC_CNT = GCLK_RTC/8"] + DIV8 = 4, + #[doc = "5: CLK_RTC_CNT = GCLK_RTC/16"] + DIV16 = 5, + #[doc = "6: CLK_RTC_CNT = GCLK_RTC/32"] + DIV32 = 6, + #[doc = "7: CLK_RTC_CNT = GCLK_RTC/64"] + DIV64 = 7, + #[doc = "8: CLK_RTC_CNT = GCLK_RTC/128"] + DIV128 = 8, + #[doc = "9: CLK_RTC_CNT = GCLK_RTC/256"] + DIV256 = 9, + #[doc = "10: CLK_RTC_CNT = GCLK_RTC/512"] + DIV512 = 10, + #[doc = "11: CLK_RTC_CNT = GCLK_RTC/1024"] + DIV1024 = 11, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCALER_A::OFF), + 1 => Some(PRESCALER_A::DIV1), + 2 => Some(PRESCALER_A::DIV2), + 3 => Some(PRESCALER_A::DIV4), + 4 => Some(PRESCALER_A::DIV8), + 5 => Some(PRESCALER_A::DIV16), + 6 => Some(PRESCALER_A::DIV32), + 7 => Some(PRESCALER_A::DIV64), + 8 => Some(PRESCALER_A::DIV128), + 9 => Some(PRESCALER_A::DIV256), + 10 => Some(PRESCALER_A::DIV512), + 11 => Some(PRESCALER_A::DIV1024), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == PRESCALER_A::OFF + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == PRESCALER_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == PRESCALER_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == PRESCALER_A::DIV128 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV512`"] + #[inline(always)] + pub fn is_div512(&self) -> bool { + **self == PRESCALER_A::DIV512 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PRESCALER_A::DIV1024 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(PRESCALER_A::OFF) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV32) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV128) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/512"] + #[inline(always)] + pub fn div512(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV512) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 8)) | ((value as u16 & 0x0f) << 8); + self.w + } +} +#[doc = "Field `COUNTSYNC` reader - Count Read Synchronization Enable"] +pub struct COUNTSYNC_R(crate::FieldReader); +impl COUNTSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNTSYNC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNTSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNTSYNC` writer - Count Read Synchronization Enable"] +pub struct COUNTSYNC_W<'a> { + w: &'a mut W, +} +impl<'a> COUNTSYNC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:3 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bit 7 - Clear on Match"] + #[inline(always)] + pub fn matchclr(&self) -> MATCHCLR_R { + MATCHCLR_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:11 - Prescaler"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 15 - Count Read Synchronization Enable"] + #[inline(always)] + pub fn countsync(&self) -> COUNTSYNC_R { + COUNTSYNC_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:3 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 7 - Clear on Match"] + #[inline(always)] + pub fn matchclr(&mut self) -> MATCHCLR_W { + MATCHCLR_W { w: self } + } + #[doc = "Bits 8:11 - Prescaler"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Bit 15 - Count Read Synchronization Enable"] + #[inline(always)] + pub fn countsync(&mut self) -> COUNTSYNC_W { + COUNTSYNC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE0 Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/rtc/mode0/dbgctrl.rs b/pac/atsamc21g/src/rtc/mode0/dbgctrl.rs new file mode 100644 index 000000000000..0383e70d0429 --- /dev/null +++ b/pac/atsamc21g/src/rtc/mode0/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Run During Debug"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Run During Debug"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/rtc/mode0/evctrl.rs b/pac/atsamc21g/src/rtc/mode0/evctrl.rs new file mode 100644 index 000000000000..c73647759dbe --- /dev/null +++ b/pac/atsamc21g/src/rtc/mode0/evctrl.rs @@ -0,0 +1,536 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PEREO0` reader - Periodic Interval 0 Event Output Enable"] +pub struct PEREO0_R(crate::FieldReader); +impl PEREO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO0` writer - Periodic Interval 0 Event Output Enable"] +pub struct PEREO0_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `PEREO1` reader - Periodic Interval 1 Event Output Enable"] +pub struct PEREO1_R(crate::FieldReader); +impl PEREO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO1` writer - Periodic Interval 1 Event Output Enable"] +pub struct PEREO1_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PEREO2` reader - Periodic Interval 2 Event Output Enable"] +pub struct PEREO2_R(crate::FieldReader); +impl PEREO2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO2` writer - Periodic Interval 2 Event Output Enable"] +pub struct PEREO2_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PEREO3` reader - Periodic Interval 3 Event Output Enable"] +pub struct PEREO3_R(crate::FieldReader); +impl PEREO3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO3` writer - Periodic Interval 3 Event Output Enable"] +pub struct PEREO3_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PEREO4` reader - Periodic Interval 4 Event Output Enable"] +pub struct PEREO4_R(crate::FieldReader); +impl PEREO4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO4` writer - Periodic Interval 4 Event Output Enable"] +pub struct PEREO4_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PEREO5` reader - Periodic Interval 5 Event Output Enable"] +pub struct PEREO5_R(crate::FieldReader); +impl PEREO5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO5` writer - Periodic Interval 5 Event Output Enable"] +pub struct PEREO5_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PEREO6` reader - Periodic Interval 6 Event Output Enable"] +pub struct PEREO6_R(crate::FieldReader); +impl PEREO6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO6` writer - Periodic Interval 6 Event Output Enable"] +pub struct PEREO6_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PEREO7` reader - Periodic Interval 7 Event Output Enable"] +pub struct PEREO7_R(crate::FieldReader); +impl PEREO7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO7` writer - Periodic Interval 7 Event Output Enable"] +pub struct PEREO7_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CMPEO0` reader - Compare 0 Event Output Enable"] +pub struct CMPEO0_R(crate::FieldReader); +impl CMPEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMPEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMPEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMPEO0` writer - Compare 0 Event Output Enable"] +pub struct CMPEO0_W<'a> { + w: &'a mut W, +} +impl<'a> CMPEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `OVFEO` reader - Overflow Event Output Enable"] +pub struct OVFEO_R(crate::FieldReader); +impl OVFEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVFEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVFEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVFEO` writer - Overflow Event Output Enable"] +pub struct OVFEO_W<'a> { + w: &'a mut W, +} +impl<'a> OVFEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Event Output Enable"] + #[inline(always)] + pub fn pereo0(&self) -> PEREO0_R { + PEREO0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Event Output Enable"] + #[inline(always)] + pub fn pereo1(&self) -> PEREO1_R { + PEREO1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Event Output Enable"] + #[inline(always)] + pub fn pereo2(&self) -> PEREO2_R { + PEREO2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Event Output Enable"] + #[inline(always)] + pub fn pereo3(&self) -> PEREO3_R { + PEREO3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Event Output Enable"] + #[inline(always)] + pub fn pereo4(&self) -> PEREO4_R { + PEREO4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Event Output Enable"] + #[inline(always)] + pub fn pereo5(&self) -> PEREO5_R { + PEREO5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Event Output Enable"] + #[inline(always)] + pub fn pereo6(&self) -> PEREO6_R { + PEREO6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Event Output Enable"] + #[inline(always)] + pub fn pereo7(&self) -> PEREO7_R { + PEREO7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Compare 0 Event Output Enable"] + #[inline(always)] + pub fn cmpeo0(&self) -> CMPEO0_R { + CMPEO0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&self) -> OVFEO_R { + OVFEO_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Event Output Enable"] + #[inline(always)] + pub fn pereo0(&mut self) -> PEREO0_W { + PEREO0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1 Event Output Enable"] + #[inline(always)] + pub fn pereo1(&mut self) -> PEREO1_W { + PEREO1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2 Event Output Enable"] + #[inline(always)] + pub fn pereo2(&mut self) -> PEREO2_W { + PEREO2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3 Event Output Enable"] + #[inline(always)] + pub fn pereo3(&mut self) -> PEREO3_W { + PEREO3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4 Event Output Enable"] + #[inline(always)] + pub fn pereo4(&mut self) -> PEREO4_W { + PEREO4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5 Event Output Enable"] + #[inline(always)] + pub fn pereo5(&mut self) -> PEREO5_W { + PEREO5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6 Event Output Enable"] + #[inline(always)] + pub fn pereo6(&mut self) -> PEREO6_W { + PEREO6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7 Event Output Enable"] + #[inline(always)] + pub fn pereo7(&mut self) -> PEREO7_W { + PEREO7_W { w: self } + } + #[doc = "Bit 8 - Compare 0 Event Output Enable"] + #[inline(always)] + pub fn cmpeo0(&mut self) -> CMPEO0_W { + CMPEO0_W { w: self } + } + #[doc = "Bit 15 - Overflow Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&mut self) -> OVFEO_W { + OVFEO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE0 Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/rtc/mode0/freqcorr.rs b/pac/atsamc21g/src/rtc/mode0/freqcorr.rs new file mode 100644 index 000000000000..043ba6f88eb2 --- /dev/null +++ b/pac/atsamc21g/src/rtc/mode0/freqcorr.rs @@ -0,0 +1,150 @@ +#[doc = "Register `FREQCORR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FREQCORR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `VALUE` reader - Correction Value"] +pub struct VALUE_R(crate::FieldReader); +impl VALUE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + VALUE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VALUE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VALUE` writer - Correction Value"] +pub struct VALUE_W<'a> { + w: &'a mut W, +} +impl<'a> VALUE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x7f) | (value as u8 & 0x7f); + self.w + } +} +#[doc = "Field `SIGN` reader - Correction Sign"] +pub struct SIGN_R(crate::FieldReader); +impl SIGN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SIGN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SIGN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SIGN` writer - Correction Sign"] +pub struct SIGN_W<'a> { + w: &'a mut W, +} +impl<'a> SIGN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bits 0:6 - Correction Value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bit 7 - Correction Sign"] + #[inline(always)] + pub fn sign(&self) -> SIGN_R { + SIGN_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:6 - Correction Value"] + #[inline(always)] + pub fn value(&mut self) -> VALUE_W { + VALUE_W { w: self } + } + #[doc = "Bit 7 - Correction Sign"] + #[inline(always)] + pub fn sign(&mut self) -> SIGN_W { + SIGN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Frequency Correction\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [freqcorr](index.html) module"] +pub struct FREQCORR_SPEC; +impl crate::RegisterSpec for FREQCORR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [freqcorr::R](R) reader structure"] +impl crate::Readable for FREQCORR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [freqcorr::W](W) writer structure"] +impl crate::Writable for FREQCORR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets FREQCORR to value 0"] +impl crate::Resettable for FREQCORR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/rtc/mode0/intenclr.rs b/pac/atsamc21g/src/rtc/mode0/intenclr.rs new file mode 100644 index 000000000000..8be5e2c3920b --- /dev/null +++ b/pac/atsamc21g/src/rtc/mode0/intenclr.rs @@ -0,0 +1,536 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER0` reader - Periodic Interval 0 Interrupt Enable"] +pub struct PER0_R(crate::FieldReader); +impl PER0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER0` writer - Periodic Interval 0 Interrupt Enable"] +pub struct PER0_W<'a> { + w: &'a mut W, +} +impl<'a> PER0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PER1` reader - Periodic Interval 1 Interrupt Enable"] +pub struct PER1_R(crate::FieldReader); +impl PER1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER1` writer - Periodic Interval 1 Interrupt Enable"] +pub struct PER1_W<'a> { + w: &'a mut W, +} +impl<'a> PER1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PER2` reader - Periodic Interval 2 Interrupt Enable"] +pub struct PER2_R(crate::FieldReader); +impl PER2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER2` writer - Periodic Interval 2 Interrupt Enable"] +pub struct PER2_W<'a> { + w: &'a mut W, +} +impl<'a> PER2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PER3` reader - Periodic Interval 3 Interrupt Enable"] +pub struct PER3_R(crate::FieldReader); +impl PER3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER3` writer - Periodic Interval 3 Interrupt Enable"] +pub struct PER3_W<'a> { + w: &'a mut W, +} +impl<'a> PER3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PER4` reader - Periodic Interval 4 Interrupt Enable"] +pub struct PER4_R(crate::FieldReader); +impl PER4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER4` writer - Periodic Interval 4 Interrupt Enable"] +pub struct PER4_W<'a> { + w: &'a mut W, +} +impl<'a> PER4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PER5` reader - Periodic Interval 5 Interrupt Enable"] +pub struct PER5_R(crate::FieldReader); +impl PER5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER5` writer - Periodic Interval 5 Interrupt Enable"] +pub struct PER5_W<'a> { + w: &'a mut W, +} +impl<'a> PER5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PER6` reader - Periodic Interval 6 Interrupt Enable"] +pub struct PER6_R(crate::FieldReader); +impl PER6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER6` writer - Periodic Interval 6 Interrupt Enable"] +pub struct PER6_W<'a> { + w: &'a mut W, +} +impl<'a> PER6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PER7` reader - Periodic Interval 7 Interrupt Enable"] +pub struct PER7_R(crate::FieldReader); +impl PER7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER7` writer - Periodic Interval 7 Interrupt Enable"] +pub struct PER7_W<'a> { + w: &'a mut W, +} +impl<'a> PER7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CMP0` reader - Compare 0 Interrupt Enable"] +pub struct CMP0_R(crate::FieldReader); +impl CMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP0` writer - Compare 0 Interrupt Enable"] +pub struct CMP0_W<'a> { + w: &'a mut W, +} +impl<'a> CMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + pub fn per0(&self) -> PER0_R { + PER0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + pub fn per1(&self) -> PER1_R { + PER1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + pub fn per2(&self) -> PER2_R { + PER2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + pub fn per3(&self) -> PER3_R { + PER3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + pub fn per4(&self) -> PER4_R { + PER4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + pub fn per5(&self) -> PER5_R { + PER5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + pub fn per6(&self) -> PER6_R { + PER6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + pub fn per7(&self) -> PER7_R { + PER7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&self) -> CMP0_R { + CMP0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + pub fn per0(&mut self) -> PER0_W { + PER0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + pub fn per1(&mut self) -> PER1_W { + PER1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + pub fn per2(&mut self) -> PER2_W { + PER2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + pub fn per3(&mut self) -> PER3_W { + PER3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + pub fn per4(&mut self) -> PER4_W { + PER4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + pub fn per5(&mut self) -> PER5_W { + PER5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + pub fn per6(&mut self) -> PER6_W { + PER6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + pub fn per7(&mut self) -> PER7_W { + PER7_W { w: self } + } + #[doc = "Bit 8 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&mut self) -> CMP0_W { + CMP0_W { w: self } + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE0 Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/rtc/mode0/intenset.rs b/pac/atsamc21g/src/rtc/mode0/intenset.rs new file mode 100644 index 000000000000..7228f5d486f5 --- /dev/null +++ b/pac/atsamc21g/src/rtc/mode0/intenset.rs @@ -0,0 +1,536 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER0` reader - Periodic Interval 0 Interrupt Enable"] +pub struct PER0_R(crate::FieldReader); +impl PER0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER0` writer - Periodic Interval 0 Interrupt Enable"] +pub struct PER0_W<'a> { + w: &'a mut W, +} +impl<'a> PER0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PER1` reader - Periodic Interval 1 Interrupt Enable"] +pub struct PER1_R(crate::FieldReader); +impl PER1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER1` writer - Periodic Interval 1 Interrupt Enable"] +pub struct PER1_W<'a> { + w: &'a mut W, +} +impl<'a> PER1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PER2` reader - Periodic Interval 2 Interrupt Enable"] +pub struct PER2_R(crate::FieldReader); +impl PER2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER2` writer - Periodic Interval 2 Interrupt Enable"] +pub struct PER2_W<'a> { + w: &'a mut W, +} +impl<'a> PER2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PER3` reader - Periodic Interval 3 Interrupt Enable"] +pub struct PER3_R(crate::FieldReader); +impl PER3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER3` writer - Periodic Interval 3 Interrupt Enable"] +pub struct PER3_W<'a> { + w: &'a mut W, +} +impl<'a> PER3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PER4` reader - Periodic Interval 4 Interrupt Enable"] +pub struct PER4_R(crate::FieldReader); +impl PER4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER4` writer - Periodic Interval 4 Interrupt Enable"] +pub struct PER4_W<'a> { + w: &'a mut W, +} +impl<'a> PER4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PER5` reader - Periodic Interval 5 Interrupt Enable"] +pub struct PER5_R(crate::FieldReader); +impl PER5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER5` writer - Periodic Interval 5 Interrupt Enable"] +pub struct PER5_W<'a> { + w: &'a mut W, +} +impl<'a> PER5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PER6` reader - Periodic Interval 6 Interrupt Enable"] +pub struct PER6_R(crate::FieldReader); +impl PER6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER6` writer - Periodic Interval 6 Interrupt Enable"] +pub struct PER6_W<'a> { + w: &'a mut W, +} +impl<'a> PER6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PER7` reader - Periodic Interval 7 Interrupt Enable"] +pub struct PER7_R(crate::FieldReader); +impl PER7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER7` writer - Periodic Interval 7 Interrupt Enable"] +pub struct PER7_W<'a> { + w: &'a mut W, +} +impl<'a> PER7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CMP0` reader - Compare 0 Interrupt Enable"] +pub struct CMP0_R(crate::FieldReader); +impl CMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP0` writer - Compare 0 Interrupt Enable"] +pub struct CMP0_W<'a> { + w: &'a mut W, +} +impl<'a> CMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + pub fn per0(&self) -> PER0_R { + PER0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + pub fn per1(&self) -> PER1_R { + PER1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + pub fn per2(&self) -> PER2_R { + PER2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + pub fn per3(&self) -> PER3_R { + PER3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + pub fn per4(&self) -> PER4_R { + PER4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + pub fn per5(&self) -> PER5_R { + PER5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + pub fn per6(&self) -> PER6_R { + PER6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + pub fn per7(&self) -> PER7_R { + PER7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&self) -> CMP0_R { + CMP0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + pub fn per0(&mut self) -> PER0_W { + PER0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + pub fn per1(&mut self) -> PER1_W { + PER1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + pub fn per2(&mut self) -> PER2_W { + PER2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + pub fn per3(&mut self) -> PER3_W { + PER3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + pub fn per4(&mut self) -> PER4_W { + PER4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + pub fn per5(&mut self) -> PER5_W { + PER5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + pub fn per6(&mut self) -> PER6_W { + PER6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + pub fn per7(&mut self) -> PER7_W { + PER7_W { w: self } + } + #[doc = "Bit 8 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&mut self) -> CMP0_W { + CMP0_W { w: self } + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE0 Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/rtc/mode0/intflag.rs b/pac/atsamc21g/src/rtc/mode0/intflag.rs new file mode 100644 index 000000000000..f2dccdb04aa4 --- /dev/null +++ b/pac/atsamc21g/src/rtc/mode0/intflag.rs @@ -0,0 +1,536 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER0` reader - Periodic Interval 0"] +pub struct PER0_R(crate::FieldReader); +impl PER0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER0` writer - Periodic Interval 0"] +pub struct PER0_W<'a> { + w: &'a mut W, +} +impl<'a> PER0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PER1` reader - Periodic Interval 1"] +pub struct PER1_R(crate::FieldReader); +impl PER1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER1` writer - Periodic Interval 1"] +pub struct PER1_W<'a> { + w: &'a mut W, +} +impl<'a> PER1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PER2` reader - Periodic Interval 2"] +pub struct PER2_R(crate::FieldReader); +impl PER2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER2` writer - Periodic Interval 2"] +pub struct PER2_W<'a> { + w: &'a mut W, +} +impl<'a> PER2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PER3` reader - Periodic Interval 3"] +pub struct PER3_R(crate::FieldReader); +impl PER3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER3` writer - Periodic Interval 3"] +pub struct PER3_W<'a> { + w: &'a mut W, +} +impl<'a> PER3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PER4` reader - Periodic Interval 4"] +pub struct PER4_R(crate::FieldReader); +impl PER4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER4` writer - Periodic Interval 4"] +pub struct PER4_W<'a> { + w: &'a mut W, +} +impl<'a> PER4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PER5` reader - Periodic Interval 5"] +pub struct PER5_R(crate::FieldReader); +impl PER5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER5` writer - Periodic Interval 5"] +pub struct PER5_W<'a> { + w: &'a mut W, +} +impl<'a> PER5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PER6` reader - Periodic Interval 6"] +pub struct PER6_R(crate::FieldReader); +impl PER6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER6` writer - Periodic Interval 6"] +pub struct PER6_W<'a> { + w: &'a mut W, +} +impl<'a> PER6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PER7` reader - Periodic Interval 7"] +pub struct PER7_R(crate::FieldReader); +impl PER7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER7` writer - Periodic Interval 7"] +pub struct PER7_W<'a> { + w: &'a mut W, +} +impl<'a> PER7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CMP0` reader - Compare 0"] +pub struct CMP0_R(crate::FieldReader); +impl CMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP0` writer - Compare 0"] +pub struct CMP0_W<'a> { + w: &'a mut W, +} +impl<'a> CMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0"] + #[inline(always)] + pub fn per0(&self) -> PER0_R { + PER0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1"] + #[inline(always)] + pub fn per1(&self) -> PER1_R { + PER1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2"] + #[inline(always)] + pub fn per2(&self) -> PER2_R { + PER2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3"] + #[inline(always)] + pub fn per3(&self) -> PER3_R { + PER3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4"] + #[inline(always)] + pub fn per4(&self) -> PER4_R { + PER4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5"] + #[inline(always)] + pub fn per5(&self) -> PER5_R { + PER5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6"] + #[inline(always)] + pub fn per6(&self) -> PER6_R { + PER6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7"] + #[inline(always)] + pub fn per7(&self) -> PER7_R { + PER7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Compare 0"] + #[inline(always)] + pub fn cmp0(&self) -> CMP0_R { + CMP0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0"] + #[inline(always)] + pub fn per0(&mut self) -> PER0_W { + PER0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1"] + #[inline(always)] + pub fn per1(&mut self) -> PER1_W { + PER1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2"] + #[inline(always)] + pub fn per2(&mut self) -> PER2_W { + PER2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3"] + #[inline(always)] + pub fn per3(&mut self) -> PER3_W { + PER3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4"] + #[inline(always)] + pub fn per4(&mut self) -> PER4_W { + PER4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5"] + #[inline(always)] + pub fn per5(&mut self) -> PER5_W { + PER5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6"] + #[inline(always)] + pub fn per6(&mut self) -> PER6_W { + PER6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7"] + #[inline(always)] + pub fn per7(&mut self) -> PER7_W { + PER7_W { w: self } + } + #[doc = "Bit 8 - Compare 0"] + #[inline(always)] + pub fn cmp0(&mut self) -> CMP0_W { + CMP0_W { w: self } + } + #[doc = "Bit 15 - Overflow"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE0 Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/rtc/mode0/syncbusy.rs b/pac/atsamc21g/src/rtc/mode0/syncbusy.rs new file mode 100644 index 000000000000..518dea115a18 --- /dev/null +++ b/pac/atsamc21g/src/rtc/mode0/syncbusy.rs @@ -0,0 +1,153 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - Enable Bit Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FREQCORR` reader - FREQCORR Register Busy"] +pub struct FREQCORR_R(crate::FieldReader); +impl FREQCORR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FREQCORR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FREQCORR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` reader - COUNT Register Busy"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP0` reader - COMP 0 Register Busy"] +pub struct COMP0_R(crate::FieldReader); +impl COMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNTSYNC` reader - Count Read Synchronization Enable Bit Busy"] +pub struct COUNTSYNC_R(crate::FieldReader); +impl COUNTSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNTSYNC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNTSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable Bit Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - FREQCORR Register Busy"] + #[inline(always)] + pub fn freqcorr(&self) -> FREQCORR_R { + FREQCORR_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - COUNT Register Busy"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 5 - COMP 0 Register Busy"] + #[inline(always)] + pub fn comp0(&self) -> COMP0_R { + COMP0_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 15 - Count Read Synchronization Enable Bit Busy"] + #[inline(always)] + pub fn countsync(&self) -> COUNTSYNC_R { + COUNTSYNC_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +#[doc = "MODE0 Synchronization Busy Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/rtc/mode1.rs b/pac/atsamc21g/src/rtc/mode1.rs new file mode 100644 index 000000000000..9ea1bc17497c --- /dev/null +++ b/pac/atsamc21g/src/rtc/mode1.rs @@ -0,0 +1,44 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "MODE1 Control A"] +pub mod ctrla; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "MODE1 Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "MODE1 Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "MODE1 Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "MODE1 Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "MODE1 Synchronization Busy Status"] +pub mod syncbusy; +#[doc = "FREQCORR register accessor: an alias for `Reg`"] +pub type FREQCORR = crate::Reg; +#[doc = "Frequency Correction"] +pub mod freqcorr; +#[doc = "COUNT register accessor: an alias for `Reg`"] +pub type COUNT = crate::Reg; +#[doc = "MODE1 Counter Value"] +pub mod count; +#[doc = "PER register accessor: an alias for `Reg`"] +pub type PER = crate::Reg; +#[doc = "MODE1 Counter Period"] +pub mod per; +#[doc = "COMP register accessor: an alias for `Reg`"] +pub type COMP = crate::Reg; +#[doc = "MODE1 Compare n Value"] +pub mod comp; diff --git a/pac/atsamc21g/src/rtc/mode1/comp.rs b/pac/atsamc21g/src/rtc/mode1/comp.rs new file mode 100644 index 000000000000..6935385840f1 --- /dev/null +++ b/pac/atsamc21g/src/rtc/mode1/comp.rs @@ -0,0 +1,104 @@ +#[doc = "Register `COMP[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COMP[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COMP` reader - Compare Value"] +pub struct COMP_R(crate::FieldReader); +impl COMP_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + COMP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP` writer - Compare Value"] +pub struct COMP_W<'a> { + w: &'a mut W, +} +impl<'a> COMP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Compare Value"] + #[inline(always)] + pub fn comp(&self) -> COMP_R { + COMP_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Compare Value"] + #[inline(always)] + pub fn comp(&mut self) -> COMP_W { + COMP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Compare n Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [comp](index.html) module"] +pub struct COMP_SPEC; +impl crate::RegisterSpec for COMP_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [comp::R](R) reader structure"] +impl crate::Readable for COMP_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [comp::W](W) writer structure"] +impl crate::Writable for COMP_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COMP[%s] +to value 0"] +impl crate::Resettable for COMP_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/rtc/mode1/count.rs b/pac/atsamc21g/src/rtc/mode1/count.rs new file mode 100644 index 000000000000..2c41937b189c --- /dev/null +++ b/pac/atsamc21g/src/rtc/mode1/count.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Counter Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count](index.html) module"] +pub struct COUNT_SPEC; +impl crate::RegisterSpec for COUNT_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [count::R](R) reader structure"] +impl crate::Readable for COUNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count::W](W) writer structure"] +impl crate::Writable for COUNT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT to value 0"] +impl crate::Resettable for COUNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/rtc/mode1/ctrla.rs b/pac/atsamc21g/src/rtc/mode1/ctrla.rs new file mode 100644 index 000000000000..6e3e2042a9c4 --- /dev/null +++ b/pac/atsamc21g/src/rtc/mode1/ctrla.rs @@ -0,0 +1,522 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: Mode 0: 32-bit Counter"] + COUNT32 = 0, + #[doc = "1: Mode 1: 16-bit Counter"] + COUNT16 = 1, + #[doc = "2: Mode 2: Clock/Calendar"] + CLOCK = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::COUNT32), + 1 => Some(MODE_A::COUNT16), + 2 => Some(MODE_A::CLOCK), + _ => None, + } + } + #[doc = "Checks if the value of the field is `COUNT32`"] + #[inline(always)] + pub fn is_count32(&self) -> bool { + **self == MODE_A::COUNT32 + } + #[doc = "Checks if the value of the field is `COUNT16`"] + #[inline(always)] + pub fn is_count16(&self) -> bool { + **self == MODE_A::COUNT16 + } + #[doc = "Checks if the value of the field is `CLOCK`"] + #[inline(always)] + pub fn is_clock(&self) -> bool { + **self == MODE_A::CLOCK + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Mode 0: 32-bit Counter"] + #[inline(always)] + pub fn count32(self) -> &'a mut W { + self.variant(MODE_A::COUNT32) + } + #[doc = "Mode 1: 16-bit Counter"] + #[inline(always)] + pub fn count16(self) -> &'a mut W { + self.variant(MODE_A::COUNT16) + } + #[doc = "Mode 2: Clock/Calendar"] + #[inline(always)] + pub fn clock(self) -> &'a mut W { + self.variant(MODE_A::CLOCK) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u16 & 0x03) << 2); + self.w + } +} +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: CLK_RTC_CNT = GCLK_RTC/1"] + OFF = 0, + #[doc = "1: CLK_RTC_CNT = GCLK_RTC/1"] + DIV1 = 1, + #[doc = "2: CLK_RTC_CNT = GCLK_RTC/2"] + DIV2 = 2, + #[doc = "3: CLK_RTC_CNT = GCLK_RTC/4"] + DIV4 = 3, + #[doc = "4: CLK_RTC_CNT = GCLK_RTC/8"] + DIV8 = 4, + #[doc = "5: CLK_RTC_CNT = GCLK_RTC/16"] + DIV16 = 5, + #[doc = "6: CLK_RTC_CNT = GCLK_RTC/32"] + DIV32 = 6, + #[doc = "7: CLK_RTC_CNT = GCLK_RTC/64"] + DIV64 = 7, + #[doc = "8: CLK_RTC_CNT = GCLK_RTC/128"] + DIV128 = 8, + #[doc = "9: CLK_RTC_CNT = GCLK_RTC/256"] + DIV256 = 9, + #[doc = "10: CLK_RTC_CNT = GCLK_RTC/512"] + DIV512 = 10, + #[doc = "11: CLK_RTC_CNT = GCLK_RTC/1024"] + DIV1024 = 11, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCALER_A::OFF), + 1 => Some(PRESCALER_A::DIV1), + 2 => Some(PRESCALER_A::DIV2), + 3 => Some(PRESCALER_A::DIV4), + 4 => Some(PRESCALER_A::DIV8), + 5 => Some(PRESCALER_A::DIV16), + 6 => Some(PRESCALER_A::DIV32), + 7 => Some(PRESCALER_A::DIV64), + 8 => Some(PRESCALER_A::DIV128), + 9 => Some(PRESCALER_A::DIV256), + 10 => Some(PRESCALER_A::DIV512), + 11 => Some(PRESCALER_A::DIV1024), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == PRESCALER_A::OFF + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == PRESCALER_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == PRESCALER_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == PRESCALER_A::DIV128 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV512`"] + #[inline(always)] + pub fn is_div512(&self) -> bool { + **self == PRESCALER_A::DIV512 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PRESCALER_A::DIV1024 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(PRESCALER_A::OFF) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV32) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV128) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/512"] + #[inline(always)] + pub fn div512(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV512) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 8)) | ((value as u16 & 0x0f) << 8); + self.w + } +} +#[doc = "Field `COUNTSYNC` reader - Count Read Synchronization Enable"] +pub struct COUNTSYNC_R(crate::FieldReader); +impl COUNTSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNTSYNC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNTSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNTSYNC` writer - Count Read Synchronization Enable"] +pub struct COUNTSYNC_W<'a> { + w: &'a mut W, +} +impl<'a> COUNTSYNC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:3 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bits 8:11 - Prescaler"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 15 - Count Read Synchronization Enable"] + #[inline(always)] + pub fn countsync(&self) -> COUNTSYNC_R { + COUNTSYNC_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:3 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bits 8:11 - Prescaler"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Bit 15 - Count Read Synchronization Enable"] + #[inline(always)] + pub fn countsync(&mut self) -> COUNTSYNC_W { + COUNTSYNC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/rtc/mode1/dbgctrl.rs b/pac/atsamc21g/src/rtc/mode1/dbgctrl.rs new file mode 100644 index 000000000000..0383e70d0429 --- /dev/null +++ b/pac/atsamc21g/src/rtc/mode1/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Run During Debug"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Run During Debug"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/rtc/mode1/evctrl.rs b/pac/atsamc21g/src/rtc/mode1/evctrl.rs new file mode 100644 index 000000000000..e15624f828c7 --- /dev/null +++ b/pac/atsamc21g/src/rtc/mode1/evctrl.rs @@ -0,0 +1,583 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PEREO0` reader - Periodic Interval 0 Event Output Enable"] +pub struct PEREO0_R(crate::FieldReader); +impl PEREO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO0` writer - Periodic Interval 0 Event Output Enable"] +pub struct PEREO0_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `PEREO1` reader - Periodic Interval 1 Event Output Enable"] +pub struct PEREO1_R(crate::FieldReader); +impl PEREO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO1` writer - Periodic Interval 1 Event Output Enable"] +pub struct PEREO1_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PEREO2` reader - Periodic Interval 2 Event Output Enable"] +pub struct PEREO2_R(crate::FieldReader); +impl PEREO2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO2` writer - Periodic Interval 2 Event Output Enable"] +pub struct PEREO2_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PEREO3` reader - Periodic Interval 3 Event Output Enable"] +pub struct PEREO3_R(crate::FieldReader); +impl PEREO3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO3` writer - Periodic Interval 3 Event Output Enable"] +pub struct PEREO3_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PEREO4` reader - Periodic Interval 4 Event Output Enable"] +pub struct PEREO4_R(crate::FieldReader); +impl PEREO4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO4` writer - Periodic Interval 4 Event Output Enable"] +pub struct PEREO4_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PEREO5` reader - Periodic Interval 5 Event Output Enable"] +pub struct PEREO5_R(crate::FieldReader); +impl PEREO5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO5` writer - Periodic Interval 5 Event Output Enable"] +pub struct PEREO5_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PEREO6` reader - Periodic Interval 6 Event Output Enable"] +pub struct PEREO6_R(crate::FieldReader); +impl PEREO6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO6` writer - Periodic Interval 6 Event Output Enable"] +pub struct PEREO6_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PEREO7` reader - Periodic Interval 7 Event Output Enable"] +pub struct PEREO7_R(crate::FieldReader); +impl PEREO7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO7` writer - Periodic Interval 7 Event Output Enable"] +pub struct PEREO7_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CMPEO0` reader - Compare 0 Event Output Enable"] +pub struct CMPEO0_R(crate::FieldReader); +impl CMPEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMPEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMPEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMPEO0` writer - Compare 0 Event Output Enable"] +pub struct CMPEO0_W<'a> { + w: &'a mut W, +} +impl<'a> CMPEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `CMPEO1` reader - Compare 1 Event Output Enable"] +pub struct CMPEO1_R(crate::FieldReader); +impl CMPEO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMPEO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMPEO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMPEO1` writer - Compare 1 Event Output Enable"] +pub struct CMPEO1_W<'a> { + w: &'a mut W, +} +impl<'a> CMPEO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `OVFEO` reader - Overflow Event Output Enable"] +pub struct OVFEO_R(crate::FieldReader); +impl OVFEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVFEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVFEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVFEO` writer - Overflow Event Output Enable"] +pub struct OVFEO_W<'a> { + w: &'a mut W, +} +impl<'a> OVFEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Event Output Enable"] + #[inline(always)] + pub fn pereo0(&self) -> PEREO0_R { + PEREO0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Event Output Enable"] + #[inline(always)] + pub fn pereo1(&self) -> PEREO1_R { + PEREO1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Event Output Enable"] + #[inline(always)] + pub fn pereo2(&self) -> PEREO2_R { + PEREO2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Event Output Enable"] + #[inline(always)] + pub fn pereo3(&self) -> PEREO3_R { + PEREO3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Event Output Enable"] + #[inline(always)] + pub fn pereo4(&self) -> PEREO4_R { + PEREO4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Event Output Enable"] + #[inline(always)] + pub fn pereo5(&self) -> PEREO5_R { + PEREO5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Event Output Enable"] + #[inline(always)] + pub fn pereo6(&self) -> PEREO6_R { + PEREO6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Event Output Enable"] + #[inline(always)] + pub fn pereo7(&self) -> PEREO7_R { + PEREO7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Compare 0 Event Output Enable"] + #[inline(always)] + pub fn cmpeo0(&self) -> CMPEO0_R { + CMPEO0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Compare 1 Event Output Enable"] + #[inline(always)] + pub fn cmpeo1(&self) -> CMPEO1_R { + CMPEO1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&self) -> OVFEO_R { + OVFEO_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Event Output Enable"] + #[inline(always)] + pub fn pereo0(&mut self) -> PEREO0_W { + PEREO0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1 Event Output Enable"] + #[inline(always)] + pub fn pereo1(&mut self) -> PEREO1_W { + PEREO1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2 Event Output Enable"] + #[inline(always)] + pub fn pereo2(&mut self) -> PEREO2_W { + PEREO2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3 Event Output Enable"] + #[inline(always)] + pub fn pereo3(&mut self) -> PEREO3_W { + PEREO3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4 Event Output Enable"] + #[inline(always)] + pub fn pereo4(&mut self) -> PEREO4_W { + PEREO4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5 Event Output Enable"] + #[inline(always)] + pub fn pereo5(&mut self) -> PEREO5_W { + PEREO5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6 Event Output Enable"] + #[inline(always)] + pub fn pereo6(&mut self) -> PEREO6_W { + PEREO6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7 Event Output Enable"] + #[inline(always)] + pub fn pereo7(&mut self) -> PEREO7_W { + PEREO7_W { w: self } + } + #[doc = "Bit 8 - Compare 0 Event Output Enable"] + #[inline(always)] + pub fn cmpeo0(&mut self) -> CMPEO0_W { + CMPEO0_W { w: self } + } + #[doc = "Bit 9 - Compare 1 Event Output Enable"] + #[inline(always)] + pub fn cmpeo1(&mut self) -> CMPEO1_W { + CMPEO1_W { w: self } + } + #[doc = "Bit 15 - Overflow Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&mut self) -> OVFEO_W { + OVFEO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/rtc/mode1/freqcorr.rs b/pac/atsamc21g/src/rtc/mode1/freqcorr.rs new file mode 100644 index 000000000000..043ba6f88eb2 --- /dev/null +++ b/pac/atsamc21g/src/rtc/mode1/freqcorr.rs @@ -0,0 +1,150 @@ +#[doc = "Register `FREQCORR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FREQCORR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `VALUE` reader - Correction Value"] +pub struct VALUE_R(crate::FieldReader); +impl VALUE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + VALUE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VALUE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VALUE` writer - Correction Value"] +pub struct VALUE_W<'a> { + w: &'a mut W, +} +impl<'a> VALUE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x7f) | (value as u8 & 0x7f); + self.w + } +} +#[doc = "Field `SIGN` reader - Correction Sign"] +pub struct SIGN_R(crate::FieldReader); +impl SIGN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SIGN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SIGN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SIGN` writer - Correction Sign"] +pub struct SIGN_W<'a> { + w: &'a mut W, +} +impl<'a> SIGN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bits 0:6 - Correction Value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bit 7 - Correction Sign"] + #[inline(always)] + pub fn sign(&self) -> SIGN_R { + SIGN_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:6 - Correction Value"] + #[inline(always)] + pub fn value(&mut self) -> VALUE_W { + VALUE_W { w: self } + } + #[doc = "Bit 7 - Correction Sign"] + #[inline(always)] + pub fn sign(&mut self) -> SIGN_W { + SIGN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Frequency Correction\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [freqcorr](index.html) module"] +pub struct FREQCORR_SPEC; +impl crate::RegisterSpec for FREQCORR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [freqcorr::R](R) reader structure"] +impl crate::Readable for FREQCORR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [freqcorr::W](W) writer structure"] +impl crate::Writable for FREQCORR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets FREQCORR to value 0"] +impl crate::Resettable for FREQCORR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/rtc/mode1/intenclr.rs b/pac/atsamc21g/src/rtc/mode1/intenclr.rs new file mode 100644 index 000000000000..d3fc5b3df34b --- /dev/null +++ b/pac/atsamc21g/src/rtc/mode1/intenclr.rs @@ -0,0 +1,583 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER0` reader - Periodic Interval 0 Interrupt Enable"] +pub struct PER0_R(crate::FieldReader); +impl PER0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER0` writer - Periodic Interval 0 Interrupt Enable"] +pub struct PER0_W<'a> { + w: &'a mut W, +} +impl<'a> PER0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PER1` reader - Periodic Interval 1 Interrupt Enable"] +pub struct PER1_R(crate::FieldReader); +impl PER1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER1` writer - Periodic Interval 1 Interrupt Enable"] +pub struct PER1_W<'a> { + w: &'a mut W, +} +impl<'a> PER1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PER2` reader - Periodic Interval 2 Interrupt Enable"] +pub struct PER2_R(crate::FieldReader); +impl PER2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER2` writer - Periodic Interval 2 Interrupt Enable"] +pub struct PER2_W<'a> { + w: &'a mut W, +} +impl<'a> PER2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PER3` reader - Periodic Interval 3 Interrupt Enable"] +pub struct PER3_R(crate::FieldReader); +impl PER3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER3` writer - Periodic Interval 3 Interrupt Enable"] +pub struct PER3_W<'a> { + w: &'a mut W, +} +impl<'a> PER3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PER4` reader - Periodic Interval 4 Interrupt Enable"] +pub struct PER4_R(crate::FieldReader); +impl PER4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER4` writer - Periodic Interval 4 Interrupt Enable"] +pub struct PER4_W<'a> { + w: &'a mut W, +} +impl<'a> PER4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PER5` reader - Periodic Interval 5 Interrupt Enable"] +pub struct PER5_R(crate::FieldReader); +impl PER5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER5` writer - Periodic Interval 5 Interrupt Enable"] +pub struct PER5_W<'a> { + w: &'a mut W, +} +impl<'a> PER5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PER6` reader - Periodic Interval 6 Interrupt Enable"] +pub struct PER6_R(crate::FieldReader); +impl PER6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER6` writer - Periodic Interval 6 Interrupt Enable"] +pub struct PER6_W<'a> { + w: &'a mut W, +} +impl<'a> PER6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PER7` reader - Periodic Interval 7 Interrupt Enable"] +pub struct PER7_R(crate::FieldReader); +impl PER7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER7` writer - Periodic Interval 7 Interrupt Enable"] +pub struct PER7_W<'a> { + w: &'a mut W, +} +impl<'a> PER7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CMP0` reader - Compare 0 Interrupt Enable"] +pub struct CMP0_R(crate::FieldReader); +impl CMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP0` writer - Compare 0 Interrupt Enable"] +pub struct CMP0_W<'a> { + w: &'a mut W, +} +impl<'a> CMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `CMP1` reader - Compare 1 Interrupt Enable"] +pub struct CMP1_R(crate::FieldReader); +impl CMP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP1` writer - Compare 1 Interrupt Enable"] +pub struct CMP1_W<'a> { + w: &'a mut W, +} +impl<'a> CMP1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + pub fn per0(&self) -> PER0_R { + PER0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + pub fn per1(&self) -> PER1_R { + PER1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + pub fn per2(&self) -> PER2_R { + PER2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + pub fn per3(&self) -> PER3_R { + PER3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + pub fn per4(&self) -> PER4_R { + PER4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + pub fn per5(&self) -> PER5_R { + PER5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + pub fn per6(&self) -> PER6_R { + PER6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + pub fn per7(&self) -> PER7_R { + PER7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&self) -> CMP0_R { + CMP0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Compare 1 Interrupt Enable"] + #[inline(always)] + pub fn cmp1(&self) -> CMP1_R { + CMP1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + pub fn per0(&mut self) -> PER0_W { + PER0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + pub fn per1(&mut self) -> PER1_W { + PER1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + pub fn per2(&mut self) -> PER2_W { + PER2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + pub fn per3(&mut self) -> PER3_W { + PER3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + pub fn per4(&mut self) -> PER4_W { + PER4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + pub fn per5(&mut self) -> PER5_W { + PER5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + pub fn per6(&mut self) -> PER6_W { + PER6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + pub fn per7(&mut self) -> PER7_W { + PER7_W { w: self } + } + #[doc = "Bit 8 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&mut self) -> CMP0_W { + CMP0_W { w: self } + } + #[doc = "Bit 9 - Compare 1 Interrupt Enable"] + #[inline(always)] + pub fn cmp1(&mut self) -> CMP1_W { + CMP1_W { w: self } + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/rtc/mode1/intenset.rs b/pac/atsamc21g/src/rtc/mode1/intenset.rs new file mode 100644 index 000000000000..074cb377926a --- /dev/null +++ b/pac/atsamc21g/src/rtc/mode1/intenset.rs @@ -0,0 +1,583 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER0` reader - Periodic Interval 0 Interrupt Enable"] +pub struct PER0_R(crate::FieldReader); +impl PER0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER0` writer - Periodic Interval 0 Interrupt Enable"] +pub struct PER0_W<'a> { + w: &'a mut W, +} +impl<'a> PER0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PER1` reader - Periodic Interval 1 Interrupt Enable"] +pub struct PER1_R(crate::FieldReader); +impl PER1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER1` writer - Periodic Interval 1 Interrupt Enable"] +pub struct PER1_W<'a> { + w: &'a mut W, +} +impl<'a> PER1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PER2` reader - Periodic Interval 2 Interrupt Enable"] +pub struct PER2_R(crate::FieldReader); +impl PER2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER2` writer - Periodic Interval 2 Interrupt Enable"] +pub struct PER2_W<'a> { + w: &'a mut W, +} +impl<'a> PER2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PER3` reader - Periodic Interval 3 Interrupt Enable"] +pub struct PER3_R(crate::FieldReader); +impl PER3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER3` writer - Periodic Interval 3 Interrupt Enable"] +pub struct PER3_W<'a> { + w: &'a mut W, +} +impl<'a> PER3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PER4` reader - Periodic Interval 4 Interrupt Enable"] +pub struct PER4_R(crate::FieldReader); +impl PER4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER4` writer - Periodic Interval 4 Interrupt Enable"] +pub struct PER4_W<'a> { + w: &'a mut W, +} +impl<'a> PER4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PER5` reader - Periodic Interval 5 Interrupt Enable"] +pub struct PER5_R(crate::FieldReader); +impl PER5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER5` writer - Periodic Interval 5 Interrupt Enable"] +pub struct PER5_W<'a> { + w: &'a mut W, +} +impl<'a> PER5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PER6` reader - Periodic Interval 6 Interrupt Enable"] +pub struct PER6_R(crate::FieldReader); +impl PER6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER6` writer - Periodic Interval 6 Interrupt Enable"] +pub struct PER6_W<'a> { + w: &'a mut W, +} +impl<'a> PER6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PER7` reader - Periodic Interval 7 Interrupt Enable"] +pub struct PER7_R(crate::FieldReader); +impl PER7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER7` writer - Periodic Interval 7 Interrupt Enable"] +pub struct PER7_W<'a> { + w: &'a mut W, +} +impl<'a> PER7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CMP0` reader - Compare 0 Interrupt Enable"] +pub struct CMP0_R(crate::FieldReader); +impl CMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP0` writer - Compare 0 Interrupt Enable"] +pub struct CMP0_W<'a> { + w: &'a mut W, +} +impl<'a> CMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `CMP1` reader - Compare 1 Interrupt Enable"] +pub struct CMP1_R(crate::FieldReader); +impl CMP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP1` writer - Compare 1 Interrupt Enable"] +pub struct CMP1_W<'a> { + w: &'a mut W, +} +impl<'a> CMP1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + pub fn per0(&self) -> PER0_R { + PER0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + pub fn per1(&self) -> PER1_R { + PER1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + pub fn per2(&self) -> PER2_R { + PER2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + pub fn per3(&self) -> PER3_R { + PER3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + pub fn per4(&self) -> PER4_R { + PER4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + pub fn per5(&self) -> PER5_R { + PER5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + pub fn per6(&self) -> PER6_R { + PER6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + pub fn per7(&self) -> PER7_R { + PER7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&self) -> CMP0_R { + CMP0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Compare 1 Interrupt Enable"] + #[inline(always)] + pub fn cmp1(&self) -> CMP1_R { + CMP1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + pub fn per0(&mut self) -> PER0_W { + PER0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + pub fn per1(&mut self) -> PER1_W { + PER1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + pub fn per2(&mut self) -> PER2_W { + PER2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + pub fn per3(&mut self) -> PER3_W { + PER3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + pub fn per4(&mut self) -> PER4_W { + PER4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + pub fn per5(&mut self) -> PER5_W { + PER5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + pub fn per6(&mut self) -> PER6_W { + PER6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + pub fn per7(&mut self) -> PER7_W { + PER7_W { w: self } + } + #[doc = "Bit 8 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&mut self) -> CMP0_W { + CMP0_W { w: self } + } + #[doc = "Bit 9 - Compare 1 Interrupt Enable"] + #[inline(always)] + pub fn cmp1(&mut self) -> CMP1_W { + CMP1_W { w: self } + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/rtc/mode1/intflag.rs b/pac/atsamc21g/src/rtc/mode1/intflag.rs new file mode 100644 index 000000000000..25bce956f46b --- /dev/null +++ b/pac/atsamc21g/src/rtc/mode1/intflag.rs @@ -0,0 +1,583 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER0` reader - Periodic Interval 0"] +pub struct PER0_R(crate::FieldReader); +impl PER0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER0` writer - Periodic Interval 0"] +pub struct PER0_W<'a> { + w: &'a mut W, +} +impl<'a> PER0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PER1` reader - Periodic Interval 1"] +pub struct PER1_R(crate::FieldReader); +impl PER1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER1` writer - Periodic Interval 1"] +pub struct PER1_W<'a> { + w: &'a mut W, +} +impl<'a> PER1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PER2` reader - Periodic Interval 2"] +pub struct PER2_R(crate::FieldReader); +impl PER2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER2` writer - Periodic Interval 2"] +pub struct PER2_W<'a> { + w: &'a mut W, +} +impl<'a> PER2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PER3` reader - Periodic Interval 3"] +pub struct PER3_R(crate::FieldReader); +impl PER3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER3` writer - Periodic Interval 3"] +pub struct PER3_W<'a> { + w: &'a mut W, +} +impl<'a> PER3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PER4` reader - Periodic Interval 4"] +pub struct PER4_R(crate::FieldReader); +impl PER4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER4` writer - Periodic Interval 4"] +pub struct PER4_W<'a> { + w: &'a mut W, +} +impl<'a> PER4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PER5` reader - Periodic Interval 5"] +pub struct PER5_R(crate::FieldReader); +impl PER5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER5` writer - Periodic Interval 5"] +pub struct PER5_W<'a> { + w: &'a mut W, +} +impl<'a> PER5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PER6` reader - Periodic Interval 6"] +pub struct PER6_R(crate::FieldReader); +impl PER6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER6` writer - Periodic Interval 6"] +pub struct PER6_W<'a> { + w: &'a mut W, +} +impl<'a> PER6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PER7` reader - Periodic Interval 7"] +pub struct PER7_R(crate::FieldReader); +impl PER7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER7` writer - Periodic Interval 7"] +pub struct PER7_W<'a> { + w: &'a mut W, +} +impl<'a> PER7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CMP0` reader - Compare 0"] +pub struct CMP0_R(crate::FieldReader); +impl CMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP0` writer - Compare 0"] +pub struct CMP0_W<'a> { + w: &'a mut W, +} +impl<'a> CMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `CMP1` reader - Compare 1"] +pub struct CMP1_R(crate::FieldReader); +impl CMP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP1` writer - Compare 1"] +pub struct CMP1_W<'a> { + w: &'a mut W, +} +impl<'a> CMP1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0"] + #[inline(always)] + pub fn per0(&self) -> PER0_R { + PER0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1"] + #[inline(always)] + pub fn per1(&self) -> PER1_R { + PER1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2"] + #[inline(always)] + pub fn per2(&self) -> PER2_R { + PER2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3"] + #[inline(always)] + pub fn per3(&self) -> PER3_R { + PER3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4"] + #[inline(always)] + pub fn per4(&self) -> PER4_R { + PER4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5"] + #[inline(always)] + pub fn per5(&self) -> PER5_R { + PER5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6"] + #[inline(always)] + pub fn per6(&self) -> PER6_R { + PER6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7"] + #[inline(always)] + pub fn per7(&self) -> PER7_R { + PER7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Compare 0"] + #[inline(always)] + pub fn cmp0(&self) -> CMP0_R { + CMP0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Compare 1"] + #[inline(always)] + pub fn cmp1(&self) -> CMP1_R { + CMP1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0"] + #[inline(always)] + pub fn per0(&mut self) -> PER0_W { + PER0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1"] + #[inline(always)] + pub fn per1(&mut self) -> PER1_W { + PER1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2"] + #[inline(always)] + pub fn per2(&mut self) -> PER2_W { + PER2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3"] + #[inline(always)] + pub fn per3(&mut self) -> PER3_W { + PER3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4"] + #[inline(always)] + pub fn per4(&mut self) -> PER4_W { + PER4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5"] + #[inline(always)] + pub fn per5(&mut self) -> PER5_W { + PER5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6"] + #[inline(always)] + pub fn per6(&mut self) -> PER6_W { + PER6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7"] + #[inline(always)] + pub fn per7(&mut self) -> PER7_W { + PER7_W { w: self } + } + #[doc = "Bit 8 - Compare 0"] + #[inline(always)] + pub fn cmp0(&mut self) -> CMP0_W { + CMP0_W { w: self } + } + #[doc = "Bit 9 - Compare 1"] + #[inline(always)] + pub fn cmp1(&mut self) -> CMP1_W { + CMP1_W { w: self } + } + #[doc = "Bit 15 - Overflow"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/rtc/mode1/per.rs b/pac/atsamc21g/src/rtc/mode1/per.rs new file mode 100644 index 000000000000..c09b31fa30dd --- /dev/null +++ b/pac/atsamc21g/src/rtc/mode1/per.rs @@ -0,0 +1,103 @@ +#[doc = "Register `PER` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PER` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER` reader - Counter Period"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` writer - Counter Period"] +pub struct PER_W<'a> { + w: &'a mut W, +} +impl<'a> PER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Counter Period"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Counter Period"] + #[inline(always)] + pub fn per(&mut self) -> PER_W { + PER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Counter Period\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [per](index.html) module"] +pub struct PER_SPEC; +impl crate::RegisterSpec for PER_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [per::R](R) reader structure"] +impl crate::Readable for PER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [per::W](W) writer structure"] +impl crate::Writable for PER_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PER to value 0"] +impl crate::Resettable for PER_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/rtc/mode1/syncbusy.rs b/pac/atsamc21g/src/rtc/mode1/syncbusy.rs new file mode 100644 index 000000000000..b64c973bafff --- /dev/null +++ b/pac/atsamc21g/src/rtc/mode1/syncbusy.rs @@ -0,0 +1,193 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Bit Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - Enable Bit Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FREQCORR` reader - FREQCORR Register Busy"] +pub struct FREQCORR_R(crate::FieldReader); +impl FREQCORR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FREQCORR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FREQCORR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` reader - COUNT Register Busy"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` reader - PER Register Busy"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP0` reader - COMP 0 Register Busy"] +pub struct COMP0_R(crate::FieldReader); +impl COMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP1` reader - COMP 1 Register Busy"] +pub struct COMP1_R(crate::FieldReader); +impl COMP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNTSYNC` reader - Count Read Synchronization Enable Bit Busy"] +pub struct COUNTSYNC_R(crate::FieldReader); +impl COUNTSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNTSYNC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNTSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Bit Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable Bit Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - FREQCORR Register Busy"] + #[inline(always)] + pub fn freqcorr(&self) -> FREQCORR_R { + FREQCORR_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - COUNT Register Busy"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - PER Register Busy"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - COMP 0 Register Busy"] + #[inline(always)] + pub fn comp0(&self) -> COMP0_R { + COMP0_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - COMP 1 Register Busy"] + #[inline(always)] + pub fn comp1(&self) -> COMP1_R { + COMP1_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 15 - Count Read Synchronization Enable Bit Busy"] + #[inline(always)] + pub fn countsync(&self) -> COUNTSYNC_R { + COUNTSYNC_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +#[doc = "MODE1 Synchronization Busy Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/rtc/mode2.rs b/pac/atsamc21g/src/rtc/mode2.rs new file mode 100644 index 000000000000..b0bc13e81dbc --- /dev/null +++ b/pac/atsamc21g/src/rtc/mode2.rs @@ -0,0 +1,44 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "MODE2 Control A"] +pub mod ctrla; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "MODE2 Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "MODE2 Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "MODE2 Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "MODE2 Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "MODE2 Synchronization Busy Status"] +pub mod syncbusy; +#[doc = "FREQCORR register accessor: an alias for `Reg`"] +pub type FREQCORR = crate::Reg; +#[doc = "Frequency Correction"] +pub mod freqcorr; +#[doc = "CLOCK register accessor: an alias for `Reg`"] +pub type CLOCK = crate::Reg; +#[doc = "MODE2 Clock Value"] +pub mod clock; +#[doc = "ALARM register accessor: an alias for `Reg`"] +pub type ALARM = crate::Reg; +#[doc = "MODE2_ALARM Alarm n Value"] +pub mod alarm; +#[doc = "MASK register accessor: an alias for `Reg`"] +pub type MASK = crate::Reg; +#[doc = "MODE2_ALARM Alarm n Mask"] +pub mod mask; diff --git a/pac/atsamc21g/src/rtc/mode2/alarm.rs b/pac/atsamc21g/src/rtc/mode2/alarm.rs new file mode 100644 index 000000000000..1242477ea69f --- /dev/null +++ b/pac/atsamc21g/src/rtc/mode2/alarm.rs @@ -0,0 +1,337 @@ +#[doc = "Register `ALARM` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ALARM` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SECOND` reader - Second"] +pub struct SECOND_R(crate::FieldReader); +impl SECOND_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SECOND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SECOND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SECOND` writer - Second"] +pub struct SECOND_W<'a> { + w: &'a mut W, +} +impl<'a> SECOND_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +#[doc = "Field `MINUTE` reader - Minute"] +pub struct MINUTE_R(crate::FieldReader); +impl MINUTE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MINUTE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MINUTE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MINUTE` writer - Minute"] +pub struct MINUTE_W<'a> { + w: &'a mut W, +} +impl<'a> MINUTE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 6)) | ((value as u32 & 0x3f) << 6); + self.w + } +} +#[doc = "Hour\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum HOUR_A { + #[doc = "0: Morning hour"] + AM = 0, + #[doc = "16: Afternoon hour"] + PM = 16, +} +impl From for u8 { + #[inline(always)] + fn from(variant: HOUR_A) -> Self { + variant as _ + } +} +#[doc = "Field `HOUR` reader - Hour"] +pub struct HOUR_R(crate::FieldReader); +impl HOUR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + HOUR_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(HOUR_A::AM), + 16 => Some(HOUR_A::PM), + _ => None, + } + } + #[doc = "Checks if the value of the field is `AM`"] + #[inline(always)] + pub fn is_am(&self) -> bool { + **self == HOUR_A::AM + } + #[doc = "Checks if the value of the field is `PM`"] + #[inline(always)] + pub fn is_pm(&self) -> bool { + **self == HOUR_A::PM + } +} +impl core::ops::Deref for HOUR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HOUR` writer - Hour"] +pub struct HOUR_W<'a> { + w: &'a mut W, +} +impl<'a> HOUR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: HOUR_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Morning hour"] + #[inline(always)] + pub fn am(self) -> &'a mut W { + self.variant(HOUR_A::AM) + } + #[doc = "Afternoon hour"] + #[inline(always)] + pub fn pm(self) -> &'a mut W { + self.variant(HOUR_A::PM) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 12)) | ((value as u32 & 0x1f) << 12); + self.w + } +} +#[doc = "Field `DAY` reader - Day"] +pub struct DAY_R(crate::FieldReader); +impl DAY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DAY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DAY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DAY` writer - Day"] +pub struct DAY_W<'a> { + w: &'a mut W, +} +impl<'a> DAY_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 17)) | ((value as u32 & 0x1f) << 17); + self.w + } +} +#[doc = "Field `MONTH` reader - Month"] +pub struct MONTH_R(crate::FieldReader); +impl MONTH_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MONTH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MONTH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MONTH` writer - Month"] +pub struct MONTH_W<'a> { + w: &'a mut W, +} +impl<'a> MONTH_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 22)) | ((value as u32 & 0x0f) << 22); + self.w + } +} +#[doc = "Field `YEAR` reader - Year"] +pub struct YEAR_R(crate::FieldReader); +impl YEAR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + YEAR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for YEAR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `YEAR` writer - Year"] +pub struct YEAR_W<'a> { + w: &'a mut W, +} +impl<'a> YEAR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 26)) | ((value as u32 & 0x3f) << 26); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Second"] + #[inline(always)] + pub fn second(&self) -> SECOND_R { + SECOND_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:11 - Minute"] + #[inline(always)] + pub fn minute(&self) -> MINUTE_R { + MINUTE_R::new(((self.bits >> 6) & 0x3f) as u8) + } + #[doc = "Bits 12:16 - Hour"] + #[inline(always)] + pub fn hour(&self) -> HOUR_R { + HOUR_R::new(((self.bits >> 12) & 0x1f) as u8) + } + #[doc = "Bits 17:21 - Day"] + #[inline(always)] + pub fn day(&self) -> DAY_R { + DAY_R::new(((self.bits >> 17) & 0x1f) as u8) + } + #[doc = "Bits 22:25 - Month"] + #[inline(always)] + pub fn month(&self) -> MONTH_R { + MONTH_R::new(((self.bits >> 22) & 0x0f) as u8) + } + #[doc = "Bits 26:31 - Year"] + #[inline(always)] + pub fn year(&self) -> YEAR_R { + YEAR_R::new(((self.bits >> 26) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - Second"] + #[inline(always)] + pub fn second(&mut self) -> SECOND_W { + SECOND_W { w: self } + } + #[doc = "Bits 6:11 - Minute"] + #[inline(always)] + pub fn minute(&mut self) -> MINUTE_W { + MINUTE_W { w: self } + } + #[doc = "Bits 12:16 - Hour"] + #[inline(always)] + pub fn hour(&mut self) -> HOUR_W { + HOUR_W { w: self } + } + #[doc = "Bits 17:21 - Day"] + #[inline(always)] + pub fn day(&mut self) -> DAY_W { + DAY_W { w: self } + } + #[doc = "Bits 22:25 - Month"] + #[inline(always)] + pub fn month(&mut self) -> MONTH_W { + MONTH_W { w: self } + } + #[doc = "Bits 26:31 - Year"] + #[inline(always)] + pub fn year(&mut self) -> YEAR_W { + YEAR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2_ALARM Alarm n Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [alarm](index.html) module"] +pub struct ALARM_SPEC; +impl crate::RegisterSpec for ALARM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [alarm::R](R) reader structure"] +impl crate::Readable for ALARM_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [alarm::W](W) writer structure"] +impl crate::Writable for ALARM_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ALARM to value 0"] +impl crate::Resettable for ALARM_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/rtc/mode2/clock.rs b/pac/atsamc21g/src/rtc/mode2/clock.rs new file mode 100644 index 000000000000..3f364ff8e57b --- /dev/null +++ b/pac/atsamc21g/src/rtc/mode2/clock.rs @@ -0,0 +1,337 @@ +#[doc = "Register `CLOCK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CLOCK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SECOND` reader - Second"] +pub struct SECOND_R(crate::FieldReader); +impl SECOND_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SECOND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SECOND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SECOND` writer - Second"] +pub struct SECOND_W<'a> { + w: &'a mut W, +} +impl<'a> SECOND_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +#[doc = "Field `MINUTE` reader - Minute"] +pub struct MINUTE_R(crate::FieldReader); +impl MINUTE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MINUTE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MINUTE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MINUTE` writer - Minute"] +pub struct MINUTE_W<'a> { + w: &'a mut W, +} +impl<'a> MINUTE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 6)) | ((value as u32 & 0x3f) << 6); + self.w + } +} +#[doc = "Hour\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum HOUR_A { + #[doc = "0: AM when CLKREP in 12-hour"] + AM = 0, + #[doc = "16: PM when CLKREP in 12-hour"] + PM = 16, +} +impl From for u8 { + #[inline(always)] + fn from(variant: HOUR_A) -> Self { + variant as _ + } +} +#[doc = "Field `HOUR` reader - Hour"] +pub struct HOUR_R(crate::FieldReader); +impl HOUR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + HOUR_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(HOUR_A::AM), + 16 => Some(HOUR_A::PM), + _ => None, + } + } + #[doc = "Checks if the value of the field is `AM`"] + #[inline(always)] + pub fn is_am(&self) -> bool { + **self == HOUR_A::AM + } + #[doc = "Checks if the value of the field is `PM`"] + #[inline(always)] + pub fn is_pm(&self) -> bool { + **self == HOUR_A::PM + } +} +impl core::ops::Deref for HOUR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HOUR` writer - Hour"] +pub struct HOUR_W<'a> { + w: &'a mut W, +} +impl<'a> HOUR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: HOUR_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "AM when CLKREP in 12-hour"] + #[inline(always)] + pub fn am(self) -> &'a mut W { + self.variant(HOUR_A::AM) + } + #[doc = "PM when CLKREP in 12-hour"] + #[inline(always)] + pub fn pm(self) -> &'a mut W { + self.variant(HOUR_A::PM) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 12)) | ((value as u32 & 0x1f) << 12); + self.w + } +} +#[doc = "Field `DAY` reader - Day"] +pub struct DAY_R(crate::FieldReader); +impl DAY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DAY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DAY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DAY` writer - Day"] +pub struct DAY_W<'a> { + w: &'a mut W, +} +impl<'a> DAY_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 17)) | ((value as u32 & 0x1f) << 17); + self.w + } +} +#[doc = "Field `MONTH` reader - Month"] +pub struct MONTH_R(crate::FieldReader); +impl MONTH_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MONTH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MONTH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MONTH` writer - Month"] +pub struct MONTH_W<'a> { + w: &'a mut W, +} +impl<'a> MONTH_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 22)) | ((value as u32 & 0x0f) << 22); + self.w + } +} +#[doc = "Field `YEAR` reader - Year"] +pub struct YEAR_R(crate::FieldReader); +impl YEAR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + YEAR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for YEAR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `YEAR` writer - Year"] +pub struct YEAR_W<'a> { + w: &'a mut W, +} +impl<'a> YEAR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 26)) | ((value as u32 & 0x3f) << 26); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Second"] + #[inline(always)] + pub fn second(&self) -> SECOND_R { + SECOND_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:11 - Minute"] + #[inline(always)] + pub fn minute(&self) -> MINUTE_R { + MINUTE_R::new(((self.bits >> 6) & 0x3f) as u8) + } + #[doc = "Bits 12:16 - Hour"] + #[inline(always)] + pub fn hour(&self) -> HOUR_R { + HOUR_R::new(((self.bits >> 12) & 0x1f) as u8) + } + #[doc = "Bits 17:21 - Day"] + #[inline(always)] + pub fn day(&self) -> DAY_R { + DAY_R::new(((self.bits >> 17) & 0x1f) as u8) + } + #[doc = "Bits 22:25 - Month"] + #[inline(always)] + pub fn month(&self) -> MONTH_R { + MONTH_R::new(((self.bits >> 22) & 0x0f) as u8) + } + #[doc = "Bits 26:31 - Year"] + #[inline(always)] + pub fn year(&self) -> YEAR_R { + YEAR_R::new(((self.bits >> 26) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - Second"] + #[inline(always)] + pub fn second(&mut self) -> SECOND_W { + SECOND_W { w: self } + } + #[doc = "Bits 6:11 - Minute"] + #[inline(always)] + pub fn minute(&mut self) -> MINUTE_W { + MINUTE_W { w: self } + } + #[doc = "Bits 12:16 - Hour"] + #[inline(always)] + pub fn hour(&mut self) -> HOUR_W { + HOUR_W { w: self } + } + #[doc = "Bits 17:21 - Day"] + #[inline(always)] + pub fn day(&mut self) -> DAY_W { + DAY_W { w: self } + } + #[doc = "Bits 22:25 - Month"] + #[inline(always)] + pub fn month(&mut self) -> MONTH_W { + MONTH_W { w: self } + } + #[doc = "Bits 26:31 - Year"] + #[inline(always)] + pub fn year(&mut self) -> YEAR_W { + YEAR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2 Clock Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clock](index.html) module"] +pub struct CLOCK_SPEC; +impl crate::RegisterSpec for CLOCK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [clock::R](R) reader structure"] +impl crate::Readable for CLOCK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [clock::W](W) writer structure"] +impl crate::Writable for CLOCK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CLOCK to value 0"] +impl crate::Resettable for CLOCK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/rtc/mode2/ctrla.rs b/pac/atsamc21g/src/rtc/mode2/ctrla.rs new file mode 100644 index 000000000000..fc4bfda16bd8 --- /dev/null +++ b/pac/atsamc21g/src/rtc/mode2/ctrla.rs @@ -0,0 +1,616 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: Mode 0: 32-bit Counter"] + COUNT32 = 0, + #[doc = "1: Mode 1: 16-bit Counter"] + COUNT16 = 1, + #[doc = "2: Mode 2: Clock/Calendar"] + CLOCK = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::COUNT32), + 1 => Some(MODE_A::COUNT16), + 2 => Some(MODE_A::CLOCK), + _ => None, + } + } + #[doc = "Checks if the value of the field is `COUNT32`"] + #[inline(always)] + pub fn is_count32(&self) -> bool { + **self == MODE_A::COUNT32 + } + #[doc = "Checks if the value of the field is `COUNT16`"] + #[inline(always)] + pub fn is_count16(&self) -> bool { + **self == MODE_A::COUNT16 + } + #[doc = "Checks if the value of the field is `CLOCK`"] + #[inline(always)] + pub fn is_clock(&self) -> bool { + **self == MODE_A::CLOCK + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Mode 0: 32-bit Counter"] + #[inline(always)] + pub fn count32(self) -> &'a mut W { + self.variant(MODE_A::COUNT32) + } + #[doc = "Mode 1: 16-bit Counter"] + #[inline(always)] + pub fn count16(self) -> &'a mut W { + self.variant(MODE_A::COUNT16) + } + #[doc = "Mode 2: Clock/Calendar"] + #[inline(always)] + pub fn clock(self) -> &'a mut W { + self.variant(MODE_A::CLOCK) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u16 & 0x03) << 2); + self.w + } +} +#[doc = "Field `CLKREP` reader - Clock Representation"] +pub struct CLKREP_R(crate::FieldReader); +impl CLKREP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKREP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKREP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKREP` writer - Clock Representation"] +pub struct CLKREP_W<'a> { + w: &'a mut W, +} +impl<'a> CLKREP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `MATCHCLR` reader - Clear on Match"] +pub struct MATCHCLR_R(crate::FieldReader); +impl MATCHCLR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MATCHCLR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MATCHCLR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MATCHCLR` writer - Clear on Match"] +pub struct MATCHCLR_W<'a> { + w: &'a mut W, +} +impl<'a> MATCHCLR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: CLK_RTC_CNT = GCLK_RTC/1"] + OFF = 0, + #[doc = "1: CLK_RTC_CNT = GCLK_RTC/1"] + DIV1 = 1, + #[doc = "2: CLK_RTC_CNT = GCLK_RTC/2"] + DIV2 = 2, + #[doc = "3: CLK_RTC_CNT = GCLK_RTC/4"] + DIV4 = 3, + #[doc = "4: CLK_RTC_CNT = GCLK_RTC/8"] + DIV8 = 4, + #[doc = "5: CLK_RTC_CNT = GCLK_RTC/16"] + DIV16 = 5, + #[doc = "6: CLK_RTC_CNT = GCLK_RTC/32"] + DIV32 = 6, + #[doc = "7: CLK_RTC_CNT = GCLK_RTC/64"] + DIV64 = 7, + #[doc = "8: CLK_RTC_CNT = GCLK_RTC/128"] + DIV128 = 8, + #[doc = "9: CLK_RTC_CNT = GCLK_RTC/256"] + DIV256 = 9, + #[doc = "10: CLK_RTC_CNT = GCLK_RTC/512"] + DIV512 = 10, + #[doc = "11: CLK_RTC_CNT = GCLK_RTC/1024"] + DIV1024 = 11, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCALER_A::OFF), + 1 => Some(PRESCALER_A::DIV1), + 2 => Some(PRESCALER_A::DIV2), + 3 => Some(PRESCALER_A::DIV4), + 4 => Some(PRESCALER_A::DIV8), + 5 => Some(PRESCALER_A::DIV16), + 6 => Some(PRESCALER_A::DIV32), + 7 => Some(PRESCALER_A::DIV64), + 8 => Some(PRESCALER_A::DIV128), + 9 => Some(PRESCALER_A::DIV256), + 10 => Some(PRESCALER_A::DIV512), + 11 => Some(PRESCALER_A::DIV1024), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == PRESCALER_A::OFF + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == PRESCALER_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == PRESCALER_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == PRESCALER_A::DIV128 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV512`"] + #[inline(always)] + pub fn is_div512(&self) -> bool { + **self == PRESCALER_A::DIV512 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PRESCALER_A::DIV1024 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(PRESCALER_A::OFF) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV32) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV128) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/512"] + #[inline(always)] + pub fn div512(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV512) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 8)) | ((value as u16 & 0x0f) << 8); + self.w + } +} +#[doc = "Field `CLOCKSYNC` reader - Clock Read Synchronization Enable"] +pub struct CLOCKSYNC_R(crate::FieldReader); +impl CLOCKSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLOCKSYNC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLOCKSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLOCKSYNC` writer - Clock Read Synchronization Enable"] +pub struct CLOCKSYNC_W<'a> { + w: &'a mut W, +} +impl<'a> CLOCKSYNC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:3 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bit 6 - Clock Representation"] + #[inline(always)] + pub fn clkrep(&self) -> CLKREP_R { + CLKREP_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Clear on Match"] + #[inline(always)] + pub fn matchclr(&self) -> MATCHCLR_R { + MATCHCLR_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:11 - Prescaler"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 15 - Clock Read Synchronization Enable"] + #[inline(always)] + pub fn clocksync(&self) -> CLOCKSYNC_R { + CLOCKSYNC_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:3 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 6 - Clock Representation"] + #[inline(always)] + pub fn clkrep(&mut self) -> CLKREP_W { + CLKREP_W { w: self } + } + #[doc = "Bit 7 - Clear on Match"] + #[inline(always)] + pub fn matchclr(&mut self) -> MATCHCLR_W { + MATCHCLR_W { w: self } + } + #[doc = "Bits 8:11 - Prescaler"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Bit 15 - Clock Read Synchronization Enable"] + #[inline(always)] + pub fn clocksync(&mut self) -> CLOCKSYNC_W { + CLOCKSYNC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2 Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/rtc/mode2/dbgctrl.rs b/pac/atsamc21g/src/rtc/mode2/dbgctrl.rs new file mode 100644 index 000000000000..0383e70d0429 --- /dev/null +++ b/pac/atsamc21g/src/rtc/mode2/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Run During Debug"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Run During Debug"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/rtc/mode2/evctrl.rs b/pac/atsamc21g/src/rtc/mode2/evctrl.rs new file mode 100644 index 000000000000..17bc3da4a79e --- /dev/null +++ b/pac/atsamc21g/src/rtc/mode2/evctrl.rs @@ -0,0 +1,536 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PEREO0` reader - Periodic Interval 0 Event Output Enable"] +pub struct PEREO0_R(crate::FieldReader); +impl PEREO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO0` writer - Periodic Interval 0 Event Output Enable"] +pub struct PEREO0_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `PEREO1` reader - Periodic Interval 1 Event Output Enable"] +pub struct PEREO1_R(crate::FieldReader); +impl PEREO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO1` writer - Periodic Interval 1 Event Output Enable"] +pub struct PEREO1_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PEREO2` reader - Periodic Interval 2 Event Output Enable"] +pub struct PEREO2_R(crate::FieldReader); +impl PEREO2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO2` writer - Periodic Interval 2 Event Output Enable"] +pub struct PEREO2_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PEREO3` reader - Periodic Interval 3 Event Output Enable"] +pub struct PEREO3_R(crate::FieldReader); +impl PEREO3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO3` writer - Periodic Interval 3 Event Output Enable"] +pub struct PEREO3_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PEREO4` reader - Periodic Interval 4 Event Output Enable"] +pub struct PEREO4_R(crate::FieldReader); +impl PEREO4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO4` writer - Periodic Interval 4 Event Output Enable"] +pub struct PEREO4_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PEREO5` reader - Periodic Interval 5 Event Output Enable"] +pub struct PEREO5_R(crate::FieldReader); +impl PEREO5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO5` writer - Periodic Interval 5 Event Output Enable"] +pub struct PEREO5_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PEREO6` reader - Periodic Interval 6 Event Output Enable"] +pub struct PEREO6_R(crate::FieldReader); +impl PEREO6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO6` writer - Periodic Interval 6 Event Output Enable"] +pub struct PEREO6_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PEREO7` reader - Periodic Interval 7 Event Output Enable"] +pub struct PEREO7_R(crate::FieldReader); +impl PEREO7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO7` writer - Periodic Interval 7 Event Output Enable"] +pub struct PEREO7_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `ALARMEO0` reader - Alarm 0 Event Output Enable"] +pub struct ALARMEO0_R(crate::FieldReader); +impl ALARMEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALARMEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALARMEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALARMEO0` writer - Alarm 0 Event Output Enable"] +pub struct ALARMEO0_W<'a> { + w: &'a mut W, +} +impl<'a> ALARMEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `OVFEO` reader - Overflow Event Output Enable"] +pub struct OVFEO_R(crate::FieldReader); +impl OVFEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVFEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVFEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVFEO` writer - Overflow Event Output Enable"] +pub struct OVFEO_W<'a> { + w: &'a mut W, +} +impl<'a> OVFEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Event Output Enable"] + #[inline(always)] + pub fn pereo0(&self) -> PEREO0_R { + PEREO0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Event Output Enable"] + #[inline(always)] + pub fn pereo1(&self) -> PEREO1_R { + PEREO1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Event Output Enable"] + #[inline(always)] + pub fn pereo2(&self) -> PEREO2_R { + PEREO2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Event Output Enable"] + #[inline(always)] + pub fn pereo3(&self) -> PEREO3_R { + PEREO3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Event Output Enable"] + #[inline(always)] + pub fn pereo4(&self) -> PEREO4_R { + PEREO4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Event Output Enable"] + #[inline(always)] + pub fn pereo5(&self) -> PEREO5_R { + PEREO5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Event Output Enable"] + #[inline(always)] + pub fn pereo6(&self) -> PEREO6_R { + PEREO6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Event Output Enable"] + #[inline(always)] + pub fn pereo7(&self) -> PEREO7_R { + PEREO7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Alarm 0 Event Output Enable"] + #[inline(always)] + pub fn alarmeo0(&self) -> ALARMEO0_R { + ALARMEO0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&self) -> OVFEO_R { + OVFEO_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Event Output Enable"] + #[inline(always)] + pub fn pereo0(&mut self) -> PEREO0_W { + PEREO0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1 Event Output Enable"] + #[inline(always)] + pub fn pereo1(&mut self) -> PEREO1_W { + PEREO1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2 Event Output Enable"] + #[inline(always)] + pub fn pereo2(&mut self) -> PEREO2_W { + PEREO2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3 Event Output Enable"] + #[inline(always)] + pub fn pereo3(&mut self) -> PEREO3_W { + PEREO3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4 Event Output Enable"] + #[inline(always)] + pub fn pereo4(&mut self) -> PEREO4_W { + PEREO4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5 Event Output Enable"] + #[inline(always)] + pub fn pereo5(&mut self) -> PEREO5_W { + PEREO5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6 Event Output Enable"] + #[inline(always)] + pub fn pereo6(&mut self) -> PEREO6_W { + PEREO6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7 Event Output Enable"] + #[inline(always)] + pub fn pereo7(&mut self) -> PEREO7_W { + PEREO7_W { w: self } + } + #[doc = "Bit 8 - Alarm 0 Event Output Enable"] + #[inline(always)] + pub fn alarmeo0(&mut self) -> ALARMEO0_W { + ALARMEO0_W { w: self } + } + #[doc = "Bit 15 - Overflow Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&mut self) -> OVFEO_W { + OVFEO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2 Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/rtc/mode2/freqcorr.rs b/pac/atsamc21g/src/rtc/mode2/freqcorr.rs new file mode 100644 index 000000000000..043ba6f88eb2 --- /dev/null +++ b/pac/atsamc21g/src/rtc/mode2/freqcorr.rs @@ -0,0 +1,150 @@ +#[doc = "Register `FREQCORR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FREQCORR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `VALUE` reader - Correction Value"] +pub struct VALUE_R(crate::FieldReader); +impl VALUE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + VALUE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VALUE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VALUE` writer - Correction Value"] +pub struct VALUE_W<'a> { + w: &'a mut W, +} +impl<'a> VALUE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x7f) | (value as u8 & 0x7f); + self.w + } +} +#[doc = "Field `SIGN` reader - Correction Sign"] +pub struct SIGN_R(crate::FieldReader); +impl SIGN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SIGN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SIGN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SIGN` writer - Correction Sign"] +pub struct SIGN_W<'a> { + w: &'a mut W, +} +impl<'a> SIGN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bits 0:6 - Correction Value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bit 7 - Correction Sign"] + #[inline(always)] + pub fn sign(&self) -> SIGN_R { + SIGN_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:6 - Correction Value"] + #[inline(always)] + pub fn value(&mut self) -> VALUE_W { + VALUE_W { w: self } + } + #[doc = "Bit 7 - Correction Sign"] + #[inline(always)] + pub fn sign(&mut self) -> SIGN_W { + SIGN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Frequency Correction\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [freqcorr](index.html) module"] +pub struct FREQCORR_SPEC; +impl crate::RegisterSpec for FREQCORR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [freqcorr::R](R) reader structure"] +impl crate::Readable for FREQCORR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [freqcorr::W](W) writer structure"] +impl crate::Writable for FREQCORR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets FREQCORR to value 0"] +impl crate::Resettable for FREQCORR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/rtc/mode2/intenclr.rs b/pac/atsamc21g/src/rtc/mode2/intenclr.rs new file mode 100644 index 000000000000..84aa17f78a0e --- /dev/null +++ b/pac/atsamc21g/src/rtc/mode2/intenclr.rs @@ -0,0 +1,536 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER0` reader - Periodic Interval 0 Interrupt Enable"] +pub struct PER0_R(crate::FieldReader); +impl PER0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER0` writer - Periodic Interval 0 Interrupt Enable"] +pub struct PER0_W<'a> { + w: &'a mut W, +} +impl<'a> PER0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PER1` reader - Periodic Interval 1 Interrupt Enable"] +pub struct PER1_R(crate::FieldReader); +impl PER1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER1` writer - Periodic Interval 1 Interrupt Enable"] +pub struct PER1_W<'a> { + w: &'a mut W, +} +impl<'a> PER1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PER2` reader - Periodic Interval 2 Interrupt Enable"] +pub struct PER2_R(crate::FieldReader); +impl PER2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER2` writer - Periodic Interval 2 Interrupt Enable"] +pub struct PER2_W<'a> { + w: &'a mut W, +} +impl<'a> PER2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PER3` reader - Periodic Interval 3 Interrupt Enable"] +pub struct PER3_R(crate::FieldReader); +impl PER3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER3` writer - Periodic Interval 3 Interrupt Enable"] +pub struct PER3_W<'a> { + w: &'a mut W, +} +impl<'a> PER3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PER4` reader - Periodic Interval 4 Interrupt Enable"] +pub struct PER4_R(crate::FieldReader); +impl PER4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER4` writer - Periodic Interval 4 Interrupt Enable"] +pub struct PER4_W<'a> { + w: &'a mut W, +} +impl<'a> PER4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PER5` reader - Periodic Interval 5 Interrupt Enable"] +pub struct PER5_R(crate::FieldReader); +impl PER5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER5` writer - Periodic Interval 5 Interrupt Enable"] +pub struct PER5_W<'a> { + w: &'a mut W, +} +impl<'a> PER5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PER6` reader - Periodic Interval 6 Interrupt Enable"] +pub struct PER6_R(crate::FieldReader); +impl PER6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER6` writer - Periodic Interval 6 Interrupt Enable"] +pub struct PER6_W<'a> { + w: &'a mut W, +} +impl<'a> PER6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PER7` reader - Periodic Interval 7 Interrupt Enable"] +pub struct PER7_R(crate::FieldReader); +impl PER7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER7` writer - Periodic Interval 7 Interrupt Enable"] +pub struct PER7_W<'a> { + w: &'a mut W, +} +impl<'a> PER7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `ALARM0` reader - Alarm 0 Interrupt Enable"] +pub struct ALARM0_R(crate::FieldReader); +impl ALARM0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALARM0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALARM0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALARM0` writer - Alarm 0 Interrupt Enable"] +pub struct ALARM0_W<'a> { + w: &'a mut W, +} +impl<'a> ALARM0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + pub fn per0(&self) -> PER0_R { + PER0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + pub fn per1(&self) -> PER1_R { + PER1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + pub fn per2(&self) -> PER2_R { + PER2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + pub fn per3(&self) -> PER3_R { + PER3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + pub fn per4(&self) -> PER4_R { + PER4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + pub fn per5(&self) -> PER5_R { + PER5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + pub fn per6(&self) -> PER6_R { + PER6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + pub fn per7(&self) -> PER7_R { + PER7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Alarm 0 Interrupt Enable"] + #[inline(always)] + pub fn alarm0(&self) -> ALARM0_R { + ALARM0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + pub fn per0(&mut self) -> PER0_W { + PER0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + pub fn per1(&mut self) -> PER1_W { + PER1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + pub fn per2(&mut self) -> PER2_W { + PER2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + pub fn per3(&mut self) -> PER3_W { + PER3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + pub fn per4(&mut self) -> PER4_W { + PER4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + pub fn per5(&mut self) -> PER5_W { + PER5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + pub fn per6(&mut self) -> PER6_W { + PER6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + pub fn per7(&mut self) -> PER7_W { + PER7_W { w: self } + } + #[doc = "Bit 8 - Alarm 0 Interrupt Enable"] + #[inline(always)] + pub fn alarm0(&mut self) -> ALARM0_W { + ALARM0_W { w: self } + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2 Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/rtc/mode2/intenset.rs b/pac/atsamc21g/src/rtc/mode2/intenset.rs new file mode 100644 index 000000000000..a41687fa1ee5 --- /dev/null +++ b/pac/atsamc21g/src/rtc/mode2/intenset.rs @@ -0,0 +1,536 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER0` reader - Periodic Interval 0 Enable"] +pub struct PER0_R(crate::FieldReader); +impl PER0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER0` writer - Periodic Interval 0 Enable"] +pub struct PER0_W<'a> { + w: &'a mut W, +} +impl<'a> PER0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PER1` reader - Periodic Interval 1 Enable"] +pub struct PER1_R(crate::FieldReader); +impl PER1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER1` writer - Periodic Interval 1 Enable"] +pub struct PER1_W<'a> { + w: &'a mut W, +} +impl<'a> PER1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PER2` reader - Periodic Interval 2 Enable"] +pub struct PER2_R(crate::FieldReader); +impl PER2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER2` writer - Periodic Interval 2 Enable"] +pub struct PER2_W<'a> { + w: &'a mut W, +} +impl<'a> PER2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PER3` reader - Periodic Interval 3 Enable"] +pub struct PER3_R(crate::FieldReader); +impl PER3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER3` writer - Periodic Interval 3 Enable"] +pub struct PER3_W<'a> { + w: &'a mut W, +} +impl<'a> PER3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PER4` reader - Periodic Interval 4 Enable"] +pub struct PER4_R(crate::FieldReader); +impl PER4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER4` writer - Periodic Interval 4 Enable"] +pub struct PER4_W<'a> { + w: &'a mut W, +} +impl<'a> PER4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PER5` reader - Periodic Interval 5 Enable"] +pub struct PER5_R(crate::FieldReader); +impl PER5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER5` writer - Periodic Interval 5 Enable"] +pub struct PER5_W<'a> { + w: &'a mut W, +} +impl<'a> PER5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PER6` reader - Periodic Interval 6 Enable"] +pub struct PER6_R(crate::FieldReader); +impl PER6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER6` writer - Periodic Interval 6 Enable"] +pub struct PER6_W<'a> { + w: &'a mut W, +} +impl<'a> PER6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PER7` reader - Periodic Interval 7 Enable"] +pub struct PER7_R(crate::FieldReader); +impl PER7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER7` writer - Periodic Interval 7 Enable"] +pub struct PER7_W<'a> { + w: &'a mut W, +} +impl<'a> PER7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `ALARM0` reader - Alarm 0 Interrupt Enable"] +pub struct ALARM0_R(crate::FieldReader); +impl ALARM0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALARM0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALARM0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALARM0` writer - Alarm 0 Interrupt Enable"] +pub struct ALARM0_W<'a> { + w: &'a mut W, +} +impl<'a> ALARM0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Enable"] + #[inline(always)] + pub fn per0(&self) -> PER0_R { + PER0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Enable"] + #[inline(always)] + pub fn per1(&self) -> PER1_R { + PER1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Enable"] + #[inline(always)] + pub fn per2(&self) -> PER2_R { + PER2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Enable"] + #[inline(always)] + pub fn per3(&self) -> PER3_R { + PER3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Enable"] + #[inline(always)] + pub fn per4(&self) -> PER4_R { + PER4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Enable"] + #[inline(always)] + pub fn per5(&self) -> PER5_R { + PER5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Enable"] + #[inline(always)] + pub fn per6(&self) -> PER6_R { + PER6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Enable"] + #[inline(always)] + pub fn per7(&self) -> PER7_R { + PER7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Alarm 0 Interrupt Enable"] + #[inline(always)] + pub fn alarm0(&self) -> ALARM0_R { + ALARM0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Enable"] + #[inline(always)] + pub fn per0(&mut self) -> PER0_W { + PER0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1 Enable"] + #[inline(always)] + pub fn per1(&mut self) -> PER1_W { + PER1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2 Enable"] + #[inline(always)] + pub fn per2(&mut self) -> PER2_W { + PER2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3 Enable"] + #[inline(always)] + pub fn per3(&mut self) -> PER3_W { + PER3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4 Enable"] + #[inline(always)] + pub fn per4(&mut self) -> PER4_W { + PER4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5 Enable"] + #[inline(always)] + pub fn per5(&mut self) -> PER5_W { + PER5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6 Enable"] + #[inline(always)] + pub fn per6(&mut self) -> PER6_W { + PER6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7 Enable"] + #[inline(always)] + pub fn per7(&mut self) -> PER7_W { + PER7_W { w: self } + } + #[doc = "Bit 8 - Alarm 0 Interrupt Enable"] + #[inline(always)] + pub fn alarm0(&mut self) -> ALARM0_W { + ALARM0_W { w: self } + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2 Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/rtc/mode2/intflag.rs b/pac/atsamc21g/src/rtc/mode2/intflag.rs new file mode 100644 index 000000000000..8de0f3efd1d0 --- /dev/null +++ b/pac/atsamc21g/src/rtc/mode2/intflag.rs @@ -0,0 +1,536 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER0` reader - Periodic Interval 0"] +pub struct PER0_R(crate::FieldReader); +impl PER0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER0` writer - Periodic Interval 0"] +pub struct PER0_W<'a> { + w: &'a mut W, +} +impl<'a> PER0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PER1` reader - Periodic Interval 1"] +pub struct PER1_R(crate::FieldReader); +impl PER1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER1` writer - Periodic Interval 1"] +pub struct PER1_W<'a> { + w: &'a mut W, +} +impl<'a> PER1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PER2` reader - Periodic Interval 2"] +pub struct PER2_R(crate::FieldReader); +impl PER2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER2` writer - Periodic Interval 2"] +pub struct PER2_W<'a> { + w: &'a mut W, +} +impl<'a> PER2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PER3` reader - Periodic Interval 3"] +pub struct PER3_R(crate::FieldReader); +impl PER3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER3` writer - Periodic Interval 3"] +pub struct PER3_W<'a> { + w: &'a mut W, +} +impl<'a> PER3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PER4` reader - Periodic Interval 4"] +pub struct PER4_R(crate::FieldReader); +impl PER4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER4` writer - Periodic Interval 4"] +pub struct PER4_W<'a> { + w: &'a mut W, +} +impl<'a> PER4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PER5` reader - Periodic Interval 5"] +pub struct PER5_R(crate::FieldReader); +impl PER5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER5` writer - Periodic Interval 5"] +pub struct PER5_W<'a> { + w: &'a mut W, +} +impl<'a> PER5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PER6` reader - Periodic Interval 6"] +pub struct PER6_R(crate::FieldReader); +impl PER6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER6` writer - Periodic Interval 6"] +pub struct PER6_W<'a> { + w: &'a mut W, +} +impl<'a> PER6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PER7` reader - Periodic Interval 7"] +pub struct PER7_R(crate::FieldReader); +impl PER7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER7` writer - Periodic Interval 7"] +pub struct PER7_W<'a> { + w: &'a mut W, +} +impl<'a> PER7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `ALARM0` reader - Alarm 0"] +pub struct ALARM0_R(crate::FieldReader); +impl ALARM0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALARM0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALARM0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALARM0` writer - Alarm 0"] +pub struct ALARM0_W<'a> { + w: &'a mut W, +} +impl<'a> ALARM0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0"] + #[inline(always)] + pub fn per0(&self) -> PER0_R { + PER0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1"] + #[inline(always)] + pub fn per1(&self) -> PER1_R { + PER1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2"] + #[inline(always)] + pub fn per2(&self) -> PER2_R { + PER2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3"] + #[inline(always)] + pub fn per3(&self) -> PER3_R { + PER3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4"] + #[inline(always)] + pub fn per4(&self) -> PER4_R { + PER4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5"] + #[inline(always)] + pub fn per5(&self) -> PER5_R { + PER5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6"] + #[inline(always)] + pub fn per6(&self) -> PER6_R { + PER6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7"] + #[inline(always)] + pub fn per7(&self) -> PER7_R { + PER7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Alarm 0"] + #[inline(always)] + pub fn alarm0(&self) -> ALARM0_R { + ALARM0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0"] + #[inline(always)] + pub fn per0(&mut self) -> PER0_W { + PER0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1"] + #[inline(always)] + pub fn per1(&mut self) -> PER1_W { + PER1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2"] + #[inline(always)] + pub fn per2(&mut self) -> PER2_W { + PER2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3"] + #[inline(always)] + pub fn per3(&mut self) -> PER3_W { + PER3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4"] + #[inline(always)] + pub fn per4(&mut self) -> PER4_W { + PER4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5"] + #[inline(always)] + pub fn per5(&mut self) -> PER5_W { + PER5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6"] + #[inline(always)] + pub fn per6(&mut self) -> PER6_W { + PER6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7"] + #[inline(always)] + pub fn per7(&mut self) -> PER7_W { + PER7_W { w: self } + } + #[doc = "Bit 8 - Alarm 0"] + #[inline(always)] + pub fn alarm0(&mut self) -> ALARM0_W { + ALARM0_W { w: self } + } + #[doc = "Bit 15 - Overflow"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2 Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/rtc/mode2/mask.rs b/pac/atsamc21g/src/rtc/mode2/mask.rs new file mode 100644 index 000000000000..53e0bb491a62 --- /dev/null +++ b/pac/atsamc21g/src/rtc/mode2/mask.rs @@ -0,0 +1,217 @@ +#[doc = "Register `MASK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MASK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Alarm Mask Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SEL_A { + #[doc = "0: Alarm Disabled"] + OFF = 0, + #[doc = "1: Match seconds only"] + SS = 1, + #[doc = "2: Match seconds and minutes only"] + MMSS = 2, + #[doc = "3: Match seconds, minutes, and hours only"] + HHMMSS = 3, + #[doc = "4: Match seconds, minutes, hours, and days only"] + DDHHMMSS = 4, + #[doc = "5: Match seconds, minutes, hours, days, and months only"] + MMDDHHMMSS = 5, + #[doc = "6: Match seconds, minutes, hours, days, months, and years"] + YYMMDDHHMMSS = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `SEL` reader - Alarm Mask Selection"] +pub struct SEL_R(crate::FieldReader); +impl SEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEL_A::OFF), + 1 => Some(SEL_A::SS), + 2 => Some(SEL_A::MMSS), + 3 => Some(SEL_A::HHMMSS), + 4 => Some(SEL_A::DDHHMMSS), + 5 => Some(SEL_A::MMDDHHMMSS), + 6 => Some(SEL_A::YYMMDDHHMMSS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == SEL_A::OFF + } + #[doc = "Checks if the value of the field is `SS`"] + #[inline(always)] + pub fn is_ss(&self) -> bool { + **self == SEL_A::SS + } + #[doc = "Checks if the value of the field is `MMSS`"] + #[inline(always)] + pub fn is_mmss(&self) -> bool { + **self == SEL_A::MMSS + } + #[doc = "Checks if the value of the field is `HHMMSS`"] + #[inline(always)] + pub fn is_hhmmss(&self) -> bool { + **self == SEL_A::HHMMSS + } + #[doc = "Checks if the value of the field is `DDHHMMSS`"] + #[inline(always)] + pub fn is_ddhhmmss(&self) -> bool { + **self == SEL_A::DDHHMMSS + } + #[doc = "Checks if the value of the field is `MMDDHHMMSS`"] + #[inline(always)] + pub fn is_mmddhhmmss(&self) -> bool { + **self == SEL_A::MMDDHHMMSS + } + #[doc = "Checks if the value of the field is `YYMMDDHHMMSS`"] + #[inline(always)] + pub fn is_yymmddhhmmss(&self) -> bool { + **self == SEL_A::YYMMDDHHMMSS + } +} +impl core::ops::Deref for SEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEL` writer - Alarm Mask Selection"] +pub struct SEL_W<'a> { + w: &'a mut W, +} +impl<'a> SEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SEL_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Alarm Disabled"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(SEL_A::OFF) + } + #[doc = "Match seconds only"] + #[inline(always)] + pub fn ss(self) -> &'a mut W { + self.variant(SEL_A::SS) + } + #[doc = "Match seconds and minutes only"] + #[inline(always)] + pub fn mmss(self) -> &'a mut W { + self.variant(SEL_A::MMSS) + } + #[doc = "Match seconds, minutes, and hours only"] + #[inline(always)] + pub fn hhmmss(self) -> &'a mut W { + self.variant(SEL_A::HHMMSS) + } + #[doc = "Match seconds, minutes, hours, and days only"] + #[inline(always)] + pub fn ddhhmmss(self) -> &'a mut W { + self.variant(SEL_A::DDHHMMSS) + } + #[doc = "Match seconds, minutes, hours, days, and months only"] + #[inline(always)] + pub fn mmddhhmmss(self) -> &'a mut W { + self.variant(SEL_A::MMDDHHMMSS) + } + #[doc = "Match seconds, minutes, hours, days, months, and years"] + #[inline(always)] + pub fn yymmddhhmmss(self) -> &'a mut W { + self.variant(SEL_A::YYMMDDHHMMSS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Alarm Mask Selection"] + #[inline(always)] + pub fn sel(&self) -> SEL_R { + SEL_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Alarm Mask Selection"] + #[inline(always)] + pub fn sel(&mut self) -> SEL_W { + SEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2_ALARM Alarm n Mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mask](index.html) module"] +pub struct MASK_SPEC; +impl crate::RegisterSpec for MASK_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [mask::R](R) reader structure"] +impl crate::Readable for MASK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [mask::W](W) writer structure"] +impl crate::Writable for MASK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets MASK to value 0"] +impl crate::Resettable for MASK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/rtc/mode2/syncbusy.rs b/pac/atsamc21g/src/rtc/mode2/syncbusy.rs new file mode 100644 index 000000000000..b517ee5ae8b2 --- /dev/null +++ b/pac/atsamc21g/src/rtc/mode2/syncbusy.rs @@ -0,0 +1,173 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Bit Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - Enable Bit Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FREQCORR` reader - FREQCORR Register Busy"] +pub struct FREQCORR_R(crate::FieldReader); +impl FREQCORR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FREQCORR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FREQCORR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLOCK` reader - CLOCK Register Busy"] +pub struct CLOCK_R(crate::FieldReader); +impl CLOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALARM0` reader - ALARM 0 Register Busy"] +pub struct ALARM0_R(crate::FieldReader); +impl ALARM0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALARM0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALARM0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MASK0` reader - MASK 0 Register Busy"] +pub struct MASK0_R(crate::FieldReader); +impl MASK0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MASK0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MASK0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLOCKSYNC` reader - Clock Read Synchronization Enable Bit Busy"] +pub struct CLOCKSYNC_R(crate::FieldReader); +impl CLOCKSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLOCKSYNC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLOCKSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Bit Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable Bit Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - FREQCORR Register Busy"] + #[inline(always)] + pub fn freqcorr(&self) -> FREQCORR_R { + FREQCORR_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - CLOCK Register Busy"] + #[inline(always)] + pub fn clock(&self) -> CLOCK_R { + CLOCK_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 5 - ALARM 0 Register Busy"] + #[inline(always)] + pub fn alarm0(&self) -> ALARM0_R { + ALARM0_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 11 - MASK 0 Register Busy"] + #[inline(always)] + pub fn mask0(&self) -> MASK0_R { + MASK0_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 15 - Clock Read Synchronization Enable Bit Busy"] + #[inline(always)] + pub fn clocksync(&self) -> CLOCKSYNC_R { + CLOCKSYNC_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +#[doc = "MODE2 Synchronization Busy Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sdadc.rs b/pac/atsamc21g/src/sdadc.rs new file mode 100644 index 000000000000..11e926a1d2de --- /dev/null +++ b/pac/atsamc21g/src/sdadc.rs @@ -0,0 +1,140 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + #[doc = "0x01 - Reference Control"] + pub refctrl: crate::Reg, + #[doc = "0x02 - Control B"] + pub ctrlb: crate::Reg, + #[doc = "0x04 - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x05 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x06 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x07 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x08 - Sequence Status"] + pub seqstatus: crate::Reg, + #[doc = "0x09 - Input Control"] + pub inputctrl: crate::Reg, + #[doc = "0x0a - Control C"] + pub ctrlc: crate::Reg, + #[doc = "0x0b - Window Monitor Control"] + pub winctrl: crate::Reg, + #[doc = "0x0c - Window Monitor Lower Threshold"] + pub winlt: crate::Reg, + #[doc = "0x10 - Window Monitor Upper Threshold"] + pub winut: crate::Reg, + #[doc = "0x14 - Offset Correction"] + pub offsetcorr: crate::Reg, + #[doc = "0x18 - Gain Correction"] + pub gaincorr: crate::Reg, + #[doc = "0x1a - Shift Correction"] + pub shiftcorr: crate::Reg, + _reserved16: [u8; 0x01], + #[doc = "0x1c - Software Trigger"] + pub swtrig: crate::Reg, + _reserved17: [u8; 0x03], + #[doc = "0x20 - Synchronization Busy"] + pub syncbusy: crate::Reg, + #[doc = "0x24 - Result"] + pub result: crate::Reg, + #[doc = "0x28 - Sequence Control"] + pub seqctrl: crate::Reg, + _reserved20: [u8; 0x03], + #[doc = "0x2c - Analog Control"] + pub anactrl: crate::Reg, + _reserved21: [u8; 0x01], + #[doc = "0x2e - Debug Control"] + pub dbgctrl: crate::Reg, +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "REFCTRL register accessor: an alias for `Reg`"] +pub type REFCTRL = crate::Reg; +#[doc = "Reference Control"] +pub mod refctrl; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "Control B"] +pub mod ctrlb; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "SEQSTATUS register accessor: an alias for `Reg`"] +pub type SEQSTATUS = crate::Reg; +#[doc = "Sequence Status"] +pub mod seqstatus; +#[doc = "INPUTCTRL register accessor: an alias for `Reg`"] +pub type INPUTCTRL = crate::Reg; +#[doc = "Input Control"] +pub mod inputctrl; +#[doc = "CTRLC register accessor: an alias for `Reg`"] +pub type CTRLC = crate::Reg; +#[doc = "Control C"] +pub mod ctrlc; +#[doc = "WINCTRL register accessor: an alias for `Reg`"] +pub type WINCTRL = crate::Reg; +#[doc = "Window Monitor Control"] +pub mod winctrl; +#[doc = "WINLT register accessor: an alias for `Reg`"] +pub type WINLT = crate::Reg; +#[doc = "Window Monitor Lower Threshold"] +pub mod winlt; +#[doc = "WINUT register accessor: an alias for `Reg`"] +pub type WINUT = crate::Reg; +#[doc = "Window Monitor Upper Threshold"] +pub mod winut; +#[doc = "OFFSETCORR register accessor: an alias for `Reg`"] +pub type OFFSETCORR = crate::Reg; +#[doc = "Offset Correction"] +pub mod offsetcorr; +#[doc = "GAINCORR register accessor: an alias for `Reg`"] +pub type GAINCORR = crate::Reg; +#[doc = "Gain Correction"] +pub mod gaincorr; +#[doc = "SHIFTCORR register accessor: an alias for `Reg`"] +pub type SHIFTCORR = crate::Reg; +#[doc = "Shift Correction"] +pub mod shiftcorr; +#[doc = "SWTRIG register accessor: an alias for `Reg`"] +pub type SWTRIG = crate::Reg; +#[doc = "Software Trigger"] +pub mod swtrig; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Busy"] +pub mod syncbusy; +#[doc = "RESULT register accessor: an alias for `Reg`"] +pub type RESULT = crate::Reg; +#[doc = "Result"] +pub mod result; +#[doc = "SEQCTRL register accessor: an alias for `Reg`"] +pub type SEQCTRL = crate::Reg; +#[doc = "Sequence Control"] +pub mod seqctrl; +#[doc = "ANACTRL register accessor: an alias for `Reg`"] +pub type ANACTRL = crate::Reg; +#[doc = "Analog Control"] +pub mod anactrl; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; diff --git a/pac/atsamc21g/src/sdadc/anactrl.rs b/pac/atsamc21g/src/sdadc/anactrl.rs new file mode 100644 index 000000000000..3261811c0348 --- /dev/null +++ b/pac/atsamc21g/src/sdadc/anactrl.rs @@ -0,0 +1,197 @@ +#[doc = "Register `ANACTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ANACTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CTRSDADC` reader - SDADC Control"] +pub struct CTRSDADC_R(crate::FieldReader); +impl CTRSDADC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CTRSDADC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRSDADC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRSDADC` writer - SDADC Control"] +pub struct CTRSDADC_W<'a> { + w: &'a mut W, +} +impl<'a> CTRSDADC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u8 & 0x3f); + self.w + } +} +#[doc = "Field `ONCHOP` reader - Chopper"] +pub struct ONCHOP_R(crate::FieldReader); +impl ONCHOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONCHOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONCHOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONCHOP` writer - Chopper"] +pub struct ONCHOP_W<'a> { + w: &'a mut W, +} +impl<'a> ONCHOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +#[doc = "Field `BUFTEST` reader - BUFTEST"] +pub struct BUFTEST_R(crate::FieldReader); +impl BUFTEST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUFTEST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUFTEST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUFTEST` writer - BUFTEST"] +pub struct BUFTEST_W<'a> { + w: &'a mut W, +} +impl<'a> BUFTEST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - SDADC Control"] + #[inline(always)] + pub fn ctrsdadc(&self) -> CTRSDADC_R { + CTRSDADC_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - Chopper"] + #[inline(always)] + pub fn onchop(&self) -> ONCHOP_R { + ONCHOP_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - BUFTEST"] + #[inline(always)] + pub fn buftest(&self) -> BUFTEST_R { + BUFTEST_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:5 - SDADC Control"] + #[inline(always)] + pub fn ctrsdadc(&mut self) -> CTRSDADC_W { + CTRSDADC_W { w: self } + } + #[doc = "Bit 6 - Chopper"] + #[inline(always)] + pub fn onchop(&mut self) -> ONCHOP_W { + ONCHOP_W { w: self } + } + #[doc = "Bit 7 - BUFTEST"] + #[inline(always)] + pub fn buftest(&mut self) -> BUFTEST_W { + BUFTEST_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Analog Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [anactrl](index.html) module"] +pub struct ANACTRL_SPEC; +impl crate::RegisterSpec for ANACTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [anactrl::R](R) reader structure"] +impl crate::Readable for ANACTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [anactrl::W](W) writer structure"] +impl crate::Writable for ANACTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ANACTRL to value 0"] +impl crate::Resettable for ANACTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sdadc/ctrla.rs b/pac/atsamc21g/src/sdadc/ctrla.rs new file mode 100644 index 000000000000..8fccdcb93995 --- /dev/null +++ b/pac/atsamc21g/src/sdadc/ctrla.rs @@ -0,0 +1,254 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - On Demand Control"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - On Demand Control"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sdadc/ctrlb.rs b/pac/atsamc21g/src/sdadc/ctrlb.rs new file mode 100644 index 000000000000..ee0dce613bc4 --- /dev/null +++ b/pac/atsamc21g/src/sdadc/ctrlb.rs @@ -0,0 +1,392 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Prescaler Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: Peripheral clock divided by 2"] + DIV2 = 0, + #[doc = "1: Peripheral clock divided by 4"] + DIV4 = 1, + #[doc = "2: Peripheral clock divided by 8"] + DIV8 = 2, + #[doc = "3: Peripheral clock divided by 16"] + DIV16 = 3, + #[doc = "4: Peripheral clock divided by 32"] + DIV32 = 4, + #[doc = "5: Peripheral clock divided by 64"] + DIV64 = 5, + #[doc = "6: Peripheral clock divided by 128"] + DIV128 = 6, + #[doc = "7: Peripheral clock divided by 256"] + DIV256 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler Configuration"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCALER_A::DIV2), + 1 => Some(PRESCALER_A::DIV4), + 2 => Some(PRESCALER_A::DIV8), + 3 => Some(PRESCALER_A::DIV16), + 4 => Some(PRESCALER_A::DIV32), + 5 => Some(PRESCALER_A::DIV64), + 6 => Some(PRESCALER_A::DIV128), + 7 => Some(PRESCALER_A::DIV256), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == PRESCALER_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == PRESCALER_A::DIV128 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler Configuration"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Peripheral clock divided by 2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "Peripheral clock divided by 4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "Peripheral clock divided by 8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "Peripheral clock divided by 16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "Peripheral clock divided by 32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV32) + } + #[doc = "Peripheral clock divided by 64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "Peripheral clock divided by 128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV128) + } + #[doc = "Peripheral clock divided by 256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u16 & 0xff); + self.w + } +} +#[doc = "Over Sampling Ratio\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum OSR_A { + #[doc = "0: Over Sampling Ratio is 64"] + OSR64 = 0, + #[doc = "1: Over Sampling Ratio is 128"] + OSR128 = 1, + #[doc = "2: Over Sampling Ratio is 256"] + OSR256 = 2, + #[doc = "3: Over Sampling Ratio is 512"] + OSR512 = 3, + #[doc = "4: Over Sampling Ratio is 1024"] + OSR1024 = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: OSR_A) -> Self { + variant as _ + } +} +#[doc = "Field `OSR` reader - Over Sampling Ratio"] +pub struct OSR_R(crate::FieldReader); +impl OSR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + OSR_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(OSR_A::OSR64), + 1 => Some(OSR_A::OSR128), + 2 => Some(OSR_A::OSR256), + 3 => Some(OSR_A::OSR512), + 4 => Some(OSR_A::OSR1024), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OSR64`"] + #[inline(always)] + pub fn is_osr64(&self) -> bool { + **self == OSR_A::OSR64 + } + #[doc = "Checks if the value of the field is `OSR128`"] + #[inline(always)] + pub fn is_osr128(&self) -> bool { + **self == OSR_A::OSR128 + } + #[doc = "Checks if the value of the field is `OSR256`"] + #[inline(always)] + pub fn is_osr256(&self) -> bool { + **self == OSR_A::OSR256 + } + #[doc = "Checks if the value of the field is `OSR512`"] + #[inline(always)] + pub fn is_osr512(&self) -> bool { + **self == OSR_A::OSR512 + } + #[doc = "Checks if the value of the field is `OSR1024`"] + #[inline(always)] + pub fn is_osr1024(&self) -> bool { + **self == OSR_A::OSR1024 + } +} +impl core::ops::Deref for OSR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSR` writer - Over Sampling Ratio"] +pub struct OSR_W<'a> { + w: &'a mut W, +} +impl<'a> OSR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: OSR_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Over Sampling Ratio is 64"] + #[inline(always)] + pub fn osr64(self) -> &'a mut W { + self.variant(OSR_A::OSR64) + } + #[doc = "Over Sampling Ratio is 128"] + #[inline(always)] + pub fn osr128(self) -> &'a mut W { + self.variant(OSR_A::OSR128) + } + #[doc = "Over Sampling Ratio is 256"] + #[inline(always)] + pub fn osr256(self) -> &'a mut W { + self.variant(OSR_A::OSR256) + } + #[doc = "Over Sampling Ratio is 512"] + #[inline(always)] + pub fn osr512(self) -> &'a mut W { + self.variant(OSR_A::OSR512) + } + #[doc = "Over Sampling Ratio is 1024"] + #[inline(always)] + pub fn osr1024(self) -> &'a mut W { + self.variant(OSR_A::OSR1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u16 & 0x07) << 8); + self.w + } +} +#[doc = "Field `SKPCNT` reader - Skip Sample Count"] +pub struct SKPCNT_R(crate::FieldReader); +impl SKPCNT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SKPCNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SKPCNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SKPCNT` writer - Skip Sample Count"] +pub struct SKPCNT_W<'a> { + w: &'a mut W, +} +impl<'a> SKPCNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 12)) | ((value as u16 & 0x0f) << 12); + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Prescaler Configuration"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:10 - Over Sampling Ratio"] + #[inline(always)] + pub fn osr(&self) -> OSR_R { + OSR_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bits 12:15 - Skip Sample Count"] + #[inline(always)] + pub fn skpcnt(&self) -> SKPCNT_R { + SKPCNT_R::new(((self.bits >> 12) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Prescaler Configuration"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Bits 8:10 - Over Sampling Ratio"] + #[inline(always)] + pub fn osr(&mut self) -> OSR_W { + OSR_W { w: self } + } + #[doc = "Bits 12:15 - Skip Sample Count"] + #[inline(always)] + pub fn skpcnt(&mut self) -> SKPCNT_W { + SKPCNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0x2000"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x2000 + } +} diff --git a/pac/atsamc21g/src/sdadc/ctrlc.rs b/pac/atsamc21g/src/sdadc/ctrlc.rs new file mode 100644 index 000000000000..320cfe4ec4aa --- /dev/null +++ b/pac/atsamc21g/src/sdadc/ctrlc.rs @@ -0,0 +1,113 @@ +#[doc = "Register `CTRLC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FREERUN` reader - Free Running Mode"] +pub struct FREERUN_R(crate::FieldReader); +impl FREERUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FREERUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FREERUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FREERUN` writer - Free Running Mode"] +pub struct FREERUN_W<'a> { + w: &'a mut W, +} +impl<'a> FREERUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Free Running Mode"] + #[inline(always)] + pub fn freerun(&self) -> FREERUN_R { + FREERUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Free Running Mode"] + #[inline(always)] + pub fn freerun(&mut self) -> FREERUN_W { + FREERUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control C\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlc](index.html) module"] +pub struct CTRLC_SPEC; +impl crate::RegisterSpec for CTRLC_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlc::R](R) reader structure"] +impl crate::Readable for CTRLC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlc::W](W) writer structure"] +impl crate::Writable for CTRLC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLC to value 0"] +impl crate::Resettable for CTRLC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sdadc/dbgctrl.rs b/pac/atsamc21g/src/sdadc/dbgctrl.rs new file mode 100644 index 000000000000..53636eb2b339 --- /dev/null +++ b/pac/atsamc21g/src/sdadc/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Debug Run"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Debug Run"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sdadc/evctrl.rs b/pac/atsamc21g/src/sdadc/evctrl.rs new file mode 100644 index 000000000000..2c50a979c544 --- /dev/null +++ b/pac/atsamc21g/src/sdadc/evctrl.rs @@ -0,0 +1,348 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FLUSHEI` reader - Flush Event Input Enable"] +pub struct FLUSHEI_R(crate::FieldReader); +impl FLUSHEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FLUSHEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FLUSHEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLUSHEI` writer - Flush Event Input Enable"] +pub struct FLUSHEI_W<'a> { + w: &'a mut W, +} +impl<'a> FLUSHEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `STARTEI` reader - Start Conversion Event Input Enable"] +pub struct STARTEI_R(crate::FieldReader); +impl STARTEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STARTEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STARTEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STARTEI` writer - Start Conversion Event Input Enable"] +pub struct STARTEI_W<'a> { + w: &'a mut W, +} +impl<'a> STARTEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `FLUSHINV` reader - Flush Event Invert Enable"] +pub struct FLUSHINV_R(crate::FieldReader); +impl FLUSHINV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FLUSHINV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FLUSHINV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLUSHINV` writer - Flush Event Invert Enable"] +pub struct FLUSHINV_W<'a> { + w: &'a mut W, +} +impl<'a> FLUSHINV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `STARTINV` reader - Satrt Event Invert Enable"] +pub struct STARTINV_R(crate::FieldReader); +impl STARTINV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STARTINV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STARTINV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STARTINV` writer - Satrt Event Invert Enable"] +pub struct STARTINV_W<'a> { + w: &'a mut W, +} +impl<'a> STARTINV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `RESRDYEO` reader - Result Ready Event Out"] +pub struct RESRDYEO_R(crate::FieldReader); +impl RESRDYEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESRDYEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESRDYEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESRDYEO` writer - Result Ready Event Out"] +pub struct RESRDYEO_W<'a> { + w: &'a mut W, +} +impl<'a> RESRDYEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `WINMONEO` reader - Window Monitor Event Out"] +pub struct WINMONEO_R(crate::FieldReader); +impl WINMONEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINMONEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINMONEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMONEO` writer - Window Monitor Event Out"] +pub struct WINMONEO_W<'a> { + w: &'a mut W, +} +impl<'a> WINMONEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Flush Event Input Enable"] + #[inline(always)] + pub fn flushei(&self) -> FLUSHEI_R { + FLUSHEI_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Start Conversion Event Input Enable"] + #[inline(always)] + pub fn startei(&self) -> STARTEI_R { + STARTEI_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Flush Event Invert Enable"] + #[inline(always)] + pub fn flushinv(&self) -> FLUSHINV_R { + FLUSHINV_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Satrt Event Invert Enable"] + #[inline(always)] + pub fn startinv(&self) -> STARTINV_R { + STARTINV_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Result Ready Event Out"] + #[inline(always)] + pub fn resrdyeo(&self) -> RESRDYEO_R { + RESRDYEO_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Window Monitor Event Out"] + #[inline(always)] + pub fn winmoneo(&self) -> WINMONEO_R { + WINMONEO_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Flush Event Input Enable"] + #[inline(always)] + pub fn flushei(&mut self) -> FLUSHEI_W { + FLUSHEI_W { w: self } + } + #[doc = "Bit 1 - Start Conversion Event Input Enable"] + #[inline(always)] + pub fn startei(&mut self) -> STARTEI_W { + STARTEI_W { w: self } + } + #[doc = "Bit 2 - Flush Event Invert Enable"] + #[inline(always)] + pub fn flushinv(&mut self) -> FLUSHINV_W { + FLUSHINV_W { w: self } + } + #[doc = "Bit 3 - Satrt Event Invert Enable"] + #[inline(always)] + pub fn startinv(&mut self) -> STARTINV_W { + STARTINV_W { w: self } + } + #[doc = "Bit 4 - Result Ready Event Out"] + #[inline(always)] + pub fn resrdyeo(&mut self) -> RESRDYEO_W { + RESRDYEO_W { w: self } + } + #[doc = "Bit 5 - Window Monitor Event Out"] + #[inline(always)] + pub fn winmoneo(&mut self) -> WINMONEO_W { + WINMONEO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sdadc/gaincorr.rs b/pac/atsamc21g/src/sdadc/gaincorr.rs new file mode 100644 index 000000000000..0f20d1cdef86 --- /dev/null +++ b/pac/atsamc21g/src/sdadc/gaincorr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `GAINCORR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GAINCORR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `GAINCORR` reader - Gain Correction Value"] +pub struct GAINCORR_R(crate::FieldReader); +impl GAINCORR_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + GAINCORR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GAINCORR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GAINCORR` writer - Gain Correction Value"] +pub struct GAINCORR_W<'a> { + w: &'a mut W, +} +impl<'a> GAINCORR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3fff) | (value as u16 & 0x3fff); + self.w + } +} +impl R { + #[doc = "Bits 0:13 - Gain Correction Value"] + #[inline(always)] + pub fn gaincorr(&self) -> GAINCORR_R { + GAINCORR_R::new((self.bits & 0x3fff) as u16) + } +} +impl W { + #[doc = "Bits 0:13 - Gain Correction Value"] + #[inline(always)] + pub fn gaincorr(&mut self) -> GAINCORR_W { + GAINCORR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Gain Correction\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gaincorr](index.html) module"] +pub struct GAINCORR_SPEC; +impl crate::RegisterSpec for GAINCORR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [gaincorr::R](R) reader structure"] +impl crate::Readable for GAINCORR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gaincorr::W](W) writer structure"] +impl crate::Writable for GAINCORR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets GAINCORR to value 0x01"] +impl crate::Resettable for GAINCORR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pac/atsamc21g/src/sdadc/inputctrl.rs b/pac/atsamc21g/src/sdadc/inputctrl.rs new file mode 100644 index 000000000000..e256cd3bbfc1 --- /dev/null +++ b/pac/atsamc21g/src/sdadc/inputctrl.rs @@ -0,0 +1,165 @@ +#[doc = "Register `INPUTCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INPUTCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "SDADC Input Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MUXSEL_A { + #[doc = "0: SDADC AIN0 Pin"] + AIN0 = 0, + #[doc = "1: SDADC AIN1 Pin"] + AIN1 = 1, + #[doc = "2: SDADC AIN2 Pin"] + AIN2 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MUXSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `MUXSEL` reader - SDADC Input Selection"] +pub struct MUXSEL_R(crate::FieldReader); +impl MUXSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MUXSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MUXSEL_A::AIN0), + 1 => Some(MUXSEL_A::AIN1), + 2 => Some(MUXSEL_A::AIN2), + _ => None, + } + } + #[doc = "Checks if the value of the field is `AIN0`"] + #[inline(always)] + pub fn is_ain0(&self) -> bool { + **self == MUXSEL_A::AIN0 + } + #[doc = "Checks if the value of the field is `AIN1`"] + #[inline(always)] + pub fn is_ain1(&self) -> bool { + **self == MUXSEL_A::AIN1 + } + #[doc = "Checks if the value of the field is `AIN2`"] + #[inline(always)] + pub fn is_ain2(&self) -> bool { + **self == MUXSEL_A::AIN2 + } +} +impl core::ops::Deref for MUXSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MUXSEL` writer - SDADC Input Selection"] +pub struct MUXSEL_W<'a> { + w: &'a mut W, +} +impl<'a> MUXSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MUXSEL_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "SDADC AIN0 Pin"] + #[inline(always)] + pub fn ain0(self) -> &'a mut W { + self.variant(MUXSEL_A::AIN0) + } + #[doc = "SDADC AIN1 Pin"] + #[inline(always)] + pub fn ain1(self) -> &'a mut W { + self.variant(MUXSEL_A::AIN1) + } + #[doc = "SDADC AIN2 Pin"] + #[inline(always)] + pub fn ain2(self) -> &'a mut W { + self.variant(MUXSEL_A::AIN2) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - SDADC Input Selection"] + #[inline(always)] + pub fn muxsel(&self) -> MUXSEL_R { + MUXSEL_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - SDADC Input Selection"] + #[inline(always)] + pub fn muxsel(&mut self) -> MUXSEL_W { + MUXSEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Input Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [inputctrl](index.html) module"] +pub struct INPUTCTRL_SPEC; +impl crate::RegisterSpec for INPUTCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [inputctrl::R](R) reader structure"] +impl crate::Readable for INPUTCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [inputctrl::W](W) writer structure"] +impl crate::Writable for INPUTCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INPUTCTRL to value 0"] +impl crate::Resettable for INPUTCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sdadc/intenclr.rs b/pac/atsamc21g/src/sdadc/intenclr.rs new file mode 100644 index 000000000000..b10f428d30b1 --- /dev/null +++ b/pac/atsamc21g/src/sdadc/intenclr.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RESRDY` reader - Result Ready Interrupt Disable"] +pub struct RESRDY_R(crate::FieldReader); +impl RESRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESRDY` writer - Result Ready Interrupt Disable"] +pub struct RESRDY_W<'a> { + w: &'a mut W, +} +impl<'a> RESRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `OVERRUN` reader - Overrun Interrupt Disable"] +pub struct OVERRUN_R(crate::FieldReader); +impl OVERRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVERRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVERRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVERRUN` writer - Overrun Interrupt Disable"] +pub struct OVERRUN_W<'a> { + w: &'a mut W, +} +impl<'a> OVERRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WINMON` reader - Window Monitor Interrupt Disable"] +pub struct WINMON_R(crate::FieldReader); +impl WINMON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINMON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINMON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMON` writer - Window Monitor Interrupt Disable"] +pub struct WINMON_W<'a> { + w: &'a mut W, +} +impl<'a> WINMON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Result Ready Interrupt Disable"] + #[inline(always)] + pub fn resrdy(&self) -> RESRDY_R { + RESRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Overrun Interrupt Disable"] + #[inline(always)] + pub fn overrun(&self) -> OVERRUN_R { + OVERRUN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Window Monitor Interrupt Disable"] + #[inline(always)] + pub fn winmon(&self) -> WINMON_R { + WINMON_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Result Ready Interrupt Disable"] + #[inline(always)] + pub fn resrdy(&mut self) -> RESRDY_W { + RESRDY_W { w: self } + } + #[doc = "Bit 1 - Overrun Interrupt Disable"] + #[inline(always)] + pub fn overrun(&mut self) -> OVERRUN_W { + OVERRUN_W { w: self } + } + #[doc = "Bit 2 - Window Monitor Interrupt Disable"] + #[inline(always)] + pub fn winmon(&mut self) -> WINMON_W { + WINMON_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sdadc/intenset.rs b/pac/atsamc21g/src/sdadc/intenset.rs new file mode 100644 index 000000000000..5ca93b05b859 --- /dev/null +++ b/pac/atsamc21g/src/sdadc/intenset.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RESRDY` reader - Result Ready Interrupt Enable"] +pub struct RESRDY_R(crate::FieldReader); +impl RESRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESRDY` writer - Result Ready Interrupt Enable"] +pub struct RESRDY_W<'a> { + w: &'a mut W, +} +impl<'a> RESRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `OVERRUN` reader - Overrun Interrupt Enable"] +pub struct OVERRUN_R(crate::FieldReader); +impl OVERRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVERRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVERRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVERRUN` writer - Overrun Interrupt Enable"] +pub struct OVERRUN_W<'a> { + w: &'a mut W, +} +impl<'a> OVERRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WINMON` reader - Window Monitor Interrupt Enable"] +pub struct WINMON_R(crate::FieldReader); +impl WINMON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINMON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINMON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMON` writer - Window Monitor Interrupt Enable"] +pub struct WINMON_W<'a> { + w: &'a mut W, +} +impl<'a> WINMON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Result Ready Interrupt Enable"] + #[inline(always)] + pub fn resrdy(&self) -> RESRDY_R { + RESRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Overrun Interrupt Enable"] + #[inline(always)] + pub fn overrun(&self) -> OVERRUN_R { + OVERRUN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Window Monitor Interrupt Enable"] + #[inline(always)] + pub fn winmon(&self) -> WINMON_R { + WINMON_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Result Ready Interrupt Enable"] + #[inline(always)] + pub fn resrdy(&mut self) -> RESRDY_W { + RESRDY_W { w: self } + } + #[doc = "Bit 1 - Overrun Interrupt Enable"] + #[inline(always)] + pub fn overrun(&mut self) -> OVERRUN_W { + OVERRUN_W { w: self } + } + #[doc = "Bit 2 - Window Monitor Interrupt Enable"] + #[inline(always)] + pub fn winmon(&mut self) -> WINMON_W { + WINMON_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sdadc/intflag.rs b/pac/atsamc21g/src/sdadc/intflag.rs new file mode 100644 index 000000000000..3cd74788b226 --- /dev/null +++ b/pac/atsamc21g/src/sdadc/intflag.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RESRDY` reader - Result Ready Interrupt Flag"] +pub struct RESRDY_R(crate::FieldReader); +impl RESRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESRDY` writer - Result Ready Interrupt Flag"] +pub struct RESRDY_W<'a> { + w: &'a mut W, +} +impl<'a> RESRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `OVERRUN` reader - Overrun Interrupt Flag"] +pub struct OVERRUN_R(crate::FieldReader); +impl OVERRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVERRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVERRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVERRUN` writer - Overrun Interrupt Flag"] +pub struct OVERRUN_W<'a> { + w: &'a mut W, +} +impl<'a> OVERRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WINMON` reader - Window Monitor Interrupt Flag"] +pub struct WINMON_R(crate::FieldReader); +impl WINMON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINMON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINMON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMON` writer - Window Monitor Interrupt Flag"] +pub struct WINMON_W<'a> { + w: &'a mut W, +} +impl<'a> WINMON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Result Ready Interrupt Flag"] + #[inline(always)] + pub fn resrdy(&self) -> RESRDY_R { + RESRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Overrun Interrupt Flag"] + #[inline(always)] + pub fn overrun(&self) -> OVERRUN_R { + OVERRUN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Window Monitor Interrupt Flag"] + #[inline(always)] + pub fn winmon(&self) -> WINMON_R { + WINMON_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Result Ready Interrupt Flag"] + #[inline(always)] + pub fn resrdy(&mut self) -> RESRDY_W { + RESRDY_W { w: self } + } + #[doc = "Bit 1 - Overrun Interrupt Flag"] + #[inline(always)] + pub fn overrun(&mut self) -> OVERRUN_W { + OVERRUN_W { w: self } + } + #[doc = "Bit 2 - Window Monitor Interrupt Flag"] + #[inline(always)] + pub fn winmon(&mut self) -> WINMON_W { + WINMON_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sdadc/offsetcorr.rs b/pac/atsamc21g/src/sdadc/offsetcorr.rs new file mode 100644 index 000000000000..7bda80d6fbfc --- /dev/null +++ b/pac/atsamc21g/src/sdadc/offsetcorr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `OFFSETCORR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OFFSETCORR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OFFSETCORR` reader - Offset Correction Value"] +pub struct OFFSETCORR_R(crate::FieldReader); +impl OFFSETCORR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + OFFSETCORR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OFFSETCORR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OFFSETCORR` writer - Offset Correction Value"] +pub struct OFFSETCORR_W<'a> { + w: &'a mut W, +} +impl<'a> OFFSETCORR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Offset Correction Value"] + #[inline(always)] + pub fn offsetcorr(&self) -> OFFSETCORR_R { + OFFSETCORR_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Offset Correction Value"] + #[inline(always)] + pub fn offsetcorr(&mut self) -> OFFSETCORR_W { + OFFSETCORR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Offset Correction\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [offsetcorr](index.html) module"] +pub struct OFFSETCORR_SPEC; +impl crate::RegisterSpec for OFFSETCORR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [offsetcorr::R](R) reader structure"] +impl crate::Readable for OFFSETCORR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [offsetcorr::W](W) writer structure"] +impl crate::Writable for OFFSETCORR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OFFSETCORR to value 0"] +impl crate::Resettable for OFFSETCORR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sdadc/refctrl.rs b/pac/atsamc21g/src/sdadc/refctrl.rs new file mode 100644 index 000000000000..89449071a49b --- /dev/null +++ b/pac/atsamc21g/src/sdadc/refctrl.rs @@ -0,0 +1,262 @@ +#[doc = "Register `REFCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `REFCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Reference Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum REFSEL_A { + #[doc = "0: Internal Bandgap Reference"] + INTREF = 0, + #[doc = "1: External Reference"] + AREFB = 1, + #[doc = "2: Internal DAC Output"] + DAC = 2, + #[doc = "3: VDDANA"] + INTVCC = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: REFSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `REFSEL` reader - Reference Selection"] +pub struct REFSEL_R(crate::FieldReader); +impl REFSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REFSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> REFSEL_A { + match self.bits { + 0 => REFSEL_A::INTREF, + 1 => REFSEL_A::AREFB, + 2 => REFSEL_A::DAC, + 3 => REFSEL_A::INTVCC, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INTREF`"] + #[inline(always)] + pub fn is_intref(&self) -> bool { + **self == REFSEL_A::INTREF + } + #[doc = "Checks if the value of the field is `AREFB`"] + #[inline(always)] + pub fn is_arefb(&self) -> bool { + **self == REFSEL_A::AREFB + } + #[doc = "Checks if the value of the field is `DAC`"] + #[inline(always)] + pub fn is_dac(&self) -> bool { + **self == REFSEL_A::DAC + } + #[doc = "Checks if the value of the field is `INTVCC`"] + #[inline(always)] + pub fn is_intvcc(&self) -> bool { + **self == REFSEL_A::INTVCC + } +} +impl core::ops::Deref for REFSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REFSEL` writer - Reference Selection"] +pub struct REFSEL_W<'a> { + w: &'a mut W, +} +impl<'a> REFSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: REFSEL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Internal Bandgap Reference"] + #[inline(always)] + pub fn intref(self) -> &'a mut W { + self.variant(REFSEL_A::INTREF) + } + #[doc = "External Reference"] + #[inline(always)] + pub fn arefb(self) -> &'a mut W { + self.variant(REFSEL_A::AREFB) + } + #[doc = "Internal DAC Output"] + #[inline(always)] + pub fn dac(self) -> &'a mut W { + self.variant(REFSEL_A::DAC) + } + #[doc = "VDDANA"] + #[inline(always)] + pub fn intvcc(self) -> &'a mut W { + self.variant(REFSEL_A::INTVCC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u8 & 0x03); + self.w + } +} +#[doc = "Field `REFRANGE` reader - Reference Range"] +pub struct REFRANGE_R(crate::FieldReader); +impl REFRANGE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REFRANGE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REFRANGE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REFRANGE` writer - Reference Range"] +pub struct REFRANGE_W<'a> { + w: &'a mut W, +} +impl<'a> REFRANGE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u8 & 0x03) << 4); + self.w + } +} +#[doc = "Field `ONREFBUF` reader - Reference Buffer"] +pub struct ONREFBUF_R(crate::FieldReader); +impl ONREFBUF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONREFBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONREFBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONREFBUF` writer - Reference Buffer"] +pub struct ONREFBUF_W<'a> { + w: &'a mut W, +} +impl<'a> ONREFBUF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Reference Selection"] + #[inline(always)] + pub fn refsel(&self) -> REFSEL_R { + REFSEL_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bits 4:5 - Reference Range"] + #[inline(always)] + pub fn refrange(&self) -> REFRANGE_R { + REFRANGE_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bit 7 - Reference Buffer"] + #[inline(always)] + pub fn onrefbuf(&self) -> ONREFBUF_R { + ONREFBUF_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:1 - Reference Selection"] + #[inline(always)] + pub fn refsel(&mut self) -> REFSEL_W { + REFSEL_W { w: self } + } + #[doc = "Bits 4:5 - Reference Range"] + #[inline(always)] + pub fn refrange(&mut self) -> REFRANGE_W { + REFRANGE_W { w: self } + } + #[doc = "Bit 7 - Reference Buffer"] + #[inline(always)] + pub fn onrefbuf(&mut self) -> ONREFBUF_W { + ONREFBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Reference Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [refctrl](index.html) module"] +pub struct REFCTRL_SPEC; +impl crate::RegisterSpec for REFCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [refctrl::R](R) reader structure"] +impl crate::Readable for REFCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [refctrl::W](W) writer structure"] +impl crate::Writable for REFCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets REFCTRL to value 0"] +impl crate::Resettable for REFCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sdadc/result.rs b/pac/atsamc21g/src/sdadc/result.rs new file mode 100644 index 000000000000..3f88d8b60ca6 --- /dev/null +++ b/pac/atsamc21g/src/sdadc/result.rs @@ -0,0 +1,53 @@ +#[doc = "Register `RESULT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `RESULT` reader - Result Value"] +pub struct RESULT_R(crate::FieldReader); +impl RESULT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + RESULT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESULT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:23 - Result Value"] + #[inline(always)] + pub fn result(&self) -> RESULT_R { + RESULT_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +#[doc = "Result\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [result](index.html) module"] +pub struct RESULT_SPEC; +impl crate::RegisterSpec for RESULT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [result::R](R) reader structure"] +impl crate::Readable for RESULT_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets RESULT to value 0"] +impl crate::Resettable for RESULT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sdadc/seqctrl.rs b/pac/atsamc21g/src/sdadc/seqctrl.rs new file mode 100644 index 000000000000..c8d1103959ee --- /dev/null +++ b/pac/atsamc21g/src/sdadc/seqctrl.rs @@ -0,0 +1,103 @@ +#[doc = "Register `SEQCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SEQCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SEQEN` reader - Enable Positive Input in the Sequence"] +pub struct SEQEN_R(crate::FieldReader); +impl SEQEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SEQEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEQEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEQEN` writer - Enable Positive Input in the Sequence"] +pub struct SEQEN_W<'a> { + w: &'a mut W, +} +impl<'a> SEQEN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Enable Positive Input in the Sequence"] + #[inline(always)] + pub fn seqen(&self) -> SEQEN_R { + SEQEN_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Enable Positive Input in the Sequence"] + #[inline(always)] + pub fn seqen(&mut self) -> SEQEN_W { + SEQEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Sequence Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [seqctrl](index.html) module"] +pub struct SEQCTRL_SPEC; +impl crate::RegisterSpec for SEQCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [seqctrl::R](R) reader structure"] +impl crate::Readable for SEQCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [seqctrl::W](W) writer structure"] +impl crate::Writable for SEQCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SEQCTRL to value 0"] +impl crate::Resettable for SEQCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sdadc/seqstatus.rs b/pac/atsamc21g/src/sdadc/seqstatus.rs new file mode 100644 index 000000000000..db10e7ca448e --- /dev/null +++ b/pac/atsamc21g/src/sdadc/seqstatus.rs @@ -0,0 +1,73 @@ +#[doc = "Register `SEQSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SEQSTATE` reader - Sequence State"] +pub struct SEQSTATE_R(crate::FieldReader); +impl SEQSTATE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SEQSTATE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEQSTATE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEQBUSY` reader - Sequence Busy"] +pub struct SEQBUSY_R(crate::FieldReader); +impl SEQBUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SEQBUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEQBUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:3 - Sequence State"] + #[inline(always)] + pub fn seqstate(&self) -> SEQSTATE_R { + SEQSTATE_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 7 - Sequence Busy"] + #[inline(always)] + pub fn seqbusy(&self) -> SEQBUSY_R { + SEQBUSY_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +#[doc = "Sequence Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [seqstatus](index.html) module"] +pub struct SEQSTATUS_SPEC; +impl crate::RegisterSpec for SEQSTATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [seqstatus::R](R) reader structure"] +impl crate::Readable for SEQSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SEQSTATUS to value 0"] +impl crate::Resettable for SEQSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sdadc/shiftcorr.rs b/pac/atsamc21g/src/sdadc/shiftcorr.rs new file mode 100644 index 000000000000..a5940537700e --- /dev/null +++ b/pac/atsamc21g/src/sdadc/shiftcorr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `SHIFTCORR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SHIFTCORR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SHIFTCORR` reader - Shift Correction Value"] +pub struct SHIFTCORR_R(crate::FieldReader); +impl SHIFTCORR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SHIFTCORR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SHIFTCORR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SHIFTCORR` writer - Shift Correction Value"] +pub struct SHIFTCORR_W<'a> { + w: &'a mut W, +} +impl<'a> SHIFTCORR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Shift Correction Value"] + #[inline(always)] + pub fn shiftcorr(&self) -> SHIFTCORR_R { + SHIFTCORR_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Shift Correction Value"] + #[inline(always)] + pub fn shiftcorr(&mut self) -> SHIFTCORR_W { + SHIFTCORR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Shift Correction\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [shiftcorr](index.html) module"] +pub struct SHIFTCORR_SPEC; +impl crate::RegisterSpec for SHIFTCORR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [shiftcorr::R](R) reader structure"] +impl crate::Readable for SHIFTCORR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [shiftcorr::W](W) writer structure"] +impl crate::Writable for SHIFTCORR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SHIFTCORR to value 0"] +impl crate::Resettable for SHIFTCORR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sdadc/swtrig.rs b/pac/atsamc21g/src/sdadc/swtrig.rs new file mode 100644 index 000000000000..7656a614dd67 --- /dev/null +++ b/pac/atsamc21g/src/sdadc/swtrig.rs @@ -0,0 +1,160 @@ +#[doc = "Register `SWTRIG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SWTRIG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FLUSH` reader - SDADC Flush"] +pub struct FLUSH_R(crate::FieldReader); +impl FLUSH_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FLUSH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FLUSH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLUSH` writer - SDADC Flush"] +pub struct FLUSH_W<'a> { + w: &'a mut W, +} +impl<'a> FLUSH_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `START` reader - Start SDADC Conversion"] +pub struct START_R(crate::FieldReader); +impl START_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + START_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for START_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `START` writer - Start SDADC Conversion"] +pub struct START_W<'a> { + w: &'a mut W, +} +impl<'a> START_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - SDADC Flush"] + #[inline(always)] + pub fn flush(&self) -> FLUSH_R { + FLUSH_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Start SDADC Conversion"] + #[inline(always)] + pub fn start(&self) -> START_R { + START_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - SDADC Flush"] + #[inline(always)] + pub fn flush(&mut self) -> FLUSH_W { + FLUSH_W { w: self } + } + #[doc = "Bit 1 - Start SDADC Conversion"] + #[inline(always)] + pub fn start(&mut self) -> START_W { + START_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Software Trigger\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [swtrig](index.html) module"] +pub struct SWTRIG_SPEC; +impl crate::RegisterSpec for SWTRIG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [swtrig::R](R) reader structure"] +impl crate::Readable for SWTRIG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [swtrig::W](W) writer structure"] +impl crate::Writable for SWTRIG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SWTRIG to value 0"] +impl crate::Resettable for SWTRIG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sdadc/syncbusy.rs b/pac/atsamc21g/src/sdadc/syncbusy.rs new file mode 100644 index 000000000000..519fa5e8a57f --- /dev/null +++ b/pac/atsamc21g/src/sdadc/syncbusy.rs @@ -0,0 +1,273 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - SWRST Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - ENABLE Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLC` reader - CTRLC Synchronization Busy"] +pub struct CTRLC_R(crate::FieldReader); +impl CTRLC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INPUTCTRL` reader - INPUTCTRL Synchronization Busy"] +pub struct INPUTCTRL_R(crate::FieldReader); +impl INPUTCTRL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INPUTCTRL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INPUTCTRL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINCTRL` reader - WINCTRL Synchronization Busy"] +pub struct WINCTRL_R(crate::FieldReader); +impl WINCTRL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINCTRL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINCTRL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINLT` reader - WINLT Synchronization Busy"] +pub struct WINLT_R(crate::FieldReader); +impl WINLT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINLT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINLT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINUT` reader - WINUT Synchronization Busy"] +pub struct WINUT_R(crate::FieldReader); +impl WINUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OFFSETCORR` reader - OFFSETCTRL Synchronization Busy"] +pub struct OFFSETCORR_R(crate::FieldReader); +impl OFFSETCORR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OFFSETCORR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OFFSETCORR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GAINCORR` reader - GAINCORR Synchronization Busy"] +pub struct GAINCORR_R(crate::FieldReader); +impl GAINCORR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GAINCORR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GAINCORR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SHIFTCORR` reader - SHIFTCORR Synchronization Busy"] +pub struct SHIFTCORR_R(crate::FieldReader); +impl SHIFTCORR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SHIFTCORR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SHIFTCORR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG` reader - SWTRG Synchronization Busy"] +pub struct SWTRIG_R(crate::FieldReader); +impl SWTRIG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ANACTRL` reader - ANACTRL Synchronization Busy"] +pub struct ANACTRL_R(crate::FieldReader); +impl ANACTRL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ANACTRL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ANACTRL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - SWRST Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ENABLE Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - CTRLC Synchronization Busy"] + #[inline(always)] + pub fn ctrlc(&self) -> CTRLC_R { + CTRLC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - INPUTCTRL Synchronization Busy"] + #[inline(always)] + pub fn inputctrl(&self) -> INPUTCTRL_R { + INPUTCTRL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - WINCTRL Synchronization Busy"] + #[inline(always)] + pub fn winctrl(&self) -> WINCTRL_R { + WINCTRL_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - WINLT Synchronization Busy"] + #[inline(always)] + pub fn winlt(&self) -> WINLT_R { + WINLT_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - WINUT Synchronization Busy"] + #[inline(always)] + pub fn winut(&self) -> WINUT_R { + WINUT_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - OFFSETCTRL Synchronization Busy"] + #[inline(always)] + pub fn offsetcorr(&self) -> OFFSETCORR_R { + OFFSETCORR_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - GAINCORR Synchronization Busy"] + #[inline(always)] + pub fn gaincorr(&self) -> GAINCORR_R { + GAINCORR_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - SHIFTCORR Synchronization Busy"] + #[inline(always)] + pub fn shiftcorr(&self) -> SHIFTCORR_R { + SHIFTCORR_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - SWTRG Synchronization Busy"] + #[inline(always)] + pub fn swtrig(&self) -> SWTRIG_R { + SWTRIG_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - ANACTRL Synchronization Busy"] + #[inline(always)] + pub fn anactrl(&self) -> ANACTRL_R { + ANACTRL_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +#[doc = "Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sdadc/winctrl.rs b/pac/atsamc21g/src/sdadc/winctrl.rs new file mode 100644 index 000000000000..ed0d2d4fe006 --- /dev/null +++ b/pac/atsamc21g/src/sdadc/winctrl.rs @@ -0,0 +1,103 @@ +#[doc = "Register `WINCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WINCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WINMODE` reader - Window Monitor Mode"] +pub struct WINMODE_R(crate::FieldReader); +impl WINMODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WINMODE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMODE` writer - Window Monitor Mode"] +pub struct WINMODE_W<'a> { + w: &'a mut W, +} +impl<'a> WINMODE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Window Monitor Mode"] + #[inline(always)] + pub fn winmode(&self) -> WINMODE_R { + WINMODE_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Window Monitor Mode"] + #[inline(always)] + pub fn winmode(&mut self) -> WINMODE_W { + WINMODE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Window Monitor Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [winctrl](index.html) module"] +pub struct WINCTRL_SPEC; +impl crate::RegisterSpec for WINCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [winctrl::R](R) reader structure"] +impl crate::Readable for WINCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [winctrl::W](W) writer structure"] +impl crate::Writable for WINCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WINCTRL to value 0"] +impl crate::Resettable for WINCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sdadc/winlt.rs b/pac/atsamc21g/src/sdadc/winlt.rs new file mode 100644 index 000000000000..be16283e9e36 --- /dev/null +++ b/pac/atsamc21g/src/sdadc/winlt.rs @@ -0,0 +1,103 @@ +#[doc = "Register `WINLT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WINLT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WINLT` reader - Window Lower Threshold"] +pub struct WINLT_R(crate::FieldReader); +impl WINLT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + WINLT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINLT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINLT` writer - Window Lower Threshold"] +pub struct WINLT_W<'a> { + w: &'a mut W, +} +impl<'a> WINLT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Window Lower Threshold"] + #[inline(always)] + pub fn winlt(&self) -> WINLT_R { + WINLT_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Window Lower Threshold"] + #[inline(always)] + pub fn winlt(&mut self) -> WINLT_W { + WINLT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Window Monitor Lower Threshold\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [winlt](index.html) module"] +pub struct WINLT_SPEC; +impl crate::RegisterSpec for WINLT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [winlt::R](R) reader structure"] +impl crate::Readable for WINLT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [winlt::W](W) writer structure"] +impl crate::Writable for WINLT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WINLT to value 0"] +impl crate::Resettable for WINLT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sdadc/winut.rs b/pac/atsamc21g/src/sdadc/winut.rs new file mode 100644 index 000000000000..7dc20e7c5f9e --- /dev/null +++ b/pac/atsamc21g/src/sdadc/winut.rs @@ -0,0 +1,103 @@ +#[doc = "Register `WINUT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WINUT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WINUT` reader - Window Upper Threshold"] +pub struct WINUT_R(crate::FieldReader); +impl WINUT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + WINUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINUT` writer - Window Upper Threshold"] +pub struct WINUT_W<'a> { + w: &'a mut W, +} +impl<'a> WINUT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Window Upper Threshold"] + #[inline(always)] + pub fn winut(&self) -> WINUT_R { + WINUT_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Window Upper Threshold"] + #[inline(always)] + pub fn winut(&mut self) -> WINUT_W { + WINUT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Window Monitor Upper Threshold\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [winut](index.html) module"] +pub struct WINUT_SPEC; +impl crate::RegisterSpec for WINUT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [winut::R](R) reader structure"] +impl crate::Readable for WINUT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [winut::W](W) writer structure"] +impl crate::Writable for WINUT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WINUT to value 0"] +impl crate::Resettable for WINUT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sercom0.rs b/pac/atsamc21g/src/sercom0.rs new file mode 100644 index 000000000000..da7b62f750c6 --- /dev/null +++ b/pac/atsamc21g/src/sercom0.rs @@ -0,0 +1,327 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved_0_i2cm: [u8; 0x31], +} +impl RegisterBlock { + #[doc = "0x00..0x31 - USART INTERNAL CLOCK Mode"] + #[inline(always)] + pub fn usart_int(&self) -> &USART_INT { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const USART_INT) } + } + #[doc = "0x00..0x31 - USART EXTERNAL CLOCK Mode"] + #[inline(always)] + pub fn usart_ext(&self) -> &USART_EXT { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const USART_EXT) } + } + #[doc = "0x00..0x31 - SPI Master Mode"] + #[inline(always)] + pub fn spim(&self) -> &SPIM { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const SPIM) } + } + #[doc = "0x00..0x31 - SPI Slave Mode"] + #[inline(always)] + pub fn spis(&self) -> &SPIS { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const SPIS) } + } + #[doc = "0x00..0x29 - I2C Slave Mode"] + #[inline(always)] + pub fn i2cs(&self) -> &I2CS { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const I2CS) } + } + #[doc = "0x00..0x31 - I2C Master Mode"] + #[inline(always)] + pub fn i2cm(&self) -> &I2CM { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const I2CM) } + } +} +#[doc = r"Register block"] +#[repr(C)] +pub struct I2CM { + #[doc = "0x00 - I2CM Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - I2CM Control B"] + pub ctrlb: crate::Reg, + _reserved2: [u8; 0x04], + #[doc = "0x0c - I2CM Baud Rate"] + pub baud: crate::Reg, + _reserved3: [u8; 0x04], + #[doc = "0x14 - I2CM Interrupt Enable Clear"] + pub intenclr: crate::Reg, + _reserved4: [u8; 0x01], + #[doc = "0x16 - I2CM Interrupt Enable Set"] + pub intenset: crate::Reg, + _reserved5: [u8; 0x01], + #[doc = "0x18 - I2CM Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x1a - I2CM Status"] + pub status: crate::Reg, + #[doc = "0x1c - I2CM Synchronization Busy"] + pub syncbusy: crate::Reg, + _reserved8: [u8; 0x04], + #[doc = "0x24 - I2CM Address"] + pub addr: crate::Reg, + #[doc = "0x28 - I2CM Data"] + pub data: crate::Reg, + _reserved10: [u8; 0x07], + #[doc = "0x30 - I2CM Debug Control"] + pub dbgctrl: crate::Reg, +} +#[doc = r"Register block"] +#[doc = "I2C Master Mode"] +pub mod i2cm; +#[doc = r"Register block"] +#[repr(C)] +pub struct I2CS { + #[doc = "0x00 - I2CS Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - I2CS Control B"] + pub ctrlb: crate::Reg, + _reserved2: [u8; 0x0c], + #[doc = "0x14 - I2CS Interrupt Enable Clear"] + pub intenclr: crate::Reg, + _reserved3: [u8; 0x01], + #[doc = "0x16 - I2CS Interrupt Enable Set"] + pub intenset: crate::Reg, + _reserved4: [u8; 0x01], + #[doc = "0x18 - I2CS Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved5: [u8; 0x01], + #[doc = "0x1a - I2CS Status"] + pub status: crate::Reg, + #[doc = "0x1c - I2CS Synchronization Busy"] + pub syncbusy: crate::Reg, + _reserved7: [u8; 0x04], + #[doc = "0x24 - I2CS Address"] + pub addr: crate::Reg, + #[doc = "0x28 - I2CS Data"] + pub data: crate::Reg, +} +#[doc = r"Register block"] +#[doc = "I2C Slave Mode"] +pub mod i2cs; +#[doc = r"Register block"] +#[repr(C)] +pub struct SPIS { + #[doc = "0x00 - SPIS Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - SPIS Control B"] + pub ctrlb: crate::Reg, + _reserved2: [u8; 0x04], + #[doc = "0x0c - SPIS Baud Rate"] + pub baud: crate::Reg, + _reserved3: [u8; 0x07], + #[doc = "0x14 - SPIS Interrupt Enable Clear"] + pub intenclr: crate::Reg, + _reserved4: [u8; 0x01], + #[doc = "0x16 - SPIS Interrupt Enable Set"] + pub intenset: crate::Reg, + _reserved5: [u8; 0x01], + #[doc = "0x18 - SPIS Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x1a - SPIS Status"] + pub status: crate::Reg, + #[doc = "0x1c - SPIS Synchronization Busy"] + pub syncbusy: crate::Reg, + _reserved8: [u8; 0x04], + #[doc = "0x24 - SPIS Address"] + pub addr: crate::Reg, + #[doc = "0x28 - SPIS Data"] + pub data: crate::Reg, + _reserved10: [u8; 0x04], + #[doc = "0x30 - SPIS Debug Control"] + pub dbgctrl: crate::Reg, +} +#[doc = r"Register block"] +#[doc = "SPI Slave Mode"] +pub mod spis; +#[doc = r"Register block"] +#[repr(C)] +pub struct SPIM { + #[doc = "0x00 - SPIM Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - SPIM Control B"] + pub ctrlb: crate::Reg, + _reserved2: [u8; 0x04], + #[doc = "0x0c - SPIM Baud Rate"] + pub baud: crate::Reg, + _reserved3: [u8; 0x07], + #[doc = "0x14 - SPIM Interrupt Enable Clear"] + pub intenclr: crate::Reg, + _reserved4: [u8; 0x01], + #[doc = "0x16 - SPIM Interrupt Enable Set"] + pub intenset: crate::Reg, + _reserved5: [u8; 0x01], + #[doc = "0x18 - SPIM Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x1a - SPIM Status"] + pub status: crate::Reg, + #[doc = "0x1c - SPIM Synchronization Busy"] + pub syncbusy: crate::Reg, + _reserved8: [u8; 0x04], + #[doc = "0x24 - SPIM Address"] + pub addr: crate::Reg, + #[doc = "0x28 - SPIM Data"] + pub data: crate::Reg, + _reserved10: [u8; 0x04], + #[doc = "0x30 - SPIM Debug Control"] + pub dbgctrl: crate::Reg, +} +#[doc = r"Register block"] +#[doc = "SPI Master Mode"] +pub mod spim; +#[doc = r"Register block"] +#[repr(C)] +pub struct USART_EXT { + #[doc = "0x00 - USART_EXT Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - USART_EXT Control B"] + pub ctrlb: crate::Reg, + #[doc = "0x08 - USART_EXT Control C"] + pub ctrlc: crate::Reg, + _reserved_3_baud: [u8; 0x02], + #[doc = "0x0e - USART_EXT Receive Pulse Length"] + pub rxpl: crate::Reg, + _reserved5: [u8; 0x05], + #[doc = "0x14 - USART_EXT Interrupt Enable Clear"] + pub intenclr: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x16 - USART_EXT Interrupt Enable Set"] + pub intenset: crate::Reg, + _reserved7: [u8; 0x01], + #[doc = "0x18 - USART_EXT Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved8: [u8; 0x01], + #[doc = "0x1a - USART_EXT Status"] + pub status: crate::Reg, + #[doc = "0x1c - USART_EXT Synchronization Busy"] + pub syncbusy: crate::Reg, + _reserved10: [u8; 0x08], + #[doc = "0x28 - USART_EXT Data"] + pub data: crate::Reg, + _reserved11: [u8; 0x06], + #[doc = "0x30 - USART_EXT Debug Control"] + pub dbgctrl: crate::Reg, +} +impl USART_EXT { + #[doc = "0x0c - USART_EXT Baud Rate"] + #[inline(always)] + pub fn baud_usartfp_mode( + &self, + ) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } + #[doc = "0x0c - USART_EXT Baud Rate"] + #[inline(always)] + pub fn baud_fracfp_mode( + &self, + ) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } + #[doc = "0x0c - USART_EXT Baud Rate"] + #[inline(always)] + pub fn baud_frac_mode( + &self, + ) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } + #[doc = "0x0c - USART_EXT Baud Rate"] + #[inline(always)] + pub fn baud(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } +} +#[doc = r"Register block"] +#[doc = "USART EXTERNAL CLOCK Mode"] +pub mod usart_ext; +#[doc = r"Register block"] +#[repr(C)] +pub struct USART_INT { + #[doc = "0x00 - USART_INT Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - USART_INT Control B"] + pub ctrlb: crate::Reg, + #[doc = "0x08 - USART_INT Control C"] + pub ctrlc: crate::Reg, + _reserved_3_baud: [u8; 0x02], + #[doc = "0x0e - USART_INT Receive Pulse Length"] + pub rxpl: crate::Reg, + _reserved5: [u8; 0x05], + #[doc = "0x14 - USART_INT Interrupt Enable Clear"] + pub intenclr: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x16 - USART_INT Interrupt Enable Set"] + pub intenset: crate::Reg, + _reserved7: [u8; 0x01], + #[doc = "0x18 - USART_INT Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved8: [u8; 0x01], + #[doc = "0x1a - USART_INT Status"] + pub status: crate::Reg, + #[doc = "0x1c - USART_INT Synchronization Busy"] + pub syncbusy: crate::Reg, + _reserved10: [u8; 0x08], + #[doc = "0x28 - USART_INT Data"] + pub data: crate::Reg, + _reserved11: [u8; 0x06], + #[doc = "0x30 - USART_INT Debug Control"] + pub dbgctrl: crate::Reg, +} +impl USART_INT { + #[doc = "0x0c - USART_INT Baud Rate"] + #[inline(always)] + pub fn baud_usartfp_mode( + &self, + ) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } + #[doc = "0x0c - USART_INT Baud Rate"] + #[inline(always)] + pub fn baud_fracfp_mode( + &self, + ) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } + #[doc = "0x0c - USART_INT Baud Rate"] + #[inline(always)] + pub fn baud_frac_mode( + &self, + ) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } + #[doc = "0x0c - USART_INT Baud Rate"] + #[inline(always)] + pub fn baud(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } +} +#[doc = r"Register block"] +#[doc = "USART INTERNAL CLOCK Mode"] +pub mod usart_int; diff --git a/pac/atsamc21g/src/sercom0/i2cm.rs b/pac/atsamc21g/src/sercom0/i2cm.rs new file mode 100644 index 000000000000..8aa217da8b18 --- /dev/null +++ b/pac/atsamc21g/src/sercom0/i2cm.rs @@ -0,0 +1,44 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "I2CM Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "I2CM Control B"] +pub mod ctrlb; +#[doc = "BAUD register accessor: an alias for `Reg`"] +pub type BAUD = crate::Reg; +#[doc = "I2CM Baud Rate"] +pub mod baud; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "I2CM Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "I2CM Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "I2CM Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "I2CM Status"] +pub mod status; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "I2CM Synchronization Busy"] +pub mod syncbusy; +#[doc = "ADDR register accessor: an alias for `Reg`"] +pub type ADDR = crate::Reg; +#[doc = "I2CM Address"] +pub mod addr; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "I2CM Data"] +pub mod data; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "I2CM Debug Control"] +pub mod dbgctrl; diff --git a/pac/atsamc21g/src/sercom0/i2cm/addr.rs b/pac/atsamc21g/src/sercom0/i2cm/addr.rs new file mode 100644 index 000000000000..4efd19e824c6 --- /dev/null +++ b/pac/atsamc21g/src/sercom0/i2cm/addr.rs @@ -0,0 +1,281 @@ +#[doc = "Register `ADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ADDR` reader - Address Value"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - Address Value"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07ff) | (value as u32 & 0x07ff); + self.w + } +} +#[doc = "Field `LENEN` reader - Length Enable"] +pub struct LENEN_R(crate::FieldReader); +impl LENEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LENEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LENEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LENEN` writer - Length Enable"] +pub struct LENEN_W<'a> { + w: &'a mut W, +} +impl<'a> LENEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `HS` reader - High Speed Mode"] +pub struct HS_R(crate::FieldReader); +impl HS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HS` writer - High Speed Mode"] +pub struct HS_W<'a> { + w: &'a mut W, +} +impl<'a> HS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `TENBITEN` reader - Ten Bit Addressing Enable"] +pub struct TENBITEN_R(crate::FieldReader); +impl TENBITEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TENBITEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TENBITEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TENBITEN` writer - Ten Bit Addressing Enable"] +pub struct TENBITEN_W<'a> { + w: &'a mut W, +} +impl<'a> TENBITEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `LEN` reader - Length"] +pub struct LEN_R(crate::FieldReader); +impl LEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LEN` writer - Length"] +pub struct LEN_W<'a> { + w: &'a mut W, +} +impl<'a> LEN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:10 - Address Value"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new((self.bits & 0x07ff) as u16) + } + #[doc = "Bit 13 - Length Enable"] + #[inline(always)] + pub fn lenen(&self) -> LENEN_R { + LENEN_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - High Speed Mode"] + #[inline(always)] + pub fn hs(&self) -> HS_R { + HS_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Ten Bit Addressing Enable"] + #[inline(always)] + pub fn tenbiten(&self) -> TENBITEN_R { + TENBITEN_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:23 - Length"] + #[inline(always)] + pub fn len(&self) -> LEN_R { + LEN_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:10 - Address Value"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Bit 13 - Length Enable"] + #[inline(always)] + pub fn lenen(&mut self) -> LENEN_W { + LENEN_W { w: self } + } + #[doc = "Bit 14 - High Speed Mode"] + #[inline(always)] + pub fn hs(&mut self) -> HS_W { + HS_W { w: self } + } + #[doc = "Bit 15 - Ten Bit Addressing Enable"] + #[inline(always)] + pub fn tenbiten(&mut self) -> TENBITEN_W { + TENBITEN_W { w: self } + } + #[doc = "Bits 16:23 - Length"] + #[inline(always)] + pub fn len(&mut self) -> LEN_W { + LEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [addr](index.html) module"] +pub struct ADDR_SPEC; +impl crate::RegisterSpec for ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [addr::R](R) reader structure"] +impl crate::Readable for ADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [addr::W](W) writer structure"] +impl crate::Writable for ADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ADDR to value 0"] +impl crate::Resettable for ADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sercom0/i2cm/baud.rs b/pac/atsamc21g/src/sercom0/i2cm/baud.rs new file mode 100644 index 000000000000..7c98d3b5b0de --- /dev/null +++ b/pac/atsamc21g/src/sercom0/i2cm/baud.rs @@ -0,0 +1,214 @@ +#[doc = "Register `BAUD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +#[doc = "Field `BAUDLOW` reader - Baud Rate Value Low"] +pub struct BAUDLOW_R(crate::FieldReader); +impl BAUDLOW_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BAUDLOW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUDLOW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUDLOW` writer - Baud Rate Value Low"] +pub struct BAUDLOW_W<'a> { + w: &'a mut W, +} +impl<'a> BAUDLOW_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +#[doc = "Field `HSBAUD` reader - High Speed Baud Rate Value"] +pub struct HSBAUD_R(crate::FieldReader); +impl HSBAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + HSBAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HSBAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HSBAUD` writer - High Speed Baud Rate Value"] +pub struct HSBAUD_W<'a> { + w: &'a mut W, +} +impl<'a> HSBAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +#[doc = "Field `HSBAUDLOW` reader - High Speed Baud Rate Value Low"] +pub struct HSBAUDLOW_R(crate::FieldReader); +impl HSBAUDLOW_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + HSBAUDLOW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HSBAUDLOW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HSBAUDLOW` writer - High Speed Baud Rate Value Low"] +pub struct HSBAUDLOW_W<'a> { + w: &'a mut W, +} +impl<'a> HSBAUDLOW_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 24)) | ((value as u32 & 0xff) << 24); + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Baud Rate Value Low"] + #[inline(always)] + pub fn baudlow(&self) -> BAUDLOW_R { + BAUDLOW_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - High Speed Baud Rate Value"] + #[inline(always)] + pub fn hsbaud(&self) -> HSBAUD_R { + HSBAUD_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - High Speed Baud Rate Value Low"] + #[inline(always)] + pub fn hsbaudlow(&self) -> HSBAUDLOW_R { + HSBAUDLOW_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Bits 8:15 - Baud Rate Value Low"] + #[inline(always)] + pub fn baudlow(&mut self) -> BAUDLOW_W { + BAUDLOW_W { w: self } + } + #[doc = "Bits 16:23 - High Speed Baud Rate Value"] + #[inline(always)] + pub fn hsbaud(&mut self) -> HSBAUD_W { + HSBAUD_W { w: self } + } + #[doc = "Bits 24:31 - High Speed Baud Rate Value Low"] + #[inline(always)] + pub fn hsbaudlow(&mut self) -> HSBAUDLOW_W { + HSBAUDLOW_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud](index.html) module"] +pub struct BAUD_SPEC; +impl crate::RegisterSpec for BAUD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [baud::R](R) reader structure"] +impl crate::Readable for BAUD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud::W](W) writer structure"] +impl crate::Writable for BAUD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD to value 0"] +impl crate::Resettable for BAUD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sercom0/i2cm/ctrla.rs b/pac/atsamc21g/src/sercom0/i2cm/ctrla.rs new file mode 100644 index 000000000000..34fa668b7967 --- /dev/null +++ b/pac/atsamc21g/src/sercom0/i2cm/ctrla.rs @@ -0,0 +1,903 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: USART with external clock"] + USART_EXT_CLK = 0, + #[doc = "1: USART with internal clock"] + USART_INT_CLK = 1, + #[doc = "2: SPI in slave operation"] + SPI_SLAVE = 2, + #[doc = "3: SPI in master operation"] + SPI_MASTER = 3, + #[doc = "4: I2C slave operation"] + I2C_SLAVE = 4, + #[doc = "5: I2C master operation"] + I2C_MASTER = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::USART_EXT_CLK), + 1 => Some(MODE_A::USART_INT_CLK), + 2 => Some(MODE_A::SPI_SLAVE), + 3 => Some(MODE_A::SPI_MASTER), + 4 => Some(MODE_A::I2C_SLAVE), + 5 => Some(MODE_A::I2C_MASTER), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_EXT_CLK`"] + #[inline(always)] + pub fn is_usart_ext_clk(&self) -> bool { + **self == MODE_A::USART_EXT_CLK + } + #[doc = "Checks if the value of the field is `USART_INT_CLK`"] + #[inline(always)] + pub fn is_usart_int_clk(&self) -> bool { + **self == MODE_A::USART_INT_CLK + } + #[doc = "Checks if the value of the field is `SPI_SLAVE`"] + #[inline(always)] + pub fn is_spi_slave(&self) -> bool { + **self == MODE_A::SPI_SLAVE + } + #[doc = "Checks if the value of the field is `SPI_MASTER`"] + #[inline(always)] + pub fn is_spi_master(&self) -> bool { + **self == MODE_A::SPI_MASTER + } + #[doc = "Checks if the value of the field is `I2C_SLAVE`"] + #[inline(always)] + pub fn is_i2c_slave(&self) -> bool { + **self == MODE_A::I2C_SLAVE + } + #[doc = "Checks if the value of the field is `I2C_MASTER`"] + #[inline(always)] + pub fn is_i2c_master(&self) -> bool { + **self == MODE_A::I2C_MASTER + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART with external clock"] + #[inline(always)] + pub fn usart_ext_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_EXT_CLK) + } + #[doc = "USART with internal clock"] + #[inline(always)] + pub fn usart_int_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_INT_CLK) + } + #[doc = "SPI in slave operation"] + #[inline(always)] + pub fn spi_slave(self) -> &'a mut W { + self.variant(MODE_A::SPI_SLAVE) + } + #[doc = "SPI in master operation"] + #[inline(always)] + pub fn spi_master(self) -> &'a mut W { + self.variant(MODE_A::SPI_MASTER) + } + #[doc = "I2C slave operation"] + #[inline(always)] + pub fn i2c_slave(self) -> &'a mut W { + self.variant(MODE_A::I2C_SLAVE) + } + #[doc = "I2C master operation"] + #[inline(always)] + pub fn i2c_master(self) -> &'a mut W { + self.variant(MODE_A::I2C_MASTER) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 2)) | ((value as u32 & 0x07) << 2); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `PINOUT` reader - Pin Usage"] +pub struct PINOUT_R(crate::FieldReader); +impl PINOUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PINOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PINOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PINOUT` writer - Pin Usage"] +pub struct PINOUT_W<'a> { + w: &'a mut W, +} +impl<'a> PINOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "SDA Hold Time\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SDAHOLD_A { + #[doc = "0: Disabled"] + DISABLE = 0, + #[doc = "1: 50-100ns hold time"] + _75NS = 1, + #[doc = "2: 300-600ns hold time"] + _450NS = 2, + #[doc = "3: 400-800ns hold time"] + _600NS = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SDAHOLD_A) -> Self { + variant as _ + } +} +#[doc = "Field `SDAHOLD` reader - SDA Hold Time"] +pub struct SDAHOLD_R(crate::FieldReader); +impl SDAHOLD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SDAHOLD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SDAHOLD_A { + match self.bits { + 0 => SDAHOLD_A::DISABLE, + 1 => SDAHOLD_A::_75NS, + 2 => SDAHOLD_A::_450NS, + 3 => SDAHOLD_A::_600NS, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == SDAHOLD_A::DISABLE + } + #[doc = "Checks if the value of the field is `_75NS`"] + #[inline(always)] + pub fn is_75ns(&self) -> bool { + **self == SDAHOLD_A::_75NS + } + #[doc = "Checks if the value of the field is `_450NS`"] + #[inline(always)] + pub fn is_450ns(&self) -> bool { + **self == SDAHOLD_A::_450NS + } + #[doc = "Checks if the value of the field is `_600NS`"] + #[inline(always)] + pub fn is_600ns(&self) -> bool { + **self == SDAHOLD_A::_600NS + } +} +impl core::ops::Deref for SDAHOLD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SDAHOLD` writer - SDA Hold Time"] +pub struct SDAHOLD_W<'a> { + w: &'a mut W, +} +impl<'a> SDAHOLD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SDAHOLD_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(SDAHOLD_A::DISABLE) + } + #[doc = "50-100ns hold time"] + #[inline(always)] + pub fn _75ns(self) -> &'a mut W { + self.variant(SDAHOLD_A::_75NS) + } + #[doc = "300-600ns hold time"] + #[inline(always)] + pub fn _450ns(self) -> &'a mut W { + self.variant(SDAHOLD_A::_450NS) + } + #[doc = "400-800ns hold time"] + #[inline(always)] + pub fn _600ns(self) -> &'a mut W { + self.variant(SDAHOLD_A::_600NS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 20)) | ((value as u32 & 0x03) << 20); + self.w + } +} +#[doc = "Field `MEXTTOEN` reader - Master SCL Low Extend Timeout"] +pub struct MEXTTOEN_R(crate::FieldReader); +impl MEXTTOEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MEXTTOEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MEXTTOEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MEXTTOEN` writer - Master SCL Low Extend Timeout"] +pub struct MEXTTOEN_W<'a> { + w: &'a mut W, +} +impl<'a> MEXTTOEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `SEXTTOEN` reader - Slave SCL Low Extend Timeout"] +pub struct SEXTTOEN_R(crate::FieldReader); +impl SEXTTOEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SEXTTOEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEXTTOEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEXTTOEN` writer - Slave SCL Low Extend Timeout"] +pub struct SEXTTOEN_W<'a> { + w: &'a mut W, +} +impl<'a> SEXTTOEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Transfer Speed\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SPEED_A { + #[doc = "0: Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz"] + STANDARD_AND_FAST_MODE = 0, + #[doc = "1: Fast-mode Plus Upto 1MHz"] + FASTPLUS_MODE = 1, + #[doc = "2: High-speed mode Upto 3.4MHz"] + HIGH_SPEED_MODE = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SPEED_A) -> Self { + variant as _ + } +} +#[doc = "Field `SPEED` reader - Transfer Speed"] +pub struct SPEED_R(crate::FieldReader); +impl SPEED_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SPEED_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SPEED_A::STANDARD_AND_FAST_MODE), + 1 => Some(SPEED_A::FASTPLUS_MODE), + 2 => Some(SPEED_A::HIGH_SPEED_MODE), + _ => None, + } + } + #[doc = "Checks if the value of the field is `STANDARD_AND_FAST_MODE`"] + #[inline(always)] + pub fn is_standard_and_fast_mode(&self) -> bool { + **self == SPEED_A::STANDARD_AND_FAST_MODE + } + #[doc = "Checks if the value of the field is `FASTPLUS_MODE`"] + #[inline(always)] + pub fn is_fastplus_mode(&self) -> bool { + **self == SPEED_A::FASTPLUS_MODE + } + #[doc = "Checks if the value of the field is `HIGH_SPEED_MODE`"] + #[inline(always)] + pub fn is_high_speed_mode(&self) -> bool { + **self == SPEED_A::HIGH_SPEED_MODE + } +} +impl core::ops::Deref for SPEED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SPEED` writer - Transfer Speed"] +pub struct SPEED_W<'a> { + w: &'a mut W, +} +impl<'a> SPEED_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SPEED_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz"] + #[inline(always)] + pub fn standard_and_fast_mode(self) -> &'a mut W { + self.variant(SPEED_A::STANDARD_AND_FAST_MODE) + } + #[doc = "Fast-mode Plus Upto 1MHz"] + #[inline(always)] + pub fn fastplus_mode(self) -> &'a mut W { + self.variant(SPEED_A::FASTPLUS_MODE) + } + #[doc = "High-speed mode Upto 3.4MHz"] + #[inline(always)] + pub fn high_speed_mode(self) -> &'a mut W { + self.variant(SPEED_A::HIGH_SPEED_MODE) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 24)) | ((value as u32 & 0x03) << 24); + self.w + } +} +#[doc = "Field `SCLSM` reader - SCL Clock Stretch Mode"] +pub struct SCLSM_R(crate::FieldReader); +impl SCLSM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SCLSM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SCLSM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SCLSM` writer - SCL Clock Stretch Mode"] +pub struct SCLSM_W<'a> { + w: &'a mut W, +} +impl<'a> SCLSM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +#[doc = "Inactive Time-Out\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum INACTOUT_A { + #[doc = "0: Disabled"] + DISABLE = 0, + #[doc = "1: 5-6 SCL Time-Out(50-60us)"] + _55US = 1, + #[doc = "2: 10-11 SCL Time-Out(100-110us)"] + _105US = 2, + #[doc = "3: 20-21 SCL Time-Out(200-210us)"] + _205US = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: INACTOUT_A) -> Self { + variant as _ + } +} +#[doc = "Field `INACTOUT` reader - Inactive Time-Out"] +pub struct INACTOUT_R(crate::FieldReader); +impl INACTOUT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + INACTOUT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INACTOUT_A { + match self.bits { + 0 => INACTOUT_A::DISABLE, + 1 => INACTOUT_A::_55US, + 2 => INACTOUT_A::_105US, + 3 => INACTOUT_A::_205US, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == INACTOUT_A::DISABLE + } + #[doc = "Checks if the value of the field is `_55US`"] + #[inline(always)] + pub fn is_55us(&self) -> bool { + **self == INACTOUT_A::_55US + } + #[doc = "Checks if the value of the field is `_105US`"] + #[inline(always)] + pub fn is_105us(&self) -> bool { + **self == INACTOUT_A::_105US + } + #[doc = "Checks if the value of the field is `_205US`"] + #[inline(always)] + pub fn is_205us(&self) -> bool { + **self == INACTOUT_A::_205US + } +} +impl core::ops::Deref for INACTOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INACTOUT` writer - Inactive Time-Out"] +pub struct INACTOUT_W<'a> { + w: &'a mut W, +} +impl<'a> INACTOUT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: INACTOUT_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(INACTOUT_A::DISABLE) + } + #[doc = "5-6 SCL Time-Out(50-60us)"] + #[inline(always)] + pub fn _55us(self) -> &'a mut W { + self.variant(INACTOUT_A::_55US) + } + #[doc = "10-11 SCL Time-Out(100-110us)"] + #[inline(always)] + pub fn _105us(self) -> &'a mut W { + self.variant(INACTOUT_A::_105US) + } + #[doc = "20-21 SCL Time-Out(200-210us)"] + #[inline(always)] + pub fn _205us(self) -> &'a mut W { + self.variant(INACTOUT_A::_205US) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 28)) | ((value as u32 & 0x03) << 28); + self.w + } +} +#[doc = "Field `LOWTOUTEN` reader - SCL Low Timeout Enable"] +pub struct LOWTOUTEN_R(crate::FieldReader); +impl LOWTOUTEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LOWTOUTEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOWTOUTEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LOWTOUTEN` writer - SCL Low Timeout Enable"] +pub struct LOWTOUTEN_W<'a> { + w: &'a mut W, +} +impl<'a> LOWTOUTEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x07) as u8) + } + #[doc = "Bit 7 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 16 - Pin Usage"] + #[inline(always)] + pub fn pinout(&self) -> PINOUT_R { + PINOUT_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bits 20:21 - SDA Hold Time"] + #[inline(always)] + pub fn sdahold(&self) -> SDAHOLD_R { + SDAHOLD_R::new(((self.bits >> 20) & 0x03) as u8) + } + #[doc = "Bit 22 - Master SCL Low Extend Timeout"] + #[inline(always)] + pub fn mexttoen(&self) -> MEXTTOEN_R { + MEXTTOEN_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttoen(&self) -> SEXTTOEN_R { + SEXTTOEN_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bits 24:25 - Transfer Speed"] + #[inline(always)] + pub fn speed(&self) -> SPEED_R { + SPEED_R::new(((self.bits >> 24) & 0x03) as u8) + } + #[doc = "Bit 27 - SCL Clock Stretch Mode"] + #[inline(always)] + pub fn sclsm(&self) -> SCLSM_R { + SCLSM_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bits 28:29 - Inactive Time-Out"] + #[inline(always)] + pub fn inactout(&self) -> INACTOUT_R { + INACTOUT_R::new(((self.bits >> 28) & 0x03) as u8) + } + #[doc = "Bit 30 - SCL Low Timeout Enable"] + #[inline(always)] + pub fn lowtouten(&self) -> LOWTOUTEN_R { + LOWTOUTEN_R::new(((self.bits >> 30) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 7 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 16 - Pin Usage"] + #[inline(always)] + pub fn pinout(&mut self) -> PINOUT_W { + PINOUT_W { w: self } + } + #[doc = "Bits 20:21 - SDA Hold Time"] + #[inline(always)] + pub fn sdahold(&mut self) -> SDAHOLD_W { + SDAHOLD_W { w: self } + } + #[doc = "Bit 22 - Master SCL Low Extend Timeout"] + #[inline(always)] + pub fn mexttoen(&mut self) -> MEXTTOEN_W { + MEXTTOEN_W { w: self } + } + #[doc = "Bit 23 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttoen(&mut self) -> SEXTTOEN_W { + SEXTTOEN_W { w: self } + } + #[doc = "Bits 24:25 - Transfer Speed"] + #[inline(always)] + pub fn speed(&mut self) -> SPEED_W { + SPEED_W { w: self } + } + #[doc = "Bit 27 - SCL Clock Stretch Mode"] + #[inline(always)] + pub fn sclsm(&mut self) -> SCLSM_W { + SCLSM_W { w: self } + } + #[doc = "Bits 28:29 - Inactive Time-Out"] + #[inline(always)] + pub fn inactout(&mut self) -> INACTOUT_W { + INACTOUT_W { w: self } + } + #[doc = "Bit 30 - SCL Low Timeout Enable"] + #[inline(always)] + pub fn lowtouten(&mut self) -> LOWTOUTEN_W { + LOWTOUTEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sercom0/i2cm/ctrlb.rs b/pac/atsamc21g/src/sercom0/i2cm/ctrlb.rs new file mode 100644 index 000000000000..ce534463c0da --- /dev/null +++ b/pac/atsamc21g/src/sercom0/i2cm/ctrlb.rs @@ -0,0 +1,244 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SMEN` reader - Smart Mode Enable"] +pub struct SMEN_R(crate::FieldReader); +impl SMEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SMEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SMEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SMEN` writer - Smart Mode Enable"] +pub struct SMEN_W<'a> { + w: &'a mut W, +} +impl<'a> SMEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `QCEN` reader - Quick Command Enable"] +pub struct QCEN_R(crate::FieldReader); +impl QCEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + QCEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for QCEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `QCEN` writer - Quick Command Enable"] +pub struct QCEN_W<'a> { + w: &'a mut W, +} +impl<'a> QCEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Field `ACKACT` reader - Acknowledge Action"] +pub struct ACKACT_R(crate::FieldReader); +impl ACKACT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ACKACT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ACKACT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ACKACT` writer - Acknowledge Action"] +pub struct ACKACT_W<'a> { + w: &'a mut W, +} +impl<'a> ACKACT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +impl R { + #[doc = "Bit 8 - Smart Mode Enable"] + #[inline(always)] + pub fn smen(&self) -> SMEN_R { + SMEN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Quick Command Enable"] + #[inline(always)] + pub fn qcen(&self) -> QCEN_R { + QCEN_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bits 16:17 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bit 18 - Acknowledge Action"] + #[inline(always)] + pub fn ackact(&self) -> ACKACT_R { + ACKACT_R::new(((self.bits >> 18) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 8 - Smart Mode Enable"] + #[inline(always)] + pub fn smen(&mut self) -> SMEN_W { + SMEN_W { w: self } + } + #[doc = "Bit 9 - Quick Command Enable"] + #[inline(always)] + pub fn qcen(&mut self) -> QCEN_W { + QCEN_W { w: self } + } + #[doc = "Bits 16:17 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Bit 18 - Acknowledge Action"] + #[inline(always)] + pub fn ackact(&mut self) -> ACKACT_W { + ACKACT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sercom0/i2cm/data.rs b/pac/atsamc21g/src/sercom0/i2cm/data.rs new file mode 100644 index 000000000000..cf204596d3a6 --- /dev/null +++ b/pac/atsamc21g/src/sercom0/i2cm/data.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data Value"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data Value"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Data Value"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Value"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sercom0/i2cm/dbgctrl.rs b/pac/atsamc21g/src/sercom0/i2cm/dbgctrl.rs new file mode 100644 index 000000000000..0fffdb4c6e39 --- /dev/null +++ b/pac/atsamc21g/src/sercom0/i2cm/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGSTOP` reader - Debug Mode"] +pub struct DBGSTOP_R(crate::FieldReader); +impl DBGSTOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGSTOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGSTOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGSTOP` writer - Debug Mode"] +pub struct DBGSTOP_W<'a> { + w: &'a mut W, +} +impl<'a> DBGSTOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&self) -> DBGSTOP_R { + DBGSTOP_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&mut self) -> DBGSTOP_W { + DBGSTOP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sercom0/i2cm/intenclr.rs b/pac/atsamc21g/src/sercom0/i2cm/intenclr.rs new file mode 100644 index 000000000000..17f067a55656 --- /dev/null +++ b/pac/atsamc21g/src/sercom0/i2cm/intenclr.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MB` reader - Master On Bus Interrupt Disable"] +pub struct MB_R(crate::FieldReader); +impl MB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MB` writer - Master On Bus Interrupt Disable"] +pub struct MB_W<'a> { + w: &'a mut W, +} +impl<'a> MB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SB` reader - Slave On Bus Interrupt Disable"] +pub struct SB_R(crate::FieldReader); +impl SB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SB` writer - Slave On Bus Interrupt Disable"] +pub struct SB_W<'a> { + w: &'a mut W, +} +impl<'a> SB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Disable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Disable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Master On Bus Interrupt Disable"] + #[inline(always)] + pub fn mb(&self) -> MB_R { + MB_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Slave On Bus Interrupt Disable"] + #[inline(always)] + pub fn sb(&self) -> SB_R { + SB_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Master On Bus Interrupt Disable"] + #[inline(always)] + pub fn mb(&mut self) -> MB_W { + MB_W { w: self } + } + #[doc = "Bit 1 - Slave On Bus Interrupt Disable"] + #[inline(always)] + pub fn sb(&mut self) -> SB_W { + SB_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sercom0/i2cm/intenset.rs b/pac/atsamc21g/src/sercom0/i2cm/intenset.rs new file mode 100644 index 000000000000..a0cbf96b3aa0 --- /dev/null +++ b/pac/atsamc21g/src/sercom0/i2cm/intenset.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MB` reader - Master On Bus Interrupt Enable"] +pub struct MB_R(crate::FieldReader); +impl MB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MB` writer - Master On Bus Interrupt Enable"] +pub struct MB_W<'a> { + w: &'a mut W, +} +impl<'a> MB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SB` reader - Slave On Bus Interrupt Enable"] +pub struct SB_R(crate::FieldReader); +impl SB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SB` writer - Slave On Bus Interrupt Enable"] +pub struct SB_W<'a> { + w: &'a mut W, +} +impl<'a> SB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Master On Bus Interrupt Enable"] + #[inline(always)] + pub fn mb(&self) -> MB_R { + MB_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Slave On Bus Interrupt Enable"] + #[inline(always)] + pub fn sb(&self) -> SB_R { + SB_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Master On Bus Interrupt Enable"] + #[inline(always)] + pub fn mb(&mut self) -> MB_W { + MB_W { w: self } + } + #[doc = "Bit 1 - Slave On Bus Interrupt Enable"] + #[inline(always)] + pub fn sb(&mut self) -> SB_W { + SB_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sercom0/i2cm/intflag.rs b/pac/atsamc21g/src/sercom0/i2cm/intflag.rs new file mode 100644 index 000000000000..0fb0d2b9060c --- /dev/null +++ b/pac/atsamc21g/src/sercom0/i2cm/intflag.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MB` reader - Master On Bus Interrupt"] +pub struct MB_R(crate::FieldReader); +impl MB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MB` writer - Master On Bus Interrupt"] +pub struct MB_W<'a> { + w: &'a mut W, +} +impl<'a> MB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SB` reader - Slave On Bus Interrupt"] +pub struct SB_R(crate::FieldReader); +impl SB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SB` writer - Slave On Bus Interrupt"] +pub struct SB_W<'a> { + w: &'a mut W, +} +impl<'a> SB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Master On Bus Interrupt"] + #[inline(always)] + pub fn mb(&self) -> MB_R { + MB_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Slave On Bus Interrupt"] + #[inline(always)] + pub fn sb(&self) -> SB_R { + SB_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Master On Bus Interrupt"] + #[inline(always)] + pub fn mb(&mut self) -> MB_W { + MB_W { w: self } + } + #[doc = "Bit 1 - Slave On Bus Interrupt"] + #[inline(always)] + pub fn sb(&mut self) -> SB_W { + SB_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sercom0/i2cm/status.rs b/pac/atsamc21g/src/sercom0/i2cm/status.rs new file mode 100644 index 000000000000..95af23673ec4 --- /dev/null +++ b/pac/atsamc21g/src/sercom0/i2cm/status.rs @@ -0,0 +1,479 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BUSERR` reader - Bus Error"] +pub struct BUSERR_R(crate::FieldReader); +impl BUSERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSERR` writer - Bus Error"] +pub struct BUSERR_W<'a> { + w: &'a mut W, +} +impl<'a> BUSERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `ARBLOST` reader - Arbitration Lost"] +pub struct ARBLOST_R(crate::FieldReader); +impl ARBLOST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ARBLOST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ARBLOST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ARBLOST` writer - Arbitration Lost"] +pub struct ARBLOST_W<'a> { + w: &'a mut W, +} +impl<'a> ARBLOST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXNACK` reader - Received Not Acknowledge"] +pub struct RXNACK_R(crate::FieldReader); +impl RXNACK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXNACK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXNACK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXNACK` writer - Received Not Acknowledge"] +pub struct RXNACK_W<'a> { + w: &'a mut W, +} +impl<'a> RXNACK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `BUSSTATE` reader - Bus State"] +pub struct BUSSTATE_R(crate::FieldReader); +impl BUSSTATE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BUSSTATE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSSTATE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSSTATE` writer - Bus State"] +pub struct BUSSTATE_W<'a> { + w: &'a mut W, +} +impl<'a> BUSSTATE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u16 & 0x03) << 4); + self.w + } +} +#[doc = "Field `LOWTOUT` reader - SCL Low Timeout"] +pub struct LOWTOUT_R(crate::FieldReader); +impl LOWTOUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LOWTOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOWTOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LOWTOUT` writer - SCL Low Timeout"] +pub struct LOWTOUT_W<'a> { + w: &'a mut W, +} +impl<'a> LOWTOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `CLKHOLD` reader - Clock Hold"] +pub struct CLKHOLD_R(crate::FieldReader); +impl CLKHOLD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKHOLD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKHOLD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKHOLD` writer - Clock Hold"] +pub struct CLKHOLD_W<'a> { + w: &'a mut W, +} +impl<'a> CLKHOLD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `MEXTTOUT` reader - Master SCL Low Extend Timeout"] +pub struct MEXTTOUT_R(crate::FieldReader); +impl MEXTTOUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MEXTTOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MEXTTOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MEXTTOUT` writer - Master SCL Low Extend Timeout"] +pub struct MEXTTOUT_W<'a> { + w: &'a mut W, +} +impl<'a> MEXTTOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `SEXTTOUT` reader - Slave SCL Low Extend Timeout"] +pub struct SEXTTOUT_R(crate::FieldReader); +impl SEXTTOUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SEXTTOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEXTTOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEXTTOUT` writer - Slave SCL Low Extend Timeout"] +pub struct SEXTTOUT_W<'a> { + w: &'a mut W, +} +impl<'a> SEXTTOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `LENERR` reader - Length Error"] +pub struct LENERR_R(crate::FieldReader); +impl LENERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LENERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LENERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LENERR` writer - Length Error"] +pub struct LENERR_W<'a> { + w: &'a mut W, +} +impl<'a> LENERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u16 & 0x01) << 10); + self.w + } +} +impl R { + #[doc = "Bit 0 - Bus Error"] + #[inline(always)] + pub fn buserr(&self) -> BUSERR_R { + BUSERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Arbitration Lost"] + #[inline(always)] + pub fn arblost(&self) -> ARBLOST_R { + ARBLOST_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Received Not Acknowledge"] + #[inline(always)] + pub fn rxnack(&self) -> RXNACK_R { + RXNACK_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 4:5 - Bus State"] + #[inline(always)] + pub fn busstate(&self) -> BUSSTATE_R { + BUSSTATE_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bit 6 - SCL Low Timeout"] + #[inline(always)] + pub fn lowtout(&self) -> LOWTOUT_R { + LOWTOUT_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Clock Hold"] + #[inline(always)] + pub fn clkhold(&self) -> CLKHOLD_R { + CLKHOLD_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Master SCL Low Extend Timeout"] + #[inline(always)] + pub fn mexttout(&self) -> MEXTTOUT_R { + MEXTTOUT_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttout(&self) -> SEXTTOUT_R { + SEXTTOUT_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Length Error"] + #[inline(always)] + pub fn lenerr(&self) -> LENERR_R { + LENERR_R::new(((self.bits >> 10) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Bus Error"] + #[inline(always)] + pub fn buserr(&mut self) -> BUSERR_W { + BUSERR_W { w: self } + } + #[doc = "Bit 1 - Arbitration Lost"] + #[inline(always)] + pub fn arblost(&mut self) -> ARBLOST_W { + ARBLOST_W { w: self } + } + #[doc = "Bit 2 - Received Not Acknowledge"] + #[inline(always)] + pub fn rxnack(&mut self) -> RXNACK_W { + RXNACK_W { w: self } + } + #[doc = "Bits 4:5 - Bus State"] + #[inline(always)] + pub fn busstate(&mut self) -> BUSSTATE_W { + BUSSTATE_W { w: self } + } + #[doc = "Bit 6 - SCL Low Timeout"] + #[inline(always)] + pub fn lowtout(&mut self) -> LOWTOUT_W { + LOWTOUT_W { w: self } + } + #[doc = "Bit 7 - Clock Hold"] + #[inline(always)] + pub fn clkhold(&mut self) -> CLKHOLD_W { + CLKHOLD_W { w: self } + } + #[doc = "Bit 8 - Master SCL Low Extend Timeout"] + #[inline(always)] + pub fn mexttout(&mut self) -> MEXTTOUT_W { + MEXTTOUT_W { w: self } + } + #[doc = "Bit 9 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttout(&mut self) -> SEXTTOUT_W { + SEXTTOUT_W { w: self } + } + #[doc = "Bit 10 - Length Error"] + #[inline(always)] + pub fn lenerr(&mut self) -> LENERR_W { + LENERR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sercom0/i2cm/syncbusy.rs b/pac/atsamc21g/src/sercom0/i2cm/syncbusy.rs new file mode 100644 index 000000000000..87dd418d1cd3 --- /dev/null +++ b/pac/atsamc21g/src/sercom0/i2cm/syncbusy.rs @@ -0,0 +1,93 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - SERCOM Enable Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYSOP` reader - System Operation Synchronization Busy"] +pub struct SYSOP_R(crate::FieldReader); +impl SYSOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYSOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYSOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM Enable Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - System Operation Synchronization Busy"] + #[inline(always)] + pub fn sysop(&self) -> SYSOP_R { + SYSOP_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +#[doc = "I2CM Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sercom0/i2cs.rs b/pac/atsamc21g/src/sercom0/i2cs.rs new file mode 100644 index 000000000000..baf9513c6cc1 --- /dev/null +++ b/pac/atsamc21g/src/sercom0/i2cs.rs @@ -0,0 +1,36 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "I2CS Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "I2CS Control B"] +pub mod ctrlb; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "I2CS Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "I2CS Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "I2CS Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "I2CS Status"] +pub mod status; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "I2CS Synchronization Busy"] +pub mod syncbusy; +#[doc = "ADDR register accessor: an alias for `Reg`"] +pub type ADDR = crate::Reg; +#[doc = "I2CS Address"] +pub mod addr; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "I2CS Data"] +pub mod data; diff --git a/pac/atsamc21g/src/sercom0/i2cs/addr.rs b/pac/atsamc21g/src/sercom0/i2cs/addr.rs new file mode 100644 index 000000000000..c1b69ee22891 --- /dev/null +++ b/pac/atsamc21g/src/sercom0/i2cs/addr.rs @@ -0,0 +1,234 @@ +#[doc = "Register `ADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `GENCEN` reader - General Call Address Enable"] +pub struct GENCEN_R(crate::FieldReader); +impl GENCEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENCEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENCEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENCEN` writer - General Call Address Enable"] +pub struct GENCEN_W<'a> { + w: &'a mut W, +} +impl<'a> GENCEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ADDR` reader - Address Value"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - Address Value"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03ff << 1)) | ((value as u32 & 0x03ff) << 1); + self.w + } +} +#[doc = "Field `TENBITEN` reader - Ten Bit Addressing Enable"] +pub struct TENBITEN_R(crate::FieldReader); +impl TENBITEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TENBITEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TENBITEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TENBITEN` writer - Ten Bit Addressing Enable"] +pub struct TENBITEN_W<'a> { + w: &'a mut W, +} +impl<'a> TENBITEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `ADDRMASK` reader - Address Mask"] +pub struct ADDRMASK_R(crate::FieldReader); +impl ADDRMASK_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + ADDRMASK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDRMASK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDRMASK` writer - Address Mask"] +pub struct ADDRMASK_W<'a> { + w: &'a mut W, +} +impl<'a> ADDRMASK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03ff << 17)) | ((value as u32 & 0x03ff) << 17); + self.w + } +} +impl R { + #[doc = "Bit 0 - General Call Address Enable"] + #[inline(always)] + pub fn gencen(&self) -> GENCEN_R { + GENCEN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bits 1:10 - Address Value"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new(((self.bits >> 1) & 0x03ff) as u16) + } + #[doc = "Bit 15 - Ten Bit Addressing Enable"] + #[inline(always)] + pub fn tenbiten(&self) -> TENBITEN_R { + TENBITEN_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 17:26 - Address Mask"] + #[inline(always)] + pub fn addrmask(&self) -> ADDRMASK_R { + ADDRMASK_R::new(((self.bits >> 17) & 0x03ff) as u16) + } +} +impl W { + #[doc = "Bit 0 - General Call Address Enable"] + #[inline(always)] + pub fn gencen(&mut self) -> GENCEN_W { + GENCEN_W { w: self } + } + #[doc = "Bits 1:10 - Address Value"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Bit 15 - Ten Bit Addressing Enable"] + #[inline(always)] + pub fn tenbiten(&mut self) -> TENBITEN_W { + TENBITEN_W { w: self } + } + #[doc = "Bits 17:26 - Address Mask"] + #[inline(always)] + pub fn addrmask(&mut self) -> ADDRMASK_W { + ADDRMASK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [addr](index.html) module"] +pub struct ADDR_SPEC; +impl crate::RegisterSpec for ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [addr::R](R) reader structure"] +impl crate::Readable for ADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [addr::W](W) writer structure"] +impl crate::Writable for ADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ADDR to value 0"] +impl crate::Resettable for ADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sercom0/i2cs/ctrla.rs b/pac/atsamc21g/src/sercom0/i2cs/ctrla.rs new file mode 100644 index 000000000000..ec93812b004f --- /dev/null +++ b/pac/atsamc21g/src/sercom0/i2cs/ctrla.rs @@ -0,0 +1,744 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: USART with external clock"] + USART_EXT_CLK = 0, + #[doc = "1: USART with internal clock"] + USART_INT_CLK = 1, + #[doc = "2: SPI in slave operation"] + SPI_SLAVE = 2, + #[doc = "3: SPI in master operation"] + SPI_MASTER = 3, + #[doc = "4: I2C slave operation"] + I2C_SLAVE = 4, + #[doc = "5: I2C master operation"] + I2C_MASTER = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::USART_EXT_CLK), + 1 => Some(MODE_A::USART_INT_CLK), + 2 => Some(MODE_A::SPI_SLAVE), + 3 => Some(MODE_A::SPI_MASTER), + 4 => Some(MODE_A::I2C_SLAVE), + 5 => Some(MODE_A::I2C_MASTER), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_EXT_CLK`"] + #[inline(always)] + pub fn is_usart_ext_clk(&self) -> bool { + **self == MODE_A::USART_EXT_CLK + } + #[doc = "Checks if the value of the field is `USART_INT_CLK`"] + #[inline(always)] + pub fn is_usart_int_clk(&self) -> bool { + **self == MODE_A::USART_INT_CLK + } + #[doc = "Checks if the value of the field is `SPI_SLAVE`"] + #[inline(always)] + pub fn is_spi_slave(&self) -> bool { + **self == MODE_A::SPI_SLAVE + } + #[doc = "Checks if the value of the field is `SPI_MASTER`"] + #[inline(always)] + pub fn is_spi_master(&self) -> bool { + **self == MODE_A::SPI_MASTER + } + #[doc = "Checks if the value of the field is `I2C_SLAVE`"] + #[inline(always)] + pub fn is_i2c_slave(&self) -> bool { + **self == MODE_A::I2C_SLAVE + } + #[doc = "Checks if the value of the field is `I2C_MASTER`"] + #[inline(always)] + pub fn is_i2c_master(&self) -> bool { + **self == MODE_A::I2C_MASTER + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART with external clock"] + #[inline(always)] + pub fn usart_ext_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_EXT_CLK) + } + #[doc = "USART with internal clock"] + #[inline(always)] + pub fn usart_int_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_INT_CLK) + } + #[doc = "SPI in slave operation"] + #[inline(always)] + pub fn spi_slave(self) -> &'a mut W { + self.variant(MODE_A::SPI_SLAVE) + } + #[doc = "SPI in master operation"] + #[inline(always)] + pub fn spi_master(self) -> &'a mut W { + self.variant(MODE_A::SPI_MASTER) + } + #[doc = "I2C slave operation"] + #[inline(always)] + pub fn i2c_slave(self) -> &'a mut W { + self.variant(MODE_A::I2C_SLAVE) + } + #[doc = "I2C master operation"] + #[inline(always)] + pub fn i2c_master(self) -> &'a mut W { + self.variant(MODE_A::I2C_MASTER) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 2)) | ((value as u32 & 0x07) << 2); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `PINOUT` reader - Pin Usage"] +pub struct PINOUT_R(crate::FieldReader); +impl PINOUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PINOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PINOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PINOUT` writer - Pin Usage"] +pub struct PINOUT_W<'a> { + w: &'a mut W, +} +impl<'a> PINOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "SDA Hold Time\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SDAHOLD_A { + #[doc = "0: Disabled"] + DISABLE = 0, + #[doc = "1: 50-100ns hold time"] + _75NS = 1, + #[doc = "2: 300-600ns hold time"] + _450NS = 2, + #[doc = "3: 400-800ns hold time"] + _600NS = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SDAHOLD_A) -> Self { + variant as _ + } +} +#[doc = "Field `SDAHOLD` reader - SDA Hold Time"] +pub struct SDAHOLD_R(crate::FieldReader); +impl SDAHOLD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SDAHOLD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SDAHOLD_A { + match self.bits { + 0 => SDAHOLD_A::DISABLE, + 1 => SDAHOLD_A::_75NS, + 2 => SDAHOLD_A::_450NS, + 3 => SDAHOLD_A::_600NS, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == SDAHOLD_A::DISABLE + } + #[doc = "Checks if the value of the field is `_75NS`"] + #[inline(always)] + pub fn is_75ns(&self) -> bool { + **self == SDAHOLD_A::_75NS + } + #[doc = "Checks if the value of the field is `_450NS`"] + #[inline(always)] + pub fn is_450ns(&self) -> bool { + **self == SDAHOLD_A::_450NS + } + #[doc = "Checks if the value of the field is `_600NS`"] + #[inline(always)] + pub fn is_600ns(&self) -> bool { + **self == SDAHOLD_A::_600NS + } +} +impl core::ops::Deref for SDAHOLD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SDAHOLD` writer - SDA Hold Time"] +pub struct SDAHOLD_W<'a> { + w: &'a mut W, +} +impl<'a> SDAHOLD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SDAHOLD_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(SDAHOLD_A::DISABLE) + } + #[doc = "50-100ns hold time"] + #[inline(always)] + pub fn _75ns(self) -> &'a mut W { + self.variant(SDAHOLD_A::_75NS) + } + #[doc = "300-600ns hold time"] + #[inline(always)] + pub fn _450ns(self) -> &'a mut W { + self.variant(SDAHOLD_A::_450NS) + } + #[doc = "400-800ns hold time"] + #[inline(always)] + pub fn _600ns(self) -> &'a mut W { + self.variant(SDAHOLD_A::_600NS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 20)) | ((value as u32 & 0x03) << 20); + self.w + } +} +#[doc = "Field `SEXTTOEN` reader - Slave SCL Low Extend Timeout"] +pub struct SEXTTOEN_R(crate::FieldReader); +impl SEXTTOEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SEXTTOEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEXTTOEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEXTTOEN` writer - Slave SCL Low Extend Timeout"] +pub struct SEXTTOEN_W<'a> { + w: &'a mut W, +} +impl<'a> SEXTTOEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Transfer Speed\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SPEED_A { + #[doc = "0: Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz"] + STANDARD_AND_FAST_MODE = 0, + #[doc = "1: Fast-mode Plus Upto 1MHz"] + FASTPLUS_MODE = 1, + #[doc = "2: High-speed mode Upto 3.4MHz"] + HIGH_SPEED_MODE = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SPEED_A) -> Self { + variant as _ + } +} +#[doc = "Field `SPEED` reader - Transfer Speed"] +pub struct SPEED_R(crate::FieldReader); +impl SPEED_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SPEED_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SPEED_A::STANDARD_AND_FAST_MODE), + 1 => Some(SPEED_A::FASTPLUS_MODE), + 2 => Some(SPEED_A::HIGH_SPEED_MODE), + _ => None, + } + } + #[doc = "Checks if the value of the field is `STANDARD_AND_FAST_MODE`"] + #[inline(always)] + pub fn is_standard_and_fast_mode(&self) -> bool { + **self == SPEED_A::STANDARD_AND_FAST_MODE + } + #[doc = "Checks if the value of the field is `FASTPLUS_MODE`"] + #[inline(always)] + pub fn is_fastplus_mode(&self) -> bool { + **self == SPEED_A::FASTPLUS_MODE + } + #[doc = "Checks if the value of the field is `HIGH_SPEED_MODE`"] + #[inline(always)] + pub fn is_high_speed_mode(&self) -> bool { + **self == SPEED_A::HIGH_SPEED_MODE + } +} +impl core::ops::Deref for SPEED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SPEED` writer - Transfer Speed"] +pub struct SPEED_W<'a> { + w: &'a mut W, +} +impl<'a> SPEED_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SPEED_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz"] + #[inline(always)] + pub fn standard_and_fast_mode(self) -> &'a mut W { + self.variant(SPEED_A::STANDARD_AND_FAST_MODE) + } + #[doc = "Fast-mode Plus Upto 1MHz"] + #[inline(always)] + pub fn fastplus_mode(self) -> &'a mut W { + self.variant(SPEED_A::FASTPLUS_MODE) + } + #[doc = "High-speed mode Upto 3.4MHz"] + #[inline(always)] + pub fn high_speed_mode(self) -> &'a mut W { + self.variant(SPEED_A::HIGH_SPEED_MODE) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 24)) | ((value as u32 & 0x03) << 24); + self.w + } +} +#[doc = "Field `SCLSM` reader - SCL Clock Stretch Mode"] +pub struct SCLSM_R(crate::FieldReader); +impl SCLSM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SCLSM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SCLSM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SCLSM` writer - SCL Clock Stretch Mode"] +pub struct SCLSM_W<'a> { + w: &'a mut W, +} +impl<'a> SCLSM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +#[doc = "Field `LOWTOUTEN` reader - SCL Low Timeout Enable"] +pub struct LOWTOUTEN_R(crate::FieldReader); +impl LOWTOUTEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LOWTOUTEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOWTOUTEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LOWTOUTEN` writer - SCL Low Timeout Enable"] +pub struct LOWTOUTEN_W<'a> { + w: &'a mut W, +} +impl<'a> LOWTOUTEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x07) as u8) + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 16 - Pin Usage"] + #[inline(always)] + pub fn pinout(&self) -> PINOUT_R { + PINOUT_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bits 20:21 - SDA Hold Time"] + #[inline(always)] + pub fn sdahold(&self) -> SDAHOLD_R { + SDAHOLD_R::new(((self.bits >> 20) & 0x03) as u8) + } + #[doc = "Bit 23 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttoen(&self) -> SEXTTOEN_R { + SEXTTOEN_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bits 24:25 - Transfer Speed"] + #[inline(always)] + pub fn speed(&self) -> SPEED_R { + SPEED_R::new(((self.bits >> 24) & 0x03) as u8) + } + #[doc = "Bit 27 - SCL Clock Stretch Mode"] + #[inline(always)] + pub fn sclsm(&self) -> SCLSM_R { + SCLSM_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 30 - SCL Low Timeout Enable"] + #[inline(always)] + pub fn lowtouten(&self) -> LOWTOUTEN_R { + LOWTOUTEN_R::new(((self.bits >> 30) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 16 - Pin Usage"] + #[inline(always)] + pub fn pinout(&mut self) -> PINOUT_W { + PINOUT_W { w: self } + } + #[doc = "Bits 20:21 - SDA Hold Time"] + #[inline(always)] + pub fn sdahold(&mut self) -> SDAHOLD_W { + SDAHOLD_W { w: self } + } + #[doc = "Bit 23 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttoen(&mut self) -> SEXTTOEN_W { + SEXTTOEN_W { w: self } + } + #[doc = "Bits 24:25 - Transfer Speed"] + #[inline(always)] + pub fn speed(&mut self) -> SPEED_W { + SPEED_W { w: self } + } + #[doc = "Bit 27 - SCL Clock Stretch Mode"] + #[inline(always)] + pub fn sclsm(&mut self) -> SCLSM_W { + SCLSM_W { w: self } + } + #[doc = "Bit 30 - SCL Low Timeout Enable"] + #[inline(always)] + pub fn lowtouten(&mut self) -> LOWTOUTEN_W { + LOWTOUTEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sercom0/i2cs/ctrlb.rs b/pac/atsamc21g/src/sercom0/i2cs/ctrlb.rs new file mode 100644 index 000000000000..b20f48581ed5 --- /dev/null +++ b/pac/atsamc21g/src/sercom0/i2cs/ctrlb.rs @@ -0,0 +1,328 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SMEN` reader - Smart Mode Enable"] +pub struct SMEN_R(crate::FieldReader); +impl SMEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SMEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SMEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SMEN` writer - Smart Mode Enable"] +pub struct SMEN_W<'a> { + w: &'a mut W, +} +impl<'a> SMEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `GCMD` reader - PMBus Group Command"] +pub struct GCMD_R(crate::FieldReader); +impl GCMD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GCMD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GCMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GCMD` writer - PMBus Group Command"] +pub struct GCMD_W<'a> { + w: &'a mut W, +} +impl<'a> GCMD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `AACKEN` reader - Automatic Address Acknowledge"] +pub struct AACKEN_R(crate::FieldReader); +impl AACKEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AACKEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AACKEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AACKEN` writer - Automatic Address Acknowledge"] +pub struct AACKEN_W<'a> { + w: &'a mut W, +} +impl<'a> AACKEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `AMODE` reader - Address Mode"] +pub struct AMODE_R(crate::FieldReader); +impl AMODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + AMODE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AMODE` writer - Address Mode"] +pub struct AMODE_W<'a> { + w: &'a mut W, +} +impl<'a> AMODE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 14)) | ((value as u32 & 0x03) << 14); + self.w + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Field `ACKACT` reader - Acknowledge Action"] +pub struct ACKACT_R(crate::FieldReader); +impl ACKACT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ACKACT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ACKACT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ACKACT` writer - Acknowledge Action"] +pub struct ACKACT_W<'a> { + w: &'a mut W, +} +impl<'a> ACKACT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +impl R { + #[doc = "Bit 8 - Smart Mode Enable"] + #[inline(always)] + pub fn smen(&self) -> SMEN_R { + SMEN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - PMBus Group Command"] + #[inline(always)] + pub fn gcmd(&self) -> GCMD_R { + GCMD_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Automatic Address Acknowledge"] + #[inline(always)] + pub fn aacken(&self) -> AACKEN_R { + AACKEN_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bits 14:15 - Address Mode"] + #[inline(always)] + pub fn amode(&self) -> AMODE_R { + AMODE_R::new(((self.bits >> 14) & 0x03) as u8) + } + #[doc = "Bits 16:17 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bit 18 - Acknowledge Action"] + #[inline(always)] + pub fn ackact(&self) -> ACKACT_R { + ACKACT_R::new(((self.bits >> 18) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 8 - Smart Mode Enable"] + #[inline(always)] + pub fn smen(&mut self) -> SMEN_W { + SMEN_W { w: self } + } + #[doc = "Bit 9 - PMBus Group Command"] + #[inline(always)] + pub fn gcmd(&mut self) -> GCMD_W { + GCMD_W { w: self } + } + #[doc = "Bit 10 - Automatic Address Acknowledge"] + #[inline(always)] + pub fn aacken(&mut self) -> AACKEN_W { + AACKEN_W { w: self } + } + #[doc = "Bits 14:15 - Address Mode"] + #[inline(always)] + pub fn amode(&mut self) -> AMODE_W { + AMODE_W { w: self } + } + #[doc = "Bits 16:17 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Bit 18 - Acknowledge Action"] + #[inline(always)] + pub fn ackact(&mut self) -> ACKACT_W { + ACKACT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sercom0/i2cs/data.rs b/pac/atsamc21g/src/sercom0/i2cs/data.rs new file mode 100644 index 000000000000..d8bfe070431a --- /dev/null +++ b/pac/atsamc21g/src/sercom0/i2cs/data.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data Value"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data Value"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Data Value"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Value"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sercom0/i2cs/intenclr.rs b/pac/atsamc21g/src/sercom0/i2cs/intenclr.rs new file mode 100644 index 000000000000..49f5191c8d63 --- /dev/null +++ b/pac/atsamc21g/src/sercom0/i2cs/intenclr.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PREC` reader - Stop Received Interrupt Disable"] +pub struct PREC_R(crate::FieldReader); +impl PREC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PREC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PREC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PREC` writer - Stop Received Interrupt Disable"] +pub struct PREC_W<'a> { + w: &'a mut W, +} +impl<'a> PREC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `AMATCH` reader - Address Match Interrupt Disable"] +pub struct AMATCH_R(crate::FieldReader); +impl AMATCH_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AMATCH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AMATCH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AMATCH` writer - Address Match Interrupt Disable"] +pub struct AMATCH_W<'a> { + w: &'a mut W, +} +impl<'a> AMATCH_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `DRDY` reader - Data Interrupt Disable"] +pub struct DRDY_R(crate::FieldReader); +impl DRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRDY` writer - Data Interrupt Disable"] +pub struct DRDY_W<'a> { + w: &'a mut W, +} +impl<'a> DRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Disable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Disable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Stop Received Interrupt Disable"] + #[inline(always)] + pub fn prec(&self) -> PREC_R { + PREC_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Address Match Interrupt Disable"] + #[inline(always)] + pub fn amatch(&self) -> AMATCH_R { + AMATCH_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Data Interrupt Disable"] + #[inline(always)] + pub fn drdy(&self) -> DRDY_R { + DRDY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Stop Received Interrupt Disable"] + #[inline(always)] + pub fn prec(&mut self) -> PREC_W { + PREC_W { w: self } + } + #[doc = "Bit 1 - Address Match Interrupt Disable"] + #[inline(always)] + pub fn amatch(&mut self) -> AMATCH_W { + AMATCH_W { w: self } + } + #[doc = "Bit 2 - Data Interrupt Disable"] + #[inline(always)] + pub fn drdy(&mut self) -> DRDY_W { + DRDY_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sercom0/i2cs/intenset.rs b/pac/atsamc21g/src/sercom0/i2cs/intenset.rs new file mode 100644 index 000000000000..97ea784d7476 --- /dev/null +++ b/pac/atsamc21g/src/sercom0/i2cs/intenset.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PREC` reader - Stop Received Interrupt Enable"] +pub struct PREC_R(crate::FieldReader); +impl PREC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PREC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PREC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PREC` writer - Stop Received Interrupt Enable"] +pub struct PREC_W<'a> { + w: &'a mut W, +} +impl<'a> PREC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `AMATCH` reader - Address Match Interrupt Enable"] +pub struct AMATCH_R(crate::FieldReader); +impl AMATCH_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AMATCH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AMATCH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AMATCH` writer - Address Match Interrupt Enable"] +pub struct AMATCH_W<'a> { + w: &'a mut W, +} +impl<'a> AMATCH_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `DRDY` reader - Data Interrupt Enable"] +pub struct DRDY_R(crate::FieldReader); +impl DRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRDY` writer - Data Interrupt Enable"] +pub struct DRDY_W<'a> { + w: &'a mut W, +} +impl<'a> DRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Stop Received Interrupt Enable"] + #[inline(always)] + pub fn prec(&self) -> PREC_R { + PREC_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Address Match Interrupt Enable"] + #[inline(always)] + pub fn amatch(&self) -> AMATCH_R { + AMATCH_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Data Interrupt Enable"] + #[inline(always)] + pub fn drdy(&self) -> DRDY_R { + DRDY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Stop Received Interrupt Enable"] + #[inline(always)] + pub fn prec(&mut self) -> PREC_W { + PREC_W { w: self } + } + #[doc = "Bit 1 - Address Match Interrupt Enable"] + #[inline(always)] + pub fn amatch(&mut self) -> AMATCH_W { + AMATCH_W { w: self } + } + #[doc = "Bit 2 - Data Interrupt Enable"] + #[inline(always)] + pub fn drdy(&mut self) -> DRDY_W { + DRDY_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sercom0/i2cs/intflag.rs b/pac/atsamc21g/src/sercom0/i2cs/intflag.rs new file mode 100644 index 000000000000..2eee333e4e59 --- /dev/null +++ b/pac/atsamc21g/src/sercom0/i2cs/intflag.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PREC` reader - Stop Received Interrupt"] +pub struct PREC_R(crate::FieldReader); +impl PREC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PREC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PREC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PREC` writer - Stop Received Interrupt"] +pub struct PREC_W<'a> { + w: &'a mut W, +} +impl<'a> PREC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `AMATCH` reader - Address Match Interrupt"] +pub struct AMATCH_R(crate::FieldReader); +impl AMATCH_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AMATCH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AMATCH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AMATCH` writer - Address Match Interrupt"] +pub struct AMATCH_W<'a> { + w: &'a mut W, +} +impl<'a> AMATCH_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `DRDY` reader - Data Interrupt"] +pub struct DRDY_R(crate::FieldReader); +impl DRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRDY` writer - Data Interrupt"] +pub struct DRDY_W<'a> { + w: &'a mut W, +} +impl<'a> DRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Stop Received Interrupt"] + #[inline(always)] + pub fn prec(&self) -> PREC_R { + PREC_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Address Match Interrupt"] + #[inline(always)] + pub fn amatch(&self) -> AMATCH_R { + AMATCH_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Data Interrupt"] + #[inline(always)] + pub fn drdy(&self) -> DRDY_R { + DRDY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Stop Received Interrupt"] + #[inline(always)] + pub fn prec(&mut self) -> PREC_W { + PREC_W { w: self } + } + #[doc = "Bit 1 - Address Match Interrupt"] + #[inline(always)] + pub fn amatch(&mut self) -> AMATCH_W { + AMATCH_W { w: self } + } + #[doc = "Bit 2 - Data Interrupt"] + #[inline(always)] + pub fn drdy(&mut self) -> DRDY_W { + DRDY_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sercom0/i2cs/status.rs b/pac/atsamc21g/src/sercom0/i2cs/status.rs new file mode 100644 index 000000000000..b3f6d218fa66 --- /dev/null +++ b/pac/atsamc21g/src/sercom0/i2cs/status.rs @@ -0,0 +1,489 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BUSERR` reader - Bus Error"] +pub struct BUSERR_R(crate::FieldReader); +impl BUSERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSERR` writer - Bus Error"] +pub struct BUSERR_W<'a> { + w: &'a mut W, +} +impl<'a> BUSERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `COLL` reader - Transmit Collision"] +pub struct COLL_R(crate::FieldReader); +impl COLL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COLL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COLL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COLL` writer - Transmit Collision"] +pub struct COLL_W<'a> { + w: &'a mut W, +} +impl<'a> COLL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXNACK` reader - Received Not Acknowledge"] +pub struct RXNACK_R(crate::FieldReader); +impl RXNACK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXNACK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXNACK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXNACK` writer - Received Not Acknowledge"] +pub struct RXNACK_W<'a> { + w: &'a mut W, +} +impl<'a> RXNACK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `DIR` reader - Read/Write Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Read/Write Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `SR` reader - Repeated Start"] +pub struct SR_R(crate::FieldReader); +impl SR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SR` writer - Repeated Start"] +pub struct SR_W<'a> { + w: &'a mut W, +} +impl<'a> SR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `LOWTOUT` reader - SCL Low Timeout"] +pub struct LOWTOUT_R(crate::FieldReader); +impl LOWTOUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LOWTOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOWTOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LOWTOUT` writer - SCL Low Timeout"] +pub struct LOWTOUT_W<'a> { + w: &'a mut W, +} +impl<'a> LOWTOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `CLKHOLD` reader - Clock Hold"] +pub struct CLKHOLD_R(crate::FieldReader); +impl CLKHOLD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKHOLD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKHOLD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKHOLD` writer - Clock Hold"] +pub struct CLKHOLD_W<'a> { + w: &'a mut W, +} +impl<'a> CLKHOLD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `SEXTTOUT` reader - Slave SCL Low Extend Timeout"] +pub struct SEXTTOUT_R(crate::FieldReader); +impl SEXTTOUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SEXTTOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEXTTOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEXTTOUT` writer - Slave SCL Low Extend Timeout"] +pub struct SEXTTOUT_W<'a> { + w: &'a mut W, +} +impl<'a> SEXTTOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `HS` reader - High Speed"] +pub struct HS_R(crate::FieldReader); +impl HS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HS` writer - High Speed"] +pub struct HS_W<'a> { + w: &'a mut W, +} +impl<'a> HS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u16 & 0x01) << 10); + self.w + } +} +impl R { + #[doc = "Bit 0 - Bus Error"] + #[inline(always)] + pub fn buserr(&self) -> BUSERR_R { + BUSERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Collision"] + #[inline(always)] + pub fn coll(&self) -> COLL_R { + COLL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Received Not Acknowledge"] + #[inline(always)] + pub fn rxnack(&self) -> RXNACK_R { + RXNACK_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Read/Write Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Repeated Start"] + #[inline(always)] + pub fn sr(&self) -> SR_R { + SR_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 6 - SCL Low Timeout"] + #[inline(always)] + pub fn lowtout(&self) -> LOWTOUT_R { + LOWTOUT_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Clock Hold"] + #[inline(always)] + pub fn clkhold(&self) -> CLKHOLD_R { + CLKHOLD_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 9 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttout(&self) -> SEXTTOUT_R { + SEXTTOUT_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - High Speed"] + #[inline(always)] + pub fn hs(&self) -> HS_R { + HS_R::new(((self.bits >> 10) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Bus Error"] + #[inline(always)] + pub fn buserr(&mut self) -> BUSERR_W { + BUSERR_W { w: self } + } + #[doc = "Bit 1 - Transmit Collision"] + #[inline(always)] + pub fn coll(&mut self) -> COLL_W { + COLL_W { w: self } + } + #[doc = "Bit 2 - Received Not Acknowledge"] + #[inline(always)] + pub fn rxnack(&mut self) -> RXNACK_W { + RXNACK_W { w: self } + } + #[doc = "Bit 3 - Read/Write Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 4 - Repeated Start"] + #[inline(always)] + pub fn sr(&mut self) -> SR_W { + SR_W { w: self } + } + #[doc = "Bit 6 - SCL Low Timeout"] + #[inline(always)] + pub fn lowtout(&mut self) -> LOWTOUT_W { + LOWTOUT_W { w: self } + } + #[doc = "Bit 7 - Clock Hold"] + #[inline(always)] + pub fn clkhold(&mut self) -> CLKHOLD_W { + CLKHOLD_W { w: self } + } + #[doc = "Bit 9 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttout(&mut self) -> SEXTTOUT_W { + SEXTTOUT_W { w: self } + } + #[doc = "Bit 10 - High Speed"] + #[inline(always)] + pub fn hs(&mut self) -> HS_W { + HS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sercom0/i2cs/syncbusy.rs b/pac/atsamc21g/src/sercom0/i2cs/syncbusy.rs new file mode 100644 index 000000000000..38e2509d9666 --- /dev/null +++ b/pac/atsamc21g/src/sercom0/i2cs/syncbusy.rs @@ -0,0 +1,73 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - SERCOM Enable Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM Enable Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +#[doc = "I2CS Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sercom0/spim.rs b/pac/atsamc21g/src/sercom0/spim.rs new file mode 100644 index 000000000000..528e38e1b811 --- /dev/null +++ b/pac/atsamc21g/src/sercom0/spim.rs @@ -0,0 +1,44 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "SPIM Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "SPIM Control B"] +pub mod ctrlb; +#[doc = "BAUD register accessor: an alias for `Reg`"] +pub type BAUD = crate::Reg; +#[doc = "SPIM Baud Rate"] +pub mod baud; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "SPIM Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "SPIM Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "SPIM Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "SPIM Status"] +pub mod status; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "SPIM Synchronization Busy"] +pub mod syncbusy; +#[doc = "ADDR register accessor: an alias for `Reg`"] +pub type ADDR = crate::Reg; +#[doc = "SPIM Address"] +pub mod addr; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "SPIM Data"] +pub mod data; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "SPIM Debug Control"] +pub mod dbgctrl; diff --git a/pac/atsamc21g/src/sercom0/spim/addr.rs b/pac/atsamc21g/src/sercom0/spim/addr.rs new file mode 100644 index 000000000000..7c25cd522ea2 --- /dev/null +++ b/pac/atsamc21g/src/sercom0/spim/addr.rs @@ -0,0 +1,140 @@ +#[doc = "Register `ADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ADDR` reader - Address Value"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - Address Value"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +#[doc = "Field `ADDRMASK` reader - Address Mask"] +pub struct ADDRMASK_R(crate::FieldReader); +impl ADDRMASK_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ADDRMASK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDRMASK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDRMASK` writer - Address Mask"] +pub struct ADDRMASK_W<'a> { + w: &'a mut W, +} +impl<'a> ADDRMASK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Address Value"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 16:23 - Address Mask"] + #[inline(always)] + pub fn addrmask(&self) -> ADDRMASK_R { + ADDRMASK_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Address Value"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Bits 16:23 - Address Mask"] + #[inline(always)] + pub fn addrmask(&mut self) -> ADDRMASK_W { + ADDRMASK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [addr](index.html) module"] +pub struct ADDR_SPEC; +impl crate::RegisterSpec for ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [addr::R](R) reader structure"] +impl crate::Readable for ADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [addr::W](W) writer structure"] +impl crate::Writable for ADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ADDR to value 0"] +impl crate::Resettable for ADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sercom0/spim/baud.rs b/pac/atsamc21g/src/sercom0/spim/baud.rs new file mode 100644 index 000000000000..6bec9ca74355 --- /dev/null +++ b/pac/atsamc21g/src/sercom0/spim/baud.rs @@ -0,0 +1,103 @@ +#[doc = "Register `BAUD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud](index.html) module"] +pub struct BAUD_SPEC; +impl crate::RegisterSpec for BAUD_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [baud::R](R) reader structure"] +impl crate::Readable for BAUD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud::W](W) writer structure"] +impl crate::Writable for BAUD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD to value 0"] +impl crate::Resettable for BAUD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sercom0/spim/ctrla.rs b/pac/atsamc21g/src/sercom0/spim/ctrla.rs new file mode 100644 index 000000000000..44028f8cbdd7 --- /dev/null +++ b/pac/atsamc21g/src/sercom0/spim/ctrla.rs @@ -0,0 +1,992 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: USART with external clock"] + USART_EXT_CLK = 0, + #[doc = "1: USART with internal clock"] + USART_INT_CLK = 1, + #[doc = "2: SPI in slave operation"] + SPI_SLAVE = 2, + #[doc = "3: SPI in master operation"] + SPI_MASTER = 3, + #[doc = "4: I2C slave operation"] + I2C_SLAVE = 4, + #[doc = "5: I2C master operation"] + I2C_MASTER = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::USART_EXT_CLK), + 1 => Some(MODE_A::USART_INT_CLK), + 2 => Some(MODE_A::SPI_SLAVE), + 3 => Some(MODE_A::SPI_MASTER), + 4 => Some(MODE_A::I2C_SLAVE), + 5 => Some(MODE_A::I2C_MASTER), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_EXT_CLK`"] + #[inline(always)] + pub fn is_usart_ext_clk(&self) -> bool { + **self == MODE_A::USART_EXT_CLK + } + #[doc = "Checks if the value of the field is `USART_INT_CLK`"] + #[inline(always)] + pub fn is_usart_int_clk(&self) -> bool { + **self == MODE_A::USART_INT_CLK + } + #[doc = "Checks if the value of the field is `SPI_SLAVE`"] + #[inline(always)] + pub fn is_spi_slave(&self) -> bool { + **self == MODE_A::SPI_SLAVE + } + #[doc = "Checks if the value of the field is `SPI_MASTER`"] + #[inline(always)] + pub fn is_spi_master(&self) -> bool { + **self == MODE_A::SPI_MASTER + } + #[doc = "Checks if the value of the field is `I2C_SLAVE`"] + #[inline(always)] + pub fn is_i2c_slave(&self) -> bool { + **self == MODE_A::I2C_SLAVE + } + #[doc = "Checks if the value of the field is `I2C_MASTER`"] + #[inline(always)] + pub fn is_i2c_master(&self) -> bool { + **self == MODE_A::I2C_MASTER + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART with external clock"] + #[inline(always)] + pub fn usart_ext_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_EXT_CLK) + } + #[doc = "USART with internal clock"] + #[inline(always)] + pub fn usart_int_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_INT_CLK) + } + #[doc = "SPI in slave operation"] + #[inline(always)] + pub fn spi_slave(self) -> &'a mut W { + self.variant(MODE_A::SPI_SLAVE) + } + #[doc = "SPI in master operation"] + #[inline(always)] + pub fn spi_master(self) -> &'a mut W { + self.variant(MODE_A::SPI_MASTER) + } + #[doc = "I2C slave operation"] + #[inline(always)] + pub fn i2c_slave(self) -> &'a mut W { + self.variant(MODE_A::I2C_SLAVE) + } + #[doc = "I2C master operation"] + #[inline(always)] + pub fn i2c_master(self) -> &'a mut W { + self.variant(MODE_A::I2C_MASTER) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 2)) | ((value as u32 & 0x07) << 2); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `IBON` reader - Immediate Buffer Overflow Notification"] +pub struct IBON_R(crate::FieldReader); +impl IBON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IBON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IBON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IBON` writer - Immediate Buffer Overflow Notification"] +pub struct IBON_W<'a> { + w: &'a mut W, +} +impl<'a> IBON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Data Out Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DOPO_A { + #[doc = "0: DO on PAD\\[0\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + PAD0 = 0, + #[doc = "1: DO on PAD\\[2\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + PAD1 = 1, + #[doc = "2: DO on PAD\\[3\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + PAD2 = 2, + #[doc = "3: DO on PAD\\[0\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + PAD3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DOPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `DOPO` reader - Data Out Pinout"] +pub struct DOPO_R(crate::FieldReader); +impl DOPO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DOPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DOPO_A { + match self.bits { + 0 => DOPO_A::PAD0, + 1 => DOPO_A::PAD1, + 2 => DOPO_A::PAD2, + 3 => DOPO_A::PAD3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == DOPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD1`"] + #[inline(always)] + pub fn is_pad1(&self) -> bool { + **self == DOPO_A::PAD1 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == DOPO_A::PAD2 + } + #[doc = "Checks if the value of the field is `PAD3`"] + #[inline(always)] + pub fn is_pad3(&self) -> bool { + **self == DOPO_A::PAD3 + } +} +impl core::ops::Deref for DOPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DOPO` writer - Data Out Pinout"] +pub struct DOPO_W<'a> { + w: &'a mut W, +} +impl<'a> DOPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DOPO_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "DO on PAD\\[0\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(DOPO_A::PAD0) + } + #[doc = "DO on PAD\\[2\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + #[inline(always)] + pub fn pad1(self) -> &'a mut W { + self.variant(DOPO_A::PAD1) + } + #[doc = "DO on PAD\\[3\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(DOPO_A::PAD2) + } + #[doc = "DO on PAD\\[0\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + #[inline(always)] + pub fn pad3(self) -> &'a mut W { + self.variant(DOPO_A::PAD3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Data In Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DIPO_A { + #[doc = "0: SERCOM PAD\\[0\\]"] + PAD0 = 0, + #[doc = "1: SERCOM PAD\\[1\\]"] + PAD1 = 1, + #[doc = "2: SERCOM PAD\\[2\\]"] + PAD2 = 2, + #[doc = "3: SERCOM PAD\\[3\\]"] + PAD3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DIPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `DIPO` reader - Data In Pinout"] +pub struct DIPO_R(crate::FieldReader); +impl DIPO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DIPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DIPO_A { + match self.bits { + 0 => DIPO_A::PAD0, + 1 => DIPO_A::PAD1, + 2 => DIPO_A::PAD2, + 3 => DIPO_A::PAD3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == DIPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD1`"] + #[inline(always)] + pub fn is_pad1(&self) -> bool { + **self == DIPO_A::PAD1 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == DIPO_A::PAD2 + } + #[doc = "Checks if the value of the field is `PAD3`"] + #[inline(always)] + pub fn is_pad3(&self) -> bool { + **self == DIPO_A::PAD3 + } +} +impl core::ops::Deref for DIPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIPO` writer - Data In Pinout"] +pub struct DIPO_W<'a> { + w: &'a mut W, +} +impl<'a> DIPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DIPO_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "SERCOM PAD\\[0\\]"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(DIPO_A::PAD0) + } + #[doc = "SERCOM PAD\\[1\\]"] + #[inline(always)] + pub fn pad1(self) -> &'a mut W { + self.variant(DIPO_A::PAD1) + } + #[doc = "SERCOM PAD\\[2\\]"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(DIPO_A::PAD2) + } + #[doc = "SERCOM PAD\\[3\\]"] + #[inline(always)] + pub fn pad3(self) -> &'a mut W { + self.variant(DIPO_A::PAD3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 20)) | ((value as u32 & 0x03) << 20); + self.w + } +} +#[doc = "Frame Format\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FORM_A { + #[doc = "0: SPI Frame"] + SPI_FRAME = 0, + #[doc = "2: SPI Frame with Addr"] + SPI_FRAME_WITH_ADDR = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FORM_A) -> Self { + variant as _ + } +} +#[doc = "Field `FORM` reader - Frame Format"] +pub struct FORM_R(crate::FieldReader); +impl FORM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FORM_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(FORM_A::SPI_FRAME), + 2 => Some(FORM_A::SPI_FRAME_WITH_ADDR), + _ => None, + } + } + #[doc = "Checks if the value of the field is `SPI_FRAME`"] + #[inline(always)] + pub fn is_spi_frame(&self) -> bool { + **self == FORM_A::SPI_FRAME + } + #[doc = "Checks if the value of the field is `SPI_FRAME_WITH_ADDR`"] + #[inline(always)] + pub fn is_spi_frame_with_addr(&self) -> bool { + **self == FORM_A::SPI_FRAME_WITH_ADDR + } +} +impl core::ops::Deref for FORM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FORM` writer - Frame Format"] +pub struct FORM_W<'a> { + w: &'a mut W, +} +impl<'a> FORM_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FORM_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "SPI Frame"] + #[inline(always)] + pub fn spi_frame(self) -> &'a mut W { + self.variant(FORM_A::SPI_FRAME) + } + #[doc = "SPI Frame with Addr"] + #[inline(always)] + pub fn spi_frame_with_addr(self) -> &'a mut W { + self.variant(FORM_A::SPI_FRAME_WITH_ADDR) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Clock Phase\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CPHA_A { + #[doc = "0: The data is sampled on a leading SCK edge and changed on a trailing SCK edge"] + LEADING_EDGE = 0, + #[doc = "1: The data is sampled on a trailing SCK edge and changed on a leading SCK edge"] + TRAILING_EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CPHA_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CPHA` reader - Clock Phase"] +pub struct CPHA_R(crate::FieldReader); +impl CPHA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPHA_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CPHA_A { + match self.bits { + false => CPHA_A::LEADING_EDGE, + true => CPHA_A::TRAILING_EDGE, + } + } + #[doc = "Checks if the value of the field is `LEADING_EDGE`"] + #[inline(always)] + pub fn is_leading_edge(&self) -> bool { + **self == CPHA_A::LEADING_EDGE + } + #[doc = "Checks if the value of the field is `TRAILING_EDGE`"] + #[inline(always)] + pub fn is_trailing_edge(&self) -> bool { + **self == CPHA_A::TRAILING_EDGE + } +} +impl core::ops::Deref for CPHA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPHA` writer - Clock Phase"] +pub struct CPHA_W<'a> { + w: &'a mut W, +} +impl<'a> CPHA_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CPHA_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "The data is sampled on a leading SCK edge and changed on a trailing SCK edge"] + #[inline(always)] + pub fn leading_edge(self) -> &'a mut W { + self.variant(CPHA_A::LEADING_EDGE) + } + #[doc = "The data is sampled on a trailing SCK edge and changed on a leading SCK edge"] + #[inline(always)] + pub fn trailing_edge(self) -> &'a mut W { + self.variant(CPHA_A::TRAILING_EDGE) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Clock Polarity\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CPOL_A { + #[doc = "0: SCK is low when idle"] + IDLE_LOW = 0, + #[doc = "1: SCK is high when idle"] + IDLE_HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CPOL_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CPOL` reader - Clock Polarity"] +pub struct CPOL_R(crate::FieldReader); +impl CPOL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPOL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CPOL_A { + match self.bits { + false => CPOL_A::IDLE_LOW, + true => CPOL_A::IDLE_HIGH, + } + } + #[doc = "Checks if the value of the field is `IDLE_LOW`"] + #[inline(always)] + pub fn is_idle_low(&self) -> bool { + **self == CPOL_A::IDLE_LOW + } + #[doc = "Checks if the value of the field is `IDLE_HIGH`"] + #[inline(always)] + pub fn is_idle_high(&self) -> bool { + **self == CPOL_A::IDLE_HIGH + } +} +impl core::ops::Deref for CPOL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPOL` writer - Clock Polarity"] +pub struct CPOL_W<'a> { + w: &'a mut W, +} +impl<'a> CPOL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CPOL_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "SCK is low when idle"] + #[inline(always)] + pub fn idle_low(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_LOW) + } + #[doc = "SCK is high when idle"] + #[inline(always)] + pub fn idle_high(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_HIGH) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29); + self.w + } +} +#[doc = "Data Order\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum DORD_A { + #[doc = "0: MSB is transferred first"] + MSB = 0, + #[doc = "1: LSB is transferred first"] + LSB = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DORD_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DORD` reader - Data Order"] +pub struct DORD_R(crate::FieldReader); +impl DORD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DORD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DORD_A { + match self.bits { + false => DORD_A::MSB, + true => DORD_A::LSB, + } + } + #[doc = "Checks if the value of the field is `MSB`"] + #[inline(always)] + pub fn is_msb(&self) -> bool { + **self == DORD_A::MSB + } + #[doc = "Checks if the value of the field is `LSB`"] + #[inline(always)] + pub fn is_lsb(&self) -> bool { + **self == DORD_A::LSB + } +} +impl core::ops::Deref for DORD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DORD` writer - Data Order"] +pub struct DORD_W<'a> { + w: &'a mut W, +} +impl<'a> DORD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DORD_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "MSB is transferred first"] + #[inline(always)] + pub fn msb(self) -> &'a mut W { + self.variant(DORD_A::MSB) + } + #[doc = "LSB is transferred first"] + #[inline(always)] + pub fn lsb(self) -> &'a mut W { + self.variant(DORD_A::LSB) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x07) as u8) + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&self) -> IBON_R { + IBON_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bits 16:17 - Data Out Pinout"] + #[inline(always)] + pub fn dopo(&self) -> DOPO_R { + DOPO_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bits 20:21 - Data In Pinout"] + #[inline(always)] + pub fn dipo(&self) -> DIPO_R { + DIPO_R::new(((self.bits >> 20) & 0x03) as u8) + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&self) -> FORM_R { + FORM_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 28 - Clock Phase"] + #[inline(always)] + pub fn cpha(&self) -> CPHA_R { + CPHA_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&self) -> CPOL_R { + CPOL_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&self) -> DORD_R { + DORD_R::new(((self.bits >> 30) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&mut self) -> IBON_W { + IBON_W { w: self } + } + #[doc = "Bits 16:17 - Data Out Pinout"] + #[inline(always)] + pub fn dopo(&mut self) -> DOPO_W { + DOPO_W { w: self } + } + #[doc = "Bits 20:21 - Data In Pinout"] + #[inline(always)] + pub fn dipo(&mut self) -> DIPO_W { + DIPO_W { w: self } + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&mut self) -> FORM_W { + FORM_W { w: self } + } + #[doc = "Bit 28 - Clock Phase"] + #[inline(always)] + pub fn cpha(&mut self) -> CPHA_W { + CPHA_W { w: self } + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&mut self) -> CPOL_W { + CPOL_W { w: self } + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&mut self) -> DORD_W { + DORD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sercom0/spim/ctrlb.rs b/pac/atsamc21g/src/sercom0/spim/ctrlb.rs new file mode 100644 index 000000000000..3d94f824ce83 --- /dev/null +++ b/pac/atsamc21g/src/sercom0/spim/ctrlb.rs @@ -0,0 +1,439 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Character Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CHSIZE_A { + #[doc = "0: 8 bits"] + _8_BIT = 0, + #[doc = "1: 9 bits"] + _9_BIT = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CHSIZE_A) -> Self { + variant as _ + } +} +#[doc = "Field `CHSIZE` reader - Character Size"] +pub struct CHSIZE_R(crate::FieldReader); +impl CHSIZE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CHSIZE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CHSIZE_A::_8_BIT), + 1 => Some(CHSIZE_A::_9_BIT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_8_BIT`"] + #[inline(always)] + pub fn is_8_bit(&self) -> bool { + **self == CHSIZE_A::_8_BIT + } + #[doc = "Checks if the value of the field is `_9_BIT`"] + #[inline(always)] + pub fn is_9_bit(&self) -> bool { + **self == CHSIZE_A::_9_BIT + } +} +impl core::ops::Deref for CHSIZE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHSIZE` writer - Character Size"] +pub struct CHSIZE_W<'a> { + w: &'a mut W, +} +impl<'a> CHSIZE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CHSIZE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8 bits"] + #[inline(always)] + pub fn _8_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_8_BIT) + } + #[doc = "9 bits"] + #[inline(always)] + pub fn _9_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_9_BIT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Field `PLOADEN` reader - Data Preload Enable"] +pub struct PLOADEN_R(crate::FieldReader); +impl PLOADEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PLOADEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PLOADEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PLOADEN` writer - Data Preload Enable"] +pub struct PLOADEN_W<'a> { + w: &'a mut W, +} +impl<'a> PLOADEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `SSDE` reader - Slave Select Low Detect Enable"] +pub struct SSDE_R(crate::FieldReader); +impl SSDE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SSDE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSDE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSDE` writer - Slave Select Low Detect Enable"] +pub struct SSDE_W<'a> { + w: &'a mut W, +} +impl<'a> SSDE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `MSSEN` reader - Master Slave Select Enable"] +pub struct MSSEN_R(crate::FieldReader); +impl MSSEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MSSEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MSSEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MSSEN` writer - Master Slave Select Enable"] +pub struct MSSEN_W<'a> { + w: &'a mut W, +} +impl<'a> MSSEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Address Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum AMODE_A { + #[doc = "0: SPI Address mask"] + MASK = 0, + #[doc = "1: Two unique Addressess"] + _2_ADDRESSES = 1, + #[doc = "2: Address Range"] + RANGE = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: AMODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `AMODE` reader - Address Mode"] +pub struct AMODE_R(crate::FieldReader); +impl AMODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + AMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(AMODE_A::MASK), + 1 => Some(AMODE_A::_2_ADDRESSES), + 2 => Some(AMODE_A::RANGE), + _ => None, + } + } + #[doc = "Checks if the value of the field is `MASK`"] + #[inline(always)] + pub fn is_mask(&self) -> bool { + **self == AMODE_A::MASK + } + #[doc = "Checks if the value of the field is `_2_ADDRESSES`"] + #[inline(always)] + pub fn is_2_addresses(&self) -> bool { + **self == AMODE_A::_2_ADDRESSES + } + #[doc = "Checks if the value of the field is `RANGE`"] + #[inline(always)] + pub fn is_range(&self) -> bool { + **self == AMODE_A::RANGE + } +} +impl core::ops::Deref for AMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AMODE` writer - Address Mode"] +pub struct AMODE_W<'a> { + w: &'a mut W, +} +impl<'a> AMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: AMODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "SPI Address mask"] + #[inline(always)] + pub fn mask(self) -> &'a mut W { + self.variant(AMODE_A::MASK) + } + #[doc = "Two unique Addressess"] + #[inline(always)] + pub fn _2_addresses(self) -> &'a mut W { + self.variant(AMODE_A::_2_ADDRESSES) + } + #[doc = "Address Range"] + #[inline(always)] + pub fn range(self) -> &'a mut W { + self.variant(AMODE_A::RANGE) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 14)) | ((value as u32 & 0x03) << 14); + self.w + } +} +#[doc = "Field `RXEN` reader - Receiver Enable"] +pub struct RXEN_R(crate::FieldReader); +impl RXEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXEN` writer - Receiver Enable"] +pub struct RXEN_W<'a> { + w: &'a mut W, +} +impl<'a> RXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&self) -> CHSIZE_R { + CHSIZE_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 6 - Data Preload Enable"] + #[inline(always)] + pub fn ploaden(&self) -> PLOADEN_R { + PLOADEN_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 9 - Slave Select Low Detect Enable"] + #[inline(always)] + pub fn ssde(&self) -> SSDE_R { + SSDE_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 13 - Master Slave Select Enable"] + #[inline(always)] + pub fn mssen(&self) -> MSSEN_R { + MSSEN_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bits 14:15 - Address Mode"] + #[inline(always)] + pub fn amode(&self) -> AMODE_R { + AMODE_R::new(((self.bits >> 14) & 0x03) as u8) + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&self) -> RXEN_R { + RXEN_R::new(((self.bits >> 17) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&mut self) -> CHSIZE_W { + CHSIZE_W { w: self } + } + #[doc = "Bit 6 - Data Preload Enable"] + #[inline(always)] + pub fn ploaden(&mut self) -> PLOADEN_W { + PLOADEN_W { w: self } + } + #[doc = "Bit 9 - Slave Select Low Detect Enable"] + #[inline(always)] + pub fn ssde(&mut self) -> SSDE_W { + SSDE_W { w: self } + } + #[doc = "Bit 13 - Master Slave Select Enable"] + #[inline(always)] + pub fn mssen(&mut self) -> MSSEN_W { + MSSEN_W { w: self } + } + #[doc = "Bits 14:15 - Address Mode"] + #[inline(always)] + pub fn amode(&mut self) -> AMODE_W { + AMODE_W { w: self } + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&mut self) -> RXEN_W { + RXEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sercom0/spim/data.rs b/pac/atsamc21g/src/sercom0/spim/data.rs new file mode 100644 index 000000000000..dc9cd020d2a5 --- /dev/null +++ b/pac/atsamc21g/src/sercom0/spim/data.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data Value"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data Value"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01ff) | (value as u32 & 0x01ff); + self.w + } +} +impl R { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new((self.bits & 0x01ff) as u16) + } +} +impl W { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sercom0/spim/dbgctrl.rs b/pac/atsamc21g/src/sercom0/spim/dbgctrl.rs new file mode 100644 index 000000000000..d9aa7495940c --- /dev/null +++ b/pac/atsamc21g/src/sercom0/spim/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGSTOP` reader - Debug Mode"] +pub struct DBGSTOP_R(crate::FieldReader); +impl DBGSTOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGSTOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGSTOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGSTOP` writer - Debug Mode"] +pub struct DBGSTOP_W<'a> { + w: &'a mut W, +} +impl<'a> DBGSTOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&self) -> DBGSTOP_R { + DBGSTOP_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&mut self) -> DBGSTOP_W { + DBGSTOP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sercom0/spim/intenclr.rs b/pac/atsamc21g/src/sercom0/spim/intenclr.rs new file mode 100644 index 000000000000..ccab3de4348d --- /dev/null +++ b/pac/atsamc21g/src/sercom0/spim/intenclr.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Disable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Disable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Disable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Disable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Disable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Disable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SSL` reader - Slave Select Low Interrupt Disable"] +pub struct SSL_R(crate::FieldReader); +impl SSL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SSL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSL` writer - Slave Select Low Interrupt Disable"] +pub struct SSL_W<'a> { + w: &'a mut W, +} +impl<'a> SSL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Disable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Disable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Slave Select Low Interrupt Disable"] + #[inline(always)] + pub fn ssl(&self) -> SSL_R { + SSL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Slave Select Low Interrupt Disable"] + #[inline(always)] + pub fn ssl(&mut self) -> SSL_W { + SSL_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sercom0/spim/intenset.rs b/pac/atsamc21g/src/sercom0/spim/intenset.rs new file mode 100644 index 000000000000..d9779cf897c2 --- /dev/null +++ b/pac/atsamc21g/src/sercom0/spim/intenset.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Enable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Enable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Enable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Enable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Enable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Enable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SSL` reader - Slave Select Low Interrupt Enable"] +pub struct SSL_R(crate::FieldReader); +impl SSL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SSL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSL` writer - Slave Select Low Interrupt Enable"] +pub struct SSL_W<'a> { + w: &'a mut W, +} +impl<'a> SSL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Slave Select Low Interrupt Enable"] + #[inline(always)] + pub fn ssl(&self) -> SSL_R { + SSL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Slave Select Low Interrupt Enable"] + #[inline(always)] + pub fn ssl(&mut self) -> SSL_W { + SSL_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sercom0/spim/intflag.rs b/pac/atsamc21g/src/sercom0/spim/intflag.rs new file mode 100644 index 000000000000..e9bc10c271b8 --- /dev/null +++ b/pac/atsamc21g/src/sercom0/spim/intflag.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SSL` reader - Slave Select Low Interrupt Flag"] +pub struct SSL_R(crate::FieldReader); +impl SSL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SSL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSL` writer - Slave Select Low Interrupt Flag"] +pub struct SSL_W<'a> { + w: &'a mut W, +} +impl<'a> SSL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Slave Select Low Interrupt Flag"] + #[inline(always)] + pub fn ssl(&self) -> SSL_R { + SSL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Slave Select Low Interrupt Flag"] + #[inline(always)] + pub fn ssl(&mut self) -> SSL_W { + SSL_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sercom0/spim/status.rs b/pac/atsamc21g/src/sercom0/spim/status.rs new file mode 100644 index 000000000000..9919460bf0e2 --- /dev/null +++ b/pac/atsamc21g/src/sercom0/spim/status.rs @@ -0,0 +1,113 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BUFOVF` reader - Buffer Overflow"] +pub struct BUFOVF_R(crate::FieldReader); +impl BUFOVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUFOVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUFOVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUFOVF` writer - Buffer Overflow"] +pub struct BUFOVF_W<'a> { + w: &'a mut W, +} +impl<'a> BUFOVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&self) -> BUFOVF_R { + BUFOVF_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&mut self) -> BUFOVF_W { + BUFOVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sercom0/spim/syncbusy.rs b/pac/atsamc21g/src/sercom0/spim/syncbusy.rs new file mode 100644 index 000000000000..bee13adf7084 --- /dev/null +++ b/pac/atsamc21g/src/sercom0/spim/syncbusy.rs @@ -0,0 +1,93 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - SERCOM Enable Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLB` reader - CTRLB Synchronization Busy"] +pub struct CTRLB_R(crate::FieldReader); +impl CTRLB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM Enable Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - CTRLB Synchronization Busy"] + #[inline(always)] + pub fn ctrlb(&self) -> CTRLB_R { + CTRLB_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +#[doc = "SPIM Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sercom0/spis.rs b/pac/atsamc21g/src/sercom0/spis.rs new file mode 100644 index 000000000000..eed10c90c460 --- /dev/null +++ b/pac/atsamc21g/src/sercom0/spis.rs @@ -0,0 +1,44 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "SPIS Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "SPIS Control B"] +pub mod ctrlb; +#[doc = "BAUD register accessor: an alias for `Reg`"] +pub type BAUD = crate::Reg; +#[doc = "SPIS Baud Rate"] +pub mod baud; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "SPIS Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "SPIS Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "SPIS Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "SPIS Status"] +pub mod status; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "SPIS Synchronization Busy"] +pub mod syncbusy; +#[doc = "ADDR register accessor: an alias for `Reg`"] +pub type ADDR = crate::Reg; +#[doc = "SPIS Address"] +pub mod addr; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "SPIS Data"] +pub mod data; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "SPIS Debug Control"] +pub mod dbgctrl; diff --git a/pac/atsamc21g/src/sercom0/spis/addr.rs b/pac/atsamc21g/src/sercom0/spis/addr.rs new file mode 100644 index 000000000000..5fca0a698bfe --- /dev/null +++ b/pac/atsamc21g/src/sercom0/spis/addr.rs @@ -0,0 +1,140 @@ +#[doc = "Register `ADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ADDR` reader - Address Value"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - Address Value"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +#[doc = "Field `ADDRMASK` reader - Address Mask"] +pub struct ADDRMASK_R(crate::FieldReader); +impl ADDRMASK_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ADDRMASK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDRMASK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDRMASK` writer - Address Mask"] +pub struct ADDRMASK_W<'a> { + w: &'a mut W, +} +impl<'a> ADDRMASK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Address Value"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 16:23 - Address Mask"] + #[inline(always)] + pub fn addrmask(&self) -> ADDRMASK_R { + ADDRMASK_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Address Value"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Bits 16:23 - Address Mask"] + #[inline(always)] + pub fn addrmask(&mut self) -> ADDRMASK_W { + ADDRMASK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [addr](index.html) module"] +pub struct ADDR_SPEC; +impl crate::RegisterSpec for ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [addr::R](R) reader structure"] +impl crate::Readable for ADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [addr::W](W) writer structure"] +impl crate::Writable for ADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ADDR to value 0"] +impl crate::Resettable for ADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sercom0/spis/baud.rs b/pac/atsamc21g/src/sercom0/spis/baud.rs new file mode 100644 index 000000000000..eeee4cf633e5 --- /dev/null +++ b/pac/atsamc21g/src/sercom0/spis/baud.rs @@ -0,0 +1,103 @@ +#[doc = "Register `BAUD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud](index.html) module"] +pub struct BAUD_SPEC; +impl crate::RegisterSpec for BAUD_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [baud::R](R) reader structure"] +impl crate::Readable for BAUD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud::W](W) writer structure"] +impl crate::Writable for BAUD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD to value 0"] +impl crate::Resettable for BAUD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sercom0/spis/ctrla.rs b/pac/atsamc21g/src/sercom0/spis/ctrla.rs new file mode 100644 index 000000000000..6151433a8529 --- /dev/null +++ b/pac/atsamc21g/src/sercom0/spis/ctrla.rs @@ -0,0 +1,992 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: USART with external clock"] + USART_EXT_CLK = 0, + #[doc = "1: USART with internal clock"] + USART_INT_CLK = 1, + #[doc = "2: SPI in slave operation"] + SPI_SLAVE = 2, + #[doc = "3: SPI in master operation"] + SPI_MASTER = 3, + #[doc = "4: I2C slave operation"] + I2C_SLAVE = 4, + #[doc = "5: I2C master operation"] + I2C_MASTER = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::USART_EXT_CLK), + 1 => Some(MODE_A::USART_INT_CLK), + 2 => Some(MODE_A::SPI_SLAVE), + 3 => Some(MODE_A::SPI_MASTER), + 4 => Some(MODE_A::I2C_SLAVE), + 5 => Some(MODE_A::I2C_MASTER), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_EXT_CLK`"] + #[inline(always)] + pub fn is_usart_ext_clk(&self) -> bool { + **self == MODE_A::USART_EXT_CLK + } + #[doc = "Checks if the value of the field is `USART_INT_CLK`"] + #[inline(always)] + pub fn is_usart_int_clk(&self) -> bool { + **self == MODE_A::USART_INT_CLK + } + #[doc = "Checks if the value of the field is `SPI_SLAVE`"] + #[inline(always)] + pub fn is_spi_slave(&self) -> bool { + **self == MODE_A::SPI_SLAVE + } + #[doc = "Checks if the value of the field is `SPI_MASTER`"] + #[inline(always)] + pub fn is_spi_master(&self) -> bool { + **self == MODE_A::SPI_MASTER + } + #[doc = "Checks if the value of the field is `I2C_SLAVE`"] + #[inline(always)] + pub fn is_i2c_slave(&self) -> bool { + **self == MODE_A::I2C_SLAVE + } + #[doc = "Checks if the value of the field is `I2C_MASTER`"] + #[inline(always)] + pub fn is_i2c_master(&self) -> bool { + **self == MODE_A::I2C_MASTER + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART with external clock"] + #[inline(always)] + pub fn usart_ext_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_EXT_CLK) + } + #[doc = "USART with internal clock"] + #[inline(always)] + pub fn usart_int_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_INT_CLK) + } + #[doc = "SPI in slave operation"] + #[inline(always)] + pub fn spi_slave(self) -> &'a mut W { + self.variant(MODE_A::SPI_SLAVE) + } + #[doc = "SPI in master operation"] + #[inline(always)] + pub fn spi_master(self) -> &'a mut W { + self.variant(MODE_A::SPI_MASTER) + } + #[doc = "I2C slave operation"] + #[inline(always)] + pub fn i2c_slave(self) -> &'a mut W { + self.variant(MODE_A::I2C_SLAVE) + } + #[doc = "I2C master operation"] + #[inline(always)] + pub fn i2c_master(self) -> &'a mut W { + self.variant(MODE_A::I2C_MASTER) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 2)) | ((value as u32 & 0x07) << 2); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `IBON` reader - Immediate Buffer Overflow Notification"] +pub struct IBON_R(crate::FieldReader); +impl IBON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IBON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IBON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IBON` writer - Immediate Buffer Overflow Notification"] +pub struct IBON_W<'a> { + w: &'a mut W, +} +impl<'a> IBON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Data Out Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DOPO_A { + #[doc = "0: DO on PAD\\[0\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + PAD0 = 0, + #[doc = "1: DO on PAD\\[2\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + PAD1 = 1, + #[doc = "2: DO on PAD\\[3\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + PAD2 = 2, + #[doc = "3: DO on PAD\\[0\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + PAD3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DOPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `DOPO` reader - Data Out Pinout"] +pub struct DOPO_R(crate::FieldReader); +impl DOPO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DOPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DOPO_A { + match self.bits { + 0 => DOPO_A::PAD0, + 1 => DOPO_A::PAD1, + 2 => DOPO_A::PAD2, + 3 => DOPO_A::PAD3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == DOPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD1`"] + #[inline(always)] + pub fn is_pad1(&self) -> bool { + **self == DOPO_A::PAD1 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == DOPO_A::PAD2 + } + #[doc = "Checks if the value of the field is `PAD3`"] + #[inline(always)] + pub fn is_pad3(&self) -> bool { + **self == DOPO_A::PAD3 + } +} +impl core::ops::Deref for DOPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DOPO` writer - Data Out Pinout"] +pub struct DOPO_W<'a> { + w: &'a mut W, +} +impl<'a> DOPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DOPO_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "DO on PAD\\[0\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(DOPO_A::PAD0) + } + #[doc = "DO on PAD\\[2\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + #[inline(always)] + pub fn pad1(self) -> &'a mut W { + self.variant(DOPO_A::PAD1) + } + #[doc = "DO on PAD\\[3\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(DOPO_A::PAD2) + } + #[doc = "DO on PAD\\[0\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + #[inline(always)] + pub fn pad3(self) -> &'a mut W { + self.variant(DOPO_A::PAD3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Data In Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DIPO_A { + #[doc = "0: SERCOM PAD\\[0\\]"] + PAD0 = 0, + #[doc = "1: SERCOM PAD\\[1\\]"] + PAD1 = 1, + #[doc = "2: SERCOM PAD\\[2\\]"] + PAD2 = 2, + #[doc = "3: SERCOM PAD\\[3\\]"] + PAD3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DIPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `DIPO` reader - Data In Pinout"] +pub struct DIPO_R(crate::FieldReader); +impl DIPO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DIPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DIPO_A { + match self.bits { + 0 => DIPO_A::PAD0, + 1 => DIPO_A::PAD1, + 2 => DIPO_A::PAD2, + 3 => DIPO_A::PAD3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == DIPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD1`"] + #[inline(always)] + pub fn is_pad1(&self) -> bool { + **self == DIPO_A::PAD1 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == DIPO_A::PAD2 + } + #[doc = "Checks if the value of the field is `PAD3`"] + #[inline(always)] + pub fn is_pad3(&self) -> bool { + **self == DIPO_A::PAD3 + } +} +impl core::ops::Deref for DIPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIPO` writer - Data In Pinout"] +pub struct DIPO_W<'a> { + w: &'a mut W, +} +impl<'a> DIPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DIPO_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "SERCOM PAD\\[0\\]"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(DIPO_A::PAD0) + } + #[doc = "SERCOM PAD\\[1\\]"] + #[inline(always)] + pub fn pad1(self) -> &'a mut W { + self.variant(DIPO_A::PAD1) + } + #[doc = "SERCOM PAD\\[2\\]"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(DIPO_A::PAD2) + } + #[doc = "SERCOM PAD\\[3\\]"] + #[inline(always)] + pub fn pad3(self) -> &'a mut W { + self.variant(DIPO_A::PAD3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 20)) | ((value as u32 & 0x03) << 20); + self.w + } +} +#[doc = "Frame Format\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FORM_A { + #[doc = "0: SPI Frame"] + SPI_FRAME = 0, + #[doc = "2: SPI Frame with Addr"] + SPI_FRAME_WITH_ADDR = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FORM_A) -> Self { + variant as _ + } +} +#[doc = "Field `FORM` reader - Frame Format"] +pub struct FORM_R(crate::FieldReader); +impl FORM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FORM_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(FORM_A::SPI_FRAME), + 2 => Some(FORM_A::SPI_FRAME_WITH_ADDR), + _ => None, + } + } + #[doc = "Checks if the value of the field is `SPI_FRAME`"] + #[inline(always)] + pub fn is_spi_frame(&self) -> bool { + **self == FORM_A::SPI_FRAME + } + #[doc = "Checks if the value of the field is `SPI_FRAME_WITH_ADDR`"] + #[inline(always)] + pub fn is_spi_frame_with_addr(&self) -> bool { + **self == FORM_A::SPI_FRAME_WITH_ADDR + } +} +impl core::ops::Deref for FORM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FORM` writer - Frame Format"] +pub struct FORM_W<'a> { + w: &'a mut W, +} +impl<'a> FORM_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FORM_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "SPI Frame"] + #[inline(always)] + pub fn spi_frame(self) -> &'a mut W { + self.variant(FORM_A::SPI_FRAME) + } + #[doc = "SPI Frame with Addr"] + #[inline(always)] + pub fn spi_frame_with_addr(self) -> &'a mut W { + self.variant(FORM_A::SPI_FRAME_WITH_ADDR) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Clock Phase\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CPHA_A { + #[doc = "0: The data is sampled on a leading SCK edge and changed on a trailing SCK edge"] + LEADING_EDGE = 0, + #[doc = "1: The data is sampled on a trailing SCK edge and changed on a leading SCK edge"] + TRAILING_EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CPHA_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CPHA` reader - Clock Phase"] +pub struct CPHA_R(crate::FieldReader); +impl CPHA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPHA_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CPHA_A { + match self.bits { + false => CPHA_A::LEADING_EDGE, + true => CPHA_A::TRAILING_EDGE, + } + } + #[doc = "Checks if the value of the field is `LEADING_EDGE`"] + #[inline(always)] + pub fn is_leading_edge(&self) -> bool { + **self == CPHA_A::LEADING_EDGE + } + #[doc = "Checks if the value of the field is `TRAILING_EDGE`"] + #[inline(always)] + pub fn is_trailing_edge(&self) -> bool { + **self == CPHA_A::TRAILING_EDGE + } +} +impl core::ops::Deref for CPHA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPHA` writer - Clock Phase"] +pub struct CPHA_W<'a> { + w: &'a mut W, +} +impl<'a> CPHA_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CPHA_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "The data is sampled on a leading SCK edge and changed on a trailing SCK edge"] + #[inline(always)] + pub fn leading_edge(self) -> &'a mut W { + self.variant(CPHA_A::LEADING_EDGE) + } + #[doc = "The data is sampled on a trailing SCK edge and changed on a leading SCK edge"] + #[inline(always)] + pub fn trailing_edge(self) -> &'a mut W { + self.variant(CPHA_A::TRAILING_EDGE) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Clock Polarity\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CPOL_A { + #[doc = "0: SCK is low when idle"] + IDLE_LOW = 0, + #[doc = "1: SCK is high when idle"] + IDLE_HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CPOL_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CPOL` reader - Clock Polarity"] +pub struct CPOL_R(crate::FieldReader); +impl CPOL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPOL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CPOL_A { + match self.bits { + false => CPOL_A::IDLE_LOW, + true => CPOL_A::IDLE_HIGH, + } + } + #[doc = "Checks if the value of the field is `IDLE_LOW`"] + #[inline(always)] + pub fn is_idle_low(&self) -> bool { + **self == CPOL_A::IDLE_LOW + } + #[doc = "Checks if the value of the field is `IDLE_HIGH`"] + #[inline(always)] + pub fn is_idle_high(&self) -> bool { + **self == CPOL_A::IDLE_HIGH + } +} +impl core::ops::Deref for CPOL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPOL` writer - Clock Polarity"] +pub struct CPOL_W<'a> { + w: &'a mut W, +} +impl<'a> CPOL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CPOL_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "SCK is low when idle"] + #[inline(always)] + pub fn idle_low(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_LOW) + } + #[doc = "SCK is high when idle"] + #[inline(always)] + pub fn idle_high(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_HIGH) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29); + self.w + } +} +#[doc = "Data Order\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum DORD_A { + #[doc = "0: MSB is transferred first"] + MSB = 0, + #[doc = "1: LSB is transferred first"] + LSB = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DORD_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DORD` reader - Data Order"] +pub struct DORD_R(crate::FieldReader); +impl DORD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DORD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DORD_A { + match self.bits { + false => DORD_A::MSB, + true => DORD_A::LSB, + } + } + #[doc = "Checks if the value of the field is `MSB`"] + #[inline(always)] + pub fn is_msb(&self) -> bool { + **self == DORD_A::MSB + } + #[doc = "Checks if the value of the field is `LSB`"] + #[inline(always)] + pub fn is_lsb(&self) -> bool { + **self == DORD_A::LSB + } +} +impl core::ops::Deref for DORD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DORD` writer - Data Order"] +pub struct DORD_W<'a> { + w: &'a mut W, +} +impl<'a> DORD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DORD_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "MSB is transferred first"] + #[inline(always)] + pub fn msb(self) -> &'a mut W { + self.variant(DORD_A::MSB) + } + #[doc = "LSB is transferred first"] + #[inline(always)] + pub fn lsb(self) -> &'a mut W { + self.variant(DORD_A::LSB) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x07) as u8) + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&self) -> IBON_R { + IBON_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bits 16:17 - Data Out Pinout"] + #[inline(always)] + pub fn dopo(&self) -> DOPO_R { + DOPO_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bits 20:21 - Data In Pinout"] + #[inline(always)] + pub fn dipo(&self) -> DIPO_R { + DIPO_R::new(((self.bits >> 20) & 0x03) as u8) + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&self) -> FORM_R { + FORM_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 28 - Clock Phase"] + #[inline(always)] + pub fn cpha(&self) -> CPHA_R { + CPHA_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&self) -> CPOL_R { + CPOL_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&self) -> DORD_R { + DORD_R::new(((self.bits >> 30) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&mut self) -> IBON_W { + IBON_W { w: self } + } + #[doc = "Bits 16:17 - Data Out Pinout"] + #[inline(always)] + pub fn dopo(&mut self) -> DOPO_W { + DOPO_W { w: self } + } + #[doc = "Bits 20:21 - Data In Pinout"] + #[inline(always)] + pub fn dipo(&mut self) -> DIPO_W { + DIPO_W { w: self } + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&mut self) -> FORM_W { + FORM_W { w: self } + } + #[doc = "Bit 28 - Clock Phase"] + #[inline(always)] + pub fn cpha(&mut self) -> CPHA_W { + CPHA_W { w: self } + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&mut self) -> CPOL_W { + CPOL_W { w: self } + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&mut self) -> DORD_W { + DORD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sercom0/spis/ctrlb.rs b/pac/atsamc21g/src/sercom0/spis/ctrlb.rs new file mode 100644 index 000000000000..ccb70582cf34 --- /dev/null +++ b/pac/atsamc21g/src/sercom0/spis/ctrlb.rs @@ -0,0 +1,439 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Character Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CHSIZE_A { + #[doc = "0: 8 bits"] + _8_BIT = 0, + #[doc = "1: 9 bits"] + _9_BIT = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CHSIZE_A) -> Self { + variant as _ + } +} +#[doc = "Field `CHSIZE` reader - Character Size"] +pub struct CHSIZE_R(crate::FieldReader); +impl CHSIZE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CHSIZE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CHSIZE_A::_8_BIT), + 1 => Some(CHSIZE_A::_9_BIT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_8_BIT`"] + #[inline(always)] + pub fn is_8_bit(&self) -> bool { + **self == CHSIZE_A::_8_BIT + } + #[doc = "Checks if the value of the field is `_9_BIT`"] + #[inline(always)] + pub fn is_9_bit(&self) -> bool { + **self == CHSIZE_A::_9_BIT + } +} +impl core::ops::Deref for CHSIZE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHSIZE` writer - Character Size"] +pub struct CHSIZE_W<'a> { + w: &'a mut W, +} +impl<'a> CHSIZE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CHSIZE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8 bits"] + #[inline(always)] + pub fn _8_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_8_BIT) + } + #[doc = "9 bits"] + #[inline(always)] + pub fn _9_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_9_BIT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Field `PLOADEN` reader - Data Preload Enable"] +pub struct PLOADEN_R(crate::FieldReader); +impl PLOADEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PLOADEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PLOADEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PLOADEN` writer - Data Preload Enable"] +pub struct PLOADEN_W<'a> { + w: &'a mut W, +} +impl<'a> PLOADEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `SSDE` reader - Slave Select Low Detect Enable"] +pub struct SSDE_R(crate::FieldReader); +impl SSDE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SSDE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSDE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSDE` writer - Slave Select Low Detect Enable"] +pub struct SSDE_W<'a> { + w: &'a mut W, +} +impl<'a> SSDE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `MSSEN` reader - Master Slave Select Enable"] +pub struct MSSEN_R(crate::FieldReader); +impl MSSEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MSSEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MSSEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MSSEN` writer - Master Slave Select Enable"] +pub struct MSSEN_W<'a> { + w: &'a mut W, +} +impl<'a> MSSEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Address Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum AMODE_A { + #[doc = "0: SPI Address mask"] + MASK = 0, + #[doc = "1: Two unique Addressess"] + _2_ADDRESSES = 1, + #[doc = "2: Address Range"] + RANGE = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: AMODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `AMODE` reader - Address Mode"] +pub struct AMODE_R(crate::FieldReader); +impl AMODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + AMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(AMODE_A::MASK), + 1 => Some(AMODE_A::_2_ADDRESSES), + 2 => Some(AMODE_A::RANGE), + _ => None, + } + } + #[doc = "Checks if the value of the field is `MASK`"] + #[inline(always)] + pub fn is_mask(&self) -> bool { + **self == AMODE_A::MASK + } + #[doc = "Checks if the value of the field is `_2_ADDRESSES`"] + #[inline(always)] + pub fn is_2_addresses(&self) -> bool { + **self == AMODE_A::_2_ADDRESSES + } + #[doc = "Checks if the value of the field is `RANGE`"] + #[inline(always)] + pub fn is_range(&self) -> bool { + **self == AMODE_A::RANGE + } +} +impl core::ops::Deref for AMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AMODE` writer - Address Mode"] +pub struct AMODE_W<'a> { + w: &'a mut W, +} +impl<'a> AMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: AMODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "SPI Address mask"] + #[inline(always)] + pub fn mask(self) -> &'a mut W { + self.variant(AMODE_A::MASK) + } + #[doc = "Two unique Addressess"] + #[inline(always)] + pub fn _2_addresses(self) -> &'a mut W { + self.variant(AMODE_A::_2_ADDRESSES) + } + #[doc = "Address Range"] + #[inline(always)] + pub fn range(self) -> &'a mut W { + self.variant(AMODE_A::RANGE) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 14)) | ((value as u32 & 0x03) << 14); + self.w + } +} +#[doc = "Field `RXEN` reader - Receiver Enable"] +pub struct RXEN_R(crate::FieldReader); +impl RXEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXEN` writer - Receiver Enable"] +pub struct RXEN_W<'a> { + w: &'a mut W, +} +impl<'a> RXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&self) -> CHSIZE_R { + CHSIZE_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 6 - Data Preload Enable"] + #[inline(always)] + pub fn ploaden(&self) -> PLOADEN_R { + PLOADEN_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 9 - Slave Select Low Detect Enable"] + #[inline(always)] + pub fn ssde(&self) -> SSDE_R { + SSDE_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 13 - Master Slave Select Enable"] + #[inline(always)] + pub fn mssen(&self) -> MSSEN_R { + MSSEN_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bits 14:15 - Address Mode"] + #[inline(always)] + pub fn amode(&self) -> AMODE_R { + AMODE_R::new(((self.bits >> 14) & 0x03) as u8) + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&self) -> RXEN_R { + RXEN_R::new(((self.bits >> 17) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&mut self) -> CHSIZE_W { + CHSIZE_W { w: self } + } + #[doc = "Bit 6 - Data Preload Enable"] + #[inline(always)] + pub fn ploaden(&mut self) -> PLOADEN_W { + PLOADEN_W { w: self } + } + #[doc = "Bit 9 - Slave Select Low Detect Enable"] + #[inline(always)] + pub fn ssde(&mut self) -> SSDE_W { + SSDE_W { w: self } + } + #[doc = "Bit 13 - Master Slave Select Enable"] + #[inline(always)] + pub fn mssen(&mut self) -> MSSEN_W { + MSSEN_W { w: self } + } + #[doc = "Bits 14:15 - Address Mode"] + #[inline(always)] + pub fn amode(&mut self) -> AMODE_W { + AMODE_W { w: self } + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&mut self) -> RXEN_W { + RXEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sercom0/spis/data.rs b/pac/atsamc21g/src/sercom0/spis/data.rs new file mode 100644 index 000000000000..4edf8089b29f --- /dev/null +++ b/pac/atsamc21g/src/sercom0/spis/data.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data Value"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data Value"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01ff) | (value as u32 & 0x01ff); + self.w + } +} +impl R { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new((self.bits & 0x01ff) as u16) + } +} +impl W { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sercom0/spis/dbgctrl.rs b/pac/atsamc21g/src/sercom0/spis/dbgctrl.rs new file mode 100644 index 000000000000..ec36bbd26057 --- /dev/null +++ b/pac/atsamc21g/src/sercom0/spis/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGSTOP` reader - Debug Mode"] +pub struct DBGSTOP_R(crate::FieldReader); +impl DBGSTOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGSTOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGSTOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGSTOP` writer - Debug Mode"] +pub struct DBGSTOP_W<'a> { + w: &'a mut W, +} +impl<'a> DBGSTOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&self) -> DBGSTOP_R { + DBGSTOP_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&mut self) -> DBGSTOP_W { + DBGSTOP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sercom0/spis/intenclr.rs b/pac/atsamc21g/src/sercom0/spis/intenclr.rs new file mode 100644 index 000000000000..e4c9ee0d506d --- /dev/null +++ b/pac/atsamc21g/src/sercom0/spis/intenclr.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Disable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Disable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Disable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Disable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Disable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Disable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SSL` reader - Slave Select Low Interrupt Disable"] +pub struct SSL_R(crate::FieldReader); +impl SSL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SSL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSL` writer - Slave Select Low Interrupt Disable"] +pub struct SSL_W<'a> { + w: &'a mut W, +} +impl<'a> SSL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Disable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Disable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Slave Select Low Interrupt Disable"] + #[inline(always)] + pub fn ssl(&self) -> SSL_R { + SSL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Slave Select Low Interrupt Disable"] + #[inline(always)] + pub fn ssl(&mut self) -> SSL_W { + SSL_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sercom0/spis/intenset.rs b/pac/atsamc21g/src/sercom0/spis/intenset.rs new file mode 100644 index 000000000000..99582a624ebc --- /dev/null +++ b/pac/atsamc21g/src/sercom0/spis/intenset.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Enable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Enable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Enable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Enable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Enable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Enable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SSL` reader - Slave Select Low Interrupt Enable"] +pub struct SSL_R(crate::FieldReader); +impl SSL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SSL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSL` writer - Slave Select Low Interrupt Enable"] +pub struct SSL_W<'a> { + w: &'a mut W, +} +impl<'a> SSL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Slave Select Low Interrupt Enable"] + #[inline(always)] + pub fn ssl(&self) -> SSL_R { + SSL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Slave Select Low Interrupt Enable"] + #[inline(always)] + pub fn ssl(&mut self) -> SSL_W { + SSL_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sercom0/spis/intflag.rs b/pac/atsamc21g/src/sercom0/spis/intflag.rs new file mode 100644 index 000000000000..589e73c2329f --- /dev/null +++ b/pac/atsamc21g/src/sercom0/spis/intflag.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SSL` reader - Slave Select Low Interrupt Flag"] +pub struct SSL_R(crate::FieldReader); +impl SSL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SSL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSL` writer - Slave Select Low Interrupt Flag"] +pub struct SSL_W<'a> { + w: &'a mut W, +} +impl<'a> SSL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Slave Select Low Interrupt Flag"] + #[inline(always)] + pub fn ssl(&self) -> SSL_R { + SSL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Slave Select Low Interrupt Flag"] + #[inline(always)] + pub fn ssl(&mut self) -> SSL_W { + SSL_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sercom0/spis/status.rs b/pac/atsamc21g/src/sercom0/spis/status.rs new file mode 100644 index 000000000000..55c39c1a709f --- /dev/null +++ b/pac/atsamc21g/src/sercom0/spis/status.rs @@ -0,0 +1,113 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BUFOVF` reader - Buffer Overflow"] +pub struct BUFOVF_R(crate::FieldReader); +impl BUFOVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUFOVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUFOVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUFOVF` writer - Buffer Overflow"] +pub struct BUFOVF_W<'a> { + w: &'a mut W, +} +impl<'a> BUFOVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&self) -> BUFOVF_R { + BUFOVF_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&mut self) -> BUFOVF_W { + BUFOVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sercom0/spis/syncbusy.rs b/pac/atsamc21g/src/sercom0/spis/syncbusy.rs new file mode 100644 index 000000000000..ac2f2e2c27ec --- /dev/null +++ b/pac/atsamc21g/src/sercom0/spis/syncbusy.rs @@ -0,0 +1,93 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - SERCOM Enable Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLB` reader - CTRLB Synchronization Busy"] +pub struct CTRLB_R(crate::FieldReader); +impl CTRLB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM Enable Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - CTRLB Synchronization Busy"] + #[inline(always)] + pub fn ctrlb(&self) -> CTRLB_R { + CTRLB_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +#[doc = "SPIS Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sercom0/usart_ext.rs b/pac/atsamc21g/src/sercom0/usart_ext.rs new file mode 100644 index 000000000000..8c08b9efc1d5 --- /dev/null +++ b/pac/atsamc21g/src/sercom0/usart_ext.rs @@ -0,0 +1,60 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "USART_EXT Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "USART_EXT Control B"] +pub mod ctrlb; +#[doc = "CTRLC register accessor: an alias for `Reg`"] +pub type CTRLC = crate::Reg; +#[doc = "USART_EXT Control C"] +pub mod ctrlc; +#[doc = "BAUD register accessor: an alias for `Reg`"] +pub type BAUD = crate::Reg; +#[doc = "USART_EXT Baud Rate"] +pub mod baud; +#[doc = "BAUD_FRAC_MODE register accessor: an alias for `Reg`"] +pub type BAUD_FRAC_MODE = crate::Reg; +#[doc = "USART_EXT Baud Rate"] +pub mod baud_frac_mode; +#[doc = "BAUD_FRACFP_MODE register accessor: an alias for `Reg`"] +pub type BAUD_FRACFP_MODE = crate::Reg; +#[doc = "USART_EXT Baud Rate"] +pub mod baud_fracfp_mode; +#[doc = "BAUD_USARTFP_MODE register accessor: an alias for `Reg`"] +pub type BAUD_USARTFP_MODE = crate::Reg; +#[doc = "USART_EXT Baud Rate"] +pub mod baud_usartfp_mode; +#[doc = "RXPL register accessor: an alias for `Reg`"] +pub type RXPL = crate::Reg; +#[doc = "USART_EXT Receive Pulse Length"] +pub mod rxpl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "USART_EXT Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "USART_EXT Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "USART_EXT Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "USART_EXT Status"] +pub mod status; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "USART_EXT Synchronization Busy"] +pub mod syncbusy; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "USART_EXT Data"] +pub mod data; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "USART_EXT Debug Control"] +pub mod dbgctrl; diff --git a/pac/atsamc21g/src/sercom0/usart_ext/baud.rs b/pac/atsamc21g/src/sercom0/usart_ext/baud.rs new file mode 100644 index 000000000000..9558a8e1a52d --- /dev/null +++ b/pac/atsamc21g/src/sercom0/usart_ext/baud.rs @@ -0,0 +1,103 @@ +#[doc = "Register `BAUD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud](index.html) module"] +pub struct BAUD_SPEC; +impl crate::RegisterSpec for BAUD_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud::R](R) reader structure"] +impl crate::Readable for BAUD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud::W](W) writer structure"] +impl crate::Writable for BAUD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD to value 0"] +impl crate::Resettable for BAUD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sercom0/usart_ext/baud_frac_mode.rs b/pac/atsamc21g/src/sercom0/usart_ext/baud_frac_mode.rs new file mode 100644 index 000000000000..d7cdd4570e26 --- /dev/null +++ b/pac/atsamc21g/src/sercom0/usart_ext/baud_frac_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `BAUD_FRAC_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD_FRAC_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1fff) | (value as u16 & 0x1fff); + self.w + } +} +#[doc = "Field `FP` reader - Fractional Part"] +pub struct FP_R(crate::FieldReader); +impl FP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FP` writer - Fractional Part"] +pub struct FP_W<'a> { + w: &'a mut W, +} +impl<'a> FP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 13)) | ((value as u16 & 0x07) << 13); + self.w + } +} +impl R { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new((self.bits & 0x1fff) as u16) + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&self) -> FP_R { + FP_R::new(((self.bits >> 13) & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&mut self) -> FP_W { + FP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud_frac_mode](index.html) module"] +pub struct BAUD_FRAC_MODE_SPEC; +impl crate::RegisterSpec for BAUD_FRAC_MODE_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud_frac_mode::R](R) reader structure"] +impl crate::Readable for BAUD_FRAC_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud_frac_mode::W](W) writer structure"] +impl crate::Writable for BAUD_FRAC_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD_FRAC_MODE to value 0"] +impl crate::Resettable for BAUD_FRAC_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sercom0/usart_ext/baud_fracfp_mode.rs b/pac/atsamc21g/src/sercom0/usart_ext/baud_fracfp_mode.rs new file mode 100644 index 000000000000..c1dc50807677 --- /dev/null +++ b/pac/atsamc21g/src/sercom0/usart_ext/baud_fracfp_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `BAUD_FRACFP_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD_FRACFP_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1fff) | (value as u16 & 0x1fff); + self.w + } +} +#[doc = "Field `FP` reader - Fractional Part"] +pub struct FP_R(crate::FieldReader); +impl FP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FP` writer - Fractional Part"] +pub struct FP_W<'a> { + w: &'a mut W, +} +impl<'a> FP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 13)) | ((value as u16 & 0x07) << 13); + self.w + } +} +impl R { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new((self.bits & 0x1fff) as u16) + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&self) -> FP_R { + FP_R::new(((self.bits >> 13) & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&mut self) -> FP_W { + FP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud_fracfp_mode](index.html) module"] +pub struct BAUD_FRACFP_MODE_SPEC; +impl crate::RegisterSpec for BAUD_FRACFP_MODE_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud_fracfp_mode::R](R) reader structure"] +impl crate::Readable for BAUD_FRACFP_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud_fracfp_mode::W](W) writer structure"] +impl crate::Writable for BAUD_FRACFP_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD_FRACFP_MODE to value 0"] +impl crate::Resettable for BAUD_FRACFP_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sercom0/usart_ext/baud_usartfp_mode.rs b/pac/atsamc21g/src/sercom0/usart_ext/baud_usartfp_mode.rs new file mode 100644 index 000000000000..8d4db16e0245 --- /dev/null +++ b/pac/atsamc21g/src/sercom0/usart_ext/baud_usartfp_mode.rs @@ -0,0 +1,103 @@ +#[doc = "Register `BAUD_USARTFP_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD_USARTFP_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud_usartfp_mode](index.html) module"] +pub struct BAUD_USARTFP_MODE_SPEC; +impl crate::RegisterSpec for BAUD_USARTFP_MODE_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud_usartfp_mode::R](R) reader structure"] +impl crate::Readable for BAUD_USARTFP_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud_usartfp_mode::W](W) writer structure"] +impl crate::Writable for BAUD_USARTFP_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD_USARTFP_MODE to value 0"] +impl crate::Resettable for BAUD_USARTFP_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sercom0/usart_ext/ctrla.rs b/pac/atsamc21g/src/sercom0/usart_ext/ctrla.rs new file mode 100644 index 000000000000..535875ac8b25 --- /dev/null +++ b/pac/atsamc21g/src/sercom0/usart_ext/ctrla.rs @@ -0,0 +1,1171 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: USART with external clock"] + USART_EXT_CLK = 0, + #[doc = "1: USART with internal clock"] + USART_INT_CLK = 1, + #[doc = "2: SPI in slave operation"] + SPI_SLAVE = 2, + #[doc = "3: SPI in master operation"] + SPI_MASTER = 3, + #[doc = "4: I2C slave operation"] + I2C_SLAVE = 4, + #[doc = "5: I2C master operation"] + I2C_MASTER = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::USART_EXT_CLK), + 1 => Some(MODE_A::USART_INT_CLK), + 2 => Some(MODE_A::SPI_SLAVE), + 3 => Some(MODE_A::SPI_MASTER), + 4 => Some(MODE_A::I2C_SLAVE), + 5 => Some(MODE_A::I2C_MASTER), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_EXT_CLK`"] + #[inline(always)] + pub fn is_usart_ext_clk(&self) -> bool { + **self == MODE_A::USART_EXT_CLK + } + #[doc = "Checks if the value of the field is `USART_INT_CLK`"] + #[inline(always)] + pub fn is_usart_int_clk(&self) -> bool { + **self == MODE_A::USART_INT_CLK + } + #[doc = "Checks if the value of the field is `SPI_SLAVE`"] + #[inline(always)] + pub fn is_spi_slave(&self) -> bool { + **self == MODE_A::SPI_SLAVE + } + #[doc = "Checks if the value of the field is `SPI_MASTER`"] + #[inline(always)] + pub fn is_spi_master(&self) -> bool { + **self == MODE_A::SPI_MASTER + } + #[doc = "Checks if the value of the field is `I2C_SLAVE`"] + #[inline(always)] + pub fn is_i2c_slave(&self) -> bool { + **self == MODE_A::I2C_SLAVE + } + #[doc = "Checks if the value of the field is `I2C_MASTER`"] + #[inline(always)] + pub fn is_i2c_master(&self) -> bool { + **self == MODE_A::I2C_MASTER + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART with external clock"] + #[inline(always)] + pub fn usart_ext_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_EXT_CLK) + } + #[doc = "USART with internal clock"] + #[inline(always)] + pub fn usart_int_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_INT_CLK) + } + #[doc = "SPI in slave operation"] + #[inline(always)] + pub fn spi_slave(self) -> &'a mut W { + self.variant(MODE_A::SPI_SLAVE) + } + #[doc = "SPI in master operation"] + #[inline(always)] + pub fn spi_master(self) -> &'a mut W { + self.variant(MODE_A::SPI_MASTER) + } + #[doc = "I2C slave operation"] + #[inline(always)] + pub fn i2c_slave(self) -> &'a mut W { + self.variant(MODE_A::I2C_SLAVE) + } + #[doc = "I2C master operation"] + #[inline(always)] + pub fn i2c_master(self) -> &'a mut W { + self.variant(MODE_A::I2C_MASTER) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 2)) | ((value as u32 & 0x07) << 2); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `IBON` reader - Immediate Buffer Overflow Notification"] +pub struct IBON_R(crate::FieldReader); +impl IBON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IBON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IBON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IBON` writer - Immediate Buffer Overflow Notification"] +pub struct IBON_W<'a> { + w: &'a mut W, +} +impl<'a> IBON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Sample\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SAMPR_A { + #[doc = "0: 16x over-sampling using arithmetic baudrate generation"] + _16X_ARITHMETIC = 0, + #[doc = "1: 16x over-sampling using fractional baudrate generation"] + _16X_FRACTIONAL = 1, + #[doc = "2: 8x over-sampling using arithmetic baudrate generation"] + _8X_ARITHMETIC = 2, + #[doc = "3: 8x over-sampling using fractional baudrate generation"] + _8X_FRACTIONAL = 3, + #[doc = "4: 3x over-sampling using arithmetic baudrate generation"] + _3X_ARITHMETIC = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SAMPR_A) -> Self { + variant as _ + } +} +#[doc = "Field `SAMPR` reader - Sample"] +pub struct SAMPR_R(crate::FieldReader); +impl SAMPR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SAMPR_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SAMPR_A::_16X_ARITHMETIC), + 1 => Some(SAMPR_A::_16X_FRACTIONAL), + 2 => Some(SAMPR_A::_8X_ARITHMETIC), + 3 => Some(SAMPR_A::_8X_FRACTIONAL), + 4 => Some(SAMPR_A::_3X_ARITHMETIC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_16X_ARITHMETIC`"] + #[inline(always)] + pub fn is_16x_arithmetic(&self) -> bool { + **self == SAMPR_A::_16X_ARITHMETIC + } + #[doc = "Checks if the value of the field is `_16X_FRACTIONAL`"] + #[inline(always)] + pub fn is_16x_fractional(&self) -> bool { + **self == SAMPR_A::_16X_FRACTIONAL + } + #[doc = "Checks if the value of the field is `_8X_ARITHMETIC`"] + #[inline(always)] + pub fn is_8x_arithmetic(&self) -> bool { + **self == SAMPR_A::_8X_ARITHMETIC + } + #[doc = "Checks if the value of the field is `_8X_FRACTIONAL`"] + #[inline(always)] + pub fn is_8x_fractional(&self) -> bool { + **self == SAMPR_A::_8X_FRACTIONAL + } + #[doc = "Checks if the value of the field is `_3X_ARITHMETIC`"] + #[inline(always)] + pub fn is_3x_arithmetic(&self) -> bool { + **self == SAMPR_A::_3X_ARITHMETIC + } +} +impl core::ops::Deref for SAMPR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SAMPR` writer - Sample"] +pub struct SAMPR_W<'a> { + w: &'a mut W, +} +impl<'a> SAMPR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SAMPR_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "16x over-sampling using arithmetic baudrate generation"] + #[inline(always)] + pub fn _16x_arithmetic(self) -> &'a mut W { + self.variant(SAMPR_A::_16X_ARITHMETIC) + } + #[doc = "16x over-sampling using fractional baudrate generation"] + #[inline(always)] + pub fn _16x_fractional(self) -> &'a mut W { + self.variant(SAMPR_A::_16X_FRACTIONAL) + } + #[doc = "8x over-sampling using arithmetic baudrate generation"] + #[inline(always)] + pub fn _8x_arithmetic(self) -> &'a mut W { + self.variant(SAMPR_A::_8X_ARITHMETIC) + } + #[doc = "8x over-sampling using fractional baudrate generation"] + #[inline(always)] + pub fn _8x_fractional(self) -> &'a mut W { + self.variant(SAMPR_A::_8X_FRACTIONAL) + } + #[doc = "3x over-sampling using arithmetic baudrate generation"] + #[inline(always)] + pub fn _3x_arithmetic(self) -> &'a mut W { + self.variant(SAMPR_A::_3X_ARITHMETIC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 13)) | ((value as u32 & 0x07) << 13); + self.w + } +} +#[doc = "Transmit Data Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum TXPO_A { + #[doc = "0: SERCOM PAD\\[0\\] +is used for data transmission"] + PAD0 = 0, + #[doc = "1: SERCOM PAD\\[2\\] +is used for data transmission"] + PAD2 = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: TXPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `TXPO` reader - Transmit Data Pinout"] +pub struct TXPO_R(crate::FieldReader); +impl TXPO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TXPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(TXPO_A::PAD0), + 1 => Some(TXPO_A::PAD2), + _ => None, + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == TXPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == TXPO_A::PAD2 + } +} +impl core::ops::Deref for TXPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXPO` writer - Transmit Data Pinout"] +pub struct TXPO_W<'a> { + w: &'a mut W, +} +impl<'a> TXPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TXPO_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "SERCOM PAD\\[0\\] +is used for data transmission"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(TXPO_A::PAD0) + } + #[doc = "SERCOM PAD\\[2\\] +is used for data transmission"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(TXPO_A::PAD2) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Receive Data Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum RXPO_A { + #[doc = "0: SERCOM PAD\\[0\\] +is used for data reception"] + PAD0 = 0, + #[doc = "1: SERCOM PAD\\[1\\] +is used for data reception"] + PAD1 = 1, + #[doc = "2: SERCOM PAD\\[2\\] +is used for data reception"] + PAD2 = 2, + #[doc = "3: SERCOM PAD\\[3\\] +is used for data reception"] + PAD3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RXPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `RXPO` reader - Receive Data Pinout"] +pub struct RXPO_R(crate::FieldReader); +impl RXPO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RXPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RXPO_A { + match self.bits { + 0 => RXPO_A::PAD0, + 1 => RXPO_A::PAD1, + 2 => RXPO_A::PAD2, + 3 => RXPO_A::PAD3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == RXPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD1`"] + #[inline(always)] + pub fn is_pad1(&self) -> bool { + **self == RXPO_A::PAD1 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == RXPO_A::PAD2 + } + #[doc = "Checks if the value of the field is `PAD3`"] + #[inline(always)] + pub fn is_pad3(&self) -> bool { + **self == RXPO_A::PAD3 + } +} +impl core::ops::Deref for RXPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXPO` writer - Receive Data Pinout"] +pub struct RXPO_W<'a> { + w: &'a mut W, +} +impl<'a> RXPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RXPO_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "SERCOM PAD\\[0\\] +is used for data reception"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(RXPO_A::PAD0) + } + #[doc = "SERCOM PAD\\[1\\] +is used for data reception"] + #[inline(always)] + pub fn pad1(self) -> &'a mut W { + self.variant(RXPO_A::PAD1) + } + #[doc = "SERCOM PAD\\[2\\] +is used for data reception"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(RXPO_A::PAD2) + } + #[doc = "SERCOM PAD\\[3\\] +is used for data reception"] + #[inline(always)] + pub fn pad3(self) -> &'a mut W { + self.variant(RXPO_A::PAD3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 20)) | ((value as u32 & 0x03) << 20); + self.w + } +} +#[doc = "Field `SAMPA` reader - Sample Adjustment"] +pub struct SAMPA_R(crate::FieldReader); +impl SAMPA_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SAMPA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SAMPA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SAMPA` writer - Sample Adjustment"] +pub struct SAMPA_W<'a> { + w: &'a mut W, +} +impl<'a> SAMPA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 22)) | ((value as u32 & 0x03) << 22); + self.w + } +} +#[doc = "Frame Format\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FORM_A { + #[doc = "0: USART frame"] + USART_FRAME_NO_PARITY = 0, + #[doc = "1: USART frame with parity"] + USART_FRAME_WITH_PARITY = 1, + #[doc = "2: LIN Master - Break and sync generation"] + USART_FRAME_LIN_MASTER_MODE = 2, + #[doc = "4: Auto-baud - break detection and auto-baud"] + USART_FRAME_AUTO_BAUD_NO_PARITY = 4, + #[doc = "5: Auto-baud - break detection and auto-baud with parity"] + USART_FRAME_AUTO_BAUD_WITH_PARITY = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FORM_A) -> Self { + variant as _ + } +} +#[doc = "Field `FORM` reader - Frame Format"] +pub struct FORM_R(crate::FieldReader); +impl FORM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FORM_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(FORM_A::USART_FRAME_NO_PARITY), + 1 => Some(FORM_A::USART_FRAME_WITH_PARITY), + 2 => Some(FORM_A::USART_FRAME_LIN_MASTER_MODE), + 4 => Some(FORM_A::USART_FRAME_AUTO_BAUD_NO_PARITY), + 5 => Some(FORM_A::USART_FRAME_AUTO_BAUD_WITH_PARITY), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_FRAME_NO_PARITY`"] + #[inline(always)] + pub fn is_usart_frame_no_parity(&self) -> bool { + **self == FORM_A::USART_FRAME_NO_PARITY + } + #[doc = "Checks if the value of the field is `USART_FRAME_WITH_PARITY`"] + #[inline(always)] + pub fn is_usart_frame_with_parity(&self) -> bool { + **self == FORM_A::USART_FRAME_WITH_PARITY + } + #[doc = "Checks if the value of the field is `USART_FRAME_LIN_MASTER_MODE`"] + #[inline(always)] + pub fn is_usart_frame_lin_master_mode(&self) -> bool { + **self == FORM_A::USART_FRAME_LIN_MASTER_MODE + } + #[doc = "Checks if the value of the field is `USART_FRAME_AUTO_BAUD_NO_PARITY`"] + #[inline(always)] + pub fn is_usart_frame_auto_baud_no_parity(&self) -> bool { + **self == FORM_A::USART_FRAME_AUTO_BAUD_NO_PARITY + } + #[doc = "Checks if the value of the field is `USART_FRAME_AUTO_BAUD_WITH_PARITY`"] + #[inline(always)] + pub fn is_usart_frame_auto_baud_with_parity(&self) -> bool { + **self == FORM_A::USART_FRAME_AUTO_BAUD_WITH_PARITY + } +} +impl core::ops::Deref for FORM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FORM` writer - Frame Format"] +pub struct FORM_W<'a> { + w: &'a mut W, +} +impl<'a> FORM_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FORM_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART frame"] + #[inline(always)] + pub fn usart_frame_no_parity(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_NO_PARITY) + } + #[doc = "USART frame with parity"] + #[inline(always)] + pub fn usart_frame_with_parity(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_WITH_PARITY) + } + #[doc = "LIN Master - Break and sync generation"] + #[inline(always)] + pub fn usart_frame_lin_master_mode(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_LIN_MASTER_MODE) + } + #[doc = "Auto-baud - break detection and auto-baud"] + #[inline(always)] + pub fn usart_frame_auto_baud_no_parity(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_AUTO_BAUD_NO_PARITY) + } + #[doc = "Auto-baud - break detection and auto-baud with parity"] + #[inline(always)] + pub fn usart_frame_auto_baud_with_parity(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_AUTO_BAUD_WITH_PARITY) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Communication Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CMODE_A { + #[doc = "0: Asynchronous Communication"] + ASYNC = 0, + #[doc = "1: Synchronous Communication"] + SYNC = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CMODE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CMODE` reader - Communication Mode"] +pub struct CMODE_R(crate::FieldReader); +impl CMODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CMODE_A { + match self.bits { + false => CMODE_A::ASYNC, + true => CMODE_A::SYNC, + } + } + #[doc = "Checks if the value of the field is `ASYNC`"] + #[inline(always)] + pub fn is_async(&self) -> bool { + **self == CMODE_A::ASYNC + } + #[doc = "Checks if the value of the field is `SYNC`"] + #[inline(always)] + pub fn is_sync(&self) -> bool { + **self == CMODE_A::SYNC + } +} +impl core::ops::Deref for CMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMODE` writer - Communication Mode"] +pub struct CMODE_W<'a> { + w: &'a mut W, +} +impl<'a> CMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMODE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Asynchronous Communication"] + #[inline(always)] + pub fn async_(self) -> &'a mut W { + self.variant(CMODE_A::ASYNC) + } + #[doc = "Synchronous Communication"] + #[inline(always)] + pub fn sync(self) -> &'a mut W { + self.variant(CMODE_A::SYNC) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Clock Polarity\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CPOL_A { + #[doc = "0: TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge"] + IDLE_LOW = 0, + #[doc = "1: TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge"] + IDLE_HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CPOL_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CPOL` reader - Clock Polarity"] +pub struct CPOL_R(crate::FieldReader); +impl CPOL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPOL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CPOL_A { + match self.bits { + false => CPOL_A::IDLE_LOW, + true => CPOL_A::IDLE_HIGH, + } + } + #[doc = "Checks if the value of the field is `IDLE_LOW`"] + #[inline(always)] + pub fn is_idle_low(&self) -> bool { + **self == CPOL_A::IDLE_LOW + } + #[doc = "Checks if the value of the field is `IDLE_HIGH`"] + #[inline(always)] + pub fn is_idle_high(&self) -> bool { + **self == CPOL_A::IDLE_HIGH + } +} +impl core::ops::Deref for CPOL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPOL` writer - Clock Polarity"] +pub struct CPOL_W<'a> { + w: &'a mut W, +} +impl<'a> CPOL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CPOL_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge"] + #[inline(always)] + pub fn idle_low(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_LOW) + } + #[doc = "TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge"] + #[inline(always)] + pub fn idle_high(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_HIGH) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29); + self.w + } +} +#[doc = "Data Order\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum DORD_A { + #[doc = "0: MSB is transmitted first"] + MSB = 0, + #[doc = "1: LSB is transmitted first"] + LSB = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DORD_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DORD` reader - Data Order"] +pub struct DORD_R(crate::FieldReader); +impl DORD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DORD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DORD_A { + match self.bits { + false => DORD_A::MSB, + true => DORD_A::LSB, + } + } + #[doc = "Checks if the value of the field is `MSB`"] + #[inline(always)] + pub fn is_msb(&self) -> bool { + **self == DORD_A::MSB + } + #[doc = "Checks if the value of the field is `LSB`"] + #[inline(always)] + pub fn is_lsb(&self) -> bool { + **self == DORD_A::LSB + } +} +impl core::ops::Deref for DORD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DORD` writer - Data Order"] +pub struct DORD_W<'a> { + w: &'a mut W, +} +impl<'a> DORD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DORD_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "MSB is transmitted first"] + #[inline(always)] + pub fn msb(self) -> &'a mut W { + self.variant(DORD_A::MSB) + } + #[doc = "LSB is transmitted first"] + #[inline(always)] + pub fn lsb(self) -> &'a mut W { + self.variant(DORD_A::LSB) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x07) as u8) + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&self) -> IBON_R { + IBON_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bits 13:15 - Sample"] + #[inline(always)] + pub fn sampr(&self) -> SAMPR_R { + SAMPR_R::new(((self.bits >> 13) & 0x07) as u8) + } + #[doc = "Bits 16:17 - Transmit Data Pinout"] + #[inline(always)] + pub fn txpo(&self) -> TXPO_R { + TXPO_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bits 20:21 - Receive Data Pinout"] + #[inline(always)] + pub fn rxpo(&self) -> RXPO_R { + RXPO_R::new(((self.bits >> 20) & 0x03) as u8) + } + #[doc = "Bits 22:23 - Sample Adjustment"] + #[inline(always)] + pub fn sampa(&self) -> SAMPA_R { + SAMPA_R::new(((self.bits >> 22) & 0x03) as u8) + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&self) -> FORM_R { + FORM_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 28 - Communication Mode"] + #[inline(always)] + pub fn cmode(&self) -> CMODE_R { + CMODE_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&self) -> CPOL_R { + CPOL_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&self) -> DORD_R { + DORD_R::new(((self.bits >> 30) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&mut self) -> IBON_W { + IBON_W { w: self } + } + #[doc = "Bits 13:15 - Sample"] + #[inline(always)] + pub fn sampr(&mut self) -> SAMPR_W { + SAMPR_W { w: self } + } + #[doc = "Bits 16:17 - Transmit Data Pinout"] + #[inline(always)] + pub fn txpo(&mut self) -> TXPO_W { + TXPO_W { w: self } + } + #[doc = "Bits 20:21 - Receive Data Pinout"] + #[inline(always)] + pub fn rxpo(&mut self) -> RXPO_W { + RXPO_W { w: self } + } + #[doc = "Bits 22:23 - Sample Adjustment"] + #[inline(always)] + pub fn sampa(&mut self) -> SAMPA_W { + SAMPA_W { w: self } + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&mut self) -> FORM_W { + FORM_W { w: self } + } + #[doc = "Bit 28 - Communication Mode"] + #[inline(always)] + pub fn cmode(&mut self) -> CMODE_W { + CMODE_W { w: self } + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&mut self) -> CPOL_W { + CPOL_W { w: self } + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&mut self) -> DORD_W { + DORD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sercom0/usart_ext/ctrlb.rs b/pac/atsamc21g/src/sercom0/usart_ext/ctrlb.rs new file mode 100644 index 000000000000..37567555e842 --- /dev/null +++ b/pac/atsamc21g/src/sercom0/usart_ext/ctrlb.rs @@ -0,0 +1,651 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Character Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CHSIZE_A { + #[doc = "0: 8 Bits"] + _8_BIT = 0, + #[doc = "1: 9 Bits"] + _9_BIT = 1, + #[doc = "5: 5 Bits"] + _5_BIT = 5, + #[doc = "6: 6 Bits"] + _6_BIT = 6, + #[doc = "7: 7 Bits"] + _7_BIT = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CHSIZE_A) -> Self { + variant as _ + } +} +#[doc = "Field `CHSIZE` reader - Character Size"] +pub struct CHSIZE_R(crate::FieldReader); +impl CHSIZE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CHSIZE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CHSIZE_A::_8_BIT), + 1 => Some(CHSIZE_A::_9_BIT), + 5 => Some(CHSIZE_A::_5_BIT), + 6 => Some(CHSIZE_A::_6_BIT), + 7 => Some(CHSIZE_A::_7_BIT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_8_BIT`"] + #[inline(always)] + pub fn is_8_bit(&self) -> bool { + **self == CHSIZE_A::_8_BIT + } + #[doc = "Checks if the value of the field is `_9_BIT`"] + #[inline(always)] + pub fn is_9_bit(&self) -> bool { + **self == CHSIZE_A::_9_BIT + } + #[doc = "Checks if the value of the field is `_5_BIT`"] + #[inline(always)] + pub fn is_5_bit(&self) -> bool { + **self == CHSIZE_A::_5_BIT + } + #[doc = "Checks if the value of the field is `_6_BIT`"] + #[inline(always)] + pub fn is_6_bit(&self) -> bool { + **self == CHSIZE_A::_6_BIT + } + #[doc = "Checks if the value of the field is `_7_BIT`"] + #[inline(always)] + pub fn is_7_bit(&self) -> bool { + **self == CHSIZE_A::_7_BIT + } +} +impl core::ops::Deref for CHSIZE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHSIZE` writer - Character Size"] +pub struct CHSIZE_W<'a> { + w: &'a mut W, +} +impl<'a> CHSIZE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CHSIZE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8 Bits"] + #[inline(always)] + pub fn _8_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_8_BIT) + } + #[doc = "9 Bits"] + #[inline(always)] + pub fn _9_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_9_BIT) + } + #[doc = "5 Bits"] + #[inline(always)] + pub fn _5_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_5_BIT) + } + #[doc = "6 Bits"] + #[inline(always)] + pub fn _6_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_6_BIT) + } + #[doc = "7 Bits"] + #[inline(always)] + pub fn _7_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_7_BIT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Stop Bit Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SBMODE_A { + #[doc = "0: One Stop Bit"] + _1_BIT = 0, + #[doc = "1: Two Stop Bits"] + _2_BIT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SBMODE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SBMODE` reader - Stop Bit Mode"] +pub struct SBMODE_R(crate::FieldReader); +impl SBMODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SBMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SBMODE_A { + match self.bits { + false => SBMODE_A::_1_BIT, + true => SBMODE_A::_2_BIT, + } + } + #[doc = "Checks if the value of the field is `_1_BIT`"] + #[inline(always)] + pub fn is_1_bit(&self) -> bool { + **self == SBMODE_A::_1_BIT + } + #[doc = "Checks if the value of the field is `_2_BIT`"] + #[inline(always)] + pub fn is_2_bit(&self) -> bool { + **self == SBMODE_A::_2_BIT + } +} +impl core::ops::Deref for SBMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SBMODE` writer - Stop Bit Mode"] +pub struct SBMODE_W<'a> { + w: &'a mut W, +} +impl<'a> SBMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SBMODE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "One Stop Bit"] + #[inline(always)] + pub fn _1_bit(self) -> &'a mut W { + self.variant(SBMODE_A::_1_BIT) + } + #[doc = "Two Stop Bits"] + #[inline(always)] + pub fn _2_bit(self) -> &'a mut W { + self.variant(SBMODE_A::_2_BIT) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `COLDEN` reader - Collision Detection Enable"] +pub struct COLDEN_R(crate::FieldReader); +impl COLDEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COLDEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COLDEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COLDEN` writer - Collision Detection Enable"] +pub struct COLDEN_W<'a> { + w: &'a mut W, +} +impl<'a> COLDEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `SFDE` reader - Start of Frame Detection Enable"] +pub struct SFDE_R(crate::FieldReader); +impl SFDE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SFDE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SFDE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SFDE` writer - Start of Frame Detection Enable"] +pub struct SFDE_W<'a> { + w: &'a mut W, +} +impl<'a> SFDE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `ENC` reader - Encoding Format"] +pub struct ENC_R(crate::FieldReader); +impl ENC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENC` writer - Encoding Format"] +pub struct ENC_W<'a> { + w: &'a mut W, +} +impl<'a> ENC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Parity Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PMODE_A { + #[doc = "0: Even Parity"] + EVEN = 0, + #[doc = "1: Odd Parity"] + ODD = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PMODE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PMODE` reader - Parity Mode"] +pub struct PMODE_R(crate::FieldReader); +impl PMODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PMODE_A { + match self.bits { + false => PMODE_A::EVEN, + true => PMODE_A::ODD, + } + } + #[doc = "Checks if the value of the field is `EVEN`"] + #[inline(always)] + pub fn is_even(&self) -> bool { + **self == PMODE_A::EVEN + } + #[doc = "Checks if the value of the field is `ODD`"] + #[inline(always)] + pub fn is_odd(&self) -> bool { + **self == PMODE_A::ODD + } +} +impl core::ops::Deref for PMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PMODE` writer - Parity Mode"] +pub struct PMODE_W<'a> { + w: &'a mut W, +} +impl<'a> PMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PMODE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Even Parity"] + #[inline(always)] + pub fn even(self) -> &'a mut W { + self.variant(PMODE_A::EVEN) + } + #[doc = "Odd Parity"] + #[inline(always)] + pub fn odd(self) -> &'a mut W { + self.variant(PMODE_A::ODD) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `TXEN` reader - Transmitter Enable"] +pub struct TXEN_R(crate::FieldReader); +impl TXEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXEN` writer - Transmitter Enable"] +pub struct TXEN_W<'a> { + w: &'a mut W, +} +impl<'a> TXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `RXEN` reader - Receiver Enable"] +pub struct RXEN_R(crate::FieldReader); +impl RXEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXEN` writer - Receiver Enable"] +pub struct RXEN_W<'a> { + w: &'a mut W, +} +impl<'a> RXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `LINCMD` reader - LIN Command"] +pub struct LINCMD_R(crate::FieldReader); +impl LINCMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LINCMD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LINCMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LINCMD` writer - LIN Command"] +pub struct LINCMD_W<'a> { + w: &'a mut W, +} +impl<'a> LINCMD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 24)) | ((value as u32 & 0x03) << 24); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&self) -> CHSIZE_R { + CHSIZE_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 6 - Stop Bit Mode"] + #[inline(always)] + pub fn sbmode(&self) -> SBMODE_R { + SBMODE_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 8 - Collision Detection Enable"] + #[inline(always)] + pub fn colden(&self) -> COLDEN_R { + COLDEN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Start of Frame Detection Enable"] + #[inline(always)] + pub fn sfde(&self) -> SFDE_R { + SFDE_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Encoding Format"] + #[inline(always)] + pub fn enc(&self) -> ENC_R { + ENC_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 13 - Parity Mode"] + #[inline(always)] + pub fn pmode(&self) -> PMODE_R { + PMODE_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 16 - Transmitter Enable"] + #[inline(always)] + pub fn txen(&self) -> TXEN_R { + TXEN_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&self) -> RXEN_R { + RXEN_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bits 24:25 - LIN Command"] + #[inline(always)] + pub fn lincmd(&self) -> LINCMD_R { + LINCMD_R::new(((self.bits >> 24) & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&mut self) -> CHSIZE_W { + CHSIZE_W { w: self } + } + #[doc = "Bit 6 - Stop Bit Mode"] + #[inline(always)] + pub fn sbmode(&mut self) -> SBMODE_W { + SBMODE_W { w: self } + } + #[doc = "Bit 8 - Collision Detection Enable"] + #[inline(always)] + pub fn colden(&mut self) -> COLDEN_W { + COLDEN_W { w: self } + } + #[doc = "Bit 9 - Start of Frame Detection Enable"] + #[inline(always)] + pub fn sfde(&mut self) -> SFDE_W { + SFDE_W { w: self } + } + #[doc = "Bit 10 - Encoding Format"] + #[inline(always)] + pub fn enc(&mut self) -> ENC_W { + ENC_W { w: self } + } + #[doc = "Bit 13 - Parity Mode"] + #[inline(always)] + pub fn pmode(&mut self) -> PMODE_W { + PMODE_W { w: self } + } + #[doc = "Bit 16 - Transmitter Enable"] + #[inline(always)] + pub fn txen(&mut self) -> TXEN_W { + TXEN_W { w: self } + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&mut self) -> RXEN_W { + RXEN_W { w: self } + } + #[doc = "Bits 24:25 - LIN Command"] + #[inline(always)] + pub fn lincmd(&mut self) -> LINCMD_W { + LINCMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sercom0/usart_ext/ctrlc.rs b/pac/atsamc21g/src/sercom0/usart_ext/ctrlc.rs new file mode 100644 index 000000000000..5840d5c3bd06 --- /dev/null +++ b/pac/atsamc21g/src/sercom0/usart_ext/ctrlc.rs @@ -0,0 +1,177 @@ +#[doc = "Register `CTRLC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `GTIME` reader - RS485 Guard Time"] +pub struct GTIME_R(crate::FieldReader); +impl GTIME_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + GTIME_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GTIME_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GTIME` writer - RS485 Guard Time"] +pub struct GTIME_W<'a> { + w: &'a mut W, +} +impl<'a> GTIME_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Field `BRKLEN` reader - LIN Master Break Length"] +pub struct BRKLEN_R(crate::FieldReader); +impl BRKLEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BRKLEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BRKLEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BRKLEN` writer - LIN Master Break Length"] +pub struct BRKLEN_W<'a> { + w: &'a mut W, +} +impl<'a> BRKLEN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 8)) | ((value as u32 & 0x03) << 8); + self.w + } +} +#[doc = "Field `HDRDLY` reader - LIN Master Header Delay"] +pub struct HDRDLY_R(crate::FieldReader); +impl HDRDLY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + HDRDLY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HDRDLY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HDRDLY` writer - LIN Master Header Delay"] +pub struct HDRDLY_W<'a> { + w: &'a mut W, +} +impl<'a> HDRDLY_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 10)) | ((value as u32 & 0x03) << 10); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - RS485 Guard Time"] + #[inline(always)] + pub fn gtime(&self) -> GTIME_R { + GTIME_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bits 8:9 - LIN Master Break Length"] + #[inline(always)] + pub fn brklen(&self) -> BRKLEN_R { + BRKLEN_R::new(((self.bits >> 8) & 0x03) as u8) + } + #[doc = "Bits 10:11 - LIN Master Header Delay"] + #[inline(always)] + pub fn hdrdly(&self) -> HDRDLY_R { + HDRDLY_R::new(((self.bits >> 10) & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - RS485 Guard Time"] + #[inline(always)] + pub fn gtime(&mut self) -> GTIME_W { + GTIME_W { w: self } + } + #[doc = "Bits 8:9 - LIN Master Break Length"] + #[inline(always)] + pub fn brklen(&mut self) -> BRKLEN_W { + BRKLEN_W { w: self } + } + #[doc = "Bits 10:11 - LIN Master Header Delay"] + #[inline(always)] + pub fn hdrdly(&mut self) -> HDRDLY_W { + HDRDLY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Control C\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlc](index.html) module"] +pub struct CTRLC_SPEC; +impl crate::RegisterSpec for CTRLC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlc::R](R) reader structure"] +impl crate::Readable for CTRLC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlc::W](W) writer structure"] +impl crate::Writable for CTRLC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLC to value 0"] +impl crate::Resettable for CTRLC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sercom0/usart_ext/data.rs b/pac/atsamc21g/src/sercom0/usart_ext/data.rs new file mode 100644 index 000000000000..a54152c9571a --- /dev/null +++ b/pac/atsamc21g/src/sercom0/usart_ext/data.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data Value"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data Value"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01ff) | (value as u16 & 0x01ff); + self.w + } +} +impl R { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new((self.bits & 0x01ff) as u16) + } +} +impl W { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sercom0/usart_ext/dbgctrl.rs b/pac/atsamc21g/src/sercom0/usart_ext/dbgctrl.rs new file mode 100644 index 000000000000..6c844f3fe40d --- /dev/null +++ b/pac/atsamc21g/src/sercom0/usart_ext/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGSTOP` reader - Debug Mode"] +pub struct DBGSTOP_R(crate::FieldReader); +impl DBGSTOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGSTOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGSTOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGSTOP` writer - Debug Mode"] +pub struct DBGSTOP_W<'a> { + w: &'a mut W, +} +impl<'a> DBGSTOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&self) -> DBGSTOP_R { + DBGSTOP_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&mut self) -> DBGSTOP_W { + DBGSTOP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sercom0/usart_ext/intenclr.rs b/pac/atsamc21g/src/sercom0/usart_ext/intenclr.rs new file mode 100644 index 000000000000..a815553ce666 --- /dev/null +++ b/pac/atsamc21g/src/sercom0/usart_ext/intenclr.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Disable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Disable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Disable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Disable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Disable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Disable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RXS` reader - Receive Start Interrupt Disable"] +pub struct RXS_R(crate::FieldReader); +impl RXS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXS` writer - Receive Start Interrupt Disable"] +pub struct RXS_W<'a> { + w: &'a mut W, +} +impl<'a> RXS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CTSIC` reader - Clear To Send Input Change Interrupt Disable"] +pub struct CTSIC_R(crate::FieldReader); +impl CTSIC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTSIC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTSIC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTSIC` writer - Clear To Send Input Change Interrupt Disable"] +pub struct CTSIC_W<'a> { + w: &'a mut W, +} +impl<'a> CTSIC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RXBRK` reader - Break Received Interrupt Disable"] +pub struct RXBRK_R(crate::FieldReader); +impl RXBRK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXBRK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXBRK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXBRK` writer - Break Received Interrupt Disable"] +pub struct RXBRK_W<'a> { + w: &'a mut W, +} +impl<'a> RXBRK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Disable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Disable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Receive Start Interrupt Disable"] + #[inline(always)] + pub fn rxs(&self) -> RXS_R { + RXS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Disable"] + #[inline(always)] + pub fn ctsic(&self) -> CTSIC_R { + CTSIC_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Break Received Interrupt Disable"] + #[inline(always)] + pub fn rxbrk(&self) -> RXBRK_R { + RXBRK_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Receive Start Interrupt Disable"] + #[inline(always)] + pub fn rxs(&mut self) -> RXS_W { + RXS_W { w: self } + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Disable"] + #[inline(always)] + pub fn ctsic(&mut self) -> CTSIC_W { + CTSIC_W { w: self } + } + #[doc = "Bit 5 - Break Received Interrupt Disable"] + #[inline(always)] + pub fn rxbrk(&mut self) -> RXBRK_W { + RXBRK_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sercom0/usart_ext/intenset.rs b/pac/atsamc21g/src/sercom0/usart_ext/intenset.rs new file mode 100644 index 000000000000..e800681cf423 --- /dev/null +++ b/pac/atsamc21g/src/sercom0/usart_ext/intenset.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Enable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Enable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Enable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Enable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Enable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Enable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RXS` reader - Receive Start Interrupt Enable"] +pub struct RXS_R(crate::FieldReader); +impl RXS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXS` writer - Receive Start Interrupt Enable"] +pub struct RXS_W<'a> { + w: &'a mut W, +} +impl<'a> RXS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CTSIC` reader - Clear To Send Input Change Interrupt Enable"] +pub struct CTSIC_R(crate::FieldReader); +impl CTSIC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTSIC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTSIC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTSIC` writer - Clear To Send Input Change Interrupt Enable"] +pub struct CTSIC_W<'a> { + w: &'a mut W, +} +impl<'a> CTSIC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RXBRK` reader - Break Received Interrupt Enable"] +pub struct RXBRK_R(crate::FieldReader); +impl RXBRK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXBRK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXBRK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXBRK` writer - Break Received Interrupt Enable"] +pub struct RXBRK_W<'a> { + w: &'a mut W, +} +impl<'a> RXBRK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Receive Start Interrupt Enable"] + #[inline(always)] + pub fn rxs(&self) -> RXS_R { + RXS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Enable"] + #[inline(always)] + pub fn ctsic(&self) -> CTSIC_R { + CTSIC_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Break Received Interrupt Enable"] + #[inline(always)] + pub fn rxbrk(&self) -> RXBRK_R { + RXBRK_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Receive Start Interrupt Enable"] + #[inline(always)] + pub fn rxs(&mut self) -> RXS_W { + RXS_W { w: self } + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Enable"] + #[inline(always)] + pub fn ctsic(&mut self) -> CTSIC_W { + CTSIC_W { w: self } + } + #[doc = "Bit 5 - Break Received Interrupt Enable"] + #[inline(always)] + pub fn rxbrk(&mut self) -> RXBRK_W { + RXBRK_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sercom0/usart_ext/intflag.rs b/pac/atsamc21g/src/sercom0/usart_ext/intflag.rs new file mode 100644 index 000000000000..4b0be279a9ae --- /dev/null +++ b/pac/atsamc21g/src/sercom0/usart_ext/intflag.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RXS` reader - Receive Start Interrupt"] +pub struct RXS_R(crate::FieldReader); +impl RXS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXS` writer - Receive Start Interrupt"] +pub struct RXS_W<'a> { + w: &'a mut W, +} +impl<'a> RXS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CTSIC` reader - Clear To Send Input Change Interrupt"] +pub struct CTSIC_R(crate::FieldReader); +impl CTSIC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTSIC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTSIC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTSIC` writer - Clear To Send Input Change Interrupt"] +pub struct CTSIC_W<'a> { + w: &'a mut W, +} +impl<'a> CTSIC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RXBRK` reader - Break Received Interrupt"] +pub struct RXBRK_R(crate::FieldReader); +impl RXBRK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXBRK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXBRK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXBRK` writer - Break Received Interrupt"] +pub struct RXBRK_W<'a> { + w: &'a mut W, +} +impl<'a> RXBRK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Receive Start Interrupt"] + #[inline(always)] + pub fn rxs(&self) -> RXS_R { + RXS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt"] + #[inline(always)] + pub fn ctsic(&self) -> CTSIC_R { + CTSIC_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Break Received Interrupt"] + #[inline(always)] + pub fn rxbrk(&self) -> RXBRK_R { + RXBRK_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Receive Start Interrupt"] + #[inline(always)] + pub fn rxs(&mut self) -> RXS_W { + RXS_W { w: self } + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt"] + #[inline(always)] + pub fn ctsic(&mut self) -> CTSIC_W { + CTSIC_W { w: self } + } + #[doc = "Bit 5 - Break Received Interrupt"] + #[inline(always)] + pub fn rxbrk(&mut self) -> RXBRK_W { + RXBRK_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sercom0/usart_ext/rxpl.rs b/pac/atsamc21g/src/sercom0/usart_ext/rxpl.rs new file mode 100644 index 000000000000..174464dc16b5 --- /dev/null +++ b/pac/atsamc21g/src/sercom0/usart_ext/rxpl.rs @@ -0,0 +1,103 @@ +#[doc = "Register `RXPL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RXPL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RXPL` reader - Receive Pulse Length"] +pub struct RXPL_R(crate::FieldReader); +impl RXPL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RXPL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXPL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXPL` writer - Receive Pulse Length"] +pub struct RXPL_W<'a> { + w: &'a mut W, +} +impl<'a> RXPL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Receive Pulse Length"] + #[inline(always)] + pub fn rxpl(&self) -> RXPL_R { + RXPL_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Receive Pulse Length"] + #[inline(always)] + pub fn rxpl(&mut self) -> RXPL_W { + RXPL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Receive Pulse Length\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxpl](index.html) module"] +pub struct RXPL_SPEC; +impl crate::RegisterSpec for RXPL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [rxpl::R](R) reader structure"] +impl crate::Readable for RXPL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rxpl::W](W) writer structure"] +impl crate::Writable for RXPL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RXPL to value 0"] +impl crate::Resettable for RXPL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sercom0/usart_ext/status.rs b/pac/atsamc21g/src/sercom0/usart_ext/status.rs new file mode 100644 index 000000000000..a0c50c1bc2cf --- /dev/null +++ b/pac/atsamc21g/src/sercom0/usart_ext/status.rs @@ -0,0 +1,395 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PERR` reader - Parity Error"] +pub struct PERR_R(crate::FieldReader); +impl PERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERR` writer - Parity Error"] +pub struct PERR_W<'a> { + w: &'a mut W, +} +impl<'a> PERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `FERR` reader - Frame Error"] +pub struct FERR_R(crate::FieldReader); +impl FERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FERR` writer - Frame Error"] +pub struct FERR_W<'a> { + w: &'a mut W, +} +impl<'a> FERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `BUFOVF` reader - Buffer Overflow"] +pub struct BUFOVF_R(crate::FieldReader); +impl BUFOVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUFOVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUFOVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUFOVF` writer - Buffer Overflow"] +pub struct BUFOVF_W<'a> { + w: &'a mut W, +} +impl<'a> BUFOVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CTS` reader - Clear To Send"] +pub struct CTS_R(crate::FieldReader); +impl CTS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTS` writer - Clear To Send"] +pub struct CTS_W<'a> { + w: &'a mut W, +} +impl<'a> CTS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ISF` reader - Inconsistent Sync Field"] +pub struct ISF_R(crate::FieldReader); +impl ISF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ISF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ISF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ISF` writer - Inconsistent Sync Field"] +pub struct ISF_W<'a> { + w: &'a mut W, +} +impl<'a> ISF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `COLL` reader - Collision Detected"] +pub struct COLL_R(crate::FieldReader); +impl COLL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COLL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COLL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COLL` writer - Collision Detected"] +pub struct COLL_W<'a> { + w: &'a mut W, +} +impl<'a> COLL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `TXE` reader - Transmitter Empty"] +pub struct TXE_R(crate::FieldReader); +impl TXE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXE` writer - Transmitter Empty"] +pub struct TXE_W<'a> { + w: &'a mut W, +} +impl<'a> TXE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - Parity Error"] + #[inline(always)] + pub fn perr(&self) -> PERR_R { + PERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Frame Error"] + #[inline(always)] + pub fn ferr(&self) -> FERR_R { + FERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&self) -> BUFOVF_R { + BUFOVF_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Clear To Send"] + #[inline(always)] + pub fn cts(&self) -> CTS_R { + CTS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Inconsistent Sync Field"] + #[inline(always)] + pub fn isf(&self) -> ISF_R { + ISF_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Collision Detected"] + #[inline(always)] + pub fn coll(&self) -> COLL_R { + COLL_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Transmitter Empty"] + #[inline(always)] + pub fn txe(&self) -> TXE_R { + TXE_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Parity Error"] + #[inline(always)] + pub fn perr(&mut self) -> PERR_W { + PERR_W { w: self } + } + #[doc = "Bit 1 - Frame Error"] + #[inline(always)] + pub fn ferr(&mut self) -> FERR_W { + FERR_W { w: self } + } + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&mut self) -> BUFOVF_W { + BUFOVF_W { w: self } + } + #[doc = "Bit 3 - Clear To Send"] + #[inline(always)] + pub fn cts(&mut self) -> CTS_W { + CTS_W { w: self } + } + #[doc = "Bit 4 - Inconsistent Sync Field"] + #[inline(always)] + pub fn isf(&mut self) -> ISF_W { + ISF_W { w: self } + } + #[doc = "Bit 5 - Collision Detected"] + #[inline(always)] + pub fn coll(&mut self) -> COLL_W { + COLL_W { w: self } + } + #[doc = "Bit 6 - Transmitter Empty"] + #[inline(always)] + pub fn txe(&mut self) -> TXE_W { + TXE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sercom0/usart_ext/syncbusy.rs b/pac/atsamc21g/src/sercom0/usart_ext/syncbusy.rs new file mode 100644 index 000000000000..7c3b817bbb04 --- /dev/null +++ b/pac/atsamc21g/src/sercom0/usart_ext/syncbusy.rs @@ -0,0 +1,93 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - SERCOM Enable Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLB` reader - CTRLB Synchronization Busy"] +pub struct CTRLB_R(crate::FieldReader); +impl CTRLB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM Enable Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - CTRLB Synchronization Busy"] + #[inline(always)] + pub fn ctrlb(&self) -> CTRLB_R { + CTRLB_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +#[doc = "USART_EXT Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sercom0/usart_int.rs b/pac/atsamc21g/src/sercom0/usart_int.rs new file mode 100644 index 000000000000..157c8c4b4fdc --- /dev/null +++ b/pac/atsamc21g/src/sercom0/usart_int.rs @@ -0,0 +1,60 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "USART_INT Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "USART_INT Control B"] +pub mod ctrlb; +#[doc = "CTRLC register accessor: an alias for `Reg`"] +pub type CTRLC = crate::Reg; +#[doc = "USART_INT Control C"] +pub mod ctrlc; +#[doc = "BAUD register accessor: an alias for `Reg`"] +pub type BAUD = crate::Reg; +#[doc = "USART_INT Baud Rate"] +pub mod baud; +#[doc = "BAUD_FRAC_MODE register accessor: an alias for `Reg`"] +pub type BAUD_FRAC_MODE = crate::Reg; +#[doc = "USART_INT Baud Rate"] +pub mod baud_frac_mode; +#[doc = "BAUD_FRACFP_MODE register accessor: an alias for `Reg`"] +pub type BAUD_FRACFP_MODE = crate::Reg; +#[doc = "USART_INT Baud Rate"] +pub mod baud_fracfp_mode; +#[doc = "BAUD_USARTFP_MODE register accessor: an alias for `Reg`"] +pub type BAUD_USARTFP_MODE = crate::Reg; +#[doc = "USART_INT Baud Rate"] +pub mod baud_usartfp_mode; +#[doc = "RXPL register accessor: an alias for `Reg`"] +pub type RXPL = crate::Reg; +#[doc = "USART_INT Receive Pulse Length"] +pub mod rxpl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "USART_INT Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "USART_INT Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "USART_INT Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "USART_INT Status"] +pub mod status; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "USART_INT Synchronization Busy"] +pub mod syncbusy; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "USART_INT Data"] +pub mod data; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "USART_INT Debug Control"] +pub mod dbgctrl; diff --git a/pac/atsamc21g/src/sercom0/usart_int/baud.rs b/pac/atsamc21g/src/sercom0/usart_int/baud.rs new file mode 100644 index 000000000000..a82df20712b3 --- /dev/null +++ b/pac/atsamc21g/src/sercom0/usart_int/baud.rs @@ -0,0 +1,103 @@ +#[doc = "Register `BAUD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud](index.html) module"] +pub struct BAUD_SPEC; +impl crate::RegisterSpec for BAUD_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud::R](R) reader structure"] +impl crate::Readable for BAUD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud::W](W) writer structure"] +impl crate::Writable for BAUD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD to value 0"] +impl crate::Resettable for BAUD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sercom0/usart_int/baud_frac_mode.rs b/pac/atsamc21g/src/sercom0/usart_int/baud_frac_mode.rs new file mode 100644 index 000000000000..b9c7fa4c4b2a --- /dev/null +++ b/pac/atsamc21g/src/sercom0/usart_int/baud_frac_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `BAUD_FRAC_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD_FRAC_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1fff) | (value as u16 & 0x1fff); + self.w + } +} +#[doc = "Field `FP` reader - Fractional Part"] +pub struct FP_R(crate::FieldReader); +impl FP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FP` writer - Fractional Part"] +pub struct FP_W<'a> { + w: &'a mut W, +} +impl<'a> FP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 13)) | ((value as u16 & 0x07) << 13); + self.w + } +} +impl R { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new((self.bits & 0x1fff) as u16) + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&self) -> FP_R { + FP_R::new(((self.bits >> 13) & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&mut self) -> FP_W { + FP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud_frac_mode](index.html) module"] +pub struct BAUD_FRAC_MODE_SPEC; +impl crate::RegisterSpec for BAUD_FRAC_MODE_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud_frac_mode::R](R) reader structure"] +impl crate::Readable for BAUD_FRAC_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud_frac_mode::W](W) writer structure"] +impl crate::Writable for BAUD_FRAC_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD_FRAC_MODE to value 0"] +impl crate::Resettable for BAUD_FRAC_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sercom0/usart_int/baud_fracfp_mode.rs b/pac/atsamc21g/src/sercom0/usart_int/baud_fracfp_mode.rs new file mode 100644 index 000000000000..0671db99cc9d --- /dev/null +++ b/pac/atsamc21g/src/sercom0/usart_int/baud_fracfp_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `BAUD_FRACFP_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD_FRACFP_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1fff) | (value as u16 & 0x1fff); + self.w + } +} +#[doc = "Field `FP` reader - Fractional Part"] +pub struct FP_R(crate::FieldReader); +impl FP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FP` writer - Fractional Part"] +pub struct FP_W<'a> { + w: &'a mut W, +} +impl<'a> FP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 13)) | ((value as u16 & 0x07) << 13); + self.w + } +} +impl R { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new((self.bits & 0x1fff) as u16) + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&self) -> FP_R { + FP_R::new(((self.bits >> 13) & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&mut self) -> FP_W { + FP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud_fracfp_mode](index.html) module"] +pub struct BAUD_FRACFP_MODE_SPEC; +impl crate::RegisterSpec for BAUD_FRACFP_MODE_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud_fracfp_mode::R](R) reader structure"] +impl crate::Readable for BAUD_FRACFP_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud_fracfp_mode::W](W) writer structure"] +impl crate::Writable for BAUD_FRACFP_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD_FRACFP_MODE to value 0"] +impl crate::Resettable for BAUD_FRACFP_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sercom0/usart_int/baud_usartfp_mode.rs b/pac/atsamc21g/src/sercom0/usart_int/baud_usartfp_mode.rs new file mode 100644 index 000000000000..b49a7ef5b84c --- /dev/null +++ b/pac/atsamc21g/src/sercom0/usart_int/baud_usartfp_mode.rs @@ -0,0 +1,103 @@ +#[doc = "Register `BAUD_USARTFP_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD_USARTFP_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud_usartfp_mode](index.html) module"] +pub struct BAUD_USARTFP_MODE_SPEC; +impl crate::RegisterSpec for BAUD_USARTFP_MODE_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud_usartfp_mode::R](R) reader structure"] +impl crate::Readable for BAUD_USARTFP_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud_usartfp_mode::W](W) writer structure"] +impl crate::Writable for BAUD_USARTFP_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD_USARTFP_MODE to value 0"] +impl crate::Resettable for BAUD_USARTFP_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sercom0/usart_int/ctrla.rs b/pac/atsamc21g/src/sercom0/usart_int/ctrla.rs new file mode 100644 index 000000000000..19d10ecf8e8f --- /dev/null +++ b/pac/atsamc21g/src/sercom0/usart_int/ctrla.rs @@ -0,0 +1,1171 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: USART with external clock"] + USART_EXT_CLK = 0, + #[doc = "1: USART with internal clock"] + USART_INT_CLK = 1, + #[doc = "2: SPI in slave operation"] + SPI_SLAVE = 2, + #[doc = "3: SPI in master operation"] + SPI_MASTER = 3, + #[doc = "4: I2C slave operation"] + I2C_SLAVE = 4, + #[doc = "5: I2C master operation"] + I2C_MASTER = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::USART_EXT_CLK), + 1 => Some(MODE_A::USART_INT_CLK), + 2 => Some(MODE_A::SPI_SLAVE), + 3 => Some(MODE_A::SPI_MASTER), + 4 => Some(MODE_A::I2C_SLAVE), + 5 => Some(MODE_A::I2C_MASTER), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_EXT_CLK`"] + #[inline(always)] + pub fn is_usart_ext_clk(&self) -> bool { + **self == MODE_A::USART_EXT_CLK + } + #[doc = "Checks if the value of the field is `USART_INT_CLK`"] + #[inline(always)] + pub fn is_usart_int_clk(&self) -> bool { + **self == MODE_A::USART_INT_CLK + } + #[doc = "Checks if the value of the field is `SPI_SLAVE`"] + #[inline(always)] + pub fn is_spi_slave(&self) -> bool { + **self == MODE_A::SPI_SLAVE + } + #[doc = "Checks if the value of the field is `SPI_MASTER`"] + #[inline(always)] + pub fn is_spi_master(&self) -> bool { + **self == MODE_A::SPI_MASTER + } + #[doc = "Checks if the value of the field is `I2C_SLAVE`"] + #[inline(always)] + pub fn is_i2c_slave(&self) -> bool { + **self == MODE_A::I2C_SLAVE + } + #[doc = "Checks if the value of the field is `I2C_MASTER`"] + #[inline(always)] + pub fn is_i2c_master(&self) -> bool { + **self == MODE_A::I2C_MASTER + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART with external clock"] + #[inline(always)] + pub fn usart_ext_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_EXT_CLK) + } + #[doc = "USART with internal clock"] + #[inline(always)] + pub fn usart_int_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_INT_CLK) + } + #[doc = "SPI in slave operation"] + #[inline(always)] + pub fn spi_slave(self) -> &'a mut W { + self.variant(MODE_A::SPI_SLAVE) + } + #[doc = "SPI in master operation"] + #[inline(always)] + pub fn spi_master(self) -> &'a mut W { + self.variant(MODE_A::SPI_MASTER) + } + #[doc = "I2C slave operation"] + #[inline(always)] + pub fn i2c_slave(self) -> &'a mut W { + self.variant(MODE_A::I2C_SLAVE) + } + #[doc = "I2C master operation"] + #[inline(always)] + pub fn i2c_master(self) -> &'a mut W { + self.variant(MODE_A::I2C_MASTER) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 2)) | ((value as u32 & 0x07) << 2); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `IBON` reader - Immediate Buffer Overflow Notification"] +pub struct IBON_R(crate::FieldReader); +impl IBON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IBON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IBON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IBON` writer - Immediate Buffer Overflow Notification"] +pub struct IBON_W<'a> { + w: &'a mut W, +} +impl<'a> IBON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Sample\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SAMPR_A { + #[doc = "0: 16x over-sampling using arithmetic baudrate generation"] + _16X_ARITHMETIC = 0, + #[doc = "1: 16x over-sampling using fractional baudrate generation"] + _16X_FRACTIONAL = 1, + #[doc = "2: 8x over-sampling using arithmetic baudrate generation"] + _8X_ARITHMETIC = 2, + #[doc = "3: 8x over-sampling using fractional baudrate generation"] + _8X_FRACTIONAL = 3, + #[doc = "4: 3x over-sampling using arithmetic baudrate generation"] + _3X_ARITHMETIC = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SAMPR_A) -> Self { + variant as _ + } +} +#[doc = "Field `SAMPR` reader - Sample"] +pub struct SAMPR_R(crate::FieldReader); +impl SAMPR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SAMPR_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SAMPR_A::_16X_ARITHMETIC), + 1 => Some(SAMPR_A::_16X_FRACTIONAL), + 2 => Some(SAMPR_A::_8X_ARITHMETIC), + 3 => Some(SAMPR_A::_8X_FRACTIONAL), + 4 => Some(SAMPR_A::_3X_ARITHMETIC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_16X_ARITHMETIC`"] + #[inline(always)] + pub fn is_16x_arithmetic(&self) -> bool { + **self == SAMPR_A::_16X_ARITHMETIC + } + #[doc = "Checks if the value of the field is `_16X_FRACTIONAL`"] + #[inline(always)] + pub fn is_16x_fractional(&self) -> bool { + **self == SAMPR_A::_16X_FRACTIONAL + } + #[doc = "Checks if the value of the field is `_8X_ARITHMETIC`"] + #[inline(always)] + pub fn is_8x_arithmetic(&self) -> bool { + **self == SAMPR_A::_8X_ARITHMETIC + } + #[doc = "Checks if the value of the field is `_8X_FRACTIONAL`"] + #[inline(always)] + pub fn is_8x_fractional(&self) -> bool { + **self == SAMPR_A::_8X_FRACTIONAL + } + #[doc = "Checks if the value of the field is `_3X_ARITHMETIC`"] + #[inline(always)] + pub fn is_3x_arithmetic(&self) -> bool { + **self == SAMPR_A::_3X_ARITHMETIC + } +} +impl core::ops::Deref for SAMPR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SAMPR` writer - Sample"] +pub struct SAMPR_W<'a> { + w: &'a mut W, +} +impl<'a> SAMPR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SAMPR_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "16x over-sampling using arithmetic baudrate generation"] + #[inline(always)] + pub fn _16x_arithmetic(self) -> &'a mut W { + self.variant(SAMPR_A::_16X_ARITHMETIC) + } + #[doc = "16x over-sampling using fractional baudrate generation"] + #[inline(always)] + pub fn _16x_fractional(self) -> &'a mut W { + self.variant(SAMPR_A::_16X_FRACTIONAL) + } + #[doc = "8x over-sampling using arithmetic baudrate generation"] + #[inline(always)] + pub fn _8x_arithmetic(self) -> &'a mut W { + self.variant(SAMPR_A::_8X_ARITHMETIC) + } + #[doc = "8x over-sampling using fractional baudrate generation"] + #[inline(always)] + pub fn _8x_fractional(self) -> &'a mut W { + self.variant(SAMPR_A::_8X_FRACTIONAL) + } + #[doc = "3x over-sampling using arithmetic baudrate generation"] + #[inline(always)] + pub fn _3x_arithmetic(self) -> &'a mut W { + self.variant(SAMPR_A::_3X_ARITHMETIC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 13)) | ((value as u32 & 0x07) << 13); + self.w + } +} +#[doc = "Transmit Data Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum TXPO_A { + #[doc = "0: SERCOM PAD\\[0\\] +is used for data transmission"] + PAD0 = 0, + #[doc = "1: SERCOM PAD\\[2\\] +is used for data transmission"] + PAD2 = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: TXPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `TXPO` reader - Transmit Data Pinout"] +pub struct TXPO_R(crate::FieldReader); +impl TXPO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TXPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(TXPO_A::PAD0), + 1 => Some(TXPO_A::PAD2), + _ => None, + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == TXPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == TXPO_A::PAD2 + } +} +impl core::ops::Deref for TXPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXPO` writer - Transmit Data Pinout"] +pub struct TXPO_W<'a> { + w: &'a mut W, +} +impl<'a> TXPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TXPO_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "SERCOM PAD\\[0\\] +is used for data transmission"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(TXPO_A::PAD0) + } + #[doc = "SERCOM PAD\\[2\\] +is used for data transmission"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(TXPO_A::PAD2) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Receive Data Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum RXPO_A { + #[doc = "0: SERCOM PAD\\[0\\] +is used for data reception"] + PAD0 = 0, + #[doc = "1: SERCOM PAD\\[1\\] +is used for data reception"] + PAD1 = 1, + #[doc = "2: SERCOM PAD\\[2\\] +is used for data reception"] + PAD2 = 2, + #[doc = "3: SERCOM PAD\\[3\\] +is used for data reception"] + PAD3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RXPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `RXPO` reader - Receive Data Pinout"] +pub struct RXPO_R(crate::FieldReader); +impl RXPO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RXPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RXPO_A { + match self.bits { + 0 => RXPO_A::PAD0, + 1 => RXPO_A::PAD1, + 2 => RXPO_A::PAD2, + 3 => RXPO_A::PAD3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == RXPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD1`"] + #[inline(always)] + pub fn is_pad1(&self) -> bool { + **self == RXPO_A::PAD1 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == RXPO_A::PAD2 + } + #[doc = "Checks if the value of the field is `PAD3`"] + #[inline(always)] + pub fn is_pad3(&self) -> bool { + **self == RXPO_A::PAD3 + } +} +impl core::ops::Deref for RXPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXPO` writer - Receive Data Pinout"] +pub struct RXPO_W<'a> { + w: &'a mut W, +} +impl<'a> RXPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RXPO_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "SERCOM PAD\\[0\\] +is used for data reception"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(RXPO_A::PAD0) + } + #[doc = "SERCOM PAD\\[1\\] +is used for data reception"] + #[inline(always)] + pub fn pad1(self) -> &'a mut W { + self.variant(RXPO_A::PAD1) + } + #[doc = "SERCOM PAD\\[2\\] +is used for data reception"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(RXPO_A::PAD2) + } + #[doc = "SERCOM PAD\\[3\\] +is used for data reception"] + #[inline(always)] + pub fn pad3(self) -> &'a mut W { + self.variant(RXPO_A::PAD3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 20)) | ((value as u32 & 0x03) << 20); + self.w + } +} +#[doc = "Field `SAMPA` reader - Sample Adjustment"] +pub struct SAMPA_R(crate::FieldReader); +impl SAMPA_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SAMPA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SAMPA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SAMPA` writer - Sample Adjustment"] +pub struct SAMPA_W<'a> { + w: &'a mut W, +} +impl<'a> SAMPA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 22)) | ((value as u32 & 0x03) << 22); + self.w + } +} +#[doc = "Frame Format\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FORM_A { + #[doc = "0: USART frame"] + USART_FRAME_NO_PARITY = 0, + #[doc = "1: USART frame with parity"] + USART_FRAME_WITH_PARITY = 1, + #[doc = "2: LIN Master - Break and sync generation"] + USART_FRAME_LIN_MASTER_MODE = 2, + #[doc = "4: Auto-baud - break detection and auto-baud"] + USART_FRAME_AUTO_BAUD_NO_PARITY = 4, + #[doc = "5: Auto-baud - break detection and auto-baud with parity"] + USART_FRAME_AUTO_BAUD_WITH_PARITY = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FORM_A) -> Self { + variant as _ + } +} +#[doc = "Field `FORM` reader - Frame Format"] +pub struct FORM_R(crate::FieldReader); +impl FORM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FORM_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(FORM_A::USART_FRAME_NO_PARITY), + 1 => Some(FORM_A::USART_FRAME_WITH_PARITY), + 2 => Some(FORM_A::USART_FRAME_LIN_MASTER_MODE), + 4 => Some(FORM_A::USART_FRAME_AUTO_BAUD_NO_PARITY), + 5 => Some(FORM_A::USART_FRAME_AUTO_BAUD_WITH_PARITY), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_FRAME_NO_PARITY`"] + #[inline(always)] + pub fn is_usart_frame_no_parity(&self) -> bool { + **self == FORM_A::USART_FRAME_NO_PARITY + } + #[doc = "Checks if the value of the field is `USART_FRAME_WITH_PARITY`"] + #[inline(always)] + pub fn is_usart_frame_with_parity(&self) -> bool { + **self == FORM_A::USART_FRAME_WITH_PARITY + } + #[doc = "Checks if the value of the field is `USART_FRAME_LIN_MASTER_MODE`"] + #[inline(always)] + pub fn is_usart_frame_lin_master_mode(&self) -> bool { + **self == FORM_A::USART_FRAME_LIN_MASTER_MODE + } + #[doc = "Checks if the value of the field is `USART_FRAME_AUTO_BAUD_NO_PARITY`"] + #[inline(always)] + pub fn is_usart_frame_auto_baud_no_parity(&self) -> bool { + **self == FORM_A::USART_FRAME_AUTO_BAUD_NO_PARITY + } + #[doc = "Checks if the value of the field is `USART_FRAME_AUTO_BAUD_WITH_PARITY`"] + #[inline(always)] + pub fn is_usart_frame_auto_baud_with_parity(&self) -> bool { + **self == FORM_A::USART_FRAME_AUTO_BAUD_WITH_PARITY + } +} +impl core::ops::Deref for FORM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FORM` writer - Frame Format"] +pub struct FORM_W<'a> { + w: &'a mut W, +} +impl<'a> FORM_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FORM_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART frame"] + #[inline(always)] + pub fn usart_frame_no_parity(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_NO_PARITY) + } + #[doc = "USART frame with parity"] + #[inline(always)] + pub fn usart_frame_with_parity(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_WITH_PARITY) + } + #[doc = "LIN Master - Break and sync generation"] + #[inline(always)] + pub fn usart_frame_lin_master_mode(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_LIN_MASTER_MODE) + } + #[doc = "Auto-baud - break detection and auto-baud"] + #[inline(always)] + pub fn usart_frame_auto_baud_no_parity(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_AUTO_BAUD_NO_PARITY) + } + #[doc = "Auto-baud - break detection and auto-baud with parity"] + #[inline(always)] + pub fn usart_frame_auto_baud_with_parity(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_AUTO_BAUD_WITH_PARITY) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Communication Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CMODE_A { + #[doc = "0: Asynchronous Communication"] + ASYNC = 0, + #[doc = "1: Synchronous Communication"] + SYNC = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CMODE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CMODE` reader - Communication Mode"] +pub struct CMODE_R(crate::FieldReader); +impl CMODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CMODE_A { + match self.bits { + false => CMODE_A::ASYNC, + true => CMODE_A::SYNC, + } + } + #[doc = "Checks if the value of the field is `ASYNC`"] + #[inline(always)] + pub fn is_async(&self) -> bool { + **self == CMODE_A::ASYNC + } + #[doc = "Checks if the value of the field is `SYNC`"] + #[inline(always)] + pub fn is_sync(&self) -> bool { + **self == CMODE_A::SYNC + } +} +impl core::ops::Deref for CMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMODE` writer - Communication Mode"] +pub struct CMODE_W<'a> { + w: &'a mut W, +} +impl<'a> CMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMODE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Asynchronous Communication"] + #[inline(always)] + pub fn async_(self) -> &'a mut W { + self.variant(CMODE_A::ASYNC) + } + #[doc = "Synchronous Communication"] + #[inline(always)] + pub fn sync(self) -> &'a mut W { + self.variant(CMODE_A::SYNC) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Clock Polarity\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CPOL_A { + #[doc = "0: TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge"] + IDLE_LOW = 0, + #[doc = "1: TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge"] + IDLE_HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CPOL_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CPOL` reader - Clock Polarity"] +pub struct CPOL_R(crate::FieldReader); +impl CPOL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPOL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CPOL_A { + match self.bits { + false => CPOL_A::IDLE_LOW, + true => CPOL_A::IDLE_HIGH, + } + } + #[doc = "Checks if the value of the field is `IDLE_LOW`"] + #[inline(always)] + pub fn is_idle_low(&self) -> bool { + **self == CPOL_A::IDLE_LOW + } + #[doc = "Checks if the value of the field is `IDLE_HIGH`"] + #[inline(always)] + pub fn is_idle_high(&self) -> bool { + **self == CPOL_A::IDLE_HIGH + } +} +impl core::ops::Deref for CPOL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPOL` writer - Clock Polarity"] +pub struct CPOL_W<'a> { + w: &'a mut W, +} +impl<'a> CPOL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CPOL_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge"] + #[inline(always)] + pub fn idle_low(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_LOW) + } + #[doc = "TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge"] + #[inline(always)] + pub fn idle_high(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_HIGH) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29); + self.w + } +} +#[doc = "Data Order\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum DORD_A { + #[doc = "0: MSB is transmitted first"] + MSB = 0, + #[doc = "1: LSB is transmitted first"] + LSB = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DORD_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DORD` reader - Data Order"] +pub struct DORD_R(crate::FieldReader); +impl DORD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DORD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DORD_A { + match self.bits { + false => DORD_A::MSB, + true => DORD_A::LSB, + } + } + #[doc = "Checks if the value of the field is `MSB`"] + #[inline(always)] + pub fn is_msb(&self) -> bool { + **self == DORD_A::MSB + } + #[doc = "Checks if the value of the field is `LSB`"] + #[inline(always)] + pub fn is_lsb(&self) -> bool { + **self == DORD_A::LSB + } +} +impl core::ops::Deref for DORD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DORD` writer - Data Order"] +pub struct DORD_W<'a> { + w: &'a mut W, +} +impl<'a> DORD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DORD_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "MSB is transmitted first"] + #[inline(always)] + pub fn msb(self) -> &'a mut W { + self.variant(DORD_A::MSB) + } + #[doc = "LSB is transmitted first"] + #[inline(always)] + pub fn lsb(self) -> &'a mut W { + self.variant(DORD_A::LSB) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x07) as u8) + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&self) -> IBON_R { + IBON_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bits 13:15 - Sample"] + #[inline(always)] + pub fn sampr(&self) -> SAMPR_R { + SAMPR_R::new(((self.bits >> 13) & 0x07) as u8) + } + #[doc = "Bits 16:17 - Transmit Data Pinout"] + #[inline(always)] + pub fn txpo(&self) -> TXPO_R { + TXPO_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bits 20:21 - Receive Data Pinout"] + #[inline(always)] + pub fn rxpo(&self) -> RXPO_R { + RXPO_R::new(((self.bits >> 20) & 0x03) as u8) + } + #[doc = "Bits 22:23 - Sample Adjustment"] + #[inline(always)] + pub fn sampa(&self) -> SAMPA_R { + SAMPA_R::new(((self.bits >> 22) & 0x03) as u8) + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&self) -> FORM_R { + FORM_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 28 - Communication Mode"] + #[inline(always)] + pub fn cmode(&self) -> CMODE_R { + CMODE_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&self) -> CPOL_R { + CPOL_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&self) -> DORD_R { + DORD_R::new(((self.bits >> 30) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&mut self) -> IBON_W { + IBON_W { w: self } + } + #[doc = "Bits 13:15 - Sample"] + #[inline(always)] + pub fn sampr(&mut self) -> SAMPR_W { + SAMPR_W { w: self } + } + #[doc = "Bits 16:17 - Transmit Data Pinout"] + #[inline(always)] + pub fn txpo(&mut self) -> TXPO_W { + TXPO_W { w: self } + } + #[doc = "Bits 20:21 - Receive Data Pinout"] + #[inline(always)] + pub fn rxpo(&mut self) -> RXPO_W { + RXPO_W { w: self } + } + #[doc = "Bits 22:23 - Sample Adjustment"] + #[inline(always)] + pub fn sampa(&mut self) -> SAMPA_W { + SAMPA_W { w: self } + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&mut self) -> FORM_W { + FORM_W { w: self } + } + #[doc = "Bit 28 - Communication Mode"] + #[inline(always)] + pub fn cmode(&mut self) -> CMODE_W { + CMODE_W { w: self } + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&mut self) -> CPOL_W { + CPOL_W { w: self } + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&mut self) -> DORD_W { + DORD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sercom0/usart_int/ctrlb.rs b/pac/atsamc21g/src/sercom0/usart_int/ctrlb.rs new file mode 100644 index 000000000000..d556e0c3cfc2 --- /dev/null +++ b/pac/atsamc21g/src/sercom0/usart_int/ctrlb.rs @@ -0,0 +1,651 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Character Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CHSIZE_A { + #[doc = "0: 8 Bits"] + _8_BIT = 0, + #[doc = "1: 9 Bits"] + _9_BIT = 1, + #[doc = "5: 5 Bits"] + _5_BIT = 5, + #[doc = "6: 6 Bits"] + _6_BIT = 6, + #[doc = "7: 7 Bits"] + _7_BIT = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CHSIZE_A) -> Self { + variant as _ + } +} +#[doc = "Field `CHSIZE` reader - Character Size"] +pub struct CHSIZE_R(crate::FieldReader); +impl CHSIZE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CHSIZE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CHSIZE_A::_8_BIT), + 1 => Some(CHSIZE_A::_9_BIT), + 5 => Some(CHSIZE_A::_5_BIT), + 6 => Some(CHSIZE_A::_6_BIT), + 7 => Some(CHSIZE_A::_7_BIT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_8_BIT`"] + #[inline(always)] + pub fn is_8_bit(&self) -> bool { + **self == CHSIZE_A::_8_BIT + } + #[doc = "Checks if the value of the field is `_9_BIT`"] + #[inline(always)] + pub fn is_9_bit(&self) -> bool { + **self == CHSIZE_A::_9_BIT + } + #[doc = "Checks if the value of the field is `_5_BIT`"] + #[inline(always)] + pub fn is_5_bit(&self) -> bool { + **self == CHSIZE_A::_5_BIT + } + #[doc = "Checks if the value of the field is `_6_BIT`"] + #[inline(always)] + pub fn is_6_bit(&self) -> bool { + **self == CHSIZE_A::_6_BIT + } + #[doc = "Checks if the value of the field is `_7_BIT`"] + #[inline(always)] + pub fn is_7_bit(&self) -> bool { + **self == CHSIZE_A::_7_BIT + } +} +impl core::ops::Deref for CHSIZE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHSIZE` writer - Character Size"] +pub struct CHSIZE_W<'a> { + w: &'a mut W, +} +impl<'a> CHSIZE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CHSIZE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8 Bits"] + #[inline(always)] + pub fn _8_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_8_BIT) + } + #[doc = "9 Bits"] + #[inline(always)] + pub fn _9_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_9_BIT) + } + #[doc = "5 Bits"] + #[inline(always)] + pub fn _5_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_5_BIT) + } + #[doc = "6 Bits"] + #[inline(always)] + pub fn _6_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_6_BIT) + } + #[doc = "7 Bits"] + #[inline(always)] + pub fn _7_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_7_BIT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Stop Bit Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SBMODE_A { + #[doc = "0: One Stop Bit"] + _1_BIT = 0, + #[doc = "1: Two Stop Bits"] + _2_BIT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SBMODE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SBMODE` reader - Stop Bit Mode"] +pub struct SBMODE_R(crate::FieldReader); +impl SBMODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SBMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SBMODE_A { + match self.bits { + false => SBMODE_A::_1_BIT, + true => SBMODE_A::_2_BIT, + } + } + #[doc = "Checks if the value of the field is `_1_BIT`"] + #[inline(always)] + pub fn is_1_bit(&self) -> bool { + **self == SBMODE_A::_1_BIT + } + #[doc = "Checks if the value of the field is `_2_BIT`"] + #[inline(always)] + pub fn is_2_bit(&self) -> bool { + **self == SBMODE_A::_2_BIT + } +} +impl core::ops::Deref for SBMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SBMODE` writer - Stop Bit Mode"] +pub struct SBMODE_W<'a> { + w: &'a mut W, +} +impl<'a> SBMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SBMODE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "One Stop Bit"] + #[inline(always)] + pub fn _1_bit(self) -> &'a mut W { + self.variant(SBMODE_A::_1_BIT) + } + #[doc = "Two Stop Bits"] + #[inline(always)] + pub fn _2_bit(self) -> &'a mut W { + self.variant(SBMODE_A::_2_BIT) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `COLDEN` reader - Collision Detection Enable"] +pub struct COLDEN_R(crate::FieldReader); +impl COLDEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COLDEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COLDEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COLDEN` writer - Collision Detection Enable"] +pub struct COLDEN_W<'a> { + w: &'a mut W, +} +impl<'a> COLDEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `SFDE` reader - Start of Frame Detection Enable"] +pub struct SFDE_R(crate::FieldReader); +impl SFDE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SFDE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SFDE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SFDE` writer - Start of Frame Detection Enable"] +pub struct SFDE_W<'a> { + w: &'a mut W, +} +impl<'a> SFDE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `ENC` reader - Encoding Format"] +pub struct ENC_R(crate::FieldReader); +impl ENC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENC` writer - Encoding Format"] +pub struct ENC_W<'a> { + w: &'a mut W, +} +impl<'a> ENC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Parity Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PMODE_A { + #[doc = "0: Even Parity"] + EVEN = 0, + #[doc = "1: Odd Parity"] + ODD = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PMODE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PMODE` reader - Parity Mode"] +pub struct PMODE_R(crate::FieldReader); +impl PMODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PMODE_A { + match self.bits { + false => PMODE_A::EVEN, + true => PMODE_A::ODD, + } + } + #[doc = "Checks if the value of the field is `EVEN`"] + #[inline(always)] + pub fn is_even(&self) -> bool { + **self == PMODE_A::EVEN + } + #[doc = "Checks if the value of the field is `ODD`"] + #[inline(always)] + pub fn is_odd(&self) -> bool { + **self == PMODE_A::ODD + } +} +impl core::ops::Deref for PMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PMODE` writer - Parity Mode"] +pub struct PMODE_W<'a> { + w: &'a mut W, +} +impl<'a> PMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PMODE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Even Parity"] + #[inline(always)] + pub fn even(self) -> &'a mut W { + self.variant(PMODE_A::EVEN) + } + #[doc = "Odd Parity"] + #[inline(always)] + pub fn odd(self) -> &'a mut W { + self.variant(PMODE_A::ODD) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `TXEN` reader - Transmitter Enable"] +pub struct TXEN_R(crate::FieldReader); +impl TXEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXEN` writer - Transmitter Enable"] +pub struct TXEN_W<'a> { + w: &'a mut W, +} +impl<'a> TXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `RXEN` reader - Receiver Enable"] +pub struct RXEN_R(crate::FieldReader); +impl RXEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXEN` writer - Receiver Enable"] +pub struct RXEN_W<'a> { + w: &'a mut W, +} +impl<'a> RXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `LINCMD` reader - LIN Command"] +pub struct LINCMD_R(crate::FieldReader); +impl LINCMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LINCMD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LINCMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LINCMD` writer - LIN Command"] +pub struct LINCMD_W<'a> { + w: &'a mut W, +} +impl<'a> LINCMD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 24)) | ((value as u32 & 0x03) << 24); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&self) -> CHSIZE_R { + CHSIZE_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 6 - Stop Bit Mode"] + #[inline(always)] + pub fn sbmode(&self) -> SBMODE_R { + SBMODE_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 8 - Collision Detection Enable"] + #[inline(always)] + pub fn colden(&self) -> COLDEN_R { + COLDEN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Start of Frame Detection Enable"] + #[inline(always)] + pub fn sfde(&self) -> SFDE_R { + SFDE_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Encoding Format"] + #[inline(always)] + pub fn enc(&self) -> ENC_R { + ENC_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 13 - Parity Mode"] + #[inline(always)] + pub fn pmode(&self) -> PMODE_R { + PMODE_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 16 - Transmitter Enable"] + #[inline(always)] + pub fn txen(&self) -> TXEN_R { + TXEN_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&self) -> RXEN_R { + RXEN_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bits 24:25 - LIN Command"] + #[inline(always)] + pub fn lincmd(&self) -> LINCMD_R { + LINCMD_R::new(((self.bits >> 24) & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&mut self) -> CHSIZE_W { + CHSIZE_W { w: self } + } + #[doc = "Bit 6 - Stop Bit Mode"] + #[inline(always)] + pub fn sbmode(&mut self) -> SBMODE_W { + SBMODE_W { w: self } + } + #[doc = "Bit 8 - Collision Detection Enable"] + #[inline(always)] + pub fn colden(&mut self) -> COLDEN_W { + COLDEN_W { w: self } + } + #[doc = "Bit 9 - Start of Frame Detection Enable"] + #[inline(always)] + pub fn sfde(&mut self) -> SFDE_W { + SFDE_W { w: self } + } + #[doc = "Bit 10 - Encoding Format"] + #[inline(always)] + pub fn enc(&mut self) -> ENC_W { + ENC_W { w: self } + } + #[doc = "Bit 13 - Parity Mode"] + #[inline(always)] + pub fn pmode(&mut self) -> PMODE_W { + PMODE_W { w: self } + } + #[doc = "Bit 16 - Transmitter Enable"] + #[inline(always)] + pub fn txen(&mut self) -> TXEN_W { + TXEN_W { w: self } + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&mut self) -> RXEN_W { + RXEN_W { w: self } + } + #[doc = "Bits 24:25 - LIN Command"] + #[inline(always)] + pub fn lincmd(&mut self) -> LINCMD_W { + LINCMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sercom0/usart_int/ctrlc.rs b/pac/atsamc21g/src/sercom0/usart_int/ctrlc.rs new file mode 100644 index 000000000000..e2182cc7f768 --- /dev/null +++ b/pac/atsamc21g/src/sercom0/usart_int/ctrlc.rs @@ -0,0 +1,177 @@ +#[doc = "Register `CTRLC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `GTIME` reader - RS485 Guard Time"] +pub struct GTIME_R(crate::FieldReader); +impl GTIME_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + GTIME_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GTIME_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GTIME` writer - RS485 Guard Time"] +pub struct GTIME_W<'a> { + w: &'a mut W, +} +impl<'a> GTIME_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Field `BRKLEN` reader - LIN Master Break Length"] +pub struct BRKLEN_R(crate::FieldReader); +impl BRKLEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BRKLEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BRKLEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BRKLEN` writer - LIN Master Break Length"] +pub struct BRKLEN_W<'a> { + w: &'a mut W, +} +impl<'a> BRKLEN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 8)) | ((value as u32 & 0x03) << 8); + self.w + } +} +#[doc = "Field `HDRDLY` reader - LIN Master Header Delay"] +pub struct HDRDLY_R(crate::FieldReader); +impl HDRDLY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + HDRDLY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HDRDLY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HDRDLY` writer - LIN Master Header Delay"] +pub struct HDRDLY_W<'a> { + w: &'a mut W, +} +impl<'a> HDRDLY_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 10)) | ((value as u32 & 0x03) << 10); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - RS485 Guard Time"] + #[inline(always)] + pub fn gtime(&self) -> GTIME_R { + GTIME_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bits 8:9 - LIN Master Break Length"] + #[inline(always)] + pub fn brklen(&self) -> BRKLEN_R { + BRKLEN_R::new(((self.bits >> 8) & 0x03) as u8) + } + #[doc = "Bits 10:11 - LIN Master Header Delay"] + #[inline(always)] + pub fn hdrdly(&self) -> HDRDLY_R { + HDRDLY_R::new(((self.bits >> 10) & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - RS485 Guard Time"] + #[inline(always)] + pub fn gtime(&mut self) -> GTIME_W { + GTIME_W { w: self } + } + #[doc = "Bits 8:9 - LIN Master Break Length"] + #[inline(always)] + pub fn brklen(&mut self) -> BRKLEN_W { + BRKLEN_W { w: self } + } + #[doc = "Bits 10:11 - LIN Master Header Delay"] + #[inline(always)] + pub fn hdrdly(&mut self) -> HDRDLY_W { + HDRDLY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Control C\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlc](index.html) module"] +pub struct CTRLC_SPEC; +impl crate::RegisterSpec for CTRLC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlc::R](R) reader structure"] +impl crate::Readable for CTRLC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlc::W](W) writer structure"] +impl crate::Writable for CTRLC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLC to value 0"] +impl crate::Resettable for CTRLC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sercom0/usart_int/data.rs b/pac/atsamc21g/src/sercom0/usart_int/data.rs new file mode 100644 index 000000000000..19d74c337d44 --- /dev/null +++ b/pac/atsamc21g/src/sercom0/usart_int/data.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data Value"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data Value"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01ff) | (value as u16 & 0x01ff); + self.w + } +} +impl R { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new((self.bits & 0x01ff) as u16) + } +} +impl W { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sercom0/usart_int/dbgctrl.rs b/pac/atsamc21g/src/sercom0/usart_int/dbgctrl.rs new file mode 100644 index 000000000000..0ac5b9c7b902 --- /dev/null +++ b/pac/atsamc21g/src/sercom0/usart_int/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGSTOP` reader - Debug Mode"] +pub struct DBGSTOP_R(crate::FieldReader); +impl DBGSTOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGSTOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGSTOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGSTOP` writer - Debug Mode"] +pub struct DBGSTOP_W<'a> { + w: &'a mut W, +} +impl<'a> DBGSTOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&self) -> DBGSTOP_R { + DBGSTOP_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&mut self) -> DBGSTOP_W { + DBGSTOP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sercom0/usart_int/intenclr.rs b/pac/atsamc21g/src/sercom0/usart_int/intenclr.rs new file mode 100644 index 000000000000..5ad23ad15636 --- /dev/null +++ b/pac/atsamc21g/src/sercom0/usart_int/intenclr.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Disable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Disable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Disable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Disable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Disable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Disable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RXS` reader - Receive Start Interrupt Disable"] +pub struct RXS_R(crate::FieldReader); +impl RXS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXS` writer - Receive Start Interrupt Disable"] +pub struct RXS_W<'a> { + w: &'a mut W, +} +impl<'a> RXS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CTSIC` reader - Clear To Send Input Change Interrupt Disable"] +pub struct CTSIC_R(crate::FieldReader); +impl CTSIC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTSIC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTSIC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTSIC` writer - Clear To Send Input Change Interrupt Disable"] +pub struct CTSIC_W<'a> { + w: &'a mut W, +} +impl<'a> CTSIC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RXBRK` reader - Break Received Interrupt Disable"] +pub struct RXBRK_R(crate::FieldReader); +impl RXBRK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXBRK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXBRK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXBRK` writer - Break Received Interrupt Disable"] +pub struct RXBRK_W<'a> { + w: &'a mut W, +} +impl<'a> RXBRK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Disable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Disable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Receive Start Interrupt Disable"] + #[inline(always)] + pub fn rxs(&self) -> RXS_R { + RXS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Disable"] + #[inline(always)] + pub fn ctsic(&self) -> CTSIC_R { + CTSIC_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Break Received Interrupt Disable"] + #[inline(always)] + pub fn rxbrk(&self) -> RXBRK_R { + RXBRK_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Receive Start Interrupt Disable"] + #[inline(always)] + pub fn rxs(&mut self) -> RXS_W { + RXS_W { w: self } + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Disable"] + #[inline(always)] + pub fn ctsic(&mut self) -> CTSIC_W { + CTSIC_W { w: self } + } + #[doc = "Bit 5 - Break Received Interrupt Disable"] + #[inline(always)] + pub fn rxbrk(&mut self) -> RXBRK_W { + RXBRK_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sercom0/usart_int/intenset.rs b/pac/atsamc21g/src/sercom0/usart_int/intenset.rs new file mode 100644 index 000000000000..457f440e13e9 --- /dev/null +++ b/pac/atsamc21g/src/sercom0/usart_int/intenset.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Enable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Enable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Enable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Enable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Enable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Enable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RXS` reader - Receive Start Interrupt Enable"] +pub struct RXS_R(crate::FieldReader); +impl RXS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXS` writer - Receive Start Interrupt Enable"] +pub struct RXS_W<'a> { + w: &'a mut W, +} +impl<'a> RXS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CTSIC` reader - Clear To Send Input Change Interrupt Enable"] +pub struct CTSIC_R(crate::FieldReader); +impl CTSIC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTSIC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTSIC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTSIC` writer - Clear To Send Input Change Interrupt Enable"] +pub struct CTSIC_W<'a> { + w: &'a mut W, +} +impl<'a> CTSIC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RXBRK` reader - Break Received Interrupt Enable"] +pub struct RXBRK_R(crate::FieldReader); +impl RXBRK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXBRK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXBRK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXBRK` writer - Break Received Interrupt Enable"] +pub struct RXBRK_W<'a> { + w: &'a mut W, +} +impl<'a> RXBRK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Receive Start Interrupt Enable"] + #[inline(always)] + pub fn rxs(&self) -> RXS_R { + RXS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Enable"] + #[inline(always)] + pub fn ctsic(&self) -> CTSIC_R { + CTSIC_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Break Received Interrupt Enable"] + #[inline(always)] + pub fn rxbrk(&self) -> RXBRK_R { + RXBRK_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Receive Start Interrupt Enable"] + #[inline(always)] + pub fn rxs(&mut self) -> RXS_W { + RXS_W { w: self } + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Enable"] + #[inline(always)] + pub fn ctsic(&mut self) -> CTSIC_W { + CTSIC_W { w: self } + } + #[doc = "Bit 5 - Break Received Interrupt Enable"] + #[inline(always)] + pub fn rxbrk(&mut self) -> RXBRK_W { + RXBRK_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sercom0/usart_int/intflag.rs b/pac/atsamc21g/src/sercom0/usart_int/intflag.rs new file mode 100644 index 000000000000..a6a26321b8c4 --- /dev/null +++ b/pac/atsamc21g/src/sercom0/usart_int/intflag.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RXS` reader - Receive Start Interrupt"] +pub struct RXS_R(crate::FieldReader); +impl RXS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXS` writer - Receive Start Interrupt"] +pub struct RXS_W<'a> { + w: &'a mut W, +} +impl<'a> RXS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CTSIC` reader - Clear To Send Input Change Interrupt"] +pub struct CTSIC_R(crate::FieldReader); +impl CTSIC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTSIC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTSIC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTSIC` writer - Clear To Send Input Change Interrupt"] +pub struct CTSIC_W<'a> { + w: &'a mut W, +} +impl<'a> CTSIC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RXBRK` reader - Break Received Interrupt"] +pub struct RXBRK_R(crate::FieldReader); +impl RXBRK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXBRK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXBRK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXBRK` writer - Break Received Interrupt"] +pub struct RXBRK_W<'a> { + w: &'a mut W, +} +impl<'a> RXBRK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Receive Start Interrupt"] + #[inline(always)] + pub fn rxs(&self) -> RXS_R { + RXS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt"] + #[inline(always)] + pub fn ctsic(&self) -> CTSIC_R { + CTSIC_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Break Received Interrupt"] + #[inline(always)] + pub fn rxbrk(&self) -> RXBRK_R { + RXBRK_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Receive Start Interrupt"] + #[inline(always)] + pub fn rxs(&mut self) -> RXS_W { + RXS_W { w: self } + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt"] + #[inline(always)] + pub fn ctsic(&mut self) -> CTSIC_W { + CTSIC_W { w: self } + } + #[doc = "Bit 5 - Break Received Interrupt"] + #[inline(always)] + pub fn rxbrk(&mut self) -> RXBRK_W { + RXBRK_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sercom0/usart_int/rxpl.rs b/pac/atsamc21g/src/sercom0/usart_int/rxpl.rs new file mode 100644 index 000000000000..324cbac371c1 --- /dev/null +++ b/pac/atsamc21g/src/sercom0/usart_int/rxpl.rs @@ -0,0 +1,103 @@ +#[doc = "Register `RXPL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RXPL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RXPL` reader - Receive Pulse Length"] +pub struct RXPL_R(crate::FieldReader); +impl RXPL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RXPL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXPL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXPL` writer - Receive Pulse Length"] +pub struct RXPL_W<'a> { + w: &'a mut W, +} +impl<'a> RXPL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Receive Pulse Length"] + #[inline(always)] + pub fn rxpl(&self) -> RXPL_R { + RXPL_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Receive Pulse Length"] + #[inline(always)] + pub fn rxpl(&mut self) -> RXPL_W { + RXPL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Receive Pulse Length\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxpl](index.html) module"] +pub struct RXPL_SPEC; +impl crate::RegisterSpec for RXPL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [rxpl::R](R) reader structure"] +impl crate::Readable for RXPL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rxpl::W](W) writer structure"] +impl crate::Writable for RXPL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RXPL to value 0"] +impl crate::Resettable for RXPL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sercom0/usart_int/status.rs b/pac/atsamc21g/src/sercom0/usart_int/status.rs new file mode 100644 index 000000000000..1a92018a359b --- /dev/null +++ b/pac/atsamc21g/src/sercom0/usart_int/status.rs @@ -0,0 +1,395 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PERR` reader - Parity Error"] +pub struct PERR_R(crate::FieldReader); +impl PERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERR` writer - Parity Error"] +pub struct PERR_W<'a> { + w: &'a mut W, +} +impl<'a> PERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `FERR` reader - Frame Error"] +pub struct FERR_R(crate::FieldReader); +impl FERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FERR` writer - Frame Error"] +pub struct FERR_W<'a> { + w: &'a mut W, +} +impl<'a> FERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `BUFOVF` reader - Buffer Overflow"] +pub struct BUFOVF_R(crate::FieldReader); +impl BUFOVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUFOVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUFOVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUFOVF` writer - Buffer Overflow"] +pub struct BUFOVF_W<'a> { + w: &'a mut W, +} +impl<'a> BUFOVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CTS` reader - Clear To Send"] +pub struct CTS_R(crate::FieldReader); +impl CTS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTS` writer - Clear To Send"] +pub struct CTS_W<'a> { + w: &'a mut W, +} +impl<'a> CTS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ISF` reader - Inconsistent Sync Field"] +pub struct ISF_R(crate::FieldReader); +impl ISF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ISF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ISF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ISF` writer - Inconsistent Sync Field"] +pub struct ISF_W<'a> { + w: &'a mut W, +} +impl<'a> ISF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `COLL` reader - Collision Detected"] +pub struct COLL_R(crate::FieldReader); +impl COLL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COLL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COLL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COLL` writer - Collision Detected"] +pub struct COLL_W<'a> { + w: &'a mut W, +} +impl<'a> COLL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `TXE` reader - Transmitter Empty"] +pub struct TXE_R(crate::FieldReader); +impl TXE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXE` writer - Transmitter Empty"] +pub struct TXE_W<'a> { + w: &'a mut W, +} +impl<'a> TXE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - Parity Error"] + #[inline(always)] + pub fn perr(&self) -> PERR_R { + PERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Frame Error"] + #[inline(always)] + pub fn ferr(&self) -> FERR_R { + FERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&self) -> BUFOVF_R { + BUFOVF_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Clear To Send"] + #[inline(always)] + pub fn cts(&self) -> CTS_R { + CTS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Inconsistent Sync Field"] + #[inline(always)] + pub fn isf(&self) -> ISF_R { + ISF_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Collision Detected"] + #[inline(always)] + pub fn coll(&self) -> COLL_R { + COLL_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Transmitter Empty"] + #[inline(always)] + pub fn txe(&self) -> TXE_R { + TXE_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Parity Error"] + #[inline(always)] + pub fn perr(&mut self) -> PERR_W { + PERR_W { w: self } + } + #[doc = "Bit 1 - Frame Error"] + #[inline(always)] + pub fn ferr(&mut self) -> FERR_W { + FERR_W { w: self } + } + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&mut self) -> BUFOVF_W { + BUFOVF_W { w: self } + } + #[doc = "Bit 3 - Clear To Send"] + #[inline(always)] + pub fn cts(&mut self) -> CTS_W { + CTS_W { w: self } + } + #[doc = "Bit 4 - Inconsistent Sync Field"] + #[inline(always)] + pub fn isf(&mut self) -> ISF_W { + ISF_W { w: self } + } + #[doc = "Bit 5 - Collision Detected"] + #[inline(always)] + pub fn coll(&mut self) -> COLL_W { + COLL_W { w: self } + } + #[doc = "Bit 6 - Transmitter Empty"] + #[inline(always)] + pub fn txe(&mut self) -> TXE_W { + TXE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sercom0/usart_int/syncbusy.rs b/pac/atsamc21g/src/sercom0/usart_int/syncbusy.rs new file mode 100644 index 000000000000..5dea9a5a7bab --- /dev/null +++ b/pac/atsamc21g/src/sercom0/usart_int/syncbusy.rs @@ -0,0 +1,93 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - SERCOM Enable Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLB` reader - CTRLB Synchronization Busy"] +pub struct CTRLB_R(crate::FieldReader); +impl CTRLB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM Enable Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - CTRLB Synchronization Busy"] + #[inline(always)] + pub fn ctrlb(&self) -> CTRLB_R { + CTRLB_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +#[doc = "USART_INT Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/supc.rs b/pac/atsamc21g/src/supc.rs new file mode 100644 index 000000000000..452d8f3f9613 --- /dev/null +++ b/pac/atsamc21g/src/supc.rs @@ -0,0 +1,52 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x04 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x08 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x0c - Power and Clocks Status"] + pub status: crate::Reg, + #[doc = "0x10 - BODVDD Control"] + pub bodvdd: crate::Reg, + #[doc = "0x14 - BODCORE Control"] + pub bodcore: crate::Reg, + #[doc = "0x18 - VREG Control"] + pub vreg: crate::Reg, + #[doc = "0x1c - VREF Control"] + pub vref: crate::Reg, +} +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Power and Clocks Status"] +pub mod status; +#[doc = "BODVDD register accessor: an alias for `Reg`"] +pub type BODVDD = crate::Reg; +#[doc = "BODVDD Control"] +pub mod bodvdd; +#[doc = "BODCORE register accessor: an alias for `Reg`"] +pub type BODCORE = crate::Reg; +#[doc = "BODCORE Control"] +pub mod bodcore; +#[doc = "VREG register accessor: an alias for `Reg`"] +pub type VREG = crate::Reg; +#[doc = "VREG Control"] +pub mod vreg; +#[doc = "VREF register accessor: an alias for `Reg`"] +pub type VREF = crate::Reg; +#[doc = "VREF Control"] +pub mod vref; diff --git a/pac/atsamc21g/src/supc/bodcore.rs b/pac/atsamc21g/src/supc/bodcore.rs new file mode 100644 index 000000000000..670dec8e048c --- /dev/null +++ b/pac/atsamc21g/src/supc/bodcore.rs @@ -0,0 +1,705 @@ +#[doc = "Register `BODCORE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BODCORE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `HYST` reader - Hysteresis Enable"] +pub struct HYST_R(crate::FieldReader); +impl HYST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HYST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HYST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HYST` writer - Hysteresis Enable"] +pub struct HYST_W<'a> { + w: &'a mut W, +} +impl<'a> HYST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Action when Threshold Crossed\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum ACTION_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: The BODCORE generates a reset"] + RESET = 1, + #[doc = "2: The BODCORE generates an interrupt"] + INT = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: ACTION_A) -> Self { + variant as _ + } +} +#[doc = "Field `ACTION` reader - Action when Threshold Crossed"] +pub struct ACTION_R(crate::FieldReader); +impl ACTION_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ACTION_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(ACTION_A::NONE), + 1 => Some(ACTION_A::RESET), + 2 => Some(ACTION_A::INT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == ACTION_A::NONE + } + #[doc = "Checks if the value of the field is `RESET`"] + #[inline(always)] + pub fn is_reset(&self) -> bool { + **self == ACTION_A::RESET + } + #[doc = "Checks if the value of the field is `INT`"] + #[inline(always)] + pub fn is_int(&self) -> bool { + **self == ACTION_A::INT + } +} +impl core::ops::Deref for ACTION_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ACTION` writer - Action when Threshold Crossed"] +pub struct ACTION_W<'a> { + w: &'a mut W, +} +impl<'a> ACTION_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: ACTION_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(ACTION_A::NONE) + } + #[doc = "The BODCORE generates a reset"] + #[inline(always)] + pub fn reset(self) -> &'a mut W { + self.variant(ACTION_A::RESET) + } + #[doc = "The BODCORE generates an interrupt"] + #[inline(always)] + pub fn int(self) -> &'a mut W { + self.variant(ACTION_A::INT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 3)) | ((value as u32 & 0x03) << 3); + self.w + } +} +#[doc = "Field `STDBYCFG` reader - Configuration in Standby mode"] +pub struct STDBYCFG_R(crate::FieldReader); +impl STDBYCFG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STDBYCFG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STDBYCFG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STDBYCFG` writer - Configuration in Standby mode"] +pub struct STDBYCFG_W<'a> { + w: &'a mut W, +} +impl<'a> STDBYCFG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ACTCFG` reader - Configuration in Active mode"] +pub struct ACTCFG_R(crate::FieldReader); +impl ACTCFG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ACTCFG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ACTCFG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ACTCFG` writer - Configuration in Active mode"] +pub struct ACTCFG_W<'a> { + w: &'a mut W, +} +impl<'a> ACTCFG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Prescaler Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PSEL_A { + #[doc = "0: Divide clock by 2"] + DIV2 = 0, + #[doc = "1: Divide clock by 4"] + DIV4 = 1, + #[doc = "2: Divide clock by 8"] + DIV8 = 2, + #[doc = "3: Divide clock by 16"] + DIV16 = 3, + #[doc = "4: Divide clock by 32"] + DIV32 = 4, + #[doc = "5: Divide clock by 64"] + DIV64 = 5, + #[doc = "6: Divide clock by 128"] + DIV128 = 6, + #[doc = "7: Divide clock by 256"] + DIV256 = 7, + #[doc = "8: Divide clock by 512"] + DIV512 = 8, + #[doc = "9: Divide clock by 1024"] + DIV1024 = 9, + #[doc = "10: Divide clock by 2048"] + DIV2048 = 10, + #[doc = "11: Divide clock by 4096"] + DIV4096 = 11, + #[doc = "12: Divide clock by 8192"] + DIV8192 = 12, + #[doc = "13: Divide clock by 16384"] + DIV16384 = 13, + #[doc = "14: Divide clock by 32768"] + DIV32768 = 14, + #[doc = "15: Divide clock by 65536"] + DIV65536 = 15, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `PSEL` reader - Prescaler Select"] +pub struct PSEL_R(crate::FieldReader); +impl PSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PSEL_A { + match self.bits { + 0 => PSEL_A::DIV2, + 1 => PSEL_A::DIV4, + 2 => PSEL_A::DIV8, + 3 => PSEL_A::DIV16, + 4 => PSEL_A::DIV32, + 5 => PSEL_A::DIV64, + 6 => PSEL_A::DIV128, + 7 => PSEL_A::DIV256, + 8 => PSEL_A::DIV512, + 9 => PSEL_A::DIV1024, + 10 => PSEL_A::DIV2048, + 11 => PSEL_A::DIV4096, + 12 => PSEL_A::DIV8192, + 13 => PSEL_A::DIV16384, + 14 => PSEL_A::DIV32768, + 15 => PSEL_A::DIV65536, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PSEL_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PSEL_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PSEL_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PSEL_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == PSEL_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PSEL_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == PSEL_A::DIV128 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PSEL_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV512`"] + #[inline(always)] + pub fn is_div512(&self) -> bool { + **self == PSEL_A::DIV512 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PSEL_A::DIV1024 + } + #[doc = "Checks if the value of the field is `DIV2048`"] + #[inline(always)] + pub fn is_div2048(&self) -> bool { + **self == PSEL_A::DIV2048 + } + #[doc = "Checks if the value of the field is `DIV4096`"] + #[inline(always)] + pub fn is_div4096(&self) -> bool { + **self == PSEL_A::DIV4096 + } + #[doc = "Checks if the value of the field is `DIV8192`"] + #[inline(always)] + pub fn is_div8192(&self) -> bool { + **self == PSEL_A::DIV8192 + } + #[doc = "Checks if the value of the field is `DIV16384`"] + #[inline(always)] + pub fn is_div16384(&self) -> bool { + **self == PSEL_A::DIV16384 + } + #[doc = "Checks if the value of the field is `DIV32768`"] + #[inline(always)] + pub fn is_div32768(&self) -> bool { + **self == PSEL_A::DIV32768 + } + #[doc = "Checks if the value of the field is `DIV65536`"] + #[inline(always)] + pub fn is_div65536(&self) -> bool { + **self == PSEL_A::DIV65536 + } +} +impl core::ops::Deref for PSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PSEL` writer - Prescaler Select"] +pub struct PSEL_W<'a> { + w: &'a mut W, +} +impl<'a> PSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PSEL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Divide clock by 2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PSEL_A::DIV2) + } + #[doc = "Divide clock by 4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PSEL_A::DIV4) + } + #[doc = "Divide clock by 8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PSEL_A::DIV8) + } + #[doc = "Divide clock by 16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PSEL_A::DIV16) + } + #[doc = "Divide clock by 32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(PSEL_A::DIV32) + } + #[doc = "Divide clock by 64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PSEL_A::DIV64) + } + #[doc = "Divide clock by 128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(PSEL_A::DIV128) + } + #[doc = "Divide clock by 256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PSEL_A::DIV256) + } + #[doc = "Divide clock by 512"] + #[inline(always)] + pub fn div512(self) -> &'a mut W { + self.variant(PSEL_A::DIV512) + } + #[doc = "Divide clock by 1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PSEL_A::DIV1024) + } + #[doc = "Divide clock by 2048"] + #[inline(always)] + pub fn div2048(self) -> &'a mut W { + self.variant(PSEL_A::DIV2048) + } + #[doc = "Divide clock by 4096"] + #[inline(always)] + pub fn div4096(self) -> &'a mut W { + self.variant(PSEL_A::DIV4096) + } + #[doc = "Divide clock by 8192"] + #[inline(always)] + pub fn div8192(self) -> &'a mut W { + self.variant(PSEL_A::DIV8192) + } + #[doc = "Divide clock by 16384"] + #[inline(always)] + pub fn div16384(self) -> &'a mut W { + self.variant(PSEL_A::DIV16384) + } + #[doc = "Divide clock by 32768"] + #[inline(always)] + pub fn div32768(self) -> &'a mut W { + self.variant(PSEL_A::DIV32768) + } + #[doc = "Divide clock by 65536"] + #[inline(always)] + pub fn div65536(self) -> &'a mut W { + self.variant(PSEL_A::DIV65536) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 12)) | ((value as u32 & 0x0f) << 12); + self.w + } +} +#[doc = "Field `LEVEL` reader - Threshold Level"] +pub struct LEVEL_R(crate::FieldReader); +impl LEVEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LEVEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LEVEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LEVEL` writer - Threshold Level"] +pub struct LEVEL_W<'a> { + w: &'a mut W, +} +impl<'a> LEVEL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 16)) | ((value as u32 & 0x3f) << 16); + self.w + } +} +impl R { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Hysteresis Enable"] + #[inline(always)] + pub fn hyst(&self) -> HYST_R { + HYST_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 3:4 - Action when Threshold Crossed"] + #[inline(always)] + pub fn action(&self) -> ACTION_R { + ACTION_R::new(((self.bits >> 3) & 0x03) as u8) + } + #[doc = "Bit 5 - Configuration in Standby mode"] + #[inline(always)] + pub fn stdbycfg(&self) -> STDBYCFG_R { + STDBYCFG_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 8 - Configuration in Active mode"] + #[inline(always)] + pub fn actcfg(&self) -> ACTCFG_R { + ACTCFG_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bits 12:15 - Prescaler Select"] + #[inline(always)] + pub fn psel(&self) -> PSEL_R { + PSEL_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:21 - Threshold Level"] + #[inline(always)] + pub fn level(&self) -> LEVEL_R { + LEVEL_R::new(((self.bits >> 16) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - Hysteresis Enable"] + #[inline(always)] + pub fn hyst(&mut self) -> HYST_W { + HYST_W { w: self } + } + #[doc = "Bits 3:4 - Action when Threshold Crossed"] + #[inline(always)] + pub fn action(&mut self) -> ACTION_W { + ACTION_W { w: self } + } + #[doc = "Bit 5 - Configuration in Standby mode"] + #[inline(always)] + pub fn stdbycfg(&mut self) -> STDBYCFG_W { + STDBYCFG_W { w: self } + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 8 - Configuration in Active mode"] + #[inline(always)] + pub fn actcfg(&mut self) -> ACTCFG_W { + ACTCFG_W { w: self } + } + #[doc = "Bits 12:15 - Prescaler Select"] + #[inline(always)] + pub fn psel(&mut self) -> PSEL_W { + PSEL_W { w: self } + } + #[doc = "Bits 16:21 - Threshold Level"] + #[inline(always)] + pub fn level(&mut self) -> LEVEL_W { + LEVEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "BODCORE Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [bodcore](index.html) module"] +pub struct BODCORE_SPEC; +impl crate::RegisterSpec for BODCORE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [bodcore::R](R) reader structure"] +impl crate::Readable for BODCORE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [bodcore::W](W) writer structure"] +impl crate::Writable for BODCORE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BODCORE to value 0"] +impl crate::Resettable for BODCORE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/supc/bodvdd.rs b/pac/atsamc21g/src/supc/bodvdd.rs new file mode 100644 index 000000000000..f5cbfffb6453 --- /dev/null +++ b/pac/atsamc21g/src/supc/bodvdd.rs @@ -0,0 +1,705 @@ +#[doc = "Register `BODVDD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BODVDD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `HYST` reader - Hysteresis Enable"] +pub struct HYST_R(crate::FieldReader); +impl HYST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HYST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HYST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HYST` writer - Hysteresis Enable"] +pub struct HYST_W<'a> { + w: &'a mut W, +} +impl<'a> HYST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Action when Threshold Crossed\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum ACTION_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: The BODVDD generates a reset"] + RESET = 1, + #[doc = "2: The BODVDD generates an interrupt"] + INT = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: ACTION_A) -> Self { + variant as _ + } +} +#[doc = "Field `ACTION` reader - Action when Threshold Crossed"] +pub struct ACTION_R(crate::FieldReader); +impl ACTION_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ACTION_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(ACTION_A::NONE), + 1 => Some(ACTION_A::RESET), + 2 => Some(ACTION_A::INT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == ACTION_A::NONE + } + #[doc = "Checks if the value of the field is `RESET`"] + #[inline(always)] + pub fn is_reset(&self) -> bool { + **self == ACTION_A::RESET + } + #[doc = "Checks if the value of the field is `INT`"] + #[inline(always)] + pub fn is_int(&self) -> bool { + **self == ACTION_A::INT + } +} +impl core::ops::Deref for ACTION_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ACTION` writer - Action when Threshold Crossed"] +pub struct ACTION_W<'a> { + w: &'a mut W, +} +impl<'a> ACTION_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: ACTION_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(ACTION_A::NONE) + } + #[doc = "The BODVDD generates a reset"] + #[inline(always)] + pub fn reset(self) -> &'a mut W { + self.variant(ACTION_A::RESET) + } + #[doc = "The BODVDD generates an interrupt"] + #[inline(always)] + pub fn int(self) -> &'a mut W { + self.variant(ACTION_A::INT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 3)) | ((value as u32 & 0x03) << 3); + self.w + } +} +#[doc = "Field `STDBYCFG` reader - Configuration in Standby mode"] +pub struct STDBYCFG_R(crate::FieldReader); +impl STDBYCFG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STDBYCFG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STDBYCFG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STDBYCFG` writer - Configuration in Standby mode"] +pub struct STDBYCFG_W<'a> { + w: &'a mut W, +} +impl<'a> STDBYCFG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ACTCFG` reader - Configuration in Active mode"] +pub struct ACTCFG_R(crate::FieldReader); +impl ACTCFG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ACTCFG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ACTCFG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ACTCFG` writer - Configuration in Active mode"] +pub struct ACTCFG_W<'a> { + w: &'a mut W, +} +impl<'a> ACTCFG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Prescaler Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PSEL_A { + #[doc = "0: Divide clock by 2"] + DIV2 = 0, + #[doc = "1: Divide clock by 4"] + DIV4 = 1, + #[doc = "2: Divide clock by 8"] + DIV8 = 2, + #[doc = "3: Divide clock by 16"] + DIV16 = 3, + #[doc = "4: Divide clock by 32"] + DIV32 = 4, + #[doc = "5: Divide clock by 64"] + DIV64 = 5, + #[doc = "6: Divide clock by 128"] + DIV128 = 6, + #[doc = "7: Divide clock by 256"] + DIV256 = 7, + #[doc = "8: Divide clock by 512"] + DIV512 = 8, + #[doc = "9: Divide clock by 1024"] + DIV1024 = 9, + #[doc = "10: Divide clock by 2048"] + DIV2048 = 10, + #[doc = "11: Divide clock by 4096"] + DIV4096 = 11, + #[doc = "12: Divide clock by 8192"] + DIV8192 = 12, + #[doc = "13: Divide clock by 16384"] + DIV16384 = 13, + #[doc = "14: Divide clock by 32768"] + DIV32768 = 14, + #[doc = "15: Divide clock by 65536"] + DIV65536 = 15, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `PSEL` reader - Prescaler Select"] +pub struct PSEL_R(crate::FieldReader); +impl PSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PSEL_A { + match self.bits { + 0 => PSEL_A::DIV2, + 1 => PSEL_A::DIV4, + 2 => PSEL_A::DIV8, + 3 => PSEL_A::DIV16, + 4 => PSEL_A::DIV32, + 5 => PSEL_A::DIV64, + 6 => PSEL_A::DIV128, + 7 => PSEL_A::DIV256, + 8 => PSEL_A::DIV512, + 9 => PSEL_A::DIV1024, + 10 => PSEL_A::DIV2048, + 11 => PSEL_A::DIV4096, + 12 => PSEL_A::DIV8192, + 13 => PSEL_A::DIV16384, + 14 => PSEL_A::DIV32768, + 15 => PSEL_A::DIV65536, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PSEL_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PSEL_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PSEL_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PSEL_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == PSEL_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PSEL_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == PSEL_A::DIV128 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PSEL_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV512`"] + #[inline(always)] + pub fn is_div512(&self) -> bool { + **self == PSEL_A::DIV512 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PSEL_A::DIV1024 + } + #[doc = "Checks if the value of the field is `DIV2048`"] + #[inline(always)] + pub fn is_div2048(&self) -> bool { + **self == PSEL_A::DIV2048 + } + #[doc = "Checks if the value of the field is `DIV4096`"] + #[inline(always)] + pub fn is_div4096(&self) -> bool { + **self == PSEL_A::DIV4096 + } + #[doc = "Checks if the value of the field is `DIV8192`"] + #[inline(always)] + pub fn is_div8192(&self) -> bool { + **self == PSEL_A::DIV8192 + } + #[doc = "Checks if the value of the field is `DIV16384`"] + #[inline(always)] + pub fn is_div16384(&self) -> bool { + **self == PSEL_A::DIV16384 + } + #[doc = "Checks if the value of the field is `DIV32768`"] + #[inline(always)] + pub fn is_div32768(&self) -> bool { + **self == PSEL_A::DIV32768 + } + #[doc = "Checks if the value of the field is `DIV65536`"] + #[inline(always)] + pub fn is_div65536(&self) -> bool { + **self == PSEL_A::DIV65536 + } +} +impl core::ops::Deref for PSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PSEL` writer - Prescaler Select"] +pub struct PSEL_W<'a> { + w: &'a mut W, +} +impl<'a> PSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PSEL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Divide clock by 2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PSEL_A::DIV2) + } + #[doc = "Divide clock by 4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PSEL_A::DIV4) + } + #[doc = "Divide clock by 8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PSEL_A::DIV8) + } + #[doc = "Divide clock by 16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PSEL_A::DIV16) + } + #[doc = "Divide clock by 32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(PSEL_A::DIV32) + } + #[doc = "Divide clock by 64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PSEL_A::DIV64) + } + #[doc = "Divide clock by 128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(PSEL_A::DIV128) + } + #[doc = "Divide clock by 256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PSEL_A::DIV256) + } + #[doc = "Divide clock by 512"] + #[inline(always)] + pub fn div512(self) -> &'a mut W { + self.variant(PSEL_A::DIV512) + } + #[doc = "Divide clock by 1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PSEL_A::DIV1024) + } + #[doc = "Divide clock by 2048"] + #[inline(always)] + pub fn div2048(self) -> &'a mut W { + self.variant(PSEL_A::DIV2048) + } + #[doc = "Divide clock by 4096"] + #[inline(always)] + pub fn div4096(self) -> &'a mut W { + self.variant(PSEL_A::DIV4096) + } + #[doc = "Divide clock by 8192"] + #[inline(always)] + pub fn div8192(self) -> &'a mut W { + self.variant(PSEL_A::DIV8192) + } + #[doc = "Divide clock by 16384"] + #[inline(always)] + pub fn div16384(self) -> &'a mut W { + self.variant(PSEL_A::DIV16384) + } + #[doc = "Divide clock by 32768"] + #[inline(always)] + pub fn div32768(self) -> &'a mut W { + self.variant(PSEL_A::DIV32768) + } + #[doc = "Divide clock by 65536"] + #[inline(always)] + pub fn div65536(self) -> &'a mut W { + self.variant(PSEL_A::DIV65536) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 12)) | ((value as u32 & 0x0f) << 12); + self.w + } +} +#[doc = "Field `LEVEL` reader - Threshold Level for VDD"] +pub struct LEVEL_R(crate::FieldReader); +impl LEVEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LEVEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LEVEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LEVEL` writer - Threshold Level for VDD"] +pub struct LEVEL_W<'a> { + w: &'a mut W, +} +impl<'a> LEVEL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 16)) | ((value as u32 & 0x3f) << 16); + self.w + } +} +impl R { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Hysteresis Enable"] + #[inline(always)] + pub fn hyst(&self) -> HYST_R { + HYST_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 3:4 - Action when Threshold Crossed"] + #[inline(always)] + pub fn action(&self) -> ACTION_R { + ACTION_R::new(((self.bits >> 3) & 0x03) as u8) + } + #[doc = "Bit 5 - Configuration in Standby mode"] + #[inline(always)] + pub fn stdbycfg(&self) -> STDBYCFG_R { + STDBYCFG_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 8 - Configuration in Active mode"] + #[inline(always)] + pub fn actcfg(&self) -> ACTCFG_R { + ACTCFG_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bits 12:15 - Prescaler Select"] + #[inline(always)] + pub fn psel(&self) -> PSEL_R { + PSEL_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:21 - Threshold Level for VDD"] + #[inline(always)] + pub fn level(&self) -> LEVEL_R { + LEVEL_R::new(((self.bits >> 16) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - Hysteresis Enable"] + #[inline(always)] + pub fn hyst(&mut self) -> HYST_W { + HYST_W { w: self } + } + #[doc = "Bits 3:4 - Action when Threshold Crossed"] + #[inline(always)] + pub fn action(&mut self) -> ACTION_W { + ACTION_W { w: self } + } + #[doc = "Bit 5 - Configuration in Standby mode"] + #[inline(always)] + pub fn stdbycfg(&mut self) -> STDBYCFG_W { + STDBYCFG_W { w: self } + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 8 - Configuration in Active mode"] + #[inline(always)] + pub fn actcfg(&mut self) -> ACTCFG_W { + ACTCFG_W { w: self } + } + #[doc = "Bits 12:15 - Prescaler Select"] + #[inline(always)] + pub fn psel(&mut self) -> PSEL_W { + PSEL_W { w: self } + } + #[doc = "Bits 16:21 - Threshold Level for VDD"] + #[inline(always)] + pub fn level(&mut self) -> LEVEL_W { + LEVEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "BODVDD Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [bodvdd](index.html) module"] +pub struct BODVDD_SPEC; +impl crate::RegisterSpec for BODVDD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [bodvdd::R](R) reader structure"] +impl crate::Readable for BODVDD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [bodvdd::W](W) writer structure"] +impl crate::Writable for BODVDD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BODVDD to value 0"] +impl crate::Resettable for BODVDD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/supc/intenclr.rs b/pac/atsamc21g/src/supc/intenclr.rs new file mode 100644 index 000000000000..7b399544fafd --- /dev/null +++ b/pac/atsamc21g/src/supc/intenclr.rs @@ -0,0 +1,348 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BODVDDRDY` reader - BODVDD Ready"] +pub struct BODVDDRDY_R(crate::FieldReader); +impl BODVDDRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODVDDRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODVDDRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODVDDRDY` writer - BODVDD Ready"] +pub struct BODVDDRDY_W<'a> { + w: &'a mut W, +} +impl<'a> BODVDDRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `BODVDDDET` reader - BODVDD Detection"] +pub struct BODVDDDET_R(crate::FieldReader); +impl BODVDDDET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODVDDDET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODVDDDET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODVDDDET` writer - BODVDD Detection"] +pub struct BODVDDDET_W<'a> { + w: &'a mut W, +} +impl<'a> BODVDDDET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `BVDDSRDY` reader - BODVDD Synchronization Ready"] +pub struct BVDDSRDY_R(crate::FieldReader); +impl BVDDSRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BVDDSRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BVDDSRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BVDDSRDY` writer - BODVDD Synchronization Ready"] +pub struct BVDDSRDY_W<'a> { + w: &'a mut W, +} +impl<'a> BVDDSRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `BODCORERDY` reader - BODCORE Ready"] +pub struct BODCORERDY_R(crate::FieldReader); +impl BODCORERDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODCORERDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODCORERDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODCORERDY` writer - BODCORE Ready"] +pub struct BODCORERDY_W<'a> { + w: &'a mut W, +} +impl<'a> BODCORERDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `BODCOREDET` reader - BODCORE Detection"] +pub struct BODCOREDET_R(crate::FieldReader); +impl BODCOREDET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODCOREDET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODCOREDET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODCOREDET` writer - BODCORE Detection"] +pub struct BODCOREDET_W<'a> { + w: &'a mut W, +} +impl<'a> BODCOREDET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `BCORESRDY` reader - BODCORE Synchronization Ready"] +pub struct BCORESRDY_R(crate::FieldReader); +impl BCORESRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BCORESRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BCORESRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BCORESRDY` writer - BODCORE Synchronization Ready"] +pub struct BCORESRDY_W<'a> { + w: &'a mut W, +} +impl<'a> BCORESRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - BODVDD Ready"] + #[inline(always)] + pub fn bodvddrdy(&self) -> BODVDDRDY_R { + BODVDDRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - BODVDD Detection"] + #[inline(always)] + pub fn bodvdddet(&self) -> BODVDDDET_R { + BODVDDDET_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - BODVDD Synchronization Ready"] + #[inline(always)] + pub fn bvddsrdy(&self) -> BVDDSRDY_R { + BVDDSRDY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - BODCORE Ready"] + #[inline(always)] + pub fn bodcorerdy(&self) -> BODCORERDY_R { + BODCORERDY_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - BODCORE Detection"] + #[inline(always)] + pub fn bodcoredet(&self) -> BODCOREDET_R { + BODCOREDET_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - BODCORE Synchronization Ready"] + #[inline(always)] + pub fn bcoresrdy(&self) -> BCORESRDY_R { + BCORESRDY_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - BODVDD Ready"] + #[inline(always)] + pub fn bodvddrdy(&mut self) -> BODVDDRDY_W { + BODVDDRDY_W { w: self } + } + #[doc = "Bit 1 - BODVDD Detection"] + #[inline(always)] + pub fn bodvdddet(&mut self) -> BODVDDDET_W { + BODVDDDET_W { w: self } + } + #[doc = "Bit 2 - BODVDD Synchronization Ready"] + #[inline(always)] + pub fn bvddsrdy(&mut self) -> BVDDSRDY_W { + BVDDSRDY_W { w: self } + } + #[doc = "Bit 3 - BODCORE Ready"] + #[inline(always)] + pub fn bodcorerdy(&mut self) -> BODCORERDY_W { + BODCORERDY_W { w: self } + } + #[doc = "Bit 4 - BODCORE Detection"] + #[inline(always)] + pub fn bodcoredet(&mut self) -> BODCOREDET_W { + BODCOREDET_W { w: self } + } + #[doc = "Bit 5 - BODCORE Synchronization Ready"] + #[inline(always)] + pub fn bcoresrdy(&mut self) -> BCORESRDY_W { + BCORESRDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/supc/intenset.rs b/pac/atsamc21g/src/supc/intenset.rs new file mode 100644 index 000000000000..9e86a6e5b772 --- /dev/null +++ b/pac/atsamc21g/src/supc/intenset.rs @@ -0,0 +1,348 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BODVDDRDY` reader - BODVDD Ready"] +pub struct BODVDDRDY_R(crate::FieldReader); +impl BODVDDRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODVDDRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODVDDRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODVDDRDY` writer - BODVDD Ready"] +pub struct BODVDDRDY_W<'a> { + w: &'a mut W, +} +impl<'a> BODVDDRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `BODVDDDET` reader - BODVDD Detection"] +pub struct BODVDDDET_R(crate::FieldReader); +impl BODVDDDET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODVDDDET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODVDDDET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODVDDDET` writer - BODVDD Detection"] +pub struct BODVDDDET_W<'a> { + w: &'a mut W, +} +impl<'a> BODVDDDET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `BVDDSRDY` reader - BODVDD Synchronization Ready"] +pub struct BVDDSRDY_R(crate::FieldReader); +impl BVDDSRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BVDDSRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BVDDSRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BVDDSRDY` writer - BODVDD Synchronization Ready"] +pub struct BVDDSRDY_W<'a> { + w: &'a mut W, +} +impl<'a> BVDDSRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `BODCORERDY` reader - BODCORE Ready"] +pub struct BODCORERDY_R(crate::FieldReader); +impl BODCORERDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODCORERDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODCORERDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODCORERDY` writer - BODCORE Ready"] +pub struct BODCORERDY_W<'a> { + w: &'a mut W, +} +impl<'a> BODCORERDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `BODCOREDET` reader - BODCORE Detection"] +pub struct BODCOREDET_R(crate::FieldReader); +impl BODCOREDET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODCOREDET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODCOREDET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODCOREDET` writer - BODCORE Detection"] +pub struct BODCOREDET_W<'a> { + w: &'a mut W, +} +impl<'a> BODCOREDET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `BCORESRDY` reader - BODCORE Synchronization Ready"] +pub struct BCORESRDY_R(crate::FieldReader); +impl BCORESRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BCORESRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BCORESRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BCORESRDY` writer - BODCORE Synchronization Ready"] +pub struct BCORESRDY_W<'a> { + w: &'a mut W, +} +impl<'a> BCORESRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - BODVDD Ready"] + #[inline(always)] + pub fn bodvddrdy(&self) -> BODVDDRDY_R { + BODVDDRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - BODVDD Detection"] + #[inline(always)] + pub fn bodvdddet(&self) -> BODVDDDET_R { + BODVDDDET_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - BODVDD Synchronization Ready"] + #[inline(always)] + pub fn bvddsrdy(&self) -> BVDDSRDY_R { + BVDDSRDY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - BODCORE Ready"] + #[inline(always)] + pub fn bodcorerdy(&self) -> BODCORERDY_R { + BODCORERDY_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - BODCORE Detection"] + #[inline(always)] + pub fn bodcoredet(&self) -> BODCOREDET_R { + BODCOREDET_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - BODCORE Synchronization Ready"] + #[inline(always)] + pub fn bcoresrdy(&self) -> BCORESRDY_R { + BCORESRDY_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - BODVDD Ready"] + #[inline(always)] + pub fn bodvddrdy(&mut self) -> BODVDDRDY_W { + BODVDDRDY_W { w: self } + } + #[doc = "Bit 1 - BODVDD Detection"] + #[inline(always)] + pub fn bodvdddet(&mut self) -> BODVDDDET_W { + BODVDDDET_W { w: self } + } + #[doc = "Bit 2 - BODVDD Synchronization Ready"] + #[inline(always)] + pub fn bvddsrdy(&mut self) -> BVDDSRDY_W { + BVDDSRDY_W { w: self } + } + #[doc = "Bit 3 - BODCORE Ready"] + #[inline(always)] + pub fn bodcorerdy(&mut self) -> BODCORERDY_W { + BODCORERDY_W { w: self } + } + #[doc = "Bit 4 - BODCORE Detection"] + #[inline(always)] + pub fn bodcoredet(&mut self) -> BODCOREDET_W { + BODCOREDET_W { w: self } + } + #[doc = "Bit 5 - BODCORE Synchronization Ready"] + #[inline(always)] + pub fn bcoresrdy(&mut self) -> BCORESRDY_W { + BCORESRDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/supc/intflag.rs b/pac/atsamc21g/src/supc/intflag.rs new file mode 100644 index 000000000000..46b4b52add2d --- /dev/null +++ b/pac/atsamc21g/src/supc/intflag.rs @@ -0,0 +1,348 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BODVDDRDY` reader - BODVDD Ready"] +pub struct BODVDDRDY_R(crate::FieldReader); +impl BODVDDRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODVDDRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODVDDRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODVDDRDY` writer - BODVDD Ready"] +pub struct BODVDDRDY_W<'a> { + w: &'a mut W, +} +impl<'a> BODVDDRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `BODVDDDET` reader - BODVDD Detection"] +pub struct BODVDDDET_R(crate::FieldReader); +impl BODVDDDET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODVDDDET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODVDDDET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODVDDDET` writer - BODVDD Detection"] +pub struct BODVDDDET_W<'a> { + w: &'a mut W, +} +impl<'a> BODVDDDET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `BVDDSRDY` reader - BODVDD Synchronization Ready"] +pub struct BVDDSRDY_R(crate::FieldReader); +impl BVDDSRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BVDDSRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BVDDSRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BVDDSRDY` writer - BODVDD Synchronization Ready"] +pub struct BVDDSRDY_W<'a> { + w: &'a mut W, +} +impl<'a> BVDDSRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `BODCORERDY` reader - BODCORE Ready"] +pub struct BODCORERDY_R(crate::FieldReader); +impl BODCORERDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODCORERDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODCORERDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODCORERDY` writer - BODCORE Ready"] +pub struct BODCORERDY_W<'a> { + w: &'a mut W, +} +impl<'a> BODCORERDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `BODCOREDET` reader - BODCORE Detection"] +pub struct BODCOREDET_R(crate::FieldReader); +impl BODCOREDET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODCOREDET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODCOREDET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODCOREDET` writer - BODCORE Detection"] +pub struct BODCOREDET_W<'a> { + w: &'a mut W, +} +impl<'a> BODCOREDET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `BCORESRDY` reader - BODCORE Synchronization Ready"] +pub struct BCORESRDY_R(crate::FieldReader); +impl BCORESRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BCORESRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BCORESRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BCORESRDY` writer - BODCORE Synchronization Ready"] +pub struct BCORESRDY_W<'a> { + w: &'a mut W, +} +impl<'a> BCORESRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - BODVDD Ready"] + #[inline(always)] + pub fn bodvddrdy(&self) -> BODVDDRDY_R { + BODVDDRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - BODVDD Detection"] + #[inline(always)] + pub fn bodvdddet(&self) -> BODVDDDET_R { + BODVDDDET_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - BODVDD Synchronization Ready"] + #[inline(always)] + pub fn bvddsrdy(&self) -> BVDDSRDY_R { + BVDDSRDY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - BODCORE Ready"] + #[inline(always)] + pub fn bodcorerdy(&self) -> BODCORERDY_R { + BODCORERDY_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - BODCORE Detection"] + #[inline(always)] + pub fn bodcoredet(&self) -> BODCOREDET_R { + BODCOREDET_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - BODCORE Synchronization Ready"] + #[inline(always)] + pub fn bcoresrdy(&self) -> BCORESRDY_R { + BCORESRDY_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - BODVDD Ready"] + #[inline(always)] + pub fn bodvddrdy(&mut self) -> BODVDDRDY_W { + BODVDDRDY_W { w: self } + } + #[doc = "Bit 1 - BODVDD Detection"] + #[inline(always)] + pub fn bodvdddet(&mut self) -> BODVDDDET_W { + BODVDDDET_W { w: self } + } + #[doc = "Bit 2 - BODVDD Synchronization Ready"] + #[inline(always)] + pub fn bvddsrdy(&mut self) -> BVDDSRDY_W { + BVDDSRDY_W { w: self } + } + #[doc = "Bit 3 - BODCORE Ready"] + #[inline(always)] + pub fn bodcorerdy(&mut self) -> BODCORERDY_W { + BODCORERDY_W { w: self } + } + #[doc = "Bit 4 - BODCORE Detection"] + #[inline(always)] + pub fn bodcoredet(&mut self) -> BODCOREDET_W { + BODCOREDET_W { w: self } + } + #[doc = "Bit 5 - BODCORE Synchronization Ready"] + #[inline(always)] + pub fn bcoresrdy(&mut self) -> BCORESRDY_W { + BCORESRDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/supc/status.rs b/pac/atsamc21g/src/supc/status.rs new file mode 100644 index 000000000000..0fc1de3635b5 --- /dev/null +++ b/pac/atsamc21g/src/supc/status.rs @@ -0,0 +1,153 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `BODVDDRDY` reader - BODVDD Ready"] +pub struct BODVDDRDY_R(crate::FieldReader); +impl BODVDDRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODVDDRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODVDDRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODVDDDET` reader - BODVDD Detection"] +pub struct BODVDDDET_R(crate::FieldReader); +impl BODVDDDET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODVDDDET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODVDDDET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BVDDSRDY` reader - BODVDD Synchronization Ready"] +pub struct BVDDSRDY_R(crate::FieldReader); +impl BVDDSRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BVDDSRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BVDDSRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODCORERDY` reader - BODCORE Ready"] +pub struct BODCORERDY_R(crate::FieldReader); +impl BODCORERDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODCORERDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODCORERDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODCOREDET` reader - BODCORE Detection"] +pub struct BODCOREDET_R(crate::FieldReader); +impl BODCOREDET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODCOREDET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODCOREDET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BCORESRDY` reader - BODCORE Synchronization Ready"] +pub struct BCORESRDY_R(crate::FieldReader); +impl BCORESRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BCORESRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BCORESRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - BODVDD Ready"] + #[inline(always)] + pub fn bodvddrdy(&self) -> BODVDDRDY_R { + BODVDDRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - BODVDD Detection"] + #[inline(always)] + pub fn bodvdddet(&self) -> BODVDDDET_R { + BODVDDDET_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - BODVDD Synchronization Ready"] + #[inline(always)] + pub fn bvddsrdy(&self) -> BVDDSRDY_R { + BVDDSRDY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - BODCORE Ready"] + #[inline(always)] + pub fn bodcorerdy(&self) -> BODCORERDY_R { + BODCORERDY_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - BODCORE Detection"] + #[inline(always)] + pub fn bodcoredet(&self) -> BODCOREDET_R { + BODCOREDET_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - BODCORE Synchronization Ready"] + #[inline(always)] + pub fn bcoresrdy(&self) -> BCORESRDY_R { + BCORESRDY_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +#[doc = "Power and Clocks Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/supc/vref.rs b/pac/atsamc21g/src/supc/vref.rs new file mode 100644 index 000000000000..2d5b1381885e --- /dev/null +++ b/pac/atsamc21g/src/supc/vref.rs @@ -0,0 +1,353 @@ +#[doc = "Register `VREF` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `VREF` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TSEN` reader - Temperature Sensor Output Enable"] +pub struct TSEN_R(crate::FieldReader); +impl TSEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSEN` writer - Temperature Sensor Output Enable"] +pub struct TSEN_W<'a> { + w: &'a mut W, +} +impl<'a> TSEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `VREFOE` reader - Voltage Reference Output Enable"] +pub struct VREFOE_R(crate::FieldReader); +impl VREFOE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + VREFOE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VREFOE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VREFOE` writer - Voltage Reference Output Enable"] +pub struct VREFOE_W<'a> { + w: &'a mut W, +} +impl<'a> VREFOE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - On Demand Contrl"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - On Demand Contrl"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Voltage Reference Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SEL_A { + #[doc = "0: 1.024V voltage reference typical value"] + _1V024 = 0, + #[doc = "2: 2.048V voltage reference typical value"] + _2V048 = 2, + #[doc = "3: 4.096V voltage reference typical value"] + _4V096 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `SEL` reader - Voltage Reference Selection"] +pub struct SEL_R(crate::FieldReader); +impl SEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEL_A::_1V024), + 2 => Some(SEL_A::_2V048), + 3 => Some(SEL_A::_4V096), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_1V024`"] + #[inline(always)] + pub fn is_1v024(&self) -> bool { + **self == SEL_A::_1V024 + } + #[doc = "Checks if the value of the field is `_2V048`"] + #[inline(always)] + pub fn is_2v048(&self) -> bool { + **self == SEL_A::_2V048 + } + #[doc = "Checks if the value of the field is `_4V096`"] + #[inline(always)] + pub fn is_4v096(&self) -> bool { + **self == SEL_A::_4V096 + } +} +impl core::ops::Deref for SEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEL` writer - Voltage Reference Selection"] +pub struct SEL_W<'a> { + w: &'a mut W, +} +impl<'a> SEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SEL_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "1.024V voltage reference typical value"] + #[inline(always)] + pub fn _1v024(self) -> &'a mut W { + self.variant(SEL_A::_1V024) + } + #[doc = "2.048V voltage reference typical value"] + #[inline(always)] + pub fn _2v048(self) -> &'a mut W { + self.variant(SEL_A::_2V048) + } + #[doc = "4.096V voltage reference typical value"] + #[inline(always)] + pub fn _4v096(self) -> &'a mut W { + self.variant(SEL_A::_4V096) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 16)) | ((value as u32 & 0x0f) << 16); + self.w + } +} +impl R { + #[doc = "Bit 1 - Temperature Sensor Output Enable"] + #[inline(always)] + pub fn tsen(&self) -> TSEN_R { + TSEN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Voltage Reference Output Enable"] + #[inline(always)] + pub fn vrefoe(&self) -> VREFOE_R { + VREFOE_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - On Demand Contrl"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 16:19 - Voltage Reference Selection"] + #[inline(always)] + pub fn sel(&self) -> SEL_R { + SEL_R::new(((self.bits >> 16) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bit 1 - Temperature Sensor Output Enable"] + #[inline(always)] + pub fn tsen(&mut self) -> TSEN_W { + TSEN_W { w: self } + } + #[doc = "Bit 2 - Voltage Reference Output Enable"] + #[inline(always)] + pub fn vrefoe(&mut self) -> VREFOE_W { + VREFOE_W { w: self } + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - On Demand Contrl"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Bits 16:19 - Voltage Reference Selection"] + #[inline(always)] + pub fn sel(&mut self) -> SEL_W { + SEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "VREF Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [vref](index.html) module"] +pub struct VREF_SPEC; +impl crate::RegisterSpec for VREF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [vref::R](R) reader structure"] +impl crate::Readable for VREF_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [vref::W](W) writer structure"] +impl crate::Writable for VREF_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets VREF to value 0"] +impl crate::Resettable for VREF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/supc/vreg.rs b/pac/atsamc21g/src/supc/vreg.rs new file mode 100644 index 000000000000..fb5b12a185cf --- /dev/null +++ b/pac/atsamc21g/src/supc/vreg.rs @@ -0,0 +1,160 @@ +#[doc = "Register `VREG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `VREG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "VREG Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [vreg](index.html) module"] +pub struct VREG_SPEC; +impl crate::RegisterSpec for VREG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [vreg::R](R) reader structure"] +impl crate::Readable for VREG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [vreg::W](W) writer structure"] +impl crate::Writable for VREG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets VREG to value 0"] +impl crate::Resettable for VREG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sys_tick.rs b/pac/atsamc21g/src/sys_tick.rs new file mode 100644 index 000000000000..b0fe7a59e5ed --- /dev/null +++ b/pac/atsamc21g/src/sys_tick.rs @@ -0,0 +1,28 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - SysTick Control and Status Register"] + pub csr: crate::Reg, + #[doc = "0x04 - SysTick Reload Value Register"] + pub rvr: crate::Reg, + #[doc = "0x08 - SysTick Current Value Register"] + pub cvr: crate::Reg, + #[doc = "0x0c - SysTick Calibration Value Register"] + pub calib: crate::Reg, +} +#[doc = "CSR register accessor: an alias for `Reg`"] +pub type CSR = crate::Reg; +#[doc = "SysTick Control and Status Register"] +pub mod csr; +#[doc = "RVR register accessor: an alias for `Reg`"] +pub type RVR = crate::Reg; +#[doc = "SysTick Reload Value Register"] +pub mod rvr; +#[doc = "CVR register accessor: an alias for `Reg`"] +pub type CVR = crate::Reg; +#[doc = "SysTick Current Value Register"] +pub mod cvr; +#[doc = "CALIB register accessor: an alias for `Reg`"] +pub type CALIB = crate::Reg; +#[doc = "SysTick Calibration Value Register"] +pub mod calib; diff --git a/pac/atsamc21g/src/sys_tick/calib.rs b/pac/atsamc21g/src/sys_tick/calib.rs new file mode 100644 index 000000000000..df7fd80f773a --- /dev/null +++ b/pac/atsamc21g/src/sys_tick/calib.rs @@ -0,0 +1,157 @@ +#[doc = "Register `CALIB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `TENMS` reader - Reload value to use for 10ms timing"] +pub struct TENMS_R(crate::FieldReader); +impl TENMS_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + TENMS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TENMS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "TENMS is rounded from non-integer ratio\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SKEW_A { + #[doc = "0: 10ms calibration value is exact"] + VALUE_0 = 0, + #[doc = "1: 10ms calibration value is inexact, because of the clock frequency"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SKEW_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SKEW` reader - TENMS is rounded from non-integer ratio"] +pub struct SKEW_R(crate::FieldReader); +impl SKEW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SKEW_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SKEW_A { + match self.bits { + false => SKEW_A::VALUE_0, + true => SKEW_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == SKEW_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == SKEW_A::VALUE_1 + } +} +impl core::ops::Deref for SKEW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "No Separate Reference Clock\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum NOREF_A { + #[doc = "0: The reference clock is provided"] + VALUE_0 = 0, + #[doc = "1: The reference clock is not provided"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NOREF_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NOREF` reader - No Separate Reference Clock"] +pub struct NOREF_R(crate::FieldReader); +impl NOREF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NOREF_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> NOREF_A { + match self.bits { + false => NOREF_A::VALUE_0, + true => NOREF_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == NOREF_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == NOREF_A::VALUE_1 + } +} +impl core::ops::Deref for NOREF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:23 - Reload value to use for 10ms timing"] + #[inline(always)] + pub fn tenms(&self) -> TENMS_R { + TENMS_R::new((self.bits & 0x00ff_ffff) as u32) + } + #[doc = "Bit 30 - TENMS is rounded from non-integer ratio"] + #[inline(always)] + pub fn skew(&self) -> SKEW_R { + SKEW_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 31 - No Separate Reference Clock"] + #[inline(always)] + pub fn noref(&self) -> NOREF_R { + NOREF_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +#[doc = "SysTick Calibration Value Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [calib](index.html) module"] +pub struct CALIB_SPEC; +impl crate::RegisterSpec for CALIB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [calib::R](R) reader structure"] +impl crate::Readable for CALIB_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CALIB to value 0"] +impl crate::Resettable for CALIB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sys_tick/csr.rs b/pac/atsamc21g/src/sys_tick/csr.rs new file mode 100644 index 000000000000..872d637f5a86 --- /dev/null +++ b/pac/atsamc21g/src/sys_tick/csr.rs @@ -0,0 +1,395 @@ +#[doc = "Register `CSR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CSR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "SysTick Counter Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ENABLE_A { + #[doc = "0: Counter disabled"] + VALUE_0 = 0, + #[doc = "1: Counter enabled"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ENABLE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ENABLE` reader - SysTick Counter Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ENABLE_A { + match self.bits { + false => ENABLE_A::VALUE_0, + true => ENABLE_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == ENABLE_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == ENABLE_A::VALUE_1 + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - SysTick Counter Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: ENABLE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Counter disabled"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(ENABLE_A::VALUE_0) + } + #[doc = "Counter enabled"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(ENABLE_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "SysTick Exception Request Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TICKINT_A { + #[doc = "0: Counting down to 0 does not assert the SysTick exception request"] + VALUE_0 = 0, + #[doc = "1: Counting down to 0 asserts the SysTick exception request"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TICKINT_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TICKINT` reader - SysTick Exception Request Enable"] +pub struct TICKINT_R(crate::FieldReader); +impl TICKINT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TICKINT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TICKINT_A { + match self.bits { + false => TICKINT_A::VALUE_0, + true => TICKINT_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == TICKINT_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == TICKINT_A::VALUE_1 + } +} +impl core::ops::Deref for TICKINT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TICKINT` writer - SysTick Exception Request Enable"] +pub struct TICKINT_W<'a> { + w: &'a mut W, +} +impl<'a> TICKINT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TICKINT_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Counting down to 0 does not assert the SysTick exception request"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(TICKINT_A::VALUE_0) + } + #[doc = "Counting down to 0 asserts the SysTick exception request"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(TICKINT_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Clock Source 0=external, 1=processor\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CLKSOURCE_A { + #[doc = "0: External clock"] + VALUE_0 = 0, + #[doc = "1: Processor clock"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CLKSOURCE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CLKSOURCE` reader - Clock Source 0=external, 1=processor"] +pub struct CLKSOURCE_R(crate::FieldReader); +impl CLKSOURCE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKSOURCE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CLKSOURCE_A { + match self.bits { + false => CLKSOURCE_A::VALUE_0, + true => CLKSOURCE_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == CLKSOURCE_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == CLKSOURCE_A::VALUE_1 + } +} +impl core::ops::Deref for CLKSOURCE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKSOURCE` writer - Clock Source 0=external, 1=processor"] +pub struct CLKSOURCE_W<'a> { + w: &'a mut W, +} +impl<'a> CLKSOURCE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CLKSOURCE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "External clock"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(CLKSOURCE_A::VALUE_0) + } + #[doc = "Processor clock"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(CLKSOURCE_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `COUNTFLAG` reader - Timer counted to 0 since last read of register"] +pub struct COUNTFLAG_R(crate::FieldReader); +impl COUNTFLAG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNTFLAG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNTFLAG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNTFLAG` writer - Timer counted to 0 since last read of register"] +pub struct COUNTFLAG_W<'a> { + w: &'a mut W, +} +impl<'a> COUNTFLAG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +impl R { + #[doc = "Bit 0 - SysTick Counter Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SysTick Exception Request Enable"] + #[inline(always)] + pub fn tickint(&self) -> TICKINT_R { + TICKINT_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Clock Source 0=external, 1=processor"] + #[inline(always)] + pub fn clksource(&self) -> CLKSOURCE_R { + CLKSOURCE_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 16 - Timer counted to 0 since last read of register"] + #[inline(always)] + pub fn countflag(&self) -> COUNTFLAG_R { + COUNTFLAG_R::new(((self.bits >> 16) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - SysTick Counter Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 1 - SysTick Exception Request Enable"] + #[inline(always)] + pub fn tickint(&mut self) -> TICKINT_W { + TICKINT_W { w: self } + } + #[doc = "Bit 2 - Clock Source 0=external, 1=processor"] + #[inline(always)] + pub fn clksource(&mut self) -> CLKSOURCE_W { + CLKSOURCE_W { w: self } + } + #[doc = "Bit 16 - Timer counted to 0 since last read of register"] + #[inline(always)] + pub fn countflag(&mut self) -> COUNTFLAG_W { + COUNTFLAG_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SysTick Control and Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [csr](index.html) module"] +pub struct CSR_SPEC; +impl crate::RegisterSpec for CSR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [csr::R](R) reader structure"] +impl crate::Readable for CSR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [csr::W](W) writer structure"] +impl crate::Writable for CSR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CSR to value 0x04"] +impl crate::Resettable for CSR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x04 + } +} diff --git a/pac/atsamc21g/src/sys_tick/cvr.rs b/pac/atsamc21g/src/sys_tick/cvr.rs new file mode 100644 index 000000000000..8a40b5f43b3a --- /dev/null +++ b/pac/atsamc21g/src/sys_tick/cvr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `CVR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CVR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CURRENT` reader - Current value at the time the register is accessed"] +pub struct CURRENT_R(crate::FieldReader); +impl CURRENT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CURRENT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CURRENT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CURRENT` writer - Current value at the time the register is accessed"] +pub struct CURRENT_W<'a> { + w: &'a mut W, +} +impl<'a> CURRENT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Current value at the time the register is accessed"] + #[inline(always)] + pub fn current(&self) -> CURRENT_R { + CURRENT_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Current value at the time the register is accessed"] + #[inline(always)] + pub fn current(&mut self) -> CURRENT_W { + CURRENT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SysTick Current Value Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cvr](index.html) module"] +pub struct CVR_SPEC; +impl crate::RegisterSpec for CVR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cvr::R](R) reader structure"] +impl crate::Readable for CVR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cvr::W](W) writer structure"] +impl crate::Writable for CVR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CVR to value 0"] +impl crate::Resettable for CVR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/sys_tick/rvr.rs b/pac/atsamc21g/src/sys_tick/rvr.rs new file mode 100644 index 000000000000..ac023ff75f36 --- /dev/null +++ b/pac/atsamc21g/src/sys_tick/rvr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `RVR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RVR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RELOAD` reader - Value to load into the SysTick Current Value Register when the counter reaches 0"] +pub struct RELOAD_R(crate::FieldReader); +impl RELOAD_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + RELOAD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RELOAD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RELOAD` writer - Value to load into the SysTick Current Value Register when the counter reaches 0"] +pub struct RELOAD_W<'a> { + w: &'a mut W, +} +impl<'a> RELOAD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Value to load into the SysTick Current Value Register when the counter reaches 0"] + #[inline(always)] + pub fn reload(&self) -> RELOAD_R { + RELOAD_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Value to load into the SysTick Current Value Register when the counter reaches 0"] + #[inline(always)] + pub fn reload(&mut self) -> RELOAD_W { + RELOAD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SysTick Reload Value Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rvr](index.html) module"] +pub struct RVR_SPEC; +impl crate::RegisterSpec for RVR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rvr::R](R) reader structure"] +impl crate::Readable for RVR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rvr::W](W) writer structure"] +impl crate::Writable for RVR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RVR to value 0"] +impl crate::Resettable for RVR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/system_control.rs b/pac/atsamc21g/src/system_control.rs new file mode 100644 index 000000000000..4894b22b258f --- /dev/null +++ b/pac/atsamc21g/src/system_control.rs @@ -0,0 +1,67 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved0: [u8; 0x0d00], + #[doc = "0xd00 - CPUID Base Register"] + pub cpuid: crate::Reg, + #[doc = "0xd04 - Interrupt Control and State Register"] + pub icsr: crate::Reg, + #[doc = "0xd08 - Vector Table Offset Register"] + pub vtor: crate::Reg, + #[doc = "0xd0c - Application Interrupt and Reset Control Register"] + pub aircr: crate::Reg, + #[doc = "0xd10 - System Control Register"] + pub scr: crate::Reg, + #[doc = "0xd14 - Configuration and Control Register"] + pub ccr: crate::Reg, + _reserved6: [u8; 0x04], + #[doc = "0xd1c - System Handler Priority Register 2"] + pub shpr2: crate::Reg, + #[doc = "0xd20 - System Handler Priority Register 3"] + pub shpr3: crate::Reg, + #[doc = "0xd24 - System Handler Control and State Register"] + pub shcsr: crate::Reg, + _reserved9: [u8; 0x08], + #[doc = "0xd30 - Debug Fault Status Register"] + pub dfsr: crate::Reg, +} +#[doc = "CPUID register accessor: an alias for `Reg`"] +pub type CPUID = crate::Reg; +#[doc = "CPUID Base Register"] +pub mod cpuid; +#[doc = "ICSR register accessor: an alias for `Reg`"] +pub type ICSR = crate::Reg; +#[doc = "Interrupt Control and State Register"] +pub mod icsr; +#[doc = "VTOR register accessor: an alias for `Reg`"] +pub type VTOR = crate::Reg; +#[doc = "Vector Table Offset Register"] +pub mod vtor; +#[doc = "AIRCR register accessor: an alias for `Reg`"] +pub type AIRCR = crate::Reg; +#[doc = "Application Interrupt and Reset Control Register"] +pub mod aircr; +#[doc = "SCR register accessor: an alias for `Reg`"] +pub type SCR = crate::Reg; +#[doc = "System Control Register"] +pub mod scr; +#[doc = "CCR register accessor: an alias for `Reg`"] +pub type CCR = crate::Reg; +#[doc = "Configuration and Control Register"] +pub mod ccr; +#[doc = "SHPR2 register accessor: an alias for `Reg`"] +pub type SHPR2 = crate::Reg; +#[doc = "System Handler Priority Register 2"] +pub mod shpr2; +#[doc = "SHPR3 register accessor: an alias for `Reg`"] +pub type SHPR3 = crate::Reg; +#[doc = "System Handler Priority Register 3"] +pub mod shpr3; +#[doc = "SHCSR register accessor: an alias for `Reg`"] +pub type SHCSR = crate::Reg; +#[doc = "System Handler Control and State Register"] +pub mod shcsr; +#[doc = "DFSR register accessor: an alias for `Reg`"] +pub type DFSR = crate::Reg; +#[doc = "Debug Fault Status Register"] +pub mod dfsr; diff --git a/pac/atsamc21g/src/system_control/aircr.rs b/pac/atsamc21g/src/system_control/aircr.rs new file mode 100644 index 000000000000..9453cc6f30bc --- /dev/null +++ b/pac/atsamc21g/src/system_control/aircr.rs @@ -0,0 +1,338 @@ +#[doc = "Register `AIRCR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `AIRCR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `VECTCLRACTIVE` reader - Debug: Clear state information"] +pub struct VECTCLRACTIVE_R(crate::FieldReader); +impl VECTCLRACTIVE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + VECTCLRACTIVE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VECTCLRACTIVE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VECTCLRACTIVE` writer - Debug: Clear state information"] +pub struct VECTCLRACTIVE_W<'a> { + w: &'a mut W, +} +impl<'a> VECTCLRACTIVE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "System Reset Request\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SYSRESETREQ_A { + #[doc = "0: No system reset request"] + VALUE_0 = 0, + #[doc = "1: Asserts a signal to the outer system that requests a reset"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SYSRESETREQ_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SYSRESETREQ` reader - System Reset Request"] +pub struct SYSRESETREQ_R(crate::FieldReader); +impl SYSRESETREQ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYSRESETREQ_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SYSRESETREQ_A { + match self.bits { + false => SYSRESETREQ_A::VALUE_0, + true => SYSRESETREQ_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == SYSRESETREQ_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == SYSRESETREQ_A::VALUE_1 + } +} +impl core::ops::Deref for SYSRESETREQ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYSRESETREQ` writer - System Reset Request"] +pub struct SYSRESETREQ_W<'a> { + w: &'a mut W, +} +impl<'a> SYSRESETREQ_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SYSRESETREQ_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "No system reset request"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(SYSRESETREQ_A::VALUE_0) + } + #[doc = "Asserts a signal to the outer system that requests a reset"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(SYSRESETREQ_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Data Endianness, 0=little, 1=big\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ENDIANNESS_A { + #[doc = "0: Little-endian"] + VALUE_0 = 0, + #[doc = "1: Big-endian"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ENDIANNESS_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ENDIANNESS` reader - Data Endianness, 0=little, 1=big"] +pub struct ENDIANNESS_R(crate::FieldReader); +impl ENDIANNESS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENDIANNESS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ENDIANNESS_A { + match self.bits { + false => ENDIANNESS_A::VALUE_0, + true => ENDIANNESS_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == ENDIANNESS_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == ENDIANNESS_A::VALUE_1 + } +} +impl core::ops::Deref for ENDIANNESS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENDIANNESS` writer - Data Endianness, 0=little, 1=big"] +pub struct ENDIANNESS_W<'a> { + w: &'a mut W, +} +impl<'a> ENDIANNESS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: ENDIANNESS_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Little-endian"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(ENDIANNESS_A::VALUE_0) + } + #[doc = "Big-endian"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(ENDIANNESS_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `VECTKEY` reader - Register key (0x05FA)"] +pub struct VECTKEY_R(crate::FieldReader); +impl VECTKEY_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + VECTKEY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VECTKEY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VECTKEY` writer - Register key (0x05FA)"] +pub struct VECTKEY_W<'a> { + w: &'a mut W, +} +impl<'a> VECTKEY_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xffff << 16)) | ((value as u32 & 0xffff) << 16); + self.w + } +} +impl R { + #[doc = "Bit 1 - Debug: Clear state information"] + #[inline(always)] + pub fn vectclractive(&self) -> VECTCLRACTIVE_R { + VECTCLRACTIVE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - System Reset Request"] + #[inline(always)] + pub fn sysresetreq(&self) -> SYSRESETREQ_R { + SYSRESETREQ_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 15 - Data Endianness, 0=little, 1=big"] + #[inline(always)] + pub fn endianness(&self) -> ENDIANNESS_R { + ENDIANNESS_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:31 - Register key (0x05FA)"] + #[inline(always)] + pub fn vectkey(&self) -> VECTKEY_R { + VECTKEY_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bit 1 - Debug: Clear state information"] + #[inline(always)] + pub fn vectclractive(&mut self) -> VECTCLRACTIVE_W { + VECTCLRACTIVE_W { w: self } + } + #[doc = "Bit 2 - System Reset Request"] + #[inline(always)] + pub fn sysresetreq(&mut self) -> SYSRESETREQ_W { + SYSRESETREQ_W { w: self } + } + #[doc = "Bit 15 - Data Endianness, 0=little, 1=big"] + #[inline(always)] + pub fn endianness(&mut self) -> ENDIANNESS_W { + ENDIANNESS_W { w: self } + } + #[doc = "Bits 16:31 - Register key (0x05FA)"] + #[inline(always)] + pub fn vectkey(&mut self) -> VECTKEY_W { + VECTKEY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Application Interrupt and Reset Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [aircr](index.html) module"] +pub struct AIRCR_SPEC; +impl crate::RegisterSpec for AIRCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [aircr::R](R) reader structure"] +impl crate::Readable for AIRCR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [aircr::W](W) writer structure"] +impl crate::Writable for AIRCR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets AIRCR to value 0"] +impl crate::Resettable for AIRCR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/system_control/ccr.rs b/pac/atsamc21g/src/system_control/ccr.rs new file mode 100644 index 000000000000..62516a7b60c8 --- /dev/null +++ b/pac/atsamc21g/src/system_control/ccr.rs @@ -0,0 +1,137 @@ +#[doc = "Register `CCR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Unaligned accesses generates a Hard Fault\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum UNALIGN_TRP_A { + #[doc = "0: Do not trap unaligned halfword and word accesses"] + VALUE_0 = 0, + #[doc = "1: Trap unaligned halfword and word accesses"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: UNALIGN_TRP_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `UNALIGN_TRP` reader - Unaligned accesses generates a Hard Fault"] +pub struct UNALIGN_TRP_R(crate::FieldReader); +impl UNALIGN_TRP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UNALIGN_TRP_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> UNALIGN_TRP_A { + match self.bits { + false => UNALIGN_TRP_A::VALUE_0, + true => UNALIGN_TRP_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == UNALIGN_TRP_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == UNALIGN_TRP_A::VALUE_1 + } +} +impl core::ops::Deref for UNALIGN_TRP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Stack 8-byte aligned on exception entry\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum STKALIGN_A { + #[doc = "0: 4-byte aligned"] + VALUE_0 = 0, + #[doc = "1: 8-byte aligned"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: STKALIGN_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STKALIGN` reader - Stack 8-byte aligned on exception entry"] +pub struct STKALIGN_R(crate::FieldReader); +impl STKALIGN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STKALIGN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STKALIGN_A { + match self.bits { + false => STKALIGN_A::VALUE_0, + true => STKALIGN_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == STKALIGN_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == STKALIGN_A::VALUE_1 + } +} +impl core::ops::Deref for STKALIGN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 3 - Unaligned accesses generates a Hard Fault"] + #[inline(always)] + pub fn unalign_trp(&self) -> UNALIGN_TRP_R { + UNALIGN_TRP_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 9 - Stack 8-byte aligned on exception entry"] + #[inline(always)] + pub fn stkalign(&self) -> STKALIGN_R { + STKALIGN_R::new(((self.bits >> 9) & 0x01) != 0) + } +} +#[doc = "Configuration and Control Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccr](index.html) module"] +pub struct CCR_SPEC; +impl crate::RegisterSpec for CCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ccr::R](R) reader structure"] +impl crate::Readable for CCR_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CCR to value 0x0204"] +impl crate::Resettable for CCR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0204 + } +} diff --git a/pac/atsamc21g/src/system_control/cpuid.rs b/pac/atsamc21g/src/system_control/cpuid.rs new file mode 100644 index 000000000000..4157d7a94e97 --- /dev/null +++ b/pac/atsamc21g/src/system_control/cpuid.rs @@ -0,0 +1,133 @@ +#[doc = "Register `CPUID` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `REVISION` reader - Minor revision number"] +pub struct REVISION_R(crate::FieldReader); +impl REVISION_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REVISION_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REVISION_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PARTNO` reader - Processor Part Number, 0xC60=Cortex-M0+"] +pub struct PARTNO_R(crate::FieldReader); +impl PARTNO_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + PARTNO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PARTNO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ARCHITECTURE` reader - Processor Architecture, 0xC=ARMv6-M"] +pub struct ARCHITECTURE_R(crate::FieldReader); +impl ARCHITECTURE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ARCHITECTURE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ARCHITECTURE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VARIANT` reader - Major revision number"] +pub struct VARIANT_R(crate::FieldReader); +impl VARIANT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + VARIANT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VARIANT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IMPLEMENTER` reader - Implementer code, ARM=0x41"] +pub struct IMPLEMENTER_R(crate::FieldReader); +impl IMPLEMENTER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + IMPLEMENTER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IMPLEMENTER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:3 - Minor revision number"] + #[inline(always)] + pub fn revision(&self) -> REVISION_R { + REVISION_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:15 - Processor Part Number, 0xC60=Cortex-M0+"] + #[inline(always)] + pub fn partno(&self) -> PARTNO_R { + PARTNO_R::new(((self.bits >> 4) & 0x0fff) as u16) + } + #[doc = "Bits 16:19 - Processor Architecture, 0xC=ARMv6-M"] + #[inline(always)] + pub fn architecture(&self) -> ARCHITECTURE_R { + ARCHITECTURE_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bits 20:23 - Major revision number"] + #[inline(always)] + pub fn variant(&self) -> VARIANT_R { + VARIANT_R::new(((self.bits >> 20) & 0x0f) as u8) + } + #[doc = "Bits 24:31 - Implementer code, ARM=0x41"] + #[inline(always)] + pub fn implementer(&self) -> IMPLEMENTER_R { + IMPLEMENTER_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[doc = "CPUID Base Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cpuid](index.html) module"] +pub struct CPUID_SPEC; +impl crate::RegisterSpec for CPUID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cpuid::R](R) reader structure"] +impl crate::Readable for CPUID_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CPUID to value 0x410c_c601"] +impl crate::Resettable for CPUID_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x410c_c601 + } +} diff --git a/pac/atsamc21g/src/system_control/dfsr.rs b/pac/atsamc21g/src/system_control/dfsr.rs new file mode 100644 index 000000000000..948899af0905 --- /dev/null +++ b/pac/atsamc21g/src/system_control/dfsr.rs @@ -0,0 +1,301 @@ +#[doc = "Register `DFSR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DFSR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `HALTED` reader - Halt request debug event active"] +pub struct HALTED_R(crate::FieldReader); +impl HALTED_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HALTED_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HALTED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HALTED` writer - Halt request debug event active"] +pub struct HALTED_W<'a> { + w: &'a mut W, +} +impl<'a> HALTED_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `BKPT` reader - Breakpoint debug event"] +pub struct BKPT_R(crate::FieldReader); +impl BKPT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BKPT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BKPT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BKPT` writer - Breakpoint debug event"] +pub struct BKPT_W<'a> { + w: &'a mut W, +} +impl<'a> BKPT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `DWTTRAP` reader - DWT debug event"] +pub struct DWTTRAP_R(crate::FieldReader); +impl DWTTRAP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DWTTRAP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DWTTRAP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DWTTRAP` writer - DWT debug event"] +pub struct DWTTRAP_W<'a> { + w: &'a mut W, +} +impl<'a> DWTTRAP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `VCATCH` reader - Vector catch debug event"] +pub struct VCATCH_R(crate::FieldReader); +impl VCATCH_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + VCATCH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VCATCH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VCATCH` writer - Vector catch debug event"] +pub struct VCATCH_W<'a> { + w: &'a mut W, +} +impl<'a> VCATCH_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `EXTERNAL` reader - EDBGRQ debug event"] +pub struct EXTERNAL_R(crate::FieldReader); +impl EXTERNAL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTERNAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTERNAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTERNAL` writer - EDBGRQ debug event"] +pub struct EXTERNAL_W<'a> { + w: &'a mut W, +} +impl<'a> EXTERNAL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +impl R { + #[doc = "Bit 0 - Halt request debug event active"] + #[inline(always)] + pub fn halted(&self) -> HALTED_R { + HALTED_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Breakpoint debug event"] + #[inline(always)] + pub fn bkpt(&self) -> BKPT_R { + BKPT_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - DWT debug event"] + #[inline(always)] + pub fn dwttrap(&self) -> DWTTRAP_R { + DWTTRAP_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Vector catch debug event"] + #[inline(always)] + pub fn vcatch(&self) -> VCATCH_R { + VCATCH_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - EDBGRQ debug event"] + #[inline(always)] + pub fn external(&self) -> EXTERNAL_R { + EXTERNAL_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Halt request debug event active"] + #[inline(always)] + pub fn halted(&mut self) -> HALTED_W { + HALTED_W { w: self } + } + #[doc = "Bit 1 - Breakpoint debug event"] + #[inline(always)] + pub fn bkpt(&mut self) -> BKPT_W { + BKPT_W { w: self } + } + #[doc = "Bit 2 - DWT debug event"] + #[inline(always)] + pub fn dwttrap(&mut self) -> DWTTRAP_W { + DWTTRAP_W { w: self } + } + #[doc = "Bit 3 - Vector catch debug event"] + #[inline(always)] + pub fn vcatch(&mut self) -> VCATCH_W { + VCATCH_W { w: self } + } + #[doc = "Bit 4 - EDBGRQ debug event"] + #[inline(always)] + pub fn external(&mut self) -> EXTERNAL_W { + EXTERNAL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Fault Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dfsr](index.html) module"] +pub struct DFSR_SPEC; +impl crate::RegisterSpec for DFSR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dfsr::R](R) reader structure"] +impl crate::Readable for DFSR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dfsr::W](W) writer structure"] +impl crate::Writable for DFSR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DFSR to value 0"] +impl crate::Resettable for DFSR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/system_control/icsr.rs b/pac/atsamc21g/src/system_control/icsr.rs new file mode 100644 index 000000000000..7fe5fd412116 --- /dev/null +++ b/pac/atsamc21g/src/system_control/icsr.rs @@ -0,0 +1,704 @@ +#[doc = "Register `ICSR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ICSR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `VECTACTIVE` reader - Debug: Exception number of currently executing exception, or 0 if thread mode"] +pub struct VECTACTIVE_R(crate::FieldReader); +impl VECTACTIVE_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + VECTACTIVE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VECTACTIVE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VECTACTIVE` writer - Debug: Exception number of currently executing exception, or 0 if thread mode"] +pub struct VECTACTIVE_W<'a> { + w: &'a mut W, +} +impl<'a> VECTACTIVE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01ff) | (value as u32 & 0x01ff); + self.w + } +} +#[doc = "Field `VECTPENDING` reader - Exception number of the highest priority pending enabled exception"] +pub struct VECTPENDING_R(crate::FieldReader); +impl VECTPENDING_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + VECTPENDING_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VECTPENDING_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VECTPENDING` writer - Exception number of the highest priority pending enabled exception"] +pub struct VECTPENDING_W<'a> { + w: &'a mut W, +} +impl<'a> VECTPENDING_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01ff << 12)) | ((value as u32 & 0x01ff) << 12); + self.w + } +} +#[doc = "Field `ISRPENDING` reader - Debug: NVIC interrupt pending"] +pub struct ISRPENDING_R(crate::FieldReader); +impl ISRPENDING_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ISRPENDING_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ISRPENDING_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ISRPENDING` writer - Debug: NVIC interrupt pending"] +pub struct ISRPENDING_W<'a> { + w: &'a mut W, +} +impl<'a> ISRPENDING_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `ISRPREEMPT` reader - Debug: Pending exception serviced on exit from debug halt"] +pub struct ISRPREEMPT_R(crate::FieldReader); +impl ISRPREEMPT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ISRPREEMPT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ISRPREEMPT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ISRPREEMPT` writer - Debug: Pending exception serviced on exit from debug halt"] +pub struct ISRPREEMPT_W<'a> { + w: &'a mut W, +} +impl<'a> ISRPREEMPT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "SysTick exception clear-pending bit\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PENDSTCLR_A { + #[doc = "0: No effect"] + VALUE_0 = 0, + #[doc = "1: Removes the pending state from the SysTick exception"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PENDSTCLR_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PENDSTCLR` reader - SysTick exception clear-pending bit"] +pub struct PENDSTCLR_R(crate::FieldReader); +impl PENDSTCLR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDSTCLR_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PENDSTCLR_A { + match self.bits { + false => PENDSTCLR_A::VALUE_0, + true => PENDSTCLR_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == PENDSTCLR_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == PENDSTCLR_A::VALUE_1 + } +} +impl core::ops::Deref for PENDSTCLR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDSTCLR` writer - SysTick exception clear-pending bit"] +pub struct PENDSTCLR_W<'a> { + w: &'a mut W, +} +impl<'a> PENDSTCLR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PENDSTCLR_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "No effect"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(PENDSTCLR_A::VALUE_0) + } + #[doc = "Removes the pending state from the SysTick exception"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(PENDSTCLR_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "SysTick exception set-pending bit\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PENDSTSET_A { + #[doc = "0: Write: no effect; read: SysTick exception is not pending"] + VALUE_0 = 0, + #[doc = "1: Write: changes SysTick exception state to pending; read: SysTick exception is pending"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PENDSTSET_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PENDSTSET` reader - SysTick exception set-pending bit"] +pub struct PENDSTSET_R(crate::FieldReader); +impl PENDSTSET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDSTSET_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PENDSTSET_A { + match self.bits { + false => PENDSTSET_A::VALUE_0, + true => PENDSTSET_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == PENDSTSET_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == PENDSTSET_A::VALUE_1 + } +} +impl core::ops::Deref for PENDSTSET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDSTSET` writer - SysTick exception set-pending bit"] +pub struct PENDSTSET_W<'a> { + w: &'a mut W, +} +impl<'a> PENDSTSET_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PENDSTSET_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Write: no effect; read: SysTick exception is not pending"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(PENDSTSET_A::VALUE_0) + } + #[doc = "Write: changes SysTick exception state to pending; read: SysTick exception is pending"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(PENDSTSET_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "PendSV clear-pending bit\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PENDSVCLR_A { + #[doc = "0: No effect"] + VALUE_0 = 0, + #[doc = "1: Removes the pending state from the PendSV exception"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PENDSVCLR_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PENDSVCLR` reader - PendSV clear-pending bit"] +pub struct PENDSVCLR_R(crate::FieldReader); +impl PENDSVCLR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDSVCLR_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PENDSVCLR_A { + match self.bits { + false => PENDSVCLR_A::VALUE_0, + true => PENDSVCLR_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == PENDSVCLR_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == PENDSVCLR_A::VALUE_1 + } +} +impl core::ops::Deref for PENDSVCLR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDSVCLR` writer - PendSV clear-pending bit"] +pub struct PENDSVCLR_W<'a> { + w: &'a mut W, +} +impl<'a> PENDSVCLR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PENDSVCLR_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "No effect"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(PENDSVCLR_A::VALUE_0) + } + #[doc = "Removes the pending state from the PendSV exception"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(PENDSVCLR_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +#[doc = "PendSV set-pending bit\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PENDSVSET_A { + #[doc = "0: Write: no effect; read: PendSV exception is not pending"] + VALUE_0 = 0, + #[doc = "1: Write: changes PendSV exception state to pending; read: PendSV exception is pending"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PENDSVSET_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PENDSVSET` reader - PendSV set-pending bit"] +pub struct PENDSVSET_R(crate::FieldReader); +impl PENDSVSET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDSVSET_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PENDSVSET_A { + match self.bits { + false => PENDSVSET_A::VALUE_0, + true => PENDSVSET_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == PENDSVSET_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == PENDSVSET_A::VALUE_1 + } +} +impl core::ops::Deref for PENDSVSET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDSVSET` writer - PendSV set-pending bit"] +pub struct PENDSVSET_W<'a> { + w: &'a mut W, +} +impl<'a> PENDSVSET_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PENDSVSET_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Write: no effect; read: PendSV exception is not pending"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(PENDSVSET_A::VALUE_0) + } + #[doc = "Write: changes PendSV exception state to pending; read: PendSV exception is pending"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(PENDSVSET_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "NMI set-pending bit\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum NMIPENDSET_A { + #[doc = "0: Write: no effect; read: NMI exception is not pending"] + VALUE_0 = 0, + #[doc = "1: Write: changes NMI exception state to pending; read: NMI exception is pending"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NMIPENDSET_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NMIPENDSET` reader - NMI set-pending bit"] +pub struct NMIPENDSET_R(crate::FieldReader); +impl NMIPENDSET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NMIPENDSET_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> NMIPENDSET_A { + match self.bits { + false => NMIPENDSET_A::VALUE_0, + true => NMIPENDSET_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == NMIPENDSET_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == NMIPENDSET_A::VALUE_1 + } +} +impl core::ops::Deref for NMIPENDSET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NMIPENDSET` writer - NMI set-pending bit"] +pub struct NMIPENDSET_W<'a> { + w: &'a mut W, +} +impl<'a> NMIPENDSET_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: NMIPENDSET_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Write: no effect; read: NMI exception is not pending"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(NMIPENDSET_A::VALUE_0) + } + #[doc = "Write: changes NMI exception state to pending; read: NMI exception is pending"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(NMIPENDSET_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bits 0:8 - Debug: Exception number of currently executing exception, or 0 if thread mode"] + #[inline(always)] + pub fn vectactive(&self) -> VECTACTIVE_R { + VECTACTIVE_R::new((self.bits & 0x01ff) as u16) + } + #[doc = "Bits 12:20 - Exception number of the highest priority pending enabled exception"] + #[inline(always)] + pub fn vectpending(&self) -> VECTPENDING_R { + VECTPENDING_R::new(((self.bits >> 12) & 0x01ff) as u16) + } + #[doc = "Bit 22 - Debug: NVIC interrupt pending"] + #[inline(always)] + pub fn isrpending(&self) -> ISRPENDING_R { + ISRPENDING_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Debug: Pending exception serviced on exit from debug halt"] + #[inline(always)] + pub fn isrpreempt(&self) -> ISRPREEMPT_R { + ISRPREEMPT_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 25 - SysTick exception clear-pending bit"] + #[inline(always)] + pub fn pendstclr(&self) -> PENDSTCLR_R { + PENDSTCLR_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - SysTick exception set-pending bit"] + #[inline(always)] + pub fn pendstset(&self) -> PENDSTSET_R { + PENDSTSET_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - PendSV clear-pending bit"] + #[inline(always)] + pub fn pendsvclr(&self) -> PENDSVCLR_R { + PENDSVCLR_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28 - PendSV set-pending bit"] + #[inline(always)] + pub fn pendsvset(&self) -> PENDSVSET_R { + PENDSVSET_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 31 - NMI set-pending bit"] + #[inline(always)] + pub fn nmipendset(&self) -> NMIPENDSET_R { + NMIPENDSET_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:8 - Debug: Exception number of currently executing exception, or 0 if thread mode"] + #[inline(always)] + pub fn vectactive(&mut self) -> VECTACTIVE_W { + VECTACTIVE_W { w: self } + } + #[doc = "Bits 12:20 - Exception number of the highest priority pending enabled exception"] + #[inline(always)] + pub fn vectpending(&mut self) -> VECTPENDING_W { + VECTPENDING_W { w: self } + } + #[doc = "Bit 22 - Debug: NVIC interrupt pending"] + #[inline(always)] + pub fn isrpending(&mut self) -> ISRPENDING_W { + ISRPENDING_W { w: self } + } + #[doc = "Bit 23 - Debug: Pending exception serviced on exit from debug halt"] + #[inline(always)] + pub fn isrpreempt(&mut self) -> ISRPREEMPT_W { + ISRPREEMPT_W { w: self } + } + #[doc = "Bit 25 - SysTick exception clear-pending bit"] + #[inline(always)] + pub fn pendstclr(&mut self) -> PENDSTCLR_W { + PENDSTCLR_W { w: self } + } + #[doc = "Bit 26 - SysTick exception set-pending bit"] + #[inline(always)] + pub fn pendstset(&mut self) -> PENDSTSET_W { + PENDSTSET_W { w: self } + } + #[doc = "Bit 27 - PendSV clear-pending bit"] + #[inline(always)] + pub fn pendsvclr(&mut self) -> PENDSVCLR_W { + PENDSVCLR_W { w: self } + } + #[doc = "Bit 28 - PendSV set-pending bit"] + #[inline(always)] + pub fn pendsvset(&mut self) -> PENDSVSET_W { + PENDSVSET_W { w: self } + } + #[doc = "Bit 31 - NMI set-pending bit"] + #[inline(always)] + pub fn nmipendset(&mut self) -> NMIPENDSET_W { + NMIPENDSET_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Control and State Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [icsr](index.html) module"] +pub struct ICSR_SPEC; +impl crate::RegisterSpec for ICSR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [icsr::R](R) reader structure"] +impl crate::Readable for ICSR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [icsr::W](W) writer structure"] +impl crate::Writable for ICSR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ICSR to value 0"] +impl crate::Resettable for ICSR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/system_control/scr.rs b/pac/atsamc21g/src/system_control/scr.rs new file mode 100644 index 000000000000..db9c54fe6f6f --- /dev/null +++ b/pac/atsamc21g/src/system_control/scr.rs @@ -0,0 +1,348 @@ +#[doc = "Register `SCR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SCR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Sleep-On-Exit when exiting Handler mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SLEEPONEXIT_A { + #[doc = "0: O not sleep when returning to Thread mode"] + VALUE_0 = 0, + #[doc = "1: Enter sleep, or deep sleep, on return from an ISR"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SLEEPONEXIT_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SLEEPONEXIT` reader - Sleep-On-Exit when exiting Handler mode"] +pub struct SLEEPONEXIT_R(crate::FieldReader); +impl SLEEPONEXIT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLEEPONEXIT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SLEEPONEXIT_A { + match self.bits { + false => SLEEPONEXIT_A::VALUE_0, + true => SLEEPONEXIT_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == SLEEPONEXIT_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == SLEEPONEXIT_A::VALUE_1 + } +} +impl core::ops::Deref for SLEEPONEXIT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLEEPONEXIT` writer - Sleep-On-Exit when exiting Handler mode"] +pub struct SLEEPONEXIT_W<'a> { + w: &'a mut W, +} +impl<'a> SLEEPONEXIT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SLEEPONEXIT_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "O not sleep when returning to Thread mode"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(SLEEPONEXIT_A::VALUE_0) + } + #[doc = "Enter sleep, or deep sleep, on return from an ISR"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(SLEEPONEXIT_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Uses Deep Sleep as low power mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SLEEPDEEP_A { + #[doc = "0: Sleep"] + VALUE_0 = 0, + #[doc = "1: Deep sleep"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SLEEPDEEP_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SLEEPDEEP` reader - Uses Deep Sleep as low power mode"] +pub struct SLEEPDEEP_R(crate::FieldReader); +impl SLEEPDEEP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLEEPDEEP_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SLEEPDEEP_A { + match self.bits { + false => SLEEPDEEP_A::VALUE_0, + true => SLEEPDEEP_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == SLEEPDEEP_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == SLEEPDEEP_A::VALUE_1 + } +} +impl core::ops::Deref for SLEEPDEEP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLEEPDEEP` writer - Uses Deep Sleep as low power mode"] +pub struct SLEEPDEEP_W<'a> { + w: &'a mut W, +} +impl<'a> SLEEPDEEP_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SLEEPDEEP_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Sleep"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(SLEEPDEEP_A::VALUE_0) + } + #[doc = "Deep sleep"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(SLEEPDEEP_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Send Event on Pending bit\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SEVONPEND_A { + #[doc = "0: Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded"] + VALUE_0 = 0, + #[doc = "1: Enabled events and all interrupts, including disabled interrupts, can wakeup the processor"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SEVONPEND_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SEVONPEND` reader - Send Event on Pending bit"] +pub struct SEVONPEND_R(crate::FieldReader); +impl SEVONPEND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SEVONPEND_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SEVONPEND_A { + match self.bits { + false => SEVONPEND_A::VALUE_0, + true => SEVONPEND_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == SEVONPEND_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == SEVONPEND_A::VALUE_1 + } +} +impl core::ops::Deref for SEVONPEND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEVONPEND` writer - Send Event on Pending bit"] +pub struct SEVONPEND_W<'a> { + w: &'a mut W, +} +impl<'a> SEVONPEND_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SEVONPEND_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(SEVONPEND_A::VALUE_0) + } + #[doc = "Enabled events and all interrupts, including disabled interrupts, can wakeup the processor"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(SEVONPEND_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +impl R { + #[doc = "Bit 1 - Sleep-On-Exit when exiting Handler mode"] + #[inline(always)] + pub fn sleeponexit(&self) -> SLEEPONEXIT_R { + SLEEPONEXIT_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Uses Deep Sleep as low power mode"] + #[inline(always)] + pub fn sleepdeep(&self) -> SLEEPDEEP_R { + SLEEPDEEP_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 4 - Send Event on Pending bit"] + #[inline(always)] + pub fn sevonpend(&self) -> SEVONPEND_R { + SEVONPEND_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 1 - Sleep-On-Exit when exiting Handler mode"] + #[inline(always)] + pub fn sleeponexit(&mut self) -> SLEEPONEXIT_W { + SLEEPONEXIT_W { w: self } + } + #[doc = "Bit 2 - Uses Deep Sleep as low power mode"] + #[inline(always)] + pub fn sleepdeep(&mut self) -> SLEEPDEEP_W { + SLEEPDEEP_W { w: self } + } + #[doc = "Bit 4 - Send Event on Pending bit"] + #[inline(always)] + pub fn sevonpend(&mut self) -> SEVONPEND_W { + SEVONPEND_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "System Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [scr](index.html) module"] +pub struct SCR_SPEC; +impl crate::RegisterSpec for SCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [scr::R](R) reader structure"] +impl crate::Readable for SCR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [scr::W](W) writer structure"] +impl crate::Writable for SCR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SCR to value 0"] +impl crate::Resettable for SCR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/system_control/shcsr.rs b/pac/atsamc21g/src/system_control/shcsr.rs new file mode 100644 index 000000000000..bfba26ac06ad --- /dev/null +++ b/pac/atsamc21g/src/system_control/shcsr.rs @@ -0,0 +1,113 @@ +#[doc = "Register `SHCSR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SHCSR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SVCALLPENDED` reader - "] +pub struct SVCALLPENDED_R(crate::FieldReader); +impl SVCALLPENDED_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SVCALLPENDED_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SVCALLPENDED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SVCALLPENDED` writer - "] +pub struct SVCALLPENDED_W<'a> { + w: &'a mut W, +} +impl<'a> SVCALLPENDED_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 15"] + #[inline(always)] + pub fn svcallpended(&self) -> SVCALLPENDED_R { + SVCALLPENDED_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 15"] + #[inline(always)] + pub fn svcallpended(&mut self) -> SVCALLPENDED_W { + SVCALLPENDED_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "System Handler Control and State Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [shcsr](index.html) module"] +pub struct SHCSR_SPEC; +impl crate::RegisterSpec for SHCSR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [shcsr::R](R) reader structure"] +impl crate::Readable for SHCSR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [shcsr::W](W) writer structure"] +impl crate::Writable for SHCSR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SHCSR to value 0"] +impl crate::Resettable for SHCSR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/system_control/shpr2.rs b/pac/atsamc21g/src/system_control/shpr2.rs new file mode 100644 index 000000000000..5665d6a5e8a9 --- /dev/null +++ b/pac/atsamc21g/src/system_control/shpr2.rs @@ -0,0 +1,103 @@ +#[doc = "Register `SHPR2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SHPR2` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PRI_11` reader - Priority of system handler 11, SVCall"] +pub struct PRI_11_R(crate::FieldReader); +impl PRI_11_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRI_11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PRI_11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRI_11` writer - Priority of system handler 11, SVCall"] +pub struct PRI_11_W<'a> { + w: &'a mut W, +} +impl<'a> PRI_11_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 24)) | ((value as u32 & 0xff) << 24); + self.w + } +} +impl R { + #[doc = "Bits 24:31 - Priority of system handler 11, SVCall"] + #[inline(always)] + pub fn pri_11(&self) -> PRI_11_R { + PRI_11_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 24:31 - Priority of system handler 11, SVCall"] + #[inline(always)] + pub fn pri_11(&mut self) -> PRI_11_W { + PRI_11_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "System Handler Priority Register 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [shpr2](index.html) module"] +pub struct SHPR2_SPEC; +impl crate::RegisterSpec for SHPR2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [shpr2::R](R) reader structure"] +impl crate::Readable for SHPR2_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [shpr2::W](W) writer structure"] +impl crate::Writable for SHPR2_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SHPR2 to value 0"] +impl crate::Resettable for SHPR2_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/system_control/shpr3.rs b/pac/atsamc21g/src/system_control/shpr3.rs new file mode 100644 index 000000000000..cb5a92c53503 --- /dev/null +++ b/pac/atsamc21g/src/system_control/shpr3.rs @@ -0,0 +1,140 @@ +#[doc = "Register `SHPR3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SHPR3` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PRI_14` reader - Priority of system handler 14, PendSV"] +pub struct PRI_14_R(crate::FieldReader); +impl PRI_14_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRI_14_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PRI_14_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRI_14` writer - Priority of system handler 14, PendSV"] +pub struct PRI_14_W<'a> { + w: &'a mut W, +} +impl<'a> PRI_14_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +#[doc = "Field `PRI_15` reader - Priority of system handler 15, SysTick exception"] +pub struct PRI_15_R(crate::FieldReader); +impl PRI_15_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRI_15_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PRI_15_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRI_15` writer - Priority of system handler 15, SysTick exception"] +pub struct PRI_15_W<'a> { + w: &'a mut W, +} +impl<'a> PRI_15_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 24)) | ((value as u32 & 0xff) << 24); + self.w + } +} +impl R { + #[doc = "Bits 16:23 - Priority of system handler 14, PendSV"] + #[inline(always)] + pub fn pri_14(&self) -> PRI_14_R { + PRI_14_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Priority of system handler 15, SysTick exception"] + #[inline(always)] + pub fn pri_15(&self) -> PRI_15_R { + PRI_15_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 16:23 - Priority of system handler 14, PendSV"] + #[inline(always)] + pub fn pri_14(&mut self) -> PRI_14_W { + PRI_14_W { w: self } + } + #[doc = "Bits 24:31 - Priority of system handler 15, SysTick exception"] + #[inline(always)] + pub fn pri_15(&mut self) -> PRI_15_W { + PRI_15_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "System Handler Priority Register 3\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [shpr3](index.html) module"] +pub struct SHPR3_SPEC; +impl crate::RegisterSpec for SHPR3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [shpr3::R](R) reader structure"] +impl crate::Readable for SHPR3_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [shpr3::W](W) writer structure"] +impl crate::Writable for SHPR3_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SHPR3 to value 0"] +impl crate::Resettable for SHPR3_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/system_control/vtor.rs b/pac/atsamc21g/src/system_control/vtor.rs new file mode 100644 index 000000000000..0ee4c7817817 --- /dev/null +++ b/pac/atsamc21g/src/system_control/vtor.rs @@ -0,0 +1,103 @@ +#[doc = "Register `VTOR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `VTOR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TBLOFF` reader - Vector table base offset"] +pub struct TBLOFF_R(crate::FieldReader); +impl TBLOFF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + TBLOFF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TBLOFF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TBLOFF` writer - Vector table base offset"] +pub struct TBLOFF_W<'a> { + w: &'a mut W, +} +impl<'a> TBLOFF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01ff_ffff << 7)) | ((value as u32 & 0x01ff_ffff) << 7); + self.w + } +} +impl R { + #[doc = "Bits 7:31 - Vector table base offset"] + #[inline(always)] + pub fn tbloff(&self) -> TBLOFF_R { + TBLOFF_R::new(((self.bits >> 7) & 0x01ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 7:31 - Vector table base offset"] + #[inline(always)] + pub fn tbloff(&mut self) -> TBLOFF_W { + TBLOFF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Vector Table Offset Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [vtor](index.html) module"] +pub struct VTOR_SPEC; +impl crate::RegisterSpec for VTOR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [vtor::R](R) reader structure"] +impl crate::Readable for VTOR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [vtor::W](W) writer structure"] +impl crate::Writable for VTOR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets VTOR to value 0"] +impl crate::Resettable for VTOR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/tc0.rs b/pac/atsamc21g/src/tc0.rs new file mode 100644 index 000000000000..86e973b276e7 --- /dev/null +++ b/pac/atsamc21g/src/tc0.rs @@ -0,0 +1,146 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved_0_count8: [u8; 0x38], +} +impl RegisterBlock { + #[doc = "0x00..0x38 - 32-bit Counter Mode"] + #[inline(always)] + pub fn count32(&self) -> &COUNT32 { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const COUNT32) } + } + #[doc = "0x00..0x34 - 16-bit Counter Mode"] + #[inline(always)] + pub fn count16(&self) -> &COUNT16 { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const COUNT16) } + } + #[doc = "0x00..0x32 - 8-bit Counter Mode"] + #[inline(always)] + pub fn count8(&self) -> &COUNT8 { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const COUNT8) } + } +} +#[doc = r"Register block"] +#[repr(C)] +pub struct COUNT8 { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - Control B Clear"] + pub ctrlbclr: crate::Reg, + #[doc = "0x05 - Control B Set"] + pub ctrlbset: crate::Reg, + #[doc = "0x06 - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x08 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x09 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x0a - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x0b - Status"] + pub status: crate::Reg, + #[doc = "0x0c - Waveform Generation Control"] + pub wave: crate::Reg, + #[doc = "0x0d - Control C"] + pub drvctrl: crate::Reg, + _reserved10: [u8; 0x01], + #[doc = "0x0f - Debug Control"] + pub dbgctrl: crate::Reg, + #[doc = "0x10 - Synchronization Status"] + pub syncbusy: crate::Reg, + #[doc = "0x14 - COUNT8 Count"] + pub count: crate::Reg, + _reserved13: [u8; 0x06], + #[doc = "0x1b - COUNT8 Period"] + pub per: crate::Reg, + #[doc = "0x1c - COUNT8 Compare and Capture"] + pub cc: [crate::Reg; 2], + _reserved15: [u8; 0x11], + #[doc = "0x2f - COUNT8 Period Buffer"] + pub perbuf: crate::Reg, + #[doc = "0x30 - COUNT8 Compare and Capture Buffer"] + pub ccbuf: [crate::Reg; 2], +} +#[doc = r"Register block"] +#[doc = "8-bit Counter Mode"] +pub mod count8; +#[doc = r"Register block"] +#[repr(C)] +pub struct COUNT16 { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - Control B Clear"] + pub ctrlbclr: crate::Reg, + #[doc = "0x05 - Control B Set"] + pub ctrlbset: crate::Reg, + #[doc = "0x06 - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x08 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x09 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x0a - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x0b - Status"] + pub status: crate::Reg, + #[doc = "0x0c - Waveform Generation Control"] + pub wave: crate::Reg, + #[doc = "0x0d - Control C"] + pub drvctrl: crate::Reg, + _reserved10: [u8; 0x01], + #[doc = "0x0f - Debug Control"] + pub dbgctrl: crate::Reg, + #[doc = "0x10 - Synchronization Status"] + pub syncbusy: crate::Reg, + #[doc = "0x14 - COUNT16 Count"] + pub count: crate::Reg, + _reserved13: [u8; 0x06], + #[doc = "0x1c - COUNT16 Compare and Capture"] + pub cc: [crate::Reg; 2], + _reserved14: [u8; 0x10], + #[doc = "0x30 - COUNT16 Compare and Capture Buffer"] + pub ccbuf: [crate::Reg; 2], +} +#[doc = r"Register block"] +#[doc = "16-bit Counter Mode"] +pub mod count16; +#[doc = r"Register block"] +#[repr(C)] +pub struct COUNT32 { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - Control B Clear"] + pub ctrlbclr: crate::Reg, + #[doc = "0x05 - Control B Set"] + pub ctrlbset: crate::Reg, + #[doc = "0x06 - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x08 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x09 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x0a - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x0b - Status"] + pub status: crate::Reg, + #[doc = "0x0c - Waveform Generation Control"] + pub wave: crate::Reg, + #[doc = "0x0d - Control C"] + pub drvctrl: crate::Reg, + _reserved10: [u8; 0x01], + #[doc = "0x0f - Debug Control"] + pub dbgctrl: crate::Reg, + #[doc = "0x10 - Synchronization Status"] + pub syncbusy: crate::Reg, + #[doc = "0x14 - COUNT32 Count"] + pub count: crate::Reg, + _reserved13: [u8; 0x04], + #[doc = "0x1c..0x24 - COUNT32 Compare and Capture"] + pub cc: [crate::Reg; 2], + _reserved14: [u8; 0x0c], + #[doc = "0x30..0x38 - COUNT32 Compare and Capture Buffer"] + pub ccbuf: [crate::Reg; 2], +} +#[doc = r"Register block"] +#[doc = "32-bit Counter Mode"] +pub mod count32; diff --git a/pac/atsamc21g/src/tc0/count16.rs b/pac/atsamc21g/src/tc0/count16.rs new file mode 100644 index 000000000000..5bd1e88c7efb --- /dev/null +++ b/pac/atsamc21g/src/tc0/count16.rs @@ -0,0 +1,60 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "CTRLBCLR register accessor: an alias for `Reg`"] +pub type CTRLBCLR = crate::Reg; +#[doc = "Control B Clear"] +pub mod ctrlbclr; +#[doc = "CTRLBSET register accessor: an alias for `Reg`"] +pub type CTRLBSET = crate::Reg; +#[doc = "Control B Set"] +pub mod ctrlbset; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "WAVE register accessor: an alias for `Reg`"] +pub type WAVE = crate::Reg; +#[doc = "Waveform Generation Control"] +pub mod wave; +#[doc = "DRVCTRL register accessor: an alias for `Reg`"] +pub type DRVCTRL = crate::Reg; +#[doc = "Control C"] +pub mod drvctrl; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Status"] +pub mod syncbusy; +#[doc = "COUNT register accessor: an alias for `Reg`"] +pub type COUNT = crate::Reg; +#[doc = "COUNT16 Count"] +pub mod count; +#[doc = "CC register accessor: an alias for `Reg`"] +pub type CC = crate::Reg; +#[doc = "COUNT16 Compare and Capture"] +pub mod cc; +#[doc = "CCBUF register accessor: an alias for `Reg`"] +pub type CCBUF = crate::Reg; +#[doc = "COUNT16 Compare and Capture Buffer"] +pub mod ccbuf; diff --git a/pac/atsamc21g/src/tc0/count16/cc.rs b/pac/atsamc21g/src/tc0/count16/cc.rs new file mode 100644 index 000000000000..b6f975905e31 --- /dev/null +++ b/pac/atsamc21g/src/tc0/count16/cc.rs @@ -0,0 +1,104 @@ +#[doc = "Register `CC[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CC[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CC` reader - Counter/Compare Value"] +pub struct CC_R(crate::FieldReader); +impl CC_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + CC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC` writer - Counter/Compare Value"] +pub struct CC_W<'a> { + w: &'a mut W, +} +impl<'a> CC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Counter/Compare Value"] + #[inline(always)] + pub fn cc(&self) -> CC_R { + CC_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Counter/Compare Value"] + #[inline(always)] + pub fn cc(&mut self) -> CC_W { + CC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT16 Compare and Capture\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc](index.html) module"] +pub struct CC_SPEC; +impl crate::RegisterSpec for CC_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [cc::R](R) reader structure"] +impl crate::Readable for CC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cc::W](W) writer structure"] +impl crate::Writable for CC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CC[%s] +to value 0"] +impl crate::Resettable for CC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/tc0/count16/ccbuf.rs b/pac/atsamc21g/src/tc0/count16/ccbuf.rs new file mode 100644 index 000000000000..2f922bba8d31 --- /dev/null +++ b/pac/atsamc21g/src/tc0/count16/ccbuf.rs @@ -0,0 +1,104 @@ +#[doc = "Register `CCBUF[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CCBUF[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CCBUF` reader - Counter/Compare Buffer Value"] +pub struct CCBUF_R(crate::FieldReader); +impl CCBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + CCBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUF` writer - Counter/Compare Buffer Value"] +pub struct CCBUF_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Counter/Compare Buffer Value"] + #[inline(always)] + pub fn ccbuf(&self) -> CCBUF_R { + CCBUF_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Counter/Compare Buffer Value"] + #[inline(always)] + pub fn ccbuf(&mut self) -> CCBUF_W { + CCBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT16 Compare and Capture Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccbuf](index.html) module"] +pub struct CCBUF_SPEC; +impl crate::RegisterSpec for CCBUF_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ccbuf::R](R) reader structure"] +impl crate::Readable for CCBUF_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ccbuf::W](W) writer structure"] +impl crate::Writable for CCBUF_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CCBUF[%s] +to value 0"] +impl crate::Resettable for CCBUF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/tc0/count16/count.rs b/pac/atsamc21g/src/tc0/count16/count.rs new file mode 100644 index 000000000000..5d26b509abb1 --- /dev/null +++ b/pac/atsamc21g/src/tc0/count16/count.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT16 Count\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count](index.html) module"] +pub struct COUNT_SPEC; +impl crate::RegisterSpec for COUNT_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [count::R](R) reader structure"] +impl crate::Readable for COUNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count::W](W) writer structure"] +impl crate::Writable for COUNT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT to value 0"] +impl crate::Resettable for COUNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/tc0/count16/ctrla.rs b/pac/atsamc21g/src/tc0/count16/ctrla.rs new file mode 100644 index 000000000000..cadcddaaead8 --- /dev/null +++ b/pac/atsamc21g/src/tc0/count16/ctrla.rs @@ -0,0 +1,851 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Timer Counter Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: Counter in 16-bit mode"] + COUNT16 = 0, + #[doc = "1: Counter in 8-bit mode"] + COUNT8 = 1, + #[doc = "2: Counter in 32-bit mode"] + COUNT32 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Timer Counter Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::COUNT16), + 1 => Some(MODE_A::COUNT8), + 2 => Some(MODE_A::COUNT32), + _ => None, + } + } + #[doc = "Checks if the value of the field is `COUNT16`"] + #[inline(always)] + pub fn is_count16(&self) -> bool { + **self == MODE_A::COUNT16 + } + #[doc = "Checks if the value of the field is `COUNT8`"] + #[inline(always)] + pub fn is_count8(&self) -> bool { + **self == MODE_A::COUNT8 + } + #[doc = "Checks if the value of the field is `COUNT32`"] + #[inline(always)] + pub fn is_count32(&self) -> bool { + **self == MODE_A::COUNT32 + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Timer Counter Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Counter in 16-bit mode"] + #[inline(always)] + pub fn count16(self) -> &'a mut W { + self.variant(MODE_A::COUNT16) + } + #[doc = "Counter in 8-bit mode"] + #[inline(always)] + pub fn count8(self) -> &'a mut W { + self.variant(MODE_A::COUNT8) + } + #[doc = "Counter in 32-bit mode"] + #[inline(always)] + pub fn count32(self) -> &'a mut W { + self.variant(MODE_A::COUNT32) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u32 & 0x03) << 2); + self.w + } +} +#[doc = "Prescaler and Counter Synchronization\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCSYNC_A { + #[doc = "0: Reload or reset the counter on next generic clock"] + GCLK = 0, + #[doc = "1: Reload or reset the counter on next prescaler clock"] + PRESC = 1, + #[doc = "2: Reload or reset the counter on next generic clock and reset the prescaler counter"] + RESYNC = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCSYNC_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCSYNC` reader - Prescaler and Counter Synchronization"] +pub struct PRESCSYNC_R(crate::FieldReader); +impl PRESCSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCSYNC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCSYNC_A::GCLK), + 1 => Some(PRESCSYNC_A::PRESC), + 2 => Some(PRESCSYNC_A::RESYNC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `GCLK`"] + #[inline(always)] + pub fn is_gclk(&self) -> bool { + **self == PRESCSYNC_A::GCLK + } + #[doc = "Checks if the value of the field is `PRESC`"] + #[inline(always)] + pub fn is_presc(&self) -> bool { + **self == PRESCSYNC_A::PRESC + } + #[doc = "Checks if the value of the field is `RESYNC`"] + #[inline(always)] + pub fn is_resync(&self) -> bool { + **self == PRESCSYNC_A::RESYNC + } +} +impl core::ops::Deref for PRESCSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCSYNC` writer - Prescaler and Counter Synchronization"] +pub struct PRESCSYNC_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCSYNC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCSYNC_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Reload or reset the counter on next generic clock"] + #[inline(always)] + pub fn gclk(self) -> &'a mut W { + self.variant(PRESCSYNC_A::GCLK) + } + #[doc = "Reload or reset the counter on next prescaler clock"] + #[inline(always)] + pub fn presc(self) -> &'a mut W { + self.variant(PRESCSYNC_A::PRESC) + } + #[doc = "Reload or reset the counter on next generic clock and reset the prescaler counter"] + #[inline(always)] + pub fn resync(self) -> &'a mut W { + self.variant(PRESCSYNC_A::RESYNC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u32 & 0x03) << 4); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - Clock On Demand"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - Clock On Demand"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: Prescaler: GCLK_TC"] + DIV1 = 0, + #[doc = "1: Prescaler: GCLK_TC/2"] + DIV2 = 1, + #[doc = "2: Prescaler: GCLK_TC/4"] + DIV4 = 2, + #[doc = "3: Prescaler: GCLK_TC/8"] + DIV8 = 3, + #[doc = "4: Prescaler: GCLK_TC/16"] + DIV16 = 4, + #[doc = "5: Prescaler: GCLK_TC/64"] + DIV64 = 5, + #[doc = "6: Prescaler: GCLK_TC/256"] + DIV256 = 6, + #[doc = "7: Prescaler: GCLK_TC/1024"] + DIV1024 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PRESCALER_A { + match self.bits { + 0 => PRESCALER_A::DIV1, + 1 => PRESCALER_A::DIV2, + 2 => PRESCALER_A::DIV4, + 3 => PRESCALER_A::DIV8, + 4 => PRESCALER_A::DIV16, + 5 => PRESCALER_A::DIV64, + 6 => PRESCALER_A::DIV256, + 7 => PRESCALER_A::DIV1024, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == PRESCALER_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PRESCALER_A::DIV1024 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Prescaler: GCLK_TC"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1) + } + #[doc = "Prescaler: GCLK_TC/2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "Prescaler: GCLK_TC/4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "Prescaler: GCLK_TC/8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "Prescaler: GCLK_TC/16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "Prescaler: GCLK_TC/64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "Prescaler: GCLK_TC/256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = "Prescaler: GCLK_TC/1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +#[doc = "Field `ALOCK` reader - Auto Lock"] +pub struct ALOCK_R(crate::FieldReader); +impl ALOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALOCK` writer - Auto Lock"] +pub struct ALOCK_W<'a> { + w: &'a mut W, +} +impl<'a> ALOCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `CAPTEN0` reader - Capture Channel 0 Enable"] +pub struct CAPTEN0_R(crate::FieldReader); +impl CAPTEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CAPTEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CAPTEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAPTEN0` writer - Capture Channel 0 Enable"] +pub struct CAPTEN0_W<'a> { + w: &'a mut W, +} +impl<'a> CAPTEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `CAPTEN1` reader - Capture Channel 1 Enable"] +pub struct CAPTEN1_R(crate::FieldReader); +impl CAPTEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CAPTEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CAPTEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAPTEN1` writer - Capture Channel 1 Enable"] +pub struct CAPTEN1_W<'a> { + w: &'a mut W, +} +impl<'a> CAPTEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `COPEN0` reader - Capture On Pin 0 Enable"] +pub struct COPEN0_R(crate::FieldReader); +impl COPEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COPEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COPEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COPEN0` writer - Capture On Pin 0 Enable"] +pub struct COPEN0_W<'a> { + w: &'a mut W, +} +impl<'a> COPEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `COPEN1` reader - Capture On Pin 1 Enable"] +pub struct COPEN1_R(crate::FieldReader); +impl COPEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COPEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COPEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COPEN1` writer - Capture On Pin 1 Enable"] +pub struct COPEN1_W<'a> { + w: &'a mut W, +} +impl<'a> COPEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:3 - Timer Counter Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bits 4:5 - Prescaler and Counter Synchronization"] + #[inline(always)] + pub fn prescsync(&self) -> PRESCSYNC_R { + PRESCSYNC_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Clock On Demand"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 11 - Auto Lock"] + #[inline(always)] + pub fn alock(&self) -> ALOCK_R { + ALOCK_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 16 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn capten0(&self) -> CAPTEN0_R { + CAPTEN0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn capten1(&self) -> CAPTEN1_R { + CAPTEN1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 20 - Capture On Pin 0 Enable"] + #[inline(always)] + pub fn copen0(&self) -> COPEN0_R { + COPEN0_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Capture On Pin 1 Enable"] + #[inline(always)] + pub fn copen1(&self) -> COPEN1_R { + COPEN1_R::new(((self.bits >> 21) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:3 - Timer Counter Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bits 4:5 - Prescaler and Counter Synchronization"] + #[inline(always)] + pub fn prescsync(&mut self) -> PRESCSYNC_W { + PRESCSYNC_W { w: self } + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - Clock On Demand"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Bit 11 - Auto Lock"] + #[inline(always)] + pub fn alock(&mut self) -> ALOCK_W { + ALOCK_W { w: self } + } + #[doc = "Bit 16 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn capten0(&mut self) -> CAPTEN0_W { + CAPTEN0_W { w: self } + } + #[doc = "Bit 17 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn capten1(&mut self) -> CAPTEN1_W { + CAPTEN1_W { w: self } + } + #[doc = "Bit 20 - Capture On Pin 0 Enable"] + #[inline(always)] + pub fn copen0(&mut self) -> COPEN0_W { + COPEN0_W { w: self } + } + #[doc = "Bit 21 - Capture On Pin 1 Enable"] + #[inline(always)] + pub fn copen1(&mut self) -> COPEN1_W { + COPEN1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/tc0/count16/ctrlbclr.rs b/pac/atsamc21g/src/tc0/count16/ctrlbclr.rs new file mode 100644 index 000000000000..76265674036a --- /dev/null +++ b/pac/atsamc21g/src/tc0/count16/ctrlbclr.rs @@ -0,0 +1,345 @@ +#[doc = "Register `CTRLBCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Counter Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `LUPD` reader - Lock Update"] +pub struct LUPD_R(crate::FieldReader); +impl LUPD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LUPD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LUPD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LUPD` writer - Lock Update"] +pub struct LUPD_W<'a> { + w: &'a mut W, +} +impl<'a> LUPD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ONESHOT` reader - One-Shot on Counter"] +pub struct ONESHOT_R(crate::FieldReader); +impl ONESHOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONESHOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONESHOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONESHOT` writer - One-Shot on Counter"] +pub struct ONESHOT_W<'a> { + w: &'a mut W, +} +impl<'a> ONESHOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Force a start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force a stop"] + STOP = 2, + #[doc = "3: Force update of double-buffered register"] + UPDATE = 3, + #[doc = "4: Force a read synchronization of COUNT"] + READSYNC = 4, + #[doc = "5: One-shot DMA trigger"] + DMAOS = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NONE), + 1 => Some(CMD_A::RETRIGGER), + 2 => Some(CMD_A::STOP), + 3 => Some(CMD_A::UPDATE), + 4 => Some(CMD_A::READSYNC), + 5 => Some(CMD_A::DMAOS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == CMD_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == CMD_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == CMD_A::STOP + } + #[doc = "Checks if the value of the field is `UPDATE`"] + #[inline(always)] + pub fn is_update(&self) -> bool { + **self == CMD_A::UPDATE + } + #[doc = "Checks if the value of the field is `READSYNC`"] + #[inline(always)] + pub fn is_readsync(&self) -> bool { + **self == CMD_A::READSYNC + } + #[doc = "Checks if the value of the field is `DMAOS`"] + #[inline(always)] + pub fn is_dmaos(&self) -> bool { + **self == CMD_A::DMAOS + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMD_A::NONE) + } + #[doc = "Force a start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMD_A::RETRIGGER) + } + #[doc = "Force a stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMD_A::STOP) + } + #[doc = "Force update of double-buffered register"] + #[inline(always)] + pub fn update(self) -> &'a mut W { + self.variant(CMD_A::UPDATE) + } + #[doc = "Force a read synchronization of COUNT"] + #[inline(always)] + pub fn readsync(self) -> &'a mut W { + self.variant(CMD_A::READSYNC) + } + #[doc = "One-shot DMA trigger"] + #[inline(always)] + pub fn dmaos(self) -> &'a mut W { + self.variant(CMD_A::DMAOS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 5)) | ((value as u8 & 0x07) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&self) -> LUPD_R { + LUPD_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 5) & 0x07) as u8) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&mut self) -> LUPD_W { + LUPD_W { w: self } + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&mut self) -> ONESHOT_W { + ONESHOT_W { w: self } + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbclr](index.html) module"] +pub struct CTRLBCLR_SPEC; +impl crate::RegisterSpec for CTRLBCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbclr::R](R) reader structure"] +impl crate::Readable for CTRLBCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbclr::W](W) writer structure"] +impl crate::Writable for CTRLBCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLBCLR to value 0"] +impl crate::Resettable for CTRLBCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/tc0/count16/ctrlbset.rs b/pac/atsamc21g/src/tc0/count16/ctrlbset.rs new file mode 100644 index 000000000000..610914c9c7c8 --- /dev/null +++ b/pac/atsamc21g/src/tc0/count16/ctrlbset.rs @@ -0,0 +1,345 @@ +#[doc = "Register `CTRLBSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Counter Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `LUPD` reader - Lock Update"] +pub struct LUPD_R(crate::FieldReader); +impl LUPD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LUPD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LUPD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LUPD` writer - Lock Update"] +pub struct LUPD_W<'a> { + w: &'a mut W, +} +impl<'a> LUPD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ONESHOT` reader - One-Shot on Counter"] +pub struct ONESHOT_R(crate::FieldReader); +impl ONESHOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONESHOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONESHOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONESHOT` writer - One-Shot on Counter"] +pub struct ONESHOT_W<'a> { + w: &'a mut W, +} +impl<'a> ONESHOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Force a start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force a stop"] + STOP = 2, + #[doc = "3: Force update of double-buffered register"] + UPDATE = 3, + #[doc = "4: Force a read synchronization of COUNT"] + READSYNC = 4, + #[doc = "5: One-shot DMA trigger"] + DMAOS = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NONE), + 1 => Some(CMD_A::RETRIGGER), + 2 => Some(CMD_A::STOP), + 3 => Some(CMD_A::UPDATE), + 4 => Some(CMD_A::READSYNC), + 5 => Some(CMD_A::DMAOS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == CMD_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == CMD_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == CMD_A::STOP + } + #[doc = "Checks if the value of the field is `UPDATE`"] + #[inline(always)] + pub fn is_update(&self) -> bool { + **self == CMD_A::UPDATE + } + #[doc = "Checks if the value of the field is `READSYNC`"] + #[inline(always)] + pub fn is_readsync(&self) -> bool { + **self == CMD_A::READSYNC + } + #[doc = "Checks if the value of the field is `DMAOS`"] + #[inline(always)] + pub fn is_dmaos(&self) -> bool { + **self == CMD_A::DMAOS + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMD_A::NONE) + } + #[doc = "Force a start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMD_A::RETRIGGER) + } + #[doc = "Force a stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMD_A::STOP) + } + #[doc = "Force update of double-buffered register"] + #[inline(always)] + pub fn update(self) -> &'a mut W { + self.variant(CMD_A::UPDATE) + } + #[doc = "Force a read synchronization of COUNT"] + #[inline(always)] + pub fn readsync(self) -> &'a mut W { + self.variant(CMD_A::READSYNC) + } + #[doc = "One-shot DMA trigger"] + #[inline(always)] + pub fn dmaos(self) -> &'a mut W { + self.variant(CMD_A::DMAOS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 5)) | ((value as u8 & 0x07) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&self) -> LUPD_R { + LUPD_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 5) & 0x07) as u8) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&mut self) -> LUPD_W { + LUPD_W { w: self } + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&mut self) -> ONESHOT_W { + ONESHOT_W { w: self } + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbset](index.html) module"] +pub struct CTRLBSET_SPEC; +impl crate::RegisterSpec for CTRLBSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbset::R](R) reader structure"] +impl crate::Readable for CTRLBSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbset::W](W) writer structure"] +impl crate::Writable for CTRLBSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLBSET to value 0"] +impl crate::Resettable for CTRLBSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/tc0/count16/dbgctrl.rs b/pac/atsamc21g/src/tc0/count16/dbgctrl.rs new file mode 100644 index 000000000000..0383e70d0429 --- /dev/null +++ b/pac/atsamc21g/src/tc0/count16/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Run During Debug"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Run During Debug"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/tc0/count16/drvctrl.rs b/pac/atsamc21g/src/tc0/count16/drvctrl.rs new file mode 100644 index 000000000000..323926b4b22d --- /dev/null +++ b/pac/atsamc21g/src/tc0/count16/drvctrl.rs @@ -0,0 +1,160 @@ +#[doc = "Register `DRVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DRVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INVEN0` reader - Output Waveform Invert Enable 0"] +pub struct INVEN0_R(crate::FieldReader); +impl INVEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN0` writer - Output Waveform Invert Enable 0"] +pub struct INVEN0_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `INVEN1` reader - Output Waveform Invert Enable 1"] +pub struct INVEN1_R(crate::FieldReader); +impl INVEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN1` writer - Output Waveform Invert Enable 1"] +pub struct INVEN1_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - Output Waveform Invert Enable 0"] + #[inline(always)] + pub fn inven0(&self) -> INVEN0_R { + INVEN0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Output Waveform Invert Enable 1"] + #[inline(always)] + pub fn inven1(&self) -> INVEN1_R { + INVEN1_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Output Waveform Invert Enable 0"] + #[inline(always)] + pub fn inven0(&mut self) -> INVEN0_W { + INVEN0_W { w: self } + } + #[doc = "Bit 1 - Output Waveform Invert Enable 1"] + #[inline(always)] + pub fn inven1(&mut self) -> INVEN1_W { + INVEN1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control C\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [drvctrl](index.html) module"] +pub struct DRVCTRL_SPEC; +impl crate::RegisterSpec for DRVCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [drvctrl::R](R) reader structure"] +impl crate::Readable for DRVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [drvctrl::W](W) writer structure"] +impl crate::Writable for DRVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DRVCTRL to value 0"] +impl crate::Resettable for DRVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/tc0/count16/evctrl.rs b/pac/atsamc21g/src/tc0/count16/evctrl.rs new file mode 100644 index 000000000000..7d4c38d486c1 --- /dev/null +++ b/pac/atsamc21g/src/tc0/count16/evctrl.rs @@ -0,0 +1,465 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Event Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EVACT_A { + #[doc = "0: Event action disabled"] + OFF = 0, + #[doc = "1: Start, restart or retrigger TC on event"] + RETRIGGER = 1, + #[doc = "2: Count on event"] + COUNT = 2, + #[doc = "3: Start TC on event"] + START = 3, + #[doc = "4: Time stamp capture"] + STAMP = 4, + #[doc = "5: Period catured in CC0, pulse width in CC1"] + PPW = 5, + #[doc = "6: Period catured in CC1, pulse width in CC0"] + PWP = 6, + #[doc = "7: Pulse width capture"] + PW = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EVACT_A) -> Self { + variant as _ + } +} +#[doc = "Field `EVACT` reader - Event Action"] +pub struct EVACT_R(crate::FieldReader); +impl EVACT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVACT_A { + match self.bits { + 0 => EVACT_A::OFF, + 1 => EVACT_A::RETRIGGER, + 2 => EVACT_A::COUNT, + 3 => EVACT_A::START, + 4 => EVACT_A::STAMP, + 5 => EVACT_A::PPW, + 6 => EVACT_A::PWP, + 7 => EVACT_A::PW, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == EVACT_A::OFF + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == EVACT_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `COUNT`"] + #[inline(always)] + pub fn is_count(&self) -> bool { + **self == EVACT_A::COUNT + } + #[doc = "Checks if the value of the field is `START`"] + #[inline(always)] + pub fn is_start(&self) -> bool { + **self == EVACT_A::START + } + #[doc = "Checks if the value of the field is `STAMP`"] + #[inline(always)] + pub fn is_stamp(&self) -> bool { + **self == EVACT_A::STAMP + } + #[doc = "Checks if the value of the field is `PPW`"] + #[inline(always)] + pub fn is_ppw(&self) -> bool { + **self == EVACT_A::PPW + } + #[doc = "Checks if the value of the field is `PWP`"] + #[inline(always)] + pub fn is_pwp(&self) -> bool { + **self == EVACT_A::PWP + } + #[doc = "Checks if the value of the field is `PW`"] + #[inline(always)] + pub fn is_pw(&self) -> bool { + **self == EVACT_A::PW + } +} +impl core::ops::Deref for EVACT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT` writer - Event Action"] +pub struct EVACT_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EVACT_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Event action disabled"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(EVACT_A::OFF) + } + #[doc = "Start, restart or retrigger TC on event"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(EVACT_A::RETRIGGER) + } + #[doc = "Count on event"] + #[inline(always)] + pub fn count(self) -> &'a mut W { + self.variant(EVACT_A::COUNT) + } + #[doc = "Start TC on event"] + #[inline(always)] + pub fn start(self) -> &'a mut W { + self.variant(EVACT_A::START) + } + #[doc = "Time stamp capture"] + #[inline(always)] + pub fn stamp(self) -> &'a mut W { + self.variant(EVACT_A::STAMP) + } + #[doc = "Period catured in CC0, pulse width in CC1"] + #[inline(always)] + pub fn ppw(self) -> &'a mut W { + self.variant(EVACT_A::PPW) + } + #[doc = "Period catured in CC1, pulse width in CC0"] + #[inline(always)] + pub fn pwp(self) -> &'a mut W { + self.variant(EVACT_A::PWP) + } + #[doc = "Pulse width capture"] + #[inline(always)] + pub fn pw(self) -> &'a mut W { + self.variant(EVACT_A::PW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u16 & 0x07); + self.w + } +} +#[doc = "Field `TCINV` reader - TC Event Input Polarity"] +pub struct TCINV_R(crate::FieldReader); +impl TCINV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCINV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCINV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCINV` writer - TC Event Input Polarity"] +pub struct TCINV_W<'a> { + w: &'a mut W, +} +impl<'a> TCINV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `TCEI` reader - TC Event Enable"] +pub struct TCEI_R(crate::FieldReader); +impl TCEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCEI` writer - TC Event Enable"] +pub struct TCEI_W<'a> { + w: &'a mut W, +} +impl<'a> TCEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `OVFEO` reader - Event Output Enable"] +pub struct OVFEO_R(crate::FieldReader); +impl OVFEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVFEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVFEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVFEO` writer - Event Output Enable"] +pub struct OVFEO_W<'a> { + w: &'a mut W, +} +impl<'a> OVFEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `MCEO0` reader - MC Event Output Enable 0"] +pub struct MCEO0_R(crate::FieldReader); +impl MCEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO0` writer - MC Event Output Enable 0"] +pub struct MCEO0_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u16 & 0x01) << 12); + self.w + } +} +#[doc = "Field `MCEO1` reader - MC Event Output Enable 1"] +pub struct MCEO1_R(crate::FieldReader); +impl MCEO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO1` writer - MC Event Output Enable 1"] +pub struct MCEO1_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u16 & 0x01) << 13); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Event Action"] + #[inline(always)] + pub fn evact(&self) -> EVACT_R { + EVACT_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 4 - TC Event Input Polarity"] + #[inline(always)] + pub fn tcinv(&self) -> TCINV_R { + TCINV_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - TC Event Enable"] + #[inline(always)] + pub fn tcei(&self) -> TCEI_R { + TCEI_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 8 - Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&self) -> OVFEO_R { + OVFEO_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 12 - MC Event Output Enable 0"] + #[inline(always)] + pub fn mceo0(&self) -> MCEO0_R { + MCEO0_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - MC Event Output Enable 1"] + #[inline(always)] + pub fn mceo1(&self) -> MCEO1_R { + MCEO1_R::new(((self.bits >> 13) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Event Action"] + #[inline(always)] + pub fn evact(&mut self) -> EVACT_W { + EVACT_W { w: self } + } + #[doc = "Bit 4 - TC Event Input Polarity"] + #[inline(always)] + pub fn tcinv(&mut self) -> TCINV_W { + TCINV_W { w: self } + } + #[doc = "Bit 5 - TC Event Enable"] + #[inline(always)] + pub fn tcei(&mut self) -> TCEI_W { + TCEI_W { w: self } + } + #[doc = "Bit 8 - Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&mut self) -> OVFEO_W { + OVFEO_W { w: self } + } + #[doc = "Bit 12 - MC Event Output Enable 0"] + #[inline(always)] + pub fn mceo0(&mut self) -> MCEO0_W { + MCEO0_W { w: self } + } + #[doc = "Bit 13 - MC Event Output Enable 1"] + #[inline(always)] + pub fn mceo1(&mut self) -> MCEO1_W { + MCEO1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/tc0/count16/intenclr.rs b/pac/atsamc21g/src/tc0/count16/intenclr.rs new file mode 100644 index 000000000000..af01ef5b7dca --- /dev/null +++ b/pac/atsamc21g/src/tc0/count16/intenclr.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - OVF Interrupt Disable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - OVF Interrupt Disable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - ERR Interrupt Disable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - ERR Interrupt Disable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MC0` reader - MC Interrupt Disable 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - MC Interrupt Disable 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - MC Interrupt Disable 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - MC Interrupt Disable 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - OVF Interrupt Disable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ERR Interrupt Disable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - MC Interrupt Disable 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - MC Interrupt Disable 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - OVF Interrupt Disable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - ERR Interrupt Disable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 4 - MC Interrupt Disable 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - MC Interrupt Disable 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/tc0/count16/intenset.rs b/pac/atsamc21g/src/tc0/count16/intenset.rs new file mode 100644 index 000000000000..0e1883a2f20a --- /dev/null +++ b/pac/atsamc21g/src/tc0/count16/intenset.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - OVF Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - OVF Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - ERR Interrupt Enable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - ERR Interrupt Enable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MC0` reader - MC Interrupt Enable 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - MC Interrupt Enable 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - MC Interrupt Enable 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - MC Interrupt Enable 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - OVF Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ERR Interrupt Enable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - MC Interrupt Enable 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - MC Interrupt Enable 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - OVF Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - ERR Interrupt Enable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 4 - MC Interrupt Enable 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - MC Interrupt Enable 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/tc0/count16/intflag.rs b/pac/atsamc21g/src/tc0/count16/intflag.rs new file mode 100644 index 000000000000..1dddffaf8e7f --- /dev/null +++ b/pac/atsamc21g/src/tc0/count16/intflag.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - OVF Interrupt Flag"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - OVF Interrupt Flag"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - ERR Interrupt Flag"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - ERR Interrupt Flag"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MC0` reader - MC Interrupt Flag 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - MC Interrupt Flag 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - MC Interrupt Flag 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - MC Interrupt Flag 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - OVF Interrupt Flag"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ERR Interrupt Flag"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - MC Interrupt Flag 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - MC Interrupt Flag 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - OVF Interrupt Flag"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - ERR Interrupt Flag"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 4 - MC Interrupt Flag 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - MC Interrupt Flag 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/tc0/count16/status.rs b/pac/atsamc21g/src/tc0/count16/status.rs new file mode 100644 index 000000000000..5088af446830 --- /dev/null +++ b/pac/atsamc21g/src/tc0/count16/status.rs @@ -0,0 +1,301 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `STOP` reader - Stop Status Flag"] +pub struct STOP_R(crate::FieldReader); +impl STOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STOP` writer - Stop Status Flag"] +pub struct STOP_W<'a> { + w: &'a mut W, +} +impl<'a> STOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SLAVE` reader - Slave Status Flag"] +pub struct SLAVE_R(crate::FieldReader); +impl SLAVE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLAVE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SLAVE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLAVE` writer - Slave Status Flag"] +pub struct SLAVE_W<'a> { + w: &'a mut W, +} +impl<'a> SLAVE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PERBUFV` reader - Synchronization Busy Status"] +pub struct PERBUFV_R(crate::FieldReader); +impl PERBUFV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PERBUFV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERBUFV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERBUFV` writer - Synchronization Busy Status"] +pub struct PERBUFV_W<'a> { + w: &'a mut W, +} +impl<'a> PERBUFV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CCBUFV0` reader - Compare channel buffer 0 valid"] +pub struct CCBUFV0_R(crate::FieldReader); +impl CCBUFV0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBUFV0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUFV0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUFV0` writer - Compare channel buffer 0 valid"] +pub struct CCBUFV0_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUFV0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `CCBUFV1` reader - Compare channel buffer 1 valid"] +pub struct CCBUFV1_R(crate::FieldReader); +impl CCBUFV1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBUFV1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUFV1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUFV1` writer - Compare channel buffer 1 valid"] +pub struct CCBUFV1_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUFV1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Stop Status Flag"] + #[inline(always)] + pub fn stop(&self) -> STOP_R { + STOP_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Slave Status Flag"] + #[inline(always)] + pub fn slave(&self) -> SLAVE_R { + SLAVE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 3 - Synchronization Busy Status"] + #[inline(always)] + pub fn perbufv(&self) -> PERBUFV_R { + PERBUFV_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Compare channel buffer 0 valid"] + #[inline(always)] + pub fn ccbufv0(&self) -> CCBUFV0_R { + CCBUFV0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Compare channel buffer 1 valid"] + #[inline(always)] + pub fn ccbufv1(&self) -> CCBUFV1_R { + CCBUFV1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Stop Status Flag"] + #[inline(always)] + pub fn stop(&mut self) -> STOP_W { + STOP_W { w: self } + } + #[doc = "Bit 1 - Slave Status Flag"] + #[inline(always)] + pub fn slave(&mut self) -> SLAVE_W { + SLAVE_W { w: self } + } + #[doc = "Bit 3 - Synchronization Busy Status"] + #[inline(always)] + pub fn perbufv(&mut self) -> PERBUFV_W { + PERBUFV_W { w: self } + } + #[doc = "Bit 4 - Compare channel buffer 0 valid"] + #[inline(always)] + pub fn ccbufv0(&mut self) -> CCBUFV0_W { + CCBUFV0_W { w: self } + } + #[doc = "Bit 5 - Compare channel buffer 1 valid"] + #[inline(always)] + pub fn ccbufv1(&mut self) -> CCBUFV1_W { + CCBUFV1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0x01"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pac/atsamc21g/src/tc0/count16/syncbusy.rs b/pac/atsamc21g/src/tc0/count16/syncbusy.rs new file mode 100644 index 000000000000..7ad8d91a84de --- /dev/null +++ b/pac/atsamc21g/src/tc0/count16/syncbusy.rs @@ -0,0 +1,193 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - swrst"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLB` reader - CTRLB"] +pub struct CTRLB_R(crate::FieldReader); +impl CTRLB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STATUS` reader - STATUS"] +pub struct STATUS_R(crate::FieldReader); +impl STATUS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STATUS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STATUS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` reader - Counter"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` reader - Period"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC0` reader - Compare Channel 0"] +pub struct CC0_R(crate::FieldReader); +impl CC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC1` reader - Compare Channel 1"] +pub struct CC1_R(crate::FieldReader); +impl CC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - swrst"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - CTRLB"] + #[inline(always)] + pub fn ctrlb(&self) -> CTRLB_R { + CTRLB_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - STATUS"] + #[inline(always)] + pub fn status(&self) -> STATUS_R { + STATUS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Counter"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Period"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Compare Channel 0"] + #[inline(always)] + pub fn cc0(&self) -> CC0_R { + CC0_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Compare Channel 1"] + #[inline(always)] + pub fn cc1(&self) -> CC1_R { + CC1_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +#[doc = "Synchronization Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/tc0/count16/wave.rs b/pac/atsamc21g/src/tc0/count16/wave.rs new file mode 100644 index 000000000000..46061b24b75d --- /dev/null +++ b/pac/atsamc21g/src/tc0/count16/wave.rs @@ -0,0 +1,178 @@ +#[doc = "Register `WAVE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WAVE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Waveform Generation Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WAVEGEN_A { + #[doc = "0: Normal frequency"] + NFRQ = 0, + #[doc = "1: Match frequency"] + MFRQ = 1, + #[doc = "2: Normal PWM"] + NPWM = 2, + #[doc = "3: Match PWM"] + MPWM = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WAVEGEN_A) -> Self { + variant as _ + } +} +#[doc = "Field `WAVEGEN` reader - Waveform Generation Mode"] +pub struct WAVEGEN_R(crate::FieldReader); +impl WAVEGEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WAVEGEN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> WAVEGEN_A { + match self.bits { + 0 => WAVEGEN_A::NFRQ, + 1 => WAVEGEN_A::MFRQ, + 2 => WAVEGEN_A::NPWM, + 3 => WAVEGEN_A::MPWM, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NFRQ`"] + #[inline(always)] + pub fn is_nfrq(&self) -> bool { + **self == WAVEGEN_A::NFRQ + } + #[doc = "Checks if the value of the field is `MFRQ`"] + #[inline(always)] + pub fn is_mfrq(&self) -> bool { + **self == WAVEGEN_A::MFRQ + } + #[doc = "Checks if the value of the field is `NPWM`"] + #[inline(always)] + pub fn is_npwm(&self) -> bool { + **self == WAVEGEN_A::NPWM + } + #[doc = "Checks if the value of the field is `MPWM`"] + #[inline(always)] + pub fn is_mpwm(&self) -> bool { + **self == WAVEGEN_A::MPWM + } +} +impl core::ops::Deref for WAVEGEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAVEGEN` writer - Waveform Generation Mode"] +pub struct WAVEGEN_W<'a> { + w: &'a mut W, +} +impl<'a> WAVEGEN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WAVEGEN_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Normal frequency"] + #[inline(always)] + pub fn nfrq(self) -> &'a mut W { + self.variant(WAVEGEN_A::NFRQ) + } + #[doc = "Match frequency"] + #[inline(always)] + pub fn mfrq(self) -> &'a mut W { + self.variant(WAVEGEN_A::MFRQ) + } + #[doc = "Normal PWM"] + #[inline(always)] + pub fn npwm(self) -> &'a mut W { + self.variant(WAVEGEN_A::NPWM) + } + #[doc = "Match PWM"] + #[inline(always)] + pub fn mpwm(self) -> &'a mut W { + self.variant(WAVEGEN_A::MPWM) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u8 & 0x03); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Waveform Generation Mode"] + #[inline(always)] + pub fn wavegen(&self) -> WAVEGEN_R { + WAVEGEN_R::new((self.bits & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Waveform Generation Mode"] + #[inline(always)] + pub fn wavegen(&mut self) -> WAVEGEN_W { + WAVEGEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Waveform Generation Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wave](index.html) module"] +pub struct WAVE_SPEC; +impl crate::RegisterSpec for WAVE_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [wave::R](R) reader structure"] +impl crate::Readable for WAVE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wave::W](W) writer structure"] +impl crate::Writable for WAVE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WAVE to value 0"] +impl crate::Resettable for WAVE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/tc0/count32.rs b/pac/atsamc21g/src/tc0/count32.rs new file mode 100644 index 000000000000..9062acfbbd7f --- /dev/null +++ b/pac/atsamc21g/src/tc0/count32.rs @@ -0,0 +1,60 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "CTRLBCLR register accessor: an alias for `Reg`"] +pub type CTRLBCLR = crate::Reg; +#[doc = "Control B Clear"] +pub mod ctrlbclr; +#[doc = "CTRLBSET register accessor: an alias for `Reg`"] +pub type CTRLBSET = crate::Reg; +#[doc = "Control B Set"] +pub mod ctrlbset; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "WAVE register accessor: an alias for `Reg`"] +pub type WAVE = crate::Reg; +#[doc = "Waveform Generation Control"] +pub mod wave; +#[doc = "DRVCTRL register accessor: an alias for `Reg`"] +pub type DRVCTRL = crate::Reg; +#[doc = "Control C"] +pub mod drvctrl; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Status"] +pub mod syncbusy; +#[doc = "COUNT register accessor: an alias for `Reg`"] +pub type COUNT = crate::Reg; +#[doc = "COUNT32 Count"] +pub mod count; +#[doc = "CC register accessor: an alias for `Reg`"] +pub type CC = crate::Reg; +#[doc = "COUNT32 Compare and Capture"] +pub mod cc; +#[doc = "CCBUF register accessor: an alias for `Reg`"] +pub type CCBUF = crate::Reg; +#[doc = "COUNT32 Compare and Capture Buffer"] +pub mod ccbuf; diff --git a/pac/atsamc21g/src/tc0/count32/cc.rs b/pac/atsamc21g/src/tc0/count32/cc.rs new file mode 100644 index 000000000000..512a1e01ffd4 --- /dev/null +++ b/pac/atsamc21g/src/tc0/count32/cc.rs @@ -0,0 +1,104 @@ +#[doc = "Register `CC[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CC[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CC` reader - Counter/Compare Value"] +pub struct CC_R(crate::FieldReader); +impl CC_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC` writer - Counter/Compare Value"] +pub struct CC_W<'a> { + w: &'a mut W, +} +impl<'a> CC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Counter/Compare Value"] + #[inline(always)] + pub fn cc(&self) -> CC_R { + CC_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Counter/Compare Value"] + #[inline(always)] + pub fn cc(&mut self) -> CC_W { + CC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT32 Compare and Capture\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc](index.html) module"] +pub struct CC_SPEC; +impl crate::RegisterSpec for CC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cc::R](R) reader structure"] +impl crate::Readable for CC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cc::W](W) writer structure"] +impl crate::Writable for CC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CC[%s] +to value 0"] +impl crate::Resettable for CC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/tc0/count32/ccbuf.rs b/pac/atsamc21g/src/tc0/count32/ccbuf.rs new file mode 100644 index 000000000000..9fb2d9f8f66c --- /dev/null +++ b/pac/atsamc21g/src/tc0/count32/ccbuf.rs @@ -0,0 +1,104 @@ +#[doc = "Register `CCBUF[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CCBUF[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CCBUF` reader - Counter/Compare Buffer Value"] +pub struct CCBUF_R(crate::FieldReader); +impl CCBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CCBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUF` writer - Counter/Compare Buffer Value"] +pub struct CCBUF_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Counter/Compare Buffer Value"] + #[inline(always)] + pub fn ccbuf(&self) -> CCBUF_R { + CCBUF_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Counter/Compare Buffer Value"] + #[inline(always)] + pub fn ccbuf(&mut self) -> CCBUF_W { + CCBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT32 Compare and Capture Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccbuf](index.html) module"] +pub struct CCBUF_SPEC; +impl crate::RegisterSpec for CCBUF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ccbuf::R](R) reader structure"] +impl crate::Readable for CCBUF_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ccbuf::W](W) writer structure"] +impl crate::Writable for CCBUF_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CCBUF[%s] +to value 0"] +impl crate::Resettable for CCBUF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/tc0/count32/count.rs b/pac/atsamc21g/src/tc0/count32/count.rs new file mode 100644 index 000000000000..9aea527a8b3c --- /dev/null +++ b/pac/atsamc21g/src/tc0/count32/count.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT32 Count\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count](index.html) module"] +pub struct COUNT_SPEC; +impl crate::RegisterSpec for COUNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [count::R](R) reader structure"] +impl crate::Readable for COUNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count::W](W) writer structure"] +impl crate::Writable for COUNT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT to value 0"] +impl crate::Resettable for COUNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/tc0/count32/ctrla.rs b/pac/atsamc21g/src/tc0/count32/ctrla.rs new file mode 100644 index 000000000000..cadcddaaead8 --- /dev/null +++ b/pac/atsamc21g/src/tc0/count32/ctrla.rs @@ -0,0 +1,851 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Timer Counter Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: Counter in 16-bit mode"] + COUNT16 = 0, + #[doc = "1: Counter in 8-bit mode"] + COUNT8 = 1, + #[doc = "2: Counter in 32-bit mode"] + COUNT32 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Timer Counter Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::COUNT16), + 1 => Some(MODE_A::COUNT8), + 2 => Some(MODE_A::COUNT32), + _ => None, + } + } + #[doc = "Checks if the value of the field is `COUNT16`"] + #[inline(always)] + pub fn is_count16(&self) -> bool { + **self == MODE_A::COUNT16 + } + #[doc = "Checks if the value of the field is `COUNT8`"] + #[inline(always)] + pub fn is_count8(&self) -> bool { + **self == MODE_A::COUNT8 + } + #[doc = "Checks if the value of the field is `COUNT32`"] + #[inline(always)] + pub fn is_count32(&self) -> bool { + **self == MODE_A::COUNT32 + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Timer Counter Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Counter in 16-bit mode"] + #[inline(always)] + pub fn count16(self) -> &'a mut W { + self.variant(MODE_A::COUNT16) + } + #[doc = "Counter in 8-bit mode"] + #[inline(always)] + pub fn count8(self) -> &'a mut W { + self.variant(MODE_A::COUNT8) + } + #[doc = "Counter in 32-bit mode"] + #[inline(always)] + pub fn count32(self) -> &'a mut W { + self.variant(MODE_A::COUNT32) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u32 & 0x03) << 2); + self.w + } +} +#[doc = "Prescaler and Counter Synchronization\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCSYNC_A { + #[doc = "0: Reload or reset the counter on next generic clock"] + GCLK = 0, + #[doc = "1: Reload or reset the counter on next prescaler clock"] + PRESC = 1, + #[doc = "2: Reload or reset the counter on next generic clock and reset the prescaler counter"] + RESYNC = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCSYNC_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCSYNC` reader - Prescaler and Counter Synchronization"] +pub struct PRESCSYNC_R(crate::FieldReader); +impl PRESCSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCSYNC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCSYNC_A::GCLK), + 1 => Some(PRESCSYNC_A::PRESC), + 2 => Some(PRESCSYNC_A::RESYNC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `GCLK`"] + #[inline(always)] + pub fn is_gclk(&self) -> bool { + **self == PRESCSYNC_A::GCLK + } + #[doc = "Checks if the value of the field is `PRESC`"] + #[inline(always)] + pub fn is_presc(&self) -> bool { + **self == PRESCSYNC_A::PRESC + } + #[doc = "Checks if the value of the field is `RESYNC`"] + #[inline(always)] + pub fn is_resync(&self) -> bool { + **self == PRESCSYNC_A::RESYNC + } +} +impl core::ops::Deref for PRESCSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCSYNC` writer - Prescaler and Counter Synchronization"] +pub struct PRESCSYNC_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCSYNC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCSYNC_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Reload or reset the counter on next generic clock"] + #[inline(always)] + pub fn gclk(self) -> &'a mut W { + self.variant(PRESCSYNC_A::GCLK) + } + #[doc = "Reload or reset the counter on next prescaler clock"] + #[inline(always)] + pub fn presc(self) -> &'a mut W { + self.variant(PRESCSYNC_A::PRESC) + } + #[doc = "Reload or reset the counter on next generic clock and reset the prescaler counter"] + #[inline(always)] + pub fn resync(self) -> &'a mut W { + self.variant(PRESCSYNC_A::RESYNC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u32 & 0x03) << 4); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - Clock On Demand"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - Clock On Demand"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: Prescaler: GCLK_TC"] + DIV1 = 0, + #[doc = "1: Prescaler: GCLK_TC/2"] + DIV2 = 1, + #[doc = "2: Prescaler: GCLK_TC/4"] + DIV4 = 2, + #[doc = "3: Prescaler: GCLK_TC/8"] + DIV8 = 3, + #[doc = "4: Prescaler: GCLK_TC/16"] + DIV16 = 4, + #[doc = "5: Prescaler: GCLK_TC/64"] + DIV64 = 5, + #[doc = "6: Prescaler: GCLK_TC/256"] + DIV256 = 6, + #[doc = "7: Prescaler: GCLK_TC/1024"] + DIV1024 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PRESCALER_A { + match self.bits { + 0 => PRESCALER_A::DIV1, + 1 => PRESCALER_A::DIV2, + 2 => PRESCALER_A::DIV4, + 3 => PRESCALER_A::DIV8, + 4 => PRESCALER_A::DIV16, + 5 => PRESCALER_A::DIV64, + 6 => PRESCALER_A::DIV256, + 7 => PRESCALER_A::DIV1024, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == PRESCALER_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PRESCALER_A::DIV1024 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Prescaler: GCLK_TC"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1) + } + #[doc = "Prescaler: GCLK_TC/2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "Prescaler: GCLK_TC/4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "Prescaler: GCLK_TC/8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "Prescaler: GCLK_TC/16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "Prescaler: GCLK_TC/64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "Prescaler: GCLK_TC/256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = "Prescaler: GCLK_TC/1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +#[doc = "Field `ALOCK` reader - Auto Lock"] +pub struct ALOCK_R(crate::FieldReader); +impl ALOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALOCK` writer - Auto Lock"] +pub struct ALOCK_W<'a> { + w: &'a mut W, +} +impl<'a> ALOCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `CAPTEN0` reader - Capture Channel 0 Enable"] +pub struct CAPTEN0_R(crate::FieldReader); +impl CAPTEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CAPTEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CAPTEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAPTEN0` writer - Capture Channel 0 Enable"] +pub struct CAPTEN0_W<'a> { + w: &'a mut W, +} +impl<'a> CAPTEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `CAPTEN1` reader - Capture Channel 1 Enable"] +pub struct CAPTEN1_R(crate::FieldReader); +impl CAPTEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CAPTEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CAPTEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAPTEN1` writer - Capture Channel 1 Enable"] +pub struct CAPTEN1_W<'a> { + w: &'a mut W, +} +impl<'a> CAPTEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `COPEN0` reader - Capture On Pin 0 Enable"] +pub struct COPEN0_R(crate::FieldReader); +impl COPEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COPEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COPEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COPEN0` writer - Capture On Pin 0 Enable"] +pub struct COPEN0_W<'a> { + w: &'a mut W, +} +impl<'a> COPEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `COPEN1` reader - Capture On Pin 1 Enable"] +pub struct COPEN1_R(crate::FieldReader); +impl COPEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COPEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COPEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COPEN1` writer - Capture On Pin 1 Enable"] +pub struct COPEN1_W<'a> { + w: &'a mut W, +} +impl<'a> COPEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:3 - Timer Counter Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bits 4:5 - Prescaler and Counter Synchronization"] + #[inline(always)] + pub fn prescsync(&self) -> PRESCSYNC_R { + PRESCSYNC_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Clock On Demand"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 11 - Auto Lock"] + #[inline(always)] + pub fn alock(&self) -> ALOCK_R { + ALOCK_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 16 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn capten0(&self) -> CAPTEN0_R { + CAPTEN0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn capten1(&self) -> CAPTEN1_R { + CAPTEN1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 20 - Capture On Pin 0 Enable"] + #[inline(always)] + pub fn copen0(&self) -> COPEN0_R { + COPEN0_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Capture On Pin 1 Enable"] + #[inline(always)] + pub fn copen1(&self) -> COPEN1_R { + COPEN1_R::new(((self.bits >> 21) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:3 - Timer Counter Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bits 4:5 - Prescaler and Counter Synchronization"] + #[inline(always)] + pub fn prescsync(&mut self) -> PRESCSYNC_W { + PRESCSYNC_W { w: self } + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - Clock On Demand"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Bit 11 - Auto Lock"] + #[inline(always)] + pub fn alock(&mut self) -> ALOCK_W { + ALOCK_W { w: self } + } + #[doc = "Bit 16 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn capten0(&mut self) -> CAPTEN0_W { + CAPTEN0_W { w: self } + } + #[doc = "Bit 17 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn capten1(&mut self) -> CAPTEN1_W { + CAPTEN1_W { w: self } + } + #[doc = "Bit 20 - Capture On Pin 0 Enable"] + #[inline(always)] + pub fn copen0(&mut self) -> COPEN0_W { + COPEN0_W { w: self } + } + #[doc = "Bit 21 - Capture On Pin 1 Enable"] + #[inline(always)] + pub fn copen1(&mut self) -> COPEN1_W { + COPEN1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/tc0/count32/ctrlbclr.rs b/pac/atsamc21g/src/tc0/count32/ctrlbclr.rs new file mode 100644 index 000000000000..76265674036a --- /dev/null +++ b/pac/atsamc21g/src/tc0/count32/ctrlbclr.rs @@ -0,0 +1,345 @@ +#[doc = "Register `CTRLBCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Counter Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `LUPD` reader - Lock Update"] +pub struct LUPD_R(crate::FieldReader); +impl LUPD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LUPD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LUPD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LUPD` writer - Lock Update"] +pub struct LUPD_W<'a> { + w: &'a mut W, +} +impl<'a> LUPD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ONESHOT` reader - One-Shot on Counter"] +pub struct ONESHOT_R(crate::FieldReader); +impl ONESHOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONESHOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONESHOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONESHOT` writer - One-Shot on Counter"] +pub struct ONESHOT_W<'a> { + w: &'a mut W, +} +impl<'a> ONESHOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Force a start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force a stop"] + STOP = 2, + #[doc = "3: Force update of double-buffered register"] + UPDATE = 3, + #[doc = "4: Force a read synchronization of COUNT"] + READSYNC = 4, + #[doc = "5: One-shot DMA trigger"] + DMAOS = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NONE), + 1 => Some(CMD_A::RETRIGGER), + 2 => Some(CMD_A::STOP), + 3 => Some(CMD_A::UPDATE), + 4 => Some(CMD_A::READSYNC), + 5 => Some(CMD_A::DMAOS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == CMD_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == CMD_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == CMD_A::STOP + } + #[doc = "Checks if the value of the field is `UPDATE`"] + #[inline(always)] + pub fn is_update(&self) -> bool { + **self == CMD_A::UPDATE + } + #[doc = "Checks if the value of the field is `READSYNC`"] + #[inline(always)] + pub fn is_readsync(&self) -> bool { + **self == CMD_A::READSYNC + } + #[doc = "Checks if the value of the field is `DMAOS`"] + #[inline(always)] + pub fn is_dmaos(&self) -> bool { + **self == CMD_A::DMAOS + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMD_A::NONE) + } + #[doc = "Force a start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMD_A::RETRIGGER) + } + #[doc = "Force a stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMD_A::STOP) + } + #[doc = "Force update of double-buffered register"] + #[inline(always)] + pub fn update(self) -> &'a mut W { + self.variant(CMD_A::UPDATE) + } + #[doc = "Force a read synchronization of COUNT"] + #[inline(always)] + pub fn readsync(self) -> &'a mut W { + self.variant(CMD_A::READSYNC) + } + #[doc = "One-shot DMA trigger"] + #[inline(always)] + pub fn dmaos(self) -> &'a mut W { + self.variant(CMD_A::DMAOS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 5)) | ((value as u8 & 0x07) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&self) -> LUPD_R { + LUPD_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 5) & 0x07) as u8) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&mut self) -> LUPD_W { + LUPD_W { w: self } + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&mut self) -> ONESHOT_W { + ONESHOT_W { w: self } + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbclr](index.html) module"] +pub struct CTRLBCLR_SPEC; +impl crate::RegisterSpec for CTRLBCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbclr::R](R) reader structure"] +impl crate::Readable for CTRLBCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbclr::W](W) writer structure"] +impl crate::Writable for CTRLBCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLBCLR to value 0"] +impl crate::Resettable for CTRLBCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/tc0/count32/ctrlbset.rs b/pac/atsamc21g/src/tc0/count32/ctrlbset.rs new file mode 100644 index 000000000000..610914c9c7c8 --- /dev/null +++ b/pac/atsamc21g/src/tc0/count32/ctrlbset.rs @@ -0,0 +1,345 @@ +#[doc = "Register `CTRLBSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Counter Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `LUPD` reader - Lock Update"] +pub struct LUPD_R(crate::FieldReader); +impl LUPD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LUPD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LUPD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LUPD` writer - Lock Update"] +pub struct LUPD_W<'a> { + w: &'a mut W, +} +impl<'a> LUPD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ONESHOT` reader - One-Shot on Counter"] +pub struct ONESHOT_R(crate::FieldReader); +impl ONESHOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONESHOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONESHOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONESHOT` writer - One-Shot on Counter"] +pub struct ONESHOT_W<'a> { + w: &'a mut W, +} +impl<'a> ONESHOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Force a start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force a stop"] + STOP = 2, + #[doc = "3: Force update of double-buffered register"] + UPDATE = 3, + #[doc = "4: Force a read synchronization of COUNT"] + READSYNC = 4, + #[doc = "5: One-shot DMA trigger"] + DMAOS = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NONE), + 1 => Some(CMD_A::RETRIGGER), + 2 => Some(CMD_A::STOP), + 3 => Some(CMD_A::UPDATE), + 4 => Some(CMD_A::READSYNC), + 5 => Some(CMD_A::DMAOS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == CMD_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == CMD_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == CMD_A::STOP + } + #[doc = "Checks if the value of the field is `UPDATE`"] + #[inline(always)] + pub fn is_update(&self) -> bool { + **self == CMD_A::UPDATE + } + #[doc = "Checks if the value of the field is `READSYNC`"] + #[inline(always)] + pub fn is_readsync(&self) -> bool { + **self == CMD_A::READSYNC + } + #[doc = "Checks if the value of the field is `DMAOS`"] + #[inline(always)] + pub fn is_dmaos(&self) -> bool { + **self == CMD_A::DMAOS + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMD_A::NONE) + } + #[doc = "Force a start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMD_A::RETRIGGER) + } + #[doc = "Force a stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMD_A::STOP) + } + #[doc = "Force update of double-buffered register"] + #[inline(always)] + pub fn update(self) -> &'a mut W { + self.variant(CMD_A::UPDATE) + } + #[doc = "Force a read synchronization of COUNT"] + #[inline(always)] + pub fn readsync(self) -> &'a mut W { + self.variant(CMD_A::READSYNC) + } + #[doc = "One-shot DMA trigger"] + #[inline(always)] + pub fn dmaos(self) -> &'a mut W { + self.variant(CMD_A::DMAOS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 5)) | ((value as u8 & 0x07) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&self) -> LUPD_R { + LUPD_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 5) & 0x07) as u8) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&mut self) -> LUPD_W { + LUPD_W { w: self } + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&mut self) -> ONESHOT_W { + ONESHOT_W { w: self } + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbset](index.html) module"] +pub struct CTRLBSET_SPEC; +impl crate::RegisterSpec for CTRLBSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbset::R](R) reader structure"] +impl crate::Readable for CTRLBSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbset::W](W) writer structure"] +impl crate::Writable for CTRLBSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLBSET to value 0"] +impl crate::Resettable for CTRLBSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/tc0/count32/dbgctrl.rs b/pac/atsamc21g/src/tc0/count32/dbgctrl.rs new file mode 100644 index 000000000000..0383e70d0429 --- /dev/null +++ b/pac/atsamc21g/src/tc0/count32/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Run During Debug"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Run During Debug"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/tc0/count32/drvctrl.rs b/pac/atsamc21g/src/tc0/count32/drvctrl.rs new file mode 100644 index 000000000000..323926b4b22d --- /dev/null +++ b/pac/atsamc21g/src/tc0/count32/drvctrl.rs @@ -0,0 +1,160 @@ +#[doc = "Register `DRVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DRVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INVEN0` reader - Output Waveform Invert Enable 0"] +pub struct INVEN0_R(crate::FieldReader); +impl INVEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN0` writer - Output Waveform Invert Enable 0"] +pub struct INVEN0_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `INVEN1` reader - Output Waveform Invert Enable 1"] +pub struct INVEN1_R(crate::FieldReader); +impl INVEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN1` writer - Output Waveform Invert Enable 1"] +pub struct INVEN1_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - Output Waveform Invert Enable 0"] + #[inline(always)] + pub fn inven0(&self) -> INVEN0_R { + INVEN0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Output Waveform Invert Enable 1"] + #[inline(always)] + pub fn inven1(&self) -> INVEN1_R { + INVEN1_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Output Waveform Invert Enable 0"] + #[inline(always)] + pub fn inven0(&mut self) -> INVEN0_W { + INVEN0_W { w: self } + } + #[doc = "Bit 1 - Output Waveform Invert Enable 1"] + #[inline(always)] + pub fn inven1(&mut self) -> INVEN1_W { + INVEN1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control C\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [drvctrl](index.html) module"] +pub struct DRVCTRL_SPEC; +impl crate::RegisterSpec for DRVCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [drvctrl::R](R) reader structure"] +impl crate::Readable for DRVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [drvctrl::W](W) writer structure"] +impl crate::Writable for DRVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DRVCTRL to value 0"] +impl crate::Resettable for DRVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/tc0/count32/evctrl.rs b/pac/atsamc21g/src/tc0/count32/evctrl.rs new file mode 100644 index 000000000000..7d4c38d486c1 --- /dev/null +++ b/pac/atsamc21g/src/tc0/count32/evctrl.rs @@ -0,0 +1,465 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Event Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EVACT_A { + #[doc = "0: Event action disabled"] + OFF = 0, + #[doc = "1: Start, restart or retrigger TC on event"] + RETRIGGER = 1, + #[doc = "2: Count on event"] + COUNT = 2, + #[doc = "3: Start TC on event"] + START = 3, + #[doc = "4: Time stamp capture"] + STAMP = 4, + #[doc = "5: Period catured in CC0, pulse width in CC1"] + PPW = 5, + #[doc = "6: Period catured in CC1, pulse width in CC0"] + PWP = 6, + #[doc = "7: Pulse width capture"] + PW = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EVACT_A) -> Self { + variant as _ + } +} +#[doc = "Field `EVACT` reader - Event Action"] +pub struct EVACT_R(crate::FieldReader); +impl EVACT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVACT_A { + match self.bits { + 0 => EVACT_A::OFF, + 1 => EVACT_A::RETRIGGER, + 2 => EVACT_A::COUNT, + 3 => EVACT_A::START, + 4 => EVACT_A::STAMP, + 5 => EVACT_A::PPW, + 6 => EVACT_A::PWP, + 7 => EVACT_A::PW, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == EVACT_A::OFF + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == EVACT_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `COUNT`"] + #[inline(always)] + pub fn is_count(&self) -> bool { + **self == EVACT_A::COUNT + } + #[doc = "Checks if the value of the field is `START`"] + #[inline(always)] + pub fn is_start(&self) -> bool { + **self == EVACT_A::START + } + #[doc = "Checks if the value of the field is `STAMP`"] + #[inline(always)] + pub fn is_stamp(&self) -> bool { + **self == EVACT_A::STAMP + } + #[doc = "Checks if the value of the field is `PPW`"] + #[inline(always)] + pub fn is_ppw(&self) -> bool { + **self == EVACT_A::PPW + } + #[doc = "Checks if the value of the field is `PWP`"] + #[inline(always)] + pub fn is_pwp(&self) -> bool { + **self == EVACT_A::PWP + } + #[doc = "Checks if the value of the field is `PW`"] + #[inline(always)] + pub fn is_pw(&self) -> bool { + **self == EVACT_A::PW + } +} +impl core::ops::Deref for EVACT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT` writer - Event Action"] +pub struct EVACT_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EVACT_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Event action disabled"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(EVACT_A::OFF) + } + #[doc = "Start, restart or retrigger TC on event"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(EVACT_A::RETRIGGER) + } + #[doc = "Count on event"] + #[inline(always)] + pub fn count(self) -> &'a mut W { + self.variant(EVACT_A::COUNT) + } + #[doc = "Start TC on event"] + #[inline(always)] + pub fn start(self) -> &'a mut W { + self.variant(EVACT_A::START) + } + #[doc = "Time stamp capture"] + #[inline(always)] + pub fn stamp(self) -> &'a mut W { + self.variant(EVACT_A::STAMP) + } + #[doc = "Period catured in CC0, pulse width in CC1"] + #[inline(always)] + pub fn ppw(self) -> &'a mut W { + self.variant(EVACT_A::PPW) + } + #[doc = "Period catured in CC1, pulse width in CC0"] + #[inline(always)] + pub fn pwp(self) -> &'a mut W { + self.variant(EVACT_A::PWP) + } + #[doc = "Pulse width capture"] + #[inline(always)] + pub fn pw(self) -> &'a mut W { + self.variant(EVACT_A::PW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u16 & 0x07); + self.w + } +} +#[doc = "Field `TCINV` reader - TC Event Input Polarity"] +pub struct TCINV_R(crate::FieldReader); +impl TCINV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCINV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCINV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCINV` writer - TC Event Input Polarity"] +pub struct TCINV_W<'a> { + w: &'a mut W, +} +impl<'a> TCINV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `TCEI` reader - TC Event Enable"] +pub struct TCEI_R(crate::FieldReader); +impl TCEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCEI` writer - TC Event Enable"] +pub struct TCEI_W<'a> { + w: &'a mut W, +} +impl<'a> TCEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `OVFEO` reader - Event Output Enable"] +pub struct OVFEO_R(crate::FieldReader); +impl OVFEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVFEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVFEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVFEO` writer - Event Output Enable"] +pub struct OVFEO_W<'a> { + w: &'a mut W, +} +impl<'a> OVFEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `MCEO0` reader - MC Event Output Enable 0"] +pub struct MCEO0_R(crate::FieldReader); +impl MCEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO0` writer - MC Event Output Enable 0"] +pub struct MCEO0_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u16 & 0x01) << 12); + self.w + } +} +#[doc = "Field `MCEO1` reader - MC Event Output Enable 1"] +pub struct MCEO1_R(crate::FieldReader); +impl MCEO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO1` writer - MC Event Output Enable 1"] +pub struct MCEO1_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u16 & 0x01) << 13); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Event Action"] + #[inline(always)] + pub fn evact(&self) -> EVACT_R { + EVACT_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 4 - TC Event Input Polarity"] + #[inline(always)] + pub fn tcinv(&self) -> TCINV_R { + TCINV_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - TC Event Enable"] + #[inline(always)] + pub fn tcei(&self) -> TCEI_R { + TCEI_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 8 - Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&self) -> OVFEO_R { + OVFEO_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 12 - MC Event Output Enable 0"] + #[inline(always)] + pub fn mceo0(&self) -> MCEO0_R { + MCEO0_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - MC Event Output Enable 1"] + #[inline(always)] + pub fn mceo1(&self) -> MCEO1_R { + MCEO1_R::new(((self.bits >> 13) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Event Action"] + #[inline(always)] + pub fn evact(&mut self) -> EVACT_W { + EVACT_W { w: self } + } + #[doc = "Bit 4 - TC Event Input Polarity"] + #[inline(always)] + pub fn tcinv(&mut self) -> TCINV_W { + TCINV_W { w: self } + } + #[doc = "Bit 5 - TC Event Enable"] + #[inline(always)] + pub fn tcei(&mut self) -> TCEI_W { + TCEI_W { w: self } + } + #[doc = "Bit 8 - Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&mut self) -> OVFEO_W { + OVFEO_W { w: self } + } + #[doc = "Bit 12 - MC Event Output Enable 0"] + #[inline(always)] + pub fn mceo0(&mut self) -> MCEO0_W { + MCEO0_W { w: self } + } + #[doc = "Bit 13 - MC Event Output Enable 1"] + #[inline(always)] + pub fn mceo1(&mut self) -> MCEO1_W { + MCEO1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/tc0/count32/intenclr.rs b/pac/atsamc21g/src/tc0/count32/intenclr.rs new file mode 100644 index 000000000000..af01ef5b7dca --- /dev/null +++ b/pac/atsamc21g/src/tc0/count32/intenclr.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - OVF Interrupt Disable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - OVF Interrupt Disable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - ERR Interrupt Disable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - ERR Interrupt Disable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MC0` reader - MC Interrupt Disable 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - MC Interrupt Disable 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - MC Interrupt Disable 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - MC Interrupt Disable 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - OVF Interrupt Disable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ERR Interrupt Disable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - MC Interrupt Disable 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - MC Interrupt Disable 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - OVF Interrupt Disable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - ERR Interrupt Disable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 4 - MC Interrupt Disable 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - MC Interrupt Disable 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/tc0/count32/intenset.rs b/pac/atsamc21g/src/tc0/count32/intenset.rs new file mode 100644 index 000000000000..0e1883a2f20a --- /dev/null +++ b/pac/atsamc21g/src/tc0/count32/intenset.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - OVF Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - OVF Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - ERR Interrupt Enable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - ERR Interrupt Enable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MC0` reader - MC Interrupt Enable 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - MC Interrupt Enable 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - MC Interrupt Enable 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - MC Interrupt Enable 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - OVF Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ERR Interrupt Enable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - MC Interrupt Enable 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - MC Interrupt Enable 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - OVF Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - ERR Interrupt Enable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 4 - MC Interrupt Enable 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - MC Interrupt Enable 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/tc0/count32/intflag.rs b/pac/atsamc21g/src/tc0/count32/intflag.rs new file mode 100644 index 000000000000..1dddffaf8e7f --- /dev/null +++ b/pac/atsamc21g/src/tc0/count32/intflag.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - OVF Interrupt Flag"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - OVF Interrupt Flag"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - ERR Interrupt Flag"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - ERR Interrupt Flag"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MC0` reader - MC Interrupt Flag 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - MC Interrupt Flag 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - MC Interrupt Flag 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - MC Interrupt Flag 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - OVF Interrupt Flag"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ERR Interrupt Flag"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - MC Interrupt Flag 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - MC Interrupt Flag 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - OVF Interrupt Flag"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - ERR Interrupt Flag"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 4 - MC Interrupt Flag 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - MC Interrupt Flag 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/tc0/count32/status.rs b/pac/atsamc21g/src/tc0/count32/status.rs new file mode 100644 index 000000000000..5088af446830 --- /dev/null +++ b/pac/atsamc21g/src/tc0/count32/status.rs @@ -0,0 +1,301 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `STOP` reader - Stop Status Flag"] +pub struct STOP_R(crate::FieldReader); +impl STOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STOP` writer - Stop Status Flag"] +pub struct STOP_W<'a> { + w: &'a mut W, +} +impl<'a> STOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SLAVE` reader - Slave Status Flag"] +pub struct SLAVE_R(crate::FieldReader); +impl SLAVE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLAVE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SLAVE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLAVE` writer - Slave Status Flag"] +pub struct SLAVE_W<'a> { + w: &'a mut W, +} +impl<'a> SLAVE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PERBUFV` reader - Synchronization Busy Status"] +pub struct PERBUFV_R(crate::FieldReader); +impl PERBUFV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PERBUFV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERBUFV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERBUFV` writer - Synchronization Busy Status"] +pub struct PERBUFV_W<'a> { + w: &'a mut W, +} +impl<'a> PERBUFV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CCBUFV0` reader - Compare channel buffer 0 valid"] +pub struct CCBUFV0_R(crate::FieldReader); +impl CCBUFV0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBUFV0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUFV0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUFV0` writer - Compare channel buffer 0 valid"] +pub struct CCBUFV0_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUFV0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `CCBUFV1` reader - Compare channel buffer 1 valid"] +pub struct CCBUFV1_R(crate::FieldReader); +impl CCBUFV1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBUFV1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUFV1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUFV1` writer - Compare channel buffer 1 valid"] +pub struct CCBUFV1_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUFV1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Stop Status Flag"] + #[inline(always)] + pub fn stop(&self) -> STOP_R { + STOP_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Slave Status Flag"] + #[inline(always)] + pub fn slave(&self) -> SLAVE_R { + SLAVE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 3 - Synchronization Busy Status"] + #[inline(always)] + pub fn perbufv(&self) -> PERBUFV_R { + PERBUFV_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Compare channel buffer 0 valid"] + #[inline(always)] + pub fn ccbufv0(&self) -> CCBUFV0_R { + CCBUFV0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Compare channel buffer 1 valid"] + #[inline(always)] + pub fn ccbufv1(&self) -> CCBUFV1_R { + CCBUFV1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Stop Status Flag"] + #[inline(always)] + pub fn stop(&mut self) -> STOP_W { + STOP_W { w: self } + } + #[doc = "Bit 1 - Slave Status Flag"] + #[inline(always)] + pub fn slave(&mut self) -> SLAVE_W { + SLAVE_W { w: self } + } + #[doc = "Bit 3 - Synchronization Busy Status"] + #[inline(always)] + pub fn perbufv(&mut self) -> PERBUFV_W { + PERBUFV_W { w: self } + } + #[doc = "Bit 4 - Compare channel buffer 0 valid"] + #[inline(always)] + pub fn ccbufv0(&mut self) -> CCBUFV0_W { + CCBUFV0_W { w: self } + } + #[doc = "Bit 5 - Compare channel buffer 1 valid"] + #[inline(always)] + pub fn ccbufv1(&mut self) -> CCBUFV1_W { + CCBUFV1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0x01"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pac/atsamc21g/src/tc0/count32/syncbusy.rs b/pac/atsamc21g/src/tc0/count32/syncbusy.rs new file mode 100644 index 000000000000..7ad8d91a84de --- /dev/null +++ b/pac/atsamc21g/src/tc0/count32/syncbusy.rs @@ -0,0 +1,193 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - swrst"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLB` reader - CTRLB"] +pub struct CTRLB_R(crate::FieldReader); +impl CTRLB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STATUS` reader - STATUS"] +pub struct STATUS_R(crate::FieldReader); +impl STATUS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STATUS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STATUS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` reader - Counter"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` reader - Period"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC0` reader - Compare Channel 0"] +pub struct CC0_R(crate::FieldReader); +impl CC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC1` reader - Compare Channel 1"] +pub struct CC1_R(crate::FieldReader); +impl CC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - swrst"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - CTRLB"] + #[inline(always)] + pub fn ctrlb(&self) -> CTRLB_R { + CTRLB_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - STATUS"] + #[inline(always)] + pub fn status(&self) -> STATUS_R { + STATUS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Counter"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Period"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Compare Channel 0"] + #[inline(always)] + pub fn cc0(&self) -> CC0_R { + CC0_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Compare Channel 1"] + #[inline(always)] + pub fn cc1(&self) -> CC1_R { + CC1_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +#[doc = "Synchronization Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/tc0/count32/wave.rs b/pac/atsamc21g/src/tc0/count32/wave.rs new file mode 100644 index 000000000000..46061b24b75d --- /dev/null +++ b/pac/atsamc21g/src/tc0/count32/wave.rs @@ -0,0 +1,178 @@ +#[doc = "Register `WAVE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WAVE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Waveform Generation Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WAVEGEN_A { + #[doc = "0: Normal frequency"] + NFRQ = 0, + #[doc = "1: Match frequency"] + MFRQ = 1, + #[doc = "2: Normal PWM"] + NPWM = 2, + #[doc = "3: Match PWM"] + MPWM = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WAVEGEN_A) -> Self { + variant as _ + } +} +#[doc = "Field `WAVEGEN` reader - Waveform Generation Mode"] +pub struct WAVEGEN_R(crate::FieldReader); +impl WAVEGEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WAVEGEN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> WAVEGEN_A { + match self.bits { + 0 => WAVEGEN_A::NFRQ, + 1 => WAVEGEN_A::MFRQ, + 2 => WAVEGEN_A::NPWM, + 3 => WAVEGEN_A::MPWM, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NFRQ`"] + #[inline(always)] + pub fn is_nfrq(&self) -> bool { + **self == WAVEGEN_A::NFRQ + } + #[doc = "Checks if the value of the field is `MFRQ`"] + #[inline(always)] + pub fn is_mfrq(&self) -> bool { + **self == WAVEGEN_A::MFRQ + } + #[doc = "Checks if the value of the field is `NPWM`"] + #[inline(always)] + pub fn is_npwm(&self) -> bool { + **self == WAVEGEN_A::NPWM + } + #[doc = "Checks if the value of the field is `MPWM`"] + #[inline(always)] + pub fn is_mpwm(&self) -> bool { + **self == WAVEGEN_A::MPWM + } +} +impl core::ops::Deref for WAVEGEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAVEGEN` writer - Waveform Generation Mode"] +pub struct WAVEGEN_W<'a> { + w: &'a mut W, +} +impl<'a> WAVEGEN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WAVEGEN_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Normal frequency"] + #[inline(always)] + pub fn nfrq(self) -> &'a mut W { + self.variant(WAVEGEN_A::NFRQ) + } + #[doc = "Match frequency"] + #[inline(always)] + pub fn mfrq(self) -> &'a mut W { + self.variant(WAVEGEN_A::MFRQ) + } + #[doc = "Normal PWM"] + #[inline(always)] + pub fn npwm(self) -> &'a mut W { + self.variant(WAVEGEN_A::NPWM) + } + #[doc = "Match PWM"] + #[inline(always)] + pub fn mpwm(self) -> &'a mut W { + self.variant(WAVEGEN_A::MPWM) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u8 & 0x03); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Waveform Generation Mode"] + #[inline(always)] + pub fn wavegen(&self) -> WAVEGEN_R { + WAVEGEN_R::new((self.bits & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Waveform Generation Mode"] + #[inline(always)] + pub fn wavegen(&mut self) -> WAVEGEN_W { + WAVEGEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Waveform Generation Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wave](index.html) module"] +pub struct WAVE_SPEC; +impl crate::RegisterSpec for WAVE_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [wave::R](R) reader structure"] +impl crate::Readable for WAVE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wave::W](W) writer structure"] +impl crate::Writable for WAVE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WAVE to value 0"] +impl crate::Resettable for WAVE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/tc0/count8.rs b/pac/atsamc21g/src/tc0/count8.rs new file mode 100644 index 000000000000..777da5744358 --- /dev/null +++ b/pac/atsamc21g/src/tc0/count8.rs @@ -0,0 +1,68 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "CTRLBCLR register accessor: an alias for `Reg`"] +pub type CTRLBCLR = crate::Reg; +#[doc = "Control B Clear"] +pub mod ctrlbclr; +#[doc = "CTRLBSET register accessor: an alias for `Reg`"] +pub type CTRLBSET = crate::Reg; +#[doc = "Control B Set"] +pub mod ctrlbset; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "WAVE register accessor: an alias for `Reg`"] +pub type WAVE = crate::Reg; +#[doc = "Waveform Generation Control"] +pub mod wave; +#[doc = "DRVCTRL register accessor: an alias for `Reg`"] +pub type DRVCTRL = crate::Reg; +#[doc = "Control C"] +pub mod drvctrl; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Status"] +pub mod syncbusy; +#[doc = "COUNT register accessor: an alias for `Reg`"] +pub type COUNT = crate::Reg; +#[doc = "COUNT8 Count"] +pub mod count; +#[doc = "PER register accessor: an alias for `Reg`"] +pub type PER = crate::Reg; +#[doc = "COUNT8 Period"] +pub mod per; +#[doc = "CC register accessor: an alias for `Reg`"] +pub type CC = crate::Reg; +#[doc = "COUNT8 Compare and Capture"] +pub mod cc; +#[doc = "PERBUF register accessor: an alias for `Reg`"] +pub type PERBUF = crate::Reg; +#[doc = "COUNT8 Period Buffer"] +pub mod perbuf; +#[doc = "CCBUF register accessor: an alias for `Reg`"] +pub type CCBUF = crate::Reg; +#[doc = "COUNT8 Compare and Capture Buffer"] +pub mod ccbuf; diff --git a/pac/atsamc21g/src/tc0/count8/cc.rs b/pac/atsamc21g/src/tc0/count8/cc.rs new file mode 100644 index 000000000000..45f5c29c89af --- /dev/null +++ b/pac/atsamc21g/src/tc0/count8/cc.rs @@ -0,0 +1,104 @@ +#[doc = "Register `CC[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CC[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CC` reader - Counter/Compare Value"] +pub struct CC_R(crate::FieldReader); +impl CC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC` writer - Counter/Compare Value"] +pub struct CC_W<'a> { + w: &'a mut W, +} +impl<'a> CC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Counter/Compare Value"] + #[inline(always)] + pub fn cc(&self) -> CC_R { + CC_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Counter/Compare Value"] + #[inline(always)] + pub fn cc(&mut self) -> CC_W { + CC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT8 Compare and Capture\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc](index.html) module"] +pub struct CC_SPEC; +impl crate::RegisterSpec for CC_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [cc::R](R) reader structure"] +impl crate::Readable for CC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cc::W](W) writer structure"] +impl crate::Writable for CC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CC[%s] +to value 0"] +impl crate::Resettable for CC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/tc0/count8/ccbuf.rs b/pac/atsamc21g/src/tc0/count8/ccbuf.rs new file mode 100644 index 000000000000..cd81b1219860 --- /dev/null +++ b/pac/atsamc21g/src/tc0/count8/ccbuf.rs @@ -0,0 +1,104 @@ +#[doc = "Register `CCBUF[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CCBUF[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CCBUF` reader - Counter/Compare Buffer Value"] +pub struct CCBUF_R(crate::FieldReader); +impl CCBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CCBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUF` writer - Counter/Compare Buffer Value"] +pub struct CCBUF_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Counter/Compare Buffer Value"] + #[inline(always)] + pub fn ccbuf(&self) -> CCBUF_R { + CCBUF_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Counter/Compare Buffer Value"] + #[inline(always)] + pub fn ccbuf(&mut self) -> CCBUF_W { + CCBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT8 Compare and Capture Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccbuf](index.html) module"] +pub struct CCBUF_SPEC; +impl crate::RegisterSpec for CCBUF_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ccbuf::R](R) reader structure"] +impl crate::Readable for CCBUF_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ccbuf::W](W) writer structure"] +impl crate::Writable for CCBUF_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CCBUF[%s] +to value 0"] +impl crate::Resettable for CCBUF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/tc0/count8/count.rs b/pac/atsamc21g/src/tc0/count8/count.rs new file mode 100644 index 000000000000..0edbb0f17bb7 --- /dev/null +++ b/pac/atsamc21g/src/tc0/count8/count.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT8 Count\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count](index.html) module"] +pub struct COUNT_SPEC; +impl crate::RegisterSpec for COUNT_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [count::R](R) reader structure"] +impl crate::Readable for COUNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count::W](W) writer structure"] +impl crate::Writable for COUNT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT to value 0"] +impl crate::Resettable for COUNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/tc0/count8/ctrla.rs b/pac/atsamc21g/src/tc0/count8/ctrla.rs new file mode 100644 index 000000000000..cadcddaaead8 --- /dev/null +++ b/pac/atsamc21g/src/tc0/count8/ctrla.rs @@ -0,0 +1,851 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Timer Counter Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: Counter in 16-bit mode"] + COUNT16 = 0, + #[doc = "1: Counter in 8-bit mode"] + COUNT8 = 1, + #[doc = "2: Counter in 32-bit mode"] + COUNT32 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Timer Counter Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::COUNT16), + 1 => Some(MODE_A::COUNT8), + 2 => Some(MODE_A::COUNT32), + _ => None, + } + } + #[doc = "Checks if the value of the field is `COUNT16`"] + #[inline(always)] + pub fn is_count16(&self) -> bool { + **self == MODE_A::COUNT16 + } + #[doc = "Checks if the value of the field is `COUNT8`"] + #[inline(always)] + pub fn is_count8(&self) -> bool { + **self == MODE_A::COUNT8 + } + #[doc = "Checks if the value of the field is `COUNT32`"] + #[inline(always)] + pub fn is_count32(&self) -> bool { + **self == MODE_A::COUNT32 + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Timer Counter Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Counter in 16-bit mode"] + #[inline(always)] + pub fn count16(self) -> &'a mut W { + self.variant(MODE_A::COUNT16) + } + #[doc = "Counter in 8-bit mode"] + #[inline(always)] + pub fn count8(self) -> &'a mut W { + self.variant(MODE_A::COUNT8) + } + #[doc = "Counter in 32-bit mode"] + #[inline(always)] + pub fn count32(self) -> &'a mut W { + self.variant(MODE_A::COUNT32) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u32 & 0x03) << 2); + self.w + } +} +#[doc = "Prescaler and Counter Synchronization\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCSYNC_A { + #[doc = "0: Reload or reset the counter on next generic clock"] + GCLK = 0, + #[doc = "1: Reload or reset the counter on next prescaler clock"] + PRESC = 1, + #[doc = "2: Reload or reset the counter on next generic clock and reset the prescaler counter"] + RESYNC = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCSYNC_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCSYNC` reader - Prescaler and Counter Synchronization"] +pub struct PRESCSYNC_R(crate::FieldReader); +impl PRESCSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCSYNC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCSYNC_A::GCLK), + 1 => Some(PRESCSYNC_A::PRESC), + 2 => Some(PRESCSYNC_A::RESYNC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `GCLK`"] + #[inline(always)] + pub fn is_gclk(&self) -> bool { + **self == PRESCSYNC_A::GCLK + } + #[doc = "Checks if the value of the field is `PRESC`"] + #[inline(always)] + pub fn is_presc(&self) -> bool { + **self == PRESCSYNC_A::PRESC + } + #[doc = "Checks if the value of the field is `RESYNC`"] + #[inline(always)] + pub fn is_resync(&self) -> bool { + **self == PRESCSYNC_A::RESYNC + } +} +impl core::ops::Deref for PRESCSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCSYNC` writer - Prescaler and Counter Synchronization"] +pub struct PRESCSYNC_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCSYNC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCSYNC_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Reload or reset the counter on next generic clock"] + #[inline(always)] + pub fn gclk(self) -> &'a mut W { + self.variant(PRESCSYNC_A::GCLK) + } + #[doc = "Reload or reset the counter on next prescaler clock"] + #[inline(always)] + pub fn presc(self) -> &'a mut W { + self.variant(PRESCSYNC_A::PRESC) + } + #[doc = "Reload or reset the counter on next generic clock and reset the prescaler counter"] + #[inline(always)] + pub fn resync(self) -> &'a mut W { + self.variant(PRESCSYNC_A::RESYNC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u32 & 0x03) << 4); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - Clock On Demand"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - Clock On Demand"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: Prescaler: GCLK_TC"] + DIV1 = 0, + #[doc = "1: Prescaler: GCLK_TC/2"] + DIV2 = 1, + #[doc = "2: Prescaler: GCLK_TC/4"] + DIV4 = 2, + #[doc = "3: Prescaler: GCLK_TC/8"] + DIV8 = 3, + #[doc = "4: Prescaler: GCLK_TC/16"] + DIV16 = 4, + #[doc = "5: Prescaler: GCLK_TC/64"] + DIV64 = 5, + #[doc = "6: Prescaler: GCLK_TC/256"] + DIV256 = 6, + #[doc = "7: Prescaler: GCLK_TC/1024"] + DIV1024 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PRESCALER_A { + match self.bits { + 0 => PRESCALER_A::DIV1, + 1 => PRESCALER_A::DIV2, + 2 => PRESCALER_A::DIV4, + 3 => PRESCALER_A::DIV8, + 4 => PRESCALER_A::DIV16, + 5 => PRESCALER_A::DIV64, + 6 => PRESCALER_A::DIV256, + 7 => PRESCALER_A::DIV1024, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == PRESCALER_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PRESCALER_A::DIV1024 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Prescaler: GCLK_TC"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1) + } + #[doc = "Prescaler: GCLK_TC/2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "Prescaler: GCLK_TC/4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "Prescaler: GCLK_TC/8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "Prescaler: GCLK_TC/16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "Prescaler: GCLK_TC/64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "Prescaler: GCLK_TC/256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = "Prescaler: GCLK_TC/1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +#[doc = "Field `ALOCK` reader - Auto Lock"] +pub struct ALOCK_R(crate::FieldReader); +impl ALOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALOCK` writer - Auto Lock"] +pub struct ALOCK_W<'a> { + w: &'a mut W, +} +impl<'a> ALOCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `CAPTEN0` reader - Capture Channel 0 Enable"] +pub struct CAPTEN0_R(crate::FieldReader); +impl CAPTEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CAPTEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CAPTEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAPTEN0` writer - Capture Channel 0 Enable"] +pub struct CAPTEN0_W<'a> { + w: &'a mut W, +} +impl<'a> CAPTEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `CAPTEN1` reader - Capture Channel 1 Enable"] +pub struct CAPTEN1_R(crate::FieldReader); +impl CAPTEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CAPTEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CAPTEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAPTEN1` writer - Capture Channel 1 Enable"] +pub struct CAPTEN1_W<'a> { + w: &'a mut W, +} +impl<'a> CAPTEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `COPEN0` reader - Capture On Pin 0 Enable"] +pub struct COPEN0_R(crate::FieldReader); +impl COPEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COPEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COPEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COPEN0` writer - Capture On Pin 0 Enable"] +pub struct COPEN0_W<'a> { + w: &'a mut W, +} +impl<'a> COPEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `COPEN1` reader - Capture On Pin 1 Enable"] +pub struct COPEN1_R(crate::FieldReader); +impl COPEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COPEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COPEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COPEN1` writer - Capture On Pin 1 Enable"] +pub struct COPEN1_W<'a> { + w: &'a mut W, +} +impl<'a> COPEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:3 - Timer Counter Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bits 4:5 - Prescaler and Counter Synchronization"] + #[inline(always)] + pub fn prescsync(&self) -> PRESCSYNC_R { + PRESCSYNC_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Clock On Demand"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 11 - Auto Lock"] + #[inline(always)] + pub fn alock(&self) -> ALOCK_R { + ALOCK_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 16 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn capten0(&self) -> CAPTEN0_R { + CAPTEN0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn capten1(&self) -> CAPTEN1_R { + CAPTEN1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 20 - Capture On Pin 0 Enable"] + #[inline(always)] + pub fn copen0(&self) -> COPEN0_R { + COPEN0_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Capture On Pin 1 Enable"] + #[inline(always)] + pub fn copen1(&self) -> COPEN1_R { + COPEN1_R::new(((self.bits >> 21) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:3 - Timer Counter Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bits 4:5 - Prescaler and Counter Synchronization"] + #[inline(always)] + pub fn prescsync(&mut self) -> PRESCSYNC_W { + PRESCSYNC_W { w: self } + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - Clock On Demand"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Bit 11 - Auto Lock"] + #[inline(always)] + pub fn alock(&mut self) -> ALOCK_W { + ALOCK_W { w: self } + } + #[doc = "Bit 16 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn capten0(&mut self) -> CAPTEN0_W { + CAPTEN0_W { w: self } + } + #[doc = "Bit 17 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn capten1(&mut self) -> CAPTEN1_W { + CAPTEN1_W { w: self } + } + #[doc = "Bit 20 - Capture On Pin 0 Enable"] + #[inline(always)] + pub fn copen0(&mut self) -> COPEN0_W { + COPEN0_W { w: self } + } + #[doc = "Bit 21 - Capture On Pin 1 Enable"] + #[inline(always)] + pub fn copen1(&mut self) -> COPEN1_W { + COPEN1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/tc0/count8/ctrlbclr.rs b/pac/atsamc21g/src/tc0/count8/ctrlbclr.rs new file mode 100644 index 000000000000..76265674036a --- /dev/null +++ b/pac/atsamc21g/src/tc0/count8/ctrlbclr.rs @@ -0,0 +1,345 @@ +#[doc = "Register `CTRLBCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Counter Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `LUPD` reader - Lock Update"] +pub struct LUPD_R(crate::FieldReader); +impl LUPD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LUPD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LUPD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LUPD` writer - Lock Update"] +pub struct LUPD_W<'a> { + w: &'a mut W, +} +impl<'a> LUPD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ONESHOT` reader - One-Shot on Counter"] +pub struct ONESHOT_R(crate::FieldReader); +impl ONESHOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONESHOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONESHOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONESHOT` writer - One-Shot on Counter"] +pub struct ONESHOT_W<'a> { + w: &'a mut W, +} +impl<'a> ONESHOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Force a start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force a stop"] + STOP = 2, + #[doc = "3: Force update of double-buffered register"] + UPDATE = 3, + #[doc = "4: Force a read synchronization of COUNT"] + READSYNC = 4, + #[doc = "5: One-shot DMA trigger"] + DMAOS = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NONE), + 1 => Some(CMD_A::RETRIGGER), + 2 => Some(CMD_A::STOP), + 3 => Some(CMD_A::UPDATE), + 4 => Some(CMD_A::READSYNC), + 5 => Some(CMD_A::DMAOS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == CMD_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == CMD_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == CMD_A::STOP + } + #[doc = "Checks if the value of the field is `UPDATE`"] + #[inline(always)] + pub fn is_update(&self) -> bool { + **self == CMD_A::UPDATE + } + #[doc = "Checks if the value of the field is `READSYNC`"] + #[inline(always)] + pub fn is_readsync(&self) -> bool { + **self == CMD_A::READSYNC + } + #[doc = "Checks if the value of the field is `DMAOS`"] + #[inline(always)] + pub fn is_dmaos(&self) -> bool { + **self == CMD_A::DMAOS + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMD_A::NONE) + } + #[doc = "Force a start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMD_A::RETRIGGER) + } + #[doc = "Force a stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMD_A::STOP) + } + #[doc = "Force update of double-buffered register"] + #[inline(always)] + pub fn update(self) -> &'a mut W { + self.variant(CMD_A::UPDATE) + } + #[doc = "Force a read synchronization of COUNT"] + #[inline(always)] + pub fn readsync(self) -> &'a mut W { + self.variant(CMD_A::READSYNC) + } + #[doc = "One-shot DMA trigger"] + #[inline(always)] + pub fn dmaos(self) -> &'a mut W { + self.variant(CMD_A::DMAOS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 5)) | ((value as u8 & 0x07) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&self) -> LUPD_R { + LUPD_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 5) & 0x07) as u8) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&mut self) -> LUPD_W { + LUPD_W { w: self } + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&mut self) -> ONESHOT_W { + ONESHOT_W { w: self } + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbclr](index.html) module"] +pub struct CTRLBCLR_SPEC; +impl crate::RegisterSpec for CTRLBCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbclr::R](R) reader structure"] +impl crate::Readable for CTRLBCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbclr::W](W) writer structure"] +impl crate::Writable for CTRLBCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLBCLR to value 0"] +impl crate::Resettable for CTRLBCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/tc0/count8/ctrlbset.rs b/pac/atsamc21g/src/tc0/count8/ctrlbset.rs new file mode 100644 index 000000000000..610914c9c7c8 --- /dev/null +++ b/pac/atsamc21g/src/tc0/count8/ctrlbset.rs @@ -0,0 +1,345 @@ +#[doc = "Register `CTRLBSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Counter Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `LUPD` reader - Lock Update"] +pub struct LUPD_R(crate::FieldReader); +impl LUPD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LUPD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LUPD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LUPD` writer - Lock Update"] +pub struct LUPD_W<'a> { + w: &'a mut W, +} +impl<'a> LUPD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ONESHOT` reader - One-Shot on Counter"] +pub struct ONESHOT_R(crate::FieldReader); +impl ONESHOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONESHOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONESHOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONESHOT` writer - One-Shot on Counter"] +pub struct ONESHOT_W<'a> { + w: &'a mut W, +} +impl<'a> ONESHOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Force a start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force a stop"] + STOP = 2, + #[doc = "3: Force update of double-buffered register"] + UPDATE = 3, + #[doc = "4: Force a read synchronization of COUNT"] + READSYNC = 4, + #[doc = "5: One-shot DMA trigger"] + DMAOS = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NONE), + 1 => Some(CMD_A::RETRIGGER), + 2 => Some(CMD_A::STOP), + 3 => Some(CMD_A::UPDATE), + 4 => Some(CMD_A::READSYNC), + 5 => Some(CMD_A::DMAOS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == CMD_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == CMD_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == CMD_A::STOP + } + #[doc = "Checks if the value of the field is `UPDATE`"] + #[inline(always)] + pub fn is_update(&self) -> bool { + **self == CMD_A::UPDATE + } + #[doc = "Checks if the value of the field is `READSYNC`"] + #[inline(always)] + pub fn is_readsync(&self) -> bool { + **self == CMD_A::READSYNC + } + #[doc = "Checks if the value of the field is `DMAOS`"] + #[inline(always)] + pub fn is_dmaos(&self) -> bool { + **self == CMD_A::DMAOS + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMD_A::NONE) + } + #[doc = "Force a start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMD_A::RETRIGGER) + } + #[doc = "Force a stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMD_A::STOP) + } + #[doc = "Force update of double-buffered register"] + #[inline(always)] + pub fn update(self) -> &'a mut W { + self.variant(CMD_A::UPDATE) + } + #[doc = "Force a read synchronization of COUNT"] + #[inline(always)] + pub fn readsync(self) -> &'a mut W { + self.variant(CMD_A::READSYNC) + } + #[doc = "One-shot DMA trigger"] + #[inline(always)] + pub fn dmaos(self) -> &'a mut W { + self.variant(CMD_A::DMAOS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 5)) | ((value as u8 & 0x07) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&self) -> LUPD_R { + LUPD_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 5) & 0x07) as u8) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&mut self) -> LUPD_W { + LUPD_W { w: self } + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&mut self) -> ONESHOT_W { + ONESHOT_W { w: self } + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbset](index.html) module"] +pub struct CTRLBSET_SPEC; +impl crate::RegisterSpec for CTRLBSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbset::R](R) reader structure"] +impl crate::Readable for CTRLBSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbset::W](W) writer structure"] +impl crate::Writable for CTRLBSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLBSET to value 0"] +impl crate::Resettable for CTRLBSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/tc0/count8/dbgctrl.rs b/pac/atsamc21g/src/tc0/count8/dbgctrl.rs new file mode 100644 index 000000000000..0383e70d0429 --- /dev/null +++ b/pac/atsamc21g/src/tc0/count8/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Run During Debug"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Run During Debug"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/tc0/count8/drvctrl.rs b/pac/atsamc21g/src/tc0/count8/drvctrl.rs new file mode 100644 index 000000000000..323926b4b22d --- /dev/null +++ b/pac/atsamc21g/src/tc0/count8/drvctrl.rs @@ -0,0 +1,160 @@ +#[doc = "Register `DRVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DRVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INVEN0` reader - Output Waveform Invert Enable 0"] +pub struct INVEN0_R(crate::FieldReader); +impl INVEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN0` writer - Output Waveform Invert Enable 0"] +pub struct INVEN0_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `INVEN1` reader - Output Waveform Invert Enable 1"] +pub struct INVEN1_R(crate::FieldReader); +impl INVEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN1` writer - Output Waveform Invert Enable 1"] +pub struct INVEN1_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - Output Waveform Invert Enable 0"] + #[inline(always)] + pub fn inven0(&self) -> INVEN0_R { + INVEN0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Output Waveform Invert Enable 1"] + #[inline(always)] + pub fn inven1(&self) -> INVEN1_R { + INVEN1_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Output Waveform Invert Enable 0"] + #[inline(always)] + pub fn inven0(&mut self) -> INVEN0_W { + INVEN0_W { w: self } + } + #[doc = "Bit 1 - Output Waveform Invert Enable 1"] + #[inline(always)] + pub fn inven1(&mut self) -> INVEN1_W { + INVEN1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control C\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [drvctrl](index.html) module"] +pub struct DRVCTRL_SPEC; +impl crate::RegisterSpec for DRVCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [drvctrl::R](R) reader structure"] +impl crate::Readable for DRVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [drvctrl::W](W) writer structure"] +impl crate::Writable for DRVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DRVCTRL to value 0"] +impl crate::Resettable for DRVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/tc0/count8/evctrl.rs b/pac/atsamc21g/src/tc0/count8/evctrl.rs new file mode 100644 index 000000000000..7d4c38d486c1 --- /dev/null +++ b/pac/atsamc21g/src/tc0/count8/evctrl.rs @@ -0,0 +1,465 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Event Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EVACT_A { + #[doc = "0: Event action disabled"] + OFF = 0, + #[doc = "1: Start, restart or retrigger TC on event"] + RETRIGGER = 1, + #[doc = "2: Count on event"] + COUNT = 2, + #[doc = "3: Start TC on event"] + START = 3, + #[doc = "4: Time stamp capture"] + STAMP = 4, + #[doc = "5: Period catured in CC0, pulse width in CC1"] + PPW = 5, + #[doc = "6: Period catured in CC1, pulse width in CC0"] + PWP = 6, + #[doc = "7: Pulse width capture"] + PW = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EVACT_A) -> Self { + variant as _ + } +} +#[doc = "Field `EVACT` reader - Event Action"] +pub struct EVACT_R(crate::FieldReader); +impl EVACT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVACT_A { + match self.bits { + 0 => EVACT_A::OFF, + 1 => EVACT_A::RETRIGGER, + 2 => EVACT_A::COUNT, + 3 => EVACT_A::START, + 4 => EVACT_A::STAMP, + 5 => EVACT_A::PPW, + 6 => EVACT_A::PWP, + 7 => EVACT_A::PW, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == EVACT_A::OFF + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == EVACT_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `COUNT`"] + #[inline(always)] + pub fn is_count(&self) -> bool { + **self == EVACT_A::COUNT + } + #[doc = "Checks if the value of the field is `START`"] + #[inline(always)] + pub fn is_start(&self) -> bool { + **self == EVACT_A::START + } + #[doc = "Checks if the value of the field is `STAMP`"] + #[inline(always)] + pub fn is_stamp(&self) -> bool { + **self == EVACT_A::STAMP + } + #[doc = "Checks if the value of the field is `PPW`"] + #[inline(always)] + pub fn is_ppw(&self) -> bool { + **self == EVACT_A::PPW + } + #[doc = "Checks if the value of the field is `PWP`"] + #[inline(always)] + pub fn is_pwp(&self) -> bool { + **self == EVACT_A::PWP + } + #[doc = "Checks if the value of the field is `PW`"] + #[inline(always)] + pub fn is_pw(&self) -> bool { + **self == EVACT_A::PW + } +} +impl core::ops::Deref for EVACT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT` writer - Event Action"] +pub struct EVACT_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EVACT_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Event action disabled"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(EVACT_A::OFF) + } + #[doc = "Start, restart or retrigger TC on event"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(EVACT_A::RETRIGGER) + } + #[doc = "Count on event"] + #[inline(always)] + pub fn count(self) -> &'a mut W { + self.variant(EVACT_A::COUNT) + } + #[doc = "Start TC on event"] + #[inline(always)] + pub fn start(self) -> &'a mut W { + self.variant(EVACT_A::START) + } + #[doc = "Time stamp capture"] + #[inline(always)] + pub fn stamp(self) -> &'a mut W { + self.variant(EVACT_A::STAMP) + } + #[doc = "Period catured in CC0, pulse width in CC1"] + #[inline(always)] + pub fn ppw(self) -> &'a mut W { + self.variant(EVACT_A::PPW) + } + #[doc = "Period catured in CC1, pulse width in CC0"] + #[inline(always)] + pub fn pwp(self) -> &'a mut W { + self.variant(EVACT_A::PWP) + } + #[doc = "Pulse width capture"] + #[inline(always)] + pub fn pw(self) -> &'a mut W { + self.variant(EVACT_A::PW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u16 & 0x07); + self.w + } +} +#[doc = "Field `TCINV` reader - TC Event Input Polarity"] +pub struct TCINV_R(crate::FieldReader); +impl TCINV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCINV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCINV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCINV` writer - TC Event Input Polarity"] +pub struct TCINV_W<'a> { + w: &'a mut W, +} +impl<'a> TCINV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `TCEI` reader - TC Event Enable"] +pub struct TCEI_R(crate::FieldReader); +impl TCEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCEI` writer - TC Event Enable"] +pub struct TCEI_W<'a> { + w: &'a mut W, +} +impl<'a> TCEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `OVFEO` reader - Event Output Enable"] +pub struct OVFEO_R(crate::FieldReader); +impl OVFEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVFEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVFEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVFEO` writer - Event Output Enable"] +pub struct OVFEO_W<'a> { + w: &'a mut W, +} +impl<'a> OVFEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `MCEO0` reader - MC Event Output Enable 0"] +pub struct MCEO0_R(crate::FieldReader); +impl MCEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO0` writer - MC Event Output Enable 0"] +pub struct MCEO0_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u16 & 0x01) << 12); + self.w + } +} +#[doc = "Field `MCEO1` reader - MC Event Output Enable 1"] +pub struct MCEO1_R(crate::FieldReader); +impl MCEO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO1` writer - MC Event Output Enable 1"] +pub struct MCEO1_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u16 & 0x01) << 13); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Event Action"] + #[inline(always)] + pub fn evact(&self) -> EVACT_R { + EVACT_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 4 - TC Event Input Polarity"] + #[inline(always)] + pub fn tcinv(&self) -> TCINV_R { + TCINV_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - TC Event Enable"] + #[inline(always)] + pub fn tcei(&self) -> TCEI_R { + TCEI_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 8 - Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&self) -> OVFEO_R { + OVFEO_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 12 - MC Event Output Enable 0"] + #[inline(always)] + pub fn mceo0(&self) -> MCEO0_R { + MCEO0_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - MC Event Output Enable 1"] + #[inline(always)] + pub fn mceo1(&self) -> MCEO1_R { + MCEO1_R::new(((self.bits >> 13) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Event Action"] + #[inline(always)] + pub fn evact(&mut self) -> EVACT_W { + EVACT_W { w: self } + } + #[doc = "Bit 4 - TC Event Input Polarity"] + #[inline(always)] + pub fn tcinv(&mut self) -> TCINV_W { + TCINV_W { w: self } + } + #[doc = "Bit 5 - TC Event Enable"] + #[inline(always)] + pub fn tcei(&mut self) -> TCEI_W { + TCEI_W { w: self } + } + #[doc = "Bit 8 - Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&mut self) -> OVFEO_W { + OVFEO_W { w: self } + } + #[doc = "Bit 12 - MC Event Output Enable 0"] + #[inline(always)] + pub fn mceo0(&mut self) -> MCEO0_W { + MCEO0_W { w: self } + } + #[doc = "Bit 13 - MC Event Output Enable 1"] + #[inline(always)] + pub fn mceo1(&mut self) -> MCEO1_W { + MCEO1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/tc0/count8/intenclr.rs b/pac/atsamc21g/src/tc0/count8/intenclr.rs new file mode 100644 index 000000000000..af01ef5b7dca --- /dev/null +++ b/pac/atsamc21g/src/tc0/count8/intenclr.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - OVF Interrupt Disable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - OVF Interrupt Disable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - ERR Interrupt Disable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - ERR Interrupt Disable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MC0` reader - MC Interrupt Disable 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - MC Interrupt Disable 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - MC Interrupt Disable 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - MC Interrupt Disable 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - OVF Interrupt Disable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ERR Interrupt Disable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - MC Interrupt Disable 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - MC Interrupt Disable 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - OVF Interrupt Disable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - ERR Interrupt Disable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 4 - MC Interrupt Disable 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - MC Interrupt Disable 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/tc0/count8/intenset.rs b/pac/atsamc21g/src/tc0/count8/intenset.rs new file mode 100644 index 000000000000..0e1883a2f20a --- /dev/null +++ b/pac/atsamc21g/src/tc0/count8/intenset.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - OVF Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - OVF Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - ERR Interrupt Enable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - ERR Interrupt Enable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MC0` reader - MC Interrupt Enable 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - MC Interrupt Enable 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - MC Interrupt Enable 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - MC Interrupt Enable 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - OVF Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ERR Interrupt Enable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - MC Interrupt Enable 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - MC Interrupt Enable 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - OVF Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - ERR Interrupt Enable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 4 - MC Interrupt Enable 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - MC Interrupt Enable 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/tc0/count8/intflag.rs b/pac/atsamc21g/src/tc0/count8/intflag.rs new file mode 100644 index 000000000000..1dddffaf8e7f --- /dev/null +++ b/pac/atsamc21g/src/tc0/count8/intflag.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - OVF Interrupt Flag"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - OVF Interrupt Flag"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - ERR Interrupt Flag"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - ERR Interrupt Flag"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MC0` reader - MC Interrupt Flag 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - MC Interrupt Flag 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - MC Interrupt Flag 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - MC Interrupt Flag 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - OVF Interrupt Flag"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ERR Interrupt Flag"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - MC Interrupt Flag 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - MC Interrupt Flag 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - OVF Interrupt Flag"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - ERR Interrupt Flag"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 4 - MC Interrupt Flag 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - MC Interrupt Flag 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/tc0/count8/per.rs b/pac/atsamc21g/src/tc0/count8/per.rs new file mode 100644 index 000000000000..c9ab52e247d8 --- /dev/null +++ b/pac/atsamc21g/src/tc0/count8/per.rs @@ -0,0 +1,103 @@ +#[doc = "Register `PER` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PER` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER` reader - Period Value"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` writer - Period Value"] +pub struct PER_W<'a> { + w: &'a mut W, +} +impl<'a> PER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Period Value"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Period Value"] + #[inline(always)] + pub fn per(&mut self) -> PER_W { + PER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT8 Period\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [per](index.html) module"] +pub struct PER_SPEC; +impl crate::RegisterSpec for PER_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [per::R](R) reader structure"] +impl crate::Readable for PER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [per::W](W) writer structure"] +impl crate::Writable for PER_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PER to value 0xff"] +impl crate::Resettable for PER_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xff + } +} diff --git a/pac/atsamc21g/src/tc0/count8/perbuf.rs b/pac/atsamc21g/src/tc0/count8/perbuf.rs new file mode 100644 index 000000000000..cbd500e2bbe1 --- /dev/null +++ b/pac/atsamc21g/src/tc0/count8/perbuf.rs @@ -0,0 +1,103 @@ +#[doc = "Register `PERBUF` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PERBUF` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PERBUF` reader - Period Buffer Value"] +pub struct PERBUF_R(crate::FieldReader); +impl PERBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PERBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERBUF` writer - Period Buffer Value"] +pub struct PERBUF_W<'a> { + w: &'a mut W, +} +impl<'a> PERBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Period Buffer Value"] + #[inline(always)] + pub fn perbuf(&self) -> PERBUF_R { + PERBUF_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Period Buffer Value"] + #[inline(always)] + pub fn perbuf(&mut self) -> PERBUF_W { + PERBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT8 Period Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [perbuf](index.html) module"] +pub struct PERBUF_SPEC; +impl crate::RegisterSpec for PERBUF_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [perbuf::R](R) reader structure"] +impl crate::Readable for PERBUF_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [perbuf::W](W) writer structure"] +impl crate::Writable for PERBUF_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PERBUF to value 0xff"] +impl crate::Resettable for PERBUF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xff + } +} diff --git a/pac/atsamc21g/src/tc0/count8/status.rs b/pac/atsamc21g/src/tc0/count8/status.rs new file mode 100644 index 000000000000..5088af446830 --- /dev/null +++ b/pac/atsamc21g/src/tc0/count8/status.rs @@ -0,0 +1,301 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `STOP` reader - Stop Status Flag"] +pub struct STOP_R(crate::FieldReader); +impl STOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STOP` writer - Stop Status Flag"] +pub struct STOP_W<'a> { + w: &'a mut W, +} +impl<'a> STOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SLAVE` reader - Slave Status Flag"] +pub struct SLAVE_R(crate::FieldReader); +impl SLAVE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLAVE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SLAVE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLAVE` writer - Slave Status Flag"] +pub struct SLAVE_W<'a> { + w: &'a mut W, +} +impl<'a> SLAVE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PERBUFV` reader - Synchronization Busy Status"] +pub struct PERBUFV_R(crate::FieldReader); +impl PERBUFV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PERBUFV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERBUFV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERBUFV` writer - Synchronization Busy Status"] +pub struct PERBUFV_W<'a> { + w: &'a mut W, +} +impl<'a> PERBUFV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CCBUFV0` reader - Compare channel buffer 0 valid"] +pub struct CCBUFV0_R(crate::FieldReader); +impl CCBUFV0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBUFV0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUFV0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUFV0` writer - Compare channel buffer 0 valid"] +pub struct CCBUFV0_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUFV0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `CCBUFV1` reader - Compare channel buffer 1 valid"] +pub struct CCBUFV1_R(crate::FieldReader); +impl CCBUFV1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBUFV1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUFV1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUFV1` writer - Compare channel buffer 1 valid"] +pub struct CCBUFV1_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUFV1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Stop Status Flag"] + #[inline(always)] + pub fn stop(&self) -> STOP_R { + STOP_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Slave Status Flag"] + #[inline(always)] + pub fn slave(&self) -> SLAVE_R { + SLAVE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 3 - Synchronization Busy Status"] + #[inline(always)] + pub fn perbufv(&self) -> PERBUFV_R { + PERBUFV_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Compare channel buffer 0 valid"] + #[inline(always)] + pub fn ccbufv0(&self) -> CCBUFV0_R { + CCBUFV0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Compare channel buffer 1 valid"] + #[inline(always)] + pub fn ccbufv1(&self) -> CCBUFV1_R { + CCBUFV1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Stop Status Flag"] + #[inline(always)] + pub fn stop(&mut self) -> STOP_W { + STOP_W { w: self } + } + #[doc = "Bit 1 - Slave Status Flag"] + #[inline(always)] + pub fn slave(&mut self) -> SLAVE_W { + SLAVE_W { w: self } + } + #[doc = "Bit 3 - Synchronization Busy Status"] + #[inline(always)] + pub fn perbufv(&mut self) -> PERBUFV_W { + PERBUFV_W { w: self } + } + #[doc = "Bit 4 - Compare channel buffer 0 valid"] + #[inline(always)] + pub fn ccbufv0(&mut self) -> CCBUFV0_W { + CCBUFV0_W { w: self } + } + #[doc = "Bit 5 - Compare channel buffer 1 valid"] + #[inline(always)] + pub fn ccbufv1(&mut self) -> CCBUFV1_W { + CCBUFV1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0x01"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pac/atsamc21g/src/tc0/count8/syncbusy.rs b/pac/atsamc21g/src/tc0/count8/syncbusy.rs new file mode 100644 index 000000000000..7ad8d91a84de --- /dev/null +++ b/pac/atsamc21g/src/tc0/count8/syncbusy.rs @@ -0,0 +1,193 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - swrst"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLB` reader - CTRLB"] +pub struct CTRLB_R(crate::FieldReader); +impl CTRLB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STATUS` reader - STATUS"] +pub struct STATUS_R(crate::FieldReader); +impl STATUS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STATUS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STATUS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` reader - Counter"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` reader - Period"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC0` reader - Compare Channel 0"] +pub struct CC0_R(crate::FieldReader); +impl CC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC1` reader - Compare Channel 1"] +pub struct CC1_R(crate::FieldReader); +impl CC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - swrst"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - CTRLB"] + #[inline(always)] + pub fn ctrlb(&self) -> CTRLB_R { + CTRLB_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - STATUS"] + #[inline(always)] + pub fn status(&self) -> STATUS_R { + STATUS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Counter"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Period"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Compare Channel 0"] + #[inline(always)] + pub fn cc0(&self) -> CC0_R { + CC0_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Compare Channel 1"] + #[inline(always)] + pub fn cc1(&self) -> CC1_R { + CC1_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +#[doc = "Synchronization Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/tc0/count8/wave.rs b/pac/atsamc21g/src/tc0/count8/wave.rs new file mode 100644 index 000000000000..46061b24b75d --- /dev/null +++ b/pac/atsamc21g/src/tc0/count8/wave.rs @@ -0,0 +1,178 @@ +#[doc = "Register `WAVE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WAVE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Waveform Generation Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WAVEGEN_A { + #[doc = "0: Normal frequency"] + NFRQ = 0, + #[doc = "1: Match frequency"] + MFRQ = 1, + #[doc = "2: Normal PWM"] + NPWM = 2, + #[doc = "3: Match PWM"] + MPWM = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WAVEGEN_A) -> Self { + variant as _ + } +} +#[doc = "Field `WAVEGEN` reader - Waveform Generation Mode"] +pub struct WAVEGEN_R(crate::FieldReader); +impl WAVEGEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WAVEGEN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> WAVEGEN_A { + match self.bits { + 0 => WAVEGEN_A::NFRQ, + 1 => WAVEGEN_A::MFRQ, + 2 => WAVEGEN_A::NPWM, + 3 => WAVEGEN_A::MPWM, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NFRQ`"] + #[inline(always)] + pub fn is_nfrq(&self) -> bool { + **self == WAVEGEN_A::NFRQ + } + #[doc = "Checks if the value of the field is `MFRQ`"] + #[inline(always)] + pub fn is_mfrq(&self) -> bool { + **self == WAVEGEN_A::MFRQ + } + #[doc = "Checks if the value of the field is `NPWM`"] + #[inline(always)] + pub fn is_npwm(&self) -> bool { + **self == WAVEGEN_A::NPWM + } + #[doc = "Checks if the value of the field is `MPWM`"] + #[inline(always)] + pub fn is_mpwm(&self) -> bool { + **self == WAVEGEN_A::MPWM + } +} +impl core::ops::Deref for WAVEGEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAVEGEN` writer - Waveform Generation Mode"] +pub struct WAVEGEN_W<'a> { + w: &'a mut W, +} +impl<'a> WAVEGEN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WAVEGEN_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Normal frequency"] + #[inline(always)] + pub fn nfrq(self) -> &'a mut W { + self.variant(WAVEGEN_A::NFRQ) + } + #[doc = "Match frequency"] + #[inline(always)] + pub fn mfrq(self) -> &'a mut W { + self.variant(WAVEGEN_A::MFRQ) + } + #[doc = "Normal PWM"] + #[inline(always)] + pub fn npwm(self) -> &'a mut W { + self.variant(WAVEGEN_A::NPWM) + } + #[doc = "Match PWM"] + #[inline(always)] + pub fn mpwm(self) -> &'a mut W { + self.variant(WAVEGEN_A::MPWM) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u8 & 0x03); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Waveform Generation Mode"] + #[inline(always)] + pub fn wavegen(&self) -> WAVEGEN_R { + WAVEGEN_R::new((self.bits & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Waveform Generation Mode"] + #[inline(always)] + pub fn wavegen(&mut self) -> WAVEGEN_W { + WAVEGEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Waveform Generation Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wave](index.html) module"] +pub struct WAVE_SPEC; +impl crate::RegisterSpec for WAVE_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [wave::R](R) reader structure"] +impl crate::Readable for WAVE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wave::W](W) writer structure"] +impl crate::Writable for WAVE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WAVE to value 0"] +impl crate::Resettable for WAVE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/tcc0.rs b/pac/atsamc21g/src/tcc0.rs new file mode 100644 index 000000000000..6ce813a9e3d5 --- /dev/null +++ b/pac/atsamc21g/src/tcc0.rs @@ -0,0 +1,359 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - Control B Clear"] + pub ctrlbclr: crate::Reg, + #[doc = "0x05 - Control B Set"] + pub ctrlbset: crate::Reg, + _reserved3: [u8; 0x02], + #[doc = "0x08 - Synchronization Busy"] + pub syncbusy: crate::Reg, + #[doc = "0x0c - Recoverable Fault A Configuration"] + pub fctrla: crate::Reg, + #[doc = "0x10 - Recoverable Fault B Configuration"] + pub fctrlb: crate::Reg, + #[doc = "0x14 - Waveform Extension Configuration"] + pub wexctrl: crate::Reg, + #[doc = "0x18 - Driver Control"] + pub drvctrl: crate::Reg, + _reserved8: [u8; 0x02], + #[doc = "0x1e - Debug Control"] + pub dbgctrl: crate::Reg, + _reserved9: [u8; 0x01], + #[doc = "0x20 - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x24 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x28 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x2c - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x30 - Status"] + pub status: crate::Reg, + _reserved_14_count: [u8; 0x04], + #[doc = "0x38 - Pattern"] + pub patt: crate::Reg, + _reserved16: [u8; 0x02], + #[doc = "0x3c - Waveform Control"] + pub wave: crate::Reg, + _reserved_17_per: [u8; 0x04], + _reserved_18_cc: [u8; 0x10], + _reserved19: [u8; 0x10], + #[doc = "0x64 - Pattern Buffer"] + pub pattbuf: crate::Reg, + _reserved20: [u8; 0x06], + _reserved_20_perbuf: [u8; 0x04], + _reserved_21_ccbuf: [u8; 0x10], +} +impl RegisterBlock { + #[doc = "0x34 - Count"] + #[inline(always)] + pub fn count_dith6_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(52usize) + as *const crate::Reg) + } + } + #[doc = "0x34 - Count"] + #[inline(always)] + pub fn count_dith5_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(52usize) + as *const crate::Reg) + } + } + #[doc = "0x34 - Count"] + #[inline(always)] + pub fn count_dith4_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(52usize) + as *const crate::Reg) + } + } + #[doc = "0x34 - Count"] + #[inline(always)] + pub fn count(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(52usize) + as *const crate::Reg) + } + } + #[doc = "0x40 - Period"] + #[inline(always)] + pub fn per_dith6_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(64usize) + as *const crate::Reg) + } + } + #[doc = "0x40 - Period"] + #[inline(always)] + pub fn per_dith5_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(64usize) + as *const crate::Reg) + } + } + #[doc = "0x40 - Period"] + #[inline(always)] + pub fn per_dith4_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(64usize) + as *const crate::Reg) + } + } + #[doc = "0x40 - Period"] + #[inline(always)] + pub fn per(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(64usize) + as *const crate::Reg) + } + } + #[doc = "0x44..0x54 - Compare and Capture"] + #[inline(always)] + pub fn cc_dith6_mode(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(68usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x44..0x54 - Compare and Capture"] + #[inline(always)] + pub fn cc_dith5_mode(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(68usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x44..0x54 - Compare and Capture"] + #[inline(always)] + pub fn cc_dith4_mode(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(68usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x44..0x54 - Compare and Capture"] + #[inline(always)] + pub fn cc(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(68usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x6c - Period Buffer"] + #[inline(always)] + pub fn perbuf_dith6_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(108usize) + as *const crate::Reg) + } + } + #[doc = "0x6c - Period Buffer"] + #[inline(always)] + pub fn perbuf_dith5_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(108usize) + as *const crate::Reg) + } + } + #[doc = "0x6c - Period Buffer"] + #[inline(always)] + pub fn perbuf_dith4_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(108usize) + as *const crate::Reg) + } + } + #[doc = "0x6c - Period Buffer"] + #[inline(always)] + pub fn perbuf(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(108usize) + as *const crate::Reg) + } + } + #[doc = "0x70..0x80 - Compare and Capture Buffer"] + #[inline(always)] + pub fn ccbuf_dith6_mode(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(112usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x70..0x80 - Compare and Capture Buffer"] + #[inline(always)] + pub fn ccbuf_dith5_mode(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(112usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x70..0x80 - Compare and Capture Buffer"] + #[inline(always)] + pub fn ccbuf_dith4_mode(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(112usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x70..0x80 - Compare and Capture Buffer"] + #[inline(always)] + pub fn ccbuf(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(112usize) + as *const [crate::Reg; 4]) + } + } +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "CTRLBCLR register accessor: an alias for `Reg`"] +pub type CTRLBCLR = crate::Reg; +#[doc = "Control B Clear"] +pub mod ctrlbclr; +#[doc = "CTRLBSET register accessor: an alias for `Reg`"] +pub type CTRLBSET = crate::Reg; +#[doc = "Control B Set"] +pub mod ctrlbset; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Busy"] +pub mod syncbusy; +#[doc = "FCTRLA register accessor: an alias for `Reg`"] +pub type FCTRLA = crate::Reg; +#[doc = "Recoverable Fault A Configuration"] +pub mod fctrla; +#[doc = "FCTRLB register accessor: an alias for `Reg`"] +pub type FCTRLB = crate::Reg; +#[doc = "Recoverable Fault B Configuration"] +pub mod fctrlb; +#[doc = "WEXCTRL register accessor: an alias for `Reg`"] +pub type WEXCTRL = crate::Reg; +#[doc = "Waveform Extension Configuration"] +pub mod wexctrl; +#[doc = "DRVCTRL register accessor: an alias for `Reg`"] +pub type DRVCTRL = crate::Reg; +#[doc = "Driver Control"] +pub mod drvctrl; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "COUNT register accessor: an alias for `Reg`"] +pub type COUNT = crate::Reg; +#[doc = "Count"] +pub mod count; +#[doc = "COUNT_DITH4_MODE register accessor: an alias for `Reg`"] +pub type COUNT_DITH4_MODE = crate::Reg; +#[doc = "Count"] +pub mod count_dith4_mode; +#[doc = "COUNT_DITH5_MODE register accessor: an alias for `Reg`"] +pub type COUNT_DITH5_MODE = crate::Reg; +#[doc = "Count"] +pub mod count_dith5_mode; +#[doc = "COUNT_DITH6_MODE register accessor: an alias for `Reg`"] +pub type COUNT_DITH6_MODE = crate::Reg; +#[doc = "Count"] +pub mod count_dith6_mode; +#[doc = "PATT register accessor: an alias for `Reg`"] +pub type PATT = crate::Reg; +#[doc = "Pattern"] +pub mod patt; +#[doc = "WAVE register accessor: an alias for `Reg`"] +pub type WAVE = crate::Reg; +#[doc = "Waveform Control"] +pub mod wave; +#[doc = "PER register accessor: an alias for `Reg`"] +pub type PER = crate::Reg; +#[doc = "Period"] +pub mod per; +#[doc = "PER_DITH4_MODE register accessor: an alias for `Reg`"] +pub type PER_DITH4_MODE = crate::Reg; +#[doc = "Period"] +pub mod per_dith4_mode; +#[doc = "PER_DITH5_MODE register accessor: an alias for `Reg`"] +pub type PER_DITH5_MODE = crate::Reg; +#[doc = "Period"] +pub mod per_dith5_mode; +#[doc = "PER_DITH6_MODE register accessor: an alias for `Reg`"] +pub type PER_DITH6_MODE = crate::Reg; +#[doc = "Period"] +pub mod per_dith6_mode; +#[doc = "CC register accessor: an alias for `Reg`"] +pub type CC = crate::Reg; +#[doc = "Compare and Capture"] +pub mod cc; +#[doc = "CC_DITH4_MODE register accessor: an alias for `Reg`"] +pub type CC_DITH4_MODE = crate::Reg; +#[doc = "Compare and Capture"] +pub mod cc_dith4_mode; +#[doc = "CC_DITH5_MODE register accessor: an alias for `Reg`"] +pub type CC_DITH5_MODE = crate::Reg; +#[doc = "Compare and Capture"] +pub mod cc_dith5_mode; +#[doc = "CC_DITH6_MODE register accessor: an alias for `Reg`"] +pub type CC_DITH6_MODE = crate::Reg; +#[doc = "Compare and Capture"] +pub mod cc_dith6_mode; +#[doc = "PATTBUF register accessor: an alias for `Reg`"] +pub type PATTBUF = crate::Reg; +#[doc = "Pattern Buffer"] +pub mod pattbuf; +#[doc = "PERBUF register accessor: an alias for `Reg`"] +pub type PERBUF = crate::Reg; +#[doc = "Period Buffer"] +pub mod perbuf; +#[doc = "PERBUF_DITH4_MODE register accessor: an alias for `Reg`"] +pub type PERBUF_DITH4_MODE = crate::Reg; +#[doc = "Period Buffer"] +pub mod perbuf_dith4_mode; +#[doc = "PERBUF_DITH5_MODE register accessor: an alias for `Reg`"] +pub type PERBUF_DITH5_MODE = crate::Reg; +#[doc = "Period Buffer"] +pub mod perbuf_dith5_mode; +#[doc = "PERBUF_DITH6_MODE register accessor: an alias for `Reg`"] +pub type PERBUF_DITH6_MODE = crate::Reg; +#[doc = "Period Buffer"] +pub mod perbuf_dith6_mode; +#[doc = "CCBUF register accessor: an alias for `Reg`"] +pub type CCBUF = crate::Reg; +#[doc = "Compare and Capture Buffer"] +pub mod ccbuf; +#[doc = "CCBUF_DITH4_MODE register accessor: an alias for `Reg`"] +pub type CCBUF_DITH4_MODE = crate::Reg; +#[doc = "Compare and Capture Buffer"] +pub mod ccbuf_dith4_mode; +#[doc = "CCBUF_DITH5_MODE register accessor: an alias for `Reg`"] +pub type CCBUF_DITH5_MODE = crate::Reg; +#[doc = "Compare and Capture Buffer"] +pub mod ccbuf_dith5_mode; +#[doc = "CCBUF_DITH6_MODE register accessor: an alias for `Reg`"] +pub type CCBUF_DITH6_MODE = crate::Reg; +#[doc = "Compare and Capture Buffer"] +pub mod ccbuf_dith6_mode; diff --git a/pac/atsamc21g/src/tcc0/cc.rs b/pac/atsamc21g/src/tcc0/cc.rs new file mode 100644 index 000000000000..c4d6df7a9a20 --- /dev/null +++ b/pac/atsamc21g/src/tcc0/cc.rs @@ -0,0 +1,104 @@ +#[doc = "Register `CC[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CC[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CC` reader - Channel Compare/Capture Value"] +pub struct CC_R(crate::FieldReader); +impl CC_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC` writer - Channel Compare/Capture Value"] +pub struct CC_W<'a> { + w: &'a mut W, +} +impl<'a> CC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&self) -> CC_R { + CC_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&mut self) -> CC_W { + CC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc](index.html) module"] +pub struct CC_SPEC; +impl crate::RegisterSpec for CC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cc::R](R) reader structure"] +impl crate::Readable for CC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cc::W](W) writer structure"] +impl crate::Writable for CC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CC[%s] +to value 0"] +impl crate::Resettable for CC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/tcc0/cc_dith4_mode.rs b/pac/atsamc21g/src/tcc0/cc_dith4_mode.rs new file mode 100644 index 000000000000..c45d8b6bac41 --- /dev/null +++ b/pac/atsamc21g/src/tcc0/cc_dith4_mode.rs @@ -0,0 +1,141 @@ +#[doc = "Register `CC_DITH4_MODE[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CC_DITH4_MODE[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHER` reader - Dithering Cycle Number"] +pub struct DITHER_R(crate::FieldReader); +impl DITHER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHER` writer - Dithering Cycle Number"] +pub struct DITHER_W<'a> { + w: &'a mut W, +} +impl<'a> DITHER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Field `CC` reader - Channel Compare/Capture Value"] +pub struct CC_R(crate::FieldReader); +impl CC_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC` writer - Channel Compare/Capture Value"] +pub struct CC_W<'a> { + w: &'a mut W, +} +impl<'a> CC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x000f_ffff << 4)) | ((value as u32 & 0x000f_ffff) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&self) -> DITHER_R { + DITHER_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&self) -> CC_R { + CC_R::new(((self.bits >> 4) & 0x000f_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:3 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&mut self) -> DITHER_W { + DITHER_W { w: self } + } + #[doc = "Bits 4:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&mut self) -> CC_W { + CC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc_dith4_mode](index.html) module"] +pub struct CC_DITH4_MODE_SPEC; +impl crate::RegisterSpec for CC_DITH4_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cc_dith4_mode::R](R) reader structure"] +impl crate::Readable for CC_DITH4_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cc_dith4_mode::W](W) writer structure"] +impl crate::Writable for CC_DITH4_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CC_DITH4_MODE[%s] +to value 0"] +impl crate::Resettable for CC_DITH4_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/tcc0/cc_dith5_mode.rs b/pac/atsamc21g/src/tcc0/cc_dith5_mode.rs new file mode 100644 index 000000000000..0592b923051a --- /dev/null +++ b/pac/atsamc21g/src/tcc0/cc_dith5_mode.rs @@ -0,0 +1,141 @@ +#[doc = "Register `CC_DITH5_MODE[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CC_DITH5_MODE[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHER` reader - Dithering Cycle Number"] +pub struct DITHER_R(crate::FieldReader); +impl DITHER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHER` writer - Dithering Cycle Number"] +pub struct DITHER_W<'a> { + w: &'a mut W, +} +impl<'a> DITHER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f); + self.w + } +} +#[doc = "Field `CC` reader - Channel Compare/Capture Value"] +pub struct CC_R(crate::FieldReader); +impl CC_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC` writer - Channel Compare/Capture Value"] +pub struct CC_W<'a> { + w: &'a mut W, +} +impl<'a> CC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0007_ffff << 5)) | ((value as u32 & 0x0007_ffff) << 5); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&self) -> DITHER_R { + DITHER_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&self) -> CC_R { + CC_R::new(((self.bits >> 5) & 0x0007_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:4 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&mut self) -> DITHER_W { + DITHER_W { w: self } + } + #[doc = "Bits 5:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&mut self) -> CC_W { + CC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc_dith5_mode](index.html) module"] +pub struct CC_DITH5_MODE_SPEC; +impl crate::RegisterSpec for CC_DITH5_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cc_dith5_mode::R](R) reader structure"] +impl crate::Readable for CC_DITH5_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cc_dith5_mode::W](W) writer structure"] +impl crate::Writable for CC_DITH5_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CC_DITH5_MODE[%s] +to value 0"] +impl crate::Resettable for CC_DITH5_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/tcc0/cc_dith6_mode.rs b/pac/atsamc21g/src/tcc0/cc_dith6_mode.rs new file mode 100644 index 000000000000..62a82a872426 --- /dev/null +++ b/pac/atsamc21g/src/tcc0/cc_dith6_mode.rs @@ -0,0 +1,141 @@ +#[doc = "Register `CC_DITH6_MODE[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CC_DITH6_MODE[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHER` reader - Dithering Cycle Number"] +pub struct DITHER_R(crate::FieldReader); +impl DITHER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHER` writer - Dithering Cycle Number"] +pub struct DITHER_W<'a> { + w: &'a mut W, +} +impl<'a> DITHER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +#[doc = "Field `CC` reader - Channel Compare/Capture Value"] +pub struct CC_R(crate::FieldReader); +impl CC_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC` writer - Channel Compare/Capture Value"] +pub struct CC_W<'a> { + w: &'a mut W, +} +impl<'a> CC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0003_ffff << 6)) | ((value as u32 & 0x0003_ffff) << 6); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&self) -> DITHER_R { + DITHER_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&self) -> CC_R { + CC_R::new(((self.bits >> 6) & 0x0003_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:5 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&mut self) -> DITHER_W { + DITHER_W { w: self } + } + #[doc = "Bits 6:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&mut self) -> CC_W { + CC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc_dith6_mode](index.html) module"] +pub struct CC_DITH6_MODE_SPEC; +impl crate::RegisterSpec for CC_DITH6_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cc_dith6_mode::R](R) reader structure"] +impl crate::Readable for CC_DITH6_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cc_dith6_mode::W](W) writer structure"] +impl crate::Writable for CC_DITH6_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CC_DITH6_MODE[%s] +to value 0"] +impl crate::Resettable for CC_DITH6_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/tcc0/ccbuf.rs b/pac/atsamc21g/src/tcc0/ccbuf.rs new file mode 100644 index 000000000000..a4db1135f095 --- /dev/null +++ b/pac/atsamc21g/src/tcc0/ccbuf.rs @@ -0,0 +1,104 @@ +#[doc = "Register `CCBUF[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CCBUF[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CCBUF` reader - Channel Compare/Capture Buffer Value"] +pub struct CCBUF_R(crate::FieldReader); +impl CCBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CCBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUF` writer - Channel Compare/Capture Buffer Value"] +pub struct CCBUF_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccbuf(&self) -> CCBUF_R { + CCBUF_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccbuf(&mut self) -> CCBUF_W { + CCBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccbuf](index.html) module"] +pub struct CCBUF_SPEC; +impl crate::RegisterSpec for CCBUF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ccbuf::R](R) reader structure"] +impl crate::Readable for CCBUF_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ccbuf::W](W) writer structure"] +impl crate::Writable for CCBUF_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CCBUF[%s] +to value 0"] +impl crate::Resettable for CCBUF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/tcc0/ccbuf_dith4_mode.rs b/pac/atsamc21g/src/tcc0/ccbuf_dith4_mode.rs new file mode 100644 index 000000000000..dfa16e936175 --- /dev/null +++ b/pac/atsamc21g/src/tcc0/ccbuf_dith4_mode.rs @@ -0,0 +1,141 @@ +#[doc = "Register `CCBUF_DITH4_MODE[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CCBUF_DITH4_MODE[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CCBUF` reader - Channel Compare/Capture Buffer Value"] +pub struct CCBUF_R(crate::FieldReader); +impl CCBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CCBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUF` writer - Channel Compare/Capture Buffer Value"] +pub struct CCBUF_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Field `DITHERBUF` reader - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_R(crate::FieldReader); +impl DITHERBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + DITHERBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHERBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHERBUF` writer - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_W<'a> { + w: &'a mut W, +} +impl<'a> DITHERBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x000f_ffff << 4)) | ((value as u32 & 0x000f_ffff) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccbuf(&self) -> CCBUF_R { + CCBUF_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:23 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&self) -> DITHERBUF_R { + DITHERBUF_R::new(((self.bits >> 4) & 0x000f_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:3 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccbuf(&mut self) -> CCBUF_W { + CCBUF_W { w: self } + } + #[doc = "Bits 4:23 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&mut self) -> DITHERBUF_W { + DITHERBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccbuf_dith4_mode](index.html) module"] +pub struct CCBUF_DITH4_MODE_SPEC; +impl crate::RegisterSpec for CCBUF_DITH4_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ccbuf_dith4_mode::R](R) reader structure"] +impl crate::Readable for CCBUF_DITH4_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ccbuf_dith4_mode::W](W) writer structure"] +impl crate::Writable for CCBUF_DITH4_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CCBUF_DITH4_MODE[%s] +to value 0"] +impl crate::Resettable for CCBUF_DITH4_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/tcc0/ccbuf_dith5_mode.rs b/pac/atsamc21g/src/tcc0/ccbuf_dith5_mode.rs new file mode 100644 index 000000000000..0c78ba3303c0 --- /dev/null +++ b/pac/atsamc21g/src/tcc0/ccbuf_dith5_mode.rs @@ -0,0 +1,141 @@ +#[doc = "Register `CCBUF_DITH5_MODE[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CCBUF_DITH5_MODE[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHERBUF` reader - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_R(crate::FieldReader); +impl DITHERBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHERBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHERBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHERBUF` writer - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_W<'a> { + w: &'a mut W, +} +impl<'a> DITHERBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f); + self.w + } +} +#[doc = "Field `CCBUF` reader - Channel Compare/Capture Buffer Value"] +pub struct CCBUF_R(crate::FieldReader); +impl CCBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CCBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUF` writer - Channel Compare/Capture Buffer Value"] +pub struct CCBUF_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0007_ffff << 5)) | ((value as u32 & 0x0007_ffff) << 5); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&self) -> DITHERBUF_R { + DITHERBUF_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:23 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccbuf(&self) -> CCBUF_R { + CCBUF_R::new(((self.bits >> 5) & 0x0007_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:4 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&mut self) -> DITHERBUF_W { + DITHERBUF_W { w: self } + } + #[doc = "Bits 5:23 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccbuf(&mut self) -> CCBUF_W { + CCBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccbuf_dith5_mode](index.html) module"] +pub struct CCBUF_DITH5_MODE_SPEC; +impl crate::RegisterSpec for CCBUF_DITH5_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ccbuf_dith5_mode::R](R) reader structure"] +impl crate::Readable for CCBUF_DITH5_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ccbuf_dith5_mode::W](W) writer structure"] +impl crate::Writable for CCBUF_DITH5_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CCBUF_DITH5_MODE[%s] +to value 0"] +impl crate::Resettable for CCBUF_DITH5_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/tcc0/ccbuf_dith6_mode.rs b/pac/atsamc21g/src/tcc0/ccbuf_dith6_mode.rs new file mode 100644 index 000000000000..8d19b8a9e595 --- /dev/null +++ b/pac/atsamc21g/src/tcc0/ccbuf_dith6_mode.rs @@ -0,0 +1,141 @@ +#[doc = "Register `CCBUF_DITH6_MODE[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CCBUF_DITH6_MODE[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHERBUF` reader - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_R(crate::FieldReader); +impl DITHERBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHERBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHERBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHERBUF` writer - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_W<'a> { + w: &'a mut W, +} +impl<'a> DITHERBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +#[doc = "Field `CCBUF` reader - Channel Compare/Capture Buffer Value"] +pub struct CCBUF_R(crate::FieldReader); +impl CCBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CCBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUF` writer - Channel Compare/Capture Buffer Value"] +pub struct CCBUF_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0003_ffff << 6)) | ((value as u32 & 0x0003_ffff) << 6); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&self) -> DITHERBUF_R { + DITHERBUF_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:23 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccbuf(&self) -> CCBUF_R { + CCBUF_R::new(((self.bits >> 6) & 0x0003_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:5 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&mut self) -> DITHERBUF_W { + DITHERBUF_W { w: self } + } + #[doc = "Bits 6:23 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccbuf(&mut self) -> CCBUF_W { + CCBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccbuf_dith6_mode](index.html) module"] +pub struct CCBUF_DITH6_MODE_SPEC; +impl crate::RegisterSpec for CCBUF_DITH6_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ccbuf_dith6_mode::R](R) reader structure"] +impl crate::Readable for CCBUF_DITH6_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ccbuf_dith6_mode::W](W) writer structure"] +impl crate::Writable for CCBUF_DITH6_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CCBUF_DITH6_MODE[%s] +to value 0"] +impl crate::Resettable for CCBUF_DITH6_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/tcc0/count.rs b/pac/atsamc21g/src/tcc0/count.rs new file mode 100644 index 000000000000..7628f2c0d5e1 --- /dev/null +++ b/pac/atsamc21g/src/tcc0/count.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Count\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count](index.html) module"] +pub struct COUNT_SPEC; +impl crate::RegisterSpec for COUNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [count::R](R) reader structure"] +impl crate::Readable for COUNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count::W](W) writer structure"] +impl crate::Writable for COUNT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT to value 0"] +impl crate::Resettable for COUNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/tcc0/count_dith4_mode.rs b/pac/atsamc21g/src/tcc0/count_dith4_mode.rs new file mode 100644 index 000000000000..fc058ae5efd5 --- /dev/null +++ b/pac/atsamc21g/src/tcc0/count_dith4_mode.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT_DITH4_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT_DITH4_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x000f_ffff << 4)) | ((value as u32 & 0x000f_ffff) << 4); + self.w + } +} +impl R { + #[doc = "Bits 4:23 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 4) & 0x000f_ffff) as u32) + } +} +impl W { + #[doc = "Bits 4:23 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Count\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count_dith4_mode](index.html) module"] +pub struct COUNT_DITH4_MODE_SPEC; +impl crate::RegisterSpec for COUNT_DITH4_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [count_dith4_mode::R](R) reader structure"] +impl crate::Readable for COUNT_DITH4_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count_dith4_mode::W](W) writer structure"] +impl crate::Writable for COUNT_DITH4_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT_DITH4_MODE to value 0"] +impl crate::Resettable for COUNT_DITH4_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/tcc0/count_dith5_mode.rs b/pac/atsamc21g/src/tcc0/count_dith5_mode.rs new file mode 100644 index 000000000000..e66e20310726 --- /dev/null +++ b/pac/atsamc21g/src/tcc0/count_dith5_mode.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT_DITH5_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT_DITH5_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0007_ffff << 5)) | ((value as u32 & 0x0007_ffff) << 5); + self.w + } +} +impl R { + #[doc = "Bits 5:23 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 5) & 0x0007_ffff) as u32) + } +} +impl W { + #[doc = "Bits 5:23 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Count\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count_dith5_mode](index.html) module"] +pub struct COUNT_DITH5_MODE_SPEC; +impl crate::RegisterSpec for COUNT_DITH5_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [count_dith5_mode::R](R) reader structure"] +impl crate::Readable for COUNT_DITH5_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count_dith5_mode::W](W) writer structure"] +impl crate::Writable for COUNT_DITH5_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT_DITH5_MODE to value 0"] +impl crate::Resettable for COUNT_DITH5_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/tcc0/count_dith6_mode.rs b/pac/atsamc21g/src/tcc0/count_dith6_mode.rs new file mode 100644 index 000000000000..5410fc6c9459 --- /dev/null +++ b/pac/atsamc21g/src/tcc0/count_dith6_mode.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT_DITH6_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT_DITH6_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0003_ffff << 6)) | ((value as u32 & 0x0003_ffff) << 6); + self.w + } +} +impl R { + #[doc = "Bits 6:23 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 6) & 0x0003_ffff) as u32) + } +} +impl W { + #[doc = "Bits 6:23 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Count\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count_dith6_mode](index.html) module"] +pub struct COUNT_DITH6_MODE_SPEC; +impl crate::RegisterSpec for COUNT_DITH6_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [count_dith6_mode::R](R) reader structure"] +impl crate::Readable for COUNT_DITH6_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count_dith6_mode::W](W) writer structure"] +impl crate::Writable for COUNT_DITH6_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT_DITH6_MODE to value 0"] +impl crate::Resettable for COUNT_DITH6_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/tcc0/ctrla.rs b/pac/atsamc21g/src/tcc0/ctrla.rs new file mode 100644 index 000000000000..b717d1ac6ae0 --- /dev/null +++ b/pac/atsamc21g/src/tcc0/ctrla.rs @@ -0,0 +1,911 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Enhanced Resolution\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum RESOLUTION_A { + #[doc = "0: Dithering is disabled"] + NONE = 0, + #[doc = "1: Dithering is done every 16 PWM frames"] + DITH4 = 1, + #[doc = "2: Dithering is done every 32 PWM frames"] + DITH5 = 2, + #[doc = "3: Dithering is done every 64 PWM frames"] + DITH6 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RESOLUTION_A) -> Self { + variant as _ + } +} +#[doc = "Field `RESOLUTION` reader - Enhanced Resolution"] +pub struct RESOLUTION_R(crate::FieldReader); +impl RESOLUTION_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RESOLUTION_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RESOLUTION_A { + match self.bits { + 0 => RESOLUTION_A::NONE, + 1 => RESOLUTION_A::DITH4, + 2 => RESOLUTION_A::DITH5, + 3 => RESOLUTION_A::DITH6, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == RESOLUTION_A::NONE + } + #[doc = "Checks if the value of the field is `DITH4`"] + #[inline(always)] + pub fn is_dith4(&self) -> bool { + **self == RESOLUTION_A::DITH4 + } + #[doc = "Checks if the value of the field is `DITH5`"] + #[inline(always)] + pub fn is_dith5(&self) -> bool { + **self == RESOLUTION_A::DITH5 + } + #[doc = "Checks if the value of the field is `DITH6`"] + #[inline(always)] + pub fn is_dith6(&self) -> bool { + **self == RESOLUTION_A::DITH6 + } +} +impl core::ops::Deref for RESOLUTION_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESOLUTION` writer - Enhanced Resolution"] +pub struct RESOLUTION_W<'a> { + w: &'a mut W, +} +impl<'a> RESOLUTION_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RESOLUTION_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Dithering is disabled"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(RESOLUTION_A::NONE) + } + #[doc = "Dithering is done every 16 PWM frames"] + #[inline(always)] + pub fn dith4(self) -> &'a mut W { + self.variant(RESOLUTION_A::DITH4) + } + #[doc = "Dithering is done every 32 PWM frames"] + #[inline(always)] + pub fn dith5(self) -> &'a mut W { + self.variant(RESOLUTION_A::DITH5) + } + #[doc = "Dithering is done every 64 PWM frames"] + #[inline(always)] + pub fn dith6(self) -> &'a mut W { + self.variant(RESOLUTION_A::DITH6) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 5)) | ((value as u32 & 0x03) << 5); + self.w + } +} +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: No division"] + DIV1 = 0, + #[doc = "1: Divide by 2"] + DIV2 = 1, + #[doc = "2: Divide by 4"] + DIV4 = 2, + #[doc = "3: Divide by 8"] + DIV8 = 3, + #[doc = "4: Divide by 16"] + DIV16 = 4, + #[doc = "5: Divide by 64"] + DIV64 = 5, + #[doc = "6: Divide by 256"] + DIV256 = 6, + #[doc = "7: Divide by 1024"] + DIV1024 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PRESCALER_A { + match self.bits { + 0 => PRESCALER_A::DIV1, + 1 => PRESCALER_A::DIV2, + 2 => PRESCALER_A::DIV4, + 3 => PRESCALER_A::DIV8, + 4 => PRESCALER_A::DIV16, + 5 => PRESCALER_A::DIV64, + 6 => PRESCALER_A::DIV256, + 7 => PRESCALER_A::DIV1024, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == PRESCALER_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PRESCALER_A::DIV1024 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "No division"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1) + } + #[doc = "Divide by 2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "Divide by 4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "Divide by 8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "Divide by 16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "Divide by 64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "Divide by 256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = "Divide by 1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Prescaler and Counter Synchronization Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCSYNC_A { + #[doc = "0: Reload or reset counter on next GCLK"] + GCLK = 0, + #[doc = "1: Reload or reset counter on next prescaler clock"] + PRESC = 1, + #[doc = "2: Reload or reset counter on next GCLK and reset prescaler counter"] + RESYNC = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCSYNC_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCSYNC` reader - Prescaler and Counter Synchronization Selection"] +pub struct PRESCSYNC_R(crate::FieldReader); +impl PRESCSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCSYNC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCSYNC_A::GCLK), + 1 => Some(PRESCSYNC_A::PRESC), + 2 => Some(PRESCSYNC_A::RESYNC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `GCLK`"] + #[inline(always)] + pub fn is_gclk(&self) -> bool { + **self == PRESCSYNC_A::GCLK + } + #[doc = "Checks if the value of the field is `PRESC`"] + #[inline(always)] + pub fn is_presc(&self) -> bool { + **self == PRESCSYNC_A::PRESC + } + #[doc = "Checks if the value of the field is `RESYNC`"] + #[inline(always)] + pub fn is_resync(&self) -> bool { + **self == PRESCSYNC_A::RESYNC + } +} +impl core::ops::Deref for PRESCSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCSYNC` writer - Prescaler and Counter Synchronization Selection"] +pub struct PRESCSYNC_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCSYNC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCSYNC_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Reload or reset counter on next GCLK"] + #[inline(always)] + pub fn gclk(self) -> &'a mut W { + self.variant(PRESCSYNC_A::GCLK) + } + #[doc = "Reload or reset counter on next prescaler clock"] + #[inline(always)] + pub fn presc(self) -> &'a mut W { + self.variant(PRESCSYNC_A::PRESC) + } + #[doc = "Reload or reset counter on next GCLK and reset prescaler counter"] + #[inline(always)] + pub fn resync(self) -> &'a mut W { + self.variant(PRESCSYNC_A::RESYNC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 12)) | ((value as u32 & 0x03) << 12); + self.w + } +} +#[doc = "Field `ALOCK` reader - Auto Lock"] +pub struct ALOCK_R(crate::FieldReader); +impl ALOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALOCK` writer - Auto Lock"] +pub struct ALOCK_W<'a> { + w: &'a mut W, +} +impl<'a> ALOCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `MSYNC` reader - Master Synchronization (only for TCC Slave Instance)"] +pub struct MSYNC_R(crate::FieldReader); +impl MSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MSYNC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MSYNC` writer - Master Synchronization (only for TCC Slave Instance)"] +pub struct MSYNC_W<'a> { + w: &'a mut W, +} +impl<'a> MSYNC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `DMAOS` reader - DMA One-shot Trigger Mode"] +pub struct DMAOS_R(crate::FieldReader); +impl DMAOS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DMAOS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DMAOS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DMAOS` writer - DMA One-shot Trigger Mode"] +pub struct DMAOS_W<'a> { + w: &'a mut W, +} +impl<'a> DMAOS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `CPTEN0` reader - Capture Channel 0 Enable"] +pub struct CPTEN0_R(crate::FieldReader); +impl CPTEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPTEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CPTEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPTEN0` writer - Capture Channel 0 Enable"] +pub struct CPTEN0_W<'a> { + w: &'a mut W, +} +impl<'a> CPTEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `CPTEN1` reader - Capture Channel 1 Enable"] +pub struct CPTEN1_R(crate::FieldReader); +impl CPTEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPTEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CPTEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPTEN1` writer - Capture Channel 1 Enable"] +pub struct CPTEN1_W<'a> { + w: &'a mut W, +} +impl<'a> CPTEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `CPTEN2` reader - Capture Channel 2 Enable"] +pub struct CPTEN2_R(crate::FieldReader); +impl CPTEN2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPTEN2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CPTEN2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPTEN2` writer - Capture Channel 2 Enable"] +pub struct CPTEN2_W<'a> { + w: &'a mut W, +} +impl<'a> CPTEN2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `CPTEN3` reader - Capture Channel 3 Enable"] +pub struct CPTEN3_R(crate::FieldReader); +impl CPTEN3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPTEN3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CPTEN3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPTEN3` writer - Capture Channel 3 Enable"] +pub struct CPTEN3_W<'a> { + w: &'a mut W, +} +impl<'a> CPTEN3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 5:6 - Enhanced Resolution"] + #[inline(always)] + pub fn resolution(&self) -> RESOLUTION_R { + RESOLUTION_R::new(((self.bits >> 5) & 0x03) as u8) + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 11 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bits 12:13 - Prescaler and Counter Synchronization Selection"] + #[inline(always)] + pub fn prescsync(&self) -> PRESCSYNC_R { + PRESCSYNC_R::new(((self.bits >> 12) & 0x03) as u8) + } + #[doc = "Bit 14 - Auto Lock"] + #[inline(always)] + pub fn alock(&self) -> ALOCK_R { + ALOCK_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Master Synchronization (only for TCC Slave Instance)"] + #[inline(always)] + pub fn msync(&self) -> MSYNC_R { + MSYNC_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 23 - DMA One-shot Trigger Mode"] + #[inline(always)] + pub fn dmaos(&self) -> DMAOS_R { + DMAOS_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn cpten0(&self) -> CPTEN0_R { + CPTEN0_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn cpten1(&self) -> CPTEN1_R { + CPTEN1_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Capture Channel 2 Enable"] + #[inline(always)] + pub fn cpten2(&self) -> CPTEN2_R { + CPTEN2_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Capture Channel 3 Enable"] + #[inline(always)] + pub fn cpten3(&self) -> CPTEN3_R { + CPTEN3_R::new(((self.bits >> 27) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 5:6 - Enhanced Resolution"] + #[inline(always)] + pub fn resolution(&mut self) -> RESOLUTION_W { + RESOLUTION_W { w: self } + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Bit 11 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bits 12:13 - Prescaler and Counter Synchronization Selection"] + #[inline(always)] + pub fn prescsync(&mut self) -> PRESCSYNC_W { + PRESCSYNC_W { w: self } + } + #[doc = "Bit 14 - Auto Lock"] + #[inline(always)] + pub fn alock(&mut self) -> ALOCK_W { + ALOCK_W { w: self } + } + #[doc = "Bit 15 - Master Synchronization (only for TCC Slave Instance)"] + #[inline(always)] + pub fn msync(&mut self) -> MSYNC_W { + MSYNC_W { w: self } + } + #[doc = "Bit 23 - DMA One-shot Trigger Mode"] + #[inline(always)] + pub fn dmaos(&mut self) -> DMAOS_W { + DMAOS_W { w: self } + } + #[doc = "Bit 24 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn cpten0(&mut self) -> CPTEN0_W { + CPTEN0_W { w: self } + } + #[doc = "Bit 25 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn cpten1(&mut self) -> CPTEN1_W { + CPTEN1_W { w: self } + } + #[doc = "Bit 26 - Capture Channel 2 Enable"] + #[inline(always)] + pub fn cpten2(&mut self) -> CPTEN2_W { + CPTEN2_W { w: self } + } + #[doc = "Bit 27 - Capture Channel 3 Enable"] + #[inline(always)] + pub fn cpten3(&mut self) -> CPTEN3_W { + CPTEN3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/tcc0/ctrlbclr.rs b/pac/atsamc21g/src/tcc0/ctrlbclr.rs new file mode 100644 index 000000000000..f96ce81ffde3 --- /dev/null +++ b/pac/atsamc21g/src/tcc0/ctrlbclr.rs @@ -0,0 +1,457 @@ +#[doc = "Register `CTRLBCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Counter Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `LUPD` reader - Lock Update"] +pub struct LUPD_R(crate::FieldReader); +impl LUPD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LUPD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LUPD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LUPD` writer - Lock Update"] +pub struct LUPD_W<'a> { + w: &'a mut W, +} +impl<'a> LUPD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ONESHOT` reader - One-Shot"] +pub struct ONESHOT_R(crate::FieldReader); +impl ONESHOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONESHOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONESHOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONESHOT` writer - One-Shot"] +pub struct ONESHOT_W<'a> { + w: &'a mut W, +} +impl<'a> ONESHOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Ramp Index Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum IDXCMD_A { + #[doc = "0: Command disabled: Index toggles between cycles A and B"] + DISABLE = 0, + #[doc = "1: Set index: cycle B will be forced in the next cycle"] + SET = 1, + #[doc = "2: Clear index: cycle A will be forced in the next cycle"] + CLEAR = 2, + #[doc = "3: Hold index: the next cycle will be the same as the current cycle"] + HOLD = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: IDXCMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `IDXCMD` reader - Ramp Index Command"] +pub struct IDXCMD_R(crate::FieldReader); +impl IDXCMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + IDXCMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> IDXCMD_A { + match self.bits { + 0 => IDXCMD_A::DISABLE, + 1 => IDXCMD_A::SET, + 2 => IDXCMD_A::CLEAR, + 3 => IDXCMD_A::HOLD, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == IDXCMD_A::DISABLE + } + #[doc = "Checks if the value of the field is `SET`"] + #[inline(always)] + pub fn is_set(&self) -> bool { + **self == IDXCMD_A::SET + } + #[doc = "Checks if the value of the field is `CLEAR`"] + #[inline(always)] + pub fn is_clear(&self) -> bool { + **self == IDXCMD_A::CLEAR + } + #[doc = "Checks if the value of the field is `HOLD`"] + #[inline(always)] + pub fn is_hold(&self) -> bool { + **self == IDXCMD_A::HOLD + } +} +impl core::ops::Deref for IDXCMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IDXCMD` writer - Ramp Index Command"] +pub struct IDXCMD_W<'a> { + w: &'a mut W, +} +impl<'a> IDXCMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: IDXCMD_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Command disabled: Index toggles between cycles A and B"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(IDXCMD_A::DISABLE) + } + #[doc = "Set index: cycle B will be forced in the next cycle"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(IDXCMD_A::SET) + } + #[doc = "Clear index: cycle A will be forced in the next cycle"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(IDXCMD_A::CLEAR) + } + #[doc = "Hold index: the next cycle will be the same as the current cycle"] + #[inline(always)] + pub fn hold(self) -> &'a mut W { + self.variant(IDXCMD_A::HOLD) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 3)) | ((value as u8 & 0x03) << 3); + self.w + } +} +#[doc = "TCC Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Clear start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force stop"] + STOP = 2, + #[doc = "3: Force update or double buffered registers"] + UPDATE = 3, + #[doc = "4: Force COUNT read synchronization"] + READSYNC = 4, + #[doc = "5: One-shot DMA trigger"] + DMAOS = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - TCC Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NONE), + 1 => Some(CMD_A::RETRIGGER), + 2 => Some(CMD_A::STOP), + 3 => Some(CMD_A::UPDATE), + 4 => Some(CMD_A::READSYNC), + 5 => Some(CMD_A::DMAOS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == CMD_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == CMD_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == CMD_A::STOP + } + #[doc = "Checks if the value of the field is `UPDATE`"] + #[inline(always)] + pub fn is_update(&self) -> bool { + **self == CMD_A::UPDATE + } + #[doc = "Checks if the value of the field is `READSYNC`"] + #[inline(always)] + pub fn is_readsync(&self) -> bool { + **self == CMD_A::READSYNC + } + #[doc = "Checks if the value of the field is `DMAOS`"] + #[inline(always)] + pub fn is_dmaos(&self) -> bool { + **self == CMD_A::DMAOS + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - TCC Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMD_A::NONE) + } + #[doc = "Clear start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMD_A::RETRIGGER) + } + #[doc = "Force stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMD_A::STOP) + } + #[doc = "Force update or double buffered registers"] + #[inline(always)] + pub fn update(self) -> &'a mut W { + self.variant(CMD_A::UPDATE) + } + #[doc = "Force COUNT read synchronization"] + #[inline(always)] + pub fn readsync(self) -> &'a mut W { + self.variant(CMD_A::READSYNC) + } + #[doc = "One-shot DMA trigger"] + #[inline(always)] + pub fn dmaos(self) -> &'a mut W { + self.variant(CMD_A::DMAOS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 5)) | ((value as u8 & 0x07) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&self) -> LUPD_R { + LUPD_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - One-Shot"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 3:4 - Ramp Index Command"] + #[inline(always)] + pub fn idxcmd(&self) -> IDXCMD_R { + IDXCMD_R::new(((self.bits >> 3) & 0x03) as u8) + } + #[doc = "Bits 5:7 - TCC Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 5) & 0x07) as u8) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&mut self) -> LUPD_W { + LUPD_W { w: self } + } + #[doc = "Bit 2 - One-Shot"] + #[inline(always)] + pub fn oneshot(&mut self) -> ONESHOT_W { + ONESHOT_W { w: self } + } + #[doc = "Bits 3:4 - Ramp Index Command"] + #[inline(always)] + pub fn idxcmd(&mut self) -> IDXCMD_W { + IDXCMD_W { w: self } + } + #[doc = "Bits 5:7 - TCC Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbclr](index.html) module"] +pub struct CTRLBCLR_SPEC; +impl crate::RegisterSpec for CTRLBCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbclr::R](R) reader structure"] +impl crate::Readable for CTRLBCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbclr::W](W) writer structure"] +impl crate::Writable for CTRLBCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLBCLR to value 0"] +impl crate::Resettable for CTRLBCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/tcc0/ctrlbset.rs b/pac/atsamc21g/src/tcc0/ctrlbset.rs new file mode 100644 index 000000000000..7002dd71efe7 --- /dev/null +++ b/pac/atsamc21g/src/tcc0/ctrlbset.rs @@ -0,0 +1,457 @@ +#[doc = "Register `CTRLBSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Counter Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `LUPD` reader - Lock Update"] +pub struct LUPD_R(crate::FieldReader); +impl LUPD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LUPD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LUPD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LUPD` writer - Lock Update"] +pub struct LUPD_W<'a> { + w: &'a mut W, +} +impl<'a> LUPD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ONESHOT` reader - One-Shot"] +pub struct ONESHOT_R(crate::FieldReader); +impl ONESHOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONESHOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONESHOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONESHOT` writer - One-Shot"] +pub struct ONESHOT_W<'a> { + w: &'a mut W, +} +impl<'a> ONESHOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Ramp Index Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum IDXCMD_A { + #[doc = "0: Command disabled: Index toggles between cycles A and B"] + DISABLE = 0, + #[doc = "1: Set index: cycle B will be forced in the next cycle"] + SET = 1, + #[doc = "2: Clear index: cycle A will be forced in the next cycle"] + CLEAR = 2, + #[doc = "3: Hold index: the next cycle will be the same as the current cycle"] + HOLD = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: IDXCMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `IDXCMD` reader - Ramp Index Command"] +pub struct IDXCMD_R(crate::FieldReader); +impl IDXCMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + IDXCMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> IDXCMD_A { + match self.bits { + 0 => IDXCMD_A::DISABLE, + 1 => IDXCMD_A::SET, + 2 => IDXCMD_A::CLEAR, + 3 => IDXCMD_A::HOLD, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == IDXCMD_A::DISABLE + } + #[doc = "Checks if the value of the field is `SET`"] + #[inline(always)] + pub fn is_set(&self) -> bool { + **self == IDXCMD_A::SET + } + #[doc = "Checks if the value of the field is `CLEAR`"] + #[inline(always)] + pub fn is_clear(&self) -> bool { + **self == IDXCMD_A::CLEAR + } + #[doc = "Checks if the value of the field is `HOLD`"] + #[inline(always)] + pub fn is_hold(&self) -> bool { + **self == IDXCMD_A::HOLD + } +} +impl core::ops::Deref for IDXCMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IDXCMD` writer - Ramp Index Command"] +pub struct IDXCMD_W<'a> { + w: &'a mut W, +} +impl<'a> IDXCMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: IDXCMD_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Command disabled: Index toggles between cycles A and B"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(IDXCMD_A::DISABLE) + } + #[doc = "Set index: cycle B will be forced in the next cycle"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(IDXCMD_A::SET) + } + #[doc = "Clear index: cycle A will be forced in the next cycle"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(IDXCMD_A::CLEAR) + } + #[doc = "Hold index: the next cycle will be the same as the current cycle"] + #[inline(always)] + pub fn hold(self) -> &'a mut W { + self.variant(IDXCMD_A::HOLD) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 3)) | ((value as u8 & 0x03) << 3); + self.w + } +} +#[doc = "TCC Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Clear start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force stop"] + STOP = 2, + #[doc = "3: Force update or double buffered registers"] + UPDATE = 3, + #[doc = "4: Force COUNT read synchronization"] + READSYNC = 4, + #[doc = "5: One-shot DMA trigger"] + DMAOS = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - TCC Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NONE), + 1 => Some(CMD_A::RETRIGGER), + 2 => Some(CMD_A::STOP), + 3 => Some(CMD_A::UPDATE), + 4 => Some(CMD_A::READSYNC), + 5 => Some(CMD_A::DMAOS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == CMD_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == CMD_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == CMD_A::STOP + } + #[doc = "Checks if the value of the field is `UPDATE`"] + #[inline(always)] + pub fn is_update(&self) -> bool { + **self == CMD_A::UPDATE + } + #[doc = "Checks if the value of the field is `READSYNC`"] + #[inline(always)] + pub fn is_readsync(&self) -> bool { + **self == CMD_A::READSYNC + } + #[doc = "Checks if the value of the field is `DMAOS`"] + #[inline(always)] + pub fn is_dmaos(&self) -> bool { + **self == CMD_A::DMAOS + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - TCC Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMD_A::NONE) + } + #[doc = "Clear start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMD_A::RETRIGGER) + } + #[doc = "Force stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMD_A::STOP) + } + #[doc = "Force update or double buffered registers"] + #[inline(always)] + pub fn update(self) -> &'a mut W { + self.variant(CMD_A::UPDATE) + } + #[doc = "Force COUNT read synchronization"] + #[inline(always)] + pub fn readsync(self) -> &'a mut W { + self.variant(CMD_A::READSYNC) + } + #[doc = "One-shot DMA trigger"] + #[inline(always)] + pub fn dmaos(self) -> &'a mut W { + self.variant(CMD_A::DMAOS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 5)) | ((value as u8 & 0x07) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&self) -> LUPD_R { + LUPD_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - One-Shot"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 3:4 - Ramp Index Command"] + #[inline(always)] + pub fn idxcmd(&self) -> IDXCMD_R { + IDXCMD_R::new(((self.bits >> 3) & 0x03) as u8) + } + #[doc = "Bits 5:7 - TCC Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 5) & 0x07) as u8) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&mut self) -> LUPD_W { + LUPD_W { w: self } + } + #[doc = "Bit 2 - One-Shot"] + #[inline(always)] + pub fn oneshot(&mut self) -> ONESHOT_W { + ONESHOT_W { w: self } + } + #[doc = "Bits 3:4 - Ramp Index Command"] + #[inline(always)] + pub fn idxcmd(&mut self) -> IDXCMD_W { + IDXCMD_W { w: self } + } + #[doc = "Bits 5:7 - TCC Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbset](index.html) module"] +pub struct CTRLBSET_SPEC; +impl crate::RegisterSpec for CTRLBSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbset::R](R) reader structure"] +impl crate::Readable for CTRLBSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbset::W](W) writer structure"] +impl crate::Writable for CTRLBSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLBSET to value 0"] +impl crate::Resettable for CTRLBSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/tcc0/dbgctrl.rs b/pac/atsamc21g/src/tcc0/dbgctrl.rs new file mode 100644 index 000000000000..313ebe3f5c18 --- /dev/null +++ b/pac/atsamc21g/src/tcc0/dbgctrl.rs @@ -0,0 +1,160 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Debug Running Mode"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Debug Running Mode"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `FDDBD` reader - Fault Detection on Debug Break Detection"] +pub struct FDDBD_R(crate::FieldReader); +impl FDDBD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FDDBD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FDDBD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FDDBD` writer - Fault Detection on Debug Break Detection"] +pub struct FDDBD_W<'a> { + w: &'a mut W, +} +impl<'a> FDDBD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Running Mode"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 2 - Fault Detection on Debug Break Detection"] + #[inline(always)] + pub fn fddbd(&self) -> FDDBD_R { + FDDBD_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Running Mode"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Bit 2 - Fault Detection on Debug Break Detection"] + #[inline(always)] + pub fn fddbd(&mut self) -> FDDBD_W { + FDDBD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/tcc0/drvctrl.rs b/pac/atsamc21g/src/tcc0/drvctrl.rs new file mode 100644 index 000000000000..316041e1e3be --- /dev/null +++ b/pac/atsamc21g/src/tcc0/drvctrl.rs @@ -0,0 +1,1268 @@ +#[doc = "Register `DRVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DRVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `NRE0` reader - Non-Recoverable State 0 Output Enable"] +pub struct NRE0_R(crate::FieldReader); +impl NRE0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRE0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRE0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRE0` writer - Non-Recoverable State 0 Output Enable"] +pub struct NRE0_W<'a> { + w: &'a mut W, +} +impl<'a> NRE0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `NRE1` reader - Non-Recoverable State 1 Output Enable"] +pub struct NRE1_R(crate::FieldReader); +impl NRE1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRE1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRE1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRE1` writer - Non-Recoverable State 1 Output Enable"] +pub struct NRE1_W<'a> { + w: &'a mut W, +} +impl<'a> NRE1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `NRE2` reader - Non-Recoverable State 2 Output Enable"] +pub struct NRE2_R(crate::FieldReader); +impl NRE2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRE2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRE2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRE2` writer - Non-Recoverable State 2 Output Enable"] +pub struct NRE2_W<'a> { + w: &'a mut W, +} +impl<'a> NRE2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `NRE3` reader - Non-Recoverable State 3 Output Enable"] +pub struct NRE3_R(crate::FieldReader); +impl NRE3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRE3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRE3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRE3` writer - Non-Recoverable State 3 Output Enable"] +pub struct NRE3_W<'a> { + w: &'a mut W, +} +impl<'a> NRE3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `NRE4` reader - Non-Recoverable State 4 Output Enable"] +pub struct NRE4_R(crate::FieldReader); +impl NRE4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRE4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRE4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRE4` writer - Non-Recoverable State 4 Output Enable"] +pub struct NRE4_W<'a> { + w: &'a mut W, +} +impl<'a> NRE4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `NRE5` reader - Non-Recoverable State 5 Output Enable"] +pub struct NRE5_R(crate::FieldReader); +impl NRE5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRE5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRE5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRE5` writer - Non-Recoverable State 5 Output Enable"] +pub struct NRE5_W<'a> { + w: &'a mut W, +} +impl<'a> NRE5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `NRE6` reader - Non-Recoverable State 6 Output Enable"] +pub struct NRE6_R(crate::FieldReader); +impl NRE6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRE6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRE6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRE6` writer - Non-Recoverable State 6 Output Enable"] +pub struct NRE6_W<'a> { + w: &'a mut W, +} +impl<'a> NRE6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `NRE7` reader - Non-Recoverable State 7 Output Enable"] +pub struct NRE7_R(crate::FieldReader); +impl NRE7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRE7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRE7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRE7` writer - Non-Recoverable State 7 Output Enable"] +pub struct NRE7_W<'a> { + w: &'a mut W, +} +impl<'a> NRE7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `NRV0` reader - Non-Recoverable State 0 Output Value"] +pub struct NRV0_R(crate::FieldReader); +impl NRV0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRV0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRV0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRV0` writer - Non-Recoverable State 0 Output Value"] +pub struct NRV0_W<'a> { + w: &'a mut W, +} +impl<'a> NRV0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `NRV1` reader - Non-Recoverable State 1 Output Value"] +pub struct NRV1_R(crate::FieldReader); +impl NRV1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRV1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRV1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRV1` writer - Non-Recoverable State 1 Output Value"] +pub struct NRV1_W<'a> { + w: &'a mut W, +} +impl<'a> NRV1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `NRV2` reader - Non-Recoverable State 2 Output Value"] +pub struct NRV2_R(crate::FieldReader); +impl NRV2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRV2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRV2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRV2` writer - Non-Recoverable State 2 Output Value"] +pub struct NRV2_W<'a> { + w: &'a mut W, +} +impl<'a> NRV2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `NRV3` reader - Non-Recoverable State 3 Output Value"] +pub struct NRV3_R(crate::FieldReader); +impl NRV3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRV3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRV3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRV3` writer - Non-Recoverable State 3 Output Value"] +pub struct NRV3_W<'a> { + w: &'a mut W, +} +impl<'a> NRV3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `NRV4` reader - Non-Recoverable State 4 Output Value"] +pub struct NRV4_R(crate::FieldReader); +impl NRV4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRV4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRV4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRV4` writer - Non-Recoverable State 4 Output Value"] +pub struct NRV4_W<'a> { + w: &'a mut W, +} +impl<'a> NRV4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `NRV5` reader - Non-Recoverable State 5 Output Value"] +pub struct NRV5_R(crate::FieldReader); +impl NRV5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRV5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRV5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRV5` writer - Non-Recoverable State 5 Output Value"] +pub struct NRV5_W<'a> { + w: &'a mut W, +} +impl<'a> NRV5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `NRV6` reader - Non-Recoverable State 6 Output Value"] +pub struct NRV6_R(crate::FieldReader); +impl NRV6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRV6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRV6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRV6` writer - Non-Recoverable State 6 Output Value"] +pub struct NRV6_W<'a> { + w: &'a mut W, +} +impl<'a> NRV6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `NRV7` reader - Non-Recoverable State 7 Output Value"] +pub struct NRV7_R(crate::FieldReader); +impl NRV7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRV7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRV7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRV7` writer - Non-Recoverable State 7 Output Value"] +pub struct NRV7_W<'a> { + w: &'a mut W, +} +impl<'a> NRV7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `INVEN0` reader - Output Waveform 0 Inversion"] +pub struct INVEN0_R(crate::FieldReader); +impl INVEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN0` writer - Output Waveform 0 Inversion"] +pub struct INVEN0_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `INVEN1` reader - Output Waveform 1 Inversion"] +pub struct INVEN1_R(crate::FieldReader); +impl INVEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN1` writer - Output Waveform 1 Inversion"] +pub struct INVEN1_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `INVEN2` reader - Output Waveform 2 Inversion"] +pub struct INVEN2_R(crate::FieldReader); +impl INVEN2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN2` writer - Output Waveform 2 Inversion"] +pub struct INVEN2_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `INVEN3` reader - Output Waveform 3 Inversion"] +pub struct INVEN3_R(crate::FieldReader); +impl INVEN3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN3` writer - Output Waveform 3 Inversion"] +pub struct INVEN3_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `INVEN4` reader - Output Waveform 4 Inversion"] +pub struct INVEN4_R(crate::FieldReader); +impl INVEN4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN4` writer - Output Waveform 4 Inversion"] +pub struct INVEN4_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `INVEN5` reader - Output Waveform 5 Inversion"] +pub struct INVEN5_R(crate::FieldReader); +impl INVEN5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN5` writer - Output Waveform 5 Inversion"] +pub struct INVEN5_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `INVEN6` reader - Output Waveform 6 Inversion"] +pub struct INVEN6_R(crate::FieldReader); +impl INVEN6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN6` writer - Output Waveform 6 Inversion"] +pub struct INVEN6_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `INVEN7` reader - Output Waveform 7 Inversion"] +pub struct INVEN7_R(crate::FieldReader); +impl INVEN7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN7` writer - Output Waveform 7 Inversion"] +pub struct INVEN7_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `FILTERVAL0` reader - Non-Recoverable Fault Input 0 Filter Value"] +pub struct FILTERVAL0_R(crate::FieldReader); +impl FILTERVAL0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FILTERVAL0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTERVAL0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTERVAL0` writer - Non-Recoverable Fault Input 0 Filter Value"] +pub struct FILTERVAL0_W<'a> { + w: &'a mut W, +} +impl<'a> FILTERVAL0_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Field `FILTERVAL1` reader - Non-Recoverable Fault Input 1 Filter Value"] +pub struct FILTERVAL1_R(crate::FieldReader); +impl FILTERVAL1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FILTERVAL1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTERVAL1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTERVAL1` writer - Non-Recoverable Fault Input 1 Filter Value"] +pub struct FILTERVAL1_W<'a> { + w: &'a mut W, +} +impl<'a> FILTERVAL1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 28)) | ((value as u32 & 0x0f) << 28); + self.w + } +} +impl R { + #[doc = "Bit 0 - Non-Recoverable State 0 Output Enable"] + #[inline(always)] + pub fn nre0(&self) -> NRE0_R { + NRE0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Non-Recoverable State 1 Output Enable"] + #[inline(always)] + pub fn nre1(&self) -> NRE1_R { + NRE1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Non-Recoverable State 2 Output Enable"] + #[inline(always)] + pub fn nre2(&self) -> NRE2_R { + NRE2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Non-Recoverable State 3 Output Enable"] + #[inline(always)] + pub fn nre3(&self) -> NRE3_R { + NRE3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Non-Recoverable State 4 Output Enable"] + #[inline(always)] + pub fn nre4(&self) -> NRE4_R { + NRE4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Non-Recoverable State 5 Output Enable"] + #[inline(always)] + pub fn nre5(&self) -> NRE5_R { + NRE5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Non-Recoverable State 6 Output Enable"] + #[inline(always)] + pub fn nre6(&self) -> NRE6_R { + NRE6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Non-Recoverable State 7 Output Enable"] + #[inline(always)] + pub fn nre7(&self) -> NRE7_R { + NRE7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Non-Recoverable State 0 Output Value"] + #[inline(always)] + pub fn nrv0(&self) -> NRV0_R { + NRV0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Non-Recoverable State 1 Output Value"] + #[inline(always)] + pub fn nrv1(&self) -> NRV1_R { + NRV1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Non-Recoverable State 2 Output Value"] + #[inline(always)] + pub fn nrv2(&self) -> NRV2_R { + NRV2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Non-Recoverable State 3 Output Value"] + #[inline(always)] + pub fn nrv3(&self) -> NRV3_R { + NRV3_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Non-Recoverable State 4 Output Value"] + #[inline(always)] + pub fn nrv4(&self) -> NRV4_R { + NRV4_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Non-Recoverable State 5 Output Value"] + #[inline(always)] + pub fn nrv5(&self) -> NRV5_R { + NRV5_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Non-Recoverable State 6 Output Value"] + #[inline(always)] + pub fn nrv6(&self) -> NRV6_R { + NRV6_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Non-Recoverable State 7 Output Value"] + #[inline(always)] + pub fn nrv7(&self) -> NRV7_R { + NRV7_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Output Waveform 0 Inversion"] + #[inline(always)] + pub fn inven0(&self) -> INVEN0_R { + INVEN0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Output Waveform 1 Inversion"] + #[inline(always)] + pub fn inven1(&self) -> INVEN1_R { + INVEN1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Output Waveform 2 Inversion"] + #[inline(always)] + pub fn inven2(&self) -> INVEN2_R { + INVEN2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Output Waveform 3 Inversion"] + #[inline(always)] + pub fn inven3(&self) -> INVEN3_R { + INVEN3_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Output Waveform 4 Inversion"] + #[inline(always)] + pub fn inven4(&self) -> INVEN4_R { + INVEN4_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Output Waveform 5 Inversion"] + #[inline(always)] + pub fn inven5(&self) -> INVEN5_R { + INVEN5_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Output Waveform 6 Inversion"] + #[inline(always)] + pub fn inven6(&self) -> INVEN6_R { + INVEN6_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Output Waveform 7 Inversion"] + #[inline(always)] + pub fn inven7(&self) -> INVEN7_R { + INVEN7_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bits 24:27 - Non-Recoverable Fault Input 0 Filter Value"] + #[inline(always)] + pub fn filterval0(&self) -> FILTERVAL0_R { + FILTERVAL0_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bits 28:31 - Non-Recoverable Fault Input 1 Filter Value"] + #[inline(always)] + pub fn filterval1(&self) -> FILTERVAL1_R { + FILTERVAL1_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bit 0 - Non-Recoverable State 0 Output Enable"] + #[inline(always)] + pub fn nre0(&mut self) -> NRE0_W { + NRE0_W { w: self } + } + #[doc = "Bit 1 - Non-Recoverable State 1 Output Enable"] + #[inline(always)] + pub fn nre1(&mut self) -> NRE1_W { + NRE1_W { w: self } + } + #[doc = "Bit 2 - Non-Recoverable State 2 Output Enable"] + #[inline(always)] + pub fn nre2(&mut self) -> NRE2_W { + NRE2_W { w: self } + } + #[doc = "Bit 3 - Non-Recoverable State 3 Output Enable"] + #[inline(always)] + pub fn nre3(&mut self) -> NRE3_W { + NRE3_W { w: self } + } + #[doc = "Bit 4 - Non-Recoverable State 4 Output Enable"] + #[inline(always)] + pub fn nre4(&mut self) -> NRE4_W { + NRE4_W { w: self } + } + #[doc = "Bit 5 - Non-Recoverable State 5 Output Enable"] + #[inline(always)] + pub fn nre5(&mut self) -> NRE5_W { + NRE5_W { w: self } + } + #[doc = "Bit 6 - Non-Recoverable State 6 Output Enable"] + #[inline(always)] + pub fn nre6(&mut self) -> NRE6_W { + NRE6_W { w: self } + } + #[doc = "Bit 7 - Non-Recoverable State 7 Output Enable"] + #[inline(always)] + pub fn nre7(&mut self) -> NRE7_W { + NRE7_W { w: self } + } + #[doc = "Bit 8 - Non-Recoverable State 0 Output Value"] + #[inline(always)] + pub fn nrv0(&mut self) -> NRV0_W { + NRV0_W { w: self } + } + #[doc = "Bit 9 - Non-Recoverable State 1 Output Value"] + #[inline(always)] + pub fn nrv1(&mut self) -> NRV1_W { + NRV1_W { w: self } + } + #[doc = "Bit 10 - Non-Recoverable State 2 Output Value"] + #[inline(always)] + pub fn nrv2(&mut self) -> NRV2_W { + NRV2_W { w: self } + } + #[doc = "Bit 11 - Non-Recoverable State 3 Output Value"] + #[inline(always)] + pub fn nrv3(&mut self) -> NRV3_W { + NRV3_W { w: self } + } + #[doc = "Bit 12 - Non-Recoverable State 4 Output Value"] + #[inline(always)] + pub fn nrv4(&mut self) -> NRV4_W { + NRV4_W { w: self } + } + #[doc = "Bit 13 - Non-Recoverable State 5 Output Value"] + #[inline(always)] + pub fn nrv5(&mut self) -> NRV5_W { + NRV5_W { w: self } + } + #[doc = "Bit 14 - Non-Recoverable State 6 Output Value"] + #[inline(always)] + pub fn nrv6(&mut self) -> NRV6_W { + NRV6_W { w: self } + } + #[doc = "Bit 15 - Non-Recoverable State 7 Output Value"] + #[inline(always)] + pub fn nrv7(&mut self) -> NRV7_W { + NRV7_W { w: self } + } + #[doc = "Bit 16 - Output Waveform 0 Inversion"] + #[inline(always)] + pub fn inven0(&mut self) -> INVEN0_W { + INVEN0_W { w: self } + } + #[doc = "Bit 17 - Output Waveform 1 Inversion"] + #[inline(always)] + pub fn inven1(&mut self) -> INVEN1_W { + INVEN1_W { w: self } + } + #[doc = "Bit 18 - Output Waveform 2 Inversion"] + #[inline(always)] + pub fn inven2(&mut self) -> INVEN2_W { + INVEN2_W { w: self } + } + #[doc = "Bit 19 - Output Waveform 3 Inversion"] + #[inline(always)] + pub fn inven3(&mut self) -> INVEN3_W { + INVEN3_W { w: self } + } + #[doc = "Bit 20 - Output Waveform 4 Inversion"] + #[inline(always)] + pub fn inven4(&mut self) -> INVEN4_W { + INVEN4_W { w: self } + } + #[doc = "Bit 21 - Output Waveform 5 Inversion"] + #[inline(always)] + pub fn inven5(&mut self) -> INVEN5_W { + INVEN5_W { w: self } + } + #[doc = "Bit 22 - Output Waveform 6 Inversion"] + #[inline(always)] + pub fn inven6(&mut self) -> INVEN6_W { + INVEN6_W { w: self } + } + #[doc = "Bit 23 - Output Waveform 7 Inversion"] + #[inline(always)] + pub fn inven7(&mut self) -> INVEN7_W { + INVEN7_W { w: self } + } + #[doc = "Bits 24:27 - Non-Recoverable Fault Input 0 Filter Value"] + #[inline(always)] + pub fn filterval0(&mut self) -> FILTERVAL0_W { + FILTERVAL0_W { w: self } + } + #[doc = "Bits 28:31 - Non-Recoverable Fault Input 1 Filter Value"] + #[inline(always)] + pub fn filterval1(&mut self) -> FILTERVAL1_W { + FILTERVAL1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Driver Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [drvctrl](index.html) module"] +pub struct DRVCTRL_SPEC; +impl crate::RegisterSpec for DRVCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [drvctrl::R](R) reader structure"] +impl crate::Readable for DRVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [drvctrl::W](W) writer structure"] +impl crate::Writable for DRVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DRVCTRL to value 0"] +impl crate::Resettable for DRVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/tcc0/evctrl.rs b/pac/atsamc21g/src/tcc0/evctrl.rs new file mode 100644 index 000000000000..334a53924d61 --- /dev/null +++ b/pac/atsamc21g/src/tcc0/evctrl.rs @@ -0,0 +1,1211 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Timer/counter Input Event0 Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EVACT0_A { + #[doc = "0: Event action disabled"] + OFF = 0, + #[doc = "1: Start, restart or re-trigger counter on event"] + RETRIGGER = 1, + #[doc = "2: Count on event"] + COUNTEV = 2, + #[doc = "3: Start counter on event"] + START = 3, + #[doc = "4: Increment counter on event"] + INC = 4, + #[doc = "5: Count on active state of asynchronous event"] + COUNT = 5, + #[doc = "6: Stamp capture"] + STAMP = 6, + #[doc = "7: Non-recoverable fault"] + FAULT = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EVACT0_A) -> Self { + variant as _ + } +} +#[doc = "Field `EVACT0` reader - Timer/counter Input Event0 Action"] +pub struct EVACT0_R(crate::FieldReader); +impl EVACT0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVACT0_A { + match self.bits { + 0 => EVACT0_A::OFF, + 1 => EVACT0_A::RETRIGGER, + 2 => EVACT0_A::COUNTEV, + 3 => EVACT0_A::START, + 4 => EVACT0_A::INC, + 5 => EVACT0_A::COUNT, + 6 => EVACT0_A::STAMP, + 7 => EVACT0_A::FAULT, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == EVACT0_A::OFF + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == EVACT0_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `COUNTEV`"] + #[inline(always)] + pub fn is_countev(&self) -> bool { + **self == EVACT0_A::COUNTEV + } + #[doc = "Checks if the value of the field is `START`"] + #[inline(always)] + pub fn is_start(&self) -> bool { + **self == EVACT0_A::START + } + #[doc = "Checks if the value of the field is `INC`"] + #[inline(always)] + pub fn is_inc(&self) -> bool { + **self == EVACT0_A::INC + } + #[doc = "Checks if the value of the field is `COUNT`"] + #[inline(always)] + pub fn is_count(&self) -> bool { + **self == EVACT0_A::COUNT + } + #[doc = "Checks if the value of the field is `STAMP`"] + #[inline(always)] + pub fn is_stamp(&self) -> bool { + **self == EVACT0_A::STAMP + } + #[doc = "Checks if the value of the field is `FAULT`"] + #[inline(always)] + pub fn is_fault(&self) -> bool { + **self == EVACT0_A::FAULT + } +} +impl core::ops::Deref for EVACT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT0` writer - Timer/counter Input Event0 Action"] +pub struct EVACT0_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT0_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EVACT0_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Event action disabled"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(EVACT0_A::OFF) + } + #[doc = "Start, restart or re-trigger counter on event"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(EVACT0_A::RETRIGGER) + } + #[doc = "Count on event"] + #[inline(always)] + pub fn countev(self) -> &'a mut W { + self.variant(EVACT0_A::COUNTEV) + } + #[doc = "Start counter on event"] + #[inline(always)] + pub fn start(self) -> &'a mut W { + self.variant(EVACT0_A::START) + } + #[doc = "Increment counter on event"] + #[inline(always)] + pub fn inc(self) -> &'a mut W { + self.variant(EVACT0_A::INC) + } + #[doc = "Count on active state of asynchronous event"] + #[inline(always)] + pub fn count(self) -> &'a mut W { + self.variant(EVACT0_A::COUNT) + } + #[doc = "Stamp capture"] + #[inline(always)] + pub fn stamp(self) -> &'a mut W { + self.variant(EVACT0_A::STAMP) + } + #[doc = "Non-recoverable fault"] + #[inline(always)] + pub fn fault(self) -> &'a mut W { + self.variant(EVACT0_A::FAULT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Timer/counter Input Event1 Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EVACT1_A { + #[doc = "0: Event action disabled"] + OFF = 0, + #[doc = "1: Re-trigger counter on event"] + RETRIGGER = 1, + #[doc = "2: Direction control"] + DIR = 2, + #[doc = "3: Stop counter on event"] + STOP = 3, + #[doc = "4: Decrement counter on event"] + DEC = 4, + #[doc = "5: Period capture value in CC0 register, pulse width capture value in CC1 register"] + PPW = 5, + #[doc = "6: Period capture value in CC1 register, pulse width capture value in CC0 register"] + PWP = 6, + #[doc = "7: Non-recoverable fault"] + FAULT = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EVACT1_A) -> Self { + variant as _ + } +} +#[doc = "Field `EVACT1` reader - Timer/counter Input Event1 Action"] +pub struct EVACT1_R(crate::FieldReader); +impl EVACT1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT1_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVACT1_A { + match self.bits { + 0 => EVACT1_A::OFF, + 1 => EVACT1_A::RETRIGGER, + 2 => EVACT1_A::DIR, + 3 => EVACT1_A::STOP, + 4 => EVACT1_A::DEC, + 5 => EVACT1_A::PPW, + 6 => EVACT1_A::PWP, + 7 => EVACT1_A::FAULT, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == EVACT1_A::OFF + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == EVACT1_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `DIR`"] + #[inline(always)] + pub fn is_dir(&self) -> bool { + **self == EVACT1_A::DIR + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == EVACT1_A::STOP + } + #[doc = "Checks if the value of the field is `DEC`"] + #[inline(always)] + pub fn is_dec(&self) -> bool { + **self == EVACT1_A::DEC + } + #[doc = "Checks if the value of the field is `PPW`"] + #[inline(always)] + pub fn is_ppw(&self) -> bool { + **self == EVACT1_A::PPW + } + #[doc = "Checks if the value of the field is `PWP`"] + #[inline(always)] + pub fn is_pwp(&self) -> bool { + **self == EVACT1_A::PWP + } + #[doc = "Checks if the value of the field is `FAULT`"] + #[inline(always)] + pub fn is_fault(&self) -> bool { + **self == EVACT1_A::FAULT + } +} +impl core::ops::Deref for EVACT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT1` writer - Timer/counter Input Event1 Action"] +pub struct EVACT1_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT1_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EVACT1_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Event action disabled"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(EVACT1_A::OFF) + } + #[doc = "Re-trigger counter on event"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(EVACT1_A::RETRIGGER) + } + #[doc = "Direction control"] + #[inline(always)] + pub fn dir(self) -> &'a mut W { + self.variant(EVACT1_A::DIR) + } + #[doc = "Stop counter on event"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(EVACT1_A::STOP) + } + #[doc = "Decrement counter on event"] + #[inline(always)] + pub fn dec(self) -> &'a mut W { + self.variant(EVACT1_A::DEC) + } + #[doc = "Period capture value in CC0 register, pulse width capture value in CC1 register"] + #[inline(always)] + pub fn ppw(self) -> &'a mut W { + self.variant(EVACT1_A::PPW) + } + #[doc = "Period capture value in CC1 register, pulse width capture value in CC0 register"] + #[inline(always)] + pub fn pwp(self) -> &'a mut W { + self.variant(EVACT1_A::PWP) + } + #[doc = "Non-recoverable fault"] + #[inline(always)] + pub fn fault(self) -> &'a mut W { + self.variant(EVACT1_A::FAULT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 3)) | ((value as u32 & 0x07) << 3); + self.w + } +} +#[doc = "Timer/counter Output Event Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CNTSEL_A { + #[doc = "0: An interrupt/event is generated when a new counter cycle starts"] + START = 0, + #[doc = "1: An interrupt/event is generated when a counter cycle ends"] + END = 1, + #[doc = "2: An interrupt/event is generated when a counter cycle ends, except for the first and last cycles"] + BETWEEN = 2, + #[doc = "3: An interrupt/event is generated when a new counter cycle starts or a counter cycle ends"] + BOUNDARY = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CNTSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `CNTSEL` reader - Timer/counter Output Event Mode"] +pub struct CNTSEL_R(crate::FieldReader); +impl CNTSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CNTSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CNTSEL_A { + match self.bits { + 0 => CNTSEL_A::START, + 1 => CNTSEL_A::END, + 2 => CNTSEL_A::BETWEEN, + 3 => CNTSEL_A::BOUNDARY, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `START`"] + #[inline(always)] + pub fn is_start(&self) -> bool { + **self == CNTSEL_A::START + } + #[doc = "Checks if the value of the field is `END`"] + #[inline(always)] + pub fn is_end(&self) -> bool { + **self == CNTSEL_A::END + } + #[doc = "Checks if the value of the field is `BETWEEN`"] + #[inline(always)] + pub fn is_between(&self) -> bool { + **self == CNTSEL_A::BETWEEN + } + #[doc = "Checks if the value of the field is `BOUNDARY`"] + #[inline(always)] + pub fn is_boundary(&self) -> bool { + **self == CNTSEL_A::BOUNDARY + } +} +impl core::ops::Deref for CNTSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CNTSEL` writer - Timer/counter Output Event Mode"] +pub struct CNTSEL_W<'a> { + w: &'a mut W, +} +impl<'a> CNTSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CNTSEL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "An interrupt/event is generated when a new counter cycle starts"] + #[inline(always)] + pub fn start(self) -> &'a mut W { + self.variant(CNTSEL_A::START) + } + #[doc = "An interrupt/event is generated when a counter cycle ends"] + #[inline(always)] + pub fn end(self) -> &'a mut W { + self.variant(CNTSEL_A::END) + } + #[doc = "An interrupt/event is generated when a counter cycle ends, except for the first and last cycles"] + #[inline(always)] + pub fn between(self) -> &'a mut W { + self.variant(CNTSEL_A::BETWEEN) + } + #[doc = "An interrupt/event is generated when a new counter cycle starts or a counter cycle ends"] + #[inline(always)] + pub fn boundary(self) -> &'a mut W { + self.variant(CNTSEL_A::BOUNDARY) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 6)) | ((value as u32 & 0x03) << 6); + self.w + } +} +#[doc = "Field `OVFEO` reader - Overflow/Underflow Output Event Enable"] +pub struct OVFEO_R(crate::FieldReader); +impl OVFEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVFEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVFEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVFEO` writer - Overflow/Underflow Output Event Enable"] +pub struct OVFEO_W<'a> { + w: &'a mut W, +} +impl<'a> OVFEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `TRGEO` reader - Retrigger Output Event Enable"] +pub struct TRGEO_R(crate::FieldReader); +impl TRGEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRGEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRGEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRGEO` writer - Retrigger Output Event Enable"] +pub struct TRGEO_W<'a> { + w: &'a mut W, +} +impl<'a> TRGEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `CNTEO` reader - Timer/counter Output Event Enable"] +pub struct CNTEO_R(crate::FieldReader); +impl CNTEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CNTEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CNTEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CNTEO` writer - Timer/counter Output Event Enable"] +pub struct CNTEO_W<'a> { + w: &'a mut W, +} +impl<'a> CNTEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `TCINV0` reader - Inverted Event 0 Input Enable"] +pub struct TCINV0_R(crate::FieldReader); +impl TCINV0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCINV0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCINV0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCINV0` writer - Inverted Event 0 Input Enable"] +pub struct TCINV0_W<'a> { + w: &'a mut W, +} +impl<'a> TCINV0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `TCINV1` reader - Inverted Event 1 Input Enable"] +pub struct TCINV1_R(crate::FieldReader); +impl TCINV1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCINV1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCINV1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCINV1` writer - Inverted Event 1 Input Enable"] +pub struct TCINV1_W<'a> { + w: &'a mut W, +} +impl<'a> TCINV1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `TCEI0` reader - Timer/counter Event 0 Input Enable"] +pub struct TCEI0_R(crate::FieldReader); +impl TCEI0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCEI0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCEI0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCEI0` writer - Timer/counter Event 0 Input Enable"] +pub struct TCEI0_W<'a> { + w: &'a mut W, +} +impl<'a> TCEI0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `TCEI1` reader - Timer/counter Event 1 Input Enable"] +pub struct TCEI1_R(crate::FieldReader); +impl TCEI1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCEI1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCEI1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCEI1` writer - Timer/counter Event 1 Input Enable"] +pub struct TCEI1_W<'a> { + w: &'a mut W, +} +impl<'a> TCEI1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `MCEI0` reader - Match or Capture Channel 0 Event Input Enable"] +pub struct MCEI0_R(crate::FieldReader); +impl MCEI0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEI0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEI0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEI0` writer - Match or Capture Channel 0 Event Input Enable"] +pub struct MCEI0_W<'a> { + w: &'a mut W, +} +impl<'a> MCEI0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `MCEI1` reader - Match or Capture Channel 1 Event Input Enable"] +pub struct MCEI1_R(crate::FieldReader); +impl MCEI1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEI1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEI1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEI1` writer - Match or Capture Channel 1 Event Input Enable"] +pub struct MCEI1_W<'a> { + w: &'a mut W, +} +impl<'a> MCEI1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `MCEI2` reader - Match or Capture Channel 2 Event Input Enable"] +pub struct MCEI2_R(crate::FieldReader); +impl MCEI2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEI2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEI2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEI2` writer - Match or Capture Channel 2 Event Input Enable"] +pub struct MCEI2_W<'a> { + w: &'a mut W, +} +impl<'a> MCEI2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `MCEI3` reader - Match or Capture Channel 3 Event Input Enable"] +pub struct MCEI3_R(crate::FieldReader); +impl MCEI3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEI3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEI3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEI3` writer - Match or Capture Channel 3 Event Input Enable"] +pub struct MCEI3_W<'a> { + w: &'a mut W, +} +impl<'a> MCEI3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `MCEO0` reader - Match or Capture Channel 0 Event Output Enable"] +pub struct MCEO0_R(crate::FieldReader); +impl MCEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO0` writer - Match or Capture Channel 0 Event Output Enable"] +pub struct MCEO0_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `MCEO1` reader - Match or Capture Channel 1 Event Output Enable"] +pub struct MCEO1_R(crate::FieldReader); +impl MCEO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO1` writer - Match or Capture Channel 1 Event Output Enable"] +pub struct MCEO1_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `MCEO2` reader - Match or Capture Channel 2 Event Output Enable"] +pub struct MCEO2_R(crate::FieldReader); +impl MCEO2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO2` writer - Match or Capture Channel 2 Event Output Enable"] +pub struct MCEO2_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `MCEO3` reader - Match or Capture Channel 3 Event Output Enable"] +pub struct MCEO3_R(crate::FieldReader); +impl MCEO3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO3` writer - Match or Capture Channel 3 Event Output Enable"] +pub struct MCEO3_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Timer/counter Input Event0 Action"] + #[inline(always)] + pub fn evact0(&self) -> EVACT0_R { + EVACT0_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bits 3:5 - Timer/counter Input Event1 Action"] + #[inline(always)] + pub fn evact1(&self) -> EVACT1_R { + EVACT1_R::new(((self.bits >> 3) & 0x07) as u8) + } + #[doc = "Bits 6:7 - Timer/counter Output Event Mode"] + #[inline(always)] + pub fn cntsel(&self) -> CNTSEL_R { + CNTSEL_R::new(((self.bits >> 6) & 0x03) as u8) + } + #[doc = "Bit 8 - Overflow/Underflow Output Event Enable"] + #[inline(always)] + pub fn ovfeo(&self) -> OVFEO_R { + OVFEO_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Retrigger Output Event Enable"] + #[inline(always)] + pub fn trgeo(&self) -> TRGEO_R { + TRGEO_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Timer/counter Output Event Enable"] + #[inline(always)] + pub fn cnteo(&self) -> CNTEO_R { + CNTEO_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 12 - Inverted Event 0 Input Enable"] + #[inline(always)] + pub fn tcinv0(&self) -> TCINV0_R { + TCINV0_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Inverted Event 1 Input Enable"] + #[inline(always)] + pub fn tcinv1(&self) -> TCINV1_R { + TCINV1_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Timer/counter Event 0 Input Enable"] + #[inline(always)] + pub fn tcei0(&self) -> TCEI0_R { + TCEI0_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Timer/counter Event 1 Input Enable"] + #[inline(always)] + pub fn tcei1(&self) -> TCEI1_R { + TCEI1_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Match or Capture Channel 0 Event Input Enable"] + #[inline(always)] + pub fn mcei0(&self) -> MCEI0_R { + MCEI0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Match or Capture Channel 1 Event Input Enable"] + #[inline(always)] + pub fn mcei1(&self) -> MCEI1_R { + MCEI1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Match or Capture Channel 2 Event Input Enable"] + #[inline(always)] + pub fn mcei2(&self) -> MCEI2_R { + MCEI2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Match or Capture Channel 3 Event Input Enable"] + #[inline(always)] + pub fn mcei3(&self) -> MCEI3_R { + MCEI3_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 24 - Match or Capture Channel 0 Event Output Enable"] + #[inline(always)] + pub fn mceo0(&self) -> MCEO0_R { + MCEO0_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Match or Capture Channel 1 Event Output Enable"] + #[inline(always)] + pub fn mceo1(&self) -> MCEO1_R { + MCEO1_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Match or Capture Channel 2 Event Output Enable"] + #[inline(always)] + pub fn mceo2(&self) -> MCEO2_R { + MCEO2_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Match or Capture Channel 3 Event Output Enable"] + #[inline(always)] + pub fn mceo3(&self) -> MCEO3_R { + MCEO3_R::new(((self.bits >> 27) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Timer/counter Input Event0 Action"] + #[inline(always)] + pub fn evact0(&mut self) -> EVACT0_W { + EVACT0_W { w: self } + } + #[doc = "Bits 3:5 - Timer/counter Input Event1 Action"] + #[inline(always)] + pub fn evact1(&mut self) -> EVACT1_W { + EVACT1_W { w: self } + } + #[doc = "Bits 6:7 - Timer/counter Output Event Mode"] + #[inline(always)] + pub fn cntsel(&mut self) -> CNTSEL_W { + CNTSEL_W { w: self } + } + #[doc = "Bit 8 - Overflow/Underflow Output Event Enable"] + #[inline(always)] + pub fn ovfeo(&mut self) -> OVFEO_W { + OVFEO_W { w: self } + } + #[doc = "Bit 9 - Retrigger Output Event Enable"] + #[inline(always)] + pub fn trgeo(&mut self) -> TRGEO_W { + TRGEO_W { w: self } + } + #[doc = "Bit 10 - Timer/counter Output Event Enable"] + #[inline(always)] + pub fn cnteo(&mut self) -> CNTEO_W { + CNTEO_W { w: self } + } + #[doc = "Bit 12 - Inverted Event 0 Input Enable"] + #[inline(always)] + pub fn tcinv0(&mut self) -> TCINV0_W { + TCINV0_W { w: self } + } + #[doc = "Bit 13 - Inverted Event 1 Input Enable"] + #[inline(always)] + pub fn tcinv1(&mut self) -> TCINV1_W { + TCINV1_W { w: self } + } + #[doc = "Bit 14 - Timer/counter Event 0 Input Enable"] + #[inline(always)] + pub fn tcei0(&mut self) -> TCEI0_W { + TCEI0_W { w: self } + } + #[doc = "Bit 15 - Timer/counter Event 1 Input Enable"] + #[inline(always)] + pub fn tcei1(&mut self) -> TCEI1_W { + TCEI1_W { w: self } + } + #[doc = "Bit 16 - Match or Capture Channel 0 Event Input Enable"] + #[inline(always)] + pub fn mcei0(&mut self) -> MCEI0_W { + MCEI0_W { w: self } + } + #[doc = "Bit 17 - Match or Capture Channel 1 Event Input Enable"] + #[inline(always)] + pub fn mcei1(&mut self) -> MCEI1_W { + MCEI1_W { w: self } + } + #[doc = "Bit 18 - Match or Capture Channel 2 Event Input Enable"] + #[inline(always)] + pub fn mcei2(&mut self) -> MCEI2_W { + MCEI2_W { w: self } + } + #[doc = "Bit 19 - Match or Capture Channel 3 Event Input Enable"] + #[inline(always)] + pub fn mcei3(&mut self) -> MCEI3_W { + MCEI3_W { w: self } + } + #[doc = "Bit 24 - Match or Capture Channel 0 Event Output Enable"] + #[inline(always)] + pub fn mceo0(&mut self) -> MCEO0_W { + MCEO0_W { w: self } + } + #[doc = "Bit 25 - Match or Capture Channel 1 Event Output Enable"] + #[inline(always)] + pub fn mceo1(&mut self) -> MCEO1_W { + MCEO1_W { w: self } + } + #[doc = "Bit 26 - Match or Capture Channel 2 Event Output Enable"] + #[inline(always)] + pub fn mceo2(&mut self) -> MCEO2_W { + MCEO2_W { w: self } + } + #[doc = "Bit 27 - Match or Capture Channel 3 Event Output Enable"] + #[inline(always)] + pub fn mceo3(&mut self) -> MCEO3_W { + MCEO3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/tcc0/fctrla.rs b/pac/atsamc21g/src/tcc0/fctrla.rs new file mode 100644 index 000000000000..77c7276fee23 --- /dev/null +++ b/pac/atsamc21g/src/tcc0/fctrla.rs @@ -0,0 +1,940 @@ +#[doc = "Register `FCTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FCTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Fault A Source\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SRC_A { + #[doc = "0: Fault input disabled"] + DISABLE = 0, + #[doc = "1: MCEx (x=0,1) event input"] + ENABLE = 1, + #[doc = "2: Inverted MCEx (x=0,1) event input"] + INVERT = 2, + #[doc = "3: Alternate fault (A or B) state at the end of the previous period"] + ALTFAULT = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SRC_A) -> Self { + variant as _ + } +} +#[doc = "Field `SRC` reader - Fault A Source"] +pub struct SRC_R(crate::FieldReader); +impl SRC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SRC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SRC_A { + match self.bits { + 0 => SRC_A::DISABLE, + 1 => SRC_A::ENABLE, + 2 => SRC_A::INVERT, + 3 => SRC_A::ALTFAULT, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == SRC_A::DISABLE + } + #[doc = "Checks if the value of the field is `ENABLE`"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + **self == SRC_A::ENABLE + } + #[doc = "Checks if the value of the field is `INVERT`"] + #[inline(always)] + pub fn is_invert(&self) -> bool { + **self == SRC_A::INVERT + } + #[doc = "Checks if the value of the field is `ALTFAULT`"] + #[inline(always)] + pub fn is_altfault(&self) -> bool { + **self == SRC_A::ALTFAULT + } +} +impl core::ops::Deref for SRC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SRC` writer - Fault A Source"] +pub struct SRC_W<'a> { + w: &'a mut W, +} +impl<'a> SRC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SRC_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Fault input disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(SRC_A::DISABLE) + } + #[doc = "MCEx (x=0,1) event input"] + #[inline(always)] + pub fn enable(self) -> &'a mut W { + self.variant(SRC_A::ENABLE) + } + #[doc = "Inverted MCEx (x=0,1) event input"] + #[inline(always)] + pub fn invert(self) -> &'a mut W { + self.variant(SRC_A::INVERT) + } + #[doc = "Alternate fault (A or B) state at the end of the previous period"] + #[inline(always)] + pub fn altfault(self) -> &'a mut W { + self.variant(SRC_A::ALTFAULT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u32 & 0x03); + self.w + } +} +#[doc = "Field `KEEP` reader - Fault A Keeper"] +pub struct KEEP_R(crate::FieldReader); +impl KEEP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + KEEP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for KEEP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `KEEP` writer - Fault A Keeper"] +pub struct KEEP_W<'a> { + w: &'a mut W, +} +impl<'a> KEEP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `QUAL` reader - Fault A Qualification"] +pub struct QUAL_R(crate::FieldReader); +impl QUAL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + QUAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for QUAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `QUAL` writer - Fault A Qualification"] +pub struct QUAL_W<'a> { + w: &'a mut W, +} +impl<'a> QUAL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Fault A Blanking Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum BLANK_A { + #[doc = "0: Blanking applied from start of the ramp"] + START = 0, + #[doc = "1: Blanking applied from rising edge of the output waveform"] + RISE = 1, + #[doc = "2: Blanking applied from falling edge of the output waveform"] + FALL = 2, + #[doc = "3: Blanking applied from each toggle of the output waveform"] + BOTH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: BLANK_A) -> Self { + variant as _ + } +} +#[doc = "Field `BLANK` reader - Fault A Blanking Mode"] +pub struct BLANK_R(crate::FieldReader); +impl BLANK_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BLANK_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> BLANK_A { + match self.bits { + 0 => BLANK_A::START, + 1 => BLANK_A::RISE, + 2 => BLANK_A::FALL, + 3 => BLANK_A::BOTH, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `START`"] + #[inline(always)] + pub fn is_start(&self) -> bool { + **self == BLANK_A::START + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == BLANK_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == BLANK_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == BLANK_A::BOTH + } +} +impl core::ops::Deref for BLANK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BLANK` writer - Fault A Blanking Mode"] +pub struct BLANK_W<'a> { + w: &'a mut W, +} +impl<'a> BLANK_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: BLANK_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Blanking applied from start of the ramp"] + #[inline(always)] + pub fn start(self) -> &'a mut W { + self.variant(BLANK_A::START) + } + #[doc = "Blanking applied from rising edge of the output waveform"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(BLANK_A::RISE) + } + #[doc = "Blanking applied from falling edge of the output waveform"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(BLANK_A::FALL) + } + #[doc = "Blanking applied from each toggle of the output waveform"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(BLANK_A::BOTH) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 5)) | ((value as u32 & 0x03) << 5); + self.w + } +} +#[doc = "Field `RESTART` reader - Fault A Restart"] +pub struct RESTART_R(crate::FieldReader); +impl RESTART_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESTART_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESTART_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESTART` writer - Fault A Restart"] +pub struct RESTART_W<'a> { + w: &'a mut W, +} +impl<'a> RESTART_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Fault A Halt Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum HALT_A { + #[doc = "0: Halt action disabled"] + DISABLE = 0, + #[doc = "1: Hardware halt action"] + HW = 1, + #[doc = "2: Software halt action"] + SW = 2, + #[doc = "3: Non-recoverable fault"] + NR = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: HALT_A) -> Self { + variant as _ + } +} +#[doc = "Field `HALT` reader - Fault A Halt Mode"] +pub struct HALT_R(crate::FieldReader); +impl HALT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + HALT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> HALT_A { + match self.bits { + 0 => HALT_A::DISABLE, + 1 => HALT_A::HW, + 2 => HALT_A::SW, + 3 => HALT_A::NR, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == HALT_A::DISABLE + } + #[doc = "Checks if the value of the field is `HW`"] + #[inline(always)] + pub fn is_hw(&self) -> bool { + **self == HALT_A::HW + } + #[doc = "Checks if the value of the field is `SW`"] + #[inline(always)] + pub fn is_sw(&self) -> bool { + **self == HALT_A::SW + } + #[doc = "Checks if the value of the field is `NR`"] + #[inline(always)] + pub fn is_nr(&self) -> bool { + **self == HALT_A::NR + } +} +impl core::ops::Deref for HALT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HALT` writer - Fault A Halt Mode"] +pub struct HALT_W<'a> { + w: &'a mut W, +} +impl<'a> HALT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: HALT_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Halt action disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(HALT_A::DISABLE) + } + #[doc = "Hardware halt action"] + #[inline(always)] + pub fn hw(self) -> &'a mut W { + self.variant(HALT_A::HW) + } + #[doc = "Software halt action"] + #[inline(always)] + pub fn sw(self) -> &'a mut W { + self.variant(HALT_A::SW) + } + #[doc = "Non-recoverable fault"] + #[inline(always)] + pub fn nr(self) -> &'a mut W { + self.variant(HALT_A::NR) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 8)) | ((value as u32 & 0x03) << 8); + self.w + } +} +#[doc = "Fault A Capture Channel\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CHSEL_A { + #[doc = "0: Capture value stored in channel 0"] + CC0 = 0, + #[doc = "1: Capture value stored in channel 1"] + CC1 = 1, + #[doc = "2: Capture value stored in channel 2"] + CC2 = 2, + #[doc = "3: Capture value stored in channel 3"] + CC3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CHSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `CHSEL` reader - Fault A Capture Channel"] +pub struct CHSEL_R(crate::FieldReader); +impl CHSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CHSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CHSEL_A { + match self.bits { + 0 => CHSEL_A::CC0, + 1 => CHSEL_A::CC1, + 2 => CHSEL_A::CC2, + 3 => CHSEL_A::CC3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `CC0`"] + #[inline(always)] + pub fn is_cc0(&self) -> bool { + **self == CHSEL_A::CC0 + } + #[doc = "Checks if the value of the field is `CC1`"] + #[inline(always)] + pub fn is_cc1(&self) -> bool { + **self == CHSEL_A::CC1 + } + #[doc = "Checks if the value of the field is `CC2`"] + #[inline(always)] + pub fn is_cc2(&self) -> bool { + **self == CHSEL_A::CC2 + } + #[doc = "Checks if the value of the field is `CC3`"] + #[inline(always)] + pub fn is_cc3(&self) -> bool { + **self == CHSEL_A::CC3 + } +} +impl core::ops::Deref for CHSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHSEL` writer - Fault A Capture Channel"] +pub struct CHSEL_W<'a> { + w: &'a mut W, +} +impl<'a> CHSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CHSEL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Capture value stored in channel 0"] + #[inline(always)] + pub fn cc0(self) -> &'a mut W { + self.variant(CHSEL_A::CC0) + } + #[doc = "Capture value stored in channel 1"] + #[inline(always)] + pub fn cc1(self) -> &'a mut W { + self.variant(CHSEL_A::CC1) + } + #[doc = "Capture value stored in channel 2"] + #[inline(always)] + pub fn cc2(self) -> &'a mut W { + self.variant(CHSEL_A::CC2) + } + #[doc = "Capture value stored in channel 3"] + #[inline(always)] + pub fn cc3(self) -> &'a mut W { + self.variant(CHSEL_A::CC3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 10)) | ((value as u32 & 0x03) << 10); + self.w + } +} +#[doc = "Fault A Capture Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CAPTURE_A { + #[doc = "0: No capture"] + DISABLE = 0, + #[doc = "1: Capture on fault"] + CAPT = 1, + #[doc = "2: Minimum capture"] + CAPTMIN = 2, + #[doc = "3: Maximum capture"] + CAPTMAX = 3, + #[doc = "4: Minimum local detection"] + LOCMIN = 4, + #[doc = "5: Maximum local detection"] + LOCMAX = 5, + #[doc = "6: Minimum and maximum local detection"] + DERIV0 = 6, + #[doc = "7: Capture with ramp index as MSB value"] + CAPTMARK = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CAPTURE_A) -> Self { + variant as _ + } +} +#[doc = "Field `CAPTURE` reader - Fault A Capture Action"] +pub struct CAPTURE_R(crate::FieldReader); +impl CAPTURE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CAPTURE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CAPTURE_A { + match self.bits { + 0 => CAPTURE_A::DISABLE, + 1 => CAPTURE_A::CAPT, + 2 => CAPTURE_A::CAPTMIN, + 3 => CAPTURE_A::CAPTMAX, + 4 => CAPTURE_A::LOCMIN, + 5 => CAPTURE_A::LOCMAX, + 6 => CAPTURE_A::DERIV0, + 7 => CAPTURE_A::CAPTMARK, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == CAPTURE_A::DISABLE + } + #[doc = "Checks if the value of the field is `CAPT`"] + #[inline(always)] + pub fn is_capt(&self) -> bool { + **self == CAPTURE_A::CAPT + } + #[doc = "Checks if the value of the field is `CAPTMIN`"] + #[inline(always)] + pub fn is_captmin(&self) -> bool { + **self == CAPTURE_A::CAPTMIN + } + #[doc = "Checks if the value of the field is `CAPTMAX`"] + #[inline(always)] + pub fn is_captmax(&self) -> bool { + **self == CAPTURE_A::CAPTMAX + } + #[doc = "Checks if the value of the field is `LOCMIN`"] + #[inline(always)] + pub fn is_locmin(&self) -> bool { + **self == CAPTURE_A::LOCMIN + } + #[doc = "Checks if the value of the field is `LOCMAX`"] + #[inline(always)] + pub fn is_locmax(&self) -> bool { + **self == CAPTURE_A::LOCMAX + } + #[doc = "Checks if the value of the field is `DERIV0`"] + #[inline(always)] + pub fn is_deriv0(&self) -> bool { + **self == CAPTURE_A::DERIV0 + } + #[doc = "Checks if the value of the field is `CAPTMARK`"] + #[inline(always)] + pub fn is_captmark(&self) -> bool { + **self == CAPTURE_A::CAPTMARK + } +} +impl core::ops::Deref for CAPTURE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAPTURE` writer - Fault A Capture Action"] +pub struct CAPTURE_W<'a> { + w: &'a mut W, +} +impl<'a> CAPTURE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CAPTURE_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "No capture"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(CAPTURE_A::DISABLE) + } + #[doc = "Capture on fault"] + #[inline(always)] + pub fn capt(self) -> &'a mut W { + self.variant(CAPTURE_A::CAPT) + } + #[doc = "Minimum capture"] + #[inline(always)] + pub fn captmin(self) -> &'a mut W { + self.variant(CAPTURE_A::CAPTMIN) + } + #[doc = "Maximum capture"] + #[inline(always)] + pub fn captmax(self) -> &'a mut W { + self.variant(CAPTURE_A::CAPTMAX) + } + #[doc = "Minimum local detection"] + #[inline(always)] + pub fn locmin(self) -> &'a mut W { + self.variant(CAPTURE_A::LOCMIN) + } + #[doc = "Maximum local detection"] + #[inline(always)] + pub fn locmax(self) -> &'a mut W { + self.variant(CAPTURE_A::LOCMAX) + } + #[doc = "Minimum and maximum local detection"] + #[inline(always)] + pub fn deriv0(self) -> &'a mut W { + self.variant(CAPTURE_A::DERIV0) + } + #[doc = "Capture with ramp index as MSB value"] + #[inline(always)] + pub fn captmark(self) -> &'a mut W { + self.variant(CAPTURE_A::CAPTMARK) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 12)) | ((value as u32 & 0x07) << 12); + self.w + } +} +#[doc = "Field `BLANKPRESC` reader - Fault A Blanking Prescaler"] +pub struct BLANKPRESC_R(crate::FieldReader); +impl BLANKPRESC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BLANKPRESC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BLANKPRESC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BLANKPRESC` writer - Fault A Blanking Prescaler"] +pub struct BLANKPRESC_W<'a> { + w: &'a mut W, +} +impl<'a> BLANKPRESC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `BLANKVAL` reader - Fault A Blanking Time"] +pub struct BLANKVAL_R(crate::FieldReader); +impl BLANKVAL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BLANKVAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BLANKVAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BLANKVAL` writer - Fault A Blanking Time"] +pub struct BLANKVAL_W<'a> { + w: &'a mut W, +} +impl<'a> BLANKVAL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +#[doc = "Field `FILTERVAL` reader - Fault A Filter Value"] +pub struct FILTERVAL_R(crate::FieldReader); +impl FILTERVAL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FILTERVAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTERVAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTERVAL` writer - Fault A Filter Value"] +pub struct FILTERVAL_W<'a> { + w: &'a mut W, +} +impl<'a> FILTERVAL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Fault A Source"] + #[inline(always)] + pub fn src(&self) -> SRC_R { + SRC_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bit 3 - Fault A Keeper"] + #[inline(always)] + pub fn keep(&self) -> KEEP_R { + KEEP_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Fault A Qualification"] + #[inline(always)] + pub fn qual(&self) -> QUAL_R { + QUAL_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bits 5:6 - Fault A Blanking Mode"] + #[inline(always)] + pub fn blank(&self) -> BLANK_R { + BLANK_R::new(((self.bits >> 5) & 0x03) as u8) + } + #[doc = "Bit 7 - Fault A Restart"] + #[inline(always)] + pub fn restart(&self) -> RESTART_R { + RESTART_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:9 - Fault A Halt Mode"] + #[inline(always)] + pub fn halt(&self) -> HALT_R { + HALT_R::new(((self.bits >> 8) & 0x03) as u8) + } + #[doc = "Bits 10:11 - Fault A Capture Channel"] + #[inline(always)] + pub fn chsel(&self) -> CHSEL_R { + CHSEL_R::new(((self.bits >> 10) & 0x03) as u8) + } + #[doc = "Bits 12:14 - Fault A Capture Action"] + #[inline(always)] + pub fn capture(&self) -> CAPTURE_R { + CAPTURE_R::new(((self.bits >> 12) & 0x07) as u8) + } + #[doc = "Bit 15 - Fault A Blanking Prescaler"] + #[inline(always)] + pub fn blankpresc(&self) -> BLANKPRESC_R { + BLANKPRESC_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:23 - Fault A Blanking Time"] + #[inline(always)] + pub fn blankval(&self) -> BLANKVAL_R { + BLANKVAL_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:27 - Fault A Filter Value"] + #[inline(always)] + pub fn filterval(&self) -> FILTERVAL_R { + FILTERVAL_R::new(((self.bits >> 24) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Fault A Source"] + #[inline(always)] + pub fn src(&mut self) -> SRC_W { + SRC_W { w: self } + } + #[doc = "Bit 3 - Fault A Keeper"] + #[inline(always)] + pub fn keep(&mut self) -> KEEP_W { + KEEP_W { w: self } + } + #[doc = "Bit 4 - Fault A Qualification"] + #[inline(always)] + pub fn qual(&mut self) -> QUAL_W { + QUAL_W { w: self } + } + #[doc = "Bits 5:6 - Fault A Blanking Mode"] + #[inline(always)] + pub fn blank(&mut self) -> BLANK_W { + BLANK_W { w: self } + } + #[doc = "Bit 7 - Fault A Restart"] + #[inline(always)] + pub fn restart(&mut self) -> RESTART_W { + RESTART_W { w: self } + } + #[doc = "Bits 8:9 - Fault A Halt Mode"] + #[inline(always)] + pub fn halt(&mut self) -> HALT_W { + HALT_W { w: self } + } + #[doc = "Bits 10:11 - Fault A Capture Channel"] + #[inline(always)] + pub fn chsel(&mut self) -> CHSEL_W { + CHSEL_W { w: self } + } + #[doc = "Bits 12:14 - Fault A Capture Action"] + #[inline(always)] + pub fn capture(&mut self) -> CAPTURE_W { + CAPTURE_W { w: self } + } + #[doc = "Bit 15 - Fault A Blanking Prescaler"] + #[inline(always)] + pub fn blankpresc(&mut self) -> BLANKPRESC_W { + BLANKPRESC_W { w: self } + } + #[doc = "Bits 16:23 - Fault A Blanking Time"] + #[inline(always)] + pub fn blankval(&mut self) -> BLANKVAL_W { + BLANKVAL_W { w: self } + } + #[doc = "Bits 24:27 - Fault A Filter Value"] + #[inline(always)] + pub fn filterval(&mut self) -> FILTERVAL_W { + FILTERVAL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Recoverable Fault A Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fctrla](index.html) module"] +pub struct FCTRLA_SPEC; +impl crate::RegisterSpec for FCTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [fctrla::R](R) reader structure"] +impl crate::Readable for FCTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [fctrla::W](W) writer structure"] +impl crate::Writable for FCTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets FCTRLA to value 0"] +impl crate::Resettable for FCTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/tcc0/fctrlb.rs b/pac/atsamc21g/src/tcc0/fctrlb.rs new file mode 100644 index 000000000000..4c1dfd1af93d --- /dev/null +++ b/pac/atsamc21g/src/tcc0/fctrlb.rs @@ -0,0 +1,940 @@ +#[doc = "Register `FCTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FCTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Fault B Source\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SRC_A { + #[doc = "0: Fault input disabled"] + DISABLE = 0, + #[doc = "1: MCEx (x=0,1) event input"] + ENABLE = 1, + #[doc = "2: Inverted MCEx (x=0,1) event input"] + INVERT = 2, + #[doc = "3: Alternate fault (A or B) state at the end of the previous period"] + ALTFAULT = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SRC_A) -> Self { + variant as _ + } +} +#[doc = "Field `SRC` reader - Fault B Source"] +pub struct SRC_R(crate::FieldReader); +impl SRC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SRC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SRC_A { + match self.bits { + 0 => SRC_A::DISABLE, + 1 => SRC_A::ENABLE, + 2 => SRC_A::INVERT, + 3 => SRC_A::ALTFAULT, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == SRC_A::DISABLE + } + #[doc = "Checks if the value of the field is `ENABLE`"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + **self == SRC_A::ENABLE + } + #[doc = "Checks if the value of the field is `INVERT`"] + #[inline(always)] + pub fn is_invert(&self) -> bool { + **self == SRC_A::INVERT + } + #[doc = "Checks if the value of the field is `ALTFAULT`"] + #[inline(always)] + pub fn is_altfault(&self) -> bool { + **self == SRC_A::ALTFAULT + } +} +impl core::ops::Deref for SRC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SRC` writer - Fault B Source"] +pub struct SRC_W<'a> { + w: &'a mut W, +} +impl<'a> SRC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SRC_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Fault input disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(SRC_A::DISABLE) + } + #[doc = "MCEx (x=0,1) event input"] + #[inline(always)] + pub fn enable(self) -> &'a mut W { + self.variant(SRC_A::ENABLE) + } + #[doc = "Inverted MCEx (x=0,1) event input"] + #[inline(always)] + pub fn invert(self) -> &'a mut W { + self.variant(SRC_A::INVERT) + } + #[doc = "Alternate fault (A or B) state at the end of the previous period"] + #[inline(always)] + pub fn altfault(self) -> &'a mut W { + self.variant(SRC_A::ALTFAULT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u32 & 0x03); + self.w + } +} +#[doc = "Field `KEEP` reader - Fault B Keeper"] +pub struct KEEP_R(crate::FieldReader); +impl KEEP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + KEEP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for KEEP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `KEEP` writer - Fault B Keeper"] +pub struct KEEP_W<'a> { + w: &'a mut W, +} +impl<'a> KEEP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `QUAL` reader - Fault B Qualification"] +pub struct QUAL_R(crate::FieldReader); +impl QUAL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + QUAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for QUAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `QUAL` writer - Fault B Qualification"] +pub struct QUAL_W<'a> { + w: &'a mut W, +} +impl<'a> QUAL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Fault B Blanking Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum BLANK_A { + #[doc = "0: Blanking applied from start of the ramp"] + START = 0, + #[doc = "1: Blanking applied from rising edge of the output waveform"] + RISE = 1, + #[doc = "2: Blanking applied from falling edge of the output waveform"] + FALL = 2, + #[doc = "3: Blanking applied from each toggle of the output waveform"] + BOTH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: BLANK_A) -> Self { + variant as _ + } +} +#[doc = "Field `BLANK` reader - Fault B Blanking Mode"] +pub struct BLANK_R(crate::FieldReader); +impl BLANK_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BLANK_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> BLANK_A { + match self.bits { + 0 => BLANK_A::START, + 1 => BLANK_A::RISE, + 2 => BLANK_A::FALL, + 3 => BLANK_A::BOTH, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `START`"] + #[inline(always)] + pub fn is_start(&self) -> bool { + **self == BLANK_A::START + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == BLANK_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == BLANK_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == BLANK_A::BOTH + } +} +impl core::ops::Deref for BLANK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BLANK` writer - Fault B Blanking Mode"] +pub struct BLANK_W<'a> { + w: &'a mut W, +} +impl<'a> BLANK_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: BLANK_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Blanking applied from start of the ramp"] + #[inline(always)] + pub fn start(self) -> &'a mut W { + self.variant(BLANK_A::START) + } + #[doc = "Blanking applied from rising edge of the output waveform"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(BLANK_A::RISE) + } + #[doc = "Blanking applied from falling edge of the output waveform"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(BLANK_A::FALL) + } + #[doc = "Blanking applied from each toggle of the output waveform"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(BLANK_A::BOTH) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 5)) | ((value as u32 & 0x03) << 5); + self.w + } +} +#[doc = "Field `RESTART` reader - Fault B Restart"] +pub struct RESTART_R(crate::FieldReader); +impl RESTART_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESTART_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESTART_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESTART` writer - Fault B Restart"] +pub struct RESTART_W<'a> { + w: &'a mut W, +} +impl<'a> RESTART_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Fault B Halt Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum HALT_A { + #[doc = "0: Halt action disabled"] + DISABLE = 0, + #[doc = "1: Hardware halt action"] + HW = 1, + #[doc = "2: Software halt action"] + SW = 2, + #[doc = "3: Non-recoverable fault"] + NR = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: HALT_A) -> Self { + variant as _ + } +} +#[doc = "Field `HALT` reader - Fault B Halt Mode"] +pub struct HALT_R(crate::FieldReader); +impl HALT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + HALT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> HALT_A { + match self.bits { + 0 => HALT_A::DISABLE, + 1 => HALT_A::HW, + 2 => HALT_A::SW, + 3 => HALT_A::NR, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == HALT_A::DISABLE + } + #[doc = "Checks if the value of the field is `HW`"] + #[inline(always)] + pub fn is_hw(&self) -> bool { + **self == HALT_A::HW + } + #[doc = "Checks if the value of the field is `SW`"] + #[inline(always)] + pub fn is_sw(&self) -> bool { + **self == HALT_A::SW + } + #[doc = "Checks if the value of the field is `NR`"] + #[inline(always)] + pub fn is_nr(&self) -> bool { + **self == HALT_A::NR + } +} +impl core::ops::Deref for HALT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HALT` writer - Fault B Halt Mode"] +pub struct HALT_W<'a> { + w: &'a mut W, +} +impl<'a> HALT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: HALT_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Halt action disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(HALT_A::DISABLE) + } + #[doc = "Hardware halt action"] + #[inline(always)] + pub fn hw(self) -> &'a mut W { + self.variant(HALT_A::HW) + } + #[doc = "Software halt action"] + #[inline(always)] + pub fn sw(self) -> &'a mut W { + self.variant(HALT_A::SW) + } + #[doc = "Non-recoverable fault"] + #[inline(always)] + pub fn nr(self) -> &'a mut W { + self.variant(HALT_A::NR) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 8)) | ((value as u32 & 0x03) << 8); + self.w + } +} +#[doc = "Fault B Capture Channel\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CHSEL_A { + #[doc = "0: Capture value stored in channel 0"] + CC0 = 0, + #[doc = "1: Capture value stored in channel 1"] + CC1 = 1, + #[doc = "2: Capture value stored in channel 2"] + CC2 = 2, + #[doc = "3: Capture value stored in channel 3"] + CC3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CHSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `CHSEL` reader - Fault B Capture Channel"] +pub struct CHSEL_R(crate::FieldReader); +impl CHSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CHSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CHSEL_A { + match self.bits { + 0 => CHSEL_A::CC0, + 1 => CHSEL_A::CC1, + 2 => CHSEL_A::CC2, + 3 => CHSEL_A::CC3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `CC0`"] + #[inline(always)] + pub fn is_cc0(&self) -> bool { + **self == CHSEL_A::CC0 + } + #[doc = "Checks if the value of the field is `CC1`"] + #[inline(always)] + pub fn is_cc1(&self) -> bool { + **self == CHSEL_A::CC1 + } + #[doc = "Checks if the value of the field is `CC2`"] + #[inline(always)] + pub fn is_cc2(&self) -> bool { + **self == CHSEL_A::CC2 + } + #[doc = "Checks if the value of the field is `CC3`"] + #[inline(always)] + pub fn is_cc3(&self) -> bool { + **self == CHSEL_A::CC3 + } +} +impl core::ops::Deref for CHSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHSEL` writer - Fault B Capture Channel"] +pub struct CHSEL_W<'a> { + w: &'a mut W, +} +impl<'a> CHSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CHSEL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Capture value stored in channel 0"] + #[inline(always)] + pub fn cc0(self) -> &'a mut W { + self.variant(CHSEL_A::CC0) + } + #[doc = "Capture value stored in channel 1"] + #[inline(always)] + pub fn cc1(self) -> &'a mut W { + self.variant(CHSEL_A::CC1) + } + #[doc = "Capture value stored in channel 2"] + #[inline(always)] + pub fn cc2(self) -> &'a mut W { + self.variant(CHSEL_A::CC2) + } + #[doc = "Capture value stored in channel 3"] + #[inline(always)] + pub fn cc3(self) -> &'a mut W { + self.variant(CHSEL_A::CC3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 10)) | ((value as u32 & 0x03) << 10); + self.w + } +} +#[doc = "Fault B Capture Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CAPTURE_A { + #[doc = "0: No capture"] + DISABLE = 0, + #[doc = "1: Capture on fault"] + CAPT = 1, + #[doc = "2: Minimum capture"] + CAPTMIN = 2, + #[doc = "3: Maximum capture"] + CAPTMAX = 3, + #[doc = "4: Minimum local detection"] + LOCMIN = 4, + #[doc = "5: Maximum local detection"] + LOCMAX = 5, + #[doc = "6: Minimum and maximum local detection"] + DERIV0 = 6, + #[doc = "7: Capture with ramp index as MSB value"] + CAPTMARK = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CAPTURE_A) -> Self { + variant as _ + } +} +#[doc = "Field `CAPTURE` reader - Fault B Capture Action"] +pub struct CAPTURE_R(crate::FieldReader); +impl CAPTURE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CAPTURE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CAPTURE_A { + match self.bits { + 0 => CAPTURE_A::DISABLE, + 1 => CAPTURE_A::CAPT, + 2 => CAPTURE_A::CAPTMIN, + 3 => CAPTURE_A::CAPTMAX, + 4 => CAPTURE_A::LOCMIN, + 5 => CAPTURE_A::LOCMAX, + 6 => CAPTURE_A::DERIV0, + 7 => CAPTURE_A::CAPTMARK, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == CAPTURE_A::DISABLE + } + #[doc = "Checks if the value of the field is `CAPT`"] + #[inline(always)] + pub fn is_capt(&self) -> bool { + **self == CAPTURE_A::CAPT + } + #[doc = "Checks if the value of the field is `CAPTMIN`"] + #[inline(always)] + pub fn is_captmin(&self) -> bool { + **self == CAPTURE_A::CAPTMIN + } + #[doc = "Checks if the value of the field is `CAPTMAX`"] + #[inline(always)] + pub fn is_captmax(&self) -> bool { + **self == CAPTURE_A::CAPTMAX + } + #[doc = "Checks if the value of the field is `LOCMIN`"] + #[inline(always)] + pub fn is_locmin(&self) -> bool { + **self == CAPTURE_A::LOCMIN + } + #[doc = "Checks if the value of the field is `LOCMAX`"] + #[inline(always)] + pub fn is_locmax(&self) -> bool { + **self == CAPTURE_A::LOCMAX + } + #[doc = "Checks if the value of the field is `DERIV0`"] + #[inline(always)] + pub fn is_deriv0(&self) -> bool { + **self == CAPTURE_A::DERIV0 + } + #[doc = "Checks if the value of the field is `CAPTMARK`"] + #[inline(always)] + pub fn is_captmark(&self) -> bool { + **self == CAPTURE_A::CAPTMARK + } +} +impl core::ops::Deref for CAPTURE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAPTURE` writer - Fault B Capture Action"] +pub struct CAPTURE_W<'a> { + w: &'a mut W, +} +impl<'a> CAPTURE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CAPTURE_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "No capture"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(CAPTURE_A::DISABLE) + } + #[doc = "Capture on fault"] + #[inline(always)] + pub fn capt(self) -> &'a mut W { + self.variant(CAPTURE_A::CAPT) + } + #[doc = "Minimum capture"] + #[inline(always)] + pub fn captmin(self) -> &'a mut W { + self.variant(CAPTURE_A::CAPTMIN) + } + #[doc = "Maximum capture"] + #[inline(always)] + pub fn captmax(self) -> &'a mut W { + self.variant(CAPTURE_A::CAPTMAX) + } + #[doc = "Minimum local detection"] + #[inline(always)] + pub fn locmin(self) -> &'a mut W { + self.variant(CAPTURE_A::LOCMIN) + } + #[doc = "Maximum local detection"] + #[inline(always)] + pub fn locmax(self) -> &'a mut W { + self.variant(CAPTURE_A::LOCMAX) + } + #[doc = "Minimum and maximum local detection"] + #[inline(always)] + pub fn deriv0(self) -> &'a mut W { + self.variant(CAPTURE_A::DERIV0) + } + #[doc = "Capture with ramp index as MSB value"] + #[inline(always)] + pub fn captmark(self) -> &'a mut W { + self.variant(CAPTURE_A::CAPTMARK) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 12)) | ((value as u32 & 0x07) << 12); + self.w + } +} +#[doc = "Field `BLANKPRESC` reader - Fault B Blanking Prescaler"] +pub struct BLANKPRESC_R(crate::FieldReader); +impl BLANKPRESC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BLANKPRESC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BLANKPRESC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BLANKPRESC` writer - Fault B Blanking Prescaler"] +pub struct BLANKPRESC_W<'a> { + w: &'a mut W, +} +impl<'a> BLANKPRESC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `BLANKVAL` reader - Fault B Blanking Time"] +pub struct BLANKVAL_R(crate::FieldReader); +impl BLANKVAL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BLANKVAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BLANKVAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BLANKVAL` writer - Fault B Blanking Time"] +pub struct BLANKVAL_W<'a> { + w: &'a mut W, +} +impl<'a> BLANKVAL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +#[doc = "Field `FILTERVAL` reader - Fault B Filter Value"] +pub struct FILTERVAL_R(crate::FieldReader); +impl FILTERVAL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FILTERVAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTERVAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTERVAL` writer - Fault B Filter Value"] +pub struct FILTERVAL_W<'a> { + w: &'a mut W, +} +impl<'a> FILTERVAL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Fault B Source"] + #[inline(always)] + pub fn src(&self) -> SRC_R { + SRC_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bit 3 - Fault B Keeper"] + #[inline(always)] + pub fn keep(&self) -> KEEP_R { + KEEP_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Fault B Qualification"] + #[inline(always)] + pub fn qual(&self) -> QUAL_R { + QUAL_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bits 5:6 - Fault B Blanking Mode"] + #[inline(always)] + pub fn blank(&self) -> BLANK_R { + BLANK_R::new(((self.bits >> 5) & 0x03) as u8) + } + #[doc = "Bit 7 - Fault B Restart"] + #[inline(always)] + pub fn restart(&self) -> RESTART_R { + RESTART_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:9 - Fault B Halt Mode"] + #[inline(always)] + pub fn halt(&self) -> HALT_R { + HALT_R::new(((self.bits >> 8) & 0x03) as u8) + } + #[doc = "Bits 10:11 - Fault B Capture Channel"] + #[inline(always)] + pub fn chsel(&self) -> CHSEL_R { + CHSEL_R::new(((self.bits >> 10) & 0x03) as u8) + } + #[doc = "Bits 12:14 - Fault B Capture Action"] + #[inline(always)] + pub fn capture(&self) -> CAPTURE_R { + CAPTURE_R::new(((self.bits >> 12) & 0x07) as u8) + } + #[doc = "Bit 15 - Fault B Blanking Prescaler"] + #[inline(always)] + pub fn blankpresc(&self) -> BLANKPRESC_R { + BLANKPRESC_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:23 - Fault B Blanking Time"] + #[inline(always)] + pub fn blankval(&self) -> BLANKVAL_R { + BLANKVAL_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:27 - Fault B Filter Value"] + #[inline(always)] + pub fn filterval(&self) -> FILTERVAL_R { + FILTERVAL_R::new(((self.bits >> 24) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Fault B Source"] + #[inline(always)] + pub fn src(&mut self) -> SRC_W { + SRC_W { w: self } + } + #[doc = "Bit 3 - Fault B Keeper"] + #[inline(always)] + pub fn keep(&mut self) -> KEEP_W { + KEEP_W { w: self } + } + #[doc = "Bit 4 - Fault B Qualification"] + #[inline(always)] + pub fn qual(&mut self) -> QUAL_W { + QUAL_W { w: self } + } + #[doc = "Bits 5:6 - Fault B Blanking Mode"] + #[inline(always)] + pub fn blank(&mut self) -> BLANK_W { + BLANK_W { w: self } + } + #[doc = "Bit 7 - Fault B Restart"] + #[inline(always)] + pub fn restart(&mut self) -> RESTART_W { + RESTART_W { w: self } + } + #[doc = "Bits 8:9 - Fault B Halt Mode"] + #[inline(always)] + pub fn halt(&mut self) -> HALT_W { + HALT_W { w: self } + } + #[doc = "Bits 10:11 - Fault B Capture Channel"] + #[inline(always)] + pub fn chsel(&mut self) -> CHSEL_W { + CHSEL_W { w: self } + } + #[doc = "Bits 12:14 - Fault B Capture Action"] + #[inline(always)] + pub fn capture(&mut self) -> CAPTURE_W { + CAPTURE_W { w: self } + } + #[doc = "Bit 15 - Fault B Blanking Prescaler"] + #[inline(always)] + pub fn blankpresc(&mut self) -> BLANKPRESC_W { + BLANKPRESC_W { w: self } + } + #[doc = "Bits 16:23 - Fault B Blanking Time"] + #[inline(always)] + pub fn blankval(&mut self) -> BLANKVAL_W { + BLANKVAL_W { w: self } + } + #[doc = "Bits 24:27 - Fault B Filter Value"] + #[inline(always)] + pub fn filterval(&mut self) -> FILTERVAL_W { + FILTERVAL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Recoverable Fault B Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fctrlb](index.html) module"] +pub struct FCTRLB_SPEC; +impl crate::RegisterSpec for FCTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [fctrlb::R](R) reader structure"] +impl crate::Readable for FCTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [fctrlb::W](W) writer structure"] +impl crate::Writable for FCTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets FCTRLB to value 0"] +impl crate::Resettable for FCTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/tcc0/intenclr.rs b/pac/atsamc21g/src/tcc0/intenclr.rs new file mode 100644 index 000000000000..a227a8405a3c --- /dev/null +++ b/pac/atsamc21g/src/tcc0/intenclr.rs @@ -0,0 +1,724 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `TRG` reader - Retrigger Interrupt Enable"] +pub struct TRG_R(crate::FieldReader); +impl TRG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRG` writer - Retrigger Interrupt Enable"] +pub struct TRG_W<'a> { + w: &'a mut W, +} +impl<'a> TRG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CNT` reader - Counter Interrupt Enable"] +pub struct CNT_R(crate::FieldReader); +impl CNT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CNT` writer - Counter Interrupt Enable"] +pub struct CNT_W<'a> { + w: &'a mut W, +} +impl<'a> CNT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `ERR` reader - Error Interrupt Enable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - Error Interrupt Enable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `UFS` reader - Non-Recoverable Update Fault Interrupt Enable"] +pub struct UFS_R(crate::FieldReader); +impl UFS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UFS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for UFS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `UFS` writer - Non-Recoverable Update Fault Interrupt Enable"] +pub struct UFS_W<'a> { + w: &'a mut W, +} +impl<'a> UFS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `DFS` reader - Non-Recoverable Debug Fault Interrupt Enable"] +pub struct DFS_R(crate::FieldReader); +impl DFS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFS` writer - Non-Recoverable Debug Fault Interrupt Enable"] +pub struct DFS_W<'a> { + w: &'a mut W, +} +impl<'a> DFS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `FAULTA` reader - Recoverable Fault A Interrupt Enable"] +pub struct FAULTA_R(crate::FieldReader); +impl FAULTA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTA` writer - Recoverable Fault A Interrupt Enable"] +pub struct FAULTA_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `FAULTB` reader - Recoverable Fault B Interrupt Enable"] +pub struct FAULTB_R(crate::FieldReader); +impl FAULTB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTB` writer - Recoverable Fault B Interrupt Enable"] +pub struct FAULTB_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `FAULT0` reader - Non-Recoverable Fault 0 Interrupt Enable"] +pub struct FAULT0_R(crate::FieldReader); +impl FAULT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT0` writer - Non-Recoverable Fault 0 Interrupt Enable"] +pub struct FAULT0_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `FAULT1` reader - Non-Recoverable Fault 1 Interrupt Enable"] +pub struct FAULT1_R(crate::FieldReader); +impl FAULT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT1` writer - Non-Recoverable Fault 1 Interrupt Enable"] +pub struct FAULT1_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `MC0` reader - Match or Capture Channel 0 Interrupt Enable"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - Match or Capture Channel 0 Interrupt Enable"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `MC1` reader - Match or Capture Channel 1 Interrupt Enable"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - Match or Capture Channel 1 Interrupt Enable"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `MC2` reader - Match or Capture Channel 2 Interrupt Enable"] +pub struct MC2_R(crate::FieldReader); +impl MC2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC2` writer - Match or Capture Channel 2 Interrupt Enable"] +pub struct MC2_W<'a> { + w: &'a mut W, +} +impl<'a> MC2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `MC3` reader - Match or Capture Channel 3 Interrupt Enable"] +pub struct MC3_R(crate::FieldReader); +impl MC3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC3` writer - Match or Capture Channel 3 Interrupt Enable"] +pub struct MC3_W<'a> { + w: &'a mut W, +} +impl<'a> MC3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +impl R { + #[doc = "Bit 0 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Retrigger Interrupt Enable"] + #[inline(always)] + pub fn trg(&self) -> TRG_R { + TRG_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Counter Interrupt Enable"] + #[inline(always)] + pub fn cnt(&self) -> CNT_R { + CNT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Error Interrupt Enable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 10 - Non-Recoverable Update Fault Interrupt Enable"] + #[inline(always)] + pub fn ufs(&self) -> UFS_R { + UFS_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Non-Recoverable Debug Fault Interrupt Enable"] + #[inline(always)] + pub fn dfs(&self) -> DFS_R { + DFS_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Recoverable Fault A Interrupt Enable"] + #[inline(always)] + pub fn faulta(&self) -> FAULTA_R { + FAULTA_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Recoverable Fault B Interrupt Enable"] + #[inline(always)] + pub fn faultb(&self) -> FAULTB_R { + FAULTB_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Non-Recoverable Fault 0 Interrupt Enable"] + #[inline(always)] + pub fn fault0(&self) -> FAULT0_R { + FAULT0_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Non-Recoverable Fault 1 Interrupt Enable"] + #[inline(always)] + pub fn fault1(&self) -> FAULT1_R { + FAULT1_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Match or Capture Channel 0 Interrupt Enable"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Match or Capture Channel 1 Interrupt Enable"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Match or Capture Channel 2 Interrupt Enable"] + #[inline(always)] + pub fn mc2(&self) -> MC2_R { + MC2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Match or Capture Channel 3 Interrupt Enable"] + #[inline(always)] + pub fn mc3(&self) -> MC3_R { + MC3_R::new(((self.bits >> 19) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - Retrigger Interrupt Enable"] + #[inline(always)] + pub fn trg(&mut self) -> TRG_W { + TRG_W { w: self } + } + #[doc = "Bit 2 - Counter Interrupt Enable"] + #[inline(always)] + pub fn cnt(&mut self) -> CNT_W { + CNT_W { w: self } + } + #[doc = "Bit 3 - Error Interrupt Enable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 10 - Non-Recoverable Update Fault Interrupt Enable"] + #[inline(always)] + pub fn ufs(&mut self) -> UFS_W { + UFS_W { w: self } + } + #[doc = "Bit 11 - Non-Recoverable Debug Fault Interrupt Enable"] + #[inline(always)] + pub fn dfs(&mut self) -> DFS_W { + DFS_W { w: self } + } + #[doc = "Bit 12 - Recoverable Fault A Interrupt Enable"] + #[inline(always)] + pub fn faulta(&mut self) -> FAULTA_W { + FAULTA_W { w: self } + } + #[doc = "Bit 13 - Recoverable Fault B Interrupt Enable"] + #[inline(always)] + pub fn faultb(&mut self) -> FAULTB_W { + FAULTB_W { w: self } + } + #[doc = "Bit 14 - Non-Recoverable Fault 0 Interrupt Enable"] + #[inline(always)] + pub fn fault0(&mut self) -> FAULT0_W { + FAULT0_W { w: self } + } + #[doc = "Bit 15 - Non-Recoverable Fault 1 Interrupt Enable"] + #[inline(always)] + pub fn fault1(&mut self) -> FAULT1_W { + FAULT1_W { w: self } + } + #[doc = "Bit 16 - Match or Capture Channel 0 Interrupt Enable"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 17 - Match or Capture Channel 1 Interrupt Enable"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Bit 18 - Match or Capture Channel 2 Interrupt Enable"] + #[inline(always)] + pub fn mc2(&mut self) -> MC2_W { + MC2_W { w: self } + } + #[doc = "Bit 19 - Match or Capture Channel 3 Interrupt Enable"] + #[inline(always)] + pub fn mc3(&mut self) -> MC3_W { + MC3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/tcc0/intenset.rs b/pac/atsamc21g/src/tcc0/intenset.rs new file mode 100644 index 000000000000..0125a220bd02 --- /dev/null +++ b/pac/atsamc21g/src/tcc0/intenset.rs @@ -0,0 +1,724 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `TRG` reader - Retrigger Interrupt Enable"] +pub struct TRG_R(crate::FieldReader); +impl TRG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRG` writer - Retrigger Interrupt Enable"] +pub struct TRG_W<'a> { + w: &'a mut W, +} +impl<'a> TRG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CNT` reader - Counter Interrupt Enable"] +pub struct CNT_R(crate::FieldReader); +impl CNT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CNT` writer - Counter Interrupt Enable"] +pub struct CNT_W<'a> { + w: &'a mut W, +} +impl<'a> CNT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `ERR` reader - Error Interrupt Enable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - Error Interrupt Enable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `UFS` reader - Non-Recoverable Update Fault Interrupt Enable"] +pub struct UFS_R(crate::FieldReader); +impl UFS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UFS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for UFS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `UFS` writer - Non-Recoverable Update Fault Interrupt Enable"] +pub struct UFS_W<'a> { + w: &'a mut W, +} +impl<'a> UFS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `DFS` reader - Non-Recoverable Debug Fault Interrupt Enable"] +pub struct DFS_R(crate::FieldReader); +impl DFS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFS` writer - Non-Recoverable Debug Fault Interrupt Enable"] +pub struct DFS_W<'a> { + w: &'a mut W, +} +impl<'a> DFS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `FAULTA` reader - Recoverable Fault A Interrupt Enable"] +pub struct FAULTA_R(crate::FieldReader); +impl FAULTA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTA` writer - Recoverable Fault A Interrupt Enable"] +pub struct FAULTA_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `FAULTB` reader - Recoverable Fault B Interrupt Enable"] +pub struct FAULTB_R(crate::FieldReader); +impl FAULTB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTB` writer - Recoverable Fault B Interrupt Enable"] +pub struct FAULTB_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `FAULT0` reader - Non-Recoverable Fault 0 Interrupt Enable"] +pub struct FAULT0_R(crate::FieldReader); +impl FAULT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT0` writer - Non-Recoverable Fault 0 Interrupt Enable"] +pub struct FAULT0_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `FAULT1` reader - Non-Recoverable Fault 1 Interrupt Enable"] +pub struct FAULT1_R(crate::FieldReader); +impl FAULT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT1` writer - Non-Recoverable Fault 1 Interrupt Enable"] +pub struct FAULT1_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `MC0` reader - Match or Capture Channel 0 Interrupt Enable"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - Match or Capture Channel 0 Interrupt Enable"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `MC1` reader - Match or Capture Channel 1 Interrupt Enable"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - Match or Capture Channel 1 Interrupt Enable"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `MC2` reader - Match or Capture Channel 2 Interrupt Enable"] +pub struct MC2_R(crate::FieldReader); +impl MC2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC2` writer - Match or Capture Channel 2 Interrupt Enable"] +pub struct MC2_W<'a> { + w: &'a mut W, +} +impl<'a> MC2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `MC3` reader - Match or Capture Channel 3 Interrupt Enable"] +pub struct MC3_R(crate::FieldReader); +impl MC3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC3` writer - Match or Capture Channel 3 Interrupt Enable"] +pub struct MC3_W<'a> { + w: &'a mut W, +} +impl<'a> MC3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +impl R { + #[doc = "Bit 0 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Retrigger Interrupt Enable"] + #[inline(always)] + pub fn trg(&self) -> TRG_R { + TRG_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Counter Interrupt Enable"] + #[inline(always)] + pub fn cnt(&self) -> CNT_R { + CNT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Error Interrupt Enable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 10 - Non-Recoverable Update Fault Interrupt Enable"] + #[inline(always)] + pub fn ufs(&self) -> UFS_R { + UFS_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Non-Recoverable Debug Fault Interrupt Enable"] + #[inline(always)] + pub fn dfs(&self) -> DFS_R { + DFS_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Recoverable Fault A Interrupt Enable"] + #[inline(always)] + pub fn faulta(&self) -> FAULTA_R { + FAULTA_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Recoverable Fault B Interrupt Enable"] + #[inline(always)] + pub fn faultb(&self) -> FAULTB_R { + FAULTB_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Non-Recoverable Fault 0 Interrupt Enable"] + #[inline(always)] + pub fn fault0(&self) -> FAULT0_R { + FAULT0_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Non-Recoverable Fault 1 Interrupt Enable"] + #[inline(always)] + pub fn fault1(&self) -> FAULT1_R { + FAULT1_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Match or Capture Channel 0 Interrupt Enable"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Match or Capture Channel 1 Interrupt Enable"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Match or Capture Channel 2 Interrupt Enable"] + #[inline(always)] + pub fn mc2(&self) -> MC2_R { + MC2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Match or Capture Channel 3 Interrupt Enable"] + #[inline(always)] + pub fn mc3(&self) -> MC3_R { + MC3_R::new(((self.bits >> 19) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - Retrigger Interrupt Enable"] + #[inline(always)] + pub fn trg(&mut self) -> TRG_W { + TRG_W { w: self } + } + #[doc = "Bit 2 - Counter Interrupt Enable"] + #[inline(always)] + pub fn cnt(&mut self) -> CNT_W { + CNT_W { w: self } + } + #[doc = "Bit 3 - Error Interrupt Enable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 10 - Non-Recoverable Update Fault Interrupt Enable"] + #[inline(always)] + pub fn ufs(&mut self) -> UFS_W { + UFS_W { w: self } + } + #[doc = "Bit 11 - Non-Recoverable Debug Fault Interrupt Enable"] + #[inline(always)] + pub fn dfs(&mut self) -> DFS_W { + DFS_W { w: self } + } + #[doc = "Bit 12 - Recoverable Fault A Interrupt Enable"] + #[inline(always)] + pub fn faulta(&mut self) -> FAULTA_W { + FAULTA_W { w: self } + } + #[doc = "Bit 13 - Recoverable Fault B Interrupt Enable"] + #[inline(always)] + pub fn faultb(&mut self) -> FAULTB_W { + FAULTB_W { w: self } + } + #[doc = "Bit 14 - Non-Recoverable Fault 0 Interrupt Enable"] + #[inline(always)] + pub fn fault0(&mut self) -> FAULT0_W { + FAULT0_W { w: self } + } + #[doc = "Bit 15 - Non-Recoverable Fault 1 Interrupt Enable"] + #[inline(always)] + pub fn fault1(&mut self) -> FAULT1_W { + FAULT1_W { w: self } + } + #[doc = "Bit 16 - Match or Capture Channel 0 Interrupt Enable"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 17 - Match or Capture Channel 1 Interrupt Enable"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Bit 18 - Match or Capture Channel 2 Interrupt Enable"] + #[inline(always)] + pub fn mc2(&mut self) -> MC2_W { + MC2_W { w: self } + } + #[doc = "Bit 19 - Match or Capture Channel 3 Interrupt Enable"] + #[inline(always)] + pub fn mc3(&mut self) -> MC3_W { + MC3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/tcc0/intflag.rs b/pac/atsamc21g/src/tcc0/intflag.rs new file mode 100644 index 000000000000..b2d5088f4087 --- /dev/null +++ b/pac/atsamc21g/src/tcc0/intflag.rs @@ -0,0 +1,724 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - Overflow"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `TRG` reader - Retrigger"] +pub struct TRG_R(crate::FieldReader); +impl TRG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRG` writer - Retrigger"] +pub struct TRG_W<'a> { + w: &'a mut W, +} +impl<'a> TRG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CNT` reader - Counter"] +pub struct CNT_R(crate::FieldReader); +impl CNT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CNT` writer - Counter"] +pub struct CNT_W<'a> { + w: &'a mut W, +} +impl<'a> CNT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `ERR` reader - Error"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - Error"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `UFS` reader - Non-Recoverable Update Fault"] +pub struct UFS_R(crate::FieldReader); +impl UFS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UFS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for UFS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `UFS` writer - Non-Recoverable Update Fault"] +pub struct UFS_W<'a> { + w: &'a mut W, +} +impl<'a> UFS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `DFS` reader - Non-Recoverable Debug Fault"] +pub struct DFS_R(crate::FieldReader); +impl DFS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFS` writer - Non-Recoverable Debug Fault"] +pub struct DFS_W<'a> { + w: &'a mut W, +} +impl<'a> DFS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `FAULTA` reader - Recoverable Fault A"] +pub struct FAULTA_R(crate::FieldReader); +impl FAULTA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTA` writer - Recoverable Fault A"] +pub struct FAULTA_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `FAULTB` reader - Recoverable Fault B"] +pub struct FAULTB_R(crate::FieldReader); +impl FAULTB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTB` writer - Recoverable Fault B"] +pub struct FAULTB_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `FAULT0` reader - Non-Recoverable Fault 0"] +pub struct FAULT0_R(crate::FieldReader); +impl FAULT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT0` writer - Non-Recoverable Fault 0"] +pub struct FAULT0_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `FAULT1` reader - Non-Recoverable Fault 1"] +pub struct FAULT1_R(crate::FieldReader); +impl FAULT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT1` writer - Non-Recoverable Fault 1"] +pub struct FAULT1_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `MC0` reader - Match or Capture 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - Match or Capture 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `MC1` reader - Match or Capture 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - Match or Capture 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `MC2` reader - Match or Capture 2"] +pub struct MC2_R(crate::FieldReader); +impl MC2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC2` writer - Match or Capture 2"] +pub struct MC2_W<'a> { + w: &'a mut W, +} +impl<'a> MC2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `MC3` reader - Match or Capture 3"] +pub struct MC3_R(crate::FieldReader); +impl MC3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC3` writer - Match or Capture 3"] +pub struct MC3_W<'a> { + w: &'a mut W, +} +impl<'a> MC3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +impl R { + #[doc = "Bit 0 - Overflow"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Retrigger"] + #[inline(always)] + pub fn trg(&self) -> TRG_R { + TRG_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Counter"] + #[inline(always)] + pub fn cnt(&self) -> CNT_R { + CNT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Error"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 10 - Non-Recoverable Update Fault"] + #[inline(always)] + pub fn ufs(&self) -> UFS_R { + UFS_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Non-Recoverable Debug Fault"] + #[inline(always)] + pub fn dfs(&self) -> DFS_R { + DFS_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Recoverable Fault A"] + #[inline(always)] + pub fn faulta(&self) -> FAULTA_R { + FAULTA_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Recoverable Fault B"] + #[inline(always)] + pub fn faultb(&self) -> FAULTB_R { + FAULTB_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Non-Recoverable Fault 0"] + #[inline(always)] + pub fn fault0(&self) -> FAULT0_R { + FAULT0_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Non-Recoverable Fault 1"] + #[inline(always)] + pub fn fault1(&self) -> FAULT1_R { + FAULT1_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Match or Capture 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Match or Capture 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Match or Capture 2"] + #[inline(always)] + pub fn mc2(&self) -> MC2_R { + MC2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Match or Capture 3"] + #[inline(always)] + pub fn mc3(&self) -> MC3_R { + MC3_R::new(((self.bits >> 19) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Overflow"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - Retrigger"] + #[inline(always)] + pub fn trg(&mut self) -> TRG_W { + TRG_W { w: self } + } + #[doc = "Bit 2 - Counter"] + #[inline(always)] + pub fn cnt(&mut self) -> CNT_W { + CNT_W { w: self } + } + #[doc = "Bit 3 - Error"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 10 - Non-Recoverable Update Fault"] + #[inline(always)] + pub fn ufs(&mut self) -> UFS_W { + UFS_W { w: self } + } + #[doc = "Bit 11 - Non-Recoverable Debug Fault"] + #[inline(always)] + pub fn dfs(&mut self) -> DFS_W { + DFS_W { w: self } + } + #[doc = "Bit 12 - Recoverable Fault A"] + #[inline(always)] + pub fn faulta(&mut self) -> FAULTA_W { + FAULTA_W { w: self } + } + #[doc = "Bit 13 - Recoverable Fault B"] + #[inline(always)] + pub fn faultb(&mut self) -> FAULTB_W { + FAULTB_W { w: self } + } + #[doc = "Bit 14 - Non-Recoverable Fault 0"] + #[inline(always)] + pub fn fault0(&mut self) -> FAULT0_W { + FAULT0_W { w: self } + } + #[doc = "Bit 15 - Non-Recoverable Fault 1"] + #[inline(always)] + pub fn fault1(&mut self) -> FAULT1_W { + FAULT1_W { w: self } + } + #[doc = "Bit 16 - Match or Capture 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 17 - Match or Capture 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Bit 18 - Match or Capture 2"] + #[inline(always)] + pub fn mc2(&mut self) -> MC2_W { + MC2_W { w: self } + } + #[doc = "Bit 19 - Match or Capture 3"] + #[inline(always)] + pub fn mc3(&mut self) -> MC3_W { + MC3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/tcc0/patt.rs b/pac/atsamc21g/src/tcc0/patt.rs new file mode 100644 index 000000000000..ea458642b182 --- /dev/null +++ b/pac/atsamc21g/src/tcc0/patt.rs @@ -0,0 +1,818 @@ +#[doc = "Register `PATT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PATT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PGE0` reader - Pattern Generator 0 Output Enable"] +pub struct PGE0_R(crate::FieldReader); +impl PGE0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGE0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGE0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGE0` writer - Pattern Generator 0 Output Enable"] +pub struct PGE0_W<'a> { + w: &'a mut W, +} +impl<'a> PGE0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PGE1` reader - Pattern Generator 1 Output Enable"] +pub struct PGE1_R(crate::FieldReader); +impl PGE1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGE1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGE1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGE1` writer - Pattern Generator 1 Output Enable"] +pub struct PGE1_W<'a> { + w: &'a mut W, +} +impl<'a> PGE1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PGE2` reader - Pattern Generator 2 Output Enable"] +pub struct PGE2_R(crate::FieldReader); +impl PGE2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGE2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGE2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGE2` writer - Pattern Generator 2 Output Enable"] +pub struct PGE2_W<'a> { + w: &'a mut W, +} +impl<'a> PGE2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PGE3` reader - Pattern Generator 3 Output Enable"] +pub struct PGE3_R(crate::FieldReader); +impl PGE3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGE3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGE3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGE3` writer - Pattern Generator 3 Output Enable"] +pub struct PGE3_W<'a> { + w: &'a mut W, +} +impl<'a> PGE3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PGE4` reader - Pattern Generator 4 Output Enable"] +pub struct PGE4_R(crate::FieldReader); +impl PGE4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGE4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGE4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGE4` writer - Pattern Generator 4 Output Enable"] +pub struct PGE4_W<'a> { + w: &'a mut W, +} +impl<'a> PGE4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PGE5` reader - Pattern Generator 5 Output Enable"] +pub struct PGE5_R(crate::FieldReader); +impl PGE5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGE5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGE5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGE5` writer - Pattern Generator 5 Output Enable"] +pub struct PGE5_W<'a> { + w: &'a mut W, +} +impl<'a> PGE5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PGE6` reader - Pattern Generator 6 Output Enable"] +pub struct PGE6_R(crate::FieldReader); +impl PGE6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGE6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGE6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGE6` writer - Pattern Generator 6 Output Enable"] +pub struct PGE6_W<'a> { + w: &'a mut W, +} +impl<'a> PGE6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PGE7` reader - Pattern Generator 7 Output Enable"] +pub struct PGE7_R(crate::FieldReader); +impl PGE7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGE7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGE7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGE7` writer - Pattern Generator 7 Output Enable"] +pub struct PGE7_W<'a> { + w: &'a mut W, +} +impl<'a> PGE7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `PGV0` reader - Pattern Generator 0 Output Value"] +pub struct PGV0_R(crate::FieldReader); +impl PGV0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGV0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGV0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGV0` writer - Pattern Generator 0 Output Value"] +pub struct PGV0_W<'a> { + w: &'a mut W, +} +impl<'a> PGV0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `PGV1` reader - Pattern Generator 1 Output Value"] +pub struct PGV1_R(crate::FieldReader); +impl PGV1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGV1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGV1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGV1` writer - Pattern Generator 1 Output Value"] +pub struct PGV1_W<'a> { + w: &'a mut W, +} +impl<'a> PGV1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `PGV2` reader - Pattern Generator 2 Output Value"] +pub struct PGV2_R(crate::FieldReader); +impl PGV2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGV2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGV2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGV2` writer - Pattern Generator 2 Output Value"] +pub struct PGV2_W<'a> { + w: &'a mut W, +} +impl<'a> PGV2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u16 & 0x01) << 10); + self.w + } +} +#[doc = "Field `PGV3` reader - Pattern Generator 3 Output Value"] +pub struct PGV3_R(crate::FieldReader); +impl PGV3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGV3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGV3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGV3` writer - Pattern Generator 3 Output Value"] +pub struct PGV3_W<'a> { + w: &'a mut W, +} +impl<'a> PGV3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u16 & 0x01) << 11); + self.w + } +} +#[doc = "Field `PGV4` reader - Pattern Generator 4 Output Value"] +pub struct PGV4_R(crate::FieldReader); +impl PGV4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGV4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGV4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGV4` writer - Pattern Generator 4 Output Value"] +pub struct PGV4_W<'a> { + w: &'a mut W, +} +impl<'a> PGV4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u16 & 0x01) << 12); + self.w + } +} +#[doc = "Field `PGV5` reader - Pattern Generator 5 Output Value"] +pub struct PGV5_R(crate::FieldReader); +impl PGV5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGV5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGV5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGV5` writer - Pattern Generator 5 Output Value"] +pub struct PGV5_W<'a> { + w: &'a mut W, +} +impl<'a> PGV5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u16 & 0x01) << 13); + self.w + } +} +#[doc = "Field `PGV6` reader - Pattern Generator 6 Output Value"] +pub struct PGV6_R(crate::FieldReader); +impl PGV6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGV6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGV6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGV6` writer - Pattern Generator 6 Output Value"] +pub struct PGV6_W<'a> { + w: &'a mut W, +} +impl<'a> PGV6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u16 & 0x01) << 14); + self.w + } +} +#[doc = "Field `PGV7` reader - Pattern Generator 7 Output Value"] +pub struct PGV7_R(crate::FieldReader); +impl PGV7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGV7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGV7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGV7` writer - Pattern Generator 7 Output Value"] +pub struct PGV7_W<'a> { + w: &'a mut W, +} +impl<'a> PGV7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Pattern Generator 0 Output Enable"] + #[inline(always)] + pub fn pge0(&self) -> PGE0_R { + PGE0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Pattern Generator 1 Output Enable"] + #[inline(always)] + pub fn pge1(&self) -> PGE1_R { + PGE1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Pattern Generator 2 Output Enable"] + #[inline(always)] + pub fn pge2(&self) -> PGE2_R { + PGE2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Pattern Generator 3 Output Enable"] + #[inline(always)] + pub fn pge3(&self) -> PGE3_R { + PGE3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Pattern Generator 4 Output Enable"] + #[inline(always)] + pub fn pge4(&self) -> PGE4_R { + PGE4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Pattern Generator 5 Output Enable"] + #[inline(always)] + pub fn pge5(&self) -> PGE5_R { + PGE5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Pattern Generator 6 Output Enable"] + #[inline(always)] + pub fn pge6(&self) -> PGE6_R { + PGE6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Pattern Generator 7 Output Enable"] + #[inline(always)] + pub fn pge7(&self) -> PGE7_R { + PGE7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Pattern Generator 0 Output Value"] + #[inline(always)] + pub fn pgv0(&self) -> PGV0_R { + PGV0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Pattern Generator 1 Output Value"] + #[inline(always)] + pub fn pgv1(&self) -> PGV1_R { + PGV1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Pattern Generator 2 Output Value"] + #[inline(always)] + pub fn pgv2(&self) -> PGV2_R { + PGV2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Pattern Generator 3 Output Value"] + #[inline(always)] + pub fn pgv3(&self) -> PGV3_R { + PGV3_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Pattern Generator 4 Output Value"] + #[inline(always)] + pub fn pgv4(&self) -> PGV4_R { + PGV4_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Pattern Generator 5 Output Value"] + #[inline(always)] + pub fn pgv5(&self) -> PGV5_R { + PGV5_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Pattern Generator 6 Output Value"] + #[inline(always)] + pub fn pgv6(&self) -> PGV6_R { + PGV6_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Pattern Generator 7 Output Value"] + #[inline(always)] + pub fn pgv7(&self) -> PGV7_R { + PGV7_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pattern Generator 0 Output Enable"] + #[inline(always)] + pub fn pge0(&mut self) -> PGE0_W { + PGE0_W { w: self } + } + #[doc = "Bit 1 - Pattern Generator 1 Output Enable"] + #[inline(always)] + pub fn pge1(&mut self) -> PGE1_W { + PGE1_W { w: self } + } + #[doc = "Bit 2 - Pattern Generator 2 Output Enable"] + #[inline(always)] + pub fn pge2(&mut self) -> PGE2_W { + PGE2_W { w: self } + } + #[doc = "Bit 3 - Pattern Generator 3 Output Enable"] + #[inline(always)] + pub fn pge3(&mut self) -> PGE3_W { + PGE3_W { w: self } + } + #[doc = "Bit 4 - Pattern Generator 4 Output Enable"] + #[inline(always)] + pub fn pge4(&mut self) -> PGE4_W { + PGE4_W { w: self } + } + #[doc = "Bit 5 - Pattern Generator 5 Output Enable"] + #[inline(always)] + pub fn pge5(&mut self) -> PGE5_W { + PGE5_W { w: self } + } + #[doc = "Bit 6 - Pattern Generator 6 Output Enable"] + #[inline(always)] + pub fn pge6(&mut self) -> PGE6_W { + PGE6_W { w: self } + } + #[doc = "Bit 7 - Pattern Generator 7 Output Enable"] + #[inline(always)] + pub fn pge7(&mut self) -> PGE7_W { + PGE7_W { w: self } + } + #[doc = "Bit 8 - Pattern Generator 0 Output Value"] + #[inline(always)] + pub fn pgv0(&mut self) -> PGV0_W { + PGV0_W { w: self } + } + #[doc = "Bit 9 - Pattern Generator 1 Output Value"] + #[inline(always)] + pub fn pgv1(&mut self) -> PGV1_W { + PGV1_W { w: self } + } + #[doc = "Bit 10 - Pattern Generator 2 Output Value"] + #[inline(always)] + pub fn pgv2(&mut self) -> PGV2_W { + PGV2_W { w: self } + } + #[doc = "Bit 11 - Pattern Generator 3 Output Value"] + #[inline(always)] + pub fn pgv3(&mut self) -> PGV3_W { + PGV3_W { w: self } + } + #[doc = "Bit 12 - Pattern Generator 4 Output Value"] + #[inline(always)] + pub fn pgv4(&mut self) -> PGV4_W { + PGV4_W { w: self } + } + #[doc = "Bit 13 - Pattern Generator 5 Output Value"] + #[inline(always)] + pub fn pgv5(&mut self) -> PGV5_W { + PGV5_W { w: self } + } + #[doc = "Bit 14 - Pattern Generator 6 Output Value"] + #[inline(always)] + pub fn pgv6(&mut self) -> PGV6_W { + PGV6_W { w: self } + } + #[doc = "Bit 15 - Pattern Generator 7 Output Value"] + #[inline(always)] + pub fn pgv7(&mut self) -> PGV7_W { + PGV7_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Pattern\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [patt](index.html) module"] +pub struct PATT_SPEC; +impl crate::RegisterSpec for PATT_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [patt::R](R) reader structure"] +impl crate::Readable for PATT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [patt::W](W) writer structure"] +impl crate::Writable for PATT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PATT to value 0"] +impl crate::Resettable for PATT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/tcc0/pattbuf.rs b/pac/atsamc21g/src/tcc0/pattbuf.rs new file mode 100644 index 000000000000..c9375e27645c --- /dev/null +++ b/pac/atsamc21g/src/tcc0/pattbuf.rs @@ -0,0 +1,818 @@ +#[doc = "Register `PATTBUF` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PATTBUF` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PGEB0` reader - Pattern Generator 0 Output Enable Buffer"] +pub struct PGEB0_R(crate::FieldReader); +impl PGEB0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGEB0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGEB0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGEB0` writer - Pattern Generator 0 Output Enable Buffer"] +pub struct PGEB0_W<'a> { + w: &'a mut W, +} +impl<'a> PGEB0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PGEB1` reader - Pattern Generator 1 Output Enable Buffer"] +pub struct PGEB1_R(crate::FieldReader); +impl PGEB1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGEB1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGEB1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGEB1` writer - Pattern Generator 1 Output Enable Buffer"] +pub struct PGEB1_W<'a> { + w: &'a mut W, +} +impl<'a> PGEB1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PGEB2` reader - Pattern Generator 2 Output Enable Buffer"] +pub struct PGEB2_R(crate::FieldReader); +impl PGEB2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGEB2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGEB2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGEB2` writer - Pattern Generator 2 Output Enable Buffer"] +pub struct PGEB2_W<'a> { + w: &'a mut W, +} +impl<'a> PGEB2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PGEB3` reader - Pattern Generator 3 Output Enable Buffer"] +pub struct PGEB3_R(crate::FieldReader); +impl PGEB3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGEB3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGEB3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGEB3` writer - Pattern Generator 3 Output Enable Buffer"] +pub struct PGEB3_W<'a> { + w: &'a mut W, +} +impl<'a> PGEB3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PGEB4` reader - Pattern Generator 4 Output Enable Buffer"] +pub struct PGEB4_R(crate::FieldReader); +impl PGEB4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGEB4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGEB4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGEB4` writer - Pattern Generator 4 Output Enable Buffer"] +pub struct PGEB4_W<'a> { + w: &'a mut W, +} +impl<'a> PGEB4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PGEB5` reader - Pattern Generator 5 Output Enable Buffer"] +pub struct PGEB5_R(crate::FieldReader); +impl PGEB5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGEB5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGEB5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGEB5` writer - Pattern Generator 5 Output Enable Buffer"] +pub struct PGEB5_W<'a> { + w: &'a mut W, +} +impl<'a> PGEB5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PGEB6` reader - Pattern Generator 6 Output Enable Buffer"] +pub struct PGEB6_R(crate::FieldReader); +impl PGEB6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGEB6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGEB6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGEB6` writer - Pattern Generator 6 Output Enable Buffer"] +pub struct PGEB6_W<'a> { + w: &'a mut W, +} +impl<'a> PGEB6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PGEB7` reader - Pattern Generator 7 Output Enable Buffer"] +pub struct PGEB7_R(crate::FieldReader); +impl PGEB7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGEB7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGEB7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGEB7` writer - Pattern Generator 7 Output Enable Buffer"] +pub struct PGEB7_W<'a> { + w: &'a mut W, +} +impl<'a> PGEB7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `PGVB0` reader - Pattern Generator 0 Output Enable"] +pub struct PGVB0_R(crate::FieldReader); +impl PGVB0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGVB0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGVB0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGVB0` writer - Pattern Generator 0 Output Enable"] +pub struct PGVB0_W<'a> { + w: &'a mut W, +} +impl<'a> PGVB0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `PGVB1` reader - Pattern Generator 1 Output Enable"] +pub struct PGVB1_R(crate::FieldReader); +impl PGVB1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGVB1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGVB1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGVB1` writer - Pattern Generator 1 Output Enable"] +pub struct PGVB1_W<'a> { + w: &'a mut W, +} +impl<'a> PGVB1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `PGVB2` reader - Pattern Generator 2 Output Enable"] +pub struct PGVB2_R(crate::FieldReader); +impl PGVB2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGVB2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGVB2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGVB2` writer - Pattern Generator 2 Output Enable"] +pub struct PGVB2_W<'a> { + w: &'a mut W, +} +impl<'a> PGVB2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u16 & 0x01) << 10); + self.w + } +} +#[doc = "Field `PGVB3` reader - Pattern Generator 3 Output Enable"] +pub struct PGVB3_R(crate::FieldReader); +impl PGVB3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGVB3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGVB3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGVB3` writer - Pattern Generator 3 Output Enable"] +pub struct PGVB3_W<'a> { + w: &'a mut W, +} +impl<'a> PGVB3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u16 & 0x01) << 11); + self.w + } +} +#[doc = "Field `PGVB4` reader - Pattern Generator 4 Output Enable"] +pub struct PGVB4_R(crate::FieldReader); +impl PGVB4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGVB4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGVB4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGVB4` writer - Pattern Generator 4 Output Enable"] +pub struct PGVB4_W<'a> { + w: &'a mut W, +} +impl<'a> PGVB4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u16 & 0x01) << 12); + self.w + } +} +#[doc = "Field `PGVB5` reader - Pattern Generator 5 Output Enable"] +pub struct PGVB5_R(crate::FieldReader); +impl PGVB5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGVB5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGVB5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGVB5` writer - Pattern Generator 5 Output Enable"] +pub struct PGVB5_W<'a> { + w: &'a mut W, +} +impl<'a> PGVB5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u16 & 0x01) << 13); + self.w + } +} +#[doc = "Field `PGVB6` reader - Pattern Generator 6 Output Enable"] +pub struct PGVB6_R(crate::FieldReader); +impl PGVB6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGVB6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGVB6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGVB6` writer - Pattern Generator 6 Output Enable"] +pub struct PGVB6_W<'a> { + w: &'a mut W, +} +impl<'a> PGVB6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u16 & 0x01) << 14); + self.w + } +} +#[doc = "Field `PGVB7` reader - Pattern Generator 7 Output Enable"] +pub struct PGVB7_R(crate::FieldReader); +impl PGVB7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGVB7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGVB7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGVB7` writer - Pattern Generator 7 Output Enable"] +pub struct PGVB7_W<'a> { + w: &'a mut W, +} +impl<'a> PGVB7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Pattern Generator 0 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb0(&self) -> PGEB0_R { + PGEB0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Pattern Generator 1 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb1(&self) -> PGEB1_R { + PGEB1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Pattern Generator 2 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb2(&self) -> PGEB2_R { + PGEB2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Pattern Generator 3 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb3(&self) -> PGEB3_R { + PGEB3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Pattern Generator 4 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb4(&self) -> PGEB4_R { + PGEB4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Pattern Generator 5 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb5(&self) -> PGEB5_R { + PGEB5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Pattern Generator 6 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb6(&self) -> PGEB6_R { + PGEB6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Pattern Generator 7 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb7(&self) -> PGEB7_R { + PGEB7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Pattern Generator 0 Output Enable"] + #[inline(always)] + pub fn pgvb0(&self) -> PGVB0_R { + PGVB0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Pattern Generator 1 Output Enable"] + #[inline(always)] + pub fn pgvb1(&self) -> PGVB1_R { + PGVB1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Pattern Generator 2 Output Enable"] + #[inline(always)] + pub fn pgvb2(&self) -> PGVB2_R { + PGVB2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Pattern Generator 3 Output Enable"] + #[inline(always)] + pub fn pgvb3(&self) -> PGVB3_R { + PGVB3_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Pattern Generator 4 Output Enable"] + #[inline(always)] + pub fn pgvb4(&self) -> PGVB4_R { + PGVB4_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Pattern Generator 5 Output Enable"] + #[inline(always)] + pub fn pgvb5(&self) -> PGVB5_R { + PGVB5_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Pattern Generator 6 Output Enable"] + #[inline(always)] + pub fn pgvb6(&self) -> PGVB6_R { + PGVB6_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Pattern Generator 7 Output Enable"] + #[inline(always)] + pub fn pgvb7(&self) -> PGVB7_R { + PGVB7_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pattern Generator 0 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb0(&mut self) -> PGEB0_W { + PGEB0_W { w: self } + } + #[doc = "Bit 1 - Pattern Generator 1 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb1(&mut self) -> PGEB1_W { + PGEB1_W { w: self } + } + #[doc = "Bit 2 - Pattern Generator 2 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb2(&mut self) -> PGEB2_W { + PGEB2_W { w: self } + } + #[doc = "Bit 3 - Pattern Generator 3 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb3(&mut self) -> PGEB3_W { + PGEB3_W { w: self } + } + #[doc = "Bit 4 - Pattern Generator 4 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb4(&mut self) -> PGEB4_W { + PGEB4_W { w: self } + } + #[doc = "Bit 5 - Pattern Generator 5 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb5(&mut self) -> PGEB5_W { + PGEB5_W { w: self } + } + #[doc = "Bit 6 - Pattern Generator 6 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb6(&mut self) -> PGEB6_W { + PGEB6_W { w: self } + } + #[doc = "Bit 7 - Pattern Generator 7 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb7(&mut self) -> PGEB7_W { + PGEB7_W { w: self } + } + #[doc = "Bit 8 - Pattern Generator 0 Output Enable"] + #[inline(always)] + pub fn pgvb0(&mut self) -> PGVB0_W { + PGVB0_W { w: self } + } + #[doc = "Bit 9 - Pattern Generator 1 Output Enable"] + #[inline(always)] + pub fn pgvb1(&mut self) -> PGVB1_W { + PGVB1_W { w: self } + } + #[doc = "Bit 10 - Pattern Generator 2 Output Enable"] + #[inline(always)] + pub fn pgvb2(&mut self) -> PGVB2_W { + PGVB2_W { w: self } + } + #[doc = "Bit 11 - Pattern Generator 3 Output Enable"] + #[inline(always)] + pub fn pgvb3(&mut self) -> PGVB3_W { + PGVB3_W { w: self } + } + #[doc = "Bit 12 - Pattern Generator 4 Output Enable"] + #[inline(always)] + pub fn pgvb4(&mut self) -> PGVB4_W { + PGVB4_W { w: self } + } + #[doc = "Bit 13 - Pattern Generator 5 Output Enable"] + #[inline(always)] + pub fn pgvb5(&mut self) -> PGVB5_W { + PGVB5_W { w: self } + } + #[doc = "Bit 14 - Pattern Generator 6 Output Enable"] + #[inline(always)] + pub fn pgvb6(&mut self) -> PGVB6_W { + PGVB6_W { w: self } + } + #[doc = "Bit 15 - Pattern Generator 7 Output Enable"] + #[inline(always)] + pub fn pgvb7(&mut self) -> PGVB7_W { + PGVB7_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Pattern Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pattbuf](index.html) module"] +pub struct PATTBUF_SPEC; +impl crate::RegisterSpec for PATTBUF_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [pattbuf::R](R) reader structure"] +impl crate::Readable for PATTBUF_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [pattbuf::W](W) writer structure"] +impl crate::Writable for PATTBUF_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PATTBUF to value 0"] +impl crate::Resettable for PATTBUF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/tcc0/per.rs b/pac/atsamc21g/src/tcc0/per.rs new file mode 100644 index 000000000000..9d8618631650 --- /dev/null +++ b/pac/atsamc21g/src/tcc0/per.rs @@ -0,0 +1,103 @@ +#[doc = "Register `PER` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PER` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER` reader - Period Value"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` writer - Period Value"] +pub struct PER_W<'a> { + w: &'a mut W, +} +impl<'a> PER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Period Value"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Period Value"] + #[inline(always)] + pub fn per(&mut self) -> PER_W { + PER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [per](index.html) module"] +pub struct PER_SPEC; +impl crate::RegisterSpec for PER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [per::R](R) reader structure"] +impl crate::Readable for PER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [per::W](W) writer structure"] +impl crate::Writable for PER_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PER to value 0xffff_ffff"] +impl crate::Resettable for PER_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pac/atsamc21g/src/tcc0/per_dith4_mode.rs b/pac/atsamc21g/src/tcc0/per_dith4_mode.rs new file mode 100644 index 000000000000..2f600552db84 --- /dev/null +++ b/pac/atsamc21g/src/tcc0/per_dith4_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PER_DITH4_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PER_DITH4_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHER` reader - Dithering Cycle Number"] +pub struct DITHER_R(crate::FieldReader); +impl DITHER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHER` writer - Dithering Cycle Number"] +pub struct DITHER_W<'a> { + w: &'a mut W, +} +impl<'a> DITHER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Field `PER` reader - Period Value"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` writer - Period Value"] +pub struct PER_W<'a> { + w: &'a mut W, +} +impl<'a> PER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x000f_ffff << 4)) | ((value as u32 & 0x000f_ffff) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&self) -> DITHER_R { + DITHER_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:23 - Period Value"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(((self.bits >> 4) & 0x000f_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:3 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&mut self) -> DITHER_W { + DITHER_W { w: self } + } + #[doc = "Bits 4:23 - Period Value"] + #[inline(always)] + pub fn per(&mut self) -> PER_W { + PER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [per_dith4_mode](index.html) module"] +pub struct PER_DITH4_MODE_SPEC; +impl crate::RegisterSpec for PER_DITH4_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [per_dith4_mode::R](R) reader structure"] +impl crate::Readable for PER_DITH4_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [per_dith4_mode::W](W) writer structure"] +impl crate::Writable for PER_DITH4_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PER_DITH4_MODE to value 0xffff_ffff"] +impl crate::Resettable for PER_DITH4_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pac/atsamc21g/src/tcc0/per_dith5_mode.rs b/pac/atsamc21g/src/tcc0/per_dith5_mode.rs new file mode 100644 index 000000000000..1906582e4c95 --- /dev/null +++ b/pac/atsamc21g/src/tcc0/per_dith5_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PER_DITH5_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PER_DITH5_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHER` reader - Dithering Cycle Number"] +pub struct DITHER_R(crate::FieldReader); +impl DITHER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHER` writer - Dithering Cycle Number"] +pub struct DITHER_W<'a> { + w: &'a mut W, +} +impl<'a> DITHER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f); + self.w + } +} +#[doc = "Field `PER` reader - Period Value"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` writer - Period Value"] +pub struct PER_W<'a> { + w: &'a mut W, +} +impl<'a> PER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0007_ffff << 5)) | ((value as u32 & 0x0007_ffff) << 5); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&self) -> DITHER_R { + DITHER_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:23 - Period Value"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(((self.bits >> 5) & 0x0007_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:4 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&mut self) -> DITHER_W { + DITHER_W { w: self } + } + #[doc = "Bits 5:23 - Period Value"] + #[inline(always)] + pub fn per(&mut self) -> PER_W { + PER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [per_dith5_mode](index.html) module"] +pub struct PER_DITH5_MODE_SPEC; +impl crate::RegisterSpec for PER_DITH5_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [per_dith5_mode::R](R) reader structure"] +impl crate::Readable for PER_DITH5_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [per_dith5_mode::W](W) writer structure"] +impl crate::Writable for PER_DITH5_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PER_DITH5_MODE to value 0xffff_ffff"] +impl crate::Resettable for PER_DITH5_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pac/atsamc21g/src/tcc0/per_dith6_mode.rs b/pac/atsamc21g/src/tcc0/per_dith6_mode.rs new file mode 100644 index 000000000000..67880e220a9c --- /dev/null +++ b/pac/atsamc21g/src/tcc0/per_dith6_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PER_DITH6_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PER_DITH6_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHER` reader - Dithering Cycle Number"] +pub struct DITHER_R(crate::FieldReader); +impl DITHER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHER` writer - Dithering Cycle Number"] +pub struct DITHER_W<'a> { + w: &'a mut W, +} +impl<'a> DITHER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +#[doc = "Field `PER` reader - Period Value"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` writer - Period Value"] +pub struct PER_W<'a> { + w: &'a mut W, +} +impl<'a> PER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0003_ffff << 6)) | ((value as u32 & 0x0003_ffff) << 6); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&self) -> DITHER_R { + DITHER_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:23 - Period Value"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(((self.bits >> 6) & 0x0003_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:5 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&mut self) -> DITHER_W { + DITHER_W { w: self } + } + #[doc = "Bits 6:23 - Period Value"] + #[inline(always)] + pub fn per(&mut self) -> PER_W { + PER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [per_dith6_mode](index.html) module"] +pub struct PER_DITH6_MODE_SPEC; +impl crate::RegisterSpec for PER_DITH6_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [per_dith6_mode::R](R) reader structure"] +impl crate::Readable for PER_DITH6_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [per_dith6_mode::W](W) writer structure"] +impl crate::Writable for PER_DITH6_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PER_DITH6_MODE to value 0xffff_ffff"] +impl crate::Resettable for PER_DITH6_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pac/atsamc21g/src/tcc0/perbuf.rs b/pac/atsamc21g/src/tcc0/perbuf.rs new file mode 100644 index 000000000000..169f17479616 --- /dev/null +++ b/pac/atsamc21g/src/tcc0/perbuf.rs @@ -0,0 +1,103 @@ +#[doc = "Register `PERBUF` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PERBUF` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PERBUF` reader - Period Buffer Value"] +pub struct PERBUF_R(crate::FieldReader); +impl PERBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + PERBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERBUF` writer - Period Buffer Value"] +pub struct PERBUF_W<'a> { + w: &'a mut W, +} +impl<'a> PERBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Period Buffer Value"] + #[inline(always)] + pub fn perbuf(&self) -> PERBUF_R { + PERBUF_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Period Buffer Value"] + #[inline(always)] + pub fn perbuf(&mut self) -> PERBUF_W { + PERBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [perbuf](index.html) module"] +pub struct PERBUF_SPEC; +impl crate::RegisterSpec for PERBUF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [perbuf::R](R) reader structure"] +impl crate::Readable for PERBUF_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [perbuf::W](W) writer structure"] +impl crate::Writable for PERBUF_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PERBUF to value 0xffff_ffff"] +impl crate::Resettable for PERBUF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pac/atsamc21g/src/tcc0/perbuf_dith4_mode.rs b/pac/atsamc21g/src/tcc0/perbuf_dith4_mode.rs new file mode 100644 index 000000000000..ccf96ecef185 --- /dev/null +++ b/pac/atsamc21g/src/tcc0/perbuf_dith4_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PERBUF_DITH4_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PERBUF_DITH4_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHERBUF` reader - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_R(crate::FieldReader); +impl DITHERBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHERBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHERBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHERBUF` writer - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_W<'a> { + w: &'a mut W, +} +impl<'a> DITHERBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Field `PERBUF` reader - Period Buffer Value"] +pub struct PERBUF_R(crate::FieldReader); +impl PERBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + PERBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERBUF` writer - Period Buffer Value"] +pub struct PERBUF_W<'a> { + w: &'a mut W, +} +impl<'a> PERBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x000f_ffff << 4)) | ((value as u32 & 0x000f_ffff) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&self) -> DITHERBUF_R { + DITHERBUF_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:23 - Period Buffer Value"] + #[inline(always)] + pub fn perbuf(&self) -> PERBUF_R { + PERBUF_R::new(((self.bits >> 4) & 0x000f_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:3 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&mut self) -> DITHERBUF_W { + DITHERBUF_W { w: self } + } + #[doc = "Bits 4:23 - Period Buffer Value"] + #[inline(always)] + pub fn perbuf(&mut self) -> PERBUF_W { + PERBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [perbuf_dith4_mode](index.html) module"] +pub struct PERBUF_DITH4_MODE_SPEC; +impl crate::RegisterSpec for PERBUF_DITH4_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [perbuf_dith4_mode::R](R) reader structure"] +impl crate::Readable for PERBUF_DITH4_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [perbuf_dith4_mode::W](W) writer structure"] +impl crate::Writable for PERBUF_DITH4_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PERBUF_DITH4_MODE to value 0xffff_ffff"] +impl crate::Resettable for PERBUF_DITH4_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pac/atsamc21g/src/tcc0/perbuf_dith5_mode.rs b/pac/atsamc21g/src/tcc0/perbuf_dith5_mode.rs new file mode 100644 index 000000000000..d55f6d52c5ba --- /dev/null +++ b/pac/atsamc21g/src/tcc0/perbuf_dith5_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PERBUF_DITH5_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PERBUF_DITH5_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHERBUF` reader - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_R(crate::FieldReader); +impl DITHERBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHERBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHERBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHERBUF` writer - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_W<'a> { + w: &'a mut W, +} +impl<'a> DITHERBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f); + self.w + } +} +#[doc = "Field `PERBUF` reader - Period Buffer Value"] +pub struct PERBUF_R(crate::FieldReader); +impl PERBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + PERBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERBUF` writer - Period Buffer Value"] +pub struct PERBUF_W<'a> { + w: &'a mut W, +} +impl<'a> PERBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0007_ffff << 5)) | ((value as u32 & 0x0007_ffff) << 5); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&self) -> DITHERBUF_R { + DITHERBUF_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:23 - Period Buffer Value"] + #[inline(always)] + pub fn perbuf(&self) -> PERBUF_R { + PERBUF_R::new(((self.bits >> 5) & 0x0007_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:4 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&mut self) -> DITHERBUF_W { + DITHERBUF_W { w: self } + } + #[doc = "Bits 5:23 - Period Buffer Value"] + #[inline(always)] + pub fn perbuf(&mut self) -> PERBUF_W { + PERBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [perbuf_dith5_mode](index.html) module"] +pub struct PERBUF_DITH5_MODE_SPEC; +impl crate::RegisterSpec for PERBUF_DITH5_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [perbuf_dith5_mode::R](R) reader structure"] +impl crate::Readable for PERBUF_DITH5_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [perbuf_dith5_mode::W](W) writer structure"] +impl crate::Writable for PERBUF_DITH5_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PERBUF_DITH5_MODE to value 0xffff_ffff"] +impl crate::Resettable for PERBUF_DITH5_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pac/atsamc21g/src/tcc0/perbuf_dith6_mode.rs b/pac/atsamc21g/src/tcc0/perbuf_dith6_mode.rs new file mode 100644 index 000000000000..983c849f9073 --- /dev/null +++ b/pac/atsamc21g/src/tcc0/perbuf_dith6_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PERBUF_DITH6_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PERBUF_DITH6_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHERBUF` reader - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_R(crate::FieldReader); +impl DITHERBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHERBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHERBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHERBUF` writer - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_W<'a> { + w: &'a mut W, +} +impl<'a> DITHERBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +#[doc = "Field `PERBUF` reader - Period Buffer Value"] +pub struct PERBUF_R(crate::FieldReader); +impl PERBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + PERBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERBUF` writer - Period Buffer Value"] +pub struct PERBUF_W<'a> { + w: &'a mut W, +} +impl<'a> PERBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0003_ffff << 6)) | ((value as u32 & 0x0003_ffff) << 6); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&self) -> DITHERBUF_R { + DITHERBUF_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:23 - Period Buffer Value"] + #[inline(always)] + pub fn perbuf(&self) -> PERBUF_R { + PERBUF_R::new(((self.bits >> 6) & 0x0003_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:5 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&mut self) -> DITHERBUF_W { + DITHERBUF_W { w: self } + } + #[doc = "Bits 6:23 - Period Buffer Value"] + #[inline(always)] + pub fn perbuf(&mut self) -> PERBUF_W { + PERBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [perbuf_dith6_mode](index.html) module"] +pub struct PERBUF_DITH6_MODE_SPEC; +impl crate::RegisterSpec for PERBUF_DITH6_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [perbuf_dith6_mode::R](R) reader structure"] +impl crate::Readable for PERBUF_DITH6_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [perbuf_dith6_mode::W](W) writer structure"] +impl crate::Writable for PERBUF_DITH6_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PERBUF_DITH6_MODE to value 0xffff_ffff"] +impl crate::Resettable for PERBUF_DITH6_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pac/atsamc21g/src/tcc0/status.rs b/pac/atsamc21g/src/tcc0/status.rs new file mode 100644 index 000000000000..eecd909e6093 --- /dev/null +++ b/pac/atsamc21g/src/tcc0/status.rs @@ -0,0 +1,1147 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `STOP` reader - Stop"] +pub struct STOP_R(crate::FieldReader); +impl STOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STOP` writer - Stop"] +pub struct STOP_W<'a> { + w: &'a mut W, +} +impl<'a> STOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `IDX` reader - Ramp"] +pub struct IDX_R(crate::FieldReader); +impl IDX_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IDX_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IDX_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IDX` writer - Ramp"] +pub struct IDX_W<'a> { + w: &'a mut W, +} +impl<'a> IDX_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `UFS` reader - Non-recoverable Update Fault State"] +pub struct UFS_R(crate::FieldReader); +impl UFS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UFS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for UFS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `UFS` writer - Non-recoverable Update Fault State"] +pub struct UFS_W<'a> { + w: &'a mut W, +} +impl<'a> UFS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `DFS` reader - Non-Recoverable Debug Fault State"] +pub struct DFS_R(crate::FieldReader); +impl DFS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFS` writer - Non-Recoverable Debug Fault State"] +pub struct DFS_W<'a> { + w: &'a mut W, +} +impl<'a> DFS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `SLAVE` reader - Slave"] +pub struct SLAVE_R(crate::FieldReader); +impl SLAVE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLAVE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SLAVE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLAVE` writer - Slave"] +pub struct SLAVE_W<'a> { + w: &'a mut W, +} +impl<'a> SLAVE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PATTBUFV` reader - Pattern Buffer Valid"] +pub struct PATTBUFV_R(crate::FieldReader); +impl PATTBUFV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PATTBUFV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PATTBUFV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PATTBUFV` writer - Pattern Buffer Valid"] +pub struct PATTBUFV_W<'a> { + w: &'a mut W, +} +impl<'a> PATTBUFV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PERBUFV` reader - Period Buffer Valid"] +pub struct PERBUFV_R(crate::FieldReader); +impl PERBUFV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PERBUFV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERBUFV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERBUFV` writer - Period Buffer Valid"] +pub struct PERBUFV_W<'a> { + w: &'a mut W, +} +impl<'a> PERBUFV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `FAULTAIN` reader - Recoverable Fault A Input"] +pub struct FAULTAIN_R(crate::FieldReader); +impl FAULTAIN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTAIN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTAIN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTAIN` writer - Recoverable Fault A Input"] +pub struct FAULTAIN_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTAIN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `FAULTBIN` reader - Recoverable Fault B Input"] +pub struct FAULTBIN_R(crate::FieldReader); +impl FAULTBIN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTBIN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTBIN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTBIN` writer - Recoverable Fault B Input"] +pub struct FAULTBIN_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTBIN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `FAULT0IN` reader - Non-Recoverable Fault0 Input"] +pub struct FAULT0IN_R(crate::FieldReader); +impl FAULT0IN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT0IN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT0IN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT0IN` writer - Non-Recoverable Fault0 Input"] +pub struct FAULT0IN_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT0IN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `FAULT1IN` reader - Non-Recoverable Fault1 Input"] +pub struct FAULT1IN_R(crate::FieldReader); +impl FAULT1IN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT1IN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT1IN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT1IN` writer - Non-Recoverable Fault1 Input"] +pub struct FAULT1IN_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT1IN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `FAULTA` reader - Recoverable Fault A State"] +pub struct FAULTA_R(crate::FieldReader); +impl FAULTA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTA` writer - Recoverable Fault A State"] +pub struct FAULTA_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `FAULTB` reader - Recoverable Fault B State"] +pub struct FAULTB_R(crate::FieldReader); +impl FAULTB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTB` writer - Recoverable Fault B State"] +pub struct FAULTB_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `FAULT0` reader - Non-Recoverable Fault 0 State"] +pub struct FAULT0_R(crate::FieldReader); +impl FAULT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT0` writer - Non-Recoverable Fault 0 State"] +pub struct FAULT0_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `FAULT1` reader - Non-Recoverable Fault 1 State"] +pub struct FAULT1_R(crate::FieldReader); +impl FAULT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT1` writer - Non-Recoverable Fault 1 State"] +pub struct FAULT1_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `CCBUFV0` reader - Compare Channel 0 Buffer Valid"] +pub struct CCBUFV0_R(crate::FieldReader); +impl CCBUFV0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBUFV0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUFV0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUFV0` writer - Compare Channel 0 Buffer Valid"] +pub struct CCBUFV0_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUFV0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `CCBUFV1` reader - Compare Channel 1 Buffer Valid"] +pub struct CCBUFV1_R(crate::FieldReader); +impl CCBUFV1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBUFV1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUFV1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUFV1` writer - Compare Channel 1 Buffer Valid"] +pub struct CCBUFV1_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUFV1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `CCBUFV2` reader - Compare Channel 2 Buffer Valid"] +pub struct CCBUFV2_R(crate::FieldReader); +impl CCBUFV2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBUFV2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUFV2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUFV2` writer - Compare Channel 2 Buffer Valid"] +pub struct CCBUFV2_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUFV2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `CCBUFV3` reader - Compare Channel 3 Buffer Valid"] +pub struct CCBUFV3_R(crate::FieldReader); +impl CCBUFV3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBUFV3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUFV3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUFV3` writer - Compare Channel 3 Buffer Valid"] +pub struct CCBUFV3_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUFV3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `CMP0` reader - Compare Channel 0 Value"] +pub struct CMP0_R(crate::FieldReader); +impl CMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP0` writer - Compare Channel 0 Value"] +pub struct CMP0_W<'a> { + w: &'a mut W, +} +impl<'a> CMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `CMP1` reader - Compare Channel 1 Value"] +pub struct CMP1_R(crate::FieldReader); +impl CMP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP1` writer - Compare Channel 1 Value"] +pub struct CMP1_W<'a> { + w: &'a mut W, +} +impl<'a> CMP1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `CMP2` reader - Compare Channel 2 Value"] +pub struct CMP2_R(crate::FieldReader); +impl CMP2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP2` writer - Compare Channel 2 Value"] +pub struct CMP2_W<'a> { + w: &'a mut W, +} +impl<'a> CMP2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `CMP3` reader - Compare Channel 3 Value"] +pub struct CMP3_R(crate::FieldReader); +impl CMP3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP3` writer - Compare Channel 3 Value"] +pub struct CMP3_W<'a> { + w: &'a mut W, +} +impl<'a> CMP3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +impl R { + #[doc = "Bit 0 - Stop"] + #[inline(always)] + pub fn stop(&self) -> STOP_R { + STOP_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Ramp"] + #[inline(always)] + pub fn idx(&self) -> IDX_R { + IDX_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Non-recoverable Update Fault State"] + #[inline(always)] + pub fn ufs(&self) -> UFS_R { + UFS_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Non-Recoverable Debug Fault State"] + #[inline(always)] + pub fn dfs(&self) -> DFS_R { + DFS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Slave"] + #[inline(always)] + pub fn slave(&self) -> SLAVE_R { + SLAVE_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Pattern Buffer Valid"] + #[inline(always)] + pub fn pattbufv(&self) -> PATTBUFV_R { + PATTBUFV_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 7 - Period Buffer Valid"] + #[inline(always)] + pub fn perbufv(&self) -> PERBUFV_R { + PERBUFV_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Recoverable Fault A Input"] + #[inline(always)] + pub fn faultain(&self) -> FAULTAIN_R { + FAULTAIN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Recoverable Fault B Input"] + #[inline(always)] + pub fn faultbin(&self) -> FAULTBIN_R { + FAULTBIN_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Non-Recoverable Fault0 Input"] + #[inline(always)] + pub fn fault0in(&self) -> FAULT0IN_R { + FAULT0IN_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Non-Recoverable Fault1 Input"] + #[inline(always)] + pub fn fault1in(&self) -> FAULT1IN_R { + FAULT1IN_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Recoverable Fault A State"] + #[inline(always)] + pub fn faulta(&self) -> FAULTA_R { + FAULTA_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Recoverable Fault B State"] + #[inline(always)] + pub fn faultb(&self) -> FAULTB_R { + FAULTB_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Non-Recoverable Fault 0 State"] + #[inline(always)] + pub fn fault0(&self) -> FAULT0_R { + FAULT0_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Non-Recoverable Fault 1 State"] + #[inline(always)] + pub fn fault1(&self) -> FAULT1_R { + FAULT1_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Compare Channel 0 Buffer Valid"] + #[inline(always)] + pub fn ccbufv0(&self) -> CCBUFV0_R { + CCBUFV0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Compare Channel 1 Buffer Valid"] + #[inline(always)] + pub fn ccbufv1(&self) -> CCBUFV1_R { + CCBUFV1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Compare Channel 2 Buffer Valid"] + #[inline(always)] + pub fn ccbufv2(&self) -> CCBUFV2_R { + CCBUFV2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Compare Channel 3 Buffer Valid"] + #[inline(always)] + pub fn ccbufv3(&self) -> CCBUFV3_R { + CCBUFV3_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 24 - Compare Channel 0 Value"] + #[inline(always)] + pub fn cmp0(&self) -> CMP0_R { + CMP0_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Compare Channel 1 Value"] + #[inline(always)] + pub fn cmp1(&self) -> CMP1_R { + CMP1_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Compare Channel 2 Value"] + #[inline(always)] + pub fn cmp2(&self) -> CMP2_R { + CMP2_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Compare Channel 3 Value"] + #[inline(always)] + pub fn cmp3(&self) -> CMP3_R { + CMP3_R::new(((self.bits >> 27) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Stop"] + #[inline(always)] + pub fn stop(&mut self) -> STOP_W { + STOP_W { w: self } + } + #[doc = "Bit 1 - Ramp"] + #[inline(always)] + pub fn idx(&mut self) -> IDX_W { + IDX_W { w: self } + } + #[doc = "Bit 2 - Non-recoverable Update Fault State"] + #[inline(always)] + pub fn ufs(&mut self) -> UFS_W { + UFS_W { w: self } + } + #[doc = "Bit 3 - Non-Recoverable Debug Fault State"] + #[inline(always)] + pub fn dfs(&mut self) -> DFS_W { + DFS_W { w: self } + } + #[doc = "Bit 4 - Slave"] + #[inline(always)] + pub fn slave(&mut self) -> SLAVE_W { + SLAVE_W { w: self } + } + #[doc = "Bit 5 - Pattern Buffer Valid"] + #[inline(always)] + pub fn pattbufv(&mut self) -> PATTBUFV_W { + PATTBUFV_W { w: self } + } + #[doc = "Bit 7 - Period Buffer Valid"] + #[inline(always)] + pub fn perbufv(&mut self) -> PERBUFV_W { + PERBUFV_W { w: self } + } + #[doc = "Bit 8 - Recoverable Fault A Input"] + #[inline(always)] + pub fn faultain(&mut self) -> FAULTAIN_W { + FAULTAIN_W { w: self } + } + #[doc = "Bit 9 - Recoverable Fault B Input"] + #[inline(always)] + pub fn faultbin(&mut self) -> FAULTBIN_W { + FAULTBIN_W { w: self } + } + #[doc = "Bit 10 - Non-Recoverable Fault0 Input"] + #[inline(always)] + pub fn fault0in(&mut self) -> FAULT0IN_W { + FAULT0IN_W { w: self } + } + #[doc = "Bit 11 - Non-Recoverable Fault1 Input"] + #[inline(always)] + pub fn fault1in(&mut self) -> FAULT1IN_W { + FAULT1IN_W { w: self } + } + #[doc = "Bit 12 - Recoverable Fault A State"] + #[inline(always)] + pub fn faulta(&mut self) -> FAULTA_W { + FAULTA_W { w: self } + } + #[doc = "Bit 13 - Recoverable Fault B State"] + #[inline(always)] + pub fn faultb(&mut self) -> FAULTB_W { + FAULTB_W { w: self } + } + #[doc = "Bit 14 - Non-Recoverable Fault 0 State"] + #[inline(always)] + pub fn fault0(&mut self) -> FAULT0_W { + FAULT0_W { w: self } + } + #[doc = "Bit 15 - Non-Recoverable Fault 1 State"] + #[inline(always)] + pub fn fault1(&mut self) -> FAULT1_W { + FAULT1_W { w: self } + } + #[doc = "Bit 16 - Compare Channel 0 Buffer Valid"] + #[inline(always)] + pub fn ccbufv0(&mut self) -> CCBUFV0_W { + CCBUFV0_W { w: self } + } + #[doc = "Bit 17 - Compare Channel 1 Buffer Valid"] + #[inline(always)] + pub fn ccbufv1(&mut self) -> CCBUFV1_W { + CCBUFV1_W { w: self } + } + #[doc = "Bit 18 - Compare Channel 2 Buffer Valid"] + #[inline(always)] + pub fn ccbufv2(&mut self) -> CCBUFV2_W { + CCBUFV2_W { w: self } + } + #[doc = "Bit 19 - Compare Channel 3 Buffer Valid"] + #[inline(always)] + pub fn ccbufv3(&mut self) -> CCBUFV3_W { + CCBUFV3_W { w: self } + } + #[doc = "Bit 24 - Compare Channel 0 Value"] + #[inline(always)] + pub fn cmp0(&mut self) -> CMP0_W { + CMP0_W { w: self } + } + #[doc = "Bit 25 - Compare Channel 1 Value"] + #[inline(always)] + pub fn cmp1(&mut self) -> CMP1_W { + CMP1_W { w: self } + } + #[doc = "Bit 26 - Compare Channel 2 Value"] + #[inline(always)] + pub fn cmp2(&mut self) -> CMP2_W { + CMP2_W { w: self } + } + #[doc = "Bit 27 - Compare Channel 3 Value"] + #[inline(always)] + pub fn cmp3(&mut self) -> CMP3_W { + CMP3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0x01"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pac/atsamc21g/src/tcc0/syncbusy.rs b/pac/atsamc21g/src/tcc0/syncbusy.rs new file mode 100644 index 000000000000..db0788c3f206 --- /dev/null +++ b/pac/atsamc21g/src/tcc0/syncbusy.rs @@ -0,0 +1,273 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Swrst Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - Enable Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLB` reader - Ctrlb Busy"] +pub struct CTRLB_R(crate::FieldReader); +impl CTRLB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STATUS` reader - Status Busy"] +pub struct STATUS_R(crate::FieldReader); +impl STATUS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STATUS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STATUS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` reader - Count Busy"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PATT` reader - Pattern Busy"] +pub struct PATT_R(crate::FieldReader); +impl PATT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PATT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PATT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAVE` reader - Wave Busy"] +pub struct WAVE_R(crate::FieldReader); +impl WAVE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAVE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAVE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` reader - Period Busy"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC0` reader - Compare Channel 0 Busy"] +pub struct CC0_R(crate::FieldReader); +impl CC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC1` reader - Compare Channel 1 Busy"] +pub struct CC1_R(crate::FieldReader); +impl CC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC2` reader - Compare Channel 2 Busy"] +pub struct CC2_R(crate::FieldReader); +impl CC2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC3` reader - Compare Channel 3 Busy"] +pub struct CC3_R(crate::FieldReader); +impl CC3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Swrst Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Ctrlb Busy"] + #[inline(always)] + pub fn ctrlb(&self) -> CTRLB_R { + CTRLB_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Status Busy"] + #[inline(always)] + pub fn status(&self) -> STATUS_R { + STATUS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Count Busy"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Pattern Busy"] + #[inline(always)] + pub fn patt(&self) -> PATT_R { + PATT_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Wave Busy"] + #[inline(always)] + pub fn wave(&self) -> WAVE_R { + WAVE_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Period Busy"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Compare Channel 0 Busy"] + #[inline(always)] + pub fn cc0(&self) -> CC0_R { + CC0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Compare Channel 1 Busy"] + #[inline(always)] + pub fn cc1(&self) -> CC1_R { + CC1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Compare Channel 2 Busy"] + #[inline(always)] + pub fn cc2(&self) -> CC2_R { + CC2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Compare Channel 3 Busy"] + #[inline(always)] + pub fn cc3(&self) -> CC3_R { + CC3_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +#[doc = "Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/tcc0/wave.rs b/pac/atsamc21g/src/tcc0/wave.rs new file mode 100644 index 000000000000..8d092d429a91 --- /dev/null +++ b/pac/atsamc21g/src/tcc0/wave.rs @@ -0,0 +1,940 @@ +#[doc = "Register `WAVE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WAVE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Waveform Generation\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WAVEGEN_A { + #[doc = "0: Normal frequency"] + NFRQ = 0, + #[doc = "1: Match frequency"] + MFRQ = 1, + #[doc = "2: Normal PWM"] + NPWM = 2, + #[doc = "4: Dual-slope critical"] + DSCRITICAL = 4, + #[doc = "5: Dual-slope with interrupt/event condition when COUNT reaches ZERO"] + DSBOTTOM = 5, + #[doc = "6: Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP"] + DSBOTH = 6, + #[doc = "7: Dual-slope with interrupt/event condition when COUNT reaches TOP"] + DSTOP = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WAVEGEN_A) -> Self { + variant as _ + } +} +#[doc = "Field `WAVEGEN` reader - Waveform Generation"] +pub struct WAVEGEN_R(crate::FieldReader); +impl WAVEGEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WAVEGEN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(WAVEGEN_A::NFRQ), + 1 => Some(WAVEGEN_A::MFRQ), + 2 => Some(WAVEGEN_A::NPWM), + 4 => Some(WAVEGEN_A::DSCRITICAL), + 5 => Some(WAVEGEN_A::DSBOTTOM), + 6 => Some(WAVEGEN_A::DSBOTH), + 7 => Some(WAVEGEN_A::DSTOP), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NFRQ`"] + #[inline(always)] + pub fn is_nfrq(&self) -> bool { + **self == WAVEGEN_A::NFRQ + } + #[doc = "Checks if the value of the field is `MFRQ`"] + #[inline(always)] + pub fn is_mfrq(&self) -> bool { + **self == WAVEGEN_A::MFRQ + } + #[doc = "Checks if the value of the field is `NPWM`"] + #[inline(always)] + pub fn is_npwm(&self) -> bool { + **self == WAVEGEN_A::NPWM + } + #[doc = "Checks if the value of the field is `DSCRITICAL`"] + #[inline(always)] + pub fn is_dscritical(&self) -> bool { + **self == WAVEGEN_A::DSCRITICAL + } + #[doc = "Checks if the value of the field is `DSBOTTOM`"] + #[inline(always)] + pub fn is_dsbottom(&self) -> bool { + **self == WAVEGEN_A::DSBOTTOM + } + #[doc = "Checks if the value of the field is `DSBOTH`"] + #[inline(always)] + pub fn is_dsboth(&self) -> bool { + **self == WAVEGEN_A::DSBOTH + } + #[doc = "Checks if the value of the field is `DSTOP`"] + #[inline(always)] + pub fn is_dstop(&self) -> bool { + **self == WAVEGEN_A::DSTOP + } +} +impl core::ops::Deref for WAVEGEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAVEGEN` writer - Waveform Generation"] +pub struct WAVEGEN_W<'a> { + w: &'a mut W, +} +impl<'a> WAVEGEN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WAVEGEN_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Normal frequency"] + #[inline(always)] + pub fn nfrq(self) -> &'a mut W { + self.variant(WAVEGEN_A::NFRQ) + } + #[doc = "Match frequency"] + #[inline(always)] + pub fn mfrq(self) -> &'a mut W { + self.variant(WAVEGEN_A::MFRQ) + } + #[doc = "Normal PWM"] + #[inline(always)] + pub fn npwm(self) -> &'a mut W { + self.variant(WAVEGEN_A::NPWM) + } + #[doc = "Dual-slope critical"] + #[inline(always)] + pub fn dscritical(self) -> &'a mut W { + self.variant(WAVEGEN_A::DSCRITICAL) + } + #[doc = "Dual-slope with interrupt/event condition when COUNT reaches ZERO"] + #[inline(always)] + pub fn dsbottom(self) -> &'a mut W { + self.variant(WAVEGEN_A::DSBOTTOM) + } + #[doc = "Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP"] + #[inline(always)] + pub fn dsboth(self) -> &'a mut W { + self.variant(WAVEGEN_A::DSBOTH) + } + #[doc = "Dual-slope with interrupt/event condition when COUNT reaches TOP"] + #[inline(always)] + pub fn dstop(self) -> &'a mut W { + self.variant(WAVEGEN_A::DSTOP) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Ramp Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum RAMP_A { + #[doc = "0: RAMP1 operation"] + RAMP1 = 0, + #[doc = "1: Alternative RAMP2 operation"] + RAMP2A = 1, + #[doc = "2: RAMP2 operation"] + RAMP2 = 2, + #[doc = "3: Critical RAMP2 operation"] + RAMP2C = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RAMP_A) -> Self { + variant as _ + } +} +#[doc = "Field `RAMP` reader - Ramp Mode"] +pub struct RAMP_R(crate::FieldReader); +impl RAMP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RAMP_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RAMP_A { + match self.bits { + 0 => RAMP_A::RAMP1, + 1 => RAMP_A::RAMP2A, + 2 => RAMP_A::RAMP2, + 3 => RAMP_A::RAMP2C, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `RAMP1`"] + #[inline(always)] + pub fn is_ramp1(&self) -> bool { + **self == RAMP_A::RAMP1 + } + #[doc = "Checks if the value of the field is `RAMP2A`"] + #[inline(always)] + pub fn is_ramp2a(&self) -> bool { + **self == RAMP_A::RAMP2A + } + #[doc = "Checks if the value of the field is `RAMP2`"] + #[inline(always)] + pub fn is_ramp2(&self) -> bool { + **self == RAMP_A::RAMP2 + } + #[doc = "Checks if the value of the field is `RAMP2C`"] + #[inline(always)] + pub fn is_ramp2c(&self) -> bool { + **self == RAMP_A::RAMP2C + } +} +impl core::ops::Deref for RAMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RAMP` writer - Ramp Mode"] +pub struct RAMP_W<'a> { + w: &'a mut W, +} +impl<'a> RAMP_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RAMP_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "RAMP1 operation"] + #[inline(always)] + pub fn ramp1(self) -> &'a mut W { + self.variant(RAMP_A::RAMP1) + } + #[doc = "Alternative RAMP2 operation"] + #[inline(always)] + pub fn ramp2a(self) -> &'a mut W { + self.variant(RAMP_A::RAMP2A) + } + #[doc = "RAMP2 operation"] + #[inline(always)] + pub fn ramp2(self) -> &'a mut W { + self.variant(RAMP_A::RAMP2) + } + #[doc = "Critical RAMP2 operation"] + #[inline(always)] + pub fn ramp2c(self) -> &'a mut W { + self.variant(RAMP_A::RAMP2C) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u32 & 0x03) << 4); + self.w + } +} +#[doc = "Field `CIPEREN` reader - Circular period Enable"] +pub struct CIPEREN_R(crate::FieldReader); +impl CIPEREN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CIPEREN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CIPEREN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CIPEREN` writer - Circular period Enable"] +pub struct CIPEREN_W<'a> { + w: &'a mut W, +} +impl<'a> CIPEREN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CICCEN0` reader - Circular Channel 0 Enable"] +pub struct CICCEN0_R(crate::FieldReader); +impl CICCEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CICCEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CICCEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CICCEN0` writer - Circular Channel 0 Enable"] +pub struct CICCEN0_W<'a> { + w: &'a mut W, +} +impl<'a> CICCEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `CICCEN1` reader - Circular Channel 1 Enable"] +pub struct CICCEN1_R(crate::FieldReader); +impl CICCEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CICCEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CICCEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CICCEN1` writer - Circular Channel 1 Enable"] +pub struct CICCEN1_W<'a> { + w: &'a mut W, +} +impl<'a> CICCEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `CICCEN2` reader - Circular Channel 2 Enable"] +pub struct CICCEN2_R(crate::FieldReader); +impl CICCEN2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CICCEN2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CICCEN2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CICCEN2` writer - Circular Channel 2 Enable"] +pub struct CICCEN2_W<'a> { + w: &'a mut W, +} +impl<'a> CICCEN2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `CICCEN3` reader - Circular Channel 3 Enable"] +pub struct CICCEN3_R(crate::FieldReader); +impl CICCEN3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CICCEN3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CICCEN3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CICCEN3` writer - Circular Channel 3 Enable"] +pub struct CICCEN3_W<'a> { + w: &'a mut W, +} +impl<'a> CICCEN3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `POL0` reader - Channel 0 Polarity"] +pub struct POL0_R(crate::FieldReader); +impl POL0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + POL0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for POL0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `POL0` writer - Channel 0 Polarity"] +pub struct POL0_W<'a> { + w: &'a mut W, +} +impl<'a> POL0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `POL1` reader - Channel 1 Polarity"] +pub struct POL1_R(crate::FieldReader); +impl POL1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + POL1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for POL1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `POL1` writer - Channel 1 Polarity"] +pub struct POL1_W<'a> { + w: &'a mut W, +} +impl<'a> POL1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `POL2` reader - Channel 2 Polarity"] +pub struct POL2_R(crate::FieldReader); +impl POL2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + POL2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for POL2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `POL2` writer - Channel 2 Polarity"] +pub struct POL2_W<'a> { + w: &'a mut W, +} +impl<'a> POL2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `POL3` reader - Channel 3 Polarity"] +pub struct POL3_R(crate::FieldReader); +impl POL3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + POL3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for POL3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `POL3` writer - Channel 3 Polarity"] +pub struct POL3_W<'a> { + w: &'a mut W, +} +impl<'a> POL3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `SWAP0` reader - Swap DTI Output Pair 0"] +pub struct SWAP0_R(crate::FieldReader); +impl SWAP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWAP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWAP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWAP0` writer - Swap DTI Output Pair 0"] +pub struct SWAP0_W<'a> { + w: &'a mut W, +} +impl<'a> SWAP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `SWAP1` reader - Swap DTI Output Pair 1"] +pub struct SWAP1_R(crate::FieldReader); +impl SWAP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWAP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWAP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWAP1` writer - Swap DTI Output Pair 1"] +pub struct SWAP1_W<'a> { + w: &'a mut W, +} +impl<'a> SWAP1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `SWAP2` reader - Swap DTI Output Pair 2"] +pub struct SWAP2_R(crate::FieldReader); +impl SWAP2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWAP2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWAP2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWAP2` writer - Swap DTI Output Pair 2"] +pub struct SWAP2_W<'a> { + w: &'a mut W, +} +impl<'a> SWAP2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `SWAP3` reader - Swap DTI Output Pair 3"] +pub struct SWAP3_R(crate::FieldReader); +impl SWAP3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWAP3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWAP3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWAP3` writer - Swap DTI Output Pair 3"] +pub struct SWAP3_W<'a> { + w: &'a mut W, +} +impl<'a> SWAP3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Waveform Generation"] + #[inline(always)] + pub fn wavegen(&self) -> WAVEGEN_R { + WAVEGEN_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bits 4:5 - Ramp Mode"] + #[inline(always)] + pub fn ramp(&self) -> RAMP_R { + RAMP_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bit 7 - Circular period Enable"] + #[inline(always)] + pub fn ciperen(&self) -> CIPEREN_R { + CIPEREN_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Circular Channel 0 Enable"] + #[inline(always)] + pub fn ciccen0(&self) -> CICCEN0_R { + CICCEN0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Circular Channel 1 Enable"] + #[inline(always)] + pub fn ciccen1(&self) -> CICCEN1_R { + CICCEN1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Circular Channel 2 Enable"] + #[inline(always)] + pub fn ciccen2(&self) -> CICCEN2_R { + CICCEN2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Circular Channel 3 Enable"] + #[inline(always)] + pub fn ciccen3(&self) -> CICCEN3_R { + CICCEN3_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 16 - Channel 0 Polarity"] + #[inline(always)] + pub fn pol0(&self) -> POL0_R { + POL0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Channel 1 Polarity"] + #[inline(always)] + pub fn pol1(&self) -> POL1_R { + POL1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Channel 2 Polarity"] + #[inline(always)] + pub fn pol2(&self) -> POL2_R { + POL2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Channel 3 Polarity"] + #[inline(always)] + pub fn pol3(&self) -> POL3_R { + POL3_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 24 - Swap DTI Output Pair 0"] + #[inline(always)] + pub fn swap0(&self) -> SWAP0_R { + SWAP0_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Swap DTI Output Pair 1"] + #[inline(always)] + pub fn swap1(&self) -> SWAP1_R { + SWAP1_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Swap DTI Output Pair 2"] + #[inline(always)] + pub fn swap2(&self) -> SWAP2_R { + SWAP2_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Swap DTI Output Pair 3"] + #[inline(always)] + pub fn swap3(&self) -> SWAP3_R { + SWAP3_R::new(((self.bits >> 27) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Waveform Generation"] + #[inline(always)] + pub fn wavegen(&mut self) -> WAVEGEN_W { + WAVEGEN_W { w: self } + } + #[doc = "Bits 4:5 - Ramp Mode"] + #[inline(always)] + pub fn ramp(&mut self) -> RAMP_W { + RAMP_W { w: self } + } + #[doc = "Bit 7 - Circular period Enable"] + #[inline(always)] + pub fn ciperen(&mut self) -> CIPEREN_W { + CIPEREN_W { w: self } + } + #[doc = "Bit 8 - Circular Channel 0 Enable"] + #[inline(always)] + pub fn ciccen0(&mut self) -> CICCEN0_W { + CICCEN0_W { w: self } + } + #[doc = "Bit 9 - Circular Channel 1 Enable"] + #[inline(always)] + pub fn ciccen1(&mut self) -> CICCEN1_W { + CICCEN1_W { w: self } + } + #[doc = "Bit 10 - Circular Channel 2 Enable"] + #[inline(always)] + pub fn ciccen2(&mut self) -> CICCEN2_W { + CICCEN2_W { w: self } + } + #[doc = "Bit 11 - Circular Channel 3 Enable"] + #[inline(always)] + pub fn ciccen3(&mut self) -> CICCEN3_W { + CICCEN3_W { w: self } + } + #[doc = "Bit 16 - Channel 0 Polarity"] + #[inline(always)] + pub fn pol0(&mut self) -> POL0_W { + POL0_W { w: self } + } + #[doc = "Bit 17 - Channel 1 Polarity"] + #[inline(always)] + pub fn pol1(&mut self) -> POL1_W { + POL1_W { w: self } + } + #[doc = "Bit 18 - Channel 2 Polarity"] + #[inline(always)] + pub fn pol2(&mut self) -> POL2_W { + POL2_W { w: self } + } + #[doc = "Bit 19 - Channel 3 Polarity"] + #[inline(always)] + pub fn pol3(&mut self) -> POL3_W { + POL3_W { w: self } + } + #[doc = "Bit 24 - Swap DTI Output Pair 0"] + #[inline(always)] + pub fn swap0(&mut self) -> SWAP0_W { + SWAP0_W { w: self } + } + #[doc = "Bit 25 - Swap DTI Output Pair 1"] + #[inline(always)] + pub fn swap1(&mut self) -> SWAP1_W { + SWAP1_W { w: self } + } + #[doc = "Bit 26 - Swap DTI Output Pair 2"] + #[inline(always)] + pub fn swap2(&mut self) -> SWAP2_W { + SWAP2_W { w: self } + } + #[doc = "Bit 27 - Swap DTI Output Pair 3"] + #[inline(always)] + pub fn swap3(&mut self) -> SWAP3_W { + SWAP3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Waveform Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wave](index.html) module"] +pub struct WAVE_SPEC; +impl crate::RegisterSpec for WAVE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [wave::R](R) reader structure"] +impl crate::Readable for WAVE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wave::W](W) writer structure"] +impl crate::Writable for WAVE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WAVE to value 0"] +impl crate::Resettable for WAVE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/tcc0/wexctrl.rs b/pac/atsamc21g/src/tcc0/wexctrl.rs new file mode 100644 index 000000000000..8eb0d29cbee5 --- /dev/null +++ b/pac/atsamc21g/src/tcc0/wexctrl.rs @@ -0,0 +1,365 @@ +#[doc = "Register `WEXCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WEXCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OTMX` reader - Output Matrix"] +pub struct OTMX_R(crate::FieldReader); +impl OTMX_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + OTMX_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OTMX_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OTMX` writer - Output Matrix"] +pub struct OTMX_W<'a> { + w: &'a mut W, +} +impl<'a> OTMX_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u32 & 0x03); + self.w + } +} +#[doc = "Field `DTIEN0` reader - Dead-time Insertion Generator 0 Enable"] +pub struct DTIEN0_R(crate::FieldReader); +impl DTIEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DTIEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DTIEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DTIEN0` writer - Dead-time Insertion Generator 0 Enable"] +pub struct DTIEN0_W<'a> { + w: &'a mut W, +} +impl<'a> DTIEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `DTIEN1` reader - Dead-time Insertion Generator 1 Enable"] +pub struct DTIEN1_R(crate::FieldReader); +impl DTIEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DTIEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DTIEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DTIEN1` writer - Dead-time Insertion Generator 1 Enable"] +pub struct DTIEN1_W<'a> { + w: &'a mut W, +} +impl<'a> DTIEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `DTIEN2` reader - Dead-time Insertion Generator 2 Enable"] +pub struct DTIEN2_R(crate::FieldReader); +impl DTIEN2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DTIEN2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DTIEN2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DTIEN2` writer - Dead-time Insertion Generator 2 Enable"] +pub struct DTIEN2_W<'a> { + w: &'a mut W, +} +impl<'a> DTIEN2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `DTIEN3` reader - Dead-time Insertion Generator 3 Enable"] +pub struct DTIEN3_R(crate::FieldReader); +impl DTIEN3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DTIEN3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DTIEN3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DTIEN3` writer - Dead-time Insertion Generator 3 Enable"] +pub struct DTIEN3_W<'a> { + w: &'a mut W, +} +impl<'a> DTIEN3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `DTLS` reader - Dead-time Low Side Outputs Value"] +pub struct DTLS_R(crate::FieldReader); +impl DTLS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DTLS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DTLS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DTLS` writer - Dead-time Low Side Outputs Value"] +pub struct DTLS_W<'a> { + w: &'a mut W, +} +impl<'a> DTLS_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +#[doc = "Field `DTHS` reader - Dead-time High Side Outputs Value"] +pub struct DTHS_R(crate::FieldReader); +impl DTHS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DTHS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DTHS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DTHS` writer - Dead-time High Side Outputs Value"] +pub struct DTHS_W<'a> { + w: &'a mut W, +} +impl<'a> DTHS_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 24)) | ((value as u32 & 0xff) << 24); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Output Matrix"] + #[inline(always)] + pub fn otmx(&self) -> OTMX_R { + OTMX_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bit 8 - Dead-time Insertion Generator 0 Enable"] + #[inline(always)] + pub fn dtien0(&self) -> DTIEN0_R { + DTIEN0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Dead-time Insertion Generator 1 Enable"] + #[inline(always)] + pub fn dtien1(&self) -> DTIEN1_R { + DTIEN1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Dead-time Insertion Generator 2 Enable"] + #[inline(always)] + pub fn dtien2(&self) -> DTIEN2_R { + DTIEN2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Dead-time Insertion Generator 3 Enable"] + #[inline(always)] + pub fn dtien3(&self) -> DTIEN3_R { + DTIEN3_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bits 16:23 - Dead-time Low Side Outputs Value"] + #[inline(always)] + pub fn dtls(&self) -> DTLS_R { + DTLS_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Dead-time High Side Outputs Value"] + #[inline(always)] + pub fn dths(&self) -> DTHS_R { + DTHS_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Output Matrix"] + #[inline(always)] + pub fn otmx(&mut self) -> OTMX_W { + OTMX_W { w: self } + } + #[doc = "Bit 8 - Dead-time Insertion Generator 0 Enable"] + #[inline(always)] + pub fn dtien0(&mut self) -> DTIEN0_W { + DTIEN0_W { w: self } + } + #[doc = "Bit 9 - Dead-time Insertion Generator 1 Enable"] + #[inline(always)] + pub fn dtien1(&mut self) -> DTIEN1_W { + DTIEN1_W { w: self } + } + #[doc = "Bit 10 - Dead-time Insertion Generator 2 Enable"] + #[inline(always)] + pub fn dtien2(&mut self) -> DTIEN2_W { + DTIEN2_W { w: self } + } + #[doc = "Bit 11 - Dead-time Insertion Generator 3 Enable"] + #[inline(always)] + pub fn dtien3(&mut self) -> DTIEN3_W { + DTIEN3_W { w: self } + } + #[doc = "Bits 16:23 - Dead-time Low Side Outputs Value"] + #[inline(always)] + pub fn dtls(&mut self) -> DTLS_W { + DTLS_W { w: self } + } + #[doc = "Bits 24:31 - Dead-time High Side Outputs Value"] + #[inline(always)] + pub fn dths(&mut self) -> DTHS_W { + DTHS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Waveform Extension Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wexctrl](index.html) module"] +pub struct WEXCTRL_SPEC; +impl crate::RegisterSpec for WEXCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [wexctrl::R](R) reader structure"] +impl crate::Readable for WEXCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wexctrl::W](W) writer structure"] +impl crate::Writable for WEXCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WEXCTRL to value 0"] +impl crate::Resettable for WEXCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/tsens.rs b/pac/atsamc21g/src/tsens.rs new file mode 100644 index 000000000000..3156dee6d87f --- /dev/null +++ b/pac/atsamc21g/src/tsens.rs @@ -0,0 +1,100 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control A Register"] + pub ctrla: crate::Reg, + #[doc = "0x01 - Control B Register"] + pub ctrlb: crate::Reg, + #[doc = "0x02 - Control C Register"] + pub ctrlc: crate::Reg, + #[doc = "0x03 - Event Control Register"] + pub evctrl: crate::Reg, + #[doc = "0x04 - Interrupt Enable Clear Register"] + pub intenclr: crate::Reg, + #[doc = "0x05 - Interrupt Enable Set Register"] + pub intenset: crate::Reg, + #[doc = "0x06 - Interrupt Flag Status and Clear Register"] + pub intflag: crate::Reg, + #[doc = "0x07 - Status Register"] + pub status: crate::Reg, + #[doc = "0x08 - Synchronization Busy Register"] + pub syncbusy: crate::Reg, + #[doc = "0x0c - Value Register"] + pub value: crate::Reg, + #[doc = "0x10 - Window Monitor Lower Threshold Register"] + pub winlt: crate::Reg, + #[doc = "0x14 - Window Monitor Upper Threshold Register"] + pub winut: crate::Reg, + #[doc = "0x18 - Gain Register"] + pub gain: crate::Reg, + #[doc = "0x1c - Offset Register"] + pub offset: crate::Reg, + #[doc = "0x20 - Calibration Register"] + pub cal: crate::Reg, + #[doc = "0x24 - Debug Control Register"] + pub dbgctrl: crate::Reg, +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A Register"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "Control B Register"] +pub mod ctrlb; +#[doc = "CTRLC register accessor: an alias for `Reg`"] +pub type CTRLC = crate::Reg; +#[doc = "Control C Register"] +pub mod ctrlc; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control Register"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear Register"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set Register"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear Register"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status Register"] +pub mod status; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Busy Register"] +pub mod syncbusy; +#[doc = "VALUE register accessor: an alias for `Reg`"] +pub type VALUE = crate::Reg; +#[doc = "Value Register"] +pub mod value; +#[doc = "WINLT register accessor: an alias for `Reg`"] +pub type WINLT = crate::Reg; +#[doc = "Window Monitor Lower Threshold Register"] +pub mod winlt; +#[doc = "WINUT register accessor: an alias for `Reg`"] +pub type WINUT = crate::Reg; +#[doc = "Window Monitor Upper Threshold Register"] +pub mod winut; +#[doc = "GAIN register accessor: an alias for `Reg`"] +pub type GAIN = crate::Reg; +#[doc = "Gain Register"] +pub mod gain; +#[doc = "OFFSET register accessor: an alias for `Reg`"] +pub type OFFSET = crate::Reg; +#[doc = "Offset Register"] +pub mod offset; +#[doc = "CAL register accessor: an alias for `Reg`"] +pub type CAL = crate::Reg; +#[doc = "Calibration Register"] +pub mod cal; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control Register"] +pub mod dbgctrl; diff --git a/pac/atsamc21g/src/tsens/cal.rs b/pac/atsamc21g/src/tsens/cal.rs new file mode 100644 index 000000000000..9b0d76eef9eb --- /dev/null +++ b/pac/atsamc21g/src/tsens/cal.rs @@ -0,0 +1,140 @@ +#[doc = "Register `CAL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CAL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FCAL` reader - Frequency Calibration"] +pub struct FCAL_R(crate::FieldReader); +impl FCAL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FCAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FCAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FCAL` writer - Frequency Calibration"] +pub struct FCAL_W<'a> { + w: &'a mut W, +} +impl<'a> FCAL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +#[doc = "Field `TCAL` reader - Temperature Calibration"] +pub struct TCAL_R(crate::FieldReader); +impl TCAL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TCAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCAL` writer - Temperature Calibration"] +pub struct TCAL_W<'a> { + w: &'a mut W, +} +impl<'a> TCAL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 8)) | ((value as u32 & 0x3f) << 8); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Frequency Calibration"] + #[inline(always)] + pub fn fcal(&self) -> FCAL_R { + FCAL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 8:13 - Temperature Calibration"] + #[inline(always)] + pub fn tcal(&self) -> TCAL_R { + TCAL_R::new(((self.bits >> 8) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - Frequency Calibration"] + #[inline(always)] + pub fn fcal(&mut self) -> FCAL_W { + FCAL_W { w: self } + } + #[doc = "Bits 8:13 - Temperature Calibration"] + #[inline(always)] + pub fn tcal(&mut self) -> TCAL_W { + TCAL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Calibration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cal](index.html) module"] +pub struct CAL_SPEC; +impl crate::RegisterSpec for CAL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cal::R](R) reader structure"] +impl crate::Readable for CAL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cal::W](W) writer structure"] +impl crate::Writable for CAL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CAL to value 0"] +impl crate::Resettable for CAL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/tsens/ctrla.rs b/pac/atsamc21g/src/tsens/ctrla.rs new file mode 100644 index 000000000000..6be7f2fc82f2 --- /dev/null +++ b/pac/atsamc21g/src/tsens/ctrla.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/tsens/ctrlb.rs b/pac/atsamc21g/src/tsens/ctrlb.rs new file mode 100644 index 000000000000..7d350e71fbf3 --- /dev/null +++ b/pac/atsamc21g/src/tsens/ctrlb.rs @@ -0,0 +1,72 @@ +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `START` writer - Start Measurement"] +pub struct START_W<'a> { + w: &'a mut W, +} +impl<'a> START_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0 - Start Measurement"] + #[inline(always)] + pub fn start(&mut self) -> START_W { + START_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u8; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/tsens/ctrlc.rs b/pac/atsamc21g/src/tsens/ctrlc.rs new file mode 100644 index 000000000000..82390cea825d --- /dev/null +++ b/pac/atsamc21g/src/tsens/ctrlc.rs @@ -0,0 +1,264 @@ +#[doc = "Register `CTRLC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Window Monitor Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WINMODE_A { + #[doc = "0: No window mode (default)"] + DISABLE = 0, + #[doc = "1: VALUE greater than WINLT"] + ABOVE = 1, + #[doc = "2: VALUE less than WINUT"] + BELOW = 2, + #[doc = "3: VALUE greater than WINLT and VALUE less than WINUT"] + INSIDE = 3, + #[doc = "4: VALUE less than WINLT or VALUE greater than WINUT"] + OUTSIDE = 4, + #[doc = "5: VALUE greater than WINUT with hysteresis to WINLT"] + HYST_ABOVE = 5, + #[doc = "6: VALUE less than WINLST with hysteresis to WINUT"] + HYST_BELOW = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WINMODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `WINMODE` reader - Window Monitor Mode"] +pub struct WINMODE_R(crate::FieldReader); +impl WINMODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WINMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(WINMODE_A::DISABLE), + 1 => Some(WINMODE_A::ABOVE), + 2 => Some(WINMODE_A::BELOW), + 3 => Some(WINMODE_A::INSIDE), + 4 => Some(WINMODE_A::OUTSIDE), + 5 => Some(WINMODE_A::HYST_ABOVE), + 6 => Some(WINMODE_A::HYST_BELOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == WINMODE_A::DISABLE + } + #[doc = "Checks if the value of the field is `ABOVE`"] + #[inline(always)] + pub fn is_above(&self) -> bool { + **self == WINMODE_A::ABOVE + } + #[doc = "Checks if the value of the field is `BELOW`"] + #[inline(always)] + pub fn is_below(&self) -> bool { + **self == WINMODE_A::BELOW + } + #[doc = "Checks if the value of the field is `INSIDE`"] + #[inline(always)] + pub fn is_inside(&self) -> bool { + **self == WINMODE_A::INSIDE + } + #[doc = "Checks if the value of the field is `OUTSIDE`"] + #[inline(always)] + pub fn is_outside(&self) -> bool { + **self == WINMODE_A::OUTSIDE + } + #[doc = "Checks if the value of the field is `HYST_ABOVE`"] + #[inline(always)] + pub fn is_hyst_above(&self) -> bool { + **self == WINMODE_A::HYST_ABOVE + } + #[doc = "Checks if the value of the field is `HYST_BELOW`"] + #[inline(always)] + pub fn is_hyst_below(&self) -> bool { + **self == WINMODE_A::HYST_BELOW + } +} +impl core::ops::Deref for WINMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMODE` writer - Window Monitor Mode"] +pub struct WINMODE_W<'a> { + w: &'a mut W, +} +impl<'a> WINMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WINMODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No window mode (default)"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(WINMODE_A::DISABLE) + } + #[doc = "VALUE greater than WINLT"] + #[inline(always)] + pub fn above(self) -> &'a mut W { + self.variant(WINMODE_A::ABOVE) + } + #[doc = "VALUE less than WINUT"] + #[inline(always)] + pub fn below(self) -> &'a mut W { + self.variant(WINMODE_A::BELOW) + } + #[doc = "VALUE greater than WINLT and VALUE less than WINUT"] + #[inline(always)] + pub fn inside(self) -> &'a mut W { + self.variant(WINMODE_A::INSIDE) + } + #[doc = "VALUE less than WINLT or VALUE greater than WINUT"] + #[inline(always)] + pub fn outside(self) -> &'a mut W { + self.variant(WINMODE_A::OUTSIDE) + } + #[doc = "VALUE greater than WINUT with hysteresis to WINLT"] + #[inline(always)] + pub fn hyst_above(self) -> &'a mut W { + self.variant(WINMODE_A::HYST_ABOVE) + } + #[doc = "VALUE less than WINLST with hysteresis to WINUT"] + #[inline(always)] + pub fn hyst_below(self) -> &'a mut W { + self.variant(WINMODE_A::HYST_BELOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +#[doc = "Field `FREERUN` reader - Free Running Measurement"] +pub struct FREERUN_R(crate::FieldReader); +impl FREERUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FREERUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FREERUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FREERUN` writer - Free Running Measurement"] +pub struct FREERUN_W<'a> { + w: &'a mut W, +} +impl<'a> FREERUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Window Monitor Mode"] + #[inline(always)] + pub fn winmode(&self) -> WINMODE_R { + WINMODE_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 4 - Free Running Measurement"] + #[inline(always)] + pub fn freerun(&self) -> FREERUN_R { + FREERUN_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Window Monitor Mode"] + #[inline(always)] + pub fn winmode(&mut self) -> WINMODE_W { + WINMODE_W { w: self } + } + #[doc = "Bit 4 - Free Running Measurement"] + #[inline(always)] + pub fn freerun(&mut self) -> FREERUN_W { + FREERUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control C Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlc](index.html) module"] +pub struct CTRLC_SPEC; +impl crate::RegisterSpec for CTRLC_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlc::R](R) reader structure"] +impl crate::Readable for CTRLC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlc::W](W) writer structure"] +impl crate::Writable for CTRLC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLC to value 0"] +impl crate::Resettable for CTRLC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/tsens/dbgctrl.rs b/pac/atsamc21g/src/tsens/dbgctrl.rs new file mode 100644 index 000000000000..dd129a857202 --- /dev/null +++ b/pac/atsamc21g/src/tsens/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Debug Run"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Debug Run"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/tsens/evctrl.rs b/pac/atsamc21g/src/tsens/evctrl.rs new file mode 100644 index 000000000000..20d0f3497e37 --- /dev/null +++ b/pac/atsamc21g/src/tsens/evctrl.rs @@ -0,0 +1,207 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `STARTEI` reader - Start Conversion Event Input Enable"] +pub struct STARTEI_R(crate::FieldReader); +impl STARTEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STARTEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STARTEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STARTEI` writer - Start Conversion Event Input Enable"] +pub struct STARTEI_W<'a> { + w: &'a mut W, +} +impl<'a> STARTEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `STARTINV` reader - Start Conversion Event Invert Enable"] +pub struct STARTINV_R(crate::FieldReader); +impl STARTINV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STARTINV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STARTINV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STARTINV` writer - Start Conversion Event Invert Enable"] +pub struct STARTINV_W<'a> { + w: &'a mut W, +} +impl<'a> STARTINV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WINEO` reader - Window Monitor Event Out"] +pub struct WINEO_R(crate::FieldReader); +impl WINEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINEO` writer - Window Monitor Event Out"] +pub struct WINEO_W<'a> { + w: &'a mut W, +} +impl<'a> WINEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Start Conversion Event Input Enable"] + #[inline(always)] + pub fn startei(&self) -> STARTEI_R { + STARTEI_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Start Conversion Event Invert Enable"] + #[inline(always)] + pub fn startinv(&self) -> STARTINV_R { + STARTINV_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Window Monitor Event Out"] + #[inline(always)] + pub fn wineo(&self) -> WINEO_R { + WINEO_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Start Conversion Event Input Enable"] + #[inline(always)] + pub fn startei(&mut self) -> STARTEI_W { + STARTEI_W { w: self } + } + #[doc = "Bit 1 - Start Conversion Event Invert Enable"] + #[inline(always)] + pub fn startinv(&mut self) -> STARTINV_W { + STARTINV_W { w: self } + } + #[doc = "Bit 2 - Window Monitor Event Out"] + #[inline(always)] + pub fn wineo(&mut self) -> WINEO_W { + WINEO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/tsens/gain.rs b/pac/atsamc21g/src/tsens/gain.rs new file mode 100644 index 000000000000..785bbef3b6a4 --- /dev/null +++ b/pac/atsamc21g/src/tsens/gain.rs @@ -0,0 +1,103 @@ +#[doc = "Register `GAIN` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GAIN` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `GAIN` reader - Time Amplifier Gain"] +pub struct GAIN_R(crate::FieldReader); +impl GAIN_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + GAIN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GAIN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GAIN` writer - Time Amplifier Gain"] +pub struct GAIN_W<'a> { + w: &'a mut W, +} +impl<'a> GAIN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Time Amplifier Gain"] + #[inline(always)] + pub fn gain(&self) -> GAIN_R { + GAIN_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Time Amplifier Gain"] + #[inline(always)] + pub fn gain(&mut self) -> GAIN_W { + GAIN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Gain Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gain](index.html) module"] +pub struct GAIN_SPEC; +impl crate::RegisterSpec for GAIN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gain::R](R) reader structure"] +impl crate::Readable for GAIN_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gain::W](W) writer structure"] +impl crate::Writable for GAIN_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets GAIN to value 0"] +impl crate::Resettable for GAIN_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/tsens/intenclr.rs b/pac/atsamc21g/src/tsens/intenclr.rs new file mode 100644 index 000000000000..2362cf7b512b --- /dev/null +++ b/pac/atsamc21g/src/tsens/intenclr.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RESRDY` reader - Result Ready Interrupt Enable"] +pub struct RESRDY_R(crate::FieldReader); +impl RESRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESRDY` writer - Result Ready Interrupt Enable"] +pub struct RESRDY_W<'a> { + w: &'a mut W, +} +impl<'a> RESRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `OVERRUN` reader - Overrun Interrupt Enable"] +pub struct OVERRUN_R(crate::FieldReader); +impl OVERRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVERRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVERRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVERRUN` writer - Overrun Interrupt Enable"] +pub struct OVERRUN_W<'a> { + w: &'a mut W, +} +impl<'a> OVERRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WINMON` reader - Window Monitor Interrupt Enable"] +pub struct WINMON_R(crate::FieldReader); +impl WINMON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINMON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINMON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMON` writer - Window Monitor Interrupt Enable"] +pub struct WINMON_W<'a> { + w: &'a mut W, +} +impl<'a> WINMON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +impl R { + #[doc = "Bit 0 - Result Ready Interrupt Enable"] + #[inline(always)] + pub fn resrdy(&self) -> RESRDY_R { + RESRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Overrun Interrupt Enable"] + #[inline(always)] + pub fn overrun(&self) -> OVERRUN_R { + OVERRUN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Window Monitor Interrupt Enable"] + #[inline(always)] + pub fn winmon(&self) -> WINMON_R { + WINMON_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 3) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Result Ready Interrupt Enable"] + #[inline(always)] + pub fn resrdy(&mut self) -> RESRDY_W { + RESRDY_W { w: self } + } + #[doc = "Bit 1 - Overrun Interrupt Enable"] + #[inline(always)] + pub fn overrun(&mut self) -> OVERRUN_W { + OVERRUN_W { w: self } + } + #[doc = "Bit 2 - Window Monitor Interrupt Enable"] + #[inline(always)] + pub fn winmon(&mut self) -> WINMON_W { + WINMON_W { w: self } + } + #[doc = "Bit 3 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/tsens/intenset.rs b/pac/atsamc21g/src/tsens/intenset.rs new file mode 100644 index 000000000000..51df8bb668f2 --- /dev/null +++ b/pac/atsamc21g/src/tsens/intenset.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RESRDY` reader - Result Ready Interrupt Enable"] +pub struct RESRDY_R(crate::FieldReader); +impl RESRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESRDY` writer - Result Ready Interrupt Enable"] +pub struct RESRDY_W<'a> { + w: &'a mut W, +} +impl<'a> RESRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `OVERRUN` reader - Overrun Interrupt Enable"] +pub struct OVERRUN_R(crate::FieldReader); +impl OVERRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVERRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVERRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVERRUN` writer - Overrun Interrupt Enable"] +pub struct OVERRUN_W<'a> { + w: &'a mut W, +} +impl<'a> OVERRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WINMON` reader - Window Monitor Interrupt Enable"] +pub struct WINMON_R(crate::FieldReader); +impl WINMON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINMON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINMON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMON` writer - Window Monitor Interrupt Enable"] +pub struct WINMON_W<'a> { + w: &'a mut W, +} +impl<'a> WINMON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +impl R { + #[doc = "Bit 0 - Result Ready Interrupt Enable"] + #[inline(always)] + pub fn resrdy(&self) -> RESRDY_R { + RESRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Overrun Interrupt Enable"] + #[inline(always)] + pub fn overrun(&self) -> OVERRUN_R { + OVERRUN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Window Monitor Interrupt Enable"] + #[inline(always)] + pub fn winmon(&self) -> WINMON_R { + WINMON_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 3) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Result Ready Interrupt Enable"] + #[inline(always)] + pub fn resrdy(&mut self) -> RESRDY_W { + RESRDY_W { w: self } + } + #[doc = "Bit 1 - Overrun Interrupt Enable"] + #[inline(always)] + pub fn overrun(&mut self) -> OVERRUN_W { + OVERRUN_W { w: self } + } + #[doc = "Bit 2 - Window Monitor Interrupt Enable"] + #[inline(always)] + pub fn winmon(&mut self) -> WINMON_W { + WINMON_W { w: self } + } + #[doc = "Bit 3 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/tsens/intflag.rs b/pac/atsamc21g/src/tsens/intflag.rs new file mode 100644 index 000000000000..5058a4f8712c --- /dev/null +++ b/pac/atsamc21g/src/tsens/intflag.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RESRDY` reader - Result Ready"] +pub struct RESRDY_R(crate::FieldReader); +impl RESRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESRDY` writer - Result Ready"] +pub struct RESRDY_W<'a> { + w: &'a mut W, +} +impl<'a> RESRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `OVERRUN` reader - Overrun"] +pub struct OVERRUN_R(crate::FieldReader); +impl OVERRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVERRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVERRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVERRUN` writer - Overrun"] +pub struct OVERRUN_W<'a> { + w: &'a mut W, +} +impl<'a> OVERRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WINMON` reader - Window Monitor"] +pub struct WINMON_R(crate::FieldReader); +impl WINMON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINMON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINMON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMON` writer - Window Monitor"] +pub struct WINMON_W<'a> { + w: &'a mut W, +} +impl<'a> WINMON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +impl R { + #[doc = "Bit 0 - Result Ready"] + #[inline(always)] + pub fn resrdy(&self) -> RESRDY_R { + RESRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Overrun"] + #[inline(always)] + pub fn overrun(&self) -> OVERRUN_R { + OVERRUN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Window Monitor"] + #[inline(always)] + pub fn winmon(&self) -> WINMON_R { + WINMON_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Overflow"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 3) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Result Ready"] + #[inline(always)] + pub fn resrdy(&mut self) -> RESRDY_W { + RESRDY_W { w: self } + } + #[doc = "Bit 1 - Overrun"] + #[inline(always)] + pub fn overrun(&mut self) -> OVERRUN_W { + OVERRUN_W { w: self } + } + #[doc = "Bit 2 - Window Monitor"] + #[inline(always)] + pub fn winmon(&mut self) -> WINMON_W { + WINMON_W { w: self } + } + #[doc = "Bit 3 - Overflow"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/tsens/offset.rs b/pac/atsamc21g/src/tsens/offset.rs new file mode 100644 index 000000000000..1796ac252c12 --- /dev/null +++ b/pac/atsamc21g/src/tsens/offset.rs @@ -0,0 +1,103 @@ +#[doc = "Register `OFFSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OFFSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OFFSETC` reader - Offset Correction"] +pub struct OFFSETC_R(crate::FieldReader); +impl OFFSETC_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + OFFSETC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OFFSETC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OFFSETC` writer - Offset Correction"] +pub struct OFFSETC_W<'a> { + w: &'a mut W, +} +impl<'a> OFFSETC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Offset Correction"] + #[inline(always)] + pub fn offsetc(&self) -> OFFSETC_R { + OFFSETC_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Offset Correction"] + #[inline(always)] + pub fn offsetc(&mut self) -> OFFSETC_W { + OFFSETC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Offset Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [offset](index.html) module"] +pub struct OFFSET_SPEC; +impl crate::RegisterSpec for OFFSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [offset::R](R) reader structure"] +impl crate::Readable for OFFSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [offset::W](W) writer structure"] +impl crate::Writable for OFFSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OFFSET to value 0"] +impl crate::Resettable for OFFSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/tsens/status.rs b/pac/atsamc21g/src/tsens/status.rs new file mode 100644 index 000000000000..42309f7dcb4c --- /dev/null +++ b/pac/atsamc21g/src/tsens/status.rs @@ -0,0 +1,53 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `OVF` reader - Result Overflow"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Result Overflow"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } +} +#[doc = "Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/tsens/syncbusy.rs b/pac/atsamc21g/src/tsens/syncbusy.rs new file mode 100644 index 000000000000..e4492e16ad3c --- /dev/null +++ b/pac/atsamc21g/src/tsens/syncbusy.rs @@ -0,0 +1,73 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - Enable Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +#[doc = "Synchronization Busy Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/tsens/value.rs b/pac/atsamc21g/src/tsens/value.rs new file mode 100644 index 000000000000..54232a992edf --- /dev/null +++ b/pac/atsamc21g/src/tsens/value.rs @@ -0,0 +1,53 @@ +#[doc = "Register `VALUE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `VALUE` reader - Measurement Value"] +pub struct VALUE_R(crate::FieldReader); +impl VALUE_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + VALUE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VALUE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:23 - Measurement Value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +#[doc = "Value Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [value](index.html) module"] +pub struct VALUE_SPEC; +impl crate::RegisterSpec for VALUE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [value::R](R) reader structure"] +impl crate::Readable for VALUE_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets VALUE to value 0"] +impl crate::Resettable for VALUE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/tsens/winlt.rs b/pac/atsamc21g/src/tsens/winlt.rs new file mode 100644 index 000000000000..85a1d01b4b34 --- /dev/null +++ b/pac/atsamc21g/src/tsens/winlt.rs @@ -0,0 +1,103 @@ +#[doc = "Register `WINLT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WINLT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WINLT` reader - Window Lower Threshold"] +pub struct WINLT_R(crate::FieldReader); +impl WINLT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + WINLT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINLT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINLT` writer - Window Lower Threshold"] +pub struct WINLT_W<'a> { + w: &'a mut W, +} +impl<'a> WINLT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Window Lower Threshold"] + #[inline(always)] + pub fn winlt(&self) -> WINLT_R { + WINLT_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Window Lower Threshold"] + #[inline(always)] + pub fn winlt(&mut self) -> WINLT_W { + WINLT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Window Monitor Lower Threshold Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [winlt](index.html) module"] +pub struct WINLT_SPEC; +impl crate::RegisterSpec for WINLT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [winlt::R](R) reader structure"] +impl crate::Readable for WINLT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [winlt::W](W) writer structure"] +impl crate::Writable for WINLT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WINLT to value 0"] +impl crate::Resettable for WINLT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/tsens/winut.rs b/pac/atsamc21g/src/tsens/winut.rs new file mode 100644 index 000000000000..7da0850f8e50 --- /dev/null +++ b/pac/atsamc21g/src/tsens/winut.rs @@ -0,0 +1,103 @@ +#[doc = "Register `WINUT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WINUT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WINUT` reader - Window Upper Threshold"] +pub struct WINUT_R(crate::FieldReader); +impl WINUT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + WINUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINUT` writer - Window Upper Threshold"] +pub struct WINUT_W<'a> { + w: &'a mut W, +} +impl<'a> WINUT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Window Upper Threshold"] + #[inline(always)] + pub fn winut(&self) -> WINUT_R { + WINUT_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Window Upper Threshold"] + #[inline(always)] + pub fn winut(&mut self) -> WINUT_W { + WINUT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Window Monitor Upper Threshold Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [winut](index.html) module"] +pub struct WINUT_SPEC; +impl crate::RegisterSpec for WINUT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [winut::R](R) reader structure"] +impl crate::Readable for WINUT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [winut::W](W) writer structure"] +impl crate::Writable for WINUT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WINUT to value 0"] +impl crate::Resettable for WINUT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/wdt.rs b/pac/atsamc21g/src/wdt.rs new file mode 100644 index 000000000000..22b5c2bb706f --- /dev/null +++ b/pac/atsamc21g/src/wdt.rs @@ -0,0 +1,54 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrla: crate::Reg, + #[doc = "0x01 - Configuration"] + pub config: crate::Reg, + #[doc = "0x02 - Early Warning Interrupt Control"] + pub ewctrl: crate::Reg, + _reserved3: [u8; 0x01], + #[doc = "0x04 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x05 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x06 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x08 - Synchronization Busy"] + pub syncbusy: crate::Reg, + #[doc = "0x0c - Clear"] + pub clear: crate::Reg, +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control"] +pub mod ctrla; +#[doc = "CONFIG register accessor: an alias for `Reg`"] +pub type CONFIG = crate::Reg; +#[doc = "Configuration"] +pub mod config; +#[doc = "EWCTRL register accessor: an alias for `Reg`"] +pub type EWCTRL = crate::Reg; +#[doc = "Early Warning Interrupt Control"] +pub mod ewctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Busy"] +pub mod syncbusy; +#[doc = "CLEAR register accessor: an alias for `Reg`"] +pub type CLEAR = crate::Reg; +#[doc = "Clear"] +pub mod clear; diff --git a/pac/atsamc21g/src/wdt/clear.rs b/pac/atsamc21g/src/wdt/clear.rs new file mode 100644 index 000000000000..61ee21f3246a --- /dev/null +++ b/pac/atsamc21g/src/wdt/clear.rs @@ -0,0 +1,85 @@ +#[doc = "Register `CLEAR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Watchdog Clear\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CLEAR_AW { + #[doc = "165: Clear Key"] + KEY = 165, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CLEAR_AW) -> Self { + variant as _ + } +} +#[doc = "Field `CLEAR` writer - Watchdog Clear"] +pub struct CLEAR_W<'a> { + w: &'a mut W, +} +impl<'a> CLEAR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CLEAR_AW) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Clear Key"] + #[inline(always)] + pub fn key(self) -> &'a mut W { + self.variant(CLEAR_AW::KEY) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl W { + #[doc = "Bits 0:7 - Watchdog Clear"] + #[inline(always)] + pub fn clear(&mut self) -> CLEAR_W { + CLEAR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Clear\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clear](index.html) module"] +pub struct CLEAR_SPEC; +impl crate::RegisterSpec for CLEAR_SPEC { + type Ux = u8; +} +#[doc = "`write(|w| ..)` method takes [clear::W](W) writer structure"] +impl crate::Writable for CLEAR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CLEAR to value 0"] +impl crate::Resettable for CLEAR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/wdt/config.rs b/pac/atsamc21g/src/wdt/config.rs new file mode 100644 index 000000000000..c90f062b01f0 --- /dev/null +++ b/pac/atsamc21g/src/wdt/config.rs @@ -0,0 +1,498 @@ +#[doc = "Register `CONFIG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CONFIG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Time-Out Period\n\nValue on reset: 11"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PER_A { + #[doc = "0: 8 clock cycles"] + CYC8 = 0, + #[doc = "1: 16 clock cycles"] + CYC16 = 1, + #[doc = "2: 32 clock cycles"] + CYC32 = 2, + #[doc = "3: 64 clock cycles"] + CYC64 = 3, + #[doc = "4: 128 clock cycles"] + CYC128 = 4, + #[doc = "5: 256 clock cycles"] + CYC256 = 5, + #[doc = "6: 512 clock cycles"] + CYC512 = 6, + #[doc = "7: 1024 clock cycles"] + CYC1024 = 7, + #[doc = "8: 2048 clock cycles"] + CYC2048 = 8, + #[doc = "9: 4096 clock cycles"] + CYC4096 = 9, + #[doc = "10: 8192 clock cycles"] + CYC8192 = 10, + #[doc = "11: 16384 clock cycles"] + CYC16384 = 11, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PER` reader - Time-Out Period"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PER_A::CYC8), + 1 => Some(PER_A::CYC16), + 2 => Some(PER_A::CYC32), + 3 => Some(PER_A::CYC64), + 4 => Some(PER_A::CYC128), + 5 => Some(PER_A::CYC256), + 6 => Some(PER_A::CYC512), + 7 => Some(PER_A::CYC1024), + 8 => Some(PER_A::CYC2048), + 9 => Some(PER_A::CYC4096), + 10 => Some(PER_A::CYC8192), + 11 => Some(PER_A::CYC16384), + _ => None, + } + } + #[doc = "Checks if the value of the field is `CYC8`"] + #[inline(always)] + pub fn is_cyc8(&self) -> bool { + **self == PER_A::CYC8 + } + #[doc = "Checks if the value of the field is `CYC16`"] + #[inline(always)] + pub fn is_cyc16(&self) -> bool { + **self == PER_A::CYC16 + } + #[doc = "Checks if the value of the field is `CYC32`"] + #[inline(always)] + pub fn is_cyc32(&self) -> bool { + **self == PER_A::CYC32 + } + #[doc = "Checks if the value of the field is `CYC64`"] + #[inline(always)] + pub fn is_cyc64(&self) -> bool { + **self == PER_A::CYC64 + } + #[doc = "Checks if the value of the field is `CYC128`"] + #[inline(always)] + pub fn is_cyc128(&self) -> bool { + **self == PER_A::CYC128 + } + #[doc = "Checks if the value of the field is `CYC256`"] + #[inline(always)] + pub fn is_cyc256(&self) -> bool { + **self == PER_A::CYC256 + } + #[doc = "Checks if the value of the field is `CYC512`"] + #[inline(always)] + pub fn is_cyc512(&self) -> bool { + **self == PER_A::CYC512 + } + #[doc = "Checks if the value of the field is `CYC1024`"] + #[inline(always)] + pub fn is_cyc1024(&self) -> bool { + **self == PER_A::CYC1024 + } + #[doc = "Checks if the value of the field is `CYC2048`"] + #[inline(always)] + pub fn is_cyc2048(&self) -> bool { + **self == PER_A::CYC2048 + } + #[doc = "Checks if the value of the field is `CYC4096`"] + #[inline(always)] + pub fn is_cyc4096(&self) -> bool { + **self == PER_A::CYC4096 + } + #[doc = "Checks if the value of the field is `CYC8192`"] + #[inline(always)] + pub fn is_cyc8192(&self) -> bool { + **self == PER_A::CYC8192 + } + #[doc = "Checks if the value of the field is `CYC16384`"] + #[inline(always)] + pub fn is_cyc16384(&self) -> bool { + **self == PER_A::CYC16384 + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` writer - Time-Out Period"] +pub struct PER_W<'a> { + w: &'a mut W, +} +impl<'a> PER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PER_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8 clock cycles"] + #[inline(always)] + pub fn cyc8(self) -> &'a mut W { + self.variant(PER_A::CYC8) + } + #[doc = "16 clock cycles"] + #[inline(always)] + pub fn cyc16(self) -> &'a mut W { + self.variant(PER_A::CYC16) + } + #[doc = "32 clock cycles"] + #[inline(always)] + pub fn cyc32(self) -> &'a mut W { + self.variant(PER_A::CYC32) + } + #[doc = "64 clock cycles"] + #[inline(always)] + pub fn cyc64(self) -> &'a mut W { + self.variant(PER_A::CYC64) + } + #[doc = "128 clock cycles"] + #[inline(always)] + pub fn cyc128(self) -> &'a mut W { + self.variant(PER_A::CYC128) + } + #[doc = "256 clock cycles"] + #[inline(always)] + pub fn cyc256(self) -> &'a mut W { + self.variant(PER_A::CYC256) + } + #[doc = "512 clock cycles"] + #[inline(always)] + pub fn cyc512(self) -> &'a mut W { + self.variant(PER_A::CYC512) + } + #[doc = "1024 clock cycles"] + #[inline(always)] + pub fn cyc1024(self) -> &'a mut W { + self.variant(PER_A::CYC1024) + } + #[doc = "2048 clock cycles"] + #[inline(always)] + pub fn cyc2048(self) -> &'a mut W { + self.variant(PER_A::CYC2048) + } + #[doc = "4096 clock cycles"] + #[inline(always)] + pub fn cyc4096(self) -> &'a mut W { + self.variant(PER_A::CYC4096) + } + #[doc = "8192 clock cycles"] + #[inline(always)] + pub fn cyc8192(self) -> &'a mut W { + self.variant(PER_A::CYC8192) + } + #[doc = "16384 clock cycles"] + #[inline(always)] + pub fn cyc16384(self) -> &'a mut W { + self.variant(PER_A::CYC16384) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +#[doc = "Window Mode Time-Out Period\n\nValue on reset: 11"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WINDOW_A { + #[doc = "0: 8 clock cycles"] + CYC8 = 0, + #[doc = "1: 16 clock cycles"] + CYC16 = 1, + #[doc = "2: 32 clock cycles"] + CYC32 = 2, + #[doc = "3: 64 clock cycles"] + CYC64 = 3, + #[doc = "4: 128 clock cycles"] + CYC128 = 4, + #[doc = "5: 256 clock cycles"] + CYC256 = 5, + #[doc = "6: 512 clock cycles"] + CYC512 = 6, + #[doc = "7: 1024 clock cycles"] + CYC1024 = 7, + #[doc = "8: 2048 clock cycles"] + CYC2048 = 8, + #[doc = "9: 4096 clock cycles"] + CYC4096 = 9, + #[doc = "10: 8192 clock cycles"] + CYC8192 = 10, + #[doc = "11: 16384 clock cycles"] + CYC16384 = 11, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WINDOW_A) -> Self { + variant as _ + } +} +#[doc = "Field `WINDOW` reader - Window Mode Time-Out Period"] +pub struct WINDOW_R(crate::FieldReader); +impl WINDOW_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WINDOW_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(WINDOW_A::CYC8), + 1 => Some(WINDOW_A::CYC16), + 2 => Some(WINDOW_A::CYC32), + 3 => Some(WINDOW_A::CYC64), + 4 => Some(WINDOW_A::CYC128), + 5 => Some(WINDOW_A::CYC256), + 6 => Some(WINDOW_A::CYC512), + 7 => Some(WINDOW_A::CYC1024), + 8 => Some(WINDOW_A::CYC2048), + 9 => Some(WINDOW_A::CYC4096), + 10 => Some(WINDOW_A::CYC8192), + 11 => Some(WINDOW_A::CYC16384), + _ => None, + } + } + #[doc = "Checks if the value of the field is `CYC8`"] + #[inline(always)] + pub fn is_cyc8(&self) -> bool { + **self == WINDOW_A::CYC8 + } + #[doc = "Checks if the value of the field is `CYC16`"] + #[inline(always)] + pub fn is_cyc16(&self) -> bool { + **self == WINDOW_A::CYC16 + } + #[doc = "Checks if the value of the field is `CYC32`"] + #[inline(always)] + pub fn is_cyc32(&self) -> bool { + **self == WINDOW_A::CYC32 + } + #[doc = "Checks if the value of the field is `CYC64`"] + #[inline(always)] + pub fn is_cyc64(&self) -> bool { + **self == WINDOW_A::CYC64 + } + #[doc = "Checks if the value of the field is `CYC128`"] + #[inline(always)] + pub fn is_cyc128(&self) -> bool { + **self == WINDOW_A::CYC128 + } + #[doc = "Checks if the value of the field is `CYC256`"] + #[inline(always)] + pub fn is_cyc256(&self) -> bool { + **self == WINDOW_A::CYC256 + } + #[doc = "Checks if the value of the field is `CYC512`"] + #[inline(always)] + pub fn is_cyc512(&self) -> bool { + **self == WINDOW_A::CYC512 + } + #[doc = "Checks if the value of the field is `CYC1024`"] + #[inline(always)] + pub fn is_cyc1024(&self) -> bool { + **self == WINDOW_A::CYC1024 + } + #[doc = "Checks if the value of the field is `CYC2048`"] + #[inline(always)] + pub fn is_cyc2048(&self) -> bool { + **self == WINDOW_A::CYC2048 + } + #[doc = "Checks if the value of the field is `CYC4096`"] + #[inline(always)] + pub fn is_cyc4096(&self) -> bool { + **self == WINDOW_A::CYC4096 + } + #[doc = "Checks if the value of the field is `CYC8192`"] + #[inline(always)] + pub fn is_cyc8192(&self) -> bool { + **self == WINDOW_A::CYC8192 + } + #[doc = "Checks if the value of the field is `CYC16384`"] + #[inline(always)] + pub fn is_cyc16384(&self) -> bool { + **self == WINDOW_A::CYC16384 + } +} +impl core::ops::Deref for WINDOW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINDOW` writer - Window Mode Time-Out Period"] +pub struct WINDOW_W<'a> { + w: &'a mut W, +} +impl<'a> WINDOW_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WINDOW_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8 clock cycles"] + #[inline(always)] + pub fn cyc8(self) -> &'a mut W { + self.variant(WINDOW_A::CYC8) + } + #[doc = "16 clock cycles"] + #[inline(always)] + pub fn cyc16(self) -> &'a mut W { + self.variant(WINDOW_A::CYC16) + } + #[doc = "32 clock cycles"] + #[inline(always)] + pub fn cyc32(self) -> &'a mut W { + self.variant(WINDOW_A::CYC32) + } + #[doc = "64 clock cycles"] + #[inline(always)] + pub fn cyc64(self) -> &'a mut W { + self.variant(WINDOW_A::CYC64) + } + #[doc = "128 clock cycles"] + #[inline(always)] + pub fn cyc128(self) -> &'a mut W { + self.variant(WINDOW_A::CYC128) + } + #[doc = "256 clock cycles"] + #[inline(always)] + pub fn cyc256(self) -> &'a mut W { + self.variant(WINDOW_A::CYC256) + } + #[doc = "512 clock cycles"] + #[inline(always)] + pub fn cyc512(self) -> &'a mut W { + self.variant(WINDOW_A::CYC512) + } + #[doc = "1024 clock cycles"] + #[inline(always)] + pub fn cyc1024(self) -> &'a mut W { + self.variant(WINDOW_A::CYC1024) + } + #[doc = "2048 clock cycles"] + #[inline(always)] + pub fn cyc2048(self) -> &'a mut W { + self.variant(WINDOW_A::CYC2048) + } + #[doc = "4096 clock cycles"] + #[inline(always)] + pub fn cyc4096(self) -> &'a mut W { + self.variant(WINDOW_A::CYC4096) + } + #[doc = "8192 clock cycles"] + #[inline(always)] + pub fn cyc8192(self) -> &'a mut W { + self.variant(WINDOW_A::CYC8192) + } + #[doc = "16384 clock cycles"] + #[inline(always)] + pub fn cyc16384(self) -> &'a mut W { + self.variant(WINDOW_A::CYC16384) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 4)) | ((value as u8 & 0x0f) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Time-Out Period"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Window Mode Time-Out Period"] + #[inline(always)] + pub fn window(&self) -> WINDOW_R { + WINDOW_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Time-Out Period"] + #[inline(always)] + pub fn per(&mut self) -> PER_W { + PER_W { w: self } + } + #[doc = "Bits 4:7 - Window Mode Time-Out Period"] + #[inline(always)] + pub fn window(&mut self) -> WINDOW_W { + WINDOW_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [config](index.html) module"] +pub struct CONFIG_SPEC; +impl crate::RegisterSpec for CONFIG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [config::R](R) reader structure"] +impl crate::Readable for CONFIG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [config::W](W) writer structure"] +impl crate::Writable for CONFIG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CONFIG to value 0xbb"] +impl crate::Resettable for CONFIG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xbb + } +} diff --git a/pac/atsamc21g/src/wdt/ctrla.rs b/pac/atsamc21g/src/wdt/ctrla.rs new file mode 100644 index 000000000000..895169d36aeb --- /dev/null +++ b/pac/atsamc21g/src/wdt/ctrla.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WEN` reader - Watchdog Timer Window Mode Enable"] +pub struct WEN_R(crate::FieldReader); +impl WEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WEN` writer - Watchdog Timer Window Mode Enable"] +pub struct WEN_W<'a> { + w: &'a mut W, +} +impl<'a> WEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `ALWAYSON` reader - Always-On"] +pub struct ALWAYSON_R(crate::FieldReader); +impl ALWAYSON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALWAYSON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALWAYSON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALWAYSON` writer - Always-On"] +pub struct ALWAYSON_W<'a> { + w: &'a mut W, +} +impl<'a> ALWAYSON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Watchdog Timer Window Mode Enable"] + #[inline(always)] + pub fn wen(&self) -> WEN_R { + WEN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 7 - Always-On"] + #[inline(always)] + pub fn alwayson(&self) -> ALWAYSON_R { + ALWAYSON_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - Watchdog Timer Window Mode Enable"] + #[inline(always)] + pub fn wen(&mut self) -> WEN_W { + WEN_W { w: self } + } + #[doc = "Bit 7 - Always-On"] + #[inline(always)] + pub fn alwayson(&mut self) -> ALWAYSON_W { + ALWAYSON_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/wdt/ewctrl.rs b/pac/atsamc21g/src/wdt/ewctrl.rs new file mode 100644 index 000000000000..94542e9897a9 --- /dev/null +++ b/pac/atsamc21g/src/wdt/ewctrl.rs @@ -0,0 +1,282 @@ +#[doc = "Register `EWCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EWCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Early Warning Interrupt Time Offset\n\nValue on reset: 11"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EWOFFSET_A { + #[doc = "0: 8 clock cycles"] + CYC8 = 0, + #[doc = "1: 16 clock cycles"] + CYC16 = 1, + #[doc = "2: 32 clock cycles"] + CYC32 = 2, + #[doc = "3: 64 clock cycles"] + CYC64 = 3, + #[doc = "4: 128 clock cycles"] + CYC128 = 4, + #[doc = "5: 256 clock cycles"] + CYC256 = 5, + #[doc = "6: 512 clock cycles"] + CYC512 = 6, + #[doc = "7: 1024 clock cycles"] + CYC1024 = 7, + #[doc = "8: 2048 clock cycles"] + CYC2048 = 8, + #[doc = "9: 4096 clock cycles"] + CYC4096 = 9, + #[doc = "10: 8192 clock cycles"] + CYC8192 = 10, + #[doc = "11: 16384 clock cycles"] + CYC16384 = 11, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EWOFFSET_A) -> Self { + variant as _ + } +} +#[doc = "Field `EWOFFSET` reader - Early Warning Interrupt Time Offset"] +pub struct EWOFFSET_R(crate::FieldReader); +impl EWOFFSET_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EWOFFSET_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(EWOFFSET_A::CYC8), + 1 => Some(EWOFFSET_A::CYC16), + 2 => Some(EWOFFSET_A::CYC32), + 3 => Some(EWOFFSET_A::CYC64), + 4 => Some(EWOFFSET_A::CYC128), + 5 => Some(EWOFFSET_A::CYC256), + 6 => Some(EWOFFSET_A::CYC512), + 7 => Some(EWOFFSET_A::CYC1024), + 8 => Some(EWOFFSET_A::CYC2048), + 9 => Some(EWOFFSET_A::CYC4096), + 10 => Some(EWOFFSET_A::CYC8192), + 11 => Some(EWOFFSET_A::CYC16384), + _ => None, + } + } + #[doc = "Checks if the value of the field is `CYC8`"] + #[inline(always)] + pub fn is_cyc8(&self) -> bool { + **self == EWOFFSET_A::CYC8 + } + #[doc = "Checks if the value of the field is `CYC16`"] + #[inline(always)] + pub fn is_cyc16(&self) -> bool { + **self == EWOFFSET_A::CYC16 + } + #[doc = "Checks if the value of the field is `CYC32`"] + #[inline(always)] + pub fn is_cyc32(&self) -> bool { + **self == EWOFFSET_A::CYC32 + } + #[doc = "Checks if the value of the field is `CYC64`"] + #[inline(always)] + pub fn is_cyc64(&self) -> bool { + **self == EWOFFSET_A::CYC64 + } + #[doc = "Checks if the value of the field is `CYC128`"] + #[inline(always)] + pub fn is_cyc128(&self) -> bool { + **self == EWOFFSET_A::CYC128 + } + #[doc = "Checks if the value of the field is `CYC256`"] + #[inline(always)] + pub fn is_cyc256(&self) -> bool { + **self == EWOFFSET_A::CYC256 + } + #[doc = "Checks if the value of the field is `CYC512`"] + #[inline(always)] + pub fn is_cyc512(&self) -> bool { + **self == EWOFFSET_A::CYC512 + } + #[doc = "Checks if the value of the field is `CYC1024`"] + #[inline(always)] + pub fn is_cyc1024(&self) -> bool { + **self == EWOFFSET_A::CYC1024 + } + #[doc = "Checks if the value of the field is `CYC2048`"] + #[inline(always)] + pub fn is_cyc2048(&self) -> bool { + **self == EWOFFSET_A::CYC2048 + } + #[doc = "Checks if the value of the field is `CYC4096`"] + #[inline(always)] + pub fn is_cyc4096(&self) -> bool { + **self == EWOFFSET_A::CYC4096 + } + #[doc = "Checks if the value of the field is `CYC8192`"] + #[inline(always)] + pub fn is_cyc8192(&self) -> bool { + **self == EWOFFSET_A::CYC8192 + } + #[doc = "Checks if the value of the field is `CYC16384`"] + #[inline(always)] + pub fn is_cyc16384(&self) -> bool { + **self == EWOFFSET_A::CYC16384 + } +} +impl core::ops::Deref for EWOFFSET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EWOFFSET` writer - Early Warning Interrupt Time Offset"] +pub struct EWOFFSET_W<'a> { + w: &'a mut W, +} +impl<'a> EWOFFSET_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EWOFFSET_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8 clock cycles"] + #[inline(always)] + pub fn cyc8(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC8) + } + #[doc = "16 clock cycles"] + #[inline(always)] + pub fn cyc16(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC16) + } + #[doc = "32 clock cycles"] + #[inline(always)] + pub fn cyc32(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC32) + } + #[doc = "64 clock cycles"] + #[inline(always)] + pub fn cyc64(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC64) + } + #[doc = "128 clock cycles"] + #[inline(always)] + pub fn cyc128(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC128) + } + #[doc = "256 clock cycles"] + #[inline(always)] + pub fn cyc256(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC256) + } + #[doc = "512 clock cycles"] + #[inline(always)] + pub fn cyc512(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC512) + } + #[doc = "1024 clock cycles"] + #[inline(always)] + pub fn cyc1024(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC1024) + } + #[doc = "2048 clock cycles"] + #[inline(always)] + pub fn cyc2048(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC2048) + } + #[doc = "4096 clock cycles"] + #[inline(always)] + pub fn cyc4096(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC4096) + } + #[doc = "8192 clock cycles"] + #[inline(always)] + pub fn cyc8192(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC8192) + } + #[doc = "16384 clock cycles"] + #[inline(always)] + pub fn cyc16384(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC16384) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Early Warning Interrupt Time Offset"] + #[inline(always)] + pub fn ewoffset(&self) -> EWOFFSET_R { + EWOFFSET_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Early Warning Interrupt Time Offset"] + #[inline(always)] + pub fn ewoffset(&mut self) -> EWOFFSET_W { + EWOFFSET_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Early Warning Interrupt Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ewctrl](index.html) module"] +pub struct EWCTRL_SPEC; +impl crate::RegisterSpec for EWCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ewctrl::R](R) reader structure"] +impl crate::Readable for EWCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ewctrl::W](W) writer structure"] +impl crate::Writable for EWCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EWCTRL to value 0x0b"] +impl crate::Resettable for EWCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0b + } +} diff --git a/pac/atsamc21g/src/wdt/intenclr.rs b/pac/atsamc21g/src/wdt/intenclr.rs new file mode 100644 index 000000000000..ed4021f96cce --- /dev/null +++ b/pac/atsamc21g/src/wdt/intenclr.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EW` reader - Early Warning Interrupt Enable"] +pub struct EW_R(crate::FieldReader); +impl EW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EW` writer - Early Warning Interrupt Enable"] +pub struct EW_W<'a> { + w: &'a mut W, +} +impl<'a> EW_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Early Warning Interrupt Enable"] + #[inline(always)] + pub fn ew(&self) -> EW_R { + EW_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Early Warning Interrupt Enable"] + #[inline(always)] + pub fn ew(&mut self) -> EW_W { + EW_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/wdt/intenset.rs b/pac/atsamc21g/src/wdt/intenset.rs new file mode 100644 index 000000000000..5a0928ff0532 --- /dev/null +++ b/pac/atsamc21g/src/wdt/intenset.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EW` reader - Early Warning Interrupt Enable"] +pub struct EW_R(crate::FieldReader); +impl EW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EW` writer - Early Warning Interrupt Enable"] +pub struct EW_W<'a> { + w: &'a mut W, +} +impl<'a> EW_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Early Warning Interrupt Enable"] + #[inline(always)] + pub fn ew(&self) -> EW_R { + EW_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Early Warning Interrupt Enable"] + #[inline(always)] + pub fn ew(&mut self) -> EW_W { + EW_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/wdt/intflag.rs b/pac/atsamc21g/src/wdt/intflag.rs new file mode 100644 index 000000000000..f2c9b858a199 --- /dev/null +++ b/pac/atsamc21g/src/wdt/intflag.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EW` reader - Early Warning"] +pub struct EW_R(crate::FieldReader); +impl EW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EW` writer - Early Warning"] +pub struct EW_W<'a> { + w: &'a mut W, +} +impl<'a> EW_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Early Warning"] + #[inline(always)] + pub fn ew(&self) -> EW_R { + EW_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Early Warning"] + #[inline(always)] + pub fn ew(&mut self) -> EW_W { + EW_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21g/src/wdt/syncbusy.rs b/pac/atsamc21g/src/wdt/syncbusy.rs new file mode 100644 index 000000000000..a3ecf7fbdb8a --- /dev/null +++ b/pac/atsamc21g/src/wdt/syncbusy.rs @@ -0,0 +1,113 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `ENABLE` reader - Enable Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WEN` reader - Window Enable Busy"] +pub struct WEN_R(crate::FieldReader); +impl WEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALWAYSON` reader - Always-On Busy"] +pub struct ALWAYSON_R(crate::FieldReader); +impl ALWAYSON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALWAYSON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALWAYSON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLEAR` reader - Clear Busy"] +pub struct CLEAR_R(crate::FieldReader); +impl CLEAR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLEAR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLEAR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 1 - Enable Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Window Enable Busy"] + #[inline(always)] + pub fn wen(&self) -> WEN_R { + WEN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Always-On Busy"] + #[inline(always)] + pub fn alwayson(&self) -> ALWAYSON_R { + ALWAYSON_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Clear Busy"] + #[inline(always)] + pub fn clear(&self) -> CLEAR_R { + CLEAR_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +#[doc = "Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/CHANGELOG.md b/pac/atsamc21j/CHANGELOG.md new file mode 100644 index 000000000000..e28d85f63b31 --- /dev/null +++ b/pac/atsamc21j/CHANGELOG.md @@ -0,0 +1,6 @@ +# Unreleased + +- Initial version +--- + +Changelog tracking started at v0.0.1 diff --git a/pac/atsamc21j/Cargo.toml b/pac/atsamc21j/Cargo.toml new file mode 100644 index 000000000000..e3e40e417244 --- /dev/null +++ b/pac/atsamc21j/Cargo.toml @@ -0,0 +1,22 @@ +[package] +name = "atsamc21j" +description = "Peripheral access API for ATSAMC21J microcontrollers (generated using svd2rust)" +version = "0.0.1" +authors = ["Jeremy Boynes "] +keywords = ["no-std", "arm", "cortex-m"] +categories = ["embedded", "hardware-support", "no-std"] +license = "MIT OR Apache-2.0" +repository = "https://github.com/atsamd-rs/atsamd" +readme = "README.md" +edition = "2021" + +[dependencies] +cortex-m = "0.7" +vcell = "0.1" + +[dependencies.cortex-m-rt] +version = "0.7" +optional = true + +[features] +rt = ["cortex-m-rt/device"] diff --git a/pac/atsamc21j/README.md b/pac/atsamc21j/README.md new file mode 100644 index 000000000000..e4ca1c38895f --- /dev/null +++ b/pac/atsamc21j/README.md @@ -0,0 +1,26 @@ +# ATSAMC21 + +A peripheral access crate for the ATSAMC21J chip from Microchip (née Atmel) for Rust Embedded projects. + +[![Build Status](https://travis-ci.org/atsamd-rs/atsamd.svg?branch=master)](https://travis-ci.org/atsamd-rs/atsamd) +[![Crates.io](https://img.shields.io/crates/v/atsamc21j.svg)](https://crates.io/crates/atsamc21j) + +## [Documentation](https://docs.rs/atsamc21j) + +This source was automatically generated using `svd2rust`, split into smaller pieces using `form` and formatted via `rustfmt`. + +## License + +Licensed under either of: + +- Apache License, Version 2.0 ([LICENSE-APACHE](https://github.com/atsamd-rs/atsamd/blob/master/LICENSE-APACHE) or + http://www.apache.org/licenses/LICENSE-2.0) +- MIT license ([LICENSE-MIT](https://github.com/atsamd-rs/atsamd/blob/master/LICENSE-MIT) or http://opensource.org/licenses/MIT) + +at your option. + +### Contribution + +Unless you explicitly state otherwise, any contribution intentionally submitted +for inclusion in the work by you, as defined in the Apache-2.0 license, shall +be dual licensed as above, without any additional terms or conditions. diff --git a/pac/atsamc21j/build.rs b/pac/atsamc21j/build.rs new file mode 100644 index 000000000000..597923f50892 --- /dev/null +++ b/pac/atsamc21j/build.rs @@ -0,0 +1,16 @@ +use std::env; +use std::fs::File; +use std::io::Write; +use std::path::PathBuf; +fn main() { + if env::var_os("CARGO_FEATURE_RT").is_some() { + let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap()); + File::create(out.join("device.x")) + .unwrap() + .write_all(include_bytes!("device.x")) + .unwrap(); + println!("cargo:rustc-link-search={}", out.display()); + println!("cargo:rerun-if-changed=device.x"); + } + println!("cargo:rerun-if-changed=build.rs"); +} diff --git a/pac/atsamc21j/device.x b/pac/atsamc21j/device.x new file mode 100644 index 000000000000..54baa7b6516c --- /dev/null +++ b/pac/atsamc21j/device.x @@ -0,0 +1,31 @@ +PROVIDE(WDT = DefaultHandler); +PROVIDE(RTC = DefaultHandler); +PROVIDE(EIC = DefaultHandler); +PROVIDE(FREQM = DefaultHandler); +PROVIDE(TSENS = DefaultHandler); +PROVIDE(NVMCTRL = DefaultHandler); +PROVIDE(DMAC = DefaultHandler); +PROVIDE(EVSYS = DefaultHandler); +PROVIDE(SERCOM0 = DefaultHandler); +PROVIDE(SERCOM1 = DefaultHandler); +PROVIDE(SERCOM2 = DefaultHandler); +PROVIDE(SERCOM3 = DefaultHandler); +PROVIDE(SERCOM4 = DefaultHandler); +PROVIDE(SERCOM5 = DefaultHandler); +PROVIDE(CAN0 = DefaultHandler); +PROVIDE(CAN1 = DefaultHandler); +PROVIDE(TCC0 = DefaultHandler); +PROVIDE(TCC1 = DefaultHandler); +PROVIDE(TCC2 = DefaultHandler); +PROVIDE(TC0 = DefaultHandler); +PROVIDE(TC1 = DefaultHandler); +PROVIDE(TC2 = DefaultHandler); +PROVIDE(TC3 = DefaultHandler); +PROVIDE(TC4 = DefaultHandler); +PROVIDE(ADC0 = DefaultHandler); +PROVIDE(ADC1 = DefaultHandler); +PROVIDE(AC = DefaultHandler); +PROVIDE(DAC = DefaultHandler); +PROVIDE(SDADC = DefaultHandler); +PROVIDE(PTC = DefaultHandler); + diff --git a/pac/atsamc21j/src/ac.rs b/pac/atsamc21j/src/ac.rs new file mode 100644 index 000000000000..b66620475572 --- /dev/null +++ b/pac/atsamc21j/src/ac.rs @@ -0,0 +1,83 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + #[doc = "0x01 - Control B"] + pub ctrlb: crate::Reg, + #[doc = "0x02 - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x04 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x05 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x06 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x07 - Status A"] + pub statusa: crate::Reg, + #[doc = "0x08 - Status B"] + pub statusb: crate::Reg, + #[doc = "0x09 - Debug Control"] + pub dbgctrl: crate::Reg, + #[doc = "0x0a - Window Control"] + pub winctrl: crate::Reg, + _reserved10: [u8; 0x01], + #[doc = "0x0c - Scaler n"] + pub scaler: [crate::Reg; 4], + #[doc = "0x10..0x20 - Comparator Control n"] + pub compctrl: [crate::Reg; 4], + #[doc = "0x20 - Synchronization Busy"] + pub syncbusy: crate::Reg, +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "Control B"] +pub mod ctrlb; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUSA register accessor: an alias for `Reg`"] +pub type STATUSA = crate::Reg; +#[doc = "Status A"] +pub mod statusa; +#[doc = "STATUSB register accessor: an alias for `Reg`"] +pub type STATUSB = crate::Reg; +#[doc = "Status B"] +pub mod statusb; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "WINCTRL register accessor: an alias for `Reg`"] +pub type WINCTRL = crate::Reg; +#[doc = "Window Control"] +pub mod winctrl; +#[doc = "SCALER register accessor: an alias for `Reg`"] +pub type SCALER = crate::Reg; +#[doc = "Scaler n"] +pub mod scaler; +#[doc = "COMPCTRL register accessor: an alias for `Reg`"] +pub type COMPCTRL = crate::Reg; +#[doc = "Comparator Control n"] +pub mod compctrl; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Busy"] +pub mod syncbusy; diff --git a/pac/atsamc21j/src/ac/compctrl.rs b/pac/atsamc21j/src/ac/compctrl.rs new file mode 100644 index 000000000000..791525fd7407 --- /dev/null +++ b/pac/atsamc21j/src/ac/compctrl.rs @@ -0,0 +1,987 @@ +#[doc = "Register `COMPCTRL[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COMPCTRL[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SINGLE` reader - Single-Shot Mode"] +pub struct SINGLE_R(crate::FieldReader); +impl SINGLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SINGLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SINGLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SINGLE` writer - Single-Shot Mode"] +pub struct SINGLE_W<'a> { + w: &'a mut W, +} +impl<'a> SINGLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Interrupt Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum INTSEL_A { + #[doc = "0: Interrupt on comparator output toggle"] + TOGGLE = 0, + #[doc = "1: Interrupt on comparator output rising"] + RISING = 1, + #[doc = "2: Interrupt on comparator output falling"] + FALLING = 2, + #[doc = "3: Interrupt on end of comparison (single-shot mode only)"] + EOC = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: INTSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `INTSEL` reader - Interrupt Selection"] +pub struct INTSEL_R(crate::FieldReader); +impl INTSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + INTSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INTSEL_A { + match self.bits { + 0 => INTSEL_A::TOGGLE, + 1 => INTSEL_A::RISING, + 2 => INTSEL_A::FALLING, + 3 => INTSEL_A::EOC, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `TOGGLE`"] + #[inline(always)] + pub fn is_toggle(&self) -> bool { + **self == INTSEL_A::TOGGLE + } + #[doc = "Checks if the value of the field is `RISING`"] + #[inline(always)] + pub fn is_rising(&self) -> bool { + **self == INTSEL_A::RISING + } + #[doc = "Checks if the value of the field is `FALLING`"] + #[inline(always)] + pub fn is_falling(&self) -> bool { + **self == INTSEL_A::FALLING + } + #[doc = "Checks if the value of the field is `EOC`"] + #[inline(always)] + pub fn is_eoc(&self) -> bool { + **self == INTSEL_A::EOC + } +} +impl core::ops::Deref for INTSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INTSEL` writer - Interrupt Selection"] +pub struct INTSEL_W<'a> { + w: &'a mut W, +} +impl<'a> INTSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: INTSEL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Interrupt on comparator output toggle"] + #[inline(always)] + pub fn toggle(self) -> &'a mut W { + self.variant(INTSEL_A::TOGGLE) + } + #[doc = "Interrupt on comparator output rising"] + #[inline(always)] + pub fn rising(self) -> &'a mut W { + self.variant(INTSEL_A::RISING) + } + #[doc = "Interrupt on comparator output falling"] + #[inline(always)] + pub fn falling(self) -> &'a mut W { + self.variant(INTSEL_A::FALLING) + } + #[doc = "Interrupt on end of comparison (single-shot mode only)"] + #[inline(always)] + pub fn eoc(self) -> &'a mut W { + self.variant(INTSEL_A::EOC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 3)) | ((value as u32 & 0x03) << 3); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Negative Input Mux Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MUXNEG_A { + #[doc = "0: I/O pin 0"] + PIN0 = 0, + #[doc = "1: I/O pin 1"] + PIN1 = 1, + #[doc = "2: I/O pin 2"] + PIN2 = 2, + #[doc = "3: I/O pin 3"] + PIN3 = 3, + #[doc = "4: Ground"] + GND = 4, + #[doc = "5: VDD scaler"] + VSCALE = 5, + #[doc = "6: Internal bandgap voltage"] + BANDGAP = 6, + #[doc = "7: DAC output"] + DAC = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MUXNEG_A) -> Self { + variant as _ + } +} +#[doc = "Field `MUXNEG` reader - Negative Input Mux Selection"] +pub struct MUXNEG_R(crate::FieldReader); +impl MUXNEG_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MUXNEG_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> MUXNEG_A { + match self.bits { + 0 => MUXNEG_A::PIN0, + 1 => MUXNEG_A::PIN1, + 2 => MUXNEG_A::PIN2, + 3 => MUXNEG_A::PIN3, + 4 => MUXNEG_A::GND, + 5 => MUXNEG_A::VSCALE, + 6 => MUXNEG_A::BANDGAP, + 7 => MUXNEG_A::DAC, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `PIN0`"] + #[inline(always)] + pub fn is_pin0(&self) -> bool { + **self == MUXNEG_A::PIN0 + } + #[doc = "Checks if the value of the field is `PIN1`"] + #[inline(always)] + pub fn is_pin1(&self) -> bool { + **self == MUXNEG_A::PIN1 + } + #[doc = "Checks if the value of the field is `PIN2`"] + #[inline(always)] + pub fn is_pin2(&self) -> bool { + **self == MUXNEG_A::PIN2 + } + #[doc = "Checks if the value of the field is `PIN3`"] + #[inline(always)] + pub fn is_pin3(&self) -> bool { + **self == MUXNEG_A::PIN3 + } + #[doc = "Checks if the value of the field is `GND`"] + #[inline(always)] + pub fn is_gnd(&self) -> bool { + **self == MUXNEG_A::GND + } + #[doc = "Checks if the value of the field is `VSCALE`"] + #[inline(always)] + pub fn is_vscale(&self) -> bool { + **self == MUXNEG_A::VSCALE + } + #[doc = "Checks if the value of the field is `BANDGAP`"] + #[inline(always)] + pub fn is_bandgap(&self) -> bool { + **self == MUXNEG_A::BANDGAP + } + #[doc = "Checks if the value of the field is `DAC`"] + #[inline(always)] + pub fn is_dac(&self) -> bool { + **self == MUXNEG_A::DAC + } +} +impl core::ops::Deref for MUXNEG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MUXNEG` writer - Negative Input Mux Selection"] +pub struct MUXNEG_W<'a> { + w: &'a mut W, +} +impl<'a> MUXNEG_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MUXNEG_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "I/O pin 0"] + #[inline(always)] + pub fn pin0(self) -> &'a mut W { + self.variant(MUXNEG_A::PIN0) + } + #[doc = "I/O pin 1"] + #[inline(always)] + pub fn pin1(self) -> &'a mut W { + self.variant(MUXNEG_A::PIN1) + } + #[doc = "I/O pin 2"] + #[inline(always)] + pub fn pin2(self) -> &'a mut W { + self.variant(MUXNEG_A::PIN2) + } + #[doc = "I/O pin 3"] + #[inline(always)] + pub fn pin3(self) -> &'a mut W { + self.variant(MUXNEG_A::PIN3) + } + #[doc = "Ground"] + #[inline(always)] + pub fn gnd(self) -> &'a mut W { + self.variant(MUXNEG_A::GND) + } + #[doc = "VDD scaler"] + #[inline(always)] + pub fn vscale(self) -> &'a mut W { + self.variant(MUXNEG_A::VSCALE) + } + #[doc = "Internal bandgap voltage"] + #[inline(always)] + pub fn bandgap(self) -> &'a mut W { + self.variant(MUXNEG_A::BANDGAP) + } + #[doc = "DAC output"] + #[inline(always)] + pub fn dac(self) -> &'a mut W { + self.variant(MUXNEG_A::DAC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +#[doc = "Positive Input Mux Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MUXPOS_A { + #[doc = "0: I/O pin 0"] + PIN0 = 0, + #[doc = "1: I/O pin 1"] + PIN1 = 1, + #[doc = "2: I/O pin 2"] + PIN2 = 2, + #[doc = "3: I/O pin 3"] + PIN3 = 3, + #[doc = "4: VDD Scaler"] + VSCALE = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MUXPOS_A) -> Self { + variant as _ + } +} +#[doc = "Field `MUXPOS` reader - Positive Input Mux Selection"] +pub struct MUXPOS_R(crate::FieldReader); +impl MUXPOS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MUXPOS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MUXPOS_A::PIN0), + 1 => Some(MUXPOS_A::PIN1), + 2 => Some(MUXPOS_A::PIN2), + 3 => Some(MUXPOS_A::PIN3), + 4 => Some(MUXPOS_A::VSCALE), + _ => None, + } + } + #[doc = "Checks if the value of the field is `PIN0`"] + #[inline(always)] + pub fn is_pin0(&self) -> bool { + **self == MUXPOS_A::PIN0 + } + #[doc = "Checks if the value of the field is `PIN1`"] + #[inline(always)] + pub fn is_pin1(&self) -> bool { + **self == MUXPOS_A::PIN1 + } + #[doc = "Checks if the value of the field is `PIN2`"] + #[inline(always)] + pub fn is_pin2(&self) -> bool { + **self == MUXPOS_A::PIN2 + } + #[doc = "Checks if the value of the field is `PIN3`"] + #[inline(always)] + pub fn is_pin3(&self) -> bool { + **self == MUXPOS_A::PIN3 + } + #[doc = "Checks if the value of the field is `VSCALE`"] + #[inline(always)] + pub fn is_vscale(&self) -> bool { + **self == MUXPOS_A::VSCALE + } +} +impl core::ops::Deref for MUXPOS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MUXPOS` writer - Positive Input Mux Selection"] +pub struct MUXPOS_W<'a> { + w: &'a mut W, +} +impl<'a> MUXPOS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MUXPOS_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "I/O pin 0"] + #[inline(always)] + pub fn pin0(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN0) + } + #[doc = "I/O pin 1"] + #[inline(always)] + pub fn pin1(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN1) + } + #[doc = "I/O pin 2"] + #[inline(always)] + pub fn pin2(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN2) + } + #[doc = "I/O pin 3"] + #[inline(always)] + pub fn pin3(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN3) + } + #[doc = "VDD Scaler"] + #[inline(always)] + pub fn vscale(self) -> &'a mut W { + self.variant(MUXPOS_A::VSCALE) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 12)) | ((value as u32 & 0x07) << 12); + self.w + } +} +#[doc = "Field `SWAP` reader - Swap Inputs and Invert"] +pub struct SWAP_R(crate::FieldReader); +impl SWAP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWAP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWAP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWAP` writer - Swap Inputs and Invert"] +pub struct SWAP_W<'a> { + w: &'a mut W, +} +impl<'a> SWAP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Speed Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SPEED_A { + #[doc = "0: Low speed"] + LOW = 0, + #[doc = "3: High speed"] + HIGH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SPEED_A) -> Self { + variant as _ + } +} +#[doc = "Field `SPEED` reader - Speed Selection"] +pub struct SPEED_R(crate::FieldReader); +impl SPEED_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SPEED_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SPEED_A::LOW), + 3 => Some(SPEED_A::HIGH), + _ => None, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SPEED_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SPEED_A::HIGH + } +} +impl core::ops::Deref for SPEED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SPEED` writer - Speed Selection"] +pub struct SPEED_W<'a> { + w: &'a mut W, +} +impl<'a> SPEED_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SPEED_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Low speed"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SPEED_A::LOW) + } + #[doc = "High speed"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SPEED_A::HIGH) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Field `HYSTEN` reader - Hysteresis Enable"] +pub struct HYSTEN_R(crate::FieldReader); +impl HYSTEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HYSTEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HYSTEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HYSTEN` writer - Hysteresis Enable"] +pub struct HYSTEN_W<'a> { + w: &'a mut W, +} +impl<'a> HYSTEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Filter Length\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FLEN_A { + #[doc = "0: No filtering"] + OFF = 0, + #[doc = "1: 3-bit majority function (2 of 3)"] + MAJ3 = 1, + #[doc = "2: 5-bit majority function (3 of 5)"] + MAJ5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FLEN_A) -> Self { + variant as _ + } +} +#[doc = "Field `FLEN` reader - Filter Length"] +pub struct FLEN_R(crate::FieldReader); +impl FLEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FLEN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(FLEN_A::OFF), + 1 => Some(FLEN_A::MAJ3), + 2 => Some(FLEN_A::MAJ5), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == FLEN_A::OFF + } + #[doc = "Checks if the value of the field is `MAJ3`"] + #[inline(always)] + pub fn is_maj3(&self) -> bool { + **self == FLEN_A::MAJ3 + } + #[doc = "Checks if the value of the field is `MAJ5`"] + #[inline(always)] + pub fn is_maj5(&self) -> bool { + **self == FLEN_A::MAJ5 + } +} +impl core::ops::Deref for FLEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLEN` writer - Filter Length"] +pub struct FLEN_W<'a> { + w: &'a mut W, +} +impl<'a> FLEN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FLEN_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No filtering"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(FLEN_A::OFF) + } + #[doc = "3-bit majority function (2 of 3)"] + #[inline(always)] + pub fn maj3(self) -> &'a mut W { + self.variant(FLEN_A::MAJ3) + } + #[doc = "5-bit majority function (3 of 5)"] + #[inline(always)] + pub fn maj5(self) -> &'a mut W { + self.variant(FLEN_A::MAJ5) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 24)) | ((value as u32 & 0x07) << 24); + self.w + } +} +#[doc = "Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum OUT_A { + #[doc = "0: The output of COMPn is not routed to the COMPn I/O port"] + OFF = 0, + #[doc = "1: The asynchronous output of COMPn is routed to the COMPn I/O port"] + ASYNC = 1, + #[doc = "2: The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port"] + SYNC = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: OUT_A) -> Self { + variant as _ + } +} +#[doc = "Field `OUT` reader - Output"] +pub struct OUT_R(crate::FieldReader); +impl OUT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + OUT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(OUT_A::OFF), + 1 => Some(OUT_A::ASYNC), + 2 => Some(OUT_A::SYNC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == OUT_A::OFF + } + #[doc = "Checks if the value of the field is `ASYNC`"] + #[inline(always)] + pub fn is_async(&self) -> bool { + **self == OUT_A::ASYNC + } + #[doc = "Checks if the value of the field is `SYNC`"] + #[inline(always)] + pub fn is_sync(&self) -> bool { + **self == OUT_A::SYNC + } +} +impl core::ops::Deref for OUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OUT` writer - Output"] +pub struct OUT_W<'a> { + w: &'a mut W, +} +impl<'a> OUT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: OUT_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "The output of COMPn is not routed to the COMPn I/O port"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(OUT_A::OFF) + } + #[doc = "The asynchronous output of COMPn is routed to the COMPn I/O port"] + #[inline(always)] + pub fn async_(self) -> &'a mut W { + self.variant(OUT_A::ASYNC) + } + #[doc = "The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port"] + #[inline(always)] + pub fn sync(self) -> &'a mut W { + self.variant(OUT_A::SYNC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 28)) | ((value as u32 & 0x03) << 28); + self.w + } +} +impl R { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Single-Shot Mode"] + #[inline(always)] + pub fn single(&self) -> SINGLE_R { + SINGLE_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 3:4 - Interrupt Selection"] + #[inline(always)] + pub fn intsel(&self) -> INTSEL_R { + INTSEL_R::new(((self.bits >> 3) & 0x03) as u8) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Negative Input Mux Selection"] + #[inline(always)] + pub fn muxneg(&self) -> MUXNEG_R { + MUXNEG_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bits 12:14 - Positive Input Mux Selection"] + #[inline(always)] + pub fn muxpos(&self) -> MUXPOS_R { + MUXPOS_R::new(((self.bits >> 12) & 0x07) as u8) + } + #[doc = "Bit 15 - Swap Inputs and Invert"] + #[inline(always)] + pub fn swap(&self) -> SWAP_R { + SWAP_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:17 - Speed Selection"] + #[inline(always)] + pub fn speed(&self) -> SPEED_R { + SPEED_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bit 19 - Hysteresis Enable"] + #[inline(always)] + pub fn hysten(&self) -> HYSTEN_R { + HYSTEN_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bits 24:26 - Filter Length"] + #[inline(always)] + pub fn flen(&self) -> FLEN_R { + FLEN_R::new(((self.bits >> 24) & 0x07) as u8) + } + #[doc = "Bits 28:29 - Output"] + #[inline(always)] + pub fn out(&self) -> OUT_R { + OUT_R::new(((self.bits >> 28) & 0x03) as u8) + } +} +impl W { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - Single-Shot Mode"] + #[inline(always)] + pub fn single(&mut self) -> SINGLE_W { + SINGLE_W { w: self } + } + #[doc = "Bits 3:4 - Interrupt Selection"] + #[inline(always)] + pub fn intsel(&mut self) -> INTSEL_W { + INTSEL_W { w: self } + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bits 8:10 - Negative Input Mux Selection"] + #[inline(always)] + pub fn muxneg(&mut self) -> MUXNEG_W { + MUXNEG_W { w: self } + } + #[doc = "Bits 12:14 - Positive Input Mux Selection"] + #[inline(always)] + pub fn muxpos(&mut self) -> MUXPOS_W { + MUXPOS_W { w: self } + } + #[doc = "Bit 15 - Swap Inputs and Invert"] + #[inline(always)] + pub fn swap(&mut self) -> SWAP_W { + SWAP_W { w: self } + } + #[doc = "Bits 16:17 - Speed Selection"] + #[inline(always)] + pub fn speed(&mut self) -> SPEED_W { + SPEED_W { w: self } + } + #[doc = "Bit 19 - Hysteresis Enable"] + #[inline(always)] + pub fn hysten(&mut self) -> HYSTEN_W { + HYSTEN_W { w: self } + } + #[doc = "Bits 24:26 - Filter Length"] + #[inline(always)] + pub fn flen(&mut self) -> FLEN_W { + FLEN_W { w: self } + } + #[doc = "Bits 28:29 - Output"] + #[inline(always)] + pub fn out(&mut self) -> OUT_W { + OUT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Comparator Control n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [compctrl](index.html) module"] +pub struct COMPCTRL_SPEC; +impl crate::RegisterSpec for COMPCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [compctrl::R](R) reader structure"] +impl crate::Readable for COMPCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [compctrl::W](W) writer structure"] +impl crate::Writable for COMPCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COMPCTRL[%s] +to value 0"] +impl crate::Resettable for COMPCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/ac/ctrla.rs b/pac/atsamc21j/src/ac/ctrla.rs new file mode 100644 index 000000000000..5f2c406226f4 --- /dev/null +++ b/pac/atsamc21j/src/ac/ctrla.rs @@ -0,0 +1,160 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/ac/ctrlb.rs b/pac/atsamc21j/src/ac/ctrlb.rs new file mode 100644 index 000000000000..fa9d604101c2 --- /dev/null +++ b/pac/atsamc21j/src/ac/ctrlb.rs @@ -0,0 +1,153 @@ +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `START0` writer - Comparator 0 Start Comparison"] +pub struct START0_W<'a> { + w: &'a mut W, +} +impl<'a> START0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `START1` writer - Comparator 1 Start Comparison"] +pub struct START1_W<'a> { + w: &'a mut W, +} +impl<'a> START1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `START2` writer - Comparator 2 Start Comparison"] +pub struct START2_W<'a> { + w: &'a mut W, +} +impl<'a> START2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `START3` writer - Comparator 3 Start Comparison"] +pub struct START3_W<'a> { + w: &'a mut W, +} +impl<'a> START3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +impl W { + #[doc = "Bit 0 - Comparator 0 Start Comparison"] + #[inline(always)] + pub fn start0(&mut self) -> START0_W { + START0_W { w: self } + } + #[doc = "Bit 1 - Comparator 1 Start Comparison"] + #[inline(always)] + pub fn start1(&mut self) -> START1_W { + START1_W { w: self } + } + #[doc = "Bit 2 - Comparator 2 Start Comparison"] + #[inline(always)] + pub fn start2(&mut self) -> START2_W { + START2_W { w: self } + } + #[doc = "Bit 3 - Comparator 3 Start Comparison"] + #[inline(always)] + pub fn start3(&mut self) -> START3_W { + START3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u8; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/ac/dbgctrl.rs b/pac/atsamc21j/src/ac/dbgctrl.rs new file mode 100644 index 000000000000..53636eb2b339 --- /dev/null +++ b/pac/atsamc21j/src/ac/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Debug Run"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Debug Run"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/ac/evctrl.rs b/pac/atsamc21j/src/ac/evctrl.rs new file mode 100644 index 000000000000..b2f64ee12108 --- /dev/null +++ b/pac/atsamc21j/src/ac/evctrl.rs @@ -0,0 +1,724 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COMPEO0` reader - Comparator 0 Event Output Enable"] +pub struct COMPEO0_R(crate::FieldReader); +impl COMPEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPEO0` writer - Comparator 0 Event Output Enable"] +pub struct COMPEO0_W<'a> { + w: &'a mut W, +} +impl<'a> COMPEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `COMPEO1` reader - Comparator 1 Event Output Enable"] +pub struct COMPEO1_R(crate::FieldReader); +impl COMPEO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPEO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPEO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPEO1` writer - Comparator 1 Event Output Enable"] +pub struct COMPEO1_W<'a> { + w: &'a mut W, +} +impl<'a> COMPEO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `COMPEO2` reader - Comparator 2 Event Output Enable"] +pub struct COMPEO2_R(crate::FieldReader); +impl COMPEO2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPEO2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPEO2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPEO2` writer - Comparator 2 Event Output Enable"] +pub struct COMPEO2_W<'a> { + w: &'a mut W, +} +impl<'a> COMPEO2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `COMPEO3` reader - Comparator 3 Event Output Enable"] +pub struct COMPEO3_R(crate::FieldReader); +impl COMPEO3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPEO3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPEO3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPEO3` writer - Comparator 3 Event Output Enable"] +pub struct COMPEO3_W<'a> { + w: &'a mut W, +} +impl<'a> COMPEO3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `WINEO0` reader - Window 0 Event Output Enable"] +pub struct WINEO0_R(crate::FieldReader); +impl WINEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINEO0` writer - Window 0 Event Output Enable"] +pub struct WINEO0_W<'a> { + w: &'a mut W, +} +impl<'a> WINEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `WINEO1` reader - Window 1 Event Output Enable"] +pub struct WINEO1_R(crate::FieldReader); +impl WINEO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINEO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINEO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINEO1` writer - Window 1 Event Output Enable"] +pub struct WINEO1_W<'a> { + w: &'a mut W, +} +impl<'a> WINEO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `COMPEI0` reader - Comparator 0 Event Input Enable"] +pub struct COMPEI0_R(crate::FieldReader); +impl COMPEI0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPEI0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPEI0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPEI0` writer - Comparator 0 Event Input Enable"] +pub struct COMPEI0_W<'a> { + w: &'a mut W, +} +impl<'a> COMPEI0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `COMPEI1` reader - Comparator 1 Event Input Enable"] +pub struct COMPEI1_R(crate::FieldReader); +impl COMPEI1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPEI1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPEI1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPEI1` writer - Comparator 1 Event Input Enable"] +pub struct COMPEI1_W<'a> { + w: &'a mut W, +} +impl<'a> COMPEI1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `COMPEI2` reader - Comparator 2 Event Input Enable"] +pub struct COMPEI2_R(crate::FieldReader); +impl COMPEI2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPEI2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPEI2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPEI2` writer - Comparator 2 Event Input Enable"] +pub struct COMPEI2_W<'a> { + w: &'a mut W, +} +impl<'a> COMPEI2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u16 & 0x01) << 10); + self.w + } +} +#[doc = "Field `COMPEI3` reader - Comparator 3 Event Input Enable"] +pub struct COMPEI3_R(crate::FieldReader); +impl COMPEI3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPEI3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPEI3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPEI3` writer - Comparator 3 Event Input Enable"] +pub struct COMPEI3_W<'a> { + w: &'a mut W, +} +impl<'a> COMPEI3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u16 & 0x01) << 11); + self.w + } +} +#[doc = "Field `INVEI0` reader - Comparator 0 Input Event Invert Enable"] +pub struct INVEI0_R(crate::FieldReader); +impl INVEI0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEI0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEI0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEI0` writer - Comparator 0 Input Event Invert Enable"] +pub struct INVEI0_W<'a> { + w: &'a mut W, +} +impl<'a> INVEI0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u16 & 0x01) << 12); + self.w + } +} +#[doc = "Field `INVEI1` reader - Comparator 1 Input Event Invert Enable"] +pub struct INVEI1_R(crate::FieldReader); +impl INVEI1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEI1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEI1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEI1` writer - Comparator 1 Input Event Invert Enable"] +pub struct INVEI1_W<'a> { + w: &'a mut W, +} +impl<'a> INVEI1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u16 & 0x01) << 13); + self.w + } +} +#[doc = "Field `INVEI2` reader - Comparator 2 Input Event Invert Enable"] +pub struct INVEI2_R(crate::FieldReader); +impl INVEI2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEI2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEI2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEI2` writer - Comparator 2 Input Event Invert Enable"] +pub struct INVEI2_W<'a> { + w: &'a mut W, +} +impl<'a> INVEI2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u16 & 0x01) << 14); + self.w + } +} +#[doc = "Field `INVEI3` reader - Comparator 3 Input Event Invert Enable"] +pub struct INVEI3_R(crate::FieldReader); +impl INVEI3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEI3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEI3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEI3` writer - Comparator 3 Input Event Invert Enable"] +pub struct INVEI3_W<'a> { + w: &'a mut W, +} +impl<'a> INVEI3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Comparator 0 Event Output Enable"] + #[inline(always)] + pub fn compeo0(&self) -> COMPEO0_R { + COMPEO0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Comparator 1 Event Output Enable"] + #[inline(always)] + pub fn compeo1(&self) -> COMPEO1_R { + COMPEO1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Comparator 2 Event Output Enable"] + #[inline(always)] + pub fn compeo2(&self) -> COMPEO2_R { + COMPEO2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Comparator 3 Event Output Enable"] + #[inline(always)] + pub fn compeo3(&self) -> COMPEO3_R { + COMPEO3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Window 0 Event Output Enable"] + #[inline(always)] + pub fn wineo0(&self) -> WINEO0_R { + WINEO0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Window 1 Event Output Enable"] + #[inline(always)] + pub fn wineo1(&self) -> WINEO1_R { + WINEO1_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 8 - Comparator 0 Event Input Enable"] + #[inline(always)] + pub fn compei0(&self) -> COMPEI0_R { + COMPEI0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Comparator 1 Event Input Enable"] + #[inline(always)] + pub fn compei1(&self) -> COMPEI1_R { + COMPEI1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Comparator 2 Event Input Enable"] + #[inline(always)] + pub fn compei2(&self) -> COMPEI2_R { + COMPEI2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Comparator 3 Event Input Enable"] + #[inline(always)] + pub fn compei3(&self) -> COMPEI3_R { + COMPEI3_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Comparator 0 Input Event Invert Enable"] + #[inline(always)] + pub fn invei0(&self) -> INVEI0_R { + INVEI0_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Comparator 1 Input Event Invert Enable"] + #[inline(always)] + pub fn invei1(&self) -> INVEI1_R { + INVEI1_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Comparator 2 Input Event Invert Enable"] + #[inline(always)] + pub fn invei2(&self) -> INVEI2_R { + INVEI2_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Comparator 3 Input Event Invert Enable"] + #[inline(always)] + pub fn invei3(&self) -> INVEI3_R { + INVEI3_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Comparator 0 Event Output Enable"] + #[inline(always)] + pub fn compeo0(&mut self) -> COMPEO0_W { + COMPEO0_W { w: self } + } + #[doc = "Bit 1 - Comparator 1 Event Output Enable"] + #[inline(always)] + pub fn compeo1(&mut self) -> COMPEO1_W { + COMPEO1_W { w: self } + } + #[doc = "Bit 2 - Comparator 2 Event Output Enable"] + #[inline(always)] + pub fn compeo2(&mut self) -> COMPEO2_W { + COMPEO2_W { w: self } + } + #[doc = "Bit 3 - Comparator 3 Event Output Enable"] + #[inline(always)] + pub fn compeo3(&mut self) -> COMPEO3_W { + COMPEO3_W { w: self } + } + #[doc = "Bit 4 - Window 0 Event Output Enable"] + #[inline(always)] + pub fn wineo0(&mut self) -> WINEO0_W { + WINEO0_W { w: self } + } + #[doc = "Bit 5 - Window 1 Event Output Enable"] + #[inline(always)] + pub fn wineo1(&mut self) -> WINEO1_W { + WINEO1_W { w: self } + } + #[doc = "Bit 8 - Comparator 0 Event Input Enable"] + #[inline(always)] + pub fn compei0(&mut self) -> COMPEI0_W { + COMPEI0_W { w: self } + } + #[doc = "Bit 9 - Comparator 1 Event Input Enable"] + #[inline(always)] + pub fn compei1(&mut self) -> COMPEI1_W { + COMPEI1_W { w: self } + } + #[doc = "Bit 10 - Comparator 2 Event Input Enable"] + #[inline(always)] + pub fn compei2(&mut self) -> COMPEI2_W { + COMPEI2_W { w: self } + } + #[doc = "Bit 11 - Comparator 3 Event Input Enable"] + #[inline(always)] + pub fn compei3(&mut self) -> COMPEI3_W { + COMPEI3_W { w: self } + } + #[doc = "Bit 12 - Comparator 0 Input Event Invert Enable"] + #[inline(always)] + pub fn invei0(&mut self) -> INVEI0_W { + INVEI0_W { w: self } + } + #[doc = "Bit 13 - Comparator 1 Input Event Invert Enable"] + #[inline(always)] + pub fn invei1(&mut self) -> INVEI1_W { + INVEI1_W { w: self } + } + #[doc = "Bit 14 - Comparator 2 Input Event Invert Enable"] + #[inline(always)] + pub fn invei2(&mut self) -> INVEI2_W { + INVEI2_W { w: self } + } + #[doc = "Bit 15 - Comparator 3 Input Event Invert Enable"] + #[inline(always)] + pub fn invei3(&mut self) -> INVEI3_W { + INVEI3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/ac/intenclr.rs b/pac/atsamc21j/src/ac/intenclr.rs new file mode 100644 index 000000000000..e948bee83d3f --- /dev/null +++ b/pac/atsamc21j/src/ac/intenclr.rs @@ -0,0 +1,348 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COMP0` reader - Comparator 0 Interrupt Enable"] +pub struct COMP0_R(crate::FieldReader); +impl COMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP0` writer - Comparator 0 Interrupt Enable"] +pub struct COMP0_W<'a> { + w: &'a mut W, +} +impl<'a> COMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `COMP1` reader - Comparator 1 Interrupt Enable"] +pub struct COMP1_R(crate::FieldReader); +impl COMP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP1` writer - Comparator 1 Interrupt Enable"] +pub struct COMP1_W<'a> { + w: &'a mut W, +} +impl<'a> COMP1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `COMP2` reader - Comparator 2 Interrupt Enable"] +pub struct COMP2_R(crate::FieldReader); +impl COMP2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP2` writer - Comparator 2 Interrupt Enable"] +pub struct COMP2_W<'a> { + w: &'a mut W, +} +impl<'a> COMP2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `COMP3` reader - Comparator 3 Interrupt Enable"] +pub struct COMP3_R(crate::FieldReader); +impl COMP3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP3` writer - Comparator 3 Interrupt Enable"] +pub struct COMP3_W<'a> { + w: &'a mut W, +} +impl<'a> COMP3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `WIN0` reader - Window 0 Interrupt Enable"] +pub struct WIN0_R(crate::FieldReader); +impl WIN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WIN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WIN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WIN0` writer - Window 0 Interrupt Enable"] +pub struct WIN0_W<'a> { + w: &'a mut W, +} +impl<'a> WIN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `WIN1` reader - Window 1 Interrupt Enable"] +pub struct WIN1_R(crate::FieldReader); +impl WIN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WIN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WIN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WIN1` writer - Window 1 Interrupt Enable"] +pub struct WIN1_W<'a> { + w: &'a mut W, +} +impl<'a> WIN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Comparator 0 Interrupt Enable"] + #[inline(always)] + pub fn comp0(&self) -> COMP0_R { + COMP0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Comparator 1 Interrupt Enable"] + #[inline(always)] + pub fn comp1(&self) -> COMP1_R { + COMP1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Comparator 2 Interrupt Enable"] + #[inline(always)] + pub fn comp2(&self) -> COMP2_R { + COMP2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Comparator 3 Interrupt Enable"] + #[inline(always)] + pub fn comp3(&self) -> COMP3_R { + COMP3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Window 0 Interrupt Enable"] + #[inline(always)] + pub fn win0(&self) -> WIN0_R { + WIN0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Window 1 Interrupt Enable"] + #[inline(always)] + pub fn win1(&self) -> WIN1_R { + WIN1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Comparator 0 Interrupt Enable"] + #[inline(always)] + pub fn comp0(&mut self) -> COMP0_W { + COMP0_W { w: self } + } + #[doc = "Bit 1 - Comparator 1 Interrupt Enable"] + #[inline(always)] + pub fn comp1(&mut self) -> COMP1_W { + COMP1_W { w: self } + } + #[doc = "Bit 2 - Comparator 2 Interrupt Enable"] + #[inline(always)] + pub fn comp2(&mut self) -> COMP2_W { + COMP2_W { w: self } + } + #[doc = "Bit 3 - Comparator 3 Interrupt Enable"] + #[inline(always)] + pub fn comp3(&mut self) -> COMP3_W { + COMP3_W { w: self } + } + #[doc = "Bit 4 - Window 0 Interrupt Enable"] + #[inline(always)] + pub fn win0(&mut self) -> WIN0_W { + WIN0_W { w: self } + } + #[doc = "Bit 5 - Window 1 Interrupt Enable"] + #[inline(always)] + pub fn win1(&mut self) -> WIN1_W { + WIN1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/ac/intenset.rs b/pac/atsamc21j/src/ac/intenset.rs new file mode 100644 index 000000000000..b631f5136fb6 --- /dev/null +++ b/pac/atsamc21j/src/ac/intenset.rs @@ -0,0 +1,348 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COMP0` reader - Comparator 0 Interrupt Enable"] +pub struct COMP0_R(crate::FieldReader); +impl COMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP0` writer - Comparator 0 Interrupt Enable"] +pub struct COMP0_W<'a> { + w: &'a mut W, +} +impl<'a> COMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `COMP1` reader - Comparator 1 Interrupt Enable"] +pub struct COMP1_R(crate::FieldReader); +impl COMP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP1` writer - Comparator 1 Interrupt Enable"] +pub struct COMP1_W<'a> { + w: &'a mut W, +} +impl<'a> COMP1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `COMP2` reader - Comparator 2 Interrupt Enable"] +pub struct COMP2_R(crate::FieldReader); +impl COMP2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP2` writer - Comparator 2 Interrupt Enable"] +pub struct COMP2_W<'a> { + w: &'a mut W, +} +impl<'a> COMP2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `COMP3` reader - Comparator 3 Interrupt Enable"] +pub struct COMP3_R(crate::FieldReader); +impl COMP3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP3` writer - Comparator 3 Interrupt Enable"] +pub struct COMP3_W<'a> { + w: &'a mut W, +} +impl<'a> COMP3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `WIN0` reader - Window 0 Interrupt Enable"] +pub struct WIN0_R(crate::FieldReader); +impl WIN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WIN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WIN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WIN0` writer - Window 0 Interrupt Enable"] +pub struct WIN0_W<'a> { + w: &'a mut W, +} +impl<'a> WIN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `WIN1` reader - Window 1 Interrupt Enable"] +pub struct WIN1_R(crate::FieldReader); +impl WIN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WIN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WIN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WIN1` writer - Window 1 Interrupt Enable"] +pub struct WIN1_W<'a> { + w: &'a mut W, +} +impl<'a> WIN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Comparator 0 Interrupt Enable"] + #[inline(always)] + pub fn comp0(&self) -> COMP0_R { + COMP0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Comparator 1 Interrupt Enable"] + #[inline(always)] + pub fn comp1(&self) -> COMP1_R { + COMP1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Comparator 2 Interrupt Enable"] + #[inline(always)] + pub fn comp2(&self) -> COMP2_R { + COMP2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Comparator 3 Interrupt Enable"] + #[inline(always)] + pub fn comp3(&self) -> COMP3_R { + COMP3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Window 0 Interrupt Enable"] + #[inline(always)] + pub fn win0(&self) -> WIN0_R { + WIN0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Window 1 Interrupt Enable"] + #[inline(always)] + pub fn win1(&self) -> WIN1_R { + WIN1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Comparator 0 Interrupt Enable"] + #[inline(always)] + pub fn comp0(&mut self) -> COMP0_W { + COMP0_W { w: self } + } + #[doc = "Bit 1 - Comparator 1 Interrupt Enable"] + #[inline(always)] + pub fn comp1(&mut self) -> COMP1_W { + COMP1_W { w: self } + } + #[doc = "Bit 2 - Comparator 2 Interrupt Enable"] + #[inline(always)] + pub fn comp2(&mut self) -> COMP2_W { + COMP2_W { w: self } + } + #[doc = "Bit 3 - Comparator 3 Interrupt Enable"] + #[inline(always)] + pub fn comp3(&mut self) -> COMP3_W { + COMP3_W { w: self } + } + #[doc = "Bit 4 - Window 0 Interrupt Enable"] + #[inline(always)] + pub fn win0(&mut self) -> WIN0_W { + WIN0_W { w: self } + } + #[doc = "Bit 5 - Window 1 Interrupt Enable"] + #[inline(always)] + pub fn win1(&mut self) -> WIN1_W { + WIN1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/ac/intflag.rs b/pac/atsamc21j/src/ac/intflag.rs new file mode 100644 index 000000000000..6557a5e48464 --- /dev/null +++ b/pac/atsamc21j/src/ac/intflag.rs @@ -0,0 +1,348 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COMP0` reader - Comparator 0"] +pub struct COMP0_R(crate::FieldReader); +impl COMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP0` writer - Comparator 0"] +pub struct COMP0_W<'a> { + w: &'a mut W, +} +impl<'a> COMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `COMP1` reader - Comparator 1"] +pub struct COMP1_R(crate::FieldReader); +impl COMP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP1` writer - Comparator 1"] +pub struct COMP1_W<'a> { + w: &'a mut W, +} +impl<'a> COMP1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `COMP2` reader - Comparator 2"] +pub struct COMP2_R(crate::FieldReader); +impl COMP2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP2` writer - Comparator 2"] +pub struct COMP2_W<'a> { + w: &'a mut W, +} +impl<'a> COMP2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `COMP3` reader - Comparator 3"] +pub struct COMP3_R(crate::FieldReader); +impl COMP3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP3` writer - Comparator 3"] +pub struct COMP3_W<'a> { + w: &'a mut W, +} +impl<'a> COMP3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `WIN0` reader - Window 0"] +pub struct WIN0_R(crate::FieldReader); +impl WIN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WIN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WIN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WIN0` writer - Window 0"] +pub struct WIN0_W<'a> { + w: &'a mut W, +} +impl<'a> WIN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `WIN1` reader - Window 1"] +pub struct WIN1_R(crate::FieldReader); +impl WIN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WIN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WIN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WIN1` writer - Window 1"] +pub struct WIN1_W<'a> { + w: &'a mut W, +} +impl<'a> WIN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Comparator 0"] + #[inline(always)] + pub fn comp0(&self) -> COMP0_R { + COMP0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Comparator 1"] + #[inline(always)] + pub fn comp1(&self) -> COMP1_R { + COMP1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Comparator 2"] + #[inline(always)] + pub fn comp2(&self) -> COMP2_R { + COMP2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Comparator 3"] + #[inline(always)] + pub fn comp3(&self) -> COMP3_R { + COMP3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Window 0"] + #[inline(always)] + pub fn win0(&self) -> WIN0_R { + WIN0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Window 1"] + #[inline(always)] + pub fn win1(&self) -> WIN1_R { + WIN1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Comparator 0"] + #[inline(always)] + pub fn comp0(&mut self) -> COMP0_W { + COMP0_W { w: self } + } + #[doc = "Bit 1 - Comparator 1"] + #[inline(always)] + pub fn comp1(&mut self) -> COMP1_W { + COMP1_W { w: self } + } + #[doc = "Bit 2 - Comparator 2"] + #[inline(always)] + pub fn comp2(&mut self) -> COMP2_W { + COMP2_W { w: self } + } + #[doc = "Bit 3 - Comparator 3"] + #[inline(always)] + pub fn comp3(&mut self) -> COMP3_W { + COMP3_W { w: self } + } + #[doc = "Bit 4 - Window 0"] + #[inline(always)] + pub fn win0(&mut self) -> WIN0_W { + WIN0_W { w: self } + } + #[doc = "Bit 5 - Window 1"] + #[inline(always)] + pub fn win1(&mut self) -> WIN1_W { + WIN1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/ac/scaler.rs b/pac/atsamc21j/src/ac/scaler.rs new file mode 100644 index 000000000000..091cacfaeb4b --- /dev/null +++ b/pac/atsamc21j/src/ac/scaler.rs @@ -0,0 +1,104 @@ +#[doc = "Register `SCALER[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SCALER[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `VALUE` reader - Scaler Value"] +pub struct VALUE_R(crate::FieldReader); +impl VALUE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + VALUE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VALUE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VALUE` writer - Scaler Value"] +pub struct VALUE_W<'a> { + w: &'a mut W, +} +impl<'a> VALUE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u8 & 0x3f); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Scaler Value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - Scaler Value"] + #[inline(always)] + pub fn value(&mut self) -> VALUE_W { + VALUE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Scaler n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [scaler](index.html) module"] +pub struct SCALER_SPEC; +impl crate::RegisterSpec for SCALER_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [scaler::R](R) reader structure"] +impl crate::Readable for SCALER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [scaler::W](W) writer structure"] +impl crate::Writable for SCALER_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SCALER[%s] +to value 0"] +impl crate::Resettable for SCALER_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/ac/statusa.rs b/pac/atsamc21j/src/ac/statusa.rs new file mode 100644 index 000000000000..f79619555497 --- /dev/null +++ b/pac/atsamc21j/src/ac/statusa.rs @@ -0,0 +1,237 @@ +#[doc = "Register `STATUSA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `STATE0` reader - Comparator 0 Current State"] +pub struct STATE0_R(crate::FieldReader); +impl STATE0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STATE0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STATE0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STATE1` reader - Comparator 1 Current State"] +pub struct STATE1_R(crate::FieldReader); +impl STATE1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STATE1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STATE1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STATE2` reader - Comparator 2 Current State"] +pub struct STATE2_R(crate::FieldReader); +impl STATE2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STATE2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STATE2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STATE3` reader - Comparator 3 Current State"] +pub struct STATE3_R(crate::FieldReader); +impl STATE3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STATE3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STATE3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Window 0 Current State\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WSTATE0_A { + #[doc = "0: Signal is above window"] + ABOVE = 0, + #[doc = "1: Signal is inside window"] + INSIDE = 1, + #[doc = "2: Signal is below window"] + BELOW = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WSTATE0_A) -> Self { + variant as _ + } +} +#[doc = "Field `WSTATE0` reader - Window 0 Current State"] +pub struct WSTATE0_R(crate::FieldReader); +impl WSTATE0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WSTATE0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(WSTATE0_A::ABOVE), + 1 => Some(WSTATE0_A::INSIDE), + 2 => Some(WSTATE0_A::BELOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `ABOVE`"] + #[inline(always)] + pub fn is_above(&self) -> bool { + **self == WSTATE0_A::ABOVE + } + #[doc = "Checks if the value of the field is `INSIDE`"] + #[inline(always)] + pub fn is_inside(&self) -> bool { + **self == WSTATE0_A::INSIDE + } + #[doc = "Checks if the value of the field is `BELOW`"] + #[inline(always)] + pub fn is_below(&self) -> bool { + **self == WSTATE0_A::BELOW + } +} +impl core::ops::Deref for WSTATE0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Window 1 Current State\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WSTATE1_A { + #[doc = "0: Signal is above window"] + ABOVE = 0, + #[doc = "1: Signal is inside window"] + INSIDE = 1, + #[doc = "2: Signal is below window"] + BELOW = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WSTATE1_A) -> Self { + variant as _ + } +} +#[doc = "Field `WSTATE1` reader - Window 1 Current State"] +pub struct WSTATE1_R(crate::FieldReader); +impl WSTATE1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WSTATE1_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(WSTATE1_A::ABOVE), + 1 => Some(WSTATE1_A::INSIDE), + 2 => Some(WSTATE1_A::BELOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `ABOVE`"] + #[inline(always)] + pub fn is_above(&self) -> bool { + **self == WSTATE1_A::ABOVE + } + #[doc = "Checks if the value of the field is `INSIDE`"] + #[inline(always)] + pub fn is_inside(&self) -> bool { + **self == WSTATE1_A::INSIDE + } + #[doc = "Checks if the value of the field is `BELOW`"] + #[inline(always)] + pub fn is_below(&self) -> bool { + **self == WSTATE1_A::BELOW + } +} +impl core::ops::Deref for WSTATE1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Comparator 0 Current State"] + #[inline(always)] + pub fn state0(&self) -> STATE0_R { + STATE0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Comparator 1 Current State"] + #[inline(always)] + pub fn state1(&self) -> STATE1_R { + STATE1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Comparator 2 Current State"] + #[inline(always)] + pub fn state2(&self) -> STATE2_R { + STATE2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Comparator 3 Current State"] + #[inline(always)] + pub fn state3(&self) -> STATE3_R { + STATE3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bits 4:5 - Window 0 Current State"] + #[inline(always)] + pub fn wstate0(&self) -> WSTATE0_R { + WSTATE0_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bits 6:7 - Window 1 Current State"] + #[inline(always)] + pub fn wstate1(&self) -> WSTATE1_R { + WSTATE1_R::new(((self.bits >> 6) & 0x03) as u8) + } +} +#[doc = "Status A\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [statusa](index.html) module"] +pub struct STATUSA_SPEC; +impl crate::RegisterSpec for STATUSA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [statusa::R](R) reader structure"] +impl crate::Readable for STATUSA_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUSA to value 0"] +impl crate::Resettable for STATUSA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/ac/statusb.rs b/pac/atsamc21j/src/ac/statusb.rs new file mode 100644 index 000000000000..1f7035958bd8 --- /dev/null +++ b/pac/atsamc21j/src/ac/statusb.rs @@ -0,0 +1,113 @@ +#[doc = "Register `STATUSB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `READY0` reader - Comparator 0 Ready"] +pub struct READY0_R(crate::FieldReader); +impl READY0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + READY0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for READY0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `READY1` reader - Comparator 1 Ready"] +pub struct READY1_R(crate::FieldReader); +impl READY1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + READY1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for READY1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `READY2` reader - Comparator 2 Ready"] +pub struct READY2_R(crate::FieldReader); +impl READY2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + READY2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for READY2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `READY3` reader - Comparator 3 Ready"] +pub struct READY3_R(crate::FieldReader); +impl READY3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + READY3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for READY3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Comparator 0 Ready"] + #[inline(always)] + pub fn ready0(&self) -> READY0_R { + READY0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Comparator 1 Ready"] + #[inline(always)] + pub fn ready1(&self) -> READY1_R { + READY1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Comparator 2 Ready"] + #[inline(always)] + pub fn ready2(&self) -> READY2_R { + READY2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Comparator 3 Ready"] + #[inline(always)] + pub fn ready3(&self) -> READY3_R { + READY3_R::new(((self.bits >> 3) & 0x01) != 0) + } +} +#[doc = "Status B\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [statusb](index.html) module"] +pub struct STATUSB_SPEC; +impl crate::RegisterSpec for STATUSB_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [statusb::R](R) reader structure"] +impl crate::Readable for STATUSB_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUSB to value 0"] +impl crate::Resettable for STATUSB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/ac/syncbusy.rs b/pac/atsamc21j/src/ac/syncbusy.rs new file mode 100644 index 000000000000..bbd5b5cbe18f --- /dev/null +++ b/pac/atsamc21j/src/ac/syncbusy.rs @@ -0,0 +1,173 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - Enable Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINCTRL` reader - WINCTRL Synchronization Busy"] +pub struct WINCTRL_R(crate::FieldReader); +impl WINCTRL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINCTRL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINCTRL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPCTRL0` reader - COMPCTRL 0 Synchronization Busy"] +pub struct COMPCTRL0_R(crate::FieldReader); +impl COMPCTRL0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPCTRL0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPCTRL0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPCTRL1` reader - COMPCTRL 1 Synchronization Busy"] +pub struct COMPCTRL1_R(crate::FieldReader); +impl COMPCTRL1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPCTRL1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPCTRL1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPCTRL2` reader - COMPCTRL 2 Synchronization Busy"] +pub struct COMPCTRL2_R(crate::FieldReader); +impl COMPCTRL2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPCTRL2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPCTRL2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPCTRL3` reader - COMPCTRL 3 Synchronization Busy"] +pub struct COMPCTRL3_R(crate::FieldReader); +impl COMPCTRL3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPCTRL3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPCTRL3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - WINCTRL Synchronization Busy"] + #[inline(always)] + pub fn winctrl(&self) -> WINCTRL_R { + WINCTRL_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - COMPCTRL 0 Synchronization Busy"] + #[inline(always)] + pub fn compctrl0(&self) -> COMPCTRL0_R { + COMPCTRL0_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - COMPCTRL 1 Synchronization Busy"] + #[inline(always)] + pub fn compctrl1(&self) -> COMPCTRL1_R { + COMPCTRL1_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - COMPCTRL 2 Synchronization Busy"] + #[inline(always)] + pub fn compctrl2(&self) -> COMPCTRL2_R { + COMPCTRL2_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - COMPCTRL 3 Synchronization Busy"] + #[inline(always)] + pub fn compctrl3(&self) -> COMPCTRL3_R { + COMPCTRL3_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +#[doc = "Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/ac/winctrl.rs b/pac/atsamc21j/src/ac/winctrl.rs new file mode 100644 index 000000000000..e3fe941f07bd --- /dev/null +++ b/pac/atsamc21j/src/ac/winctrl.rs @@ -0,0 +1,384 @@ +#[doc = "Register `WINCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WINCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WEN0` reader - Window 0 Mode Enable"] +pub struct WEN0_R(crate::FieldReader); +impl WEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WEN0` writer - Window 0 Mode Enable"] +pub struct WEN0_W<'a> { + w: &'a mut W, +} +impl<'a> WEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Window 0 Interrupt Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WINTSEL0_A { + #[doc = "0: Interrupt on signal above window"] + ABOVE = 0, + #[doc = "1: Interrupt on signal inside window"] + INSIDE = 1, + #[doc = "2: Interrupt on signal below window"] + BELOW = 2, + #[doc = "3: Interrupt on signal outside window"] + OUTSIDE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WINTSEL0_A) -> Self { + variant as _ + } +} +#[doc = "Field `WINTSEL0` reader - Window 0 Interrupt Selection"] +pub struct WINTSEL0_R(crate::FieldReader); +impl WINTSEL0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WINTSEL0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> WINTSEL0_A { + match self.bits { + 0 => WINTSEL0_A::ABOVE, + 1 => WINTSEL0_A::INSIDE, + 2 => WINTSEL0_A::BELOW, + 3 => WINTSEL0_A::OUTSIDE, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `ABOVE`"] + #[inline(always)] + pub fn is_above(&self) -> bool { + **self == WINTSEL0_A::ABOVE + } + #[doc = "Checks if the value of the field is `INSIDE`"] + #[inline(always)] + pub fn is_inside(&self) -> bool { + **self == WINTSEL0_A::INSIDE + } + #[doc = "Checks if the value of the field is `BELOW`"] + #[inline(always)] + pub fn is_below(&self) -> bool { + **self == WINTSEL0_A::BELOW + } + #[doc = "Checks if the value of the field is `OUTSIDE`"] + #[inline(always)] + pub fn is_outside(&self) -> bool { + **self == WINTSEL0_A::OUTSIDE + } +} +impl core::ops::Deref for WINTSEL0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINTSEL0` writer - Window 0 Interrupt Selection"] +pub struct WINTSEL0_W<'a> { + w: &'a mut W, +} +impl<'a> WINTSEL0_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WINTSEL0_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Interrupt on signal above window"] + #[inline(always)] + pub fn above(self) -> &'a mut W { + self.variant(WINTSEL0_A::ABOVE) + } + #[doc = "Interrupt on signal inside window"] + #[inline(always)] + pub fn inside(self) -> &'a mut W { + self.variant(WINTSEL0_A::INSIDE) + } + #[doc = "Interrupt on signal below window"] + #[inline(always)] + pub fn below(self) -> &'a mut W { + self.variant(WINTSEL0_A::BELOW) + } + #[doc = "Interrupt on signal outside window"] + #[inline(always)] + pub fn outside(self) -> &'a mut W { + self.variant(WINTSEL0_A::OUTSIDE) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 1)) | ((value as u8 & 0x03) << 1); + self.w + } +} +#[doc = "Field `WEN1` reader - Window 1 Mode Enable"] +pub struct WEN1_R(crate::FieldReader); +impl WEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WEN1` writer - Window 1 Mode Enable"] +pub struct WEN1_W<'a> { + w: &'a mut W, +} +impl<'a> WEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Window 1 Interrupt Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WINTSEL1_A { + #[doc = "0: Interrupt on signal above window"] + ABOVE = 0, + #[doc = "1: Interrupt on signal inside window"] + INSIDE = 1, + #[doc = "2: Interrupt on signal below window"] + BELOW = 2, + #[doc = "3: Interrupt on signal outside window"] + OUTSIDE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WINTSEL1_A) -> Self { + variant as _ + } +} +#[doc = "Field `WINTSEL1` reader - Window 1 Interrupt Selection"] +pub struct WINTSEL1_R(crate::FieldReader); +impl WINTSEL1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WINTSEL1_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> WINTSEL1_A { + match self.bits { + 0 => WINTSEL1_A::ABOVE, + 1 => WINTSEL1_A::INSIDE, + 2 => WINTSEL1_A::BELOW, + 3 => WINTSEL1_A::OUTSIDE, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `ABOVE`"] + #[inline(always)] + pub fn is_above(&self) -> bool { + **self == WINTSEL1_A::ABOVE + } + #[doc = "Checks if the value of the field is `INSIDE`"] + #[inline(always)] + pub fn is_inside(&self) -> bool { + **self == WINTSEL1_A::INSIDE + } + #[doc = "Checks if the value of the field is `BELOW`"] + #[inline(always)] + pub fn is_below(&self) -> bool { + **self == WINTSEL1_A::BELOW + } + #[doc = "Checks if the value of the field is `OUTSIDE`"] + #[inline(always)] + pub fn is_outside(&self) -> bool { + **self == WINTSEL1_A::OUTSIDE + } +} +impl core::ops::Deref for WINTSEL1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINTSEL1` writer - Window 1 Interrupt Selection"] +pub struct WINTSEL1_W<'a> { + w: &'a mut W, +} +impl<'a> WINTSEL1_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WINTSEL1_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Interrupt on signal above window"] + #[inline(always)] + pub fn above(self) -> &'a mut W { + self.variant(WINTSEL1_A::ABOVE) + } + #[doc = "Interrupt on signal inside window"] + #[inline(always)] + pub fn inside(self) -> &'a mut W { + self.variant(WINTSEL1_A::INSIDE) + } + #[doc = "Interrupt on signal below window"] + #[inline(always)] + pub fn below(self) -> &'a mut W { + self.variant(WINTSEL1_A::BELOW) + } + #[doc = "Interrupt on signal outside window"] + #[inline(always)] + pub fn outside(self) -> &'a mut W { + self.variant(WINTSEL1_A::OUTSIDE) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 5)) | ((value as u8 & 0x03) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Window 0 Mode Enable"] + #[inline(always)] + pub fn wen0(&self) -> WEN0_R { + WEN0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bits 1:2 - Window 0 Interrupt Selection"] + #[inline(always)] + pub fn wintsel0(&self) -> WINTSEL0_R { + WINTSEL0_R::new(((self.bits >> 1) & 0x03) as u8) + } + #[doc = "Bit 4 - Window 1 Mode Enable"] + #[inline(always)] + pub fn wen1(&self) -> WEN1_R { + WEN1_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bits 5:6 - Window 1 Interrupt Selection"] + #[inline(always)] + pub fn wintsel1(&self) -> WINTSEL1_R { + WINTSEL1_R::new(((self.bits >> 5) & 0x03) as u8) + } +} +impl W { + #[doc = "Bit 0 - Window 0 Mode Enable"] + #[inline(always)] + pub fn wen0(&mut self) -> WEN0_W { + WEN0_W { w: self } + } + #[doc = "Bits 1:2 - Window 0 Interrupt Selection"] + #[inline(always)] + pub fn wintsel0(&mut self) -> WINTSEL0_W { + WINTSEL0_W { w: self } + } + #[doc = "Bit 4 - Window 1 Mode Enable"] + #[inline(always)] + pub fn wen1(&mut self) -> WEN1_W { + WEN1_W { w: self } + } + #[doc = "Bits 5:6 - Window 1 Interrupt Selection"] + #[inline(always)] + pub fn wintsel1(&mut self) -> WINTSEL1_W { + WINTSEL1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Window Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [winctrl](index.html) module"] +pub struct WINCTRL_SPEC; +impl crate::RegisterSpec for WINCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [winctrl::R](R) reader structure"] +impl crate::Readable for WINCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [winctrl::W](W) writer structure"] +impl crate::Writable for WINCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WINCTRL to value 0"] +impl crate::Resettable for WINCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/adc0.rs b/pac/atsamc21j/src/adc0.rs new file mode 100644 index 000000000000..453f56ed28c8 --- /dev/null +++ b/pac/atsamc21j/src/adc0.rs @@ -0,0 +1,141 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + #[doc = "0x01 - Control B"] + pub ctrlb: crate::Reg, + #[doc = "0x02 - Reference Control"] + pub refctrl: crate::Reg, + #[doc = "0x03 - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x04 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x05 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x06 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x07 - Sequence Status"] + pub seqstatus: crate::Reg, + #[doc = "0x08 - Input Control"] + pub inputctrl: crate::Reg, + #[doc = "0x0a - Control C"] + pub ctrlc: crate::Reg, + #[doc = "0x0c - Average Control"] + pub avgctrl: crate::Reg, + #[doc = "0x0d - Sample Time Control"] + pub sampctrl: crate::Reg, + #[doc = "0x0e - Window Monitor Lower Threshold"] + pub winlt: crate::Reg, + #[doc = "0x10 - Window Monitor Upper Threshold"] + pub winut: crate::Reg, + #[doc = "0x12 - Gain Correction"] + pub gaincorr: crate::Reg, + #[doc = "0x14 - Offset Correction"] + pub offsetcorr: crate::Reg, + _reserved16: [u8; 0x02], + #[doc = "0x18 - Software Trigger"] + pub swtrig: crate::Reg, + _reserved17: [u8; 0x03], + #[doc = "0x1c - Debug Control"] + pub dbgctrl: crate::Reg, + _reserved18: [u8; 0x03], + #[doc = "0x20 - Synchronization Busy"] + pub syncbusy: crate::Reg, + _reserved19: [u8; 0x02], + #[doc = "0x24 - Result"] + pub result: crate::Reg, + _reserved20: [u8; 0x02], + #[doc = "0x28 - Sequence Control"] + pub seqctrl: crate::Reg, + #[doc = "0x2c - Calibration"] + pub calib: crate::Reg, +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "Control B"] +pub mod ctrlb; +#[doc = "REFCTRL register accessor: an alias for `Reg`"] +pub type REFCTRL = crate::Reg; +#[doc = "Reference Control"] +pub mod refctrl; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "SEQSTATUS register accessor: an alias for `Reg`"] +pub type SEQSTATUS = crate::Reg; +#[doc = "Sequence Status"] +pub mod seqstatus; +#[doc = "INPUTCTRL register accessor: an alias for `Reg`"] +pub type INPUTCTRL = crate::Reg; +#[doc = "Input Control"] +pub mod inputctrl; +#[doc = "CTRLC register accessor: an alias for `Reg`"] +pub type CTRLC = crate::Reg; +#[doc = "Control C"] +pub mod ctrlc; +#[doc = "AVGCTRL register accessor: an alias for `Reg`"] +pub type AVGCTRL = crate::Reg; +#[doc = "Average Control"] +pub mod avgctrl; +#[doc = "SAMPCTRL register accessor: an alias for `Reg`"] +pub type SAMPCTRL = crate::Reg; +#[doc = "Sample Time Control"] +pub mod sampctrl; +#[doc = "WINLT register accessor: an alias for `Reg`"] +pub type WINLT = crate::Reg; +#[doc = "Window Monitor Lower Threshold"] +pub mod winlt; +#[doc = "WINUT register accessor: an alias for `Reg`"] +pub type WINUT = crate::Reg; +#[doc = "Window Monitor Upper Threshold"] +pub mod winut; +#[doc = "GAINCORR register accessor: an alias for `Reg`"] +pub type GAINCORR = crate::Reg; +#[doc = "Gain Correction"] +pub mod gaincorr; +#[doc = "OFFSETCORR register accessor: an alias for `Reg`"] +pub type OFFSETCORR = crate::Reg; +#[doc = "Offset Correction"] +pub mod offsetcorr; +#[doc = "SWTRIG register accessor: an alias for `Reg`"] +pub type SWTRIG = crate::Reg; +#[doc = "Software Trigger"] +pub mod swtrig; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Busy"] +pub mod syncbusy; +#[doc = "RESULT register accessor: an alias for `Reg`"] +pub type RESULT = crate::Reg; +#[doc = "Result"] +pub mod result; +#[doc = "SEQCTRL register accessor: an alias for `Reg`"] +pub type SEQCTRL = crate::Reg; +#[doc = "Sequence Control"] +pub mod seqctrl; +#[doc = "CALIB register accessor: an alias for `Reg`"] +pub type CALIB = crate::Reg; +#[doc = "Calibration"] +pub mod calib; diff --git a/pac/atsamc21j/src/adc0/avgctrl.rs b/pac/atsamc21j/src/adc0/avgctrl.rs new file mode 100644 index 000000000000..ddb735715c98 --- /dev/null +++ b/pac/atsamc21j/src/adc0/avgctrl.rs @@ -0,0 +1,306 @@ +#[doc = "Register `AVGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `AVGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Number of Samples to be Collected\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SAMPLENUM_A { + #[doc = "0: 1 sample"] + _1 = 0, + #[doc = "1: 2 samples"] + _2 = 1, + #[doc = "2: 4 samples"] + _4 = 2, + #[doc = "3: 8 samples"] + _8 = 3, + #[doc = "4: 16 samples"] + _16 = 4, + #[doc = "5: 32 samples"] + _32 = 5, + #[doc = "6: 64 samples"] + _64 = 6, + #[doc = "7: 128 samples"] + _128 = 7, + #[doc = "8: 256 samples"] + _256 = 8, + #[doc = "9: 512 samples"] + _512 = 9, + #[doc = "10: 1024 samples"] + _1024 = 10, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SAMPLENUM_A) -> Self { + variant as _ + } +} +#[doc = "Field `SAMPLENUM` reader - Number of Samples to be Collected"] +pub struct SAMPLENUM_R(crate::FieldReader); +impl SAMPLENUM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SAMPLENUM_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SAMPLENUM_A::_1), + 1 => Some(SAMPLENUM_A::_2), + 2 => Some(SAMPLENUM_A::_4), + 3 => Some(SAMPLENUM_A::_8), + 4 => Some(SAMPLENUM_A::_16), + 5 => Some(SAMPLENUM_A::_32), + 6 => Some(SAMPLENUM_A::_64), + 7 => Some(SAMPLENUM_A::_128), + 8 => Some(SAMPLENUM_A::_256), + 9 => Some(SAMPLENUM_A::_512), + 10 => Some(SAMPLENUM_A::_1024), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_1`"] + #[inline(always)] + pub fn is_1(&self) -> bool { + **self == SAMPLENUM_A::_1 + } + #[doc = "Checks if the value of the field is `_2`"] + #[inline(always)] + pub fn is_2(&self) -> bool { + **self == SAMPLENUM_A::_2 + } + #[doc = "Checks if the value of the field is `_4`"] + #[inline(always)] + pub fn is_4(&self) -> bool { + **self == SAMPLENUM_A::_4 + } + #[doc = "Checks if the value of the field is `_8`"] + #[inline(always)] + pub fn is_8(&self) -> bool { + **self == SAMPLENUM_A::_8 + } + #[doc = "Checks if the value of the field is `_16`"] + #[inline(always)] + pub fn is_16(&self) -> bool { + **self == SAMPLENUM_A::_16 + } + #[doc = "Checks if the value of the field is `_32`"] + #[inline(always)] + pub fn is_32(&self) -> bool { + **self == SAMPLENUM_A::_32 + } + #[doc = "Checks if the value of the field is `_64`"] + #[inline(always)] + pub fn is_64(&self) -> bool { + **self == SAMPLENUM_A::_64 + } + #[doc = "Checks if the value of the field is `_128`"] + #[inline(always)] + pub fn is_128(&self) -> bool { + **self == SAMPLENUM_A::_128 + } + #[doc = "Checks if the value of the field is `_256`"] + #[inline(always)] + pub fn is_256(&self) -> bool { + **self == SAMPLENUM_A::_256 + } + #[doc = "Checks if the value of the field is `_512`"] + #[inline(always)] + pub fn is_512(&self) -> bool { + **self == SAMPLENUM_A::_512 + } + #[doc = "Checks if the value of the field is `_1024`"] + #[inline(always)] + pub fn is_1024(&self) -> bool { + **self == SAMPLENUM_A::_1024 + } +} +impl core::ops::Deref for SAMPLENUM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SAMPLENUM` writer - Number of Samples to be Collected"] +pub struct SAMPLENUM_W<'a> { + w: &'a mut W, +} +impl<'a> SAMPLENUM_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SAMPLENUM_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "1 sample"] + #[inline(always)] + pub fn _1(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_1) + } + #[doc = "2 samples"] + #[inline(always)] + pub fn _2(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_2) + } + #[doc = "4 samples"] + #[inline(always)] + pub fn _4(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_4) + } + #[doc = "8 samples"] + #[inline(always)] + pub fn _8(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_8) + } + #[doc = "16 samples"] + #[inline(always)] + pub fn _16(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_16) + } + #[doc = "32 samples"] + #[inline(always)] + pub fn _32(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_32) + } + #[doc = "64 samples"] + #[inline(always)] + pub fn _64(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_64) + } + #[doc = "128 samples"] + #[inline(always)] + pub fn _128(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_128) + } + #[doc = "256 samples"] + #[inline(always)] + pub fn _256(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_256) + } + #[doc = "512 samples"] + #[inline(always)] + pub fn _512(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_512) + } + #[doc = "1024 samples"] + #[inline(always)] + pub fn _1024(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +#[doc = "Field `ADJRES` reader - Adjusting Result / Division Coefficient"] +pub struct ADJRES_R(crate::FieldReader); +impl ADJRES_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ADJRES_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADJRES_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADJRES` writer - Adjusting Result / Division Coefficient"] +pub struct ADJRES_W<'a> { + w: &'a mut W, +} +impl<'a> ADJRES_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 4)) | ((value as u8 & 0x07) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Number of Samples to be Collected"] + #[inline(always)] + pub fn samplenum(&self) -> SAMPLENUM_R { + SAMPLENUM_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:6 - Adjusting Result / Division Coefficient"] + #[inline(always)] + pub fn adjres(&self) -> ADJRES_R { + ADJRES_R::new(((self.bits >> 4) & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Number of Samples to be Collected"] + #[inline(always)] + pub fn samplenum(&mut self) -> SAMPLENUM_W { + SAMPLENUM_W { w: self } + } + #[doc = "Bits 4:6 - Adjusting Result / Division Coefficient"] + #[inline(always)] + pub fn adjres(&mut self) -> ADJRES_W { + ADJRES_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Average Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [avgctrl](index.html) module"] +pub struct AVGCTRL_SPEC; +impl crate::RegisterSpec for AVGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [avgctrl::R](R) reader structure"] +impl crate::Readable for AVGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [avgctrl::W](W) writer structure"] +impl crate::Writable for AVGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets AVGCTRL to value 0"] +impl crate::Resettable for AVGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/adc0/calib.rs b/pac/atsamc21j/src/adc0/calib.rs new file mode 100644 index 000000000000..8a1a99b8c47d --- /dev/null +++ b/pac/atsamc21j/src/adc0/calib.rs @@ -0,0 +1,140 @@ +#[doc = "Register `CALIB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CALIB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BIASCOMP` reader - Bias Comparator Scaling"] +pub struct BIASCOMP_R(crate::FieldReader); +impl BIASCOMP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BIASCOMP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BIASCOMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BIASCOMP` writer - Bias Comparator Scaling"] +pub struct BIASCOMP_W<'a> { + w: &'a mut W, +} +impl<'a> BIASCOMP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u16 & 0x07); + self.w + } +} +#[doc = "Field `BIASREFBUF` reader - Bias Reference Buffer Scaling"] +pub struct BIASREFBUF_R(crate::FieldReader); +impl BIASREFBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BIASREFBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BIASREFBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BIASREFBUF` writer - Bias Reference Buffer Scaling"] +pub struct BIASREFBUF_W<'a> { + w: &'a mut W, +} +impl<'a> BIASREFBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u16 & 0x07) << 8); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Bias Comparator Scaling"] + #[inline(always)] + pub fn biascomp(&self) -> BIASCOMP_R { + BIASCOMP_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bits 8:10 - Bias Reference Buffer Scaling"] + #[inline(always)] + pub fn biasrefbuf(&self) -> BIASREFBUF_R { + BIASREFBUF_R::new(((self.bits >> 8) & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Bias Comparator Scaling"] + #[inline(always)] + pub fn biascomp(&mut self) -> BIASCOMP_W { + BIASCOMP_W { w: self } + } + #[doc = "Bits 8:10 - Bias Reference Buffer Scaling"] + #[inline(always)] + pub fn biasrefbuf(&mut self) -> BIASREFBUF_W { + BIASREFBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Calibration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [calib](index.html) module"] +pub struct CALIB_SPEC; +impl crate::RegisterSpec for CALIB_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [calib::R](R) reader structure"] +impl crate::Readable for CALIB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [calib::W](W) writer structure"] +impl crate::Writable for CALIB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CALIB to value 0"] +impl crate::Resettable for CALIB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/adc0/ctrla.rs b/pac/atsamc21j/src/adc0/ctrla.rs new file mode 100644 index 000000000000..47c681045f95 --- /dev/null +++ b/pac/atsamc21j/src/adc0/ctrla.rs @@ -0,0 +1,301 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SLAVEEN` reader - Slave Enable"] +pub struct SLAVEEN_R(crate::FieldReader); +impl SLAVEEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLAVEEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SLAVEEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLAVEEN` writer - Slave Enable"] +pub struct SLAVEEN_W<'a> { + w: &'a mut W, +} +impl<'a> SLAVEEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run During Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run During Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - On Demand Control"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - On Demand Control"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 5 - Slave Enable"] + #[inline(always)] + pub fn slaveen(&self) -> SLAVEEN_R { + SLAVEEN_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Run During Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 5 - Slave Enable"] + #[inline(always)] + pub fn slaveen(&mut self) -> SLAVEEN_W { + SLAVEEN_W { w: self } + } + #[doc = "Bit 6 - Run During Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/adc0/ctrlb.rs b/pac/atsamc21j/src/adc0/ctrlb.rs new file mode 100644 index 000000000000..4d39688fc975 --- /dev/null +++ b/pac/atsamc21j/src/adc0/ctrlb.rs @@ -0,0 +1,230 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Prescaler Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: Peripheral clock / 2"] + DIV2 = 0, + #[doc = "1: Peripheral clock / 4"] + DIV4 = 1, + #[doc = "2: Peripheral clock / 8"] + DIV8 = 2, + #[doc = "3: Peripheral clock / 16"] + DIV16 = 3, + #[doc = "4: Peripheral clock / 32"] + DIV32 = 4, + #[doc = "5: Peripheral clock / 64"] + DIV64 = 5, + #[doc = "6: Peripheral clock / 128"] + DIV128 = 6, + #[doc = "7: Peripheral clock / 256"] + DIV256 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler Configuration"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PRESCALER_A { + match self.bits { + 0 => PRESCALER_A::DIV2, + 1 => PRESCALER_A::DIV4, + 2 => PRESCALER_A::DIV8, + 3 => PRESCALER_A::DIV16, + 4 => PRESCALER_A::DIV32, + 5 => PRESCALER_A::DIV64, + 6 => PRESCALER_A::DIV128, + 7 => PRESCALER_A::DIV256, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == PRESCALER_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == PRESCALER_A::DIV128 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler Configuration"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Peripheral clock / 2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "Peripheral clock / 4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "Peripheral clock / 8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "Peripheral clock / 16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "Peripheral clock / 32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV32) + } + #[doc = "Peripheral clock / 64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "Peripheral clock / 128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV128) + } + #[doc = "Peripheral clock / 256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Prescaler Configuration"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Prescaler Configuration"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/adc0/ctrlc.rs b/pac/atsamc21j/src/adc0/ctrlc.rs new file mode 100644 index 000000000000..1b6ac5a6ea17 --- /dev/null +++ b/pac/atsamc21j/src/adc0/ctrlc.rs @@ -0,0 +1,624 @@ +#[doc = "Register `CTRLC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIFFMODE` reader - Differential Mode"] +pub struct DIFFMODE_R(crate::FieldReader); +impl DIFFMODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIFFMODE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIFFMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIFFMODE` writer - Differential Mode"] +pub struct DIFFMODE_W<'a> { + w: &'a mut W, +} +impl<'a> DIFFMODE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `LEFTADJ` reader - Left-Adjusted Result"] +pub struct LEFTADJ_R(crate::FieldReader); +impl LEFTADJ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LEFTADJ_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LEFTADJ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LEFTADJ` writer - Left-Adjusted Result"] +pub struct LEFTADJ_W<'a> { + w: &'a mut W, +} +impl<'a> LEFTADJ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `FREERUN` reader - Free Running Mode"] +pub struct FREERUN_R(crate::FieldReader); +impl FREERUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FREERUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FREERUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FREERUN` writer - Free Running Mode"] +pub struct FREERUN_W<'a> { + w: &'a mut W, +} +impl<'a> FREERUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CORREN` reader - Digital Correction Logic Enable"] +pub struct CORREN_R(crate::FieldReader); +impl CORREN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CORREN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CORREN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CORREN` writer - Digital Correction Logic Enable"] +pub struct CORREN_W<'a> { + w: &'a mut W, +} +impl<'a> CORREN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Conversion Result Resolution\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum RESSEL_A { + #[doc = "0: 12-bit"] + _12BIT = 0, + #[doc = "1: 16-bit averaging mode"] + _16BIT = 1, + #[doc = "2: 10-bit"] + _10BIT = 2, + #[doc = "3: 8-bit"] + _8BIT = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RESSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `RESSEL` reader - Conversion Result Resolution"] +pub struct RESSEL_R(crate::FieldReader); +impl RESSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RESSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RESSEL_A { + match self.bits { + 0 => RESSEL_A::_12BIT, + 1 => RESSEL_A::_16BIT, + 2 => RESSEL_A::_10BIT, + 3 => RESSEL_A::_8BIT, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `_12BIT`"] + #[inline(always)] + pub fn is_12bit(&self) -> bool { + **self == RESSEL_A::_12BIT + } + #[doc = "Checks if the value of the field is `_16BIT`"] + #[inline(always)] + pub fn is_16bit(&self) -> bool { + **self == RESSEL_A::_16BIT + } + #[doc = "Checks if the value of the field is `_10BIT`"] + #[inline(always)] + pub fn is_10bit(&self) -> bool { + **self == RESSEL_A::_10BIT + } + #[doc = "Checks if the value of the field is `_8BIT`"] + #[inline(always)] + pub fn is_8bit(&self) -> bool { + **self == RESSEL_A::_8BIT + } +} +impl core::ops::Deref for RESSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESSEL` writer - Conversion Result Resolution"] +pub struct RESSEL_W<'a> { + w: &'a mut W, +} +impl<'a> RESSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RESSEL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "12-bit"] + #[inline(always)] + pub fn _12bit(self) -> &'a mut W { + self.variant(RESSEL_A::_12BIT) + } + #[doc = "16-bit averaging mode"] + #[inline(always)] + pub fn _16bit(self) -> &'a mut W { + self.variant(RESSEL_A::_16BIT) + } + #[doc = "10-bit"] + #[inline(always)] + pub fn _10bit(self) -> &'a mut W { + self.variant(RESSEL_A::_10BIT) + } + #[doc = "8-bit"] + #[inline(always)] + pub fn _8bit(self) -> &'a mut W { + self.variant(RESSEL_A::_8BIT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u16 & 0x03) << 4); + self.w + } +} +#[doc = "Field `R2R` reader - Rail-to-Rail mode enable"] +pub struct R2R_R(crate::FieldReader); +impl R2R_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + R2R_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for R2R_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `R2R` writer - Rail-to-Rail mode enable"] +pub struct R2R_W<'a> { + w: &'a mut W, +} +impl<'a> R2R_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Window Monitor Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WINMODE_A { + #[doc = "0: No window mode (default)"] + DISABLE = 0, + #[doc = "1: RESULT > WINLT"] + MODE1 = 1, + #[doc = "2: RESULT < WINUT"] + MODE2 = 2, + #[doc = "3: WINLT < RESULT < WINUT"] + MODE3 = 3, + #[doc = "4: !(WINLT < RESULT < WINUT)"] + MODE4 = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WINMODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `WINMODE` reader - Window Monitor Mode"] +pub struct WINMODE_R(crate::FieldReader); +impl WINMODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WINMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(WINMODE_A::DISABLE), + 1 => Some(WINMODE_A::MODE1), + 2 => Some(WINMODE_A::MODE2), + 3 => Some(WINMODE_A::MODE3), + 4 => Some(WINMODE_A::MODE4), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == WINMODE_A::DISABLE + } + #[doc = "Checks if the value of the field is `MODE1`"] + #[inline(always)] + pub fn is_mode1(&self) -> bool { + **self == WINMODE_A::MODE1 + } + #[doc = "Checks if the value of the field is `MODE2`"] + #[inline(always)] + pub fn is_mode2(&self) -> bool { + **self == WINMODE_A::MODE2 + } + #[doc = "Checks if the value of the field is `MODE3`"] + #[inline(always)] + pub fn is_mode3(&self) -> bool { + **self == WINMODE_A::MODE3 + } + #[doc = "Checks if the value of the field is `MODE4`"] + #[inline(always)] + pub fn is_mode4(&self) -> bool { + **self == WINMODE_A::MODE4 + } +} +impl core::ops::Deref for WINMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMODE` writer - Window Monitor Mode"] +pub struct WINMODE_W<'a> { + w: &'a mut W, +} +impl<'a> WINMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WINMODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No window mode (default)"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(WINMODE_A::DISABLE) + } + #[doc = "RESULT > WINLT"] + #[inline(always)] + pub fn mode1(self) -> &'a mut W { + self.variant(WINMODE_A::MODE1) + } + #[doc = "RESULT < WINUT"] + #[inline(always)] + pub fn mode2(self) -> &'a mut W { + self.variant(WINMODE_A::MODE2) + } + #[doc = "WINLT < RESULT < WINUT"] + #[inline(always)] + pub fn mode3(self) -> &'a mut W { + self.variant(WINMODE_A::MODE3) + } + #[doc = "!(WINLT < RESULT < WINUT)"] + #[inline(always)] + pub fn mode4(self) -> &'a mut W { + self.variant(WINMODE_A::MODE4) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u16 & 0x07) << 8); + self.w + } +} +#[doc = "Dual Mode Trigger Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DUALSEL_A { + #[doc = "0: Start event or software trigger will start a conversion on both ADCs"] + BOTH = 0, + #[doc = "1: START event or software trigger will alternately start a conversion on ADC0 and ADC1"] + INTERLEAVE = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DUALSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `DUALSEL` reader - Dual Mode Trigger Selection"] +pub struct DUALSEL_R(crate::FieldReader); +impl DUALSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DUALSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(DUALSEL_A::BOTH), + 1 => Some(DUALSEL_A::INTERLEAVE), + _ => None, + } + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == DUALSEL_A::BOTH + } + #[doc = "Checks if the value of the field is `INTERLEAVE`"] + #[inline(always)] + pub fn is_interleave(&self) -> bool { + **self == DUALSEL_A::INTERLEAVE + } +} +impl core::ops::Deref for DUALSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DUALSEL` writer - Dual Mode Trigger Selection"] +pub struct DUALSEL_W<'a> { + w: &'a mut W, +} +impl<'a> DUALSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DUALSEL_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Start event or software trigger will start a conversion on both ADCs"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(DUALSEL_A::BOTH) + } + #[doc = "START event or software trigger will alternately start a conversion on ADC0 and ADC1"] + #[inline(always)] + pub fn interleave(self) -> &'a mut W { + self.variant(DUALSEL_A::INTERLEAVE) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 12)) | ((value as u16 & 0x03) << 12); + self.w + } +} +impl R { + #[doc = "Bit 0 - Differential Mode"] + #[inline(always)] + pub fn diffmode(&self) -> DIFFMODE_R { + DIFFMODE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Left-Adjusted Result"] + #[inline(always)] + pub fn leftadj(&self) -> LEFTADJ_R { + LEFTADJ_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Free Running Mode"] + #[inline(always)] + pub fn freerun(&self) -> FREERUN_R { + FREERUN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Digital Correction Logic Enable"] + #[inline(always)] + pub fn corren(&self) -> CORREN_R { + CORREN_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bits 4:5 - Conversion Result Resolution"] + #[inline(always)] + pub fn ressel(&self) -> RESSEL_R { + RESSEL_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bit 7 - Rail-to-Rail mode enable"] + #[inline(always)] + pub fn r2r(&self) -> R2R_R { + R2R_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Window Monitor Mode"] + #[inline(always)] + pub fn winmode(&self) -> WINMODE_R { + WINMODE_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bits 12:13 - Dual Mode Trigger Selection"] + #[inline(always)] + pub fn dualsel(&self) -> DUALSEL_R { + DUALSEL_R::new(((self.bits >> 12) & 0x03) as u8) + } +} +impl W { + #[doc = "Bit 0 - Differential Mode"] + #[inline(always)] + pub fn diffmode(&mut self) -> DIFFMODE_W { + DIFFMODE_W { w: self } + } + #[doc = "Bit 1 - Left-Adjusted Result"] + #[inline(always)] + pub fn leftadj(&mut self) -> LEFTADJ_W { + LEFTADJ_W { w: self } + } + #[doc = "Bit 2 - Free Running Mode"] + #[inline(always)] + pub fn freerun(&mut self) -> FREERUN_W { + FREERUN_W { w: self } + } + #[doc = "Bit 3 - Digital Correction Logic Enable"] + #[inline(always)] + pub fn corren(&mut self) -> CORREN_W { + CORREN_W { w: self } + } + #[doc = "Bits 4:5 - Conversion Result Resolution"] + #[inline(always)] + pub fn ressel(&mut self) -> RESSEL_W { + RESSEL_W { w: self } + } + #[doc = "Bit 7 - Rail-to-Rail mode enable"] + #[inline(always)] + pub fn r2r(&mut self) -> R2R_W { + R2R_W { w: self } + } + #[doc = "Bits 8:10 - Window Monitor Mode"] + #[inline(always)] + pub fn winmode(&mut self) -> WINMODE_W { + WINMODE_W { w: self } + } + #[doc = "Bits 12:13 - Dual Mode Trigger Selection"] + #[inline(always)] + pub fn dualsel(&mut self) -> DUALSEL_W { + DUALSEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control C\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlc](index.html) module"] +pub struct CTRLC_SPEC; +impl crate::RegisterSpec for CTRLC_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrlc::R](R) reader structure"] +impl crate::Readable for CTRLC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlc::W](W) writer structure"] +impl crate::Writable for CTRLC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLC to value 0"] +impl crate::Resettable for CTRLC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/adc0/dbgctrl.rs b/pac/atsamc21j/src/adc0/dbgctrl.rs new file mode 100644 index 000000000000..53636eb2b339 --- /dev/null +++ b/pac/atsamc21j/src/adc0/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Debug Run"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Debug Run"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/adc0/evctrl.rs b/pac/atsamc21j/src/adc0/evctrl.rs new file mode 100644 index 000000000000..295508f82de3 --- /dev/null +++ b/pac/atsamc21j/src/adc0/evctrl.rs @@ -0,0 +1,348 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FLUSHEI` reader - Flush Event Input Enable"] +pub struct FLUSHEI_R(crate::FieldReader); +impl FLUSHEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FLUSHEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FLUSHEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLUSHEI` writer - Flush Event Input Enable"] +pub struct FLUSHEI_W<'a> { + w: &'a mut W, +} +impl<'a> FLUSHEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `STARTEI` reader - Start Conversion Event Input Enable"] +pub struct STARTEI_R(crate::FieldReader); +impl STARTEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STARTEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STARTEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STARTEI` writer - Start Conversion Event Input Enable"] +pub struct STARTEI_W<'a> { + w: &'a mut W, +} +impl<'a> STARTEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `FLUSHINV` reader - Flush Event Invert Enable"] +pub struct FLUSHINV_R(crate::FieldReader); +impl FLUSHINV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FLUSHINV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FLUSHINV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLUSHINV` writer - Flush Event Invert Enable"] +pub struct FLUSHINV_W<'a> { + w: &'a mut W, +} +impl<'a> FLUSHINV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `STARTINV` reader - Start Event Invert Enable"] +pub struct STARTINV_R(crate::FieldReader); +impl STARTINV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STARTINV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STARTINV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STARTINV` writer - Start Event Invert Enable"] +pub struct STARTINV_W<'a> { + w: &'a mut W, +} +impl<'a> STARTINV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `RESRDYEO` reader - Result Ready Event Out"] +pub struct RESRDYEO_R(crate::FieldReader); +impl RESRDYEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESRDYEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESRDYEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESRDYEO` writer - Result Ready Event Out"] +pub struct RESRDYEO_W<'a> { + w: &'a mut W, +} +impl<'a> RESRDYEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `WINMONEO` reader - Window Monitor Event Out"] +pub struct WINMONEO_R(crate::FieldReader); +impl WINMONEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINMONEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINMONEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMONEO` writer - Window Monitor Event Out"] +pub struct WINMONEO_W<'a> { + w: &'a mut W, +} +impl<'a> WINMONEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Flush Event Input Enable"] + #[inline(always)] + pub fn flushei(&self) -> FLUSHEI_R { + FLUSHEI_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Start Conversion Event Input Enable"] + #[inline(always)] + pub fn startei(&self) -> STARTEI_R { + STARTEI_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Flush Event Invert Enable"] + #[inline(always)] + pub fn flushinv(&self) -> FLUSHINV_R { + FLUSHINV_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Start Event Invert Enable"] + #[inline(always)] + pub fn startinv(&self) -> STARTINV_R { + STARTINV_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Result Ready Event Out"] + #[inline(always)] + pub fn resrdyeo(&self) -> RESRDYEO_R { + RESRDYEO_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Window Monitor Event Out"] + #[inline(always)] + pub fn winmoneo(&self) -> WINMONEO_R { + WINMONEO_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Flush Event Input Enable"] + #[inline(always)] + pub fn flushei(&mut self) -> FLUSHEI_W { + FLUSHEI_W { w: self } + } + #[doc = "Bit 1 - Start Conversion Event Input Enable"] + #[inline(always)] + pub fn startei(&mut self) -> STARTEI_W { + STARTEI_W { w: self } + } + #[doc = "Bit 2 - Flush Event Invert Enable"] + #[inline(always)] + pub fn flushinv(&mut self) -> FLUSHINV_W { + FLUSHINV_W { w: self } + } + #[doc = "Bit 3 - Start Event Invert Enable"] + #[inline(always)] + pub fn startinv(&mut self) -> STARTINV_W { + STARTINV_W { w: self } + } + #[doc = "Bit 4 - Result Ready Event Out"] + #[inline(always)] + pub fn resrdyeo(&mut self) -> RESRDYEO_W { + RESRDYEO_W { w: self } + } + #[doc = "Bit 5 - Window Monitor Event Out"] + #[inline(always)] + pub fn winmoneo(&mut self) -> WINMONEO_W { + WINMONEO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/adc0/gaincorr.rs b/pac/atsamc21j/src/adc0/gaincorr.rs new file mode 100644 index 000000000000..496cb8c6021c --- /dev/null +++ b/pac/atsamc21j/src/adc0/gaincorr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `GAINCORR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GAINCORR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `GAINCORR` reader - Gain Correction Value"] +pub struct GAINCORR_R(crate::FieldReader); +impl GAINCORR_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + GAINCORR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GAINCORR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GAINCORR` writer - Gain Correction Value"] +pub struct GAINCORR_W<'a> { + w: &'a mut W, +} +impl<'a> GAINCORR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0fff) | (value as u16 & 0x0fff); + self.w + } +} +impl R { + #[doc = "Bits 0:11 - Gain Correction Value"] + #[inline(always)] + pub fn gaincorr(&self) -> GAINCORR_R { + GAINCORR_R::new((self.bits & 0x0fff) as u16) + } +} +impl W { + #[doc = "Bits 0:11 - Gain Correction Value"] + #[inline(always)] + pub fn gaincorr(&mut self) -> GAINCORR_W { + GAINCORR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Gain Correction\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gaincorr](index.html) module"] +pub struct GAINCORR_SPEC; +impl crate::RegisterSpec for GAINCORR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [gaincorr::R](R) reader structure"] +impl crate::Readable for GAINCORR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gaincorr::W](W) writer structure"] +impl crate::Writable for GAINCORR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets GAINCORR to value 0"] +impl crate::Resettable for GAINCORR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/adc0/inputctrl.rs b/pac/atsamc21j/src/adc0/inputctrl.rs new file mode 100644 index 000000000000..82367a5d38c7 --- /dev/null +++ b/pac/atsamc21j/src/adc0/inputctrl.rs @@ -0,0 +1,485 @@ +#[doc = "Register `INPUTCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INPUTCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Positive Mux Input Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MUXPOS_A { + #[doc = "0: ADC AIN0 Pin"] + AIN0 = 0, + #[doc = "1: ADC AIN1 Pin"] + AIN1 = 1, + #[doc = "2: ADC AIN2 Pin"] + AIN2 = 2, + #[doc = "3: ADC AIN3 Pin"] + AIN3 = 3, + #[doc = "4: ADC AIN4 Pin"] + AIN4 = 4, + #[doc = "5: ADC AIN5 Pin"] + AIN5 = 5, + #[doc = "6: ADC AIN6 Pin"] + AIN6 = 6, + #[doc = "7: ADC AIN7 Pin"] + AIN7 = 7, + #[doc = "8: ADC AIN8 Pin"] + AIN8 = 8, + #[doc = "9: ADC AIN9 Pin"] + AIN9 = 9, + #[doc = "10: ADC AIN10 Pin"] + AIN10 = 10, + #[doc = "11: ADC AIN11 Pin"] + AIN11 = 11, + #[doc = "25: Bandgap Voltage"] + BANDGAP = 25, + #[doc = "26: 1/4 Scaled Core Supply"] + SCALEDCOREVCC = 26, + #[doc = "27: 1/4 Scaled I/O Supply"] + SCALEDIOVCC = 27, + #[doc = "28: DAC Output"] + DAC = 28, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MUXPOS_A) -> Self { + variant as _ + } +} +#[doc = "Field `MUXPOS` reader - Positive Mux Input Selection"] +pub struct MUXPOS_R(crate::FieldReader); +impl MUXPOS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MUXPOS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MUXPOS_A::AIN0), + 1 => Some(MUXPOS_A::AIN1), + 2 => Some(MUXPOS_A::AIN2), + 3 => Some(MUXPOS_A::AIN3), + 4 => Some(MUXPOS_A::AIN4), + 5 => Some(MUXPOS_A::AIN5), + 6 => Some(MUXPOS_A::AIN6), + 7 => Some(MUXPOS_A::AIN7), + 8 => Some(MUXPOS_A::AIN8), + 9 => Some(MUXPOS_A::AIN9), + 10 => Some(MUXPOS_A::AIN10), + 11 => Some(MUXPOS_A::AIN11), + 25 => Some(MUXPOS_A::BANDGAP), + 26 => Some(MUXPOS_A::SCALEDCOREVCC), + 27 => Some(MUXPOS_A::SCALEDIOVCC), + 28 => Some(MUXPOS_A::DAC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `AIN0`"] + #[inline(always)] + pub fn is_ain0(&self) -> bool { + **self == MUXPOS_A::AIN0 + } + #[doc = "Checks if the value of the field is `AIN1`"] + #[inline(always)] + pub fn is_ain1(&self) -> bool { + **self == MUXPOS_A::AIN1 + } + #[doc = "Checks if the value of the field is `AIN2`"] + #[inline(always)] + pub fn is_ain2(&self) -> bool { + **self == MUXPOS_A::AIN2 + } + #[doc = "Checks if the value of the field is `AIN3`"] + #[inline(always)] + pub fn is_ain3(&self) -> bool { + **self == MUXPOS_A::AIN3 + } + #[doc = "Checks if the value of the field is `AIN4`"] + #[inline(always)] + pub fn is_ain4(&self) -> bool { + **self == MUXPOS_A::AIN4 + } + #[doc = "Checks if the value of the field is `AIN5`"] + #[inline(always)] + pub fn is_ain5(&self) -> bool { + **self == MUXPOS_A::AIN5 + } + #[doc = "Checks if the value of the field is `AIN6`"] + #[inline(always)] + pub fn is_ain6(&self) -> bool { + **self == MUXPOS_A::AIN6 + } + #[doc = "Checks if the value of the field is `AIN7`"] + #[inline(always)] + pub fn is_ain7(&self) -> bool { + **self == MUXPOS_A::AIN7 + } + #[doc = "Checks if the value of the field is `AIN8`"] + #[inline(always)] + pub fn is_ain8(&self) -> bool { + **self == MUXPOS_A::AIN8 + } + #[doc = "Checks if the value of the field is `AIN9`"] + #[inline(always)] + pub fn is_ain9(&self) -> bool { + **self == MUXPOS_A::AIN9 + } + #[doc = "Checks if the value of the field is `AIN10`"] + #[inline(always)] + pub fn is_ain10(&self) -> bool { + **self == MUXPOS_A::AIN10 + } + #[doc = "Checks if the value of the field is `AIN11`"] + #[inline(always)] + pub fn is_ain11(&self) -> bool { + **self == MUXPOS_A::AIN11 + } + #[doc = "Checks if the value of the field is `BANDGAP`"] + #[inline(always)] + pub fn is_bandgap(&self) -> bool { + **self == MUXPOS_A::BANDGAP + } + #[doc = "Checks if the value of the field is `SCALEDCOREVCC`"] + #[inline(always)] + pub fn is_scaledcorevcc(&self) -> bool { + **self == MUXPOS_A::SCALEDCOREVCC + } + #[doc = "Checks if the value of the field is `SCALEDIOVCC`"] + #[inline(always)] + pub fn is_scalediovcc(&self) -> bool { + **self == MUXPOS_A::SCALEDIOVCC + } + #[doc = "Checks if the value of the field is `DAC`"] + #[inline(always)] + pub fn is_dac(&self) -> bool { + **self == MUXPOS_A::DAC + } +} +impl core::ops::Deref for MUXPOS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MUXPOS` writer - Positive Mux Input Selection"] +pub struct MUXPOS_W<'a> { + w: &'a mut W, +} +impl<'a> MUXPOS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MUXPOS_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "ADC AIN0 Pin"] + #[inline(always)] + pub fn ain0(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN0) + } + #[doc = "ADC AIN1 Pin"] + #[inline(always)] + pub fn ain1(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN1) + } + #[doc = "ADC AIN2 Pin"] + #[inline(always)] + pub fn ain2(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN2) + } + #[doc = "ADC AIN3 Pin"] + #[inline(always)] + pub fn ain3(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN3) + } + #[doc = "ADC AIN4 Pin"] + #[inline(always)] + pub fn ain4(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN4) + } + #[doc = "ADC AIN5 Pin"] + #[inline(always)] + pub fn ain5(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN5) + } + #[doc = "ADC AIN6 Pin"] + #[inline(always)] + pub fn ain6(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN6) + } + #[doc = "ADC AIN7 Pin"] + #[inline(always)] + pub fn ain7(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN7) + } + #[doc = "ADC AIN8 Pin"] + #[inline(always)] + pub fn ain8(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN8) + } + #[doc = "ADC AIN9 Pin"] + #[inline(always)] + pub fn ain9(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN9) + } + #[doc = "ADC AIN10 Pin"] + #[inline(always)] + pub fn ain10(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN10) + } + #[doc = "ADC AIN11 Pin"] + #[inline(always)] + pub fn ain11(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN11) + } + #[doc = "Bandgap Voltage"] + #[inline(always)] + pub fn bandgap(self) -> &'a mut W { + self.variant(MUXPOS_A::BANDGAP) + } + #[doc = "1/4 Scaled Core Supply"] + #[inline(always)] + pub fn scaledcorevcc(self) -> &'a mut W { + self.variant(MUXPOS_A::SCALEDCOREVCC) + } + #[doc = "1/4 Scaled I/O Supply"] + #[inline(always)] + pub fn scalediovcc(self) -> &'a mut W { + self.variant(MUXPOS_A::SCALEDIOVCC) + } + #[doc = "DAC Output"] + #[inline(always)] + pub fn dac(self) -> &'a mut W { + self.variant(MUXPOS_A::DAC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u16 & 0x1f); + self.w + } +} +#[doc = "Negative Mux Input Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MUXNEG_A { + #[doc = "0: ADC AIN0 Pin"] + AIN0 = 0, + #[doc = "1: ADC AIN1 Pin"] + AIN1 = 1, + #[doc = "2: ADC AIN2 Pin"] + AIN2 = 2, + #[doc = "3: ADC AIN3 Pin"] + AIN3 = 3, + #[doc = "4: ADC AIN4 Pin"] + AIN4 = 4, + #[doc = "5: ADC AIN5 Pin"] + AIN5 = 5, + #[doc = "24: Internal Ground"] + GND = 24, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MUXNEG_A) -> Self { + variant as _ + } +} +#[doc = "Field `MUXNEG` reader - Negative Mux Input Selection"] +pub struct MUXNEG_R(crate::FieldReader); +impl MUXNEG_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MUXNEG_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MUXNEG_A::AIN0), + 1 => Some(MUXNEG_A::AIN1), + 2 => Some(MUXNEG_A::AIN2), + 3 => Some(MUXNEG_A::AIN3), + 4 => Some(MUXNEG_A::AIN4), + 5 => Some(MUXNEG_A::AIN5), + 24 => Some(MUXNEG_A::GND), + _ => None, + } + } + #[doc = "Checks if the value of the field is `AIN0`"] + #[inline(always)] + pub fn is_ain0(&self) -> bool { + **self == MUXNEG_A::AIN0 + } + #[doc = "Checks if the value of the field is `AIN1`"] + #[inline(always)] + pub fn is_ain1(&self) -> bool { + **self == MUXNEG_A::AIN1 + } + #[doc = "Checks if the value of the field is `AIN2`"] + #[inline(always)] + pub fn is_ain2(&self) -> bool { + **self == MUXNEG_A::AIN2 + } + #[doc = "Checks if the value of the field is `AIN3`"] + #[inline(always)] + pub fn is_ain3(&self) -> bool { + **self == MUXNEG_A::AIN3 + } + #[doc = "Checks if the value of the field is `AIN4`"] + #[inline(always)] + pub fn is_ain4(&self) -> bool { + **self == MUXNEG_A::AIN4 + } + #[doc = "Checks if the value of the field is `AIN5`"] + #[inline(always)] + pub fn is_ain5(&self) -> bool { + **self == MUXNEG_A::AIN5 + } + #[doc = "Checks if the value of the field is `GND`"] + #[inline(always)] + pub fn is_gnd(&self) -> bool { + **self == MUXNEG_A::GND + } +} +impl core::ops::Deref for MUXNEG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MUXNEG` writer - Negative Mux Input Selection"] +pub struct MUXNEG_W<'a> { + w: &'a mut W, +} +impl<'a> MUXNEG_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MUXNEG_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "ADC AIN0 Pin"] + #[inline(always)] + pub fn ain0(self) -> &'a mut W { + self.variant(MUXNEG_A::AIN0) + } + #[doc = "ADC AIN1 Pin"] + #[inline(always)] + pub fn ain1(self) -> &'a mut W { + self.variant(MUXNEG_A::AIN1) + } + #[doc = "ADC AIN2 Pin"] + #[inline(always)] + pub fn ain2(self) -> &'a mut W { + self.variant(MUXNEG_A::AIN2) + } + #[doc = "ADC AIN3 Pin"] + #[inline(always)] + pub fn ain3(self) -> &'a mut W { + self.variant(MUXNEG_A::AIN3) + } + #[doc = "ADC AIN4 Pin"] + #[inline(always)] + pub fn ain4(self) -> &'a mut W { + self.variant(MUXNEG_A::AIN4) + } + #[doc = "ADC AIN5 Pin"] + #[inline(always)] + pub fn ain5(self) -> &'a mut W { + self.variant(MUXNEG_A::AIN5) + } + #[doc = "Internal Ground"] + #[inline(always)] + pub fn gnd(self) -> &'a mut W { + self.variant(MUXNEG_A::GND) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 8)) | ((value as u16 & 0x1f) << 8); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Positive Mux Input Selection"] + #[inline(always)] + pub fn muxpos(&self) -> MUXPOS_R { + MUXPOS_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 8:12 - Negative Mux Input Selection"] + #[inline(always)] + pub fn muxneg(&self) -> MUXNEG_R { + MUXNEG_R::new(((self.bits >> 8) & 0x1f) as u8) + } +} +impl W { + #[doc = "Bits 0:4 - Positive Mux Input Selection"] + #[inline(always)] + pub fn muxpos(&mut self) -> MUXPOS_W { + MUXPOS_W { w: self } + } + #[doc = "Bits 8:12 - Negative Mux Input Selection"] + #[inline(always)] + pub fn muxneg(&mut self) -> MUXNEG_W { + MUXNEG_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Input Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [inputctrl](index.html) module"] +pub struct INPUTCTRL_SPEC; +impl crate::RegisterSpec for INPUTCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [inputctrl::R](R) reader structure"] +impl crate::Readable for INPUTCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [inputctrl::W](W) writer structure"] +impl crate::Writable for INPUTCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INPUTCTRL to value 0"] +impl crate::Resettable for INPUTCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/adc0/intenclr.rs b/pac/atsamc21j/src/adc0/intenclr.rs new file mode 100644 index 000000000000..b10f428d30b1 --- /dev/null +++ b/pac/atsamc21j/src/adc0/intenclr.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RESRDY` reader - Result Ready Interrupt Disable"] +pub struct RESRDY_R(crate::FieldReader); +impl RESRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESRDY` writer - Result Ready Interrupt Disable"] +pub struct RESRDY_W<'a> { + w: &'a mut W, +} +impl<'a> RESRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `OVERRUN` reader - Overrun Interrupt Disable"] +pub struct OVERRUN_R(crate::FieldReader); +impl OVERRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVERRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVERRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVERRUN` writer - Overrun Interrupt Disable"] +pub struct OVERRUN_W<'a> { + w: &'a mut W, +} +impl<'a> OVERRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WINMON` reader - Window Monitor Interrupt Disable"] +pub struct WINMON_R(crate::FieldReader); +impl WINMON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINMON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINMON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMON` writer - Window Monitor Interrupt Disable"] +pub struct WINMON_W<'a> { + w: &'a mut W, +} +impl<'a> WINMON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Result Ready Interrupt Disable"] + #[inline(always)] + pub fn resrdy(&self) -> RESRDY_R { + RESRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Overrun Interrupt Disable"] + #[inline(always)] + pub fn overrun(&self) -> OVERRUN_R { + OVERRUN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Window Monitor Interrupt Disable"] + #[inline(always)] + pub fn winmon(&self) -> WINMON_R { + WINMON_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Result Ready Interrupt Disable"] + #[inline(always)] + pub fn resrdy(&mut self) -> RESRDY_W { + RESRDY_W { w: self } + } + #[doc = "Bit 1 - Overrun Interrupt Disable"] + #[inline(always)] + pub fn overrun(&mut self) -> OVERRUN_W { + OVERRUN_W { w: self } + } + #[doc = "Bit 2 - Window Monitor Interrupt Disable"] + #[inline(always)] + pub fn winmon(&mut self) -> WINMON_W { + WINMON_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/adc0/intenset.rs b/pac/atsamc21j/src/adc0/intenset.rs new file mode 100644 index 000000000000..5ca93b05b859 --- /dev/null +++ b/pac/atsamc21j/src/adc0/intenset.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RESRDY` reader - Result Ready Interrupt Enable"] +pub struct RESRDY_R(crate::FieldReader); +impl RESRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESRDY` writer - Result Ready Interrupt Enable"] +pub struct RESRDY_W<'a> { + w: &'a mut W, +} +impl<'a> RESRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `OVERRUN` reader - Overrun Interrupt Enable"] +pub struct OVERRUN_R(crate::FieldReader); +impl OVERRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVERRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVERRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVERRUN` writer - Overrun Interrupt Enable"] +pub struct OVERRUN_W<'a> { + w: &'a mut W, +} +impl<'a> OVERRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WINMON` reader - Window Monitor Interrupt Enable"] +pub struct WINMON_R(crate::FieldReader); +impl WINMON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINMON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINMON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMON` writer - Window Monitor Interrupt Enable"] +pub struct WINMON_W<'a> { + w: &'a mut W, +} +impl<'a> WINMON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Result Ready Interrupt Enable"] + #[inline(always)] + pub fn resrdy(&self) -> RESRDY_R { + RESRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Overrun Interrupt Enable"] + #[inline(always)] + pub fn overrun(&self) -> OVERRUN_R { + OVERRUN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Window Monitor Interrupt Enable"] + #[inline(always)] + pub fn winmon(&self) -> WINMON_R { + WINMON_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Result Ready Interrupt Enable"] + #[inline(always)] + pub fn resrdy(&mut self) -> RESRDY_W { + RESRDY_W { w: self } + } + #[doc = "Bit 1 - Overrun Interrupt Enable"] + #[inline(always)] + pub fn overrun(&mut self) -> OVERRUN_W { + OVERRUN_W { w: self } + } + #[doc = "Bit 2 - Window Monitor Interrupt Enable"] + #[inline(always)] + pub fn winmon(&mut self) -> WINMON_W { + WINMON_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/adc0/intflag.rs b/pac/atsamc21j/src/adc0/intflag.rs new file mode 100644 index 000000000000..3cd74788b226 --- /dev/null +++ b/pac/atsamc21j/src/adc0/intflag.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RESRDY` reader - Result Ready Interrupt Flag"] +pub struct RESRDY_R(crate::FieldReader); +impl RESRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESRDY` writer - Result Ready Interrupt Flag"] +pub struct RESRDY_W<'a> { + w: &'a mut W, +} +impl<'a> RESRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `OVERRUN` reader - Overrun Interrupt Flag"] +pub struct OVERRUN_R(crate::FieldReader); +impl OVERRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVERRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVERRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVERRUN` writer - Overrun Interrupt Flag"] +pub struct OVERRUN_W<'a> { + w: &'a mut W, +} +impl<'a> OVERRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WINMON` reader - Window Monitor Interrupt Flag"] +pub struct WINMON_R(crate::FieldReader); +impl WINMON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINMON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINMON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMON` writer - Window Monitor Interrupt Flag"] +pub struct WINMON_W<'a> { + w: &'a mut W, +} +impl<'a> WINMON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Result Ready Interrupt Flag"] + #[inline(always)] + pub fn resrdy(&self) -> RESRDY_R { + RESRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Overrun Interrupt Flag"] + #[inline(always)] + pub fn overrun(&self) -> OVERRUN_R { + OVERRUN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Window Monitor Interrupt Flag"] + #[inline(always)] + pub fn winmon(&self) -> WINMON_R { + WINMON_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Result Ready Interrupt Flag"] + #[inline(always)] + pub fn resrdy(&mut self) -> RESRDY_W { + RESRDY_W { w: self } + } + #[doc = "Bit 1 - Overrun Interrupt Flag"] + #[inline(always)] + pub fn overrun(&mut self) -> OVERRUN_W { + OVERRUN_W { w: self } + } + #[doc = "Bit 2 - Window Monitor Interrupt Flag"] + #[inline(always)] + pub fn winmon(&mut self) -> WINMON_W { + WINMON_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/adc0/offsetcorr.rs b/pac/atsamc21j/src/adc0/offsetcorr.rs new file mode 100644 index 000000000000..24a97427c64e --- /dev/null +++ b/pac/atsamc21j/src/adc0/offsetcorr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `OFFSETCORR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OFFSETCORR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OFFSETCORR` reader - Offset Correction Value"] +pub struct OFFSETCORR_R(crate::FieldReader); +impl OFFSETCORR_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + OFFSETCORR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OFFSETCORR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OFFSETCORR` writer - Offset Correction Value"] +pub struct OFFSETCORR_W<'a> { + w: &'a mut W, +} +impl<'a> OFFSETCORR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0fff) | (value as u16 & 0x0fff); + self.w + } +} +impl R { + #[doc = "Bits 0:11 - Offset Correction Value"] + #[inline(always)] + pub fn offsetcorr(&self) -> OFFSETCORR_R { + OFFSETCORR_R::new((self.bits & 0x0fff) as u16) + } +} +impl W { + #[doc = "Bits 0:11 - Offset Correction Value"] + #[inline(always)] + pub fn offsetcorr(&mut self) -> OFFSETCORR_W { + OFFSETCORR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Offset Correction\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [offsetcorr](index.html) module"] +pub struct OFFSETCORR_SPEC; +impl crate::RegisterSpec for OFFSETCORR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [offsetcorr::R](R) reader structure"] +impl crate::Readable for OFFSETCORR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [offsetcorr::W](W) writer structure"] +impl crate::Writable for OFFSETCORR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OFFSETCORR to value 0"] +impl crate::Resettable for OFFSETCORR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/adc0/refctrl.rs b/pac/atsamc21j/src/adc0/refctrl.rs new file mode 100644 index 000000000000..007d86e306bc --- /dev/null +++ b/pac/atsamc21j/src/adc0/refctrl.rs @@ -0,0 +1,251 @@ +#[doc = "Register `REFCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `REFCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Reference Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum REFSEL_A { + #[doc = "0: Internal Bandgap Reference"] + INTREF = 0, + #[doc = "1: 1/1.6 VDDANA"] + INTVCC0 = 1, + #[doc = "2: 1/2 VDDANA"] + INTVCC1 = 2, + #[doc = "3: External Reference"] + AREFA = 3, + #[doc = "4: DAC"] + DAC = 4, + #[doc = "5: VDDANA"] + INTVCC2 = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: REFSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `REFSEL` reader - Reference Selection"] +pub struct REFSEL_R(crate::FieldReader); +impl REFSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REFSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(REFSEL_A::INTREF), + 1 => Some(REFSEL_A::INTVCC0), + 2 => Some(REFSEL_A::INTVCC1), + 3 => Some(REFSEL_A::AREFA), + 4 => Some(REFSEL_A::DAC), + 5 => Some(REFSEL_A::INTVCC2), + _ => None, + } + } + #[doc = "Checks if the value of the field is `INTREF`"] + #[inline(always)] + pub fn is_intref(&self) -> bool { + **self == REFSEL_A::INTREF + } + #[doc = "Checks if the value of the field is `INTVCC0`"] + #[inline(always)] + pub fn is_intvcc0(&self) -> bool { + **self == REFSEL_A::INTVCC0 + } + #[doc = "Checks if the value of the field is `INTVCC1`"] + #[inline(always)] + pub fn is_intvcc1(&self) -> bool { + **self == REFSEL_A::INTVCC1 + } + #[doc = "Checks if the value of the field is `AREFA`"] + #[inline(always)] + pub fn is_arefa(&self) -> bool { + **self == REFSEL_A::AREFA + } + #[doc = "Checks if the value of the field is `DAC`"] + #[inline(always)] + pub fn is_dac(&self) -> bool { + **self == REFSEL_A::DAC + } + #[doc = "Checks if the value of the field is `INTVCC2`"] + #[inline(always)] + pub fn is_intvcc2(&self) -> bool { + **self == REFSEL_A::INTVCC2 + } +} +impl core::ops::Deref for REFSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REFSEL` writer - Reference Selection"] +pub struct REFSEL_W<'a> { + w: &'a mut W, +} +impl<'a> REFSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: REFSEL_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Internal Bandgap Reference"] + #[inline(always)] + pub fn intref(self) -> &'a mut W { + self.variant(REFSEL_A::INTREF) + } + #[doc = "1/1.6 VDDANA"] + #[inline(always)] + pub fn intvcc0(self) -> &'a mut W { + self.variant(REFSEL_A::INTVCC0) + } + #[doc = "1/2 VDDANA"] + #[inline(always)] + pub fn intvcc1(self) -> &'a mut W { + self.variant(REFSEL_A::INTVCC1) + } + #[doc = "External Reference"] + #[inline(always)] + pub fn arefa(self) -> &'a mut W { + self.variant(REFSEL_A::AREFA) + } + #[doc = "DAC"] + #[inline(always)] + pub fn dac(self) -> &'a mut W { + self.variant(REFSEL_A::DAC) + } + #[doc = "VDDANA"] + #[inline(always)] + pub fn intvcc2(self) -> &'a mut W { + self.variant(REFSEL_A::INTVCC2) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +#[doc = "Field `REFCOMP` reader - Reference Buffer Offset Compensation Enable"] +pub struct REFCOMP_R(crate::FieldReader); +impl REFCOMP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + REFCOMP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REFCOMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REFCOMP` writer - Reference Buffer Offset Compensation Enable"] +pub struct REFCOMP_W<'a> { + w: &'a mut W, +} +impl<'a> REFCOMP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Reference Selection"] + #[inline(always)] + pub fn refsel(&self) -> REFSEL_R { + REFSEL_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 7 - Reference Buffer Offset Compensation Enable"] + #[inline(always)] + pub fn refcomp(&self) -> REFCOMP_R { + REFCOMP_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Reference Selection"] + #[inline(always)] + pub fn refsel(&mut self) -> REFSEL_W { + REFSEL_W { w: self } + } + #[doc = "Bit 7 - Reference Buffer Offset Compensation Enable"] + #[inline(always)] + pub fn refcomp(&mut self) -> REFCOMP_W { + REFCOMP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Reference Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [refctrl](index.html) module"] +pub struct REFCTRL_SPEC; +impl crate::RegisterSpec for REFCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [refctrl::R](R) reader structure"] +impl crate::Readable for REFCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [refctrl::W](W) writer structure"] +impl crate::Writable for REFCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets REFCTRL to value 0"] +impl crate::Resettable for REFCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/adc0/result.rs b/pac/atsamc21j/src/adc0/result.rs new file mode 100644 index 000000000000..b63b08cc72b9 --- /dev/null +++ b/pac/atsamc21j/src/adc0/result.rs @@ -0,0 +1,53 @@ +#[doc = "Register `RESULT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `RESULT` reader - Result Value"] +pub struct RESULT_R(crate::FieldReader); +impl RESULT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + RESULT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESULT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:15 - Result Value"] + #[inline(always)] + pub fn result(&self) -> RESULT_R { + RESULT_R::new(self.bits as u16) + } +} +#[doc = "Result\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [result](index.html) module"] +pub struct RESULT_SPEC; +impl crate::RegisterSpec for RESULT_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [result::R](R) reader structure"] +impl crate::Readable for RESULT_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets RESULT to value 0"] +impl crate::Resettable for RESULT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/adc0/sampctrl.rs b/pac/atsamc21j/src/adc0/sampctrl.rs new file mode 100644 index 000000000000..be4b77a80410 --- /dev/null +++ b/pac/atsamc21j/src/adc0/sampctrl.rs @@ -0,0 +1,150 @@ +#[doc = "Register `SAMPCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SAMPCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SAMPLEN` reader - Sampling Time Length"] +pub struct SAMPLEN_R(crate::FieldReader); +impl SAMPLEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SAMPLEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SAMPLEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SAMPLEN` writer - Sampling Time Length"] +pub struct SAMPLEN_W<'a> { + w: &'a mut W, +} +impl<'a> SAMPLEN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u8 & 0x3f); + self.w + } +} +#[doc = "Field `OFFCOMP` reader - Comparator Offset Compensation Enable"] +pub struct OFFCOMP_R(crate::FieldReader); +impl OFFCOMP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OFFCOMP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OFFCOMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OFFCOMP` writer - Comparator Offset Compensation Enable"] +pub struct OFFCOMP_W<'a> { + w: &'a mut W, +} +impl<'a> OFFCOMP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Sampling Time Length"] + #[inline(always)] + pub fn samplen(&self) -> SAMPLEN_R { + SAMPLEN_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 7 - Comparator Offset Compensation Enable"] + #[inline(always)] + pub fn offcomp(&self) -> OFFCOMP_R { + OFFCOMP_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:5 - Sampling Time Length"] + #[inline(always)] + pub fn samplen(&mut self) -> SAMPLEN_W { + SAMPLEN_W { w: self } + } + #[doc = "Bit 7 - Comparator Offset Compensation Enable"] + #[inline(always)] + pub fn offcomp(&mut self) -> OFFCOMP_W { + OFFCOMP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Sample Time Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sampctrl](index.html) module"] +pub struct SAMPCTRL_SPEC; +impl crate::RegisterSpec for SAMPCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [sampctrl::R](R) reader structure"] +impl crate::Readable for SAMPCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [sampctrl::W](W) writer structure"] +impl crate::Writable for SAMPCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SAMPCTRL to value 0"] +impl crate::Resettable for SAMPCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/adc0/seqctrl.rs b/pac/atsamc21j/src/adc0/seqctrl.rs new file mode 100644 index 000000000000..c8388c9a393f --- /dev/null +++ b/pac/atsamc21j/src/adc0/seqctrl.rs @@ -0,0 +1,103 @@ +#[doc = "Register `SEQCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SEQCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SEQEN` reader - Enable Positive Input in the Sequence"] +pub struct SEQEN_R(crate::FieldReader); +impl SEQEN_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + SEQEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEQEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEQEN` writer - Enable Positive Input in the Sequence"] +pub struct SEQEN_W<'a> { + w: &'a mut W, +} +impl<'a> SEQEN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Enable Positive Input in the Sequence"] + #[inline(always)] + pub fn seqen(&self) -> SEQEN_R { + SEQEN_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Enable Positive Input in the Sequence"] + #[inline(always)] + pub fn seqen(&mut self) -> SEQEN_W { + SEQEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Sequence Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [seqctrl](index.html) module"] +pub struct SEQCTRL_SPEC; +impl crate::RegisterSpec for SEQCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [seqctrl::R](R) reader structure"] +impl crate::Readable for SEQCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [seqctrl::W](W) writer structure"] +impl crate::Writable for SEQCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SEQCTRL to value 0"] +impl crate::Resettable for SEQCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/adc0/seqstatus.rs b/pac/atsamc21j/src/adc0/seqstatus.rs new file mode 100644 index 000000000000..42c820892e9a --- /dev/null +++ b/pac/atsamc21j/src/adc0/seqstatus.rs @@ -0,0 +1,73 @@ +#[doc = "Register `SEQSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SEQSTATE` reader - Sequence State"] +pub struct SEQSTATE_R(crate::FieldReader); +impl SEQSTATE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SEQSTATE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEQSTATE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEQBUSY` reader - Sequence Busy"] +pub struct SEQBUSY_R(crate::FieldReader); +impl SEQBUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SEQBUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEQBUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:4 - Sequence State"] + #[inline(always)] + pub fn seqstate(&self) -> SEQSTATE_R { + SEQSTATE_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bit 7 - Sequence Busy"] + #[inline(always)] + pub fn seqbusy(&self) -> SEQBUSY_R { + SEQBUSY_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +#[doc = "Sequence Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [seqstatus](index.html) module"] +pub struct SEQSTATUS_SPEC; +impl crate::RegisterSpec for SEQSTATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [seqstatus::R](R) reader structure"] +impl crate::Readable for SEQSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SEQSTATUS to value 0"] +impl crate::Resettable for SEQSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/adc0/swtrig.rs b/pac/atsamc21j/src/adc0/swtrig.rs new file mode 100644 index 000000000000..5e23ed7865ed --- /dev/null +++ b/pac/atsamc21j/src/adc0/swtrig.rs @@ -0,0 +1,160 @@ +#[doc = "Register `SWTRIG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SWTRIG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FLUSH` reader - ADC Flush"] +pub struct FLUSH_R(crate::FieldReader); +impl FLUSH_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FLUSH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FLUSH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLUSH` writer - ADC Flush"] +pub struct FLUSH_W<'a> { + w: &'a mut W, +} +impl<'a> FLUSH_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `START` reader - Start ADC Conversion"] +pub struct START_R(crate::FieldReader); +impl START_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + START_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for START_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `START` writer - Start ADC Conversion"] +pub struct START_W<'a> { + w: &'a mut W, +} +impl<'a> START_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - ADC Flush"] + #[inline(always)] + pub fn flush(&self) -> FLUSH_R { + FLUSH_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Start ADC Conversion"] + #[inline(always)] + pub fn start(&self) -> START_R { + START_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - ADC Flush"] + #[inline(always)] + pub fn flush(&mut self) -> FLUSH_W { + FLUSH_W { w: self } + } + #[doc = "Bit 1 - Start ADC Conversion"] + #[inline(always)] + pub fn start(&mut self) -> START_W { + START_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Software Trigger\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [swtrig](index.html) module"] +pub struct SWTRIG_SPEC; +impl crate::RegisterSpec for SWTRIG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [swtrig::R](R) reader structure"] +impl crate::Readable for SWTRIG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [swtrig::W](W) writer structure"] +impl crate::Writable for SWTRIG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SWTRIG to value 0"] +impl crate::Resettable for SWTRIG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/adc0/syncbusy.rs b/pac/atsamc21j/src/adc0/syncbusy.rs new file mode 100644 index 000000000000..9c92da8a7c74 --- /dev/null +++ b/pac/atsamc21j/src/adc0/syncbusy.rs @@ -0,0 +1,253 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - SWRST Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - ENABLE Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INPUTCTRL` reader - INPUTCTRL Synchronization Busy"] +pub struct INPUTCTRL_R(crate::FieldReader); +impl INPUTCTRL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INPUTCTRL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INPUTCTRL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLC` reader - CTRLC Synchronization Busy"] +pub struct CTRLC_R(crate::FieldReader); +impl CTRLC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AVGCTRL` reader - AVGCTRL Synchronization Busy"] +pub struct AVGCTRL_R(crate::FieldReader); +impl AVGCTRL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AVGCTRL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AVGCTRL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SAMPCTRL` reader - SAMPCTRL Synchronization Busy"] +pub struct SAMPCTRL_R(crate::FieldReader); +impl SAMPCTRL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SAMPCTRL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SAMPCTRL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINLT` reader - WINLT Synchronization Busy"] +pub struct WINLT_R(crate::FieldReader); +impl WINLT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINLT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINLT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINUT` reader - WINUT Synchronization Busy"] +pub struct WINUT_R(crate::FieldReader); +impl WINUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GAINCORR` reader - GAINCORR Synchronization Busy"] +pub struct GAINCORR_R(crate::FieldReader); +impl GAINCORR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GAINCORR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GAINCORR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OFFSETCORR` reader - OFFSETCTRL Synchronization Busy"] +pub struct OFFSETCORR_R(crate::FieldReader); +impl OFFSETCORR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OFFSETCORR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OFFSETCORR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG` reader - SWTRG Synchronization Busy"] +pub struct SWTRIG_R(crate::FieldReader); +impl SWTRIG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - SWRST Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ENABLE Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - INPUTCTRL Synchronization Busy"] + #[inline(always)] + pub fn inputctrl(&self) -> INPUTCTRL_R { + INPUTCTRL_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - CTRLC Synchronization Busy"] + #[inline(always)] + pub fn ctrlc(&self) -> CTRLC_R { + CTRLC_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - AVGCTRL Synchronization Busy"] + #[inline(always)] + pub fn avgctrl(&self) -> AVGCTRL_R { + AVGCTRL_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - SAMPCTRL Synchronization Busy"] + #[inline(always)] + pub fn sampctrl(&self) -> SAMPCTRL_R { + SAMPCTRL_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - WINLT Synchronization Busy"] + #[inline(always)] + pub fn winlt(&self) -> WINLT_R { + WINLT_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - WINUT Synchronization Busy"] + #[inline(always)] + pub fn winut(&self) -> WINUT_R { + WINUT_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - GAINCORR Synchronization Busy"] + #[inline(always)] + pub fn gaincorr(&self) -> GAINCORR_R { + GAINCORR_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - OFFSETCTRL Synchronization Busy"] + #[inline(always)] + pub fn offsetcorr(&self) -> OFFSETCORR_R { + OFFSETCORR_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - SWTRG Synchronization Busy"] + #[inline(always)] + pub fn swtrig(&self) -> SWTRIG_R { + SWTRIG_R::new(((self.bits >> 10) & 0x01) != 0) + } +} +#[doc = "Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/adc0/winlt.rs b/pac/atsamc21j/src/adc0/winlt.rs new file mode 100644 index 000000000000..2a3397684767 --- /dev/null +++ b/pac/atsamc21j/src/adc0/winlt.rs @@ -0,0 +1,103 @@ +#[doc = "Register `WINLT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WINLT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WINLT` reader - Window Lower Threshold"] +pub struct WINLT_R(crate::FieldReader); +impl WINLT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + WINLT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINLT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINLT` writer - Window Lower Threshold"] +pub struct WINLT_W<'a> { + w: &'a mut W, +} +impl<'a> WINLT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Window Lower Threshold"] + #[inline(always)] + pub fn winlt(&self) -> WINLT_R { + WINLT_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Window Lower Threshold"] + #[inline(always)] + pub fn winlt(&mut self) -> WINLT_W { + WINLT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Window Monitor Lower Threshold\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [winlt](index.html) module"] +pub struct WINLT_SPEC; +impl crate::RegisterSpec for WINLT_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [winlt::R](R) reader structure"] +impl crate::Readable for WINLT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [winlt::W](W) writer structure"] +impl crate::Writable for WINLT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WINLT to value 0"] +impl crate::Resettable for WINLT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/adc0/winut.rs b/pac/atsamc21j/src/adc0/winut.rs new file mode 100644 index 000000000000..0ea123174937 --- /dev/null +++ b/pac/atsamc21j/src/adc0/winut.rs @@ -0,0 +1,103 @@ +#[doc = "Register `WINUT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WINUT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WINUT` reader - Window Upper Threshold"] +pub struct WINUT_R(crate::FieldReader); +impl WINUT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + WINUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINUT` writer - Window Upper Threshold"] +pub struct WINUT_W<'a> { + w: &'a mut W, +} +impl<'a> WINUT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Window Upper Threshold"] + #[inline(always)] + pub fn winut(&self) -> WINUT_R { + WINUT_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Window Upper Threshold"] + #[inline(always)] + pub fn winut(&mut self) -> WINUT_W { + WINUT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Window Monitor Upper Threshold\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [winut](index.html) module"] +pub struct WINUT_SPEC; +impl crate::RegisterSpec for WINUT_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [winut::R](R) reader structure"] +impl crate::Readable for WINUT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [winut::W](W) writer structure"] +impl crate::Writable for WINUT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WINUT to value 0"] +impl crate::Resettable for WINUT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/can0.rs b/pac/atsamc21j/src/can0.rs new file mode 100644 index 000000000000..96ccd4c5970c --- /dev/null +++ b/pac/atsamc21j/src/can0.rs @@ -0,0 +1,291 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Core Release"] + pub crel: crate::Reg, + #[doc = "0x04 - Endian"] + pub endn: crate::Reg, + #[doc = "0x08 - Message RAM Configuration"] + pub mrcfg: crate::Reg, + #[doc = "0x0c - Fast Bit Timing and Prescaler"] + pub dbtp: crate::Reg, + #[doc = "0x10 - Test"] + pub test: crate::Reg, + #[doc = "0x14 - RAM Watchdog"] + pub rwd: crate::Reg, + #[doc = "0x18 - CC Control"] + pub cccr: crate::Reg, + #[doc = "0x1c - Nominal Bit Timing and Prescaler"] + pub nbtp: crate::Reg, + #[doc = "0x20 - Timestamp Counter Configuration"] + pub tscc: crate::Reg, + #[doc = "0x24 - Timestamp Counter Value"] + pub tscv: crate::Reg, + #[doc = "0x28 - Timeout Counter Configuration"] + pub tocc: crate::Reg, + #[doc = "0x2c - Timeout Counter Value"] + pub tocv: crate::Reg, + _reserved12: [u8; 0x10], + #[doc = "0x40 - Error Counter"] + pub ecr: crate::Reg, + #[doc = "0x44 - Protocol Status"] + pub psr: crate::Reg, + #[doc = "0x48 - Extended ID Filter Configuration"] + pub tdcr: crate::Reg, + _reserved15: [u8; 0x04], + #[doc = "0x50 - Interrupt"] + pub ir: crate::Reg, + #[doc = "0x54 - Interrupt Enable"] + pub ie: crate::Reg, + #[doc = "0x58 - Interrupt Line Select"] + pub ils: crate::Reg, + #[doc = "0x5c - Interrupt Line Enable"] + pub ile: crate::Reg, + _reserved19: [u8; 0x20], + #[doc = "0x80 - Global Filter Configuration"] + pub gfc: crate::Reg, + #[doc = "0x84 - Standard ID Filter Configuration"] + pub sidfc: crate::Reg, + #[doc = "0x88 - Extended ID Filter Configuration"] + pub xidfc: crate::Reg, + _reserved22: [u8; 0x04], + #[doc = "0x90 - Extended ID AND Mask"] + pub xidam: crate::Reg, + #[doc = "0x94 - High Priority Message Status"] + pub hpms: crate::Reg, + #[doc = "0x98 - New Data 1"] + pub ndat1: crate::Reg, + #[doc = "0x9c - New Data 2"] + pub ndat2: crate::Reg, + #[doc = "0xa0 - Rx FIFO 0 Configuration"] + pub rxf0c: crate::Reg, + #[doc = "0xa4 - Rx FIFO 0 Status"] + pub rxf0s: crate::Reg, + #[doc = "0xa8 - Rx FIFO 0 Acknowledge"] + pub rxf0a: crate::Reg, + #[doc = "0xac - Rx Buffer Configuration"] + pub rxbc: crate::Reg, + #[doc = "0xb0 - Rx FIFO 1 Configuration"] + pub rxf1c: crate::Reg, + #[doc = "0xb4 - Rx FIFO 1 Status"] + pub rxf1s: crate::Reg, + #[doc = "0xb8 - Rx FIFO 1 Acknowledge"] + pub rxf1a: crate::Reg, + #[doc = "0xbc - Rx Buffer / FIFO Element Size Configuration"] + pub rxesc: crate::Reg, + #[doc = "0xc0 - Tx Buffer Configuration"] + pub txbc: crate::Reg, + #[doc = "0xc4 - Tx FIFO / Queue Status"] + pub txfqs: crate::Reg, + #[doc = "0xc8 - Tx Buffer Element Size Configuration"] + pub txesc: crate::Reg, + #[doc = "0xcc - Tx Buffer Request Pending"] + pub txbrp: crate::Reg, + #[doc = "0xd0 - Tx Buffer Add Request"] + pub txbar: crate::Reg, + #[doc = "0xd4 - Tx Buffer Cancellation Request"] + pub txbcr: crate::Reg, + #[doc = "0xd8 - Tx Buffer Transmission Occurred"] + pub txbto: crate::Reg, + #[doc = "0xdc - Tx Buffer Cancellation Finished"] + pub txbcf: crate::Reg, + #[doc = "0xe0 - Tx Buffer Transmission Interrupt Enable"] + pub txbtie: crate::Reg, + #[doc = "0xe4 - Tx Buffer Cancellation Finished Interrupt Enable"] + pub txbcie: crate::Reg, + _reserved44: [u8; 0x08], + #[doc = "0xf0 - Tx Event FIFO Configuration"] + pub txefc: crate::Reg, + #[doc = "0xf4 - Tx Event FIFO Status"] + pub txefs: crate::Reg, + #[doc = "0xf8 - Tx Event FIFO Acknowledge"] + pub txefa: crate::Reg, +} +#[doc = "CREL register accessor: an alias for `Reg`"] +pub type CREL = crate::Reg; +#[doc = "Core Release"] +pub mod crel; +#[doc = "ENDN register accessor: an alias for `Reg`"] +pub type ENDN = crate::Reg; +#[doc = "Endian"] +pub mod endn; +#[doc = "MRCFG register accessor: an alias for `Reg`"] +pub type MRCFG = crate::Reg; +#[doc = "Message RAM Configuration"] +pub mod mrcfg; +#[doc = "DBTP register accessor: an alias for `Reg`"] +pub type DBTP = crate::Reg; +#[doc = "Fast Bit Timing and Prescaler"] +pub mod dbtp; +#[doc = "TEST register accessor: an alias for `Reg`"] +pub type TEST = crate::Reg; +#[doc = "Test"] +pub mod test; +#[doc = "RWD register accessor: an alias for `Reg`"] +pub type RWD = crate::Reg; +#[doc = "RAM Watchdog"] +pub mod rwd; +#[doc = "CCCR register accessor: an alias for `Reg`"] +pub type CCCR = crate::Reg; +#[doc = "CC Control"] +pub mod cccr; +#[doc = "NBTP register accessor: an alias for `Reg`"] +pub type NBTP = crate::Reg; +#[doc = "Nominal Bit Timing and Prescaler"] +pub mod nbtp; +#[doc = "TSCC register accessor: an alias for `Reg`"] +pub type TSCC = crate::Reg; +#[doc = "Timestamp Counter Configuration"] +pub mod tscc; +#[doc = "TSCV register accessor: an alias for `Reg`"] +pub type TSCV = crate::Reg; +#[doc = "Timestamp Counter Value"] +pub mod tscv; +#[doc = "TOCC register accessor: an alias for `Reg`"] +pub type TOCC = crate::Reg; +#[doc = "Timeout Counter Configuration"] +pub mod tocc; +#[doc = "TOCV register accessor: an alias for `Reg`"] +pub type TOCV = crate::Reg; +#[doc = "Timeout Counter Value"] +pub mod tocv; +#[doc = "ECR register accessor: an alias for `Reg`"] +pub type ECR = crate::Reg; +#[doc = "Error Counter"] +pub mod ecr; +#[doc = "PSR register accessor: an alias for `Reg`"] +pub type PSR = crate::Reg; +#[doc = "Protocol Status"] +pub mod psr; +#[doc = "TDCR register accessor: an alias for `Reg`"] +pub type TDCR = crate::Reg; +#[doc = "Extended ID Filter Configuration"] +pub mod tdcr; +#[doc = "IR register accessor: an alias for `Reg`"] +pub type IR = crate::Reg; +#[doc = "Interrupt"] +pub mod ir; +#[doc = "IE register accessor: an alias for `Reg`"] +pub type IE = crate::Reg; +#[doc = "Interrupt Enable"] +pub mod ie; +#[doc = "ILS register accessor: an alias for `Reg`"] +pub type ILS = crate::Reg; +#[doc = "Interrupt Line Select"] +pub mod ils; +#[doc = "ILE register accessor: an alias for `Reg`"] +pub type ILE = crate::Reg; +#[doc = "Interrupt Line Enable"] +pub mod ile; +#[doc = "GFC register accessor: an alias for `Reg`"] +pub type GFC = crate::Reg; +#[doc = "Global Filter Configuration"] +pub mod gfc; +#[doc = "SIDFC register accessor: an alias for `Reg`"] +pub type SIDFC = crate::Reg; +#[doc = "Standard ID Filter Configuration"] +pub mod sidfc; +#[doc = "XIDFC register accessor: an alias for `Reg`"] +pub type XIDFC = crate::Reg; +#[doc = "Extended ID Filter Configuration"] +pub mod xidfc; +#[doc = "XIDAM register accessor: an alias for `Reg`"] +pub type XIDAM = crate::Reg; +#[doc = "Extended ID AND Mask"] +pub mod xidam; +#[doc = "HPMS register accessor: an alias for `Reg`"] +pub type HPMS = crate::Reg; +#[doc = "High Priority Message Status"] +pub mod hpms; +#[doc = "NDAT1 register accessor: an alias for `Reg`"] +pub type NDAT1 = crate::Reg; +#[doc = "New Data 1"] +pub mod ndat1; +#[doc = "NDAT2 register accessor: an alias for `Reg`"] +pub type NDAT2 = crate::Reg; +#[doc = "New Data 2"] +pub mod ndat2; +#[doc = "RXF0C register accessor: an alias for `Reg`"] +pub type RXF0C = crate::Reg; +#[doc = "Rx FIFO 0 Configuration"] +pub mod rxf0c; +#[doc = "RXF0S register accessor: an alias for `Reg`"] +pub type RXF0S = crate::Reg; +#[doc = "Rx FIFO 0 Status"] +pub mod rxf0s; +#[doc = "RXF0A register accessor: an alias for `Reg`"] +pub type RXF0A = crate::Reg; +#[doc = "Rx FIFO 0 Acknowledge"] +pub mod rxf0a; +#[doc = "RXBC register accessor: an alias for `Reg`"] +pub type RXBC = crate::Reg; +#[doc = "Rx Buffer Configuration"] +pub mod rxbc; +#[doc = "RXF1C register accessor: an alias for `Reg`"] +pub type RXF1C = crate::Reg; +#[doc = "Rx FIFO 1 Configuration"] +pub mod rxf1c; +#[doc = "RXF1S register accessor: an alias for `Reg`"] +pub type RXF1S = crate::Reg; +#[doc = "Rx FIFO 1 Status"] +pub mod rxf1s; +#[doc = "RXF1A register accessor: an alias for `Reg`"] +pub type RXF1A = crate::Reg; +#[doc = "Rx FIFO 1 Acknowledge"] +pub mod rxf1a; +#[doc = "RXESC register accessor: an alias for `Reg`"] +pub type RXESC = crate::Reg; +#[doc = "Rx Buffer / FIFO Element Size Configuration"] +pub mod rxesc; +#[doc = "TXBC register accessor: an alias for `Reg`"] +pub type TXBC = crate::Reg; +#[doc = "Tx Buffer Configuration"] +pub mod txbc; +#[doc = "TXFQS register accessor: an alias for `Reg`"] +pub type TXFQS = crate::Reg; +#[doc = "Tx FIFO / Queue Status"] +pub mod txfqs; +#[doc = "TXESC register accessor: an alias for `Reg`"] +pub type TXESC = crate::Reg; +#[doc = "Tx Buffer Element Size Configuration"] +pub mod txesc; +#[doc = "TXBRP register accessor: an alias for `Reg`"] +pub type TXBRP = crate::Reg; +#[doc = "Tx Buffer Request Pending"] +pub mod txbrp; +#[doc = "TXBAR register accessor: an alias for `Reg`"] +pub type TXBAR = crate::Reg; +#[doc = "Tx Buffer Add Request"] +pub mod txbar; +#[doc = "TXBCR register accessor: an alias for `Reg`"] +pub type TXBCR = crate::Reg; +#[doc = "Tx Buffer Cancellation Request"] +pub mod txbcr; +#[doc = "TXBTO register accessor: an alias for `Reg`"] +pub type TXBTO = crate::Reg; +#[doc = "Tx Buffer Transmission Occurred"] +pub mod txbto; +#[doc = "TXBCF register accessor: an alias for `Reg`"] +pub type TXBCF = crate::Reg; +#[doc = "Tx Buffer Cancellation Finished"] +pub mod txbcf; +#[doc = "TXBTIE register accessor: an alias for `Reg`"] +pub type TXBTIE = crate::Reg; +#[doc = "Tx Buffer Transmission Interrupt Enable"] +pub mod txbtie; +#[doc = "TXBCIE register accessor: an alias for `Reg`"] +pub type TXBCIE = crate::Reg; +#[doc = "Tx Buffer Cancellation Finished Interrupt Enable"] +pub mod txbcie; +#[doc = "TXEFC register accessor: an alias for `Reg`"] +pub type TXEFC = crate::Reg; +#[doc = "Tx Event FIFO Configuration"] +pub mod txefc; +#[doc = "TXEFS register accessor: an alias for `Reg`"] +pub type TXEFS = crate::Reg; +#[doc = "Tx Event FIFO Status"] +pub mod txefs; +#[doc = "TXEFA register accessor: an alias for `Reg`"] +pub type TXEFA = crate::Reg; +#[doc = "Tx Event FIFO Acknowledge"] +pub mod txefa; diff --git a/pac/atsamc21j/src/can0/cccr.rs b/pac/atsamc21j/src/can0/cccr.rs new file mode 100644 index 000000000000..c2ff17d123cf --- /dev/null +++ b/pac/atsamc21j/src/can0/cccr.rs @@ -0,0 +1,724 @@ +#[doc = "Register `CCCR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CCCR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INIT` reader - Initialization"] +pub struct INIT_R(crate::FieldReader); +impl INIT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INIT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INIT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INIT` writer - Initialization"] +pub struct INIT_W<'a> { + w: &'a mut W, +} +impl<'a> INIT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `CCE` reader - Configuration Change Enable"] +pub struct CCE_R(crate::FieldReader); +impl CCE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCE` writer - Configuration Change Enable"] +pub struct CCE_W<'a> { + w: &'a mut W, +} +impl<'a> CCE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ASM` reader - ASM Restricted Operation Mode"] +pub struct ASM_R(crate::FieldReader); +impl ASM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ASM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ASM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ASM` writer - ASM Restricted Operation Mode"] +pub struct ASM_W<'a> { + w: &'a mut W, +} +impl<'a> ASM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CSA` reader - Clock Stop Acknowledge"] +pub struct CSA_R(crate::FieldReader); +impl CSA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CSA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CSA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CSA` writer - Clock Stop Acknowledge"] +pub struct CSA_W<'a> { + w: &'a mut W, +} +impl<'a> CSA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CSR` reader - Clock Stop Request"] +pub struct CSR_R(crate::FieldReader); +impl CSR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CSR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CSR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CSR` writer - Clock Stop Request"] +pub struct CSR_W<'a> { + w: &'a mut W, +} +impl<'a> CSR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MON` reader - Bus Monitoring Mode"] +pub struct MON_R(crate::FieldReader); +impl MON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MON` writer - Bus Monitoring Mode"] +pub struct MON_W<'a> { + w: &'a mut W, +} +impl<'a> MON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `DAR` reader - Disable Automatic Retransmission"] +pub struct DAR_R(crate::FieldReader); +impl DAR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DAR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DAR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DAR` writer - Disable Automatic Retransmission"] +pub struct DAR_W<'a> { + w: &'a mut W, +} +impl<'a> DAR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `TEST` reader - Test Mode Enable"] +pub struct TEST_R(crate::FieldReader); +impl TEST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TEST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TEST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TEST` writer - Test Mode Enable"] +pub struct TEST_W<'a> { + w: &'a mut W, +} +impl<'a> TEST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `FDOE` reader - FD Operation Enable"] +pub struct FDOE_R(crate::FieldReader); +impl FDOE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FDOE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FDOE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FDOE` writer - FD Operation Enable"] +pub struct FDOE_W<'a> { + w: &'a mut W, +} +impl<'a> FDOE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `BRSE` reader - Bit Rate Switch Enable"] +pub struct BRSE_R(crate::FieldReader); +impl BRSE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BRSE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BRSE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BRSE` writer - Bit Rate Switch Enable"] +pub struct BRSE_W<'a> { + w: &'a mut W, +} +impl<'a> BRSE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `PXHD` reader - Protocol Exception Handling Disable"] +pub struct PXHD_R(crate::FieldReader); +impl PXHD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PXHD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PXHD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PXHD` writer - Protocol Exception Handling Disable"] +pub struct PXHD_W<'a> { + w: &'a mut W, +} +impl<'a> PXHD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `EFBI` reader - Edge Filtering during Bus Integration"] +pub struct EFBI_R(crate::FieldReader); +impl EFBI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EFBI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EFBI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EFBI` writer - Edge Filtering during Bus Integration"] +pub struct EFBI_W<'a> { + w: &'a mut W, +} +impl<'a> EFBI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `TXP` reader - Transmit Pause"] +pub struct TXP_R(crate::FieldReader); +impl TXP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXP` writer - Transmit Pause"] +pub struct TXP_W<'a> { + w: &'a mut W, +} +impl<'a> TXP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `NISO` reader - Non ISO Operation"] +pub struct NISO_R(crate::FieldReader); +impl NISO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NISO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NISO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NISO` writer - Non ISO Operation"] +pub struct NISO_W<'a> { + w: &'a mut W, +} +impl<'a> NISO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Initialization"] + #[inline(always)] + pub fn init(&self) -> INIT_R { + INIT_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Configuration Change Enable"] + #[inline(always)] + pub fn cce(&self) -> CCE_R { + CCE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - ASM Restricted Operation Mode"] + #[inline(always)] + pub fn asm(&self) -> ASM_R { + ASM_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Clock Stop Acknowledge"] + #[inline(always)] + pub fn csa(&self) -> CSA_R { + CSA_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Clock Stop Request"] + #[inline(always)] + pub fn csr(&self) -> CSR_R { + CSR_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Bus Monitoring Mode"] + #[inline(always)] + pub fn mon(&self) -> MON_R { + MON_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Disable Automatic Retransmission"] + #[inline(always)] + pub fn dar(&self) -> DAR_R { + DAR_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Test Mode Enable"] + #[inline(always)] + pub fn test(&self) -> TEST_R { + TEST_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - FD Operation Enable"] + #[inline(always)] + pub fn fdoe(&self) -> FDOE_R { + FDOE_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Bit Rate Switch Enable"] + #[inline(always)] + pub fn brse(&self) -> BRSE_R { + BRSE_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 12 - Protocol Exception Handling Disable"] + #[inline(always)] + pub fn pxhd(&self) -> PXHD_R { + PXHD_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Edge Filtering during Bus Integration"] + #[inline(always)] + pub fn efbi(&self) -> EFBI_R { + EFBI_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Transmit Pause"] + #[inline(always)] + pub fn txp(&self) -> TXP_R { + TXP_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Non ISO Operation"] + #[inline(always)] + pub fn niso(&self) -> NISO_R { + NISO_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Initialization"] + #[inline(always)] + pub fn init(&mut self) -> INIT_W { + INIT_W { w: self } + } + #[doc = "Bit 1 - Configuration Change Enable"] + #[inline(always)] + pub fn cce(&mut self) -> CCE_W { + CCE_W { w: self } + } + #[doc = "Bit 2 - ASM Restricted Operation Mode"] + #[inline(always)] + pub fn asm(&mut self) -> ASM_W { + ASM_W { w: self } + } + #[doc = "Bit 3 - Clock Stop Acknowledge"] + #[inline(always)] + pub fn csa(&mut self) -> CSA_W { + CSA_W { w: self } + } + #[doc = "Bit 4 - Clock Stop Request"] + #[inline(always)] + pub fn csr(&mut self) -> CSR_W { + CSR_W { w: self } + } + #[doc = "Bit 5 - Bus Monitoring Mode"] + #[inline(always)] + pub fn mon(&mut self) -> MON_W { + MON_W { w: self } + } + #[doc = "Bit 6 - Disable Automatic Retransmission"] + #[inline(always)] + pub fn dar(&mut self) -> DAR_W { + DAR_W { w: self } + } + #[doc = "Bit 7 - Test Mode Enable"] + #[inline(always)] + pub fn test(&mut self) -> TEST_W { + TEST_W { w: self } + } + #[doc = "Bit 8 - FD Operation Enable"] + #[inline(always)] + pub fn fdoe(&mut self) -> FDOE_W { + FDOE_W { w: self } + } + #[doc = "Bit 9 - Bit Rate Switch Enable"] + #[inline(always)] + pub fn brse(&mut self) -> BRSE_W { + BRSE_W { w: self } + } + #[doc = "Bit 12 - Protocol Exception Handling Disable"] + #[inline(always)] + pub fn pxhd(&mut self) -> PXHD_W { + PXHD_W { w: self } + } + #[doc = "Bit 13 - Edge Filtering during Bus Integration"] + #[inline(always)] + pub fn efbi(&mut self) -> EFBI_W { + EFBI_W { w: self } + } + #[doc = "Bit 14 - Transmit Pause"] + #[inline(always)] + pub fn txp(&mut self) -> TXP_W { + TXP_W { w: self } + } + #[doc = "Bit 15 - Non ISO Operation"] + #[inline(always)] + pub fn niso(&mut self) -> NISO_W { + NISO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CC Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cccr](index.html) module"] +pub struct CCCR_SPEC; +impl crate::RegisterSpec for CCCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cccr::R](R) reader structure"] +impl crate::Readable for CCCR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cccr::W](W) writer structure"] +impl crate::Writable for CCCR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CCCR to value 0x01"] +impl crate::Resettable for CCCR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pac/atsamc21j/src/can0/crel.rs b/pac/atsamc21j/src/can0/crel.rs new file mode 100644 index 000000000000..4e9dcdbf5f03 --- /dev/null +++ b/pac/atsamc21j/src/can0/crel.rs @@ -0,0 +1,93 @@ +#[doc = "Register `CREL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SUBSTEP` reader - Sub-step of Core Release"] +pub struct SUBSTEP_R(crate::FieldReader); +impl SUBSTEP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SUBSTEP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SUBSTEP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STEP` reader - Step of Core Release"] +pub struct STEP_R(crate::FieldReader); +impl STEP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + STEP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STEP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REL` reader - Core Release"] +pub struct REL_R(crate::FieldReader); +impl REL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 20:23 - Sub-step of Core Release"] + #[inline(always)] + pub fn substep(&self) -> SUBSTEP_R { + SUBSTEP_R::new(((self.bits >> 20) & 0x0f) as u8) + } + #[doc = "Bits 24:27 - Step of Core Release"] + #[inline(always)] + pub fn step(&self) -> STEP_R { + STEP_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bits 28:31 - Core Release"] + #[inline(always)] + pub fn rel(&self) -> REL_R { + REL_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +#[doc = "Core Release\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [crel](index.html) module"] +pub struct CREL_SPEC; +impl crate::RegisterSpec for CREL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [crel::R](R) reader structure"] +impl crate::Readable for CREL_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CREL to value 0x3210_0000"] +impl crate::Resettable for CREL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x3210_0000 + } +} diff --git a/pac/atsamc21j/src/can0/dbtp.rs b/pac/atsamc21j/src/can0/dbtp.rs new file mode 100644 index 000000000000..5c1d2bc7ccdd --- /dev/null +++ b/pac/atsamc21j/src/can0/dbtp.rs @@ -0,0 +1,261 @@ +#[doc = "Register `DBTP` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBTP` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DSJW` reader - Data (Re)Synchronization Jump Width"] +pub struct DSJW_R(crate::FieldReader); +impl DSJW_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DSJW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DSJW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DSJW` writer - Data (Re)Synchronization Jump Width"] +pub struct DSJW_W<'a> { + w: &'a mut W, +} +impl<'a> DSJW_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Field `DTSEG2` reader - Data time segment after sample point"] +pub struct DTSEG2_R(crate::FieldReader); +impl DTSEG2_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DTSEG2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DTSEG2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DTSEG2` writer - Data time segment after sample point"] +pub struct DTSEG2_W<'a> { + w: &'a mut W, +} +impl<'a> DTSEG2_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 4)) | ((value as u32 & 0x0f) << 4); + self.w + } +} +#[doc = "Field `DTSEG1` reader - Data time segment before sample point"] +pub struct DTSEG1_R(crate::FieldReader); +impl DTSEG1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DTSEG1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DTSEG1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DTSEG1` writer - Data time segment before sample point"] +pub struct DTSEG1_W<'a> { + w: &'a mut W, +} +impl<'a> DTSEG1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 8)) | ((value as u32 & 0x1f) << 8); + self.w + } +} +#[doc = "Field `DBRP` reader - Data Baud Rate Prescaler"] +pub struct DBRP_R(crate::FieldReader); +impl DBRP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DBRP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBRP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBRP` writer - Data Baud Rate Prescaler"] +pub struct DBRP_W<'a> { + w: &'a mut W, +} +impl<'a> DBRP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 16)) | ((value as u32 & 0x1f) << 16); + self.w + } +} +#[doc = "Field `TDC` reader - Tranceiver Delay Compensation"] +pub struct TDC_R(crate::FieldReader); +impl TDC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TDC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TDC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TDC` writer - Tranceiver Delay Compensation"] +pub struct TDC_W<'a> { + w: &'a mut W, +} +impl<'a> TDC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Data (Re)Synchronization Jump Width"] + #[inline(always)] + pub fn dsjw(&self) -> DSJW_R { + DSJW_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Data time segment after sample point"] + #[inline(always)] + pub fn dtseg2(&self) -> DTSEG2_R { + DTSEG2_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 8:12 - Data time segment before sample point"] + #[inline(always)] + pub fn dtseg1(&self) -> DTSEG1_R { + DTSEG1_R::new(((self.bits >> 8) & 0x1f) as u8) + } + #[doc = "Bits 16:20 - Data Baud Rate Prescaler"] + #[inline(always)] + pub fn dbrp(&self) -> DBRP_R { + DBRP_R::new(((self.bits >> 16) & 0x1f) as u8) + } + #[doc = "Bit 23 - Tranceiver Delay Compensation"] + #[inline(always)] + pub fn tdc(&self) -> TDC_R { + TDC_R::new(((self.bits >> 23) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Data (Re)Synchronization Jump Width"] + #[inline(always)] + pub fn dsjw(&mut self) -> DSJW_W { + DSJW_W { w: self } + } + #[doc = "Bits 4:7 - Data time segment after sample point"] + #[inline(always)] + pub fn dtseg2(&mut self) -> DTSEG2_W { + DTSEG2_W { w: self } + } + #[doc = "Bits 8:12 - Data time segment before sample point"] + #[inline(always)] + pub fn dtseg1(&mut self) -> DTSEG1_W { + DTSEG1_W { w: self } + } + #[doc = "Bits 16:20 - Data Baud Rate Prescaler"] + #[inline(always)] + pub fn dbrp(&mut self) -> DBRP_W { + DBRP_W { w: self } + } + #[doc = "Bit 23 - Tranceiver Delay Compensation"] + #[inline(always)] + pub fn tdc(&mut self) -> TDC_W { + TDC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Fast Bit Timing and Prescaler\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbtp](index.html) module"] +pub struct DBTP_SPEC; +impl crate::RegisterSpec for DBTP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dbtp::R](R) reader structure"] +impl crate::Readable for DBTP_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbtp::W](W) writer structure"] +impl crate::Writable for DBTP_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBTP to value 0x0a33"] +impl crate::Resettable for DBTP_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0a33 + } +} diff --git a/pac/atsamc21j/src/can0/ecr.rs b/pac/atsamc21j/src/can0/ecr.rs new file mode 100644 index 000000000000..044085d7706d --- /dev/null +++ b/pac/atsamc21j/src/can0/ecr.rs @@ -0,0 +1,113 @@ +#[doc = "Register `ECR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `TEC` reader - Transmit Error Counter"] +pub struct TEC_R(crate::FieldReader); +impl TEC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TEC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TEC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REC` reader - Receive Error Counter"] +pub struct REC_R(crate::FieldReader); +impl REC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RP` reader - Receive Error Passive"] +pub struct RP_R(crate::FieldReader); +impl RP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CEL` reader - CAN Error Logging"] +pub struct CEL_R(crate::FieldReader); +impl CEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:7 - Transmit Error Counter"] + #[inline(always)] + pub fn tec(&self) -> TEC_R { + TEC_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:14 - Receive Error Counter"] + #[inline(always)] + pub fn rec(&self) -> REC_R { + REC_R::new(((self.bits >> 8) & 0x7f) as u8) + } + #[doc = "Bit 15 - Receive Error Passive"] + #[inline(always)] + pub fn rp(&self) -> RP_R { + RP_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:23 - CAN Error Logging"] + #[inline(always)] + pub fn cel(&self) -> CEL_R { + CEL_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +#[doc = "Error Counter\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ecr](index.html) module"] +pub struct ECR_SPEC; +impl crate::RegisterSpec for ECR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ecr::R](R) reader structure"] +impl crate::Readable for ECR_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets ECR to value 0"] +impl crate::Resettable for ECR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/can0/endn.rs b/pac/atsamc21j/src/can0/endn.rs new file mode 100644 index 000000000000..9628fa2a3f48 --- /dev/null +++ b/pac/atsamc21j/src/can0/endn.rs @@ -0,0 +1,53 @@ +#[doc = "Register `ENDN` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `ETV` reader - Endianness Test Value"] +pub struct ETV_R(crate::FieldReader); +impl ETV_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + ETV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ETV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - Endianness Test Value"] + #[inline(always)] + pub fn etv(&self) -> ETV_R { + ETV_R::new(self.bits as u32) + } +} +#[doc = "Endian\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [endn](index.html) module"] +pub struct ENDN_SPEC; +impl crate::RegisterSpec for ENDN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [endn::R](R) reader structure"] +impl crate::Readable for ENDN_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets ENDN to value 0x8765_4321"] +impl crate::Resettable for ENDN_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x8765_4321 + } +} diff --git a/pac/atsamc21j/src/can0/gfc.rs b/pac/atsamc21j/src/can0/gfc.rs new file mode 100644 index 000000000000..a9e7a8cc9f62 --- /dev/null +++ b/pac/atsamc21j/src/can0/gfc.rs @@ -0,0 +1,358 @@ +#[doc = "Register `GFC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GFC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RRFE` reader - Reject Remote Frames Extended"] +pub struct RRFE_R(crate::FieldReader); +impl RRFE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RRFE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RRFE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RRFE` writer - Reject Remote Frames Extended"] +pub struct RRFE_W<'a> { + w: &'a mut W, +} +impl<'a> RRFE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `RRFS` reader - Reject Remote Frames Standard"] +pub struct RRFS_R(crate::FieldReader); +impl RRFS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RRFS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RRFS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RRFS` writer - Reject Remote Frames Standard"] +pub struct RRFS_W<'a> { + w: &'a mut W, +} +impl<'a> RRFS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Accept Non-matching Frames Extended\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum ANFE_A { + #[doc = "0: Accept in Rx FIFO 0"] + RXF0 = 0, + #[doc = "1: Accept in Rx FIFO 1"] + RXF1 = 1, + #[doc = "2: Reject"] + REJECT = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: ANFE_A) -> Self { + variant as _ + } +} +#[doc = "Field `ANFE` reader - Accept Non-matching Frames Extended"] +pub struct ANFE_R(crate::FieldReader); +impl ANFE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ANFE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(ANFE_A::RXF0), + 1 => Some(ANFE_A::RXF1), + 2 => Some(ANFE_A::REJECT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `RXF0`"] + #[inline(always)] + pub fn is_rxf0(&self) -> bool { + **self == ANFE_A::RXF0 + } + #[doc = "Checks if the value of the field is `RXF1`"] + #[inline(always)] + pub fn is_rxf1(&self) -> bool { + **self == ANFE_A::RXF1 + } + #[doc = "Checks if the value of the field is `REJECT`"] + #[inline(always)] + pub fn is_reject(&self) -> bool { + **self == ANFE_A::REJECT + } +} +impl core::ops::Deref for ANFE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ANFE` writer - Accept Non-matching Frames Extended"] +pub struct ANFE_W<'a> { + w: &'a mut W, +} +impl<'a> ANFE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: ANFE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Accept in Rx FIFO 0"] + #[inline(always)] + pub fn rxf0(self) -> &'a mut W { + self.variant(ANFE_A::RXF0) + } + #[doc = "Accept in Rx FIFO 1"] + #[inline(always)] + pub fn rxf1(self) -> &'a mut W { + self.variant(ANFE_A::RXF1) + } + #[doc = "Reject"] + #[inline(always)] + pub fn reject(self) -> &'a mut W { + self.variant(ANFE_A::REJECT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u32 & 0x03) << 2); + self.w + } +} +#[doc = "Accept Non-matching Frames Standard\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum ANFS_A { + #[doc = "0: Accept in Rx FIFO 0"] + RXF0 = 0, + #[doc = "1: Accept in Rx FIFO 1"] + RXF1 = 1, + #[doc = "2: Reject"] + REJECT = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: ANFS_A) -> Self { + variant as _ + } +} +#[doc = "Field `ANFS` reader - Accept Non-matching Frames Standard"] +pub struct ANFS_R(crate::FieldReader); +impl ANFS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ANFS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(ANFS_A::RXF0), + 1 => Some(ANFS_A::RXF1), + 2 => Some(ANFS_A::REJECT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `RXF0`"] + #[inline(always)] + pub fn is_rxf0(&self) -> bool { + **self == ANFS_A::RXF0 + } + #[doc = "Checks if the value of the field is `RXF1`"] + #[inline(always)] + pub fn is_rxf1(&self) -> bool { + **self == ANFS_A::RXF1 + } + #[doc = "Checks if the value of the field is `REJECT`"] + #[inline(always)] + pub fn is_reject(&self) -> bool { + **self == ANFS_A::REJECT + } +} +impl core::ops::Deref for ANFS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ANFS` writer - Accept Non-matching Frames Standard"] +pub struct ANFS_W<'a> { + w: &'a mut W, +} +impl<'a> ANFS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: ANFS_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Accept in Rx FIFO 0"] + #[inline(always)] + pub fn rxf0(self) -> &'a mut W { + self.variant(ANFS_A::RXF0) + } + #[doc = "Accept in Rx FIFO 1"] + #[inline(always)] + pub fn rxf1(self) -> &'a mut W { + self.variant(ANFS_A::RXF1) + } + #[doc = "Reject"] + #[inline(always)] + pub fn reject(self) -> &'a mut W { + self.variant(ANFS_A::REJECT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u32 & 0x03) << 4); + self.w + } +} +impl R { + #[doc = "Bit 0 - Reject Remote Frames Extended"] + #[inline(always)] + pub fn rrfe(&self) -> RRFE_R { + RRFE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Reject Remote Frames Standard"] + #[inline(always)] + pub fn rrfs(&self) -> RRFS_R { + RRFS_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:3 - Accept Non-matching Frames Extended"] + #[inline(always)] + pub fn anfe(&self) -> ANFE_R { + ANFE_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bits 4:5 - Accept Non-matching Frames Standard"] + #[inline(always)] + pub fn anfs(&self) -> ANFS_R { + ANFS_R::new(((self.bits >> 4) & 0x03) as u8) + } +} +impl W { + #[doc = "Bit 0 - Reject Remote Frames Extended"] + #[inline(always)] + pub fn rrfe(&mut self) -> RRFE_W { + RRFE_W { w: self } + } + #[doc = "Bit 1 - Reject Remote Frames Standard"] + #[inline(always)] + pub fn rrfs(&mut self) -> RRFS_W { + RRFS_W { w: self } + } + #[doc = "Bits 2:3 - Accept Non-matching Frames Extended"] + #[inline(always)] + pub fn anfe(&mut self) -> ANFE_W { + ANFE_W { w: self } + } + #[doc = "Bits 4:5 - Accept Non-matching Frames Standard"] + #[inline(always)] + pub fn anfs(&mut self) -> ANFS_W { + ANFS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Global Filter Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gfc](index.html) module"] +pub struct GFC_SPEC; +impl crate::RegisterSpec for GFC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gfc::R](R) reader structure"] +impl crate::Readable for GFC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gfc::W](W) writer structure"] +impl crate::Writable for GFC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets GFC to value 0"] +impl crate::Resettable for GFC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/can0/hpms.rs b/pac/atsamc21j/src/can0/hpms.rs new file mode 100644 index 000000000000..ff26a312fb47 --- /dev/null +++ b/pac/atsamc21j/src/can0/hpms.rs @@ -0,0 +1,163 @@ +#[doc = "Register `HPMS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `BIDX` reader - Buffer Index"] +pub struct BIDX_R(crate::FieldReader); +impl BIDX_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BIDX_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BIDX_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Message Storage Indicator\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MSI_A { + #[doc = "0: No FIFO selected"] + NONE = 0, + #[doc = "1: FIFO message lost"] + LOST = 1, + #[doc = "2: Message stored in FIFO 0"] + FIFO0 = 2, + #[doc = "3: Message stored in FIFO 1"] + FIFO1 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MSI_A) -> Self { + variant as _ + } +} +#[doc = "Field `MSI` reader - Message Storage Indicator"] +pub struct MSI_R(crate::FieldReader); +impl MSI_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MSI_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> MSI_A { + match self.bits { + 0 => MSI_A::NONE, + 1 => MSI_A::LOST, + 2 => MSI_A::FIFO0, + 3 => MSI_A::FIFO1, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == MSI_A::NONE + } + #[doc = "Checks if the value of the field is `LOST`"] + #[inline(always)] + pub fn is_lost(&self) -> bool { + **self == MSI_A::LOST + } + #[doc = "Checks if the value of the field is `FIFO0`"] + #[inline(always)] + pub fn is_fifo0(&self) -> bool { + **self == MSI_A::FIFO0 + } + #[doc = "Checks if the value of the field is `FIFO1`"] + #[inline(always)] + pub fn is_fifo1(&self) -> bool { + **self == MSI_A::FIFO1 + } +} +impl core::ops::Deref for MSI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FIDX` reader - Filter Index"] +pub struct FIDX_R(crate::FieldReader); +impl FIDX_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FIDX_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FIDX_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLST` reader - Filter List"] +pub struct FLST_R(crate::FieldReader); +impl FLST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FLST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FLST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:5 - Buffer Index"] + #[inline(always)] + pub fn bidx(&self) -> BIDX_R { + BIDX_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:7 - Message Storage Indicator"] + #[inline(always)] + pub fn msi(&self) -> MSI_R { + MSI_R::new(((self.bits >> 6) & 0x03) as u8) + } + #[doc = "Bits 8:14 - Filter Index"] + #[inline(always)] + pub fn fidx(&self) -> FIDX_R { + FIDX_R::new(((self.bits >> 8) & 0x7f) as u8) + } + #[doc = "Bit 15 - Filter List"] + #[inline(always)] + pub fn flst(&self) -> FLST_R { + FLST_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +#[doc = "High Priority Message Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hpms](index.html) module"] +pub struct HPMS_SPEC; +impl crate::RegisterSpec for HPMS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [hpms::R](R) reader structure"] +impl crate::Readable for HPMS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets HPMS to value 0"] +impl crate::Resettable for HPMS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/can0/ie.rs b/pac/atsamc21j/src/can0/ie.rs new file mode 100644 index 000000000000..c773ba115329 --- /dev/null +++ b/pac/atsamc21j/src/can0/ie.rs @@ -0,0 +1,1476 @@ +#[doc = "Register `IE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `IE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RF0NE` reader - Rx FIFO 0 New Message Interrupt Enable"] +pub struct RF0NE_R(crate::FieldReader); +impl RF0NE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF0NE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF0NE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF0NE` writer - Rx FIFO 0 New Message Interrupt Enable"] +pub struct RF0NE_W<'a> { + w: &'a mut W, +} +impl<'a> RF0NE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `RF0WE` reader - Rx FIFO 0 Watermark Reached Interrupt Enable"] +pub struct RF0WE_R(crate::FieldReader); +impl RF0WE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF0WE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF0WE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF0WE` writer - Rx FIFO 0 Watermark Reached Interrupt Enable"] +pub struct RF0WE_W<'a> { + w: &'a mut W, +} +impl<'a> RF0WE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RF0FE` reader - Rx FIFO 0 Full Interrupt Enable"] +pub struct RF0FE_R(crate::FieldReader); +impl RF0FE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF0FE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF0FE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF0FE` writer - Rx FIFO 0 Full Interrupt Enable"] +pub struct RF0FE_W<'a> { + w: &'a mut W, +} +impl<'a> RF0FE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RF0LE` reader - Rx FIFO 0 Message Lost Interrupt Enable"] +pub struct RF0LE_R(crate::FieldReader); +impl RF0LE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF0LE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF0LE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF0LE` writer - Rx FIFO 0 Message Lost Interrupt Enable"] +pub struct RF0LE_W<'a> { + w: &'a mut W, +} +impl<'a> RF0LE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `RF1NE` reader - Rx FIFO 1 New Message Interrupt Enable"] +pub struct RF1NE_R(crate::FieldReader); +impl RF1NE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF1NE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF1NE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF1NE` writer - Rx FIFO 1 New Message Interrupt Enable"] +pub struct RF1NE_W<'a> { + w: &'a mut W, +} +impl<'a> RF1NE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RF1WE` reader - Rx FIFO 1 Watermark Reached Interrupt Enable"] +pub struct RF1WE_R(crate::FieldReader); +impl RF1WE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF1WE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF1WE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF1WE` writer - Rx FIFO 1 Watermark Reached Interrupt Enable"] +pub struct RF1WE_W<'a> { + w: &'a mut W, +} +impl<'a> RF1WE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `RF1FE` reader - Rx FIFO 1 FIFO Full Interrupt Enable"] +pub struct RF1FE_R(crate::FieldReader); +impl RF1FE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF1FE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF1FE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF1FE` writer - Rx FIFO 1 FIFO Full Interrupt Enable"] +pub struct RF1FE_W<'a> { + w: &'a mut W, +} +impl<'a> RF1FE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `RF1LE` reader - Rx FIFO 1 Message Lost Interrupt Enable"] +pub struct RF1LE_R(crate::FieldReader); +impl RF1LE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF1LE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF1LE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF1LE` writer - Rx FIFO 1 Message Lost Interrupt Enable"] +pub struct RF1LE_W<'a> { + w: &'a mut W, +} +impl<'a> RF1LE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `HPME` reader - High Priority Message Interrupt Enable"] +pub struct HPME_R(crate::FieldReader); +impl HPME_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HPME_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HPME_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HPME` writer - High Priority Message Interrupt Enable"] +pub struct HPME_W<'a> { + w: &'a mut W, +} +impl<'a> HPME_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `TCE` reader - Timestamp Completed Interrupt Enable"] +pub struct TCE_R(crate::FieldReader); +impl TCE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCE` writer - Timestamp Completed Interrupt Enable"] +pub struct TCE_W<'a> { + w: &'a mut W, +} +impl<'a> TCE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `TCFE` reader - Transmission Cancellation Finished Interrupt Enable"] +pub struct TCFE_R(crate::FieldReader); +impl TCFE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCFE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCFE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCFE` writer - Transmission Cancellation Finished Interrupt Enable"] +pub struct TCFE_W<'a> { + w: &'a mut W, +} +impl<'a> TCFE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `TFEE` reader - Tx FIFO Empty Interrupt Enable"] +pub struct TFEE_R(crate::FieldReader); +impl TFEE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TFEE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TFEE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TFEE` writer - Tx FIFO Empty Interrupt Enable"] +pub struct TFEE_W<'a> { + w: &'a mut W, +} +impl<'a> TFEE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `TEFNE` reader - Tx Event FIFO New Entry Interrupt Enable"] +pub struct TEFNE_R(crate::FieldReader); +impl TEFNE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TEFNE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TEFNE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TEFNE` writer - Tx Event FIFO New Entry Interrupt Enable"] +pub struct TEFNE_W<'a> { + w: &'a mut W, +} +impl<'a> TEFNE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `TEFWE` reader - Tx Event FIFO Watermark Reached Interrupt Enable"] +pub struct TEFWE_R(crate::FieldReader); +impl TEFWE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TEFWE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TEFWE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TEFWE` writer - Tx Event FIFO Watermark Reached Interrupt Enable"] +pub struct TEFWE_W<'a> { + w: &'a mut W, +} +impl<'a> TEFWE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `TEFFE` reader - Tx Event FIFO Full Interrupt Enable"] +pub struct TEFFE_R(crate::FieldReader); +impl TEFFE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TEFFE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TEFFE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TEFFE` writer - Tx Event FIFO Full Interrupt Enable"] +pub struct TEFFE_W<'a> { + w: &'a mut W, +} +impl<'a> TEFFE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `TEFLE` reader - Tx Event FIFO Element Lost Interrupt Enable"] +pub struct TEFLE_R(crate::FieldReader); +impl TEFLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TEFLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TEFLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TEFLE` writer - Tx Event FIFO Element Lost Interrupt Enable"] +pub struct TEFLE_W<'a> { + w: &'a mut W, +} +impl<'a> TEFLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `TSWE` reader - Timestamp Wraparound Interrupt Enable"] +pub struct TSWE_R(crate::FieldReader); +impl TSWE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSWE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSWE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSWE` writer - Timestamp Wraparound Interrupt Enable"] +pub struct TSWE_W<'a> { + w: &'a mut W, +} +impl<'a> TSWE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `MRAFE` reader - Message RAM Access Failure Interrupt Enable"] +pub struct MRAFE_R(crate::FieldReader); +impl MRAFE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MRAFE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MRAFE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MRAFE` writer - Message RAM Access Failure Interrupt Enable"] +pub struct MRAFE_W<'a> { + w: &'a mut W, +} +impl<'a> MRAFE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `TOOE` reader - Timeout Occurred Interrupt Enable"] +pub struct TOOE_R(crate::FieldReader); +impl TOOE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TOOE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TOOE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TOOE` writer - Timeout Occurred Interrupt Enable"] +pub struct TOOE_W<'a> { + w: &'a mut W, +} +impl<'a> TOOE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `DRXE` reader - Message stored to Dedicated Rx Buffer Interrupt Enable"] +pub struct DRXE_R(crate::FieldReader); +impl DRXE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRXE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRXE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRXE` writer - Message stored to Dedicated Rx Buffer Interrupt Enable"] +pub struct DRXE_W<'a> { + w: &'a mut W, +} +impl<'a> DRXE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `BECE` reader - Bit Error Corrected Interrupt Enable"] +pub struct BECE_R(crate::FieldReader); +impl BECE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BECE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BECE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BECE` writer - Bit Error Corrected Interrupt Enable"] +pub struct BECE_W<'a> { + w: &'a mut W, +} +impl<'a> BECE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `BEUE` reader - Bit Error Uncorrected Interrupt Enable"] +pub struct BEUE_R(crate::FieldReader); +impl BEUE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BEUE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BEUE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BEUE` writer - Bit Error Uncorrected Interrupt Enable"] +pub struct BEUE_W<'a> { + w: &'a mut W, +} +impl<'a> BEUE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `ELOE` reader - Error Logging Overflow Interrupt Enable"] +pub struct ELOE_R(crate::FieldReader); +impl ELOE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ELOE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ELOE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ELOE` writer - Error Logging Overflow Interrupt Enable"] +pub struct ELOE_W<'a> { + w: &'a mut W, +} +impl<'a> ELOE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `EPE` reader - Error Passive Interrupt Enable"] +pub struct EPE_R(crate::FieldReader); +impl EPE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EPE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EPE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EPE` writer - Error Passive Interrupt Enable"] +pub struct EPE_W<'a> { + w: &'a mut W, +} +impl<'a> EPE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `EWE` reader - Warning Status Interrupt Enable"] +pub struct EWE_R(crate::FieldReader); +impl EWE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EWE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EWE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EWE` writer - Warning Status Interrupt Enable"] +pub struct EWE_W<'a> { + w: &'a mut W, +} +impl<'a> EWE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `BOE` reader - Bus_Off Status Interrupt Enable"] +pub struct BOE_R(crate::FieldReader); +impl BOE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BOE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BOE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BOE` writer - Bus_Off Status Interrupt Enable"] +pub struct BOE_W<'a> { + w: &'a mut W, +} +impl<'a> BOE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `WDIE` reader - Watchdog Interrupt Interrupt Enable"] +pub struct WDIE_R(crate::FieldReader); +impl WDIE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WDIE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WDIE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WDIE` writer - Watchdog Interrupt Interrupt Enable"] +pub struct WDIE_W<'a> { + w: &'a mut W, +} +impl<'a> WDIE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `PEAE` reader - Protocol Error in Arbitration Phase Enable"] +pub struct PEAE_R(crate::FieldReader); +impl PEAE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEAE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEAE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEAE` writer - Protocol Error in Arbitration Phase Enable"] +pub struct PEAE_W<'a> { + w: &'a mut W, +} +impl<'a> PEAE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +#[doc = "Field `PEDE` reader - Protocol Error in Data Phase Enable"] +pub struct PEDE_R(crate::FieldReader); +impl PEDE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEDE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEDE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEDE` writer - Protocol Error in Data Phase Enable"] +pub struct PEDE_W<'a> { + w: &'a mut W, +} +impl<'a> PEDE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Field `ARAE` reader - Access to Reserved Address Enable"] +pub struct ARAE_R(crate::FieldReader); +impl ARAE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ARAE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ARAE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ARAE` writer - Access to Reserved Address Enable"] +pub struct ARAE_W<'a> { + w: &'a mut W, +} +impl<'a> ARAE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29); + self.w + } +} +impl R { + #[doc = "Bit 0 - Rx FIFO 0 New Message Interrupt Enable"] + #[inline(always)] + pub fn rf0ne(&self) -> RF0NE_R { + RF0NE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Rx FIFO 0 Watermark Reached Interrupt Enable"] + #[inline(always)] + pub fn rf0we(&self) -> RF0WE_R { + RF0WE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Rx FIFO 0 Full Interrupt Enable"] + #[inline(always)] + pub fn rf0fe(&self) -> RF0FE_R { + RF0FE_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Rx FIFO 0 Message Lost Interrupt Enable"] + #[inline(always)] + pub fn rf0le(&self) -> RF0LE_R { + RF0LE_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Rx FIFO 1 New Message Interrupt Enable"] + #[inline(always)] + pub fn rf1ne(&self) -> RF1NE_R { + RF1NE_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Rx FIFO 1 Watermark Reached Interrupt Enable"] + #[inline(always)] + pub fn rf1we(&self) -> RF1WE_R { + RF1WE_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Rx FIFO 1 FIFO Full Interrupt Enable"] + #[inline(always)] + pub fn rf1fe(&self) -> RF1FE_R { + RF1FE_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Rx FIFO 1 Message Lost Interrupt Enable"] + #[inline(always)] + pub fn rf1le(&self) -> RF1LE_R { + RF1LE_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - High Priority Message Interrupt Enable"] + #[inline(always)] + pub fn hpme(&self) -> HPME_R { + HPME_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Timestamp Completed Interrupt Enable"] + #[inline(always)] + pub fn tce(&self) -> TCE_R { + TCE_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Transmission Cancellation Finished Interrupt Enable"] + #[inline(always)] + pub fn tcfe(&self) -> TCFE_R { + TCFE_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Tx FIFO Empty Interrupt Enable"] + #[inline(always)] + pub fn tfee(&self) -> TFEE_R { + TFEE_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Tx Event FIFO New Entry Interrupt Enable"] + #[inline(always)] + pub fn tefne(&self) -> TEFNE_R { + TEFNE_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Tx Event FIFO Watermark Reached Interrupt Enable"] + #[inline(always)] + pub fn tefwe(&self) -> TEFWE_R { + TEFWE_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Tx Event FIFO Full Interrupt Enable"] + #[inline(always)] + pub fn teffe(&self) -> TEFFE_R { + TEFFE_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Tx Event FIFO Element Lost Interrupt Enable"] + #[inline(always)] + pub fn tefle(&self) -> TEFLE_R { + TEFLE_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Timestamp Wraparound Interrupt Enable"] + #[inline(always)] + pub fn tswe(&self) -> TSWE_R { + TSWE_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Message RAM Access Failure Interrupt Enable"] + #[inline(always)] + pub fn mrafe(&self) -> MRAFE_R { + MRAFE_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Timeout Occurred Interrupt Enable"] + #[inline(always)] + pub fn tooe(&self) -> TOOE_R { + TOOE_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Message stored to Dedicated Rx Buffer Interrupt Enable"] + #[inline(always)] + pub fn drxe(&self) -> DRXE_R { + DRXE_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Bit Error Corrected Interrupt Enable"] + #[inline(always)] + pub fn bece(&self) -> BECE_R { + BECE_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Bit Error Uncorrected Interrupt Enable"] + #[inline(always)] + pub fn beue(&self) -> BEUE_R { + BEUE_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Error Logging Overflow Interrupt Enable"] + #[inline(always)] + pub fn eloe(&self) -> ELOE_R { + ELOE_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Error Passive Interrupt Enable"] + #[inline(always)] + pub fn epe(&self) -> EPE_R { + EPE_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24 - Warning Status Interrupt Enable"] + #[inline(always)] + pub fn ewe(&self) -> EWE_R { + EWE_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Bus_Off Status Interrupt Enable"] + #[inline(always)] + pub fn boe(&self) -> BOE_R { + BOE_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Watchdog Interrupt Interrupt Enable"] + #[inline(always)] + pub fn wdie(&self) -> WDIE_R { + WDIE_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Protocol Error in Arbitration Phase Enable"] + #[inline(always)] + pub fn peae(&self) -> PEAE_R { + PEAE_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28 - Protocol Error in Data Phase Enable"] + #[inline(always)] + pub fn pede(&self) -> PEDE_R { + PEDE_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Access to Reserved Address Enable"] + #[inline(always)] + pub fn arae(&self) -> ARAE_R { + ARAE_R::new(((self.bits >> 29) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Rx FIFO 0 New Message Interrupt Enable"] + #[inline(always)] + pub fn rf0ne(&mut self) -> RF0NE_W { + RF0NE_W { w: self } + } + #[doc = "Bit 1 - Rx FIFO 0 Watermark Reached Interrupt Enable"] + #[inline(always)] + pub fn rf0we(&mut self) -> RF0WE_W { + RF0WE_W { w: self } + } + #[doc = "Bit 2 - Rx FIFO 0 Full Interrupt Enable"] + #[inline(always)] + pub fn rf0fe(&mut self) -> RF0FE_W { + RF0FE_W { w: self } + } + #[doc = "Bit 3 - Rx FIFO 0 Message Lost Interrupt Enable"] + #[inline(always)] + pub fn rf0le(&mut self) -> RF0LE_W { + RF0LE_W { w: self } + } + #[doc = "Bit 4 - Rx FIFO 1 New Message Interrupt Enable"] + #[inline(always)] + pub fn rf1ne(&mut self) -> RF1NE_W { + RF1NE_W { w: self } + } + #[doc = "Bit 5 - Rx FIFO 1 Watermark Reached Interrupt Enable"] + #[inline(always)] + pub fn rf1we(&mut self) -> RF1WE_W { + RF1WE_W { w: self } + } + #[doc = "Bit 6 - Rx FIFO 1 FIFO Full Interrupt Enable"] + #[inline(always)] + pub fn rf1fe(&mut self) -> RF1FE_W { + RF1FE_W { w: self } + } + #[doc = "Bit 7 - Rx FIFO 1 Message Lost Interrupt Enable"] + #[inline(always)] + pub fn rf1le(&mut self) -> RF1LE_W { + RF1LE_W { w: self } + } + #[doc = "Bit 8 - High Priority Message Interrupt Enable"] + #[inline(always)] + pub fn hpme(&mut self) -> HPME_W { + HPME_W { w: self } + } + #[doc = "Bit 9 - Timestamp Completed Interrupt Enable"] + #[inline(always)] + pub fn tce(&mut self) -> TCE_W { + TCE_W { w: self } + } + #[doc = "Bit 10 - Transmission Cancellation Finished Interrupt Enable"] + #[inline(always)] + pub fn tcfe(&mut self) -> TCFE_W { + TCFE_W { w: self } + } + #[doc = "Bit 11 - Tx FIFO Empty Interrupt Enable"] + #[inline(always)] + pub fn tfee(&mut self) -> TFEE_W { + TFEE_W { w: self } + } + #[doc = "Bit 12 - Tx Event FIFO New Entry Interrupt Enable"] + #[inline(always)] + pub fn tefne(&mut self) -> TEFNE_W { + TEFNE_W { w: self } + } + #[doc = "Bit 13 - Tx Event FIFO Watermark Reached Interrupt Enable"] + #[inline(always)] + pub fn tefwe(&mut self) -> TEFWE_W { + TEFWE_W { w: self } + } + #[doc = "Bit 14 - Tx Event FIFO Full Interrupt Enable"] + #[inline(always)] + pub fn teffe(&mut self) -> TEFFE_W { + TEFFE_W { w: self } + } + #[doc = "Bit 15 - Tx Event FIFO Element Lost Interrupt Enable"] + #[inline(always)] + pub fn tefle(&mut self) -> TEFLE_W { + TEFLE_W { w: self } + } + #[doc = "Bit 16 - Timestamp Wraparound Interrupt Enable"] + #[inline(always)] + pub fn tswe(&mut self) -> TSWE_W { + TSWE_W { w: self } + } + #[doc = "Bit 17 - Message RAM Access Failure Interrupt Enable"] + #[inline(always)] + pub fn mrafe(&mut self) -> MRAFE_W { + MRAFE_W { w: self } + } + #[doc = "Bit 18 - Timeout Occurred Interrupt Enable"] + #[inline(always)] + pub fn tooe(&mut self) -> TOOE_W { + TOOE_W { w: self } + } + #[doc = "Bit 19 - Message stored to Dedicated Rx Buffer Interrupt Enable"] + #[inline(always)] + pub fn drxe(&mut self) -> DRXE_W { + DRXE_W { w: self } + } + #[doc = "Bit 20 - Bit Error Corrected Interrupt Enable"] + #[inline(always)] + pub fn bece(&mut self) -> BECE_W { + BECE_W { w: self } + } + #[doc = "Bit 21 - Bit Error Uncorrected Interrupt Enable"] + #[inline(always)] + pub fn beue(&mut self) -> BEUE_W { + BEUE_W { w: self } + } + #[doc = "Bit 22 - Error Logging Overflow Interrupt Enable"] + #[inline(always)] + pub fn eloe(&mut self) -> ELOE_W { + ELOE_W { w: self } + } + #[doc = "Bit 23 - Error Passive Interrupt Enable"] + #[inline(always)] + pub fn epe(&mut self) -> EPE_W { + EPE_W { w: self } + } + #[doc = "Bit 24 - Warning Status Interrupt Enable"] + #[inline(always)] + pub fn ewe(&mut self) -> EWE_W { + EWE_W { w: self } + } + #[doc = "Bit 25 - Bus_Off Status Interrupt Enable"] + #[inline(always)] + pub fn boe(&mut self) -> BOE_W { + BOE_W { w: self } + } + #[doc = "Bit 26 - Watchdog Interrupt Interrupt Enable"] + #[inline(always)] + pub fn wdie(&mut self) -> WDIE_W { + WDIE_W { w: self } + } + #[doc = "Bit 27 - Protocol Error in Arbitration Phase Enable"] + #[inline(always)] + pub fn peae(&mut self) -> PEAE_W { + PEAE_W { w: self } + } + #[doc = "Bit 28 - Protocol Error in Data Phase Enable"] + #[inline(always)] + pub fn pede(&mut self) -> PEDE_W { + PEDE_W { w: self } + } + #[doc = "Bit 29 - Access to Reserved Address Enable"] + #[inline(always)] + pub fn arae(&mut self) -> ARAE_W { + ARAE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ie](index.html) module"] +pub struct IE_SPEC; +impl crate::RegisterSpec for IE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ie::R](R) reader structure"] +impl crate::Readable for IE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ie::W](W) writer structure"] +impl crate::Writable for IE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets IE to value 0"] +impl crate::Resettable for IE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/can0/ile.rs b/pac/atsamc21j/src/can0/ile.rs new file mode 100644 index 000000000000..3284b08f7d4c --- /dev/null +++ b/pac/atsamc21j/src/can0/ile.rs @@ -0,0 +1,160 @@ +#[doc = "Register `ILE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ILE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EINT0` reader - Enable Interrupt Line 0"] +pub struct EINT0_R(crate::FieldReader); +impl EINT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EINT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EINT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EINT0` writer - Enable Interrupt Line 0"] +pub struct EINT0_W<'a> { + w: &'a mut W, +} +impl<'a> EINT0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `EINT1` reader - Enable Interrupt Line 1"] +pub struct EINT1_R(crate::FieldReader); +impl EINT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EINT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EINT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EINT1` writer - Enable Interrupt Line 1"] +pub struct EINT1_W<'a> { + w: &'a mut W, +} +impl<'a> EINT1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - Enable Interrupt Line 0"] + #[inline(always)] + pub fn eint0(&self) -> EINT0_R { + EINT0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable Interrupt Line 1"] + #[inline(always)] + pub fn eint1(&self) -> EINT1_R { + EINT1_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Enable Interrupt Line 0"] + #[inline(always)] + pub fn eint0(&mut self) -> EINT0_W { + EINT0_W { w: self } + } + #[doc = "Bit 1 - Enable Interrupt Line 1"] + #[inline(always)] + pub fn eint1(&mut self) -> EINT1_W { + EINT1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Line Enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ile](index.html) module"] +pub struct ILE_SPEC; +impl crate::RegisterSpec for ILE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ile::R](R) reader structure"] +impl crate::Readable for ILE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ile::W](W) writer structure"] +impl crate::Writable for ILE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ILE to value 0"] +impl crate::Resettable for ILE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/can0/ils.rs b/pac/atsamc21j/src/can0/ils.rs new file mode 100644 index 000000000000..14ac6de68d59 --- /dev/null +++ b/pac/atsamc21j/src/can0/ils.rs @@ -0,0 +1,1476 @@ +#[doc = "Register `ILS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ILS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RF0NL` reader - Rx FIFO 0 New Message Interrupt Line"] +pub struct RF0NL_R(crate::FieldReader); +impl RF0NL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF0NL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF0NL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF0NL` writer - Rx FIFO 0 New Message Interrupt Line"] +pub struct RF0NL_W<'a> { + w: &'a mut W, +} +impl<'a> RF0NL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `RF0WL` reader - Rx FIFO 0 Watermark Reached Interrupt Line"] +pub struct RF0WL_R(crate::FieldReader); +impl RF0WL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF0WL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF0WL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF0WL` writer - Rx FIFO 0 Watermark Reached Interrupt Line"] +pub struct RF0WL_W<'a> { + w: &'a mut W, +} +impl<'a> RF0WL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RF0FL` reader - Rx FIFO 0 Full Interrupt Line"] +pub struct RF0FL_R(crate::FieldReader); +impl RF0FL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF0FL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF0FL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF0FL` writer - Rx FIFO 0 Full Interrupt Line"] +pub struct RF0FL_W<'a> { + w: &'a mut W, +} +impl<'a> RF0FL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RF0LL` reader - Rx FIFO 0 Message Lost Interrupt Line"] +pub struct RF0LL_R(crate::FieldReader); +impl RF0LL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF0LL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF0LL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF0LL` writer - Rx FIFO 0 Message Lost Interrupt Line"] +pub struct RF0LL_W<'a> { + w: &'a mut W, +} +impl<'a> RF0LL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `RF1NL` reader - Rx FIFO 1 New Message Interrupt Line"] +pub struct RF1NL_R(crate::FieldReader); +impl RF1NL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF1NL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF1NL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF1NL` writer - Rx FIFO 1 New Message Interrupt Line"] +pub struct RF1NL_W<'a> { + w: &'a mut W, +} +impl<'a> RF1NL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RF1WL` reader - Rx FIFO 1 Watermark Reached Interrupt Line"] +pub struct RF1WL_R(crate::FieldReader); +impl RF1WL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF1WL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF1WL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF1WL` writer - Rx FIFO 1 Watermark Reached Interrupt Line"] +pub struct RF1WL_W<'a> { + w: &'a mut W, +} +impl<'a> RF1WL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `RF1FL` reader - Rx FIFO 1 FIFO Full Interrupt Line"] +pub struct RF1FL_R(crate::FieldReader); +impl RF1FL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF1FL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF1FL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF1FL` writer - Rx FIFO 1 FIFO Full Interrupt Line"] +pub struct RF1FL_W<'a> { + w: &'a mut W, +} +impl<'a> RF1FL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `RF1LL` reader - Rx FIFO 1 Message Lost Interrupt Line"] +pub struct RF1LL_R(crate::FieldReader); +impl RF1LL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF1LL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF1LL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF1LL` writer - Rx FIFO 1 Message Lost Interrupt Line"] +pub struct RF1LL_W<'a> { + w: &'a mut W, +} +impl<'a> RF1LL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `HPML` reader - High Priority Message Interrupt Line"] +pub struct HPML_R(crate::FieldReader); +impl HPML_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HPML_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HPML_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HPML` writer - High Priority Message Interrupt Line"] +pub struct HPML_W<'a> { + w: &'a mut W, +} +impl<'a> HPML_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `TCL` reader - Timestamp Completed Interrupt Line"] +pub struct TCL_R(crate::FieldReader); +impl TCL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCL` writer - Timestamp Completed Interrupt Line"] +pub struct TCL_W<'a> { + w: &'a mut W, +} +impl<'a> TCL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `TCFL` reader - Transmission Cancellation Finished Interrupt Line"] +pub struct TCFL_R(crate::FieldReader); +impl TCFL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCFL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCFL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCFL` writer - Transmission Cancellation Finished Interrupt Line"] +pub struct TCFL_W<'a> { + w: &'a mut W, +} +impl<'a> TCFL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `TFEL` reader - Tx FIFO Empty Interrupt Line"] +pub struct TFEL_R(crate::FieldReader); +impl TFEL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TFEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TFEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TFEL` writer - Tx FIFO Empty Interrupt Line"] +pub struct TFEL_W<'a> { + w: &'a mut W, +} +impl<'a> TFEL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `TEFNL` reader - Tx Event FIFO New Entry Interrupt Line"] +pub struct TEFNL_R(crate::FieldReader); +impl TEFNL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TEFNL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TEFNL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TEFNL` writer - Tx Event FIFO New Entry Interrupt Line"] +pub struct TEFNL_W<'a> { + w: &'a mut W, +} +impl<'a> TEFNL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `TEFWL` reader - Tx Event FIFO Watermark Reached Interrupt Line"] +pub struct TEFWL_R(crate::FieldReader); +impl TEFWL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TEFWL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TEFWL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TEFWL` writer - Tx Event FIFO Watermark Reached Interrupt Line"] +pub struct TEFWL_W<'a> { + w: &'a mut W, +} +impl<'a> TEFWL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `TEFFL` reader - Tx Event FIFO Full Interrupt Line"] +pub struct TEFFL_R(crate::FieldReader); +impl TEFFL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TEFFL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TEFFL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TEFFL` writer - Tx Event FIFO Full Interrupt Line"] +pub struct TEFFL_W<'a> { + w: &'a mut W, +} +impl<'a> TEFFL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `TEFLL` reader - Tx Event FIFO Element Lost Interrupt Line"] +pub struct TEFLL_R(crate::FieldReader); +impl TEFLL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TEFLL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TEFLL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TEFLL` writer - Tx Event FIFO Element Lost Interrupt Line"] +pub struct TEFLL_W<'a> { + w: &'a mut W, +} +impl<'a> TEFLL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `TSWL` reader - Timestamp Wraparound Interrupt Line"] +pub struct TSWL_R(crate::FieldReader); +impl TSWL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSWL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSWL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSWL` writer - Timestamp Wraparound Interrupt Line"] +pub struct TSWL_W<'a> { + w: &'a mut W, +} +impl<'a> TSWL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `MRAFL` reader - Message RAM Access Failure Interrupt Line"] +pub struct MRAFL_R(crate::FieldReader); +impl MRAFL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MRAFL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MRAFL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MRAFL` writer - Message RAM Access Failure Interrupt Line"] +pub struct MRAFL_W<'a> { + w: &'a mut W, +} +impl<'a> MRAFL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `TOOL` reader - Timeout Occurred Interrupt Line"] +pub struct TOOL_R(crate::FieldReader); +impl TOOL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TOOL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TOOL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TOOL` writer - Timeout Occurred Interrupt Line"] +pub struct TOOL_W<'a> { + w: &'a mut W, +} +impl<'a> TOOL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `DRXL` reader - Message stored to Dedicated Rx Buffer Interrupt Line"] +pub struct DRXL_R(crate::FieldReader); +impl DRXL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRXL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRXL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRXL` writer - Message stored to Dedicated Rx Buffer Interrupt Line"] +pub struct DRXL_W<'a> { + w: &'a mut W, +} +impl<'a> DRXL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `BECL` reader - Bit Error Corrected Interrupt Line"] +pub struct BECL_R(crate::FieldReader); +impl BECL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BECL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BECL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BECL` writer - Bit Error Corrected Interrupt Line"] +pub struct BECL_W<'a> { + w: &'a mut W, +} +impl<'a> BECL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `BEUL` reader - Bit Error Uncorrected Interrupt Line"] +pub struct BEUL_R(crate::FieldReader); +impl BEUL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BEUL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BEUL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BEUL` writer - Bit Error Uncorrected Interrupt Line"] +pub struct BEUL_W<'a> { + w: &'a mut W, +} +impl<'a> BEUL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `ELOL` reader - Error Logging Overflow Interrupt Line"] +pub struct ELOL_R(crate::FieldReader); +impl ELOL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ELOL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ELOL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ELOL` writer - Error Logging Overflow Interrupt Line"] +pub struct ELOL_W<'a> { + w: &'a mut W, +} +impl<'a> ELOL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `EPL` reader - Error Passive Interrupt Line"] +pub struct EPL_R(crate::FieldReader); +impl EPL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EPL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EPL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EPL` writer - Error Passive Interrupt Line"] +pub struct EPL_W<'a> { + w: &'a mut W, +} +impl<'a> EPL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `EWL` reader - Warning Status Interrupt Line"] +pub struct EWL_R(crate::FieldReader); +impl EWL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EWL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EWL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EWL` writer - Warning Status Interrupt Line"] +pub struct EWL_W<'a> { + w: &'a mut W, +} +impl<'a> EWL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `BOL` reader - Bus_Off Status Interrupt Line"] +pub struct BOL_R(crate::FieldReader); +impl BOL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BOL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BOL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BOL` writer - Bus_Off Status Interrupt Line"] +pub struct BOL_W<'a> { + w: &'a mut W, +} +impl<'a> BOL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `WDIL` reader - Watchdog Interrupt Interrupt Line"] +pub struct WDIL_R(crate::FieldReader); +impl WDIL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WDIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WDIL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WDIL` writer - Watchdog Interrupt Interrupt Line"] +pub struct WDIL_W<'a> { + w: &'a mut W, +} +impl<'a> WDIL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `PEAL` reader - Protocol Error in Arbitration Phase Line"] +pub struct PEAL_R(crate::FieldReader); +impl PEAL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEAL` writer - Protocol Error in Arbitration Phase Line"] +pub struct PEAL_W<'a> { + w: &'a mut W, +} +impl<'a> PEAL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +#[doc = "Field `PEDL` reader - Protocol Error in Data Phase Line"] +pub struct PEDL_R(crate::FieldReader); +impl PEDL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEDL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEDL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEDL` writer - Protocol Error in Data Phase Line"] +pub struct PEDL_W<'a> { + w: &'a mut W, +} +impl<'a> PEDL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Field `ARAL` reader - Access to Reserved Address Line"] +pub struct ARAL_R(crate::FieldReader); +impl ARAL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ARAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ARAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ARAL` writer - Access to Reserved Address Line"] +pub struct ARAL_W<'a> { + w: &'a mut W, +} +impl<'a> ARAL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29); + self.w + } +} +impl R { + #[doc = "Bit 0 - Rx FIFO 0 New Message Interrupt Line"] + #[inline(always)] + pub fn rf0nl(&self) -> RF0NL_R { + RF0NL_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Rx FIFO 0 Watermark Reached Interrupt Line"] + #[inline(always)] + pub fn rf0wl(&self) -> RF0WL_R { + RF0WL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Rx FIFO 0 Full Interrupt Line"] + #[inline(always)] + pub fn rf0fl(&self) -> RF0FL_R { + RF0FL_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Rx FIFO 0 Message Lost Interrupt Line"] + #[inline(always)] + pub fn rf0ll(&self) -> RF0LL_R { + RF0LL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Rx FIFO 1 New Message Interrupt Line"] + #[inline(always)] + pub fn rf1nl(&self) -> RF1NL_R { + RF1NL_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Rx FIFO 1 Watermark Reached Interrupt Line"] + #[inline(always)] + pub fn rf1wl(&self) -> RF1WL_R { + RF1WL_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Rx FIFO 1 FIFO Full Interrupt Line"] + #[inline(always)] + pub fn rf1fl(&self) -> RF1FL_R { + RF1FL_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Rx FIFO 1 Message Lost Interrupt Line"] + #[inline(always)] + pub fn rf1ll(&self) -> RF1LL_R { + RF1LL_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - High Priority Message Interrupt Line"] + #[inline(always)] + pub fn hpml(&self) -> HPML_R { + HPML_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Timestamp Completed Interrupt Line"] + #[inline(always)] + pub fn tcl(&self) -> TCL_R { + TCL_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Transmission Cancellation Finished Interrupt Line"] + #[inline(always)] + pub fn tcfl(&self) -> TCFL_R { + TCFL_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Tx FIFO Empty Interrupt Line"] + #[inline(always)] + pub fn tfel(&self) -> TFEL_R { + TFEL_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Tx Event FIFO New Entry Interrupt Line"] + #[inline(always)] + pub fn tefnl(&self) -> TEFNL_R { + TEFNL_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Tx Event FIFO Watermark Reached Interrupt Line"] + #[inline(always)] + pub fn tefwl(&self) -> TEFWL_R { + TEFWL_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Tx Event FIFO Full Interrupt Line"] + #[inline(always)] + pub fn teffl(&self) -> TEFFL_R { + TEFFL_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Tx Event FIFO Element Lost Interrupt Line"] + #[inline(always)] + pub fn tefll(&self) -> TEFLL_R { + TEFLL_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Timestamp Wraparound Interrupt Line"] + #[inline(always)] + pub fn tswl(&self) -> TSWL_R { + TSWL_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Message RAM Access Failure Interrupt Line"] + #[inline(always)] + pub fn mrafl(&self) -> MRAFL_R { + MRAFL_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Timeout Occurred Interrupt Line"] + #[inline(always)] + pub fn tool(&self) -> TOOL_R { + TOOL_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Message stored to Dedicated Rx Buffer Interrupt Line"] + #[inline(always)] + pub fn drxl(&self) -> DRXL_R { + DRXL_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Bit Error Corrected Interrupt Line"] + #[inline(always)] + pub fn becl(&self) -> BECL_R { + BECL_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Bit Error Uncorrected Interrupt Line"] + #[inline(always)] + pub fn beul(&self) -> BEUL_R { + BEUL_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Error Logging Overflow Interrupt Line"] + #[inline(always)] + pub fn elol(&self) -> ELOL_R { + ELOL_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Error Passive Interrupt Line"] + #[inline(always)] + pub fn epl(&self) -> EPL_R { + EPL_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24 - Warning Status Interrupt Line"] + #[inline(always)] + pub fn ewl(&self) -> EWL_R { + EWL_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Bus_Off Status Interrupt Line"] + #[inline(always)] + pub fn bol(&self) -> BOL_R { + BOL_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Watchdog Interrupt Interrupt Line"] + #[inline(always)] + pub fn wdil(&self) -> WDIL_R { + WDIL_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Protocol Error in Arbitration Phase Line"] + #[inline(always)] + pub fn peal(&self) -> PEAL_R { + PEAL_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28 - Protocol Error in Data Phase Line"] + #[inline(always)] + pub fn pedl(&self) -> PEDL_R { + PEDL_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Access to Reserved Address Line"] + #[inline(always)] + pub fn aral(&self) -> ARAL_R { + ARAL_R::new(((self.bits >> 29) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Rx FIFO 0 New Message Interrupt Line"] + #[inline(always)] + pub fn rf0nl(&mut self) -> RF0NL_W { + RF0NL_W { w: self } + } + #[doc = "Bit 1 - Rx FIFO 0 Watermark Reached Interrupt Line"] + #[inline(always)] + pub fn rf0wl(&mut self) -> RF0WL_W { + RF0WL_W { w: self } + } + #[doc = "Bit 2 - Rx FIFO 0 Full Interrupt Line"] + #[inline(always)] + pub fn rf0fl(&mut self) -> RF0FL_W { + RF0FL_W { w: self } + } + #[doc = "Bit 3 - Rx FIFO 0 Message Lost Interrupt Line"] + #[inline(always)] + pub fn rf0ll(&mut self) -> RF0LL_W { + RF0LL_W { w: self } + } + #[doc = "Bit 4 - Rx FIFO 1 New Message Interrupt Line"] + #[inline(always)] + pub fn rf1nl(&mut self) -> RF1NL_W { + RF1NL_W { w: self } + } + #[doc = "Bit 5 - Rx FIFO 1 Watermark Reached Interrupt Line"] + #[inline(always)] + pub fn rf1wl(&mut self) -> RF1WL_W { + RF1WL_W { w: self } + } + #[doc = "Bit 6 - Rx FIFO 1 FIFO Full Interrupt Line"] + #[inline(always)] + pub fn rf1fl(&mut self) -> RF1FL_W { + RF1FL_W { w: self } + } + #[doc = "Bit 7 - Rx FIFO 1 Message Lost Interrupt Line"] + #[inline(always)] + pub fn rf1ll(&mut self) -> RF1LL_W { + RF1LL_W { w: self } + } + #[doc = "Bit 8 - High Priority Message Interrupt Line"] + #[inline(always)] + pub fn hpml(&mut self) -> HPML_W { + HPML_W { w: self } + } + #[doc = "Bit 9 - Timestamp Completed Interrupt Line"] + #[inline(always)] + pub fn tcl(&mut self) -> TCL_W { + TCL_W { w: self } + } + #[doc = "Bit 10 - Transmission Cancellation Finished Interrupt Line"] + #[inline(always)] + pub fn tcfl(&mut self) -> TCFL_W { + TCFL_W { w: self } + } + #[doc = "Bit 11 - Tx FIFO Empty Interrupt Line"] + #[inline(always)] + pub fn tfel(&mut self) -> TFEL_W { + TFEL_W { w: self } + } + #[doc = "Bit 12 - Tx Event FIFO New Entry Interrupt Line"] + #[inline(always)] + pub fn tefnl(&mut self) -> TEFNL_W { + TEFNL_W { w: self } + } + #[doc = "Bit 13 - Tx Event FIFO Watermark Reached Interrupt Line"] + #[inline(always)] + pub fn tefwl(&mut self) -> TEFWL_W { + TEFWL_W { w: self } + } + #[doc = "Bit 14 - Tx Event FIFO Full Interrupt Line"] + #[inline(always)] + pub fn teffl(&mut self) -> TEFFL_W { + TEFFL_W { w: self } + } + #[doc = "Bit 15 - Tx Event FIFO Element Lost Interrupt Line"] + #[inline(always)] + pub fn tefll(&mut self) -> TEFLL_W { + TEFLL_W { w: self } + } + #[doc = "Bit 16 - Timestamp Wraparound Interrupt Line"] + #[inline(always)] + pub fn tswl(&mut self) -> TSWL_W { + TSWL_W { w: self } + } + #[doc = "Bit 17 - Message RAM Access Failure Interrupt Line"] + #[inline(always)] + pub fn mrafl(&mut self) -> MRAFL_W { + MRAFL_W { w: self } + } + #[doc = "Bit 18 - Timeout Occurred Interrupt Line"] + #[inline(always)] + pub fn tool(&mut self) -> TOOL_W { + TOOL_W { w: self } + } + #[doc = "Bit 19 - Message stored to Dedicated Rx Buffer Interrupt Line"] + #[inline(always)] + pub fn drxl(&mut self) -> DRXL_W { + DRXL_W { w: self } + } + #[doc = "Bit 20 - Bit Error Corrected Interrupt Line"] + #[inline(always)] + pub fn becl(&mut self) -> BECL_W { + BECL_W { w: self } + } + #[doc = "Bit 21 - Bit Error Uncorrected Interrupt Line"] + #[inline(always)] + pub fn beul(&mut self) -> BEUL_W { + BEUL_W { w: self } + } + #[doc = "Bit 22 - Error Logging Overflow Interrupt Line"] + #[inline(always)] + pub fn elol(&mut self) -> ELOL_W { + ELOL_W { w: self } + } + #[doc = "Bit 23 - Error Passive Interrupt Line"] + #[inline(always)] + pub fn epl(&mut self) -> EPL_W { + EPL_W { w: self } + } + #[doc = "Bit 24 - Warning Status Interrupt Line"] + #[inline(always)] + pub fn ewl(&mut self) -> EWL_W { + EWL_W { w: self } + } + #[doc = "Bit 25 - Bus_Off Status Interrupt Line"] + #[inline(always)] + pub fn bol(&mut self) -> BOL_W { + BOL_W { w: self } + } + #[doc = "Bit 26 - Watchdog Interrupt Interrupt Line"] + #[inline(always)] + pub fn wdil(&mut self) -> WDIL_W { + WDIL_W { w: self } + } + #[doc = "Bit 27 - Protocol Error in Arbitration Phase Line"] + #[inline(always)] + pub fn peal(&mut self) -> PEAL_W { + PEAL_W { w: self } + } + #[doc = "Bit 28 - Protocol Error in Data Phase Line"] + #[inline(always)] + pub fn pedl(&mut self) -> PEDL_W { + PEDL_W { w: self } + } + #[doc = "Bit 29 - Access to Reserved Address Line"] + #[inline(always)] + pub fn aral(&mut self) -> ARAL_W { + ARAL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Line Select\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ils](index.html) module"] +pub struct ILS_SPEC; +impl crate::RegisterSpec for ILS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ils::R](R) reader structure"] +impl crate::Readable for ILS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ils::W](W) writer structure"] +impl crate::Writable for ILS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ILS to value 0"] +impl crate::Resettable for ILS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/can0/ir.rs b/pac/atsamc21j/src/can0/ir.rs new file mode 100644 index 000000000000..ae6efc178861 --- /dev/null +++ b/pac/atsamc21j/src/can0/ir.rs @@ -0,0 +1,1476 @@ +#[doc = "Register `IR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `IR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RF0N` reader - Rx FIFO 0 New Message"] +pub struct RF0N_R(crate::FieldReader); +impl RF0N_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF0N_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF0N_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF0N` writer - Rx FIFO 0 New Message"] +pub struct RF0N_W<'a> { + w: &'a mut W, +} +impl<'a> RF0N_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `RF0W` reader - Rx FIFO 0 Watermark Reached"] +pub struct RF0W_R(crate::FieldReader); +impl RF0W_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF0W_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF0W_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF0W` writer - Rx FIFO 0 Watermark Reached"] +pub struct RF0W_W<'a> { + w: &'a mut W, +} +impl<'a> RF0W_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RF0F` reader - Rx FIFO 0 Full"] +pub struct RF0F_R(crate::FieldReader); +impl RF0F_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF0F_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF0F_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF0F` writer - Rx FIFO 0 Full"] +pub struct RF0F_W<'a> { + w: &'a mut W, +} +impl<'a> RF0F_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RF0L` reader - Rx FIFO 0 Message Lost"] +pub struct RF0L_R(crate::FieldReader); +impl RF0L_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF0L_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF0L_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF0L` writer - Rx FIFO 0 Message Lost"] +pub struct RF0L_W<'a> { + w: &'a mut W, +} +impl<'a> RF0L_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `RF1N` reader - Rx FIFO 1 New Message"] +pub struct RF1N_R(crate::FieldReader); +impl RF1N_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF1N_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF1N_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF1N` writer - Rx FIFO 1 New Message"] +pub struct RF1N_W<'a> { + w: &'a mut W, +} +impl<'a> RF1N_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RF1W` reader - Rx FIFO 1 Watermark Reached"] +pub struct RF1W_R(crate::FieldReader); +impl RF1W_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF1W_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF1W_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF1W` writer - Rx FIFO 1 Watermark Reached"] +pub struct RF1W_W<'a> { + w: &'a mut W, +} +impl<'a> RF1W_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `RF1F` reader - Rx FIFO 1 FIFO Full"] +pub struct RF1F_R(crate::FieldReader); +impl RF1F_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF1F_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF1F_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF1F` writer - Rx FIFO 1 FIFO Full"] +pub struct RF1F_W<'a> { + w: &'a mut W, +} +impl<'a> RF1F_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `RF1L` reader - Rx FIFO 1 Message Lost"] +pub struct RF1L_R(crate::FieldReader); +impl RF1L_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF1L_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF1L_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF1L` writer - Rx FIFO 1 Message Lost"] +pub struct RF1L_W<'a> { + w: &'a mut W, +} +impl<'a> RF1L_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `HPM` reader - High Priority Message"] +pub struct HPM_R(crate::FieldReader); +impl HPM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HPM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HPM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HPM` writer - High Priority Message"] +pub struct HPM_W<'a> { + w: &'a mut W, +} +impl<'a> HPM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `TC` reader - Timestamp Completed"] +pub struct TC_R(crate::FieldReader); +impl TC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC` writer - Timestamp Completed"] +pub struct TC_W<'a> { + w: &'a mut W, +} +impl<'a> TC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `TCF` reader - Transmission Cancellation Finished"] +pub struct TCF_R(crate::FieldReader); +impl TCF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCF` writer - Transmission Cancellation Finished"] +pub struct TCF_W<'a> { + w: &'a mut W, +} +impl<'a> TCF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `TFE` reader - Tx FIFO Empty"] +pub struct TFE_R(crate::FieldReader); +impl TFE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TFE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TFE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TFE` writer - Tx FIFO Empty"] +pub struct TFE_W<'a> { + w: &'a mut W, +} +impl<'a> TFE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `TEFN` reader - Tx Event FIFO New Entry"] +pub struct TEFN_R(crate::FieldReader); +impl TEFN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TEFN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TEFN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TEFN` writer - Tx Event FIFO New Entry"] +pub struct TEFN_W<'a> { + w: &'a mut W, +} +impl<'a> TEFN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `TEFW` reader - Tx Event FIFO Watermark Reached"] +pub struct TEFW_R(crate::FieldReader); +impl TEFW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TEFW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TEFW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TEFW` writer - Tx Event FIFO Watermark Reached"] +pub struct TEFW_W<'a> { + w: &'a mut W, +} +impl<'a> TEFW_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `TEFF` reader - Tx Event FIFO Full"] +pub struct TEFF_R(crate::FieldReader); +impl TEFF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TEFF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TEFF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TEFF` writer - Tx Event FIFO Full"] +pub struct TEFF_W<'a> { + w: &'a mut W, +} +impl<'a> TEFF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `TEFL` reader - Tx Event FIFO Element Lost"] +pub struct TEFL_R(crate::FieldReader); +impl TEFL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TEFL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TEFL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TEFL` writer - Tx Event FIFO Element Lost"] +pub struct TEFL_W<'a> { + w: &'a mut W, +} +impl<'a> TEFL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `TSW` reader - Timestamp Wraparound"] +pub struct TSW_R(crate::FieldReader); +impl TSW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSW` writer - Timestamp Wraparound"] +pub struct TSW_W<'a> { + w: &'a mut W, +} +impl<'a> TSW_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `MRAF` reader - Message RAM Access Failure"] +pub struct MRAF_R(crate::FieldReader); +impl MRAF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MRAF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MRAF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MRAF` writer - Message RAM Access Failure"] +pub struct MRAF_W<'a> { + w: &'a mut W, +} +impl<'a> MRAF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `TOO` reader - Timeout Occurred"] +pub struct TOO_R(crate::FieldReader); +impl TOO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TOO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TOO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TOO` writer - Timeout Occurred"] +pub struct TOO_W<'a> { + w: &'a mut W, +} +impl<'a> TOO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `DRX` reader - Message stored to Dedicated Rx Buffer"] +pub struct DRX_R(crate::FieldReader); +impl DRX_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRX_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRX_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRX` writer - Message stored to Dedicated Rx Buffer"] +pub struct DRX_W<'a> { + w: &'a mut W, +} +impl<'a> DRX_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `BEC` reader - Bit Error Corrected"] +pub struct BEC_R(crate::FieldReader); +impl BEC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BEC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BEC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BEC` writer - Bit Error Corrected"] +pub struct BEC_W<'a> { + w: &'a mut W, +} +impl<'a> BEC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `BEU` reader - Bit Error Uncorrected"] +pub struct BEU_R(crate::FieldReader); +impl BEU_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BEU_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BEU_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BEU` writer - Bit Error Uncorrected"] +pub struct BEU_W<'a> { + w: &'a mut W, +} +impl<'a> BEU_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `ELO` reader - Error Logging Overflow"] +pub struct ELO_R(crate::FieldReader); +impl ELO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ELO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ELO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ELO` writer - Error Logging Overflow"] +pub struct ELO_W<'a> { + w: &'a mut W, +} +impl<'a> ELO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `EP` reader - Error Passive"] +pub struct EP_R(crate::FieldReader); +impl EP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EP` writer - Error Passive"] +pub struct EP_W<'a> { + w: &'a mut W, +} +impl<'a> EP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `EW` reader - Warning Status"] +pub struct EW_R(crate::FieldReader); +impl EW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EW` writer - Warning Status"] +pub struct EW_W<'a> { + w: &'a mut W, +} +impl<'a> EW_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `BO` reader - Bus_Off Status"] +pub struct BO_R(crate::FieldReader); +impl BO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BO` writer - Bus_Off Status"] +pub struct BO_W<'a> { + w: &'a mut W, +} +impl<'a> BO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `WDI` reader - Watchdog Interrupt"] +pub struct WDI_R(crate::FieldReader); +impl WDI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WDI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WDI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WDI` writer - Watchdog Interrupt"] +pub struct WDI_W<'a> { + w: &'a mut W, +} +impl<'a> WDI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `PEA` reader - Protocol Error in Arbitration Phase"] +pub struct PEA_R(crate::FieldReader); +impl PEA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEA` writer - Protocol Error in Arbitration Phase"] +pub struct PEA_W<'a> { + w: &'a mut W, +} +impl<'a> PEA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +#[doc = "Field `PED` reader - Protocol Error in Data Phase"] +pub struct PED_R(crate::FieldReader); +impl PED_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PED_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PED` writer - Protocol Error in Data Phase"] +pub struct PED_W<'a> { + w: &'a mut W, +} +impl<'a> PED_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Field `ARA` reader - Access to Reserved Address"] +pub struct ARA_R(crate::FieldReader); +impl ARA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ARA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ARA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ARA` writer - Access to Reserved Address"] +pub struct ARA_W<'a> { + w: &'a mut W, +} +impl<'a> ARA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29); + self.w + } +} +impl R { + #[doc = "Bit 0 - Rx FIFO 0 New Message"] + #[inline(always)] + pub fn rf0n(&self) -> RF0N_R { + RF0N_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Rx FIFO 0 Watermark Reached"] + #[inline(always)] + pub fn rf0w(&self) -> RF0W_R { + RF0W_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Rx FIFO 0 Full"] + #[inline(always)] + pub fn rf0f(&self) -> RF0F_R { + RF0F_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Rx FIFO 0 Message Lost"] + #[inline(always)] + pub fn rf0l(&self) -> RF0L_R { + RF0L_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Rx FIFO 1 New Message"] + #[inline(always)] + pub fn rf1n(&self) -> RF1N_R { + RF1N_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Rx FIFO 1 Watermark Reached"] + #[inline(always)] + pub fn rf1w(&self) -> RF1W_R { + RF1W_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Rx FIFO 1 FIFO Full"] + #[inline(always)] + pub fn rf1f(&self) -> RF1F_R { + RF1F_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Rx FIFO 1 Message Lost"] + #[inline(always)] + pub fn rf1l(&self) -> RF1L_R { + RF1L_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - High Priority Message"] + #[inline(always)] + pub fn hpm(&self) -> HPM_R { + HPM_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Timestamp Completed"] + #[inline(always)] + pub fn tc(&self) -> TC_R { + TC_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Transmission Cancellation Finished"] + #[inline(always)] + pub fn tcf(&self) -> TCF_R { + TCF_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Tx FIFO Empty"] + #[inline(always)] + pub fn tfe(&self) -> TFE_R { + TFE_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Tx Event FIFO New Entry"] + #[inline(always)] + pub fn tefn(&self) -> TEFN_R { + TEFN_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Tx Event FIFO Watermark Reached"] + #[inline(always)] + pub fn tefw(&self) -> TEFW_R { + TEFW_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Tx Event FIFO Full"] + #[inline(always)] + pub fn teff(&self) -> TEFF_R { + TEFF_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Tx Event FIFO Element Lost"] + #[inline(always)] + pub fn tefl(&self) -> TEFL_R { + TEFL_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Timestamp Wraparound"] + #[inline(always)] + pub fn tsw(&self) -> TSW_R { + TSW_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Message RAM Access Failure"] + #[inline(always)] + pub fn mraf(&self) -> MRAF_R { + MRAF_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Timeout Occurred"] + #[inline(always)] + pub fn too(&self) -> TOO_R { + TOO_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Message stored to Dedicated Rx Buffer"] + #[inline(always)] + pub fn drx(&self) -> DRX_R { + DRX_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Bit Error Corrected"] + #[inline(always)] + pub fn bec(&self) -> BEC_R { + BEC_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Bit Error Uncorrected"] + #[inline(always)] + pub fn beu(&self) -> BEU_R { + BEU_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Error Logging Overflow"] + #[inline(always)] + pub fn elo(&self) -> ELO_R { + ELO_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Error Passive"] + #[inline(always)] + pub fn ep(&self) -> EP_R { + EP_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24 - Warning Status"] + #[inline(always)] + pub fn ew(&self) -> EW_R { + EW_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Bus_Off Status"] + #[inline(always)] + pub fn bo(&self) -> BO_R { + BO_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Watchdog Interrupt"] + #[inline(always)] + pub fn wdi(&self) -> WDI_R { + WDI_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Protocol Error in Arbitration Phase"] + #[inline(always)] + pub fn pea(&self) -> PEA_R { + PEA_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28 - Protocol Error in Data Phase"] + #[inline(always)] + pub fn ped(&self) -> PED_R { + PED_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Access to Reserved Address"] + #[inline(always)] + pub fn ara(&self) -> ARA_R { + ARA_R::new(((self.bits >> 29) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Rx FIFO 0 New Message"] + #[inline(always)] + pub fn rf0n(&mut self) -> RF0N_W { + RF0N_W { w: self } + } + #[doc = "Bit 1 - Rx FIFO 0 Watermark Reached"] + #[inline(always)] + pub fn rf0w(&mut self) -> RF0W_W { + RF0W_W { w: self } + } + #[doc = "Bit 2 - Rx FIFO 0 Full"] + #[inline(always)] + pub fn rf0f(&mut self) -> RF0F_W { + RF0F_W { w: self } + } + #[doc = "Bit 3 - Rx FIFO 0 Message Lost"] + #[inline(always)] + pub fn rf0l(&mut self) -> RF0L_W { + RF0L_W { w: self } + } + #[doc = "Bit 4 - Rx FIFO 1 New Message"] + #[inline(always)] + pub fn rf1n(&mut self) -> RF1N_W { + RF1N_W { w: self } + } + #[doc = "Bit 5 - Rx FIFO 1 Watermark Reached"] + #[inline(always)] + pub fn rf1w(&mut self) -> RF1W_W { + RF1W_W { w: self } + } + #[doc = "Bit 6 - Rx FIFO 1 FIFO Full"] + #[inline(always)] + pub fn rf1f(&mut self) -> RF1F_W { + RF1F_W { w: self } + } + #[doc = "Bit 7 - Rx FIFO 1 Message Lost"] + #[inline(always)] + pub fn rf1l(&mut self) -> RF1L_W { + RF1L_W { w: self } + } + #[doc = "Bit 8 - High Priority Message"] + #[inline(always)] + pub fn hpm(&mut self) -> HPM_W { + HPM_W { w: self } + } + #[doc = "Bit 9 - Timestamp Completed"] + #[inline(always)] + pub fn tc(&mut self) -> TC_W { + TC_W { w: self } + } + #[doc = "Bit 10 - Transmission Cancellation Finished"] + #[inline(always)] + pub fn tcf(&mut self) -> TCF_W { + TCF_W { w: self } + } + #[doc = "Bit 11 - Tx FIFO Empty"] + #[inline(always)] + pub fn tfe(&mut self) -> TFE_W { + TFE_W { w: self } + } + #[doc = "Bit 12 - Tx Event FIFO New Entry"] + #[inline(always)] + pub fn tefn(&mut self) -> TEFN_W { + TEFN_W { w: self } + } + #[doc = "Bit 13 - Tx Event FIFO Watermark Reached"] + #[inline(always)] + pub fn tefw(&mut self) -> TEFW_W { + TEFW_W { w: self } + } + #[doc = "Bit 14 - Tx Event FIFO Full"] + #[inline(always)] + pub fn teff(&mut self) -> TEFF_W { + TEFF_W { w: self } + } + #[doc = "Bit 15 - Tx Event FIFO Element Lost"] + #[inline(always)] + pub fn tefl(&mut self) -> TEFL_W { + TEFL_W { w: self } + } + #[doc = "Bit 16 - Timestamp Wraparound"] + #[inline(always)] + pub fn tsw(&mut self) -> TSW_W { + TSW_W { w: self } + } + #[doc = "Bit 17 - Message RAM Access Failure"] + #[inline(always)] + pub fn mraf(&mut self) -> MRAF_W { + MRAF_W { w: self } + } + #[doc = "Bit 18 - Timeout Occurred"] + #[inline(always)] + pub fn too(&mut self) -> TOO_W { + TOO_W { w: self } + } + #[doc = "Bit 19 - Message stored to Dedicated Rx Buffer"] + #[inline(always)] + pub fn drx(&mut self) -> DRX_W { + DRX_W { w: self } + } + #[doc = "Bit 20 - Bit Error Corrected"] + #[inline(always)] + pub fn bec(&mut self) -> BEC_W { + BEC_W { w: self } + } + #[doc = "Bit 21 - Bit Error Uncorrected"] + #[inline(always)] + pub fn beu(&mut self) -> BEU_W { + BEU_W { w: self } + } + #[doc = "Bit 22 - Error Logging Overflow"] + #[inline(always)] + pub fn elo(&mut self) -> ELO_W { + ELO_W { w: self } + } + #[doc = "Bit 23 - Error Passive"] + #[inline(always)] + pub fn ep(&mut self) -> EP_W { + EP_W { w: self } + } + #[doc = "Bit 24 - Warning Status"] + #[inline(always)] + pub fn ew(&mut self) -> EW_W { + EW_W { w: self } + } + #[doc = "Bit 25 - Bus_Off Status"] + #[inline(always)] + pub fn bo(&mut self) -> BO_W { + BO_W { w: self } + } + #[doc = "Bit 26 - Watchdog Interrupt"] + #[inline(always)] + pub fn wdi(&mut self) -> WDI_W { + WDI_W { w: self } + } + #[doc = "Bit 27 - Protocol Error in Arbitration Phase"] + #[inline(always)] + pub fn pea(&mut self) -> PEA_W { + PEA_W { w: self } + } + #[doc = "Bit 28 - Protocol Error in Data Phase"] + #[inline(always)] + pub fn ped(&mut self) -> PED_W { + PED_W { w: self } + } + #[doc = "Bit 29 - Access to Reserved Address"] + #[inline(always)] + pub fn ara(&mut self) -> ARA_W { + ARA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ir](index.html) module"] +pub struct IR_SPEC; +impl crate::RegisterSpec for IR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ir::R](R) reader structure"] +impl crate::Readable for IR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ir::W](W) writer structure"] +impl crate::Writable for IR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets IR to value 0"] +impl crate::Resettable for IR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/can0/mrcfg.rs b/pac/atsamc21j/src/can0/mrcfg.rs new file mode 100644 index 000000000000..7a4b25f0969a --- /dev/null +++ b/pac/atsamc21j/src/can0/mrcfg.rs @@ -0,0 +1,178 @@ +#[doc = "Register `MRCFG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MRCFG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Quality of Service\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum QOS_A { + #[doc = "0: Background (no sensitive operation)"] + DISABLE = 0, + #[doc = "1: Sensitive Bandwidth"] + LOW = 1, + #[doc = "2: Sensitive Latency"] + MEDIUM = 2, + #[doc = "3: Critical Latency"] + HIGH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: QOS_A) -> Self { + variant as _ + } +} +#[doc = "Field `QOS` reader - Quality of Service"] +pub struct QOS_R(crate::FieldReader); +impl QOS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + QOS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> QOS_A { + match self.bits { + 0 => QOS_A::DISABLE, + 1 => QOS_A::LOW, + 2 => QOS_A::MEDIUM, + 3 => QOS_A::HIGH, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == QOS_A::DISABLE + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == QOS_A::LOW + } + #[doc = "Checks if the value of the field is `MEDIUM`"] + #[inline(always)] + pub fn is_medium(&self) -> bool { + **self == QOS_A::MEDIUM + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == QOS_A::HIGH + } +} +impl core::ops::Deref for QOS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `QOS` writer - Quality of Service"] +pub struct QOS_W<'a> { + w: &'a mut W, +} +impl<'a> QOS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: QOS_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Background (no sensitive operation)"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(QOS_A::DISABLE) + } + #[doc = "Sensitive Bandwidth"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(QOS_A::LOW) + } + #[doc = "Sensitive Latency"] + #[inline(always)] + pub fn medium(self) -> &'a mut W { + self.variant(QOS_A::MEDIUM) + } + #[doc = "Critical Latency"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(QOS_A::HIGH) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u32 & 0x03); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Quality of Service"] + #[inline(always)] + pub fn qos(&self) -> QOS_R { + QOS_R::new((self.bits & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Quality of Service"] + #[inline(always)] + pub fn qos(&mut self) -> QOS_W { + QOS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Message RAM Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mrcfg](index.html) module"] +pub struct MRCFG_SPEC; +impl crate::RegisterSpec for MRCFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [mrcfg::R](R) reader structure"] +impl crate::Readable for MRCFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [mrcfg::W](W) writer structure"] +impl crate::Writable for MRCFG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets MRCFG to value 0x02"] +impl crate::Resettable for MRCFG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x02 + } +} diff --git a/pac/atsamc21j/src/can0/nbtp.rs b/pac/atsamc21j/src/can0/nbtp.rs new file mode 100644 index 000000000000..8de06d283b22 --- /dev/null +++ b/pac/atsamc21j/src/can0/nbtp.rs @@ -0,0 +1,214 @@ +#[doc = "Register `NBTP` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `NBTP` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `NTSEG2` reader - Nominal Time segment after sample point"] +pub struct NTSEG2_R(crate::FieldReader); +impl NTSEG2_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + NTSEG2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NTSEG2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NTSEG2` writer - Nominal Time segment after sample point"] +pub struct NTSEG2_W<'a> { + w: &'a mut W, +} +impl<'a> NTSEG2_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x7f) | (value as u32 & 0x7f); + self.w + } +} +#[doc = "Field `NTSEG1` reader - Nominal Time segment before sample point"] +pub struct NTSEG1_R(crate::FieldReader); +impl NTSEG1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + NTSEG1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NTSEG1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NTSEG1` writer - Nominal Time segment before sample point"] +pub struct NTSEG1_W<'a> { + w: &'a mut W, +} +impl<'a> NTSEG1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +#[doc = "Field `NBRP` reader - Nominal Baud Rate Prescaler"] +pub struct NBRP_R(crate::FieldReader); +impl NBRP_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + NBRP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NBRP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NBRP` writer - Nominal Baud Rate Prescaler"] +pub struct NBRP_W<'a> { + w: &'a mut W, +} +impl<'a> NBRP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01ff << 16)) | ((value as u32 & 0x01ff) << 16); + self.w + } +} +#[doc = "Field `NSJW` reader - Nominal (Re)Synchronization Jump Width"] +pub struct NSJW_R(crate::FieldReader); +impl NSJW_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + NSJW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NSJW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NSJW` writer - Nominal (Re)Synchronization Jump Width"] +pub struct NSJW_W<'a> { + w: &'a mut W, +} +impl<'a> NSJW_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x7f << 25)) | ((value as u32 & 0x7f) << 25); + self.w + } +} +impl R { + #[doc = "Bits 0:6 - Nominal Time segment after sample point"] + #[inline(always)] + pub fn ntseg2(&self) -> NTSEG2_R { + NTSEG2_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bits 8:15 - Nominal Time segment before sample point"] + #[inline(always)] + pub fn ntseg1(&self) -> NTSEG1_R { + NTSEG1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:24 - Nominal Baud Rate Prescaler"] + #[inline(always)] + pub fn nbrp(&self) -> NBRP_R { + NBRP_R::new(((self.bits >> 16) & 0x01ff) as u16) + } + #[doc = "Bits 25:31 - Nominal (Re)Synchronization Jump Width"] + #[inline(always)] + pub fn nsjw(&self) -> NSJW_R { + NSJW_R::new(((self.bits >> 25) & 0x7f) as u8) + } +} +impl W { + #[doc = "Bits 0:6 - Nominal Time segment after sample point"] + #[inline(always)] + pub fn ntseg2(&mut self) -> NTSEG2_W { + NTSEG2_W { w: self } + } + #[doc = "Bits 8:15 - Nominal Time segment before sample point"] + #[inline(always)] + pub fn ntseg1(&mut self) -> NTSEG1_W { + NTSEG1_W { w: self } + } + #[doc = "Bits 16:24 - Nominal Baud Rate Prescaler"] + #[inline(always)] + pub fn nbrp(&mut self) -> NBRP_W { + NBRP_W { w: self } + } + #[doc = "Bits 25:31 - Nominal (Re)Synchronization Jump Width"] + #[inline(always)] + pub fn nsjw(&mut self) -> NSJW_W { + NSJW_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Nominal Bit Timing and Prescaler\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [nbtp](index.html) module"] +pub struct NBTP_SPEC; +impl crate::RegisterSpec for NBTP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [nbtp::R](R) reader structure"] +impl crate::Readable for NBTP_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [nbtp::W](W) writer structure"] +impl crate::Writable for NBTP_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets NBTP to value 0x0600_0a03"] +impl crate::Resettable for NBTP_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0600_0a03 + } +} diff --git a/pac/atsamc21j/src/can0/ndat1.rs b/pac/atsamc21j/src/can0/ndat1.rs new file mode 100644 index 000000000000..63da465a27d8 --- /dev/null +++ b/pac/atsamc21j/src/can0/ndat1.rs @@ -0,0 +1,1570 @@ +#[doc = "Register `NDAT1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `NDAT1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ND0` reader - New Data 0"] +pub struct ND0_R(crate::FieldReader); +impl ND0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND0` writer - New Data 0"] +pub struct ND0_W<'a> { + w: &'a mut W, +} +impl<'a> ND0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ND1` reader - New Data 1"] +pub struct ND1_R(crate::FieldReader); +impl ND1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND1` writer - New Data 1"] +pub struct ND1_W<'a> { + w: &'a mut W, +} +impl<'a> ND1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ND2` reader - New Data 2"] +pub struct ND2_R(crate::FieldReader); +impl ND2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND2` writer - New Data 2"] +pub struct ND2_W<'a> { + w: &'a mut W, +} +impl<'a> ND2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `ND3` reader - New Data 3"] +pub struct ND3_R(crate::FieldReader); +impl ND3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND3` writer - New Data 3"] +pub struct ND3_W<'a> { + w: &'a mut W, +} +impl<'a> ND3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ND4` reader - New Data 4"] +pub struct ND4_R(crate::FieldReader); +impl ND4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND4` writer - New Data 4"] +pub struct ND4_W<'a> { + w: &'a mut W, +} +impl<'a> ND4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `ND5` reader - New Data 5"] +pub struct ND5_R(crate::FieldReader); +impl ND5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND5` writer - New Data 5"] +pub struct ND5_W<'a> { + w: &'a mut W, +} +impl<'a> ND5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `ND6` reader - New Data 6"] +pub struct ND6_R(crate::FieldReader); +impl ND6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND6` writer - New Data 6"] +pub struct ND6_W<'a> { + w: &'a mut W, +} +impl<'a> ND6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ND7` reader - New Data 7"] +pub struct ND7_R(crate::FieldReader); +impl ND7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND7` writer - New Data 7"] +pub struct ND7_W<'a> { + w: &'a mut W, +} +impl<'a> ND7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `ND8` reader - New Data 8"] +pub struct ND8_R(crate::FieldReader); +impl ND8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND8` writer - New Data 8"] +pub struct ND8_W<'a> { + w: &'a mut W, +} +impl<'a> ND8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `ND9` reader - New Data 9"] +pub struct ND9_R(crate::FieldReader); +impl ND9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND9` writer - New Data 9"] +pub struct ND9_W<'a> { + w: &'a mut W, +} +impl<'a> ND9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `ND10` reader - New Data 10"] +pub struct ND10_R(crate::FieldReader); +impl ND10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND10` writer - New Data 10"] +pub struct ND10_W<'a> { + w: &'a mut W, +} +impl<'a> ND10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `ND11` reader - New Data 11"] +pub struct ND11_R(crate::FieldReader); +impl ND11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND11` writer - New Data 11"] +pub struct ND11_W<'a> { + w: &'a mut W, +} +impl<'a> ND11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `ND12` reader - New Data 12"] +pub struct ND12_R(crate::FieldReader); +impl ND12_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND12_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND12_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND12` writer - New Data 12"] +pub struct ND12_W<'a> { + w: &'a mut W, +} +impl<'a> ND12_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `ND13` reader - New Data 13"] +pub struct ND13_R(crate::FieldReader); +impl ND13_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND13_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND13_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND13` writer - New Data 13"] +pub struct ND13_W<'a> { + w: &'a mut W, +} +impl<'a> ND13_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `ND14` reader - New Data 14"] +pub struct ND14_R(crate::FieldReader); +impl ND14_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND14_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND14_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND14` writer - New Data 14"] +pub struct ND14_W<'a> { + w: &'a mut W, +} +impl<'a> ND14_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `ND15` reader - New Data 15"] +pub struct ND15_R(crate::FieldReader); +impl ND15_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND15_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND15_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND15` writer - New Data 15"] +pub struct ND15_W<'a> { + w: &'a mut W, +} +impl<'a> ND15_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `ND16` reader - New Data 16"] +pub struct ND16_R(crate::FieldReader); +impl ND16_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND16_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND16_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND16` writer - New Data 16"] +pub struct ND16_W<'a> { + w: &'a mut W, +} +impl<'a> ND16_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `ND17` reader - New Data 17"] +pub struct ND17_R(crate::FieldReader); +impl ND17_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND17_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND17_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND17` writer - New Data 17"] +pub struct ND17_W<'a> { + w: &'a mut W, +} +impl<'a> ND17_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `ND18` reader - New Data 18"] +pub struct ND18_R(crate::FieldReader); +impl ND18_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND18_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND18_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND18` writer - New Data 18"] +pub struct ND18_W<'a> { + w: &'a mut W, +} +impl<'a> ND18_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `ND19` reader - New Data 19"] +pub struct ND19_R(crate::FieldReader); +impl ND19_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND19_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND19_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND19` writer - New Data 19"] +pub struct ND19_W<'a> { + w: &'a mut W, +} +impl<'a> ND19_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `ND20` reader - New Data 20"] +pub struct ND20_R(crate::FieldReader); +impl ND20_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND20_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND20_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND20` writer - New Data 20"] +pub struct ND20_W<'a> { + w: &'a mut W, +} +impl<'a> ND20_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `ND21` reader - New Data 21"] +pub struct ND21_R(crate::FieldReader); +impl ND21_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND21_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND21_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND21` writer - New Data 21"] +pub struct ND21_W<'a> { + w: &'a mut W, +} +impl<'a> ND21_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `ND22` reader - New Data 22"] +pub struct ND22_R(crate::FieldReader); +impl ND22_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND22_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND22_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND22` writer - New Data 22"] +pub struct ND22_W<'a> { + w: &'a mut W, +} +impl<'a> ND22_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `ND23` reader - New Data 23"] +pub struct ND23_R(crate::FieldReader); +impl ND23_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND23_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND23_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND23` writer - New Data 23"] +pub struct ND23_W<'a> { + w: &'a mut W, +} +impl<'a> ND23_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `ND24` reader - New Data 24"] +pub struct ND24_R(crate::FieldReader); +impl ND24_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND24_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND24_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND24` writer - New Data 24"] +pub struct ND24_W<'a> { + w: &'a mut W, +} +impl<'a> ND24_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `ND25` reader - New Data 25"] +pub struct ND25_R(crate::FieldReader); +impl ND25_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND25_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND25_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND25` writer - New Data 25"] +pub struct ND25_W<'a> { + w: &'a mut W, +} +impl<'a> ND25_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `ND26` reader - New Data 26"] +pub struct ND26_R(crate::FieldReader); +impl ND26_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND26_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND26_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND26` writer - New Data 26"] +pub struct ND26_W<'a> { + w: &'a mut W, +} +impl<'a> ND26_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `ND27` reader - New Data 27"] +pub struct ND27_R(crate::FieldReader); +impl ND27_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND27_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND27_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND27` writer - New Data 27"] +pub struct ND27_W<'a> { + w: &'a mut W, +} +impl<'a> ND27_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +#[doc = "Field `ND28` reader - New Data 28"] +pub struct ND28_R(crate::FieldReader); +impl ND28_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND28_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND28_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND28` writer - New Data 28"] +pub struct ND28_W<'a> { + w: &'a mut W, +} +impl<'a> ND28_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Field `ND29` reader - New Data 29"] +pub struct ND29_R(crate::FieldReader); +impl ND29_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND29_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND29_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND29` writer - New Data 29"] +pub struct ND29_W<'a> { + w: &'a mut W, +} +impl<'a> ND29_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29); + self.w + } +} +#[doc = "Field `ND30` reader - New Data 30"] +pub struct ND30_R(crate::FieldReader); +impl ND30_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND30_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND30_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND30` writer - New Data 30"] +pub struct ND30_W<'a> { + w: &'a mut W, +} +impl<'a> ND30_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +#[doc = "Field `ND31` reader - New Data 31"] +pub struct ND31_R(crate::FieldReader); +impl ND31_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND31_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND31_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND31` writer - New Data 31"] +pub struct ND31_W<'a> { + w: &'a mut W, +} +impl<'a> ND31_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bit 0 - New Data 0"] + #[inline(always)] + pub fn nd0(&self) -> ND0_R { + ND0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - New Data 1"] + #[inline(always)] + pub fn nd1(&self) -> ND1_R { + ND1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - New Data 2"] + #[inline(always)] + pub fn nd2(&self) -> ND2_R { + ND2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - New Data 3"] + #[inline(always)] + pub fn nd3(&self) -> ND3_R { + ND3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - New Data 4"] + #[inline(always)] + pub fn nd4(&self) -> ND4_R { + ND4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - New Data 5"] + #[inline(always)] + pub fn nd5(&self) -> ND5_R { + ND5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - New Data 6"] + #[inline(always)] + pub fn nd6(&self) -> ND6_R { + ND6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - New Data 7"] + #[inline(always)] + pub fn nd7(&self) -> ND7_R { + ND7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - New Data 8"] + #[inline(always)] + pub fn nd8(&self) -> ND8_R { + ND8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - New Data 9"] + #[inline(always)] + pub fn nd9(&self) -> ND9_R { + ND9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - New Data 10"] + #[inline(always)] + pub fn nd10(&self) -> ND10_R { + ND10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - New Data 11"] + #[inline(always)] + pub fn nd11(&self) -> ND11_R { + ND11_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - New Data 12"] + #[inline(always)] + pub fn nd12(&self) -> ND12_R { + ND12_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - New Data 13"] + #[inline(always)] + pub fn nd13(&self) -> ND13_R { + ND13_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - New Data 14"] + #[inline(always)] + pub fn nd14(&self) -> ND14_R { + ND14_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - New Data 15"] + #[inline(always)] + pub fn nd15(&self) -> ND15_R { + ND15_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - New Data 16"] + #[inline(always)] + pub fn nd16(&self) -> ND16_R { + ND16_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - New Data 17"] + #[inline(always)] + pub fn nd17(&self) -> ND17_R { + ND17_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - New Data 18"] + #[inline(always)] + pub fn nd18(&self) -> ND18_R { + ND18_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - New Data 19"] + #[inline(always)] + pub fn nd19(&self) -> ND19_R { + ND19_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - New Data 20"] + #[inline(always)] + pub fn nd20(&self) -> ND20_R { + ND20_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - New Data 21"] + #[inline(always)] + pub fn nd21(&self) -> ND21_R { + ND21_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - New Data 22"] + #[inline(always)] + pub fn nd22(&self) -> ND22_R { + ND22_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - New Data 23"] + #[inline(always)] + pub fn nd23(&self) -> ND23_R { + ND23_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24 - New Data 24"] + #[inline(always)] + pub fn nd24(&self) -> ND24_R { + ND24_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - New Data 25"] + #[inline(always)] + pub fn nd25(&self) -> ND25_R { + ND25_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - New Data 26"] + #[inline(always)] + pub fn nd26(&self) -> ND26_R { + ND26_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - New Data 27"] + #[inline(always)] + pub fn nd27(&self) -> ND27_R { + ND27_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28 - New Data 28"] + #[inline(always)] + pub fn nd28(&self) -> ND28_R { + ND28_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - New Data 29"] + #[inline(always)] + pub fn nd29(&self) -> ND29_R { + ND29_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - New Data 30"] + #[inline(always)] + pub fn nd30(&self) -> ND30_R { + ND30_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 31 - New Data 31"] + #[inline(always)] + pub fn nd31(&self) -> ND31_R { + ND31_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - New Data 0"] + #[inline(always)] + pub fn nd0(&mut self) -> ND0_W { + ND0_W { w: self } + } + #[doc = "Bit 1 - New Data 1"] + #[inline(always)] + pub fn nd1(&mut self) -> ND1_W { + ND1_W { w: self } + } + #[doc = "Bit 2 - New Data 2"] + #[inline(always)] + pub fn nd2(&mut self) -> ND2_W { + ND2_W { w: self } + } + #[doc = "Bit 3 - New Data 3"] + #[inline(always)] + pub fn nd3(&mut self) -> ND3_W { + ND3_W { w: self } + } + #[doc = "Bit 4 - New Data 4"] + #[inline(always)] + pub fn nd4(&mut self) -> ND4_W { + ND4_W { w: self } + } + #[doc = "Bit 5 - New Data 5"] + #[inline(always)] + pub fn nd5(&mut self) -> ND5_W { + ND5_W { w: self } + } + #[doc = "Bit 6 - New Data 6"] + #[inline(always)] + pub fn nd6(&mut self) -> ND6_W { + ND6_W { w: self } + } + #[doc = "Bit 7 - New Data 7"] + #[inline(always)] + pub fn nd7(&mut self) -> ND7_W { + ND7_W { w: self } + } + #[doc = "Bit 8 - New Data 8"] + #[inline(always)] + pub fn nd8(&mut self) -> ND8_W { + ND8_W { w: self } + } + #[doc = "Bit 9 - New Data 9"] + #[inline(always)] + pub fn nd9(&mut self) -> ND9_W { + ND9_W { w: self } + } + #[doc = "Bit 10 - New Data 10"] + #[inline(always)] + pub fn nd10(&mut self) -> ND10_W { + ND10_W { w: self } + } + #[doc = "Bit 11 - New Data 11"] + #[inline(always)] + pub fn nd11(&mut self) -> ND11_W { + ND11_W { w: self } + } + #[doc = "Bit 12 - New Data 12"] + #[inline(always)] + pub fn nd12(&mut self) -> ND12_W { + ND12_W { w: self } + } + #[doc = "Bit 13 - New Data 13"] + #[inline(always)] + pub fn nd13(&mut self) -> ND13_W { + ND13_W { w: self } + } + #[doc = "Bit 14 - New Data 14"] + #[inline(always)] + pub fn nd14(&mut self) -> ND14_W { + ND14_W { w: self } + } + #[doc = "Bit 15 - New Data 15"] + #[inline(always)] + pub fn nd15(&mut self) -> ND15_W { + ND15_W { w: self } + } + #[doc = "Bit 16 - New Data 16"] + #[inline(always)] + pub fn nd16(&mut self) -> ND16_W { + ND16_W { w: self } + } + #[doc = "Bit 17 - New Data 17"] + #[inline(always)] + pub fn nd17(&mut self) -> ND17_W { + ND17_W { w: self } + } + #[doc = "Bit 18 - New Data 18"] + #[inline(always)] + pub fn nd18(&mut self) -> ND18_W { + ND18_W { w: self } + } + #[doc = "Bit 19 - New Data 19"] + #[inline(always)] + pub fn nd19(&mut self) -> ND19_W { + ND19_W { w: self } + } + #[doc = "Bit 20 - New Data 20"] + #[inline(always)] + pub fn nd20(&mut self) -> ND20_W { + ND20_W { w: self } + } + #[doc = "Bit 21 - New Data 21"] + #[inline(always)] + pub fn nd21(&mut self) -> ND21_W { + ND21_W { w: self } + } + #[doc = "Bit 22 - New Data 22"] + #[inline(always)] + pub fn nd22(&mut self) -> ND22_W { + ND22_W { w: self } + } + #[doc = "Bit 23 - New Data 23"] + #[inline(always)] + pub fn nd23(&mut self) -> ND23_W { + ND23_W { w: self } + } + #[doc = "Bit 24 - New Data 24"] + #[inline(always)] + pub fn nd24(&mut self) -> ND24_W { + ND24_W { w: self } + } + #[doc = "Bit 25 - New Data 25"] + #[inline(always)] + pub fn nd25(&mut self) -> ND25_W { + ND25_W { w: self } + } + #[doc = "Bit 26 - New Data 26"] + #[inline(always)] + pub fn nd26(&mut self) -> ND26_W { + ND26_W { w: self } + } + #[doc = "Bit 27 - New Data 27"] + #[inline(always)] + pub fn nd27(&mut self) -> ND27_W { + ND27_W { w: self } + } + #[doc = "Bit 28 - New Data 28"] + #[inline(always)] + pub fn nd28(&mut self) -> ND28_W { + ND28_W { w: self } + } + #[doc = "Bit 29 - New Data 29"] + #[inline(always)] + pub fn nd29(&mut self) -> ND29_W { + ND29_W { w: self } + } + #[doc = "Bit 30 - New Data 30"] + #[inline(always)] + pub fn nd30(&mut self) -> ND30_W { + ND30_W { w: self } + } + #[doc = "Bit 31 - New Data 31"] + #[inline(always)] + pub fn nd31(&mut self) -> ND31_W { + ND31_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "New Data 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ndat1](index.html) module"] +pub struct NDAT1_SPEC; +impl crate::RegisterSpec for NDAT1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ndat1::R](R) reader structure"] +impl crate::Readable for NDAT1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ndat1::W](W) writer structure"] +impl crate::Writable for NDAT1_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets NDAT1 to value 0"] +impl crate::Resettable for NDAT1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/can0/ndat2.rs b/pac/atsamc21j/src/can0/ndat2.rs new file mode 100644 index 000000000000..ada8dac123fb --- /dev/null +++ b/pac/atsamc21j/src/can0/ndat2.rs @@ -0,0 +1,1570 @@ +#[doc = "Register `NDAT2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `NDAT2` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ND32` reader - New Data 32"] +pub struct ND32_R(crate::FieldReader); +impl ND32_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND32_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND32_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND32` writer - New Data 32"] +pub struct ND32_W<'a> { + w: &'a mut W, +} +impl<'a> ND32_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ND33` reader - New Data 33"] +pub struct ND33_R(crate::FieldReader); +impl ND33_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND33_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND33_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND33` writer - New Data 33"] +pub struct ND33_W<'a> { + w: &'a mut W, +} +impl<'a> ND33_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ND34` reader - New Data 34"] +pub struct ND34_R(crate::FieldReader); +impl ND34_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND34_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND34_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND34` writer - New Data 34"] +pub struct ND34_W<'a> { + w: &'a mut W, +} +impl<'a> ND34_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `ND35` reader - New Data 35"] +pub struct ND35_R(crate::FieldReader); +impl ND35_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND35_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND35_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND35` writer - New Data 35"] +pub struct ND35_W<'a> { + w: &'a mut W, +} +impl<'a> ND35_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ND36` reader - New Data 36"] +pub struct ND36_R(crate::FieldReader); +impl ND36_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND36_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND36_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND36` writer - New Data 36"] +pub struct ND36_W<'a> { + w: &'a mut W, +} +impl<'a> ND36_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `ND37` reader - New Data 37"] +pub struct ND37_R(crate::FieldReader); +impl ND37_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND37_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND37_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND37` writer - New Data 37"] +pub struct ND37_W<'a> { + w: &'a mut W, +} +impl<'a> ND37_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `ND38` reader - New Data 38"] +pub struct ND38_R(crate::FieldReader); +impl ND38_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND38_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND38_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND38` writer - New Data 38"] +pub struct ND38_W<'a> { + w: &'a mut W, +} +impl<'a> ND38_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ND39` reader - New Data 39"] +pub struct ND39_R(crate::FieldReader); +impl ND39_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND39_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND39_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND39` writer - New Data 39"] +pub struct ND39_W<'a> { + w: &'a mut W, +} +impl<'a> ND39_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `ND40` reader - New Data 40"] +pub struct ND40_R(crate::FieldReader); +impl ND40_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND40_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND40_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND40` writer - New Data 40"] +pub struct ND40_W<'a> { + w: &'a mut W, +} +impl<'a> ND40_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `ND41` reader - New Data 41"] +pub struct ND41_R(crate::FieldReader); +impl ND41_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND41_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND41_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND41` writer - New Data 41"] +pub struct ND41_W<'a> { + w: &'a mut W, +} +impl<'a> ND41_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `ND42` reader - New Data 42"] +pub struct ND42_R(crate::FieldReader); +impl ND42_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND42_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND42_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND42` writer - New Data 42"] +pub struct ND42_W<'a> { + w: &'a mut W, +} +impl<'a> ND42_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `ND43` reader - New Data 43"] +pub struct ND43_R(crate::FieldReader); +impl ND43_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND43_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND43_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND43` writer - New Data 43"] +pub struct ND43_W<'a> { + w: &'a mut W, +} +impl<'a> ND43_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `ND44` reader - New Data 44"] +pub struct ND44_R(crate::FieldReader); +impl ND44_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND44_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND44_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND44` writer - New Data 44"] +pub struct ND44_W<'a> { + w: &'a mut W, +} +impl<'a> ND44_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `ND45` reader - New Data 45"] +pub struct ND45_R(crate::FieldReader); +impl ND45_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND45_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND45_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND45` writer - New Data 45"] +pub struct ND45_W<'a> { + w: &'a mut W, +} +impl<'a> ND45_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `ND46` reader - New Data 46"] +pub struct ND46_R(crate::FieldReader); +impl ND46_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND46_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND46_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND46` writer - New Data 46"] +pub struct ND46_W<'a> { + w: &'a mut W, +} +impl<'a> ND46_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `ND47` reader - New Data 47"] +pub struct ND47_R(crate::FieldReader); +impl ND47_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND47_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND47_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND47` writer - New Data 47"] +pub struct ND47_W<'a> { + w: &'a mut W, +} +impl<'a> ND47_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `ND48` reader - New Data 48"] +pub struct ND48_R(crate::FieldReader); +impl ND48_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND48_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND48_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND48` writer - New Data 48"] +pub struct ND48_W<'a> { + w: &'a mut W, +} +impl<'a> ND48_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `ND49` reader - New Data 49"] +pub struct ND49_R(crate::FieldReader); +impl ND49_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND49_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND49_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND49` writer - New Data 49"] +pub struct ND49_W<'a> { + w: &'a mut W, +} +impl<'a> ND49_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `ND50` reader - New Data 50"] +pub struct ND50_R(crate::FieldReader); +impl ND50_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND50_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND50_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND50` writer - New Data 50"] +pub struct ND50_W<'a> { + w: &'a mut W, +} +impl<'a> ND50_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `ND51` reader - New Data 51"] +pub struct ND51_R(crate::FieldReader); +impl ND51_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND51_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND51_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND51` writer - New Data 51"] +pub struct ND51_W<'a> { + w: &'a mut W, +} +impl<'a> ND51_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `ND52` reader - New Data 52"] +pub struct ND52_R(crate::FieldReader); +impl ND52_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND52_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND52_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND52` writer - New Data 52"] +pub struct ND52_W<'a> { + w: &'a mut W, +} +impl<'a> ND52_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `ND53` reader - New Data 53"] +pub struct ND53_R(crate::FieldReader); +impl ND53_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND53_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND53_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND53` writer - New Data 53"] +pub struct ND53_W<'a> { + w: &'a mut W, +} +impl<'a> ND53_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `ND54` reader - New Data 54"] +pub struct ND54_R(crate::FieldReader); +impl ND54_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND54_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND54_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND54` writer - New Data 54"] +pub struct ND54_W<'a> { + w: &'a mut W, +} +impl<'a> ND54_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `ND55` reader - New Data 55"] +pub struct ND55_R(crate::FieldReader); +impl ND55_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND55_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND55_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND55` writer - New Data 55"] +pub struct ND55_W<'a> { + w: &'a mut W, +} +impl<'a> ND55_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `ND56` reader - New Data 56"] +pub struct ND56_R(crate::FieldReader); +impl ND56_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND56_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND56_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND56` writer - New Data 56"] +pub struct ND56_W<'a> { + w: &'a mut W, +} +impl<'a> ND56_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `ND57` reader - New Data 57"] +pub struct ND57_R(crate::FieldReader); +impl ND57_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND57_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND57_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND57` writer - New Data 57"] +pub struct ND57_W<'a> { + w: &'a mut W, +} +impl<'a> ND57_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `ND58` reader - New Data 58"] +pub struct ND58_R(crate::FieldReader); +impl ND58_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND58_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND58_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND58` writer - New Data 58"] +pub struct ND58_W<'a> { + w: &'a mut W, +} +impl<'a> ND58_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `ND59` reader - New Data 59"] +pub struct ND59_R(crate::FieldReader); +impl ND59_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND59_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND59_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND59` writer - New Data 59"] +pub struct ND59_W<'a> { + w: &'a mut W, +} +impl<'a> ND59_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +#[doc = "Field `ND60` reader - New Data 60"] +pub struct ND60_R(crate::FieldReader); +impl ND60_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND60_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND60_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND60` writer - New Data 60"] +pub struct ND60_W<'a> { + w: &'a mut W, +} +impl<'a> ND60_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Field `ND61` reader - New Data 61"] +pub struct ND61_R(crate::FieldReader); +impl ND61_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND61_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND61_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND61` writer - New Data 61"] +pub struct ND61_W<'a> { + w: &'a mut W, +} +impl<'a> ND61_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29); + self.w + } +} +#[doc = "Field `ND62` reader - New Data 62"] +pub struct ND62_R(crate::FieldReader); +impl ND62_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND62_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND62_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND62` writer - New Data 62"] +pub struct ND62_W<'a> { + w: &'a mut W, +} +impl<'a> ND62_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +#[doc = "Field `ND63` reader - New Data 63"] +pub struct ND63_R(crate::FieldReader); +impl ND63_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND63_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND63_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND63` writer - New Data 63"] +pub struct ND63_W<'a> { + w: &'a mut W, +} +impl<'a> ND63_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bit 0 - New Data 32"] + #[inline(always)] + pub fn nd32(&self) -> ND32_R { + ND32_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - New Data 33"] + #[inline(always)] + pub fn nd33(&self) -> ND33_R { + ND33_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - New Data 34"] + #[inline(always)] + pub fn nd34(&self) -> ND34_R { + ND34_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - New Data 35"] + #[inline(always)] + pub fn nd35(&self) -> ND35_R { + ND35_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - New Data 36"] + #[inline(always)] + pub fn nd36(&self) -> ND36_R { + ND36_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - New Data 37"] + #[inline(always)] + pub fn nd37(&self) -> ND37_R { + ND37_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - New Data 38"] + #[inline(always)] + pub fn nd38(&self) -> ND38_R { + ND38_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - New Data 39"] + #[inline(always)] + pub fn nd39(&self) -> ND39_R { + ND39_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - New Data 40"] + #[inline(always)] + pub fn nd40(&self) -> ND40_R { + ND40_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - New Data 41"] + #[inline(always)] + pub fn nd41(&self) -> ND41_R { + ND41_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - New Data 42"] + #[inline(always)] + pub fn nd42(&self) -> ND42_R { + ND42_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - New Data 43"] + #[inline(always)] + pub fn nd43(&self) -> ND43_R { + ND43_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - New Data 44"] + #[inline(always)] + pub fn nd44(&self) -> ND44_R { + ND44_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - New Data 45"] + #[inline(always)] + pub fn nd45(&self) -> ND45_R { + ND45_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - New Data 46"] + #[inline(always)] + pub fn nd46(&self) -> ND46_R { + ND46_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - New Data 47"] + #[inline(always)] + pub fn nd47(&self) -> ND47_R { + ND47_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - New Data 48"] + #[inline(always)] + pub fn nd48(&self) -> ND48_R { + ND48_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - New Data 49"] + #[inline(always)] + pub fn nd49(&self) -> ND49_R { + ND49_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - New Data 50"] + #[inline(always)] + pub fn nd50(&self) -> ND50_R { + ND50_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - New Data 51"] + #[inline(always)] + pub fn nd51(&self) -> ND51_R { + ND51_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - New Data 52"] + #[inline(always)] + pub fn nd52(&self) -> ND52_R { + ND52_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - New Data 53"] + #[inline(always)] + pub fn nd53(&self) -> ND53_R { + ND53_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - New Data 54"] + #[inline(always)] + pub fn nd54(&self) -> ND54_R { + ND54_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - New Data 55"] + #[inline(always)] + pub fn nd55(&self) -> ND55_R { + ND55_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24 - New Data 56"] + #[inline(always)] + pub fn nd56(&self) -> ND56_R { + ND56_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - New Data 57"] + #[inline(always)] + pub fn nd57(&self) -> ND57_R { + ND57_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - New Data 58"] + #[inline(always)] + pub fn nd58(&self) -> ND58_R { + ND58_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - New Data 59"] + #[inline(always)] + pub fn nd59(&self) -> ND59_R { + ND59_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28 - New Data 60"] + #[inline(always)] + pub fn nd60(&self) -> ND60_R { + ND60_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - New Data 61"] + #[inline(always)] + pub fn nd61(&self) -> ND61_R { + ND61_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - New Data 62"] + #[inline(always)] + pub fn nd62(&self) -> ND62_R { + ND62_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 31 - New Data 63"] + #[inline(always)] + pub fn nd63(&self) -> ND63_R { + ND63_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - New Data 32"] + #[inline(always)] + pub fn nd32(&mut self) -> ND32_W { + ND32_W { w: self } + } + #[doc = "Bit 1 - New Data 33"] + #[inline(always)] + pub fn nd33(&mut self) -> ND33_W { + ND33_W { w: self } + } + #[doc = "Bit 2 - New Data 34"] + #[inline(always)] + pub fn nd34(&mut self) -> ND34_W { + ND34_W { w: self } + } + #[doc = "Bit 3 - New Data 35"] + #[inline(always)] + pub fn nd35(&mut self) -> ND35_W { + ND35_W { w: self } + } + #[doc = "Bit 4 - New Data 36"] + #[inline(always)] + pub fn nd36(&mut self) -> ND36_W { + ND36_W { w: self } + } + #[doc = "Bit 5 - New Data 37"] + #[inline(always)] + pub fn nd37(&mut self) -> ND37_W { + ND37_W { w: self } + } + #[doc = "Bit 6 - New Data 38"] + #[inline(always)] + pub fn nd38(&mut self) -> ND38_W { + ND38_W { w: self } + } + #[doc = "Bit 7 - New Data 39"] + #[inline(always)] + pub fn nd39(&mut self) -> ND39_W { + ND39_W { w: self } + } + #[doc = "Bit 8 - New Data 40"] + #[inline(always)] + pub fn nd40(&mut self) -> ND40_W { + ND40_W { w: self } + } + #[doc = "Bit 9 - New Data 41"] + #[inline(always)] + pub fn nd41(&mut self) -> ND41_W { + ND41_W { w: self } + } + #[doc = "Bit 10 - New Data 42"] + #[inline(always)] + pub fn nd42(&mut self) -> ND42_W { + ND42_W { w: self } + } + #[doc = "Bit 11 - New Data 43"] + #[inline(always)] + pub fn nd43(&mut self) -> ND43_W { + ND43_W { w: self } + } + #[doc = "Bit 12 - New Data 44"] + #[inline(always)] + pub fn nd44(&mut self) -> ND44_W { + ND44_W { w: self } + } + #[doc = "Bit 13 - New Data 45"] + #[inline(always)] + pub fn nd45(&mut self) -> ND45_W { + ND45_W { w: self } + } + #[doc = "Bit 14 - New Data 46"] + #[inline(always)] + pub fn nd46(&mut self) -> ND46_W { + ND46_W { w: self } + } + #[doc = "Bit 15 - New Data 47"] + #[inline(always)] + pub fn nd47(&mut self) -> ND47_W { + ND47_W { w: self } + } + #[doc = "Bit 16 - New Data 48"] + #[inline(always)] + pub fn nd48(&mut self) -> ND48_W { + ND48_W { w: self } + } + #[doc = "Bit 17 - New Data 49"] + #[inline(always)] + pub fn nd49(&mut self) -> ND49_W { + ND49_W { w: self } + } + #[doc = "Bit 18 - New Data 50"] + #[inline(always)] + pub fn nd50(&mut self) -> ND50_W { + ND50_W { w: self } + } + #[doc = "Bit 19 - New Data 51"] + #[inline(always)] + pub fn nd51(&mut self) -> ND51_W { + ND51_W { w: self } + } + #[doc = "Bit 20 - New Data 52"] + #[inline(always)] + pub fn nd52(&mut self) -> ND52_W { + ND52_W { w: self } + } + #[doc = "Bit 21 - New Data 53"] + #[inline(always)] + pub fn nd53(&mut self) -> ND53_W { + ND53_W { w: self } + } + #[doc = "Bit 22 - New Data 54"] + #[inline(always)] + pub fn nd54(&mut self) -> ND54_W { + ND54_W { w: self } + } + #[doc = "Bit 23 - New Data 55"] + #[inline(always)] + pub fn nd55(&mut self) -> ND55_W { + ND55_W { w: self } + } + #[doc = "Bit 24 - New Data 56"] + #[inline(always)] + pub fn nd56(&mut self) -> ND56_W { + ND56_W { w: self } + } + #[doc = "Bit 25 - New Data 57"] + #[inline(always)] + pub fn nd57(&mut self) -> ND57_W { + ND57_W { w: self } + } + #[doc = "Bit 26 - New Data 58"] + #[inline(always)] + pub fn nd58(&mut self) -> ND58_W { + ND58_W { w: self } + } + #[doc = "Bit 27 - New Data 59"] + #[inline(always)] + pub fn nd59(&mut self) -> ND59_W { + ND59_W { w: self } + } + #[doc = "Bit 28 - New Data 60"] + #[inline(always)] + pub fn nd60(&mut self) -> ND60_W { + ND60_W { w: self } + } + #[doc = "Bit 29 - New Data 61"] + #[inline(always)] + pub fn nd61(&mut self) -> ND61_W { + ND61_W { w: self } + } + #[doc = "Bit 30 - New Data 62"] + #[inline(always)] + pub fn nd62(&mut self) -> ND62_W { + ND62_W { w: self } + } + #[doc = "Bit 31 - New Data 63"] + #[inline(always)] + pub fn nd63(&mut self) -> ND63_W { + ND63_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "New Data 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ndat2](index.html) module"] +pub struct NDAT2_SPEC; +impl crate::RegisterSpec for NDAT2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ndat2::R](R) reader structure"] +impl crate::Readable for NDAT2_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ndat2::W](W) writer structure"] +impl crate::Writable for NDAT2_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets NDAT2 to value 0"] +impl crate::Resettable for NDAT2_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/can0/psr.rs b/pac/atsamc21j/src/can0/psr.rs new file mode 100644 index 000000000000..0b5f73b9413b --- /dev/null +++ b/pac/atsamc21j/src/can0/psr.rs @@ -0,0 +1,467 @@ +#[doc = "Register `PSR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Last Error Code\n\nValue on reset: 7"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum LEC_A { + #[doc = "0: No Error"] + NONE = 0, + #[doc = "1: Stuff Error"] + STUFF = 1, + #[doc = "2: Form Error"] + FORM = 2, + #[doc = "3: Ack Error"] + ACK = 3, + #[doc = "4: Bit1 Error"] + BIT1 = 4, + #[doc = "5: Bit0 Error"] + BIT0 = 5, + #[doc = "6: CRC Error"] + CRC = 6, + #[doc = "7: No Change"] + NC = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LEC_A) -> Self { + variant as _ + } +} +#[doc = "Field `LEC` reader - Last Error Code"] +pub struct LEC_R(crate::FieldReader); +impl LEC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LEC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> LEC_A { + match self.bits { + 0 => LEC_A::NONE, + 1 => LEC_A::STUFF, + 2 => LEC_A::FORM, + 3 => LEC_A::ACK, + 4 => LEC_A::BIT1, + 5 => LEC_A::BIT0, + 6 => LEC_A::CRC, + 7 => LEC_A::NC, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == LEC_A::NONE + } + #[doc = "Checks if the value of the field is `STUFF`"] + #[inline(always)] + pub fn is_stuff(&self) -> bool { + **self == LEC_A::STUFF + } + #[doc = "Checks if the value of the field is `FORM`"] + #[inline(always)] + pub fn is_form(&self) -> bool { + **self == LEC_A::FORM + } + #[doc = "Checks if the value of the field is `ACK`"] + #[inline(always)] + pub fn is_ack(&self) -> bool { + **self == LEC_A::ACK + } + #[doc = "Checks if the value of the field is `BIT1`"] + #[inline(always)] + pub fn is_bit1(&self) -> bool { + **self == LEC_A::BIT1 + } + #[doc = "Checks if the value of the field is `BIT0`"] + #[inline(always)] + pub fn is_bit0(&self) -> bool { + **self == LEC_A::BIT0 + } + #[doc = "Checks if the value of the field is `CRC`"] + #[inline(always)] + pub fn is_crc(&self) -> bool { + **self == LEC_A::CRC + } + #[doc = "Checks if the value of the field is `NC`"] + #[inline(always)] + pub fn is_nc(&self) -> bool { + **self == LEC_A::NC + } +} +impl core::ops::Deref for LEC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Activity\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum ACT_A { + #[doc = "0: Node is synchronizing on CAN communication"] + SYNC = 0, + #[doc = "1: Node is neither receiver nor transmitter"] + IDLE = 1, + #[doc = "2: Node is operating as receiver"] + RX = 2, + #[doc = "3: Node is operating as transmitter"] + TX = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: ACT_A) -> Self { + variant as _ + } +} +#[doc = "Field `ACT` reader - Activity"] +pub struct ACT_R(crate::FieldReader); +impl ACT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ACT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ACT_A { + match self.bits { + 0 => ACT_A::SYNC, + 1 => ACT_A::IDLE, + 2 => ACT_A::RX, + 3 => ACT_A::TX, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `SYNC`"] + #[inline(always)] + pub fn is_sync(&self) -> bool { + **self == ACT_A::SYNC + } + #[doc = "Checks if the value of the field is `IDLE`"] + #[inline(always)] + pub fn is_idle(&self) -> bool { + **self == ACT_A::IDLE + } + #[doc = "Checks if the value of the field is `RX`"] + #[inline(always)] + pub fn is_rx(&self) -> bool { + **self == ACT_A::RX + } + #[doc = "Checks if the value of the field is `TX`"] + #[inline(always)] + pub fn is_tx(&self) -> bool { + **self == ACT_A::TX + } +} +impl core::ops::Deref for ACT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EP` reader - Error Passive"] +pub struct EP_R(crate::FieldReader); +impl EP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EW` reader - Warning Status"] +pub struct EW_R(crate::FieldReader); +impl EW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BO` reader - Bus_Off Status"] +pub struct BO_R(crate::FieldReader); +impl BO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Data Phase Last Error Code\n\nValue on reset: 7"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DLEC_A { + #[doc = "0: No Error"] + NONE = 0, + #[doc = "1: Stuff Error"] + STUFF = 1, + #[doc = "2: Form Error"] + FORM = 2, + #[doc = "3: Ack Error"] + ACK = 3, + #[doc = "4: Bit1 Error"] + BIT1 = 4, + #[doc = "5: Bit0 Error"] + BIT0 = 5, + #[doc = "6: CRC Error"] + CRC = 6, + #[doc = "7: No Change"] + NC = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DLEC_A) -> Self { + variant as _ + } +} +#[doc = "Field `DLEC` reader - Data Phase Last Error Code"] +pub struct DLEC_R(crate::FieldReader); +impl DLEC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DLEC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DLEC_A { + match self.bits { + 0 => DLEC_A::NONE, + 1 => DLEC_A::STUFF, + 2 => DLEC_A::FORM, + 3 => DLEC_A::ACK, + 4 => DLEC_A::BIT1, + 5 => DLEC_A::BIT0, + 6 => DLEC_A::CRC, + 7 => DLEC_A::NC, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == DLEC_A::NONE + } + #[doc = "Checks if the value of the field is `STUFF`"] + #[inline(always)] + pub fn is_stuff(&self) -> bool { + **self == DLEC_A::STUFF + } + #[doc = "Checks if the value of the field is `FORM`"] + #[inline(always)] + pub fn is_form(&self) -> bool { + **self == DLEC_A::FORM + } + #[doc = "Checks if the value of the field is `ACK`"] + #[inline(always)] + pub fn is_ack(&self) -> bool { + **self == DLEC_A::ACK + } + #[doc = "Checks if the value of the field is `BIT1`"] + #[inline(always)] + pub fn is_bit1(&self) -> bool { + **self == DLEC_A::BIT1 + } + #[doc = "Checks if the value of the field is `BIT0`"] + #[inline(always)] + pub fn is_bit0(&self) -> bool { + **self == DLEC_A::BIT0 + } + #[doc = "Checks if the value of the field is `CRC`"] + #[inline(always)] + pub fn is_crc(&self) -> bool { + **self == DLEC_A::CRC + } + #[doc = "Checks if the value of the field is `NC`"] + #[inline(always)] + pub fn is_nc(&self) -> bool { + **self == DLEC_A::NC + } +} +impl core::ops::Deref for DLEC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESI` reader - ESI flag of last received CAN FD Message"] +pub struct RESI_R(crate::FieldReader); +impl RESI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RBRS` reader - BRS flag of last received CAN FD Message"] +pub struct RBRS_R(crate::FieldReader); +impl RBRS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RBRS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RBRS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RFDF` reader - Received a CAN FD Message"] +pub struct RFDF_R(crate::FieldReader); +impl RFDF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RFDF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RFDF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PXE` reader - Protocol Exception Event"] +pub struct PXE_R(crate::FieldReader); +impl PXE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PXE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PXE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TDCV` reader - Transmitter Delay Compensation Value"] +pub struct TDCV_R(crate::FieldReader); +impl TDCV_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TDCV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TDCV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:2 - Last Error Code"] + #[inline(always)] + pub fn lec(&self) -> LEC_R { + LEC_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bits 3:4 - Activity"] + #[inline(always)] + pub fn act(&self) -> ACT_R { + ACT_R::new(((self.bits >> 3) & 0x03) as u8) + } + #[doc = "Bit 5 - Error Passive"] + #[inline(always)] + pub fn ep(&self) -> EP_R { + EP_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Warning Status"] + #[inline(always)] + pub fn ew(&self) -> EW_R { + EW_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Bus_Off Status"] + #[inline(always)] + pub fn bo(&self) -> BO_R { + BO_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Data Phase Last Error Code"] + #[inline(always)] + pub fn dlec(&self) -> DLEC_R { + DLEC_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 11 - ESI flag of last received CAN FD Message"] + #[inline(always)] + pub fn resi(&self) -> RESI_R { + RESI_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - BRS flag of last received CAN FD Message"] + #[inline(always)] + pub fn rbrs(&self) -> RBRS_R { + RBRS_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Received a CAN FD Message"] + #[inline(always)] + pub fn rfdf(&self) -> RFDF_R { + RFDF_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Protocol Exception Event"] + #[inline(always)] + pub fn pxe(&self) -> PXE_R { + PXE_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bits 16:22 - Transmitter Delay Compensation Value"] + #[inline(always)] + pub fn tdcv(&self) -> TDCV_R { + TDCV_R::new(((self.bits >> 16) & 0x7f) as u8) + } +} +#[doc = "Protocol Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [psr](index.html) module"] +pub struct PSR_SPEC; +impl crate::RegisterSpec for PSR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [psr::R](R) reader structure"] +impl crate::Readable for PSR_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PSR to value 0x0707"] +impl crate::Resettable for PSR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0707 + } +} diff --git a/pac/atsamc21j/src/can0/rwd.rs b/pac/atsamc21j/src/can0/rwd.rs new file mode 100644 index 000000000000..88f5b86a33f2 --- /dev/null +++ b/pac/atsamc21j/src/can0/rwd.rs @@ -0,0 +1,140 @@ +#[doc = "Register `RWD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RWD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WDC` reader - Watchdog Configuration"] +pub struct WDC_R(crate::FieldReader); +impl WDC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WDC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WDC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WDC` writer - Watchdog Configuration"] +pub struct WDC_W<'a> { + w: &'a mut W, +} +impl<'a> WDC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +#[doc = "Field `WDV` reader - Watchdog Value"] +pub struct WDV_R(crate::FieldReader); +impl WDV_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WDV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WDV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WDV` writer - Watchdog Value"] +pub struct WDV_W<'a> { + w: &'a mut W, +} +impl<'a> WDV_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Watchdog Configuration"] + #[inline(always)] + pub fn wdc(&self) -> WDC_R { + WDC_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Watchdog Value"] + #[inline(always)] + pub fn wdv(&self) -> WDV_R { + WDV_R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Watchdog Configuration"] + #[inline(always)] + pub fn wdc(&mut self) -> WDC_W { + WDC_W { w: self } + } + #[doc = "Bits 8:15 - Watchdog Value"] + #[inline(always)] + pub fn wdv(&mut self) -> WDV_W { + WDV_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "RAM Watchdog\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rwd](index.html) module"] +pub struct RWD_SPEC; +impl crate::RegisterSpec for RWD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rwd::R](R) reader structure"] +impl crate::Readable for RWD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rwd::W](W) writer structure"] +impl crate::Writable for RWD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RWD to value 0"] +impl crate::Resettable for RWD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/can0/rxbc.rs b/pac/atsamc21j/src/can0/rxbc.rs new file mode 100644 index 000000000000..d320ea61f4c2 --- /dev/null +++ b/pac/atsamc21j/src/can0/rxbc.rs @@ -0,0 +1,103 @@ +#[doc = "Register `RXBC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RXBC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RBSA` reader - Rx Buffer Start Address"] +pub struct RBSA_R(crate::FieldReader); +impl RBSA_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + RBSA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RBSA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RBSA` writer - Rx Buffer Start Address"] +pub struct RBSA_W<'a> { + w: &'a mut W, +} +impl<'a> RBSA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Rx Buffer Start Address"] + #[inline(always)] + pub fn rbsa(&self) -> RBSA_R { + RBSA_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Rx Buffer Start Address"] + #[inline(always)] + pub fn rbsa(&mut self) -> RBSA_W { + RBSA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Rx Buffer Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxbc](index.html) module"] +pub struct RXBC_SPEC; +impl crate::RegisterSpec for RXBC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rxbc::R](R) reader structure"] +impl crate::Readable for RXBC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rxbc::W](W) writer structure"] +impl crate::Writable for RXBC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RXBC to value 0"] +impl crate::Resettable for RXBC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/can0/rxesc.rs b/pac/atsamc21j/src/can0/rxesc.rs new file mode 100644 index 000000000000..b0a972eaf1f0 --- /dev/null +++ b/pac/atsamc21j/src/can0/rxesc.rs @@ -0,0 +1,558 @@ +#[doc = "Register `RXESC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RXESC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Rx FIFO 0 Data Field Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum F0DS_A { + #[doc = "0: 8 byte data field"] + DATA8 = 0, + #[doc = "1: 12 byte data field"] + DATA12 = 1, + #[doc = "2: 16 byte data field"] + DATA16 = 2, + #[doc = "3: 20 byte data field"] + DATA20 = 3, + #[doc = "4: 24 byte data field"] + DATA24 = 4, + #[doc = "5: 32 byte data field"] + DATA32 = 5, + #[doc = "6: 48 byte data field"] + DATA48 = 6, + #[doc = "7: 64 byte data field"] + DATA64 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: F0DS_A) -> Self { + variant as _ + } +} +#[doc = "Field `F0DS` reader - Rx FIFO 0 Data Field Size"] +pub struct F0DS_R(crate::FieldReader); +impl F0DS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + F0DS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> F0DS_A { + match self.bits { + 0 => F0DS_A::DATA8, + 1 => F0DS_A::DATA12, + 2 => F0DS_A::DATA16, + 3 => F0DS_A::DATA20, + 4 => F0DS_A::DATA24, + 5 => F0DS_A::DATA32, + 6 => F0DS_A::DATA48, + 7 => F0DS_A::DATA64, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DATA8`"] + #[inline(always)] + pub fn is_data8(&self) -> bool { + **self == F0DS_A::DATA8 + } + #[doc = "Checks if the value of the field is `DATA12`"] + #[inline(always)] + pub fn is_data12(&self) -> bool { + **self == F0DS_A::DATA12 + } + #[doc = "Checks if the value of the field is `DATA16`"] + #[inline(always)] + pub fn is_data16(&self) -> bool { + **self == F0DS_A::DATA16 + } + #[doc = "Checks if the value of the field is `DATA20`"] + #[inline(always)] + pub fn is_data20(&self) -> bool { + **self == F0DS_A::DATA20 + } + #[doc = "Checks if the value of the field is `DATA24`"] + #[inline(always)] + pub fn is_data24(&self) -> bool { + **self == F0DS_A::DATA24 + } + #[doc = "Checks if the value of the field is `DATA32`"] + #[inline(always)] + pub fn is_data32(&self) -> bool { + **self == F0DS_A::DATA32 + } + #[doc = "Checks if the value of the field is `DATA48`"] + #[inline(always)] + pub fn is_data48(&self) -> bool { + **self == F0DS_A::DATA48 + } + #[doc = "Checks if the value of the field is `DATA64`"] + #[inline(always)] + pub fn is_data64(&self) -> bool { + **self == F0DS_A::DATA64 + } +} +impl core::ops::Deref for F0DS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `F0DS` writer - Rx FIFO 0 Data Field Size"] +pub struct F0DS_W<'a> { + w: &'a mut W, +} +impl<'a> F0DS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: F0DS_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "8 byte data field"] + #[inline(always)] + pub fn data8(self) -> &'a mut W { + self.variant(F0DS_A::DATA8) + } + #[doc = "12 byte data field"] + #[inline(always)] + pub fn data12(self) -> &'a mut W { + self.variant(F0DS_A::DATA12) + } + #[doc = "16 byte data field"] + #[inline(always)] + pub fn data16(self) -> &'a mut W { + self.variant(F0DS_A::DATA16) + } + #[doc = "20 byte data field"] + #[inline(always)] + pub fn data20(self) -> &'a mut W { + self.variant(F0DS_A::DATA20) + } + #[doc = "24 byte data field"] + #[inline(always)] + pub fn data24(self) -> &'a mut W { + self.variant(F0DS_A::DATA24) + } + #[doc = "32 byte data field"] + #[inline(always)] + pub fn data32(self) -> &'a mut W { + self.variant(F0DS_A::DATA32) + } + #[doc = "48 byte data field"] + #[inline(always)] + pub fn data48(self) -> &'a mut W { + self.variant(F0DS_A::DATA48) + } + #[doc = "64 byte data field"] + #[inline(always)] + pub fn data64(self) -> &'a mut W { + self.variant(F0DS_A::DATA64) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Rx FIFO 1 Data Field Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum F1DS_A { + #[doc = "0: 8 byte data field"] + DATA8 = 0, + #[doc = "1: 12 byte data field"] + DATA12 = 1, + #[doc = "2: 16 byte data field"] + DATA16 = 2, + #[doc = "3: 20 byte data field"] + DATA20 = 3, + #[doc = "4: 24 byte data field"] + DATA24 = 4, + #[doc = "5: 32 byte data field"] + DATA32 = 5, + #[doc = "6: 48 byte data field"] + DATA48 = 6, + #[doc = "7: 64 byte data field"] + DATA64 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: F1DS_A) -> Self { + variant as _ + } +} +#[doc = "Field `F1DS` reader - Rx FIFO 1 Data Field Size"] +pub struct F1DS_R(crate::FieldReader); +impl F1DS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + F1DS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> F1DS_A { + match self.bits { + 0 => F1DS_A::DATA8, + 1 => F1DS_A::DATA12, + 2 => F1DS_A::DATA16, + 3 => F1DS_A::DATA20, + 4 => F1DS_A::DATA24, + 5 => F1DS_A::DATA32, + 6 => F1DS_A::DATA48, + 7 => F1DS_A::DATA64, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DATA8`"] + #[inline(always)] + pub fn is_data8(&self) -> bool { + **self == F1DS_A::DATA8 + } + #[doc = "Checks if the value of the field is `DATA12`"] + #[inline(always)] + pub fn is_data12(&self) -> bool { + **self == F1DS_A::DATA12 + } + #[doc = "Checks if the value of the field is `DATA16`"] + #[inline(always)] + pub fn is_data16(&self) -> bool { + **self == F1DS_A::DATA16 + } + #[doc = "Checks if the value of the field is `DATA20`"] + #[inline(always)] + pub fn is_data20(&self) -> bool { + **self == F1DS_A::DATA20 + } + #[doc = "Checks if the value of the field is `DATA24`"] + #[inline(always)] + pub fn is_data24(&self) -> bool { + **self == F1DS_A::DATA24 + } + #[doc = "Checks if the value of the field is `DATA32`"] + #[inline(always)] + pub fn is_data32(&self) -> bool { + **self == F1DS_A::DATA32 + } + #[doc = "Checks if the value of the field is `DATA48`"] + #[inline(always)] + pub fn is_data48(&self) -> bool { + **self == F1DS_A::DATA48 + } + #[doc = "Checks if the value of the field is `DATA64`"] + #[inline(always)] + pub fn is_data64(&self) -> bool { + **self == F1DS_A::DATA64 + } +} +impl core::ops::Deref for F1DS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `F1DS` writer - Rx FIFO 1 Data Field Size"] +pub struct F1DS_W<'a> { + w: &'a mut W, +} +impl<'a> F1DS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: F1DS_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "8 byte data field"] + #[inline(always)] + pub fn data8(self) -> &'a mut W { + self.variant(F1DS_A::DATA8) + } + #[doc = "12 byte data field"] + #[inline(always)] + pub fn data12(self) -> &'a mut W { + self.variant(F1DS_A::DATA12) + } + #[doc = "16 byte data field"] + #[inline(always)] + pub fn data16(self) -> &'a mut W { + self.variant(F1DS_A::DATA16) + } + #[doc = "20 byte data field"] + #[inline(always)] + pub fn data20(self) -> &'a mut W { + self.variant(F1DS_A::DATA20) + } + #[doc = "24 byte data field"] + #[inline(always)] + pub fn data24(self) -> &'a mut W { + self.variant(F1DS_A::DATA24) + } + #[doc = "32 byte data field"] + #[inline(always)] + pub fn data32(self) -> &'a mut W { + self.variant(F1DS_A::DATA32) + } + #[doc = "48 byte data field"] + #[inline(always)] + pub fn data48(self) -> &'a mut W { + self.variant(F1DS_A::DATA48) + } + #[doc = "64 byte data field"] + #[inline(always)] + pub fn data64(self) -> &'a mut W { + self.variant(F1DS_A::DATA64) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 4)) | ((value as u32 & 0x07) << 4); + self.w + } +} +#[doc = "Rx Buffer Data Field Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum RBDS_A { + #[doc = "0: 8 byte data field"] + DATA8 = 0, + #[doc = "1: 12 byte data field"] + DATA12 = 1, + #[doc = "2: 16 byte data field"] + DATA16 = 2, + #[doc = "3: 20 byte data field"] + DATA20 = 3, + #[doc = "4: 24 byte data field"] + DATA24 = 4, + #[doc = "5: 32 byte data field"] + DATA32 = 5, + #[doc = "6: 48 byte data field"] + DATA48 = 6, + #[doc = "7: 64 byte data field"] + DATA64 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RBDS_A) -> Self { + variant as _ + } +} +#[doc = "Field `RBDS` reader - Rx Buffer Data Field Size"] +pub struct RBDS_R(crate::FieldReader); +impl RBDS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RBDS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RBDS_A { + match self.bits { + 0 => RBDS_A::DATA8, + 1 => RBDS_A::DATA12, + 2 => RBDS_A::DATA16, + 3 => RBDS_A::DATA20, + 4 => RBDS_A::DATA24, + 5 => RBDS_A::DATA32, + 6 => RBDS_A::DATA48, + 7 => RBDS_A::DATA64, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DATA8`"] + #[inline(always)] + pub fn is_data8(&self) -> bool { + **self == RBDS_A::DATA8 + } + #[doc = "Checks if the value of the field is `DATA12`"] + #[inline(always)] + pub fn is_data12(&self) -> bool { + **self == RBDS_A::DATA12 + } + #[doc = "Checks if the value of the field is `DATA16`"] + #[inline(always)] + pub fn is_data16(&self) -> bool { + **self == RBDS_A::DATA16 + } + #[doc = "Checks if the value of the field is `DATA20`"] + #[inline(always)] + pub fn is_data20(&self) -> bool { + **self == RBDS_A::DATA20 + } + #[doc = "Checks if the value of the field is `DATA24`"] + #[inline(always)] + pub fn is_data24(&self) -> bool { + **self == RBDS_A::DATA24 + } + #[doc = "Checks if the value of the field is `DATA32`"] + #[inline(always)] + pub fn is_data32(&self) -> bool { + **self == RBDS_A::DATA32 + } + #[doc = "Checks if the value of the field is `DATA48`"] + #[inline(always)] + pub fn is_data48(&self) -> bool { + **self == RBDS_A::DATA48 + } + #[doc = "Checks if the value of the field is `DATA64`"] + #[inline(always)] + pub fn is_data64(&self) -> bool { + **self == RBDS_A::DATA64 + } +} +impl core::ops::Deref for RBDS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RBDS` writer - Rx Buffer Data Field Size"] +pub struct RBDS_W<'a> { + w: &'a mut W, +} +impl<'a> RBDS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RBDS_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "8 byte data field"] + #[inline(always)] + pub fn data8(self) -> &'a mut W { + self.variant(RBDS_A::DATA8) + } + #[doc = "12 byte data field"] + #[inline(always)] + pub fn data12(self) -> &'a mut W { + self.variant(RBDS_A::DATA12) + } + #[doc = "16 byte data field"] + #[inline(always)] + pub fn data16(self) -> &'a mut W { + self.variant(RBDS_A::DATA16) + } + #[doc = "20 byte data field"] + #[inline(always)] + pub fn data20(self) -> &'a mut W { + self.variant(RBDS_A::DATA20) + } + #[doc = "24 byte data field"] + #[inline(always)] + pub fn data24(self) -> &'a mut W { + self.variant(RBDS_A::DATA24) + } + #[doc = "32 byte data field"] + #[inline(always)] + pub fn data32(self) -> &'a mut W { + self.variant(RBDS_A::DATA32) + } + #[doc = "48 byte data field"] + #[inline(always)] + pub fn data48(self) -> &'a mut W { + self.variant(RBDS_A::DATA48) + } + #[doc = "64 byte data field"] + #[inline(always)] + pub fn data64(self) -> &'a mut W { + self.variant(RBDS_A::DATA64) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Rx FIFO 0 Data Field Size"] + #[inline(always)] + pub fn f0ds(&self) -> F0DS_R { + F0DS_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bits 4:6 - Rx FIFO 1 Data Field Size"] + #[inline(always)] + pub fn f1ds(&self) -> F1DS_R { + F1DS_R::new(((self.bits >> 4) & 0x07) as u8) + } + #[doc = "Bits 8:10 - Rx Buffer Data Field Size"] + #[inline(always)] + pub fn rbds(&self) -> RBDS_R { + RBDS_R::new(((self.bits >> 8) & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Rx FIFO 0 Data Field Size"] + #[inline(always)] + pub fn f0ds(&mut self) -> F0DS_W { + F0DS_W { w: self } + } + #[doc = "Bits 4:6 - Rx FIFO 1 Data Field Size"] + #[inline(always)] + pub fn f1ds(&mut self) -> F1DS_W { + F1DS_W { w: self } + } + #[doc = "Bits 8:10 - Rx Buffer Data Field Size"] + #[inline(always)] + pub fn rbds(&mut self) -> RBDS_W { + RBDS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Rx Buffer / FIFO Element Size Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxesc](index.html) module"] +pub struct RXESC_SPEC; +impl crate::RegisterSpec for RXESC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rxesc::R](R) reader structure"] +impl crate::Readable for RXESC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rxesc::W](W) writer structure"] +impl crate::Writable for RXESC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RXESC to value 0"] +impl crate::Resettable for RXESC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/can0/rxf0a.rs b/pac/atsamc21j/src/can0/rxf0a.rs new file mode 100644 index 000000000000..568144edf95d --- /dev/null +++ b/pac/atsamc21j/src/can0/rxf0a.rs @@ -0,0 +1,103 @@ +#[doc = "Register `RXF0A` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RXF0A` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `F0AI` reader - Rx FIFO 0 Acknowledge Index"] +pub struct F0AI_R(crate::FieldReader); +impl F0AI_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + F0AI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for F0AI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `F0AI` writer - Rx FIFO 0 Acknowledge Index"] +pub struct F0AI_W<'a> { + w: &'a mut W, +} +impl<'a> F0AI_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Rx FIFO 0 Acknowledge Index"] + #[inline(always)] + pub fn f0ai(&self) -> F0AI_R { + F0AI_R::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - Rx FIFO 0 Acknowledge Index"] + #[inline(always)] + pub fn f0ai(&mut self) -> F0AI_W { + F0AI_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Rx FIFO 0 Acknowledge\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxf0a](index.html) module"] +pub struct RXF0A_SPEC; +impl crate::RegisterSpec for RXF0A_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rxf0a::R](R) reader structure"] +impl crate::Readable for RXF0A_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rxf0a::W](W) writer structure"] +impl crate::Writable for RXF0A_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RXF0A to value 0"] +impl crate::Resettable for RXF0A_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/can0/rxf0c.rs b/pac/atsamc21j/src/can0/rxf0c.rs new file mode 100644 index 000000000000..a1e1def5881a --- /dev/null +++ b/pac/atsamc21j/src/can0/rxf0c.rs @@ -0,0 +1,224 @@ +#[doc = "Register `RXF0C` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RXF0C` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `F0SA` reader - Rx FIFO 0 Start Address"] +pub struct F0SA_R(crate::FieldReader); +impl F0SA_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + F0SA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for F0SA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `F0SA` writer - Rx FIFO 0 Start Address"] +pub struct F0SA_W<'a> { + w: &'a mut W, +} +impl<'a> F0SA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +#[doc = "Field `F0S` reader - Rx FIFO 0 Size"] +pub struct F0S_R(crate::FieldReader); +impl F0S_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + F0S_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for F0S_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `F0S` writer - Rx FIFO 0 Size"] +pub struct F0S_W<'a> { + w: &'a mut W, +} +impl<'a> F0S_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x7f << 16)) | ((value as u32 & 0x7f) << 16); + self.w + } +} +#[doc = "Field `F0WM` reader - Rx FIFO 0 Watermark"] +pub struct F0WM_R(crate::FieldReader); +impl F0WM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + F0WM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for F0WM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `F0WM` writer - Rx FIFO 0 Watermark"] +pub struct F0WM_W<'a> { + w: &'a mut W, +} +impl<'a> F0WM_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x7f << 24)) | ((value as u32 & 0x7f) << 24); + self.w + } +} +#[doc = "Field `F0OM` reader - FIFO 0 Operation Mode"] +pub struct F0OM_R(crate::FieldReader); +impl F0OM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + F0OM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for F0OM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `F0OM` writer - FIFO 0 Operation Mode"] +pub struct F0OM_W<'a> { + w: &'a mut W, +} +impl<'a> F0OM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Rx FIFO 0 Start Address"] + #[inline(always)] + pub fn f0sa(&self) -> F0SA_R { + F0SA_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:22 - Rx FIFO 0 Size"] + #[inline(always)] + pub fn f0s(&self) -> F0S_R { + F0S_R::new(((self.bits >> 16) & 0x7f) as u8) + } + #[doc = "Bits 24:30 - Rx FIFO 0 Watermark"] + #[inline(always)] + pub fn f0wm(&self) -> F0WM_R { + F0WM_R::new(((self.bits >> 24) & 0x7f) as u8) + } + #[doc = "Bit 31 - FIFO 0 Operation Mode"] + #[inline(always)] + pub fn f0om(&self) -> F0OM_R { + F0OM_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Rx FIFO 0 Start Address"] + #[inline(always)] + pub fn f0sa(&mut self) -> F0SA_W { + F0SA_W { w: self } + } + #[doc = "Bits 16:22 - Rx FIFO 0 Size"] + #[inline(always)] + pub fn f0s(&mut self) -> F0S_W { + F0S_W { w: self } + } + #[doc = "Bits 24:30 - Rx FIFO 0 Watermark"] + #[inline(always)] + pub fn f0wm(&mut self) -> F0WM_W { + F0WM_W { w: self } + } + #[doc = "Bit 31 - FIFO 0 Operation Mode"] + #[inline(always)] + pub fn f0om(&mut self) -> F0OM_W { + F0OM_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Rx FIFO 0 Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxf0c](index.html) module"] +pub struct RXF0C_SPEC; +impl crate::RegisterSpec for RXF0C_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rxf0c::R](R) reader structure"] +impl crate::Readable for RXF0C_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rxf0c::W](W) writer structure"] +impl crate::Writable for RXF0C_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RXF0C to value 0"] +impl crate::Resettable for RXF0C_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/can0/rxf0s.rs b/pac/atsamc21j/src/can0/rxf0s.rs new file mode 100644 index 000000000000..c26ef5fed347 --- /dev/null +++ b/pac/atsamc21j/src/can0/rxf0s.rs @@ -0,0 +1,133 @@ +#[doc = "Register `RXF0S` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `F0FL` reader - Rx FIFO 0 Fill Level"] +pub struct F0FL_R(crate::FieldReader); +impl F0FL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + F0FL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for F0FL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `F0GI` reader - Rx FIFO 0 Get Index"] +pub struct F0GI_R(crate::FieldReader); +impl F0GI_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + F0GI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for F0GI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `F0PI` reader - Rx FIFO 0 Put Index"] +pub struct F0PI_R(crate::FieldReader); +impl F0PI_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + F0PI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for F0PI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `F0F` reader - Rx FIFO 0 Full"] +pub struct F0F_R(crate::FieldReader); +impl F0F_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + F0F_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for F0F_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF0L` reader - Rx FIFO 0 Message Lost"] +pub struct RF0L_R(crate::FieldReader); +impl RF0L_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF0L_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF0L_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:6 - Rx FIFO 0 Fill Level"] + #[inline(always)] + pub fn f0fl(&self) -> F0FL_R { + F0FL_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bits 8:13 - Rx FIFO 0 Get Index"] + #[inline(always)] + pub fn f0gi(&self) -> F0GI_R { + F0GI_R::new(((self.bits >> 8) & 0x3f) as u8) + } + #[doc = "Bits 16:21 - Rx FIFO 0 Put Index"] + #[inline(always)] + pub fn f0pi(&self) -> F0PI_R { + F0PI_R::new(((self.bits >> 16) & 0x3f) as u8) + } + #[doc = "Bit 24 - Rx FIFO 0 Full"] + #[inline(always)] + pub fn f0f(&self) -> F0F_R { + F0F_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Rx FIFO 0 Message Lost"] + #[inline(always)] + pub fn rf0l(&self) -> RF0L_R { + RF0L_R::new(((self.bits >> 25) & 0x01) != 0) + } +} +#[doc = "Rx FIFO 0 Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxf0s](index.html) module"] +pub struct RXF0S_SPEC; +impl crate::RegisterSpec for RXF0S_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rxf0s::R](R) reader structure"] +impl crate::Readable for RXF0S_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets RXF0S to value 0"] +impl crate::Resettable for RXF0S_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/can0/rxf1a.rs b/pac/atsamc21j/src/can0/rxf1a.rs new file mode 100644 index 000000000000..56b074f7f444 --- /dev/null +++ b/pac/atsamc21j/src/can0/rxf1a.rs @@ -0,0 +1,103 @@ +#[doc = "Register `RXF1A` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RXF1A` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `F1AI` reader - Rx FIFO 1 Acknowledge Index"] +pub struct F1AI_R(crate::FieldReader); +impl F1AI_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + F1AI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for F1AI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `F1AI` writer - Rx FIFO 1 Acknowledge Index"] +pub struct F1AI_W<'a> { + w: &'a mut W, +} +impl<'a> F1AI_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Rx FIFO 1 Acknowledge Index"] + #[inline(always)] + pub fn f1ai(&self) -> F1AI_R { + F1AI_R::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - Rx FIFO 1 Acknowledge Index"] + #[inline(always)] + pub fn f1ai(&mut self) -> F1AI_W { + F1AI_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Rx FIFO 1 Acknowledge\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxf1a](index.html) module"] +pub struct RXF1A_SPEC; +impl crate::RegisterSpec for RXF1A_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rxf1a::R](R) reader structure"] +impl crate::Readable for RXF1A_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rxf1a::W](W) writer structure"] +impl crate::Writable for RXF1A_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RXF1A to value 0"] +impl crate::Resettable for RXF1A_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/can0/rxf1c.rs b/pac/atsamc21j/src/can0/rxf1c.rs new file mode 100644 index 000000000000..c9e23925c0c8 --- /dev/null +++ b/pac/atsamc21j/src/can0/rxf1c.rs @@ -0,0 +1,224 @@ +#[doc = "Register `RXF1C` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RXF1C` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `F1SA` reader - Rx FIFO 1 Start Address"] +pub struct F1SA_R(crate::FieldReader); +impl F1SA_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + F1SA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for F1SA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `F1SA` writer - Rx FIFO 1 Start Address"] +pub struct F1SA_W<'a> { + w: &'a mut W, +} +impl<'a> F1SA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +#[doc = "Field `F1S` reader - Rx FIFO 1 Size"] +pub struct F1S_R(crate::FieldReader); +impl F1S_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + F1S_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for F1S_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `F1S` writer - Rx FIFO 1 Size"] +pub struct F1S_W<'a> { + w: &'a mut W, +} +impl<'a> F1S_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x7f << 16)) | ((value as u32 & 0x7f) << 16); + self.w + } +} +#[doc = "Field `F1WM` reader - Rx FIFO 1 Watermark"] +pub struct F1WM_R(crate::FieldReader); +impl F1WM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + F1WM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for F1WM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `F1WM` writer - Rx FIFO 1 Watermark"] +pub struct F1WM_W<'a> { + w: &'a mut W, +} +impl<'a> F1WM_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x7f << 24)) | ((value as u32 & 0x7f) << 24); + self.w + } +} +#[doc = "Field `F1OM` reader - FIFO 1 Operation Mode"] +pub struct F1OM_R(crate::FieldReader); +impl F1OM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + F1OM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for F1OM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `F1OM` writer - FIFO 1 Operation Mode"] +pub struct F1OM_W<'a> { + w: &'a mut W, +} +impl<'a> F1OM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Rx FIFO 1 Start Address"] + #[inline(always)] + pub fn f1sa(&self) -> F1SA_R { + F1SA_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:22 - Rx FIFO 1 Size"] + #[inline(always)] + pub fn f1s(&self) -> F1S_R { + F1S_R::new(((self.bits >> 16) & 0x7f) as u8) + } + #[doc = "Bits 24:30 - Rx FIFO 1 Watermark"] + #[inline(always)] + pub fn f1wm(&self) -> F1WM_R { + F1WM_R::new(((self.bits >> 24) & 0x7f) as u8) + } + #[doc = "Bit 31 - FIFO 1 Operation Mode"] + #[inline(always)] + pub fn f1om(&self) -> F1OM_R { + F1OM_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Rx FIFO 1 Start Address"] + #[inline(always)] + pub fn f1sa(&mut self) -> F1SA_W { + F1SA_W { w: self } + } + #[doc = "Bits 16:22 - Rx FIFO 1 Size"] + #[inline(always)] + pub fn f1s(&mut self) -> F1S_W { + F1S_W { w: self } + } + #[doc = "Bits 24:30 - Rx FIFO 1 Watermark"] + #[inline(always)] + pub fn f1wm(&mut self) -> F1WM_W { + F1WM_W { w: self } + } + #[doc = "Bit 31 - FIFO 1 Operation Mode"] + #[inline(always)] + pub fn f1om(&mut self) -> F1OM_W { + F1OM_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Rx FIFO 1 Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxf1c](index.html) module"] +pub struct RXF1C_SPEC; +impl crate::RegisterSpec for RXF1C_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rxf1c::R](R) reader structure"] +impl crate::Readable for RXF1C_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rxf1c::W](W) writer structure"] +impl crate::Writable for RXF1C_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RXF1C to value 0"] +impl crate::Resettable for RXF1C_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/can0/rxf1s.rs b/pac/atsamc21j/src/can0/rxf1s.rs new file mode 100644 index 000000000000..7005a3339afb --- /dev/null +++ b/pac/atsamc21j/src/can0/rxf1s.rs @@ -0,0 +1,203 @@ +#[doc = "Register `RXF1S` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `F1FL` reader - Rx FIFO 1 Fill Level"] +pub struct F1FL_R(crate::FieldReader); +impl F1FL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + F1FL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for F1FL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `F1GI` reader - Rx FIFO 1 Get Index"] +pub struct F1GI_R(crate::FieldReader); +impl F1GI_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + F1GI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for F1GI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `F1PI` reader - Rx FIFO 1 Put Index"] +pub struct F1PI_R(crate::FieldReader); +impl F1PI_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + F1PI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for F1PI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `F1F` reader - Rx FIFO 1 Full"] +pub struct F1F_R(crate::FieldReader); +impl F1F_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + F1F_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for F1F_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF1L` reader - Rx FIFO 1 Message Lost"] +pub struct RF1L_R(crate::FieldReader); +impl RF1L_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF1L_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF1L_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Debug Message Status\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DMS_A { + #[doc = "0: Idle state"] + IDLE = 0, + #[doc = "1: Debug message A received"] + DBGA = 1, + #[doc = "2: Debug message A/B received"] + DBGB = 2, + #[doc = "3: Debug message A/B/C received, DMA request set"] + DBGC = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DMS_A) -> Self { + variant as _ + } +} +#[doc = "Field `DMS` reader - Debug Message Status"] +pub struct DMS_R(crate::FieldReader); +impl DMS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DMS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DMS_A { + match self.bits { + 0 => DMS_A::IDLE, + 1 => DMS_A::DBGA, + 2 => DMS_A::DBGB, + 3 => DMS_A::DBGC, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `IDLE`"] + #[inline(always)] + pub fn is_idle(&self) -> bool { + **self == DMS_A::IDLE + } + #[doc = "Checks if the value of the field is `DBGA`"] + #[inline(always)] + pub fn is_dbga(&self) -> bool { + **self == DMS_A::DBGA + } + #[doc = "Checks if the value of the field is `DBGB`"] + #[inline(always)] + pub fn is_dbgb(&self) -> bool { + **self == DMS_A::DBGB + } + #[doc = "Checks if the value of the field is `DBGC`"] + #[inline(always)] + pub fn is_dbgc(&self) -> bool { + **self == DMS_A::DBGC + } +} +impl core::ops::Deref for DMS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:6 - Rx FIFO 1 Fill Level"] + #[inline(always)] + pub fn f1fl(&self) -> F1FL_R { + F1FL_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bits 8:13 - Rx FIFO 1 Get Index"] + #[inline(always)] + pub fn f1gi(&self) -> F1GI_R { + F1GI_R::new(((self.bits >> 8) & 0x3f) as u8) + } + #[doc = "Bits 16:21 - Rx FIFO 1 Put Index"] + #[inline(always)] + pub fn f1pi(&self) -> F1PI_R { + F1PI_R::new(((self.bits >> 16) & 0x3f) as u8) + } + #[doc = "Bit 24 - Rx FIFO 1 Full"] + #[inline(always)] + pub fn f1f(&self) -> F1F_R { + F1F_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Rx FIFO 1 Message Lost"] + #[inline(always)] + pub fn rf1l(&self) -> RF1L_R { + RF1L_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bits 30:31 - Debug Message Status"] + #[inline(always)] + pub fn dms(&self) -> DMS_R { + DMS_R::new(((self.bits >> 30) & 0x03) as u8) + } +} +#[doc = "Rx FIFO 1 Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxf1s](index.html) module"] +pub struct RXF1S_SPEC; +impl crate::RegisterSpec for RXF1S_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rxf1s::R](R) reader structure"] +impl crate::Readable for RXF1S_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets RXF1S to value 0"] +impl crate::Resettable for RXF1S_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/can0/sidfc.rs b/pac/atsamc21j/src/can0/sidfc.rs new file mode 100644 index 000000000000..95a73efe426a --- /dev/null +++ b/pac/atsamc21j/src/can0/sidfc.rs @@ -0,0 +1,140 @@ +#[doc = "Register `SIDFC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SIDFC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FLSSA` reader - Filter List Standard Start Address"] +pub struct FLSSA_R(crate::FieldReader); +impl FLSSA_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + FLSSA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FLSSA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLSSA` writer - Filter List Standard Start Address"] +pub struct FLSSA_W<'a> { + w: &'a mut W, +} +impl<'a> FLSSA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +#[doc = "Field `LSS` reader - List Size Standard"] +pub struct LSS_R(crate::FieldReader); +impl LSS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LSS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LSS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LSS` writer - List Size Standard"] +pub struct LSS_W<'a> { + w: &'a mut W, +} +impl<'a> LSS_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Filter List Standard Start Address"] + #[inline(always)] + pub fn flssa(&self) -> FLSSA_R { + FLSSA_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:23 - List Size Standard"] + #[inline(always)] + pub fn lss(&self) -> LSS_R { + LSS_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:15 - Filter List Standard Start Address"] + #[inline(always)] + pub fn flssa(&mut self) -> FLSSA_W { + FLSSA_W { w: self } + } + #[doc = "Bits 16:23 - List Size Standard"] + #[inline(always)] + pub fn lss(&mut self) -> LSS_W { + LSS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Standard ID Filter Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sidfc](index.html) module"] +pub struct SIDFC_SPEC; +impl crate::RegisterSpec for SIDFC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [sidfc::R](R) reader structure"] +impl crate::Readable for SIDFC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [sidfc::W](W) writer structure"] +impl crate::Writable for SIDFC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SIDFC to value 0"] +impl crate::Resettable for SIDFC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/can0/tdcr.rs b/pac/atsamc21j/src/can0/tdcr.rs new file mode 100644 index 000000000000..0cec58f98e28 --- /dev/null +++ b/pac/atsamc21j/src/can0/tdcr.rs @@ -0,0 +1,140 @@ +#[doc = "Register `TDCR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TDCR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TDCF` reader - Transmitter Delay Compensation Filter Length"] +pub struct TDCF_R(crate::FieldReader); +impl TDCF_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TDCF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TDCF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TDCF` writer - Transmitter Delay Compensation Filter Length"] +pub struct TDCF_W<'a> { + w: &'a mut W, +} +impl<'a> TDCF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x7f) | (value as u32 & 0x7f); + self.w + } +} +#[doc = "Field `TDCO` reader - Transmitter Delay Compensation Offset"] +pub struct TDCO_R(crate::FieldReader); +impl TDCO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TDCO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TDCO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TDCO` writer - Transmitter Delay Compensation Offset"] +pub struct TDCO_W<'a> { + w: &'a mut W, +} +impl<'a> TDCO_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x7f << 8)) | ((value as u32 & 0x7f) << 8); + self.w + } +} +impl R { + #[doc = "Bits 0:6 - Transmitter Delay Compensation Filter Length"] + #[inline(always)] + pub fn tdcf(&self) -> TDCF_R { + TDCF_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bits 8:14 - Transmitter Delay Compensation Offset"] + #[inline(always)] + pub fn tdco(&self) -> TDCO_R { + TDCO_R::new(((self.bits >> 8) & 0x7f) as u8) + } +} +impl W { + #[doc = "Bits 0:6 - Transmitter Delay Compensation Filter Length"] + #[inline(always)] + pub fn tdcf(&mut self) -> TDCF_W { + TDCF_W { w: self } + } + #[doc = "Bits 8:14 - Transmitter Delay Compensation Offset"] + #[inline(always)] + pub fn tdco(&mut self) -> TDCO_W { + TDCO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Extended ID Filter Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tdcr](index.html) module"] +pub struct TDCR_SPEC; +impl crate::RegisterSpec for TDCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [tdcr::R](R) reader structure"] +impl crate::Readable for TDCR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [tdcr::W](W) writer structure"] +impl crate::Writable for TDCR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TDCR to value 0"] +impl crate::Resettable for TDCR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/can0/test.rs b/pac/atsamc21j/src/can0/test.rs new file mode 100644 index 000000000000..fe1417a03d90 --- /dev/null +++ b/pac/atsamc21j/src/can0/test.rs @@ -0,0 +1,272 @@ +#[doc = "Register `TEST` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TEST` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `LBCK` reader - Loop Back Mode"] +pub struct LBCK_R(crate::FieldReader); +impl LBCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LBCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LBCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LBCK` writer - Loop Back Mode"] +pub struct LBCK_W<'a> { + w: &'a mut W, +} +impl<'a> LBCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Control of Transmit Pin\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum TX_A { + #[doc = "0: TX controlled by CAN core"] + CORE = 0, + #[doc = "1: TX monitoring sample point"] + SAMPLE = 1, + #[doc = "2: Dominant (0) level at pin CAN_TX"] + DOMINANT = 2, + #[doc = "3: Recessive (1) level at pin CAN_TX"] + RECESSIVE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: TX_A) -> Self { + variant as _ + } +} +#[doc = "Field `TX` reader - Control of Transmit Pin"] +pub struct TX_R(crate::FieldReader); +impl TX_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TX_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TX_A { + match self.bits { + 0 => TX_A::CORE, + 1 => TX_A::SAMPLE, + 2 => TX_A::DOMINANT, + 3 => TX_A::RECESSIVE, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `CORE`"] + #[inline(always)] + pub fn is_core(&self) -> bool { + **self == TX_A::CORE + } + #[doc = "Checks if the value of the field is `SAMPLE`"] + #[inline(always)] + pub fn is_sample(&self) -> bool { + **self == TX_A::SAMPLE + } + #[doc = "Checks if the value of the field is `DOMINANT`"] + #[inline(always)] + pub fn is_dominant(&self) -> bool { + **self == TX_A::DOMINANT + } + #[doc = "Checks if the value of the field is `RECESSIVE`"] + #[inline(always)] + pub fn is_recessive(&self) -> bool { + **self == TX_A::RECESSIVE + } +} +impl core::ops::Deref for TX_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TX` writer - Control of Transmit Pin"] +pub struct TX_W<'a> { + w: &'a mut W, +} +impl<'a> TX_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TX_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "TX controlled by CAN core"] + #[inline(always)] + pub fn core(self) -> &'a mut W { + self.variant(TX_A::CORE) + } + #[doc = "TX monitoring sample point"] + #[inline(always)] + pub fn sample(self) -> &'a mut W { + self.variant(TX_A::SAMPLE) + } + #[doc = "Dominant (0) level at pin CAN_TX"] + #[inline(always)] + pub fn dominant(self) -> &'a mut W { + self.variant(TX_A::DOMINANT) + } + #[doc = "Recessive (1) level at pin CAN_TX"] + #[inline(always)] + pub fn recessive(self) -> &'a mut W { + self.variant(TX_A::RECESSIVE) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 5)) | ((value as u32 & 0x03) << 5); + self.w + } +} +#[doc = "Field `RX` reader - Receive Pin"] +pub struct RX_R(crate::FieldReader); +impl RX_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RX_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RX_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RX` writer - Receive Pin"] +pub struct RX_W<'a> { + w: &'a mut W, +} +impl<'a> RX_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 4 - Loop Back Mode"] + #[inline(always)] + pub fn lbck(&self) -> LBCK_R { + LBCK_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bits 5:6 - Control of Transmit Pin"] + #[inline(always)] + pub fn tx(&self) -> TX_R { + TX_R::new(((self.bits >> 5) & 0x03) as u8) + } + #[doc = "Bit 7 - Receive Pin"] + #[inline(always)] + pub fn rx(&self) -> RX_R { + RX_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 4 - Loop Back Mode"] + #[inline(always)] + pub fn lbck(&mut self) -> LBCK_W { + LBCK_W { w: self } + } + #[doc = "Bits 5:6 - Control of Transmit Pin"] + #[inline(always)] + pub fn tx(&mut self) -> TX_W { + TX_W { w: self } + } + #[doc = "Bit 7 - Receive Pin"] + #[inline(always)] + pub fn rx(&mut self) -> RX_W { + RX_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Test\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [test](index.html) module"] +pub struct TEST_SPEC; +impl crate::RegisterSpec for TEST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [test::R](R) reader structure"] +impl crate::Readable for TEST_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [test::W](W) writer structure"] +impl crate::Writable for TEST_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TEST to value 0"] +impl crate::Resettable for TEST_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/can0/tocc.rs b/pac/atsamc21j/src/can0/tocc.rs new file mode 100644 index 000000000000..fa64916ef75f --- /dev/null +++ b/pac/atsamc21j/src/can0/tocc.rs @@ -0,0 +1,262 @@ +#[doc = "Register `TOCC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TOCC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ETOC` reader - Enable Timeout Counter"] +pub struct ETOC_R(crate::FieldReader); +impl ETOC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ETOC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ETOC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ETOC` writer - Enable Timeout Counter"] +pub struct ETOC_W<'a> { + w: &'a mut W, +} +impl<'a> ETOC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Timeout Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum TOS_A { + #[doc = "0: Continuout operation"] + CONT = 0, + #[doc = "1: Timeout controlled by TX Event FIFO"] + TXEF = 1, + #[doc = "2: Timeout controlled by Rx FIFO 0"] + RXF0 = 2, + #[doc = "3: Timeout controlled by Rx FIFO 1"] + RXF1 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: TOS_A) -> Self { + variant as _ + } +} +#[doc = "Field `TOS` reader - Timeout Select"] +pub struct TOS_R(crate::FieldReader); +impl TOS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TOS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TOS_A { + match self.bits { + 0 => TOS_A::CONT, + 1 => TOS_A::TXEF, + 2 => TOS_A::RXF0, + 3 => TOS_A::RXF1, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `CONT`"] + #[inline(always)] + pub fn is_cont(&self) -> bool { + **self == TOS_A::CONT + } + #[doc = "Checks if the value of the field is `TXEF`"] + #[inline(always)] + pub fn is_txef(&self) -> bool { + **self == TOS_A::TXEF + } + #[doc = "Checks if the value of the field is `RXF0`"] + #[inline(always)] + pub fn is_rxf0(&self) -> bool { + **self == TOS_A::RXF0 + } + #[doc = "Checks if the value of the field is `RXF1`"] + #[inline(always)] + pub fn is_rxf1(&self) -> bool { + **self == TOS_A::RXF1 + } +} +impl core::ops::Deref for TOS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TOS` writer - Timeout Select"] +pub struct TOS_W<'a> { + w: &'a mut W, +} +impl<'a> TOS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TOS_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Continuout operation"] + #[inline(always)] + pub fn cont(self) -> &'a mut W { + self.variant(TOS_A::CONT) + } + #[doc = "Timeout controlled by TX Event FIFO"] + #[inline(always)] + pub fn txef(self) -> &'a mut W { + self.variant(TOS_A::TXEF) + } + #[doc = "Timeout controlled by Rx FIFO 0"] + #[inline(always)] + pub fn rxf0(self) -> &'a mut W { + self.variant(TOS_A::RXF0) + } + #[doc = "Timeout controlled by Rx FIFO 1"] + #[inline(always)] + pub fn rxf1(self) -> &'a mut W { + self.variant(TOS_A::RXF1) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 1)) | ((value as u32 & 0x03) << 1); + self.w + } +} +#[doc = "Field `TOP` reader - Timeout Period"] +pub struct TOP_R(crate::FieldReader); +impl TOP_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + TOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TOP` writer - Timeout Period"] +pub struct TOP_W<'a> { + w: &'a mut W, +} +impl<'a> TOP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xffff << 16)) | ((value as u32 & 0xffff) << 16); + self.w + } +} +impl R { + #[doc = "Bit 0 - Enable Timeout Counter"] + #[inline(always)] + pub fn etoc(&self) -> ETOC_R { + ETOC_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bits 1:2 - Timeout Select"] + #[inline(always)] + pub fn tos(&self) -> TOS_R { + TOS_R::new(((self.bits >> 1) & 0x03) as u8) + } + #[doc = "Bits 16:31 - Timeout Period"] + #[inline(always)] + pub fn top(&self) -> TOP_R { + TOP_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bit 0 - Enable Timeout Counter"] + #[inline(always)] + pub fn etoc(&mut self) -> ETOC_W { + ETOC_W { w: self } + } + #[doc = "Bits 1:2 - Timeout Select"] + #[inline(always)] + pub fn tos(&mut self) -> TOS_W { + TOS_W { w: self } + } + #[doc = "Bits 16:31 - Timeout Period"] + #[inline(always)] + pub fn top(&mut self) -> TOP_W { + TOP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Timeout Counter Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tocc](index.html) module"] +pub struct TOCC_SPEC; +impl crate::RegisterSpec for TOCC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [tocc::R](R) reader structure"] +impl crate::Readable for TOCC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [tocc::W](W) writer structure"] +impl crate::Writable for TOCC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TOCC to value 0xffff_0000"] +impl crate::Resettable for TOCC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_0000 + } +} diff --git a/pac/atsamc21j/src/can0/tocv.rs b/pac/atsamc21j/src/can0/tocv.rs new file mode 100644 index 000000000000..f49b24ce65bf --- /dev/null +++ b/pac/atsamc21j/src/can0/tocv.rs @@ -0,0 +1,103 @@ +#[doc = "Register `TOCV` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TOCV` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TOC` reader - Timeout Counter"] +pub struct TOC_R(crate::FieldReader); +impl TOC_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + TOC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TOC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TOC` writer - Timeout Counter"] +pub struct TOC_W<'a> { + w: &'a mut W, +} +impl<'a> TOC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Timeout Counter"] + #[inline(always)] + pub fn toc(&self) -> TOC_R { + TOC_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Timeout Counter"] + #[inline(always)] + pub fn toc(&mut self) -> TOC_W { + TOC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Timeout Counter Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tocv](index.html) module"] +pub struct TOCV_SPEC; +impl crate::RegisterSpec for TOCV_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [tocv::R](R) reader structure"] +impl crate::Readable for TOCV_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [tocv::W](W) writer structure"] +impl crate::Writable for TOCV_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TOCV to value 0xffff"] +impl crate::Resettable for TOCV_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff + } +} diff --git a/pac/atsamc21j/src/can0/tscc.rs b/pac/atsamc21j/src/can0/tscc.rs new file mode 100644 index 000000000000..298084cc06b8 --- /dev/null +++ b/pac/atsamc21j/src/can0/tscc.rs @@ -0,0 +1,202 @@ +#[doc = "Register `TSCC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TSCC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Timestamp Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum TSS_A { + #[doc = "0: Timestamp counter value always 0x0000"] + ZERO = 0, + #[doc = "1: Timestamp counter value incremented by TCP"] + INC = 1, + #[doc = "2: External timestamp counter value used"] + EXT = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: TSS_A) -> Self { + variant as _ + } +} +#[doc = "Field `TSS` reader - Timestamp Select"] +pub struct TSS_R(crate::FieldReader); +impl TSS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TSS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(TSS_A::ZERO), + 1 => Some(TSS_A::INC), + 2 => Some(TSS_A::EXT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `ZERO`"] + #[inline(always)] + pub fn is_zero(&self) -> bool { + **self == TSS_A::ZERO + } + #[doc = "Checks if the value of the field is `INC`"] + #[inline(always)] + pub fn is_inc(&self) -> bool { + **self == TSS_A::INC + } + #[doc = "Checks if the value of the field is `EXT`"] + #[inline(always)] + pub fn is_ext(&self) -> bool { + **self == TSS_A::EXT + } +} +impl core::ops::Deref for TSS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSS` writer - Timestamp Select"] +pub struct TSS_W<'a> { + w: &'a mut W, +} +impl<'a> TSS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TSS_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Timestamp counter value always 0x0000"] + #[inline(always)] + pub fn zero(self) -> &'a mut W { + self.variant(TSS_A::ZERO) + } + #[doc = "Timestamp counter value incremented by TCP"] + #[inline(always)] + pub fn inc(self) -> &'a mut W { + self.variant(TSS_A::INC) + } + #[doc = "External timestamp counter value used"] + #[inline(always)] + pub fn ext(self) -> &'a mut W { + self.variant(TSS_A::EXT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u32 & 0x03); + self.w + } +} +#[doc = "Field `TCP` reader - Timestamp Counter Prescaler"] +pub struct TCP_R(crate::FieldReader); +impl TCP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TCP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCP` writer - Timestamp Counter Prescaler"] +pub struct TCP_W<'a> { + w: &'a mut W, +} +impl<'a> TCP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 16)) | ((value as u32 & 0x0f) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Timestamp Select"] + #[inline(always)] + pub fn tss(&self) -> TSS_R { + TSS_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bits 16:19 - Timestamp Counter Prescaler"] + #[inline(always)] + pub fn tcp(&self) -> TCP_R { + TCP_R::new(((self.bits >> 16) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Timestamp Select"] + #[inline(always)] + pub fn tss(&mut self) -> TSS_W { + TSS_W { w: self } + } + #[doc = "Bits 16:19 - Timestamp Counter Prescaler"] + #[inline(always)] + pub fn tcp(&mut self) -> TCP_W { + TCP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Timestamp Counter Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tscc](index.html) module"] +pub struct TSCC_SPEC; +impl crate::RegisterSpec for TSCC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [tscc::R](R) reader structure"] +impl crate::Readable for TSCC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [tscc::W](W) writer structure"] +impl crate::Writable for TSCC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TSCC to value 0"] +impl crate::Resettable for TSCC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/can0/tscv.rs b/pac/atsamc21j/src/can0/tscv.rs new file mode 100644 index 000000000000..7ba4561d588f --- /dev/null +++ b/pac/atsamc21j/src/can0/tscv.rs @@ -0,0 +1,53 @@ +#[doc = "Register `TSCV` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `TSC` reader - Timestamp Counter"] +pub struct TSC_R(crate::FieldReader); +impl TSC_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + TSC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:15 - Timestamp Counter"] + #[inline(always)] + pub fn tsc(&self) -> TSC_R { + TSC_R::new((self.bits & 0xffff) as u16) + } +} +#[doc = "Timestamp Counter Value\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tscv](index.html) module"] +pub struct TSCV_SPEC; +impl crate::RegisterSpec for TSCV_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [tscv::R](R) reader structure"] +impl crate::Readable for TSCV_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets TSCV to value 0"] +impl crate::Resettable for TSCV_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/can0/txbar.rs b/pac/atsamc21j/src/can0/txbar.rs new file mode 100644 index 000000000000..bd15a3f2bd29 --- /dev/null +++ b/pac/atsamc21j/src/can0/txbar.rs @@ -0,0 +1,1570 @@ +#[doc = "Register `TXBAR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TXBAR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `AR0` reader - Add Request 0"] +pub struct AR0_R(crate::FieldReader); +impl AR0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR0` writer - Add Request 0"] +pub struct AR0_W<'a> { + w: &'a mut W, +} +impl<'a> AR0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `AR1` reader - Add Request 1"] +pub struct AR1_R(crate::FieldReader); +impl AR1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR1` writer - Add Request 1"] +pub struct AR1_W<'a> { + w: &'a mut W, +} +impl<'a> AR1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `AR2` reader - Add Request 2"] +pub struct AR2_R(crate::FieldReader); +impl AR2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR2` writer - Add Request 2"] +pub struct AR2_W<'a> { + w: &'a mut W, +} +impl<'a> AR2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `AR3` reader - Add Request 3"] +pub struct AR3_R(crate::FieldReader); +impl AR3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR3` writer - Add Request 3"] +pub struct AR3_W<'a> { + w: &'a mut W, +} +impl<'a> AR3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `AR4` reader - Add Request 4"] +pub struct AR4_R(crate::FieldReader); +impl AR4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR4` writer - Add Request 4"] +pub struct AR4_W<'a> { + w: &'a mut W, +} +impl<'a> AR4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `AR5` reader - Add Request 5"] +pub struct AR5_R(crate::FieldReader); +impl AR5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR5` writer - Add Request 5"] +pub struct AR5_W<'a> { + w: &'a mut W, +} +impl<'a> AR5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `AR6` reader - Add Request 6"] +pub struct AR6_R(crate::FieldReader); +impl AR6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR6` writer - Add Request 6"] +pub struct AR6_W<'a> { + w: &'a mut W, +} +impl<'a> AR6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `AR7` reader - Add Request 7"] +pub struct AR7_R(crate::FieldReader); +impl AR7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR7` writer - Add Request 7"] +pub struct AR7_W<'a> { + w: &'a mut W, +} +impl<'a> AR7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `AR8` reader - Add Request 8"] +pub struct AR8_R(crate::FieldReader); +impl AR8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR8` writer - Add Request 8"] +pub struct AR8_W<'a> { + w: &'a mut W, +} +impl<'a> AR8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `AR9` reader - Add Request 9"] +pub struct AR9_R(crate::FieldReader); +impl AR9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR9` writer - Add Request 9"] +pub struct AR9_W<'a> { + w: &'a mut W, +} +impl<'a> AR9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `AR10` reader - Add Request 10"] +pub struct AR10_R(crate::FieldReader); +impl AR10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR10` writer - Add Request 10"] +pub struct AR10_W<'a> { + w: &'a mut W, +} +impl<'a> AR10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `AR11` reader - Add Request 11"] +pub struct AR11_R(crate::FieldReader); +impl AR11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR11` writer - Add Request 11"] +pub struct AR11_W<'a> { + w: &'a mut W, +} +impl<'a> AR11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `AR12` reader - Add Request 12"] +pub struct AR12_R(crate::FieldReader); +impl AR12_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR12_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR12_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR12` writer - Add Request 12"] +pub struct AR12_W<'a> { + w: &'a mut W, +} +impl<'a> AR12_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `AR13` reader - Add Request 13"] +pub struct AR13_R(crate::FieldReader); +impl AR13_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR13_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR13_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR13` writer - Add Request 13"] +pub struct AR13_W<'a> { + w: &'a mut W, +} +impl<'a> AR13_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `AR14` reader - Add Request 14"] +pub struct AR14_R(crate::FieldReader); +impl AR14_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR14_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR14_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR14` writer - Add Request 14"] +pub struct AR14_W<'a> { + w: &'a mut W, +} +impl<'a> AR14_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `AR15` reader - Add Request 15"] +pub struct AR15_R(crate::FieldReader); +impl AR15_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR15_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR15_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR15` writer - Add Request 15"] +pub struct AR15_W<'a> { + w: &'a mut W, +} +impl<'a> AR15_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `AR16` reader - Add Request 16"] +pub struct AR16_R(crate::FieldReader); +impl AR16_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR16_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR16_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR16` writer - Add Request 16"] +pub struct AR16_W<'a> { + w: &'a mut W, +} +impl<'a> AR16_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `AR17` reader - Add Request 17"] +pub struct AR17_R(crate::FieldReader); +impl AR17_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR17_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR17_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR17` writer - Add Request 17"] +pub struct AR17_W<'a> { + w: &'a mut W, +} +impl<'a> AR17_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `AR18` reader - Add Request 18"] +pub struct AR18_R(crate::FieldReader); +impl AR18_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR18_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR18_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR18` writer - Add Request 18"] +pub struct AR18_W<'a> { + w: &'a mut W, +} +impl<'a> AR18_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `AR19` reader - Add Request 19"] +pub struct AR19_R(crate::FieldReader); +impl AR19_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR19_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR19_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR19` writer - Add Request 19"] +pub struct AR19_W<'a> { + w: &'a mut W, +} +impl<'a> AR19_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `AR20` reader - Add Request 20"] +pub struct AR20_R(crate::FieldReader); +impl AR20_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR20_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR20_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR20` writer - Add Request 20"] +pub struct AR20_W<'a> { + w: &'a mut W, +} +impl<'a> AR20_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `AR21` reader - Add Request 21"] +pub struct AR21_R(crate::FieldReader); +impl AR21_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR21_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR21_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR21` writer - Add Request 21"] +pub struct AR21_W<'a> { + w: &'a mut W, +} +impl<'a> AR21_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `AR22` reader - Add Request 22"] +pub struct AR22_R(crate::FieldReader); +impl AR22_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR22_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR22_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR22` writer - Add Request 22"] +pub struct AR22_W<'a> { + w: &'a mut W, +} +impl<'a> AR22_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `AR23` reader - Add Request 23"] +pub struct AR23_R(crate::FieldReader); +impl AR23_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR23_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR23_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR23` writer - Add Request 23"] +pub struct AR23_W<'a> { + w: &'a mut W, +} +impl<'a> AR23_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `AR24` reader - Add Request 24"] +pub struct AR24_R(crate::FieldReader); +impl AR24_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR24_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR24_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR24` writer - Add Request 24"] +pub struct AR24_W<'a> { + w: &'a mut W, +} +impl<'a> AR24_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `AR25` reader - Add Request 25"] +pub struct AR25_R(crate::FieldReader); +impl AR25_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR25_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR25_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR25` writer - Add Request 25"] +pub struct AR25_W<'a> { + w: &'a mut W, +} +impl<'a> AR25_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `AR26` reader - Add Request 26"] +pub struct AR26_R(crate::FieldReader); +impl AR26_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR26_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR26_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR26` writer - Add Request 26"] +pub struct AR26_W<'a> { + w: &'a mut W, +} +impl<'a> AR26_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `AR27` reader - Add Request 27"] +pub struct AR27_R(crate::FieldReader); +impl AR27_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR27_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR27_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR27` writer - Add Request 27"] +pub struct AR27_W<'a> { + w: &'a mut W, +} +impl<'a> AR27_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +#[doc = "Field `AR28` reader - Add Request 28"] +pub struct AR28_R(crate::FieldReader); +impl AR28_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR28_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR28_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR28` writer - Add Request 28"] +pub struct AR28_W<'a> { + w: &'a mut W, +} +impl<'a> AR28_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Field `AR29` reader - Add Request 29"] +pub struct AR29_R(crate::FieldReader); +impl AR29_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR29_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR29_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR29` writer - Add Request 29"] +pub struct AR29_W<'a> { + w: &'a mut W, +} +impl<'a> AR29_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29); + self.w + } +} +#[doc = "Field `AR30` reader - Add Request 30"] +pub struct AR30_R(crate::FieldReader); +impl AR30_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR30_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR30_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR30` writer - Add Request 30"] +pub struct AR30_W<'a> { + w: &'a mut W, +} +impl<'a> AR30_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +#[doc = "Field `AR31` reader - Add Request 31"] +pub struct AR31_R(crate::FieldReader); +impl AR31_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR31_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR31_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR31` writer - Add Request 31"] +pub struct AR31_W<'a> { + w: &'a mut W, +} +impl<'a> AR31_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bit 0 - Add Request 0"] + #[inline(always)] + pub fn ar0(&self) -> AR0_R { + AR0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Add Request 1"] + #[inline(always)] + pub fn ar1(&self) -> AR1_R { + AR1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Add Request 2"] + #[inline(always)] + pub fn ar2(&self) -> AR2_R { + AR2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Add Request 3"] + #[inline(always)] + pub fn ar3(&self) -> AR3_R { + AR3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Add Request 4"] + #[inline(always)] + pub fn ar4(&self) -> AR4_R { + AR4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Add Request 5"] + #[inline(always)] + pub fn ar5(&self) -> AR5_R { + AR5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Add Request 6"] + #[inline(always)] + pub fn ar6(&self) -> AR6_R { + AR6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Add Request 7"] + #[inline(always)] + pub fn ar7(&self) -> AR7_R { + AR7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Add Request 8"] + #[inline(always)] + pub fn ar8(&self) -> AR8_R { + AR8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Add Request 9"] + #[inline(always)] + pub fn ar9(&self) -> AR9_R { + AR9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Add Request 10"] + #[inline(always)] + pub fn ar10(&self) -> AR10_R { + AR10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Add Request 11"] + #[inline(always)] + pub fn ar11(&self) -> AR11_R { + AR11_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Add Request 12"] + #[inline(always)] + pub fn ar12(&self) -> AR12_R { + AR12_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Add Request 13"] + #[inline(always)] + pub fn ar13(&self) -> AR13_R { + AR13_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Add Request 14"] + #[inline(always)] + pub fn ar14(&self) -> AR14_R { + AR14_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Add Request 15"] + #[inline(always)] + pub fn ar15(&self) -> AR15_R { + AR15_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Add Request 16"] + #[inline(always)] + pub fn ar16(&self) -> AR16_R { + AR16_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Add Request 17"] + #[inline(always)] + pub fn ar17(&self) -> AR17_R { + AR17_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Add Request 18"] + #[inline(always)] + pub fn ar18(&self) -> AR18_R { + AR18_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Add Request 19"] + #[inline(always)] + pub fn ar19(&self) -> AR19_R { + AR19_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Add Request 20"] + #[inline(always)] + pub fn ar20(&self) -> AR20_R { + AR20_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Add Request 21"] + #[inline(always)] + pub fn ar21(&self) -> AR21_R { + AR21_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Add Request 22"] + #[inline(always)] + pub fn ar22(&self) -> AR22_R { + AR22_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Add Request 23"] + #[inline(always)] + pub fn ar23(&self) -> AR23_R { + AR23_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24 - Add Request 24"] + #[inline(always)] + pub fn ar24(&self) -> AR24_R { + AR24_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Add Request 25"] + #[inline(always)] + pub fn ar25(&self) -> AR25_R { + AR25_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Add Request 26"] + #[inline(always)] + pub fn ar26(&self) -> AR26_R { + AR26_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Add Request 27"] + #[inline(always)] + pub fn ar27(&self) -> AR27_R { + AR27_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28 - Add Request 28"] + #[inline(always)] + pub fn ar28(&self) -> AR28_R { + AR28_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Add Request 29"] + #[inline(always)] + pub fn ar29(&self) -> AR29_R { + AR29_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - Add Request 30"] + #[inline(always)] + pub fn ar30(&self) -> AR30_R { + AR30_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 31 - Add Request 31"] + #[inline(always)] + pub fn ar31(&self) -> AR31_R { + AR31_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Add Request 0"] + #[inline(always)] + pub fn ar0(&mut self) -> AR0_W { + AR0_W { w: self } + } + #[doc = "Bit 1 - Add Request 1"] + #[inline(always)] + pub fn ar1(&mut self) -> AR1_W { + AR1_W { w: self } + } + #[doc = "Bit 2 - Add Request 2"] + #[inline(always)] + pub fn ar2(&mut self) -> AR2_W { + AR2_W { w: self } + } + #[doc = "Bit 3 - Add Request 3"] + #[inline(always)] + pub fn ar3(&mut self) -> AR3_W { + AR3_W { w: self } + } + #[doc = "Bit 4 - Add Request 4"] + #[inline(always)] + pub fn ar4(&mut self) -> AR4_W { + AR4_W { w: self } + } + #[doc = "Bit 5 - Add Request 5"] + #[inline(always)] + pub fn ar5(&mut self) -> AR5_W { + AR5_W { w: self } + } + #[doc = "Bit 6 - Add Request 6"] + #[inline(always)] + pub fn ar6(&mut self) -> AR6_W { + AR6_W { w: self } + } + #[doc = "Bit 7 - Add Request 7"] + #[inline(always)] + pub fn ar7(&mut self) -> AR7_W { + AR7_W { w: self } + } + #[doc = "Bit 8 - Add Request 8"] + #[inline(always)] + pub fn ar8(&mut self) -> AR8_W { + AR8_W { w: self } + } + #[doc = "Bit 9 - Add Request 9"] + #[inline(always)] + pub fn ar9(&mut self) -> AR9_W { + AR9_W { w: self } + } + #[doc = "Bit 10 - Add Request 10"] + #[inline(always)] + pub fn ar10(&mut self) -> AR10_W { + AR10_W { w: self } + } + #[doc = "Bit 11 - Add Request 11"] + #[inline(always)] + pub fn ar11(&mut self) -> AR11_W { + AR11_W { w: self } + } + #[doc = "Bit 12 - Add Request 12"] + #[inline(always)] + pub fn ar12(&mut self) -> AR12_W { + AR12_W { w: self } + } + #[doc = "Bit 13 - Add Request 13"] + #[inline(always)] + pub fn ar13(&mut self) -> AR13_W { + AR13_W { w: self } + } + #[doc = "Bit 14 - Add Request 14"] + #[inline(always)] + pub fn ar14(&mut self) -> AR14_W { + AR14_W { w: self } + } + #[doc = "Bit 15 - Add Request 15"] + #[inline(always)] + pub fn ar15(&mut self) -> AR15_W { + AR15_W { w: self } + } + #[doc = "Bit 16 - Add Request 16"] + #[inline(always)] + pub fn ar16(&mut self) -> AR16_W { + AR16_W { w: self } + } + #[doc = "Bit 17 - Add Request 17"] + #[inline(always)] + pub fn ar17(&mut self) -> AR17_W { + AR17_W { w: self } + } + #[doc = "Bit 18 - Add Request 18"] + #[inline(always)] + pub fn ar18(&mut self) -> AR18_W { + AR18_W { w: self } + } + #[doc = "Bit 19 - Add Request 19"] + #[inline(always)] + pub fn ar19(&mut self) -> AR19_W { + AR19_W { w: self } + } + #[doc = "Bit 20 - Add Request 20"] + #[inline(always)] + pub fn ar20(&mut self) -> AR20_W { + AR20_W { w: self } + } + #[doc = "Bit 21 - Add Request 21"] + #[inline(always)] + pub fn ar21(&mut self) -> AR21_W { + AR21_W { w: self } + } + #[doc = "Bit 22 - Add Request 22"] + #[inline(always)] + pub fn ar22(&mut self) -> AR22_W { + AR22_W { w: self } + } + #[doc = "Bit 23 - Add Request 23"] + #[inline(always)] + pub fn ar23(&mut self) -> AR23_W { + AR23_W { w: self } + } + #[doc = "Bit 24 - Add Request 24"] + #[inline(always)] + pub fn ar24(&mut self) -> AR24_W { + AR24_W { w: self } + } + #[doc = "Bit 25 - Add Request 25"] + #[inline(always)] + pub fn ar25(&mut self) -> AR25_W { + AR25_W { w: self } + } + #[doc = "Bit 26 - Add Request 26"] + #[inline(always)] + pub fn ar26(&mut self) -> AR26_W { + AR26_W { w: self } + } + #[doc = "Bit 27 - Add Request 27"] + #[inline(always)] + pub fn ar27(&mut self) -> AR27_W { + AR27_W { w: self } + } + #[doc = "Bit 28 - Add Request 28"] + #[inline(always)] + pub fn ar28(&mut self) -> AR28_W { + AR28_W { w: self } + } + #[doc = "Bit 29 - Add Request 29"] + #[inline(always)] + pub fn ar29(&mut self) -> AR29_W { + AR29_W { w: self } + } + #[doc = "Bit 30 - Add Request 30"] + #[inline(always)] + pub fn ar30(&mut self) -> AR30_W { + AR30_W { w: self } + } + #[doc = "Bit 31 - Add Request 31"] + #[inline(always)] + pub fn ar31(&mut self) -> AR31_W { + AR31_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Tx Buffer Add Request\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txbar](index.html) module"] +pub struct TXBAR_SPEC; +impl crate::RegisterSpec for TXBAR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [txbar::R](R) reader structure"] +impl crate::Readable for TXBAR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [txbar::W](W) writer structure"] +impl crate::Writable for TXBAR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TXBAR to value 0"] +impl crate::Resettable for TXBAR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/can0/txbc.rs b/pac/atsamc21j/src/can0/txbc.rs new file mode 100644 index 000000000000..9545eaebf91d --- /dev/null +++ b/pac/atsamc21j/src/can0/txbc.rs @@ -0,0 +1,224 @@ +#[doc = "Register `TXBC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TXBC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TBSA` reader - Tx Buffers Start Address"] +pub struct TBSA_R(crate::FieldReader); +impl TBSA_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + TBSA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TBSA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TBSA` writer - Tx Buffers Start Address"] +pub struct TBSA_W<'a> { + w: &'a mut W, +} +impl<'a> TBSA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +#[doc = "Field `NDTB` reader - Number of Dedicated Transmit Buffers"] +pub struct NDTB_R(crate::FieldReader); +impl NDTB_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + NDTB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NDTB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NDTB` writer - Number of Dedicated Transmit Buffers"] +pub struct NDTB_W<'a> { + w: &'a mut W, +} +impl<'a> NDTB_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 16)) | ((value as u32 & 0x3f) << 16); + self.w + } +} +#[doc = "Field `TFQS` reader - Transmit FIFO/Queue Size"] +pub struct TFQS_R(crate::FieldReader); +impl TFQS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TFQS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TFQS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TFQS` writer - Transmit FIFO/Queue Size"] +pub struct TFQS_W<'a> { + w: &'a mut W, +} +impl<'a> TFQS_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 24)) | ((value as u32 & 0x3f) << 24); + self.w + } +} +#[doc = "Field `TFQM` reader - Tx FIFO/Queue Mode"] +pub struct TFQM_R(crate::FieldReader); +impl TFQM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TFQM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TFQM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TFQM` writer - Tx FIFO/Queue Mode"] +pub struct TFQM_W<'a> { + w: &'a mut W, +} +impl<'a> TFQM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Tx Buffers Start Address"] + #[inline(always)] + pub fn tbsa(&self) -> TBSA_R { + TBSA_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:21 - Number of Dedicated Transmit Buffers"] + #[inline(always)] + pub fn ndtb(&self) -> NDTB_R { + NDTB_R::new(((self.bits >> 16) & 0x3f) as u8) + } + #[doc = "Bits 24:29 - Transmit FIFO/Queue Size"] + #[inline(always)] + pub fn tfqs(&self) -> TFQS_R { + TFQS_R::new(((self.bits >> 24) & 0x3f) as u8) + } + #[doc = "Bit 30 - Tx FIFO/Queue Mode"] + #[inline(always)] + pub fn tfqm(&self) -> TFQM_R { + TFQM_R::new(((self.bits >> 30) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Tx Buffers Start Address"] + #[inline(always)] + pub fn tbsa(&mut self) -> TBSA_W { + TBSA_W { w: self } + } + #[doc = "Bits 16:21 - Number of Dedicated Transmit Buffers"] + #[inline(always)] + pub fn ndtb(&mut self) -> NDTB_W { + NDTB_W { w: self } + } + #[doc = "Bits 24:29 - Transmit FIFO/Queue Size"] + #[inline(always)] + pub fn tfqs(&mut self) -> TFQS_W { + TFQS_W { w: self } + } + #[doc = "Bit 30 - Tx FIFO/Queue Mode"] + #[inline(always)] + pub fn tfqm(&mut self) -> TFQM_W { + TFQM_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Tx Buffer Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txbc](index.html) module"] +pub struct TXBC_SPEC; +impl crate::RegisterSpec for TXBC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [txbc::R](R) reader structure"] +impl crate::Readable for TXBC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [txbc::W](W) writer structure"] +impl crate::Writable for TXBC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TXBC to value 0"] +impl crate::Resettable for TXBC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/can0/txbcf.rs b/pac/atsamc21j/src/can0/txbcf.rs new file mode 100644 index 000000000000..e592d4e90bea --- /dev/null +++ b/pac/atsamc21j/src/can0/txbcf.rs @@ -0,0 +1,673 @@ +#[doc = "Register `TXBCF` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `CF0` reader - Tx Buffer Cancellation Finished 0"] +pub struct CF0_R(crate::FieldReader); +impl CF0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF1` reader - Tx Buffer Cancellation Finished 1"] +pub struct CF1_R(crate::FieldReader); +impl CF1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF2` reader - Tx Buffer Cancellation Finished 2"] +pub struct CF2_R(crate::FieldReader); +impl CF2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF3` reader - Tx Buffer Cancellation Finished 3"] +pub struct CF3_R(crate::FieldReader); +impl CF3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF4` reader - Tx Buffer Cancellation Finished 4"] +pub struct CF4_R(crate::FieldReader); +impl CF4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF5` reader - Tx Buffer Cancellation Finished 5"] +pub struct CF5_R(crate::FieldReader); +impl CF5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF6` reader - Tx Buffer Cancellation Finished 6"] +pub struct CF6_R(crate::FieldReader); +impl CF6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF7` reader - Tx Buffer Cancellation Finished 7"] +pub struct CF7_R(crate::FieldReader); +impl CF7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF8` reader - Tx Buffer Cancellation Finished 8"] +pub struct CF8_R(crate::FieldReader); +impl CF8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF9` reader - Tx Buffer Cancellation Finished 9"] +pub struct CF9_R(crate::FieldReader); +impl CF9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF10` reader - Tx Buffer Cancellation Finished 10"] +pub struct CF10_R(crate::FieldReader); +impl CF10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF11` reader - Tx Buffer Cancellation Finished 11"] +pub struct CF11_R(crate::FieldReader); +impl CF11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF12` reader - Tx Buffer Cancellation Finished 12"] +pub struct CF12_R(crate::FieldReader); +impl CF12_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF12_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF12_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF13` reader - Tx Buffer Cancellation Finished 13"] +pub struct CF13_R(crate::FieldReader); +impl CF13_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF13_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF13_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF14` reader - Tx Buffer Cancellation Finished 14"] +pub struct CF14_R(crate::FieldReader); +impl CF14_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF14_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF14_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF15` reader - Tx Buffer Cancellation Finished 15"] +pub struct CF15_R(crate::FieldReader); +impl CF15_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF15_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF15_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF16` reader - Tx Buffer Cancellation Finished 16"] +pub struct CF16_R(crate::FieldReader); +impl CF16_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF16_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF16_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF17` reader - Tx Buffer Cancellation Finished 17"] +pub struct CF17_R(crate::FieldReader); +impl CF17_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF17_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF17_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF18` reader - Tx Buffer Cancellation Finished 18"] +pub struct CF18_R(crate::FieldReader); +impl CF18_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF18_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF18_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF19` reader - Tx Buffer Cancellation Finished 19"] +pub struct CF19_R(crate::FieldReader); +impl CF19_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF19_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF19_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF20` reader - Tx Buffer Cancellation Finished 20"] +pub struct CF20_R(crate::FieldReader); +impl CF20_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF20_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF20_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF21` reader - Tx Buffer Cancellation Finished 21"] +pub struct CF21_R(crate::FieldReader); +impl CF21_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF21_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF21_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF22` reader - Tx Buffer Cancellation Finished 22"] +pub struct CF22_R(crate::FieldReader); +impl CF22_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF22_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF22_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF23` reader - Tx Buffer Cancellation Finished 23"] +pub struct CF23_R(crate::FieldReader); +impl CF23_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF23_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF23_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF24` reader - Tx Buffer Cancellation Finished 24"] +pub struct CF24_R(crate::FieldReader); +impl CF24_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF24_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF24_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF25` reader - Tx Buffer Cancellation Finished 25"] +pub struct CF25_R(crate::FieldReader); +impl CF25_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF25_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF25_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF26` reader - Tx Buffer Cancellation Finished 26"] +pub struct CF26_R(crate::FieldReader); +impl CF26_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF26_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF26_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF27` reader - Tx Buffer Cancellation Finished 27"] +pub struct CF27_R(crate::FieldReader); +impl CF27_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF27_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF27_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF28` reader - Tx Buffer Cancellation Finished 28"] +pub struct CF28_R(crate::FieldReader); +impl CF28_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF28_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF28_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF29` reader - Tx Buffer Cancellation Finished 29"] +pub struct CF29_R(crate::FieldReader); +impl CF29_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF29_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF29_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF30` reader - Tx Buffer Cancellation Finished 30"] +pub struct CF30_R(crate::FieldReader); +impl CF30_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF30_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF30_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF31` reader - Tx Buffer Cancellation Finished 31"] +pub struct CF31_R(crate::FieldReader); +impl CF31_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF31_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF31_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Tx Buffer Cancellation Finished 0"] + #[inline(always)] + pub fn cf0(&self) -> CF0_R { + CF0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Tx Buffer Cancellation Finished 1"] + #[inline(always)] + pub fn cf1(&self) -> CF1_R { + CF1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Tx Buffer Cancellation Finished 2"] + #[inline(always)] + pub fn cf2(&self) -> CF2_R { + CF2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Tx Buffer Cancellation Finished 3"] + #[inline(always)] + pub fn cf3(&self) -> CF3_R { + CF3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Tx Buffer Cancellation Finished 4"] + #[inline(always)] + pub fn cf4(&self) -> CF4_R { + CF4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Tx Buffer Cancellation Finished 5"] + #[inline(always)] + pub fn cf5(&self) -> CF5_R { + CF5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Tx Buffer Cancellation Finished 6"] + #[inline(always)] + pub fn cf6(&self) -> CF6_R { + CF6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Tx Buffer Cancellation Finished 7"] + #[inline(always)] + pub fn cf7(&self) -> CF7_R { + CF7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Tx Buffer Cancellation Finished 8"] + #[inline(always)] + pub fn cf8(&self) -> CF8_R { + CF8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Tx Buffer Cancellation Finished 9"] + #[inline(always)] + pub fn cf9(&self) -> CF9_R { + CF9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Tx Buffer Cancellation Finished 10"] + #[inline(always)] + pub fn cf10(&self) -> CF10_R { + CF10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Tx Buffer Cancellation Finished 11"] + #[inline(always)] + pub fn cf11(&self) -> CF11_R { + CF11_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Tx Buffer Cancellation Finished 12"] + #[inline(always)] + pub fn cf12(&self) -> CF12_R { + CF12_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Tx Buffer Cancellation Finished 13"] + #[inline(always)] + pub fn cf13(&self) -> CF13_R { + CF13_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Tx Buffer Cancellation Finished 14"] + #[inline(always)] + pub fn cf14(&self) -> CF14_R { + CF14_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Tx Buffer Cancellation Finished 15"] + #[inline(always)] + pub fn cf15(&self) -> CF15_R { + CF15_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Tx Buffer Cancellation Finished 16"] + #[inline(always)] + pub fn cf16(&self) -> CF16_R { + CF16_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Tx Buffer Cancellation Finished 17"] + #[inline(always)] + pub fn cf17(&self) -> CF17_R { + CF17_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Tx Buffer Cancellation Finished 18"] + #[inline(always)] + pub fn cf18(&self) -> CF18_R { + CF18_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Tx Buffer Cancellation Finished 19"] + #[inline(always)] + pub fn cf19(&self) -> CF19_R { + CF19_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Tx Buffer Cancellation Finished 20"] + #[inline(always)] + pub fn cf20(&self) -> CF20_R { + CF20_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Tx Buffer Cancellation Finished 21"] + #[inline(always)] + pub fn cf21(&self) -> CF21_R { + CF21_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Tx Buffer Cancellation Finished 22"] + #[inline(always)] + pub fn cf22(&self) -> CF22_R { + CF22_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Tx Buffer Cancellation Finished 23"] + #[inline(always)] + pub fn cf23(&self) -> CF23_R { + CF23_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24 - Tx Buffer Cancellation Finished 24"] + #[inline(always)] + pub fn cf24(&self) -> CF24_R { + CF24_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Tx Buffer Cancellation Finished 25"] + #[inline(always)] + pub fn cf25(&self) -> CF25_R { + CF25_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Tx Buffer Cancellation Finished 26"] + #[inline(always)] + pub fn cf26(&self) -> CF26_R { + CF26_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Tx Buffer Cancellation Finished 27"] + #[inline(always)] + pub fn cf27(&self) -> CF27_R { + CF27_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28 - Tx Buffer Cancellation Finished 28"] + #[inline(always)] + pub fn cf28(&self) -> CF28_R { + CF28_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Tx Buffer Cancellation Finished 29"] + #[inline(always)] + pub fn cf29(&self) -> CF29_R { + CF29_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - Tx Buffer Cancellation Finished 30"] + #[inline(always)] + pub fn cf30(&self) -> CF30_R { + CF30_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 31 - Tx Buffer Cancellation Finished 31"] + #[inline(always)] + pub fn cf31(&self) -> CF31_R { + CF31_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +#[doc = "Tx Buffer Cancellation Finished\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txbcf](index.html) module"] +pub struct TXBCF_SPEC; +impl crate::RegisterSpec for TXBCF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [txbcf::R](R) reader structure"] +impl crate::Readable for TXBCF_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets TXBCF to value 0"] +impl crate::Resettable for TXBCF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/can0/txbcie.rs b/pac/atsamc21j/src/can0/txbcie.rs new file mode 100644 index 000000000000..ca0c9c0a2822 --- /dev/null +++ b/pac/atsamc21j/src/can0/txbcie.rs @@ -0,0 +1,1570 @@ +#[doc = "Register `TXBCIE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TXBCIE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CFIE0` reader - Cancellation Finished Interrupt Enable 0"] +pub struct CFIE0_R(crate::FieldReader); +impl CFIE0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE0` writer - Cancellation Finished Interrupt Enable 0"] +pub struct CFIE0_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `CFIE1` reader - Cancellation Finished Interrupt Enable 1"] +pub struct CFIE1_R(crate::FieldReader); +impl CFIE1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE1` writer - Cancellation Finished Interrupt Enable 1"] +pub struct CFIE1_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CFIE2` reader - Cancellation Finished Interrupt Enable 2"] +pub struct CFIE2_R(crate::FieldReader); +impl CFIE2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE2` writer - Cancellation Finished Interrupt Enable 2"] +pub struct CFIE2_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CFIE3` reader - Cancellation Finished Interrupt Enable 3"] +pub struct CFIE3_R(crate::FieldReader); +impl CFIE3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE3` writer - Cancellation Finished Interrupt Enable 3"] +pub struct CFIE3_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CFIE4` reader - Cancellation Finished Interrupt Enable 4"] +pub struct CFIE4_R(crate::FieldReader); +impl CFIE4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE4` writer - Cancellation Finished Interrupt Enable 4"] +pub struct CFIE4_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `CFIE5` reader - Cancellation Finished Interrupt Enable 5"] +pub struct CFIE5_R(crate::FieldReader); +impl CFIE5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE5` writer - Cancellation Finished Interrupt Enable 5"] +pub struct CFIE5_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `CFIE6` reader - Cancellation Finished Interrupt Enable 6"] +pub struct CFIE6_R(crate::FieldReader); +impl CFIE6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE6` writer - Cancellation Finished Interrupt Enable 6"] +pub struct CFIE6_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `CFIE7` reader - Cancellation Finished Interrupt Enable 7"] +pub struct CFIE7_R(crate::FieldReader); +impl CFIE7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE7` writer - Cancellation Finished Interrupt Enable 7"] +pub struct CFIE7_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CFIE8` reader - Cancellation Finished Interrupt Enable 8"] +pub struct CFIE8_R(crate::FieldReader); +impl CFIE8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE8` writer - Cancellation Finished Interrupt Enable 8"] +pub struct CFIE8_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `CFIE9` reader - Cancellation Finished Interrupt Enable 9"] +pub struct CFIE9_R(crate::FieldReader); +impl CFIE9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE9` writer - Cancellation Finished Interrupt Enable 9"] +pub struct CFIE9_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `CFIE10` reader - Cancellation Finished Interrupt Enable 10"] +pub struct CFIE10_R(crate::FieldReader); +impl CFIE10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE10` writer - Cancellation Finished Interrupt Enable 10"] +pub struct CFIE10_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `CFIE11` reader - Cancellation Finished Interrupt Enable 11"] +pub struct CFIE11_R(crate::FieldReader); +impl CFIE11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE11` writer - Cancellation Finished Interrupt Enable 11"] +pub struct CFIE11_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `CFIE12` reader - Cancellation Finished Interrupt Enable 12"] +pub struct CFIE12_R(crate::FieldReader); +impl CFIE12_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE12_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE12_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE12` writer - Cancellation Finished Interrupt Enable 12"] +pub struct CFIE12_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE12_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `CFIE13` reader - Cancellation Finished Interrupt Enable 13"] +pub struct CFIE13_R(crate::FieldReader); +impl CFIE13_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE13_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE13_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE13` writer - Cancellation Finished Interrupt Enable 13"] +pub struct CFIE13_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE13_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `CFIE14` reader - Cancellation Finished Interrupt Enable 14"] +pub struct CFIE14_R(crate::FieldReader); +impl CFIE14_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE14_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE14_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE14` writer - Cancellation Finished Interrupt Enable 14"] +pub struct CFIE14_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE14_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `CFIE15` reader - Cancellation Finished Interrupt Enable 15"] +pub struct CFIE15_R(crate::FieldReader); +impl CFIE15_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE15_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE15_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE15` writer - Cancellation Finished Interrupt Enable 15"] +pub struct CFIE15_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE15_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `CFIE16` reader - Cancellation Finished Interrupt Enable 16"] +pub struct CFIE16_R(crate::FieldReader); +impl CFIE16_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE16_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE16_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE16` writer - Cancellation Finished Interrupt Enable 16"] +pub struct CFIE16_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE16_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `CFIE17` reader - Cancellation Finished Interrupt Enable 17"] +pub struct CFIE17_R(crate::FieldReader); +impl CFIE17_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE17_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE17_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE17` writer - Cancellation Finished Interrupt Enable 17"] +pub struct CFIE17_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE17_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `CFIE18` reader - Cancellation Finished Interrupt Enable 18"] +pub struct CFIE18_R(crate::FieldReader); +impl CFIE18_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE18_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE18_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE18` writer - Cancellation Finished Interrupt Enable 18"] +pub struct CFIE18_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE18_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `CFIE19` reader - Cancellation Finished Interrupt Enable 19"] +pub struct CFIE19_R(crate::FieldReader); +impl CFIE19_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE19_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE19_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE19` writer - Cancellation Finished Interrupt Enable 19"] +pub struct CFIE19_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE19_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `CFIE20` reader - Cancellation Finished Interrupt Enable 20"] +pub struct CFIE20_R(crate::FieldReader); +impl CFIE20_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE20_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE20_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE20` writer - Cancellation Finished Interrupt Enable 20"] +pub struct CFIE20_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE20_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `CFIE21` reader - Cancellation Finished Interrupt Enable 21"] +pub struct CFIE21_R(crate::FieldReader); +impl CFIE21_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE21_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE21_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE21` writer - Cancellation Finished Interrupt Enable 21"] +pub struct CFIE21_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE21_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `CFIE22` reader - Cancellation Finished Interrupt Enable 22"] +pub struct CFIE22_R(crate::FieldReader); +impl CFIE22_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE22_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE22_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE22` writer - Cancellation Finished Interrupt Enable 22"] +pub struct CFIE22_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE22_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `CFIE23` reader - Cancellation Finished Interrupt Enable 23"] +pub struct CFIE23_R(crate::FieldReader); +impl CFIE23_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE23_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE23_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE23` writer - Cancellation Finished Interrupt Enable 23"] +pub struct CFIE23_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE23_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `CFIE24` reader - Cancellation Finished Interrupt Enable 24"] +pub struct CFIE24_R(crate::FieldReader); +impl CFIE24_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE24_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE24_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE24` writer - Cancellation Finished Interrupt Enable 24"] +pub struct CFIE24_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE24_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `CFIE25` reader - Cancellation Finished Interrupt Enable 25"] +pub struct CFIE25_R(crate::FieldReader); +impl CFIE25_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE25_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE25_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE25` writer - Cancellation Finished Interrupt Enable 25"] +pub struct CFIE25_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE25_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `CFIE26` reader - Cancellation Finished Interrupt Enable 26"] +pub struct CFIE26_R(crate::FieldReader); +impl CFIE26_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE26_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE26_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE26` writer - Cancellation Finished Interrupt Enable 26"] +pub struct CFIE26_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE26_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `CFIE27` reader - Cancellation Finished Interrupt Enable 27"] +pub struct CFIE27_R(crate::FieldReader); +impl CFIE27_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE27_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE27_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE27` writer - Cancellation Finished Interrupt Enable 27"] +pub struct CFIE27_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE27_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +#[doc = "Field `CFIE28` reader - Cancellation Finished Interrupt Enable 28"] +pub struct CFIE28_R(crate::FieldReader); +impl CFIE28_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE28_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE28_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE28` writer - Cancellation Finished Interrupt Enable 28"] +pub struct CFIE28_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE28_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Field `CFIE29` reader - Cancellation Finished Interrupt Enable 29"] +pub struct CFIE29_R(crate::FieldReader); +impl CFIE29_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE29_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE29_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE29` writer - Cancellation Finished Interrupt Enable 29"] +pub struct CFIE29_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE29_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29); + self.w + } +} +#[doc = "Field `CFIE30` reader - Cancellation Finished Interrupt Enable 30"] +pub struct CFIE30_R(crate::FieldReader); +impl CFIE30_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE30_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE30_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE30` writer - Cancellation Finished Interrupt Enable 30"] +pub struct CFIE30_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE30_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +#[doc = "Field `CFIE31` reader - Cancellation Finished Interrupt Enable 31"] +pub struct CFIE31_R(crate::FieldReader); +impl CFIE31_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE31_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE31_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE31` writer - Cancellation Finished Interrupt Enable 31"] +pub struct CFIE31_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE31_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bit 0 - Cancellation Finished Interrupt Enable 0"] + #[inline(always)] + pub fn cfie0(&self) -> CFIE0_R { + CFIE0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Cancellation Finished Interrupt Enable 1"] + #[inline(always)] + pub fn cfie1(&self) -> CFIE1_R { + CFIE1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Cancellation Finished Interrupt Enable 2"] + #[inline(always)] + pub fn cfie2(&self) -> CFIE2_R { + CFIE2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Cancellation Finished Interrupt Enable 3"] + #[inline(always)] + pub fn cfie3(&self) -> CFIE3_R { + CFIE3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Cancellation Finished Interrupt Enable 4"] + #[inline(always)] + pub fn cfie4(&self) -> CFIE4_R { + CFIE4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Cancellation Finished Interrupt Enable 5"] + #[inline(always)] + pub fn cfie5(&self) -> CFIE5_R { + CFIE5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Cancellation Finished Interrupt Enable 6"] + #[inline(always)] + pub fn cfie6(&self) -> CFIE6_R { + CFIE6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Cancellation Finished Interrupt Enable 7"] + #[inline(always)] + pub fn cfie7(&self) -> CFIE7_R { + CFIE7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Cancellation Finished Interrupt Enable 8"] + #[inline(always)] + pub fn cfie8(&self) -> CFIE8_R { + CFIE8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Cancellation Finished Interrupt Enable 9"] + #[inline(always)] + pub fn cfie9(&self) -> CFIE9_R { + CFIE9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Cancellation Finished Interrupt Enable 10"] + #[inline(always)] + pub fn cfie10(&self) -> CFIE10_R { + CFIE10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Cancellation Finished Interrupt Enable 11"] + #[inline(always)] + pub fn cfie11(&self) -> CFIE11_R { + CFIE11_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Cancellation Finished Interrupt Enable 12"] + #[inline(always)] + pub fn cfie12(&self) -> CFIE12_R { + CFIE12_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Cancellation Finished Interrupt Enable 13"] + #[inline(always)] + pub fn cfie13(&self) -> CFIE13_R { + CFIE13_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Cancellation Finished Interrupt Enable 14"] + #[inline(always)] + pub fn cfie14(&self) -> CFIE14_R { + CFIE14_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Cancellation Finished Interrupt Enable 15"] + #[inline(always)] + pub fn cfie15(&self) -> CFIE15_R { + CFIE15_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Cancellation Finished Interrupt Enable 16"] + #[inline(always)] + pub fn cfie16(&self) -> CFIE16_R { + CFIE16_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Cancellation Finished Interrupt Enable 17"] + #[inline(always)] + pub fn cfie17(&self) -> CFIE17_R { + CFIE17_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Cancellation Finished Interrupt Enable 18"] + #[inline(always)] + pub fn cfie18(&self) -> CFIE18_R { + CFIE18_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Cancellation Finished Interrupt Enable 19"] + #[inline(always)] + pub fn cfie19(&self) -> CFIE19_R { + CFIE19_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Cancellation Finished Interrupt Enable 20"] + #[inline(always)] + pub fn cfie20(&self) -> CFIE20_R { + CFIE20_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Cancellation Finished Interrupt Enable 21"] + #[inline(always)] + pub fn cfie21(&self) -> CFIE21_R { + CFIE21_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Cancellation Finished Interrupt Enable 22"] + #[inline(always)] + pub fn cfie22(&self) -> CFIE22_R { + CFIE22_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Cancellation Finished Interrupt Enable 23"] + #[inline(always)] + pub fn cfie23(&self) -> CFIE23_R { + CFIE23_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24 - Cancellation Finished Interrupt Enable 24"] + #[inline(always)] + pub fn cfie24(&self) -> CFIE24_R { + CFIE24_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Cancellation Finished Interrupt Enable 25"] + #[inline(always)] + pub fn cfie25(&self) -> CFIE25_R { + CFIE25_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Cancellation Finished Interrupt Enable 26"] + #[inline(always)] + pub fn cfie26(&self) -> CFIE26_R { + CFIE26_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Cancellation Finished Interrupt Enable 27"] + #[inline(always)] + pub fn cfie27(&self) -> CFIE27_R { + CFIE27_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28 - Cancellation Finished Interrupt Enable 28"] + #[inline(always)] + pub fn cfie28(&self) -> CFIE28_R { + CFIE28_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Cancellation Finished Interrupt Enable 29"] + #[inline(always)] + pub fn cfie29(&self) -> CFIE29_R { + CFIE29_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - Cancellation Finished Interrupt Enable 30"] + #[inline(always)] + pub fn cfie30(&self) -> CFIE30_R { + CFIE30_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 31 - Cancellation Finished Interrupt Enable 31"] + #[inline(always)] + pub fn cfie31(&self) -> CFIE31_R { + CFIE31_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Cancellation Finished Interrupt Enable 0"] + #[inline(always)] + pub fn cfie0(&mut self) -> CFIE0_W { + CFIE0_W { w: self } + } + #[doc = "Bit 1 - Cancellation Finished Interrupt Enable 1"] + #[inline(always)] + pub fn cfie1(&mut self) -> CFIE1_W { + CFIE1_W { w: self } + } + #[doc = "Bit 2 - Cancellation Finished Interrupt Enable 2"] + #[inline(always)] + pub fn cfie2(&mut self) -> CFIE2_W { + CFIE2_W { w: self } + } + #[doc = "Bit 3 - Cancellation Finished Interrupt Enable 3"] + #[inline(always)] + pub fn cfie3(&mut self) -> CFIE3_W { + CFIE3_W { w: self } + } + #[doc = "Bit 4 - Cancellation Finished Interrupt Enable 4"] + #[inline(always)] + pub fn cfie4(&mut self) -> CFIE4_W { + CFIE4_W { w: self } + } + #[doc = "Bit 5 - Cancellation Finished Interrupt Enable 5"] + #[inline(always)] + pub fn cfie5(&mut self) -> CFIE5_W { + CFIE5_W { w: self } + } + #[doc = "Bit 6 - Cancellation Finished Interrupt Enable 6"] + #[inline(always)] + pub fn cfie6(&mut self) -> CFIE6_W { + CFIE6_W { w: self } + } + #[doc = "Bit 7 - Cancellation Finished Interrupt Enable 7"] + #[inline(always)] + pub fn cfie7(&mut self) -> CFIE7_W { + CFIE7_W { w: self } + } + #[doc = "Bit 8 - Cancellation Finished Interrupt Enable 8"] + #[inline(always)] + pub fn cfie8(&mut self) -> CFIE8_W { + CFIE8_W { w: self } + } + #[doc = "Bit 9 - Cancellation Finished Interrupt Enable 9"] + #[inline(always)] + pub fn cfie9(&mut self) -> CFIE9_W { + CFIE9_W { w: self } + } + #[doc = "Bit 10 - Cancellation Finished Interrupt Enable 10"] + #[inline(always)] + pub fn cfie10(&mut self) -> CFIE10_W { + CFIE10_W { w: self } + } + #[doc = "Bit 11 - Cancellation Finished Interrupt Enable 11"] + #[inline(always)] + pub fn cfie11(&mut self) -> CFIE11_W { + CFIE11_W { w: self } + } + #[doc = "Bit 12 - Cancellation Finished Interrupt Enable 12"] + #[inline(always)] + pub fn cfie12(&mut self) -> CFIE12_W { + CFIE12_W { w: self } + } + #[doc = "Bit 13 - Cancellation Finished Interrupt Enable 13"] + #[inline(always)] + pub fn cfie13(&mut self) -> CFIE13_W { + CFIE13_W { w: self } + } + #[doc = "Bit 14 - Cancellation Finished Interrupt Enable 14"] + #[inline(always)] + pub fn cfie14(&mut self) -> CFIE14_W { + CFIE14_W { w: self } + } + #[doc = "Bit 15 - Cancellation Finished Interrupt Enable 15"] + #[inline(always)] + pub fn cfie15(&mut self) -> CFIE15_W { + CFIE15_W { w: self } + } + #[doc = "Bit 16 - Cancellation Finished Interrupt Enable 16"] + #[inline(always)] + pub fn cfie16(&mut self) -> CFIE16_W { + CFIE16_W { w: self } + } + #[doc = "Bit 17 - Cancellation Finished Interrupt Enable 17"] + #[inline(always)] + pub fn cfie17(&mut self) -> CFIE17_W { + CFIE17_W { w: self } + } + #[doc = "Bit 18 - Cancellation Finished Interrupt Enable 18"] + #[inline(always)] + pub fn cfie18(&mut self) -> CFIE18_W { + CFIE18_W { w: self } + } + #[doc = "Bit 19 - Cancellation Finished Interrupt Enable 19"] + #[inline(always)] + pub fn cfie19(&mut self) -> CFIE19_W { + CFIE19_W { w: self } + } + #[doc = "Bit 20 - Cancellation Finished Interrupt Enable 20"] + #[inline(always)] + pub fn cfie20(&mut self) -> CFIE20_W { + CFIE20_W { w: self } + } + #[doc = "Bit 21 - Cancellation Finished Interrupt Enable 21"] + #[inline(always)] + pub fn cfie21(&mut self) -> CFIE21_W { + CFIE21_W { w: self } + } + #[doc = "Bit 22 - Cancellation Finished Interrupt Enable 22"] + #[inline(always)] + pub fn cfie22(&mut self) -> CFIE22_W { + CFIE22_W { w: self } + } + #[doc = "Bit 23 - Cancellation Finished Interrupt Enable 23"] + #[inline(always)] + pub fn cfie23(&mut self) -> CFIE23_W { + CFIE23_W { w: self } + } + #[doc = "Bit 24 - Cancellation Finished Interrupt Enable 24"] + #[inline(always)] + pub fn cfie24(&mut self) -> CFIE24_W { + CFIE24_W { w: self } + } + #[doc = "Bit 25 - Cancellation Finished Interrupt Enable 25"] + #[inline(always)] + pub fn cfie25(&mut self) -> CFIE25_W { + CFIE25_W { w: self } + } + #[doc = "Bit 26 - Cancellation Finished Interrupt Enable 26"] + #[inline(always)] + pub fn cfie26(&mut self) -> CFIE26_W { + CFIE26_W { w: self } + } + #[doc = "Bit 27 - Cancellation Finished Interrupt Enable 27"] + #[inline(always)] + pub fn cfie27(&mut self) -> CFIE27_W { + CFIE27_W { w: self } + } + #[doc = "Bit 28 - Cancellation Finished Interrupt Enable 28"] + #[inline(always)] + pub fn cfie28(&mut self) -> CFIE28_W { + CFIE28_W { w: self } + } + #[doc = "Bit 29 - Cancellation Finished Interrupt Enable 29"] + #[inline(always)] + pub fn cfie29(&mut self) -> CFIE29_W { + CFIE29_W { w: self } + } + #[doc = "Bit 30 - Cancellation Finished Interrupt Enable 30"] + #[inline(always)] + pub fn cfie30(&mut self) -> CFIE30_W { + CFIE30_W { w: self } + } + #[doc = "Bit 31 - Cancellation Finished Interrupt Enable 31"] + #[inline(always)] + pub fn cfie31(&mut self) -> CFIE31_W { + CFIE31_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Tx Buffer Cancellation Finished Interrupt Enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txbcie](index.html) module"] +pub struct TXBCIE_SPEC; +impl crate::RegisterSpec for TXBCIE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [txbcie::R](R) reader structure"] +impl crate::Readable for TXBCIE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [txbcie::W](W) writer structure"] +impl crate::Writable for TXBCIE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TXBCIE to value 0"] +impl crate::Resettable for TXBCIE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/can0/txbcr.rs b/pac/atsamc21j/src/can0/txbcr.rs new file mode 100644 index 000000000000..e5d0e61de8c9 --- /dev/null +++ b/pac/atsamc21j/src/can0/txbcr.rs @@ -0,0 +1,1570 @@ +#[doc = "Register `TXBCR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TXBCR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CR0` reader - Cancellation Request 0"] +pub struct CR0_R(crate::FieldReader); +impl CR0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR0` writer - Cancellation Request 0"] +pub struct CR0_W<'a> { + w: &'a mut W, +} +impl<'a> CR0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `CR1` reader - Cancellation Request 1"] +pub struct CR1_R(crate::FieldReader); +impl CR1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR1` writer - Cancellation Request 1"] +pub struct CR1_W<'a> { + w: &'a mut W, +} +impl<'a> CR1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CR2` reader - Cancellation Request 2"] +pub struct CR2_R(crate::FieldReader); +impl CR2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR2` writer - Cancellation Request 2"] +pub struct CR2_W<'a> { + w: &'a mut W, +} +impl<'a> CR2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CR3` reader - Cancellation Request 3"] +pub struct CR3_R(crate::FieldReader); +impl CR3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR3` writer - Cancellation Request 3"] +pub struct CR3_W<'a> { + w: &'a mut W, +} +impl<'a> CR3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CR4` reader - Cancellation Request 4"] +pub struct CR4_R(crate::FieldReader); +impl CR4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR4` writer - Cancellation Request 4"] +pub struct CR4_W<'a> { + w: &'a mut W, +} +impl<'a> CR4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `CR5` reader - Cancellation Request 5"] +pub struct CR5_R(crate::FieldReader); +impl CR5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR5` writer - Cancellation Request 5"] +pub struct CR5_W<'a> { + w: &'a mut W, +} +impl<'a> CR5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `CR6` reader - Cancellation Request 6"] +pub struct CR6_R(crate::FieldReader); +impl CR6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR6` writer - Cancellation Request 6"] +pub struct CR6_W<'a> { + w: &'a mut W, +} +impl<'a> CR6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `CR7` reader - Cancellation Request 7"] +pub struct CR7_R(crate::FieldReader); +impl CR7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR7` writer - Cancellation Request 7"] +pub struct CR7_W<'a> { + w: &'a mut W, +} +impl<'a> CR7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CR8` reader - Cancellation Request 8"] +pub struct CR8_R(crate::FieldReader); +impl CR8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR8` writer - Cancellation Request 8"] +pub struct CR8_W<'a> { + w: &'a mut W, +} +impl<'a> CR8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `CR9` reader - Cancellation Request 9"] +pub struct CR9_R(crate::FieldReader); +impl CR9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR9` writer - Cancellation Request 9"] +pub struct CR9_W<'a> { + w: &'a mut W, +} +impl<'a> CR9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `CR10` reader - Cancellation Request 10"] +pub struct CR10_R(crate::FieldReader); +impl CR10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR10` writer - Cancellation Request 10"] +pub struct CR10_W<'a> { + w: &'a mut W, +} +impl<'a> CR10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `CR11` reader - Cancellation Request 11"] +pub struct CR11_R(crate::FieldReader); +impl CR11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR11` writer - Cancellation Request 11"] +pub struct CR11_W<'a> { + w: &'a mut W, +} +impl<'a> CR11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `CR12` reader - Cancellation Request 12"] +pub struct CR12_R(crate::FieldReader); +impl CR12_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR12_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR12_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR12` writer - Cancellation Request 12"] +pub struct CR12_W<'a> { + w: &'a mut W, +} +impl<'a> CR12_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `CR13` reader - Cancellation Request 13"] +pub struct CR13_R(crate::FieldReader); +impl CR13_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR13_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR13_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR13` writer - Cancellation Request 13"] +pub struct CR13_W<'a> { + w: &'a mut W, +} +impl<'a> CR13_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `CR14` reader - Cancellation Request 14"] +pub struct CR14_R(crate::FieldReader); +impl CR14_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR14_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR14_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR14` writer - Cancellation Request 14"] +pub struct CR14_W<'a> { + w: &'a mut W, +} +impl<'a> CR14_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `CR15` reader - Cancellation Request 15"] +pub struct CR15_R(crate::FieldReader); +impl CR15_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR15_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR15_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR15` writer - Cancellation Request 15"] +pub struct CR15_W<'a> { + w: &'a mut W, +} +impl<'a> CR15_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `CR16` reader - Cancellation Request 16"] +pub struct CR16_R(crate::FieldReader); +impl CR16_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR16_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR16_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR16` writer - Cancellation Request 16"] +pub struct CR16_W<'a> { + w: &'a mut W, +} +impl<'a> CR16_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `CR17` reader - Cancellation Request 17"] +pub struct CR17_R(crate::FieldReader); +impl CR17_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR17_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR17_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR17` writer - Cancellation Request 17"] +pub struct CR17_W<'a> { + w: &'a mut W, +} +impl<'a> CR17_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `CR18` reader - Cancellation Request 18"] +pub struct CR18_R(crate::FieldReader); +impl CR18_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR18_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR18_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR18` writer - Cancellation Request 18"] +pub struct CR18_W<'a> { + w: &'a mut W, +} +impl<'a> CR18_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `CR19` reader - Cancellation Request 19"] +pub struct CR19_R(crate::FieldReader); +impl CR19_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR19_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR19_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR19` writer - Cancellation Request 19"] +pub struct CR19_W<'a> { + w: &'a mut W, +} +impl<'a> CR19_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `CR20` reader - Cancellation Request 20"] +pub struct CR20_R(crate::FieldReader); +impl CR20_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR20_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR20_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR20` writer - Cancellation Request 20"] +pub struct CR20_W<'a> { + w: &'a mut W, +} +impl<'a> CR20_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `CR21` reader - Cancellation Request 21"] +pub struct CR21_R(crate::FieldReader); +impl CR21_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR21_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR21_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR21` writer - Cancellation Request 21"] +pub struct CR21_W<'a> { + w: &'a mut W, +} +impl<'a> CR21_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `CR22` reader - Cancellation Request 22"] +pub struct CR22_R(crate::FieldReader); +impl CR22_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR22_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR22_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR22` writer - Cancellation Request 22"] +pub struct CR22_W<'a> { + w: &'a mut W, +} +impl<'a> CR22_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `CR23` reader - Cancellation Request 23"] +pub struct CR23_R(crate::FieldReader); +impl CR23_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR23_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR23_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR23` writer - Cancellation Request 23"] +pub struct CR23_W<'a> { + w: &'a mut W, +} +impl<'a> CR23_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `CR24` reader - Cancellation Request 24"] +pub struct CR24_R(crate::FieldReader); +impl CR24_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR24_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR24_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR24` writer - Cancellation Request 24"] +pub struct CR24_W<'a> { + w: &'a mut W, +} +impl<'a> CR24_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `CR25` reader - Cancellation Request 25"] +pub struct CR25_R(crate::FieldReader); +impl CR25_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR25_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR25_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR25` writer - Cancellation Request 25"] +pub struct CR25_W<'a> { + w: &'a mut W, +} +impl<'a> CR25_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `CR26` reader - Cancellation Request 26"] +pub struct CR26_R(crate::FieldReader); +impl CR26_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR26_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR26_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR26` writer - Cancellation Request 26"] +pub struct CR26_W<'a> { + w: &'a mut W, +} +impl<'a> CR26_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `CR27` reader - Cancellation Request 27"] +pub struct CR27_R(crate::FieldReader); +impl CR27_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR27_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR27_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR27` writer - Cancellation Request 27"] +pub struct CR27_W<'a> { + w: &'a mut W, +} +impl<'a> CR27_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +#[doc = "Field `CR28` reader - Cancellation Request 28"] +pub struct CR28_R(crate::FieldReader); +impl CR28_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR28_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR28_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR28` writer - Cancellation Request 28"] +pub struct CR28_W<'a> { + w: &'a mut W, +} +impl<'a> CR28_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Field `CR29` reader - Cancellation Request 29"] +pub struct CR29_R(crate::FieldReader); +impl CR29_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR29_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR29_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR29` writer - Cancellation Request 29"] +pub struct CR29_W<'a> { + w: &'a mut W, +} +impl<'a> CR29_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29); + self.w + } +} +#[doc = "Field `CR30` reader - Cancellation Request 30"] +pub struct CR30_R(crate::FieldReader); +impl CR30_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR30_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR30_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR30` writer - Cancellation Request 30"] +pub struct CR30_W<'a> { + w: &'a mut W, +} +impl<'a> CR30_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +#[doc = "Field `CR31` reader - Cancellation Request 31"] +pub struct CR31_R(crate::FieldReader); +impl CR31_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR31_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR31_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR31` writer - Cancellation Request 31"] +pub struct CR31_W<'a> { + w: &'a mut W, +} +impl<'a> CR31_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bit 0 - Cancellation Request 0"] + #[inline(always)] + pub fn cr0(&self) -> CR0_R { + CR0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Cancellation Request 1"] + #[inline(always)] + pub fn cr1(&self) -> CR1_R { + CR1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Cancellation Request 2"] + #[inline(always)] + pub fn cr2(&self) -> CR2_R { + CR2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Cancellation Request 3"] + #[inline(always)] + pub fn cr3(&self) -> CR3_R { + CR3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Cancellation Request 4"] + #[inline(always)] + pub fn cr4(&self) -> CR4_R { + CR4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Cancellation Request 5"] + #[inline(always)] + pub fn cr5(&self) -> CR5_R { + CR5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Cancellation Request 6"] + #[inline(always)] + pub fn cr6(&self) -> CR6_R { + CR6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Cancellation Request 7"] + #[inline(always)] + pub fn cr7(&self) -> CR7_R { + CR7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Cancellation Request 8"] + #[inline(always)] + pub fn cr8(&self) -> CR8_R { + CR8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Cancellation Request 9"] + #[inline(always)] + pub fn cr9(&self) -> CR9_R { + CR9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Cancellation Request 10"] + #[inline(always)] + pub fn cr10(&self) -> CR10_R { + CR10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Cancellation Request 11"] + #[inline(always)] + pub fn cr11(&self) -> CR11_R { + CR11_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Cancellation Request 12"] + #[inline(always)] + pub fn cr12(&self) -> CR12_R { + CR12_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Cancellation Request 13"] + #[inline(always)] + pub fn cr13(&self) -> CR13_R { + CR13_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Cancellation Request 14"] + #[inline(always)] + pub fn cr14(&self) -> CR14_R { + CR14_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Cancellation Request 15"] + #[inline(always)] + pub fn cr15(&self) -> CR15_R { + CR15_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Cancellation Request 16"] + #[inline(always)] + pub fn cr16(&self) -> CR16_R { + CR16_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Cancellation Request 17"] + #[inline(always)] + pub fn cr17(&self) -> CR17_R { + CR17_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Cancellation Request 18"] + #[inline(always)] + pub fn cr18(&self) -> CR18_R { + CR18_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Cancellation Request 19"] + #[inline(always)] + pub fn cr19(&self) -> CR19_R { + CR19_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Cancellation Request 20"] + #[inline(always)] + pub fn cr20(&self) -> CR20_R { + CR20_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Cancellation Request 21"] + #[inline(always)] + pub fn cr21(&self) -> CR21_R { + CR21_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Cancellation Request 22"] + #[inline(always)] + pub fn cr22(&self) -> CR22_R { + CR22_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Cancellation Request 23"] + #[inline(always)] + pub fn cr23(&self) -> CR23_R { + CR23_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24 - Cancellation Request 24"] + #[inline(always)] + pub fn cr24(&self) -> CR24_R { + CR24_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Cancellation Request 25"] + #[inline(always)] + pub fn cr25(&self) -> CR25_R { + CR25_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Cancellation Request 26"] + #[inline(always)] + pub fn cr26(&self) -> CR26_R { + CR26_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Cancellation Request 27"] + #[inline(always)] + pub fn cr27(&self) -> CR27_R { + CR27_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28 - Cancellation Request 28"] + #[inline(always)] + pub fn cr28(&self) -> CR28_R { + CR28_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Cancellation Request 29"] + #[inline(always)] + pub fn cr29(&self) -> CR29_R { + CR29_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - Cancellation Request 30"] + #[inline(always)] + pub fn cr30(&self) -> CR30_R { + CR30_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 31 - Cancellation Request 31"] + #[inline(always)] + pub fn cr31(&self) -> CR31_R { + CR31_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Cancellation Request 0"] + #[inline(always)] + pub fn cr0(&mut self) -> CR0_W { + CR0_W { w: self } + } + #[doc = "Bit 1 - Cancellation Request 1"] + #[inline(always)] + pub fn cr1(&mut self) -> CR1_W { + CR1_W { w: self } + } + #[doc = "Bit 2 - Cancellation Request 2"] + #[inline(always)] + pub fn cr2(&mut self) -> CR2_W { + CR2_W { w: self } + } + #[doc = "Bit 3 - Cancellation Request 3"] + #[inline(always)] + pub fn cr3(&mut self) -> CR3_W { + CR3_W { w: self } + } + #[doc = "Bit 4 - Cancellation Request 4"] + #[inline(always)] + pub fn cr4(&mut self) -> CR4_W { + CR4_W { w: self } + } + #[doc = "Bit 5 - Cancellation Request 5"] + #[inline(always)] + pub fn cr5(&mut self) -> CR5_W { + CR5_W { w: self } + } + #[doc = "Bit 6 - Cancellation Request 6"] + #[inline(always)] + pub fn cr6(&mut self) -> CR6_W { + CR6_W { w: self } + } + #[doc = "Bit 7 - Cancellation Request 7"] + #[inline(always)] + pub fn cr7(&mut self) -> CR7_W { + CR7_W { w: self } + } + #[doc = "Bit 8 - Cancellation Request 8"] + #[inline(always)] + pub fn cr8(&mut self) -> CR8_W { + CR8_W { w: self } + } + #[doc = "Bit 9 - Cancellation Request 9"] + #[inline(always)] + pub fn cr9(&mut self) -> CR9_W { + CR9_W { w: self } + } + #[doc = "Bit 10 - Cancellation Request 10"] + #[inline(always)] + pub fn cr10(&mut self) -> CR10_W { + CR10_W { w: self } + } + #[doc = "Bit 11 - Cancellation Request 11"] + #[inline(always)] + pub fn cr11(&mut self) -> CR11_W { + CR11_W { w: self } + } + #[doc = "Bit 12 - Cancellation Request 12"] + #[inline(always)] + pub fn cr12(&mut self) -> CR12_W { + CR12_W { w: self } + } + #[doc = "Bit 13 - Cancellation Request 13"] + #[inline(always)] + pub fn cr13(&mut self) -> CR13_W { + CR13_W { w: self } + } + #[doc = "Bit 14 - Cancellation Request 14"] + #[inline(always)] + pub fn cr14(&mut self) -> CR14_W { + CR14_W { w: self } + } + #[doc = "Bit 15 - Cancellation Request 15"] + #[inline(always)] + pub fn cr15(&mut self) -> CR15_W { + CR15_W { w: self } + } + #[doc = "Bit 16 - Cancellation Request 16"] + #[inline(always)] + pub fn cr16(&mut self) -> CR16_W { + CR16_W { w: self } + } + #[doc = "Bit 17 - Cancellation Request 17"] + #[inline(always)] + pub fn cr17(&mut self) -> CR17_W { + CR17_W { w: self } + } + #[doc = "Bit 18 - Cancellation Request 18"] + #[inline(always)] + pub fn cr18(&mut self) -> CR18_W { + CR18_W { w: self } + } + #[doc = "Bit 19 - Cancellation Request 19"] + #[inline(always)] + pub fn cr19(&mut self) -> CR19_W { + CR19_W { w: self } + } + #[doc = "Bit 20 - Cancellation Request 20"] + #[inline(always)] + pub fn cr20(&mut self) -> CR20_W { + CR20_W { w: self } + } + #[doc = "Bit 21 - Cancellation Request 21"] + #[inline(always)] + pub fn cr21(&mut self) -> CR21_W { + CR21_W { w: self } + } + #[doc = "Bit 22 - Cancellation Request 22"] + #[inline(always)] + pub fn cr22(&mut self) -> CR22_W { + CR22_W { w: self } + } + #[doc = "Bit 23 - Cancellation Request 23"] + #[inline(always)] + pub fn cr23(&mut self) -> CR23_W { + CR23_W { w: self } + } + #[doc = "Bit 24 - Cancellation Request 24"] + #[inline(always)] + pub fn cr24(&mut self) -> CR24_W { + CR24_W { w: self } + } + #[doc = "Bit 25 - Cancellation Request 25"] + #[inline(always)] + pub fn cr25(&mut self) -> CR25_W { + CR25_W { w: self } + } + #[doc = "Bit 26 - Cancellation Request 26"] + #[inline(always)] + pub fn cr26(&mut self) -> CR26_W { + CR26_W { w: self } + } + #[doc = "Bit 27 - Cancellation Request 27"] + #[inline(always)] + pub fn cr27(&mut self) -> CR27_W { + CR27_W { w: self } + } + #[doc = "Bit 28 - Cancellation Request 28"] + #[inline(always)] + pub fn cr28(&mut self) -> CR28_W { + CR28_W { w: self } + } + #[doc = "Bit 29 - Cancellation Request 29"] + #[inline(always)] + pub fn cr29(&mut self) -> CR29_W { + CR29_W { w: self } + } + #[doc = "Bit 30 - Cancellation Request 30"] + #[inline(always)] + pub fn cr30(&mut self) -> CR30_W { + CR30_W { w: self } + } + #[doc = "Bit 31 - Cancellation Request 31"] + #[inline(always)] + pub fn cr31(&mut self) -> CR31_W { + CR31_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Tx Buffer Cancellation Request\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txbcr](index.html) module"] +pub struct TXBCR_SPEC; +impl crate::RegisterSpec for TXBCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [txbcr::R](R) reader structure"] +impl crate::Readable for TXBCR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [txbcr::W](W) writer structure"] +impl crate::Writable for TXBCR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TXBCR to value 0"] +impl crate::Resettable for TXBCR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/can0/txbrp.rs b/pac/atsamc21j/src/can0/txbrp.rs new file mode 100644 index 000000000000..9be5da39419d --- /dev/null +++ b/pac/atsamc21j/src/can0/txbrp.rs @@ -0,0 +1,673 @@ +#[doc = "Register `TXBRP` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `TRP0` reader - Transmission Request Pending 0"] +pub struct TRP0_R(crate::FieldReader); +impl TRP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP1` reader - Transmission Request Pending 1"] +pub struct TRP1_R(crate::FieldReader); +impl TRP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP2` reader - Transmission Request Pending 2"] +pub struct TRP2_R(crate::FieldReader); +impl TRP2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP3` reader - Transmission Request Pending 3"] +pub struct TRP3_R(crate::FieldReader); +impl TRP3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP4` reader - Transmission Request Pending 4"] +pub struct TRP4_R(crate::FieldReader); +impl TRP4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP5` reader - Transmission Request Pending 5"] +pub struct TRP5_R(crate::FieldReader); +impl TRP5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP6` reader - Transmission Request Pending 6"] +pub struct TRP6_R(crate::FieldReader); +impl TRP6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP7` reader - Transmission Request Pending 7"] +pub struct TRP7_R(crate::FieldReader); +impl TRP7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP8` reader - Transmission Request Pending 8"] +pub struct TRP8_R(crate::FieldReader); +impl TRP8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP9` reader - Transmission Request Pending 9"] +pub struct TRP9_R(crate::FieldReader); +impl TRP9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP10` reader - Transmission Request Pending 10"] +pub struct TRP10_R(crate::FieldReader); +impl TRP10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP11` reader - Transmission Request Pending 11"] +pub struct TRP11_R(crate::FieldReader); +impl TRP11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP12` reader - Transmission Request Pending 12"] +pub struct TRP12_R(crate::FieldReader); +impl TRP12_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP12_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP12_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP13` reader - Transmission Request Pending 13"] +pub struct TRP13_R(crate::FieldReader); +impl TRP13_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP13_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP13_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP14` reader - Transmission Request Pending 14"] +pub struct TRP14_R(crate::FieldReader); +impl TRP14_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP14_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP14_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP15` reader - Transmission Request Pending 15"] +pub struct TRP15_R(crate::FieldReader); +impl TRP15_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP15_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP15_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP16` reader - Transmission Request Pending 16"] +pub struct TRP16_R(crate::FieldReader); +impl TRP16_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP16_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP16_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP17` reader - Transmission Request Pending 17"] +pub struct TRP17_R(crate::FieldReader); +impl TRP17_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP17_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP17_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP18` reader - Transmission Request Pending 18"] +pub struct TRP18_R(crate::FieldReader); +impl TRP18_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP18_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP18_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP19` reader - Transmission Request Pending 19"] +pub struct TRP19_R(crate::FieldReader); +impl TRP19_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP19_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP19_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP20` reader - Transmission Request Pending 20"] +pub struct TRP20_R(crate::FieldReader); +impl TRP20_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP20_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP20_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP21` reader - Transmission Request Pending 21"] +pub struct TRP21_R(crate::FieldReader); +impl TRP21_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP21_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP21_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP22` reader - Transmission Request Pending 22"] +pub struct TRP22_R(crate::FieldReader); +impl TRP22_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP22_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP22_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP23` reader - Transmission Request Pending 23"] +pub struct TRP23_R(crate::FieldReader); +impl TRP23_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP23_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP23_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP24` reader - Transmission Request Pending 24"] +pub struct TRP24_R(crate::FieldReader); +impl TRP24_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP24_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP24_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP25` reader - Transmission Request Pending 25"] +pub struct TRP25_R(crate::FieldReader); +impl TRP25_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP25_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP25_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP26` reader - Transmission Request Pending 26"] +pub struct TRP26_R(crate::FieldReader); +impl TRP26_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP26_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP26_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP27` reader - Transmission Request Pending 27"] +pub struct TRP27_R(crate::FieldReader); +impl TRP27_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP27_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP27_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP28` reader - Transmission Request Pending 28"] +pub struct TRP28_R(crate::FieldReader); +impl TRP28_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP28_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP28_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP29` reader - Transmission Request Pending 29"] +pub struct TRP29_R(crate::FieldReader); +impl TRP29_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP29_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP29_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP30` reader - Transmission Request Pending 30"] +pub struct TRP30_R(crate::FieldReader); +impl TRP30_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP30_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP30_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP31` reader - Transmission Request Pending 31"] +pub struct TRP31_R(crate::FieldReader); +impl TRP31_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP31_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP31_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Transmission Request Pending 0"] + #[inline(always)] + pub fn trp0(&self) -> TRP0_R { + TRP0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmission Request Pending 1"] + #[inline(always)] + pub fn trp1(&self) -> TRP1_R { + TRP1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Transmission Request Pending 2"] + #[inline(always)] + pub fn trp2(&self) -> TRP2_R { + TRP2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Transmission Request Pending 3"] + #[inline(always)] + pub fn trp3(&self) -> TRP3_R { + TRP3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Transmission Request Pending 4"] + #[inline(always)] + pub fn trp4(&self) -> TRP4_R { + TRP4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Transmission Request Pending 5"] + #[inline(always)] + pub fn trp5(&self) -> TRP5_R { + TRP5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Transmission Request Pending 6"] + #[inline(always)] + pub fn trp6(&self) -> TRP6_R { + TRP6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Transmission Request Pending 7"] + #[inline(always)] + pub fn trp7(&self) -> TRP7_R { + TRP7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Transmission Request Pending 8"] + #[inline(always)] + pub fn trp8(&self) -> TRP8_R { + TRP8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Transmission Request Pending 9"] + #[inline(always)] + pub fn trp9(&self) -> TRP9_R { + TRP9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Transmission Request Pending 10"] + #[inline(always)] + pub fn trp10(&self) -> TRP10_R { + TRP10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Transmission Request Pending 11"] + #[inline(always)] + pub fn trp11(&self) -> TRP11_R { + TRP11_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Transmission Request Pending 12"] + #[inline(always)] + pub fn trp12(&self) -> TRP12_R { + TRP12_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Transmission Request Pending 13"] + #[inline(always)] + pub fn trp13(&self) -> TRP13_R { + TRP13_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Transmission Request Pending 14"] + #[inline(always)] + pub fn trp14(&self) -> TRP14_R { + TRP14_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Transmission Request Pending 15"] + #[inline(always)] + pub fn trp15(&self) -> TRP15_R { + TRP15_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Transmission Request Pending 16"] + #[inline(always)] + pub fn trp16(&self) -> TRP16_R { + TRP16_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Transmission Request Pending 17"] + #[inline(always)] + pub fn trp17(&self) -> TRP17_R { + TRP17_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Transmission Request Pending 18"] + #[inline(always)] + pub fn trp18(&self) -> TRP18_R { + TRP18_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Transmission Request Pending 19"] + #[inline(always)] + pub fn trp19(&self) -> TRP19_R { + TRP19_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Transmission Request Pending 20"] + #[inline(always)] + pub fn trp20(&self) -> TRP20_R { + TRP20_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Transmission Request Pending 21"] + #[inline(always)] + pub fn trp21(&self) -> TRP21_R { + TRP21_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Transmission Request Pending 22"] + #[inline(always)] + pub fn trp22(&self) -> TRP22_R { + TRP22_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Transmission Request Pending 23"] + #[inline(always)] + pub fn trp23(&self) -> TRP23_R { + TRP23_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24 - Transmission Request Pending 24"] + #[inline(always)] + pub fn trp24(&self) -> TRP24_R { + TRP24_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Transmission Request Pending 25"] + #[inline(always)] + pub fn trp25(&self) -> TRP25_R { + TRP25_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Transmission Request Pending 26"] + #[inline(always)] + pub fn trp26(&self) -> TRP26_R { + TRP26_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Transmission Request Pending 27"] + #[inline(always)] + pub fn trp27(&self) -> TRP27_R { + TRP27_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28 - Transmission Request Pending 28"] + #[inline(always)] + pub fn trp28(&self) -> TRP28_R { + TRP28_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Transmission Request Pending 29"] + #[inline(always)] + pub fn trp29(&self) -> TRP29_R { + TRP29_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - Transmission Request Pending 30"] + #[inline(always)] + pub fn trp30(&self) -> TRP30_R { + TRP30_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 31 - Transmission Request Pending 31"] + #[inline(always)] + pub fn trp31(&self) -> TRP31_R { + TRP31_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +#[doc = "Tx Buffer Request Pending\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txbrp](index.html) module"] +pub struct TXBRP_SPEC; +impl crate::RegisterSpec for TXBRP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [txbrp::R](R) reader structure"] +impl crate::Readable for TXBRP_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets TXBRP to value 0"] +impl crate::Resettable for TXBRP_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/can0/txbtie.rs b/pac/atsamc21j/src/can0/txbtie.rs new file mode 100644 index 000000000000..ed808faba7a1 --- /dev/null +++ b/pac/atsamc21j/src/can0/txbtie.rs @@ -0,0 +1,1570 @@ +#[doc = "Register `TXBTIE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TXBTIE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TIE0` reader - Transmission Interrupt Enable 0"] +pub struct TIE0_R(crate::FieldReader); +impl TIE0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE0` writer - Transmission Interrupt Enable 0"] +pub struct TIE0_W<'a> { + w: &'a mut W, +} +impl<'a> TIE0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `TIE1` reader - Transmission Interrupt Enable 1"] +pub struct TIE1_R(crate::FieldReader); +impl TIE1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE1` writer - Transmission Interrupt Enable 1"] +pub struct TIE1_W<'a> { + w: &'a mut W, +} +impl<'a> TIE1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `TIE2` reader - Transmission Interrupt Enable 2"] +pub struct TIE2_R(crate::FieldReader); +impl TIE2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE2` writer - Transmission Interrupt Enable 2"] +pub struct TIE2_W<'a> { + w: &'a mut W, +} +impl<'a> TIE2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `TIE3` reader - Transmission Interrupt Enable 3"] +pub struct TIE3_R(crate::FieldReader); +impl TIE3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE3` writer - Transmission Interrupt Enable 3"] +pub struct TIE3_W<'a> { + w: &'a mut W, +} +impl<'a> TIE3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `TIE4` reader - Transmission Interrupt Enable 4"] +pub struct TIE4_R(crate::FieldReader); +impl TIE4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE4` writer - Transmission Interrupt Enable 4"] +pub struct TIE4_W<'a> { + w: &'a mut W, +} +impl<'a> TIE4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `TIE5` reader - Transmission Interrupt Enable 5"] +pub struct TIE5_R(crate::FieldReader); +impl TIE5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE5` writer - Transmission Interrupt Enable 5"] +pub struct TIE5_W<'a> { + w: &'a mut W, +} +impl<'a> TIE5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `TIE6` reader - Transmission Interrupt Enable 6"] +pub struct TIE6_R(crate::FieldReader); +impl TIE6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE6` writer - Transmission Interrupt Enable 6"] +pub struct TIE6_W<'a> { + w: &'a mut W, +} +impl<'a> TIE6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `TIE7` reader - Transmission Interrupt Enable 7"] +pub struct TIE7_R(crate::FieldReader); +impl TIE7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE7` writer - Transmission Interrupt Enable 7"] +pub struct TIE7_W<'a> { + w: &'a mut W, +} +impl<'a> TIE7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `TIE8` reader - Transmission Interrupt Enable 8"] +pub struct TIE8_R(crate::FieldReader); +impl TIE8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE8` writer - Transmission Interrupt Enable 8"] +pub struct TIE8_W<'a> { + w: &'a mut W, +} +impl<'a> TIE8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `TIE9` reader - Transmission Interrupt Enable 9"] +pub struct TIE9_R(crate::FieldReader); +impl TIE9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE9` writer - Transmission Interrupt Enable 9"] +pub struct TIE9_W<'a> { + w: &'a mut W, +} +impl<'a> TIE9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `TIE10` reader - Transmission Interrupt Enable 10"] +pub struct TIE10_R(crate::FieldReader); +impl TIE10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE10` writer - Transmission Interrupt Enable 10"] +pub struct TIE10_W<'a> { + w: &'a mut W, +} +impl<'a> TIE10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `TIE11` reader - Transmission Interrupt Enable 11"] +pub struct TIE11_R(crate::FieldReader); +impl TIE11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE11` writer - Transmission Interrupt Enable 11"] +pub struct TIE11_W<'a> { + w: &'a mut W, +} +impl<'a> TIE11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `TIE12` reader - Transmission Interrupt Enable 12"] +pub struct TIE12_R(crate::FieldReader); +impl TIE12_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE12_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE12_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE12` writer - Transmission Interrupt Enable 12"] +pub struct TIE12_W<'a> { + w: &'a mut W, +} +impl<'a> TIE12_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `TIE13` reader - Transmission Interrupt Enable 13"] +pub struct TIE13_R(crate::FieldReader); +impl TIE13_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE13_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE13_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE13` writer - Transmission Interrupt Enable 13"] +pub struct TIE13_W<'a> { + w: &'a mut W, +} +impl<'a> TIE13_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `TIE14` reader - Transmission Interrupt Enable 14"] +pub struct TIE14_R(crate::FieldReader); +impl TIE14_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE14_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE14_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE14` writer - Transmission Interrupt Enable 14"] +pub struct TIE14_W<'a> { + w: &'a mut W, +} +impl<'a> TIE14_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `TIE15` reader - Transmission Interrupt Enable 15"] +pub struct TIE15_R(crate::FieldReader); +impl TIE15_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE15_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE15_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE15` writer - Transmission Interrupt Enable 15"] +pub struct TIE15_W<'a> { + w: &'a mut W, +} +impl<'a> TIE15_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `TIE16` reader - Transmission Interrupt Enable 16"] +pub struct TIE16_R(crate::FieldReader); +impl TIE16_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE16_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE16_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE16` writer - Transmission Interrupt Enable 16"] +pub struct TIE16_W<'a> { + w: &'a mut W, +} +impl<'a> TIE16_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `TIE17` reader - Transmission Interrupt Enable 17"] +pub struct TIE17_R(crate::FieldReader); +impl TIE17_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE17_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE17_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE17` writer - Transmission Interrupt Enable 17"] +pub struct TIE17_W<'a> { + w: &'a mut W, +} +impl<'a> TIE17_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `TIE18` reader - Transmission Interrupt Enable 18"] +pub struct TIE18_R(crate::FieldReader); +impl TIE18_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE18_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE18_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE18` writer - Transmission Interrupt Enable 18"] +pub struct TIE18_W<'a> { + w: &'a mut W, +} +impl<'a> TIE18_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `TIE19` reader - Transmission Interrupt Enable 19"] +pub struct TIE19_R(crate::FieldReader); +impl TIE19_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE19_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE19_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE19` writer - Transmission Interrupt Enable 19"] +pub struct TIE19_W<'a> { + w: &'a mut W, +} +impl<'a> TIE19_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `TIE20` reader - Transmission Interrupt Enable 20"] +pub struct TIE20_R(crate::FieldReader); +impl TIE20_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE20_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE20_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE20` writer - Transmission Interrupt Enable 20"] +pub struct TIE20_W<'a> { + w: &'a mut W, +} +impl<'a> TIE20_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `TIE21` reader - Transmission Interrupt Enable 21"] +pub struct TIE21_R(crate::FieldReader); +impl TIE21_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE21_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE21_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE21` writer - Transmission Interrupt Enable 21"] +pub struct TIE21_W<'a> { + w: &'a mut W, +} +impl<'a> TIE21_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `TIE22` reader - Transmission Interrupt Enable 22"] +pub struct TIE22_R(crate::FieldReader); +impl TIE22_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE22_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE22_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE22` writer - Transmission Interrupt Enable 22"] +pub struct TIE22_W<'a> { + w: &'a mut W, +} +impl<'a> TIE22_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `TIE23` reader - Transmission Interrupt Enable 23"] +pub struct TIE23_R(crate::FieldReader); +impl TIE23_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE23_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE23_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE23` writer - Transmission Interrupt Enable 23"] +pub struct TIE23_W<'a> { + w: &'a mut W, +} +impl<'a> TIE23_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `TIE24` reader - Transmission Interrupt Enable 24"] +pub struct TIE24_R(crate::FieldReader); +impl TIE24_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE24_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE24_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE24` writer - Transmission Interrupt Enable 24"] +pub struct TIE24_W<'a> { + w: &'a mut W, +} +impl<'a> TIE24_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `TIE25` reader - Transmission Interrupt Enable 25"] +pub struct TIE25_R(crate::FieldReader); +impl TIE25_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE25_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE25_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE25` writer - Transmission Interrupt Enable 25"] +pub struct TIE25_W<'a> { + w: &'a mut W, +} +impl<'a> TIE25_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `TIE26` reader - Transmission Interrupt Enable 26"] +pub struct TIE26_R(crate::FieldReader); +impl TIE26_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE26_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE26_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE26` writer - Transmission Interrupt Enable 26"] +pub struct TIE26_W<'a> { + w: &'a mut W, +} +impl<'a> TIE26_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `TIE27` reader - Transmission Interrupt Enable 27"] +pub struct TIE27_R(crate::FieldReader); +impl TIE27_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE27_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE27_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE27` writer - Transmission Interrupt Enable 27"] +pub struct TIE27_W<'a> { + w: &'a mut W, +} +impl<'a> TIE27_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +#[doc = "Field `TIE28` reader - Transmission Interrupt Enable 28"] +pub struct TIE28_R(crate::FieldReader); +impl TIE28_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE28_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE28_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE28` writer - Transmission Interrupt Enable 28"] +pub struct TIE28_W<'a> { + w: &'a mut W, +} +impl<'a> TIE28_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Field `TIE29` reader - Transmission Interrupt Enable 29"] +pub struct TIE29_R(crate::FieldReader); +impl TIE29_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE29_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE29_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE29` writer - Transmission Interrupt Enable 29"] +pub struct TIE29_W<'a> { + w: &'a mut W, +} +impl<'a> TIE29_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29); + self.w + } +} +#[doc = "Field `TIE30` reader - Transmission Interrupt Enable 30"] +pub struct TIE30_R(crate::FieldReader); +impl TIE30_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE30_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE30_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE30` writer - Transmission Interrupt Enable 30"] +pub struct TIE30_W<'a> { + w: &'a mut W, +} +impl<'a> TIE30_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +#[doc = "Field `TIE31` reader - Transmission Interrupt Enable 31"] +pub struct TIE31_R(crate::FieldReader); +impl TIE31_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE31_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE31_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE31` writer - Transmission Interrupt Enable 31"] +pub struct TIE31_W<'a> { + w: &'a mut W, +} +impl<'a> TIE31_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bit 0 - Transmission Interrupt Enable 0"] + #[inline(always)] + pub fn tie0(&self) -> TIE0_R { + TIE0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmission Interrupt Enable 1"] + #[inline(always)] + pub fn tie1(&self) -> TIE1_R { + TIE1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Transmission Interrupt Enable 2"] + #[inline(always)] + pub fn tie2(&self) -> TIE2_R { + TIE2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Transmission Interrupt Enable 3"] + #[inline(always)] + pub fn tie3(&self) -> TIE3_R { + TIE3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Transmission Interrupt Enable 4"] + #[inline(always)] + pub fn tie4(&self) -> TIE4_R { + TIE4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Transmission Interrupt Enable 5"] + #[inline(always)] + pub fn tie5(&self) -> TIE5_R { + TIE5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Transmission Interrupt Enable 6"] + #[inline(always)] + pub fn tie6(&self) -> TIE6_R { + TIE6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Transmission Interrupt Enable 7"] + #[inline(always)] + pub fn tie7(&self) -> TIE7_R { + TIE7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Transmission Interrupt Enable 8"] + #[inline(always)] + pub fn tie8(&self) -> TIE8_R { + TIE8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Transmission Interrupt Enable 9"] + #[inline(always)] + pub fn tie9(&self) -> TIE9_R { + TIE9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Transmission Interrupt Enable 10"] + #[inline(always)] + pub fn tie10(&self) -> TIE10_R { + TIE10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Transmission Interrupt Enable 11"] + #[inline(always)] + pub fn tie11(&self) -> TIE11_R { + TIE11_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Transmission Interrupt Enable 12"] + #[inline(always)] + pub fn tie12(&self) -> TIE12_R { + TIE12_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Transmission Interrupt Enable 13"] + #[inline(always)] + pub fn tie13(&self) -> TIE13_R { + TIE13_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Transmission Interrupt Enable 14"] + #[inline(always)] + pub fn tie14(&self) -> TIE14_R { + TIE14_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Transmission Interrupt Enable 15"] + #[inline(always)] + pub fn tie15(&self) -> TIE15_R { + TIE15_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Transmission Interrupt Enable 16"] + #[inline(always)] + pub fn tie16(&self) -> TIE16_R { + TIE16_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Transmission Interrupt Enable 17"] + #[inline(always)] + pub fn tie17(&self) -> TIE17_R { + TIE17_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Transmission Interrupt Enable 18"] + #[inline(always)] + pub fn tie18(&self) -> TIE18_R { + TIE18_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Transmission Interrupt Enable 19"] + #[inline(always)] + pub fn tie19(&self) -> TIE19_R { + TIE19_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Transmission Interrupt Enable 20"] + #[inline(always)] + pub fn tie20(&self) -> TIE20_R { + TIE20_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Transmission Interrupt Enable 21"] + #[inline(always)] + pub fn tie21(&self) -> TIE21_R { + TIE21_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Transmission Interrupt Enable 22"] + #[inline(always)] + pub fn tie22(&self) -> TIE22_R { + TIE22_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Transmission Interrupt Enable 23"] + #[inline(always)] + pub fn tie23(&self) -> TIE23_R { + TIE23_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24 - Transmission Interrupt Enable 24"] + #[inline(always)] + pub fn tie24(&self) -> TIE24_R { + TIE24_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Transmission Interrupt Enable 25"] + #[inline(always)] + pub fn tie25(&self) -> TIE25_R { + TIE25_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Transmission Interrupt Enable 26"] + #[inline(always)] + pub fn tie26(&self) -> TIE26_R { + TIE26_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Transmission Interrupt Enable 27"] + #[inline(always)] + pub fn tie27(&self) -> TIE27_R { + TIE27_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28 - Transmission Interrupt Enable 28"] + #[inline(always)] + pub fn tie28(&self) -> TIE28_R { + TIE28_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Transmission Interrupt Enable 29"] + #[inline(always)] + pub fn tie29(&self) -> TIE29_R { + TIE29_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - Transmission Interrupt Enable 30"] + #[inline(always)] + pub fn tie30(&self) -> TIE30_R { + TIE30_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 31 - Transmission Interrupt Enable 31"] + #[inline(always)] + pub fn tie31(&self) -> TIE31_R { + TIE31_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Transmission Interrupt Enable 0"] + #[inline(always)] + pub fn tie0(&mut self) -> TIE0_W { + TIE0_W { w: self } + } + #[doc = "Bit 1 - Transmission Interrupt Enable 1"] + #[inline(always)] + pub fn tie1(&mut self) -> TIE1_W { + TIE1_W { w: self } + } + #[doc = "Bit 2 - Transmission Interrupt Enable 2"] + #[inline(always)] + pub fn tie2(&mut self) -> TIE2_W { + TIE2_W { w: self } + } + #[doc = "Bit 3 - Transmission Interrupt Enable 3"] + #[inline(always)] + pub fn tie3(&mut self) -> TIE3_W { + TIE3_W { w: self } + } + #[doc = "Bit 4 - Transmission Interrupt Enable 4"] + #[inline(always)] + pub fn tie4(&mut self) -> TIE4_W { + TIE4_W { w: self } + } + #[doc = "Bit 5 - Transmission Interrupt Enable 5"] + #[inline(always)] + pub fn tie5(&mut self) -> TIE5_W { + TIE5_W { w: self } + } + #[doc = "Bit 6 - Transmission Interrupt Enable 6"] + #[inline(always)] + pub fn tie6(&mut self) -> TIE6_W { + TIE6_W { w: self } + } + #[doc = "Bit 7 - Transmission Interrupt Enable 7"] + #[inline(always)] + pub fn tie7(&mut self) -> TIE7_W { + TIE7_W { w: self } + } + #[doc = "Bit 8 - Transmission Interrupt Enable 8"] + #[inline(always)] + pub fn tie8(&mut self) -> TIE8_W { + TIE8_W { w: self } + } + #[doc = "Bit 9 - Transmission Interrupt Enable 9"] + #[inline(always)] + pub fn tie9(&mut self) -> TIE9_W { + TIE9_W { w: self } + } + #[doc = "Bit 10 - Transmission Interrupt Enable 10"] + #[inline(always)] + pub fn tie10(&mut self) -> TIE10_W { + TIE10_W { w: self } + } + #[doc = "Bit 11 - Transmission Interrupt Enable 11"] + #[inline(always)] + pub fn tie11(&mut self) -> TIE11_W { + TIE11_W { w: self } + } + #[doc = "Bit 12 - Transmission Interrupt Enable 12"] + #[inline(always)] + pub fn tie12(&mut self) -> TIE12_W { + TIE12_W { w: self } + } + #[doc = "Bit 13 - Transmission Interrupt Enable 13"] + #[inline(always)] + pub fn tie13(&mut self) -> TIE13_W { + TIE13_W { w: self } + } + #[doc = "Bit 14 - Transmission Interrupt Enable 14"] + #[inline(always)] + pub fn tie14(&mut self) -> TIE14_W { + TIE14_W { w: self } + } + #[doc = "Bit 15 - Transmission Interrupt Enable 15"] + #[inline(always)] + pub fn tie15(&mut self) -> TIE15_W { + TIE15_W { w: self } + } + #[doc = "Bit 16 - Transmission Interrupt Enable 16"] + #[inline(always)] + pub fn tie16(&mut self) -> TIE16_W { + TIE16_W { w: self } + } + #[doc = "Bit 17 - Transmission Interrupt Enable 17"] + #[inline(always)] + pub fn tie17(&mut self) -> TIE17_W { + TIE17_W { w: self } + } + #[doc = "Bit 18 - Transmission Interrupt Enable 18"] + #[inline(always)] + pub fn tie18(&mut self) -> TIE18_W { + TIE18_W { w: self } + } + #[doc = "Bit 19 - Transmission Interrupt Enable 19"] + #[inline(always)] + pub fn tie19(&mut self) -> TIE19_W { + TIE19_W { w: self } + } + #[doc = "Bit 20 - Transmission Interrupt Enable 20"] + #[inline(always)] + pub fn tie20(&mut self) -> TIE20_W { + TIE20_W { w: self } + } + #[doc = "Bit 21 - Transmission Interrupt Enable 21"] + #[inline(always)] + pub fn tie21(&mut self) -> TIE21_W { + TIE21_W { w: self } + } + #[doc = "Bit 22 - Transmission Interrupt Enable 22"] + #[inline(always)] + pub fn tie22(&mut self) -> TIE22_W { + TIE22_W { w: self } + } + #[doc = "Bit 23 - Transmission Interrupt Enable 23"] + #[inline(always)] + pub fn tie23(&mut self) -> TIE23_W { + TIE23_W { w: self } + } + #[doc = "Bit 24 - Transmission Interrupt Enable 24"] + #[inline(always)] + pub fn tie24(&mut self) -> TIE24_W { + TIE24_W { w: self } + } + #[doc = "Bit 25 - Transmission Interrupt Enable 25"] + #[inline(always)] + pub fn tie25(&mut self) -> TIE25_W { + TIE25_W { w: self } + } + #[doc = "Bit 26 - Transmission Interrupt Enable 26"] + #[inline(always)] + pub fn tie26(&mut self) -> TIE26_W { + TIE26_W { w: self } + } + #[doc = "Bit 27 - Transmission Interrupt Enable 27"] + #[inline(always)] + pub fn tie27(&mut self) -> TIE27_W { + TIE27_W { w: self } + } + #[doc = "Bit 28 - Transmission Interrupt Enable 28"] + #[inline(always)] + pub fn tie28(&mut self) -> TIE28_W { + TIE28_W { w: self } + } + #[doc = "Bit 29 - Transmission Interrupt Enable 29"] + #[inline(always)] + pub fn tie29(&mut self) -> TIE29_W { + TIE29_W { w: self } + } + #[doc = "Bit 30 - Transmission Interrupt Enable 30"] + #[inline(always)] + pub fn tie30(&mut self) -> TIE30_W { + TIE30_W { w: self } + } + #[doc = "Bit 31 - Transmission Interrupt Enable 31"] + #[inline(always)] + pub fn tie31(&mut self) -> TIE31_W { + TIE31_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Tx Buffer Transmission Interrupt Enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txbtie](index.html) module"] +pub struct TXBTIE_SPEC; +impl crate::RegisterSpec for TXBTIE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [txbtie::R](R) reader structure"] +impl crate::Readable for TXBTIE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [txbtie::W](W) writer structure"] +impl crate::Writable for TXBTIE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TXBTIE to value 0"] +impl crate::Resettable for TXBTIE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/can0/txbto.rs b/pac/atsamc21j/src/can0/txbto.rs new file mode 100644 index 000000000000..54bc8f1295ad --- /dev/null +++ b/pac/atsamc21j/src/can0/txbto.rs @@ -0,0 +1,673 @@ +#[doc = "Register `TXBTO` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `TO0` reader - Transmission Occurred 0"] +pub struct TO0_R(crate::FieldReader); +impl TO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO1` reader - Transmission Occurred 1"] +pub struct TO1_R(crate::FieldReader); +impl TO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO2` reader - Transmission Occurred 2"] +pub struct TO2_R(crate::FieldReader); +impl TO2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO3` reader - Transmission Occurred 3"] +pub struct TO3_R(crate::FieldReader); +impl TO3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO4` reader - Transmission Occurred 4"] +pub struct TO4_R(crate::FieldReader); +impl TO4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO5` reader - Transmission Occurred 5"] +pub struct TO5_R(crate::FieldReader); +impl TO5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO6` reader - Transmission Occurred 6"] +pub struct TO6_R(crate::FieldReader); +impl TO6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO7` reader - Transmission Occurred 7"] +pub struct TO7_R(crate::FieldReader); +impl TO7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO8` reader - Transmission Occurred 8"] +pub struct TO8_R(crate::FieldReader); +impl TO8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO9` reader - Transmission Occurred 9"] +pub struct TO9_R(crate::FieldReader); +impl TO9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO10` reader - Transmission Occurred 10"] +pub struct TO10_R(crate::FieldReader); +impl TO10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO11` reader - Transmission Occurred 11"] +pub struct TO11_R(crate::FieldReader); +impl TO11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO12` reader - Transmission Occurred 12"] +pub struct TO12_R(crate::FieldReader); +impl TO12_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO12_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO12_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO13` reader - Transmission Occurred 13"] +pub struct TO13_R(crate::FieldReader); +impl TO13_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO13_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO13_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO14` reader - Transmission Occurred 14"] +pub struct TO14_R(crate::FieldReader); +impl TO14_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO14_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO14_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO15` reader - Transmission Occurred 15"] +pub struct TO15_R(crate::FieldReader); +impl TO15_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO15_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO15_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO16` reader - Transmission Occurred 16"] +pub struct TO16_R(crate::FieldReader); +impl TO16_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO16_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO16_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO17` reader - Transmission Occurred 17"] +pub struct TO17_R(crate::FieldReader); +impl TO17_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO17_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO17_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO18` reader - Transmission Occurred 18"] +pub struct TO18_R(crate::FieldReader); +impl TO18_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO18_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO18_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO19` reader - Transmission Occurred 19"] +pub struct TO19_R(crate::FieldReader); +impl TO19_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO19_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO19_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO20` reader - Transmission Occurred 20"] +pub struct TO20_R(crate::FieldReader); +impl TO20_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO20_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO20_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO21` reader - Transmission Occurred 21"] +pub struct TO21_R(crate::FieldReader); +impl TO21_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO21_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO21_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO22` reader - Transmission Occurred 22"] +pub struct TO22_R(crate::FieldReader); +impl TO22_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO22_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO22_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO23` reader - Transmission Occurred 23"] +pub struct TO23_R(crate::FieldReader); +impl TO23_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO23_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO23_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO24` reader - Transmission Occurred 24"] +pub struct TO24_R(crate::FieldReader); +impl TO24_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO24_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO24_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO25` reader - Transmission Occurred 25"] +pub struct TO25_R(crate::FieldReader); +impl TO25_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO25_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO25_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO26` reader - Transmission Occurred 26"] +pub struct TO26_R(crate::FieldReader); +impl TO26_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO26_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO26_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO27` reader - Transmission Occurred 27"] +pub struct TO27_R(crate::FieldReader); +impl TO27_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO27_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO27_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO28` reader - Transmission Occurred 28"] +pub struct TO28_R(crate::FieldReader); +impl TO28_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO28_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO28_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO29` reader - Transmission Occurred 29"] +pub struct TO29_R(crate::FieldReader); +impl TO29_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO29_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO29_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO30` reader - Transmission Occurred 30"] +pub struct TO30_R(crate::FieldReader); +impl TO30_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO30_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO30_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO31` reader - Transmission Occurred 31"] +pub struct TO31_R(crate::FieldReader); +impl TO31_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO31_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO31_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Transmission Occurred 0"] + #[inline(always)] + pub fn to0(&self) -> TO0_R { + TO0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmission Occurred 1"] + #[inline(always)] + pub fn to1(&self) -> TO1_R { + TO1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Transmission Occurred 2"] + #[inline(always)] + pub fn to2(&self) -> TO2_R { + TO2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Transmission Occurred 3"] + #[inline(always)] + pub fn to3(&self) -> TO3_R { + TO3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Transmission Occurred 4"] + #[inline(always)] + pub fn to4(&self) -> TO4_R { + TO4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Transmission Occurred 5"] + #[inline(always)] + pub fn to5(&self) -> TO5_R { + TO5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Transmission Occurred 6"] + #[inline(always)] + pub fn to6(&self) -> TO6_R { + TO6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Transmission Occurred 7"] + #[inline(always)] + pub fn to7(&self) -> TO7_R { + TO7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Transmission Occurred 8"] + #[inline(always)] + pub fn to8(&self) -> TO8_R { + TO8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Transmission Occurred 9"] + #[inline(always)] + pub fn to9(&self) -> TO9_R { + TO9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Transmission Occurred 10"] + #[inline(always)] + pub fn to10(&self) -> TO10_R { + TO10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Transmission Occurred 11"] + #[inline(always)] + pub fn to11(&self) -> TO11_R { + TO11_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Transmission Occurred 12"] + #[inline(always)] + pub fn to12(&self) -> TO12_R { + TO12_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Transmission Occurred 13"] + #[inline(always)] + pub fn to13(&self) -> TO13_R { + TO13_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Transmission Occurred 14"] + #[inline(always)] + pub fn to14(&self) -> TO14_R { + TO14_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Transmission Occurred 15"] + #[inline(always)] + pub fn to15(&self) -> TO15_R { + TO15_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Transmission Occurred 16"] + #[inline(always)] + pub fn to16(&self) -> TO16_R { + TO16_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Transmission Occurred 17"] + #[inline(always)] + pub fn to17(&self) -> TO17_R { + TO17_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Transmission Occurred 18"] + #[inline(always)] + pub fn to18(&self) -> TO18_R { + TO18_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Transmission Occurred 19"] + #[inline(always)] + pub fn to19(&self) -> TO19_R { + TO19_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Transmission Occurred 20"] + #[inline(always)] + pub fn to20(&self) -> TO20_R { + TO20_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Transmission Occurred 21"] + #[inline(always)] + pub fn to21(&self) -> TO21_R { + TO21_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Transmission Occurred 22"] + #[inline(always)] + pub fn to22(&self) -> TO22_R { + TO22_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Transmission Occurred 23"] + #[inline(always)] + pub fn to23(&self) -> TO23_R { + TO23_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24 - Transmission Occurred 24"] + #[inline(always)] + pub fn to24(&self) -> TO24_R { + TO24_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Transmission Occurred 25"] + #[inline(always)] + pub fn to25(&self) -> TO25_R { + TO25_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Transmission Occurred 26"] + #[inline(always)] + pub fn to26(&self) -> TO26_R { + TO26_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Transmission Occurred 27"] + #[inline(always)] + pub fn to27(&self) -> TO27_R { + TO27_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28 - Transmission Occurred 28"] + #[inline(always)] + pub fn to28(&self) -> TO28_R { + TO28_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Transmission Occurred 29"] + #[inline(always)] + pub fn to29(&self) -> TO29_R { + TO29_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - Transmission Occurred 30"] + #[inline(always)] + pub fn to30(&self) -> TO30_R { + TO30_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 31 - Transmission Occurred 31"] + #[inline(always)] + pub fn to31(&self) -> TO31_R { + TO31_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +#[doc = "Tx Buffer Transmission Occurred\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txbto](index.html) module"] +pub struct TXBTO_SPEC; +impl crate::RegisterSpec for TXBTO_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [txbto::R](R) reader structure"] +impl crate::Readable for TXBTO_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets TXBTO to value 0"] +impl crate::Resettable for TXBTO_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/can0/txefa.rs b/pac/atsamc21j/src/can0/txefa.rs new file mode 100644 index 000000000000..c539b8fc3dc0 --- /dev/null +++ b/pac/atsamc21j/src/can0/txefa.rs @@ -0,0 +1,103 @@ +#[doc = "Register `TXEFA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TXEFA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EFAI` reader - Event FIFO Acknowledge Index"] +pub struct EFAI_R(crate::FieldReader); +impl EFAI_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EFAI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EFAI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EFAI` writer - Event FIFO Acknowledge Index"] +pub struct EFAI_W<'a> { + w: &'a mut W, +} +impl<'a> EFAI_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Event FIFO Acknowledge Index"] + #[inline(always)] + pub fn efai(&self) -> EFAI_R { + EFAI_R::new((self.bits & 0x1f) as u8) + } +} +impl W { + #[doc = "Bits 0:4 - Event FIFO Acknowledge Index"] + #[inline(always)] + pub fn efai(&mut self) -> EFAI_W { + EFAI_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Tx Event FIFO Acknowledge\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txefa](index.html) module"] +pub struct TXEFA_SPEC; +impl crate::RegisterSpec for TXEFA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [txefa::R](R) reader structure"] +impl crate::Readable for TXEFA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [txefa::W](W) writer structure"] +impl crate::Writable for TXEFA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TXEFA to value 0"] +impl crate::Resettable for TXEFA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/can0/txefc.rs b/pac/atsamc21j/src/can0/txefc.rs new file mode 100644 index 000000000000..0c9b658d285b --- /dev/null +++ b/pac/atsamc21j/src/can0/txefc.rs @@ -0,0 +1,177 @@ +#[doc = "Register `TXEFC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TXEFC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EFSA` reader - Event FIFO Start Address"] +pub struct EFSA_R(crate::FieldReader); +impl EFSA_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + EFSA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EFSA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EFSA` writer - Event FIFO Start Address"] +pub struct EFSA_W<'a> { + w: &'a mut W, +} +impl<'a> EFSA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +#[doc = "Field `EFS` reader - Event FIFO Size"] +pub struct EFS_R(crate::FieldReader); +impl EFS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EFS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EFS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EFS` writer - Event FIFO Size"] +pub struct EFS_W<'a> { + w: &'a mut W, +} +impl<'a> EFS_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 16)) | ((value as u32 & 0x3f) << 16); + self.w + } +} +#[doc = "Field `EFWM` reader - Event FIFO Watermark"] +pub struct EFWM_R(crate::FieldReader); +impl EFWM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EFWM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EFWM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EFWM` writer - Event FIFO Watermark"] +pub struct EFWM_W<'a> { + w: &'a mut W, +} +impl<'a> EFWM_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 24)) | ((value as u32 & 0x3f) << 24); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Event FIFO Start Address"] + #[inline(always)] + pub fn efsa(&self) -> EFSA_R { + EFSA_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:21 - Event FIFO Size"] + #[inline(always)] + pub fn efs(&self) -> EFS_R { + EFS_R::new(((self.bits >> 16) & 0x3f) as u8) + } + #[doc = "Bits 24:29 - Event FIFO Watermark"] + #[inline(always)] + pub fn efwm(&self) -> EFWM_R { + EFWM_R::new(((self.bits >> 24) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:15 - Event FIFO Start Address"] + #[inline(always)] + pub fn efsa(&mut self) -> EFSA_W { + EFSA_W { w: self } + } + #[doc = "Bits 16:21 - Event FIFO Size"] + #[inline(always)] + pub fn efs(&mut self) -> EFS_W { + EFS_W { w: self } + } + #[doc = "Bits 24:29 - Event FIFO Watermark"] + #[inline(always)] + pub fn efwm(&mut self) -> EFWM_W { + EFWM_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Tx Event FIFO Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txefc](index.html) module"] +pub struct TXEFC_SPEC; +impl crate::RegisterSpec for TXEFC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [txefc::R](R) reader structure"] +impl crate::Readable for TXEFC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [txefc::W](W) writer structure"] +impl crate::Writable for TXEFC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TXEFC to value 0"] +impl crate::Resettable for TXEFC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/can0/txefs.rs b/pac/atsamc21j/src/can0/txefs.rs new file mode 100644 index 000000000000..85cac75a7ad7 --- /dev/null +++ b/pac/atsamc21j/src/can0/txefs.rs @@ -0,0 +1,133 @@ +#[doc = "Register `TXEFS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `EFFL` reader - Event FIFO Fill Level"] +pub struct EFFL_R(crate::FieldReader); +impl EFFL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EFFL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EFFL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EFGI` reader - Event FIFO Get Index"] +pub struct EFGI_R(crate::FieldReader); +impl EFGI_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EFGI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EFGI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EFPI` reader - Event FIFO Put Index"] +pub struct EFPI_R(crate::FieldReader); +impl EFPI_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EFPI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EFPI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EFF` reader - Event FIFO Full"] +pub struct EFF_R(crate::FieldReader); +impl EFF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EFF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EFF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TEFL` reader - Tx Event FIFO Element Lost"] +pub struct TEFL_R(crate::FieldReader); +impl TEFL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TEFL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TEFL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:5 - Event FIFO Fill Level"] + #[inline(always)] + pub fn effl(&self) -> EFFL_R { + EFFL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 8:12 - Event FIFO Get Index"] + #[inline(always)] + pub fn efgi(&self) -> EFGI_R { + EFGI_R::new(((self.bits >> 8) & 0x1f) as u8) + } + #[doc = "Bits 16:20 - Event FIFO Put Index"] + #[inline(always)] + pub fn efpi(&self) -> EFPI_R { + EFPI_R::new(((self.bits >> 16) & 0x1f) as u8) + } + #[doc = "Bit 24 - Event FIFO Full"] + #[inline(always)] + pub fn eff(&self) -> EFF_R { + EFF_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Tx Event FIFO Element Lost"] + #[inline(always)] + pub fn tefl(&self) -> TEFL_R { + TEFL_R::new(((self.bits >> 25) & 0x01) != 0) + } +} +#[doc = "Tx Event FIFO Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txefs](index.html) module"] +pub struct TXEFS_SPEC; +impl crate::RegisterSpec for TXEFS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [txefs::R](R) reader structure"] +impl crate::Readable for TXEFS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets TXEFS to value 0"] +impl crate::Resettable for TXEFS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/can0/txesc.rs b/pac/atsamc21j/src/can0/txesc.rs new file mode 100644 index 000000000000..7d1339f7c1cb --- /dev/null +++ b/pac/atsamc21j/src/can0/txesc.rs @@ -0,0 +1,230 @@ +#[doc = "Register `TXESC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TXESC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Tx Buffer Data Field Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum TBDS_A { + #[doc = "0: 8 byte data field"] + DATA8 = 0, + #[doc = "1: 12 byte data field"] + DATA12 = 1, + #[doc = "2: 16 byte data field"] + DATA16 = 2, + #[doc = "3: 20 byte data field"] + DATA20 = 3, + #[doc = "4: 24 byte data field"] + DATA24 = 4, + #[doc = "5: 32 byte data field"] + DATA32 = 5, + #[doc = "6: 48 byte data field"] + DATA48 = 6, + #[doc = "7: 64 byte data field"] + DATA64 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: TBDS_A) -> Self { + variant as _ + } +} +#[doc = "Field `TBDS` reader - Tx Buffer Data Field Size"] +pub struct TBDS_R(crate::FieldReader); +impl TBDS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TBDS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TBDS_A { + match self.bits { + 0 => TBDS_A::DATA8, + 1 => TBDS_A::DATA12, + 2 => TBDS_A::DATA16, + 3 => TBDS_A::DATA20, + 4 => TBDS_A::DATA24, + 5 => TBDS_A::DATA32, + 6 => TBDS_A::DATA48, + 7 => TBDS_A::DATA64, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DATA8`"] + #[inline(always)] + pub fn is_data8(&self) -> bool { + **self == TBDS_A::DATA8 + } + #[doc = "Checks if the value of the field is `DATA12`"] + #[inline(always)] + pub fn is_data12(&self) -> bool { + **self == TBDS_A::DATA12 + } + #[doc = "Checks if the value of the field is `DATA16`"] + #[inline(always)] + pub fn is_data16(&self) -> bool { + **self == TBDS_A::DATA16 + } + #[doc = "Checks if the value of the field is `DATA20`"] + #[inline(always)] + pub fn is_data20(&self) -> bool { + **self == TBDS_A::DATA20 + } + #[doc = "Checks if the value of the field is `DATA24`"] + #[inline(always)] + pub fn is_data24(&self) -> bool { + **self == TBDS_A::DATA24 + } + #[doc = "Checks if the value of the field is `DATA32`"] + #[inline(always)] + pub fn is_data32(&self) -> bool { + **self == TBDS_A::DATA32 + } + #[doc = "Checks if the value of the field is `DATA48`"] + #[inline(always)] + pub fn is_data48(&self) -> bool { + **self == TBDS_A::DATA48 + } + #[doc = "Checks if the value of the field is `DATA64`"] + #[inline(always)] + pub fn is_data64(&self) -> bool { + **self == TBDS_A::DATA64 + } +} +impl core::ops::Deref for TBDS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TBDS` writer - Tx Buffer Data Field Size"] +pub struct TBDS_W<'a> { + w: &'a mut W, +} +impl<'a> TBDS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TBDS_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "8 byte data field"] + #[inline(always)] + pub fn data8(self) -> &'a mut W { + self.variant(TBDS_A::DATA8) + } + #[doc = "12 byte data field"] + #[inline(always)] + pub fn data12(self) -> &'a mut W { + self.variant(TBDS_A::DATA12) + } + #[doc = "16 byte data field"] + #[inline(always)] + pub fn data16(self) -> &'a mut W { + self.variant(TBDS_A::DATA16) + } + #[doc = "20 byte data field"] + #[inline(always)] + pub fn data20(self) -> &'a mut W { + self.variant(TBDS_A::DATA20) + } + #[doc = "24 byte data field"] + #[inline(always)] + pub fn data24(self) -> &'a mut W { + self.variant(TBDS_A::DATA24) + } + #[doc = "32 byte data field"] + #[inline(always)] + pub fn data32(self) -> &'a mut W { + self.variant(TBDS_A::DATA32) + } + #[doc = "48 byte data field"] + #[inline(always)] + pub fn data48(self) -> &'a mut W { + self.variant(TBDS_A::DATA48) + } + #[doc = "64 byte data field"] + #[inline(always)] + pub fn data64(self) -> &'a mut W { + self.variant(TBDS_A::DATA64) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Tx Buffer Data Field Size"] + #[inline(always)] + pub fn tbds(&self) -> TBDS_R { + TBDS_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Tx Buffer Data Field Size"] + #[inline(always)] + pub fn tbds(&mut self) -> TBDS_W { + TBDS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Tx Buffer Element Size Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txesc](index.html) module"] +pub struct TXESC_SPEC; +impl crate::RegisterSpec for TXESC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [txesc::R](R) reader structure"] +impl crate::Readable for TXESC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [txesc::W](W) writer structure"] +impl crate::Writable for TXESC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TXESC to value 0"] +impl crate::Resettable for TXESC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/can0/txfqs.rs b/pac/atsamc21j/src/can0/txfqs.rs new file mode 100644 index 000000000000..19ef5f5d3fe6 --- /dev/null +++ b/pac/atsamc21j/src/can0/txfqs.rs @@ -0,0 +1,113 @@ +#[doc = "Register `TXFQS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `TFFL` reader - Tx FIFO Free Level"] +pub struct TFFL_R(crate::FieldReader); +impl TFFL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TFFL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TFFL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TFGI` reader - Tx FIFO Get Index"] +pub struct TFGI_R(crate::FieldReader); +impl TFGI_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TFGI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TFGI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TFQPI` reader - Tx FIFO/Queue Put Index"] +pub struct TFQPI_R(crate::FieldReader); +impl TFQPI_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TFQPI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TFQPI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TFQF` reader - Tx FIFO/Queue Full"] +pub struct TFQF_R(crate::FieldReader); +impl TFQF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TFQF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TFQF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:5 - Tx FIFO Free Level"] + #[inline(always)] + pub fn tffl(&self) -> TFFL_R { + TFFL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 8:12 - Tx FIFO Get Index"] + #[inline(always)] + pub fn tfgi(&self) -> TFGI_R { + TFGI_R::new(((self.bits >> 8) & 0x1f) as u8) + } + #[doc = "Bits 16:20 - Tx FIFO/Queue Put Index"] + #[inline(always)] + pub fn tfqpi(&self) -> TFQPI_R { + TFQPI_R::new(((self.bits >> 16) & 0x1f) as u8) + } + #[doc = "Bit 21 - Tx FIFO/Queue Full"] + #[inline(always)] + pub fn tfqf(&self) -> TFQF_R { + TFQF_R::new(((self.bits >> 21) & 0x01) != 0) + } +} +#[doc = "Tx FIFO / Queue Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txfqs](index.html) module"] +pub struct TXFQS_SPEC; +impl crate::RegisterSpec for TXFQS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [txfqs::R](R) reader structure"] +impl crate::Readable for TXFQS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets TXFQS to value 0"] +impl crate::Resettable for TXFQS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/can0/xidam.rs b/pac/atsamc21j/src/can0/xidam.rs new file mode 100644 index 000000000000..8d78879a63be --- /dev/null +++ b/pac/atsamc21j/src/can0/xidam.rs @@ -0,0 +1,103 @@ +#[doc = "Register `XIDAM` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `XIDAM` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EIDM` reader - Extended ID Mask"] +pub struct EIDM_R(crate::FieldReader); +impl EIDM_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + EIDM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EIDM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EIDM` writer - Extended ID Mask"] +pub struct EIDM_W<'a> { + w: &'a mut W, +} +impl<'a> EIDM_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1fff_ffff) | (value as u32 & 0x1fff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:28 - Extended ID Mask"] + #[inline(always)] + pub fn eidm(&self) -> EIDM_R { + EIDM_R::new((self.bits & 0x1fff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:28 - Extended ID Mask"] + #[inline(always)] + pub fn eidm(&mut self) -> EIDM_W { + EIDM_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Extended ID AND Mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [xidam](index.html) module"] +pub struct XIDAM_SPEC; +impl crate::RegisterSpec for XIDAM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [xidam::R](R) reader structure"] +impl crate::Readable for XIDAM_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [xidam::W](W) writer structure"] +impl crate::Writable for XIDAM_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets XIDAM to value 0x1fff_ffff"] +impl crate::Resettable for XIDAM_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x1fff_ffff + } +} diff --git a/pac/atsamc21j/src/can0/xidfc.rs b/pac/atsamc21j/src/can0/xidfc.rs new file mode 100644 index 000000000000..57b31389a71f --- /dev/null +++ b/pac/atsamc21j/src/can0/xidfc.rs @@ -0,0 +1,140 @@ +#[doc = "Register `XIDFC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `XIDFC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FLESA` reader - Filter List Extended Start Address"] +pub struct FLESA_R(crate::FieldReader); +impl FLESA_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + FLESA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FLESA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLESA` writer - Filter List Extended Start Address"] +pub struct FLESA_W<'a> { + w: &'a mut W, +} +impl<'a> FLESA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +#[doc = "Field `LSE` reader - List Size Extended"] +pub struct LSE_R(crate::FieldReader); +impl LSE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LSE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LSE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LSE` writer - List Size Extended"] +pub struct LSE_W<'a> { + w: &'a mut W, +} +impl<'a> LSE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x7f << 16)) | ((value as u32 & 0x7f) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Filter List Extended Start Address"] + #[inline(always)] + pub fn flesa(&self) -> FLESA_R { + FLESA_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:22 - List Size Extended"] + #[inline(always)] + pub fn lse(&self) -> LSE_R { + LSE_R::new(((self.bits >> 16) & 0x7f) as u8) + } +} +impl W { + #[doc = "Bits 0:15 - Filter List Extended Start Address"] + #[inline(always)] + pub fn flesa(&mut self) -> FLESA_W { + FLESA_W { w: self } + } + #[doc = "Bits 16:22 - List Size Extended"] + #[inline(always)] + pub fn lse(&mut self) -> LSE_W { + LSE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Extended ID Filter Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [xidfc](index.html) module"] +pub struct XIDFC_SPEC; +impl crate::RegisterSpec for XIDFC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [xidfc::R](R) reader structure"] +impl crate::Readable for XIDFC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [xidfc::W](W) writer structure"] +impl crate::Writable for XIDFC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets XIDFC to value 0"] +impl crate::Resettable for XIDFC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/ccl.rs b/pac/atsamc21j/src/ccl.rs new file mode 100644 index 000000000000..30b1f41639c1 --- /dev/null +++ b/pac/atsamc21j/src/ccl.rs @@ -0,0 +1,24 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrl: crate::Reg, + _reserved1: [u8; 0x03], + #[doc = "0x04 - SEQ Control x"] + pub seqctrl: [crate::Reg; 2], + _reserved2: [u8; 0x02], + #[doc = "0x08..0x18 - LUT Control x"] + pub lutctrl: [crate::Reg; 4], +} +#[doc = "CTRL register accessor: an alias for `Reg`"] +pub type CTRL = crate::Reg; +#[doc = "Control"] +pub mod ctrl; +#[doc = "SEQCTRL register accessor: an alias for `Reg`"] +pub type SEQCTRL = crate::Reg; +#[doc = "SEQ Control x"] +pub mod seqctrl; +#[doc = "LUTCTRL register accessor: an alias for `Reg`"] +pub type LUTCTRL = crate::Reg; +#[doc = "LUT Control x"] +pub mod lutctrl; diff --git a/pac/atsamc21j/src/ccl/ctrl.rs b/pac/atsamc21j/src/ccl/ctrl.rs new file mode 100644 index 000000000000..5e515fe037ca --- /dev/null +++ b/pac/atsamc21j/src/ccl/ctrl.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"] +pub struct CTRL_SPEC; +impl crate::RegisterSpec for CTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrl::R](R) reader structure"] +impl crate::Readable for CTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"] +impl crate::Writable for CTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/ccl/lutctrl.rs b/pac/atsamc21j/src/ccl/lutctrl.rs new file mode 100644 index 000000000000..530ed34f7c81 --- /dev/null +++ b/pac/atsamc21j/src/ccl/lutctrl.rs @@ -0,0 +1,702 @@ +#[doc = "Register `LUTCTRL[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `LUTCTRL[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - LUT Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - LUT Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Filter Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FILTSEL_A { + #[doc = "0: Filter disabled"] + DISABLE = 0, + #[doc = "1: Synchronizer enabled"] + SYNCH = 1, + #[doc = "2: Filter enabled"] + FILTER = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FILTSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `FILTSEL` reader - Filter Selection"] +pub struct FILTSEL_R(crate::FieldReader); +impl FILTSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FILTSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(FILTSEL_A::DISABLE), + 1 => Some(FILTSEL_A::SYNCH), + 2 => Some(FILTSEL_A::FILTER), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == FILTSEL_A::DISABLE + } + #[doc = "Checks if the value of the field is `SYNCH`"] + #[inline(always)] + pub fn is_synch(&self) -> bool { + **self == FILTSEL_A::SYNCH + } + #[doc = "Checks if the value of the field is `FILTER`"] + #[inline(always)] + pub fn is_filter(&self) -> bool { + **self == FILTSEL_A::FILTER + } +} +impl core::ops::Deref for FILTSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTSEL` writer - Filter Selection"] +pub struct FILTSEL_W<'a> { + w: &'a mut W, +} +impl<'a> FILTSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FILTSEL_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Filter disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(FILTSEL_A::DISABLE) + } + #[doc = "Synchronizer enabled"] + #[inline(always)] + pub fn synch(self) -> &'a mut W { + self.variant(FILTSEL_A::SYNCH) + } + #[doc = "Filter enabled"] + #[inline(always)] + pub fn filter(self) -> &'a mut W { + self.variant(FILTSEL_A::FILTER) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u32 & 0x03) << 4); + self.w + } +} +#[doc = "Field `EDGESEL` reader - Edge Selection"] +pub struct EDGESEL_R(crate::FieldReader); +impl EDGESEL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EDGESEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EDGESEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EDGESEL` writer - Edge Selection"] +pub struct EDGESEL_W<'a> { + w: &'a mut W, +} +impl<'a> EDGESEL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Input Selection 0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum INSEL0_A { + #[doc = "0: Masked input"] + MASK = 0, + #[doc = "1: Feedback input source"] + FEEDBACK = 1, + #[doc = "2: Linked LUT input source"] + LINK = 2, + #[doc = "3: Event in put source"] + EVENT = 3, + #[doc = "4: I/O pin input source"] + IO = 4, + #[doc = "5: AC input source"] + AC = 5, + #[doc = "6: TC input source"] + TC = 6, + #[doc = "7: Alternate TC input source"] + ALTTC = 7, + #[doc = "8: TCC input source"] + TCC = 8, + #[doc = "9: SERCOM inout source"] + SERCOM = 9, +} +impl From for u8 { + #[inline(always)] + fn from(variant: INSEL0_A) -> Self { + variant as _ + } +} +#[doc = "Field `INSEL0` reader - Input Selection 0"] +pub struct INSEL0_R(crate::FieldReader); +impl INSEL0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + INSEL0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(INSEL0_A::MASK), + 1 => Some(INSEL0_A::FEEDBACK), + 2 => Some(INSEL0_A::LINK), + 3 => Some(INSEL0_A::EVENT), + 4 => Some(INSEL0_A::IO), + 5 => Some(INSEL0_A::AC), + 6 => Some(INSEL0_A::TC), + 7 => Some(INSEL0_A::ALTTC), + 8 => Some(INSEL0_A::TCC), + 9 => Some(INSEL0_A::SERCOM), + _ => None, + } + } + #[doc = "Checks if the value of the field is `MASK`"] + #[inline(always)] + pub fn is_mask(&self) -> bool { + **self == INSEL0_A::MASK + } + #[doc = "Checks if the value of the field is `FEEDBACK`"] + #[inline(always)] + pub fn is_feedback(&self) -> bool { + **self == INSEL0_A::FEEDBACK + } + #[doc = "Checks if the value of the field is `LINK`"] + #[inline(always)] + pub fn is_link(&self) -> bool { + **self == INSEL0_A::LINK + } + #[doc = "Checks if the value of the field is `EVENT`"] + #[inline(always)] + pub fn is_event(&self) -> bool { + **self == INSEL0_A::EVENT + } + #[doc = "Checks if the value of the field is `IO`"] + #[inline(always)] + pub fn is_io(&self) -> bool { + **self == INSEL0_A::IO + } + #[doc = "Checks if the value of the field is `AC`"] + #[inline(always)] + pub fn is_ac(&self) -> bool { + **self == INSEL0_A::AC + } + #[doc = "Checks if the value of the field is `TC`"] + #[inline(always)] + pub fn is_tc(&self) -> bool { + **self == INSEL0_A::TC + } + #[doc = "Checks if the value of the field is `ALTTC`"] + #[inline(always)] + pub fn is_alttc(&self) -> bool { + **self == INSEL0_A::ALTTC + } + #[doc = "Checks if the value of the field is `TCC`"] + #[inline(always)] + pub fn is_tcc(&self) -> bool { + **self == INSEL0_A::TCC + } + #[doc = "Checks if the value of the field is `SERCOM`"] + #[inline(always)] + pub fn is_sercom(&self) -> bool { + **self == INSEL0_A::SERCOM + } +} +impl core::ops::Deref for INSEL0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INSEL0` writer - Input Selection 0"] +pub struct INSEL0_W<'a> { + w: &'a mut W, +} +impl<'a> INSEL0_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: INSEL0_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Masked input"] + #[inline(always)] + pub fn mask(self) -> &'a mut W { + self.variant(INSEL0_A::MASK) + } + #[doc = "Feedback input source"] + #[inline(always)] + pub fn feedback(self) -> &'a mut W { + self.variant(INSEL0_A::FEEDBACK) + } + #[doc = "Linked LUT input source"] + #[inline(always)] + pub fn link(self) -> &'a mut W { + self.variant(INSEL0_A::LINK) + } + #[doc = "Event in put source"] + #[inline(always)] + pub fn event(self) -> &'a mut W { + self.variant(INSEL0_A::EVENT) + } + #[doc = "I/O pin input source"] + #[inline(always)] + pub fn io(self) -> &'a mut W { + self.variant(INSEL0_A::IO) + } + #[doc = "AC input source"] + #[inline(always)] + pub fn ac(self) -> &'a mut W { + self.variant(INSEL0_A::AC) + } + #[doc = "TC input source"] + #[inline(always)] + pub fn tc(self) -> &'a mut W { + self.variant(INSEL0_A::TC) + } + #[doc = "Alternate TC input source"] + #[inline(always)] + pub fn alttc(self) -> &'a mut W { + self.variant(INSEL0_A::ALTTC) + } + #[doc = "TCC input source"] + #[inline(always)] + pub fn tcc(self) -> &'a mut W { + self.variant(INSEL0_A::TCC) + } + #[doc = "SERCOM inout source"] + #[inline(always)] + pub fn sercom(self) -> &'a mut W { + self.variant(INSEL0_A::SERCOM) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 8)) | ((value as u32 & 0x0f) << 8); + self.w + } +} +#[doc = "Field `INSEL1` reader - Input Selection 1"] +pub struct INSEL1_R(crate::FieldReader); +impl INSEL1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + INSEL1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INSEL1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INSEL1` writer - Input Selection 1"] +pub struct INSEL1_W<'a> { + w: &'a mut W, +} +impl<'a> INSEL1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 12)) | ((value as u32 & 0x0f) << 12); + self.w + } +} +#[doc = "Field `INSEL2` reader - Input Selection 2"] +pub struct INSEL2_R(crate::FieldReader); +impl INSEL2_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + INSEL2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INSEL2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INSEL2` writer - Input Selection 2"] +pub struct INSEL2_W<'a> { + w: &'a mut W, +} +impl<'a> INSEL2_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 16)) | ((value as u32 & 0x0f) << 16); + self.w + } +} +#[doc = "Field `INVEI` reader - Input Event Invert"] +pub struct INVEI_R(crate::FieldReader); +impl INVEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEI` writer - Input Event Invert"] +pub struct INVEI_W<'a> { + w: &'a mut W, +} +impl<'a> INVEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `LUTEI` reader - Event Input Enable"] +pub struct LUTEI_R(crate::FieldReader); +impl LUTEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LUTEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LUTEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LUTEI` writer - Event Input Enable"] +pub struct LUTEI_W<'a> { + w: &'a mut W, +} +impl<'a> LUTEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `LUTEO` reader - Event Output Enable"] +pub struct LUTEO_R(crate::FieldReader); +impl LUTEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LUTEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LUTEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LUTEO` writer - Event Output Enable"] +pub struct LUTEO_W<'a> { + w: &'a mut W, +} +impl<'a> LUTEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `TRUTH` reader - Truth Value"] +pub struct TRUTH_R(crate::FieldReader); +impl TRUTH_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TRUTH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRUTH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRUTH` writer - Truth Value"] +pub struct TRUTH_W<'a> { + w: &'a mut W, +} +impl<'a> TRUTH_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 24)) | ((value as u32 & 0xff) << 24); + self.w + } +} +impl R { + #[doc = "Bit 1 - LUT Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 4:5 - Filter Selection"] + #[inline(always)] + pub fn filtsel(&self) -> FILTSEL_R { + FILTSEL_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bit 7 - Edge Selection"] + #[inline(always)] + pub fn edgesel(&self) -> EDGESEL_R { + EDGESEL_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:11 - Input Selection 0"] + #[inline(always)] + pub fn insel0(&self) -> INSEL0_R { + INSEL0_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - Input Selection 1"] + #[inline(always)] + pub fn insel1(&self) -> INSEL1_R { + INSEL1_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:19 - Input Selection 2"] + #[inline(always)] + pub fn insel2(&self) -> INSEL2_R { + INSEL2_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Input Event Invert"] + #[inline(always)] + pub fn invei(&self) -> INVEI_R { + INVEI_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Event Input Enable"] + #[inline(always)] + pub fn lutei(&self) -> LUTEI_R { + LUTEI_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Event Output Enable"] + #[inline(always)] + pub fn luteo(&self) -> LUTEO_R { + LUTEO_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bits 24:31 - Truth Value"] + #[inline(always)] + pub fn truth(&self) -> TRUTH_R { + TRUTH_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bit 1 - LUT Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 4:5 - Filter Selection"] + #[inline(always)] + pub fn filtsel(&mut self) -> FILTSEL_W { + FILTSEL_W { w: self } + } + #[doc = "Bit 7 - Edge Selection"] + #[inline(always)] + pub fn edgesel(&mut self) -> EDGESEL_W { + EDGESEL_W { w: self } + } + #[doc = "Bits 8:11 - Input Selection 0"] + #[inline(always)] + pub fn insel0(&mut self) -> INSEL0_W { + INSEL0_W { w: self } + } + #[doc = "Bits 12:15 - Input Selection 1"] + #[inline(always)] + pub fn insel1(&mut self) -> INSEL1_W { + INSEL1_W { w: self } + } + #[doc = "Bits 16:19 - Input Selection 2"] + #[inline(always)] + pub fn insel2(&mut self) -> INSEL2_W { + INSEL2_W { w: self } + } + #[doc = "Bit 20 - Input Event Invert"] + #[inline(always)] + pub fn invei(&mut self) -> INVEI_W { + INVEI_W { w: self } + } + #[doc = "Bit 21 - Event Input Enable"] + #[inline(always)] + pub fn lutei(&mut self) -> LUTEI_W { + LUTEI_W { w: self } + } + #[doc = "Bit 22 - Event Output Enable"] + #[inline(always)] + pub fn luteo(&mut self) -> LUTEO_W { + LUTEO_W { w: self } + } + #[doc = "Bits 24:31 - Truth Value"] + #[inline(always)] + pub fn truth(&mut self) -> TRUTH_W { + TRUTH_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "LUT Control x\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lutctrl](index.html) module"] +pub struct LUTCTRL_SPEC; +impl crate::RegisterSpec for LUTCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [lutctrl::R](R) reader structure"] +impl crate::Readable for LUTCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [lutctrl::W](W) writer structure"] +impl crate::Writable for LUTCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets LUTCTRL[%s] +to value 0"] +impl crate::Resettable for LUTCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/ccl/seqctrl.rs b/pac/atsamc21j/src/ccl/seqctrl.rs new file mode 100644 index 000000000000..e2597a1042f3 --- /dev/null +++ b/pac/atsamc21j/src/ccl/seqctrl.rs @@ -0,0 +1,192 @@ +#[doc = "Register `SEQCTRL[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SEQCTRL[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Sequential Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SEQSEL_A { + #[doc = "0: Sequential logic is disabled"] + DISABLE = 0, + #[doc = "1: D flip flop"] + DFF = 1, + #[doc = "2: JK flip flop"] + JK = 2, + #[doc = "3: D latch"] + LATCH = 3, + #[doc = "4: RS latch"] + RS = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEQSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `SEQSEL` reader - Sequential Selection"] +pub struct SEQSEL_R(crate::FieldReader); +impl SEQSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SEQSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEQSEL_A::DISABLE), + 1 => Some(SEQSEL_A::DFF), + 2 => Some(SEQSEL_A::JK), + 3 => Some(SEQSEL_A::LATCH), + 4 => Some(SEQSEL_A::RS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == SEQSEL_A::DISABLE + } + #[doc = "Checks if the value of the field is `DFF`"] + #[inline(always)] + pub fn is_dff(&self) -> bool { + **self == SEQSEL_A::DFF + } + #[doc = "Checks if the value of the field is `JK`"] + #[inline(always)] + pub fn is_jk(&self) -> bool { + **self == SEQSEL_A::JK + } + #[doc = "Checks if the value of the field is `LATCH`"] + #[inline(always)] + pub fn is_latch(&self) -> bool { + **self == SEQSEL_A::LATCH + } + #[doc = "Checks if the value of the field is `RS`"] + #[inline(always)] + pub fn is_rs(&self) -> bool { + **self == SEQSEL_A::RS + } +} +impl core::ops::Deref for SEQSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEQSEL` writer - Sequential Selection"] +pub struct SEQSEL_W<'a> { + w: &'a mut W, +} +impl<'a> SEQSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SEQSEL_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Sequential logic is disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(SEQSEL_A::DISABLE) + } + #[doc = "D flip flop"] + #[inline(always)] + pub fn dff(self) -> &'a mut W { + self.variant(SEQSEL_A::DFF) + } + #[doc = "JK flip flop"] + #[inline(always)] + pub fn jk(self) -> &'a mut W { + self.variant(SEQSEL_A::JK) + } + #[doc = "D latch"] + #[inline(always)] + pub fn latch(self) -> &'a mut W { + self.variant(SEQSEL_A::LATCH) + } + #[doc = "RS latch"] + #[inline(always)] + pub fn rs(self) -> &'a mut W { + self.variant(SEQSEL_A::RS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Sequential Selection"] + #[inline(always)] + pub fn seqsel(&self) -> SEQSEL_R { + SEQSEL_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Sequential Selection"] + #[inline(always)] + pub fn seqsel(&mut self) -> SEQSEL_W { + SEQSEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SEQ Control x\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [seqctrl](index.html) module"] +pub struct SEQCTRL_SPEC; +impl crate::RegisterSpec for SEQCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [seqctrl::R](R) reader structure"] +impl crate::Readable for SEQCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [seqctrl::W](W) writer structure"] +impl crate::Writable for SEQCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SEQCTRL[%s] +to value 0"] +impl crate::Resettable for SEQCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/dac.rs b/pac/atsamc21j/src/dac.rs new file mode 100644 index 000000000000..255af9263600 --- /dev/null +++ b/pac/atsamc21j/src/dac.rs @@ -0,0 +1,73 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + #[doc = "0x01 - Control B"] + pub ctrlb: crate::Reg, + #[doc = "0x02 - Event Control"] + pub evctrl: crate::Reg, + _reserved3: [u8; 0x01], + #[doc = "0x04 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x05 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x06 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x07 - Status"] + pub status: crate::Reg, + #[doc = "0x08 - Data"] + pub data: crate::Reg, + _reserved8: [u8; 0x02], + #[doc = "0x0c - Data Buffer"] + pub databuf: crate::Reg, + _reserved9: [u8; 0x02], + #[doc = "0x10 - Synchronization Busy"] + pub syncbusy: crate::Reg, + #[doc = "0x14 - Debug Control"] + pub dbgctrl: crate::Reg, +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "Control B"] +pub mod ctrlb; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "Data"] +pub mod data; +#[doc = "DATABUF register accessor: an alias for `Reg`"] +pub type DATABUF = crate::Reg; +#[doc = "Data Buffer"] +pub mod databuf; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Busy"] +pub mod syncbusy; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; diff --git a/pac/atsamc21j/src/dac/ctrla.rs b/pac/atsamc21j/src/dac/ctrla.rs new file mode 100644 index 000000000000..3ff2fbd9c4d5 --- /dev/null +++ b/pac/atsamc21j/src/dac/ctrla.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/dac/ctrlb.rs b/pac/atsamc21j/src/dac/ctrlb.rs new file mode 100644 index 000000000000..ac7d537964e1 --- /dev/null +++ b/pac/atsamc21j/src/dac/ctrlb.rs @@ -0,0 +1,400 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EOEN` reader - External Output Enable"] +pub struct EOEN_R(crate::FieldReader); +impl EOEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EOEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EOEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EOEN` writer - External Output Enable"] +pub struct EOEN_W<'a> { + w: &'a mut W, +} +impl<'a> EOEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `IOEN` reader - Internal Output Enable"] +pub struct IOEN_R(crate::FieldReader); +impl IOEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IOEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IOEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IOEN` writer - Internal Output Enable"] +pub struct IOEN_W<'a> { + w: &'a mut W, +} +impl<'a> IOEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `LEFTADJ` reader - Left Adjusted Data"] +pub struct LEFTADJ_R(crate::FieldReader); +impl LEFTADJ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LEFTADJ_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LEFTADJ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LEFTADJ` writer - Left Adjusted Data"] +pub struct LEFTADJ_W<'a> { + w: &'a mut W, +} +impl<'a> LEFTADJ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `VPD` reader - Voltage Pump Disable"] +pub struct VPD_R(crate::FieldReader); +impl VPD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + VPD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VPD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VPD` writer - Voltage Pump Disable"] +pub struct VPD_W<'a> { + w: &'a mut W, +} +impl<'a> VPD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `DITHER` reader - Dither Enable"] +pub struct DITHER_R(crate::FieldReader); +impl DITHER_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DITHER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHER` writer - Dither Enable"] +pub struct DITHER_W<'a> { + w: &'a mut W, +} +impl<'a> DITHER_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Reference Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum REFSEL_A { + #[doc = "0: Internal 1.0V reference"] + INT1V = 0, + #[doc = "1: AVCC"] + AVCC = 1, + #[doc = "2: External reference"] + VREFP = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: REFSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `REFSEL` reader - Reference Selection"] +pub struct REFSEL_R(crate::FieldReader); +impl REFSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REFSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(REFSEL_A::INT1V), + 1 => Some(REFSEL_A::AVCC), + 2 => Some(REFSEL_A::VREFP), + _ => None, + } + } + #[doc = "Checks if the value of the field is `INT1V`"] + #[inline(always)] + pub fn is_int1v(&self) -> bool { + **self == REFSEL_A::INT1V + } + #[doc = "Checks if the value of the field is `AVCC`"] + #[inline(always)] + pub fn is_avcc(&self) -> bool { + **self == REFSEL_A::AVCC + } + #[doc = "Checks if the value of the field is `VREFP`"] + #[inline(always)] + pub fn is_vrefp(&self) -> bool { + **self == REFSEL_A::VREFP + } +} +impl core::ops::Deref for REFSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REFSEL` writer - Reference Selection"] +pub struct REFSEL_W<'a> { + w: &'a mut W, +} +impl<'a> REFSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: REFSEL_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Internal 1.0V reference"] + #[inline(always)] + pub fn int1v(self) -> &'a mut W { + self.variant(REFSEL_A::INT1V) + } + #[doc = "AVCC"] + #[inline(always)] + pub fn avcc(self) -> &'a mut W { + self.variant(REFSEL_A::AVCC) + } + #[doc = "External reference"] + #[inline(always)] + pub fn vrefp(self) -> &'a mut W { + self.variant(REFSEL_A::VREFP) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 6)) | ((value as u8 & 0x03) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - External Output Enable"] + #[inline(always)] + pub fn eoen(&self) -> EOEN_R { + EOEN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Internal Output Enable"] + #[inline(always)] + pub fn ioen(&self) -> IOEN_R { + IOEN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Left Adjusted Data"] + #[inline(always)] + pub fn leftadj(&self) -> LEFTADJ_R { + LEFTADJ_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Voltage Pump Disable"] + #[inline(always)] + pub fn vpd(&self) -> VPD_R { + VPD_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 5 - Dither Enable"] + #[inline(always)] + pub fn dither(&self) -> DITHER_R { + DITHER_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bits 6:7 - Reference Selection"] + #[inline(always)] + pub fn refsel(&self) -> REFSEL_R { + REFSEL_R::new(((self.bits >> 6) & 0x03) as u8) + } +} +impl W { + #[doc = "Bit 0 - External Output Enable"] + #[inline(always)] + pub fn eoen(&mut self) -> EOEN_W { + EOEN_W { w: self } + } + #[doc = "Bit 1 - Internal Output Enable"] + #[inline(always)] + pub fn ioen(&mut self) -> IOEN_W { + IOEN_W { w: self } + } + #[doc = "Bit 2 - Left Adjusted Data"] + #[inline(always)] + pub fn leftadj(&mut self) -> LEFTADJ_W { + LEFTADJ_W { w: self } + } + #[doc = "Bit 3 - Voltage Pump Disable"] + #[inline(always)] + pub fn vpd(&mut self) -> VPD_W { + VPD_W { w: self } + } + #[doc = "Bit 5 - Dither Enable"] + #[inline(always)] + pub fn dither(&mut self) -> DITHER_W { + DITHER_W { w: self } + } + #[doc = "Bits 6:7 - Reference Selection"] + #[inline(always)] + pub fn refsel(&mut self) -> REFSEL_W { + REFSEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/dac/data.rs b/pac/atsamc21j/src/dac/data.rs new file mode 100644 index 000000000000..d70d1a60e76f --- /dev/null +++ b/pac/atsamc21j/src/dac/data.rs @@ -0,0 +1,62 @@ +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` writer - Data value to be converted"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl W { + #[doc = "Bits 0:15 - Data value to be converted"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u16; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/dac/databuf.rs b/pac/atsamc21j/src/dac/databuf.rs new file mode 100644 index 000000000000..fc2aa61686cd --- /dev/null +++ b/pac/atsamc21j/src/dac/databuf.rs @@ -0,0 +1,62 @@ +#[doc = "Register `DATABUF` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATABUF` writer - Data Buffer"] +pub struct DATABUF_W<'a> { + w: &'a mut W, +} +impl<'a> DATABUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl W { + #[doc = "Bits 0:15 - Data Buffer"] + #[inline(always)] + pub fn databuf(&mut self) -> DATABUF_W { + DATABUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Buffer\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [databuf](index.html) module"] +pub struct DATABUF_SPEC; +impl crate::RegisterSpec for DATABUF_SPEC { + type Ux = u16; +} +#[doc = "`write(|w| ..)` method takes [databuf::W](W) writer structure"] +impl crate::Writable for DATABUF_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATABUF to value 0"] +impl crate::Resettable for DATABUF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/dac/dbgctrl.rs b/pac/atsamc21j/src/dac/dbgctrl.rs new file mode 100644 index 000000000000..53636eb2b339 --- /dev/null +++ b/pac/atsamc21j/src/dac/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Debug Run"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Debug Run"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/dac/evctrl.rs b/pac/atsamc21j/src/dac/evctrl.rs new file mode 100644 index 000000000000..1032a853887d --- /dev/null +++ b/pac/atsamc21j/src/dac/evctrl.rs @@ -0,0 +1,207 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `STARTEI` reader - Start Conversion Event Input"] +pub struct STARTEI_R(crate::FieldReader); +impl STARTEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STARTEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STARTEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STARTEI` writer - Start Conversion Event Input"] +pub struct STARTEI_W<'a> { + w: &'a mut W, +} +impl<'a> STARTEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `EMPTYEO` reader - Data Buffer Empty Event Output"] +pub struct EMPTYEO_R(crate::FieldReader); +impl EMPTYEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EMPTYEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EMPTYEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EMPTYEO` writer - Data Buffer Empty Event Output"] +pub struct EMPTYEO_W<'a> { + w: &'a mut W, +} +impl<'a> EMPTYEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `INVEI` reader - Invert Event Input"] +pub struct INVEI_R(crate::FieldReader); +impl INVEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEI` writer - Invert Event Input"] +pub struct INVEI_W<'a> { + w: &'a mut W, +} +impl<'a> INVEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Start Conversion Event Input"] + #[inline(always)] + pub fn startei(&self) -> STARTEI_R { + STARTEI_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Data Buffer Empty Event Output"] + #[inline(always)] + pub fn emptyeo(&self) -> EMPTYEO_R { + EMPTYEO_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Invert Event Input"] + #[inline(always)] + pub fn invei(&self) -> INVEI_R { + INVEI_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Start Conversion Event Input"] + #[inline(always)] + pub fn startei(&mut self) -> STARTEI_W { + STARTEI_W { w: self } + } + #[doc = "Bit 1 - Data Buffer Empty Event Output"] + #[inline(always)] + pub fn emptyeo(&mut self) -> EMPTYEO_W { + EMPTYEO_W { w: self } + } + #[doc = "Bit 2 - Invert Event Input"] + #[inline(always)] + pub fn invei(&mut self) -> INVEI_W { + INVEI_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/dac/intenclr.rs b/pac/atsamc21j/src/dac/intenclr.rs new file mode 100644 index 000000000000..408feebf63ca --- /dev/null +++ b/pac/atsamc21j/src/dac/intenclr.rs @@ -0,0 +1,160 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `UNDERRUN` reader - Underrun Interrupt Enable"] +pub struct UNDERRUN_R(crate::FieldReader); +impl UNDERRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UNDERRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for UNDERRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `UNDERRUN` writer - Underrun Interrupt Enable"] +pub struct UNDERRUN_W<'a> { + w: &'a mut W, +} +impl<'a> UNDERRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `EMPTY` reader - Data Buffer Empty Interrupt Enable"] +pub struct EMPTY_R(crate::FieldReader); +impl EMPTY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EMPTY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EMPTY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EMPTY` writer - Data Buffer Empty Interrupt Enable"] +pub struct EMPTY_W<'a> { + w: &'a mut W, +} +impl<'a> EMPTY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - Underrun Interrupt Enable"] + #[inline(always)] + pub fn underrun(&self) -> UNDERRUN_R { + UNDERRUN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Data Buffer Empty Interrupt Enable"] + #[inline(always)] + pub fn empty(&self) -> EMPTY_R { + EMPTY_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Underrun Interrupt Enable"] + #[inline(always)] + pub fn underrun(&mut self) -> UNDERRUN_W { + UNDERRUN_W { w: self } + } + #[doc = "Bit 1 - Data Buffer Empty Interrupt Enable"] + #[inline(always)] + pub fn empty(&mut self) -> EMPTY_W { + EMPTY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/dac/intenset.rs b/pac/atsamc21j/src/dac/intenset.rs new file mode 100644 index 000000000000..db38e69ed2e5 --- /dev/null +++ b/pac/atsamc21j/src/dac/intenset.rs @@ -0,0 +1,160 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `UNDERRUN` reader - Underrun Interrupt Enable"] +pub struct UNDERRUN_R(crate::FieldReader); +impl UNDERRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UNDERRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for UNDERRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `UNDERRUN` writer - Underrun Interrupt Enable"] +pub struct UNDERRUN_W<'a> { + w: &'a mut W, +} +impl<'a> UNDERRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `EMPTY` reader - Data Buffer Empty Interrupt Enable"] +pub struct EMPTY_R(crate::FieldReader); +impl EMPTY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EMPTY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EMPTY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EMPTY` writer - Data Buffer Empty Interrupt Enable"] +pub struct EMPTY_W<'a> { + w: &'a mut W, +} +impl<'a> EMPTY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - Underrun Interrupt Enable"] + #[inline(always)] + pub fn underrun(&self) -> UNDERRUN_R { + UNDERRUN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Data Buffer Empty Interrupt Enable"] + #[inline(always)] + pub fn empty(&self) -> EMPTY_R { + EMPTY_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Underrun Interrupt Enable"] + #[inline(always)] + pub fn underrun(&mut self) -> UNDERRUN_W { + UNDERRUN_W { w: self } + } + #[doc = "Bit 1 - Data Buffer Empty Interrupt Enable"] + #[inline(always)] + pub fn empty(&mut self) -> EMPTY_W { + EMPTY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/dac/intflag.rs b/pac/atsamc21j/src/dac/intflag.rs new file mode 100644 index 000000000000..6779ed161d08 --- /dev/null +++ b/pac/atsamc21j/src/dac/intflag.rs @@ -0,0 +1,160 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `UNDERRUN` reader - Underrun"] +pub struct UNDERRUN_R(crate::FieldReader); +impl UNDERRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UNDERRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for UNDERRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `UNDERRUN` writer - Underrun"] +pub struct UNDERRUN_W<'a> { + w: &'a mut W, +} +impl<'a> UNDERRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `EMPTY` reader - Data Buffer Empty"] +pub struct EMPTY_R(crate::FieldReader); +impl EMPTY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EMPTY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EMPTY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EMPTY` writer - Data Buffer Empty"] +pub struct EMPTY_W<'a> { + w: &'a mut W, +} +impl<'a> EMPTY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - Underrun"] + #[inline(always)] + pub fn underrun(&self) -> UNDERRUN_R { + UNDERRUN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Data Buffer Empty"] + #[inline(always)] + pub fn empty(&self) -> EMPTY_R { + EMPTY_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Underrun"] + #[inline(always)] + pub fn underrun(&mut self) -> UNDERRUN_W { + UNDERRUN_W { w: self } + } + #[doc = "Bit 1 - Data Buffer Empty"] + #[inline(always)] + pub fn empty(&mut self) -> EMPTY_W { + EMPTY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/dac/status.rs b/pac/atsamc21j/src/dac/status.rs new file mode 100644 index 000000000000..9b5a27716dab --- /dev/null +++ b/pac/atsamc21j/src/dac/status.rs @@ -0,0 +1,53 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `READY` reader - Ready"] +pub struct READY_R(crate::FieldReader); +impl READY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + READY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for READY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Ready"] + #[inline(always)] + pub fn ready(&self) -> READY_R { + READY_R::new((self.bits & 0x01) != 0) + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/dac/syncbusy.rs b/pac/atsamc21j/src/dac/syncbusy.rs new file mode 100644 index 000000000000..490533dae28e --- /dev/null +++ b/pac/atsamc21j/src/dac/syncbusy.rs @@ -0,0 +1,113 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` reader - Data"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATABUF` reader - Data Buffer"] +pub struct DATABUF_R(crate::FieldReader); +impl DATABUF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DATABUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATABUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Data"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Data Buffer"] + #[inline(always)] + pub fn databuf(&self) -> DATABUF_R { + DATABUF_R::new(((self.bits >> 3) & 0x01) != 0) + } +} +#[doc = "Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/divas.rs b/pac/atsamc21j/src/divas.rs new file mode 100644 index 000000000000..dbc2f5f226da --- /dev/null +++ b/pac/atsamc21j/src/divas.rs @@ -0,0 +1,48 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrla: crate::Reg, + _reserved1: [u8; 0x03], + #[doc = "0x04 - Status"] + pub status: crate::Reg, + _reserved2: [u8; 0x03], + #[doc = "0x08 - Dividend"] + pub dividend: crate::Reg, + #[doc = "0x0c - Divisor"] + pub divisor: crate::Reg, + #[doc = "0x10 - Result"] + pub result: crate::Reg, + #[doc = "0x14 - Remainder"] + pub rem: crate::Reg, + #[doc = "0x18 - Square Root Input"] + pub sqrnum: crate::Reg, +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control"] +pub mod ctrla; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "DIVIDEND register accessor: an alias for `Reg`"] +pub type DIVIDEND = crate::Reg; +#[doc = "Dividend"] +pub mod dividend; +#[doc = "DIVISOR register accessor: an alias for `Reg`"] +pub type DIVISOR = crate::Reg; +#[doc = "Divisor"] +pub mod divisor; +#[doc = "RESULT register accessor: an alias for `Reg`"] +pub type RESULT = crate::Reg; +#[doc = "Result"] +pub mod result; +#[doc = "REM register accessor: an alias for `Reg`"] +pub type REM = crate::Reg; +#[doc = "Remainder"] +pub mod rem; +#[doc = "SQRNUM register accessor: an alias for `Reg`"] +pub type SQRNUM = crate::Reg; +#[doc = "Square Root Input"] +pub mod sqrnum; diff --git a/pac/atsamc21j/src/divas/ctrla.rs b/pac/atsamc21j/src/divas/ctrla.rs new file mode 100644 index 000000000000..7f79349da05c --- /dev/null +++ b/pac/atsamc21j/src/divas/ctrla.rs @@ -0,0 +1,160 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SIGNED` reader - Signed"] +pub struct SIGNED_R(crate::FieldReader); +impl SIGNED_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SIGNED_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SIGNED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SIGNED` writer - Signed"] +pub struct SIGNED_W<'a> { + w: &'a mut W, +} +impl<'a> SIGNED_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `DLZ` reader - Disable Leading Zero Optimization"] +pub struct DLZ_R(crate::FieldReader); +impl DLZ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DLZ_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DLZ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DLZ` writer - Disable Leading Zero Optimization"] +pub struct DLZ_W<'a> { + w: &'a mut W, +} +impl<'a> DLZ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - Signed"] + #[inline(always)] + pub fn signed(&self) -> SIGNED_R { + SIGNED_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Disable Leading Zero Optimization"] + #[inline(always)] + pub fn dlz(&self) -> DLZ_R { + DLZ_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Signed"] + #[inline(always)] + pub fn signed(&mut self) -> SIGNED_W { + SIGNED_W { w: self } + } + #[doc = "Bit 1 - Disable Leading Zero Optimization"] + #[inline(always)] + pub fn dlz(&mut self) -> DLZ_W { + DLZ_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/divas/dividend.rs b/pac/atsamc21j/src/divas/dividend.rs new file mode 100644 index 000000000000..215f44261a6c --- /dev/null +++ b/pac/atsamc21j/src/divas/dividend.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DIVIDEND` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIVIDEND` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIVIDEND` reader - DIVIDEND"] +pub struct DIVIDEND_R(crate::FieldReader); +impl DIVIDEND_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + DIVIDEND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIVIDEND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIVIDEND` writer - DIVIDEND"] +pub struct DIVIDEND_W<'a> { + w: &'a mut W, +} +impl<'a> DIVIDEND_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - DIVIDEND"] + #[inline(always)] + pub fn dividend(&self) -> DIVIDEND_R { + DIVIDEND_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - DIVIDEND"] + #[inline(always)] + pub fn dividend(&mut self) -> DIVIDEND_W { + DIVIDEND_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Dividend\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dividend](index.html) module"] +pub struct DIVIDEND_SPEC; +impl crate::RegisterSpec for DIVIDEND_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dividend::R](R) reader structure"] +impl crate::Readable for DIVIDEND_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dividend::W](W) writer structure"] +impl crate::Writable for DIVIDEND_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DIVIDEND to value 0"] +impl crate::Resettable for DIVIDEND_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/divas/divisor.rs b/pac/atsamc21j/src/divas/divisor.rs new file mode 100644 index 000000000000..b711870a5cd6 --- /dev/null +++ b/pac/atsamc21j/src/divas/divisor.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DIVISOR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIVISOR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIVISOR` reader - DIVISOR"] +pub struct DIVISOR_R(crate::FieldReader); +impl DIVISOR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + DIVISOR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIVISOR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIVISOR` writer - DIVISOR"] +pub struct DIVISOR_W<'a> { + w: &'a mut W, +} +impl<'a> DIVISOR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - DIVISOR"] + #[inline(always)] + pub fn divisor(&self) -> DIVISOR_R { + DIVISOR_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - DIVISOR"] + #[inline(always)] + pub fn divisor(&mut self) -> DIVISOR_W { + DIVISOR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Divisor\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [divisor](index.html) module"] +pub struct DIVISOR_SPEC; +impl crate::RegisterSpec for DIVISOR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [divisor::R](R) reader structure"] +impl crate::Readable for DIVISOR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [divisor::W](W) writer structure"] +impl crate::Writable for DIVISOR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DIVISOR to value 0"] +impl crate::Resettable for DIVISOR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/divas/rem.rs b/pac/atsamc21j/src/divas/rem.rs new file mode 100644 index 000000000000..76f3a90878ed --- /dev/null +++ b/pac/atsamc21j/src/divas/rem.rs @@ -0,0 +1,53 @@ +#[doc = "Register `REM` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `REM` reader - REM"] +pub struct REM_R(crate::FieldReader); +impl REM_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + REM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - REM"] + #[inline(always)] + pub fn rem(&self) -> REM_R { + REM_R::new(self.bits as u32) + } +} +#[doc = "Remainder\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rem](index.html) module"] +pub struct REM_SPEC; +impl crate::RegisterSpec for REM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rem::R](R) reader structure"] +impl crate::Readable for REM_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets REM to value 0"] +impl crate::Resettable for REM_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/divas/result.rs b/pac/atsamc21j/src/divas/result.rs new file mode 100644 index 000000000000..85fc1a025f9e --- /dev/null +++ b/pac/atsamc21j/src/divas/result.rs @@ -0,0 +1,53 @@ +#[doc = "Register `RESULT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `RESULT` reader - RESULT"] +pub struct RESULT_R(crate::FieldReader); +impl RESULT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + RESULT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESULT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - RESULT"] + #[inline(always)] + pub fn result(&self) -> RESULT_R { + RESULT_R::new(self.bits as u32) + } +} +#[doc = "Result\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [result](index.html) module"] +pub struct RESULT_SPEC; +impl crate::RegisterSpec for RESULT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [result::R](R) reader structure"] +impl crate::Readable for RESULT_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets RESULT to value 0"] +impl crate::Resettable for RESULT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/divas/sqrnum.rs b/pac/atsamc21j/src/divas/sqrnum.rs new file mode 100644 index 000000000000..cc0ce6806beb --- /dev/null +++ b/pac/atsamc21j/src/divas/sqrnum.rs @@ -0,0 +1,103 @@ +#[doc = "Register `SQRNUM` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SQRNUM` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SQRNUM` reader - Square Root Input"] +pub struct SQRNUM_R(crate::FieldReader); +impl SQRNUM_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + SQRNUM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SQRNUM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SQRNUM` writer - Square Root Input"] +pub struct SQRNUM_W<'a> { + w: &'a mut W, +} +impl<'a> SQRNUM_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Square Root Input"] + #[inline(always)] + pub fn sqrnum(&self) -> SQRNUM_R { + SQRNUM_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Square Root Input"] + #[inline(always)] + pub fn sqrnum(&mut self) -> SQRNUM_W { + SQRNUM_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Square Root Input\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sqrnum](index.html) module"] +pub struct SQRNUM_SPEC; +impl crate::RegisterSpec for SQRNUM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [sqrnum::R](R) reader structure"] +impl crate::Readable for SQRNUM_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [sqrnum::W](W) writer structure"] +impl crate::Writable for SQRNUM_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SQRNUM to value 0"] +impl crate::Resettable for SQRNUM_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/divas/status.rs b/pac/atsamc21j/src/divas/status.rs new file mode 100644 index 000000000000..feffbccec659 --- /dev/null +++ b/pac/atsamc21j/src/divas/status.rs @@ -0,0 +1,160 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BUSY` reader - DIVAS Accelerator Busy"] +pub struct BUSY_R(crate::FieldReader); +impl BUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSY` writer - DIVAS Accelerator Busy"] +pub struct BUSY_W<'a> { + w: &'a mut W, +} +impl<'a> BUSY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `DBZ` reader - Writing a one to this bit clears DBZ to zero"] +pub struct DBZ_R(crate::FieldReader); +impl DBZ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBZ_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBZ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBZ` writer - Writing a one to this bit clears DBZ to zero"] +pub struct DBZ_W<'a> { + w: &'a mut W, +} +impl<'a> DBZ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - DIVAS Accelerator Busy"] + #[inline(always)] + pub fn busy(&self) -> BUSY_R { + BUSY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Writing a one to this bit clears DBZ to zero"] + #[inline(always)] + pub fn dbz(&self) -> DBZ_R { + DBZ_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - DIVAS Accelerator Busy"] + #[inline(always)] + pub fn busy(&mut self) -> BUSY_W { + BUSY_W { w: self } + } + #[doc = "Bit 1 - Writing a one to this bit clears DBZ to zero"] + #[inline(always)] + pub fn dbz(&mut self) -> DBZ_W { + DBZ_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/dmac.rs b/pac/atsamc21j/src/dmac.rs new file mode 100644 index 000000000000..c23d36697550 --- /dev/null +++ b/pac/atsamc21j/src/dmac.rs @@ -0,0 +1,148 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrl: crate::Reg, + #[doc = "0x02 - CRC Control"] + pub crcctrl: crate::Reg, + #[doc = "0x04 - CRC Data Input"] + pub crcdatain: crate::Reg, + #[doc = "0x08 - CRC Checksum"] + pub crcchksum: crate::Reg, + #[doc = "0x0c - CRC Status"] + pub crcstatus: crate::Reg, + #[doc = "0x0d - Debug Control"] + pub dbgctrl: crate::Reg, + #[doc = "0x0e - QOS Control"] + pub qosctrl: crate::Reg, + _reserved7: [u8; 0x01], + #[doc = "0x10 - Software Trigger Control"] + pub swtrigctrl: crate::Reg, + #[doc = "0x14 - Priority Control 0"] + pub prictrl0: crate::Reg, + _reserved9: [u8; 0x08], + #[doc = "0x20 - Interrupt Pending"] + pub intpend: crate::Reg, + _reserved10: [u8; 0x02], + #[doc = "0x24 - Interrupt Status"] + pub intstatus: crate::Reg, + #[doc = "0x28 - Busy Channels"] + pub busych: crate::Reg, + #[doc = "0x2c - Pending Channels"] + pub pendch: crate::Reg, + #[doc = "0x30 - Active Channel and Levels"] + pub active: crate::Reg, + #[doc = "0x34 - Descriptor Memory Section Base Address"] + pub baseaddr: crate::Reg, + #[doc = "0x38 - Write-Back Memory Section Base Address"] + pub wrbaddr: crate::Reg, + _reserved16: [u8; 0x03], + #[doc = "0x3f - Channel ID"] + pub chid: crate::Reg, + #[doc = "0x40 - Channel Control A"] + pub chctrla: crate::Reg, + _reserved18: [u8; 0x03], + #[doc = "0x44 - Channel Control B"] + pub chctrlb: crate::Reg, + _reserved19: [u8; 0x04], + #[doc = "0x4c - Channel Interrupt Enable Clear"] + pub chintenclr: crate::Reg, + #[doc = "0x4d - Channel Interrupt Enable Set"] + pub chintenset: crate::Reg, + #[doc = "0x4e - Channel Interrupt Flag Status and Clear"] + pub chintflag: crate::Reg, + #[doc = "0x4f - Channel Status"] + pub chstatus: crate::Reg, +} +#[doc = "CTRL register accessor: an alias for `Reg`"] +pub type CTRL = crate::Reg; +#[doc = "Control"] +pub mod ctrl; +#[doc = "CRCCTRL register accessor: an alias for `Reg`"] +pub type CRCCTRL = crate::Reg; +#[doc = "CRC Control"] +pub mod crcctrl; +#[doc = "CRCDATAIN register accessor: an alias for `Reg`"] +pub type CRCDATAIN = crate::Reg; +#[doc = "CRC Data Input"] +pub mod crcdatain; +#[doc = "CRCCHKSUM register accessor: an alias for `Reg`"] +pub type CRCCHKSUM = crate::Reg; +#[doc = "CRC Checksum"] +pub mod crcchksum; +#[doc = "CRCSTATUS register accessor: an alias for `Reg`"] +pub type CRCSTATUS = crate::Reg; +#[doc = "CRC Status"] +pub mod crcstatus; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "QOSCTRL register accessor: an alias for `Reg`"] +pub type QOSCTRL = crate::Reg; +#[doc = "QOS Control"] +pub mod qosctrl; +#[doc = "SWTRIGCTRL register accessor: an alias for `Reg`"] +pub type SWTRIGCTRL = crate::Reg; +#[doc = "Software Trigger Control"] +pub mod swtrigctrl; +#[doc = "PRICTRL0 register accessor: an alias for `Reg`"] +pub type PRICTRL0 = crate::Reg; +#[doc = "Priority Control 0"] +pub mod prictrl0; +#[doc = "INTPEND register accessor: an alias for `Reg`"] +pub type INTPEND = crate::Reg; +#[doc = "Interrupt Pending"] +pub mod intpend; +#[doc = "INTSTATUS register accessor: an alias for `Reg`"] +pub type INTSTATUS = crate::Reg; +#[doc = "Interrupt Status"] +pub mod intstatus; +#[doc = "BUSYCH register accessor: an alias for `Reg`"] +pub type BUSYCH = crate::Reg; +#[doc = "Busy Channels"] +pub mod busych; +#[doc = "PENDCH register accessor: an alias for `Reg`"] +pub type PENDCH = crate::Reg; +#[doc = "Pending Channels"] +pub mod pendch; +#[doc = "ACTIVE register accessor: an alias for `Reg`"] +pub type ACTIVE = crate::Reg; +#[doc = "Active Channel and Levels"] +pub mod active; +#[doc = "BASEADDR register accessor: an alias for `Reg`"] +pub type BASEADDR = crate::Reg; +#[doc = "Descriptor Memory Section Base Address"] +pub mod baseaddr; +#[doc = "WRBADDR register accessor: an alias for `Reg`"] +pub type WRBADDR = crate::Reg; +#[doc = "Write-Back Memory Section Base Address"] +pub mod wrbaddr; +#[doc = "CHID register accessor: an alias for `Reg`"] +pub type CHID = crate::Reg; +#[doc = "Channel ID"] +pub mod chid; +#[doc = "CHCTRLA register accessor: an alias for `Reg`"] +pub type CHCTRLA = crate::Reg; +#[doc = "Channel Control A"] +pub mod chctrla; +#[doc = "CHCTRLB register accessor: an alias for `Reg`"] +pub type CHCTRLB = crate::Reg; +#[doc = "Channel Control B"] +pub mod chctrlb; +#[doc = "CHINTENCLR register accessor: an alias for `Reg`"] +pub type CHINTENCLR = crate::Reg; +#[doc = "Channel Interrupt Enable Clear"] +pub mod chintenclr; +#[doc = "CHINTENSET register accessor: an alias for `Reg`"] +pub type CHINTENSET = crate::Reg; +#[doc = "Channel Interrupt Enable Set"] +pub mod chintenset; +#[doc = "CHINTFLAG register accessor: an alias for `Reg`"] +pub type CHINTFLAG = crate::Reg; +#[doc = "Channel Interrupt Flag Status and Clear"] +pub mod chintflag; +#[doc = "CHSTATUS register accessor: an alias for `Reg`"] +pub type CHSTATUS = crate::Reg; +#[doc = "Channel Status"] +pub mod chstatus; diff --git a/pac/atsamc21j/src/dmac/active.rs b/pac/atsamc21j/src/dmac/active.rs new file mode 100644 index 000000000000..c3cc5a0420bc --- /dev/null +++ b/pac/atsamc21j/src/dmac/active.rs @@ -0,0 +1,173 @@ +#[doc = "Register `ACTIVE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `LVLEX0` reader - Level 0 Channel Trigger Request Executing"] +pub struct LVLEX0_R(crate::FieldReader); +impl LVLEX0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LVLEX0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEX0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLEX1` reader - Level 1 Channel Trigger Request Executing"] +pub struct LVLEX1_R(crate::FieldReader); +impl LVLEX1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LVLEX1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEX1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLEX2` reader - Level 2 Channel Trigger Request Executing"] +pub struct LVLEX2_R(crate::FieldReader); +impl LVLEX2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LVLEX2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEX2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLEX3` reader - Level 3 Channel Trigger Request Executing"] +pub struct LVLEX3_R(crate::FieldReader); +impl LVLEX3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LVLEX3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEX3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ID` reader - Active Channel ID"] +pub struct ID_R(crate::FieldReader); +impl ID_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ID_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ID_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ABUSY` reader - Active Channel Busy"] +pub struct ABUSY_R(crate::FieldReader); +impl ABUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ABUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ABUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BTCNT` reader - Active Channel Block Transfer Count"] +pub struct BTCNT_R(crate::FieldReader); +impl BTCNT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BTCNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BTCNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Level 0 Channel Trigger Request Executing"] + #[inline(always)] + pub fn lvlex0(&self) -> LVLEX0_R { + LVLEX0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Level 1 Channel Trigger Request Executing"] + #[inline(always)] + pub fn lvlex1(&self) -> LVLEX1_R { + LVLEX1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Level 2 Channel Trigger Request Executing"] + #[inline(always)] + pub fn lvlex2(&self) -> LVLEX2_R { + LVLEX2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Level 3 Channel Trigger Request Executing"] + #[inline(always)] + pub fn lvlex3(&self) -> LVLEX3_R { + LVLEX3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bits 8:12 - Active Channel ID"] + #[inline(always)] + pub fn id(&self) -> ID_R { + ID_R::new(((self.bits >> 8) & 0x1f) as u8) + } + #[doc = "Bit 15 - Active Channel Busy"] + #[inline(always)] + pub fn abusy(&self) -> ABUSY_R { + ABUSY_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:31 - Active Channel Block Transfer Count"] + #[inline(always)] + pub fn btcnt(&self) -> BTCNT_R { + BTCNT_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[doc = "Active Channel and Levels\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [active](index.html) module"] +pub struct ACTIVE_SPEC; +impl crate::RegisterSpec for ACTIVE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [active::R](R) reader structure"] +impl crate::Readable for ACTIVE_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets ACTIVE to value 0"] +impl crate::Resettable for ACTIVE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/dmac/baseaddr.rs b/pac/atsamc21j/src/dmac/baseaddr.rs new file mode 100644 index 000000000000..cec8c8cf0777 --- /dev/null +++ b/pac/atsamc21j/src/dmac/baseaddr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `BASEADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BASEADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BASEADDR` reader - Descriptor Memory Base Address"] +pub struct BASEADDR_R(crate::FieldReader); +impl BASEADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + BASEADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BASEADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BASEADDR` writer - Descriptor Memory Base Address"] +pub struct BASEADDR_W<'a> { + w: &'a mut W, +} +impl<'a> BASEADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Descriptor Memory Base Address"] + #[inline(always)] + pub fn baseaddr(&self) -> BASEADDR_R { + BASEADDR_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Descriptor Memory Base Address"] + #[inline(always)] + pub fn baseaddr(&mut self) -> BASEADDR_W { + BASEADDR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Descriptor Memory Section Base Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baseaddr](index.html) module"] +pub struct BASEADDR_SPEC; +impl crate::RegisterSpec for BASEADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [baseaddr::R](R) reader structure"] +impl crate::Readable for BASEADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baseaddr::W](W) writer structure"] +impl crate::Writable for BASEADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BASEADDR to value 0"] +impl crate::Resettable for BASEADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/dmac/busych.rs b/pac/atsamc21j/src/dmac/busych.rs new file mode 100644 index 000000000000..6f9419d5828b --- /dev/null +++ b/pac/atsamc21j/src/dmac/busych.rs @@ -0,0 +1,273 @@ +#[doc = "Register `BUSYCH` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `BUSYCH0` reader - Busy Channel 0"] +pub struct BUSYCH0_R(crate::FieldReader); +impl BUSYCH0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH1` reader - Busy Channel 1"] +pub struct BUSYCH1_R(crate::FieldReader); +impl BUSYCH1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH2` reader - Busy Channel 2"] +pub struct BUSYCH2_R(crate::FieldReader); +impl BUSYCH2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH3` reader - Busy Channel 3"] +pub struct BUSYCH3_R(crate::FieldReader); +impl BUSYCH3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH4` reader - Busy Channel 4"] +pub struct BUSYCH4_R(crate::FieldReader); +impl BUSYCH4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH5` reader - Busy Channel 5"] +pub struct BUSYCH5_R(crate::FieldReader); +impl BUSYCH5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH6` reader - Busy Channel 6"] +pub struct BUSYCH6_R(crate::FieldReader); +impl BUSYCH6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH7` reader - Busy Channel 7"] +pub struct BUSYCH7_R(crate::FieldReader); +impl BUSYCH7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH8` reader - Busy Channel 8"] +pub struct BUSYCH8_R(crate::FieldReader); +impl BUSYCH8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH9` reader - Busy Channel 9"] +pub struct BUSYCH9_R(crate::FieldReader); +impl BUSYCH9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH10` reader - Busy Channel 10"] +pub struct BUSYCH10_R(crate::FieldReader); +impl BUSYCH10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH11` reader - Busy Channel 11"] +pub struct BUSYCH11_R(crate::FieldReader); +impl BUSYCH11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Busy Channel 0"] + #[inline(always)] + pub fn busych0(&self) -> BUSYCH0_R { + BUSYCH0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Busy Channel 1"] + #[inline(always)] + pub fn busych1(&self) -> BUSYCH1_R { + BUSYCH1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Busy Channel 2"] + #[inline(always)] + pub fn busych2(&self) -> BUSYCH2_R { + BUSYCH2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Busy Channel 3"] + #[inline(always)] + pub fn busych3(&self) -> BUSYCH3_R { + BUSYCH3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Busy Channel 4"] + #[inline(always)] + pub fn busych4(&self) -> BUSYCH4_R { + BUSYCH4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Busy Channel 5"] + #[inline(always)] + pub fn busych5(&self) -> BUSYCH5_R { + BUSYCH5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Busy Channel 6"] + #[inline(always)] + pub fn busych6(&self) -> BUSYCH6_R { + BUSYCH6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Busy Channel 7"] + #[inline(always)] + pub fn busych7(&self) -> BUSYCH7_R { + BUSYCH7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Busy Channel 8"] + #[inline(always)] + pub fn busych8(&self) -> BUSYCH8_R { + BUSYCH8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Busy Channel 9"] + #[inline(always)] + pub fn busych9(&self) -> BUSYCH9_R { + BUSYCH9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Busy Channel 10"] + #[inline(always)] + pub fn busych10(&self) -> BUSYCH10_R { + BUSYCH10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Busy Channel 11"] + #[inline(always)] + pub fn busych11(&self) -> BUSYCH11_R { + BUSYCH11_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +#[doc = "Busy Channels\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [busych](index.html) module"] +pub struct BUSYCH_SPEC; +impl crate::RegisterSpec for BUSYCH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [busych::R](R) reader structure"] +impl crate::Readable for BUSYCH_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets BUSYCH to value 0"] +impl crate::Resettable for BUSYCH_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/dmac/chctrla.rs b/pac/atsamc21j/src/dmac/chctrla.rs new file mode 100644 index 000000000000..22e8d456e05c --- /dev/null +++ b/pac/atsamc21j/src/dmac/chctrla.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CHCTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHCTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Channel Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Channel Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Channel Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Channel Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Channel run in standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Channel run in standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - Channel Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 6 - Channel run in standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Channel Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 6 - Channel run in standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chctrla](index.html) module"] +pub struct CHCTRLA_SPEC; +impl crate::RegisterSpec for CHCTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [chctrla::R](R) reader structure"] +impl crate::Readable for CHCTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chctrla::W](W) writer structure"] +impl crate::Writable for CHCTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHCTRLA to value 0"] +impl crate::Resettable for CHCTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/dmac/chctrlb.rs b/pac/atsamc21j/src/dmac/chctrlb.rs new file mode 100644 index 000000000000..6299733fed6d --- /dev/null +++ b/pac/atsamc21j/src/dmac/chctrlb.rs @@ -0,0 +1,1318 @@ +#[doc = "Register `CHCTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHCTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Event Input Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EVACT_A { + #[doc = "0: No action"] + NOACT = 0, + #[doc = "1: Transfer and periodic transfer trigger"] + TRIG = 1, + #[doc = "2: Conditional transfer trigger"] + CTRIG = 2, + #[doc = "3: Conditional block transfer"] + CBLOCK = 3, + #[doc = "4: Channel suspend operation"] + SUSPEND = 4, + #[doc = "5: Channel resume operation"] + RESUME = 5, + #[doc = "6: Skip next block suspend action"] + SSKIP = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EVACT_A) -> Self { + variant as _ + } +} +#[doc = "Field `EVACT` reader - Event Input Action"] +pub struct EVACT_R(crate::FieldReader); +impl EVACT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(EVACT_A::NOACT), + 1 => Some(EVACT_A::TRIG), + 2 => Some(EVACT_A::CTRIG), + 3 => Some(EVACT_A::CBLOCK), + 4 => Some(EVACT_A::SUSPEND), + 5 => Some(EVACT_A::RESUME), + 6 => Some(EVACT_A::SSKIP), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NOACT`"] + #[inline(always)] + pub fn is_noact(&self) -> bool { + **self == EVACT_A::NOACT + } + #[doc = "Checks if the value of the field is `TRIG`"] + #[inline(always)] + pub fn is_trig(&self) -> bool { + **self == EVACT_A::TRIG + } + #[doc = "Checks if the value of the field is `CTRIG`"] + #[inline(always)] + pub fn is_ctrig(&self) -> bool { + **self == EVACT_A::CTRIG + } + #[doc = "Checks if the value of the field is `CBLOCK`"] + #[inline(always)] + pub fn is_cblock(&self) -> bool { + **self == EVACT_A::CBLOCK + } + #[doc = "Checks if the value of the field is `SUSPEND`"] + #[inline(always)] + pub fn is_suspend(&self) -> bool { + **self == EVACT_A::SUSPEND + } + #[doc = "Checks if the value of the field is `RESUME`"] + #[inline(always)] + pub fn is_resume(&self) -> bool { + **self == EVACT_A::RESUME + } + #[doc = "Checks if the value of the field is `SSKIP`"] + #[inline(always)] + pub fn is_sskip(&self) -> bool { + **self == EVACT_A::SSKIP + } +} +impl core::ops::Deref for EVACT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT` writer - Event Input Action"] +pub struct EVACT_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EVACT_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn noact(self) -> &'a mut W { + self.variant(EVACT_A::NOACT) + } + #[doc = "Transfer and periodic transfer trigger"] + #[inline(always)] + pub fn trig(self) -> &'a mut W { + self.variant(EVACT_A::TRIG) + } + #[doc = "Conditional transfer trigger"] + #[inline(always)] + pub fn ctrig(self) -> &'a mut W { + self.variant(EVACT_A::CTRIG) + } + #[doc = "Conditional block transfer"] + #[inline(always)] + pub fn cblock(self) -> &'a mut W { + self.variant(EVACT_A::CBLOCK) + } + #[doc = "Channel suspend operation"] + #[inline(always)] + pub fn suspend(self) -> &'a mut W { + self.variant(EVACT_A::SUSPEND) + } + #[doc = "Channel resume operation"] + #[inline(always)] + pub fn resume(self) -> &'a mut W { + self.variant(EVACT_A::RESUME) + } + #[doc = "Skip next block suspend action"] + #[inline(always)] + pub fn sskip(self) -> &'a mut W { + self.variant(EVACT_A::SSKIP) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Field `EVIE` reader - Channel Event Input Enable"] +pub struct EVIE_R(crate::FieldReader); +impl EVIE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVIE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVIE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVIE` writer - Channel Event Input Enable"] +pub struct EVIE_W<'a> { + w: &'a mut W, +} +impl<'a> EVIE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `EVOE` reader - Channel Event Output Enable"] +pub struct EVOE_R(crate::FieldReader); +impl EVOE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVOE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVOE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVOE` writer - Channel Event Output Enable"] +pub struct EVOE_W<'a> { + w: &'a mut W, +} +impl<'a> EVOE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Channel Arbitration Level\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum LVL_A { + #[doc = "0: Channel Priority Level 0"] + LVL0 = 0, + #[doc = "1: Channel Priority Level 1"] + LVL1 = 1, + #[doc = "2: Channel Priority Level 2"] + LVL2 = 2, + #[doc = "3: Channel Priority Level 3"] + LVL3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LVL_A) -> Self { + variant as _ + } +} +#[doc = "Field `LVL` reader - Channel Arbitration Level"] +pub struct LVL_R(crate::FieldReader); +impl LVL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LVL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> LVL_A { + match self.bits { + 0 => LVL_A::LVL0, + 1 => LVL_A::LVL1, + 2 => LVL_A::LVL2, + 3 => LVL_A::LVL3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `LVL0`"] + #[inline(always)] + pub fn is_lvl0(&self) -> bool { + **self == LVL_A::LVL0 + } + #[doc = "Checks if the value of the field is `LVL1`"] + #[inline(always)] + pub fn is_lvl1(&self) -> bool { + **self == LVL_A::LVL1 + } + #[doc = "Checks if the value of the field is `LVL2`"] + #[inline(always)] + pub fn is_lvl2(&self) -> bool { + **self == LVL_A::LVL2 + } + #[doc = "Checks if the value of the field is `LVL3`"] + #[inline(always)] + pub fn is_lvl3(&self) -> bool { + **self == LVL_A::LVL3 + } +} +impl core::ops::Deref for LVL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVL` writer - Channel Arbitration Level"] +pub struct LVL_W<'a> { + w: &'a mut W, +} +impl<'a> LVL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: LVL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Channel Priority Level 0"] + #[inline(always)] + pub fn lvl0(self) -> &'a mut W { + self.variant(LVL_A::LVL0) + } + #[doc = "Channel Priority Level 1"] + #[inline(always)] + pub fn lvl1(self) -> &'a mut W { + self.variant(LVL_A::LVL1) + } + #[doc = "Channel Priority Level 2"] + #[inline(always)] + pub fn lvl2(self) -> &'a mut W { + self.variant(LVL_A::LVL2) + } + #[doc = "Channel Priority Level 3"] + #[inline(always)] + pub fn lvl3(self) -> &'a mut W { + self.variant(LVL_A::LVL3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 5)) | ((value as u32 & 0x03) << 5); + self.w + } +} +#[doc = "Trigger Source\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum TRIGSRC_A { + #[doc = "0: Only software/event triggers"] + DISABLE = 0, + #[doc = "1: TSENS Result Ready Trigger"] + TSENS = 1, + #[doc = "2: SERCOM0 RX Trigger"] + SERCOM0_RX = 2, + #[doc = "3: SERCOM0 TX Trigger"] + SERCOM0_TX = 3, + #[doc = "4: SERCOM1 RX Trigger"] + SERCOM1_RX = 4, + #[doc = "5: SERCOM1 TX Trigger"] + SERCOM1_TX = 5, + #[doc = "6: SERCOM2 RX Trigger"] + SERCOM2_RX = 6, + #[doc = "7: SERCOM2 TX Trigger"] + SERCOM2_TX = 7, + #[doc = "8: SERCOM3 RX Trigger"] + SERCOM3_RX = 8, + #[doc = "9: SERCOM3 TX Trigger"] + SERCOM3_TX = 9, + #[doc = "10: SERCOM4 RX Trigger"] + SERCOM4_RX = 10, + #[doc = "11: SERCOM4 TX Trigger"] + SERCOM4_TX = 11, + #[doc = "12: SERCOM5 RX Trigger"] + SERCOM5_RX = 12, + #[doc = "13: SERCOM5 TX Trigger"] + SERCOM5_TX = 13, + #[doc = "14: CAN0 Debug Trigger Reserved"] + CAN0_DEBUG = 14, + #[doc = "15: CAN1 Debug Trigger Reserved"] + CAN1_DEBUG = 15, + #[doc = "16: TCC0 Overflow Trigger"] + TCC0_OVF = 16, + #[doc = "17: TCC0 Match/Compare 0 Trigger"] + TCC0_MC0 = 17, + #[doc = "18: TCC0 Match/Compare 1 Trigger"] + TCC0_MC1 = 18, + #[doc = "19: TCC0 Match/Compare 2 Trigger"] + TCC0_MC2 = 19, + #[doc = "20: TCC0 Match/Compare 3 Trigger"] + TCC0_MC3 = 20, + #[doc = "21: TCC1 Overflow Trigger"] + TCC1_OVF = 21, + #[doc = "22: TCC1 Match/Compare 0 Trigger"] + TCC1_MC0 = 22, + #[doc = "23: TCC1 Match/Compare 1 Trigger"] + TCC1_MC1 = 23, + #[doc = "24: TCC2 Overflow Trigger"] + TCC2_OVF = 24, + #[doc = "25: TCC2 Match/Compare 0 Trigger"] + TCC2_MC0 = 25, + #[doc = "26: TCC2 Match/Compare 1 Trigger"] + TCC2_MC1 = 26, + #[doc = "27: TC0 Overflow Trigger"] + TC0_OVF = 27, + #[doc = "28: TC0 Match/Compare 0 Trigger"] + TC0_MC0 = 28, + #[doc = "29: TC0 Match/Compare 1 Trigger"] + TC0_MC1 = 29, + #[doc = "30: TC1 Overflow Trigger"] + TC1_OVF = 30, + #[doc = "31: TC1 Match/Compare 0 Trigger"] + TC1_MC0 = 31, + #[doc = "32: TC1 Match/Compare 1 Trigger"] + TC1_MC1 = 32, + #[doc = "33: TC2 Overflow Trigger"] + TC2_OVF = 33, + #[doc = "34: TC2 Match/Compare 0 Trigger"] + TC2_MC0 = 34, + #[doc = "35: TC2 Match/Compare 1 Trigger"] + TC2_MC1 = 35, + #[doc = "36: TC3 Overflow Trigger"] + TC3_OVF = 36, + #[doc = "37: TC3 Match/Compare 0 Trigger"] + TC3_MC0 = 37, + #[doc = "38: TC3 Match/Compare 1 Trigger"] + TC3_MC1 = 38, + #[doc = "39: TC4 Overflow Trigger"] + TC4_OVF = 39, + #[doc = "40: TC4 Match/Compare 0 Trigger"] + TC4_MC0 = 40, + #[doc = "41: TC4 Match/Compare 1 Trigger"] + TC4_MC1 = 41, + #[doc = "42: ADC0 Result Ready Trigger"] + ADC0_RESRDY = 42, + #[doc = "43: ADC1 Result Ready Trigger"] + ADC1_RESRDY = 43, + #[doc = "44: SDADC Result Ready Trigger"] + SDADC_RESRDY = 44, + #[doc = "45: DAC Empty Trigger"] + DAC_EMPTY = 45, + #[doc = "46: PTC End of Conversion Trigger"] + PTC_EOC = 46, + #[doc = "47: PTC Window Compare Trigger"] + PTC_WCOMP = 47, + #[doc = "48: PTC Sequence Trigger"] + PTC_SEQ = 48, +} +impl From for u8 { + #[inline(always)] + fn from(variant: TRIGSRC_A) -> Self { + variant as _ + } +} +#[doc = "Field `TRIGSRC` reader - Trigger Source"] +pub struct TRIGSRC_R(crate::FieldReader); +impl TRIGSRC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TRIGSRC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(TRIGSRC_A::DISABLE), + 1 => Some(TRIGSRC_A::TSENS), + 2 => Some(TRIGSRC_A::SERCOM0_RX), + 3 => Some(TRIGSRC_A::SERCOM0_TX), + 4 => Some(TRIGSRC_A::SERCOM1_RX), + 5 => Some(TRIGSRC_A::SERCOM1_TX), + 6 => Some(TRIGSRC_A::SERCOM2_RX), + 7 => Some(TRIGSRC_A::SERCOM2_TX), + 8 => Some(TRIGSRC_A::SERCOM3_RX), + 9 => Some(TRIGSRC_A::SERCOM3_TX), + 10 => Some(TRIGSRC_A::SERCOM4_RX), + 11 => Some(TRIGSRC_A::SERCOM4_TX), + 12 => Some(TRIGSRC_A::SERCOM5_RX), + 13 => Some(TRIGSRC_A::SERCOM5_TX), + 14 => Some(TRIGSRC_A::CAN0_DEBUG), + 15 => Some(TRIGSRC_A::CAN1_DEBUG), + 16 => Some(TRIGSRC_A::TCC0_OVF), + 17 => Some(TRIGSRC_A::TCC0_MC0), + 18 => Some(TRIGSRC_A::TCC0_MC1), + 19 => Some(TRIGSRC_A::TCC0_MC2), + 20 => Some(TRIGSRC_A::TCC0_MC3), + 21 => Some(TRIGSRC_A::TCC1_OVF), + 22 => Some(TRIGSRC_A::TCC1_MC0), + 23 => Some(TRIGSRC_A::TCC1_MC1), + 24 => Some(TRIGSRC_A::TCC2_OVF), + 25 => Some(TRIGSRC_A::TCC2_MC0), + 26 => Some(TRIGSRC_A::TCC2_MC1), + 27 => Some(TRIGSRC_A::TC0_OVF), + 28 => Some(TRIGSRC_A::TC0_MC0), + 29 => Some(TRIGSRC_A::TC0_MC1), + 30 => Some(TRIGSRC_A::TC1_OVF), + 31 => Some(TRIGSRC_A::TC1_MC0), + 32 => Some(TRIGSRC_A::TC1_MC1), + 33 => Some(TRIGSRC_A::TC2_OVF), + 34 => Some(TRIGSRC_A::TC2_MC0), + 35 => Some(TRIGSRC_A::TC2_MC1), + 36 => Some(TRIGSRC_A::TC3_OVF), + 37 => Some(TRIGSRC_A::TC3_MC0), + 38 => Some(TRIGSRC_A::TC3_MC1), + 39 => Some(TRIGSRC_A::TC4_OVF), + 40 => Some(TRIGSRC_A::TC4_MC0), + 41 => Some(TRIGSRC_A::TC4_MC1), + 42 => Some(TRIGSRC_A::ADC0_RESRDY), + 43 => Some(TRIGSRC_A::ADC1_RESRDY), + 44 => Some(TRIGSRC_A::SDADC_RESRDY), + 45 => Some(TRIGSRC_A::DAC_EMPTY), + 46 => Some(TRIGSRC_A::PTC_EOC), + 47 => Some(TRIGSRC_A::PTC_WCOMP), + 48 => Some(TRIGSRC_A::PTC_SEQ), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == TRIGSRC_A::DISABLE + } + #[doc = "Checks if the value of the field is `TSENS`"] + #[inline(always)] + pub fn is_tsens(&self) -> bool { + **self == TRIGSRC_A::TSENS + } + #[doc = "Checks if the value of the field is `SERCOM0_RX`"] + #[inline(always)] + pub fn is_sercom0_rx(&self) -> bool { + **self == TRIGSRC_A::SERCOM0_RX + } + #[doc = "Checks if the value of the field is `SERCOM0_TX`"] + #[inline(always)] + pub fn is_sercom0_tx(&self) -> bool { + **self == TRIGSRC_A::SERCOM0_TX + } + #[doc = "Checks if the value of the field is `SERCOM1_RX`"] + #[inline(always)] + pub fn is_sercom1_rx(&self) -> bool { + **self == TRIGSRC_A::SERCOM1_RX + } + #[doc = "Checks if the value of the field is `SERCOM1_TX`"] + #[inline(always)] + pub fn is_sercom1_tx(&self) -> bool { + **self == TRIGSRC_A::SERCOM1_TX + } + #[doc = "Checks if the value of the field is `SERCOM2_RX`"] + #[inline(always)] + pub fn is_sercom2_rx(&self) -> bool { + **self == TRIGSRC_A::SERCOM2_RX + } + #[doc = "Checks if the value of the field is `SERCOM2_TX`"] + #[inline(always)] + pub fn is_sercom2_tx(&self) -> bool { + **self == TRIGSRC_A::SERCOM2_TX + } + #[doc = "Checks if the value of the field is `SERCOM3_RX`"] + #[inline(always)] + pub fn is_sercom3_rx(&self) -> bool { + **self == TRIGSRC_A::SERCOM3_RX + } + #[doc = "Checks if the value of the field is `SERCOM3_TX`"] + #[inline(always)] + pub fn is_sercom3_tx(&self) -> bool { + **self == TRIGSRC_A::SERCOM3_TX + } + #[doc = "Checks if the value of the field is `SERCOM4_RX`"] + #[inline(always)] + pub fn is_sercom4_rx(&self) -> bool { + **self == TRIGSRC_A::SERCOM4_RX + } + #[doc = "Checks if the value of the field is `SERCOM4_TX`"] + #[inline(always)] + pub fn is_sercom4_tx(&self) -> bool { + **self == TRIGSRC_A::SERCOM4_TX + } + #[doc = "Checks if the value of the field is `SERCOM5_RX`"] + #[inline(always)] + pub fn is_sercom5_rx(&self) -> bool { + **self == TRIGSRC_A::SERCOM5_RX + } + #[doc = "Checks if the value of the field is `SERCOM5_TX`"] + #[inline(always)] + pub fn is_sercom5_tx(&self) -> bool { + **self == TRIGSRC_A::SERCOM5_TX + } + #[doc = "Checks if the value of the field is `CAN0_DEBUG`"] + #[inline(always)] + pub fn is_can0_debug(&self) -> bool { + **self == TRIGSRC_A::CAN0_DEBUG + } + #[doc = "Checks if the value of the field is `CAN1_DEBUG`"] + #[inline(always)] + pub fn is_can1_debug(&self) -> bool { + **self == TRIGSRC_A::CAN1_DEBUG + } + #[doc = "Checks if the value of the field is `TCC0_OVF`"] + #[inline(always)] + pub fn is_tcc0_ovf(&self) -> bool { + **self == TRIGSRC_A::TCC0_OVF + } + #[doc = "Checks if the value of the field is `TCC0_MC0`"] + #[inline(always)] + pub fn is_tcc0_mc0(&self) -> bool { + **self == TRIGSRC_A::TCC0_MC0 + } + #[doc = "Checks if the value of the field is `TCC0_MC1`"] + #[inline(always)] + pub fn is_tcc0_mc1(&self) -> bool { + **self == TRIGSRC_A::TCC0_MC1 + } + #[doc = "Checks if the value of the field is `TCC0_MC2`"] + #[inline(always)] + pub fn is_tcc0_mc2(&self) -> bool { + **self == TRIGSRC_A::TCC0_MC2 + } + #[doc = "Checks if the value of the field is `TCC0_MC3`"] + #[inline(always)] + pub fn is_tcc0_mc3(&self) -> bool { + **self == TRIGSRC_A::TCC0_MC3 + } + #[doc = "Checks if the value of the field is `TCC1_OVF`"] + #[inline(always)] + pub fn is_tcc1_ovf(&self) -> bool { + **self == TRIGSRC_A::TCC1_OVF + } + #[doc = "Checks if the value of the field is `TCC1_MC0`"] + #[inline(always)] + pub fn is_tcc1_mc0(&self) -> bool { + **self == TRIGSRC_A::TCC1_MC0 + } + #[doc = "Checks if the value of the field is `TCC1_MC1`"] + #[inline(always)] + pub fn is_tcc1_mc1(&self) -> bool { + **self == TRIGSRC_A::TCC1_MC1 + } + #[doc = "Checks if the value of the field is `TCC2_OVF`"] + #[inline(always)] + pub fn is_tcc2_ovf(&self) -> bool { + **self == TRIGSRC_A::TCC2_OVF + } + #[doc = "Checks if the value of the field is `TCC2_MC0`"] + #[inline(always)] + pub fn is_tcc2_mc0(&self) -> bool { + **self == TRIGSRC_A::TCC2_MC0 + } + #[doc = "Checks if the value of the field is `TCC2_MC1`"] + #[inline(always)] + pub fn is_tcc2_mc1(&self) -> bool { + **self == TRIGSRC_A::TCC2_MC1 + } + #[doc = "Checks if the value of the field is `TC0_OVF`"] + #[inline(always)] + pub fn is_tc0_ovf(&self) -> bool { + **self == TRIGSRC_A::TC0_OVF + } + #[doc = "Checks if the value of the field is `TC0_MC0`"] + #[inline(always)] + pub fn is_tc0_mc0(&self) -> bool { + **self == TRIGSRC_A::TC0_MC0 + } + #[doc = "Checks if the value of the field is `TC0_MC1`"] + #[inline(always)] + pub fn is_tc0_mc1(&self) -> bool { + **self == TRIGSRC_A::TC0_MC1 + } + #[doc = "Checks if the value of the field is `TC1_OVF`"] + #[inline(always)] + pub fn is_tc1_ovf(&self) -> bool { + **self == TRIGSRC_A::TC1_OVF + } + #[doc = "Checks if the value of the field is `TC1_MC0`"] + #[inline(always)] + pub fn is_tc1_mc0(&self) -> bool { + **self == TRIGSRC_A::TC1_MC0 + } + #[doc = "Checks if the value of the field is `TC1_MC1`"] + #[inline(always)] + pub fn is_tc1_mc1(&self) -> bool { + **self == TRIGSRC_A::TC1_MC1 + } + #[doc = "Checks if the value of the field is `TC2_OVF`"] + #[inline(always)] + pub fn is_tc2_ovf(&self) -> bool { + **self == TRIGSRC_A::TC2_OVF + } + #[doc = "Checks if the value of the field is `TC2_MC0`"] + #[inline(always)] + pub fn is_tc2_mc0(&self) -> bool { + **self == TRIGSRC_A::TC2_MC0 + } + #[doc = "Checks if the value of the field is `TC2_MC1`"] + #[inline(always)] + pub fn is_tc2_mc1(&self) -> bool { + **self == TRIGSRC_A::TC2_MC1 + } + #[doc = "Checks if the value of the field is `TC3_OVF`"] + #[inline(always)] + pub fn is_tc3_ovf(&self) -> bool { + **self == TRIGSRC_A::TC3_OVF + } + #[doc = "Checks if the value of the field is `TC3_MC0`"] + #[inline(always)] + pub fn is_tc3_mc0(&self) -> bool { + **self == TRIGSRC_A::TC3_MC0 + } + #[doc = "Checks if the value of the field is `TC3_MC1`"] + #[inline(always)] + pub fn is_tc3_mc1(&self) -> bool { + **self == TRIGSRC_A::TC3_MC1 + } + #[doc = "Checks if the value of the field is `TC4_OVF`"] + #[inline(always)] + pub fn is_tc4_ovf(&self) -> bool { + **self == TRIGSRC_A::TC4_OVF + } + #[doc = "Checks if the value of the field is `TC4_MC0`"] + #[inline(always)] + pub fn is_tc4_mc0(&self) -> bool { + **self == TRIGSRC_A::TC4_MC0 + } + #[doc = "Checks if the value of the field is `TC4_MC1`"] + #[inline(always)] + pub fn is_tc4_mc1(&self) -> bool { + **self == TRIGSRC_A::TC4_MC1 + } + #[doc = "Checks if the value of the field is `ADC0_RESRDY`"] + #[inline(always)] + pub fn is_adc0_resrdy(&self) -> bool { + **self == TRIGSRC_A::ADC0_RESRDY + } + #[doc = "Checks if the value of the field is `ADC1_RESRDY`"] + #[inline(always)] + pub fn is_adc1_resrdy(&self) -> bool { + **self == TRIGSRC_A::ADC1_RESRDY + } + #[doc = "Checks if the value of the field is `SDADC_RESRDY`"] + #[inline(always)] + pub fn is_sdadc_resrdy(&self) -> bool { + **self == TRIGSRC_A::SDADC_RESRDY + } + #[doc = "Checks if the value of the field is `DAC_EMPTY`"] + #[inline(always)] + pub fn is_dac_empty(&self) -> bool { + **self == TRIGSRC_A::DAC_EMPTY + } + #[doc = "Checks if the value of the field is `PTC_EOC`"] + #[inline(always)] + pub fn is_ptc_eoc(&self) -> bool { + **self == TRIGSRC_A::PTC_EOC + } + #[doc = "Checks if the value of the field is `PTC_WCOMP`"] + #[inline(always)] + pub fn is_ptc_wcomp(&self) -> bool { + **self == TRIGSRC_A::PTC_WCOMP + } + #[doc = "Checks if the value of the field is `PTC_SEQ`"] + #[inline(always)] + pub fn is_ptc_seq(&self) -> bool { + **self == TRIGSRC_A::PTC_SEQ + } +} +impl core::ops::Deref for TRIGSRC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRIGSRC` writer - Trigger Source"] +pub struct TRIGSRC_W<'a> { + w: &'a mut W, +} +impl<'a> TRIGSRC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TRIGSRC_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Only software/event triggers"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(TRIGSRC_A::DISABLE) + } + #[doc = "TSENS Result Ready Trigger"] + #[inline(always)] + pub fn tsens(self) -> &'a mut W { + self.variant(TRIGSRC_A::TSENS) + } + #[doc = "SERCOM0 RX Trigger"] + #[inline(always)] + pub fn sercom0_rx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM0_RX) + } + #[doc = "SERCOM0 TX Trigger"] + #[inline(always)] + pub fn sercom0_tx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM0_TX) + } + #[doc = "SERCOM1 RX Trigger"] + #[inline(always)] + pub fn sercom1_rx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM1_RX) + } + #[doc = "SERCOM1 TX Trigger"] + #[inline(always)] + pub fn sercom1_tx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM1_TX) + } + #[doc = "SERCOM2 RX Trigger"] + #[inline(always)] + pub fn sercom2_rx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM2_RX) + } + #[doc = "SERCOM2 TX Trigger"] + #[inline(always)] + pub fn sercom2_tx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM2_TX) + } + #[doc = "SERCOM3 RX Trigger"] + #[inline(always)] + pub fn sercom3_rx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM3_RX) + } + #[doc = "SERCOM3 TX Trigger"] + #[inline(always)] + pub fn sercom3_tx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM3_TX) + } + #[doc = "SERCOM4 RX Trigger"] + #[inline(always)] + pub fn sercom4_rx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM4_RX) + } + #[doc = "SERCOM4 TX Trigger"] + #[inline(always)] + pub fn sercom4_tx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM4_TX) + } + #[doc = "SERCOM5 RX Trigger"] + #[inline(always)] + pub fn sercom5_rx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM5_RX) + } + #[doc = "SERCOM5 TX Trigger"] + #[inline(always)] + pub fn sercom5_tx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM5_TX) + } + #[doc = "CAN0 Debug Trigger Reserved"] + #[inline(always)] + pub fn can0_debug(self) -> &'a mut W { + self.variant(TRIGSRC_A::CAN0_DEBUG) + } + #[doc = "CAN1 Debug Trigger Reserved"] + #[inline(always)] + pub fn can1_debug(self) -> &'a mut W { + self.variant(TRIGSRC_A::CAN1_DEBUG) + } + #[doc = "TCC0 Overflow Trigger"] + #[inline(always)] + pub fn tcc0_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC0_OVF) + } + #[doc = "TCC0 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tcc0_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC0_MC0) + } + #[doc = "TCC0 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tcc0_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC0_MC1) + } + #[doc = "TCC0 Match/Compare 2 Trigger"] + #[inline(always)] + pub fn tcc0_mc2(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC0_MC2) + } + #[doc = "TCC0 Match/Compare 3 Trigger"] + #[inline(always)] + pub fn tcc0_mc3(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC0_MC3) + } + #[doc = "TCC1 Overflow Trigger"] + #[inline(always)] + pub fn tcc1_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC1_OVF) + } + #[doc = "TCC1 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tcc1_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC1_MC0) + } + #[doc = "TCC1 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tcc1_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC1_MC1) + } + #[doc = "TCC2 Overflow Trigger"] + #[inline(always)] + pub fn tcc2_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC2_OVF) + } + #[doc = "TCC2 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tcc2_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC2_MC0) + } + #[doc = "TCC2 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tcc2_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC2_MC1) + } + #[doc = "TC0 Overflow Trigger"] + #[inline(always)] + pub fn tc0_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC0_OVF) + } + #[doc = "TC0 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tc0_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC0_MC0) + } + #[doc = "TC0 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tc0_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC0_MC1) + } + #[doc = "TC1 Overflow Trigger"] + #[inline(always)] + pub fn tc1_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC1_OVF) + } + #[doc = "TC1 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tc1_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC1_MC0) + } + #[doc = "TC1 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tc1_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC1_MC1) + } + #[doc = "TC2 Overflow Trigger"] + #[inline(always)] + pub fn tc2_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC2_OVF) + } + #[doc = "TC2 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tc2_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC2_MC0) + } + #[doc = "TC2 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tc2_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC2_MC1) + } + #[doc = "TC3 Overflow Trigger"] + #[inline(always)] + pub fn tc3_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC3_OVF) + } + #[doc = "TC3 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tc3_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC3_MC0) + } + #[doc = "TC3 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tc3_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC3_MC1) + } + #[doc = "TC4 Overflow Trigger"] + #[inline(always)] + pub fn tc4_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC4_OVF) + } + #[doc = "TC4 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tc4_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC4_MC0) + } + #[doc = "TC4 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tc4_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC4_MC1) + } + #[doc = "ADC0 Result Ready Trigger"] + #[inline(always)] + pub fn adc0_resrdy(self) -> &'a mut W { + self.variant(TRIGSRC_A::ADC0_RESRDY) + } + #[doc = "ADC1 Result Ready Trigger"] + #[inline(always)] + pub fn adc1_resrdy(self) -> &'a mut W { + self.variant(TRIGSRC_A::ADC1_RESRDY) + } + #[doc = "SDADC Result Ready Trigger"] + #[inline(always)] + pub fn sdadc_resrdy(self) -> &'a mut W { + self.variant(TRIGSRC_A::SDADC_RESRDY) + } + #[doc = "DAC Empty Trigger"] + #[inline(always)] + pub fn dac_empty(self) -> &'a mut W { + self.variant(TRIGSRC_A::DAC_EMPTY) + } + #[doc = "PTC End of Conversion Trigger"] + #[inline(always)] + pub fn ptc_eoc(self) -> &'a mut W { + self.variant(TRIGSRC_A::PTC_EOC) + } + #[doc = "PTC Window Compare Trigger"] + #[inline(always)] + pub fn ptc_wcomp(self) -> &'a mut W { + self.variant(TRIGSRC_A::PTC_WCOMP) + } + #[doc = "PTC Sequence Trigger"] + #[inline(always)] + pub fn ptc_seq(self) -> &'a mut W { + self.variant(TRIGSRC_A::PTC_SEQ) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 8)) | ((value as u32 & 0x3f) << 8); + self.w + } +} +#[doc = "Trigger Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum TRIGACT_A { + #[doc = "0: One trigger required for each block transfer"] + BLOCK = 0, + #[doc = "2: One trigger required for each beat transfer"] + BEAT = 2, + #[doc = "3: One trigger required for each transaction"] + TRANSACTION = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: TRIGACT_A) -> Self { + variant as _ + } +} +#[doc = "Field `TRIGACT` reader - Trigger Action"] +pub struct TRIGACT_R(crate::FieldReader); +impl TRIGACT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TRIGACT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(TRIGACT_A::BLOCK), + 2 => Some(TRIGACT_A::BEAT), + 3 => Some(TRIGACT_A::TRANSACTION), + _ => None, + } + } + #[doc = "Checks if the value of the field is `BLOCK`"] + #[inline(always)] + pub fn is_block(&self) -> bool { + **self == TRIGACT_A::BLOCK + } + #[doc = "Checks if the value of the field is `BEAT`"] + #[inline(always)] + pub fn is_beat(&self) -> bool { + **self == TRIGACT_A::BEAT + } + #[doc = "Checks if the value of the field is `TRANSACTION`"] + #[inline(always)] + pub fn is_transaction(&self) -> bool { + **self == TRIGACT_A::TRANSACTION + } +} +impl core::ops::Deref for TRIGACT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRIGACT` writer - Trigger Action"] +pub struct TRIGACT_W<'a> { + w: &'a mut W, +} +impl<'a> TRIGACT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TRIGACT_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "One trigger required for each block transfer"] + #[inline(always)] + pub fn block(self) -> &'a mut W { + self.variant(TRIGACT_A::BLOCK) + } + #[doc = "One trigger required for each beat transfer"] + #[inline(always)] + pub fn beat(self) -> &'a mut W { + self.variant(TRIGACT_A::BEAT) + } + #[doc = "One trigger required for each transaction"] + #[inline(always)] + pub fn transaction(self) -> &'a mut W { + self.variant(TRIGACT_A::TRANSACTION) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 22)) | ((value as u32 & 0x03) << 22); + self.w + } +} +#[doc = "Software Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NOACT = 0, + #[doc = "1: Channel suspend operation"] + SUSPEND = 1, + #[doc = "2: Channel resume operation"] + RESUME = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Software Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NOACT), + 1 => Some(CMD_A::SUSPEND), + 2 => Some(CMD_A::RESUME), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NOACT`"] + #[inline(always)] + pub fn is_noact(&self) -> bool { + **self == CMD_A::NOACT + } + #[doc = "Checks if the value of the field is `SUSPEND`"] + #[inline(always)] + pub fn is_suspend(&self) -> bool { + **self == CMD_A::SUSPEND + } + #[doc = "Checks if the value of the field is `RESUME`"] + #[inline(always)] + pub fn is_resume(&self) -> bool { + **self == CMD_A::RESUME + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Software Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn noact(self) -> &'a mut W { + self.variant(CMD_A::NOACT) + } + #[doc = "Channel suspend operation"] + #[inline(always)] + pub fn suspend(self) -> &'a mut W { + self.variant(CMD_A::SUSPEND) + } + #[doc = "Channel resume operation"] + #[inline(always)] + pub fn resume(self) -> &'a mut W { + self.variant(CMD_A::RESUME) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 24)) | ((value as u32 & 0x03) << 24); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Event Input Action"] + #[inline(always)] + pub fn evact(&self) -> EVACT_R { + EVACT_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 3 - Channel Event Input Enable"] + #[inline(always)] + pub fn evie(&self) -> EVIE_R { + EVIE_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Channel Event Output Enable"] + #[inline(always)] + pub fn evoe(&self) -> EVOE_R { + EVOE_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bits 5:6 - Channel Arbitration Level"] + #[inline(always)] + pub fn lvl(&self) -> LVL_R { + LVL_R::new(((self.bits >> 5) & 0x03) as u8) + } + #[doc = "Bits 8:13 - Trigger Source"] + #[inline(always)] + pub fn trigsrc(&self) -> TRIGSRC_R { + TRIGSRC_R::new(((self.bits >> 8) & 0x3f) as u8) + } + #[doc = "Bits 22:23 - Trigger Action"] + #[inline(always)] + pub fn trigact(&self) -> TRIGACT_R { + TRIGACT_R::new(((self.bits >> 22) & 0x03) as u8) + } + #[doc = "Bits 24:25 - Software Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 24) & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Event Input Action"] + #[inline(always)] + pub fn evact(&mut self) -> EVACT_W { + EVACT_W { w: self } + } + #[doc = "Bit 3 - Channel Event Input Enable"] + #[inline(always)] + pub fn evie(&mut self) -> EVIE_W { + EVIE_W { w: self } + } + #[doc = "Bit 4 - Channel Event Output Enable"] + #[inline(always)] + pub fn evoe(&mut self) -> EVOE_W { + EVOE_W { w: self } + } + #[doc = "Bits 5:6 - Channel Arbitration Level"] + #[inline(always)] + pub fn lvl(&mut self) -> LVL_W { + LVL_W { w: self } + } + #[doc = "Bits 8:13 - Trigger Source"] + #[inline(always)] + pub fn trigsrc(&mut self) -> TRIGSRC_W { + TRIGSRC_W { w: self } + } + #[doc = "Bits 22:23 - Trigger Action"] + #[inline(always)] + pub fn trigact(&mut self) -> TRIGACT_W { + TRIGACT_W { w: self } + } + #[doc = "Bits 24:25 - Software Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chctrlb](index.html) module"] +pub struct CHCTRLB_SPEC; +impl crate::RegisterSpec for CHCTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [chctrlb::R](R) reader structure"] +impl crate::Readable for CHCTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chctrlb::W](W) writer structure"] +impl crate::Writable for CHCTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHCTRLB to value 0"] +impl crate::Resettable for CHCTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/dmac/chid.rs b/pac/atsamc21j/src/dmac/chid.rs new file mode 100644 index 000000000000..19151d8e10b0 --- /dev/null +++ b/pac/atsamc21j/src/dmac/chid.rs @@ -0,0 +1,103 @@ +#[doc = "Register `CHID` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHID` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ID` reader - Channel ID"] +pub struct ID_R(crate::FieldReader); +impl ID_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ID_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ID_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ID` writer - Channel ID"] +pub struct ID_W<'a> { + w: &'a mut W, +} +impl<'a> ID_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Channel ID"] + #[inline(always)] + pub fn id(&self) -> ID_R { + ID_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Channel ID"] + #[inline(always)] + pub fn id(&mut self) -> ID_W { + ID_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel ID\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chid](index.html) module"] +pub struct CHID_SPEC; +impl crate::RegisterSpec for CHID_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [chid::R](R) reader structure"] +impl crate::Readable for CHID_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chid::W](W) writer structure"] +impl crate::Writable for CHID_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHID to value 0"] +impl crate::Resettable for CHID_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/dmac/chintenclr.rs b/pac/atsamc21j/src/dmac/chintenclr.rs new file mode 100644 index 000000000000..5ae3096f9ab8 --- /dev/null +++ b/pac/atsamc21j/src/dmac/chintenclr.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CHINTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHINTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TERR` reader - Channel Transfer Error Interrupt Enable"] +pub struct TERR_R(crate::FieldReader); +impl TERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TERR` writer - Channel Transfer Error Interrupt Enable"] +pub struct TERR_W<'a> { + w: &'a mut W, +} +impl<'a> TERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TCMPL` reader - Channel Transfer Complete Interrupt Enable"] +pub struct TCMPL_R(crate::FieldReader); +impl TCMPL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCMPL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCMPL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCMPL` writer - Channel Transfer Complete Interrupt Enable"] +pub struct TCMPL_W<'a> { + w: &'a mut W, +} +impl<'a> TCMPL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SUSP` reader - Channel Suspend Interrupt Enable"] +pub struct SUSP_R(crate::FieldReader); +impl SUSP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SUSP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SUSP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SUSP` writer - Channel Suspend Interrupt Enable"] +pub struct SUSP_W<'a> { + w: &'a mut W, +} +impl<'a> SUSP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Channel Transfer Error Interrupt Enable"] + #[inline(always)] + pub fn terr(&self) -> TERR_R { + TERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel Transfer Complete Interrupt Enable"] + #[inline(always)] + pub fn tcmpl(&self) -> TCMPL_R { + TCMPL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel Suspend Interrupt Enable"] + #[inline(always)] + pub fn susp(&self) -> SUSP_R { + SUSP_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel Transfer Error Interrupt Enable"] + #[inline(always)] + pub fn terr(&mut self) -> TERR_W { + TERR_W { w: self } + } + #[doc = "Bit 1 - Channel Transfer Complete Interrupt Enable"] + #[inline(always)] + pub fn tcmpl(&mut self) -> TCMPL_W { + TCMPL_W { w: self } + } + #[doc = "Bit 2 - Channel Suspend Interrupt Enable"] + #[inline(always)] + pub fn susp(&mut self) -> SUSP_W { + SUSP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chintenclr](index.html) module"] +pub struct CHINTENCLR_SPEC; +impl crate::RegisterSpec for CHINTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [chintenclr::R](R) reader structure"] +impl crate::Readable for CHINTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chintenclr::W](W) writer structure"] +impl crate::Writable for CHINTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHINTENCLR to value 0"] +impl crate::Resettable for CHINTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/dmac/chintenset.rs b/pac/atsamc21j/src/dmac/chintenset.rs new file mode 100644 index 000000000000..2e7daef20a6f --- /dev/null +++ b/pac/atsamc21j/src/dmac/chintenset.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CHINTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHINTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TERR` reader - Channel Transfer Error Interrupt Enable"] +pub struct TERR_R(crate::FieldReader); +impl TERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TERR` writer - Channel Transfer Error Interrupt Enable"] +pub struct TERR_W<'a> { + w: &'a mut W, +} +impl<'a> TERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TCMPL` reader - Channel Transfer Complete Interrupt Enable"] +pub struct TCMPL_R(crate::FieldReader); +impl TCMPL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCMPL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCMPL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCMPL` writer - Channel Transfer Complete Interrupt Enable"] +pub struct TCMPL_W<'a> { + w: &'a mut W, +} +impl<'a> TCMPL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SUSP` reader - Channel Suspend Interrupt Enable"] +pub struct SUSP_R(crate::FieldReader); +impl SUSP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SUSP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SUSP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SUSP` writer - Channel Suspend Interrupt Enable"] +pub struct SUSP_W<'a> { + w: &'a mut W, +} +impl<'a> SUSP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Channel Transfer Error Interrupt Enable"] + #[inline(always)] + pub fn terr(&self) -> TERR_R { + TERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel Transfer Complete Interrupt Enable"] + #[inline(always)] + pub fn tcmpl(&self) -> TCMPL_R { + TCMPL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel Suspend Interrupt Enable"] + #[inline(always)] + pub fn susp(&self) -> SUSP_R { + SUSP_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel Transfer Error Interrupt Enable"] + #[inline(always)] + pub fn terr(&mut self) -> TERR_W { + TERR_W { w: self } + } + #[doc = "Bit 1 - Channel Transfer Complete Interrupt Enable"] + #[inline(always)] + pub fn tcmpl(&mut self) -> TCMPL_W { + TCMPL_W { w: self } + } + #[doc = "Bit 2 - Channel Suspend Interrupt Enable"] + #[inline(always)] + pub fn susp(&mut self) -> SUSP_W { + SUSP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chintenset](index.html) module"] +pub struct CHINTENSET_SPEC; +impl crate::RegisterSpec for CHINTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [chintenset::R](R) reader structure"] +impl crate::Readable for CHINTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chintenset::W](W) writer structure"] +impl crate::Writable for CHINTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHINTENSET to value 0"] +impl crate::Resettable for CHINTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/dmac/chintflag.rs b/pac/atsamc21j/src/dmac/chintflag.rs new file mode 100644 index 000000000000..4e61d6510c30 --- /dev/null +++ b/pac/atsamc21j/src/dmac/chintflag.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CHINTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHINTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TERR` reader - Channel Transfer Error"] +pub struct TERR_R(crate::FieldReader); +impl TERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TERR` writer - Channel Transfer Error"] +pub struct TERR_W<'a> { + w: &'a mut W, +} +impl<'a> TERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TCMPL` reader - Channel Transfer Complete"] +pub struct TCMPL_R(crate::FieldReader); +impl TCMPL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCMPL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCMPL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCMPL` writer - Channel Transfer Complete"] +pub struct TCMPL_W<'a> { + w: &'a mut W, +} +impl<'a> TCMPL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SUSP` reader - Channel Suspend"] +pub struct SUSP_R(crate::FieldReader); +impl SUSP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SUSP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SUSP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SUSP` writer - Channel Suspend"] +pub struct SUSP_W<'a> { + w: &'a mut W, +} +impl<'a> SUSP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Channel Transfer Error"] + #[inline(always)] + pub fn terr(&self) -> TERR_R { + TERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel Transfer Complete"] + #[inline(always)] + pub fn tcmpl(&self) -> TCMPL_R { + TCMPL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel Suspend"] + #[inline(always)] + pub fn susp(&self) -> SUSP_R { + SUSP_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel Transfer Error"] + #[inline(always)] + pub fn terr(&mut self) -> TERR_W { + TERR_W { w: self } + } + #[doc = "Bit 1 - Channel Transfer Complete"] + #[inline(always)] + pub fn tcmpl(&mut self) -> TCMPL_W { + TCMPL_W { w: self } + } + #[doc = "Bit 2 - Channel Suspend"] + #[inline(always)] + pub fn susp(&mut self) -> SUSP_W { + SUSP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chintflag](index.html) module"] +pub struct CHINTFLAG_SPEC; +impl crate::RegisterSpec for CHINTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [chintflag::R](R) reader structure"] +impl crate::Readable for CHINTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chintflag::W](W) writer structure"] +impl crate::Writable for CHINTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHINTFLAG to value 0"] +impl crate::Resettable for CHINTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/dmac/chstatus.rs b/pac/atsamc21j/src/dmac/chstatus.rs new file mode 100644 index 000000000000..98a84345d4f7 --- /dev/null +++ b/pac/atsamc21j/src/dmac/chstatus.rs @@ -0,0 +1,93 @@ +#[doc = "Register `CHSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PEND` reader - Channel Pending"] +pub struct PEND_R(crate::FieldReader); +impl PEND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSY` reader - Channel Busy"] +pub struct BUSY_R(crate::FieldReader); +impl BUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FERR` reader - Channel Fetch Error"] +pub struct FERR_R(crate::FieldReader); +impl FERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Channel Pending"] + #[inline(always)] + pub fn pend(&self) -> PEND_R { + PEND_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel Busy"] + #[inline(always)] + pub fn busy(&self) -> BUSY_R { + BUSY_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel Fetch Error"] + #[inline(always)] + pub fn ferr(&self) -> FERR_R { + FERR_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +#[doc = "Channel Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chstatus](index.html) module"] +pub struct CHSTATUS_SPEC; +impl crate::RegisterSpec for CHSTATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [chstatus::R](R) reader structure"] +impl crate::Readable for CHSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CHSTATUS to value 0"] +impl crate::Resettable for CHSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/dmac/crcchksum.rs b/pac/atsamc21j/src/dmac/crcchksum.rs new file mode 100644 index 000000000000..89eb5b38a093 --- /dev/null +++ b/pac/atsamc21j/src/dmac/crcchksum.rs @@ -0,0 +1,103 @@ +#[doc = "Register `CRCCHKSUM` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CRCCHKSUM` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CRCCHKSUM` reader - CRC Checksum"] +pub struct CRCCHKSUM_R(crate::FieldReader); +impl CRCCHKSUM_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CRCCHKSUM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CRCCHKSUM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCCHKSUM` writer - CRC Checksum"] +pub struct CRCCHKSUM_W<'a> { + w: &'a mut W, +} +impl<'a> CRCCHKSUM_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - CRC Checksum"] + #[inline(always)] + pub fn crcchksum(&self) -> CRCCHKSUM_R { + CRCCHKSUM_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - CRC Checksum"] + #[inline(always)] + pub fn crcchksum(&mut self) -> CRCCHKSUM_W { + CRCCHKSUM_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CRC Checksum\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [crcchksum](index.html) module"] +pub struct CRCCHKSUM_SPEC; +impl crate::RegisterSpec for CRCCHKSUM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [crcchksum::R](R) reader structure"] +impl crate::Readable for CRCCHKSUM_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [crcchksum::W](W) writer structure"] +impl crate::Writable for CRCCHKSUM_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CRCCHKSUM to value 0"] +impl crate::Resettable for CRCCHKSUM_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/dmac/crcctrl.rs b/pac/atsamc21j/src/dmac/crcctrl.rs new file mode 100644 index 000000000000..b8daf7b8259d --- /dev/null +++ b/pac/atsamc21j/src/dmac/crcctrl.rs @@ -0,0 +1,337 @@ +#[doc = "Register `CRCCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CRCCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "CRC Beat Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CRCBEATSIZE_A { + #[doc = "0: 8-bit bus transfer"] + BYTE = 0, + #[doc = "1: 16-bit bus transfer"] + HWORD = 1, + #[doc = "2: 32-bit bus transfer"] + WORD = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CRCBEATSIZE_A) -> Self { + variant as _ + } +} +#[doc = "Field `CRCBEATSIZE` reader - CRC Beat Size"] +pub struct CRCBEATSIZE_R(crate::FieldReader); +impl CRCBEATSIZE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CRCBEATSIZE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CRCBEATSIZE_A::BYTE), + 1 => Some(CRCBEATSIZE_A::HWORD), + 2 => Some(CRCBEATSIZE_A::WORD), + _ => None, + } + } + #[doc = "Checks if the value of the field is `BYTE`"] + #[inline(always)] + pub fn is_byte(&self) -> bool { + **self == CRCBEATSIZE_A::BYTE + } + #[doc = "Checks if the value of the field is `HWORD`"] + #[inline(always)] + pub fn is_hword(&self) -> bool { + **self == CRCBEATSIZE_A::HWORD + } + #[doc = "Checks if the value of the field is `WORD`"] + #[inline(always)] + pub fn is_word(&self) -> bool { + **self == CRCBEATSIZE_A::WORD + } +} +impl core::ops::Deref for CRCBEATSIZE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCBEATSIZE` writer - CRC Beat Size"] +pub struct CRCBEATSIZE_W<'a> { + w: &'a mut W, +} +impl<'a> CRCBEATSIZE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CRCBEATSIZE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8-bit bus transfer"] + #[inline(always)] + pub fn byte(self) -> &'a mut W { + self.variant(CRCBEATSIZE_A::BYTE) + } + #[doc = "16-bit bus transfer"] + #[inline(always)] + pub fn hword(self) -> &'a mut W { + self.variant(CRCBEATSIZE_A::HWORD) + } + #[doc = "32-bit bus transfer"] + #[inline(always)] + pub fn word(self) -> &'a mut W { + self.variant(CRCBEATSIZE_A::WORD) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u16 & 0x03); + self.w + } +} +#[doc = "CRC Polynomial Type\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CRCPOLY_A { + #[doc = "0: CRC-16 (CRC-CCITT)"] + CRC16 = 0, + #[doc = "1: CRC32 (IEEE 802.3)"] + CRC32 = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CRCPOLY_A) -> Self { + variant as _ + } +} +#[doc = "Field `CRCPOLY` reader - CRC Polynomial Type"] +pub struct CRCPOLY_R(crate::FieldReader); +impl CRCPOLY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CRCPOLY_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CRCPOLY_A::CRC16), + 1 => Some(CRCPOLY_A::CRC32), + _ => None, + } + } + #[doc = "Checks if the value of the field is `CRC16`"] + #[inline(always)] + pub fn is_crc16(&self) -> bool { + **self == CRCPOLY_A::CRC16 + } + #[doc = "Checks if the value of the field is `CRC32`"] + #[inline(always)] + pub fn is_crc32(&self) -> bool { + **self == CRCPOLY_A::CRC32 + } +} +impl core::ops::Deref for CRCPOLY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCPOLY` writer - CRC Polynomial Type"] +pub struct CRCPOLY_W<'a> { + w: &'a mut W, +} +impl<'a> CRCPOLY_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CRCPOLY_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "CRC-16 (CRC-CCITT)"] + #[inline(always)] + pub fn crc16(self) -> &'a mut W { + self.variant(CRCPOLY_A::CRC16) + } + #[doc = "CRC32 (IEEE 802.3)"] + #[inline(always)] + pub fn crc32(self) -> &'a mut W { + self.variant(CRCPOLY_A::CRC32) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u16 & 0x03) << 2); + self.w + } +} +#[doc = "CRC Input Source\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CRCSRC_A { + #[doc = "0: No action"] + NOACT = 0, + #[doc = "1: I/O interface"] + IO = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CRCSRC_A) -> Self { + variant as _ + } +} +#[doc = "Field `CRCSRC` reader - CRC Input Source"] +pub struct CRCSRC_R(crate::FieldReader); +impl CRCSRC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CRCSRC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CRCSRC_A::NOACT), + 1 => Some(CRCSRC_A::IO), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NOACT`"] + #[inline(always)] + pub fn is_noact(&self) -> bool { + **self == CRCSRC_A::NOACT + } + #[doc = "Checks if the value of the field is `IO`"] + #[inline(always)] + pub fn is_io(&self) -> bool { + **self == CRCSRC_A::IO + } +} +impl core::ops::Deref for CRCSRC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCSRC` writer - CRC Input Source"] +pub struct CRCSRC_W<'a> { + w: &'a mut W, +} +impl<'a> CRCSRC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CRCSRC_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn noact(self) -> &'a mut W { + self.variant(CRCSRC_A::NOACT) + } + #[doc = "I/O interface"] + #[inline(always)] + pub fn io(self) -> &'a mut W { + self.variant(CRCSRC_A::IO) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 8)) | ((value as u16 & 0x3f) << 8); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - CRC Beat Size"] + #[inline(always)] + pub fn crcbeatsize(&self) -> CRCBEATSIZE_R { + CRCBEATSIZE_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bits 2:3 - CRC Polynomial Type"] + #[inline(always)] + pub fn crcpoly(&self) -> CRCPOLY_R { + CRCPOLY_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bits 8:13 - CRC Input Source"] + #[inline(always)] + pub fn crcsrc(&self) -> CRCSRC_R { + CRCSRC_R::new(((self.bits >> 8) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - CRC Beat Size"] + #[inline(always)] + pub fn crcbeatsize(&mut self) -> CRCBEATSIZE_W { + CRCBEATSIZE_W { w: self } + } + #[doc = "Bits 2:3 - CRC Polynomial Type"] + #[inline(always)] + pub fn crcpoly(&mut self) -> CRCPOLY_W { + CRCPOLY_W { w: self } + } + #[doc = "Bits 8:13 - CRC Input Source"] + #[inline(always)] + pub fn crcsrc(&mut self) -> CRCSRC_W { + CRCSRC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CRC Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [crcctrl](index.html) module"] +pub struct CRCCTRL_SPEC; +impl crate::RegisterSpec for CRCCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [crcctrl::R](R) reader structure"] +impl crate::Readable for CRCCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [crcctrl::W](W) writer structure"] +impl crate::Writable for CRCCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CRCCTRL to value 0"] +impl crate::Resettable for CRCCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/dmac/crcdatain.rs b/pac/atsamc21j/src/dmac/crcdatain.rs new file mode 100644 index 000000000000..ca0879a12136 --- /dev/null +++ b/pac/atsamc21j/src/dmac/crcdatain.rs @@ -0,0 +1,103 @@ +#[doc = "Register `CRCDATAIN` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CRCDATAIN` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CRCDATAIN` reader - CRC Data Input"] +pub struct CRCDATAIN_R(crate::FieldReader); +impl CRCDATAIN_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CRCDATAIN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CRCDATAIN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCDATAIN` writer - CRC Data Input"] +pub struct CRCDATAIN_W<'a> { + w: &'a mut W, +} +impl<'a> CRCDATAIN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - CRC Data Input"] + #[inline(always)] + pub fn crcdatain(&self) -> CRCDATAIN_R { + CRCDATAIN_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - CRC Data Input"] + #[inline(always)] + pub fn crcdatain(&mut self) -> CRCDATAIN_W { + CRCDATAIN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CRC Data Input\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [crcdatain](index.html) module"] +pub struct CRCDATAIN_SPEC; +impl crate::RegisterSpec for CRCDATAIN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [crcdatain::R](R) reader structure"] +impl crate::Readable for CRCDATAIN_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [crcdatain::W](W) writer structure"] +impl crate::Writable for CRCDATAIN_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CRCDATAIN to value 0"] +impl crate::Resettable for CRCDATAIN_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/dmac/crcstatus.rs b/pac/atsamc21j/src/dmac/crcstatus.rs new file mode 100644 index 000000000000..a132e9d5cd03 --- /dev/null +++ b/pac/atsamc21j/src/dmac/crcstatus.rs @@ -0,0 +1,160 @@ +#[doc = "Register `CRCSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CRCSTATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CRCBUSY` reader - CRC Module Busy"] +pub struct CRCBUSY_R(crate::FieldReader); +impl CRCBUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CRCBUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CRCBUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCBUSY` writer - CRC Module Busy"] +pub struct CRCBUSY_W<'a> { + w: &'a mut W, +} +impl<'a> CRCBUSY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `CRCZERO` reader - CRC Zero"] +pub struct CRCZERO_R(crate::FieldReader); +impl CRCZERO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CRCZERO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CRCZERO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCZERO` writer - CRC Zero"] +pub struct CRCZERO_W<'a> { + w: &'a mut W, +} +impl<'a> CRCZERO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - CRC Module Busy"] + #[inline(always)] + pub fn crcbusy(&self) -> CRCBUSY_R { + CRCBUSY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - CRC Zero"] + #[inline(always)] + pub fn crczero(&self) -> CRCZERO_R { + CRCZERO_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - CRC Module Busy"] + #[inline(always)] + pub fn crcbusy(&mut self) -> CRCBUSY_W { + CRCBUSY_W { w: self } + } + #[doc = "Bit 1 - CRC Zero"] + #[inline(always)] + pub fn crczero(&mut self) -> CRCZERO_W { + CRCZERO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CRC Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [crcstatus](index.html) module"] +pub struct CRCSTATUS_SPEC; +impl crate::RegisterSpec for CRCSTATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [crcstatus::R](R) reader structure"] +impl crate::Readable for CRCSTATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [crcstatus::W](W) writer structure"] +impl crate::Writable for CRCSTATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CRCSTATUS to value 0"] +impl crate::Resettable for CRCSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/dmac/ctrl.rs b/pac/atsamc21j/src/dmac/ctrl.rs new file mode 100644 index 000000000000..fabae9d82a6c --- /dev/null +++ b/pac/atsamc21j/src/dmac/ctrl.rs @@ -0,0 +1,395 @@ +#[doc = "Register `CTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `DMAENABLE` reader - DMA Enable"] +pub struct DMAENABLE_R(crate::FieldReader); +impl DMAENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DMAENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DMAENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DMAENABLE` writer - DMA Enable"] +pub struct DMAENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> DMAENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CRCENABLE` reader - CRC Enable"] +pub struct CRCENABLE_R(crate::FieldReader); +impl CRCENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CRCENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CRCENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCENABLE` writer - CRC Enable"] +pub struct CRCENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> CRCENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `LVLEN0` reader - Priority Level 0 Enable"] +pub struct LVLEN0_R(crate::FieldReader); +impl LVLEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LVLEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLEN0` writer - Priority Level 0 Enable"] +pub struct LVLEN0_W<'a> { + w: &'a mut W, +} +impl<'a> LVLEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `LVLEN1` reader - Priority Level 1 Enable"] +pub struct LVLEN1_R(crate::FieldReader); +impl LVLEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LVLEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLEN1` writer - Priority Level 1 Enable"] +pub struct LVLEN1_W<'a> { + w: &'a mut W, +} +impl<'a> LVLEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `LVLEN2` reader - Priority Level 2 Enable"] +pub struct LVLEN2_R(crate::FieldReader); +impl LVLEN2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LVLEN2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEN2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLEN2` writer - Priority Level 2 Enable"] +pub struct LVLEN2_W<'a> { + w: &'a mut W, +} +impl<'a> LVLEN2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u16 & 0x01) << 10); + self.w + } +} +#[doc = "Field `LVLEN3` reader - Priority Level 3 Enable"] +pub struct LVLEN3_R(crate::FieldReader); +impl LVLEN3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LVLEN3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEN3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLEN3` writer - Priority Level 3 Enable"] +pub struct LVLEN3_W<'a> { + w: &'a mut W, +} +impl<'a> LVLEN3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u16 & 0x01) << 11); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - DMA Enable"] + #[inline(always)] + pub fn dmaenable(&self) -> DMAENABLE_R { + DMAENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - CRC Enable"] + #[inline(always)] + pub fn crcenable(&self) -> CRCENABLE_R { + CRCENABLE_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 8 - Priority Level 0 Enable"] + #[inline(always)] + pub fn lvlen0(&self) -> LVLEN0_R { + LVLEN0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Priority Level 1 Enable"] + #[inline(always)] + pub fn lvlen1(&self) -> LVLEN1_R { + LVLEN1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Priority Level 2 Enable"] + #[inline(always)] + pub fn lvlen2(&self) -> LVLEN2_R { + LVLEN2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Priority Level 3 Enable"] + #[inline(always)] + pub fn lvlen3(&self) -> LVLEN3_R { + LVLEN3_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - DMA Enable"] + #[inline(always)] + pub fn dmaenable(&mut self) -> DMAENABLE_W { + DMAENABLE_W { w: self } + } + #[doc = "Bit 2 - CRC Enable"] + #[inline(always)] + pub fn crcenable(&mut self) -> CRCENABLE_W { + CRCENABLE_W { w: self } + } + #[doc = "Bit 8 - Priority Level 0 Enable"] + #[inline(always)] + pub fn lvlen0(&mut self) -> LVLEN0_W { + LVLEN0_W { w: self } + } + #[doc = "Bit 9 - Priority Level 1 Enable"] + #[inline(always)] + pub fn lvlen1(&mut self) -> LVLEN1_W { + LVLEN1_W { w: self } + } + #[doc = "Bit 10 - Priority Level 2 Enable"] + #[inline(always)] + pub fn lvlen2(&mut self) -> LVLEN2_W { + LVLEN2_W { w: self } + } + #[doc = "Bit 11 - Priority Level 3 Enable"] + #[inline(always)] + pub fn lvlen3(&mut self) -> LVLEN3_W { + LVLEN3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"] +pub struct CTRL_SPEC; +impl crate::RegisterSpec for CTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrl::R](R) reader structure"] +impl crate::Readable for CTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"] +impl crate::Writable for CTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/dmac/dbgctrl.rs b/pac/atsamc21j/src/dmac/dbgctrl.rs new file mode 100644 index 000000000000..53636eb2b339 --- /dev/null +++ b/pac/atsamc21j/src/dmac/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Debug Run"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Debug Run"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/dmac/intpend.rs b/pac/atsamc21j/src/dmac/intpend.rs new file mode 100644 index 000000000000..a107c4c32e66 --- /dev/null +++ b/pac/atsamc21j/src/dmac/intpend.rs @@ -0,0 +1,385 @@ +#[doc = "Register `INTPEND` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTPEND` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ID` reader - Channel ID"] +pub struct ID_R(crate::FieldReader); +impl ID_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ID_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ID_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ID` writer - Channel ID"] +pub struct ID_W<'a> { + w: &'a mut W, +} +impl<'a> ID_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u16 & 0x0f); + self.w + } +} +#[doc = "Field `TERR` reader - Transfer Error"] +pub struct TERR_R(crate::FieldReader); +impl TERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TERR` writer - Transfer Error"] +pub struct TERR_W<'a> { + w: &'a mut W, +} +impl<'a> TERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `TCMPL` reader - Transfer Complete"] +pub struct TCMPL_R(crate::FieldReader); +impl TCMPL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCMPL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCMPL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCMPL` writer - Transfer Complete"] +pub struct TCMPL_W<'a> { + w: &'a mut W, +} +impl<'a> TCMPL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `SUSP` reader - Channel Suspend"] +pub struct SUSP_R(crate::FieldReader); +impl SUSP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SUSP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SUSP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SUSP` writer - Channel Suspend"] +pub struct SUSP_W<'a> { + w: &'a mut W, +} +impl<'a> SUSP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u16 & 0x01) << 10); + self.w + } +} +#[doc = "Field `FERR` reader - Fetch Error"] +pub struct FERR_R(crate::FieldReader); +impl FERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FERR` writer - Fetch Error"] +pub struct FERR_W<'a> { + w: &'a mut W, +} +impl<'a> FERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u16 & 0x01) << 13); + self.w + } +} +#[doc = "Field `BUSY` reader - Busy"] +pub struct BUSY_R(crate::FieldReader); +impl BUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSY` writer - Busy"] +pub struct BUSY_W<'a> { + w: &'a mut W, +} +impl<'a> BUSY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u16 & 0x01) << 14); + self.w + } +} +#[doc = "Field `PEND` reader - Pending"] +pub struct PEND_R(crate::FieldReader); +impl PEND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEND` writer - Pending"] +pub struct PEND_W<'a> { + w: &'a mut W, +} +impl<'a> PEND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Channel ID"] + #[inline(always)] + pub fn id(&self) -> ID_R { + ID_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 8 - Transfer Error"] + #[inline(always)] + pub fn terr(&self) -> TERR_R { + TERR_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Transfer Complete"] + #[inline(always)] + pub fn tcmpl(&self) -> TCMPL_R { + TCMPL_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Channel Suspend"] + #[inline(always)] + pub fn susp(&self) -> SUSP_R { + SUSP_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 13 - Fetch Error"] + #[inline(always)] + pub fn ferr(&self) -> FERR_R { + FERR_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Busy"] + #[inline(always)] + pub fn busy(&self) -> BUSY_R { + BUSY_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Pending"] + #[inline(always)] + pub fn pend(&self) -> PEND_R { + PEND_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Channel ID"] + #[inline(always)] + pub fn id(&mut self) -> ID_W { + ID_W { w: self } + } + #[doc = "Bit 8 - Transfer Error"] + #[inline(always)] + pub fn terr(&mut self) -> TERR_W { + TERR_W { w: self } + } + #[doc = "Bit 9 - Transfer Complete"] + #[inline(always)] + pub fn tcmpl(&mut self) -> TCMPL_W { + TCMPL_W { w: self } + } + #[doc = "Bit 10 - Channel Suspend"] + #[inline(always)] + pub fn susp(&mut self) -> SUSP_W { + SUSP_W { w: self } + } + #[doc = "Bit 13 - Fetch Error"] + #[inline(always)] + pub fn ferr(&mut self) -> FERR_W { + FERR_W { w: self } + } + #[doc = "Bit 14 - Busy"] + #[inline(always)] + pub fn busy(&mut self) -> BUSY_W { + BUSY_W { w: self } + } + #[doc = "Bit 15 - Pending"] + #[inline(always)] + pub fn pend(&mut self) -> PEND_W { + PEND_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Pending\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intpend](index.html) module"] +pub struct INTPEND_SPEC; +impl crate::RegisterSpec for INTPEND_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intpend::R](R) reader structure"] +impl crate::Readable for INTPEND_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intpend::W](W) writer structure"] +impl crate::Writable for INTPEND_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTPEND to value 0"] +impl crate::Resettable for INTPEND_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/dmac/intstatus.rs b/pac/atsamc21j/src/dmac/intstatus.rs new file mode 100644 index 000000000000..74a836f4a2ff --- /dev/null +++ b/pac/atsamc21j/src/dmac/intstatus.rs @@ -0,0 +1,273 @@ +#[doc = "Register `INTSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `CHINT0` reader - Channel 0 Pending Interrupt"] +pub struct CHINT0_R(crate::FieldReader); +impl CHINT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT1` reader - Channel 1 Pending Interrupt"] +pub struct CHINT1_R(crate::FieldReader); +impl CHINT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT2` reader - Channel 2 Pending Interrupt"] +pub struct CHINT2_R(crate::FieldReader); +impl CHINT2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT3` reader - Channel 3 Pending Interrupt"] +pub struct CHINT3_R(crate::FieldReader); +impl CHINT3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT4` reader - Channel 4 Pending Interrupt"] +pub struct CHINT4_R(crate::FieldReader); +impl CHINT4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT5` reader - Channel 5 Pending Interrupt"] +pub struct CHINT5_R(crate::FieldReader); +impl CHINT5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT6` reader - Channel 6 Pending Interrupt"] +pub struct CHINT6_R(crate::FieldReader); +impl CHINT6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT7` reader - Channel 7 Pending Interrupt"] +pub struct CHINT7_R(crate::FieldReader); +impl CHINT7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT8` reader - Channel 8 Pending Interrupt"] +pub struct CHINT8_R(crate::FieldReader); +impl CHINT8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT9` reader - Channel 9 Pending Interrupt"] +pub struct CHINT9_R(crate::FieldReader); +impl CHINT9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT10` reader - Channel 10 Pending Interrupt"] +pub struct CHINT10_R(crate::FieldReader); +impl CHINT10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT11` reader - Channel 11 Pending Interrupt"] +pub struct CHINT11_R(crate::FieldReader); +impl CHINT11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Channel 0 Pending Interrupt"] + #[inline(always)] + pub fn chint0(&self) -> CHINT0_R { + CHINT0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel 1 Pending Interrupt"] + #[inline(always)] + pub fn chint1(&self) -> CHINT1_R { + CHINT1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel 2 Pending Interrupt"] + #[inline(always)] + pub fn chint2(&self) -> CHINT2_R { + CHINT2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Channel 3 Pending Interrupt"] + #[inline(always)] + pub fn chint3(&self) -> CHINT3_R { + CHINT3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Channel 4 Pending Interrupt"] + #[inline(always)] + pub fn chint4(&self) -> CHINT4_R { + CHINT4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Channel 5 Pending Interrupt"] + #[inline(always)] + pub fn chint5(&self) -> CHINT5_R { + CHINT5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Channel 6 Pending Interrupt"] + #[inline(always)] + pub fn chint6(&self) -> CHINT6_R { + CHINT6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Channel 7 Pending Interrupt"] + #[inline(always)] + pub fn chint7(&self) -> CHINT7_R { + CHINT7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Channel 8 Pending Interrupt"] + #[inline(always)] + pub fn chint8(&self) -> CHINT8_R { + CHINT8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Channel 9 Pending Interrupt"] + #[inline(always)] + pub fn chint9(&self) -> CHINT9_R { + CHINT9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Channel 10 Pending Interrupt"] + #[inline(always)] + pub fn chint10(&self) -> CHINT10_R { + CHINT10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Channel 11 Pending Interrupt"] + #[inline(always)] + pub fn chint11(&self) -> CHINT11_R { + CHINT11_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +#[doc = "Interrupt Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intstatus](index.html) module"] +pub struct INTSTATUS_SPEC; +impl crate::RegisterSpec for INTSTATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intstatus::R](R) reader structure"] +impl crate::Readable for INTSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets INTSTATUS to value 0"] +impl crate::Resettable for INTSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/dmac/pendch.rs b/pac/atsamc21j/src/dmac/pendch.rs new file mode 100644 index 000000000000..8bb68ff8fa5d --- /dev/null +++ b/pac/atsamc21j/src/dmac/pendch.rs @@ -0,0 +1,273 @@ +#[doc = "Register `PENDCH` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PENDCH0` reader - Pending Channel 0"] +pub struct PENDCH0_R(crate::FieldReader); +impl PENDCH0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH1` reader - Pending Channel 1"] +pub struct PENDCH1_R(crate::FieldReader); +impl PENDCH1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH2` reader - Pending Channel 2"] +pub struct PENDCH2_R(crate::FieldReader); +impl PENDCH2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH3` reader - Pending Channel 3"] +pub struct PENDCH3_R(crate::FieldReader); +impl PENDCH3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH4` reader - Pending Channel 4"] +pub struct PENDCH4_R(crate::FieldReader); +impl PENDCH4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH5` reader - Pending Channel 5"] +pub struct PENDCH5_R(crate::FieldReader); +impl PENDCH5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH6` reader - Pending Channel 6"] +pub struct PENDCH6_R(crate::FieldReader); +impl PENDCH6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH7` reader - Pending Channel 7"] +pub struct PENDCH7_R(crate::FieldReader); +impl PENDCH7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH8` reader - Pending Channel 8"] +pub struct PENDCH8_R(crate::FieldReader); +impl PENDCH8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH9` reader - Pending Channel 9"] +pub struct PENDCH9_R(crate::FieldReader); +impl PENDCH9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH10` reader - Pending Channel 10"] +pub struct PENDCH10_R(crate::FieldReader); +impl PENDCH10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH11` reader - Pending Channel 11"] +pub struct PENDCH11_R(crate::FieldReader); +impl PENDCH11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Pending Channel 0"] + #[inline(always)] + pub fn pendch0(&self) -> PENDCH0_R { + PENDCH0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Pending Channel 1"] + #[inline(always)] + pub fn pendch1(&self) -> PENDCH1_R { + PENDCH1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Pending Channel 2"] + #[inline(always)] + pub fn pendch2(&self) -> PENDCH2_R { + PENDCH2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Pending Channel 3"] + #[inline(always)] + pub fn pendch3(&self) -> PENDCH3_R { + PENDCH3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Pending Channel 4"] + #[inline(always)] + pub fn pendch4(&self) -> PENDCH4_R { + PENDCH4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Pending Channel 5"] + #[inline(always)] + pub fn pendch5(&self) -> PENDCH5_R { + PENDCH5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Pending Channel 6"] + #[inline(always)] + pub fn pendch6(&self) -> PENDCH6_R { + PENDCH6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Pending Channel 7"] + #[inline(always)] + pub fn pendch7(&self) -> PENDCH7_R { + PENDCH7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Pending Channel 8"] + #[inline(always)] + pub fn pendch8(&self) -> PENDCH8_R { + PENDCH8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Pending Channel 9"] + #[inline(always)] + pub fn pendch9(&self) -> PENDCH9_R { + PENDCH9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Pending Channel 10"] + #[inline(always)] + pub fn pendch10(&self) -> PENDCH10_R { + PENDCH10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Pending Channel 11"] + #[inline(always)] + pub fn pendch11(&self) -> PENDCH11_R { + PENDCH11_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +#[doc = "Pending Channels\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pendch](index.html) module"] +pub struct PENDCH_SPEC; +impl crate::RegisterSpec for PENDCH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pendch::R](R) reader structure"] +impl crate::Readable for PENDCH_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PENDCH to value 0"] +impl crate::Resettable for PENDCH_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/dmac/prictrl0.rs b/pac/atsamc21j/src/dmac/prictrl0.rs new file mode 100644 index 000000000000..618e54ad23f2 --- /dev/null +++ b/pac/atsamc21j/src/dmac/prictrl0.rs @@ -0,0 +1,449 @@ +#[doc = "Register `PRICTRL0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PRICTRL0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `LVLPRI0` reader - Level 0 Channel Priority Number"] +pub struct LVLPRI0_R(crate::FieldReader); +impl LVLPRI0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LVLPRI0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLPRI0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLPRI0` writer - Level 0 Channel Priority Number"] +pub struct LVLPRI0_W<'a> { + w: &'a mut W, +} +impl<'a> LVLPRI0_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Level 0 Round-Robin Scheduling Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RRLVLEN0_A { + #[doc = "0: Static arbitration scheme for channels with level 3 priority"] + STATIC_LVL = 0, + #[doc = "1: Round-robin arbitration scheme for channels with level 3 priority"] + ROUND_ROBIN_LVL = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RRLVLEN0_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RRLVLEN0` reader - Level 0 Round-Robin Scheduling Enable"] +pub struct RRLVLEN0_R(crate::FieldReader); +impl RRLVLEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RRLVLEN0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RRLVLEN0_A { + match self.bits { + false => RRLVLEN0_A::STATIC_LVL, + true => RRLVLEN0_A::ROUND_ROBIN_LVL, + } + } + #[doc = "Checks if the value of the field is `STATIC_LVL`"] + #[inline(always)] + pub fn is_static_lvl(&self) -> bool { + **self == RRLVLEN0_A::STATIC_LVL + } + #[doc = "Checks if the value of the field is `ROUND_ROBIN_LVL`"] + #[inline(always)] + pub fn is_round_robin_lvl(&self) -> bool { + **self == RRLVLEN0_A::ROUND_ROBIN_LVL + } +} +impl core::ops::Deref for RRLVLEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RRLVLEN0` writer - Level 0 Round-Robin Scheduling Enable"] +pub struct RRLVLEN0_W<'a> { + w: &'a mut W, +} +impl<'a> RRLVLEN0_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RRLVLEN0_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Static arbitration scheme for channels with level 3 priority"] + #[inline(always)] + pub fn static_lvl(self) -> &'a mut W { + self.variant(RRLVLEN0_A::STATIC_LVL) + } + #[doc = "Round-robin arbitration scheme for channels with level 3 priority"] + #[inline(always)] + pub fn round_robin_lvl(self) -> &'a mut W { + self.variant(RRLVLEN0_A::ROUND_ROBIN_LVL) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `LVLPRI1` reader - Level 1 Channel Priority Number"] +pub struct LVLPRI1_R(crate::FieldReader); +impl LVLPRI1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LVLPRI1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLPRI1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLPRI1` writer - Level 1 Channel Priority Number"] +pub struct LVLPRI1_W<'a> { + w: &'a mut W, +} +impl<'a> LVLPRI1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 8)) | ((value as u32 & 0x0f) << 8); + self.w + } +} +#[doc = "Field `RRLVLEN1` reader - Level 1 Round-Robin Scheduling Enable"] +pub struct RRLVLEN1_R(crate::FieldReader); +impl RRLVLEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RRLVLEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RRLVLEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RRLVLEN1` writer - Level 1 Round-Robin Scheduling Enable"] +pub struct RRLVLEN1_W<'a> { + w: &'a mut W, +} +impl<'a> RRLVLEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `LVLPRI2` reader - Level 2 Channel Priority Number"] +pub struct LVLPRI2_R(crate::FieldReader); +impl LVLPRI2_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LVLPRI2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLPRI2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLPRI2` writer - Level 2 Channel Priority Number"] +pub struct LVLPRI2_W<'a> { + w: &'a mut W, +} +impl<'a> LVLPRI2_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 16)) | ((value as u32 & 0x0f) << 16); + self.w + } +} +#[doc = "Field `RRLVLEN2` reader - Level 2 Round-Robin Scheduling Enable"] +pub struct RRLVLEN2_R(crate::FieldReader); +impl RRLVLEN2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RRLVLEN2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RRLVLEN2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RRLVLEN2` writer - Level 2 Round-Robin Scheduling Enable"] +pub struct RRLVLEN2_W<'a> { + w: &'a mut W, +} +impl<'a> RRLVLEN2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `LVLPRI3` reader - Level 3 Channel Priority Number"] +pub struct LVLPRI3_R(crate::FieldReader); +impl LVLPRI3_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LVLPRI3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLPRI3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLPRI3` writer - Level 3 Channel Priority Number"] +pub struct LVLPRI3_W<'a> { + w: &'a mut W, +} +impl<'a> LVLPRI3_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Field `RRLVLEN3` reader - Level 3 Round-Robin Scheduling Enable"] +pub struct RRLVLEN3_R(crate::FieldReader); +impl RRLVLEN3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RRLVLEN3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RRLVLEN3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RRLVLEN3` writer - Level 3 Round-Robin Scheduling Enable"] +pub struct RRLVLEN3_W<'a> { + w: &'a mut W, +} +impl<'a> RRLVLEN3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Level 0 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri0(&self) -> LVLPRI0_R { + LVLPRI0_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 7 - Level 0 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen0(&self) -> RRLVLEN0_R { + RRLVLEN0_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:11 - Level 1 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri1(&self) -> LVLPRI1_R { + LVLPRI1_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 15 - Level 1 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen1(&self) -> RRLVLEN1_R { + RRLVLEN1_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:19 - Level 2 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri2(&self) -> LVLPRI2_R { + LVLPRI2_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 23 - Level 2 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen2(&self) -> RRLVLEN2_R { + RRLVLEN2_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bits 24:27 - Level 3 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri3(&self) -> LVLPRI3_R { + LVLPRI3_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 31 - Level 3 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen3(&self) -> RRLVLEN3_R { + RRLVLEN3_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Level 0 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri0(&mut self) -> LVLPRI0_W { + LVLPRI0_W { w: self } + } + #[doc = "Bit 7 - Level 0 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen0(&mut self) -> RRLVLEN0_W { + RRLVLEN0_W { w: self } + } + #[doc = "Bits 8:11 - Level 1 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri1(&mut self) -> LVLPRI1_W { + LVLPRI1_W { w: self } + } + #[doc = "Bit 15 - Level 1 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen1(&mut self) -> RRLVLEN1_W { + RRLVLEN1_W { w: self } + } + #[doc = "Bits 16:19 - Level 2 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri2(&mut self) -> LVLPRI2_W { + LVLPRI2_W { w: self } + } + #[doc = "Bit 23 - Level 2 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen2(&mut self) -> RRLVLEN2_W { + RRLVLEN2_W { w: self } + } + #[doc = "Bits 24:27 - Level 3 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri3(&mut self) -> LVLPRI3_W { + LVLPRI3_W { w: self } + } + #[doc = "Bit 31 - Level 3 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen3(&mut self) -> RRLVLEN3_W { + RRLVLEN3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Priority Control 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [prictrl0](index.html) module"] +pub struct PRICTRL0_SPEC; +impl crate::RegisterSpec for PRICTRL0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [prictrl0::R](R) reader structure"] +impl crate::Readable for PRICTRL0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [prictrl0::W](W) writer structure"] +impl crate::Writable for PRICTRL0_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PRICTRL0 to value 0"] +impl crate::Resettable for PRICTRL0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/dmac/qosctrl.rs b/pac/atsamc21j/src/dmac/qosctrl.rs new file mode 100644 index 000000000000..016fcaa221ef --- /dev/null +++ b/pac/atsamc21j/src/dmac/qosctrl.rs @@ -0,0 +1,402 @@ +#[doc = "Register `QOSCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `QOSCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Write-Back Quality of Service\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WRBQOS_A { + #[doc = "0: Background (no sensitive operation)"] + DISABLE = 0, + #[doc = "1: Sensitive Bandwidth"] + LOW = 1, + #[doc = "2: Sensitive Latency"] + MEDIUM = 2, + #[doc = "3: Critical Latency"] + HIGH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WRBQOS_A) -> Self { + variant as _ + } +} +#[doc = "Field `WRBQOS` reader - Write-Back Quality of Service"] +pub struct WRBQOS_R(crate::FieldReader); +impl WRBQOS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WRBQOS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> WRBQOS_A { + match self.bits { + 0 => WRBQOS_A::DISABLE, + 1 => WRBQOS_A::LOW, + 2 => WRBQOS_A::MEDIUM, + 3 => WRBQOS_A::HIGH, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == WRBQOS_A::DISABLE + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == WRBQOS_A::LOW + } + #[doc = "Checks if the value of the field is `MEDIUM`"] + #[inline(always)] + pub fn is_medium(&self) -> bool { + **self == WRBQOS_A::MEDIUM + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == WRBQOS_A::HIGH + } +} +impl core::ops::Deref for WRBQOS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WRBQOS` writer - Write-Back Quality of Service"] +pub struct WRBQOS_W<'a> { + w: &'a mut W, +} +impl<'a> WRBQOS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WRBQOS_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Background (no sensitive operation)"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(WRBQOS_A::DISABLE) + } + #[doc = "Sensitive Bandwidth"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(WRBQOS_A::LOW) + } + #[doc = "Sensitive Latency"] + #[inline(always)] + pub fn medium(self) -> &'a mut W { + self.variant(WRBQOS_A::MEDIUM) + } + #[doc = "Critical Latency"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(WRBQOS_A::HIGH) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u8 & 0x03); + self.w + } +} +#[doc = "Fetch Quality of Service\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FQOS_A { + #[doc = "0: Background (no sensitive operation)"] + DISABLE = 0, + #[doc = "1: Sensitive Bandwidth"] + LOW = 1, + #[doc = "2: Sensitive Latency"] + MEDIUM = 2, + #[doc = "3: Critical Latency"] + HIGH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FQOS_A) -> Self { + variant as _ + } +} +#[doc = "Field `FQOS` reader - Fetch Quality of Service"] +pub struct FQOS_R(crate::FieldReader); +impl FQOS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FQOS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FQOS_A { + match self.bits { + 0 => FQOS_A::DISABLE, + 1 => FQOS_A::LOW, + 2 => FQOS_A::MEDIUM, + 3 => FQOS_A::HIGH, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == FQOS_A::DISABLE + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == FQOS_A::LOW + } + #[doc = "Checks if the value of the field is `MEDIUM`"] + #[inline(always)] + pub fn is_medium(&self) -> bool { + **self == FQOS_A::MEDIUM + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == FQOS_A::HIGH + } +} +impl core::ops::Deref for FQOS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FQOS` writer - Fetch Quality of Service"] +pub struct FQOS_W<'a> { + w: &'a mut W, +} +impl<'a> FQOS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FQOS_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Background (no sensitive operation)"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(FQOS_A::DISABLE) + } + #[doc = "Sensitive Bandwidth"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(FQOS_A::LOW) + } + #[doc = "Sensitive Latency"] + #[inline(always)] + pub fn medium(self) -> &'a mut W { + self.variant(FQOS_A::MEDIUM) + } + #[doc = "Critical Latency"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(FQOS_A::HIGH) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u8 & 0x03) << 2); + self.w + } +} +#[doc = "Data Transfer Quality of Service\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DQOS_A { + #[doc = "0: Background (no sensitive operation)"] + DISABLE = 0, + #[doc = "1: Sensitive Bandwidth"] + LOW = 1, + #[doc = "2: Sensitive Latency"] + MEDIUM = 2, + #[doc = "3: Critical Latency"] + HIGH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DQOS_A) -> Self { + variant as _ + } +} +#[doc = "Field `DQOS` reader - Data Transfer Quality of Service"] +pub struct DQOS_R(crate::FieldReader); +impl DQOS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DQOS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DQOS_A { + match self.bits { + 0 => DQOS_A::DISABLE, + 1 => DQOS_A::LOW, + 2 => DQOS_A::MEDIUM, + 3 => DQOS_A::HIGH, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == DQOS_A::DISABLE + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == DQOS_A::LOW + } + #[doc = "Checks if the value of the field is `MEDIUM`"] + #[inline(always)] + pub fn is_medium(&self) -> bool { + **self == DQOS_A::MEDIUM + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == DQOS_A::HIGH + } +} +impl core::ops::Deref for DQOS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DQOS` writer - Data Transfer Quality of Service"] +pub struct DQOS_W<'a> { + w: &'a mut W, +} +impl<'a> DQOS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DQOS_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Background (no sensitive operation)"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(DQOS_A::DISABLE) + } + #[doc = "Sensitive Bandwidth"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(DQOS_A::LOW) + } + #[doc = "Sensitive Latency"] + #[inline(always)] + pub fn medium(self) -> &'a mut W { + self.variant(DQOS_A::MEDIUM) + } + #[doc = "Critical Latency"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(DQOS_A::HIGH) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u8 & 0x03) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Write-Back Quality of Service"] + #[inline(always)] + pub fn wrbqos(&self) -> WRBQOS_R { + WRBQOS_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bits 2:3 - Fetch Quality of Service"] + #[inline(always)] + pub fn fqos(&self) -> FQOS_R { + FQOS_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bits 4:5 - Data Transfer Quality of Service"] + #[inline(always)] + pub fn dqos(&self) -> DQOS_R { + DQOS_R::new(((self.bits >> 4) & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Write-Back Quality of Service"] + #[inline(always)] + pub fn wrbqos(&mut self) -> WRBQOS_W { + WRBQOS_W { w: self } + } + #[doc = "Bits 2:3 - Fetch Quality of Service"] + #[inline(always)] + pub fn fqos(&mut self) -> FQOS_W { + FQOS_W { w: self } + } + #[doc = "Bits 4:5 - Data Transfer Quality of Service"] + #[inline(always)] + pub fn dqos(&mut self) -> DQOS_W { + DQOS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "QOS Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [qosctrl](index.html) module"] +pub struct QOSCTRL_SPEC; +impl crate::RegisterSpec for QOSCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [qosctrl::R](R) reader structure"] +impl crate::Readable for QOSCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [qosctrl::W](W) writer structure"] +impl crate::Writable for QOSCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets QOSCTRL to value 0x2a"] +impl crate::Resettable for QOSCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x2a + } +} diff --git a/pac/atsamc21j/src/dmac/swtrigctrl.rs b/pac/atsamc21j/src/dmac/swtrigctrl.rs new file mode 100644 index 000000000000..8590fef852dc --- /dev/null +++ b/pac/atsamc21j/src/dmac/swtrigctrl.rs @@ -0,0 +1,630 @@ +#[doc = "Register `SWTRIGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SWTRIGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWTRIG0` reader - Channel 0 Software Trigger"] +pub struct SWTRIG0_R(crate::FieldReader); +impl SWTRIG0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG0` writer - Channel 0 Software Trigger"] +pub struct SWTRIG0_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `SWTRIG1` reader - Channel 1 Software Trigger"] +pub struct SWTRIG1_R(crate::FieldReader); +impl SWTRIG1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG1` writer - Channel 1 Software Trigger"] +pub struct SWTRIG1_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SWTRIG2` reader - Channel 2 Software Trigger"] +pub struct SWTRIG2_R(crate::FieldReader); +impl SWTRIG2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG2` writer - Channel 2 Software Trigger"] +pub struct SWTRIG2_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SWTRIG3` reader - Channel 3 Software Trigger"] +pub struct SWTRIG3_R(crate::FieldReader); +impl SWTRIG3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG3` writer - Channel 3 Software Trigger"] +pub struct SWTRIG3_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `SWTRIG4` reader - Channel 4 Software Trigger"] +pub struct SWTRIG4_R(crate::FieldReader); +impl SWTRIG4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG4` writer - Channel 4 Software Trigger"] +pub struct SWTRIG4_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `SWTRIG5` reader - Channel 5 Software Trigger"] +pub struct SWTRIG5_R(crate::FieldReader); +impl SWTRIG5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG5` writer - Channel 5 Software Trigger"] +pub struct SWTRIG5_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `SWTRIG6` reader - Channel 6 Software Trigger"] +pub struct SWTRIG6_R(crate::FieldReader); +impl SWTRIG6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG6` writer - Channel 6 Software Trigger"] +pub struct SWTRIG6_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `SWTRIG7` reader - Channel 7 Software Trigger"] +pub struct SWTRIG7_R(crate::FieldReader); +impl SWTRIG7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG7` writer - Channel 7 Software Trigger"] +pub struct SWTRIG7_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `SWTRIG8` reader - Channel 8 Software Trigger"] +pub struct SWTRIG8_R(crate::FieldReader); +impl SWTRIG8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG8` writer - Channel 8 Software Trigger"] +pub struct SWTRIG8_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `SWTRIG9` reader - Channel 9 Software Trigger"] +pub struct SWTRIG9_R(crate::FieldReader); +impl SWTRIG9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG9` writer - Channel 9 Software Trigger"] +pub struct SWTRIG9_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `SWTRIG10` reader - Channel 10 Software Trigger"] +pub struct SWTRIG10_R(crate::FieldReader); +impl SWTRIG10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG10` writer - Channel 10 Software Trigger"] +pub struct SWTRIG10_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `SWTRIG11` reader - Channel 11 Software Trigger"] +pub struct SWTRIG11_R(crate::FieldReader); +impl SWTRIG11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG11` writer - Channel 11 Software Trigger"] +pub struct SWTRIG11_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +impl R { + #[doc = "Bit 0 - Channel 0 Software Trigger"] + #[inline(always)] + pub fn swtrig0(&self) -> SWTRIG0_R { + SWTRIG0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel 1 Software Trigger"] + #[inline(always)] + pub fn swtrig1(&self) -> SWTRIG1_R { + SWTRIG1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel 2 Software Trigger"] + #[inline(always)] + pub fn swtrig2(&self) -> SWTRIG2_R { + SWTRIG2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Channel 3 Software Trigger"] + #[inline(always)] + pub fn swtrig3(&self) -> SWTRIG3_R { + SWTRIG3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Channel 4 Software Trigger"] + #[inline(always)] + pub fn swtrig4(&self) -> SWTRIG4_R { + SWTRIG4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Channel 5 Software Trigger"] + #[inline(always)] + pub fn swtrig5(&self) -> SWTRIG5_R { + SWTRIG5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Channel 6 Software Trigger"] + #[inline(always)] + pub fn swtrig6(&self) -> SWTRIG6_R { + SWTRIG6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Channel 7 Software Trigger"] + #[inline(always)] + pub fn swtrig7(&self) -> SWTRIG7_R { + SWTRIG7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Channel 8 Software Trigger"] + #[inline(always)] + pub fn swtrig8(&self) -> SWTRIG8_R { + SWTRIG8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Channel 9 Software Trigger"] + #[inline(always)] + pub fn swtrig9(&self) -> SWTRIG9_R { + SWTRIG9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Channel 10 Software Trigger"] + #[inline(always)] + pub fn swtrig10(&self) -> SWTRIG10_R { + SWTRIG10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Channel 11 Software Trigger"] + #[inline(always)] + pub fn swtrig11(&self) -> SWTRIG11_R { + SWTRIG11_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel 0 Software Trigger"] + #[inline(always)] + pub fn swtrig0(&mut self) -> SWTRIG0_W { + SWTRIG0_W { w: self } + } + #[doc = "Bit 1 - Channel 1 Software Trigger"] + #[inline(always)] + pub fn swtrig1(&mut self) -> SWTRIG1_W { + SWTRIG1_W { w: self } + } + #[doc = "Bit 2 - Channel 2 Software Trigger"] + #[inline(always)] + pub fn swtrig2(&mut self) -> SWTRIG2_W { + SWTRIG2_W { w: self } + } + #[doc = "Bit 3 - Channel 3 Software Trigger"] + #[inline(always)] + pub fn swtrig3(&mut self) -> SWTRIG3_W { + SWTRIG3_W { w: self } + } + #[doc = "Bit 4 - Channel 4 Software Trigger"] + #[inline(always)] + pub fn swtrig4(&mut self) -> SWTRIG4_W { + SWTRIG4_W { w: self } + } + #[doc = "Bit 5 - Channel 5 Software Trigger"] + #[inline(always)] + pub fn swtrig5(&mut self) -> SWTRIG5_W { + SWTRIG5_W { w: self } + } + #[doc = "Bit 6 - Channel 6 Software Trigger"] + #[inline(always)] + pub fn swtrig6(&mut self) -> SWTRIG6_W { + SWTRIG6_W { w: self } + } + #[doc = "Bit 7 - Channel 7 Software Trigger"] + #[inline(always)] + pub fn swtrig7(&mut self) -> SWTRIG7_W { + SWTRIG7_W { w: self } + } + #[doc = "Bit 8 - Channel 8 Software Trigger"] + #[inline(always)] + pub fn swtrig8(&mut self) -> SWTRIG8_W { + SWTRIG8_W { w: self } + } + #[doc = "Bit 9 - Channel 9 Software Trigger"] + #[inline(always)] + pub fn swtrig9(&mut self) -> SWTRIG9_W { + SWTRIG9_W { w: self } + } + #[doc = "Bit 10 - Channel 10 Software Trigger"] + #[inline(always)] + pub fn swtrig10(&mut self) -> SWTRIG10_W { + SWTRIG10_W { w: self } + } + #[doc = "Bit 11 - Channel 11 Software Trigger"] + #[inline(always)] + pub fn swtrig11(&mut self) -> SWTRIG11_W { + SWTRIG11_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Software Trigger Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [swtrigctrl](index.html) module"] +pub struct SWTRIGCTRL_SPEC; +impl crate::RegisterSpec for SWTRIGCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [swtrigctrl::R](R) reader structure"] +impl crate::Readable for SWTRIGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [swtrigctrl::W](W) writer structure"] +impl crate::Writable for SWTRIGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SWTRIGCTRL to value 0"] +impl crate::Resettable for SWTRIGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/dmac/wrbaddr.rs b/pac/atsamc21j/src/dmac/wrbaddr.rs new file mode 100644 index 000000000000..ccf2a376b853 --- /dev/null +++ b/pac/atsamc21j/src/dmac/wrbaddr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `WRBADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WRBADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WRBADDR` reader - Write-Back Memory Base Address"] +pub struct WRBADDR_R(crate::FieldReader); +impl WRBADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + WRBADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WRBADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WRBADDR` writer - Write-Back Memory Base Address"] +pub struct WRBADDR_W<'a> { + w: &'a mut W, +} +impl<'a> WRBADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Write-Back Memory Base Address"] + #[inline(always)] + pub fn wrbaddr(&self) -> WRBADDR_R { + WRBADDR_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Write-Back Memory Base Address"] + #[inline(always)] + pub fn wrbaddr(&mut self) -> WRBADDR_W { + WRBADDR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Write-Back Memory Section Base Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wrbaddr](index.html) module"] +pub struct WRBADDR_SPEC; +impl crate::RegisterSpec for WRBADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [wrbaddr::R](R) reader structure"] +impl crate::Readable for WRBADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wrbaddr::W](W) writer structure"] +impl crate::Writable for WRBADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WRBADDR to value 0"] +impl crate::Resettable for WRBADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/dsu.rs b/pac/atsamc21j/src/dsu.rs new file mode 100644 index 000000000000..88324f764961 --- /dev/null +++ b/pac/atsamc21j/src/dsu.rs @@ -0,0 +1,163 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrl: crate::Reg, + #[doc = "0x01 - Status A"] + pub statusa: crate::Reg, + #[doc = "0x02 - Status B"] + pub statusb: crate::Reg, + #[doc = "0x03 - Status C"] + pub statusc: crate::Reg, + #[doc = "0x04 - Address"] + pub addr: crate::Reg, + #[doc = "0x08 - Length"] + pub length: crate::Reg, + #[doc = "0x0c - Data"] + pub data: crate::Reg, + #[doc = "0x10..0x18 - Debug Communication Channel n"] + pub dcc: [crate::Reg; 2], + #[doc = "0x18 - Device Identification"] + pub did: crate::Reg, + _reserved9: [u8; 0xd4], + #[doc = "0xf0..0xf8 - Device Configuration"] + pub dcfg: [crate::Reg; 2], + _reserved10: [u8; 0x0f08], + #[doc = "0x1000 - CoreSight ROM Table Entry 0"] + pub entry0: crate::Reg, + #[doc = "0x1004 - CoreSight ROM Table Entry 1"] + pub entry1: crate::Reg, + #[doc = "0x1008 - CoreSight ROM Table End"] + pub end: crate::Reg, + _reserved13: [u8; 0x0fc0], + #[doc = "0x1fcc - CoreSight ROM Table Memory Type"] + pub memtype: crate::Reg, + #[doc = "0x1fd0 - Peripheral Identification 4"] + pub pid4: crate::Reg, + #[doc = "0x1fd4 - Peripheral Identification 5"] + pub pid5: crate::Reg, + #[doc = "0x1fd8 - Peripheral Identification 6"] + pub pid6: crate::Reg, + #[doc = "0x1fdc - Peripheral Identification 7"] + pub pid7: crate::Reg, + #[doc = "0x1fe0 - Peripheral Identification 0"] + pub pid0: crate::Reg, + #[doc = "0x1fe4 - Peripheral Identification 1"] + pub pid1: crate::Reg, + #[doc = "0x1fe8 - Peripheral Identification 2"] + pub pid2: crate::Reg, + #[doc = "0x1fec - Peripheral Identification 3"] + pub pid3: crate::Reg, + #[doc = "0x1ff0 - Component Identification 0"] + pub cid0: crate::Reg, + #[doc = "0x1ff4 - Component Identification 1"] + pub cid1: crate::Reg, + #[doc = "0x1ff8 - Component Identification 2"] + pub cid2: crate::Reg, + #[doc = "0x1ffc - Component Identification 3"] + pub cid3: crate::Reg, +} +#[doc = "CTRL register accessor: an alias for `Reg`"] +pub type CTRL = crate::Reg; +#[doc = "Control"] +pub mod ctrl; +#[doc = "STATUSA register accessor: an alias for `Reg`"] +pub type STATUSA = crate::Reg; +#[doc = "Status A"] +pub mod statusa; +#[doc = "STATUSB register accessor: an alias for `Reg`"] +pub type STATUSB = crate::Reg; +#[doc = "Status B"] +pub mod statusb; +#[doc = "STATUSC register accessor: an alias for `Reg`"] +pub type STATUSC = crate::Reg; +#[doc = "Status C"] +pub mod statusc; +#[doc = "ADDR register accessor: an alias for `Reg`"] +pub type ADDR = crate::Reg; +#[doc = "Address"] +pub mod addr; +#[doc = "LENGTH register accessor: an alias for `Reg`"] +pub type LENGTH = crate::Reg; +#[doc = "Length"] +pub mod length; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "Data"] +pub mod data; +#[doc = "DCC register accessor: an alias for `Reg`"] +pub type DCC = crate::Reg; +#[doc = "Debug Communication Channel n"] +pub mod dcc; +#[doc = "DID register accessor: an alias for `Reg`"] +pub type DID = crate::Reg; +#[doc = "Device Identification"] +pub mod did; +#[doc = "DCFG register accessor: an alias for `Reg`"] +pub type DCFG = crate::Reg; +#[doc = "Device Configuration"] +pub mod dcfg; +#[doc = "ENTRY0 register accessor: an alias for `Reg`"] +pub type ENTRY0 = crate::Reg; +#[doc = "CoreSight ROM Table Entry 0"] +pub mod entry0; +#[doc = "ENTRY1 register accessor: an alias for `Reg`"] +pub type ENTRY1 = crate::Reg; +#[doc = "CoreSight ROM Table Entry 1"] +pub mod entry1; +#[doc = "END register accessor: an alias for `Reg`"] +pub type END = crate::Reg; +#[doc = "CoreSight ROM Table End"] +pub mod end; +#[doc = "MEMTYPE register accessor: an alias for `Reg`"] +pub type MEMTYPE = crate::Reg; +#[doc = "CoreSight ROM Table Memory Type"] +pub mod memtype; +#[doc = "PID4 register accessor: an alias for `Reg`"] +pub type PID4 = crate::Reg; +#[doc = "Peripheral Identification 4"] +pub mod pid4; +#[doc = "PID5 register accessor: an alias for `Reg`"] +pub type PID5 = crate::Reg; +#[doc = "Peripheral Identification 5"] +pub mod pid5; +#[doc = "PID6 register accessor: an alias for `Reg`"] +pub type PID6 = crate::Reg; +#[doc = "Peripheral Identification 6"] +pub mod pid6; +#[doc = "PID7 register accessor: an alias for `Reg`"] +pub type PID7 = crate::Reg; +#[doc = "Peripheral Identification 7"] +pub mod pid7; +#[doc = "PID0 register accessor: an alias for `Reg`"] +pub type PID0 = crate::Reg; +#[doc = "Peripheral Identification 0"] +pub mod pid0; +#[doc = "PID1 register accessor: an alias for `Reg`"] +pub type PID1 = crate::Reg; +#[doc = "Peripheral Identification 1"] +pub mod pid1; +#[doc = "PID2 register accessor: an alias for `Reg`"] +pub type PID2 = crate::Reg; +#[doc = "Peripheral Identification 2"] +pub mod pid2; +#[doc = "PID3 register accessor: an alias for `Reg`"] +pub type PID3 = crate::Reg; +#[doc = "Peripheral Identification 3"] +pub mod pid3; +#[doc = "CID0 register accessor: an alias for `Reg`"] +pub type CID0 = crate::Reg; +#[doc = "Component Identification 0"] +pub mod cid0; +#[doc = "CID1 register accessor: an alias for `Reg`"] +pub type CID1 = crate::Reg; +#[doc = "Component Identification 1"] +pub mod cid1; +#[doc = "CID2 register accessor: an alias for `Reg`"] +pub type CID2 = crate::Reg; +#[doc = "Component Identification 2"] +pub mod cid2; +#[doc = "CID3 register accessor: an alias for `Reg`"] +pub type CID3 = crate::Reg; +#[doc = "Component Identification 3"] +pub mod cid3; diff --git a/pac/atsamc21j/src/dsu/addr.rs b/pac/atsamc21j/src/dsu/addr.rs new file mode 100644 index 000000000000..412f874d6b15 --- /dev/null +++ b/pac/atsamc21j/src/dsu/addr.rs @@ -0,0 +1,140 @@ +#[doc = "Register `ADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `AMOD` reader - Access Mode"] +pub struct AMOD_R(crate::FieldReader); +impl AMOD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + AMOD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AMOD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AMOD` writer - Access Mode"] +pub struct AMOD_W<'a> { + w: &'a mut W, +} +impl<'a> AMOD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u32 & 0x03); + self.w + } +} +#[doc = "Field `ADDR` reader - Address"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - Address"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3fff_ffff << 2)) | ((value as u32 & 0x3fff_ffff) << 2); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Access Mode"] + #[inline(always)] + pub fn amod(&self) -> AMOD_R { + AMOD_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bits 2:31 - Address"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new(((self.bits >> 2) & 0x3fff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:1 - Access Mode"] + #[inline(always)] + pub fn amod(&mut self) -> AMOD_W { + AMOD_W { w: self } + } + #[doc = "Bits 2:31 - Address"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [addr](index.html) module"] +pub struct ADDR_SPEC; +impl crate::RegisterSpec for ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [addr::R](R) reader structure"] +impl crate::Readable for ADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [addr::W](W) writer structure"] +impl crate::Writable for ADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ADDR to value 0"] +impl crate::Resettable for ADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/dsu/cid0.rs b/pac/atsamc21j/src/dsu/cid0.rs new file mode 100644 index 000000000000..b3c2373dfc99 --- /dev/null +++ b/pac/atsamc21j/src/dsu/cid0.rs @@ -0,0 +1,53 @@ +#[doc = "Register `CID0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PREAMBLEB0` reader - Preamble Byte 0"] +pub struct PREAMBLEB0_R(crate::FieldReader); +impl PREAMBLEB0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PREAMBLEB0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PREAMBLEB0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:7 - Preamble Byte 0"] + #[inline(always)] + pub fn preambleb0(&self) -> PREAMBLEB0_R { + PREAMBLEB0_R::new((self.bits & 0xff) as u8) + } +} +#[doc = "Component Identification 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid0](index.html) module"] +pub struct CID0_SPEC; +impl crate::RegisterSpec for CID0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid0::R](R) reader structure"] +impl crate::Readable for CID0_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID0 to value 0x0d"] +impl crate::Resettable for CID0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0d + } +} diff --git a/pac/atsamc21j/src/dsu/cid1.rs b/pac/atsamc21j/src/dsu/cid1.rs new file mode 100644 index 000000000000..3628ceac64a7 --- /dev/null +++ b/pac/atsamc21j/src/dsu/cid1.rs @@ -0,0 +1,73 @@ +#[doc = "Register `CID1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PREAMBLE` reader - Preamble"] +pub struct PREAMBLE_R(crate::FieldReader); +impl PREAMBLE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PREAMBLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PREAMBLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCLASS` reader - Component Class"] +pub struct CCLASS_R(crate::FieldReader); +impl CCLASS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CCLASS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCLASS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:3 - Preamble"] + #[inline(always)] + pub fn preamble(&self) -> PREAMBLE_R { + PREAMBLE_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Component Class"] + #[inline(always)] + pub fn cclass(&self) -> CCLASS_R { + CCLASS_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +#[doc = "Component Identification 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid1](index.html) module"] +pub struct CID1_SPEC; +impl crate::RegisterSpec for CID1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid1::R](R) reader structure"] +impl crate::Readable for CID1_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID1 to value 0x10"] +impl crate::Resettable for CID1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x10 + } +} diff --git a/pac/atsamc21j/src/dsu/cid2.rs b/pac/atsamc21j/src/dsu/cid2.rs new file mode 100644 index 000000000000..714078d5c430 --- /dev/null +++ b/pac/atsamc21j/src/dsu/cid2.rs @@ -0,0 +1,53 @@ +#[doc = "Register `CID2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PREAMBLEB2` reader - Preamble Byte 2"] +pub struct PREAMBLEB2_R(crate::FieldReader); +impl PREAMBLEB2_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PREAMBLEB2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PREAMBLEB2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:7 - Preamble Byte 2"] + #[inline(always)] + pub fn preambleb2(&self) -> PREAMBLEB2_R { + PREAMBLEB2_R::new((self.bits & 0xff) as u8) + } +} +#[doc = "Component Identification 2\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid2](index.html) module"] +pub struct CID2_SPEC; +impl crate::RegisterSpec for CID2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid2::R](R) reader structure"] +impl crate::Readable for CID2_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID2 to value 0x05"] +impl crate::Resettable for CID2_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x05 + } +} diff --git a/pac/atsamc21j/src/dsu/cid3.rs b/pac/atsamc21j/src/dsu/cid3.rs new file mode 100644 index 000000000000..a345af7b5166 --- /dev/null +++ b/pac/atsamc21j/src/dsu/cid3.rs @@ -0,0 +1,53 @@ +#[doc = "Register `CID3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PREAMBLEB3` reader - Preamble Byte 3"] +pub struct PREAMBLEB3_R(crate::FieldReader); +impl PREAMBLEB3_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PREAMBLEB3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PREAMBLEB3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:7 - Preamble Byte 3"] + #[inline(always)] + pub fn preambleb3(&self) -> PREAMBLEB3_R { + PREAMBLEB3_R::new((self.bits & 0xff) as u8) + } +} +#[doc = "Component Identification 3\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid3](index.html) module"] +pub struct CID3_SPEC; +impl crate::RegisterSpec for CID3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid3::R](R) reader structure"] +impl crate::Readable for CID3_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID3 to value 0xb1"] +impl crate::Resettable for CID3_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xb1 + } +} diff --git a/pac/atsamc21j/src/dsu/ctrl.rs b/pac/atsamc21j/src/dsu/ctrl.rs new file mode 100644 index 000000000000..0a19db5a5239 --- /dev/null +++ b/pac/atsamc21j/src/dsu/ctrl.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `CRC` writer - 32-bit Cyclic Redundancy Code"] +pub struct CRC_W<'a> { + w: &'a mut W, +} +impl<'a> CRC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `MBIST` writer - Memory built-in self-test"] +pub struct MBIST_W<'a> { + w: &'a mut W, +} +impl<'a> MBIST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CE` writer - Chip-Erase"] +pub struct CE_W<'a> { + w: &'a mut W, +} +impl<'a> CE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `ARR` writer - Auxiliary Row Read"] +pub struct ARR_W<'a> { + w: &'a mut W, +} +impl<'a> ARR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +#[doc = "Field `SMSA` writer - Start Memory Stream Access"] +pub struct SMSA_W<'a> { + w: &'a mut W, +} +impl<'a> SMSA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 2 - 32-bit Cyclic Redundancy Code"] + #[inline(always)] + pub fn crc(&mut self) -> CRC_W { + CRC_W { w: self } + } + #[doc = "Bit 3 - Memory built-in self-test"] + #[inline(always)] + pub fn mbist(&mut self) -> MBIST_W { + MBIST_W { w: self } + } + #[doc = "Bit 4 - Chip-Erase"] + #[inline(always)] + pub fn ce(&mut self) -> CE_W { + CE_W { w: self } + } + #[doc = "Bit 6 - Auxiliary Row Read"] + #[inline(always)] + pub fn arr(&mut self) -> ARR_W { + ARR_W { w: self } + } + #[doc = "Bit 7 - Start Memory Stream Access"] + #[inline(always)] + pub fn smsa(&mut self) -> SMSA_W { + SMSA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"] +pub struct CTRL_SPEC; +impl crate::RegisterSpec for CTRL_SPEC { + type Ux = u8; +} +#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"] +impl crate::Writable for CTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/dsu/data.rs b/pac/atsamc21j/src/dsu/data.rs new file mode 100644 index 000000000000..193cc49a07fd --- /dev/null +++ b/pac/atsamc21j/src/dsu/data.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Data"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Data"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/dsu/dcc.rs b/pac/atsamc21j/src/dsu/dcc.rs new file mode 100644 index 000000000000..354323a499ef --- /dev/null +++ b/pac/atsamc21j/src/dsu/dcc.rs @@ -0,0 +1,104 @@ +#[doc = "Register `DCC[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DCC[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Data"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Data"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Communication Channel n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dcc](index.html) module"] +pub struct DCC_SPEC; +impl crate::RegisterSpec for DCC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dcc::R](R) reader structure"] +impl crate::Readable for DCC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dcc::W](W) writer structure"] +impl crate::Writable for DCC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DCC[%s] +to value 0"] +impl crate::Resettable for DCC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/dsu/dcfg.rs b/pac/atsamc21j/src/dsu/dcfg.rs new file mode 100644 index 000000000000..c6d61d0b496e --- /dev/null +++ b/pac/atsamc21j/src/dsu/dcfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `DCFG[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DCFG[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DCFG` reader - Device Configuration"] +pub struct DCFG_R(crate::FieldReader); +impl DCFG_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + DCFG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DCFG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DCFG` writer - Device Configuration"] +pub struct DCFG_W<'a> { + w: &'a mut W, +} +impl<'a> DCFG_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Device Configuration"] + #[inline(always)] + pub fn dcfg(&self) -> DCFG_R { + DCFG_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Device Configuration"] + #[inline(always)] + pub fn dcfg(&mut self) -> DCFG_W { + DCFG_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Device Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dcfg](index.html) module"] +pub struct DCFG_SPEC; +impl crate::RegisterSpec for DCFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dcfg::R](R) reader structure"] +impl crate::Readable for DCFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dcfg::W](W) writer structure"] +impl crate::Writable for DCFG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DCFG[%s] +to value 0"] +impl crate::Resettable for DCFG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/dsu/did.rs b/pac/atsamc21j/src/dsu/did.rs new file mode 100644 index 000000000000..07a770aad6ee --- /dev/null +++ b/pac/atsamc21j/src/dsu/did.rs @@ -0,0 +1,279 @@ +#[doc = "Register `DID` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `DEVSEL` reader - Device Select"] +pub struct DEVSEL_R(crate::FieldReader); +impl DEVSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DEVSEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DEVSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REVISION` reader - Revision Number"] +pub struct REVISION_R(crate::FieldReader); +impl REVISION_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REVISION_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REVISION_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIE` reader - Die Number"] +pub struct DIE_R(crate::FieldReader); +impl DIE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DIE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Series\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SERIES_A { + #[doc = "0: Cortex-M0+ processor, basic feature set"] + _0 = 0, + #[doc = "1: Cortex-M0+ processor, CAN"] + _1 = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SERIES_A) -> Self { + variant as _ + } +} +#[doc = "Field `SERIES` reader - Series"] +pub struct SERIES_R(crate::FieldReader); +impl SERIES_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SERIES_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SERIES_A::_0), + 1 => Some(SERIES_A::_1), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_0`"] + #[inline(always)] + pub fn is_0(&self) -> bool { + **self == SERIES_A::_0 + } + #[doc = "Checks if the value of the field is `_1`"] + #[inline(always)] + pub fn is_1(&self) -> bool { + **self == SERIES_A::_1 + } +} +impl core::ops::Deref for SERIES_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Family\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FAMILY_A { + #[doc = "0: General purpose microcontroller"] + _0 = 0, + #[doc = "1: PicoPower"] + _1 = 1, + #[doc = "2: 5V Industrial"] + _2 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FAMILY_A) -> Self { + variant as _ + } +} +#[doc = "Field `FAMILY` reader - Family"] +pub struct FAMILY_R(crate::FieldReader); +impl FAMILY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FAMILY_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(FAMILY_A::_0), + 1 => Some(FAMILY_A::_1), + 2 => Some(FAMILY_A::_2), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_0`"] + #[inline(always)] + pub fn is_0(&self) -> bool { + **self == FAMILY_A::_0 + } + #[doc = "Checks if the value of the field is `_1`"] + #[inline(always)] + pub fn is_1(&self) -> bool { + **self == FAMILY_A::_1 + } + #[doc = "Checks if the value of the field is `_2`"] + #[inline(always)] + pub fn is_2(&self) -> bool { + **self == FAMILY_A::_2 + } +} +impl core::ops::Deref for FAMILY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Processor\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PROCESSOR_A { + #[doc = "0: Cortex-M0"] + _0 = 0, + #[doc = "1: Cortex-M0+"] + _1 = 1, + #[doc = "2: Cortex-M3"] + _2 = 2, + #[doc = "3: Cortex-M4"] + _3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PROCESSOR_A) -> Self { + variant as _ + } +} +#[doc = "Field `PROCESSOR` reader - Processor"] +pub struct PROCESSOR_R(crate::FieldReader); +impl PROCESSOR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PROCESSOR_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PROCESSOR_A::_0), + 1 => Some(PROCESSOR_A::_1), + 2 => Some(PROCESSOR_A::_2), + 3 => Some(PROCESSOR_A::_3), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_0`"] + #[inline(always)] + pub fn is_0(&self) -> bool { + **self == PROCESSOR_A::_0 + } + #[doc = "Checks if the value of the field is `_1`"] + #[inline(always)] + pub fn is_1(&self) -> bool { + **self == PROCESSOR_A::_1 + } + #[doc = "Checks if the value of the field is `_2`"] + #[inline(always)] + pub fn is_2(&self) -> bool { + **self == PROCESSOR_A::_2 + } + #[doc = "Checks if the value of the field is `_3`"] + #[inline(always)] + pub fn is_3(&self) -> bool { + **self == PROCESSOR_A::_3 + } +} +impl core::ops::Deref for PROCESSOR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:7 - Device Select"] + #[inline(always)] + pub fn devsel(&self) -> DEVSEL_R { + DEVSEL_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:11 - Revision Number"] + #[inline(always)] + pub fn revision(&self) -> REVISION_R { + REVISION_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - Die Number"] + #[inline(always)] + pub fn die(&self) -> DIE_R { + DIE_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:21 - Series"] + #[inline(always)] + pub fn series(&self) -> SERIES_R { + SERIES_R::new(((self.bits >> 16) & 0x3f) as u8) + } + #[doc = "Bits 23:27 - Family"] + #[inline(always)] + pub fn family(&self) -> FAMILY_R { + FAMILY_R::new(((self.bits >> 23) & 0x1f) as u8) + } + #[doc = "Bits 28:31 - Processor"] + #[inline(always)] + pub fn processor(&self) -> PROCESSOR_R { + PROCESSOR_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +#[doc = "Device Identification\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [did](index.html) module"] +pub struct DID_SPEC; +impl crate::RegisterSpec for DID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [did::R](R) reader structure"] +impl crate::Readable for DID_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DID to value 0x1101_0500"] +impl crate::Resettable for DID_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x1101_0500 + } +} diff --git a/pac/atsamc21j/src/dsu/end.rs b/pac/atsamc21j/src/dsu/end.rs new file mode 100644 index 000000000000..cce2edea2bce --- /dev/null +++ b/pac/atsamc21j/src/dsu/end.rs @@ -0,0 +1,53 @@ +#[doc = "Register `END` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `END` reader - End Marker"] +pub struct END_R(crate::FieldReader); +impl END_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + END_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for END_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - End Marker"] + #[inline(always)] + pub fn end(&self) -> END_R { + END_R::new(self.bits as u32) + } +} +#[doc = "CoreSight ROM Table End\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [end](index.html) module"] +pub struct END_SPEC; +impl crate::RegisterSpec for END_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [end::R](R) reader structure"] +impl crate::Readable for END_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets END to value 0"] +impl crate::Resettable for END_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/dsu/entry0.rs b/pac/atsamc21j/src/dsu/entry0.rs new file mode 100644 index 000000000000..d8563990e827 --- /dev/null +++ b/pac/atsamc21j/src/dsu/entry0.rs @@ -0,0 +1,93 @@ +#[doc = "Register `ENTRY0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `EPRES` reader - Entry Present"] +pub struct EPRES_R(crate::FieldReader); +impl EPRES_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EPRES_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EPRES_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FMT` reader - Format"] +pub struct FMT_R(crate::FieldReader); +impl FMT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FMT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FMT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDOFF` reader - Address Offset"] +pub struct ADDOFF_R(crate::FieldReader); +impl ADDOFF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + ADDOFF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDOFF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Entry Present"] + #[inline(always)] + pub fn epres(&self) -> EPRES_R { + EPRES_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Format"] + #[inline(always)] + pub fn fmt(&self) -> FMT_R { + FMT_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 12:31 - Address Offset"] + #[inline(always)] + pub fn addoff(&self) -> ADDOFF_R { + ADDOFF_R::new(((self.bits >> 12) & 0x000f_ffff) as u32) + } +} +#[doc = "CoreSight ROM Table Entry 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [entry0](index.html) module"] +pub struct ENTRY0_SPEC; +impl crate::RegisterSpec for ENTRY0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [entry0::R](R) reader structure"] +impl crate::Readable for ENTRY0_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets ENTRY0 to value 0x9f0f_c002"] +impl crate::Resettable for ENTRY0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x9f0f_c002 + } +} diff --git a/pac/atsamc21j/src/dsu/entry1.rs b/pac/atsamc21j/src/dsu/entry1.rs new file mode 100644 index 000000000000..cec8fa367705 --- /dev/null +++ b/pac/atsamc21j/src/dsu/entry1.rs @@ -0,0 +1,31 @@ +#[doc = "Register `ENTRY1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "CoreSight ROM Table Entry 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [entry1](index.html) module"] +pub struct ENTRY1_SPEC; +impl crate::RegisterSpec for ENTRY1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [entry1::R](R) reader structure"] +impl crate::Readable for ENTRY1_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets ENTRY1 to value 0x5002"] +impl crate::Resettable for ENTRY1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x5002 + } +} diff --git a/pac/atsamc21j/src/dsu/length.rs b/pac/atsamc21j/src/dsu/length.rs new file mode 100644 index 000000000000..2dc771f74dfd --- /dev/null +++ b/pac/atsamc21j/src/dsu/length.rs @@ -0,0 +1,103 @@ +#[doc = "Register `LENGTH` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `LENGTH` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `LENGTH` reader - Length"] +pub struct LENGTH_R(crate::FieldReader); +impl LENGTH_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + LENGTH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LENGTH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LENGTH` writer - Length"] +pub struct LENGTH_W<'a> { + w: &'a mut W, +} +impl<'a> LENGTH_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3fff_ffff << 2)) | ((value as u32 & 0x3fff_ffff) << 2); + self.w + } +} +impl R { + #[doc = "Bits 2:31 - Length"] + #[inline(always)] + pub fn length(&self) -> LENGTH_R { + LENGTH_R::new(((self.bits >> 2) & 0x3fff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 2:31 - Length"] + #[inline(always)] + pub fn length(&mut self) -> LENGTH_W { + LENGTH_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Length\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [length](index.html) module"] +pub struct LENGTH_SPEC; +impl crate::RegisterSpec for LENGTH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [length::R](R) reader structure"] +impl crate::Readable for LENGTH_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [length::W](W) writer structure"] +impl crate::Writable for LENGTH_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets LENGTH to value 0"] +impl crate::Resettable for LENGTH_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/dsu/memtype.rs b/pac/atsamc21j/src/dsu/memtype.rs new file mode 100644 index 000000000000..3cc841e2ba78 --- /dev/null +++ b/pac/atsamc21j/src/dsu/memtype.rs @@ -0,0 +1,53 @@ +#[doc = "Register `MEMTYPE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SMEMP` reader - System Memory Present"] +pub struct SMEMP_R(crate::FieldReader); +impl SMEMP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SMEMP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SMEMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - System Memory Present"] + #[inline(always)] + pub fn smemp(&self) -> SMEMP_R { + SMEMP_R::new((self.bits & 0x01) != 0) + } +} +#[doc = "CoreSight ROM Table Memory Type\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [memtype](index.html) module"] +pub struct MEMTYPE_SPEC; +impl crate::RegisterSpec for MEMTYPE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [memtype::R](R) reader structure"] +impl crate::Readable for MEMTYPE_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets MEMTYPE to value 0"] +impl crate::Resettable for MEMTYPE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/dsu/pid0.rs b/pac/atsamc21j/src/dsu/pid0.rs new file mode 100644 index 000000000000..98028ea62838 --- /dev/null +++ b/pac/atsamc21j/src/dsu/pid0.rs @@ -0,0 +1,53 @@ +#[doc = "Register `PID0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PARTNBL` reader - Part Number Low"] +pub struct PARTNBL_R(crate::FieldReader); +impl PARTNBL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PARTNBL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PARTNBL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:7 - Part Number Low"] + #[inline(always)] + pub fn partnbl(&self) -> PARTNBL_R { + PARTNBL_R::new((self.bits & 0xff) as u8) + } +} +#[doc = "Peripheral Identification 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid0](index.html) module"] +pub struct PID0_SPEC; +impl crate::RegisterSpec for PID0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid0::R](R) reader structure"] +impl crate::Readable for PID0_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID0 to value 0xd0"] +impl crate::Resettable for PID0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xd0 + } +} diff --git a/pac/atsamc21j/src/dsu/pid1.rs b/pac/atsamc21j/src/dsu/pid1.rs new file mode 100644 index 000000000000..4f94b853507c --- /dev/null +++ b/pac/atsamc21j/src/dsu/pid1.rs @@ -0,0 +1,73 @@ +#[doc = "Register `PID1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PARTNBH` reader - Part Number High"] +pub struct PARTNBH_R(crate::FieldReader); +impl PARTNBH_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PARTNBH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PARTNBH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `JEPIDCL` reader - Low part of the JEP-106 Identity Code"] +pub struct JEPIDCL_R(crate::FieldReader); +impl JEPIDCL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + JEPIDCL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for JEPIDCL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:3 - Part Number High"] + #[inline(always)] + pub fn partnbh(&self) -> PARTNBH_R { + PARTNBH_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Low part of the JEP-106 Identity Code"] + #[inline(always)] + pub fn jepidcl(&self) -> JEPIDCL_R { + JEPIDCL_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +#[doc = "Peripheral Identification 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid1](index.html) module"] +pub struct PID1_SPEC; +impl crate::RegisterSpec for PID1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid1::R](R) reader structure"] +impl crate::Readable for PID1_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID1 to value 0xfc"] +impl crate::Resettable for PID1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xfc + } +} diff --git a/pac/atsamc21j/src/dsu/pid2.rs b/pac/atsamc21j/src/dsu/pid2.rs new file mode 100644 index 000000000000..d8f8ed10192e --- /dev/null +++ b/pac/atsamc21j/src/dsu/pid2.rs @@ -0,0 +1,93 @@ +#[doc = "Register `PID2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `JEPIDCH` reader - JEP-106 Identity Code High"] +pub struct JEPIDCH_R(crate::FieldReader); +impl JEPIDCH_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + JEPIDCH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for JEPIDCH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `JEPU` reader - JEP-106 Identity Code is used"] +pub struct JEPU_R(crate::FieldReader); +impl JEPU_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + JEPU_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for JEPU_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REVISION` reader - Revision Number"] +pub struct REVISION_R(crate::FieldReader); +impl REVISION_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REVISION_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REVISION_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:2 - JEP-106 Identity Code High"] + #[inline(always)] + pub fn jepidch(&self) -> JEPIDCH_R { + JEPIDCH_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 3 - JEP-106 Identity Code is used"] + #[inline(always)] + pub fn jepu(&self) -> JEPU_R { + JEPU_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bits 4:7 - Revision Number"] + #[inline(always)] + pub fn revision(&self) -> REVISION_R { + REVISION_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +#[doc = "Peripheral Identification 2\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid2](index.html) module"] +pub struct PID2_SPEC; +impl crate::RegisterSpec for PID2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid2::R](R) reader structure"] +impl crate::Readable for PID2_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID2 to value 0x09"] +impl crate::Resettable for PID2_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x09 + } +} diff --git a/pac/atsamc21j/src/dsu/pid3.rs b/pac/atsamc21j/src/dsu/pid3.rs new file mode 100644 index 000000000000..c0a8fb2d7f92 --- /dev/null +++ b/pac/atsamc21j/src/dsu/pid3.rs @@ -0,0 +1,73 @@ +#[doc = "Register `PID3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `CUSMOD` reader - ARM CUSMOD"] +pub struct CUSMOD_R(crate::FieldReader); +impl CUSMOD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CUSMOD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CUSMOD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REVAND` reader - Revision Number"] +pub struct REVAND_R(crate::FieldReader); +impl REVAND_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REVAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REVAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:3 - ARM CUSMOD"] + #[inline(always)] + pub fn cusmod(&self) -> CUSMOD_R { + CUSMOD_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Revision Number"] + #[inline(always)] + pub fn revand(&self) -> REVAND_R { + REVAND_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +#[doc = "Peripheral Identification 3\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid3](index.html) module"] +pub struct PID3_SPEC; +impl crate::RegisterSpec for PID3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid3::R](R) reader structure"] +impl crate::Readable for PID3_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID3 to value 0"] +impl crate::Resettable for PID3_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/dsu/pid4.rs b/pac/atsamc21j/src/dsu/pid4.rs new file mode 100644 index 000000000000..d3a1bd120f0b --- /dev/null +++ b/pac/atsamc21j/src/dsu/pid4.rs @@ -0,0 +1,73 @@ +#[doc = "Register `PID4` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `JEPCC` reader - JEP-106 Continuation Code"] +pub struct JEPCC_R(crate::FieldReader); +impl JEPCC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + JEPCC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for JEPCC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FKBC` reader - 4KB count"] +pub struct FKBC_R(crate::FieldReader); +impl FKBC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FKBC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FKBC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:3 - JEP-106 Continuation Code"] + #[inline(always)] + pub fn jepcc(&self) -> JEPCC_R { + JEPCC_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - 4KB count"] + #[inline(always)] + pub fn fkbc(&self) -> FKBC_R { + FKBC_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +#[doc = "Peripheral Identification 4\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid4](index.html) module"] +pub struct PID4_SPEC; +impl crate::RegisterSpec for PID4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid4::R](R) reader structure"] +impl crate::Readable for PID4_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID4 to value 0"] +impl crate::Resettable for PID4_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/dsu/pid5.rs b/pac/atsamc21j/src/dsu/pid5.rs new file mode 100644 index 000000000000..d343d4800b95 --- /dev/null +++ b/pac/atsamc21j/src/dsu/pid5.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID5` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 5\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid5](index.html) module"] +pub struct PID5_SPEC; +impl crate::RegisterSpec for PID5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid5::R](R) reader structure"] +impl crate::Readable for PID5_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID5 to value 0"] +impl crate::Resettable for PID5_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/dsu/pid6.rs b/pac/atsamc21j/src/dsu/pid6.rs new file mode 100644 index 000000000000..55cc2b8b5861 --- /dev/null +++ b/pac/atsamc21j/src/dsu/pid6.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID6` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 6\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid6](index.html) module"] +pub struct PID6_SPEC; +impl crate::RegisterSpec for PID6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid6::R](R) reader structure"] +impl crate::Readable for PID6_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID6 to value 0"] +impl crate::Resettable for PID6_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/dsu/pid7.rs b/pac/atsamc21j/src/dsu/pid7.rs new file mode 100644 index 000000000000..77664d4f2f95 --- /dev/null +++ b/pac/atsamc21j/src/dsu/pid7.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID7` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 7\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid7](index.html) module"] +pub struct PID7_SPEC; +impl crate::RegisterSpec for PID7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid7::R](R) reader structure"] +impl crate::Readable for PID7_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID7 to value 0"] +impl crate::Resettable for PID7_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/dsu/statusa.rs b/pac/atsamc21j/src/dsu/statusa.rs new file mode 100644 index 000000000000..c7b90a13e491 --- /dev/null +++ b/pac/atsamc21j/src/dsu/statusa.rs @@ -0,0 +1,301 @@ +#[doc = "Register `STATUSA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUSA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DONE` reader - Done"] +pub struct DONE_R(crate::FieldReader); +impl DONE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DONE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DONE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DONE` writer - Done"] +pub struct DONE_W<'a> { + w: &'a mut W, +} +impl<'a> DONE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `CRSTEXT` reader - CPU Reset Phase Extension"] +pub struct CRSTEXT_R(crate::FieldReader); +impl CRSTEXT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CRSTEXT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CRSTEXT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRSTEXT` writer - CPU Reset Phase Extension"] +pub struct CRSTEXT_W<'a> { + w: &'a mut W, +} +impl<'a> CRSTEXT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `BERR` reader - Bus Error"] +pub struct BERR_R(crate::FieldReader); +impl BERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BERR` writer - Bus Error"] +pub struct BERR_W<'a> { + w: &'a mut W, +} +impl<'a> BERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `FAIL` reader - Failure"] +pub struct FAIL_R(crate::FieldReader); +impl FAIL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAIL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAIL` writer - Failure"] +pub struct FAIL_W<'a> { + w: &'a mut W, +} +impl<'a> FAIL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PERR` reader - Protection Error"] +pub struct PERR_R(crate::FieldReader); +impl PERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERR` writer - Protection Error"] +pub struct PERR_W<'a> { + w: &'a mut W, +} +impl<'a> PERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +impl R { + #[doc = "Bit 0 - Done"] + #[inline(always)] + pub fn done(&self) -> DONE_R { + DONE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - CPU Reset Phase Extension"] + #[inline(always)] + pub fn crstext(&self) -> CRSTEXT_R { + CRSTEXT_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Bus Error"] + #[inline(always)] + pub fn berr(&self) -> BERR_R { + BERR_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Failure"] + #[inline(always)] + pub fn fail(&self) -> FAIL_R { + FAIL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Protection Error"] + #[inline(always)] + pub fn perr(&self) -> PERR_R { + PERR_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Done"] + #[inline(always)] + pub fn done(&mut self) -> DONE_W { + DONE_W { w: self } + } + #[doc = "Bit 1 - CPU Reset Phase Extension"] + #[inline(always)] + pub fn crstext(&mut self) -> CRSTEXT_W { + CRSTEXT_W { w: self } + } + #[doc = "Bit 2 - Bus Error"] + #[inline(always)] + pub fn berr(&mut self) -> BERR_W { + BERR_W { w: self } + } + #[doc = "Bit 3 - Failure"] + #[inline(always)] + pub fn fail(&mut self) -> FAIL_W { + FAIL_W { w: self } + } + #[doc = "Bit 4 - Protection Error"] + #[inline(always)] + pub fn perr(&mut self) -> PERR_W { + PERR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [statusa](index.html) module"] +pub struct STATUSA_SPEC; +impl crate::RegisterSpec for STATUSA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [statusa::R](R) reader structure"] +impl crate::Readable for STATUSA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [statusa::W](W) writer structure"] +impl crate::Writable for STATUSA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUSA to value 0"] +impl crate::Resettable for STATUSA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/dsu/statusb.rs b/pac/atsamc21j/src/dsu/statusb.rs new file mode 100644 index 000000000000..1e9374f8deae --- /dev/null +++ b/pac/atsamc21j/src/dsu/statusb.rs @@ -0,0 +1,133 @@ +#[doc = "Register `STATUSB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PROT` reader - Protected"] +pub struct PROT_R(crate::FieldReader); +impl PROT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PROT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PROT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGPRES` reader - Debugger Present"] +pub struct DBGPRES_R(crate::FieldReader); +impl DBGPRES_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGPRES_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGPRES_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DCCD0` reader - Debug Communication Channel 0 Dirty"] +pub struct DCCD0_R(crate::FieldReader); +impl DCCD0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DCCD0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DCCD0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DCCD1` reader - Debug Communication Channel 1 Dirty"] +pub struct DCCD1_R(crate::FieldReader); +impl DCCD1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DCCD1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DCCD1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HPE` reader - Hot-Plugging Enable"] +pub struct HPE_R(crate::FieldReader); +impl HPE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HPE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HPE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Protected"] + #[inline(always)] + pub fn prot(&self) -> PROT_R { + PROT_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Debugger Present"] + #[inline(always)] + pub fn dbgpres(&self) -> DBGPRES_R { + DBGPRES_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Debug Communication Channel 0 Dirty"] + #[inline(always)] + pub fn dccd0(&self) -> DCCD0_R { + DCCD0_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Debug Communication Channel 1 Dirty"] + #[inline(always)] + pub fn dccd1(&self) -> DCCD1_R { + DCCD1_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Hot-Plugging Enable"] + #[inline(always)] + pub fn hpe(&self) -> HPE_R { + HPE_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +#[doc = "Status B\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [statusb](index.html) module"] +pub struct STATUSB_SPEC; +impl crate::RegisterSpec for STATUSB_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [statusb::R](R) reader structure"] +impl crate::Readable for STATUSB_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUSB to value 0"] +impl crate::Resettable for STATUSB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/dsu/statusc.rs b/pac/atsamc21j/src/dsu/statusc.rs new file mode 100644 index 000000000000..14b3f7b1c7e3 --- /dev/null +++ b/pac/atsamc21j/src/dsu/statusc.rs @@ -0,0 +1,53 @@ +#[doc = "Register `STATUSC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `STATE` reader - State"] +pub struct STATE_R(crate::FieldReader); +impl STATE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + STATE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STATE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:2 - State"] + #[inline(always)] + pub fn state(&self) -> STATE_R { + STATE_R::new((self.bits & 0x07) as u8) + } +} +#[doc = "Status C\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [statusc](index.html) module"] +pub struct STATUSC_SPEC; +impl crate::RegisterSpec for STATUSC_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [statusc::R](R) reader structure"] +impl crate::Readable for STATUSC_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUSC to value 0"] +impl crate::Resettable for STATUSC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/eic.rs b/pac/atsamc21j/src/eic.rs new file mode 100644 index 000000000000..606231233f4b --- /dev/null +++ b/pac/atsamc21j/src/eic.rs @@ -0,0 +1,64 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrla: crate::Reg, + #[doc = "0x01 - NMI Control"] + pub nmictrl: crate::Reg, + #[doc = "0x02 - NMI Interrupt Flag"] + pub nmiflag: crate::Reg, + #[doc = "0x04 - Syncbusy register"] + pub syncbusy: crate::Reg, + #[doc = "0x08 - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x0c - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x10 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x14 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x18 - EIC Asynchronous edge Detection Enable"] + pub asynch: crate::Reg, + #[doc = "0x1c..0x24 - Configuration n"] + pub config: [crate::Reg; 2], +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control"] +pub mod ctrla; +#[doc = "NMICTRL register accessor: an alias for `Reg`"] +pub type NMICTRL = crate::Reg; +#[doc = "NMI Control"] +pub mod nmictrl; +#[doc = "NMIFLAG register accessor: an alias for `Reg`"] +pub type NMIFLAG = crate::Reg; +#[doc = "NMI Interrupt Flag"] +pub mod nmiflag; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Syncbusy register"] +pub mod syncbusy; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "ASYNCH register accessor: an alias for `Reg`"] +pub type ASYNCH = crate::Reg; +#[doc = "EIC Asynchronous edge Detection Enable"] +pub mod asynch; +#[doc = "CONFIG register accessor: an alias for `Reg`"] +pub type CONFIG = crate::Reg; +#[doc = "Configuration n"] +pub mod config; diff --git a/pac/atsamc21j/src/eic/asynch.rs b/pac/atsamc21j/src/eic/asynch.rs new file mode 100644 index 000000000000..78a9b5c5f054 --- /dev/null +++ b/pac/atsamc21j/src/eic/asynch.rs @@ -0,0 +1,152 @@ +#[doc = "Register `ASYNCH` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ASYNCH` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "EIC Asynchronous edge Detection Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u16)] +pub enum ASYNCH_A { + #[doc = "0: Edge detection is clock synchronously operated"] + SYNC = 0, + #[doc = "1: Edge detection is clock asynchronously operated"] + ASYNC = 1, +} +impl From for u16 { + #[inline(always)] + fn from(variant: ASYNCH_A) -> Self { + variant as _ + } +} +#[doc = "Field `ASYNCH` reader - EIC Asynchronous edge Detection Enable"] +pub struct ASYNCH_R(crate::FieldReader); +impl ASYNCH_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + ASYNCH_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(ASYNCH_A::SYNC), + 1 => Some(ASYNCH_A::ASYNC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `SYNC`"] + #[inline(always)] + pub fn is_sync(&self) -> bool { + **self == ASYNCH_A::SYNC + } + #[doc = "Checks if the value of the field is `ASYNC`"] + #[inline(always)] + pub fn is_async(&self) -> bool { + **self == ASYNCH_A::ASYNC + } +} +impl core::ops::Deref for ASYNCH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ASYNCH` writer - EIC Asynchronous edge Detection Enable"] +pub struct ASYNCH_W<'a> { + w: &'a mut W, +} +impl<'a> ASYNCH_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: ASYNCH_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Edge detection is clock synchronously operated"] + #[inline(always)] + pub fn sync(self) -> &'a mut W { + self.variant(ASYNCH_A::SYNC) + } + #[doc = "Edge detection is clock asynchronously operated"] + #[inline(always)] + pub fn async_(self) -> &'a mut W { + self.variant(ASYNCH_A::ASYNC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - EIC Asynchronous edge Detection Enable"] + #[inline(always)] + pub fn asynch(&self) -> ASYNCH_R { + ASYNCH_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - EIC Asynchronous edge Detection Enable"] + #[inline(always)] + pub fn asynch(&mut self) -> ASYNCH_W { + ASYNCH_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "EIC Asynchronous edge Detection Enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [asynch](index.html) module"] +pub struct ASYNCH_SPEC; +impl crate::RegisterSpec for ASYNCH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [asynch::R](R) reader structure"] +impl crate::Readable for ASYNCH_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [asynch::W](W) writer structure"] +impl crate::Writable for ASYNCH_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ASYNCH to value 0"] +impl crate::Resettable for ASYNCH_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/eic/config.rs b/pac/atsamc21j/src/eic/config.rs new file mode 100644 index 000000000000..ab2c30950417 --- /dev/null +++ b/pac/atsamc21j/src/eic/config.rs @@ -0,0 +1,1547 @@ +#[doc = "Register `CONFIG[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CONFIG[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Input Sense Configuration 0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE0_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE0_A) -> Self { + variant as _ + } +} +#[doc = "Field `SENSE0` reader - Input Sense Configuration 0"] +pub struct SENSE0_R(crate::FieldReader); +impl SENSE0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SENSE0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE0_A::NONE), + 1 => Some(SENSE0_A::RISE), + 2 => Some(SENSE0_A::FALL), + 3 => Some(SENSE0_A::BOTH), + 4 => Some(SENSE0_A::HIGH), + 5 => Some(SENSE0_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == SENSE0_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == SENSE0_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == SENSE0_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == SENSE0_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SENSE0_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SENSE0_A::LOW + } +} +impl core::ops::Deref for SENSE0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SENSE0` writer - Input Sense Configuration 0"] +pub struct SENSE0_W<'a> { + w: &'a mut W, +} +impl<'a> SENSE0_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SENSE0_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE0_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE0_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE0_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE0_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE0_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE0_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Field `FILTEN0` reader - Filter Enable 0"] +pub struct FILTEN0_R(crate::FieldReader); +impl FILTEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FILTEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTEN0` writer - Filter Enable 0"] +pub struct FILTEN0_W<'a> { + w: &'a mut W, +} +impl<'a> FILTEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Input Sense Configuration 1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE1_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE1_A) -> Self { + variant as _ + } +} +#[doc = "Field `SENSE1` reader - Input Sense Configuration 1"] +pub struct SENSE1_R(crate::FieldReader); +impl SENSE1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SENSE1_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE1_A::NONE), + 1 => Some(SENSE1_A::RISE), + 2 => Some(SENSE1_A::FALL), + 3 => Some(SENSE1_A::BOTH), + 4 => Some(SENSE1_A::HIGH), + 5 => Some(SENSE1_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == SENSE1_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == SENSE1_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == SENSE1_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == SENSE1_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SENSE1_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SENSE1_A::LOW + } +} +impl core::ops::Deref for SENSE1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SENSE1` writer - Input Sense Configuration 1"] +pub struct SENSE1_W<'a> { + w: &'a mut W, +} +impl<'a> SENSE1_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SENSE1_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE1_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE1_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE1_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE1_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE1_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE1_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 4)) | ((value as u32 & 0x07) << 4); + self.w + } +} +#[doc = "Field `FILTEN1` reader - Filter Enable 1"] +pub struct FILTEN1_R(crate::FieldReader); +impl FILTEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FILTEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTEN1` writer - Filter Enable 1"] +pub struct FILTEN1_W<'a> { + w: &'a mut W, +} +impl<'a> FILTEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Input Sense Configuration 2\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE2_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE2_A) -> Self { + variant as _ + } +} +#[doc = "Field `SENSE2` reader - Input Sense Configuration 2"] +pub struct SENSE2_R(crate::FieldReader); +impl SENSE2_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SENSE2_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE2_A::NONE), + 1 => Some(SENSE2_A::RISE), + 2 => Some(SENSE2_A::FALL), + 3 => Some(SENSE2_A::BOTH), + 4 => Some(SENSE2_A::HIGH), + 5 => Some(SENSE2_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == SENSE2_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == SENSE2_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == SENSE2_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == SENSE2_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SENSE2_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SENSE2_A::LOW + } +} +impl core::ops::Deref for SENSE2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SENSE2` writer - Input Sense Configuration 2"] +pub struct SENSE2_W<'a> { + w: &'a mut W, +} +impl<'a> SENSE2_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SENSE2_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE2_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE2_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE2_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE2_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE2_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE2_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +#[doc = "Field `FILTEN2` reader - Filter Enable 2"] +pub struct FILTEN2_R(crate::FieldReader); +impl FILTEN2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FILTEN2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTEN2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTEN2` writer - Filter Enable 2"] +pub struct FILTEN2_W<'a> { + w: &'a mut W, +} +impl<'a> FILTEN2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Input Sense Configuration 3\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE3_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE3_A) -> Self { + variant as _ + } +} +#[doc = "Field `SENSE3` reader - Input Sense Configuration 3"] +pub struct SENSE3_R(crate::FieldReader); +impl SENSE3_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SENSE3_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE3_A::NONE), + 1 => Some(SENSE3_A::RISE), + 2 => Some(SENSE3_A::FALL), + 3 => Some(SENSE3_A::BOTH), + 4 => Some(SENSE3_A::HIGH), + 5 => Some(SENSE3_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == SENSE3_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == SENSE3_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == SENSE3_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == SENSE3_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SENSE3_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SENSE3_A::LOW + } +} +impl core::ops::Deref for SENSE3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SENSE3` writer - Input Sense Configuration 3"] +pub struct SENSE3_W<'a> { + w: &'a mut W, +} +impl<'a> SENSE3_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SENSE3_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE3_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE3_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE3_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE3_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE3_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE3_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 12)) | ((value as u32 & 0x07) << 12); + self.w + } +} +#[doc = "Field `FILTEN3` reader - Filter Enable 3"] +pub struct FILTEN3_R(crate::FieldReader); +impl FILTEN3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FILTEN3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTEN3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTEN3` writer - Filter Enable 3"] +pub struct FILTEN3_W<'a> { + w: &'a mut W, +} +impl<'a> FILTEN3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Input Sense Configuration 4\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE4_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE4_A) -> Self { + variant as _ + } +} +#[doc = "Field `SENSE4` reader - Input Sense Configuration 4"] +pub struct SENSE4_R(crate::FieldReader); +impl SENSE4_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SENSE4_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE4_A::NONE), + 1 => Some(SENSE4_A::RISE), + 2 => Some(SENSE4_A::FALL), + 3 => Some(SENSE4_A::BOTH), + 4 => Some(SENSE4_A::HIGH), + 5 => Some(SENSE4_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == SENSE4_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == SENSE4_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == SENSE4_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == SENSE4_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SENSE4_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SENSE4_A::LOW + } +} +impl core::ops::Deref for SENSE4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SENSE4` writer - Input Sense Configuration 4"] +pub struct SENSE4_W<'a> { + w: &'a mut W, +} +impl<'a> SENSE4_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SENSE4_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE4_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE4_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE4_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE4_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE4_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE4_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 16)) | ((value as u32 & 0x07) << 16); + self.w + } +} +#[doc = "Field `FILTEN4` reader - Filter Enable 4"] +pub struct FILTEN4_R(crate::FieldReader); +impl FILTEN4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FILTEN4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTEN4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTEN4` writer - Filter Enable 4"] +pub struct FILTEN4_W<'a> { + w: &'a mut W, +} +impl<'a> FILTEN4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Input Sense Configuration 5\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE5_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE5_A) -> Self { + variant as _ + } +} +#[doc = "Field `SENSE5` reader - Input Sense Configuration 5"] +pub struct SENSE5_R(crate::FieldReader); +impl SENSE5_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SENSE5_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE5_A::NONE), + 1 => Some(SENSE5_A::RISE), + 2 => Some(SENSE5_A::FALL), + 3 => Some(SENSE5_A::BOTH), + 4 => Some(SENSE5_A::HIGH), + 5 => Some(SENSE5_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == SENSE5_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == SENSE5_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == SENSE5_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == SENSE5_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SENSE5_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SENSE5_A::LOW + } +} +impl core::ops::Deref for SENSE5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SENSE5` writer - Input Sense Configuration 5"] +pub struct SENSE5_W<'a> { + w: &'a mut W, +} +impl<'a> SENSE5_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SENSE5_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE5_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE5_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE5_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE5_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE5_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE5_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 20)) | ((value as u32 & 0x07) << 20); + self.w + } +} +#[doc = "Field `FILTEN5` reader - Filter Enable 5"] +pub struct FILTEN5_R(crate::FieldReader); +impl FILTEN5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FILTEN5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTEN5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTEN5` writer - Filter Enable 5"] +pub struct FILTEN5_W<'a> { + w: &'a mut W, +} +impl<'a> FILTEN5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Input Sense Configuration 6\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE6_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE6_A) -> Self { + variant as _ + } +} +#[doc = "Field `SENSE6` reader - Input Sense Configuration 6"] +pub struct SENSE6_R(crate::FieldReader); +impl SENSE6_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SENSE6_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE6_A::NONE), + 1 => Some(SENSE6_A::RISE), + 2 => Some(SENSE6_A::FALL), + 3 => Some(SENSE6_A::BOTH), + 4 => Some(SENSE6_A::HIGH), + 5 => Some(SENSE6_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == SENSE6_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == SENSE6_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == SENSE6_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == SENSE6_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SENSE6_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SENSE6_A::LOW + } +} +impl core::ops::Deref for SENSE6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SENSE6` writer - Input Sense Configuration 6"] +pub struct SENSE6_W<'a> { + w: &'a mut W, +} +impl<'a> SENSE6_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SENSE6_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE6_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE6_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE6_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE6_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE6_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE6_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 24)) | ((value as u32 & 0x07) << 24); + self.w + } +} +#[doc = "Field `FILTEN6` reader - Filter Enable 6"] +pub struct FILTEN6_R(crate::FieldReader); +impl FILTEN6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FILTEN6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTEN6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTEN6` writer - Filter Enable 6"] +pub struct FILTEN6_W<'a> { + w: &'a mut W, +} +impl<'a> FILTEN6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +#[doc = "Input Sense Configuration 7\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE7_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE7_A) -> Self { + variant as _ + } +} +#[doc = "Field `SENSE7` reader - Input Sense Configuration 7"] +pub struct SENSE7_R(crate::FieldReader); +impl SENSE7_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SENSE7_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE7_A::NONE), + 1 => Some(SENSE7_A::RISE), + 2 => Some(SENSE7_A::FALL), + 3 => Some(SENSE7_A::BOTH), + 4 => Some(SENSE7_A::HIGH), + 5 => Some(SENSE7_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == SENSE7_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == SENSE7_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == SENSE7_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == SENSE7_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SENSE7_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SENSE7_A::LOW + } +} +impl core::ops::Deref for SENSE7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SENSE7` writer - Input Sense Configuration 7"] +pub struct SENSE7_W<'a> { + w: &'a mut W, +} +impl<'a> SENSE7_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SENSE7_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE7_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE7_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE7_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE7_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE7_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE7_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 28)) | ((value as u32 & 0x07) << 28); + self.w + } +} +#[doc = "Field `FILTEN7` reader - Filter Enable 7"] +pub struct FILTEN7_R(crate::FieldReader); +impl FILTEN7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FILTEN7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTEN7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTEN7` writer - Filter Enable 7"] +pub struct FILTEN7_W<'a> { + w: &'a mut W, +} +impl<'a> FILTEN7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Input Sense Configuration 0"] + #[inline(always)] + pub fn sense0(&self) -> SENSE0_R { + SENSE0_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 3 - Filter Enable 0"] + #[inline(always)] + pub fn filten0(&self) -> FILTEN0_R { + FILTEN0_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bits 4:6 - Input Sense Configuration 1"] + #[inline(always)] + pub fn sense1(&self) -> SENSE1_R { + SENSE1_R::new(((self.bits >> 4) & 0x07) as u8) + } + #[doc = "Bit 7 - Filter Enable 1"] + #[inline(always)] + pub fn filten1(&self) -> FILTEN1_R { + FILTEN1_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Input Sense Configuration 2"] + #[inline(always)] + pub fn sense2(&self) -> SENSE2_R { + SENSE2_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 11 - Filter Enable 2"] + #[inline(always)] + pub fn filten2(&self) -> FILTEN2_R { + FILTEN2_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bits 12:14 - Input Sense Configuration 3"] + #[inline(always)] + pub fn sense3(&self) -> SENSE3_R { + SENSE3_R::new(((self.bits >> 12) & 0x07) as u8) + } + #[doc = "Bit 15 - Filter Enable 3"] + #[inline(always)] + pub fn filten3(&self) -> FILTEN3_R { + FILTEN3_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:18 - Input Sense Configuration 4"] + #[inline(always)] + pub fn sense4(&self) -> SENSE4_R { + SENSE4_R::new(((self.bits >> 16) & 0x07) as u8) + } + #[doc = "Bit 19 - Filter Enable 4"] + #[inline(always)] + pub fn filten4(&self) -> FILTEN4_R { + FILTEN4_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bits 20:22 - Input Sense Configuration 5"] + #[inline(always)] + pub fn sense5(&self) -> SENSE5_R { + SENSE5_R::new(((self.bits >> 20) & 0x07) as u8) + } + #[doc = "Bit 23 - Filter Enable 5"] + #[inline(always)] + pub fn filten5(&self) -> FILTEN5_R { + FILTEN5_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bits 24:26 - Input Sense Configuration 6"] + #[inline(always)] + pub fn sense6(&self) -> SENSE6_R { + SENSE6_R::new(((self.bits >> 24) & 0x07) as u8) + } + #[doc = "Bit 27 - Filter Enable 6"] + #[inline(always)] + pub fn filten6(&self) -> FILTEN6_R { + FILTEN6_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bits 28:30 - Input Sense Configuration 7"] + #[inline(always)] + pub fn sense7(&self) -> SENSE7_R { + SENSE7_R::new(((self.bits >> 28) & 0x07) as u8) + } + #[doc = "Bit 31 - Filter Enable 7"] + #[inline(always)] + pub fn filten7(&self) -> FILTEN7_R { + FILTEN7_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Input Sense Configuration 0"] + #[inline(always)] + pub fn sense0(&mut self) -> SENSE0_W { + SENSE0_W { w: self } + } + #[doc = "Bit 3 - Filter Enable 0"] + #[inline(always)] + pub fn filten0(&mut self) -> FILTEN0_W { + FILTEN0_W { w: self } + } + #[doc = "Bits 4:6 - Input Sense Configuration 1"] + #[inline(always)] + pub fn sense1(&mut self) -> SENSE1_W { + SENSE1_W { w: self } + } + #[doc = "Bit 7 - Filter Enable 1"] + #[inline(always)] + pub fn filten1(&mut self) -> FILTEN1_W { + FILTEN1_W { w: self } + } + #[doc = "Bits 8:10 - Input Sense Configuration 2"] + #[inline(always)] + pub fn sense2(&mut self) -> SENSE2_W { + SENSE2_W { w: self } + } + #[doc = "Bit 11 - Filter Enable 2"] + #[inline(always)] + pub fn filten2(&mut self) -> FILTEN2_W { + FILTEN2_W { w: self } + } + #[doc = "Bits 12:14 - Input Sense Configuration 3"] + #[inline(always)] + pub fn sense3(&mut self) -> SENSE3_W { + SENSE3_W { w: self } + } + #[doc = "Bit 15 - Filter Enable 3"] + #[inline(always)] + pub fn filten3(&mut self) -> FILTEN3_W { + FILTEN3_W { w: self } + } + #[doc = "Bits 16:18 - Input Sense Configuration 4"] + #[inline(always)] + pub fn sense4(&mut self) -> SENSE4_W { + SENSE4_W { w: self } + } + #[doc = "Bit 19 - Filter Enable 4"] + #[inline(always)] + pub fn filten4(&mut self) -> FILTEN4_W { + FILTEN4_W { w: self } + } + #[doc = "Bits 20:22 - Input Sense Configuration 5"] + #[inline(always)] + pub fn sense5(&mut self) -> SENSE5_W { + SENSE5_W { w: self } + } + #[doc = "Bit 23 - Filter Enable 5"] + #[inline(always)] + pub fn filten5(&mut self) -> FILTEN5_W { + FILTEN5_W { w: self } + } + #[doc = "Bits 24:26 - Input Sense Configuration 6"] + #[inline(always)] + pub fn sense6(&mut self) -> SENSE6_W { + SENSE6_W { w: self } + } + #[doc = "Bit 27 - Filter Enable 6"] + #[inline(always)] + pub fn filten6(&mut self) -> FILTEN6_W { + FILTEN6_W { w: self } + } + #[doc = "Bits 28:30 - Input Sense Configuration 7"] + #[inline(always)] + pub fn sense7(&mut self) -> SENSE7_W { + SENSE7_W { w: self } + } + #[doc = "Bit 31 - Filter Enable 7"] + #[inline(always)] + pub fn filten7(&mut self) -> FILTEN7_W { + FILTEN7_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Configuration n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [config](index.html) module"] +pub struct CONFIG_SPEC; +impl crate::RegisterSpec for CONFIG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [config::R](R) reader structure"] +impl crate::Readable for CONFIG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [config::W](W) writer structure"] +impl crate::Writable for CONFIG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CONFIG[%s] +to value 0"] +impl crate::Resettable for CONFIG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/eic/ctrla.rs b/pac/atsamc21j/src/eic/ctrla.rs new file mode 100644 index 000000000000..25e701dd3db2 --- /dev/null +++ b/pac/atsamc21j/src/eic/ctrla.rs @@ -0,0 +1,254 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Clock Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CKSEL_A { + #[doc = "0: Clocked by GCLK"] + CLK_GCLK = 0, + #[doc = "1: Clocked by ULP32K"] + CLK_ULP32K = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CKSEL_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CKSEL` reader - Clock Selection"] +pub struct CKSEL_R(crate::FieldReader); +impl CKSEL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CKSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CKSEL_A { + match self.bits { + false => CKSEL_A::CLK_GCLK, + true => CKSEL_A::CLK_ULP32K, + } + } + #[doc = "Checks if the value of the field is `CLK_GCLK`"] + #[inline(always)] + pub fn is_clk_gclk(&self) -> bool { + **self == CKSEL_A::CLK_GCLK + } + #[doc = "Checks if the value of the field is `CLK_ULP32K`"] + #[inline(always)] + pub fn is_clk_ulp32k(&self) -> bool { + **self == CKSEL_A::CLK_ULP32K + } +} +impl core::ops::Deref for CKSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CKSEL` writer - Clock Selection"] +pub struct CKSEL_W<'a> { + w: &'a mut W, +} +impl<'a> CKSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CKSEL_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Clocked by GCLK"] + #[inline(always)] + pub fn clk_gclk(self) -> &'a mut W { + self.variant(CKSEL_A::CLK_GCLK) + } + #[doc = "Clocked by ULP32K"] + #[inline(always)] + pub fn clk_ulp32k(self) -> &'a mut W { + self.variant(CKSEL_A::CLK_ULP32K) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - Clock Selection"] + #[inline(always)] + pub fn cksel(&self) -> CKSEL_R { + CKSEL_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 4 - Clock Selection"] + #[inline(always)] + pub fn cksel(&mut self) -> CKSEL_W { + CKSEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/eic/evctrl.rs b/pac/atsamc21j/src/eic/evctrl.rs new file mode 100644 index 000000000000..25adccf3558e --- /dev/null +++ b/pac/atsamc21j/src/eic/evctrl.rs @@ -0,0 +1,103 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EXTINTEO` reader - External Interrupt Event Output Enable"] +pub struct EXTINTEO_R(crate::FieldReader); +impl EXTINTEO_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + EXTINTEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINTEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINTEO` writer - External Interrupt Event Output Enable"] +pub struct EXTINTEO_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINTEO_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - External Interrupt Event Output Enable"] + #[inline(always)] + pub fn extinteo(&self) -> EXTINTEO_R { + EXTINTEO_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - External Interrupt Event Output Enable"] + #[inline(always)] + pub fn extinteo(&mut self) -> EXTINTEO_W { + EXTINTEO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/eic/intenclr.rs b/pac/atsamc21j/src/eic/intenclr.rs new file mode 100644 index 000000000000..198c3aac9eb1 --- /dev/null +++ b/pac/atsamc21j/src/eic/intenclr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EXTINT` reader - External Interrupt Disable"] +pub struct EXTINT_R(crate::FieldReader); +impl EXTINT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + EXTINT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT` writer - External Interrupt Disable"] +pub struct EXTINT_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - External Interrupt Disable"] + #[inline(always)] + pub fn extint(&self) -> EXTINT_R { + EXTINT_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - External Interrupt Disable"] + #[inline(always)] + pub fn extint(&mut self) -> EXTINT_W { + EXTINT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/eic/intenset.rs b/pac/atsamc21j/src/eic/intenset.rs new file mode 100644 index 000000000000..e2ff6729d71f --- /dev/null +++ b/pac/atsamc21j/src/eic/intenset.rs @@ -0,0 +1,103 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EXTINT` reader - External Interrupt Enable"] +pub struct EXTINT_R(crate::FieldReader); +impl EXTINT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + EXTINT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT` writer - External Interrupt Enable"] +pub struct EXTINT_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - External Interrupt Enable"] + #[inline(always)] + pub fn extint(&self) -> EXTINT_R { + EXTINT_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - External Interrupt Enable"] + #[inline(always)] + pub fn extint(&mut self) -> EXTINT_W { + EXTINT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/eic/intflag.rs b/pac/atsamc21j/src/eic/intflag.rs new file mode 100644 index 000000000000..df2f15490feb --- /dev/null +++ b/pac/atsamc21j/src/eic/intflag.rs @@ -0,0 +1,103 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EXTINT` reader - External Interrupt Flag"] +pub struct EXTINT_R(crate::FieldReader); +impl EXTINT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + EXTINT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT` writer - External Interrupt Flag"] +pub struct EXTINT_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - External Interrupt Flag"] + #[inline(always)] + pub fn extint(&self) -> EXTINT_R { + EXTINT_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - External Interrupt Flag"] + #[inline(always)] + pub fn extint(&mut self) -> EXTINT_W { + EXTINT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/eic/nmictrl.rs b/pac/atsamc21j/src/eic/nmictrl.rs new file mode 100644 index 000000000000..c9b276ea2a29 --- /dev/null +++ b/pac/atsamc21j/src/eic/nmictrl.rs @@ -0,0 +1,345 @@ +#[doc = "Register `NMICTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `NMICTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "NMI Input Sense Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum NMISENSE_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising-edge detection"] + RISE = 1, + #[doc = "2: Falling-edge detection"] + FALL = 2, + #[doc = "3: Both-edges detection"] + BOTH = 3, + #[doc = "4: High-level detection"] + HIGH = 4, + #[doc = "5: Low-level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: NMISENSE_A) -> Self { + variant as _ + } +} +#[doc = "Field `NMISENSE` reader - NMI Input Sense Configuration"] +pub struct NMISENSE_R(crate::FieldReader); +impl NMISENSE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + NMISENSE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(NMISENSE_A::NONE), + 1 => Some(NMISENSE_A::RISE), + 2 => Some(NMISENSE_A::FALL), + 3 => Some(NMISENSE_A::BOTH), + 4 => Some(NMISENSE_A::HIGH), + 5 => Some(NMISENSE_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == NMISENSE_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == NMISENSE_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == NMISENSE_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == NMISENSE_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == NMISENSE_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == NMISENSE_A::LOW + } +} +impl core::ops::Deref for NMISENSE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NMISENSE` writer - NMI Input Sense Configuration"] +pub struct NMISENSE_W<'a> { + w: &'a mut W, +} +impl<'a> NMISENSE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: NMISENSE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(NMISENSE_A::NONE) + } + #[doc = "Rising-edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(NMISENSE_A::RISE) + } + #[doc = "Falling-edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(NMISENSE_A::FALL) + } + #[doc = "Both-edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(NMISENSE_A::BOTH) + } + #[doc = "High-level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(NMISENSE_A::HIGH) + } + #[doc = "Low-level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(NMISENSE_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +#[doc = "Field `NMIFILTEN` reader - NMI Filter Enable"] +pub struct NMIFILTEN_R(crate::FieldReader); +impl NMIFILTEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NMIFILTEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NMIFILTEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NMIFILTEN` writer - NMI Filter Enable"] +pub struct NMIFILTEN_W<'a> { + w: &'a mut W, +} +impl<'a> NMIFILTEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "NMI Asynchronous edge Detection Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum NMIASYNCH_A { + #[doc = "0: Edge detection is clock synchronously operated"] + SYNC = 0, + #[doc = "1: Edge detection is clock asynchronously operated"] + ASYNC = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NMIASYNCH_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NMIASYNCH` reader - NMI Asynchronous edge Detection Enable"] +pub struct NMIASYNCH_R(crate::FieldReader); +impl NMIASYNCH_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NMIASYNCH_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> NMIASYNCH_A { + match self.bits { + false => NMIASYNCH_A::SYNC, + true => NMIASYNCH_A::ASYNC, + } + } + #[doc = "Checks if the value of the field is `SYNC`"] + #[inline(always)] + pub fn is_sync(&self) -> bool { + **self == NMIASYNCH_A::SYNC + } + #[doc = "Checks if the value of the field is `ASYNC`"] + #[inline(always)] + pub fn is_async(&self) -> bool { + **self == NMIASYNCH_A::ASYNC + } +} +impl core::ops::Deref for NMIASYNCH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NMIASYNCH` writer - NMI Asynchronous edge Detection Enable"] +pub struct NMIASYNCH_W<'a> { + w: &'a mut W, +} +impl<'a> NMIASYNCH_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: NMIASYNCH_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Edge detection is clock synchronously operated"] + #[inline(always)] + pub fn sync(self) -> &'a mut W { + self.variant(NMIASYNCH_A::SYNC) + } + #[doc = "Edge detection is clock asynchronously operated"] + #[inline(always)] + pub fn async_(self) -> &'a mut W { + self.variant(NMIASYNCH_A::ASYNC) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - NMI Input Sense Configuration"] + #[inline(always)] + pub fn nmisense(&self) -> NMISENSE_R { + NMISENSE_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 3 - NMI Filter Enable"] + #[inline(always)] + pub fn nmifilten(&self) -> NMIFILTEN_R { + NMIFILTEN_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - NMI Asynchronous edge Detection Enable"] + #[inline(always)] + pub fn nmiasynch(&self) -> NMIASYNCH_R { + NMIASYNCH_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - NMI Input Sense Configuration"] + #[inline(always)] + pub fn nmisense(&mut self) -> NMISENSE_W { + NMISENSE_W { w: self } + } + #[doc = "Bit 3 - NMI Filter Enable"] + #[inline(always)] + pub fn nmifilten(&mut self) -> NMIFILTEN_W { + NMIFILTEN_W { w: self } + } + #[doc = "Bit 4 - NMI Asynchronous edge Detection Enable"] + #[inline(always)] + pub fn nmiasynch(&mut self) -> NMIASYNCH_W { + NMIASYNCH_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "NMI Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [nmictrl](index.html) module"] +pub struct NMICTRL_SPEC; +impl crate::RegisterSpec for NMICTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [nmictrl::R](R) reader structure"] +impl crate::Readable for NMICTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [nmictrl::W](W) writer structure"] +impl crate::Writable for NMICTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets NMICTRL to value 0"] +impl crate::Resettable for NMICTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/eic/nmiflag.rs b/pac/atsamc21j/src/eic/nmiflag.rs new file mode 100644 index 000000000000..97934b501c12 --- /dev/null +++ b/pac/atsamc21j/src/eic/nmiflag.rs @@ -0,0 +1,113 @@ +#[doc = "Register `NMIFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `NMIFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `NMI` reader - NMI Interrupt Flag"] +pub struct NMI_R(crate::FieldReader); +impl NMI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NMI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NMI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NMI` writer - NMI Interrupt Flag"] +pub struct NMI_W<'a> { + w: &'a mut W, +} +impl<'a> NMI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - NMI Interrupt Flag"] + #[inline(always)] + pub fn nmi(&self) -> NMI_R { + NMI_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - NMI Interrupt Flag"] + #[inline(always)] + pub fn nmi(&mut self) -> NMI_W { + NMI_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "NMI Interrupt Flag\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [nmiflag](index.html) module"] +pub struct NMIFLAG_SPEC; +impl crate::RegisterSpec for NMIFLAG_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [nmiflag::R](R) reader structure"] +impl crate::Readable for NMIFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [nmiflag::W](W) writer structure"] +impl crate::Writable for NMIFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets NMIFLAG to value 0"] +impl crate::Resettable for NMIFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/eic/syncbusy.rs b/pac/atsamc21j/src/eic/syncbusy.rs new file mode 100644 index 000000000000..84d125d0acf1 --- /dev/null +++ b/pac/atsamc21j/src/eic/syncbusy.rs @@ -0,0 +1,73 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software reset synchronisation"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - Enable synchronisation"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software reset synchronisation"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable synchronisation"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +#[doc = "Syncbusy register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/evsys.rs b/pac/atsamc21j/src/evsys.rs new file mode 100644 index 000000000000..9e54201975f7 --- /dev/null +++ b/pac/atsamc21j/src/evsys.rs @@ -0,0 +1,54 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrla: crate::Reg, + _reserved1: [u8; 0x0b], + #[doc = "0x0c - Channel Status"] + pub chstatus: crate::Reg, + #[doc = "0x10 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x14 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x18 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x1c - Software Event"] + pub swevt: crate::Reg, + #[doc = "0x20..0x50 - Channel n"] + pub channel: [crate::Reg; 12], + _reserved7: [u8; 0x30], + #[doc = "0x80..0x13c - User Multiplexer n"] + pub user: [crate::Reg; 47], +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control"] +pub mod ctrla; +#[doc = "CHSTATUS register accessor: an alias for `Reg`"] +pub type CHSTATUS = crate::Reg; +#[doc = "Channel Status"] +pub mod chstatus; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "SWEVT register accessor: an alias for `Reg`"] +pub type SWEVT = crate::Reg; +#[doc = "Software Event"] +pub mod swevt; +#[doc = "CHANNEL register accessor: an alias for `Reg`"] +pub type CHANNEL = crate::Reg; +#[doc = "Channel n"] +pub mod channel; +#[doc = "USER register accessor: an alias for `Reg`"] +pub type USER = crate::Reg; +#[doc = "User Multiplexer n"] +pub mod user; diff --git a/pac/atsamc21j/src/evsys/channel.rs b/pac/atsamc21j/src/evsys/channel.rs new file mode 100644 index 000000000000..20e3857da922 --- /dev/null +++ b/pac/atsamc21j/src/evsys/channel.rs @@ -0,0 +1,409 @@ +#[doc = "Register `CHANNEL[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHANNEL[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVGEN` reader - Event Generator Selection"] +pub struct EVGEN_R(crate::FieldReader); +impl EVGEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVGEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVGEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVGEN` writer - Event Generator Selection"] +pub struct EVGEN_W<'a> { + w: &'a mut W, +} +impl<'a> EVGEN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x7f) | (value as u32 & 0x7f); + self.w + } +} +#[doc = "Path Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PATH_A { + #[doc = "0: Synchronous path"] + SYNCHRONOUS = 0, + #[doc = "1: Resynchronized path"] + RESYNCHRONIZED = 1, + #[doc = "2: Asynchronous path"] + ASYNCHRONOUS = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PATH_A) -> Self { + variant as _ + } +} +#[doc = "Field `PATH` reader - Path Selection"] +pub struct PATH_R(crate::FieldReader); +impl PATH_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PATH_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PATH_A::SYNCHRONOUS), + 1 => Some(PATH_A::RESYNCHRONIZED), + 2 => Some(PATH_A::ASYNCHRONOUS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `SYNCHRONOUS`"] + #[inline(always)] + pub fn is_synchronous(&self) -> bool { + **self == PATH_A::SYNCHRONOUS + } + #[doc = "Checks if the value of the field is `RESYNCHRONIZED`"] + #[inline(always)] + pub fn is_resynchronized(&self) -> bool { + **self == PATH_A::RESYNCHRONIZED + } + #[doc = "Checks if the value of the field is `ASYNCHRONOUS`"] + #[inline(always)] + pub fn is_asynchronous(&self) -> bool { + **self == PATH_A::ASYNCHRONOUS + } +} +impl core::ops::Deref for PATH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PATH` writer - Path Selection"] +pub struct PATH_W<'a> { + w: &'a mut W, +} +impl<'a> PATH_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PATH_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Synchronous path"] + #[inline(always)] + pub fn synchronous(self) -> &'a mut W { + self.variant(PATH_A::SYNCHRONOUS) + } + #[doc = "Resynchronized path"] + #[inline(always)] + pub fn resynchronized(self) -> &'a mut W { + self.variant(PATH_A::RESYNCHRONIZED) + } + #[doc = "Asynchronous path"] + #[inline(always)] + pub fn asynchronous(self) -> &'a mut W { + self.variant(PATH_A::ASYNCHRONOUS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 8)) | ((value as u32 & 0x03) << 8); + self.w + } +} +#[doc = "Edge Detection Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EDGSEL_A { + #[doc = "0: No event output when using the resynchronized or synchronous path"] + NO_EVT_OUTPUT = 0, + #[doc = "1: Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path"] + RISING_EDGE = 1, + #[doc = "2: Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path"] + FALLING_EDGE = 2, + #[doc = "3: Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path"] + BOTH_EDGES = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EDGSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `EDGSEL` reader - Edge Detection Selection"] +pub struct EDGSEL_R(crate::FieldReader); +impl EDGSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EDGSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EDGSEL_A { + match self.bits { + 0 => EDGSEL_A::NO_EVT_OUTPUT, + 1 => EDGSEL_A::RISING_EDGE, + 2 => EDGSEL_A::FALLING_EDGE, + 3 => EDGSEL_A::BOTH_EDGES, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NO_EVT_OUTPUT`"] + #[inline(always)] + pub fn is_no_evt_output(&self) -> bool { + **self == EDGSEL_A::NO_EVT_OUTPUT + } + #[doc = "Checks if the value of the field is `RISING_EDGE`"] + #[inline(always)] + pub fn is_rising_edge(&self) -> bool { + **self == EDGSEL_A::RISING_EDGE + } + #[doc = "Checks if the value of the field is `FALLING_EDGE`"] + #[inline(always)] + pub fn is_falling_edge(&self) -> bool { + **self == EDGSEL_A::FALLING_EDGE + } + #[doc = "Checks if the value of the field is `BOTH_EDGES`"] + #[inline(always)] + pub fn is_both_edges(&self) -> bool { + **self == EDGSEL_A::BOTH_EDGES + } +} +impl core::ops::Deref for EDGSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EDGSEL` writer - Edge Detection Selection"] +pub struct EDGSEL_W<'a> { + w: &'a mut W, +} +impl<'a> EDGSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EDGSEL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "No event output when using the resynchronized or synchronous path"] + #[inline(always)] + pub fn no_evt_output(self) -> &'a mut W { + self.variant(EDGSEL_A::NO_EVT_OUTPUT) + } + #[doc = "Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path"] + #[inline(always)] + pub fn rising_edge(self) -> &'a mut W { + self.variant(EDGSEL_A::RISING_EDGE) + } + #[doc = "Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path"] + #[inline(always)] + pub fn falling_edge(self) -> &'a mut W { + self.variant(EDGSEL_A::FALLING_EDGE) + } + #[doc = "Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path"] + #[inline(always)] + pub fn both_edges(self) -> &'a mut W { + self.variant(EDGSEL_A::BOTH_EDGES) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 10)) | ((value as u32 & 0x03) << 10); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - Generic Clock On Demand"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - Generic Clock On Demand"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bits 0:6 - Event Generator Selection"] + #[inline(always)] + pub fn evgen(&self) -> EVGEN_R { + EVGEN_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bits 8:9 - Path Selection"] + #[inline(always)] + pub fn path(&self) -> PATH_R { + PATH_R::new(((self.bits >> 8) & 0x03) as u8) + } + #[doc = "Bits 10:11 - Edge Detection Selection"] + #[inline(always)] + pub fn edgsel(&self) -> EDGSEL_R { + EDGSEL_R::new(((self.bits >> 10) & 0x03) as u8) + } + #[doc = "Bit 14 - Run in standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Generic Clock On Demand"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:6 - Event Generator Selection"] + #[inline(always)] + pub fn evgen(&mut self) -> EVGEN_W { + EVGEN_W { w: self } + } + #[doc = "Bits 8:9 - Path Selection"] + #[inline(always)] + pub fn path(&mut self) -> PATH_W { + PATH_W { w: self } + } + #[doc = "Bits 10:11 - Edge Detection Selection"] + #[inline(always)] + pub fn edgsel(&mut self) -> EDGSEL_W { + EDGSEL_W { w: self } + } + #[doc = "Bit 14 - Run in standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 15 - Generic Clock On Demand"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [channel](index.html) module"] +pub struct CHANNEL_SPEC; +impl crate::RegisterSpec for CHANNEL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [channel::R](R) reader structure"] +impl crate::Readable for CHANNEL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [channel::W](W) writer structure"] +impl crate::Writable for CHANNEL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHANNEL[%s] +to value 0x8000"] +impl crate::Resettable for CHANNEL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x8000 + } +} diff --git a/pac/atsamc21j/src/evsys/chstatus.rs b/pac/atsamc21j/src/evsys/chstatus.rs new file mode 100644 index 000000000000..811089dfdeb8 --- /dev/null +++ b/pac/atsamc21j/src/evsys/chstatus.rs @@ -0,0 +1,513 @@ +#[doc = "Register `CHSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `USRRDY0` reader - Channel 0 User Ready"] +pub struct USRRDY0_R(crate::FieldReader); +impl USRRDY0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY1` reader - Channel 1 User Ready"] +pub struct USRRDY1_R(crate::FieldReader); +impl USRRDY1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY2` reader - Channel 2 User Ready"] +pub struct USRRDY2_R(crate::FieldReader); +impl USRRDY2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY3` reader - Channel 3 User Ready"] +pub struct USRRDY3_R(crate::FieldReader); +impl USRRDY3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY4` reader - Channel 4 User Ready"] +pub struct USRRDY4_R(crate::FieldReader); +impl USRRDY4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY5` reader - Channel 5 User Ready"] +pub struct USRRDY5_R(crate::FieldReader); +impl USRRDY5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY6` reader - Channel 6 User Ready"] +pub struct USRRDY6_R(crate::FieldReader); +impl USRRDY6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY7` reader - Channel 7 User Ready"] +pub struct USRRDY7_R(crate::FieldReader); +impl USRRDY7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY8` reader - Channel 8 User Ready"] +pub struct USRRDY8_R(crate::FieldReader); +impl USRRDY8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY9` reader - Channel 9 User Ready"] +pub struct USRRDY9_R(crate::FieldReader); +impl USRRDY9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY10` reader - Channel 10 User Ready"] +pub struct USRRDY10_R(crate::FieldReader); +impl USRRDY10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY11` reader - Channel 11 User Ready"] +pub struct USRRDY11_R(crate::FieldReader); +impl USRRDY11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY0` reader - Channel 0 Busy"] +pub struct CHBUSY0_R(crate::FieldReader); +impl CHBUSY0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY1` reader - Channel 1 Busy"] +pub struct CHBUSY1_R(crate::FieldReader); +impl CHBUSY1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY2` reader - Channel 2 Busy"] +pub struct CHBUSY2_R(crate::FieldReader); +impl CHBUSY2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY3` reader - Channel 3 Busy"] +pub struct CHBUSY3_R(crate::FieldReader); +impl CHBUSY3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY4` reader - Channel 4 Busy"] +pub struct CHBUSY4_R(crate::FieldReader); +impl CHBUSY4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY5` reader - Channel 5 Busy"] +pub struct CHBUSY5_R(crate::FieldReader); +impl CHBUSY5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY6` reader - Channel 6 Busy"] +pub struct CHBUSY6_R(crate::FieldReader); +impl CHBUSY6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY7` reader - Channel 7 Busy"] +pub struct CHBUSY7_R(crate::FieldReader); +impl CHBUSY7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY8` reader - Channel 8 Busy"] +pub struct CHBUSY8_R(crate::FieldReader); +impl CHBUSY8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY9` reader - Channel 9 Busy"] +pub struct CHBUSY9_R(crate::FieldReader); +impl CHBUSY9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY10` reader - Channel 10 Busy"] +pub struct CHBUSY10_R(crate::FieldReader); +impl CHBUSY10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY11` reader - Channel 11 Busy"] +pub struct CHBUSY11_R(crate::FieldReader); +impl CHBUSY11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Channel 0 User Ready"] + #[inline(always)] + pub fn usrrdy0(&self) -> USRRDY0_R { + USRRDY0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel 1 User Ready"] + #[inline(always)] + pub fn usrrdy1(&self) -> USRRDY1_R { + USRRDY1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel 2 User Ready"] + #[inline(always)] + pub fn usrrdy2(&self) -> USRRDY2_R { + USRRDY2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Channel 3 User Ready"] + #[inline(always)] + pub fn usrrdy3(&self) -> USRRDY3_R { + USRRDY3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Channel 4 User Ready"] + #[inline(always)] + pub fn usrrdy4(&self) -> USRRDY4_R { + USRRDY4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Channel 5 User Ready"] + #[inline(always)] + pub fn usrrdy5(&self) -> USRRDY5_R { + USRRDY5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Channel 6 User Ready"] + #[inline(always)] + pub fn usrrdy6(&self) -> USRRDY6_R { + USRRDY6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Channel 7 User Ready"] + #[inline(always)] + pub fn usrrdy7(&self) -> USRRDY7_R { + USRRDY7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Channel 8 User Ready"] + #[inline(always)] + pub fn usrrdy8(&self) -> USRRDY8_R { + USRRDY8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Channel 9 User Ready"] + #[inline(always)] + pub fn usrrdy9(&self) -> USRRDY9_R { + USRRDY9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Channel 10 User Ready"] + #[inline(always)] + pub fn usrrdy10(&self) -> USRRDY10_R { + USRRDY10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Channel 11 User Ready"] + #[inline(always)] + pub fn usrrdy11(&self) -> USRRDY11_R { + USRRDY11_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 16 - Channel 0 Busy"] + #[inline(always)] + pub fn chbusy0(&self) -> CHBUSY0_R { + CHBUSY0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Channel 1 Busy"] + #[inline(always)] + pub fn chbusy1(&self) -> CHBUSY1_R { + CHBUSY1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Channel 2 Busy"] + #[inline(always)] + pub fn chbusy2(&self) -> CHBUSY2_R { + CHBUSY2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Channel 3 Busy"] + #[inline(always)] + pub fn chbusy3(&self) -> CHBUSY3_R { + CHBUSY3_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Channel 4 Busy"] + #[inline(always)] + pub fn chbusy4(&self) -> CHBUSY4_R { + CHBUSY4_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Channel 5 Busy"] + #[inline(always)] + pub fn chbusy5(&self) -> CHBUSY5_R { + CHBUSY5_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Channel 6 Busy"] + #[inline(always)] + pub fn chbusy6(&self) -> CHBUSY6_R { + CHBUSY6_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Channel 7 Busy"] + #[inline(always)] + pub fn chbusy7(&self) -> CHBUSY7_R { + CHBUSY7_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24 - Channel 8 Busy"] + #[inline(always)] + pub fn chbusy8(&self) -> CHBUSY8_R { + CHBUSY8_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Channel 9 Busy"] + #[inline(always)] + pub fn chbusy9(&self) -> CHBUSY9_R { + CHBUSY9_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Channel 10 Busy"] + #[inline(always)] + pub fn chbusy10(&self) -> CHBUSY10_R { + CHBUSY10_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Channel 11 Busy"] + #[inline(always)] + pub fn chbusy11(&self) -> CHBUSY11_R { + CHBUSY11_R::new(((self.bits >> 27) & 0x01) != 0) + } +} +#[doc = "Channel Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chstatus](index.html) module"] +pub struct CHSTATUS_SPEC; +impl crate::RegisterSpec for CHSTATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [chstatus::R](R) reader structure"] +impl crate::Readable for CHSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CHSTATUS to value 0"] +impl crate::Resettable for CHSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/evsys/ctrla.rs b/pac/atsamc21j/src/evsys/ctrla.rs new file mode 100644 index 000000000000..1c24704395ad --- /dev/null +++ b/pac/atsamc21j/src/evsys/ctrla.rs @@ -0,0 +1,113 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/evsys/intenclr.rs b/pac/atsamc21j/src/evsys/intenclr.rs new file mode 100644 index 000000000000..6a6a0b2b94c5 --- /dev/null +++ b/pac/atsamc21j/src/evsys/intenclr.rs @@ -0,0 +1,1194 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVR0` reader - Channel 0 Overrun Interrupt Enable"] +pub struct OVR0_R(crate::FieldReader); +impl OVR0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR0` writer - Channel 0 Overrun Interrupt Enable"] +pub struct OVR0_W<'a> { + w: &'a mut W, +} +impl<'a> OVR0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `OVR1` reader - Channel 1 Overrun Interrupt Enable"] +pub struct OVR1_R(crate::FieldReader); +impl OVR1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR1` writer - Channel 1 Overrun Interrupt Enable"] +pub struct OVR1_W<'a> { + w: &'a mut W, +} +impl<'a> OVR1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `OVR2` reader - Channel 2 Overrun Interrupt Enable"] +pub struct OVR2_R(crate::FieldReader); +impl OVR2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR2` writer - Channel 2 Overrun Interrupt Enable"] +pub struct OVR2_W<'a> { + w: &'a mut W, +} +impl<'a> OVR2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `OVR3` reader - Channel 3 Overrun Interrupt Enable"] +pub struct OVR3_R(crate::FieldReader); +impl OVR3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR3` writer - Channel 3 Overrun Interrupt Enable"] +pub struct OVR3_W<'a> { + w: &'a mut W, +} +impl<'a> OVR3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `OVR4` reader - Channel 4 Overrun Interrupt Enable"] +pub struct OVR4_R(crate::FieldReader); +impl OVR4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR4` writer - Channel 4 Overrun Interrupt Enable"] +pub struct OVR4_W<'a> { + w: &'a mut W, +} +impl<'a> OVR4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `OVR5` reader - Channel 5 Overrun Interrupt Enable"] +pub struct OVR5_R(crate::FieldReader); +impl OVR5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR5` writer - Channel 5 Overrun Interrupt Enable"] +pub struct OVR5_W<'a> { + w: &'a mut W, +} +impl<'a> OVR5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `OVR6` reader - Channel 6 Overrun Interrupt Enable"] +pub struct OVR6_R(crate::FieldReader); +impl OVR6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR6` writer - Channel 6 Overrun Interrupt Enable"] +pub struct OVR6_W<'a> { + w: &'a mut W, +} +impl<'a> OVR6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `OVR7` reader - Channel 7 Overrun Interrupt Enable"] +pub struct OVR7_R(crate::FieldReader); +impl OVR7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR7` writer - Channel 7 Overrun Interrupt Enable"] +pub struct OVR7_W<'a> { + w: &'a mut W, +} +impl<'a> OVR7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `OVR8` reader - Channel 8 Overrun Interrupt Enable"] +pub struct OVR8_R(crate::FieldReader); +impl OVR8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR8` writer - Channel 8 Overrun Interrupt Enable"] +pub struct OVR8_W<'a> { + w: &'a mut W, +} +impl<'a> OVR8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `OVR9` reader - Channel 9 Overrun Interrupt Enable"] +pub struct OVR9_R(crate::FieldReader); +impl OVR9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR9` writer - Channel 9 Overrun Interrupt Enable"] +pub struct OVR9_W<'a> { + w: &'a mut W, +} +impl<'a> OVR9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `OVR10` reader - Channel 10 Overrun Interrupt Enable"] +pub struct OVR10_R(crate::FieldReader); +impl OVR10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR10` writer - Channel 10 Overrun Interrupt Enable"] +pub struct OVR10_W<'a> { + w: &'a mut W, +} +impl<'a> OVR10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `OVR11` reader - Channel 11 Overrun Interrupt Enable"] +pub struct OVR11_R(crate::FieldReader); +impl OVR11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR11` writer - Channel 11 Overrun Interrupt Enable"] +pub struct OVR11_W<'a> { + w: &'a mut W, +} +impl<'a> OVR11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `EVD0` reader - Channel 0 Event Detection Interrupt Enable"] +pub struct EVD0_R(crate::FieldReader); +impl EVD0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD0` writer - Channel 0 Event Detection Interrupt Enable"] +pub struct EVD0_W<'a> { + w: &'a mut W, +} +impl<'a> EVD0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `EVD1` reader - Channel 1 Event Detection Interrupt Enable"] +pub struct EVD1_R(crate::FieldReader); +impl EVD1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD1` writer - Channel 1 Event Detection Interrupt Enable"] +pub struct EVD1_W<'a> { + w: &'a mut W, +} +impl<'a> EVD1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `EVD2` reader - Channel 2 Event Detection Interrupt Enable"] +pub struct EVD2_R(crate::FieldReader); +impl EVD2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD2` writer - Channel 2 Event Detection Interrupt Enable"] +pub struct EVD2_W<'a> { + w: &'a mut W, +} +impl<'a> EVD2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `EVD3` reader - Channel 3 Event Detection Interrupt Enable"] +pub struct EVD3_R(crate::FieldReader); +impl EVD3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD3` writer - Channel 3 Event Detection Interrupt Enable"] +pub struct EVD3_W<'a> { + w: &'a mut W, +} +impl<'a> EVD3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `EVD4` reader - Channel 4 Event Detection Interrupt Enable"] +pub struct EVD4_R(crate::FieldReader); +impl EVD4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD4` writer - Channel 4 Event Detection Interrupt Enable"] +pub struct EVD4_W<'a> { + w: &'a mut W, +} +impl<'a> EVD4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `EVD5` reader - Channel 5 Event Detection Interrupt Enable"] +pub struct EVD5_R(crate::FieldReader); +impl EVD5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD5` writer - Channel 5 Event Detection Interrupt Enable"] +pub struct EVD5_W<'a> { + w: &'a mut W, +} +impl<'a> EVD5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `EVD6` reader - Channel 6 Event Detection Interrupt Enable"] +pub struct EVD6_R(crate::FieldReader); +impl EVD6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD6` writer - Channel 6 Event Detection Interrupt Enable"] +pub struct EVD6_W<'a> { + w: &'a mut W, +} +impl<'a> EVD6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `EVD7` reader - Channel 7 Event Detection Interrupt Enable"] +pub struct EVD7_R(crate::FieldReader); +impl EVD7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD7` writer - Channel 7 Event Detection Interrupt Enable"] +pub struct EVD7_W<'a> { + w: &'a mut W, +} +impl<'a> EVD7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `EVD8` reader - Channel 8 Event Detection Interrupt Enable"] +pub struct EVD8_R(crate::FieldReader); +impl EVD8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD8` writer - Channel 8 Event Detection Interrupt Enable"] +pub struct EVD8_W<'a> { + w: &'a mut W, +} +impl<'a> EVD8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `EVD9` reader - Channel 9 Event Detection Interrupt Enable"] +pub struct EVD9_R(crate::FieldReader); +impl EVD9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD9` writer - Channel 9 Event Detection Interrupt Enable"] +pub struct EVD9_W<'a> { + w: &'a mut W, +} +impl<'a> EVD9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `EVD10` reader - Channel 10 Event Detection Interrupt Enable"] +pub struct EVD10_R(crate::FieldReader); +impl EVD10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD10` writer - Channel 10 Event Detection Interrupt Enable"] +pub struct EVD10_W<'a> { + w: &'a mut W, +} +impl<'a> EVD10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `EVD11` reader - Channel 11 Event Detection Interrupt Enable"] +pub struct EVD11_R(crate::FieldReader); +impl EVD11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD11` writer - Channel 11 Event Detection Interrupt Enable"] +pub struct EVD11_W<'a> { + w: &'a mut W, +} +impl<'a> EVD11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +impl R { + #[doc = "Bit 0 - Channel 0 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr0(&self) -> OVR0_R { + OVR0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel 1 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr1(&self) -> OVR1_R { + OVR1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel 2 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr2(&self) -> OVR2_R { + OVR2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Channel 3 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr3(&self) -> OVR3_R { + OVR3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Channel 4 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr4(&self) -> OVR4_R { + OVR4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Channel 5 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr5(&self) -> OVR5_R { + OVR5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Channel 6 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr6(&self) -> OVR6_R { + OVR6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Channel 7 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr7(&self) -> OVR7_R { + OVR7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Channel 8 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr8(&self) -> OVR8_R { + OVR8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Channel 9 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr9(&self) -> OVR9_R { + OVR9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Channel 10 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr10(&self) -> OVR10_R { + OVR10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Channel 11 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr11(&self) -> OVR11_R { + OVR11_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 16 - Channel 0 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd0(&self) -> EVD0_R { + EVD0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Channel 1 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd1(&self) -> EVD1_R { + EVD1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Channel 2 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd2(&self) -> EVD2_R { + EVD2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Channel 3 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd3(&self) -> EVD3_R { + EVD3_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Channel 4 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd4(&self) -> EVD4_R { + EVD4_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Channel 5 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd5(&self) -> EVD5_R { + EVD5_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Channel 6 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd6(&self) -> EVD6_R { + EVD6_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Channel 7 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd7(&self) -> EVD7_R { + EVD7_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24 - Channel 8 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd8(&self) -> EVD8_R { + EVD8_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Channel 9 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd9(&self) -> EVD9_R { + EVD9_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Channel 10 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd10(&self) -> EVD10_R { + EVD10_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Channel 11 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd11(&self) -> EVD11_R { + EVD11_R::new(((self.bits >> 27) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel 0 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr0(&mut self) -> OVR0_W { + OVR0_W { w: self } + } + #[doc = "Bit 1 - Channel 1 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr1(&mut self) -> OVR1_W { + OVR1_W { w: self } + } + #[doc = "Bit 2 - Channel 2 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr2(&mut self) -> OVR2_W { + OVR2_W { w: self } + } + #[doc = "Bit 3 - Channel 3 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr3(&mut self) -> OVR3_W { + OVR3_W { w: self } + } + #[doc = "Bit 4 - Channel 4 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr4(&mut self) -> OVR4_W { + OVR4_W { w: self } + } + #[doc = "Bit 5 - Channel 5 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr5(&mut self) -> OVR5_W { + OVR5_W { w: self } + } + #[doc = "Bit 6 - Channel 6 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr6(&mut self) -> OVR6_W { + OVR6_W { w: self } + } + #[doc = "Bit 7 - Channel 7 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr7(&mut self) -> OVR7_W { + OVR7_W { w: self } + } + #[doc = "Bit 8 - Channel 8 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr8(&mut self) -> OVR8_W { + OVR8_W { w: self } + } + #[doc = "Bit 9 - Channel 9 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr9(&mut self) -> OVR9_W { + OVR9_W { w: self } + } + #[doc = "Bit 10 - Channel 10 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr10(&mut self) -> OVR10_W { + OVR10_W { w: self } + } + #[doc = "Bit 11 - Channel 11 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr11(&mut self) -> OVR11_W { + OVR11_W { w: self } + } + #[doc = "Bit 16 - Channel 0 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd0(&mut self) -> EVD0_W { + EVD0_W { w: self } + } + #[doc = "Bit 17 - Channel 1 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd1(&mut self) -> EVD1_W { + EVD1_W { w: self } + } + #[doc = "Bit 18 - Channel 2 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd2(&mut self) -> EVD2_W { + EVD2_W { w: self } + } + #[doc = "Bit 19 - Channel 3 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd3(&mut self) -> EVD3_W { + EVD3_W { w: self } + } + #[doc = "Bit 20 - Channel 4 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd4(&mut self) -> EVD4_W { + EVD4_W { w: self } + } + #[doc = "Bit 21 - Channel 5 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd5(&mut self) -> EVD5_W { + EVD5_W { w: self } + } + #[doc = "Bit 22 - Channel 6 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd6(&mut self) -> EVD6_W { + EVD6_W { w: self } + } + #[doc = "Bit 23 - Channel 7 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd7(&mut self) -> EVD7_W { + EVD7_W { w: self } + } + #[doc = "Bit 24 - Channel 8 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd8(&mut self) -> EVD8_W { + EVD8_W { w: self } + } + #[doc = "Bit 25 - Channel 9 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd9(&mut self) -> EVD9_W { + EVD9_W { w: self } + } + #[doc = "Bit 26 - Channel 10 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd10(&mut self) -> EVD10_W { + EVD10_W { w: self } + } + #[doc = "Bit 27 - Channel 11 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd11(&mut self) -> EVD11_W { + EVD11_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/evsys/intenset.rs b/pac/atsamc21j/src/evsys/intenset.rs new file mode 100644 index 000000000000..d84061297909 --- /dev/null +++ b/pac/atsamc21j/src/evsys/intenset.rs @@ -0,0 +1,1194 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVR0` reader - Channel 0 Overrun Interrupt Enable"] +pub struct OVR0_R(crate::FieldReader); +impl OVR0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR0` writer - Channel 0 Overrun Interrupt Enable"] +pub struct OVR0_W<'a> { + w: &'a mut W, +} +impl<'a> OVR0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `OVR1` reader - Channel 1 Overrun Interrupt Enable"] +pub struct OVR1_R(crate::FieldReader); +impl OVR1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR1` writer - Channel 1 Overrun Interrupt Enable"] +pub struct OVR1_W<'a> { + w: &'a mut W, +} +impl<'a> OVR1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `OVR2` reader - Channel 2 Overrun Interrupt Enable"] +pub struct OVR2_R(crate::FieldReader); +impl OVR2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR2` writer - Channel 2 Overrun Interrupt Enable"] +pub struct OVR2_W<'a> { + w: &'a mut W, +} +impl<'a> OVR2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `OVR3` reader - Channel 3 Overrun Interrupt Enable"] +pub struct OVR3_R(crate::FieldReader); +impl OVR3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR3` writer - Channel 3 Overrun Interrupt Enable"] +pub struct OVR3_W<'a> { + w: &'a mut W, +} +impl<'a> OVR3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `OVR4` reader - Channel 4 Overrun Interrupt Enable"] +pub struct OVR4_R(crate::FieldReader); +impl OVR4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR4` writer - Channel 4 Overrun Interrupt Enable"] +pub struct OVR4_W<'a> { + w: &'a mut W, +} +impl<'a> OVR4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `OVR5` reader - Channel 5 Overrun Interrupt Enable"] +pub struct OVR5_R(crate::FieldReader); +impl OVR5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR5` writer - Channel 5 Overrun Interrupt Enable"] +pub struct OVR5_W<'a> { + w: &'a mut W, +} +impl<'a> OVR5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `OVR6` reader - Channel 6 Overrun Interrupt Enable"] +pub struct OVR6_R(crate::FieldReader); +impl OVR6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR6` writer - Channel 6 Overrun Interrupt Enable"] +pub struct OVR6_W<'a> { + w: &'a mut W, +} +impl<'a> OVR6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `OVR7` reader - Channel 7 Overrun Interrupt Enable"] +pub struct OVR7_R(crate::FieldReader); +impl OVR7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR7` writer - Channel 7 Overrun Interrupt Enable"] +pub struct OVR7_W<'a> { + w: &'a mut W, +} +impl<'a> OVR7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `OVR8` reader - Channel 8 Overrun Interrupt Enable"] +pub struct OVR8_R(crate::FieldReader); +impl OVR8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR8` writer - Channel 8 Overrun Interrupt Enable"] +pub struct OVR8_W<'a> { + w: &'a mut W, +} +impl<'a> OVR8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `OVR9` reader - Channel 9 Overrun Interrupt Enable"] +pub struct OVR9_R(crate::FieldReader); +impl OVR9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR9` writer - Channel 9 Overrun Interrupt Enable"] +pub struct OVR9_W<'a> { + w: &'a mut W, +} +impl<'a> OVR9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `OVR10` reader - Channel 10 Overrun Interrupt Enable"] +pub struct OVR10_R(crate::FieldReader); +impl OVR10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR10` writer - Channel 10 Overrun Interrupt Enable"] +pub struct OVR10_W<'a> { + w: &'a mut W, +} +impl<'a> OVR10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `OVR11` reader - Channel 11 Overrun Interrupt Enable"] +pub struct OVR11_R(crate::FieldReader); +impl OVR11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR11` writer - Channel 11 Overrun Interrupt Enable"] +pub struct OVR11_W<'a> { + w: &'a mut W, +} +impl<'a> OVR11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `EVD0` reader - Channel 0 Event Detection Interrupt Enable"] +pub struct EVD0_R(crate::FieldReader); +impl EVD0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD0` writer - Channel 0 Event Detection Interrupt Enable"] +pub struct EVD0_W<'a> { + w: &'a mut W, +} +impl<'a> EVD0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `EVD1` reader - Channel 1 Event Detection Interrupt Enable"] +pub struct EVD1_R(crate::FieldReader); +impl EVD1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD1` writer - Channel 1 Event Detection Interrupt Enable"] +pub struct EVD1_W<'a> { + w: &'a mut W, +} +impl<'a> EVD1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `EVD2` reader - Channel 2 Event Detection Interrupt Enable"] +pub struct EVD2_R(crate::FieldReader); +impl EVD2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD2` writer - Channel 2 Event Detection Interrupt Enable"] +pub struct EVD2_W<'a> { + w: &'a mut W, +} +impl<'a> EVD2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `EVD3` reader - Channel 3 Event Detection Interrupt Enable"] +pub struct EVD3_R(crate::FieldReader); +impl EVD3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD3` writer - Channel 3 Event Detection Interrupt Enable"] +pub struct EVD3_W<'a> { + w: &'a mut W, +} +impl<'a> EVD3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `EVD4` reader - Channel 4 Event Detection Interrupt Enable"] +pub struct EVD4_R(crate::FieldReader); +impl EVD4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD4` writer - Channel 4 Event Detection Interrupt Enable"] +pub struct EVD4_W<'a> { + w: &'a mut W, +} +impl<'a> EVD4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `EVD5` reader - Channel 5 Event Detection Interrupt Enable"] +pub struct EVD5_R(crate::FieldReader); +impl EVD5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD5` writer - Channel 5 Event Detection Interrupt Enable"] +pub struct EVD5_W<'a> { + w: &'a mut W, +} +impl<'a> EVD5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `EVD6` reader - Channel 6 Event Detection Interrupt Enable"] +pub struct EVD6_R(crate::FieldReader); +impl EVD6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD6` writer - Channel 6 Event Detection Interrupt Enable"] +pub struct EVD6_W<'a> { + w: &'a mut W, +} +impl<'a> EVD6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `EVD7` reader - Channel 7 Event Detection Interrupt Enable"] +pub struct EVD7_R(crate::FieldReader); +impl EVD7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD7` writer - Channel 7 Event Detection Interrupt Enable"] +pub struct EVD7_W<'a> { + w: &'a mut W, +} +impl<'a> EVD7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `EVD8` reader - Channel 8 Event Detection Interrupt Enable"] +pub struct EVD8_R(crate::FieldReader); +impl EVD8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD8` writer - Channel 8 Event Detection Interrupt Enable"] +pub struct EVD8_W<'a> { + w: &'a mut W, +} +impl<'a> EVD8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `EVD9` reader - Channel 9 Event Detection Interrupt Enable"] +pub struct EVD9_R(crate::FieldReader); +impl EVD9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD9` writer - Channel 9 Event Detection Interrupt Enable"] +pub struct EVD9_W<'a> { + w: &'a mut W, +} +impl<'a> EVD9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `EVD10` reader - Channel 10 Event Detection Interrupt Enable"] +pub struct EVD10_R(crate::FieldReader); +impl EVD10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD10` writer - Channel 10 Event Detection Interrupt Enable"] +pub struct EVD10_W<'a> { + w: &'a mut W, +} +impl<'a> EVD10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `EVD11` reader - Channel 11 Event Detection Interrupt Enable"] +pub struct EVD11_R(crate::FieldReader); +impl EVD11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD11` writer - Channel 11 Event Detection Interrupt Enable"] +pub struct EVD11_W<'a> { + w: &'a mut W, +} +impl<'a> EVD11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +impl R { + #[doc = "Bit 0 - Channel 0 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr0(&self) -> OVR0_R { + OVR0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel 1 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr1(&self) -> OVR1_R { + OVR1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel 2 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr2(&self) -> OVR2_R { + OVR2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Channel 3 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr3(&self) -> OVR3_R { + OVR3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Channel 4 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr4(&self) -> OVR4_R { + OVR4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Channel 5 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr5(&self) -> OVR5_R { + OVR5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Channel 6 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr6(&self) -> OVR6_R { + OVR6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Channel 7 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr7(&self) -> OVR7_R { + OVR7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Channel 8 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr8(&self) -> OVR8_R { + OVR8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Channel 9 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr9(&self) -> OVR9_R { + OVR9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Channel 10 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr10(&self) -> OVR10_R { + OVR10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Channel 11 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr11(&self) -> OVR11_R { + OVR11_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 16 - Channel 0 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd0(&self) -> EVD0_R { + EVD0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Channel 1 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd1(&self) -> EVD1_R { + EVD1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Channel 2 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd2(&self) -> EVD2_R { + EVD2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Channel 3 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd3(&self) -> EVD3_R { + EVD3_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Channel 4 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd4(&self) -> EVD4_R { + EVD4_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Channel 5 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd5(&self) -> EVD5_R { + EVD5_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Channel 6 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd6(&self) -> EVD6_R { + EVD6_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Channel 7 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd7(&self) -> EVD7_R { + EVD7_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24 - Channel 8 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd8(&self) -> EVD8_R { + EVD8_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Channel 9 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd9(&self) -> EVD9_R { + EVD9_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Channel 10 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd10(&self) -> EVD10_R { + EVD10_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Channel 11 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd11(&self) -> EVD11_R { + EVD11_R::new(((self.bits >> 27) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel 0 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr0(&mut self) -> OVR0_W { + OVR0_W { w: self } + } + #[doc = "Bit 1 - Channel 1 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr1(&mut self) -> OVR1_W { + OVR1_W { w: self } + } + #[doc = "Bit 2 - Channel 2 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr2(&mut self) -> OVR2_W { + OVR2_W { w: self } + } + #[doc = "Bit 3 - Channel 3 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr3(&mut self) -> OVR3_W { + OVR3_W { w: self } + } + #[doc = "Bit 4 - Channel 4 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr4(&mut self) -> OVR4_W { + OVR4_W { w: self } + } + #[doc = "Bit 5 - Channel 5 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr5(&mut self) -> OVR5_W { + OVR5_W { w: self } + } + #[doc = "Bit 6 - Channel 6 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr6(&mut self) -> OVR6_W { + OVR6_W { w: self } + } + #[doc = "Bit 7 - Channel 7 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr7(&mut self) -> OVR7_W { + OVR7_W { w: self } + } + #[doc = "Bit 8 - Channel 8 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr8(&mut self) -> OVR8_W { + OVR8_W { w: self } + } + #[doc = "Bit 9 - Channel 9 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr9(&mut self) -> OVR9_W { + OVR9_W { w: self } + } + #[doc = "Bit 10 - Channel 10 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr10(&mut self) -> OVR10_W { + OVR10_W { w: self } + } + #[doc = "Bit 11 - Channel 11 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr11(&mut self) -> OVR11_W { + OVR11_W { w: self } + } + #[doc = "Bit 16 - Channel 0 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd0(&mut self) -> EVD0_W { + EVD0_W { w: self } + } + #[doc = "Bit 17 - Channel 1 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd1(&mut self) -> EVD1_W { + EVD1_W { w: self } + } + #[doc = "Bit 18 - Channel 2 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd2(&mut self) -> EVD2_W { + EVD2_W { w: self } + } + #[doc = "Bit 19 - Channel 3 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd3(&mut self) -> EVD3_W { + EVD3_W { w: self } + } + #[doc = "Bit 20 - Channel 4 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd4(&mut self) -> EVD4_W { + EVD4_W { w: self } + } + #[doc = "Bit 21 - Channel 5 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd5(&mut self) -> EVD5_W { + EVD5_W { w: self } + } + #[doc = "Bit 22 - Channel 6 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd6(&mut self) -> EVD6_W { + EVD6_W { w: self } + } + #[doc = "Bit 23 - Channel 7 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd7(&mut self) -> EVD7_W { + EVD7_W { w: self } + } + #[doc = "Bit 24 - Channel 8 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd8(&mut self) -> EVD8_W { + EVD8_W { w: self } + } + #[doc = "Bit 25 - Channel 9 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd9(&mut self) -> EVD9_W { + EVD9_W { w: self } + } + #[doc = "Bit 26 - Channel 10 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd10(&mut self) -> EVD10_W { + EVD10_W { w: self } + } + #[doc = "Bit 27 - Channel 11 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd11(&mut self) -> EVD11_W { + EVD11_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/evsys/intflag.rs b/pac/atsamc21j/src/evsys/intflag.rs new file mode 100644 index 000000000000..4d5cbe3950f6 --- /dev/null +++ b/pac/atsamc21j/src/evsys/intflag.rs @@ -0,0 +1,1194 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVR0` reader - Channel 0 Overrun"] +pub struct OVR0_R(crate::FieldReader); +impl OVR0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR0` writer - Channel 0 Overrun"] +pub struct OVR0_W<'a> { + w: &'a mut W, +} +impl<'a> OVR0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `OVR1` reader - Channel 1 Overrun"] +pub struct OVR1_R(crate::FieldReader); +impl OVR1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR1` writer - Channel 1 Overrun"] +pub struct OVR1_W<'a> { + w: &'a mut W, +} +impl<'a> OVR1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `OVR2` reader - Channel 2 Overrun"] +pub struct OVR2_R(crate::FieldReader); +impl OVR2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR2` writer - Channel 2 Overrun"] +pub struct OVR2_W<'a> { + w: &'a mut W, +} +impl<'a> OVR2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `OVR3` reader - Channel 3 Overrun"] +pub struct OVR3_R(crate::FieldReader); +impl OVR3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR3` writer - Channel 3 Overrun"] +pub struct OVR3_W<'a> { + w: &'a mut W, +} +impl<'a> OVR3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `OVR4` reader - Channel 4 Overrun"] +pub struct OVR4_R(crate::FieldReader); +impl OVR4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR4` writer - Channel 4 Overrun"] +pub struct OVR4_W<'a> { + w: &'a mut W, +} +impl<'a> OVR4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `OVR5` reader - Channel 5 Overrun"] +pub struct OVR5_R(crate::FieldReader); +impl OVR5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR5` writer - Channel 5 Overrun"] +pub struct OVR5_W<'a> { + w: &'a mut W, +} +impl<'a> OVR5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `OVR6` reader - Channel 6 Overrun"] +pub struct OVR6_R(crate::FieldReader); +impl OVR6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR6` writer - Channel 6 Overrun"] +pub struct OVR6_W<'a> { + w: &'a mut W, +} +impl<'a> OVR6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `OVR7` reader - Channel 7 Overrun"] +pub struct OVR7_R(crate::FieldReader); +impl OVR7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR7` writer - Channel 7 Overrun"] +pub struct OVR7_W<'a> { + w: &'a mut W, +} +impl<'a> OVR7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `OVR8` reader - Channel 8 Overrun"] +pub struct OVR8_R(crate::FieldReader); +impl OVR8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR8` writer - Channel 8 Overrun"] +pub struct OVR8_W<'a> { + w: &'a mut W, +} +impl<'a> OVR8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `OVR9` reader - Channel 9 Overrun"] +pub struct OVR9_R(crate::FieldReader); +impl OVR9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR9` writer - Channel 9 Overrun"] +pub struct OVR9_W<'a> { + w: &'a mut W, +} +impl<'a> OVR9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `OVR10` reader - Channel 10 Overrun"] +pub struct OVR10_R(crate::FieldReader); +impl OVR10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR10` writer - Channel 10 Overrun"] +pub struct OVR10_W<'a> { + w: &'a mut W, +} +impl<'a> OVR10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `OVR11` reader - Channel 11 Overrun"] +pub struct OVR11_R(crate::FieldReader); +impl OVR11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR11` writer - Channel 11 Overrun"] +pub struct OVR11_W<'a> { + w: &'a mut W, +} +impl<'a> OVR11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `EVD0` reader - Channel 0 Event Detection"] +pub struct EVD0_R(crate::FieldReader); +impl EVD0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD0` writer - Channel 0 Event Detection"] +pub struct EVD0_W<'a> { + w: &'a mut W, +} +impl<'a> EVD0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `EVD1` reader - Channel 1 Event Detection"] +pub struct EVD1_R(crate::FieldReader); +impl EVD1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD1` writer - Channel 1 Event Detection"] +pub struct EVD1_W<'a> { + w: &'a mut W, +} +impl<'a> EVD1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `EVD2` reader - Channel 2 Event Detection"] +pub struct EVD2_R(crate::FieldReader); +impl EVD2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD2` writer - Channel 2 Event Detection"] +pub struct EVD2_W<'a> { + w: &'a mut W, +} +impl<'a> EVD2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `EVD3` reader - Channel 3 Event Detection"] +pub struct EVD3_R(crate::FieldReader); +impl EVD3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD3` writer - Channel 3 Event Detection"] +pub struct EVD3_W<'a> { + w: &'a mut W, +} +impl<'a> EVD3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `EVD4` reader - Channel 4 Event Detection"] +pub struct EVD4_R(crate::FieldReader); +impl EVD4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD4` writer - Channel 4 Event Detection"] +pub struct EVD4_W<'a> { + w: &'a mut W, +} +impl<'a> EVD4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `EVD5` reader - Channel 5 Event Detection"] +pub struct EVD5_R(crate::FieldReader); +impl EVD5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD5` writer - Channel 5 Event Detection"] +pub struct EVD5_W<'a> { + w: &'a mut W, +} +impl<'a> EVD5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `EVD6` reader - Channel 6 Event Detection"] +pub struct EVD6_R(crate::FieldReader); +impl EVD6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD6` writer - Channel 6 Event Detection"] +pub struct EVD6_W<'a> { + w: &'a mut W, +} +impl<'a> EVD6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `EVD7` reader - Channel 7 Event Detection"] +pub struct EVD7_R(crate::FieldReader); +impl EVD7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD7` writer - Channel 7 Event Detection"] +pub struct EVD7_W<'a> { + w: &'a mut W, +} +impl<'a> EVD7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `EVD8` reader - Channel 8 Event Detection"] +pub struct EVD8_R(crate::FieldReader); +impl EVD8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD8` writer - Channel 8 Event Detection"] +pub struct EVD8_W<'a> { + w: &'a mut W, +} +impl<'a> EVD8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `EVD9` reader - Channel 9 Event Detection"] +pub struct EVD9_R(crate::FieldReader); +impl EVD9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD9` writer - Channel 9 Event Detection"] +pub struct EVD9_W<'a> { + w: &'a mut W, +} +impl<'a> EVD9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `EVD10` reader - Channel 10 Event Detection"] +pub struct EVD10_R(crate::FieldReader); +impl EVD10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD10` writer - Channel 10 Event Detection"] +pub struct EVD10_W<'a> { + w: &'a mut W, +} +impl<'a> EVD10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `EVD11` reader - Channel 11 Event Detection"] +pub struct EVD11_R(crate::FieldReader); +impl EVD11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD11` writer - Channel 11 Event Detection"] +pub struct EVD11_W<'a> { + w: &'a mut W, +} +impl<'a> EVD11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +impl R { + #[doc = "Bit 0 - Channel 0 Overrun"] + #[inline(always)] + pub fn ovr0(&self) -> OVR0_R { + OVR0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel 1 Overrun"] + #[inline(always)] + pub fn ovr1(&self) -> OVR1_R { + OVR1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel 2 Overrun"] + #[inline(always)] + pub fn ovr2(&self) -> OVR2_R { + OVR2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Channel 3 Overrun"] + #[inline(always)] + pub fn ovr3(&self) -> OVR3_R { + OVR3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Channel 4 Overrun"] + #[inline(always)] + pub fn ovr4(&self) -> OVR4_R { + OVR4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Channel 5 Overrun"] + #[inline(always)] + pub fn ovr5(&self) -> OVR5_R { + OVR5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Channel 6 Overrun"] + #[inline(always)] + pub fn ovr6(&self) -> OVR6_R { + OVR6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Channel 7 Overrun"] + #[inline(always)] + pub fn ovr7(&self) -> OVR7_R { + OVR7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Channel 8 Overrun"] + #[inline(always)] + pub fn ovr8(&self) -> OVR8_R { + OVR8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Channel 9 Overrun"] + #[inline(always)] + pub fn ovr9(&self) -> OVR9_R { + OVR9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Channel 10 Overrun"] + #[inline(always)] + pub fn ovr10(&self) -> OVR10_R { + OVR10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Channel 11 Overrun"] + #[inline(always)] + pub fn ovr11(&self) -> OVR11_R { + OVR11_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 16 - Channel 0 Event Detection"] + #[inline(always)] + pub fn evd0(&self) -> EVD0_R { + EVD0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Channel 1 Event Detection"] + #[inline(always)] + pub fn evd1(&self) -> EVD1_R { + EVD1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Channel 2 Event Detection"] + #[inline(always)] + pub fn evd2(&self) -> EVD2_R { + EVD2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Channel 3 Event Detection"] + #[inline(always)] + pub fn evd3(&self) -> EVD3_R { + EVD3_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Channel 4 Event Detection"] + #[inline(always)] + pub fn evd4(&self) -> EVD4_R { + EVD4_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Channel 5 Event Detection"] + #[inline(always)] + pub fn evd5(&self) -> EVD5_R { + EVD5_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Channel 6 Event Detection"] + #[inline(always)] + pub fn evd6(&self) -> EVD6_R { + EVD6_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Channel 7 Event Detection"] + #[inline(always)] + pub fn evd7(&self) -> EVD7_R { + EVD7_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24 - Channel 8 Event Detection"] + #[inline(always)] + pub fn evd8(&self) -> EVD8_R { + EVD8_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Channel 9 Event Detection"] + #[inline(always)] + pub fn evd9(&self) -> EVD9_R { + EVD9_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Channel 10 Event Detection"] + #[inline(always)] + pub fn evd10(&self) -> EVD10_R { + EVD10_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Channel 11 Event Detection"] + #[inline(always)] + pub fn evd11(&self) -> EVD11_R { + EVD11_R::new(((self.bits >> 27) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel 0 Overrun"] + #[inline(always)] + pub fn ovr0(&mut self) -> OVR0_W { + OVR0_W { w: self } + } + #[doc = "Bit 1 - Channel 1 Overrun"] + #[inline(always)] + pub fn ovr1(&mut self) -> OVR1_W { + OVR1_W { w: self } + } + #[doc = "Bit 2 - Channel 2 Overrun"] + #[inline(always)] + pub fn ovr2(&mut self) -> OVR2_W { + OVR2_W { w: self } + } + #[doc = "Bit 3 - Channel 3 Overrun"] + #[inline(always)] + pub fn ovr3(&mut self) -> OVR3_W { + OVR3_W { w: self } + } + #[doc = "Bit 4 - Channel 4 Overrun"] + #[inline(always)] + pub fn ovr4(&mut self) -> OVR4_W { + OVR4_W { w: self } + } + #[doc = "Bit 5 - Channel 5 Overrun"] + #[inline(always)] + pub fn ovr5(&mut self) -> OVR5_W { + OVR5_W { w: self } + } + #[doc = "Bit 6 - Channel 6 Overrun"] + #[inline(always)] + pub fn ovr6(&mut self) -> OVR6_W { + OVR6_W { w: self } + } + #[doc = "Bit 7 - Channel 7 Overrun"] + #[inline(always)] + pub fn ovr7(&mut self) -> OVR7_W { + OVR7_W { w: self } + } + #[doc = "Bit 8 - Channel 8 Overrun"] + #[inline(always)] + pub fn ovr8(&mut self) -> OVR8_W { + OVR8_W { w: self } + } + #[doc = "Bit 9 - Channel 9 Overrun"] + #[inline(always)] + pub fn ovr9(&mut self) -> OVR9_W { + OVR9_W { w: self } + } + #[doc = "Bit 10 - Channel 10 Overrun"] + #[inline(always)] + pub fn ovr10(&mut self) -> OVR10_W { + OVR10_W { w: self } + } + #[doc = "Bit 11 - Channel 11 Overrun"] + #[inline(always)] + pub fn ovr11(&mut self) -> OVR11_W { + OVR11_W { w: self } + } + #[doc = "Bit 16 - Channel 0 Event Detection"] + #[inline(always)] + pub fn evd0(&mut self) -> EVD0_W { + EVD0_W { w: self } + } + #[doc = "Bit 17 - Channel 1 Event Detection"] + #[inline(always)] + pub fn evd1(&mut self) -> EVD1_W { + EVD1_W { w: self } + } + #[doc = "Bit 18 - Channel 2 Event Detection"] + #[inline(always)] + pub fn evd2(&mut self) -> EVD2_W { + EVD2_W { w: self } + } + #[doc = "Bit 19 - Channel 3 Event Detection"] + #[inline(always)] + pub fn evd3(&mut self) -> EVD3_W { + EVD3_W { w: self } + } + #[doc = "Bit 20 - Channel 4 Event Detection"] + #[inline(always)] + pub fn evd4(&mut self) -> EVD4_W { + EVD4_W { w: self } + } + #[doc = "Bit 21 - Channel 5 Event Detection"] + #[inline(always)] + pub fn evd5(&mut self) -> EVD5_W { + EVD5_W { w: self } + } + #[doc = "Bit 22 - Channel 6 Event Detection"] + #[inline(always)] + pub fn evd6(&mut self) -> EVD6_W { + EVD6_W { w: self } + } + #[doc = "Bit 23 - Channel 7 Event Detection"] + #[inline(always)] + pub fn evd7(&mut self) -> EVD7_W { + EVD7_W { w: self } + } + #[doc = "Bit 24 - Channel 8 Event Detection"] + #[inline(always)] + pub fn evd8(&mut self) -> EVD8_W { + EVD8_W { w: self } + } + #[doc = "Bit 25 - Channel 9 Event Detection"] + #[inline(always)] + pub fn evd9(&mut self) -> EVD9_W { + EVD9_W { w: self } + } + #[doc = "Bit 26 - Channel 10 Event Detection"] + #[inline(always)] + pub fn evd10(&mut self) -> EVD10_W { + EVD10_W { w: self } + } + #[doc = "Bit 27 - Channel 11 Event Detection"] + #[inline(always)] + pub fn evd11(&mut self) -> EVD11_W { + EVD11_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/evsys/swevt.rs b/pac/atsamc21j/src/evsys/swevt.rs new file mode 100644 index 000000000000..df58fe290de2 --- /dev/null +++ b/pac/atsamc21j/src/evsys/swevt.rs @@ -0,0 +1,369 @@ +#[doc = "Register `SWEVT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHANNEL0` writer - Channel 0 Software Selection"] +pub struct CHANNEL0_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `CHANNEL1` writer - Channel 1 Software Selection"] +pub struct CHANNEL1_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CHANNEL2` writer - Channel 2 Software Selection"] +pub struct CHANNEL2_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CHANNEL3` writer - Channel 3 Software Selection"] +pub struct CHANNEL3_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CHANNEL4` writer - Channel 4 Software Selection"] +pub struct CHANNEL4_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `CHANNEL5` writer - Channel 5 Software Selection"] +pub struct CHANNEL5_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `CHANNEL6` writer - Channel 6 Software Selection"] +pub struct CHANNEL6_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `CHANNEL7` writer - Channel 7 Software Selection"] +pub struct CHANNEL7_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CHANNEL8` writer - Channel 8 Software Selection"] +pub struct CHANNEL8_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `CHANNEL9` writer - Channel 9 Software Selection"] +pub struct CHANNEL9_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `CHANNEL10` writer - Channel 10 Software Selection"] +pub struct CHANNEL10_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `CHANNEL11` writer - Channel 11 Software Selection"] +pub struct CHANNEL11_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +impl W { + #[doc = "Bit 0 - Channel 0 Software Selection"] + #[inline(always)] + pub fn channel0(&mut self) -> CHANNEL0_W { + CHANNEL0_W { w: self } + } + #[doc = "Bit 1 - Channel 1 Software Selection"] + #[inline(always)] + pub fn channel1(&mut self) -> CHANNEL1_W { + CHANNEL1_W { w: self } + } + #[doc = "Bit 2 - Channel 2 Software Selection"] + #[inline(always)] + pub fn channel2(&mut self) -> CHANNEL2_W { + CHANNEL2_W { w: self } + } + #[doc = "Bit 3 - Channel 3 Software Selection"] + #[inline(always)] + pub fn channel3(&mut self) -> CHANNEL3_W { + CHANNEL3_W { w: self } + } + #[doc = "Bit 4 - Channel 4 Software Selection"] + #[inline(always)] + pub fn channel4(&mut self) -> CHANNEL4_W { + CHANNEL4_W { w: self } + } + #[doc = "Bit 5 - Channel 5 Software Selection"] + #[inline(always)] + pub fn channel5(&mut self) -> CHANNEL5_W { + CHANNEL5_W { w: self } + } + #[doc = "Bit 6 - Channel 6 Software Selection"] + #[inline(always)] + pub fn channel6(&mut self) -> CHANNEL6_W { + CHANNEL6_W { w: self } + } + #[doc = "Bit 7 - Channel 7 Software Selection"] + #[inline(always)] + pub fn channel7(&mut self) -> CHANNEL7_W { + CHANNEL7_W { w: self } + } + #[doc = "Bit 8 - Channel 8 Software Selection"] + #[inline(always)] + pub fn channel8(&mut self) -> CHANNEL8_W { + CHANNEL8_W { w: self } + } + #[doc = "Bit 9 - Channel 9 Software Selection"] + #[inline(always)] + pub fn channel9(&mut self) -> CHANNEL9_W { + CHANNEL9_W { w: self } + } + #[doc = "Bit 10 - Channel 10 Software Selection"] + #[inline(always)] + pub fn channel10(&mut self) -> CHANNEL10_W { + CHANNEL10_W { w: self } + } + #[doc = "Bit 11 - Channel 11 Software Selection"] + #[inline(always)] + pub fn channel11(&mut self) -> CHANNEL11_W { + CHANNEL11_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Software Event\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [swevt](index.html) module"] +pub struct SWEVT_SPEC; +impl crate::RegisterSpec for SWEVT_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [swevt::W](W) writer structure"] +impl crate::Writable for SWEVT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SWEVT to value 0"] +impl crate::Resettable for SWEVT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/evsys/user.rs b/pac/atsamc21j/src/evsys/user.rs new file mode 100644 index 000000000000..848f9f599b79 --- /dev/null +++ b/pac/atsamc21j/src/evsys/user.rs @@ -0,0 +1,104 @@ +#[doc = "Register `USER[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `USER[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHANNEL` reader - Channel Event Selection"] +pub struct CHANNEL_R(crate::FieldReader); +impl CHANNEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CHANNEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHANNEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHANNEL` writer - Channel Event Selection"] +pub struct CHANNEL_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Channel Event Selection"] + #[inline(always)] + pub fn channel(&self) -> CHANNEL_R { + CHANNEL_R::new((self.bits & 0x1f) as u8) + } +} +impl W { + #[doc = "Bits 0:4 - Channel Event Selection"] + #[inline(always)] + pub fn channel(&mut self) -> CHANNEL_W { + CHANNEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "User Multiplexer n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [user](index.html) module"] +pub struct USER_SPEC; +impl crate::RegisterSpec for USER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [user::R](R) reader structure"] +impl crate::Readable for USER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [user::W](W) writer structure"] +impl crate::Writable for USER_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets USER[%s] +to value 0"] +impl crate::Resettable for USER_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/freqm.rs b/pac/atsamc21j/src/freqm.rs new file mode 100644 index 000000000000..f0fc6fda975e --- /dev/null +++ b/pac/atsamc21j/src/freqm.rs @@ -0,0 +1,59 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control A Register"] + pub ctrla: crate::Reg, + #[doc = "0x01 - Control B Register"] + pub ctrlb: crate::Reg, + #[doc = "0x02 - Config A register"] + pub cfga: crate::Reg, + _reserved3: [u8; 0x04], + #[doc = "0x08 - Interrupt Enable Clear Register"] + pub intenclr: crate::Reg, + #[doc = "0x09 - Interrupt Enable Set Register"] + pub intenset: crate::Reg, + #[doc = "0x0a - Interrupt Flag Register"] + pub intflag: crate::Reg, + #[doc = "0x0b - Status Register"] + pub status: crate::Reg, + #[doc = "0x0c - Synchronization Busy Register"] + pub syncbusy: crate::Reg, + #[doc = "0x10 - Count Value Register"] + pub value: crate::Reg, +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A Register"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "Control B Register"] +pub mod ctrlb; +#[doc = "CFGA register accessor: an alias for `Reg`"] +pub type CFGA = crate::Reg; +#[doc = "Config A register"] +pub mod cfga; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear Register"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set Register"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Register"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status Register"] +pub mod status; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Busy Register"] +pub mod syncbusy; +#[doc = "VALUE register accessor: an alias for `Reg`"] +pub type VALUE = crate::Reg; +#[doc = "Count Value Register"] +pub mod value; diff --git a/pac/atsamc21j/src/freqm/cfga.rs b/pac/atsamc21j/src/freqm/cfga.rs new file mode 100644 index 000000000000..573c62964185 --- /dev/null +++ b/pac/atsamc21j/src/freqm/cfga.rs @@ -0,0 +1,103 @@ +#[doc = "Register `CFGA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CFGA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `REFNUM` reader - Number of Reference Clock Cycles"] +pub struct REFNUM_R(crate::FieldReader); +impl REFNUM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REFNUM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REFNUM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REFNUM` writer - Number of Reference Clock Cycles"] +pub struct REFNUM_W<'a> { + w: &'a mut W, +} +impl<'a> REFNUM_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u16 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Number of Reference Clock Cycles"] + #[inline(always)] + pub fn refnum(&self) -> REFNUM_R { + REFNUM_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Number of Reference Clock Cycles"] + #[inline(always)] + pub fn refnum(&mut self) -> REFNUM_W { + REFNUM_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Config A register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cfga](index.html) module"] +pub struct CFGA_SPEC; +impl crate::RegisterSpec for CFGA_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [cfga::R](R) reader structure"] +impl crate::Readable for CFGA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cfga::W](W) writer structure"] +impl crate::Writable for CFGA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CFGA to value 0"] +impl crate::Resettable for CFGA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/freqm/ctrla.rs b/pac/atsamc21j/src/freqm/ctrla.rs new file mode 100644 index 000000000000..b2cefdd45770 --- /dev/null +++ b/pac/atsamc21j/src/freqm/ctrla.rs @@ -0,0 +1,160 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/freqm/ctrlb.rs b/pac/atsamc21j/src/freqm/ctrlb.rs new file mode 100644 index 000000000000..7d350e71fbf3 --- /dev/null +++ b/pac/atsamc21j/src/freqm/ctrlb.rs @@ -0,0 +1,72 @@ +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `START` writer - Start Measurement"] +pub struct START_W<'a> { + w: &'a mut W, +} +impl<'a> START_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0 - Start Measurement"] + #[inline(always)] + pub fn start(&mut self) -> START_W { + START_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u8; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/freqm/intenclr.rs b/pac/atsamc21j/src/freqm/intenclr.rs new file mode 100644 index 000000000000..a224aa5500f6 --- /dev/null +++ b/pac/atsamc21j/src/freqm/intenclr.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DONE` reader - Measurement Done Interrupt Enable"] +pub struct DONE_R(crate::FieldReader); +impl DONE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DONE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DONE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DONE` writer - Measurement Done Interrupt Enable"] +pub struct DONE_W<'a> { + w: &'a mut W, +} +impl<'a> DONE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Measurement Done Interrupt Enable"] + #[inline(always)] + pub fn done(&self) -> DONE_R { + DONE_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Measurement Done Interrupt Enable"] + #[inline(always)] + pub fn done(&mut self) -> DONE_W { + DONE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/freqm/intenset.rs b/pac/atsamc21j/src/freqm/intenset.rs new file mode 100644 index 000000000000..53b3d0bef7c0 --- /dev/null +++ b/pac/atsamc21j/src/freqm/intenset.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DONE` reader - Measurement Done Interrupt Enable"] +pub struct DONE_R(crate::FieldReader); +impl DONE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DONE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DONE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DONE` writer - Measurement Done Interrupt Enable"] +pub struct DONE_W<'a> { + w: &'a mut W, +} +impl<'a> DONE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Measurement Done Interrupt Enable"] + #[inline(always)] + pub fn done(&self) -> DONE_R { + DONE_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Measurement Done Interrupt Enable"] + #[inline(always)] + pub fn done(&mut self) -> DONE_W { + DONE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/freqm/intflag.rs b/pac/atsamc21j/src/freqm/intflag.rs new file mode 100644 index 000000000000..3b8fdab47703 --- /dev/null +++ b/pac/atsamc21j/src/freqm/intflag.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DONE` reader - Measurement Done"] +pub struct DONE_R(crate::FieldReader); +impl DONE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DONE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DONE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DONE` writer - Measurement Done"] +pub struct DONE_W<'a> { + w: &'a mut W, +} +impl<'a> DONE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Measurement Done"] + #[inline(always)] + pub fn done(&self) -> DONE_R { + DONE_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Measurement Done"] + #[inline(always)] + pub fn done(&mut self) -> DONE_W { + DONE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/freqm/status.rs b/pac/atsamc21j/src/freqm/status.rs new file mode 100644 index 000000000000..8a81662f51b0 --- /dev/null +++ b/pac/atsamc21j/src/freqm/status.rs @@ -0,0 +1,160 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BUSY` reader - FREQM Status"] +pub struct BUSY_R(crate::FieldReader); +impl BUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSY` writer - FREQM Status"] +pub struct BUSY_W<'a> { + w: &'a mut W, +} +impl<'a> BUSY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `OVF` reader - Sticky Count Value Overflow"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Sticky Count Value Overflow"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - FREQM Status"] + #[inline(always)] + pub fn busy(&self) -> BUSY_R { + BUSY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Sticky Count Value Overflow"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - FREQM Status"] + #[inline(always)] + pub fn busy(&mut self) -> BUSY_W { + BUSY_W { w: self } + } + #[doc = "Bit 1 - Sticky Count Value Overflow"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/freqm/syncbusy.rs b/pac/atsamc21j/src/freqm/syncbusy.rs new file mode 100644 index 000000000000..54396368e817 --- /dev/null +++ b/pac/atsamc21j/src/freqm/syncbusy.rs @@ -0,0 +1,73 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +#[doc = "Synchronization Busy Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/freqm/value.rs b/pac/atsamc21j/src/freqm/value.rs new file mode 100644 index 000000000000..5b0f5dfd9b67 --- /dev/null +++ b/pac/atsamc21j/src/freqm/value.rs @@ -0,0 +1,53 @@ +#[doc = "Register `VALUE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `VALUE` reader - Measurement Value"] +pub struct VALUE_R(crate::FieldReader); +impl VALUE_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + VALUE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VALUE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:23 - Measurement Value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +#[doc = "Count Value Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [value](index.html) module"] +pub struct VALUE_SPEC; +impl crate::RegisterSpec for VALUE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [value::R](R) reader structure"] +impl crate::Readable for VALUE_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets VALUE to value 0"] +impl crate::Resettable for VALUE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/gclk.rs b/pac/atsamc21j/src/gclk.rs new file mode 100644 index 000000000000..2a37bdedcab3 --- /dev/null +++ b/pac/atsamc21j/src/gclk.rs @@ -0,0 +1,31 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrla: crate::Reg, + _reserved1: [u8; 0x03], + #[doc = "0x04 - Synchronization Busy"] + pub syncbusy: crate::Reg, + _reserved2: [u8; 0x18], + #[doc = "0x20..0x44 - Generic Clock Generator Control"] + pub genctrl: [crate::Reg; 9], + _reserved3: [u8; 0x3c], + #[doc = "0x80..0x124 - Peripheral Clock Control"] + pub pchctrl: [crate::Reg; 41], +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control"] +pub mod ctrla; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Busy"] +pub mod syncbusy; +#[doc = "GENCTRL register accessor: an alias for `Reg`"] +pub type GENCTRL = crate::Reg; +#[doc = "Generic Clock Generator Control"] +pub mod genctrl; +#[doc = "PCHCTRL register accessor: an alias for `Reg`"] +pub type PCHCTRL = crate::Reg; +#[doc = "Peripheral Clock Control"] +pub mod pchctrl; diff --git a/pac/atsamc21j/src/gclk/ctrla.rs b/pac/atsamc21j/src/gclk/ctrla.rs new file mode 100644 index 000000000000..1c24704395ad --- /dev/null +++ b/pac/atsamc21j/src/gclk/ctrla.rs @@ -0,0 +1,113 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/gclk/genctrl.rs b/pac/atsamc21j/src/gclk/genctrl.rs new file mode 100644 index 000000000000..052b2915ca7f --- /dev/null +++ b/pac/atsamc21j/src/gclk/genctrl.rs @@ -0,0 +1,597 @@ +#[doc = "Register `GENCTRL[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GENCTRL[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Source Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SRC_A { + #[doc = "0: XOSC oscillator output"] + XOSC = 0, + #[doc = "1: Generator input pad"] + GCLKIN = 1, + #[doc = "2: Generic clock generator 1 output"] + GCLKGEN1 = 2, + #[doc = "3: OSCULP32K oscillator output"] + OSCULP32K = 3, + #[doc = "4: OSC32K oscillator output"] + OSC32K = 4, + #[doc = "5: XOSC32K oscillator output"] + XOSC32K = 5, + #[doc = "6: OSC48M oscillator output"] + OSC48M = 6, + #[doc = "7: DPLL96M output"] + DPLL96M = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SRC_A) -> Self { + variant as _ + } +} +#[doc = "Field `SRC` reader - Source Select"] +pub struct SRC_R(crate::FieldReader); +impl SRC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SRC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SRC_A { + match self.bits { + 0 => SRC_A::XOSC, + 1 => SRC_A::GCLKIN, + 2 => SRC_A::GCLKGEN1, + 3 => SRC_A::OSCULP32K, + 4 => SRC_A::OSC32K, + 5 => SRC_A::XOSC32K, + 6 => SRC_A::OSC48M, + 7 => SRC_A::DPLL96M, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `XOSC`"] + #[inline(always)] + pub fn is_xosc(&self) -> bool { + **self == SRC_A::XOSC + } + #[doc = "Checks if the value of the field is `GCLKIN`"] + #[inline(always)] + pub fn is_gclkin(&self) -> bool { + **self == SRC_A::GCLKIN + } + #[doc = "Checks if the value of the field is `GCLKGEN1`"] + #[inline(always)] + pub fn is_gclkgen1(&self) -> bool { + **self == SRC_A::GCLKGEN1 + } + #[doc = "Checks if the value of the field is `OSCULP32K`"] + #[inline(always)] + pub fn is_osculp32k(&self) -> bool { + **self == SRC_A::OSCULP32K + } + #[doc = "Checks if the value of the field is `OSC32K`"] + #[inline(always)] + pub fn is_osc32k(&self) -> bool { + **self == SRC_A::OSC32K + } + #[doc = "Checks if the value of the field is `XOSC32K`"] + #[inline(always)] + pub fn is_xosc32k(&self) -> bool { + **self == SRC_A::XOSC32K + } + #[doc = "Checks if the value of the field is `OSC48M`"] + #[inline(always)] + pub fn is_osc48m(&self) -> bool { + **self == SRC_A::OSC48M + } + #[doc = "Checks if the value of the field is `DPLL96M`"] + #[inline(always)] + pub fn is_dpll96m(&self) -> bool { + **self == SRC_A::DPLL96M + } +} +impl core::ops::Deref for SRC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SRC` writer - Source Select"] +pub struct SRC_W<'a> { + w: &'a mut W, +} +impl<'a> SRC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SRC_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "XOSC oscillator output"] + #[inline(always)] + pub fn xosc(self) -> &'a mut W { + self.variant(SRC_A::XOSC) + } + #[doc = "Generator input pad"] + #[inline(always)] + pub fn gclkin(self) -> &'a mut W { + self.variant(SRC_A::GCLKIN) + } + #[doc = "Generic clock generator 1 output"] + #[inline(always)] + pub fn gclkgen1(self) -> &'a mut W { + self.variant(SRC_A::GCLKGEN1) + } + #[doc = "OSCULP32K oscillator output"] + #[inline(always)] + pub fn osculp32k(self) -> &'a mut W { + self.variant(SRC_A::OSCULP32K) + } + #[doc = "OSC32K oscillator output"] + #[inline(always)] + pub fn osc32k(self) -> &'a mut W { + self.variant(SRC_A::OSC32K) + } + #[doc = "XOSC32K oscillator output"] + #[inline(always)] + pub fn xosc32k(self) -> &'a mut W { + self.variant(SRC_A::XOSC32K) + } + #[doc = "OSC48M oscillator output"] + #[inline(always)] + pub fn osc48m(self) -> &'a mut W { + self.variant(SRC_A::OSC48M) + } + #[doc = "DPLL96M output"] + #[inline(always)] + pub fn dpll96m(self) -> &'a mut W { + self.variant(SRC_A::DPLL96M) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Field `GENEN` reader - Generic Clock Generator Enable"] +pub struct GENEN_R(crate::FieldReader); +impl GENEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENEN` writer - Generic Clock Generator Enable"] +pub struct GENEN_W<'a> { + w: &'a mut W, +} +impl<'a> GENEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `IDC` reader - Improve Duty Cycle"] +pub struct IDC_R(crate::FieldReader); +impl IDC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IDC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IDC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IDC` writer - Improve Duty Cycle"] +pub struct IDC_W<'a> { + w: &'a mut W, +} +impl<'a> IDC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `OOV` reader - Output Off Value"] +pub struct OOV_R(crate::FieldReader); +impl OOV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OOV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OOV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OOV` writer - Output Off Value"] +pub struct OOV_W<'a> { + w: &'a mut W, +} +impl<'a> OOV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `OE` reader - Output Enable"] +pub struct OE_R(crate::FieldReader); +impl OE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OE` writer - Output Enable"] +pub struct OE_W<'a> { + w: &'a mut W, +} +impl<'a> OE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Divide Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum DIVSEL_A { + #[doc = "0: Divide input directly by divider factor"] + DIV1 = 0, + #[doc = "1: Divide input by 2^(divider factor+ 1)"] + DIV2 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DIVSEL_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DIVSEL` reader - Divide Selection"] +pub struct DIVSEL_R(crate::FieldReader); +impl DIVSEL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIVSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DIVSEL_A { + match self.bits { + false => DIVSEL_A::DIV1, + true => DIVSEL_A::DIV2, + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == DIVSEL_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == DIVSEL_A::DIV2 + } +} +impl core::ops::Deref for DIVSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIVSEL` writer - Divide Selection"] +pub struct DIVSEL_W<'a> { + w: &'a mut W, +} +impl<'a> DIVSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DIVSEL_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Divide input directly by divider factor"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(DIVSEL_A::DIV1) + } + #[doc = "Divide input by 2^(divider factor+ 1)"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(DIVSEL_A::DIV2) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `DIV` reader - Division Factor"] +pub struct DIV_R(crate::FieldReader); +impl DIV_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + DIV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIV` writer - Division Factor"] +pub struct DIV_W<'a> { + w: &'a mut W, +} +impl<'a> DIV_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xffff << 16)) | ((value as u32 & 0xffff) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Source Select"] + #[inline(always)] + pub fn src(&self) -> SRC_R { + SRC_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 8 - Generic Clock Generator Enable"] + #[inline(always)] + pub fn genen(&self) -> GENEN_R { + GENEN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Improve Duty Cycle"] + #[inline(always)] + pub fn idc(&self) -> IDC_R { + IDC_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Output Off Value"] + #[inline(always)] + pub fn oov(&self) -> OOV_R { + OOV_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Output Enable"] + #[inline(always)] + pub fn oe(&self) -> OE_R { + OE_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Divide Selection"] + #[inline(always)] + pub fn divsel(&self) -> DIVSEL_R { + DIVSEL_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bits 16:31 - Division Factor"] + #[inline(always)] + pub fn div(&self) -> DIV_R { + DIV_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:2 - Source Select"] + #[inline(always)] + pub fn src(&mut self) -> SRC_W { + SRC_W { w: self } + } + #[doc = "Bit 8 - Generic Clock Generator Enable"] + #[inline(always)] + pub fn genen(&mut self) -> GENEN_W { + GENEN_W { w: self } + } + #[doc = "Bit 9 - Improve Duty Cycle"] + #[inline(always)] + pub fn idc(&mut self) -> IDC_W { + IDC_W { w: self } + } + #[doc = "Bit 10 - Output Off Value"] + #[inline(always)] + pub fn oov(&mut self) -> OOV_W { + OOV_W { w: self } + } + #[doc = "Bit 11 - Output Enable"] + #[inline(always)] + pub fn oe(&mut self) -> OE_W { + OE_W { w: self } + } + #[doc = "Bit 12 - Divide Selection"] + #[inline(always)] + pub fn divsel(&mut self) -> DIVSEL_W { + DIVSEL_W { w: self } + } + #[doc = "Bit 13 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bits 16:31 - Division Factor"] + #[inline(always)] + pub fn div(&mut self) -> DIV_W { + DIV_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Generic Clock Generator Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [genctrl](index.html) module"] +pub struct GENCTRL_SPEC; +impl crate::RegisterSpec for GENCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [genctrl::R](R) reader structure"] +impl crate::Readable for GENCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [genctrl::W](W) writer structure"] +impl crate::Writable for GENCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets GENCTRL[%s] +to value 0"] +impl crate::Resettable for GENCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/gclk/pchctrl.rs b/pac/atsamc21j/src/gclk/pchctrl.rs new file mode 100644 index 000000000000..8001ffeaa1ee --- /dev/null +++ b/pac/atsamc21j/src/gclk/pchctrl.rs @@ -0,0 +1,338 @@ +#[doc = "Register `PCHCTRL[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PCHCTRL[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Generic Clock Generator\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum GEN_A { + #[doc = "0: Generic clock generator 0"] + GCLK0 = 0, + #[doc = "1: Generic clock generator 1"] + GCLK1 = 1, + #[doc = "2: Generic clock generator 2"] + GCLK2 = 2, + #[doc = "3: Generic clock generator 3"] + GCLK3 = 3, + #[doc = "4: Generic clock generator 4"] + GCLK4 = 4, + #[doc = "5: Generic clock generator 5"] + GCLK5 = 5, + #[doc = "6: Generic clock generator 6"] + GCLK6 = 6, + #[doc = "7: Generic clock generator 7"] + GCLK7 = 7, + #[doc = "8: Generic clock generator 8"] + GCLK8 = 8, +} +impl From for u8 { + #[inline(always)] + fn from(variant: GEN_A) -> Self { + variant as _ + } +} +#[doc = "Field `GEN` reader - Generic Clock Generator"] +pub struct GEN_R(crate::FieldReader); +impl GEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + GEN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(GEN_A::GCLK0), + 1 => Some(GEN_A::GCLK1), + 2 => Some(GEN_A::GCLK2), + 3 => Some(GEN_A::GCLK3), + 4 => Some(GEN_A::GCLK4), + 5 => Some(GEN_A::GCLK5), + 6 => Some(GEN_A::GCLK6), + 7 => Some(GEN_A::GCLK7), + 8 => Some(GEN_A::GCLK8), + _ => None, + } + } + #[doc = "Checks if the value of the field is `GCLK0`"] + #[inline(always)] + pub fn is_gclk0(&self) -> bool { + **self == GEN_A::GCLK0 + } + #[doc = "Checks if the value of the field is `GCLK1`"] + #[inline(always)] + pub fn is_gclk1(&self) -> bool { + **self == GEN_A::GCLK1 + } + #[doc = "Checks if the value of the field is `GCLK2`"] + #[inline(always)] + pub fn is_gclk2(&self) -> bool { + **self == GEN_A::GCLK2 + } + #[doc = "Checks if the value of the field is `GCLK3`"] + #[inline(always)] + pub fn is_gclk3(&self) -> bool { + **self == GEN_A::GCLK3 + } + #[doc = "Checks if the value of the field is `GCLK4`"] + #[inline(always)] + pub fn is_gclk4(&self) -> bool { + **self == GEN_A::GCLK4 + } + #[doc = "Checks if the value of the field is `GCLK5`"] + #[inline(always)] + pub fn is_gclk5(&self) -> bool { + **self == GEN_A::GCLK5 + } + #[doc = "Checks if the value of the field is `GCLK6`"] + #[inline(always)] + pub fn is_gclk6(&self) -> bool { + **self == GEN_A::GCLK6 + } + #[doc = "Checks if the value of the field is `GCLK7`"] + #[inline(always)] + pub fn is_gclk7(&self) -> bool { + **self == GEN_A::GCLK7 + } + #[doc = "Checks if the value of the field is `GCLK8`"] + #[inline(always)] + pub fn is_gclk8(&self) -> bool { + **self == GEN_A::GCLK8 + } +} +impl core::ops::Deref for GEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GEN` writer - Generic Clock Generator"] +pub struct GEN_W<'a> { + w: &'a mut W, +} +impl<'a> GEN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: GEN_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Generic clock generator 0"] + #[inline(always)] + pub fn gclk0(self) -> &'a mut W { + self.variant(GEN_A::GCLK0) + } + #[doc = "Generic clock generator 1"] + #[inline(always)] + pub fn gclk1(self) -> &'a mut W { + self.variant(GEN_A::GCLK1) + } + #[doc = "Generic clock generator 2"] + #[inline(always)] + pub fn gclk2(self) -> &'a mut W { + self.variant(GEN_A::GCLK2) + } + #[doc = "Generic clock generator 3"] + #[inline(always)] + pub fn gclk3(self) -> &'a mut W { + self.variant(GEN_A::GCLK3) + } + #[doc = "Generic clock generator 4"] + #[inline(always)] + pub fn gclk4(self) -> &'a mut W { + self.variant(GEN_A::GCLK4) + } + #[doc = "Generic clock generator 5"] + #[inline(always)] + pub fn gclk5(self) -> &'a mut W { + self.variant(GEN_A::GCLK5) + } + #[doc = "Generic clock generator 6"] + #[inline(always)] + pub fn gclk6(self) -> &'a mut W { + self.variant(GEN_A::GCLK6) + } + #[doc = "Generic clock generator 7"] + #[inline(always)] + pub fn gclk7(self) -> &'a mut W { + self.variant(GEN_A::GCLK7) + } + #[doc = "Generic clock generator 8"] + #[inline(always)] + pub fn gclk8(self) -> &'a mut W { + self.variant(GEN_A::GCLK8) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Field `CHEN` reader - Channel Enable"] +pub struct CHEN_R(crate::FieldReader); +impl CHEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHEN` writer - Channel Enable"] +pub struct CHEN_W<'a> { + w: &'a mut W, +} +impl<'a> CHEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `WRTLOCK` reader - Write Lock"] +pub struct WRTLOCK_R(crate::FieldReader); +impl WRTLOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WRTLOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WRTLOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WRTLOCK` writer - Write Lock"] +pub struct WRTLOCK_W<'a> { + w: &'a mut W, +} +impl<'a> WRTLOCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Generic Clock Generator"] + #[inline(always)] + pub fn gen(&self) -> GEN_R { + GEN_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 6 - Channel Enable"] + #[inline(always)] + pub fn chen(&self) -> CHEN_R { + CHEN_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&self) -> WRTLOCK_R { + WRTLOCK_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Generic Clock Generator"] + #[inline(always)] + pub fn gen(&mut self) -> GEN_W { + GEN_W { w: self } + } + #[doc = "Bit 6 - Channel Enable"] + #[inline(always)] + pub fn chen(&mut self) -> CHEN_W { + CHEN_W { w: self } + } + #[doc = "Bit 7 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&mut self) -> WRTLOCK_W { + WRTLOCK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Peripheral Clock Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pchctrl](index.html) module"] +pub struct PCHCTRL_SPEC; +impl crate::RegisterSpec for PCHCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pchctrl::R](R) reader structure"] +impl crate::Readable for PCHCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [pchctrl::W](W) writer structure"] +impl crate::Writable for PCHCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PCHCTRL[%s] +to value 0"] +impl crate::Resettable for PCHCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/gclk/syncbusy.rs b/pac/atsamc21j/src/gclk/syncbusy.rs new file mode 100644 index 000000000000..f21640440354 --- /dev/null +++ b/pac/atsamc21j/src/gclk/syncbusy.rs @@ -0,0 +1,233 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchroniation Busy bit"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENCTRL0` reader - Generic Clock Generator Control 0 Synchronization Busy bits"] +pub struct GENCTRL0_R(crate::FieldReader); +impl GENCTRL0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENCTRL0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENCTRL0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENCTRL1` reader - Generic Clock Generator Control 1 Synchronization Busy bits"] +pub struct GENCTRL1_R(crate::FieldReader); +impl GENCTRL1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENCTRL1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENCTRL1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENCTRL2` reader - Generic Clock Generator Control 2 Synchronization Busy bits"] +pub struct GENCTRL2_R(crate::FieldReader); +impl GENCTRL2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENCTRL2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENCTRL2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENCTRL3` reader - Generic Clock Generator Control 3 Synchronization Busy bits"] +pub struct GENCTRL3_R(crate::FieldReader); +impl GENCTRL3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENCTRL3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENCTRL3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENCTRL4` reader - Generic Clock Generator Control 4 Synchronization Busy bits"] +pub struct GENCTRL4_R(crate::FieldReader); +impl GENCTRL4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENCTRL4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENCTRL4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENCTRL5` reader - Generic Clock Generator Control 5 Synchronization Busy bits"] +pub struct GENCTRL5_R(crate::FieldReader); +impl GENCTRL5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENCTRL5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENCTRL5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENCTRL6` reader - Generic Clock Generator Control 6 Synchronization Busy bits"] +pub struct GENCTRL6_R(crate::FieldReader); +impl GENCTRL6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENCTRL6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENCTRL6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENCTRL7` reader - Generic Clock Generator Control 7 Synchronization Busy bits"] +pub struct GENCTRL7_R(crate::FieldReader); +impl GENCTRL7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENCTRL7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENCTRL7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENCTRL8` reader - Generic Clock Generator Control 8 Synchronization Busy bits"] +pub struct GENCTRL8_R(crate::FieldReader); +impl GENCTRL8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENCTRL8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENCTRL8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchroniation Busy bit"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 2 - Generic Clock Generator Control 0 Synchronization Busy bits"] + #[inline(always)] + pub fn genctrl0(&self) -> GENCTRL0_R { + GENCTRL0_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Generic Clock Generator Control 1 Synchronization Busy bits"] + #[inline(always)] + pub fn genctrl1(&self) -> GENCTRL1_R { + GENCTRL1_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Generic Clock Generator Control 2 Synchronization Busy bits"] + #[inline(always)] + pub fn genctrl2(&self) -> GENCTRL2_R { + GENCTRL2_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Generic Clock Generator Control 3 Synchronization Busy bits"] + #[inline(always)] + pub fn genctrl3(&self) -> GENCTRL3_R { + GENCTRL3_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Generic Clock Generator Control 4 Synchronization Busy bits"] + #[inline(always)] + pub fn genctrl4(&self) -> GENCTRL4_R { + GENCTRL4_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Generic Clock Generator Control 5 Synchronization Busy bits"] + #[inline(always)] + pub fn genctrl5(&self) -> GENCTRL5_R { + GENCTRL5_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Generic Clock Generator Control 6 Synchronization Busy bits"] + #[inline(always)] + pub fn genctrl6(&self) -> GENCTRL6_R { + GENCTRL6_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Generic Clock Generator Control 7 Synchronization Busy bits"] + #[inline(always)] + pub fn genctrl7(&self) -> GENCTRL7_R { + GENCTRL7_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Generic Clock Generator Control 8 Synchronization Busy bits"] + #[inline(always)] + pub fn genctrl8(&self) -> GENCTRL8_R { + GENCTRL8_R::new(((self.bits >> 10) & 0x01) != 0) + } +} +#[doc = "Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/generic.rs b/pac/atsamc21j/src/generic.rs new file mode 100644 index 000000000000..76159643acfa --- /dev/null +++ b/pac/atsamc21j/src/generic.rs @@ -0,0 +1,260 @@ +use core::marker; +#[doc = " Raw register type"] +pub trait RegisterSpec { + #[doc = " Raw register type (`u8`, `u16`, `u32`, ...)."] + type Ux: Copy; +} +#[doc = " Trait implemented by readable registers to enable the `read` method."] +#[doc = ""] +#[doc = " Registers marked with `Writable` can be also `modify`'ed."] +pub trait Readable: RegisterSpec { + #[doc = " Result from a call to `read` and argument to `modify`."] + type Reader: From> + core::ops::Deref>; +} +#[doc = " Trait implemented by writeable registers."] +#[doc = ""] +#[doc = " This enables the `write`, `write_with_zero` and `reset` methods."] +#[doc = ""] +#[doc = " Registers marked with `Readable` can be also `modify`'ed."] +pub trait Writable: RegisterSpec { + #[doc = " Writer type argument to `write`, et al."] + type Writer: From> + core::ops::DerefMut>; +} +#[doc = " Reset value of the register."] +#[doc = ""] +#[doc = " This value is the initial value for the `write` method. It can also be directly written to the"] +#[doc = " register by using the `reset` method."] +pub trait Resettable: RegisterSpec { + #[doc = " Reset value of the register."] + fn reset_value() -> Self::Ux; +} +#[doc = " This structure provides volatile access to registers."] +#[repr(transparent)] +pub struct Reg { + register: vcell::VolatileCell, + _marker: marker::PhantomData, +} +unsafe impl Send for Reg where REG::Ux: Send {} +impl Reg { + #[doc = " Returns the underlying memory address of register."] + #[doc = ""] + #[doc = " ```ignore"] + #[doc = " let reg_ptr = periph.reg.as_ptr();"] + #[doc = " ```"] + #[inline(always)] + pub fn as_ptr(&self) -> *mut REG::Ux { + self.register.as_ptr() + } +} +impl Reg { + #[doc = " Reads the contents of a `Readable` register."] + #[doc = ""] + #[doc = " You can read the raw contents of a register by using `bits`:"] + #[doc = " ```ignore"] + #[doc = " let bits = periph.reg.read().bits();"] + #[doc = " ```"] + #[doc = " or get the content of a particular field of a register:"] + #[doc = " ```ignore"] + #[doc = " let reader = periph.reg.read();"] + #[doc = " let bits = reader.field1().bits();"] + #[doc = " let flag = reader.field2().bit_is_set();"] + #[doc = " ```"] + #[inline(always)] + pub fn read(&self) -> REG::Reader { + REG::Reader::from(R { + bits: self.register.get(), + _reg: marker::PhantomData, + }) + } +} +impl Reg { + #[doc = " Writes the reset value to `Writable` register."] + #[doc = ""] + #[doc = " Resets the register to its initial state."] + #[inline(always)] + pub fn reset(&self) { + self.register.set(REG::reset_value()) + } + #[doc = " Writes bits to a `Writable` register."] + #[doc = ""] + #[doc = " You can write raw bits into a register:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.write(|w| unsafe { w.bits(rawbits) });"] + #[doc = " ```"] + #[doc = " or write only the fields you need:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.write(|w| w"] + #[doc = " .field1().bits(newfield1bits)"] + #[doc = " .field2().set_bit()"] + #[doc = " .field3().variant(VARIANT)"] + #[doc = " );"] + #[doc = " ```"] + #[doc = " In the latter case, other fields will be set to their reset value."] + #[inline(always)] + pub fn write(&self, f: F) + where + F: FnOnce(&mut REG::Writer) -> &mut W, + { + self.register.set( + f(&mut REG::Writer::from(W { + bits: REG::reset_value(), + _reg: marker::PhantomData, + })) + .bits, + ); + } +} +impl Reg +where + REG::Ux: Default, +{ + #[doc = " Writes 0 to a `Writable` register."] + #[doc = ""] + #[doc = " Similar to `write`, but unused bits will contain 0."] + #[inline(always)] + pub unsafe fn write_with_zero(&self, f: F) + where + F: FnOnce(&mut REG::Writer) -> &mut W, + { + self.register.set( + (*f(&mut REG::Writer::from(W { + bits: REG::Ux::default(), + _reg: marker::PhantomData, + }))) + .bits, + ); + } +} +impl Reg { + #[doc = " Modifies the contents of the register by reading and then writing it."] + #[doc = ""] + #[doc = " E.g. to do a read-modify-write sequence to change parts of a register:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.modify(|r, w| unsafe { w.bits("] + #[doc = " r.bits() | 3"] + #[doc = " ) });"] + #[doc = " ```"] + #[doc = " or"] + #[doc = " ```ignore"] + #[doc = " periph.reg.modify(|_, w| w"] + #[doc = " .field1().bits(newfield1bits)"] + #[doc = " .field2().set_bit()"] + #[doc = " .field3().variant(VARIANT)"] + #[doc = " );"] + #[doc = " ```"] + #[doc = " Other fields will have the value they had before the call to `modify`."] + #[inline(always)] + pub fn modify(&self, f: F) + where + for<'w> F: FnOnce(®::Reader, &'w mut REG::Writer) -> &'w mut W, + { + let bits = self.register.get(); + self.register.set( + f( + ®::Reader::from(R { + bits, + _reg: marker::PhantomData, + }), + &mut REG::Writer::from(W { + bits, + _reg: marker::PhantomData, + }), + ) + .bits, + ); + } +} +#[doc = " Register reader."] +#[doc = ""] +#[doc = " Result of the `read` methods of registers. Also used as a closure argument in the `modify`"] +#[doc = " method."] +pub struct R { + pub(crate) bits: REG::Ux, + _reg: marker::PhantomData, +} +impl R { + #[doc = " Reads raw bits from register."] + #[inline(always)] + pub fn bits(&self) -> REG::Ux { + self.bits + } +} +impl PartialEq for R +where + REG::Ux: PartialEq, + FI: Copy + Into, +{ + #[inline(always)] + fn eq(&self, other: &FI) -> bool { + self.bits.eq(&(*other).into()) + } +} +#[doc = " Register writer."] +#[doc = ""] +#[doc = " Used as an argument to the closures in the `write` and `modify` methods of the register."] +pub struct W { + #[doc = "Writable bits"] + pub(crate) bits: REG::Ux, + _reg: marker::PhantomData, +} +impl W { + #[doc = " Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = " Field reader."] +#[doc = ""] +#[doc = " Result of the `read` methods of fields."] +pub struct FieldReader { + pub(crate) bits: U, + _reg: marker::PhantomData, +} +impl FieldReader +where + U: Copy, +{ + #[doc = " Creates a new instance of the reader."] + #[allow(unused)] + #[inline(always)] + pub(crate) fn new(bits: U) -> Self { + Self { + bits, + _reg: marker::PhantomData, + } + } + #[doc = " Reads raw bits from field."] + #[inline(always)] + pub fn bits(&self) -> U { + self.bits + } +} +impl PartialEq for FieldReader +where + U: PartialEq, + FI: Copy + Into, +{ + #[inline(always)] + fn eq(&self, other: &FI) -> bool { + self.bits.eq(&(*other).into()) + } +} +impl FieldReader { + #[doc = " Value of the field as raw bits."] + #[inline(always)] + pub fn bit(&self) -> bool { + self.bits + } + #[doc = " Returns `true` if the bit is clear (0)."] + #[inline(always)] + pub fn bit_is_clear(&self) -> bool { + !self.bit() + } + #[doc = " Returns `true` if the bit is set (1)."] + #[inline(always)] + pub fn bit_is_set(&self) -> bool { + self.bit() + } +} diff --git a/pac/atsamc21j/src/hmatrixhs.rs b/pac/atsamc21j/src/hmatrixhs.rs new file mode 100644 index 000000000000..c8129ac89b6f --- /dev/null +++ b/pac/atsamc21j/src/hmatrixhs.rs @@ -0,0 +1,43 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00..0x40 - Master Configuration"] + pub mcfg: [crate::Reg; 16], + #[doc = "0x40..0x80 - Slave Configuration"] + pub scfg: [crate::Reg; 16], + #[doc = "0x80..0xa0 - PRS\\[%s\\]"] + pub prs: [PRS; 4], + _reserved3: [u8; 0x60], + #[doc = "0x100 - Master Remap Control"] + pub mrcr: crate::Reg, + _reserved4: [u8; 0x0c], + #[doc = "0x110..0x150 - Special Function"] + pub sfr: [crate::Reg; 16], +} +#[doc = r"Register block"] +#[repr(C)] +pub struct PRS { + #[doc = "0x00 - Priority A for Slave"] + pub pras: crate::Reg, + #[doc = "0x04 - Priority B for Slave"] + pub prbs: crate::Reg, +} +#[doc = r"Register block"] +#[doc = "PRS\\[%s\\]"] +pub mod prs; +#[doc = "MCFG register accessor: an alias for `Reg`"] +pub type MCFG = crate::Reg; +#[doc = "Master Configuration"] +pub mod mcfg; +#[doc = "SCFG register accessor: an alias for `Reg`"] +pub type SCFG = crate::Reg; +#[doc = "Slave Configuration"] +pub mod scfg; +#[doc = "MRCR register accessor: an alias for `Reg`"] +pub type MRCR = crate::Reg; +#[doc = "Master Remap Control"] +pub mod mrcr; +#[doc = "SFR register accessor: an alias for `Reg`"] +pub type SFR = crate::Reg; +#[doc = "Special Function"] +pub mod sfr; diff --git a/pac/atsamc21j/src/hmatrixhs/mcfg.rs b/pac/atsamc21j/src/hmatrixhs/mcfg.rs new file mode 100644 index 000000000000..454a39fabe13 --- /dev/null +++ b/pac/atsamc21j/src/hmatrixhs/mcfg.rs @@ -0,0 +1,192 @@ +#[doc = "Register `MCFG[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MCFG[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Undefined Length Burst Type\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum ULBT_A { + #[doc = "0: Infinite Length"] + INFINITE = 0, + #[doc = "1: Single Access"] + SINGLE = 1, + #[doc = "2: Four Beat Burst"] + FOUR_BEAT = 2, + #[doc = "3: Eight Beat Burst"] + EIGHT_BEAT = 3, + #[doc = "4: Sixteen Beat Burst"] + SIXTEEN_BEAT = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: ULBT_A) -> Self { + variant as _ + } +} +#[doc = "Field `ULBT` reader - Undefined Length Burst Type"] +pub struct ULBT_R(crate::FieldReader); +impl ULBT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ULBT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(ULBT_A::INFINITE), + 1 => Some(ULBT_A::SINGLE), + 2 => Some(ULBT_A::FOUR_BEAT), + 3 => Some(ULBT_A::EIGHT_BEAT), + 4 => Some(ULBT_A::SIXTEEN_BEAT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `INFINITE`"] + #[inline(always)] + pub fn is_infinite(&self) -> bool { + **self == ULBT_A::INFINITE + } + #[doc = "Checks if the value of the field is `SINGLE`"] + #[inline(always)] + pub fn is_single(&self) -> bool { + **self == ULBT_A::SINGLE + } + #[doc = "Checks if the value of the field is `FOUR_BEAT`"] + #[inline(always)] + pub fn is_four_beat(&self) -> bool { + **self == ULBT_A::FOUR_BEAT + } + #[doc = "Checks if the value of the field is `EIGHT_BEAT`"] + #[inline(always)] + pub fn is_eight_beat(&self) -> bool { + **self == ULBT_A::EIGHT_BEAT + } + #[doc = "Checks if the value of the field is `SIXTEEN_BEAT`"] + #[inline(always)] + pub fn is_sixteen_beat(&self) -> bool { + **self == ULBT_A::SIXTEEN_BEAT + } +} +impl core::ops::Deref for ULBT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ULBT` writer - Undefined Length Burst Type"] +pub struct ULBT_W<'a> { + w: &'a mut W, +} +impl<'a> ULBT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: ULBT_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Infinite Length"] + #[inline(always)] + pub fn infinite(self) -> &'a mut W { + self.variant(ULBT_A::INFINITE) + } + #[doc = "Single Access"] + #[inline(always)] + pub fn single(self) -> &'a mut W { + self.variant(ULBT_A::SINGLE) + } + #[doc = "Four Beat Burst"] + #[inline(always)] + pub fn four_beat(self) -> &'a mut W { + self.variant(ULBT_A::FOUR_BEAT) + } + #[doc = "Eight Beat Burst"] + #[inline(always)] + pub fn eight_beat(self) -> &'a mut W { + self.variant(ULBT_A::EIGHT_BEAT) + } + #[doc = "Sixteen Beat Burst"] + #[inline(always)] + pub fn sixteen_beat(self) -> &'a mut W { + self.variant(ULBT_A::SIXTEEN_BEAT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Undefined Length Burst Type"] + #[inline(always)] + pub fn ulbt(&self) -> ULBT_R { + ULBT_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Undefined Length Burst Type"] + #[inline(always)] + pub fn ulbt(&mut self) -> ULBT_W { + ULBT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Master Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mcfg](index.html) module"] +pub struct MCFG_SPEC; +impl crate::RegisterSpec for MCFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [mcfg::R](R) reader structure"] +impl crate::Readable for MCFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [mcfg::W](W) writer structure"] +impl crate::Writable for MCFG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets MCFG[%s] +to value 0x02"] +impl crate::Resettable for MCFG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x02 + } +} diff --git a/pac/atsamc21j/src/hmatrixhs/mrcr.rs b/pac/atsamc21j/src/hmatrixhs/mrcr.rs new file mode 100644 index 000000000000..0cf2a1fb01be --- /dev/null +++ b/pac/atsamc21j/src/hmatrixhs/mrcr.rs @@ -0,0 +1,1570 @@ +#[doc = "Register `MRCR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MRCR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Remap Command Bit for Master 0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB0_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB0_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB0` reader - Remap Command Bit for Master 0"] +pub struct RCB0_R(crate::FieldReader); +impl RCB0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB0_A { + match self.bits { + false => RCB0_A::DIS, + true => RCB0_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB0_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB0_A::ENA + } +} +impl core::ops::Deref for RCB0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB0` writer - Remap Command Bit for Master 0"] +pub struct RCB0_W<'a> { + w: &'a mut W, +} +impl<'a> RCB0_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB0_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB0_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB0_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Remap Command Bit for Master 1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB1_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB1_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB1` reader - Remap Command Bit for Master 1"] +pub struct RCB1_R(crate::FieldReader); +impl RCB1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB1_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB1_A { + match self.bits { + false => RCB1_A::DIS, + true => RCB1_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB1_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB1_A::ENA + } +} +impl core::ops::Deref for RCB1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB1` writer - Remap Command Bit for Master 1"] +pub struct RCB1_W<'a> { + w: &'a mut W, +} +impl<'a> RCB1_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB1_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB1_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB1_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Remap Command Bit for Master 2\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB2_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB2_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB2` reader - Remap Command Bit for Master 2"] +pub struct RCB2_R(crate::FieldReader); +impl RCB2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB2_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB2_A { + match self.bits { + false => RCB2_A::DIS, + true => RCB2_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB2_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB2_A::ENA + } +} +impl core::ops::Deref for RCB2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB2` writer - Remap Command Bit for Master 2"] +pub struct RCB2_W<'a> { + w: &'a mut W, +} +impl<'a> RCB2_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB2_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB2_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB2_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Remap Command Bit for Master 3\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB3_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB3_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB3` reader - Remap Command Bit for Master 3"] +pub struct RCB3_R(crate::FieldReader); +impl RCB3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB3_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB3_A { + match self.bits { + false => RCB3_A::DIS, + true => RCB3_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB3_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB3_A::ENA + } +} +impl core::ops::Deref for RCB3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB3` writer - Remap Command Bit for Master 3"] +pub struct RCB3_W<'a> { + w: &'a mut W, +} +impl<'a> RCB3_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB3_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB3_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB3_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Remap Command Bit for Master 4\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB4_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB4_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB4` reader - Remap Command Bit for Master 4"] +pub struct RCB4_R(crate::FieldReader); +impl RCB4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB4_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB4_A { + match self.bits { + false => RCB4_A::DIS, + true => RCB4_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB4_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB4_A::ENA + } +} +impl core::ops::Deref for RCB4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB4` writer - Remap Command Bit for Master 4"] +pub struct RCB4_W<'a> { + w: &'a mut W, +} +impl<'a> RCB4_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB4_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB4_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB4_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Remap Command Bit for Master 5\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB5_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB5_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB5` reader - Remap Command Bit for Master 5"] +pub struct RCB5_R(crate::FieldReader); +impl RCB5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB5_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB5_A { + match self.bits { + false => RCB5_A::DIS, + true => RCB5_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB5_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB5_A::ENA + } +} +impl core::ops::Deref for RCB5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB5` writer - Remap Command Bit for Master 5"] +pub struct RCB5_W<'a> { + w: &'a mut W, +} +impl<'a> RCB5_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB5_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB5_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB5_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Remap Command Bit for Master 6\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB6_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB6_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB6` reader - Remap Command Bit for Master 6"] +pub struct RCB6_R(crate::FieldReader); +impl RCB6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB6_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB6_A { + match self.bits { + false => RCB6_A::DIS, + true => RCB6_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB6_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB6_A::ENA + } +} +impl core::ops::Deref for RCB6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB6` writer - Remap Command Bit for Master 6"] +pub struct RCB6_W<'a> { + w: &'a mut W, +} +impl<'a> RCB6_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB6_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB6_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB6_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Remap Command Bit for Master 7\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB7_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB7_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB7` reader - Remap Command Bit for Master 7"] +pub struct RCB7_R(crate::FieldReader); +impl RCB7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB7_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB7_A { + match self.bits { + false => RCB7_A::DIS, + true => RCB7_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB7_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB7_A::ENA + } +} +impl core::ops::Deref for RCB7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB7` writer - Remap Command Bit for Master 7"] +pub struct RCB7_W<'a> { + w: &'a mut W, +} +impl<'a> RCB7_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB7_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB7_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB7_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Remap Command Bit for Master 8\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB8_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB8_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB8` reader - Remap Command Bit for Master 8"] +pub struct RCB8_R(crate::FieldReader); +impl RCB8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB8_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB8_A { + match self.bits { + false => RCB8_A::DIS, + true => RCB8_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB8_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB8_A::ENA + } +} +impl core::ops::Deref for RCB8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB8` writer - Remap Command Bit for Master 8"] +pub struct RCB8_W<'a> { + w: &'a mut W, +} +impl<'a> RCB8_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB8_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB8_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB8_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Remap Command Bit for Master 9\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB9_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB9_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB9` reader - Remap Command Bit for Master 9"] +pub struct RCB9_R(crate::FieldReader); +impl RCB9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB9_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB9_A { + match self.bits { + false => RCB9_A::DIS, + true => RCB9_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB9_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB9_A::ENA + } +} +impl core::ops::Deref for RCB9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB9` writer - Remap Command Bit for Master 9"] +pub struct RCB9_W<'a> { + w: &'a mut W, +} +impl<'a> RCB9_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB9_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB9_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB9_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Remap Command Bit for Master 10\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB10_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB10_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB10` reader - Remap Command Bit for Master 10"] +pub struct RCB10_R(crate::FieldReader); +impl RCB10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB10_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB10_A { + match self.bits { + false => RCB10_A::DIS, + true => RCB10_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB10_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB10_A::ENA + } +} +impl core::ops::Deref for RCB10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB10` writer - Remap Command Bit for Master 10"] +pub struct RCB10_W<'a> { + w: &'a mut W, +} +impl<'a> RCB10_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB10_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB10_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB10_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Remap Command Bit for Master 11\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB11_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB11_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB11` reader - Remap Command Bit for Master 11"] +pub struct RCB11_R(crate::FieldReader); +impl RCB11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB11_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB11_A { + match self.bits { + false => RCB11_A::DIS, + true => RCB11_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB11_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB11_A::ENA + } +} +impl core::ops::Deref for RCB11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB11` writer - Remap Command Bit for Master 11"] +pub struct RCB11_W<'a> { + w: &'a mut W, +} +impl<'a> RCB11_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB11_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB11_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB11_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Remap Command Bit for Master 12\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB12_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB12_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB12` reader - Remap Command Bit for Master 12"] +pub struct RCB12_R(crate::FieldReader); +impl RCB12_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB12_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB12_A { + match self.bits { + false => RCB12_A::DIS, + true => RCB12_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB12_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB12_A::ENA + } +} +impl core::ops::Deref for RCB12_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB12` writer - Remap Command Bit for Master 12"] +pub struct RCB12_W<'a> { + w: &'a mut W, +} +impl<'a> RCB12_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB12_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB12_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB12_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Remap Command Bit for Master 13\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB13_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB13_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB13` reader - Remap Command Bit for Master 13"] +pub struct RCB13_R(crate::FieldReader); +impl RCB13_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB13_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB13_A { + match self.bits { + false => RCB13_A::DIS, + true => RCB13_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB13_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB13_A::ENA + } +} +impl core::ops::Deref for RCB13_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB13` writer - Remap Command Bit for Master 13"] +pub struct RCB13_W<'a> { + w: &'a mut W, +} +impl<'a> RCB13_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB13_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB13_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB13_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Remap Command Bit for Master 14\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB14_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB14_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB14` reader - Remap Command Bit for Master 14"] +pub struct RCB14_R(crate::FieldReader); +impl RCB14_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB14_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB14_A { + match self.bits { + false => RCB14_A::DIS, + true => RCB14_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB14_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB14_A::ENA + } +} +impl core::ops::Deref for RCB14_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB14` writer - Remap Command Bit for Master 14"] +pub struct RCB14_W<'a> { + w: &'a mut W, +} +impl<'a> RCB14_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB14_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB14_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB14_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Remap Command Bit for Master 15\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB15_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB15_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB15` reader - Remap Command Bit for Master 15"] +pub struct RCB15_R(crate::FieldReader); +impl RCB15_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB15_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB15_A { + match self.bits { + false => RCB15_A::DIS, + true => RCB15_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB15_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB15_A::ENA + } +} +impl core::ops::Deref for RCB15_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB15` writer - Remap Command Bit for Master 15"] +pub struct RCB15_W<'a> { + w: &'a mut W, +} +impl<'a> RCB15_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB15_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB15_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB15_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Remap Command Bit for Master 0"] + #[inline(always)] + pub fn rcb0(&self) -> RCB0_R { + RCB0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Remap Command Bit for Master 1"] + #[inline(always)] + pub fn rcb1(&self) -> RCB1_R { + RCB1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Remap Command Bit for Master 2"] + #[inline(always)] + pub fn rcb2(&self) -> RCB2_R { + RCB2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Remap Command Bit for Master 3"] + #[inline(always)] + pub fn rcb3(&self) -> RCB3_R { + RCB3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Remap Command Bit for Master 4"] + #[inline(always)] + pub fn rcb4(&self) -> RCB4_R { + RCB4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Remap Command Bit for Master 5"] + #[inline(always)] + pub fn rcb5(&self) -> RCB5_R { + RCB5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Remap Command Bit for Master 6"] + #[inline(always)] + pub fn rcb6(&self) -> RCB6_R { + RCB6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Remap Command Bit for Master 7"] + #[inline(always)] + pub fn rcb7(&self) -> RCB7_R { + RCB7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Remap Command Bit for Master 8"] + #[inline(always)] + pub fn rcb8(&self) -> RCB8_R { + RCB8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Remap Command Bit for Master 9"] + #[inline(always)] + pub fn rcb9(&self) -> RCB9_R { + RCB9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Remap Command Bit for Master 10"] + #[inline(always)] + pub fn rcb10(&self) -> RCB10_R { + RCB10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Remap Command Bit for Master 11"] + #[inline(always)] + pub fn rcb11(&self) -> RCB11_R { + RCB11_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Remap Command Bit for Master 12"] + #[inline(always)] + pub fn rcb12(&self) -> RCB12_R { + RCB12_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Remap Command Bit for Master 13"] + #[inline(always)] + pub fn rcb13(&self) -> RCB13_R { + RCB13_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Remap Command Bit for Master 14"] + #[inline(always)] + pub fn rcb14(&self) -> RCB14_R { + RCB14_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Remap Command Bit for Master 15"] + #[inline(always)] + pub fn rcb15(&self) -> RCB15_R { + RCB15_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Remap Command Bit for Master 0"] + #[inline(always)] + pub fn rcb0(&mut self) -> RCB0_W { + RCB0_W { w: self } + } + #[doc = "Bit 1 - Remap Command Bit for Master 1"] + #[inline(always)] + pub fn rcb1(&mut self) -> RCB1_W { + RCB1_W { w: self } + } + #[doc = "Bit 2 - Remap Command Bit for Master 2"] + #[inline(always)] + pub fn rcb2(&mut self) -> RCB2_W { + RCB2_W { w: self } + } + #[doc = "Bit 3 - Remap Command Bit for Master 3"] + #[inline(always)] + pub fn rcb3(&mut self) -> RCB3_W { + RCB3_W { w: self } + } + #[doc = "Bit 4 - Remap Command Bit for Master 4"] + #[inline(always)] + pub fn rcb4(&mut self) -> RCB4_W { + RCB4_W { w: self } + } + #[doc = "Bit 5 - Remap Command Bit for Master 5"] + #[inline(always)] + pub fn rcb5(&mut self) -> RCB5_W { + RCB5_W { w: self } + } + #[doc = "Bit 6 - Remap Command Bit for Master 6"] + #[inline(always)] + pub fn rcb6(&mut self) -> RCB6_W { + RCB6_W { w: self } + } + #[doc = "Bit 7 - Remap Command Bit for Master 7"] + #[inline(always)] + pub fn rcb7(&mut self) -> RCB7_W { + RCB7_W { w: self } + } + #[doc = "Bit 8 - Remap Command Bit for Master 8"] + #[inline(always)] + pub fn rcb8(&mut self) -> RCB8_W { + RCB8_W { w: self } + } + #[doc = "Bit 9 - Remap Command Bit for Master 9"] + #[inline(always)] + pub fn rcb9(&mut self) -> RCB9_W { + RCB9_W { w: self } + } + #[doc = "Bit 10 - Remap Command Bit for Master 10"] + #[inline(always)] + pub fn rcb10(&mut self) -> RCB10_W { + RCB10_W { w: self } + } + #[doc = "Bit 11 - Remap Command Bit for Master 11"] + #[inline(always)] + pub fn rcb11(&mut self) -> RCB11_W { + RCB11_W { w: self } + } + #[doc = "Bit 12 - Remap Command Bit for Master 12"] + #[inline(always)] + pub fn rcb12(&mut self) -> RCB12_W { + RCB12_W { w: self } + } + #[doc = "Bit 13 - Remap Command Bit for Master 13"] + #[inline(always)] + pub fn rcb13(&mut self) -> RCB13_W { + RCB13_W { w: self } + } + #[doc = "Bit 14 - Remap Command Bit for Master 14"] + #[inline(always)] + pub fn rcb14(&mut self) -> RCB14_W { + RCB14_W { w: self } + } + #[doc = "Bit 15 - Remap Command Bit for Master 15"] + #[inline(always)] + pub fn rcb15(&mut self) -> RCB15_W { + RCB15_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Master Remap Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mrcr](index.html) module"] +pub struct MRCR_SPEC; +impl crate::RegisterSpec for MRCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [mrcr::R](R) reader structure"] +impl crate::Readable for MRCR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [mrcr::W](W) writer structure"] +impl crate::Writable for MRCR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets MRCR to value 0"] +impl crate::Resettable for MRCR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/hmatrixhs/prs.rs b/pac/atsamc21j/src/hmatrixhs/prs.rs new file mode 100644 index 000000000000..0313f3c4fc20 --- /dev/null +++ b/pac/atsamc21j/src/hmatrixhs/prs.rs @@ -0,0 +1,8 @@ +#[doc = "PRAS register accessor: an alias for `Reg`"] +pub type PRAS = crate::Reg; +#[doc = "Priority A for Slave"] +pub mod pras; +#[doc = "PRBS register accessor: an alias for `Reg`"] +pub type PRBS = crate::Reg; +#[doc = "Priority B for Slave"] +pub mod prbs; diff --git a/pac/atsamc21j/src/hmatrixhs/prs/pras.rs b/pac/atsamc21j/src/hmatrixhs/prs/pras.rs new file mode 100644 index 000000000000..ac4744a9e2a0 --- /dev/null +++ b/pac/atsamc21j/src/hmatrixhs/prs/pras.rs @@ -0,0 +1,362 @@ +#[doc = "Register `PRAS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PRAS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `M0PR` reader - Master 0 Priority"] +pub struct M0PR_R(crate::FieldReader); +impl M0PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M0PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M0PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M0PR` writer - Master 0 Priority"] +pub struct M0PR_W<'a> { + w: &'a mut W, +} +impl<'a> M0PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Field `M1PR` reader - Master 1 Priority"] +pub struct M1PR_R(crate::FieldReader); +impl M1PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M1PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M1PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M1PR` writer - Master 1 Priority"] +pub struct M1PR_W<'a> { + w: &'a mut W, +} +impl<'a> M1PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 4)) | ((value as u32 & 0x0f) << 4); + self.w + } +} +#[doc = "Field `M2PR` reader - Master 2 Priority"] +pub struct M2PR_R(crate::FieldReader); +impl M2PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M2PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M2PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M2PR` writer - Master 2 Priority"] +pub struct M2PR_W<'a> { + w: &'a mut W, +} +impl<'a> M2PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 8)) | ((value as u32 & 0x0f) << 8); + self.w + } +} +#[doc = "Field `M3PR` reader - Master 3 Priority"] +pub struct M3PR_R(crate::FieldReader); +impl M3PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M3PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M3PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M3PR` writer - Master 3 Priority"] +pub struct M3PR_W<'a> { + w: &'a mut W, +} +impl<'a> M3PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 12)) | ((value as u32 & 0x0f) << 12); + self.w + } +} +#[doc = "Field `M4PR` reader - Master 4 Priority"] +pub struct M4PR_R(crate::FieldReader); +impl M4PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M4PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M4PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M4PR` writer - Master 4 Priority"] +pub struct M4PR_W<'a> { + w: &'a mut W, +} +impl<'a> M4PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 16)) | ((value as u32 & 0x0f) << 16); + self.w + } +} +#[doc = "Field `M5PR` reader - Master 5 Priority"] +pub struct M5PR_R(crate::FieldReader); +impl M5PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M5PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M5PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M5PR` writer - Master 5 Priority"] +pub struct M5PR_W<'a> { + w: &'a mut W, +} +impl<'a> M5PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 20)) | ((value as u32 & 0x0f) << 20); + self.w + } +} +#[doc = "Field `M6PR` reader - Master 6 Priority"] +pub struct M6PR_R(crate::FieldReader); +impl M6PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M6PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M6PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M6PR` writer - Master 6 Priority"] +pub struct M6PR_W<'a> { + w: &'a mut W, +} +impl<'a> M6PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Field `M7PR` reader - Master 7 Priority"] +pub struct M7PR_R(crate::FieldReader); +impl M7PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M7PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M7PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M7PR` writer - Master 7 Priority"] +pub struct M7PR_W<'a> { + w: &'a mut W, +} +impl<'a> M7PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 28)) | ((value as u32 & 0x0f) << 28); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Master 0 Priority"] + #[inline(always)] + pub fn m0pr(&self) -> M0PR_R { + M0PR_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Master 1 Priority"] + #[inline(always)] + pub fn m1pr(&self) -> M1PR_R { + M1PR_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 8:11 - Master 2 Priority"] + #[inline(always)] + pub fn m2pr(&self) -> M2PR_R { + M2PR_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - Master 3 Priority"] + #[inline(always)] + pub fn m3pr(&self) -> M3PR_R { + M3PR_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:19 - Master 4 Priority"] + #[inline(always)] + pub fn m4pr(&self) -> M4PR_R { + M4PR_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bits 20:23 - Master 5 Priority"] + #[inline(always)] + pub fn m5pr(&self) -> M5PR_R { + M5PR_R::new(((self.bits >> 20) & 0x0f) as u8) + } + #[doc = "Bits 24:27 - Master 6 Priority"] + #[inline(always)] + pub fn m6pr(&self) -> M6PR_R { + M6PR_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bits 28:31 - Master 7 Priority"] + #[inline(always)] + pub fn m7pr(&self) -> M7PR_R { + M7PR_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Master 0 Priority"] + #[inline(always)] + pub fn m0pr(&mut self) -> M0PR_W { + M0PR_W { w: self } + } + #[doc = "Bits 4:7 - Master 1 Priority"] + #[inline(always)] + pub fn m1pr(&mut self) -> M1PR_W { + M1PR_W { w: self } + } + #[doc = "Bits 8:11 - Master 2 Priority"] + #[inline(always)] + pub fn m2pr(&mut self) -> M2PR_W { + M2PR_W { w: self } + } + #[doc = "Bits 12:15 - Master 3 Priority"] + #[inline(always)] + pub fn m3pr(&mut self) -> M3PR_W { + M3PR_W { w: self } + } + #[doc = "Bits 16:19 - Master 4 Priority"] + #[inline(always)] + pub fn m4pr(&mut self) -> M4PR_W { + M4PR_W { w: self } + } + #[doc = "Bits 20:23 - Master 5 Priority"] + #[inline(always)] + pub fn m5pr(&mut self) -> M5PR_W { + M5PR_W { w: self } + } + #[doc = "Bits 24:27 - Master 6 Priority"] + #[inline(always)] + pub fn m6pr(&mut self) -> M6PR_W { + M6PR_W { w: self } + } + #[doc = "Bits 28:31 - Master 7 Priority"] + #[inline(always)] + pub fn m7pr(&mut self) -> M7PR_W { + M7PR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Priority A for Slave\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pras](index.html) module"] +pub struct PRAS_SPEC; +impl crate::RegisterSpec for PRAS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pras::R](R) reader structure"] +impl crate::Readable for PRAS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [pras::W](W) writer structure"] +impl crate::Writable for PRAS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PRAS to value 0"] +impl crate::Resettable for PRAS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/hmatrixhs/prs/prbs.rs b/pac/atsamc21j/src/hmatrixhs/prs/prbs.rs new file mode 100644 index 000000000000..a2cc6bb9f6b0 --- /dev/null +++ b/pac/atsamc21j/src/hmatrixhs/prs/prbs.rs @@ -0,0 +1,362 @@ +#[doc = "Register `PRBS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PRBS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `M8PR` reader - Master 8 Priority"] +pub struct M8PR_R(crate::FieldReader); +impl M8PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M8PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M8PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M8PR` writer - Master 8 Priority"] +pub struct M8PR_W<'a> { + w: &'a mut W, +} +impl<'a> M8PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Field `M9PR` reader - Master 9 Priority"] +pub struct M9PR_R(crate::FieldReader); +impl M9PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M9PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M9PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M9PR` writer - Master 9 Priority"] +pub struct M9PR_W<'a> { + w: &'a mut W, +} +impl<'a> M9PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 4)) | ((value as u32 & 0x0f) << 4); + self.w + } +} +#[doc = "Field `M10PR` reader - Master 10 Priority"] +pub struct M10PR_R(crate::FieldReader); +impl M10PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M10PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M10PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M10PR` writer - Master 10 Priority"] +pub struct M10PR_W<'a> { + w: &'a mut W, +} +impl<'a> M10PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 8)) | ((value as u32 & 0x0f) << 8); + self.w + } +} +#[doc = "Field `M11PR` reader - Master 11 Priority"] +pub struct M11PR_R(crate::FieldReader); +impl M11PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M11PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M11PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M11PR` writer - Master 11 Priority"] +pub struct M11PR_W<'a> { + w: &'a mut W, +} +impl<'a> M11PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 12)) | ((value as u32 & 0x0f) << 12); + self.w + } +} +#[doc = "Field `M12PR` reader - Master 12 Priority"] +pub struct M12PR_R(crate::FieldReader); +impl M12PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M12PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M12PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M12PR` writer - Master 12 Priority"] +pub struct M12PR_W<'a> { + w: &'a mut W, +} +impl<'a> M12PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 16)) | ((value as u32 & 0x0f) << 16); + self.w + } +} +#[doc = "Field `M13PR` reader - Master 13 Priority"] +pub struct M13PR_R(crate::FieldReader); +impl M13PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M13PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M13PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M13PR` writer - Master 13 Priority"] +pub struct M13PR_W<'a> { + w: &'a mut W, +} +impl<'a> M13PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 20)) | ((value as u32 & 0x0f) << 20); + self.w + } +} +#[doc = "Field `M14PR` reader - Master 14 Priority"] +pub struct M14PR_R(crate::FieldReader); +impl M14PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M14PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M14PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M14PR` writer - Master 14 Priority"] +pub struct M14PR_W<'a> { + w: &'a mut W, +} +impl<'a> M14PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Field `M15PR` reader - Master 15 Priority"] +pub struct M15PR_R(crate::FieldReader); +impl M15PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M15PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M15PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M15PR` writer - Master 15 Priority"] +pub struct M15PR_W<'a> { + w: &'a mut W, +} +impl<'a> M15PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 28)) | ((value as u32 & 0x0f) << 28); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Master 8 Priority"] + #[inline(always)] + pub fn m8pr(&self) -> M8PR_R { + M8PR_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Master 9 Priority"] + #[inline(always)] + pub fn m9pr(&self) -> M9PR_R { + M9PR_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 8:11 - Master 10 Priority"] + #[inline(always)] + pub fn m10pr(&self) -> M10PR_R { + M10PR_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - Master 11 Priority"] + #[inline(always)] + pub fn m11pr(&self) -> M11PR_R { + M11PR_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:19 - Master 12 Priority"] + #[inline(always)] + pub fn m12pr(&self) -> M12PR_R { + M12PR_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bits 20:23 - Master 13 Priority"] + #[inline(always)] + pub fn m13pr(&self) -> M13PR_R { + M13PR_R::new(((self.bits >> 20) & 0x0f) as u8) + } + #[doc = "Bits 24:27 - Master 14 Priority"] + #[inline(always)] + pub fn m14pr(&self) -> M14PR_R { + M14PR_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bits 28:31 - Master 15 Priority"] + #[inline(always)] + pub fn m15pr(&self) -> M15PR_R { + M15PR_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Master 8 Priority"] + #[inline(always)] + pub fn m8pr(&mut self) -> M8PR_W { + M8PR_W { w: self } + } + #[doc = "Bits 4:7 - Master 9 Priority"] + #[inline(always)] + pub fn m9pr(&mut self) -> M9PR_W { + M9PR_W { w: self } + } + #[doc = "Bits 8:11 - Master 10 Priority"] + #[inline(always)] + pub fn m10pr(&mut self) -> M10PR_W { + M10PR_W { w: self } + } + #[doc = "Bits 12:15 - Master 11 Priority"] + #[inline(always)] + pub fn m11pr(&mut self) -> M11PR_W { + M11PR_W { w: self } + } + #[doc = "Bits 16:19 - Master 12 Priority"] + #[inline(always)] + pub fn m12pr(&mut self) -> M12PR_W { + M12PR_W { w: self } + } + #[doc = "Bits 20:23 - Master 13 Priority"] + #[inline(always)] + pub fn m13pr(&mut self) -> M13PR_W { + M13PR_W { w: self } + } + #[doc = "Bits 24:27 - Master 14 Priority"] + #[inline(always)] + pub fn m14pr(&mut self) -> M14PR_W { + M14PR_W { w: self } + } + #[doc = "Bits 28:31 - Master 15 Priority"] + #[inline(always)] + pub fn m15pr(&mut self) -> M15PR_W { + M15PR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Priority B for Slave\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [prbs](index.html) module"] +pub struct PRBS_SPEC; +impl crate::RegisterSpec for PRBS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [prbs::R](R) reader structure"] +impl crate::Readable for PRBS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [prbs::W](W) writer structure"] +impl crate::Writable for PRBS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PRBS to value 0"] +impl crate::Resettable for PRBS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/hmatrixhs/scfg.rs b/pac/atsamc21j/src/hmatrixhs/scfg.rs new file mode 100644 index 000000000000..7180c043195a --- /dev/null +++ b/pac/atsamc21j/src/hmatrixhs/scfg.rs @@ -0,0 +1,334 @@ +#[doc = "Register `SCFG[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SCFG[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SLOT_CYCLE` reader - Maximum Number of Allowed Cycles for a Burst"] +pub struct SLOT_CYCLE_R(crate::FieldReader); +impl SLOT_CYCLE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SLOT_CYCLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SLOT_CYCLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLOT_CYCLE` writer - Maximum Number of Allowed Cycles for a Burst"] +pub struct SLOT_CYCLE_W<'a> { + w: &'a mut W, +} +impl<'a> SLOT_CYCLE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +#[doc = "Default Master Type\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DEFMSTR_TYPE_A { + #[doc = "0: No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst."] + NO_DEFAULT = 0, + #[doc = "1: Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave."] + LAST_DEFAULT = 1, + #[doc = "2: Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave."] + FIXED_DEFAULT = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DEFMSTR_TYPE_A) -> Self { + variant as _ + } +} +#[doc = "Field `DEFMSTR_TYPE` reader - Default Master Type"] +pub struct DEFMSTR_TYPE_R(crate::FieldReader); +impl DEFMSTR_TYPE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DEFMSTR_TYPE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(DEFMSTR_TYPE_A::NO_DEFAULT), + 1 => Some(DEFMSTR_TYPE_A::LAST_DEFAULT), + 2 => Some(DEFMSTR_TYPE_A::FIXED_DEFAULT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NO_DEFAULT`"] + #[inline(always)] + pub fn is_no_default(&self) -> bool { + **self == DEFMSTR_TYPE_A::NO_DEFAULT + } + #[doc = "Checks if the value of the field is `LAST_DEFAULT`"] + #[inline(always)] + pub fn is_last_default(&self) -> bool { + **self == DEFMSTR_TYPE_A::LAST_DEFAULT + } + #[doc = "Checks if the value of the field is `FIXED_DEFAULT`"] + #[inline(always)] + pub fn is_fixed_default(&self) -> bool { + **self == DEFMSTR_TYPE_A::FIXED_DEFAULT + } +} +impl core::ops::Deref for DEFMSTR_TYPE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DEFMSTR_TYPE` writer - Default Master Type"] +pub struct DEFMSTR_TYPE_W<'a> { + w: &'a mut W, +} +impl<'a> DEFMSTR_TYPE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DEFMSTR_TYPE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst."] + #[inline(always)] + pub fn no_default(self) -> &'a mut W { + self.variant(DEFMSTR_TYPE_A::NO_DEFAULT) + } + #[doc = "Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave."] + #[inline(always)] + pub fn last_default(self) -> &'a mut W { + self.variant(DEFMSTR_TYPE_A::LAST_DEFAULT) + } + #[doc = "Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave."] + #[inline(always)] + pub fn fixed_default(self) -> &'a mut W { + self.variant(DEFMSTR_TYPE_A::FIXED_DEFAULT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Field `FIXED_DEFMSTR` reader - Fixed Index of Default Master"] +pub struct FIXED_DEFMSTR_R(crate::FieldReader); +impl FIXED_DEFMSTR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FIXED_DEFMSTR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FIXED_DEFMSTR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FIXED_DEFMSTR` writer - Fixed Index of Default Master"] +pub struct FIXED_DEFMSTR_W<'a> { + w: &'a mut W, +} +impl<'a> FIXED_DEFMSTR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 18)) | ((value as u32 & 0x0f) << 18); + self.w + } +} +#[doc = "Arbitration Type\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ARBT_A { + #[doc = "0: Round-Robin Arbitration"] + ROUND_ROBIN = 0, + #[doc = "1: Fixed Priority Arbitration"] + FIXED_PRIORITY = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ARBT_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ARBT` reader - Arbitration Type"] +pub struct ARBT_R(crate::FieldReader); +impl ARBT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ARBT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ARBT_A { + match self.bits { + false => ARBT_A::ROUND_ROBIN, + true => ARBT_A::FIXED_PRIORITY, + } + } + #[doc = "Checks if the value of the field is `ROUND_ROBIN`"] + #[inline(always)] + pub fn is_round_robin(&self) -> bool { + **self == ARBT_A::ROUND_ROBIN + } + #[doc = "Checks if the value of the field is `FIXED_PRIORITY`"] + #[inline(always)] + pub fn is_fixed_priority(&self) -> bool { + **self == ARBT_A::FIXED_PRIORITY + } +} +impl core::ops::Deref for ARBT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ARBT` writer - Arbitration Type"] +pub struct ARBT_W<'a> { + w: &'a mut W, +} +impl<'a> ARBT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: ARBT_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Round-Robin Arbitration"] + #[inline(always)] + pub fn round_robin(self) -> &'a mut W { + self.variant(ARBT_A::ROUND_ROBIN) + } + #[doc = "Fixed Priority Arbitration"] + #[inline(always)] + pub fn fixed_priority(self) -> &'a mut W { + self.variant(ARBT_A::FIXED_PRIORITY) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Maximum Number of Allowed Cycles for a Burst"] + #[inline(always)] + pub fn slot_cycle(&self) -> SLOT_CYCLE_R { + SLOT_CYCLE_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 16:17 - Default Master Type"] + #[inline(always)] + pub fn defmstr_type(&self) -> DEFMSTR_TYPE_R { + DEFMSTR_TYPE_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bits 18:21 - Fixed Index of Default Master"] + #[inline(always)] + pub fn fixed_defmstr(&self) -> FIXED_DEFMSTR_R { + FIXED_DEFMSTR_R::new(((self.bits >> 18) & 0x0f) as u8) + } + #[doc = "Bit 24 - Arbitration Type"] + #[inline(always)] + pub fn arbt(&self) -> ARBT_R { + ARBT_R::new(((self.bits >> 24) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - Maximum Number of Allowed Cycles for a Burst"] + #[inline(always)] + pub fn slot_cycle(&mut self) -> SLOT_CYCLE_W { + SLOT_CYCLE_W { w: self } + } + #[doc = "Bits 16:17 - Default Master Type"] + #[inline(always)] + pub fn defmstr_type(&mut self) -> DEFMSTR_TYPE_W { + DEFMSTR_TYPE_W { w: self } + } + #[doc = "Bits 18:21 - Fixed Index of Default Master"] + #[inline(always)] + pub fn fixed_defmstr(&mut self) -> FIXED_DEFMSTR_W { + FIXED_DEFMSTR_W { w: self } + } + #[doc = "Bit 24 - Arbitration Type"] + #[inline(always)] + pub fn arbt(&mut self) -> ARBT_W { + ARBT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Slave Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [scfg](index.html) module"] +pub struct SCFG_SPEC; +impl crate::RegisterSpec for SCFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [scfg::R](R) reader structure"] +impl crate::Readable for SCFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [scfg::W](W) writer structure"] +impl crate::Writable for SCFG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SCFG[%s] +to value 0x10"] +impl crate::Resettable for SCFG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x10 + } +} diff --git a/pac/atsamc21j/src/hmatrixhs/sfr.rs b/pac/atsamc21j/src/hmatrixhs/sfr.rs new file mode 100644 index 000000000000..0a7e024f73c8 --- /dev/null +++ b/pac/atsamc21j/src/hmatrixhs/sfr.rs @@ -0,0 +1,104 @@ +#[doc = "Register `SFR[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SFR[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SFR` reader - Special Function Register"] +pub struct SFR_R(crate::FieldReader); +impl SFR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + SFR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SFR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SFR` writer - Special Function Register"] +pub struct SFR_W<'a> { + w: &'a mut W, +} +impl<'a> SFR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Special Function Register"] + #[inline(always)] + pub fn sfr(&self) -> SFR_R { + SFR_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Special Function Register"] + #[inline(always)] + pub fn sfr(&mut self) -> SFR_W { + SFR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Special Function\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sfr](index.html) module"] +pub struct SFR_SPEC; +impl crate::RegisterSpec for SFR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [sfr::R](R) reader structure"] +impl crate::Readable for SFR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [sfr::W](W) writer structure"] +impl crate::Writable for SFR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SFR[%s] +to value 0"] +impl crate::Resettable for SFR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/lib.rs b/pac/atsamc21j/src/lib.rs new file mode 100644 index 000000000000..412239d74d35 --- /dev/null +++ b/pac/atsamc21j/src/lib.rs @@ -0,0 +1,1725 @@ +#![doc = "Peripheral access API for ATSAMC21J microcontrollers (generated using svd2rust v0.20.0 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] +svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.20.0/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"] +#![deny(const_err)] +#![deny(dead_code)] +#![deny(improper_ctypes)] +#![deny(missing_docs)] +#![deny(no_mangle_generic_items)] +#![deny(non_shorthand_field_patterns)] +#![deny(overflowing_literals)] +#![deny(path_statements)] +#![deny(patterns_in_fns_without_body)] +#![deny(private_in_public)] +#![deny(unconditional_recursion)] +#![deny(unused_allocation)] +#![deny(unused_comparisons)] +#![deny(unused_parens)] +#![deny(while_true)] +#![allow(non_camel_case_types)] +#![allow(non_snake_case)] +#![allow(clippy::all)] +#![no_std] +use core::marker::PhantomData; +use core::ops::Deref; +#[doc = r"Number available in the NVIC for configuring priority"] +pub const NVIC_PRIO_BITS: u8 = 2; +#[cfg(feature = "rt")] +pub use self::Interrupt as interrupt; +pub use cortex_m::peripheral::Peripherals as CorePeripherals; +pub use cortex_m::peripheral::{CBP, CPUID, DCB, DWT, FPB, ITM, MPU, NVIC, SCB, SYST, TPIU}; +#[cfg(feature = "rt")] +pub use cortex_m_rt::interrupt; +#[allow(unused_imports)] +use generic::*; +#[doc = r"Common register and bit access and modify traits"] +pub mod generic; +#[cfg(feature = "rt")] +extern "C" { + fn WDT(); + fn RTC(); + fn EIC(); + fn FREQM(); + fn TSENS(); + fn NVMCTRL(); + fn DMAC(); + fn EVSYS(); + fn SERCOM0(); + fn SERCOM1(); + fn SERCOM2(); + fn SERCOM3(); + fn SERCOM4(); + fn SERCOM5(); + fn CAN0(); + fn CAN1(); + fn TCC0(); + fn TCC1(); + fn TCC2(); + fn TC0(); + fn TC1(); + fn TC2(); + fn TC3(); + fn TC4(); + fn ADC0(); + fn ADC1(); + fn AC(); + fn DAC(); + fn SDADC(); + fn PTC(); +} +#[doc(hidden)] +pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, +} +#[cfg(feature = "rt")] +#[doc(hidden)] +#[link_section = ".vector_table.interrupts"] +#[no_mangle] +pub static __INTERRUPTS: [Vector; 31] = [ + Vector { _reserved: 0 }, + Vector { _handler: WDT }, + Vector { _handler: RTC }, + Vector { _handler: EIC }, + Vector { _handler: FREQM }, + Vector { _handler: TSENS }, + Vector { _handler: NVMCTRL }, + Vector { _handler: DMAC }, + Vector { _handler: EVSYS }, + Vector { _handler: SERCOM0 }, + Vector { _handler: SERCOM1 }, + Vector { _handler: SERCOM2 }, + Vector { _handler: SERCOM3 }, + Vector { _handler: SERCOM4 }, + Vector { _handler: SERCOM5 }, + Vector { _handler: CAN0 }, + Vector { _handler: CAN1 }, + Vector { _handler: TCC0 }, + Vector { _handler: TCC1 }, + Vector { _handler: TCC2 }, + Vector { _handler: TC0 }, + Vector { _handler: TC1 }, + Vector { _handler: TC2 }, + Vector { _handler: TC3 }, + Vector { _handler: TC4 }, + Vector { _handler: ADC0 }, + Vector { _handler: ADC1 }, + Vector { _handler: AC }, + Vector { _handler: DAC }, + Vector { _handler: SDADC }, + Vector { _handler: PTC }, +]; +#[doc = r"Enumeration of all the interrupts."] +#[derive(Copy, Clone, Debug, PartialEq, Eq)] +#[repr(u16)] +pub enum Interrupt { + #[doc = "1 - WDT"] + WDT = 1, + #[doc = "2 - RTC"] + RTC = 2, + #[doc = "3 - EIC"] + EIC = 3, + #[doc = "4 - FREQM"] + FREQM = 4, + #[doc = "5 - TSENS"] + TSENS = 5, + #[doc = "6 - NVMCTRL"] + NVMCTRL = 6, + #[doc = "7 - DMAC"] + DMAC = 7, + #[doc = "8 - EVSYS"] + EVSYS = 8, + #[doc = "9 - SERCOM0"] + SERCOM0 = 9, + #[doc = "10 - SERCOM1"] + SERCOM1 = 10, + #[doc = "11 - SERCOM2"] + SERCOM2 = 11, + #[doc = "12 - SERCOM3"] + SERCOM3 = 12, + #[doc = "13 - SERCOM4"] + SERCOM4 = 13, + #[doc = "14 - SERCOM5"] + SERCOM5 = 14, + #[doc = "15 - CAN0"] + CAN0 = 15, + #[doc = "16 - CAN1"] + CAN1 = 16, + #[doc = "17 - TCC0"] + TCC0 = 17, + #[doc = "18 - TCC1"] + TCC1 = 18, + #[doc = "19 - TCC2"] + TCC2 = 19, + #[doc = "20 - TC0"] + TC0 = 20, + #[doc = "21 - TC1"] + TC1 = 21, + #[doc = "22 - TC2"] + TC2 = 22, + #[doc = "23 - TC3"] + TC3 = 23, + #[doc = "24 - TC4"] + TC4 = 24, + #[doc = "25 - ADC0"] + ADC0 = 25, + #[doc = "26 - ADC1"] + ADC1 = 26, + #[doc = "27 - AC"] + AC = 27, + #[doc = "28 - DAC"] + DAC = 28, + #[doc = "29 - SDADC"] + SDADC = 29, + #[doc = "30 - PTC"] + PTC = 30, +} +unsafe impl cortex_m::interrupt::InterruptNumber for Interrupt { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } +} +#[doc = "Analog Comparators"] +pub struct AC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for AC {} +impl AC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const ac::RegisterBlock = 0x4200_5000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const ac::RegisterBlock { + Self::PTR + } +} +impl Deref for AC { + type Target = ac::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for AC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AC").finish() + } +} +#[doc = "Analog Comparators"] +pub mod ac; +#[doc = "Analog Digital Converter"] +pub struct ADC0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for ADC0 {} +impl ADC0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const adc0::RegisterBlock = 0x4200_4400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const adc0::RegisterBlock { + Self::PTR + } +} +impl Deref for ADC0 { + type Target = adc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for ADC0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ADC0").finish() + } +} +#[doc = "Analog Digital Converter"] +pub mod adc0; +#[doc = "Analog Digital Converter"] +pub struct ADC1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for ADC1 {} +impl ADC1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const adc0::RegisterBlock = 0x4200_4800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const adc0::RegisterBlock { + Self::PTR + } +} +impl Deref for ADC1 { + type Target = adc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for ADC1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ADC1").finish() + } +} +#[doc = "Analog Digital Converter"] +pub use adc0 as adc1; +#[doc = "Control Area Network"] +pub struct CAN0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for CAN0 {} +impl CAN0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const can0::RegisterBlock = 0x4200_1c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const can0::RegisterBlock { + Self::PTR + } +} +impl Deref for CAN0 { + type Target = can0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for CAN0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CAN0").finish() + } +} +#[doc = "Control Area Network"] +pub mod can0; +#[doc = "Control Area Network"] +pub struct CAN1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for CAN1 {} +impl CAN1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const can0::RegisterBlock = 0x4200_2000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const can0::RegisterBlock { + Self::PTR + } +} +impl Deref for CAN1 { + type Target = can0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for CAN1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CAN1").finish() + } +} +#[doc = "Control Area Network"] +pub use can0 as can1; +#[doc = "Configurable Custom Logic"] +pub struct CCL { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for CCL {} +impl CCL { + #[doc = r"Pointer to the register block"] + pub const PTR: *const ccl::RegisterBlock = 0x4200_5c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const ccl::RegisterBlock { + Self::PTR + } +} +impl Deref for CCL { + type Target = ccl::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for CCL { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CCL").finish() + } +} +#[doc = "Configurable Custom Logic"] +pub mod ccl; +#[doc = "Digital Analog Converter"] +pub struct DAC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for DAC {} +impl DAC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const dac::RegisterBlock = 0x4200_5400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const dac::RegisterBlock { + Self::PTR + } +} +impl Deref for DAC { + type Target = dac::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for DAC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DAC").finish() + } +} +#[doc = "Digital Analog Converter"] +pub mod dac; +#[doc = "Divide and Square Root Accelerator"] +pub struct DIVAS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for DIVAS {} +impl DIVAS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const divas::RegisterBlock = 0x4800_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const divas::RegisterBlock { + Self::PTR + } +} +impl Deref for DIVAS { + type Target = divas::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for DIVAS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DIVAS").finish() + } +} +#[doc = "Divide and Square Root Accelerator"] +pub mod divas; +#[doc = "Direct Memory Access Controller"] +pub struct DMAC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for DMAC {} +impl DMAC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const dmac::RegisterBlock = 0x4100_6000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const dmac::RegisterBlock { + Self::PTR + } +} +impl Deref for DMAC { + type Target = dmac::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for DMAC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DMAC").finish() + } +} +#[doc = "Direct Memory Access Controller"] +pub mod dmac; +#[doc = "Device Service Unit"] +pub struct DSU { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for DSU {} +impl DSU { + #[doc = r"Pointer to the register block"] + pub const PTR: *const dsu::RegisterBlock = 0x4100_2000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const dsu::RegisterBlock { + Self::PTR + } +} +impl Deref for DSU { + type Target = dsu::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for DSU { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DSU").finish() + } +} +#[doc = "Device Service Unit"] +pub mod dsu; +#[doc = "External Interrupt Controller"] +pub struct EIC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for EIC {} +impl EIC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const eic::RegisterBlock = 0x4000_2800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const eic::RegisterBlock { + Self::PTR + } +} +impl Deref for EIC { + type Target = eic::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for EIC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EIC").finish() + } +} +#[doc = "External Interrupt Controller"] +pub mod eic; +#[doc = "Event System Interface"] +pub struct EVSYS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for EVSYS {} +impl EVSYS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const evsys::RegisterBlock = 0x4200_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const evsys::RegisterBlock { + Self::PTR + } +} +impl Deref for EVSYS { + type Target = evsys::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for EVSYS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EVSYS").finish() + } +} +#[doc = "Event System Interface"] +pub mod evsys; +#[doc = "Frequency Meter"] +pub struct FREQM { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for FREQM {} +impl FREQM { + #[doc = r"Pointer to the register block"] + pub const PTR: *const freqm::RegisterBlock = 0x4000_2c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const freqm::RegisterBlock { + Self::PTR + } +} +impl Deref for FREQM { + type Target = freqm::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for FREQM { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FREQM").finish() + } +} +#[doc = "Frequency Meter"] +pub mod freqm; +#[doc = "Generic Clock Generator"] +pub struct GCLK { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for GCLK {} +impl GCLK { + #[doc = r"Pointer to the register block"] + pub const PTR: *const gclk::RegisterBlock = 0x4000_1c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const gclk::RegisterBlock { + Self::PTR + } +} +impl Deref for GCLK { + type Target = gclk::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for GCLK { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GCLK").finish() + } +} +#[doc = "Generic Clock Generator"] +pub mod gclk; +#[doc = "HSB Matrix"] +pub struct HMATRIXHS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for HMATRIXHS {} +impl HMATRIXHS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const hmatrixhs::RegisterBlock = 0x4100_a000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const hmatrixhs::RegisterBlock { + Self::PTR + } +} +impl Deref for HMATRIXHS { + type Target = hmatrixhs::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for HMATRIXHS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HMATRIXHS").finish() + } +} +#[doc = "HSB Matrix"] +pub mod hmatrixhs; +#[doc = "Main Clock"] +pub struct MCLK { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for MCLK {} +impl MCLK { + #[doc = r"Pointer to the register block"] + pub const PTR: *const mclk::RegisterBlock = 0x4000_0800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const mclk::RegisterBlock { + Self::PTR + } +} +impl Deref for MCLK { + type Target = mclk::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for MCLK { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MCLK").finish() + } +} +#[doc = "Main Clock"] +pub mod mclk; +#[doc = "Cortex-M0+ Micro-Trace Buffer"] +pub struct MTB { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for MTB {} +impl MTB { + #[doc = r"Pointer to the register block"] + pub const PTR: *const mtb::RegisterBlock = 0x4100_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const mtb::RegisterBlock { + Self::PTR + } +} +impl Deref for MTB { + type Target = mtb::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for MTB { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MTB").finish() + } +} +#[doc = "Cortex-M0+ Micro-Trace Buffer"] +pub mod mtb; +#[doc = "Non-Volatile Memory Controller"] +pub struct NVMCTRL { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for NVMCTRL {} +impl NVMCTRL { + #[doc = r"Pointer to the register block"] + pub const PTR: *const nvmctrl::RegisterBlock = 0x4100_4000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const nvmctrl::RegisterBlock { + Self::PTR + } +} +impl Deref for NVMCTRL { + type Target = nvmctrl::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for NVMCTRL { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("NVMCTRL").finish() + } +} +#[doc = "Non-Volatile Memory Controller"] +pub mod nvmctrl; +#[doc = "Oscillators Control"] +pub struct OSCCTRL { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for OSCCTRL {} +impl OSCCTRL { + #[doc = r"Pointer to the register block"] + pub const PTR: *const oscctrl::RegisterBlock = 0x4000_1000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const oscctrl::RegisterBlock { + Self::PTR + } +} +impl Deref for OSCCTRL { + type Target = oscctrl::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for OSCCTRL { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OSCCTRL").finish() + } +} +#[doc = "Oscillators Control"] +pub mod oscctrl; +#[doc = "32k Oscillators Control"] +pub struct OSC32KCTRL { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for OSC32KCTRL {} +impl OSC32KCTRL { + #[doc = r"Pointer to the register block"] + pub const PTR: *const osc32kctrl::RegisterBlock = 0x4000_1400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const osc32kctrl::RegisterBlock { + Self::PTR + } +} +impl Deref for OSC32KCTRL { + type Target = osc32kctrl::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for OSC32KCTRL { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OSC32KCTRL").finish() + } +} +#[doc = "32k Oscillators Control"] +pub mod osc32kctrl; +#[doc = "Peripheral Access Controller"] +pub struct PAC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PAC {} +impl PAC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const pac::RegisterBlock = 0x4000_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const pac::RegisterBlock { + Self::PTR + } +} +impl Deref for PAC { + type Target = pac::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PAC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PAC").finish() + } +} +#[doc = "Peripheral Access Controller"] +pub mod pac; +#[doc = "Power Manager"] +pub struct PM { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PM {} +impl PM { + #[doc = r"Pointer to the register block"] + pub const PTR: *const pm::RegisterBlock = 0x4000_0400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const pm::RegisterBlock { + Self::PTR + } +} +impl Deref for PM { + type Target = pm::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PM { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PM").finish() + } +} +#[doc = "Power Manager"] +pub mod pm; +#[doc = "Port Module"] +pub struct PORT { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PORT {} +impl PORT { + #[doc = r"Pointer to the register block"] + pub const PTR: *const port::RegisterBlock = 0x4100_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const port::RegisterBlock { + Self::PTR + } +} +impl Deref for PORT { + type Target = port::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PORT { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PORT").finish() + } +} +#[doc = "Port Module"] +pub mod port; +#[doc = "Port Module"] +pub struct PORT_IOBUS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PORT_IOBUS {} +impl PORT_IOBUS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const port::RegisterBlock = 0x6000_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const port::RegisterBlock { + Self::PTR + } +} +impl Deref for PORT_IOBUS { + type Target = port::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PORT_IOBUS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PORT_IOBUS").finish() + } +} +#[doc = "Port Module"] +pub use port as port_iobus; +#[doc = "Reset Controller"] +pub struct RSTC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for RSTC {} +impl RSTC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const rstc::RegisterBlock = 0x4000_0c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const rstc::RegisterBlock { + Self::PTR + } +} +impl Deref for RSTC { + type Target = rstc::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for RSTC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RSTC").finish() + } +} +#[doc = "Reset Controller"] +pub mod rstc; +#[doc = "Real-Time Counter"] +pub struct RTC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for RTC {} +impl RTC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const rtc::RegisterBlock = 0x4000_2400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const rtc::RegisterBlock { + Self::PTR + } +} +impl Deref for RTC { + type Target = rtc::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for RTC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RTC").finish() + } +} +#[doc = "Real-Time Counter"] +pub mod rtc; +#[doc = "Sigma-Delta Analog Digital Converter"] +pub struct SDADC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SDADC {} +impl SDADC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sdadc::RegisterBlock = 0x4200_4c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sdadc::RegisterBlock { + Self::PTR + } +} +impl Deref for SDADC { + type Target = sdadc::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SDADC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SDADC").finish() + } +} +#[doc = "Sigma-Delta Analog Digital Converter"] +pub mod sdadc; +#[doc = "Serial Communication Interface"] +pub struct SERCOM0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SERCOM0 {} +impl SERCOM0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sercom0::RegisterBlock = 0x4200_0400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sercom0::RegisterBlock { + Self::PTR + } +} +impl Deref for SERCOM0 { + type Target = sercom0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SERCOM0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SERCOM0").finish() + } +} +#[doc = "Serial Communication Interface"] +pub mod sercom0; +#[doc = "Serial Communication Interface"] +pub struct SERCOM1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SERCOM1 {} +impl SERCOM1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sercom0::RegisterBlock = 0x4200_0800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sercom0::RegisterBlock { + Self::PTR + } +} +impl Deref for SERCOM1 { + type Target = sercom0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SERCOM1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SERCOM1").finish() + } +} +#[doc = "Serial Communication Interface"] +pub use sercom0 as sercom1; +#[doc = "Serial Communication Interface"] +pub struct SERCOM2 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SERCOM2 {} +impl SERCOM2 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sercom0::RegisterBlock = 0x4200_0c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sercom0::RegisterBlock { + Self::PTR + } +} +impl Deref for SERCOM2 { + type Target = sercom0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SERCOM2 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SERCOM2").finish() + } +} +#[doc = "Serial Communication Interface"] +pub use sercom0 as sercom2; +#[doc = "Serial Communication Interface"] +pub struct SERCOM3 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SERCOM3 {} +impl SERCOM3 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sercom0::RegisterBlock = 0x4200_1000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sercom0::RegisterBlock { + Self::PTR + } +} +impl Deref for SERCOM3 { + type Target = sercom0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SERCOM3 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SERCOM3").finish() + } +} +#[doc = "Serial Communication Interface"] +pub use sercom0 as sercom3; +#[doc = "Serial Communication Interface"] +pub struct SERCOM4 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SERCOM4 {} +impl SERCOM4 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sercom0::RegisterBlock = 0x4200_1400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sercom0::RegisterBlock { + Self::PTR + } +} +impl Deref for SERCOM4 { + type Target = sercom0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SERCOM4 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SERCOM4").finish() + } +} +#[doc = "Serial Communication Interface"] +pub use sercom0 as sercom4; +#[doc = "Serial Communication Interface"] +pub struct SERCOM5 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SERCOM5 {} +impl SERCOM5 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sercom0::RegisterBlock = 0x4200_1800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sercom0::RegisterBlock { + Self::PTR + } +} +impl Deref for SERCOM5 { + type Target = sercom0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SERCOM5 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SERCOM5").finish() + } +} +#[doc = "Serial Communication Interface"] +pub use sercom0 as sercom5; +#[doc = "Supply Controller"] +pub struct SUPC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SUPC {} +impl SUPC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const supc::RegisterBlock = 0x4000_1800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const supc::RegisterBlock { + Self::PTR + } +} +impl Deref for SUPC { + type Target = supc::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SUPC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SUPC").finish() + } +} +#[doc = "Supply Controller"] +pub mod supc; +#[doc = "Basic Timer Counter"] +pub struct TC0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TC0 {} +impl TC0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tc0::RegisterBlock = 0x4200_3000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tc0::RegisterBlock { + Self::PTR + } +} +impl Deref for TC0 { + type Target = tc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TC0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TC0").finish() + } +} +#[doc = "Basic Timer Counter"] +pub mod tc0; +#[doc = "Basic Timer Counter"] +pub struct TC1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TC1 {} +impl TC1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tc0::RegisterBlock = 0x4200_3400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tc0::RegisterBlock { + Self::PTR + } +} +impl Deref for TC1 { + type Target = tc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TC1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TC1").finish() + } +} +#[doc = "Basic Timer Counter"] +pub use tc0 as tc1; +#[doc = "Basic Timer Counter"] +pub struct TC2 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TC2 {} +impl TC2 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tc0::RegisterBlock = 0x4200_3800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tc0::RegisterBlock { + Self::PTR + } +} +impl Deref for TC2 { + type Target = tc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TC2 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TC2").finish() + } +} +#[doc = "Basic Timer Counter"] +pub use tc0 as tc2; +#[doc = "Basic Timer Counter"] +pub struct TC3 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TC3 {} +impl TC3 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tc0::RegisterBlock = 0x4200_3c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tc0::RegisterBlock { + Self::PTR + } +} +impl Deref for TC3 { + type Target = tc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TC3 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TC3").finish() + } +} +#[doc = "Basic Timer Counter"] +pub use tc0 as tc3; +#[doc = "Basic Timer Counter"] +pub struct TC4 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TC4 {} +impl TC4 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tc0::RegisterBlock = 0x4200_4000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tc0::RegisterBlock { + Self::PTR + } +} +impl Deref for TC4 { + type Target = tc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TC4 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TC4").finish() + } +} +#[doc = "Basic Timer Counter"] +pub use tc0 as tc4; +#[doc = "Timer Counter Control"] +pub struct TCC0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TCC0 {} +impl TCC0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tcc0::RegisterBlock = 0x4200_2400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tcc0::RegisterBlock { + Self::PTR + } +} +impl Deref for TCC0 { + type Target = tcc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TCC0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TCC0").finish() + } +} +#[doc = "Timer Counter Control"] +pub mod tcc0; +#[doc = "Timer Counter Control"] +pub struct TCC1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TCC1 {} +impl TCC1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tcc0::RegisterBlock = 0x4200_2800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tcc0::RegisterBlock { + Self::PTR + } +} +impl Deref for TCC1 { + type Target = tcc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TCC1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TCC1").finish() + } +} +#[doc = "Timer Counter Control"] +pub use tcc0 as tcc1; +#[doc = "Timer Counter Control"] +pub struct TCC2 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TCC2 {} +impl TCC2 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tcc0::RegisterBlock = 0x4200_2c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tcc0::RegisterBlock { + Self::PTR + } +} +impl Deref for TCC2 { + type Target = tcc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TCC2 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TCC2").finish() + } +} +#[doc = "Timer Counter Control"] +pub use tcc0 as tcc2; +#[doc = "Temperature Sensor"] +pub struct TSENS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TSENS {} +impl TSENS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tsens::RegisterBlock = 0x4000_3000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tsens::RegisterBlock { + Self::PTR + } +} +impl Deref for TSENS { + type Target = tsens::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TSENS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TSENS").finish() + } +} +#[doc = "Temperature Sensor"] +pub mod tsens; +#[doc = "Watchdog Timer"] +pub struct WDT { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for WDT {} +impl WDT { + #[doc = r"Pointer to the register block"] + pub const PTR: *const wdt::RegisterBlock = 0x4000_2000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const wdt::RegisterBlock { + Self::PTR + } +} +impl Deref for WDT { + type Target = wdt::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for WDT { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("WDT").finish() + } +} +#[doc = "Watchdog Timer"] +pub mod wdt; +#[doc = "System timer"] +pub struct SYSTICK { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SYSTICK {} +impl SYSTICK { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sys_tick::RegisterBlock = 0xe000_e010 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sys_tick::RegisterBlock { + Self::PTR + } +} +impl Deref for SYSTICK { + type Target = sys_tick::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SYSTICK { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SYSTICK").finish() + } +} +#[doc = "System timer"] +pub mod sys_tick; +#[doc = "System Control Registers"] +pub struct SYSTEMCONTROL { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SYSTEMCONTROL {} +impl SYSTEMCONTROL { + #[doc = r"Pointer to the register block"] + pub const PTR: *const system_control::RegisterBlock = 0xe000_e000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const system_control::RegisterBlock { + Self::PTR + } +} +impl Deref for SYSTEMCONTROL { + type Target = system_control::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SYSTEMCONTROL { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SYSTEMCONTROL").finish() + } +} +#[doc = "System Control Registers"] +pub mod system_control; +#[no_mangle] +static mut DEVICE_PERIPHERALS: bool = false; +#[doc = r"All the peripherals"] +#[allow(non_snake_case)] +pub struct Peripherals { + #[doc = "AC"] + pub AC: AC, + #[doc = "ADC0"] + pub ADC0: ADC0, + #[doc = "ADC1"] + pub ADC1: ADC1, + #[doc = "CAN0"] + pub CAN0: CAN0, + #[doc = "CAN1"] + pub CAN1: CAN1, + #[doc = "CCL"] + pub CCL: CCL, + #[doc = "DAC"] + pub DAC: DAC, + #[doc = "DIVAS"] + pub DIVAS: DIVAS, + #[doc = "DMAC"] + pub DMAC: DMAC, + #[doc = "DSU"] + pub DSU: DSU, + #[doc = "EIC"] + pub EIC: EIC, + #[doc = "EVSYS"] + pub EVSYS: EVSYS, + #[doc = "FREQM"] + pub FREQM: FREQM, + #[doc = "GCLK"] + pub GCLK: GCLK, + #[doc = "HMATRIXHS"] + pub HMATRIXHS: HMATRIXHS, + #[doc = "MCLK"] + pub MCLK: MCLK, + #[doc = "MTB"] + pub MTB: MTB, + #[doc = "NVMCTRL"] + pub NVMCTRL: NVMCTRL, + #[doc = "OSCCTRL"] + pub OSCCTRL: OSCCTRL, + #[doc = "OSC32KCTRL"] + pub OSC32KCTRL: OSC32KCTRL, + #[doc = "PAC"] + pub PAC: PAC, + #[doc = "PM"] + pub PM: PM, + #[doc = "PORT"] + pub PORT: PORT, + #[doc = "PORT_IOBUS"] + pub PORT_IOBUS: PORT_IOBUS, + #[doc = "RSTC"] + pub RSTC: RSTC, + #[doc = "RTC"] + pub RTC: RTC, + #[doc = "SDADC"] + pub SDADC: SDADC, + #[doc = "SERCOM0"] + pub SERCOM0: SERCOM0, + #[doc = "SERCOM1"] + pub SERCOM1: SERCOM1, + #[doc = "SERCOM2"] + pub SERCOM2: SERCOM2, + #[doc = "SERCOM3"] + pub SERCOM3: SERCOM3, + #[doc = "SERCOM4"] + pub SERCOM4: SERCOM4, + #[doc = "SERCOM5"] + pub SERCOM5: SERCOM5, + #[doc = "SUPC"] + pub SUPC: SUPC, + #[doc = "TC0"] + pub TC0: TC0, + #[doc = "TC1"] + pub TC1: TC1, + #[doc = "TC2"] + pub TC2: TC2, + #[doc = "TC3"] + pub TC3: TC3, + #[doc = "TC4"] + pub TC4: TC4, + #[doc = "TCC0"] + pub TCC0: TCC0, + #[doc = "TCC1"] + pub TCC1: TCC1, + #[doc = "TCC2"] + pub TCC2: TCC2, + #[doc = "TSENS"] + pub TSENS: TSENS, + #[doc = "WDT"] + pub WDT: WDT, + #[doc = "SYSTICK"] + pub SYSTICK: SYSTICK, + #[doc = "SYSTEMCONTROL"] + pub SYSTEMCONTROL: SYSTEMCONTROL, +} +impl Peripherals { + #[doc = r"Returns all the peripherals *once*"] + #[inline] + pub fn take() -> Option { + cortex_m::interrupt::free(|_| { + if unsafe { DEVICE_PERIPHERALS } { + None + } else { + Some(unsafe { Peripherals::steal() }) + } + }) + } + #[doc = r"Unchecked version of `Peripherals::take`"] + #[inline] + pub unsafe fn steal() -> Self { + DEVICE_PERIPHERALS = true; + Peripherals { + AC: AC { + _marker: PhantomData, + }, + ADC0: ADC0 { + _marker: PhantomData, + }, + ADC1: ADC1 { + _marker: PhantomData, + }, + CAN0: CAN0 { + _marker: PhantomData, + }, + CAN1: CAN1 { + _marker: PhantomData, + }, + CCL: CCL { + _marker: PhantomData, + }, + DAC: DAC { + _marker: PhantomData, + }, + DIVAS: DIVAS { + _marker: PhantomData, + }, + DMAC: DMAC { + _marker: PhantomData, + }, + DSU: DSU { + _marker: PhantomData, + }, + EIC: EIC { + _marker: PhantomData, + }, + EVSYS: EVSYS { + _marker: PhantomData, + }, + FREQM: FREQM { + _marker: PhantomData, + }, + GCLK: GCLK { + _marker: PhantomData, + }, + HMATRIXHS: HMATRIXHS { + _marker: PhantomData, + }, + MCLK: MCLK { + _marker: PhantomData, + }, + MTB: MTB { + _marker: PhantomData, + }, + NVMCTRL: NVMCTRL { + _marker: PhantomData, + }, + OSCCTRL: OSCCTRL { + _marker: PhantomData, + }, + OSC32KCTRL: OSC32KCTRL { + _marker: PhantomData, + }, + PAC: PAC { + _marker: PhantomData, + }, + PM: PM { + _marker: PhantomData, + }, + PORT: PORT { + _marker: PhantomData, + }, + PORT_IOBUS: PORT_IOBUS { + _marker: PhantomData, + }, + RSTC: RSTC { + _marker: PhantomData, + }, + RTC: RTC { + _marker: PhantomData, + }, + SDADC: SDADC { + _marker: PhantomData, + }, + SERCOM0: SERCOM0 { + _marker: PhantomData, + }, + SERCOM1: SERCOM1 { + _marker: PhantomData, + }, + SERCOM2: SERCOM2 { + _marker: PhantomData, + }, + SERCOM3: SERCOM3 { + _marker: PhantomData, + }, + SERCOM4: SERCOM4 { + _marker: PhantomData, + }, + SERCOM5: SERCOM5 { + _marker: PhantomData, + }, + SUPC: SUPC { + _marker: PhantomData, + }, + TC0: TC0 { + _marker: PhantomData, + }, + TC1: TC1 { + _marker: PhantomData, + }, + TC2: TC2 { + _marker: PhantomData, + }, + TC3: TC3 { + _marker: PhantomData, + }, + TC4: TC4 { + _marker: PhantomData, + }, + TCC0: TCC0 { + _marker: PhantomData, + }, + TCC1: TCC1 { + _marker: PhantomData, + }, + TCC2: TCC2 { + _marker: PhantomData, + }, + TSENS: TSENS { + _marker: PhantomData, + }, + WDT: WDT { + _marker: PhantomData, + }, + SYSTICK: SYSTICK { + _marker: PhantomData, + }, + SYSTEMCONTROL: SYSTEMCONTROL { + _marker: PhantomData, + }, + } + } +} diff --git a/pac/atsamc21j/src/mclk.rs b/pac/atsamc21j/src/mclk.rs new file mode 100644 index 000000000000..fc7efe3a584e --- /dev/null +++ b/pac/atsamc21j/src/mclk.rs @@ -0,0 +1,54 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved0: [u8; 0x01], + #[doc = "0x01 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x02 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x03 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x04 - CPU Clock Division"] + pub cpudiv: crate::Reg, + _reserved4: [u8; 0x0b], + #[doc = "0x10 - AHB Mask"] + pub ahbmask: crate::Reg, + #[doc = "0x14 - APBA Mask"] + pub apbamask: crate::Reg, + #[doc = "0x18 - APBB Mask"] + pub apbbmask: crate::Reg, + #[doc = "0x1c - APBC Mask"] + pub apbcmask: crate::Reg, +} +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "CPUDIV register accessor: an alias for `Reg`"] +pub type CPUDIV = crate::Reg; +#[doc = "CPU Clock Division"] +pub mod cpudiv; +#[doc = "AHBMASK register accessor: an alias for `Reg`"] +pub type AHBMASK = crate::Reg; +#[doc = "AHB Mask"] +pub mod ahbmask; +#[doc = "APBAMASK register accessor: an alias for `Reg`"] +pub type APBAMASK = crate::Reg; +#[doc = "APBA Mask"] +pub mod apbamask; +#[doc = "APBBMASK register accessor: an alias for `Reg`"] +pub type APBBMASK = crate::Reg; +#[doc = "APBB Mask"] +pub mod apbbmask; +#[doc = "APBCMASK register accessor: an alias for `Reg`"] +pub type APBCMASK = crate::Reg; +#[doc = "APBC Mask"] +pub mod apbcmask; diff --git a/pac/atsamc21j/src/mclk/ahbmask.rs b/pac/atsamc21j/src/mclk/ahbmask.rs new file mode 100644 index 000000000000..1e21340e0b11 --- /dev/null +++ b/pac/atsamc21j/src/mclk/ahbmask.rs @@ -0,0 +1,677 @@ +#[doc = "Register `AHBMASK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `AHBMASK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `HPB0_` reader - HPB0 AHB Clock Mask"] +pub struct HPB0__R(crate::FieldReader); +impl HPB0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HPB0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HPB0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HPB0_` writer - HPB0 AHB Clock Mask"] +pub struct HPB0__W<'a> { + w: &'a mut W, +} +impl<'a> HPB0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `HPB1_` reader - HPB1 AHB Clock Mask"] +pub struct HPB1__R(crate::FieldReader); +impl HPB1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HPB1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HPB1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HPB1_` writer - HPB1 AHB Clock Mask"] +pub struct HPB1__W<'a> { + w: &'a mut W, +} +impl<'a> HPB1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `HPB2_` reader - HPB2 AHB Clock Mask"] +pub struct HPB2__R(crate::FieldReader); +impl HPB2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HPB2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HPB2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HPB2_` writer - HPB2 AHB Clock Mask"] +pub struct HPB2__W<'a> { + w: &'a mut W, +} +impl<'a> HPB2__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `DSU_` reader - DSU AHB Clock Mask"] +pub struct DSU__R(crate::FieldReader); +impl DSU__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DSU__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DSU__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DSU_` writer - DSU AHB Clock Mask"] +pub struct DSU__W<'a> { + w: &'a mut W, +} +impl<'a> DSU__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `HMATRIXHS_` reader - HMATRIXHS AHB Clock Mask"] +pub struct HMATRIXHS__R(crate::FieldReader); +impl HMATRIXHS__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HMATRIXHS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HMATRIXHS__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HMATRIXHS_` writer - HMATRIXHS AHB Clock Mask"] +pub struct HMATRIXHS__W<'a> { + w: &'a mut W, +} +impl<'a> HMATRIXHS__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `NVMCTRL_` reader - NVMCTRL AHB Clock Mask"] +pub struct NVMCTRL__R(crate::FieldReader); +impl NVMCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NVMCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NVMCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NVMCTRL_` writer - NVMCTRL AHB Clock Mask"] +pub struct NVMCTRL__W<'a> { + w: &'a mut W, +} +impl<'a> NVMCTRL__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `HSRAM_` reader - HSRAM AHB Clock Mask"] +pub struct HSRAM__R(crate::FieldReader); +impl HSRAM__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HSRAM__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HSRAM__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HSRAM_` writer - HSRAM AHB Clock Mask"] +pub struct HSRAM__W<'a> { + w: &'a mut W, +} +impl<'a> HSRAM__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `DMAC_` reader - DMAC AHB Clock Mask"] +pub struct DMAC__R(crate::FieldReader); +impl DMAC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DMAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DMAC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DMAC_` writer - DMAC AHB Clock Mask"] +pub struct DMAC__W<'a> { + w: &'a mut W, +} +impl<'a> DMAC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CAN0_` reader - CAN0 AHB Clock Mask"] +pub struct CAN0__R(crate::FieldReader); +impl CAN0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CAN0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CAN0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAN0_` writer - CAN0 AHB Clock Mask"] +pub struct CAN0__W<'a> { + w: &'a mut W, +} +impl<'a> CAN0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `CAN1_` reader - CAN1 AHB Clock Mask"] +pub struct CAN1__R(crate::FieldReader); +impl CAN1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CAN1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CAN1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAN1_` writer - CAN1 AHB Clock Mask"] +pub struct CAN1__W<'a> { + w: &'a mut W, +} +impl<'a> CAN1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `PAC_` reader - PAC AHB Clock Mask"] +pub struct PAC__R(crate::FieldReader); +impl PAC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PAC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PAC_` writer - PAC AHB Clock Mask"] +pub struct PAC__W<'a> { + w: &'a mut W, +} +impl<'a> PAC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `NVMCTRL_PICACHU_` reader - NVMCTRL_PICACHU AHB Clock Mask"] +pub struct NVMCTRL_PICACHU__R(crate::FieldReader); +impl NVMCTRL_PICACHU__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NVMCTRL_PICACHU__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NVMCTRL_PICACHU__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NVMCTRL_PICACHU_` writer - NVMCTRL_PICACHU AHB Clock Mask"] +pub struct NVMCTRL_PICACHU__W<'a> { + w: &'a mut W, +} +impl<'a> NVMCTRL_PICACHU__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `DIVAS_` reader - DIVAS AHB Clock Mask"] +pub struct DIVAS__R(crate::FieldReader); +impl DIVAS__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIVAS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIVAS__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIVAS_` writer - DIVAS AHB Clock Mask"] +pub struct DIVAS__W<'a> { + w: &'a mut W, +} +impl<'a> DIVAS__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +impl R { + #[doc = "Bit 0 - HPB0 AHB Clock Mask"] + #[inline(always)] + pub fn hpb0_(&self) -> HPB0__R { + HPB0__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - HPB1 AHB Clock Mask"] + #[inline(always)] + pub fn hpb1_(&self) -> HPB1__R { + HPB1__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - HPB2 AHB Clock Mask"] + #[inline(always)] + pub fn hpb2_(&self) -> HPB2__R { + HPB2__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - DSU AHB Clock Mask"] + #[inline(always)] + pub fn dsu_(&self) -> DSU__R { + DSU__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - HMATRIXHS AHB Clock Mask"] + #[inline(always)] + pub fn hmatrixhs_(&self) -> HMATRIXHS__R { + HMATRIXHS__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - NVMCTRL AHB Clock Mask"] + #[inline(always)] + pub fn nvmctrl_(&self) -> NVMCTRL__R { + NVMCTRL__R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - HSRAM AHB Clock Mask"] + #[inline(always)] + pub fn hsram_(&self) -> HSRAM__R { + HSRAM__R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - DMAC AHB Clock Mask"] + #[inline(always)] + pub fn dmac_(&self) -> DMAC__R { + DMAC__R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - CAN0 AHB Clock Mask"] + #[inline(always)] + pub fn can0_(&self) -> CAN0__R { + CAN0__R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - CAN1 AHB Clock Mask"] + #[inline(always)] + pub fn can1_(&self) -> CAN1__R { + CAN1__R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - PAC AHB Clock Mask"] + #[inline(always)] + pub fn pac_(&self) -> PAC__R { + PAC__R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - NVMCTRL_PICACHU AHB Clock Mask"] + #[inline(always)] + pub fn nvmctrl_picachu_(&self) -> NVMCTRL_PICACHU__R { + NVMCTRL_PICACHU__R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - DIVAS AHB Clock Mask"] + #[inline(always)] + pub fn divas_(&self) -> DIVAS__R { + DIVAS__R::new(((self.bits >> 12) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - HPB0 AHB Clock Mask"] + #[inline(always)] + pub fn hpb0_(&mut self) -> HPB0__W { + HPB0__W { w: self } + } + #[doc = "Bit 1 - HPB1 AHB Clock Mask"] + #[inline(always)] + pub fn hpb1_(&mut self) -> HPB1__W { + HPB1__W { w: self } + } + #[doc = "Bit 2 - HPB2 AHB Clock Mask"] + #[inline(always)] + pub fn hpb2_(&mut self) -> HPB2__W { + HPB2__W { w: self } + } + #[doc = "Bit 3 - DSU AHB Clock Mask"] + #[inline(always)] + pub fn dsu_(&mut self) -> DSU__W { + DSU__W { w: self } + } + #[doc = "Bit 4 - HMATRIXHS AHB Clock Mask"] + #[inline(always)] + pub fn hmatrixhs_(&mut self) -> HMATRIXHS__W { + HMATRIXHS__W { w: self } + } + #[doc = "Bit 5 - NVMCTRL AHB Clock Mask"] + #[inline(always)] + pub fn nvmctrl_(&mut self) -> NVMCTRL__W { + NVMCTRL__W { w: self } + } + #[doc = "Bit 6 - HSRAM AHB Clock Mask"] + #[inline(always)] + pub fn hsram_(&mut self) -> HSRAM__W { + HSRAM__W { w: self } + } + #[doc = "Bit 7 - DMAC AHB Clock Mask"] + #[inline(always)] + pub fn dmac_(&mut self) -> DMAC__W { + DMAC__W { w: self } + } + #[doc = "Bit 8 - CAN0 AHB Clock Mask"] + #[inline(always)] + pub fn can0_(&mut self) -> CAN0__W { + CAN0__W { w: self } + } + #[doc = "Bit 9 - CAN1 AHB Clock Mask"] + #[inline(always)] + pub fn can1_(&mut self) -> CAN1__W { + CAN1__W { w: self } + } + #[doc = "Bit 10 - PAC AHB Clock Mask"] + #[inline(always)] + pub fn pac_(&mut self) -> PAC__W { + PAC__W { w: self } + } + #[doc = "Bit 11 - NVMCTRL_PICACHU AHB Clock Mask"] + #[inline(always)] + pub fn nvmctrl_picachu_(&mut self) -> NVMCTRL_PICACHU__W { + NVMCTRL_PICACHU__W { w: self } + } + #[doc = "Bit 12 - DIVAS AHB Clock Mask"] + #[inline(always)] + pub fn divas_(&mut self) -> DIVAS__W { + DIVAS__W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "AHB Mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ahbmask](index.html) module"] +pub struct AHBMASK_SPEC; +impl crate::RegisterSpec for AHBMASK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ahbmask::R](R) reader structure"] +impl crate::Readable for AHBMASK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ahbmask::W](W) writer structure"] +impl crate::Writable for AHBMASK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets AHBMASK to value 0x1cff"] +impl crate::Resettable for AHBMASK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x1cff + } +} diff --git a/pac/atsamc21j/src/mclk/apbamask.rs b/pac/atsamc21j/src/mclk/apbamask.rs new file mode 100644 index 000000000000..144b1163d5cb --- /dev/null +++ b/pac/atsamc21j/src/mclk/apbamask.rs @@ -0,0 +1,677 @@ +#[doc = "Register `APBAMASK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `APBAMASK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PAC_` reader - PAC APB Clock Enable"] +pub struct PAC__R(crate::FieldReader); +impl PAC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PAC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PAC_` writer - PAC APB Clock Enable"] +pub struct PAC__W<'a> { + w: &'a mut W, +} +impl<'a> PAC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `PM_` reader - PM APB Clock Enable"] +pub struct PM__R(crate::FieldReader); +impl PM__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PM__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PM__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PM_` writer - PM APB Clock Enable"] +pub struct PM__W<'a> { + w: &'a mut W, +} +impl<'a> PM__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MCLK_` reader - MCLK APB Clock Enable"] +pub struct MCLK__R(crate::FieldReader); +impl MCLK__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCLK__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCLK__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCLK_` writer - MCLK APB Clock Enable"] +pub struct MCLK__W<'a> { + w: &'a mut W, +} +impl<'a> MCLK__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RSTC_` reader - RSTC APB Clock Enable"] +pub struct RSTC__R(crate::FieldReader); +impl RSTC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RSTC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RSTC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RSTC_` writer - RSTC APB Clock Enable"] +pub struct RSTC__W<'a> { + w: &'a mut W, +} +impl<'a> RSTC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `OSCCTRL_` reader - OSCCTRL APB Clock Enable"] +pub struct OSCCTRL__R(crate::FieldReader); +impl OSCCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSCCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSCCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSCCTRL_` writer - OSCCTRL APB Clock Enable"] +pub struct OSCCTRL__W<'a> { + w: &'a mut W, +} +impl<'a> OSCCTRL__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `OSC32KCTRL_` reader - OSC32KCTRL APB Clock Enable"] +pub struct OSC32KCTRL__R(crate::FieldReader); +impl OSC32KCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC32KCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC32KCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC32KCTRL_` writer - OSC32KCTRL APB Clock Enable"] +pub struct OSC32KCTRL__W<'a> { + w: &'a mut W, +} +impl<'a> OSC32KCTRL__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `SUPC_` reader - SUPC APB Clock Enable"] +pub struct SUPC__R(crate::FieldReader); +impl SUPC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SUPC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SUPC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SUPC_` writer - SUPC APB Clock Enable"] +pub struct SUPC__W<'a> { + w: &'a mut W, +} +impl<'a> SUPC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `GCLK_` reader - GCLK APB Clock Enable"] +pub struct GCLK__R(crate::FieldReader); +impl GCLK__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GCLK__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GCLK__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GCLK_` writer - GCLK APB Clock Enable"] +pub struct GCLK__W<'a> { + w: &'a mut W, +} +impl<'a> GCLK__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `WDT_` reader - WDT APB Clock Enable"] +pub struct WDT__R(crate::FieldReader); +impl WDT__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WDT__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WDT__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WDT_` writer - WDT APB Clock Enable"] +pub struct WDT__W<'a> { + w: &'a mut W, +} +impl<'a> WDT__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `RTC_` reader - RTC APB Clock Enable"] +pub struct RTC__R(crate::FieldReader); +impl RTC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RTC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RTC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RTC_` writer - RTC APB Clock Enable"] +pub struct RTC__W<'a> { + w: &'a mut W, +} +impl<'a> RTC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `EIC_` reader - EIC APB Clock Enable"] +pub struct EIC__R(crate::FieldReader); +impl EIC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EIC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EIC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EIC_` writer - EIC APB Clock Enable"] +pub struct EIC__W<'a> { + w: &'a mut W, +} +impl<'a> EIC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `FREQM_` reader - FREQM APB Clock Enable"] +pub struct FREQM__R(crate::FieldReader); +impl FREQM__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FREQM__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FREQM__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FREQM_` writer - FREQM APB Clock Enable"] +pub struct FREQM__W<'a> { + w: &'a mut W, +} +impl<'a> FREQM__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `TSENS_` reader - TSENS APB Clock Enable"] +pub struct TSENS__R(crate::FieldReader); +impl TSENS__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSENS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSENS__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSENS_` writer - TSENS APB Clock Enable"] +pub struct TSENS__W<'a> { + w: &'a mut W, +} +impl<'a> TSENS__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +impl R { + #[doc = "Bit 0 - PAC APB Clock Enable"] + #[inline(always)] + pub fn pac_(&self) -> PAC__R { + PAC__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - PM APB Clock Enable"] + #[inline(always)] + pub fn pm_(&self) -> PM__R { + PM__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - MCLK APB Clock Enable"] + #[inline(always)] + pub fn mclk_(&self) -> MCLK__R { + MCLK__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - RSTC APB Clock Enable"] + #[inline(always)] + pub fn rstc_(&self) -> RSTC__R { + RSTC__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - OSCCTRL APB Clock Enable"] + #[inline(always)] + pub fn oscctrl_(&self) -> OSCCTRL__R { + OSCCTRL__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - OSC32KCTRL APB Clock Enable"] + #[inline(always)] + pub fn osc32kctrl_(&self) -> OSC32KCTRL__R { + OSC32KCTRL__R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - SUPC APB Clock Enable"] + #[inline(always)] + pub fn supc_(&self) -> SUPC__R { + SUPC__R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - GCLK APB Clock Enable"] + #[inline(always)] + pub fn gclk_(&self) -> GCLK__R { + GCLK__R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - WDT APB Clock Enable"] + #[inline(always)] + pub fn wdt_(&self) -> WDT__R { + WDT__R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - RTC APB Clock Enable"] + #[inline(always)] + pub fn rtc_(&self) -> RTC__R { + RTC__R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - EIC APB Clock Enable"] + #[inline(always)] + pub fn eic_(&self) -> EIC__R { + EIC__R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - FREQM APB Clock Enable"] + #[inline(always)] + pub fn freqm_(&self) -> FREQM__R { + FREQM__R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - TSENS APB Clock Enable"] + #[inline(always)] + pub fn tsens_(&self) -> TSENS__R { + TSENS__R::new(((self.bits >> 12) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - PAC APB Clock Enable"] + #[inline(always)] + pub fn pac_(&mut self) -> PAC__W { + PAC__W { w: self } + } + #[doc = "Bit 1 - PM APB Clock Enable"] + #[inline(always)] + pub fn pm_(&mut self) -> PM__W { + PM__W { w: self } + } + #[doc = "Bit 2 - MCLK APB Clock Enable"] + #[inline(always)] + pub fn mclk_(&mut self) -> MCLK__W { + MCLK__W { w: self } + } + #[doc = "Bit 3 - RSTC APB Clock Enable"] + #[inline(always)] + pub fn rstc_(&mut self) -> RSTC__W { + RSTC__W { w: self } + } + #[doc = "Bit 4 - OSCCTRL APB Clock Enable"] + #[inline(always)] + pub fn oscctrl_(&mut self) -> OSCCTRL__W { + OSCCTRL__W { w: self } + } + #[doc = "Bit 5 - OSC32KCTRL APB Clock Enable"] + #[inline(always)] + pub fn osc32kctrl_(&mut self) -> OSC32KCTRL__W { + OSC32KCTRL__W { w: self } + } + #[doc = "Bit 6 - SUPC APB Clock Enable"] + #[inline(always)] + pub fn supc_(&mut self) -> SUPC__W { + SUPC__W { w: self } + } + #[doc = "Bit 7 - GCLK APB Clock Enable"] + #[inline(always)] + pub fn gclk_(&mut self) -> GCLK__W { + GCLK__W { w: self } + } + #[doc = "Bit 8 - WDT APB Clock Enable"] + #[inline(always)] + pub fn wdt_(&mut self) -> WDT__W { + WDT__W { w: self } + } + #[doc = "Bit 9 - RTC APB Clock Enable"] + #[inline(always)] + pub fn rtc_(&mut self) -> RTC__W { + RTC__W { w: self } + } + #[doc = "Bit 10 - EIC APB Clock Enable"] + #[inline(always)] + pub fn eic_(&mut self) -> EIC__W { + EIC__W { w: self } + } + #[doc = "Bit 11 - FREQM APB Clock Enable"] + #[inline(always)] + pub fn freqm_(&mut self) -> FREQM__W { + FREQM__W { w: self } + } + #[doc = "Bit 12 - TSENS APB Clock Enable"] + #[inline(always)] + pub fn tsens_(&mut self) -> TSENS__W { + TSENS__W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "APBA Mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [apbamask](index.html) module"] +pub struct APBAMASK_SPEC; +impl crate::RegisterSpec for APBAMASK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [apbamask::R](R) reader structure"] +impl crate::Readable for APBAMASK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [apbamask::W](W) writer structure"] +impl crate::Writable for APBAMASK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets APBAMASK to value 0x0fff"] +impl crate::Resettable for APBAMASK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0fff + } +} diff --git a/pac/atsamc21j/src/mclk/apbbmask.rs b/pac/atsamc21j/src/mclk/apbbmask.rs new file mode 100644 index 000000000000..e1ec6b1f2323 --- /dev/null +++ b/pac/atsamc21j/src/mclk/apbbmask.rs @@ -0,0 +1,254 @@ +#[doc = "Register `APBBMASK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `APBBMASK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PORT_` reader - PORT APB Clock Enable"] +pub struct PORT__R(crate::FieldReader); +impl PORT__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PORT__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PORT__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PORT_` writer - PORT APB Clock Enable"] +pub struct PORT__W<'a> { + w: &'a mut W, +} +impl<'a> PORT__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `DSU_` reader - DSU APB Clock Enable"] +pub struct DSU__R(crate::FieldReader); +impl DSU__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DSU__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DSU__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DSU_` writer - DSU APB Clock Enable"] +pub struct DSU__W<'a> { + w: &'a mut W, +} +impl<'a> DSU__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `NVMCTRL_` reader - NVMCTRL APB Clock Enable"] +pub struct NVMCTRL__R(crate::FieldReader); +impl NVMCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NVMCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NVMCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NVMCTRL_` writer - NVMCTRL APB Clock Enable"] +pub struct NVMCTRL__W<'a> { + w: &'a mut W, +} +impl<'a> NVMCTRL__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `HMATRIXHS_` reader - HMATRIXHS APB Clock Enable"] +pub struct HMATRIXHS__R(crate::FieldReader); +impl HMATRIXHS__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HMATRIXHS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HMATRIXHS__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HMATRIXHS_` writer - HMATRIXHS APB Clock Enable"] +pub struct HMATRIXHS__W<'a> { + w: &'a mut W, +} +impl<'a> HMATRIXHS__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - PORT APB Clock Enable"] + #[inline(always)] + pub fn port_(&self) -> PORT__R { + PORT__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - DSU APB Clock Enable"] + #[inline(always)] + pub fn dsu_(&self) -> DSU__R { + DSU__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - NVMCTRL APB Clock Enable"] + #[inline(always)] + pub fn nvmctrl_(&self) -> NVMCTRL__R { + NVMCTRL__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 5 - HMATRIXHS APB Clock Enable"] + #[inline(always)] + pub fn hmatrixhs_(&self) -> HMATRIXHS__R { + HMATRIXHS__R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - PORT APB Clock Enable"] + #[inline(always)] + pub fn port_(&mut self) -> PORT__W { + PORT__W { w: self } + } + #[doc = "Bit 1 - DSU APB Clock Enable"] + #[inline(always)] + pub fn dsu_(&mut self) -> DSU__W { + DSU__W { w: self } + } + #[doc = "Bit 2 - NVMCTRL APB Clock Enable"] + #[inline(always)] + pub fn nvmctrl_(&mut self) -> NVMCTRL__W { + NVMCTRL__W { w: self } + } + #[doc = "Bit 5 - HMATRIXHS APB Clock Enable"] + #[inline(always)] + pub fn hmatrixhs_(&mut self) -> HMATRIXHS__W { + HMATRIXHS__W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "APBB Mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [apbbmask](index.html) module"] +pub struct APBBMASK_SPEC; +impl crate::RegisterSpec for APBBMASK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [apbbmask::R](R) reader structure"] +impl crate::Readable for APBBMASK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [apbbmask::W](W) writer structure"] +impl crate::Writable for APBBMASK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets APBBMASK to value 0x07"] +impl crate::Resettable for APBBMASK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x07 + } +} diff --git a/pac/atsamc21j/src/mclk/apbcmask.rs b/pac/atsamc21j/src/mclk/apbcmask.rs new file mode 100644 index 000000000000..04e63311c88e --- /dev/null +++ b/pac/atsamc21j/src/mclk/apbcmask.rs @@ -0,0 +1,1100 @@ +#[doc = "Register `APBCMASK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `APBCMASK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVSYS_` reader - EVSYS APB Clock Enable"] +pub struct EVSYS__R(crate::FieldReader); +impl EVSYS__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVSYS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVSYS__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVSYS_` writer - EVSYS APB Clock Enable"] +pub struct EVSYS__W<'a> { + w: &'a mut W, +} +impl<'a> EVSYS__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `SERCOM0_` reader - SERCOM0 APB Clock Enable"] +pub struct SERCOM0__R(crate::FieldReader); +impl SERCOM0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM0_` writer - SERCOM0 APB Clock Enable"] +pub struct SERCOM0__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SERCOM1_` reader - SERCOM1 APB Clock Enable"] +pub struct SERCOM1__R(crate::FieldReader); +impl SERCOM1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM1_` writer - SERCOM1 APB Clock Enable"] +pub struct SERCOM1__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SERCOM2_` reader - SERCOM2 APB Clock Enable"] +pub struct SERCOM2__R(crate::FieldReader); +impl SERCOM2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM2_` writer - SERCOM2 APB Clock Enable"] +pub struct SERCOM2__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM2__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `SERCOM3_` reader - SERCOM3 APB Clock Enable"] +pub struct SERCOM3__R(crate::FieldReader); +impl SERCOM3__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM3__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM3__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM3_` writer - SERCOM3 APB Clock Enable"] +pub struct SERCOM3__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM3__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `SERCOM4_` reader - SERCOM4 APB Clock Enable"] +pub struct SERCOM4__R(crate::FieldReader); +impl SERCOM4__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM4__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM4__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM4_` writer - SERCOM4 APB Clock Enable"] +pub struct SERCOM4__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM4__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `SERCOM5_` reader - SERCOM5 APB Clock Enable"] +pub struct SERCOM5__R(crate::FieldReader); +impl SERCOM5__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM5__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM5__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM5_` writer - SERCOM5 APB Clock Enable"] +pub struct SERCOM5__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM5__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `TCC0_` reader - TCC0 APB Clock Enable"] +pub struct TCC0__R(crate::FieldReader); +impl TCC0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCC0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCC0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCC0_` writer - TCC0 APB Clock Enable"] +pub struct TCC0__W<'a> { + w: &'a mut W, +} +impl<'a> TCC0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `TCC1_` reader - TCC1 APB Clock Enable"] +pub struct TCC1__R(crate::FieldReader); +impl TCC1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCC1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCC1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCC1_` writer - TCC1 APB Clock Enable"] +pub struct TCC1__W<'a> { + w: &'a mut W, +} +impl<'a> TCC1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `TCC2_` reader - TCC2 APB Clock Enable"] +pub struct TCC2__R(crate::FieldReader); +impl TCC2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCC2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCC2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCC2_` writer - TCC2 APB Clock Enable"] +pub struct TCC2__W<'a> { + w: &'a mut W, +} +impl<'a> TCC2__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `TC0_` reader - TC0 APB Clock Enable"] +pub struct TC0__R(crate::FieldReader); +impl TC0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC0_` writer - TC0 APB Clock Enable"] +pub struct TC0__W<'a> { + w: &'a mut W, +} +impl<'a> TC0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `TC1_` reader - TC1 APB Clock Enable"] +pub struct TC1__R(crate::FieldReader); +impl TC1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC1_` writer - TC1 APB Clock Enable"] +pub struct TC1__W<'a> { + w: &'a mut W, +} +impl<'a> TC1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `TC2_` reader - TC2 APB Clock Enable"] +pub struct TC2__R(crate::FieldReader); +impl TC2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC2_` writer - TC2 APB Clock Enable"] +pub struct TC2__W<'a> { + w: &'a mut W, +} +impl<'a> TC2__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `TC3_` reader - TC3 APB Clock Enable"] +pub struct TC3__R(crate::FieldReader); +impl TC3__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC3__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC3__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC3_` writer - TC3 APB Clock Enable"] +pub struct TC3__W<'a> { + w: &'a mut W, +} +impl<'a> TC3__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `TC4_` reader - TC4 APB Clock Enable"] +pub struct TC4__R(crate::FieldReader); +impl TC4__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC4__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC4__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC4_` writer - TC4 APB Clock Enable"] +pub struct TC4__W<'a> { + w: &'a mut W, +} +impl<'a> TC4__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `ADC0_` reader - ADC0 APB Clock Enable"] +pub struct ADC0__R(crate::FieldReader); +impl ADC0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ADC0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADC0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADC0_` writer - ADC0 APB Clock Enable"] +pub struct ADC0__W<'a> { + w: &'a mut W, +} +impl<'a> ADC0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `ADC1_` reader - ADC1 APB Clock Enable"] +pub struct ADC1__R(crate::FieldReader); +impl ADC1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ADC1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADC1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADC1_` writer - ADC1 APB Clock Enable"] +pub struct ADC1__W<'a> { + w: &'a mut W, +} +impl<'a> ADC1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `SDADC_` reader - SDADC APB Clock Enable"] +pub struct SDADC__R(crate::FieldReader); +impl SDADC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SDADC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SDADC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SDADC_` writer - SDADC APB Clock Enable"] +pub struct SDADC__W<'a> { + w: &'a mut W, +} +impl<'a> SDADC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `AC_` reader - AC APB Clock Enable"] +pub struct AC__R(crate::FieldReader); +impl AC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AC_` writer - AC APB Clock Enable"] +pub struct AC__W<'a> { + w: &'a mut W, +} +impl<'a> AC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `DAC_` reader - DAC APB Clock Enable"] +pub struct DAC__R(crate::FieldReader); +impl DAC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DAC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DAC_` writer - DAC APB Clock Enable"] +pub struct DAC__W<'a> { + w: &'a mut W, +} +impl<'a> DAC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `PTC_` reader - PTC APB Clock Enable"] +pub struct PTC__R(crate::FieldReader); +impl PTC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PTC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PTC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PTC_` writer - PTC APB Clock Enable"] +pub struct PTC__W<'a> { + w: &'a mut W, +} +impl<'a> PTC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `CCL_` reader - CCL APB Clock Enable"] +pub struct CCL__R(crate::FieldReader); +impl CCL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCL_` writer - CCL APB Clock Enable"] +pub struct CCL__W<'a> { + w: &'a mut W, +} +impl<'a> CCL__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +impl R { + #[doc = "Bit 0 - EVSYS APB Clock Enable"] + #[inline(always)] + pub fn evsys_(&self) -> EVSYS__R { + EVSYS__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM0 APB Clock Enable"] + #[inline(always)] + pub fn sercom0_(&self) -> SERCOM0__R { + SERCOM0__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - SERCOM1 APB Clock Enable"] + #[inline(always)] + pub fn sercom1_(&self) -> SERCOM1__R { + SERCOM1__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - SERCOM2 APB Clock Enable"] + #[inline(always)] + pub fn sercom2_(&self) -> SERCOM2__R { + SERCOM2__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - SERCOM3 APB Clock Enable"] + #[inline(always)] + pub fn sercom3_(&self) -> SERCOM3__R { + SERCOM3__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - SERCOM4 APB Clock Enable"] + #[inline(always)] + pub fn sercom4_(&self) -> SERCOM4__R { + SERCOM4__R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - SERCOM5 APB Clock Enable"] + #[inline(always)] + pub fn sercom5_(&self) -> SERCOM5__R { + SERCOM5__R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 9 - TCC0 APB Clock Enable"] + #[inline(always)] + pub fn tcc0_(&self) -> TCC0__R { + TCC0__R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - TCC1 APB Clock Enable"] + #[inline(always)] + pub fn tcc1_(&self) -> TCC1__R { + TCC1__R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - TCC2 APB Clock Enable"] + #[inline(always)] + pub fn tcc2_(&self) -> TCC2__R { + TCC2__R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - TC0 APB Clock Enable"] + #[inline(always)] + pub fn tc0_(&self) -> TC0__R { + TC0__R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - TC1 APB Clock Enable"] + #[inline(always)] + pub fn tc1_(&self) -> TC1__R { + TC1__R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - TC2 APB Clock Enable"] + #[inline(always)] + pub fn tc2_(&self) -> TC2__R { + TC2__R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - TC3 APB Clock Enable"] + #[inline(always)] + pub fn tc3_(&self) -> TC3__R { + TC3__R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - TC4 APB Clock Enable"] + #[inline(always)] + pub fn tc4_(&self) -> TC4__R { + TC4__R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - ADC0 APB Clock Enable"] + #[inline(always)] + pub fn adc0_(&self) -> ADC0__R { + ADC0__R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - ADC1 APB Clock Enable"] + #[inline(always)] + pub fn adc1_(&self) -> ADC1__R { + ADC1__R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - SDADC APB Clock Enable"] + #[inline(always)] + pub fn sdadc_(&self) -> SDADC__R { + SDADC__R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - AC APB Clock Enable"] + #[inline(always)] + pub fn ac_(&self) -> AC__R { + AC__R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - DAC APB Clock Enable"] + #[inline(always)] + pub fn dac_(&self) -> DAC__R { + DAC__R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - PTC APB Clock Enable"] + #[inline(always)] + pub fn ptc_(&self) -> PTC__R { + PTC__R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - CCL APB Clock Enable"] + #[inline(always)] + pub fn ccl_(&self) -> CCL__R { + CCL__R::new(((self.bits >> 23) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - EVSYS APB Clock Enable"] + #[inline(always)] + pub fn evsys_(&mut self) -> EVSYS__W { + EVSYS__W { w: self } + } + #[doc = "Bit 1 - SERCOM0 APB Clock Enable"] + #[inline(always)] + pub fn sercom0_(&mut self) -> SERCOM0__W { + SERCOM0__W { w: self } + } + #[doc = "Bit 2 - SERCOM1 APB Clock Enable"] + #[inline(always)] + pub fn sercom1_(&mut self) -> SERCOM1__W { + SERCOM1__W { w: self } + } + #[doc = "Bit 3 - SERCOM2 APB Clock Enable"] + #[inline(always)] + pub fn sercom2_(&mut self) -> SERCOM2__W { + SERCOM2__W { w: self } + } + #[doc = "Bit 4 - SERCOM3 APB Clock Enable"] + #[inline(always)] + pub fn sercom3_(&mut self) -> SERCOM3__W { + SERCOM3__W { w: self } + } + #[doc = "Bit 5 - SERCOM4 APB Clock Enable"] + #[inline(always)] + pub fn sercom4_(&mut self) -> SERCOM4__W { + SERCOM4__W { w: self } + } + #[doc = "Bit 6 - SERCOM5 APB Clock Enable"] + #[inline(always)] + pub fn sercom5_(&mut self) -> SERCOM5__W { + SERCOM5__W { w: self } + } + #[doc = "Bit 9 - TCC0 APB Clock Enable"] + #[inline(always)] + pub fn tcc0_(&mut self) -> TCC0__W { + TCC0__W { w: self } + } + #[doc = "Bit 10 - TCC1 APB Clock Enable"] + #[inline(always)] + pub fn tcc1_(&mut self) -> TCC1__W { + TCC1__W { w: self } + } + #[doc = "Bit 11 - TCC2 APB Clock Enable"] + #[inline(always)] + pub fn tcc2_(&mut self) -> TCC2__W { + TCC2__W { w: self } + } + #[doc = "Bit 12 - TC0 APB Clock Enable"] + #[inline(always)] + pub fn tc0_(&mut self) -> TC0__W { + TC0__W { w: self } + } + #[doc = "Bit 13 - TC1 APB Clock Enable"] + #[inline(always)] + pub fn tc1_(&mut self) -> TC1__W { + TC1__W { w: self } + } + #[doc = "Bit 14 - TC2 APB Clock Enable"] + #[inline(always)] + pub fn tc2_(&mut self) -> TC2__W { + TC2__W { w: self } + } + #[doc = "Bit 15 - TC3 APB Clock Enable"] + #[inline(always)] + pub fn tc3_(&mut self) -> TC3__W { + TC3__W { w: self } + } + #[doc = "Bit 16 - TC4 APB Clock Enable"] + #[inline(always)] + pub fn tc4_(&mut self) -> TC4__W { + TC4__W { w: self } + } + #[doc = "Bit 17 - ADC0 APB Clock Enable"] + #[inline(always)] + pub fn adc0_(&mut self) -> ADC0__W { + ADC0__W { w: self } + } + #[doc = "Bit 18 - ADC1 APB Clock Enable"] + #[inline(always)] + pub fn adc1_(&mut self) -> ADC1__W { + ADC1__W { w: self } + } + #[doc = "Bit 19 - SDADC APB Clock Enable"] + #[inline(always)] + pub fn sdadc_(&mut self) -> SDADC__W { + SDADC__W { w: self } + } + #[doc = "Bit 20 - AC APB Clock Enable"] + #[inline(always)] + pub fn ac_(&mut self) -> AC__W { + AC__W { w: self } + } + #[doc = "Bit 21 - DAC APB Clock Enable"] + #[inline(always)] + pub fn dac_(&mut self) -> DAC__W { + DAC__W { w: self } + } + #[doc = "Bit 22 - PTC APB Clock Enable"] + #[inline(always)] + pub fn ptc_(&mut self) -> PTC__W { + PTC__W { w: self } + } + #[doc = "Bit 23 - CCL APB Clock Enable"] + #[inline(always)] + pub fn ccl_(&mut self) -> CCL__W { + CCL__W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "APBC Mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [apbcmask](index.html) module"] +pub struct APBCMASK_SPEC; +impl crate::RegisterSpec for APBCMASK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [apbcmask::R](R) reader structure"] +impl crate::Readable for APBCMASK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [apbcmask::W](W) writer structure"] +impl crate::Writable for APBCMASK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets APBCMASK to value 0"] +impl crate::Resettable for APBCMASK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/mclk/cpudiv.rs b/pac/atsamc21j/src/mclk/cpudiv.rs new file mode 100644 index 000000000000..a21fdae21357 --- /dev/null +++ b/pac/atsamc21j/src/mclk/cpudiv.rs @@ -0,0 +1,230 @@ +#[doc = "Register `CPUDIV` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CPUDIV` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "CPU Clock Division Factor\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CPUDIV_A { + #[doc = "1: Divide by 1"] + DIV1 = 1, + #[doc = "2: Divide by 2"] + DIV2 = 2, + #[doc = "4: Divide by 4"] + DIV4 = 4, + #[doc = "8: Divide by 8"] + DIV8 = 8, + #[doc = "16: Divide by 16"] + DIV16 = 16, + #[doc = "32: Divide by 32"] + DIV32 = 32, + #[doc = "64: Divide by 64"] + DIV64 = 64, + #[doc = "128: Divide by 128"] + DIV128 = 128, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CPUDIV_A) -> Self { + variant as _ + } +} +#[doc = "Field `CPUDIV` reader - CPU Clock Division Factor"] +pub struct CPUDIV_R(crate::FieldReader); +impl CPUDIV_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CPUDIV_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 1 => Some(CPUDIV_A::DIV1), + 2 => Some(CPUDIV_A::DIV2), + 4 => Some(CPUDIV_A::DIV4), + 8 => Some(CPUDIV_A::DIV8), + 16 => Some(CPUDIV_A::DIV16), + 32 => Some(CPUDIV_A::DIV32), + 64 => Some(CPUDIV_A::DIV64), + 128 => Some(CPUDIV_A::DIV128), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == CPUDIV_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == CPUDIV_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == CPUDIV_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == CPUDIV_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == CPUDIV_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == CPUDIV_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == CPUDIV_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == CPUDIV_A::DIV128 + } +} +impl core::ops::Deref for CPUDIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPUDIV` writer - CPU Clock Division Factor"] +pub struct CPUDIV_W<'a> { + w: &'a mut W, +} +impl<'a> CPUDIV_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CPUDIV_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Divide by 1"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV1) + } + #[doc = "Divide by 2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV2) + } + #[doc = "Divide by 4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV4) + } + #[doc = "Divide by 8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV8) + } + #[doc = "Divide by 16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV16) + } + #[doc = "Divide by 32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV32) + } + #[doc = "Divide by 64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV64) + } + #[doc = "Divide by 128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV128) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - CPU Clock Division Factor"] + #[inline(always)] + pub fn cpudiv(&self) -> CPUDIV_R { + CPUDIV_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - CPU Clock Division Factor"] + #[inline(always)] + pub fn cpudiv(&mut self) -> CPUDIV_W { + CPUDIV_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CPU Clock Division\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cpudiv](index.html) module"] +pub struct CPUDIV_SPEC; +impl crate::RegisterSpec for CPUDIV_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [cpudiv::R](R) reader structure"] +impl crate::Readable for CPUDIV_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cpudiv::W](W) writer structure"] +impl crate::Writable for CPUDIV_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CPUDIV to value 0x01"] +impl crate::Resettable for CPUDIV_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pac/atsamc21j/src/mclk/intenclr.rs b/pac/atsamc21j/src/mclk/intenclr.rs new file mode 100644 index 000000000000..14feb632dbb7 --- /dev/null +++ b/pac/atsamc21j/src/mclk/intenclr.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CKRDY` reader - Clock Ready Interrupt Enable"] +pub struct CKRDY_R(crate::FieldReader); +impl CKRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CKRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CKRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CKRDY` writer - Clock Ready Interrupt Enable"] +pub struct CKRDY_W<'a> { + w: &'a mut W, +} +impl<'a> CKRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Clock Ready Interrupt Enable"] + #[inline(always)] + pub fn ckrdy(&self) -> CKRDY_R { + CKRDY_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Clock Ready Interrupt Enable"] + #[inline(always)] + pub fn ckrdy(&mut self) -> CKRDY_W { + CKRDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/mclk/intenset.rs b/pac/atsamc21j/src/mclk/intenset.rs new file mode 100644 index 000000000000..f01fcc316d93 --- /dev/null +++ b/pac/atsamc21j/src/mclk/intenset.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CKRDY` reader - Clock Ready Interrupt Enable"] +pub struct CKRDY_R(crate::FieldReader); +impl CKRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CKRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CKRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CKRDY` writer - Clock Ready Interrupt Enable"] +pub struct CKRDY_W<'a> { + w: &'a mut W, +} +impl<'a> CKRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Clock Ready Interrupt Enable"] + #[inline(always)] + pub fn ckrdy(&self) -> CKRDY_R { + CKRDY_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Clock Ready Interrupt Enable"] + #[inline(always)] + pub fn ckrdy(&mut self) -> CKRDY_W { + CKRDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/mclk/intflag.rs b/pac/atsamc21j/src/mclk/intflag.rs new file mode 100644 index 000000000000..cf421d4ac61a --- /dev/null +++ b/pac/atsamc21j/src/mclk/intflag.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CKRDY` reader - Clock Ready"] +pub struct CKRDY_R(crate::FieldReader); +impl CKRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CKRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CKRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CKRDY` writer - Clock Ready"] +pub struct CKRDY_W<'a> { + w: &'a mut W, +} +impl<'a> CKRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Clock Ready"] + #[inline(always)] + pub fn ckrdy(&self) -> CKRDY_R { + CKRDY_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Clock Ready"] + #[inline(always)] + pub fn ckrdy(&mut self) -> CKRDY_W { + CKRDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0x01"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pac/atsamc21j/src/mtb.rs b/pac/atsamc21j/src/mtb.rs new file mode 100644 index 000000000000..01be005c0fb9 --- /dev/null +++ b/pac/atsamc21j/src/mtb.rs @@ -0,0 +1,158 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - MTB Position"] + pub position: crate::Reg, + #[doc = "0x04 - MTB Master"] + pub master: crate::Reg, + #[doc = "0x08 - MTB Flow"] + pub flow: crate::Reg, + #[doc = "0x0c - MTB Base"] + pub base: crate::Reg, + _reserved4: [u8; 0x0ef0], + #[doc = "0xf00 - MTB Integration Mode Control"] + pub itctrl: crate::Reg, + _reserved5: [u8; 0x9c], + #[doc = "0xfa0 - MTB Claim Set"] + pub claimset: crate::Reg, + #[doc = "0xfa4 - MTB Claim Clear"] + pub claimclr: crate::Reg, + _reserved7: [u8; 0x08], + #[doc = "0xfb0 - MTB Lock Access"] + pub lockaccess: crate::Reg, + #[doc = "0xfb4 - MTB Lock Status"] + pub lockstatus: crate::Reg, + #[doc = "0xfb8 - MTB Authentication Status"] + pub authstatus: crate::Reg, + #[doc = "0xfbc - MTB Device Architecture"] + pub devarch: crate::Reg, + _reserved11: [u8; 0x08], + #[doc = "0xfc8 - MTB Device Configuration"] + pub devid: crate::Reg, + #[doc = "0xfcc - MTB Device Type"] + pub devtype: crate::Reg, + #[doc = "0xfd0 - Peripheral Identification 4"] + pub pid4: crate::Reg, + #[doc = "0xfd4 - Peripheral Identification 5"] + pub pid5: crate::Reg, + #[doc = "0xfd8 - Peripheral Identification 6"] + pub pid6: crate::Reg, + #[doc = "0xfdc - Peripheral Identification 7"] + pub pid7: crate::Reg, + #[doc = "0xfe0 - Peripheral Identification 0"] + pub pid0: crate::Reg, + #[doc = "0xfe4 - Peripheral Identification 1"] + pub pid1: crate::Reg, + #[doc = "0xfe8 - Peripheral Identification 2"] + pub pid2: crate::Reg, + #[doc = "0xfec - Peripheral Identification 3"] + pub pid3: crate::Reg, + #[doc = "0xff0 - Component Identification 0"] + pub cid0: crate::Reg, + #[doc = "0xff4 - Component Identification 1"] + pub cid1: crate::Reg, + #[doc = "0xff8 - Component Identification 2"] + pub cid2: crate::Reg, + #[doc = "0xffc - Component Identification 3"] + pub cid3: crate::Reg, +} +#[doc = "POSITION register accessor: an alias for `Reg`"] +pub type POSITION = crate::Reg; +#[doc = "MTB Position"] +pub mod position; +#[doc = "MASTER register accessor: an alias for `Reg`"] +pub type MASTER = crate::Reg; +#[doc = "MTB Master"] +pub mod master; +#[doc = "FLOW register accessor: an alias for `Reg`"] +pub type FLOW = crate::Reg; +#[doc = "MTB Flow"] +pub mod flow; +#[doc = "BASE register accessor: an alias for `Reg`"] +pub type BASE = crate::Reg; +#[doc = "MTB Base"] +pub mod base; +#[doc = "ITCTRL register accessor: an alias for `Reg`"] +pub type ITCTRL = crate::Reg; +#[doc = "MTB Integration Mode Control"] +pub mod itctrl; +#[doc = "CLAIMSET register accessor: an alias for `Reg`"] +pub type CLAIMSET = crate::Reg; +#[doc = "MTB Claim Set"] +pub mod claimset; +#[doc = "CLAIMCLR register accessor: an alias for `Reg`"] +pub type CLAIMCLR = crate::Reg; +#[doc = "MTB Claim Clear"] +pub mod claimclr; +#[doc = "LOCKACCESS register accessor: an alias for `Reg`"] +pub type LOCKACCESS = crate::Reg; +#[doc = "MTB Lock Access"] +pub mod lockaccess; +#[doc = "LOCKSTATUS register accessor: an alias for `Reg`"] +pub type LOCKSTATUS = crate::Reg; +#[doc = "MTB Lock Status"] +pub mod lockstatus; +#[doc = "AUTHSTATUS register accessor: an alias for `Reg`"] +pub type AUTHSTATUS = crate::Reg; +#[doc = "MTB Authentication Status"] +pub mod authstatus; +#[doc = "DEVARCH register accessor: an alias for `Reg`"] +pub type DEVARCH = crate::Reg; +#[doc = "MTB Device Architecture"] +pub mod devarch; +#[doc = "DEVID register accessor: an alias for `Reg`"] +pub type DEVID = crate::Reg; +#[doc = "MTB Device Configuration"] +pub mod devid; +#[doc = "DEVTYPE register accessor: an alias for `Reg`"] +pub type DEVTYPE = crate::Reg; +#[doc = "MTB Device Type"] +pub mod devtype; +#[doc = "PID4 register accessor: an alias for `Reg`"] +pub type PID4 = crate::Reg; +#[doc = "Peripheral Identification 4"] +pub mod pid4; +#[doc = "PID5 register accessor: an alias for `Reg`"] +pub type PID5 = crate::Reg; +#[doc = "Peripheral Identification 5"] +pub mod pid5; +#[doc = "PID6 register accessor: an alias for `Reg`"] +pub type PID6 = crate::Reg; +#[doc = "Peripheral Identification 6"] +pub mod pid6; +#[doc = "PID7 register accessor: an alias for `Reg`"] +pub type PID7 = crate::Reg; +#[doc = "Peripheral Identification 7"] +pub mod pid7; +#[doc = "PID0 register accessor: an alias for `Reg`"] +pub type PID0 = crate::Reg; +#[doc = "Peripheral Identification 0"] +pub mod pid0; +#[doc = "PID1 register accessor: an alias for `Reg`"] +pub type PID1 = crate::Reg; +#[doc = "Peripheral Identification 1"] +pub mod pid1; +#[doc = "PID2 register accessor: an alias for `Reg`"] +pub type PID2 = crate::Reg; +#[doc = "Peripheral Identification 2"] +pub mod pid2; +#[doc = "PID3 register accessor: an alias for `Reg`"] +pub type PID3 = crate::Reg; +#[doc = "Peripheral Identification 3"] +pub mod pid3; +#[doc = "CID0 register accessor: an alias for `Reg`"] +pub type CID0 = crate::Reg; +#[doc = "Component Identification 0"] +pub mod cid0; +#[doc = "CID1 register accessor: an alias for `Reg`"] +pub type CID1 = crate::Reg; +#[doc = "Component Identification 1"] +pub mod cid1; +#[doc = "CID2 register accessor: an alias for `Reg`"] +pub type CID2 = crate::Reg; +#[doc = "Component Identification 2"] +pub mod cid2; +#[doc = "CID3 register accessor: an alias for `Reg`"] +pub type CID3 = crate::Reg; +#[doc = "Component Identification 3"] +pub mod cid3; diff --git a/pac/atsamc21j/src/mtb/authstatus.rs b/pac/atsamc21j/src/mtb/authstatus.rs new file mode 100644 index 000000000000..6fe441e0554d --- /dev/null +++ b/pac/atsamc21j/src/mtb/authstatus.rs @@ -0,0 +1,31 @@ +#[doc = "Register `AUTHSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "MTB Authentication Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [authstatus](index.html) module"] +pub struct AUTHSTATUS_SPEC; +impl crate::RegisterSpec for AUTHSTATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [authstatus::R](R) reader structure"] +impl crate::Readable for AUTHSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets AUTHSTATUS to value 0"] +impl crate::Resettable for AUTHSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/mtb/base.rs b/pac/atsamc21j/src/mtb/base.rs new file mode 100644 index 000000000000..f59b5a97a398 --- /dev/null +++ b/pac/atsamc21j/src/mtb/base.rs @@ -0,0 +1,31 @@ +#[doc = "Register `BASE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "MTB Base\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [base](index.html) module"] +pub struct BASE_SPEC; +impl crate::RegisterSpec for BASE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [base::R](R) reader structure"] +impl crate::Readable for BASE_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets BASE to value 0"] +impl crate::Resettable for BASE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/mtb/cid0.rs b/pac/atsamc21j/src/mtb/cid0.rs new file mode 100644 index 000000000000..e03bd35fa470 --- /dev/null +++ b/pac/atsamc21j/src/mtb/cid0.rs @@ -0,0 +1,31 @@ +#[doc = "Register `CID0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Component Identification 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid0](index.html) module"] +pub struct CID0_SPEC; +impl crate::RegisterSpec for CID0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid0::R](R) reader structure"] +impl crate::Readable for CID0_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID0 to value 0"] +impl crate::Resettable for CID0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/mtb/cid1.rs b/pac/atsamc21j/src/mtb/cid1.rs new file mode 100644 index 000000000000..1cafc8e0fb9a --- /dev/null +++ b/pac/atsamc21j/src/mtb/cid1.rs @@ -0,0 +1,31 @@ +#[doc = "Register `CID1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Component Identification 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid1](index.html) module"] +pub struct CID1_SPEC; +impl crate::RegisterSpec for CID1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid1::R](R) reader structure"] +impl crate::Readable for CID1_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID1 to value 0"] +impl crate::Resettable for CID1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/mtb/cid2.rs b/pac/atsamc21j/src/mtb/cid2.rs new file mode 100644 index 000000000000..6a91e4e23206 --- /dev/null +++ b/pac/atsamc21j/src/mtb/cid2.rs @@ -0,0 +1,31 @@ +#[doc = "Register `CID2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Component Identification 2\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid2](index.html) module"] +pub struct CID2_SPEC; +impl crate::RegisterSpec for CID2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid2::R](R) reader structure"] +impl crate::Readable for CID2_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID2 to value 0"] +impl crate::Resettable for CID2_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/mtb/cid3.rs b/pac/atsamc21j/src/mtb/cid3.rs new file mode 100644 index 000000000000..726290f4ffed --- /dev/null +++ b/pac/atsamc21j/src/mtb/cid3.rs @@ -0,0 +1,31 @@ +#[doc = "Register `CID3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Component Identification 3\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid3](index.html) module"] +pub struct CID3_SPEC; +impl crate::RegisterSpec for CID3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid3::R](R) reader structure"] +impl crate::Readable for CID3_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID3 to value 0"] +impl crate::Resettable for CID3_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/mtb/claimclr.rs b/pac/atsamc21j/src/mtb/claimclr.rs new file mode 100644 index 000000000000..7d0fa5d487b2 --- /dev/null +++ b/pac/atsamc21j/src/mtb/claimclr.rs @@ -0,0 +1,64 @@ +#[doc = "Register `CLAIMCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CLAIMCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MTB Claim Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [claimclr](index.html) module"] +pub struct CLAIMCLR_SPEC; +impl crate::RegisterSpec for CLAIMCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [claimclr::R](R) reader structure"] +impl crate::Readable for CLAIMCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [claimclr::W](W) writer structure"] +impl crate::Writable for CLAIMCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CLAIMCLR to value 0"] +impl crate::Resettable for CLAIMCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/mtb/claimset.rs b/pac/atsamc21j/src/mtb/claimset.rs new file mode 100644 index 000000000000..d5e8ffaa4846 --- /dev/null +++ b/pac/atsamc21j/src/mtb/claimset.rs @@ -0,0 +1,64 @@ +#[doc = "Register `CLAIMSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CLAIMSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MTB Claim Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [claimset](index.html) module"] +pub struct CLAIMSET_SPEC; +impl crate::RegisterSpec for CLAIMSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [claimset::R](R) reader structure"] +impl crate::Readable for CLAIMSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [claimset::W](W) writer structure"] +impl crate::Writable for CLAIMSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CLAIMSET to value 0"] +impl crate::Resettable for CLAIMSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/mtb/devarch.rs b/pac/atsamc21j/src/mtb/devarch.rs new file mode 100644 index 000000000000..b79480753d5e --- /dev/null +++ b/pac/atsamc21j/src/mtb/devarch.rs @@ -0,0 +1,31 @@ +#[doc = "Register `DEVARCH` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "MTB Device Architecture\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [devarch](index.html) module"] +pub struct DEVARCH_SPEC; +impl crate::RegisterSpec for DEVARCH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [devarch::R](R) reader structure"] +impl crate::Readable for DEVARCH_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DEVARCH to value 0"] +impl crate::Resettable for DEVARCH_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/mtb/devid.rs b/pac/atsamc21j/src/mtb/devid.rs new file mode 100644 index 000000000000..21c15d952032 --- /dev/null +++ b/pac/atsamc21j/src/mtb/devid.rs @@ -0,0 +1,31 @@ +#[doc = "Register `DEVID` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "MTB Device Configuration\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [devid](index.html) module"] +pub struct DEVID_SPEC; +impl crate::RegisterSpec for DEVID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [devid::R](R) reader structure"] +impl crate::Readable for DEVID_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DEVID to value 0"] +impl crate::Resettable for DEVID_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/mtb/devtype.rs b/pac/atsamc21j/src/mtb/devtype.rs new file mode 100644 index 000000000000..c00d66b98a2f --- /dev/null +++ b/pac/atsamc21j/src/mtb/devtype.rs @@ -0,0 +1,31 @@ +#[doc = "Register `DEVTYPE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "MTB Device Type\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [devtype](index.html) module"] +pub struct DEVTYPE_SPEC; +impl crate::RegisterSpec for DEVTYPE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [devtype::R](R) reader structure"] +impl crate::Readable for DEVTYPE_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DEVTYPE to value 0"] +impl crate::Resettable for DEVTYPE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/mtb/flow.rs b/pac/atsamc21j/src/mtb/flow.rs new file mode 100644 index 000000000000..1b94efdb89b8 --- /dev/null +++ b/pac/atsamc21j/src/mtb/flow.rs @@ -0,0 +1,197 @@ +#[doc = "Register `FLOW` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FLOW` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `AUTOSTOP` reader - Auto Stop Tracing"] +pub struct AUTOSTOP_R(crate::FieldReader); +impl AUTOSTOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AUTOSTOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AUTOSTOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AUTOSTOP` writer - Auto Stop Tracing"] +pub struct AUTOSTOP_W<'a> { + w: &'a mut W, +} +impl<'a> AUTOSTOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `AUTOHALT` reader - Auto Halt Request"] +pub struct AUTOHALT_R(crate::FieldReader); +impl AUTOHALT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AUTOHALT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AUTOHALT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AUTOHALT` writer - Auto Halt Request"] +pub struct AUTOHALT_W<'a> { + w: &'a mut W, +} +impl<'a> AUTOHALT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WATERMARK` reader - Watermark value"] +pub struct WATERMARK_R(crate::FieldReader); +impl WATERMARK_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + WATERMARK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WATERMARK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WATERMARK` writer - Watermark value"] +pub struct WATERMARK_W<'a> { + w: &'a mut W, +} +impl<'a> WATERMARK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1fff_ffff << 3)) | ((value as u32 & 0x1fff_ffff) << 3); + self.w + } +} +impl R { + #[doc = "Bit 0 - Auto Stop Tracing"] + #[inline(always)] + pub fn autostop(&self) -> AUTOSTOP_R { + AUTOSTOP_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Auto Halt Request"] + #[inline(always)] + pub fn autohalt(&self) -> AUTOHALT_R { + AUTOHALT_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 3:31 - Watermark value"] + #[inline(always)] + pub fn watermark(&self) -> WATERMARK_R { + WATERMARK_R::new(((self.bits >> 3) & 0x1fff_ffff) as u32) + } +} +impl W { + #[doc = "Bit 0 - Auto Stop Tracing"] + #[inline(always)] + pub fn autostop(&mut self) -> AUTOSTOP_W { + AUTOSTOP_W { w: self } + } + #[doc = "Bit 1 - Auto Halt Request"] + #[inline(always)] + pub fn autohalt(&mut self) -> AUTOHALT_W { + AUTOHALT_W { w: self } + } + #[doc = "Bits 3:31 - Watermark value"] + #[inline(always)] + pub fn watermark(&mut self) -> WATERMARK_W { + WATERMARK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MTB Flow\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [flow](index.html) module"] +pub struct FLOW_SPEC; +impl crate::RegisterSpec for FLOW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [flow::R](R) reader structure"] +impl crate::Readable for FLOW_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [flow::W](W) writer structure"] +impl crate::Writable for FLOW_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets FLOW to value 0"] +impl crate::Resettable for FLOW_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/mtb/itctrl.rs b/pac/atsamc21j/src/mtb/itctrl.rs new file mode 100644 index 000000000000..a48364e0b062 --- /dev/null +++ b/pac/atsamc21j/src/mtb/itctrl.rs @@ -0,0 +1,64 @@ +#[doc = "Register `ITCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ITCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MTB Integration Mode Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [itctrl](index.html) module"] +pub struct ITCTRL_SPEC; +impl crate::RegisterSpec for ITCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [itctrl::R](R) reader structure"] +impl crate::Readable for ITCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [itctrl::W](W) writer structure"] +impl crate::Writable for ITCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ITCTRL to value 0"] +impl crate::Resettable for ITCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/mtb/lockaccess.rs b/pac/atsamc21j/src/mtb/lockaccess.rs new file mode 100644 index 000000000000..0400690beade --- /dev/null +++ b/pac/atsamc21j/src/mtb/lockaccess.rs @@ -0,0 +1,64 @@ +#[doc = "Register `LOCKACCESS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `LOCKACCESS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MTB Lock Access\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lockaccess](index.html) module"] +pub struct LOCKACCESS_SPEC; +impl crate::RegisterSpec for LOCKACCESS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [lockaccess::R](R) reader structure"] +impl crate::Readable for LOCKACCESS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [lockaccess::W](W) writer structure"] +impl crate::Writable for LOCKACCESS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets LOCKACCESS to value 0"] +impl crate::Resettable for LOCKACCESS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/mtb/lockstatus.rs b/pac/atsamc21j/src/mtb/lockstatus.rs new file mode 100644 index 000000000000..0c68410c6944 --- /dev/null +++ b/pac/atsamc21j/src/mtb/lockstatus.rs @@ -0,0 +1,31 @@ +#[doc = "Register `LOCKSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "MTB Lock Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lockstatus](index.html) module"] +pub struct LOCKSTATUS_SPEC; +impl crate::RegisterSpec for LOCKSTATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [lockstatus::R](R) reader structure"] +impl crate::Readable for LOCKSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets LOCKSTATUS to value 0"] +impl crate::Resettable for LOCKSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/mtb/master.rs b/pac/atsamc21j/src/mtb/master.rs new file mode 100644 index 000000000000..0190ca1ce909 --- /dev/null +++ b/pac/atsamc21j/src/mtb/master.rs @@ -0,0 +1,385 @@ +#[doc = "Register `MASTER` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MASTER` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MASK` reader - Maximum Value of the Trace Buffer in SRAM"] +pub struct MASK_R(crate::FieldReader); +impl MASK_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MASK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MASK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MASK` writer - Maximum Value of the Trace Buffer in SRAM"] +pub struct MASK_W<'a> { + w: &'a mut W, +} +impl<'a> MASK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f); + self.w + } +} +#[doc = "Field `TSTARTEN` reader - Trace Start Input Enable"] +pub struct TSTARTEN_R(crate::FieldReader); +impl TSTARTEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSTARTEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSTARTEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSTARTEN` writer - Trace Start Input Enable"] +pub struct TSTARTEN_W<'a> { + w: &'a mut W, +} +impl<'a> TSTARTEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `TSTOPEN` reader - Trace Stop Input Enable"] +pub struct TSTOPEN_R(crate::FieldReader); +impl TSTOPEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSTOPEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSTOPEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSTOPEN` writer - Trace Stop Input Enable"] +pub struct TSTOPEN_W<'a> { + w: &'a mut W, +} +impl<'a> TSTOPEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `SFRWPRIV` reader - Special Function Register Write Privilege"] +pub struct SFRWPRIV_R(crate::FieldReader); +impl SFRWPRIV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SFRWPRIV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SFRWPRIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SFRWPRIV` writer - Special Function Register Write Privilege"] +pub struct SFRWPRIV_W<'a> { + w: &'a mut W, +} +impl<'a> SFRWPRIV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `RAMPRIV` reader - SRAM Privilege"] +pub struct RAMPRIV_R(crate::FieldReader); +impl RAMPRIV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RAMPRIV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RAMPRIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RAMPRIV` writer - SRAM Privilege"] +pub struct RAMPRIV_W<'a> { + w: &'a mut W, +} +impl<'a> RAMPRIV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `HALTREQ` reader - Halt Request"] +pub struct HALTREQ_R(crate::FieldReader); +impl HALTREQ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HALTREQ_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HALTREQ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HALTREQ` writer - Halt Request"] +pub struct HALTREQ_W<'a> { + w: &'a mut W, +} +impl<'a> HALTREQ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `EN` reader - Main Trace Enable"] +pub struct EN_R(crate::FieldReader); +impl EN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EN` writer - Main Trace Enable"] +pub struct EN_W<'a> { + w: &'a mut W, +} +impl<'a> EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Maximum Value of the Trace Buffer in SRAM"] + #[inline(always)] + pub fn mask(&self) -> MASK_R { + MASK_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bit 5 - Trace Start Input Enable"] + #[inline(always)] + pub fn tstarten(&self) -> TSTARTEN_R { + TSTARTEN_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Trace Stop Input Enable"] + #[inline(always)] + pub fn tstopen(&self) -> TSTOPEN_R { + TSTOPEN_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Special Function Register Write Privilege"] + #[inline(always)] + pub fn sfrwpriv(&self) -> SFRWPRIV_R { + SFRWPRIV_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - SRAM Privilege"] + #[inline(always)] + pub fn rampriv(&self) -> RAMPRIV_R { + RAMPRIV_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Halt Request"] + #[inline(always)] + pub fn haltreq(&self) -> HALTREQ_R { + HALTREQ_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 31 - Main Trace Enable"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Maximum Value of the Trace Buffer in SRAM"] + #[inline(always)] + pub fn mask(&mut self) -> MASK_W { + MASK_W { w: self } + } + #[doc = "Bit 5 - Trace Start Input Enable"] + #[inline(always)] + pub fn tstarten(&mut self) -> TSTARTEN_W { + TSTARTEN_W { w: self } + } + #[doc = "Bit 6 - Trace Stop Input Enable"] + #[inline(always)] + pub fn tstopen(&mut self) -> TSTOPEN_W { + TSTOPEN_W { w: self } + } + #[doc = "Bit 7 - Special Function Register Write Privilege"] + #[inline(always)] + pub fn sfrwpriv(&mut self) -> SFRWPRIV_W { + SFRWPRIV_W { w: self } + } + #[doc = "Bit 8 - SRAM Privilege"] + #[inline(always)] + pub fn rampriv(&mut self) -> RAMPRIV_W { + RAMPRIV_W { w: self } + } + #[doc = "Bit 9 - Halt Request"] + #[inline(always)] + pub fn haltreq(&mut self) -> HALTREQ_W { + HALTREQ_W { w: self } + } + #[doc = "Bit 31 - Main Trace Enable"] + #[inline(always)] + pub fn en(&mut self) -> EN_W { + EN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MTB Master\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [master](index.html) module"] +pub struct MASTER_SPEC; +impl crate::RegisterSpec for MASTER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [master::R](R) reader structure"] +impl crate::Readable for MASTER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [master::W](W) writer structure"] +impl crate::Writable for MASTER_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets MASTER to value 0"] +impl crate::Resettable for MASTER_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/mtb/pid0.rs b/pac/atsamc21j/src/mtb/pid0.rs new file mode 100644 index 000000000000..0a7183189fe5 --- /dev/null +++ b/pac/atsamc21j/src/mtb/pid0.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid0](index.html) module"] +pub struct PID0_SPEC; +impl crate::RegisterSpec for PID0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid0::R](R) reader structure"] +impl crate::Readable for PID0_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID0 to value 0"] +impl crate::Resettable for PID0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/mtb/pid1.rs b/pac/atsamc21j/src/mtb/pid1.rs new file mode 100644 index 000000000000..7d6381917f5d --- /dev/null +++ b/pac/atsamc21j/src/mtb/pid1.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid1](index.html) module"] +pub struct PID1_SPEC; +impl crate::RegisterSpec for PID1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid1::R](R) reader structure"] +impl crate::Readable for PID1_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID1 to value 0"] +impl crate::Resettable for PID1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/mtb/pid2.rs b/pac/atsamc21j/src/mtb/pid2.rs new file mode 100644 index 000000000000..74c230346b4c --- /dev/null +++ b/pac/atsamc21j/src/mtb/pid2.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 2\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid2](index.html) module"] +pub struct PID2_SPEC; +impl crate::RegisterSpec for PID2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid2::R](R) reader structure"] +impl crate::Readable for PID2_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID2 to value 0"] +impl crate::Resettable for PID2_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/mtb/pid3.rs b/pac/atsamc21j/src/mtb/pid3.rs new file mode 100644 index 000000000000..e9e922aa2f21 --- /dev/null +++ b/pac/atsamc21j/src/mtb/pid3.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 3\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid3](index.html) module"] +pub struct PID3_SPEC; +impl crate::RegisterSpec for PID3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid3::R](R) reader structure"] +impl crate::Readable for PID3_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID3 to value 0"] +impl crate::Resettable for PID3_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/mtb/pid4.rs b/pac/atsamc21j/src/mtb/pid4.rs new file mode 100644 index 000000000000..89074d3c2692 --- /dev/null +++ b/pac/atsamc21j/src/mtb/pid4.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID4` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 4\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid4](index.html) module"] +pub struct PID4_SPEC; +impl crate::RegisterSpec for PID4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid4::R](R) reader structure"] +impl crate::Readable for PID4_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID4 to value 0"] +impl crate::Resettable for PID4_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/mtb/pid5.rs b/pac/atsamc21j/src/mtb/pid5.rs new file mode 100644 index 000000000000..d343d4800b95 --- /dev/null +++ b/pac/atsamc21j/src/mtb/pid5.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID5` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 5\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid5](index.html) module"] +pub struct PID5_SPEC; +impl crate::RegisterSpec for PID5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid5::R](R) reader structure"] +impl crate::Readable for PID5_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID5 to value 0"] +impl crate::Resettable for PID5_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/mtb/pid6.rs b/pac/atsamc21j/src/mtb/pid6.rs new file mode 100644 index 000000000000..55cc2b8b5861 --- /dev/null +++ b/pac/atsamc21j/src/mtb/pid6.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID6` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 6\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid6](index.html) module"] +pub struct PID6_SPEC; +impl crate::RegisterSpec for PID6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid6::R](R) reader structure"] +impl crate::Readable for PID6_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID6 to value 0"] +impl crate::Resettable for PID6_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/mtb/pid7.rs b/pac/atsamc21j/src/mtb/pid7.rs new file mode 100644 index 000000000000..77664d4f2f95 --- /dev/null +++ b/pac/atsamc21j/src/mtb/pid7.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID7` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 7\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid7](index.html) module"] +pub struct PID7_SPEC; +impl crate::RegisterSpec for PID7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid7::R](R) reader structure"] +impl crate::Readable for PID7_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID7 to value 0"] +impl crate::Resettable for PID7_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/mtb/position.rs b/pac/atsamc21j/src/mtb/position.rs new file mode 100644 index 000000000000..4bab0425b142 --- /dev/null +++ b/pac/atsamc21j/src/mtb/position.rs @@ -0,0 +1,150 @@ +#[doc = "Register `POSITION` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `POSITION` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WRAP` reader - Pointer Value Wraps"] +pub struct WRAP_R(crate::FieldReader); +impl WRAP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WRAP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WRAP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WRAP` writer - Pointer Value Wraps"] +pub struct WRAP_W<'a> { + w: &'a mut W, +} +impl<'a> WRAP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `POINTER` reader - Trace Packet Location Pointer"] +pub struct POINTER_R(crate::FieldReader); +impl POINTER_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + POINTER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for POINTER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `POINTER` writer - Trace Packet Location Pointer"] +pub struct POINTER_W<'a> { + w: &'a mut W, +} +impl<'a> POINTER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1fff_ffff << 3)) | ((value as u32 & 0x1fff_ffff) << 3); + self.w + } +} +impl R { + #[doc = "Bit 2 - Pointer Value Wraps"] + #[inline(always)] + pub fn wrap(&self) -> WRAP_R { + WRAP_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 3:31 - Trace Packet Location Pointer"] + #[inline(always)] + pub fn pointer(&self) -> POINTER_R { + POINTER_R::new(((self.bits >> 3) & 0x1fff_ffff) as u32) + } +} +impl W { + #[doc = "Bit 2 - Pointer Value Wraps"] + #[inline(always)] + pub fn wrap(&mut self) -> WRAP_W { + WRAP_W { w: self } + } + #[doc = "Bits 3:31 - Trace Packet Location Pointer"] + #[inline(always)] + pub fn pointer(&mut self) -> POINTER_W { + POINTER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MTB Position\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [position](index.html) module"] +pub struct POSITION_SPEC; +impl crate::RegisterSpec for POSITION_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [position::R](R) reader structure"] +impl crate::Readable for POSITION_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [position::W](W) writer structure"] +impl crate::Writable for POSITION_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets POSITION to value 0"] +impl crate::Resettable for POSITION_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/nvmctrl.rs b/pac/atsamc21j/src/nvmctrl.rs new file mode 100644 index 000000000000..2c017caaef9c --- /dev/null +++ b/pac/atsamc21j/src/nvmctrl.rs @@ -0,0 +1,76 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + _reserved1: [u8; 0x02], + #[doc = "0x04 - Control B"] + pub ctrlb: crate::Reg, + #[doc = "0x08 - NVM Parameter"] + pub param: crate::Reg, + #[doc = "0x0c - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + _reserved4: [u8; 0x03], + #[doc = "0x10 - Interrupt Enable Set"] + pub intenset: crate::Reg, + _reserved5: [u8; 0x03], + #[doc = "0x14 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved6: [u8; 0x03], + #[doc = "0x18 - Status"] + pub status: crate::Reg, + _reserved7: [u8; 0x02], + #[doc = "0x1c - Address"] + pub addr: crate::Reg, + #[doc = "0x20 - Lock Section"] + pub lock: crate::Reg, + _reserved9: [u8; 0x06], + #[doc = "0x28 - Page Buffer Load Data 0"] + pub pbldata0: crate::Reg, + #[doc = "0x2c - Page Buffer Load Data 1"] + pub pbldata1: crate::Reg, +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "Control B"] +pub mod ctrlb; +#[doc = "PARAM register accessor: an alias for `Reg`"] +pub type PARAM = crate::Reg; +#[doc = "NVM Parameter"] +pub mod param; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "ADDR register accessor: an alias for `Reg`"] +pub type ADDR = crate::Reg; +#[doc = "Address"] +pub mod addr; +#[doc = "LOCK register accessor: an alias for `Reg`"] +pub type LOCK = crate::Reg; +#[doc = "Lock Section"] +pub mod lock; +#[doc = "PBLDATA0 register accessor: an alias for `Reg`"] +pub type PBLDATA0 = crate::Reg; +#[doc = "Page Buffer Load Data 0"] +pub mod pbldata0; +#[doc = "PBLDATA1 register accessor: an alias for `Reg`"] +pub type PBLDATA1 = crate::Reg; +#[doc = "Page Buffer Load Data 1"] +pub mod pbldata1; diff --git a/pac/atsamc21j/src/nvmctrl/addr.rs b/pac/atsamc21j/src/nvmctrl/addr.rs new file mode 100644 index 000000000000..74ed27736dac --- /dev/null +++ b/pac/atsamc21j/src/nvmctrl/addr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `ADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ADDR` reader - NVM Address"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - NVM Address"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x003f_ffff) | (value as u32 & 0x003f_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:21 - NVM Address"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new((self.bits & 0x003f_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:21 - NVM Address"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [addr](index.html) module"] +pub struct ADDR_SPEC; +impl crate::RegisterSpec for ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [addr::R](R) reader structure"] +impl crate::Readable for ADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [addr::W](W) writer structure"] +impl crate::Writable for ADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ADDR to value 0"] +impl crate::Resettable for ADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/nvmctrl/ctrla.rs b/pac/atsamc21j/src/nvmctrl/ctrla.rs new file mode 100644 index 000000000000..89f175771e4d --- /dev/null +++ b/pac/atsamc21j/src/nvmctrl/ctrla.rs @@ -0,0 +1,394 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "2: Erase Row - Erases the row addressed by the ADDR register."] + ER = 2, + #[doc = "4: Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register."] + WP = 4, + #[doc = "5: Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row."] + EAR = 5, + #[doc = "6: Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row."] + WAP = 6, + #[doc = "10: Security Flow Command"] + SF = 10, + #[doc = "15: Write lockbits"] + WL = 15, + #[doc = "26: RWW EEPROM area Erase Row - Erases the row addressed by the ADDR register."] + RWWEEER = 26, + #[doc = "28: RWW EEPROM Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register."] + RWWEEWP = 28, + #[doc = "64: Lock Region - Locks the region containing the address location in the ADDR register."] + LR = 64, + #[doc = "65: Unlock Region - Unlocks the region containing the address location in the ADDR register."] + UR = 65, + #[doc = "66: Sets the power reduction mode."] + SPRM = 66, + #[doc = "67: Clears the power reduction mode."] + CPRM = 67, + #[doc = "68: Page Buffer Clear - Clears the page buffer."] + PBC = 68, + #[doc = "69: Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row."] + SSB = 69, + #[doc = "70: Invalidate all cache lines."] + INVALL = 70, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 2 => Some(CMD_A::ER), + 4 => Some(CMD_A::WP), + 5 => Some(CMD_A::EAR), + 6 => Some(CMD_A::WAP), + 10 => Some(CMD_A::SF), + 15 => Some(CMD_A::WL), + 26 => Some(CMD_A::RWWEEER), + 28 => Some(CMD_A::RWWEEWP), + 64 => Some(CMD_A::LR), + 65 => Some(CMD_A::UR), + 66 => Some(CMD_A::SPRM), + 67 => Some(CMD_A::CPRM), + 68 => Some(CMD_A::PBC), + 69 => Some(CMD_A::SSB), + 70 => Some(CMD_A::INVALL), + _ => None, + } + } + #[doc = "Checks if the value of the field is `ER`"] + #[inline(always)] + pub fn is_er(&self) -> bool { + **self == CMD_A::ER + } + #[doc = "Checks if the value of the field is `WP`"] + #[inline(always)] + pub fn is_wp(&self) -> bool { + **self == CMD_A::WP + } + #[doc = "Checks if the value of the field is `EAR`"] + #[inline(always)] + pub fn is_ear(&self) -> bool { + **self == CMD_A::EAR + } + #[doc = "Checks if the value of the field is `WAP`"] + #[inline(always)] + pub fn is_wap(&self) -> bool { + **self == CMD_A::WAP + } + #[doc = "Checks if the value of the field is `SF`"] + #[inline(always)] + pub fn is_sf(&self) -> bool { + **self == CMD_A::SF + } + #[doc = "Checks if the value of the field is `WL`"] + #[inline(always)] + pub fn is_wl(&self) -> bool { + **self == CMD_A::WL + } + #[doc = "Checks if the value of the field is `RWWEEER`"] + #[inline(always)] + pub fn is_rwweeer(&self) -> bool { + **self == CMD_A::RWWEEER + } + #[doc = "Checks if the value of the field is `RWWEEWP`"] + #[inline(always)] + pub fn is_rwweewp(&self) -> bool { + **self == CMD_A::RWWEEWP + } + #[doc = "Checks if the value of the field is `LR`"] + #[inline(always)] + pub fn is_lr(&self) -> bool { + **self == CMD_A::LR + } + #[doc = "Checks if the value of the field is `UR`"] + #[inline(always)] + pub fn is_ur(&self) -> bool { + **self == CMD_A::UR + } + #[doc = "Checks if the value of the field is `SPRM`"] + #[inline(always)] + pub fn is_sprm(&self) -> bool { + **self == CMD_A::SPRM + } + #[doc = "Checks if the value of the field is `CPRM`"] + #[inline(always)] + pub fn is_cprm(&self) -> bool { + **self == CMD_A::CPRM + } + #[doc = "Checks if the value of the field is `PBC`"] + #[inline(always)] + pub fn is_pbc(&self) -> bool { + **self == CMD_A::PBC + } + #[doc = "Checks if the value of the field is `SSB`"] + #[inline(always)] + pub fn is_ssb(&self) -> bool { + **self == CMD_A::SSB + } + #[doc = "Checks if the value of the field is `INVALL`"] + #[inline(always)] + pub fn is_invall(&self) -> bool { + **self == CMD_A::INVALL + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Erase Row - Erases the row addressed by the ADDR register."] + #[inline(always)] + pub fn er(self) -> &'a mut W { + self.variant(CMD_A::ER) + } + #[doc = "Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register."] + #[inline(always)] + pub fn wp(self) -> &'a mut W { + self.variant(CMD_A::WP) + } + #[doc = "Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row."] + #[inline(always)] + pub fn ear(self) -> &'a mut W { + self.variant(CMD_A::EAR) + } + #[doc = "Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row."] + #[inline(always)] + pub fn wap(self) -> &'a mut W { + self.variant(CMD_A::WAP) + } + #[doc = "Security Flow Command"] + #[inline(always)] + pub fn sf(self) -> &'a mut W { + self.variant(CMD_A::SF) + } + #[doc = "Write lockbits"] + #[inline(always)] + pub fn wl(self) -> &'a mut W { + self.variant(CMD_A::WL) + } + #[doc = "RWW EEPROM area Erase Row - Erases the row addressed by the ADDR register."] + #[inline(always)] + pub fn rwweeer(self) -> &'a mut W { + self.variant(CMD_A::RWWEEER) + } + #[doc = "RWW EEPROM Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register."] + #[inline(always)] + pub fn rwweewp(self) -> &'a mut W { + self.variant(CMD_A::RWWEEWP) + } + #[doc = "Lock Region - Locks the region containing the address location in the ADDR register."] + #[inline(always)] + pub fn lr(self) -> &'a mut W { + self.variant(CMD_A::LR) + } + #[doc = "Unlock Region - Unlocks the region containing the address location in the ADDR register."] + #[inline(always)] + pub fn ur(self) -> &'a mut W { + self.variant(CMD_A::UR) + } + #[doc = "Sets the power reduction mode."] + #[inline(always)] + pub fn sprm(self) -> &'a mut W { + self.variant(CMD_A::SPRM) + } + #[doc = "Clears the power reduction mode."] + #[inline(always)] + pub fn cprm(self) -> &'a mut W { + self.variant(CMD_A::CPRM) + } + #[doc = "Page Buffer Clear - Clears the page buffer."] + #[inline(always)] + pub fn pbc(self) -> &'a mut W { + self.variant(CMD_A::PBC) + } + #[doc = "Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row."] + #[inline(always)] + pub fn ssb(self) -> &'a mut W { + self.variant(CMD_A::SSB) + } + #[doc = "Invalidate all cache lines."] + #[inline(always)] + pub fn invall(self) -> &'a mut W { + self.variant(CMD_A::INVALL) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x7f) | (value as u16 & 0x7f); + self.w + } +} +#[doc = "Command Execution\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMDEX_A { + #[doc = "165: Execution Key"] + KEY = 165, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMDEX_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMDEX` reader - Command Execution"] +pub struct CMDEX_R(crate::FieldReader); +impl CMDEX_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMDEX_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 165 => Some(CMDEX_A::KEY), + _ => None, + } + } + #[doc = "Checks if the value of the field is `KEY`"] + #[inline(always)] + pub fn is_key(&self) -> bool { + **self == CMDEX_A::KEY + } +} +impl core::ops::Deref for CMDEX_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMDEX` writer - Command Execution"] +pub struct CMDEX_W<'a> { + w: &'a mut W, +} +impl<'a> CMDEX_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMDEX_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Execution Key"] + #[inline(always)] + pub fn key(self) -> &'a mut W { + self.variant(CMDEX_A::KEY) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u16 & 0xff) << 8); + self.w + } +} +impl R { + #[doc = "Bits 0:6 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bits 8:15 - Command Execution"] + #[inline(always)] + pub fn cmdex(&self) -> CMDEX_R { + CMDEX_R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:6 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Bits 8:15 - Command Execution"] + #[inline(always)] + pub fn cmdex(&mut self) -> CMDEX_W { + CMDEX_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/nvmctrl/ctrlb.rs b/pac/atsamc21j/src/nvmctrl/ctrlb.rs new file mode 100644 index 000000000000..6162d0d4ade0 --- /dev/null +++ b/pac/atsamc21j/src/nvmctrl/ctrlb.rs @@ -0,0 +1,447 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "NVM Read Wait States\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum RWS_A { + #[doc = "0: Single Auto Wait State"] + SINGLE = 0, + #[doc = "1: Half Auto Wait State"] + HALF = 1, + #[doc = "2: Dual Auto Wait State"] + DUAL = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RWS_A) -> Self { + variant as _ + } +} +#[doc = "Field `RWS` reader - NVM Read Wait States"] +pub struct RWS_R(crate::FieldReader); +impl RWS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RWS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(RWS_A::SINGLE), + 1 => Some(RWS_A::HALF), + 2 => Some(RWS_A::DUAL), + _ => None, + } + } + #[doc = "Checks if the value of the field is `SINGLE`"] + #[inline(always)] + pub fn is_single(&self) -> bool { + **self == RWS_A::SINGLE + } + #[doc = "Checks if the value of the field is `HALF`"] + #[inline(always)] + pub fn is_half(&self) -> bool { + **self == RWS_A::HALF + } + #[doc = "Checks if the value of the field is `DUAL`"] + #[inline(always)] + pub fn is_dual(&self) -> bool { + **self == RWS_A::DUAL + } +} +impl core::ops::Deref for RWS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RWS` writer - NVM Read Wait States"] +pub struct RWS_W<'a> { + w: &'a mut W, +} +impl<'a> RWS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RWS_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Single Auto Wait State"] + #[inline(always)] + pub fn single(self) -> &'a mut W { + self.variant(RWS_A::SINGLE) + } + #[doc = "Half Auto Wait State"] + #[inline(always)] + pub fn half(self) -> &'a mut W { + self.variant(RWS_A::HALF) + } + #[doc = "Dual Auto Wait State"] + #[inline(always)] + pub fn dual(self) -> &'a mut W { + self.variant(RWS_A::DUAL) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 1)) | ((value as u32 & 0x0f) << 1); + self.w + } +} +#[doc = "Field `MANW` reader - Manual Write"] +pub struct MANW_R(crate::FieldReader); +impl MANW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MANW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MANW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MANW` writer - Manual Write"] +pub struct MANW_W<'a> { + w: &'a mut W, +} +impl<'a> MANW_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Power Reduction Mode during Sleep\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SLEEPPRM_A { + #[doc = "0: NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access."] + WAKEONACCESS = 0, + #[doc = "1: NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep."] + WAKEUPINSTANT = 1, + #[doc = "3: Auto power reduction disabled."] + DISABLED = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SLEEPPRM_A) -> Self { + variant as _ + } +} +#[doc = "Field `SLEEPPRM` reader - Power Reduction Mode during Sleep"] +pub struct SLEEPPRM_R(crate::FieldReader); +impl SLEEPPRM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SLEEPPRM_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SLEEPPRM_A::WAKEONACCESS), + 1 => Some(SLEEPPRM_A::WAKEUPINSTANT), + 3 => Some(SLEEPPRM_A::DISABLED), + _ => None, + } + } + #[doc = "Checks if the value of the field is `WAKEONACCESS`"] + #[inline(always)] + pub fn is_wakeonaccess(&self) -> bool { + **self == SLEEPPRM_A::WAKEONACCESS + } + #[doc = "Checks if the value of the field is `WAKEUPINSTANT`"] + #[inline(always)] + pub fn is_wakeupinstant(&self) -> bool { + **self == SLEEPPRM_A::WAKEUPINSTANT + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + **self == SLEEPPRM_A::DISABLED + } +} +impl core::ops::Deref for SLEEPPRM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLEEPPRM` writer - Power Reduction Mode during Sleep"] +pub struct SLEEPPRM_W<'a> { + w: &'a mut W, +} +impl<'a> SLEEPPRM_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SLEEPPRM_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access."] + #[inline(always)] + pub fn wakeonaccess(self) -> &'a mut W { + self.variant(SLEEPPRM_A::WAKEONACCESS) + } + #[doc = "NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep."] + #[inline(always)] + pub fn wakeupinstant(self) -> &'a mut W { + self.variant(SLEEPPRM_A::WAKEUPINSTANT) + } + #[doc = "Auto power reduction disabled."] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(SLEEPPRM_A::DISABLED) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 8)) | ((value as u32 & 0x03) << 8); + self.w + } +} +#[doc = "NVMCTRL Read Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum READMODE_A { + #[doc = "0: The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance."] + NO_MISS_PENALTY = 0, + #[doc = "1: Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time."] + LOW_POWER = 1, + #[doc = "2: The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings."] + DETERMINISTIC = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: READMODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `READMODE` reader - NVMCTRL Read Mode"] +pub struct READMODE_R(crate::FieldReader); +impl READMODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + READMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(READMODE_A::NO_MISS_PENALTY), + 1 => Some(READMODE_A::LOW_POWER), + 2 => Some(READMODE_A::DETERMINISTIC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NO_MISS_PENALTY`"] + #[inline(always)] + pub fn is_no_miss_penalty(&self) -> bool { + **self == READMODE_A::NO_MISS_PENALTY + } + #[doc = "Checks if the value of the field is `LOW_POWER`"] + #[inline(always)] + pub fn is_low_power(&self) -> bool { + **self == READMODE_A::LOW_POWER + } + #[doc = "Checks if the value of the field is `DETERMINISTIC`"] + #[inline(always)] + pub fn is_deterministic(&self) -> bool { + **self == READMODE_A::DETERMINISTIC + } +} +impl core::ops::Deref for READMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `READMODE` writer - NVMCTRL Read Mode"] +pub struct READMODE_W<'a> { + w: &'a mut W, +} +impl<'a> READMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: READMODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance."] + #[inline(always)] + pub fn no_miss_penalty(self) -> &'a mut W { + self.variant(READMODE_A::NO_MISS_PENALTY) + } + #[doc = "Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time."] + #[inline(always)] + pub fn low_power(self) -> &'a mut W { + self.variant(READMODE_A::LOW_POWER) + } + #[doc = "The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings."] + #[inline(always)] + pub fn deterministic(self) -> &'a mut W { + self.variant(READMODE_A::DETERMINISTIC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Field `CACHEDIS` reader - Cache Disable"] +pub struct CACHEDIS_R(crate::FieldReader); +impl CACHEDIS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CACHEDIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CACHEDIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CACHEDIS` writer - Cache Disable"] +pub struct CACHEDIS_W<'a> { + w: &'a mut W, +} +impl<'a> CACHEDIS_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 18)) | ((value as u32 & 0x03) << 18); + self.w + } +} +impl R { + #[doc = "Bits 1:4 - NVM Read Wait States"] + #[inline(always)] + pub fn rws(&self) -> RWS_R { + RWS_R::new(((self.bits >> 1) & 0x0f) as u8) + } + #[doc = "Bit 7 - Manual Write"] + #[inline(always)] + pub fn manw(&self) -> MANW_R { + MANW_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:9 - Power Reduction Mode during Sleep"] + #[inline(always)] + pub fn sleepprm(&self) -> SLEEPPRM_R { + SLEEPPRM_R::new(((self.bits >> 8) & 0x03) as u8) + } + #[doc = "Bits 16:17 - NVMCTRL Read Mode"] + #[inline(always)] + pub fn readmode(&self) -> READMODE_R { + READMODE_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bits 18:19 - Cache Disable"] + #[inline(always)] + pub fn cachedis(&self) -> CACHEDIS_R { + CACHEDIS_R::new(((self.bits >> 18) & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 1:4 - NVM Read Wait States"] + #[inline(always)] + pub fn rws(&mut self) -> RWS_W { + RWS_W { w: self } + } + #[doc = "Bit 7 - Manual Write"] + #[inline(always)] + pub fn manw(&mut self) -> MANW_W { + MANW_W { w: self } + } + #[doc = "Bits 8:9 - Power Reduction Mode during Sleep"] + #[inline(always)] + pub fn sleepprm(&mut self) -> SLEEPPRM_W { + SLEEPPRM_W { w: self } + } + #[doc = "Bits 16:17 - NVMCTRL Read Mode"] + #[inline(always)] + pub fn readmode(&mut self) -> READMODE_W { + READMODE_W { w: self } + } + #[doc = "Bits 18:19 - Cache Disable"] + #[inline(always)] + pub fn cachedis(&mut self) -> CACHEDIS_W { + CACHEDIS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0x80"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x80 + } +} diff --git a/pac/atsamc21j/src/nvmctrl/intenclr.rs b/pac/atsamc21j/src/nvmctrl/intenclr.rs new file mode 100644 index 000000000000..6e7db4b52c9d --- /dev/null +++ b/pac/atsamc21j/src/nvmctrl/intenclr.rs @@ -0,0 +1,160 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `READY` reader - NVM Ready Interrupt Enable"] +pub struct READY_R(crate::FieldReader); +impl READY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + READY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for READY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `READY` writer - NVM Ready Interrupt Enable"] +pub struct READY_W<'a> { + w: &'a mut W, +} +impl<'a> READY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERROR` reader - Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - NVM Ready Interrupt Enable"] + #[inline(always)] + pub fn ready(&self) -> READY_R { + READY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - NVM Ready Interrupt Enable"] + #[inline(always)] + pub fn ready(&mut self) -> READY_W { + READY_W { w: self } + } + #[doc = "Bit 1 - Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/nvmctrl/intenset.rs b/pac/atsamc21j/src/nvmctrl/intenset.rs new file mode 100644 index 000000000000..ba8698e86c3e --- /dev/null +++ b/pac/atsamc21j/src/nvmctrl/intenset.rs @@ -0,0 +1,160 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `READY` reader - NVM Ready Interrupt Enable"] +pub struct READY_R(crate::FieldReader); +impl READY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + READY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for READY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `READY` writer - NVM Ready Interrupt Enable"] +pub struct READY_W<'a> { + w: &'a mut W, +} +impl<'a> READY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERROR` reader - Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - NVM Ready Interrupt Enable"] + #[inline(always)] + pub fn ready(&self) -> READY_R { + READY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - NVM Ready Interrupt Enable"] + #[inline(always)] + pub fn ready(&mut self) -> READY_W { + READY_W { w: self } + } + #[doc = "Bit 1 - Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/nvmctrl/intflag.rs b/pac/atsamc21j/src/nvmctrl/intflag.rs new file mode 100644 index 000000000000..1b30cdddf25d --- /dev/null +++ b/pac/atsamc21j/src/nvmctrl/intflag.rs @@ -0,0 +1,160 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `READY` reader - NVM Ready"] +pub struct READY_R(crate::FieldReader); +impl READY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + READY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for READY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `READY` writer - NVM Ready"] +pub struct READY_W<'a> { + w: &'a mut W, +} +impl<'a> READY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERROR` reader - Error"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Error"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - NVM Ready"] + #[inline(always)] + pub fn ready(&self) -> READY_R { + READY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Error"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - NVM Ready"] + #[inline(always)] + pub fn ready(&mut self) -> READY_W { + READY_W { w: self } + } + #[doc = "Bit 1 - Error"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/nvmctrl/lock.rs b/pac/atsamc21j/src/nvmctrl/lock.rs new file mode 100644 index 000000000000..dbcf37a8107f --- /dev/null +++ b/pac/atsamc21j/src/nvmctrl/lock.rs @@ -0,0 +1,103 @@ +#[doc = "Register `LOCK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `LOCK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `LOCK` reader - Region Lock Bits"] +pub struct LOCK_R(crate::FieldReader); +impl LOCK_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + LOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LOCK` writer - Region Lock Bits"] +pub struct LOCK_W<'a> { + w: &'a mut W, +} +impl<'a> LOCK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Region Lock Bits"] + #[inline(always)] + pub fn lock(&self) -> LOCK_R { + LOCK_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Region Lock Bits"] + #[inline(always)] + pub fn lock(&mut self) -> LOCK_W { + LOCK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Lock Section\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lock](index.html) module"] +pub struct LOCK_SPEC; +impl crate::RegisterSpec for LOCK_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [lock::R](R) reader structure"] +impl crate::Readable for LOCK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [lock::W](W) writer structure"] +impl crate::Writable for LOCK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets LOCK to value 0"] +impl crate::Resettable for LOCK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/nvmctrl/param.rs b/pac/atsamc21j/src/nvmctrl/param.rs new file mode 100644 index 000000000000..d9197cf16de4 --- /dev/null +++ b/pac/atsamc21j/src/nvmctrl/param.rs @@ -0,0 +1,304 @@ +#[doc = "Register `PARAM` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PARAM` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `NVMP` reader - NVM Pages"] +pub struct NVMP_R(crate::FieldReader); +impl NVMP_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + NVMP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NVMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NVMP` writer - NVM Pages"] +pub struct NVMP_W<'a> { + w: &'a mut W, +} +impl<'a> NVMP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +#[doc = "Page Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PSZ_A { + #[doc = "0: 8 bytes"] + _8 = 0, + #[doc = "1: 16 bytes"] + _16 = 1, + #[doc = "2: 32 bytes"] + _32 = 2, + #[doc = "3: 64 bytes"] + _64 = 3, + #[doc = "4: 128 bytes"] + _128 = 4, + #[doc = "5: 256 bytes"] + _256 = 5, + #[doc = "6: 512 bytes"] + _512 = 6, + #[doc = "7: 1024 bytes"] + _1024 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PSZ_A) -> Self { + variant as _ + } +} +#[doc = "Field `PSZ` reader - Page Size"] +pub struct PSZ_R(crate::FieldReader); +impl PSZ_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PSZ_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PSZ_A { + match self.bits { + 0 => PSZ_A::_8, + 1 => PSZ_A::_16, + 2 => PSZ_A::_32, + 3 => PSZ_A::_64, + 4 => PSZ_A::_128, + 5 => PSZ_A::_256, + 6 => PSZ_A::_512, + 7 => PSZ_A::_1024, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `_8`"] + #[inline(always)] + pub fn is_8(&self) -> bool { + **self == PSZ_A::_8 + } + #[doc = "Checks if the value of the field is `_16`"] + #[inline(always)] + pub fn is_16(&self) -> bool { + **self == PSZ_A::_16 + } + #[doc = "Checks if the value of the field is `_32`"] + #[inline(always)] + pub fn is_32(&self) -> bool { + **self == PSZ_A::_32 + } + #[doc = "Checks if the value of the field is `_64`"] + #[inline(always)] + pub fn is_64(&self) -> bool { + **self == PSZ_A::_64 + } + #[doc = "Checks if the value of the field is `_128`"] + #[inline(always)] + pub fn is_128(&self) -> bool { + **self == PSZ_A::_128 + } + #[doc = "Checks if the value of the field is `_256`"] + #[inline(always)] + pub fn is_256(&self) -> bool { + **self == PSZ_A::_256 + } + #[doc = "Checks if the value of the field is `_512`"] + #[inline(always)] + pub fn is_512(&self) -> bool { + **self == PSZ_A::_512 + } + #[doc = "Checks if the value of the field is `_1024`"] + #[inline(always)] + pub fn is_1024(&self) -> bool { + **self == PSZ_A::_1024 + } +} +impl core::ops::Deref for PSZ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PSZ` writer - Page Size"] +pub struct PSZ_W<'a> { + w: &'a mut W, +} +impl<'a> PSZ_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PSZ_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "8 bytes"] + #[inline(always)] + pub fn _8(self) -> &'a mut W { + self.variant(PSZ_A::_8) + } + #[doc = "16 bytes"] + #[inline(always)] + pub fn _16(self) -> &'a mut W { + self.variant(PSZ_A::_16) + } + #[doc = "32 bytes"] + #[inline(always)] + pub fn _32(self) -> &'a mut W { + self.variant(PSZ_A::_32) + } + #[doc = "64 bytes"] + #[inline(always)] + pub fn _64(self) -> &'a mut W { + self.variant(PSZ_A::_64) + } + #[doc = "128 bytes"] + #[inline(always)] + pub fn _128(self) -> &'a mut W { + self.variant(PSZ_A::_128) + } + #[doc = "256 bytes"] + #[inline(always)] + pub fn _256(self) -> &'a mut W { + self.variant(PSZ_A::_256) + } + #[doc = "512 bytes"] + #[inline(always)] + pub fn _512(self) -> &'a mut W { + self.variant(PSZ_A::_512) + } + #[doc = "1024 bytes"] + #[inline(always)] + pub fn _1024(self) -> &'a mut W { + self.variant(PSZ_A::_1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 16)) | ((value as u32 & 0x07) << 16); + self.w + } +} +#[doc = "Field `RWWEEP` reader - RWW EEPROM Pages"] +pub struct RWWEEP_R(crate::FieldReader); +impl RWWEEP_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + RWWEEP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RWWEEP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RWWEEP` writer - RWW EEPROM Pages"] +pub struct RWWEEP_W<'a> { + w: &'a mut W, +} +impl<'a> RWWEEP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0fff << 20)) | ((value as u32 & 0x0fff) << 20); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - NVM Pages"] + #[inline(always)] + pub fn nvmp(&self) -> NVMP_R { + NVMP_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:18 - Page Size"] + #[inline(always)] + pub fn psz(&self) -> PSZ_R { + PSZ_R::new(((self.bits >> 16) & 0x07) as u8) + } + #[doc = "Bits 20:31 - RWW EEPROM Pages"] + #[inline(always)] + pub fn rwweep(&self) -> RWWEEP_R { + RWWEEP_R::new(((self.bits >> 20) & 0x0fff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - NVM Pages"] + #[inline(always)] + pub fn nvmp(&mut self) -> NVMP_W { + NVMP_W { w: self } + } + #[doc = "Bits 16:18 - Page Size"] + #[inline(always)] + pub fn psz(&mut self) -> PSZ_W { + PSZ_W { w: self } + } + #[doc = "Bits 20:31 - RWW EEPROM Pages"] + #[inline(always)] + pub fn rwweep(&mut self) -> RWWEEP_W { + RWWEEP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "NVM Parameter\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [param](index.html) module"] +pub struct PARAM_SPEC; +impl crate::RegisterSpec for PARAM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [param::R](R) reader structure"] +impl crate::Readable for PARAM_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [param::W](W) writer structure"] +impl crate::Writable for PARAM_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PARAM to value 0"] +impl crate::Resettable for PARAM_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/nvmctrl/pbldata0.rs b/pac/atsamc21j/src/nvmctrl/pbldata0.rs new file mode 100644 index 000000000000..ff2effaf4d89 --- /dev/null +++ b/pac/atsamc21j/src/nvmctrl/pbldata0.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PBLDATA0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Page Buffer Load Data 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pbldata0](index.html) module"] +pub struct PBLDATA0_SPEC; +impl crate::RegisterSpec for PBLDATA0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pbldata0::R](R) reader structure"] +impl crate::Readable for PBLDATA0_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PBLDATA0 to value 0"] +impl crate::Resettable for PBLDATA0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/nvmctrl/pbldata1.rs b/pac/atsamc21j/src/nvmctrl/pbldata1.rs new file mode 100644 index 000000000000..9fc6404691c5 --- /dev/null +++ b/pac/atsamc21j/src/nvmctrl/pbldata1.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PBLDATA1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Page Buffer Load Data 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pbldata1](index.html) module"] +pub struct PBLDATA1_SPEC; +impl crate::RegisterSpec for PBLDATA1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pbldata1::R](R) reader structure"] +impl crate::Readable for PBLDATA1_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PBLDATA1 to value 0"] +impl crate::Resettable for PBLDATA1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/nvmctrl/status.rs b/pac/atsamc21j/src/nvmctrl/status.rs new file mode 100644 index 000000000000..ce849015560e --- /dev/null +++ b/pac/atsamc21j/src/nvmctrl/status.rs @@ -0,0 +1,348 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PRM` reader - Power Reduction Mode"] +pub struct PRM_R(crate::FieldReader); +impl PRM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PRM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PRM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRM` writer - Power Reduction Mode"] +pub struct PRM_W<'a> { + w: &'a mut W, +} +impl<'a> PRM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `LOAD` reader - NVM Page Buffer Active Loading"] +pub struct LOAD_R(crate::FieldReader); +impl LOAD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LOAD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOAD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LOAD` writer - NVM Page Buffer Active Loading"] +pub struct LOAD_W<'a> { + w: &'a mut W, +} +impl<'a> LOAD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PROGE` reader - Programming Error Status"] +pub struct PROGE_R(crate::FieldReader); +impl PROGE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PROGE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PROGE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PROGE` writer - Programming Error Status"] +pub struct PROGE_W<'a> { + w: &'a mut W, +} +impl<'a> PROGE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `LOCKE` reader - Lock Error Status"] +pub struct LOCKE_R(crate::FieldReader); +impl LOCKE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LOCKE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOCKE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LOCKE` writer - Lock Error Status"] +pub struct LOCKE_W<'a> { + w: &'a mut W, +} +impl<'a> LOCKE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `NVME` reader - NVM Error"] +pub struct NVME_R(crate::FieldReader); +impl NVME_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NVME_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NVME_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NVME` writer - NVM Error"] +pub struct NVME_W<'a> { + w: &'a mut W, +} +impl<'a> NVME_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `SB` reader - Security Bit Status"] +pub struct SB_R(crate::FieldReader); +impl SB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SB` writer - Security Bit Status"] +pub struct SB_W<'a> { + w: &'a mut W, +} +impl<'a> SB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +impl R { + #[doc = "Bit 0 - Power Reduction Mode"] + #[inline(always)] + pub fn prm(&self) -> PRM_R { + PRM_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - NVM Page Buffer Active Loading"] + #[inline(always)] + pub fn load(&self) -> LOAD_R { + LOAD_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Programming Error Status"] + #[inline(always)] + pub fn proge(&self) -> PROGE_R { + PROGE_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Lock Error Status"] + #[inline(always)] + pub fn locke(&self) -> LOCKE_R { + LOCKE_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - NVM Error"] + #[inline(always)] + pub fn nvme(&self) -> NVME_R { + NVME_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 8 - Security Bit Status"] + #[inline(always)] + pub fn sb(&self) -> SB_R { + SB_R::new(((self.bits >> 8) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Power Reduction Mode"] + #[inline(always)] + pub fn prm(&mut self) -> PRM_W { + PRM_W { w: self } + } + #[doc = "Bit 1 - NVM Page Buffer Active Loading"] + #[inline(always)] + pub fn load(&mut self) -> LOAD_W { + LOAD_W { w: self } + } + #[doc = "Bit 2 - Programming Error Status"] + #[inline(always)] + pub fn proge(&mut self) -> PROGE_W { + PROGE_W { w: self } + } + #[doc = "Bit 3 - Lock Error Status"] + #[inline(always)] + pub fn locke(&mut self) -> LOCKE_W { + LOCKE_W { w: self } + } + #[doc = "Bit 4 - NVM Error"] + #[inline(always)] + pub fn nvme(&mut self) -> NVME_W { + NVME_W { w: self } + } + #[doc = "Bit 8 - Security Bit Status"] + #[inline(always)] + pub fn sb(&mut self) -> SB_W { + SB_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/osc32kctrl.rs b/pac/atsamc21j/src/osc32kctrl.rs new file mode 100644 index 000000000000..263cd2f61d59 --- /dev/null +++ b/pac/atsamc21j/src/osc32kctrl.rs @@ -0,0 +1,64 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x04 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x08 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x0c - Power and Clocks Status"] + pub status: crate::Reg, + #[doc = "0x10 - Clock selection"] + pub rtcctrl: crate::Reg, + #[doc = "0x14 - 32kHz External Crystal Oscillator (XOSC32K) Control"] + pub xosc32k: crate::Reg, + #[doc = "0x16 - Clock Failure Detector Control"] + pub cfdctrl: crate::Reg, + #[doc = "0x17 - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x18 - 32kHz Internal Oscillator (OSC32K) Control"] + pub osc32k: crate::Reg, + #[doc = "0x1c - 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control"] + pub osculp32k: crate::Reg, +} +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Power and Clocks Status"] +pub mod status; +#[doc = "RTCCTRL register accessor: an alias for `Reg`"] +pub type RTCCTRL = crate::Reg; +#[doc = "Clock selection"] +pub mod rtcctrl; +#[doc = "XOSC32K register accessor: an alias for `Reg`"] +pub type XOSC32K = crate::Reg; +#[doc = "32kHz External Crystal Oscillator (XOSC32K) Control"] +pub mod xosc32k; +#[doc = "CFDCTRL register accessor: an alias for `Reg`"] +pub type CFDCTRL = crate::Reg; +#[doc = "Clock Failure Detector Control"] +pub mod cfdctrl; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "OSC32K register accessor: an alias for `Reg`"] +pub type OSC32K = crate::Reg; +#[doc = "32kHz Internal Oscillator (OSC32K) Control"] +pub mod osc32k; +#[doc = "OSCULP32K register accessor: an alias for `Reg`"] +pub type OSCULP32K = crate::Reg; +#[doc = "32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control"] +pub mod osculp32k; diff --git a/pac/atsamc21j/src/osc32kctrl/cfdctrl.rs b/pac/atsamc21j/src/osc32kctrl/cfdctrl.rs new file mode 100644 index 000000000000..492a86e1a5a7 --- /dev/null +++ b/pac/atsamc21j/src/osc32kctrl/cfdctrl.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CFDCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CFDCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CFDEN` reader - Clock Failure Detector Enable"] +pub struct CFDEN_R(crate::FieldReader); +impl CFDEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFDEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFDEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFDEN` writer - Clock Failure Detector Enable"] +pub struct CFDEN_W<'a> { + w: &'a mut W, +} +impl<'a> CFDEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SWBACK` reader - Clock Switch Back"] +pub struct SWBACK_R(crate::FieldReader); +impl SWBACK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWBACK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWBACK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWBACK` writer - Clock Switch Back"] +pub struct SWBACK_W<'a> { + w: &'a mut W, +} +impl<'a> SWBACK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CFDPRESC` reader - Clock Failure Detector Prescaler"] +pub struct CFDPRESC_R(crate::FieldReader); +impl CFDPRESC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFDPRESC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFDPRESC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFDPRESC` writer - Clock Failure Detector Prescaler"] +pub struct CFDPRESC_W<'a> { + w: &'a mut W, +} +impl<'a> CFDPRESC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Clock Failure Detector Enable"] + #[inline(always)] + pub fn cfden(&self) -> CFDEN_R { + CFDEN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Clock Switch Back"] + #[inline(always)] + pub fn swback(&self) -> SWBACK_R { + SWBACK_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Clock Failure Detector Prescaler"] + #[inline(always)] + pub fn cfdpresc(&self) -> CFDPRESC_R { + CFDPRESC_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Clock Failure Detector Enable"] + #[inline(always)] + pub fn cfden(&mut self) -> CFDEN_W { + CFDEN_W { w: self } + } + #[doc = "Bit 1 - Clock Switch Back"] + #[inline(always)] + pub fn swback(&mut self) -> SWBACK_W { + SWBACK_W { w: self } + } + #[doc = "Bit 2 - Clock Failure Detector Prescaler"] + #[inline(always)] + pub fn cfdpresc(&mut self) -> CFDPRESC_W { + CFDPRESC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Clock Failure Detector Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cfdctrl](index.html) module"] +pub struct CFDCTRL_SPEC; +impl crate::RegisterSpec for CFDCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [cfdctrl::R](R) reader structure"] +impl crate::Readable for CFDCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cfdctrl::W](W) writer structure"] +impl crate::Writable for CFDCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CFDCTRL to value 0"] +impl crate::Resettable for CFDCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/osc32kctrl/evctrl.rs b/pac/atsamc21j/src/osc32kctrl/evctrl.rs new file mode 100644 index 000000000000..e22ba62f0fe2 --- /dev/null +++ b/pac/atsamc21j/src/osc32kctrl/evctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CFDEO` reader - Clock Failure Detector Event Output Enable"] +pub struct CFDEO_R(crate::FieldReader); +impl CFDEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFDEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFDEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFDEO` writer - Clock Failure Detector Event Output Enable"] +pub struct CFDEO_W<'a> { + w: &'a mut W, +} +impl<'a> CFDEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Clock Failure Detector Event Output Enable"] + #[inline(always)] + pub fn cfdeo(&self) -> CFDEO_R { + CFDEO_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Clock Failure Detector Event Output Enable"] + #[inline(always)] + pub fn cfdeo(&mut self) -> CFDEO_W { + CFDEO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/osc32kctrl/intenclr.rs b/pac/atsamc21j/src/osc32kctrl/intenclr.rs new file mode 100644 index 000000000000..7e330c8de495 --- /dev/null +++ b/pac/atsamc21j/src/osc32kctrl/intenclr.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XOSC32KRDY` reader - XOSC32K Ready Interrupt Enable"] +pub struct XOSC32KRDY_R(crate::FieldReader); +impl XOSC32KRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSC32KRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSC32KRDY` writer - XOSC32K Ready Interrupt Enable"] +pub struct XOSC32KRDY_W<'a> { + w: &'a mut W, +} +impl<'a> XOSC32KRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `OSC32KRDY` reader - OSC32K Ready Interrupt Enable"] +pub struct OSC32KRDY_R(crate::FieldReader); +impl OSC32KRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC32KRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC32KRDY` writer - OSC32K Ready Interrupt Enable"] +pub struct OSC32KRDY_W<'a> { + w: &'a mut W, +} +impl<'a> OSC32KRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CLKFAIL` reader - XOSC32K Clock Failure Detector Interrupt Enable"] +pub struct CLKFAIL_R(crate::FieldReader); +impl CLKFAIL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKFAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKFAIL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKFAIL` writer - XOSC32K Clock Failure Detector Interrupt Enable"] +pub struct CLKFAIL_W<'a> { + w: &'a mut W, +} +impl<'a> CLKFAIL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - XOSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn xosc32krdy(&self) -> XOSC32KRDY_R { + XOSC32KRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - OSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn osc32krdy(&self) -> OSC32KRDY_R { + OSC32KRDY_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - XOSC32K Clock Failure Detector Interrupt Enable"] + #[inline(always)] + pub fn clkfail(&self) -> CLKFAIL_R { + CLKFAIL_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - XOSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn xosc32krdy(&mut self) -> XOSC32KRDY_W { + XOSC32KRDY_W { w: self } + } + #[doc = "Bit 1 - OSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn osc32krdy(&mut self) -> OSC32KRDY_W { + OSC32KRDY_W { w: self } + } + #[doc = "Bit 2 - XOSC32K Clock Failure Detector Interrupt Enable"] + #[inline(always)] + pub fn clkfail(&mut self) -> CLKFAIL_W { + CLKFAIL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/osc32kctrl/intenset.rs b/pac/atsamc21j/src/osc32kctrl/intenset.rs new file mode 100644 index 000000000000..e853d40049f2 --- /dev/null +++ b/pac/atsamc21j/src/osc32kctrl/intenset.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XOSC32KRDY` reader - XOSC32K Ready Interrupt Enable"] +pub struct XOSC32KRDY_R(crate::FieldReader); +impl XOSC32KRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSC32KRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSC32KRDY` writer - XOSC32K Ready Interrupt Enable"] +pub struct XOSC32KRDY_W<'a> { + w: &'a mut W, +} +impl<'a> XOSC32KRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `OSC32KRDY` reader - OSC32K Ready Interrupt Enable"] +pub struct OSC32KRDY_R(crate::FieldReader); +impl OSC32KRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC32KRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC32KRDY` writer - OSC32K Ready Interrupt Enable"] +pub struct OSC32KRDY_W<'a> { + w: &'a mut W, +} +impl<'a> OSC32KRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CLKFAIL` reader - XOSC32K Clock Failure Detector Interrupt Enable"] +pub struct CLKFAIL_R(crate::FieldReader); +impl CLKFAIL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKFAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKFAIL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKFAIL` writer - XOSC32K Clock Failure Detector Interrupt Enable"] +pub struct CLKFAIL_W<'a> { + w: &'a mut W, +} +impl<'a> CLKFAIL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - XOSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn xosc32krdy(&self) -> XOSC32KRDY_R { + XOSC32KRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - OSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn osc32krdy(&self) -> OSC32KRDY_R { + OSC32KRDY_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - XOSC32K Clock Failure Detector Interrupt Enable"] + #[inline(always)] + pub fn clkfail(&self) -> CLKFAIL_R { + CLKFAIL_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - XOSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn xosc32krdy(&mut self) -> XOSC32KRDY_W { + XOSC32KRDY_W { w: self } + } + #[doc = "Bit 1 - OSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn osc32krdy(&mut self) -> OSC32KRDY_W { + OSC32KRDY_W { w: self } + } + #[doc = "Bit 2 - XOSC32K Clock Failure Detector Interrupt Enable"] + #[inline(always)] + pub fn clkfail(&mut self) -> CLKFAIL_W { + CLKFAIL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/osc32kctrl/intflag.rs b/pac/atsamc21j/src/osc32kctrl/intflag.rs new file mode 100644 index 000000000000..9ca42439429d --- /dev/null +++ b/pac/atsamc21j/src/osc32kctrl/intflag.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XOSC32KRDY` reader - XOSC32K Ready"] +pub struct XOSC32KRDY_R(crate::FieldReader); +impl XOSC32KRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSC32KRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSC32KRDY` writer - XOSC32K Ready"] +pub struct XOSC32KRDY_W<'a> { + w: &'a mut W, +} +impl<'a> XOSC32KRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `OSC32KRDY` reader - OSC32K Ready"] +pub struct OSC32KRDY_R(crate::FieldReader); +impl OSC32KRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC32KRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC32KRDY` writer - OSC32K Ready"] +pub struct OSC32KRDY_W<'a> { + w: &'a mut W, +} +impl<'a> OSC32KRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CLKFAIL` reader - XOSC32K Clock Failure Detector"] +pub struct CLKFAIL_R(crate::FieldReader); +impl CLKFAIL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKFAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKFAIL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKFAIL` writer - XOSC32K Clock Failure Detector"] +pub struct CLKFAIL_W<'a> { + w: &'a mut W, +} +impl<'a> CLKFAIL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - XOSC32K Ready"] + #[inline(always)] + pub fn xosc32krdy(&self) -> XOSC32KRDY_R { + XOSC32KRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - OSC32K Ready"] + #[inline(always)] + pub fn osc32krdy(&self) -> OSC32KRDY_R { + OSC32KRDY_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - XOSC32K Clock Failure Detector"] + #[inline(always)] + pub fn clkfail(&self) -> CLKFAIL_R { + CLKFAIL_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - XOSC32K Ready"] + #[inline(always)] + pub fn xosc32krdy(&mut self) -> XOSC32KRDY_W { + XOSC32KRDY_W { w: self } + } + #[doc = "Bit 1 - OSC32K Ready"] + #[inline(always)] + pub fn osc32krdy(&mut self) -> OSC32KRDY_W { + OSC32KRDY_W { w: self } + } + #[doc = "Bit 2 - XOSC32K Clock Failure Detector"] + #[inline(always)] + pub fn clkfail(&mut self) -> CLKFAIL_W { + CLKFAIL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/osc32kctrl/osc32k.rs b/pac/atsamc21j/src/osc32kctrl/osc32k.rs new file mode 100644 index 000000000000..aa32cb287aa7 --- /dev/null +++ b/pac/atsamc21j/src/osc32kctrl/osc32k.rs @@ -0,0 +1,549 @@ +#[doc = "Register `OSC32K` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OSC32K` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Oscillator Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Oscillator Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `EN32K` reader - 32kHz Output Enable"] +pub struct EN32K_R(crate::FieldReader); +impl EN32K_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EN32K_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EN32K_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EN32K` writer - 32kHz Output Enable"] +pub struct EN32K_W<'a> { + w: &'a mut W, +} +impl<'a> EN32K_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `EN1K` reader - 1kHz Output Enable"] +pub struct EN1K_R(crate::FieldReader); +impl EN1K_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EN1K_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EN1K_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EN1K` writer - 1kHz Output Enable"] +pub struct EN1K_W<'a> { + w: &'a mut W, +} +impl<'a> EN1K_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - On Demand Control"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - On Demand Control"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Oscillator Start-Up Time\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum STARTUP_A { + #[doc = "0: 0.092 ms"] + CYCLE3 = 0, + #[doc = "1: 0.122 ms"] + CYCLE4 = 1, + #[doc = "2: 0.183 ms"] + CYCLE6 = 2, + #[doc = "3: 0.305 ms"] + CYCLE10 = 3, + #[doc = "4: 0.549 ms"] + CYCLE18 = 4, + #[doc = "5: 1.038 ms"] + CYCLE34 = 5, + #[doc = "6: 2.014 ms"] + CYCLE66 = 6, + #[doc = "7: 3.967 ms"] + CYCLE130 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: STARTUP_A) -> Self { + variant as _ + } +} +#[doc = "Field `STARTUP` reader - Oscillator Start-Up Time"] +pub struct STARTUP_R(crate::FieldReader); +impl STARTUP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + STARTUP_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STARTUP_A { + match self.bits { + 0 => STARTUP_A::CYCLE3, + 1 => STARTUP_A::CYCLE4, + 2 => STARTUP_A::CYCLE6, + 3 => STARTUP_A::CYCLE10, + 4 => STARTUP_A::CYCLE18, + 5 => STARTUP_A::CYCLE34, + 6 => STARTUP_A::CYCLE66, + 7 => STARTUP_A::CYCLE130, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `CYCLE3`"] + #[inline(always)] + pub fn is_cycle3(&self) -> bool { + **self == STARTUP_A::CYCLE3 + } + #[doc = "Checks if the value of the field is `CYCLE4`"] + #[inline(always)] + pub fn is_cycle4(&self) -> bool { + **self == STARTUP_A::CYCLE4 + } + #[doc = "Checks if the value of the field is `CYCLE6`"] + #[inline(always)] + pub fn is_cycle6(&self) -> bool { + **self == STARTUP_A::CYCLE6 + } + #[doc = "Checks if the value of the field is `CYCLE10`"] + #[inline(always)] + pub fn is_cycle10(&self) -> bool { + **self == STARTUP_A::CYCLE10 + } + #[doc = "Checks if the value of the field is `CYCLE18`"] + #[inline(always)] + pub fn is_cycle18(&self) -> bool { + **self == STARTUP_A::CYCLE18 + } + #[doc = "Checks if the value of the field is `CYCLE34`"] + #[inline(always)] + pub fn is_cycle34(&self) -> bool { + **self == STARTUP_A::CYCLE34 + } + #[doc = "Checks if the value of the field is `CYCLE66`"] + #[inline(always)] + pub fn is_cycle66(&self) -> bool { + **self == STARTUP_A::CYCLE66 + } + #[doc = "Checks if the value of the field is `CYCLE130`"] + #[inline(always)] + pub fn is_cycle130(&self) -> bool { + **self == STARTUP_A::CYCLE130 + } +} +impl core::ops::Deref for STARTUP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STARTUP` writer - Oscillator Start-Up Time"] +pub struct STARTUP_W<'a> { + w: &'a mut W, +} +impl<'a> STARTUP_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: STARTUP_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "0.092 ms"] + #[inline(always)] + pub fn cycle3(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE3) + } + #[doc = "0.122 ms"] + #[inline(always)] + pub fn cycle4(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE4) + } + #[doc = "0.183 ms"] + #[inline(always)] + pub fn cycle6(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE6) + } + #[doc = "0.305 ms"] + #[inline(always)] + pub fn cycle10(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE10) + } + #[doc = "0.549 ms"] + #[inline(always)] + pub fn cycle18(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE18) + } + #[doc = "1.038 ms"] + #[inline(always)] + pub fn cycle34(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE34) + } + #[doc = "2.014 ms"] + #[inline(always)] + pub fn cycle66(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE66) + } + #[doc = "3.967 ms"] + #[inline(always)] + pub fn cycle130(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE130) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +#[doc = "Field `WRTLOCK` reader - Write Lock"] +pub struct WRTLOCK_R(crate::FieldReader); +impl WRTLOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WRTLOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WRTLOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WRTLOCK` writer - Write Lock"] +pub struct WRTLOCK_W<'a> { + w: &'a mut W, +} +impl<'a> WRTLOCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `CALIB` reader - Oscillator Calibration"] +pub struct CALIB_R(crate::FieldReader); +impl CALIB_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CALIB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CALIB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CALIB` writer - Oscillator Calibration"] +pub struct CALIB_W<'a> { + w: &'a mut W, +} +impl<'a> CALIB_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x7f << 16)) | ((value as u32 & 0x7f) << 16); + self.w + } +} +impl R { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - 32kHz Output Enable"] + #[inline(always)] + pub fn en32k(&self) -> EN32K_R { + EN32K_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - 1kHz Output Enable"] + #[inline(always)] + pub fn en1k(&self) -> EN1K_R { + EN1K_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Oscillator Start-Up Time"] + #[inline(always)] + pub fn startup(&self) -> STARTUP_R { + STARTUP_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 12 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&self) -> WRTLOCK_R { + WRTLOCK_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bits 16:22 - Oscillator Calibration"] + #[inline(always)] + pub fn calib(&self) -> CALIB_R { + CALIB_R::new(((self.bits >> 16) & 0x7f) as u8) + } +} +impl W { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - 32kHz Output Enable"] + #[inline(always)] + pub fn en32k(&mut self) -> EN32K_W { + EN32K_W { w: self } + } + #[doc = "Bit 3 - 1kHz Output Enable"] + #[inline(always)] + pub fn en1k(&mut self) -> EN1K_W { + EN1K_W { w: self } + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Bits 8:10 - Oscillator Start-Up Time"] + #[inline(always)] + pub fn startup(&mut self) -> STARTUP_W { + STARTUP_W { w: self } + } + #[doc = "Bit 12 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&mut self) -> WRTLOCK_W { + WRTLOCK_W { w: self } + } + #[doc = "Bits 16:22 - Oscillator Calibration"] + #[inline(always)] + pub fn calib(&mut self) -> CALIB_W { + CALIB_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "32kHz Internal Oscillator (OSC32K) Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [osc32k](index.html) module"] +pub struct OSC32K_SPEC; +impl crate::RegisterSpec for OSC32K_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [osc32k::R](R) reader structure"] +impl crate::Readable for OSC32K_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [osc32k::W](W) writer structure"] +impl crate::Writable for OSC32K_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OSC32K to value 0x003f_0080"] +impl crate::Resettable for OSC32K_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x003f_0080 + } +} diff --git a/pac/atsamc21j/src/osc32kctrl/osculp32k.rs b/pac/atsamc21j/src/osc32kctrl/osculp32k.rs new file mode 100644 index 000000000000..1c351c406e59 --- /dev/null +++ b/pac/atsamc21j/src/osc32kctrl/osculp32k.rs @@ -0,0 +1,150 @@ +#[doc = "Register `OSCULP32K` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OSCULP32K` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CALIB` reader - Oscillator Calibration"] +pub struct CALIB_R(crate::FieldReader); +impl CALIB_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CALIB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CALIB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CALIB` writer - Oscillator Calibration"] +pub struct CALIB_W<'a> { + w: &'a mut W, +} +impl<'a> CALIB_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 8)) | ((value as u32 & 0x1f) << 8); + self.w + } +} +#[doc = "Field `WRTLOCK` reader - Write Lock"] +pub struct WRTLOCK_R(crate::FieldReader); +impl WRTLOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WRTLOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WRTLOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WRTLOCK` writer - Write Lock"] +pub struct WRTLOCK_W<'a> { + w: &'a mut W, +} +impl<'a> WRTLOCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bits 8:12 - Oscillator Calibration"] + #[inline(always)] + pub fn calib(&self) -> CALIB_R { + CALIB_R::new(((self.bits >> 8) & 0x1f) as u8) + } + #[doc = "Bit 15 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&self) -> WRTLOCK_R { + WRTLOCK_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 8:12 - Oscillator Calibration"] + #[inline(always)] + pub fn calib(&mut self) -> CALIB_W { + CALIB_W { w: self } + } + #[doc = "Bit 15 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&mut self) -> WRTLOCK_W { + WRTLOCK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [osculp32k](index.html) module"] +pub struct OSCULP32K_SPEC; +impl crate::RegisterSpec for OSCULP32K_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [osculp32k::R](R) reader structure"] +impl crate::Readable for OSCULP32K_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [osculp32k::W](W) writer structure"] +impl crate::Writable for OSCULP32K_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OSCULP32K to value 0"] +impl crate::Resettable for OSCULP32K_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/osc32kctrl/rtcctrl.rs b/pac/atsamc21j/src/osc32kctrl/rtcctrl.rs new file mode 100644 index 000000000000..1248024a03b9 --- /dev/null +++ b/pac/atsamc21j/src/osc32kctrl/rtcctrl.rs @@ -0,0 +1,204 @@ +#[doc = "Register `RTCCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RTCCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "RTC Clock Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum RTCSEL_A { + #[doc = "0: 1.024kHz from 32kHz internal ULP oscillator"] + ULP1K = 0, + #[doc = "1: 32.768kHz from 32kHz internal ULP oscillator"] + ULP32K = 1, + #[doc = "2: 1.024kHz from 32.768kHz internal oscillator"] + OSC1K = 2, + #[doc = "3: 32.768kHz from 32.768kHz internal oscillator"] + OSC32K = 3, + #[doc = "4: 1.024kHz from 32.768kHz internal oscillator"] + XOSC1K = 4, + #[doc = "5: 32.768kHz from 32.768kHz external crystal oscillator"] + XOSC32K = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RTCSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `RTCSEL` reader - RTC Clock Selection"] +pub struct RTCSEL_R(crate::FieldReader); +impl RTCSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RTCSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(RTCSEL_A::ULP1K), + 1 => Some(RTCSEL_A::ULP32K), + 2 => Some(RTCSEL_A::OSC1K), + 3 => Some(RTCSEL_A::OSC32K), + 4 => Some(RTCSEL_A::XOSC1K), + 5 => Some(RTCSEL_A::XOSC32K), + _ => None, + } + } + #[doc = "Checks if the value of the field is `ULP1K`"] + #[inline(always)] + pub fn is_ulp1k(&self) -> bool { + **self == RTCSEL_A::ULP1K + } + #[doc = "Checks if the value of the field is `ULP32K`"] + #[inline(always)] + pub fn is_ulp32k(&self) -> bool { + **self == RTCSEL_A::ULP32K + } + #[doc = "Checks if the value of the field is `OSC1K`"] + #[inline(always)] + pub fn is_osc1k(&self) -> bool { + **self == RTCSEL_A::OSC1K + } + #[doc = "Checks if the value of the field is `OSC32K`"] + #[inline(always)] + pub fn is_osc32k(&self) -> bool { + **self == RTCSEL_A::OSC32K + } + #[doc = "Checks if the value of the field is `XOSC1K`"] + #[inline(always)] + pub fn is_xosc1k(&self) -> bool { + **self == RTCSEL_A::XOSC1K + } + #[doc = "Checks if the value of the field is `XOSC32K`"] + #[inline(always)] + pub fn is_xosc32k(&self) -> bool { + **self == RTCSEL_A::XOSC32K + } +} +impl core::ops::Deref for RTCSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RTCSEL` writer - RTC Clock Selection"] +pub struct RTCSEL_W<'a> { + w: &'a mut W, +} +impl<'a> RTCSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RTCSEL_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "1.024kHz from 32kHz internal ULP oscillator"] + #[inline(always)] + pub fn ulp1k(self) -> &'a mut W { + self.variant(RTCSEL_A::ULP1K) + } + #[doc = "32.768kHz from 32kHz internal ULP oscillator"] + #[inline(always)] + pub fn ulp32k(self) -> &'a mut W { + self.variant(RTCSEL_A::ULP32K) + } + #[doc = "1.024kHz from 32.768kHz internal oscillator"] + #[inline(always)] + pub fn osc1k(self) -> &'a mut W { + self.variant(RTCSEL_A::OSC1K) + } + #[doc = "32.768kHz from 32.768kHz internal oscillator"] + #[inline(always)] + pub fn osc32k(self) -> &'a mut W { + self.variant(RTCSEL_A::OSC32K) + } + #[doc = "1.024kHz from 32.768kHz internal oscillator"] + #[inline(always)] + pub fn xosc1k(self) -> &'a mut W { + self.variant(RTCSEL_A::XOSC1K) + } + #[doc = "32.768kHz from 32.768kHz external crystal oscillator"] + #[inline(always)] + pub fn xosc32k(self) -> &'a mut W { + self.variant(RTCSEL_A::XOSC32K) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - RTC Clock Selection"] + #[inline(always)] + pub fn rtcsel(&self) -> RTCSEL_R { + RTCSEL_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - RTC Clock Selection"] + #[inline(always)] + pub fn rtcsel(&mut self) -> RTCSEL_W { + RTCSEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Clock selection\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rtcctrl](index.html) module"] +pub struct RTCCTRL_SPEC; +impl crate::RegisterSpec for RTCCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rtcctrl::R](R) reader structure"] +impl crate::Readable for RTCCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rtcctrl::W](W) writer structure"] +impl crate::Writable for RTCCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RTCCTRL to value 0"] +impl crate::Resettable for RTCCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/osc32kctrl/status.rs b/pac/atsamc21j/src/osc32kctrl/status.rs new file mode 100644 index 000000000000..f1f1483ac4e8 --- /dev/null +++ b/pac/atsamc21j/src/osc32kctrl/status.rs @@ -0,0 +1,113 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `XOSC32KRDY` reader - XOSC32K Ready"] +pub struct XOSC32KRDY_R(crate::FieldReader); +impl XOSC32KRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSC32KRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC32KRDY` reader - OSC32K Ready"] +pub struct OSC32KRDY_R(crate::FieldReader); +impl OSC32KRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC32KRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKFAIL` reader - XOSC32K Clock Failure Detector"] +pub struct CLKFAIL_R(crate::FieldReader); +impl CLKFAIL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKFAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKFAIL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKSW` reader - XOSC32K Clock switch"] +pub struct CLKSW_R(crate::FieldReader); +impl CLKSW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKSW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKSW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - XOSC32K Ready"] + #[inline(always)] + pub fn xosc32krdy(&self) -> XOSC32KRDY_R { + XOSC32KRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - OSC32K Ready"] + #[inline(always)] + pub fn osc32krdy(&self) -> OSC32KRDY_R { + OSC32KRDY_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - XOSC32K Clock Failure Detector"] + #[inline(always)] + pub fn clkfail(&self) -> CLKFAIL_R { + CLKFAIL_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - XOSC32K Clock switch"] + #[inline(always)] + pub fn clksw(&self) -> CLKSW_R { + CLKSW_R::new(((self.bits >> 3) & 0x01) != 0) + } +} +#[doc = "Power and Clocks Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/osc32kctrl/xosc32k.rs b/pac/atsamc21j/src/osc32kctrl/xosc32k.rs new file mode 100644 index 000000000000..93e42bba3c0e --- /dev/null +++ b/pac/atsamc21j/src/osc32kctrl/xosc32k.rs @@ -0,0 +1,559 @@ +#[doc = "Register `XOSC32K` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `XOSC32K` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Oscillator Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Oscillator Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `XTALEN` reader - Crystal Oscillator Enable"] +pub struct XTALEN_R(crate::FieldReader); +impl XTALEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XTALEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XTALEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XTALEN` writer - Crystal Oscillator Enable"] +pub struct XTALEN_W<'a> { + w: &'a mut W, +} +impl<'a> XTALEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `EN32K` reader - 32kHz Output Enable"] +pub struct EN32K_R(crate::FieldReader); +impl EN32K_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EN32K_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EN32K_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EN32K` writer - 32kHz Output Enable"] +pub struct EN32K_W<'a> { + w: &'a mut W, +} +impl<'a> EN32K_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `EN1K` reader - 1kHz Output Enable"] +pub struct EN1K_R(crate::FieldReader); +impl EN1K_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EN1K_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EN1K_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EN1K` writer - 1kHz Output Enable"] +pub struct EN1K_W<'a> { + w: &'a mut W, +} +impl<'a> EN1K_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - On Demand Control"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - On Demand Control"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Oscillator Start-Up Time\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum STARTUP_A { + #[doc = "0: 0.122 ms"] + CYCLE1 = 0, + #[doc = "1: 1.068 ms"] + CYCLE32 = 1, + #[doc = "2: 62.6 ms"] + CYCLE2048 = 2, + #[doc = "3: 125 ms"] + CYCLE4096 = 3, + #[doc = "4: 500 ms"] + CYCLE16384 = 4, + #[doc = "5: 1000 ms"] + CYCLE32768 = 5, + #[doc = "6: 2000 ms"] + CYCLE65536 = 6, + #[doc = "7: 4000 ms"] + CYCLE131072 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: STARTUP_A) -> Self { + variant as _ + } +} +#[doc = "Field `STARTUP` reader - Oscillator Start-Up Time"] +pub struct STARTUP_R(crate::FieldReader); +impl STARTUP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + STARTUP_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STARTUP_A { + match self.bits { + 0 => STARTUP_A::CYCLE1, + 1 => STARTUP_A::CYCLE32, + 2 => STARTUP_A::CYCLE2048, + 3 => STARTUP_A::CYCLE4096, + 4 => STARTUP_A::CYCLE16384, + 5 => STARTUP_A::CYCLE32768, + 6 => STARTUP_A::CYCLE65536, + 7 => STARTUP_A::CYCLE131072, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `CYCLE1`"] + #[inline(always)] + pub fn is_cycle1(&self) -> bool { + **self == STARTUP_A::CYCLE1 + } + #[doc = "Checks if the value of the field is `CYCLE32`"] + #[inline(always)] + pub fn is_cycle32(&self) -> bool { + **self == STARTUP_A::CYCLE32 + } + #[doc = "Checks if the value of the field is `CYCLE2048`"] + #[inline(always)] + pub fn is_cycle2048(&self) -> bool { + **self == STARTUP_A::CYCLE2048 + } + #[doc = "Checks if the value of the field is `CYCLE4096`"] + #[inline(always)] + pub fn is_cycle4096(&self) -> bool { + **self == STARTUP_A::CYCLE4096 + } + #[doc = "Checks if the value of the field is `CYCLE16384`"] + #[inline(always)] + pub fn is_cycle16384(&self) -> bool { + **self == STARTUP_A::CYCLE16384 + } + #[doc = "Checks if the value of the field is `CYCLE32768`"] + #[inline(always)] + pub fn is_cycle32768(&self) -> bool { + **self == STARTUP_A::CYCLE32768 + } + #[doc = "Checks if the value of the field is `CYCLE65536`"] + #[inline(always)] + pub fn is_cycle65536(&self) -> bool { + **self == STARTUP_A::CYCLE65536 + } + #[doc = "Checks if the value of the field is `CYCLE131072`"] + #[inline(always)] + pub fn is_cycle131072(&self) -> bool { + **self == STARTUP_A::CYCLE131072 + } +} +impl core::ops::Deref for STARTUP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STARTUP` writer - Oscillator Start-Up Time"] +pub struct STARTUP_W<'a> { + w: &'a mut W, +} +impl<'a> STARTUP_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: STARTUP_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "0.122 ms"] + #[inline(always)] + pub fn cycle1(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE1) + } + #[doc = "1.068 ms"] + #[inline(always)] + pub fn cycle32(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE32) + } + #[doc = "62.6 ms"] + #[inline(always)] + pub fn cycle2048(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE2048) + } + #[doc = "125 ms"] + #[inline(always)] + pub fn cycle4096(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE4096) + } + #[doc = "500 ms"] + #[inline(always)] + pub fn cycle16384(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE16384) + } + #[doc = "1000 ms"] + #[inline(always)] + pub fn cycle32768(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE32768) + } + #[doc = "2000 ms"] + #[inline(always)] + pub fn cycle65536(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE65536) + } + #[doc = "4000 ms"] + #[inline(always)] + pub fn cycle131072(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE131072) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u16 & 0x07) << 8); + self.w + } +} +#[doc = "Field `WRTLOCK` reader - Write Lock"] +pub struct WRTLOCK_R(crate::FieldReader); +impl WRTLOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WRTLOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WRTLOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WRTLOCK` writer - Write Lock"] +pub struct WRTLOCK_W<'a> { + w: &'a mut W, +} +impl<'a> WRTLOCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u16 & 0x01) << 12); + self.w + } +} +impl R { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Crystal Oscillator Enable"] + #[inline(always)] + pub fn xtalen(&self) -> XTALEN_R { + XTALEN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - 32kHz Output Enable"] + #[inline(always)] + pub fn en32k(&self) -> EN32K_R { + EN32K_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - 1kHz Output Enable"] + #[inline(always)] + pub fn en1k(&self) -> EN1K_R { + EN1K_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Oscillator Start-Up Time"] + #[inline(always)] + pub fn startup(&self) -> STARTUP_R { + STARTUP_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 12 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&self) -> WRTLOCK_R { + WRTLOCK_R::new(((self.bits >> 12) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - Crystal Oscillator Enable"] + #[inline(always)] + pub fn xtalen(&mut self) -> XTALEN_W { + XTALEN_W { w: self } + } + #[doc = "Bit 3 - 32kHz Output Enable"] + #[inline(always)] + pub fn en32k(&mut self) -> EN32K_W { + EN32K_W { w: self } + } + #[doc = "Bit 4 - 1kHz Output Enable"] + #[inline(always)] + pub fn en1k(&mut self) -> EN1K_W { + EN1K_W { w: self } + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Bits 8:10 - Oscillator Start-Up Time"] + #[inline(always)] + pub fn startup(&mut self) -> STARTUP_W { + STARTUP_W { w: self } + } + #[doc = "Bit 12 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&mut self) -> WRTLOCK_W { + WRTLOCK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "32kHz External Crystal Oscillator (XOSC32K) Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [xosc32k](index.html) module"] +pub struct XOSC32K_SPEC; +impl crate::RegisterSpec for XOSC32K_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [xosc32k::R](R) reader structure"] +impl crate::Readable for XOSC32K_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [xosc32k::W](W) writer structure"] +impl crate::Writable for XOSC32K_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets XOSC32K to value 0x80"] +impl crate::Resettable for XOSC32K_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x80 + } +} diff --git a/pac/atsamc21j/src/oscctrl.rs b/pac/atsamc21j/src/oscctrl.rs new file mode 100644 index 000000000000..e6dd0929927c --- /dev/null +++ b/pac/atsamc21j/src/oscctrl.rs @@ -0,0 +1,117 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x04 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x08 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x0c - Power and Clocks Status"] + pub status: crate::Reg, + #[doc = "0x10 - External Multipurpose Crystal Oscillator (XOSC) Control"] + pub xoscctrl: crate::Reg, + #[doc = "0x12 - Clock Failure Detector Prescaler"] + pub cfdpresc: crate::Reg, + #[doc = "0x13 - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x14 - 48MHz Internal Oscillator (OSC48M) Control"] + pub osc48mctrl: crate::Reg, + #[doc = "0x15 - OSC48M Divider"] + pub osc48mdiv: crate::Reg, + #[doc = "0x16 - OSC48M Startup Time"] + pub osc48mstup: crate::Reg, + _reserved10: [u8; 0x01], + #[doc = "0x18 - OSC48M Synchronization Busy"] + pub osc48msyncbusy: crate::Reg, + #[doc = "0x1c - DPLL Control"] + pub dpllctrla: crate::Reg, + _reserved12: [u8; 0x03], + #[doc = "0x20 - DPLL Ratio Control"] + pub dpllratio: crate::Reg, + #[doc = "0x24 - Digital Core Configuration"] + pub dpllctrlb: crate::Reg, + #[doc = "0x28 - DPLL Prescaler"] + pub dpllpresc: crate::Reg, + _reserved15: [u8; 0x03], + #[doc = "0x2c - DPLL Synchronization Busy"] + pub dpllsyncbusy: crate::Reg, + _reserved16: [u8; 0x03], + #[doc = "0x30 - DPLL Status"] + pub dpllstatus: crate::Reg, + _reserved17: [u8; 0x07], + #[doc = "0x38 - 48MHz Oscillator Calibration"] + pub cal48m: crate::Reg, +} +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Power and Clocks Status"] +pub mod status; +#[doc = "XOSCCTRL register accessor: an alias for `Reg`"] +pub type XOSCCTRL = crate::Reg; +#[doc = "External Multipurpose Crystal Oscillator (XOSC) Control"] +pub mod xoscctrl; +#[doc = "CFDPRESC register accessor: an alias for `Reg`"] +pub type CFDPRESC = crate::Reg; +#[doc = "Clock Failure Detector Prescaler"] +pub mod cfdpresc; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "OSC48MCTRL register accessor: an alias for `Reg`"] +pub type OSC48MCTRL = crate::Reg; +#[doc = "48MHz Internal Oscillator (OSC48M) Control"] +pub mod osc48mctrl; +#[doc = "OSC48MDIV register accessor: an alias for `Reg`"] +pub type OSC48MDIV = crate::Reg; +#[doc = "OSC48M Divider"] +pub mod osc48mdiv; +#[doc = "OSC48MSTUP register accessor: an alias for `Reg`"] +pub type OSC48MSTUP = crate::Reg; +#[doc = "OSC48M Startup Time"] +pub mod osc48mstup; +#[doc = "OSC48MSYNCBUSY register accessor: an alias for `Reg`"] +pub type OSC48MSYNCBUSY = crate::Reg; +#[doc = "OSC48M Synchronization Busy"] +pub mod osc48msyncbusy; +#[doc = "DPLLCTRLA register accessor: an alias for `Reg`"] +pub type DPLLCTRLA = crate::Reg; +#[doc = "DPLL Control"] +pub mod dpllctrla; +#[doc = "DPLLRATIO register accessor: an alias for `Reg`"] +pub type DPLLRATIO = crate::Reg; +#[doc = "DPLL Ratio Control"] +pub mod dpllratio; +#[doc = "DPLLCTRLB register accessor: an alias for `Reg`"] +pub type DPLLCTRLB = crate::Reg; +#[doc = "Digital Core Configuration"] +pub mod dpllctrlb; +#[doc = "DPLLPRESC register accessor: an alias for `Reg`"] +pub type DPLLPRESC = crate::Reg; +#[doc = "DPLL Prescaler"] +pub mod dpllpresc; +#[doc = "DPLLSYNCBUSY register accessor: an alias for `Reg`"] +pub type DPLLSYNCBUSY = crate::Reg; +#[doc = "DPLL Synchronization Busy"] +pub mod dpllsyncbusy; +#[doc = "DPLLSTATUS register accessor: an alias for `Reg`"] +pub type DPLLSTATUS = crate::Reg; +#[doc = "DPLL Status"] +pub mod dpllstatus; +#[doc = "CAL48M register accessor: an alias for `Reg`"] +pub type CAL48M = crate::Reg; +#[doc = "48MHz Oscillator Calibration"] +pub mod cal48m; diff --git a/pac/atsamc21j/src/oscctrl/cal48m.rs b/pac/atsamc21j/src/oscctrl/cal48m.rs new file mode 100644 index 000000000000..05d5cd2bbc92 --- /dev/null +++ b/pac/atsamc21j/src/oscctrl/cal48m.rs @@ -0,0 +1,177 @@ +#[doc = "Register `CAL48M` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CAL48M` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FCAL` reader - Frequency Calibration (48MHz)"] +pub struct FCAL_R(crate::FieldReader); +impl FCAL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FCAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FCAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FCAL` writer - Frequency Calibration (48MHz)"] +pub struct FCAL_W<'a> { + w: &'a mut W, +} +impl<'a> FCAL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +#[doc = "Field `FRANGE` reader - Frequency Range (48MHz)"] +pub struct FRANGE_R(crate::FieldReader); +impl FRANGE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FRANGE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FRANGE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FRANGE` writer - Frequency Range (48MHz)"] +pub struct FRANGE_W<'a> { + w: &'a mut W, +} +impl<'a> FRANGE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 8)) | ((value as u32 & 0x03) << 8); + self.w + } +} +#[doc = "Field `TCAL` reader - Temperature Calibration (48MHz)"] +pub struct TCAL_R(crate::FieldReader); +impl TCAL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TCAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCAL` writer - Temperature Calibration (48MHz)"] +pub struct TCAL_W<'a> { + w: &'a mut W, +} +impl<'a> TCAL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 16)) | ((value as u32 & 0x3f) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Frequency Calibration (48MHz)"] + #[inline(always)] + pub fn fcal(&self) -> FCAL_R { + FCAL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 8:9 - Frequency Range (48MHz)"] + #[inline(always)] + pub fn frange(&self) -> FRANGE_R { + FRANGE_R::new(((self.bits >> 8) & 0x03) as u8) + } + #[doc = "Bits 16:21 - Temperature Calibration (48MHz)"] + #[inline(always)] + pub fn tcal(&self) -> TCAL_R { + TCAL_R::new(((self.bits >> 16) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - Frequency Calibration (48MHz)"] + #[inline(always)] + pub fn fcal(&mut self) -> FCAL_W { + FCAL_W { w: self } + } + #[doc = "Bits 8:9 - Frequency Range (48MHz)"] + #[inline(always)] + pub fn frange(&mut self) -> FRANGE_W { + FRANGE_W { w: self } + } + #[doc = "Bits 16:21 - Temperature Calibration (48MHz)"] + #[inline(always)] + pub fn tcal(&mut self) -> TCAL_W { + TCAL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "48MHz Oscillator Calibration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cal48m](index.html) module"] +pub struct CAL48M_SPEC; +impl crate::RegisterSpec for CAL48M_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cal48m::R](R) reader structure"] +impl crate::Readable for CAL48M_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cal48m::W](W) writer structure"] +impl crate::Writable for CAL48M_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CAL48M to value 0"] +impl crate::Resettable for CAL48M_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/oscctrl/cfdpresc.rs b/pac/atsamc21j/src/oscctrl/cfdpresc.rs new file mode 100644 index 000000000000..029ae541eec5 --- /dev/null +++ b/pac/atsamc21j/src/oscctrl/cfdpresc.rs @@ -0,0 +1,230 @@ +#[doc = "Register `CFDPRESC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CFDPRESC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Clock Failure Detector Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CFDPRESC_A { + #[doc = "0: 48 MHz"] + DIV1 = 0, + #[doc = "1: 24 MHz"] + DIV2 = 1, + #[doc = "2: 12 MHz"] + DIV4 = 2, + #[doc = "3: 6 MHz"] + DIV8 = 3, + #[doc = "4: 3 MHz"] + DIV16 = 4, + #[doc = "5: 1.5 MHz"] + DIV32 = 5, + #[doc = "6: 0.75 MHz"] + DIV64 = 6, + #[doc = "7: 0.3125 MHz"] + DIV128 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CFDPRESC_A) -> Self { + variant as _ + } +} +#[doc = "Field `CFDPRESC` reader - Clock Failure Detector Prescaler"] +pub struct CFDPRESC_R(crate::FieldReader); +impl CFDPRESC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CFDPRESC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CFDPRESC_A { + match self.bits { + 0 => CFDPRESC_A::DIV1, + 1 => CFDPRESC_A::DIV2, + 2 => CFDPRESC_A::DIV4, + 3 => CFDPRESC_A::DIV8, + 4 => CFDPRESC_A::DIV16, + 5 => CFDPRESC_A::DIV32, + 6 => CFDPRESC_A::DIV64, + 7 => CFDPRESC_A::DIV128, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == CFDPRESC_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == CFDPRESC_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == CFDPRESC_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == CFDPRESC_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == CFDPRESC_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == CFDPRESC_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == CFDPRESC_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == CFDPRESC_A::DIV128 + } +} +impl core::ops::Deref for CFDPRESC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFDPRESC` writer - Clock Failure Detector Prescaler"] +pub struct CFDPRESC_W<'a> { + w: &'a mut W, +} +impl<'a> CFDPRESC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CFDPRESC_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "48 MHz"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(CFDPRESC_A::DIV1) + } + #[doc = "24 MHz"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(CFDPRESC_A::DIV2) + } + #[doc = "12 MHz"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(CFDPRESC_A::DIV4) + } + #[doc = "6 MHz"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(CFDPRESC_A::DIV8) + } + #[doc = "3 MHz"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(CFDPRESC_A::DIV16) + } + #[doc = "1.5 MHz"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(CFDPRESC_A::DIV32) + } + #[doc = "0.75 MHz"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(CFDPRESC_A::DIV64) + } + #[doc = "0.3125 MHz"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(CFDPRESC_A::DIV128) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Clock Failure Detector Prescaler"] + #[inline(always)] + pub fn cfdpresc(&self) -> CFDPRESC_R { + CFDPRESC_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Clock Failure Detector Prescaler"] + #[inline(always)] + pub fn cfdpresc(&mut self) -> CFDPRESC_W { + CFDPRESC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Clock Failure Detector Prescaler\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cfdpresc](index.html) module"] +pub struct CFDPRESC_SPEC; +impl crate::RegisterSpec for CFDPRESC_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [cfdpresc::R](R) reader structure"] +impl crate::Readable for CFDPRESC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cfdpresc::W](W) writer structure"] +impl crate::Writable for CFDPRESC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CFDPRESC to value 0"] +impl crate::Resettable for CFDPRESC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/oscctrl/dpllctrla.rs b/pac/atsamc21j/src/oscctrl/dpllctrla.rs new file mode 100644 index 000000000000..5a60a5087002 --- /dev/null +++ b/pac/atsamc21j/src/oscctrl/dpllctrla.rs @@ -0,0 +1,207 @@ +#[doc = "Register `DPLLCTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DPLLCTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - On Demand"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - On Demand"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - On Demand"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - On Demand"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DPLL Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dpllctrla](index.html) module"] +pub struct DPLLCTRLA_SPEC; +impl crate::RegisterSpec for DPLLCTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dpllctrla::R](R) reader structure"] +impl crate::Readable for DPLLCTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dpllctrla::W](W) writer structure"] +impl crate::Writable for DPLLCTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DPLLCTRLA to value 0x80"] +impl crate::Resettable for DPLLCTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x80 + } +} diff --git a/pac/atsamc21j/src/oscctrl/dpllctrlb.rs b/pac/atsamc21j/src/oscctrl/dpllctrlb.rs new file mode 100644 index 000000000000..8400b0572dd0 --- /dev/null +++ b/pac/atsamc21j/src/oscctrl/dpllctrlb.rs @@ -0,0 +1,580 @@ +#[doc = "Register `DPLLCTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DPLLCTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Proportional Integral Filter Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FILTER_A { + #[doc = "0: Default filter mode"] + DEFAULT = 0, + #[doc = "1: Low bandwidth filter"] + LBFILT = 1, + #[doc = "2: High bandwidth filter"] + HBFILT = 2, + #[doc = "3: High damping filter"] + HDFILT = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FILTER_A) -> Self { + variant as _ + } +} +#[doc = "Field `FILTER` reader - Proportional Integral Filter Selection"] +pub struct FILTER_R(crate::FieldReader); +impl FILTER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FILTER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FILTER_A { + match self.bits { + 0 => FILTER_A::DEFAULT, + 1 => FILTER_A::LBFILT, + 2 => FILTER_A::HBFILT, + 3 => FILTER_A::HDFILT, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DEFAULT`"] + #[inline(always)] + pub fn is_default(&self) -> bool { + **self == FILTER_A::DEFAULT + } + #[doc = "Checks if the value of the field is `LBFILT`"] + #[inline(always)] + pub fn is_lbfilt(&self) -> bool { + **self == FILTER_A::LBFILT + } + #[doc = "Checks if the value of the field is `HBFILT`"] + #[inline(always)] + pub fn is_hbfilt(&self) -> bool { + **self == FILTER_A::HBFILT + } + #[doc = "Checks if the value of the field is `HDFILT`"] + #[inline(always)] + pub fn is_hdfilt(&self) -> bool { + **self == FILTER_A::HDFILT + } +} +impl core::ops::Deref for FILTER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTER` writer - Proportional Integral Filter Selection"] +pub struct FILTER_W<'a> { + w: &'a mut W, +} +impl<'a> FILTER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FILTER_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Default filter mode"] + #[inline(always)] + pub fn default(self) -> &'a mut W { + self.variant(FILTER_A::DEFAULT) + } + #[doc = "Low bandwidth filter"] + #[inline(always)] + pub fn lbfilt(self) -> &'a mut W { + self.variant(FILTER_A::LBFILT) + } + #[doc = "High bandwidth filter"] + #[inline(always)] + pub fn hbfilt(self) -> &'a mut W { + self.variant(FILTER_A::HBFILT) + } + #[doc = "High damping filter"] + #[inline(always)] + pub fn hdfilt(self) -> &'a mut W { + self.variant(FILTER_A::HDFILT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u32 & 0x03); + self.w + } +} +#[doc = "Field `LPEN` reader - Low-Power Enable"] +pub struct LPEN_R(crate::FieldReader); +impl LPEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LPEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LPEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LPEN` writer - Low-Power Enable"] +pub struct LPEN_W<'a> { + w: &'a mut W, +} +impl<'a> LPEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `WUF` reader - Wake Up Fast"] +pub struct WUF_R(crate::FieldReader); +impl WUF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WUF` writer - Wake Up Fast"] +pub struct WUF_W<'a> { + w: &'a mut W, +} +impl<'a> WUF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Reference Clock Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum REFCLK_A { + #[doc = "0: XOSC32K clock reference"] + XOSC32K = 0, + #[doc = "1: XOSC clock reference"] + XOSC = 1, + #[doc = "2: GCLK clock reference"] + GCLK = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: REFCLK_A) -> Self { + variant as _ + } +} +#[doc = "Field `REFCLK` reader - Reference Clock Selection"] +pub struct REFCLK_R(crate::FieldReader); +impl REFCLK_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REFCLK_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(REFCLK_A::XOSC32K), + 1 => Some(REFCLK_A::XOSC), + 2 => Some(REFCLK_A::GCLK), + _ => None, + } + } + #[doc = "Checks if the value of the field is `XOSC32K`"] + #[inline(always)] + pub fn is_xosc32k(&self) -> bool { + **self == REFCLK_A::XOSC32K + } + #[doc = "Checks if the value of the field is `XOSC`"] + #[inline(always)] + pub fn is_xosc(&self) -> bool { + **self == REFCLK_A::XOSC + } + #[doc = "Checks if the value of the field is `GCLK`"] + #[inline(always)] + pub fn is_gclk(&self) -> bool { + **self == REFCLK_A::GCLK + } +} +impl core::ops::Deref for REFCLK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REFCLK` writer - Reference Clock Selection"] +pub struct REFCLK_W<'a> { + w: &'a mut W, +} +impl<'a> REFCLK_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: REFCLK_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "XOSC32K clock reference"] + #[inline(always)] + pub fn xosc32k(self) -> &'a mut W { + self.variant(REFCLK_A::XOSC32K) + } + #[doc = "XOSC clock reference"] + #[inline(always)] + pub fn xosc(self) -> &'a mut W { + self.variant(REFCLK_A::XOSC) + } + #[doc = "GCLK clock reference"] + #[inline(always)] + pub fn gclk(self) -> &'a mut W { + self.variant(REFCLK_A::GCLK) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u32 & 0x03) << 4); + self.w + } +} +#[doc = "Lock Time\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum LTIME_A { + #[doc = "0: No time-out. Automatic lock."] + DEFAULT = 0, + #[doc = "4: Time-out if no lock within 8ms"] + _8MS = 4, + #[doc = "5: Time-out if no lock within 9ms"] + _9MS = 5, + #[doc = "6: Time-out if no lock within 10ms"] + _10MS = 6, + #[doc = "7: Time-out if no lock within 11ms"] + _11MS = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LTIME_A) -> Self { + variant as _ + } +} +#[doc = "Field `LTIME` reader - Lock Time"] +pub struct LTIME_R(crate::FieldReader); +impl LTIME_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LTIME_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(LTIME_A::DEFAULT), + 4 => Some(LTIME_A::_8MS), + 5 => Some(LTIME_A::_9MS), + 6 => Some(LTIME_A::_10MS), + 7 => Some(LTIME_A::_11MS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DEFAULT`"] + #[inline(always)] + pub fn is_default(&self) -> bool { + **self == LTIME_A::DEFAULT + } + #[doc = "Checks if the value of the field is `_8MS`"] + #[inline(always)] + pub fn is_8ms(&self) -> bool { + **self == LTIME_A::_8MS + } + #[doc = "Checks if the value of the field is `_9MS`"] + #[inline(always)] + pub fn is_9ms(&self) -> bool { + **self == LTIME_A::_9MS + } + #[doc = "Checks if the value of the field is `_10MS`"] + #[inline(always)] + pub fn is_10ms(&self) -> bool { + **self == LTIME_A::_10MS + } + #[doc = "Checks if the value of the field is `_11MS`"] + #[inline(always)] + pub fn is_11ms(&self) -> bool { + **self == LTIME_A::_11MS + } +} +impl core::ops::Deref for LTIME_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LTIME` writer - Lock Time"] +pub struct LTIME_W<'a> { + w: &'a mut W, +} +impl<'a> LTIME_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: LTIME_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No time-out. Automatic lock."] + #[inline(always)] + pub fn default(self) -> &'a mut W { + self.variant(LTIME_A::DEFAULT) + } + #[doc = "Time-out if no lock within 8ms"] + #[inline(always)] + pub fn _8ms(self) -> &'a mut W { + self.variant(LTIME_A::_8MS) + } + #[doc = "Time-out if no lock within 9ms"] + #[inline(always)] + pub fn _9ms(self) -> &'a mut W { + self.variant(LTIME_A::_9MS) + } + #[doc = "Time-out if no lock within 10ms"] + #[inline(always)] + pub fn _10ms(self) -> &'a mut W { + self.variant(LTIME_A::_10MS) + } + #[doc = "Time-out if no lock within 11ms"] + #[inline(always)] + pub fn _11ms(self) -> &'a mut W { + self.variant(LTIME_A::_11MS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +#[doc = "Field `LBYPASS` reader - Lock Bypass"] +pub struct LBYPASS_R(crate::FieldReader); +impl LBYPASS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LBYPASS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LBYPASS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LBYPASS` writer - Lock Bypass"] +pub struct LBYPASS_W<'a> { + w: &'a mut W, +} +impl<'a> LBYPASS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `DIV` reader - Clock Divider"] +pub struct DIV_R(crate::FieldReader); +impl DIV_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + DIV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIV` writer - Clock Divider"] +pub struct DIV_W<'a> { + w: &'a mut W, +} +impl<'a> DIV_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07ff << 16)) | ((value as u32 & 0x07ff) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Proportional Integral Filter Selection"] + #[inline(always)] + pub fn filter(&self) -> FILTER_R { + FILTER_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bit 2 - Low-Power Enable"] + #[inline(always)] + pub fn lpen(&self) -> LPEN_R { + LPEN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Wake Up Fast"] + #[inline(always)] + pub fn wuf(&self) -> WUF_R { + WUF_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bits 4:5 - Reference Clock Selection"] + #[inline(always)] + pub fn refclk(&self) -> REFCLK_R { + REFCLK_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bits 8:10 - Lock Time"] + #[inline(always)] + pub fn ltime(&self) -> LTIME_R { + LTIME_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 12 - Lock Bypass"] + #[inline(always)] + pub fn lbypass(&self) -> LBYPASS_R { + LBYPASS_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bits 16:26 - Clock Divider"] + #[inline(always)] + pub fn div(&self) -> DIV_R { + DIV_R::new(((self.bits >> 16) & 0x07ff) as u16) + } +} +impl W { + #[doc = "Bits 0:1 - Proportional Integral Filter Selection"] + #[inline(always)] + pub fn filter(&mut self) -> FILTER_W { + FILTER_W { w: self } + } + #[doc = "Bit 2 - Low-Power Enable"] + #[inline(always)] + pub fn lpen(&mut self) -> LPEN_W { + LPEN_W { w: self } + } + #[doc = "Bit 3 - Wake Up Fast"] + #[inline(always)] + pub fn wuf(&mut self) -> WUF_W { + WUF_W { w: self } + } + #[doc = "Bits 4:5 - Reference Clock Selection"] + #[inline(always)] + pub fn refclk(&mut self) -> REFCLK_W { + REFCLK_W { w: self } + } + #[doc = "Bits 8:10 - Lock Time"] + #[inline(always)] + pub fn ltime(&mut self) -> LTIME_W { + LTIME_W { w: self } + } + #[doc = "Bit 12 - Lock Bypass"] + #[inline(always)] + pub fn lbypass(&mut self) -> LBYPASS_W { + LBYPASS_W { w: self } + } + #[doc = "Bits 16:26 - Clock Divider"] + #[inline(always)] + pub fn div(&mut self) -> DIV_W { + DIV_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Digital Core Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dpllctrlb](index.html) module"] +pub struct DPLLCTRLB_SPEC; +impl crate::RegisterSpec for DPLLCTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dpllctrlb::R](R) reader structure"] +impl crate::Readable for DPLLCTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dpllctrlb::W](W) writer structure"] +impl crate::Writable for DPLLCTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DPLLCTRLB to value 0"] +impl crate::Resettable for DPLLCTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/oscctrl/dpllpresc.rs b/pac/atsamc21j/src/oscctrl/dpllpresc.rs new file mode 100644 index 000000000000..9de662161f99 --- /dev/null +++ b/pac/atsamc21j/src/oscctrl/dpllpresc.rs @@ -0,0 +1,165 @@ +#[doc = "Register `DPLLPRESC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DPLLPRESC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Output Clock Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESC_A { + #[doc = "0: DPLL output is divided by 1"] + DIV1 = 0, + #[doc = "1: DPLL output is divided by 2"] + DIV2 = 1, + #[doc = "2: DPLL output is divided by 4"] + DIV4 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESC_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESC` reader - Output Clock Prescaler"] +pub struct PRESC_R(crate::FieldReader); +impl PRESC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESC_A::DIV1), + 1 => Some(PRESC_A::DIV2), + 2 => Some(PRESC_A::DIV4), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == PRESC_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESC_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESC_A::DIV4 + } +} +impl core::ops::Deref for PRESC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESC` writer - Output Clock Prescaler"] +pub struct PRESC_W<'a> { + w: &'a mut W, +} +impl<'a> PRESC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESC_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "DPLL output is divided by 1"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESC_A::DIV1) + } + #[doc = "DPLL output is divided by 2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESC_A::DIV2) + } + #[doc = "DPLL output is divided by 4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESC_A::DIV4) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u8 & 0x03); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Output Clock Prescaler"] + #[inline(always)] + pub fn presc(&self) -> PRESC_R { + PRESC_R::new((self.bits & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Output Clock Prescaler"] + #[inline(always)] + pub fn presc(&mut self) -> PRESC_W { + PRESC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DPLL Prescaler\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dpllpresc](index.html) module"] +pub struct DPLLPRESC_SPEC; +impl crate::RegisterSpec for DPLLPRESC_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dpllpresc::R](R) reader structure"] +impl crate::Readable for DPLLPRESC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dpllpresc::W](W) writer structure"] +impl crate::Writable for DPLLPRESC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DPLLPRESC to value 0"] +impl crate::Resettable for DPLLPRESC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/oscctrl/dpllratio.rs b/pac/atsamc21j/src/oscctrl/dpllratio.rs new file mode 100644 index 000000000000..93b39e30f1a5 --- /dev/null +++ b/pac/atsamc21j/src/oscctrl/dpllratio.rs @@ -0,0 +1,140 @@ +#[doc = "Register `DPLLRATIO` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DPLLRATIO` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `LDR` reader - Loop Divider Ratio"] +pub struct LDR_R(crate::FieldReader); +impl LDR_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + LDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LDR` writer - Loop Divider Ratio"] +pub struct LDR_W<'a> { + w: &'a mut W, +} +impl<'a> LDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0fff) | (value as u32 & 0x0fff); + self.w + } +} +#[doc = "Field `LDRFRAC` reader - Loop Divider Ratio Fractional Part"] +pub struct LDRFRAC_R(crate::FieldReader); +impl LDRFRAC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LDRFRAC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LDRFRAC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LDRFRAC` writer - Loop Divider Ratio Fractional Part"] +pub struct LDRFRAC_W<'a> { + w: &'a mut W, +} +impl<'a> LDRFRAC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 16)) | ((value as u32 & 0x0f) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:11 - Loop Divider Ratio"] + #[inline(always)] + pub fn ldr(&self) -> LDR_R { + LDR_R::new((self.bits & 0x0fff) as u16) + } + #[doc = "Bits 16:19 - Loop Divider Ratio Fractional Part"] + #[inline(always)] + pub fn ldrfrac(&self) -> LDRFRAC_R { + LDRFRAC_R::new(((self.bits >> 16) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:11 - Loop Divider Ratio"] + #[inline(always)] + pub fn ldr(&mut self) -> LDR_W { + LDR_W { w: self } + } + #[doc = "Bits 16:19 - Loop Divider Ratio Fractional Part"] + #[inline(always)] + pub fn ldrfrac(&mut self) -> LDRFRAC_W { + LDRFRAC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DPLL Ratio Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dpllratio](index.html) module"] +pub struct DPLLRATIO_SPEC; +impl crate::RegisterSpec for DPLLRATIO_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dpllratio::R](R) reader structure"] +impl crate::Readable for DPLLRATIO_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dpllratio::W](W) writer structure"] +impl crate::Writable for DPLLRATIO_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DPLLRATIO to value 0"] +impl crate::Resettable for DPLLRATIO_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/oscctrl/dpllstatus.rs b/pac/atsamc21j/src/oscctrl/dpllstatus.rs new file mode 100644 index 000000000000..931900212816 --- /dev/null +++ b/pac/atsamc21j/src/oscctrl/dpllstatus.rs @@ -0,0 +1,73 @@ +#[doc = "Register `DPLLSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `LOCK` reader - DPLL Lock Status"] +pub struct LOCK_R(crate::FieldReader); +impl LOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKRDY` reader - DPLL Clock Ready"] +pub struct CLKRDY_R(crate::FieldReader); +impl CLKRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - DPLL Lock Status"] + #[inline(always)] + pub fn lock(&self) -> LOCK_R { + LOCK_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - DPLL Clock Ready"] + #[inline(always)] + pub fn clkrdy(&self) -> CLKRDY_R { + CLKRDY_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +#[doc = "DPLL Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dpllstatus](index.html) module"] +pub struct DPLLSTATUS_SPEC; +impl crate::RegisterSpec for DPLLSTATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dpllstatus::R](R) reader structure"] +impl crate::Readable for DPLLSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DPLLSTATUS to value 0"] +impl crate::Resettable for DPLLSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/oscctrl/dpllsyncbusy.rs b/pac/atsamc21j/src/oscctrl/dpllsyncbusy.rs new file mode 100644 index 000000000000..f9fb880a5a59 --- /dev/null +++ b/pac/atsamc21j/src/oscctrl/dpllsyncbusy.rs @@ -0,0 +1,93 @@ +#[doc = "Register `DPLLSYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `ENABLE` reader - DPLL Enable Synchronization Status"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLRATIO` reader - DPLL Ratio Synchronization Status"] +pub struct DPLLRATIO_R(crate::FieldReader); +impl DPLLRATIO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLRATIO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLRATIO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLPRESC` reader - DPLL Prescaler Synchronization Status"] +pub struct DPLLPRESC_R(crate::FieldReader); +impl DPLLPRESC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLPRESC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLPRESC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 1 - DPLL Enable Synchronization Status"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - DPLL Ratio Synchronization Status"] + #[inline(always)] + pub fn dpllratio(&self) -> DPLLRATIO_R { + DPLLRATIO_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - DPLL Prescaler Synchronization Status"] + #[inline(always)] + pub fn dpllpresc(&self) -> DPLLPRESC_R { + DPLLPRESC_R::new(((self.bits >> 3) & 0x01) != 0) + } +} +#[doc = "DPLL Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dpllsyncbusy](index.html) module"] +pub struct DPLLSYNCBUSY_SPEC; +impl crate::RegisterSpec for DPLLSYNCBUSY_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dpllsyncbusy::R](R) reader structure"] +impl crate::Readable for DPLLSYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DPLLSYNCBUSY to value 0"] +impl crate::Resettable for DPLLSYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/oscctrl/evctrl.rs b/pac/atsamc21j/src/oscctrl/evctrl.rs new file mode 100644 index 000000000000..e22ba62f0fe2 --- /dev/null +++ b/pac/atsamc21j/src/oscctrl/evctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CFDEO` reader - Clock Failure Detector Event Output Enable"] +pub struct CFDEO_R(crate::FieldReader); +impl CFDEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFDEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFDEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFDEO` writer - Clock Failure Detector Event Output Enable"] +pub struct CFDEO_W<'a> { + w: &'a mut W, +} +impl<'a> CFDEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Clock Failure Detector Event Output Enable"] + #[inline(always)] + pub fn cfdeo(&self) -> CFDEO_R { + CFDEO_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Clock Failure Detector Event Output Enable"] + #[inline(always)] + pub fn cfdeo(&mut self) -> CFDEO_W { + CFDEO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/oscctrl/intenclr.rs b/pac/atsamc21j/src/oscctrl/intenclr.rs new file mode 100644 index 000000000000..0ea0034a0c02 --- /dev/null +++ b/pac/atsamc21j/src/oscctrl/intenclr.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XOSCRDY` reader - XOSC Ready Interrupt Enable"] +pub struct XOSCRDY_R(crate::FieldReader); +impl XOSCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSCRDY` writer - XOSC Ready Interrupt Enable"] +pub struct XOSCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> XOSCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `XOSCFAIL` reader - XOSC Clock Failure Detector Interrupt Enable"] +pub struct XOSCFAIL_R(crate::FieldReader); +impl XOSCFAIL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSCFAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCFAIL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSCFAIL` writer - XOSC Clock Failure Detector Interrupt Enable"] +pub struct XOSCFAIL_W<'a> { + w: &'a mut W, +} +impl<'a> XOSCFAIL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `OSC48MRDY` reader - OSC48M Ready Interrupt Enable"] +pub struct OSC48MRDY_R(crate::FieldReader); +impl OSC48MRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC48MRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC48MRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC48MRDY` writer - OSC48M Ready Interrupt Enable"] +pub struct OSC48MRDY_W<'a> { + w: &'a mut W, +} +impl<'a> OSC48MRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `DPLLLCKR` reader - DPLL Lock Rise Interrupt Enable"] +pub struct DPLLLCKR_R(crate::FieldReader); +impl DPLLLCKR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKR` writer - DPLL Lock Rise Interrupt Enable"] +pub struct DPLLLCKR_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLCKR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `DPLLLCKF` reader - DPLL Lock Fall Interrupt Enable"] +pub struct DPLLLCKF_R(crate::FieldReader); +impl DPLLLCKF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKF` writer - DPLL Lock Fall Interrupt Enable"] +pub struct DPLLLCKF_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLCKF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `DPLLLTO` reader - DPLL Time Out Interrupt Enable"] +pub struct DPLLLTO_R(crate::FieldReader); +impl DPLLLTO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLTO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLTO` writer - DPLL Time Out Interrupt Enable"] +pub struct DPLLLTO_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLTO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `DPLLLDRTO` reader - DPLL Ratio Ready Interrupt Enable"] +pub struct DPLLLDRTO_R(crate::FieldReader); +impl DPLLLDRTO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLDRTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLDRTO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLDRTO` writer - DPLL Ratio Ready Interrupt Enable"] +pub struct DPLLLDRTO_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLDRTO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +impl R { + #[doc = "Bit 0 - XOSC Ready Interrupt Enable"] + #[inline(always)] + pub fn xoscrdy(&self) -> XOSCRDY_R { + XOSCRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - XOSC Clock Failure Detector Interrupt Enable"] + #[inline(always)] + pub fn xoscfail(&self) -> XOSCFAIL_R { + XOSCFAIL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - OSC48M Ready Interrupt Enable"] + #[inline(always)] + pub fn osc48mrdy(&self) -> OSC48MRDY_R { + OSC48MRDY_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 8 - DPLL Lock Rise Interrupt Enable"] + #[inline(always)] + pub fn dplllckr(&self) -> DPLLLCKR_R { + DPLLLCKR_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - DPLL Lock Fall Interrupt Enable"] + #[inline(always)] + pub fn dplllckf(&self) -> DPLLLCKF_R { + DPLLLCKF_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - DPLL Time Out Interrupt Enable"] + #[inline(always)] + pub fn dplllto(&self) -> DPLLLTO_R { + DPLLLTO_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - DPLL Ratio Ready Interrupt Enable"] + #[inline(always)] + pub fn dpllldrto(&self) -> DPLLLDRTO_R { + DPLLLDRTO_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - XOSC Ready Interrupt Enable"] + #[inline(always)] + pub fn xoscrdy(&mut self) -> XOSCRDY_W { + XOSCRDY_W { w: self } + } + #[doc = "Bit 1 - XOSC Clock Failure Detector Interrupt Enable"] + #[inline(always)] + pub fn xoscfail(&mut self) -> XOSCFAIL_W { + XOSCFAIL_W { w: self } + } + #[doc = "Bit 4 - OSC48M Ready Interrupt Enable"] + #[inline(always)] + pub fn osc48mrdy(&mut self) -> OSC48MRDY_W { + OSC48MRDY_W { w: self } + } + #[doc = "Bit 8 - DPLL Lock Rise Interrupt Enable"] + #[inline(always)] + pub fn dplllckr(&mut self) -> DPLLLCKR_W { + DPLLLCKR_W { w: self } + } + #[doc = "Bit 9 - DPLL Lock Fall Interrupt Enable"] + #[inline(always)] + pub fn dplllckf(&mut self) -> DPLLLCKF_W { + DPLLLCKF_W { w: self } + } + #[doc = "Bit 10 - DPLL Time Out Interrupt Enable"] + #[inline(always)] + pub fn dplllto(&mut self) -> DPLLLTO_W { + DPLLLTO_W { w: self } + } + #[doc = "Bit 11 - DPLL Ratio Ready Interrupt Enable"] + #[inline(always)] + pub fn dpllldrto(&mut self) -> DPLLLDRTO_W { + DPLLLDRTO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/oscctrl/intenset.rs b/pac/atsamc21j/src/oscctrl/intenset.rs new file mode 100644 index 000000000000..2890541e4414 --- /dev/null +++ b/pac/atsamc21j/src/oscctrl/intenset.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XOSCRDY` reader - XOSC Ready Interrupt Enable"] +pub struct XOSCRDY_R(crate::FieldReader); +impl XOSCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSCRDY` writer - XOSC Ready Interrupt Enable"] +pub struct XOSCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> XOSCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `XOSCFAIL` reader - XOSC Clock Failure Detector Interrupt Enable"] +pub struct XOSCFAIL_R(crate::FieldReader); +impl XOSCFAIL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSCFAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCFAIL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSCFAIL` writer - XOSC Clock Failure Detector Interrupt Enable"] +pub struct XOSCFAIL_W<'a> { + w: &'a mut W, +} +impl<'a> XOSCFAIL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `OSC48MRDY` reader - OSC48M Ready Interrupt Enable"] +pub struct OSC48MRDY_R(crate::FieldReader); +impl OSC48MRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC48MRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC48MRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC48MRDY` writer - OSC48M Ready Interrupt Enable"] +pub struct OSC48MRDY_W<'a> { + w: &'a mut W, +} +impl<'a> OSC48MRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `DPLLLCKR` reader - DPLL Lock Rise Interrupt Enable"] +pub struct DPLLLCKR_R(crate::FieldReader); +impl DPLLLCKR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKR` writer - DPLL Lock Rise Interrupt Enable"] +pub struct DPLLLCKR_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLCKR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `DPLLLCKF` reader - DPLL Lock Fall Interrupt Enable"] +pub struct DPLLLCKF_R(crate::FieldReader); +impl DPLLLCKF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKF` writer - DPLL Lock Fall Interrupt Enable"] +pub struct DPLLLCKF_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLCKF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `DPLLLTO` reader - DPLL Time Out Interrupt Enable"] +pub struct DPLLLTO_R(crate::FieldReader); +impl DPLLLTO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLTO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLTO` writer - DPLL Time Out Interrupt Enable"] +pub struct DPLLLTO_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLTO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `DPLLLDRTO` reader - DPLL Ratio Ready Interrupt Enable"] +pub struct DPLLLDRTO_R(crate::FieldReader); +impl DPLLLDRTO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLDRTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLDRTO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLDRTO` writer - DPLL Ratio Ready Interrupt Enable"] +pub struct DPLLLDRTO_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLDRTO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +impl R { + #[doc = "Bit 0 - XOSC Ready Interrupt Enable"] + #[inline(always)] + pub fn xoscrdy(&self) -> XOSCRDY_R { + XOSCRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - XOSC Clock Failure Detector Interrupt Enable"] + #[inline(always)] + pub fn xoscfail(&self) -> XOSCFAIL_R { + XOSCFAIL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - OSC48M Ready Interrupt Enable"] + #[inline(always)] + pub fn osc48mrdy(&self) -> OSC48MRDY_R { + OSC48MRDY_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 8 - DPLL Lock Rise Interrupt Enable"] + #[inline(always)] + pub fn dplllckr(&self) -> DPLLLCKR_R { + DPLLLCKR_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - DPLL Lock Fall Interrupt Enable"] + #[inline(always)] + pub fn dplllckf(&self) -> DPLLLCKF_R { + DPLLLCKF_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - DPLL Time Out Interrupt Enable"] + #[inline(always)] + pub fn dplllto(&self) -> DPLLLTO_R { + DPLLLTO_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - DPLL Ratio Ready Interrupt Enable"] + #[inline(always)] + pub fn dpllldrto(&self) -> DPLLLDRTO_R { + DPLLLDRTO_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - XOSC Ready Interrupt Enable"] + #[inline(always)] + pub fn xoscrdy(&mut self) -> XOSCRDY_W { + XOSCRDY_W { w: self } + } + #[doc = "Bit 1 - XOSC Clock Failure Detector Interrupt Enable"] + #[inline(always)] + pub fn xoscfail(&mut self) -> XOSCFAIL_W { + XOSCFAIL_W { w: self } + } + #[doc = "Bit 4 - OSC48M Ready Interrupt Enable"] + #[inline(always)] + pub fn osc48mrdy(&mut self) -> OSC48MRDY_W { + OSC48MRDY_W { w: self } + } + #[doc = "Bit 8 - DPLL Lock Rise Interrupt Enable"] + #[inline(always)] + pub fn dplllckr(&mut self) -> DPLLLCKR_W { + DPLLLCKR_W { w: self } + } + #[doc = "Bit 9 - DPLL Lock Fall Interrupt Enable"] + #[inline(always)] + pub fn dplllckf(&mut self) -> DPLLLCKF_W { + DPLLLCKF_W { w: self } + } + #[doc = "Bit 10 - DPLL Time Out Interrupt Enable"] + #[inline(always)] + pub fn dplllto(&mut self) -> DPLLLTO_W { + DPLLLTO_W { w: self } + } + #[doc = "Bit 11 - DPLL Ratio Ready Interrupt Enable"] + #[inline(always)] + pub fn dpllldrto(&mut self) -> DPLLLDRTO_W { + DPLLLDRTO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/oscctrl/intflag.rs b/pac/atsamc21j/src/oscctrl/intflag.rs new file mode 100644 index 000000000000..71e452a1b571 --- /dev/null +++ b/pac/atsamc21j/src/oscctrl/intflag.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XOSCRDY` reader - XOSC Ready"] +pub struct XOSCRDY_R(crate::FieldReader); +impl XOSCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSCRDY` writer - XOSC Ready"] +pub struct XOSCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> XOSCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `XOSCFAIL` reader - XOSC Clock Failure Detector"] +pub struct XOSCFAIL_R(crate::FieldReader); +impl XOSCFAIL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSCFAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCFAIL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSCFAIL` writer - XOSC Clock Failure Detector"] +pub struct XOSCFAIL_W<'a> { + w: &'a mut W, +} +impl<'a> XOSCFAIL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `OSC48MRDY` reader - OSC48M Ready"] +pub struct OSC48MRDY_R(crate::FieldReader); +impl OSC48MRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC48MRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC48MRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC48MRDY` writer - OSC48M Ready"] +pub struct OSC48MRDY_W<'a> { + w: &'a mut W, +} +impl<'a> OSC48MRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `DPLLLCKR` reader - DPLL Lock Rise"] +pub struct DPLLLCKR_R(crate::FieldReader); +impl DPLLLCKR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKR` writer - DPLL Lock Rise"] +pub struct DPLLLCKR_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLCKR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `DPLLLCKF` reader - DPLL Lock Fall"] +pub struct DPLLLCKF_R(crate::FieldReader); +impl DPLLLCKF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKF` writer - DPLL Lock Fall"] +pub struct DPLLLCKF_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLCKF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `DPLLLTO` reader - DPLL Timeout"] +pub struct DPLLLTO_R(crate::FieldReader); +impl DPLLLTO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLTO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLTO` writer - DPLL Timeout"] +pub struct DPLLLTO_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLTO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `DPLLLDRTO` reader - DPLL Ratio Ready"] +pub struct DPLLLDRTO_R(crate::FieldReader); +impl DPLLLDRTO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLDRTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLDRTO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLDRTO` writer - DPLL Ratio Ready"] +pub struct DPLLLDRTO_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLDRTO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +impl R { + #[doc = "Bit 0 - XOSC Ready"] + #[inline(always)] + pub fn xoscrdy(&self) -> XOSCRDY_R { + XOSCRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - XOSC Clock Failure Detector"] + #[inline(always)] + pub fn xoscfail(&self) -> XOSCFAIL_R { + XOSCFAIL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - OSC48M Ready"] + #[inline(always)] + pub fn osc48mrdy(&self) -> OSC48MRDY_R { + OSC48MRDY_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 8 - DPLL Lock Rise"] + #[inline(always)] + pub fn dplllckr(&self) -> DPLLLCKR_R { + DPLLLCKR_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - DPLL Lock Fall"] + #[inline(always)] + pub fn dplllckf(&self) -> DPLLLCKF_R { + DPLLLCKF_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - DPLL Timeout"] + #[inline(always)] + pub fn dplllto(&self) -> DPLLLTO_R { + DPLLLTO_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - DPLL Ratio Ready"] + #[inline(always)] + pub fn dpllldrto(&self) -> DPLLLDRTO_R { + DPLLLDRTO_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - XOSC Ready"] + #[inline(always)] + pub fn xoscrdy(&mut self) -> XOSCRDY_W { + XOSCRDY_W { w: self } + } + #[doc = "Bit 1 - XOSC Clock Failure Detector"] + #[inline(always)] + pub fn xoscfail(&mut self) -> XOSCFAIL_W { + XOSCFAIL_W { w: self } + } + #[doc = "Bit 4 - OSC48M Ready"] + #[inline(always)] + pub fn osc48mrdy(&mut self) -> OSC48MRDY_W { + OSC48MRDY_W { w: self } + } + #[doc = "Bit 8 - DPLL Lock Rise"] + #[inline(always)] + pub fn dplllckr(&mut self) -> DPLLLCKR_W { + DPLLLCKR_W { w: self } + } + #[doc = "Bit 9 - DPLL Lock Fall"] + #[inline(always)] + pub fn dplllckf(&mut self) -> DPLLLCKF_W { + DPLLLCKF_W { w: self } + } + #[doc = "Bit 10 - DPLL Timeout"] + #[inline(always)] + pub fn dplllto(&mut self) -> DPLLLTO_W { + DPLLLTO_W { w: self } + } + #[doc = "Bit 11 - DPLL Ratio Ready"] + #[inline(always)] + pub fn dpllldrto(&mut self) -> DPLLLDRTO_W { + DPLLLDRTO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/oscctrl/osc48mctrl.rs b/pac/atsamc21j/src/oscctrl/osc48mctrl.rs new file mode 100644 index 000000000000..8314e21e5775 --- /dev/null +++ b/pac/atsamc21j/src/oscctrl/osc48mctrl.rs @@ -0,0 +1,207 @@ +#[doc = "Register `OSC48MCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OSC48MCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Oscillator Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Oscillator Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - On Demand Control"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - On Demand Control"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "48MHz Internal Oscillator (OSC48M) Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [osc48mctrl](index.html) module"] +pub struct OSC48MCTRL_SPEC; +impl crate::RegisterSpec for OSC48MCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [osc48mctrl::R](R) reader structure"] +impl crate::Readable for OSC48MCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [osc48mctrl::W](W) writer structure"] +impl crate::Writable for OSC48MCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OSC48MCTRL to value 0x82"] +impl crate::Resettable for OSC48MCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x82 + } +} diff --git a/pac/atsamc21j/src/oscctrl/osc48mdiv.rs b/pac/atsamc21j/src/oscctrl/osc48mdiv.rs new file mode 100644 index 000000000000..4ed854b09284 --- /dev/null +++ b/pac/atsamc21j/src/oscctrl/osc48mdiv.rs @@ -0,0 +1,334 @@ +#[doc = "Register `OSC48MDIV` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OSC48MDIV` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "OSC48M Division Factor\n\nValue on reset: 11"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DIV_A { + #[doc = "0: 48 MHz"] + DIV1 = 0, + #[doc = "1: 24 MHz"] + DIV2 = 1, + #[doc = "2: 16 MHz"] + DIV3 = 2, + #[doc = "3: 12 MHz"] + DIV4 = 3, + #[doc = "4: 9.6 MHz"] + DIV5 = 4, + #[doc = "5: 8 MHz"] + DIV6 = 5, + #[doc = "6: 6.86 MHz"] + DIV7 = 6, + #[doc = "7: 6 MHz"] + DIV8 = 7, + #[doc = "8: 5.33 MHz"] + DIV9 = 8, + #[doc = "9: 4.8 MHz"] + DIV10 = 9, + #[doc = "10: 4.36 MHz"] + DIV11 = 10, + #[doc = "11: 4 MHz"] + DIV12 = 11, + #[doc = "12: 3.69 MHz"] + DIV13 = 12, + #[doc = "13: 3.43 MHz"] + DIV14 = 13, + #[doc = "14: 3.2 MHz"] + DIV15 = 14, + #[doc = "15: 3 MHz"] + DIV16 = 15, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DIV_A) -> Self { + variant as _ + } +} +#[doc = "Field `DIV` reader - OSC48M Division Factor"] +pub struct DIV_R(crate::FieldReader); +impl DIV_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DIV_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DIV_A { + match self.bits { + 0 => DIV_A::DIV1, + 1 => DIV_A::DIV2, + 2 => DIV_A::DIV3, + 3 => DIV_A::DIV4, + 4 => DIV_A::DIV5, + 5 => DIV_A::DIV6, + 6 => DIV_A::DIV7, + 7 => DIV_A::DIV8, + 8 => DIV_A::DIV9, + 9 => DIV_A::DIV10, + 10 => DIV_A::DIV11, + 11 => DIV_A::DIV12, + 12 => DIV_A::DIV13, + 13 => DIV_A::DIV14, + 14 => DIV_A::DIV15, + 15 => DIV_A::DIV16, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == DIV_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == DIV_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV3`"] + #[inline(always)] + pub fn is_div3(&self) -> bool { + **self == DIV_A::DIV3 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == DIV_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV5`"] + #[inline(always)] + pub fn is_div5(&self) -> bool { + **self == DIV_A::DIV5 + } + #[doc = "Checks if the value of the field is `DIV6`"] + #[inline(always)] + pub fn is_div6(&self) -> bool { + **self == DIV_A::DIV6 + } + #[doc = "Checks if the value of the field is `DIV7`"] + #[inline(always)] + pub fn is_div7(&self) -> bool { + **self == DIV_A::DIV7 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == DIV_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV9`"] + #[inline(always)] + pub fn is_div9(&self) -> bool { + **self == DIV_A::DIV9 + } + #[doc = "Checks if the value of the field is `DIV10`"] + #[inline(always)] + pub fn is_div10(&self) -> bool { + **self == DIV_A::DIV10 + } + #[doc = "Checks if the value of the field is `DIV11`"] + #[inline(always)] + pub fn is_div11(&self) -> bool { + **self == DIV_A::DIV11 + } + #[doc = "Checks if the value of the field is `DIV12`"] + #[inline(always)] + pub fn is_div12(&self) -> bool { + **self == DIV_A::DIV12 + } + #[doc = "Checks if the value of the field is `DIV13`"] + #[inline(always)] + pub fn is_div13(&self) -> bool { + **self == DIV_A::DIV13 + } + #[doc = "Checks if the value of the field is `DIV14`"] + #[inline(always)] + pub fn is_div14(&self) -> bool { + **self == DIV_A::DIV14 + } + #[doc = "Checks if the value of the field is `DIV15`"] + #[inline(always)] + pub fn is_div15(&self) -> bool { + **self == DIV_A::DIV15 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == DIV_A::DIV16 + } +} +impl core::ops::Deref for DIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIV` writer - OSC48M Division Factor"] +pub struct DIV_W<'a> { + w: &'a mut W, +} +impl<'a> DIV_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DIV_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "48 MHz"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(DIV_A::DIV1) + } + #[doc = "24 MHz"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(DIV_A::DIV2) + } + #[doc = "16 MHz"] + #[inline(always)] + pub fn div3(self) -> &'a mut W { + self.variant(DIV_A::DIV3) + } + #[doc = "12 MHz"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(DIV_A::DIV4) + } + #[doc = "9.6 MHz"] + #[inline(always)] + pub fn div5(self) -> &'a mut W { + self.variant(DIV_A::DIV5) + } + #[doc = "8 MHz"] + #[inline(always)] + pub fn div6(self) -> &'a mut W { + self.variant(DIV_A::DIV6) + } + #[doc = "6.86 MHz"] + #[inline(always)] + pub fn div7(self) -> &'a mut W { + self.variant(DIV_A::DIV7) + } + #[doc = "6 MHz"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(DIV_A::DIV8) + } + #[doc = "5.33 MHz"] + #[inline(always)] + pub fn div9(self) -> &'a mut W { + self.variant(DIV_A::DIV9) + } + #[doc = "4.8 MHz"] + #[inline(always)] + pub fn div10(self) -> &'a mut W { + self.variant(DIV_A::DIV10) + } + #[doc = "4.36 MHz"] + #[inline(always)] + pub fn div11(self) -> &'a mut W { + self.variant(DIV_A::DIV11) + } + #[doc = "4 MHz"] + #[inline(always)] + pub fn div12(self) -> &'a mut W { + self.variant(DIV_A::DIV12) + } + #[doc = "3.69 MHz"] + #[inline(always)] + pub fn div13(self) -> &'a mut W { + self.variant(DIV_A::DIV13) + } + #[doc = "3.43 MHz"] + #[inline(always)] + pub fn div14(self) -> &'a mut W { + self.variant(DIV_A::DIV14) + } + #[doc = "3.2 MHz"] + #[inline(always)] + pub fn div15(self) -> &'a mut W { + self.variant(DIV_A::DIV15) + } + #[doc = "3 MHz"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(DIV_A::DIV16) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - OSC48M Division Factor"] + #[inline(always)] + pub fn div(&self) -> DIV_R { + DIV_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - OSC48M Division Factor"] + #[inline(always)] + pub fn div(&mut self) -> DIV_W { + DIV_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OSC48M Divider\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [osc48mdiv](index.html) module"] +pub struct OSC48MDIV_SPEC; +impl crate::RegisterSpec for OSC48MDIV_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [osc48mdiv::R](R) reader structure"] +impl crate::Readable for OSC48MDIV_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [osc48mdiv::W](W) writer structure"] +impl crate::Writable for OSC48MDIV_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OSC48MDIV to value 0x0b"] +impl crate::Resettable for OSC48MDIV_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0b + } +} diff --git a/pac/atsamc21j/src/oscctrl/osc48mstup.rs b/pac/atsamc21j/src/oscctrl/osc48mstup.rs new file mode 100644 index 000000000000..34da6bb7ef11 --- /dev/null +++ b/pac/atsamc21j/src/oscctrl/osc48mstup.rs @@ -0,0 +1,230 @@ +#[doc = "Register `OSC48MSTUP` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OSC48MSTUP` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Startup Time\n\nValue on reset: 7"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum STARTUP_A { + #[doc = "0: 166 ns"] + CYCLE8 = 0, + #[doc = "1: 333 ns"] + CYCLE16 = 1, + #[doc = "2: 667 ns"] + CYCLE32 = 2, + #[doc = "3: 1.333 us"] + CYCLE64 = 3, + #[doc = "4: 2.667 us"] + CYCLE128 = 4, + #[doc = "5: 5.333 us"] + CYCLE256 = 5, + #[doc = "6: 10.667 us"] + CYCLE512 = 6, + #[doc = "7: 21.333 us"] + CYCLE1024 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: STARTUP_A) -> Self { + variant as _ + } +} +#[doc = "Field `STARTUP` reader - Startup Time"] +pub struct STARTUP_R(crate::FieldReader); +impl STARTUP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + STARTUP_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STARTUP_A { + match self.bits { + 0 => STARTUP_A::CYCLE8, + 1 => STARTUP_A::CYCLE16, + 2 => STARTUP_A::CYCLE32, + 3 => STARTUP_A::CYCLE64, + 4 => STARTUP_A::CYCLE128, + 5 => STARTUP_A::CYCLE256, + 6 => STARTUP_A::CYCLE512, + 7 => STARTUP_A::CYCLE1024, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `CYCLE8`"] + #[inline(always)] + pub fn is_cycle8(&self) -> bool { + **self == STARTUP_A::CYCLE8 + } + #[doc = "Checks if the value of the field is `CYCLE16`"] + #[inline(always)] + pub fn is_cycle16(&self) -> bool { + **self == STARTUP_A::CYCLE16 + } + #[doc = "Checks if the value of the field is `CYCLE32`"] + #[inline(always)] + pub fn is_cycle32(&self) -> bool { + **self == STARTUP_A::CYCLE32 + } + #[doc = "Checks if the value of the field is `CYCLE64`"] + #[inline(always)] + pub fn is_cycle64(&self) -> bool { + **self == STARTUP_A::CYCLE64 + } + #[doc = "Checks if the value of the field is `CYCLE128`"] + #[inline(always)] + pub fn is_cycle128(&self) -> bool { + **self == STARTUP_A::CYCLE128 + } + #[doc = "Checks if the value of the field is `CYCLE256`"] + #[inline(always)] + pub fn is_cycle256(&self) -> bool { + **self == STARTUP_A::CYCLE256 + } + #[doc = "Checks if the value of the field is `CYCLE512`"] + #[inline(always)] + pub fn is_cycle512(&self) -> bool { + **self == STARTUP_A::CYCLE512 + } + #[doc = "Checks if the value of the field is `CYCLE1024`"] + #[inline(always)] + pub fn is_cycle1024(&self) -> bool { + **self == STARTUP_A::CYCLE1024 + } +} +impl core::ops::Deref for STARTUP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STARTUP` writer - Startup Time"] +pub struct STARTUP_W<'a> { + w: &'a mut W, +} +impl<'a> STARTUP_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: STARTUP_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "166 ns"] + #[inline(always)] + pub fn cycle8(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE8) + } + #[doc = "333 ns"] + #[inline(always)] + pub fn cycle16(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE16) + } + #[doc = "667 ns"] + #[inline(always)] + pub fn cycle32(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE32) + } + #[doc = "1.333 us"] + #[inline(always)] + pub fn cycle64(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE64) + } + #[doc = "2.667 us"] + #[inline(always)] + pub fn cycle128(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE128) + } + #[doc = "5.333 us"] + #[inline(always)] + pub fn cycle256(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE256) + } + #[doc = "10.667 us"] + #[inline(always)] + pub fn cycle512(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE512) + } + #[doc = "21.333 us"] + #[inline(always)] + pub fn cycle1024(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Startup Time"] + #[inline(always)] + pub fn startup(&self) -> STARTUP_R { + STARTUP_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Startup Time"] + #[inline(always)] + pub fn startup(&mut self) -> STARTUP_W { + STARTUP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OSC48M Startup Time\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [osc48mstup](index.html) module"] +pub struct OSC48MSTUP_SPEC; +impl crate::RegisterSpec for OSC48MSTUP_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [osc48mstup::R](R) reader structure"] +impl crate::Readable for OSC48MSTUP_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [osc48mstup::W](W) writer structure"] +impl crate::Writable for OSC48MSTUP_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OSC48MSTUP to value 0x07"] +impl crate::Resettable for OSC48MSTUP_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x07 + } +} diff --git a/pac/atsamc21j/src/oscctrl/osc48msyncbusy.rs b/pac/atsamc21j/src/oscctrl/osc48msyncbusy.rs new file mode 100644 index 000000000000..8d4410ae630a --- /dev/null +++ b/pac/atsamc21j/src/oscctrl/osc48msyncbusy.rs @@ -0,0 +1,53 @@ +#[doc = "Register `OSC48MSYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `OSC48MDIV` reader - OSC48MDIV Synchronization Status"] +pub struct OSC48MDIV_R(crate::FieldReader); +impl OSC48MDIV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC48MDIV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC48MDIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 2 - OSC48MDIV Synchronization Status"] + #[inline(always)] + pub fn osc48mdiv(&self) -> OSC48MDIV_R { + OSC48MDIV_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +#[doc = "OSC48M Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [osc48msyncbusy](index.html) module"] +pub struct OSC48MSYNCBUSY_SPEC; +impl crate::RegisterSpec for OSC48MSYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [osc48msyncbusy::R](R) reader structure"] +impl crate::Readable for OSC48MSYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets OSC48MSYNCBUSY to value 0"] +impl crate::Resettable for OSC48MSYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/oscctrl/status.rs b/pac/atsamc21j/src/oscctrl/status.rs new file mode 100644 index 000000000000..3025966192a3 --- /dev/null +++ b/pac/atsamc21j/src/oscctrl/status.rs @@ -0,0 +1,193 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `XOSCRDY` reader - XOSC Ready"] +pub struct XOSCRDY_R(crate::FieldReader); +impl XOSCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSCFAIL` reader - XOSC Clock Failure Detector"] +pub struct XOSCFAIL_R(crate::FieldReader); +impl XOSCFAIL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSCFAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCFAIL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSCCKSW` reader - XOSC Clock Switch"] +pub struct XOSCCKSW_R(crate::FieldReader); +impl XOSCCKSW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSCCKSW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCCKSW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC48MRDY` reader - OSC48M Ready"] +pub struct OSC48MRDY_R(crate::FieldReader); +impl OSC48MRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC48MRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC48MRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKR` reader - DPLL Lock Rise"] +pub struct DPLLLCKR_R(crate::FieldReader); +impl DPLLLCKR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKF` reader - DPLL Lock Fall"] +pub struct DPLLLCKF_R(crate::FieldReader); +impl DPLLLCKF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLTO` reader - DPLL Timeout"] +pub struct DPLLTO_R(crate::FieldReader); +impl DPLLTO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLTO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLDRTO` reader - DPLL Ratio Ready"] +pub struct DPLLLDRTO_R(crate::FieldReader); +impl DPLLLDRTO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLDRTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLDRTO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - XOSC Ready"] + #[inline(always)] + pub fn xoscrdy(&self) -> XOSCRDY_R { + XOSCRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - XOSC Clock Failure Detector"] + #[inline(always)] + pub fn xoscfail(&self) -> XOSCFAIL_R { + XOSCFAIL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - XOSC Clock Switch"] + #[inline(always)] + pub fn xosccksw(&self) -> XOSCCKSW_R { + XOSCCKSW_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 4 - OSC48M Ready"] + #[inline(always)] + pub fn osc48mrdy(&self) -> OSC48MRDY_R { + OSC48MRDY_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 8 - DPLL Lock Rise"] + #[inline(always)] + pub fn dplllckr(&self) -> DPLLLCKR_R { + DPLLLCKR_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - DPLL Lock Fall"] + #[inline(always)] + pub fn dplllckf(&self) -> DPLLLCKF_R { + DPLLLCKF_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - DPLL Timeout"] + #[inline(always)] + pub fn dpllto(&self) -> DPLLTO_R { + DPLLTO_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - DPLL Ratio Ready"] + #[inline(always)] + pub fn dpllldrto(&self) -> DPLLLDRTO_R { + DPLLLDRTO_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +#[doc = "Power and Clocks Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/oscctrl/xoscctrl.rs b/pac/atsamc21j/src/oscctrl/xoscctrl.rs new file mode 100644 index 000000000000..3a5319565c10 --- /dev/null +++ b/pac/atsamc21j/src/oscctrl/xoscctrl.rs @@ -0,0 +1,788 @@ +#[doc = "Register `XOSCCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `XOSCCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Oscillator Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Oscillator Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `XTALEN` reader - Crystal Oscillator Enable"] +pub struct XTALEN_R(crate::FieldReader); +impl XTALEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XTALEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XTALEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XTALEN` writer - Crystal Oscillator Enable"] +pub struct XTALEN_W<'a> { + w: &'a mut W, +} +impl<'a> XTALEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CFDEN` reader - Xosc Clock Failure Detector Enable"] +pub struct CFDEN_R(crate::FieldReader); +impl CFDEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFDEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFDEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFDEN` writer - Xosc Clock Failure Detector Enable"] +pub struct CFDEN_W<'a> { + w: &'a mut W, +} +impl<'a> CFDEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `SWBEN` reader - Xosc Clock Switch Enable"] +pub struct SWBEN_R(crate::FieldReader); +impl SWBEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWBEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWBEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWBEN` writer - Xosc Clock Switch Enable"] +pub struct SWBEN_W<'a> { + w: &'a mut W, +} +impl<'a> SWBEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - On Demand Control"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - On Demand Control"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Oscillator Gain\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum GAIN_A { + #[doc = "0: 2 MHz"] + GAIN2 = 0, + #[doc = "1: 4 MHz"] + GAIN4 = 1, + #[doc = "2: 8 MHz"] + GAIN8 = 2, + #[doc = "3: 16 MHz"] + GAIN16 = 3, + #[doc = "4: 30 MHz"] + GAIN30 = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: GAIN_A) -> Self { + variant as _ + } +} +#[doc = "Field `GAIN` reader - Oscillator Gain"] +pub struct GAIN_R(crate::FieldReader); +impl GAIN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + GAIN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(GAIN_A::GAIN2), + 1 => Some(GAIN_A::GAIN4), + 2 => Some(GAIN_A::GAIN8), + 3 => Some(GAIN_A::GAIN16), + 4 => Some(GAIN_A::GAIN30), + _ => None, + } + } + #[doc = "Checks if the value of the field is `GAIN2`"] + #[inline(always)] + pub fn is_gain2(&self) -> bool { + **self == GAIN_A::GAIN2 + } + #[doc = "Checks if the value of the field is `GAIN4`"] + #[inline(always)] + pub fn is_gain4(&self) -> bool { + **self == GAIN_A::GAIN4 + } + #[doc = "Checks if the value of the field is `GAIN8`"] + #[inline(always)] + pub fn is_gain8(&self) -> bool { + **self == GAIN_A::GAIN8 + } + #[doc = "Checks if the value of the field is `GAIN16`"] + #[inline(always)] + pub fn is_gain16(&self) -> bool { + **self == GAIN_A::GAIN16 + } + #[doc = "Checks if the value of the field is `GAIN30`"] + #[inline(always)] + pub fn is_gain30(&self) -> bool { + **self == GAIN_A::GAIN30 + } +} +impl core::ops::Deref for GAIN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GAIN` writer - Oscillator Gain"] +pub struct GAIN_W<'a> { + w: &'a mut W, +} +impl<'a> GAIN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: GAIN_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "2 MHz"] + #[inline(always)] + pub fn gain2(self) -> &'a mut W { + self.variant(GAIN_A::GAIN2) + } + #[doc = "4 MHz"] + #[inline(always)] + pub fn gain4(self) -> &'a mut W { + self.variant(GAIN_A::GAIN4) + } + #[doc = "8 MHz"] + #[inline(always)] + pub fn gain8(self) -> &'a mut W { + self.variant(GAIN_A::GAIN8) + } + #[doc = "16 MHz"] + #[inline(always)] + pub fn gain16(self) -> &'a mut W { + self.variant(GAIN_A::GAIN16) + } + #[doc = "30 MHz"] + #[inline(always)] + pub fn gain30(self) -> &'a mut W { + self.variant(GAIN_A::GAIN30) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u16 & 0x07) << 8); + self.w + } +} +#[doc = "Field `AMPGC` reader - Automatic Amplitude Gain Control"] +pub struct AMPGC_R(crate::FieldReader); +impl AMPGC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AMPGC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AMPGC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AMPGC` writer - Automatic Amplitude Gain Control"] +pub struct AMPGC_W<'a> { + w: &'a mut W, +} +impl<'a> AMPGC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u16 & 0x01) << 11); + self.w + } +} +#[doc = "Start-Up Time\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum STARTUP_A { + #[doc = "0: 31 us"] + CYCLE1 = 0, + #[doc = "1: 61 us"] + CYCLE2 = 1, + #[doc = "2: 122 us"] + CYCLE4 = 2, + #[doc = "3: 244 us"] + CYCLE8 = 3, + #[doc = "4: 488 us"] + CYCLE16 = 4, + #[doc = "5: 977 us"] + CYCLE32 = 5, + #[doc = "6: 1953 us"] + CYCLE64 = 6, + #[doc = "7: 3906 us"] + CYCLE128 = 7, + #[doc = "8: 7813 us"] + CYCLE256 = 8, + #[doc = "9: 15625 us"] + CYCLE512 = 9, + #[doc = "10: 31250 us"] + CYCLE1024 = 10, + #[doc = "11: 62500 us"] + CYCLE2048 = 11, + #[doc = "12: 125000 us"] + CYCLE4096 = 12, + #[doc = "13: 250000 us"] + CYCLE8192 = 13, + #[doc = "14: 500000 us"] + CYCLE16384 = 14, + #[doc = "15: 1000000 us"] + CYCLE32768 = 15, +} +impl From for u8 { + #[inline(always)] + fn from(variant: STARTUP_A) -> Self { + variant as _ + } +} +#[doc = "Field `STARTUP` reader - Start-Up Time"] +pub struct STARTUP_R(crate::FieldReader); +impl STARTUP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + STARTUP_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STARTUP_A { + match self.bits { + 0 => STARTUP_A::CYCLE1, + 1 => STARTUP_A::CYCLE2, + 2 => STARTUP_A::CYCLE4, + 3 => STARTUP_A::CYCLE8, + 4 => STARTUP_A::CYCLE16, + 5 => STARTUP_A::CYCLE32, + 6 => STARTUP_A::CYCLE64, + 7 => STARTUP_A::CYCLE128, + 8 => STARTUP_A::CYCLE256, + 9 => STARTUP_A::CYCLE512, + 10 => STARTUP_A::CYCLE1024, + 11 => STARTUP_A::CYCLE2048, + 12 => STARTUP_A::CYCLE4096, + 13 => STARTUP_A::CYCLE8192, + 14 => STARTUP_A::CYCLE16384, + 15 => STARTUP_A::CYCLE32768, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `CYCLE1`"] + #[inline(always)] + pub fn is_cycle1(&self) -> bool { + **self == STARTUP_A::CYCLE1 + } + #[doc = "Checks if the value of the field is `CYCLE2`"] + #[inline(always)] + pub fn is_cycle2(&self) -> bool { + **self == STARTUP_A::CYCLE2 + } + #[doc = "Checks if the value of the field is `CYCLE4`"] + #[inline(always)] + pub fn is_cycle4(&self) -> bool { + **self == STARTUP_A::CYCLE4 + } + #[doc = "Checks if the value of the field is `CYCLE8`"] + #[inline(always)] + pub fn is_cycle8(&self) -> bool { + **self == STARTUP_A::CYCLE8 + } + #[doc = "Checks if the value of the field is `CYCLE16`"] + #[inline(always)] + pub fn is_cycle16(&self) -> bool { + **self == STARTUP_A::CYCLE16 + } + #[doc = "Checks if the value of the field is `CYCLE32`"] + #[inline(always)] + pub fn is_cycle32(&self) -> bool { + **self == STARTUP_A::CYCLE32 + } + #[doc = "Checks if the value of the field is `CYCLE64`"] + #[inline(always)] + pub fn is_cycle64(&self) -> bool { + **self == STARTUP_A::CYCLE64 + } + #[doc = "Checks if the value of the field is `CYCLE128`"] + #[inline(always)] + pub fn is_cycle128(&self) -> bool { + **self == STARTUP_A::CYCLE128 + } + #[doc = "Checks if the value of the field is `CYCLE256`"] + #[inline(always)] + pub fn is_cycle256(&self) -> bool { + **self == STARTUP_A::CYCLE256 + } + #[doc = "Checks if the value of the field is `CYCLE512`"] + #[inline(always)] + pub fn is_cycle512(&self) -> bool { + **self == STARTUP_A::CYCLE512 + } + #[doc = "Checks if the value of the field is `CYCLE1024`"] + #[inline(always)] + pub fn is_cycle1024(&self) -> bool { + **self == STARTUP_A::CYCLE1024 + } + #[doc = "Checks if the value of the field is `CYCLE2048`"] + #[inline(always)] + pub fn is_cycle2048(&self) -> bool { + **self == STARTUP_A::CYCLE2048 + } + #[doc = "Checks if the value of the field is `CYCLE4096`"] + #[inline(always)] + pub fn is_cycle4096(&self) -> bool { + **self == STARTUP_A::CYCLE4096 + } + #[doc = "Checks if the value of the field is `CYCLE8192`"] + #[inline(always)] + pub fn is_cycle8192(&self) -> bool { + **self == STARTUP_A::CYCLE8192 + } + #[doc = "Checks if the value of the field is `CYCLE16384`"] + #[inline(always)] + pub fn is_cycle16384(&self) -> bool { + **self == STARTUP_A::CYCLE16384 + } + #[doc = "Checks if the value of the field is `CYCLE32768`"] + #[inline(always)] + pub fn is_cycle32768(&self) -> bool { + **self == STARTUP_A::CYCLE32768 + } +} +impl core::ops::Deref for STARTUP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STARTUP` writer - Start-Up Time"] +pub struct STARTUP_W<'a> { + w: &'a mut W, +} +impl<'a> STARTUP_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: STARTUP_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "31 us"] + #[inline(always)] + pub fn cycle1(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE1) + } + #[doc = "61 us"] + #[inline(always)] + pub fn cycle2(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE2) + } + #[doc = "122 us"] + #[inline(always)] + pub fn cycle4(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE4) + } + #[doc = "244 us"] + #[inline(always)] + pub fn cycle8(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE8) + } + #[doc = "488 us"] + #[inline(always)] + pub fn cycle16(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE16) + } + #[doc = "977 us"] + #[inline(always)] + pub fn cycle32(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE32) + } + #[doc = "1953 us"] + #[inline(always)] + pub fn cycle64(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE64) + } + #[doc = "3906 us"] + #[inline(always)] + pub fn cycle128(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE128) + } + #[doc = "7813 us"] + #[inline(always)] + pub fn cycle256(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE256) + } + #[doc = "15625 us"] + #[inline(always)] + pub fn cycle512(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE512) + } + #[doc = "31250 us"] + #[inline(always)] + pub fn cycle1024(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE1024) + } + #[doc = "62500 us"] + #[inline(always)] + pub fn cycle2048(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE2048) + } + #[doc = "125000 us"] + #[inline(always)] + pub fn cycle4096(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE4096) + } + #[doc = "250000 us"] + #[inline(always)] + pub fn cycle8192(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE8192) + } + #[doc = "500000 us"] + #[inline(always)] + pub fn cycle16384(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE16384) + } + #[doc = "1000000 us"] + #[inline(always)] + pub fn cycle32768(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE32768) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 12)) | ((value as u16 & 0x0f) << 12); + self.w + } +} +impl R { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Crystal Oscillator Enable"] + #[inline(always)] + pub fn xtalen(&self) -> XTALEN_R { + XTALEN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Xosc Clock Failure Detector Enable"] + #[inline(always)] + pub fn cfden(&self) -> CFDEN_R { + CFDEN_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Xosc Clock Switch Enable"] + #[inline(always)] + pub fn swben(&self) -> SWBEN_R { + SWBEN_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Oscillator Gain"] + #[inline(always)] + pub fn gain(&self) -> GAIN_R { + GAIN_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 11 - Automatic Amplitude Gain Control"] + #[inline(always)] + pub fn ampgc(&self) -> AMPGC_R { + AMPGC_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bits 12:15 - Start-Up Time"] + #[inline(always)] + pub fn startup(&self) -> STARTUP_R { + STARTUP_R::new(((self.bits >> 12) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - Crystal Oscillator Enable"] + #[inline(always)] + pub fn xtalen(&mut self) -> XTALEN_W { + XTALEN_W { w: self } + } + #[doc = "Bit 3 - Xosc Clock Failure Detector Enable"] + #[inline(always)] + pub fn cfden(&mut self) -> CFDEN_W { + CFDEN_W { w: self } + } + #[doc = "Bit 4 - Xosc Clock Switch Enable"] + #[inline(always)] + pub fn swben(&mut self) -> SWBEN_W { + SWBEN_W { w: self } + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Bits 8:10 - Oscillator Gain"] + #[inline(always)] + pub fn gain(&mut self) -> GAIN_W { + GAIN_W { w: self } + } + #[doc = "Bit 11 - Automatic Amplitude Gain Control"] + #[inline(always)] + pub fn ampgc(&mut self) -> AMPGC_W { + AMPGC_W { w: self } + } + #[doc = "Bits 12:15 - Start-Up Time"] + #[inline(always)] + pub fn startup(&mut self) -> STARTUP_W { + STARTUP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "External Multipurpose Crystal Oscillator (XOSC) Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [xoscctrl](index.html) module"] +pub struct XOSCCTRL_SPEC; +impl crate::RegisterSpec for XOSCCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [xoscctrl::R](R) reader structure"] +impl crate::Readable for XOSCCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [xoscctrl::W](W) writer structure"] +impl crate::Writable for XOSCCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets XOSCCTRL to value 0x80"] +impl crate::Resettable for XOSCCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x80 + } +} diff --git a/pac/atsamc21j/src/pac.rs b/pac/atsamc21j/src/pac.rs new file mode 100644 index 000000000000..3e365e081945 --- /dev/null +++ b/pac/atsamc21j/src/pac.rs @@ -0,0 +1,73 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Write control"] + pub wrctrl: crate::Reg, + #[doc = "0x04 - Event control"] + pub evctrl: crate::Reg, + _reserved2: [u8; 0x03], + #[doc = "0x08 - Interrupt enable clear"] + pub intenclr: crate::Reg, + #[doc = "0x09 - Interrupt enable set"] + pub intenset: crate::Reg, + _reserved4: [u8; 0x06], + #[doc = "0x10 - Bridge interrupt flag status"] + pub intflagahb: crate::Reg, + #[doc = "0x14 - Peripheral interrupt flag status - Bridge A"] + pub intflaga: crate::Reg, + #[doc = "0x18 - Peripheral interrupt flag status - Bridge B"] + pub intflagb: crate::Reg, + #[doc = "0x1c - Peripheral interrupt flag status - Bridge C"] + pub intflagc: crate::Reg, + _reserved8: [u8; 0x14], + #[doc = "0x34 - Peripheral write protection status - Bridge A"] + pub statusa: crate::Reg, + #[doc = "0x38 - Peripheral write protection status - Bridge B"] + pub statusb: crate::Reg, + #[doc = "0x3c - Peripheral write protection status - Bridge C"] + pub statusc: crate::Reg, +} +#[doc = "WRCTRL register accessor: an alias for `Reg`"] +pub type WRCTRL = crate::Reg; +#[doc = "Write control"] +pub mod wrctrl; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt enable clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt enable set"] +pub mod intenset; +#[doc = "INTFLAGAHB register accessor: an alias for `Reg`"] +pub type INTFLAGAHB = crate::Reg; +#[doc = "Bridge interrupt flag status"] +pub mod intflagahb; +#[doc = "INTFLAGA register accessor: an alias for `Reg`"] +pub type INTFLAGA = crate::Reg; +#[doc = "Peripheral interrupt flag status - Bridge A"] +pub mod intflaga; +#[doc = "INTFLAGB register accessor: an alias for `Reg`"] +pub type INTFLAGB = crate::Reg; +#[doc = "Peripheral interrupt flag status - Bridge B"] +pub mod intflagb; +#[doc = "INTFLAGC register accessor: an alias for `Reg`"] +pub type INTFLAGC = crate::Reg; +#[doc = "Peripheral interrupt flag status - Bridge C"] +pub mod intflagc; +#[doc = "STATUSA register accessor: an alias for `Reg`"] +pub type STATUSA = crate::Reg; +#[doc = "Peripheral write protection status - Bridge A"] +pub mod statusa; +#[doc = "STATUSB register accessor: an alias for `Reg`"] +pub type STATUSB = crate::Reg; +#[doc = "Peripheral write protection status - Bridge B"] +pub mod statusb; +#[doc = "STATUSC register accessor: an alias for `Reg`"] +pub type STATUSC = crate::Reg; +#[doc = "Peripheral write protection status - Bridge C"] +pub mod statusc; diff --git a/pac/atsamc21j/src/pac/evctrl.rs b/pac/atsamc21j/src/pac/evctrl.rs new file mode 100644 index 000000000000..630581b98c85 --- /dev/null +++ b/pac/atsamc21j/src/pac/evctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ERREO` reader - Peripheral acess error event output"] +pub struct ERREO_R(crate::FieldReader); +impl ERREO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERREO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERREO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERREO` writer - Peripheral acess error event output"] +pub struct ERREO_W<'a> { + w: &'a mut W, +} +impl<'a> ERREO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Peripheral acess error event output"] + #[inline(always)] + pub fn erreo(&self) -> ERREO_R { + ERREO_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Peripheral acess error event output"] + #[inline(always)] + pub fn erreo(&mut self) -> ERREO_W { + ERREO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/pac/intenclr.rs b/pac/atsamc21j/src/pac/intenclr.rs new file mode 100644 index 000000000000..609fe0fcf628 --- /dev/null +++ b/pac/atsamc21j/src/pac/intenclr.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ERR` reader - Peripheral access error interrupt disable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - Peripheral access error interrupt disable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Peripheral access error interrupt disable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Peripheral access error interrupt disable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt enable clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/pac/intenset.rs b/pac/atsamc21j/src/pac/intenset.rs new file mode 100644 index 000000000000..390545b588de --- /dev/null +++ b/pac/atsamc21j/src/pac/intenset.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ERR` reader - Peripheral access error interrupt enable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - Peripheral access error interrupt enable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Peripheral access error interrupt enable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Peripheral access error interrupt enable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt enable set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/pac/intflaga.rs b/pac/atsamc21j/src/pac/intflaga.rs new file mode 100644 index 000000000000..a1603451ad72 --- /dev/null +++ b/pac/atsamc21j/src/pac/intflaga.rs @@ -0,0 +1,677 @@ +#[doc = "Register `INTFLAGA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAGA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PAC_` reader - PAC"] +pub struct PAC__R(crate::FieldReader); +impl PAC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PAC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PAC_` writer - PAC"] +pub struct PAC__W<'a> { + w: &'a mut W, +} +impl<'a> PAC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `PM_` reader - PM"] +pub struct PM__R(crate::FieldReader); +impl PM__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PM__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PM__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PM_` writer - PM"] +pub struct PM__W<'a> { + w: &'a mut W, +} +impl<'a> PM__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MCLK_` reader - MCLK"] +pub struct MCLK__R(crate::FieldReader); +impl MCLK__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCLK__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCLK__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCLK_` writer - MCLK"] +pub struct MCLK__W<'a> { + w: &'a mut W, +} +impl<'a> MCLK__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RSTC_` reader - RSTC"] +pub struct RSTC__R(crate::FieldReader); +impl RSTC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RSTC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RSTC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RSTC_` writer - RSTC"] +pub struct RSTC__W<'a> { + w: &'a mut W, +} +impl<'a> RSTC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `OSCCTRL_` reader - OSCCTRL"] +pub struct OSCCTRL__R(crate::FieldReader); +impl OSCCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSCCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSCCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSCCTRL_` writer - OSCCTRL"] +pub struct OSCCTRL__W<'a> { + w: &'a mut W, +} +impl<'a> OSCCTRL__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `OSC32KCTRL_` reader - OSC32KCTRL"] +pub struct OSC32KCTRL__R(crate::FieldReader); +impl OSC32KCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC32KCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC32KCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC32KCTRL_` writer - OSC32KCTRL"] +pub struct OSC32KCTRL__W<'a> { + w: &'a mut W, +} +impl<'a> OSC32KCTRL__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `SUPC_` reader - SUPC"] +pub struct SUPC__R(crate::FieldReader); +impl SUPC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SUPC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SUPC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SUPC_` writer - SUPC"] +pub struct SUPC__W<'a> { + w: &'a mut W, +} +impl<'a> SUPC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `GCLK_` reader - GCLK"] +pub struct GCLK__R(crate::FieldReader); +impl GCLK__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GCLK__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GCLK__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GCLK_` writer - GCLK"] +pub struct GCLK__W<'a> { + w: &'a mut W, +} +impl<'a> GCLK__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `WDT_` reader - WDT"] +pub struct WDT__R(crate::FieldReader); +impl WDT__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WDT__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WDT__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WDT_` writer - WDT"] +pub struct WDT__W<'a> { + w: &'a mut W, +} +impl<'a> WDT__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `RTC_` reader - RTC"] +pub struct RTC__R(crate::FieldReader); +impl RTC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RTC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RTC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RTC_` writer - RTC"] +pub struct RTC__W<'a> { + w: &'a mut W, +} +impl<'a> RTC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `EIC_` reader - EIC"] +pub struct EIC__R(crate::FieldReader); +impl EIC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EIC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EIC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EIC_` writer - EIC"] +pub struct EIC__W<'a> { + w: &'a mut W, +} +impl<'a> EIC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `FREQM_` reader - FREQM"] +pub struct FREQM__R(crate::FieldReader); +impl FREQM__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FREQM__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FREQM__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FREQM_` writer - FREQM"] +pub struct FREQM__W<'a> { + w: &'a mut W, +} +impl<'a> FREQM__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `TSENS_` reader - TSENS"] +pub struct TSENS__R(crate::FieldReader); +impl TSENS__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSENS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSENS__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSENS_` writer - TSENS"] +pub struct TSENS__W<'a> { + w: &'a mut W, +} +impl<'a> TSENS__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +impl R { + #[doc = "Bit 0 - PAC"] + #[inline(always)] + pub fn pac_(&self) -> PAC__R { + PAC__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - PM"] + #[inline(always)] + pub fn pm_(&self) -> PM__R { + PM__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - MCLK"] + #[inline(always)] + pub fn mclk_(&self) -> MCLK__R { + MCLK__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - RSTC"] + #[inline(always)] + pub fn rstc_(&self) -> RSTC__R { + RSTC__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - OSCCTRL"] + #[inline(always)] + pub fn oscctrl_(&self) -> OSCCTRL__R { + OSCCTRL__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - OSC32KCTRL"] + #[inline(always)] + pub fn osc32kctrl_(&self) -> OSC32KCTRL__R { + OSC32KCTRL__R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - SUPC"] + #[inline(always)] + pub fn supc_(&self) -> SUPC__R { + SUPC__R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - GCLK"] + #[inline(always)] + pub fn gclk_(&self) -> GCLK__R { + GCLK__R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - WDT"] + #[inline(always)] + pub fn wdt_(&self) -> WDT__R { + WDT__R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - RTC"] + #[inline(always)] + pub fn rtc_(&self) -> RTC__R { + RTC__R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - EIC"] + #[inline(always)] + pub fn eic_(&self) -> EIC__R { + EIC__R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - FREQM"] + #[inline(always)] + pub fn freqm_(&self) -> FREQM__R { + FREQM__R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - TSENS"] + #[inline(always)] + pub fn tsens_(&self) -> TSENS__R { + TSENS__R::new(((self.bits >> 12) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - PAC"] + #[inline(always)] + pub fn pac_(&mut self) -> PAC__W { + PAC__W { w: self } + } + #[doc = "Bit 1 - PM"] + #[inline(always)] + pub fn pm_(&mut self) -> PM__W { + PM__W { w: self } + } + #[doc = "Bit 2 - MCLK"] + #[inline(always)] + pub fn mclk_(&mut self) -> MCLK__W { + MCLK__W { w: self } + } + #[doc = "Bit 3 - RSTC"] + #[inline(always)] + pub fn rstc_(&mut self) -> RSTC__W { + RSTC__W { w: self } + } + #[doc = "Bit 4 - OSCCTRL"] + #[inline(always)] + pub fn oscctrl_(&mut self) -> OSCCTRL__W { + OSCCTRL__W { w: self } + } + #[doc = "Bit 5 - OSC32KCTRL"] + #[inline(always)] + pub fn osc32kctrl_(&mut self) -> OSC32KCTRL__W { + OSC32KCTRL__W { w: self } + } + #[doc = "Bit 6 - SUPC"] + #[inline(always)] + pub fn supc_(&mut self) -> SUPC__W { + SUPC__W { w: self } + } + #[doc = "Bit 7 - GCLK"] + #[inline(always)] + pub fn gclk_(&mut self) -> GCLK__W { + GCLK__W { w: self } + } + #[doc = "Bit 8 - WDT"] + #[inline(always)] + pub fn wdt_(&mut self) -> WDT__W { + WDT__W { w: self } + } + #[doc = "Bit 9 - RTC"] + #[inline(always)] + pub fn rtc_(&mut self) -> RTC__W { + RTC__W { w: self } + } + #[doc = "Bit 10 - EIC"] + #[inline(always)] + pub fn eic_(&mut self) -> EIC__W { + EIC__W { w: self } + } + #[doc = "Bit 11 - FREQM"] + #[inline(always)] + pub fn freqm_(&mut self) -> FREQM__W { + FREQM__W { w: self } + } + #[doc = "Bit 12 - TSENS"] + #[inline(always)] + pub fn tsens_(&mut self) -> TSENS__W { + TSENS__W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Peripheral interrupt flag status - Bridge A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflaga](index.html) module"] +pub struct INTFLAGA_SPEC; +impl crate::RegisterSpec for INTFLAGA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflaga::R](R) reader structure"] +impl crate::Readable for INTFLAGA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflaga::W](W) writer structure"] +impl crate::Writable for INTFLAGA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAGA to value 0"] +impl crate::Resettable for INTFLAGA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/pac/intflagahb.rs b/pac/atsamc21j/src/pac/intflagahb.rs new file mode 100644 index 000000000000..4b7f7377e25e --- /dev/null +++ b/pac/atsamc21j/src/pac/intflagahb.rs @@ -0,0 +1,442 @@ +#[doc = "Register `INTFLAGAHB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAGAHB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FLASH_` reader - FLASH"] +pub struct FLASH__R(crate::FieldReader); +impl FLASH__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FLASH__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FLASH__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLASH_` writer - FLASH"] +pub struct FLASH__W<'a> { + w: &'a mut W, +} +impl<'a> FLASH__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `HSRAMCM0P_` reader - HSRAMCM0P"] +pub struct HSRAMCM0P__R(crate::FieldReader); +impl HSRAMCM0P__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HSRAMCM0P__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HSRAMCM0P__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HSRAMCM0P_` writer - HSRAMCM0P"] +pub struct HSRAMCM0P__W<'a> { + w: &'a mut W, +} +impl<'a> HSRAMCM0P__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `HSRAMDSU_` reader - HSRAMDSU"] +pub struct HSRAMDSU__R(crate::FieldReader); +impl HSRAMDSU__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HSRAMDSU__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HSRAMDSU__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HSRAMDSU_` writer - HSRAMDSU"] +pub struct HSRAMDSU__W<'a> { + w: &'a mut W, +} +impl<'a> HSRAMDSU__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `HPB1_` reader - HPB1"] +pub struct HPB1__R(crate::FieldReader); +impl HPB1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HPB1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HPB1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HPB1_` writer - HPB1"] +pub struct HPB1__W<'a> { + w: &'a mut W, +} +impl<'a> HPB1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `HPB0_` reader - HPB0"] +pub struct HPB0__R(crate::FieldReader); +impl HPB0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HPB0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HPB0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HPB0_` writer - HPB0"] +pub struct HPB0__W<'a> { + w: &'a mut W, +} +impl<'a> HPB0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `HPB2_` reader - HPB2"] +pub struct HPB2__R(crate::FieldReader); +impl HPB2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HPB2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HPB2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HPB2_` writer - HPB2"] +pub struct HPB2__W<'a> { + w: &'a mut W, +} +impl<'a> HPB2__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `LPRAMDMAC_` reader - LPRAMDMAC"] +pub struct LPRAMDMAC__R(crate::FieldReader); +impl LPRAMDMAC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LPRAMDMAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LPRAMDMAC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LPRAMDMAC_` writer - LPRAMDMAC"] +pub struct LPRAMDMAC__W<'a> { + w: &'a mut W, +} +impl<'a> LPRAMDMAC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `DIVAS_` reader - DIVAS"] +pub struct DIVAS__R(crate::FieldReader); +impl DIVAS__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIVAS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIVAS__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIVAS_` writer - DIVAS"] +pub struct DIVAS__W<'a> { + w: &'a mut W, +} +impl<'a> DIVAS__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - FLASH"] + #[inline(always)] + pub fn flash_(&self) -> FLASH__R { + FLASH__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - HSRAMCM0P"] + #[inline(always)] + pub fn hsramcm0p_(&self) -> HSRAMCM0P__R { + HSRAMCM0P__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - HSRAMDSU"] + #[inline(always)] + pub fn hsramdsu_(&self) -> HSRAMDSU__R { + HSRAMDSU__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - HPB1"] + #[inline(always)] + pub fn hpb1_(&self) -> HPB1__R { + HPB1__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - HPB0"] + #[inline(always)] + pub fn hpb0_(&self) -> HPB0__R { + HPB0__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - HPB2"] + #[inline(always)] + pub fn hpb2_(&self) -> HPB2__R { + HPB2__R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - LPRAMDMAC"] + #[inline(always)] + pub fn lpramdmac_(&self) -> LPRAMDMAC__R { + LPRAMDMAC__R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - DIVAS"] + #[inline(always)] + pub fn divas_(&self) -> DIVAS__R { + DIVAS__R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - FLASH"] + #[inline(always)] + pub fn flash_(&mut self) -> FLASH__W { + FLASH__W { w: self } + } + #[doc = "Bit 1 - HSRAMCM0P"] + #[inline(always)] + pub fn hsramcm0p_(&mut self) -> HSRAMCM0P__W { + HSRAMCM0P__W { w: self } + } + #[doc = "Bit 2 - HSRAMDSU"] + #[inline(always)] + pub fn hsramdsu_(&mut self) -> HSRAMDSU__W { + HSRAMDSU__W { w: self } + } + #[doc = "Bit 3 - HPB1"] + #[inline(always)] + pub fn hpb1_(&mut self) -> HPB1__W { + HPB1__W { w: self } + } + #[doc = "Bit 4 - HPB0"] + #[inline(always)] + pub fn hpb0_(&mut self) -> HPB0__W { + HPB0__W { w: self } + } + #[doc = "Bit 5 - HPB2"] + #[inline(always)] + pub fn hpb2_(&mut self) -> HPB2__W { + HPB2__W { w: self } + } + #[doc = "Bit 6 - LPRAMDMAC"] + #[inline(always)] + pub fn lpramdmac_(&mut self) -> LPRAMDMAC__W { + LPRAMDMAC__W { w: self } + } + #[doc = "Bit 7 - DIVAS"] + #[inline(always)] + pub fn divas_(&mut self) -> DIVAS__W { + DIVAS__W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Bridge interrupt flag status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflagahb](index.html) module"] +pub struct INTFLAGAHB_SPEC; +impl crate::RegisterSpec for INTFLAGAHB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflagahb::R](R) reader structure"] +impl crate::Readable for INTFLAGAHB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflagahb::W](W) writer structure"] +impl crate::Writable for INTFLAGAHB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAGAHB to value 0"] +impl crate::Resettable for INTFLAGAHB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/pac/intflagb.rs b/pac/atsamc21j/src/pac/intflagb.rs new file mode 100644 index 000000000000..8359f7e11f30 --- /dev/null +++ b/pac/atsamc21j/src/pac/intflagb.rs @@ -0,0 +1,348 @@ +#[doc = "Register `INTFLAGB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAGB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PORT_` reader - PORT"] +pub struct PORT__R(crate::FieldReader); +impl PORT__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PORT__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PORT__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PORT_` writer - PORT"] +pub struct PORT__W<'a> { + w: &'a mut W, +} +impl<'a> PORT__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `DSU_` reader - DSU"] +pub struct DSU__R(crate::FieldReader); +impl DSU__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DSU__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DSU__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DSU_` writer - DSU"] +pub struct DSU__W<'a> { + w: &'a mut W, +} +impl<'a> DSU__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `NVMCTRL_` reader - NVMCTRL"] +pub struct NVMCTRL__R(crate::FieldReader); +impl NVMCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NVMCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NVMCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NVMCTRL_` writer - NVMCTRL"] +pub struct NVMCTRL__W<'a> { + w: &'a mut W, +} +impl<'a> NVMCTRL__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `DMAC_` reader - DMAC"] +pub struct DMAC__R(crate::FieldReader); +impl DMAC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DMAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DMAC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DMAC_` writer - DMAC"] +pub struct DMAC__W<'a> { + w: &'a mut W, +} +impl<'a> DMAC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `MTB_` reader - MTB"] +pub struct MTB__R(crate::FieldReader); +impl MTB__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MTB__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MTB__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MTB_` writer - MTB"] +pub struct MTB__W<'a> { + w: &'a mut W, +} +impl<'a> MTB__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `HMATRIXHS_` reader - HMATRIXHS"] +pub struct HMATRIXHS__R(crate::FieldReader); +impl HMATRIXHS__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HMATRIXHS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HMATRIXHS__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HMATRIXHS_` writer - HMATRIXHS"] +pub struct HMATRIXHS__W<'a> { + w: &'a mut W, +} +impl<'a> HMATRIXHS__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - PORT"] + #[inline(always)] + pub fn port_(&self) -> PORT__R { + PORT__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - DSU"] + #[inline(always)] + pub fn dsu_(&self) -> DSU__R { + DSU__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - NVMCTRL"] + #[inline(always)] + pub fn nvmctrl_(&self) -> NVMCTRL__R { + NVMCTRL__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - DMAC"] + #[inline(always)] + pub fn dmac_(&self) -> DMAC__R { + DMAC__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - MTB"] + #[inline(always)] + pub fn mtb_(&self) -> MTB__R { + MTB__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - HMATRIXHS"] + #[inline(always)] + pub fn hmatrixhs_(&self) -> HMATRIXHS__R { + HMATRIXHS__R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - PORT"] + #[inline(always)] + pub fn port_(&mut self) -> PORT__W { + PORT__W { w: self } + } + #[doc = "Bit 1 - DSU"] + #[inline(always)] + pub fn dsu_(&mut self) -> DSU__W { + DSU__W { w: self } + } + #[doc = "Bit 2 - NVMCTRL"] + #[inline(always)] + pub fn nvmctrl_(&mut self) -> NVMCTRL__W { + NVMCTRL__W { w: self } + } + #[doc = "Bit 3 - DMAC"] + #[inline(always)] + pub fn dmac_(&mut self) -> DMAC__W { + DMAC__W { w: self } + } + #[doc = "Bit 4 - MTB"] + #[inline(always)] + pub fn mtb_(&mut self) -> MTB__W { + MTB__W { w: self } + } + #[doc = "Bit 5 - HMATRIXHS"] + #[inline(always)] + pub fn hmatrixhs_(&mut self) -> HMATRIXHS__W { + HMATRIXHS__W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Peripheral interrupt flag status - Bridge B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflagb](index.html) module"] +pub struct INTFLAGB_SPEC; +impl crate::RegisterSpec for INTFLAGB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflagb::R](R) reader structure"] +impl crate::Readable for INTFLAGB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflagb::W](W) writer structure"] +impl crate::Writable for INTFLAGB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAGB to value 0"] +impl crate::Resettable for INTFLAGB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/pac/intflagc.rs b/pac/atsamc21j/src/pac/intflagc.rs new file mode 100644 index 000000000000..80ee48da5eeb --- /dev/null +++ b/pac/atsamc21j/src/pac/intflagc.rs @@ -0,0 +1,1194 @@ +#[doc = "Register `INTFLAGC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAGC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVSYS_` reader - EVSYS"] +pub struct EVSYS__R(crate::FieldReader); +impl EVSYS__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVSYS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVSYS__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVSYS_` writer - EVSYS"] +pub struct EVSYS__W<'a> { + w: &'a mut W, +} +impl<'a> EVSYS__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `SERCOM0_` reader - SERCOM0"] +pub struct SERCOM0__R(crate::FieldReader); +impl SERCOM0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM0_` writer - SERCOM0"] +pub struct SERCOM0__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SERCOM1_` reader - SERCOM1"] +pub struct SERCOM1__R(crate::FieldReader); +impl SERCOM1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM1_` writer - SERCOM1"] +pub struct SERCOM1__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SERCOM2_` reader - SERCOM2"] +pub struct SERCOM2__R(crate::FieldReader); +impl SERCOM2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM2_` writer - SERCOM2"] +pub struct SERCOM2__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM2__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `SERCOM3_` reader - SERCOM3"] +pub struct SERCOM3__R(crate::FieldReader); +impl SERCOM3__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM3__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM3__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM3_` writer - SERCOM3"] +pub struct SERCOM3__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM3__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `SERCOM4_` reader - SERCOM4"] +pub struct SERCOM4__R(crate::FieldReader); +impl SERCOM4__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM4__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM4__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM4_` writer - SERCOM4"] +pub struct SERCOM4__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM4__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `SERCOM5_` reader - SERCOM5"] +pub struct SERCOM5__R(crate::FieldReader); +impl SERCOM5__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM5__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM5__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM5_` writer - SERCOM5"] +pub struct SERCOM5__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM5__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `CAN0_` reader - CAN0"] +pub struct CAN0__R(crate::FieldReader); +impl CAN0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CAN0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CAN0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAN0_` writer - CAN0"] +pub struct CAN0__W<'a> { + w: &'a mut W, +} +impl<'a> CAN0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CAN1_` reader - CAN1"] +pub struct CAN1__R(crate::FieldReader); +impl CAN1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CAN1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CAN1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAN1_` writer - CAN1"] +pub struct CAN1__W<'a> { + w: &'a mut W, +} +impl<'a> CAN1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `TCC0_` reader - TCC0"] +pub struct TCC0__R(crate::FieldReader); +impl TCC0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCC0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCC0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCC0_` writer - TCC0"] +pub struct TCC0__W<'a> { + w: &'a mut W, +} +impl<'a> TCC0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `TCC1_` reader - TCC1"] +pub struct TCC1__R(crate::FieldReader); +impl TCC1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCC1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCC1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCC1_` writer - TCC1"] +pub struct TCC1__W<'a> { + w: &'a mut W, +} +impl<'a> TCC1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `TCC2_` reader - TCC2"] +pub struct TCC2__R(crate::FieldReader); +impl TCC2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCC2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCC2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCC2_` writer - TCC2"] +pub struct TCC2__W<'a> { + w: &'a mut W, +} +impl<'a> TCC2__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `TC0_` reader - TC0"] +pub struct TC0__R(crate::FieldReader); +impl TC0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC0_` writer - TC0"] +pub struct TC0__W<'a> { + w: &'a mut W, +} +impl<'a> TC0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `TC1_` reader - TC1"] +pub struct TC1__R(crate::FieldReader); +impl TC1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC1_` writer - TC1"] +pub struct TC1__W<'a> { + w: &'a mut W, +} +impl<'a> TC1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `TC2_` reader - TC2"] +pub struct TC2__R(crate::FieldReader); +impl TC2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC2_` writer - TC2"] +pub struct TC2__W<'a> { + w: &'a mut W, +} +impl<'a> TC2__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `TC3_` reader - TC3"] +pub struct TC3__R(crate::FieldReader); +impl TC3__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC3__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC3__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC3_` writer - TC3"] +pub struct TC3__W<'a> { + w: &'a mut W, +} +impl<'a> TC3__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `TC4_` reader - TC4"] +pub struct TC4__R(crate::FieldReader); +impl TC4__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC4__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC4__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC4_` writer - TC4"] +pub struct TC4__W<'a> { + w: &'a mut W, +} +impl<'a> TC4__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `ADC0_` reader - ADC0"] +pub struct ADC0__R(crate::FieldReader); +impl ADC0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ADC0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADC0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADC0_` writer - ADC0"] +pub struct ADC0__W<'a> { + w: &'a mut W, +} +impl<'a> ADC0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `ADC1_` reader - ADC1"] +pub struct ADC1__R(crate::FieldReader); +impl ADC1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ADC1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADC1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADC1_` writer - ADC1"] +pub struct ADC1__W<'a> { + w: &'a mut W, +} +impl<'a> ADC1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `SDADC_` reader - SDADC"] +pub struct SDADC__R(crate::FieldReader); +impl SDADC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SDADC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SDADC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SDADC_` writer - SDADC"] +pub struct SDADC__W<'a> { + w: &'a mut W, +} +impl<'a> SDADC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `AC_` reader - AC"] +pub struct AC__R(crate::FieldReader); +impl AC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AC_` writer - AC"] +pub struct AC__W<'a> { + w: &'a mut W, +} +impl<'a> AC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `DAC_` reader - DAC"] +pub struct DAC__R(crate::FieldReader); +impl DAC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DAC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DAC_` writer - DAC"] +pub struct DAC__W<'a> { + w: &'a mut W, +} +impl<'a> DAC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `PTC_` reader - PTC"] +pub struct PTC__R(crate::FieldReader); +impl PTC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PTC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PTC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PTC_` writer - PTC"] +pub struct PTC__W<'a> { + w: &'a mut W, +} +impl<'a> PTC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `CCL_` reader - CCL"] +pub struct CCL__R(crate::FieldReader); +impl CCL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCL_` writer - CCL"] +pub struct CCL__W<'a> { + w: &'a mut W, +} +impl<'a> CCL__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +impl R { + #[doc = "Bit 0 - EVSYS"] + #[inline(always)] + pub fn evsys_(&self) -> EVSYS__R { + EVSYS__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM0"] + #[inline(always)] + pub fn sercom0_(&self) -> SERCOM0__R { + SERCOM0__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - SERCOM1"] + #[inline(always)] + pub fn sercom1_(&self) -> SERCOM1__R { + SERCOM1__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - SERCOM2"] + #[inline(always)] + pub fn sercom2_(&self) -> SERCOM2__R { + SERCOM2__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - SERCOM3"] + #[inline(always)] + pub fn sercom3_(&self) -> SERCOM3__R { + SERCOM3__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - SERCOM4"] + #[inline(always)] + pub fn sercom4_(&self) -> SERCOM4__R { + SERCOM4__R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - SERCOM5"] + #[inline(always)] + pub fn sercom5_(&self) -> SERCOM5__R { + SERCOM5__R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - CAN0"] + #[inline(always)] + pub fn can0_(&self) -> CAN0__R { + CAN0__R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - CAN1"] + #[inline(always)] + pub fn can1_(&self) -> CAN1__R { + CAN1__R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - TCC0"] + #[inline(always)] + pub fn tcc0_(&self) -> TCC0__R { + TCC0__R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - TCC1"] + #[inline(always)] + pub fn tcc1_(&self) -> TCC1__R { + TCC1__R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - TCC2"] + #[inline(always)] + pub fn tcc2_(&self) -> TCC2__R { + TCC2__R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - TC0"] + #[inline(always)] + pub fn tc0_(&self) -> TC0__R { + TC0__R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - TC1"] + #[inline(always)] + pub fn tc1_(&self) -> TC1__R { + TC1__R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - TC2"] + #[inline(always)] + pub fn tc2_(&self) -> TC2__R { + TC2__R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - TC3"] + #[inline(always)] + pub fn tc3_(&self) -> TC3__R { + TC3__R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - TC4"] + #[inline(always)] + pub fn tc4_(&self) -> TC4__R { + TC4__R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - ADC0"] + #[inline(always)] + pub fn adc0_(&self) -> ADC0__R { + ADC0__R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - ADC1"] + #[inline(always)] + pub fn adc1_(&self) -> ADC1__R { + ADC1__R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - SDADC"] + #[inline(always)] + pub fn sdadc_(&self) -> SDADC__R { + SDADC__R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - AC"] + #[inline(always)] + pub fn ac_(&self) -> AC__R { + AC__R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - DAC"] + #[inline(always)] + pub fn dac_(&self) -> DAC__R { + DAC__R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - PTC"] + #[inline(always)] + pub fn ptc_(&self) -> PTC__R { + PTC__R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - CCL"] + #[inline(always)] + pub fn ccl_(&self) -> CCL__R { + CCL__R::new(((self.bits >> 23) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - EVSYS"] + #[inline(always)] + pub fn evsys_(&mut self) -> EVSYS__W { + EVSYS__W { w: self } + } + #[doc = "Bit 1 - SERCOM0"] + #[inline(always)] + pub fn sercom0_(&mut self) -> SERCOM0__W { + SERCOM0__W { w: self } + } + #[doc = "Bit 2 - SERCOM1"] + #[inline(always)] + pub fn sercom1_(&mut self) -> SERCOM1__W { + SERCOM1__W { w: self } + } + #[doc = "Bit 3 - SERCOM2"] + #[inline(always)] + pub fn sercom2_(&mut self) -> SERCOM2__W { + SERCOM2__W { w: self } + } + #[doc = "Bit 4 - SERCOM3"] + #[inline(always)] + pub fn sercom3_(&mut self) -> SERCOM3__W { + SERCOM3__W { w: self } + } + #[doc = "Bit 5 - SERCOM4"] + #[inline(always)] + pub fn sercom4_(&mut self) -> SERCOM4__W { + SERCOM4__W { w: self } + } + #[doc = "Bit 6 - SERCOM5"] + #[inline(always)] + pub fn sercom5_(&mut self) -> SERCOM5__W { + SERCOM5__W { w: self } + } + #[doc = "Bit 7 - CAN0"] + #[inline(always)] + pub fn can0_(&mut self) -> CAN0__W { + CAN0__W { w: self } + } + #[doc = "Bit 8 - CAN1"] + #[inline(always)] + pub fn can1_(&mut self) -> CAN1__W { + CAN1__W { w: self } + } + #[doc = "Bit 9 - TCC0"] + #[inline(always)] + pub fn tcc0_(&mut self) -> TCC0__W { + TCC0__W { w: self } + } + #[doc = "Bit 10 - TCC1"] + #[inline(always)] + pub fn tcc1_(&mut self) -> TCC1__W { + TCC1__W { w: self } + } + #[doc = "Bit 11 - TCC2"] + #[inline(always)] + pub fn tcc2_(&mut self) -> TCC2__W { + TCC2__W { w: self } + } + #[doc = "Bit 12 - TC0"] + #[inline(always)] + pub fn tc0_(&mut self) -> TC0__W { + TC0__W { w: self } + } + #[doc = "Bit 13 - TC1"] + #[inline(always)] + pub fn tc1_(&mut self) -> TC1__W { + TC1__W { w: self } + } + #[doc = "Bit 14 - TC2"] + #[inline(always)] + pub fn tc2_(&mut self) -> TC2__W { + TC2__W { w: self } + } + #[doc = "Bit 15 - TC3"] + #[inline(always)] + pub fn tc3_(&mut self) -> TC3__W { + TC3__W { w: self } + } + #[doc = "Bit 16 - TC4"] + #[inline(always)] + pub fn tc4_(&mut self) -> TC4__W { + TC4__W { w: self } + } + #[doc = "Bit 17 - ADC0"] + #[inline(always)] + pub fn adc0_(&mut self) -> ADC0__W { + ADC0__W { w: self } + } + #[doc = "Bit 18 - ADC1"] + #[inline(always)] + pub fn adc1_(&mut self) -> ADC1__W { + ADC1__W { w: self } + } + #[doc = "Bit 19 - SDADC"] + #[inline(always)] + pub fn sdadc_(&mut self) -> SDADC__W { + SDADC__W { w: self } + } + #[doc = "Bit 20 - AC"] + #[inline(always)] + pub fn ac_(&mut self) -> AC__W { + AC__W { w: self } + } + #[doc = "Bit 21 - DAC"] + #[inline(always)] + pub fn dac_(&mut self) -> DAC__W { + DAC__W { w: self } + } + #[doc = "Bit 22 - PTC"] + #[inline(always)] + pub fn ptc_(&mut self) -> PTC__W { + PTC__W { w: self } + } + #[doc = "Bit 23 - CCL"] + #[inline(always)] + pub fn ccl_(&mut self) -> CCL__W { + CCL__W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Peripheral interrupt flag status - Bridge C\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflagc](index.html) module"] +pub struct INTFLAGC_SPEC; +impl crate::RegisterSpec for INTFLAGC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflagc::R](R) reader structure"] +impl crate::Readable for INTFLAGC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflagc::W](W) writer structure"] +impl crate::Writable for INTFLAGC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAGC to value 0"] +impl crate::Resettable for INTFLAGC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/pac/statusa.rs b/pac/atsamc21j/src/pac/statusa.rs new file mode 100644 index 000000000000..ca22aef2f1ce --- /dev/null +++ b/pac/atsamc21j/src/pac/statusa.rs @@ -0,0 +1,293 @@ +#[doc = "Register `STATUSA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PAC_` reader - PAC APB Protect Enable"] +pub struct PAC__R(crate::FieldReader); +impl PAC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PAC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PM_` reader - PM APB Protect Enable"] +pub struct PM__R(crate::FieldReader); +impl PM__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PM__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PM__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCLK_` reader - MCLK APB Protect Enable"] +pub struct MCLK__R(crate::FieldReader); +impl MCLK__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCLK__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCLK__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RSTC_` reader - RSTC APB Protect Enable"] +pub struct RSTC__R(crate::FieldReader); +impl RSTC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RSTC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RSTC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSCCTRL_` reader - OSCCTRL APB Protect Enable"] +pub struct OSCCTRL__R(crate::FieldReader); +impl OSCCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSCCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSCCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC32KCTRL_` reader - OSC32KCTRL APB Protect Enable"] +pub struct OSC32KCTRL__R(crate::FieldReader); +impl OSC32KCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC32KCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC32KCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SUPC_` reader - SUPC APB Protect Enable"] +pub struct SUPC__R(crate::FieldReader); +impl SUPC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SUPC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SUPC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GCLK_` reader - GCLK APB Protect Enable"] +pub struct GCLK__R(crate::FieldReader); +impl GCLK__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GCLK__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GCLK__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WDT_` reader - WDT APB Protect Enable"] +pub struct WDT__R(crate::FieldReader); +impl WDT__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WDT__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WDT__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RTC_` reader - RTC APB Protect Enable"] +pub struct RTC__R(crate::FieldReader); +impl RTC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RTC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RTC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EIC_` reader - EIC APB Protect Enable"] +pub struct EIC__R(crate::FieldReader); +impl EIC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EIC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EIC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FREQM_` reader - FREQM APB Protect Enable"] +pub struct FREQM__R(crate::FieldReader); +impl FREQM__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FREQM__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FREQM__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSENS_` reader - TSENS APB Protect Enable"] +pub struct TSENS__R(crate::FieldReader); +impl TSENS__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSENS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSENS__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - PAC APB Protect Enable"] + #[inline(always)] + pub fn pac_(&self) -> PAC__R { + PAC__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - PM APB Protect Enable"] + #[inline(always)] + pub fn pm_(&self) -> PM__R { + PM__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - MCLK APB Protect Enable"] + #[inline(always)] + pub fn mclk_(&self) -> MCLK__R { + MCLK__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - RSTC APB Protect Enable"] + #[inline(always)] + pub fn rstc_(&self) -> RSTC__R { + RSTC__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - OSCCTRL APB Protect Enable"] + #[inline(always)] + pub fn oscctrl_(&self) -> OSCCTRL__R { + OSCCTRL__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - OSC32KCTRL APB Protect Enable"] + #[inline(always)] + pub fn osc32kctrl_(&self) -> OSC32KCTRL__R { + OSC32KCTRL__R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - SUPC APB Protect Enable"] + #[inline(always)] + pub fn supc_(&self) -> SUPC__R { + SUPC__R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - GCLK APB Protect Enable"] + #[inline(always)] + pub fn gclk_(&self) -> GCLK__R { + GCLK__R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - WDT APB Protect Enable"] + #[inline(always)] + pub fn wdt_(&self) -> WDT__R { + WDT__R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - RTC APB Protect Enable"] + #[inline(always)] + pub fn rtc_(&self) -> RTC__R { + RTC__R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - EIC APB Protect Enable"] + #[inline(always)] + pub fn eic_(&self) -> EIC__R { + EIC__R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - FREQM APB Protect Enable"] + #[inline(always)] + pub fn freqm_(&self) -> FREQM__R { + FREQM__R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - TSENS APB Protect Enable"] + #[inline(always)] + pub fn tsens_(&self) -> TSENS__R { + TSENS__R::new(((self.bits >> 12) & 0x01) != 0) + } +} +#[doc = "Peripheral write protection status - Bridge A\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [statusa](index.html) module"] +pub struct STATUSA_SPEC; +impl crate::RegisterSpec for STATUSA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [statusa::R](R) reader structure"] +impl crate::Readable for STATUSA_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUSA to value 0"] +impl crate::Resettable for STATUSA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/pac/statusb.rs b/pac/atsamc21j/src/pac/statusb.rs new file mode 100644 index 000000000000..a022cc2f1d54 --- /dev/null +++ b/pac/atsamc21j/src/pac/statusb.rs @@ -0,0 +1,153 @@ +#[doc = "Register `STATUSB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PORT_` reader - PORT APB Protect Enable"] +pub struct PORT__R(crate::FieldReader); +impl PORT__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PORT__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PORT__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DSU_` reader - DSU APB Protect Enable"] +pub struct DSU__R(crate::FieldReader); +impl DSU__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DSU__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DSU__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NVMCTRL_` reader - NVMCTRL APB Protect Enable"] +pub struct NVMCTRL__R(crate::FieldReader); +impl NVMCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NVMCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NVMCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DMAC_` reader - DMAC APB Protect Enable"] +pub struct DMAC__R(crate::FieldReader); +impl DMAC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DMAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DMAC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MTB_` reader - MTB APB Protect Enable"] +pub struct MTB__R(crate::FieldReader); +impl MTB__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MTB__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MTB__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HMATRIXHS_` reader - HMATRIXHS APB Protect Enable"] +pub struct HMATRIXHS__R(crate::FieldReader); +impl HMATRIXHS__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HMATRIXHS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HMATRIXHS__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - PORT APB Protect Enable"] + #[inline(always)] + pub fn port_(&self) -> PORT__R { + PORT__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - DSU APB Protect Enable"] + #[inline(always)] + pub fn dsu_(&self) -> DSU__R { + DSU__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - NVMCTRL APB Protect Enable"] + #[inline(always)] + pub fn nvmctrl_(&self) -> NVMCTRL__R { + NVMCTRL__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - DMAC APB Protect Enable"] + #[inline(always)] + pub fn dmac_(&self) -> DMAC__R { + DMAC__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - MTB APB Protect Enable"] + #[inline(always)] + pub fn mtb_(&self) -> MTB__R { + MTB__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - HMATRIXHS APB Protect Enable"] + #[inline(always)] + pub fn hmatrixhs_(&self) -> HMATRIXHS__R { + HMATRIXHS__R::new(((self.bits >> 5) & 0x01) != 0) + } +} +#[doc = "Peripheral write protection status - Bridge B\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [statusb](index.html) module"] +pub struct STATUSB_SPEC; +impl crate::RegisterSpec for STATUSB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [statusb::R](R) reader structure"] +impl crate::Readable for STATUSB_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUSB to value 0x02"] +impl crate::Resettable for STATUSB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x02 + } +} diff --git a/pac/atsamc21j/src/pac/statusc.rs b/pac/atsamc21j/src/pac/statusc.rs new file mode 100644 index 000000000000..8c986ef451bb --- /dev/null +++ b/pac/atsamc21j/src/pac/statusc.rs @@ -0,0 +1,513 @@ +#[doc = "Register `STATUSC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `EVSYS_` reader - EVSYS APB Protect Enable"] +pub struct EVSYS__R(crate::FieldReader); +impl EVSYS__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVSYS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVSYS__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM0_` reader - SERCOM0 APB Protect Enable"] +pub struct SERCOM0__R(crate::FieldReader); +impl SERCOM0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM1_` reader - SERCOM1 APB Protect Enable"] +pub struct SERCOM1__R(crate::FieldReader); +impl SERCOM1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM2_` reader - SERCOM2 APB Protect Enable"] +pub struct SERCOM2__R(crate::FieldReader); +impl SERCOM2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM3_` reader - SERCOM3 APB Protect Enable"] +pub struct SERCOM3__R(crate::FieldReader); +impl SERCOM3__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM3__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM3__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM4_` reader - SERCOM4 APB Protect Enable"] +pub struct SERCOM4__R(crate::FieldReader); +impl SERCOM4__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM4__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM4__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM5_` reader - SERCOM5 APB Protect Enable"] +pub struct SERCOM5__R(crate::FieldReader); +impl SERCOM5__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM5__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM5__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAN0_` reader - CAN0 APB Protect Enable"] +pub struct CAN0__R(crate::FieldReader); +impl CAN0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CAN0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CAN0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAN1_` reader - CAN1 APB Protect Enable"] +pub struct CAN1__R(crate::FieldReader); +impl CAN1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CAN1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CAN1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCC0_` reader - TCC0 APB Protect Enable"] +pub struct TCC0__R(crate::FieldReader); +impl TCC0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCC0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCC0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCC1_` reader - TCC1 APB Protect Enable"] +pub struct TCC1__R(crate::FieldReader); +impl TCC1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCC1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCC1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCC2_` reader - TCC2 APB Protect Enable"] +pub struct TCC2__R(crate::FieldReader); +impl TCC2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCC2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCC2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC0_` reader - TC0 APB Protect Enable"] +pub struct TC0__R(crate::FieldReader); +impl TC0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC1_` reader - TC1 APB Protect Enable"] +pub struct TC1__R(crate::FieldReader); +impl TC1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC2_` reader - TC2 APB Protect Enable"] +pub struct TC2__R(crate::FieldReader); +impl TC2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC3_` reader - TC3 APB Protect Enable"] +pub struct TC3__R(crate::FieldReader); +impl TC3__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC3__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC3__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC4_` reader - TC4 APB Protect Enable"] +pub struct TC4__R(crate::FieldReader); +impl TC4__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC4__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC4__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADC0_` reader - ADC0 APB Protect Enable"] +pub struct ADC0__R(crate::FieldReader); +impl ADC0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ADC0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADC0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADC1_` reader - ADC1 APB Protect Enable"] +pub struct ADC1__R(crate::FieldReader); +impl ADC1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ADC1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADC1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SDADC_` reader - SDADC APB Protect Enable"] +pub struct SDADC__R(crate::FieldReader); +impl SDADC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SDADC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SDADC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AC_` reader - AC APB Protect Enable"] +pub struct AC__R(crate::FieldReader); +impl AC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DAC_` reader - DAC APB Protect Enable"] +pub struct DAC__R(crate::FieldReader); +impl DAC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DAC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PTC_` reader - PTC APB Protect Enable"] +pub struct PTC__R(crate::FieldReader); +impl PTC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PTC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PTC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCL_` reader - CCL APB Protect Enable"] +pub struct CCL__R(crate::FieldReader); +impl CCL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - EVSYS APB Protect Enable"] + #[inline(always)] + pub fn evsys_(&self) -> EVSYS__R { + EVSYS__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM0 APB Protect Enable"] + #[inline(always)] + pub fn sercom0_(&self) -> SERCOM0__R { + SERCOM0__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - SERCOM1 APB Protect Enable"] + #[inline(always)] + pub fn sercom1_(&self) -> SERCOM1__R { + SERCOM1__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - SERCOM2 APB Protect Enable"] + #[inline(always)] + pub fn sercom2_(&self) -> SERCOM2__R { + SERCOM2__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - SERCOM3 APB Protect Enable"] + #[inline(always)] + pub fn sercom3_(&self) -> SERCOM3__R { + SERCOM3__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - SERCOM4 APB Protect Enable"] + #[inline(always)] + pub fn sercom4_(&self) -> SERCOM4__R { + SERCOM4__R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - SERCOM5 APB Protect Enable"] + #[inline(always)] + pub fn sercom5_(&self) -> SERCOM5__R { + SERCOM5__R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - CAN0 APB Protect Enable"] + #[inline(always)] + pub fn can0_(&self) -> CAN0__R { + CAN0__R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - CAN1 APB Protect Enable"] + #[inline(always)] + pub fn can1_(&self) -> CAN1__R { + CAN1__R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - TCC0 APB Protect Enable"] + #[inline(always)] + pub fn tcc0_(&self) -> TCC0__R { + TCC0__R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - TCC1 APB Protect Enable"] + #[inline(always)] + pub fn tcc1_(&self) -> TCC1__R { + TCC1__R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - TCC2 APB Protect Enable"] + #[inline(always)] + pub fn tcc2_(&self) -> TCC2__R { + TCC2__R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - TC0 APB Protect Enable"] + #[inline(always)] + pub fn tc0_(&self) -> TC0__R { + TC0__R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - TC1 APB Protect Enable"] + #[inline(always)] + pub fn tc1_(&self) -> TC1__R { + TC1__R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - TC2 APB Protect Enable"] + #[inline(always)] + pub fn tc2_(&self) -> TC2__R { + TC2__R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - TC3 APB Protect Enable"] + #[inline(always)] + pub fn tc3_(&self) -> TC3__R { + TC3__R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - TC4 APB Protect Enable"] + #[inline(always)] + pub fn tc4_(&self) -> TC4__R { + TC4__R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - ADC0 APB Protect Enable"] + #[inline(always)] + pub fn adc0_(&self) -> ADC0__R { + ADC0__R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - ADC1 APB Protect Enable"] + #[inline(always)] + pub fn adc1_(&self) -> ADC1__R { + ADC1__R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - SDADC APB Protect Enable"] + #[inline(always)] + pub fn sdadc_(&self) -> SDADC__R { + SDADC__R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - AC APB Protect Enable"] + #[inline(always)] + pub fn ac_(&self) -> AC__R { + AC__R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - DAC APB Protect Enable"] + #[inline(always)] + pub fn dac_(&self) -> DAC__R { + DAC__R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - PTC APB Protect Enable"] + #[inline(always)] + pub fn ptc_(&self) -> PTC__R { + PTC__R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - CCL APB Protect Enable"] + #[inline(always)] + pub fn ccl_(&self) -> CCL__R { + CCL__R::new(((self.bits >> 23) & 0x01) != 0) + } +} +#[doc = "Peripheral write protection status - Bridge C\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [statusc](index.html) module"] +pub struct STATUSC_SPEC; +impl crate::RegisterSpec for STATUSC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [statusc::R](R) reader structure"] +impl crate::Readable for STATUSC_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUSC to value 0x0200_0000"] +impl crate::Resettable for STATUSC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0200_0000 + } +} diff --git a/pac/atsamc21j/src/pac/wrctrl.rs b/pac/atsamc21j/src/pac/wrctrl.rs new file mode 100644 index 000000000000..65773ea08d64 --- /dev/null +++ b/pac/atsamc21j/src/pac/wrctrl.rs @@ -0,0 +1,215 @@ +#[doc = "Register `WRCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WRCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PERID` reader - Peripheral identifier"] +pub struct PERID_R(crate::FieldReader); +impl PERID_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + PERID_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERID_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERID` writer - Peripheral identifier"] +pub struct PERID_W<'a> { + w: &'a mut W, +} +impl<'a> PERID_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +#[doc = "Peripheral access control key\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum KEY_A { + #[doc = "0: No action"] + OFF = 0, + #[doc = "1: Clear protection"] + CLR = 1, + #[doc = "2: Set protection"] + SET = 2, + #[doc = "3: Set and lock protection"] + SETLCK = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: KEY_A) -> Self { + variant as _ + } +} +#[doc = "Field `KEY` reader - Peripheral access control key"] +pub struct KEY_R(crate::FieldReader); +impl KEY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + KEY_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(KEY_A::OFF), + 1 => Some(KEY_A::CLR), + 2 => Some(KEY_A::SET), + 3 => Some(KEY_A::SETLCK), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == KEY_A::OFF + } + #[doc = "Checks if the value of the field is `CLR`"] + #[inline(always)] + pub fn is_clr(&self) -> bool { + **self == KEY_A::CLR + } + #[doc = "Checks if the value of the field is `SET`"] + #[inline(always)] + pub fn is_set(&self) -> bool { + **self == KEY_A::SET + } + #[doc = "Checks if the value of the field is `SETLCK`"] + #[inline(always)] + pub fn is_setlck(&self) -> bool { + **self == KEY_A::SETLCK + } +} +impl core::ops::Deref for KEY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `KEY` writer - Peripheral access control key"] +pub struct KEY_W<'a> { + w: &'a mut W, +} +impl<'a> KEY_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: KEY_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(KEY_A::OFF) + } + #[doc = "Clear protection"] + #[inline(always)] + pub fn clr(self) -> &'a mut W { + self.variant(KEY_A::CLR) + } + #[doc = "Set protection"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(KEY_A::SET) + } + #[doc = "Set and lock protection"] + #[inline(always)] + pub fn setlck(self) -> &'a mut W { + self.variant(KEY_A::SETLCK) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Peripheral identifier"] + #[inline(always)] + pub fn perid(&self) -> PERID_R { + PERID_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:23 - Peripheral access control key"] + #[inline(always)] + pub fn key(&self) -> KEY_R { + KEY_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:15 - Peripheral identifier"] + #[inline(always)] + pub fn perid(&mut self) -> PERID_W { + PERID_W { w: self } + } + #[doc = "Bits 16:23 - Peripheral access control key"] + #[inline(always)] + pub fn key(&mut self) -> KEY_W { + KEY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Write control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wrctrl](index.html) module"] +pub struct WRCTRL_SPEC; +impl crate::RegisterSpec for WRCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [wrctrl::R](R) reader structure"] +impl crate::Readable for WRCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wrctrl::W](W) writer structure"] +impl crate::Writable for WRCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WRCTRL to value 0"] +impl crate::Resettable for WRCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/pm.rs b/pac/atsamc21j/src/pm.rs new file mode 100644 index 000000000000..9da2b0e13288 --- /dev/null +++ b/pac/atsamc21j/src/pm.rs @@ -0,0 +1,18 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved0: [u8; 0x01], + #[doc = "0x01 - Sleep Configuration"] + pub sleepcfg: crate::Reg, + _reserved1: [u8; 0x06], + #[doc = "0x08 - Standby Configuration"] + pub stdbycfg: crate::Reg, +} +#[doc = "SLEEPCFG register accessor: an alias for `Reg`"] +pub type SLEEPCFG = crate::Reg; +#[doc = "Sleep Configuration"] +pub mod sleepcfg; +#[doc = "STDBYCFG register accessor: an alias for `Reg`"] +pub type STDBYCFG = crate::Reg; +#[doc = "Standby Configuration"] +pub mod stdbycfg; diff --git a/pac/atsamc21j/src/pm/sleepcfg.rs b/pac/atsamc21j/src/pm/sleepcfg.rs new file mode 100644 index 000000000000..ef643311a059 --- /dev/null +++ b/pac/atsamc21j/src/pm/sleepcfg.rs @@ -0,0 +1,178 @@ +#[doc = "Register `SLEEPCFG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SLEEPCFG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Sleep Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SLEEPMODE_A { + #[doc = "0: CPU clock is OFF"] + IDLE0 = 0, + #[doc = "1: AHB clock is OFF"] + IDLE1 = 1, + #[doc = "2: APB clock are OFF"] + IDLE2 = 2, + #[doc = "4: All Clocks are OFF"] + STANDBY = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SLEEPMODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `SLEEPMODE` reader - Sleep Mode"] +pub struct SLEEPMODE_R(crate::FieldReader); +impl SLEEPMODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SLEEPMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SLEEPMODE_A::IDLE0), + 1 => Some(SLEEPMODE_A::IDLE1), + 2 => Some(SLEEPMODE_A::IDLE2), + 4 => Some(SLEEPMODE_A::STANDBY), + _ => None, + } + } + #[doc = "Checks if the value of the field is `IDLE0`"] + #[inline(always)] + pub fn is_idle0(&self) -> bool { + **self == SLEEPMODE_A::IDLE0 + } + #[doc = "Checks if the value of the field is `IDLE1`"] + #[inline(always)] + pub fn is_idle1(&self) -> bool { + **self == SLEEPMODE_A::IDLE1 + } + #[doc = "Checks if the value of the field is `IDLE2`"] + #[inline(always)] + pub fn is_idle2(&self) -> bool { + **self == SLEEPMODE_A::IDLE2 + } + #[doc = "Checks if the value of the field is `STANDBY`"] + #[inline(always)] + pub fn is_standby(&self) -> bool { + **self == SLEEPMODE_A::STANDBY + } +} +impl core::ops::Deref for SLEEPMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLEEPMODE` writer - Sleep Mode"] +pub struct SLEEPMODE_W<'a> { + w: &'a mut W, +} +impl<'a> SLEEPMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SLEEPMODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "CPU clock is OFF"] + #[inline(always)] + pub fn idle0(self) -> &'a mut W { + self.variant(SLEEPMODE_A::IDLE0) + } + #[doc = "AHB clock is OFF"] + #[inline(always)] + pub fn idle1(self) -> &'a mut W { + self.variant(SLEEPMODE_A::IDLE1) + } + #[doc = "APB clock are OFF"] + #[inline(always)] + pub fn idle2(self) -> &'a mut W { + self.variant(SLEEPMODE_A::IDLE2) + } + #[doc = "All Clocks are OFF"] + #[inline(always)] + pub fn standby(self) -> &'a mut W { + self.variant(SLEEPMODE_A::STANDBY) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Sleep Mode"] + #[inline(always)] + pub fn sleepmode(&self) -> SLEEPMODE_R { + SLEEPMODE_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Sleep Mode"] + #[inline(always)] + pub fn sleepmode(&mut self) -> SLEEPMODE_W { + SLEEPMODE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Sleep Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sleepcfg](index.html) module"] +pub struct SLEEPCFG_SPEC; +impl crate::RegisterSpec for SLEEPCFG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [sleepcfg::R](R) reader structure"] +impl crate::Readable for SLEEPCFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [sleepcfg::W](W) writer structure"] +impl crate::Writable for SLEEPCFG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SLEEPCFG to value 0"] +impl crate::Resettable for SLEEPCFG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/pm/stdbycfg.rs b/pac/atsamc21j/src/pm/stdbycfg.rs new file mode 100644 index 000000000000..9780f2b001f5 --- /dev/null +++ b/pac/atsamc21j/src/pm/stdbycfg.rs @@ -0,0 +1,212 @@ +#[doc = "Register `STDBYCFG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STDBYCFG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Voltage Regulator Standby mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum VREGSMOD_A { + #[doc = "0: Automatic mode"] + AUTO = 0, + #[doc = "1: Performance oriented"] + PERFORMANCE = 1, + #[doc = "2: Low Power oriented"] + LP = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: VREGSMOD_A) -> Self { + variant as _ + } +} +#[doc = "Field `VREGSMOD` reader - Voltage Regulator Standby mode"] +pub struct VREGSMOD_R(crate::FieldReader); +impl VREGSMOD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + VREGSMOD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(VREGSMOD_A::AUTO), + 1 => Some(VREGSMOD_A::PERFORMANCE), + 2 => Some(VREGSMOD_A::LP), + _ => None, + } + } + #[doc = "Checks if the value of the field is `AUTO`"] + #[inline(always)] + pub fn is_auto(&self) -> bool { + **self == VREGSMOD_A::AUTO + } + #[doc = "Checks if the value of the field is `PERFORMANCE`"] + #[inline(always)] + pub fn is_performance(&self) -> bool { + **self == VREGSMOD_A::PERFORMANCE + } + #[doc = "Checks if the value of the field is `LP`"] + #[inline(always)] + pub fn is_lp(&self) -> bool { + **self == VREGSMOD_A::LP + } +} +impl core::ops::Deref for VREGSMOD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VREGSMOD` writer - Voltage Regulator Standby mode"] +pub struct VREGSMOD_W<'a> { + w: &'a mut W, +} +impl<'a> VREGSMOD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: VREGSMOD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Automatic mode"] + #[inline(always)] + pub fn auto(self) -> &'a mut W { + self.variant(VREGSMOD_A::AUTO) + } + #[doc = "Performance oriented"] + #[inline(always)] + pub fn performance(self) -> &'a mut W { + self.variant(VREGSMOD_A::PERFORMANCE) + } + #[doc = "Low Power oriented"] + #[inline(always)] + pub fn lp(self) -> &'a mut W { + self.variant(VREGSMOD_A::LP) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 6)) | ((value as u16 & 0x03) << 6); + self.w + } +} +#[doc = "Field `BBIASHS` reader - Back Bias for HMCRAMCHS"] +pub struct BBIASHS_R(crate::FieldReader); +impl BBIASHS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BBIASHS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BBIASHS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BBIASHS` writer - Back Bias for HMCRAMCHS"] +pub struct BBIASHS_W<'a> { + w: &'a mut W, +} +impl<'a> BBIASHS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u16 & 0x01) << 10); + self.w + } +} +impl R { + #[doc = "Bits 6:7 - Voltage Regulator Standby mode"] + #[inline(always)] + pub fn vregsmod(&self) -> VREGSMOD_R { + VREGSMOD_R::new(((self.bits >> 6) & 0x03) as u8) + } + #[doc = "Bit 10 - Back Bias for HMCRAMCHS"] + #[inline(always)] + pub fn bbiashs(&self) -> BBIASHS_R { + BBIASHS_R::new(((self.bits >> 10) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 6:7 - Voltage Regulator Standby mode"] + #[inline(always)] + pub fn vregsmod(&mut self) -> VREGSMOD_W { + VREGSMOD_W { w: self } + } + #[doc = "Bit 10 - Back Bias for HMCRAMCHS"] + #[inline(always)] + pub fn bbiashs(&mut self) -> BBIASHS_W { + BBIASHS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Standby Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [stdbycfg](index.html) module"] +pub struct STDBYCFG_SPEC; +impl crate::RegisterSpec for STDBYCFG_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [stdbycfg::R](R) reader structure"] +impl crate::Readable for STDBYCFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [stdbycfg::W](W) writer structure"] +impl crate::Writable for STDBYCFG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STDBYCFG to value 0x0400"] +impl crate::Resettable for STDBYCFG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0400 + } +} diff --git a/pac/atsamc21j/src/port.rs b/pac/atsamc21j/src/port.rs new file mode 100644 index 000000000000..08c16491ba07 --- /dev/null +++ b/pac/atsamc21j/src/port.rs @@ -0,0 +1,44 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00..0x60 - GROUP\\[%s\\]"] + pub group0: GROUP, + _reserved1: [u8; 0x20], + #[doc = "0x80..0xe0 - GROUP\\[%s\\]"] + pub group1: GROUP, +} +#[doc = r"Register block"] +#[repr(C)] +pub struct GROUP { + #[doc = "0x00 - Data Direction"] + pub dir: crate::Reg, + #[doc = "0x04 - Data Direction Clear"] + pub dirclr: crate::Reg, + #[doc = "0x08 - Data Direction Set"] + pub dirset: crate::Reg, + #[doc = "0x0c - Data Direction Toggle"] + pub dirtgl: crate::Reg, + #[doc = "0x10 - Data Output Value"] + pub out: crate::Reg, + #[doc = "0x14 - Data Output Value Clear"] + pub outclr: crate::Reg, + #[doc = "0x18 - Data Output Value Set"] + pub outset: crate::Reg, + #[doc = "0x1c - Data Output Value Toggle"] + pub outtgl: crate::Reg, + #[doc = "0x20 - Data Input Value"] + pub in_: crate::Reg, + #[doc = "0x24 - Control"] + pub ctrl: crate::Reg, + #[doc = "0x28 - Write Configuration"] + pub wrconfig: crate::Reg, + #[doc = "0x2c - Event Input Control"] + pub evctrl: crate::Reg, + #[doc = "0x30..0x40 - Peripheral Multiplexing n"] + pub pmux: [crate::Reg; 16], + #[doc = "0x40..0x60 - Pin Configuration n"] + pub pincfg: [crate::Reg; 32], +} +#[doc = r"Register block"] +#[doc = "GROUP\\[%s\\]"] +pub mod group; diff --git a/pac/atsamc21j/src/port/group.rs b/pac/atsamc21j/src/port/group.rs new file mode 100644 index 000000000000..d1aabcd73380 --- /dev/null +++ b/pac/atsamc21j/src/port/group.rs @@ -0,0 +1,56 @@ +#[doc = "DIR register accessor: an alias for `Reg`"] +pub type DIR = crate::Reg; +#[doc = "Data Direction"] +pub mod dir; +#[doc = "DIRCLR register accessor: an alias for `Reg`"] +pub type DIRCLR = crate::Reg; +#[doc = "Data Direction Clear"] +pub mod dirclr; +#[doc = "DIRSET register accessor: an alias for `Reg`"] +pub type DIRSET = crate::Reg; +#[doc = "Data Direction Set"] +pub mod dirset; +#[doc = "DIRTGL register accessor: an alias for `Reg`"] +pub type DIRTGL = crate::Reg; +#[doc = "Data Direction Toggle"] +pub mod dirtgl; +#[doc = "OUT register accessor: an alias for `Reg`"] +pub type OUT = crate::Reg; +#[doc = "Data Output Value"] +pub mod out; +#[doc = "OUTCLR register accessor: an alias for `Reg`"] +pub type OUTCLR = crate::Reg; +#[doc = "Data Output Value Clear"] +pub mod outclr; +#[doc = "OUTSET register accessor: an alias for `Reg`"] +pub type OUTSET = crate::Reg; +#[doc = "Data Output Value Set"] +pub mod outset; +#[doc = "OUTTGL register accessor: an alias for `Reg`"] +pub type OUTTGL = crate::Reg; +#[doc = "Data Output Value Toggle"] +pub mod outtgl; +#[doc = "IN register accessor: an alias for `Reg`"] +pub type IN = crate::Reg; +#[doc = "Data Input Value"] +pub mod in_; +#[doc = "CTRL register accessor: an alias for `Reg`"] +pub type CTRL = crate::Reg; +#[doc = "Control"] +pub mod ctrl; +#[doc = "WRCONFIG register accessor: an alias for `Reg`"] +pub type WRCONFIG = crate::Reg; +#[doc = "Write Configuration"] +pub mod wrconfig; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Input Control"] +pub mod evctrl; +#[doc = "PMUX register accessor: an alias for `Reg`"] +pub type PMUX = crate::Reg; +#[doc = "Peripheral Multiplexing n"] +pub mod pmux; +#[doc = "PINCFG register accessor: an alias for `Reg`"] +pub type PINCFG = crate::Reg; +#[doc = "Pin Configuration n"] +pub mod pincfg; diff --git a/pac/atsamc21j/src/port/group/ctrl.rs b/pac/atsamc21j/src/port/group/ctrl.rs new file mode 100644 index 000000000000..4b57cd6fcd2b --- /dev/null +++ b/pac/atsamc21j/src/port/group/ctrl.rs @@ -0,0 +1,103 @@ +#[doc = "Register `CTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SAMPLING` reader - Input Sampling Mode"] +pub struct SAMPLING_R(crate::FieldReader); +impl SAMPLING_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + SAMPLING_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SAMPLING_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SAMPLING` writer - Input Sampling Mode"] +pub struct SAMPLING_W<'a> { + w: &'a mut W, +} +impl<'a> SAMPLING_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Input Sampling Mode"] + #[inline(always)] + pub fn sampling(&self) -> SAMPLING_R { + SAMPLING_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Input Sampling Mode"] + #[inline(always)] + pub fn sampling(&mut self) -> SAMPLING_W { + SAMPLING_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"] +pub struct CTRL_SPEC; +impl crate::RegisterSpec for CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrl::R](R) reader structure"] +impl crate::Readable for CTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"] +impl crate::Writable for CTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/port/group/dir.rs b/pac/atsamc21j/src/port/group/dir.rs new file mode 100644 index 000000000000..e04452fb5d35 --- /dev/null +++ b/pac/atsamc21j/src/port/group/dir.rs @@ -0,0 +1,64 @@ +#[doc = "Register `DIR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Direction\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dir](index.html) module"] +pub struct DIR_SPEC; +impl crate::RegisterSpec for DIR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dir::R](R) reader structure"] +impl crate::Readable for DIR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dir::W](W) writer structure"] +impl crate::Writable for DIR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DIR to value 0"] +impl crate::Resettable for DIR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/port/group/dirclr.rs b/pac/atsamc21j/src/port/group/dirclr.rs new file mode 100644 index 000000000000..5e6d73d032b2 --- /dev/null +++ b/pac/atsamc21j/src/port/group/dirclr.rs @@ -0,0 +1,64 @@ +#[doc = "Register `DIRCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIRCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Direction Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dirclr](index.html) module"] +pub struct DIRCLR_SPEC; +impl crate::RegisterSpec for DIRCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dirclr::R](R) reader structure"] +impl crate::Readable for DIRCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dirclr::W](W) writer structure"] +impl crate::Writable for DIRCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DIRCLR to value 0"] +impl crate::Resettable for DIRCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/port/group/dirset.rs b/pac/atsamc21j/src/port/group/dirset.rs new file mode 100644 index 000000000000..eaa86e14f15d --- /dev/null +++ b/pac/atsamc21j/src/port/group/dirset.rs @@ -0,0 +1,64 @@ +#[doc = "Register `DIRSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIRSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Direction Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dirset](index.html) module"] +pub struct DIRSET_SPEC; +impl crate::RegisterSpec for DIRSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dirset::R](R) reader structure"] +impl crate::Readable for DIRSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dirset::W](W) writer structure"] +impl crate::Writable for DIRSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DIRSET to value 0"] +impl crate::Resettable for DIRSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/port/group/dirtgl.rs b/pac/atsamc21j/src/port/group/dirtgl.rs new file mode 100644 index 000000000000..fbd021438b1b --- /dev/null +++ b/pac/atsamc21j/src/port/group/dirtgl.rs @@ -0,0 +1,64 @@ +#[doc = "Register `DIRTGL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIRTGL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Direction Toggle\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dirtgl](index.html) module"] +pub struct DIRTGL_SPEC; +impl crate::RegisterSpec for DIRTGL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dirtgl::R](R) reader structure"] +impl crate::Readable for DIRTGL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dirtgl::W](W) writer structure"] +impl crate::Writable for DIRTGL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DIRTGL to value 0"] +impl crate::Resettable for DIRTGL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/port/group/evctrl.rs b/pac/atsamc21j/src/port/group/evctrl.rs new file mode 100644 index 000000000000..ef0a35987f3d --- /dev/null +++ b/pac/atsamc21j/src/port/group/evctrl.rs @@ -0,0 +1,625 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PID0` reader - Port Event Pin Identifier 0"] +pub struct PID0_R(crate::FieldReader); +impl PID0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PID0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PID0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PID0` writer - Port Event Pin Identifier 0"] +pub struct PID0_W<'a> { + w: &'a mut W, +} +impl<'a> PID0_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f); + self.w + } +} +#[doc = "Port Event Action 0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EVACT0_A { + #[doc = "0: Event output to pin"] + OUT = 0, + #[doc = "1: Set output register of pin on event"] + SET = 1, + #[doc = "2: Clear output register of pin on event"] + CLR = 2, + #[doc = "3: Toggle output register of pin on event"] + TGL = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EVACT0_A) -> Self { + variant as _ + } +} +#[doc = "Field `EVACT0` reader - Port Event Action 0"] +pub struct EVACT0_R(crate::FieldReader); +impl EVACT0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVACT0_A { + match self.bits { + 0 => EVACT0_A::OUT, + 1 => EVACT0_A::SET, + 2 => EVACT0_A::CLR, + 3 => EVACT0_A::TGL, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `OUT`"] + #[inline(always)] + pub fn is_out(&self) -> bool { + **self == EVACT0_A::OUT + } + #[doc = "Checks if the value of the field is `SET`"] + #[inline(always)] + pub fn is_set(&self) -> bool { + **self == EVACT0_A::SET + } + #[doc = "Checks if the value of the field is `CLR`"] + #[inline(always)] + pub fn is_clr(&self) -> bool { + **self == EVACT0_A::CLR + } + #[doc = "Checks if the value of the field is `TGL`"] + #[inline(always)] + pub fn is_tgl(&self) -> bool { + **self == EVACT0_A::TGL + } +} +impl core::ops::Deref for EVACT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT0` writer - Port Event Action 0"] +pub struct EVACT0_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT0_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EVACT0_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Event output to pin"] + #[inline(always)] + pub fn out(self) -> &'a mut W { + self.variant(EVACT0_A::OUT) + } + #[doc = "Set output register of pin on event"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(EVACT0_A::SET) + } + #[doc = "Clear output register of pin on event"] + #[inline(always)] + pub fn clr(self) -> &'a mut W { + self.variant(EVACT0_A::CLR) + } + #[doc = "Toggle output register of pin on event"] + #[inline(always)] + pub fn tgl(self) -> &'a mut W { + self.variant(EVACT0_A::TGL) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 5)) | ((value as u32 & 0x03) << 5); + self.w + } +} +#[doc = "Field `PORTEI0` reader - Port Event Enable Input 0"] +pub struct PORTEI0_R(crate::FieldReader); +impl PORTEI0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PORTEI0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PORTEI0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PORTEI0` writer - Port Event Enable Input 0"] +pub struct PORTEI0_W<'a> { + w: &'a mut W, +} +impl<'a> PORTEI0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `PID1` reader - Port Event Pin Identifier 1"] +pub struct PID1_R(crate::FieldReader); +impl PID1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PID1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PID1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PID1` writer - Port Event Pin Identifier 1"] +pub struct PID1_W<'a> { + w: &'a mut W, +} +impl<'a> PID1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 8)) | ((value as u32 & 0x1f) << 8); + self.w + } +} +#[doc = "Field `EVACT1` reader - Port Event Action 1"] +pub struct EVACT1_R(crate::FieldReader); +impl EVACT1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVACT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT1` writer - Port Event Action 1"] +pub struct EVACT1_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 13)) | ((value as u32 & 0x03) << 13); + self.w + } +} +#[doc = "Field `PORTEI1` reader - Port Event Enable Input 1"] +pub struct PORTEI1_R(crate::FieldReader); +impl PORTEI1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PORTEI1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PORTEI1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PORTEI1` writer - Port Event Enable Input 1"] +pub struct PORTEI1_W<'a> { + w: &'a mut W, +} +impl<'a> PORTEI1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `PID2` reader - Port Event Pin Identifier 2"] +pub struct PID2_R(crate::FieldReader); +impl PID2_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PID2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PID2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PID2` writer - Port Event Pin Identifier 2"] +pub struct PID2_W<'a> { + w: &'a mut W, +} +impl<'a> PID2_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 16)) | ((value as u32 & 0x1f) << 16); + self.w + } +} +#[doc = "Field `EVACT2` reader - Port Event Action 2"] +pub struct EVACT2_R(crate::FieldReader); +impl EVACT2_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVACT2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT2` writer - Port Event Action 2"] +pub struct EVACT2_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT2_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 21)) | ((value as u32 & 0x03) << 21); + self.w + } +} +#[doc = "Field `PORTEI2` reader - Port Event Enable Input 2"] +pub struct PORTEI2_R(crate::FieldReader); +impl PORTEI2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PORTEI2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PORTEI2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PORTEI2` writer - Port Event Enable Input 2"] +pub struct PORTEI2_W<'a> { + w: &'a mut W, +} +impl<'a> PORTEI2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `PID3` reader - Port Event Pin Identifier 3"] +pub struct PID3_R(crate::FieldReader); +impl PID3_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PID3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PID3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PID3` writer - Port Event Pin Identifier 3"] +pub struct PID3_W<'a> { + w: &'a mut W, +} +impl<'a> PID3_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 24)) | ((value as u32 & 0x1f) << 24); + self.w + } +} +#[doc = "Field `EVACT3` reader - Port Event Action 3"] +pub struct EVACT3_R(crate::FieldReader); +impl EVACT3_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVACT3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT3` writer - Port Event Action 3"] +pub struct EVACT3_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT3_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 29)) | ((value as u32 & 0x03) << 29); + self.w + } +} +#[doc = "Field `PORTEI3` reader - Port Event Enable Input 3"] +pub struct PORTEI3_R(crate::FieldReader); +impl PORTEI3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PORTEI3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PORTEI3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PORTEI3` writer - Port Event Enable Input 3"] +pub struct PORTEI3_W<'a> { + w: &'a mut W, +} +impl<'a> PORTEI3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Port Event Pin Identifier 0"] + #[inline(always)] + pub fn pid0(&self) -> PID0_R { + PID0_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:6 - Port Event Action 0"] + #[inline(always)] + pub fn evact0(&self) -> EVACT0_R { + EVACT0_R::new(((self.bits >> 5) & 0x03) as u8) + } + #[doc = "Bit 7 - Port Event Enable Input 0"] + #[inline(always)] + pub fn portei0(&self) -> PORTEI0_R { + PORTEI0_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:12 - Port Event Pin Identifier 1"] + #[inline(always)] + pub fn pid1(&self) -> PID1_R { + PID1_R::new(((self.bits >> 8) & 0x1f) as u8) + } + #[doc = "Bits 13:14 - Port Event Action 1"] + #[inline(always)] + pub fn evact1(&self) -> EVACT1_R { + EVACT1_R::new(((self.bits >> 13) & 0x03) as u8) + } + #[doc = "Bit 15 - Port Event Enable Input 1"] + #[inline(always)] + pub fn portei1(&self) -> PORTEI1_R { + PORTEI1_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:20 - Port Event Pin Identifier 2"] + #[inline(always)] + pub fn pid2(&self) -> PID2_R { + PID2_R::new(((self.bits >> 16) & 0x1f) as u8) + } + #[doc = "Bits 21:22 - Port Event Action 2"] + #[inline(always)] + pub fn evact2(&self) -> EVACT2_R { + EVACT2_R::new(((self.bits >> 21) & 0x03) as u8) + } + #[doc = "Bit 23 - Port Event Enable Input 2"] + #[inline(always)] + pub fn portei2(&self) -> PORTEI2_R { + PORTEI2_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bits 24:28 - Port Event Pin Identifier 3"] + #[inline(always)] + pub fn pid3(&self) -> PID3_R { + PID3_R::new(((self.bits >> 24) & 0x1f) as u8) + } + #[doc = "Bits 29:30 - Port Event Action 3"] + #[inline(always)] + pub fn evact3(&self) -> EVACT3_R { + EVACT3_R::new(((self.bits >> 29) & 0x03) as u8) + } + #[doc = "Bit 31 - Port Event Enable Input 3"] + #[inline(always)] + pub fn portei3(&self) -> PORTEI3_R { + PORTEI3_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Port Event Pin Identifier 0"] + #[inline(always)] + pub fn pid0(&mut self) -> PID0_W { + PID0_W { w: self } + } + #[doc = "Bits 5:6 - Port Event Action 0"] + #[inline(always)] + pub fn evact0(&mut self) -> EVACT0_W { + EVACT0_W { w: self } + } + #[doc = "Bit 7 - Port Event Enable Input 0"] + #[inline(always)] + pub fn portei0(&mut self) -> PORTEI0_W { + PORTEI0_W { w: self } + } + #[doc = "Bits 8:12 - Port Event Pin Identifier 1"] + #[inline(always)] + pub fn pid1(&mut self) -> PID1_W { + PID1_W { w: self } + } + #[doc = "Bits 13:14 - Port Event Action 1"] + #[inline(always)] + pub fn evact1(&mut self) -> EVACT1_W { + EVACT1_W { w: self } + } + #[doc = "Bit 15 - Port Event Enable Input 1"] + #[inline(always)] + pub fn portei1(&mut self) -> PORTEI1_W { + PORTEI1_W { w: self } + } + #[doc = "Bits 16:20 - Port Event Pin Identifier 2"] + #[inline(always)] + pub fn pid2(&mut self) -> PID2_W { + PID2_W { w: self } + } + #[doc = "Bits 21:22 - Port Event Action 2"] + #[inline(always)] + pub fn evact2(&mut self) -> EVACT2_W { + EVACT2_W { w: self } + } + #[doc = "Bit 23 - Port Event Enable Input 2"] + #[inline(always)] + pub fn portei2(&mut self) -> PORTEI2_W { + PORTEI2_W { w: self } + } + #[doc = "Bits 24:28 - Port Event Pin Identifier 3"] + #[inline(always)] + pub fn pid3(&mut self) -> PID3_W { + PID3_W { w: self } + } + #[doc = "Bits 29:30 - Port Event Action 3"] + #[inline(always)] + pub fn evact3(&mut self) -> EVACT3_W { + EVACT3_W { w: self } + } + #[doc = "Bit 31 - Port Event Enable Input 3"] + #[inline(always)] + pub fn portei3(&mut self) -> PORTEI3_W { + PORTEI3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Input Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/port/group/in_.rs b/pac/atsamc21j/src/port/group/in_.rs new file mode 100644 index 000000000000..1c8e7396a83e --- /dev/null +++ b/pac/atsamc21j/src/port/group/in_.rs @@ -0,0 +1,31 @@ +#[doc = "Register `IN` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Data Input Value\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [in_](index.html) module"] +pub struct IN_SPEC; +impl crate::RegisterSpec for IN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [in_::R](R) reader structure"] +impl crate::Readable for IN_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets IN to value 0"] +impl crate::Resettable for IN_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/port/group/out.rs b/pac/atsamc21j/src/port/group/out.rs new file mode 100644 index 000000000000..092e8dbd8023 --- /dev/null +++ b/pac/atsamc21j/src/port/group/out.rs @@ -0,0 +1,64 @@ +#[doc = "Register `OUT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OUT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Output Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [out](index.html) module"] +pub struct OUT_SPEC; +impl crate::RegisterSpec for OUT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [out::R](R) reader structure"] +impl crate::Readable for OUT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [out::W](W) writer structure"] +impl crate::Writable for OUT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OUT to value 0"] +impl crate::Resettable for OUT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/port/group/outclr.rs b/pac/atsamc21j/src/port/group/outclr.rs new file mode 100644 index 000000000000..6e734396601f --- /dev/null +++ b/pac/atsamc21j/src/port/group/outclr.rs @@ -0,0 +1,64 @@ +#[doc = "Register `OUTCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OUTCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Output Value Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [outclr](index.html) module"] +pub struct OUTCLR_SPEC; +impl crate::RegisterSpec for OUTCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [outclr::R](R) reader structure"] +impl crate::Readable for OUTCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [outclr::W](W) writer structure"] +impl crate::Writable for OUTCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OUTCLR to value 0"] +impl crate::Resettable for OUTCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/port/group/outset.rs b/pac/atsamc21j/src/port/group/outset.rs new file mode 100644 index 000000000000..6d39122deb4b --- /dev/null +++ b/pac/atsamc21j/src/port/group/outset.rs @@ -0,0 +1,64 @@ +#[doc = "Register `OUTSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OUTSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Output Value Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [outset](index.html) module"] +pub struct OUTSET_SPEC; +impl crate::RegisterSpec for OUTSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [outset::R](R) reader structure"] +impl crate::Readable for OUTSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [outset::W](W) writer structure"] +impl crate::Writable for OUTSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OUTSET to value 0"] +impl crate::Resettable for OUTSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/port/group/outtgl.rs b/pac/atsamc21j/src/port/group/outtgl.rs new file mode 100644 index 000000000000..0f3d87d6476d --- /dev/null +++ b/pac/atsamc21j/src/port/group/outtgl.rs @@ -0,0 +1,64 @@ +#[doc = "Register `OUTTGL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OUTTGL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Output Value Toggle\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [outtgl](index.html) module"] +pub struct OUTTGL_SPEC; +impl crate::RegisterSpec for OUTTGL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [outtgl::R](R) reader structure"] +impl crate::Readable for OUTTGL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [outtgl::W](W) writer structure"] +impl crate::Writable for OUTTGL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OUTTGL to value 0"] +impl crate::Resettable for OUTTGL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/port/group/pincfg.rs b/pac/atsamc21j/src/port/group/pincfg.rs new file mode 100644 index 000000000000..920af6550361 --- /dev/null +++ b/pac/atsamc21j/src/port/group/pincfg.rs @@ -0,0 +1,255 @@ +#[doc = "Register `PINCFG[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PINCFG[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PMUXEN` reader - Select Peripheral Multiplexer"] +pub struct PMUXEN_R(crate::FieldReader); +impl PMUXEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PMUXEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PMUXEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PMUXEN` writer - Select Peripheral Multiplexer"] +pub struct PMUXEN_W<'a> { + w: &'a mut W, +} +impl<'a> PMUXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `INEN` reader - Input Enable"] +pub struct INEN_R(crate::FieldReader); +impl INEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INEN` writer - Input Enable"] +pub struct INEN_W<'a> { + w: &'a mut W, +} +impl<'a> INEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PULLEN` reader - Pull Enable"] +pub struct PULLEN_R(crate::FieldReader); +impl PULLEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PULLEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PULLEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PULLEN` writer - Pull Enable"] +pub struct PULLEN_W<'a> { + w: &'a mut W, +} +impl<'a> PULLEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `DRVSTR` reader - Output Driver Strength Selection"] +pub struct DRVSTR_R(crate::FieldReader); +impl DRVSTR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRVSTR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRVSTR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRVSTR` writer - Output Driver Strength Selection"] +pub struct DRVSTR_W<'a> { + w: &'a mut W, +} +impl<'a> DRVSTR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - Select Peripheral Multiplexer"] + #[inline(always)] + pub fn pmuxen(&self) -> PMUXEN_R { + PMUXEN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Input Enable"] + #[inline(always)] + pub fn inen(&self) -> INEN_R { + INEN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Pull Enable"] + #[inline(always)] + pub fn pullen(&self) -> PULLEN_R { + PULLEN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 6 - Output Driver Strength Selection"] + #[inline(always)] + pub fn drvstr(&self) -> DRVSTR_R { + DRVSTR_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Select Peripheral Multiplexer"] + #[inline(always)] + pub fn pmuxen(&mut self) -> PMUXEN_W { + PMUXEN_W { w: self } + } + #[doc = "Bit 1 - Input Enable"] + #[inline(always)] + pub fn inen(&mut self) -> INEN_W { + INEN_W { w: self } + } + #[doc = "Bit 2 - Pull Enable"] + #[inline(always)] + pub fn pullen(&mut self) -> PULLEN_W { + PULLEN_W { w: self } + } + #[doc = "Bit 6 - Output Driver Strength Selection"] + #[inline(always)] + pub fn drvstr(&mut self) -> DRVSTR_W { + DRVSTR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Pin Configuration n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pincfg](index.html) module"] +pub struct PINCFG_SPEC; +impl crate::RegisterSpec for PINCFG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [pincfg::R](R) reader structure"] +impl crate::Readable for PINCFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [pincfg::W](W) writer structure"] +impl crate::Writable for PINCFG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PINCFG[%s] +to value 0"] +impl crate::Resettable for PINCFG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/port/group/pmux.rs b/pac/atsamc21j/src/port/group/pmux.rs new file mode 100644 index 000000000000..79c991a99daf --- /dev/null +++ b/pac/atsamc21j/src/port/group/pmux.rs @@ -0,0 +1,141 @@ +#[doc = "Register `PMUX[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PMUX[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PMUXE` reader - Peripheral Multiplexing for Even-Numbered Pin"] +pub struct PMUXE_R(crate::FieldReader); +impl PMUXE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PMUXE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PMUXE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PMUXE` writer - Peripheral Multiplexing for Even-Numbered Pin"] +pub struct PMUXE_W<'a> { + w: &'a mut W, +} +impl<'a> PMUXE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +#[doc = "Field `PMUXO` reader - Peripheral Multiplexing for Odd-Numbered Pin"] +pub struct PMUXO_R(crate::FieldReader); +impl PMUXO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PMUXO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PMUXO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PMUXO` writer - Peripheral Multiplexing for Odd-Numbered Pin"] +pub struct PMUXO_W<'a> { + w: &'a mut W, +} +impl<'a> PMUXO_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 4)) | ((value as u8 & 0x0f) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Peripheral Multiplexing for Even-Numbered Pin"] + #[inline(always)] + pub fn pmuxe(&self) -> PMUXE_R { + PMUXE_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Peripheral Multiplexing for Odd-Numbered Pin"] + #[inline(always)] + pub fn pmuxo(&self) -> PMUXO_R { + PMUXO_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Peripheral Multiplexing for Even-Numbered Pin"] + #[inline(always)] + pub fn pmuxe(&mut self) -> PMUXE_W { + PMUXE_W { w: self } + } + #[doc = "Bits 4:7 - Peripheral Multiplexing for Odd-Numbered Pin"] + #[inline(always)] + pub fn pmuxo(&mut self) -> PMUXO_W { + PMUXO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Peripheral Multiplexing n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pmux](index.html) module"] +pub struct PMUX_SPEC; +impl crate::RegisterSpec for PMUX_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [pmux::R](R) reader structure"] +impl crate::Readable for PMUX_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [pmux::W](W) writer structure"] +impl crate::Writable for PMUX_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PMUX[%s] +to value 0"] +impl crate::Resettable for PMUX_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/port/group/wrconfig.rs b/pac/atsamc21j/src/port/group/wrconfig.rs new file mode 100644 index 000000000000..c87e4f174728 --- /dev/null +++ b/pac/atsamc21j/src/port/group/wrconfig.rs @@ -0,0 +1,268 @@ +#[doc = "Register `WRCONFIG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PINMASK` writer - Pin Mask for Multiple Pin Configuration"] +pub struct PINMASK_W<'a> { + w: &'a mut W, +} +impl<'a> PINMASK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +#[doc = "Field `PMUXEN` writer - Select Peripheral Multiplexer"] +pub struct PMUXEN_W<'a> { + w: &'a mut W, +} +impl<'a> PMUXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `INEN` writer - Input Enable"] +pub struct INEN_W<'a> { + w: &'a mut W, +} +impl<'a> INEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `PULLEN` writer - Pull Enable"] +pub struct PULLEN_W<'a> { + w: &'a mut W, +} +impl<'a> PULLEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `DRVSTR` writer - Output Driver Strength Selection"] +pub struct DRVSTR_W<'a> { + w: &'a mut W, +} +impl<'a> DRVSTR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `PMUX` writer - Peripheral Multiplexing Template"] +pub struct PMUX_W<'a> { + w: &'a mut W, +} +impl<'a> PMUX_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Field `WRPMUX` writer - Write PMUX Registers"] +pub struct WRPMUX_W<'a> { + w: &'a mut W, +} +impl<'a> WRPMUX_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Field `WRPINCFG` writer - Write PINCFG Registers"] +pub struct WRPINCFG_W<'a> { + w: &'a mut W, +} +impl<'a> WRPINCFG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +#[doc = "Field `HWSEL` writer - Half-Word Select"] +pub struct HWSEL_W<'a> { + w: &'a mut W, +} +impl<'a> HWSEL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl W { + #[doc = "Bits 0:15 - Pin Mask for Multiple Pin Configuration"] + #[inline(always)] + pub fn pinmask(&mut self) -> PINMASK_W { + PINMASK_W { w: self } + } + #[doc = "Bit 16 - Select Peripheral Multiplexer"] + #[inline(always)] + pub fn pmuxen(&mut self) -> PMUXEN_W { + PMUXEN_W { w: self } + } + #[doc = "Bit 17 - Input Enable"] + #[inline(always)] + pub fn inen(&mut self) -> INEN_W { + INEN_W { w: self } + } + #[doc = "Bit 18 - Pull Enable"] + #[inline(always)] + pub fn pullen(&mut self) -> PULLEN_W { + PULLEN_W { w: self } + } + #[doc = "Bit 22 - Output Driver Strength Selection"] + #[inline(always)] + pub fn drvstr(&mut self) -> DRVSTR_W { + DRVSTR_W { w: self } + } + #[doc = "Bits 24:27 - Peripheral Multiplexing Template"] + #[inline(always)] + pub fn pmux(&mut self) -> PMUX_W { + PMUX_W { w: self } + } + #[doc = "Bit 28 - Write PMUX Registers"] + #[inline(always)] + pub fn wrpmux(&mut self) -> WRPMUX_W { + WRPMUX_W { w: self } + } + #[doc = "Bit 30 - Write PINCFG Registers"] + #[inline(always)] + pub fn wrpincfg(&mut self) -> WRPINCFG_W { + WRPINCFG_W { w: self } + } + #[doc = "Bit 31 - Half-Word Select"] + #[inline(always)] + pub fn hwsel(&mut self) -> HWSEL_W { + HWSEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Write Configuration\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wrconfig](index.html) module"] +pub struct WRCONFIG_SPEC; +impl crate::RegisterSpec for WRCONFIG_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [wrconfig::W](W) writer structure"] +impl crate::Writable for WRCONFIG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WRCONFIG to value 0"] +impl crate::Resettable for WRCONFIG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/rstc.rs b/pac/atsamc21j/src/rstc.rs new file mode 100644 index 000000000000..327b511df28a --- /dev/null +++ b/pac/atsamc21j/src/rstc.rs @@ -0,0 +1,10 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Reset Cause"] + pub rcause: crate::Reg, +} +#[doc = "RCAUSE register accessor: an alias for `Reg`"] +pub type RCAUSE = crate::Reg; +#[doc = "Reset Cause"] +pub mod rcause; diff --git a/pac/atsamc21j/src/rstc/rcause.rs b/pac/atsamc21j/src/rstc/rcause.rs new file mode 100644 index 000000000000..3dc13496e74b --- /dev/null +++ b/pac/atsamc21j/src/rstc/rcause.rs @@ -0,0 +1,153 @@ +#[doc = "Register `RCAUSE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `POR` reader - Power On Reset"] +pub struct POR_R(crate::FieldReader); +impl POR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + POR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for POR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODCORE` reader - Brown Out CORE Detector Reset"] +pub struct BODCORE_R(crate::FieldReader); +impl BODCORE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODCORE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODCORE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODVDD` reader - Brown Out VDD Detector Reset"] +pub struct BODVDD_R(crate::FieldReader); +impl BODVDD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODVDD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODVDD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXT` reader - External Reset"] +pub struct EXT_R(crate::FieldReader); +impl EXT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WDT` reader - Watchdog Reset"] +pub struct WDT_R(crate::FieldReader); +impl WDT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WDT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WDT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYST` reader - System Reset Request"] +pub struct SYST_R(crate::FieldReader); +impl SYST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Power On Reset"] + #[inline(always)] + pub fn por(&self) -> POR_R { + POR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Brown Out CORE Detector Reset"] + #[inline(always)] + pub fn bodcore(&self) -> BODCORE_R { + BODCORE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Brown Out VDD Detector Reset"] + #[inline(always)] + pub fn bodvdd(&self) -> BODVDD_R { + BODVDD_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 4 - External Reset"] + #[inline(always)] + pub fn ext(&self) -> EXT_R { + EXT_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Watchdog Reset"] + #[inline(always)] + pub fn wdt(&self) -> WDT_R { + WDT_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - System Reset Request"] + #[inline(always)] + pub fn syst(&self) -> SYST_R { + SYST_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +#[doc = "Reset Cause\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rcause](index.html) module"] +pub struct RCAUSE_SPEC; +impl crate::RegisterSpec for RCAUSE_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [rcause::R](R) reader structure"] +impl crate::Readable for RCAUSE_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets RCAUSE to value 0"] +impl crate::Resettable for RCAUSE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/rtc.rs b/pac/atsamc21j/src/rtc.rs new file mode 100644 index 000000000000..62f424cb1a8e --- /dev/null +++ b/pac/atsamc21j/src/rtc.rs @@ -0,0 +1,120 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved_0_mode0: [u8; 0x25], +} +impl RegisterBlock { + #[doc = "0x00..0x25 - Clock/Calendar with Alarm"] + #[inline(always)] + pub fn mode2(&self) -> &MODE2 { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const MODE2) } + } + #[doc = "0x00..0x24 - 16-bit Counter with Two 16-bit Compares"] + #[inline(always)] + pub fn mode1(&self) -> &MODE1 { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const MODE1) } + } + #[doc = "0x00..0x24 - 32-bit Counter with Single 32-bit Compare"] + #[inline(always)] + pub fn mode0(&self) -> &MODE0 { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const MODE0) } + } +} +#[doc = r"Register block"] +#[repr(C)] +pub struct MODE0 { + #[doc = "0x00 - MODE0 Control A"] + pub ctrla: crate::Reg, + _reserved1: [u8; 0x02], + #[doc = "0x04 - MODE0 Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x08 - MODE0 Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x0a - MODE0 Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x0c - MODE0 Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x0e - Debug Control"] + pub dbgctrl: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x10 - MODE0 Synchronization Busy Status"] + pub syncbusy: crate::Reg, + #[doc = "0x14 - Frequency Correction"] + pub freqcorr: crate::Reg, + _reserved8: [u8; 0x03], + #[doc = "0x18 - MODE0 Counter Value"] + pub count: crate::Reg, + _reserved9: [u8; 0x04], + #[doc = "0x20 - MODE0 Compare n Value"] + pub comp: crate::Reg, +} +#[doc = r"Register block"] +#[doc = "32-bit Counter with Single 32-bit Compare"] +pub mod mode0; +#[doc = r"Register block"] +#[repr(C)] +pub struct MODE1 { + #[doc = "0x00 - MODE1 Control A"] + pub ctrla: crate::Reg, + _reserved1: [u8; 0x02], + #[doc = "0x04 - MODE1 Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x08 - MODE1 Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x0a - MODE1 Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x0c - MODE1 Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x0e - Debug Control"] + pub dbgctrl: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x10 - MODE1 Synchronization Busy Status"] + pub syncbusy: crate::Reg, + #[doc = "0x14 - Frequency Correction"] + pub freqcorr: crate::Reg, + _reserved8: [u8; 0x03], + #[doc = "0x18 - MODE1 Counter Value"] + pub count: crate::Reg, + _reserved9: [u8; 0x02], + #[doc = "0x1c - MODE1 Counter Period"] + pub per: crate::Reg, + _reserved10: [u8; 0x02], + #[doc = "0x20 - MODE1 Compare n Value"] + pub comp: [crate::Reg; 2], +} +#[doc = r"Register block"] +#[doc = "16-bit Counter with Two 16-bit Compares"] +pub mod mode1; +#[doc = r"Register block"] +#[repr(C)] +pub struct MODE2 { + #[doc = "0x00 - MODE2 Control A"] + pub ctrla: crate::Reg, + _reserved1: [u8; 0x02], + #[doc = "0x04 - MODE2 Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x08 - MODE2 Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x0a - MODE2 Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x0c - MODE2 Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x0e - Debug Control"] + pub dbgctrl: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x10 - MODE2 Synchronization Busy Status"] + pub syncbusy: crate::Reg, + #[doc = "0x14 - Frequency Correction"] + pub freqcorr: crate::Reg, + _reserved8: [u8; 0x03], + #[doc = "0x18 - MODE2 Clock Value"] + pub clock: crate::Reg, + _reserved9: [u8; 0x04], + #[doc = "0x20 - MODE2_ALARM Alarm n Value"] + pub alarm: crate::Reg, + #[doc = "0x24 - MODE2_ALARM Alarm n Mask"] + pub mask: crate::Reg, +} +#[doc = r"Register block"] +#[doc = "Clock/Calendar with Alarm"] +pub mod mode2; diff --git a/pac/atsamc21j/src/rtc/mode0.rs b/pac/atsamc21j/src/rtc/mode0.rs new file mode 100644 index 000000000000..9ce5c3808169 --- /dev/null +++ b/pac/atsamc21j/src/rtc/mode0.rs @@ -0,0 +1,40 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "MODE0 Control A"] +pub mod ctrla; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "MODE0 Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "MODE0 Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "MODE0 Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "MODE0 Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "MODE0 Synchronization Busy Status"] +pub mod syncbusy; +#[doc = "FREQCORR register accessor: an alias for `Reg`"] +pub type FREQCORR = crate::Reg; +#[doc = "Frequency Correction"] +pub mod freqcorr; +#[doc = "COUNT register accessor: an alias for `Reg`"] +pub type COUNT = crate::Reg; +#[doc = "MODE0 Counter Value"] +pub mod count; +#[doc = "COMP register accessor: an alias for `Reg`"] +pub type COMP = crate::Reg; +#[doc = "MODE0 Compare n Value"] +pub mod comp; diff --git a/pac/atsamc21j/src/rtc/mode0/comp.rs b/pac/atsamc21j/src/rtc/mode0/comp.rs new file mode 100644 index 000000000000..a909d3cea2d3 --- /dev/null +++ b/pac/atsamc21j/src/rtc/mode0/comp.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COMP` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COMP` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COMP` reader - Compare Value"] +pub struct COMP_R(crate::FieldReader); +impl COMP_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COMP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP` writer - Compare Value"] +pub struct COMP_W<'a> { + w: &'a mut W, +} +impl<'a> COMP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Compare Value"] + #[inline(always)] + pub fn comp(&self) -> COMP_R { + COMP_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Compare Value"] + #[inline(always)] + pub fn comp(&mut self) -> COMP_W { + COMP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE0 Compare n Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [comp](index.html) module"] +pub struct COMP_SPEC; +impl crate::RegisterSpec for COMP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [comp::R](R) reader structure"] +impl crate::Readable for COMP_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [comp::W](W) writer structure"] +impl crate::Writable for COMP_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COMP to value 0"] +impl crate::Resettable for COMP_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/rtc/mode0/count.rs b/pac/atsamc21j/src/rtc/mode0/count.rs new file mode 100644 index 000000000000..cf880b5e77a6 --- /dev/null +++ b/pac/atsamc21j/src/rtc/mode0/count.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE0 Counter Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count](index.html) module"] +pub struct COUNT_SPEC; +impl crate::RegisterSpec for COUNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [count::R](R) reader structure"] +impl crate::Readable for COUNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count::W](W) writer structure"] +impl crate::Writable for COUNT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT to value 0"] +impl crate::Resettable for COUNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/rtc/mode0/ctrla.rs b/pac/atsamc21j/src/rtc/mode0/ctrla.rs new file mode 100644 index 000000000000..423877bd087d --- /dev/null +++ b/pac/atsamc21j/src/rtc/mode0/ctrla.rs @@ -0,0 +1,569 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: Mode 0: 32-bit Counter"] + COUNT32 = 0, + #[doc = "1: Mode 1: 16-bit Counter"] + COUNT16 = 1, + #[doc = "2: Mode 2: Clock/Calendar"] + CLOCK = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::COUNT32), + 1 => Some(MODE_A::COUNT16), + 2 => Some(MODE_A::CLOCK), + _ => None, + } + } + #[doc = "Checks if the value of the field is `COUNT32`"] + #[inline(always)] + pub fn is_count32(&self) -> bool { + **self == MODE_A::COUNT32 + } + #[doc = "Checks if the value of the field is `COUNT16`"] + #[inline(always)] + pub fn is_count16(&self) -> bool { + **self == MODE_A::COUNT16 + } + #[doc = "Checks if the value of the field is `CLOCK`"] + #[inline(always)] + pub fn is_clock(&self) -> bool { + **self == MODE_A::CLOCK + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Mode 0: 32-bit Counter"] + #[inline(always)] + pub fn count32(self) -> &'a mut W { + self.variant(MODE_A::COUNT32) + } + #[doc = "Mode 1: 16-bit Counter"] + #[inline(always)] + pub fn count16(self) -> &'a mut W { + self.variant(MODE_A::COUNT16) + } + #[doc = "Mode 2: Clock/Calendar"] + #[inline(always)] + pub fn clock(self) -> &'a mut W { + self.variant(MODE_A::CLOCK) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u16 & 0x03) << 2); + self.w + } +} +#[doc = "Field `MATCHCLR` reader - Clear on Match"] +pub struct MATCHCLR_R(crate::FieldReader); +impl MATCHCLR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MATCHCLR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MATCHCLR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MATCHCLR` writer - Clear on Match"] +pub struct MATCHCLR_W<'a> { + w: &'a mut W, +} +impl<'a> MATCHCLR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: CLK_RTC_CNT = GCLK_RTC/1"] + OFF = 0, + #[doc = "1: CLK_RTC_CNT = GCLK_RTC/1"] + DIV1 = 1, + #[doc = "2: CLK_RTC_CNT = GCLK_RTC/2"] + DIV2 = 2, + #[doc = "3: CLK_RTC_CNT = GCLK_RTC/4"] + DIV4 = 3, + #[doc = "4: CLK_RTC_CNT = GCLK_RTC/8"] + DIV8 = 4, + #[doc = "5: CLK_RTC_CNT = GCLK_RTC/16"] + DIV16 = 5, + #[doc = "6: CLK_RTC_CNT = GCLK_RTC/32"] + DIV32 = 6, + #[doc = "7: CLK_RTC_CNT = GCLK_RTC/64"] + DIV64 = 7, + #[doc = "8: CLK_RTC_CNT = GCLK_RTC/128"] + DIV128 = 8, + #[doc = "9: CLK_RTC_CNT = GCLK_RTC/256"] + DIV256 = 9, + #[doc = "10: CLK_RTC_CNT = GCLK_RTC/512"] + DIV512 = 10, + #[doc = "11: CLK_RTC_CNT = GCLK_RTC/1024"] + DIV1024 = 11, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCALER_A::OFF), + 1 => Some(PRESCALER_A::DIV1), + 2 => Some(PRESCALER_A::DIV2), + 3 => Some(PRESCALER_A::DIV4), + 4 => Some(PRESCALER_A::DIV8), + 5 => Some(PRESCALER_A::DIV16), + 6 => Some(PRESCALER_A::DIV32), + 7 => Some(PRESCALER_A::DIV64), + 8 => Some(PRESCALER_A::DIV128), + 9 => Some(PRESCALER_A::DIV256), + 10 => Some(PRESCALER_A::DIV512), + 11 => Some(PRESCALER_A::DIV1024), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == PRESCALER_A::OFF + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == PRESCALER_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == PRESCALER_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == PRESCALER_A::DIV128 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV512`"] + #[inline(always)] + pub fn is_div512(&self) -> bool { + **self == PRESCALER_A::DIV512 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PRESCALER_A::DIV1024 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(PRESCALER_A::OFF) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV32) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV128) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/512"] + #[inline(always)] + pub fn div512(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV512) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 8)) | ((value as u16 & 0x0f) << 8); + self.w + } +} +#[doc = "Field `COUNTSYNC` reader - Count Read Synchronization Enable"] +pub struct COUNTSYNC_R(crate::FieldReader); +impl COUNTSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNTSYNC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNTSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNTSYNC` writer - Count Read Synchronization Enable"] +pub struct COUNTSYNC_W<'a> { + w: &'a mut W, +} +impl<'a> COUNTSYNC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:3 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bit 7 - Clear on Match"] + #[inline(always)] + pub fn matchclr(&self) -> MATCHCLR_R { + MATCHCLR_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:11 - Prescaler"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 15 - Count Read Synchronization Enable"] + #[inline(always)] + pub fn countsync(&self) -> COUNTSYNC_R { + COUNTSYNC_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:3 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 7 - Clear on Match"] + #[inline(always)] + pub fn matchclr(&mut self) -> MATCHCLR_W { + MATCHCLR_W { w: self } + } + #[doc = "Bits 8:11 - Prescaler"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Bit 15 - Count Read Synchronization Enable"] + #[inline(always)] + pub fn countsync(&mut self) -> COUNTSYNC_W { + COUNTSYNC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE0 Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/rtc/mode0/dbgctrl.rs b/pac/atsamc21j/src/rtc/mode0/dbgctrl.rs new file mode 100644 index 000000000000..0383e70d0429 --- /dev/null +++ b/pac/atsamc21j/src/rtc/mode0/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Run During Debug"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Run During Debug"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/rtc/mode0/evctrl.rs b/pac/atsamc21j/src/rtc/mode0/evctrl.rs new file mode 100644 index 000000000000..c73647759dbe --- /dev/null +++ b/pac/atsamc21j/src/rtc/mode0/evctrl.rs @@ -0,0 +1,536 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PEREO0` reader - Periodic Interval 0 Event Output Enable"] +pub struct PEREO0_R(crate::FieldReader); +impl PEREO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO0` writer - Periodic Interval 0 Event Output Enable"] +pub struct PEREO0_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `PEREO1` reader - Periodic Interval 1 Event Output Enable"] +pub struct PEREO1_R(crate::FieldReader); +impl PEREO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO1` writer - Periodic Interval 1 Event Output Enable"] +pub struct PEREO1_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PEREO2` reader - Periodic Interval 2 Event Output Enable"] +pub struct PEREO2_R(crate::FieldReader); +impl PEREO2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO2` writer - Periodic Interval 2 Event Output Enable"] +pub struct PEREO2_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PEREO3` reader - Periodic Interval 3 Event Output Enable"] +pub struct PEREO3_R(crate::FieldReader); +impl PEREO3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO3` writer - Periodic Interval 3 Event Output Enable"] +pub struct PEREO3_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PEREO4` reader - Periodic Interval 4 Event Output Enable"] +pub struct PEREO4_R(crate::FieldReader); +impl PEREO4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO4` writer - Periodic Interval 4 Event Output Enable"] +pub struct PEREO4_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PEREO5` reader - Periodic Interval 5 Event Output Enable"] +pub struct PEREO5_R(crate::FieldReader); +impl PEREO5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO5` writer - Periodic Interval 5 Event Output Enable"] +pub struct PEREO5_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PEREO6` reader - Periodic Interval 6 Event Output Enable"] +pub struct PEREO6_R(crate::FieldReader); +impl PEREO6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO6` writer - Periodic Interval 6 Event Output Enable"] +pub struct PEREO6_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PEREO7` reader - Periodic Interval 7 Event Output Enable"] +pub struct PEREO7_R(crate::FieldReader); +impl PEREO7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO7` writer - Periodic Interval 7 Event Output Enable"] +pub struct PEREO7_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CMPEO0` reader - Compare 0 Event Output Enable"] +pub struct CMPEO0_R(crate::FieldReader); +impl CMPEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMPEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMPEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMPEO0` writer - Compare 0 Event Output Enable"] +pub struct CMPEO0_W<'a> { + w: &'a mut W, +} +impl<'a> CMPEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `OVFEO` reader - Overflow Event Output Enable"] +pub struct OVFEO_R(crate::FieldReader); +impl OVFEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVFEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVFEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVFEO` writer - Overflow Event Output Enable"] +pub struct OVFEO_W<'a> { + w: &'a mut W, +} +impl<'a> OVFEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Event Output Enable"] + #[inline(always)] + pub fn pereo0(&self) -> PEREO0_R { + PEREO0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Event Output Enable"] + #[inline(always)] + pub fn pereo1(&self) -> PEREO1_R { + PEREO1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Event Output Enable"] + #[inline(always)] + pub fn pereo2(&self) -> PEREO2_R { + PEREO2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Event Output Enable"] + #[inline(always)] + pub fn pereo3(&self) -> PEREO3_R { + PEREO3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Event Output Enable"] + #[inline(always)] + pub fn pereo4(&self) -> PEREO4_R { + PEREO4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Event Output Enable"] + #[inline(always)] + pub fn pereo5(&self) -> PEREO5_R { + PEREO5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Event Output Enable"] + #[inline(always)] + pub fn pereo6(&self) -> PEREO6_R { + PEREO6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Event Output Enable"] + #[inline(always)] + pub fn pereo7(&self) -> PEREO7_R { + PEREO7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Compare 0 Event Output Enable"] + #[inline(always)] + pub fn cmpeo0(&self) -> CMPEO0_R { + CMPEO0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&self) -> OVFEO_R { + OVFEO_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Event Output Enable"] + #[inline(always)] + pub fn pereo0(&mut self) -> PEREO0_W { + PEREO0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1 Event Output Enable"] + #[inline(always)] + pub fn pereo1(&mut self) -> PEREO1_W { + PEREO1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2 Event Output Enable"] + #[inline(always)] + pub fn pereo2(&mut self) -> PEREO2_W { + PEREO2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3 Event Output Enable"] + #[inline(always)] + pub fn pereo3(&mut self) -> PEREO3_W { + PEREO3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4 Event Output Enable"] + #[inline(always)] + pub fn pereo4(&mut self) -> PEREO4_W { + PEREO4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5 Event Output Enable"] + #[inline(always)] + pub fn pereo5(&mut self) -> PEREO5_W { + PEREO5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6 Event Output Enable"] + #[inline(always)] + pub fn pereo6(&mut self) -> PEREO6_W { + PEREO6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7 Event Output Enable"] + #[inline(always)] + pub fn pereo7(&mut self) -> PEREO7_W { + PEREO7_W { w: self } + } + #[doc = "Bit 8 - Compare 0 Event Output Enable"] + #[inline(always)] + pub fn cmpeo0(&mut self) -> CMPEO0_W { + CMPEO0_W { w: self } + } + #[doc = "Bit 15 - Overflow Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&mut self) -> OVFEO_W { + OVFEO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE0 Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/rtc/mode0/freqcorr.rs b/pac/atsamc21j/src/rtc/mode0/freqcorr.rs new file mode 100644 index 000000000000..043ba6f88eb2 --- /dev/null +++ b/pac/atsamc21j/src/rtc/mode0/freqcorr.rs @@ -0,0 +1,150 @@ +#[doc = "Register `FREQCORR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FREQCORR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `VALUE` reader - Correction Value"] +pub struct VALUE_R(crate::FieldReader); +impl VALUE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + VALUE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VALUE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VALUE` writer - Correction Value"] +pub struct VALUE_W<'a> { + w: &'a mut W, +} +impl<'a> VALUE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x7f) | (value as u8 & 0x7f); + self.w + } +} +#[doc = "Field `SIGN` reader - Correction Sign"] +pub struct SIGN_R(crate::FieldReader); +impl SIGN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SIGN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SIGN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SIGN` writer - Correction Sign"] +pub struct SIGN_W<'a> { + w: &'a mut W, +} +impl<'a> SIGN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bits 0:6 - Correction Value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bit 7 - Correction Sign"] + #[inline(always)] + pub fn sign(&self) -> SIGN_R { + SIGN_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:6 - Correction Value"] + #[inline(always)] + pub fn value(&mut self) -> VALUE_W { + VALUE_W { w: self } + } + #[doc = "Bit 7 - Correction Sign"] + #[inline(always)] + pub fn sign(&mut self) -> SIGN_W { + SIGN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Frequency Correction\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [freqcorr](index.html) module"] +pub struct FREQCORR_SPEC; +impl crate::RegisterSpec for FREQCORR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [freqcorr::R](R) reader structure"] +impl crate::Readable for FREQCORR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [freqcorr::W](W) writer structure"] +impl crate::Writable for FREQCORR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets FREQCORR to value 0"] +impl crate::Resettable for FREQCORR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/rtc/mode0/intenclr.rs b/pac/atsamc21j/src/rtc/mode0/intenclr.rs new file mode 100644 index 000000000000..8be5e2c3920b --- /dev/null +++ b/pac/atsamc21j/src/rtc/mode0/intenclr.rs @@ -0,0 +1,536 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER0` reader - Periodic Interval 0 Interrupt Enable"] +pub struct PER0_R(crate::FieldReader); +impl PER0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER0` writer - Periodic Interval 0 Interrupt Enable"] +pub struct PER0_W<'a> { + w: &'a mut W, +} +impl<'a> PER0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PER1` reader - Periodic Interval 1 Interrupt Enable"] +pub struct PER1_R(crate::FieldReader); +impl PER1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER1` writer - Periodic Interval 1 Interrupt Enable"] +pub struct PER1_W<'a> { + w: &'a mut W, +} +impl<'a> PER1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PER2` reader - Periodic Interval 2 Interrupt Enable"] +pub struct PER2_R(crate::FieldReader); +impl PER2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER2` writer - Periodic Interval 2 Interrupt Enable"] +pub struct PER2_W<'a> { + w: &'a mut W, +} +impl<'a> PER2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PER3` reader - Periodic Interval 3 Interrupt Enable"] +pub struct PER3_R(crate::FieldReader); +impl PER3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER3` writer - Periodic Interval 3 Interrupt Enable"] +pub struct PER3_W<'a> { + w: &'a mut W, +} +impl<'a> PER3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PER4` reader - Periodic Interval 4 Interrupt Enable"] +pub struct PER4_R(crate::FieldReader); +impl PER4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER4` writer - Periodic Interval 4 Interrupt Enable"] +pub struct PER4_W<'a> { + w: &'a mut W, +} +impl<'a> PER4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PER5` reader - Periodic Interval 5 Interrupt Enable"] +pub struct PER5_R(crate::FieldReader); +impl PER5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER5` writer - Periodic Interval 5 Interrupt Enable"] +pub struct PER5_W<'a> { + w: &'a mut W, +} +impl<'a> PER5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PER6` reader - Periodic Interval 6 Interrupt Enable"] +pub struct PER6_R(crate::FieldReader); +impl PER6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER6` writer - Periodic Interval 6 Interrupt Enable"] +pub struct PER6_W<'a> { + w: &'a mut W, +} +impl<'a> PER6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PER7` reader - Periodic Interval 7 Interrupt Enable"] +pub struct PER7_R(crate::FieldReader); +impl PER7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER7` writer - Periodic Interval 7 Interrupt Enable"] +pub struct PER7_W<'a> { + w: &'a mut W, +} +impl<'a> PER7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CMP0` reader - Compare 0 Interrupt Enable"] +pub struct CMP0_R(crate::FieldReader); +impl CMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP0` writer - Compare 0 Interrupt Enable"] +pub struct CMP0_W<'a> { + w: &'a mut W, +} +impl<'a> CMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + pub fn per0(&self) -> PER0_R { + PER0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + pub fn per1(&self) -> PER1_R { + PER1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + pub fn per2(&self) -> PER2_R { + PER2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + pub fn per3(&self) -> PER3_R { + PER3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + pub fn per4(&self) -> PER4_R { + PER4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + pub fn per5(&self) -> PER5_R { + PER5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + pub fn per6(&self) -> PER6_R { + PER6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + pub fn per7(&self) -> PER7_R { + PER7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&self) -> CMP0_R { + CMP0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + pub fn per0(&mut self) -> PER0_W { + PER0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + pub fn per1(&mut self) -> PER1_W { + PER1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + pub fn per2(&mut self) -> PER2_W { + PER2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + pub fn per3(&mut self) -> PER3_W { + PER3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + pub fn per4(&mut self) -> PER4_W { + PER4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + pub fn per5(&mut self) -> PER5_W { + PER5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + pub fn per6(&mut self) -> PER6_W { + PER6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + pub fn per7(&mut self) -> PER7_W { + PER7_W { w: self } + } + #[doc = "Bit 8 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&mut self) -> CMP0_W { + CMP0_W { w: self } + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE0 Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/rtc/mode0/intenset.rs b/pac/atsamc21j/src/rtc/mode0/intenset.rs new file mode 100644 index 000000000000..7228f5d486f5 --- /dev/null +++ b/pac/atsamc21j/src/rtc/mode0/intenset.rs @@ -0,0 +1,536 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER0` reader - Periodic Interval 0 Interrupt Enable"] +pub struct PER0_R(crate::FieldReader); +impl PER0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER0` writer - Periodic Interval 0 Interrupt Enable"] +pub struct PER0_W<'a> { + w: &'a mut W, +} +impl<'a> PER0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PER1` reader - Periodic Interval 1 Interrupt Enable"] +pub struct PER1_R(crate::FieldReader); +impl PER1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER1` writer - Periodic Interval 1 Interrupt Enable"] +pub struct PER1_W<'a> { + w: &'a mut W, +} +impl<'a> PER1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PER2` reader - Periodic Interval 2 Interrupt Enable"] +pub struct PER2_R(crate::FieldReader); +impl PER2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER2` writer - Periodic Interval 2 Interrupt Enable"] +pub struct PER2_W<'a> { + w: &'a mut W, +} +impl<'a> PER2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PER3` reader - Periodic Interval 3 Interrupt Enable"] +pub struct PER3_R(crate::FieldReader); +impl PER3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER3` writer - Periodic Interval 3 Interrupt Enable"] +pub struct PER3_W<'a> { + w: &'a mut W, +} +impl<'a> PER3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PER4` reader - Periodic Interval 4 Interrupt Enable"] +pub struct PER4_R(crate::FieldReader); +impl PER4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER4` writer - Periodic Interval 4 Interrupt Enable"] +pub struct PER4_W<'a> { + w: &'a mut W, +} +impl<'a> PER4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PER5` reader - Periodic Interval 5 Interrupt Enable"] +pub struct PER5_R(crate::FieldReader); +impl PER5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER5` writer - Periodic Interval 5 Interrupt Enable"] +pub struct PER5_W<'a> { + w: &'a mut W, +} +impl<'a> PER5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PER6` reader - Periodic Interval 6 Interrupt Enable"] +pub struct PER6_R(crate::FieldReader); +impl PER6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER6` writer - Periodic Interval 6 Interrupt Enable"] +pub struct PER6_W<'a> { + w: &'a mut W, +} +impl<'a> PER6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PER7` reader - Periodic Interval 7 Interrupt Enable"] +pub struct PER7_R(crate::FieldReader); +impl PER7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER7` writer - Periodic Interval 7 Interrupt Enable"] +pub struct PER7_W<'a> { + w: &'a mut W, +} +impl<'a> PER7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CMP0` reader - Compare 0 Interrupt Enable"] +pub struct CMP0_R(crate::FieldReader); +impl CMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP0` writer - Compare 0 Interrupt Enable"] +pub struct CMP0_W<'a> { + w: &'a mut W, +} +impl<'a> CMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + pub fn per0(&self) -> PER0_R { + PER0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + pub fn per1(&self) -> PER1_R { + PER1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + pub fn per2(&self) -> PER2_R { + PER2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + pub fn per3(&self) -> PER3_R { + PER3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + pub fn per4(&self) -> PER4_R { + PER4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + pub fn per5(&self) -> PER5_R { + PER5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + pub fn per6(&self) -> PER6_R { + PER6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + pub fn per7(&self) -> PER7_R { + PER7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&self) -> CMP0_R { + CMP0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + pub fn per0(&mut self) -> PER0_W { + PER0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + pub fn per1(&mut self) -> PER1_W { + PER1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + pub fn per2(&mut self) -> PER2_W { + PER2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + pub fn per3(&mut self) -> PER3_W { + PER3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + pub fn per4(&mut self) -> PER4_W { + PER4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + pub fn per5(&mut self) -> PER5_W { + PER5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + pub fn per6(&mut self) -> PER6_W { + PER6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + pub fn per7(&mut self) -> PER7_W { + PER7_W { w: self } + } + #[doc = "Bit 8 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&mut self) -> CMP0_W { + CMP0_W { w: self } + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE0 Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/rtc/mode0/intflag.rs b/pac/atsamc21j/src/rtc/mode0/intflag.rs new file mode 100644 index 000000000000..f2dccdb04aa4 --- /dev/null +++ b/pac/atsamc21j/src/rtc/mode0/intflag.rs @@ -0,0 +1,536 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER0` reader - Periodic Interval 0"] +pub struct PER0_R(crate::FieldReader); +impl PER0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER0` writer - Periodic Interval 0"] +pub struct PER0_W<'a> { + w: &'a mut W, +} +impl<'a> PER0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PER1` reader - Periodic Interval 1"] +pub struct PER1_R(crate::FieldReader); +impl PER1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER1` writer - Periodic Interval 1"] +pub struct PER1_W<'a> { + w: &'a mut W, +} +impl<'a> PER1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PER2` reader - Periodic Interval 2"] +pub struct PER2_R(crate::FieldReader); +impl PER2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER2` writer - Periodic Interval 2"] +pub struct PER2_W<'a> { + w: &'a mut W, +} +impl<'a> PER2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PER3` reader - Periodic Interval 3"] +pub struct PER3_R(crate::FieldReader); +impl PER3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER3` writer - Periodic Interval 3"] +pub struct PER3_W<'a> { + w: &'a mut W, +} +impl<'a> PER3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PER4` reader - Periodic Interval 4"] +pub struct PER4_R(crate::FieldReader); +impl PER4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER4` writer - Periodic Interval 4"] +pub struct PER4_W<'a> { + w: &'a mut W, +} +impl<'a> PER4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PER5` reader - Periodic Interval 5"] +pub struct PER5_R(crate::FieldReader); +impl PER5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER5` writer - Periodic Interval 5"] +pub struct PER5_W<'a> { + w: &'a mut W, +} +impl<'a> PER5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PER6` reader - Periodic Interval 6"] +pub struct PER6_R(crate::FieldReader); +impl PER6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER6` writer - Periodic Interval 6"] +pub struct PER6_W<'a> { + w: &'a mut W, +} +impl<'a> PER6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PER7` reader - Periodic Interval 7"] +pub struct PER7_R(crate::FieldReader); +impl PER7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER7` writer - Periodic Interval 7"] +pub struct PER7_W<'a> { + w: &'a mut W, +} +impl<'a> PER7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CMP0` reader - Compare 0"] +pub struct CMP0_R(crate::FieldReader); +impl CMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP0` writer - Compare 0"] +pub struct CMP0_W<'a> { + w: &'a mut W, +} +impl<'a> CMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0"] + #[inline(always)] + pub fn per0(&self) -> PER0_R { + PER0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1"] + #[inline(always)] + pub fn per1(&self) -> PER1_R { + PER1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2"] + #[inline(always)] + pub fn per2(&self) -> PER2_R { + PER2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3"] + #[inline(always)] + pub fn per3(&self) -> PER3_R { + PER3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4"] + #[inline(always)] + pub fn per4(&self) -> PER4_R { + PER4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5"] + #[inline(always)] + pub fn per5(&self) -> PER5_R { + PER5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6"] + #[inline(always)] + pub fn per6(&self) -> PER6_R { + PER6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7"] + #[inline(always)] + pub fn per7(&self) -> PER7_R { + PER7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Compare 0"] + #[inline(always)] + pub fn cmp0(&self) -> CMP0_R { + CMP0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0"] + #[inline(always)] + pub fn per0(&mut self) -> PER0_W { + PER0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1"] + #[inline(always)] + pub fn per1(&mut self) -> PER1_W { + PER1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2"] + #[inline(always)] + pub fn per2(&mut self) -> PER2_W { + PER2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3"] + #[inline(always)] + pub fn per3(&mut self) -> PER3_W { + PER3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4"] + #[inline(always)] + pub fn per4(&mut self) -> PER4_W { + PER4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5"] + #[inline(always)] + pub fn per5(&mut self) -> PER5_W { + PER5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6"] + #[inline(always)] + pub fn per6(&mut self) -> PER6_W { + PER6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7"] + #[inline(always)] + pub fn per7(&mut self) -> PER7_W { + PER7_W { w: self } + } + #[doc = "Bit 8 - Compare 0"] + #[inline(always)] + pub fn cmp0(&mut self) -> CMP0_W { + CMP0_W { w: self } + } + #[doc = "Bit 15 - Overflow"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE0 Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/rtc/mode0/syncbusy.rs b/pac/atsamc21j/src/rtc/mode0/syncbusy.rs new file mode 100644 index 000000000000..518dea115a18 --- /dev/null +++ b/pac/atsamc21j/src/rtc/mode0/syncbusy.rs @@ -0,0 +1,153 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - Enable Bit Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FREQCORR` reader - FREQCORR Register Busy"] +pub struct FREQCORR_R(crate::FieldReader); +impl FREQCORR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FREQCORR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FREQCORR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` reader - COUNT Register Busy"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP0` reader - COMP 0 Register Busy"] +pub struct COMP0_R(crate::FieldReader); +impl COMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNTSYNC` reader - Count Read Synchronization Enable Bit Busy"] +pub struct COUNTSYNC_R(crate::FieldReader); +impl COUNTSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNTSYNC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNTSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable Bit Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - FREQCORR Register Busy"] + #[inline(always)] + pub fn freqcorr(&self) -> FREQCORR_R { + FREQCORR_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - COUNT Register Busy"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 5 - COMP 0 Register Busy"] + #[inline(always)] + pub fn comp0(&self) -> COMP0_R { + COMP0_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 15 - Count Read Synchronization Enable Bit Busy"] + #[inline(always)] + pub fn countsync(&self) -> COUNTSYNC_R { + COUNTSYNC_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +#[doc = "MODE0 Synchronization Busy Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/rtc/mode1.rs b/pac/atsamc21j/src/rtc/mode1.rs new file mode 100644 index 000000000000..9ea1bc17497c --- /dev/null +++ b/pac/atsamc21j/src/rtc/mode1.rs @@ -0,0 +1,44 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "MODE1 Control A"] +pub mod ctrla; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "MODE1 Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "MODE1 Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "MODE1 Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "MODE1 Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "MODE1 Synchronization Busy Status"] +pub mod syncbusy; +#[doc = "FREQCORR register accessor: an alias for `Reg`"] +pub type FREQCORR = crate::Reg; +#[doc = "Frequency Correction"] +pub mod freqcorr; +#[doc = "COUNT register accessor: an alias for `Reg`"] +pub type COUNT = crate::Reg; +#[doc = "MODE1 Counter Value"] +pub mod count; +#[doc = "PER register accessor: an alias for `Reg`"] +pub type PER = crate::Reg; +#[doc = "MODE1 Counter Period"] +pub mod per; +#[doc = "COMP register accessor: an alias for `Reg`"] +pub type COMP = crate::Reg; +#[doc = "MODE1 Compare n Value"] +pub mod comp; diff --git a/pac/atsamc21j/src/rtc/mode1/comp.rs b/pac/atsamc21j/src/rtc/mode1/comp.rs new file mode 100644 index 000000000000..6935385840f1 --- /dev/null +++ b/pac/atsamc21j/src/rtc/mode1/comp.rs @@ -0,0 +1,104 @@ +#[doc = "Register `COMP[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COMP[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COMP` reader - Compare Value"] +pub struct COMP_R(crate::FieldReader); +impl COMP_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + COMP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP` writer - Compare Value"] +pub struct COMP_W<'a> { + w: &'a mut W, +} +impl<'a> COMP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Compare Value"] + #[inline(always)] + pub fn comp(&self) -> COMP_R { + COMP_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Compare Value"] + #[inline(always)] + pub fn comp(&mut self) -> COMP_W { + COMP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Compare n Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [comp](index.html) module"] +pub struct COMP_SPEC; +impl crate::RegisterSpec for COMP_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [comp::R](R) reader structure"] +impl crate::Readable for COMP_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [comp::W](W) writer structure"] +impl crate::Writable for COMP_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COMP[%s] +to value 0"] +impl crate::Resettable for COMP_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/rtc/mode1/count.rs b/pac/atsamc21j/src/rtc/mode1/count.rs new file mode 100644 index 000000000000..2c41937b189c --- /dev/null +++ b/pac/atsamc21j/src/rtc/mode1/count.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Counter Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count](index.html) module"] +pub struct COUNT_SPEC; +impl crate::RegisterSpec for COUNT_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [count::R](R) reader structure"] +impl crate::Readable for COUNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count::W](W) writer structure"] +impl crate::Writable for COUNT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT to value 0"] +impl crate::Resettable for COUNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/rtc/mode1/ctrla.rs b/pac/atsamc21j/src/rtc/mode1/ctrla.rs new file mode 100644 index 000000000000..6e3e2042a9c4 --- /dev/null +++ b/pac/atsamc21j/src/rtc/mode1/ctrla.rs @@ -0,0 +1,522 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: Mode 0: 32-bit Counter"] + COUNT32 = 0, + #[doc = "1: Mode 1: 16-bit Counter"] + COUNT16 = 1, + #[doc = "2: Mode 2: Clock/Calendar"] + CLOCK = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::COUNT32), + 1 => Some(MODE_A::COUNT16), + 2 => Some(MODE_A::CLOCK), + _ => None, + } + } + #[doc = "Checks if the value of the field is `COUNT32`"] + #[inline(always)] + pub fn is_count32(&self) -> bool { + **self == MODE_A::COUNT32 + } + #[doc = "Checks if the value of the field is `COUNT16`"] + #[inline(always)] + pub fn is_count16(&self) -> bool { + **self == MODE_A::COUNT16 + } + #[doc = "Checks if the value of the field is `CLOCK`"] + #[inline(always)] + pub fn is_clock(&self) -> bool { + **self == MODE_A::CLOCK + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Mode 0: 32-bit Counter"] + #[inline(always)] + pub fn count32(self) -> &'a mut W { + self.variant(MODE_A::COUNT32) + } + #[doc = "Mode 1: 16-bit Counter"] + #[inline(always)] + pub fn count16(self) -> &'a mut W { + self.variant(MODE_A::COUNT16) + } + #[doc = "Mode 2: Clock/Calendar"] + #[inline(always)] + pub fn clock(self) -> &'a mut W { + self.variant(MODE_A::CLOCK) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u16 & 0x03) << 2); + self.w + } +} +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: CLK_RTC_CNT = GCLK_RTC/1"] + OFF = 0, + #[doc = "1: CLK_RTC_CNT = GCLK_RTC/1"] + DIV1 = 1, + #[doc = "2: CLK_RTC_CNT = GCLK_RTC/2"] + DIV2 = 2, + #[doc = "3: CLK_RTC_CNT = GCLK_RTC/4"] + DIV4 = 3, + #[doc = "4: CLK_RTC_CNT = GCLK_RTC/8"] + DIV8 = 4, + #[doc = "5: CLK_RTC_CNT = GCLK_RTC/16"] + DIV16 = 5, + #[doc = "6: CLK_RTC_CNT = GCLK_RTC/32"] + DIV32 = 6, + #[doc = "7: CLK_RTC_CNT = GCLK_RTC/64"] + DIV64 = 7, + #[doc = "8: CLK_RTC_CNT = GCLK_RTC/128"] + DIV128 = 8, + #[doc = "9: CLK_RTC_CNT = GCLK_RTC/256"] + DIV256 = 9, + #[doc = "10: CLK_RTC_CNT = GCLK_RTC/512"] + DIV512 = 10, + #[doc = "11: CLK_RTC_CNT = GCLK_RTC/1024"] + DIV1024 = 11, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCALER_A::OFF), + 1 => Some(PRESCALER_A::DIV1), + 2 => Some(PRESCALER_A::DIV2), + 3 => Some(PRESCALER_A::DIV4), + 4 => Some(PRESCALER_A::DIV8), + 5 => Some(PRESCALER_A::DIV16), + 6 => Some(PRESCALER_A::DIV32), + 7 => Some(PRESCALER_A::DIV64), + 8 => Some(PRESCALER_A::DIV128), + 9 => Some(PRESCALER_A::DIV256), + 10 => Some(PRESCALER_A::DIV512), + 11 => Some(PRESCALER_A::DIV1024), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == PRESCALER_A::OFF + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == PRESCALER_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == PRESCALER_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == PRESCALER_A::DIV128 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV512`"] + #[inline(always)] + pub fn is_div512(&self) -> bool { + **self == PRESCALER_A::DIV512 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PRESCALER_A::DIV1024 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(PRESCALER_A::OFF) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV32) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV128) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/512"] + #[inline(always)] + pub fn div512(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV512) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 8)) | ((value as u16 & 0x0f) << 8); + self.w + } +} +#[doc = "Field `COUNTSYNC` reader - Count Read Synchronization Enable"] +pub struct COUNTSYNC_R(crate::FieldReader); +impl COUNTSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNTSYNC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNTSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNTSYNC` writer - Count Read Synchronization Enable"] +pub struct COUNTSYNC_W<'a> { + w: &'a mut W, +} +impl<'a> COUNTSYNC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:3 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bits 8:11 - Prescaler"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 15 - Count Read Synchronization Enable"] + #[inline(always)] + pub fn countsync(&self) -> COUNTSYNC_R { + COUNTSYNC_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:3 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bits 8:11 - Prescaler"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Bit 15 - Count Read Synchronization Enable"] + #[inline(always)] + pub fn countsync(&mut self) -> COUNTSYNC_W { + COUNTSYNC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/rtc/mode1/dbgctrl.rs b/pac/atsamc21j/src/rtc/mode1/dbgctrl.rs new file mode 100644 index 000000000000..0383e70d0429 --- /dev/null +++ b/pac/atsamc21j/src/rtc/mode1/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Run During Debug"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Run During Debug"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/rtc/mode1/evctrl.rs b/pac/atsamc21j/src/rtc/mode1/evctrl.rs new file mode 100644 index 000000000000..e15624f828c7 --- /dev/null +++ b/pac/atsamc21j/src/rtc/mode1/evctrl.rs @@ -0,0 +1,583 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PEREO0` reader - Periodic Interval 0 Event Output Enable"] +pub struct PEREO0_R(crate::FieldReader); +impl PEREO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO0` writer - Periodic Interval 0 Event Output Enable"] +pub struct PEREO0_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `PEREO1` reader - Periodic Interval 1 Event Output Enable"] +pub struct PEREO1_R(crate::FieldReader); +impl PEREO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO1` writer - Periodic Interval 1 Event Output Enable"] +pub struct PEREO1_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PEREO2` reader - Periodic Interval 2 Event Output Enable"] +pub struct PEREO2_R(crate::FieldReader); +impl PEREO2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO2` writer - Periodic Interval 2 Event Output Enable"] +pub struct PEREO2_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PEREO3` reader - Periodic Interval 3 Event Output Enable"] +pub struct PEREO3_R(crate::FieldReader); +impl PEREO3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO3` writer - Periodic Interval 3 Event Output Enable"] +pub struct PEREO3_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PEREO4` reader - Periodic Interval 4 Event Output Enable"] +pub struct PEREO4_R(crate::FieldReader); +impl PEREO4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO4` writer - Periodic Interval 4 Event Output Enable"] +pub struct PEREO4_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PEREO5` reader - Periodic Interval 5 Event Output Enable"] +pub struct PEREO5_R(crate::FieldReader); +impl PEREO5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO5` writer - Periodic Interval 5 Event Output Enable"] +pub struct PEREO5_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PEREO6` reader - Periodic Interval 6 Event Output Enable"] +pub struct PEREO6_R(crate::FieldReader); +impl PEREO6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO6` writer - Periodic Interval 6 Event Output Enable"] +pub struct PEREO6_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PEREO7` reader - Periodic Interval 7 Event Output Enable"] +pub struct PEREO7_R(crate::FieldReader); +impl PEREO7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO7` writer - Periodic Interval 7 Event Output Enable"] +pub struct PEREO7_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CMPEO0` reader - Compare 0 Event Output Enable"] +pub struct CMPEO0_R(crate::FieldReader); +impl CMPEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMPEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMPEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMPEO0` writer - Compare 0 Event Output Enable"] +pub struct CMPEO0_W<'a> { + w: &'a mut W, +} +impl<'a> CMPEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `CMPEO1` reader - Compare 1 Event Output Enable"] +pub struct CMPEO1_R(crate::FieldReader); +impl CMPEO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMPEO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMPEO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMPEO1` writer - Compare 1 Event Output Enable"] +pub struct CMPEO1_W<'a> { + w: &'a mut W, +} +impl<'a> CMPEO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `OVFEO` reader - Overflow Event Output Enable"] +pub struct OVFEO_R(crate::FieldReader); +impl OVFEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVFEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVFEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVFEO` writer - Overflow Event Output Enable"] +pub struct OVFEO_W<'a> { + w: &'a mut W, +} +impl<'a> OVFEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Event Output Enable"] + #[inline(always)] + pub fn pereo0(&self) -> PEREO0_R { + PEREO0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Event Output Enable"] + #[inline(always)] + pub fn pereo1(&self) -> PEREO1_R { + PEREO1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Event Output Enable"] + #[inline(always)] + pub fn pereo2(&self) -> PEREO2_R { + PEREO2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Event Output Enable"] + #[inline(always)] + pub fn pereo3(&self) -> PEREO3_R { + PEREO3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Event Output Enable"] + #[inline(always)] + pub fn pereo4(&self) -> PEREO4_R { + PEREO4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Event Output Enable"] + #[inline(always)] + pub fn pereo5(&self) -> PEREO5_R { + PEREO5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Event Output Enable"] + #[inline(always)] + pub fn pereo6(&self) -> PEREO6_R { + PEREO6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Event Output Enable"] + #[inline(always)] + pub fn pereo7(&self) -> PEREO7_R { + PEREO7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Compare 0 Event Output Enable"] + #[inline(always)] + pub fn cmpeo0(&self) -> CMPEO0_R { + CMPEO0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Compare 1 Event Output Enable"] + #[inline(always)] + pub fn cmpeo1(&self) -> CMPEO1_R { + CMPEO1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&self) -> OVFEO_R { + OVFEO_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Event Output Enable"] + #[inline(always)] + pub fn pereo0(&mut self) -> PEREO0_W { + PEREO0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1 Event Output Enable"] + #[inline(always)] + pub fn pereo1(&mut self) -> PEREO1_W { + PEREO1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2 Event Output Enable"] + #[inline(always)] + pub fn pereo2(&mut self) -> PEREO2_W { + PEREO2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3 Event Output Enable"] + #[inline(always)] + pub fn pereo3(&mut self) -> PEREO3_W { + PEREO3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4 Event Output Enable"] + #[inline(always)] + pub fn pereo4(&mut self) -> PEREO4_W { + PEREO4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5 Event Output Enable"] + #[inline(always)] + pub fn pereo5(&mut self) -> PEREO5_W { + PEREO5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6 Event Output Enable"] + #[inline(always)] + pub fn pereo6(&mut self) -> PEREO6_W { + PEREO6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7 Event Output Enable"] + #[inline(always)] + pub fn pereo7(&mut self) -> PEREO7_W { + PEREO7_W { w: self } + } + #[doc = "Bit 8 - Compare 0 Event Output Enable"] + #[inline(always)] + pub fn cmpeo0(&mut self) -> CMPEO0_W { + CMPEO0_W { w: self } + } + #[doc = "Bit 9 - Compare 1 Event Output Enable"] + #[inline(always)] + pub fn cmpeo1(&mut self) -> CMPEO1_W { + CMPEO1_W { w: self } + } + #[doc = "Bit 15 - Overflow Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&mut self) -> OVFEO_W { + OVFEO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/rtc/mode1/freqcorr.rs b/pac/atsamc21j/src/rtc/mode1/freqcorr.rs new file mode 100644 index 000000000000..043ba6f88eb2 --- /dev/null +++ b/pac/atsamc21j/src/rtc/mode1/freqcorr.rs @@ -0,0 +1,150 @@ +#[doc = "Register `FREQCORR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FREQCORR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `VALUE` reader - Correction Value"] +pub struct VALUE_R(crate::FieldReader); +impl VALUE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + VALUE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VALUE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VALUE` writer - Correction Value"] +pub struct VALUE_W<'a> { + w: &'a mut W, +} +impl<'a> VALUE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x7f) | (value as u8 & 0x7f); + self.w + } +} +#[doc = "Field `SIGN` reader - Correction Sign"] +pub struct SIGN_R(crate::FieldReader); +impl SIGN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SIGN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SIGN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SIGN` writer - Correction Sign"] +pub struct SIGN_W<'a> { + w: &'a mut W, +} +impl<'a> SIGN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bits 0:6 - Correction Value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bit 7 - Correction Sign"] + #[inline(always)] + pub fn sign(&self) -> SIGN_R { + SIGN_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:6 - Correction Value"] + #[inline(always)] + pub fn value(&mut self) -> VALUE_W { + VALUE_W { w: self } + } + #[doc = "Bit 7 - Correction Sign"] + #[inline(always)] + pub fn sign(&mut self) -> SIGN_W { + SIGN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Frequency Correction\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [freqcorr](index.html) module"] +pub struct FREQCORR_SPEC; +impl crate::RegisterSpec for FREQCORR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [freqcorr::R](R) reader structure"] +impl crate::Readable for FREQCORR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [freqcorr::W](W) writer structure"] +impl crate::Writable for FREQCORR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets FREQCORR to value 0"] +impl crate::Resettable for FREQCORR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/rtc/mode1/intenclr.rs b/pac/atsamc21j/src/rtc/mode1/intenclr.rs new file mode 100644 index 000000000000..d3fc5b3df34b --- /dev/null +++ b/pac/atsamc21j/src/rtc/mode1/intenclr.rs @@ -0,0 +1,583 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER0` reader - Periodic Interval 0 Interrupt Enable"] +pub struct PER0_R(crate::FieldReader); +impl PER0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER0` writer - Periodic Interval 0 Interrupt Enable"] +pub struct PER0_W<'a> { + w: &'a mut W, +} +impl<'a> PER0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PER1` reader - Periodic Interval 1 Interrupt Enable"] +pub struct PER1_R(crate::FieldReader); +impl PER1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER1` writer - Periodic Interval 1 Interrupt Enable"] +pub struct PER1_W<'a> { + w: &'a mut W, +} +impl<'a> PER1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PER2` reader - Periodic Interval 2 Interrupt Enable"] +pub struct PER2_R(crate::FieldReader); +impl PER2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER2` writer - Periodic Interval 2 Interrupt Enable"] +pub struct PER2_W<'a> { + w: &'a mut W, +} +impl<'a> PER2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PER3` reader - Periodic Interval 3 Interrupt Enable"] +pub struct PER3_R(crate::FieldReader); +impl PER3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER3` writer - Periodic Interval 3 Interrupt Enable"] +pub struct PER3_W<'a> { + w: &'a mut W, +} +impl<'a> PER3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PER4` reader - Periodic Interval 4 Interrupt Enable"] +pub struct PER4_R(crate::FieldReader); +impl PER4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER4` writer - Periodic Interval 4 Interrupt Enable"] +pub struct PER4_W<'a> { + w: &'a mut W, +} +impl<'a> PER4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PER5` reader - Periodic Interval 5 Interrupt Enable"] +pub struct PER5_R(crate::FieldReader); +impl PER5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER5` writer - Periodic Interval 5 Interrupt Enable"] +pub struct PER5_W<'a> { + w: &'a mut W, +} +impl<'a> PER5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PER6` reader - Periodic Interval 6 Interrupt Enable"] +pub struct PER6_R(crate::FieldReader); +impl PER6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER6` writer - Periodic Interval 6 Interrupt Enable"] +pub struct PER6_W<'a> { + w: &'a mut W, +} +impl<'a> PER6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PER7` reader - Periodic Interval 7 Interrupt Enable"] +pub struct PER7_R(crate::FieldReader); +impl PER7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER7` writer - Periodic Interval 7 Interrupt Enable"] +pub struct PER7_W<'a> { + w: &'a mut W, +} +impl<'a> PER7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CMP0` reader - Compare 0 Interrupt Enable"] +pub struct CMP0_R(crate::FieldReader); +impl CMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP0` writer - Compare 0 Interrupt Enable"] +pub struct CMP0_W<'a> { + w: &'a mut W, +} +impl<'a> CMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `CMP1` reader - Compare 1 Interrupt Enable"] +pub struct CMP1_R(crate::FieldReader); +impl CMP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP1` writer - Compare 1 Interrupt Enable"] +pub struct CMP1_W<'a> { + w: &'a mut W, +} +impl<'a> CMP1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + pub fn per0(&self) -> PER0_R { + PER0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + pub fn per1(&self) -> PER1_R { + PER1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + pub fn per2(&self) -> PER2_R { + PER2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + pub fn per3(&self) -> PER3_R { + PER3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + pub fn per4(&self) -> PER4_R { + PER4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + pub fn per5(&self) -> PER5_R { + PER5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + pub fn per6(&self) -> PER6_R { + PER6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + pub fn per7(&self) -> PER7_R { + PER7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&self) -> CMP0_R { + CMP0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Compare 1 Interrupt Enable"] + #[inline(always)] + pub fn cmp1(&self) -> CMP1_R { + CMP1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + pub fn per0(&mut self) -> PER0_W { + PER0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + pub fn per1(&mut self) -> PER1_W { + PER1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + pub fn per2(&mut self) -> PER2_W { + PER2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + pub fn per3(&mut self) -> PER3_W { + PER3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + pub fn per4(&mut self) -> PER4_W { + PER4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + pub fn per5(&mut self) -> PER5_W { + PER5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + pub fn per6(&mut self) -> PER6_W { + PER6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + pub fn per7(&mut self) -> PER7_W { + PER7_W { w: self } + } + #[doc = "Bit 8 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&mut self) -> CMP0_W { + CMP0_W { w: self } + } + #[doc = "Bit 9 - Compare 1 Interrupt Enable"] + #[inline(always)] + pub fn cmp1(&mut self) -> CMP1_W { + CMP1_W { w: self } + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/rtc/mode1/intenset.rs b/pac/atsamc21j/src/rtc/mode1/intenset.rs new file mode 100644 index 000000000000..074cb377926a --- /dev/null +++ b/pac/atsamc21j/src/rtc/mode1/intenset.rs @@ -0,0 +1,583 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER0` reader - Periodic Interval 0 Interrupt Enable"] +pub struct PER0_R(crate::FieldReader); +impl PER0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER0` writer - Periodic Interval 0 Interrupt Enable"] +pub struct PER0_W<'a> { + w: &'a mut W, +} +impl<'a> PER0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PER1` reader - Periodic Interval 1 Interrupt Enable"] +pub struct PER1_R(crate::FieldReader); +impl PER1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER1` writer - Periodic Interval 1 Interrupt Enable"] +pub struct PER1_W<'a> { + w: &'a mut W, +} +impl<'a> PER1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PER2` reader - Periodic Interval 2 Interrupt Enable"] +pub struct PER2_R(crate::FieldReader); +impl PER2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER2` writer - Periodic Interval 2 Interrupt Enable"] +pub struct PER2_W<'a> { + w: &'a mut W, +} +impl<'a> PER2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PER3` reader - Periodic Interval 3 Interrupt Enable"] +pub struct PER3_R(crate::FieldReader); +impl PER3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER3` writer - Periodic Interval 3 Interrupt Enable"] +pub struct PER3_W<'a> { + w: &'a mut W, +} +impl<'a> PER3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PER4` reader - Periodic Interval 4 Interrupt Enable"] +pub struct PER4_R(crate::FieldReader); +impl PER4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER4` writer - Periodic Interval 4 Interrupt Enable"] +pub struct PER4_W<'a> { + w: &'a mut W, +} +impl<'a> PER4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PER5` reader - Periodic Interval 5 Interrupt Enable"] +pub struct PER5_R(crate::FieldReader); +impl PER5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER5` writer - Periodic Interval 5 Interrupt Enable"] +pub struct PER5_W<'a> { + w: &'a mut W, +} +impl<'a> PER5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PER6` reader - Periodic Interval 6 Interrupt Enable"] +pub struct PER6_R(crate::FieldReader); +impl PER6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER6` writer - Periodic Interval 6 Interrupt Enable"] +pub struct PER6_W<'a> { + w: &'a mut W, +} +impl<'a> PER6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PER7` reader - Periodic Interval 7 Interrupt Enable"] +pub struct PER7_R(crate::FieldReader); +impl PER7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER7` writer - Periodic Interval 7 Interrupt Enable"] +pub struct PER7_W<'a> { + w: &'a mut W, +} +impl<'a> PER7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CMP0` reader - Compare 0 Interrupt Enable"] +pub struct CMP0_R(crate::FieldReader); +impl CMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP0` writer - Compare 0 Interrupt Enable"] +pub struct CMP0_W<'a> { + w: &'a mut W, +} +impl<'a> CMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `CMP1` reader - Compare 1 Interrupt Enable"] +pub struct CMP1_R(crate::FieldReader); +impl CMP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP1` writer - Compare 1 Interrupt Enable"] +pub struct CMP1_W<'a> { + w: &'a mut W, +} +impl<'a> CMP1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + pub fn per0(&self) -> PER0_R { + PER0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + pub fn per1(&self) -> PER1_R { + PER1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + pub fn per2(&self) -> PER2_R { + PER2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + pub fn per3(&self) -> PER3_R { + PER3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + pub fn per4(&self) -> PER4_R { + PER4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + pub fn per5(&self) -> PER5_R { + PER5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + pub fn per6(&self) -> PER6_R { + PER6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + pub fn per7(&self) -> PER7_R { + PER7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&self) -> CMP0_R { + CMP0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Compare 1 Interrupt Enable"] + #[inline(always)] + pub fn cmp1(&self) -> CMP1_R { + CMP1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + pub fn per0(&mut self) -> PER0_W { + PER0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + pub fn per1(&mut self) -> PER1_W { + PER1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + pub fn per2(&mut self) -> PER2_W { + PER2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + pub fn per3(&mut self) -> PER3_W { + PER3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + pub fn per4(&mut self) -> PER4_W { + PER4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + pub fn per5(&mut self) -> PER5_W { + PER5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + pub fn per6(&mut self) -> PER6_W { + PER6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + pub fn per7(&mut self) -> PER7_W { + PER7_W { w: self } + } + #[doc = "Bit 8 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&mut self) -> CMP0_W { + CMP0_W { w: self } + } + #[doc = "Bit 9 - Compare 1 Interrupt Enable"] + #[inline(always)] + pub fn cmp1(&mut self) -> CMP1_W { + CMP1_W { w: self } + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/rtc/mode1/intflag.rs b/pac/atsamc21j/src/rtc/mode1/intflag.rs new file mode 100644 index 000000000000..25bce956f46b --- /dev/null +++ b/pac/atsamc21j/src/rtc/mode1/intflag.rs @@ -0,0 +1,583 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER0` reader - Periodic Interval 0"] +pub struct PER0_R(crate::FieldReader); +impl PER0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER0` writer - Periodic Interval 0"] +pub struct PER0_W<'a> { + w: &'a mut W, +} +impl<'a> PER0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PER1` reader - Periodic Interval 1"] +pub struct PER1_R(crate::FieldReader); +impl PER1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER1` writer - Periodic Interval 1"] +pub struct PER1_W<'a> { + w: &'a mut W, +} +impl<'a> PER1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PER2` reader - Periodic Interval 2"] +pub struct PER2_R(crate::FieldReader); +impl PER2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER2` writer - Periodic Interval 2"] +pub struct PER2_W<'a> { + w: &'a mut W, +} +impl<'a> PER2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PER3` reader - Periodic Interval 3"] +pub struct PER3_R(crate::FieldReader); +impl PER3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER3` writer - Periodic Interval 3"] +pub struct PER3_W<'a> { + w: &'a mut W, +} +impl<'a> PER3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PER4` reader - Periodic Interval 4"] +pub struct PER4_R(crate::FieldReader); +impl PER4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER4` writer - Periodic Interval 4"] +pub struct PER4_W<'a> { + w: &'a mut W, +} +impl<'a> PER4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PER5` reader - Periodic Interval 5"] +pub struct PER5_R(crate::FieldReader); +impl PER5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER5` writer - Periodic Interval 5"] +pub struct PER5_W<'a> { + w: &'a mut W, +} +impl<'a> PER5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PER6` reader - Periodic Interval 6"] +pub struct PER6_R(crate::FieldReader); +impl PER6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER6` writer - Periodic Interval 6"] +pub struct PER6_W<'a> { + w: &'a mut W, +} +impl<'a> PER6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PER7` reader - Periodic Interval 7"] +pub struct PER7_R(crate::FieldReader); +impl PER7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER7` writer - Periodic Interval 7"] +pub struct PER7_W<'a> { + w: &'a mut W, +} +impl<'a> PER7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CMP0` reader - Compare 0"] +pub struct CMP0_R(crate::FieldReader); +impl CMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP0` writer - Compare 0"] +pub struct CMP0_W<'a> { + w: &'a mut W, +} +impl<'a> CMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `CMP1` reader - Compare 1"] +pub struct CMP1_R(crate::FieldReader); +impl CMP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP1` writer - Compare 1"] +pub struct CMP1_W<'a> { + w: &'a mut W, +} +impl<'a> CMP1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0"] + #[inline(always)] + pub fn per0(&self) -> PER0_R { + PER0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1"] + #[inline(always)] + pub fn per1(&self) -> PER1_R { + PER1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2"] + #[inline(always)] + pub fn per2(&self) -> PER2_R { + PER2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3"] + #[inline(always)] + pub fn per3(&self) -> PER3_R { + PER3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4"] + #[inline(always)] + pub fn per4(&self) -> PER4_R { + PER4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5"] + #[inline(always)] + pub fn per5(&self) -> PER5_R { + PER5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6"] + #[inline(always)] + pub fn per6(&self) -> PER6_R { + PER6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7"] + #[inline(always)] + pub fn per7(&self) -> PER7_R { + PER7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Compare 0"] + #[inline(always)] + pub fn cmp0(&self) -> CMP0_R { + CMP0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Compare 1"] + #[inline(always)] + pub fn cmp1(&self) -> CMP1_R { + CMP1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0"] + #[inline(always)] + pub fn per0(&mut self) -> PER0_W { + PER0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1"] + #[inline(always)] + pub fn per1(&mut self) -> PER1_W { + PER1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2"] + #[inline(always)] + pub fn per2(&mut self) -> PER2_W { + PER2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3"] + #[inline(always)] + pub fn per3(&mut self) -> PER3_W { + PER3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4"] + #[inline(always)] + pub fn per4(&mut self) -> PER4_W { + PER4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5"] + #[inline(always)] + pub fn per5(&mut self) -> PER5_W { + PER5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6"] + #[inline(always)] + pub fn per6(&mut self) -> PER6_W { + PER6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7"] + #[inline(always)] + pub fn per7(&mut self) -> PER7_W { + PER7_W { w: self } + } + #[doc = "Bit 8 - Compare 0"] + #[inline(always)] + pub fn cmp0(&mut self) -> CMP0_W { + CMP0_W { w: self } + } + #[doc = "Bit 9 - Compare 1"] + #[inline(always)] + pub fn cmp1(&mut self) -> CMP1_W { + CMP1_W { w: self } + } + #[doc = "Bit 15 - Overflow"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/rtc/mode1/per.rs b/pac/atsamc21j/src/rtc/mode1/per.rs new file mode 100644 index 000000000000..c09b31fa30dd --- /dev/null +++ b/pac/atsamc21j/src/rtc/mode1/per.rs @@ -0,0 +1,103 @@ +#[doc = "Register `PER` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PER` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER` reader - Counter Period"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` writer - Counter Period"] +pub struct PER_W<'a> { + w: &'a mut W, +} +impl<'a> PER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Counter Period"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Counter Period"] + #[inline(always)] + pub fn per(&mut self) -> PER_W { + PER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Counter Period\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [per](index.html) module"] +pub struct PER_SPEC; +impl crate::RegisterSpec for PER_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [per::R](R) reader structure"] +impl crate::Readable for PER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [per::W](W) writer structure"] +impl crate::Writable for PER_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PER to value 0"] +impl crate::Resettable for PER_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/rtc/mode1/syncbusy.rs b/pac/atsamc21j/src/rtc/mode1/syncbusy.rs new file mode 100644 index 000000000000..b64c973bafff --- /dev/null +++ b/pac/atsamc21j/src/rtc/mode1/syncbusy.rs @@ -0,0 +1,193 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Bit Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - Enable Bit Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FREQCORR` reader - FREQCORR Register Busy"] +pub struct FREQCORR_R(crate::FieldReader); +impl FREQCORR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FREQCORR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FREQCORR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` reader - COUNT Register Busy"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` reader - PER Register Busy"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP0` reader - COMP 0 Register Busy"] +pub struct COMP0_R(crate::FieldReader); +impl COMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP1` reader - COMP 1 Register Busy"] +pub struct COMP1_R(crate::FieldReader); +impl COMP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNTSYNC` reader - Count Read Synchronization Enable Bit Busy"] +pub struct COUNTSYNC_R(crate::FieldReader); +impl COUNTSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNTSYNC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNTSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Bit Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable Bit Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - FREQCORR Register Busy"] + #[inline(always)] + pub fn freqcorr(&self) -> FREQCORR_R { + FREQCORR_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - COUNT Register Busy"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - PER Register Busy"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - COMP 0 Register Busy"] + #[inline(always)] + pub fn comp0(&self) -> COMP0_R { + COMP0_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - COMP 1 Register Busy"] + #[inline(always)] + pub fn comp1(&self) -> COMP1_R { + COMP1_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 15 - Count Read Synchronization Enable Bit Busy"] + #[inline(always)] + pub fn countsync(&self) -> COUNTSYNC_R { + COUNTSYNC_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +#[doc = "MODE1 Synchronization Busy Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/rtc/mode2.rs b/pac/atsamc21j/src/rtc/mode2.rs new file mode 100644 index 000000000000..b0bc13e81dbc --- /dev/null +++ b/pac/atsamc21j/src/rtc/mode2.rs @@ -0,0 +1,44 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "MODE2 Control A"] +pub mod ctrla; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "MODE2 Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "MODE2 Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "MODE2 Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "MODE2 Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "MODE2 Synchronization Busy Status"] +pub mod syncbusy; +#[doc = "FREQCORR register accessor: an alias for `Reg`"] +pub type FREQCORR = crate::Reg; +#[doc = "Frequency Correction"] +pub mod freqcorr; +#[doc = "CLOCK register accessor: an alias for `Reg`"] +pub type CLOCK = crate::Reg; +#[doc = "MODE2 Clock Value"] +pub mod clock; +#[doc = "ALARM register accessor: an alias for `Reg`"] +pub type ALARM = crate::Reg; +#[doc = "MODE2_ALARM Alarm n Value"] +pub mod alarm; +#[doc = "MASK register accessor: an alias for `Reg`"] +pub type MASK = crate::Reg; +#[doc = "MODE2_ALARM Alarm n Mask"] +pub mod mask; diff --git a/pac/atsamc21j/src/rtc/mode2/alarm.rs b/pac/atsamc21j/src/rtc/mode2/alarm.rs new file mode 100644 index 000000000000..1242477ea69f --- /dev/null +++ b/pac/atsamc21j/src/rtc/mode2/alarm.rs @@ -0,0 +1,337 @@ +#[doc = "Register `ALARM` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ALARM` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SECOND` reader - Second"] +pub struct SECOND_R(crate::FieldReader); +impl SECOND_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SECOND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SECOND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SECOND` writer - Second"] +pub struct SECOND_W<'a> { + w: &'a mut W, +} +impl<'a> SECOND_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +#[doc = "Field `MINUTE` reader - Minute"] +pub struct MINUTE_R(crate::FieldReader); +impl MINUTE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MINUTE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MINUTE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MINUTE` writer - Minute"] +pub struct MINUTE_W<'a> { + w: &'a mut W, +} +impl<'a> MINUTE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 6)) | ((value as u32 & 0x3f) << 6); + self.w + } +} +#[doc = "Hour\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum HOUR_A { + #[doc = "0: Morning hour"] + AM = 0, + #[doc = "16: Afternoon hour"] + PM = 16, +} +impl From for u8 { + #[inline(always)] + fn from(variant: HOUR_A) -> Self { + variant as _ + } +} +#[doc = "Field `HOUR` reader - Hour"] +pub struct HOUR_R(crate::FieldReader); +impl HOUR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + HOUR_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(HOUR_A::AM), + 16 => Some(HOUR_A::PM), + _ => None, + } + } + #[doc = "Checks if the value of the field is `AM`"] + #[inline(always)] + pub fn is_am(&self) -> bool { + **self == HOUR_A::AM + } + #[doc = "Checks if the value of the field is `PM`"] + #[inline(always)] + pub fn is_pm(&self) -> bool { + **self == HOUR_A::PM + } +} +impl core::ops::Deref for HOUR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HOUR` writer - Hour"] +pub struct HOUR_W<'a> { + w: &'a mut W, +} +impl<'a> HOUR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: HOUR_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Morning hour"] + #[inline(always)] + pub fn am(self) -> &'a mut W { + self.variant(HOUR_A::AM) + } + #[doc = "Afternoon hour"] + #[inline(always)] + pub fn pm(self) -> &'a mut W { + self.variant(HOUR_A::PM) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 12)) | ((value as u32 & 0x1f) << 12); + self.w + } +} +#[doc = "Field `DAY` reader - Day"] +pub struct DAY_R(crate::FieldReader); +impl DAY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DAY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DAY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DAY` writer - Day"] +pub struct DAY_W<'a> { + w: &'a mut W, +} +impl<'a> DAY_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 17)) | ((value as u32 & 0x1f) << 17); + self.w + } +} +#[doc = "Field `MONTH` reader - Month"] +pub struct MONTH_R(crate::FieldReader); +impl MONTH_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MONTH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MONTH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MONTH` writer - Month"] +pub struct MONTH_W<'a> { + w: &'a mut W, +} +impl<'a> MONTH_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 22)) | ((value as u32 & 0x0f) << 22); + self.w + } +} +#[doc = "Field `YEAR` reader - Year"] +pub struct YEAR_R(crate::FieldReader); +impl YEAR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + YEAR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for YEAR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `YEAR` writer - Year"] +pub struct YEAR_W<'a> { + w: &'a mut W, +} +impl<'a> YEAR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 26)) | ((value as u32 & 0x3f) << 26); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Second"] + #[inline(always)] + pub fn second(&self) -> SECOND_R { + SECOND_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:11 - Minute"] + #[inline(always)] + pub fn minute(&self) -> MINUTE_R { + MINUTE_R::new(((self.bits >> 6) & 0x3f) as u8) + } + #[doc = "Bits 12:16 - Hour"] + #[inline(always)] + pub fn hour(&self) -> HOUR_R { + HOUR_R::new(((self.bits >> 12) & 0x1f) as u8) + } + #[doc = "Bits 17:21 - Day"] + #[inline(always)] + pub fn day(&self) -> DAY_R { + DAY_R::new(((self.bits >> 17) & 0x1f) as u8) + } + #[doc = "Bits 22:25 - Month"] + #[inline(always)] + pub fn month(&self) -> MONTH_R { + MONTH_R::new(((self.bits >> 22) & 0x0f) as u8) + } + #[doc = "Bits 26:31 - Year"] + #[inline(always)] + pub fn year(&self) -> YEAR_R { + YEAR_R::new(((self.bits >> 26) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - Second"] + #[inline(always)] + pub fn second(&mut self) -> SECOND_W { + SECOND_W { w: self } + } + #[doc = "Bits 6:11 - Minute"] + #[inline(always)] + pub fn minute(&mut self) -> MINUTE_W { + MINUTE_W { w: self } + } + #[doc = "Bits 12:16 - Hour"] + #[inline(always)] + pub fn hour(&mut self) -> HOUR_W { + HOUR_W { w: self } + } + #[doc = "Bits 17:21 - Day"] + #[inline(always)] + pub fn day(&mut self) -> DAY_W { + DAY_W { w: self } + } + #[doc = "Bits 22:25 - Month"] + #[inline(always)] + pub fn month(&mut self) -> MONTH_W { + MONTH_W { w: self } + } + #[doc = "Bits 26:31 - Year"] + #[inline(always)] + pub fn year(&mut self) -> YEAR_W { + YEAR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2_ALARM Alarm n Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [alarm](index.html) module"] +pub struct ALARM_SPEC; +impl crate::RegisterSpec for ALARM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [alarm::R](R) reader structure"] +impl crate::Readable for ALARM_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [alarm::W](W) writer structure"] +impl crate::Writable for ALARM_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ALARM to value 0"] +impl crate::Resettable for ALARM_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/rtc/mode2/clock.rs b/pac/atsamc21j/src/rtc/mode2/clock.rs new file mode 100644 index 000000000000..3f364ff8e57b --- /dev/null +++ b/pac/atsamc21j/src/rtc/mode2/clock.rs @@ -0,0 +1,337 @@ +#[doc = "Register `CLOCK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CLOCK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SECOND` reader - Second"] +pub struct SECOND_R(crate::FieldReader); +impl SECOND_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SECOND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SECOND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SECOND` writer - Second"] +pub struct SECOND_W<'a> { + w: &'a mut W, +} +impl<'a> SECOND_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +#[doc = "Field `MINUTE` reader - Minute"] +pub struct MINUTE_R(crate::FieldReader); +impl MINUTE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MINUTE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MINUTE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MINUTE` writer - Minute"] +pub struct MINUTE_W<'a> { + w: &'a mut W, +} +impl<'a> MINUTE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 6)) | ((value as u32 & 0x3f) << 6); + self.w + } +} +#[doc = "Hour\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum HOUR_A { + #[doc = "0: AM when CLKREP in 12-hour"] + AM = 0, + #[doc = "16: PM when CLKREP in 12-hour"] + PM = 16, +} +impl From for u8 { + #[inline(always)] + fn from(variant: HOUR_A) -> Self { + variant as _ + } +} +#[doc = "Field `HOUR` reader - Hour"] +pub struct HOUR_R(crate::FieldReader); +impl HOUR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + HOUR_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(HOUR_A::AM), + 16 => Some(HOUR_A::PM), + _ => None, + } + } + #[doc = "Checks if the value of the field is `AM`"] + #[inline(always)] + pub fn is_am(&self) -> bool { + **self == HOUR_A::AM + } + #[doc = "Checks if the value of the field is `PM`"] + #[inline(always)] + pub fn is_pm(&self) -> bool { + **self == HOUR_A::PM + } +} +impl core::ops::Deref for HOUR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HOUR` writer - Hour"] +pub struct HOUR_W<'a> { + w: &'a mut W, +} +impl<'a> HOUR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: HOUR_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "AM when CLKREP in 12-hour"] + #[inline(always)] + pub fn am(self) -> &'a mut W { + self.variant(HOUR_A::AM) + } + #[doc = "PM when CLKREP in 12-hour"] + #[inline(always)] + pub fn pm(self) -> &'a mut W { + self.variant(HOUR_A::PM) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 12)) | ((value as u32 & 0x1f) << 12); + self.w + } +} +#[doc = "Field `DAY` reader - Day"] +pub struct DAY_R(crate::FieldReader); +impl DAY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DAY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DAY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DAY` writer - Day"] +pub struct DAY_W<'a> { + w: &'a mut W, +} +impl<'a> DAY_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 17)) | ((value as u32 & 0x1f) << 17); + self.w + } +} +#[doc = "Field `MONTH` reader - Month"] +pub struct MONTH_R(crate::FieldReader); +impl MONTH_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MONTH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MONTH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MONTH` writer - Month"] +pub struct MONTH_W<'a> { + w: &'a mut W, +} +impl<'a> MONTH_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 22)) | ((value as u32 & 0x0f) << 22); + self.w + } +} +#[doc = "Field `YEAR` reader - Year"] +pub struct YEAR_R(crate::FieldReader); +impl YEAR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + YEAR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for YEAR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `YEAR` writer - Year"] +pub struct YEAR_W<'a> { + w: &'a mut W, +} +impl<'a> YEAR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 26)) | ((value as u32 & 0x3f) << 26); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Second"] + #[inline(always)] + pub fn second(&self) -> SECOND_R { + SECOND_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:11 - Minute"] + #[inline(always)] + pub fn minute(&self) -> MINUTE_R { + MINUTE_R::new(((self.bits >> 6) & 0x3f) as u8) + } + #[doc = "Bits 12:16 - Hour"] + #[inline(always)] + pub fn hour(&self) -> HOUR_R { + HOUR_R::new(((self.bits >> 12) & 0x1f) as u8) + } + #[doc = "Bits 17:21 - Day"] + #[inline(always)] + pub fn day(&self) -> DAY_R { + DAY_R::new(((self.bits >> 17) & 0x1f) as u8) + } + #[doc = "Bits 22:25 - Month"] + #[inline(always)] + pub fn month(&self) -> MONTH_R { + MONTH_R::new(((self.bits >> 22) & 0x0f) as u8) + } + #[doc = "Bits 26:31 - Year"] + #[inline(always)] + pub fn year(&self) -> YEAR_R { + YEAR_R::new(((self.bits >> 26) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - Second"] + #[inline(always)] + pub fn second(&mut self) -> SECOND_W { + SECOND_W { w: self } + } + #[doc = "Bits 6:11 - Minute"] + #[inline(always)] + pub fn minute(&mut self) -> MINUTE_W { + MINUTE_W { w: self } + } + #[doc = "Bits 12:16 - Hour"] + #[inline(always)] + pub fn hour(&mut self) -> HOUR_W { + HOUR_W { w: self } + } + #[doc = "Bits 17:21 - Day"] + #[inline(always)] + pub fn day(&mut self) -> DAY_W { + DAY_W { w: self } + } + #[doc = "Bits 22:25 - Month"] + #[inline(always)] + pub fn month(&mut self) -> MONTH_W { + MONTH_W { w: self } + } + #[doc = "Bits 26:31 - Year"] + #[inline(always)] + pub fn year(&mut self) -> YEAR_W { + YEAR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2 Clock Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clock](index.html) module"] +pub struct CLOCK_SPEC; +impl crate::RegisterSpec for CLOCK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [clock::R](R) reader structure"] +impl crate::Readable for CLOCK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [clock::W](W) writer structure"] +impl crate::Writable for CLOCK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CLOCK to value 0"] +impl crate::Resettable for CLOCK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/rtc/mode2/ctrla.rs b/pac/atsamc21j/src/rtc/mode2/ctrla.rs new file mode 100644 index 000000000000..fc4bfda16bd8 --- /dev/null +++ b/pac/atsamc21j/src/rtc/mode2/ctrla.rs @@ -0,0 +1,616 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: Mode 0: 32-bit Counter"] + COUNT32 = 0, + #[doc = "1: Mode 1: 16-bit Counter"] + COUNT16 = 1, + #[doc = "2: Mode 2: Clock/Calendar"] + CLOCK = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::COUNT32), + 1 => Some(MODE_A::COUNT16), + 2 => Some(MODE_A::CLOCK), + _ => None, + } + } + #[doc = "Checks if the value of the field is `COUNT32`"] + #[inline(always)] + pub fn is_count32(&self) -> bool { + **self == MODE_A::COUNT32 + } + #[doc = "Checks if the value of the field is `COUNT16`"] + #[inline(always)] + pub fn is_count16(&self) -> bool { + **self == MODE_A::COUNT16 + } + #[doc = "Checks if the value of the field is `CLOCK`"] + #[inline(always)] + pub fn is_clock(&self) -> bool { + **self == MODE_A::CLOCK + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Mode 0: 32-bit Counter"] + #[inline(always)] + pub fn count32(self) -> &'a mut W { + self.variant(MODE_A::COUNT32) + } + #[doc = "Mode 1: 16-bit Counter"] + #[inline(always)] + pub fn count16(self) -> &'a mut W { + self.variant(MODE_A::COUNT16) + } + #[doc = "Mode 2: Clock/Calendar"] + #[inline(always)] + pub fn clock(self) -> &'a mut W { + self.variant(MODE_A::CLOCK) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u16 & 0x03) << 2); + self.w + } +} +#[doc = "Field `CLKREP` reader - Clock Representation"] +pub struct CLKREP_R(crate::FieldReader); +impl CLKREP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKREP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKREP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKREP` writer - Clock Representation"] +pub struct CLKREP_W<'a> { + w: &'a mut W, +} +impl<'a> CLKREP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `MATCHCLR` reader - Clear on Match"] +pub struct MATCHCLR_R(crate::FieldReader); +impl MATCHCLR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MATCHCLR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MATCHCLR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MATCHCLR` writer - Clear on Match"] +pub struct MATCHCLR_W<'a> { + w: &'a mut W, +} +impl<'a> MATCHCLR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: CLK_RTC_CNT = GCLK_RTC/1"] + OFF = 0, + #[doc = "1: CLK_RTC_CNT = GCLK_RTC/1"] + DIV1 = 1, + #[doc = "2: CLK_RTC_CNT = GCLK_RTC/2"] + DIV2 = 2, + #[doc = "3: CLK_RTC_CNT = GCLK_RTC/4"] + DIV4 = 3, + #[doc = "4: CLK_RTC_CNT = GCLK_RTC/8"] + DIV8 = 4, + #[doc = "5: CLK_RTC_CNT = GCLK_RTC/16"] + DIV16 = 5, + #[doc = "6: CLK_RTC_CNT = GCLK_RTC/32"] + DIV32 = 6, + #[doc = "7: CLK_RTC_CNT = GCLK_RTC/64"] + DIV64 = 7, + #[doc = "8: CLK_RTC_CNT = GCLK_RTC/128"] + DIV128 = 8, + #[doc = "9: CLK_RTC_CNT = GCLK_RTC/256"] + DIV256 = 9, + #[doc = "10: CLK_RTC_CNT = GCLK_RTC/512"] + DIV512 = 10, + #[doc = "11: CLK_RTC_CNT = GCLK_RTC/1024"] + DIV1024 = 11, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCALER_A::OFF), + 1 => Some(PRESCALER_A::DIV1), + 2 => Some(PRESCALER_A::DIV2), + 3 => Some(PRESCALER_A::DIV4), + 4 => Some(PRESCALER_A::DIV8), + 5 => Some(PRESCALER_A::DIV16), + 6 => Some(PRESCALER_A::DIV32), + 7 => Some(PRESCALER_A::DIV64), + 8 => Some(PRESCALER_A::DIV128), + 9 => Some(PRESCALER_A::DIV256), + 10 => Some(PRESCALER_A::DIV512), + 11 => Some(PRESCALER_A::DIV1024), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == PRESCALER_A::OFF + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == PRESCALER_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == PRESCALER_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == PRESCALER_A::DIV128 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV512`"] + #[inline(always)] + pub fn is_div512(&self) -> bool { + **self == PRESCALER_A::DIV512 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PRESCALER_A::DIV1024 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(PRESCALER_A::OFF) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV32) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV128) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/512"] + #[inline(always)] + pub fn div512(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV512) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 8)) | ((value as u16 & 0x0f) << 8); + self.w + } +} +#[doc = "Field `CLOCKSYNC` reader - Clock Read Synchronization Enable"] +pub struct CLOCKSYNC_R(crate::FieldReader); +impl CLOCKSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLOCKSYNC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLOCKSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLOCKSYNC` writer - Clock Read Synchronization Enable"] +pub struct CLOCKSYNC_W<'a> { + w: &'a mut W, +} +impl<'a> CLOCKSYNC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:3 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bit 6 - Clock Representation"] + #[inline(always)] + pub fn clkrep(&self) -> CLKREP_R { + CLKREP_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Clear on Match"] + #[inline(always)] + pub fn matchclr(&self) -> MATCHCLR_R { + MATCHCLR_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:11 - Prescaler"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 15 - Clock Read Synchronization Enable"] + #[inline(always)] + pub fn clocksync(&self) -> CLOCKSYNC_R { + CLOCKSYNC_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:3 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 6 - Clock Representation"] + #[inline(always)] + pub fn clkrep(&mut self) -> CLKREP_W { + CLKREP_W { w: self } + } + #[doc = "Bit 7 - Clear on Match"] + #[inline(always)] + pub fn matchclr(&mut self) -> MATCHCLR_W { + MATCHCLR_W { w: self } + } + #[doc = "Bits 8:11 - Prescaler"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Bit 15 - Clock Read Synchronization Enable"] + #[inline(always)] + pub fn clocksync(&mut self) -> CLOCKSYNC_W { + CLOCKSYNC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2 Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/rtc/mode2/dbgctrl.rs b/pac/atsamc21j/src/rtc/mode2/dbgctrl.rs new file mode 100644 index 000000000000..0383e70d0429 --- /dev/null +++ b/pac/atsamc21j/src/rtc/mode2/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Run During Debug"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Run During Debug"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/rtc/mode2/evctrl.rs b/pac/atsamc21j/src/rtc/mode2/evctrl.rs new file mode 100644 index 000000000000..17bc3da4a79e --- /dev/null +++ b/pac/atsamc21j/src/rtc/mode2/evctrl.rs @@ -0,0 +1,536 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PEREO0` reader - Periodic Interval 0 Event Output Enable"] +pub struct PEREO0_R(crate::FieldReader); +impl PEREO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO0` writer - Periodic Interval 0 Event Output Enable"] +pub struct PEREO0_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `PEREO1` reader - Periodic Interval 1 Event Output Enable"] +pub struct PEREO1_R(crate::FieldReader); +impl PEREO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO1` writer - Periodic Interval 1 Event Output Enable"] +pub struct PEREO1_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PEREO2` reader - Periodic Interval 2 Event Output Enable"] +pub struct PEREO2_R(crate::FieldReader); +impl PEREO2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO2` writer - Periodic Interval 2 Event Output Enable"] +pub struct PEREO2_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PEREO3` reader - Periodic Interval 3 Event Output Enable"] +pub struct PEREO3_R(crate::FieldReader); +impl PEREO3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO3` writer - Periodic Interval 3 Event Output Enable"] +pub struct PEREO3_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PEREO4` reader - Periodic Interval 4 Event Output Enable"] +pub struct PEREO4_R(crate::FieldReader); +impl PEREO4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO4` writer - Periodic Interval 4 Event Output Enable"] +pub struct PEREO4_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PEREO5` reader - Periodic Interval 5 Event Output Enable"] +pub struct PEREO5_R(crate::FieldReader); +impl PEREO5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO5` writer - Periodic Interval 5 Event Output Enable"] +pub struct PEREO5_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PEREO6` reader - Periodic Interval 6 Event Output Enable"] +pub struct PEREO6_R(crate::FieldReader); +impl PEREO6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO6` writer - Periodic Interval 6 Event Output Enable"] +pub struct PEREO6_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PEREO7` reader - Periodic Interval 7 Event Output Enable"] +pub struct PEREO7_R(crate::FieldReader); +impl PEREO7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO7` writer - Periodic Interval 7 Event Output Enable"] +pub struct PEREO7_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `ALARMEO0` reader - Alarm 0 Event Output Enable"] +pub struct ALARMEO0_R(crate::FieldReader); +impl ALARMEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALARMEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALARMEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALARMEO0` writer - Alarm 0 Event Output Enable"] +pub struct ALARMEO0_W<'a> { + w: &'a mut W, +} +impl<'a> ALARMEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `OVFEO` reader - Overflow Event Output Enable"] +pub struct OVFEO_R(crate::FieldReader); +impl OVFEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVFEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVFEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVFEO` writer - Overflow Event Output Enable"] +pub struct OVFEO_W<'a> { + w: &'a mut W, +} +impl<'a> OVFEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Event Output Enable"] + #[inline(always)] + pub fn pereo0(&self) -> PEREO0_R { + PEREO0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Event Output Enable"] + #[inline(always)] + pub fn pereo1(&self) -> PEREO1_R { + PEREO1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Event Output Enable"] + #[inline(always)] + pub fn pereo2(&self) -> PEREO2_R { + PEREO2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Event Output Enable"] + #[inline(always)] + pub fn pereo3(&self) -> PEREO3_R { + PEREO3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Event Output Enable"] + #[inline(always)] + pub fn pereo4(&self) -> PEREO4_R { + PEREO4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Event Output Enable"] + #[inline(always)] + pub fn pereo5(&self) -> PEREO5_R { + PEREO5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Event Output Enable"] + #[inline(always)] + pub fn pereo6(&self) -> PEREO6_R { + PEREO6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Event Output Enable"] + #[inline(always)] + pub fn pereo7(&self) -> PEREO7_R { + PEREO7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Alarm 0 Event Output Enable"] + #[inline(always)] + pub fn alarmeo0(&self) -> ALARMEO0_R { + ALARMEO0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&self) -> OVFEO_R { + OVFEO_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Event Output Enable"] + #[inline(always)] + pub fn pereo0(&mut self) -> PEREO0_W { + PEREO0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1 Event Output Enable"] + #[inline(always)] + pub fn pereo1(&mut self) -> PEREO1_W { + PEREO1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2 Event Output Enable"] + #[inline(always)] + pub fn pereo2(&mut self) -> PEREO2_W { + PEREO2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3 Event Output Enable"] + #[inline(always)] + pub fn pereo3(&mut self) -> PEREO3_W { + PEREO3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4 Event Output Enable"] + #[inline(always)] + pub fn pereo4(&mut self) -> PEREO4_W { + PEREO4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5 Event Output Enable"] + #[inline(always)] + pub fn pereo5(&mut self) -> PEREO5_W { + PEREO5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6 Event Output Enable"] + #[inline(always)] + pub fn pereo6(&mut self) -> PEREO6_W { + PEREO6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7 Event Output Enable"] + #[inline(always)] + pub fn pereo7(&mut self) -> PEREO7_W { + PEREO7_W { w: self } + } + #[doc = "Bit 8 - Alarm 0 Event Output Enable"] + #[inline(always)] + pub fn alarmeo0(&mut self) -> ALARMEO0_W { + ALARMEO0_W { w: self } + } + #[doc = "Bit 15 - Overflow Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&mut self) -> OVFEO_W { + OVFEO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2 Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/rtc/mode2/freqcorr.rs b/pac/atsamc21j/src/rtc/mode2/freqcorr.rs new file mode 100644 index 000000000000..043ba6f88eb2 --- /dev/null +++ b/pac/atsamc21j/src/rtc/mode2/freqcorr.rs @@ -0,0 +1,150 @@ +#[doc = "Register `FREQCORR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FREQCORR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `VALUE` reader - Correction Value"] +pub struct VALUE_R(crate::FieldReader); +impl VALUE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + VALUE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VALUE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VALUE` writer - Correction Value"] +pub struct VALUE_W<'a> { + w: &'a mut W, +} +impl<'a> VALUE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x7f) | (value as u8 & 0x7f); + self.w + } +} +#[doc = "Field `SIGN` reader - Correction Sign"] +pub struct SIGN_R(crate::FieldReader); +impl SIGN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SIGN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SIGN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SIGN` writer - Correction Sign"] +pub struct SIGN_W<'a> { + w: &'a mut W, +} +impl<'a> SIGN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bits 0:6 - Correction Value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bit 7 - Correction Sign"] + #[inline(always)] + pub fn sign(&self) -> SIGN_R { + SIGN_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:6 - Correction Value"] + #[inline(always)] + pub fn value(&mut self) -> VALUE_W { + VALUE_W { w: self } + } + #[doc = "Bit 7 - Correction Sign"] + #[inline(always)] + pub fn sign(&mut self) -> SIGN_W { + SIGN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Frequency Correction\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [freqcorr](index.html) module"] +pub struct FREQCORR_SPEC; +impl crate::RegisterSpec for FREQCORR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [freqcorr::R](R) reader structure"] +impl crate::Readable for FREQCORR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [freqcorr::W](W) writer structure"] +impl crate::Writable for FREQCORR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets FREQCORR to value 0"] +impl crate::Resettable for FREQCORR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/rtc/mode2/intenclr.rs b/pac/atsamc21j/src/rtc/mode2/intenclr.rs new file mode 100644 index 000000000000..84aa17f78a0e --- /dev/null +++ b/pac/atsamc21j/src/rtc/mode2/intenclr.rs @@ -0,0 +1,536 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER0` reader - Periodic Interval 0 Interrupt Enable"] +pub struct PER0_R(crate::FieldReader); +impl PER0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER0` writer - Periodic Interval 0 Interrupt Enable"] +pub struct PER0_W<'a> { + w: &'a mut W, +} +impl<'a> PER0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PER1` reader - Periodic Interval 1 Interrupt Enable"] +pub struct PER1_R(crate::FieldReader); +impl PER1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER1` writer - Periodic Interval 1 Interrupt Enable"] +pub struct PER1_W<'a> { + w: &'a mut W, +} +impl<'a> PER1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PER2` reader - Periodic Interval 2 Interrupt Enable"] +pub struct PER2_R(crate::FieldReader); +impl PER2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER2` writer - Periodic Interval 2 Interrupt Enable"] +pub struct PER2_W<'a> { + w: &'a mut W, +} +impl<'a> PER2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PER3` reader - Periodic Interval 3 Interrupt Enable"] +pub struct PER3_R(crate::FieldReader); +impl PER3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER3` writer - Periodic Interval 3 Interrupt Enable"] +pub struct PER3_W<'a> { + w: &'a mut W, +} +impl<'a> PER3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PER4` reader - Periodic Interval 4 Interrupt Enable"] +pub struct PER4_R(crate::FieldReader); +impl PER4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER4` writer - Periodic Interval 4 Interrupt Enable"] +pub struct PER4_W<'a> { + w: &'a mut W, +} +impl<'a> PER4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PER5` reader - Periodic Interval 5 Interrupt Enable"] +pub struct PER5_R(crate::FieldReader); +impl PER5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER5` writer - Periodic Interval 5 Interrupt Enable"] +pub struct PER5_W<'a> { + w: &'a mut W, +} +impl<'a> PER5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PER6` reader - Periodic Interval 6 Interrupt Enable"] +pub struct PER6_R(crate::FieldReader); +impl PER6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER6` writer - Periodic Interval 6 Interrupt Enable"] +pub struct PER6_W<'a> { + w: &'a mut W, +} +impl<'a> PER6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PER7` reader - Periodic Interval 7 Interrupt Enable"] +pub struct PER7_R(crate::FieldReader); +impl PER7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER7` writer - Periodic Interval 7 Interrupt Enable"] +pub struct PER7_W<'a> { + w: &'a mut W, +} +impl<'a> PER7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `ALARM0` reader - Alarm 0 Interrupt Enable"] +pub struct ALARM0_R(crate::FieldReader); +impl ALARM0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALARM0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALARM0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALARM0` writer - Alarm 0 Interrupt Enable"] +pub struct ALARM0_W<'a> { + w: &'a mut W, +} +impl<'a> ALARM0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + pub fn per0(&self) -> PER0_R { + PER0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + pub fn per1(&self) -> PER1_R { + PER1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + pub fn per2(&self) -> PER2_R { + PER2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + pub fn per3(&self) -> PER3_R { + PER3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + pub fn per4(&self) -> PER4_R { + PER4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + pub fn per5(&self) -> PER5_R { + PER5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + pub fn per6(&self) -> PER6_R { + PER6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + pub fn per7(&self) -> PER7_R { + PER7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Alarm 0 Interrupt Enable"] + #[inline(always)] + pub fn alarm0(&self) -> ALARM0_R { + ALARM0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + pub fn per0(&mut self) -> PER0_W { + PER0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + pub fn per1(&mut self) -> PER1_W { + PER1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + pub fn per2(&mut self) -> PER2_W { + PER2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + pub fn per3(&mut self) -> PER3_W { + PER3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + pub fn per4(&mut self) -> PER4_W { + PER4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + pub fn per5(&mut self) -> PER5_W { + PER5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + pub fn per6(&mut self) -> PER6_W { + PER6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + pub fn per7(&mut self) -> PER7_W { + PER7_W { w: self } + } + #[doc = "Bit 8 - Alarm 0 Interrupt Enable"] + #[inline(always)] + pub fn alarm0(&mut self) -> ALARM0_W { + ALARM0_W { w: self } + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2 Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/rtc/mode2/intenset.rs b/pac/atsamc21j/src/rtc/mode2/intenset.rs new file mode 100644 index 000000000000..a41687fa1ee5 --- /dev/null +++ b/pac/atsamc21j/src/rtc/mode2/intenset.rs @@ -0,0 +1,536 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER0` reader - Periodic Interval 0 Enable"] +pub struct PER0_R(crate::FieldReader); +impl PER0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER0` writer - Periodic Interval 0 Enable"] +pub struct PER0_W<'a> { + w: &'a mut W, +} +impl<'a> PER0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PER1` reader - Periodic Interval 1 Enable"] +pub struct PER1_R(crate::FieldReader); +impl PER1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER1` writer - Periodic Interval 1 Enable"] +pub struct PER1_W<'a> { + w: &'a mut W, +} +impl<'a> PER1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PER2` reader - Periodic Interval 2 Enable"] +pub struct PER2_R(crate::FieldReader); +impl PER2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER2` writer - Periodic Interval 2 Enable"] +pub struct PER2_W<'a> { + w: &'a mut W, +} +impl<'a> PER2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PER3` reader - Periodic Interval 3 Enable"] +pub struct PER3_R(crate::FieldReader); +impl PER3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER3` writer - Periodic Interval 3 Enable"] +pub struct PER3_W<'a> { + w: &'a mut W, +} +impl<'a> PER3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PER4` reader - Periodic Interval 4 Enable"] +pub struct PER4_R(crate::FieldReader); +impl PER4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER4` writer - Periodic Interval 4 Enable"] +pub struct PER4_W<'a> { + w: &'a mut W, +} +impl<'a> PER4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PER5` reader - Periodic Interval 5 Enable"] +pub struct PER5_R(crate::FieldReader); +impl PER5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER5` writer - Periodic Interval 5 Enable"] +pub struct PER5_W<'a> { + w: &'a mut W, +} +impl<'a> PER5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PER6` reader - Periodic Interval 6 Enable"] +pub struct PER6_R(crate::FieldReader); +impl PER6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER6` writer - Periodic Interval 6 Enable"] +pub struct PER6_W<'a> { + w: &'a mut W, +} +impl<'a> PER6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PER7` reader - Periodic Interval 7 Enable"] +pub struct PER7_R(crate::FieldReader); +impl PER7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER7` writer - Periodic Interval 7 Enable"] +pub struct PER7_W<'a> { + w: &'a mut W, +} +impl<'a> PER7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `ALARM0` reader - Alarm 0 Interrupt Enable"] +pub struct ALARM0_R(crate::FieldReader); +impl ALARM0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALARM0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALARM0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALARM0` writer - Alarm 0 Interrupt Enable"] +pub struct ALARM0_W<'a> { + w: &'a mut W, +} +impl<'a> ALARM0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Enable"] + #[inline(always)] + pub fn per0(&self) -> PER0_R { + PER0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Enable"] + #[inline(always)] + pub fn per1(&self) -> PER1_R { + PER1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Enable"] + #[inline(always)] + pub fn per2(&self) -> PER2_R { + PER2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Enable"] + #[inline(always)] + pub fn per3(&self) -> PER3_R { + PER3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Enable"] + #[inline(always)] + pub fn per4(&self) -> PER4_R { + PER4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Enable"] + #[inline(always)] + pub fn per5(&self) -> PER5_R { + PER5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Enable"] + #[inline(always)] + pub fn per6(&self) -> PER6_R { + PER6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Enable"] + #[inline(always)] + pub fn per7(&self) -> PER7_R { + PER7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Alarm 0 Interrupt Enable"] + #[inline(always)] + pub fn alarm0(&self) -> ALARM0_R { + ALARM0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Enable"] + #[inline(always)] + pub fn per0(&mut self) -> PER0_W { + PER0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1 Enable"] + #[inline(always)] + pub fn per1(&mut self) -> PER1_W { + PER1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2 Enable"] + #[inline(always)] + pub fn per2(&mut self) -> PER2_W { + PER2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3 Enable"] + #[inline(always)] + pub fn per3(&mut self) -> PER3_W { + PER3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4 Enable"] + #[inline(always)] + pub fn per4(&mut self) -> PER4_W { + PER4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5 Enable"] + #[inline(always)] + pub fn per5(&mut self) -> PER5_W { + PER5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6 Enable"] + #[inline(always)] + pub fn per6(&mut self) -> PER6_W { + PER6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7 Enable"] + #[inline(always)] + pub fn per7(&mut self) -> PER7_W { + PER7_W { w: self } + } + #[doc = "Bit 8 - Alarm 0 Interrupt Enable"] + #[inline(always)] + pub fn alarm0(&mut self) -> ALARM0_W { + ALARM0_W { w: self } + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2 Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/rtc/mode2/intflag.rs b/pac/atsamc21j/src/rtc/mode2/intflag.rs new file mode 100644 index 000000000000..8de0f3efd1d0 --- /dev/null +++ b/pac/atsamc21j/src/rtc/mode2/intflag.rs @@ -0,0 +1,536 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER0` reader - Periodic Interval 0"] +pub struct PER0_R(crate::FieldReader); +impl PER0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER0` writer - Periodic Interval 0"] +pub struct PER0_W<'a> { + w: &'a mut W, +} +impl<'a> PER0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PER1` reader - Periodic Interval 1"] +pub struct PER1_R(crate::FieldReader); +impl PER1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER1` writer - Periodic Interval 1"] +pub struct PER1_W<'a> { + w: &'a mut W, +} +impl<'a> PER1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PER2` reader - Periodic Interval 2"] +pub struct PER2_R(crate::FieldReader); +impl PER2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER2` writer - Periodic Interval 2"] +pub struct PER2_W<'a> { + w: &'a mut W, +} +impl<'a> PER2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PER3` reader - Periodic Interval 3"] +pub struct PER3_R(crate::FieldReader); +impl PER3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER3` writer - Periodic Interval 3"] +pub struct PER3_W<'a> { + w: &'a mut W, +} +impl<'a> PER3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PER4` reader - Periodic Interval 4"] +pub struct PER4_R(crate::FieldReader); +impl PER4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER4` writer - Periodic Interval 4"] +pub struct PER4_W<'a> { + w: &'a mut W, +} +impl<'a> PER4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PER5` reader - Periodic Interval 5"] +pub struct PER5_R(crate::FieldReader); +impl PER5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER5` writer - Periodic Interval 5"] +pub struct PER5_W<'a> { + w: &'a mut W, +} +impl<'a> PER5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PER6` reader - Periodic Interval 6"] +pub struct PER6_R(crate::FieldReader); +impl PER6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER6` writer - Periodic Interval 6"] +pub struct PER6_W<'a> { + w: &'a mut W, +} +impl<'a> PER6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PER7` reader - Periodic Interval 7"] +pub struct PER7_R(crate::FieldReader); +impl PER7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER7` writer - Periodic Interval 7"] +pub struct PER7_W<'a> { + w: &'a mut W, +} +impl<'a> PER7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `ALARM0` reader - Alarm 0"] +pub struct ALARM0_R(crate::FieldReader); +impl ALARM0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALARM0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALARM0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALARM0` writer - Alarm 0"] +pub struct ALARM0_W<'a> { + w: &'a mut W, +} +impl<'a> ALARM0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0"] + #[inline(always)] + pub fn per0(&self) -> PER0_R { + PER0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1"] + #[inline(always)] + pub fn per1(&self) -> PER1_R { + PER1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2"] + #[inline(always)] + pub fn per2(&self) -> PER2_R { + PER2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3"] + #[inline(always)] + pub fn per3(&self) -> PER3_R { + PER3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4"] + #[inline(always)] + pub fn per4(&self) -> PER4_R { + PER4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5"] + #[inline(always)] + pub fn per5(&self) -> PER5_R { + PER5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6"] + #[inline(always)] + pub fn per6(&self) -> PER6_R { + PER6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7"] + #[inline(always)] + pub fn per7(&self) -> PER7_R { + PER7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Alarm 0"] + #[inline(always)] + pub fn alarm0(&self) -> ALARM0_R { + ALARM0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0"] + #[inline(always)] + pub fn per0(&mut self) -> PER0_W { + PER0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1"] + #[inline(always)] + pub fn per1(&mut self) -> PER1_W { + PER1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2"] + #[inline(always)] + pub fn per2(&mut self) -> PER2_W { + PER2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3"] + #[inline(always)] + pub fn per3(&mut self) -> PER3_W { + PER3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4"] + #[inline(always)] + pub fn per4(&mut self) -> PER4_W { + PER4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5"] + #[inline(always)] + pub fn per5(&mut self) -> PER5_W { + PER5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6"] + #[inline(always)] + pub fn per6(&mut self) -> PER6_W { + PER6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7"] + #[inline(always)] + pub fn per7(&mut self) -> PER7_W { + PER7_W { w: self } + } + #[doc = "Bit 8 - Alarm 0"] + #[inline(always)] + pub fn alarm0(&mut self) -> ALARM0_W { + ALARM0_W { w: self } + } + #[doc = "Bit 15 - Overflow"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2 Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/rtc/mode2/mask.rs b/pac/atsamc21j/src/rtc/mode2/mask.rs new file mode 100644 index 000000000000..53e0bb491a62 --- /dev/null +++ b/pac/atsamc21j/src/rtc/mode2/mask.rs @@ -0,0 +1,217 @@ +#[doc = "Register `MASK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MASK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Alarm Mask Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SEL_A { + #[doc = "0: Alarm Disabled"] + OFF = 0, + #[doc = "1: Match seconds only"] + SS = 1, + #[doc = "2: Match seconds and minutes only"] + MMSS = 2, + #[doc = "3: Match seconds, minutes, and hours only"] + HHMMSS = 3, + #[doc = "4: Match seconds, minutes, hours, and days only"] + DDHHMMSS = 4, + #[doc = "5: Match seconds, minutes, hours, days, and months only"] + MMDDHHMMSS = 5, + #[doc = "6: Match seconds, minutes, hours, days, months, and years"] + YYMMDDHHMMSS = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `SEL` reader - Alarm Mask Selection"] +pub struct SEL_R(crate::FieldReader); +impl SEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEL_A::OFF), + 1 => Some(SEL_A::SS), + 2 => Some(SEL_A::MMSS), + 3 => Some(SEL_A::HHMMSS), + 4 => Some(SEL_A::DDHHMMSS), + 5 => Some(SEL_A::MMDDHHMMSS), + 6 => Some(SEL_A::YYMMDDHHMMSS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == SEL_A::OFF + } + #[doc = "Checks if the value of the field is `SS`"] + #[inline(always)] + pub fn is_ss(&self) -> bool { + **self == SEL_A::SS + } + #[doc = "Checks if the value of the field is `MMSS`"] + #[inline(always)] + pub fn is_mmss(&self) -> bool { + **self == SEL_A::MMSS + } + #[doc = "Checks if the value of the field is `HHMMSS`"] + #[inline(always)] + pub fn is_hhmmss(&self) -> bool { + **self == SEL_A::HHMMSS + } + #[doc = "Checks if the value of the field is `DDHHMMSS`"] + #[inline(always)] + pub fn is_ddhhmmss(&self) -> bool { + **self == SEL_A::DDHHMMSS + } + #[doc = "Checks if the value of the field is `MMDDHHMMSS`"] + #[inline(always)] + pub fn is_mmddhhmmss(&self) -> bool { + **self == SEL_A::MMDDHHMMSS + } + #[doc = "Checks if the value of the field is `YYMMDDHHMMSS`"] + #[inline(always)] + pub fn is_yymmddhhmmss(&self) -> bool { + **self == SEL_A::YYMMDDHHMMSS + } +} +impl core::ops::Deref for SEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEL` writer - Alarm Mask Selection"] +pub struct SEL_W<'a> { + w: &'a mut W, +} +impl<'a> SEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SEL_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Alarm Disabled"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(SEL_A::OFF) + } + #[doc = "Match seconds only"] + #[inline(always)] + pub fn ss(self) -> &'a mut W { + self.variant(SEL_A::SS) + } + #[doc = "Match seconds and minutes only"] + #[inline(always)] + pub fn mmss(self) -> &'a mut W { + self.variant(SEL_A::MMSS) + } + #[doc = "Match seconds, minutes, and hours only"] + #[inline(always)] + pub fn hhmmss(self) -> &'a mut W { + self.variant(SEL_A::HHMMSS) + } + #[doc = "Match seconds, minutes, hours, and days only"] + #[inline(always)] + pub fn ddhhmmss(self) -> &'a mut W { + self.variant(SEL_A::DDHHMMSS) + } + #[doc = "Match seconds, minutes, hours, days, and months only"] + #[inline(always)] + pub fn mmddhhmmss(self) -> &'a mut W { + self.variant(SEL_A::MMDDHHMMSS) + } + #[doc = "Match seconds, minutes, hours, days, months, and years"] + #[inline(always)] + pub fn yymmddhhmmss(self) -> &'a mut W { + self.variant(SEL_A::YYMMDDHHMMSS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Alarm Mask Selection"] + #[inline(always)] + pub fn sel(&self) -> SEL_R { + SEL_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Alarm Mask Selection"] + #[inline(always)] + pub fn sel(&mut self) -> SEL_W { + SEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2_ALARM Alarm n Mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mask](index.html) module"] +pub struct MASK_SPEC; +impl crate::RegisterSpec for MASK_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [mask::R](R) reader structure"] +impl crate::Readable for MASK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [mask::W](W) writer structure"] +impl crate::Writable for MASK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets MASK to value 0"] +impl crate::Resettable for MASK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/rtc/mode2/syncbusy.rs b/pac/atsamc21j/src/rtc/mode2/syncbusy.rs new file mode 100644 index 000000000000..b517ee5ae8b2 --- /dev/null +++ b/pac/atsamc21j/src/rtc/mode2/syncbusy.rs @@ -0,0 +1,173 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Bit Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - Enable Bit Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FREQCORR` reader - FREQCORR Register Busy"] +pub struct FREQCORR_R(crate::FieldReader); +impl FREQCORR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FREQCORR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FREQCORR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLOCK` reader - CLOCK Register Busy"] +pub struct CLOCK_R(crate::FieldReader); +impl CLOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALARM0` reader - ALARM 0 Register Busy"] +pub struct ALARM0_R(crate::FieldReader); +impl ALARM0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALARM0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALARM0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MASK0` reader - MASK 0 Register Busy"] +pub struct MASK0_R(crate::FieldReader); +impl MASK0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MASK0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MASK0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLOCKSYNC` reader - Clock Read Synchronization Enable Bit Busy"] +pub struct CLOCKSYNC_R(crate::FieldReader); +impl CLOCKSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLOCKSYNC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLOCKSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Bit Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable Bit Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - FREQCORR Register Busy"] + #[inline(always)] + pub fn freqcorr(&self) -> FREQCORR_R { + FREQCORR_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - CLOCK Register Busy"] + #[inline(always)] + pub fn clock(&self) -> CLOCK_R { + CLOCK_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 5 - ALARM 0 Register Busy"] + #[inline(always)] + pub fn alarm0(&self) -> ALARM0_R { + ALARM0_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 11 - MASK 0 Register Busy"] + #[inline(always)] + pub fn mask0(&self) -> MASK0_R { + MASK0_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 15 - Clock Read Synchronization Enable Bit Busy"] + #[inline(always)] + pub fn clocksync(&self) -> CLOCKSYNC_R { + CLOCKSYNC_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +#[doc = "MODE2 Synchronization Busy Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sdadc.rs b/pac/atsamc21j/src/sdadc.rs new file mode 100644 index 000000000000..11e926a1d2de --- /dev/null +++ b/pac/atsamc21j/src/sdadc.rs @@ -0,0 +1,140 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + #[doc = "0x01 - Reference Control"] + pub refctrl: crate::Reg, + #[doc = "0x02 - Control B"] + pub ctrlb: crate::Reg, + #[doc = "0x04 - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x05 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x06 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x07 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x08 - Sequence Status"] + pub seqstatus: crate::Reg, + #[doc = "0x09 - Input Control"] + pub inputctrl: crate::Reg, + #[doc = "0x0a - Control C"] + pub ctrlc: crate::Reg, + #[doc = "0x0b - Window Monitor Control"] + pub winctrl: crate::Reg, + #[doc = "0x0c - Window Monitor Lower Threshold"] + pub winlt: crate::Reg, + #[doc = "0x10 - Window Monitor Upper Threshold"] + pub winut: crate::Reg, + #[doc = "0x14 - Offset Correction"] + pub offsetcorr: crate::Reg, + #[doc = "0x18 - Gain Correction"] + pub gaincorr: crate::Reg, + #[doc = "0x1a - Shift Correction"] + pub shiftcorr: crate::Reg, + _reserved16: [u8; 0x01], + #[doc = "0x1c - Software Trigger"] + pub swtrig: crate::Reg, + _reserved17: [u8; 0x03], + #[doc = "0x20 - Synchronization Busy"] + pub syncbusy: crate::Reg, + #[doc = "0x24 - Result"] + pub result: crate::Reg, + #[doc = "0x28 - Sequence Control"] + pub seqctrl: crate::Reg, + _reserved20: [u8; 0x03], + #[doc = "0x2c - Analog Control"] + pub anactrl: crate::Reg, + _reserved21: [u8; 0x01], + #[doc = "0x2e - Debug Control"] + pub dbgctrl: crate::Reg, +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "REFCTRL register accessor: an alias for `Reg`"] +pub type REFCTRL = crate::Reg; +#[doc = "Reference Control"] +pub mod refctrl; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "Control B"] +pub mod ctrlb; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "SEQSTATUS register accessor: an alias for `Reg`"] +pub type SEQSTATUS = crate::Reg; +#[doc = "Sequence Status"] +pub mod seqstatus; +#[doc = "INPUTCTRL register accessor: an alias for `Reg`"] +pub type INPUTCTRL = crate::Reg; +#[doc = "Input Control"] +pub mod inputctrl; +#[doc = "CTRLC register accessor: an alias for `Reg`"] +pub type CTRLC = crate::Reg; +#[doc = "Control C"] +pub mod ctrlc; +#[doc = "WINCTRL register accessor: an alias for `Reg`"] +pub type WINCTRL = crate::Reg; +#[doc = "Window Monitor Control"] +pub mod winctrl; +#[doc = "WINLT register accessor: an alias for `Reg`"] +pub type WINLT = crate::Reg; +#[doc = "Window Monitor Lower Threshold"] +pub mod winlt; +#[doc = "WINUT register accessor: an alias for `Reg`"] +pub type WINUT = crate::Reg; +#[doc = "Window Monitor Upper Threshold"] +pub mod winut; +#[doc = "OFFSETCORR register accessor: an alias for `Reg`"] +pub type OFFSETCORR = crate::Reg; +#[doc = "Offset Correction"] +pub mod offsetcorr; +#[doc = "GAINCORR register accessor: an alias for `Reg`"] +pub type GAINCORR = crate::Reg; +#[doc = "Gain Correction"] +pub mod gaincorr; +#[doc = "SHIFTCORR register accessor: an alias for `Reg`"] +pub type SHIFTCORR = crate::Reg; +#[doc = "Shift Correction"] +pub mod shiftcorr; +#[doc = "SWTRIG register accessor: an alias for `Reg`"] +pub type SWTRIG = crate::Reg; +#[doc = "Software Trigger"] +pub mod swtrig; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Busy"] +pub mod syncbusy; +#[doc = "RESULT register accessor: an alias for `Reg`"] +pub type RESULT = crate::Reg; +#[doc = "Result"] +pub mod result; +#[doc = "SEQCTRL register accessor: an alias for `Reg`"] +pub type SEQCTRL = crate::Reg; +#[doc = "Sequence Control"] +pub mod seqctrl; +#[doc = "ANACTRL register accessor: an alias for `Reg`"] +pub type ANACTRL = crate::Reg; +#[doc = "Analog Control"] +pub mod anactrl; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; diff --git a/pac/atsamc21j/src/sdadc/anactrl.rs b/pac/atsamc21j/src/sdadc/anactrl.rs new file mode 100644 index 000000000000..3261811c0348 --- /dev/null +++ b/pac/atsamc21j/src/sdadc/anactrl.rs @@ -0,0 +1,197 @@ +#[doc = "Register `ANACTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ANACTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CTRSDADC` reader - SDADC Control"] +pub struct CTRSDADC_R(crate::FieldReader); +impl CTRSDADC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CTRSDADC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRSDADC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRSDADC` writer - SDADC Control"] +pub struct CTRSDADC_W<'a> { + w: &'a mut W, +} +impl<'a> CTRSDADC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u8 & 0x3f); + self.w + } +} +#[doc = "Field `ONCHOP` reader - Chopper"] +pub struct ONCHOP_R(crate::FieldReader); +impl ONCHOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONCHOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONCHOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONCHOP` writer - Chopper"] +pub struct ONCHOP_W<'a> { + w: &'a mut W, +} +impl<'a> ONCHOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +#[doc = "Field `BUFTEST` reader - BUFTEST"] +pub struct BUFTEST_R(crate::FieldReader); +impl BUFTEST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUFTEST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUFTEST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUFTEST` writer - BUFTEST"] +pub struct BUFTEST_W<'a> { + w: &'a mut W, +} +impl<'a> BUFTEST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - SDADC Control"] + #[inline(always)] + pub fn ctrsdadc(&self) -> CTRSDADC_R { + CTRSDADC_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - Chopper"] + #[inline(always)] + pub fn onchop(&self) -> ONCHOP_R { + ONCHOP_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - BUFTEST"] + #[inline(always)] + pub fn buftest(&self) -> BUFTEST_R { + BUFTEST_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:5 - SDADC Control"] + #[inline(always)] + pub fn ctrsdadc(&mut self) -> CTRSDADC_W { + CTRSDADC_W { w: self } + } + #[doc = "Bit 6 - Chopper"] + #[inline(always)] + pub fn onchop(&mut self) -> ONCHOP_W { + ONCHOP_W { w: self } + } + #[doc = "Bit 7 - BUFTEST"] + #[inline(always)] + pub fn buftest(&mut self) -> BUFTEST_W { + BUFTEST_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Analog Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [anactrl](index.html) module"] +pub struct ANACTRL_SPEC; +impl crate::RegisterSpec for ANACTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [anactrl::R](R) reader structure"] +impl crate::Readable for ANACTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [anactrl::W](W) writer structure"] +impl crate::Writable for ANACTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ANACTRL to value 0"] +impl crate::Resettable for ANACTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sdadc/ctrla.rs b/pac/atsamc21j/src/sdadc/ctrla.rs new file mode 100644 index 000000000000..8fccdcb93995 --- /dev/null +++ b/pac/atsamc21j/src/sdadc/ctrla.rs @@ -0,0 +1,254 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - On Demand Control"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - On Demand Control"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sdadc/ctrlb.rs b/pac/atsamc21j/src/sdadc/ctrlb.rs new file mode 100644 index 000000000000..ee0dce613bc4 --- /dev/null +++ b/pac/atsamc21j/src/sdadc/ctrlb.rs @@ -0,0 +1,392 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Prescaler Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: Peripheral clock divided by 2"] + DIV2 = 0, + #[doc = "1: Peripheral clock divided by 4"] + DIV4 = 1, + #[doc = "2: Peripheral clock divided by 8"] + DIV8 = 2, + #[doc = "3: Peripheral clock divided by 16"] + DIV16 = 3, + #[doc = "4: Peripheral clock divided by 32"] + DIV32 = 4, + #[doc = "5: Peripheral clock divided by 64"] + DIV64 = 5, + #[doc = "6: Peripheral clock divided by 128"] + DIV128 = 6, + #[doc = "7: Peripheral clock divided by 256"] + DIV256 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler Configuration"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCALER_A::DIV2), + 1 => Some(PRESCALER_A::DIV4), + 2 => Some(PRESCALER_A::DIV8), + 3 => Some(PRESCALER_A::DIV16), + 4 => Some(PRESCALER_A::DIV32), + 5 => Some(PRESCALER_A::DIV64), + 6 => Some(PRESCALER_A::DIV128), + 7 => Some(PRESCALER_A::DIV256), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == PRESCALER_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == PRESCALER_A::DIV128 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler Configuration"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Peripheral clock divided by 2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "Peripheral clock divided by 4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "Peripheral clock divided by 8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "Peripheral clock divided by 16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "Peripheral clock divided by 32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV32) + } + #[doc = "Peripheral clock divided by 64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "Peripheral clock divided by 128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV128) + } + #[doc = "Peripheral clock divided by 256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u16 & 0xff); + self.w + } +} +#[doc = "Over Sampling Ratio\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum OSR_A { + #[doc = "0: Over Sampling Ratio is 64"] + OSR64 = 0, + #[doc = "1: Over Sampling Ratio is 128"] + OSR128 = 1, + #[doc = "2: Over Sampling Ratio is 256"] + OSR256 = 2, + #[doc = "3: Over Sampling Ratio is 512"] + OSR512 = 3, + #[doc = "4: Over Sampling Ratio is 1024"] + OSR1024 = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: OSR_A) -> Self { + variant as _ + } +} +#[doc = "Field `OSR` reader - Over Sampling Ratio"] +pub struct OSR_R(crate::FieldReader); +impl OSR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + OSR_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(OSR_A::OSR64), + 1 => Some(OSR_A::OSR128), + 2 => Some(OSR_A::OSR256), + 3 => Some(OSR_A::OSR512), + 4 => Some(OSR_A::OSR1024), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OSR64`"] + #[inline(always)] + pub fn is_osr64(&self) -> bool { + **self == OSR_A::OSR64 + } + #[doc = "Checks if the value of the field is `OSR128`"] + #[inline(always)] + pub fn is_osr128(&self) -> bool { + **self == OSR_A::OSR128 + } + #[doc = "Checks if the value of the field is `OSR256`"] + #[inline(always)] + pub fn is_osr256(&self) -> bool { + **self == OSR_A::OSR256 + } + #[doc = "Checks if the value of the field is `OSR512`"] + #[inline(always)] + pub fn is_osr512(&self) -> bool { + **self == OSR_A::OSR512 + } + #[doc = "Checks if the value of the field is `OSR1024`"] + #[inline(always)] + pub fn is_osr1024(&self) -> bool { + **self == OSR_A::OSR1024 + } +} +impl core::ops::Deref for OSR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSR` writer - Over Sampling Ratio"] +pub struct OSR_W<'a> { + w: &'a mut W, +} +impl<'a> OSR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: OSR_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Over Sampling Ratio is 64"] + #[inline(always)] + pub fn osr64(self) -> &'a mut W { + self.variant(OSR_A::OSR64) + } + #[doc = "Over Sampling Ratio is 128"] + #[inline(always)] + pub fn osr128(self) -> &'a mut W { + self.variant(OSR_A::OSR128) + } + #[doc = "Over Sampling Ratio is 256"] + #[inline(always)] + pub fn osr256(self) -> &'a mut W { + self.variant(OSR_A::OSR256) + } + #[doc = "Over Sampling Ratio is 512"] + #[inline(always)] + pub fn osr512(self) -> &'a mut W { + self.variant(OSR_A::OSR512) + } + #[doc = "Over Sampling Ratio is 1024"] + #[inline(always)] + pub fn osr1024(self) -> &'a mut W { + self.variant(OSR_A::OSR1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u16 & 0x07) << 8); + self.w + } +} +#[doc = "Field `SKPCNT` reader - Skip Sample Count"] +pub struct SKPCNT_R(crate::FieldReader); +impl SKPCNT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SKPCNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SKPCNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SKPCNT` writer - Skip Sample Count"] +pub struct SKPCNT_W<'a> { + w: &'a mut W, +} +impl<'a> SKPCNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 12)) | ((value as u16 & 0x0f) << 12); + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Prescaler Configuration"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:10 - Over Sampling Ratio"] + #[inline(always)] + pub fn osr(&self) -> OSR_R { + OSR_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bits 12:15 - Skip Sample Count"] + #[inline(always)] + pub fn skpcnt(&self) -> SKPCNT_R { + SKPCNT_R::new(((self.bits >> 12) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Prescaler Configuration"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Bits 8:10 - Over Sampling Ratio"] + #[inline(always)] + pub fn osr(&mut self) -> OSR_W { + OSR_W { w: self } + } + #[doc = "Bits 12:15 - Skip Sample Count"] + #[inline(always)] + pub fn skpcnt(&mut self) -> SKPCNT_W { + SKPCNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0x2000"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x2000 + } +} diff --git a/pac/atsamc21j/src/sdadc/ctrlc.rs b/pac/atsamc21j/src/sdadc/ctrlc.rs new file mode 100644 index 000000000000..320cfe4ec4aa --- /dev/null +++ b/pac/atsamc21j/src/sdadc/ctrlc.rs @@ -0,0 +1,113 @@ +#[doc = "Register `CTRLC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FREERUN` reader - Free Running Mode"] +pub struct FREERUN_R(crate::FieldReader); +impl FREERUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FREERUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FREERUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FREERUN` writer - Free Running Mode"] +pub struct FREERUN_W<'a> { + w: &'a mut W, +} +impl<'a> FREERUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Free Running Mode"] + #[inline(always)] + pub fn freerun(&self) -> FREERUN_R { + FREERUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Free Running Mode"] + #[inline(always)] + pub fn freerun(&mut self) -> FREERUN_W { + FREERUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control C\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlc](index.html) module"] +pub struct CTRLC_SPEC; +impl crate::RegisterSpec for CTRLC_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlc::R](R) reader structure"] +impl crate::Readable for CTRLC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlc::W](W) writer structure"] +impl crate::Writable for CTRLC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLC to value 0"] +impl crate::Resettable for CTRLC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sdadc/dbgctrl.rs b/pac/atsamc21j/src/sdadc/dbgctrl.rs new file mode 100644 index 000000000000..53636eb2b339 --- /dev/null +++ b/pac/atsamc21j/src/sdadc/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Debug Run"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Debug Run"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sdadc/evctrl.rs b/pac/atsamc21j/src/sdadc/evctrl.rs new file mode 100644 index 000000000000..2c50a979c544 --- /dev/null +++ b/pac/atsamc21j/src/sdadc/evctrl.rs @@ -0,0 +1,348 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FLUSHEI` reader - Flush Event Input Enable"] +pub struct FLUSHEI_R(crate::FieldReader); +impl FLUSHEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FLUSHEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FLUSHEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLUSHEI` writer - Flush Event Input Enable"] +pub struct FLUSHEI_W<'a> { + w: &'a mut W, +} +impl<'a> FLUSHEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `STARTEI` reader - Start Conversion Event Input Enable"] +pub struct STARTEI_R(crate::FieldReader); +impl STARTEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STARTEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STARTEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STARTEI` writer - Start Conversion Event Input Enable"] +pub struct STARTEI_W<'a> { + w: &'a mut W, +} +impl<'a> STARTEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `FLUSHINV` reader - Flush Event Invert Enable"] +pub struct FLUSHINV_R(crate::FieldReader); +impl FLUSHINV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FLUSHINV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FLUSHINV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLUSHINV` writer - Flush Event Invert Enable"] +pub struct FLUSHINV_W<'a> { + w: &'a mut W, +} +impl<'a> FLUSHINV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `STARTINV` reader - Satrt Event Invert Enable"] +pub struct STARTINV_R(crate::FieldReader); +impl STARTINV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STARTINV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STARTINV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STARTINV` writer - Satrt Event Invert Enable"] +pub struct STARTINV_W<'a> { + w: &'a mut W, +} +impl<'a> STARTINV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `RESRDYEO` reader - Result Ready Event Out"] +pub struct RESRDYEO_R(crate::FieldReader); +impl RESRDYEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESRDYEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESRDYEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESRDYEO` writer - Result Ready Event Out"] +pub struct RESRDYEO_W<'a> { + w: &'a mut W, +} +impl<'a> RESRDYEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `WINMONEO` reader - Window Monitor Event Out"] +pub struct WINMONEO_R(crate::FieldReader); +impl WINMONEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINMONEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINMONEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMONEO` writer - Window Monitor Event Out"] +pub struct WINMONEO_W<'a> { + w: &'a mut W, +} +impl<'a> WINMONEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Flush Event Input Enable"] + #[inline(always)] + pub fn flushei(&self) -> FLUSHEI_R { + FLUSHEI_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Start Conversion Event Input Enable"] + #[inline(always)] + pub fn startei(&self) -> STARTEI_R { + STARTEI_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Flush Event Invert Enable"] + #[inline(always)] + pub fn flushinv(&self) -> FLUSHINV_R { + FLUSHINV_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Satrt Event Invert Enable"] + #[inline(always)] + pub fn startinv(&self) -> STARTINV_R { + STARTINV_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Result Ready Event Out"] + #[inline(always)] + pub fn resrdyeo(&self) -> RESRDYEO_R { + RESRDYEO_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Window Monitor Event Out"] + #[inline(always)] + pub fn winmoneo(&self) -> WINMONEO_R { + WINMONEO_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Flush Event Input Enable"] + #[inline(always)] + pub fn flushei(&mut self) -> FLUSHEI_W { + FLUSHEI_W { w: self } + } + #[doc = "Bit 1 - Start Conversion Event Input Enable"] + #[inline(always)] + pub fn startei(&mut self) -> STARTEI_W { + STARTEI_W { w: self } + } + #[doc = "Bit 2 - Flush Event Invert Enable"] + #[inline(always)] + pub fn flushinv(&mut self) -> FLUSHINV_W { + FLUSHINV_W { w: self } + } + #[doc = "Bit 3 - Satrt Event Invert Enable"] + #[inline(always)] + pub fn startinv(&mut self) -> STARTINV_W { + STARTINV_W { w: self } + } + #[doc = "Bit 4 - Result Ready Event Out"] + #[inline(always)] + pub fn resrdyeo(&mut self) -> RESRDYEO_W { + RESRDYEO_W { w: self } + } + #[doc = "Bit 5 - Window Monitor Event Out"] + #[inline(always)] + pub fn winmoneo(&mut self) -> WINMONEO_W { + WINMONEO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sdadc/gaincorr.rs b/pac/atsamc21j/src/sdadc/gaincorr.rs new file mode 100644 index 000000000000..0f20d1cdef86 --- /dev/null +++ b/pac/atsamc21j/src/sdadc/gaincorr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `GAINCORR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GAINCORR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `GAINCORR` reader - Gain Correction Value"] +pub struct GAINCORR_R(crate::FieldReader); +impl GAINCORR_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + GAINCORR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GAINCORR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GAINCORR` writer - Gain Correction Value"] +pub struct GAINCORR_W<'a> { + w: &'a mut W, +} +impl<'a> GAINCORR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3fff) | (value as u16 & 0x3fff); + self.w + } +} +impl R { + #[doc = "Bits 0:13 - Gain Correction Value"] + #[inline(always)] + pub fn gaincorr(&self) -> GAINCORR_R { + GAINCORR_R::new((self.bits & 0x3fff) as u16) + } +} +impl W { + #[doc = "Bits 0:13 - Gain Correction Value"] + #[inline(always)] + pub fn gaincorr(&mut self) -> GAINCORR_W { + GAINCORR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Gain Correction\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gaincorr](index.html) module"] +pub struct GAINCORR_SPEC; +impl crate::RegisterSpec for GAINCORR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [gaincorr::R](R) reader structure"] +impl crate::Readable for GAINCORR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gaincorr::W](W) writer structure"] +impl crate::Writable for GAINCORR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets GAINCORR to value 0x01"] +impl crate::Resettable for GAINCORR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pac/atsamc21j/src/sdadc/inputctrl.rs b/pac/atsamc21j/src/sdadc/inputctrl.rs new file mode 100644 index 000000000000..e256cd3bbfc1 --- /dev/null +++ b/pac/atsamc21j/src/sdadc/inputctrl.rs @@ -0,0 +1,165 @@ +#[doc = "Register `INPUTCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INPUTCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "SDADC Input Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MUXSEL_A { + #[doc = "0: SDADC AIN0 Pin"] + AIN0 = 0, + #[doc = "1: SDADC AIN1 Pin"] + AIN1 = 1, + #[doc = "2: SDADC AIN2 Pin"] + AIN2 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MUXSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `MUXSEL` reader - SDADC Input Selection"] +pub struct MUXSEL_R(crate::FieldReader); +impl MUXSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MUXSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MUXSEL_A::AIN0), + 1 => Some(MUXSEL_A::AIN1), + 2 => Some(MUXSEL_A::AIN2), + _ => None, + } + } + #[doc = "Checks if the value of the field is `AIN0`"] + #[inline(always)] + pub fn is_ain0(&self) -> bool { + **self == MUXSEL_A::AIN0 + } + #[doc = "Checks if the value of the field is `AIN1`"] + #[inline(always)] + pub fn is_ain1(&self) -> bool { + **self == MUXSEL_A::AIN1 + } + #[doc = "Checks if the value of the field is `AIN2`"] + #[inline(always)] + pub fn is_ain2(&self) -> bool { + **self == MUXSEL_A::AIN2 + } +} +impl core::ops::Deref for MUXSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MUXSEL` writer - SDADC Input Selection"] +pub struct MUXSEL_W<'a> { + w: &'a mut W, +} +impl<'a> MUXSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MUXSEL_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "SDADC AIN0 Pin"] + #[inline(always)] + pub fn ain0(self) -> &'a mut W { + self.variant(MUXSEL_A::AIN0) + } + #[doc = "SDADC AIN1 Pin"] + #[inline(always)] + pub fn ain1(self) -> &'a mut W { + self.variant(MUXSEL_A::AIN1) + } + #[doc = "SDADC AIN2 Pin"] + #[inline(always)] + pub fn ain2(self) -> &'a mut W { + self.variant(MUXSEL_A::AIN2) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - SDADC Input Selection"] + #[inline(always)] + pub fn muxsel(&self) -> MUXSEL_R { + MUXSEL_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - SDADC Input Selection"] + #[inline(always)] + pub fn muxsel(&mut self) -> MUXSEL_W { + MUXSEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Input Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [inputctrl](index.html) module"] +pub struct INPUTCTRL_SPEC; +impl crate::RegisterSpec for INPUTCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [inputctrl::R](R) reader structure"] +impl crate::Readable for INPUTCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [inputctrl::W](W) writer structure"] +impl crate::Writable for INPUTCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INPUTCTRL to value 0"] +impl crate::Resettable for INPUTCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sdadc/intenclr.rs b/pac/atsamc21j/src/sdadc/intenclr.rs new file mode 100644 index 000000000000..b10f428d30b1 --- /dev/null +++ b/pac/atsamc21j/src/sdadc/intenclr.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RESRDY` reader - Result Ready Interrupt Disable"] +pub struct RESRDY_R(crate::FieldReader); +impl RESRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESRDY` writer - Result Ready Interrupt Disable"] +pub struct RESRDY_W<'a> { + w: &'a mut W, +} +impl<'a> RESRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `OVERRUN` reader - Overrun Interrupt Disable"] +pub struct OVERRUN_R(crate::FieldReader); +impl OVERRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVERRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVERRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVERRUN` writer - Overrun Interrupt Disable"] +pub struct OVERRUN_W<'a> { + w: &'a mut W, +} +impl<'a> OVERRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WINMON` reader - Window Monitor Interrupt Disable"] +pub struct WINMON_R(crate::FieldReader); +impl WINMON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINMON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINMON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMON` writer - Window Monitor Interrupt Disable"] +pub struct WINMON_W<'a> { + w: &'a mut W, +} +impl<'a> WINMON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Result Ready Interrupt Disable"] + #[inline(always)] + pub fn resrdy(&self) -> RESRDY_R { + RESRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Overrun Interrupt Disable"] + #[inline(always)] + pub fn overrun(&self) -> OVERRUN_R { + OVERRUN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Window Monitor Interrupt Disable"] + #[inline(always)] + pub fn winmon(&self) -> WINMON_R { + WINMON_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Result Ready Interrupt Disable"] + #[inline(always)] + pub fn resrdy(&mut self) -> RESRDY_W { + RESRDY_W { w: self } + } + #[doc = "Bit 1 - Overrun Interrupt Disable"] + #[inline(always)] + pub fn overrun(&mut self) -> OVERRUN_W { + OVERRUN_W { w: self } + } + #[doc = "Bit 2 - Window Monitor Interrupt Disable"] + #[inline(always)] + pub fn winmon(&mut self) -> WINMON_W { + WINMON_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sdadc/intenset.rs b/pac/atsamc21j/src/sdadc/intenset.rs new file mode 100644 index 000000000000..5ca93b05b859 --- /dev/null +++ b/pac/atsamc21j/src/sdadc/intenset.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RESRDY` reader - Result Ready Interrupt Enable"] +pub struct RESRDY_R(crate::FieldReader); +impl RESRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESRDY` writer - Result Ready Interrupt Enable"] +pub struct RESRDY_W<'a> { + w: &'a mut W, +} +impl<'a> RESRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `OVERRUN` reader - Overrun Interrupt Enable"] +pub struct OVERRUN_R(crate::FieldReader); +impl OVERRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVERRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVERRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVERRUN` writer - Overrun Interrupt Enable"] +pub struct OVERRUN_W<'a> { + w: &'a mut W, +} +impl<'a> OVERRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WINMON` reader - Window Monitor Interrupt Enable"] +pub struct WINMON_R(crate::FieldReader); +impl WINMON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINMON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINMON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMON` writer - Window Monitor Interrupt Enable"] +pub struct WINMON_W<'a> { + w: &'a mut W, +} +impl<'a> WINMON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Result Ready Interrupt Enable"] + #[inline(always)] + pub fn resrdy(&self) -> RESRDY_R { + RESRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Overrun Interrupt Enable"] + #[inline(always)] + pub fn overrun(&self) -> OVERRUN_R { + OVERRUN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Window Monitor Interrupt Enable"] + #[inline(always)] + pub fn winmon(&self) -> WINMON_R { + WINMON_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Result Ready Interrupt Enable"] + #[inline(always)] + pub fn resrdy(&mut self) -> RESRDY_W { + RESRDY_W { w: self } + } + #[doc = "Bit 1 - Overrun Interrupt Enable"] + #[inline(always)] + pub fn overrun(&mut self) -> OVERRUN_W { + OVERRUN_W { w: self } + } + #[doc = "Bit 2 - Window Monitor Interrupt Enable"] + #[inline(always)] + pub fn winmon(&mut self) -> WINMON_W { + WINMON_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sdadc/intflag.rs b/pac/atsamc21j/src/sdadc/intflag.rs new file mode 100644 index 000000000000..3cd74788b226 --- /dev/null +++ b/pac/atsamc21j/src/sdadc/intflag.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RESRDY` reader - Result Ready Interrupt Flag"] +pub struct RESRDY_R(crate::FieldReader); +impl RESRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESRDY` writer - Result Ready Interrupt Flag"] +pub struct RESRDY_W<'a> { + w: &'a mut W, +} +impl<'a> RESRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `OVERRUN` reader - Overrun Interrupt Flag"] +pub struct OVERRUN_R(crate::FieldReader); +impl OVERRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVERRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVERRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVERRUN` writer - Overrun Interrupt Flag"] +pub struct OVERRUN_W<'a> { + w: &'a mut W, +} +impl<'a> OVERRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WINMON` reader - Window Monitor Interrupt Flag"] +pub struct WINMON_R(crate::FieldReader); +impl WINMON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINMON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINMON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMON` writer - Window Monitor Interrupt Flag"] +pub struct WINMON_W<'a> { + w: &'a mut W, +} +impl<'a> WINMON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Result Ready Interrupt Flag"] + #[inline(always)] + pub fn resrdy(&self) -> RESRDY_R { + RESRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Overrun Interrupt Flag"] + #[inline(always)] + pub fn overrun(&self) -> OVERRUN_R { + OVERRUN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Window Monitor Interrupt Flag"] + #[inline(always)] + pub fn winmon(&self) -> WINMON_R { + WINMON_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Result Ready Interrupt Flag"] + #[inline(always)] + pub fn resrdy(&mut self) -> RESRDY_W { + RESRDY_W { w: self } + } + #[doc = "Bit 1 - Overrun Interrupt Flag"] + #[inline(always)] + pub fn overrun(&mut self) -> OVERRUN_W { + OVERRUN_W { w: self } + } + #[doc = "Bit 2 - Window Monitor Interrupt Flag"] + #[inline(always)] + pub fn winmon(&mut self) -> WINMON_W { + WINMON_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sdadc/offsetcorr.rs b/pac/atsamc21j/src/sdadc/offsetcorr.rs new file mode 100644 index 000000000000..7bda80d6fbfc --- /dev/null +++ b/pac/atsamc21j/src/sdadc/offsetcorr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `OFFSETCORR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OFFSETCORR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OFFSETCORR` reader - Offset Correction Value"] +pub struct OFFSETCORR_R(crate::FieldReader); +impl OFFSETCORR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + OFFSETCORR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OFFSETCORR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OFFSETCORR` writer - Offset Correction Value"] +pub struct OFFSETCORR_W<'a> { + w: &'a mut W, +} +impl<'a> OFFSETCORR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Offset Correction Value"] + #[inline(always)] + pub fn offsetcorr(&self) -> OFFSETCORR_R { + OFFSETCORR_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Offset Correction Value"] + #[inline(always)] + pub fn offsetcorr(&mut self) -> OFFSETCORR_W { + OFFSETCORR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Offset Correction\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [offsetcorr](index.html) module"] +pub struct OFFSETCORR_SPEC; +impl crate::RegisterSpec for OFFSETCORR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [offsetcorr::R](R) reader structure"] +impl crate::Readable for OFFSETCORR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [offsetcorr::W](W) writer structure"] +impl crate::Writable for OFFSETCORR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OFFSETCORR to value 0"] +impl crate::Resettable for OFFSETCORR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sdadc/refctrl.rs b/pac/atsamc21j/src/sdadc/refctrl.rs new file mode 100644 index 000000000000..89449071a49b --- /dev/null +++ b/pac/atsamc21j/src/sdadc/refctrl.rs @@ -0,0 +1,262 @@ +#[doc = "Register `REFCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `REFCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Reference Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum REFSEL_A { + #[doc = "0: Internal Bandgap Reference"] + INTREF = 0, + #[doc = "1: External Reference"] + AREFB = 1, + #[doc = "2: Internal DAC Output"] + DAC = 2, + #[doc = "3: VDDANA"] + INTVCC = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: REFSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `REFSEL` reader - Reference Selection"] +pub struct REFSEL_R(crate::FieldReader); +impl REFSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REFSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> REFSEL_A { + match self.bits { + 0 => REFSEL_A::INTREF, + 1 => REFSEL_A::AREFB, + 2 => REFSEL_A::DAC, + 3 => REFSEL_A::INTVCC, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INTREF`"] + #[inline(always)] + pub fn is_intref(&self) -> bool { + **self == REFSEL_A::INTREF + } + #[doc = "Checks if the value of the field is `AREFB`"] + #[inline(always)] + pub fn is_arefb(&self) -> bool { + **self == REFSEL_A::AREFB + } + #[doc = "Checks if the value of the field is `DAC`"] + #[inline(always)] + pub fn is_dac(&self) -> bool { + **self == REFSEL_A::DAC + } + #[doc = "Checks if the value of the field is `INTVCC`"] + #[inline(always)] + pub fn is_intvcc(&self) -> bool { + **self == REFSEL_A::INTVCC + } +} +impl core::ops::Deref for REFSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REFSEL` writer - Reference Selection"] +pub struct REFSEL_W<'a> { + w: &'a mut W, +} +impl<'a> REFSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: REFSEL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Internal Bandgap Reference"] + #[inline(always)] + pub fn intref(self) -> &'a mut W { + self.variant(REFSEL_A::INTREF) + } + #[doc = "External Reference"] + #[inline(always)] + pub fn arefb(self) -> &'a mut W { + self.variant(REFSEL_A::AREFB) + } + #[doc = "Internal DAC Output"] + #[inline(always)] + pub fn dac(self) -> &'a mut W { + self.variant(REFSEL_A::DAC) + } + #[doc = "VDDANA"] + #[inline(always)] + pub fn intvcc(self) -> &'a mut W { + self.variant(REFSEL_A::INTVCC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u8 & 0x03); + self.w + } +} +#[doc = "Field `REFRANGE` reader - Reference Range"] +pub struct REFRANGE_R(crate::FieldReader); +impl REFRANGE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REFRANGE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REFRANGE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REFRANGE` writer - Reference Range"] +pub struct REFRANGE_W<'a> { + w: &'a mut W, +} +impl<'a> REFRANGE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u8 & 0x03) << 4); + self.w + } +} +#[doc = "Field `ONREFBUF` reader - Reference Buffer"] +pub struct ONREFBUF_R(crate::FieldReader); +impl ONREFBUF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONREFBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONREFBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONREFBUF` writer - Reference Buffer"] +pub struct ONREFBUF_W<'a> { + w: &'a mut W, +} +impl<'a> ONREFBUF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Reference Selection"] + #[inline(always)] + pub fn refsel(&self) -> REFSEL_R { + REFSEL_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bits 4:5 - Reference Range"] + #[inline(always)] + pub fn refrange(&self) -> REFRANGE_R { + REFRANGE_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bit 7 - Reference Buffer"] + #[inline(always)] + pub fn onrefbuf(&self) -> ONREFBUF_R { + ONREFBUF_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:1 - Reference Selection"] + #[inline(always)] + pub fn refsel(&mut self) -> REFSEL_W { + REFSEL_W { w: self } + } + #[doc = "Bits 4:5 - Reference Range"] + #[inline(always)] + pub fn refrange(&mut self) -> REFRANGE_W { + REFRANGE_W { w: self } + } + #[doc = "Bit 7 - Reference Buffer"] + #[inline(always)] + pub fn onrefbuf(&mut self) -> ONREFBUF_W { + ONREFBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Reference Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [refctrl](index.html) module"] +pub struct REFCTRL_SPEC; +impl crate::RegisterSpec for REFCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [refctrl::R](R) reader structure"] +impl crate::Readable for REFCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [refctrl::W](W) writer structure"] +impl crate::Writable for REFCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets REFCTRL to value 0"] +impl crate::Resettable for REFCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sdadc/result.rs b/pac/atsamc21j/src/sdadc/result.rs new file mode 100644 index 000000000000..3f88d8b60ca6 --- /dev/null +++ b/pac/atsamc21j/src/sdadc/result.rs @@ -0,0 +1,53 @@ +#[doc = "Register `RESULT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `RESULT` reader - Result Value"] +pub struct RESULT_R(crate::FieldReader); +impl RESULT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + RESULT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESULT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:23 - Result Value"] + #[inline(always)] + pub fn result(&self) -> RESULT_R { + RESULT_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +#[doc = "Result\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [result](index.html) module"] +pub struct RESULT_SPEC; +impl crate::RegisterSpec for RESULT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [result::R](R) reader structure"] +impl crate::Readable for RESULT_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets RESULT to value 0"] +impl crate::Resettable for RESULT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sdadc/seqctrl.rs b/pac/atsamc21j/src/sdadc/seqctrl.rs new file mode 100644 index 000000000000..c8d1103959ee --- /dev/null +++ b/pac/atsamc21j/src/sdadc/seqctrl.rs @@ -0,0 +1,103 @@ +#[doc = "Register `SEQCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SEQCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SEQEN` reader - Enable Positive Input in the Sequence"] +pub struct SEQEN_R(crate::FieldReader); +impl SEQEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SEQEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEQEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEQEN` writer - Enable Positive Input in the Sequence"] +pub struct SEQEN_W<'a> { + w: &'a mut W, +} +impl<'a> SEQEN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Enable Positive Input in the Sequence"] + #[inline(always)] + pub fn seqen(&self) -> SEQEN_R { + SEQEN_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Enable Positive Input in the Sequence"] + #[inline(always)] + pub fn seqen(&mut self) -> SEQEN_W { + SEQEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Sequence Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [seqctrl](index.html) module"] +pub struct SEQCTRL_SPEC; +impl crate::RegisterSpec for SEQCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [seqctrl::R](R) reader structure"] +impl crate::Readable for SEQCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [seqctrl::W](W) writer structure"] +impl crate::Writable for SEQCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SEQCTRL to value 0"] +impl crate::Resettable for SEQCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sdadc/seqstatus.rs b/pac/atsamc21j/src/sdadc/seqstatus.rs new file mode 100644 index 000000000000..db10e7ca448e --- /dev/null +++ b/pac/atsamc21j/src/sdadc/seqstatus.rs @@ -0,0 +1,73 @@ +#[doc = "Register `SEQSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SEQSTATE` reader - Sequence State"] +pub struct SEQSTATE_R(crate::FieldReader); +impl SEQSTATE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SEQSTATE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEQSTATE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEQBUSY` reader - Sequence Busy"] +pub struct SEQBUSY_R(crate::FieldReader); +impl SEQBUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SEQBUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEQBUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:3 - Sequence State"] + #[inline(always)] + pub fn seqstate(&self) -> SEQSTATE_R { + SEQSTATE_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 7 - Sequence Busy"] + #[inline(always)] + pub fn seqbusy(&self) -> SEQBUSY_R { + SEQBUSY_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +#[doc = "Sequence Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [seqstatus](index.html) module"] +pub struct SEQSTATUS_SPEC; +impl crate::RegisterSpec for SEQSTATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [seqstatus::R](R) reader structure"] +impl crate::Readable for SEQSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SEQSTATUS to value 0"] +impl crate::Resettable for SEQSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sdadc/shiftcorr.rs b/pac/atsamc21j/src/sdadc/shiftcorr.rs new file mode 100644 index 000000000000..a5940537700e --- /dev/null +++ b/pac/atsamc21j/src/sdadc/shiftcorr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `SHIFTCORR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SHIFTCORR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SHIFTCORR` reader - Shift Correction Value"] +pub struct SHIFTCORR_R(crate::FieldReader); +impl SHIFTCORR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SHIFTCORR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SHIFTCORR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SHIFTCORR` writer - Shift Correction Value"] +pub struct SHIFTCORR_W<'a> { + w: &'a mut W, +} +impl<'a> SHIFTCORR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Shift Correction Value"] + #[inline(always)] + pub fn shiftcorr(&self) -> SHIFTCORR_R { + SHIFTCORR_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Shift Correction Value"] + #[inline(always)] + pub fn shiftcorr(&mut self) -> SHIFTCORR_W { + SHIFTCORR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Shift Correction\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [shiftcorr](index.html) module"] +pub struct SHIFTCORR_SPEC; +impl crate::RegisterSpec for SHIFTCORR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [shiftcorr::R](R) reader structure"] +impl crate::Readable for SHIFTCORR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [shiftcorr::W](W) writer structure"] +impl crate::Writable for SHIFTCORR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SHIFTCORR to value 0"] +impl crate::Resettable for SHIFTCORR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sdadc/swtrig.rs b/pac/atsamc21j/src/sdadc/swtrig.rs new file mode 100644 index 000000000000..7656a614dd67 --- /dev/null +++ b/pac/atsamc21j/src/sdadc/swtrig.rs @@ -0,0 +1,160 @@ +#[doc = "Register `SWTRIG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SWTRIG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FLUSH` reader - SDADC Flush"] +pub struct FLUSH_R(crate::FieldReader); +impl FLUSH_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FLUSH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FLUSH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLUSH` writer - SDADC Flush"] +pub struct FLUSH_W<'a> { + w: &'a mut W, +} +impl<'a> FLUSH_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `START` reader - Start SDADC Conversion"] +pub struct START_R(crate::FieldReader); +impl START_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + START_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for START_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `START` writer - Start SDADC Conversion"] +pub struct START_W<'a> { + w: &'a mut W, +} +impl<'a> START_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - SDADC Flush"] + #[inline(always)] + pub fn flush(&self) -> FLUSH_R { + FLUSH_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Start SDADC Conversion"] + #[inline(always)] + pub fn start(&self) -> START_R { + START_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - SDADC Flush"] + #[inline(always)] + pub fn flush(&mut self) -> FLUSH_W { + FLUSH_W { w: self } + } + #[doc = "Bit 1 - Start SDADC Conversion"] + #[inline(always)] + pub fn start(&mut self) -> START_W { + START_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Software Trigger\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [swtrig](index.html) module"] +pub struct SWTRIG_SPEC; +impl crate::RegisterSpec for SWTRIG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [swtrig::R](R) reader structure"] +impl crate::Readable for SWTRIG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [swtrig::W](W) writer structure"] +impl crate::Writable for SWTRIG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SWTRIG to value 0"] +impl crate::Resettable for SWTRIG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sdadc/syncbusy.rs b/pac/atsamc21j/src/sdadc/syncbusy.rs new file mode 100644 index 000000000000..519fa5e8a57f --- /dev/null +++ b/pac/atsamc21j/src/sdadc/syncbusy.rs @@ -0,0 +1,273 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - SWRST Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - ENABLE Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLC` reader - CTRLC Synchronization Busy"] +pub struct CTRLC_R(crate::FieldReader); +impl CTRLC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INPUTCTRL` reader - INPUTCTRL Synchronization Busy"] +pub struct INPUTCTRL_R(crate::FieldReader); +impl INPUTCTRL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INPUTCTRL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INPUTCTRL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINCTRL` reader - WINCTRL Synchronization Busy"] +pub struct WINCTRL_R(crate::FieldReader); +impl WINCTRL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINCTRL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINCTRL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINLT` reader - WINLT Synchronization Busy"] +pub struct WINLT_R(crate::FieldReader); +impl WINLT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINLT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINLT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINUT` reader - WINUT Synchronization Busy"] +pub struct WINUT_R(crate::FieldReader); +impl WINUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OFFSETCORR` reader - OFFSETCTRL Synchronization Busy"] +pub struct OFFSETCORR_R(crate::FieldReader); +impl OFFSETCORR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OFFSETCORR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OFFSETCORR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GAINCORR` reader - GAINCORR Synchronization Busy"] +pub struct GAINCORR_R(crate::FieldReader); +impl GAINCORR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GAINCORR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GAINCORR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SHIFTCORR` reader - SHIFTCORR Synchronization Busy"] +pub struct SHIFTCORR_R(crate::FieldReader); +impl SHIFTCORR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SHIFTCORR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SHIFTCORR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG` reader - SWTRG Synchronization Busy"] +pub struct SWTRIG_R(crate::FieldReader); +impl SWTRIG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ANACTRL` reader - ANACTRL Synchronization Busy"] +pub struct ANACTRL_R(crate::FieldReader); +impl ANACTRL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ANACTRL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ANACTRL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - SWRST Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ENABLE Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - CTRLC Synchronization Busy"] + #[inline(always)] + pub fn ctrlc(&self) -> CTRLC_R { + CTRLC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - INPUTCTRL Synchronization Busy"] + #[inline(always)] + pub fn inputctrl(&self) -> INPUTCTRL_R { + INPUTCTRL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - WINCTRL Synchronization Busy"] + #[inline(always)] + pub fn winctrl(&self) -> WINCTRL_R { + WINCTRL_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - WINLT Synchronization Busy"] + #[inline(always)] + pub fn winlt(&self) -> WINLT_R { + WINLT_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - WINUT Synchronization Busy"] + #[inline(always)] + pub fn winut(&self) -> WINUT_R { + WINUT_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - OFFSETCTRL Synchronization Busy"] + #[inline(always)] + pub fn offsetcorr(&self) -> OFFSETCORR_R { + OFFSETCORR_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - GAINCORR Synchronization Busy"] + #[inline(always)] + pub fn gaincorr(&self) -> GAINCORR_R { + GAINCORR_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - SHIFTCORR Synchronization Busy"] + #[inline(always)] + pub fn shiftcorr(&self) -> SHIFTCORR_R { + SHIFTCORR_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - SWTRG Synchronization Busy"] + #[inline(always)] + pub fn swtrig(&self) -> SWTRIG_R { + SWTRIG_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - ANACTRL Synchronization Busy"] + #[inline(always)] + pub fn anactrl(&self) -> ANACTRL_R { + ANACTRL_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +#[doc = "Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sdadc/winctrl.rs b/pac/atsamc21j/src/sdadc/winctrl.rs new file mode 100644 index 000000000000..ed0d2d4fe006 --- /dev/null +++ b/pac/atsamc21j/src/sdadc/winctrl.rs @@ -0,0 +1,103 @@ +#[doc = "Register `WINCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WINCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WINMODE` reader - Window Monitor Mode"] +pub struct WINMODE_R(crate::FieldReader); +impl WINMODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WINMODE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMODE` writer - Window Monitor Mode"] +pub struct WINMODE_W<'a> { + w: &'a mut W, +} +impl<'a> WINMODE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Window Monitor Mode"] + #[inline(always)] + pub fn winmode(&self) -> WINMODE_R { + WINMODE_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Window Monitor Mode"] + #[inline(always)] + pub fn winmode(&mut self) -> WINMODE_W { + WINMODE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Window Monitor Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [winctrl](index.html) module"] +pub struct WINCTRL_SPEC; +impl crate::RegisterSpec for WINCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [winctrl::R](R) reader structure"] +impl crate::Readable for WINCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [winctrl::W](W) writer structure"] +impl crate::Writable for WINCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WINCTRL to value 0"] +impl crate::Resettable for WINCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sdadc/winlt.rs b/pac/atsamc21j/src/sdadc/winlt.rs new file mode 100644 index 000000000000..be16283e9e36 --- /dev/null +++ b/pac/atsamc21j/src/sdadc/winlt.rs @@ -0,0 +1,103 @@ +#[doc = "Register `WINLT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WINLT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WINLT` reader - Window Lower Threshold"] +pub struct WINLT_R(crate::FieldReader); +impl WINLT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + WINLT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINLT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINLT` writer - Window Lower Threshold"] +pub struct WINLT_W<'a> { + w: &'a mut W, +} +impl<'a> WINLT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Window Lower Threshold"] + #[inline(always)] + pub fn winlt(&self) -> WINLT_R { + WINLT_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Window Lower Threshold"] + #[inline(always)] + pub fn winlt(&mut self) -> WINLT_W { + WINLT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Window Monitor Lower Threshold\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [winlt](index.html) module"] +pub struct WINLT_SPEC; +impl crate::RegisterSpec for WINLT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [winlt::R](R) reader structure"] +impl crate::Readable for WINLT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [winlt::W](W) writer structure"] +impl crate::Writable for WINLT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WINLT to value 0"] +impl crate::Resettable for WINLT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sdadc/winut.rs b/pac/atsamc21j/src/sdadc/winut.rs new file mode 100644 index 000000000000..7dc20e7c5f9e --- /dev/null +++ b/pac/atsamc21j/src/sdadc/winut.rs @@ -0,0 +1,103 @@ +#[doc = "Register `WINUT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WINUT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WINUT` reader - Window Upper Threshold"] +pub struct WINUT_R(crate::FieldReader); +impl WINUT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + WINUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINUT` writer - Window Upper Threshold"] +pub struct WINUT_W<'a> { + w: &'a mut W, +} +impl<'a> WINUT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Window Upper Threshold"] + #[inline(always)] + pub fn winut(&self) -> WINUT_R { + WINUT_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Window Upper Threshold"] + #[inline(always)] + pub fn winut(&mut self) -> WINUT_W { + WINUT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Window Monitor Upper Threshold\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [winut](index.html) module"] +pub struct WINUT_SPEC; +impl crate::RegisterSpec for WINUT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [winut::R](R) reader structure"] +impl crate::Readable for WINUT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [winut::W](W) writer structure"] +impl crate::Writable for WINUT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WINUT to value 0"] +impl crate::Resettable for WINUT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sercom0.rs b/pac/atsamc21j/src/sercom0.rs new file mode 100644 index 000000000000..da7b62f750c6 --- /dev/null +++ b/pac/atsamc21j/src/sercom0.rs @@ -0,0 +1,327 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved_0_i2cm: [u8; 0x31], +} +impl RegisterBlock { + #[doc = "0x00..0x31 - USART INTERNAL CLOCK Mode"] + #[inline(always)] + pub fn usart_int(&self) -> &USART_INT { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const USART_INT) } + } + #[doc = "0x00..0x31 - USART EXTERNAL CLOCK Mode"] + #[inline(always)] + pub fn usart_ext(&self) -> &USART_EXT { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const USART_EXT) } + } + #[doc = "0x00..0x31 - SPI Master Mode"] + #[inline(always)] + pub fn spim(&self) -> &SPIM { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const SPIM) } + } + #[doc = "0x00..0x31 - SPI Slave Mode"] + #[inline(always)] + pub fn spis(&self) -> &SPIS { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const SPIS) } + } + #[doc = "0x00..0x29 - I2C Slave Mode"] + #[inline(always)] + pub fn i2cs(&self) -> &I2CS { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const I2CS) } + } + #[doc = "0x00..0x31 - I2C Master Mode"] + #[inline(always)] + pub fn i2cm(&self) -> &I2CM { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const I2CM) } + } +} +#[doc = r"Register block"] +#[repr(C)] +pub struct I2CM { + #[doc = "0x00 - I2CM Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - I2CM Control B"] + pub ctrlb: crate::Reg, + _reserved2: [u8; 0x04], + #[doc = "0x0c - I2CM Baud Rate"] + pub baud: crate::Reg, + _reserved3: [u8; 0x04], + #[doc = "0x14 - I2CM Interrupt Enable Clear"] + pub intenclr: crate::Reg, + _reserved4: [u8; 0x01], + #[doc = "0x16 - I2CM Interrupt Enable Set"] + pub intenset: crate::Reg, + _reserved5: [u8; 0x01], + #[doc = "0x18 - I2CM Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x1a - I2CM Status"] + pub status: crate::Reg, + #[doc = "0x1c - I2CM Synchronization Busy"] + pub syncbusy: crate::Reg, + _reserved8: [u8; 0x04], + #[doc = "0x24 - I2CM Address"] + pub addr: crate::Reg, + #[doc = "0x28 - I2CM Data"] + pub data: crate::Reg, + _reserved10: [u8; 0x07], + #[doc = "0x30 - I2CM Debug Control"] + pub dbgctrl: crate::Reg, +} +#[doc = r"Register block"] +#[doc = "I2C Master Mode"] +pub mod i2cm; +#[doc = r"Register block"] +#[repr(C)] +pub struct I2CS { + #[doc = "0x00 - I2CS Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - I2CS Control B"] + pub ctrlb: crate::Reg, + _reserved2: [u8; 0x0c], + #[doc = "0x14 - I2CS Interrupt Enable Clear"] + pub intenclr: crate::Reg, + _reserved3: [u8; 0x01], + #[doc = "0x16 - I2CS Interrupt Enable Set"] + pub intenset: crate::Reg, + _reserved4: [u8; 0x01], + #[doc = "0x18 - I2CS Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved5: [u8; 0x01], + #[doc = "0x1a - I2CS Status"] + pub status: crate::Reg, + #[doc = "0x1c - I2CS Synchronization Busy"] + pub syncbusy: crate::Reg, + _reserved7: [u8; 0x04], + #[doc = "0x24 - I2CS Address"] + pub addr: crate::Reg, + #[doc = "0x28 - I2CS Data"] + pub data: crate::Reg, +} +#[doc = r"Register block"] +#[doc = "I2C Slave Mode"] +pub mod i2cs; +#[doc = r"Register block"] +#[repr(C)] +pub struct SPIS { + #[doc = "0x00 - SPIS Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - SPIS Control B"] + pub ctrlb: crate::Reg, + _reserved2: [u8; 0x04], + #[doc = "0x0c - SPIS Baud Rate"] + pub baud: crate::Reg, + _reserved3: [u8; 0x07], + #[doc = "0x14 - SPIS Interrupt Enable Clear"] + pub intenclr: crate::Reg, + _reserved4: [u8; 0x01], + #[doc = "0x16 - SPIS Interrupt Enable Set"] + pub intenset: crate::Reg, + _reserved5: [u8; 0x01], + #[doc = "0x18 - SPIS Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x1a - SPIS Status"] + pub status: crate::Reg, + #[doc = "0x1c - SPIS Synchronization Busy"] + pub syncbusy: crate::Reg, + _reserved8: [u8; 0x04], + #[doc = "0x24 - SPIS Address"] + pub addr: crate::Reg, + #[doc = "0x28 - SPIS Data"] + pub data: crate::Reg, + _reserved10: [u8; 0x04], + #[doc = "0x30 - SPIS Debug Control"] + pub dbgctrl: crate::Reg, +} +#[doc = r"Register block"] +#[doc = "SPI Slave Mode"] +pub mod spis; +#[doc = r"Register block"] +#[repr(C)] +pub struct SPIM { + #[doc = "0x00 - SPIM Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - SPIM Control B"] + pub ctrlb: crate::Reg, + _reserved2: [u8; 0x04], + #[doc = "0x0c - SPIM Baud Rate"] + pub baud: crate::Reg, + _reserved3: [u8; 0x07], + #[doc = "0x14 - SPIM Interrupt Enable Clear"] + pub intenclr: crate::Reg, + _reserved4: [u8; 0x01], + #[doc = "0x16 - SPIM Interrupt Enable Set"] + pub intenset: crate::Reg, + _reserved5: [u8; 0x01], + #[doc = "0x18 - SPIM Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x1a - SPIM Status"] + pub status: crate::Reg, + #[doc = "0x1c - SPIM Synchronization Busy"] + pub syncbusy: crate::Reg, + _reserved8: [u8; 0x04], + #[doc = "0x24 - SPIM Address"] + pub addr: crate::Reg, + #[doc = "0x28 - SPIM Data"] + pub data: crate::Reg, + _reserved10: [u8; 0x04], + #[doc = "0x30 - SPIM Debug Control"] + pub dbgctrl: crate::Reg, +} +#[doc = r"Register block"] +#[doc = "SPI Master Mode"] +pub mod spim; +#[doc = r"Register block"] +#[repr(C)] +pub struct USART_EXT { + #[doc = "0x00 - USART_EXT Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - USART_EXT Control B"] + pub ctrlb: crate::Reg, + #[doc = "0x08 - USART_EXT Control C"] + pub ctrlc: crate::Reg, + _reserved_3_baud: [u8; 0x02], + #[doc = "0x0e - USART_EXT Receive Pulse Length"] + pub rxpl: crate::Reg, + _reserved5: [u8; 0x05], + #[doc = "0x14 - USART_EXT Interrupt Enable Clear"] + pub intenclr: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x16 - USART_EXT Interrupt Enable Set"] + pub intenset: crate::Reg, + _reserved7: [u8; 0x01], + #[doc = "0x18 - USART_EXT Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved8: [u8; 0x01], + #[doc = "0x1a - USART_EXT Status"] + pub status: crate::Reg, + #[doc = "0x1c - USART_EXT Synchronization Busy"] + pub syncbusy: crate::Reg, + _reserved10: [u8; 0x08], + #[doc = "0x28 - USART_EXT Data"] + pub data: crate::Reg, + _reserved11: [u8; 0x06], + #[doc = "0x30 - USART_EXT Debug Control"] + pub dbgctrl: crate::Reg, +} +impl USART_EXT { + #[doc = "0x0c - USART_EXT Baud Rate"] + #[inline(always)] + pub fn baud_usartfp_mode( + &self, + ) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } + #[doc = "0x0c - USART_EXT Baud Rate"] + #[inline(always)] + pub fn baud_fracfp_mode( + &self, + ) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } + #[doc = "0x0c - USART_EXT Baud Rate"] + #[inline(always)] + pub fn baud_frac_mode( + &self, + ) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } + #[doc = "0x0c - USART_EXT Baud Rate"] + #[inline(always)] + pub fn baud(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } +} +#[doc = r"Register block"] +#[doc = "USART EXTERNAL CLOCK Mode"] +pub mod usart_ext; +#[doc = r"Register block"] +#[repr(C)] +pub struct USART_INT { + #[doc = "0x00 - USART_INT Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - USART_INT Control B"] + pub ctrlb: crate::Reg, + #[doc = "0x08 - USART_INT Control C"] + pub ctrlc: crate::Reg, + _reserved_3_baud: [u8; 0x02], + #[doc = "0x0e - USART_INT Receive Pulse Length"] + pub rxpl: crate::Reg, + _reserved5: [u8; 0x05], + #[doc = "0x14 - USART_INT Interrupt Enable Clear"] + pub intenclr: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x16 - USART_INT Interrupt Enable Set"] + pub intenset: crate::Reg, + _reserved7: [u8; 0x01], + #[doc = "0x18 - USART_INT Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved8: [u8; 0x01], + #[doc = "0x1a - USART_INT Status"] + pub status: crate::Reg, + #[doc = "0x1c - USART_INT Synchronization Busy"] + pub syncbusy: crate::Reg, + _reserved10: [u8; 0x08], + #[doc = "0x28 - USART_INT Data"] + pub data: crate::Reg, + _reserved11: [u8; 0x06], + #[doc = "0x30 - USART_INT Debug Control"] + pub dbgctrl: crate::Reg, +} +impl USART_INT { + #[doc = "0x0c - USART_INT Baud Rate"] + #[inline(always)] + pub fn baud_usartfp_mode( + &self, + ) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } + #[doc = "0x0c - USART_INT Baud Rate"] + #[inline(always)] + pub fn baud_fracfp_mode( + &self, + ) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } + #[doc = "0x0c - USART_INT Baud Rate"] + #[inline(always)] + pub fn baud_frac_mode( + &self, + ) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } + #[doc = "0x0c - USART_INT Baud Rate"] + #[inline(always)] + pub fn baud(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } +} +#[doc = r"Register block"] +#[doc = "USART INTERNAL CLOCK Mode"] +pub mod usart_int; diff --git a/pac/atsamc21j/src/sercom0/i2cm.rs b/pac/atsamc21j/src/sercom0/i2cm.rs new file mode 100644 index 000000000000..8aa217da8b18 --- /dev/null +++ b/pac/atsamc21j/src/sercom0/i2cm.rs @@ -0,0 +1,44 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "I2CM Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "I2CM Control B"] +pub mod ctrlb; +#[doc = "BAUD register accessor: an alias for `Reg`"] +pub type BAUD = crate::Reg; +#[doc = "I2CM Baud Rate"] +pub mod baud; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "I2CM Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "I2CM Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "I2CM Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "I2CM Status"] +pub mod status; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "I2CM Synchronization Busy"] +pub mod syncbusy; +#[doc = "ADDR register accessor: an alias for `Reg`"] +pub type ADDR = crate::Reg; +#[doc = "I2CM Address"] +pub mod addr; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "I2CM Data"] +pub mod data; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "I2CM Debug Control"] +pub mod dbgctrl; diff --git a/pac/atsamc21j/src/sercom0/i2cm/addr.rs b/pac/atsamc21j/src/sercom0/i2cm/addr.rs new file mode 100644 index 000000000000..4efd19e824c6 --- /dev/null +++ b/pac/atsamc21j/src/sercom0/i2cm/addr.rs @@ -0,0 +1,281 @@ +#[doc = "Register `ADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ADDR` reader - Address Value"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - Address Value"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07ff) | (value as u32 & 0x07ff); + self.w + } +} +#[doc = "Field `LENEN` reader - Length Enable"] +pub struct LENEN_R(crate::FieldReader); +impl LENEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LENEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LENEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LENEN` writer - Length Enable"] +pub struct LENEN_W<'a> { + w: &'a mut W, +} +impl<'a> LENEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `HS` reader - High Speed Mode"] +pub struct HS_R(crate::FieldReader); +impl HS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HS` writer - High Speed Mode"] +pub struct HS_W<'a> { + w: &'a mut W, +} +impl<'a> HS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `TENBITEN` reader - Ten Bit Addressing Enable"] +pub struct TENBITEN_R(crate::FieldReader); +impl TENBITEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TENBITEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TENBITEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TENBITEN` writer - Ten Bit Addressing Enable"] +pub struct TENBITEN_W<'a> { + w: &'a mut W, +} +impl<'a> TENBITEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `LEN` reader - Length"] +pub struct LEN_R(crate::FieldReader); +impl LEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LEN` writer - Length"] +pub struct LEN_W<'a> { + w: &'a mut W, +} +impl<'a> LEN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:10 - Address Value"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new((self.bits & 0x07ff) as u16) + } + #[doc = "Bit 13 - Length Enable"] + #[inline(always)] + pub fn lenen(&self) -> LENEN_R { + LENEN_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - High Speed Mode"] + #[inline(always)] + pub fn hs(&self) -> HS_R { + HS_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Ten Bit Addressing Enable"] + #[inline(always)] + pub fn tenbiten(&self) -> TENBITEN_R { + TENBITEN_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:23 - Length"] + #[inline(always)] + pub fn len(&self) -> LEN_R { + LEN_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:10 - Address Value"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Bit 13 - Length Enable"] + #[inline(always)] + pub fn lenen(&mut self) -> LENEN_W { + LENEN_W { w: self } + } + #[doc = "Bit 14 - High Speed Mode"] + #[inline(always)] + pub fn hs(&mut self) -> HS_W { + HS_W { w: self } + } + #[doc = "Bit 15 - Ten Bit Addressing Enable"] + #[inline(always)] + pub fn tenbiten(&mut self) -> TENBITEN_W { + TENBITEN_W { w: self } + } + #[doc = "Bits 16:23 - Length"] + #[inline(always)] + pub fn len(&mut self) -> LEN_W { + LEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [addr](index.html) module"] +pub struct ADDR_SPEC; +impl crate::RegisterSpec for ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [addr::R](R) reader structure"] +impl crate::Readable for ADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [addr::W](W) writer structure"] +impl crate::Writable for ADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ADDR to value 0"] +impl crate::Resettable for ADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sercom0/i2cm/baud.rs b/pac/atsamc21j/src/sercom0/i2cm/baud.rs new file mode 100644 index 000000000000..7c98d3b5b0de --- /dev/null +++ b/pac/atsamc21j/src/sercom0/i2cm/baud.rs @@ -0,0 +1,214 @@ +#[doc = "Register `BAUD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +#[doc = "Field `BAUDLOW` reader - Baud Rate Value Low"] +pub struct BAUDLOW_R(crate::FieldReader); +impl BAUDLOW_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BAUDLOW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUDLOW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUDLOW` writer - Baud Rate Value Low"] +pub struct BAUDLOW_W<'a> { + w: &'a mut W, +} +impl<'a> BAUDLOW_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +#[doc = "Field `HSBAUD` reader - High Speed Baud Rate Value"] +pub struct HSBAUD_R(crate::FieldReader); +impl HSBAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + HSBAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HSBAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HSBAUD` writer - High Speed Baud Rate Value"] +pub struct HSBAUD_W<'a> { + w: &'a mut W, +} +impl<'a> HSBAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +#[doc = "Field `HSBAUDLOW` reader - High Speed Baud Rate Value Low"] +pub struct HSBAUDLOW_R(crate::FieldReader); +impl HSBAUDLOW_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + HSBAUDLOW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HSBAUDLOW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HSBAUDLOW` writer - High Speed Baud Rate Value Low"] +pub struct HSBAUDLOW_W<'a> { + w: &'a mut W, +} +impl<'a> HSBAUDLOW_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 24)) | ((value as u32 & 0xff) << 24); + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Baud Rate Value Low"] + #[inline(always)] + pub fn baudlow(&self) -> BAUDLOW_R { + BAUDLOW_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - High Speed Baud Rate Value"] + #[inline(always)] + pub fn hsbaud(&self) -> HSBAUD_R { + HSBAUD_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - High Speed Baud Rate Value Low"] + #[inline(always)] + pub fn hsbaudlow(&self) -> HSBAUDLOW_R { + HSBAUDLOW_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Bits 8:15 - Baud Rate Value Low"] + #[inline(always)] + pub fn baudlow(&mut self) -> BAUDLOW_W { + BAUDLOW_W { w: self } + } + #[doc = "Bits 16:23 - High Speed Baud Rate Value"] + #[inline(always)] + pub fn hsbaud(&mut self) -> HSBAUD_W { + HSBAUD_W { w: self } + } + #[doc = "Bits 24:31 - High Speed Baud Rate Value Low"] + #[inline(always)] + pub fn hsbaudlow(&mut self) -> HSBAUDLOW_W { + HSBAUDLOW_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud](index.html) module"] +pub struct BAUD_SPEC; +impl crate::RegisterSpec for BAUD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [baud::R](R) reader structure"] +impl crate::Readable for BAUD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud::W](W) writer structure"] +impl crate::Writable for BAUD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD to value 0"] +impl crate::Resettable for BAUD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sercom0/i2cm/ctrla.rs b/pac/atsamc21j/src/sercom0/i2cm/ctrla.rs new file mode 100644 index 000000000000..34fa668b7967 --- /dev/null +++ b/pac/atsamc21j/src/sercom0/i2cm/ctrla.rs @@ -0,0 +1,903 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: USART with external clock"] + USART_EXT_CLK = 0, + #[doc = "1: USART with internal clock"] + USART_INT_CLK = 1, + #[doc = "2: SPI in slave operation"] + SPI_SLAVE = 2, + #[doc = "3: SPI in master operation"] + SPI_MASTER = 3, + #[doc = "4: I2C slave operation"] + I2C_SLAVE = 4, + #[doc = "5: I2C master operation"] + I2C_MASTER = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::USART_EXT_CLK), + 1 => Some(MODE_A::USART_INT_CLK), + 2 => Some(MODE_A::SPI_SLAVE), + 3 => Some(MODE_A::SPI_MASTER), + 4 => Some(MODE_A::I2C_SLAVE), + 5 => Some(MODE_A::I2C_MASTER), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_EXT_CLK`"] + #[inline(always)] + pub fn is_usart_ext_clk(&self) -> bool { + **self == MODE_A::USART_EXT_CLK + } + #[doc = "Checks if the value of the field is `USART_INT_CLK`"] + #[inline(always)] + pub fn is_usart_int_clk(&self) -> bool { + **self == MODE_A::USART_INT_CLK + } + #[doc = "Checks if the value of the field is `SPI_SLAVE`"] + #[inline(always)] + pub fn is_spi_slave(&self) -> bool { + **self == MODE_A::SPI_SLAVE + } + #[doc = "Checks if the value of the field is `SPI_MASTER`"] + #[inline(always)] + pub fn is_spi_master(&self) -> bool { + **self == MODE_A::SPI_MASTER + } + #[doc = "Checks if the value of the field is `I2C_SLAVE`"] + #[inline(always)] + pub fn is_i2c_slave(&self) -> bool { + **self == MODE_A::I2C_SLAVE + } + #[doc = "Checks if the value of the field is `I2C_MASTER`"] + #[inline(always)] + pub fn is_i2c_master(&self) -> bool { + **self == MODE_A::I2C_MASTER + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART with external clock"] + #[inline(always)] + pub fn usart_ext_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_EXT_CLK) + } + #[doc = "USART with internal clock"] + #[inline(always)] + pub fn usart_int_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_INT_CLK) + } + #[doc = "SPI in slave operation"] + #[inline(always)] + pub fn spi_slave(self) -> &'a mut W { + self.variant(MODE_A::SPI_SLAVE) + } + #[doc = "SPI in master operation"] + #[inline(always)] + pub fn spi_master(self) -> &'a mut W { + self.variant(MODE_A::SPI_MASTER) + } + #[doc = "I2C slave operation"] + #[inline(always)] + pub fn i2c_slave(self) -> &'a mut W { + self.variant(MODE_A::I2C_SLAVE) + } + #[doc = "I2C master operation"] + #[inline(always)] + pub fn i2c_master(self) -> &'a mut W { + self.variant(MODE_A::I2C_MASTER) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 2)) | ((value as u32 & 0x07) << 2); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `PINOUT` reader - Pin Usage"] +pub struct PINOUT_R(crate::FieldReader); +impl PINOUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PINOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PINOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PINOUT` writer - Pin Usage"] +pub struct PINOUT_W<'a> { + w: &'a mut W, +} +impl<'a> PINOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "SDA Hold Time\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SDAHOLD_A { + #[doc = "0: Disabled"] + DISABLE = 0, + #[doc = "1: 50-100ns hold time"] + _75NS = 1, + #[doc = "2: 300-600ns hold time"] + _450NS = 2, + #[doc = "3: 400-800ns hold time"] + _600NS = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SDAHOLD_A) -> Self { + variant as _ + } +} +#[doc = "Field `SDAHOLD` reader - SDA Hold Time"] +pub struct SDAHOLD_R(crate::FieldReader); +impl SDAHOLD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SDAHOLD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SDAHOLD_A { + match self.bits { + 0 => SDAHOLD_A::DISABLE, + 1 => SDAHOLD_A::_75NS, + 2 => SDAHOLD_A::_450NS, + 3 => SDAHOLD_A::_600NS, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == SDAHOLD_A::DISABLE + } + #[doc = "Checks if the value of the field is `_75NS`"] + #[inline(always)] + pub fn is_75ns(&self) -> bool { + **self == SDAHOLD_A::_75NS + } + #[doc = "Checks if the value of the field is `_450NS`"] + #[inline(always)] + pub fn is_450ns(&self) -> bool { + **self == SDAHOLD_A::_450NS + } + #[doc = "Checks if the value of the field is `_600NS`"] + #[inline(always)] + pub fn is_600ns(&self) -> bool { + **self == SDAHOLD_A::_600NS + } +} +impl core::ops::Deref for SDAHOLD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SDAHOLD` writer - SDA Hold Time"] +pub struct SDAHOLD_W<'a> { + w: &'a mut W, +} +impl<'a> SDAHOLD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SDAHOLD_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(SDAHOLD_A::DISABLE) + } + #[doc = "50-100ns hold time"] + #[inline(always)] + pub fn _75ns(self) -> &'a mut W { + self.variant(SDAHOLD_A::_75NS) + } + #[doc = "300-600ns hold time"] + #[inline(always)] + pub fn _450ns(self) -> &'a mut W { + self.variant(SDAHOLD_A::_450NS) + } + #[doc = "400-800ns hold time"] + #[inline(always)] + pub fn _600ns(self) -> &'a mut W { + self.variant(SDAHOLD_A::_600NS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 20)) | ((value as u32 & 0x03) << 20); + self.w + } +} +#[doc = "Field `MEXTTOEN` reader - Master SCL Low Extend Timeout"] +pub struct MEXTTOEN_R(crate::FieldReader); +impl MEXTTOEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MEXTTOEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MEXTTOEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MEXTTOEN` writer - Master SCL Low Extend Timeout"] +pub struct MEXTTOEN_W<'a> { + w: &'a mut W, +} +impl<'a> MEXTTOEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `SEXTTOEN` reader - Slave SCL Low Extend Timeout"] +pub struct SEXTTOEN_R(crate::FieldReader); +impl SEXTTOEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SEXTTOEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEXTTOEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEXTTOEN` writer - Slave SCL Low Extend Timeout"] +pub struct SEXTTOEN_W<'a> { + w: &'a mut W, +} +impl<'a> SEXTTOEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Transfer Speed\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SPEED_A { + #[doc = "0: Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz"] + STANDARD_AND_FAST_MODE = 0, + #[doc = "1: Fast-mode Plus Upto 1MHz"] + FASTPLUS_MODE = 1, + #[doc = "2: High-speed mode Upto 3.4MHz"] + HIGH_SPEED_MODE = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SPEED_A) -> Self { + variant as _ + } +} +#[doc = "Field `SPEED` reader - Transfer Speed"] +pub struct SPEED_R(crate::FieldReader); +impl SPEED_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SPEED_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SPEED_A::STANDARD_AND_FAST_MODE), + 1 => Some(SPEED_A::FASTPLUS_MODE), + 2 => Some(SPEED_A::HIGH_SPEED_MODE), + _ => None, + } + } + #[doc = "Checks if the value of the field is `STANDARD_AND_FAST_MODE`"] + #[inline(always)] + pub fn is_standard_and_fast_mode(&self) -> bool { + **self == SPEED_A::STANDARD_AND_FAST_MODE + } + #[doc = "Checks if the value of the field is `FASTPLUS_MODE`"] + #[inline(always)] + pub fn is_fastplus_mode(&self) -> bool { + **self == SPEED_A::FASTPLUS_MODE + } + #[doc = "Checks if the value of the field is `HIGH_SPEED_MODE`"] + #[inline(always)] + pub fn is_high_speed_mode(&self) -> bool { + **self == SPEED_A::HIGH_SPEED_MODE + } +} +impl core::ops::Deref for SPEED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SPEED` writer - Transfer Speed"] +pub struct SPEED_W<'a> { + w: &'a mut W, +} +impl<'a> SPEED_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SPEED_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz"] + #[inline(always)] + pub fn standard_and_fast_mode(self) -> &'a mut W { + self.variant(SPEED_A::STANDARD_AND_FAST_MODE) + } + #[doc = "Fast-mode Plus Upto 1MHz"] + #[inline(always)] + pub fn fastplus_mode(self) -> &'a mut W { + self.variant(SPEED_A::FASTPLUS_MODE) + } + #[doc = "High-speed mode Upto 3.4MHz"] + #[inline(always)] + pub fn high_speed_mode(self) -> &'a mut W { + self.variant(SPEED_A::HIGH_SPEED_MODE) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 24)) | ((value as u32 & 0x03) << 24); + self.w + } +} +#[doc = "Field `SCLSM` reader - SCL Clock Stretch Mode"] +pub struct SCLSM_R(crate::FieldReader); +impl SCLSM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SCLSM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SCLSM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SCLSM` writer - SCL Clock Stretch Mode"] +pub struct SCLSM_W<'a> { + w: &'a mut W, +} +impl<'a> SCLSM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +#[doc = "Inactive Time-Out\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum INACTOUT_A { + #[doc = "0: Disabled"] + DISABLE = 0, + #[doc = "1: 5-6 SCL Time-Out(50-60us)"] + _55US = 1, + #[doc = "2: 10-11 SCL Time-Out(100-110us)"] + _105US = 2, + #[doc = "3: 20-21 SCL Time-Out(200-210us)"] + _205US = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: INACTOUT_A) -> Self { + variant as _ + } +} +#[doc = "Field `INACTOUT` reader - Inactive Time-Out"] +pub struct INACTOUT_R(crate::FieldReader); +impl INACTOUT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + INACTOUT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INACTOUT_A { + match self.bits { + 0 => INACTOUT_A::DISABLE, + 1 => INACTOUT_A::_55US, + 2 => INACTOUT_A::_105US, + 3 => INACTOUT_A::_205US, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == INACTOUT_A::DISABLE + } + #[doc = "Checks if the value of the field is `_55US`"] + #[inline(always)] + pub fn is_55us(&self) -> bool { + **self == INACTOUT_A::_55US + } + #[doc = "Checks if the value of the field is `_105US`"] + #[inline(always)] + pub fn is_105us(&self) -> bool { + **self == INACTOUT_A::_105US + } + #[doc = "Checks if the value of the field is `_205US`"] + #[inline(always)] + pub fn is_205us(&self) -> bool { + **self == INACTOUT_A::_205US + } +} +impl core::ops::Deref for INACTOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INACTOUT` writer - Inactive Time-Out"] +pub struct INACTOUT_W<'a> { + w: &'a mut W, +} +impl<'a> INACTOUT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: INACTOUT_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(INACTOUT_A::DISABLE) + } + #[doc = "5-6 SCL Time-Out(50-60us)"] + #[inline(always)] + pub fn _55us(self) -> &'a mut W { + self.variant(INACTOUT_A::_55US) + } + #[doc = "10-11 SCL Time-Out(100-110us)"] + #[inline(always)] + pub fn _105us(self) -> &'a mut W { + self.variant(INACTOUT_A::_105US) + } + #[doc = "20-21 SCL Time-Out(200-210us)"] + #[inline(always)] + pub fn _205us(self) -> &'a mut W { + self.variant(INACTOUT_A::_205US) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 28)) | ((value as u32 & 0x03) << 28); + self.w + } +} +#[doc = "Field `LOWTOUTEN` reader - SCL Low Timeout Enable"] +pub struct LOWTOUTEN_R(crate::FieldReader); +impl LOWTOUTEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LOWTOUTEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOWTOUTEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LOWTOUTEN` writer - SCL Low Timeout Enable"] +pub struct LOWTOUTEN_W<'a> { + w: &'a mut W, +} +impl<'a> LOWTOUTEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x07) as u8) + } + #[doc = "Bit 7 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 16 - Pin Usage"] + #[inline(always)] + pub fn pinout(&self) -> PINOUT_R { + PINOUT_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bits 20:21 - SDA Hold Time"] + #[inline(always)] + pub fn sdahold(&self) -> SDAHOLD_R { + SDAHOLD_R::new(((self.bits >> 20) & 0x03) as u8) + } + #[doc = "Bit 22 - Master SCL Low Extend Timeout"] + #[inline(always)] + pub fn mexttoen(&self) -> MEXTTOEN_R { + MEXTTOEN_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttoen(&self) -> SEXTTOEN_R { + SEXTTOEN_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bits 24:25 - Transfer Speed"] + #[inline(always)] + pub fn speed(&self) -> SPEED_R { + SPEED_R::new(((self.bits >> 24) & 0x03) as u8) + } + #[doc = "Bit 27 - SCL Clock Stretch Mode"] + #[inline(always)] + pub fn sclsm(&self) -> SCLSM_R { + SCLSM_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bits 28:29 - Inactive Time-Out"] + #[inline(always)] + pub fn inactout(&self) -> INACTOUT_R { + INACTOUT_R::new(((self.bits >> 28) & 0x03) as u8) + } + #[doc = "Bit 30 - SCL Low Timeout Enable"] + #[inline(always)] + pub fn lowtouten(&self) -> LOWTOUTEN_R { + LOWTOUTEN_R::new(((self.bits >> 30) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 7 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 16 - Pin Usage"] + #[inline(always)] + pub fn pinout(&mut self) -> PINOUT_W { + PINOUT_W { w: self } + } + #[doc = "Bits 20:21 - SDA Hold Time"] + #[inline(always)] + pub fn sdahold(&mut self) -> SDAHOLD_W { + SDAHOLD_W { w: self } + } + #[doc = "Bit 22 - Master SCL Low Extend Timeout"] + #[inline(always)] + pub fn mexttoen(&mut self) -> MEXTTOEN_W { + MEXTTOEN_W { w: self } + } + #[doc = "Bit 23 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttoen(&mut self) -> SEXTTOEN_W { + SEXTTOEN_W { w: self } + } + #[doc = "Bits 24:25 - Transfer Speed"] + #[inline(always)] + pub fn speed(&mut self) -> SPEED_W { + SPEED_W { w: self } + } + #[doc = "Bit 27 - SCL Clock Stretch Mode"] + #[inline(always)] + pub fn sclsm(&mut self) -> SCLSM_W { + SCLSM_W { w: self } + } + #[doc = "Bits 28:29 - Inactive Time-Out"] + #[inline(always)] + pub fn inactout(&mut self) -> INACTOUT_W { + INACTOUT_W { w: self } + } + #[doc = "Bit 30 - SCL Low Timeout Enable"] + #[inline(always)] + pub fn lowtouten(&mut self) -> LOWTOUTEN_W { + LOWTOUTEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sercom0/i2cm/ctrlb.rs b/pac/atsamc21j/src/sercom0/i2cm/ctrlb.rs new file mode 100644 index 000000000000..ce534463c0da --- /dev/null +++ b/pac/atsamc21j/src/sercom0/i2cm/ctrlb.rs @@ -0,0 +1,244 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SMEN` reader - Smart Mode Enable"] +pub struct SMEN_R(crate::FieldReader); +impl SMEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SMEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SMEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SMEN` writer - Smart Mode Enable"] +pub struct SMEN_W<'a> { + w: &'a mut W, +} +impl<'a> SMEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `QCEN` reader - Quick Command Enable"] +pub struct QCEN_R(crate::FieldReader); +impl QCEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + QCEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for QCEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `QCEN` writer - Quick Command Enable"] +pub struct QCEN_W<'a> { + w: &'a mut W, +} +impl<'a> QCEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Field `ACKACT` reader - Acknowledge Action"] +pub struct ACKACT_R(crate::FieldReader); +impl ACKACT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ACKACT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ACKACT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ACKACT` writer - Acknowledge Action"] +pub struct ACKACT_W<'a> { + w: &'a mut W, +} +impl<'a> ACKACT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +impl R { + #[doc = "Bit 8 - Smart Mode Enable"] + #[inline(always)] + pub fn smen(&self) -> SMEN_R { + SMEN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Quick Command Enable"] + #[inline(always)] + pub fn qcen(&self) -> QCEN_R { + QCEN_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bits 16:17 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bit 18 - Acknowledge Action"] + #[inline(always)] + pub fn ackact(&self) -> ACKACT_R { + ACKACT_R::new(((self.bits >> 18) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 8 - Smart Mode Enable"] + #[inline(always)] + pub fn smen(&mut self) -> SMEN_W { + SMEN_W { w: self } + } + #[doc = "Bit 9 - Quick Command Enable"] + #[inline(always)] + pub fn qcen(&mut self) -> QCEN_W { + QCEN_W { w: self } + } + #[doc = "Bits 16:17 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Bit 18 - Acknowledge Action"] + #[inline(always)] + pub fn ackact(&mut self) -> ACKACT_W { + ACKACT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sercom0/i2cm/data.rs b/pac/atsamc21j/src/sercom0/i2cm/data.rs new file mode 100644 index 000000000000..cf204596d3a6 --- /dev/null +++ b/pac/atsamc21j/src/sercom0/i2cm/data.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data Value"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data Value"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Data Value"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Value"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sercom0/i2cm/dbgctrl.rs b/pac/atsamc21j/src/sercom0/i2cm/dbgctrl.rs new file mode 100644 index 000000000000..0fffdb4c6e39 --- /dev/null +++ b/pac/atsamc21j/src/sercom0/i2cm/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGSTOP` reader - Debug Mode"] +pub struct DBGSTOP_R(crate::FieldReader); +impl DBGSTOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGSTOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGSTOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGSTOP` writer - Debug Mode"] +pub struct DBGSTOP_W<'a> { + w: &'a mut W, +} +impl<'a> DBGSTOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&self) -> DBGSTOP_R { + DBGSTOP_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&mut self) -> DBGSTOP_W { + DBGSTOP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sercom0/i2cm/intenclr.rs b/pac/atsamc21j/src/sercom0/i2cm/intenclr.rs new file mode 100644 index 000000000000..17f067a55656 --- /dev/null +++ b/pac/atsamc21j/src/sercom0/i2cm/intenclr.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MB` reader - Master On Bus Interrupt Disable"] +pub struct MB_R(crate::FieldReader); +impl MB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MB` writer - Master On Bus Interrupt Disable"] +pub struct MB_W<'a> { + w: &'a mut W, +} +impl<'a> MB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SB` reader - Slave On Bus Interrupt Disable"] +pub struct SB_R(crate::FieldReader); +impl SB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SB` writer - Slave On Bus Interrupt Disable"] +pub struct SB_W<'a> { + w: &'a mut W, +} +impl<'a> SB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Disable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Disable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Master On Bus Interrupt Disable"] + #[inline(always)] + pub fn mb(&self) -> MB_R { + MB_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Slave On Bus Interrupt Disable"] + #[inline(always)] + pub fn sb(&self) -> SB_R { + SB_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Master On Bus Interrupt Disable"] + #[inline(always)] + pub fn mb(&mut self) -> MB_W { + MB_W { w: self } + } + #[doc = "Bit 1 - Slave On Bus Interrupt Disable"] + #[inline(always)] + pub fn sb(&mut self) -> SB_W { + SB_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sercom0/i2cm/intenset.rs b/pac/atsamc21j/src/sercom0/i2cm/intenset.rs new file mode 100644 index 000000000000..a0cbf96b3aa0 --- /dev/null +++ b/pac/atsamc21j/src/sercom0/i2cm/intenset.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MB` reader - Master On Bus Interrupt Enable"] +pub struct MB_R(crate::FieldReader); +impl MB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MB` writer - Master On Bus Interrupt Enable"] +pub struct MB_W<'a> { + w: &'a mut W, +} +impl<'a> MB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SB` reader - Slave On Bus Interrupt Enable"] +pub struct SB_R(crate::FieldReader); +impl SB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SB` writer - Slave On Bus Interrupt Enable"] +pub struct SB_W<'a> { + w: &'a mut W, +} +impl<'a> SB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Master On Bus Interrupt Enable"] + #[inline(always)] + pub fn mb(&self) -> MB_R { + MB_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Slave On Bus Interrupt Enable"] + #[inline(always)] + pub fn sb(&self) -> SB_R { + SB_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Master On Bus Interrupt Enable"] + #[inline(always)] + pub fn mb(&mut self) -> MB_W { + MB_W { w: self } + } + #[doc = "Bit 1 - Slave On Bus Interrupt Enable"] + #[inline(always)] + pub fn sb(&mut self) -> SB_W { + SB_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sercom0/i2cm/intflag.rs b/pac/atsamc21j/src/sercom0/i2cm/intflag.rs new file mode 100644 index 000000000000..0fb0d2b9060c --- /dev/null +++ b/pac/atsamc21j/src/sercom0/i2cm/intflag.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MB` reader - Master On Bus Interrupt"] +pub struct MB_R(crate::FieldReader); +impl MB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MB` writer - Master On Bus Interrupt"] +pub struct MB_W<'a> { + w: &'a mut W, +} +impl<'a> MB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SB` reader - Slave On Bus Interrupt"] +pub struct SB_R(crate::FieldReader); +impl SB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SB` writer - Slave On Bus Interrupt"] +pub struct SB_W<'a> { + w: &'a mut W, +} +impl<'a> SB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Master On Bus Interrupt"] + #[inline(always)] + pub fn mb(&self) -> MB_R { + MB_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Slave On Bus Interrupt"] + #[inline(always)] + pub fn sb(&self) -> SB_R { + SB_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Master On Bus Interrupt"] + #[inline(always)] + pub fn mb(&mut self) -> MB_W { + MB_W { w: self } + } + #[doc = "Bit 1 - Slave On Bus Interrupt"] + #[inline(always)] + pub fn sb(&mut self) -> SB_W { + SB_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sercom0/i2cm/status.rs b/pac/atsamc21j/src/sercom0/i2cm/status.rs new file mode 100644 index 000000000000..95af23673ec4 --- /dev/null +++ b/pac/atsamc21j/src/sercom0/i2cm/status.rs @@ -0,0 +1,479 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BUSERR` reader - Bus Error"] +pub struct BUSERR_R(crate::FieldReader); +impl BUSERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSERR` writer - Bus Error"] +pub struct BUSERR_W<'a> { + w: &'a mut W, +} +impl<'a> BUSERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `ARBLOST` reader - Arbitration Lost"] +pub struct ARBLOST_R(crate::FieldReader); +impl ARBLOST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ARBLOST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ARBLOST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ARBLOST` writer - Arbitration Lost"] +pub struct ARBLOST_W<'a> { + w: &'a mut W, +} +impl<'a> ARBLOST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXNACK` reader - Received Not Acknowledge"] +pub struct RXNACK_R(crate::FieldReader); +impl RXNACK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXNACK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXNACK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXNACK` writer - Received Not Acknowledge"] +pub struct RXNACK_W<'a> { + w: &'a mut W, +} +impl<'a> RXNACK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `BUSSTATE` reader - Bus State"] +pub struct BUSSTATE_R(crate::FieldReader); +impl BUSSTATE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BUSSTATE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSSTATE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSSTATE` writer - Bus State"] +pub struct BUSSTATE_W<'a> { + w: &'a mut W, +} +impl<'a> BUSSTATE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u16 & 0x03) << 4); + self.w + } +} +#[doc = "Field `LOWTOUT` reader - SCL Low Timeout"] +pub struct LOWTOUT_R(crate::FieldReader); +impl LOWTOUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LOWTOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOWTOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LOWTOUT` writer - SCL Low Timeout"] +pub struct LOWTOUT_W<'a> { + w: &'a mut W, +} +impl<'a> LOWTOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `CLKHOLD` reader - Clock Hold"] +pub struct CLKHOLD_R(crate::FieldReader); +impl CLKHOLD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKHOLD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKHOLD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKHOLD` writer - Clock Hold"] +pub struct CLKHOLD_W<'a> { + w: &'a mut W, +} +impl<'a> CLKHOLD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `MEXTTOUT` reader - Master SCL Low Extend Timeout"] +pub struct MEXTTOUT_R(crate::FieldReader); +impl MEXTTOUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MEXTTOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MEXTTOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MEXTTOUT` writer - Master SCL Low Extend Timeout"] +pub struct MEXTTOUT_W<'a> { + w: &'a mut W, +} +impl<'a> MEXTTOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `SEXTTOUT` reader - Slave SCL Low Extend Timeout"] +pub struct SEXTTOUT_R(crate::FieldReader); +impl SEXTTOUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SEXTTOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEXTTOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEXTTOUT` writer - Slave SCL Low Extend Timeout"] +pub struct SEXTTOUT_W<'a> { + w: &'a mut W, +} +impl<'a> SEXTTOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `LENERR` reader - Length Error"] +pub struct LENERR_R(crate::FieldReader); +impl LENERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LENERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LENERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LENERR` writer - Length Error"] +pub struct LENERR_W<'a> { + w: &'a mut W, +} +impl<'a> LENERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u16 & 0x01) << 10); + self.w + } +} +impl R { + #[doc = "Bit 0 - Bus Error"] + #[inline(always)] + pub fn buserr(&self) -> BUSERR_R { + BUSERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Arbitration Lost"] + #[inline(always)] + pub fn arblost(&self) -> ARBLOST_R { + ARBLOST_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Received Not Acknowledge"] + #[inline(always)] + pub fn rxnack(&self) -> RXNACK_R { + RXNACK_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 4:5 - Bus State"] + #[inline(always)] + pub fn busstate(&self) -> BUSSTATE_R { + BUSSTATE_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bit 6 - SCL Low Timeout"] + #[inline(always)] + pub fn lowtout(&self) -> LOWTOUT_R { + LOWTOUT_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Clock Hold"] + #[inline(always)] + pub fn clkhold(&self) -> CLKHOLD_R { + CLKHOLD_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Master SCL Low Extend Timeout"] + #[inline(always)] + pub fn mexttout(&self) -> MEXTTOUT_R { + MEXTTOUT_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttout(&self) -> SEXTTOUT_R { + SEXTTOUT_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Length Error"] + #[inline(always)] + pub fn lenerr(&self) -> LENERR_R { + LENERR_R::new(((self.bits >> 10) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Bus Error"] + #[inline(always)] + pub fn buserr(&mut self) -> BUSERR_W { + BUSERR_W { w: self } + } + #[doc = "Bit 1 - Arbitration Lost"] + #[inline(always)] + pub fn arblost(&mut self) -> ARBLOST_W { + ARBLOST_W { w: self } + } + #[doc = "Bit 2 - Received Not Acknowledge"] + #[inline(always)] + pub fn rxnack(&mut self) -> RXNACK_W { + RXNACK_W { w: self } + } + #[doc = "Bits 4:5 - Bus State"] + #[inline(always)] + pub fn busstate(&mut self) -> BUSSTATE_W { + BUSSTATE_W { w: self } + } + #[doc = "Bit 6 - SCL Low Timeout"] + #[inline(always)] + pub fn lowtout(&mut self) -> LOWTOUT_W { + LOWTOUT_W { w: self } + } + #[doc = "Bit 7 - Clock Hold"] + #[inline(always)] + pub fn clkhold(&mut self) -> CLKHOLD_W { + CLKHOLD_W { w: self } + } + #[doc = "Bit 8 - Master SCL Low Extend Timeout"] + #[inline(always)] + pub fn mexttout(&mut self) -> MEXTTOUT_W { + MEXTTOUT_W { w: self } + } + #[doc = "Bit 9 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttout(&mut self) -> SEXTTOUT_W { + SEXTTOUT_W { w: self } + } + #[doc = "Bit 10 - Length Error"] + #[inline(always)] + pub fn lenerr(&mut self) -> LENERR_W { + LENERR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sercom0/i2cm/syncbusy.rs b/pac/atsamc21j/src/sercom0/i2cm/syncbusy.rs new file mode 100644 index 000000000000..87dd418d1cd3 --- /dev/null +++ b/pac/atsamc21j/src/sercom0/i2cm/syncbusy.rs @@ -0,0 +1,93 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - SERCOM Enable Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYSOP` reader - System Operation Synchronization Busy"] +pub struct SYSOP_R(crate::FieldReader); +impl SYSOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYSOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYSOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM Enable Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - System Operation Synchronization Busy"] + #[inline(always)] + pub fn sysop(&self) -> SYSOP_R { + SYSOP_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +#[doc = "I2CM Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sercom0/i2cs.rs b/pac/atsamc21j/src/sercom0/i2cs.rs new file mode 100644 index 000000000000..baf9513c6cc1 --- /dev/null +++ b/pac/atsamc21j/src/sercom0/i2cs.rs @@ -0,0 +1,36 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "I2CS Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "I2CS Control B"] +pub mod ctrlb; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "I2CS Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "I2CS Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "I2CS Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "I2CS Status"] +pub mod status; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "I2CS Synchronization Busy"] +pub mod syncbusy; +#[doc = "ADDR register accessor: an alias for `Reg`"] +pub type ADDR = crate::Reg; +#[doc = "I2CS Address"] +pub mod addr; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "I2CS Data"] +pub mod data; diff --git a/pac/atsamc21j/src/sercom0/i2cs/addr.rs b/pac/atsamc21j/src/sercom0/i2cs/addr.rs new file mode 100644 index 000000000000..c1b69ee22891 --- /dev/null +++ b/pac/atsamc21j/src/sercom0/i2cs/addr.rs @@ -0,0 +1,234 @@ +#[doc = "Register `ADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `GENCEN` reader - General Call Address Enable"] +pub struct GENCEN_R(crate::FieldReader); +impl GENCEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENCEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENCEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENCEN` writer - General Call Address Enable"] +pub struct GENCEN_W<'a> { + w: &'a mut W, +} +impl<'a> GENCEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ADDR` reader - Address Value"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - Address Value"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03ff << 1)) | ((value as u32 & 0x03ff) << 1); + self.w + } +} +#[doc = "Field `TENBITEN` reader - Ten Bit Addressing Enable"] +pub struct TENBITEN_R(crate::FieldReader); +impl TENBITEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TENBITEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TENBITEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TENBITEN` writer - Ten Bit Addressing Enable"] +pub struct TENBITEN_W<'a> { + w: &'a mut W, +} +impl<'a> TENBITEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `ADDRMASK` reader - Address Mask"] +pub struct ADDRMASK_R(crate::FieldReader); +impl ADDRMASK_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + ADDRMASK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDRMASK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDRMASK` writer - Address Mask"] +pub struct ADDRMASK_W<'a> { + w: &'a mut W, +} +impl<'a> ADDRMASK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03ff << 17)) | ((value as u32 & 0x03ff) << 17); + self.w + } +} +impl R { + #[doc = "Bit 0 - General Call Address Enable"] + #[inline(always)] + pub fn gencen(&self) -> GENCEN_R { + GENCEN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bits 1:10 - Address Value"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new(((self.bits >> 1) & 0x03ff) as u16) + } + #[doc = "Bit 15 - Ten Bit Addressing Enable"] + #[inline(always)] + pub fn tenbiten(&self) -> TENBITEN_R { + TENBITEN_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 17:26 - Address Mask"] + #[inline(always)] + pub fn addrmask(&self) -> ADDRMASK_R { + ADDRMASK_R::new(((self.bits >> 17) & 0x03ff) as u16) + } +} +impl W { + #[doc = "Bit 0 - General Call Address Enable"] + #[inline(always)] + pub fn gencen(&mut self) -> GENCEN_W { + GENCEN_W { w: self } + } + #[doc = "Bits 1:10 - Address Value"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Bit 15 - Ten Bit Addressing Enable"] + #[inline(always)] + pub fn tenbiten(&mut self) -> TENBITEN_W { + TENBITEN_W { w: self } + } + #[doc = "Bits 17:26 - Address Mask"] + #[inline(always)] + pub fn addrmask(&mut self) -> ADDRMASK_W { + ADDRMASK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [addr](index.html) module"] +pub struct ADDR_SPEC; +impl crate::RegisterSpec for ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [addr::R](R) reader structure"] +impl crate::Readable for ADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [addr::W](W) writer structure"] +impl crate::Writable for ADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ADDR to value 0"] +impl crate::Resettable for ADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sercom0/i2cs/ctrla.rs b/pac/atsamc21j/src/sercom0/i2cs/ctrla.rs new file mode 100644 index 000000000000..ec93812b004f --- /dev/null +++ b/pac/atsamc21j/src/sercom0/i2cs/ctrla.rs @@ -0,0 +1,744 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: USART with external clock"] + USART_EXT_CLK = 0, + #[doc = "1: USART with internal clock"] + USART_INT_CLK = 1, + #[doc = "2: SPI in slave operation"] + SPI_SLAVE = 2, + #[doc = "3: SPI in master operation"] + SPI_MASTER = 3, + #[doc = "4: I2C slave operation"] + I2C_SLAVE = 4, + #[doc = "5: I2C master operation"] + I2C_MASTER = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::USART_EXT_CLK), + 1 => Some(MODE_A::USART_INT_CLK), + 2 => Some(MODE_A::SPI_SLAVE), + 3 => Some(MODE_A::SPI_MASTER), + 4 => Some(MODE_A::I2C_SLAVE), + 5 => Some(MODE_A::I2C_MASTER), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_EXT_CLK`"] + #[inline(always)] + pub fn is_usart_ext_clk(&self) -> bool { + **self == MODE_A::USART_EXT_CLK + } + #[doc = "Checks if the value of the field is `USART_INT_CLK`"] + #[inline(always)] + pub fn is_usart_int_clk(&self) -> bool { + **self == MODE_A::USART_INT_CLK + } + #[doc = "Checks if the value of the field is `SPI_SLAVE`"] + #[inline(always)] + pub fn is_spi_slave(&self) -> bool { + **self == MODE_A::SPI_SLAVE + } + #[doc = "Checks if the value of the field is `SPI_MASTER`"] + #[inline(always)] + pub fn is_spi_master(&self) -> bool { + **self == MODE_A::SPI_MASTER + } + #[doc = "Checks if the value of the field is `I2C_SLAVE`"] + #[inline(always)] + pub fn is_i2c_slave(&self) -> bool { + **self == MODE_A::I2C_SLAVE + } + #[doc = "Checks if the value of the field is `I2C_MASTER`"] + #[inline(always)] + pub fn is_i2c_master(&self) -> bool { + **self == MODE_A::I2C_MASTER + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART with external clock"] + #[inline(always)] + pub fn usart_ext_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_EXT_CLK) + } + #[doc = "USART with internal clock"] + #[inline(always)] + pub fn usart_int_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_INT_CLK) + } + #[doc = "SPI in slave operation"] + #[inline(always)] + pub fn spi_slave(self) -> &'a mut W { + self.variant(MODE_A::SPI_SLAVE) + } + #[doc = "SPI in master operation"] + #[inline(always)] + pub fn spi_master(self) -> &'a mut W { + self.variant(MODE_A::SPI_MASTER) + } + #[doc = "I2C slave operation"] + #[inline(always)] + pub fn i2c_slave(self) -> &'a mut W { + self.variant(MODE_A::I2C_SLAVE) + } + #[doc = "I2C master operation"] + #[inline(always)] + pub fn i2c_master(self) -> &'a mut W { + self.variant(MODE_A::I2C_MASTER) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 2)) | ((value as u32 & 0x07) << 2); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `PINOUT` reader - Pin Usage"] +pub struct PINOUT_R(crate::FieldReader); +impl PINOUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PINOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PINOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PINOUT` writer - Pin Usage"] +pub struct PINOUT_W<'a> { + w: &'a mut W, +} +impl<'a> PINOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "SDA Hold Time\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SDAHOLD_A { + #[doc = "0: Disabled"] + DISABLE = 0, + #[doc = "1: 50-100ns hold time"] + _75NS = 1, + #[doc = "2: 300-600ns hold time"] + _450NS = 2, + #[doc = "3: 400-800ns hold time"] + _600NS = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SDAHOLD_A) -> Self { + variant as _ + } +} +#[doc = "Field `SDAHOLD` reader - SDA Hold Time"] +pub struct SDAHOLD_R(crate::FieldReader); +impl SDAHOLD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SDAHOLD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SDAHOLD_A { + match self.bits { + 0 => SDAHOLD_A::DISABLE, + 1 => SDAHOLD_A::_75NS, + 2 => SDAHOLD_A::_450NS, + 3 => SDAHOLD_A::_600NS, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == SDAHOLD_A::DISABLE + } + #[doc = "Checks if the value of the field is `_75NS`"] + #[inline(always)] + pub fn is_75ns(&self) -> bool { + **self == SDAHOLD_A::_75NS + } + #[doc = "Checks if the value of the field is `_450NS`"] + #[inline(always)] + pub fn is_450ns(&self) -> bool { + **self == SDAHOLD_A::_450NS + } + #[doc = "Checks if the value of the field is `_600NS`"] + #[inline(always)] + pub fn is_600ns(&self) -> bool { + **self == SDAHOLD_A::_600NS + } +} +impl core::ops::Deref for SDAHOLD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SDAHOLD` writer - SDA Hold Time"] +pub struct SDAHOLD_W<'a> { + w: &'a mut W, +} +impl<'a> SDAHOLD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SDAHOLD_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(SDAHOLD_A::DISABLE) + } + #[doc = "50-100ns hold time"] + #[inline(always)] + pub fn _75ns(self) -> &'a mut W { + self.variant(SDAHOLD_A::_75NS) + } + #[doc = "300-600ns hold time"] + #[inline(always)] + pub fn _450ns(self) -> &'a mut W { + self.variant(SDAHOLD_A::_450NS) + } + #[doc = "400-800ns hold time"] + #[inline(always)] + pub fn _600ns(self) -> &'a mut W { + self.variant(SDAHOLD_A::_600NS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 20)) | ((value as u32 & 0x03) << 20); + self.w + } +} +#[doc = "Field `SEXTTOEN` reader - Slave SCL Low Extend Timeout"] +pub struct SEXTTOEN_R(crate::FieldReader); +impl SEXTTOEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SEXTTOEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEXTTOEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEXTTOEN` writer - Slave SCL Low Extend Timeout"] +pub struct SEXTTOEN_W<'a> { + w: &'a mut W, +} +impl<'a> SEXTTOEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Transfer Speed\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SPEED_A { + #[doc = "0: Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz"] + STANDARD_AND_FAST_MODE = 0, + #[doc = "1: Fast-mode Plus Upto 1MHz"] + FASTPLUS_MODE = 1, + #[doc = "2: High-speed mode Upto 3.4MHz"] + HIGH_SPEED_MODE = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SPEED_A) -> Self { + variant as _ + } +} +#[doc = "Field `SPEED` reader - Transfer Speed"] +pub struct SPEED_R(crate::FieldReader); +impl SPEED_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SPEED_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SPEED_A::STANDARD_AND_FAST_MODE), + 1 => Some(SPEED_A::FASTPLUS_MODE), + 2 => Some(SPEED_A::HIGH_SPEED_MODE), + _ => None, + } + } + #[doc = "Checks if the value of the field is `STANDARD_AND_FAST_MODE`"] + #[inline(always)] + pub fn is_standard_and_fast_mode(&self) -> bool { + **self == SPEED_A::STANDARD_AND_FAST_MODE + } + #[doc = "Checks if the value of the field is `FASTPLUS_MODE`"] + #[inline(always)] + pub fn is_fastplus_mode(&self) -> bool { + **self == SPEED_A::FASTPLUS_MODE + } + #[doc = "Checks if the value of the field is `HIGH_SPEED_MODE`"] + #[inline(always)] + pub fn is_high_speed_mode(&self) -> bool { + **self == SPEED_A::HIGH_SPEED_MODE + } +} +impl core::ops::Deref for SPEED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SPEED` writer - Transfer Speed"] +pub struct SPEED_W<'a> { + w: &'a mut W, +} +impl<'a> SPEED_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SPEED_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz"] + #[inline(always)] + pub fn standard_and_fast_mode(self) -> &'a mut W { + self.variant(SPEED_A::STANDARD_AND_FAST_MODE) + } + #[doc = "Fast-mode Plus Upto 1MHz"] + #[inline(always)] + pub fn fastplus_mode(self) -> &'a mut W { + self.variant(SPEED_A::FASTPLUS_MODE) + } + #[doc = "High-speed mode Upto 3.4MHz"] + #[inline(always)] + pub fn high_speed_mode(self) -> &'a mut W { + self.variant(SPEED_A::HIGH_SPEED_MODE) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 24)) | ((value as u32 & 0x03) << 24); + self.w + } +} +#[doc = "Field `SCLSM` reader - SCL Clock Stretch Mode"] +pub struct SCLSM_R(crate::FieldReader); +impl SCLSM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SCLSM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SCLSM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SCLSM` writer - SCL Clock Stretch Mode"] +pub struct SCLSM_W<'a> { + w: &'a mut W, +} +impl<'a> SCLSM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +#[doc = "Field `LOWTOUTEN` reader - SCL Low Timeout Enable"] +pub struct LOWTOUTEN_R(crate::FieldReader); +impl LOWTOUTEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LOWTOUTEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOWTOUTEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LOWTOUTEN` writer - SCL Low Timeout Enable"] +pub struct LOWTOUTEN_W<'a> { + w: &'a mut W, +} +impl<'a> LOWTOUTEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x07) as u8) + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 16 - Pin Usage"] + #[inline(always)] + pub fn pinout(&self) -> PINOUT_R { + PINOUT_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bits 20:21 - SDA Hold Time"] + #[inline(always)] + pub fn sdahold(&self) -> SDAHOLD_R { + SDAHOLD_R::new(((self.bits >> 20) & 0x03) as u8) + } + #[doc = "Bit 23 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttoen(&self) -> SEXTTOEN_R { + SEXTTOEN_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bits 24:25 - Transfer Speed"] + #[inline(always)] + pub fn speed(&self) -> SPEED_R { + SPEED_R::new(((self.bits >> 24) & 0x03) as u8) + } + #[doc = "Bit 27 - SCL Clock Stretch Mode"] + #[inline(always)] + pub fn sclsm(&self) -> SCLSM_R { + SCLSM_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 30 - SCL Low Timeout Enable"] + #[inline(always)] + pub fn lowtouten(&self) -> LOWTOUTEN_R { + LOWTOUTEN_R::new(((self.bits >> 30) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 16 - Pin Usage"] + #[inline(always)] + pub fn pinout(&mut self) -> PINOUT_W { + PINOUT_W { w: self } + } + #[doc = "Bits 20:21 - SDA Hold Time"] + #[inline(always)] + pub fn sdahold(&mut self) -> SDAHOLD_W { + SDAHOLD_W { w: self } + } + #[doc = "Bit 23 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttoen(&mut self) -> SEXTTOEN_W { + SEXTTOEN_W { w: self } + } + #[doc = "Bits 24:25 - Transfer Speed"] + #[inline(always)] + pub fn speed(&mut self) -> SPEED_W { + SPEED_W { w: self } + } + #[doc = "Bit 27 - SCL Clock Stretch Mode"] + #[inline(always)] + pub fn sclsm(&mut self) -> SCLSM_W { + SCLSM_W { w: self } + } + #[doc = "Bit 30 - SCL Low Timeout Enable"] + #[inline(always)] + pub fn lowtouten(&mut self) -> LOWTOUTEN_W { + LOWTOUTEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sercom0/i2cs/ctrlb.rs b/pac/atsamc21j/src/sercom0/i2cs/ctrlb.rs new file mode 100644 index 000000000000..b20f48581ed5 --- /dev/null +++ b/pac/atsamc21j/src/sercom0/i2cs/ctrlb.rs @@ -0,0 +1,328 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SMEN` reader - Smart Mode Enable"] +pub struct SMEN_R(crate::FieldReader); +impl SMEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SMEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SMEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SMEN` writer - Smart Mode Enable"] +pub struct SMEN_W<'a> { + w: &'a mut W, +} +impl<'a> SMEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `GCMD` reader - PMBus Group Command"] +pub struct GCMD_R(crate::FieldReader); +impl GCMD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GCMD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GCMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GCMD` writer - PMBus Group Command"] +pub struct GCMD_W<'a> { + w: &'a mut W, +} +impl<'a> GCMD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `AACKEN` reader - Automatic Address Acknowledge"] +pub struct AACKEN_R(crate::FieldReader); +impl AACKEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AACKEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AACKEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AACKEN` writer - Automatic Address Acknowledge"] +pub struct AACKEN_W<'a> { + w: &'a mut W, +} +impl<'a> AACKEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `AMODE` reader - Address Mode"] +pub struct AMODE_R(crate::FieldReader); +impl AMODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + AMODE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AMODE` writer - Address Mode"] +pub struct AMODE_W<'a> { + w: &'a mut W, +} +impl<'a> AMODE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 14)) | ((value as u32 & 0x03) << 14); + self.w + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Field `ACKACT` reader - Acknowledge Action"] +pub struct ACKACT_R(crate::FieldReader); +impl ACKACT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ACKACT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ACKACT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ACKACT` writer - Acknowledge Action"] +pub struct ACKACT_W<'a> { + w: &'a mut W, +} +impl<'a> ACKACT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +impl R { + #[doc = "Bit 8 - Smart Mode Enable"] + #[inline(always)] + pub fn smen(&self) -> SMEN_R { + SMEN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - PMBus Group Command"] + #[inline(always)] + pub fn gcmd(&self) -> GCMD_R { + GCMD_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Automatic Address Acknowledge"] + #[inline(always)] + pub fn aacken(&self) -> AACKEN_R { + AACKEN_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bits 14:15 - Address Mode"] + #[inline(always)] + pub fn amode(&self) -> AMODE_R { + AMODE_R::new(((self.bits >> 14) & 0x03) as u8) + } + #[doc = "Bits 16:17 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bit 18 - Acknowledge Action"] + #[inline(always)] + pub fn ackact(&self) -> ACKACT_R { + ACKACT_R::new(((self.bits >> 18) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 8 - Smart Mode Enable"] + #[inline(always)] + pub fn smen(&mut self) -> SMEN_W { + SMEN_W { w: self } + } + #[doc = "Bit 9 - PMBus Group Command"] + #[inline(always)] + pub fn gcmd(&mut self) -> GCMD_W { + GCMD_W { w: self } + } + #[doc = "Bit 10 - Automatic Address Acknowledge"] + #[inline(always)] + pub fn aacken(&mut self) -> AACKEN_W { + AACKEN_W { w: self } + } + #[doc = "Bits 14:15 - Address Mode"] + #[inline(always)] + pub fn amode(&mut self) -> AMODE_W { + AMODE_W { w: self } + } + #[doc = "Bits 16:17 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Bit 18 - Acknowledge Action"] + #[inline(always)] + pub fn ackact(&mut self) -> ACKACT_W { + ACKACT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sercom0/i2cs/data.rs b/pac/atsamc21j/src/sercom0/i2cs/data.rs new file mode 100644 index 000000000000..d8bfe070431a --- /dev/null +++ b/pac/atsamc21j/src/sercom0/i2cs/data.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data Value"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data Value"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Data Value"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Value"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sercom0/i2cs/intenclr.rs b/pac/atsamc21j/src/sercom0/i2cs/intenclr.rs new file mode 100644 index 000000000000..49f5191c8d63 --- /dev/null +++ b/pac/atsamc21j/src/sercom0/i2cs/intenclr.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PREC` reader - Stop Received Interrupt Disable"] +pub struct PREC_R(crate::FieldReader); +impl PREC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PREC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PREC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PREC` writer - Stop Received Interrupt Disable"] +pub struct PREC_W<'a> { + w: &'a mut W, +} +impl<'a> PREC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `AMATCH` reader - Address Match Interrupt Disable"] +pub struct AMATCH_R(crate::FieldReader); +impl AMATCH_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AMATCH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AMATCH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AMATCH` writer - Address Match Interrupt Disable"] +pub struct AMATCH_W<'a> { + w: &'a mut W, +} +impl<'a> AMATCH_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `DRDY` reader - Data Interrupt Disable"] +pub struct DRDY_R(crate::FieldReader); +impl DRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRDY` writer - Data Interrupt Disable"] +pub struct DRDY_W<'a> { + w: &'a mut W, +} +impl<'a> DRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Disable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Disable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Stop Received Interrupt Disable"] + #[inline(always)] + pub fn prec(&self) -> PREC_R { + PREC_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Address Match Interrupt Disable"] + #[inline(always)] + pub fn amatch(&self) -> AMATCH_R { + AMATCH_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Data Interrupt Disable"] + #[inline(always)] + pub fn drdy(&self) -> DRDY_R { + DRDY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Stop Received Interrupt Disable"] + #[inline(always)] + pub fn prec(&mut self) -> PREC_W { + PREC_W { w: self } + } + #[doc = "Bit 1 - Address Match Interrupt Disable"] + #[inline(always)] + pub fn amatch(&mut self) -> AMATCH_W { + AMATCH_W { w: self } + } + #[doc = "Bit 2 - Data Interrupt Disable"] + #[inline(always)] + pub fn drdy(&mut self) -> DRDY_W { + DRDY_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sercom0/i2cs/intenset.rs b/pac/atsamc21j/src/sercom0/i2cs/intenset.rs new file mode 100644 index 000000000000..97ea784d7476 --- /dev/null +++ b/pac/atsamc21j/src/sercom0/i2cs/intenset.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PREC` reader - Stop Received Interrupt Enable"] +pub struct PREC_R(crate::FieldReader); +impl PREC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PREC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PREC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PREC` writer - Stop Received Interrupt Enable"] +pub struct PREC_W<'a> { + w: &'a mut W, +} +impl<'a> PREC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `AMATCH` reader - Address Match Interrupt Enable"] +pub struct AMATCH_R(crate::FieldReader); +impl AMATCH_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AMATCH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AMATCH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AMATCH` writer - Address Match Interrupt Enable"] +pub struct AMATCH_W<'a> { + w: &'a mut W, +} +impl<'a> AMATCH_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `DRDY` reader - Data Interrupt Enable"] +pub struct DRDY_R(crate::FieldReader); +impl DRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRDY` writer - Data Interrupt Enable"] +pub struct DRDY_W<'a> { + w: &'a mut W, +} +impl<'a> DRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Stop Received Interrupt Enable"] + #[inline(always)] + pub fn prec(&self) -> PREC_R { + PREC_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Address Match Interrupt Enable"] + #[inline(always)] + pub fn amatch(&self) -> AMATCH_R { + AMATCH_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Data Interrupt Enable"] + #[inline(always)] + pub fn drdy(&self) -> DRDY_R { + DRDY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Stop Received Interrupt Enable"] + #[inline(always)] + pub fn prec(&mut self) -> PREC_W { + PREC_W { w: self } + } + #[doc = "Bit 1 - Address Match Interrupt Enable"] + #[inline(always)] + pub fn amatch(&mut self) -> AMATCH_W { + AMATCH_W { w: self } + } + #[doc = "Bit 2 - Data Interrupt Enable"] + #[inline(always)] + pub fn drdy(&mut self) -> DRDY_W { + DRDY_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sercom0/i2cs/intflag.rs b/pac/atsamc21j/src/sercom0/i2cs/intflag.rs new file mode 100644 index 000000000000..2eee333e4e59 --- /dev/null +++ b/pac/atsamc21j/src/sercom0/i2cs/intflag.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PREC` reader - Stop Received Interrupt"] +pub struct PREC_R(crate::FieldReader); +impl PREC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PREC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PREC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PREC` writer - Stop Received Interrupt"] +pub struct PREC_W<'a> { + w: &'a mut W, +} +impl<'a> PREC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `AMATCH` reader - Address Match Interrupt"] +pub struct AMATCH_R(crate::FieldReader); +impl AMATCH_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AMATCH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AMATCH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AMATCH` writer - Address Match Interrupt"] +pub struct AMATCH_W<'a> { + w: &'a mut W, +} +impl<'a> AMATCH_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `DRDY` reader - Data Interrupt"] +pub struct DRDY_R(crate::FieldReader); +impl DRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRDY` writer - Data Interrupt"] +pub struct DRDY_W<'a> { + w: &'a mut W, +} +impl<'a> DRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Stop Received Interrupt"] + #[inline(always)] + pub fn prec(&self) -> PREC_R { + PREC_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Address Match Interrupt"] + #[inline(always)] + pub fn amatch(&self) -> AMATCH_R { + AMATCH_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Data Interrupt"] + #[inline(always)] + pub fn drdy(&self) -> DRDY_R { + DRDY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Stop Received Interrupt"] + #[inline(always)] + pub fn prec(&mut self) -> PREC_W { + PREC_W { w: self } + } + #[doc = "Bit 1 - Address Match Interrupt"] + #[inline(always)] + pub fn amatch(&mut self) -> AMATCH_W { + AMATCH_W { w: self } + } + #[doc = "Bit 2 - Data Interrupt"] + #[inline(always)] + pub fn drdy(&mut self) -> DRDY_W { + DRDY_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sercom0/i2cs/status.rs b/pac/atsamc21j/src/sercom0/i2cs/status.rs new file mode 100644 index 000000000000..b3f6d218fa66 --- /dev/null +++ b/pac/atsamc21j/src/sercom0/i2cs/status.rs @@ -0,0 +1,489 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BUSERR` reader - Bus Error"] +pub struct BUSERR_R(crate::FieldReader); +impl BUSERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSERR` writer - Bus Error"] +pub struct BUSERR_W<'a> { + w: &'a mut W, +} +impl<'a> BUSERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `COLL` reader - Transmit Collision"] +pub struct COLL_R(crate::FieldReader); +impl COLL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COLL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COLL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COLL` writer - Transmit Collision"] +pub struct COLL_W<'a> { + w: &'a mut W, +} +impl<'a> COLL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXNACK` reader - Received Not Acknowledge"] +pub struct RXNACK_R(crate::FieldReader); +impl RXNACK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXNACK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXNACK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXNACK` writer - Received Not Acknowledge"] +pub struct RXNACK_W<'a> { + w: &'a mut W, +} +impl<'a> RXNACK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `DIR` reader - Read/Write Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Read/Write Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `SR` reader - Repeated Start"] +pub struct SR_R(crate::FieldReader); +impl SR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SR` writer - Repeated Start"] +pub struct SR_W<'a> { + w: &'a mut W, +} +impl<'a> SR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `LOWTOUT` reader - SCL Low Timeout"] +pub struct LOWTOUT_R(crate::FieldReader); +impl LOWTOUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LOWTOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOWTOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LOWTOUT` writer - SCL Low Timeout"] +pub struct LOWTOUT_W<'a> { + w: &'a mut W, +} +impl<'a> LOWTOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `CLKHOLD` reader - Clock Hold"] +pub struct CLKHOLD_R(crate::FieldReader); +impl CLKHOLD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKHOLD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKHOLD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKHOLD` writer - Clock Hold"] +pub struct CLKHOLD_W<'a> { + w: &'a mut W, +} +impl<'a> CLKHOLD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `SEXTTOUT` reader - Slave SCL Low Extend Timeout"] +pub struct SEXTTOUT_R(crate::FieldReader); +impl SEXTTOUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SEXTTOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEXTTOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEXTTOUT` writer - Slave SCL Low Extend Timeout"] +pub struct SEXTTOUT_W<'a> { + w: &'a mut W, +} +impl<'a> SEXTTOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `HS` reader - High Speed"] +pub struct HS_R(crate::FieldReader); +impl HS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HS` writer - High Speed"] +pub struct HS_W<'a> { + w: &'a mut W, +} +impl<'a> HS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u16 & 0x01) << 10); + self.w + } +} +impl R { + #[doc = "Bit 0 - Bus Error"] + #[inline(always)] + pub fn buserr(&self) -> BUSERR_R { + BUSERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Collision"] + #[inline(always)] + pub fn coll(&self) -> COLL_R { + COLL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Received Not Acknowledge"] + #[inline(always)] + pub fn rxnack(&self) -> RXNACK_R { + RXNACK_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Read/Write Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Repeated Start"] + #[inline(always)] + pub fn sr(&self) -> SR_R { + SR_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 6 - SCL Low Timeout"] + #[inline(always)] + pub fn lowtout(&self) -> LOWTOUT_R { + LOWTOUT_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Clock Hold"] + #[inline(always)] + pub fn clkhold(&self) -> CLKHOLD_R { + CLKHOLD_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 9 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttout(&self) -> SEXTTOUT_R { + SEXTTOUT_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - High Speed"] + #[inline(always)] + pub fn hs(&self) -> HS_R { + HS_R::new(((self.bits >> 10) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Bus Error"] + #[inline(always)] + pub fn buserr(&mut self) -> BUSERR_W { + BUSERR_W { w: self } + } + #[doc = "Bit 1 - Transmit Collision"] + #[inline(always)] + pub fn coll(&mut self) -> COLL_W { + COLL_W { w: self } + } + #[doc = "Bit 2 - Received Not Acknowledge"] + #[inline(always)] + pub fn rxnack(&mut self) -> RXNACK_W { + RXNACK_W { w: self } + } + #[doc = "Bit 3 - Read/Write Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 4 - Repeated Start"] + #[inline(always)] + pub fn sr(&mut self) -> SR_W { + SR_W { w: self } + } + #[doc = "Bit 6 - SCL Low Timeout"] + #[inline(always)] + pub fn lowtout(&mut self) -> LOWTOUT_W { + LOWTOUT_W { w: self } + } + #[doc = "Bit 7 - Clock Hold"] + #[inline(always)] + pub fn clkhold(&mut self) -> CLKHOLD_W { + CLKHOLD_W { w: self } + } + #[doc = "Bit 9 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttout(&mut self) -> SEXTTOUT_W { + SEXTTOUT_W { w: self } + } + #[doc = "Bit 10 - High Speed"] + #[inline(always)] + pub fn hs(&mut self) -> HS_W { + HS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sercom0/i2cs/syncbusy.rs b/pac/atsamc21j/src/sercom0/i2cs/syncbusy.rs new file mode 100644 index 000000000000..38e2509d9666 --- /dev/null +++ b/pac/atsamc21j/src/sercom0/i2cs/syncbusy.rs @@ -0,0 +1,73 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - SERCOM Enable Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM Enable Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +#[doc = "I2CS Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sercom0/spim.rs b/pac/atsamc21j/src/sercom0/spim.rs new file mode 100644 index 000000000000..528e38e1b811 --- /dev/null +++ b/pac/atsamc21j/src/sercom0/spim.rs @@ -0,0 +1,44 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "SPIM Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "SPIM Control B"] +pub mod ctrlb; +#[doc = "BAUD register accessor: an alias for `Reg`"] +pub type BAUD = crate::Reg; +#[doc = "SPIM Baud Rate"] +pub mod baud; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "SPIM Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "SPIM Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "SPIM Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "SPIM Status"] +pub mod status; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "SPIM Synchronization Busy"] +pub mod syncbusy; +#[doc = "ADDR register accessor: an alias for `Reg`"] +pub type ADDR = crate::Reg; +#[doc = "SPIM Address"] +pub mod addr; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "SPIM Data"] +pub mod data; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "SPIM Debug Control"] +pub mod dbgctrl; diff --git a/pac/atsamc21j/src/sercom0/spim/addr.rs b/pac/atsamc21j/src/sercom0/spim/addr.rs new file mode 100644 index 000000000000..7c25cd522ea2 --- /dev/null +++ b/pac/atsamc21j/src/sercom0/spim/addr.rs @@ -0,0 +1,140 @@ +#[doc = "Register `ADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ADDR` reader - Address Value"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - Address Value"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +#[doc = "Field `ADDRMASK` reader - Address Mask"] +pub struct ADDRMASK_R(crate::FieldReader); +impl ADDRMASK_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ADDRMASK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDRMASK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDRMASK` writer - Address Mask"] +pub struct ADDRMASK_W<'a> { + w: &'a mut W, +} +impl<'a> ADDRMASK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Address Value"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 16:23 - Address Mask"] + #[inline(always)] + pub fn addrmask(&self) -> ADDRMASK_R { + ADDRMASK_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Address Value"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Bits 16:23 - Address Mask"] + #[inline(always)] + pub fn addrmask(&mut self) -> ADDRMASK_W { + ADDRMASK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [addr](index.html) module"] +pub struct ADDR_SPEC; +impl crate::RegisterSpec for ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [addr::R](R) reader structure"] +impl crate::Readable for ADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [addr::W](W) writer structure"] +impl crate::Writable for ADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ADDR to value 0"] +impl crate::Resettable for ADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sercom0/spim/baud.rs b/pac/atsamc21j/src/sercom0/spim/baud.rs new file mode 100644 index 000000000000..6bec9ca74355 --- /dev/null +++ b/pac/atsamc21j/src/sercom0/spim/baud.rs @@ -0,0 +1,103 @@ +#[doc = "Register `BAUD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud](index.html) module"] +pub struct BAUD_SPEC; +impl crate::RegisterSpec for BAUD_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [baud::R](R) reader structure"] +impl crate::Readable for BAUD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud::W](W) writer structure"] +impl crate::Writable for BAUD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD to value 0"] +impl crate::Resettable for BAUD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sercom0/spim/ctrla.rs b/pac/atsamc21j/src/sercom0/spim/ctrla.rs new file mode 100644 index 000000000000..44028f8cbdd7 --- /dev/null +++ b/pac/atsamc21j/src/sercom0/spim/ctrla.rs @@ -0,0 +1,992 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: USART with external clock"] + USART_EXT_CLK = 0, + #[doc = "1: USART with internal clock"] + USART_INT_CLK = 1, + #[doc = "2: SPI in slave operation"] + SPI_SLAVE = 2, + #[doc = "3: SPI in master operation"] + SPI_MASTER = 3, + #[doc = "4: I2C slave operation"] + I2C_SLAVE = 4, + #[doc = "5: I2C master operation"] + I2C_MASTER = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::USART_EXT_CLK), + 1 => Some(MODE_A::USART_INT_CLK), + 2 => Some(MODE_A::SPI_SLAVE), + 3 => Some(MODE_A::SPI_MASTER), + 4 => Some(MODE_A::I2C_SLAVE), + 5 => Some(MODE_A::I2C_MASTER), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_EXT_CLK`"] + #[inline(always)] + pub fn is_usart_ext_clk(&self) -> bool { + **self == MODE_A::USART_EXT_CLK + } + #[doc = "Checks if the value of the field is `USART_INT_CLK`"] + #[inline(always)] + pub fn is_usart_int_clk(&self) -> bool { + **self == MODE_A::USART_INT_CLK + } + #[doc = "Checks if the value of the field is `SPI_SLAVE`"] + #[inline(always)] + pub fn is_spi_slave(&self) -> bool { + **self == MODE_A::SPI_SLAVE + } + #[doc = "Checks if the value of the field is `SPI_MASTER`"] + #[inline(always)] + pub fn is_spi_master(&self) -> bool { + **self == MODE_A::SPI_MASTER + } + #[doc = "Checks if the value of the field is `I2C_SLAVE`"] + #[inline(always)] + pub fn is_i2c_slave(&self) -> bool { + **self == MODE_A::I2C_SLAVE + } + #[doc = "Checks if the value of the field is `I2C_MASTER`"] + #[inline(always)] + pub fn is_i2c_master(&self) -> bool { + **self == MODE_A::I2C_MASTER + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART with external clock"] + #[inline(always)] + pub fn usart_ext_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_EXT_CLK) + } + #[doc = "USART with internal clock"] + #[inline(always)] + pub fn usart_int_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_INT_CLK) + } + #[doc = "SPI in slave operation"] + #[inline(always)] + pub fn spi_slave(self) -> &'a mut W { + self.variant(MODE_A::SPI_SLAVE) + } + #[doc = "SPI in master operation"] + #[inline(always)] + pub fn spi_master(self) -> &'a mut W { + self.variant(MODE_A::SPI_MASTER) + } + #[doc = "I2C slave operation"] + #[inline(always)] + pub fn i2c_slave(self) -> &'a mut W { + self.variant(MODE_A::I2C_SLAVE) + } + #[doc = "I2C master operation"] + #[inline(always)] + pub fn i2c_master(self) -> &'a mut W { + self.variant(MODE_A::I2C_MASTER) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 2)) | ((value as u32 & 0x07) << 2); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `IBON` reader - Immediate Buffer Overflow Notification"] +pub struct IBON_R(crate::FieldReader); +impl IBON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IBON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IBON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IBON` writer - Immediate Buffer Overflow Notification"] +pub struct IBON_W<'a> { + w: &'a mut W, +} +impl<'a> IBON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Data Out Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DOPO_A { + #[doc = "0: DO on PAD\\[0\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + PAD0 = 0, + #[doc = "1: DO on PAD\\[2\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + PAD1 = 1, + #[doc = "2: DO on PAD\\[3\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + PAD2 = 2, + #[doc = "3: DO on PAD\\[0\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + PAD3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DOPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `DOPO` reader - Data Out Pinout"] +pub struct DOPO_R(crate::FieldReader); +impl DOPO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DOPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DOPO_A { + match self.bits { + 0 => DOPO_A::PAD0, + 1 => DOPO_A::PAD1, + 2 => DOPO_A::PAD2, + 3 => DOPO_A::PAD3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == DOPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD1`"] + #[inline(always)] + pub fn is_pad1(&self) -> bool { + **self == DOPO_A::PAD1 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == DOPO_A::PAD2 + } + #[doc = "Checks if the value of the field is `PAD3`"] + #[inline(always)] + pub fn is_pad3(&self) -> bool { + **self == DOPO_A::PAD3 + } +} +impl core::ops::Deref for DOPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DOPO` writer - Data Out Pinout"] +pub struct DOPO_W<'a> { + w: &'a mut W, +} +impl<'a> DOPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DOPO_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "DO on PAD\\[0\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(DOPO_A::PAD0) + } + #[doc = "DO on PAD\\[2\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + #[inline(always)] + pub fn pad1(self) -> &'a mut W { + self.variant(DOPO_A::PAD1) + } + #[doc = "DO on PAD\\[3\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(DOPO_A::PAD2) + } + #[doc = "DO on PAD\\[0\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + #[inline(always)] + pub fn pad3(self) -> &'a mut W { + self.variant(DOPO_A::PAD3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Data In Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DIPO_A { + #[doc = "0: SERCOM PAD\\[0\\]"] + PAD0 = 0, + #[doc = "1: SERCOM PAD\\[1\\]"] + PAD1 = 1, + #[doc = "2: SERCOM PAD\\[2\\]"] + PAD2 = 2, + #[doc = "3: SERCOM PAD\\[3\\]"] + PAD3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DIPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `DIPO` reader - Data In Pinout"] +pub struct DIPO_R(crate::FieldReader); +impl DIPO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DIPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DIPO_A { + match self.bits { + 0 => DIPO_A::PAD0, + 1 => DIPO_A::PAD1, + 2 => DIPO_A::PAD2, + 3 => DIPO_A::PAD3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == DIPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD1`"] + #[inline(always)] + pub fn is_pad1(&self) -> bool { + **self == DIPO_A::PAD1 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == DIPO_A::PAD2 + } + #[doc = "Checks if the value of the field is `PAD3`"] + #[inline(always)] + pub fn is_pad3(&self) -> bool { + **self == DIPO_A::PAD3 + } +} +impl core::ops::Deref for DIPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIPO` writer - Data In Pinout"] +pub struct DIPO_W<'a> { + w: &'a mut W, +} +impl<'a> DIPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DIPO_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "SERCOM PAD\\[0\\]"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(DIPO_A::PAD0) + } + #[doc = "SERCOM PAD\\[1\\]"] + #[inline(always)] + pub fn pad1(self) -> &'a mut W { + self.variant(DIPO_A::PAD1) + } + #[doc = "SERCOM PAD\\[2\\]"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(DIPO_A::PAD2) + } + #[doc = "SERCOM PAD\\[3\\]"] + #[inline(always)] + pub fn pad3(self) -> &'a mut W { + self.variant(DIPO_A::PAD3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 20)) | ((value as u32 & 0x03) << 20); + self.w + } +} +#[doc = "Frame Format\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FORM_A { + #[doc = "0: SPI Frame"] + SPI_FRAME = 0, + #[doc = "2: SPI Frame with Addr"] + SPI_FRAME_WITH_ADDR = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FORM_A) -> Self { + variant as _ + } +} +#[doc = "Field `FORM` reader - Frame Format"] +pub struct FORM_R(crate::FieldReader); +impl FORM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FORM_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(FORM_A::SPI_FRAME), + 2 => Some(FORM_A::SPI_FRAME_WITH_ADDR), + _ => None, + } + } + #[doc = "Checks if the value of the field is `SPI_FRAME`"] + #[inline(always)] + pub fn is_spi_frame(&self) -> bool { + **self == FORM_A::SPI_FRAME + } + #[doc = "Checks if the value of the field is `SPI_FRAME_WITH_ADDR`"] + #[inline(always)] + pub fn is_spi_frame_with_addr(&self) -> bool { + **self == FORM_A::SPI_FRAME_WITH_ADDR + } +} +impl core::ops::Deref for FORM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FORM` writer - Frame Format"] +pub struct FORM_W<'a> { + w: &'a mut W, +} +impl<'a> FORM_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FORM_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "SPI Frame"] + #[inline(always)] + pub fn spi_frame(self) -> &'a mut W { + self.variant(FORM_A::SPI_FRAME) + } + #[doc = "SPI Frame with Addr"] + #[inline(always)] + pub fn spi_frame_with_addr(self) -> &'a mut W { + self.variant(FORM_A::SPI_FRAME_WITH_ADDR) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Clock Phase\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CPHA_A { + #[doc = "0: The data is sampled on a leading SCK edge and changed on a trailing SCK edge"] + LEADING_EDGE = 0, + #[doc = "1: The data is sampled on a trailing SCK edge and changed on a leading SCK edge"] + TRAILING_EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CPHA_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CPHA` reader - Clock Phase"] +pub struct CPHA_R(crate::FieldReader); +impl CPHA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPHA_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CPHA_A { + match self.bits { + false => CPHA_A::LEADING_EDGE, + true => CPHA_A::TRAILING_EDGE, + } + } + #[doc = "Checks if the value of the field is `LEADING_EDGE`"] + #[inline(always)] + pub fn is_leading_edge(&self) -> bool { + **self == CPHA_A::LEADING_EDGE + } + #[doc = "Checks if the value of the field is `TRAILING_EDGE`"] + #[inline(always)] + pub fn is_trailing_edge(&self) -> bool { + **self == CPHA_A::TRAILING_EDGE + } +} +impl core::ops::Deref for CPHA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPHA` writer - Clock Phase"] +pub struct CPHA_W<'a> { + w: &'a mut W, +} +impl<'a> CPHA_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CPHA_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "The data is sampled on a leading SCK edge and changed on a trailing SCK edge"] + #[inline(always)] + pub fn leading_edge(self) -> &'a mut W { + self.variant(CPHA_A::LEADING_EDGE) + } + #[doc = "The data is sampled on a trailing SCK edge and changed on a leading SCK edge"] + #[inline(always)] + pub fn trailing_edge(self) -> &'a mut W { + self.variant(CPHA_A::TRAILING_EDGE) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Clock Polarity\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CPOL_A { + #[doc = "0: SCK is low when idle"] + IDLE_LOW = 0, + #[doc = "1: SCK is high when idle"] + IDLE_HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CPOL_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CPOL` reader - Clock Polarity"] +pub struct CPOL_R(crate::FieldReader); +impl CPOL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPOL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CPOL_A { + match self.bits { + false => CPOL_A::IDLE_LOW, + true => CPOL_A::IDLE_HIGH, + } + } + #[doc = "Checks if the value of the field is `IDLE_LOW`"] + #[inline(always)] + pub fn is_idle_low(&self) -> bool { + **self == CPOL_A::IDLE_LOW + } + #[doc = "Checks if the value of the field is `IDLE_HIGH`"] + #[inline(always)] + pub fn is_idle_high(&self) -> bool { + **self == CPOL_A::IDLE_HIGH + } +} +impl core::ops::Deref for CPOL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPOL` writer - Clock Polarity"] +pub struct CPOL_W<'a> { + w: &'a mut W, +} +impl<'a> CPOL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CPOL_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "SCK is low when idle"] + #[inline(always)] + pub fn idle_low(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_LOW) + } + #[doc = "SCK is high when idle"] + #[inline(always)] + pub fn idle_high(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_HIGH) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29); + self.w + } +} +#[doc = "Data Order\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum DORD_A { + #[doc = "0: MSB is transferred first"] + MSB = 0, + #[doc = "1: LSB is transferred first"] + LSB = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DORD_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DORD` reader - Data Order"] +pub struct DORD_R(crate::FieldReader); +impl DORD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DORD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DORD_A { + match self.bits { + false => DORD_A::MSB, + true => DORD_A::LSB, + } + } + #[doc = "Checks if the value of the field is `MSB`"] + #[inline(always)] + pub fn is_msb(&self) -> bool { + **self == DORD_A::MSB + } + #[doc = "Checks if the value of the field is `LSB`"] + #[inline(always)] + pub fn is_lsb(&self) -> bool { + **self == DORD_A::LSB + } +} +impl core::ops::Deref for DORD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DORD` writer - Data Order"] +pub struct DORD_W<'a> { + w: &'a mut W, +} +impl<'a> DORD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DORD_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "MSB is transferred first"] + #[inline(always)] + pub fn msb(self) -> &'a mut W { + self.variant(DORD_A::MSB) + } + #[doc = "LSB is transferred first"] + #[inline(always)] + pub fn lsb(self) -> &'a mut W { + self.variant(DORD_A::LSB) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x07) as u8) + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&self) -> IBON_R { + IBON_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bits 16:17 - Data Out Pinout"] + #[inline(always)] + pub fn dopo(&self) -> DOPO_R { + DOPO_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bits 20:21 - Data In Pinout"] + #[inline(always)] + pub fn dipo(&self) -> DIPO_R { + DIPO_R::new(((self.bits >> 20) & 0x03) as u8) + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&self) -> FORM_R { + FORM_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 28 - Clock Phase"] + #[inline(always)] + pub fn cpha(&self) -> CPHA_R { + CPHA_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&self) -> CPOL_R { + CPOL_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&self) -> DORD_R { + DORD_R::new(((self.bits >> 30) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&mut self) -> IBON_W { + IBON_W { w: self } + } + #[doc = "Bits 16:17 - Data Out Pinout"] + #[inline(always)] + pub fn dopo(&mut self) -> DOPO_W { + DOPO_W { w: self } + } + #[doc = "Bits 20:21 - Data In Pinout"] + #[inline(always)] + pub fn dipo(&mut self) -> DIPO_W { + DIPO_W { w: self } + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&mut self) -> FORM_W { + FORM_W { w: self } + } + #[doc = "Bit 28 - Clock Phase"] + #[inline(always)] + pub fn cpha(&mut self) -> CPHA_W { + CPHA_W { w: self } + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&mut self) -> CPOL_W { + CPOL_W { w: self } + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&mut self) -> DORD_W { + DORD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sercom0/spim/ctrlb.rs b/pac/atsamc21j/src/sercom0/spim/ctrlb.rs new file mode 100644 index 000000000000..3d94f824ce83 --- /dev/null +++ b/pac/atsamc21j/src/sercom0/spim/ctrlb.rs @@ -0,0 +1,439 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Character Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CHSIZE_A { + #[doc = "0: 8 bits"] + _8_BIT = 0, + #[doc = "1: 9 bits"] + _9_BIT = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CHSIZE_A) -> Self { + variant as _ + } +} +#[doc = "Field `CHSIZE` reader - Character Size"] +pub struct CHSIZE_R(crate::FieldReader); +impl CHSIZE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CHSIZE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CHSIZE_A::_8_BIT), + 1 => Some(CHSIZE_A::_9_BIT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_8_BIT`"] + #[inline(always)] + pub fn is_8_bit(&self) -> bool { + **self == CHSIZE_A::_8_BIT + } + #[doc = "Checks if the value of the field is `_9_BIT`"] + #[inline(always)] + pub fn is_9_bit(&self) -> bool { + **self == CHSIZE_A::_9_BIT + } +} +impl core::ops::Deref for CHSIZE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHSIZE` writer - Character Size"] +pub struct CHSIZE_W<'a> { + w: &'a mut W, +} +impl<'a> CHSIZE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CHSIZE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8 bits"] + #[inline(always)] + pub fn _8_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_8_BIT) + } + #[doc = "9 bits"] + #[inline(always)] + pub fn _9_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_9_BIT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Field `PLOADEN` reader - Data Preload Enable"] +pub struct PLOADEN_R(crate::FieldReader); +impl PLOADEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PLOADEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PLOADEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PLOADEN` writer - Data Preload Enable"] +pub struct PLOADEN_W<'a> { + w: &'a mut W, +} +impl<'a> PLOADEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `SSDE` reader - Slave Select Low Detect Enable"] +pub struct SSDE_R(crate::FieldReader); +impl SSDE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SSDE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSDE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSDE` writer - Slave Select Low Detect Enable"] +pub struct SSDE_W<'a> { + w: &'a mut W, +} +impl<'a> SSDE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `MSSEN` reader - Master Slave Select Enable"] +pub struct MSSEN_R(crate::FieldReader); +impl MSSEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MSSEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MSSEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MSSEN` writer - Master Slave Select Enable"] +pub struct MSSEN_W<'a> { + w: &'a mut W, +} +impl<'a> MSSEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Address Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum AMODE_A { + #[doc = "0: SPI Address mask"] + MASK = 0, + #[doc = "1: Two unique Addressess"] + _2_ADDRESSES = 1, + #[doc = "2: Address Range"] + RANGE = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: AMODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `AMODE` reader - Address Mode"] +pub struct AMODE_R(crate::FieldReader); +impl AMODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + AMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(AMODE_A::MASK), + 1 => Some(AMODE_A::_2_ADDRESSES), + 2 => Some(AMODE_A::RANGE), + _ => None, + } + } + #[doc = "Checks if the value of the field is `MASK`"] + #[inline(always)] + pub fn is_mask(&self) -> bool { + **self == AMODE_A::MASK + } + #[doc = "Checks if the value of the field is `_2_ADDRESSES`"] + #[inline(always)] + pub fn is_2_addresses(&self) -> bool { + **self == AMODE_A::_2_ADDRESSES + } + #[doc = "Checks if the value of the field is `RANGE`"] + #[inline(always)] + pub fn is_range(&self) -> bool { + **self == AMODE_A::RANGE + } +} +impl core::ops::Deref for AMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AMODE` writer - Address Mode"] +pub struct AMODE_W<'a> { + w: &'a mut W, +} +impl<'a> AMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: AMODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "SPI Address mask"] + #[inline(always)] + pub fn mask(self) -> &'a mut W { + self.variant(AMODE_A::MASK) + } + #[doc = "Two unique Addressess"] + #[inline(always)] + pub fn _2_addresses(self) -> &'a mut W { + self.variant(AMODE_A::_2_ADDRESSES) + } + #[doc = "Address Range"] + #[inline(always)] + pub fn range(self) -> &'a mut W { + self.variant(AMODE_A::RANGE) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 14)) | ((value as u32 & 0x03) << 14); + self.w + } +} +#[doc = "Field `RXEN` reader - Receiver Enable"] +pub struct RXEN_R(crate::FieldReader); +impl RXEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXEN` writer - Receiver Enable"] +pub struct RXEN_W<'a> { + w: &'a mut W, +} +impl<'a> RXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&self) -> CHSIZE_R { + CHSIZE_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 6 - Data Preload Enable"] + #[inline(always)] + pub fn ploaden(&self) -> PLOADEN_R { + PLOADEN_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 9 - Slave Select Low Detect Enable"] + #[inline(always)] + pub fn ssde(&self) -> SSDE_R { + SSDE_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 13 - Master Slave Select Enable"] + #[inline(always)] + pub fn mssen(&self) -> MSSEN_R { + MSSEN_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bits 14:15 - Address Mode"] + #[inline(always)] + pub fn amode(&self) -> AMODE_R { + AMODE_R::new(((self.bits >> 14) & 0x03) as u8) + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&self) -> RXEN_R { + RXEN_R::new(((self.bits >> 17) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&mut self) -> CHSIZE_W { + CHSIZE_W { w: self } + } + #[doc = "Bit 6 - Data Preload Enable"] + #[inline(always)] + pub fn ploaden(&mut self) -> PLOADEN_W { + PLOADEN_W { w: self } + } + #[doc = "Bit 9 - Slave Select Low Detect Enable"] + #[inline(always)] + pub fn ssde(&mut self) -> SSDE_W { + SSDE_W { w: self } + } + #[doc = "Bit 13 - Master Slave Select Enable"] + #[inline(always)] + pub fn mssen(&mut self) -> MSSEN_W { + MSSEN_W { w: self } + } + #[doc = "Bits 14:15 - Address Mode"] + #[inline(always)] + pub fn amode(&mut self) -> AMODE_W { + AMODE_W { w: self } + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&mut self) -> RXEN_W { + RXEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sercom0/spim/data.rs b/pac/atsamc21j/src/sercom0/spim/data.rs new file mode 100644 index 000000000000..dc9cd020d2a5 --- /dev/null +++ b/pac/atsamc21j/src/sercom0/spim/data.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data Value"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data Value"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01ff) | (value as u32 & 0x01ff); + self.w + } +} +impl R { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new((self.bits & 0x01ff) as u16) + } +} +impl W { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sercom0/spim/dbgctrl.rs b/pac/atsamc21j/src/sercom0/spim/dbgctrl.rs new file mode 100644 index 000000000000..d9aa7495940c --- /dev/null +++ b/pac/atsamc21j/src/sercom0/spim/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGSTOP` reader - Debug Mode"] +pub struct DBGSTOP_R(crate::FieldReader); +impl DBGSTOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGSTOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGSTOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGSTOP` writer - Debug Mode"] +pub struct DBGSTOP_W<'a> { + w: &'a mut W, +} +impl<'a> DBGSTOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&self) -> DBGSTOP_R { + DBGSTOP_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&mut self) -> DBGSTOP_W { + DBGSTOP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sercom0/spim/intenclr.rs b/pac/atsamc21j/src/sercom0/spim/intenclr.rs new file mode 100644 index 000000000000..ccab3de4348d --- /dev/null +++ b/pac/atsamc21j/src/sercom0/spim/intenclr.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Disable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Disable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Disable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Disable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Disable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Disable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SSL` reader - Slave Select Low Interrupt Disable"] +pub struct SSL_R(crate::FieldReader); +impl SSL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SSL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSL` writer - Slave Select Low Interrupt Disable"] +pub struct SSL_W<'a> { + w: &'a mut W, +} +impl<'a> SSL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Disable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Disable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Slave Select Low Interrupt Disable"] + #[inline(always)] + pub fn ssl(&self) -> SSL_R { + SSL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Slave Select Low Interrupt Disable"] + #[inline(always)] + pub fn ssl(&mut self) -> SSL_W { + SSL_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sercom0/spim/intenset.rs b/pac/atsamc21j/src/sercom0/spim/intenset.rs new file mode 100644 index 000000000000..d9779cf897c2 --- /dev/null +++ b/pac/atsamc21j/src/sercom0/spim/intenset.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Enable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Enable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Enable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Enable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Enable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Enable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SSL` reader - Slave Select Low Interrupt Enable"] +pub struct SSL_R(crate::FieldReader); +impl SSL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SSL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSL` writer - Slave Select Low Interrupt Enable"] +pub struct SSL_W<'a> { + w: &'a mut W, +} +impl<'a> SSL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Slave Select Low Interrupt Enable"] + #[inline(always)] + pub fn ssl(&self) -> SSL_R { + SSL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Slave Select Low Interrupt Enable"] + #[inline(always)] + pub fn ssl(&mut self) -> SSL_W { + SSL_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sercom0/spim/intflag.rs b/pac/atsamc21j/src/sercom0/spim/intflag.rs new file mode 100644 index 000000000000..e9bc10c271b8 --- /dev/null +++ b/pac/atsamc21j/src/sercom0/spim/intflag.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SSL` reader - Slave Select Low Interrupt Flag"] +pub struct SSL_R(crate::FieldReader); +impl SSL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SSL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSL` writer - Slave Select Low Interrupt Flag"] +pub struct SSL_W<'a> { + w: &'a mut W, +} +impl<'a> SSL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Slave Select Low Interrupt Flag"] + #[inline(always)] + pub fn ssl(&self) -> SSL_R { + SSL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Slave Select Low Interrupt Flag"] + #[inline(always)] + pub fn ssl(&mut self) -> SSL_W { + SSL_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sercom0/spim/status.rs b/pac/atsamc21j/src/sercom0/spim/status.rs new file mode 100644 index 000000000000..9919460bf0e2 --- /dev/null +++ b/pac/atsamc21j/src/sercom0/spim/status.rs @@ -0,0 +1,113 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BUFOVF` reader - Buffer Overflow"] +pub struct BUFOVF_R(crate::FieldReader); +impl BUFOVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUFOVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUFOVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUFOVF` writer - Buffer Overflow"] +pub struct BUFOVF_W<'a> { + w: &'a mut W, +} +impl<'a> BUFOVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&self) -> BUFOVF_R { + BUFOVF_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&mut self) -> BUFOVF_W { + BUFOVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sercom0/spim/syncbusy.rs b/pac/atsamc21j/src/sercom0/spim/syncbusy.rs new file mode 100644 index 000000000000..bee13adf7084 --- /dev/null +++ b/pac/atsamc21j/src/sercom0/spim/syncbusy.rs @@ -0,0 +1,93 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - SERCOM Enable Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLB` reader - CTRLB Synchronization Busy"] +pub struct CTRLB_R(crate::FieldReader); +impl CTRLB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM Enable Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - CTRLB Synchronization Busy"] + #[inline(always)] + pub fn ctrlb(&self) -> CTRLB_R { + CTRLB_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +#[doc = "SPIM Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sercom0/spis.rs b/pac/atsamc21j/src/sercom0/spis.rs new file mode 100644 index 000000000000..eed10c90c460 --- /dev/null +++ b/pac/atsamc21j/src/sercom0/spis.rs @@ -0,0 +1,44 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "SPIS Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "SPIS Control B"] +pub mod ctrlb; +#[doc = "BAUD register accessor: an alias for `Reg`"] +pub type BAUD = crate::Reg; +#[doc = "SPIS Baud Rate"] +pub mod baud; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "SPIS Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "SPIS Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "SPIS Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "SPIS Status"] +pub mod status; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "SPIS Synchronization Busy"] +pub mod syncbusy; +#[doc = "ADDR register accessor: an alias for `Reg`"] +pub type ADDR = crate::Reg; +#[doc = "SPIS Address"] +pub mod addr; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "SPIS Data"] +pub mod data; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "SPIS Debug Control"] +pub mod dbgctrl; diff --git a/pac/atsamc21j/src/sercom0/spis/addr.rs b/pac/atsamc21j/src/sercom0/spis/addr.rs new file mode 100644 index 000000000000..5fca0a698bfe --- /dev/null +++ b/pac/atsamc21j/src/sercom0/spis/addr.rs @@ -0,0 +1,140 @@ +#[doc = "Register `ADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ADDR` reader - Address Value"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - Address Value"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +#[doc = "Field `ADDRMASK` reader - Address Mask"] +pub struct ADDRMASK_R(crate::FieldReader); +impl ADDRMASK_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ADDRMASK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDRMASK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDRMASK` writer - Address Mask"] +pub struct ADDRMASK_W<'a> { + w: &'a mut W, +} +impl<'a> ADDRMASK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Address Value"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 16:23 - Address Mask"] + #[inline(always)] + pub fn addrmask(&self) -> ADDRMASK_R { + ADDRMASK_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Address Value"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Bits 16:23 - Address Mask"] + #[inline(always)] + pub fn addrmask(&mut self) -> ADDRMASK_W { + ADDRMASK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [addr](index.html) module"] +pub struct ADDR_SPEC; +impl crate::RegisterSpec for ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [addr::R](R) reader structure"] +impl crate::Readable for ADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [addr::W](W) writer structure"] +impl crate::Writable for ADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ADDR to value 0"] +impl crate::Resettable for ADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sercom0/spis/baud.rs b/pac/atsamc21j/src/sercom0/spis/baud.rs new file mode 100644 index 000000000000..eeee4cf633e5 --- /dev/null +++ b/pac/atsamc21j/src/sercom0/spis/baud.rs @@ -0,0 +1,103 @@ +#[doc = "Register `BAUD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud](index.html) module"] +pub struct BAUD_SPEC; +impl crate::RegisterSpec for BAUD_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [baud::R](R) reader structure"] +impl crate::Readable for BAUD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud::W](W) writer structure"] +impl crate::Writable for BAUD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD to value 0"] +impl crate::Resettable for BAUD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sercom0/spis/ctrla.rs b/pac/atsamc21j/src/sercom0/spis/ctrla.rs new file mode 100644 index 000000000000..6151433a8529 --- /dev/null +++ b/pac/atsamc21j/src/sercom0/spis/ctrla.rs @@ -0,0 +1,992 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: USART with external clock"] + USART_EXT_CLK = 0, + #[doc = "1: USART with internal clock"] + USART_INT_CLK = 1, + #[doc = "2: SPI in slave operation"] + SPI_SLAVE = 2, + #[doc = "3: SPI in master operation"] + SPI_MASTER = 3, + #[doc = "4: I2C slave operation"] + I2C_SLAVE = 4, + #[doc = "5: I2C master operation"] + I2C_MASTER = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::USART_EXT_CLK), + 1 => Some(MODE_A::USART_INT_CLK), + 2 => Some(MODE_A::SPI_SLAVE), + 3 => Some(MODE_A::SPI_MASTER), + 4 => Some(MODE_A::I2C_SLAVE), + 5 => Some(MODE_A::I2C_MASTER), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_EXT_CLK`"] + #[inline(always)] + pub fn is_usart_ext_clk(&self) -> bool { + **self == MODE_A::USART_EXT_CLK + } + #[doc = "Checks if the value of the field is `USART_INT_CLK`"] + #[inline(always)] + pub fn is_usart_int_clk(&self) -> bool { + **self == MODE_A::USART_INT_CLK + } + #[doc = "Checks if the value of the field is `SPI_SLAVE`"] + #[inline(always)] + pub fn is_spi_slave(&self) -> bool { + **self == MODE_A::SPI_SLAVE + } + #[doc = "Checks if the value of the field is `SPI_MASTER`"] + #[inline(always)] + pub fn is_spi_master(&self) -> bool { + **self == MODE_A::SPI_MASTER + } + #[doc = "Checks if the value of the field is `I2C_SLAVE`"] + #[inline(always)] + pub fn is_i2c_slave(&self) -> bool { + **self == MODE_A::I2C_SLAVE + } + #[doc = "Checks if the value of the field is `I2C_MASTER`"] + #[inline(always)] + pub fn is_i2c_master(&self) -> bool { + **self == MODE_A::I2C_MASTER + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART with external clock"] + #[inline(always)] + pub fn usart_ext_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_EXT_CLK) + } + #[doc = "USART with internal clock"] + #[inline(always)] + pub fn usart_int_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_INT_CLK) + } + #[doc = "SPI in slave operation"] + #[inline(always)] + pub fn spi_slave(self) -> &'a mut W { + self.variant(MODE_A::SPI_SLAVE) + } + #[doc = "SPI in master operation"] + #[inline(always)] + pub fn spi_master(self) -> &'a mut W { + self.variant(MODE_A::SPI_MASTER) + } + #[doc = "I2C slave operation"] + #[inline(always)] + pub fn i2c_slave(self) -> &'a mut W { + self.variant(MODE_A::I2C_SLAVE) + } + #[doc = "I2C master operation"] + #[inline(always)] + pub fn i2c_master(self) -> &'a mut W { + self.variant(MODE_A::I2C_MASTER) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 2)) | ((value as u32 & 0x07) << 2); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `IBON` reader - Immediate Buffer Overflow Notification"] +pub struct IBON_R(crate::FieldReader); +impl IBON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IBON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IBON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IBON` writer - Immediate Buffer Overflow Notification"] +pub struct IBON_W<'a> { + w: &'a mut W, +} +impl<'a> IBON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Data Out Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DOPO_A { + #[doc = "0: DO on PAD\\[0\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + PAD0 = 0, + #[doc = "1: DO on PAD\\[2\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + PAD1 = 1, + #[doc = "2: DO on PAD\\[3\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + PAD2 = 2, + #[doc = "3: DO on PAD\\[0\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + PAD3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DOPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `DOPO` reader - Data Out Pinout"] +pub struct DOPO_R(crate::FieldReader); +impl DOPO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DOPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DOPO_A { + match self.bits { + 0 => DOPO_A::PAD0, + 1 => DOPO_A::PAD1, + 2 => DOPO_A::PAD2, + 3 => DOPO_A::PAD3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == DOPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD1`"] + #[inline(always)] + pub fn is_pad1(&self) -> bool { + **self == DOPO_A::PAD1 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == DOPO_A::PAD2 + } + #[doc = "Checks if the value of the field is `PAD3`"] + #[inline(always)] + pub fn is_pad3(&self) -> bool { + **self == DOPO_A::PAD3 + } +} +impl core::ops::Deref for DOPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DOPO` writer - Data Out Pinout"] +pub struct DOPO_W<'a> { + w: &'a mut W, +} +impl<'a> DOPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DOPO_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "DO on PAD\\[0\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(DOPO_A::PAD0) + } + #[doc = "DO on PAD\\[2\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + #[inline(always)] + pub fn pad1(self) -> &'a mut W { + self.variant(DOPO_A::PAD1) + } + #[doc = "DO on PAD\\[3\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(DOPO_A::PAD2) + } + #[doc = "DO on PAD\\[0\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + #[inline(always)] + pub fn pad3(self) -> &'a mut W { + self.variant(DOPO_A::PAD3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Data In Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DIPO_A { + #[doc = "0: SERCOM PAD\\[0\\]"] + PAD0 = 0, + #[doc = "1: SERCOM PAD\\[1\\]"] + PAD1 = 1, + #[doc = "2: SERCOM PAD\\[2\\]"] + PAD2 = 2, + #[doc = "3: SERCOM PAD\\[3\\]"] + PAD3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DIPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `DIPO` reader - Data In Pinout"] +pub struct DIPO_R(crate::FieldReader); +impl DIPO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DIPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DIPO_A { + match self.bits { + 0 => DIPO_A::PAD0, + 1 => DIPO_A::PAD1, + 2 => DIPO_A::PAD2, + 3 => DIPO_A::PAD3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == DIPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD1`"] + #[inline(always)] + pub fn is_pad1(&self) -> bool { + **self == DIPO_A::PAD1 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == DIPO_A::PAD2 + } + #[doc = "Checks if the value of the field is `PAD3`"] + #[inline(always)] + pub fn is_pad3(&self) -> bool { + **self == DIPO_A::PAD3 + } +} +impl core::ops::Deref for DIPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIPO` writer - Data In Pinout"] +pub struct DIPO_W<'a> { + w: &'a mut W, +} +impl<'a> DIPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DIPO_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "SERCOM PAD\\[0\\]"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(DIPO_A::PAD0) + } + #[doc = "SERCOM PAD\\[1\\]"] + #[inline(always)] + pub fn pad1(self) -> &'a mut W { + self.variant(DIPO_A::PAD1) + } + #[doc = "SERCOM PAD\\[2\\]"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(DIPO_A::PAD2) + } + #[doc = "SERCOM PAD\\[3\\]"] + #[inline(always)] + pub fn pad3(self) -> &'a mut W { + self.variant(DIPO_A::PAD3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 20)) | ((value as u32 & 0x03) << 20); + self.w + } +} +#[doc = "Frame Format\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FORM_A { + #[doc = "0: SPI Frame"] + SPI_FRAME = 0, + #[doc = "2: SPI Frame with Addr"] + SPI_FRAME_WITH_ADDR = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FORM_A) -> Self { + variant as _ + } +} +#[doc = "Field `FORM` reader - Frame Format"] +pub struct FORM_R(crate::FieldReader); +impl FORM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FORM_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(FORM_A::SPI_FRAME), + 2 => Some(FORM_A::SPI_FRAME_WITH_ADDR), + _ => None, + } + } + #[doc = "Checks if the value of the field is `SPI_FRAME`"] + #[inline(always)] + pub fn is_spi_frame(&self) -> bool { + **self == FORM_A::SPI_FRAME + } + #[doc = "Checks if the value of the field is `SPI_FRAME_WITH_ADDR`"] + #[inline(always)] + pub fn is_spi_frame_with_addr(&self) -> bool { + **self == FORM_A::SPI_FRAME_WITH_ADDR + } +} +impl core::ops::Deref for FORM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FORM` writer - Frame Format"] +pub struct FORM_W<'a> { + w: &'a mut W, +} +impl<'a> FORM_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FORM_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "SPI Frame"] + #[inline(always)] + pub fn spi_frame(self) -> &'a mut W { + self.variant(FORM_A::SPI_FRAME) + } + #[doc = "SPI Frame with Addr"] + #[inline(always)] + pub fn spi_frame_with_addr(self) -> &'a mut W { + self.variant(FORM_A::SPI_FRAME_WITH_ADDR) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Clock Phase\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CPHA_A { + #[doc = "0: The data is sampled on a leading SCK edge and changed on a trailing SCK edge"] + LEADING_EDGE = 0, + #[doc = "1: The data is sampled on a trailing SCK edge and changed on a leading SCK edge"] + TRAILING_EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CPHA_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CPHA` reader - Clock Phase"] +pub struct CPHA_R(crate::FieldReader); +impl CPHA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPHA_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CPHA_A { + match self.bits { + false => CPHA_A::LEADING_EDGE, + true => CPHA_A::TRAILING_EDGE, + } + } + #[doc = "Checks if the value of the field is `LEADING_EDGE`"] + #[inline(always)] + pub fn is_leading_edge(&self) -> bool { + **self == CPHA_A::LEADING_EDGE + } + #[doc = "Checks if the value of the field is `TRAILING_EDGE`"] + #[inline(always)] + pub fn is_trailing_edge(&self) -> bool { + **self == CPHA_A::TRAILING_EDGE + } +} +impl core::ops::Deref for CPHA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPHA` writer - Clock Phase"] +pub struct CPHA_W<'a> { + w: &'a mut W, +} +impl<'a> CPHA_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CPHA_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "The data is sampled on a leading SCK edge and changed on a trailing SCK edge"] + #[inline(always)] + pub fn leading_edge(self) -> &'a mut W { + self.variant(CPHA_A::LEADING_EDGE) + } + #[doc = "The data is sampled on a trailing SCK edge and changed on a leading SCK edge"] + #[inline(always)] + pub fn trailing_edge(self) -> &'a mut W { + self.variant(CPHA_A::TRAILING_EDGE) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Clock Polarity\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CPOL_A { + #[doc = "0: SCK is low when idle"] + IDLE_LOW = 0, + #[doc = "1: SCK is high when idle"] + IDLE_HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CPOL_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CPOL` reader - Clock Polarity"] +pub struct CPOL_R(crate::FieldReader); +impl CPOL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPOL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CPOL_A { + match self.bits { + false => CPOL_A::IDLE_LOW, + true => CPOL_A::IDLE_HIGH, + } + } + #[doc = "Checks if the value of the field is `IDLE_LOW`"] + #[inline(always)] + pub fn is_idle_low(&self) -> bool { + **self == CPOL_A::IDLE_LOW + } + #[doc = "Checks if the value of the field is `IDLE_HIGH`"] + #[inline(always)] + pub fn is_idle_high(&self) -> bool { + **self == CPOL_A::IDLE_HIGH + } +} +impl core::ops::Deref for CPOL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPOL` writer - Clock Polarity"] +pub struct CPOL_W<'a> { + w: &'a mut W, +} +impl<'a> CPOL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CPOL_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "SCK is low when idle"] + #[inline(always)] + pub fn idle_low(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_LOW) + } + #[doc = "SCK is high when idle"] + #[inline(always)] + pub fn idle_high(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_HIGH) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29); + self.w + } +} +#[doc = "Data Order\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum DORD_A { + #[doc = "0: MSB is transferred first"] + MSB = 0, + #[doc = "1: LSB is transferred first"] + LSB = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DORD_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DORD` reader - Data Order"] +pub struct DORD_R(crate::FieldReader); +impl DORD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DORD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DORD_A { + match self.bits { + false => DORD_A::MSB, + true => DORD_A::LSB, + } + } + #[doc = "Checks if the value of the field is `MSB`"] + #[inline(always)] + pub fn is_msb(&self) -> bool { + **self == DORD_A::MSB + } + #[doc = "Checks if the value of the field is `LSB`"] + #[inline(always)] + pub fn is_lsb(&self) -> bool { + **self == DORD_A::LSB + } +} +impl core::ops::Deref for DORD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DORD` writer - Data Order"] +pub struct DORD_W<'a> { + w: &'a mut W, +} +impl<'a> DORD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DORD_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "MSB is transferred first"] + #[inline(always)] + pub fn msb(self) -> &'a mut W { + self.variant(DORD_A::MSB) + } + #[doc = "LSB is transferred first"] + #[inline(always)] + pub fn lsb(self) -> &'a mut W { + self.variant(DORD_A::LSB) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x07) as u8) + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&self) -> IBON_R { + IBON_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bits 16:17 - Data Out Pinout"] + #[inline(always)] + pub fn dopo(&self) -> DOPO_R { + DOPO_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bits 20:21 - Data In Pinout"] + #[inline(always)] + pub fn dipo(&self) -> DIPO_R { + DIPO_R::new(((self.bits >> 20) & 0x03) as u8) + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&self) -> FORM_R { + FORM_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 28 - Clock Phase"] + #[inline(always)] + pub fn cpha(&self) -> CPHA_R { + CPHA_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&self) -> CPOL_R { + CPOL_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&self) -> DORD_R { + DORD_R::new(((self.bits >> 30) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&mut self) -> IBON_W { + IBON_W { w: self } + } + #[doc = "Bits 16:17 - Data Out Pinout"] + #[inline(always)] + pub fn dopo(&mut self) -> DOPO_W { + DOPO_W { w: self } + } + #[doc = "Bits 20:21 - Data In Pinout"] + #[inline(always)] + pub fn dipo(&mut self) -> DIPO_W { + DIPO_W { w: self } + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&mut self) -> FORM_W { + FORM_W { w: self } + } + #[doc = "Bit 28 - Clock Phase"] + #[inline(always)] + pub fn cpha(&mut self) -> CPHA_W { + CPHA_W { w: self } + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&mut self) -> CPOL_W { + CPOL_W { w: self } + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&mut self) -> DORD_W { + DORD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sercom0/spis/ctrlb.rs b/pac/atsamc21j/src/sercom0/spis/ctrlb.rs new file mode 100644 index 000000000000..ccb70582cf34 --- /dev/null +++ b/pac/atsamc21j/src/sercom0/spis/ctrlb.rs @@ -0,0 +1,439 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Character Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CHSIZE_A { + #[doc = "0: 8 bits"] + _8_BIT = 0, + #[doc = "1: 9 bits"] + _9_BIT = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CHSIZE_A) -> Self { + variant as _ + } +} +#[doc = "Field `CHSIZE` reader - Character Size"] +pub struct CHSIZE_R(crate::FieldReader); +impl CHSIZE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CHSIZE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CHSIZE_A::_8_BIT), + 1 => Some(CHSIZE_A::_9_BIT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_8_BIT`"] + #[inline(always)] + pub fn is_8_bit(&self) -> bool { + **self == CHSIZE_A::_8_BIT + } + #[doc = "Checks if the value of the field is `_9_BIT`"] + #[inline(always)] + pub fn is_9_bit(&self) -> bool { + **self == CHSIZE_A::_9_BIT + } +} +impl core::ops::Deref for CHSIZE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHSIZE` writer - Character Size"] +pub struct CHSIZE_W<'a> { + w: &'a mut W, +} +impl<'a> CHSIZE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CHSIZE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8 bits"] + #[inline(always)] + pub fn _8_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_8_BIT) + } + #[doc = "9 bits"] + #[inline(always)] + pub fn _9_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_9_BIT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Field `PLOADEN` reader - Data Preload Enable"] +pub struct PLOADEN_R(crate::FieldReader); +impl PLOADEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PLOADEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PLOADEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PLOADEN` writer - Data Preload Enable"] +pub struct PLOADEN_W<'a> { + w: &'a mut W, +} +impl<'a> PLOADEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `SSDE` reader - Slave Select Low Detect Enable"] +pub struct SSDE_R(crate::FieldReader); +impl SSDE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SSDE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSDE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSDE` writer - Slave Select Low Detect Enable"] +pub struct SSDE_W<'a> { + w: &'a mut W, +} +impl<'a> SSDE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `MSSEN` reader - Master Slave Select Enable"] +pub struct MSSEN_R(crate::FieldReader); +impl MSSEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MSSEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MSSEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MSSEN` writer - Master Slave Select Enable"] +pub struct MSSEN_W<'a> { + w: &'a mut W, +} +impl<'a> MSSEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Address Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum AMODE_A { + #[doc = "0: SPI Address mask"] + MASK = 0, + #[doc = "1: Two unique Addressess"] + _2_ADDRESSES = 1, + #[doc = "2: Address Range"] + RANGE = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: AMODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `AMODE` reader - Address Mode"] +pub struct AMODE_R(crate::FieldReader); +impl AMODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + AMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(AMODE_A::MASK), + 1 => Some(AMODE_A::_2_ADDRESSES), + 2 => Some(AMODE_A::RANGE), + _ => None, + } + } + #[doc = "Checks if the value of the field is `MASK`"] + #[inline(always)] + pub fn is_mask(&self) -> bool { + **self == AMODE_A::MASK + } + #[doc = "Checks if the value of the field is `_2_ADDRESSES`"] + #[inline(always)] + pub fn is_2_addresses(&self) -> bool { + **self == AMODE_A::_2_ADDRESSES + } + #[doc = "Checks if the value of the field is `RANGE`"] + #[inline(always)] + pub fn is_range(&self) -> bool { + **self == AMODE_A::RANGE + } +} +impl core::ops::Deref for AMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AMODE` writer - Address Mode"] +pub struct AMODE_W<'a> { + w: &'a mut W, +} +impl<'a> AMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: AMODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "SPI Address mask"] + #[inline(always)] + pub fn mask(self) -> &'a mut W { + self.variant(AMODE_A::MASK) + } + #[doc = "Two unique Addressess"] + #[inline(always)] + pub fn _2_addresses(self) -> &'a mut W { + self.variant(AMODE_A::_2_ADDRESSES) + } + #[doc = "Address Range"] + #[inline(always)] + pub fn range(self) -> &'a mut W { + self.variant(AMODE_A::RANGE) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 14)) | ((value as u32 & 0x03) << 14); + self.w + } +} +#[doc = "Field `RXEN` reader - Receiver Enable"] +pub struct RXEN_R(crate::FieldReader); +impl RXEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXEN` writer - Receiver Enable"] +pub struct RXEN_W<'a> { + w: &'a mut W, +} +impl<'a> RXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&self) -> CHSIZE_R { + CHSIZE_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 6 - Data Preload Enable"] + #[inline(always)] + pub fn ploaden(&self) -> PLOADEN_R { + PLOADEN_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 9 - Slave Select Low Detect Enable"] + #[inline(always)] + pub fn ssde(&self) -> SSDE_R { + SSDE_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 13 - Master Slave Select Enable"] + #[inline(always)] + pub fn mssen(&self) -> MSSEN_R { + MSSEN_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bits 14:15 - Address Mode"] + #[inline(always)] + pub fn amode(&self) -> AMODE_R { + AMODE_R::new(((self.bits >> 14) & 0x03) as u8) + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&self) -> RXEN_R { + RXEN_R::new(((self.bits >> 17) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&mut self) -> CHSIZE_W { + CHSIZE_W { w: self } + } + #[doc = "Bit 6 - Data Preload Enable"] + #[inline(always)] + pub fn ploaden(&mut self) -> PLOADEN_W { + PLOADEN_W { w: self } + } + #[doc = "Bit 9 - Slave Select Low Detect Enable"] + #[inline(always)] + pub fn ssde(&mut self) -> SSDE_W { + SSDE_W { w: self } + } + #[doc = "Bit 13 - Master Slave Select Enable"] + #[inline(always)] + pub fn mssen(&mut self) -> MSSEN_W { + MSSEN_W { w: self } + } + #[doc = "Bits 14:15 - Address Mode"] + #[inline(always)] + pub fn amode(&mut self) -> AMODE_W { + AMODE_W { w: self } + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&mut self) -> RXEN_W { + RXEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sercom0/spis/data.rs b/pac/atsamc21j/src/sercom0/spis/data.rs new file mode 100644 index 000000000000..4edf8089b29f --- /dev/null +++ b/pac/atsamc21j/src/sercom0/spis/data.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data Value"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data Value"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01ff) | (value as u32 & 0x01ff); + self.w + } +} +impl R { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new((self.bits & 0x01ff) as u16) + } +} +impl W { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sercom0/spis/dbgctrl.rs b/pac/atsamc21j/src/sercom0/spis/dbgctrl.rs new file mode 100644 index 000000000000..ec36bbd26057 --- /dev/null +++ b/pac/atsamc21j/src/sercom0/spis/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGSTOP` reader - Debug Mode"] +pub struct DBGSTOP_R(crate::FieldReader); +impl DBGSTOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGSTOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGSTOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGSTOP` writer - Debug Mode"] +pub struct DBGSTOP_W<'a> { + w: &'a mut W, +} +impl<'a> DBGSTOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&self) -> DBGSTOP_R { + DBGSTOP_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&mut self) -> DBGSTOP_W { + DBGSTOP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sercom0/spis/intenclr.rs b/pac/atsamc21j/src/sercom0/spis/intenclr.rs new file mode 100644 index 000000000000..e4c9ee0d506d --- /dev/null +++ b/pac/atsamc21j/src/sercom0/spis/intenclr.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Disable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Disable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Disable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Disable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Disable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Disable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SSL` reader - Slave Select Low Interrupt Disable"] +pub struct SSL_R(crate::FieldReader); +impl SSL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SSL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSL` writer - Slave Select Low Interrupt Disable"] +pub struct SSL_W<'a> { + w: &'a mut W, +} +impl<'a> SSL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Disable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Disable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Slave Select Low Interrupt Disable"] + #[inline(always)] + pub fn ssl(&self) -> SSL_R { + SSL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Slave Select Low Interrupt Disable"] + #[inline(always)] + pub fn ssl(&mut self) -> SSL_W { + SSL_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sercom0/spis/intenset.rs b/pac/atsamc21j/src/sercom0/spis/intenset.rs new file mode 100644 index 000000000000..99582a624ebc --- /dev/null +++ b/pac/atsamc21j/src/sercom0/spis/intenset.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Enable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Enable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Enable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Enable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Enable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Enable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SSL` reader - Slave Select Low Interrupt Enable"] +pub struct SSL_R(crate::FieldReader); +impl SSL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SSL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSL` writer - Slave Select Low Interrupt Enable"] +pub struct SSL_W<'a> { + w: &'a mut W, +} +impl<'a> SSL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Slave Select Low Interrupt Enable"] + #[inline(always)] + pub fn ssl(&self) -> SSL_R { + SSL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Slave Select Low Interrupt Enable"] + #[inline(always)] + pub fn ssl(&mut self) -> SSL_W { + SSL_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sercom0/spis/intflag.rs b/pac/atsamc21j/src/sercom0/spis/intflag.rs new file mode 100644 index 000000000000..589e73c2329f --- /dev/null +++ b/pac/atsamc21j/src/sercom0/spis/intflag.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SSL` reader - Slave Select Low Interrupt Flag"] +pub struct SSL_R(crate::FieldReader); +impl SSL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SSL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSL` writer - Slave Select Low Interrupt Flag"] +pub struct SSL_W<'a> { + w: &'a mut W, +} +impl<'a> SSL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Slave Select Low Interrupt Flag"] + #[inline(always)] + pub fn ssl(&self) -> SSL_R { + SSL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Slave Select Low Interrupt Flag"] + #[inline(always)] + pub fn ssl(&mut self) -> SSL_W { + SSL_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sercom0/spis/status.rs b/pac/atsamc21j/src/sercom0/spis/status.rs new file mode 100644 index 000000000000..55c39c1a709f --- /dev/null +++ b/pac/atsamc21j/src/sercom0/spis/status.rs @@ -0,0 +1,113 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BUFOVF` reader - Buffer Overflow"] +pub struct BUFOVF_R(crate::FieldReader); +impl BUFOVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUFOVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUFOVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUFOVF` writer - Buffer Overflow"] +pub struct BUFOVF_W<'a> { + w: &'a mut W, +} +impl<'a> BUFOVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&self) -> BUFOVF_R { + BUFOVF_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&mut self) -> BUFOVF_W { + BUFOVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sercom0/spis/syncbusy.rs b/pac/atsamc21j/src/sercom0/spis/syncbusy.rs new file mode 100644 index 000000000000..ac2f2e2c27ec --- /dev/null +++ b/pac/atsamc21j/src/sercom0/spis/syncbusy.rs @@ -0,0 +1,93 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - SERCOM Enable Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLB` reader - CTRLB Synchronization Busy"] +pub struct CTRLB_R(crate::FieldReader); +impl CTRLB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM Enable Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - CTRLB Synchronization Busy"] + #[inline(always)] + pub fn ctrlb(&self) -> CTRLB_R { + CTRLB_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +#[doc = "SPIS Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sercom0/usart_ext.rs b/pac/atsamc21j/src/sercom0/usart_ext.rs new file mode 100644 index 000000000000..8c08b9efc1d5 --- /dev/null +++ b/pac/atsamc21j/src/sercom0/usart_ext.rs @@ -0,0 +1,60 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "USART_EXT Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "USART_EXT Control B"] +pub mod ctrlb; +#[doc = "CTRLC register accessor: an alias for `Reg`"] +pub type CTRLC = crate::Reg; +#[doc = "USART_EXT Control C"] +pub mod ctrlc; +#[doc = "BAUD register accessor: an alias for `Reg`"] +pub type BAUD = crate::Reg; +#[doc = "USART_EXT Baud Rate"] +pub mod baud; +#[doc = "BAUD_FRAC_MODE register accessor: an alias for `Reg`"] +pub type BAUD_FRAC_MODE = crate::Reg; +#[doc = "USART_EXT Baud Rate"] +pub mod baud_frac_mode; +#[doc = "BAUD_FRACFP_MODE register accessor: an alias for `Reg`"] +pub type BAUD_FRACFP_MODE = crate::Reg; +#[doc = "USART_EXT Baud Rate"] +pub mod baud_fracfp_mode; +#[doc = "BAUD_USARTFP_MODE register accessor: an alias for `Reg`"] +pub type BAUD_USARTFP_MODE = crate::Reg; +#[doc = "USART_EXT Baud Rate"] +pub mod baud_usartfp_mode; +#[doc = "RXPL register accessor: an alias for `Reg`"] +pub type RXPL = crate::Reg; +#[doc = "USART_EXT Receive Pulse Length"] +pub mod rxpl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "USART_EXT Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "USART_EXT Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "USART_EXT Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "USART_EXT Status"] +pub mod status; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "USART_EXT Synchronization Busy"] +pub mod syncbusy; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "USART_EXT Data"] +pub mod data; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "USART_EXT Debug Control"] +pub mod dbgctrl; diff --git a/pac/atsamc21j/src/sercom0/usart_ext/baud.rs b/pac/atsamc21j/src/sercom0/usart_ext/baud.rs new file mode 100644 index 000000000000..9558a8e1a52d --- /dev/null +++ b/pac/atsamc21j/src/sercom0/usart_ext/baud.rs @@ -0,0 +1,103 @@ +#[doc = "Register `BAUD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud](index.html) module"] +pub struct BAUD_SPEC; +impl crate::RegisterSpec for BAUD_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud::R](R) reader structure"] +impl crate::Readable for BAUD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud::W](W) writer structure"] +impl crate::Writable for BAUD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD to value 0"] +impl crate::Resettable for BAUD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sercom0/usart_ext/baud_frac_mode.rs b/pac/atsamc21j/src/sercom0/usart_ext/baud_frac_mode.rs new file mode 100644 index 000000000000..d7cdd4570e26 --- /dev/null +++ b/pac/atsamc21j/src/sercom0/usart_ext/baud_frac_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `BAUD_FRAC_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD_FRAC_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1fff) | (value as u16 & 0x1fff); + self.w + } +} +#[doc = "Field `FP` reader - Fractional Part"] +pub struct FP_R(crate::FieldReader); +impl FP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FP` writer - Fractional Part"] +pub struct FP_W<'a> { + w: &'a mut W, +} +impl<'a> FP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 13)) | ((value as u16 & 0x07) << 13); + self.w + } +} +impl R { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new((self.bits & 0x1fff) as u16) + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&self) -> FP_R { + FP_R::new(((self.bits >> 13) & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&mut self) -> FP_W { + FP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud_frac_mode](index.html) module"] +pub struct BAUD_FRAC_MODE_SPEC; +impl crate::RegisterSpec for BAUD_FRAC_MODE_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud_frac_mode::R](R) reader structure"] +impl crate::Readable for BAUD_FRAC_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud_frac_mode::W](W) writer structure"] +impl crate::Writable for BAUD_FRAC_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD_FRAC_MODE to value 0"] +impl crate::Resettable for BAUD_FRAC_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sercom0/usart_ext/baud_fracfp_mode.rs b/pac/atsamc21j/src/sercom0/usart_ext/baud_fracfp_mode.rs new file mode 100644 index 000000000000..c1dc50807677 --- /dev/null +++ b/pac/atsamc21j/src/sercom0/usart_ext/baud_fracfp_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `BAUD_FRACFP_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD_FRACFP_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1fff) | (value as u16 & 0x1fff); + self.w + } +} +#[doc = "Field `FP` reader - Fractional Part"] +pub struct FP_R(crate::FieldReader); +impl FP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FP` writer - Fractional Part"] +pub struct FP_W<'a> { + w: &'a mut W, +} +impl<'a> FP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 13)) | ((value as u16 & 0x07) << 13); + self.w + } +} +impl R { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new((self.bits & 0x1fff) as u16) + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&self) -> FP_R { + FP_R::new(((self.bits >> 13) & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&mut self) -> FP_W { + FP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud_fracfp_mode](index.html) module"] +pub struct BAUD_FRACFP_MODE_SPEC; +impl crate::RegisterSpec for BAUD_FRACFP_MODE_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud_fracfp_mode::R](R) reader structure"] +impl crate::Readable for BAUD_FRACFP_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud_fracfp_mode::W](W) writer structure"] +impl crate::Writable for BAUD_FRACFP_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD_FRACFP_MODE to value 0"] +impl crate::Resettable for BAUD_FRACFP_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sercom0/usart_ext/baud_usartfp_mode.rs b/pac/atsamc21j/src/sercom0/usart_ext/baud_usartfp_mode.rs new file mode 100644 index 000000000000..8d4db16e0245 --- /dev/null +++ b/pac/atsamc21j/src/sercom0/usart_ext/baud_usartfp_mode.rs @@ -0,0 +1,103 @@ +#[doc = "Register `BAUD_USARTFP_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD_USARTFP_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud_usartfp_mode](index.html) module"] +pub struct BAUD_USARTFP_MODE_SPEC; +impl crate::RegisterSpec for BAUD_USARTFP_MODE_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud_usartfp_mode::R](R) reader structure"] +impl crate::Readable for BAUD_USARTFP_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud_usartfp_mode::W](W) writer structure"] +impl crate::Writable for BAUD_USARTFP_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD_USARTFP_MODE to value 0"] +impl crate::Resettable for BAUD_USARTFP_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sercom0/usart_ext/ctrla.rs b/pac/atsamc21j/src/sercom0/usart_ext/ctrla.rs new file mode 100644 index 000000000000..535875ac8b25 --- /dev/null +++ b/pac/atsamc21j/src/sercom0/usart_ext/ctrla.rs @@ -0,0 +1,1171 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: USART with external clock"] + USART_EXT_CLK = 0, + #[doc = "1: USART with internal clock"] + USART_INT_CLK = 1, + #[doc = "2: SPI in slave operation"] + SPI_SLAVE = 2, + #[doc = "3: SPI in master operation"] + SPI_MASTER = 3, + #[doc = "4: I2C slave operation"] + I2C_SLAVE = 4, + #[doc = "5: I2C master operation"] + I2C_MASTER = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::USART_EXT_CLK), + 1 => Some(MODE_A::USART_INT_CLK), + 2 => Some(MODE_A::SPI_SLAVE), + 3 => Some(MODE_A::SPI_MASTER), + 4 => Some(MODE_A::I2C_SLAVE), + 5 => Some(MODE_A::I2C_MASTER), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_EXT_CLK`"] + #[inline(always)] + pub fn is_usart_ext_clk(&self) -> bool { + **self == MODE_A::USART_EXT_CLK + } + #[doc = "Checks if the value of the field is `USART_INT_CLK`"] + #[inline(always)] + pub fn is_usart_int_clk(&self) -> bool { + **self == MODE_A::USART_INT_CLK + } + #[doc = "Checks if the value of the field is `SPI_SLAVE`"] + #[inline(always)] + pub fn is_spi_slave(&self) -> bool { + **self == MODE_A::SPI_SLAVE + } + #[doc = "Checks if the value of the field is `SPI_MASTER`"] + #[inline(always)] + pub fn is_spi_master(&self) -> bool { + **self == MODE_A::SPI_MASTER + } + #[doc = "Checks if the value of the field is `I2C_SLAVE`"] + #[inline(always)] + pub fn is_i2c_slave(&self) -> bool { + **self == MODE_A::I2C_SLAVE + } + #[doc = "Checks if the value of the field is `I2C_MASTER`"] + #[inline(always)] + pub fn is_i2c_master(&self) -> bool { + **self == MODE_A::I2C_MASTER + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART with external clock"] + #[inline(always)] + pub fn usart_ext_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_EXT_CLK) + } + #[doc = "USART with internal clock"] + #[inline(always)] + pub fn usart_int_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_INT_CLK) + } + #[doc = "SPI in slave operation"] + #[inline(always)] + pub fn spi_slave(self) -> &'a mut W { + self.variant(MODE_A::SPI_SLAVE) + } + #[doc = "SPI in master operation"] + #[inline(always)] + pub fn spi_master(self) -> &'a mut W { + self.variant(MODE_A::SPI_MASTER) + } + #[doc = "I2C slave operation"] + #[inline(always)] + pub fn i2c_slave(self) -> &'a mut W { + self.variant(MODE_A::I2C_SLAVE) + } + #[doc = "I2C master operation"] + #[inline(always)] + pub fn i2c_master(self) -> &'a mut W { + self.variant(MODE_A::I2C_MASTER) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 2)) | ((value as u32 & 0x07) << 2); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `IBON` reader - Immediate Buffer Overflow Notification"] +pub struct IBON_R(crate::FieldReader); +impl IBON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IBON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IBON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IBON` writer - Immediate Buffer Overflow Notification"] +pub struct IBON_W<'a> { + w: &'a mut W, +} +impl<'a> IBON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Sample\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SAMPR_A { + #[doc = "0: 16x over-sampling using arithmetic baudrate generation"] + _16X_ARITHMETIC = 0, + #[doc = "1: 16x over-sampling using fractional baudrate generation"] + _16X_FRACTIONAL = 1, + #[doc = "2: 8x over-sampling using arithmetic baudrate generation"] + _8X_ARITHMETIC = 2, + #[doc = "3: 8x over-sampling using fractional baudrate generation"] + _8X_FRACTIONAL = 3, + #[doc = "4: 3x over-sampling using arithmetic baudrate generation"] + _3X_ARITHMETIC = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SAMPR_A) -> Self { + variant as _ + } +} +#[doc = "Field `SAMPR` reader - Sample"] +pub struct SAMPR_R(crate::FieldReader); +impl SAMPR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SAMPR_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SAMPR_A::_16X_ARITHMETIC), + 1 => Some(SAMPR_A::_16X_FRACTIONAL), + 2 => Some(SAMPR_A::_8X_ARITHMETIC), + 3 => Some(SAMPR_A::_8X_FRACTIONAL), + 4 => Some(SAMPR_A::_3X_ARITHMETIC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_16X_ARITHMETIC`"] + #[inline(always)] + pub fn is_16x_arithmetic(&self) -> bool { + **self == SAMPR_A::_16X_ARITHMETIC + } + #[doc = "Checks if the value of the field is `_16X_FRACTIONAL`"] + #[inline(always)] + pub fn is_16x_fractional(&self) -> bool { + **self == SAMPR_A::_16X_FRACTIONAL + } + #[doc = "Checks if the value of the field is `_8X_ARITHMETIC`"] + #[inline(always)] + pub fn is_8x_arithmetic(&self) -> bool { + **self == SAMPR_A::_8X_ARITHMETIC + } + #[doc = "Checks if the value of the field is `_8X_FRACTIONAL`"] + #[inline(always)] + pub fn is_8x_fractional(&self) -> bool { + **self == SAMPR_A::_8X_FRACTIONAL + } + #[doc = "Checks if the value of the field is `_3X_ARITHMETIC`"] + #[inline(always)] + pub fn is_3x_arithmetic(&self) -> bool { + **self == SAMPR_A::_3X_ARITHMETIC + } +} +impl core::ops::Deref for SAMPR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SAMPR` writer - Sample"] +pub struct SAMPR_W<'a> { + w: &'a mut W, +} +impl<'a> SAMPR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SAMPR_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "16x over-sampling using arithmetic baudrate generation"] + #[inline(always)] + pub fn _16x_arithmetic(self) -> &'a mut W { + self.variant(SAMPR_A::_16X_ARITHMETIC) + } + #[doc = "16x over-sampling using fractional baudrate generation"] + #[inline(always)] + pub fn _16x_fractional(self) -> &'a mut W { + self.variant(SAMPR_A::_16X_FRACTIONAL) + } + #[doc = "8x over-sampling using arithmetic baudrate generation"] + #[inline(always)] + pub fn _8x_arithmetic(self) -> &'a mut W { + self.variant(SAMPR_A::_8X_ARITHMETIC) + } + #[doc = "8x over-sampling using fractional baudrate generation"] + #[inline(always)] + pub fn _8x_fractional(self) -> &'a mut W { + self.variant(SAMPR_A::_8X_FRACTIONAL) + } + #[doc = "3x over-sampling using arithmetic baudrate generation"] + #[inline(always)] + pub fn _3x_arithmetic(self) -> &'a mut W { + self.variant(SAMPR_A::_3X_ARITHMETIC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 13)) | ((value as u32 & 0x07) << 13); + self.w + } +} +#[doc = "Transmit Data Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum TXPO_A { + #[doc = "0: SERCOM PAD\\[0\\] +is used for data transmission"] + PAD0 = 0, + #[doc = "1: SERCOM PAD\\[2\\] +is used for data transmission"] + PAD2 = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: TXPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `TXPO` reader - Transmit Data Pinout"] +pub struct TXPO_R(crate::FieldReader); +impl TXPO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TXPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(TXPO_A::PAD0), + 1 => Some(TXPO_A::PAD2), + _ => None, + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == TXPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == TXPO_A::PAD2 + } +} +impl core::ops::Deref for TXPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXPO` writer - Transmit Data Pinout"] +pub struct TXPO_W<'a> { + w: &'a mut W, +} +impl<'a> TXPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TXPO_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "SERCOM PAD\\[0\\] +is used for data transmission"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(TXPO_A::PAD0) + } + #[doc = "SERCOM PAD\\[2\\] +is used for data transmission"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(TXPO_A::PAD2) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Receive Data Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum RXPO_A { + #[doc = "0: SERCOM PAD\\[0\\] +is used for data reception"] + PAD0 = 0, + #[doc = "1: SERCOM PAD\\[1\\] +is used for data reception"] + PAD1 = 1, + #[doc = "2: SERCOM PAD\\[2\\] +is used for data reception"] + PAD2 = 2, + #[doc = "3: SERCOM PAD\\[3\\] +is used for data reception"] + PAD3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RXPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `RXPO` reader - Receive Data Pinout"] +pub struct RXPO_R(crate::FieldReader); +impl RXPO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RXPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RXPO_A { + match self.bits { + 0 => RXPO_A::PAD0, + 1 => RXPO_A::PAD1, + 2 => RXPO_A::PAD2, + 3 => RXPO_A::PAD3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == RXPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD1`"] + #[inline(always)] + pub fn is_pad1(&self) -> bool { + **self == RXPO_A::PAD1 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == RXPO_A::PAD2 + } + #[doc = "Checks if the value of the field is `PAD3`"] + #[inline(always)] + pub fn is_pad3(&self) -> bool { + **self == RXPO_A::PAD3 + } +} +impl core::ops::Deref for RXPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXPO` writer - Receive Data Pinout"] +pub struct RXPO_W<'a> { + w: &'a mut W, +} +impl<'a> RXPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RXPO_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "SERCOM PAD\\[0\\] +is used for data reception"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(RXPO_A::PAD0) + } + #[doc = "SERCOM PAD\\[1\\] +is used for data reception"] + #[inline(always)] + pub fn pad1(self) -> &'a mut W { + self.variant(RXPO_A::PAD1) + } + #[doc = "SERCOM PAD\\[2\\] +is used for data reception"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(RXPO_A::PAD2) + } + #[doc = "SERCOM PAD\\[3\\] +is used for data reception"] + #[inline(always)] + pub fn pad3(self) -> &'a mut W { + self.variant(RXPO_A::PAD3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 20)) | ((value as u32 & 0x03) << 20); + self.w + } +} +#[doc = "Field `SAMPA` reader - Sample Adjustment"] +pub struct SAMPA_R(crate::FieldReader); +impl SAMPA_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SAMPA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SAMPA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SAMPA` writer - Sample Adjustment"] +pub struct SAMPA_W<'a> { + w: &'a mut W, +} +impl<'a> SAMPA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 22)) | ((value as u32 & 0x03) << 22); + self.w + } +} +#[doc = "Frame Format\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FORM_A { + #[doc = "0: USART frame"] + USART_FRAME_NO_PARITY = 0, + #[doc = "1: USART frame with parity"] + USART_FRAME_WITH_PARITY = 1, + #[doc = "2: LIN Master - Break and sync generation"] + USART_FRAME_LIN_MASTER_MODE = 2, + #[doc = "4: Auto-baud - break detection and auto-baud"] + USART_FRAME_AUTO_BAUD_NO_PARITY = 4, + #[doc = "5: Auto-baud - break detection and auto-baud with parity"] + USART_FRAME_AUTO_BAUD_WITH_PARITY = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FORM_A) -> Self { + variant as _ + } +} +#[doc = "Field `FORM` reader - Frame Format"] +pub struct FORM_R(crate::FieldReader); +impl FORM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FORM_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(FORM_A::USART_FRAME_NO_PARITY), + 1 => Some(FORM_A::USART_FRAME_WITH_PARITY), + 2 => Some(FORM_A::USART_FRAME_LIN_MASTER_MODE), + 4 => Some(FORM_A::USART_FRAME_AUTO_BAUD_NO_PARITY), + 5 => Some(FORM_A::USART_FRAME_AUTO_BAUD_WITH_PARITY), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_FRAME_NO_PARITY`"] + #[inline(always)] + pub fn is_usart_frame_no_parity(&self) -> bool { + **self == FORM_A::USART_FRAME_NO_PARITY + } + #[doc = "Checks if the value of the field is `USART_FRAME_WITH_PARITY`"] + #[inline(always)] + pub fn is_usart_frame_with_parity(&self) -> bool { + **self == FORM_A::USART_FRAME_WITH_PARITY + } + #[doc = "Checks if the value of the field is `USART_FRAME_LIN_MASTER_MODE`"] + #[inline(always)] + pub fn is_usart_frame_lin_master_mode(&self) -> bool { + **self == FORM_A::USART_FRAME_LIN_MASTER_MODE + } + #[doc = "Checks if the value of the field is `USART_FRAME_AUTO_BAUD_NO_PARITY`"] + #[inline(always)] + pub fn is_usart_frame_auto_baud_no_parity(&self) -> bool { + **self == FORM_A::USART_FRAME_AUTO_BAUD_NO_PARITY + } + #[doc = "Checks if the value of the field is `USART_FRAME_AUTO_BAUD_WITH_PARITY`"] + #[inline(always)] + pub fn is_usart_frame_auto_baud_with_parity(&self) -> bool { + **self == FORM_A::USART_FRAME_AUTO_BAUD_WITH_PARITY + } +} +impl core::ops::Deref for FORM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FORM` writer - Frame Format"] +pub struct FORM_W<'a> { + w: &'a mut W, +} +impl<'a> FORM_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FORM_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART frame"] + #[inline(always)] + pub fn usart_frame_no_parity(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_NO_PARITY) + } + #[doc = "USART frame with parity"] + #[inline(always)] + pub fn usart_frame_with_parity(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_WITH_PARITY) + } + #[doc = "LIN Master - Break and sync generation"] + #[inline(always)] + pub fn usart_frame_lin_master_mode(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_LIN_MASTER_MODE) + } + #[doc = "Auto-baud - break detection and auto-baud"] + #[inline(always)] + pub fn usart_frame_auto_baud_no_parity(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_AUTO_BAUD_NO_PARITY) + } + #[doc = "Auto-baud - break detection and auto-baud with parity"] + #[inline(always)] + pub fn usart_frame_auto_baud_with_parity(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_AUTO_BAUD_WITH_PARITY) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Communication Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CMODE_A { + #[doc = "0: Asynchronous Communication"] + ASYNC = 0, + #[doc = "1: Synchronous Communication"] + SYNC = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CMODE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CMODE` reader - Communication Mode"] +pub struct CMODE_R(crate::FieldReader); +impl CMODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CMODE_A { + match self.bits { + false => CMODE_A::ASYNC, + true => CMODE_A::SYNC, + } + } + #[doc = "Checks if the value of the field is `ASYNC`"] + #[inline(always)] + pub fn is_async(&self) -> bool { + **self == CMODE_A::ASYNC + } + #[doc = "Checks if the value of the field is `SYNC`"] + #[inline(always)] + pub fn is_sync(&self) -> bool { + **self == CMODE_A::SYNC + } +} +impl core::ops::Deref for CMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMODE` writer - Communication Mode"] +pub struct CMODE_W<'a> { + w: &'a mut W, +} +impl<'a> CMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMODE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Asynchronous Communication"] + #[inline(always)] + pub fn async_(self) -> &'a mut W { + self.variant(CMODE_A::ASYNC) + } + #[doc = "Synchronous Communication"] + #[inline(always)] + pub fn sync(self) -> &'a mut W { + self.variant(CMODE_A::SYNC) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Clock Polarity\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CPOL_A { + #[doc = "0: TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge"] + IDLE_LOW = 0, + #[doc = "1: TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge"] + IDLE_HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CPOL_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CPOL` reader - Clock Polarity"] +pub struct CPOL_R(crate::FieldReader); +impl CPOL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPOL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CPOL_A { + match self.bits { + false => CPOL_A::IDLE_LOW, + true => CPOL_A::IDLE_HIGH, + } + } + #[doc = "Checks if the value of the field is `IDLE_LOW`"] + #[inline(always)] + pub fn is_idle_low(&self) -> bool { + **self == CPOL_A::IDLE_LOW + } + #[doc = "Checks if the value of the field is `IDLE_HIGH`"] + #[inline(always)] + pub fn is_idle_high(&self) -> bool { + **self == CPOL_A::IDLE_HIGH + } +} +impl core::ops::Deref for CPOL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPOL` writer - Clock Polarity"] +pub struct CPOL_W<'a> { + w: &'a mut W, +} +impl<'a> CPOL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CPOL_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge"] + #[inline(always)] + pub fn idle_low(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_LOW) + } + #[doc = "TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge"] + #[inline(always)] + pub fn idle_high(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_HIGH) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29); + self.w + } +} +#[doc = "Data Order\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum DORD_A { + #[doc = "0: MSB is transmitted first"] + MSB = 0, + #[doc = "1: LSB is transmitted first"] + LSB = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DORD_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DORD` reader - Data Order"] +pub struct DORD_R(crate::FieldReader); +impl DORD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DORD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DORD_A { + match self.bits { + false => DORD_A::MSB, + true => DORD_A::LSB, + } + } + #[doc = "Checks if the value of the field is `MSB`"] + #[inline(always)] + pub fn is_msb(&self) -> bool { + **self == DORD_A::MSB + } + #[doc = "Checks if the value of the field is `LSB`"] + #[inline(always)] + pub fn is_lsb(&self) -> bool { + **self == DORD_A::LSB + } +} +impl core::ops::Deref for DORD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DORD` writer - Data Order"] +pub struct DORD_W<'a> { + w: &'a mut W, +} +impl<'a> DORD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DORD_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "MSB is transmitted first"] + #[inline(always)] + pub fn msb(self) -> &'a mut W { + self.variant(DORD_A::MSB) + } + #[doc = "LSB is transmitted first"] + #[inline(always)] + pub fn lsb(self) -> &'a mut W { + self.variant(DORD_A::LSB) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x07) as u8) + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&self) -> IBON_R { + IBON_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bits 13:15 - Sample"] + #[inline(always)] + pub fn sampr(&self) -> SAMPR_R { + SAMPR_R::new(((self.bits >> 13) & 0x07) as u8) + } + #[doc = "Bits 16:17 - Transmit Data Pinout"] + #[inline(always)] + pub fn txpo(&self) -> TXPO_R { + TXPO_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bits 20:21 - Receive Data Pinout"] + #[inline(always)] + pub fn rxpo(&self) -> RXPO_R { + RXPO_R::new(((self.bits >> 20) & 0x03) as u8) + } + #[doc = "Bits 22:23 - Sample Adjustment"] + #[inline(always)] + pub fn sampa(&self) -> SAMPA_R { + SAMPA_R::new(((self.bits >> 22) & 0x03) as u8) + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&self) -> FORM_R { + FORM_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 28 - Communication Mode"] + #[inline(always)] + pub fn cmode(&self) -> CMODE_R { + CMODE_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&self) -> CPOL_R { + CPOL_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&self) -> DORD_R { + DORD_R::new(((self.bits >> 30) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&mut self) -> IBON_W { + IBON_W { w: self } + } + #[doc = "Bits 13:15 - Sample"] + #[inline(always)] + pub fn sampr(&mut self) -> SAMPR_W { + SAMPR_W { w: self } + } + #[doc = "Bits 16:17 - Transmit Data Pinout"] + #[inline(always)] + pub fn txpo(&mut self) -> TXPO_W { + TXPO_W { w: self } + } + #[doc = "Bits 20:21 - Receive Data Pinout"] + #[inline(always)] + pub fn rxpo(&mut self) -> RXPO_W { + RXPO_W { w: self } + } + #[doc = "Bits 22:23 - Sample Adjustment"] + #[inline(always)] + pub fn sampa(&mut self) -> SAMPA_W { + SAMPA_W { w: self } + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&mut self) -> FORM_W { + FORM_W { w: self } + } + #[doc = "Bit 28 - Communication Mode"] + #[inline(always)] + pub fn cmode(&mut self) -> CMODE_W { + CMODE_W { w: self } + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&mut self) -> CPOL_W { + CPOL_W { w: self } + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&mut self) -> DORD_W { + DORD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sercom0/usart_ext/ctrlb.rs b/pac/atsamc21j/src/sercom0/usart_ext/ctrlb.rs new file mode 100644 index 000000000000..37567555e842 --- /dev/null +++ b/pac/atsamc21j/src/sercom0/usart_ext/ctrlb.rs @@ -0,0 +1,651 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Character Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CHSIZE_A { + #[doc = "0: 8 Bits"] + _8_BIT = 0, + #[doc = "1: 9 Bits"] + _9_BIT = 1, + #[doc = "5: 5 Bits"] + _5_BIT = 5, + #[doc = "6: 6 Bits"] + _6_BIT = 6, + #[doc = "7: 7 Bits"] + _7_BIT = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CHSIZE_A) -> Self { + variant as _ + } +} +#[doc = "Field `CHSIZE` reader - Character Size"] +pub struct CHSIZE_R(crate::FieldReader); +impl CHSIZE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CHSIZE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CHSIZE_A::_8_BIT), + 1 => Some(CHSIZE_A::_9_BIT), + 5 => Some(CHSIZE_A::_5_BIT), + 6 => Some(CHSIZE_A::_6_BIT), + 7 => Some(CHSIZE_A::_7_BIT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_8_BIT`"] + #[inline(always)] + pub fn is_8_bit(&self) -> bool { + **self == CHSIZE_A::_8_BIT + } + #[doc = "Checks if the value of the field is `_9_BIT`"] + #[inline(always)] + pub fn is_9_bit(&self) -> bool { + **self == CHSIZE_A::_9_BIT + } + #[doc = "Checks if the value of the field is `_5_BIT`"] + #[inline(always)] + pub fn is_5_bit(&self) -> bool { + **self == CHSIZE_A::_5_BIT + } + #[doc = "Checks if the value of the field is `_6_BIT`"] + #[inline(always)] + pub fn is_6_bit(&self) -> bool { + **self == CHSIZE_A::_6_BIT + } + #[doc = "Checks if the value of the field is `_7_BIT`"] + #[inline(always)] + pub fn is_7_bit(&self) -> bool { + **self == CHSIZE_A::_7_BIT + } +} +impl core::ops::Deref for CHSIZE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHSIZE` writer - Character Size"] +pub struct CHSIZE_W<'a> { + w: &'a mut W, +} +impl<'a> CHSIZE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CHSIZE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8 Bits"] + #[inline(always)] + pub fn _8_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_8_BIT) + } + #[doc = "9 Bits"] + #[inline(always)] + pub fn _9_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_9_BIT) + } + #[doc = "5 Bits"] + #[inline(always)] + pub fn _5_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_5_BIT) + } + #[doc = "6 Bits"] + #[inline(always)] + pub fn _6_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_6_BIT) + } + #[doc = "7 Bits"] + #[inline(always)] + pub fn _7_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_7_BIT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Stop Bit Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SBMODE_A { + #[doc = "0: One Stop Bit"] + _1_BIT = 0, + #[doc = "1: Two Stop Bits"] + _2_BIT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SBMODE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SBMODE` reader - Stop Bit Mode"] +pub struct SBMODE_R(crate::FieldReader); +impl SBMODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SBMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SBMODE_A { + match self.bits { + false => SBMODE_A::_1_BIT, + true => SBMODE_A::_2_BIT, + } + } + #[doc = "Checks if the value of the field is `_1_BIT`"] + #[inline(always)] + pub fn is_1_bit(&self) -> bool { + **self == SBMODE_A::_1_BIT + } + #[doc = "Checks if the value of the field is `_2_BIT`"] + #[inline(always)] + pub fn is_2_bit(&self) -> bool { + **self == SBMODE_A::_2_BIT + } +} +impl core::ops::Deref for SBMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SBMODE` writer - Stop Bit Mode"] +pub struct SBMODE_W<'a> { + w: &'a mut W, +} +impl<'a> SBMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SBMODE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "One Stop Bit"] + #[inline(always)] + pub fn _1_bit(self) -> &'a mut W { + self.variant(SBMODE_A::_1_BIT) + } + #[doc = "Two Stop Bits"] + #[inline(always)] + pub fn _2_bit(self) -> &'a mut W { + self.variant(SBMODE_A::_2_BIT) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `COLDEN` reader - Collision Detection Enable"] +pub struct COLDEN_R(crate::FieldReader); +impl COLDEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COLDEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COLDEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COLDEN` writer - Collision Detection Enable"] +pub struct COLDEN_W<'a> { + w: &'a mut W, +} +impl<'a> COLDEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `SFDE` reader - Start of Frame Detection Enable"] +pub struct SFDE_R(crate::FieldReader); +impl SFDE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SFDE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SFDE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SFDE` writer - Start of Frame Detection Enable"] +pub struct SFDE_W<'a> { + w: &'a mut W, +} +impl<'a> SFDE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `ENC` reader - Encoding Format"] +pub struct ENC_R(crate::FieldReader); +impl ENC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENC` writer - Encoding Format"] +pub struct ENC_W<'a> { + w: &'a mut W, +} +impl<'a> ENC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Parity Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PMODE_A { + #[doc = "0: Even Parity"] + EVEN = 0, + #[doc = "1: Odd Parity"] + ODD = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PMODE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PMODE` reader - Parity Mode"] +pub struct PMODE_R(crate::FieldReader); +impl PMODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PMODE_A { + match self.bits { + false => PMODE_A::EVEN, + true => PMODE_A::ODD, + } + } + #[doc = "Checks if the value of the field is `EVEN`"] + #[inline(always)] + pub fn is_even(&self) -> bool { + **self == PMODE_A::EVEN + } + #[doc = "Checks if the value of the field is `ODD`"] + #[inline(always)] + pub fn is_odd(&self) -> bool { + **self == PMODE_A::ODD + } +} +impl core::ops::Deref for PMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PMODE` writer - Parity Mode"] +pub struct PMODE_W<'a> { + w: &'a mut W, +} +impl<'a> PMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PMODE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Even Parity"] + #[inline(always)] + pub fn even(self) -> &'a mut W { + self.variant(PMODE_A::EVEN) + } + #[doc = "Odd Parity"] + #[inline(always)] + pub fn odd(self) -> &'a mut W { + self.variant(PMODE_A::ODD) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `TXEN` reader - Transmitter Enable"] +pub struct TXEN_R(crate::FieldReader); +impl TXEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXEN` writer - Transmitter Enable"] +pub struct TXEN_W<'a> { + w: &'a mut W, +} +impl<'a> TXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `RXEN` reader - Receiver Enable"] +pub struct RXEN_R(crate::FieldReader); +impl RXEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXEN` writer - Receiver Enable"] +pub struct RXEN_W<'a> { + w: &'a mut W, +} +impl<'a> RXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `LINCMD` reader - LIN Command"] +pub struct LINCMD_R(crate::FieldReader); +impl LINCMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LINCMD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LINCMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LINCMD` writer - LIN Command"] +pub struct LINCMD_W<'a> { + w: &'a mut W, +} +impl<'a> LINCMD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 24)) | ((value as u32 & 0x03) << 24); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&self) -> CHSIZE_R { + CHSIZE_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 6 - Stop Bit Mode"] + #[inline(always)] + pub fn sbmode(&self) -> SBMODE_R { + SBMODE_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 8 - Collision Detection Enable"] + #[inline(always)] + pub fn colden(&self) -> COLDEN_R { + COLDEN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Start of Frame Detection Enable"] + #[inline(always)] + pub fn sfde(&self) -> SFDE_R { + SFDE_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Encoding Format"] + #[inline(always)] + pub fn enc(&self) -> ENC_R { + ENC_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 13 - Parity Mode"] + #[inline(always)] + pub fn pmode(&self) -> PMODE_R { + PMODE_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 16 - Transmitter Enable"] + #[inline(always)] + pub fn txen(&self) -> TXEN_R { + TXEN_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&self) -> RXEN_R { + RXEN_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bits 24:25 - LIN Command"] + #[inline(always)] + pub fn lincmd(&self) -> LINCMD_R { + LINCMD_R::new(((self.bits >> 24) & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&mut self) -> CHSIZE_W { + CHSIZE_W { w: self } + } + #[doc = "Bit 6 - Stop Bit Mode"] + #[inline(always)] + pub fn sbmode(&mut self) -> SBMODE_W { + SBMODE_W { w: self } + } + #[doc = "Bit 8 - Collision Detection Enable"] + #[inline(always)] + pub fn colden(&mut self) -> COLDEN_W { + COLDEN_W { w: self } + } + #[doc = "Bit 9 - Start of Frame Detection Enable"] + #[inline(always)] + pub fn sfde(&mut self) -> SFDE_W { + SFDE_W { w: self } + } + #[doc = "Bit 10 - Encoding Format"] + #[inline(always)] + pub fn enc(&mut self) -> ENC_W { + ENC_W { w: self } + } + #[doc = "Bit 13 - Parity Mode"] + #[inline(always)] + pub fn pmode(&mut self) -> PMODE_W { + PMODE_W { w: self } + } + #[doc = "Bit 16 - Transmitter Enable"] + #[inline(always)] + pub fn txen(&mut self) -> TXEN_W { + TXEN_W { w: self } + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&mut self) -> RXEN_W { + RXEN_W { w: self } + } + #[doc = "Bits 24:25 - LIN Command"] + #[inline(always)] + pub fn lincmd(&mut self) -> LINCMD_W { + LINCMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sercom0/usart_ext/ctrlc.rs b/pac/atsamc21j/src/sercom0/usart_ext/ctrlc.rs new file mode 100644 index 000000000000..5840d5c3bd06 --- /dev/null +++ b/pac/atsamc21j/src/sercom0/usart_ext/ctrlc.rs @@ -0,0 +1,177 @@ +#[doc = "Register `CTRLC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `GTIME` reader - RS485 Guard Time"] +pub struct GTIME_R(crate::FieldReader); +impl GTIME_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + GTIME_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GTIME_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GTIME` writer - RS485 Guard Time"] +pub struct GTIME_W<'a> { + w: &'a mut W, +} +impl<'a> GTIME_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Field `BRKLEN` reader - LIN Master Break Length"] +pub struct BRKLEN_R(crate::FieldReader); +impl BRKLEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BRKLEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BRKLEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BRKLEN` writer - LIN Master Break Length"] +pub struct BRKLEN_W<'a> { + w: &'a mut W, +} +impl<'a> BRKLEN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 8)) | ((value as u32 & 0x03) << 8); + self.w + } +} +#[doc = "Field `HDRDLY` reader - LIN Master Header Delay"] +pub struct HDRDLY_R(crate::FieldReader); +impl HDRDLY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + HDRDLY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HDRDLY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HDRDLY` writer - LIN Master Header Delay"] +pub struct HDRDLY_W<'a> { + w: &'a mut W, +} +impl<'a> HDRDLY_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 10)) | ((value as u32 & 0x03) << 10); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - RS485 Guard Time"] + #[inline(always)] + pub fn gtime(&self) -> GTIME_R { + GTIME_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bits 8:9 - LIN Master Break Length"] + #[inline(always)] + pub fn brklen(&self) -> BRKLEN_R { + BRKLEN_R::new(((self.bits >> 8) & 0x03) as u8) + } + #[doc = "Bits 10:11 - LIN Master Header Delay"] + #[inline(always)] + pub fn hdrdly(&self) -> HDRDLY_R { + HDRDLY_R::new(((self.bits >> 10) & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - RS485 Guard Time"] + #[inline(always)] + pub fn gtime(&mut self) -> GTIME_W { + GTIME_W { w: self } + } + #[doc = "Bits 8:9 - LIN Master Break Length"] + #[inline(always)] + pub fn brklen(&mut self) -> BRKLEN_W { + BRKLEN_W { w: self } + } + #[doc = "Bits 10:11 - LIN Master Header Delay"] + #[inline(always)] + pub fn hdrdly(&mut self) -> HDRDLY_W { + HDRDLY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Control C\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlc](index.html) module"] +pub struct CTRLC_SPEC; +impl crate::RegisterSpec for CTRLC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlc::R](R) reader structure"] +impl crate::Readable for CTRLC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlc::W](W) writer structure"] +impl crate::Writable for CTRLC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLC to value 0"] +impl crate::Resettable for CTRLC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sercom0/usart_ext/data.rs b/pac/atsamc21j/src/sercom0/usart_ext/data.rs new file mode 100644 index 000000000000..a54152c9571a --- /dev/null +++ b/pac/atsamc21j/src/sercom0/usart_ext/data.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data Value"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data Value"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01ff) | (value as u16 & 0x01ff); + self.w + } +} +impl R { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new((self.bits & 0x01ff) as u16) + } +} +impl W { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sercom0/usart_ext/dbgctrl.rs b/pac/atsamc21j/src/sercom0/usart_ext/dbgctrl.rs new file mode 100644 index 000000000000..6c844f3fe40d --- /dev/null +++ b/pac/atsamc21j/src/sercom0/usart_ext/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGSTOP` reader - Debug Mode"] +pub struct DBGSTOP_R(crate::FieldReader); +impl DBGSTOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGSTOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGSTOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGSTOP` writer - Debug Mode"] +pub struct DBGSTOP_W<'a> { + w: &'a mut W, +} +impl<'a> DBGSTOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&self) -> DBGSTOP_R { + DBGSTOP_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&mut self) -> DBGSTOP_W { + DBGSTOP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sercom0/usart_ext/intenclr.rs b/pac/atsamc21j/src/sercom0/usart_ext/intenclr.rs new file mode 100644 index 000000000000..a815553ce666 --- /dev/null +++ b/pac/atsamc21j/src/sercom0/usart_ext/intenclr.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Disable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Disable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Disable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Disable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Disable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Disable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RXS` reader - Receive Start Interrupt Disable"] +pub struct RXS_R(crate::FieldReader); +impl RXS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXS` writer - Receive Start Interrupt Disable"] +pub struct RXS_W<'a> { + w: &'a mut W, +} +impl<'a> RXS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CTSIC` reader - Clear To Send Input Change Interrupt Disable"] +pub struct CTSIC_R(crate::FieldReader); +impl CTSIC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTSIC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTSIC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTSIC` writer - Clear To Send Input Change Interrupt Disable"] +pub struct CTSIC_W<'a> { + w: &'a mut W, +} +impl<'a> CTSIC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RXBRK` reader - Break Received Interrupt Disable"] +pub struct RXBRK_R(crate::FieldReader); +impl RXBRK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXBRK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXBRK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXBRK` writer - Break Received Interrupt Disable"] +pub struct RXBRK_W<'a> { + w: &'a mut W, +} +impl<'a> RXBRK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Disable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Disable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Receive Start Interrupt Disable"] + #[inline(always)] + pub fn rxs(&self) -> RXS_R { + RXS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Disable"] + #[inline(always)] + pub fn ctsic(&self) -> CTSIC_R { + CTSIC_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Break Received Interrupt Disable"] + #[inline(always)] + pub fn rxbrk(&self) -> RXBRK_R { + RXBRK_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Receive Start Interrupt Disable"] + #[inline(always)] + pub fn rxs(&mut self) -> RXS_W { + RXS_W { w: self } + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Disable"] + #[inline(always)] + pub fn ctsic(&mut self) -> CTSIC_W { + CTSIC_W { w: self } + } + #[doc = "Bit 5 - Break Received Interrupt Disable"] + #[inline(always)] + pub fn rxbrk(&mut self) -> RXBRK_W { + RXBRK_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sercom0/usart_ext/intenset.rs b/pac/atsamc21j/src/sercom0/usart_ext/intenset.rs new file mode 100644 index 000000000000..e800681cf423 --- /dev/null +++ b/pac/atsamc21j/src/sercom0/usart_ext/intenset.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Enable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Enable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Enable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Enable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Enable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Enable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RXS` reader - Receive Start Interrupt Enable"] +pub struct RXS_R(crate::FieldReader); +impl RXS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXS` writer - Receive Start Interrupt Enable"] +pub struct RXS_W<'a> { + w: &'a mut W, +} +impl<'a> RXS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CTSIC` reader - Clear To Send Input Change Interrupt Enable"] +pub struct CTSIC_R(crate::FieldReader); +impl CTSIC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTSIC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTSIC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTSIC` writer - Clear To Send Input Change Interrupt Enable"] +pub struct CTSIC_W<'a> { + w: &'a mut W, +} +impl<'a> CTSIC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RXBRK` reader - Break Received Interrupt Enable"] +pub struct RXBRK_R(crate::FieldReader); +impl RXBRK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXBRK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXBRK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXBRK` writer - Break Received Interrupt Enable"] +pub struct RXBRK_W<'a> { + w: &'a mut W, +} +impl<'a> RXBRK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Receive Start Interrupt Enable"] + #[inline(always)] + pub fn rxs(&self) -> RXS_R { + RXS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Enable"] + #[inline(always)] + pub fn ctsic(&self) -> CTSIC_R { + CTSIC_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Break Received Interrupt Enable"] + #[inline(always)] + pub fn rxbrk(&self) -> RXBRK_R { + RXBRK_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Receive Start Interrupt Enable"] + #[inline(always)] + pub fn rxs(&mut self) -> RXS_W { + RXS_W { w: self } + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Enable"] + #[inline(always)] + pub fn ctsic(&mut self) -> CTSIC_W { + CTSIC_W { w: self } + } + #[doc = "Bit 5 - Break Received Interrupt Enable"] + #[inline(always)] + pub fn rxbrk(&mut self) -> RXBRK_W { + RXBRK_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sercom0/usart_ext/intflag.rs b/pac/atsamc21j/src/sercom0/usart_ext/intflag.rs new file mode 100644 index 000000000000..4b0be279a9ae --- /dev/null +++ b/pac/atsamc21j/src/sercom0/usart_ext/intflag.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RXS` reader - Receive Start Interrupt"] +pub struct RXS_R(crate::FieldReader); +impl RXS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXS` writer - Receive Start Interrupt"] +pub struct RXS_W<'a> { + w: &'a mut W, +} +impl<'a> RXS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CTSIC` reader - Clear To Send Input Change Interrupt"] +pub struct CTSIC_R(crate::FieldReader); +impl CTSIC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTSIC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTSIC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTSIC` writer - Clear To Send Input Change Interrupt"] +pub struct CTSIC_W<'a> { + w: &'a mut W, +} +impl<'a> CTSIC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RXBRK` reader - Break Received Interrupt"] +pub struct RXBRK_R(crate::FieldReader); +impl RXBRK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXBRK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXBRK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXBRK` writer - Break Received Interrupt"] +pub struct RXBRK_W<'a> { + w: &'a mut W, +} +impl<'a> RXBRK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Receive Start Interrupt"] + #[inline(always)] + pub fn rxs(&self) -> RXS_R { + RXS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt"] + #[inline(always)] + pub fn ctsic(&self) -> CTSIC_R { + CTSIC_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Break Received Interrupt"] + #[inline(always)] + pub fn rxbrk(&self) -> RXBRK_R { + RXBRK_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Receive Start Interrupt"] + #[inline(always)] + pub fn rxs(&mut self) -> RXS_W { + RXS_W { w: self } + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt"] + #[inline(always)] + pub fn ctsic(&mut self) -> CTSIC_W { + CTSIC_W { w: self } + } + #[doc = "Bit 5 - Break Received Interrupt"] + #[inline(always)] + pub fn rxbrk(&mut self) -> RXBRK_W { + RXBRK_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sercom0/usart_ext/rxpl.rs b/pac/atsamc21j/src/sercom0/usart_ext/rxpl.rs new file mode 100644 index 000000000000..174464dc16b5 --- /dev/null +++ b/pac/atsamc21j/src/sercom0/usart_ext/rxpl.rs @@ -0,0 +1,103 @@ +#[doc = "Register `RXPL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RXPL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RXPL` reader - Receive Pulse Length"] +pub struct RXPL_R(crate::FieldReader); +impl RXPL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RXPL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXPL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXPL` writer - Receive Pulse Length"] +pub struct RXPL_W<'a> { + w: &'a mut W, +} +impl<'a> RXPL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Receive Pulse Length"] + #[inline(always)] + pub fn rxpl(&self) -> RXPL_R { + RXPL_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Receive Pulse Length"] + #[inline(always)] + pub fn rxpl(&mut self) -> RXPL_W { + RXPL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Receive Pulse Length\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxpl](index.html) module"] +pub struct RXPL_SPEC; +impl crate::RegisterSpec for RXPL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [rxpl::R](R) reader structure"] +impl crate::Readable for RXPL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rxpl::W](W) writer structure"] +impl crate::Writable for RXPL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RXPL to value 0"] +impl crate::Resettable for RXPL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sercom0/usart_ext/status.rs b/pac/atsamc21j/src/sercom0/usart_ext/status.rs new file mode 100644 index 000000000000..a0c50c1bc2cf --- /dev/null +++ b/pac/atsamc21j/src/sercom0/usart_ext/status.rs @@ -0,0 +1,395 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PERR` reader - Parity Error"] +pub struct PERR_R(crate::FieldReader); +impl PERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERR` writer - Parity Error"] +pub struct PERR_W<'a> { + w: &'a mut W, +} +impl<'a> PERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `FERR` reader - Frame Error"] +pub struct FERR_R(crate::FieldReader); +impl FERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FERR` writer - Frame Error"] +pub struct FERR_W<'a> { + w: &'a mut W, +} +impl<'a> FERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `BUFOVF` reader - Buffer Overflow"] +pub struct BUFOVF_R(crate::FieldReader); +impl BUFOVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUFOVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUFOVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUFOVF` writer - Buffer Overflow"] +pub struct BUFOVF_W<'a> { + w: &'a mut W, +} +impl<'a> BUFOVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CTS` reader - Clear To Send"] +pub struct CTS_R(crate::FieldReader); +impl CTS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTS` writer - Clear To Send"] +pub struct CTS_W<'a> { + w: &'a mut W, +} +impl<'a> CTS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ISF` reader - Inconsistent Sync Field"] +pub struct ISF_R(crate::FieldReader); +impl ISF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ISF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ISF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ISF` writer - Inconsistent Sync Field"] +pub struct ISF_W<'a> { + w: &'a mut W, +} +impl<'a> ISF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `COLL` reader - Collision Detected"] +pub struct COLL_R(crate::FieldReader); +impl COLL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COLL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COLL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COLL` writer - Collision Detected"] +pub struct COLL_W<'a> { + w: &'a mut W, +} +impl<'a> COLL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `TXE` reader - Transmitter Empty"] +pub struct TXE_R(crate::FieldReader); +impl TXE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXE` writer - Transmitter Empty"] +pub struct TXE_W<'a> { + w: &'a mut W, +} +impl<'a> TXE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - Parity Error"] + #[inline(always)] + pub fn perr(&self) -> PERR_R { + PERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Frame Error"] + #[inline(always)] + pub fn ferr(&self) -> FERR_R { + FERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&self) -> BUFOVF_R { + BUFOVF_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Clear To Send"] + #[inline(always)] + pub fn cts(&self) -> CTS_R { + CTS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Inconsistent Sync Field"] + #[inline(always)] + pub fn isf(&self) -> ISF_R { + ISF_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Collision Detected"] + #[inline(always)] + pub fn coll(&self) -> COLL_R { + COLL_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Transmitter Empty"] + #[inline(always)] + pub fn txe(&self) -> TXE_R { + TXE_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Parity Error"] + #[inline(always)] + pub fn perr(&mut self) -> PERR_W { + PERR_W { w: self } + } + #[doc = "Bit 1 - Frame Error"] + #[inline(always)] + pub fn ferr(&mut self) -> FERR_W { + FERR_W { w: self } + } + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&mut self) -> BUFOVF_W { + BUFOVF_W { w: self } + } + #[doc = "Bit 3 - Clear To Send"] + #[inline(always)] + pub fn cts(&mut self) -> CTS_W { + CTS_W { w: self } + } + #[doc = "Bit 4 - Inconsistent Sync Field"] + #[inline(always)] + pub fn isf(&mut self) -> ISF_W { + ISF_W { w: self } + } + #[doc = "Bit 5 - Collision Detected"] + #[inline(always)] + pub fn coll(&mut self) -> COLL_W { + COLL_W { w: self } + } + #[doc = "Bit 6 - Transmitter Empty"] + #[inline(always)] + pub fn txe(&mut self) -> TXE_W { + TXE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sercom0/usart_ext/syncbusy.rs b/pac/atsamc21j/src/sercom0/usart_ext/syncbusy.rs new file mode 100644 index 000000000000..7c3b817bbb04 --- /dev/null +++ b/pac/atsamc21j/src/sercom0/usart_ext/syncbusy.rs @@ -0,0 +1,93 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - SERCOM Enable Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLB` reader - CTRLB Synchronization Busy"] +pub struct CTRLB_R(crate::FieldReader); +impl CTRLB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM Enable Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - CTRLB Synchronization Busy"] + #[inline(always)] + pub fn ctrlb(&self) -> CTRLB_R { + CTRLB_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +#[doc = "USART_EXT Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sercom0/usart_int.rs b/pac/atsamc21j/src/sercom0/usart_int.rs new file mode 100644 index 000000000000..157c8c4b4fdc --- /dev/null +++ b/pac/atsamc21j/src/sercom0/usart_int.rs @@ -0,0 +1,60 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "USART_INT Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "USART_INT Control B"] +pub mod ctrlb; +#[doc = "CTRLC register accessor: an alias for `Reg`"] +pub type CTRLC = crate::Reg; +#[doc = "USART_INT Control C"] +pub mod ctrlc; +#[doc = "BAUD register accessor: an alias for `Reg`"] +pub type BAUD = crate::Reg; +#[doc = "USART_INT Baud Rate"] +pub mod baud; +#[doc = "BAUD_FRAC_MODE register accessor: an alias for `Reg`"] +pub type BAUD_FRAC_MODE = crate::Reg; +#[doc = "USART_INT Baud Rate"] +pub mod baud_frac_mode; +#[doc = "BAUD_FRACFP_MODE register accessor: an alias for `Reg`"] +pub type BAUD_FRACFP_MODE = crate::Reg; +#[doc = "USART_INT Baud Rate"] +pub mod baud_fracfp_mode; +#[doc = "BAUD_USARTFP_MODE register accessor: an alias for `Reg`"] +pub type BAUD_USARTFP_MODE = crate::Reg; +#[doc = "USART_INT Baud Rate"] +pub mod baud_usartfp_mode; +#[doc = "RXPL register accessor: an alias for `Reg`"] +pub type RXPL = crate::Reg; +#[doc = "USART_INT Receive Pulse Length"] +pub mod rxpl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "USART_INT Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "USART_INT Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "USART_INT Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "USART_INT Status"] +pub mod status; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "USART_INT Synchronization Busy"] +pub mod syncbusy; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "USART_INT Data"] +pub mod data; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "USART_INT Debug Control"] +pub mod dbgctrl; diff --git a/pac/atsamc21j/src/sercom0/usart_int/baud.rs b/pac/atsamc21j/src/sercom0/usart_int/baud.rs new file mode 100644 index 000000000000..a82df20712b3 --- /dev/null +++ b/pac/atsamc21j/src/sercom0/usart_int/baud.rs @@ -0,0 +1,103 @@ +#[doc = "Register `BAUD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud](index.html) module"] +pub struct BAUD_SPEC; +impl crate::RegisterSpec for BAUD_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud::R](R) reader structure"] +impl crate::Readable for BAUD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud::W](W) writer structure"] +impl crate::Writable for BAUD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD to value 0"] +impl crate::Resettable for BAUD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sercom0/usart_int/baud_frac_mode.rs b/pac/atsamc21j/src/sercom0/usart_int/baud_frac_mode.rs new file mode 100644 index 000000000000..b9c7fa4c4b2a --- /dev/null +++ b/pac/atsamc21j/src/sercom0/usart_int/baud_frac_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `BAUD_FRAC_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD_FRAC_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1fff) | (value as u16 & 0x1fff); + self.w + } +} +#[doc = "Field `FP` reader - Fractional Part"] +pub struct FP_R(crate::FieldReader); +impl FP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FP` writer - Fractional Part"] +pub struct FP_W<'a> { + w: &'a mut W, +} +impl<'a> FP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 13)) | ((value as u16 & 0x07) << 13); + self.w + } +} +impl R { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new((self.bits & 0x1fff) as u16) + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&self) -> FP_R { + FP_R::new(((self.bits >> 13) & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&mut self) -> FP_W { + FP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud_frac_mode](index.html) module"] +pub struct BAUD_FRAC_MODE_SPEC; +impl crate::RegisterSpec for BAUD_FRAC_MODE_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud_frac_mode::R](R) reader structure"] +impl crate::Readable for BAUD_FRAC_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud_frac_mode::W](W) writer structure"] +impl crate::Writable for BAUD_FRAC_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD_FRAC_MODE to value 0"] +impl crate::Resettable for BAUD_FRAC_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sercom0/usart_int/baud_fracfp_mode.rs b/pac/atsamc21j/src/sercom0/usart_int/baud_fracfp_mode.rs new file mode 100644 index 000000000000..0671db99cc9d --- /dev/null +++ b/pac/atsamc21j/src/sercom0/usart_int/baud_fracfp_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `BAUD_FRACFP_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD_FRACFP_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1fff) | (value as u16 & 0x1fff); + self.w + } +} +#[doc = "Field `FP` reader - Fractional Part"] +pub struct FP_R(crate::FieldReader); +impl FP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FP` writer - Fractional Part"] +pub struct FP_W<'a> { + w: &'a mut W, +} +impl<'a> FP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 13)) | ((value as u16 & 0x07) << 13); + self.w + } +} +impl R { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new((self.bits & 0x1fff) as u16) + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&self) -> FP_R { + FP_R::new(((self.bits >> 13) & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&mut self) -> FP_W { + FP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud_fracfp_mode](index.html) module"] +pub struct BAUD_FRACFP_MODE_SPEC; +impl crate::RegisterSpec for BAUD_FRACFP_MODE_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud_fracfp_mode::R](R) reader structure"] +impl crate::Readable for BAUD_FRACFP_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud_fracfp_mode::W](W) writer structure"] +impl crate::Writable for BAUD_FRACFP_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD_FRACFP_MODE to value 0"] +impl crate::Resettable for BAUD_FRACFP_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sercom0/usart_int/baud_usartfp_mode.rs b/pac/atsamc21j/src/sercom0/usart_int/baud_usartfp_mode.rs new file mode 100644 index 000000000000..b49a7ef5b84c --- /dev/null +++ b/pac/atsamc21j/src/sercom0/usart_int/baud_usartfp_mode.rs @@ -0,0 +1,103 @@ +#[doc = "Register `BAUD_USARTFP_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD_USARTFP_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud_usartfp_mode](index.html) module"] +pub struct BAUD_USARTFP_MODE_SPEC; +impl crate::RegisterSpec for BAUD_USARTFP_MODE_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud_usartfp_mode::R](R) reader structure"] +impl crate::Readable for BAUD_USARTFP_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud_usartfp_mode::W](W) writer structure"] +impl crate::Writable for BAUD_USARTFP_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD_USARTFP_MODE to value 0"] +impl crate::Resettable for BAUD_USARTFP_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sercom0/usart_int/ctrla.rs b/pac/atsamc21j/src/sercom0/usart_int/ctrla.rs new file mode 100644 index 000000000000..19d10ecf8e8f --- /dev/null +++ b/pac/atsamc21j/src/sercom0/usart_int/ctrla.rs @@ -0,0 +1,1171 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: USART with external clock"] + USART_EXT_CLK = 0, + #[doc = "1: USART with internal clock"] + USART_INT_CLK = 1, + #[doc = "2: SPI in slave operation"] + SPI_SLAVE = 2, + #[doc = "3: SPI in master operation"] + SPI_MASTER = 3, + #[doc = "4: I2C slave operation"] + I2C_SLAVE = 4, + #[doc = "5: I2C master operation"] + I2C_MASTER = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::USART_EXT_CLK), + 1 => Some(MODE_A::USART_INT_CLK), + 2 => Some(MODE_A::SPI_SLAVE), + 3 => Some(MODE_A::SPI_MASTER), + 4 => Some(MODE_A::I2C_SLAVE), + 5 => Some(MODE_A::I2C_MASTER), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_EXT_CLK`"] + #[inline(always)] + pub fn is_usart_ext_clk(&self) -> bool { + **self == MODE_A::USART_EXT_CLK + } + #[doc = "Checks if the value of the field is `USART_INT_CLK`"] + #[inline(always)] + pub fn is_usart_int_clk(&self) -> bool { + **self == MODE_A::USART_INT_CLK + } + #[doc = "Checks if the value of the field is `SPI_SLAVE`"] + #[inline(always)] + pub fn is_spi_slave(&self) -> bool { + **self == MODE_A::SPI_SLAVE + } + #[doc = "Checks if the value of the field is `SPI_MASTER`"] + #[inline(always)] + pub fn is_spi_master(&self) -> bool { + **self == MODE_A::SPI_MASTER + } + #[doc = "Checks if the value of the field is `I2C_SLAVE`"] + #[inline(always)] + pub fn is_i2c_slave(&self) -> bool { + **self == MODE_A::I2C_SLAVE + } + #[doc = "Checks if the value of the field is `I2C_MASTER`"] + #[inline(always)] + pub fn is_i2c_master(&self) -> bool { + **self == MODE_A::I2C_MASTER + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART with external clock"] + #[inline(always)] + pub fn usart_ext_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_EXT_CLK) + } + #[doc = "USART with internal clock"] + #[inline(always)] + pub fn usart_int_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_INT_CLK) + } + #[doc = "SPI in slave operation"] + #[inline(always)] + pub fn spi_slave(self) -> &'a mut W { + self.variant(MODE_A::SPI_SLAVE) + } + #[doc = "SPI in master operation"] + #[inline(always)] + pub fn spi_master(self) -> &'a mut W { + self.variant(MODE_A::SPI_MASTER) + } + #[doc = "I2C slave operation"] + #[inline(always)] + pub fn i2c_slave(self) -> &'a mut W { + self.variant(MODE_A::I2C_SLAVE) + } + #[doc = "I2C master operation"] + #[inline(always)] + pub fn i2c_master(self) -> &'a mut W { + self.variant(MODE_A::I2C_MASTER) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 2)) | ((value as u32 & 0x07) << 2); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `IBON` reader - Immediate Buffer Overflow Notification"] +pub struct IBON_R(crate::FieldReader); +impl IBON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IBON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IBON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IBON` writer - Immediate Buffer Overflow Notification"] +pub struct IBON_W<'a> { + w: &'a mut W, +} +impl<'a> IBON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Sample\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SAMPR_A { + #[doc = "0: 16x over-sampling using arithmetic baudrate generation"] + _16X_ARITHMETIC = 0, + #[doc = "1: 16x over-sampling using fractional baudrate generation"] + _16X_FRACTIONAL = 1, + #[doc = "2: 8x over-sampling using arithmetic baudrate generation"] + _8X_ARITHMETIC = 2, + #[doc = "3: 8x over-sampling using fractional baudrate generation"] + _8X_FRACTIONAL = 3, + #[doc = "4: 3x over-sampling using arithmetic baudrate generation"] + _3X_ARITHMETIC = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SAMPR_A) -> Self { + variant as _ + } +} +#[doc = "Field `SAMPR` reader - Sample"] +pub struct SAMPR_R(crate::FieldReader); +impl SAMPR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SAMPR_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SAMPR_A::_16X_ARITHMETIC), + 1 => Some(SAMPR_A::_16X_FRACTIONAL), + 2 => Some(SAMPR_A::_8X_ARITHMETIC), + 3 => Some(SAMPR_A::_8X_FRACTIONAL), + 4 => Some(SAMPR_A::_3X_ARITHMETIC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_16X_ARITHMETIC`"] + #[inline(always)] + pub fn is_16x_arithmetic(&self) -> bool { + **self == SAMPR_A::_16X_ARITHMETIC + } + #[doc = "Checks if the value of the field is `_16X_FRACTIONAL`"] + #[inline(always)] + pub fn is_16x_fractional(&self) -> bool { + **self == SAMPR_A::_16X_FRACTIONAL + } + #[doc = "Checks if the value of the field is `_8X_ARITHMETIC`"] + #[inline(always)] + pub fn is_8x_arithmetic(&self) -> bool { + **self == SAMPR_A::_8X_ARITHMETIC + } + #[doc = "Checks if the value of the field is `_8X_FRACTIONAL`"] + #[inline(always)] + pub fn is_8x_fractional(&self) -> bool { + **self == SAMPR_A::_8X_FRACTIONAL + } + #[doc = "Checks if the value of the field is `_3X_ARITHMETIC`"] + #[inline(always)] + pub fn is_3x_arithmetic(&self) -> bool { + **self == SAMPR_A::_3X_ARITHMETIC + } +} +impl core::ops::Deref for SAMPR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SAMPR` writer - Sample"] +pub struct SAMPR_W<'a> { + w: &'a mut W, +} +impl<'a> SAMPR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SAMPR_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "16x over-sampling using arithmetic baudrate generation"] + #[inline(always)] + pub fn _16x_arithmetic(self) -> &'a mut W { + self.variant(SAMPR_A::_16X_ARITHMETIC) + } + #[doc = "16x over-sampling using fractional baudrate generation"] + #[inline(always)] + pub fn _16x_fractional(self) -> &'a mut W { + self.variant(SAMPR_A::_16X_FRACTIONAL) + } + #[doc = "8x over-sampling using arithmetic baudrate generation"] + #[inline(always)] + pub fn _8x_arithmetic(self) -> &'a mut W { + self.variant(SAMPR_A::_8X_ARITHMETIC) + } + #[doc = "8x over-sampling using fractional baudrate generation"] + #[inline(always)] + pub fn _8x_fractional(self) -> &'a mut W { + self.variant(SAMPR_A::_8X_FRACTIONAL) + } + #[doc = "3x over-sampling using arithmetic baudrate generation"] + #[inline(always)] + pub fn _3x_arithmetic(self) -> &'a mut W { + self.variant(SAMPR_A::_3X_ARITHMETIC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 13)) | ((value as u32 & 0x07) << 13); + self.w + } +} +#[doc = "Transmit Data Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum TXPO_A { + #[doc = "0: SERCOM PAD\\[0\\] +is used for data transmission"] + PAD0 = 0, + #[doc = "1: SERCOM PAD\\[2\\] +is used for data transmission"] + PAD2 = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: TXPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `TXPO` reader - Transmit Data Pinout"] +pub struct TXPO_R(crate::FieldReader); +impl TXPO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TXPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(TXPO_A::PAD0), + 1 => Some(TXPO_A::PAD2), + _ => None, + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == TXPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == TXPO_A::PAD2 + } +} +impl core::ops::Deref for TXPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXPO` writer - Transmit Data Pinout"] +pub struct TXPO_W<'a> { + w: &'a mut W, +} +impl<'a> TXPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TXPO_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "SERCOM PAD\\[0\\] +is used for data transmission"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(TXPO_A::PAD0) + } + #[doc = "SERCOM PAD\\[2\\] +is used for data transmission"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(TXPO_A::PAD2) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Receive Data Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum RXPO_A { + #[doc = "0: SERCOM PAD\\[0\\] +is used for data reception"] + PAD0 = 0, + #[doc = "1: SERCOM PAD\\[1\\] +is used for data reception"] + PAD1 = 1, + #[doc = "2: SERCOM PAD\\[2\\] +is used for data reception"] + PAD2 = 2, + #[doc = "3: SERCOM PAD\\[3\\] +is used for data reception"] + PAD3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RXPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `RXPO` reader - Receive Data Pinout"] +pub struct RXPO_R(crate::FieldReader); +impl RXPO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RXPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RXPO_A { + match self.bits { + 0 => RXPO_A::PAD0, + 1 => RXPO_A::PAD1, + 2 => RXPO_A::PAD2, + 3 => RXPO_A::PAD3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == RXPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD1`"] + #[inline(always)] + pub fn is_pad1(&self) -> bool { + **self == RXPO_A::PAD1 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == RXPO_A::PAD2 + } + #[doc = "Checks if the value of the field is `PAD3`"] + #[inline(always)] + pub fn is_pad3(&self) -> bool { + **self == RXPO_A::PAD3 + } +} +impl core::ops::Deref for RXPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXPO` writer - Receive Data Pinout"] +pub struct RXPO_W<'a> { + w: &'a mut W, +} +impl<'a> RXPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RXPO_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "SERCOM PAD\\[0\\] +is used for data reception"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(RXPO_A::PAD0) + } + #[doc = "SERCOM PAD\\[1\\] +is used for data reception"] + #[inline(always)] + pub fn pad1(self) -> &'a mut W { + self.variant(RXPO_A::PAD1) + } + #[doc = "SERCOM PAD\\[2\\] +is used for data reception"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(RXPO_A::PAD2) + } + #[doc = "SERCOM PAD\\[3\\] +is used for data reception"] + #[inline(always)] + pub fn pad3(self) -> &'a mut W { + self.variant(RXPO_A::PAD3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 20)) | ((value as u32 & 0x03) << 20); + self.w + } +} +#[doc = "Field `SAMPA` reader - Sample Adjustment"] +pub struct SAMPA_R(crate::FieldReader); +impl SAMPA_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SAMPA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SAMPA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SAMPA` writer - Sample Adjustment"] +pub struct SAMPA_W<'a> { + w: &'a mut W, +} +impl<'a> SAMPA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 22)) | ((value as u32 & 0x03) << 22); + self.w + } +} +#[doc = "Frame Format\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FORM_A { + #[doc = "0: USART frame"] + USART_FRAME_NO_PARITY = 0, + #[doc = "1: USART frame with parity"] + USART_FRAME_WITH_PARITY = 1, + #[doc = "2: LIN Master - Break and sync generation"] + USART_FRAME_LIN_MASTER_MODE = 2, + #[doc = "4: Auto-baud - break detection and auto-baud"] + USART_FRAME_AUTO_BAUD_NO_PARITY = 4, + #[doc = "5: Auto-baud - break detection and auto-baud with parity"] + USART_FRAME_AUTO_BAUD_WITH_PARITY = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FORM_A) -> Self { + variant as _ + } +} +#[doc = "Field `FORM` reader - Frame Format"] +pub struct FORM_R(crate::FieldReader); +impl FORM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FORM_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(FORM_A::USART_FRAME_NO_PARITY), + 1 => Some(FORM_A::USART_FRAME_WITH_PARITY), + 2 => Some(FORM_A::USART_FRAME_LIN_MASTER_MODE), + 4 => Some(FORM_A::USART_FRAME_AUTO_BAUD_NO_PARITY), + 5 => Some(FORM_A::USART_FRAME_AUTO_BAUD_WITH_PARITY), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_FRAME_NO_PARITY`"] + #[inline(always)] + pub fn is_usart_frame_no_parity(&self) -> bool { + **self == FORM_A::USART_FRAME_NO_PARITY + } + #[doc = "Checks if the value of the field is `USART_FRAME_WITH_PARITY`"] + #[inline(always)] + pub fn is_usart_frame_with_parity(&self) -> bool { + **self == FORM_A::USART_FRAME_WITH_PARITY + } + #[doc = "Checks if the value of the field is `USART_FRAME_LIN_MASTER_MODE`"] + #[inline(always)] + pub fn is_usart_frame_lin_master_mode(&self) -> bool { + **self == FORM_A::USART_FRAME_LIN_MASTER_MODE + } + #[doc = "Checks if the value of the field is `USART_FRAME_AUTO_BAUD_NO_PARITY`"] + #[inline(always)] + pub fn is_usart_frame_auto_baud_no_parity(&self) -> bool { + **self == FORM_A::USART_FRAME_AUTO_BAUD_NO_PARITY + } + #[doc = "Checks if the value of the field is `USART_FRAME_AUTO_BAUD_WITH_PARITY`"] + #[inline(always)] + pub fn is_usart_frame_auto_baud_with_parity(&self) -> bool { + **self == FORM_A::USART_FRAME_AUTO_BAUD_WITH_PARITY + } +} +impl core::ops::Deref for FORM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FORM` writer - Frame Format"] +pub struct FORM_W<'a> { + w: &'a mut W, +} +impl<'a> FORM_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FORM_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART frame"] + #[inline(always)] + pub fn usart_frame_no_parity(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_NO_PARITY) + } + #[doc = "USART frame with parity"] + #[inline(always)] + pub fn usart_frame_with_parity(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_WITH_PARITY) + } + #[doc = "LIN Master - Break and sync generation"] + #[inline(always)] + pub fn usart_frame_lin_master_mode(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_LIN_MASTER_MODE) + } + #[doc = "Auto-baud - break detection and auto-baud"] + #[inline(always)] + pub fn usart_frame_auto_baud_no_parity(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_AUTO_BAUD_NO_PARITY) + } + #[doc = "Auto-baud - break detection and auto-baud with parity"] + #[inline(always)] + pub fn usart_frame_auto_baud_with_parity(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_AUTO_BAUD_WITH_PARITY) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Communication Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CMODE_A { + #[doc = "0: Asynchronous Communication"] + ASYNC = 0, + #[doc = "1: Synchronous Communication"] + SYNC = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CMODE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CMODE` reader - Communication Mode"] +pub struct CMODE_R(crate::FieldReader); +impl CMODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CMODE_A { + match self.bits { + false => CMODE_A::ASYNC, + true => CMODE_A::SYNC, + } + } + #[doc = "Checks if the value of the field is `ASYNC`"] + #[inline(always)] + pub fn is_async(&self) -> bool { + **self == CMODE_A::ASYNC + } + #[doc = "Checks if the value of the field is `SYNC`"] + #[inline(always)] + pub fn is_sync(&self) -> bool { + **self == CMODE_A::SYNC + } +} +impl core::ops::Deref for CMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMODE` writer - Communication Mode"] +pub struct CMODE_W<'a> { + w: &'a mut W, +} +impl<'a> CMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMODE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Asynchronous Communication"] + #[inline(always)] + pub fn async_(self) -> &'a mut W { + self.variant(CMODE_A::ASYNC) + } + #[doc = "Synchronous Communication"] + #[inline(always)] + pub fn sync(self) -> &'a mut W { + self.variant(CMODE_A::SYNC) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Clock Polarity\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CPOL_A { + #[doc = "0: TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge"] + IDLE_LOW = 0, + #[doc = "1: TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge"] + IDLE_HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CPOL_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CPOL` reader - Clock Polarity"] +pub struct CPOL_R(crate::FieldReader); +impl CPOL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPOL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CPOL_A { + match self.bits { + false => CPOL_A::IDLE_LOW, + true => CPOL_A::IDLE_HIGH, + } + } + #[doc = "Checks if the value of the field is `IDLE_LOW`"] + #[inline(always)] + pub fn is_idle_low(&self) -> bool { + **self == CPOL_A::IDLE_LOW + } + #[doc = "Checks if the value of the field is `IDLE_HIGH`"] + #[inline(always)] + pub fn is_idle_high(&self) -> bool { + **self == CPOL_A::IDLE_HIGH + } +} +impl core::ops::Deref for CPOL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPOL` writer - Clock Polarity"] +pub struct CPOL_W<'a> { + w: &'a mut W, +} +impl<'a> CPOL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CPOL_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge"] + #[inline(always)] + pub fn idle_low(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_LOW) + } + #[doc = "TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge"] + #[inline(always)] + pub fn idle_high(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_HIGH) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29); + self.w + } +} +#[doc = "Data Order\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum DORD_A { + #[doc = "0: MSB is transmitted first"] + MSB = 0, + #[doc = "1: LSB is transmitted first"] + LSB = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DORD_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DORD` reader - Data Order"] +pub struct DORD_R(crate::FieldReader); +impl DORD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DORD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DORD_A { + match self.bits { + false => DORD_A::MSB, + true => DORD_A::LSB, + } + } + #[doc = "Checks if the value of the field is `MSB`"] + #[inline(always)] + pub fn is_msb(&self) -> bool { + **self == DORD_A::MSB + } + #[doc = "Checks if the value of the field is `LSB`"] + #[inline(always)] + pub fn is_lsb(&self) -> bool { + **self == DORD_A::LSB + } +} +impl core::ops::Deref for DORD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DORD` writer - Data Order"] +pub struct DORD_W<'a> { + w: &'a mut W, +} +impl<'a> DORD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DORD_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "MSB is transmitted first"] + #[inline(always)] + pub fn msb(self) -> &'a mut W { + self.variant(DORD_A::MSB) + } + #[doc = "LSB is transmitted first"] + #[inline(always)] + pub fn lsb(self) -> &'a mut W { + self.variant(DORD_A::LSB) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x07) as u8) + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&self) -> IBON_R { + IBON_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bits 13:15 - Sample"] + #[inline(always)] + pub fn sampr(&self) -> SAMPR_R { + SAMPR_R::new(((self.bits >> 13) & 0x07) as u8) + } + #[doc = "Bits 16:17 - Transmit Data Pinout"] + #[inline(always)] + pub fn txpo(&self) -> TXPO_R { + TXPO_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bits 20:21 - Receive Data Pinout"] + #[inline(always)] + pub fn rxpo(&self) -> RXPO_R { + RXPO_R::new(((self.bits >> 20) & 0x03) as u8) + } + #[doc = "Bits 22:23 - Sample Adjustment"] + #[inline(always)] + pub fn sampa(&self) -> SAMPA_R { + SAMPA_R::new(((self.bits >> 22) & 0x03) as u8) + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&self) -> FORM_R { + FORM_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 28 - Communication Mode"] + #[inline(always)] + pub fn cmode(&self) -> CMODE_R { + CMODE_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&self) -> CPOL_R { + CPOL_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&self) -> DORD_R { + DORD_R::new(((self.bits >> 30) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&mut self) -> IBON_W { + IBON_W { w: self } + } + #[doc = "Bits 13:15 - Sample"] + #[inline(always)] + pub fn sampr(&mut self) -> SAMPR_W { + SAMPR_W { w: self } + } + #[doc = "Bits 16:17 - Transmit Data Pinout"] + #[inline(always)] + pub fn txpo(&mut self) -> TXPO_W { + TXPO_W { w: self } + } + #[doc = "Bits 20:21 - Receive Data Pinout"] + #[inline(always)] + pub fn rxpo(&mut self) -> RXPO_W { + RXPO_W { w: self } + } + #[doc = "Bits 22:23 - Sample Adjustment"] + #[inline(always)] + pub fn sampa(&mut self) -> SAMPA_W { + SAMPA_W { w: self } + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&mut self) -> FORM_W { + FORM_W { w: self } + } + #[doc = "Bit 28 - Communication Mode"] + #[inline(always)] + pub fn cmode(&mut self) -> CMODE_W { + CMODE_W { w: self } + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&mut self) -> CPOL_W { + CPOL_W { w: self } + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&mut self) -> DORD_W { + DORD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sercom0/usart_int/ctrlb.rs b/pac/atsamc21j/src/sercom0/usart_int/ctrlb.rs new file mode 100644 index 000000000000..d556e0c3cfc2 --- /dev/null +++ b/pac/atsamc21j/src/sercom0/usart_int/ctrlb.rs @@ -0,0 +1,651 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Character Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CHSIZE_A { + #[doc = "0: 8 Bits"] + _8_BIT = 0, + #[doc = "1: 9 Bits"] + _9_BIT = 1, + #[doc = "5: 5 Bits"] + _5_BIT = 5, + #[doc = "6: 6 Bits"] + _6_BIT = 6, + #[doc = "7: 7 Bits"] + _7_BIT = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CHSIZE_A) -> Self { + variant as _ + } +} +#[doc = "Field `CHSIZE` reader - Character Size"] +pub struct CHSIZE_R(crate::FieldReader); +impl CHSIZE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CHSIZE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CHSIZE_A::_8_BIT), + 1 => Some(CHSIZE_A::_9_BIT), + 5 => Some(CHSIZE_A::_5_BIT), + 6 => Some(CHSIZE_A::_6_BIT), + 7 => Some(CHSIZE_A::_7_BIT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_8_BIT`"] + #[inline(always)] + pub fn is_8_bit(&self) -> bool { + **self == CHSIZE_A::_8_BIT + } + #[doc = "Checks if the value of the field is `_9_BIT`"] + #[inline(always)] + pub fn is_9_bit(&self) -> bool { + **self == CHSIZE_A::_9_BIT + } + #[doc = "Checks if the value of the field is `_5_BIT`"] + #[inline(always)] + pub fn is_5_bit(&self) -> bool { + **self == CHSIZE_A::_5_BIT + } + #[doc = "Checks if the value of the field is `_6_BIT`"] + #[inline(always)] + pub fn is_6_bit(&self) -> bool { + **self == CHSIZE_A::_6_BIT + } + #[doc = "Checks if the value of the field is `_7_BIT`"] + #[inline(always)] + pub fn is_7_bit(&self) -> bool { + **self == CHSIZE_A::_7_BIT + } +} +impl core::ops::Deref for CHSIZE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHSIZE` writer - Character Size"] +pub struct CHSIZE_W<'a> { + w: &'a mut W, +} +impl<'a> CHSIZE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CHSIZE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8 Bits"] + #[inline(always)] + pub fn _8_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_8_BIT) + } + #[doc = "9 Bits"] + #[inline(always)] + pub fn _9_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_9_BIT) + } + #[doc = "5 Bits"] + #[inline(always)] + pub fn _5_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_5_BIT) + } + #[doc = "6 Bits"] + #[inline(always)] + pub fn _6_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_6_BIT) + } + #[doc = "7 Bits"] + #[inline(always)] + pub fn _7_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_7_BIT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Stop Bit Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SBMODE_A { + #[doc = "0: One Stop Bit"] + _1_BIT = 0, + #[doc = "1: Two Stop Bits"] + _2_BIT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SBMODE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SBMODE` reader - Stop Bit Mode"] +pub struct SBMODE_R(crate::FieldReader); +impl SBMODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SBMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SBMODE_A { + match self.bits { + false => SBMODE_A::_1_BIT, + true => SBMODE_A::_2_BIT, + } + } + #[doc = "Checks if the value of the field is `_1_BIT`"] + #[inline(always)] + pub fn is_1_bit(&self) -> bool { + **self == SBMODE_A::_1_BIT + } + #[doc = "Checks if the value of the field is `_2_BIT`"] + #[inline(always)] + pub fn is_2_bit(&self) -> bool { + **self == SBMODE_A::_2_BIT + } +} +impl core::ops::Deref for SBMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SBMODE` writer - Stop Bit Mode"] +pub struct SBMODE_W<'a> { + w: &'a mut W, +} +impl<'a> SBMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SBMODE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "One Stop Bit"] + #[inline(always)] + pub fn _1_bit(self) -> &'a mut W { + self.variant(SBMODE_A::_1_BIT) + } + #[doc = "Two Stop Bits"] + #[inline(always)] + pub fn _2_bit(self) -> &'a mut W { + self.variant(SBMODE_A::_2_BIT) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `COLDEN` reader - Collision Detection Enable"] +pub struct COLDEN_R(crate::FieldReader); +impl COLDEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COLDEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COLDEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COLDEN` writer - Collision Detection Enable"] +pub struct COLDEN_W<'a> { + w: &'a mut W, +} +impl<'a> COLDEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `SFDE` reader - Start of Frame Detection Enable"] +pub struct SFDE_R(crate::FieldReader); +impl SFDE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SFDE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SFDE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SFDE` writer - Start of Frame Detection Enable"] +pub struct SFDE_W<'a> { + w: &'a mut W, +} +impl<'a> SFDE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `ENC` reader - Encoding Format"] +pub struct ENC_R(crate::FieldReader); +impl ENC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENC` writer - Encoding Format"] +pub struct ENC_W<'a> { + w: &'a mut W, +} +impl<'a> ENC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Parity Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PMODE_A { + #[doc = "0: Even Parity"] + EVEN = 0, + #[doc = "1: Odd Parity"] + ODD = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PMODE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PMODE` reader - Parity Mode"] +pub struct PMODE_R(crate::FieldReader); +impl PMODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PMODE_A { + match self.bits { + false => PMODE_A::EVEN, + true => PMODE_A::ODD, + } + } + #[doc = "Checks if the value of the field is `EVEN`"] + #[inline(always)] + pub fn is_even(&self) -> bool { + **self == PMODE_A::EVEN + } + #[doc = "Checks if the value of the field is `ODD`"] + #[inline(always)] + pub fn is_odd(&self) -> bool { + **self == PMODE_A::ODD + } +} +impl core::ops::Deref for PMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PMODE` writer - Parity Mode"] +pub struct PMODE_W<'a> { + w: &'a mut W, +} +impl<'a> PMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PMODE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Even Parity"] + #[inline(always)] + pub fn even(self) -> &'a mut W { + self.variant(PMODE_A::EVEN) + } + #[doc = "Odd Parity"] + #[inline(always)] + pub fn odd(self) -> &'a mut W { + self.variant(PMODE_A::ODD) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `TXEN` reader - Transmitter Enable"] +pub struct TXEN_R(crate::FieldReader); +impl TXEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXEN` writer - Transmitter Enable"] +pub struct TXEN_W<'a> { + w: &'a mut W, +} +impl<'a> TXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `RXEN` reader - Receiver Enable"] +pub struct RXEN_R(crate::FieldReader); +impl RXEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXEN` writer - Receiver Enable"] +pub struct RXEN_W<'a> { + w: &'a mut W, +} +impl<'a> RXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `LINCMD` reader - LIN Command"] +pub struct LINCMD_R(crate::FieldReader); +impl LINCMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LINCMD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LINCMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LINCMD` writer - LIN Command"] +pub struct LINCMD_W<'a> { + w: &'a mut W, +} +impl<'a> LINCMD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 24)) | ((value as u32 & 0x03) << 24); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&self) -> CHSIZE_R { + CHSIZE_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 6 - Stop Bit Mode"] + #[inline(always)] + pub fn sbmode(&self) -> SBMODE_R { + SBMODE_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 8 - Collision Detection Enable"] + #[inline(always)] + pub fn colden(&self) -> COLDEN_R { + COLDEN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Start of Frame Detection Enable"] + #[inline(always)] + pub fn sfde(&self) -> SFDE_R { + SFDE_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Encoding Format"] + #[inline(always)] + pub fn enc(&self) -> ENC_R { + ENC_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 13 - Parity Mode"] + #[inline(always)] + pub fn pmode(&self) -> PMODE_R { + PMODE_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 16 - Transmitter Enable"] + #[inline(always)] + pub fn txen(&self) -> TXEN_R { + TXEN_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&self) -> RXEN_R { + RXEN_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bits 24:25 - LIN Command"] + #[inline(always)] + pub fn lincmd(&self) -> LINCMD_R { + LINCMD_R::new(((self.bits >> 24) & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&mut self) -> CHSIZE_W { + CHSIZE_W { w: self } + } + #[doc = "Bit 6 - Stop Bit Mode"] + #[inline(always)] + pub fn sbmode(&mut self) -> SBMODE_W { + SBMODE_W { w: self } + } + #[doc = "Bit 8 - Collision Detection Enable"] + #[inline(always)] + pub fn colden(&mut self) -> COLDEN_W { + COLDEN_W { w: self } + } + #[doc = "Bit 9 - Start of Frame Detection Enable"] + #[inline(always)] + pub fn sfde(&mut self) -> SFDE_W { + SFDE_W { w: self } + } + #[doc = "Bit 10 - Encoding Format"] + #[inline(always)] + pub fn enc(&mut self) -> ENC_W { + ENC_W { w: self } + } + #[doc = "Bit 13 - Parity Mode"] + #[inline(always)] + pub fn pmode(&mut self) -> PMODE_W { + PMODE_W { w: self } + } + #[doc = "Bit 16 - Transmitter Enable"] + #[inline(always)] + pub fn txen(&mut self) -> TXEN_W { + TXEN_W { w: self } + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&mut self) -> RXEN_W { + RXEN_W { w: self } + } + #[doc = "Bits 24:25 - LIN Command"] + #[inline(always)] + pub fn lincmd(&mut self) -> LINCMD_W { + LINCMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sercom0/usart_int/ctrlc.rs b/pac/atsamc21j/src/sercom0/usart_int/ctrlc.rs new file mode 100644 index 000000000000..e2182cc7f768 --- /dev/null +++ b/pac/atsamc21j/src/sercom0/usart_int/ctrlc.rs @@ -0,0 +1,177 @@ +#[doc = "Register `CTRLC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `GTIME` reader - RS485 Guard Time"] +pub struct GTIME_R(crate::FieldReader); +impl GTIME_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + GTIME_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GTIME_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GTIME` writer - RS485 Guard Time"] +pub struct GTIME_W<'a> { + w: &'a mut W, +} +impl<'a> GTIME_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Field `BRKLEN` reader - LIN Master Break Length"] +pub struct BRKLEN_R(crate::FieldReader); +impl BRKLEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BRKLEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BRKLEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BRKLEN` writer - LIN Master Break Length"] +pub struct BRKLEN_W<'a> { + w: &'a mut W, +} +impl<'a> BRKLEN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 8)) | ((value as u32 & 0x03) << 8); + self.w + } +} +#[doc = "Field `HDRDLY` reader - LIN Master Header Delay"] +pub struct HDRDLY_R(crate::FieldReader); +impl HDRDLY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + HDRDLY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HDRDLY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HDRDLY` writer - LIN Master Header Delay"] +pub struct HDRDLY_W<'a> { + w: &'a mut W, +} +impl<'a> HDRDLY_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 10)) | ((value as u32 & 0x03) << 10); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - RS485 Guard Time"] + #[inline(always)] + pub fn gtime(&self) -> GTIME_R { + GTIME_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bits 8:9 - LIN Master Break Length"] + #[inline(always)] + pub fn brklen(&self) -> BRKLEN_R { + BRKLEN_R::new(((self.bits >> 8) & 0x03) as u8) + } + #[doc = "Bits 10:11 - LIN Master Header Delay"] + #[inline(always)] + pub fn hdrdly(&self) -> HDRDLY_R { + HDRDLY_R::new(((self.bits >> 10) & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - RS485 Guard Time"] + #[inline(always)] + pub fn gtime(&mut self) -> GTIME_W { + GTIME_W { w: self } + } + #[doc = "Bits 8:9 - LIN Master Break Length"] + #[inline(always)] + pub fn brklen(&mut self) -> BRKLEN_W { + BRKLEN_W { w: self } + } + #[doc = "Bits 10:11 - LIN Master Header Delay"] + #[inline(always)] + pub fn hdrdly(&mut self) -> HDRDLY_W { + HDRDLY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Control C\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlc](index.html) module"] +pub struct CTRLC_SPEC; +impl crate::RegisterSpec for CTRLC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlc::R](R) reader structure"] +impl crate::Readable for CTRLC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlc::W](W) writer structure"] +impl crate::Writable for CTRLC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLC to value 0"] +impl crate::Resettable for CTRLC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sercom0/usart_int/data.rs b/pac/atsamc21j/src/sercom0/usart_int/data.rs new file mode 100644 index 000000000000..19d74c337d44 --- /dev/null +++ b/pac/atsamc21j/src/sercom0/usart_int/data.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data Value"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data Value"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01ff) | (value as u16 & 0x01ff); + self.w + } +} +impl R { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new((self.bits & 0x01ff) as u16) + } +} +impl W { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sercom0/usart_int/dbgctrl.rs b/pac/atsamc21j/src/sercom0/usart_int/dbgctrl.rs new file mode 100644 index 000000000000..0ac5b9c7b902 --- /dev/null +++ b/pac/atsamc21j/src/sercom0/usart_int/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGSTOP` reader - Debug Mode"] +pub struct DBGSTOP_R(crate::FieldReader); +impl DBGSTOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGSTOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGSTOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGSTOP` writer - Debug Mode"] +pub struct DBGSTOP_W<'a> { + w: &'a mut W, +} +impl<'a> DBGSTOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&self) -> DBGSTOP_R { + DBGSTOP_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&mut self) -> DBGSTOP_W { + DBGSTOP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sercom0/usart_int/intenclr.rs b/pac/atsamc21j/src/sercom0/usart_int/intenclr.rs new file mode 100644 index 000000000000..5ad23ad15636 --- /dev/null +++ b/pac/atsamc21j/src/sercom0/usart_int/intenclr.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Disable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Disable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Disable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Disable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Disable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Disable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RXS` reader - Receive Start Interrupt Disable"] +pub struct RXS_R(crate::FieldReader); +impl RXS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXS` writer - Receive Start Interrupt Disable"] +pub struct RXS_W<'a> { + w: &'a mut W, +} +impl<'a> RXS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CTSIC` reader - Clear To Send Input Change Interrupt Disable"] +pub struct CTSIC_R(crate::FieldReader); +impl CTSIC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTSIC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTSIC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTSIC` writer - Clear To Send Input Change Interrupt Disable"] +pub struct CTSIC_W<'a> { + w: &'a mut W, +} +impl<'a> CTSIC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RXBRK` reader - Break Received Interrupt Disable"] +pub struct RXBRK_R(crate::FieldReader); +impl RXBRK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXBRK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXBRK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXBRK` writer - Break Received Interrupt Disable"] +pub struct RXBRK_W<'a> { + w: &'a mut W, +} +impl<'a> RXBRK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Disable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Disable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Receive Start Interrupt Disable"] + #[inline(always)] + pub fn rxs(&self) -> RXS_R { + RXS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Disable"] + #[inline(always)] + pub fn ctsic(&self) -> CTSIC_R { + CTSIC_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Break Received Interrupt Disable"] + #[inline(always)] + pub fn rxbrk(&self) -> RXBRK_R { + RXBRK_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Receive Start Interrupt Disable"] + #[inline(always)] + pub fn rxs(&mut self) -> RXS_W { + RXS_W { w: self } + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Disable"] + #[inline(always)] + pub fn ctsic(&mut self) -> CTSIC_W { + CTSIC_W { w: self } + } + #[doc = "Bit 5 - Break Received Interrupt Disable"] + #[inline(always)] + pub fn rxbrk(&mut self) -> RXBRK_W { + RXBRK_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sercom0/usart_int/intenset.rs b/pac/atsamc21j/src/sercom0/usart_int/intenset.rs new file mode 100644 index 000000000000..457f440e13e9 --- /dev/null +++ b/pac/atsamc21j/src/sercom0/usart_int/intenset.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Enable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Enable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Enable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Enable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Enable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Enable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RXS` reader - Receive Start Interrupt Enable"] +pub struct RXS_R(crate::FieldReader); +impl RXS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXS` writer - Receive Start Interrupt Enable"] +pub struct RXS_W<'a> { + w: &'a mut W, +} +impl<'a> RXS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CTSIC` reader - Clear To Send Input Change Interrupt Enable"] +pub struct CTSIC_R(crate::FieldReader); +impl CTSIC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTSIC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTSIC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTSIC` writer - Clear To Send Input Change Interrupt Enable"] +pub struct CTSIC_W<'a> { + w: &'a mut W, +} +impl<'a> CTSIC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RXBRK` reader - Break Received Interrupt Enable"] +pub struct RXBRK_R(crate::FieldReader); +impl RXBRK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXBRK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXBRK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXBRK` writer - Break Received Interrupt Enable"] +pub struct RXBRK_W<'a> { + w: &'a mut W, +} +impl<'a> RXBRK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Receive Start Interrupt Enable"] + #[inline(always)] + pub fn rxs(&self) -> RXS_R { + RXS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Enable"] + #[inline(always)] + pub fn ctsic(&self) -> CTSIC_R { + CTSIC_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Break Received Interrupt Enable"] + #[inline(always)] + pub fn rxbrk(&self) -> RXBRK_R { + RXBRK_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Receive Start Interrupt Enable"] + #[inline(always)] + pub fn rxs(&mut self) -> RXS_W { + RXS_W { w: self } + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Enable"] + #[inline(always)] + pub fn ctsic(&mut self) -> CTSIC_W { + CTSIC_W { w: self } + } + #[doc = "Bit 5 - Break Received Interrupt Enable"] + #[inline(always)] + pub fn rxbrk(&mut self) -> RXBRK_W { + RXBRK_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sercom0/usart_int/intflag.rs b/pac/atsamc21j/src/sercom0/usart_int/intflag.rs new file mode 100644 index 000000000000..a6a26321b8c4 --- /dev/null +++ b/pac/atsamc21j/src/sercom0/usart_int/intflag.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RXS` reader - Receive Start Interrupt"] +pub struct RXS_R(crate::FieldReader); +impl RXS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXS` writer - Receive Start Interrupt"] +pub struct RXS_W<'a> { + w: &'a mut W, +} +impl<'a> RXS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CTSIC` reader - Clear To Send Input Change Interrupt"] +pub struct CTSIC_R(crate::FieldReader); +impl CTSIC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTSIC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTSIC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTSIC` writer - Clear To Send Input Change Interrupt"] +pub struct CTSIC_W<'a> { + w: &'a mut W, +} +impl<'a> CTSIC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RXBRK` reader - Break Received Interrupt"] +pub struct RXBRK_R(crate::FieldReader); +impl RXBRK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXBRK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXBRK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXBRK` writer - Break Received Interrupt"] +pub struct RXBRK_W<'a> { + w: &'a mut W, +} +impl<'a> RXBRK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Receive Start Interrupt"] + #[inline(always)] + pub fn rxs(&self) -> RXS_R { + RXS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt"] + #[inline(always)] + pub fn ctsic(&self) -> CTSIC_R { + CTSIC_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Break Received Interrupt"] + #[inline(always)] + pub fn rxbrk(&self) -> RXBRK_R { + RXBRK_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Receive Start Interrupt"] + #[inline(always)] + pub fn rxs(&mut self) -> RXS_W { + RXS_W { w: self } + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt"] + #[inline(always)] + pub fn ctsic(&mut self) -> CTSIC_W { + CTSIC_W { w: self } + } + #[doc = "Bit 5 - Break Received Interrupt"] + #[inline(always)] + pub fn rxbrk(&mut self) -> RXBRK_W { + RXBRK_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sercom0/usart_int/rxpl.rs b/pac/atsamc21j/src/sercom0/usart_int/rxpl.rs new file mode 100644 index 000000000000..324cbac371c1 --- /dev/null +++ b/pac/atsamc21j/src/sercom0/usart_int/rxpl.rs @@ -0,0 +1,103 @@ +#[doc = "Register `RXPL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RXPL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RXPL` reader - Receive Pulse Length"] +pub struct RXPL_R(crate::FieldReader); +impl RXPL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RXPL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXPL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXPL` writer - Receive Pulse Length"] +pub struct RXPL_W<'a> { + w: &'a mut W, +} +impl<'a> RXPL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Receive Pulse Length"] + #[inline(always)] + pub fn rxpl(&self) -> RXPL_R { + RXPL_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Receive Pulse Length"] + #[inline(always)] + pub fn rxpl(&mut self) -> RXPL_W { + RXPL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Receive Pulse Length\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxpl](index.html) module"] +pub struct RXPL_SPEC; +impl crate::RegisterSpec for RXPL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [rxpl::R](R) reader structure"] +impl crate::Readable for RXPL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rxpl::W](W) writer structure"] +impl crate::Writable for RXPL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RXPL to value 0"] +impl crate::Resettable for RXPL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sercom0/usart_int/status.rs b/pac/atsamc21j/src/sercom0/usart_int/status.rs new file mode 100644 index 000000000000..1a92018a359b --- /dev/null +++ b/pac/atsamc21j/src/sercom0/usart_int/status.rs @@ -0,0 +1,395 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PERR` reader - Parity Error"] +pub struct PERR_R(crate::FieldReader); +impl PERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERR` writer - Parity Error"] +pub struct PERR_W<'a> { + w: &'a mut W, +} +impl<'a> PERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `FERR` reader - Frame Error"] +pub struct FERR_R(crate::FieldReader); +impl FERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FERR` writer - Frame Error"] +pub struct FERR_W<'a> { + w: &'a mut W, +} +impl<'a> FERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `BUFOVF` reader - Buffer Overflow"] +pub struct BUFOVF_R(crate::FieldReader); +impl BUFOVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUFOVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUFOVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUFOVF` writer - Buffer Overflow"] +pub struct BUFOVF_W<'a> { + w: &'a mut W, +} +impl<'a> BUFOVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CTS` reader - Clear To Send"] +pub struct CTS_R(crate::FieldReader); +impl CTS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTS` writer - Clear To Send"] +pub struct CTS_W<'a> { + w: &'a mut W, +} +impl<'a> CTS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ISF` reader - Inconsistent Sync Field"] +pub struct ISF_R(crate::FieldReader); +impl ISF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ISF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ISF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ISF` writer - Inconsistent Sync Field"] +pub struct ISF_W<'a> { + w: &'a mut W, +} +impl<'a> ISF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `COLL` reader - Collision Detected"] +pub struct COLL_R(crate::FieldReader); +impl COLL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COLL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COLL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COLL` writer - Collision Detected"] +pub struct COLL_W<'a> { + w: &'a mut W, +} +impl<'a> COLL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `TXE` reader - Transmitter Empty"] +pub struct TXE_R(crate::FieldReader); +impl TXE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXE` writer - Transmitter Empty"] +pub struct TXE_W<'a> { + w: &'a mut W, +} +impl<'a> TXE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - Parity Error"] + #[inline(always)] + pub fn perr(&self) -> PERR_R { + PERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Frame Error"] + #[inline(always)] + pub fn ferr(&self) -> FERR_R { + FERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&self) -> BUFOVF_R { + BUFOVF_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Clear To Send"] + #[inline(always)] + pub fn cts(&self) -> CTS_R { + CTS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Inconsistent Sync Field"] + #[inline(always)] + pub fn isf(&self) -> ISF_R { + ISF_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Collision Detected"] + #[inline(always)] + pub fn coll(&self) -> COLL_R { + COLL_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Transmitter Empty"] + #[inline(always)] + pub fn txe(&self) -> TXE_R { + TXE_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Parity Error"] + #[inline(always)] + pub fn perr(&mut self) -> PERR_W { + PERR_W { w: self } + } + #[doc = "Bit 1 - Frame Error"] + #[inline(always)] + pub fn ferr(&mut self) -> FERR_W { + FERR_W { w: self } + } + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&mut self) -> BUFOVF_W { + BUFOVF_W { w: self } + } + #[doc = "Bit 3 - Clear To Send"] + #[inline(always)] + pub fn cts(&mut self) -> CTS_W { + CTS_W { w: self } + } + #[doc = "Bit 4 - Inconsistent Sync Field"] + #[inline(always)] + pub fn isf(&mut self) -> ISF_W { + ISF_W { w: self } + } + #[doc = "Bit 5 - Collision Detected"] + #[inline(always)] + pub fn coll(&mut self) -> COLL_W { + COLL_W { w: self } + } + #[doc = "Bit 6 - Transmitter Empty"] + #[inline(always)] + pub fn txe(&mut self) -> TXE_W { + TXE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sercom0/usart_int/syncbusy.rs b/pac/atsamc21j/src/sercom0/usart_int/syncbusy.rs new file mode 100644 index 000000000000..5dea9a5a7bab --- /dev/null +++ b/pac/atsamc21j/src/sercom0/usart_int/syncbusy.rs @@ -0,0 +1,93 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - SERCOM Enable Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLB` reader - CTRLB Synchronization Busy"] +pub struct CTRLB_R(crate::FieldReader); +impl CTRLB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM Enable Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - CTRLB Synchronization Busy"] + #[inline(always)] + pub fn ctrlb(&self) -> CTRLB_R { + CTRLB_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +#[doc = "USART_INT Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/supc.rs b/pac/atsamc21j/src/supc.rs new file mode 100644 index 000000000000..452d8f3f9613 --- /dev/null +++ b/pac/atsamc21j/src/supc.rs @@ -0,0 +1,52 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x04 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x08 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x0c - Power and Clocks Status"] + pub status: crate::Reg, + #[doc = "0x10 - BODVDD Control"] + pub bodvdd: crate::Reg, + #[doc = "0x14 - BODCORE Control"] + pub bodcore: crate::Reg, + #[doc = "0x18 - VREG Control"] + pub vreg: crate::Reg, + #[doc = "0x1c - VREF Control"] + pub vref: crate::Reg, +} +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Power and Clocks Status"] +pub mod status; +#[doc = "BODVDD register accessor: an alias for `Reg`"] +pub type BODVDD = crate::Reg; +#[doc = "BODVDD Control"] +pub mod bodvdd; +#[doc = "BODCORE register accessor: an alias for `Reg`"] +pub type BODCORE = crate::Reg; +#[doc = "BODCORE Control"] +pub mod bodcore; +#[doc = "VREG register accessor: an alias for `Reg`"] +pub type VREG = crate::Reg; +#[doc = "VREG Control"] +pub mod vreg; +#[doc = "VREF register accessor: an alias for `Reg`"] +pub type VREF = crate::Reg; +#[doc = "VREF Control"] +pub mod vref; diff --git a/pac/atsamc21j/src/supc/bodcore.rs b/pac/atsamc21j/src/supc/bodcore.rs new file mode 100644 index 000000000000..670dec8e048c --- /dev/null +++ b/pac/atsamc21j/src/supc/bodcore.rs @@ -0,0 +1,705 @@ +#[doc = "Register `BODCORE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BODCORE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `HYST` reader - Hysteresis Enable"] +pub struct HYST_R(crate::FieldReader); +impl HYST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HYST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HYST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HYST` writer - Hysteresis Enable"] +pub struct HYST_W<'a> { + w: &'a mut W, +} +impl<'a> HYST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Action when Threshold Crossed\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum ACTION_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: The BODCORE generates a reset"] + RESET = 1, + #[doc = "2: The BODCORE generates an interrupt"] + INT = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: ACTION_A) -> Self { + variant as _ + } +} +#[doc = "Field `ACTION` reader - Action when Threshold Crossed"] +pub struct ACTION_R(crate::FieldReader); +impl ACTION_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ACTION_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(ACTION_A::NONE), + 1 => Some(ACTION_A::RESET), + 2 => Some(ACTION_A::INT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == ACTION_A::NONE + } + #[doc = "Checks if the value of the field is `RESET`"] + #[inline(always)] + pub fn is_reset(&self) -> bool { + **self == ACTION_A::RESET + } + #[doc = "Checks if the value of the field is `INT`"] + #[inline(always)] + pub fn is_int(&self) -> bool { + **self == ACTION_A::INT + } +} +impl core::ops::Deref for ACTION_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ACTION` writer - Action when Threshold Crossed"] +pub struct ACTION_W<'a> { + w: &'a mut W, +} +impl<'a> ACTION_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: ACTION_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(ACTION_A::NONE) + } + #[doc = "The BODCORE generates a reset"] + #[inline(always)] + pub fn reset(self) -> &'a mut W { + self.variant(ACTION_A::RESET) + } + #[doc = "The BODCORE generates an interrupt"] + #[inline(always)] + pub fn int(self) -> &'a mut W { + self.variant(ACTION_A::INT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 3)) | ((value as u32 & 0x03) << 3); + self.w + } +} +#[doc = "Field `STDBYCFG` reader - Configuration in Standby mode"] +pub struct STDBYCFG_R(crate::FieldReader); +impl STDBYCFG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STDBYCFG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STDBYCFG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STDBYCFG` writer - Configuration in Standby mode"] +pub struct STDBYCFG_W<'a> { + w: &'a mut W, +} +impl<'a> STDBYCFG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ACTCFG` reader - Configuration in Active mode"] +pub struct ACTCFG_R(crate::FieldReader); +impl ACTCFG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ACTCFG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ACTCFG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ACTCFG` writer - Configuration in Active mode"] +pub struct ACTCFG_W<'a> { + w: &'a mut W, +} +impl<'a> ACTCFG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Prescaler Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PSEL_A { + #[doc = "0: Divide clock by 2"] + DIV2 = 0, + #[doc = "1: Divide clock by 4"] + DIV4 = 1, + #[doc = "2: Divide clock by 8"] + DIV8 = 2, + #[doc = "3: Divide clock by 16"] + DIV16 = 3, + #[doc = "4: Divide clock by 32"] + DIV32 = 4, + #[doc = "5: Divide clock by 64"] + DIV64 = 5, + #[doc = "6: Divide clock by 128"] + DIV128 = 6, + #[doc = "7: Divide clock by 256"] + DIV256 = 7, + #[doc = "8: Divide clock by 512"] + DIV512 = 8, + #[doc = "9: Divide clock by 1024"] + DIV1024 = 9, + #[doc = "10: Divide clock by 2048"] + DIV2048 = 10, + #[doc = "11: Divide clock by 4096"] + DIV4096 = 11, + #[doc = "12: Divide clock by 8192"] + DIV8192 = 12, + #[doc = "13: Divide clock by 16384"] + DIV16384 = 13, + #[doc = "14: Divide clock by 32768"] + DIV32768 = 14, + #[doc = "15: Divide clock by 65536"] + DIV65536 = 15, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `PSEL` reader - Prescaler Select"] +pub struct PSEL_R(crate::FieldReader); +impl PSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PSEL_A { + match self.bits { + 0 => PSEL_A::DIV2, + 1 => PSEL_A::DIV4, + 2 => PSEL_A::DIV8, + 3 => PSEL_A::DIV16, + 4 => PSEL_A::DIV32, + 5 => PSEL_A::DIV64, + 6 => PSEL_A::DIV128, + 7 => PSEL_A::DIV256, + 8 => PSEL_A::DIV512, + 9 => PSEL_A::DIV1024, + 10 => PSEL_A::DIV2048, + 11 => PSEL_A::DIV4096, + 12 => PSEL_A::DIV8192, + 13 => PSEL_A::DIV16384, + 14 => PSEL_A::DIV32768, + 15 => PSEL_A::DIV65536, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PSEL_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PSEL_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PSEL_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PSEL_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == PSEL_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PSEL_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == PSEL_A::DIV128 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PSEL_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV512`"] + #[inline(always)] + pub fn is_div512(&self) -> bool { + **self == PSEL_A::DIV512 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PSEL_A::DIV1024 + } + #[doc = "Checks if the value of the field is `DIV2048`"] + #[inline(always)] + pub fn is_div2048(&self) -> bool { + **self == PSEL_A::DIV2048 + } + #[doc = "Checks if the value of the field is `DIV4096`"] + #[inline(always)] + pub fn is_div4096(&self) -> bool { + **self == PSEL_A::DIV4096 + } + #[doc = "Checks if the value of the field is `DIV8192`"] + #[inline(always)] + pub fn is_div8192(&self) -> bool { + **self == PSEL_A::DIV8192 + } + #[doc = "Checks if the value of the field is `DIV16384`"] + #[inline(always)] + pub fn is_div16384(&self) -> bool { + **self == PSEL_A::DIV16384 + } + #[doc = "Checks if the value of the field is `DIV32768`"] + #[inline(always)] + pub fn is_div32768(&self) -> bool { + **self == PSEL_A::DIV32768 + } + #[doc = "Checks if the value of the field is `DIV65536`"] + #[inline(always)] + pub fn is_div65536(&self) -> bool { + **self == PSEL_A::DIV65536 + } +} +impl core::ops::Deref for PSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PSEL` writer - Prescaler Select"] +pub struct PSEL_W<'a> { + w: &'a mut W, +} +impl<'a> PSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PSEL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Divide clock by 2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PSEL_A::DIV2) + } + #[doc = "Divide clock by 4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PSEL_A::DIV4) + } + #[doc = "Divide clock by 8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PSEL_A::DIV8) + } + #[doc = "Divide clock by 16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PSEL_A::DIV16) + } + #[doc = "Divide clock by 32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(PSEL_A::DIV32) + } + #[doc = "Divide clock by 64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PSEL_A::DIV64) + } + #[doc = "Divide clock by 128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(PSEL_A::DIV128) + } + #[doc = "Divide clock by 256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PSEL_A::DIV256) + } + #[doc = "Divide clock by 512"] + #[inline(always)] + pub fn div512(self) -> &'a mut W { + self.variant(PSEL_A::DIV512) + } + #[doc = "Divide clock by 1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PSEL_A::DIV1024) + } + #[doc = "Divide clock by 2048"] + #[inline(always)] + pub fn div2048(self) -> &'a mut W { + self.variant(PSEL_A::DIV2048) + } + #[doc = "Divide clock by 4096"] + #[inline(always)] + pub fn div4096(self) -> &'a mut W { + self.variant(PSEL_A::DIV4096) + } + #[doc = "Divide clock by 8192"] + #[inline(always)] + pub fn div8192(self) -> &'a mut W { + self.variant(PSEL_A::DIV8192) + } + #[doc = "Divide clock by 16384"] + #[inline(always)] + pub fn div16384(self) -> &'a mut W { + self.variant(PSEL_A::DIV16384) + } + #[doc = "Divide clock by 32768"] + #[inline(always)] + pub fn div32768(self) -> &'a mut W { + self.variant(PSEL_A::DIV32768) + } + #[doc = "Divide clock by 65536"] + #[inline(always)] + pub fn div65536(self) -> &'a mut W { + self.variant(PSEL_A::DIV65536) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 12)) | ((value as u32 & 0x0f) << 12); + self.w + } +} +#[doc = "Field `LEVEL` reader - Threshold Level"] +pub struct LEVEL_R(crate::FieldReader); +impl LEVEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LEVEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LEVEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LEVEL` writer - Threshold Level"] +pub struct LEVEL_W<'a> { + w: &'a mut W, +} +impl<'a> LEVEL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 16)) | ((value as u32 & 0x3f) << 16); + self.w + } +} +impl R { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Hysteresis Enable"] + #[inline(always)] + pub fn hyst(&self) -> HYST_R { + HYST_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 3:4 - Action when Threshold Crossed"] + #[inline(always)] + pub fn action(&self) -> ACTION_R { + ACTION_R::new(((self.bits >> 3) & 0x03) as u8) + } + #[doc = "Bit 5 - Configuration in Standby mode"] + #[inline(always)] + pub fn stdbycfg(&self) -> STDBYCFG_R { + STDBYCFG_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 8 - Configuration in Active mode"] + #[inline(always)] + pub fn actcfg(&self) -> ACTCFG_R { + ACTCFG_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bits 12:15 - Prescaler Select"] + #[inline(always)] + pub fn psel(&self) -> PSEL_R { + PSEL_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:21 - Threshold Level"] + #[inline(always)] + pub fn level(&self) -> LEVEL_R { + LEVEL_R::new(((self.bits >> 16) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - Hysteresis Enable"] + #[inline(always)] + pub fn hyst(&mut self) -> HYST_W { + HYST_W { w: self } + } + #[doc = "Bits 3:4 - Action when Threshold Crossed"] + #[inline(always)] + pub fn action(&mut self) -> ACTION_W { + ACTION_W { w: self } + } + #[doc = "Bit 5 - Configuration in Standby mode"] + #[inline(always)] + pub fn stdbycfg(&mut self) -> STDBYCFG_W { + STDBYCFG_W { w: self } + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 8 - Configuration in Active mode"] + #[inline(always)] + pub fn actcfg(&mut self) -> ACTCFG_W { + ACTCFG_W { w: self } + } + #[doc = "Bits 12:15 - Prescaler Select"] + #[inline(always)] + pub fn psel(&mut self) -> PSEL_W { + PSEL_W { w: self } + } + #[doc = "Bits 16:21 - Threshold Level"] + #[inline(always)] + pub fn level(&mut self) -> LEVEL_W { + LEVEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "BODCORE Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [bodcore](index.html) module"] +pub struct BODCORE_SPEC; +impl crate::RegisterSpec for BODCORE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [bodcore::R](R) reader structure"] +impl crate::Readable for BODCORE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [bodcore::W](W) writer structure"] +impl crate::Writable for BODCORE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BODCORE to value 0"] +impl crate::Resettable for BODCORE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/supc/bodvdd.rs b/pac/atsamc21j/src/supc/bodvdd.rs new file mode 100644 index 000000000000..f5cbfffb6453 --- /dev/null +++ b/pac/atsamc21j/src/supc/bodvdd.rs @@ -0,0 +1,705 @@ +#[doc = "Register `BODVDD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BODVDD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `HYST` reader - Hysteresis Enable"] +pub struct HYST_R(crate::FieldReader); +impl HYST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HYST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HYST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HYST` writer - Hysteresis Enable"] +pub struct HYST_W<'a> { + w: &'a mut W, +} +impl<'a> HYST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Action when Threshold Crossed\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum ACTION_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: The BODVDD generates a reset"] + RESET = 1, + #[doc = "2: The BODVDD generates an interrupt"] + INT = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: ACTION_A) -> Self { + variant as _ + } +} +#[doc = "Field `ACTION` reader - Action when Threshold Crossed"] +pub struct ACTION_R(crate::FieldReader); +impl ACTION_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ACTION_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(ACTION_A::NONE), + 1 => Some(ACTION_A::RESET), + 2 => Some(ACTION_A::INT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == ACTION_A::NONE + } + #[doc = "Checks if the value of the field is `RESET`"] + #[inline(always)] + pub fn is_reset(&self) -> bool { + **self == ACTION_A::RESET + } + #[doc = "Checks if the value of the field is `INT`"] + #[inline(always)] + pub fn is_int(&self) -> bool { + **self == ACTION_A::INT + } +} +impl core::ops::Deref for ACTION_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ACTION` writer - Action when Threshold Crossed"] +pub struct ACTION_W<'a> { + w: &'a mut W, +} +impl<'a> ACTION_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: ACTION_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(ACTION_A::NONE) + } + #[doc = "The BODVDD generates a reset"] + #[inline(always)] + pub fn reset(self) -> &'a mut W { + self.variant(ACTION_A::RESET) + } + #[doc = "The BODVDD generates an interrupt"] + #[inline(always)] + pub fn int(self) -> &'a mut W { + self.variant(ACTION_A::INT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 3)) | ((value as u32 & 0x03) << 3); + self.w + } +} +#[doc = "Field `STDBYCFG` reader - Configuration in Standby mode"] +pub struct STDBYCFG_R(crate::FieldReader); +impl STDBYCFG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STDBYCFG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STDBYCFG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STDBYCFG` writer - Configuration in Standby mode"] +pub struct STDBYCFG_W<'a> { + w: &'a mut W, +} +impl<'a> STDBYCFG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ACTCFG` reader - Configuration in Active mode"] +pub struct ACTCFG_R(crate::FieldReader); +impl ACTCFG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ACTCFG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ACTCFG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ACTCFG` writer - Configuration in Active mode"] +pub struct ACTCFG_W<'a> { + w: &'a mut W, +} +impl<'a> ACTCFG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Prescaler Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PSEL_A { + #[doc = "0: Divide clock by 2"] + DIV2 = 0, + #[doc = "1: Divide clock by 4"] + DIV4 = 1, + #[doc = "2: Divide clock by 8"] + DIV8 = 2, + #[doc = "3: Divide clock by 16"] + DIV16 = 3, + #[doc = "4: Divide clock by 32"] + DIV32 = 4, + #[doc = "5: Divide clock by 64"] + DIV64 = 5, + #[doc = "6: Divide clock by 128"] + DIV128 = 6, + #[doc = "7: Divide clock by 256"] + DIV256 = 7, + #[doc = "8: Divide clock by 512"] + DIV512 = 8, + #[doc = "9: Divide clock by 1024"] + DIV1024 = 9, + #[doc = "10: Divide clock by 2048"] + DIV2048 = 10, + #[doc = "11: Divide clock by 4096"] + DIV4096 = 11, + #[doc = "12: Divide clock by 8192"] + DIV8192 = 12, + #[doc = "13: Divide clock by 16384"] + DIV16384 = 13, + #[doc = "14: Divide clock by 32768"] + DIV32768 = 14, + #[doc = "15: Divide clock by 65536"] + DIV65536 = 15, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `PSEL` reader - Prescaler Select"] +pub struct PSEL_R(crate::FieldReader); +impl PSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PSEL_A { + match self.bits { + 0 => PSEL_A::DIV2, + 1 => PSEL_A::DIV4, + 2 => PSEL_A::DIV8, + 3 => PSEL_A::DIV16, + 4 => PSEL_A::DIV32, + 5 => PSEL_A::DIV64, + 6 => PSEL_A::DIV128, + 7 => PSEL_A::DIV256, + 8 => PSEL_A::DIV512, + 9 => PSEL_A::DIV1024, + 10 => PSEL_A::DIV2048, + 11 => PSEL_A::DIV4096, + 12 => PSEL_A::DIV8192, + 13 => PSEL_A::DIV16384, + 14 => PSEL_A::DIV32768, + 15 => PSEL_A::DIV65536, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PSEL_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PSEL_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PSEL_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PSEL_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == PSEL_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PSEL_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == PSEL_A::DIV128 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PSEL_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV512`"] + #[inline(always)] + pub fn is_div512(&self) -> bool { + **self == PSEL_A::DIV512 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PSEL_A::DIV1024 + } + #[doc = "Checks if the value of the field is `DIV2048`"] + #[inline(always)] + pub fn is_div2048(&self) -> bool { + **self == PSEL_A::DIV2048 + } + #[doc = "Checks if the value of the field is `DIV4096`"] + #[inline(always)] + pub fn is_div4096(&self) -> bool { + **self == PSEL_A::DIV4096 + } + #[doc = "Checks if the value of the field is `DIV8192`"] + #[inline(always)] + pub fn is_div8192(&self) -> bool { + **self == PSEL_A::DIV8192 + } + #[doc = "Checks if the value of the field is `DIV16384`"] + #[inline(always)] + pub fn is_div16384(&self) -> bool { + **self == PSEL_A::DIV16384 + } + #[doc = "Checks if the value of the field is `DIV32768`"] + #[inline(always)] + pub fn is_div32768(&self) -> bool { + **self == PSEL_A::DIV32768 + } + #[doc = "Checks if the value of the field is `DIV65536`"] + #[inline(always)] + pub fn is_div65536(&self) -> bool { + **self == PSEL_A::DIV65536 + } +} +impl core::ops::Deref for PSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PSEL` writer - Prescaler Select"] +pub struct PSEL_W<'a> { + w: &'a mut W, +} +impl<'a> PSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PSEL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Divide clock by 2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PSEL_A::DIV2) + } + #[doc = "Divide clock by 4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PSEL_A::DIV4) + } + #[doc = "Divide clock by 8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PSEL_A::DIV8) + } + #[doc = "Divide clock by 16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PSEL_A::DIV16) + } + #[doc = "Divide clock by 32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(PSEL_A::DIV32) + } + #[doc = "Divide clock by 64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PSEL_A::DIV64) + } + #[doc = "Divide clock by 128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(PSEL_A::DIV128) + } + #[doc = "Divide clock by 256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PSEL_A::DIV256) + } + #[doc = "Divide clock by 512"] + #[inline(always)] + pub fn div512(self) -> &'a mut W { + self.variant(PSEL_A::DIV512) + } + #[doc = "Divide clock by 1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PSEL_A::DIV1024) + } + #[doc = "Divide clock by 2048"] + #[inline(always)] + pub fn div2048(self) -> &'a mut W { + self.variant(PSEL_A::DIV2048) + } + #[doc = "Divide clock by 4096"] + #[inline(always)] + pub fn div4096(self) -> &'a mut W { + self.variant(PSEL_A::DIV4096) + } + #[doc = "Divide clock by 8192"] + #[inline(always)] + pub fn div8192(self) -> &'a mut W { + self.variant(PSEL_A::DIV8192) + } + #[doc = "Divide clock by 16384"] + #[inline(always)] + pub fn div16384(self) -> &'a mut W { + self.variant(PSEL_A::DIV16384) + } + #[doc = "Divide clock by 32768"] + #[inline(always)] + pub fn div32768(self) -> &'a mut W { + self.variant(PSEL_A::DIV32768) + } + #[doc = "Divide clock by 65536"] + #[inline(always)] + pub fn div65536(self) -> &'a mut W { + self.variant(PSEL_A::DIV65536) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 12)) | ((value as u32 & 0x0f) << 12); + self.w + } +} +#[doc = "Field `LEVEL` reader - Threshold Level for VDD"] +pub struct LEVEL_R(crate::FieldReader); +impl LEVEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LEVEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LEVEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LEVEL` writer - Threshold Level for VDD"] +pub struct LEVEL_W<'a> { + w: &'a mut W, +} +impl<'a> LEVEL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 16)) | ((value as u32 & 0x3f) << 16); + self.w + } +} +impl R { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Hysteresis Enable"] + #[inline(always)] + pub fn hyst(&self) -> HYST_R { + HYST_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 3:4 - Action when Threshold Crossed"] + #[inline(always)] + pub fn action(&self) -> ACTION_R { + ACTION_R::new(((self.bits >> 3) & 0x03) as u8) + } + #[doc = "Bit 5 - Configuration in Standby mode"] + #[inline(always)] + pub fn stdbycfg(&self) -> STDBYCFG_R { + STDBYCFG_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 8 - Configuration in Active mode"] + #[inline(always)] + pub fn actcfg(&self) -> ACTCFG_R { + ACTCFG_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bits 12:15 - Prescaler Select"] + #[inline(always)] + pub fn psel(&self) -> PSEL_R { + PSEL_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:21 - Threshold Level for VDD"] + #[inline(always)] + pub fn level(&self) -> LEVEL_R { + LEVEL_R::new(((self.bits >> 16) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - Hysteresis Enable"] + #[inline(always)] + pub fn hyst(&mut self) -> HYST_W { + HYST_W { w: self } + } + #[doc = "Bits 3:4 - Action when Threshold Crossed"] + #[inline(always)] + pub fn action(&mut self) -> ACTION_W { + ACTION_W { w: self } + } + #[doc = "Bit 5 - Configuration in Standby mode"] + #[inline(always)] + pub fn stdbycfg(&mut self) -> STDBYCFG_W { + STDBYCFG_W { w: self } + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 8 - Configuration in Active mode"] + #[inline(always)] + pub fn actcfg(&mut self) -> ACTCFG_W { + ACTCFG_W { w: self } + } + #[doc = "Bits 12:15 - Prescaler Select"] + #[inline(always)] + pub fn psel(&mut self) -> PSEL_W { + PSEL_W { w: self } + } + #[doc = "Bits 16:21 - Threshold Level for VDD"] + #[inline(always)] + pub fn level(&mut self) -> LEVEL_W { + LEVEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "BODVDD Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [bodvdd](index.html) module"] +pub struct BODVDD_SPEC; +impl crate::RegisterSpec for BODVDD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [bodvdd::R](R) reader structure"] +impl crate::Readable for BODVDD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [bodvdd::W](W) writer structure"] +impl crate::Writable for BODVDD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BODVDD to value 0"] +impl crate::Resettable for BODVDD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/supc/intenclr.rs b/pac/atsamc21j/src/supc/intenclr.rs new file mode 100644 index 000000000000..7b399544fafd --- /dev/null +++ b/pac/atsamc21j/src/supc/intenclr.rs @@ -0,0 +1,348 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BODVDDRDY` reader - BODVDD Ready"] +pub struct BODVDDRDY_R(crate::FieldReader); +impl BODVDDRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODVDDRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODVDDRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODVDDRDY` writer - BODVDD Ready"] +pub struct BODVDDRDY_W<'a> { + w: &'a mut W, +} +impl<'a> BODVDDRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `BODVDDDET` reader - BODVDD Detection"] +pub struct BODVDDDET_R(crate::FieldReader); +impl BODVDDDET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODVDDDET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODVDDDET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODVDDDET` writer - BODVDD Detection"] +pub struct BODVDDDET_W<'a> { + w: &'a mut W, +} +impl<'a> BODVDDDET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `BVDDSRDY` reader - BODVDD Synchronization Ready"] +pub struct BVDDSRDY_R(crate::FieldReader); +impl BVDDSRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BVDDSRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BVDDSRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BVDDSRDY` writer - BODVDD Synchronization Ready"] +pub struct BVDDSRDY_W<'a> { + w: &'a mut W, +} +impl<'a> BVDDSRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `BODCORERDY` reader - BODCORE Ready"] +pub struct BODCORERDY_R(crate::FieldReader); +impl BODCORERDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODCORERDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODCORERDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODCORERDY` writer - BODCORE Ready"] +pub struct BODCORERDY_W<'a> { + w: &'a mut W, +} +impl<'a> BODCORERDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `BODCOREDET` reader - BODCORE Detection"] +pub struct BODCOREDET_R(crate::FieldReader); +impl BODCOREDET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODCOREDET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODCOREDET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODCOREDET` writer - BODCORE Detection"] +pub struct BODCOREDET_W<'a> { + w: &'a mut W, +} +impl<'a> BODCOREDET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `BCORESRDY` reader - BODCORE Synchronization Ready"] +pub struct BCORESRDY_R(crate::FieldReader); +impl BCORESRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BCORESRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BCORESRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BCORESRDY` writer - BODCORE Synchronization Ready"] +pub struct BCORESRDY_W<'a> { + w: &'a mut W, +} +impl<'a> BCORESRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - BODVDD Ready"] + #[inline(always)] + pub fn bodvddrdy(&self) -> BODVDDRDY_R { + BODVDDRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - BODVDD Detection"] + #[inline(always)] + pub fn bodvdddet(&self) -> BODVDDDET_R { + BODVDDDET_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - BODVDD Synchronization Ready"] + #[inline(always)] + pub fn bvddsrdy(&self) -> BVDDSRDY_R { + BVDDSRDY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - BODCORE Ready"] + #[inline(always)] + pub fn bodcorerdy(&self) -> BODCORERDY_R { + BODCORERDY_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - BODCORE Detection"] + #[inline(always)] + pub fn bodcoredet(&self) -> BODCOREDET_R { + BODCOREDET_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - BODCORE Synchronization Ready"] + #[inline(always)] + pub fn bcoresrdy(&self) -> BCORESRDY_R { + BCORESRDY_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - BODVDD Ready"] + #[inline(always)] + pub fn bodvddrdy(&mut self) -> BODVDDRDY_W { + BODVDDRDY_W { w: self } + } + #[doc = "Bit 1 - BODVDD Detection"] + #[inline(always)] + pub fn bodvdddet(&mut self) -> BODVDDDET_W { + BODVDDDET_W { w: self } + } + #[doc = "Bit 2 - BODVDD Synchronization Ready"] + #[inline(always)] + pub fn bvddsrdy(&mut self) -> BVDDSRDY_W { + BVDDSRDY_W { w: self } + } + #[doc = "Bit 3 - BODCORE Ready"] + #[inline(always)] + pub fn bodcorerdy(&mut self) -> BODCORERDY_W { + BODCORERDY_W { w: self } + } + #[doc = "Bit 4 - BODCORE Detection"] + #[inline(always)] + pub fn bodcoredet(&mut self) -> BODCOREDET_W { + BODCOREDET_W { w: self } + } + #[doc = "Bit 5 - BODCORE Synchronization Ready"] + #[inline(always)] + pub fn bcoresrdy(&mut self) -> BCORESRDY_W { + BCORESRDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/supc/intenset.rs b/pac/atsamc21j/src/supc/intenset.rs new file mode 100644 index 000000000000..9e86a6e5b772 --- /dev/null +++ b/pac/atsamc21j/src/supc/intenset.rs @@ -0,0 +1,348 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BODVDDRDY` reader - BODVDD Ready"] +pub struct BODVDDRDY_R(crate::FieldReader); +impl BODVDDRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODVDDRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODVDDRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODVDDRDY` writer - BODVDD Ready"] +pub struct BODVDDRDY_W<'a> { + w: &'a mut W, +} +impl<'a> BODVDDRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `BODVDDDET` reader - BODVDD Detection"] +pub struct BODVDDDET_R(crate::FieldReader); +impl BODVDDDET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODVDDDET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODVDDDET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODVDDDET` writer - BODVDD Detection"] +pub struct BODVDDDET_W<'a> { + w: &'a mut W, +} +impl<'a> BODVDDDET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `BVDDSRDY` reader - BODVDD Synchronization Ready"] +pub struct BVDDSRDY_R(crate::FieldReader); +impl BVDDSRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BVDDSRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BVDDSRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BVDDSRDY` writer - BODVDD Synchronization Ready"] +pub struct BVDDSRDY_W<'a> { + w: &'a mut W, +} +impl<'a> BVDDSRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `BODCORERDY` reader - BODCORE Ready"] +pub struct BODCORERDY_R(crate::FieldReader); +impl BODCORERDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODCORERDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODCORERDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODCORERDY` writer - BODCORE Ready"] +pub struct BODCORERDY_W<'a> { + w: &'a mut W, +} +impl<'a> BODCORERDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `BODCOREDET` reader - BODCORE Detection"] +pub struct BODCOREDET_R(crate::FieldReader); +impl BODCOREDET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODCOREDET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODCOREDET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODCOREDET` writer - BODCORE Detection"] +pub struct BODCOREDET_W<'a> { + w: &'a mut W, +} +impl<'a> BODCOREDET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `BCORESRDY` reader - BODCORE Synchronization Ready"] +pub struct BCORESRDY_R(crate::FieldReader); +impl BCORESRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BCORESRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BCORESRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BCORESRDY` writer - BODCORE Synchronization Ready"] +pub struct BCORESRDY_W<'a> { + w: &'a mut W, +} +impl<'a> BCORESRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - BODVDD Ready"] + #[inline(always)] + pub fn bodvddrdy(&self) -> BODVDDRDY_R { + BODVDDRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - BODVDD Detection"] + #[inline(always)] + pub fn bodvdddet(&self) -> BODVDDDET_R { + BODVDDDET_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - BODVDD Synchronization Ready"] + #[inline(always)] + pub fn bvddsrdy(&self) -> BVDDSRDY_R { + BVDDSRDY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - BODCORE Ready"] + #[inline(always)] + pub fn bodcorerdy(&self) -> BODCORERDY_R { + BODCORERDY_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - BODCORE Detection"] + #[inline(always)] + pub fn bodcoredet(&self) -> BODCOREDET_R { + BODCOREDET_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - BODCORE Synchronization Ready"] + #[inline(always)] + pub fn bcoresrdy(&self) -> BCORESRDY_R { + BCORESRDY_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - BODVDD Ready"] + #[inline(always)] + pub fn bodvddrdy(&mut self) -> BODVDDRDY_W { + BODVDDRDY_W { w: self } + } + #[doc = "Bit 1 - BODVDD Detection"] + #[inline(always)] + pub fn bodvdddet(&mut self) -> BODVDDDET_W { + BODVDDDET_W { w: self } + } + #[doc = "Bit 2 - BODVDD Synchronization Ready"] + #[inline(always)] + pub fn bvddsrdy(&mut self) -> BVDDSRDY_W { + BVDDSRDY_W { w: self } + } + #[doc = "Bit 3 - BODCORE Ready"] + #[inline(always)] + pub fn bodcorerdy(&mut self) -> BODCORERDY_W { + BODCORERDY_W { w: self } + } + #[doc = "Bit 4 - BODCORE Detection"] + #[inline(always)] + pub fn bodcoredet(&mut self) -> BODCOREDET_W { + BODCOREDET_W { w: self } + } + #[doc = "Bit 5 - BODCORE Synchronization Ready"] + #[inline(always)] + pub fn bcoresrdy(&mut self) -> BCORESRDY_W { + BCORESRDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/supc/intflag.rs b/pac/atsamc21j/src/supc/intflag.rs new file mode 100644 index 000000000000..46b4b52add2d --- /dev/null +++ b/pac/atsamc21j/src/supc/intflag.rs @@ -0,0 +1,348 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BODVDDRDY` reader - BODVDD Ready"] +pub struct BODVDDRDY_R(crate::FieldReader); +impl BODVDDRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODVDDRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODVDDRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODVDDRDY` writer - BODVDD Ready"] +pub struct BODVDDRDY_W<'a> { + w: &'a mut W, +} +impl<'a> BODVDDRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `BODVDDDET` reader - BODVDD Detection"] +pub struct BODVDDDET_R(crate::FieldReader); +impl BODVDDDET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODVDDDET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODVDDDET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODVDDDET` writer - BODVDD Detection"] +pub struct BODVDDDET_W<'a> { + w: &'a mut W, +} +impl<'a> BODVDDDET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `BVDDSRDY` reader - BODVDD Synchronization Ready"] +pub struct BVDDSRDY_R(crate::FieldReader); +impl BVDDSRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BVDDSRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BVDDSRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BVDDSRDY` writer - BODVDD Synchronization Ready"] +pub struct BVDDSRDY_W<'a> { + w: &'a mut W, +} +impl<'a> BVDDSRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `BODCORERDY` reader - BODCORE Ready"] +pub struct BODCORERDY_R(crate::FieldReader); +impl BODCORERDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODCORERDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODCORERDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODCORERDY` writer - BODCORE Ready"] +pub struct BODCORERDY_W<'a> { + w: &'a mut W, +} +impl<'a> BODCORERDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `BODCOREDET` reader - BODCORE Detection"] +pub struct BODCOREDET_R(crate::FieldReader); +impl BODCOREDET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODCOREDET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODCOREDET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODCOREDET` writer - BODCORE Detection"] +pub struct BODCOREDET_W<'a> { + w: &'a mut W, +} +impl<'a> BODCOREDET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `BCORESRDY` reader - BODCORE Synchronization Ready"] +pub struct BCORESRDY_R(crate::FieldReader); +impl BCORESRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BCORESRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BCORESRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BCORESRDY` writer - BODCORE Synchronization Ready"] +pub struct BCORESRDY_W<'a> { + w: &'a mut W, +} +impl<'a> BCORESRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - BODVDD Ready"] + #[inline(always)] + pub fn bodvddrdy(&self) -> BODVDDRDY_R { + BODVDDRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - BODVDD Detection"] + #[inline(always)] + pub fn bodvdddet(&self) -> BODVDDDET_R { + BODVDDDET_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - BODVDD Synchronization Ready"] + #[inline(always)] + pub fn bvddsrdy(&self) -> BVDDSRDY_R { + BVDDSRDY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - BODCORE Ready"] + #[inline(always)] + pub fn bodcorerdy(&self) -> BODCORERDY_R { + BODCORERDY_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - BODCORE Detection"] + #[inline(always)] + pub fn bodcoredet(&self) -> BODCOREDET_R { + BODCOREDET_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - BODCORE Synchronization Ready"] + #[inline(always)] + pub fn bcoresrdy(&self) -> BCORESRDY_R { + BCORESRDY_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - BODVDD Ready"] + #[inline(always)] + pub fn bodvddrdy(&mut self) -> BODVDDRDY_W { + BODVDDRDY_W { w: self } + } + #[doc = "Bit 1 - BODVDD Detection"] + #[inline(always)] + pub fn bodvdddet(&mut self) -> BODVDDDET_W { + BODVDDDET_W { w: self } + } + #[doc = "Bit 2 - BODVDD Synchronization Ready"] + #[inline(always)] + pub fn bvddsrdy(&mut self) -> BVDDSRDY_W { + BVDDSRDY_W { w: self } + } + #[doc = "Bit 3 - BODCORE Ready"] + #[inline(always)] + pub fn bodcorerdy(&mut self) -> BODCORERDY_W { + BODCORERDY_W { w: self } + } + #[doc = "Bit 4 - BODCORE Detection"] + #[inline(always)] + pub fn bodcoredet(&mut self) -> BODCOREDET_W { + BODCOREDET_W { w: self } + } + #[doc = "Bit 5 - BODCORE Synchronization Ready"] + #[inline(always)] + pub fn bcoresrdy(&mut self) -> BCORESRDY_W { + BCORESRDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/supc/status.rs b/pac/atsamc21j/src/supc/status.rs new file mode 100644 index 000000000000..0fc1de3635b5 --- /dev/null +++ b/pac/atsamc21j/src/supc/status.rs @@ -0,0 +1,153 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `BODVDDRDY` reader - BODVDD Ready"] +pub struct BODVDDRDY_R(crate::FieldReader); +impl BODVDDRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODVDDRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODVDDRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODVDDDET` reader - BODVDD Detection"] +pub struct BODVDDDET_R(crate::FieldReader); +impl BODVDDDET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODVDDDET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODVDDDET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BVDDSRDY` reader - BODVDD Synchronization Ready"] +pub struct BVDDSRDY_R(crate::FieldReader); +impl BVDDSRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BVDDSRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BVDDSRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODCORERDY` reader - BODCORE Ready"] +pub struct BODCORERDY_R(crate::FieldReader); +impl BODCORERDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODCORERDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODCORERDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODCOREDET` reader - BODCORE Detection"] +pub struct BODCOREDET_R(crate::FieldReader); +impl BODCOREDET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODCOREDET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODCOREDET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BCORESRDY` reader - BODCORE Synchronization Ready"] +pub struct BCORESRDY_R(crate::FieldReader); +impl BCORESRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BCORESRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BCORESRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - BODVDD Ready"] + #[inline(always)] + pub fn bodvddrdy(&self) -> BODVDDRDY_R { + BODVDDRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - BODVDD Detection"] + #[inline(always)] + pub fn bodvdddet(&self) -> BODVDDDET_R { + BODVDDDET_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - BODVDD Synchronization Ready"] + #[inline(always)] + pub fn bvddsrdy(&self) -> BVDDSRDY_R { + BVDDSRDY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - BODCORE Ready"] + #[inline(always)] + pub fn bodcorerdy(&self) -> BODCORERDY_R { + BODCORERDY_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - BODCORE Detection"] + #[inline(always)] + pub fn bodcoredet(&self) -> BODCOREDET_R { + BODCOREDET_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - BODCORE Synchronization Ready"] + #[inline(always)] + pub fn bcoresrdy(&self) -> BCORESRDY_R { + BCORESRDY_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +#[doc = "Power and Clocks Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/supc/vref.rs b/pac/atsamc21j/src/supc/vref.rs new file mode 100644 index 000000000000..2d5b1381885e --- /dev/null +++ b/pac/atsamc21j/src/supc/vref.rs @@ -0,0 +1,353 @@ +#[doc = "Register `VREF` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `VREF` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TSEN` reader - Temperature Sensor Output Enable"] +pub struct TSEN_R(crate::FieldReader); +impl TSEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSEN` writer - Temperature Sensor Output Enable"] +pub struct TSEN_W<'a> { + w: &'a mut W, +} +impl<'a> TSEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `VREFOE` reader - Voltage Reference Output Enable"] +pub struct VREFOE_R(crate::FieldReader); +impl VREFOE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + VREFOE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VREFOE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VREFOE` writer - Voltage Reference Output Enable"] +pub struct VREFOE_W<'a> { + w: &'a mut W, +} +impl<'a> VREFOE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - On Demand Contrl"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - On Demand Contrl"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Voltage Reference Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SEL_A { + #[doc = "0: 1.024V voltage reference typical value"] + _1V024 = 0, + #[doc = "2: 2.048V voltage reference typical value"] + _2V048 = 2, + #[doc = "3: 4.096V voltage reference typical value"] + _4V096 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `SEL` reader - Voltage Reference Selection"] +pub struct SEL_R(crate::FieldReader); +impl SEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEL_A::_1V024), + 2 => Some(SEL_A::_2V048), + 3 => Some(SEL_A::_4V096), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_1V024`"] + #[inline(always)] + pub fn is_1v024(&self) -> bool { + **self == SEL_A::_1V024 + } + #[doc = "Checks if the value of the field is `_2V048`"] + #[inline(always)] + pub fn is_2v048(&self) -> bool { + **self == SEL_A::_2V048 + } + #[doc = "Checks if the value of the field is `_4V096`"] + #[inline(always)] + pub fn is_4v096(&self) -> bool { + **self == SEL_A::_4V096 + } +} +impl core::ops::Deref for SEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEL` writer - Voltage Reference Selection"] +pub struct SEL_W<'a> { + w: &'a mut W, +} +impl<'a> SEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SEL_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "1.024V voltage reference typical value"] + #[inline(always)] + pub fn _1v024(self) -> &'a mut W { + self.variant(SEL_A::_1V024) + } + #[doc = "2.048V voltage reference typical value"] + #[inline(always)] + pub fn _2v048(self) -> &'a mut W { + self.variant(SEL_A::_2V048) + } + #[doc = "4.096V voltage reference typical value"] + #[inline(always)] + pub fn _4v096(self) -> &'a mut W { + self.variant(SEL_A::_4V096) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 16)) | ((value as u32 & 0x0f) << 16); + self.w + } +} +impl R { + #[doc = "Bit 1 - Temperature Sensor Output Enable"] + #[inline(always)] + pub fn tsen(&self) -> TSEN_R { + TSEN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Voltage Reference Output Enable"] + #[inline(always)] + pub fn vrefoe(&self) -> VREFOE_R { + VREFOE_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - On Demand Contrl"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 16:19 - Voltage Reference Selection"] + #[inline(always)] + pub fn sel(&self) -> SEL_R { + SEL_R::new(((self.bits >> 16) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bit 1 - Temperature Sensor Output Enable"] + #[inline(always)] + pub fn tsen(&mut self) -> TSEN_W { + TSEN_W { w: self } + } + #[doc = "Bit 2 - Voltage Reference Output Enable"] + #[inline(always)] + pub fn vrefoe(&mut self) -> VREFOE_W { + VREFOE_W { w: self } + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - On Demand Contrl"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Bits 16:19 - Voltage Reference Selection"] + #[inline(always)] + pub fn sel(&mut self) -> SEL_W { + SEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "VREF Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [vref](index.html) module"] +pub struct VREF_SPEC; +impl crate::RegisterSpec for VREF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [vref::R](R) reader structure"] +impl crate::Readable for VREF_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [vref::W](W) writer structure"] +impl crate::Writable for VREF_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets VREF to value 0"] +impl crate::Resettable for VREF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/supc/vreg.rs b/pac/atsamc21j/src/supc/vreg.rs new file mode 100644 index 000000000000..fb5b12a185cf --- /dev/null +++ b/pac/atsamc21j/src/supc/vreg.rs @@ -0,0 +1,160 @@ +#[doc = "Register `VREG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `VREG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "VREG Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [vreg](index.html) module"] +pub struct VREG_SPEC; +impl crate::RegisterSpec for VREG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [vreg::R](R) reader structure"] +impl crate::Readable for VREG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [vreg::W](W) writer structure"] +impl crate::Writable for VREG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets VREG to value 0"] +impl crate::Resettable for VREG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sys_tick.rs b/pac/atsamc21j/src/sys_tick.rs new file mode 100644 index 000000000000..b0fe7a59e5ed --- /dev/null +++ b/pac/atsamc21j/src/sys_tick.rs @@ -0,0 +1,28 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - SysTick Control and Status Register"] + pub csr: crate::Reg, + #[doc = "0x04 - SysTick Reload Value Register"] + pub rvr: crate::Reg, + #[doc = "0x08 - SysTick Current Value Register"] + pub cvr: crate::Reg, + #[doc = "0x0c - SysTick Calibration Value Register"] + pub calib: crate::Reg, +} +#[doc = "CSR register accessor: an alias for `Reg`"] +pub type CSR = crate::Reg; +#[doc = "SysTick Control and Status Register"] +pub mod csr; +#[doc = "RVR register accessor: an alias for `Reg`"] +pub type RVR = crate::Reg; +#[doc = "SysTick Reload Value Register"] +pub mod rvr; +#[doc = "CVR register accessor: an alias for `Reg`"] +pub type CVR = crate::Reg; +#[doc = "SysTick Current Value Register"] +pub mod cvr; +#[doc = "CALIB register accessor: an alias for `Reg`"] +pub type CALIB = crate::Reg; +#[doc = "SysTick Calibration Value Register"] +pub mod calib; diff --git a/pac/atsamc21j/src/sys_tick/calib.rs b/pac/atsamc21j/src/sys_tick/calib.rs new file mode 100644 index 000000000000..df7fd80f773a --- /dev/null +++ b/pac/atsamc21j/src/sys_tick/calib.rs @@ -0,0 +1,157 @@ +#[doc = "Register `CALIB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `TENMS` reader - Reload value to use for 10ms timing"] +pub struct TENMS_R(crate::FieldReader); +impl TENMS_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + TENMS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TENMS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "TENMS is rounded from non-integer ratio\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SKEW_A { + #[doc = "0: 10ms calibration value is exact"] + VALUE_0 = 0, + #[doc = "1: 10ms calibration value is inexact, because of the clock frequency"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SKEW_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SKEW` reader - TENMS is rounded from non-integer ratio"] +pub struct SKEW_R(crate::FieldReader); +impl SKEW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SKEW_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SKEW_A { + match self.bits { + false => SKEW_A::VALUE_0, + true => SKEW_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == SKEW_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == SKEW_A::VALUE_1 + } +} +impl core::ops::Deref for SKEW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "No Separate Reference Clock\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum NOREF_A { + #[doc = "0: The reference clock is provided"] + VALUE_0 = 0, + #[doc = "1: The reference clock is not provided"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NOREF_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NOREF` reader - No Separate Reference Clock"] +pub struct NOREF_R(crate::FieldReader); +impl NOREF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NOREF_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> NOREF_A { + match self.bits { + false => NOREF_A::VALUE_0, + true => NOREF_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == NOREF_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == NOREF_A::VALUE_1 + } +} +impl core::ops::Deref for NOREF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:23 - Reload value to use for 10ms timing"] + #[inline(always)] + pub fn tenms(&self) -> TENMS_R { + TENMS_R::new((self.bits & 0x00ff_ffff) as u32) + } + #[doc = "Bit 30 - TENMS is rounded from non-integer ratio"] + #[inline(always)] + pub fn skew(&self) -> SKEW_R { + SKEW_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 31 - No Separate Reference Clock"] + #[inline(always)] + pub fn noref(&self) -> NOREF_R { + NOREF_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +#[doc = "SysTick Calibration Value Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [calib](index.html) module"] +pub struct CALIB_SPEC; +impl crate::RegisterSpec for CALIB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [calib::R](R) reader structure"] +impl crate::Readable for CALIB_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CALIB to value 0"] +impl crate::Resettable for CALIB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sys_tick/csr.rs b/pac/atsamc21j/src/sys_tick/csr.rs new file mode 100644 index 000000000000..872d637f5a86 --- /dev/null +++ b/pac/atsamc21j/src/sys_tick/csr.rs @@ -0,0 +1,395 @@ +#[doc = "Register `CSR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CSR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "SysTick Counter Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ENABLE_A { + #[doc = "0: Counter disabled"] + VALUE_0 = 0, + #[doc = "1: Counter enabled"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ENABLE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ENABLE` reader - SysTick Counter Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ENABLE_A { + match self.bits { + false => ENABLE_A::VALUE_0, + true => ENABLE_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == ENABLE_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == ENABLE_A::VALUE_1 + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - SysTick Counter Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: ENABLE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Counter disabled"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(ENABLE_A::VALUE_0) + } + #[doc = "Counter enabled"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(ENABLE_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "SysTick Exception Request Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TICKINT_A { + #[doc = "0: Counting down to 0 does not assert the SysTick exception request"] + VALUE_0 = 0, + #[doc = "1: Counting down to 0 asserts the SysTick exception request"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TICKINT_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TICKINT` reader - SysTick Exception Request Enable"] +pub struct TICKINT_R(crate::FieldReader); +impl TICKINT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TICKINT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TICKINT_A { + match self.bits { + false => TICKINT_A::VALUE_0, + true => TICKINT_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == TICKINT_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == TICKINT_A::VALUE_1 + } +} +impl core::ops::Deref for TICKINT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TICKINT` writer - SysTick Exception Request Enable"] +pub struct TICKINT_W<'a> { + w: &'a mut W, +} +impl<'a> TICKINT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TICKINT_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Counting down to 0 does not assert the SysTick exception request"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(TICKINT_A::VALUE_0) + } + #[doc = "Counting down to 0 asserts the SysTick exception request"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(TICKINT_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Clock Source 0=external, 1=processor\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CLKSOURCE_A { + #[doc = "0: External clock"] + VALUE_0 = 0, + #[doc = "1: Processor clock"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CLKSOURCE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CLKSOURCE` reader - Clock Source 0=external, 1=processor"] +pub struct CLKSOURCE_R(crate::FieldReader); +impl CLKSOURCE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKSOURCE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CLKSOURCE_A { + match self.bits { + false => CLKSOURCE_A::VALUE_0, + true => CLKSOURCE_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == CLKSOURCE_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == CLKSOURCE_A::VALUE_1 + } +} +impl core::ops::Deref for CLKSOURCE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKSOURCE` writer - Clock Source 0=external, 1=processor"] +pub struct CLKSOURCE_W<'a> { + w: &'a mut W, +} +impl<'a> CLKSOURCE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CLKSOURCE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "External clock"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(CLKSOURCE_A::VALUE_0) + } + #[doc = "Processor clock"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(CLKSOURCE_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `COUNTFLAG` reader - Timer counted to 0 since last read of register"] +pub struct COUNTFLAG_R(crate::FieldReader); +impl COUNTFLAG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNTFLAG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNTFLAG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNTFLAG` writer - Timer counted to 0 since last read of register"] +pub struct COUNTFLAG_W<'a> { + w: &'a mut W, +} +impl<'a> COUNTFLAG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +impl R { + #[doc = "Bit 0 - SysTick Counter Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SysTick Exception Request Enable"] + #[inline(always)] + pub fn tickint(&self) -> TICKINT_R { + TICKINT_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Clock Source 0=external, 1=processor"] + #[inline(always)] + pub fn clksource(&self) -> CLKSOURCE_R { + CLKSOURCE_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 16 - Timer counted to 0 since last read of register"] + #[inline(always)] + pub fn countflag(&self) -> COUNTFLAG_R { + COUNTFLAG_R::new(((self.bits >> 16) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - SysTick Counter Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 1 - SysTick Exception Request Enable"] + #[inline(always)] + pub fn tickint(&mut self) -> TICKINT_W { + TICKINT_W { w: self } + } + #[doc = "Bit 2 - Clock Source 0=external, 1=processor"] + #[inline(always)] + pub fn clksource(&mut self) -> CLKSOURCE_W { + CLKSOURCE_W { w: self } + } + #[doc = "Bit 16 - Timer counted to 0 since last read of register"] + #[inline(always)] + pub fn countflag(&mut self) -> COUNTFLAG_W { + COUNTFLAG_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SysTick Control and Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [csr](index.html) module"] +pub struct CSR_SPEC; +impl crate::RegisterSpec for CSR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [csr::R](R) reader structure"] +impl crate::Readable for CSR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [csr::W](W) writer structure"] +impl crate::Writable for CSR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CSR to value 0x04"] +impl crate::Resettable for CSR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x04 + } +} diff --git a/pac/atsamc21j/src/sys_tick/cvr.rs b/pac/atsamc21j/src/sys_tick/cvr.rs new file mode 100644 index 000000000000..8a40b5f43b3a --- /dev/null +++ b/pac/atsamc21j/src/sys_tick/cvr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `CVR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CVR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CURRENT` reader - Current value at the time the register is accessed"] +pub struct CURRENT_R(crate::FieldReader); +impl CURRENT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CURRENT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CURRENT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CURRENT` writer - Current value at the time the register is accessed"] +pub struct CURRENT_W<'a> { + w: &'a mut W, +} +impl<'a> CURRENT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Current value at the time the register is accessed"] + #[inline(always)] + pub fn current(&self) -> CURRENT_R { + CURRENT_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Current value at the time the register is accessed"] + #[inline(always)] + pub fn current(&mut self) -> CURRENT_W { + CURRENT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SysTick Current Value Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cvr](index.html) module"] +pub struct CVR_SPEC; +impl crate::RegisterSpec for CVR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cvr::R](R) reader structure"] +impl crate::Readable for CVR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cvr::W](W) writer structure"] +impl crate::Writable for CVR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CVR to value 0"] +impl crate::Resettable for CVR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/sys_tick/rvr.rs b/pac/atsamc21j/src/sys_tick/rvr.rs new file mode 100644 index 000000000000..ac023ff75f36 --- /dev/null +++ b/pac/atsamc21j/src/sys_tick/rvr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `RVR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RVR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RELOAD` reader - Value to load into the SysTick Current Value Register when the counter reaches 0"] +pub struct RELOAD_R(crate::FieldReader); +impl RELOAD_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + RELOAD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RELOAD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RELOAD` writer - Value to load into the SysTick Current Value Register when the counter reaches 0"] +pub struct RELOAD_W<'a> { + w: &'a mut W, +} +impl<'a> RELOAD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Value to load into the SysTick Current Value Register when the counter reaches 0"] + #[inline(always)] + pub fn reload(&self) -> RELOAD_R { + RELOAD_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Value to load into the SysTick Current Value Register when the counter reaches 0"] + #[inline(always)] + pub fn reload(&mut self) -> RELOAD_W { + RELOAD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SysTick Reload Value Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rvr](index.html) module"] +pub struct RVR_SPEC; +impl crate::RegisterSpec for RVR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rvr::R](R) reader structure"] +impl crate::Readable for RVR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rvr::W](W) writer structure"] +impl crate::Writable for RVR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RVR to value 0"] +impl crate::Resettable for RVR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/system_control.rs b/pac/atsamc21j/src/system_control.rs new file mode 100644 index 000000000000..4894b22b258f --- /dev/null +++ b/pac/atsamc21j/src/system_control.rs @@ -0,0 +1,67 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved0: [u8; 0x0d00], + #[doc = "0xd00 - CPUID Base Register"] + pub cpuid: crate::Reg, + #[doc = "0xd04 - Interrupt Control and State Register"] + pub icsr: crate::Reg, + #[doc = "0xd08 - Vector Table Offset Register"] + pub vtor: crate::Reg, + #[doc = "0xd0c - Application Interrupt and Reset Control Register"] + pub aircr: crate::Reg, + #[doc = "0xd10 - System Control Register"] + pub scr: crate::Reg, + #[doc = "0xd14 - Configuration and Control Register"] + pub ccr: crate::Reg, + _reserved6: [u8; 0x04], + #[doc = "0xd1c - System Handler Priority Register 2"] + pub shpr2: crate::Reg, + #[doc = "0xd20 - System Handler Priority Register 3"] + pub shpr3: crate::Reg, + #[doc = "0xd24 - System Handler Control and State Register"] + pub shcsr: crate::Reg, + _reserved9: [u8; 0x08], + #[doc = "0xd30 - Debug Fault Status Register"] + pub dfsr: crate::Reg, +} +#[doc = "CPUID register accessor: an alias for `Reg`"] +pub type CPUID = crate::Reg; +#[doc = "CPUID Base Register"] +pub mod cpuid; +#[doc = "ICSR register accessor: an alias for `Reg`"] +pub type ICSR = crate::Reg; +#[doc = "Interrupt Control and State Register"] +pub mod icsr; +#[doc = "VTOR register accessor: an alias for `Reg`"] +pub type VTOR = crate::Reg; +#[doc = "Vector Table Offset Register"] +pub mod vtor; +#[doc = "AIRCR register accessor: an alias for `Reg`"] +pub type AIRCR = crate::Reg; +#[doc = "Application Interrupt and Reset Control Register"] +pub mod aircr; +#[doc = "SCR register accessor: an alias for `Reg`"] +pub type SCR = crate::Reg; +#[doc = "System Control Register"] +pub mod scr; +#[doc = "CCR register accessor: an alias for `Reg`"] +pub type CCR = crate::Reg; +#[doc = "Configuration and Control Register"] +pub mod ccr; +#[doc = "SHPR2 register accessor: an alias for `Reg`"] +pub type SHPR2 = crate::Reg; +#[doc = "System Handler Priority Register 2"] +pub mod shpr2; +#[doc = "SHPR3 register accessor: an alias for `Reg`"] +pub type SHPR3 = crate::Reg; +#[doc = "System Handler Priority Register 3"] +pub mod shpr3; +#[doc = "SHCSR register accessor: an alias for `Reg`"] +pub type SHCSR = crate::Reg; +#[doc = "System Handler Control and State Register"] +pub mod shcsr; +#[doc = "DFSR register accessor: an alias for `Reg`"] +pub type DFSR = crate::Reg; +#[doc = "Debug Fault Status Register"] +pub mod dfsr; diff --git a/pac/atsamc21j/src/system_control/aircr.rs b/pac/atsamc21j/src/system_control/aircr.rs new file mode 100644 index 000000000000..9453cc6f30bc --- /dev/null +++ b/pac/atsamc21j/src/system_control/aircr.rs @@ -0,0 +1,338 @@ +#[doc = "Register `AIRCR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `AIRCR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `VECTCLRACTIVE` reader - Debug: Clear state information"] +pub struct VECTCLRACTIVE_R(crate::FieldReader); +impl VECTCLRACTIVE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + VECTCLRACTIVE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VECTCLRACTIVE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VECTCLRACTIVE` writer - Debug: Clear state information"] +pub struct VECTCLRACTIVE_W<'a> { + w: &'a mut W, +} +impl<'a> VECTCLRACTIVE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "System Reset Request\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SYSRESETREQ_A { + #[doc = "0: No system reset request"] + VALUE_0 = 0, + #[doc = "1: Asserts a signal to the outer system that requests a reset"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SYSRESETREQ_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SYSRESETREQ` reader - System Reset Request"] +pub struct SYSRESETREQ_R(crate::FieldReader); +impl SYSRESETREQ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYSRESETREQ_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SYSRESETREQ_A { + match self.bits { + false => SYSRESETREQ_A::VALUE_0, + true => SYSRESETREQ_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == SYSRESETREQ_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == SYSRESETREQ_A::VALUE_1 + } +} +impl core::ops::Deref for SYSRESETREQ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYSRESETREQ` writer - System Reset Request"] +pub struct SYSRESETREQ_W<'a> { + w: &'a mut W, +} +impl<'a> SYSRESETREQ_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SYSRESETREQ_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "No system reset request"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(SYSRESETREQ_A::VALUE_0) + } + #[doc = "Asserts a signal to the outer system that requests a reset"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(SYSRESETREQ_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Data Endianness, 0=little, 1=big\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ENDIANNESS_A { + #[doc = "0: Little-endian"] + VALUE_0 = 0, + #[doc = "1: Big-endian"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ENDIANNESS_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ENDIANNESS` reader - Data Endianness, 0=little, 1=big"] +pub struct ENDIANNESS_R(crate::FieldReader); +impl ENDIANNESS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENDIANNESS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ENDIANNESS_A { + match self.bits { + false => ENDIANNESS_A::VALUE_0, + true => ENDIANNESS_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == ENDIANNESS_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == ENDIANNESS_A::VALUE_1 + } +} +impl core::ops::Deref for ENDIANNESS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENDIANNESS` writer - Data Endianness, 0=little, 1=big"] +pub struct ENDIANNESS_W<'a> { + w: &'a mut W, +} +impl<'a> ENDIANNESS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: ENDIANNESS_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Little-endian"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(ENDIANNESS_A::VALUE_0) + } + #[doc = "Big-endian"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(ENDIANNESS_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `VECTKEY` reader - Register key (0x05FA)"] +pub struct VECTKEY_R(crate::FieldReader); +impl VECTKEY_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + VECTKEY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VECTKEY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VECTKEY` writer - Register key (0x05FA)"] +pub struct VECTKEY_W<'a> { + w: &'a mut W, +} +impl<'a> VECTKEY_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xffff << 16)) | ((value as u32 & 0xffff) << 16); + self.w + } +} +impl R { + #[doc = "Bit 1 - Debug: Clear state information"] + #[inline(always)] + pub fn vectclractive(&self) -> VECTCLRACTIVE_R { + VECTCLRACTIVE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - System Reset Request"] + #[inline(always)] + pub fn sysresetreq(&self) -> SYSRESETREQ_R { + SYSRESETREQ_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 15 - Data Endianness, 0=little, 1=big"] + #[inline(always)] + pub fn endianness(&self) -> ENDIANNESS_R { + ENDIANNESS_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:31 - Register key (0x05FA)"] + #[inline(always)] + pub fn vectkey(&self) -> VECTKEY_R { + VECTKEY_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bit 1 - Debug: Clear state information"] + #[inline(always)] + pub fn vectclractive(&mut self) -> VECTCLRACTIVE_W { + VECTCLRACTIVE_W { w: self } + } + #[doc = "Bit 2 - System Reset Request"] + #[inline(always)] + pub fn sysresetreq(&mut self) -> SYSRESETREQ_W { + SYSRESETREQ_W { w: self } + } + #[doc = "Bit 15 - Data Endianness, 0=little, 1=big"] + #[inline(always)] + pub fn endianness(&mut self) -> ENDIANNESS_W { + ENDIANNESS_W { w: self } + } + #[doc = "Bits 16:31 - Register key (0x05FA)"] + #[inline(always)] + pub fn vectkey(&mut self) -> VECTKEY_W { + VECTKEY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Application Interrupt and Reset Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [aircr](index.html) module"] +pub struct AIRCR_SPEC; +impl crate::RegisterSpec for AIRCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [aircr::R](R) reader structure"] +impl crate::Readable for AIRCR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [aircr::W](W) writer structure"] +impl crate::Writable for AIRCR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets AIRCR to value 0"] +impl crate::Resettable for AIRCR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/system_control/ccr.rs b/pac/atsamc21j/src/system_control/ccr.rs new file mode 100644 index 000000000000..62516a7b60c8 --- /dev/null +++ b/pac/atsamc21j/src/system_control/ccr.rs @@ -0,0 +1,137 @@ +#[doc = "Register `CCR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Unaligned accesses generates a Hard Fault\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum UNALIGN_TRP_A { + #[doc = "0: Do not trap unaligned halfword and word accesses"] + VALUE_0 = 0, + #[doc = "1: Trap unaligned halfword and word accesses"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: UNALIGN_TRP_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `UNALIGN_TRP` reader - Unaligned accesses generates a Hard Fault"] +pub struct UNALIGN_TRP_R(crate::FieldReader); +impl UNALIGN_TRP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UNALIGN_TRP_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> UNALIGN_TRP_A { + match self.bits { + false => UNALIGN_TRP_A::VALUE_0, + true => UNALIGN_TRP_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == UNALIGN_TRP_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == UNALIGN_TRP_A::VALUE_1 + } +} +impl core::ops::Deref for UNALIGN_TRP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Stack 8-byte aligned on exception entry\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum STKALIGN_A { + #[doc = "0: 4-byte aligned"] + VALUE_0 = 0, + #[doc = "1: 8-byte aligned"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: STKALIGN_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STKALIGN` reader - Stack 8-byte aligned on exception entry"] +pub struct STKALIGN_R(crate::FieldReader); +impl STKALIGN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STKALIGN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STKALIGN_A { + match self.bits { + false => STKALIGN_A::VALUE_0, + true => STKALIGN_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == STKALIGN_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == STKALIGN_A::VALUE_1 + } +} +impl core::ops::Deref for STKALIGN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 3 - Unaligned accesses generates a Hard Fault"] + #[inline(always)] + pub fn unalign_trp(&self) -> UNALIGN_TRP_R { + UNALIGN_TRP_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 9 - Stack 8-byte aligned on exception entry"] + #[inline(always)] + pub fn stkalign(&self) -> STKALIGN_R { + STKALIGN_R::new(((self.bits >> 9) & 0x01) != 0) + } +} +#[doc = "Configuration and Control Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccr](index.html) module"] +pub struct CCR_SPEC; +impl crate::RegisterSpec for CCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ccr::R](R) reader structure"] +impl crate::Readable for CCR_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CCR to value 0x0204"] +impl crate::Resettable for CCR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0204 + } +} diff --git a/pac/atsamc21j/src/system_control/cpuid.rs b/pac/atsamc21j/src/system_control/cpuid.rs new file mode 100644 index 000000000000..4157d7a94e97 --- /dev/null +++ b/pac/atsamc21j/src/system_control/cpuid.rs @@ -0,0 +1,133 @@ +#[doc = "Register `CPUID` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `REVISION` reader - Minor revision number"] +pub struct REVISION_R(crate::FieldReader); +impl REVISION_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REVISION_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REVISION_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PARTNO` reader - Processor Part Number, 0xC60=Cortex-M0+"] +pub struct PARTNO_R(crate::FieldReader); +impl PARTNO_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + PARTNO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PARTNO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ARCHITECTURE` reader - Processor Architecture, 0xC=ARMv6-M"] +pub struct ARCHITECTURE_R(crate::FieldReader); +impl ARCHITECTURE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ARCHITECTURE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ARCHITECTURE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VARIANT` reader - Major revision number"] +pub struct VARIANT_R(crate::FieldReader); +impl VARIANT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + VARIANT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VARIANT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IMPLEMENTER` reader - Implementer code, ARM=0x41"] +pub struct IMPLEMENTER_R(crate::FieldReader); +impl IMPLEMENTER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + IMPLEMENTER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IMPLEMENTER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:3 - Minor revision number"] + #[inline(always)] + pub fn revision(&self) -> REVISION_R { + REVISION_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:15 - Processor Part Number, 0xC60=Cortex-M0+"] + #[inline(always)] + pub fn partno(&self) -> PARTNO_R { + PARTNO_R::new(((self.bits >> 4) & 0x0fff) as u16) + } + #[doc = "Bits 16:19 - Processor Architecture, 0xC=ARMv6-M"] + #[inline(always)] + pub fn architecture(&self) -> ARCHITECTURE_R { + ARCHITECTURE_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bits 20:23 - Major revision number"] + #[inline(always)] + pub fn variant(&self) -> VARIANT_R { + VARIANT_R::new(((self.bits >> 20) & 0x0f) as u8) + } + #[doc = "Bits 24:31 - Implementer code, ARM=0x41"] + #[inline(always)] + pub fn implementer(&self) -> IMPLEMENTER_R { + IMPLEMENTER_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[doc = "CPUID Base Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cpuid](index.html) module"] +pub struct CPUID_SPEC; +impl crate::RegisterSpec for CPUID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cpuid::R](R) reader structure"] +impl crate::Readable for CPUID_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CPUID to value 0x410c_c601"] +impl crate::Resettable for CPUID_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x410c_c601 + } +} diff --git a/pac/atsamc21j/src/system_control/dfsr.rs b/pac/atsamc21j/src/system_control/dfsr.rs new file mode 100644 index 000000000000..948899af0905 --- /dev/null +++ b/pac/atsamc21j/src/system_control/dfsr.rs @@ -0,0 +1,301 @@ +#[doc = "Register `DFSR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DFSR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `HALTED` reader - Halt request debug event active"] +pub struct HALTED_R(crate::FieldReader); +impl HALTED_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HALTED_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HALTED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HALTED` writer - Halt request debug event active"] +pub struct HALTED_W<'a> { + w: &'a mut W, +} +impl<'a> HALTED_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `BKPT` reader - Breakpoint debug event"] +pub struct BKPT_R(crate::FieldReader); +impl BKPT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BKPT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BKPT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BKPT` writer - Breakpoint debug event"] +pub struct BKPT_W<'a> { + w: &'a mut W, +} +impl<'a> BKPT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `DWTTRAP` reader - DWT debug event"] +pub struct DWTTRAP_R(crate::FieldReader); +impl DWTTRAP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DWTTRAP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DWTTRAP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DWTTRAP` writer - DWT debug event"] +pub struct DWTTRAP_W<'a> { + w: &'a mut W, +} +impl<'a> DWTTRAP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `VCATCH` reader - Vector catch debug event"] +pub struct VCATCH_R(crate::FieldReader); +impl VCATCH_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + VCATCH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VCATCH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VCATCH` writer - Vector catch debug event"] +pub struct VCATCH_W<'a> { + w: &'a mut W, +} +impl<'a> VCATCH_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `EXTERNAL` reader - EDBGRQ debug event"] +pub struct EXTERNAL_R(crate::FieldReader); +impl EXTERNAL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTERNAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTERNAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTERNAL` writer - EDBGRQ debug event"] +pub struct EXTERNAL_W<'a> { + w: &'a mut W, +} +impl<'a> EXTERNAL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +impl R { + #[doc = "Bit 0 - Halt request debug event active"] + #[inline(always)] + pub fn halted(&self) -> HALTED_R { + HALTED_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Breakpoint debug event"] + #[inline(always)] + pub fn bkpt(&self) -> BKPT_R { + BKPT_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - DWT debug event"] + #[inline(always)] + pub fn dwttrap(&self) -> DWTTRAP_R { + DWTTRAP_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Vector catch debug event"] + #[inline(always)] + pub fn vcatch(&self) -> VCATCH_R { + VCATCH_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - EDBGRQ debug event"] + #[inline(always)] + pub fn external(&self) -> EXTERNAL_R { + EXTERNAL_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Halt request debug event active"] + #[inline(always)] + pub fn halted(&mut self) -> HALTED_W { + HALTED_W { w: self } + } + #[doc = "Bit 1 - Breakpoint debug event"] + #[inline(always)] + pub fn bkpt(&mut self) -> BKPT_W { + BKPT_W { w: self } + } + #[doc = "Bit 2 - DWT debug event"] + #[inline(always)] + pub fn dwttrap(&mut self) -> DWTTRAP_W { + DWTTRAP_W { w: self } + } + #[doc = "Bit 3 - Vector catch debug event"] + #[inline(always)] + pub fn vcatch(&mut self) -> VCATCH_W { + VCATCH_W { w: self } + } + #[doc = "Bit 4 - EDBGRQ debug event"] + #[inline(always)] + pub fn external(&mut self) -> EXTERNAL_W { + EXTERNAL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Fault Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dfsr](index.html) module"] +pub struct DFSR_SPEC; +impl crate::RegisterSpec for DFSR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dfsr::R](R) reader structure"] +impl crate::Readable for DFSR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dfsr::W](W) writer structure"] +impl crate::Writable for DFSR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DFSR to value 0"] +impl crate::Resettable for DFSR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/system_control/icsr.rs b/pac/atsamc21j/src/system_control/icsr.rs new file mode 100644 index 000000000000..7fe5fd412116 --- /dev/null +++ b/pac/atsamc21j/src/system_control/icsr.rs @@ -0,0 +1,704 @@ +#[doc = "Register `ICSR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ICSR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `VECTACTIVE` reader - Debug: Exception number of currently executing exception, or 0 if thread mode"] +pub struct VECTACTIVE_R(crate::FieldReader); +impl VECTACTIVE_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + VECTACTIVE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VECTACTIVE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VECTACTIVE` writer - Debug: Exception number of currently executing exception, or 0 if thread mode"] +pub struct VECTACTIVE_W<'a> { + w: &'a mut W, +} +impl<'a> VECTACTIVE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01ff) | (value as u32 & 0x01ff); + self.w + } +} +#[doc = "Field `VECTPENDING` reader - Exception number of the highest priority pending enabled exception"] +pub struct VECTPENDING_R(crate::FieldReader); +impl VECTPENDING_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + VECTPENDING_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VECTPENDING_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VECTPENDING` writer - Exception number of the highest priority pending enabled exception"] +pub struct VECTPENDING_W<'a> { + w: &'a mut W, +} +impl<'a> VECTPENDING_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01ff << 12)) | ((value as u32 & 0x01ff) << 12); + self.w + } +} +#[doc = "Field `ISRPENDING` reader - Debug: NVIC interrupt pending"] +pub struct ISRPENDING_R(crate::FieldReader); +impl ISRPENDING_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ISRPENDING_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ISRPENDING_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ISRPENDING` writer - Debug: NVIC interrupt pending"] +pub struct ISRPENDING_W<'a> { + w: &'a mut W, +} +impl<'a> ISRPENDING_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `ISRPREEMPT` reader - Debug: Pending exception serviced on exit from debug halt"] +pub struct ISRPREEMPT_R(crate::FieldReader); +impl ISRPREEMPT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ISRPREEMPT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ISRPREEMPT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ISRPREEMPT` writer - Debug: Pending exception serviced on exit from debug halt"] +pub struct ISRPREEMPT_W<'a> { + w: &'a mut W, +} +impl<'a> ISRPREEMPT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "SysTick exception clear-pending bit\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PENDSTCLR_A { + #[doc = "0: No effect"] + VALUE_0 = 0, + #[doc = "1: Removes the pending state from the SysTick exception"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PENDSTCLR_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PENDSTCLR` reader - SysTick exception clear-pending bit"] +pub struct PENDSTCLR_R(crate::FieldReader); +impl PENDSTCLR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDSTCLR_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PENDSTCLR_A { + match self.bits { + false => PENDSTCLR_A::VALUE_0, + true => PENDSTCLR_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == PENDSTCLR_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == PENDSTCLR_A::VALUE_1 + } +} +impl core::ops::Deref for PENDSTCLR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDSTCLR` writer - SysTick exception clear-pending bit"] +pub struct PENDSTCLR_W<'a> { + w: &'a mut W, +} +impl<'a> PENDSTCLR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PENDSTCLR_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "No effect"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(PENDSTCLR_A::VALUE_0) + } + #[doc = "Removes the pending state from the SysTick exception"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(PENDSTCLR_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "SysTick exception set-pending bit\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PENDSTSET_A { + #[doc = "0: Write: no effect; read: SysTick exception is not pending"] + VALUE_0 = 0, + #[doc = "1: Write: changes SysTick exception state to pending; read: SysTick exception is pending"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PENDSTSET_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PENDSTSET` reader - SysTick exception set-pending bit"] +pub struct PENDSTSET_R(crate::FieldReader); +impl PENDSTSET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDSTSET_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PENDSTSET_A { + match self.bits { + false => PENDSTSET_A::VALUE_0, + true => PENDSTSET_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == PENDSTSET_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == PENDSTSET_A::VALUE_1 + } +} +impl core::ops::Deref for PENDSTSET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDSTSET` writer - SysTick exception set-pending bit"] +pub struct PENDSTSET_W<'a> { + w: &'a mut W, +} +impl<'a> PENDSTSET_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PENDSTSET_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Write: no effect; read: SysTick exception is not pending"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(PENDSTSET_A::VALUE_0) + } + #[doc = "Write: changes SysTick exception state to pending; read: SysTick exception is pending"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(PENDSTSET_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "PendSV clear-pending bit\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PENDSVCLR_A { + #[doc = "0: No effect"] + VALUE_0 = 0, + #[doc = "1: Removes the pending state from the PendSV exception"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PENDSVCLR_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PENDSVCLR` reader - PendSV clear-pending bit"] +pub struct PENDSVCLR_R(crate::FieldReader); +impl PENDSVCLR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDSVCLR_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PENDSVCLR_A { + match self.bits { + false => PENDSVCLR_A::VALUE_0, + true => PENDSVCLR_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == PENDSVCLR_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == PENDSVCLR_A::VALUE_1 + } +} +impl core::ops::Deref for PENDSVCLR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDSVCLR` writer - PendSV clear-pending bit"] +pub struct PENDSVCLR_W<'a> { + w: &'a mut W, +} +impl<'a> PENDSVCLR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PENDSVCLR_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "No effect"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(PENDSVCLR_A::VALUE_0) + } + #[doc = "Removes the pending state from the PendSV exception"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(PENDSVCLR_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +#[doc = "PendSV set-pending bit\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PENDSVSET_A { + #[doc = "0: Write: no effect; read: PendSV exception is not pending"] + VALUE_0 = 0, + #[doc = "1: Write: changes PendSV exception state to pending; read: PendSV exception is pending"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PENDSVSET_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PENDSVSET` reader - PendSV set-pending bit"] +pub struct PENDSVSET_R(crate::FieldReader); +impl PENDSVSET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDSVSET_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PENDSVSET_A { + match self.bits { + false => PENDSVSET_A::VALUE_0, + true => PENDSVSET_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == PENDSVSET_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == PENDSVSET_A::VALUE_1 + } +} +impl core::ops::Deref for PENDSVSET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDSVSET` writer - PendSV set-pending bit"] +pub struct PENDSVSET_W<'a> { + w: &'a mut W, +} +impl<'a> PENDSVSET_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PENDSVSET_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Write: no effect; read: PendSV exception is not pending"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(PENDSVSET_A::VALUE_0) + } + #[doc = "Write: changes PendSV exception state to pending; read: PendSV exception is pending"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(PENDSVSET_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "NMI set-pending bit\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum NMIPENDSET_A { + #[doc = "0: Write: no effect; read: NMI exception is not pending"] + VALUE_0 = 0, + #[doc = "1: Write: changes NMI exception state to pending; read: NMI exception is pending"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NMIPENDSET_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NMIPENDSET` reader - NMI set-pending bit"] +pub struct NMIPENDSET_R(crate::FieldReader); +impl NMIPENDSET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NMIPENDSET_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> NMIPENDSET_A { + match self.bits { + false => NMIPENDSET_A::VALUE_0, + true => NMIPENDSET_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == NMIPENDSET_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == NMIPENDSET_A::VALUE_1 + } +} +impl core::ops::Deref for NMIPENDSET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NMIPENDSET` writer - NMI set-pending bit"] +pub struct NMIPENDSET_W<'a> { + w: &'a mut W, +} +impl<'a> NMIPENDSET_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: NMIPENDSET_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Write: no effect; read: NMI exception is not pending"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(NMIPENDSET_A::VALUE_0) + } + #[doc = "Write: changes NMI exception state to pending; read: NMI exception is pending"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(NMIPENDSET_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bits 0:8 - Debug: Exception number of currently executing exception, or 0 if thread mode"] + #[inline(always)] + pub fn vectactive(&self) -> VECTACTIVE_R { + VECTACTIVE_R::new((self.bits & 0x01ff) as u16) + } + #[doc = "Bits 12:20 - Exception number of the highest priority pending enabled exception"] + #[inline(always)] + pub fn vectpending(&self) -> VECTPENDING_R { + VECTPENDING_R::new(((self.bits >> 12) & 0x01ff) as u16) + } + #[doc = "Bit 22 - Debug: NVIC interrupt pending"] + #[inline(always)] + pub fn isrpending(&self) -> ISRPENDING_R { + ISRPENDING_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Debug: Pending exception serviced on exit from debug halt"] + #[inline(always)] + pub fn isrpreempt(&self) -> ISRPREEMPT_R { + ISRPREEMPT_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 25 - SysTick exception clear-pending bit"] + #[inline(always)] + pub fn pendstclr(&self) -> PENDSTCLR_R { + PENDSTCLR_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - SysTick exception set-pending bit"] + #[inline(always)] + pub fn pendstset(&self) -> PENDSTSET_R { + PENDSTSET_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - PendSV clear-pending bit"] + #[inline(always)] + pub fn pendsvclr(&self) -> PENDSVCLR_R { + PENDSVCLR_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28 - PendSV set-pending bit"] + #[inline(always)] + pub fn pendsvset(&self) -> PENDSVSET_R { + PENDSVSET_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 31 - NMI set-pending bit"] + #[inline(always)] + pub fn nmipendset(&self) -> NMIPENDSET_R { + NMIPENDSET_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:8 - Debug: Exception number of currently executing exception, or 0 if thread mode"] + #[inline(always)] + pub fn vectactive(&mut self) -> VECTACTIVE_W { + VECTACTIVE_W { w: self } + } + #[doc = "Bits 12:20 - Exception number of the highest priority pending enabled exception"] + #[inline(always)] + pub fn vectpending(&mut self) -> VECTPENDING_W { + VECTPENDING_W { w: self } + } + #[doc = "Bit 22 - Debug: NVIC interrupt pending"] + #[inline(always)] + pub fn isrpending(&mut self) -> ISRPENDING_W { + ISRPENDING_W { w: self } + } + #[doc = "Bit 23 - Debug: Pending exception serviced on exit from debug halt"] + #[inline(always)] + pub fn isrpreempt(&mut self) -> ISRPREEMPT_W { + ISRPREEMPT_W { w: self } + } + #[doc = "Bit 25 - SysTick exception clear-pending bit"] + #[inline(always)] + pub fn pendstclr(&mut self) -> PENDSTCLR_W { + PENDSTCLR_W { w: self } + } + #[doc = "Bit 26 - SysTick exception set-pending bit"] + #[inline(always)] + pub fn pendstset(&mut self) -> PENDSTSET_W { + PENDSTSET_W { w: self } + } + #[doc = "Bit 27 - PendSV clear-pending bit"] + #[inline(always)] + pub fn pendsvclr(&mut self) -> PENDSVCLR_W { + PENDSVCLR_W { w: self } + } + #[doc = "Bit 28 - PendSV set-pending bit"] + #[inline(always)] + pub fn pendsvset(&mut self) -> PENDSVSET_W { + PENDSVSET_W { w: self } + } + #[doc = "Bit 31 - NMI set-pending bit"] + #[inline(always)] + pub fn nmipendset(&mut self) -> NMIPENDSET_W { + NMIPENDSET_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Control and State Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [icsr](index.html) module"] +pub struct ICSR_SPEC; +impl crate::RegisterSpec for ICSR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [icsr::R](R) reader structure"] +impl crate::Readable for ICSR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [icsr::W](W) writer structure"] +impl crate::Writable for ICSR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ICSR to value 0"] +impl crate::Resettable for ICSR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/system_control/scr.rs b/pac/atsamc21j/src/system_control/scr.rs new file mode 100644 index 000000000000..db9c54fe6f6f --- /dev/null +++ b/pac/atsamc21j/src/system_control/scr.rs @@ -0,0 +1,348 @@ +#[doc = "Register `SCR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SCR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Sleep-On-Exit when exiting Handler mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SLEEPONEXIT_A { + #[doc = "0: O not sleep when returning to Thread mode"] + VALUE_0 = 0, + #[doc = "1: Enter sleep, or deep sleep, on return from an ISR"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SLEEPONEXIT_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SLEEPONEXIT` reader - Sleep-On-Exit when exiting Handler mode"] +pub struct SLEEPONEXIT_R(crate::FieldReader); +impl SLEEPONEXIT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLEEPONEXIT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SLEEPONEXIT_A { + match self.bits { + false => SLEEPONEXIT_A::VALUE_0, + true => SLEEPONEXIT_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == SLEEPONEXIT_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == SLEEPONEXIT_A::VALUE_1 + } +} +impl core::ops::Deref for SLEEPONEXIT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLEEPONEXIT` writer - Sleep-On-Exit when exiting Handler mode"] +pub struct SLEEPONEXIT_W<'a> { + w: &'a mut W, +} +impl<'a> SLEEPONEXIT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SLEEPONEXIT_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "O not sleep when returning to Thread mode"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(SLEEPONEXIT_A::VALUE_0) + } + #[doc = "Enter sleep, or deep sleep, on return from an ISR"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(SLEEPONEXIT_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Uses Deep Sleep as low power mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SLEEPDEEP_A { + #[doc = "0: Sleep"] + VALUE_0 = 0, + #[doc = "1: Deep sleep"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SLEEPDEEP_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SLEEPDEEP` reader - Uses Deep Sleep as low power mode"] +pub struct SLEEPDEEP_R(crate::FieldReader); +impl SLEEPDEEP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLEEPDEEP_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SLEEPDEEP_A { + match self.bits { + false => SLEEPDEEP_A::VALUE_0, + true => SLEEPDEEP_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == SLEEPDEEP_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == SLEEPDEEP_A::VALUE_1 + } +} +impl core::ops::Deref for SLEEPDEEP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLEEPDEEP` writer - Uses Deep Sleep as low power mode"] +pub struct SLEEPDEEP_W<'a> { + w: &'a mut W, +} +impl<'a> SLEEPDEEP_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SLEEPDEEP_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Sleep"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(SLEEPDEEP_A::VALUE_0) + } + #[doc = "Deep sleep"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(SLEEPDEEP_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Send Event on Pending bit\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SEVONPEND_A { + #[doc = "0: Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded"] + VALUE_0 = 0, + #[doc = "1: Enabled events and all interrupts, including disabled interrupts, can wakeup the processor"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SEVONPEND_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SEVONPEND` reader - Send Event on Pending bit"] +pub struct SEVONPEND_R(crate::FieldReader); +impl SEVONPEND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SEVONPEND_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SEVONPEND_A { + match self.bits { + false => SEVONPEND_A::VALUE_0, + true => SEVONPEND_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == SEVONPEND_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == SEVONPEND_A::VALUE_1 + } +} +impl core::ops::Deref for SEVONPEND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEVONPEND` writer - Send Event on Pending bit"] +pub struct SEVONPEND_W<'a> { + w: &'a mut W, +} +impl<'a> SEVONPEND_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SEVONPEND_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(SEVONPEND_A::VALUE_0) + } + #[doc = "Enabled events and all interrupts, including disabled interrupts, can wakeup the processor"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(SEVONPEND_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +impl R { + #[doc = "Bit 1 - Sleep-On-Exit when exiting Handler mode"] + #[inline(always)] + pub fn sleeponexit(&self) -> SLEEPONEXIT_R { + SLEEPONEXIT_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Uses Deep Sleep as low power mode"] + #[inline(always)] + pub fn sleepdeep(&self) -> SLEEPDEEP_R { + SLEEPDEEP_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 4 - Send Event on Pending bit"] + #[inline(always)] + pub fn sevonpend(&self) -> SEVONPEND_R { + SEVONPEND_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 1 - Sleep-On-Exit when exiting Handler mode"] + #[inline(always)] + pub fn sleeponexit(&mut self) -> SLEEPONEXIT_W { + SLEEPONEXIT_W { w: self } + } + #[doc = "Bit 2 - Uses Deep Sleep as low power mode"] + #[inline(always)] + pub fn sleepdeep(&mut self) -> SLEEPDEEP_W { + SLEEPDEEP_W { w: self } + } + #[doc = "Bit 4 - Send Event on Pending bit"] + #[inline(always)] + pub fn sevonpend(&mut self) -> SEVONPEND_W { + SEVONPEND_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "System Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [scr](index.html) module"] +pub struct SCR_SPEC; +impl crate::RegisterSpec for SCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [scr::R](R) reader structure"] +impl crate::Readable for SCR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [scr::W](W) writer structure"] +impl crate::Writable for SCR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SCR to value 0"] +impl crate::Resettable for SCR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/system_control/shcsr.rs b/pac/atsamc21j/src/system_control/shcsr.rs new file mode 100644 index 000000000000..bfba26ac06ad --- /dev/null +++ b/pac/atsamc21j/src/system_control/shcsr.rs @@ -0,0 +1,113 @@ +#[doc = "Register `SHCSR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SHCSR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SVCALLPENDED` reader - "] +pub struct SVCALLPENDED_R(crate::FieldReader); +impl SVCALLPENDED_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SVCALLPENDED_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SVCALLPENDED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SVCALLPENDED` writer - "] +pub struct SVCALLPENDED_W<'a> { + w: &'a mut W, +} +impl<'a> SVCALLPENDED_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 15"] + #[inline(always)] + pub fn svcallpended(&self) -> SVCALLPENDED_R { + SVCALLPENDED_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 15"] + #[inline(always)] + pub fn svcallpended(&mut self) -> SVCALLPENDED_W { + SVCALLPENDED_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "System Handler Control and State Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [shcsr](index.html) module"] +pub struct SHCSR_SPEC; +impl crate::RegisterSpec for SHCSR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [shcsr::R](R) reader structure"] +impl crate::Readable for SHCSR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [shcsr::W](W) writer structure"] +impl crate::Writable for SHCSR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SHCSR to value 0"] +impl crate::Resettable for SHCSR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/system_control/shpr2.rs b/pac/atsamc21j/src/system_control/shpr2.rs new file mode 100644 index 000000000000..5665d6a5e8a9 --- /dev/null +++ b/pac/atsamc21j/src/system_control/shpr2.rs @@ -0,0 +1,103 @@ +#[doc = "Register `SHPR2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SHPR2` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PRI_11` reader - Priority of system handler 11, SVCall"] +pub struct PRI_11_R(crate::FieldReader); +impl PRI_11_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRI_11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PRI_11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRI_11` writer - Priority of system handler 11, SVCall"] +pub struct PRI_11_W<'a> { + w: &'a mut W, +} +impl<'a> PRI_11_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 24)) | ((value as u32 & 0xff) << 24); + self.w + } +} +impl R { + #[doc = "Bits 24:31 - Priority of system handler 11, SVCall"] + #[inline(always)] + pub fn pri_11(&self) -> PRI_11_R { + PRI_11_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 24:31 - Priority of system handler 11, SVCall"] + #[inline(always)] + pub fn pri_11(&mut self) -> PRI_11_W { + PRI_11_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "System Handler Priority Register 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [shpr2](index.html) module"] +pub struct SHPR2_SPEC; +impl crate::RegisterSpec for SHPR2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [shpr2::R](R) reader structure"] +impl crate::Readable for SHPR2_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [shpr2::W](W) writer structure"] +impl crate::Writable for SHPR2_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SHPR2 to value 0"] +impl crate::Resettable for SHPR2_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/system_control/shpr3.rs b/pac/atsamc21j/src/system_control/shpr3.rs new file mode 100644 index 000000000000..cb5a92c53503 --- /dev/null +++ b/pac/atsamc21j/src/system_control/shpr3.rs @@ -0,0 +1,140 @@ +#[doc = "Register `SHPR3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SHPR3` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PRI_14` reader - Priority of system handler 14, PendSV"] +pub struct PRI_14_R(crate::FieldReader); +impl PRI_14_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRI_14_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PRI_14_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRI_14` writer - Priority of system handler 14, PendSV"] +pub struct PRI_14_W<'a> { + w: &'a mut W, +} +impl<'a> PRI_14_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +#[doc = "Field `PRI_15` reader - Priority of system handler 15, SysTick exception"] +pub struct PRI_15_R(crate::FieldReader); +impl PRI_15_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRI_15_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PRI_15_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRI_15` writer - Priority of system handler 15, SysTick exception"] +pub struct PRI_15_W<'a> { + w: &'a mut W, +} +impl<'a> PRI_15_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 24)) | ((value as u32 & 0xff) << 24); + self.w + } +} +impl R { + #[doc = "Bits 16:23 - Priority of system handler 14, PendSV"] + #[inline(always)] + pub fn pri_14(&self) -> PRI_14_R { + PRI_14_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Priority of system handler 15, SysTick exception"] + #[inline(always)] + pub fn pri_15(&self) -> PRI_15_R { + PRI_15_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 16:23 - Priority of system handler 14, PendSV"] + #[inline(always)] + pub fn pri_14(&mut self) -> PRI_14_W { + PRI_14_W { w: self } + } + #[doc = "Bits 24:31 - Priority of system handler 15, SysTick exception"] + #[inline(always)] + pub fn pri_15(&mut self) -> PRI_15_W { + PRI_15_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "System Handler Priority Register 3\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [shpr3](index.html) module"] +pub struct SHPR3_SPEC; +impl crate::RegisterSpec for SHPR3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [shpr3::R](R) reader structure"] +impl crate::Readable for SHPR3_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [shpr3::W](W) writer structure"] +impl crate::Writable for SHPR3_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SHPR3 to value 0"] +impl crate::Resettable for SHPR3_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/system_control/vtor.rs b/pac/atsamc21j/src/system_control/vtor.rs new file mode 100644 index 000000000000..0ee4c7817817 --- /dev/null +++ b/pac/atsamc21j/src/system_control/vtor.rs @@ -0,0 +1,103 @@ +#[doc = "Register `VTOR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `VTOR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TBLOFF` reader - Vector table base offset"] +pub struct TBLOFF_R(crate::FieldReader); +impl TBLOFF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + TBLOFF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TBLOFF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TBLOFF` writer - Vector table base offset"] +pub struct TBLOFF_W<'a> { + w: &'a mut W, +} +impl<'a> TBLOFF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01ff_ffff << 7)) | ((value as u32 & 0x01ff_ffff) << 7); + self.w + } +} +impl R { + #[doc = "Bits 7:31 - Vector table base offset"] + #[inline(always)] + pub fn tbloff(&self) -> TBLOFF_R { + TBLOFF_R::new(((self.bits >> 7) & 0x01ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 7:31 - Vector table base offset"] + #[inline(always)] + pub fn tbloff(&mut self) -> TBLOFF_W { + TBLOFF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Vector Table Offset Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [vtor](index.html) module"] +pub struct VTOR_SPEC; +impl crate::RegisterSpec for VTOR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [vtor::R](R) reader structure"] +impl crate::Readable for VTOR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [vtor::W](W) writer structure"] +impl crate::Writable for VTOR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets VTOR to value 0"] +impl crate::Resettable for VTOR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/tc0.rs b/pac/atsamc21j/src/tc0.rs new file mode 100644 index 000000000000..86e973b276e7 --- /dev/null +++ b/pac/atsamc21j/src/tc0.rs @@ -0,0 +1,146 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved_0_count8: [u8; 0x38], +} +impl RegisterBlock { + #[doc = "0x00..0x38 - 32-bit Counter Mode"] + #[inline(always)] + pub fn count32(&self) -> &COUNT32 { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const COUNT32) } + } + #[doc = "0x00..0x34 - 16-bit Counter Mode"] + #[inline(always)] + pub fn count16(&self) -> &COUNT16 { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const COUNT16) } + } + #[doc = "0x00..0x32 - 8-bit Counter Mode"] + #[inline(always)] + pub fn count8(&self) -> &COUNT8 { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const COUNT8) } + } +} +#[doc = r"Register block"] +#[repr(C)] +pub struct COUNT8 { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - Control B Clear"] + pub ctrlbclr: crate::Reg, + #[doc = "0x05 - Control B Set"] + pub ctrlbset: crate::Reg, + #[doc = "0x06 - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x08 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x09 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x0a - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x0b - Status"] + pub status: crate::Reg, + #[doc = "0x0c - Waveform Generation Control"] + pub wave: crate::Reg, + #[doc = "0x0d - Control C"] + pub drvctrl: crate::Reg, + _reserved10: [u8; 0x01], + #[doc = "0x0f - Debug Control"] + pub dbgctrl: crate::Reg, + #[doc = "0x10 - Synchronization Status"] + pub syncbusy: crate::Reg, + #[doc = "0x14 - COUNT8 Count"] + pub count: crate::Reg, + _reserved13: [u8; 0x06], + #[doc = "0x1b - COUNT8 Period"] + pub per: crate::Reg, + #[doc = "0x1c - COUNT8 Compare and Capture"] + pub cc: [crate::Reg; 2], + _reserved15: [u8; 0x11], + #[doc = "0x2f - COUNT8 Period Buffer"] + pub perbuf: crate::Reg, + #[doc = "0x30 - COUNT8 Compare and Capture Buffer"] + pub ccbuf: [crate::Reg; 2], +} +#[doc = r"Register block"] +#[doc = "8-bit Counter Mode"] +pub mod count8; +#[doc = r"Register block"] +#[repr(C)] +pub struct COUNT16 { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - Control B Clear"] + pub ctrlbclr: crate::Reg, + #[doc = "0x05 - Control B Set"] + pub ctrlbset: crate::Reg, + #[doc = "0x06 - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x08 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x09 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x0a - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x0b - Status"] + pub status: crate::Reg, + #[doc = "0x0c - Waveform Generation Control"] + pub wave: crate::Reg, + #[doc = "0x0d - Control C"] + pub drvctrl: crate::Reg, + _reserved10: [u8; 0x01], + #[doc = "0x0f - Debug Control"] + pub dbgctrl: crate::Reg, + #[doc = "0x10 - Synchronization Status"] + pub syncbusy: crate::Reg, + #[doc = "0x14 - COUNT16 Count"] + pub count: crate::Reg, + _reserved13: [u8; 0x06], + #[doc = "0x1c - COUNT16 Compare and Capture"] + pub cc: [crate::Reg; 2], + _reserved14: [u8; 0x10], + #[doc = "0x30 - COUNT16 Compare and Capture Buffer"] + pub ccbuf: [crate::Reg; 2], +} +#[doc = r"Register block"] +#[doc = "16-bit Counter Mode"] +pub mod count16; +#[doc = r"Register block"] +#[repr(C)] +pub struct COUNT32 { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - Control B Clear"] + pub ctrlbclr: crate::Reg, + #[doc = "0x05 - Control B Set"] + pub ctrlbset: crate::Reg, + #[doc = "0x06 - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x08 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x09 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x0a - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x0b - Status"] + pub status: crate::Reg, + #[doc = "0x0c - Waveform Generation Control"] + pub wave: crate::Reg, + #[doc = "0x0d - Control C"] + pub drvctrl: crate::Reg, + _reserved10: [u8; 0x01], + #[doc = "0x0f - Debug Control"] + pub dbgctrl: crate::Reg, + #[doc = "0x10 - Synchronization Status"] + pub syncbusy: crate::Reg, + #[doc = "0x14 - COUNT32 Count"] + pub count: crate::Reg, + _reserved13: [u8; 0x04], + #[doc = "0x1c..0x24 - COUNT32 Compare and Capture"] + pub cc: [crate::Reg; 2], + _reserved14: [u8; 0x0c], + #[doc = "0x30..0x38 - COUNT32 Compare and Capture Buffer"] + pub ccbuf: [crate::Reg; 2], +} +#[doc = r"Register block"] +#[doc = "32-bit Counter Mode"] +pub mod count32; diff --git a/pac/atsamc21j/src/tc0/count16.rs b/pac/atsamc21j/src/tc0/count16.rs new file mode 100644 index 000000000000..5bd1e88c7efb --- /dev/null +++ b/pac/atsamc21j/src/tc0/count16.rs @@ -0,0 +1,60 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "CTRLBCLR register accessor: an alias for `Reg`"] +pub type CTRLBCLR = crate::Reg; +#[doc = "Control B Clear"] +pub mod ctrlbclr; +#[doc = "CTRLBSET register accessor: an alias for `Reg`"] +pub type CTRLBSET = crate::Reg; +#[doc = "Control B Set"] +pub mod ctrlbset; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "WAVE register accessor: an alias for `Reg`"] +pub type WAVE = crate::Reg; +#[doc = "Waveform Generation Control"] +pub mod wave; +#[doc = "DRVCTRL register accessor: an alias for `Reg`"] +pub type DRVCTRL = crate::Reg; +#[doc = "Control C"] +pub mod drvctrl; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Status"] +pub mod syncbusy; +#[doc = "COUNT register accessor: an alias for `Reg`"] +pub type COUNT = crate::Reg; +#[doc = "COUNT16 Count"] +pub mod count; +#[doc = "CC register accessor: an alias for `Reg`"] +pub type CC = crate::Reg; +#[doc = "COUNT16 Compare and Capture"] +pub mod cc; +#[doc = "CCBUF register accessor: an alias for `Reg`"] +pub type CCBUF = crate::Reg; +#[doc = "COUNT16 Compare and Capture Buffer"] +pub mod ccbuf; diff --git a/pac/atsamc21j/src/tc0/count16/cc.rs b/pac/atsamc21j/src/tc0/count16/cc.rs new file mode 100644 index 000000000000..b6f975905e31 --- /dev/null +++ b/pac/atsamc21j/src/tc0/count16/cc.rs @@ -0,0 +1,104 @@ +#[doc = "Register `CC[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CC[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CC` reader - Counter/Compare Value"] +pub struct CC_R(crate::FieldReader); +impl CC_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + CC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC` writer - Counter/Compare Value"] +pub struct CC_W<'a> { + w: &'a mut W, +} +impl<'a> CC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Counter/Compare Value"] + #[inline(always)] + pub fn cc(&self) -> CC_R { + CC_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Counter/Compare Value"] + #[inline(always)] + pub fn cc(&mut self) -> CC_W { + CC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT16 Compare and Capture\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc](index.html) module"] +pub struct CC_SPEC; +impl crate::RegisterSpec for CC_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [cc::R](R) reader structure"] +impl crate::Readable for CC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cc::W](W) writer structure"] +impl crate::Writable for CC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CC[%s] +to value 0"] +impl crate::Resettable for CC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/tc0/count16/ccbuf.rs b/pac/atsamc21j/src/tc0/count16/ccbuf.rs new file mode 100644 index 000000000000..2f922bba8d31 --- /dev/null +++ b/pac/atsamc21j/src/tc0/count16/ccbuf.rs @@ -0,0 +1,104 @@ +#[doc = "Register `CCBUF[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CCBUF[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CCBUF` reader - Counter/Compare Buffer Value"] +pub struct CCBUF_R(crate::FieldReader); +impl CCBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + CCBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUF` writer - Counter/Compare Buffer Value"] +pub struct CCBUF_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Counter/Compare Buffer Value"] + #[inline(always)] + pub fn ccbuf(&self) -> CCBUF_R { + CCBUF_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Counter/Compare Buffer Value"] + #[inline(always)] + pub fn ccbuf(&mut self) -> CCBUF_W { + CCBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT16 Compare and Capture Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccbuf](index.html) module"] +pub struct CCBUF_SPEC; +impl crate::RegisterSpec for CCBUF_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ccbuf::R](R) reader structure"] +impl crate::Readable for CCBUF_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ccbuf::W](W) writer structure"] +impl crate::Writable for CCBUF_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CCBUF[%s] +to value 0"] +impl crate::Resettable for CCBUF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/tc0/count16/count.rs b/pac/atsamc21j/src/tc0/count16/count.rs new file mode 100644 index 000000000000..5d26b509abb1 --- /dev/null +++ b/pac/atsamc21j/src/tc0/count16/count.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT16 Count\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count](index.html) module"] +pub struct COUNT_SPEC; +impl crate::RegisterSpec for COUNT_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [count::R](R) reader structure"] +impl crate::Readable for COUNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count::W](W) writer structure"] +impl crate::Writable for COUNT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT to value 0"] +impl crate::Resettable for COUNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/tc0/count16/ctrla.rs b/pac/atsamc21j/src/tc0/count16/ctrla.rs new file mode 100644 index 000000000000..cadcddaaead8 --- /dev/null +++ b/pac/atsamc21j/src/tc0/count16/ctrla.rs @@ -0,0 +1,851 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Timer Counter Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: Counter in 16-bit mode"] + COUNT16 = 0, + #[doc = "1: Counter in 8-bit mode"] + COUNT8 = 1, + #[doc = "2: Counter in 32-bit mode"] + COUNT32 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Timer Counter Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::COUNT16), + 1 => Some(MODE_A::COUNT8), + 2 => Some(MODE_A::COUNT32), + _ => None, + } + } + #[doc = "Checks if the value of the field is `COUNT16`"] + #[inline(always)] + pub fn is_count16(&self) -> bool { + **self == MODE_A::COUNT16 + } + #[doc = "Checks if the value of the field is `COUNT8`"] + #[inline(always)] + pub fn is_count8(&self) -> bool { + **self == MODE_A::COUNT8 + } + #[doc = "Checks if the value of the field is `COUNT32`"] + #[inline(always)] + pub fn is_count32(&self) -> bool { + **self == MODE_A::COUNT32 + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Timer Counter Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Counter in 16-bit mode"] + #[inline(always)] + pub fn count16(self) -> &'a mut W { + self.variant(MODE_A::COUNT16) + } + #[doc = "Counter in 8-bit mode"] + #[inline(always)] + pub fn count8(self) -> &'a mut W { + self.variant(MODE_A::COUNT8) + } + #[doc = "Counter in 32-bit mode"] + #[inline(always)] + pub fn count32(self) -> &'a mut W { + self.variant(MODE_A::COUNT32) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u32 & 0x03) << 2); + self.w + } +} +#[doc = "Prescaler and Counter Synchronization\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCSYNC_A { + #[doc = "0: Reload or reset the counter on next generic clock"] + GCLK = 0, + #[doc = "1: Reload or reset the counter on next prescaler clock"] + PRESC = 1, + #[doc = "2: Reload or reset the counter on next generic clock and reset the prescaler counter"] + RESYNC = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCSYNC_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCSYNC` reader - Prescaler and Counter Synchronization"] +pub struct PRESCSYNC_R(crate::FieldReader); +impl PRESCSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCSYNC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCSYNC_A::GCLK), + 1 => Some(PRESCSYNC_A::PRESC), + 2 => Some(PRESCSYNC_A::RESYNC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `GCLK`"] + #[inline(always)] + pub fn is_gclk(&self) -> bool { + **self == PRESCSYNC_A::GCLK + } + #[doc = "Checks if the value of the field is `PRESC`"] + #[inline(always)] + pub fn is_presc(&self) -> bool { + **self == PRESCSYNC_A::PRESC + } + #[doc = "Checks if the value of the field is `RESYNC`"] + #[inline(always)] + pub fn is_resync(&self) -> bool { + **self == PRESCSYNC_A::RESYNC + } +} +impl core::ops::Deref for PRESCSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCSYNC` writer - Prescaler and Counter Synchronization"] +pub struct PRESCSYNC_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCSYNC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCSYNC_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Reload or reset the counter on next generic clock"] + #[inline(always)] + pub fn gclk(self) -> &'a mut W { + self.variant(PRESCSYNC_A::GCLK) + } + #[doc = "Reload or reset the counter on next prescaler clock"] + #[inline(always)] + pub fn presc(self) -> &'a mut W { + self.variant(PRESCSYNC_A::PRESC) + } + #[doc = "Reload or reset the counter on next generic clock and reset the prescaler counter"] + #[inline(always)] + pub fn resync(self) -> &'a mut W { + self.variant(PRESCSYNC_A::RESYNC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u32 & 0x03) << 4); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - Clock On Demand"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - Clock On Demand"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: Prescaler: GCLK_TC"] + DIV1 = 0, + #[doc = "1: Prescaler: GCLK_TC/2"] + DIV2 = 1, + #[doc = "2: Prescaler: GCLK_TC/4"] + DIV4 = 2, + #[doc = "3: Prescaler: GCLK_TC/8"] + DIV8 = 3, + #[doc = "4: Prescaler: GCLK_TC/16"] + DIV16 = 4, + #[doc = "5: Prescaler: GCLK_TC/64"] + DIV64 = 5, + #[doc = "6: Prescaler: GCLK_TC/256"] + DIV256 = 6, + #[doc = "7: Prescaler: GCLK_TC/1024"] + DIV1024 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PRESCALER_A { + match self.bits { + 0 => PRESCALER_A::DIV1, + 1 => PRESCALER_A::DIV2, + 2 => PRESCALER_A::DIV4, + 3 => PRESCALER_A::DIV8, + 4 => PRESCALER_A::DIV16, + 5 => PRESCALER_A::DIV64, + 6 => PRESCALER_A::DIV256, + 7 => PRESCALER_A::DIV1024, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == PRESCALER_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PRESCALER_A::DIV1024 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Prescaler: GCLK_TC"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1) + } + #[doc = "Prescaler: GCLK_TC/2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "Prescaler: GCLK_TC/4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "Prescaler: GCLK_TC/8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "Prescaler: GCLK_TC/16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "Prescaler: GCLK_TC/64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "Prescaler: GCLK_TC/256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = "Prescaler: GCLK_TC/1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +#[doc = "Field `ALOCK` reader - Auto Lock"] +pub struct ALOCK_R(crate::FieldReader); +impl ALOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALOCK` writer - Auto Lock"] +pub struct ALOCK_W<'a> { + w: &'a mut W, +} +impl<'a> ALOCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `CAPTEN0` reader - Capture Channel 0 Enable"] +pub struct CAPTEN0_R(crate::FieldReader); +impl CAPTEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CAPTEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CAPTEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAPTEN0` writer - Capture Channel 0 Enable"] +pub struct CAPTEN0_W<'a> { + w: &'a mut W, +} +impl<'a> CAPTEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `CAPTEN1` reader - Capture Channel 1 Enable"] +pub struct CAPTEN1_R(crate::FieldReader); +impl CAPTEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CAPTEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CAPTEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAPTEN1` writer - Capture Channel 1 Enable"] +pub struct CAPTEN1_W<'a> { + w: &'a mut W, +} +impl<'a> CAPTEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `COPEN0` reader - Capture On Pin 0 Enable"] +pub struct COPEN0_R(crate::FieldReader); +impl COPEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COPEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COPEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COPEN0` writer - Capture On Pin 0 Enable"] +pub struct COPEN0_W<'a> { + w: &'a mut W, +} +impl<'a> COPEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `COPEN1` reader - Capture On Pin 1 Enable"] +pub struct COPEN1_R(crate::FieldReader); +impl COPEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COPEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COPEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COPEN1` writer - Capture On Pin 1 Enable"] +pub struct COPEN1_W<'a> { + w: &'a mut W, +} +impl<'a> COPEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:3 - Timer Counter Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bits 4:5 - Prescaler and Counter Synchronization"] + #[inline(always)] + pub fn prescsync(&self) -> PRESCSYNC_R { + PRESCSYNC_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Clock On Demand"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 11 - Auto Lock"] + #[inline(always)] + pub fn alock(&self) -> ALOCK_R { + ALOCK_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 16 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn capten0(&self) -> CAPTEN0_R { + CAPTEN0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn capten1(&self) -> CAPTEN1_R { + CAPTEN1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 20 - Capture On Pin 0 Enable"] + #[inline(always)] + pub fn copen0(&self) -> COPEN0_R { + COPEN0_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Capture On Pin 1 Enable"] + #[inline(always)] + pub fn copen1(&self) -> COPEN1_R { + COPEN1_R::new(((self.bits >> 21) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:3 - Timer Counter Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bits 4:5 - Prescaler and Counter Synchronization"] + #[inline(always)] + pub fn prescsync(&mut self) -> PRESCSYNC_W { + PRESCSYNC_W { w: self } + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - Clock On Demand"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Bit 11 - Auto Lock"] + #[inline(always)] + pub fn alock(&mut self) -> ALOCK_W { + ALOCK_W { w: self } + } + #[doc = "Bit 16 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn capten0(&mut self) -> CAPTEN0_W { + CAPTEN0_W { w: self } + } + #[doc = "Bit 17 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn capten1(&mut self) -> CAPTEN1_W { + CAPTEN1_W { w: self } + } + #[doc = "Bit 20 - Capture On Pin 0 Enable"] + #[inline(always)] + pub fn copen0(&mut self) -> COPEN0_W { + COPEN0_W { w: self } + } + #[doc = "Bit 21 - Capture On Pin 1 Enable"] + #[inline(always)] + pub fn copen1(&mut self) -> COPEN1_W { + COPEN1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/tc0/count16/ctrlbclr.rs b/pac/atsamc21j/src/tc0/count16/ctrlbclr.rs new file mode 100644 index 000000000000..76265674036a --- /dev/null +++ b/pac/atsamc21j/src/tc0/count16/ctrlbclr.rs @@ -0,0 +1,345 @@ +#[doc = "Register `CTRLBCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Counter Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `LUPD` reader - Lock Update"] +pub struct LUPD_R(crate::FieldReader); +impl LUPD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LUPD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LUPD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LUPD` writer - Lock Update"] +pub struct LUPD_W<'a> { + w: &'a mut W, +} +impl<'a> LUPD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ONESHOT` reader - One-Shot on Counter"] +pub struct ONESHOT_R(crate::FieldReader); +impl ONESHOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONESHOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONESHOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONESHOT` writer - One-Shot on Counter"] +pub struct ONESHOT_W<'a> { + w: &'a mut W, +} +impl<'a> ONESHOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Force a start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force a stop"] + STOP = 2, + #[doc = "3: Force update of double-buffered register"] + UPDATE = 3, + #[doc = "4: Force a read synchronization of COUNT"] + READSYNC = 4, + #[doc = "5: One-shot DMA trigger"] + DMAOS = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NONE), + 1 => Some(CMD_A::RETRIGGER), + 2 => Some(CMD_A::STOP), + 3 => Some(CMD_A::UPDATE), + 4 => Some(CMD_A::READSYNC), + 5 => Some(CMD_A::DMAOS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == CMD_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == CMD_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == CMD_A::STOP + } + #[doc = "Checks if the value of the field is `UPDATE`"] + #[inline(always)] + pub fn is_update(&self) -> bool { + **self == CMD_A::UPDATE + } + #[doc = "Checks if the value of the field is `READSYNC`"] + #[inline(always)] + pub fn is_readsync(&self) -> bool { + **self == CMD_A::READSYNC + } + #[doc = "Checks if the value of the field is `DMAOS`"] + #[inline(always)] + pub fn is_dmaos(&self) -> bool { + **self == CMD_A::DMAOS + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMD_A::NONE) + } + #[doc = "Force a start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMD_A::RETRIGGER) + } + #[doc = "Force a stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMD_A::STOP) + } + #[doc = "Force update of double-buffered register"] + #[inline(always)] + pub fn update(self) -> &'a mut W { + self.variant(CMD_A::UPDATE) + } + #[doc = "Force a read synchronization of COUNT"] + #[inline(always)] + pub fn readsync(self) -> &'a mut W { + self.variant(CMD_A::READSYNC) + } + #[doc = "One-shot DMA trigger"] + #[inline(always)] + pub fn dmaos(self) -> &'a mut W { + self.variant(CMD_A::DMAOS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 5)) | ((value as u8 & 0x07) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&self) -> LUPD_R { + LUPD_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 5) & 0x07) as u8) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&mut self) -> LUPD_W { + LUPD_W { w: self } + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&mut self) -> ONESHOT_W { + ONESHOT_W { w: self } + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbclr](index.html) module"] +pub struct CTRLBCLR_SPEC; +impl crate::RegisterSpec for CTRLBCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbclr::R](R) reader structure"] +impl crate::Readable for CTRLBCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbclr::W](W) writer structure"] +impl crate::Writable for CTRLBCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLBCLR to value 0"] +impl crate::Resettable for CTRLBCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/tc0/count16/ctrlbset.rs b/pac/atsamc21j/src/tc0/count16/ctrlbset.rs new file mode 100644 index 000000000000..610914c9c7c8 --- /dev/null +++ b/pac/atsamc21j/src/tc0/count16/ctrlbset.rs @@ -0,0 +1,345 @@ +#[doc = "Register `CTRLBSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Counter Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `LUPD` reader - Lock Update"] +pub struct LUPD_R(crate::FieldReader); +impl LUPD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LUPD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LUPD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LUPD` writer - Lock Update"] +pub struct LUPD_W<'a> { + w: &'a mut W, +} +impl<'a> LUPD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ONESHOT` reader - One-Shot on Counter"] +pub struct ONESHOT_R(crate::FieldReader); +impl ONESHOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONESHOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONESHOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONESHOT` writer - One-Shot on Counter"] +pub struct ONESHOT_W<'a> { + w: &'a mut W, +} +impl<'a> ONESHOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Force a start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force a stop"] + STOP = 2, + #[doc = "3: Force update of double-buffered register"] + UPDATE = 3, + #[doc = "4: Force a read synchronization of COUNT"] + READSYNC = 4, + #[doc = "5: One-shot DMA trigger"] + DMAOS = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NONE), + 1 => Some(CMD_A::RETRIGGER), + 2 => Some(CMD_A::STOP), + 3 => Some(CMD_A::UPDATE), + 4 => Some(CMD_A::READSYNC), + 5 => Some(CMD_A::DMAOS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == CMD_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == CMD_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == CMD_A::STOP + } + #[doc = "Checks if the value of the field is `UPDATE`"] + #[inline(always)] + pub fn is_update(&self) -> bool { + **self == CMD_A::UPDATE + } + #[doc = "Checks if the value of the field is `READSYNC`"] + #[inline(always)] + pub fn is_readsync(&self) -> bool { + **self == CMD_A::READSYNC + } + #[doc = "Checks if the value of the field is `DMAOS`"] + #[inline(always)] + pub fn is_dmaos(&self) -> bool { + **self == CMD_A::DMAOS + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMD_A::NONE) + } + #[doc = "Force a start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMD_A::RETRIGGER) + } + #[doc = "Force a stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMD_A::STOP) + } + #[doc = "Force update of double-buffered register"] + #[inline(always)] + pub fn update(self) -> &'a mut W { + self.variant(CMD_A::UPDATE) + } + #[doc = "Force a read synchronization of COUNT"] + #[inline(always)] + pub fn readsync(self) -> &'a mut W { + self.variant(CMD_A::READSYNC) + } + #[doc = "One-shot DMA trigger"] + #[inline(always)] + pub fn dmaos(self) -> &'a mut W { + self.variant(CMD_A::DMAOS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 5)) | ((value as u8 & 0x07) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&self) -> LUPD_R { + LUPD_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 5) & 0x07) as u8) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&mut self) -> LUPD_W { + LUPD_W { w: self } + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&mut self) -> ONESHOT_W { + ONESHOT_W { w: self } + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbset](index.html) module"] +pub struct CTRLBSET_SPEC; +impl crate::RegisterSpec for CTRLBSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbset::R](R) reader structure"] +impl crate::Readable for CTRLBSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbset::W](W) writer structure"] +impl crate::Writable for CTRLBSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLBSET to value 0"] +impl crate::Resettable for CTRLBSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/tc0/count16/dbgctrl.rs b/pac/atsamc21j/src/tc0/count16/dbgctrl.rs new file mode 100644 index 000000000000..0383e70d0429 --- /dev/null +++ b/pac/atsamc21j/src/tc0/count16/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Run During Debug"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Run During Debug"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/tc0/count16/drvctrl.rs b/pac/atsamc21j/src/tc0/count16/drvctrl.rs new file mode 100644 index 000000000000..323926b4b22d --- /dev/null +++ b/pac/atsamc21j/src/tc0/count16/drvctrl.rs @@ -0,0 +1,160 @@ +#[doc = "Register `DRVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DRVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INVEN0` reader - Output Waveform Invert Enable 0"] +pub struct INVEN0_R(crate::FieldReader); +impl INVEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN0` writer - Output Waveform Invert Enable 0"] +pub struct INVEN0_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `INVEN1` reader - Output Waveform Invert Enable 1"] +pub struct INVEN1_R(crate::FieldReader); +impl INVEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN1` writer - Output Waveform Invert Enable 1"] +pub struct INVEN1_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - Output Waveform Invert Enable 0"] + #[inline(always)] + pub fn inven0(&self) -> INVEN0_R { + INVEN0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Output Waveform Invert Enable 1"] + #[inline(always)] + pub fn inven1(&self) -> INVEN1_R { + INVEN1_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Output Waveform Invert Enable 0"] + #[inline(always)] + pub fn inven0(&mut self) -> INVEN0_W { + INVEN0_W { w: self } + } + #[doc = "Bit 1 - Output Waveform Invert Enable 1"] + #[inline(always)] + pub fn inven1(&mut self) -> INVEN1_W { + INVEN1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control C\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [drvctrl](index.html) module"] +pub struct DRVCTRL_SPEC; +impl crate::RegisterSpec for DRVCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [drvctrl::R](R) reader structure"] +impl crate::Readable for DRVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [drvctrl::W](W) writer structure"] +impl crate::Writable for DRVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DRVCTRL to value 0"] +impl crate::Resettable for DRVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/tc0/count16/evctrl.rs b/pac/atsamc21j/src/tc0/count16/evctrl.rs new file mode 100644 index 000000000000..7d4c38d486c1 --- /dev/null +++ b/pac/atsamc21j/src/tc0/count16/evctrl.rs @@ -0,0 +1,465 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Event Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EVACT_A { + #[doc = "0: Event action disabled"] + OFF = 0, + #[doc = "1: Start, restart or retrigger TC on event"] + RETRIGGER = 1, + #[doc = "2: Count on event"] + COUNT = 2, + #[doc = "3: Start TC on event"] + START = 3, + #[doc = "4: Time stamp capture"] + STAMP = 4, + #[doc = "5: Period catured in CC0, pulse width in CC1"] + PPW = 5, + #[doc = "6: Period catured in CC1, pulse width in CC0"] + PWP = 6, + #[doc = "7: Pulse width capture"] + PW = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EVACT_A) -> Self { + variant as _ + } +} +#[doc = "Field `EVACT` reader - Event Action"] +pub struct EVACT_R(crate::FieldReader); +impl EVACT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVACT_A { + match self.bits { + 0 => EVACT_A::OFF, + 1 => EVACT_A::RETRIGGER, + 2 => EVACT_A::COUNT, + 3 => EVACT_A::START, + 4 => EVACT_A::STAMP, + 5 => EVACT_A::PPW, + 6 => EVACT_A::PWP, + 7 => EVACT_A::PW, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == EVACT_A::OFF + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == EVACT_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `COUNT`"] + #[inline(always)] + pub fn is_count(&self) -> bool { + **self == EVACT_A::COUNT + } + #[doc = "Checks if the value of the field is `START`"] + #[inline(always)] + pub fn is_start(&self) -> bool { + **self == EVACT_A::START + } + #[doc = "Checks if the value of the field is `STAMP`"] + #[inline(always)] + pub fn is_stamp(&self) -> bool { + **self == EVACT_A::STAMP + } + #[doc = "Checks if the value of the field is `PPW`"] + #[inline(always)] + pub fn is_ppw(&self) -> bool { + **self == EVACT_A::PPW + } + #[doc = "Checks if the value of the field is `PWP`"] + #[inline(always)] + pub fn is_pwp(&self) -> bool { + **self == EVACT_A::PWP + } + #[doc = "Checks if the value of the field is `PW`"] + #[inline(always)] + pub fn is_pw(&self) -> bool { + **self == EVACT_A::PW + } +} +impl core::ops::Deref for EVACT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT` writer - Event Action"] +pub struct EVACT_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EVACT_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Event action disabled"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(EVACT_A::OFF) + } + #[doc = "Start, restart or retrigger TC on event"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(EVACT_A::RETRIGGER) + } + #[doc = "Count on event"] + #[inline(always)] + pub fn count(self) -> &'a mut W { + self.variant(EVACT_A::COUNT) + } + #[doc = "Start TC on event"] + #[inline(always)] + pub fn start(self) -> &'a mut W { + self.variant(EVACT_A::START) + } + #[doc = "Time stamp capture"] + #[inline(always)] + pub fn stamp(self) -> &'a mut W { + self.variant(EVACT_A::STAMP) + } + #[doc = "Period catured in CC0, pulse width in CC1"] + #[inline(always)] + pub fn ppw(self) -> &'a mut W { + self.variant(EVACT_A::PPW) + } + #[doc = "Period catured in CC1, pulse width in CC0"] + #[inline(always)] + pub fn pwp(self) -> &'a mut W { + self.variant(EVACT_A::PWP) + } + #[doc = "Pulse width capture"] + #[inline(always)] + pub fn pw(self) -> &'a mut W { + self.variant(EVACT_A::PW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u16 & 0x07); + self.w + } +} +#[doc = "Field `TCINV` reader - TC Event Input Polarity"] +pub struct TCINV_R(crate::FieldReader); +impl TCINV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCINV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCINV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCINV` writer - TC Event Input Polarity"] +pub struct TCINV_W<'a> { + w: &'a mut W, +} +impl<'a> TCINV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `TCEI` reader - TC Event Enable"] +pub struct TCEI_R(crate::FieldReader); +impl TCEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCEI` writer - TC Event Enable"] +pub struct TCEI_W<'a> { + w: &'a mut W, +} +impl<'a> TCEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `OVFEO` reader - Event Output Enable"] +pub struct OVFEO_R(crate::FieldReader); +impl OVFEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVFEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVFEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVFEO` writer - Event Output Enable"] +pub struct OVFEO_W<'a> { + w: &'a mut W, +} +impl<'a> OVFEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `MCEO0` reader - MC Event Output Enable 0"] +pub struct MCEO0_R(crate::FieldReader); +impl MCEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO0` writer - MC Event Output Enable 0"] +pub struct MCEO0_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u16 & 0x01) << 12); + self.w + } +} +#[doc = "Field `MCEO1` reader - MC Event Output Enable 1"] +pub struct MCEO1_R(crate::FieldReader); +impl MCEO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO1` writer - MC Event Output Enable 1"] +pub struct MCEO1_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u16 & 0x01) << 13); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Event Action"] + #[inline(always)] + pub fn evact(&self) -> EVACT_R { + EVACT_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 4 - TC Event Input Polarity"] + #[inline(always)] + pub fn tcinv(&self) -> TCINV_R { + TCINV_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - TC Event Enable"] + #[inline(always)] + pub fn tcei(&self) -> TCEI_R { + TCEI_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 8 - Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&self) -> OVFEO_R { + OVFEO_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 12 - MC Event Output Enable 0"] + #[inline(always)] + pub fn mceo0(&self) -> MCEO0_R { + MCEO0_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - MC Event Output Enable 1"] + #[inline(always)] + pub fn mceo1(&self) -> MCEO1_R { + MCEO1_R::new(((self.bits >> 13) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Event Action"] + #[inline(always)] + pub fn evact(&mut self) -> EVACT_W { + EVACT_W { w: self } + } + #[doc = "Bit 4 - TC Event Input Polarity"] + #[inline(always)] + pub fn tcinv(&mut self) -> TCINV_W { + TCINV_W { w: self } + } + #[doc = "Bit 5 - TC Event Enable"] + #[inline(always)] + pub fn tcei(&mut self) -> TCEI_W { + TCEI_W { w: self } + } + #[doc = "Bit 8 - Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&mut self) -> OVFEO_W { + OVFEO_W { w: self } + } + #[doc = "Bit 12 - MC Event Output Enable 0"] + #[inline(always)] + pub fn mceo0(&mut self) -> MCEO0_W { + MCEO0_W { w: self } + } + #[doc = "Bit 13 - MC Event Output Enable 1"] + #[inline(always)] + pub fn mceo1(&mut self) -> MCEO1_W { + MCEO1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/tc0/count16/intenclr.rs b/pac/atsamc21j/src/tc0/count16/intenclr.rs new file mode 100644 index 000000000000..af01ef5b7dca --- /dev/null +++ b/pac/atsamc21j/src/tc0/count16/intenclr.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - OVF Interrupt Disable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - OVF Interrupt Disable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - ERR Interrupt Disable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - ERR Interrupt Disable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MC0` reader - MC Interrupt Disable 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - MC Interrupt Disable 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - MC Interrupt Disable 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - MC Interrupt Disable 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - OVF Interrupt Disable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ERR Interrupt Disable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - MC Interrupt Disable 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - MC Interrupt Disable 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - OVF Interrupt Disable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - ERR Interrupt Disable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 4 - MC Interrupt Disable 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - MC Interrupt Disable 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/tc0/count16/intenset.rs b/pac/atsamc21j/src/tc0/count16/intenset.rs new file mode 100644 index 000000000000..0e1883a2f20a --- /dev/null +++ b/pac/atsamc21j/src/tc0/count16/intenset.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - OVF Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - OVF Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - ERR Interrupt Enable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - ERR Interrupt Enable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MC0` reader - MC Interrupt Enable 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - MC Interrupt Enable 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - MC Interrupt Enable 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - MC Interrupt Enable 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - OVF Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ERR Interrupt Enable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - MC Interrupt Enable 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - MC Interrupt Enable 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - OVF Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - ERR Interrupt Enable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 4 - MC Interrupt Enable 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - MC Interrupt Enable 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/tc0/count16/intflag.rs b/pac/atsamc21j/src/tc0/count16/intflag.rs new file mode 100644 index 000000000000..1dddffaf8e7f --- /dev/null +++ b/pac/atsamc21j/src/tc0/count16/intflag.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - OVF Interrupt Flag"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - OVF Interrupt Flag"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - ERR Interrupt Flag"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - ERR Interrupt Flag"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MC0` reader - MC Interrupt Flag 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - MC Interrupt Flag 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - MC Interrupt Flag 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - MC Interrupt Flag 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - OVF Interrupt Flag"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ERR Interrupt Flag"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - MC Interrupt Flag 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - MC Interrupt Flag 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - OVF Interrupt Flag"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - ERR Interrupt Flag"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 4 - MC Interrupt Flag 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - MC Interrupt Flag 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/tc0/count16/status.rs b/pac/atsamc21j/src/tc0/count16/status.rs new file mode 100644 index 000000000000..5088af446830 --- /dev/null +++ b/pac/atsamc21j/src/tc0/count16/status.rs @@ -0,0 +1,301 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `STOP` reader - Stop Status Flag"] +pub struct STOP_R(crate::FieldReader); +impl STOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STOP` writer - Stop Status Flag"] +pub struct STOP_W<'a> { + w: &'a mut W, +} +impl<'a> STOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SLAVE` reader - Slave Status Flag"] +pub struct SLAVE_R(crate::FieldReader); +impl SLAVE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLAVE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SLAVE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLAVE` writer - Slave Status Flag"] +pub struct SLAVE_W<'a> { + w: &'a mut W, +} +impl<'a> SLAVE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PERBUFV` reader - Synchronization Busy Status"] +pub struct PERBUFV_R(crate::FieldReader); +impl PERBUFV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PERBUFV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERBUFV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERBUFV` writer - Synchronization Busy Status"] +pub struct PERBUFV_W<'a> { + w: &'a mut W, +} +impl<'a> PERBUFV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CCBUFV0` reader - Compare channel buffer 0 valid"] +pub struct CCBUFV0_R(crate::FieldReader); +impl CCBUFV0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBUFV0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUFV0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUFV0` writer - Compare channel buffer 0 valid"] +pub struct CCBUFV0_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUFV0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `CCBUFV1` reader - Compare channel buffer 1 valid"] +pub struct CCBUFV1_R(crate::FieldReader); +impl CCBUFV1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBUFV1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUFV1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUFV1` writer - Compare channel buffer 1 valid"] +pub struct CCBUFV1_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUFV1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Stop Status Flag"] + #[inline(always)] + pub fn stop(&self) -> STOP_R { + STOP_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Slave Status Flag"] + #[inline(always)] + pub fn slave(&self) -> SLAVE_R { + SLAVE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 3 - Synchronization Busy Status"] + #[inline(always)] + pub fn perbufv(&self) -> PERBUFV_R { + PERBUFV_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Compare channel buffer 0 valid"] + #[inline(always)] + pub fn ccbufv0(&self) -> CCBUFV0_R { + CCBUFV0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Compare channel buffer 1 valid"] + #[inline(always)] + pub fn ccbufv1(&self) -> CCBUFV1_R { + CCBUFV1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Stop Status Flag"] + #[inline(always)] + pub fn stop(&mut self) -> STOP_W { + STOP_W { w: self } + } + #[doc = "Bit 1 - Slave Status Flag"] + #[inline(always)] + pub fn slave(&mut self) -> SLAVE_W { + SLAVE_W { w: self } + } + #[doc = "Bit 3 - Synchronization Busy Status"] + #[inline(always)] + pub fn perbufv(&mut self) -> PERBUFV_W { + PERBUFV_W { w: self } + } + #[doc = "Bit 4 - Compare channel buffer 0 valid"] + #[inline(always)] + pub fn ccbufv0(&mut self) -> CCBUFV0_W { + CCBUFV0_W { w: self } + } + #[doc = "Bit 5 - Compare channel buffer 1 valid"] + #[inline(always)] + pub fn ccbufv1(&mut self) -> CCBUFV1_W { + CCBUFV1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0x01"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pac/atsamc21j/src/tc0/count16/syncbusy.rs b/pac/atsamc21j/src/tc0/count16/syncbusy.rs new file mode 100644 index 000000000000..7ad8d91a84de --- /dev/null +++ b/pac/atsamc21j/src/tc0/count16/syncbusy.rs @@ -0,0 +1,193 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - swrst"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLB` reader - CTRLB"] +pub struct CTRLB_R(crate::FieldReader); +impl CTRLB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STATUS` reader - STATUS"] +pub struct STATUS_R(crate::FieldReader); +impl STATUS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STATUS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STATUS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` reader - Counter"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` reader - Period"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC0` reader - Compare Channel 0"] +pub struct CC0_R(crate::FieldReader); +impl CC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC1` reader - Compare Channel 1"] +pub struct CC1_R(crate::FieldReader); +impl CC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - swrst"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - CTRLB"] + #[inline(always)] + pub fn ctrlb(&self) -> CTRLB_R { + CTRLB_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - STATUS"] + #[inline(always)] + pub fn status(&self) -> STATUS_R { + STATUS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Counter"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Period"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Compare Channel 0"] + #[inline(always)] + pub fn cc0(&self) -> CC0_R { + CC0_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Compare Channel 1"] + #[inline(always)] + pub fn cc1(&self) -> CC1_R { + CC1_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +#[doc = "Synchronization Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/tc0/count16/wave.rs b/pac/atsamc21j/src/tc0/count16/wave.rs new file mode 100644 index 000000000000..46061b24b75d --- /dev/null +++ b/pac/atsamc21j/src/tc0/count16/wave.rs @@ -0,0 +1,178 @@ +#[doc = "Register `WAVE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WAVE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Waveform Generation Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WAVEGEN_A { + #[doc = "0: Normal frequency"] + NFRQ = 0, + #[doc = "1: Match frequency"] + MFRQ = 1, + #[doc = "2: Normal PWM"] + NPWM = 2, + #[doc = "3: Match PWM"] + MPWM = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WAVEGEN_A) -> Self { + variant as _ + } +} +#[doc = "Field `WAVEGEN` reader - Waveform Generation Mode"] +pub struct WAVEGEN_R(crate::FieldReader); +impl WAVEGEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WAVEGEN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> WAVEGEN_A { + match self.bits { + 0 => WAVEGEN_A::NFRQ, + 1 => WAVEGEN_A::MFRQ, + 2 => WAVEGEN_A::NPWM, + 3 => WAVEGEN_A::MPWM, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NFRQ`"] + #[inline(always)] + pub fn is_nfrq(&self) -> bool { + **self == WAVEGEN_A::NFRQ + } + #[doc = "Checks if the value of the field is `MFRQ`"] + #[inline(always)] + pub fn is_mfrq(&self) -> bool { + **self == WAVEGEN_A::MFRQ + } + #[doc = "Checks if the value of the field is `NPWM`"] + #[inline(always)] + pub fn is_npwm(&self) -> bool { + **self == WAVEGEN_A::NPWM + } + #[doc = "Checks if the value of the field is `MPWM`"] + #[inline(always)] + pub fn is_mpwm(&self) -> bool { + **self == WAVEGEN_A::MPWM + } +} +impl core::ops::Deref for WAVEGEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAVEGEN` writer - Waveform Generation Mode"] +pub struct WAVEGEN_W<'a> { + w: &'a mut W, +} +impl<'a> WAVEGEN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WAVEGEN_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Normal frequency"] + #[inline(always)] + pub fn nfrq(self) -> &'a mut W { + self.variant(WAVEGEN_A::NFRQ) + } + #[doc = "Match frequency"] + #[inline(always)] + pub fn mfrq(self) -> &'a mut W { + self.variant(WAVEGEN_A::MFRQ) + } + #[doc = "Normal PWM"] + #[inline(always)] + pub fn npwm(self) -> &'a mut W { + self.variant(WAVEGEN_A::NPWM) + } + #[doc = "Match PWM"] + #[inline(always)] + pub fn mpwm(self) -> &'a mut W { + self.variant(WAVEGEN_A::MPWM) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u8 & 0x03); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Waveform Generation Mode"] + #[inline(always)] + pub fn wavegen(&self) -> WAVEGEN_R { + WAVEGEN_R::new((self.bits & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Waveform Generation Mode"] + #[inline(always)] + pub fn wavegen(&mut self) -> WAVEGEN_W { + WAVEGEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Waveform Generation Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wave](index.html) module"] +pub struct WAVE_SPEC; +impl crate::RegisterSpec for WAVE_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [wave::R](R) reader structure"] +impl crate::Readable for WAVE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wave::W](W) writer structure"] +impl crate::Writable for WAVE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WAVE to value 0"] +impl crate::Resettable for WAVE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/tc0/count32.rs b/pac/atsamc21j/src/tc0/count32.rs new file mode 100644 index 000000000000..9062acfbbd7f --- /dev/null +++ b/pac/atsamc21j/src/tc0/count32.rs @@ -0,0 +1,60 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "CTRLBCLR register accessor: an alias for `Reg`"] +pub type CTRLBCLR = crate::Reg; +#[doc = "Control B Clear"] +pub mod ctrlbclr; +#[doc = "CTRLBSET register accessor: an alias for `Reg`"] +pub type CTRLBSET = crate::Reg; +#[doc = "Control B Set"] +pub mod ctrlbset; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "WAVE register accessor: an alias for `Reg`"] +pub type WAVE = crate::Reg; +#[doc = "Waveform Generation Control"] +pub mod wave; +#[doc = "DRVCTRL register accessor: an alias for `Reg`"] +pub type DRVCTRL = crate::Reg; +#[doc = "Control C"] +pub mod drvctrl; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Status"] +pub mod syncbusy; +#[doc = "COUNT register accessor: an alias for `Reg`"] +pub type COUNT = crate::Reg; +#[doc = "COUNT32 Count"] +pub mod count; +#[doc = "CC register accessor: an alias for `Reg`"] +pub type CC = crate::Reg; +#[doc = "COUNT32 Compare and Capture"] +pub mod cc; +#[doc = "CCBUF register accessor: an alias for `Reg`"] +pub type CCBUF = crate::Reg; +#[doc = "COUNT32 Compare and Capture Buffer"] +pub mod ccbuf; diff --git a/pac/atsamc21j/src/tc0/count32/cc.rs b/pac/atsamc21j/src/tc0/count32/cc.rs new file mode 100644 index 000000000000..512a1e01ffd4 --- /dev/null +++ b/pac/atsamc21j/src/tc0/count32/cc.rs @@ -0,0 +1,104 @@ +#[doc = "Register `CC[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CC[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CC` reader - Counter/Compare Value"] +pub struct CC_R(crate::FieldReader); +impl CC_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC` writer - Counter/Compare Value"] +pub struct CC_W<'a> { + w: &'a mut W, +} +impl<'a> CC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Counter/Compare Value"] + #[inline(always)] + pub fn cc(&self) -> CC_R { + CC_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Counter/Compare Value"] + #[inline(always)] + pub fn cc(&mut self) -> CC_W { + CC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT32 Compare and Capture\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc](index.html) module"] +pub struct CC_SPEC; +impl crate::RegisterSpec for CC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cc::R](R) reader structure"] +impl crate::Readable for CC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cc::W](W) writer structure"] +impl crate::Writable for CC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CC[%s] +to value 0"] +impl crate::Resettable for CC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/tc0/count32/ccbuf.rs b/pac/atsamc21j/src/tc0/count32/ccbuf.rs new file mode 100644 index 000000000000..9fb2d9f8f66c --- /dev/null +++ b/pac/atsamc21j/src/tc0/count32/ccbuf.rs @@ -0,0 +1,104 @@ +#[doc = "Register `CCBUF[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CCBUF[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CCBUF` reader - Counter/Compare Buffer Value"] +pub struct CCBUF_R(crate::FieldReader); +impl CCBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CCBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUF` writer - Counter/Compare Buffer Value"] +pub struct CCBUF_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Counter/Compare Buffer Value"] + #[inline(always)] + pub fn ccbuf(&self) -> CCBUF_R { + CCBUF_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Counter/Compare Buffer Value"] + #[inline(always)] + pub fn ccbuf(&mut self) -> CCBUF_W { + CCBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT32 Compare and Capture Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccbuf](index.html) module"] +pub struct CCBUF_SPEC; +impl crate::RegisterSpec for CCBUF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ccbuf::R](R) reader structure"] +impl crate::Readable for CCBUF_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ccbuf::W](W) writer structure"] +impl crate::Writable for CCBUF_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CCBUF[%s] +to value 0"] +impl crate::Resettable for CCBUF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/tc0/count32/count.rs b/pac/atsamc21j/src/tc0/count32/count.rs new file mode 100644 index 000000000000..9aea527a8b3c --- /dev/null +++ b/pac/atsamc21j/src/tc0/count32/count.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT32 Count\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count](index.html) module"] +pub struct COUNT_SPEC; +impl crate::RegisterSpec for COUNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [count::R](R) reader structure"] +impl crate::Readable for COUNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count::W](W) writer structure"] +impl crate::Writable for COUNT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT to value 0"] +impl crate::Resettable for COUNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/tc0/count32/ctrla.rs b/pac/atsamc21j/src/tc0/count32/ctrla.rs new file mode 100644 index 000000000000..cadcddaaead8 --- /dev/null +++ b/pac/atsamc21j/src/tc0/count32/ctrla.rs @@ -0,0 +1,851 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Timer Counter Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: Counter in 16-bit mode"] + COUNT16 = 0, + #[doc = "1: Counter in 8-bit mode"] + COUNT8 = 1, + #[doc = "2: Counter in 32-bit mode"] + COUNT32 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Timer Counter Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::COUNT16), + 1 => Some(MODE_A::COUNT8), + 2 => Some(MODE_A::COUNT32), + _ => None, + } + } + #[doc = "Checks if the value of the field is `COUNT16`"] + #[inline(always)] + pub fn is_count16(&self) -> bool { + **self == MODE_A::COUNT16 + } + #[doc = "Checks if the value of the field is `COUNT8`"] + #[inline(always)] + pub fn is_count8(&self) -> bool { + **self == MODE_A::COUNT8 + } + #[doc = "Checks if the value of the field is `COUNT32`"] + #[inline(always)] + pub fn is_count32(&self) -> bool { + **self == MODE_A::COUNT32 + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Timer Counter Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Counter in 16-bit mode"] + #[inline(always)] + pub fn count16(self) -> &'a mut W { + self.variant(MODE_A::COUNT16) + } + #[doc = "Counter in 8-bit mode"] + #[inline(always)] + pub fn count8(self) -> &'a mut W { + self.variant(MODE_A::COUNT8) + } + #[doc = "Counter in 32-bit mode"] + #[inline(always)] + pub fn count32(self) -> &'a mut W { + self.variant(MODE_A::COUNT32) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u32 & 0x03) << 2); + self.w + } +} +#[doc = "Prescaler and Counter Synchronization\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCSYNC_A { + #[doc = "0: Reload or reset the counter on next generic clock"] + GCLK = 0, + #[doc = "1: Reload or reset the counter on next prescaler clock"] + PRESC = 1, + #[doc = "2: Reload or reset the counter on next generic clock and reset the prescaler counter"] + RESYNC = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCSYNC_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCSYNC` reader - Prescaler and Counter Synchronization"] +pub struct PRESCSYNC_R(crate::FieldReader); +impl PRESCSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCSYNC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCSYNC_A::GCLK), + 1 => Some(PRESCSYNC_A::PRESC), + 2 => Some(PRESCSYNC_A::RESYNC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `GCLK`"] + #[inline(always)] + pub fn is_gclk(&self) -> bool { + **self == PRESCSYNC_A::GCLK + } + #[doc = "Checks if the value of the field is `PRESC`"] + #[inline(always)] + pub fn is_presc(&self) -> bool { + **self == PRESCSYNC_A::PRESC + } + #[doc = "Checks if the value of the field is `RESYNC`"] + #[inline(always)] + pub fn is_resync(&self) -> bool { + **self == PRESCSYNC_A::RESYNC + } +} +impl core::ops::Deref for PRESCSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCSYNC` writer - Prescaler and Counter Synchronization"] +pub struct PRESCSYNC_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCSYNC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCSYNC_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Reload or reset the counter on next generic clock"] + #[inline(always)] + pub fn gclk(self) -> &'a mut W { + self.variant(PRESCSYNC_A::GCLK) + } + #[doc = "Reload or reset the counter on next prescaler clock"] + #[inline(always)] + pub fn presc(self) -> &'a mut W { + self.variant(PRESCSYNC_A::PRESC) + } + #[doc = "Reload or reset the counter on next generic clock and reset the prescaler counter"] + #[inline(always)] + pub fn resync(self) -> &'a mut W { + self.variant(PRESCSYNC_A::RESYNC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u32 & 0x03) << 4); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - Clock On Demand"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - Clock On Demand"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: Prescaler: GCLK_TC"] + DIV1 = 0, + #[doc = "1: Prescaler: GCLK_TC/2"] + DIV2 = 1, + #[doc = "2: Prescaler: GCLK_TC/4"] + DIV4 = 2, + #[doc = "3: Prescaler: GCLK_TC/8"] + DIV8 = 3, + #[doc = "4: Prescaler: GCLK_TC/16"] + DIV16 = 4, + #[doc = "5: Prescaler: GCLK_TC/64"] + DIV64 = 5, + #[doc = "6: Prescaler: GCLK_TC/256"] + DIV256 = 6, + #[doc = "7: Prescaler: GCLK_TC/1024"] + DIV1024 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PRESCALER_A { + match self.bits { + 0 => PRESCALER_A::DIV1, + 1 => PRESCALER_A::DIV2, + 2 => PRESCALER_A::DIV4, + 3 => PRESCALER_A::DIV8, + 4 => PRESCALER_A::DIV16, + 5 => PRESCALER_A::DIV64, + 6 => PRESCALER_A::DIV256, + 7 => PRESCALER_A::DIV1024, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == PRESCALER_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PRESCALER_A::DIV1024 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Prescaler: GCLK_TC"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1) + } + #[doc = "Prescaler: GCLK_TC/2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "Prescaler: GCLK_TC/4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "Prescaler: GCLK_TC/8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "Prescaler: GCLK_TC/16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "Prescaler: GCLK_TC/64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "Prescaler: GCLK_TC/256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = "Prescaler: GCLK_TC/1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +#[doc = "Field `ALOCK` reader - Auto Lock"] +pub struct ALOCK_R(crate::FieldReader); +impl ALOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALOCK` writer - Auto Lock"] +pub struct ALOCK_W<'a> { + w: &'a mut W, +} +impl<'a> ALOCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `CAPTEN0` reader - Capture Channel 0 Enable"] +pub struct CAPTEN0_R(crate::FieldReader); +impl CAPTEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CAPTEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CAPTEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAPTEN0` writer - Capture Channel 0 Enable"] +pub struct CAPTEN0_W<'a> { + w: &'a mut W, +} +impl<'a> CAPTEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `CAPTEN1` reader - Capture Channel 1 Enable"] +pub struct CAPTEN1_R(crate::FieldReader); +impl CAPTEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CAPTEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CAPTEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAPTEN1` writer - Capture Channel 1 Enable"] +pub struct CAPTEN1_W<'a> { + w: &'a mut W, +} +impl<'a> CAPTEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `COPEN0` reader - Capture On Pin 0 Enable"] +pub struct COPEN0_R(crate::FieldReader); +impl COPEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COPEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COPEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COPEN0` writer - Capture On Pin 0 Enable"] +pub struct COPEN0_W<'a> { + w: &'a mut W, +} +impl<'a> COPEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `COPEN1` reader - Capture On Pin 1 Enable"] +pub struct COPEN1_R(crate::FieldReader); +impl COPEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COPEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COPEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COPEN1` writer - Capture On Pin 1 Enable"] +pub struct COPEN1_W<'a> { + w: &'a mut W, +} +impl<'a> COPEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:3 - Timer Counter Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bits 4:5 - Prescaler and Counter Synchronization"] + #[inline(always)] + pub fn prescsync(&self) -> PRESCSYNC_R { + PRESCSYNC_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Clock On Demand"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 11 - Auto Lock"] + #[inline(always)] + pub fn alock(&self) -> ALOCK_R { + ALOCK_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 16 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn capten0(&self) -> CAPTEN0_R { + CAPTEN0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn capten1(&self) -> CAPTEN1_R { + CAPTEN1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 20 - Capture On Pin 0 Enable"] + #[inline(always)] + pub fn copen0(&self) -> COPEN0_R { + COPEN0_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Capture On Pin 1 Enable"] + #[inline(always)] + pub fn copen1(&self) -> COPEN1_R { + COPEN1_R::new(((self.bits >> 21) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:3 - Timer Counter Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bits 4:5 - Prescaler and Counter Synchronization"] + #[inline(always)] + pub fn prescsync(&mut self) -> PRESCSYNC_W { + PRESCSYNC_W { w: self } + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - Clock On Demand"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Bit 11 - Auto Lock"] + #[inline(always)] + pub fn alock(&mut self) -> ALOCK_W { + ALOCK_W { w: self } + } + #[doc = "Bit 16 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn capten0(&mut self) -> CAPTEN0_W { + CAPTEN0_W { w: self } + } + #[doc = "Bit 17 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn capten1(&mut self) -> CAPTEN1_W { + CAPTEN1_W { w: self } + } + #[doc = "Bit 20 - Capture On Pin 0 Enable"] + #[inline(always)] + pub fn copen0(&mut self) -> COPEN0_W { + COPEN0_W { w: self } + } + #[doc = "Bit 21 - Capture On Pin 1 Enable"] + #[inline(always)] + pub fn copen1(&mut self) -> COPEN1_W { + COPEN1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/tc0/count32/ctrlbclr.rs b/pac/atsamc21j/src/tc0/count32/ctrlbclr.rs new file mode 100644 index 000000000000..76265674036a --- /dev/null +++ b/pac/atsamc21j/src/tc0/count32/ctrlbclr.rs @@ -0,0 +1,345 @@ +#[doc = "Register `CTRLBCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Counter Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `LUPD` reader - Lock Update"] +pub struct LUPD_R(crate::FieldReader); +impl LUPD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LUPD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LUPD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LUPD` writer - Lock Update"] +pub struct LUPD_W<'a> { + w: &'a mut W, +} +impl<'a> LUPD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ONESHOT` reader - One-Shot on Counter"] +pub struct ONESHOT_R(crate::FieldReader); +impl ONESHOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONESHOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONESHOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONESHOT` writer - One-Shot on Counter"] +pub struct ONESHOT_W<'a> { + w: &'a mut W, +} +impl<'a> ONESHOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Force a start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force a stop"] + STOP = 2, + #[doc = "3: Force update of double-buffered register"] + UPDATE = 3, + #[doc = "4: Force a read synchronization of COUNT"] + READSYNC = 4, + #[doc = "5: One-shot DMA trigger"] + DMAOS = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NONE), + 1 => Some(CMD_A::RETRIGGER), + 2 => Some(CMD_A::STOP), + 3 => Some(CMD_A::UPDATE), + 4 => Some(CMD_A::READSYNC), + 5 => Some(CMD_A::DMAOS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == CMD_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == CMD_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == CMD_A::STOP + } + #[doc = "Checks if the value of the field is `UPDATE`"] + #[inline(always)] + pub fn is_update(&self) -> bool { + **self == CMD_A::UPDATE + } + #[doc = "Checks if the value of the field is `READSYNC`"] + #[inline(always)] + pub fn is_readsync(&self) -> bool { + **self == CMD_A::READSYNC + } + #[doc = "Checks if the value of the field is `DMAOS`"] + #[inline(always)] + pub fn is_dmaos(&self) -> bool { + **self == CMD_A::DMAOS + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMD_A::NONE) + } + #[doc = "Force a start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMD_A::RETRIGGER) + } + #[doc = "Force a stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMD_A::STOP) + } + #[doc = "Force update of double-buffered register"] + #[inline(always)] + pub fn update(self) -> &'a mut W { + self.variant(CMD_A::UPDATE) + } + #[doc = "Force a read synchronization of COUNT"] + #[inline(always)] + pub fn readsync(self) -> &'a mut W { + self.variant(CMD_A::READSYNC) + } + #[doc = "One-shot DMA trigger"] + #[inline(always)] + pub fn dmaos(self) -> &'a mut W { + self.variant(CMD_A::DMAOS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 5)) | ((value as u8 & 0x07) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&self) -> LUPD_R { + LUPD_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 5) & 0x07) as u8) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&mut self) -> LUPD_W { + LUPD_W { w: self } + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&mut self) -> ONESHOT_W { + ONESHOT_W { w: self } + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbclr](index.html) module"] +pub struct CTRLBCLR_SPEC; +impl crate::RegisterSpec for CTRLBCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbclr::R](R) reader structure"] +impl crate::Readable for CTRLBCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbclr::W](W) writer structure"] +impl crate::Writable for CTRLBCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLBCLR to value 0"] +impl crate::Resettable for CTRLBCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/tc0/count32/ctrlbset.rs b/pac/atsamc21j/src/tc0/count32/ctrlbset.rs new file mode 100644 index 000000000000..610914c9c7c8 --- /dev/null +++ b/pac/atsamc21j/src/tc0/count32/ctrlbset.rs @@ -0,0 +1,345 @@ +#[doc = "Register `CTRLBSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Counter Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `LUPD` reader - Lock Update"] +pub struct LUPD_R(crate::FieldReader); +impl LUPD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LUPD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LUPD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LUPD` writer - Lock Update"] +pub struct LUPD_W<'a> { + w: &'a mut W, +} +impl<'a> LUPD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ONESHOT` reader - One-Shot on Counter"] +pub struct ONESHOT_R(crate::FieldReader); +impl ONESHOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONESHOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONESHOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONESHOT` writer - One-Shot on Counter"] +pub struct ONESHOT_W<'a> { + w: &'a mut W, +} +impl<'a> ONESHOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Force a start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force a stop"] + STOP = 2, + #[doc = "3: Force update of double-buffered register"] + UPDATE = 3, + #[doc = "4: Force a read synchronization of COUNT"] + READSYNC = 4, + #[doc = "5: One-shot DMA trigger"] + DMAOS = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NONE), + 1 => Some(CMD_A::RETRIGGER), + 2 => Some(CMD_A::STOP), + 3 => Some(CMD_A::UPDATE), + 4 => Some(CMD_A::READSYNC), + 5 => Some(CMD_A::DMAOS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == CMD_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == CMD_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == CMD_A::STOP + } + #[doc = "Checks if the value of the field is `UPDATE`"] + #[inline(always)] + pub fn is_update(&self) -> bool { + **self == CMD_A::UPDATE + } + #[doc = "Checks if the value of the field is `READSYNC`"] + #[inline(always)] + pub fn is_readsync(&self) -> bool { + **self == CMD_A::READSYNC + } + #[doc = "Checks if the value of the field is `DMAOS`"] + #[inline(always)] + pub fn is_dmaos(&self) -> bool { + **self == CMD_A::DMAOS + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMD_A::NONE) + } + #[doc = "Force a start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMD_A::RETRIGGER) + } + #[doc = "Force a stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMD_A::STOP) + } + #[doc = "Force update of double-buffered register"] + #[inline(always)] + pub fn update(self) -> &'a mut W { + self.variant(CMD_A::UPDATE) + } + #[doc = "Force a read synchronization of COUNT"] + #[inline(always)] + pub fn readsync(self) -> &'a mut W { + self.variant(CMD_A::READSYNC) + } + #[doc = "One-shot DMA trigger"] + #[inline(always)] + pub fn dmaos(self) -> &'a mut W { + self.variant(CMD_A::DMAOS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 5)) | ((value as u8 & 0x07) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&self) -> LUPD_R { + LUPD_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 5) & 0x07) as u8) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&mut self) -> LUPD_W { + LUPD_W { w: self } + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&mut self) -> ONESHOT_W { + ONESHOT_W { w: self } + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbset](index.html) module"] +pub struct CTRLBSET_SPEC; +impl crate::RegisterSpec for CTRLBSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbset::R](R) reader structure"] +impl crate::Readable for CTRLBSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbset::W](W) writer structure"] +impl crate::Writable for CTRLBSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLBSET to value 0"] +impl crate::Resettable for CTRLBSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/tc0/count32/dbgctrl.rs b/pac/atsamc21j/src/tc0/count32/dbgctrl.rs new file mode 100644 index 000000000000..0383e70d0429 --- /dev/null +++ b/pac/atsamc21j/src/tc0/count32/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Run During Debug"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Run During Debug"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/tc0/count32/drvctrl.rs b/pac/atsamc21j/src/tc0/count32/drvctrl.rs new file mode 100644 index 000000000000..323926b4b22d --- /dev/null +++ b/pac/atsamc21j/src/tc0/count32/drvctrl.rs @@ -0,0 +1,160 @@ +#[doc = "Register `DRVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DRVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INVEN0` reader - Output Waveform Invert Enable 0"] +pub struct INVEN0_R(crate::FieldReader); +impl INVEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN0` writer - Output Waveform Invert Enable 0"] +pub struct INVEN0_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `INVEN1` reader - Output Waveform Invert Enable 1"] +pub struct INVEN1_R(crate::FieldReader); +impl INVEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN1` writer - Output Waveform Invert Enable 1"] +pub struct INVEN1_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - Output Waveform Invert Enable 0"] + #[inline(always)] + pub fn inven0(&self) -> INVEN0_R { + INVEN0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Output Waveform Invert Enable 1"] + #[inline(always)] + pub fn inven1(&self) -> INVEN1_R { + INVEN1_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Output Waveform Invert Enable 0"] + #[inline(always)] + pub fn inven0(&mut self) -> INVEN0_W { + INVEN0_W { w: self } + } + #[doc = "Bit 1 - Output Waveform Invert Enable 1"] + #[inline(always)] + pub fn inven1(&mut self) -> INVEN1_W { + INVEN1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control C\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [drvctrl](index.html) module"] +pub struct DRVCTRL_SPEC; +impl crate::RegisterSpec for DRVCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [drvctrl::R](R) reader structure"] +impl crate::Readable for DRVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [drvctrl::W](W) writer structure"] +impl crate::Writable for DRVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DRVCTRL to value 0"] +impl crate::Resettable for DRVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/tc0/count32/evctrl.rs b/pac/atsamc21j/src/tc0/count32/evctrl.rs new file mode 100644 index 000000000000..7d4c38d486c1 --- /dev/null +++ b/pac/atsamc21j/src/tc0/count32/evctrl.rs @@ -0,0 +1,465 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Event Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EVACT_A { + #[doc = "0: Event action disabled"] + OFF = 0, + #[doc = "1: Start, restart or retrigger TC on event"] + RETRIGGER = 1, + #[doc = "2: Count on event"] + COUNT = 2, + #[doc = "3: Start TC on event"] + START = 3, + #[doc = "4: Time stamp capture"] + STAMP = 4, + #[doc = "5: Period catured in CC0, pulse width in CC1"] + PPW = 5, + #[doc = "6: Period catured in CC1, pulse width in CC0"] + PWP = 6, + #[doc = "7: Pulse width capture"] + PW = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EVACT_A) -> Self { + variant as _ + } +} +#[doc = "Field `EVACT` reader - Event Action"] +pub struct EVACT_R(crate::FieldReader); +impl EVACT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVACT_A { + match self.bits { + 0 => EVACT_A::OFF, + 1 => EVACT_A::RETRIGGER, + 2 => EVACT_A::COUNT, + 3 => EVACT_A::START, + 4 => EVACT_A::STAMP, + 5 => EVACT_A::PPW, + 6 => EVACT_A::PWP, + 7 => EVACT_A::PW, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == EVACT_A::OFF + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == EVACT_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `COUNT`"] + #[inline(always)] + pub fn is_count(&self) -> bool { + **self == EVACT_A::COUNT + } + #[doc = "Checks if the value of the field is `START`"] + #[inline(always)] + pub fn is_start(&self) -> bool { + **self == EVACT_A::START + } + #[doc = "Checks if the value of the field is `STAMP`"] + #[inline(always)] + pub fn is_stamp(&self) -> bool { + **self == EVACT_A::STAMP + } + #[doc = "Checks if the value of the field is `PPW`"] + #[inline(always)] + pub fn is_ppw(&self) -> bool { + **self == EVACT_A::PPW + } + #[doc = "Checks if the value of the field is `PWP`"] + #[inline(always)] + pub fn is_pwp(&self) -> bool { + **self == EVACT_A::PWP + } + #[doc = "Checks if the value of the field is `PW`"] + #[inline(always)] + pub fn is_pw(&self) -> bool { + **self == EVACT_A::PW + } +} +impl core::ops::Deref for EVACT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT` writer - Event Action"] +pub struct EVACT_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EVACT_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Event action disabled"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(EVACT_A::OFF) + } + #[doc = "Start, restart or retrigger TC on event"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(EVACT_A::RETRIGGER) + } + #[doc = "Count on event"] + #[inline(always)] + pub fn count(self) -> &'a mut W { + self.variant(EVACT_A::COUNT) + } + #[doc = "Start TC on event"] + #[inline(always)] + pub fn start(self) -> &'a mut W { + self.variant(EVACT_A::START) + } + #[doc = "Time stamp capture"] + #[inline(always)] + pub fn stamp(self) -> &'a mut W { + self.variant(EVACT_A::STAMP) + } + #[doc = "Period catured in CC0, pulse width in CC1"] + #[inline(always)] + pub fn ppw(self) -> &'a mut W { + self.variant(EVACT_A::PPW) + } + #[doc = "Period catured in CC1, pulse width in CC0"] + #[inline(always)] + pub fn pwp(self) -> &'a mut W { + self.variant(EVACT_A::PWP) + } + #[doc = "Pulse width capture"] + #[inline(always)] + pub fn pw(self) -> &'a mut W { + self.variant(EVACT_A::PW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u16 & 0x07); + self.w + } +} +#[doc = "Field `TCINV` reader - TC Event Input Polarity"] +pub struct TCINV_R(crate::FieldReader); +impl TCINV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCINV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCINV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCINV` writer - TC Event Input Polarity"] +pub struct TCINV_W<'a> { + w: &'a mut W, +} +impl<'a> TCINV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `TCEI` reader - TC Event Enable"] +pub struct TCEI_R(crate::FieldReader); +impl TCEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCEI` writer - TC Event Enable"] +pub struct TCEI_W<'a> { + w: &'a mut W, +} +impl<'a> TCEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `OVFEO` reader - Event Output Enable"] +pub struct OVFEO_R(crate::FieldReader); +impl OVFEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVFEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVFEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVFEO` writer - Event Output Enable"] +pub struct OVFEO_W<'a> { + w: &'a mut W, +} +impl<'a> OVFEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `MCEO0` reader - MC Event Output Enable 0"] +pub struct MCEO0_R(crate::FieldReader); +impl MCEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO0` writer - MC Event Output Enable 0"] +pub struct MCEO0_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u16 & 0x01) << 12); + self.w + } +} +#[doc = "Field `MCEO1` reader - MC Event Output Enable 1"] +pub struct MCEO1_R(crate::FieldReader); +impl MCEO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO1` writer - MC Event Output Enable 1"] +pub struct MCEO1_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u16 & 0x01) << 13); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Event Action"] + #[inline(always)] + pub fn evact(&self) -> EVACT_R { + EVACT_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 4 - TC Event Input Polarity"] + #[inline(always)] + pub fn tcinv(&self) -> TCINV_R { + TCINV_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - TC Event Enable"] + #[inline(always)] + pub fn tcei(&self) -> TCEI_R { + TCEI_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 8 - Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&self) -> OVFEO_R { + OVFEO_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 12 - MC Event Output Enable 0"] + #[inline(always)] + pub fn mceo0(&self) -> MCEO0_R { + MCEO0_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - MC Event Output Enable 1"] + #[inline(always)] + pub fn mceo1(&self) -> MCEO1_R { + MCEO1_R::new(((self.bits >> 13) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Event Action"] + #[inline(always)] + pub fn evact(&mut self) -> EVACT_W { + EVACT_W { w: self } + } + #[doc = "Bit 4 - TC Event Input Polarity"] + #[inline(always)] + pub fn tcinv(&mut self) -> TCINV_W { + TCINV_W { w: self } + } + #[doc = "Bit 5 - TC Event Enable"] + #[inline(always)] + pub fn tcei(&mut self) -> TCEI_W { + TCEI_W { w: self } + } + #[doc = "Bit 8 - Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&mut self) -> OVFEO_W { + OVFEO_W { w: self } + } + #[doc = "Bit 12 - MC Event Output Enable 0"] + #[inline(always)] + pub fn mceo0(&mut self) -> MCEO0_W { + MCEO0_W { w: self } + } + #[doc = "Bit 13 - MC Event Output Enable 1"] + #[inline(always)] + pub fn mceo1(&mut self) -> MCEO1_W { + MCEO1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/tc0/count32/intenclr.rs b/pac/atsamc21j/src/tc0/count32/intenclr.rs new file mode 100644 index 000000000000..af01ef5b7dca --- /dev/null +++ b/pac/atsamc21j/src/tc0/count32/intenclr.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - OVF Interrupt Disable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - OVF Interrupt Disable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - ERR Interrupt Disable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - ERR Interrupt Disable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MC0` reader - MC Interrupt Disable 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - MC Interrupt Disable 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - MC Interrupt Disable 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - MC Interrupt Disable 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - OVF Interrupt Disable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ERR Interrupt Disable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - MC Interrupt Disable 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - MC Interrupt Disable 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - OVF Interrupt Disable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - ERR Interrupt Disable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 4 - MC Interrupt Disable 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - MC Interrupt Disable 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/tc0/count32/intenset.rs b/pac/atsamc21j/src/tc0/count32/intenset.rs new file mode 100644 index 000000000000..0e1883a2f20a --- /dev/null +++ b/pac/atsamc21j/src/tc0/count32/intenset.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - OVF Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - OVF Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - ERR Interrupt Enable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - ERR Interrupt Enable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MC0` reader - MC Interrupt Enable 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - MC Interrupt Enable 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - MC Interrupt Enable 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - MC Interrupt Enable 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - OVF Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ERR Interrupt Enable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - MC Interrupt Enable 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - MC Interrupt Enable 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - OVF Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - ERR Interrupt Enable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 4 - MC Interrupt Enable 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - MC Interrupt Enable 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/tc0/count32/intflag.rs b/pac/atsamc21j/src/tc0/count32/intflag.rs new file mode 100644 index 000000000000..1dddffaf8e7f --- /dev/null +++ b/pac/atsamc21j/src/tc0/count32/intflag.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - OVF Interrupt Flag"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - OVF Interrupt Flag"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - ERR Interrupt Flag"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - ERR Interrupt Flag"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MC0` reader - MC Interrupt Flag 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - MC Interrupt Flag 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - MC Interrupt Flag 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - MC Interrupt Flag 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - OVF Interrupt Flag"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ERR Interrupt Flag"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - MC Interrupt Flag 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - MC Interrupt Flag 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - OVF Interrupt Flag"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - ERR Interrupt Flag"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 4 - MC Interrupt Flag 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - MC Interrupt Flag 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/tc0/count32/status.rs b/pac/atsamc21j/src/tc0/count32/status.rs new file mode 100644 index 000000000000..5088af446830 --- /dev/null +++ b/pac/atsamc21j/src/tc0/count32/status.rs @@ -0,0 +1,301 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `STOP` reader - Stop Status Flag"] +pub struct STOP_R(crate::FieldReader); +impl STOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STOP` writer - Stop Status Flag"] +pub struct STOP_W<'a> { + w: &'a mut W, +} +impl<'a> STOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SLAVE` reader - Slave Status Flag"] +pub struct SLAVE_R(crate::FieldReader); +impl SLAVE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLAVE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SLAVE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLAVE` writer - Slave Status Flag"] +pub struct SLAVE_W<'a> { + w: &'a mut W, +} +impl<'a> SLAVE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PERBUFV` reader - Synchronization Busy Status"] +pub struct PERBUFV_R(crate::FieldReader); +impl PERBUFV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PERBUFV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERBUFV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERBUFV` writer - Synchronization Busy Status"] +pub struct PERBUFV_W<'a> { + w: &'a mut W, +} +impl<'a> PERBUFV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CCBUFV0` reader - Compare channel buffer 0 valid"] +pub struct CCBUFV0_R(crate::FieldReader); +impl CCBUFV0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBUFV0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUFV0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUFV0` writer - Compare channel buffer 0 valid"] +pub struct CCBUFV0_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUFV0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `CCBUFV1` reader - Compare channel buffer 1 valid"] +pub struct CCBUFV1_R(crate::FieldReader); +impl CCBUFV1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBUFV1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUFV1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUFV1` writer - Compare channel buffer 1 valid"] +pub struct CCBUFV1_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUFV1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Stop Status Flag"] + #[inline(always)] + pub fn stop(&self) -> STOP_R { + STOP_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Slave Status Flag"] + #[inline(always)] + pub fn slave(&self) -> SLAVE_R { + SLAVE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 3 - Synchronization Busy Status"] + #[inline(always)] + pub fn perbufv(&self) -> PERBUFV_R { + PERBUFV_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Compare channel buffer 0 valid"] + #[inline(always)] + pub fn ccbufv0(&self) -> CCBUFV0_R { + CCBUFV0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Compare channel buffer 1 valid"] + #[inline(always)] + pub fn ccbufv1(&self) -> CCBUFV1_R { + CCBUFV1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Stop Status Flag"] + #[inline(always)] + pub fn stop(&mut self) -> STOP_W { + STOP_W { w: self } + } + #[doc = "Bit 1 - Slave Status Flag"] + #[inline(always)] + pub fn slave(&mut self) -> SLAVE_W { + SLAVE_W { w: self } + } + #[doc = "Bit 3 - Synchronization Busy Status"] + #[inline(always)] + pub fn perbufv(&mut self) -> PERBUFV_W { + PERBUFV_W { w: self } + } + #[doc = "Bit 4 - Compare channel buffer 0 valid"] + #[inline(always)] + pub fn ccbufv0(&mut self) -> CCBUFV0_W { + CCBUFV0_W { w: self } + } + #[doc = "Bit 5 - Compare channel buffer 1 valid"] + #[inline(always)] + pub fn ccbufv1(&mut self) -> CCBUFV1_W { + CCBUFV1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0x01"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pac/atsamc21j/src/tc0/count32/syncbusy.rs b/pac/atsamc21j/src/tc0/count32/syncbusy.rs new file mode 100644 index 000000000000..7ad8d91a84de --- /dev/null +++ b/pac/atsamc21j/src/tc0/count32/syncbusy.rs @@ -0,0 +1,193 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - swrst"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLB` reader - CTRLB"] +pub struct CTRLB_R(crate::FieldReader); +impl CTRLB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STATUS` reader - STATUS"] +pub struct STATUS_R(crate::FieldReader); +impl STATUS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STATUS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STATUS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` reader - Counter"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` reader - Period"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC0` reader - Compare Channel 0"] +pub struct CC0_R(crate::FieldReader); +impl CC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC1` reader - Compare Channel 1"] +pub struct CC1_R(crate::FieldReader); +impl CC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - swrst"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - CTRLB"] + #[inline(always)] + pub fn ctrlb(&self) -> CTRLB_R { + CTRLB_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - STATUS"] + #[inline(always)] + pub fn status(&self) -> STATUS_R { + STATUS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Counter"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Period"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Compare Channel 0"] + #[inline(always)] + pub fn cc0(&self) -> CC0_R { + CC0_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Compare Channel 1"] + #[inline(always)] + pub fn cc1(&self) -> CC1_R { + CC1_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +#[doc = "Synchronization Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/tc0/count32/wave.rs b/pac/atsamc21j/src/tc0/count32/wave.rs new file mode 100644 index 000000000000..46061b24b75d --- /dev/null +++ b/pac/atsamc21j/src/tc0/count32/wave.rs @@ -0,0 +1,178 @@ +#[doc = "Register `WAVE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WAVE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Waveform Generation Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WAVEGEN_A { + #[doc = "0: Normal frequency"] + NFRQ = 0, + #[doc = "1: Match frequency"] + MFRQ = 1, + #[doc = "2: Normal PWM"] + NPWM = 2, + #[doc = "3: Match PWM"] + MPWM = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WAVEGEN_A) -> Self { + variant as _ + } +} +#[doc = "Field `WAVEGEN` reader - Waveform Generation Mode"] +pub struct WAVEGEN_R(crate::FieldReader); +impl WAVEGEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WAVEGEN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> WAVEGEN_A { + match self.bits { + 0 => WAVEGEN_A::NFRQ, + 1 => WAVEGEN_A::MFRQ, + 2 => WAVEGEN_A::NPWM, + 3 => WAVEGEN_A::MPWM, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NFRQ`"] + #[inline(always)] + pub fn is_nfrq(&self) -> bool { + **self == WAVEGEN_A::NFRQ + } + #[doc = "Checks if the value of the field is `MFRQ`"] + #[inline(always)] + pub fn is_mfrq(&self) -> bool { + **self == WAVEGEN_A::MFRQ + } + #[doc = "Checks if the value of the field is `NPWM`"] + #[inline(always)] + pub fn is_npwm(&self) -> bool { + **self == WAVEGEN_A::NPWM + } + #[doc = "Checks if the value of the field is `MPWM`"] + #[inline(always)] + pub fn is_mpwm(&self) -> bool { + **self == WAVEGEN_A::MPWM + } +} +impl core::ops::Deref for WAVEGEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAVEGEN` writer - Waveform Generation Mode"] +pub struct WAVEGEN_W<'a> { + w: &'a mut W, +} +impl<'a> WAVEGEN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WAVEGEN_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Normal frequency"] + #[inline(always)] + pub fn nfrq(self) -> &'a mut W { + self.variant(WAVEGEN_A::NFRQ) + } + #[doc = "Match frequency"] + #[inline(always)] + pub fn mfrq(self) -> &'a mut W { + self.variant(WAVEGEN_A::MFRQ) + } + #[doc = "Normal PWM"] + #[inline(always)] + pub fn npwm(self) -> &'a mut W { + self.variant(WAVEGEN_A::NPWM) + } + #[doc = "Match PWM"] + #[inline(always)] + pub fn mpwm(self) -> &'a mut W { + self.variant(WAVEGEN_A::MPWM) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u8 & 0x03); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Waveform Generation Mode"] + #[inline(always)] + pub fn wavegen(&self) -> WAVEGEN_R { + WAVEGEN_R::new((self.bits & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Waveform Generation Mode"] + #[inline(always)] + pub fn wavegen(&mut self) -> WAVEGEN_W { + WAVEGEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Waveform Generation Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wave](index.html) module"] +pub struct WAVE_SPEC; +impl crate::RegisterSpec for WAVE_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [wave::R](R) reader structure"] +impl crate::Readable for WAVE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wave::W](W) writer structure"] +impl crate::Writable for WAVE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WAVE to value 0"] +impl crate::Resettable for WAVE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/tc0/count8.rs b/pac/atsamc21j/src/tc0/count8.rs new file mode 100644 index 000000000000..777da5744358 --- /dev/null +++ b/pac/atsamc21j/src/tc0/count8.rs @@ -0,0 +1,68 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "CTRLBCLR register accessor: an alias for `Reg`"] +pub type CTRLBCLR = crate::Reg; +#[doc = "Control B Clear"] +pub mod ctrlbclr; +#[doc = "CTRLBSET register accessor: an alias for `Reg`"] +pub type CTRLBSET = crate::Reg; +#[doc = "Control B Set"] +pub mod ctrlbset; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "WAVE register accessor: an alias for `Reg`"] +pub type WAVE = crate::Reg; +#[doc = "Waveform Generation Control"] +pub mod wave; +#[doc = "DRVCTRL register accessor: an alias for `Reg`"] +pub type DRVCTRL = crate::Reg; +#[doc = "Control C"] +pub mod drvctrl; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Status"] +pub mod syncbusy; +#[doc = "COUNT register accessor: an alias for `Reg`"] +pub type COUNT = crate::Reg; +#[doc = "COUNT8 Count"] +pub mod count; +#[doc = "PER register accessor: an alias for `Reg`"] +pub type PER = crate::Reg; +#[doc = "COUNT8 Period"] +pub mod per; +#[doc = "CC register accessor: an alias for `Reg`"] +pub type CC = crate::Reg; +#[doc = "COUNT8 Compare and Capture"] +pub mod cc; +#[doc = "PERBUF register accessor: an alias for `Reg`"] +pub type PERBUF = crate::Reg; +#[doc = "COUNT8 Period Buffer"] +pub mod perbuf; +#[doc = "CCBUF register accessor: an alias for `Reg`"] +pub type CCBUF = crate::Reg; +#[doc = "COUNT8 Compare and Capture Buffer"] +pub mod ccbuf; diff --git a/pac/atsamc21j/src/tc0/count8/cc.rs b/pac/atsamc21j/src/tc0/count8/cc.rs new file mode 100644 index 000000000000..45f5c29c89af --- /dev/null +++ b/pac/atsamc21j/src/tc0/count8/cc.rs @@ -0,0 +1,104 @@ +#[doc = "Register `CC[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CC[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CC` reader - Counter/Compare Value"] +pub struct CC_R(crate::FieldReader); +impl CC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC` writer - Counter/Compare Value"] +pub struct CC_W<'a> { + w: &'a mut W, +} +impl<'a> CC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Counter/Compare Value"] + #[inline(always)] + pub fn cc(&self) -> CC_R { + CC_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Counter/Compare Value"] + #[inline(always)] + pub fn cc(&mut self) -> CC_W { + CC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT8 Compare and Capture\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc](index.html) module"] +pub struct CC_SPEC; +impl crate::RegisterSpec for CC_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [cc::R](R) reader structure"] +impl crate::Readable for CC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cc::W](W) writer structure"] +impl crate::Writable for CC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CC[%s] +to value 0"] +impl crate::Resettable for CC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/tc0/count8/ccbuf.rs b/pac/atsamc21j/src/tc0/count8/ccbuf.rs new file mode 100644 index 000000000000..cd81b1219860 --- /dev/null +++ b/pac/atsamc21j/src/tc0/count8/ccbuf.rs @@ -0,0 +1,104 @@ +#[doc = "Register `CCBUF[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CCBUF[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CCBUF` reader - Counter/Compare Buffer Value"] +pub struct CCBUF_R(crate::FieldReader); +impl CCBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CCBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUF` writer - Counter/Compare Buffer Value"] +pub struct CCBUF_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Counter/Compare Buffer Value"] + #[inline(always)] + pub fn ccbuf(&self) -> CCBUF_R { + CCBUF_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Counter/Compare Buffer Value"] + #[inline(always)] + pub fn ccbuf(&mut self) -> CCBUF_W { + CCBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT8 Compare and Capture Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccbuf](index.html) module"] +pub struct CCBUF_SPEC; +impl crate::RegisterSpec for CCBUF_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ccbuf::R](R) reader structure"] +impl crate::Readable for CCBUF_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ccbuf::W](W) writer structure"] +impl crate::Writable for CCBUF_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CCBUF[%s] +to value 0"] +impl crate::Resettable for CCBUF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/tc0/count8/count.rs b/pac/atsamc21j/src/tc0/count8/count.rs new file mode 100644 index 000000000000..0edbb0f17bb7 --- /dev/null +++ b/pac/atsamc21j/src/tc0/count8/count.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT8 Count\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count](index.html) module"] +pub struct COUNT_SPEC; +impl crate::RegisterSpec for COUNT_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [count::R](R) reader structure"] +impl crate::Readable for COUNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count::W](W) writer structure"] +impl crate::Writable for COUNT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT to value 0"] +impl crate::Resettable for COUNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/tc0/count8/ctrla.rs b/pac/atsamc21j/src/tc0/count8/ctrla.rs new file mode 100644 index 000000000000..cadcddaaead8 --- /dev/null +++ b/pac/atsamc21j/src/tc0/count8/ctrla.rs @@ -0,0 +1,851 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Timer Counter Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: Counter in 16-bit mode"] + COUNT16 = 0, + #[doc = "1: Counter in 8-bit mode"] + COUNT8 = 1, + #[doc = "2: Counter in 32-bit mode"] + COUNT32 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Timer Counter Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::COUNT16), + 1 => Some(MODE_A::COUNT8), + 2 => Some(MODE_A::COUNT32), + _ => None, + } + } + #[doc = "Checks if the value of the field is `COUNT16`"] + #[inline(always)] + pub fn is_count16(&self) -> bool { + **self == MODE_A::COUNT16 + } + #[doc = "Checks if the value of the field is `COUNT8`"] + #[inline(always)] + pub fn is_count8(&self) -> bool { + **self == MODE_A::COUNT8 + } + #[doc = "Checks if the value of the field is `COUNT32`"] + #[inline(always)] + pub fn is_count32(&self) -> bool { + **self == MODE_A::COUNT32 + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Timer Counter Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Counter in 16-bit mode"] + #[inline(always)] + pub fn count16(self) -> &'a mut W { + self.variant(MODE_A::COUNT16) + } + #[doc = "Counter in 8-bit mode"] + #[inline(always)] + pub fn count8(self) -> &'a mut W { + self.variant(MODE_A::COUNT8) + } + #[doc = "Counter in 32-bit mode"] + #[inline(always)] + pub fn count32(self) -> &'a mut W { + self.variant(MODE_A::COUNT32) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u32 & 0x03) << 2); + self.w + } +} +#[doc = "Prescaler and Counter Synchronization\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCSYNC_A { + #[doc = "0: Reload or reset the counter on next generic clock"] + GCLK = 0, + #[doc = "1: Reload or reset the counter on next prescaler clock"] + PRESC = 1, + #[doc = "2: Reload or reset the counter on next generic clock and reset the prescaler counter"] + RESYNC = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCSYNC_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCSYNC` reader - Prescaler and Counter Synchronization"] +pub struct PRESCSYNC_R(crate::FieldReader); +impl PRESCSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCSYNC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCSYNC_A::GCLK), + 1 => Some(PRESCSYNC_A::PRESC), + 2 => Some(PRESCSYNC_A::RESYNC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `GCLK`"] + #[inline(always)] + pub fn is_gclk(&self) -> bool { + **self == PRESCSYNC_A::GCLK + } + #[doc = "Checks if the value of the field is `PRESC`"] + #[inline(always)] + pub fn is_presc(&self) -> bool { + **self == PRESCSYNC_A::PRESC + } + #[doc = "Checks if the value of the field is `RESYNC`"] + #[inline(always)] + pub fn is_resync(&self) -> bool { + **self == PRESCSYNC_A::RESYNC + } +} +impl core::ops::Deref for PRESCSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCSYNC` writer - Prescaler and Counter Synchronization"] +pub struct PRESCSYNC_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCSYNC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCSYNC_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Reload or reset the counter on next generic clock"] + #[inline(always)] + pub fn gclk(self) -> &'a mut W { + self.variant(PRESCSYNC_A::GCLK) + } + #[doc = "Reload or reset the counter on next prescaler clock"] + #[inline(always)] + pub fn presc(self) -> &'a mut W { + self.variant(PRESCSYNC_A::PRESC) + } + #[doc = "Reload or reset the counter on next generic clock and reset the prescaler counter"] + #[inline(always)] + pub fn resync(self) -> &'a mut W { + self.variant(PRESCSYNC_A::RESYNC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u32 & 0x03) << 4); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - Clock On Demand"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - Clock On Demand"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: Prescaler: GCLK_TC"] + DIV1 = 0, + #[doc = "1: Prescaler: GCLK_TC/2"] + DIV2 = 1, + #[doc = "2: Prescaler: GCLK_TC/4"] + DIV4 = 2, + #[doc = "3: Prescaler: GCLK_TC/8"] + DIV8 = 3, + #[doc = "4: Prescaler: GCLK_TC/16"] + DIV16 = 4, + #[doc = "5: Prescaler: GCLK_TC/64"] + DIV64 = 5, + #[doc = "6: Prescaler: GCLK_TC/256"] + DIV256 = 6, + #[doc = "7: Prescaler: GCLK_TC/1024"] + DIV1024 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PRESCALER_A { + match self.bits { + 0 => PRESCALER_A::DIV1, + 1 => PRESCALER_A::DIV2, + 2 => PRESCALER_A::DIV4, + 3 => PRESCALER_A::DIV8, + 4 => PRESCALER_A::DIV16, + 5 => PRESCALER_A::DIV64, + 6 => PRESCALER_A::DIV256, + 7 => PRESCALER_A::DIV1024, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == PRESCALER_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PRESCALER_A::DIV1024 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Prescaler: GCLK_TC"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1) + } + #[doc = "Prescaler: GCLK_TC/2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "Prescaler: GCLK_TC/4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "Prescaler: GCLK_TC/8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "Prescaler: GCLK_TC/16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "Prescaler: GCLK_TC/64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "Prescaler: GCLK_TC/256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = "Prescaler: GCLK_TC/1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +#[doc = "Field `ALOCK` reader - Auto Lock"] +pub struct ALOCK_R(crate::FieldReader); +impl ALOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALOCK` writer - Auto Lock"] +pub struct ALOCK_W<'a> { + w: &'a mut W, +} +impl<'a> ALOCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `CAPTEN0` reader - Capture Channel 0 Enable"] +pub struct CAPTEN0_R(crate::FieldReader); +impl CAPTEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CAPTEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CAPTEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAPTEN0` writer - Capture Channel 0 Enable"] +pub struct CAPTEN0_W<'a> { + w: &'a mut W, +} +impl<'a> CAPTEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `CAPTEN1` reader - Capture Channel 1 Enable"] +pub struct CAPTEN1_R(crate::FieldReader); +impl CAPTEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CAPTEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CAPTEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAPTEN1` writer - Capture Channel 1 Enable"] +pub struct CAPTEN1_W<'a> { + w: &'a mut W, +} +impl<'a> CAPTEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `COPEN0` reader - Capture On Pin 0 Enable"] +pub struct COPEN0_R(crate::FieldReader); +impl COPEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COPEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COPEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COPEN0` writer - Capture On Pin 0 Enable"] +pub struct COPEN0_W<'a> { + w: &'a mut W, +} +impl<'a> COPEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `COPEN1` reader - Capture On Pin 1 Enable"] +pub struct COPEN1_R(crate::FieldReader); +impl COPEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COPEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COPEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COPEN1` writer - Capture On Pin 1 Enable"] +pub struct COPEN1_W<'a> { + w: &'a mut W, +} +impl<'a> COPEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:3 - Timer Counter Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bits 4:5 - Prescaler and Counter Synchronization"] + #[inline(always)] + pub fn prescsync(&self) -> PRESCSYNC_R { + PRESCSYNC_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Clock On Demand"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 11 - Auto Lock"] + #[inline(always)] + pub fn alock(&self) -> ALOCK_R { + ALOCK_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 16 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn capten0(&self) -> CAPTEN0_R { + CAPTEN0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn capten1(&self) -> CAPTEN1_R { + CAPTEN1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 20 - Capture On Pin 0 Enable"] + #[inline(always)] + pub fn copen0(&self) -> COPEN0_R { + COPEN0_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Capture On Pin 1 Enable"] + #[inline(always)] + pub fn copen1(&self) -> COPEN1_R { + COPEN1_R::new(((self.bits >> 21) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:3 - Timer Counter Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bits 4:5 - Prescaler and Counter Synchronization"] + #[inline(always)] + pub fn prescsync(&mut self) -> PRESCSYNC_W { + PRESCSYNC_W { w: self } + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - Clock On Demand"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Bit 11 - Auto Lock"] + #[inline(always)] + pub fn alock(&mut self) -> ALOCK_W { + ALOCK_W { w: self } + } + #[doc = "Bit 16 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn capten0(&mut self) -> CAPTEN0_W { + CAPTEN0_W { w: self } + } + #[doc = "Bit 17 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn capten1(&mut self) -> CAPTEN1_W { + CAPTEN1_W { w: self } + } + #[doc = "Bit 20 - Capture On Pin 0 Enable"] + #[inline(always)] + pub fn copen0(&mut self) -> COPEN0_W { + COPEN0_W { w: self } + } + #[doc = "Bit 21 - Capture On Pin 1 Enable"] + #[inline(always)] + pub fn copen1(&mut self) -> COPEN1_W { + COPEN1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/tc0/count8/ctrlbclr.rs b/pac/atsamc21j/src/tc0/count8/ctrlbclr.rs new file mode 100644 index 000000000000..76265674036a --- /dev/null +++ b/pac/atsamc21j/src/tc0/count8/ctrlbclr.rs @@ -0,0 +1,345 @@ +#[doc = "Register `CTRLBCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Counter Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `LUPD` reader - Lock Update"] +pub struct LUPD_R(crate::FieldReader); +impl LUPD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LUPD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LUPD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LUPD` writer - Lock Update"] +pub struct LUPD_W<'a> { + w: &'a mut W, +} +impl<'a> LUPD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ONESHOT` reader - One-Shot on Counter"] +pub struct ONESHOT_R(crate::FieldReader); +impl ONESHOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONESHOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONESHOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONESHOT` writer - One-Shot on Counter"] +pub struct ONESHOT_W<'a> { + w: &'a mut W, +} +impl<'a> ONESHOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Force a start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force a stop"] + STOP = 2, + #[doc = "3: Force update of double-buffered register"] + UPDATE = 3, + #[doc = "4: Force a read synchronization of COUNT"] + READSYNC = 4, + #[doc = "5: One-shot DMA trigger"] + DMAOS = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NONE), + 1 => Some(CMD_A::RETRIGGER), + 2 => Some(CMD_A::STOP), + 3 => Some(CMD_A::UPDATE), + 4 => Some(CMD_A::READSYNC), + 5 => Some(CMD_A::DMAOS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == CMD_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == CMD_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == CMD_A::STOP + } + #[doc = "Checks if the value of the field is `UPDATE`"] + #[inline(always)] + pub fn is_update(&self) -> bool { + **self == CMD_A::UPDATE + } + #[doc = "Checks if the value of the field is `READSYNC`"] + #[inline(always)] + pub fn is_readsync(&self) -> bool { + **self == CMD_A::READSYNC + } + #[doc = "Checks if the value of the field is `DMAOS`"] + #[inline(always)] + pub fn is_dmaos(&self) -> bool { + **self == CMD_A::DMAOS + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMD_A::NONE) + } + #[doc = "Force a start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMD_A::RETRIGGER) + } + #[doc = "Force a stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMD_A::STOP) + } + #[doc = "Force update of double-buffered register"] + #[inline(always)] + pub fn update(self) -> &'a mut W { + self.variant(CMD_A::UPDATE) + } + #[doc = "Force a read synchronization of COUNT"] + #[inline(always)] + pub fn readsync(self) -> &'a mut W { + self.variant(CMD_A::READSYNC) + } + #[doc = "One-shot DMA trigger"] + #[inline(always)] + pub fn dmaos(self) -> &'a mut W { + self.variant(CMD_A::DMAOS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 5)) | ((value as u8 & 0x07) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&self) -> LUPD_R { + LUPD_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 5) & 0x07) as u8) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&mut self) -> LUPD_W { + LUPD_W { w: self } + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&mut self) -> ONESHOT_W { + ONESHOT_W { w: self } + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbclr](index.html) module"] +pub struct CTRLBCLR_SPEC; +impl crate::RegisterSpec for CTRLBCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbclr::R](R) reader structure"] +impl crate::Readable for CTRLBCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbclr::W](W) writer structure"] +impl crate::Writable for CTRLBCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLBCLR to value 0"] +impl crate::Resettable for CTRLBCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/tc0/count8/ctrlbset.rs b/pac/atsamc21j/src/tc0/count8/ctrlbset.rs new file mode 100644 index 000000000000..610914c9c7c8 --- /dev/null +++ b/pac/atsamc21j/src/tc0/count8/ctrlbset.rs @@ -0,0 +1,345 @@ +#[doc = "Register `CTRLBSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Counter Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `LUPD` reader - Lock Update"] +pub struct LUPD_R(crate::FieldReader); +impl LUPD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LUPD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LUPD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LUPD` writer - Lock Update"] +pub struct LUPD_W<'a> { + w: &'a mut W, +} +impl<'a> LUPD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ONESHOT` reader - One-Shot on Counter"] +pub struct ONESHOT_R(crate::FieldReader); +impl ONESHOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONESHOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONESHOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONESHOT` writer - One-Shot on Counter"] +pub struct ONESHOT_W<'a> { + w: &'a mut W, +} +impl<'a> ONESHOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Force a start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force a stop"] + STOP = 2, + #[doc = "3: Force update of double-buffered register"] + UPDATE = 3, + #[doc = "4: Force a read synchronization of COUNT"] + READSYNC = 4, + #[doc = "5: One-shot DMA trigger"] + DMAOS = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NONE), + 1 => Some(CMD_A::RETRIGGER), + 2 => Some(CMD_A::STOP), + 3 => Some(CMD_A::UPDATE), + 4 => Some(CMD_A::READSYNC), + 5 => Some(CMD_A::DMAOS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == CMD_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == CMD_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == CMD_A::STOP + } + #[doc = "Checks if the value of the field is `UPDATE`"] + #[inline(always)] + pub fn is_update(&self) -> bool { + **self == CMD_A::UPDATE + } + #[doc = "Checks if the value of the field is `READSYNC`"] + #[inline(always)] + pub fn is_readsync(&self) -> bool { + **self == CMD_A::READSYNC + } + #[doc = "Checks if the value of the field is `DMAOS`"] + #[inline(always)] + pub fn is_dmaos(&self) -> bool { + **self == CMD_A::DMAOS + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMD_A::NONE) + } + #[doc = "Force a start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMD_A::RETRIGGER) + } + #[doc = "Force a stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMD_A::STOP) + } + #[doc = "Force update of double-buffered register"] + #[inline(always)] + pub fn update(self) -> &'a mut W { + self.variant(CMD_A::UPDATE) + } + #[doc = "Force a read synchronization of COUNT"] + #[inline(always)] + pub fn readsync(self) -> &'a mut W { + self.variant(CMD_A::READSYNC) + } + #[doc = "One-shot DMA trigger"] + #[inline(always)] + pub fn dmaos(self) -> &'a mut W { + self.variant(CMD_A::DMAOS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 5)) | ((value as u8 & 0x07) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&self) -> LUPD_R { + LUPD_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 5) & 0x07) as u8) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&mut self) -> LUPD_W { + LUPD_W { w: self } + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&mut self) -> ONESHOT_W { + ONESHOT_W { w: self } + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbset](index.html) module"] +pub struct CTRLBSET_SPEC; +impl crate::RegisterSpec for CTRLBSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbset::R](R) reader structure"] +impl crate::Readable for CTRLBSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbset::W](W) writer structure"] +impl crate::Writable for CTRLBSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLBSET to value 0"] +impl crate::Resettable for CTRLBSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/tc0/count8/dbgctrl.rs b/pac/atsamc21j/src/tc0/count8/dbgctrl.rs new file mode 100644 index 000000000000..0383e70d0429 --- /dev/null +++ b/pac/atsamc21j/src/tc0/count8/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Run During Debug"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Run During Debug"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/tc0/count8/drvctrl.rs b/pac/atsamc21j/src/tc0/count8/drvctrl.rs new file mode 100644 index 000000000000..323926b4b22d --- /dev/null +++ b/pac/atsamc21j/src/tc0/count8/drvctrl.rs @@ -0,0 +1,160 @@ +#[doc = "Register `DRVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DRVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INVEN0` reader - Output Waveform Invert Enable 0"] +pub struct INVEN0_R(crate::FieldReader); +impl INVEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN0` writer - Output Waveform Invert Enable 0"] +pub struct INVEN0_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `INVEN1` reader - Output Waveform Invert Enable 1"] +pub struct INVEN1_R(crate::FieldReader); +impl INVEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN1` writer - Output Waveform Invert Enable 1"] +pub struct INVEN1_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - Output Waveform Invert Enable 0"] + #[inline(always)] + pub fn inven0(&self) -> INVEN0_R { + INVEN0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Output Waveform Invert Enable 1"] + #[inline(always)] + pub fn inven1(&self) -> INVEN1_R { + INVEN1_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Output Waveform Invert Enable 0"] + #[inline(always)] + pub fn inven0(&mut self) -> INVEN0_W { + INVEN0_W { w: self } + } + #[doc = "Bit 1 - Output Waveform Invert Enable 1"] + #[inline(always)] + pub fn inven1(&mut self) -> INVEN1_W { + INVEN1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control C\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [drvctrl](index.html) module"] +pub struct DRVCTRL_SPEC; +impl crate::RegisterSpec for DRVCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [drvctrl::R](R) reader structure"] +impl crate::Readable for DRVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [drvctrl::W](W) writer structure"] +impl crate::Writable for DRVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DRVCTRL to value 0"] +impl crate::Resettable for DRVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/tc0/count8/evctrl.rs b/pac/atsamc21j/src/tc0/count8/evctrl.rs new file mode 100644 index 000000000000..7d4c38d486c1 --- /dev/null +++ b/pac/atsamc21j/src/tc0/count8/evctrl.rs @@ -0,0 +1,465 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Event Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EVACT_A { + #[doc = "0: Event action disabled"] + OFF = 0, + #[doc = "1: Start, restart or retrigger TC on event"] + RETRIGGER = 1, + #[doc = "2: Count on event"] + COUNT = 2, + #[doc = "3: Start TC on event"] + START = 3, + #[doc = "4: Time stamp capture"] + STAMP = 4, + #[doc = "5: Period catured in CC0, pulse width in CC1"] + PPW = 5, + #[doc = "6: Period catured in CC1, pulse width in CC0"] + PWP = 6, + #[doc = "7: Pulse width capture"] + PW = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EVACT_A) -> Self { + variant as _ + } +} +#[doc = "Field `EVACT` reader - Event Action"] +pub struct EVACT_R(crate::FieldReader); +impl EVACT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVACT_A { + match self.bits { + 0 => EVACT_A::OFF, + 1 => EVACT_A::RETRIGGER, + 2 => EVACT_A::COUNT, + 3 => EVACT_A::START, + 4 => EVACT_A::STAMP, + 5 => EVACT_A::PPW, + 6 => EVACT_A::PWP, + 7 => EVACT_A::PW, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == EVACT_A::OFF + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == EVACT_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `COUNT`"] + #[inline(always)] + pub fn is_count(&self) -> bool { + **self == EVACT_A::COUNT + } + #[doc = "Checks if the value of the field is `START`"] + #[inline(always)] + pub fn is_start(&self) -> bool { + **self == EVACT_A::START + } + #[doc = "Checks if the value of the field is `STAMP`"] + #[inline(always)] + pub fn is_stamp(&self) -> bool { + **self == EVACT_A::STAMP + } + #[doc = "Checks if the value of the field is `PPW`"] + #[inline(always)] + pub fn is_ppw(&self) -> bool { + **self == EVACT_A::PPW + } + #[doc = "Checks if the value of the field is `PWP`"] + #[inline(always)] + pub fn is_pwp(&self) -> bool { + **self == EVACT_A::PWP + } + #[doc = "Checks if the value of the field is `PW`"] + #[inline(always)] + pub fn is_pw(&self) -> bool { + **self == EVACT_A::PW + } +} +impl core::ops::Deref for EVACT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT` writer - Event Action"] +pub struct EVACT_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EVACT_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Event action disabled"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(EVACT_A::OFF) + } + #[doc = "Start, restart or retrigger TC on event"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(EVACT_A::RETRIGGER) + } + #[doc = "Count on event"] + #[inline(always)] + pub fn count(self) -> &'a mut W { + self.variant(EVACT_A::COUNT) + } + #[doc = "Start TC on event"] + #[inline(always)] + pub fn start(self) -> &'a mut W { + self.variant(EVACT_A::START) + } + #[doc = "Time stamp capture"] + #[inline(always)] + pub fn stamp(self) -> &'a mut W { + self.variant(EVACT_A::STAMP) + } + #[doc = "Period catured in CC0, pulse width in CC1"] + #[inline(always)] + pub fn ppw(self) -> &'a mut W { + self.variant(EVACT_A::PPW) + } + #[doc = "Period catured in CC1, pulse width in CC0"] + #[inline(always)] + pub fn pwp(self) -> &'a mut W { + self.variant(EVACT_A::PWP) + } + #[doc = "Pulse width capture"] + #[inline(always)] + pub fn pw(self) -> &'a mut W { + self.variant(EVACT_A::PW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u16 & 0x07); + self.w + } +} +#[doc = "Field `TCINV` reader - TC Event Input Polarity"] +pub struct TCINV_R(crate::FieldReader); +impl TCINV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCINV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCINV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCINV` writer - TC Event Input Polarity"] +pub struct TCINV_W<'a> { + w: &'a mut W, +} +impl<'a> TCINV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `TCEI` reader - TC Event Enable"] +pub struct TCEI_R(crate::FieldReader); +impl TCEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCEI` writer - TC Event Enable"] +pub struct TCEI_W<'a> { + w: &'a mut W, +} +impl<'a> TCEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `OVFEO` reader - Event Output Enable"] +pub struct OVFEO_R(crate::FieldReader); +impl OVFEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVFEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVFEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVFEO` writer - Event Output Enable"] +pub struct OVFEO_W<'a> { + w: &'a mut W, +} +impl<'a> OVFEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `MCEO0` reader - MC Event Output Enable 0"] +pub struct MCEO0_R(crate::FieldReader); +impl MCEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO0` writer - MC Event Output Enable 0"] +pub struct MCEO0_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u16 & 0x01) << 12); + self.w + } +} +#[doc = "Field `MCEO1` reader - MC Event Output Enable 1"] +pub struct MCEO1_R(crate::FieldReader); +impl MCEO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO1` writer - MC Event Output Enable 1"] +pub struct MCEO1_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u16 & 0x01) << 13); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Event Action"] + #[inline(always)] + pub fn evact(&self) -> EVACT_R { + EVACT_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 4 - TC Event Input Polarity"] + #[inline(always)] + pub fn tcinv(&self) -> TCINV_R { + TCINV_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - TC Event Enable"] + #[inline(always)] + pub fn tcei(&self) -> TCEI_R { + TCEI_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 8 - Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&self) -> OVFEO_R { + OVFEO_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 12 - MC Event Output Enable 0"] + #[inline(always)] + pub fn mceo0(&self) -> MCEO0_R { + MCEO0_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - MC Event Output Enable 1"] + #[inline(always)] + pub fn mceo1(&self) -> MCEO1_R { + MCEO1_R::new(((self.bits >> 13) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Event Action"] + #[inline(always)] + pub fn evact(&mut self) -> EVACT_W { + EVACT_W { w: self } + } + #[doc = "Bit 4 - TC Event Input Polarity"] + #[inline(always)] + pub fn tcinv(&mut self) -> TCINV_W { + TCINV_W { w: self } + } + #[doc = "Bit 5 - TC Event Enable"] + #[inline(always)] + pub fn tcei(&mut self) -> TCEI_W { + TCEI_W { w: self } + } + #[doc = "Bit 8 - Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&mut self) -> OVFEO_W { + OVFEO_W { w: self } + } + #[doc = "Bit 12 - MC Event Output Enable 0"] + #[inline(always)] + pub fn mceo0(&mut self) -> MCEO0_W { + MCEO0_W { w: self } + } + #[doc = "Bit 13 - MC Event Output Enable 1"] + #[inline(always)] + pub fn mceo1(&mut self) -> MCEO1_W { + MCEO1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/tc0/count8/intenclr.rs b/pac/atsamc21j/src/tc0/count8/intenclr.rs new file mode 100644 index 000000000000..af01ef5b7dca --- /dev/null +++ b/pac/atsamc21j/src/tc0/count8/intenclr.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - OVF Interrupt Disable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - OVF Interrupt Disable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - ERR Interrupt Disable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - ERR Interrupt Disable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MC0` reader - MC Interrupt Disable 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - MC Interrupt Disable 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - MC Interrupt Disable 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - MC Interrupt Disable 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - OVF Interrupt Disable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ERR Interrupt Disable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - MC Interrupt Disable 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - MC Interrupt Disable 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - OVF Interrupt Disable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - ERR Interrupt Disable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 4 - MC Interrupt Disable 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - MC Interrupt Disable 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/tc0/count8/intenset.rs b/pac/atsamc21j/src/tc0/count8/intenset.rs new file mode 100644 index 000000000000..0e1883a2f20a --- /dev/null +++ b/pac/atsamc21j/src/tc0/count8/intenset.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - OVF Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - OVF Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - ERR Interrupt Enable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - ERR Interrupt Enable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MC0` reader - MC Interrupt Enable 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - MC Interrupt Enable 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - MC Interrupt Enable 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - MC Interrupt Enable 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - OVF Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ERR Interrupt Enable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - MC Interrupt Enable 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - MC Interrupt Enable 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - OVF Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - ERR Interrupt Enable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 4 - MC Interrupt Enable 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - MC Interrupt Enable 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/tc0/count8/intflag.rs b/pac/atsamc21j/src/tc0/count8/intflag.rs new file mode 100644 index 000000000000..1dddffaf8e7f --- /dev/null +++ b/pac/atsamc21j/src/tc0/count8/intflag.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - OVF Interrupt Flag"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - OVF Interrupt Flag"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - ERR Interrupt Flag"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - ERR Interrupt Flag"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MC0` reader - MC Interrupt Flag 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - MC Interrupt Flag 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - MC Interrupt Flag 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - MC Interrupt Flag 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - OVF Interrupt Flag"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ERR Interrupt Flag"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - MC Interrupt Flag 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - MC Interrupt Flag 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - OVF Interrupt Flag"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - ERR Interrupt Flag"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 4 - MC Interrupt Flag 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - MC Interrupt Flag 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/tc0/count8/per.rs b/pac/atsamc21j/src/tc0/count8/per.rs new file mode 100644 index 000000000000..c9ab52e247d8 --- /dev/null +++ b/pac/atsamc21j/src/tc0/count8/per.rs @@ -0,0 +1,103 @@ +#[doc = "Register `PER` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PER` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER` reader - Period Value"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` writer - Period Value"] +pub struct PER_W<'a> { + w: &'a mut W, +} +impl<'a> PER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Period Value"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Period Value"] + #[inline(always)] + pub fn per(&mut self) -> PER_W { + PER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT8 Period\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [per](index.html) module"] +pub struct PER_SPEC; +impl crate::RegisterSpec for PER_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [per::R](R) reader structure"] +impl crate::Readable for PER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [per::W](W) writer structure"] +impl crate::Writable for PER_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PER to value 0xff"] +impl crate::Resettable for PER_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xff + } +} diff --git a/pac/atsamc21j/src/tc0/count8/perbuf.rs b/pac/atsamc21j/src/tc0/count8/perbuf.rs new file mode 100644 index 000000000000..cbd500e2bbe1 --- /dev/null +++ b/pac/atsamc21j/src/tc0/count8/perbuf.rs @@ -0,0 +1,103 @@ +#[doc = "Register `PERBUF` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PERBUF` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PERBUF` reader - Period Buffer Value"] +pub struct PERBUF_R(crate::FieldReader); +impl PERBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PERBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERBUF` writer - Period Buffer Value"] +pub struct PERBUF_W<'a> { + w: &'a mut W, +} +impl<'a> PERBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Period Buffer Value"] + #[inline(always)] + pub fn perbuf(&self) -> PERBUF_R { + PERBUF_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Period Buffer Value"] + #[inline(always)] + pub fn perbuf(&mut self) -> PERBUF_W { + PERBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT8 Period Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [perbuf](index.html) module"] +pub struct PERBUF_SPEC; +impl crate::RegisterSpec for PERBUF_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [perbuf::R](R) reader structure"] +impl crate::Readable for PERBUF_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [perbuf::W](W) writer structure"] +impl crate::Writable for PERBUF_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PERBUF to value 0xff"] +impl crate::Resettable for PERBUF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xff + } +} diff --git a/pac/atsamc21j/src/tc0/count8/status.rs b/pac/atsamc21j/src/tc0/count8/status.rs new file mode 100644 index 000000000000..5088af446830 --- /dev/null +++ b/pac/atsamc21j/src/tc0/count8/status.rs @@ -0,0 +1,301 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `STOP` reader - Stop Status Flag"] +pub struct STOP_R(crate::FieldReader); +impl STOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STOP` writer - Stop Status Flag"] +pub struct STOP_W<'a> { + w: &'a mut W, +} +impl<'a> STOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SLAVE` reader - Slave Status Flag"] +pub struct SLAVE_R(crate::FieldReader); +impl SLAVE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLAVE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SLAVE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLAVE` writer - Slave Status Flag"] +pub struct SLAVE_W<'a> { + w: &'a mut W, +} +impl<'a> SLAVE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PERBUFV` reader - Synchronization Busy Status"] +pub struct PERBUFV_R(crate::FieldReader); +impl PERBUFV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PERBUFV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERBUFV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERBUFV` writer - Synchronization Busy Status"] +pub struct PERBUFV_W<'a> { + w: &'a mut W, +} +impl<'a> PERBUFV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CCBUFV0` reader - Compare channel buffer 0 valid"] +pub struct CCBUFV0_R(crate::FieldReader); +impl CCBUFV0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBUFV0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUFV0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUFV0` writer - Compare channel buffer 0 valid"] +pub struct CCBUFV0_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUFV0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `CCBUFV1` reader - Compare channel buffer 1 valid"] +pub struct CCBUFV1_R(crate::FieldReader); +impl CCBUFV1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBUFV1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUFV1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUFV1` writer - Compare channel buffer 1 valid"] +pub struct CCBUFV1_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUFV1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Stop Status Flag"] + #[inline(always)] + pub fn stop(&self) -> STOP_R { + STOP_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Slave Status Flag"] + #[inline(always)] + pub fn slave(&self) -> SLAVE_R { + SLAVE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 3 - Synchronization Busy Status"] + #[inline(always)] + pub fn perbufv(&self) -> PERBUFV_R { + PERBUFV_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Compare channel buffer 0 valid"] + #[inline(always)] + pub fn ccbufv0(&self) -> CCBUFV0_R { + CCBUFV0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Compare channel buffer 1 valid"] + #[inline(always)] + pub fn ccbufv1(&self) -> CCBUFV1_R { + CCBUFV1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Stop Status Flag"] + #[inline(always)] + pub fn stop(&mut self) -> STOP_W { + STOP_W { w: self } + } + #[doc = "Bit 1 - Slave Status Flag"] + #[inline(always)] + pub fn slave(&mut self) -> SLAVE_W { + SLAVE_W { w: self } + } + #[doc = "Bit 3 - Synchronization Busy Status"] + #[inline(always)] + pub fn perbufv(&mut self) -> PERBUFV_W { + PERBUFV_W { w: self } + } + #[doc = "Bit 4 - Compare channel buffer 0 valid"] + #[inline(always)] + pub fn ccbufv0(&mut self) -> CCBUFV0_W { + CCBUFV0_W { w: self } + } + #[doc = "Bit 5 - Compare channel buffer 1 valid"] + #[inline(always)] + pub fn ccbufv1(&mut self) -> CCBUFV1_W { + CCBUFV1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0x01"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pac/atsamc21j/src/tc0/count8/syncbusy.rs b/pac/atsamc21j/src/tc0/count8/syncbusy.rs new file mode 100644 index 000000000000..7ad8d91a84de --- /dev/null +++ b/pac/atsamc21j/src/tc0/count8/syncbusy.rs @@ -0,0 +1,193 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - swrst"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLB` reader - CTRLB"] +pub struct CTRLB_R(crate::FieldReader); +impl CTRLB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STATUS` reader - STATUS"] +pub struct STATUS_R(crate::FieldReader); +impl STATUS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STATUS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STATUS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` reader - Counter"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` reader - Period"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC0` reader - Compare Channel 0"] +pub struct CC0_R(crate::FieldReader); +impl CC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC1` reader - Compare Channel 1"] +pub struct CC1_R(crate::FieldReader); +impl CC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - swrst"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - CTRLB"] + #[inline(always)] + pub fn ctrlb(&self) -> CTRLB_R { + CTRLB_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - STATUS"] + #[inline(always)] + pub fn status(&self) -> STATUS_R { + STATUS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Counter"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Period"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Compare Channel 0"] + #[inline(always)] + pub fn cc0(&self) -> CC0_R { + CC0_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Compare Channel 1"] + #[inline(always)] + pub fn cc1(&self) -> CC1_R { + CC1_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +#[doc = "Synchronization Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/tc0/count8/wave.rs b/pac/atsamc21j/src/tc0/count8/wave.rs new file mode 100644 index 000000000000..46061b24b75d --- /dev/null +++ b/pac/atsamc21j/src/tc0/count8/wave.rs @@ -0,0 +1,178 @@ +#[doc = "Register `WAVE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WAVE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Waveform Generation Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WAVEGEN_A { + #[doc = "0: Normal frequency"] + NFRQ = 0, + #[doc = "1: Match frequency"] + MFRQ = 1, + #[doc = "2: Normal PWM"] + NPWM = 2, + #[doc = "3: Match PWM"] + MPWM = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WAVEGEN_A) -> Self { + variant as _ + } +} +#[doc = "Field `WAVEGEN` reader - Waveform Generation Mode"] +pub struct WAVEGEN_R(crate::FieldReader); +impl WAVEGEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WAVEGEN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> WAVEGEN_A { + match self.bits { + 0 => WAVEGEN_A::NFRQ, + 1 => WAVEGEN_A::MFRQ, + 2 => WAVEGEN_A::NPWM, + 3 => WAVEGEN_A::MPWM, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NFRQ`"] + #[inline(always)] + pub fn is_nfrq(&self) -> bool { + **self == WAVEGEN_A::NFRQ + } + #[doc = "Checks if the value of the field is `MFRQ`"] + #[inline(always)] + pub fn is_mfrq(&self) -> bool { + **self == WAVEGEN_A::MFRQ + } + #[doc = "Checks if the value of the field is `NPWM`"] + #[inline(always)] + pub fn is_npwm(&self) -> bool { + **self == WAVEGEN_A::NPWM + } + #[doc = "Checks if the value of the field is `MPWM`"] + #[inline(always)] + pub fn is_mpwm(&self) -> bool { + **self == WAVEGEN_A::MPWM + } +} +impl core::ops::Deref for WAVEGEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAVEGEN` writer - Waveform Generation Mode"] +pub struct WAVEGEN_W<'a> { + w: &'a mut W, +} +impl<'a> WAVEGEN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WAVEGEN_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Normal frequency"] + #[inline(always)] + pub fn nfrq(self) -> &'a mut W { + self.variant(WAVEGEN_A::NFRQ) + } + #[doc = "Match frequency"] + #[inline(always)] + pub fn mfrq(self) -> &'a mut W { + self.variant(WAVEGEN_A::MFRQ) + } + #[doc = "Normal PWM"] + #[inline(always)] + pub fn npwm(self) -> &'a mut W { + self.variant(WAVEGEN_A::NPWM) + } + #[doc = "Match PWM"] + #[inline(always)] + pub fn mpwm(self) -> &'a mut W { + self.variant(WAVEGEN_A::MPWM) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u8 & 0x03); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Waveform Generation Mode"] + #[inline(always)] + pub fn wavegen(&self) -> WAVEGEN_R { + WAVEGEN_R::new((self.bits & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Waveform Generation Mode"] + #[inline(always)] + pub fn wavegen(&mut self) -> WAVEGEN_W { + WAVEGEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Waveform Generation Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wave](index.html) module"] +pub struct WAVE_SPEC; +impl crate::RegisterSpec for WAVE_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [wave::R](R) reader structure"] +impl crate::Readable for WAVE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wave::W](W) writer structure"] +impl crate::Writable for WAVE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WAVE to value 0"] +impl crate::Resettable for WAVE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/tcc0.rs b/pac/atsamc21j/src/tcc0.rs new file mode 100644 index 000000000000..6ce813a9e3d5 --- /dev/null +++ b/pac/atsamc21j/src/tcc0.rs @@ -0,0 +1,359 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - Control B Clear"] + pub ctrlbclr: crate::Reg, + #[doc = "0x05 - Control B Set"] + pub ctrlbset: crate::Reg, + _reserved3: [u8; 0x02], + #[doc = "0x08 - Synchronization Busy"] + pub syncbusy: crate::Reg, + #[doc = "0x0c - Recoverable Fault A Configuration"] + pub fctrla: crate::Reg, + #[doc = "0x10 - Recoverable Fault B Configuration"] + pub fctrlb: crate::Reg, + #[doc = "0x14 - Waveform Extension Configuration"] + pub wexctrl: crate::Reg, + #[doc = "0x18 - Driver Control"] + pub drvctrl: crate::Reg, + _reserved8: [u8; 0x02], + #[doc = "0x1e - Debug Control"] + pub dbgctrl: crate::Reg, + _reserved9: [u8; 0x01], + #[doc = "0x20 - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x24 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x28 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x2c - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x30 - Status"] + pub status: crate::Reg, + _reserved_14_count: [u8; 0x04], + #[doc = "0x38 - Pattern"] + pub patt: crate::Reg, + _reserved16: [u8; 0x02], + #[doc = "0x3c - Waveform Control"] + pub wave: crate::Reg, + _reserved_17_per: [u8; 0x04], + _reserved_18_cc: [u8; 0x10], + _reserved19: [u8; 0x10], + #[doc = "0x64 - Pattern Buffer"] + pub pattbuf: crate::Reg, + _reserved20: [u8; 0x06], + _reserved_20_perbuf: [u8; 0x04], + _reserved_21_ccbuf: [u8; 0x10], +} +impl RegisterBlock { + #[doc = "0x34 - Count"] + #[inline(always)] + pub fn count_dith6_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(52usize) + as *const crate::Reg) + } + } + #[doc = "0x34 - Count"] + #[inline(always)] + pub fn count_dith5_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(52usize) + as *const crate::Reg) + } + } + #[doc = "0x34 - Count"] + #[inline(always)] + pub fn count_dith4_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(52usize) + as *const crate::Reg) + } + } + #[doc = "0x34 - Count"] + #[inline(always)] + pub fn count(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(52usize) + as *const crate::Reg) + } + } + #[doc = "0x40 - Period"] + #[inline(always)] + pub fn per_dith6_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(64usize) + as *const crate::Reg) + } + } + #[doc = "0x40 - Period"] + #[inline(always)] + pub fn per_dith5_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(64usize) + as *const crate::Reg) + } + } + #[doc = "0x40 - Period"] + #[inline(always)] + pub fn per_dith4_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(64usize) + as *const crate::Reg) + } + } + #[doc = "0x40 - Period"] + #[inline(always)] + pub fn per(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(64usize) + as *const crate::Reg) + } + } + #[doc = "0x44..0x54 - Compare and Capture"] + #[inline(always)] + pub fn cc_dith6_mode(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(68usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x44..0x54 - Compare and Capture"] + #[inline(always)] + pub fn cc_dith5_mode(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(68usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x44..0x54 - Compare and Capture"] + #[inline(always)] + pub fn cc_dith4_mode(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(68usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x44..0x54 - Compare and Capture"] + #[inline(always)] + pub fn cc(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(68usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x6c - Period Buffer"] + #[inline(always)] + pub fn perbuf_dith6_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(108usize) + as *const crate::Reg) + } + } + #[doc = "0x6c - Period Buffer"] + #[inline(always)] + pub fn perbuf_dith5_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(108usize) + as *const crate::Reg) + } + } + #[doc = "0x6c - Period Buffer"] + #[inline(always)] + pub fn perbuf_dith4_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(108usize) + as *const crate::Reg) + } + } + #[doc = "0x6c - Period Buffer"] + #[inline(always)] + pub fn perbuf(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(108usize) + as *const crate::Reg) + } + } + #[doc = "0x70..0x80 - Compare and Capture Buffer"] + #[inline(always)] + pub fn ccbuf_dith6_mode(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(112usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x70..0x80 - Compare and Capture Buffer"] + #[inline(always)] + pub fn ccbuf_dith5_mode(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(112usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x70..0x80 - Compare and Capture Buffer"] + #[inline(always)] + pub fn ccbuf_dith4_mode(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(112usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x70..0x80 - Compare and Capture Buffer"] + #[inline(always)] + pub fn ccbuf(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(112usize) + as *const [crate::Reg; 4]) + } + } +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "CTRLBCLR register accessor: an alias for `Reg`"] +pub type CTRLBCLR = crate::Reg; +#[doc = "Control B Clear"] +pub mod ctrlbclr; +#[doc = "CTRLBSET register accessor: an alias for `Reg`"] +pub type CTRLBSET = crate::Reg; +#[doc = "Control B Set"] +pub mod ctrlbset; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Busy"] +pub mod syncbusy; +#[doc = "FCTRLA register accessor: an alias for `Reg`"] +pub type FCTRLA = crate::Reg; +#[doc = "Recoverable Fault A Configuration"] +pub mod fctrla; +#[doc = "FCTRLB register accessor: an alias for `Reg`"] +pub type FCTRLB = crate::Reg; +#[doc = "Recoverable Fault B Configuration"] +pub mod fctrlb; +#[doc = "WEXCTRL register accessor: an alias for `Reg`"] +pub type WEXCTRL = crate::Reg; +#[doc = "Waveform Extension Configuration"] +pub mod wexctrl; +#[doc = "DRVCTRL register accessor: an alias for `Reg`"] +pub type DRVCTRL = crate::Reg; +#[doc = "Driver Control"] +pub mod drvctrl; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "COUNT register accessor: an alias for `Reg`"] +pub type COUNT = crate::Reg; +#[doc = "Count"] +pub mod count; +#[doc = "COUNT_DITH4_MODE register accessor: an alias for `Reg`"] +pub type COUNT_DITH4_MODE = crate::Reg; +#[doc = "Count"] +pub mod count_dith4_mode; +#[doc = "COUNT_DITH5_MODE register accessor: an alias for `Reg`"] +pub type COUNT_DITH5_MODE = crate::Reg; +#[doc = "Count"] +pub mod count_dith5_mode; +#[doc = "COUNT_DITH6_MODE register accessor: an alias for `Reg`"] +pub type COUNT_DITH6_MODE = crate::Reg; +#[doc = "Count"] +pub mod count_dith6_mode; +#[doc = "PATT register accessor: an alias for `Reg`"] +pub type PATT = crate::Reg; +#[doc = "Pattern"] +pub mod patt; +#[doc = "WAVE register accessor: an alias for `Reg`"] +pub type WAVE = crate::Reg; +#[doc = "Waveform Control"] +pub mod wave; +#[doc = "PER register accessor: an alias for `Reg`"] +pub type PER = crate::Reg; +#[doc = "Period"] +pub mod per; +#[doc = "PER_DITH4_MODE register accessor: an alias for `Reg`"] +pub type PER_DITH4_MODE = crate::Reg; +#[doc = "Period"] +pub mod per_dith4_mode; +#[doc = "PER_DITH5_MODE register accessor: an alias for `Reg`"] +pub type PER_DITH5_MODE = crate::Reg; +#[doc = "Period"] +pub mod per_dith5_mode; +#[doc = "PER_DITH6_MODE register accessor: an alias for `Reg`"] +pub type PER_DITH6_MODE = crate::Reg; +#[doc = "Period"] +pub mod per_dith6_mode; +#[doc = "CC register accessor: an alias for `Reg`"] +pub type CC = crate::Reg; +#[doc = "Compare and Capture"] +pub mod cc; +#[doc = "CC_DITH4_MODE register accessor: an alias for `Reg`"] +pub type CC_DITH4_MODE = crate::Reg; +#[doc = "Compare and Capture"] +pub mod cc_dith4_mode; +#[doc = "CC_DITH5_MODE register accessor: an alias for `Reg`"] +pub type CC_DITH5_MODE = crate::Reg; +#[doc = "Compare and Capture"] +pub mod cc_dith5_mode; +#[doc = "CC_DITH6_MODE register accessor: an alias for `Reg`"] +pub type CC_DITH6_MODE = crate::Reg; +#[doc = "Compare and Capture"] +pub mod cc_dith6_mode; +#[doc = "PATTBUF register accessor: an alias for `Reg`"] +pub type PATTBUF = crate::Reg; +#[doc = "Pattern Buffer"] +pub mod pattbuf; +#[doc = "PERBUF register accessor: an alias for `Reg`"] +pub type PERBUF = crate::Reg; +#[doc = "Period Buffer"] +pub mod perbuf; +#[doc = "PERBUF_DITH4_MODE register accessor: an alias for `Reg`"] +pub type PERBUF_DITH4_MODE = crate::Reg; +#[doc = "Period Buffer"] +pub mod perbuf_dith4_mode; +#[doc = "PERBUF_DITH5_MODE register accessor: an alias for `Reg`"] +pub type PERBUF_DITH5_MODE = crate::Reg; +#[doc = "Period Buffer"] +pub mod perbuf_dith5_mode; +#[doc = "PERBUF_DITH6_MODE register accessor: an alias for `Reg`"] +pub type PERBUF_DITH6_MODE = crate::Reg; +#[doc = "Period Buffer"] +pub mod perbuf_dith6_mode; +#[doc = "CCBUF register accessor: an alias for `Reg`"] +pub type CCBUF = crate::Reg; +#[doc = "Compare and Capture Buffer"] +pub mod ccbuf; +#[doc = "CCBUF_DITH4_MODE register accessor: an alias for `Reg`"] +pub type CCBUF_DITH4_MODE = crate::Reg; +#[doc = "Compare and Capture Buffer"] +pub mod ccbuf_dith4_mode; +#[doc = "CCBUF_DITH5_MODE register accessor: an alias for `Reg`"] +pub type CCBUF_DITH5_MODE = crate::Reg; +#[doc = "Compare and Capture Buffer"] +pub mod ccbuf_dith5_mode; +#[doc = "CCBUF_DITH6_MODE register accessor: an alias for `Reg`"] +pub type CCBUF_DITH6_MODE = crate::Reg; +#[doc = "Compare and Capture Buffer"] +pub mod ccbuf_dith6_mode; diff --git a/pac/atsamc21j/src/tcc0/cc.rs b/pac/atsamc21j/src/tcc0/cc.rs new file mode 100644 index 000000000000..c4d6df7a9a20 --- /dev/null +++ b/pac/atsamc21j/src/tcc0/cc.rs @@ -0,0 +1,104 @@ +#[doc = "Register `CC[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CC[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CC` reader - Channel Compare/Capture Value"] +pub struct CC_R(crate::FieldReader); +impl CC_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC` writer - Channel Compare/Capture Value"] +pub struct CC_W<'a> { + w: &'a mut W, +} +impl<'a> CC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&self) -> CC_R { + CC_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&mut self) -> CC_W { + CC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc](index.html) module"] +pub struct CC_SPEC; +impl crate::RegisterSpec for CC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cc::R](R) reader structure"] +impl crate::Readable for CC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cc::W](W) writer structure"] +impl crate::Writable for CC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CC[%s] +to value 0"] +impl crate::Resettable for CC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/tcc0/cc_dith4_mode.rs b/pac/atsamc21j/src/tcc0/cc_dith4_mode.rs new file mode 100644 index 000000000000..c45d8b6bac41 --- /dev/null +++ b/pac/atsamc21j/src/tcc0/cc_dith4_mode.rs @@ -0,0 +1,141 @@ +#[doc = "Register `CC_DITH4_MODE[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CC_DITH4_MODE[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHER` reader - Dithering Cycle Number"] +pub struct DITHER_R(crate::FieldReader); +impl DITHER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHER` writer - Dithering Cycle Number"] +pub struct DITHER_W<'a> { + w: &'a mut W, +} +impl<'a> DITHER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Field `CC` reader - Channel Compare/Capture Value"] +pub struct CC_R(crate::FieldReader); +impl CC_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC` writer - Channel Compare/Capture Value"] +pub struct CC_W<'a> { + w: &'a mut W, +} +impl<'a> CC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x000f_ffff << 4)) | ((value as u32 & 0x000f_ffff) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&self) -> DITHER_R { + DITHER_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&self) -> CC_R { + CC_R::new(((self.bits >> 4) & 0x000f_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:3 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&mut self) -> DITHER_W { + DITHER_W { w: self } + } + #[doc = "Bits 4:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&mut self) -> CC_W { + CC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc_dith4_mode](index.html) module"] +pub struct CC_DITH4_MODE_SPEC; +impl crate::RegisterSpec for CC_DITH4_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cc_dith4_mode::R](R) reader structure"] +impl crate::Readable for CC_DITH4_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cc_dith4_mode::W](W) writer structure"] +impl crate::Writable for CC_DITH4_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CC_DITH4_MODE[%s] +to value 0"] +impl crate::Resettable for CC_DITH4_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/tcc0/cc_dith5_mode.rs b/pac/atsamc21j/src/tcc0/cc_dith5_mode.rs new file mode 100644 index 000000000000..0592b923051a --- /dev/null +++ b/pac/atsamc21j/src/tcc0/cc_dith5_mode.rs @@ -0,0 +1,141 @@ +#[doc = "Register `CC_DITH5_MODE[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CC_DITH5_MODE[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHER` reader - Dithering Cycle Number"] +pub struct DITHER_R(crate::FieldReader); +impl DITHER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHER` writer - Dithering Cycle Number"] +pub struct DITHER_W<'a> { + w: &'a mut W, +} +impl<'a> DITHER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f); + self.w + } +} +#[doc = "Field `CC` reader - Channel Compare/Capture Value"] +pub struct CC_R(crate::FieldReader); +impl CC_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC` writer - Channel Compare/Capture Value"] +pub struct CC_W<'a> { + w: &'a mut W, +} +impl<'a> CC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0007_ffff << 5)) | ((value as u32 & 0x0007_ffff) << 5); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&self) -> DITHER_R { + DITHER_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&self) -> CC_R { + CC_R::new(((self.bits >> 5) & 0x0007_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:4 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&mut self) -> DITHER_W { + DITHER_W { w: self } + } + #[doc = "Bits 5:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&mut self) -> CC_W { + CC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc_dith5_mode](index.html) module"] +pub struct CC_DITH5_MODE_SPEC; +impl crate::RegisterSpec for CC_DITH5_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cc_dith5_mode::R](R) reader structure"] +impl crate::Readable for CC_DITH5_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cc_dith5_mode::W](W) writer structure"] +impl crate::Writable for CC_DITH5_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CC_DITH5_MODE[%s] +to value 0"] +impl crate::Resettable for CC_DITH5_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/tcc0/cc_dith6_mode.rs b/pac/atsamc21j/src/tcc0/cc_dith6_mode.rs new file mode 100644 index 000000000000..62a82a872426 --- /dev/null +++ b/pac/atsamc21j/src/tcc0/cc_dith6_mode.rs @@ -0,0 +1,141 @@ +#[doc = "Register `CC_DITH6_MODE[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CC_DITH6_MODE[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHER` reader - Dithering Cycle Number"] +pub struct DITHER_R(crate::FieldReader); +impl DITHER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHER` writer - Dithering Cycle Number"] +pub struct DITHER_W<'a> { + w: &'a mut W, +} +impl<'a> DITHER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +#[doc = "Field `CC` reader - Channel Compare/Capture Value"] +pub struct CC_R(crate::FieldReader); +impl CC_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC` writer - Channel Compare/Capture Value"] +pub struct CC_W<'a> { + w: &'a mut W, +} +impl<'a> CC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0003_ffff << 6)) | ((value as u32 & 0x0003_ffff) << 6); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&self) -> DITHER_R { + DITHER_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&self) -> CC_R { + CC_R::new(((self.bits >> 6) & 0x0003_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:5 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&mut self) -> DITHER_W { + DITHER_W { w: self } + } + #[doc = "Bits 6:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&mut self) -> CC_W { + CC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc_dith6_mode](index.html) module"] +pub struct CC_DITH6_MODE_SPEC; +impl crate::RegisterSpec for CC_DITH6_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cc_dith6_mode::R](R) reader structure"] +impl crate::Readable for CC_DITH6_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cc_dith6_mode::W](W) writer structure"] +impl crate::Writable for CC_DITH6_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CC_DITH6_MODE[%s] +to value 0"] +impl crate::Resettable for CC_DITH6_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/tcc0/ccbuf.rs b/pac/atsamc21j/src/tcc0/ccbuf.rs new file mode 100644 index 000000000000..a4db1135f095 --- /dev/null +++ b/pac/atsamc21j/src/tcc0/ccbuf.rs @@ -0,0 +1,104 @@ +#[doc = "Register `CCBUF[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CCBUF[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CCBUF` reader - Channel Compare/Capture Buffer Value"] +pub struct CCBUF_R(crate::FieldReader); +impl CCBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CCBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUF` writer - Channel Compare/Capture Buffer Value"] +pub struct CCBUF_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccbuf(&self) -> CCBUF_R { + CCBUF_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccbuf(&mut self) -> CCBUF_W { + CCBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccbuf](index.html) module"] +pub struct CCBUF_SPEC; +impl crate::RegisterSpec for CCBUF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ccbuf::R](R) reader structure"] +impl crate::Readable for CCBUF_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ccbuf::W](W) writer structure"] +impl crate::Writable for CCBUF_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CCBUF[%s] +to value 0"] +impl crate::Resettable for CCBUF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/tcc0/ccbuf_dith4_mode.rs b/pac/atsamc21j/src/tcc0/ccbuf_dith4_mode.rs new file mode 100644 index 000000000000..dfa16e936175 --- /dev/null +++ b/pac/atsamc21j/src/tcc0/ccbuf_dith4_mode.rs @@ -0,0 +1,141 @@ +#[doc = "Register `CCBUF_DITH4_MODE[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CCBUF_DITH4_MODE[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CCBUF` reader - Channel Compare/Capture Buffer Value"] +pub struct CCBUF_R(crate::FieldReader); +impl CCBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CCBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUF` writer - Channel Compare/Capture Buffer Value"] +pub struct CCBUF_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Field `DITHERBUF` reader - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_R(crate::FieldReader); +impl DITHERBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + DITHERBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHERBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHERBUF` writer - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_W<'a> { + w: &'a mut W, +} +impl<'a> DITHERBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x000f_ffff << 4)) | ((value as u32 & 0x000f_ffff) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccbuf(&self) -> CCBUF_R { + CCBUF_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:23 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&self) -> DITHERBUF_R { + DITHERBUF_R::new(((self.bits >> 4) & 0x000f_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:3 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccbuf(&mut self) -> CCBUF_W { + CCBUF_W { w: self } + } + #[doc = "Bits 4:23 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&mut self) -> DITHERBUF_W { + DITHERBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccbuf_dith4_mode](index.html) module"] +pub struct CCBUF_DITH4_MODE_SPEC; +impl crate::RegisterSpec for CCBUF_DITH4_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ccbuf_dith4_mode::R](R) reader structure"] +impl crate::Readable for CCBUF_DITH4_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ccbuf_dith4_mode::W](W) writer structure"] +impl crate::Writable for CCBUF_DITH4_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CCBUF_DITH4_MODE[%s] +to value 0"] +impl crate::Resettable for CCBUF_DITH4_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/tcc0/ccbuf_dith5_mode.rs b/pac/atsamc21j/src/tcc0/ccbuf_dith5_mode.rs new file mode 100644 index 000000000000..0c78ba3303c0 --- /dev/null +++ b/pac/atsamc21j/src/tcc0/ccbuf_dith5_mode.rs @@ -0,0 +1,141 @@ +#[doc = "Register `CCBUF_DITH5_MODE[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CCBUF_DITH5_MODE[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHERBUF` reader - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_R(crate::FieldReader); +impl DITHERBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHERBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHERBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHERBUF` writer - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_W<'a> { + w: &'a mut W, +} +impl<'a> DITHERBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f); + self.w + } +} +#[doc = "Field `CCBUF` reader - Channel Compare/Capture Buffer Value"] +pub struct CCBUF_R(crate::FieldReader); +impl CCBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CCBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUF` writer - Channel Compare/Capture Buffer Value"] +pub struct CCBUF_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0007_ffff << 5)) | ((value as u32 & 0x0007_ffff) << 5); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&self) -> DITHERBUF_R { + DITHERBUF_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:23 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccbuf(&self) -> CCBUF_R { + CCBUF_R::new(((self.bits >> 5) & 0x0007_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:4 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&mut self) -> DITHERBUF_W { + DITHERBUF_W { w: self } + } + #[doc = "Bits 5:23 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccbuf(&mut self) -> CCBUF_W { + CCBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccbuf_dith5_mode](index.html) module"] +pub struct CCBUF_DITH5_MODE_SPEC; +impl crate::RegisterSpec for CCBUF_DITH5_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ccbuf_dith5_mode::R](R) reader structure"] +impl crate::Readable for CCBUF_DITH5_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ccbuf_dith5_mode::W](W) writer structure"] +impl crate::Writable for CCBUF_DITH5_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CCBUF_DITH5_MODE[%s] +to value 0"] +impl crate::Resettable for CCBUF_DITH5_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/tcc0/ccbuf_dith6_mode.rs b/pac/atsamc21j/src/tcc0/ccbuf_dith6_mode.rs new file mode 100644 index 000000000000..8d19b8a9e595 --- /dev/null +++ b/pac/atsamc21j/src/tcc0/ccbuf_dith6_mode.rs @@ -0,0 +1,141 @@ +#[doc = "Register `CCBUF_DITH6_MODE[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CCBUF_DITH6_MODE[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHERBUF` reader - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_R(crate::FieldReader); +impl DITHERBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHERBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHERBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHERBUF` writer - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_W<'a> { + w: &'a mut W, +} +impl<'a> DITHERBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +#[doc = "Field `CCBUF` reader - Channel Compare/Capture Buffer Value"] +pub struct CCBUF_R(crate::FieldReader); +impl CCBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CCBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUF` writer - Channel Compare/Capture Buffer Value"] +pub struct CCBUF_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0003_ffff << 6)) | ((value as u32 & 0x0003_ffff) << 6); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&self) -> DITHERBUF_R { + DITHERBUF_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:23 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccbuf(&self) -> CCBUF_R { + CCBUF_R::new(((self.bits >> 6) & 0x0003_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:5 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&mut self) -> DITHERBUF_W { + DITHERBUF_W { w: self } + } + #[doc = "Bits 6:23 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccbuf(&mut self) -> CCBUF_W { + CCBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccbuf_dith6_mode](index.html) module"] +pub struct CCBUF_DITH6_MODE_SPEC; +impl crate::RegisterSpec for CCBUF_DITH6_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ccbuf_dith6_mode::R](R) reader structure"] +impl crate::Readable for CCBUF_DITH6_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ccbuf_dith6_mode::W](W) writer structure"] +impl crate::Writable for CCBUF_DITH6_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CCBUF_DITH6_MODE[%s] +to value 0"] +impl crate::Resettable for CCBUF_DITH6_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/tcc0/count.rs b/pac/atsamc21j/src/tcc0/count.rs new file mode 100644 index 000000000000..7628f2c0d5e1 --- /dev/null +++ b/pac/atsamc21j/src/tcc0/count.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Count\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count](index.html) module"] +pub struct COUNT_SPEC; +impl crate::RegisterSpec for COUNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [count::R](R) reader structure"] +impl crate::Readable for COUNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count::W](W) writer structure"] +impl crate::Writable for COUNT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT to value 0"] +impl crate::Resettable for COUNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/tcc0/count_dith4_mode.rs b/pac/atsamc21j/src/tcc0/count_dith4_mode.rs new file mode 100644 index 000000000000..fc058ae5efd5 --- /dev/null +++ b/pac/atsamc21j/src/tcc0/count_dith4_mode.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT_DITH4_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT_DITH4_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x000f_ffff << 4)) | ((value as u32 & 0x000f_ffff) << 4); + self.w + } +} +impl R { + #[doc = "Bits 4:23 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 4) & 0x000f_ffff) as u32) + } +} +impl W { + #[doc = "Bits 4:23 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Count\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count_dith4_mode](index.html) module"] +pub struct COUNT_DITH4_MODE_SPEC; +impl crate::RegisterSpec for COUNT_DITH4_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [count_dith4_mode::R](R) reader structure"] +impl crate::Readable for COUNT_DITH4_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count_dith4_mode::W](W) writer structure"] +impl crate::Writable for COUNT_DITH4_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT_DITH4_MODE to value 0"] +impl crate::Resettable for COUNT_DITH4_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/tcc0/count_dith5_mode.rs b/pac/atsamc21j/src/tcc0/count_dith5_mode.rs new file mode 100644 index 000000000000..e66e20310726 --- /dev/null +++ b/pac/atsamc21j/src/tcc0/count_dith5_mode.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT_DITH5_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT_DITH5_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0007_ffff << 5)) | ((value as u32 & 0x0007_ffff) << 5); + self.w + } +} +impl R { + #[doc = "Bits 5:23 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 5) & 0x0007_ffff) as u32) + } +} +impl W { + #[doc = "Bits 5:23 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Count\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count_dith5_mode](index.html) module"] +pub struct COUNT_DITH5_MODE_SPEC; +impl crate::RegisterSpec for COUNT_DITH5_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [count_dith5_mode::R](R) reader structure"] +impl crate::Readable for COUNT_DITH5_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count_dith5_mode::W](W) writer structure"] +impl crate::Writable for COUNT_DITH5_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT_DITH5_MODE to value 0"] +impl crate::Resettable for COUNT_DITH5_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/tcc0/count_dith6_mode.rs b/pac/atsamc21j/src/tcc0/count_dith6_mode.rs new file mode 100644 index 000000000000..5410fc6c9459 --- /dev/null +++ b/pac/atsamc21j/src/tcc0/count_dith6_mode.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT_DITH6_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT_DITH6_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0003_ffff << 6)) | ((value as u32 & 0x0003_ffff) << 6); + self.w + } +} +impl R { + #[doc = "Bits 6:23 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 6) & 0x0003_ffff) as u32) + } +} +impl W { + #[doc = "Bits 6:23 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Count\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count_dith6_mode](index.html) module"] +pub struct COUNT_DITH6_MODE_SPEC; +impl crate::RegisterSpec for COUNT_DITH6_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [count_dith6_mode::R](R) reader structure"] +impl crate::Readable for COUNT_DITH6_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count_dith6_mode::W](W) writer structure"] +impl crate::Writable for COUNT_DITH6_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT_DITH6_MODE to value 0"] +impl crate::Resettable for COUNT_DITH6_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/tcc0/ctrla.rs b/pac/atsamc21j/src/tcc0/ctrla.rs new file mode 100644 index 000000000000..b717d1ac6ae0 --- /dev/null +++ b/pac/atsamc21j/src/tcc0/ctrla.rs @@ -0,0 +1,911 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Enhanced Resolution\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum RESOLUTION_A { + #[doc = "0: Dithering is disabled"] + NONE = 0, + #[doc = "1: Dithering is done every 16 PWM frames"] + DITH4 = 1, + #[doc = "2: Dithering is done every 32 PWM frames"] + DITH5 = 2, + #[doc = "3: Dithering is done every 64 PWM frames"] + DITH6 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RESOLUTION_A) -> Self { + variant as _ + } +} +#[doc = "Field `RESOLUTION` reader - Enhanced Resolution"] +pub struct RESOLUTION_R(crate::FieldReader); +impl RESOLUTION_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RESOLUTION_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RESOLUTION_A { + match self.bits { + 0 => RESOLUTION_A::NONE, + 1 => RESOLUTION_A::DITH4, + 2 => RESOLUTION_A::DITH5, + 3 => RESOLUTION_A::DITH6, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == RESOLUTION_A::NONE + } + #[doc = "Checks if the value of the field is `DITH4`"] + #[inline(always)] + pub fn is_dith4(&self) -> bool { + **self == RESOLUTION_A::DITH4 + } + #[doc = "Checks if the value of the field is `DITH5`"] + #[inline(always)] + pub fn is_dith5(&self) -> bool { + **self == RESOLUTION_A::DITH5 + } + #[doc = "Checks if the value of the field is `DITH6`"] + #[inline(always)] + pub fn is_dith6(&self) -> bool { + **self == RESOLUTION_A::DITH6 + } +} +impl core::ops::Deref for RESOLUTION_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESOLUTION` writer - Enhanced Resolution"] +pub struct RESOLUTION_W<'a> { + w: &'a mut W, +} +impl<'a> RESOLUTION_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RESOLUTION_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Dithering is disabled"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(RESOLUTION_A::NONE) + } + #[doc = "Dithering is done every 16 PWM frames"] + #[inline(always)] + pub fn dith4(self) -> &'a mut W { + self.variant(RESOLUTION_A::DITH4) + } + #[doc = "Dithering is done every 32 PWM frames"] + #[inline(always)] + pub fn dith5(self) -> &'a mut W { + self.variant(RESOLUTION_A::DITH5) + } + #[doc = "Dithering is done every 64 PWM frames"] + #[inline(always)] + pub fn dith6(self) -> &'a mut W { + self.variant(RESOLUTION_A::DITH6) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 5)) | ((value as u32 & 0x03) << 5); + self.w + } +} +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: No division"] + DIV1 = 0, + #[doc = "1: Divide by 2"] + DIV2 = 1, + #[doc = "2: Divide by 4"] + DIV4 = 2, + #[doc = "3: Divide by 8"] + DIV8 = 3, + #[doc = "4: Divide by 16"] + DIV16 = 4, + #[doc = "5: Divide by 64"] + DIV64 = 5, + #[doc = "6: Divide by 256"] + DIV256 = 6, + #[doc = "7: Divide by 1024"] + DIV1024 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PRESCALER_A { + match self.bits { + 0 => PRESCALER_A::DIV1, + 1 => PRESCALER_A::DIV2, + 2 => PRESCALER_A::DIV4, + 3 => PRESCALER_A::DIV8, + 4 => PRESCALER_A::DIV16, + 5 => PRESCALER_A::DIV64, + 6 => PRESCALER_A::DIV256, + 7 => PRESCALER_A::DIV1024, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == PRESCALER_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PRESCALER_A::DIV1024 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "No division"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1) + } + #[doc = "Divide by 2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "Divide by 4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "Divide by 8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "Divide by 16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "Divide by 64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "Divide by 256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = "Divide by 1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Prescaler and Counter Synchronization Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCSYNC_A { + #[doc = "0: Reload or reset counter on next GCLK"] + GCLK = 0, + #[doc = "1: Reload or reset counter on next prescaler clock"] + PRESC = 1, + #[doc = "2: Reload or reset counter on next GCLK and reset prescaler counter"] + RESYNC = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCSYNC_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCSYNC` reader - Prescaler and Counter Synchronization Selection"] +pub struct PRESCSYNC_R(crate::FieldReader); +impl PRESCSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCSYNC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCSYNC_A::GCLK), + 1 => Some(PRESCSYNC_A::PRESC), + 2 => Some(PRESCSYNC_A::RESYNC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `GCLK`"] + #[inline(always)] + pub fn is_gclk(&self) -> bool { + **self == PRESCSYNC_A::GCLK + } + #[doc = "Checks if the value of the field is `PRESC`"] + #[inline(always)] + pub fn is_presc(&self) -> bool { + **self == PRESCSYNC_A::PRESC + } + #[doc = "Checks if the value of the field is `RESYNC`"] + #[inline(always)] + pub fn is_resync(&self) -> bool { + **self == PRESCSYNC_A::RESYNC + } +} +impl core::ops::Deref for PRESCSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCSYNC` writer - Prescaler and Counter Synchronization Selection"] +pub struct PRESCSYNC_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCSYNC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCSYNC_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Reload or reset counter on next GCLK"] + #[inline(always)] + pub fn gclk(self) -> &'a mut W { + self.variant(PRESCSYNC_A::GCLK) + } + #[doc = "Reload or reset counter on next prescaler clock"] + #[inline(always)] + pub fn presc(self) -> &'a mut W { + self.variant(PRESCSYNC_A::PRESC) + } + #[doc = "Reload or reset counter on next GCLK and reset prescaler counter"] + #[inline(always)] + pub fn resync(self) -> &'a mut W { + self.variant(PRESCSYNC_A::RESYNC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 12)) | ((value as u32 & 0x03) << 12); + self.w + } +} +#[doc = "Field `ALOCK` reader - Auto Lock"] +pub struct ALOCK_R(crate::FieldReader); +impl ALOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALOCK` writer - Auto Lock"] +pub struct ALOCK_W<'a> { + w: &'a mut W, +} +impl<'a> ALOCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `MSYNC` reader - Master Synchronization (only for TCC Slave Instance)"] +pub struct MSYNC_R(crate::FieldReader); +impl MSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MSYNC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MSYNC` writer - Master Synchronization (only for TCC Slave Instance)"] +pub struct MSYNC_W<'a> { + w: &'a mut W, +} +impl<'a> MSYNC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `DMAOS` reader - DMA One-shot Trigger Mode"] +pub struct DMAOS_R(crate::FieldReader); +impl DMAOS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DMAOS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DMAOS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DMAOS` writer - DMA One-shot Trigger Mode"] +pub struct DMAOS_W<'a> { + w: &'a mut W, +} +impl<'a> DMAOS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `CPTEN0` reader - Capture Channel 0 Enable"] +pub struct CPTEN0_R(crate::FieldReader); +impl CPTEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPTEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CPTEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPTEN0` writer - Capture Channel 0 Enable"] +pub struct CPTEN0_W<'a> { + w: &'a mut W, +} +impl<'a> CPTEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `CPTEN1` reader - Capture Channel 1 Enable"] +pub struct CPTEN1_R(crate::FieldReader); +impl CPTEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPTEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CPTEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPTEN1` writer - Capture Channel 1 Enable"] +pub struct CPTEN1_W<'a> { + w: &'a mut W, +} +impl<'a> CPTEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `CPTEN2` reader - Capture Channel 2 Enable"] +pub struct CPTEN2_R(crate::FieldReader); +impl CPTEN2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPTEN2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CPTEN2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPTEN2` writer - Capture Channel 2 Enable"] +pub struct CPTEN2_W<'a> { + w: &'a mut W, +} +impl<'a> CPTEN2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `CPTEN3` reader - Capture Channel 3 Enable"] +pub struct CPTEN3_R(crate::FieldReader); +impl CPTEN3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPTEN3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CPTEN3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPTEN3` writer - Capture Channel 3 Enable"] +pub struct CPTEN3_W<'a> { + w: &'a mut W, +} +impl<'a> CPTEN3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 5:6 - Enhanced Resolution"] + #[inline(always)] + pub fn resolution(&self) -> RESOLUTION_R { + RESOLUTION_R::new(((self.bits >> 5) & 0x03) as u8) + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 11 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bits 12:13 - Prescaler and Counter Synchronization Selection"] + #[inline(always)] + pub fn prescsync(&self) -> PRESCSYNC_R { + PRESCSYNC_R::new(((self.bits >> 12) & 0x03) as u8) + } + #[doc = "Bit 14 - Auto Lock"] + #[inline(always)] + pub fn alock(&self) -> ALOCK_R { + ALOCK_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Master Synchronization (only for TCC Slave Instance)"] + #[inline(always)] + pub fn msync(&self) -> MSYNC_R { + MSYNC_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 23 - DMA One-shot Trigger Mode"] + #[inline(always)] + pub fn dmaos(&self) -> DMAOS_R { + DMAOS_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn cpten0(&self) -> CPTEN0_R { + CPTEN0_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn cpten1(&self) -> CPTEN1_R { + CPTEN1_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Capture Channel 2 Enable"] + #[inline(always)] + pub fn cpten2(&self) -> CPTEN2_R { + CPTEN2_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Capture Channel 3 Enable"] + #[inline(always)] + pub fn cpten3(&self) -> CPTEN3_R { + CPTEN3_R::new(((self.bits >> 27) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 5:6 - Enhanced Resolution"] + #[inline(always)] + pub fn resolution(&mut self) -> RESOLUTION_W { + RESOLUTION_W { w: self } + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Bit 11 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bits 12:13 - Prescaler and Counter Synchronization Selection"] + #[inline(always)] + pub fn prescsync(&mut self) -> PRESCSYNC_W { + PRESCSYNC_W { w: self } + } + #[doc = "Bit 14 - Auto Lock"] + #[inline(always)] + pub fn alock(&mut self) -> ALOCK_W { + ALOCK_W { w: self } + } + #[doc = "Bit 15 - Master Synchronization (only for TCC Slave Instance)"] + #[inline(always)] + pub fn msync(&mut self) -> MSYNC_W { + MSYNC_W { w: self } + } + #[doc = "Bit 23 - DMA One-shot Trigger Mode"] + #[inline(always)] + pub fn dmaos(&mut self) -> DMAOS_W { + DMAOS_W { w: self } + } + #[doc = "Bit 24 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn cpten0(&mut self) -> CPTEN0_W { + CPTEN0_W { w: self } + } + #[doc = "Bit 25 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn cpten1(&mut self) -> CPTEN1_W { + CPTEN1_W { w: self } + } + #[doc = "Bit 26 - Capture Channel 2 Enable"] + #[inline(always)] + pub fn cpten2(&mut self) -> CPTEN2_W { + CPTEN2_W { w: self } + } + #[doc = "Bit 27 - Capture Channel 3 Enable"] + #[inline(always)] + pub fn cpten3(&mut self) -> CPTEN3_W { + CPTEN3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/tcc0/ctrlbclr.rs b/pac/atsamc21j/src/tcc0/ctrlbclr.rs new file mode 100644 index 000000000000..f96ce81ffde3 --- /dev/null +++ b/pac/atsamc21j/src/tcc0/ctrlbclr.rs @@ -0,0 +1,457 @@ +#[doc = "Register `CTRLBCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Counter Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `LUPD` reader - Lock Update"] +pub struct LUPD_R(crate::FieldReader); +impl LUPD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LUPD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LUPD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LUPD` writer - Lock Update"] +pub struct LUPD_W<'a> { + w: &'a mut W, +} +impl<'a> LUPD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ONESHOT` reader - One-Shot"] +pub struct ONESHOT_R(crate::FieldReader); +impl ONESHOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONESHOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONESHOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONESHOT` writer - One-Shot"] +pub struct ONESHOT_W<'a> { + w: &'a mut W, +} +impl<'a> ONESHOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Ramp Index Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum IDXCMD_A { + #[doc = "0: Command disabled: Index toggles between cycles A and B"] + DISABLE = 0, + #[doc = "1: Set index: cycle B will be forced in the next cycle"] + SET = 1, + #[doc = "2: Clear index: cycle A will be forced in the next cycle"] + CLEAR = 2, + #[doc = "3: Hold index: the next cycle will be the same as the current cycle"] + HOLD = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: IDXCMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `IDXCMD` reader - Ramp Index Command"] +pub struct IDXCMD_R(crate::FieldReader); +impl IDXCMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + IDXCMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> IDXCMD_A { + match self.bits { + 0 => IDXCMD_A::DISABLE, + 1 => IDXCMD_A::SET, + 2 => IDXCMD_A::CLEAR, + 3 => IDXCMD_A::HOLD, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == IDXCMD_A::DISABLE + } + #[doc = "Checks if the value of the field is `SET`"] + #[inline(always)] + pub fn is_set(&self) -> bool { + **self == IDXCMD_A::SET + } + #[doc = "Checks if the value of the field is `CLEAR`"] + #[inline(always)] + pub fn is_clear(&self) -> bool { + **self == IDXCMD_A::CLEAR + } + #[doc = "Checks if the value of the field is `HOLD`"] + #[inline(always)] + pub fn is_hold(&self) -> bool { + **self == IDXCMD_A::HOLD + } +} +impl core::ops::Deref for IDXCMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IDXCMD` writer - Ramp Index Command"] +pub struct IDXCMD_W<'a> { + w: &'a mut W, +} +impl<'a> IDXCMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: IDXCMD_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Command disabled: Index toggles between cycles A and B"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(IDXCMD_A::DISABLE) + } + #[doc = "Set index: cycle B will be forced in the next cycle"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(IDXCMD_A::SET) + } + #[doc = "Clear index: cycle A will be forced in the next cycle"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(IDXCMD_A::CLEAR) + } + #[doc = "Hold index: the next cycle will be the same as the current cycle"] + #[inline(always)] + pub fn hold(self) -> &'a mut W { + self.variant(IDXCMD_A::HOLD) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 3)) | ((value as u8 & 0x03) << 3); + self.w + } +} +#[doc = "TCC Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Clear start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force stop"] + STOP = 2, + #[doc = "3: Force update or double buffered registers"] + UPDATE = 3, + #[doc = "4: Force COUNT read synchronization"] + READSYNC = 4, + #[doc = "5: One-shot DMA trigger"] + DMAOS = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - TCC Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NONE), + 1 => Some(CMD_A::RETRIGGER), + 2 => Some(CMD_A::STOP), + 3 => Some(CMD_A::UPDATE), + 4 => Some(CMD_A::READSYNC), + 5 => Some(CMD_A::DMAOS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == CMD_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == CMD_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == CMD_A::STOP + } + #[doc = "Checks if the value of the field is `UPDATE`"] + #[inline(always)] + pub fn is_update(&self) -> bool { + **self == CMD_A::UPDATE + } + #[doc = "Checks if the value of the field is `READSYNC`"] + #[inline(always)] + pub fn is_readsync(&self) -> bool { + **self == CMD_A::READSYNC + } + #[doc = "Checks if the value of the field is `DMAOS`"] + #[inline(always)] + pub fn is_dmaos(&self) -> bool { + **self == CMD_A::DMAOS + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - TCC Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMD_A::NONE) + } + #[doc = "Clear start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMD_A::RETRIGGER) + } + #[doc = "Force stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMD_A::STOP) + } + #[doc = "Force update or double buffered registers"] + #[inline(always)] + pub fn update(self) -> &'a mut W { + self.variant(CMD_A::UPDATE) + } + #[doc = "Force COUNT read synchronization"] + #[inline(always)] + pub fn readsync(self) -> &'a mut W { + self.variant(CMD_A::READSYNC) + } + #[doc = "One-shot DMA trigger"] + #[inline(always)] + pub fn dmaos(self) -> &'a mut W { + self.variant(CMD_A::DMAOS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 5)) | ((value as u8 & 0x07) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&self) -> LUPD_R { + LUPD_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - One-Shot"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 3:4 - Ramp Index Command"] + #[inline(always)] + pub fn idxcmd(&self) -> IDXCMD_R { + IDXCMD_R::new(((self.bits >> 3) & 0x03) as u8) + } + #[doc = "Bits 5:7 - TCC Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 5) & 0x07) as u8) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&mut self) -> LUPD_W { + LUPD_W { w: self } + } + #[doc = "Bit 2 - One-Shot"] + #[inline(always)] + pub fn oneshot(&mut self) -> ONESHOT_W { + ONESHOT_W { w: self } + } + #[doc = "Bits 3:4 - Ramp Index Command"] + #[inline(always)] + pub fn idxcmd(&mut self) -> IDXCMD_W { + IDXCMD_W { w: self } + } + #[doc = "Bits 5:7 - TCC Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbclr](index.html) module"] +pub struct CTRLBCLR_SPEC; +impl crate::RegisterSpec for CTRLBCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbclr::R](R) reader structure"] +impl crate::Readable for CTRLBCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbclr::W](W) writer structure"] +impl crate::Writable for CTRLBCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLBCLR to value 0"] +impl crate::Resettable for CTRLBCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/tcc0/ctrlbset.rs b/pac/atsamc21j/src/tcc0/ctrlbset.rs new file mode 100644 index 000000000000..7002dd71efe7 --- /dev/null +++ b/pac/atsamc21j/src/tcc0/ctrlbset.rs @@ -0,0 +1,457 @@ +#[doc = "Register `CTRLBSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Counter Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `LUPD` reader - Lock Update"] +pub struct LUPD_R(crate::FieldReader); +impl LUPD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LUPD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LUPD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LUPD` writer - Lock Update"] +pub struct LUPD_W<'a> { + w: &'a mut W, +} +impl<'a> LUPD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ONESHOT` reader - One-Shot"] +pub struct ONESHOT_R(crate::FieldReader); +impl ONESHOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONESHOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONESHOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONESHOT` writer - One-Shot"] +pub struct ONESHOT_W<'a> { + w: &'a mut W, +} +impl<'a> ONESHOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Ramp Index Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum IDXCMD_A { + #[doc = "0: Command disabled: Index toggles between cycles A and B"] + DISABLE = 0, + #[doc = "1: Set index: cycle B will be forced in the next cycle"] + SET = 1, + #[doc = "2: Clear index: cycle A will be forced in the next cycle"] + CLEAR = 2, + #[doc = "3: Hold index: the next cycle will be the same as the current cycle"] + HOLD = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: IDXCMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `IDXCMD` reader - Ramp Index Command"] +pub struct IDXCMD_R(crate::FieldReader); +impl IDXCMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + IDXCMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> IDXCMD_A { + match self.bits { + 0 => IDXCMD_A::DISABLE, + 1 => IDXCMD_A::SET, + 2 => IDXCMD_A::CLEAR, + 3 => IDXCMD_A::HOLD, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == IDXCMD_A::DISABLE + } + #[doc = "Checks if the value of the field is `SET`"] + #[inline(always)] + pub fn is_set(&self) -> bool { + **self == IDXCMD_A::SET + } + #[doc = "Checks if the value of the field is `CLEAR`"] + #[inline(always)] + pub fn is_clear(&self) -> bool { + **self == IDXCMD_A::CLEAR + } + #[doc = "Checks if the value of the field is `HOLD`"] + #[inline(always)] + pub fn is_hold(&self) -> bool { + **self == IDXCMD_A::HOLD + } +} +impl core::ops::Deref for IDXCMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IDXCMD` writer - Ramp Index Command"] +pub struct IDXCMD_W<'a> { + w: &'a mut W, +} +impl<'a> IDXCMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: IDXCMD_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Command disabled: Index toggles between cycles A and B"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(IDXCMD_A::DISABLE) + } + #[doc = "Set index: cycle B will be forced in the next cycle"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(IDXCMD_A::SET) + } + #[doc = "Clear index: cycle A will be forced in the next cycle"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(IDXCMD_A::CLEAR) + } + #[doc = "Hold index: the next cycle will be the same as the current cycle"] + #[inline(always)] + pub fn hold(self) -> &'a mut W { + self.variant(IDXCMD_A::HOLD) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 3)) | ((value as u8 & 0x03) << 3); + self.w + } +} +#[doc = "TCC Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Clear start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force stop"] + STOP = 2, + #[doc = "3: Force update or double buffered registers"] + UPDATE = 3, + #[doc = "4: Force COUNT read synchronization"] + READSYNC = 4, + #[doc = "5: One-shot DMA trigger"] + DMAOS = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - TCC Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NONE), + 1 => Some(CMD_A::RETRIGGER), + 2 => Some(CMD_A::STOP), + 3 => Some(CMD_A::UPDATE), + 4 => Some(CMD_A::READSYNC), + 5 => Some(CMD_A::DMAOS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == CMD_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == CMD_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == CMD_A::STOP + } + #[doc = "Checks if the value of the field is `UPDATE`"] + #[inline(always)] + pub fn is_update(&self) -> bool { + **self == CMD_A::UPDATE + } + #[doc = "Checks if the value of the field is `READSYNC`"] + #[inline(always)] + pub fn is_readsync(&self) -> bool { + **self == CMD_A::READSYNC + } + #[doc = "Checks if the value of the field is `DMAOS`"] + #[inline(always)] + pub fn is_dmaos(&self) -> bool { + **self == CMD_A::DMAOS + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - TCC Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMD_A::NONE) + } + #[doc = "Clear start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMD_A::RETRIGGER) + } + #[doc = "Force stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMD_A::STOP) + } + #[doc = "Force update or double buffered registers"] + #[inline(always)] + pub fn update(self) -> &'a mut W { + self.variant(CMD_A::UPDATE) + } + #[doc = "Force COUNT read synchronization"] + #[inline(always)] + pub fn readsync(self) -> &'a mut W { + self.variant(CMD_A::READSYNC) + } + #[doc = "One-shot DMA trigger"] + #[inline(always)] + pub fn dmaos(self) -> &'a mut W { + self.variant(CMD_A::DMAOS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 5)) | ((value as u8 & 0x07) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&self) -> LUPD_R { + LUPD_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - One-Shot"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 3:4 - Ramp Index Command"] + #[inline(always)] + pub fn idxcmd(&self) -> IDXCMD_R { + IDXCMD_R::new(((self.bits >> 3) & 0x03) as u8) + } + #[doc = "Bits 5:7 - TCC Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 5) & 0x07) as u8) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&mut self) -> LUPD_W { + LUPD_W { w: self } + } + #[doc = "Bit 2 - One-Shot"] + #[inline(always)] + pub fn oneshot(&mut self) -> ONESHOT_W { + ONESHOT_W { w: self } + } + #[doc = "Bits 3:4 - Ramp Index Command"] + #[inline(always)] + pub fn idxcmd(&mut self) -> IDXCMD_W { + IDXCMD_W { w: self } + } + #[doc = "Bits 5:7 - TCC Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbset](index.html) module"] +pub struct CTRLBSET_SPEC; +impl crate::RegisterSpec for CTRLBSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbset::R](R) reader structure"] +impl crate::Readable for CTRLBSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbset::W](W) writer structure"] +impl crate::Writable for CTRLBSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLBSET to value 0"] +impl crate::Resettable for CTRLBSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/tcc0/dbgctrl.rs b/pac/atsamc21j/src/tcc0/dbgctrl.rs new file mode 100644 index 000000000000..313ebe3f5c18 --- /dev/null +++ b/pac/atsamc21j/src/tcc0/dbgctrl.rs @@ -0,0 +1,160 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Debug Running Mode"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Debug Running Mode"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `FDDBD` reader - Fault Detection on Debug Break Detection"] +pub struct FDDBD_R(crate::FieldReader); +impl FDDBD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FDDBD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FDDBD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FDDBD` writer - Fault Detection on Debug Break Detection"] +pub struct FDDBD_W<'a> { + w: &'a mut W, +} +impl<'a> FDDBD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Running Mode"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 2 - Fault Detection on Debug Break Detection"] + #[inline(always)] + pub fn fddbd(&self) -> FDDBD_R { + FDDBD_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Running Mode"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Bit 2 - Fault Detection on Debug Break Detection"] + #[inline(always)] + pub fn fddbd(&mut self) -> FDDBD_W { + FDDBD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/tcc0/drvctrl.rs b/pac/atsamc21j/src/tcc0/drvctrl.rs new file mode 100644 index 000000000000..316041e1e3be --- /dev/null +++ b/pac/atsamc21j/src/tcc0/drvctrl.rs @@ -0,0 +1,1268 @@ +#[doc = "Register `DRVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DRVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `NRE0` reader - Non-Recoverable State 0 Output Enable"] +pub struct NRE0_R(crate::FieldReader); +impl NRE0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRE0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRE0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRE0` writer - Non-Recoverable State 0 Output Enable"] +pub struct NRE0_W<'a> { + w: &'a mut W, +} +impl<'a> NRE0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `NRE1` reader - Non-Recoverable State 1 Output Enable"] +pub struct NRE1_R(crate::FieldReader); +impl NRE1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRE1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRE1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRE1` writer - Non-Recoverable State 1 Output Enable"] +pub struct NRE1_W<'a> { + w: &'a mut W, +} +impl<'a> NRE1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `NRE2` reader - Non-Recoverable State 2 Output Enable"] +pub struct NRE2_R(crate::FieldReader); +impl NRE2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRE2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRE2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRE2` writer - Non-Recoverable State 2 Output Enable"] +pub struct NRE2_W<'a> { + w: &'a mut W, +} +impl<'a> NRE2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `NRE3` reader - Non-Recoverable State 3 Output Enable"] +pub struct NRE3_R(crate::FieldReader); +impl NRE3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRE3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRE3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRE3` writer - Non-Recoverable State 3 Output Enable"] +pub struct NRE3_W<'a> { + w: &'a mut W, +} +impl<'a> NRE3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `NRE4` reader - Non-Recoverable State 4 Output Enable"] +pub struct NRE4_R(crate::FieldReader); +impl NRE4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRE4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRE4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRE4` writer - Non-Recoverable State 4 Output Enable"] +pub struct NRE4_W<'a> { + w: &'a mut W, +} +impl<'a> NRE4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `NRE5` reader - Non-Recoverable State 5 Output Enable"] +pub struct NRE5_R(crate::FieldReader); +impl NRE5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRE5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRE5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRE5` writer - Non-Recoverable State 5 Output Enable"] +pub struct NRE5_W<'a> { + w: &'a mut W, +} +impl<'a> NRE5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `NRE6` reader - Non-Recoverable State 6 Output Enable"] +pub struct NRE6_R(crate::FieldReader); +impl NRE6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRE6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRE6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRE6` writer - Non-Recoverable State 6 Output Enable"] +pub struct NRE6_W<'a> { + w: &'a mut W, +} +impl<'a> NRE6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `NRE7` reader - Non-Recoverable State 7 Output Enable"] +pub struct NRE7_R(crate::FieldReader); +impl NRE7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRE7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRE7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRE7` writer - Non-Recoverable State 7 Output Enable"] +pub struct NRE7_W<'a> { + w: &'a mut W, +} +impl<'a> NRE7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `NRV0` reader - Non-Recoverable State 0 Output Value"] +pub struct NRV0_R(crate::FieldReader); +impl NRV0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRV0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRV0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRV0` writer - Non-Recoverable State 0 Output Value"] +pub struct NRV0_W<'a> { + w: &'a mut W, +} +impl<'a> NRV0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `NRV1` reader - Non-Recoverable State 1 Output Value"] +pub struct NRV1_R(crate::FieldReader); +impl NRV1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRV1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRV1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRV1` writer - Non-Recoverable State 1 Output Value"] +pub struct NRV1_W<'a> { + w: &'a mut W, +} +impl<'a> NRV1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `NRV2` reader - Non-Recoverable State 2 Output Value"] +pub struct NRV2_R(crate::FieldReader); +impl NRV2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRV2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRV2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRV2` writer - Non-Recoverable State 2 Output Value"] +pub struct NRV2_W<'a> { + w: &'a mut W, +} +impl<'a> NRV2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `NRV3` reader - Non-Recoverable State 3 Output Value"] +pub struct NRV3_R(crate::FieldReader); +impl NRV3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRV3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRV3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRV3` writer - Non-Recoverable State 3 Output Value"] +pub struct NRV3_W<'a> { + w: &'a mut W, +} +impl<'a> NRV3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `NRV4` reader - Non-Recoverable State 4 Output Value"] +pub struct NRV4_R(crate::FieldReader); +impl NRV4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRV4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRV4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRV4` writer - Non-Recoverable State 4 Output Value"] +pub struct NRV4_W<'a> { + w: &'a mut W, +} +impl<'a> NRV4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `NRV5` reader - Non-Recoverable State 5 Output Value"] +pub struct NRV5_R(crate::FieldReader); +impl NRV5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRV5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRV5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRV5` writer - Non-Recoverable State 5 Output Value"] +pub struct NRV5_W<'a> { + w: &'a mut W, +} +impl<'a> NRV5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `NRV6` reader - Non-Recoverable State 6 Output Value"] +pub struct NRV6_R(crate::FieldReader); +impl NRV6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRV6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRV6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRV6` writer - Non-Recoverable State 6 Output Value"] +pub struct NRV6_W<'a> { + w: &'a mut W, +} +impl<'a> NRV6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `NRV7` reader - Non-Recoverable State 7 Output Value"] +pub struct NRV7_R(crate::FieldReader); +impl NRV7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRV7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRV7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRV7` writer - Non-Recoverable State 7 Output Value"] +pub struct NRV7_W<'a> { + w: &'a mut W, +} +impl<'a> NRV7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `INVEN0` reader - Output Waveform 0 Inversion"] +pub struct INVEN0_R(crate::FieldReader); +impl INVEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN0` writer - Output Waveform 0 Inversion"] +pub struct INVEN0_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `INVEN1` reader - Output Waveform 1 Inversion"] +pub struct INVEN1_R(crate::FieldReader); +impl INVEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN1` writer - Output Waveform 1 Inversion"] +pub struct INVEN1_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `INVEN2` reader - Output Waveform 2 Inversion"] +pub struct INVEN2_R(crate::FieldReader); +impl INVEN2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN2` writer - Output Waveform 2 Inversion"] +pub struct INVEN2_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `INVEN3` reader - Output Waveform 3 Inversion"] +pub struct INVEN3_R(crate::FieldReader); +impl INVEN3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN3` writer - Output Waveform 3 Inversion"] +pub struct INVEN3_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `INVEN4` reader - Output Waveform 4 Inversion"] +pub struct INVEN4_R(crate::FieldReader); +impl INVEN4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN4` writer - Output Waveform 4 Inversion"] +pub struct INVEN4_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `INVEN5` reader - Output Waveform 5 Inversion"] +pub struct INVEN5_R(crate::FieldReader); +impl INVEN5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN5` writer - Output Waveform 5 Inversion"] +pub struct INVEN5_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `INVEN6` reader - Output Waveform 6 Inversion"] +pub struct INVEN6_R(crate::FieldReader); +impl INVEN6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN6` writer - Output Waveform 6 Inversion"] +pub struct INVEN6_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `INVEN7` reader - Output Waveform 7 Inversion"] +pub struct INVEN7_R(crate::FieldReader); +impl INVEN7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN7` writer - Output Waveform 7 Inversion"] +pub struct INVEN7_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `FILTERVAL0` reader - Non-Recoverable Fault Input 0 Filter Value"] +pub struct FILTERVAL0_R(crate::FieldReader); +impl FILTERVAL0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FILTERVAL0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTERVAL0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTERVAL0` writer - Non-Recoverable Fault Input 0 Filter Value"] +pub struct FILTERVAL0_W<'a> { + w: &'a mut W, +} +impl<'a> FILTERVAL0_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Field `FILTERVAL1` reader - Non-Recoverable Fault Input 1 Filter Value"] +pub struct FILTERVAL1_R(crate::FieldReader); +impl FILTERVAL1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FILTERVAL1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTERVAL1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTERVAL1` writer - Non-Recoverable Fault Input 1 Filter Value"] +pub struct FILTERVAL1_W<'a> { + w: &'a mut W, +} +impl<'a> FILTERVAL1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 28)) | ((value as u32 & 0x0f) << 28); + self.w + } +} +impl R { + #[doc = "Bit 0 - Non-Recoverable State 0 Output Enable"] + #[inline(always)] + pub fn nre0(&self) -> NRE0_R { + NRE0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Non-Recoverable State 1 Output Enable"] + #[inline(always)] + pub fn nre1(&self) -> NRE1_R { + NRE1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Non-Recoverable State 2 Output Enable"] + #[inline(always)] + pub fn nre2(&self) -> NRE2_R { + NRE2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Non-Recoverable State 3 Output Enable"] + #[inline(always)] + pub fn nre3(&self) -> NRE3_R { + NRE3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Non-Recoverable State 4 Output Enable"] + #[inline(always)] + pub fn nre4(&self) -> NRE4_R { + NRE4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Non-Recoverable State 5 Output Enable"] + #[inline(always)] + pub fn nre5(&self) -> NRE5_R { + NRE5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Non-Recoverable State 6 Output Enable"] + #[inline(always)] + pub fn nre6(&self) -> NRE6_R { + NRE6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Non-Recoverable State 7 Output Enable"] + #[inline(always)] + pub fn nre7(&self) -> NRE7_R { + NRE7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Non-Recoverable State 0 Output Value"] + #[inline(always)] + pub fn nrv0(&self) -> NRV0_R { + NRV0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Non-Recoverable State 1 Output Value"] + #[inline(always)] + pub fn nrv1(&self) -> NRV1_R { + NRV1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Non-Recoverable State 2 Output Value"] + #[inline(always)] + pub fn nrv2(&self) -> NRV2_R { + NRV2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Non-Recoverable State 3 Output Value"] + #[inline(always)] + pub fn nrv3(&self) -> NRV3_R { + NRV3_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Non-Recoverable State 4 Output Value"] + #[inline(always)] + pub fn nrv4(&self) -> NRV4_R { + NRV4_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Non-Recoverable State 5 Output Value"] + #[inline(always)] + pub fn nrv5(&self) -> NRV5_R { + NRV5_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Non-Recoverable State 6 Output Value"] + #[inline(always)] + pub fn nrv6(&self) -> NRV6_R { + NRV6_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Non-Recoverable State 7 Output Value"] + #[inline(always)] + pub fn nrv7(&self) -> NRV7_R { + NRV7_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Output Waveform 0 Inversion"] + #[inline(always)] + pub fn inven0(&self) -> INVEN0_R { + INVEN0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Output Waveform 1 Inversion"] + #[inline(always)] + pub fn inven1(&self) -> INVEN1_R { + INVEN1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Output Waveform 2 Inversion"] + #[inline(always)] + pub fn inven2(&self) -> INVEN2_R { + INVEN2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Output Waveform 3 Inversion"] + #[inline(always)] + pub fn inven3(&self) -> INVEN3_R { + INVEN3_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Output Waveform 4 Inversion"] + #[inline(always)] + pub fn inven4(&self) -> INVEN4_R { + INVEN4_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Output Waveform 5 Inversion"] + #[inline(always)] + pub fn inven5(&self) -> INVEN5_R { + INVEN5_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Output Waveform 6 Inversion"] + #[inline(always)] + pub fn inven6(&self) -> INVEN6_R { + INVEN6_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Output Waveform 7 Inversion"] + #[inline(always)] + pub fn inven7(&self) -> INVEN7_R { + INVEN7_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bits 24:27 - Non-Recoverable Fault Input 0 Filter Value"] + #[inline(always)] + pub fn filterval0(&self) -> FILTERVAL0_R { + FILTERVAL0_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bits 28:31 - Non-Recoverable Fault Input 1 Filter Value"] + #[inline(always)] + pub fn filterval1(&self) -> FILTERVAL1_R { + FILTERVAL1_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bit 0 - Non-Recoverable State 0 Output Enable"] + #[inline(always)] + pub fn nre0(&mut self) -> NRE0_W { + NRE0_W { w: self } + } + #[doc = "Bit 1 - Non-Recoverable State 1 Output Enable"] + #[inline(always)] + pub fn nre1(&mut self) -> NRE1_W { + NRE1_W { w: self } + } + #[doc = "Bit 2 - Non-Recoverable State 2 Output Enable"] + #[inline(always)] + pub fn nre2(&mut self) -> NRE2_W { + NRE2_W { w: self } + } + #[doc = "Bit 3 - Non-Recoverable State 3 Output Enable"] + #[inline(always)] + pub fn nre3(&mut self) -> NRE3_W { + NRE3_W { w: self } + } + #[doc = "Bit 4 - Non-Recoverable State 4 Output Enable"] + #[inline(always)] + pub fn nre4(&mut self) -> NRE4_W { + NRE4_W { w: self } + } + #[doc = "Bit 5 - Non-Recoverable State 5 Output Enable"] + #[inline(always)] + pub fn nre5(&mut self) -> NRE5_W { + NRE5_W { w: self } + } + #[doc = "Bit 6 - Non-Recoverable State 6 Output Enable"] + #[inline(always)] + pub fn nre6(&mut self) -> NRE6_W { + NRE6_W { w: self } + } + #[doc = "Bit 7 - Non-Recoverable State 7 Output Enable"] + #[inline(always)] + pub fn nre7(&mut self) -> NRE7_W { + NRE7_W { w: self } + } + #[doc = "Bit 8 - Non-Recoverable State 0 Output Value"] + #[inline(always)] + pub fn nrv0(&mut self) -> NRV0_W { + NRV0_W { w: self } + } + #[doc = "Bit 9 - Non-Recoverable State 1 Output Value"] + #[inline(always)] + pub fn nrv1(&mut self) -> NRV1_W { + NRV1_W { w: self } + } + #[doc = "Bit 10 - Non-Recoverable State 2 Output Value"] + #[inline(always)] + pub fn nrv2(&mut self) -> NRV2_W { + NRV2_W { w: self } + } + #[doc = "Bit 11 - Non-Recoverable State 3 Output Value"] + #[inline(always)] + pub fn nrv3(&mut self) -> NRV3_W { + NRV3_W { w: self } + } + #[doc = "Bit 12 - Non-Recoverable State 4 Output Value"] + #[inline(always)] + pub fn nrv4(&mut self) -> NRV4_W { + NRV4_W { w: self } + } + #[doc = "Bit 13 - Non-Recoverable State 5 Output Value"] + #[inline(always)] + pub fn nrv5(&mut self) -> NRV5_W { + NRV5_W { w: self } + } + #[doc = "Bit 14 - Non-Recoverable State 6 Output Value"] + #[inline(always)] + pub fn nrv6(&mut self) -> NRV6_W { + NRV6_W { w: self } + } + #[doc = "Bit 15 - Non-Recoverable State 7 Output Value"] + #[inline(always)] + pub fn nrv7(&mut self) -> NRV7_W { + NRV7_W { w: self } + } + #[doc = "Bit 16 - Output Waveform 0 Inversion"] + #[inline(always)] + pub fn inven0(&mut self) -> INVEN0_W { + INVEN0_W { w: self } + } + #[doc = "Bit 17 - Output Waveform 1 Inversion"] + #[inline(always)] + pub fn inven1(&mut self) -> INVEN1_W { + INVEN1_W { w: self } + } + #[doc = "Bit 18 - Output Waveform 2 Inversion"] + #[inline(always)] + pub fn inven2(&mut self) -> INVEN2_W { + INVEN2_W { w: self } + } + #[doc = "Bit 19 - Output Waveform 3 Inversion"] + #[inline(always)] + pub fn inven3(&mut self) -> INVEN3_W { + INVEN3_W { w: self } + } + #[doc = "Bit 20 - Output Waveform 4 Inversion"] + #[inline(always)] + pub fn inven4(&mut self) -> INVEN4_W { + INVEN4_W { w: self } + } + #[doc = "Bit 21 - Output Waveform 5 Inversion"] + #[inline(always)] + pub fn inven5(&mut self) -> INVEN5_W { + INVEN5_W { w: self } + } + #[doc = "Bit 22 - Output Waveform 6 Inversion"] + #[inline(always)] + pub fn inven6(&mut self) -> INVEN6_W { + INVEN6_W { w: self } + } + #[doc = "Bit 23 - Output Waveform 7 Inversion"] + #[inline(always)] + pub fn inven7(&mut self) -> INVEN7_W { + INVEN7_W { w: self } + } + #[doc = "Bits 24:27 - Non-Recoverable Fault Input 0 Filter Value"] + #[inline(always)] + pub fn filterval0(&mut self) -> FILTERVAL0_W { + FILTERVAL0_W { w: self } + } + #[doc = "Bits 28:31 - Non-Recoverable Fault Input 1 Filter Value"] + #[inline(always)] + pub fn filterval1(&mut self) -> FILTERVAL1_W { + FILTERVAL1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Driver Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [drvctrl](index.html) module"] +pub struct DRVCTRL_SPEC; +impl crate::RegisterSpec for DRVCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [drvctrl::R](R) reader structure"] +impl crate::Readable for DRVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [drvctrl::W](W) writer structure"] +impl crate::Writable for DRVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DRVCTRL to value 0"] +impl crate::Resettable for DRVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/tcc0/evctrl.rs b/pac/atsamc21j/src/tcc0/evctrl.rs new file mode 100644 index 000000000000..334a53924d61 --- /dev/null +++ b/pac/atsamc21j/src/tcc0/evctrl.rs @@ -0,0 +1,1211 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Timer/counter Input Event0 Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EVACT0_A { + #[doc = "0: Event action disabled"] + OFF = 0, + #[doc = "1: Start, restart or re-trigger counter on event"] + RETRIGGER = 1, + #[doc = "2: Count on event"] + COUNTEV = 2, + #[doc = "3: Start counter on event"] + START = 3, + #[doc = "4: Increment counter on event"] + INC = 4, + #[doc = "5: Count on active state of asynchronous event"] + COUNT = 5, + #[doc = "6: Stamp capture"] + STAMP = 6, + #[doc = "7: Non-recoverable fault"] + FAULT = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EVACT0_A) -> Self { + variant as _ + } +} +#[doc = "Field `EVACT0` reader - Timer/counter Input Event0 Action"] +pub struct EVACT0_R(crate::FieldReader); +impl EVACT0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVACT0_A { + match self.bits { + 0 => EVACT0_A::OFF, + 1 => EVACT0_A::RETRIGGER, + 2 => EVACT0_A::COUNTEV, + 3 => EVACT0_A::START, + 4 => EVACT0_A::INC, + 5 => EVACT0_A::COUNT, + 6 => EVACT0_A::STAMP, + 7 => EVACT0_A::FAULT, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == EVACT0_A::OFF + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == EVACT0_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `COUNTEV`"] + #[inline(always)] + pub fn is_countev(&self) -> bool { + **self == EVACT0_A::COUNTEV + } + #[doc = "Checks if the value of the field is `START`"] + #[inline(always)] + pub fn is_start(&self) -> bool { + **self == EVACT0_A::START + } + #[doc = "Checks if the value of the field is `INC`"] + #[inline(always)] + pub fn is_inc(&self) -> bool { + **self == EVACT0_A::INC + } + #[doc = "Checks if the value of the field is `COUNT`"] + #[inline(always)] + pub fn is_count(&self) -> bool { + **self == EVACT0_A::COUNT + } + #[doc = "Checks if the value of the field is `STAMP`"] + #[inline(always)] + pub fn is_stamp(&self) -> bool { + **self == EVACT0_A::STAMP + } + #[doc = "Checks if the value of the field is `FAULT`"] + #[inline(always)] + pub fn is_fault(&self) -> bool { + **self == EVACT0_A::FAULT + } +} +impl core::ops::Deref for EVACT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT0` writer - Timer/counter Input Event0 Action"] +pub struct EVACT0_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT0_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EVACT0_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Event action disabled"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(EVACT0_A::OFF) + } + #[doc = "Start, restart or re-trigger counter on event"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(EVACT0_A::RETRIGGER) + } + #[doc = "Count on event"] + #[inline(always)] + pub fn countev(self) -> &'a mut W { + self.variant(EVACT0_A::COUNTEV) + } + #[doc = "Start counter on event"] + #[inline(always)] + pub fn start(self) -> &'a mut W { + self.variant(EVACT0_A::START) + } + #[doc = "Increment counter on event"] + #[inline(always)] + pub fn inc(self) -> &'a mut W { + self.variant(EVACT0_A::INC) + } + #[doc = "Count on active state of asynchronous event"] + #[inline(always)] + pub fn count(self) -> &'a mut W { + self.variant(EVACT0_A::COUNT) + } + #[doc = "Stamp capture"] + #[inline(always)] + pub fn stamp(self) -> &'a mut W { + self.variant(EVACT0_A::STAMP) + } + #[doc = "Non-recoverable fault"] + #[inline(always)] + pub fn fault(self) -> &'a mut W { + self.variant(EVACT0_A::FAULT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Timer/counter Input Event1 Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EVACT1_A { + #[doc = "0: Event action disabled"] + OFF = 0, + #[doc = "1: Re-trigger counter on event"] + RETRIGGER = 1, + #[doc = "2: Direction control"] + DIR = 2, + #[doc = "3: Stop counter on event"] + STOP = 3, + #[doc = "4: Decrement counter on event"] + DEC = 4, + #[doc = "5: Period capture value in CC0 register, pulse width capture value in CC1 register"] + PPW = 5, + #[doc = "6: Period capture value in CC1 register, pulse width capture value in CC0 register"] + PWP = 6, + #[doc = "7: Non-recoverable fault"] + FAULT = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EVACT1_A) -> Self { + variant as _ + } +} +#[doc = "Field `EVACT1` reader - Timer/counter Input Event1 Action"] +pub struct EVACT1_R(crate::FieldReader); +impl EVACT1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT1_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVACT1_A { + match self.bits { + 0 => EVACT1_A::OFF, + 1 => EVACT1_A::RETRIGGER, + 2 => EVACT1_A::DIR, + 3 => EVACT1_A::STOP, + 4 => EVACT1_A::DEC, + 5 => EVACT1_A::PPW, + 6 => EVACT1_A::PWP, + 7 => EVACT1_A::FAULT, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == EVACT1_A::OFF + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == EVACT1_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `DIR`"] + #[inline(always)] + pub fn is_dir(&self) -> bool { + **self == EVACT1_A::DIR + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == EVACT1_A::STOP + } + #[doc = "Checks if the value of the field is `DEC`"] + #[inline(always)] + pub fn is_dec(&self) -> bool { + **self == EVACT1_A::DEC + } + #[doc = "Checks if the value of the field is `PPW`"] + #[inline(always)] + pub fn is_ppw(&self) -> bool { + **self == EVACT1_A::PPW + } + #[doc = "Checks if the value of the field is `PWP`"] + #[inline(always)] + pub fn is_pwp(&self) -> bool { + **self == EVACT1_A::PWP + } + #[doc = "Checks if the value of the field is `FAULT`"] + #[inline(always)] + pub fn is_fault(&self) -> bool { + **self == EVACT1_A::FAULT + } +} +impl core::ops::Deref for EVACT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT1` writer - Timer/counter Input Event1 Action"] +pub struct EVACT1_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT1_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EVACT1_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Event action disabled"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(EVACT1_A::OFF) + } + #[doc = "Re-trigger counter on event"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(EVACT1_A::RETRIGGER) + } + #[doc = "Direction control"] + #[inline(always)] + pub fn dir(self) -> &'a mut W { + self.variant(EVACT1_A::DIR) + } + #[doc = "Stop counter on event"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(EVACT1_A::STOP) + } + #[doc = "Decrement counter on event"] + #[inline(always)] + pub fn dec(self) -> &'a mut W { + self.variant(EVACT1_A::DEC) + } + #[doc = "Period capture value in CC0 register, pulse width capture value in CC1 register"] + #[inline(always)] + pub fn ppw(self) -> &'a mut W { + self.variant(EVACT1_A::PPW) + } + #[doc = "Period capture value in CC1 register, pulse width capture value in CC0 register"] + #[inline(always)] + pub fn pwp(self) -> &'a mut W { + self.variant(EVACT1_A::PWP) + } + #[doc = "Non-recoverable fault"] + #[inline(always)] + pub fn fault(self) -> &'a mut W { + self.variant(EVACT1_A::FAULT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 3)) | ((value as u32 & 0x07) << 3); + self.w + } +} +#[doc = "Timer/counter Output Event Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CNTSEL_A { + #[doc = "0: An interrupt/event is generated when a new counter cycle starts"] + START = 0, + #[doc = "1: An interrupt/event is generated when a counter cycle ends"] + END = 1, + #[doc = "2: An interrupt/event is generated when a counter cycle ends, except for the first and last cycles"] + BETWEEN = 2, + #[doc = "3: An interrupt/event is generated when a new counter cycle starts or a counter cycle ends"] + BOUNDARY = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CNTSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `CNTSEL` reader - Timer/counter Output Event Mode"] +pub struct CNTSEL_R(crate::FieldReader); +impl CNTSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CNTSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CNTSEL_A { + match self.bits { + 0 => CNTSEL_A::START, + 1 => CNTSEL_A::END, + 2 => CNTSEL_A::BETWEEN, + 3 => CNTSEL_A::BOUNDARY, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `START`"] + #[inline(always)] + pub fn is_start(&self) -> bool { + **self == CNTSEL_A::START + } + #[doc = "Checks if the value of the field is `END`"] + #[inline(always)] + pub fn is_end(&self) -> bool { + **self == CNTSEL_A::END + } + #[doc = "Checks if the value of the field is `BETWEEN`"] + #[inline(always)] + pub fn is_between(&self) -> bool { + **self == CNTSEL_A::BETWEEN + } + #[doc = "Checks if the value of the field is `BOUNDARY`"] + #[inline(always)] + pub fn is_boundary(&self) -> bool { + **self == CNTSEL_A::BOUNDARY + } +} +impl core::ops::Deref for CNTSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CNTSEL` writer - Timer/counter Output Event Mode"] +pub struct CNTSEL_W<'a> { + w: &'a mut W, +} +impl<'a> CNTSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CNTSEL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "An interrupt/event is generated when a new counter cycle starts"] + #[inline(always)] + pub fn start(self) -> &'a mut W { + self.variant(CNTSEL_A::START) + } + #[doc = "An interrupt/event is generated when a counter cycle ends"] + #[inline(always)] + pub fn end(self) -> &'a mut W { + self.variant(CNTSEL_A::END) + } + #[doc = "An interrupt/event is generated when a counter cycle ends, except for the first and last cycles"] + #[inline(always)] + pub fn between(self) -> &'a mut W { + self.variant(CNTSEL_A::BETWEEN) + } + #[doc = "An interrupt/event is generated when a new counter cycle starts or a counter cycle ends"] + #[inline(always)] + pub fn boundary(self) -> &'a mut W { + self.variant(CNTSEL_A::BOUNDARY) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 6)) | ((value as u32 & 0x03) << 6); + self.w + } +} +#[doc = "Field `OVFEO` reader - Overflow/Underflow Output Event Enable"] +pub struct OVFEO_R(crate::FieldReader); +impl OVFEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVFEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVFEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVFEO` writer - Overflow/Underflow Output Event Enable"] +pub struct OVFEO_W<'a> { + w: &'a mut W, +} +impl<'a> OVFEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `TRGEO` reader - Retrigger Output Event Enable"] +pub struct TRGEO_R(crate::FieldReader); +impl TRGEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRGEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRGEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRGEO` writer - Retrigger Output Event Enable"] +pub struct TRGEO_W<'a> { + w: &'a mut W, +} +impl<'a> TRGEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `CNTEO` reader - Timer/counter Output Event Enable"] +pub struct CNTEO_R(crate::FieldReader); +impl CNTEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CNTEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CNTEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CNTEO` writer - Timer/counter Output Event Enable"] +pub struct CNTEO_W<'a> { + w: &'a mut W, +} +impl<'a> CNTEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `TCINV0` reader - Inverted Event 0 Input Enable"] +pub struct TCINV0_R(crate::FieldReader); +impl TCINV0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCINV0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCINV0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCINV0` writer - Inverted Event 0 Input Enable"] +pub struct TCINV0_W<'a> { + w: &'a mut W, +} +impl<'a> TCINV0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `TCINV1` reader - Inverted Event 1 Input Enable"] +pub struct TCINV1_R(crate::FieldReader); +impl TCINV1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCINV1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCINV1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCINV1` writer - Inverted Event 1 Input Enable"] +pub struct TCINV1_W<'a> { + w: &'a mut W, +} +impl<'a> TCINV1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `TCEI0` reader - Timer/counter Event 0 Input Enable"] +pub struct TCEI0_R(crate::FieldReader); +impl TCEI0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCEI0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCEI0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCEI0` writer - Timer/counter Event 0 Input Enable"] +pub struct TCEI0_W<'a> { + w: &'a mut W, +} +impl<'a> TCEI0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `TCEI1` reader - Timer/counter Event 1 Input Enable"] +pub struct TCEI1_R(crate::FieldReader); +impl TCEI1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCEI1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCEI1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCEI1` writer - Timer/counter Event 1 Input Enable"] +pub struct TCEI1_W<'a> { + w: &'a mut W, +} +impl<'a> TCEI1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `MCEI0` reader - Match or Capture Channel 0 Event Input Enable"] +pub struct MCEI0_R(crate::FieldReader); +impl MCEI0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEI0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEI0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEI0` writer - Match or Capture Channel 0 Event Input Enable"] +pub struct MCEI0_W<'a> { + w: &'a mut W, +} +impl<'a> MCEI0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `MCEI1` reader - Match or Capture Channel 1 Event Input Enable"] +pub struct MCEI1_R(crate::FieldReader); +impl MCEI1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEI1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEI1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEI1` writer - Match or Capture Channel 1 Event Input Enable"] +pub struct MCEI1_W<'a> { + w: &'a mut W, +} +impl<'a> MCEI1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `MCEI2` reader - Match or Capture Channel 2 Event Input Enable"] +pub struct MCEI2_R(crate::FieldReader); +impl MCEI2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEI2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEI2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEI2` writer - Match or Capture Channel 2 Event Input Enable"] +pub struct MCEI2_W<'a> { + w: &'a mut W, +} +impl<'a> MCEI2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `MCEI3` reader - Match or Capture Channel 3 Event Input Enable"] +pub struct MCEI3_R(crate::FieldReader); +impl MCEI3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEI3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEI3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEI3` writer - Match or Capture Channel 3 Event Input Enable"] +pub struct MCEI3_W<'a> { + w: &'a mut W, +} +impl<'a> MCEI3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `MCEO0` reader - Match or Capture Channel 0 Event Output Enable"] +pub struct MCEO0_R(crate::FieldReader); +impl MCEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO0` writer - Match or Capture Channel 0 Event Output Enable"] +pub struct MCEO0_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `MCEO1` reader - Match or Capture Channel 1 Event Output Enable"] +pub struct MCEO1_R(crate::FieldReader); +impl MCEO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO1` writer - Match or Capture Channel 1 Event Output Enable"] +pub struct MCEO1_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `MCEO2` reader - Match or Capture Channel 2 Event Output Enable"] +pub struct MCEO2_R(crate::FieldReader); +impl MCEO2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO2` writer - Match or Capture Channel 2 Event Output Enable"] +pub struct MCEO2_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `MCEO3` reader - Match or Capture Channel 3 Event Output Enable"] +pub struct MCEO3_R(crate::FieldReader); +impl MCEO3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO3` writer - Match or Capture Channel 3 Event Output Enable"] +pub struct MCEO3_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Timer/counter Input Event0 Action"] + #[inline(always)] + pub fn evact0(&self) -> EVACT0_R { + EVACT0_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bits 3:5 - Timer/counter Input Event1 Action"] + #[inline(always)] + pub fn evact1(&self) -> EVACT1_R { + EVACT1_R::new(((self.bits >> 3) & 0x07) as u8) + } + #[doc = "Bits 6:7 - Timer/counter Output Event Mode"] + #[inline(always)] + pub fn cntsel(&self) -> CNTSEL_R { + CNTSEL_R::new(((self.bits >> 6) & 0x03) as u8) + } + #[doc = "Bit 8 - Overflow/Underflow Output Event Enable"] + #[inline(always)] + pub fn ovfeo(&self) -> OVFEO_R { + OVFEO_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Retrigger Output Event Enable"] + #[inline(always)] + pub fn trgeo(&self) -> TRGEO_R { + TRGEO_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Timer/counter Output Event Enable"] + #[inline(always)] + pub fn cnteo(&self) -> CNTEO_R { + CNTEO_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 12 - Inverted Event 0 Input Enable"] + #[inline(always)] + pub fn tcinv0(&self) -> TCINV0_R { + TCINV0_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Inverted Event 1 Input Enable"] + #[inline(always)] + pub fn tcinv1(&self) -> TCINV1_R { + TCINV1_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Timer/counter Event 0 Input Enable"] + #[inline(always)] + pub fn tcei0(&self) -> TCEI0_R { + TCEI0_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Timer/counter Event 1 Input Enable"] + #[inline(always)] + pub fn tcei1(&self) -> TCEI1_R { + TCEI1_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Match or Capture Channel 0 Event Input Enable"] + #[inline(always)] + pub fn mcei0(&self) -> MCEI0_R { + MCEI0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Match or Capture Channel 1 Event Input Enable"] + #[inline(always)] + pub fn mcei1(&self) -> MCEI1_R { + MCEI1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Match or Capture Channel 2 Event Input Enable"] + #[inline(always)] + pub fn mcei2(&self) -> MCEI2_R { + MCEI2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Match or Capture Channel 3 Event Input Enable"] + #[inline(always)] + pub fn mcei3(&self) -> MCEI3_R { + MCEI3_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 24 - Match or Capture Channel 0 Event Output Enable"] + #[inline(always)] + pub fn mceo0(&self) -> MCEO0_R { + MCEO0_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Match or Capture Channel 1 Event Output Enable"] + #[inline(always)] + pub fn mceo1(&self) -> MCEO1_R { + MCEO1_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Match or Capture Channel 2 Event Output Enable"] + #[inline(always)] + pub fn mceo2(&self) -> MCEO2_R { + MCEO2_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Match or Capture Channel 3 Event Output Enable"] + #[inline(always)] + pub fn mceo3(&self) -> MCEO3_R { + MCEO3_R::new(((self.bits >> 27) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Timer/counter Input Event0 Action"] + #[inline(always)] + pub fn evact0(&mut self) -> EVACT0_W { + EVACT0_W { w: self } + } + #[doc = "Bits 3:5 - Timer/counter Input Event1 Action"] + #[inline(always)] + pub fn evact1(&mut self) -> EVACT1_W { + EVACT1_W { w: self } + } + #[doc = "Bits 6:7 - Timer/counter Output Event Mode"] + #[inline(always)] + pub fn cntsel(&mut self) -> CNTSEL_W { + CNTSEL_W { w: self } + } + #[doc = "Bit 8 - Overflow/Underflow Output Event Enable"] + #[inline(always)] + pub fn ovfeo(&mut self) -> OVFEO_W { + OVFEO_W { w: self } + } + #[doc = "Bit 9 - Retrigger Output Event Enable"] + #[inline(always)] + pub fn trgeo(&mut self) -> TRGEO_W { + TRGEO_W { w: self } + } + #[doc = "Bit 10 - Timer/counter Output Event Enable"] + #[inline(always)] + pub fn cnteo(&mut self) -> CNTEO_W { + CNTEO_W { w: self } + } + #[doc = "Bit 12 - Inverted Event 0 Input Enable"] + #[inline(always)] + pub fn tcinv0(&mut self) -> TCINV0_W { + TCINV0_W { w: self } + } + #[doc = "Bit 13 - Inverted Event 1 Input Enable"] + #[inline(always)] + pub fn tcinv1(&mut self) -> TCINV1_W { + TCINV1_W { w: self } + } + #[doc = "Bit 14 - Timer/counter Event 0 Input Enable"] + #[inline(always)] + pub fn tcei0(&mut self) -> TCEI0_W { + TCEI0_W { w: self } + } + #[doc = "Bit 15 - Timer/counter Event 1 Input Enable"] + #[inline(always)] + pub fn tcei1(&mut self) -> TCEI1_W { + TCEI1_W { w: self } + } + #[doc = "Bit 16 - Match or Capture Channel 0 Event Input Enable"] + #[inline(always)] + pub fn mcei0(&mut self) -> MCEI0_W { + MCEI0_W { w: self } + } + #[doc = "Bit 17 - Match or Capture Channel 1 Event Input Enable"] + #[inline(always)] + pub fn mcei1(&mut self) -> MCEI1_W { + MCEI1_W { w: self } + } + #[doc = "Bit 18 - Match or Capture Channel 2 Event Input Enable"] + #[inline(always)] + pub fn mcei2(&mut self) -> MCEI2_W { + MCEI2_W { w: self } + } + #[doc = "Bit 19 - Match or Capture Channel 3 Event Input Enable"] + #[inline(always)] + pub fn mcei3(&mut self) -> MCEI3_W { + MCEI3_W { w: self } + } + #[doc = "Bit 24 - Match or Capture Channel 0 Event Output Enable"] + #[inline(always)] + pub fn mceo0(&mut self) -> MCEO0_W { + MCEO0_W { w: self } + } + #[doc = "Bit 25 - Match or Capture Channel 1 Event Output Enable"] + #[inline(always)] + pub fn mceo1(&mut self) -> MCEO1_W { + MCEO1_W { w: self } + } + #[doc = "Bit 26 - Match or Capture Channel 2 Event Output Enable"] + #[inline(always)] + pub fn mceo2(&mut self) -> MCEO2_W { + MCEO2_W { w: self } + } + #[doc = "Bit 27 - Match or Capture Channel 3 Event Output Enable"] + #[inline(always)] + pub fn mceo3(&mut self) -> MCEO3_W { + MCEO3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/tcc0/fctrla.rs b/pac/atsamc21j/src/tcc0/fctrla.rs new file mode 100644 index 000000000000..77c7276fee23 --- /dev/null +++ b/pac/atsamc21j/src/tcc0/fctrla.rs @@ -0,0 +1,940 @@ +#[doc = "Register `FCTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FCTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Fault A Source\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SRC_A { + #[doc = "0: Fault input disabled"] + DISABLE = 0, + #[doc = "1: MCEx (x=0,1) event input"] + ENABLE = 1, + #[doc = "2: Inverted MCEx (x=0,1) event input"] + INVERT = 2, + #[doc = "3: Alternate fault (A or B) state at the end of the previous period"] + ALTFAULT = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SRC_A) -> Self { + variant as _ + } +} +#[doc = "Field `SRC` reader - Fault A Source"] +pub struct SRC_R(crate::FieldReader); +impl SRC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SRC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SRC_A { + match self.bits { + 0 => SRC_A::DISABLE, + 1 => SRC_A::ENABLE, + 2 => SRC_A::INVERT, + 3 => SRC_A::ALTFAULT, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == SRC_A::DISABLE + } + #[doc = "Checks if the value of the field is `ENABLE`"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + **self == SRC_A::ENABLE + } + #[doc = "Checks if the value of the field is `INVERT`"] + #[inline(always)] + pub fn is_invert(&self) -> bool { + **self == SRC_A::INVERT + } + #[doc = "Checks if the value of the field is `ALTFAULT`"] + #[inline(always)] + pub fn is_altfault(&self) -> bool { + **self == SRC_A::ALTFAULT + } +} +impl core::ops::Deref for SRC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SRC` writer - Fault A Source"] +pub struct SRC_W<'a> { + w: &'a mut W, +} +impl<'a> SRC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SRC_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Fault input disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(SRC_A::DISABLE) + } + #[doc = "MCEx (x=0,1) event input"] + #[inline(always)] + pub fn enable(self) -> &'a mut W { + self.variant(SRC_A::ENABLE) + } + #[doc = "Inverted MCEx (x=0,1) event input"] + #[inline(always)] + pub fn invert(self) -> &'a mut W { + self.variant(SRC_A::INVERT) + } + #[doc = "Alternate fault (A or B) state at the end of the previous period"] + #[inline(always)] + pub fn altfault(self) -> &'a mut W { + self.variant(SRC_A::ALTFAULT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u32 & 0x03); + self.w + } +} +#[doc = "Field `KEEP` reader - Fault A Keeper"] +pub struct KEEP_R(crate::FieldReader); +impl KEEP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + KEEP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for KEEP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `KEEP` writer - Fault A Keeper"] +pub struct KEEP_W<'a> { + w: &'a mut W, +} +impl<'a> KEEP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `QUAL` reader - Fault A Qualification"] +pub struct QUAL_R(crate::FieldReader); +impl QUAL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + QUAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for QUAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `QUAL` writer - Fault A Qualification"] +pub struct QUAL_W<'a> { + w: &'a mut W, +} +impl<'a> QUAL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Fault A Blanking Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum BLANK_A { + #[doc = "0: Blanking applied from start of the ramp"] + START = 0, + #[doc = "1: Blanking applied from rising edge of the output waveform"] + RISE = 1, + #[doc = "2: Blanking applied from falling edge of the output waveform"] + FALL = 2, + #[doc = "3: Blanking applied from each toggle of the output waveform"] + BOTH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: BLANK_A) -> Self { + variant as _ + } +} +#[doc = "Field `BLANK` reader - Fault A Blanking Mode"] +pub struct BLANK_R(crate::FieldReader); +impl BLANK_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BLANK_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> BLANK_A { + match self.bits { + 0 => BLANK_A::START, + 1 => BLANK_A::RISE, + 2 => BLANK_A::FALL, + 3 => BLANK_A::BOTH, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `START`"] + #[inline(always)] + pub fn is_start(&self) -> bool { + **self == BLANK_A::START + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == BLANK_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == BLANK_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == BLANK_A::BOTH + } +} +impl core::ops::Deref for BLANK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BLANK` writer - Fault A Blanking Mode"] +pub struct BLANK_W<'a> { + w: &'a mut W, +} +impl<'a> BLANK_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: BLANK_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Blanking applied from start of the ramp"] + #[inline(always)] + pub fn start(self) -> &'a mut W { + self.variant(BLANK_A::START) + } + #[doc = "Blanking applied from rising edge of the output waveform"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(BLANK_A::RISE) + } + #[doc = "Blanking applied from falling edge of the output waveform"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(BLANK_A::FALL) + } + #[doc = "Blanking applied from each toggle of the output waveform"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(BLANK_A::BOTH) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 5)) | ((value as u32 & 0x03) << 5); + self.w + } +} +#[doc = "Field `RESTART` reader - Fault A Restart"] +pub struct RESTART_R(crate::FieldReader); +impl RESTART_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESTART_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESTART_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESTART` writer - Fault A Restart"] +pub struct RESTART_W<'a> { + w: &'a mut W, +} +impl<'a> RESTART_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Fault A Halt Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum HALT_A { + #[doc = "0: Halt action disabled"] + DISABLE = 0, + #[doc = "1: Hardware halt action"] + HW = 1, + #[doc = "2: Software halt action"] + SW = 2, + #[doc = "3: Non-recoverable fault"] + NR = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: HALT_A) -> Self { + variant as _ + } +} +#[doc = "Field `HALT` reader - Fault A Halt Mode"] +pub struct HALT_R(crate::FieldReader); +impl HALT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + HALT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> HALT_A { + match self.bits { + 0 => HALT_A::DISABLE, + 1 => HALT_A::HW, + 2 => HALT_A::SW, + 3 => HALT_A::NR, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == HALT_A::DISABLE + } + #[doc = "Checks if the value of the field is `HW`"] + #[inline(always)] + pub fn is_hw(&self) -> bool { + **self == HALT_A::HW + } + #[doc = "Checks if the value of the field is `SW`"] + #[inline(always)] + pub fn is_sw(&self) -> bool { + **self == HALT_A::SW + } + #[doc = "Checks if the value of the field is `NR`"] + #[inline(always)] + pub fn is_nr(&self) -> bool { + **self == HALT_A::NR + } +} +impl core::ops::Deref for HALT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HALT` writer - Fault A Halt Mode"] +pub struct HALT_W<'a> { + w: &'a mut W, +} +impl<'a> HALT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: HALT_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Halt action disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(HALT_A::DISABLE) + } + #[doc = "Hardware halt action"] + #[inline(always)] + pub fn hw(self) -> &'a mut W { + self.variant(HALT_A::HW) + } + #[doc = "Software halt action"] + #[inline(always)] + pub fn sw(self) -> &'a mut W { + self.variant(HALT_A::SW) + } + #[doc = "Non-recoverable fault"] + #[inline(always)] + pub fn nr(self) -> &'a mut W { + self.variant(HALT_A::NR) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 8)) | ((value as u32 & 0x03) << 8); + self.w + } +} +#[doc = "Fault A Capture Channel\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CHSEL_A { + #[doc = "0: Capture value stored in channel 0"] + CC0 = 0, + #[doc = "1: Capture value stored in channel 1"] + CC1 = 1, + #[doc = "2: Capture value stored in channel 2"] + CC2 = 2, + #[doc = "3: Capture value stored in channel 3"] + CC3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CHSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `CHSEL` reader - Fault A Capture Channel"] +pub struct CHSEL_R(crate::FieldReader); +impl CHSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CHSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CHSEL_A { + match self.bits { + 0 => CHSEL_A::CC0, + 1 => CHSEL_A::CC1, + 2 => CHSEL_A::CC2, + 3 => CHSEL_A::CC3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `CC0`"] + #[inline(always)] + pub fn is_cc0(&self) -> bool { + **self == CHSEL_A::CC0 + } + #[doc = "Checks if the value of the field is `CC1`"] + #[inline(always)] + pub fn is_cc1(&self) -> bool { + **self == CHSEL_A::CC1 + } + #[doc = "Checks if the value of the field is `CC2`"] + #[inline(always)] + pub fn is_cc2(&self) -> bool { + **self == CHSEL_A::CC2 + } + #[doc = "Checks if the value of the field is `CC3`"] + #[inline(always)] + pub fn is_cc3(&self) -> bool { + **self == CHSEL_A::CC3 + } +} +impl core::ops::Deref for CHSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHSEL` writer - Fault A Capture Channel"] +pub struct CHSEL_W<'a> { + w: &'a mut W, +} +impl<'a> CHSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CHSEL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Capture value stored in channel 0"] + #[inline(always)] + pub fn cc0(self) -> &'a mut W { + self.variant(CHSEL_A::CC0) + } + #[doc = "Capture value stored in channel 1"] + #[inline(always)] + pub fn cc1(self) -> &'a mut W { + self.variant(CHSEL_A::CC1) + } + #[doc = "Capture value stored in channel 2"] + #[inline(always)] + pub fn cc2(self) -> &'a mut W { + self.variant(CHSEL_A::CC2) + } + #[doc = "Capture value stored in channel 3"] + #[inline(always)] + pub fn cc3(self) -> &'a mut W { + self.variant(CHSEL_A::CC3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 10)) | ((value as u32 & 0x03) << 10); + self.w + } +} +#[doc = "Fault A Capture Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CAPTURE_A { + #[doc = "0: No capture"] + DISABLE = 0, + #[doc = "1: Capture on fault"] + CAPT = 1, + #[doc = "2: Minimum capture"] + CAPTMIN = 2, + #[doc = "3: Maximum capture"] + CAPTMAX = 3, + #[doc = "4: Minimum local detection"] + LOCMIN = 4, + #[doc = "5: Maximum local detection"] + LOCMAX = 5, + #[doc = "6: Minimum and maximum local detection"] + DERIV0 = 6, + #[doc = "7: Capture with ramp index as MSB value"] + CAPTMARK = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CAPTURE_A) -> Self { + variant as _ + } +} +#[doc = "Field `CAPTURE` reader - Fault A Capture Action"] +pub struct CAPTURE_R(crate::FieldReader); +impl CAPTURE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CAPTURE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CAPTURE_A { + match self.bits { + 0 => CAPTURE_A::DISABLE, + 1 => CAPTURE_A::CAPT, + 2 => CAPTURE_A::CAPTMIN, + 3 => CAPTURE_A::CAPTMAX, + 4 => CAPTURE_A::LOCMIN, + 5 => CAPTURE_A::LOCMAX, + 6 => CAPTURE_A::DERIV0, + 7 => CAPTURE_A::CAPTMARK, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == CAPTURE_A::DISABLE + } + #[doc = "Checks if the value of the field is `CAPT`"] + #[inline(always)] + pub fn is_capt(&self) -> bool { + **self == CAPTURE_A::CAPT + } + #[doc = "Checks if the value of the field is `CAPTMIN`"] + #[inline(always)] + pub fn is_captmin(&self) -> bool { + **self == CAPTURE_A::CAPTMIN + } + #[doc = "Checks if the value of the field is `CAPTMAX`"] + #[inline(always)] + pub fn is_captmax(&self) -> bool { + **self == CAPTURE_A::CAPTMAX + } + #[doc = "Checks if the value of the field is `LOCMIN`"] + #[inline(always)] + pub fn is_locmin(&self) -> bool { + **self == CAPTURE_A::LOCMIN + } + #[doc = "Checks if the value of the field is `LOCMAX`"] + #[inline(always)] + pub fn is_locmax(&self) -> bool { + **self == CAPTURE_A::LOCMAX + } + #[doc = "Checks if the value of the field is `DERIV0`"] + #[inline(always)] + pub fn is_deriv0(&self) -> bool { + **self == CAPTURE_A::DERIV0 + } + #[doc = "Checks if the value of the field is `CAPTMARK`"] + #[inline(always)] + pub fn is_captmark(&self) -> bool { + **self == CAPTURE_A::CAPTMARK + } +} +impl core::ops::Deref for CAPTURE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAPTURE` writer - Fault A Capture Action"] +pub struct CAPTURE_W<'a> { + w: &'a mut W, +} +impl<'a> CAPTURE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CAPTURE_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "No capture"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(CAPTURE_A::DISABLE) + } + #[doc = "Capture on fault"] + #[inline(always)] + pub fn capt(self) -> &'a mut W { + self.variant(CAPTURE_A::CAPT) + } + #[doc = "Minimum capture"] + #[inline(always)] + pub fn captmin(self) -> &'a mut W { + self.variant(CAPTURE_A::CAPTMIN) + } + #[doc = "Maximum capture"] + #[inline(always)] + pub fn captmax(self) -> &'a mut W { + self.variant(CAPTURE_A::CAPTMAX) + } + #[doc = "Minimum local detection"] + #[inline(always)] + pub fn locmin(self) -> &'a mut W { + self.variant(CAPTURE_A::LOCMIN) + } + #[doc = "Maximum local detection"] + #[inline(always)] + pub fn locmax(self) -> &'a mut W { + self.variant(CAPTURE_A::LOCMAX) + } + #[doc = "Minimum and maximum local detection"] + #[inline(always)] + pub fn deriv0(self) -> &'a mut W { + self.variant(CAPTURE_A::DERIV0) + } + #[doc = "Capture with ramp index as MSB value"] + #[inline(always)] + pub fn captmark(self) -> &'a mut W { + self.variant(CAPTURE_A::CAPTMARK) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 12)) | ((value as u32 & 0x07) << 12); + self.w + } +} +#[doc = "Field `BLANKPRESC` reader - Fault A Blanking Prescaler"] +pub struct BLANKPRESC_R(crate::FieldReader); +impl BLANKPRESC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BLANKPRESC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BLANKPRESC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BLANKPRESC` writer - Fault A Blanking Prescaler"] +pub struct BLANKPRESC_W<'a> { + w: &'a mut W, +} +impl<'a> BLANKPRESC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `BLANKVAL` reader - Fault A Blanking Time"] +pub struct BLANKVAL_R(crate::FieldReader); +impl BLANKVAL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BLANKVAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BLANKVAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BLANKVAL` writer - Fault A Blanking Time"] +pub struct BLANKVAL_W<'a> { + w: &'a mut W, +} +impl<'a> BLANKVAL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +#[doc = "Field `FILTERVAL` reader - Fault A Filter Value"] +pub struct FILTERVAL_R(crate::FieldReader); +impl FILTERVAL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FILTERVAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTERVAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTERVAL` writer - Fault A Filter Value"] +pub struct FILTERVAL_W<'a> { + w: &'a mut W, +} +impl<'a> FILTERVAL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Fault A Source"] + #[inline(always)] + pub fn src(&self) -> SRC_R { + SRC_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bit 3 - Fault A Keeper"] + #[inline(always)] + pub fn keep(&self) -> KEEP_R { + KEEP_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Fault A Qualification"] + #[inline(always)] + pub fn qual(&self) -> QUAL_R { + QUAL_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bits 5:6 - Fault A Blanking Mode"] + #[inline(always)] + pub fn blank(&self) -> BLANK_R { + BLANK_R::new(((self.bits >> 5) & 0x03) as u8) + } + #[doc = "Bit 7 - Fault A Restart"] + #[inline(always)] + pub fn restart(&self) -> RESTART_R { + RESTART_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:9 - Fault A Halt Mode"] + #[inline(always)] + pub fn halt(&self) -> HALT_R { + HALT_R::new(((self.bits >> 8) & 0x03) as u8) + } + #[doc = "Bits 10:11 - Fault A Capture Channel"] + #[inline(always)] + pub fn chsel(&self) -> CHSEL_R { + CHSEL_R::new(((self.bits >> 10) & 0x03) as u8) + } + #[doc = "Bits 12:14 - Fault A Capture Action"] + #[inline(always)] + pub fn capture(&self) -> CAPTURE_R { + CAPTURE_R::new(((self.bits >> 12) & 0x07) as u8) + } + #[doc = "Bit 15 - Fault A Blanking Prescaler"] + #[inline(always)] + pub fn blankpresc(&self) -> BLANKPRESC_R { + BLANKPRESC_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:23 - Fault A Blanking Time"] + #[inline(always)] + pub fn blankval(&self) -> BLANKVAL_R { + BLANKVAL_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:27 - Fault A Filter Value"] + #[inline(always)] + pub fn filterval(&self) -> FILTERVAL_R { + FILTERVAL_R::new(((self.bits >> 24) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Fault A Source"] + #[inline(always)] + pub fn src(&mut self) -> SRC_W { + SRC_W { w: self } + } + #[doc = "Bit 3 - Fault A Keeper"] + #[inline(always)] + pub fn keep(&mut self) -> KEEP_W { + KEEP_W { w: self } + } + #[doc = "Bit 4 - Fault A Qualification"] + #[inline(always)] + pub fn qual(&mut self) -> QUAL_W { + QUAL_W { w: self } + } + #[doc = "Bits 5:6 - Fault A Blanking Mode"] + #[inline(always)] + pub fn blank(&mut self) -> BLANK_W { + BLANK_W { w: self } + } + #[doc = "Bit 7 - Fault A Restart"] + #[inline(always)] + pub fn restart(&mut self) -> RESTART_W { + RESTART_W { w: self } + } + #[doc = "Bits 8:9 - Fault A Halt Mode"] + #[inline(always)] + pub fn halt(&mut self) -> HALT_W { + HALT_W { w: self } + } + #[doc = "Bits 10:11 - Fault A Capture Channel"] + #[inline(always)] + pub fn chsel(&mut self) -> CHSEL_W { + CHSEL_W { w: self } + } + #[doc = "Bits 12:14 - Fault A Capture Action"] + #[inline(always)] + pub fn capture(&mut self) -> CAPTURE_W { + CAPTURE_W { w: self } + } + #[doc = "Bit 15 - Fault A Blanking Prescaler"] + #[inline(always)] + pub fn blankpresc(&mut self) -> BLANKPRESC_W { + BLANKPRESC_W { w: self } + } + #[doc = "Bits 16:23 - Fault A Blanking Time"] + #[inline(always)] + pub fn blankval(&mut self) -> BLANKVAL_W { + BLANKVAL_W { w: self } + } + #[doc = "Bits 24:27 - Fault A Filter Value"] + #[inline(always)] + pub fn filterval(&mut self) -> FILTERVAL_W { + FILTERVAL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Recoverable Fault A Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fctrla](index.html) module"] +pub struct FCTRLA_SPEC; +impl crate::RegisterSpec for FCTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [fctrla::R](R) reader structure"] +impl crate::Readable for FCTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [fctrla::W](W) writer structure"] +impl crate::Writable for FCTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets FCTRLA to value 0"] +impl crate::Resettable for FCTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/tcc0/fctrlb.rs b/pac/atsamc21j/src/tcc0/fctrlb.rs new file mode 100644 index 000000000000..4c1dfd1af93d --- /dev/null +++ b/pac/atsamc21j/src/tcc0/fctrlb.rs @@ -0,0 +1,940 @@ +#[doc = "Register `FCTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FCTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Fault B Source\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SRC_A { + #[doc = "0: Fault input disabled"] + DISABLE = 0, + #[doc = "1: MCEx (x=0,1) event input"] + ENABLE = 1, + #[doc = "2: Inverted MCEx (x=0,1) event input"] + INVERT = 2, + #[doc = "3: Alternate fault (A or B) state at the end of the previous period"] + ALTFAULT = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SRC_A) -> Self { + variant as _ + } +} +#[doc = "Field `SRC` reader - Fault B Source"] +pub struct SRC_R(crate::FieldReader); +impl SRC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SRC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SRC_A { + match self.bits { + 0 => SRC_A::DISABLE, + 1 => SRC_A::ENABLE, + 2 => SRC_A::INVERT, + 3 => SRC_A::ALTFAULT, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == SRC_A::DISABLE + } + #[doc = "Checks if the value of the field is `ENABLE`"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + **self == SRC_A::ENABLE + } + #[doc = "Checks if the value of the field is `INVERT`"] + #[inline(always)] + pub fn is_invert(&self) -> bool { + **self == SRC_A::INVERT + } + #[doc = "Checks if the value of the field is `ALTFAULT`"] + #[inline(always)] + pub fn is_altfault(&self) -> bool { + **self == SRC_A::ALTFAULT + } +} +impl core::ops::Deref for SRC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SRC` writer - Fault B Source"] +pub struct SRC_W<'a> { + w: &'a mut W, +} +impl<'a> SRC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SRC_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Fault input disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(SRC_A::DISABLE) + } + #[doc = "MCEx (x=0,1) event input"] + #[inline(always)] + pub fn enable(self) -> &'a mut W { + self.variant(SRC_A::ENABLE) + } + #[doc = "Inverted MCEx (x=0,1) event input"] + #[inline(always)] + pub fn invert(self) -> &'a mut W { + self.variant(SRC_A::INVERT) + } + #[doc = "Alternate fault (A or B) state at the end of the previous period"] + #[inline(always)] + pub fn altfault(self) -> &'a mut W { + self.variant(SRC_A::ALTFAULT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u32 & 0x03); + self.w + } +} +#[doc = "Field `KEEP` reader - Fault B Keeper"] +pub struct KEEP_R(crate::FieldReader); +impl KEEP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + KEEP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for KEEP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `KEEP` writer - Fault B Keeper"] +pub struct KEEP_W<'a> { + w: &'a mut W, +} +impl<'a> KEEP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `QUAL` reader - Fault B Qualification"] +pub struct QUAL_R(crate::FieldReader); +impl QUAL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + QUAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for QUAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `QUAL` writer - Fault B Qualification"] +pub struct QUAL_W<'a> { + w: &'a mut W, +} +impl<'a> QUAL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Fault B Blanking Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum BLANK_A { + #[doc = "0: Blanking applied from start of the ramp"] + START = 0, + #[doc = "1: Blanking applied from rising edge of the output waveform"] + RISE = 1, + #[doc = "2: Blanking applied from falling edge of the output waveform"] + FALL = 2, + #[doc = "3: Blanking applied from each toggle of the output waveform"] + BOTH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: BLANK_A) -> Self { + variant as _ + } +} +#[doc = "Field `BLANK` reader - Fault B Blanking Mode"] +pub struct BLANK_R(crate::FieldReader); +impl BLANK_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BLANK_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> BLANK_A { + match self.bits { + 0 => BLANK_A::START, + 1 => BLANK_A::RISE, + 2 => BLANK_A::FALL, + 3 => BLANK_A::BOTH, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `START`"] + #[inline(always)] + pub fn is_start(&self) -> bool { + **self == BLANK_A::START + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == BLANK_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == BLANK_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == BLANK_A::BOTH + } +} +impl core::ops::Deref for BLANK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BLANK` writer - Fault B Blanking Mode"] +pub struct BLANK_W<'a> { + w: &'a mut W, +} +impl<'a> BLANK_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: BLANK_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Blanking applied from start of the ramp"] + #[inline(always)] + pub fn start(self) -> &'a mut W { + self.variant(BLANK_A::START) + } + #[doc = "Blanking applied from rising edge of the output waveform"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(BLANK_A::RISE) + } + #[doc = "Blanking applied from falling edge of the output waveform"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(BLANK_A::FALL) + } + #[doc = "Blanking applied from each toggle of the output waveform"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(BLANK_A::BOTH) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 5)) | ((value as u32 & 0x03) << 5); + self.w + } +} +#[doc = "Field `RESTART` reader - Fault B Restart"] +pub struct RESTART_R(crate::FieldReader); +impl RESTART_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESTART_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESTART_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESTART` writer - Fault B Restart"] +pub struct RESTART_W<'a> { + w: &'a mut W, +} +impl<'a> RESTART_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Fault B Halt Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum HALT_A { + #[doc = "0: Halt action disabled"] + DISABLE = 0, + #[doc = "1: Hardware halt action"] + HW = 1, + #[doc = "2: Software halt action"] + SW = 2, + #[doc = "3: Non-recoverable fault"] + NR = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: HALT_A) -> Self { + variant as _ + } +} +#[doc = "Field `HALT` reader - Fault B Halt Mode"] +pub struct HALT_R(crate::FieldReader); +impl HALT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + HALT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> HALT_A { + match self.bits { + 0 => HALT_A::DISABLE, + 1 => HALT_A::HW, + 2 => HALT_A::SW, + 3 => HALT_A::NR, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == HALT_A::DISABLE + } + #[doc = "Checks if the value of the field is `HW`"] + #[inline(always)] + pub fn is_hw(&self) -> bool { + **self == HALT_A::HW + } + #[doc = "Checks if the value of the field is `SW`"] + #[inline(always)] + pub fn is_sw(&self) -> bool { + **self == HALT_A::SW + } + #[doc = "Checks if the value of the field is `NR`"] + #[inline(always)] + pub fn is_nr(&self) -> bool { + **self == HALT_A::NR + } +} +impl core::ops::Deref for HALT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HALT` writer - Fault B Halt Mode"] +pub struct HALT_W<'a> { + w: &'a mut W, +} +impl<'a> HALT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: HALT_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Halt action disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(HALT_A::DISABLE) + } + #[doc = "Hardware halt action"] + #[inline(always)] + pub fn hw(self) -> &'a mut W { + self.variant(HALT_A::HW) + } + #[doc = "Software halt action"] + #[inline(always)] + pub fn sw(self) -> &'a mut W { + self.variant(HALT_A::SW) + } + #[doc = "Non-recoverable fault"] + #[inline(always)] + pub fn nr(self) -> &'a mut W { + self.variant(HALT_A::NR) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 8)) | ((value as u32 & 0x03) << 8); + self.w + } +} +#[doc = "Fault B Capture Channel\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CHSEL_A { + #[doc = "0: Capture value stored in channel 0"] + CC0 = 0, + #[doc = "1: Capture value stored in channel 1"] + CC1 = 1, + #[doc = "2: Capture value stored in channel 2"] + CC2 = 2, + #[doc = "3: Capture value stored in channel 3"] + CC3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CHSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `CHSEL` reader - Fault B Capture Channel"] +pub struct CHSEL_R(crate::FieldReader); +impl CHSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CHSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CHSEL_A { + match self.bits { + 0 => CHSEL_A::CC0, + 1 => CHSEL_A::CC1, + 2 => CHSEL_A::CC2, + 3 => CHSEL_A::CC3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `CC0`"] + #[inline(always)] + pub fn is_cc0(&self) -> bool { + **self == CHSEL_A::CC0 + } + #[doc = "Checks if the value of the field is `CC1`"] + #[inline(always)] + pub fn is_cc1(&self) -> bool { + **self == CHSEL_A::CC1 + } + #[doc = "Checks if the value of the field is `CC2`"] + #[inline(always)] + pub fn is_cc2(&self) -> bool { + **self == CHSEL_A::CC2 + } + #[doc = "Checks if the value of the field is `CC3`"] + #[inline(always)] + pub fn is_cc3(&self) -> bool { + **self == CHSEL_A::CC3 + } +} +impl core::ops::Deref for CHSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHSEL` writer - Fault B Capture Channel"] +pub struct CHSEL_W<'a> { + w: &'a mut W, +} +impl<'a> CHSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CHSEL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Capture value stored in channel 0"] + #[inline(always)] + pub fn cc0(self) -> &'a mut W { + self.variant(CHSEL_A::CC0) + } + #[doc = "Capture value stored in channel 1"] + #[inline(always)] + pub fn cc1(self) -> &'a mut W { + self.variant(CHSEL_A::CC1) + } + #[doc = "Capture value stored in channel 2"] + #[inline(always)] + pub fn cc2(self) -> &'a mut W { + self.variant(CHSEL_A::CC2) + } + #[doc = "Capture value stored in channel 3"] + #[inline(always)] + pub fn cc3(self) -> &'a mut W { + self.variant(CHSEL_A::CC3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 10)) | ((value as u32 & 0x03) << 10); + self.w + } +} +#[doc = "Fault B Capture Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CAPTURE_A { + #[doc = "0: No capture"] + DISABLE = 0, + #[doc = "1: Capture on fault"] + CAPT = 1, + #[doc = "2: Minimum capture"] + CAPTMIN = 2, + #[doc = "3: Maximum capture"] + CAPTMAX = 3, + #[doc = "4: Minimum local detection"] + LOCMIN = 4, + #[doc = "5: Maximum local detection"] + LOCMAX = 5, + #[doc = "6: Minimum and maximum local detection"] + DERIV0 = 6, + #[doc = "7: Capture with ramp index as MSB value"] + CAPTMARK = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CAPTURE_A) -> Self { + variant as _ + } +} +#[doc = "Field `CAPTURE` reader - Fault B Capture Action"] +pub struct CAPTURE_R(crate::FieldReader); +impl CAPTURE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CAPTURE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CAPTURE_A { + match self.bits { + 0 => CAPTURE_A::DISABLE, + 1 => CAPTURE_A::CAPT, + 2 => CAPTURE_A::CAPTMIN, + 3 => CAPTURE_A::CAPTMAX, + 4 => CAPTURE_A::LOCMIN, + 5 => CAPTURE_A::LOCMAX, + 6 => CAPTURE_A::DERIV0, + 7 => CAPTURE_A::CAPTMARK, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == CAPTURE_A::DISABLE + } + #[doc = "Checks if the value of the field is `CAPT`"] + #[inline(always)] + pub fn is_capt(&self) -> bool { + **self == CAPTURE_A::CAPT + } + #[doc = "Checks if the value of the field is `CAPTMIN`"] + #[inline(always)] + pub fn is_captmin(&self) -> bool { + **self == CAPTURE_A::CAPTMIN + } + #[doc = "Checks if the value of the field is `CAPTMAX`"] + #[inline(always)] + pub fn is_captmax(&self) -> bool { + **self == CAPTURE_A::CAPTMAX + } + #[doc = "Checks if the value of the field is `LOCMIN`"] + #[inline(always)] + pub fn is_locmin(&self) -> bool { + **self == CAPTURE_A::LOCMIN + } + #[doc = "Checks if the value of the field is `LOCMAX`"] + #[inline(always)] + pub fn is_locmax(&self) -> bool { + **self == CAPTURE_A::LOCMAX + } + #[doc = "Checks if the value of the field is `DERIV0`"] + #[inline(always)] + pub fn is_deriv0(&self) -> bool { + **self == CAPTURE_A::DERIV0 + } + #[doc = "Checks if the value of the field is `CAPTMARK`"] + #[inline(always)] + pub fn is_captmark(&self) -> bool { + **self == CAPTURE_A::CAPTMARK + } +} +impl core::ops::Deref for CAPTURE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAPTURE` writer - Fault B Capture Action"] +pub struct CAPTURE_W<'a> { + w: &'a mut W, +} +impl<'a> CAPTURE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CAPTURE_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "No capture"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(CAPTURE_A::DISABLE) + } + #[doc = "Capture on fault"] + #[inline(always)] + pub fn capt(self) -> &'a mut W { + self.variant(CAPTURE_A::CAPT) + } + #[doc = "Minimum capture"] + #[inline(always)] + pub fn captmin(self) -> &'a mut W { + self.variant(CAPTURE_A::CAPTMIN) + } + #[doc = "Maximum capture"] + #[inline(always)] + pub fn captmax(self) -> &'a mut W { + self.variant(CAPTURE_A::CAPTMAX) + } + #[doc = "Minimum local detection"] + #[inline(always)] + pub fn locmin(self) -> &'a mut W { + self.variant(CAPTURE_A::LOCMIN) + } + #[doc = "Maximum local detection"] + #[inline(always)] + pub fn locmax(self) -> &'a mut W { + self.variant(CAPTURE_A::LOCMAX) + } + #[doc = "Minimum and maximum local detection"] + #[inline(always)] + pub fn deriv0(self) -> &'a mut W { + self.variant(CAPTURE_A::DERIV0) + } + #[doc = "Capture with ramp index as MSB value"] + #[inline(always)] + pub fn captmark(self) -> &'a mut W { + self.variant(CAPTURE_A::CAPTMARK) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 12)) | ((value as u32 & 0x07) << 12); + self.w + } +} +#[doc = "Field `BLANKPRESC` reader - Fault B Blanking Prescaler"] +pub struct BLANKPRESC_R(crate::FieldReader); +impl BLANKPRESC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BLANKPRESC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BLANKPRESC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BLANKPRESC` writer - Fault B Blanking Prescaler"] +pub struct BLANKPRESC_W<'a> { + w: &'a mut W, +} +impl<'a> BLANKPRESC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `BLANKVAL` reader - Fault B Blanking Time"] +pub struct BLANKVAL_R(crate::FieldReader); +impl BLANKVAL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BLANKVAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BLANKVAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BLANKVAL` writer - Fault B Blanking Time"] +pub struct BLANKVAL_W<'a> { + w: &'a mut W, +} +impl<'a> BLANKVAL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +#[doc = "Field `FILTERVAL` reader - Fault B Filter Value"] +pub struct FILTERVAL_R(crate::FieldReader); +impl FILTERVAL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FILTERVAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTERVAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTERVAL` writer - Fault B Filter Value"] +pub struct FILTERVAL_W<'a> { + w: &'a mut W, +} +impl<'a> FILTERVAL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Fault B Source"] + #[inline(always)] + pub fn src(&self) -> SRC_R { + SRC_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bit 3 - Fault B Keeper"] + #[inline(always)] + pub fn keep(&self) -> KEEP_R { + KEEP_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Fault B Qualification"] + #[inline(always)] + pub fn qual(&self) -> QUAL_R { + QUAL_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bits 5:6 - Fault B Blanking Mode"] + #[inline(always)] + pub fn blank(&self) -> BLANK_R { + BLANK_R::new(((self.bits >> 5) & 0x03) as u8) + } + #[doc = "Bit 7 - Fault B Restart"] + #[inline(always)] + pub fn restart(&self) -> RESTART_R { + RESTART_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:9 - Fault B Halt Mode"] + #[inline(always)] + pub fn halt(&self) -> HALT_R { + HALT_R::new(((self.bits >> 8) & 0x03) as u8) + } + #[doc = "Bits 10:11 - Fault B Capture Channel"] + #[inline(always)] + pub fn chsel(&self) -> CHSEL_R { + CHSEL_R::new(((self.bits >> 10) & 0x03) as u8) + } + #[doc = "Bits 12:14 - Fault B Capture Action"] + #[inline(always)] + pub fn capture(&self) -> CAPTURE_R { + CAPTURE_R::new(((self.bits >> 12) & 0x07) as u8) + } + #[doc = "Bit 15 - Fault B Blanking Prescaler"] + #[inline(always)] + pub fn blankpresc(&self) -> BLANKPRESC_R { + BLANKPRESC_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:23 - Fault B Blanking Time"] + #[inline(always)] + pub fn blankval(&self) -> BLANKVAL_R { + BLANKVAL_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:27 - Fault B Filter Value"] + #[inline(always)] + pub fn filterval(&self) -> FILTERVAL_R { + FILTERVAL_R::new(((self.bits >> 24) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Fault B Source"] + #[inline(always)] + pub fn src(&mut self) -> SRC_W { + SRC_W { w: self } + } + #[doc = "Bit 3 - Fault B Keeper"] + #[inline(always)] + pub fn keep(&mut self) -> KEEP_W { + KEEP_W { w: self } + } + #[doc = "Bit 4 - Fault B Qualification"] + #[inline(always)] + pub fn qual(&mut self) -> QUAL_W { + QUAL_W { w: self } + } + #[doc = "Bits 5:6 - Fault B Blanking Mode"] + #[inline(always)] + pub fn blank(&mut self) -> BLANK_W { + BLANK_W { w: self } + } + #[doc = "Bit 7 - Fault B Restart"] + #[inline(always)] + pub fn restart(&mut self) -> RESTART_W { + RESTART_W { w: self } + } + #[doc = "Bits 8:9 - Fault B Halt Mode"] + #[inline(always)] + pub fn halt(&mut self) -> HALT_W { + HALT_W { w: self } + } + #[doc = "Bits 10:11 - Fault B Capture Channel"] + #[inline(always)] + pub fn chsel(&mut self) -> CHSEL_W { + CHSEL_W { w: self } + } + #[doc = "Bits 12:14 - Fault B Capture Action"] + #[inline(always)] + pub fn capture(&mut self) -> CAPTURE_W { + CAPTURE_W { w: self } + } + #[doc = "Bit 15 - Fault B Blanking Prescaler"] + #[inline(always)] + pub fn blankpresc(&mut self) -> BLANKPRESC_W { + BLANKPRESC_W { w: self } + } + #[doc = "Bits 16:23 - Fault B Blanking Time"] + #[inline(always)] + pub fn blankval(&mut self) -> BLANKVAL_W { + BLANKVAL_W { w: self } + } + #[doc = "Bits 24:27 - Fault B Filter Value"] + #[inline(always)] + pub fn filterval(&mut self) -> FILTERVAL_W { + FILTERVAL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Recoverable Fault B Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fctrlb](index.html) module"] +pub struct FCTRLB_SPEC; +impl crate::RegisterSpec for FCTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [fctrlb::R](R) reader structure"] +impl crate::Readable for FCTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [fctrlb::W](W) writer structure"] +impl crate::Writable for FCTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets FCTRLB to value 0"] +impl crate::Resettable for FCTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/tcc0/intenclr.rs b/pac/atsamc21j/src/tcc0/intenclr.rs new file mode 100644 index 000000000000..a227a8405a3c --- /dev/null +++ b/pac/atsamc21j/src/tcc0/intenclr.rs @@ -0,0 +1,724 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `TRG` reader - Retrigger Interrupt Enable"] +pub struct TRG_R(crate::FieldReader); +impl TRG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRG` writer - Retrigger Interrupt Enable"] +pub struct TRG_W<'a> { + w: &'a mut W, +} +impl<'a> TRG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CNT` reader - Counter Interrupt Enable"] +pub struct CNT_R(crate::FieldReader); +impl CNT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CNT` writer - Counter Interrupt Enable"] +pub struct CNT_W<'a> { + w: &'a mut W, +} +impl<'a> CNT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `ERR` reader - Error Interrupt Enable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - Error Interrupt Enable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `UFS` reader - Non-Recoverable Update Fault Interrupt Enable"] +pub struct UFS_R(crate::FieldReader); +impl UFS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UFS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for UFS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `UFS` writer - Non-Recoverable Update Fault Interrupt Enable"] +pub struct UFS_W<'a> { + w: &'a mut W, +} +impl<'a> UFS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `DFS` reader - Non-Recoverable Debug Fault Interrupt Enable"] +pub struct DFS_R(crate::FieldReader); +impl DFS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFS` writer - Non-Recoverable Debug Fault Interrupt Enable"] +pub struct DFS_W<'a> { + w: &'a mut W, +} +impl<'a> DFS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `FAULTA` reader - Recoverable Fault A Interrupt Enable"] +pub struct FAULTA_R(crate::FieldReader); +impl FAULTA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTA` writer - Recoverable Fault A Interrupt Enable"] +pub struct FAULTA_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `FAULTB` reader - Recoverable Fault B Interrupt Enable"] +pub struct FAULTB_R(crate::FieldReader); +impl FAULTB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTB` writer - Recoverable Fault B Interrupt Enable"] +pub struct FAULTB_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `FAULT0` reader - Non-Recoverable Fault 0 Interrupt Enable"] +pub struct FAULT0_R(crate::FieldReader); +impl FAULT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT0` writer - Non-Recoverable Fault 0 Interrupt Enable"] +pub struct FAULT0_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `FAULT1` reader - Non-Recoverable Fault 1 Interrupt Enable"] +pub struct FAULT1_R(crate::FieldReader); +impl FAULT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT1` writer - Non-Recoverable Fault 1 Interrupt Enable"] +pub struct FAULT1_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `MC0` reader - Match or Capture Channel 0 Interrupt Enable"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - Match or Capture Channel 0 Interrupt Enable"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `MC1` reader - Match or Capture Channel 1 Interrupt Enable"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - Match or Capture Channel 1 Interrupt Enable"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `MC2` reader - Match or Capture Channel 2 Interrupt Enable"] +pub struct MC2_R(crate::FieldReader); +impl MC2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC2` writer - Match or Capture Channel 2 Interrupt Enable"] +pub struct MC2_W<'a> { + w: &'a mut W, +} +impl<'a> MC2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `MC3` reader - Match or Capture Channel 3 Interrupt Enable"] +pub struct MC3_R(crate::FieldReader); +impl MC3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC3` writer - Match or Capture Channel 3 Interrupt Enable"] +pub struct MC3_W<'a> { + w: &'a mut W, +} +impl<'a> MC3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +impl R { + #[doc = "Bit 0 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Retrigger Interrupt Enable"] + #[inline(always)] + pub fn trg(&self) -> TRG_R { + TRG_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Counter Interrupt Enable"] + #[inline(always)] + pub fn cnt(&self) -> CNT_R { + CNT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Error Interrupt Enable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 10 - Non-Recoverable Update Fault Interrupt Enable"] + #[inline(always)] + pub fn ufs(&self) -> UFS_R { + UFS_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Non-Recoverable Debug Fault Interrupt Enable"] + #[inline(always)] + pub fn dfs(&self) -> DFS_R { + DFS_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Recoverable Fault A Interrupt Enable"] + #[inline(always)] + pub fn faulta(&self) -> FAULTA_R { + FAULTA_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Recoverable Fault B Interrupt Enable"] + #[inline(always)] + pub fn faultb(&self) -> FAULTB_R { + FAULTB_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Non-Recoverable Fault 0 Interrupt Enable"] + #[inline(always)] + pub fn fault0(&self) -> FAULT0_R { + FAULT0_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Non-Recoverable Fault 1 Interrupt Enable"] + #[inline(always)] + pub fn fault1(&self) -> FAULT1_R { + FAULT1_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Match or Capture Channel 0 Interrupt Enable"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Match or Capture Channel 1 Interrupt Enable"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Match or Capture Channel 2 Interrupt Enable"] + #[inline(always)] + pub fn mc2(&self) -> MC2_R { + MC2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Match or Capture Channel 3 Interrupt Enable"] + #[inline(always)] + pub fn mc3(&self) -> MC3_R { + MC3_R::new(((self.bits >> 19) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - Retrigger Interrupt Enable"] + #[inline(always)] + pub fn trg(&mut self) -> TRG_W { + TRG_W { w: self } + } + #[doc = "Bit 2 - Counter Interrupt Enable"] + #[inline(always)] + pub fn cnt(&mut self) -> CNT_W { + CNT_W { w: self } + } + #[doc = "Bit 3 - Error Interrupt Enable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 10 - Non-Recoverable Update Fault Interrupt Enable"] + #[inline(always)] + pub fn ufs(&mut self) -> UFS_W { + UFS_W { w: self } + } + #[doc = "Bit 11 - Non-Recoverable Debug Fault Interrupt Enable"] + #[inline(always)] + pub fn dfs(&mut self) -> DFS_W { + DFS_W { w: self } + } + #[doc = "Bit 12 - Recoverable Fault A Interrupt Enable"] + #[inline(always)] + pub fn faulta(&mut self) -> FAULTA_W { + FAULTA_W { w: self } + } + #[doc = "Bit 13 - Recoverable Fault B Interrupt Enable"] + #[inline(always)] + pub fn faultb(&mut self) -> FAULTB_W { + FAULTB_W { w: self } + } + #[doc = "Bit 14 - Non-Recoverable Fault 0 Interrupt Enable"] + #[inline(always)] + pub fn fault0(&mut self) -> FAULT0_W { + FAULT0_W { w: self } + } + #[doc = "Bit 15 - Non-Recoverable Fault 1 Interrupt Enable"] + #[inline(always)] + pub fn fault1(&mut self) -> FAULT1_W { + FAULT1_W { w: self } + } + #[doc = "Bit 16 - Match or Capture Channel 0 Interrupt Enable"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 17 - Match or Capture Channel 1 Interrupt Enable"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Bit 18 - Match or Capture Channel 2 Interrupt Enable"] + #[inline(always)] + pub fn mc2(&mut self) -> MC2_W { + MC2_W { w: self } + } + #[doc = "Bit 19 - Match or Capture Channel 3 Interrupt Enable"] + #[inline(always)] + pub fn mc3(&mut self) -> MC3_W { + MC3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/tcc0/intenset.rs b/pac/atsamc21j/src/tcc0/intenset.rs new file mode 100644 index 000000000000..0125a220bd02 --- /dev/null +++ b/pac/atsamc21j/src/tcc0/intenset.rs @@ -0,0 +1,724 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `TRG` reader - Retrigger Interrupt Enable"] +pub struct TRG_R(crate::FieldReader); +impl TRG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRG` writer - Retrigger Interrupt Enable"] +pub struct TRG_W<'a> { + w: &'a mut W, +} +impl<'a> TRG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CNT` reader - Counter Interrupt Enable"] +pub struct CNT_R(crate::FieldReader); +impl CNT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CNT` writer - Counter Interrupt Enable"] +pub struct CNT_W<'a> { + w: &'a mut W, +} +impl<'a> CNT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `ERR` reader - Error Interrupt Enable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - Error Interrupt Enable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `UFS` reader - Non-Recoverable Update Fault Interrupt Enable"] +pub struct UFS_R(crate::FieldReader); +impl UFS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UFS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for UFS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `UFS` writer - Non-Recoverable Update Fault Interrupt Enable"] +pub struct UFS_W<'a> { + w: &'a mut W, +} +impl<'a> UFS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `DFS` reader - Non-Recoverable Debug Fault Interrupt Enable"] +pub struct DFS_R(crate::FieldReader); +impl DFS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFS` writer - Non-Recoverable Debug Fault Interrupt Enable"] +pub struct DFS_W<'a> { + w: &'a mut W, +} +impl<'a> DFS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `FAULTA` reader - Recoverable Fault A Interrupt Enable"] +pub struct FAULTA_R(crate::FieldReader); +impl FAULTA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTA` writer - Recoverable Fault A Interrupt Enable"] +pub struct FAULTA_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `FAULTB` reader - Recoverable Fault B Interrupt Enable"] +pub struct FAULTB_R(crate::FieldReader); +impl FAULTB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTB` writer - Recoverable Fault B Interrupt Enable"] +pub struct FAULTB_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `FAULT0` reader - Non-Recoverable Fault 0 Interrupt Enable"] +pub struct FAULT0_R(crate::FieldReader); +impl FAULT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT0` writer - Non-Recoverable Fault 0 Interrupt Enable"] +pub struct FAULT0_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `FAULT1` reader - Non-Recoverable Fault 1 Interrupt Enable"] +pub struct FAULT1_R(crate::FieldReader); +impl FAULT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT1` writer - Non-Recoverable Fault 1 Interrupt Enable"] +pub struct FAULT1_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `MC0` reader - Match or Capture Channel 0 Interrupt Enable"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - Match or Capture Channel 0 Interrupt Enable"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `MC1` reader - Match or Capture Channel 1 Interrupt Enable"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - Match or Capture Channel 1 Interrupt Enable"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `MC2` reader - Match or Capture Channel 2 Interrupt Enable"] +pub struct MC2_R(crate::FieldReader); +impl MC2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC2` writer - Match or Capture Channel 2 Interrupt Enable"] +pub struct MC2_W<'a> { + w: &'a mut W, +} +impl<'a> MC2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `MC3` reader - Match or Capture Channel 3 Interrupt Enable"] +pub struct MC3_R(crate::FieldReader); +impl MC3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC3` writer - Match or Capture Channel 3 Interrupt Enable"] +pub struct MC3_W<'a> { + w: &'a mut W, +} +impl<'a> MC3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +impl R { + #[doc = "Bit 0 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Retrigger Interrupt Enable"] + #[inline(always)] + pub fn trg(&self) -> TRG_R { + TRG_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Counter Interrupt Enable"] + #[inline(always)] + pub fn cnt(&self) -> CNT_R { + CNT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Error Interrupt Enable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 10 - Non-Recoverable Update Fault Interrupt Enable"] + #[inline(always)] + pub fn ufs(&self) -> UFS_R { + UFS_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Non-Recoverable Debug Fault Interrupt Enable"] + #[inline(always)] + pub fn dfs(&self) -> DFS_R { + DFS_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Recoverable Fault A Interrupt Enable"] + #[inline(always)] + pub fn faulta(&self) -> FAULTA_R { + FAULTA_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Recoverable Fault B Interrupt Enable"] + #[inline(always)] + pub fn faultb(&self) -> FAULTB_R { + FAULTB_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Non-Recoverable Fault 0 Interrupt Enable"] + #[inline(always)] + pub fn fault0(&self) -> FAULT0_R { + FAULT0_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Non-Recoverable Fault 1 Interrupt Enable"] + #[inline(always)] + pub fn fault1(&self) -> FAULT1_R { + FAULT1_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Match or Capture Channel 0 Interrupt Enable"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Match or Capture Channel 1 Interrupt Enable"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Match or Capture Channel 2 Interrupt Enable"] + #[inline(always)] + pub fn mc2(&self) -> MC2_R { + MC2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Match or Capture Channel 3 Interrupt Enable"] + #[inline(always)] + pub fn mc3(&self) -> MC3_R { + MC3_R::new(((self.bits >> 19) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - Retrigger Interrupt Enable"] + #[inline(always)] + pub fn trg(&mut self) -> TRG_W { + TRG_W { w: self } + } + #[doc = "Bit 2 - Counter Interrupt Enable"] + #[inline(always)] + pub fn cnt(&mut self) -> CNT_W { + CNT_W { w: self } + } + #[doc = "Bit 3 - Error Interrupt Enable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 10 - Non-Recoverable Update Fault Interrupt Enable"] + #[inline(always)] + pub fn ufs(&mut self) -> UFS_W { + UFS_W { w: self } + } + #[doc = "Bit 11 - Non-Recoverable Debug Fault Interrupt Enable"] + #[inline(always)] + pub fn dfs(&mut self) -> DFS_W { + DFS_W { w: self } + } + #[doc = "Bit 12 - Recoverable Fault A Interrupt Enable"] + #[inline(always)] + pub fn faulta(&mut self) -> FAULTA_W { + FAULTA_W { w: self } + } + #[doc = "Bit 13 - Recoverable Fault B Interrupt Enable"] + #[inline(always)] + pub fn faultb(&mut self) -> FAULTB_W { + FAULTB_W { w: self } + } + #[doc = "Bit 14 - Non-Recoverable Fault 0 Interrupt Enable"] + #[inline(always)] + pub fn fault0(&mut self) -> FAULT0_W { + FAULT0_W { w: self } + } + #[doc = "Bit 15 - Non-Recoverable Fault 1 Interrupt Enable"] + #[inline(always)] + pub fn fault1(&mut self) -> FAULT1_W { + FAULT1_W { w: self } + } + #[doc = "Bit 16 - Match or Capture Channel 0 Interrupt Enable"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 17 - Match or Capture Channel 1 Interrupt Enable"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Bit 18 - Match or Capture Channel 2 Interrupt Enable"] + #[inline(always)] + pub fn mc2(&mut self) -> MC2_W { + MC2_W { w: self } + } + #[doc = "Bit 19 - Match or Capture Channel 3 Interrupt Enable"] + #[inline(always)] + pub fn mc3(&mut self) -> MC3_W { + MC3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/tcc0/intflag.rs b/pac/atsamc21j/src/tcc0/intflag.rs new file mode 100644 index 000000000000..b2d5088f4087 --- /dev/null +++ b/pac/atsamc21j/src/tcc0/intflag.rs @@ -0,0 +1,724 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - Overflow"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `TRG` reader - Retrigger"] +pub struct TRG_R(crate::FieldReader); +impl TRG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRG` writer - Retrigger"] +pub struct TRG_W<'a> { + w: &'a mut W, +} +impl<'a> TRG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CNT` reader - Counter"] +pub struct CNT_R(crate::FieldReader); +impl CNT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CNT` writer - Counter"] +pub struct CNT_W<'a> { + w: &'a mut W, +} +impl<'a> CNT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `ERR` reader - Error"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - Error"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `UFS` reader - Non-Recoverable Update Fault"] +pub struct UFS_R(crate::FieldReader); +impl UFS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UFS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for UFS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `UFS` writer - Non-Recoverable Update Fault"] +pub struct UFS_W<'a> { + w: &'a mut W, +} +impl<'a> UFS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `DFS` reader - Non-Recoverable Debug Fault"] +pub struct DFS_R(crate::FieldReader); +impl DFS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFS` writer - Non-Recoverable Debug Fault"] +pub struct DFS_W<'a> { + w: &'a mut W, +} +impl<'a> DFS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `FAULTA` reader - Recoverable Fault A"] +pub struct FAULTA_R(crate::FieldReader); +impl FAULTA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTA` writer - Recoverable Fault A"] +pub struct FAULTA_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `FAULTB` reader - Recoverable Fault B"] +pub struct FAULTB_R(crate::FieldReader); +impl FAULTB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTB` writer - Recoverable Fault B"] +pub struct FAULTB_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `FAULT0` reader - Non-Recoverable Fault 0"] +pub struct FAULT0_R(crate::FieldReader); +impl FAULT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT0` writer - Non-Recoverable Fault 0"] +pub struct FAULT0_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `FAULT1` reader - Non-Recoverable Fault 1"] +pub struct FAULT1_R(crate::FieldReader); +impl FAULT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT1` writer - Non-Recoverable Fault 1"] +pub struct FAULT1_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `MC0` reader - Match or Capture 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - Match or Capture 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `MC1` reader - Match or Capture 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - Match or Capture 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `MC2` reader - Match or Capture 2"] +pub struct MC2_R(crate::FieldReader); +impl MC2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC2` writer - Match or Capture 2"] +pub struct MC2_W<'a> { + w: &'a mut W, +} +impl<'a> MC2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `MC3` reader - Match or Capture 3"] +pub struct MC3_R(crate::FieldReader); +impl MC3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC3` writer - Match or Capture 3"] +pub struct MC3_W<'a> { + w: &'a mut W, +} +impl<'a> MC3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +impl R { + #[doc = "Bit 0 - Overflow"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Retrigger"] + #[inline(always)] + pub fn trg(&self) -> TRG_R { + TRG_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Counter"] + #[inline(always)] + pub fn cnt(&self) -> CNT_R { + CNT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Error"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 10 - Non-Recoverable Update Fault"] + #[inline(always)] + pub fn ufs(&self) -> UFS_R { + UFS_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Non-Recoverable Debug Fault"] + #[inline(always)] + pub fn dfs(&self) -> DFS_R { + DFS_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Recoverable Fault A"] + #[inline(always)] + pub fn faulta(&self) -> FAULTA_R { + FAULTA_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Recoverable Fault B"] + #[inline(always)] + pub fn faultb(&self) -> FAULTB_R { + FAULTB_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Non-Recoverable Fault 0"] + #[inline(always)] + pub fn fault0(&self) -> FAULT0_R { + FAULT0_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Non-Recoverable Fault 1"] + #[inline(always)] + pub fn fault1(&self) -> FAULT1_R { + FAULT1_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Match or Capture 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Match or Capture 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Match or Capture 2"] + #[inline(always)] + pub fn mc2(&self) -> MC2_R { + MC2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Match or Capture 3"] + #[inline(always)] + pub fn mc3(&self) -> MC3_R { + MC3_R::new(((self.bits >> 19) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Overflow"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - Retrigger"] + #[inline(always)] + pub fn trg(&mut self) -> TRG_W { + TRG_W { w: self } + } + #[doc = "Bit 2 - Counter"] + #[inline(always)] + pub fn cnt(&mut self) -> CNT_W { + CNT_W { w: self } + } + #[doc = "Bit 3 - Error"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 10 - Non-Recoverable Update Fault"] + #[inline(always)] + pub fn ufs(&mut self) -> UFS_W { + UFS_W { w: self } + } + #[doc = "Bit 11 - Non-Recoverable Debug Fault"] + #[inline(always)] + pub fn dfs(&mut self) -> DFS_W { + DFS_W { w: self } + } + #[doc = "Bit 12 - Recoverable Fault A"] + #[inline(always)] + pub fn faulta(&mut self) -> FAULTA_W { + FAULTA_W { w: self } + } + #[doc = "Bit 13 - Recoverable Fault B"] + #[inline(always)] + pub fn faultb(&mut self) -> FAULTB_W { + FAULTB_W { w: self } + } + #[doc = "Bit 14 - Non-Recoverable Fault 0"] + #[inline(always)] + pub fn fault0(&mut self) -> FAULT0_W { + FAULT0_W { w: self } + } + #[doc = "Bit 15 - Non-Recoverable Fault 1"] + #[inline(always)] + pub fn fault1(&mut self) -> FAULT1_W { + FAULT1_W { w: self } + } + #[doc = "Bit 16 - Match or Capture 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 17 - Match or Capture 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Bit 18 - Match or Capture 2"] + #[inline(always)] + pub fn mc2(&mut self) -> MC2_W { + MC2_W { w: self } + } + #[doc = "Bit 19 - Match or Capture 3"] + #[inline(always)] + pub fn mc3(&mut self) -> MC3_W { + MC3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/tcc0/patt.rs b/pac/atsamc21j/src/tcc0/patt.rs new file mode 100644 index 000000000000..ea458642b182 --- /dev/null +++ b/pac/atsamc21j/src/tcc0/patt.rs @@ -0,0 +1,818 @@ +#[doc = "Register `PATT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PATT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PGE0` reader - Pattern Generator 0 Output Enable"] +pub struct PGE0_R(crate::FieldReader); +impl PGE0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGE0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGE0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGE0` writer - Pattern Generator 0 Output Enable"] +pub struct PGE0_W<'a> { + w: &'a mut W, +} +impl<'a> PGE0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PGE1` reader - Pattern Generator 1 Output Enable"] +pub struct PGE1_R(crate::FieldReader); +impl PGE1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGE1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGE1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGE1` writer - Pattern Generator 1 Output Enable"] +pub struct PGE1_W<'a> { + w: &'a mut W, +} +impl<'a> PGE1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PGE2` reader - Pattern Generator 2 Output Enable"] +pub struct PGE2_R(crate::FieldReader); +impl PGE2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGE2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGE2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGE2` writer - Pattern Generator 2 Output Enable"] +pub struct PGE2_W<'a> { + w: &'a mut W, +} +impl<'a> PGE2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PGE3` reader - Pattern Generator 3 Output Enable"] +pub struct PGE3_R(crate::FieldReader); +impl PGE3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGE3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGE3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGE3` writer - Pattern Generator 3 Output Enable"] +pub struct PGE3_W<'a> { + w: &'a mut W, +} +impl<'a> PGE3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PGE4` reader - Pattern Generator 4 Output Enable"] +pub struct PGE4_R(crate::FieldReader); +impl PGE4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGE4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGE4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGE4` writer - Pattern Generator 4 Output Enable"] +pub struct PGE4_W<'a> { + w: &'a mut W, +} +impl<'a> PGE4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PGE5` reader - Pattern Generator 5 Output Enable"] +pub struct PGE5_R(crate::FieldReader); +impl PGE5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGE5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGE5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGE5` writer - Pattern Generator 5 Output Enable"] +pub struct PGE5_W<'a> { + w: &'a mut W, +} +impl<'a> PGE5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PGE6` reader - Pattern Generator 6 Output Enable"] +pub struct PGE6_R(crate::FieldReader); +impl PGE6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGE6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGE6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGE6` writer - Pattern Generator 6 Output Enable"] +pub struct PGE6_W<'a> { + w: &'a mut W, +} +impl<'a> PGE6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PGE7` reader - Pattern Generator 7 Output Enable"] +pub struct PGE7_R(crate::FieldReader); +impl PGE7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGE7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGE7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGE7` writer - Pattern Generator 7 Output Enable"] +pub struct PGE7_W<'a> { + w: &'a mut W, +} +impl<'a> PGE7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `PGV0` reader - Pattern Generator 0 Output Value"] +pub struct PGV0_R(crate::FieldReader); +impl PGV0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGV0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGV0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGV0` writer - Pattern Generator 0 Output Value"] +pub struct PGV0_W<'a> { + w: &'a mut W, +} +impl<'a> PGV0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `PGV1` reader - Pattern Generator 1 Output Value"] +pub struct PGV1_R(crate::FieldReader); +impl PGV1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGV1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGV1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGV1` writer - Pattern Generator 1 Output Value"] +pub struct PGV1_W<'a> { + w: &'a mut W, +} +impl<'a> PGV1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `PGV2` reader - Pattern Generator 2 Output Value"] +pub struct PGV2_R(crate::FieldReader); +impl PGV2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGV2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGV2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGV2` writer - Pattern Generator 2 Output Value"] +pub struct PGV2_W<'a> { + w: &'a mut W, +} +impl<'a> PGV2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u16 & 0x01) << 10); + self.w + } +} +#[doc = "Field `PGV3` reader - Pattern Generator 3 Output Value"] +pub struct PGV3_R(crate::FieldReader); +impl PGV3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGV3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGV3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGV3` writer - Pattern Generator 3 Output Value"] +pub struct PGV3_W<'a> { + w: &'a mut W, +} +impl<'a> PGV3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u16 & 0x01) << 11); + self.w + } +} +#[doc = "Field `PGV4` reader - Pattern Generator 4 Output Value"] +pub struct PGV4_R(crate::FieldReader); +impl PGV4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGV4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGV4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGV4` writer - Pattern Generator 4 Output Value"] +pub struct PGV4_W<'a> { + w: &'a mut W, +} +impl<'a> PGV4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u16 & 0x01) << 12); + self.w + } +} +#[doc = "Field `PGV5` reader - Pattern Generator 5 Output Value"] +pub struct PGV5_R(crate::FieldReader); +impl PGV5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGV5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGV5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGV5` writer - Pattern Generator 5 Output Value"] +pub struct PGV5_W<'a> { + w: &'a mut W, +} +impl<'a> PGV5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u16 & 0x01) << 13); + self.w + } +} +#[doc = "Field `PGV6` reader - Pattern Generator 6 Output Value"] +pub struct PGV6_R(crate::FieldReader); +impl PGV6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGV6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGV6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGV6` writer - Pattern Generator 6 Output Value"] +pub struct PGV6_W<'a> { + w: &'a mut W, +} +impl<'a> PGV6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u16 & 0x01) << 14); + self.w + } +} +#[doc = "Field `PGV7` reader - Pattern Generator 7 Output Value"] +pub struct PGV7_R(crate::FieldReader); +impl PGV7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGV7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGV7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGV7` writer - Pattern Generator 7 Output Value"] +pub struct PGV7_W<'a> { + w: &'a mut W, +} +impl<'a> PGV7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Pattern Generator 0 Output Enable"] + #[inline(always)] + pub fn pge0(&self) -> PGE0_R { + PGE0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Pattern Generator 1 Output Enable"] + #[inline(always)] + pub fn pge1(&self) -> PGE1_R { + PGE1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Pattern Generator 2 Output Enable"] + #[inline(always)] + pub fn pge2(&self) -> PGE2_R { + PGE2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Pattern Generator 3 Output Enable"] + #[inline(always)] + pub fn pge3(&self) -> PGE3_R { + PGE3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Pattern Generator 4 Output Enable"] + #[inline(always)] + pub fn pge4(&self) -> PGE4_R { + PGE4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Pattern Generator 5 Output Enable"] + #[inline(always)] + pub fn pge5(&self) -> PGE5_R { + PGE5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Pattern Generator 6 Output Enable"] + #[inline(always)] + pub fn pge6(&self) -> PGE6_R { + PGE6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Pattern Generator 7 Output Enable"] + #[inline(always)] + pub fn pge7(&self) -> PGE7_R { + PGE7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Pattern Generator 0 Output Value"] + #[inline(always)] + pub fn pgv0(&self) -> PGV0_R { + PGV0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Pattern Generator 1 Output Value"] + #[inline(always)] + pub fn pgv1(&self) -> PGV1_R { + PGV1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Pattern Generator 2 Output Value"] + #[inline(always)] + pub fn pgv2(&self) -> PGV2_R { + PGV2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Pattern Generator 3 Output Value"] + #[inline(always)] + pub fn pgv3(&self) -> PGV3_R { + PGV3_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Pattern Generator 4 Output Value"] + #[inline(always)] + pub fn pgv4(&self) -> PGV4_R { + PGV4_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Pattern Generator 5 Output Value"] + #[inline(always)] + pub fn pgv5(&self) -> PGV5_R { + PGV5_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Pattern Generator 6 Output Value"] + #[inline(always)] + pub fn pgv6(&self) -> PGV6_R { + PGV6_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Pattern Generator 7 Output Value"] + #[inline(always)] + pub fn pgv7(&self) -> PGV7_R { + PGV7_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pattern Generator 0 Output Enable"] + #[inline(always)] + pub fn pge0(&mut self) -> PGE0_W { + PGE0_W { w: self } + } + #[doc = "Bit 1 - Pattern Generator 1 Output Enable"] + #[inline(always)] + pub fn pge1(&mut self) -> PGE1_W { + PGE1_W { w: self } + } + #[doc = "Bit 2 - Pattern Generator 2 Output Enable"] + #[inline(always)] + pub fn pge2(&mut self) -> PGE2_W { + PGE2_W { w: self } + } + #[doc = "Bit 3 - Pattern Generator 3 Output Enable"] + #[inline(always)] + pub fn pge3(&mut self) -> PGE3_W { + PGE3_W { w: self } + } + #[doc = "Bit 4 - Pattern Generator 4 Output Enable"] + #[inline(always)] + pub fn pge4(&mut self) -> PGE4_W { + PGE4_W { w: self } + } + #[doc = "Bit 5 - Pattern Generator 5 Output Enable"] + #[inline(always)] + pub fn pge5(&mut self) -> PGE5_W { + PGE5_W { w: self } + } + #[doc = "Bit 6 - Pattern Generator 6 Output Enable"] + #[inline(always)] + pub fn pge6(&mut self) -> PGE6_W { + PGE6_W { w: self } + } + #[doc = "Bit 7 - Pattern Generator 7 Output Enable"] + #[inline(always)] + pub fn pge7(&mut self) -> PGE7_W { + PGE7_W { w: self } + } + #[doc = "Bit 8 - Pattern Generator 0 Output Value"] + #[inline(always)] + pub fn pgv0(&mut self) -> PGV0_W { + PGV0_W { w: self } + } + #[doc = "Bit 9 - Pattern Generator 1 Output Value"] + #[inline(always)] + pub fn pgv1(&mut self) -> PGV1_W { + PGV1_W { w: self } + } + #[doc = "Bit 10 - Pattern Generator 2 Output Value"] + #[inline(always)] + pub fn pgv2(&mut self) -> PGV2_W { + PGV2_W { w: self } + } + #[doc = "Bit 11 - Pattern Generator 3 Output Value"] + #[inline(always)] + pub fn pgv3(&mut self) -> PGV3_W { + PGV3_W { w: self } + } + #[doc = "Bit 12 - Pattern Generator 4 Output Value"] + #[inline(always)] + pub fn pgv4(&mut self) -> PGV4_W { + PGV4_W { w: self } + } + #[doc = "Bit 13 - Pattern Generator 5 Output Value"] + #[inline(always)] + pub fn pgv5(&mut self) -> PGV5_W { + PGV5_W { w: self } + } + #[doc = "Bit 14 - Pattern Generator 6 Output Value"] + #[inline(always)] + pub fn pgv6(&mut self) -> PGV6_W { + PGV6_W { w: self } + } + #[doc = "Bit 15 - Pattern Generator 7 Output Value"] + #[inline(always)] + pub fn pgv7(&mut self) -> PGV7_W { + PGV7_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Pattern\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [patt](index.html) module"] +pub struct PATT_SPEC; +impl crate::RegisterSpec for PATT_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [patt::R](R) reader structure"] +impl crate::Readable for PATT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [patt::W](W) writer structure"] +impl crate::Writable for PATT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PATT to value 0"] +impl crate::Resettable for PATT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/tcc0/pattbuf.rs b/pac/atsamc21j/src/tcc0/pattbuf.rs new file mode 100644 index 000000000000..c9375e27645c --- /dev/null +++ b/pac/atsamc21j/src/tcc0/pattbuf.rs @@ -0,0 +1,818 @@ +#[doc = "Register `PATTBUF` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PATTBUF` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PGEB0` reader - Pattern Generator 0 Output Enable Buffer"] +pub struct PGEB0_R(crate::FieldReader); +impl PGEB0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGEB0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGEB0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGEB0` writer - Pattern Generator 0 Output Enable Buffer"] +pub struct PGEB0_W<'a> { + w: &'a mut W, +} +impl<'a> PGEB0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PGEB1` reader - Pattern Generator 1 Output Enable Buffer"] +pub struct PGEB1_R(crate::FieldReader); +impl PGEB1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGEB1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGEB1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGEB1` writer - Pattern Generator 1 Output Enable Buffer"] +pub struct PGEB1_W<'a> { + w: &'a mut W, +} +impl<'a> PGEB1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PGEB2` reader - Pattern Generator 2 Output Enable Buffer"] +pub struct PGEB2_R(crate::FieldReader); +impl PGEB2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGEB2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGEB2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGEB2` writer - Pattern Generator 2 Output Enable Buffer"] +pub struct PGEB2_W<'a> { + w: &'a mut W, +} +impl<'a> PGEB2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PGEB3` reader - Pattern Generator 3 Output Enable Buffer"] +pub struct PGEB3_R(crate::FieldReader); +impl PGEB3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGEB3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGEB3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGEB3` writer - Pattern Generator 3 Output Enable Buffer"] +pub struct PGEB3_W<'a> { + w: &'a mut W, +} +impl<'a> PGEB3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PGEB4` reader - Pattern Generator 4 Output Enable Buffer"] +pub struct PGEB4_R(crate::FieldReader); +impl PGEB4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGEB4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGEB4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGEB4` writer - Pattern Generator 4 Output Enable Buffer"] +pub struct PGEB4_W<'a> { + w: &'a mut W, +} +impl<'a> PGEB4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PGEB5` reader - Pattern Generator 5 Output Enable Buffer"] +pub struct PGEB5_R(crate::FieldReader); +impl PGEB5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGEB5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGEB5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGEB5` writer - Pattern Generator 5 Output Enable Buffer"] +pub struct PGEB5_W<'a> { + w: &'a mut W, +} +impl<'a> PGEB5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PGEB6` reader - Pattern Generator 6 Output Enable Buffer"] +pub struct PGEB6_R(crate::FieldReader); +impl PGEB6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGEB6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGEB6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGEB6` writer - Pattern Generator 6 Output Enable Buffer"] +pub struct PGEB6_W<'a> { + w: &'a mut W, +} +impl<'a> PGEB6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PGEB7` reader - Pattern Generator 7 Output Enable Buffer"] +pub struct PGEB7_R(crate::FieldReader); +impl PGEB7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGEB7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGEB7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGEB7` writer - Pattern Generator 7 Output Enable Buffer"] +pub struct PGEB7_W<'a> { + w: &'a mut W, +} +impl<'a> PGEB7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `PGVB0` reader - Pattern Generator 0 Output Enable"] +pub struct PGVB0_R(crate::FieldReader); +impl PGVB0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGVB0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGVB0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGVB0` writer - Pattern Generator 0 Output Enable"] +pub struct PGVB0_W<'a> { + w: &'a mut W, +} +impl<'a> PGVB0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `PGVB1` reader - Pattern Generator 1 Output Enable"] +pub struct PGVB1_R(crate::FieldReader); +impl PGVB1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGVB1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGVB1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGVB1` writer - Pattern Generator 1 Output Enable"] +pub struct PGVB1_W<'a> { + w: &'a mut W, +} +impl<'a> PGVB1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `PGVB2` reader - Pattern Generator 2 Output Enable"] +pub struct PGVB2_R(crate::FieldReader); +impl PGVB2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGVB2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGVB2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGVB2` writer - Pattern Generator 2 Output Enable"] +pub struct PGVB2_W<'a> { + w: &'a mut W, +} +impl<'a> PGVB2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u16 & 0x01) << 10); + self.w + } +} +#[doc = "Field `PGVB3` reader - Pattern Generator 3 Output Enable"] +pub struct PGVB3_R(crate::FieldReader); +impl PGVB3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGVB3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGVB3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGVB3` writer - Pattern Generator 3 Output Enable"] +pub struct PGVB3_W<'a> { + w: &'a mut W, +} +impl<'a> PGVB3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u16 & 0x01) << 11); + self.w + } +} +#[doc = "Field `PGVB4` reader - Pattern Generator 4 Output Enable"] +pub struct PGVB4_R(crate::FieldReader); +impl PGVB4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGVB4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGVB4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGVB4` writer - Pattern Generator 4 Output Enable"] +pub struct PGVB4_W<'a> { + w: &'a mut W, +} +impl<'a> PGVB4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u16 & 0x01) << 12); + self.w + } +} +#[doc = "Field `PGVB5` reader - Pattern Generator 5 Output Enable"] +pub struct PGVB5_R(crate::FieldReader); +impl PGVB5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGVB5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGVB5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGVB5` writer - Pattern Generator 5 Output Enable"] +pub struct PGVB5_W<'a> { + w: &'a mut W, +} +impl<'a> PGVB5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u16 & 0x01) << 13); + self.w + } +} +#[doc = "Field `PGVB6` reader - Pattern Generator 6 Output Enable"] +pub struct PGVB6_R(crate::FieldReader); +impl PGVB6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGVB6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGVB6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGVB6` writer - Pattern Generator 6 Output Enable"] +pub struct PGVB6_W<'a> { + w: &'a mut W, +} +impl<'a> PGVB6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u16 & 0x01) << 14); + self.w + } +} +#[doc = "Field `PGVB7` reader - Pattern Generator 7 Output Enable"] +pub struct PGVB7_R(crate::FieldReader); +impl PGVB7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGVB7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGVB7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGVB7` writer - Pattern Generator 7 Output Enable"] +pub struct PGVB7_W<'a> { + w: &'a mut W, +} +impl<'a> PGVB7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Pattern Generator 0 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb0(&self) -> PGEB0_R { + PGEB0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Pattern Generator 1 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb1(&self) -> PGEB1_R { + PGEB1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Pattern Generator 2 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb2(&self) -> PGEB2_R { + PGEB2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Pattern Generator 3 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb3(&self) -> PGEB3_R { + PGEB3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Pattern Generator 4 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb4(&self) -> PGEB4_R { + PGEB4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Pattern Generator 5 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb5(&self) -> PGEB5_R { + PGEB5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Pattern Generator 6 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb6(&self) -> PGEB6_R { + PGEB6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Pattern Generator 7 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb7(&self) -> PGEB7_R { + PGEB7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Pattern Generator 0 Output Enable"] + #[inline(always)] + pub fn pgvb0(&self) -> PGVB0_R { + PGVB0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Pattern Generator 1 Output Enable"] + #[inline(always)] + pub fn pgvb1(&self) -> PGVB1_R { + PGVB1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Pattern Generator 2 Output Enable"] + #[inline(always)] + pub fn pgvb2(&self) -> PGVB2_R { + PGVB2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Pattern Generator 3 Output Enable"] + #[inline(always)] + pub fn pgvb3(&self) -> PGVB3_R { + PGVB3_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Pattern Generator 4 Output Enable"] + #[inline(always)] + pub fn pgvb4(&self) -> PGVB4_R { + PGVB4_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Pattern Generator 5 Output Enable"] + #[inline(always)] + pub fn pgvb5(&self) -> PGVB5_R { + PGVB5_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Pattern Generator 6 Output Enable"] + #[inline(always)] + pub fn pgvb6(&self) -> PGVB6_R { + PGVB6_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Pattern Generator 7 Output Enable"] + #[inline(always)] + pub fn pgvb7(&self) -> PGVB7_R { + PGVB7_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pattern Generator 0 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb0(&mut self) -> PGEB0_W { + PGEB0_W { w: self } + } + #[doc = "Bit 1 - Pattern Generator 1 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb1(&mut self) -> PGEB1_W { + PGEB1_W { w: self } + } + #[doc = "Bit 2 - Pattern Generator 2 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb2(&mut self) -> PGEB2_W { + PGEB2_W { w: self } + } + #[doc = "Bit 3 - Pattern Generator 3 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb3(&mut self) -> PGEB3_W { + PGEB3_W { w: self } + } + #[doc = "Bit 4 - Pattern Generator 4 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb4(&mut self) -> PGEB4_W { + PGEB4_W { w: self } + } + #[doc = "Bit 5 - Pattern Generator 5 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb5(&mut self) -> PGEB5_W { + PGEB5_W { w: self } + } + #[doc = "Bit 6 - Pattern Generator 6 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb6(&mut self) -> PGEB6_W { + PGEB6_W { w: self } + } + #[doc = "Bit 7 - Pattern Generator 7 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb7(&mut self) -> PGEB7_W { + PGEB7_W { w: self } + } + #[doc = "Bit 8 - Pattern Generator 0 Output Enable"] + #[inline(always)] + pub fn pgvb0(&mut self) -> PGVB0_W { + PGVB0_W { w: self } + } + #[doc = "Bit 9 - Pattern Generator 1 Output Enable"] + #[inline(always)] + pub fn pgvb1(&mut self) -> PGVB1_W { + PGVB1_W { w: self } + } + #[doc = "Bit 10 - Pattern Generator 2 Output Enable"] + #[inline(always)] + pub fn pgvb2(&mut self) -> PGVB2_W { + PGVB2_W { w: self } + } + #[doc = "Bit 11 - Pattern Generator 3 Output Enable"] + #[inline(always)] + pub fn pgvb3(&mut self) -> PGVB3_W { + PGVB3_W { w: self } + } + #[doc = "Bit 12 - Pattern Generator 4 Output Enable"] + #[inline(always)] + pub fn pgvb4(&mut self) -> PGVB4_W { + PGVB4_W { w: self } + } + #[doc = "Bit 13 - Pattern Generator 5 Output Enable"] + #[inline(always)] + pub fn pgvb5(&mut self) -> PGVB5_W { + PGVB5_W { w: self } + } + #[doc = "Bit 14 - Pattern Generator 6 Output Enable"] + #[inline(always)] + pub fn pgvb6(&mut self) -> PGVB6_W { + PGVB6_W { w: self } + } + #[doc = "Bit 15 - Pattern Generator 7 Output Enable"] + #[inline(always)] + pub fn pgvb7(&mut self) -> PGVB7_W { + PGVB7_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Pattern Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pattbuf](index.html) module"] +pub struct PATTBUF_SPEC; +impl crate::RegisterSpec for PATTBUF_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [pattbuf::R](R) reader structure"] +impl crate::Readable for PATTBUF_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [pattbuf::W](W) writer structure"] +impl crate::Writable for PATTBUF_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PATTBUF to value 0"] +impl crate::Resettable for PATTBUF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/tcc0/per.rs b/pac/atsamc21j/src/tcc0/per.rs new file mode 100644 index 000000000000..9d8618631650 --- /dev/null +++ b/pac/atsamc21j/src/tcc0/per.rs @@ -0,0 +1,103 @@ +#[doc = "Register `PER` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PER` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER` reader - Period Value"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` writer - Period Value"] +pub struct PER_W<'a> { + w: &'a mut W, +} +impl<'a> PER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Period Value"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Period Value"] + #[inline(always)] + pub fn per(&mut self) -> PER_W { + PER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [per](index.html) module"] +pub struct PER_SPEC; +impl crate::RegisterSpec for PER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [per::R](R) reader structure"] +impl crate::Readable for PER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [per::W](W) writer structure"] +impl crate::Writable for PER_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PER to value 0xffff_ffff"] +impl crate::Resettable for PER_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pac/atsamc21j/src/tcc0/per_dith4_mode.rs b/pac/atsamc21j/src/tcc0/per_dith4_mode.rs new file mode 100644 index 000000000000..2f600552db84 --- /dev/null +++ b/pac/atsamc21j/src/tcc0/per_dith4_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PER_DITH4_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PER_DITH4_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHER` reader - Dithering Cycle Number"] +pub struct DITHER_R(crate::FieldReader); +impl DITHER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHER` writer - Dithering Cycle Number"] +pub struct DITHER_W<'a> { + w: &'a mut W, +} +impl<'a> DITHER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Field `PER` reader - Period Value"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` writer - Period Value"] +pub struct PER_W<'a> { + w: &'a mut W, +} +impl<'a> PER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x000f_ffff << 4)) | ((value as u32 & 0x000f_ffff) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&self) -> DITHER_R { + DITHER_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:23 - Period Value"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(((self.bits >> 4) & 0x000f_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:3 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&mut self) -> DITHER_W { + DITHER_W { w: self } + } + #[doc = "Bits 4:23 - Period Value"] + #[inline(always)] + pub fn per(&mut self) -> PER_W { + PER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [per_dith4_mode](index.html) module"] +pub struct PER_DITH4_MODE_SPEC; +impl crate::RegisterSpec for PER_DITH4_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [per_dith4_mode::R](R) reader structure"] +impl crate::Readable for PER_DITH4_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [per_dith4_mode::W](W) writer structure"] +impl crate::Writable for PER_DITH4_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PER_DITH4_MODE to value 0xffff_ffff"] +impl crate::Resettable for PER_DITH4_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pac/atsamc21j/src/tcc0/per_dith5_mode.rs b/pac/atsamc21j/src/tcc0/per_dith5_mode.rs new file mode 100644 index 000000000000..1906582e4c95 --- /dev/null +++ b/pac/atsamc21j/src/tcc0/per_dith5_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PER_DITH5_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PER_DITH5_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHER` reader - Dithering Cycle Number"] +pub struct DITHER_R(crate::FieldReader); +impl DITHER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHER` writer - Dithering Cycle Number"] +pub struct DITHER_W<'a> { + w: &'a mut W, +} +impl<'a> DITHER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f); + self.w + } +} +#[doc = "Field `PER` reader - Period Value"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` writer - Period Value"] +pub struct PER_W<'a> { + w: &'a mut W, +} +impl<'a> PER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0007_ffff << 5)) | ((value as u32 & 0x0007_ffff) << 5); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&self) -> DITHER_R { + DITHER_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:23 - Period Value"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(((self.bits >> 5) & 0x0007_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:4 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&mut self) -> DITHER_W { + DITHER_W { w: self } + } + #[doc = "Bits 5:23 - Period Value"] + #[inline(always)] + pub fn per(&mut self) -> PER_W { + PER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [per_dith5_mode](index.html) module"] +pub struct PER_DITH5_MODE_SPEC; +impl crate::RegisterSpec for PER_DITH5_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [per_dith5_mode::R](R) reader structure"] +impl crate::Readable for PER_DITH5_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [per_dith5_mode::W](W) writer structure"] +impl crate::Writable for PER_DITH5_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PER_DITH5_MODE to value 0xffff_ffff"] +impl crate::Resettable for PER_DITH5_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pac/atsamc21j/src/tcc0/per_dith6_mode.rs b/pac/atsamc21j/src/tcc0/per_dith6_mode.rs new file mode 100644 index 000000000000..67880e220a9c --- /dev/null +++ b/pac/atsamc21j/src/tcc0/per_dith6_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PER_DITH6_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PER_DITH6_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHER` reader - Dithering Cycle Number"] +pub struct DITHER_R(crate::FieldReader); +impl DITHER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHER` writer - Dithering Cycle Number"] +pub struct DITHER_W<'a> { + w: &'a mut W, +} +impl<'a> DITHER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +#[doc = "Field `PER` reader - Period Value"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` writer - Period Value"] +pub struct PER_W<'a> { + w: &'a mut W, +} +impl<'a> PER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0003_ffff << 6)) | ((value as u32 & 0x0003_ffff) << 6); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&self) -> DITHER_R { + DITHER_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:23 - Period Value"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(((self.bits >> 6) & 0x0003_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:5 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&mut self) -> DITHER_W { + DITHER_W { w: self } + } + #[doc = "Bits 6:23 - Period Value"] + #[inline(always)] + pub fn per(&mut self) -> PER_W { + PER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [per_dith6_mode](index.html) module"] +pub struct PER_DITH6_MODE_SPEC; +impl crate::RegisterSpec for PER_DITH6_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [per_dith6_mode::R](R) reader structure"] +impl crate::Readable for PER_DITH6_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [per_dith6_mode::W](W) writer structure"] +impl crate::Writable for PER_DITH6_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PER_DITH6_MODE to value 0xffff_ffff"] +impl crate::Resettable for PER_DITH6_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pac/atsamc21j/src/tcc0/perbuf.rs b/pac/atsamc21j/src/tcc0/perbuf.rs new file mode 100644 index 000000000000..169f17479616 --- /dev/null +++ b/pac/atsamc21j/src/tcc0/perbuf.rs @@ -0,0 +1,103 @@ +#[doc = "Register `PERBUF` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PERBUF` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PERBUF` reader - Period Buffer Value"] +pub struct PERBUF_R(crate::FieldReader); +impl PERBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + PERBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERBUF` writer - Period Buffer Value"] +pub struct PERBUF_W<'a> { + w: &'a mut W, +} +impl<'a> PERBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Period Buffer Value"] + #[inline(always)] + pub fn perbuf(&self) -> PERBUF_R { + PERBUF_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Period Buffer Value"] + #[inline(always)] + pub fn perbuf(&mut self) -> PERBUF_W { + PERBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [perbuf](index.html) module"] +pub struct PERBUF_SPEC; +impl crate::RegisterSpec for PERBUF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [perbuf::R](R) reader structure"] +impl crate::Readable for PERBUF_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [perbuf::W](W) writer structure"] +impl crate::Writable for PERBUF_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PERBUF to value 0xffff_ffff"] +impl crate::Resettable for PERBUF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pac/atsamc21j/src/tcc0/perbuf_dith4_mode.rs b/pac/atsamc21j/src/tcc0/perbuf_dith4_mode.rs new file mode 100644 index 000000000000..ccf96ecef185 --- /dev/null +++ b/pac/atsamc21j/src/tcc0/perbuf_dith4_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PERBUF_DITH4_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PERBUF_DITH4_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHERBUF` reader - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_R(crate::FieldReader); +impl DITHERBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHERBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHERBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHERBUF` writer - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_W<'a> { + w: &'a mut W, +} +impl<'a> DITHERBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Field `PERBUF` reader - Period Buffer Value"] +pub struct PERBUF_R(crate::FieldReader); +impl PERBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + PERBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERBUF` writer - Period Buffer Value"] +pub struct PERBUF_W<'a> { + w: &'a mut W, +} +impl<'a> PERBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x000f_ffff << 4)) | ((value as u32 & 0x000f_ffff) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&self) -> DITHERBUF_R { + DITHERBUF_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:23 - Period Buffer Value"] + #[inline(always)] + pub fn perbuf(&self) -> PERBUF_R { + PERBUF_R::new(((self.bits >> 4) & 0x000f_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:3 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&mut self) -> DITHERBUF_W { + DITHERBUF_W { w: self } + } + #[doc = "Bits 4:23 - Period Buffer Value"] + #[inline(always)] + pub fn perbuf(&mut self) -> PERBUF_W { + PERBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [perbuf_dith4_mode](index.html) module"] +pub struct PERBUF_DITH4_MODE_SPEC; +impl crate::RegisterSpec for PERBUF_DITH4_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [perbuf_dith4_mode::R](R) reader structure"] +impl crate::Readable for PERBUF_DITH4_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [perbuf_dith4_mode::W](W) writer structure"] +impl crate::Writable for PERBUF_DITH4_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PERBUF_DITH4_MODE to value 0xffff_ffff"] +impl crate::Resettable for PERBUF_DITH4_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pac/atsamc21j/src/tcc0/perbuf_dith5_mode.rs b/pac/atsamc21j/src/tcc0/perbuf_dith5_mode.rs new file mode 100644 index 000000000000..d55f6d52c5ba --- /dev/null +++ b/pac/atsamc21j/src/tcc0/perbuf_dith5_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PERBUF_DITH5_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PERBUF_DITH5_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHERBUF` reader - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_R(crate::FieldReader); +impl DITHERBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHERBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHERBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHERBUF` writer - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_W<'a> { + w: &'a mut W, +} +impl<'a> DITHERBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f); + self.w + } +} +#[doc = "Field `PERBUF` reader - Period Buffer Value"] +pub struct PERBUF_R(crate::FieldReader); +impl PERBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + PERBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERBUF` writer - Period Buffer Value"] +pub struct PERBUF_W<'a> { + w: &'a mut W, +} +impl<'a> PERBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0007_ffff << 5)) | ((value as u32 & 0x0007_ffff) << 5); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&self) -> DITHERBUF_R { + DITHERBUF_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:23 - Period Buffer Value"] + #[inline(always)] + pub fn perbuf(&self) -> PERBUF_R { + PERBUF_R::new(((self.bits >> 5) & 0x0007_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:4 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&mut self) -> DITHERBUF_W { + DITHERBUF_W { w: self } + } + #[doc = "Bits 5:23 - Period Buffer Value"] + #[inline(always)] + pub fn perbuf(&mut self) -> PERBUF_W { + PERBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [perbuf_dith5_mode](index.html) module"] +pub struct PERBUF_DITH5_MODE_SPEC; +impl crate::RegisterSpec for PERBUF_DITH5_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [perbuf_dith5_mode::R](R) reader structure"] +impl crate::Readable for PERBUF_DITH5_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [perbuf_dith5_mode::W](W) writer structure"] +impl crate::Writable for PERBUF_DITH5_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PERBUF_DITH5_MODE to value 0xffff_ffff"] +impl crate::Resettable for PERBUF_DITH5_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pac/atsamc21j/src/tcc0/perbuf_dith6_mode.rs b/pac/atsamc21j/src/tcc0/perbuf_dith6_mode.rs new file mode 100644 index 000000000000..983c849f9073 --- /dev/null +++ b/pac/atsamc21j/src/tcc0/perbuf_dith6_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PERBUF_DITH6_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PERBUF_DITH6_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHERBUF` reader - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_R(crate::FieldReader); +impl DITHERBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHERBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHERBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHERBUF` writer - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_W<'a> { + w: &'a mut W, +} +impl<'a> DITHERBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +#[doc = "Field `PERBUF` reader - Period Buffer Value"] +pub struct PERBUF_R(crate::FieldReader); +impl PERBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + PERBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERBUF` writer - Period Buffer Value"] +pub struct PERBUF_W<'a> { + w: &'a mut W, +} +impl<'a> PERBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0003_ffff << 6)) | ((value as u32 & 0x0003_ffff) << 6); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&self) -> DITHERBUF_R { + DITHERBUF_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:23 - Period Buffer Value"] + #[inline(always)] + pub fn perbuf(&self) -> PERBUF_R { + PERBUF_R::new(((self.bits >> 6) & 0x0003_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:5 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&mut self) -> DITHERBUF_W { + DITHERBUF_W { w: self } + } + #[doc = "Bits 6:23 - Period Buffer Value"] + #[inline(always)] + pub fn perbuf(&mut self) -> PERBUF_W { + PERBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [perbuf_dith6_mode](index.html) module"] +pub struct PERBUF_DITH6_MODE_SPEC; +impl crate::RegisterSpec for PERBUF_DITH6_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [perbuf_dith6_mode::R](R) reader structure"] +impl crate::Readable for PERBUF_DITH6_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [perbuf_dith6_mode::W](W) writer structure"] +impl crate::Writable for PERBUF_DITH6_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PERBUF_DITH6_MODE to value 0xffff_ffff"] +impl crate::Resettable for PERBUF_DITH6_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pac/atsamc21j/src/tcc0/status.rs b/pac/atsamc21j/src/tcc0/status.rs new file mode 100644 index 000000000000..eecd909e6093 --- /dev/null +++ b/pac/atsamc21j/src/tcc0/status.rs @@ -0,0 +1,1147 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `STOP` reader - Stop"] +pub struct STOP_R(crate::FieldReader); +impl STOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STOP` writer - Stop"] +pub struct STOP_W<'a> { + w: &'a mut W, +} +impl<'a> STOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `IDX` reader - Ramp"] +pub struct IDX_R(crate::FieldReader); +impl IDX_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IDX_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IDX_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IDX` writer - Ramp"] +pub struct IDX_W<'a> { + w: &'a mut W, +} +impl<'a> IDX_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `UFS` reader - Non-recoverable Update Fault State"] +pub struct UFS_R(crate::FieldReader); +impl UFS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UFS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for UFS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `UFS` writer - Non-recoverable Update Fault State"] +pub struct UFS_W<'a> { + w: &'a mut W, +} +impl<'a> UFS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `DFS` reader - Non-Recoverable Debug Fault State"] +pub struct DFS_R(crate::FieldReader); +impl DFS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFS` writer - Non-Recoverable Debug Fault State"] +pub struct DFS_W<'a> { + w: &'a mut W, +} +impl<'a> DFS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `SLAVE` reader - Slave"] +pub struct SLAVE_R(crate::FieldReader); +impl SLAVE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLAVE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SLAVE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLAVE` writer - Slave"] +pub struct SLAVE_W<'a> { + w: &'a mut W, +} +impl<'a> SLAVE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PATTBUFV` reader - Pattern Buffer Valid"] +pub struct PATTBUFV_R(crate::FieldReader); +impl PATTBUFV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PATTBUFV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PATTBUFV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PATTBUFV` writer - Pattern Buffer Valid"] +pub struct PATTBUFV_W<'a> { + w: &'a mut W, +} +impl<'a> PATTBUFV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PERBUFV` reader - Period Buffer Valid"] +pub struct PERBUFV_R(crate::FieldReader); +impl PERBUFV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PERBUFV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERBUFV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERBUFV` writer - Period Buffer Valid"] +pub struct PERBUFV_W<'a> { + w: &'a mut W, +} +impl<'a> PERBUFV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `FAULTAIN` reader - Recoverable Fault A Input"] +pub struct FAULTAIN_R(crate::FieldReader); +impl FAULTAIN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTAIN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTAIN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTAIN` writer - Recoverable Fault A Input"] +pub struct FAULTAIN_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTAIN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `FAULTBIN` reader - Recoverable Fault B Input"] +pub struct FAULTBIN_R(crate::FieldReader); +impl FAULTBIN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTBIN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTBIN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTBIN` writer - Recoverable Fault B Input"] +pub struct FAULTBIN_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTBIN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `FAULT0IN` reader - Non-Recoverable Fault0 Input"] +pub struct FAULT0IN_R(crate::FieldReader); +impl FAULT0IN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT0IN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT0IN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT0IN` writer - Non-Recoverable Fault0 Input"] +pub struct FAULT0IN_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT0IN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `FAULT1IN` reader - Non-Recoverable Fault1 Input"] +pub struct FAULT1IN_R(crate::FieldReader); +impl FAULT1IN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT1IN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT1IN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT1IN` writer - Non-Recoverable Fault1 Input"] +pub struct FAULT1IN_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT1IN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `FAULTA` reader - Recoverable Fault A State"] +pub struct FAULTA_R(crate::FieldReader); +impl FAULTA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTA` writer - Recoverable Fault A State"] +pub struct FAULTA_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `FAULTB` reader - Recoverable Fault B State"] +pub struct FAULTB_R(crate::FieldReader); +impl FAULTB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTB` writer - Recoverable Fault B State"] +pub struct FAULTB_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `FAULT0` reader - Non-Recoverable Fault 0 State"] +pub struct FAULT0_R(crate::FieldReader); +impl FAULT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT0` writer - Non-Recoverable Fault 0 State"] +pub struct FAULT0_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `FAULT1` reader - Non-Recoverable Fault 1 State"] +pub struct FAULT1_R(crate::FieldReader); +impl FAULT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT1` writer - Non-Recoverable Fault 1 State"] +pub struct FAULT1_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `CCBUFV0` reader - Compare Channel 0 Buffer Valid"] +pub struct CCBUFV0_R(crate::FieldReader); +impl CCBUFV0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBUFV0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUFV0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUFV0` writer - Compare Channel 0 Buffer Valid"] +pub struct CCBUFV0_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUFV0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `CCBUFV1` reader - Compare Channel 1 Buffer Valid"] +pub struct CCBUFV1_R(crate::FieldReader); +impl CCBUFV1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBUFV1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUFV1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUFV1` writer - Compare Channel 1 Buffer Valid"] +pub struct CCBUFV1_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUFV1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `CCBUFV2` reader - Compare Channel 2 Buffer Valid"] +pub struct CCBUFV2_R(crate::FieldReader); +impl CCBUFV2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBUFV2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUFV2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUFV2` writer - Compare Channel 2 Buffer Valid"] +pub struct CCBUFV2_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUFV2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `CCBUFV3` reader - Compare Channel 3 Buffer Valid"] +pub struct CCBUFV3_R(crate::FieldReader); +impl CCBUFV3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBUFV3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUFV3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUFV3` writer - Compare Channel 3 Buffer Valid"] +pub struct CCBUFV3_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUFV3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `CMP0` reader - Compare Channel 0 Value"] +pub struct CMP0_R(crate::FieldReader); +impl CMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP0` writer - Compare Channel 0 Value"] +pub struct CMP0_W<'a> { + w: &'a mut W, +} +impl<'a> CMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `CMP1` reader - Compare Channel 1 Value"] +pub struct CMP1_R(crate::FieldReader); +impl CMP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP1` writer - Compare Channel 1 Value"] +pub struct CMP1_W<'a> { + w: &'a mut W, +} +impl<'a> CMP1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `CMP2` reader - Compare Channel 2 Value"] +pub struct CMP2_R(crate::FieldReader); +impl CMP2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP2` writer - Compare Channel 2 Value"] +pub struct CMP2_W<'a> { + w: &'a mut W, +} +impl<'a> CMP2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `CMP3` reader - Compare Channel 3 Value"] +pub struct CMP3_R(crate::FieldReader); +impl CMP3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP3` writer - Compare Channel 3 Value"] +pub struct CMP3_W<'a> { + w: &'a mut W, +} +impl<'a> CMP3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +impl R { + #[doc = "Bit 0 - Stop"] + #[inline(always)] + pub fn stop(&self) -> STOP_R { + STOP_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Ramp"] + #[inline(always)] + pub fn idx(&self) -> IDX_R { + IDX_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Non-recoverable Update Fault State"] + #[inline(always)] + pub fn ufs(&self) -> UFS_R { + UFS_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Non-Recoverable Debug Fault State"] + #[inline(always)] + pub fn dfs(&self) -> DFS_R { + DFS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Slave"] + #[inline(always)] + pub fn slave(&self) -> SLAVE_R { + SLAVE_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Pattern Buffer Valid"] + #[inline(always)] + pub fn pattbufv(&self) -> PATTBUFV_R { + PATTBUFV_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 7 - Period Buffer Valid"] + #[inline(always)] + pub fn perbufv(&self) -> PERBUFV_R { + PERBUFV_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Recoverable Fault A Input"] + #[inline(always)] + pub fn faultain(&self) -> FAULTAIN_R { + FAULTAIN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Recoverable Fault B Input"] + #[inline(always)] + pub fn faultbin(&self) -> FAULTBIN_R { + FAULTBIN_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Non-Recoverable Fault0 Input"] + #[inline(always)] + pub fn fault0in(&self) -> FAULT0IN_R { + FAULT0IN_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Non-Recoverable Fault1 Input"] + #[inline(always)] + pub fn fault1in(&self) -> FAULT1IN_R { + FAULT1IN_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Recoverable Fault A State"] + #[inline(always)] + pub fn faulta(&self) -> FAULTA_R { + FAULTA_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Recoverable Fault B State"] + #[inline(always)] + pub fn faultb(&self) -> FAULTB_R { + FAULTB_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Non-Recoverable Fault 0 State"] + #[inline(always)] + pub fn fault0(&self) -> FAULT0_R { + FAULT0_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Non-Recoverable Fault 1 State"] + #[inline(always)] + pub fn fault1(&self) -> FAULT1_R { + FAULT1_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Compare Channel 0 Buffer Valid"] + #[inline(always)] + pub fn ccbufv0(&self) -> CCBUFV0_R { + CCBUFV0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Compare Channel 1 Buffer Valid"] + #[inline(always)] + pub fn ccbufv1(&self) -> CCBUFV1_R { + CCBUFV1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Compare Channel 2 Buffer Valid"] + #[inline(always)] + pub fn ccbufv2(&self) -> CCBUFV2_R { + CCBUFV2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Compare Channel 3 Buffer Valid"] + #[inline(always)] + pub fn ccbufv3(&self) -> CCBUFV3_R { + CCBUFV3_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 24 - Compare Channel 0 Value"] + #[inline(always)] + pub fn cmp0(&self) -> CMP0_R { + CMP0_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Compare Channel 1 Value"] + #[inline(always)] + pub fn cmp1(&self) -> CMP1_R { + CMP1_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Compare Channel 2 Value"] + #[inline(always)] + pub fn cmp2(&self) -> CMP2_R { + CMP2_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Compare Channel 3 Value"] + #[inline(always)] + pub fn cmp3(&self) -> CMP3_R { + CMP3_R::new(((self.bits >> 27) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Stop"] + #[inline(always)] + pub fn stop(&mut self) -> STOP_W { + STOP_W { w: self } + } + #[doc = "Bit 1 - Ramp"] + #[inline(always)] + pub fn idx(&mut self) -> IDX_W { + IDX_W { w: self } + } + #[doc = "Bit 2 - Non-recoverable Update Fault State"] + #[inline(always)] + pub fn ufs(&mut self) -> UFS_W { + UFS_W { w: self } + } + #[doc = "Bit 3 - Non-Recoverable Debug Fault State"] + #[inline(always)] + pub fn dfs(&mut self) -> DFS_W { + DFS_W { w: self } + } + #[doc = "Bit 4 - Slave"] + #[inline(always)] + pub fn slave(&mut self) -> SLAVE_W { + SLAVE_W { w: self } + } + #[doc = "Bit 5 - Pattern Buffer Valid"] + #[inline(always)] + pub fn pattbufv(&mut self) -> PATTBUFV_W { + PATTBUFV_W { w: self } + } + #[doc = "Bit 7 - Period Buffer Valid"] + #[inline(always)] + pub fn perbufv(&mut self) -> PERBUFV_W { + PERBUFV_W { w: self } + } + #[doc = "Bit 8 - Recoverable Fault A Input"] + #[inline(always)] + pub fn faultain(&mut self) -> FAULTAIN_W { + FAULTAIN_W { w: self } + } + #[doc = "Bit 9 - Recoverable Fault B Input"] + #[inline(always)] + pub fn faultbin(&mut self) -> FAULTBIN_W { + FAULTBIN_W { w: self } + } + #[doc = "Bit 10 - Non-Recoverable Fault0 Input"] + #[inline(always)] + pub fn fault0in(&mut self) -> FAULT0IN_W { + FAULT0IN_W { w: self } + } + #[doc = "Bit 11 - Non-Recoverable Fault1 Input"] + #[inline(always)] + pub fn fault1in(&mut self) -> FAULT1IN_W { + FAULT1IN_W { w: self } + } + #[doc = "Bit 12 - Recoverable Fault A State"] + #[inline(always)] + pub fn faulta(&mut self) -> FAULTA_W { + FAULTA_W { w: self } + } + #[doc = "Bit 13 - Recoverable Fault B State"] + #[inline(always)] + pub fn faultb(&mut self) -> FAULTB_W { + FAULTB_W { w: self } + } + #[doc = "Bit 14 - Non-Recoverable Fault 0 State"] + #[inline(always)] + pub fn fault0(&mut self) -> FAULT0_W { + FAULT0_W { w: self } + } + #[doc = "Bit 15 - Non-Recoverable Fault 1 State"] + #[inline(always)] + pub fn fault1(&mut self) -> FAULT1_W { + FAULT1_W { w: self } + } + #[doc = "Bit 16 - Compare Channel 0 Buffer Valid"] + #[inline(always)] + pub fn ccbufv0(&mut self) -> CCBUFV0_W { + CCBUFV0_W { w: self } + } + #[doc = "Bit 17 - Compare Channel 1 Buffer Valid"] + #[inline(always)] + pub fn ccbufv1(&mut self) -> CCBUFV1_W { + CCBUFV1_W { w: self } + } + #[doc = "Bit 18 - Compare Channel 2 Buffer Valid"] + #[inline(always)] + pub fn ccbufv2(&mut self) -> CCBUFV2_W { + CCBUFV2_W { w: self } + } + #[doc = "Bit 19 - Compare Channel 3 Buffer Valid"] + #[inline(always)] + pub fn ccbufv3(&mut self) -> CCBUFV3_W { + CCBUFV3_W { w: self } + } + #[doc = "Bit 24 - Compare Channel 0 Value"] + #[inline(always)] + pub fn cmp0(&mut self) -> CMP0_W { + CMP0_W { w: self } + } + #[doc = "Bit 25 - Compare Channel 1 Value"] + #[inline(always)] + pub fn cmp1(&mut self) -> CMP1_W { + CMP1_W { w: self } + } + #[doc = "Bit 26 - Compare Channel 2 Value"] + #[inline(always)] + pub fn cmp2(&mut self) -> CMP2_W { + CMP2_W { w: self } + } + #[doc = "Bit 27 - Compare Channel 3 Value"] + #[inline(always)] + pub fn cmp3(&mut self) -> CMP3_W { + CMP3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0x01"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pac/atsamc21j/src/tcc0/syncbusy.rs b/pac/atsamc21j/src/tcc0/syncbusy.rs new file mode 100644 index 000000000000..db0788c3f206 --- /dev/null +++ b/pac/atsamc21j/src/tcc0/syncbusy.rs @@ -0,0 +1,273 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Swrst Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - Enable Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLB` reader - Ctrlb Busy"] +pub struct CTRLB_R(crate::FieldReader); +impl CTRLB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STATUS` reader - Status Busy"] +pub struct STATUS_R(crate::FieldReader); +impl STATUS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STATUS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STATUS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` reader - Count Busy"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PATT` reader - Pattern Busy"] +pub struct PATT_R(crate::FieldReader); +impl PATT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PATT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PATT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAVE` reader - Wave Busy"] +pub struct WAVE_R(crate::FieldReader); +impl WAVE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAVE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAVE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` reader - Period Busy"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC0` reader - Compare Channel 0 Busy"] +pub struct CC0_R(crate::FieldReader); +impl CC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC1` reader - Compare Channel 1 Busy"] +pub struct CC1_R(crate::FieldReader); +impl CC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC2` reader - Compare Channel 2 Busy"] +pub struct CC2_R(crate::FieldReader); +impl CC2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC3` reader - Compare Channel 3 Busy"] +pub struct CC3_R(crate::FieldReader); +impl CC3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Swrst Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Ctrlb Busy"] + #[inline(always)] + pub fn ctrlb(&self) -> CTRLB_R { + CTRLB_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Status Busy"] + #[inline(always)] + pub fn status(&self) -> STATUS_R { + STATUS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Count Busy"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Pattern Busy"] + #[inline(always)] + pub fn patt(&self) -> PATT_R { + PATT_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Wave Busy"] + #[inline(always)] + pub fn wave(&self) -> WAVE_R { + WAVE_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Period Busy"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Compare Channel 0 Busy"] + #[inline(always)] + pub fn cc0(&self) -> CC0_R { + CC0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Compare Channel 1 Busy"] + #[inline(always)] + pub fn cc1(&self) -> CC1_R { + CC1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Compare Channel 2 Busy"] + #[inline(always)] + pub fn cc2(&self) -> CC2_R { + CC2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Compare Channel 3 Busy"] + #[inline(always)] + pub fn cc3(&self) -> CC3_R { + CC3_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +#[doc = "Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/tcc0/wave.rs b/pac/atsamc21j/src/tcc0/wave.rs new file mode 100644 index 000000000000..8d092d429a91 --- /dev/null +++ b/pac/atsamc21j/src/tcc0/wave.rs @@ -0,0 +1,940 @@ +#[doc = "Register `WAVE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WAVE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Waveform Generation\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WAVEGEN_A { + #[doc = "0: Normal frequency"] + NFRQ = 0, + #[doc = "1: Match frequency"] + MFRQ = 1, + #[doc = "2: Normal PWM"] + NPWM = 2, + #[doc = "4: Dual-slope critical"] + DSCRITICAL = 4, + #[doc = "5: Dual-slope with interrupt/event condition when COUNT reaches ZERO"] + DSBOTTOM = 5, + #[doc = "6: Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP"] + DSBOTH = 6, + #[doc = "7: Dual-slope with interrupt/event condition when COUNT reaches TOP"] + DSTOP = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WAVEGEN_A) -> Self { + variant as _ + } +} +#[doc = "Field `WAVEGEN` reader - Waveform Generation"] +pub struct WAVEGEN_R(crate::FieldReader); +impl WAVEGEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WAVEGEN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(WAVEGEN_A::NFRQ), + 1 => Some(WAVEGEN_A::MFRQ), + 2 => Some(WAVEGEN_A::NPWM), + 4 => Some(WAVEGEN_A::DSCRITICAL), + 5 => Some(WAVEGEN_A::DSBOTTOM), + 6 => Some(WAVEGEN_A::DSBOTH), + 7 => Some(WAVEGEN_A::DSTOP), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NFRQ`"] + #[inline(always)] + pub fn is_nfrq(&self) -> bool { + **self == WAVEGEN_A::NFRQ + } + #[doc = "Checks if the value of the field is `MFRQ`"] + #[inline(always)] + pub fn is_mfrq(&self) -> bool { + **self == WAVEGEN_A::MFRQ + } + #[doc = "Checks if the value of the field is `NPWM`"] + #[inline(always)] + pub fn is_npwm(&self) -> bool { + **self == WAVEGEN_A::NPWM + } + #[doc = "Checks if the value of the field is `DSCRITICAL`"] + #[inline(always)] + pub fn is_dscritical(&self) -> bool { + **self == WAVEGEN_A::DSCRITICAL + } + #[doc = "Checks if the value of the field is `DSBOTTOM`"] + #[inline(always)] + pub fn is_dsbottom(&self) -> bool { + **self == WAVEGEN_A::DSBOTTOM + } + #[doc = "Checks if the value of the field is `DSBOTH`"] + #[inline(always)] + pub fn is_dsboth(&self) -> bool { + **self == WAVEGEN_A::DSBOTH + } + #[doc = "Checks if the value of the field is `DSTOP`"] + #[inline(always)] + pub fn is_dstop(&self) -> bool { + **self == WAVEGEN_A::DSTOP + } +} +impl core::ops::Deref for WAVEGEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAVEGEN` writer - Waveform Generation"] +pub struct WAVEGEN_W<'a> { + w: &'a mut W, +} +impl<'a> WAVEGEN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WAVEGEN_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Normal frequency"] + #[inline(always)] + pub fn nfrq(self) -> &'a mut W { + self.variant(WAVEGEN_A::NFRQ) + } + #[doc = "Match frequency"] + #[inline(always)] + pub fn mfrq(self) -> &'a mut W { + self.variant(WAVEGEN_A::MFRQ) + } + #[doc = "Normal PWM"] + #[inline(always)] + pub fn npwm(self) -> &'a mut W { + self.variant(WAVEGEN_A::NPWM) + } + #[doc = "Dual-slope critical"] + #[inline(always)] + pub fn dscritical(self) -> &'a mut W { + self.variant(WAVEGEN_A::DSCRITICAL) + } + #[doc = "Dual-slope with interrupt/event condition when COUNT reaches ZERO"] + #[inline(always)] + pub fn dsbottom(self) -> &'a mut W { + self.variant(WAVEGEN_A::DSBOTTOM) + } + #[doc = "Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP"] + #[inline(always)] + pub fn dsboth(self) -> &'a mut W { + self.variant(WAVEGEN_A::DSBOTH) + } + #[doc = "Dual-slope with interrupt/event condition when COUNT reaches TOP"] + #[inline(always)] + pub fn dstop(self) -> &'a mut W { + self.variant(WAVEGEN_A::DSTOP) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Ramp Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum RAMP_A { + #[doc = "0: RAMP1 operation"] + RAMP1 = 0, + #[doc = "1: Alternative RAMP2 operation"] + RAMP2A = 1, + #[doc = "2: RAMP2 operation"] + RAMP2 = 2, + #[doc = "3: Critical RAMP2 operation"] + RAMP2C = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RAMP_A) -> Self { + variant as _ + } +} +#[doc = "Field `RAMP` reader - Ramp Mode"] +pub struct RAMP_R(crate::FieldReader); +impl RAMP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RAMP_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RAMP_A { + match self.bits { + 0 => RAMP_A::RAMP1, + 1 => RAMP_A::RAMP2A, + 2 => RAMP_A::RAMP2, + 3 => RAMP_A::RAMP2C, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `RAMP1`"] + #[inline(always)] + pub fn is_ramp1(&self) -> bool { + **self == RAMP_A::RAMP1 + } + #[doc = "Checks if the value of the field is `RAMP2A`"] + #[inline(always)] + pub fn is_ramp2a(&self) -> bool { + **self == RAMP_A::RAMP2A + } + #[doc = "Checks if the value of the field is `RAMP2`"] + #[inline(always)] + pub fn is_ramp2(&self) -> bool { + **self == RAMP_A::RAMP2 + } + #[doc = "Checks if the value of the field is `RAMP2C`"] + #[inline(always)] + pub fn is_ramp2c(&self) -> bool { + **self == RAMP_A::RAMP2C + } +} +impl core::ops::Deref for RAMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RAMP` writer - Ramp Mode"] +pub struct RAMP_W<'a> { + w: &'a mut W, +} +impl<'a> RAMP_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RAMP_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "RAMP1 operation"] + #[inline(always)] + pub fn ramp1(self) -> &'a mut W { + self.variant(RAMP_A::RAMP1) + } + #[doc = "Alternative RAMP2 operation"] + #[inline(always)] + pub fn ramp2a(self) -> &'a mut W { + self.variant(RAMP_A::RAMP2A) + } + #[doc = "RAMP2 operation"] + #[inline(always)] + pub fn ramp2(self) -> &'a mut W { + self.variant(RAMP_A::RAMP2) + } + #[doc = "Critical RAMP2 operation"] + #[inline(always)] + pub fn ramp2c(self) -> &'a mut W { + self.variant(RAMP_A::RAMP2C) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u32 & 0x03) << 4); + self.w + } +} +#[doc = "Field `CIPEREN` reader - Circular period Enable"] +pub struct CIPEREN_R(crate::FieldReader); +impl CIPEREN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CIPEREN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CIPEREN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CIPEREN` writer - Circular period Enable"] +pub struct CIPEREN_W<'a> { + w: &'a mut W, +} +impl<'a> CIPEREN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CICCEN0` reader - Circular Channel 0 Enable"] +pub struct CICCEN0_R(crate::FieldReader); +impl CICCEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CICCEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CICCEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CICCEN0` writer - Circular Channel 0 Enable"] +pub struct CICCEN0_W<'a> { + w: &'a mut W, +} +impl<'a> CICCEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `CICCEN1` reader - Circular Channel 1 Enable"] +pub struct CICCEN1_R(crate::FieldReader); +impl CICCEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CICCEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CICCEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CICCEN1` writer - Circular Channel 1 Enable"] +pub struct CICCEN1_W<'a> { + w: &'a mut W, +} +impl<'a> CICCEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `CICCEN2` reader - Circular Channel 2 Enable"] +pub struct CICCEN2_R(crate::FieldReader); +impl CICCEN2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CICCEN2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CICCEN2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CICCEN2` writer - Circular Channel 2 Enable"] +pub struct CICCEN2_W<'a> { + w: &'a mut W, +} +impl<'a> CICCEN2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `CICCEN3` reader - Circular Channel 3 Enable"] +pub struct CICCEN3_R(crate::FieldReader); +impl CICCEN3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CICCEN3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CICCEN3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CICCEN3` writer - Circular Channel 3 Enable"] +pub struct CICCEN3_W<'a> { + w: &'a mut W, +} +impl<'a> CICCEN3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `POL0` reader - Channel 0 Polarity"] +pub struct POL0_R(crate::FieldReader); +impl POL0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + POL0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for POL0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `POL0` writer - Channel 0 Polarity"] +pub struct POL0_W<'a> { + w: &'a mut W, +} +impl<'a> POL0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `POL1` reader - Channel 1 Polarity"] +pub struct POL1_R(crate::FieldReader); +impl POL1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + POL1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for POL1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `POL1` writer - Channel 1 Polarity"] +pub struct POL1_W<'a> { + w: &'a mut W, +} +impl<'a> POL1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `POL2` reader - Channel 2 Polarity"] +pub struct POL2_R(crate::FieldReader); +impl POL2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + POL2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for POL2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `POL2` writer - Channel 2 Polarity"] +pub struct POL2_W<'a> { + w: &'a mut W, +} +impl<'a> POL2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `POL3` reader - Channel 3 Polarity"] +pub struct POL3_R(crate::FieldReader); +impl POL3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + POL3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for POL3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `POL3` writer - Channel 3 Polarity"] +pub struct POL3_W<'a> { + w: &'a mut W, +} +impl<'a> POL3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `SWAP0` reader - Swap DTI Output Pair 0"] +pub struct SWAP0_R(crate::FieldReader); +impl SWAP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWAP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWAP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWAP0` writer - Swap DTI Output Pair 0"] +pub struct SWAP0_W<'a> { + w: &'a mut W, +} +impl<'a> SWAP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `SWAP1` reader - Swap DTI Output Pair 1"] +pub struct SWAP1_R(crate::FieldReader); +impl SWAP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWAP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWAP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWAP1` writer - Swap DTI Output Pair 1"] +pub struct SWAP1_W<'a> { + w: &'a mut W, +} +impl<'a> SWAP1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `SWAP2` reader - Swap DTI Output Pair 2"] +pub struct SWAP2_R(crate::FieldReader); +impl SWAP2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWAP2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWAP2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWAP2` writer - Swap DTI Output Pair 2"] +pub struct SWAP2_W<'a> { + w: &'a mut W, +} +impl<'a> SWAP2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `SWAP3` reader - Swap DTI Output Pair 3"] +pub struct SWAP3_R(crate::FieldReader); +impl SWAP3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWAP3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWAP3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWAP3` writer - Swap DTI Output Pair 3"] +pub struct SWAP3_W<'a> { + w: &'a mut W, +} +impl<'a> SWAP3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Waveform Generation"] + #[inline(always)] + pub fn wavegen(&self) -> WAVEGEN_R { + WAVEGEN_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bits 4:5 - Ramp Mode"] + #[inline(always)] + pub fn ramp(&self) -> RAMP_R { + RAMP_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bit 7 - Circular period Enable"] + #[inline(always)] + pub fn ciperen(&self) -> CIPEREN_R { + CIPEREN_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Circular Channel 0 Enable"] + #[inline(always)] + pub fn ciccen0(&self) -> CICCEN0_R { + CICCEN0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Circular Channel 1 Enable"] + #[inline(always)] + pub fn ciccen1(&self) -> CICCEN1_R { + CICCEN1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Circular Channel 2 Enable"] + #[inline(always)] + pub fn ciccen2(&self) -> CICCEN2_R { + CICCEN2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Circular Channel 3 Enable"] + #[inline(always)] + pub fn ciccen3(&self) -> CICCEN3_R { + CICCEN3_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 16 - Channel 0 Polarity"] + #[inline(always)] + pub fn pol0(&self) -> POL0_R { + POL0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Channel 1 Polarity"] + #[inline(always)] + pub fn pol1(&self) -> POL1_R { + POL1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Channel 2 Polarity"] + #[inline(always)] + pub fn pol2(&self) -> POL2_R { + POL2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Channel 3 Polarity"] + #[inline(always)] + pub fn pol3(&self) -> POL3_R { + POL3_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 24 - Swap DTI Output Pair 0"] + #[inline(always)] + pub fn swap0(&self) -> SWAP0_R { + SWAP0_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Swap DTI Output Pair 1"] + #[inline(always)] + pub fn swap1(&self) -> SWAP1_R { + SWAP1_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Swap DTI Output Pair 2"] + #[inline(always)] + pub fn swap2(&self) -> SWAP2_R { + SWAP2_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Swap DTI Output Pair 3"] + #[inline(always)] + pub fn swap3(&self) -> SWAP3_R { + SWAP3_R::new(((self.bits >> 27) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Waveform Generation"] + #[inline(always)] + pub fn wavegen(&mut self) -> WAVEGEN_W { + WAVEGEN_W { w: self } + } + #[doc = "Bits 4:5 - Ramp Mode"] + #[inline(always)] + pub fn ramp(&mut self) -> RAMP_W { + RAMP_W { w: self } + } + #[doc = "Bit 7 - Circular period Enable"] + #[inline(always)] + pub fn ciperen(&mut self) -> CIPEREN_W { + CIPEREN_W { w: self } + } + #[doc = "Bit 8 - Circular Channel 0 Enable"] + #[inline(always)] + pub fn ciccen0(&mut self) -> CICCEN0_W { + CICCEN0_W { w: self } + } + #[doc = "Bit 9 - Circular Channel 1 Enable"] + #[inline(always)] + pub fn ciccen1(&mut self) -> CICCEN1_W { + CICCEN1_W { w: self } + } + #[doc = "Bit 10 - Circular Channel 2 Enable"] + #[inline(always)] + pub fn ciccen2(&mut self) -> CICCEN2_W { + CICCEN2_W { w: self } + } + #[doc = "Bit 11 - Circular Channel 3 Enable"] + #[inline(always)] + pub fn ciccen3(&mut self) -> CICCEN3_W { + CICCEN3_W { w: self } + } + #[doc = "Bit 16 - Channel 0 Polarity"] + #[inline(always)] + pub fn pol0(&mut self) -> POL0_W { + POL0_W { w: self } + } + #[doc = "Bit 17 - Channel 1 Polarity"] + #[inline(always)] + pub fn pol1(&mut self) -> POL1_W { + POL1_W { w: self } + } + #[doc = "Bit 18 - Channel 2 Polarity"] + #[inline(always)] + pub fn pol2(&mut self) -> POL2_W { + POL2_W { w: self } + } + #[doc = "Bit 19 - Channel 3 Polarity"] + #[inline(always)] + pub fn pol3(&mut self) -> POL3_W { + POL3_W { w: self } + } + #[doc = "Bit 24 - Swap DTI Output Pair 0"] + #[inline(always)] + pub fn swap0(&mut self) -> SWAP0_W { + SWAP0_W { w: self } + } + #[doc = "Bit 25 - Swap DTI Output Pair 1"] + #[inline(always)] + pub fn swap1(&mut self) -> SWAP1_W { + SWAP1_W { w: self } + } + #[doc = "Bit 26 - Swap DTI Output Pair 2"] + #[inline(always)] + pub fn swap2(&mut self) -> SWAP2_W { + SWAP2_W { w: self } + } + #[doc = "Bit 27 - Swap DTI Output Pair 3"] + #[inline(always)] + pub fn swap3(&mut self) -> SWAP3_W { + SWAP3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Waveform Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wave](index.html) module"] +pub struct WAVE_SPEC; +impl crate::RegisterSpec for WAVE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [wave::R](R) reader structure"] +impl crate::Readable for WAVE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wave::W](W) writer structure"] +impl crate::Writable for WAVE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WAVE to value 0"] +impl crate::Resettable for WAVE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/tcc0/wexctrl.rs b/pac/atsamc21j/src/tcc0/wexctrl.rs new file mode 100644 index 000000000000..8eb0d29cbee5 --- /dev/null +++ b/pac/atsamc21j/src/tcc0/wexctrl.rs @@ -0,0 +1,365 @@ +#[doc = "Register `WEXCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WEXCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OTMX` reader - Output Matrix"] +pub struct OTMX_R(crate::FieldReader); +impl OTMX_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + OTMX_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OTMX_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OTMX` writer - Output Matrix"] +pub struct OTMX_W<'a> { + w: &'a mut W, +} +impl<'a> OTMX_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u32 & 0x03); + self.w + } +} +#[doc = "Field `DTIEN0` reader - Dead-time Insertion Generator 0 Enable"] +pub struct DTIEN0_R(crate::FieldReader); +impl DTIEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DTIEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DTIEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DTIEN0` writer - Dead-time Insertion Generator 0 Enable"] +pub struct DTIEN0_W<'a> { + w: &'a mut W, +} +impl<'a> DTIEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `DTIEN1` reader - Dead-time Insertion Generator 1 Enable"] +pub struct DTIEN1_R(crate::FieldReader); +impl DTIEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DTIEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DTIEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DTIEN1` writer - Dead-time Insertion Generator 1 Enable"] +pub struct DTIEN1_W<'a> { + w: &'a mut W, +} +impl<'a> DTIEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `DTIEN2` reader - Dead-time Insertion Generator 2 Enable"] +pub struct DTIEN2_R(crate::FieldReader); +impl DTIEN2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DTIEN2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DTIEN2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DTIEN2` writer - Dead-time Insertion Generator 2 Enable"] +pub struct DTIEN2_W<'a> { + w: &'a mut W, +} +impl<'a> DTIEN2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `DTIEN3` reader - Dead-time Insertion Generator 3 Enable"] +pub struct DTIEN3_R(crate::FieldReader); +impl DTIEN3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DTIEN3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DTIEN3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DTIEN3` writer - Dead-time Insertion Generator 3 Enable"] +pub struct DTIEN3_W<'a> { + w: &'a mut W, +} +impl<'a> DTIEN3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `DTLS` reader - Dead-time Low Side Outputs Value"] +pub struct DTLS_R(crate::FieldReader); +impl DTLS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DTLS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DTLS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DTLS` writer - Dead-time Low Side Outputs Value"] +pub struct DTLS_W<'a> { + w: &'a mut W, +} +impl<'a> DTLS_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +#[doc = "Field `DTHS` reader - Dead-time High Side Outputs Value"] +pub struct DTHS_R(crate::FieldReader); +impl DTHS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DTHS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DTHS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DTHS` writer - Dead-time High Side Outputs Value"] +pub struct DTHS_W<'a> { + w: &'a mut W, +} +impl<'a> DTHS_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 24)) | ((value as u32 & 0xff) << 24); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Output Matrix"] + #[inline(always)] + pub fn otmx(&self) -> OTMX_R { + OTMX_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bit 8 - Dead-time Insertion Generator 0 Enable"] + #[inline(always)] + pub fn dtien0(&self) -> DTIEN0_R { + DTIEN0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Dead-time Insertion Generator 1 Enable"] + #[inline(always)] + pub fn dtien1(&self) -> DTIEN1_R { + DTIEN1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Dead-time Insertion Generator 2 Enable"] + #[inline(always)] + pub fn dtien2(&self) -> DTIEN2_R { + DTIEN2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Dead-time Insertion Generator 3 Enable"] + #[inline(always)] + pub fn dtien3(&self) -> DTIEN3_R { + DTIEN3_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bits 16:23 - Dead-time Low Side Outputs Value"] + #[inline(always)] + pub fn dtls(&self) -> DTLS_R { + DTLS_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Dead-time High Side Outputs Value"] + #[inline(always)] + pub fn dths(&self) -> DTHS_R { + DTHS_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Output Matrix"] + #[inline(always)] + pub fn otmx(&mut self) -> OTMX_W { + OTMX_W { w: self } + } + #[doc = "Bit 8 - Dead-time Insertion Generator 0 Enable"] + #[inline(always)] + pub fn dtien0(&mut self) -> DTIEN0_W { + DTIEN0_W { w: self } + } + #[doc = "Bit 9 - Dead-time Insertion Generator 1 Enable"] + #[inline(always)] + pub fn dtien1(&mut self) -> DTIEN1_W { + DTIEN1_W { w: self } + } + #[doc = "Bit 10 - Dead-time Insertion Generator 2 Enable"] + #[inline(always)] + pub fn dtien2(&mut self) -> DTIEN2_W { + DTIEN2_W { w: self } + } + #[doc = "Bit 11 - Dead-time Insertion Generator 3 Enable"] + #[inline(always)] + pub fn dtien3(&mut self) -> DTIEN3_W { + DTIEN3_W { w: self } + } + #[doc = "Bits 16:23 - Dead-time Low Side Outputs Value"] + #[inline(always)] + pub fn dtls(&mut self) -> DTLS_W { + DTLS_W { w: self } + } + #[doc = "Bits 24:31 - Dead-time High Side Outputs Value"] + #[inline(always)] + pub fn dths(&mut self) -> DTHS_W { + DTHS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Waveform Extension Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wexctrl](index.html) module"] +pub struct WEXCTRL_SPEC; +impl crate::RegisterSpec for WEXCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [wexctrl::R](R) reader structure"] +impl crate::Readable for WEXCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wexctrl::W](W) writer structure"] +impl crate::Writable for WEXCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WEXCTRL to value 0"] +impl crate::Resettable for WEXCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/tsens.rs b/pac/atsamc21j/src/tsens.rs new file mode 100644 index 000000000000..3156dee6d87f --- /dev/null +++ b/pac/atsamc21j/src/tsens.rs @@ -0,0 +1,100 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control A Register"] + pub ctrla: crate::Reg, + #[doc = "0x01 - Control B Register"] + pub ctrlb: crate::Reg, + #[doc = "0x02 - Control C Register"] + pub ctrlc: crate::Reg, + #[doc = "0x03 - Event Control Register"] + pub evctrl: crate::Reg, + #[doc = "0x04 - Interrupt Enable Clear Register"] + pub intenclr: crate::Reg, + #[doc = "0x05 - Interrupt Enable Set Register"] + pub intenset: crate::Reg, + #[doc = "0x06 - Interrupt Flag Status and Clear Register"] + pub intflag: crate::Reg, + #[doc = "0x07 - Status Register"] + pub status: crate::Reg, + #[doc = "0x08 - Synchronization Busy Register"] + pub syncbusy: crate::Reg, + #[doc = "0x0c - Value Register"] + pub value: crate::Reg, + #[doc = "0x10 - Window Monitor Lower Threshold Register"] + pub winlt: crate::Reg, + #[doc = "0x14 - Window Monitor Upper Threshold Register"] + pub winut: crate::Reg, + #[doc = "0x18 - Gain Register"] + pub gain: crate::Reg, + #[doc = "0x1c - Offset Register"] + pub offset: crate::Reg, + #[doc = "0x20 - Calibration Register"] + pub cal: crate::Reg, + #[doc = "0x24 - Debug Control Register"] + pub dbgctrl: crate::Reg, +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A Register"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "Control B Register"] +pub mod ctrlb; +#[doc = "CTRLC register accessor: an alias for `Reg`"] +pub type CTRLC = crate::Reg; +#[doc = "Control C Register"] +pub mod ctrlc; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control Register"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear Register"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set Register"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear Register"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status Register"] +pub mod status; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Busy Register"] +pub mod syncbusy; +#[doc = "VALUE register accessor: an alias for `Reg`"] +pub type VALUE = crate::Reg; +#[doc = "Value Register"] +pub mod value; +#[doc = "WINLT register accessor: an alias for `Reg`"] +pub type WINLT = crate::Reg; +#[doc = "Window Monitor Lower Threshold Register"] +pub mod winlt; +#[doc = "WINUT register accessor: an alias for `Reg`"] +pub type WINUT = crate::Reg; +#[doc = "Window Monitor Upper Threshold Register"] +pub mod winut; +#[doc = "GAIN register accessor: an alias for `Reg`"] +pub type GAIN = crate::Reg; +#[doc = "Gain Register"] +pub mod gain; +#[doc = "OFFSET register accessor: an alias for `Reg`"] +pub type OFFSET = crate::Reg; +#[doc = "Offset Register"] +pub mod offset; +#[doc = "CAL register accessor: an alias for `Reg`"] +pub type CAL = crate::Reg; +#[doc = "Calibration Register"] +pub mod cal; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control Register"] +pub mod dbgctrl; diff --git a/pac/atsamc21j/src/tsens/cal.rs b/pac/atsamc21j/src/tsens/cal.rs new file mode 100644 index 000000000000..9b0d76eef9eb --- /dev/null +++ b/pac/atsamc21j/src/tsens/cal.rs @@ -0,0 +1,140 @@ +#[doc = "Register `CAL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CAL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FCAL` reader - Frequency Calibration"] +pub struct FCAL_R(crate::FieldReader); +impl FCAL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FCAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FCAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FCAL` writer - Frequency Calibration"] +pub struct FCAL_W<'a> { + w: &'a mut W, +} +impl<'a> FCAL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +#[doc = "Field `TCAL` reader - Temperature Calibration"] +pub struct TCAL_R(crate::FieldReader); +impl TCAL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TCAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCAL` writer - Temperature Calibration"] +pub struct TCAL_W<'a> { + w: &'a mut W, +} +impl<'a> TCAL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 8)) | ((value as u32 & 0x3f) << 8); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Frequency Calibration"] + #[inline(always)] + pub fn fcal(&self) -> FCAL_R { + FCAL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 8:13 - Temperature Calibration"] + #[inline(always)] + pub fn tcal(&self) -> TCAL_R { + TCAL_R::new(((self.bits >> 8) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - Frequency Calibration"] + #[inline(always)] + pub fn fcal(&mut self) -> FCAL_W { + FCAL_W { w: self } + } + #[doc = "Bits 8:13 - Temperature Calibration"] + #[inline(always)] + pub fn tcal(&mut self) -> TCAL_W { + TCAL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Calibration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cal](index.html) module"] +pub struct CAL_SPEC; +impl crate::RegisterSpec for CAL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cal::R](R) reader structure"] +impl crate::Readable for CAL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cal::W](W) writer structure"] +impl crate::Writable for CAL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CAL to value 0"] +impl crate::Resettable for CAL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/tsens/ctrla.rs b/pac/atsamc21j/src/tsens/ctrla.rs new file mode 100644 index 000000000000..6be7f2fc82f2 --- /dev/null +++ b/pac/atsamc21j/src/tsens/ctrla.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/tsens/ctrlb.rs b/pac/atsamc21j/src/tsens/ctrlb.rs new file mode 100644 index 000000000000..7d350e71fbf3 --- /dev/null +++ b/pac/atsamc21j/src/tsens/ctrlb.rs @@ -0,0 +1,72 @@ +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `START` writer - Start Measurement"] +pub struct START_W<'a> { + w: &'a mut W, +} +impl<'a> START_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0 - Start Measurement"] + #[inline(always)] + pub fn start(&mut self) -> START_W { + START_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u8; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/tsens/ctrlc.rs b/pac/atsamc21j/src/tsens/ctrlc.rs new file mode 100644 index 000000000000..82390cea825d --- /dev/null +++ b/pac/atsamc21j/src/tsens/ctrlc.rs @@ -0,0 +1,264 @@ +#[doc = "Register `CTRLC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Window Monitor Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WINMODE_A { + #[doc = "0: No window mode (default)"] + DISABLE = 0, + #[doc = "1: VALUE greater than WINLT"] + ABOVE = 1, + #[doc = "2: VALUE less than WINUT"] + BELOW = 2, + #[doc = "3: VALUE greater than WINLT and VALUE less than WINUT"] + INSIDE = 3, + #[doc = "4: VALUE less than WINLT or VALUE greater than WINUT"] + OUTSIDE = 4, + #[doc = "5: VALUE greater than WINUT with hysteresis to WINLT"] + HYST_ABOVE = 5, + #[doc = "6: VALUE less than WINLST with hysteresis to WINUT"] + HYST_BELOW = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WINMODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `WINMODE` reader - Window Monitor Mode"] +pub struct WINMODE_R(crate::FieldReader); +impl WINMODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WINMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(WINMODE_A::DISABLE), + 1 => Some(WINMODE_A::ABOVE), + 2 => Some(WINMODE_A::BELOW), + 3 => Some(WINMODE_A::INSIDE), + 4 => Some(WINMODE_A::OUTSIDE), + 5 => Some(WINMODE_A::HYST_ABOVE), + 6 => Some(WINMODE_A::HYST_BELOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == WINMODE_A::DISABLE + } + #[doc = "Checks if the value of the field is `ABOVE`"] + #[inline(always)] + pub fn is_above(&self) -> bool { + **self == WINMODE_A::ABOVE + } + #[doc = "Checks if the value of the field is `BELOW`"] + #[inline(always)] + pub fn is_below(&self) -> bool { + **self == WINMODE_A::BELOW + } + #[doc = "Checks if the value of the field is `INSIDE`"] + #[inline(always)] + pub fn is_inside(&self) -> bool { + **self == WINMODE_A::INSIDE + } + #[doc = "Checks if the value of the field is `OUTSIDE`"] + #[inline(always)] + pub fn is_outside(&self) -> bool { + **self == WINMODE_A::OUTSIDE + } + #[doc = "Checks if the value of the field is `HYST_ABOVE`"] + #[inline(always)] + pub fn is_hyst_above(&self) -> bool { + **self == WINMODE_A::HYST_ABOVE + } + #[doc = "Checks if the value of the field is `HYST_BELOW`"] + #[inline(always)] + pub fn is_hyst_below(&self) -> bool { + **self == WINMODE_A::HYST_BELOW + } +} +impl core::ops::Deref for WINMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMODE` writer - Window Monitor Mode"] +pub struct WINMODE_W<'a> { + w: &'a mut W, +} +impl<'a> WINMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WINMODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No window mode (default)"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(WINMODE_A::DISABLE) + } + #[doc = "VALUE greater than WINLT"] + #[inline(always)] + pub fn above(self) -> &'a mut W { + self.variant(WINMODE_A::ABOVE) + } + #[doc = "VALUE less than WINUT"] + #[inline(always)] + pub fn below(self) -> &'a mut W { + self.variant(WINMODE_A::BELOW) + } + #[doc = "VALUE greater than WINLT and VALUE less than WINUT"] + #[inline(always)] + pub fn inside(self) -> &'a mut W { + self.variant(WINMODE_A::INSIDE) + } + #[doc = "VALUE less than WINLT or VALUE greater than WINUT"] + #[inline(always)] + pub fn outside(self) -> &'a mut W { + self.variant(WINMODE_A::OUTSIDE) + } + #[doc = "VALUE greater than WINUT with hysteresis to WINLT"] + #[inline(always)] + pub fn hyst_above(self) -> &'a mut W { + self.variant(WINMODE_A::HYST_ABOVE) + } + #[doc = "VALUE less than WINLST with hysteresis to WINUT"] + #[inline(always)] + pub fn hyst_below(self) -> &'a mut W { + self.variant(WINMODE_A::HYST_BELOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +#[doc = "Field `FREERUN` reader - Free Running Measurement"] +pub struct FREERUN_R(crate::FieldReader); +impl FREERUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FREERUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FREERUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FREERUN` writer - Free Running Measurement"] +pub struct FREERUN_W<'a> { + w: &'a mut W, +} +impl<'a> FREERUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Window Monitor Mode"] + #[inline(always)] + pub fn winmode(&self) -> WINMODE_R { + WINMODE_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 4 - Free Running Measurement"] + #[inline(always)] + pub fn freerun(&self) -> FREERUN_R { + FREERUN_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Window Monitor Mode"] + #[inline(always)] + pub fn winmode(&mut self) -> WINMODE_W { + WINMODE_W { w: self } + } + #[doc = "Bit 4 - Free Running Measurement"] + #[inline(always)] + pub fn freerun(&mut self) -> FREERUN_W { + FREERUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control C Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlc](index.html) module"] +pub struct CTRLC_SPEC; +impl crate::RegisterSpec for CTRLC_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlc::R](R) reader structure"] +impl crate::Readable for CTRLC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlc::W](W) writer structure"] +impl crate::Writable for CTRLC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLC to value 0"] +impl crate::Resettable for CTRLC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/tsens/dbgctrl.rs b/pac/atsamc21j/src/tsens/dbgctrl.rs new file mode 100644 index 000000000000..dd129a857202 --- /dev/null +++ b/pac/atsamc21j/src/tsens/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Debug Run"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Debug Run"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/tsens/evctrl.rs b/pac/atsamc21j/src/tsens/evctrl.rs new file mode 100644 index 000000000000..20d0f3497e37 --- /dev/null +++ b/pac/atsamc21j/src/tsens/evctrl.rs @@ -0,0 +1,207 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `STARTEI` reader - Start Conversion Event Input Enable"] +pub struct STARTEI_R(crate::FieldReader); +impl STARTEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STARTEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STARTEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STARTEI` writer - Start Conversion Event Input Enable"] +pub struct STARTEI_W<'a> { + w: &'a mut W, +} +impl<'a> STARTEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `STARTINV` reader - Start Conversion Event Invert Enable"] +pub struct STARTINV_R(crate::FieldReader); +impl STARTINV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STARTINV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STARTINV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STARTINV` writer - Start Conversion Event Invert Enable"] +pub struct STARTINV_W<'a> { + w: &'a mut W, +} +impl<'a> STARTINV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WINEO` reader - Window Monitor Event Out"] +pub struct WINEO_R(crate::FieldReader); +impl WINEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINEO` writer - Window Monitor Event Out"] +pub struct WINEO_W<'a> { + w: &'a mut W, +} +impl<'a> WINEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Start Conversion Event Input Enable"] + #[inline(always)] + pub fn startei(&self) -> STARTEI_R { + STARTEI_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Start Conversion Event Invert Enable"] + #[inline(always)] + pub fn startinv(&self) -> STARTINV_R { + STARTINV_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Window Monitor Event Out"] + #[inline(always)] + pub fn wineo(&self) -> WINEO_R { + WINEO_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Start Conversion Event Input Enable"] + #[inline(always)] + pub fn startei(&mut self) -> STARTEI_W { + STARTEI_W { w: self } + } + #[doc = "Bit 1 - Start Conversion Event Invert Enable"] + #[inline(always)] + pub fn startinv(&mut self) -> STARTINV_W { + STARTINV_W { w: self } + } + #[doc = "Bit 2 - Window Monitor Event Out"] + #[inline(always)] + pub fn wineo(&mut self) -> WINEO_W { + WINEO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/tsens/gain.rs b/pac/atsamc21j/src/tsens/gain.rs new file mode 100644 index 000000000000..785bbef3b6a4 --- /dev/null +++ b/pac/atsamc21j/src/tsens/gain.rs @@ -0,0 +1,103 @@ +#[doc = "Register `GAIN` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GAIN` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `GAIN` reader - Time Amplifier Gain"] +pub struct GAIN_R(crate::FieldReader); +impl GAIN_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + GAIN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GAIN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GAIN` writer - Time Amplifier Gain"] +pub struct GAIN_W<'a> { + w: &'a mut W, +} +impl<'a> GAIN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Time Amplifier Gain"] + #[inline(always)] + pub fn gain(&self) -> GAIN_R { + GAIN_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Time Amplifier Gain"] + #[inline(always)] + pub fn gain(&mut self) -> GAIN_W { + GAIN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Gain Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gain](index.html) module"] +pub struct GAIN_SPEC; +impl crate::RegisterSpec for GAIN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gain::R](R) reader structure"] +impl crate::Readable for GAIN_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gain::W](W) writer structure"] +impl crate::Writable for GAIN_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets GAIN to value 0"] +impl crate::Resettable for GAIN_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/tsens/intenclr.rs b/pac/atsamc21j/src/tsens/intenclr.rs new file mode 100644 index 000000000000..2362cf7b512b --- /dev/null +++ b/pac/atsamc21j/src/tsens/intenclr.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RESRDY` reader - Result Ready Interrupt Enable"] +pub struct RESRDY_R(crate::FieldReader); +impl RESRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESRDY` writer - Result Ready Interrupt Enable"] +pub struct RESRDY_W<'a> { + w: &'a mut W, +} +impl<'a> RESRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `OVERRUN` reader - Overrun Interrupt Enable"] +pub struct OVERRUN_R(crate::FieldReader); +impl OVERRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVERRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVERRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVERRUN` writer - Overrun Interrupt Enable"] +pub struct OVERRUN_W<'a> { + w: &'a mut W, +} +impl<'a> OVERRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WINMON` reader - Window Monitor Interrupt Enable"] +pub struct WINMON_R(crate::FieldReader); +impl WINMON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINMON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINMON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMON` writer - Window Monitor Interrupt Enable"] +pub struct WINMON_W<'a> { + w: &'a mut W, +} +impl<'a> WINMON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +impl R { + #[doc = "Bit 0 - Result Ready Interrupt Enable"] + #[inline(always)] + pub fn resrdy(&self) -> RESRDY_R { + RESRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Overrun Interrupt Enable"] + #[inline(always)] + pub fn overrun(&self) -> OVERRUN_R { + OVERRUN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Window Monitor Interrupt Enable"] + #[inline(always)] + pub fn winmon(&self) -> WINMON_R { + WINMON_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 3) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Result Ready Interrupt Enable"] + #[inline(always)] + pub fn resrdy(&mut self) -> RESRDY_W { + RESRDY_W { w: self } + } + #[doc = "Bit 1 - Overrun Interrupt Enable"] + #[inline(always)] + pub fn overrun(&mut self) -> OVERRUN_W { + OVERRUN_W { w: self } + } + #[doc = "Bit 2 - Window Monitor Interrupt Enable"] + #[inline(always)] + pub fn winmon(&mut self) -> WINMON_W { + WINMON_W { w: self } + } + #[doc = "Bit 3 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/tsens/intenset.rs b/pac/atsamc21j/src/tsens/intenset.rs new file mode 100644 index 000000000000..51df8bb668f2 --- /dev/null +++ b/pac/atsamc21j/src/tsens/intenset.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RESRDY` reader - Result Ready Interrupt Enable"] +pub struct RESRDY_R(crate::FieldReader); +impl RESRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESRDY` writer - Result Ready Interrupt Enable"] +pub struct RESRDY_W<'a> { + w: &'a mut W, +} +impl<'a> RESRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `OVERRUN` reader - Overrun Interrupt Enable"] +pub struct OVERRUN_R(crate::FieldReader); +impl OVERRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVERRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVERRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVERRUN` writer - Overrun Interrupt Enable"] +pub struct OVERRUN_W<'a> { + w: &'a mut W, +} +impl<'a> OVERRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WINMON` reader - Window Monitor Interrupt Enable"] +pub struct WINMON_R(crate::FieldReader); +impl WINMON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINMON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINMON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMON` writer - Window Monitor Interrupt Enable"] +pub struct WINMON_W<'a> { + w: &'a mut W, +} +impl<'a> WINMON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +impl R { + #[doc = "Bit 0 - Result Ready Interrupt Enable"] + #[inline(always)] + pub fn resrdy(&self) -> RESRDY_R { + RESRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Overrun Interrupt Enable"] + #[inline(always)] + pub fn overrun(&self) -> OVERRUN_R { + OVERRUN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Window Monitor Interrupt Enable"] + #[inline(always)] + pub fn winmon(&self) -> WINMON_R { + WINMON_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 3) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Result Ready Interrupt Enable"] + #[inline(always)] + pub fn resrdy(&mut self) -> RESRDY_W { + RESRDY_W { w: self } + } + #[doc = "Bit 1 - Overrun Interrupt Enable"] + #[inline(always)] + pub fn overrun(&mut self) -> OVERRUN_W { + OVERRUN_W { w: self } + } + #[doc = "Bit 2 - Window Monitor Interrupt Enable"] + #[inline(always)] + pub fn winmon(&mut self) -> WINMON_W { + WINMON_W { w: self } + } + #[doc = "Bit 3 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/tsens/intflag.rs b/pac/atsamc21j/src/tsens/intflag.rs new file mode 100644 index 000000000000..5058a4f8712c --- /dev/null +++ b/pac/atsamc21j/src/tsens/intflag.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RESRDY` reader - Result Ready"] +pub struct RESRDY_R(crate::FieldReader); +impl RESRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESRDY` writer - Result Ready"] +pub struct RESRDY_W<'a> { + w: &'a mut W, +} +impl<'a> RESRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `OVERRUN` reader - Overrun"] +pub struct OVERRUN_R(crate::FieldReader); +impl OVERRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVERRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVERRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVERRUN` writer - Overrun"] +pub struct OVERRUN_W<'a> { + w: &'a mut W, +} +impl<'a> OVERRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WINMON` reader - Window Monitor"] +pub struct WINMON_R(crate::FieldReader); +impl WINMON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINMON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINMON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMON` writer - Window Monitor"] +pub struct WINMON_W<'a> { + w: &'a mut W, +} +impl<'a> WINMON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +impl R { + #[doc = "Bit 0 - Result Ready"] + #[inline(always)] + pub fn resrdy(&self) -> RESRDY_R { + RESRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Overrun"] + #[inline(always)] + pub fn overrun(&self) -> OVERRUN_R { + OVERRUN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Window Monitor"] + #[inline(always)] + pub fn winmon(&self) -> WINMON_R { + WINMON_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Overflow"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 3) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Result Ready"] + #[inline(always)] + pub fn resrdy(&mut self) -> RESRDY_W { + RESRDY_W { w: self } + } + #[doc = "Bit 1 - Overrun"] + #[inline(always)] + pub fn overrun(&mut self) -> OVERRUN_W { + OVERRUN_W { w: self } + } + #[doc = "Bit 2 - Window Monitor"] + #[inline(always)] + pub fn winmon(&mut self) -> WINMON_W { + WINMON_W { w: self } + } + #[doc = "Bit 3 - Overflow"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/tsens/offset.rs b/pac/atsamc21j/src/tsens/offset.rs new file mode 100644 index 000000000000..1796ac252c12 --- /dev/null +++ b/pac/atsamc21j/src/tsens/offset.rs @@ -0,0 +1,103 @@ +#[doc = "Register `OFFSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OFFSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OFFSETC` reader - Offset Correction"] +pub struct OFFSETC_R(crate::FieldReader); +impl OFFSETC_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + OFFSETC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OFFSETC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OFFSETC` writer - Offset Correction"] +pub struct OFFSETC_W<'a> { + w: &'a mut W, +} +impl<'a> OFFSETC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Offset Correction"] + #[inline(always)] + pub fn offsetc(&self) -> OFFSETC_R { + OFFSETC_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Offset Correction"] + #[inline(always)] + pub fn offsetc(&mut self) -> OFFSETC_W { + OFFSETC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Offset Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [offset](index.html) module"] +pub struct OFFSET_SPEC; +impl crate::RegisterSpec for OFFSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [offset::R](R) reader structure"] +impl crate::Readable for OFFSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [offset::W](W) writer structure"] +impl crate::Writable for OFFSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OFFSET to value 0"] +impl crate::Resettable for OFFSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/tsens/status.rs b/pac/atsamc21j/src/tsens/status.rs new file mode 100644 index 000000000000..42309f7dcb4c --- /dev/null +++ b/pac/atsamc21j/src/tsens/status.rs @@ -0,0 +1,53 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `OVF` reader - Result Overflow"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Result Overflow"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } +} +#[doc = "Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/tsens/syncbusy.rs b/pac/atsamc21j/src/tsens/syncbusy.rs new file mode 100644 index 000000000000..e4492e16ad3c --- /dev/null +++ b/pac/atsamc21j/src/tsens/syncbusy.rs @@ -0,0 +1,73 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - Enable Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +#[doc = "Synchronization Busy Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/tsens/value.rs b/pac/atsamc21j/src/tsens/value.rs new file mode 100644 index 000000000000..54232a992edf --- /dev/null +++ b/pac/atsamc21j/src/tsens/value.rs @@ -0,0 +1,53 @@ +#[doc = "Register `VALUE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `VALUE` reader - Measurement Value"] +pub struct VALUE_R(crate::FieldReader); +impl VALUE_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + VALUE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VALUE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:23 - Measurement Value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +#[doc = "Value Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [value](index.html) module"] +pub struct VALUE_SPEC; +impl crate::RegisterSpec for VALUE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [value::R](R) reader structure"] +impl crate::Readable for VALUE_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets VALUE to value 0"] +impl crate::Resettable for VALUE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/tsens/winlt.rs b/pac/atsamc21j/src/tsens/winlt.rs new file mode 100644 index 000000000000..85a1d01b4b34 --- /dev/null +++ b/pac/atsamc21j/src/tsens/winlt.rs @@ -0,0 +1,103 @@ +#[doc = "Register `WINLT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WINLT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WINLT` reader - Window Lower Threshold"] +pub struct WINLT_R(crate::FieldReader); +impl WINLT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + WINLT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINLT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINLT` writer - Window Lower Threshold"] +pub struct WINLT_W<'a> { + w: &'a mut W, +} +impl<'a> WINLT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Window Lower Threshold"] + #[inline(always)] + pub fn winlt(&self) -> WINLT_R { + WINLT_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Window Lower Threshold"] + #[inline(always)] + pub fn winlt(&mut self) -> WINLT_W { + WINLT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Window Monitor Lower Threshold Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [winlt](index.html) module"] +pub struct WINLT_SPEC; +impl crate::RegisterSpec for WINLT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [winlt::R](R) reader structure"] +impl crate::Readable for WINLT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [winlt::W](W) writer structure"] +impl crate::Writable for WINLT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WINLT to value 0"] +impl crate::Resettable for WINLT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/tsens/winut.rs b/pac/atsamc21j/src/tsens/winut.rs new file mode 100644 index 000000000000..7da0850f8e50 --- /dev/null +++ b/pac/atsamc21j/src/tsens/winut.rs @@ -0,0 +1,103 @@ +#[doc = "Register `WINUT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WINUT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WINUT` reader - Window Upper Threshold"] +pub struct WINUT_R(crate::FieldReader); +impl WINUT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + WINUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINUT` writer - Window Upper Threshold"] +pub struct WINUT_W<'a> { + w: &'a mut W, +} +impl<'a> WINUT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Window Upper Threshold"] + #[inline(always)] + pub fn winut(&self) -> WINUT_R { + WINUT_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Window Upper Threshold"] + #[inline(always)] + pub fn winut(&mut self) -> WINUT_W { + WINUT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Window Monitor Upper Threshold Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [winut](index.html) module"] +pub struct WINUT_SPEC; +impl crate::RegisterSpec for WINUT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [winut::R](R) reader structure"] +impl crate::Readable for WINUT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [winut::W](W) writer structure"] +impl crate::Writable for WINUT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WINUT to value 0"] +impl crate::Resettable for WINUT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/wdt.rs b/pac/atsamc21j/src/wdt.rs new file mode 100644 index 000000000000..22b5c2bb706f --- /dev/null +++ b/pac/atsamc21j/src/wdt.rs @@ -0,0 +1,54 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrla: crate::Reg, + #[doc = "0x01 - Configuration"] + pub config: crate::Reg, + #[doc = "0x02 - Early Warning Interrupt Control"] + pub ewctrl: crate::Reg, + _reserved3: [u8; 0x01], + #[doc = "0x04 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x05 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x06 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x08 - Synchronization Busy"] + pub syncbusy: crate::Reg, + #[doc = "0x0c - Clear"] + pub clear: crate::Reg, +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control"] +pub mod ctrla; +#[doc = "CONFIG register accessor: an alias for `Reg`"] +pub type CONFIG = crate::Reg; +#[doc = "Configuration"] +pub mod config; +#[doc = "EWCTRL register accessor: an alias for `Reg`"] +pub type EWCTRL = crate::Reg; +#[doc = "Early Warning Interrupt Control"] +pub mod ewctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Busy"] +pub mod syncbusy; +#[doc = "CLEAR register accessor: an alias for `Reg`"] +pub type CLEAR = crate::Reg; +#[doc = "Clear"] +pub mod clear; diff --git a/pac/atsamc21j/src/wdt/clear.rs b/pac/atsamc21j/src/wdt/clear.rs new file mode 100644 index 000000000000..61ee21f3246a --- /dev/null +++ b/pac/atsamc21j/src/wdt/clear.rs @@ -0,0 +1,85 @@ +#[doc = "Register `CLEAR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Watchdog Clear\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CLEAR_AW { + #[doc = "165: Clear Key"] + KEY = 165, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CLEAR_AW) -> Self { + variant as _ + } +} +#[doc = "Field `CLEAR` writer - Watchdog Clear"] +pub struct CLEAR_W<'a> { + w: &'a mut W, +} +impl<'a> CLEAR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CLEAR_AW) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Clear Key"] + #[inline(always)] + pub fn key(self) -> &'a mut W { + self.variant(CLEAR_AW::KEY) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl W { + #[doc = "Bits 0:7 - Watchdog Clear"] + #[inline(always)] + pub fn clear(&mut self) -> CLEAR_W { + CLEAR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Clear\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clear](index.html) module"] +pub struct CLEAR_SPEC; +impl crate::RegisterSpec for CLEAR_SPEC { + type Ux = u8; +} +#[doc = "`write(|w| ..)` method takes [clear::W](W) writer structure"] +impl crate::Writable for CLEAR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CLEAR to value 0"] +impl crate::Resettable for CLEAR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/wdt/config.rs b/pac/atsamc21j/src/wdt/config.rs new file mode 100644 index 000000000000..c90f062b01f0 --- /dev/null +++ b/pac/atsamc21j/src/wdt/config.rs @@ -0,0 +1,498 @@ +#[doc = "Register `CONFIG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CONFIG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Time-Out Period\n\nValue on reset: 11"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PER_A { + #[doc = "0: 8 clock cycles"] + CYC8 = 0, + #[doc = "1: 16 clock cycles"] + CYC16 = 1, + #[doc = "2: 32 clock cycles"] + CYC32 = 2, + #[doc = "3: 64 clock cycles"] + CYC64 = 3, + #[doc = "4: 128 clock cycles"] + CYC128 = 4, + #[doc = "5: 256 clock cycles"] + CYC256 = 5, + #[doc = "6: 512 clock cycles"] + CYC512 = 6, + #[doc = "7: 1024 clock cycles"] + CYC1024 = 7, + #[doc = "8: 2048 clock cycles"] + CYC2048 = 8, + #[doc = "9: 4096 clock cycles"] + CYC4096 = 9, + #[doc = "10: 8192 clock cycles"] + CYC8192 = 10, + #[doc = "11: 16384 clock cycles"] + CYC16384 = 11, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PER` reader - Time-Out Period"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PER_A::CYC8), + 1 => Some(PER_A::CYC16), + 2 => Some(PER_A::CYC32), + 3 => Some(PER_A::CYC64), + 4 => Some(PER_A::CYC128), + 5 => Some(PER_A::CYC256), + 6 => Some(PER_A::CYC512), + 7 => Some(PER_A::CYC1024), + 8 => Some(PER_A::CYC2048), + 9 => Some(PER_A::CYC4096), + 10 => Some(PER_A::CYC8192), + 11 => Some(PER_A::CYC16384), + _ => None, + } + } + #[doc = "Checks if the value of the field is `CYC8`"] + #[inline(always)] + pub fn is_cyc8(&self) -> bool { + **self == PER_A::CYC8 + } + #[doc = "Checks if the value of the field is `CYC16`"] + #[inline(always)] + pub fn is_cyc16(&self) -> bool { + **self == PER_A::CYC16 + } + #[doc = "Checks if the value of the field is `CYC32`"] + #[inline(always)] + pub fn is_cyc32(&self) -> bool { + **self == PER_A::CYC32 + } + #[doc = "Checks if the value of the field is `CYC64`"] + #[inline(always)] + pub fn is_cyc64(&self) -> bool { + **self == PER_A::CYC64 + } + #[doc = "Checks if the value of the field is `CYC128`"] + #[inline(always)] + pub fn is_cyc128(&self) -> bool { + **self == PER_A::CYC128 + } + #[doc = "Checks if the value of the field is `CYC256`"] + #[inline(always)] + pub fn is_cyc256(&self) -> bool { + **self == PER_A::CYC256 + } + #[doc = "Checks if the value of the field is `CYC512`"] + #[inline(always)] + pub fn is_cyc512(&self) -> bool { + **self == PER_A::CYC512 + } + #[doc = "Checks if the value of the field is `CYC1024`"] + #[inline(always)] + pub fn is_cyc1024(&self) -> bool { + **self == PER_A::CYC1024 + } + #[doc = "Checks if the value of the field is `CYC2048`"] + #[inline(always)] + pub fn is_cyc2048(&self) -> bool { + **self == PER_A::CYC2048 + } + #[doc = "Checks if the value of the field is `CYC4096`"] + #[inline(always)] + pub fn is_cyc4096(&self) -> bool { + **self == PER_A::CYC4096 + } + #[doc = "Checks if the value of the field is `CYC8192`"] + #[inline(always)] + pub fn is_cyc8192(&self) -> bool { + **self == PER_A::CYC8192 + } + #[doc = "Checks if the value of the field is `CYC16384`"] + #[inline(always)] + pub fn is_cyc16384(&self) -> bool { + **self == PER_A::CYC16384 + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` writer - Time-Out Period"] +pub struct PER_W<'a> { + w: &'a mut W, +} +impl<'a> PER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PER_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8 clock cycles"] + #[inline(always)] + pub fn cyc8(self) -> &'a mut W { + self.variant(PER_A::CYC8) + } + #[doc = "16 clock cycles"] + #[inline(always)] + pub fn cyc16(self) -> &'a mut W { + self.variant(PER_A::CYC16) + } + #[doc = "32 clock cycles"] + #[inline(always)] + pub fn cyc32(self) -> &'a mut W { + self.variant(PER_A::CYC32) + } + #[doc = "64 clock cycles"] + #[inline(always)] + pub fn cyc64(self) -> &'a mut W { + self.variant(PER_A::CYC64) + } + #[doc = "128 clock cycles"] + #[inline(always)] + pub fn cyc128(self) -> &'a mut W { + self.variant(PER_A::CYC128) + } + #[doc = "256 clock cycles"] + #[inline(always)] + pub fn cyc256(self) -> &'a mut W { + self.variant(PER_A::CYC256) + } + #[doc = "512 clock cycles"] + #[inline(always)] + pub fn cyc512(self) -> &'a mut W { + self.variant(PER_A::CYC512) + } + #[doc = "1024 clock cycles"] + #[inline(always)] + pub fn cyc1024(self) -> &'a mut W { + self.variant(PER_A::CYC1024) + } + #[doc = "2048 clock cycles"] + #[inline(always)] + pub fn cyc2048(self) -> &'a mut W { + self.variant(PER_A::CYC2048) + } + #[doc = "4096 clock cycles"] + #[inline(always)] + pub fn cyc4096(self) -> &'a mut W { + self.variant(PER_A::CYC4096) + } + #[doc = "8192 clock cycles"] + #[inline(always)] + pub fn cyc8192(self) -> &'a mut W { + self.variant(PER_A::CYC8192) + } + #[doc = "16384 clock cycles"] + #[inline(always)] + pub fn cyc16384(self) -> &'a mut W { + self.variant(PER_A::CYC16384) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +#[doc = "Window Mode Time-Out Period\n\nValue on reset: 11"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WINDOW_A { + #[doc = "0: 8 clock cycles"] + CYC8 = 0, + #[doc = "1: 16 clock cycles"] + CYC16 = 1, + #[doc = "2: 32 clock cycles"] + CYC32 = 2, + #[doc = "3: 64 clock cycles"] + CYC64 = 3, + #[doc = "4: 128 clock cycles"] + CYC128 = 4, + #[doc = "5: 256 clock cycles"] + CYC256 = 5, + #[doc = "6: 512 clock cycles"] + CYC512 = 6, + #[doc = "7: 1024 clock cycles"] + CYC1024 = 7, + #[doc = "8: 2048 clock cycles"] + CYC2048 = 8, + #[doc = "9: 4096 clock cycles"] + CYC4096 = 9, + #[doc = "10: 8192 clock cycles"] + CYC8192 = 10, + #[doc = "11: 16384 clock cycles"] + CYC16384 = 11, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WINDOW_A) -> Self { + variant as _ + } +} +#[doc = "Field `WINDOW` reader - Window Mode Time-Out Period"] +pub struct WINDOW_R(crate::FieldReader); +impl WINDOW_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WINDOW_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(WINDOW_A::CYC8), + 1 => Some(WINDOW_A::CYC16), + 2 => Some(WINDOW_A::CYC32), + 3 => Some(WINDOW_A::CYC64), + 4 => Some(WINDOW_A::CYC128), + 5 => Some(WINDOW_A::CYC256), + 6 => Some(WINDOW_A::CYC512), + 7 => Some(WINDOW_A::CYC1024), + 8 => Some(WINDOW_A::CYC2048), + 9 => Some(WINDOW_A::CYC4096), + 10 => Some(WINDOW_A::CYC8192), + 11 => Some(WINDOW_A::CYC16384), + _ => None, + } + } + #[doc = "Checks if the value of the field is `CYC8`"] + #[inline(always)] + pub fn is_cyc8(&self) -> bool { + **self == WINDOW_A::CYC8 + } + #[doc = "Checks if the value of the field is `CYC16`"] + #[inline(always)] + pub fn is_cyc16(&self) -> bool { + **self == WINDOW_A::CYC16 + } + #[doc = "Checks if the value of the field is `CYC32`"] + #[inline(always)] + pub fn is_cyc32(&self) -> bool { + **self == WINDOW_A::CYC32 + } + #[doc = "Checks if the value of the field is `CYC64`"] + #[inline(always)] + pub fn is_cyc64(&self) -> bool { + **self == WINDOW_A::CYC64 + } + #[doc = "Checks if the value of the field is `CYC128`"] + #[inline(always)] + pub fn is_cyc128(&self) -> bool { + **self == WINDOW_A::CYC128 + } + #[doc = "Checks if the value of the field is `CYC256`"] + #[inline(always)] + pub fn is_cyc256(&self) -> bool { + **self == WINDOW_A::CYC256 + } + #[doc = "Checks if the value of the field is `CYC512`"] + #[inline(always)] + pub fn is_cyc512(&self) -> bool { + **self == WINDOW_A::CYC512 + } + #[doc = "Checks if the value of the field is `CYC1024`"] + #[inline(always)] + pub fn is_cyc1024(&self) -> bool { + **self == WINDOW_A::CYC1024 + } + #[doc = "Checks if the value of the field is `CYC2048`"] + #[inline(always)] + pub fn is_cyc2048(&self) -> bool { + **self == WINDOW_A::CYC2048 + } + #[doc = "Checks if the value of the field is `CYC4096`"] + #[inline(always)] + pub fn is_cyc4096(&self) -> bool { + **self == WINDOW_A::CYC4096 + } + #[doc = "Checks if the value of the field is `CYC8192`"] + #[inline(always)] + pub fn is_cyc8192(&self) -> bool { + **self == WINDOW_A::CYC8192 + } + #[doc = "Checks if the value of the field is `CYC16384`"] + #[inline(always)] + pub fn is_cyc16384(&self) -> bool { + **self == WINDOW_A::CYC16384 + } +} +impl core::ops::Deref for WINDOW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINDOW` writer - Window Mode Time-Out Period"] +pub struct WINDOW_W<'a> { + w: &'a mut W, +} +impl<'a> WINDOW_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WINDOW_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8 clock cycles"] + #[inline(always)] + pub fn cyc8(self) -> &'a mut W { + self.variant(WINDOW_A::CYC8) + } + #[doc = "16 clock cycles"] + #[inline(always)] + pub fn cyc16(self) -> &'a mut W { + self.variant(WINDOW_A::CYC16) + } + #[doc = "32 clock cycles"] + #[inline(always)] + pub fn cyc32(self) -> &'a mut W { + self.variant(WINDOW_A::CYC32) + } + #[doc = "64 clock cycles"] + #[inline(always)] + pub fn cyc64(self) -> &'a mut W { + self.variant(WINDOW_A::CYC64) + } + #[doc = "128 clock cycles"] + #[inline(always)] + pub fn cyc128(self) -> &'a mut W { + self.variant(WINDOW_A::CYC128) + } + #[doc = "256 clock cycles"] + #[inline(always)] + pub fn cyc256(self) -> &'a mut W { + self.variant(WINDOW_A::CYC256) + } + #[doc = "512 clock cycles"] + #[inline(always)] + pub fn cyc512(self) -> &'a mut W { + self.variant(WINDOW_A::CYC512) + } + #[doc = "1024 clock cycles"] + #[inline(always)] + pub fn cyc1024(self) -> &'a mut W { + self.variant(WINDOW_A::CYC1024) + } + #[doc = "2048 clock cycles"] + #[inline(always)] + pub fn cyc2048(self) -> &'a mut W { + self.variant(WINDOW_A::CYC2048) + } + #[doc = "4096 clock cycles"] + #[inline(always)] + pub fn cyc4096(self) -> &'a mut W { + self.variant(WINDOW_A::CYC4096) + } + #[doc = "8192 clock cycles"] + #[inline(always)] + pub fn cyc8192(self) -> &'a mut W { + self.variant(WINDOW_A::CYC8192) + } + #[doc = "16384 clock cycles"] + #[inline(always)] + pub fn cyc16384(self) -> &'a mut W { + self.variant(WINDOW_A::CYC16384) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 4)) | ((value as u8 & 0x0f) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Time-Out Period"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Window Mode Time-Out Period"] + #[inline(always)] + pub fn window(&self) -> WINDOW_R { + WINDOW_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Time-Out Period"] + #[inline(always)] + pub fn per(&mut self) -> PER_W { + PER_W { w: self } + } + #[doc = "Bits 4:7 - Window Mode Time-Out Period"] + #[inline(always)] + pub fn window(&mut self) -> WINDOW_W { + WINDOW_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [config](index.html) module"] +pub struct CONFIG_SPEC; +impl crate::RegisterSpec for CONFIG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [config::R](R) reader structure"] +impl crate::Readable for CONFIG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [config::W](W) writer structure"] +impl crate::Writable for CONFIG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CONFIG to value 0xbb"] +impl crate::Resettable for CONFIG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xbb + } +} diff --git a/pac/atsamc21j/src/wdt/ctrla.rs b/pac/atsamc21j/src/wdt/ctrla.rs new file mode 100644 index 000000000000..895169d36aeb --- /dev/null +++ b/pac/atsamc21j/src/wdt/ctrla.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WEN` reader - Watchdog Timer Window Mode Enable"] +pub struct WEN_R(crate::FieldReader); +impl WEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WEN` writer - Watchdog Timer Window Mode Enable"] +pub struct WEN_W<'a> { + w: &'a mut W, +} +impl<'a> WEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `ALWAYSON` reader - Always-On"] +pub struct ALWAYSON_R(crate::FieldReader); +impl ALWAYSON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALWAYSON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALWAYSON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALWAYSON` writer - Always-On"] +pub struct ALWAYSON_W<'a> { + w: &'a mut W, +} +impl<'a> ALWAYSON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Watchdog Timer Window Mode Enable"] + #[inline(always)] + pub fn wen(&self) -> WEN_R { + WEN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 7 - Always-On"] + #[inline(always)] + pub fn alwayson(&self) -> ALWAYSON_R { + ALWAYSON_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - Watchdog Timer Window Mode Enable"] + #[inline(always)] + pub fn wen(&mut self) -> WEN_W { + WEN_W { w: self } + } + #[doc = "Bit 7 - Always-On"] + #[inline(always)] + pub fn alwayson(&mut self) -> ALWAYSON_W { + ALWAYSON_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/wdt/ewctrl.rs b/pac/atsamc21j/src/wdt/ewctrl.rs new file mode 100644 index 000000000000..94542e9897a9 --- /dev/null +++ b/pac/atsamc21j/src/wdt/ewctrl.rs @@ -0,0 +1,282 @@ +#[doc = "Register `EWCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EWCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Early Warning Interrupt Time Offset\n\nValue on reset: 11"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EWOFFSET_A { + #[doc = "0: 8 clock cycles"] + CYC8 = 0, + #[doc = "1: 16 clock cycles"] + CYC16 = 1, + #[doc = "2: 32 clock cycles"] + CYC32 = 2, + #[doc = "3: 64 clock cycles"] + CYC64 = 3, + #[doc = "4: 128 clock cycles"] + CYC128 = 4, + #[doc = "5: 256 clock cycles"] + CYC256 = 5, + #[doc = "6: 512 clock cycles"] + CYC512 = 6, + #[doc = "7: 1024 clock cycles"] + CYC1024 = 7, + #[doc = "8: 2048 clock cycles"] + CYC2048 = 8, + #[doc = "9: 4096 clock cycles"] + CYC4096 = 9, + #[doc = "10: 8192 clock cycles"] + CYC8192 = 10, + #[doc = "11: 16384 clock cycles"] + CYC16384 = 11, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EWOFFSET_A) -> Self { + variant as _ + } +} +#[doc = "Field `EWOFFSET` reader - Early Warning Interrupt Time Offset"] +pub struct EWOFFSET_R(crate::FieldReader); +impl EWOFFSET_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EWOFFSET_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(EWOFFSET_A::CYC8), + 1 => Some(EWOFFSET_A::CYC16), + 2 => Some(EWOFFSET_A::CYC32), + 3 => Some(EWOFFSET_A::CYC64), + 4 => Some(EWOFFSET_A::CYC128), + 5 => Some(EWOFFSET_A::CYC256), + 6 => Some(EWOFFSET_A::CYC512), + 7 => Some(EWOFFSET_A::CYC1024), + 8 => Some(EWOFFSET_A::CYC2048), + 9 => Some(EWOFFSET_A::CYC4096), + 10 => Some(EWOFFSET_A::CYC8192), + 11 => Some(EWOFFSET_A::CYC16384), + _ => None, + } + } + #[doc = "Checks if the value of the field is `CYC8`"] + #[inline(always)] + pub fn is_cyc8(&self) -> bool { + **self == EWOFFSET_A::CYC8 + } + #[doc = "Checks if the value of the field is `CYC16`"] + #[inline(always)] + pub fn is_cyc16(&self) -> bool { + **self == EWOFFSET_A::CYC16 + } + #[doc = "Checks if the value of the field is `CYC32`"] + #[inline(always)] + pub fn is_cyc32(&self) -> bool { + **self == EWOFFSET_A::CYC32 + } + #[doc = "Checks if the value of the field is `CYC64`"] + #[inline(always)] + pub fn is_cyc64(&self) -> bool { + **self == EWOFFSET_A::CYC64 + } + #[doc = "Checks if the value of the field is `CYC128`"] + #[inline(always)] + pub fn is_cyc128(&self) -> bool { + **self == EWOFFSET_A::CYC128 + } + #[doc = "Checks if the value of the field is `CYC256`"] + #[inline(always)] + pub fn is_cyc256(&self) -> bool { + **self == EWOFFSET_A::CYC256 + } + #[doc = "Checks if the value of the field is `CYC512`"] + #[inline(always)] + pub fn is_cyc512(&self) -> bool { + **self == EWOFFSET_A::CYC512 + } + #[doc = "Checks if the value of the field is `CYC1024`"] + #[inline(always)] + pub fn is_cyc1024(&self) -> bool { + **self == EWOFFSET_A::CYC1024 + } + #[doc = "Checks if the value of the field is `CYC2048`"] + #[inline(always)] + pub fn is_cyc2048(&self) -> bool { + **self == EWOFFSET_A::CYC2048 + } + #[doc = "Checks if the value of the field is `CYC4096`"] + #[inline(always)] + pub fn is_cyc4096(&self) -> bool { + **self == EWOFFSET_A::CYC4096 + } + #[doc = "Checks if the value of the field is `CYC8192`"] + #[inline(always)] + pub fn is_cyc8192(&self) -> bool { + **self == EWOFFSET_A::CYC8192 + } + #[doc = "Checks if the value of the field is `CYC16384`"] + #[inline(always)] + pub fn is_cyc16384(&self) -> bool { + **self == EWOFFSET_A::CYC16384 + } +} +impl core::ops::Deref for EWOFFSET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EWOFFSET` writer - Early Warning Interrupt Time Offset"] +pub struct EWOFFSET_W<'a> { + w: &'a mut W, +} +impl<'a> EWOFFSET_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EWOFFSET_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8 clock cycles"] + #[inline(always)] + pub fn cyc8(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC8) + } + #[doc = "16 clock cycles"] + #[inline(always)] + pub fn cyc16(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC16) + } + #[doc = "32 clock cycles"] + #[inline(always)] + pub fn cyc32(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC32) + } + #[doc = "64 clock cycles"] + #[inline(always)] + pub fn cyc64(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC64) + } + #[doc = "128 clock cycles"] + #[inline(always)] + pub fn cyc128(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC128) + } + #[doc = "256 clock cycles"] + #[inline(always)] + pub fn cyc256(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC256) + } + #[doc = "512 clock cycles"] + #[inline(always)] + pub fn cyc512(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC512) + } + #[doc = "1024 clock cycles"] + #[inline(always)] + pub fn cyc1024(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC1024) + } + #[doc = "2048 clock cycles"] + #[inline(always)] + pub fn cyc2048(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC2048) + } + #[doc = "4096 clock cycles"] + #[inline(always)] + pub fn cyc4096(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC4096) + } + #[doc = "8192 clock cycles"] + #[inline(always)] + pub fn cyc8192(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC8192) + } + #[doc = "16384 clock cycles"] + #[inline(always)] + pub fn cyc16384(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC16384) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Early Warning Interrupt Time Offset"] + #[inline(always)] + pub fn ewoffset(&self) -> EWOFFSET_R { + EWOFFSET_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Early Warning Interrupt Time Offset"] + #[inline(always)] + pub fn ewoffset(&mut self) -> EWOFFSET_W { + EWOFFSET_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Early Warning Interrupt Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ewctrl](index.html) module"] +pub struct EWCTRL_SPEC; +impl crate::RegisterSpec for EWCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ewctrl::R](R) reader structure"] +impl crate::Readable for EWCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ewctrl::W](W) writer structure"] +impl crate::Writable for EWCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EWCTRL to value 0x0b"] +impl crate::Resettable for EWCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0b + } +} diff --git a/pac/atsamc21j/src/wdt/intenclr.rs b/pac/atsamc21j/src/wdt/intenclr.rs new file mode 100644 index 000000000000..ed4021f96cce --- /dev/null +++ b/pac/atsamc21j/src/wdt/intenclr.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EW` reader - Early Warning Interrupt Enable"] +pub struct EW_R(crate::FieldReader); +impl EW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EW` writer - Early Warning Interrupt Enable"] +pub struct EW_W<'a> { + w: &'a mut W, +} +impl<'a> EW_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Early Warning Interrupt Enable"] + #[inline(always)] + pub fn ew(&self) -> EW_R { + EW_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Early Warning Interrupt Enable"] + #[inline(always)] + pub fn ew(&mut self) -> EW_W { + EW_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/wdt/intenset.rs b/pac/atsamc21j/src/wdt/intenset.rs new file mode 100644 index 000000000000..5a0928ff0532 --- /dev/null +++ b/pac/atsamc21j/src/wdt/intenset.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EW` reader - Early Warning Interrupt Enable"] +pub struct EW_R(crate::FieldReader); +impl EW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EW` writer - Early Warning Interrupt Enable"] +pub struct EW_W<'a> { + w: &'a mut W, +} +impl<'a> EW_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Early Warning Interrupt Enable"] + #[inline(always)] + pub fn ew(&self) -> EW_R { + EW_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Early Warning Interrupt Enable"] + #[inline(always)] + pub fn ew(&mut self) -> EW_W { + EW_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/wdt/intflag.rs b/pac/atsamc21j/src/wdt/intflag.rs new file mode 100644 index 000000000000..f2c9b858a199 --- /dev/null +++ b/pac/atsamc21j/src/wdt/intflag.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EW` reader - Early Warning"] +pub struct EW_R(crate::FieldReader); +impl EW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EW` writer - Early Warning"] +pub struct EW_W<'a> { + w: &'a mut W, +} +impl<'a> EW_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Early Warning"] + #[inline(always)] + pub fn ew(&self) -> EW_R { + EW_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Early Warning"] + #[inline(always)] + pub fn ew(&mut self) -> EW_W { + EW_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21j/src/wdt/syncbusy.rs b/pac/atsamc21j/src/wdt/syncbusy.rs new file mode 100644 index 000000000000..a3ecf7fbdb8a --- /dev/null +++ b/pac/atsamc21j/src/wdt/syncbusy.rs @@ -0,0 +1,113 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `ENABLE` reader - Enable Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WEN` reader - Window Enable Busy"] +pub struct WEN_R(crate::FieldReader); +impl WEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALWAYSON` reader - Always-On Busy"] +pub struct ALWAYSON_R(crate::FieldReader); +impl ALWAYSON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALWAYSON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALWAYSON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLEAR` reader - Clear Busy"] +pub struct CLEAR_R(crate::FieldReader); +impl CLEAR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLEAR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLEAR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 1 - Enable Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Window Enable Busy"] + #[inline(always)] + pub fn wen(&self) -> WEN_R { + WEN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Always-On Busy"] + #[inline(always)] + pub fn alwayson(&self) -> ALWAYSON_R { + ALWAYSON_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Clear Busy"] + #[inline(always)] + pub fn clear(&self) -> CLEAR_R { + CLEAR_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +#[doc = "Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/CHANGELOG.md b/pac/atsamc21n/CHANGELOG.md new file mode 100644 index 000000000000..e28d85f63b31 --- /dev/null +++ b/pac/atsamc21n/CHANGELOG.md @@ -0,0 +1,6 @@ +# Unreleased + +- Initial version +--- + +Changelog tracking started at v0.0.1 diff --git a/pac/atsamc21n/Cargo.toml b/pac/atsamc21n/Cargo.toml new file mode 100644 index 000000000000..14a66cb3f843 --- /dev/null +++ b/pac/atsamc21n/Cargo.toml @@ -0,0 +1,22 @@ +[package] +name = "atsamc21n" +description = "Peripheral access API for ATSAMC21N microcontrollers (generated using svd2rust)" +version = "0.0.1" +authors = ["Jeremy Boynes "] +keywords = ["no-std", "arm", "cortex-m"] +categories = ["embedded", "hardware-support", "no-std"] +license = "MIT OR Apache-2.0" +repository = "https://github.com/atsamd-rs/atsamd" +readme = "README.md" +edition = "2021" + +[dependencies] +cortex-m = "0.7" +vcell = "0.1" + +[dependencies.cortex-m-rt] +version = "0.7" +optional = true + +[features] +rt = ["cortex-m-rt/device"] diff --git a/pac/atsamc21n/README.md b/pac/atsamc21n/README.md new file mode 100644 index 000000000000..92afab825302 --- /dev/null +++ b/pac/atsamc21n/README.md @@ -0,0 +1,26 @@ +# ATSAMC21N + +A peripheral access crate for the ATSAMC21N chip from Microchip (née Atmel) for Rust Embedded projects. + +[![Build Status](https://travis-ci.org/atsamd-rs/atsamd.svg?branch=master)](https://travis-ci.org/atsamd-rs/atsamd) +[![Crates.io](https://img.shields.io/crates/v/atsamc21n.svg)](https://crates.io/crates/atsamc21n) + +## [Documentation](https://docs.rs/atsamc21n) + +This source was automatically generated using `svd2rust`, split into smaller pieces using `form` and formatted via `rustfmt`. + +## License + +Licensed under either of: + +- Apache License, Version 2.0 ([LICENSE-APACHE](https://github.com/atsamd-rs/atsamd/blob/master/LICENSE-APACHE) or + http://www.apache.org/licenses/LICENSE-2.0) +- MIT license ([LICENSE-MIT](https://github.com/atsamd-rs/atsamd/blob/master/LICENSE-MIT) or http://opensource.org/licenses/MIT) + +at your option. + +### Contribution + +Unless you explicitly state otherwise, any contribution intentionally submitted +for inclusion in the work by you, as defined in the Apache-2.0 license, shall +be dual licensed as above, without any additional terms or conditions. diff --git a/pac/atsamc21n/build.rs b/pac/atsamc21n/build.rs new file mode 100644 index 000000000000..597923f50892 --- /dev/null +++ b/pac/atsamc21n/build.rs @@ -0,0 +1,16 @@ +use std::env; +use std::fs::File; +use std::io::Write; +use std::path::PathBuf; +fn main() { + if env::var_os("CARGO_FEATURE_RT").is_some() { + let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap()); + File::create(out.join("device.x")) + .unwrap() + .write_all(include_bytes!("device.x")) + .unwrap(); + println!("cargo:rustc-link-search={}", out.display()); + println!("cargo:rerun-if-changed=device.x"); + } + println!("cargo:rerun-if-changed=build.rs"); +} diff --git a/pac/atsamc21n/device.x b/pac/atsamc21n/device.x new file mode 100644 index 000000000000..c89e27739ac7 --- /dev/null +++ b/pac/atsamc21n/device.x @@ -0,0 +1,26 @@ +PROVIDE(WDT = DefaultHandler); +PROVIDE(RTC = DefaultHandler); +PROVIDE(EIC = DefaultHandler); +PROVIDE(FREQM = DefaultHandler); +PROVIDE(TSENS = DefaultHandler); +PROVIDE(NVMCTRL = DefaultHandler); +PROVIDE(DMAC = DefaultHandler); +PROVIDE(EVSYS = DefaultHandler); +PROVIDE(SERCOM2 = DefaultHandler); +PROVIDE(SERCOM3 = DefaultHandler); +PROVIDE(SERCOM4 = DefaultHandler); +PROVIDE(SERCOM5 = DefaultHandler); +PROVIDE(CAN0 = DefaultHandler); +PROVIDE(CAN1 = DefaultHandler); +PROVIDE(TCC0 = DefaultHandler); +PROVIDE(TCC1 = DefaultHandler); +PROVIDE(TCC2 = DefaultHandler); +PROVIDE(TC3 = DefaultHandler); +PROVIDE(TC4 = DefaultHandler); +PROVIDE(ADC0 = DefaultHandler); +PROVIDE(ADC1 = DefaultHandler); +PROVIDE(AC = DefaultHandler); +PROVIDE(DAC = DefaultHandler); +PROVIDE(SDADC = DefaultHandler); +PROVIDE(PTC = DefaultHandler); + diff --git a/pac/atsamc21n/src/ac.rs b/pac/atsamc21n/src/ac.rs new file mode 100644 index 000000000000..b66620475572 --- /dev/null +++ b/pac/atsamc21n/src/ac.rs @@ -0,0 +1,83 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + #[doc = "0x01 - Control B"] + pub ctrlb: crate::Reg, + #[doc = "0x02 - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x04 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x05 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x06 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x07 - Status A"] + pub statusa: crate::Reg, + #[doc = "0x08 - Status B"] + pub statusb: crate::Reg, + #[doc = "0x09 - Debug Control"] + pub dbgctrl: crate::Reg, + #[doc = "0x0a - Window Control"] + pub winctrl: crate::Reg, + _reserved10: [u8; 0x01], + #[doc = "0x0c - Scaler n"] + pub scaler: [crate::Reg; 4], + #[doc = "0x10..0x20 - Comparator Control n"] + pub compctrl: [crate::Reg; 4], + #[doc = "0x20 - Synchronization Busy"] + pub syncbusy: crate::Reg, +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "Control B"] +pub mod ctrlb; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUSA register accessor: an alias for `Reg`"] +pub type STATUSA = crate::Reg; +#[doc = "Status A"] +pub mod statusa; +#[doc = "STATUSB register accessor: an alias for `Reg`"] +pub type STATUSB = crate::Reg; +#[doc = "Status B"] +pub mod statusb; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "WINCTRL register accessor: an alias for `Reg`"] +pub type WINCTRL = crate::Reg; +#[doc = "Window Control"] +pub mod winctrl; +#[doc = "SCALER register accessor: an alias for `Reg`"] +pub type SCALER = crate::Reg; +#[doc = "Scaler n"] +pub mod scaler; +#[doc = "COMPCTRL register accessor: an alias for `Reg`"] +pub type COMPCTRL = crate::Reg; +#[doc = "Comparator Control n"] +pub mod compctrl; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Busy"] +pub mod syncbusy; diff --git a/pac/atsamc21n/src/ac/compctrl.rs b/pac/atsamc21n/src/ac/compctrl.rs new file mode 100644 index 000000000000..791525fd7407 --- /dev/null +++ b/pac/atsamc21n/src/ac/compctrl.rs @@ -0,0 +1,987 @@ +#[doc = "Register `COMPCTRL[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COMPCTRL[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SINGLE` reader - Single-Shot Mode"] +pub struct SINGLE_R(crate::FieldReader); +impl SINGLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SINGLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SINGLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SINGLE` writer - Single-Shot Mode"] +pub struct SINGLE_W<'a> { + w: &'a mut W, +} +impl<'a> SINGLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Interrupt Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum INTSEL_A { + #[doc = "0: Interrupt on comparator output toggle"] + TOGGLE = 0, + #[doc = "1: Interrupt on comparator output rising"] + RISING = 1, + #[doc = "2: Interrupt on comparator output falling"] + FALLING = 2, + #[doc = "3: Interrupt on end of comparison (single-shot mode only)"] + EOC = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: INTSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `INTSEL` reader - Interrupt Selection"] +pub struct INTSEL_R(crate::FieldReader); +impl INTSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + INTSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INTSEL_A { + match self.bits { + 0 => INTSEL_A::TOGGLE, + 1 => INTSEL_A::RISING, + 2 => INTSEL_A::FALLING, + 3 => INTSEL_A::EOC, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `TOGGLE`"] + #[inline(always)] + pub fn is_toggle(&self) -> bool { + **self == INTSEL_A::TOGGLE + } + #[doc = "Checks if the value of the field is `RISING`"] + #[inline(always)] + pub fn is_rising(&self) -> bool { + **self == INTSEL_A::RISING + } + #[doc = "Checks if the value of the field is `FALLING`"] + #[inline(always)] + pub fn is_falling(&self) -> bool { + **self == INTSEL_A::FALLING + } + #[doc = "Checks if the value of the field is `EOC`"] + #[inline(always)] + pub fn is_eoc(&self) -> bool { + **self == INTSEL_A::EOC + } +} +impl core::ops::Deref for INTSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INTSEL` writer - Interrupt Selection"] +pub struct INTSEL_W<'a> { + w: &'a mut W, +} +impl<'a> INTSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: INTSEL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Interrupt on comparator output toggle"] + #[inline(always)] + pub fn toggle(self) -> &'a mut W { + self.variant(INTSEL_A::TOGGLE) + } + #[doc = "Interrupt on comparator output rising"] + #[inline(always)] + pub fn rising(self) -> &'a mut W { + self.variant(INTSEL_A::RISING) + } + #[doc = "Interrupt on comparator output falling"] + #[inline(always)] + pub fn falling(self) -> &'a mut W { + self.variant(INTSEL_A::FALLING) + } + #[doc = "Interrupt on end of comparison (single-shot mode only)"] + #[inline(always)] + pub fn eoc(self) -> &'a mut W { + self.variant(INTSEL_A::EOC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 3)) | ((value as u32 & 0x03) << 3); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Negative Input Mux Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MUXNEG_A { + #[doc = "0: I/O pin 0"] + PIN0 = 0, + #[doc = "1: I/O pin 1"] + PIN1 = 1, + #[doc = "2: I/O pin 2"] + PIN2 = 2, + #[doc = "3: I/O pin 3"] + PIN3 = 3, + #[doc = "4: Ground"] + GND = 4, + #[doc = "5: VDD scaler"] + VSCALE = 5, + #[doc = "6: Internal bandgap voltage"] + BANDGAP = 6, + #[doc = "7: DAC output"] + DAC = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MUXNEG_A) -> Self { + variant as _ + } +} +#[doc = "Field `MUXNEG` reader - Negative Input Mux Selection"] +pub struct MUXNEG_R(crate::FieldReader); +impl MUXNEG_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MUXNEG_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> MUXNEG_A { + match self.bits { + 0 => MUXNEG_A::PIN0, + 1 => MUXNEG_A::PIN1, + 2 => MUXNEG_A::PIN2, + 3 => MUXNEG_A::PIN3, + 4 => MUXNEG_A::GND, + 5 => MUXNEG_A::VSCALE, + 6 => MUXNEG_A::BANDGAP, + 7 => MUXNEG_A::DAC, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `PIN0`"] + #[inline(always)] + pub fn is_pin0(&self) -> bool { + **self == MUXNEG_A::PIN0 + } + #[doc = "Checks if the value of the field is `PIN1`"] + #[inline(always)] + pub fn is_pin1(&self) -> bool { + **self == MUXNEG_A::PIN1 + } + #[doc = "Checks if the value of the field is `PIN2`"] + #[inline(always)] + pub fn is_pin2(&self) -> bool { + **self == MUXNEG_A::PIN2 + } + #[doc = "Checks if the value of the field is `PIN3`"] + #[inline(always)] + pub fn is_pin3(&self) -> bool { + **self == MUXNEG_A::PIN3 + } + #[doc = "Checks if the value of the field is `GND`"] + #[inline(always)] + pub fn is_gnd(&self) -> bool { + **self == MUXNEG_A::GND + } + #[doc = "Checks if the value of the field is `VSCALE`"] + #[inline(always)] + pub fn is_vscale(&self) -> bool { + **self == MUXNEG_A::VSCALE + } + #[doc = "Checks if the value of the field is `BANDGAP`"] + #[inline(always)] + pub fn is_bandgap(&self) -> bool { + **self == MUXNEG_A::BANDGAP + } + #[doc = "Checks if the value of the field is `DAC`"] + #[inline(always)] + pub fn is_dac(&self) -> bool { + **self == MUXNEG_A::DAC + } +} +impl core::ops::Deref for MUXNEG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MUXNEG` writer - Negative Input Mux Selection"] +pub struct MUXNEG_W<'a> { + w: &'a mut W, +} +impl<'a> MUXNEG_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MUXNEG_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "I/O pin 0"] + #[inline(always)] + pub fn pin0(self) -> &'a mut W { + self.variant(MUXNEG_A::PIN0) + } + #[doc = "I/O pin 1"] + #[inline(always)] + pub fn pin1(self) -> &'a mut W { + self.variant(MUXNEG_A::PIN1) + } + #[doc = "I/O pin 2"] + #[inline(always)] + pub fn pin2(self) -> &'a mut W { + self.variant(MUXNEG_A::PIN2) + } + #[doc = "I/O pin 3"] + #[inline(always)] + pub fn pin3(self) -> &'a mut W { + self.variant(MUXNEG_A::PIN3) + } + #[doc = "Ground"] + #[inline(always)] + pub fn gnd(self) -> &'a mut W { + self.variant(MUXNEG_A::GND) + } + #[doc = "VDD scaler"] + #[inline(always)] + pub fn vscale(self) -> &'a mut W { + self.variant(MUXNEG_A::VSCALE) + } + #[doc = "Internal bandgap voltage"] + #[inline(always)] + pub fn bandgap(self) -> &'a mut W { + self.variant(MUXNEG_A::BANDGAP) + } + #[doc = "DAC output"] + #[inline(always)] + pub fn dac(self) -> &'a mut W { + self.variant(MUXNEG_A::DAC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +#[doc = "Positive Input Mux Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MUXPOS_A { + #[doc = "0: I/O pin 0"] + PIN0 = 0, + #[doc = "1: I/O pin 1"] + PIN1 = 1, + #[doc = "2: I/O pin 2"] + PIN2 = 2, + #[doc = "3: I/O pin 3"] + PIN3 = 3, + #[doc = "4: VDD Scaler"] + VSCALE = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MUXPOS_A) -> Self { + variant as _ + } +} +#[doc = "Field `MUXPOS` reader - Positive Input Mux Selection"] +pub struct MUXPOS_R(crate::FieldReader); +impl MUXPOS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MUXPOS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MUXPOS_A::PIN0), + 1 => Some(MUXPOS_A::PIN1), + 2 => Some(MUXPOS_A::PIN2), + 3 => Some(MUXPOS_A::PIN3), + 4 => Some(MUXPOS_A::VSCALE), + _ => None, + } + } + #[doc = "Checks if the value of the field is `PIN0`"] + #[inline(always)] + pub fn is_pin0(&self) -> bool { + **self == MUXPOS_A::PIN0 + } + #[doc = "Checks if the value of the field is `PIN1`"] + #[inline(always)] + pub fn is_pin1(&self) -> bool { + **self == MUXPOS_A::PIN1 + } + #[doc = "Checks if the value of the field is `PIN2`"] + #[inline(always)] + pub fn is_pin2(&self) -> bool { + **self == MUXPOS_A::PIN2 + } + #[doc = "Checks if the value of the field is `PIN3`"] + #[inline(always)] + pub fn is_pin3(&self) -> bool { + **self == MUXPOS_A::PIN3 + } + #[doc = "Checks if the value of the field is `VSCALE`"] + #[inline(always)] + pub fn is_vscale(&self) -> bool { + **self == MUXPOS_A::VSCALE + } +} +impl core::ops::Deref for MUXPOS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MUXPOS` writer - Positive Input Mux Selection"] +pub struct MUXPOS_W<'a> { + w: &'a mut W, +} +impl<'a> MUXPOS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MUXPOS_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "I/O pin 0"] + #[inline(always)] + pub fn pin0(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN0) + } + #[doc = "I/O pin 1"] + #[inline(always)] + pub fn pin1(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN1) + } + #[doc = "I/O pin 2"] + #[inline(always)] + pub fn pin2(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN2) + } + #[doc = "I/O pin 3"] + #[inline(always)] + pub fn pin3(self) -> &'a mut W { + self.variant(MUXPOS_A::PIN3) + } + #[doc = "VDD Scaler"] + #[inline(always)] + pub fn vscale(self) -> &'a mut W { + self.variant(MUXPOS_A::VSCALE) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 12)) | ((value as u32 & 0x07) << 12); + self.w + } +} +#[doc = "Field `SWAP` reader - Swap Inputs and Invert"] +pub struct SWAP_R(crate::FieldReader); +impl SWAP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWAP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWAP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWAP` writer - Swap Inputs and Invert"] +pub struct SWAP_W<'a> { + w: &'a mut W, +} +impl<'a> SWAP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Speed Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SPEED_A { + #[doc = "0: Low speed"] + LOW = 0, + #[doc = "3: High speed"] + HIGH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SPEED_A) -> Self { + variant as _ + } +} +#[doc = "Field `SPEED` reader - Speed Selection"] +pub struct SPEED_R(crate::FieldReader); +impl SPEED_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SPEED_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SPEED_A::LOW), + 3 => Some(SPEED_A::HIGH), + _ => None, + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SPEED_A::LOW + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SPEED_A::HIGH + } +} +impl core::ops::Deref for SPEED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SPEED` writer - Speed Selection"] +pub struct SPEED_W<'a> { + w: &'a mut W, +} +impl<'a> SPEED_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SPEED_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Low speed"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SPEED_A::LOW) + } + #[doc = "High speed"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SPEED_A::HIGH) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Field `HYSTEN` reader - Hysteresis Enable"] +pub struct HYSTEN_R(crate::FieldReader); +impl HYSTEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HYSTEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HYSTEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HYSTEN` writer - Hysteresis Enable"] +pub struct HYSTEN_W<'a> { + w: &'a mut W, +} +impl<'a> HYSTEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Filter Length\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FLEN_A { + #[doc = "0: No filtering"] + OFF = 0, + #[doc = "1: 3-bit majority function (2 of 3)"] + MAJ3 = 1, + #[doc = "2: 5-bit majority function (3 of 5)"] + MAJ5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FLEN_A) -> Self { + variant as _ + } +} +#[doc = "Field `FLEN` reader - Filter Length"] +pub struct FLEN_R(crate::FieldReader); +impl FLEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FLEN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(FLEN_A::OFF), + 1 => Some(FLEN_A::MAJ3), + 2 => Some(FLEN_A::MAJ5), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == FLEN_A::OFF + } + #[doc = "Checks if the value of the field is `MAJ3`"] + #[inline(always)] + pub fn is_maj3(&self) -> bool { + **self == FLEN_A::MAJ3 + } + #[doc = "Checks if the value of the field is `MAJ5`"] + #[inline(always)] + pub fn is_maj5(&self) -> bool { + **self == FLEN_A::MAJ5 + } +} +impl core::ops::Deref for FLEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLEN` writer - Filter Length"] +pub struct FLEN_W<'a> { + w: &'a mut W, +} +impl<'a> FLEN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FLEN_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No filtering"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(FLEN_A::OFF) + } + #[doc = "3-bit majority function (2 of 3)"] + #[inline(always)] + pub fn maj3(self) -> &'a mut W { + self.variant(FLEN_A::MAJ3) + } + #[doc = "5-bit majority function (3 of 5)"] + #[inline(always)] + pub fn maj5(self) -> &'a mut W { + self.variant(FLEN_A::MAJ5) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 24)) | ((value as u32 & 0x07) << 24); + self.w + } +} +#[doc = "Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum OUT_A { + #[doc = "0: The output of COMPn is not routed to the COMPn I/O port"] + OFF = 0, + #[doc = "1: The asynchronous output of COMPn is routed to the COMPn I/O port"] + ASYNC = 1, + #[doc = "2: The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port"] + SYNC = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: OUT_A) -> Self { + variant as _ + } +} +#[doc = "Field `OUT` reader - Output"] +pub struct OUT_R(crate::FieldReader); +impl OUT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + OUT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(OUT_A::OFF), + 1 => Some(OUT_A::ASYNC), + 2 => Some(OUT_A::SYNC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == OUT_A::OFF + } + #[doc = "Checks if the value of the field is `ASYNC`"] + #[inline(always)] + pub fn is_async(&self) -> bool { + **self == OUT_A::ASYNC + } + #[doc = "Checks if the value of the field is `SYNC`"] + #[inline(always)] + pub fn is_sync(&self) -> bool { + **self == OUT_A::SYNC + } +} +impl core::ops::Deref for OUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OUT` writer - Output"] +pub struct OUT_W<'a> { + w: &'a mut W, +} +impl<'a> OUT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: OUT_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "The output of COMPn is not routed to the COMPn I/O port"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(OUT_A::OFF) + } + #[doc = "The asynchronous output of COMPn is routed to the COMPn I/O port"] + #[inline(always)] + pub fn async_(self) -> &'a mut W { + self.variant(OUT_A::ASYNC) + } + #[doc = "The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port"] + #[inline(always)] + pub fn sync(self) -> &'a mut W { + self.variant(OUT_A::SYNC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 28)) | ((value as u32 & 0x03) << 28); + self.w + } +} +impl R { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Single-Shot Mode"] + #[inline(always)] + pub fn single(&self) -> SINGLE_R { + SINGLE_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 3:4 - Interrupt Selection"] + #[inline(always)] + pub fn intsel(&self) -> INTSEL_R { + INTSEL_R::new(((self.bits >> 3) & 0x03) as u8) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Negative Input Mux Selection"] + #[inline(always)] + pub fn muxneg(&self) -> MUXNEG_R { + MUXNEG_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bits 12:14 - Positive Input Mux Selection"] + #[inline(always)] + pub fn muxpos(&self) -> MUXPOS_R { + MUXPOS_R::new(((self.bits >> 12) & 0x07) as u8) + } + #[doc = "Bit 15 - Swap Inputs and Invert"] + #[inline(always)] + pub fn swap(&self) -> SWAP_R { + SWAP_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:17 - Speed Selection"] + #[inline(always)] + pub fn speed(&self) -> SPEED_R { + SPEED_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bit 19 - Hysteresis Enable"] + #[inline(always)] + pub fn hysten(&self) -> HYSTEN_R { + HYSTEN_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bits 24:26 - Filter Length"] + #[inline(always)] + pub fn flen(&self) -> FLEN_R { + FLEN_R::new(((self.bits >> 24) & 0x07) as u8) + } + #[doc = "Bits 28:29 - Output"] + #[inline(always)] + pub fn out(&self) -> OUT_R { + OUT_R::new(((self.bits >> 28) & 0x03) as u8) + } +} +impl W { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - Single-Shot Mode"] + #[inline(always)] + pub fn single(&mut self) -> SINGLE_W { + SINGLE_W { w: self } + } + #[doc = "Bits 3:4 - Interrupt Selection"] + #[inline(always)] + pub fn intsel(&mut self) -> INTSEL_W { + INTSEL_W { w: self } + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bits 8:10 - Negative Input Mux Selection"] + #[inline(always)] + pub fn muxneg(&mut self) -> MUXNEG_W { + MUXNEG_W { w: self } + } + #[doc = "Bits 12:14 - Positive Input Mux Selection"] + #[inline(always)] + pub fn muxpos(&mut self) -> MUXPOS_W { + MUXPOS_W { w: self } + } + #[doc = "Bit 15 - Swap Inputs and Invert"] + #[inline(always)] + pub fn swap(&mut self) -> SWAP_W { + SWAP_W { w: self } + } + #[doc = "Bits 16:17 - Speed Selection"] + #[inline(always)] + pub fn speed(&mut self) -> SPEED_W { + SPEED_W { w: self } + } + #[doc = "Bit 19 - Hysteresis Enable"] + #[inline(always)] + pub fn hysten(&mut self) -> HYSTEN_W { + HYSTEN_W { w: self } + } + #[doc = "Bits 24:26 - Filter Length"] + #[inline(always)] + pub fn flen(&mut self) -> FLEN_W { + FLEN_W { w: self } + } + #[doc = "Bits 28:29 - Output"] + #[inline(always)] + pub fn out(&mut self) -> OUT_W { + OUT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Comparator Control n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [compctrl](index.html) module"] +pub struct COMPCTRL_SPEC; +impl crate::RegisterSpec for COMPCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [compctrl::R](R) reader structure"] +impl crate::Readable for COMPCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [compctrl::W](W) writer structure"] +impl crate::Writable for COMPCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COMPCTRL[%s] +to value 0"] +impl crate::Resettable for COMPCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/ac/ctrla.rs b/pac/atsamc21n/src/ac/ctrla.rs new file mode 100644 index 000000000000..5f2c406226f4 --- /dev/null +++ b/pac/atsamc21n/src/ac/ctrla.rs @@ -0,0 +1,160 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/ac/ctrlb.rs b/pac/atsamc21n/src/ac/ctrlb.rs new file mode 100644 index 000000000000..fa9d604101c2 --- /dev/null +++ b/pac/atsamc21n/src/ac/ctrlb.rs @@ -0,0 +1,153 @@ +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `START0` writer - Comparator 0 Start Comparison"] +pub struct START0_W<'a> { + w: &'a mut W, +} +impl<'a> START0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `START1` writer - Comparator 1 Start Comparison"] +pub struct START1_W<'a> { + w: &'a mut W, +} +impl<'a> START1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `START2` writer - Comparator 2 Start Comparison"] +pub struct START2_W<'a> { + w: &'a mut W, +} +impl<'a> START2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `START3` writer - Comparator 3 Start Comparison"] +pub struct START3_W<'a> { + w: &'a mut W, +} +impl<'a> START3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +impl W { + #[doc = "Bit 0 - Comparator 0 Start Comparison"] + #[inline(always)] + pub fn start0(&mut self) -> START0_W { + START0_W { w: self } + } + #[doc = "Bit 1 - Comparator 1 Start Comparison"] + #[inline(always)] + pub fn start1(&mut self) -> START1_W { + START1_W { w: self } + } + #[doc = "Bit 2 - Comparator 2 Start Comparison"] + #[inline(always)] + pub fn start2(&mut self) -> START2_W { + START2_W { w: self } + } + #[doc = "Bit 3 - Comparator 3 Start Comparison"] + #[inline(always)] + pub fn start3(&mut self) -> START3_W { + START3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u8; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/ac/dbgctrl.rs b/pac/atsamc21n/src/ac/dbgctrl.rs new file mode 100644 index 000000000000..53636eb2b339 --- /dev/null +++ b/pac/atsamc21n/src/ac/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Debug Run"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Debug Run"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/ac/evctrl.rs b/pac/atsamc21n/src/ac/evctrl.rs new file mode 100644 index 000000000000..b2f64ee12108 --- /dev/null +++ b/pac/atsamc21n/src/ac/evctrl.rs @@ -0,0 +1,724 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COMPEO0` reader - Comparator 0 Event Output Enable"] +pub struct COMPEO0_R(crate::FieldReader); +impl COMPEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPEO0` writer - Comparator 0 Event Output Enable"] +pub struct COMPEO0_W<'a> { + w: &'a mut W, +} +impl<'a> COMPEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `COMPEO1` reader - Comparator 1 Event Output Enable"] +pub struct COMPEO1_R(crate::FieldReader); +impl COMPEO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPEO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPEO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPEO1` writer - Comparator 1 Event Output Enable"] +pub struct COMPEO1_W<'a> { + w: &'a mut W, +} +impl<'a> COMPEO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `COMPEO2` reader - Comparator 2 Event Output Enable"] +pub struct COMPEO2_R(crate::FieldReader); +impl COMPEO2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPEO2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPEO2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPEO2` writer - Comparator 2 Event Output Enable"] +pub struct COMPEO2_W<'a> { + w: &'a mut W, +} +impl<'a> COMPEO2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `COMPEO3` reader - Comparator 3 Event Output Enable"] +pub struct COMPEO3_R(crate::FieldReader); +impl COMPEO3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPEO3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPEO3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPEO3` writer - Comparator 3 Event Output Enable"] +pub struct COMPEO3_W<'a> { + w: &'a mut W, +} +impl<'a> COMPEO3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `WINEO0` reader - Window 0 Event Output Enable"] +pub struct WINEO0_R(crate::FieldReader); +impl WINEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINEO0` writer - Window 0 Event Output Enable"] +pub struct WINEO0_W<'a> { + w: &'a mut W, +} +impl<'a> WINEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `WINEO1` reader - Window 1 Event Output Enable"] +pub struct WINEO1_R(crate::FieldReader); +impl WINEO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINEO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINEO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINEO1` writer - Window 1 Event Output Enable"] +pub struct WINEO1_W<'a> { + w: &'a mut W, +} +impl<'a> WINEO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `COMPEI0` reader - Comparator 0 Event Input Enable"] +pub struct COMPEI0_R(crate::FieldReader); +impl COMPEI0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPEI0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPEI0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPEI0` writer - Comparator 0 Event Input Enable"] +pub struct COMPEI0_W<'a> { + w: &'a mut W, +} +impl<'a> COMPEI0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `COMPEI1` reader - Comparator 1 Event Input Enable"] +pub struct COMPEI1_R(crate::FieldReader); +impl COMPEI1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPEI1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPEI1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPEI1` writer - Comparator 1 Event Input Enable"] +pub struct COMPEI1_W<'a> { + w: &'a mut W, +} +impl<'a> COMPEI1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `COMPEI2` reader - Comparator 2 Event Input Enable"] +pub struct COMPEI2_R(crate::FieldReader); +impl COMPEI2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPEI2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPEI2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPEI2` writer - Comparator 2 Event Input Enable"] +pub struct COMPEI2_W<'a> { + w: &'a mut W, +} +impl<'a> COMPEI2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u16 & 0x01) << 10); + self.w + } +} +#[doc = "Field `COMPEI3` reader - Comparator 3 Event Input Enable"] +pub struct COMPEI3_R(crate::FieldReader); +impl COMPEI3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPEI3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPEI3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPEI3` writer - Comparator 3 Event Input Enable"] +pub struct COMPEI3_W<'a> { + w: &'a mut W, +} +impl<'a> COMPEI3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u16 & 0x01) << 11); + self.w + } +} +#[doc = "Field `INVEI0` reader - Comparator 0 Input Event Invert Enable"] +pub struct INVEI0_R(crate::FieldReader); +impl INVEI0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEI0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEI0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEI0` writer - Comparator 0 Input Event Invert Enable"] +pub struct INVEI0_W<'a> { + w: &'a mut W, +} +impl<'a> INVEI0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u16 & 0x01) << 12); + self.w + } +} +#[doc = "Field `INVEI1` reader - Comparator 1 Input Event Invert Enable"] +pub struct INVEI1_R(crate::FieldReader); +impl INVEI1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEI1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEI1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEI1` writer - Comparator 1 Input Event Invert Enable"] +pub struct INVEI1_W<'a> { + w: &'a mut W, +} +impl<'a> INVEI1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u16 & 0x01) << 13); + self.w + } +} +#[doc = "Field `INVEI2` reader - Comparator 2 Input Event Invert Enable"] +pub struct INVEI2_R(crate::FieldReader); +impl INVEI2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEI2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEI2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEI2` writer - Comparator 2 Input Event Invert Enable"] +pub struct INVEI2_W<'a> { + w: &'a mut W, +} +impl<'a> INVEI2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u16 & 0x01) << 14); + self.w + } +} +#[doc = "Field `INVEI3` reader - Comparator 3 Input Event Invert Enable"] +pub struct INVEI3_R(crate::FieldReader); +impl INVEI3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEI3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEI3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEI3` writer - Comparator 3 Input Event Invert Enable"] +pub struct INVEI3_W<'a> { + w: &'a mut W, +} +impl<'a> INVEI3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Comparator 0 Event Output Enable"] + #[inline(always)] + pub fn compeo0(&self) -> COMPEO0_R { + COMPEO0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Comparator 1 Event Output Enable"] + #[inline(always)] + pub fn compeo1(&self) -> COMPEO1_R { + COMPEO1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Comparator 2 Event Output Enable"] + #[inline(always)] + pub fn compeo2(&self) -> COMPEO2_R { + COMPEO2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Comparator 3 Event Output Enable"] + #[inline(always)] + pub fn compeo3(&self) -> COMPEO3_R { + COMPEO3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Window 0 Event Output Enable"] + #[inline(always)] + pub fn wineo0(&self) -> WINEO0_R { + WINEO0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Window 1 Event Output Enable"] + #[inline(always)] + pub fn wineo1(&self) -> WINEO1_R { + WINEO1_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 8 - Comparator 0 Event Input Enable"] + #[inline(always)] + pub fn compei0(&self) -> COMPEI0_R { + COMPEI0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Comparator 1 Event Input Enable"] + #[inline(always)] + pub fn compei1(&self) -> COMPEI1_R { + COMPEI1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Comparator 2 Event Input Enable"] + #[inline(always)] + pub fn compei2(&self) -> COMPEI2_R { + COMPEI2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Comparator 3 Event Input Enable"] + #[inline(always)] + pub fn compei3(&self) -> COMPEI3_R { + COMPEI3_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Comparator 0 Input Event Invert Enable"] + #[inline(always)] + pub fn invei0(&self) -> INVEI0_R { + INVEI0_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Comparator 1 Input Event Invert Enable"] + #[inline(always)] + pub fn invei1(&self) -> INVEI1_R { + INVEI1_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Comparator 2 Input Event Invert Enable"] + #[inline(always)] + pub fn invei2(&self) -> INVEI2_R { + INVEI2_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Comparator 3 Input Event Invert Enable"] + #[inline(always)] + pub fn invei3(&self) -> INVEI3_R { + INVEI3_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Comparator 0 Event Output Enable"] + #[inline(always)] + pub fn compeo0(&mut self) -> COMPEO0_W { + COMPEO0_W { w: self } + } + #[doc = "Bit 1 - Comparator 1 Event Output Enable"] + #[inline(always)] + pub fn compeo1(&mut self) -> COMPEO1_W { + COMPEO1_W { w: self } + } + #[doc = "Bit 2 - Comparator 2 Event Output Enable"] + #[inline(always)] + pub fn compeo2(&mut self) -> COMPEO2_W { + COMPEO2_W { w: self } + } + #[doc = "Bit 3 - Comparator 3 Event Output Enable"] + #[inline(always)] + pub fn compeo3(&mut self) -> COMPEO3_W { + COMPEO3_W { w: self } + } + #[doc = "Bit 4 - Window 0 Event Output Enable"] + #[inline(always)] + pub fn wineo0(&mut self) -> WINEO0_W { + WINEO0_W { w: self } + } + #[doc = "Bit 5 - Window 1 Event Output Enable"] + #[inline(always)] + pub fn wineo1(&mut self) -> WINEO1_W { + WINEO1_W { w: self } + } + #[doc = "Bit 8 - Comparator 0 Event Input Enable"] + #[inline(always)] + pub fn compei0(&mut self) -> COMPEI0_W { + COMPEI0_W { w: self } + } + #[doc = "Bit 9 - Comparator 1 Event Input Enable"] + #[inline(always)] + pub fn compei1(&mut self) -> COMPEI1_W { + COMPEI1_W { w: self } + } + #[doc = "Bit 10 - Comparator 2 Event Input Enable"] + #[inline(always)] + pub fn compei2(&mut self) -> COMPEI2_W { + COMPEI2_W { w: self } + } + #[doc = "Bit 11 - Comparator 3 Event Input Enable"] + #[inline(always)] + pub fn compei3(&mut self) -> COMPEI3_W { + COMPEI3_W { w: self } + } + #[doc = "Bit 12 - Comparator 0 Input Event Invert Enable"] + #[inline(always)] + pub fn invei0(&mut self) -> INVEI0_W { + INVEI0_W { w: self } + } + #[doc = "Bit 13 - Comparator 1 Input Event Invert Enable"] + #[inline(always)] + pub fn invei1(&mut self) -> INVEI1_W { + INVEI1_W { w: self } + } + #[doc = "Bit 14 - Comparator 2 Input Event Invert Enable"] + #[inline(always)] + pub fn invei2(&mut self) -> INVEI2_W { + INVEI2_W { w: self } + } + #[doc = "Bit 15 - Comparator 3 Input Event Invert Enable"] + #[inline(always)] + pub fn invei3(&mut self) -> INVEI3_W { + INVEI3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/ac/intenclr.rs b/pac/atsamc21n/src/ac/intenclr.rs new file mode 100644 index 000000000000..e948bee83d3f --- /dev/null +++ b/pac/atsamc21n/src/ac/intenclr.rs @@ -0,0 +1,348 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COMP0` reader - Comparator 0 Interrupt Enable"] +pub struct COMP0_R(crate::FieldReader); +impl COMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP0` writer - Comparator 0 Interrupt Enable"] +pub struct COMP0_W<'a> { + w: &'a mut W, +} +impl<'a> COMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `COMP1` reader - Comparator 1 Interrupt Enable"] +pub struct COMP1_R(crate::FieldReader); +impl COMP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP1` writer - Comparator 1 Interrupt Enable"] +pub struct COMP1_W<'a> { + w: &'a mut W, +} +impl<'a> COMP1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `COMP2` reader - Comparator 2 Interrupt Enable"] +pub struct COMP2_R(crate::FieldReader); +impl COMP2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP2` writer - Comparator 2 Interrupt Enable"] +pub struct COMP2_W<'a> { + w: &'a mut W, +} +impl<'a> COMP2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `COMP3` reader - Comparator 3 Interrupt Enable"] +pub struct COMP3_R(crate::FieldReader); +impl COMP3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP3` writer - Comparator 3 Interrupt Enable"] +pub struct COMP3_W<'a> { + w: &'a mut W, +} +impl<'a> COMP3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `WIN0` reader - Window 0 Interrupt Enable"] +pub struct WIN0_R(crate::FieldReader); +impl WIN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WIN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WIN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WIN0` writer - Window 0 Interrupt Enable"] +pub struct WIN0_W<'a> { + w: &'a mut W, +} +impl<'a> WIN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `WIN1` reader - Window 1 Interrupt Enable"] +pub struct WIN1_R(crate::FieldReader); +impl WIN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WIN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WIN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WIN1` writer - Window 1 Interrupt Enable"] +pub struct WIN1_W<'a> { + w: &'a mut W, +} +impl<'a> WIN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Comparator 0 Interrupt Enable"] + #[inline(always)] + pub fn comp0(&self) -> COMP0_R { + COMP0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Comparator 1 Interrupt Enable"] + #[inline(always)] + pub fn comp1(&self) -> COMP1_R { + COMP1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Comparator 2 Interrupt Enable"] + #[inline(always)] + pub fn comp2(&self) -> COMP2_R { + COMP2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Comparator 3 Interrupt Enable"] + #[inline(always)] + pub fn comp3(&self) -> COMP3_R { + COMP3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Window 0 Interrupt Enable"] + #[inline(always)] + pub fn win0(&self) -> WIN0_R { + WIN0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Window 1 Interrupt Enable"] + #[inline(always)] + pub fn win1(&self) -> WIN1_R { + WIN1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Comparator 0 Interrupt Enable"] + #[inline(always)] + pub fn comp0(&mut self) -> COMP0_W { + COMP0_W { w: self } + } + #[doc = "Bit 1 - Comparator 1 Interrupt Enable"] + #[inline(always)] + pub fn comp1(&mut self) -> COMP1_W { + COMP1_W { w: self } + } + #[doc = "Bit 2 - Comparator 2 Interrupt Enable"] + #[inline(always)] + pub fn comp2(&mut self) -> COMP2_W { + COMP2_W { w: self } + } + #[doc = "Bit 3 - Comparator 3 Interrupt Enable"] + #[inline(always)] + pub fn comp3(&mut self) -> COMP3_W { + COMP3_W { w: self } + } + #[doc = "Bit 4 - Window 0 Interrupt Enable"] + #[inline(always)] + pub fn win0(&mut self) -> WIN0_W { + WIN0_W { w: self } + } + #[doc = "Bit 5 - Window 1 Interrupt Enable"] + #[inline(always)] + pub fn win1(&mut self) -> WIN1_W { + WIN1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/ac/intenset.rs b/pac/atsamc21n/src/ac/intenset.rs new file mode 100644 index 000000000000..b631f5136fb6 --- /dev/null +++ b/pac/atsamc21n/src/ac/intenset.rs @@ -0,0 +1,348 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COMP0` reader - Comparator 0 Interrupt Enable"] +pub struct COMP0_R(crate::FieldReader); +impl COMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP0` writer - Comparator 0 Interrupt Enable"] +pub struct COMP0_W<'a> { + w: &'a mut W, +} +impl<'a> COMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `COMP1` reader - Comparator 1 Interrupt Enable"] +pub struct COMP1_R(crate::FieldReader); +impl COMP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP1` writer - Comparator 1 Interrupt Enable"] +pub struct COMP1_W<'a> { + w: &'a mut W, +} +impl<'a> COMP1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `COMP2` reader - Comparator 2 Interrupt Enable"] +pub struct COMP2_R(crate::FieldReader); +impl COMP2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP2` writer - Comparator 2 Interrupt Enable"] +pub struct COMP2_W<'a> { + w: &'a mut W, +} +impl<'a> COMP2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `COMP3` reader - Comparator 3 Interrupt Enable"] +pub struct COMP3_R(crate::FieldReader); +impl COMP3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP3` writer - Comparator 3 Interrupt Enable"] +pub struct COMP3_W<'a> { + w: &'a mut W, +} +impl<'a> COMP3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `WIN0` reader - Window 0 Interrupt Enable"] +pub struct WIN0_R(crate::FieldReader); +impl WIN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WIN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WIN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WIN0` writer - Window 0 Interrupt Enable"] +pub struct WIN0_W<'a> { + w: &'a mut W, +} +impl<'a> WIN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `WIN1` reader - Window 1 Interrupt Enable"] +pub struct WIN1_R(crate::FieldReader); +impl WIN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WIN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WIN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WIN1` writer - Window 1 Interrupt Enable"] +pub struct WIN1_W<'a> { + w: &'a mut W, +} +impl<'a> WIN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Comparator 0 Interrupt Enable"] + #[inline(always)] + pub fn comp0(&self) -> COMP0_R { + COMP0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Comparator 1 Interrupt Enable"] + #[inline(always)] + pub fn comp1(&self) -> COMP1_R { + COMP1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Comparator 2 Interrupt Enable"] + #[inline(always)] + pub fn comp2(&self) -> COMP2_R { + COMP2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Comparator 3 Interrupt Enable"] + #[inline(always)] + pub fn comp3(&self) -> COMP3_R { + COMP3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Window 0 Interrupt Enable"] + #[inline(always)] + pub fn win0(&self) -> WIN0_R { + WIN0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Window 1 Interrupt Enable"] + #[inline(always)] + pub fn win1(&self) -> WIN1_R { + WIN1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Comparator 0 Interrupt Enable"] + #[inline(always)] + pub fn comp0(&mut self) -> COMP0_W { + COMP0_W { w: self } + } + #[doc = "Bit 1 - Comparator 1 Interrupt Enable"] + #[inline(always)] + pub fn comp1(&mut self) -> COMP1_W { + COMP1_W { w: self } + } + #[doc = "Bit 2 - Comparator 2 Interrupt Enable"] + #[inline(always)] + pub fn comp2(&mut self) -> COMP2_W { + COMP2_W { w: self } + } + #[doc = "Bit 3 - Comparator 3 Interrupt Enable"] + #[inline(always)] + pub fn comp3(&mut self) -> COMP3_W { + COMP3_W { w: self } + } + #[doc = "Bit 4 - Window 0 Interrupt Enable"] + #[inline(always)] + pub fn win0(&mut self) -> WIN0_W { + WIN0_W { w: self } + } + #[doc = "Bit 5 - Window 1 Interrupt Enable"] + #[inline(always)] + pub fn win1(&mut self) -> WIN1_W { + WIN1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/ac/intflag.rs b/pac/atsamc21n/src/ac/intflag.rs new file mode 100644 index 000000000000..6557a5e48464 --- /dev/null +++ b/pac/atsamc21n/src/ac/intflag.rs @@ -0,0 +1,348 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COMP0` reader - Comparator 0"] +pub struct COMP0_R(crate::FieldReader); +impl COMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP0` writer - Comparator 0"] +pub struct COMP0_W<'a> { + w: &'a mut W, +} +impl<'a> COMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `COMP1` reader - Comparator 1"] +pub struct COMP1_R(crate::FieldReader); +impl COMP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP1` writer - Comparator 1"] +pub struct COMP1_W<'a> { + w: &'a mut W, +} +impl<'a> COMP1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `COMP2` reader - Comparator 2"] +pub struct COMP2_R(crate::FieldReader); +impl COMP2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP2` writer - Comparator 2"] +pub struct COMP2_W<'a> { + w: &'a mut W, +} +impl<'a> COMP2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `COMP3` reader - Comparator 3"] +pub struct COMP3_R(crate::FieldReader); +impl COMP3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP3` writer - Comparator 3"] +pub struct COMP3_W<'a> { + w: &'a mut W, +} +impl<'a> COMP3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `WIN0` reader - Window 0"] +pub struct WIN0_R(crate::FieldReader); +impl WIN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WIN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WIN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WIN0` writer - Window 0"] +pub struct WIN0_W<'a> { + w: &'a mut W, +} +impl<'a> WIN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `WIN1` reader - Window 1"] +pub struct WIN1_R(crate::FieldReader); +impl WIN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WIN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WIN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WIN1` writer - Window 1"] +pub struct WIN1_W<'a> { + w: &'a mut W, +} +impl<'a> WIN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Comparator 0"] + #[inline(always)] + pub fn comp0(&self) -> COMP0_R { + COMP0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Comparator 1"] + #[inline(always)] + pub fn comp1(&self) -> COMP1_R { + COMP1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Comparator 2"] + #[inline(always)] + pub fn comp2(&self) -> COMP2_R { + COMP2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Comparator 3"] + #[inline(always)] + pub fn comp3(&self) -> COMP3_R { + COMP3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Window 0"] + #[inline(always)] + pub fn win0(&self) -> WIN0_R { + WIN0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Window 1"] + #[inline(always)] + pub fn win1(&self) -> WIN1_R { + WIN1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Comparator 0"] + #[inline(always)] + pub fn comp0(&mut self) -> COMP0_W { + COMP0_W { w: self } + } + #[doc = "Bit 1 - Comparator 1"] + #[inline(always)] + pub fn comp1(&mut self) -> COMP1_W { + COMP1_W { w: self } + } + #[doc = "Bit 2 - Comparator 2"] + #[inline(always)] + pub fn comp2(&mut self) -> COMP2_W { + COMP2_W { w: self } + } + #[doc = "Bit 3 - Comparator 3"] + #[inline(always)] + pub fn comp3(&mut self) -> COMP3_W { + COMP3_W { w: self } + } + #[doc = "Bit 4 - Window 0"] + #[inline(always)] + pub fn win0(&mut self) -> WIN0_W { + WIN0_W { w: self } + } + #[doc = "Bit 5 - Window 1"] + #[inline(always)] + pub fn win1(&mut self) -> WIN1_W { + WIN1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/ac/scaler.rs b/pac/atsamc21n/src/ac/scaler.rs new file mode 100644 index 000000000000..091cacfaeb4b --- /dev/null +++ b/pac/atsamc21n/src/ac/scaler.rs @@ -0,0 +1,104 @@ +#[doc = "Register `SCALER[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SCALER[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `VALUE` reader - Scaler Value"] +pub struct VALUE_R(crate::FieldReader); +impl VALUE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + VALUE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VALUE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VALUE` writer - Scaler Value"] +pub struct VALUE_W<'a> { + w: &'a mut W, +} +impl<'a> VALUE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u8 & 0x3f); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Scaler Value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - Scaler Value"] + #[inline(always)] + pub fn value(&mut self) -> VALUE_W { + VALUE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Scaler n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [scaler](index.html) module"] +pub struct SCALER_SPEC; +impl crate::RegisterSpec for SCALER_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [scaler::R](R) reader structure"] +impl crate::Readable for SCALER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [scaler::W](W) writer structure"] +impl crate::Writable for SCALER_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SCALER[%s] +to value 0"] +impl crate::Resettable for SCALER_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/ac/statusa.rs b/pac/atsamc21n/src/ac/statusa.rs new file mode 100644 index 000000000000..f79619555497 --- /dev/null +++ b/pac/atsamc21n/src/ac/statusa.rs @@ -0,0 +1,237 @@ +#[doc = "Register `STATUSA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `STATE0` reader - Comparator 0 Current State"] +pub struct STATE0_R(crate::FieldReader); +impl STATE0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STATE0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STATE0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STATE1` reader - Comparator 1 Current State"] +pub struct STATE1_R(crate::FieldReader); +impl STATE1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STATE1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STATE1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STATE2` reader - Comparator 2 Current State"] +pub struct STATE2_R(crate::FieldReader); +impl STATE2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STATE2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STATE2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STATE3` reader - Comparator 3 Current State"] +pub struct STATE3_R(crate::FieldReader); +impl STATE3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STATE3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STATE3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Window 0 Current State\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WSTATE0_A { + #[doc = "0: Signal is above window"] + ABOVE = 0, + #[doc = "1: Signal is inside window"] + INSIDE = 1, + #[doc = "2: Signal is below window"] + BELOW = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WSTATE0_A) -> Self { + variant as _ + } +} +#[doc = "Field `WSTATE0` reader - Window 0 Current State"] +pub struct WSTATE0_R(crate::FieldReader); +impl WSTATE0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WSTATE0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(WSTATE0_A::ABOVE), + 1 => Some(WSTATE0_A::INSIDE), + 2 => Some(WSTATE0_A::BELOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `ABOVE`"] + #[inline(always)] + pub fn is_above(&self) -> bool { + **self == WSTATE0_A::ABOVE + } + #[doc = "Checks if the value of the field is `INSIDE`"] + #[inline(always)] + pub fn is_inside(&self) -> bool { + **self == WSTATE0_A::INSIDE + } + #[doc = "Checks if the value of the field is `BELOW`"] + #[inline(always)] + pub fn is_below(&self) -> bool { + **self == WSTATE0_A::BELOW + } +} +impl core::ops::Deref for WSTATE0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Window 1 Current State\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WSTATE1_A { + #[doc = "0: Signal is above window"] + ABOVE = 0, + #[doc = "1: Signal is inside window"] + INSIDE = 1, + #[doc = "2: Signal is below window"] + BELOW = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WSTATE1_A) -> Self { + variant as _ + } +} +#[doc = "Field `WSTATE1` reader - Window 1 Current State"] +pub struct WSTATE1_R(crate::FieldReader); +impl WSTATE1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WSTATE1_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(WSTATE1_A::ABOVE), + 1 => Some(WSTATE1_A::INSIDE), + 2 => Some(WSTATE1_A::BELOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `ABOVE`"] + #[inline(always)] + pub fn is_above(&self) -> bool { + **self == WSTATE1_A::ABOVE + } + #[doc = "Checks if the value of the field is `INSIDE`"] + #[inline(always)] + pub fn is_inside(&self) -> bool { + **self == WSTATE1_A::INSIDE + } + #[doc = "Checks if the value of the field is `BELOW`"] + #[inline(always)] + pub fn is_below(&self) -> bool { + **self == WSTATE1_A::BELOW + } +} +impl core::ops::Deref for WSTATE1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Comparator 0 Current State"] + #[inline(always)] + pub fn state0(&self) -> STATE0_R { + STATE0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Comparator 1 Current State"] + #[inline(always)] + pub fn state1(&self) -> STATE1_R { + STATE1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Comparator 2 Current State"] + #[inline(always)] + pub fn state2(&self) -> STATE2_R { + STATE2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Comparator 3 Current State"] + #[inline(always)] + pub fn state3(&self) -> STATE3_R { + STATE3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bits 4:5 - Window 0 Current State"] + #[inline(always)] + pub fn wstate0(&self) -> WSTATE0_R { + WSTATE0_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bits 6:7 - Window 1 Current State"] + #[inline(always)] + pub fn wstate1(&self) -> WSTATE1_R { + WSTATE1_R::new(((self.bits >> 6) & 0x03) as u8) + } +} +#[doc = "Status A\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [statusa](index.html) module"] +pub struct STATUSA_SPEC; +impl crate::RegisterSpec for STATUSA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [statusa::R](R) reader structure"] +impl crate::Readable for STATUSA_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUSA to value 0"] +impl crate::Resettable for STATUSA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/ac/statusb.rs b/pac/atsamc21n/src/ac/statusb.rs new file mode 100644 index 000000000000..1f7035958bd8 --- /dev/null +++ b/pac/atsamc21n/src/ac/statusb.rs @@ -0,0 +1,113 @@ +#[doc = "Register `STATUSB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `READY0` reader - Comparator 0 Ready"] +pub struct READY0_R(crate::FieldReader); +impl READY0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + READY0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for READY0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `READY1` reader - Comparator 1 Ready"] +pub struct READY1_R(crate::FieldReader); +impl READY1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + READY1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for READY1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `READY2` reader - Comparator 2 Ready"] +pub struct READY2_R(crate::FieldReader); +impl READY2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + READY2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for READY2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `READY3` reader - Comparator 3 Ready"] +pub struct READY3_R(crate::FieldReader); +impl READY3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + READY3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for READY3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Comparator 0 Ready"] + #[inline(always)] + pub fn ready0(&self) -> READY0_R { + READY0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Comparator 1 Ready"] + #[inline(always)] + pub fn ready1(&self) -> READY1_R { + READY1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Comparator 2 Ready"] + #[inline(always)] + pub fn ready2(&self) -> READY2_R { + READY2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Comparator 3 Ready"] + #[inline(always)] + pub fn ready3(&self) -> READY3_R { + READY3_R::new(((self.bits >> 3) & 0x01) != 0) + } +} +#[doc = "Status B\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [statusb](index.html) module"] +pub struct STATUSB_SPEC; +impl crate::RegisterSpec for STATUSB_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [statusb::R](R) reader structure"] +impl crate::Readable for STATUSB_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUSB to value 0"] +impl crate::Resettable for STATUSB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/ac/syncbusy.rs b/pac/atsamc21n/src/ac/syncbusy.rs new file mode 100644 index 000000000000..bbd5b5cbe18f --- /dev/null +++ b/pac/atsamc21n/src/ac/syncbusy.rs @@ -0,0 +1,173 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - Enable Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINCTRL` reader - WINCTRL Synchronization Busy"] +pub struct WINCTRL_R(crate::FieldReader); +impl WINCTRL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINCTRL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINCTRL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPCTRL0` reader - COMPCTRL 0 Synchronization Busy"] +pub struct COMPCTRL0_R(crate::FieldReader); +impl COMPCTRL0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPCTRL0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPCTRL0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPCTRL1` reader - COMPCTRL 1 Synchronization Busy"] +pub struct COMPCTRL1_R(crate::FieldReader); +impl COMPCTRL1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPCTRL1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPCTRL1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPCTRL2` reader - COMPCTRL 2 Synchronization Busy"] +pub struct COMPCTRL2_R(crate::FieldReader); +impl COMPCTRL2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPCTRL2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPCTRL2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPCTRL3` reader - COMPCTRL 3 Synchronization Busy"] +pub struct COMPCTRL3_R(crate::FieldReader); +impl COMPCTRL3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPCTRL3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPCTRL3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - WINCTRL Synchronization Busy"] + #[inline(always)] + pub fn winctrl(&self) -> WINCTRL_R { + WINCTRL_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - COMPCTRL 0 Synchronization Busy"] + #[inline(always)] + pub fn compctrl0(&self) -> COMPCTRL0_R { + COMPCTRL0_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - COMPCTRL 1 Synchronization Busy"] + #[inline(always)] + pub fn compctrl1(&self) -> COMPCTRL1_R { + COMPCTRL1_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - COMPCTRL 2 Synchronization Busy"] + #[inline(always)] + pub fn compctrl2(&self) -> COMPCTRL2_R { + COMPCTRL2_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - COMPCTRL 3 Synchronization Busy"] + #[inline(always)] + pub fn compctrl3(&self) -> COMPCTRL3_R { + COMPCTRL3_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +#[doc = "Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/ac/winctrl.rs b/pac/atsamc21n/src/ac/winctrl.rs new file mode 100644 index 000000000000..e3fe941f07bd --- /dev/null +++ b/pac/atsamc21n/src/ac/winctrl.rs @@ -0,0 +1,384 @@ +#[doc = "Register `WINCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WINCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WEN0` reader - Window 0 Mode Enable"] +pub struct WEN0_R(crate::FieldReader); +impl WEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WEN0` writer - Window 0 Mode Enable"] +pub struct WEN0_W<'a> { + w: &'a mut W, +} +impl<'a> WEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Window 0 Interrupt Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WINTSEL0_A { + #[doc = "0: Interrupt on signal above window"] + ABOVE = 0, + #[doc = "1: Interrupt on signal inside window"] + INSIDE = 1, + #[doc = "2: Interrupt on signal below window"] + BELOW = 2, + #[doc = "3: Interrupt on signal outside window"] + OUTSIDE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WINTSEL0_A) -> Self { + variant as _ + } +} +#[doc = "Field `WINTSEL0` reader - Window 0 Interrupt Selection"] +pub struct WINTSEL0_R(crate::FieldReader); +impl WINTSEL0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WINTSEL0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> WINTSEL0_A { + match self.bits { + 0 => WINTSEL0_A::ABOVE, + 1 => WINTSEL0_A::INSIDE, + 2 => WINTSEL0_A::BELOW, + 3 => WINTSEL0_A::OUTSIDE, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `ABOVE`"] + #[inline(always)] + pub fn is_above(&self) -> bool { + **self == WINTSEL0_A::ABOVE + } + #[doc = "Checks if the value of the field is `INSIDE`"] + #[inline(always)] + pub fn is_inside(&self) -> bool { + **self == WINTSEL0_A::INSIDE + } + #[doc = "Checks if the value of the field is `BELOW`"] + #[inline(always)] + pub fn is_below(&self) -> bool { + **self == WINTSEL0_A::BELOW + } + #[doc = "Checks if the value of the field is `OUTSIDE`"] + #[inline(always)] + pub fn is_outside(&self) -> bool { + **self == WINTSEL0_A::OUTSIDE + } +} +impl core::ops::Deref for WINTSEL0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINTSEL0` writer - Window 0 Interrupt Selection"] +pub struct WINTSEL0_W<'a> { + w: &'a mut W, +} +impl<'a> WINTSEL0_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WINTSEL0_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Interrupt on signal above window"] + #[inline(always)] + pub fn above(self) -> &'a mut W { + self.variant(WINTSEL0_A::ABOVE) + } + #[doc = "Interrupt on signal inside window"] + #[inline(always)] + pub fn inside(self) -> &'a mut W { + self.variant(WINTSEL0_A::INSIDE) + } + #[doc = "Interrupt on signal below window"] + #[inline(always)] + pub fn below(self) -> &'a mut W { + self.variant(WINTSEL0_A::BELOW) + } + #[doc = "Interrupt on signal outside window"] + #[inline(always)] + pub fn outside(self) -> &'a mut W { + self.variant(WINTSEL0_A::OUTSIDE) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 1)) | ((value as u8 & 0x03) << 1); + self.w + } +} +#[doc = "Field `WEN1` reader - Window 1 Mode Enable"] +pub struct WEN1_R(crate::FieldReader); +impl WEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WEN1` writer - Window 1 Mode Enable"] +pub struct WEN1_W<'a> { + w: &'a mut W, +} +impl<'a> WEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Window 1 Interrupt Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WINTSEL1_A { + #[doc = "0: Interrupt on signal above window"] + ABOVE = 0, + #[doc = "1: Interrupt on signal inside window"] + INSIDE = 1, + #[doc = "2: Interrupt on signal below window"] + BELOW = 2, + #[doc = "3: Interrupt on signal outside window"] + OUTSIDE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WINTSEL1_A) -> Self { + variant as _ + } +} +#[doc = "Field `WINTSEL1` reader - Window 1 Interrupt Selection"] +pub struct WINTSEL1_R(crate::FieldReader); +impl WINTSEL1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WINTSEL1_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> WINTSEL1_A { + match self.bits { + 0 => WINTSEL1_A::ABOVE, + 1 => WINTSEL1_A::INSIDE, + 2 => WINTSEL1_A::BELOW, + 3 => WINTSEL1_A::OUTSIDE, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `ABOVE`"] + #[inline(always)] + pub fn is_above(&self) -> bool { + **self == WINTSEL1_A::ABOVE + } + #[doc = "Checks if the value of the field is `INSIDE`"] + #[inline(always)] + pub fn is_inside(&self) -> bool { + **self == WINTSEL1_A::INSIDE + } + #[doc = "Checks if the value of the field is `BELOW`"] + #[inline(always)] + pub fn is_below(&self) -> bool { + **self == WINTSEL1_A::BELOW + } + #[doc = "Checks if the value of the field is `OUTSIDE`"] + #[inline(always)] + pub fn is_outside(&self) -> bool { + **self == WINTSEL1_A::OUTSIDE + } +} +impl core::ops::Deref for WINTSEL1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINTSEL1` writer - Window 1 Interrupt Selection"] +pub struct WINTSEL1_W<'a> { + w: &'a mut W, +} +impl<'a> WINTSEL1_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WINTSEL1_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Interrupt on signal above window"] + #[inline(always)] + pub fn above(self) -> &'a mut W { + self.variant(WINTSEL1_A::ABOVE) + } + #[doc = "Interrupt on signal inside window"] + #[inline(always)] + pub fn inside(self) -> &'a mut W { + self.variant(WINTSEL1_A::INSIDE) + } + #[doc = "Interrupt on signal below window"] + #[inline(always)] + pub fn below(self) -> &'a mut W { + self.variant(WINTSEL1_A::BELOW) + } + #[doc = "Interrupt on signal outside window"] + #[inline(always)] + pub fn outside(self) -> &'a mut W { + self.variant(WINTSEL1_A::OUTSIDE) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 5)) | ((value as u8 & 0x03) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Window 0 Mode Enable"] + #[inline(always)] + pub fn wen0(&self) -> WEN0_R { + WEN0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bits 1:2 - Window 0 Interrupt Selection"] + #[inline(always)] + pub fn wintsel0(&self) -> WINTSEL0_R { + WINTSEL0_R::new(((self.bits >> 1) & 0x03) as u8) + } + #[doc = "Bit 4 - Window 1 Mode Enable"] + #[inline(always)] + pub fn wen1(&self) -> WEN1_R { + WEN1_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bits 5:6 - Window 1 Interrupt Selection"] + #[inline(always)] + pub fn wintsel1(&self) -> WINTSEL1_R { + WINTSEL1_R::new(((self.bits >> 5) & 0x03) as u8) + } +} +impl W { + #[doc = "Bit 0 - Window 0 Mode Enable"] + #[inline(always)] + pub fn wen0(&mut self) -> WEN0_W { + WEN0_W { w: self } + } + #[doc = "Bits 1:2 - Window 0 Interrupt Selection"] + #[inline(always)] + pub fn wintsel0(&mut self) -> WINTSEL0_W { + WINTSEL0_W { w: self } + } + #[doc = "Bit 4 - Window 1 Mode Enable"] + #[inline(always)] + pub fn wen1(&mut self) -> WEN1_W { + WEN1_W { w: self } + } + #[doc = "Bits 5:6 - Window 1 Interrupt Selection"] + #[inline(always)] + pub fn wintsel1(&mut self) -> WINTSEL1_W { + WINTSEL1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Window Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [winctrl](index.html) module"] +pub struct WINCTRL_SPEC; +impl crate::RegisterSpec for WINCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [winctrl::R](R) reader structure"] +impl crate::Readable for WINCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [winctrl::W](W) writer structure"] +impl crate::Writable for WINCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WINCTRL to value 0"] +impl crate::Resettable for WINCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/adc0.rs b/pac/atsamc21n/src/adc0.rs new file mode 100644 index 000000000000..453f56ed28c8 --- /dev/null +++ b/pac/atsamc21n/src/adc0.rs @@ -0,0 +1,141 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + #[doc = "0x01 - Control B"] + pub ctrlb: crate::Reg, + #[doc = "0x02 - Reference Control"] + pub refctrl: crate::Reg, + #[doc = "0x03 - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x04 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x05 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x06 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x07 - Sequence Status"] + pub seqstatus: crate::Reg, + #[doc = "0x08 - Input Control"] + pub inputctrl: crate::Reg, + #[doc = "0x0a - Control C"] + pub ctrlc: crate::Reg, + #[doc = "0x0c - Average Control"] + pub avgctrl: crate::Reg, + #[doc = "0x0d - Sample Time Control"] + pub sampctrl: crate::Reg, + #[doc = "0x0e - Window Monitor Lower Threshold"] + pub winlt: crate::Reg, + #[doc = "0x10 - Window Monitor Upper Threshold"] + pub winut: crate::Reg, + #[doc = "0x12 - Gain Correction"] + pub gaincorr: crate::Reg, + #[doc = "0x14 - Offset Correction"] + pub offsetcorr: crate::Reg, + _reserved16: [u8; 0x02], + #[doc = "0x18 - Software Trigger"] + pub swtrig: crate::Reg, + _reserved17: [u8; 0x03], + #[doc = "0x1c - Debug Control"] + pub dbgctrl: crate::Reg, + _reserved18: [u8; 0x03], + #[doc = "0x20 - Synchronization Busy"] + pub syncbusy: crate::Reg, + _reserved19: [u8; 0x02], + #[doc = "0x24 - Result"] + pub result: crate::Reg, + _reserved20: [u8; 0x02], + #[doc = "0x28 - Sequence Control"] + pub seqctrl: crate::Reg, + #[doc = "0x2c - Calibration"] + pub calib: crate::Reg, +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "Control B"] +pub mod ctrlb; +#[doc = "REFCTRL register accessor: an alias for `Reg`"] +pub type REFCTRL = crate::Reg; +#[doc = "Reference Control"] +pub mod refctrl; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "SEQSTATUS register accessor: an alias for `Reg`"] +pub type SEQSTATUS = crate::Reg; +#[doc = "Sequence Status"] +pub mod seqstatus; +#[doc = "INPUTCTRL register accessor: an alias for `Reg`"] +pub type INPUTCTRL = crate::Reg; +#[doc = "Input Control"] +pub mod inputctrl; +#[doc = "CTRLC register accessor: an alias for `Reg`"] +pub type CTRLC = crate::Reg; +#[doc = "Control C"] +pub mod ctrlc; +#[doc = "AVGCTRL register accessor: an alias for `Reg`"] +pub type AVGCTRL = crate::Reg; +#[doc = "Average Control"] +pub mod avgctrl; +#[doc = "SAMPCTRL register accessor: an alias for `Reg`"] +pub type SAMPCTRL = crate::Reg; +#[doc = "Sample Time Control"] +pub mod sampctrl; +#[doc = "WINLT register accessor: an alias for `Reg`"] +pub type WINLT = crate::Reg; +#[doc = "Window Monitor Lower Threshold"] +pub mod winlt; +#[doc = "WINUT register accessor: an alias for `Reg`"] +pub type WINUT = crate::Reg; +#[doc = "Window Monitor Upper Threshold"] +pub mod winut; +#[doc = "GAINCORR register accessor: an alias for `Reg`"] +pub type GAINCORR = crate::Reg; +#[doc = "Gain Correction"] +pub mod gaincorr; +#[doc = "OFFSETCORR register accessor: an alias for `Reg`"] +pub type OFFSETCORR = crate::Reg; +#[doc = "Offset Correction"] +pub mod offsetcorr; +#[doc = "SWTRIG register accessor: an alias for `Reg`"] +pub type SWTRIG = crate::Reg; +#[doc = "Software Trigger"] +pub mod swtrig; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Busy"] +pub mod syncbusy; +#[doc = "RESULT register accessor: an alias for `Reg`"] +pub type RESULT = crate::Reg; +#[doc = "Result"] +pub mod result; +#[doc = "SEQCTRL register accessor: an alias for `Reg`"] +pub type SEQCTRL = crate::Reg; +#[doc = "Sequence Control"] +pub mod seqctrl; +#[doc = "CALIB register accessor: an alias for `Reg`"] +pub type CALIB = crate::Reg; +#[doc = "Calibration"] +pub mod calib; diff --git a/pac/atsamc21n/src/adc0/avgctrl.rs b/pac/atsamc21n/src/adc0/avgctrl.rs new file mode 100644 index 000000000000..ddb735715c98 --- /dev/null +++ b/pac/atsamc21n/src/adc0/avgctrl.rs @@ -0,0 +1,306 @@ +#[doc = "Register `AVGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `AVGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Number of Samples to be Collected\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SAMPLENUM_A { + #[doc = "0: 1 sample"] + _1 = 0, + #[doc = "1: 2 samples"] + _2 = 1, + #[doc = "2: 4 samples"] + _4 = 2, + #[doc = "3: 8 samples"] + _8 = 3, + #[doc = "4: 16 samples"] + _16 = 4, + #[doc = "5: 32 samples"] + _32 = 5, + #[doc = "6: 64 samples"] + _64 = 6, + #[doc = "7: 128 samples"] + _128 = 7, + #[doc = "8: 256 samples"] + _256 = 8, + #[doc = "9: 512 samples"] + _512 = 9, + #[doc = "10: 1024 samples"] + _1024 = 10, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SAMPLENUM_A) -> Self { + variant as _ + } +} +#[doc = "Field `SAMPLENUM` reader - Number of Samples to be Collected"] +pub struct SAMPLENUM_R(crate::FieldReader); +impl SAMPLENUM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SAMPLENUM_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SAMPLENUM_A::_1), + 1 => Some(SAMPLENUM_A::_2), + 2 => Some(SAMPLENUM_A::_4), + 3 => Some(SAMPLENUM_A::_8), + 4 => Some(SAMPLENUM_A::_16), + 5 => Some(SAMPLENUM_A::_32), + 6 => Some(SAMPLENUM_A::_64), + 7 => Some(SAMPLENUM_A::_128), + 8 => Some(SAMPLENUM_A::_256), + 9 => Some(SAMPLENUM_A::_512), + 10 => Some(SAMPLENUM_A::_1024), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_1`"] + #[inline(always)] + pub fn is_1(&self) -> bool { + **self == SAMPLENUM_A::_1 + } + #[doc = "Checks if the value of the field is `_2`"] + #[inline(always)] + pub fn is_2(&self) -> bool { + **self == SAMPLENUM_A::_2 + } + #[doc = "Checks if the value of the field is `_4`"] + #[inline(always)] + pub fn is_4(&self) -> bool { + **self == SAMPLENUM_A::_4 + } + #[doc = "Checks if the value of the field is `_8`"] + #[inline(always)] + pub fn is_8(&self) -> bool { + **self == SAMPLENUM_A::_8 + } + #[doc = "Checks if the value of the field is `_16`"] + #[inline(always)] + pub fn is_16(&self) -> bool { + **self == SAMPLENUM_A::_16 + } + #[doc = "Checks if the value of the field is `_32`"] + #[inline(always)] + pub fn is_32(&self) -> bool { + **self == SAMPLENUM_A::_32 + } + #[doc = "Checks if the value of the field is `_64`"] + #[inline(always)] + pub fn is_64(&self) -> bool { + **self == SAMPLENUM_A::_64 + } + #[doc = "Checks if the value of the field is `_128`"] + #[inline(always)] + pub fn is_128(&self) -> bool { + **self == SAMPLENUM_A::_128 + } + #[doc = "Checks if the value of the field is `_256`"] + #[inline(always)] + pub fn is_256(&self) -> bool { + **self == SAMPLENUM_A::_256 + } + #[doc = "Checks if the value of the field is `_512`"] + #[inline(always)] + pub fn is_512(&self) -> bool { + **self == SAMPLENUM_A::_512 + } + #[doc = "Checks if the value of the field is `_1024`"] + #[inline(always)] + pub fn is_1024(&self) -> bool { + **self == SAMPLENUM_A::_1024 + } +} +impl core::ops::Deref for SAMPLENUM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SAMPLENUM` writer - Number of Samples to be Collected"] +pub struct SAMPLENUM_W<'a> { + w: &'a mut W, +} +impl<'a> SAMPLENUM_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SAMPLENUM_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "1 sample"] + #[inline(always)] + pub fn _1(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_1) + } + #[doc = "2 samples"] + #[inline(always)] + pub fn _2(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_2) + } + #[doc = "4 samples"] + #[inline(always)] + pub fn _4(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_4) + } + #[doc = "8 samples"] + #[inline(always)] + pub fn _8(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_8) + } + #[doc = "16 samples"] + #[inline(always)] + pub fn _16(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_16) + } + #[doc = "32 samples"] + #[inline(always)] + pub fn _32(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_32) + } + #[doc = "64 samples"] + #[inline(always)] + pub fn _64(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_64) + } + #[doc = "128 samples"] + #[inline(always)] + pub fn _128(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_128) + } + #[doc = "256 samples"] + #[inline(always)] + pub fn _256(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_256) + } + #[doc = "512 samples"] + #[inline(always)] + pub fn _512(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_512) + } + #[doc = "1024 samples"] + #[inline(always)] + pub fn _1024(self) -> &'a mut W { + self.variant(SAMPLENUM_A::_1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +#[doc = "Field `ADJRES` reader - Adjusting Result / Division Coefficient"] +pub struct ADJRES_R(crate::FieldReader); +impl ADJRES_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ADJRES_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADJRES_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADJRES` writer - Adjusting Result / Division Coefficient"] +pub struct ADJRES_W<'a> { + w: &'a mut W, +} +impl<'a> ADJRES_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 4)) | ((value as u8 & 0x07) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Number of Samples to be Collected"] + #[inline(always)] + pub fn samplenum(&self) -> SAMPLENUM_R { + SAMPLENUM_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:6 - Adjusting Result / Division Coefficient"] + #[inline(always)] + pub fn adjres(&self) -> ADJRES_R { + ADJRES_R::new(((self.bits >> 4) & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Number of Samples to be Collected"] + #[inline(always)] + pub fn samplenum(&mut self) -> SAMPLENUM_W { + SAMPLENUM_W { w: self } + } + #[doc = "Bits 4:6 - Adjusting Result / Division Coefficient"] + #[inline(always)] + pub fn adjres(&mut self) -> ADJRES_W { + ADJRES_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Average Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [avgctrl](index.html) module"] +pub struct AVGCTRL_SPEC; +impl crate::RegisterSpec for AVGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [avgctrl::R](R) reader structure"] +impl crate::Readable for AVGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [avgctrl::W](W) writer structure"] +impl crate::Writable for AVGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets AVGCTRL to value 0"] +impl crate::Resettable for AVGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/adc0/calib.rs b/pac/atsamc21n/src/adc0/calib.rs new file mode 100644 index 000000000000..8a1a99b8c47d --- /dev/null +++ b/pac/atsamc21n/src/adc0/calib.rs @@ -0,0 +1,140 @@ +#[doc = "Register `CALIB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CALIB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BIASCOMP` reader - Bias Comparator Scaling"] +pub struct BIASCOMP_R(crate::FieldReader); +impl BIASCOMP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BIASCOMP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BIASCOMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BIASCOMP` writer - Bias Comparator Scaling"] +pub struct BIASCOMP_W<'a> { + w: &'a mut W, +} +impl<'a> BIASCOMP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u16 & 0x07); + self.w + } +} +#[doc = "Field `BIASREFBUF` reader - Bias Reference Buffer Scaling"] +pub struct BIASREFBUF_R(crate::FieldReader); +impl BIASREFBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BIASREFBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BIASREFBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BIASREFBUF` writer - Bias Reference Buffer Scaling"] +pub struct BIASREFBUF_W<'a> { + w: &'a mut W, +} +impl<'a> BIASREFBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u16 & 0x07) << 8); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Bias Comparator Scaling"] + #[inline(always)] + pub fn biascomp(&self) -> BIASCOMP_R { + BIASCOMP_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bits 8:10 - Bias Reference Buffer Scaling"] + #[inline(always)] + pub fn biasrefbuf(&self) -> BIASREFBUF_R { + BIASREFBUF_R::new(((self.bits >> 8) & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Bias Comparator Scaling"] + #[inline(always)] + pub fn biascomp(&mut self) -> BIASCOMP_W { + BIASCOMP_W { w: self } + } + #[doc = "Bits 8:10 - Bias Reference Buffer Scaling"] + #[inline(always)] + pub fn biasrefbuf(&mut self) -> BIASREFBUF_W { + BIASREFBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Calibration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [calib](index.html) module"] +pub struct CALIB_SPEC; +impl crate::RegisterSpec for CALIB_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [calib::R](R) reader structure"] +impl crate::Readable for CALIB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [calib::W](W) writer structure"] +impl crate::Writable for CALIB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CALIB to value 0"] +impl crate::Resettable for CALIB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/adc0/ctrla.rs b/pac/atsamc21n/src/adc0/ctrla.rs new file mode 100644 index 000000000000..47c681045f95 --- /dev/null +++ b/pac/atsamc21n/src/adc0/ctrla.rs @@ -0,0 +1,301 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SLAVEEN` reader - Slave Enable"] +pub struct SLAVEEN_R(crate::FieldReader); +impl SLAVEEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLAVEEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SLAVEEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLAVEEN` writer - Slave Enable"] +pub struct SLAVEEN_W<'a> { + w: &'a mut W, +} +impl<'a> SLAVEEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run During Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run During Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - On Demand Control"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - On Demand Control"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 5 - Slave Enable"] + #[inline(always)] + pub fn slaveen(&self) -> SLAVEEN_R { + SLAVEEN_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Run During Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 5 - Slave Enable"] + #[inline(always)] + pub fn slaveen(&mut self) -> SLAVEEN_W { + SLAVEEN_W { w: self } + } + #[doc = "Bit 6 - Run During Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/adc0/ctrlb.rs b/pac/atsamc21n/src/adc0/ctrlb.rs new file mode 100644 index 000000000000..60dabcbf562e --- /dev/null +++ b/pac/atsamc21n/src/adc0/ctrlb.rs @@ -0,0 +1,230 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Prescaler Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: Peripheral clock divided by 2"] + DIV2 = 0, + #[doc = "1: Peripheral clock divided by 4"] + DIV4 = 1, + #[doc = "2: Peripheral clock divided by 8"] + DIV8 = 2, + #[doc = "3: Peripheral clock divided by 16"] + DIV16 = 3, + #[doc = "4: Peripheral clock divided by 32"] + DIV32 = 4, + #[doc = "5: Peripheral clock divided by 64"] + DIV64 = 5, + #[doc = "6: Peripheral clock divided by 128"] + DIV128 = 6, + #[doc = "7: Peripheral clock divided by 256"] + DIV256 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler Configuration"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PRESCALER_A { + match self.bits { + 0 => PRESCALER_A::DIV2, + 1 => PRESCALER_A::DIV4, + 2 => PRESCALER_A::DIV8, + 3 => PRESCALER_A::DIV16, + 4 => PRESCALER_A::DIV32, + 5 => PRESCALER_A::DIV64, + 6 => PRESCALER_A::DIV128, + 7 => PRESCALER_A::DIV256, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == PRESCALER_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == PRESCALER_A::DIV128 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler Configuration"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Peripheral clock divided by 2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "Peripheral clock divided by 4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "Peripheral clock divided by 8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "Peripheral clock divided by 16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "Peripheral clock divided by 32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV32) + } + #[doc = "Peripheral clock divided by 64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "Peripheral clock divided by 128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV128) + } + #[doc = "Peripheral clock divided by 256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Prescaler Configuration"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Prescaler Configuration"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/adc0/ctrlc.rs b/pac/atsamc21n/src/adc0/ctrlc.rs new file mode 100644 index 000000000000..145f8d0f768a --- /dev/null +++ b/pac/atsamc21n/src/adc0/ctrlc.rs @@ -0,0 +1,624 @@ +#[doc = "Register `CTRLC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIFFMODE` reader - Differential Mode"] +pub struct DIFFMODE_R(crate::FieldReader); +impl DIFFMODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIFFMODE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIFFMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIFFMODE` writer - Differential Mode"] +pub struct DIFFMODE_W<'a> { + w: &'a mut W, +} +impl<'a> DIFFMODE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `LEFTADJ` reader - Left-Adjusted Result"] +pub struct LEFTADJ_R(crate::FieldReader); +impl LEFTADJ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LEFTADJ_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LEFTADJ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LEFTADJ` writer - Left-Adjusted Result"] +pub struct LEFTADJ_W<'a> { + w: &'a mut W, +} +impl<'a> LEFTADJ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `FREERUN` reader - Free Running Mode"] +pub struct FREERUN_R(crate::FieldReader); +impl FREERUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FREERUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FREERUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FREERUN` writer - Free Running Mode"] +pub struct FREERUN_W<'a> { + w: &'a mut W, +} +impl<'a> FREERUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CORREN` reader - Digital Correction Logic Enable"] +pub struct CORREN_R(crate::FieldReader); +impl CORREN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CORREN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CORREN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CORREN` writer - Digital Correction Logic Enable"] +pub struct CORREN_W<'a> { + w: &'a mut W, +} +impl<'a> CORREN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Conversion Result Resolution\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum RESSEL_A { + #[doc = "0: 12-bit"] + _12BIT = 0, + #[doc = "1: 16-bit averaging mode"] + _16BIT = 1, + #[doc = "2: 10-bit"] + _10BIT = 2, + #[doc = "3: 8-bit"] + _8BIT = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RESSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `RESSEL` reader - Conversion Result Resolution"] +pub struct RESSEL_R(crate::FieldReader); +impl RESSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RESSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RESSEL_A { + match self.bits { + 0 => RESSEL_A::_12BIT, + 1 => RESSEL_A::_16BIT, + 2 => RESSEL_A::_10BIT, + 3 => RESSEL_A::_8BIT, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `_12BIT`"] + #[inline(always)] + pub fn is_12bit(&self) -> bool { + **self == RESSEL_A::_12BIT + } + #[doc = "Checks if the value of the field is `_16BIT`"] + #[inline(always)] + pub fn is_16bit(&self) -> bool { + **self == RESSEL_A::_16BIT + } + #[doc = "Checks if the value of the field is `_10BIT`"] + #[inline(always)] + pub fn is_10bit(&self) -> bool { + **self == RESSEL_A::_10BIT + } + #[doc = "Checks if the value of the field is `_8BIT`"] + #[inline(always)] + pub fn is_8bit(&self) -> bool { + **self == RESSEL_A::_8BIT + } +} +impl core::ops::Deref for RESSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESSEL` writer - Conversion Result Resolution"] +pub struct RESSEL_W<'a> { + w: &'a mut W, +} +impl<'a> RESSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RESSEL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "12-bit"] + #[inline(always)] + pub fn _12bit(self) -> &'a mut W { + self.variant(RESSEL_A::_12BIT) + } + #[doc = "16-bit averaging mode"] + #[inline(always)] + pub fn _16bit(self) -> &'a mut W { + self.variant(RESSEL_A::_16BIT) + } + #[doc = "10-bit"] + #[inline(always)] + pub fn _10bit(self) -> &'a mut W { + self.variant(RESSEL_A::_10BIT) + } + #[doc = "8-bit"] + #[inline(always)] + pub fn _8bit(self) -> &'a mut W { + self.variant(RESSEL_A::_8BIT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u16 & 0x03) << 4); + self.w + } +} +#[doc = "Field `R2R` reader - Rail-to-Rail mode enable"] +pub struct R2R_R(crate::FieldReader); +impl R2R_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + R2R_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for R2R_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `R2R` writer - Rail-to-Rail mode enable"] +pub struct R2R_W<'a> { + w: &'a mut W, +} +impl<'a> R2R_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Window Monitor Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WINMODE_A { + #[doc = "0: No window mode (default)"] + DISABLE = 0, + #[doc = "1: RESULT > WINLT"] + MODE1 = 1, + #[doc = "2: RESULT < WINUT"] + MODE2 = 2, + #[doc = "3: WINLT < RESULT < WINUT"] + MODE3 = 3, + #[doc = "4: !(WINLT < RESULT < WINUT)"] + MODE4 = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WINMODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `WINMODE` reader - Window Monitor Mode"] +pub struct WINMODE_R(crate::FieldReader); +impl WINMODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WINMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(WINMODE_A::DISABLE), + 1 => Some(WINMODE_A::MODE1), + 2 => Some(WINMODE_A::MODE2), + 3 => Some(WINMODE_A::MODE3), + 4 => Some(WINMODE_A::MODE4), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == WINMODE_A::DISABLE + } + #[doc = "Checks if the value of the field is `MODE1`"] + #[inline(always)] + pub fn is_mode1(&self) -> bool { + **self == WINMODE_A::MODE1 + } + #[doc = "Checks if the value of the field is `MODE2`"] + #[inline(always)] + pub fn is_mode2(&self) -> bool { + **self == WINMODE_A::MODE2 + } + #[doc = "Checks if the value of the field is `MODE3`"] + #[inline(always)] + pub fn is_mode3(&self) -> bool { + **self == WINMODE_A::MODE3 + } + #[doc = "Checks if the value of the field is `MODE4`"] + #[inline(always)] + pub fn is_mode4(&self) -> bool { + **self == WINMODE_A::MODE4 + } +} +impl core::ops::Deref for WINMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMODE` writer - Window Monitor Mode"] +pub struct WINMODE_W<'a> { + w: &'a mut W, +} +impl<'a> WINMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WINMODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No window mode (default)"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(WINMODE_A::DISABLE) + } + #[doc = "RESULT > WINLT"] + #[inline(always)] + pub fn mode1(self) -> &'a mut W { + self.variant(WINMODE_A::MODE1) + } + #[doc = "RESULT < WINUT"] + #[inline(always)] + pub fn mode2(self) -> &'a mut W { + self.variant(WINMODE_A::MODE2) + } + #[doc = "WINLT < RESULT < WINUT"] + #[inline(always)] + pub fn mode3(self) -> &'a mut W { + self.variant(WINMODE_A::MODE3) + } + #[doc = "!(WINLT < RESULT < WINUT)"] + #[inline(always)] + pub fn mode4(self) -> &'a mut W { + self.variant(WINMODE_A::MODE4) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u16 & 0x07) << 8); + self.w + } +} +#[doc = "Dual Mode Trigger Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DUALSEL_A { + #[doc = "0: Start event or software trigger will start a conversion on both ADCs"] + BOTH = 0, + #[doc = "1: START event or software trigger will alternatingly start a conversion on ADC0 and ADC1"] + INTERLEAVE = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DUALSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `DUALSEL` reader - Dual Mode Trigger Selection"] +pub struct DUALSEL_R(crate::FieldReader); +impl DUALSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DUALSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(DUALSEL_A::BOTH), + 1 => Some(DUALSEL_A::INTERLEAVE), + _ => None, + } + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == DUALSEL_A::BOTH + } + #[doc = "Checks if the value of the field is `INTERLEAVE`"] + #[inline(always)] + pub fn is_interleave(&self) -> bool { + **self == DUALSEL_A::INTERLEAVE + } +} +impl core::ops::Deref for DUALSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DUALSEL` writer - Dual Mode Trigger Selection"] +pub struct DUALSEL_W<'a> { + w: &'a mut W, +} +impl<'a> DUALSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DUALSEL_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Start event or software trigger will start a conversion on both ADCs"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(DUALSEL_A::BOTH) + } + #[doc = "START event or software trigger will alternatingly start a conversion on ADC0 and ADC1"] + #[inline(always)] + pub fn interleave(self) -> &'a mut W { + self.variant(DUALSEL_A::INTERLEAVE) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 12)) | ((value as u16 & 0x03) << 12); + self.w + } +} +impl R { + #[doc = "Bit 0 - Differential Mode"] + #[inline(always)] + pub fn diffmode(&self) -> DIFFMODE_R { + DIFFMODE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Left-Adjusted Result"] + #[inline(always)] + pub fn leftadj(&self) -> LEFTADJ_R { + LEFTADJ_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Free Running Mode"] + #[inline(always)] + pub fn freerun(&self) -> FREERUN_R { + FREERUN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Digital Correction Logic Enable"] + #[inline(always)] + pub fn corren(&self) -> CORREN_R { + CORREN_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bits 4:5 - Conversion Result Resolution"] + #[inline(always)] + pub fn ressel(&self) -> RESSEL_R { + RESSEL_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bit 7 - Rail-to-Rail mode enable"] + #[inline(always)] + pub fn r2r(&self) -> R2R_R { + R2R_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Window Monitor Mode"] + #[inline(always)] + pub fn winmode(&self) -> WINMODE_R { + WINMODE_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bits 12:13 - Dual Mode Trigger Selection"] + #[inline(always)] + pub fn dualsel(&self) -> DUALSEL_R { + DUALSEL_R::new(((self.bits >> 12) & 0x03) as u8) + } +} +impl W { + #[doc = "Bit 0 - Differential Mode"] + #[inline(always)] + pub fn diffmode(&mut self) -> DIFFMODE_W { + DIFFMODE_W { w: self } + } + #[doc = "Bit 1 - Left-Adjusted Result"] + #[inline(always)] + pub fn leftadj(&mut self) -> LEFTADJ_W { + LEFTADJ_W { w: self } + } + #[doc = "Bit 2 - Free Running Mode"] + #[inline(always)] + pub fn freerun(&mut self) -> FREERUN_W { + FREERUN_W { w: self } + } + #[doc = "Bit 3 - Digital Correction Logic Enable"] + #[inline(always)] + pub fn corren(&mut self) -> CORREN_W { + CORREN_W { w: self } + } + #[doc = "Bits 4:5 - Conversion Result Resolution"] + #[inline(always)] + pub fn ressel(&mut self) -> RESSEL_W { + RESSEL_W { w: self } + } + #[doc = "Bit 7 - Rail-to-Rail mode enable"] + #[inline(always)] + pub fn r2r(&mut self) -> R2R_W { + R2R_W { w: self } + } + #[doc = "Bits 8:10 - Window Monitor Mode"] + #[inline(always)] + pub fn winmode(&mut self) -> WINMODE_W { + WINMODE_W { w: self } + } + #[doc = "Bits 12:13 - Dual Mode Trigger Selection"] + #[inline(always)] + pub fn dualsel(&mut self) -> DUALSEL_W { + DUALSEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control C\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlc](index.html) module"] +pub struct CTRLC_SPEC; +impl crate::RegisterSpec for CTRLC_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrlc::R](R) reader structure"] +impl crate::Readable for CTRLC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlc::W](W) writer structure"] +impl crate::Writable for CTRLC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLC to value 0"] +impl crate::Resettable for CTRLC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/adc0/dbgctrl.rs b/pac/atsamc21n/src/adc0/dbgctrl.rs new file mode 100644 index 000000000000..53636eb2b339 --- /dev/null +++ b/pac/atsamc21n/src/adc0/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Debug Run"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Debug Run"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/adc0/evctrl.rs b/pac/atsamc21n/src/adc0/evctrl.rs new file mode 100644 index 000000000000..295508f82de3 --- /dev/null +++ b/pac/atsamc21n/src/adc0/evctrl.rs @@ -0,0 +1,348 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FLUSHEI` reader - Flush Event Input Enable"] +pub struct FLUSHEI_R(crate::FieldReader); +impl FLUSHEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FLUSHEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FLUSHEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLUSHEI` writer - Flush Event Input Enable"] +pub struct FLUSHEI_W<'a> { + w: &'a mut W, +} +impl<'a> FLUSHEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `STARTEI` reader - Start Conversion Event Input Enable"] +pub struct STARTEI_R(crate::FieldReader); +impl STARTEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STARTEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STARTEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STARTEI` writer - Start Conversion Event Input Enable"] +pub struct STARTEI_W<'a> { + w: &'a mut W, +} +impl<'a> STARTEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `FLUSHINV` reader - Flush Event Invert Enable"] +pub struct FLUSHINV_R(crate::FieldReader); +impl FLUSHINV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FLUSHINV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FLUSHINV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLUSHINV` writer - Flush Event Invert Enable"] +pub struct FLUSHINV_W<'a> { + w: &'a mut W, +} +impl<'a> FLUSHINV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `STARTINV` reader - Start Event Invert Enable"] +pub struct STARTINV_R(crate::FieldReader); +impl STARTINV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STARTINV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STARTINV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STARTINV` writer - Start Event Invert Enable"] +pub struct STARTINV_W<'a> { + w: &'a mut W, +} +impl<'a> STARTINV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `RESRDYEO` reader - Result Ready Event Out"] +pub struct RESRDYEO_R(crate::FieldReader); +impl RESRDYEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESRDYEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESRDYEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESRDYEO` writer - Result Ready Event Out"] +pub struct RESRDYEO_W<'a> { + w: &'a mut W, +} +impl<'a> RESRDYEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `WINMONEO` reader - Window Monitor Event Out"] +pub struct WINMONEO_R(crate::FieldReader); +impl WINMONEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINMONEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINMONEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMONEO` writer - Window Monitor Event Out"] +pub struct WINMONEO_W<'a> { + w: &'a mut W, +} +impl<'a> WINMONEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Flush Event Input Enable"] + #[inline(always)] + pub fn flushei(&self) -> FLUSHEI_R { + FLUSHEI_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Start Conversion Event Input Enable"] + #[inline(always)] + pub fn startei(&self) -> STARTEI_R { + STARTEI_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Flush Event Invert Enable"] + #[inline(always)] + pub fn flushinv(&self) -> FLUSHINV_R { + FLUSHINV_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Start Event Invert Enable"] + #[inline(always)] + pub fn startinv(&self) -> STARTINV_R { + STARTINV_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Result Ready Event Out"] + #[inline(always)] + pub fn resrdyeo(&self) -> RESRDYEO_R { + RESRDYEO_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Window Monitor Event Out"] + #[inline(always)] + pub fn winmoneo(&self) -> WINMONEO_R { + WINMONEO_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Flush Event Input Enable"] + #[inline(always)] + pub fn flushei(&mut self) -> FLUSHEI_W { + FLUSHEI_W { w: self } + } + #[doc = "Bit 1 - Start Conversion Event Input Enable"] + #[inline(always)] + pub fn startei(&mut self) -> STARTEI_W { + STARTEI_W { w: self } + } + #[doc = "Bit 2 - Flush Event Invert Enable"] + #[inline(always)] + pub fn flushinv(&mut self) -> FLUSHINV_W { + FLUSHINV_W { w: self } + } + #[doc = "Bit 3 - Start Event Invert Enable"] + #[inline(always)] + pub fn startinv(&mut self) -> STARTINV_W { + STARTINV_W { w: self } + } + #[doc = "Bit 4 - Result Ready Event Out"] + #[inline(always)] + pub fn resrdyeo(&mut self) -> RESRDYEO_W { + RESRDYEO_W { w: self } + } + #[doc = "Bit 5 - Window Monitor Event Out"] + #[inline(always)] + pub fn winmoneo(&mut self) -> WINMONEO_W { + WINMONEO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/adc0/gaincorr.rs b/pac/atsamc21n/src/adc0/gaincorr.rs new file mode 100644 index 000000000000..496cb8c6021c --- /dev/null +++ b/pac/atsamc21n/src/adc0/gaincorr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `GAINCORR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GAINCORR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `GAINCORR` reader - Gain Correction Value"] +pub struct GAINCORR_R(crate::FieldReader); +impl GAINCORR_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + GAINCORR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GAINCORR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GAINCORR` writer - Gain Correction Value"] +pub struct GAINCORR_W<'a> { + w: &'a mut W, +} +impl<'a> GAINCORR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0fff) | (value as u16 & 0x0fff); + self.w + } +} +impl R { + #[doc = "Bits 0:11 - Gain Correction Value"] + #[inline(always)] + pub fn gaincorr(&self) -> GAINCORR_R { + GAINCORR_R::new((self.bits & 0x0fff) as u16) + } +} +impl W { + #[doc = "Bits 0:11 - Gain Correction Value"] + #[inline(always)] + pub fn gaincorr(&mut self) -> GAINCORR_W { + GAINCORR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Gain Correction\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gaincorr](index.html) module"] +pub struct GAINCORR_SPEC; +impl crate::RegisterSpec for GAINCORR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [gaincorr::R](R) reader structure"] +impl crate::Readable for GAINCORR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gaincorr::W](W) writer structure"] +impl crate::Writable for GAINCORR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets GAINCORR to value 0"] +impl crate::Resettable for GAINCORR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/adc0/inputctrl.rs b/pac/atsamc21n/src/adc0/inputctrl.rs new file mode 100644 index 000000000000..3b36f08c6414 --- /dev/null +++ b/pac/atsamc21n/src/adc0/inputctrl.rs @@ -0,0 +1,498 @@ +#[doc = "Register `INPUTCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INPUTCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Positive Mux Input Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MUXPOS_A { + #[doc = "0: ADC AIN0 Pin"] + AIN0 = 0, + #[doc = "1: ADC AIN1 Pin"] + AIN1 = 1, + #[doc = "2: ADC AIN2 Pin"] + AIN2 = 2, + #[doc = "3: ADC AIN3 Pin"] + AIN3 = 3, + #[doc = "4: ADC AIN4 Pin"] + AIN4 = 4, + #[doc = "5: ADC AIN5 Pin"] + AIN5 = 5, + #[doc = "6: ADC AIN6 Pin"] + AIN6 = 6, + #[doc = "7: ADC AIN7 Pin"] + AIN7 = 7, + #[doc = "8: ADC AIN8 Pin"] + AIN8 = 8, + #[doc = "9: ADC AIN9 Pin"] + AIN9 = 9, + #[doc = "10: ADC AIN10 Pin"] + AIN10 = 10, + #[doc = "11: ADC AIN11 Pin"] + AIN11 = 11, + #[doc = "24: Temperature Sensor"] + TEMP = 24, + #[doc = "25: Bandgap Voltage"] + BANDGAP = 25, + #[doc = "26: 1/4 Scaled Core Supply"] + SCALEDCOREVCC = 26, + #[doc = "27: 1/4 Scaled I/O Supply"] + SCALEDIOVCC = 27, + #[doc = "28: DAC Output"] + DAC = 28, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MUXPOS_A) -> Self { + variant as _ + } +} +#[doc = "Field `MUXPOS` reader - Positive Mux Input Selection"] +pub struct MUXPOS_R(crate::FieldReader); +impl MUXPOS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MUXPOS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MUXPOS_A::AIN0), + 1 => Some(MUXPOS_A::AIN1), + 2 => Some(MUXPOS_A::AIN2), + 3 => Some(MUXPOS_A::AIN3), + 4 => Some(MUXPOS_A::AIN4), + 5 => Some(MUXPOS_A::AIN5), + 6 => Some(MUXPOS_A::AIN6), + 7 => Some(MUXPOS_A::AIN7), + 8 => Some(MUXPOS_A::AIN8), + 9 => Some(MUXPOS_A::AIN9), + 10 => Some(MUXPOS_A::AIN10), + 11 => Some(MUXPOS_A::AIN11), + 24 => Some(MUXPOS_A::TEMP), + 25 => Some(MUXPOS_A::BANDGAP), + 26 => Some(MUXPOS_A::SCALEDCOREVCC), + 27 => Some(MUXPOS_A::SCALEDIOVCC), + 28 => Some(MUXPOS_A::DAC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `AIN0`"] + #[inline(always)] + pub fn is_ain0(&self) -> bool { + **self == MUXPOS_A::AIN0 + } + #[doc = "Checks if the value of the field is `AIN1`"] + #[inline(always)] + pub fn is_ain1(&self) -> bool { + **self == MUXPOS_A::AIN1 + } + #[doc = "Checks if the value of the field is `AIN2`"] + #[inline(always)] + pub fn is_ain2(&self) -> bool { + **self == MUXPOS_A::AIN2 + } + #[doc = "Checks if the value of the field is `AIN3`"] + #[inline(always)] + pub fn is_ain3(&self) -> bool { + **self == MUXPOS_A::AIN3 + } + #[doc = "Checks if the value of the field is `AIN4`"] + #[inline(always)] + pub fn is_ain4(&self) -> bool { + **self == MUXPOS_A::AIN4 + } + #[doc = "Checks if the value of the field is `AIN5`"] + #[inline(always)] + pub fn is_ain5(&self) -> bool { + **self == MUXPOS_A::AIN5 + } + #[doc = "Checks if the value of the field is `AIN6`"] + #[inline(always)] + pub fn is_ain6(&self) -> bool { + **self == MUXPOS_A::AIN6 + } + #[doc = "Checks if the value of the field is `AIN7`"] + #[inline(always)] + pub fn is_ain7(&self) -> bool { + **self == MUXPOS_A::AIN7 + } + #[doc = "Checks if the value of the field is `AIN8`"] + #[inline(always)] + pub fn is_ain8(&self) -> bool { + **self == MUXPOS_A::AIN8 + } + #[doc = "Checks if the value of the field is `AIN9`"] + #[inline(always)] + pub fn is_ain9(&self) -> bool { + **self == MUXPOS_A::AIN9 + } + #[doc = "Checks if the value of the field is `AIN10`"] + #[inline(always)] + pub fn is_ain10(&self) -> bool { + **self == MUXPOS_A::AIN10 + } + #[doc = "Checks if the value of the field is `AIN11`"] + #[inline(always)] + pub fn is_ain11(&self) -> bool { + **self == MUXPOS_A::AIN11 + } + #[doc = "Checks if the value of the field is `TEMP`"] + #[inline(always)] + pub fn is_temp(&self) -> bool { + **self == MUXPOS_A::TEMP + } + #[doc = "Checks if the value of the field is `BANDGAP`"] + #[inline(always)] + pub fn is_bandgap(&self) -> bool { + **self == MUXPOS_A::BANDGAP + } + #[doc = "Checks if the value of the field is `SCALEDCOREVCC`"] + #[inline(always)] + pub fn is_scaledcorevcc(&self) -> bool { + **self == MUXPOS_A::SCALEDCOREVCC + } + #[doc = "Checks if the value of the field is `SCALEDIOVCC`"] + #[inline(always)] + pub fn is_scalediovcc(&self) -> bool { + **self == MUXPOS_A::SCALEDIOVCC + } + #[doc = "Checks if the value of the field is `DAC`"] + #[inline(always)] + pub fn is_dac(&self) -> bool { + **self == MUXPOS_A::DAC + } +} +impl core::ops::Deref for MUXPOS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MUXPOS` writer - Positive Mux Input Selection"] +pub struct MUXPOS_W<'a> { + w: &'a mut W, +} +impl<'a> MUXPOS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MUXPOS_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "ADC AIN0 Pin"] + #[inline(always)] + pub fn ain0(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN0) + } + #[doc = "ADC AIN1 Pin"] + #[inline(always)] + pub fn ain1(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN1) + } + #[doc = "ADC AIN2 Pin"] + #[inline(always)] + pub fn ain2(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN2) + } + #[doc = "ADC AIN3 Pin"] + #[inline(always)] + pub fn ain3(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN3) + } + #[doc = "ADC AIN4 Pin"] + #[inline(always)] + pub fn ain4(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN4) + } + #[doc = "ADC AIN5 Pin"] + #[inline(always)] + pub fn ain5(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN5) + } + #[doc = "ADC AIN6 Pin"] + #[inline(always)] + pub fn ain6(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN6) + } + #[doc = "ADC AIN7 Pin"] + #[inline(always)] + pub fn ain7(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN7) + } + #[doc = "ADC AIN8 Pin"] + #[inline(always)] + pub fn ain8(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN8) + } + #[doc = "ADC AIN9 Pin"] + #[inline(always)] + pub fn ain9(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN9) + } + #[doc = "ADC AIN10 Pin"] + #[inline(always)] + pub fn ain10(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN10) + } + #[doc = "ADC AIN11 Pin"] + #[inline(always)] + pub fn ain11(self) -> &'a mut W { + self.variant(MUXPOS_A::AIN11) + } + #[doc = "Temperature Sensor"] + #[inline(always)] + pub fn temp(self) -> &'a mut W { + self.variant(MUXPOS_A::TEMP) + } + #[doc = "Bandgap Voltage"] + #[inline(always)] + pub fn bandgap(self) -> &'a mut W { + self.variant(MUXPOS_A::BANDGAP) + } + #[doc = "1/4 Scaled Core Supply"] + #[inline(always)] + pub fn scaledcorevcc(self) -> &'a mut W { + self.variant(MUXPOS_A::SCALEDCOREVCC) + } + #[doc = "1/4 Scaled I/O Supply"] + #[inline(always)] + pub fn scalediovcc(self) -> &'a mut W { + self.variant(MUXPOS_A::SCALEDIOVCC) + } + #[doc = "DAC Output"] + #[inline(always)] + pub fn dac(self) -> &'a mut W { + self.variant(MUXPOS_A::DAC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u16 & 0x1f); + self.w + } +} +#[doc = "Negative Mux Input Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MUXNEG_A { + #[doc = "0: ADC AIN0 Pin"] + AIN0 = 0, + #[doc = "1: ADC AIN1 Pin"] + AIN1 = 1, + #[doc = "2: ADC AIN2 Pin"] + AIN2 = 2, + #[doc = "3: ADC AIN3 Pin"] + AIN3 = 3, + #[doc = "4: ADC AIN4 Pin"] + AIN4 = 4, + #[doc = "5: ADC AIN5 Pin"] + AIN5 = 5, + #[doc = "24: Internal Ground"] + GND = 24, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MUXNEG_A) -> Self { + variant as _ + } +} +#[doc = "Field `MUXNEG` reader - Negative Mux Input Selection"] +pub struct MUXNEG_R(crate::FieldReader); +impl MUXNEG_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MUXNEG_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MUXNEG_A::AIN0), + 1 => Some(MUXNEG_A::AIN1), + 2 => Some(MUXNEG_A::AIN2), + 3 => Some(MUXNEG_A::AIN3), + 4 => Some(MUXNEG_A::AIN4), + 5 => Some(MUXNEG_A::AIN5), + 24 => Some(MUXNEG_A::GND), + _ => None, + } + } + #[doc = "Checks if the value of the field is `AIN0`"] + #[inline(always)] + pub fn is_ain0(&self) -> bool { + **self == MUXNEG_A::AIN0 + } + #[doc = "Checks if the value of the field is `AIN1`"] + #[inline(always)] + pub fn is_ain1(&self) -> bool { + **self == MUXNEG_A::AIN1 + } + #[doc = "Checks if the value of the field is `AIN2`"] + #[inline(always)] + pub fn is_ain2(&self) -> bool { + **self == MUXNEG_A::AIN2 + } + #[doc = "Checks if the value of the field is `AIN3`"] + #[inline(always)] + pub fn is_ain3(&self) -> bool { + **self == MUXNEG_A::AIN3 + } + #[doc = "Checks if the value of the field is `AIN4`"] + #[inline(always)] + pub fn is_ain4(&self) -> bool { + **self == MUXNEG_A::AIN4 + } + #[doc = "Checks if the value of the field is `AIN5`"] + #[inline(always)] + pub fn is_ain5(&self) -> bool { + **self == MUXNEG_A::AIN5 + } + #[doc = "Checks if the value of the field is `GND`"] + #[inline(always)] + pub fn is_gnd(&self) -> bool { + **self == MUXNEG_A::GND + } +} +impl core::ops::Deref for MUXNEG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MUXNEG` writer - Negative Mux Input Selection"] +pub struct MUXNEG_W<'a> { + w: &'a mut W, +} +impl<'a> MUXNEG_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MUXNEG_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "ADC AIN0 Pin"] + #[inline(always)] + pub fn ain0(self) -> &'a mut W { + self.variant(MUXNEG_A::AIN0) + } + #[doc = "ADC AIN1 Pin"] + #[inline(always)] + pub fn ain1(self) -> &'a mut W { + self.variant(MUXNEG_A::AIN1) + } + #[doc = "ADC AIN2 Pin"] + #[inline(always)] + pub fn ain2(self) -> &'a mut W { + self.variant(MUXNEG_A::AIN2) + } + #[doc = "ADC AIN3 Pin"] + #[inline(always)] + pub fn ain3(self) -> &'a mut W { + self.variant(MUXNEG_A::AIN3) + } + #[doc = "ADC AIN4 Pin"] + #[inline(always)] + pub fn ain4(self) -> &'a mut W { + self.variant(MUXNEG_A::AIN4) + } + #[doc = "ADC AIN5 Pin"] + #[inline(always)] + pub fn ain5(self) -> &'a mut W { + self.variant(MUXNEG_A::AIN5) + } + #[doc = "Internal Ground"] + #[inline(always)] + pub fn gnd(self) -> &'a mut W { + self.variant(MUXNEG_A::GND) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 8)) | ((value as u16 & 0x1f) << 8); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Positive Mux Input Selection"] + #[inline(always)] + pub fn muxpos(&self) -> MUXPOS_R { + MUXPOS_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 8:12 - Negative Mux Input Selection"] + #[inline(always)] + pub fn muxneg(&self) -> MUXNEG_R { + MUXNEG_R::new(((self.bits >> 8) & 0x1f) as u8) + } +} +impl W { + #[doc = "Bits 0:4 - Positive Mux Input Selection"] + #[inline(always)] + pub fn muxpos(&mut self) -> MUXPOS_W { + MUXPOS_W { w: self } + } + #[doc = "Bits 8:12 - Negative Mux Input Selection"] + #[inline(always)] + pub fn muxneg(&mut self) -> MUXNEG_W { + MUXNEG_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Input Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [inputctrl](index.html) module"] +pub struct INPUTCTRL_SPEC; +impl crate::RegisterSpec for INPUTCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [inputctrl::R](R) reader structure"] +impl crate::Readable for INPUTCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [inputctrl::W](W) writer structure"] +impl crate::Writable for INPUTCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INPUTCTRL to value 0"] +impl crate::Resettable for INPUTCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/adc0/intenclr.rs b/pac/atsamc21n/src/adc0/intenclr.rs new file mode 100644 index 000000000000..b10f428d30b1 --- /dev/null +++ b/pac/atsamc21n/src/adc0/intenclr.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RESRDY` reader - Result Ready Interrupt Disable"] +pub struct RESRDY_R(crate::FieldReader); +impl RESRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESRDY` writer - Result Ready Interrupt Disable"] +pub struct RESRDY_W<'a> { + w: &'a mut W, +} +impl<'a> RESRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `OVERRUN` reader - Overrun Interrupt Disable"] +pub struct OVERRUN_R(crate::FieldReader); +impl OVERRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVERRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVERRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVERRUN` writer - Overrun Interrupt Disable"] +pub struct OVERRUN_W<'a> { + w: &'a mut W, +} +impl<'a> OVERRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WINMON` reader - Window Monitor Interrupt Disable"] +pub struct WINMON_R(crate::FieldReader); +impl WINMON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINMON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINMON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMON` writer - Window Monitor Interrupt Disable"] +pub struct WINMON_W<'a> { + w: &'a mut W, +} +impl<'a> WINMON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Result Ready Interrupt Disable"] + #[inline(always)] + pub fn resrdy(&self) -> RESRDY_R { + RESRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Overrun Interrupt Disable"] + #[inline(always)] + pub fn overrun(&self) -> OVERRUN_R { + OVERRUN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Window Monitor Interrupt Disable"] + #[inline(always)] + pub fn winmon(&self) -> WINMON_R { + WINMON_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Result Ready Interrupt Disable"] + #[inline(always)] + pub fn resrdy(&mut self) -> RESRDY_W { + RESRDY_W { w: self } + } + #[doc = "Bit 1 - Overrun Interrupt Disable"] + #[inline(always)] + pub fn overrun(&mut self) -> OVERRUN_W { + OVERRUN_W { w: self } + } + #[doc = "Bit 2 - Window Monitor Interrupt Disable"] + #[inline(always)] + pub fn winmon(&mut self) -> WINMON_W { + WINMON_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/adc0/intenset.rs b/pac/atsamc21n/src/adc0/intenset.rs new file mode 100644 index 000000000000..5ca93b05b859 --- /dev/null +++ b/pac/atsamc21n/src/adc0/intenset.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RESRDY` reader - Result Ready Interrupt Enable"] +pub struct RESRDY_R(crate::FieldReader); +impl RESRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESRDY` writer - Result Ready Interrupt Enable"] +pub struct RESRDY_W<'a> { + w: &'a mut W, +} +impl<'a> RESRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `OVERRUN` reader - Overrun Interrupt Enable"] +pub struct OVERRUN_R(crate::FieldReader); +impl OVERRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVERRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVERRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVERRUN` writer - Overrun Interrupt Enable"] +pub struct OVERRUN_W<'a> { + w: &'a mut W, +} +impl<'a> OVERRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WINMON` reader - Window Monitor Interrupt Enable"] +pub struct WINMON_R(crate::FieldReader); +impl WINMON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINMON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINMON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMON` writer - Window Monitor Interrupt Enable"] +pub struct WINMON_W<'a> { + w: &'a mut W, +} +impl<'a> WINMON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Result Ready Interrupt Enable"] + #[inline(always)] + pub fn resrdy(&self) -> RESRDY_R { + RESRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Overrun Interrupt Enable"] + #[inline(always)] + pub fn overrun(&self) -> OVERRUN_R { + OVERRUN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Window Monitor Interrupt Enable"] + #[inline(always)] + pub fn winmon(&self) -> WINMON_R { + WINMON_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Result Ready Interrupt Enable"] + #[inline(always)] + pub fn resrdy(&mut self) -> RESRDY_W { + RESRDY_W { w: self } + } + #[doc = "Bit 1 - Overrun Interrupt Enable"] + #[inline(always)] + pub fn overrun(&mut self) -> OVERRUN_W { + OVERRUN_W { w: self } + } + #[doc = "Bit 2 - Window Monitor Interrupt Enable"] + #[inline(always)] + pub fn winmon(&mut self) -> WINMON_W { + WINMON_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/adc0/intflag.rs b/pac/atsamc21n/src/adc0/intflag.rs new file mode 100644 index 000000000000..3cd74788b226 --- /dev/null +++ b/pac/atsamc21n/src/adc0/intflag.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RESRDY` reader - Result Ready Interrupt Flag"] +pub struct RESRDY_R(crate::FieldReader); +impl RESRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESRDY` writer - Result Ready Interrupt Flag"] +pub struct RESRDY_W<'a> { + w: &'a mut W, +} +impl<'a> RESRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `OVERRUN` reader - Overrun Interrupt Flag"] +pub struct OVERRUN_R(crate::FieldReader); +impl OVERRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVERRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVERRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVERRUN` writer - Overrun Interrupt Flag"] +pub struct OVERRUN_W<'a> { + w: &'a mut W, +} +impl<'a> OVERRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WINMON` reader - Window Monitor Interrupt Flag"] +pub struct WINMON_R(crate::FieldReader); +impl WINMON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINMON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINMON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMON` writer - Window Monitor Interrupt Flag"] +pub struct WINMON_W<'a> { + w: &'a mut W, +} +impl<'a> WINMON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Result Ready Interrupt Flag"] + #[inline(always)] + pub fn resrdy(&self) -> RESRDY_R { + RESRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Overrun Interrupt Flag"] + #[inline(always)] + pub fn overrun(&self) -> OVERRUN_R { + OVERRUN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Window Monitor Interrupt Flag"] + #[inline(always)] + pub fn winmon(&self) -> WINMON_R { + WINMON_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Result Ready Interrupt Flag"] + #[inline(always)] + pub fn resrdy(&mut self) -> RESRDY_W { + RESRDY_W { w: self } + } + #[doc = "Bit 1 - Overrun Interrupt Flag"] + #[inline(always)] + pub fn overrun(&mut self) -> OVERRUN_W { + OVERRUN_W { w: self } + } + #[doc = "Bit 2 - Window Monitor Interrupt Flag"] + #[inline(always)] + pub fn winmon(&mut self) -> WINMON_W { + WINMON_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/adc0/offsetcorr.rs b/pac/atsamc21n/src/adc0/offsetcorr.rs new file mode 100644 index 000000000000..24a97427c64e --- /dev/null +++ b/pac/atsamc21n/src/adc0/offsetcorr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `OFFSETCORR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OFFSETCORR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OFFSETCORR` reader - Offset Correction Value"] +pub struct OFFSETCORR_R(crate::FieldReader); +impl OFFSETCORR_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + OFFSETCORR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OFFSETCORR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OFFSETCORR` writer - Offset Correction Value"] +pub struct OFFSETCORR_W<'a> { + w: &'a mut W, +} +impl<'a> OFFSETCORR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0fff) | (value as u16 & 0x0fff); + self.w + } +} +impl R { + #[doc = "Bits 0:11 - Offset Correction Value"] + #[inline(always)] + pub fn offsetcorr(&self) -> OFFSETCORR_R { + OFFSETCORR_R::new((self.bits & 0x0fff) as u16) + } +} +impl W { + #[doc = "Bits 0:11 - Offset Correction Value"] + #[inline(always)] + pub fn offsetcorr(&mut self) -> OFFSETCORR_W { + OFFSETCORR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Offset Correction\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [offsetcorr](index.html) module"] +pub struct OFFSETCORR_SPEC; +impl crate::RegisterSpec for OFFSETCORR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [offsetcorr::R](R) reader structure"] +impl crate::Readable for OFFSETCORR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [offsetcorr::W](W) writer structure"] +impl crate::Writable for OFFSETCORR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OFFSETCORR to value 0"] +impl crate::Resettable for OFFSETCORR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/adc0/refctrl.rs b/pac/atsamc21n/src/adc0/refctrl.rs new file mode 100644 index 000000000000..007d86e306bc --- /dev/null +++ b/pac/atsamc21n/src/adc0/refctrl.rs @@ -0,0 +1,251 @@ +#[doc = "Register `REFCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `REFCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Reference Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum REFSEL_A { + #[doc = "0: Internal Bandgap Reference"] + INTREF = 0, + #[doc = "1: 1/1.6 VDDANA"] + INTVCC0 = 1, + #[doc = "2: 1/2 VDDANA"] + INTVCC1 = 2, + #[doc = "3: External Reference"] + AREFA = 3, + #[doc = "4: DAC"] + DAC = 4, + #[doc = "5: VDDANA"] + INTVCC2 = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: REFSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `REFSEL` reader - Reference Selection"] +pub struct REFSEL_R(crate::FieldReader); +impl REFSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REFSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(REFSEL_A::INTREF), + 1 => Some(REFSEL_A::INTVCC0), + 2 => Some(REFSEL_A::INTVCC1), + 3 => Some(REFSEL_A::AREFA), + 4 => Some(REFSEL_A::DAC), + 5 => Some(REFSEL_A::INTVCC2), + _ => None, + } + } + #[doc = "Checks if the value of the field is `INTREF`"] + #[inline(always)] + pub fn is_intref(&self) -> bool { + **self == REFSEL_A::INTREF + } + #[doc = "Checks if the value of the field is `INTVCC0`"] + #[inline(always)] + pub fn is_intvcc0(&self) -> bool { + **self == REFSEL_A::INTVCC0 + } + #[doc = "Checks if the value of the field is `INTVCC1`"] + #[inline(always)] + pub fn is_intvcc1(&self) -> bool { + **self == REFSEL_A::INTVCC1 + } + #[doc = "Checks if the value of the field is `AREFA`"] + #[inline(always)] + pub fn is_arefa(&self) -> bool { + **self == REFSEL_A::AREFA + } + #[doc = "Checks if the value of the field is `DAC`"] + #[inline(always)] + pub fn is_dac(&self) -> bool { + **self == REFSEL_A::DAC + } + #[doc = "Checks if the value of the field is `INTVCC2`"] + #[inline(always)] + pub fn is_intvcc2(&self) -> bool { + **self == REFSEL_A::INTVCC2 + } +} +impl core::ops::Deref for REFSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REFSEL` writer - Reference Selection"] +pub struct REFSEL_W<'a> { + w: &'a mut W, +} +impl<'a> REFSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: REFSEL_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Internal Bandgap Reference"] + #[inline(always)] + pub fn intref(self) -> &'a mut W { + self.variant(REFSEL_A::INTREF) + } + #[doc = "1/1.6 VDDANA"] + #[inline(always)] + pub fn intvcc0(self) -> &'a mut W { + self.variant(REFSEL_A::INTVCC0) + } + #[doc = "1/2 VDDANA"] + #[inline(always)] + pub fn intvcc1(self) -> &'a mut W { + self.variant(REFSEL_A::INTVCC1) + } + #[doc = "External Reference"] + #[inline(always)] + pub fn arefa(self) -> &'a mut W { + self.variant(REFSEL_A::AREFA) + } + #[doc = "DAC"] + #[inline(always)] + pub fn dac(self) -> &'a mut W { + self.variant(REFSEL_A::DAC) + } + #[doc = "VDDANA"] + #[inline(always)] + pub fn intvcc2(self) -> &'a mut W { + self.variant(REFSEL_A::INTVCC2) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +#[doc = "Field `REFCOMP` reader - Reference Buffer Offset Compensation Enable"] +pub struct REFCOMP_R(crate::FieldReader); +impl REFCOMP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + REFCOMP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REFCOMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REFCOMP` writer - Reference Buffer Offset Compensation Enable"] +pub struct REFCOMP_W<'a> { + w: &'a mut W, +} +impl<'a> REFCOMP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Reference Selection"] + #[inline(always)] + pub fn refsel(&self) -> REFSEL_R { + REFSEL_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 7 - Reference Buffer Offset Compensation Enable"] + #[inline(always)] + pub fn refcomp(&self) -> REFCOMP_R { + REFCOMP_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Reference Selection"] + #[inline(always)] + pub fn refsel(&mut self) -> REFSEL_W { + REFSEL_W { w: self } + } + #[doc = "Bit 7 - Reference Buffer Offset Compensation Enable"] + #[inline(always)] + pub fn refcomp(&mut self) -> REFCOMP_W { + REFCOMP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Reference Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [refctrl](index.html) module"] +pub struct REFCTRL_SPEC; +impl crate::RegisterSpec for REFCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [refctrl::R](R) reader structure"] +impl crate::Readable for REFCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [refctrl::W](W) writer structure"] +impl crate::Writable for REFCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets REFCTRL to value 0"] +impl crate::Resettable for REFCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/adc0/result.rs b/pac/atsamc21n/src/adc0/result.rs new file mode 100644 index 000000000000..b63b08cc72b9 --- /dev/null +++ b/pac/atsamc21n/src/adc0/result.rs @@ -0,0 +1,53 @@ +#[doc = "Register `RESULT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `RESULT` reader - Result Value"] +pub struct RESULT_R(crate::FieldReader); +impl RESULT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + RESULT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESULT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:15 - Result Value"] + #[inline(always)] + pub fn result(&self) -> RESULT_R { + RESULT_R::new(self.bits as u16) + } +} +#[doc = "Result\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [result](index.html) module"] +pub struct RESULT_SPEC; +impl crate::RegisterSpec for RESULT_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [result::R](R) reader structure"] +impl crate::Readable for RESULT_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets RESULT to value 0"] +impl crate::Resettable for RESULT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/adc0/sampctrl.rs b/pac/atsamc21n/src/adc0/sampctrl.rs new file mode 100644 index 000000000000..be4b77a80410 --- /dev/null +++ b/pac/atsamc21n/src/adc0/sampctrl.rs @@ -0,0 +1,150 @@ +#[doc = "Register `SAMPCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SAMPCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SAMPLEN` reader - Sampling Time Length"] +pub struct SAMPLEN_R(crate::FieldReader); +impl SAMPLEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SAMPLEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SAMPLEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SAMPLEN` writer - Sampling Time Length"] +pub struct SAMPLEN_W<'a> { + w: &'a mut W, +} +impl<'a> SAMPLEN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u8 & 0x3f); + self.w + } +} +#[doc = "Field `OFFCOMP` reader - Comparator Offset Compensation Enable"] +pub struct OFFCOMP_R(crate::FieldReader); +impl OFFCOMP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OFFCOMP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OFFCOMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OFFCOMP` writer - Comparator Offset Compensation Enable"] +pub struct OFFCOMP_W<'a> { + w: &'a mut W, +} +impl<'a> OFFCOMP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Sampling Time Length"] + #[inline(always)] + pub fn samplen(&self) -> SAMPLEN_R { + SAMPLEN_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 7 - Comparator Offset Compensation Enable"] + #[inline(always)] + pub fn offcomp(&self) -> OFFCOMP_R { + OFFCOMP_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:5 - Sampling Time Length"] + #[inline(always)] + pub fn samplen(&mut self) -> SAMPLEN_W { + SAMPLEN_W { w: self } + } + #[doc = "Bit 7 - Comparator Offset Compensation Enable"] + #[inline(always)] + pub fn offcomp(&mut self) -> OFFCOMP_W { + OFFCOMP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Sample Time Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sampctrl](index.html) module"] +pub struct SAMPCTRL_SPEC; +impl crate::RegisterSpec for SAMPCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [sampctrl::R](R) reader structure"] +impl crate::Readable for SAMPCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [sampctrl::W](W) writer structure"] +impl crate::Writable for SAMPCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SAMPCTRL to value 0"] +impl crate::Resettable for SAMPCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/adc0/seqctrl.rs b/pac/atsamc21n/src/adc0/seqctrl.rs new file mode 100644 index 000000000000..c8388c9a393f --- /dev/null +++ b/pac/atsamc21n/src/adc0/seqctrl.rs @@ -0,0 +1,103 @@ +#[doc = "Register `SEQCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SEQCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SEQEN` reader - Enable Positive Input in the Sequence"] +pub struct SEQEN_R(crate::FieldReader); +impl SEQEN_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + SEQEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEQEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEQEN` writer - Enable Positive Input in the Sequence"] +pub struct SEQEN_W<'a> { + w: &'a mut W, +} +impl<'a> SEQEN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Enable Positive Input in the Sequence"] + #[inline(always)] + pub fn seqen(&self) -> SEQEN_R { + SEQEN_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Enable Positive Input in the Sequence"] + #[inline(always)] + pub fn seqen(&mut self) -> SEQEN_W { + SEQEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Sequence Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [seqctrl](index.html) module"] +pub struct SEQCTRL_SPEC; +impl crate::RegisterSpec for SEQCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [seqctrl::R](R) reader structure"] +impl crate::Readable for SEQCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [seqctrl::W](W) writer structure"] +impl crate::Writable for SEQCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SEQCTRL to value 0"] +impl crate::Resettable for SEQCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/adc0/seqstatus.rs b/pac/atsamc21n/src/adc0/seqstatus.rs new file mode 100644 index 000000000000..42c820892e9a --- /dev/null +++ b/pac/atsamc21n/src/adc0/seqstatus.rs @@ -0,0 +1,73 @@ +#[doc = "Register `SEQSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SEQSTATE` reader - Sequence State"] +pub struct SEQSTATE_R(crate::FieldReader); +impl SEQSTATE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SEQSTATE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEQSTATE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEQBUSY` reader - Sequence Busy"] +pub struct SEQBUSY_R(crate::FieldReader); +impl SEQBUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SEQBUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEQBUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:4 - Sequence State"] + #[inline(always)] + pub fn seqstate(&self) -> SEQSTATE_R { + SEQSTATE_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bit 7 - Sequence Busy"] + #[inline(always)] + pub fn seqbusy(&self) -> SEQBUSY_R { + SEQBUSY_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +#[doc = "Sequence Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [seqstatus](index.html) module"] +pub struct SEQSTATUS_SPEC; +impl crate::RegisterSpec for SEQSTATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [seqstatus::R](R) reader structure"] +impl crate::Readable for SEQSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SEQSTATUS to value 0"] +impl crate::Resettable for SEQSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/adc0/swtrig.rs b/pac/atsamc21n/src/adc0/swtrig.rs new file mode 100644 index 000000000000..5e23ed7865ed --- /dev/null +++ b/pac/atsamc21n/src/adc0/swtrig.rs @@ -0,0 +1,160 @@ +#[doc = "Register `SWTRIG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SWTRIG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FLUSH` reader - ADC Flush"] +pub struct FLUSH_R(crate::FieldReader); +impl FLUSH_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FLUSH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FLUSH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLUSH` writer - ADC Flush"] +pub struct FLUSH_W<'a> { + w: &'a mut W, +} +impl<'a> FLUSH_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `START` reader - Start ADC Conversion"] +pub struct START_R(crate::FieldReader); +impl START_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + START_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for START_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `START` writer - Start ADC Conversion"] +pub struct START_W<'a> { + w: &'a mut W, +} +impl<'a> START_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - ADC Flush"] + #[inline(always)] + pub fn flush(&self) -> FLUSH_R { + FLUSH_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Start ADC Conversion"] + #[inline(always)] + pub fn start(&self) -> START_R { + START_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - ADC Flush"] + #[inline(always)] + pub fn flush(&mut self) -> FLUSH_W { + FLUSH_W { w: self } + } + #[doc = "Bit 1 - Start ADC Conversion"] + #[inline(always)] + pub fn start(&mut self) -> START_W { + START_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Software Trigger\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [swtrig](index.html) module"] +pub struct SWTRIG_SPEC; +impl crate::RegisterSpec for SWTRIG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [swtrig::R](R) reader structure"] +impl crate::Readable for SWTRIG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [swtrig::W](W) writer structure"] +impl crate::Writable for SWTRIG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SWTRIG to value 0"] +impl crate::Resettable for SWTRIG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/adc0/syncbusy.rs b/pac/atsamc21n/src/adc0/syncbusy.rs new file mode 100644 index 000000000000..9c92da8a7c74 --- /dev/null +++ b/pac/atsamc21n/src/adc0/syncbusy.rs @@ -0,0 +1,253 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - SWRST Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - ENABLE Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INPUTCTRL` reader - INPUTCTRL Synchronization Busy"] +pub struct INPUTCTRL_R(crate::FieldReader); +impl INPUTCTRL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INPUTCTRL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INPUTCTRL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLC` reader - CTRLC Synchronization Busy"] +pub struct CTRLC_R(crate::FieldReader); +impl CTRLC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AVGCTRL` reader - AVGCTRL Synchronization Busy"] +pub struct AVGCTRL_R(crate::FieldReader); +impl AVGCTRL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AVGCTRL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AVGCTRL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SAMPCTRL` reader - SAMPCTRL Synchronization Busy"] +pub struct SAMPCTRL_R(crate::FieldReader); +impl SAMPCTRL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SAMPCTRL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SAMPCTRL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINLT` reader - WINLT Synchronization Busy"] +pub struct WINLT_R(crate::FieldReader); +impl WINLT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINLT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINLT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINUT` reader - WINUT Synchronization Busy"] +pub struct WINUT_R(crate::FieldReader); +impl WINUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GAINCORR` reader - GAINCORR Synchronization Busy"] +pub struct GAINCORR_R(crate::FieldReader); +impl GAINCORR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GAINCORR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GAINCORR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OFFSETCORR` reader - OFFSETCTRL Synchronization Busy"] +pub struct OFFSETCORR_R(crate::FieldReader); +impl OFFSETCORR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OFFSETCORR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OFFSETCORR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG` reader - SWTRG Synchronization Busy"] +pub struct SWTRIG_R(crate::FieldReader); +impl SWTRIG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - SWRST Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ENABLE Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - INPUTCTRL Synchronization Busy"] + #[inline(always)] + pub fn inputctrl(&self) -> INPUTCTRL_R { + INPUTCTRL_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - CTRLC Synchronization Busy"] + #[inline(always)] + pub fn ctrlc(&self) -> CTRLC_R { + CTRLC_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - AVGCTRL Synchronization Busy"] + #[inline(always)] + pub fn avgctrl(&self) -> AVGCTRL_R { + AVGCTRL_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - SAMPCTRL Synchronization Busy"] + #[inline(always)] + pub fn sampctrl(&self) -> SAMPCTRL_R { + SAMPCTRL_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - WINLT Synchronization Busy"] + #[inline(always)] + pub fn winlt(&self) -> WINLT_R { + WINLT_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - WINUT Synchronization Busy"] + #[inline(always)] + pub fn winut(&self) -> WINUT_R { + WINUT_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - GAINCORR Synchronization Busy"] + #[inline(always)] + pub fn gaincorr(&self) -> GAINCORR_R { + GAINCORR_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - OFFSETCTRL Synchronization Busy"] + #[inline(always)] + pub fn offsetcorr(&self) -> OFFSETCORR_R { + OFFSETCORR_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - SWTRG Synchronization Busy"] + #[inline(always)] + pub fn swtrig(&self) -> SWTRIG_R { + SWTRIG_R::new(((self.bits >> 10) & 0x01) != 0) + } +} +#[doc = "Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/adc0/winlt.rs b/pac/atsamc21n/src/adc0/winlt.rs new file mode 100644 index 000000000000..2a3397684767 --- /dev/null +++ b/pac/atsamc21n/src/adc0/winlt.rs @@ -0,0 +1,103 @@ +#[doc = "Register `WINLT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WINLT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WINLT` reader - Window Lower Threshold"] +pub struct WINLT_R(crate::FieldReader); +impl WINLT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + WINLT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINLT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINLT` writer - Window Lower Threshold"] +pub struct WINLT_W<'a> { + w: &'a mut W, +} +impl<'a> WINLT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Window Lower Threshold"] + #[inline(always)] + pub fn winlt(&self) -> WINLT_R { + WINLT_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Window Lower Threshold"] + #[inline(always)] + pub fn winlt(&mut self) -> WINLT_W { + WINLT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Window Monitor Lower Threshold\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [winlt](index.html) module"] +pub struct WINLT_SPEC; +impl crate::RegisterSpec for WINLT_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [winlt::R](R) reader structure"] +impl crate::Readable for WINLT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [winlt::W](W) writer structure"] +impl crate::Writable for WINLT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WINLT to value 0"] +impl crate::Resettable for WINLT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/adc0/winut.rs b/pac/atsamc21n/src/adc0/winut.rs new file mode 100644 index 000000000000..0ea123174937 --- /dev/null +++ b/pac/atsamc21n/src/adc0/winut.rs @@ -0,0 +1,103 @@ +#[doc = "Register `WINUT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WINUT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WINUT` reader - Window Upper Threshold"] +pub struct WINUT_R(crate::FieldReader); +impl WINUT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + WINUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINUT` writer - Window Upper Threshold"] +pub struct WINUT_W<'a> { + w: &'a mut W, +} +impl<'a> WINUT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Window Upper Threshold"] + #[inline(always)] + pub fn winut(&self) -> WINUT_R { + WINUT_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Window Upper Threshold"] + #[inline(always)] + pub fn winut(&mut self) -> WINUT_W { + WINUT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Window Monitor Upper Threshold\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [winut](index.html) module"] +pub struct WINUT_SPEC; +impl crate::RegisterSpec for WINUT_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [winut::R](R) reader structure"] +impl crate::Readable for WINUT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [winut::W](W) writer structure"] +impl crate::Writable for WINUT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WINUT to value 0"] +impl crate::Resettable for WINUT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/can0.rs b/pac/atsamc21n/src/can0.rs new file mode 100644 index 000000000000..96ccd4c5970c --- /dev/null +++ b/pac/atsamc21n/src/can0.rs @@ -0,0 +1,291 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Core Release"] + pub crel: crate::Reg, + #[doc = "0x04 - Endian"] + pub endn: crate::Reg, + #[doc = "0x08 - Message RAM Configuration"] + pub mrcfg: crate::Reg, + #[doc = "0x0c - Fast Bit Timing and Prescaler"] + pub dbtp: crate::Reg, + #[doc = "0x10 - Test"] + pub test: crate::Reg, + #[doc = "0x14 - RAM Watchdog"] + pub rwd: crate::Reg, + #[doc = "0x18 - CC Control"] + pub cccr: crate::Reg, + #[doc = "0x1c - Nominal Bit Timing and Prescaler"] + pub nbtp: crate::Reg, + #[doc = "0x20 - Timestamp Counter Configuration"] + pub tscc: crate::Reg, + #[doc = "0x24 - Timestamp Counter Value"] + pub tscv: crate::Reg, + #[doc = "0x28 - Timeout Counter Configuration"] + pub tocc: crate::Reg, + #[doc = "0x2c - Timeout Counter Value"] + pub tocv: crate::Reg, + _reserved12: [u8; 0x10], + #[doc = "0x40 - Error Counter"] + pub ecr: crate::Reg, + #[doc = "0x44 - Protocol Status"] + pub psr: crate::Reg, + #[doc = "0x48 - Extended ID Filter Configuration"] + pub tdcr: crate::Reg, + _reserved15: [u8; 0x04], + #[doc = "0x50 - Interrupt"] + pub ir: crate::Reg, + #[doc = "0x54 - Interrupt Enable"] + pub ie: crate::Reg, + #[doc = "0x58 - Interrupt Line Select"] + pub ils: crate::Reg, + #[doc = "0x5c - Interrupt Line Enable"] + pub ile: crate::Reg, + _reserved19: [u8; 0x20], + #[doc = "0x80 - Global Filter Configuration"] + pub gfc: crate::Reg, + #[doc = "0x84 - Standard ID Filter Configuration"] + pub sidfc: crate::Reg, + #[doc = "0x88 - Extended ID Filter Configuration"] + pub xidfc: crate::Reg, + _reserved22: [u8; 0x04], + #[doc = "0x90 - Extended ID AND Mask"] + pub xidam: crate::Reg, + #[doc = "0x94 - High Priority Message Status"] + pub hpms: crate::Reg, + #[doc = "0x98 - New Data 1"] + pub ndat1: crate::Reg, + #[doc = "0x9c - New Data 2"] + pub ndat2: crate::Reg, + #[doc = "0xa0 - Rx FIFO 0 Configuration"] + pub rxf0c: crate::Reg, + #[doc = "0xa4 - Rx FIFO 0 Status"] + pub rxf0s: crate::Reg, + #[doc = "0xa8 - Rx FIFO 0 Acknowledge"] + pub rxf0a: crate::Reg, + #[doc = "0xac - Rx Buffer Configuration"] + pub rxbc: crate::Reg, + #[doc = "0xb0 - Rx FIFO 1 Configuration"] + pub rxf1c: crate::Reg, + #[doc = "0xb4 - Rx FIFO 1 Status"] + pub rxf1s: crate::Reg, + #[doc = "0xb8 - Rx FIFO 1 Acknowledge"] + pub rxf1a: crate::Reg, + #[doc = "0xbc - Rx Buffer / FIFO Element Size Configuration"] + pub rxesc: crate::Reg, + #[doc = "0xc0 - Tx Buffer Configuration"] + pub txbc: crate::Reg, + #[doc = "0xc4 - Tx FIFO / Queue Status"] + pub txfqs: crate::Reg, + #[doc = "0xc8 - Tx Buffer Element Size Configuration"] + pub txesc: crate::Reg, + #[doc = "0xcc - Tx Buffer Request Pending"] + pub txbrp: crate::Reg, + #[doc = "0xd0 - Tx Buffer Add Request"] + pub txbar: crate::Reg, + #[doc = "0xd4 - Tx Buffer Cancellation Request"] + pub txbcr: crate::Reg, + #[doc = "0xd8 - Tx Buffer Transmission Occurred"] + pub txbto: crate::Reg, + #[doc = "0xdc - Tx Buffer Cancellation Finished"] + pub txbcf: crate::Reg, + #[doc = "0xe0 - Tx Buffer Transmission Interrupt Enable"] + pub txbtie: crate::Reg, + #[doc = "0xe4 - Tx Buffer Cancellation Finished Interrupt Enable"] + pub txbcie: crate::Reg, + _reserved44: [u8; 0x08], + #[doc = "0xf0 - Tx Event FIFO Configuration"] + pub txefc: crate::Reg, + #[doc = "0xf4 - Tx Event FIFO Status"] + pub txefs: crate::Reg, + #[doc = "0xf8 - Tx Event FIFO Acknowledge"] + pub txefa: crate::Reg, +} +#[doc = "CREL register accessor: an alias for `Reg`"] +pub type CREL = crate::Reg; +#[doc = "Core Release"] +pub mod crel; +#[doc = "ENDN register accessor: an alias for `Reg`"] +pub type ENDN = crate::Reg; +#[doc = "Endian"] +pub mod endn; +#[doc = "MRCFG register accessor: an alias for `Reg`"] +pub type MRCFG = crate::Reg; +#[doc = "Message RAM Configuration"] +pub mod mrcfg; +#[doc = "DBTP register accessor: an alias for `Reg`"] +pub type DBTP = crate::Reg; +#[doc = "Fast Bit Timing and Prescaler"] +pub mod dbtp; +#[doc = "TEST register accessor: an alias for `Reg`"] +pub type TEST = crate::Reg; +#[doc = "Test"] +pub mod test; +#[doc = "RWD register accessor: an alias for `Reg`"] +pub type RWD = crate::Reg; +#[doc = "RAM Watchdog"] +pub mod rwd; +#[doc = "CCCR register accessor: an alias for `Reg`"] +pub type CCCR = crate::Reg; +#[doc = "CC Control"] +pub mod cccr; +#[doc = "NBTP register accessor: an alias for `Reg`"] +pub type NBTP = crate::Reg; +#[doc = "Nominal Bit Timing and Prescaler"] +pub mod nbtp; +#[doc = "TSCC register accessor: an alias for `Reg`"] +pub type TSCC = crate::Reg; +#[doc = "Timestamp Counter Configuration"] +pub mod tscc; +#[doc = "TSCV register accessor: an alias for `Reg`"] +pub type TSCV = crate::Reg; +#[doc = "Timestamp Counter Value"] +pub mod tscv; +#[doc = "TOCC register accessor: an alias for `Reg`"] +pub type TOCC = crate::Reg; +#[doc = "Timeout Counter Configuration"] +pub mod tocc; +#[doc = "TOCV register accessor: an alias for `Reg`"] +pub type TOCV = crate::Reg; +#[doc = "Timeout Counter Value"] +pub mod tocv; +#[doc = "ECR register accessor: an alias for `Reg`"] +pub type ECR = crate::Reg; +#[doc = "Error Counter"] +pub mod ecr; +#[doc = "PSR register accessor: an alias for `Reg`"] +pub type PSR = crate::Reg; +#[doc = "Protocol Status"] +pub mod psr; +#[doc = "TDCR register accessor: an alias for `Reg`"] +pub type TDCR = crate::Reg; +#[doc = "Extended ID Filter Configuration"] +pub mod tdcr; +#[doc = "IR register accessor: an alias for `Reg`"] +pub type IR = crate::Reg; +#[doc = "Interrupt"] +pub mod ir; +#[doc = "IE register accessor: an alias for `Reg`"] +pub type IE = crate::Reg; +#[doc = "Interrupt Enable"] +pub mod ie; +#[doc = "ILS register accessor: an alias for `Reg`"] +pub type ILS = crate::Reg; +#[doc = "Interrupt Line Select"] +pub mod ils; +#[doc = "ILE register accessor: an alias for `Reg`"] +pub type ILE = crate::Reg; +#[doc = "Interrupt Line Enable"] +pub mod ile; +#[doc = "GFC register accessor: an alias for `Reg`"] +pub type GFC = crate::Reg; +#[doc = "Global Filter Configuration"] +pub mod gfc; +#[doc = "SIDFC register accessor: an alias for `Reg`"] +pub type SIDFC = crate::Reg; +#[doc = "Standard ID Filter Configuration"] +pub mod sidfc; +#[doc = "XIDFC register accessor: an alias for `Reg`"] +pub type XIDFC = crate::Reg; +#[doc = "Extended ID Filter Configuration"] +pub mod xidfc; +#[doc = "XIDAM register accessor: an alias for `Reg`"] +pub type XIDAM = crate::Reg; +#[doc = "Extended ID AND Mask"] +pub mod xidam; +#[doc = "HPMS register accessor: an alias for `Reg`"] +pub type HPMS = crate::Reg; +#[doc = "High Priority Message Status"] +pub mod hpms; +#[doc = "NDAT1 register accessor: an alias for `Reg`"] +pub type NDAT1 = crate::Reg; +#[doc = "New Data 1"] +pub mod ndat1; +#[doc = "NDAT2 register accessor: an alias for `Reg`"] +pub type NDAT2 = crate::Reg; +#[doc = "New Data 2"] +pub mod ndat2; +#[doc = "RXF0C register accessor: an alias for `Reg`"] +pub type RXF0C = crate::Reg; +#[doc = "Rx FIFO 0 Configuration"] +pub mod rxf0c; +#[doc = "RXF0S register accessor: an alias for `Reg`"] +pub type RXF0S = crate::Reg; +#[doc = "Rx FIFO 0 Status"] +pub mod rxf0s; +#[doc = "RXF0A register accessor: an alias for `Reg`"] +pub type RXF0A = crate::Reg; +#[doc = "Rx FIFO 0 Acknowledge"] +pub mod rxf0a; +#[doc = "RXBC register accessor: an alias for `Reg`"] +pub type RXBC = crate::Reg; +#[doc = "Rx Buffer Configuration"] +pub mod rxbc; +#[doc = "RXF1C register accessor: an alias for `Reg`"] +pub type RXF1C = crate::Reg; +#[doc = "Rx FIFO 1 Configuration"] +pub mod rxf1c; +#[doc = "RXF1S register accessor: an alias for `Reg`"] +pub type RXF1S = crate::Reg; +#[doc = "Rx FIFO 1 Status"] +pub mod rxf1s; +#[doc = "RXF1A register accessor: an alias for `Reg`"] +pub type RXF1A = crate::Reg; +#[doc = "Rx FIFO 1 Acknowledge"] +pub mod rxf1a; +#[doc = "RXESC register accessor: an alias for `Reg`"] +pub type RXESC = crate::Reg; +#[doc = "Rx Buffer / FIFO Element Size Configuration"] +pub mod rxesc; +#[doc = "TXBC register accessor: an alias for `Reg`"] +pub type TXBC = crate::Reg; +#[doc = "Tx Buffer Configuration"] +pub mod txbc; +#[doc = "TXFQS register accessor: an alias for `Reg`"] +pub type TXFQS = crate::Reg; +#[doc = "Tx FIFO / Queue Status"] +pub mod txfqs; +#[doc = "TXESC register accessor: an alias for `Reg`"] +pub type TXESC = crate::Reg; +#[doc = "Tx Buffer Element Size Configuration"] +pub mod txesc; +#[doc = "TXBRP register accessor: an alias for `Reg`"] +pub type TXBRP = crate::Reg; +#[doc = "Tx Buffer Request Pending"] +pub mod txbrp; +#[doc = "TXBAR register accessor: an alias for `Reg`"] +pub type TXBAR = crate::Reg; +#[doc = "Tx Buffer Add Request"] +pub mod txbar; +#[doc = "TXBCR register accessor: an alias for `Reg`"] +pub type TXBCR = crate::Reg; +#[doc = "Tx Buffer Cancellation Request"] +pub mod txbcr; +#[doc = "TXBTO register accessor: an alias for `Reg`"] +pub type TXBTO = crate::Reg; +#[doc = "Tx Buffer Transmission Occurred"] +pub mod txbto; +#[doc = "TXBCF register accessor: an alias for `Reg`"] +pub type TXBCF = crate::Reg; +#[doc = "Tx Buffer Cancellation Finished"] +pub mod txbcf; +#[doc = "TXBTIE register accessor: an alias for `Reg`"] +pub type TXBTIE = crate::Reg; +#[doc = "Tx Buffer Transmission Interrupt Enable"] +pub mod txbtie; +#[doc = "TXBCIE register accessor: an alias for `Reg`"] +pub type TXBCIE = crate::Reg; +#[doc = "Tx Buffer Cancellation Finished Interrupt Enable"] +pub mod txbcie; +#[doc = "TXEFC register accessor: an alias for `Reg`"] +pub type TXEFC = crate::Reg; +#[doc = "Tx Event FIFO Configuration"] +pub mod txefc; +#[doc = "TXEFS register accessor: an alias for `Reg`"] +pub type TXEFS = crate::Reg; +#[doc = "Tx Event FIFO Status"] +pub mod txefs; +#[doc = "TXEFA register accessor: an alias for `Reg`"] +pub type TXEFA = crate::Reg; +#[doc = "Tx Event FIFO Acknowledge"] +pub mod txefa; diff --git a/pac/atsamc21n/src/can0/cccr.rs b/pac/atsamc21n/src/can0/cccr.rs new file mode 100644 index 000000000000..c2ff17d123cf --- /dev/null +++ b/pac/atsamc21n/src/can0/cccr.rs @@ -0,0 +1,724 @@ +#[doc = "Register `CCCR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CCCR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INIT` reader - Initialization"] +pub struct INIT_R(crate::FieldReader); +impl INIT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INIT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INIT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INIT` writer - Initialization"] +pub struct INIT_W<'a> { + w: &'a mut W, +} +impl<'a> INIT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `CCE` reader - Configuration Change Enable"] +pub struct CCE_R(crate::FieldReader); +impl CCE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCE` writer - Configuration Change Enable"] +pub struct CCE_W<'a> { + w: &'a mut W, +} +impl<'a> CCE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ASM` reader - ASM Restricted Operation Mode"] +pub struct ASM_R(crate::FieldReader); +impl ASM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ASM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ASM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ASM` writer - ASM Restricted Operation Mode"] +pub struct ASM_W<'a> { + w: &'a mut W, +} +impl<'a> ASM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CSA` reader - Clock Stop Acknowledge"] +pub struct CSA_R(crate::FieldReader); +impl CSA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CSA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CSA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CSA` writer - Clock Stop Acknowledge"] +pub struct CSA_W<'a> { + w: &'a mut W, +} +impl<'a> CSA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CSR` reader - Clock Stop Request"] +pub struct CSR_R(crate::FieldReader); +impl CSR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CSR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CSR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CSR` writer - Clock Stop Request"] +pub struct CSR_W<'a> { + w: &'a mut W, +} +impl<'a> CSR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MON` reader - Bus Monitoring Mode"] +pub struct MON_R(crate::FieldReader); +impl MON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MON` writer - Bus Monitoring Mode"] +pub struct MON_W<'a> { + w: &'a mut W, +} +impl<'a> MON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `DAR` reader - Disable Automatic Retransmission"] +pub struct DAR_R(crate::FieldReader); +impl DAR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DAR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DAR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DAR` writer - Disable Automatic Retransmission"] +pub struct DAR_W<'a> { + w: &'a mut W, +} +impl<'a> DAR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `TEST` reader - Test Mode Enable"] +pub struct TEST_R(crate::FieldReader); +impl TEST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TEST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TEST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TEST` writer - Test Mode Enable"] +pub struct TEST_W<'a> { + w: &'a mut W, +} +impl<'a> TEST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `FDOE` reader - FD Operation Enable"] +pub struct FDOE_R(crate::FieldReader); +impl FDOE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FDOE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FDOE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FDOE` writer - FD Operation Enable"] +pub struct FDOE_W<'a> { + w: &'a mut W, +} +impl<'a> FDOE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `BRSE` reader - Bit Rate Switch Enable"] +pub struct BRSE_R(crate::FieldReader); +impl BRSE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BRSE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BRSE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BRSE` writer - Bit Rate Switch Enable"] +pub struct BRSE_W<'a> { + w: &'a mut W, +} +impl<'a> BRSE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `PXHD` reader - Protocol Exception Handling Disable"] +pub struct PXHD_R(crate::FieldReader); +impl PXHD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PXHD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PXHD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PXHD` writer - Protocol Exception Handling Disable"] +pub struct PXHD_W<'a> { + w: &'a mut W, +} +impl<'a> PXHD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `EFBI` reader - Edge Filtering during Bus Integration"] +pub struct EFBI_R(crate::FieldReader); +impl EFBI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EFBI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EFBI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EFBI` writer - Edge Filtering during Bus Integration"] +pub struct EFBI_W<'a> { + w: &'a mut W, +} +impl<'a> EFBI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `TXP` reader - Transmit Pause"] +pub struct TXP_R(crate::FieldReader); +impl TXP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXP` writer - Transmit Pause"] +pub struct TXP_W<'a> { + w: &'a mut W, +} +impl<'a> TXP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `NISO` reader - Non ISO Operation"] +pub struct NISO_R(crate::FieldReader); +impl NISO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NISO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NISO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NISO` writer - Non ISO Operation"] +pub struct NISO_W<'a> { + w: &'a mut W, +} +impl<'a> NISO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Initialization"] + #[inline(always)] + pub fn init(&self) -> INIT_R { + INIT_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Configuration Change Enable"] + #[inline(always)] + pub fn cce(&self) -> CCE_R { + CCE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - ASM Restricted Operation Mode"] + #[inline(always)] + pub fn asm(&self) -> ASM_R { + ASM_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Clock Stop Acknowledge"] + #[inline(always)] + pub fn csa(&self) -> CSA_R { + CSA_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Clock Stop Request"] + #[inline(always)] + pub fn csr(&self) -> CSR_R { + CSR_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Bus Monitoring Mode"] + #[inline(always)] + pub fn mon(&self) -> MON_R { + MON_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Disable Automatic Retransmission"] + #[inline(always)] + pub fn dar(&self) -> DAR_R { + DAR_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Test Mode Enable"] + #[inline(always)] + pub fn test(&self) -> TEST_R { + TEST_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - FD Operation Enable"] + #[inline(always)] + pub fn fdoe(&self) -> FDOE_R { + FDOE_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Bit Rate Switch Enable"] + #[inline(always)] + pub fn brse(&self) -> BRSE_R { + BRSE_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 12 - Protocol Exception Handling Disable"] + #[inline(always)] + pub fn pxhd(&self) -> PXHD_R { + PXHD_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Edge Filtering during Bus Integration"] + #[inline(always)] + pub fn efbi(&self) -> EFBI_R { + EFBI_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Transmit Pause"] + #[inline(always)] + pub fn txp(&self) -> TXP_R { + TXP_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Non ISO Operation"] + #[inline(always)] + pub fn niso(&self) -> NISO_R { + NISO_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Initialization"] + #[inline(always)] + pub fn init(&mut self) -> INIT_W { + INIT_W { w: self } + } + #[doc = "Bit 1 - Configuration Change Enable"] + #[inline(always)] + pub fn cce(&mut self) -> CCE_W { + CCE_W { w: self } + } + #[doc = "Bit 2 - ASM Restricted Operation Mode"] + #[inline(always)] + pub fn asm(&mut self) -> ASM_W { + ASM_W { w: self } + } + #[doc = "Bit 3 - Clock Stop Acknowledge"] + #[inline(always)] + pub fn csa(&mut self) -> CSA_W { + CSA_W { w: self } + } + #[doc = "Bit 4 - Clock Stop Request"] + #[inline(always)] + pub fn csr(&mut self) -> CSR_W { + CSR_W { w: self } + } + #[doc = "Bit 5 - Bus Monitoring Mode"] + #[inline(always)] + pub fn mon(&mut self) -> MON_W { + MON_W { w: self } + } + #[doc = "Bit 6 - Disable Automatic Retransmission"] + #[inline(always)] + pub fn dar(&mut self) -> DAR_W { + DAR_W { w: self } + } + #[doc = "Bit 7 - Test Mode Enable"] + #[inline(always)] + pub fn test(&mut self) -> TEST_W { + TEST_W { w: self } + } + #[doc = "Bit 8 - FD Operation Enable"] + #[inline(always)] + pub fn fdoe(&mut self) -> FDOE_W { + FDOE_W { w: self } + } + #[doc = "Bit 9 - Bit Rate Switch Enable"] + #[inline(always)] + pub fn brse(&mut self) -> BRSE_W { + BRSE_W { w: self } + } + #[doc = "Bit 12 - Protocol Exception Handling Disable"] + #[inline(always)] + pub fn pxhd(&mut self) -> PXHD_W { + PXHD_W { w: self } + } + #[doc = "Bit 13 - Edge Filtering during Bus Integration"] + #[inline(always)] + pub fn efbi(&mut self) -> EFBI_W { + EFBI_W { w: self } + } + #[doc = "Bit 14 - Transmit Pause"] + #[inline(always)] + pub fn txp(&mut self) -> TXP_W { + TXP_W { w: self } + } + #[doc = "Bit 15 - Non ISO Operation"] + #[inline(always)] + pub fn niso(&mut self) -> NISO_W { + NISO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CC Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cccr](index.html) module"] +pub struct CCCR_SPEC; +impl crate::RegisterSpec for CCCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cccr::R](R) reader structure"] +impl crate::Readable for CCCR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cccr::W](W) writer structure"] +impl crate::Writable for CCCR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CCCR to value 0x01"] +impl crate::Resettable for CCCR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pac/atsamc21n/src/can0/crel.rs b/pac/atsamc21n/src/can0/crel.rs new file mode 100644 index 000000000000..4e9dcdbf5f03 --- /dev/null +++ b/pac/atsamc21n/src/can0/crel.rs @@ -0,0 +1,93 @@ +#[doc = "Register `CREL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SUBSTEP` reader - Sub-step of Core Release"] +pub struct SUBSTEP_R(crate::FieldReader); +impl SUBSTEP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SUBSTEP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SUBSTEP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STEP` reader - Step of Core Release"] +pub struct STEP_R(crate::FieldReader); +impl STEP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + STEP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STEP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REL` reader - Core Release"] +pub struct REL_R(crate::FieldReader); +impl REL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 20:23 - Sub-step of Core Release"] + #[inline(always)] + pub fn substep(&self) -> SUBSTEP_R { + SUBSTEP_R::new(((self.bits >> 20) & 0x0f) as u8) + } + #[doc = "Bits 24:27 - Step of Core Release"] + #[inline(always)] + pub fn step(&self) -> STEP_R { + STEP_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bits 28:31 - Core Release"] + #[inline(always)] + pub fn rel(&self) -> REL_R { + REL_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +#[doc = "Core Release\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [crel](index.html) module"] +pub struct CREL_SPEC; +impl crate::RegisterSpec for CREL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [crel::R](R) reader structure"] +impl crate::Readable for CREL_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CREL to value 0x3210_0000"] +impl crate::Resettable for CREL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x3210_0000 + } +} diff --git a/pac/atsamc21n/src/can0/dbtp.rs b/pac/atsamc21n/src/can0/dbtp.rs new file mode 100644 index 000000000000..5c1d2bc7ccdd --- /dev/null +++ b/pac/atsamc21n/src/can0/dbtp.rs @@ -0,0 +1,261 @@ +#[doc = "Register `DBTP` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBTP` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DSJW` reader - Data (Re)Synchronization Jump Width"] +pub struct DSJW_R(crate::FieldReader); +impl DSJW_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DSJW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DSJW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DSJW` writer - Data (Re)Synchronization Jump Width"] +pub struct DSJW_W<'a> { + w: &'a mut W, +} +impl<'a> DSJW_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Field `DTSEG2` reader - Data time segment after sample point"] +pub struct DTSEG2_R(crate::FieldReader); +impl DTSEG2_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DTSEG2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DTSEG2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DTSEG2` writer - Data time segment after sample point"] +pub struct DTSEG2_W<'a> { + w: &'a mut W, +} +impl<'a> DTSEG2_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 4)) | ((value as u32 & 0x0f) << 4); + self.w + } +} +#[doc = "Field `DTSEG1` reader - Data time segment before sample point"] +pub struct DTSEG1_R(crate::FieldReader); +impl DTSEG1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DTSEG1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DTSEG1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DTSEG1` writer - Data time segment before sample point"] +pub struct DTSEG1_W<'a> { + w: &'a mut W, +} +impl<'a> DTSEG1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 8)) | ((value as u32 & 0x1f) << 8); + self.w + } +} +#[doc = "Field `DBRP` reader - Data Baud Rate Prescaler"] +pub struct DBRP_R(crate::FieldReader); +impl DBRP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DBRP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBRP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBRP` writer - Data Baud Rate Prescaler"] +pub struct DBRP_W<'a> { + w: &'a mut W, +} +impl<'a> DBRP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 16)) | ((value as u32 & 0x1f) << 16); + self.w + } +} +#[doc = "Field `TDC` reader - Tranceiver Delay Compensation"] +pub struct TDC_R(crate::FieldReader); +impl TDC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TDC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TDC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TDC` writer - Tranceiver Delay Compensation"] +pub struct TDC_W<'a> { + w: &'a mut W, +} +impl<'a> TDC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Data (Re)Synchronization Jump Width"] + #[inline(always)] + pub fn dsjw(&self) -> DSJW_R { + DSJW_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Data time segment after sample point"] + #[inline(always)] + pub fn dtseg2(&self) -> DTSEG2_R { + DTSEG2_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 8:12 - Data time segment before sample point"] + #[inline(always)] + pub fn dtseg1(&self) -> DTSEG1_R { + DTSEG1_R::new(((self.bits >> 8) & 0x1f) as u8) + } + #[doc = "Bits 16:20 - Data Baud Rate Prescaler"] + #[inline(always)] + pub fn dbrp(&self) -> DBRP_R { + DBRP_R::new(((self.bits >> 16) & 0x1f) as u8) + } + #[doc = "Bit 23 - Tranceiver Delay Compensation"] + #[inline(always)] + pub fn tdc(&self) -> TDC_R { + TDC_R::new(((self.bits >> 23) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Data (Re)Synchronization Jump Width"] + #[inline(always)] + pub fn dsjw(&mut self) -> DSJW_W { + DSJW_W { w: self } + } + #[doc = "Bits 4:7 - Data time segment after sample point"] + #[inline(always)] + pub fn dtseg2(&mut self) -> DTSEG2_W { + DTSEG2_W { w: self } + } + #[doc = "Bits 8:12 - Data time segment before sample point"] + #[inline(always)] + pub fn dtseg1(&mut self) -> DTSEG1_W { + DTSEG1_W { w: self } + } + #[doc = "Bits 16:20 - Data Baud Rate Prescaler"] + #[inline(always)] + pub fn dbrp(&mut self) -> DBRP_W { + DBRP_W { w: self } + } + #[doc = "Bit 23 - Tranceiver Delay Compensation"] + #[inline(always)] + pub fn tdc(&mut self) -> TDC_W { + TDC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Fast Bit Timing and Prescaler\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbtp](index.html) module"] +pub struct DBTP_SPEC; +impl crate::RegisterSpec for DBTP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dbtp::R](R) reader structure"] +impl crate::Readable for DBTP_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbtp::W](W) writer structure"] +impl crate::Writable for DBTP_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBTP to value 0x0a33"] +impl crate::Resettable for DBTP_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0a33 + } +} diff --git a/pac/atsamc21n/src/can0/ecr.rs b/pac/atsamc21n/src/can0/ecr.rs new file mode 100644 index 000000000000..044085d7706d --- /dev/null +++ b/pac/atsamc21n/src/can0/ecr.rs @@ -0,0 +1,113 @@ +#[doc = "Register `ECR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `TEC` reader - Transmit Error Counter"] +pub struct TEC_R(crate::FieldReader); +impl TEC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TEC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TEC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REC` reader - Receive Error Counter"] +pub struct REC_R(crate::FieldReader); +impl REC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RP` reader - Receive Error Passive"] +pub struct RP_R(crate::FieldReader); +impl RP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CEL` reader - CAN Error Logging"] +pub struct CEL_R(crate::FieldReader); +impl CEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:7 - Transmit Error Counter"] + #[inline(always)] + pub fn tec(&self) -> TEC_R { + TEC_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:14 - Receive Error Counter"] + #[inline(always)] + pub fn rec(&self) -> REC_R { + REC_R::new(((self.bits >> 8) & 0x7f) as u8) + } + #[doc = "Bit 15 - Receive Error Passive"] + #[inline(always)] + pub fn rp(&self) -> RP_R { + RP_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:23 - CAN Error Logging"] + #[inline(always)] + pub fn cel(&self) -> CEL_R { + CEL_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +#[doc = "Error Counter\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ecr](index.html) module"] +pub struct ECR_SPEC; +impl crate::RegisterSpec for ECR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ecr::R](R) reader structure"] +impl crate::Readable for ECR_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets ECR to value 0"] +impl crate::Resettable for ECR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/can0/endn.rs b/pac/atsamc21n/src/can0/endn.rs new file mode 100644 index 000000000000..9628fa2a3f48 --- /dev/null +++ b/pac/atsamc21n/src/can0/endn.rs @@ -0,0 +1,53 @@ +#[doc = "Register `ENDN` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `ETV` reader - Endianness Test Value"] +pub struct ETV_R(crate::FieldReader); +impl ETV_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + ETV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ETV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - Endianness Test Value"] + #[inline(always)] + pub fn etv(&self) -> ETV_R { + ETV_R::new(self.bits as u32) + } +} +#[doc = "Endian\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [endn](index.html) module"] +pub struct ENDN_SPEC; +impl crate::RegisterSpec for ENDN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [endn::R](R) reader structure"] +impl crate::Readable for ENDN_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets ENDN to value 0x8765_4321"] +impl crate::Resettable for ENDN_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x8765_4321 + } +} diff --git a/pac/atsamc21n/src/can0/gfc.rs b/pac/atsamc21n/src/can0/gfc.rs new file mode 100644 index 000000000000..a9e7a8cc9f62 --- /dev/null +++ b/pac/atsamc21n/src/can0/gfc.rs @@ -0,0 +1,358 @@ +#[doc = "Register `GFC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GFC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RRFE` reader - Reject Remote Frames Extended"] +pub struct RRFE_R(crate::FieldReader); +impl RRFE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RRFE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RRFE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RRFE` writer - Reject Remote Frames Extended"] +pub struct RRFE_W<'a> { + w: &'a mut W, +} +impl<'a> RRFE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `RRFS` reader - Reject Remote Frames Standard"] +pub struct RRFS_R(crate::FieldReader); +impl RRFS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RRFS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RRFS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RRFS` writer - Reject Remote Frames Standard"] +pub struct RRFS_W<'a> { + w: &'a mut W, +} +impl<'a> RRFS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Accept Non-matching Frames Extended\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum ANFE_A { + #[doc = "0: Accept in Rx FIFO 0"] + RXF0 = 0, + #[doc = "1: Accept in Rx FIFO 1"] + RXF1 = 1, + #[doc = "2: Reject"] + REJECT = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: ANFE_A) -> Self { + variant as _ + } +} +#[doc = "Field `ANFE` reader - Accept Non-matching Frames Extended"] +pub struct ANFE_R(crate::FieldReader); +impl ANFE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ANFE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(ANFE_A::RXF0), + 1 => Some(ANFE_A::RXF1), + 2 => Some(ANFE_A::REJECT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `RXF0`"] + #[inline(always)] + pub fn is_rxf0(&self) -> bool { + **self == ANFE_A::RXF0 + } + #[doc = "Checks if the value of the field is `RXF1`"] + #[inline(always)] + pub fn is_rxf1(&self) -> bool { + **self == ANFE_A::RXF1 + } + #[doc = "Checks if the value of the field is `REJECT`"] + #[inline(always)] + pub fn is_reject(&self) -> bool { + **self == ANFE_A::REJECT + } +} +impl core::ops::Deref for ANFE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ANFE` writer - Accept Non-matching Frames Extended"] +pub struct ANFE_W<'a> { + w: &'a mut W, +} +impl<'a> ANFE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: ANFE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Accept in Rx FIFO 0"] + #[inline(always)] + pub fn rxf0(self) -> &'a mut W { + self.variant(ANFE_A::RXF0) + } + #[doc = "Accept in Rx FIFO 1"] + #[inline(always)] + pub fn rxf1(self) -> &'a mut W { + self.variant(ANFE_A::RXF1) + } + #[doc = "Reject"] + #[inline(always)] + pub fn reject(self) -> &'a mut W { + self.variant(ANFE_A::REJECT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u32 & 0x03) << 2); + self.w + } +} +#[doc = "Accept Non-matching Frames Standard\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum ANFS_A { + #[doc = "0: Accept in Rx FIFO 0"] + RXF0 = 0, + #[doc = "1: Accept in Rx FIFO 1"] + RXF1 = 1, + #[doc = "2: Reject"] + REJECT = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: ANFS_A) -> Self { + variant as _ + } +} +#[doc = "Field `ANFS` reader - Accept Non-matching Frames Standard"] +pub struct ANFS_R(crate::FieldReader); +impl ANFS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ANFS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(ANFS_A::RXF0), + 1 => Some(ANFS_A::RXF1), + 2 => Some(ANFS_A::REJECT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `RXF0`"] + #[inline(always)] + pub fn is_rxf0(&self) -> bool { + **self == ANFS_A::RXF0 + } + #[doc = "Checks if the value of the field is `RXF1`"] + #[inline(always)] + pub fn is_rxf1(&self) -> bool { + **self == ANFS_A::RXF1 + } + #[doc = "Checks if the value of the field is `REJECT`"] + #[inline(always)] + pub fn is_reject(&self) -> bool { + **self == ANFS_A::REJECT + } +} +impl core::ops::Deref for ANFS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ANFS` writer - Accept Non-matching Frames Standard"] +pub struct ANFS_W<'a> { + w: &'a mut W, +} +impl<'a> ANFS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: ANFS_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Accept in Rx FIFO 0"] + #[inline(always)] + pub fn rxf0(self) -> &'a mut W { + self.variant(ANFS_A::RXF0) + } + #[doc = "Accept in Rx FIFO 1"] + #[inline(always)] + pub fn rxf1(self) -> &'a mut W { + self.variant(ANFS_A::RXF1) + } + #[doc = "Reject"] + #[inline(always)] + pub fn reject(self) -> &'a mut W { + self.variant(ANFS_A::REJECT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u32 & 0x03) << 4); + self.w + } +} +impl R { + #[doc = "Bit 0 - Reject Remote Frames Extended"] + #[inline(always)] + pub fn rrfe(&self) -> RRFE_R { + RRFE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Reject Remote Frames Standard"] + #[inline(always)] + pub fn rrfs(&self) -> RRFS_R { + RRFS_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:3 - Accept Non-matching Frames Extended"] + #[inline(always)] + pub fn anfe(&self) -> ANFE_R { + ANFE_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bits 4:5 - Accept Non-matching Frames Standard"] + #[inline(always)] + pub fn anfs(&self) -> ANFS_R { + ANFS_R::new(((self.bits >> 4) & 0x03) as u8) + } +} +impl W { + #[doc = "Bit 0 - Reject Remote Frames Extended"] + #[inline(always)] + pub fn rrfe(&mut self) -> RRFE_W { + RRFE_W { w: self } + } + #[doc = "Bit 1 - Reject Remote Frames Standard"] + #[inline(always)] + pub fn rrfs(&mut self) -> RRFS_W { + RRFS_W { w: self } + } + #[doc = "Bits 2:3 - Accept Non-matching Frames Extended"] + #[inline(always)] + pub fn anfe(&mut self) -> ANFE_W { + ANFE_W { w: self } + } + #[doc = "Bits 4:5 - Accept Non-matching Frames Standard"] + #[inline(always)] + pub fn anfs(&mut self) -> ANFS_W { + ANFS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Global Filter Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gfc](index.html) module"] +pub struct GFC_SPEC; +impl crate::RegisterSpec for GFC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gfc::R](R) reader structure"] +impl crate::Readable for GFC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gfc::W](W) writer structure"] +impl crate::Writable for GFC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets GFC to value 0"] +impl crate::Resettable for GFC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/can0/hpms.rs b/pac/atsamc21n/src/can0/hpms.rs new file mode 100644 index 000000000000..ff26a312fb47 --- /dev/null +++ b/pac/atsamc21n/src/can0/hpms.rs @@ -0,0 +1,163 @@ +#[doc = "Register `HPMS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `BIDX` reader - Buffer Index"] +pub struct BIDX_R(crate::FieldReader); +impl BIDX_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BIDX_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BIDX_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Message Storage Indicator\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MSI_A { + #[doc = "0: No FIFO selected"] + NONE = 0, + #[doc = "1: FIFO message lost"] + LOST = 1, + #[doc = "2: Message stored in FIFO 0"] + FIFO0 = 2, + #[doc = "3: Message stored in FIFO 1"] + FIFO1 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MSI_A) -> Self { + variant as _ + } +} +#[doc = "Field `MSI` reader - Message Storage Indicator"] +pub struct MSI_R(crate::FieldReader); +impl MSI_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MSI_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> MSI_A { + match self.bits { + 0 => MSI_A::NONE, + 1 => MSI_A::LOST, + 2 => MSI_A::FIFO0, + 3 => MSI_A::FIFO1, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == MSI_A::NONE + } + #[doc = "Checks if the value of the field is `LOST`"] + #[inline(always)] + pub fn is_lost(&self) -> bool { + **self == MSI_A::LOST + } + #[doc = "Checks if the value of the field is `FIFO0`"] + #[inline(always)] + pub fn is_fifo0(&self) -> bool { + **self == MSI_A::FIFO0 + } + #[doc = "Checks if the value of the field is `FIFO1`"] + #[inline(always)] + pub fn is_fifo1(&self) -> bool { + **self == MSI_A::FIFO1 + } +} +impl core::ops::Deref for MSI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FIDX` reader - Filter Index"] +pub struct FIDX_R(crate::FieldReader); +impl FIDX_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FIDX_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FIDX_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLST` reader - Filter List"] +pub struct FLST_R(crate::FieldReader); +impl FLST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FLST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FLST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:5 - Buffer Index"] + #[inline(always)] + pub fn bidx(&self) -> BIDX_R { + BIDX_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:7 - Message Storage Indicator"] + #[inline(always)] + pub fn msi(&self) -> MSI_R { + MSI_R::new(((self.bits >> 6) & 0x03) as u8) + } + #[doc = "Bits 8:14 - Filter Index"] + #[inline(always)] + pub fn fidx(&self) -> FIDX_R { + FIDX_R::new(((self.bits >> 8) & 0x7f) as u8) + } + #[doc = "Bit 15 - Filter List"] + #[inline(always)] + pub fn flst(&self) -> FLST_R { + FLST_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +#[doc = "High Priority Message Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hpms](index.html) module"] +pub struct HPMS_SPEC; +impl crate::RegisterSpec for HPMS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [hpms::R](R) reader structure"] +impl crate::Readable for HPMS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets HPMS to value 0"] +impl crate::Resettable for HPMS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/can0/ie.rs b/pac/atsamc21n/src/can0/ie.rs new file mode 100644 index 000000000000..c773ba115329 --- /dev/null +++ b/pac/atsamc21n/src/can0/ie.rs @@ -0,0 +1,1476 @@ +#[doc = "Register `IE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `IE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RF0NE` reader - Rx FIFO 0 New Message Interrupt Enable"] +pub struct RF0NE_R(crate::FieldReader); +impl RF0NE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF0NE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF0NE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF0NE` writer - Rx FIFO 0 New Message Interrupt Enable"] +pub struct RF0NE_W<'a> { + w: &'a mut W, +} +impl<'a> RF0NE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `RF0WE` reader - Rx FIFO 0 Watermark Reached Interrupt Enable"] +pub struct RF0WE_R(crate::FieldReader); +impl RF0WE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF0WE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF0WE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF0WE` writer - Rx FIFO 0 Watermark Reached Interrupt Enable"] +pub struct RF0WE_W<'a> { + w: &'a mut W, +} +impl<'a> RF0WE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RF0FE` reader - Rx FIFO 0 Full Interrupt Enable"] +pub struct RF0FE_R(crate::FieldReader); +impl RF0FE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF0FE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF0FE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF0FE` writer - Rx FIFO 0 Full Interrupt Enable"] +pub struct RF0FE_W<'a> { + w: &'a mut W, +} +impl<'a> RF0FE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RF0LE` reader - Rx FIFO 0 Message Lost Interrupt Enable"] +pub struct RF0LE_R(crate::FieldReader); +impl RF0LE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF0LE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF0LE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF0LE` writer - Rx FIFO 0 Message Lost Interrupt Enable"] +pub struct RF0LE_W<'a> { + w: &'a mut W, +} +impl<'a> RF0LE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `RF1NE` reader - Rx FIFO 1 New Message Interrupt Enable"] +pub struct RF1NE_R(crate::FieldReader); +impl RF1NE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF1NE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF1NE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF1NE` writer - Rx FIFO 1 New Message Interrupt Enable"] +pub struct RF1NE_W<'a> { + w: &'a mut W, +} +impl<'a> RF1NE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RF1WE` reader - Rx FIFO 1 Watermark Reached Interrupt Enable"] +pub struct RF1WE_R(crate::FieldReader); +impl RF1WE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF1WE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF1WE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF1WE` writer - Rx FIFO 1 Watermark Reached Interrupt Enable"] +pub struct RF1WE_W<'a> { + w: &'a mut W, +} +impl<'a> RF1WE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `RF1FE` reader - Rx FIFO 1 FIFO Full Interrupt Enable"] +pub struct RF1FE_R(crate::FieldReader); +impl RF1FE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF1FE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF1FE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF1FE` writer - Rx FIFO 1 FIFO Full Interrupt Enable"] +pub struct RF1FE_W<'a> { + w: &'a mut W, +} +impl<'a> RF1FE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `RF1LE` reader - Rx FIFO 1 Message Lost Interrupt Enable"] +pub struct RF1LE_R(crate::FieldReader); +impl RF1LE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF1LE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF1LE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF1LE` writer - Rx FIFO 1 Message Lost Interrupt Enable"] +pub struct RF1LE_W<'a> { + w: &'a mut W, +} +impl<'a> RF1LE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `HPME` reader - High Priority Message Interrupt Enable"] +pub struct HPME_R(crate::FieldReader); +impl HPME_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HPME_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HPME_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HPME` writer - High Priority Message Interrupt Enable"] +pub struct HPME_W<'a> { + w: &'a mut W, +} +impl<'a> HPME_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `TCE` reader - Timestamp Completed Interrupt Enable"] +pub struct TCE_R(crate::FieldReader); +impl TCE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCE` writer - Timestamp Completed Interrupt Enable"] +pub struct TCE_W<'a> { + w: &'a mut W, +} +impl<'a> TCE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `TCFE` reader - Transmission Cancellation Finished Interrupt Enable"] +pub struct TCFE_R(crate::FieldReader); +impl TCFE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCFE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCFE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCFE` writer - Transmission Cancellation Finished Interrupt Enable"] +pub struct TCFE_W<'a> { + w: &'a mut W, +} +impl<'a> TCFE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `TFEE` reader - Tx FIFO Empty Interrupt Enable"] +pub struct TFEE_R(crate::FieldReader); +impl TFEE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TFEE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TFEE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TFEE` writer - Tx FIFO Empty Interrupt Enable"] +pub struct TFEE_W<'a> { + w: &'a mut W, +} +impl<'a> TFEE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `TEFNE` reader - Tx Event FIFO New Entry Interrupt Enable"] +pub struct TEFNE_R(crate::FieldReader); +impl TEFNE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TEFNE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TEFNE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TEFNE` writer - Tx Event FIFO New Entry Interrupt Enable"] +pub struct TEFNE_W<'a> { + w: &'a mut W, +} +impl<'a> TEFNE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `TEFWE` reader - Tx Event FIFO Watermark Reached Interrupt Enable"] +pub struct TEFWE_R(crate::FieldReader); +impl TEFWE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TEFWE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TEFWE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TEFWE` writer - Tx Event FIFO Watermark Reached Interrupt Enable"] +pub struct TEFWE_W<'a> { + w: &'a mut W, +} +impl<'a> TEFWE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `TEFFE` reader - Tx Event FIFO Full Interrupt Enable"] +pub struct TEFFE_R(crate::FieldReader); +impl TEFFE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TEFFE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TEFFE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TEFFE` writer - Tx Event FIFO Full Interrupt Enable"] +pub struct TEFFE_W<'a> { + w: &'a mut W, +} +impl<'a> TEFFE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `TEFLE` reader - Tx Event FIFO Element Lost Interrupt Enable"] +pub struct TEFLE_R(crate::FieldReader); +impl TEFLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TEFLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TEFLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TEFLE` writer - Tx Event FIFO Element Lost Interrupt Enable"] +pub struct TEFLE_W<'a> { + w: &'a mut W, +} +impl<'a> TEFLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `TSWE` reader - Timestamp Wraparound Interrupt Enable"] +pub struct TSWE_R(crate::FieldReader); +impl TSWE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSWE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSWE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSWE` writer - Timestamp Wraparound Interrupt Enable"] +pub struct TSWE_W<'a> { + w: &'a mut W, +} +impl<'a> TSWE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `MRAFE` reader - Message RAM Access Failure Interrupt Enable"] +pub struct MRAFE_R(crate::FieldReader); +impl MRAFE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MRAFE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MRAFE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MRAFE` writer - Message RAM Access Failure Interrupt Enable"] +pub struct MRAFE_W<'a> { + w: &'a mut W, +} +impl<'a> MRAFE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `TOOE` reader - Timeout Occurred Interrupt Enable"] +pub struct TOOE_R(crate::FieldReader); +impl TOOE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TOOE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TOOE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TOOE` writer - Timeout Occurred Interrupt Enable"] +pub struct TOOE_W<'a> { + w: &'a mut W, +} +impl<'a> TOOE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `DRXE` reader - Message stored to Dedicated Rx Buffer Interrupt Enable"] +pub struct DRXE_R(crate::FieldReader); +impl DRXE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRXE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRXE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRXE` writer - Message stored to Dedicated Rx Buffer Interrupt Enable"] +pub struct DRXE_W<'a> { + w: &'a mut W, +} +impl<'a> DRXE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `BECE` reader - Bit Error Corrected Interrupt Enable"] +pub struct BECE_R(crate::FieldReader); +impl BECE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BECE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BECE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BECE` writer - Bit Error Corrected Interrupt Enable"] +pub struct BECE_W<'a> { + w: &'a mut W, +} +impl<'a> BECE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `BEUE` reader - Bit Error Uncorrected Interrupt Enable"] +pub struct BEUE_R(crate::FieldReader); +impl BEUE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BEUE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BEUE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BEUE` writer - Bit Error Uncorrected Interrupt Enable"] +pub struct BEUE_W<'a> { + w: &'a mut W, +} +impl<'a> BEUE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `ELOE` reader - Error Logging Overflow Interrupt Enable"] +pub struct ELOE_R(crate::FieldReader); +impl ELOE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ELOE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ELOE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ELOE` writer - Error Logging Overflow Interrupt Enable"] +pub struct ELOE_W<'a> { + w: &'a mut W, +} +impl<'a> ELOE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `EPE` reader - Error Passive Interrupt Enable"] +pub struct EPE_R(crate::FieldReader); +impl EPE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EPE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EPE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EPE` writer - Error Passive Interrupt Enable"] +pub struct EPE_W<'a> { + w: &'a mut W, +} +impl<'a> EPE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `EWE` reader - Warning Status Interrupt Enable"] +pub struct EWE_R(crate::FieldReader); +impl EWE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EWE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EWE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EWE` writer - Warning Status Interrupt Enable"] +pub struct EWE_W<'a> { + w: &'a mut W, +} +impl<'a> EWE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `BOE` reader - Bus_Off Status Interrupt Enable"] +pub struct BOE_R(crate::FieldReader); +impl BOE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BOE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BOE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BOE` writer - Bus_Off Status Interrupt Enable"] +pub struct BOE_W<'a> { + w: &'a mut W, +} +impl<'a> BOE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `WDIE` reader - Watchdog Interrupt Interrupt Enable"] +pub struct WDIE_R(crate::FieldReader); +impl WDIE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WDIE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WDIE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WDIE` writer - Watchdog Interrupt Interrupt Enable"] +pub struct WDIE_W<'a> { + w: &'a mut W, +} +impl<'a> WDIE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `PEAE` reader - Protocol Error in Arbitration Phase Enable"] +pub struct PEAE_R(crate::FieldReader); +impl PEAE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEAE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEAE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEAE` writer - Protocol Error in Arbitration Phase Enable"] +pub struct PEAE_W<'a> { + w: &'a mut W, +} +impl<'a> PEAE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +#[doc = "Field `PEDE` reader - Protocol Error in Data Phase Enable"] +pub struct PEDE_R(crate::FieldReader); +impl PEDE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEDE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEDE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEDE` writer - Protocol Error in Data Phase Enable"] +pub struct PEDE_W<'a> { + w: &'a mut W, +} +impl<'a> PEDE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Field `ARAE` reader - Access to Reserved Address Enable"] +pub struct ARAE_R(crate::FieldReader); +impl ARAE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ARAE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ARAE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ARAE` writer - Access to Reserved Address Enable"] +pub struct ARAE_W<'a> { + w: &'a mut W, +} +impl<'a> ARAE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29); + self.w + } +} +impl R { + #[doc = "Bit 0 - Rx FIFO 0 New Message Interrupt Enable"] + #[inline(always)] + pub fn rf0ne(&self) -> RF0NE_R { + RF0NE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Rx FIFO 0 Watermark Reached Interrupt Enable"] + #[inline(always)] + pub fn rf0we(&self) -> RF0WE_R { + RF0WE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Rx FIFO 0 Full Interrupt Enable"] + #[inline(always)] + pub fn rf0fe(&self) -> RF0FE_R { + RF0FE_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Rx FIFO 0 Message Lost Interrupt Enable"] + #[inline(always)] + pub fn rf0le(&self) -> RF0LE_R { + RF0LE_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Rx FIFO 1 New Message Interrupt Enable"] + #[inline(always)] + pub fn rf1ne(&self) -> RF1NE_R { + RF1NE_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Rx FIFO 1 Watermark Reached Interrupt Enable"] + #[inline(always)] + pub fn rf1we(&self) -> RF1WE_R { + RF1WE_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Rx FIFO 1 FIFO Full Interrupt Enable"] + #[inline(always)] + pub fn rf1fe(&self) -> RF1FE_R { + RF1FE_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Rx FIFO 1 Message Lost Interrupt Enable"] + #[inline(always)] + pub fn rf1le(&self) -> RF1LE_R { + RF1LE_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - High Priority Message Interrupt Enable"] + #[inline(always)] + pub fn hpme(&self) -> HPME_R { + HPME_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Timestamp Completed Interrupt Enable"] + #[inline(always)] + pub fn tce(&self) -> TCE_R { + TCE_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Transmission Cancellation Finished Interrupt Enable"] + #[inline(always)] + pub fn tcfe(&self) -> TCFE_R { + TCFE_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Tx FIFO Empty Interrupt Enable"] + #[inline(always)] + pub fn tfee(&self) -> TFEE_R { + TFEE_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Tx Event FIFO New Entry Interrupt Enable"] + #[inline(always)] + pub fn tefne(&self) -> TEFNE_R { + TEFNE_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Tx Event FIFO Watermark Reached Interrupt Enable"] + #[inline(always)] + pub fn tefwe(&self) -> TEFWE_R { + TEFWE_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Tx Event FIFO Full Interrupt Enable"] + #[inline(always)] + pub fn teffe(&self) -> TEFFE_R { + TEFFE_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Tx Event FIFO Element Lost Interrupt Enable"] + #[inline(always)] + pub fn tefle(&self) -> TEFLE_R { + TEFLE_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Timestamp Wraparound Interrupt Enable"] + #[inline(always)] + pub fn tswe(&self) -> TSWE_R { + TSWE_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Message RAM Access Failure Interrupt Enable"] + #[inline(always)] + pub fn mrafe(&self) -> MRAFE_R { + MRAFE_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Timeout Occurred Interrupt Enable"] + #[inline(always)] + pub fn tooe(&self) -> TOOE_R { + TOOE_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Message stored to Dedicated Rx Buffer Interrupt Enable"] + #[inline(always)] + pub fn drxe(&self) -> DRXE_R { + DRXE_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Bit Error Corrected Interrupt Enable"] + #[inline(always)] + pub fn bece(&self) -> BECE_R { + BECE_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Bit Error Uncorrected Interrupt Enable"] + #[inline(always)] + pub fn beue(&self) -> BEUE_R { + BEUE_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Error Logging Overflow Interrupt Enable"] + #[inline(always)] + pub fn eloe(&self) -> ELOE_R { + ELOE_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Error Passive Interrupt Enable"] + #[inline(always)] + pub fn epe(&self) -> EPE_R { + EPE_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24 - Warning Status Interrupt Enable"] + #[inline(always)] + pub fn ewe(&self) -> EWE_R { + EWE_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Bus_Off Status Interrupt Enable"] + #[inline(always)] + pub fn boe(&self) -> BOE_R { + BOE_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Watchdog Interrupt Interrupt Enable"] + #[inline(always)] + pub fn wdie(&self) -> WDIE_R { + WDIE_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Protocol Error in Arbitration Phase Enable"] + #[inline(always)] + pub fn peae(&self) -> PEAE_R { + PEAE_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28 - Protocol Error in Data Phase Enable"] + #[inline(always)] + pub fn pede(&self) -> PEDE_R { + PEDE_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Access to Reserved Address Enable"] + #[inline(always)] + pub fn arae(&self) -> ARAE_R { + ARAE_R::new(((self.bits >> 29) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Rx FIFO 0 New Message Interrupt Enable"] + #[inline(always)] + pub fn rf0ne(&mut self) -> RF0NE_W { + RF0NE_W { w: self } + } + #[doc = "Bit 1 - Rx FIFO 0 Watermark Reached Interrupt Enable"] + #[inline(always)] + pub fn rf0we(&mut self) -> RF0WE_W { + RF0WE_W { w: self } + } + #[doc = "Bit 2 - Rx FIFO 0 Full Interrupt Enable"] + #[inline(always)] + pub fn rf0fe(&mut self) -> RF0FE_W { + RF0FE_W { w: self } + } + #[doc = "Bit 3 - Rx FIFO 0 Message Lost Interrupt Enable"] + #[inline(always)] + pub fn rf0le(&mut self) -> RF0LE_W { + RF0LE_W { w: self } + } + #[doc = "Bit 4 - Rx FIFO 1 New Message Interrupt Enable"] + #[inline(always)] + pub fn rf1ne(&mut self) -> RF1NE_W { + RF1NE_W { w: self } + } + #[doc = "Bit 5 - Rx FIFO 1 Watermark Reached Interrupt Enable"] + #[inline(always)] + pub fn rf1we(&mut self) -> RF1WE_W { + RF1WE_W { w: self } + } + #[doc = "Bit 6 - Rx FIFO 1 FIFO Full Interrupt Enable"] + #[inline(always)] + pub fn rf1fe(&mut self) -> RF1FE_W { + RF1FE_W { w: self } + } + #[doc = "Bit 7 - Rx FIFO 1 Message Lost Interrupt Enable"] + #[inline(always)] + pub fn rf1le(&mut self) -> RF1LE_W { + RF1LE_W { w: self } + } + #[doc = "Bit 8 - High Priority Message Interrupt Enable"] + #[inline(always)] + pub fn hpme(&mut self) -> HPME_W { + HPME_W { w: self } + } + #[doc = "Bit 9 - Timestamp Completed Interrupt Enable"] + #[inline(always)] + pub fn tce(&mut self) -> TCE_W { + TCE_W { w: self } + } + #[doc = "Bit 10 - Transmission Cancellation Finished Interrupt Enable"] + #[inline(always)] + pub fn tcfe(&mut self) -> TCFE_W { + TCFE_W { w: self } + } + #[doc = "Bit 11 - Tx FIFO Empty Interrupt Enable"] + #[inline(always)] + pub fn tfee(&mut self) -> TFEE_W { + TFEE_W { w: self } + } + #[doc = "Bit 12 - Tx Event FIFO New Entry Interrupt Enable"] + #[inline(always)] + pub fn tefne(&mut self) -> TEFNE_W { + TEFNE_W { w: self } + } + #[doc = "Bit 13 - Tx Event FIFO Watermark Reached Interrupt Enable"] + #[inline(always)] + pub fn tefwe(&mut self) -> TEFWE_W { + TEFWE_W { w: self } + } + #[doc = "Bit 14 - Tx Event FIFO Full Interrupt Enable"] + #[inline(always)] + pub fn teffe(&mut self) -> TEFFE_W { + TEFFE_W { w: self } + } + #[doc = "Bit 15 - Tx Event FIFO Element Lost Interrupt Enable"] + #[inline(always)] + pub fn tefle(&mut self) -> TEFLE_W { + TEFLE_W { w: self } + } + #[doc = "Bit 16 - Timestamp Wraparound Interrupt Enable"] + #[inline(always)] + pub fn tswe(&mut self) -> TSWE_W { + TSWE_W { w: self } + } + #[doc = "Bit 17 - Message RAM Access Failure Interrupt Enable"] + #[inline(always)] + pub fn mrafe(&mut self) -> MRAFE_W { + MRAFE_W { w: self } + } + #[doc = "Bit 18 - Timeout Occurred Interrupt Enable"] + #[inline(always)] + pub fn tooe(&mut self) -> TOOE_W { + TOOE_W { w: self } + } + #[doc = "Bit 19 - Message stored to Dedicated Rx Buffer Interrupt Enable"] + #[inline(always)] + pub fn drxe(&mut self) -> DRXE_W { + DRXE_W { w: self } + } + #[doc = "Bit 20 - Bit Error Corrected Interrupt Enable"] + #[inline(always)] + pub fn bece(&mut self) -> BECE_W { + BECE_W { w: self } + } + #[doc = "Bit 21 - Bit Error Uncorrected Interrupt Enable"] + #[inline(always)] + pub fn beue(&mut self) -> BEUE_W { + BEUE_W { w: self } + } + #[doc = "Bit 22 - Error Logging Overflow Interrupt Enable"] + #[inline(always)] + pub fn eloe(&mut self) -> ELOE_W { + ELOE_W { w: self } + } + #[doc = "Bit 23 - Error Passive Interrupt Enable"] + #[inline(always)] + pub fn epe(&mut self) -> EPE_W { + EPE_W { w: self } + } + #[doc = "Bit 24 - Warning Status Interrupt Enable"] + #[inline(always)] + pub fn ewe(&mut self) -> EWE_W { + EWE_W { w: self } + } + #[doc = "Bit 25 - Bus_Off Status Interrupt Enable"] + #[inline(always)] + pub fn boe(&mut self) -> BOE_W { + BOE_W { w: self } + } + #[doc = "Bit 26 - Watchdog Interrupt Interrupt Enable"] + #[inline(always)] + pub fn wdie(&mut self) -> WDIE_W { + WDIE_W { w: self } + } + #[doc = "Bit 27 - Protocol Error in Arbitration Phase Enable"] + #[inline(always)] + pub fn peae(&mut self) -> PEAE_W { + PEAE_W { w: self } + } + #[doc = "Bit 28 - Protocol Error in Data Phase Enable"] + #[inline(always)] + pub fn pede(&mut self) -> PEDE_W { + PEDE_W { w: self } + } + #[doc = "Bit 29 - Access to Reserved Address Enable"] + #[inline(always)] + pub fn arae(&mut self) -> ARAE_W { + ARAE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ie](index.html) module"] +pub struct IE_SPEC; +impl crate::RegisterSpec for IE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ie::R](R) reader structure"] +impl crate::Readable for IE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ie::W](W) writer structure"] +impl crate::Writable for IE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets IE to value 0"] +impl crate::Resettable for IE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/can0/ile.rs b/pac/atsamc21n/src/can0/ile.rs new file mode 100644 index 000000000000..3284b08f7d4c --- /dev/null +++ b/pac/atsamc21n/src/can0/ile.rs @@ -0,0 +1,160 @@ +#[doc = "Register `ILE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ILE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EINT0` reader - Enable Interrupt Line 0"] +pub struct EINT0_R(crate::FieldReader); +impl EINT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EINT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EINT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EINT0` writer - Enable Interrupt Line 0"] +pub struct EINT0_W<'a> { + w: &'a mut W, +} +impl<'a> EINT0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `EINT1` reader - Enable Interrupt Line 1"] +pub struct EINT1_R(crate::FieldReader); +impl EINT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EINT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EINT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EINT1` writer - Enable Interrupt Line 1"] +pub struct EINT1_W<'a> { + w: &'a mut W, +} +impl<'a> EINT1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - Enable Interrupt Line 0"] + #[inline(always)] + pub fn eint0(&self) -> EINT0_R { + EINT0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable Interrupt Line 1"] + #[inline(always)] + pub fn eint1(&self) -> EINT1_R { + EINT1_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Enable Interrupt Line 0"] + #[inline(always)] + pub fn eint0(&mut self) -> EINT0_W { + EINT0_W { w: self } + } + #[doc = "Bit 1 - Enable Interrupt Line 1"] + #[inline(always)] + pub fn eint1(&mut self) -> EINT1_W { + EINT1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Line Enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ile](index.html) module"] +pub struct ILE_SPEC; +impl crate::RegisterSpec for ILE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ile::R](R) reader structure"] +impl crate::Readable for ILE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ile::W](W) writer structure"] +impl crate::Writable for ILE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ILE to value 0"] +impl crate::Resettable for ILE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/can0/ils.rs b/pac/atsamc21n/src/can0/ils.rs new file mode 100644 index 000000000000..14ac6de68d59 --- /dev/null +++ b/pac/atsamc21n/src/can0/ils.rs @@ -0,0 +1,1476 @@ +#[doc = "Register `ILS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ILS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RF0NL` reader - Rx FIFO 0 New Message Interrupt Line"] +pub struct RF0NL_R(crate::FieldReader); +impl RF0NL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF0NL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF0NL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF0NL` writer - Rx FIFO 0 New Message Interrupt Line"] +pub struct RF0NL_W<'a> { + w: &'a mut W, +} +impl<'a> RF0NL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `RF0WL` reader - Rx FIFO 0 Watermark Reached Interrupt Line"] +pub struct RF0WL_R(crate::FieldReader); +impl RF0WL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF0WL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF0WL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF0WL` writer - Rx FIFO 0 Watermark Reached Interrupt Line"] +pub struct RF0WL_W<'a> { + w: &'a mut W, +} +impl<'a> RF0WL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RF0FL` reader - Rx FIFO 0 Full Interrupt Line"] +pub struct RF0FL_R(crate::FieldReader); +impl RF0FL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF0FL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF0FL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF0FL` writer - Rx FIFO 0 Full Interrupt Line"] +pub struct RF0FL_W<'a> { + w: &'a mut W, +} +impl<'a> RF0FL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RF0LL` reader - Rx FIFO 0 Message Lost Interrupt Line"] +pub struct RF0LL_R(crate::FieldReader); +impl RF0LL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF0LL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF0LL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF0LL` writer - Rx FIFO 0 Message Lost Interrupt Line"] +pub struct RF0LL_W<'a> { + w: &'a mut W, +} +impl<'a> RF0LL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `RF1NL` reader - Rx FIFO 1 New Message Interrupt Line"] +pub struct RF1NL_R(crate::FieldReader); +impl RF1NL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF1NL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF1NL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF1NL` writer - Rx FIFO 1 New Message Interrupt Line"] +pub struct RF1NL_W<'a> { + w: &'a mut W, +} +impl<'a> RF1NL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RF1WL` reader - Rx FIFO 1 Watermark Reached Interrupt Line"] +pub struct RF1WL_R(crate::FieldReader); +impl RF1WL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF1WL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF1WL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF1WL` writer - Rx FIFO 1 Watermark Reached Interrupt Line"] +pub struct RF1WL_W<'a> { + w: &'a mut W, +} +impl<'a> RF1WL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `RF1FL` reader - Rx FIFO 1 FIFO Full Interrupt Line"] +pub struct RF1FL_R(crate::FieldReader); +impl RF1FL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF1FL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF1FL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF1FL` writer - Rx FIFO 1 FIFO Full Interrupt Line"] +pub struct RF1FL_W<'a> { + w: &'a mut W, +} +impl<'a> RF1FL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `RF1LL` reader - Rx FIFO 1 Message Lost Interrupt Line"] +pub struct RF1LL_R(crate::FieldReader); +impl RF1LL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF1LL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF1LL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF1LL` writer - Rx FIFO 1 Message Lost Interrupt Line"] +pub struct RF1LL_W<'a> { + w: &'a mut W, +} +impl<'a> RF1LL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `HPML` reader - High Priority Message Interrupt Line"] +pub struct HPML_R(crate::FieldReader); +impl HPML_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HPML_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HPML_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HPML` writer - High Priority Message Interrupt Line"] +pub struct HPML_W<'a> { + w: &'a mut W, +} +impl<'a> HPML_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `TCL` reader - Timestamp Completed Interrupt Line"] +pub struct TCL_R(crate::FieldReader); +impl TCL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCL` writer - Timestamp Completed Interrupt Line"] +pub struct TCL_W<'a> { + w: &'a mut W, +} +impl<'a> TCL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `TCFL` reader - Transmission Cancellation Finished Interrupt Line"] +pub struct TCFL_R(crate::FieldReader); +impl TCFL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCFL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCFL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCFL` writer - Transmission Cancellation Finished Interrupt Line"] +pub struct TCFL_W<'a> { + w: &'a mut W, +} +impl<'a> TCFL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `TFEL` reader - Tx FIFO Empty Interrupt Line"] +pub struct TFEL_R(crate::FieldReader); +impl TFEL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TFEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TFEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TFEL` writer - Tx FIFO Empty Interrupt Line"] +pub struct TFEL_W<'a> { + w: &'a mut W, +} +impl<'a> TFEL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `TEFNL` reader - Tx Event FIFO New Entry Interrupt Line"] +pub struct TEFNL_R(crate::FieldReader); +impl TEFNL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TEFNL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TEFNL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TEFNL` writer - Tx Event FIFO New Entry Interrupt Line"] +pub struct TEFNL_W<'a> { + w: &'a mut W, +} +impl<'a> TEFNL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `TEFWL` reader - Tx Event FIFO Watermark Reached Interrupt Line"] +pub struct TEFWL_R(crate::FieldReader); +impl TEFWL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TEFWL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TEFWL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TEFWL` writer - Tx Event FIFO Watermark Reached Interrupt Line"] +pub struct TEFWL_W<'a> { + w: &'a mut W, +} +impl<'a> TEFWL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `TEFFL` reader - Tx Event FIFO Full Interrupt Line"] +pub struct TEFFL_R(crate::FieldReader); +impl TEFFL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TEFFL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TEFFL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TEFFL` writer - Tx Event FIFO Full Interrupt Line"] +pub struct TEFFL_W<'a> { + w: &'a mut W, +} +impl<'a> TEFFL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `TEFLL` reader - Tx Event FIFO Element Lost Interrupt Line"] +pub struct TEFLL_R(crate::FieldReader); +impl TEFLL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TEFLL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TEFLL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TEFLL` writer - Tx Event FIFO Element Lost Interrupt Line"] +pub struct TEFLL_W<'a> { + w: &'a mut W, +} +impl<'a> TEFLL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `TSWL` reader - Timestamp Wraparound Interrupt Line"] +pub struct TSWL_R(crate::FieldReader); +impl TSWL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSWL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSWL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSWL` writer - Timestamp Wraparound Interrupt Line"] +pub struct TSWL_W<'a> { + w: &'a mut W, +} +impl<'a> TSWL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `MRAFL` reader - Message RAM Access Failure Interrupt Line"] +pub struct MRAFL_R(crate::FieldReader); +impl MRAFL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MRAFL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MRAFL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MRAFL` writer - Message RAM Access Failure Interrupt Line"] +pub struct MRAFL_W<'a> { + w: &'a mut W, +} +impl<'a> MRAFL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `TOOL` reader - Timeout Occurred Interrupt Line"] +pub struct TOOL_R(crate::FieldReader); +impl TOOL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TOOL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TOOL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TOOL` writer - Timeout Occurred Interrupt Line"] +pub struct TOOL_W<'a> { + w: &'a mut W, +} +impl<'a> TOOL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `DRXL` reader - Message stored to Dedicated Rx Buffer Interrupt Line"] +pub struct DRXL_R(crate::FieldReader); +impl DRXL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRXL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRXL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRXL` writer - Message stored to Dedicated Rx Buffer Interrupt Line"] +pub struct DRXL_W<'a> { + w: &'a mut W, +} +impl<'a> DRXL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `BECL` reader - Bit Error Corrected Interrupt Line"] +pub struct BECL_R(crate::FieldReader); +impl BECL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BECL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BECL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BECL` writer - Bit Error Corrected Interrupt Line"] +pub struct BECL_W<'a> { + w: &'a mut W, +} +impl<'a> BECL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `BEUL` reader - Bit Error Uncorrected Interrupt Line"] +pub struct BEUL_R(crate::FieldReader); +impl BEUL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BEUL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BEUL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BEUL` writer - Bit Error Uncorrected Interrupt Line"] +pub struct BEUL_W<'a> { + w: &'a mut W, +} +impl<'a> BEUL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `ELOL` reader - Error Logging Overflow Interrupt Line"] +pub struct ELOL_R(crate::FieldReader); +impl ELOL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ELOL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ELOL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ELOL` writer - Error Logging Overflow Interrupt Line"] +pub struct ELOL_W<'a> { + w: &'a mut W, +} +impl<'a> ELOL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `EPL` reader - Error Passive Interrupt Line"] +pub struct EPL_R(crate::FieldReader); +impl EPL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EPL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EPL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EPL` writer - Error Passive Interrupt Line"] +pub struct EPL_W<'a> { + w: &'a mut W, +} +impl<'a> EPL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `EWL` reader - Warning Status Interrupt Line"] +pub struct EWL_R(crate::FieldReader); +impl EWL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EWL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EWL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EWL` writer - Warning Status Interrupt Line"] +pub struct EWL_W<'a> { + w: &'a mut W, +} +impl<'a> EWL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `BOL` reader - Bus_Off Status Interrupt Line"] +pub struct BOL_R(crate::FieldReader); +impl BOL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BOL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BOL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BOL` writer - Bus_Off Status Interrupt Line"] +pub struct BOL_W<'a> { + w: &'a mut W, +} +impl<'a> BOL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `WDIL` reader - Watchdog Interrupt Interrupt Line"] +pub struct WDIL_R(crate::FieldReader); +impl WDIL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WDIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WDIL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WDIL` writer - Watchdog Interrupt Interrupt Line"] +pub struct WDIL_W<'a> { + w: &'a mut W, +} +impl<'a> WDIL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `PEAL` reader - Protocol Error in Arbitration Phase Line"] +pub struct PEAL_R(crate::FieldReader); +impl PEAL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEAL` writer - Protocol Error in Arbitration Phase Line"] +pub struct PEAL_W<'a> { + w: &'a mut W, +} +impl<'a> PEAL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +#[doc = "Field `PEDL` reader - Protocol Error in Data Phase Line"] +pub struct PEDL_R(crate::FieldReader); +impl PEDL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEDL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEDL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEDL` writer - Protocol Error in Data Phase Line"] +pub struct PEDL_W<'a> { + w: &'a mut W, +} +impl<'a> PEDL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Field `ARAL` reader - Access to Reserved Address Line"] +pub struct ARAL_R(crate::FieldReader); +impl ARAL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ARAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ARAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ARAL` writer - Access to Reserved Address Line"] +pub struct ARAL_W<'a> { + w: &'a mut W, +} +impl<'a> ARAL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29); + self.w + } +} +impl R { + #[doc = "Bit 0 - Rx FIFO 0 New Message Interrupt Line"] + #[inline(always)] + pub fn rf0nl(&self) -> RF0NL_R { + RF0NL_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Rx FIFO 0 Watermark Reached Interrupt Line"] + #[inline(always)] + pub fn rf0wl(&self) -> RF0WL_R { + RF0WL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Rx FIFO 0 Full Interrupt Line"] + #[inline(always)] + pub fn rf0fl(&self) -> RF0FL_R { + RF0FL_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Rx FIFO 0 Message Lost Interrupt Line"] + #[inline(always)] + pub fn rf0ll(&self) -> RF0LL_R { + RF0LL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Rx FIFO 1 New Message Interrupt Line"] + #[inline(always)] + pub fn rf1nl(&self) -> RF1NL_R { + RF1NL_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Rx FIFO 1 Watermark Reached Interrupt Line"] + #[inline(always)] + pub fn rf1wl(&self) -> RF1WL_R { + RF1WL_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Rx FIFO 1 FIFO Full Interrupt Line"] + #[inline(always)] + pub fn rf1fl(&self) -> RF1FL_R { + RF1FL_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Rx FIFO 1 Message Lost Interrupt Line"] + #[inline(always)] + pub fn rf1ll(&self) -> RF1LL_R { + RF1LL_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - High Priority Message Interrupt Line"] + #[inline(always)] + pub fn hpml(&self) -> HPML_R { + HPML_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Timestamp Completed Interrupt Line"] + #[inline(always)] + pub fn tcl(&self) -> TCL_R { + TCL_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Transmission Cancellation Finished Interrupt Line"] + #[inline(always)] + pub fn tcfl(&self) -> TCFL_R { + TCFL_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Tx FIFO Empty Interrupt Line"] + #[inline(always)] + pub fn tfel(&self) -> TFEL_R { + TFEL_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Tx Event FIFO New Entry Interrupt Line"] + #[inline(always)] + pub fn tefnl(&self) -> TEFNL_R { + TEFNL_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Tx Event FIFO Watermark Reached Interrupt Line"] + #[inline(always)] + pub fn tefwl(&self) -> TEFWL_R { + TEFWL_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Tx Event FIFO Full Interrupt Line"] + #[inline(always)] + pub fn teffl(&self) -> TEFFL_R { + TEFFL_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Tx Event FIFO Element Lost Interrupt Line"] + #[inline(always)] + pub fn tefll(&self) -> TEFLL_R { + TEFLL_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Timestamp Wraparound Interrupt Line"] + #[inline(always)] + pub fn tswl(&self) -> TSWL_R { + TSWL_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Message RAM Access Failure Interrupt Line"] + #[inline(always)] + pub fn mrafl(&self) -> MRAFL_R { + MRAFL_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Timeout Occurred Interrupt Line"] + #[inline(always)] + pub fn tool(&self) -> TOOL_R { + TOOL_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Message stored to Dedicated Rx Buffer Interrupt Line"] + #[inline(always)] + pub fn drxl(&self) -> DRXL_R { + DRXL_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Bit Error Corrected Interrupt Line"] + #[inline(always)] + pub fn becl(&self) -> BECL_R { + BECL_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Bit Error Uncorrected Interrupt Line"] + #[inline(always)] + pub fn beul(&self) -> BEUL_R { + BEUL_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Error Logging Overflow Interrupt Line"] + #[inline(always)] + pub fn elol(&self) -> ELOL_R { + ELOL_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Error Passive Interrupt Line"] + #[inline(always)] + pub fn epl(&self) -> EPL_R { + EPL_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24 - Warning Status Interrupt Line"] + #[inline(always)] + pub fn ewl(&self) -> EWL_R { + EWL_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Bus_Off Status Interrupt Line"] + #[inline(always)] + pub fn bol(&self) -> BOL_R { + BOL_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Watchdog Interrupt Interrupt Line"] + #[inline(always)] + pub fn wdil(&self) -> WDIL_R { + WDIL_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Protocol Error in Arbitration Phase Line"] + #[inline(always)] + pub fn peal(&self) -> PEAL_R { + PEAL_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28 - Protocol Error in Data Phase Line"] + #[inline(always)] + pub fn pedl(&self) -> PEDL_R { + PEDL_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Access to Reserved Address Line"] + #[inline(always)] + pub fn aral(&self) -> ARAL_R { + ARAL_R::new(((self.bits >> 29) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Rx FIFO 0 New Message Interrupt Line"] + #[inline(always)] + pub fn rf0nl(&mut self) -> RF0NL_W { + RF0NL_W { w: self } + } + #[doc = "Bit 1 - Rx FIFO 0 Watermark Reached Interrupt Line"] + #[inline(always)] + pub fn rf0wl(&mut self) -> RF0WL_W { + RF0WL_W { w: self } + } + #[doc = "Bit 2 - Rx FIFO 0 Full Interrupt Line"] + #[inline(always)] + pub fn rf0fl(&mut self) -> RF0FL_W { + RF0FL_W { w: self } + } + #[doc = "Bit 3 - Rx FIFO 0 Message Lost Interrupt Line"] + #[inline(always)] + pub fn rf0ll(&mut self) -> RF0LL_W { + RF0LL_W { w: self } + } + #[doc = "Bit 4 - Rx FIFO 1 New Message Interrupt Line"] + #[inline(always)] + pub fn rf1nl(&mut self) -> RF1NL_W { + RF1NL_W { w: self } + } + #[doc = "Bit 5 - Rx FIFO 1 Watermark Reached Interrupt Line"] + #[inline(always)] + pub fn rf1wl(&mut self) -> RF1WL_W { + RF1WL_W { w: self } + } + #[doc = "Bit 6 - Rx FIFO 1 FIFO Full Interrupt Line"] + #[inline(always)] + pub fn rf1fl(&mut self) -> RF1FL_W { + RF1FL_W { w: self } + } + #[doc = "Bit 7 - Rx FIFO 1 Message Lost Interrupt Line"] + #[inline(always)] + pub fn rf1ll(&mut self) -> RF1LL_W { + RF1LL_W { w: self } + } + #[doc = "Bit 8 - High Priority Message Interrupt Line"] + #[inline(always)] + pub fn hpml(&mut self) -> HPML_W { + HPML_W { w: self } + } + #[doc = "Bit 9 - Timestamp Completed Interrupt Line"] + #[inline(always)] + pub fn tcl(&mut self) -> TCL_W { + TCL_W { w: self } + } + #[doc = "Bit 10 - Transmission Cancellation Finished Interrupt Line"] + #[inline(always)] + pub fn tcfl(&mut self) -> TCFL_W { + TCFL_W { w: self } + } + #[doc = "Bit 11 - Tx FIFO Empty Interrupt Line"] + #[inline(always)] + pub fn tfel(&mut self) -> TFEL_W { + TFEL_W { w: self } + } + #[doc = "Bit 12 - Tx Event FIFO New Entry Interrupt Line"] + #[inline(always)] + pub fn tefnl(&mut self) -> TEFNL_W { + TEFNL_W { w: self } + } + #[doc = "Bit 13 - Tx Event FIFO Watermark Reached Interrupt Line"] + #[inline(always)] + pub fn tefwl(&mut self) -> TEFWL_W { + TEFWL_W { w: self } + } + #[doc = "Bit 14 - Tx Event FIFO Full Interrupt Line"] + #[inline(always)] + pub fn teffl(&mut self) -> TEFFL_W { + TEFFL_W { w: self } + } + #[doc = "Bit 15 - Tx Event FIFO Element Lost Interrupt Line"] + #[inline(always)] + pub fn tefll(&mut self) -> TEFLL_W { + TEFLL_W { w: self } + } + #[doc = "Bit 16 - Timestamp Wraparound Interrupt Line"] + #[inline(always)] + pub fn tswl(&mut self) -> TSWL_W { + TSWL_W { w: self } + } + #[doc = "Bit 17 - Message RAM Access Failure Interrupt Line"] + #[inline(always)] + pub fn mrafl(&mut self) -> MRAFL_W { + MRAFL_W { w: self } + } + #[doc = "Bit 18 - Timeout Occurred Interrupt Line"] + #[inline(always)] + pub fn tool(&mut self) -> TOOL_W { + TOOL_W { w: self } + } + #[doc = "Bit 19 - Message stored to Dedicated Rx Buffer Interrupt Line"] + #[inline(always)] + pub fn drxl(&mut self) -> DRXL_W { + DRXL_W { w: self } + } + #[doc = "Bit 20 - Bit Error Corrected Interrupt Line"] + #[inline(always)] + pub fn becl(&mut self) -> BECL_W { + BECL_W { w: self } + } + #[doc = "Bit 21 - Bit Error Uncorrected Interrupt Line"] + #[inline(always)] + pub fn beul(&mut self) -> BEUL_W { + BEUL_W { w: self } + } + #[doc = "Bit 22 - Error Logging Overflow Interrupt Line"] + #[inline(always)] + pub fn elol(&mut self) -> ELOL_W { + ELOL_W { w: self } + } + #[doc = "Bit 23 - Error Passive Interrupt Line"] + #[inline(always)] + pub fn epl(&mut self) -> EPL_W { + EPL_W { w: self } + } + #[doc = "Bit 24 - Warning Status Interrupt Line"] + #[inline(always)] + pub fn ewl(&mut self) -> EWL_W { + EWL_W { w: self } + } + #[doc = "Bit 25 - Bus_Off Status Interrupt Line"] + #[inline(always)] + pub fn bol(&mut self) -> BOL_W { + BOL_W { w: self } + } + #[doc = "Bit 26 - Watchdog Interrupt Interrupt Line"] + #[inline(always)] + pub fn wdil(&mut self) -> WDIL_W { + WDIL_W { w: self } + } + #[doc = "Bit 27 - Protocol Error in Arbitration Phase Line"] + #[inline(always)] + pub fn peal(&mut self) -> PEAL_W { + PEAL_W { w: self } + } + #[doc = "Bit 28 - Protocol Error in Data Phase Line"] + #[inline(always)] + pub fn pedl(&mut self) -> PEDL_W { + PEDL_W { w: self } + } + #[doc = "Bit 29 - Access to Reserved Address Line"] + #[inline(always)] + pub fn aral(&mut self) -> ARAL_W { + ARAL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Line Select\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ils](index.html) module"] +pub struct ILS_SPEC; +impl crate::RegisterSpec for ILS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ils::R](R) reader structure"] +impl crate::Readable for ILS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ils::W](W) writer structure"] +impl crate::Writable for ILS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ILS to value 0"] +impl crate::Resettable for ILS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/can0/ir.rs b/pac/atsamc21n/src/can0/ir.rs new file mode 100644 index 000000000000..ae6efc178861 --- /dev/null +++ b/pac/atsamc21n/src/can0/ir.rs @@ -0,0 +1,1476 @@ +#[doc = "Register `IR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `IR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RF0N` reader - Rx FIFO 0 New Message"] +pub struct RF0N_R(crate::FieldReader); +impl RF0N_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF0N_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF0N_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF0N` writer - Rx FIFO 0 New Message"] +pub struct RF0N_W<'a> { + w: &'a mut W, +} +impl<'a> RF0N_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `RF0W` reader - Rx FIFO 0 Watermark Reached"] +pub struct RF0W_R(crate::FieldReader); +impl RF0W_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF0W_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF0W_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF0W` writer - Rx FIFO 0 Watermark Reached"] +pub struct RF0W_W<'a> { + w: &'a mut W, +} +impl<'a> RF0W_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RF0F` reader - Rx FIFO 0 Full"] +pub struct RF0F_R(crate::FieldReader); +impl RF0F_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF0F_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF0F_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF0F` writer - Rx FIFO 0 Full"] +pub struct RF0F_W<'a> { + w: &'a mut W, +} +impl<'a> RF0F_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RF0L` reader - Rx FIFO 0 Message Lost"] +pub struct RF0L_R(crate::FieldReader); +impl RF0L_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF0L_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF0L_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF0L` writer - Rx FIFO 0 Message Lost"] +pub struct RF0L_W<'a> { + w: &'a mut W, +} +impl<'a> RF0L_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `RF1N` reader - Rx FIFO 1 New Message"] +pub struct RF1N_R(crate::FieldReader); +impl RF1N_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF1N_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF1N_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF1N` writer - Rx FIFO 1 New Message"] +pub struct RF1N_W<'a> { + w: &'a mut W, +} +impl<'a> RF1N_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RF1W` reader - Rx FIFO 1 Watermark Reached"] +pub struct RF1W_R(crate::FieldReader); +impl RF1W_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF1W_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF1W_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF1W` writer - Rx FIFO 1 Watermark Reached"] +pub struct RF1W_W<'a> { + w: &'a mut W, +} +impl<'a> RF1W_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `RF1F` reader - Rx FIFO 1 FIFO Full"] +pub struct RF1F_R(crate::FieldReader); +impl RF1F_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF1F_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF1F_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF1F` writer - Rx FIFO 1 FIFO Full"] +pub struct RF1F_W<'a> { + w: &'a mut W, +} +impl<'a> RF1F_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `RF1L` reader - Rx FIFO 1 Message Lost"] +pub struct RF1L_R(crate::FieldReader); +impl RF1L_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF1L_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF1L_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF1L` writer - Rx FIFO 1 Message Lost"] +pub struct RF1L_W<'a> { + w: &'a mut W, +} +impl<'a> RF1L_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `HPM` reader - High Priority Message"] +pub struct HPM_R(crate::FieldReader); +impl HPM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HPM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HPM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HPM` writer - High Priority Message"] +pub struct HPM_W<'a> { + w: &'a mut W, +} +impl<'a> HPM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `TC` reader - Timestamp Completed"] +pub struct TC_R(crate::FieldReader); +impl TC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC` writer - Timestamp Completed"] +pub struct TC_W<'a> { + w: &'a mut W, +} +impl<'a> TC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `TCF` reader - Transmission Cancellation Finished"] +pub struct TCF_R(crate::FieldReader); +impl TCF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCF` writer - Transmission Cancellation Finished"] +pub struct TCF_W<'a> { + w: &'a mut W, +} +impl<'a> TCF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `TFE` reader - Tx FIFO Empty"] +pub struct TFE_R(crate::FieldReader); +impl TFE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TFE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TFE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TFE` writer - Tx FIFO Empty"] +pub struct TFE_W<'a> { + w: &'a mut W, +} +impl<'a> TFE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `TEFN` reader - Tx Event FIFO New Entry"] +pub struct TEFN_R(crate::FieldReader); +impl TEFN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TEFN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TEFN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TEFN` writer - Tx Event FIFO New Entry"] +pub struct TEFN_W<'a> { + w: &'a mut W, +} +impl<'a> TEFN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `TEFW` reader - Tx Event FIFO Watermark Reached"] +pub struct TEFW_R(crate::FieldReader); +impl TEFW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TEFW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TEFW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TEFW` writer - Tx Event FIFO Watermark Reached"] +pub struct TEFW_W<'a> { + w: &'a mut W, +} +impl<'a> TEFW_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `TEFF` reader - Tx Event FIFO Full"] +pub struct TEFF_R(crate::FieldReader); +impl TEFF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TEFF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TEFF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TEFF` writer - Tx Event FIFO Full"] +pub struct TEFF_W<'a> { + w: &'a mut W, +} +impl<'a> TEFF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `TEFL` reader - Tx Event FIFO Element Lost"] +pub struct TEFL_R(crate::FieldReader); +impl TEFL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TEFL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TEFL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TEFL` writer - Tx Event FIFO Element Lost"] +pub struct TEFL_W<'a> { + w: &'a mut W, +} +impl<'a> TEFL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `TSW` reader - Timestamp Wraparound"] +pub struct TSW_R(crate::FieldReader); +impl TSW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSW` writer - Timestamp Wraparound"] +pub struct TSW_W<'a> { + w: &'a mut W, +} +impl<'a> TSW_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `MRAF` reader - Message RAM Access Failure"] +pub struct MRAF_R(crate::FieldReader); +impl MRAF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MRAF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MRAF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MRAF` writer - Message RAM Access Failure"] +pub struct MRAF_W<'a> { + w: &'a mut W, +} +impl<'a> MRAF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `TOO` reader - Timeout Occurred"] +pub struct TOO_R(crate::FieldReader); +impl TOO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TOO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TOO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TOO` writer - Timeout Occurred"] +pub struct TOO_W<'a> { + w: &'a mut W, +} +impl<'a> TOO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `DRX` reader - Message stored to Dedicated Rx Buffer"] +pub struct DRX_R(crate::FieldReader); +impl DRX_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRX_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRX_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRX` writer - Message stored to Dedicated Rx Buffer"] +pub struct DRX_W<'a> { + w: &'a mut W, +} +impl<'a> DRX_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `BEC` reader - Bit Error Corrected"] +pub struct BEC_R(crate::FieldReader); +impl BEC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BEC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BEC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BEC` writer - Bit Error Corrected"] +pub struct BEC_W<'a> { + w: &'a mut W, +} +impl<'a> BEC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `BEU` reader - Bit Error Uncorrected"] +pub struct BEU_R(crate::FieldReader); +impl BEU_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BEU_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BEU_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BEU` writer - Bit Error Uncorrected"] +pub struct BEU_W<'a> { + w: &'a mut W, +} +impl<'a> BEU_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `ELO` reader - Error Logging Overflow"] +pub struct ELO_R(crate::FieldReader); +impl ELO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ELO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ELO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ELO` writer - Error Logging Overflow"] +pub struct ELO_W<'a> { + w: &'a mut W, +} +impl<'a> ELO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `EP` reader - Error Passive"] +pub struct EP_R(crate::FieldReader); +impl EP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EP` writer - Error Passive"] +pub struct EP_W<'a> { + w: &'a mut W, +} +impl<'a> EP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `EW` reader - Warning Status"] +pub struct EW_R(crate::FieldReader); +impl EW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EW` writer - Warning Status"] +pub struct EW_W<'a> { + w: &'a mut W, +} +impl<'a> EW_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `BO` reader - Bus_Off Status"] +pub struct BO_R(crate::FieldReader); +impl BO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BO` writer - Bus_Off Status"] +pub struct BO_W<'a> { + w: &'a mut W, +} +impl<'a> BO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `WDI` reader - Watchdog Interrupt"] +pub struct WDI_R(crate::FieldReader); +impl WDI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WDI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WDI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WDI` writer - Watchdog Interrupt"] +pub struct WDI_W<'a> { + w: &'a mut W, +} +impl<'a> WDI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `PEA` reader - Protocol Error in Arbitration Phase"] +pub struct PEA_R(crate::FieldReader); +impl PEA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEA` writer - Protocol Error in Arbitration Phase"] +pub struct PEA_W<'a> { + w: &'a mut W, +} +impl<'a> PEA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +#[doc = "Field `PED` reader - Protocol Error in Data Phase"] +pub struct PED_R(crate::FieldReader); +impl PED_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PED_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PED` writer - Protocol Error in Data Phase"] +pub struct PED_W<'a> { + w: &'a mut W, +} +impl<'a> PED_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Field `ARA` reader - Access to Reserved Address"] +pub struct ARA_R(crate::FieldReader); +impl ARA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ARA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ARA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ARA` writer - Access to Reserved Address"] +pub struct ARA_W<'a> { + w: &'a mut W, +} +impl<'a> ARA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29); + self.w + } +} +impl R { + #[doc = "Bit 0 - Rx FIFO 0 New Message"] + #[inline(always)] + pub fn rf0n(&self) -> RF0N_R { + RF0N_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Rx FIFO 0 Watermark Reached"] + #[inline(always)] + pub fn rf0w(&self) -> RF0W_R { + RF0W_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Rx FIFO 0 Full"] + #[inline(always)] + pub fn rf0f(&self) -> RF0F_R { + RF0F_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Rx FIFO 0 Message Lost"] + #[inline(always)] + pub fn rf0l(&self) -> RF0L_R { + RF0L_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Rx FIFO 1 New Message"] + #[inline(always)] + pub fn rf1n(&self) -> RF1N_R { + RF1N_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Rx FIFO 1 Watermark Reached"] + #[inline(always)] + pub fn rf1w(&self) -> RF1W_R { + RF1W_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Rx FIFO 1 FIFO Full"] + #[inline(always)] + pub fn rf1f(&self) -> RF1F_R { + RF1F_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Rx FIFO 1 Message Lost"] + #[inline(always)] + pub fn rf1l(&self) -> RF1L_R { + RF1L_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - High Priority Message"] + #[inline(always)] + pub fn hpm(&self) -> HPM_R { + HPM_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Timestamp Completed"] + #[inline(always)] + pub fn tc(&self) -> TC_R { + TC_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Transmission Cancellation Finished"] + #[inline(always)] + pub fn tcf(&self) -> TCF_R { + TCF_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Tx FIFO Empty"] + #[inline(always)] + pub fn tfe(&self) -> TFE_R { + TFE_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Tx Event FIFO New Entry"] + #[inline(always)] + pub fn tefn(&self) -> TEFN_R { + TEFN_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Tx Event FIFO Watermark Reached"] + #[inline(always)] + pub fn tefw(&self) -> TEFW_R { + TEFW_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Tx Event FIFO Full"] + #[inline(always)] + pub fn teff(&self) -> TEFF_R { + TEFF_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Tx Event FIFO Element Lost"] + #[inline(always)] + pub fn tefl(&self) -> TEFL_R { + TEFL_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Timestamp Wraparound"] + #[inline(always)] + pub fn tsw(&self) -> TSW_R { + TSW_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Message RAM Access Failure"] + #[inline(always)] + pub fn mraf(&self) -> MRAF_R { + MRAF_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Timeout Occurred"] + #[inline(always)] + pub fn too(&self) -> TOO_R { + TOO_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Message stored to Dedicated Rx Buffer"] + #[inline(always)] + pub fn drx(&self) -> DRX_R { + DRX_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Bit Error Corrected"] + #[inline(always)] + pub fn bec(&self) -> BEC_R { + BEC_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Bit Error Uncorrected"] + #[inline(always)] + pub fn beu(&self) -> BEU_R { + BEU_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Error Logging Overflow"] + #[inline(always)] + pub fn elo(&self) -> ELO_R { + ELO_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Error Passive"] + #[inline(always)] + pub fn ep(&self) -> EP_R { + EP_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24 - Warning Status"] + #[inline(always)] + pub fn ew(&self) -> EW_R { + EW_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Bus_Off Status"] + #[inline(always)] + pub fn bo(&self) -> BO_R { + BO_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Watchdog Interrupt"] + #[inline(always)] + pub fn wdi(&self) -> WDI_R { + WDI_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Protocol Error in Arbitration Phase"] + #[inline(always)] + pub fn pea(&self) -> PEA_R { + PEA_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28 - Protocol Error in Data Phase"] + #[inline(always)] + pub fn ped(&self) -> PED_R { + PED_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Access to Reserved Address"] + #[inline(always)] + pub fn ara(&self) -> ARA_R { + ARA_R::new(((self.bits >> 29) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Rx FIFO 0 New Message"] + #[inline(always)] + pub fn rf0n(&mut self) -> RF0N_W { + RF0N_W { w: self } + } + #[doc = "Bit 1 - Rx FIFO 0 Watermark Reached"] + #[inline(always)] + pub fn rf0w(&mut self) -> RF0W_W { + RF0W_W { w: self } + } + #[doc = "Bit 2 - Rx FIFO 0 Full"] + #[inline(always)] + pub fn rf0f(&mut self) -> RF0F_W { + RF0F_W { w: self } + } + #[doc = "Bit 3 - Rx FIFO 0 Message Lost"] + #[inline(always)] + pub fn rf0l(&mut self) -> RF0L_W { + RF0L_W { w: self } + } + #[doc = "Bit 4 - Rx FIFO 1 New Message"] + #[inline(always)] + pub fn rf1n(&mut self) -> RF1N_W { + RF1N_W { w: self } + } + #[doc = "Bit 5 - Rx FIFO 1 Watermark Reached"] + #[inline(always)] + pub fn rf1w(&mut self) -> RF1W_W { + RF1W_W { w: self } + } + #[doc = "Bit 6 - Rx FIFO 1 FIFO Full"] + #[inline(always)] + pub fn rf1f(&mut self) -> RF1F_W { + RF1F_W { w: self } + } + #[doc = "Bit 7 - Rx FIFO 1 Message Lost"] + #[inline(always)] + pub fn rf1l(&mut self) -> RF1L_W { + RF1L_W { w: self } + } + #[doc = "Bit 8 - High Priority Message"] + #[inline(always)] + pub fn hpm(&mut self) -> HPM_W { + HPM_W { w: self } + } + #[doc = "Bit 9 - Timestamp Completed"] + #[inline(always)] + pub fn tc(&mut self) -> TC_W { + TC_W { w: self } + } + #[doc = "Bit 10 - Transmission Cancellation Finished"] + #[inline(always)] + pub fn tcf(&mut self) -> TCF_W { + TCF_W { w: self } + } + #[doc = "Bit 11 - Tx FIFO Empty"] + #[inline(always)] + pub fn tfe(&mut self) -> TFE_W { + TFE_W { w: self } + } + #[doc = "Bit 12 - Tx Event FIFO New Entry"] + #[inline(always)] + pub fn tefn(&mut self) -> TEFN_W { + TEFN_W { w: self } + } + #[doc = "Bit 13 - Tx Event FIFO Watermark Reached"] + #[inline(always)] + pub fn tefw(&mut self) -> TEFW_W { + TEFW_W { w: self } + } + #[doc = "Bit 14 - Tx Event FIFO Full"] + #[inline(always)] + pub fn teff(&mut self) -> TEFF_W { + TEFF_W { w: self } + } + #[doc = "Bit 15 - Tx Event FIFO Element Lost"] + #[inline(always)] + pub fn tefl(&mut self) -> TEFL_W { + TEFL_W { w: self } + } + #[doc = "Bit 16 - Timestamp Wraparound"] + #[inline(always)] + pub fn tsw(&mut self) -> TSW_W { + TSW_W { w: self } + } + #[doc = "Bit 17 - Message RAM Access Failure"] + #[inline(always)] + pub fn mraf(&mut self) -> MRAF_W { + MRAF_W { w: self } + } + #[doc = "Bit 18 - Timeout Occurred"] + #[inline(always)] + pub fn too(&mut self) -> TOO_W { + TOO_W { w: self } + } + #[doc = "Bit 19 - Message stored to Dedicated Rx Buffer"] + #[inline(always)] + pub fn drx(&mut self) -> DRX_W { + DRX_W { w: self } + } + #[doc = "Bit 20 - Bit Error Corrected"] + #[inline(always)] + pub fn bec(&mut self) -> BEC_W { + BEC_W { w: self } + } + #[doc = "Bit 21 - Bit Error Uncorrected"] + #[inline(always)] + pub fn beu(&mut self) -> BEU_W { + BEU_W { w: self } + } + #[doc = "Bit 22 - Error Logging Overflow"] + #[inline(always)] + pub fn elo(&mut self) -> ELO_W { + ELO_W { w: self } + } + #[doc = "Bit 23 - Error Passive"] + #[inline(always)] + pub fn ep(&mut self) -> EP_W { + EP_W { w: self } + } + #[doc = "Bit 24 - Warning Status"] + #[inline(always)] + pub fn ew(&mut self) -> EW_W { + EW_W { w: self } + } + #[doc = "Bit 25 - Bus_Off Status"] + #[inline(always)] + pub fn bo(&mut self) -> BO_W { + BO_W { w: self } + } + #[doc = "Bit 26 - Watchdog Interrupt"] + #[inline(always)] + pub fn wdi(&mut self) -> WDI_W { + WDI_W { w: self } + } + #[doc = "Bit 27 - Protocol Error in Arbitration Phase"] + #[inline(always)] + pub fn pea(&mut self) -> PEA_W { + PEA_W { w: self } + } + #[doc = "Bit 28 - Protocol Error in Data Phase"] + #[inline(always)] + pub fn ped(&mut self) -> PED_W { + PED_W { w: self } + } + #[doc = "Bit 29 - Access to Reserved Address"] + #[inline(always)] + pub fn ara(&mut self) -> ARA_W { + ARA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ir](index.html) module"] +pub struct IR_SPEC; +impl crate::RegisterSpec for IR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ir::R](R) reader structure"] +impl crate::Readable for IR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ir::W](W) writer structure"] +impl crate::Writable for IR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets IR to value 0"] +impl crate::Resettable for IR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/can0/mrcfg.rs b/pac/atsamc21n/src/can0/mrcfg.rs new file mode 100644 index 000000000000..7a4b25f0969a --- /dev/null +++ b/pac/atsamc21n/src/can0/mrcfg.rs @@ -0,0 +1,178 @@ +#[doc = "Register `MRCFG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MRCFG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Quality of Service\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum QOS_A { + #[doc = "0: Background (no sensitive operation)"] + DISABLE = 0, + #[doc = "1: Sensitive Bandwidth"] + LOW = 1, + #[doc = "2: Sensitive Latency"] + MEDIUM = 2, + #[doc = "3: Critical Latency"] + HIGH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: QOS_A) -> Self { + variant as _ + } +} +#[doc = "Field `QOS` reader - Quality of Service"] +pub struct QOS_R(crate::FieldReader); +impl QOS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + QOS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> QOS_A { + match self.bits { + 0 => QOS_A::DISABLE, + 1 => QOS_A::LOW, + 2 => QOS_A::MEDIUM, + 3 => QOS_A::HIGH, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == QOS_A::DISABLE + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == QOS_A::LOW + } + #[doc = "Checks if the value of the field is `MEDIUM`"] + #[inline(always)] + pub fn is_medium(&self) -> bool { + **self == QOS_A::MEDIUM + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == QOS_A::HIGH + } +} +impl core::ops::Deref for QOS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `QOS` writer - Quality of Service"] +pub struct QOS_W<'a> { + w: &'a mut W, +} +impl<'a> QOS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: QOS_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Background (no sensitive operation)"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(QOS_A::DISABLE) + } + #[doc = "Sensitive Bandwidth"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(QOS_A::LOW) + } + #[doc = "Sensitive Latency"] + #[inline(always)] + pub fn medium(self) -> &'a mut W { + self.variant(QOS_A::MEDIUM) + } + #[doc = "Critical Latency"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(QOS_A::HIGH) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u32 & 0x03); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Quality of Service"] + #[inline(always)] + pub fn qos(&self) -> QOS_R { + QOS_R::new((self.bits & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Quality of Service"] + #[inline(always)] + pub fn qos(&mut self) -> QOS_W { + QOS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Message RAM Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mrcfg](index.html) module"] +pub struct MRCFG_SPEC; +impl crate::RegisterSpec for MRCFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [mrcfg::R](R) reader structure"] +impl crate::Readable for MRCFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [mrcfg::W](W) writer structure"] +impl crate::Writable for MRCFG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets MRCFG to value 0x02"] +impl crate::Resettable for MRCFG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x02 + } +} diff --git a/pac/atsamc21n/src/can0/nbtp.rs b/pac/atsamc21n/src/can0/nbtp.rs new file mode 100644 index 000000000000..8de06d283b22 --- /dev/null +++ b/pac/atsamc21n/src/can0/nbtp.rs @@ -0,0 +1,214 @@ +#[doc = "Register `NBTP` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `NBTP` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `NTSEG2` reader - Nominal Time segment after sample point"] +pub struct NTSEG2_R(crate::FieldReader); +impl NTSEG2_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + NTSEG2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NTSEG2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NTSEG2` writer - Nominal Time segment after sample point"] +pub struct NTSEG2_W<'a> { + w: &'a mut W, +} +impl<'a> NTSEG2_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x7f) | (value as u32 & 0x7f); + self.w + } +} +#[doc = "Field `NTSEG1` reader - Nominal Time segment before sample point"] +pub struct NTSEG1_R(crate::FieldReader); +impl NTSEG1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + NTSEG1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NTSEG1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NTSEG1` writer - Nominal Time segment before sample point"] +pub struct NTSEG1_W<'a> { + w: &'a mut W, +} +impl<'a> NTSEG1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +#[doc = "Field `NBRP` reader - Nominal Baud Rate Prescaler"] +pub struct NBRP_R(crate::FieldReader); +impl NBRP_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + NBRP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NBRP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NBRP` writer - Nominal Baud Rate Prescaler"] +pub struct NBRP_W<'a> { + w: &'a mut W, +} +impl<'a> NBRP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01ff << 16)) | ((value as u32 & 0x01ff) << 16); + self.w + } +} +#[doc = "Field `NSJW` reader - Nominal (Re)Synchronization Jump Width"] +pub struct NSJW_R(crate::FieldReader); +impl NSJW_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + NSJW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NSJW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NSJW` writer - Nominal (Re)Synchronization Jump Width"] +pub struct NSJW_W<'a> { + w: &'a mut W, +} +impl<'a> NSJW_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x7f << 25)) | ((value as u32 & 0x7f) << 25); + self.w + } +} +impl R { + #[doc = "Bits 0:6 - Nominal Time segment after sample point"] + #[inline(always)] + pub fn ntseg2(&self) -> NTSEG2_R { + NTSEG2_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bits 8:15 - Nominal Time segment before sample point"] + #[inline(always)] + pub fn ntseg1(&self) -> NTSEG1_R { + NTSEG1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:24 - Nominal Baud Rate Prescaler"] + #[inline(always)] + pub fn nbrp(&self) -> NBRP_R { + NBRP_R::new(((self.bits >> 16) & 0x01ff) as u16) + } + #[doc = "Bits 25:31 - Nominal (Re)Synchronization Jump Width"] + #[inline(always)] + pub fn nsjw(&self) -> NSJW_R { + NSJW_R::new(((self.bits >> 25) & 0x7f) as u8) + } +} +impl W { + #[doc = "Bits 0:6 - Nominal Time segment after sample point"] + #[inline(always)] + pub fn ntseg2(&mut self) -> NTSEG2_W { + NTSEG2_W { w: self } + } + #[doc = "Bits 8:15 - Nominal Time segment before sample point"] + #[inline(always)] + pub fn ntseg1(&mut self) -> NTSEG1_W { + NTSEG1_W { w: self } + } + #[doc = "Bits 16:24 - Nominal Baud Rate Prescaler"] + #[inline(always)] + pub fn nbrp(&mut self) -> NBRP_W { + NBRP_W { w: self } + } + #[doc = "Bits 25:31 - Nominal (Re)Synchronization Jump Width"] + #[inline(always)] + pub fn nsjw(&mut self) -> NSJW_W { + NSJW_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Nominal Bit Timing and Prescaler\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [nbtp](index.html) module"] +pub struct NBTP_SPEC; +impl crate::RegisterSpec for NBTP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [nbtp::R](R) reader structure"] +impl crate::Readable for NBTP_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [nbtp::W](W) writer structure"] +impl crate::Writable for NBTP_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets NBTP to value 0x0600_0a03"] +impl crate::Resettable for NBTP_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0600_0a03 + } +} diff --git a/pac/atsamc21n/src/can0/ndat1.rs b/pac/atsamc21n/src/can0/ndat1.rs new file mode 100644 index 000000000000..63da465a27d8 --- /dev/null +++ b/pac/atsamc21n/src/can0/ndat1.rs @@ -0,0 +1,1570 @@ +#[doc = "Register `NDAT1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `NDAT1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ND0` reader - New Data 0"] +pub struct ND0_R(crate::FieldReader); +impl ND0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND0` writer - New Data 0"] +pub struct ND0_W<'a> { + w: &'a mut W, +} +impl<'a> ND0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ND1` reader - New Data 1"] +pub struct ND1_R(crate::FieldReader); +impl ND1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND1` writer - New Data 1"] +pub struct ND1_W<'a> { + w: &'a mut W, +} +impl<'a> ND1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ND2` reader - New Data 2"] +pub struct ND2_R(crate::FieldReader); +impl ND2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND2` writer - New Data 2"] +pub struct ND2_W<'a> { + w: &'a mut W, +} +impl<'a> ND2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `ND3` reader - New Data 3"] +pub struct ND3_R(crate::FieldReader); +impl ND3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND3` writer - New Data 3"] +pub struct ND3_W<'a> { + w: &'a mut W, +} +impl<'a> ND3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ND4` reader - New Data 4"] +pub struct ND4_R(crate::FieldReader); +impl ND4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND4` writer - New Data 4"] +pub struct ND4_W<'a> { + w: &'a mut W, +} +impl<'a> ND4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `ND5` reader - New Data 5"] +pub struct ND5_R(crate::FieldReader); +impl ND5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND5` writer - New Data 5"] +pub struct ND5_W<'a> { + w: &'a mut W, +} +impl<'a> ND5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `ND6` reader - New Data 6"] +pub struct ND6_R(crate::FieldReader); +impl ND6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND6` writer - New Data 6"] +pub struct ND6_W<'a> { + w: &'a mut W, +} +impl<'a> ND6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ND7` reader - New Data 7"] +pub struct ND7_R(crate::FieldReader); +impl ND7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND7` writer - New Data 7"] +pub struct ND7_W<'a> { + w: &'a mut W, +} +impl<'a> ND7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `ND8` reader - New Data 8"] +pub struct ND8_R(crate::FieldReader); +impl ND8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND8` writer - New Data 8"] +pub struct ND8_W<'a> { + w: &'a mut W, +} +impl<'a> ND8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `ND9` reader - New Data 9"] +pub struct ND9_R(crate::FieldReader); +impl ND9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND9` writer - New Data 9"] +pub struct ND9_W<'a> { + w: &'a mut W, +} +impl<'a> ND9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `ND10` reader - New Data 10"] +pub struct ND10_R(crate::FieldReader); +impl ND10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND10` writer - New Data 10"] +pub struct ND10_W<'a> { + w: &'a mut W, +} +impl<'a> ND10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `ND11` reader - New Data 11"] +pub struct ND11_R(crate::FieldReader); +impl ND11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND11` writer - New Data 11"] +pub struct ND11_W<'a> { + w: &'a mut W, +} +impl<'a> ND11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `ND12` reader - New Data 12"] +pub struct ND12_R(crate::FieldReader); +impl ND12_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND12_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND12_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND12` writer - New Data 12"] +pub struct ND12_W<'a> { + w: &'a mut W, +} +impl<'a> ND12_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `ND13` reader - New Data 13"] +pub struct ND13_R(crate::FieldReader); +impl ND13_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND13_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND13_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND13` writer - New Data 13"] +pub struct ND13_W<'a> { + w: &'a mut W, +} +impl<'a> ND13_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `ND14` reader - New Data 14"] +pub struct ND14_R(crate::FieldReader); +impl ND14_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND14_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND14_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND14` writer - New Data 14"] +pub struct ND14_W<'a> { + w: &'a mut W, +} +impl<'a> ND14_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `ND15` reader - New Data 15"] +pub struct ND15_R(crate::FieldReader); +impl ND15_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND15_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND15_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND15` writer - New Data 15"] +pub struct ND15_W<'a> { + w: &'a mut W, +} +impl<'a> ND15_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `ND16` reader - New Data 16"] +pub struct ND16_R(crate::FieldReader); +impl ND16_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND16_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND16_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND16` writer - New Data 16"] +pub struct ND16_W<'a> { + w: &'a mut W, +} +impl<'a> ND16_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `ND17` reader - New Data 17"] +pub struct ND17_R(crate::FieldReader); +impl ND17_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND17_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND17_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND17` writer - New Data 17"] +pub struct ND17_W<'a> { + w: &'a mut W, +} +impl<'a> ND17_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `ND18` reader - New Data 18"] +pub struct ND18_R(crate::FieldReader); +impl ND18_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND18_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND18_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND18` writer - New Data 18"] +pub struct ND18_W<'a> { + w: &'a mut W, +} +impl<'a> ND18_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `ND19` reader - New Data 19"] +pub struct ND19_R(crate::FieldReader); +impl ND19_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND19_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND19_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND19` writer - New Data 19"] +pub struct ND19_W<'a> { + w: &'a mut W, +} +impl<'a> ND19_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `ND20` reader - New Data 20"] +pub struct ND20_R(crate::FieldReader); +impl ND20_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND20_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND20_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND20` writer - New Data 20"] +pub struct ND20_W<'a> { + w: &'a mut W, +} +impl<'a> ND20_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `ND21` reader - New Data 21"] +pub struct ND21_R(crate::FieldReader); +impl ND21_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND21_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND21_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND21` writer - New Data 21"] +pub struct ND21_W<'a> { + w: &'a mut W, +} +impl<'a> ND21_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `ND22` reader - New Data 22"] +pub struct ND22_R(crate::FieldReader); +impl ND22_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND22_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND22_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND22` writer - New Data 22"] +pub struct ND22_W<'a> { + w: &'a mut W, +} +impl<'a> ND22_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `ND23` reader - New Data 23"] +pub struct ND23_R(crate::FieldReader); +impl ND23_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND23_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND23_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND23` writer - New Data 23"] +pub struct ND23_W<'a> { + w: &'a mut W, +} +impl<'a> ND23_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `ND24` reader - New Data 24"] +pub struct ND24_R(crate::FieldReader); +impl ND24_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND24_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND24_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND24` writer - New Data 24"] +pub struct ND24_W<'a> { + w: &'a mut W, +} +impl<'a> ND24_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `ND25` reader - New Data 25"] +pub struct ND25_R(crate::FieldReader); +impl ND25_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND25_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND25_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND25` writer - New Data 25"] +pub struct ND25_W<'a> { + w: &'a mut W, +} +impl<'a> ND25_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `ND26` reader - New Data 26"] +pub struct ND26_R(crate::FieldReader); +impl ND26_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND26_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND26_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND26` writer - New Data 26"] +pub struct ND26_W<'a> { + w: &'a mut W, +} +impl<'a> ND26_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `ND27` reader - New Data 27"] +pub struct ND27_R(crate::FieldReader); +impl ND27_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND27_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND27_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND27` writer - New Data 27"] +pub struct ND27_W<'a> { + w: &'a mut W, +} +impl<'a> ND27_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +#[doc = "Field `ND28` reader - New Data 28"] +pub struct ND28_R(crate::FieldReader); +impl ND28_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND28_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND28_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND28` writer - New Data 28"] +pub struct ND28_W<'a> { + w: &'a mut W, +} +impl<'a> ND28_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Field `ND29` reader - New Data 29"] +pub struct ND29_R(crate::FieldReader); +impl ND29_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND29_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND29_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND29` writer - New Data 29"] +pub struct ND29_W<'a> { + w: &'a mut W, +} +impl<'a> ND29_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29); + self.w + } +} +#[doc = "Field `ND30` reader - New Data 30"] +pub struct ND30_R(crate::FieldReader); +impl ND30_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND30_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND30_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND30` writer - New Data 30"] +pub struct ND30_W<'a> { + w: &'a mut W, +} +impl<'a> ND30_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +#[doc = "Field `ND31` reader - New Data 31"] +pub struct ND31_R(crate::FieldReader); +impl ND31_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND31_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND31_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND31` writer - New Data 31"] +pub struct ND31_W<'a> { + w: &'a mut W, +} +impl<'a> ND31_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bit 0 - New Data 0"] + #[inline(always)] + pub fn nd0(&self) -> ND0_R { + ND0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - New Data 1"] + #[inline(always)] + pub fn nd1(&self) -> ND1_R { + ND1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - New Data 2"] + #[inline(always)] + pub fn nd2(&self) -> ND2_R { + ND2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - New Data 3"] + #[inline(always)] + pub fn nd3(&self) -> ND3_R { + ND3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - New Data 4"] + #[inline(always)] + pub fn nd4(&self) -> ND4_R { + ND4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - New Data 5"] + #[inline(always)] + pub fn nd5(&self) -> ND5_R { + ND5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - New Data 6"] + #[inline(always)] + pub fn nd6(&self) -> ND6_R { + ND6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - New Data 7"] + #[inline(always)] + pub fn nd7(&self) -> ND7_R { + ND7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - New Data 8"] + #[inline(always)] + pub fn nd8(&self) -> ND8_R { + ND8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - New Data 9"] + #[inline(always)] + pub fn nd9(&self) -> ND9_R { + ND9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - New Data 10"] + #[inline(always)] + pub fn nd10(&self) -> ND10_R { + ND10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - New Data 11"] + #[inline(always)] + pub fn nd11(&self) -> ND11_R { + ND11_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - New Data 12"] + #[inline(always)] + pub fn nd12(&self) -> ND12_R { + ND12_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - New Data 13"] + #[inline(always)] + pub fn nd13(&self) -> ND13_R { + ND13_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - New Data 14"] + #[inline(always)] + pub fn nd14(&self) -> ND14_R { + ND14_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - New Data 15"] + #[inline(always)] + pub fn nd15(&self) -> ND15_R { + ND15_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - New Data 16"] + #[inline(always)] + pub fn nd16(&self) -> ND16_R { + ND16_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - New Data 17"] + #[inline(always)] + pub fn nd17(&self) -> ND17_R { + ND17_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - New Data 18"] + #[inline(always)] + pub fn nd18(&self) -> ND18_R { + ND18_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - New Data 19"] + #[inline(always)] + pub fn nd19(&self) -> ND19_R { + ND19_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - New Data 20"] + #[inline(always)] + pub fn nd20(&self) -> ND20_R { + ND20_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - New Data 21"] + #[inline(always)] + pub fn nd21(&self) -> ND21_R { + ND21_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - New Data 22"] + #[inline(always)] + pub fn nd22(&self) -> ND22_R { + ND22_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - New Data 23"] + #[inline(always)] + pub fn nd23(&self) -> ND23_R { + ND23_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24 - New Data 24"] + #[inline(always)] + pub fn nd24(&self) -> ND24_R { + ND24_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - New Data 25"] + #[inline(always)] + pub fn nd25(&self) -> ND25_R { + ND25_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - New Data 26"] + #[inline(always)] + pub fn nd26(&self) -> ND26_R { + ND26_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - New Data 27"] + #[inline(always)] + pub fn nd27(&self) -> ND27_R { + ND27_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28 - New Data 28"] + #[inline(always)] + pub fn nd28(&self) -> ND28_R { + ND28_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - New Data 29"] + #[inline(always)] + pub fn nd29(&self) -> ND29_R { + ND29_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - New Data 30"] + #[inline(always)] + pub fn nd30(&self) -> ND30_R { + ND30_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 31 - New Data 31"] + #[inline(always)] + pub fn nd31(&self) -> ND31_R { + ND31_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - New Data 0"] + #[inline(always)] + pub fn nd0(&mut self) -> ND0_W { + ND0_W { w: self } + } + #[doc = "Bit 1 - New Data 1"] + #[inline(always)] + pub fn nd1(&mut self) -> ND1_W { + ND1_W { w: self } + } + #[doc = "Bit 2 - New Data 2"] + #[inline(always)] + pub fn nd2(&mut self) -> ND2_W { + ND2_W { w: self } + } + #[doc = "Bit 3 - New Data 3"] + #[inline(always)] + pub fn nd3(&mut self) -> ND3_W { + ND3_W { w: self } + } + #[doc = "Bit 4 - New Data 4"] + #[inline(always)] + pub fn nd4(&mut self) -> ND4_W { + ND4_W { w: self } + } + #[doc = "Bit 5 - New Data 5"] + #[inline(always)] + pub fn nd5(&mut self) -> ND5_W { + ND5_W { w: self } + } + #[doc = "Bit 6 - New Data 6"] + #[inline(always)] + pub fn nd6(&mut self) -> ND6_W { + ND6_W { w: self } + } + #[doc = "Bit 7 - New Data 7"] + #[inline(always)] + pub fn nd7(&mut self) -> ND7_W { + ND7_W { w: self } + } + #[doc = "Bit 8 - New Data 8"] + #[inline(always)] + pub fn nd8(&mut self) -> ND8_W { + ND8_W { w: self } + } + #[doc = "Bit 9 - New Data 9"] + #[inline(always)] + pub fn nd9(&mut self) -> ND9_W { + ND9_W { w: self } + } + #[doc = "Bit 10 - New Data 10"] + #[inline(always)] + pub fn nd10(&mut self) -> ND10_W { + ND10_W { w: self } + } + #[doc = "Bit 11 - New Data 11"] + #[inline(always)] + pub fn nd11(&mut self) -> ND11_W { + ND11_W { w: self } + } + #[doc = "Bit 12 - New Data 12"] + #[inline(always)] + pub fn nd12(&mut self) -> ND12_W { + ND12_W { w: self } + } + #[doc = "Bit 13 - New Data 13"] + #[inline(always)] + pub fn nd13(&mut self) -> ND13_W { + ND13_W { w: self } + } + #[doc = "Bit 14 - New Data 14"] + #[inline(always)] + pub fn nd14(&mut self) -> ND14_W { + ND14_W { w: self } + } + #[doc = "Bit 15 - New Data 15"] + #[inline(always)] + pub fn nd15(&mut self) -> ND15_W { + ND15_W { w: self } + } + #[doc = "Bit 16 - New Data 16"] + #[inline(always)] + pub fn nd16(&mut self) -> ND16_W { + ND16_W { w: self } + } + #[doc = "Bit 17 - New Data 17"] + #[inline(always)] + pub fn nd17(&mut self) -> ND17_W { + ND17_W { w: self } + } + #[doc = "Bit 18 - New Data 18"] + #[inline(always)] + pub fn nd18(&mut self) -> ND18_W { + ND18_W { w: self } + } + #[doc = "Bit 19 - New Data 19"] + #[inline(always)] + pub fn nd19(&mut self) -> ND19_W { + ND19_W { w: self } + } + #[doc = "Bit 20 - New Data 20"] + #[inline(always)] + pub fn nd20(&mut self) -> ND20_W { + ND20_W { w: self } + } + #[doc = "Bit 21 - New Data 21"] + #[inline(always)] + pub fn nd21(&mut self) -> ND21_W { + ND21_W { w: self } + } + #[doc = "Bit 22 - New Data 22"] + #[inline(always)] + pub fn nd22(&mut self) -> ND22_W { + ND22_W { w: self } + } + #[doc = "Bit 23 - New Data 23"] + #[inline(always)] + pub fn nd23(&mut self) -> ND23_W { + ND23_W { w: self } + } + #[doc = "Bit 24 - New Data 24"] + #[inline(always)] + pub fn nd24(&mut self) -> ND24_W { + ND24_W { w: self } + } + #[doc = "Bit 25 - New Data 25"] + #[inline(always)] + pub fn nd25(&mut self) -> ND25_W { + ND25_W { w: self } + } + #[doc = "Bit 26 - New Data 26"] + #[inline(always)] + pub fn nd26(&mut self) -> ND26_W { + ND26_W { w: self } + } + #[doc = "Bit 27 - New Data 27"] + #[inline(always)] + pub fn nd27(&mut self) -> ND27_W { + ND27_W { w: self } + } + #[doc = "Bit 28 - New Data 28"] + #[inline(always)] + pub fn nd28(&mut self) -> ND28_W { + ND28_W { w: self } + } + #[doc = "Bit 29 - New Data 29"] + #[inline(always)] + pub fn nd29(&mut self) -> ND29_W { + ND29_W { w: self } + } + #[doc = "Bit 30 - New Data 30"] + #[inline(always)] + pub fn nd30(&mut self) -> ND30_W { + ND30_W { w: self } + } + #[doc = "Bit 31 - New Data 31"] + #[inline(always)] + pub fn nd31(&mut self) -> ND31_W { + ND31_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "New Data 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ndat1](index.html) module"] +pub struct NDAT1_SPEC; +impl crate::RegisterSpec for NDAT1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ndat1::R](R) reader structure"] +impl crate::Readable for NDAT1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ndat1::W](W) writer structure"] +impl crate::Writable for NDAT1_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets NDAT1 to value 0"] +impl crate::Resettable for NDAT1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/can0/ndat2.rs b/pac/atsamc21n/src/can0/ndat2.rs new file mode 100644 index 000000000000..ada8dac123fb --- /dev/null +++ b/pac/atsamc21n/src/can0/ndat2.rs @@ -0,0 +1,1570 @@ +#[doc = "Register `NDAT2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `NDAT2` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ND32` reader - New Data 32"] +pub struct ND32_R(crate::FieldReader); +impl ND32_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND32_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND32_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND32` writer - New Data 32"] +pub struct ND32_W<'a> { + w: &'a mut W, +} +impl<'a> ND32_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ND33` reader - New Data 33"] +pub struct ND33_R(crate::FieldReader); +impl ND33_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND33_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND33_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND33` writer - New Data 33"] +pub struct ND33_W<'a> { + w: &'a mut W, +} +impl<'a> ND33_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ND34` reader - New Data 34"] +pub struct ND34_R(crate::FieldReader); +impl ND34_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND34_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND34_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND34` writer - New Data 34"] +pub struct ND34_W<'a> { + w: &'a mut W, +} +impl<'a> ND34_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `ND35` reader - New Data 35"] +pub struct ND35_R(crate::FieldReader); +impl ND35_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND35_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND35_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND35` writer - New Data 35"] +pub struct ND35_W<'a> { + w: &'a mut W, +} +impl<'a> ND35_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ND36` reader - New Data 36"] +pub struct ND36_R(crate::FieldReader); +impl ND36_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND36_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND36_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND36` writer - New Data 36"] +pub struct ND36_W<'a> { + w: &'a mut W, +} +impl<'a> ND36_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `ND37` reader - New Data 37"] +pub struct ND37_R(crate::FieldReader); +impl ND37_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND37_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND37_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND37` writer - New Data 37"] +pub struct ND37_W<'a> { + w: &'a mut W, +} +impl<'a> ND37_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `ND38` reader - New Data 38"] +pub struct ND38_R(crate::FieldReader); +impl ND38_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND38_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND38_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND38` writer - New Data 38"] +pub struct ND38_W<'a> { + w: &'a mut W, +} +impl<'a> ND38_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ND39` reader - New Data 39"] +pub struct ND39_R(crate::FieldReader); +impl ND39_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND39_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND39_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND39` writer - New Data 39"] +pub struct ND39_W<'a> { + w: &'a mut W, +} +impl<'a> ND39_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `ND40` reader - New Data 40"] +pub struct ND40_R(crate::FieldReader); +impl ND40_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND40_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND40_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND40` writer - New Data 40"] +pub struct ND40_W<'a> { + w: &'a mut W, +} +impl<'a> ND40_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `ND41` reader - New Data 41"] +pub struct ND41_R(crate::FieldReader); +impl ND41_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND41_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND41_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND41` writer - New Data 41"] +pub struct ND41_W<'a> { + w: &'a mut W, +} +impl<'a> ND41_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `ND42` reader - New Data 42"] +pub struct ND42_R(crate::FieldReader); +impl ND42_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND42_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND42_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND42` writer - New Data 42"] +pub struct ND42_W<'a> { + w: &'a mut W, +} +impl<'a> ND42_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `ND43` reader - New Data 43"] +pub struct ND43_R(crate::FieldReader); +impl ND43_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND43_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND43_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND43` writer - New Data 43"] +pub struct ND43_W<'a> { + w: &'a mut W, +} +impl<'a> ND43_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `ND44` reader - New Data 44"] +pub struct ND44_R(crate::FieldReader); +impl ND44_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND44_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND44_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND44` writer - New Data 44"] +pub struct ND44_W<'a> { + w: &'a mut W, +} +impl<'a> ND44_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `ND45` reader - New Data 45"] +pub struct ND45_R(crate::FieldReader); +impl ND45_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND45_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND45_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND45` writer - New Data 45"] +pub struct ND45_W<'a> { + w: &'a mut W, +} +impl<'a> ND45_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `ND46` reader - New Data 46"] +pub struct ND46_R(crate::FieldReader); +impl ND46_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND46_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND46_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND46` writer - New Data 46"] +pub struct ND46_W<'a> { + w: &'a mut W, +} +impl<'a> ND46_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `ND47` reader - New Data 47"] +pub struct ND47_R(crate::FieldReader); +impl ND47_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND47_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND47_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND47` writer - New Data 47"] +pub struct ND47_W<'a> { + w: &'a mut W, +} +impl<'a> ND47_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `ND48` reader - New Data 48"] +pub struct ND48_R(crate::FieldReader); +impl ND48_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND48_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND48_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND48` writer - New Data 48"] +pub struct ND48_W<'a> { + w: &'a mut W, +} +impl<'a> ND48_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `ND49` reader - New Data 49"] +pub struct ND49_R(crate::FieldReader); +impl ND49_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND49_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND49_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND49` writer - New Data 49"] +pub struct ND49_W<'a> { + w: &'a mut W, +} +impl<'a> ND49_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `ND50` reader - New Data 50"] +pub struct ND50_R(crate::FieldReader); +impl ND50_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND50_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND50_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND50` writer - New Data 50"] +pub struct ND50_W<'a> { + w: &'a mut W, +} +impl<'a> ND50_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `ND51` reader - New Data 51"] +pub struct ND51_R(crate::FieldReader); +impl ND51_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND51_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND51_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND51` writer - New Data 51"] +pub struct ND51_W<'a> { + w: &'a mut W, +} +impl<'a> ND51_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `ND52` reader - New Data 52"] +pub struct ND52_R(crate::FieldReader); +impl ND52_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND52_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND52_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND52` writer - New Data 52"] +pub struct ND52_W<'a> { + w: &'a mut W, +} +impl<'a> ND52_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `ND53` reader - New Data 53"] +pub struct ND53_R(crate::FieldReader); +impl ND53_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND53_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND53_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND53` writer - New Data 53"] +pub struct ND53_W<'a> { + w: &'a mut W, +} +impl<'a> ND53_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `ND54` reader - New Data 54"] +pub struct ND54_R(crate::FieldReader); +impl ND54_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND54_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND54_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND54` writer - New Data 54"] +pub struct ND54_W<'a> { + w: &'a mut W, +} +impl<'a> ND54_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `ND55` reader - New Data 55"] +pub struct ND55_R(crate::FieldReader); +impl ND55_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND55_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND55_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND55` writer - New Data 55"] +pub struct ND55_W<'a> { + w: &'a mut W, +} +impl<'a> ND55_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `ND56` reader - New Data 56"] +pub struct ND56_R(crate::FieldReader); +impl ND56_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND56_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND56_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND56` writer - New Data 56"] +pub struct ND56_W<'a> { + w: &'a mut W, +} +impl<'a> ND56_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `ND57` reader - New Data 57"] +pub struct ND57_R(crate::FieldReader); +impl ND57_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND57_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND57_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND57` writer - New Data 57"] +pub struct ND57_W<'a> { + w: &'a mut W, +} +impl<'a> ND57_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `ND58` reader - New Data 58"] +pub struct ND58_R(crate::FieldReader); +impl ND58_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND58_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND58_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND58` writer - New Data 58"] +pub struct ND58_W<'a> { + w: &'a mut W, +} +impl<'a> ND58_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `ND59` reader - New Data 59"] +pub struct ND59_R(crate::FieldReader); +impl ND59_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND59_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND59_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND59` writer - New Data 59"] +pub struct ND59_W<'a> { + w: &'a mut W, +} +impl<'a> ND59_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +#[doc = "Field `ND60` reader - New Data 60"] +pub struct ND60_R(crate::FieldReader); +impl ND60_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND60_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND60_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND60` writer - New Data 60"] +pub struct ND60_W<'a> { + w: &'a mut W, +} +impl<'a> ND60_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Field `ND61` reader - New Data 61"] +pub struct ND61_R(crate::FieldReader); +impl ND61_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND61_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND61_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND61` writer - New Data 61"] +pub struct ND61_W<'a> { + w: &'a mut W, +} +impl<'a> ND61_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29); + self.w + } +} +#[doc = "Field `ND62` reader - New Data 62"] +pub struct ND62_R(crate::FieldReader); +impl ND62_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND62_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND62_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND62` writer - New Data 62"] +pub struct ND62_W<'a> { + w: &'a mut W, +} +impl<'a> ND62_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +#[doc = "Field `ND63` reader - New Data 63"] +pub struct ND63_R(crate::FieldReader); +impl ND63_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ND63_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ND63_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ND63` writer - New Data 63"] +pub struct ND63_W<'a> { + w: &'a mut W, +} +impl<'a> ND63_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bit 0 - New Data 32"] + #[inline(always)] + pub fn nd32(&self) -> ND32_R { + ND32_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - New Data 33"] + #[inline(always)] + pub fn nd33(&self) -> ND33_R { + ND33_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - New Data 34"] + #[inline(always)] + pub fn nd34(&self) -> ND34_R { + ND34_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - New Data 35"] + #[inline(always)] + pub fn nd35(&self) -> ND35_R { + ND35_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - New Data 36"] + #[inline(always)] + pub fn nd36(&self) -> ND36_R { + ND36_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - New Data 37"] + #[inline(always)] + pub fn nd37(&self) -> ND37_R { + ND37_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - New Data 38"] + #[inline(always)] + pub fn nd38(&self) -> ND38_R { + ND38_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - New Data 39"] + #[inline(always)] + pub fn nd39(&self) -> ND39_R { + ND39_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - New Data 40"] + #[inline(always)] + pub fn nd40(&self) -> ND40_R { + ND40_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - New Data 41"] + #[inline(always)] + pub fn nd41(&self) -> ND41_R { + ND41_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - New Data 42"] + #[inline(always)] + pub fn nd42(&self) -> ND42_R { + ND42_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - New Data 43"] + #[inline(always)] + pub fn nd43(&self) -> ND43_R { + ND43_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - New Data 44"] + #[inline(always)] + pub fn nd44(&self) -> ND44_R { + ND44_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - New Data 45"] + #[inline(always)] + pub fn nd45(&self) -> ND45_R { + ND45_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - New Data 46"] + #[inline(always)] + pub fn nd46(&self) -> ND46_R { + ND46_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - New Data 47"] + #[inline(always)] + pub fn nd47(&self) -> ND47_R { + ND47_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - New Data 48"] + #[inline(always)] + pub fn nd48(&self) -> ND48_R { + ND48_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - New Data 49"] + #[inline(always)] + pub fn nd49(&self) -> ND49_R { + ND49_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - New Data 50"] + #[inline(always)] + pub fn nd50(&self) -> ND50_R { + ND50_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - New Data 51"] + #[inline(always)] + pub fn nd51(&self) -> ND51_R { + ND51_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - New Data 52"] + #[inline(always)] + pub fn nd52(&self) -> ND52_R { + ND52_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - New Data 53"] + #[inline(always)] + pub fn nd53(&self) -> ND53_R { + ND53_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - New Data 54"] + #[inline(always)] + pub fn nd54(&self) -> ND54_R { + ND54_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - New Data 55"] + #[inline(always)] + pub fn nd55(&self) -> ND55_R { + ND55_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24 - New Data 56"] + #[inline(always)] + pub fn nd56(&self) -> ND56_R { + ND56_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - New Data 57"] + #[inline(always)] + pub fn nd57(&self) -> ND57_R { + ND57_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - New Data 58"] + #[inline(always)] + pub fn nd58(&self) -> ND58_R { + ND58_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - New Data 59"] + #[inline(always)] + pub fn nd59(&self) -> ND59_R { + ND59_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28 - New Data 60"] + #[inline(always)] + pub fn nd60(&self) -> ND60_R { + ND60_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - New Data 61"] + #[inline(always)] + pub fn nd61(&self) -> ND61_R { + ND61_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - New Data 62"] + #[inline(always)] + pub fn nd62(&self) -> ND62_R { + ND62_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 31 - New Data 63"] + #[inline(always)] + pub fn nd63(&self) -> ND63_R { + ND63_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - New Data 32"] + #[inline(always)] + pub fn nd32(&mut self) -> ND32_W { + ND32_W { w: self } + } + #[doc = "Bit 1 - New Data 33"] + #[inline(always)] + pub fn nd33(&mut self) -> ND33_W { + ND33_W { w: self } + } + #[doc = "Bit 2 - New Data 34"] + #[inline(always)] + pub fn nd34(&mut self) -> ND34_W { + ND34_W { w: self } + } + #[doc = "Bit 3 - New Data 35"] + #[inline(always)] + pub fn nd35(&mut self) -> ND35_W { + ND35_W { w: self } + } + #[doc = "Bit 4 - New Data 36"] + #[inline(always)] + pub fn nd36(&mut self) -> ND36_W { + ND36_W { w: self } + } + #[doc = "Bit 5 - New Data 37"] + #[inline(always)] + pub fn nd37(&mut self) -> ND37_W { + ND37_W { w: self } + } + #[doc = "Bit 6 - New Data 38"] + #[inline(always)] + pub fn nd38(&mut self) -> ND38_W { + ND38_W { w: self } + } + #[doc = "Bit 7 - New Data 39"] + #[inline(always)] + pub fn nd39(&mut self) -> ND39_W { + ND39_W { w: self } + } + #[doc = "Bit 8 - New Data 40"] + #[inline(always)] + pub fn nd40(&mut self) -> ND40_W { + ND40_W { w: self } + } + #[doc = "Bit 9 - New Data 41"] + #[inline(always)] + pub fn nd41(&mut self) -> ND41_W { + ND41_W { w: self } + } + #[doc = "Bit 10 - New Data 42"] + #[inline(always)] + pub fn nd42(&mut self) -> ND42_W { + ND42_W { w: self } + } + #[doc = "Bit 11 - New Data 43"] + #[inline(always)] + pub fn nd43(&mut self) -> ND43_W { + ND43_W { w: self } + } + #[doc = "Bit 12 - New Data 44"] + #[inline(always)] + pub fn nd44(&mut self) -> ND44_W { + ND44_W { w: self } + } + #[doc = "Bit 13 - New Data 45"] + #[inline(always)] + pub fn nd45(&mut self) -> ND45_W { + ND45_W { w: self } + } + #[doc = "Bit 14 - New Data 46"] + #[inline(always)] + pub fn nd46(&mut self) -> ND46_W { + ND46_W { w: self } + } + #[doc = "Bit 15 - New Data 47"] + #[inline(always)] + pub fn nd47(&mut self) -> ND47_W { + ND47_W { w: self } + } + #[doc = "Bit 16 - New Data 48"] + #[inline(always)] + pub fn nd48(&mut self) -> ND48_W { + ND48_W { w: self } + } + #[doc = "Bit 17 - New Data 49"] + #[inline(always)] + pub fn nd49(&mut self) -> ND49_W { + ND49_W { w: self } + } + #[doc = "Bit 18 - New Data 50"] + #[inline(always)] + pub fn nd50(&mut self) -> ND50_W { + ND50_W { w: self } + } + #[doc = "Bit 19 - New Data 51"] + #[inline(always)] + pub fn nd51(&mut self) -> ND51_W { + ND51_W { w: self } + } + #[doc = "Bit 20 - New Data 52"] + #[inline(always)] + pub fn nd52(&mut self) -> ND52_W { + ND52_W { w: self } + } + #[doc = "Bit 21 - New Data 53"] + #[inline(always)] + pub fn nd53(&mut self) -> ND53_W { + ND53_W { w: self } + } + #[doc = "Bit 22 - New Data 54"] + #[inline(always)] + pub fn nd54(&mut self) -> ND54_W { + ND54_W { w: self } + } + #[doc = "Bit 23 - New Data 55"] + #[inline(always)] + pub fn nd55(&mut self) -> ND55_W { + ND55_W { w: self } + } + #[doc = "Bit 24 - New Data 56"] + #[inline(always)] + pub fn nd56(&mut self) -> ND56_W { + ND56_W { w: self } + } + #[doc = "Bit 25 - New Data 57"] + #[inline(always)] + pub fn nd57(&mut self) -> ND57_W { + ND57_W { w: self } + } + #[doc = "Bit 26 - New Data 58"] + #[inline(always)] + pub fn nd58(&mut self) -> ND58_W { + ND58_W { w: self } + } + #[doc = "Bit 27 - New Data 59"] + #[inline(always)] + pub fn nd59(&mut self) -> ND59_W { + ND59_W { w: self } + } + #[doc = "Bit 28 - New Data 60"] + #[inline(always)] + pub fn nd60(&mut self) -> ND60_W { + ND60_W { w: self } + } + #[doc = "Bit 29 - New Data 61"] + #[inline(always)] + pub fn nd61(&mut self) -> ND61_W { + ND61_W { w: self } + } + #[doc = "Bit 30 - New Data 62"] + #[inline(always)] + pub fn nd62(&mut self) -> ND62_W { + ND62_W { w: self } + } + #[doc = "Bit 31 - New Data 63"] + #[inline(always)] + pub fn nd63(&mut self) -> ND63_W { + ND63_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "New Data 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ndat2](index.html) module"] +pub struct NDAT2_SPEC; +impl crate::RegisterSpec for NDAT2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ndat2::R](R) reader structure"] +impl crate::Readable for NDAT2_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ndat2::W](W) writer structure"] +impl crate::Writable for NDAT2_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets NDAT2 to value 0"] +impl crate::Resettable for NDAT2_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/can0/psr.rs b/pac/atsamc21n/src/can0/psr.rs new file mode 100644 index 000000000000..0b5f73b9413b --- /dev/null +++ b/pac/atsamc21n/src/can0/psr.rs @@ -0,0 +1,467 @@ +#[doc = "Register `PSR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Last Error Code\n\nValue on reset: 7"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum LEC_A { + #[doc = "0: No Error"] + NONE = 0, + #[doc = "1: Stuff Error"] + STUFF = 1, + #[doc = "2: Form Error"] + FORM = 2, + #[doc = "3: Ack Error"] + ACK = 3, + #[doc = "4: Bit1 Error"] + BIT1 = 4, + #[doc = "5: Bit0 Error"] + BIT0 = 5, + #[doc = "6: CRC Error"] + CRC = 6, + #[doc = "7: No Change"] + NC = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LEC_A) -> Self { + variant as _ + } +} +#[doc = "Field `LEC` reader - Last Error Code"] +pub struct LEC_R(crate::FieldReader); +impl LEC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LEC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> LEC_A { + match self.bits { + 0 => LEC_A::NONE, + 1 => LEC_A::STUFF, + 2 => LEC_A::FORM, + 3 => LEC_A::ACK, + 4 => LEC_A::BIT1, + 5 => LEC_A::BIT0, + 6 => LEC_A::CRC, + 7 => LEC_A::NC, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == LEC_A::NONE + } + #[doc = "Checks if the value of the field is `STUFF`"] + #[inline(always)] + pub fn is_stuff(&self) -> bool { + **self == LEC_A::STUFF + } + #[doc = "Checks if the value of the field is `FORM`"] + #[inline(always)] + pub fn is_form(&self) -> bool { + **self == LEC_A::FORM + } + #[doc = "Checks if the value of the field is `ACK`"] + #[inline(always)] + pub fn is_ack(&self) -> bool { + **self == LEC_A::ACK + } + #[doc = "Checks if the value of the field is `BIT1`"] + #[inline(always)] + pub fn is_bit1(&self) -> bool { + **self == LEC_A::BIT1 + } + #[doc = "Checks if the value of the field is `BIT0`"] + #[inline(always)] + pub fn is_bit0(&self) -> bool { + **self == LEC_A::BIT0 + } + #[doc = "Checks if the value of the field is `CRC`"] + #[inline(always)] + pub fn is_crc(&self) -> bool { + **self == LEC_A::CRC + } + #[doc = "Checks if the value of the field is `NC`"] + #[inline(always)] + pub fn is_nc(&self) -> bool { + **self == LEC_A::NC + } +} +impl core::ops::Deref for LEC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Activity\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum ACT_A { + #[doc = "0: Node is synchronizing on CAN communication"] + SYNC = 0, + #[doc = "1: Node is neither receiver nor transmitter"] + IDLE = 1, + #[doc = "2: Node is operating as receiver"] + RX = 2, + #[doc = "3: Node is operating as transmitter"] + TX = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: ACT_A) -> Self { + variant as _ + } +} +#[doc = "Field `ACT` reader - Activity"] +pub struct ACT_R(crate::FieldReader); +impl ACT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ACT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ACT_A { + match self.bits { + 0 => ACT_A::SYNC, + 1 => ACT_A::IDLE, + 2 => ACT_A::RX, + 3 => ACT_A::TX, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `SYNC`"] + #[inline(always)] + pub fn is_sync(&self) -> bool { + **self == ACT_A::SYNC + } + #[doc = "Checks if the value of the field is `IDLE`"] + #[inline(always)] + pub fn is_idle(&self) -> bool { + **self == ACT_A::IDLE + } + #[doc = "Checks if the value of the field is `RX`"] + #[inline(always)] + pub fn is_rx(&self) -> bool { + **self == ACT_A::RX + } + #[doc = "Checks if the value of the field is `TX`"] + #[inline(always)] + pub fn is_tx(&self) -> bool { + **self == ACT_A::TX + } +} +impl core::ops::Deref for ACT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EP` reader - Error Passive"] +pub struct EP_R(crate::FieldReader); +impl EP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EW` reader - Warning Status"] +pub struct EW_R(crate::FieldReader); +impl EW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BO` reader - Bus_Off Status"] +pub struct BO_R(crate::FieldReader); +impl BO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Data Phase Last Error Code\n\nValue on reset: 7"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DLEC_A { + #[doc = "0: No Error"] + NONE = 0, + #[doc = "1: Stuff Error"] + STUFF = 1, + #[doc = "2: Form Error"] + FORM = 2, + #[doc = "3: Ack Error"] + ACK = 3, + #[doc = "4: Bit1 Error"] + BIT1 = 4, + #[doc = "5: Bit0 Error"] + BIT0 = 5, + #[doc = "6: CRC Error"] + CRC = 6, + #[doc = "7: No Change"] + NC = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DLEC_A) -> Self { + variant as _ + } +} +#[doc = "Field `DLEC` reader - Data Phase Last Error Code"] +pub struct DLEC_R(crate::FieldReader); +impl DLEC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DLEC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DLEC_A { + match self.bits { + 0 => DLEC_A::NONE, + 1 => DLEC_A::STUFF, + 2 => DLEC_A::FORM, + 3 => DLEC_A::ACK, + 4 => DLEC_A::BIT1, + 5 => DLEC_A::BIT0, + 6 => DLEC_A::CRC, + 7 => DLEC_A::NC, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == DLEC_A::NONE + } + #[doc = "Checks if the value of the field is `STUFF`"] + #[inline(always)] + pub fn is_stuff(&self) -> bool { + **self == DLEC_A::STUFF + } + #[doc = "Checks if the value of the field is `FORM`"] + #[inline(always)] + pub fn is_form(&self) -> bool { + **self == DLEC_A::FORM + } + #[doc = "Checks if the value of the field is `ACK`"] + #[inline(always)] + pub fn is_ack(&self) -> bool { + **self == DLEC_A::ACK + } + #[doc = "Checks if the value of the field is `BIT1`"] + #[inline(always)] + pub fn is_bit1(&self) -> bool { + **self == DLEC_A::BIT1 + } + #[doc = "Checks if the value of the field is `BIT0`"] + #[inline(always)] + pub fn is_bit0(&self) -> bool { + **self == DLEC_A::BIT0 + } + #[doc = "Checks if the value of the field is `CRC`"] + #[inline(always)] + pub fn is_crc(&self) -> bool { + **self == DLEC_A::CRC + } + #[doc = "Checks if the value of the field is `NC`"] + #[inline(always)] + pub fn is_nc(&self) -> bool { + **self == DLEC_A::NC + } +} +impl core::ops::Deref for DLEC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESI` reader - ESI flag of last received CAN FD Message"] +pub struct RESI_R(crate::FieldReader); +impl RESI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RBRS` reader - BRS flag of last received CAN FD Message"] +pub struct RBRS_R(crate::FieldReader); +impl RBRS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RBRS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RBRS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RFDF` reader - Received a CAN FD Message"] +pub struct RFDF_R(crate::FieldReader); +impl RFDF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RFDF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RFDF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PXE` reader - Protocol Exception Event"] +pub struct PXE_R(crate::FieldReader); +impl PXE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PXE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PXE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TDCV` reader - Transmitter Delay Compensation Value"] +pub struct TDCV_R(crate::FieldReader); +impl TDCV_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TDCV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TDCV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:2 - Last Error Code"] + #[inline(always)] + pub fn lec(&self) -> LEC_R { + LEC_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bits 3:4 - Activity"] + #[inline(always)] + pub fn act(&self) -> ACT_R { + ACT_R::new(((self.bits >> 3) & 0x03) as u8) + } + #[doc = "Bit 5 - Error Passive"] + #[inline(always)] + pub fn ep(&self) -> EP_R { + EP_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Warning Status"] + #[inline(always)] + pub fn ew(&self) -> EW_R { + EW_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Bus_Off Status"] + #[inline(always)] + pub fn bo(&self) -> BO_R { + BO_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Data Phase Last Error Code"] + #[inline(always)] + pub fn dlec(&self) -> DLEC_R { + DLEC_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 11 - ESI flag of last received CAN FD Message"] + #[inline(always)] + pub fn resi(&self) -> RESI_R { + RESI_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - BRS flag of last received CAN FD Message"] + #[inline(always)] + pub fn rbrs(&self) -> RBRS_R { + RBRS_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Received a CAN FD Message"] + #[inline(always)] + pub fn rfdf(&self) -> RFDF_R { + RFDF_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Protocol Exception Event"] + #[inline(always)] + pub fn pxe(&self) -> PXE_R { + PXE_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bits 16:22 - Transmitter Delay Compensation Value"] + #[inline(always)] + pub fn tdcv(&self) -> TDCV_R { + TDCV_R::new(((self.bits >> 16) & 0x7f) as u8) + } +} +#[doc = "Protocol Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [psr](index.html) module"] +pub struct PSR_SPEC; +impl crate::RegisterSpec for PSR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [psr::R](R) reader structure"] +impl crate::Readable for PSR_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PSR to value 0x0707"] +impl crate::Resettable for PSR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0707 + } +} diff --git a/pac/atsamc21n/src/can0/rwd.rs b/pac/atsamc21n/src/can0/rwd.rs new file mode 100644 index 000000000000..88f5b86a33f2 --- /dev/null +++ b/pac/atsamc21n/src/can0/rwd.rs @@ -0,0 +1,140 @@ +#[doc = "Register `RWD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RWD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WDC` reader - Watchdog Configuration"] +pub struct WDC_R(crate::FieldReader); +impl WDC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WDC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WDC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WDC` writer - Watchdog Configuration"] +pub struct WDC_W<'a> { + w: &'a mut W, +} +impl<'a> WDC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +#[doc = "Field `WDV` reader - Watchdog Value"] +pub struct WDV_R(crate::FieldReader); +impl WDV_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WDV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WDV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WDV` writer - Watchdog Value"] +pub struct WDV_W<'a> { + w: &'a mut W, +} +impl<'a> WDV_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Watchdog Configuration"] + #[inline(always)] + pub fn wdc(&self) -> WDC_R { + WDC_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Watchdog Value"] + #[inline(always)] + pub fn wdv(&self) -> WDV_R { + WDV_R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Watchdog Configuration"] + #[inline(always)] + pub fn wdc(&mut self) -> WDC_W { + WDC_W { w: self } + } + #[doc = "Bits 8:15 - Watchdog Value"] + #[inline(always)] + pub fn wdv(&mut self) -> WDV_W { + WDV_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "RAM Watchdog\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rwd](index.html) module"] +pub struct RWD_SPEC; +impl crate::RegisterSpec for RWD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rwd::R](R) reader structure"] +impl crate::Readable for RWD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rwd::W](W) writer structure"] +impl crate::Writable for RWD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RWD to value 0"] +impl crate::Resettable for RWD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/can0/rxbc.rs b/pac/atsamc21n/src/can0/rxbc.rs new file mode 100644 index 000000000000..d320ea61f4c2 --- /dev/null +++ b/pac/atsamc21n/src/can0/rxbc.rs @@ -0,0 +1,103 @@ +#[doc = "Register `RXBC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RXBC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RBSA` reader - Rx Buffer Start Address"] +pub struct RBSA_R(crate::FieldReader); +impl RBSA_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + RBSA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RBSA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RBSA` writer - Rx Buffer Start Address"] +pub struct RBSA_W<'a> { + w: &'a mut W, +} +impl<'a> RBSA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Rx Buffer Start Address"] + #[inline(always)] + pub fn rbsa(&self) -> RBSA_R { + RBSA_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Rx Buffer Start Address"] + #[inline(always)] + pub fn rbsa(&mut self) -> RBSA_W { + RBSA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Rx Buffer Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxbc](index.html) module"] +pub struct RXBC_SPEC; +impl crate::RegisterSpec for RXBC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rxbc::R](R) reader structure"] +impl crate::Readable for RXBC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rxbc::W](W) writer structure"] +impl crate::Writable for RXBC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RXBC to value 0"] +impl crate::Resettable for RXBC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/can0/rxesc.rs b/pac/atsamc21n/src/can0/rxesc.rs new file mode 100644 index 000000000000..b0a972eaf1f0 --- /dev/null +++ b/pac/atsamc21n/src/can0/rxesc.rs @@ -0,0 +1,558 @@ +#[doc = "Register `RXESC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RXESC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Rx FIFO 0 Data Field Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum F0DS_A { + #[doc = "0: 8 byte data field"] + DATA8 = 0, + #[doc = "1: 12 byte data field"] + DATA12 = 1, + #[doc = "2: 16 byte data field"] + DATA16 = 2, + #[doc = "3: 20 byte data field"] + DATA20 = 3, + #[doc = "4: 24 byte data field"] + DATA24 = 4, + #[doc = "5: 32 byte data field"] + DATA32 = 5, + #[doc = "6: 48 byte data field"] + DATA48 = 6, + #[doc = "7: 64 byte data field"] + DATA64 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: F0DS_A) -> Self { + variant as _ + } +} +#[doc = "Field `F0DS` reader - Rx FIFO 0 Data Field Size"] +pub struct F0DS_R(crate::FieldReader); +impl F0DS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + F0DS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> F0DS_A { + match self.bits { + 0 => F0DS_A::DATA8, + 1 => F0DS_A::DATA12, + 2 => F0DS_A::DATA16, + 3 => F0DS_A::DATA20, + 4 => F0DS_A::DATA24, + 5 => F0DS_A::DATA32, + 6 => F0DS_A::DATA48, + 7 => F0DS_A::DATA64, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DATA8`"] + #[inline(always)] + pub fn is_data8(&self) -> bool { + **self == F0DS_A::DATA8 + } + #[doc = "Checks if the value of the field is `DATA12`"] + #[inline(always)] + pub fn is_data12(&self) -> bool { + **self == F0DS_A::DATA12 + } + #[doc = "Checks if the value of the field is `DATA16`"] + #[inline(always)] + pub fn is_data16(&self) -> bool { + **self == F0DS_A::DATA16 + } + #[doc = "Checks if the value of the field is `DATA20`"] + #[inline(always)] + pub fn is_data20(&self) -> bool { + **self == F0DS_A::DATA20 + } + #[doc = "Checks if the value of the field is `DATA24`"] + #[inline(always)] + pub fn is_data24(&self) -> bool { + **self == F0DS_A::DATA24 + } + #[doc = "Checks if the value of the field is `DATA32`"] + #[inline(always)] + pub fn is_data32(&self) -> bool { + **self == F0DS_A::DATA32 + } + #[doc = "Checks if the value of the field is `DATA48`"] + #[inline(always)] + pub fn is_data48(&self) -> bool { + **self == F0DS_A::DATA48 + } + #[doc = "Checks if the value of the field is `DATA64`"] + #[inline(always)] + pub fn is_data64(&self) -> bool { + **self == F0DS_A::DATA64 + } +} +impl core::ops::Deref for F0DS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `F0DS` writer - Rx FIFO 0 Data Field Size"] +pub struct F0DS_W<'a> { + w: &'a mut W, +} +impl<'a> F0DS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: F0DS_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "8 byte data field"] + #[inline(always)] + pub fn data8(self) -> &'a mut W { + self.variant(F0DS_A::DATA8) + } + #[doc = "12 byte data field"] + #[inline(always)] + pub fn data12(self) -> &'a mut W { + self.variant(F0DS_A::DATA12) + } + #[doc = "16 byte data field"] + #[inline(always)] + pub fn data16(self) -> &'a mut W { + self.variant(F0DS_A::DATA16) + } + #[doc = "20 byte data field"] + #[inline(always)] + pub fn data20(self) -> &'a mut W { + self.variant(F0DS_A::DATA20) + } + #[doc = "24 byte data field"] + #[inline(always)] + pub fn data24(self) -> &'a mut W { + self.variant(F0DS_A::DATA24) + } + #[doc = "32 byte data field"] + #[inline(always)] + pub fn data32(self) -> &'a mut W { + self.variant(F0DS_A::DATA32) + } + #[doc = "48 byte data field"] + #[inline(always)] + pub fn data48(self) -> &'a mut W { + self.variant(F0DS_A::DATA48) + } + #[doc = "64 byte data field"] + #[inline(always)] + pub fn data64(self) -> &'a mut W { + self.variant(F0DS_A::DATA64) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Rx FIFO 1 Data Field Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum F1DS_A { + #[doc = "0: 8 byte data field"] + DATA8 = 0, + #[doc = "1: 12 byte data field"] + DATA12 = 1, + #[doc = "2: 16 byte data field"] + DATA16 = 2, + #[doc = "3: 20 byte data field"] + DATA20 = 3, + #[doc = "4: 24 byte data field"] + DATA24 = 4, + #[doc = "5: 32 byte data field"] + DATA32 = 5, + #[doc = "6: 48 byte data field"] + DATA48 = 6, + #[doc = "7: 64 byte data field"] + DATA64 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: F1DS_A) -> Self { + variant as _ + } +} +#[doc = "Field `F1DS` reader - Rx FIFO 1 Data Field Size"] +pub struct F1DS_R(crate::FieldReader); +impl F1DS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + F1DS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> F1DS_A { + match self.bits { + 0 => F1DS_A::DATA8, + 1 => F1DS_A::DATA12, + 2 => F1DS_A::DATA16, + 3 => F1DS_A::DATA20, + 4 => F1DS_A::DATA24, + 5 => F1DS_A::DATA32, + 6 => F1DS_A::DATA48, + 7 => F1DS_A::DATA64, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DATA8`"] + #[inline(always)] + pub fn is_data8(&self) -> bool { + **self == F1DS_A::DATA8 + } + #[doc = "Checks if the value of the field is `DATA12`"] + #[inline(always)] + pub fn is_data12(&self) -> bool { + **self == F1DS_A::DATA12 + } + #[doc = "Checks if the value of the field is `DATA16`"] + #[inline(always)] + pub fn is_data16(&self) -> bool { + **self == F1DS_A::DATA16 + } + #[doc = "Checks if the value of the field is `DATA20`"] + #[inline(always)] + pub fn is_data20(&self) -> bool { + **self == F1DS_A::DATA20 + } + #[doc = "Checks if the value of the field is `DATA24`"] + #[inline(always)] + pub fn is_data24(&self) -> bool { + **self == F1DS_A::DATA24 + } + #[doc = "Checks if the value of the field is `DATA32`"] + #[inline(always)] + pub fn is_data32(&self) -> bool { + **self == F1DS_A::DATA32 + } + #[doc = "Checks if the value of the field is `DATA48`"] + #[inline(always)] + pub fn is_data48(&self) -> bool { + **self == F1DS_A::DATA48 + } + #[doc = "Checks if the value of the field is `DATA64`"] + #[inline(always)] + pub fn is_data64(&self) -> bool { + **self == F1DS_A::DATA64 + } +} +impl core::ops::Deref for F1DS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `F1DS` writer - Rx FIFO 1 Data Field Size"] +pub struct F1DS_W<'a> { + w: &'a mut W, +} +impl<'a> F1DS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: F1DS_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "8 byte data field"] + #[inline(always)] + pub fn data8(self) -> &'a mut W { + self.variant(F1DS_A::DATA8) + } + #[doc = "12 byte data field"] + #[inline(always)] + pub fn data12(self) -> &'a mut W { + self.variant(F1DS_A::DATA12) + } + #[doc = "16 byte data field"] + #[inline(always)] + pub fn data16(self) -> &'a mut W { + self.variant(F1DS_A::DATA16) + } + #[doc = "20 byte data field"] + #[inline(always)] + pub fn data20(self) -> &'a mut W { + self.variant(F1DS_A::DATA20) + } + #[doc = "24 byte data field"] + #[inline(always)] + pub fn data24(self) -> &'a mut W { + self.variant(F1DS_A::DATA24) + } + #[doc = "32 byte data field"] + #[inline(always)] + pub fn data32(self) -> &'a mut W { + self.variant(F1DS_A::DATA32) + } + #[doc = "48 byte data field"] + #[inline(always)] + pub fn data48(self) -> &'a mut W { + self.variant(F1DS_A::DATA48) + } + #[doc = "64 byte data field"] + #[inline(always)] + pub fn data64(self) -> &'a mut W { + self.variant(F1DS_A::DATA64) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 4)) | ((value as u32 & 0x07) << 4); + self.w + } +} +#[doc = "Rx Buffer Data Field Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum RBDS_A { + #[doc = "0: 8 byte data field"] + DATA8 = 0, + #[doc = "1: 12 byte data field"] + DATA12 = 1, + #[doc = "2: 16 byte data field"] + DATA16 = 2, + #[doc = "3: 20 byte data field"] + DATA20 = 3, + #[doc = "4: 24 byte data field"] + DATA24 = 4, + #[doc = "5: 32 byte data field"] + DATA32 = 5, + #[doc = "6: 48 byte data field"] + DATA48 = 6, + #[doc = "7: 64 byte data field"] + DATA64 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RBDS_A) -> Self { + variant as _ + } +} +#[doc = "Field `RBDS` reader - Rx Buffer Data Field Size"] +pub struct RBDS_R(crate::FieldReader); +impl RBDS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RBDS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RBDS_A { + match self.bits { + 0 => RBDS_A::DATA8, + 1 => RBDS_A::DATA12, + 2 => RBDS_A::DATA16, + 3 => RBDS_A::DATA20, + 4 => RBDS_A::DATA24, + 5 => RBDS_A::DATA32, + 6 => RBDS_A::DATA48, + 7 => RBDS_A::DATA64, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DATA8`"] + #[inline(always)] + pub fn is_data8(&self) -> bool { + **self == RBDS_A::DATA8 + } + #[doc = "Checks if the value of the field is `DATA12`"] + #[inline(always)] + pub fn is_data12(&self) -> bool { + **self == RBDS_A::DATA12 + } + #[doc = "Checks if the value of the field is `DATA16`"] + #[inline(always)] + pub fn is_data16(&self) -> bool { + **self == RBDS_A::DATA16 + } + #[doc = "Checks if the value of the field is `DATA20`"] + #[inline(always)] + pub fn is_data20(&self) -> bool { + **self == RBDS_A::DATA20 + } + #[doc = "Checks if the value of the field is `DATA24`"] + #[inline(always)] + pub fn is_data24(&self) -> bool { + **self == RBDS_A::DATA24 + } + #[doc = "Checks if the value of the field is `DATA32`"] + #[inline(always)] + pub fn is_data32(&self) -> bool { + **self == RBDS_A::DATA32 + } + #[doc = "Checks if the value of the field is `DATA48`"] + #[inline(always)] + pub fn is_data48(&self) -> bool { + **self == RBDS_A::DATA48 + } + #[doc = "Checks if the value of the field is `DATA64`"] + #[inline(always)] + pub fn is_data64(&self) -> bool { + **self == RBDS_A::DATA64 + } +} +impl core::ops::Deref for RBDS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RBDS` writer - Rx Buffer Data Field Size"] +pub struct RBDS_W<'a> { + w: &'a mut W, +} +impl<'a> RBDS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RBDS_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "8 byte data field"] + #[inline(always)] + pub fn data8(self) -> &'a mut W { + self.variant(RBDS_A::DATA8) + } + #[doc = "12 byte data field"] + #[inline(always)] + pub fn data12(self) -> &'a mut W { + self.variant(RBDS_A::DATA12) + } + #[doc = "16 byte data field"] + #[inline(always)] + pub fn data16(self) -> &'a mut W { + self.variant(RBDS_A::DATA16) + } + #[doc = "20 byte data field"] + #[inline(always)] + pub fn data20(self) -> &'a mut W { + self.variant(RBDS_A::DATA20) + } + #[doc = "24 byte data field"] + #[inline(always)] + pub fn data24(self) -> &'a mut W { + self.variant(RBDS_A::DATA24) + } + #[doc = "32 byte data field"] + #[inline(always)] + pub fn data32(self) -> &'a mut W { + self.variant(RBDS_A::DATA32) + } + #[doc = "48 byte data field"] + #[inline(always)] + pub fn data48(self) -> &'a mut W { + self.variant(RBDS_A::DATA48) + } + #[doc = "64 byte data field"] + #[inline(always)] + pub fn data64(self) -> &'a mut W { + self.variant(RBDS_A::DATA64) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Rx FIFO 0 Data Field Size"] + #[inline(always)] + pub fn f0ds(&self) -> F0DS_R { + F0DS_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bits 4:6 - Rx FIFO 1 Data Field Size"] + #[inline(always)] + pub fn f1ds(&self) -> F1DS_R { + F1DS_R::new(((self.bits >> 4) & 0x07) as u8) + } + #[doc = "Bits 8:10 - Rx Buffer Data Field Size"] + #[inline(always)] + pub fn rbds(&self) -> RBDS_R { + RBDS_R::new(((self.bits >> 8) & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Rx FIFO 0 Data Field Size"] + #[inline(always)] + pub fn f0ds(&mut self) -> F0DS_W { + F0DS_W { w: self } + } + #[doc = "Bits 4:6 - Rx FIFO 1 Data Field Size"] + #[inline(always)] + pub fn f1ds(&mut self) -> F1DS_W { + F1DS_W { w: self } + } + #[doc = "Bits 8:10 - Rx Buffer Data Field Size"] + #[inline(always)] + pub fn rbds(&mut self) -> RBDS_W { + RBDS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Rx Buffer / FIFO Element Size Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxesc](index.html) module"] +pub struct RXESC_SPEC; +impl crate::RegisterSpec for RXESC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rxesc::R](R) reader structure"] +impl crate::Readable for RXESC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rxesc::W](W) writer structure"] +impl crate::Writable for RXESC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RXESC to value 0"] +impl crate::Resettable for RXESC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/can0/rxf0a.rs b/pac/atsamc21n/src/can0/rxf0a.rs new file mode 100644 index 000000000000..568144edf95d --- /dev/null +++ b/pac/atsamc21n/src/can0/rxf0a.rs @@ -0,0 +1,103 @@ +#[doc = "Register `RXF0A` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RXF0A` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `F0AI` reader - Rx FIFO 0 Acknowledge Index"] +pub struct F0AI_R(crate::FieldReader); +impl F0AI_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + F0AI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for F0AI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `F0AI` writer - Rx FIFO 0 Acknowledge Index"] +pub struct F0AI_W<'a> { + w: &'a mut W, +} +impl<'a> F0AI_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Rx FIFO 0 Acknowledge Index"] + #[inline(always)] + pub fn f0ai(&self) -> F0AI_R { + F0AI_R::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - Rx FIFO 0 Acknowledge Index"] + #[inline(always)] + pub fn f0ai(&mut self) -> F0AI_W { + F0AI_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Rx FIFO 0 Acknowledge\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxf0a](index.html) module"] +pub struct RXF0A_SPEC; +impl crate::RegisterSpec for RXF0A_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rxf0a::R](R) reader structure"] +impl crate::Readable for RXF0A_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rxf0a::W](W) writer structure"] +impl crate::Writable for RXF0A_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RXF0A to value 0"] +impl crate::Resettable for RXF0A_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/can0/rxf0c.rs b/pac/atsamc21n/src/can0/rxf0c.rs new file mode 100644 index 000000000000..a1e1def5881a --- /dev/null +++ b/pac/atsamc21n/src/can0/rxf0c.rs @@ -0,0 +1,224 @@ +#[doc = "Register `RXF0C` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RXF0C` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `F0SA` reader - Rx FIFO 0 Start Address"] +pub struct F0SA_R(crate::FieldReader); +impl F0SA_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + F0SA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for F0SA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `F0SA` writer - Rx FIFO 0 Start Address"] +pub struct F0SA_W<'a> { + w: &'a mut W, +} +impl<'a> F0SA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +#[doc = "Field `F0S` reader - Rx FIFO 0 Size"] +pub struct F0S_R(crate::FieldReader); +impl F0S_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + F0S_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for F0S_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `F0S` writer - Rx FIFO 0 Size"] +pub struct F0S_W<'a> { + w: &'a mut W, +} +impl<'a> F0S_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x7f << 16)) | ((value as u32 & 0x7f) << 16); + self.w + } +} +#[doc = "Field `F0WM` reader - Rx FIFO 0 Watermark"] +pub struct F0WM_R(crate::FieldReader); +impl F0WM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + F0WM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for F0WM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `F0WM` writer - Rx FIFO 0 Watermark"] +pub struct F0WM_W<'a> { + w: &'a mut W, +} +impl<'a> F0WM_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x7f << 24)) | ((value as u32 & 0x7f) << 24); + self.w + } +} +#[doc = "Field `F0OM` reader - FIFO 0 Operation Mode"] +pub struct F0OM_R(crate::FieldReader); +impl F0OM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + F0OM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for F0OM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `F0OM` writer - FIFO 0 Operation Mode"] +pub struct F0OM_W<'a> { + w: &'a mut W, +} +impl<'a> F0OM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Rx FIFO 0 Start Address"] + #[inline(always)] + pub fn f0sa(&self) -> F0SA_R { + F0SA_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:22 - Rx FIFO 0 Size"] + #[inline(always)] + pub fn f0s(&self) -> F0S_R { + F0S_R::new(((self.bits >> 16) & 0x7f) as u8) + } + #[doc = "Bits 24:30 - Rx FIFO 0 Watermark"] + #[inline(always)] + pub fn f0wm(&self) -> F0WM_R { + F0WM_R::new(((self.bits >> 24) & 0x7f) as u8) + } + #[doc = "Bit 31 - FIFO 0 Operation Mode"] + #[inline(always)] + pub fn f0om(&self) -> F0OM_R { + F0OM_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Rx FIFO 0 Start Address"] + #[inline(always)] + pub fn f0sa(&mut self) -> F0SA_W { + F0SA_W { w: self } + } + #[doc = "Bits 16:22 - Rx FIFO 0 Size"] + #[inline(always)] + pub fn f0s(&mut self) -> F0S_W { + F0S_W { w: self } + } + #[doc = "Bits 24:30 - Rx FIFO 0 Watermark"] + #[inline(always)] + pub fn f0wm(&mut self) -> F0WM_W { + F0WM_W { w: self } + } + #[doc = "Bit 31 - FIFO 0 Operation Mode"] + #[inline(always)] + pub fn f0om(&mut self) -> F0OM_W { + F0OM_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Rx FIFO 0 Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxf0c](index.html) module"] +pub struct RXF0C_SPEC; +impl crate::RegisterSpec for RXF0C_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rxf0c::R](R) reader structure"] +impl crate::Readable for RXF0C_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rxf0c::W](W) writer structure"] +impl crate::Writable for RXF0C_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RXF0C to value 0"] +impl crate::Resettable for RXF0C_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/can0/rxf0s.rs b/pac/atsamc21n/src/can0/rxf0s.rs new file mode 100644 index 000000000000..c26ef5fed347 --- /dev/null +++ b/pac/atsamc21n/src/can0/rxf0s.rs @@ -0,0 +1,133 @@ +#[doc = "Register `RXF0S` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `F0FL` reader - Rx FIFO 0 Fill Level"] +pub struct F0FL_R(crate::FieldReader); +impl F0FL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + F0FL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for F0FL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `F0GI` reader - Rx FIFO 0 Get Index"] +pub struct F0GI_R(crate::FieldReader); +impl F0GI_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + F0GI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for F0GI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `F0PI` reader - Rx FIFO 0 Put Index"] +pub struct F0PI_R(crate::FieldReader); +impl F0PI_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + F0PI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for F0PI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `F0F` reader - Rx FIFO 0 Full"] +pub struct F0F_R(crate::FieldReader); +impl F0F_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + F0F_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for F0F_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF0L` reader - Rx FIFO 0 Message Lost"] +pub struct RF0L_R(crate::FieldReader); +impl RF0L_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF0L_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF0L_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:6 - Rx FIFO 0 Fill Level"] + #[inline(always)] + pub fn f0fl(&self) -> F0FL_R { + F0FL_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bits 8:13 - Rx FIFO 0 Get Index"] + #[inline(always)] + pub fn f0gi(&self) -> F0GI_R { + F0GI_R::new(((self.bits >> 8) & 0x3f) as u8) + } + #[doc = "Bits 16:21 - Rx FIFO 0 Put Index"] + #[inline(always)] + pub fn f0pi(&self) -> F0PI_R { + F0PI_R::new(((self.bits >> 16) & 0x3f) as u8) + } + #[doc = "Bit 24 - Rx FIFO 0 Full"] + #[inline(always)] + pub fn f0f(&self) -> F0F_R { + F0F_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Rx FIFO 0 Message Lost"] + #[inline(always)] + pub fn rf0l(&self) -> RF0L_R { + RF0L_R::new(((self.bits >> 25) & 0x01) != 0) + } +} +#[doc = "Rx FIFO 0 Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxf0s](index.html) module"] +pub struct RXF0S_SPEC; +impl crate::RegisterSpec for RXF0S_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rxf0s::R](R) reader structure"] +impl crate::Readable for RXF0S_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets RXF0S to value 0"] +impl crate::Resettable for RXF0S_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/can0/rxf1a.rs b/pac/atsamc21n/src/can0/rxf1a.rs new file mode 100644 index 000000000000..56b074f7f444 --- /dev/null +++ b/pac/atsamc21n/src/can0/rxf1a.rs @@ -0,0 +1,103 @@ +#[doc = "Register `RXF1A` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RXF1A` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `F1AI` reader - Rx FIFO 1 Acknowledge Index"] +pub struct F1AI_R(crate::FieldReader); +impl F1AI_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + F1AI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for F1AI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `F1AI` writer - Rx FIFO 1 Acknowledge Index"] +pub struct F1AI_W<'a> { + w: &'a mut W, +} +impl<'a> F1AI_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Rx FIFO 1 Acknowledge Index"] + #[inline(always)] + pub fn f1ai(&self) -> F1AI_R { + F1AI_R::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - Rx FIFO 1 Acknowledge Index"] + #[inline(always)] + pub fn f1ai(&mut self) -> F1AI_W { + F1AI_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Rx FIFO 1 Acknowledge\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxf1a](index.html) module"] +pub struct RXF1A_SPEC; +impl crate::RegisterSpec for RXF1A_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rxf1a::R](R) reader structure"] +impl crate::Readable for RXF1A_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rxf1a::W](W) writer structure"] +impl crate::Writable for RXF1A_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RXF1A to value 0"] +impl crate::Resettable for RXF1A_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/can0/rxf1c.rs b/pac/atsamc21n/src/can0/rxf1c.rs new file mode 100644 index 000000000000..c9e23925c0c8 --- /dev/null +++ b/pac/atsamc21n/src/can0/rxf1c.rs @@ -0,0 +1,224 @@ +#[doc = "Register `RXF1C` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RXF1C` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `F1SA` reader - Rx FIFO 1 Start Address"] +pub struct F1SA_R(crate::FieldReader); +impl F1SA_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + F1SA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for F1SA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `F1SA` writer - Rx FIFO 1 Start Address"] +pub struct F1SA_W<'a> { + w: &'a mut W, +} +impl<'a> F1SA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +#[doc = "Field `F1S` reader - Rx FIFO 1 Size"] +pub struct F1S_R(crate::FieldReader); +impl F1S_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + F1S_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for F1S_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `F1S` writer - Rx FIFO 1 Size"] +pub struct F1S_W<'a> { + w: &'a mut W, +} +impl<'a> F1S_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x7f << 16)) | ((value as u32 & 0x7f) << 16); + self.w + } +} +#[doc = "Field `F1WM` reader - Rx FIFO 1 Watermark"] +pub struct F1WM_R(crate::FieldReader); +impl F1WM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + F1WM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for F1WM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `F1WM` writer - Rx FIFO 1 Watermark"] +pub struct F1WM_W<'a> { + w: &'a mut W, +} +impl<'a> F1WM_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x7f << 24)) | ((value as u32 & 0x7f) << 24); + self.w + } +} +#[doc = "Field `F1OM` reader - FIFO 1 Operation Mode"] +pub struct F1OM_R(crate::FieldReader); +impl F1OM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + F1OM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for F1OM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `F1OM` writer - FIFO 1 Operation Mode"] +pub struct F1OM_W<'a> { + w: &'a mut W, +} +impl<'a> F1OM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Rx FIFO 1 Start Address"] + #[inline(always)] + pub fn f1sa(&self) -> F1SA_R { + F1SA_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:22 - Rx FIFO 1 Size"] + #[inline(always)] + pub fn f1s(&self) -> F1S_R { + F1S_R::new(((self.bits >> 16) & 0x7f) as u8) + } + #[doc = "Bits 24:30 - Rx FIFO 1 Watermark"] + #[inline(always)] + pub fn f1wm(&self) -> F1WM_R { + F1WM_R::new(((self.bits >> 24) & 0x7f) as u8) + } + #[doc = "Bit 31 - FIFO 1 Operation Mode"] + #[inline(always)] + pub fn f1om(&self) -> F1OM_R { + F1OM_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Rx FIFO 1 Start Address"] + #[inline(always)] + pub fn f1sa(&mut self) -> F1SA_W { + F1SA_W { w: self } + } + #[doc = "Bits 16:22 - Rx FIFO 1 Size"] + #[inline(always)] + pub fn f1s(&mut self) -> F1S_W { + F1S_W { w: self } + } + #[doc = "Bits 24:30 - Rx FIFO 1 Watermark"] + #[inline(always)] + pub fn f1wm(&mut self) -> F1WM_W { + F1WM_W { w: self } + } + #[doc = "Bit 31 - FIFO 1 Operation Mode"] + #[inline(always)] + pub fn f1om(&mut self) -> F1OM_W { + F1OM_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Rx FIFO 1 Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxf1c](index.html) module"] +pub struct RXF1C_SPEC; +impl crate::RegisterSpec for RXF1C_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rxf1c::R](R) reader structure"] +impl crate::Readable for RXF1C_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rxf1c::W](W) writer structure"] +impl crate::Writable for RXF1C_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RXF1C to value 0"] +impl crate::Resettable for RXF1C_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/can0/rxf1s.rs b/pac/atsamc21n/src/can0/rxf1s.rs new file mode 100644 index 000000000000..7005a3339afb --- /dev/null +++ b/pac/atsamc21n/src/can0/rxf1s.rs @@ -0,0 +1,203 @@ +#[doc = "Register `RXF1S` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `F1FL` reader - Rx FIFO 1 Fill Level"] +pub struct F1FL_R(crate::FieldReader); +impl F1FL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + F1FL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for F1FL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `F1GI` reader - Rx FIFO 1 Get Index"] +pub struct F1GI_R(crate::FieldReader); +impl F1GI_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + F1GI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for F1GI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `F1PI` reader - Rx FIFO 1 Put Index"] +pub struct F1PI_R(crate::FieldReader); +impl F1PI_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + F1PI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for F1PI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `F1F` reader - Rx FIFO 1 Full"] +pub struct F1F_R(crate::FieldReader); +impl F1F_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + F1F_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for F1F_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RF1L` reader - Rx FIFO 1 Message Lost"] +pub struct RF1L_R(crate::FieldReader); +impl RF1L_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RF1L_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RF1L_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Debug Message Status\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DMS_A { + #[doc = "0: Idle state"] + IDLE = 0, + #[doc = "1: Debug message A received"] + DBGA = 1, + #[doc = "2: Debug message A/B received"] + DBGB = 2, + #[doc = "3: Debug message A/B/C received, DMA request set"] + DBGC = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DMS_A) -> Self { + variant as _ + } +} +#[doc = "Field `DMS` reader - Debug Message Status"] +pub struct DMS_R(crate::FieldReader); +impl DMS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DMS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DMS_A { + match self.bits { + 0 => DMS_A::IDLE, + 1 => DMS_A::DBGA, + 2 => DMS_A::DBGB, + 3 => DMS_A::DBGC, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `IDLE`"] + #[inline(always)] + pub fn is_idle(&self) -> bool { + **self == DMS_A::IDLE + } + #[doc = "Checks if the value of the field is `DBGA`"] + #[inline(always)] + pub fn is_dbga(&self) -> bool { + **self == DMS_A::DBGA + } + #[doc = "Checks if the value of the field is `DBGB`"] + #[inline(always)] + pub fn is_dbgb(&self) -> bool { + **self == DMS_A::DBGB + } + #[doc = "Checks if the value of the field is `DBGC`"] + #[inline(always)] + pub fn is_dbgc(&self) -> bool { + **self == DMS_A::DBGC + } +} +impl core::ops::Deref for DMS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:6 - Rx FIFO 1 Fill Level"] + #[inline(always)] + pub fn f1fl(&self) -> F1FL_R { + F1FL_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bits 8:13 - Rx FIFO 1 Get Index"] + #[inline(always)] + pub fn f1gi(&self) -> F1GI_R { + F1GI_R::new(((self.bits >> 8) & 0x3f) as u8) + } + #[doc = "Bits 16:21 - Rx FIFO 1 Put Index"] + #[inline(always)] + pub fn f1pi(&self) -> F1PI_R { + F1PI_R::new(((self.bits >> 16) & 0x3f) as u8) + } + #[doc = "Bit 24 - Rx FIFO 1 Full"] + #[inline(always)] + pub fn f1f(&self) -> F1F_R { + F1F_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Rx FIFO 1 Message Lost"] + #[inline(always)] + pub fn rf1l(&self) -> RF1L_R { + RF1L_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bits 30:31 - Debug Message Status"] + #[inline(always)] + pub fn dms(&self) -> DMS_R { + DMS_R::new(((self.bits >> 30) & 0x03) as u8) + } +} +#[doc = "Rx FIFO 1 Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxf1s](index.html) module"] +pub struct RXF1S_SPEC; +impl crate::RegisterSpec for RXF1S_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rxf1s::R](R) reader structure"] +impl crate::Readable for RXF1S_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets RXF1S to value 0"] +impl crate::Resettable for RXF1S_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/can0/sidfc.rs b/pac/atsamc21n/src/can0/sidfc.rs new file mode 100644 index 000000000000..95a73efe426a --- /dev/null +++ b/pac/atsamc21n/src/can0/sidfc.rs @@ -0,0 +1,140 @@ +#[doc = "Register `SIDFC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SIDFC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FLSSA` reader - Filter List Standard Start Address"] +pub struct FLSSA_R(crate::FieldReader); +impl FLSSA_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + FLSSA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FLSSA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLSSA` writer - Filter List Standard Start Address"] +pub struct FLSSA_W<'a> { + w: &'a mut W, +} +impl<'a> FLSSA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +#[doc = "Field `LSS` reader - List Size Standard"] +pub struct LSS_R(crate::FieldReader); +impl LSS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LSS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LSS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LSS` writer - List Size Standard"] +pub struct LSS_W<'a> { + w: &'a mut W, +} +impl<'a> LSS_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Filter List Standard Start Address"] + #[inline(always)] + pub fn flssa(&self) -> FLSSA_R { + FLSSA_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:23 - List Size Standard"] + #[inline(always)] + pub fn lss(&self) -> LSS_R { + LSS_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:15 - Filter List Standard Start Address"] + #[inline(always)] + pub fn flssa(&mut self) -> FLSSA_W { + FLSSA_W { w: self } + } + #[doc = "Bits 16:23 - List Size Standard"] + #[inline(always)] + pub fn lss(&mut self) -> LSS_W { + LSS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Standard ID Filter Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sidfc](index.html) module"] +pub struct SIDFC_SPEC; +impl crate::RegisterSpec for SIDFC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [sidfc::R](R) reader structure"] +impl crate::Readable for SIDFC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [sidfc::W](W) writer structure"] +impl crate::Writable for SIDFC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SIDFC to value 0"] +impl crate::Resettable for SIDFC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/can0/tdcr.rs b/pac/atsamc21n/src/can0/tdcr.rs new file mode 100644 index 000000000000..0cec58f98e28 --- /dev/null +++ b/pac/atsamc21n/src/can0/tdcr.rs @@ -0,0 +1,140 @@ +#[doc = "Register `TDCR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TDCR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TDCF` reader - Transmitter Delay Compensation Filter Length"] +pub struct TDCF_R(crate::FieldReader); +impl TDCF_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TDCF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TDCF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TDCF` writer - Transmitter Delay Compensation Filter Length"] +pub struct TDCF_W<'a> { + w: &'a mut W, +} +impl<'a> TDCF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x7f) | (value as u32 & 0x7f); + self.w + } +} +#[doc = "Field `TDCO` reader - Transmitter Delay Compensation Offset"] +pub struct TDCO_R(crate::FieldReader); +impl TDCO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TDCO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TDCO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TDCO` writer - Transmitter Delay Compensation Offset"] +pub struct TDCO_W<'a> { + w: &'a mut W, +} +impl<'a> TDCO_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x7f << 8)) | ((value as u32 & 0x7f) << 8); + self.w + } +} +impl R { + #[doc = "Bits 0:6 - Transmitter Delay Compensation Filter Length"] + #[inline(always)] + pub fn tdcf(&self) -> TDCF_R { + TDCF_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bits 8:14 - Transmitter Delay Compensation Offset"] + #[inline(always)] + pub fn tdco(&self) -> TDCO_R { + TDCO_R::new(((self.bits >> 8) & 0x7f) as u8) + } +} +impl W { + #[doc = "Bits 0:6 - Transmitter Delay Compensation Filter Length"] + #[inline(always)] + pub fn tdcf(&mut self) -> TDCF_W { + TDCF_W { w: self } + } + #[doc = "Bits 8:14 - Transmitter Delay Compensation Offset"] + #[inline(always)] + pub fn tdco(&mut self) -> TDCO_W { + TDCO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Extended ID Filter Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tdcr](index.html) module"] +pub struct TDCR_SPEC; +impl crate::RegisterSpec for TDCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [tdcr::R](R) reader structure"] +impl crate::Readable for TDCR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [tdcr::W](W) writer structure"] +impl crate::Writable for TDCR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TDCR to value 0"] +impl crate::Resettable for TDCR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/can0/test.rs b/pac/atsamc21n/src/can0/test.rs new file mode 100644 index 000000000000..fe1417a03d90 --- /dev/null +++ b/pac/atsamc21n/src/can0/test.rs @@ -0,0 +1,272 @@ +#[doc = "Register `TEST` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TEST` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `LBCK` reader - Loop Back Mode"] +pub struct LBCK_R(crate::FieldReader); +impl LBCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LBCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LBCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LBCK` writer - Loop Back Mode"] +pub struct LBCK_W<'a> { + w: &'a mut W, +} +impl<'a> LBCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Control of Transmit Pin\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum TX_A { + #[doc = "0: TX controlled by CAN core"] + CORE = 0, + #[doc = "1: TX monitoring sample point"] + SAMPLE = 1, + #[doc = "2: Dominant (0) level at pin CAN_TX"] + DOMINANT = 2, + #[doc = "3: Recessive (1) level at pin CAN_TX"] + RECESSIVE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: TX_A) -> Self { + variant as _ + } +} +#[doc = "Field `TX` reader - Control of Transmit Pin"] +pub struct TX_R(crate::FieldReader); +impl TX_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TX_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TX_A { + match self.bits { + 0 => TX_A::CORE, + 1 => TX_A::SAMPLE, + 2 => TX_A::DOMINANT, + 3 => TX_A::RECESSIVE, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `CORE`"] + #[inline(always)] + pub fn is_core(&self) -> bool { + **self == TX_A::CORE + } + #[doc = "Checks if the value of the field is `SAMPLE`"] + #[inline(always)] + pub fn is_sample(&self) -> bool { + **self == TX_A::SAMPLE + } + #[doc = "Checks if the value of the field is `DOMINANT`"] + #[inline(always)] + pub fn is_dominant(&self) -> bool { + **self == TX_A::DOMINANT + } + #[doc = "Checks if the value of the field is `RECESSIVE`"] + #[inline(always)] + pub fn is_recessive(&self) -> bool { + **self == TX_A::RECESSIVE + } +} +impl core::ops::Deref for TX_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TX` writer - Control of Transmit Pin"] +pub struct TX_W<'a> { + w: &'a mut W, +} +impl<'a> TX_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TX_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "TX controlled by CAN core"] + #[inline(always)] + pub fn core(self) -> &'a mut W { + self.variant(TX_A::CORE) + } + #[doc = "TX monitoring sample point"] + #[inline(always)] + pub fn sample(self) -> &'a mut W { + self.variant(TX_A::SAMPLE) + } + #[doc = "Dominant (0) level at pin CAN_TX"] + #[inline(always)] + pub fn dominant(self) -> &'a mut W { + self.variant(TX_A::DOMINANT) + } + #[doc = "Recessive (1) level at pin CAN_TX"] + #[inline(always)] + pub fn recessive(self) -> &'a mut W { + self.variant(TX_A::RECESSIVE) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 5)) | ((value as u32 & 0x03) << 5); + self.w + } +} +#[doc = "Field `RX` reader - Receive Pin"] +pub struct RX_R(crate::FieldReader); +impl RX_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RX_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RX_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RX` writer - Receive Pin"] +pub struct RX_W<'a> { + w: &'a mut W, +} +impl<'a> RX_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 4 - Loop Back Mode"] + #[inline(always)] + pub fn lbck(&self) -> LBCK_R { + LBCK_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bits 5:6 - Control of Transmit Pin"] + #[inline(always)] + pub fn tx(&self) -> TX_R { + TX_R::new(((self.bits >> 5) & 0x03) as u8) + } + #[doc = "Bit 7 - Receive Pin"] + #[inline(always)] + pub fn rx(&self) -> RX_R { + RX_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 4 - Loop Back Mode"] + #[inline(always)] + pub fn lbck(&mut self) -> LBCK_W { + LBCK_W { w: self } + } + #[doc = "Bits 5:6 - Control of Transmit Pin"] + #[inline(always)] + pub fn tx(&mut self) -> TX_W { + TX_W { w: self } + } + #[doc = "Bit 7 - Receive Pin"] + #[inline(always)] + pub fn rx(&mut self) -> RX_W { + RX_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Test\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [test](index.html) module"] +pub struct TEST_SPEC; +impl crate::RegisterSpec for TEST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [test::R](R) reader structure"] +impl crate::Readable for TEST_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [test::W](W) writer structure"] +impl crate::Writable for TEST_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TEST to value 0"] +impl crate::Resettable for TEST_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/can0/tocc.rs b/pac/atsamc21n/src/can0/tocc.rs new file mode 100644 index 000000000000..fa64916ef75f --- /dev/null +++ b/pac/atsamc21n/src/can0/tocc.rs @@ -0,0 +1,262 @@ +#[doc = "Register `TOCC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TOCC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ETOC` reader - Enable Timeout Counter"] +pub struct ETOC_R(crate::FieldReader); +impl ETOC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ETOC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ETOC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ETOC` writer - Enable Timeout Counter"] +pub struct ETOC_W<'a> { + w: &'a mut W, +} +impl<'a> ETOC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Timeout Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum TOS_A { + #[doc = "0: Continuout operation"] + CONT = 0, + #[doc = "1: Timeout controlled by TX Event FIFO"] + TXEF = 1, + #[doc = "2: Timeout controlled by Rx FIFO 0"] + RXF0 = 2, + #[doc = "3: Timeout controlled by Rx FIFO 1"] + RXF1 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: TOS_A) -> Self { + variant as _ + } +} +#[doc = "Field `TOS` reader - Timeout Select"] +pub struct TOS_R(crate::FieldReader); +impl TOS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TOS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TOS_A { + match self.bits { + 0 => TOS_A::CONT, + 1 => TOS_A::TXEF, + 2 => TOS_A::RXF0, + 3 => TOS_A::RXF1, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `CONT`"] + #[inline(always)] + pub fn is_cont(&self) -> bool { + **self == TOS_A::CONT + } + #[doc = "Checks if the value of the field is `TXEF`"] + #[inline(always)] + pub fn is_txef(&self) -> bool { + **self == TOS_A::TXEF + } + #[doc = "Checks if the value of the field is `RXF0`"] + #[inline(always)] + pub fn is_rxf0(&self) -> bool { + **self == TOS_A::RXF0 + } + #[doc = "Checks if the value of the field is `RXF1`"] + #[inline(always)] + pub fn is_rxf1(&self) -> bool { + **self == TOS_A::RXF1 + } +} +impl core::ops::Deref for TOS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TOS` writer - Timeout Select"] +pub struct TOS_W<'a> { + w: &'a mut W, +} +impl<'a> TOS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TOS_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Continuout operation"] + #[inline(always)] + pub fn cont(self) -> &'a mut W { + self.variant(TOS_A::CONT) + } + #[doc = "Timeout controlled by TX Event FIFO"] + #[inline(always)] + pub fn txef(self) -> &'a mut W { + self.variant(TOS_A::TXEF) + } + #[doc = "Timeout controlled by Rx FIFO 0"] + #[inline(always)] + pub fn rxf0(self) -> &'a mut W { + self.variant(TOS_A::RXF0) + } + #[doc = "Timeout controlled by Rx FIFO 1"] + #[inline(always)] + pub fn rxf1(self) -> &'a mut W { + self.variant(TOS_A::RXF1) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 1)) | ((value as u32 & 0x03) << 1); + self.w + } +} +#[doc = "Field `TOP` reader - Timeout Period"] +pub struct TOP_R(crate::FieldReader); +impl TOP_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + TOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TOP` writer - Timeout Period"] +pub struct TOP_W<'a> { + w: &'a mut W, +} +impl<'a> TOP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xffff << 16)) | ((value as u32 & 0xffff) << 16); + self.w + } +} +impl R { + #[doc = "Bit 0 - Enable Timeout Counter"] + #[inline(always)] + pub fn etoc(&self) -> ETOC_R { + ETOC_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bits 1:2 - Timeout Select"] + #[inline(always)] + pub fn tos(&self) -> TOS_R { + TOS_R::new(((self.bits >> 1) & 0x03) as u8) + } + #[doc = "Bits 16:31 - Timeout Period"] + #[inline(always)] + pub fn top(&self) -> TOP_R { + TOP_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bit 0 - Enable Timeout Counter"] + #[inline(always)] + pub fn etoc(&mut self) -> ETOC_W { + ETOC_W { w: self } + } + #[doc = "Bits 1:2 - Timeout Select"] + #[inline(always)] + pub fn tos(&mut self) -> TOS_W { + TOS_W { w: self } + } + #[doc = "Bits 16:31 - Timeout Period"] + #[inline(always)] + pub fn top(&mut self) -> TOP_W { + TOP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Timeout Counter Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tocc](index.html) module"] +pub struct TOCC_SPEC; +impl crate::RegisterSpec for TOCC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [tocc::R](R) reader structure"] +impl crate::Readable for TOCC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [tocc::W](W) writer structure"] +impl crate::Writable for TOCC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TOCC to value 0xffff_0000"] +impl crate::Resettable for TOCC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_0000 + } +} diff --git a/pac/atsamc21n/src/can0/tocv.rs b/pac/atsamc21n/src/can0/tocv.rs new file mode 100644 index 000000000000..f49b24ce65bf --- /dev/null +++ b/pac/atsamc21n/src/can0/tocv.rs @@ -0,0 +1,103 @@ +#[doc = "Register `TOCV` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TOCV` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TOC` reader - Timeout Counter"] +pub struct TOC_R(crate::FieldReader); +impl TOC_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + TOC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TOC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TOC` writer - Timeout Counter"] +pub struct TOC_W<'a> { + w: &'a mut W, +} +impl<'a> TOC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Timeout Counter"] + #[inline(always)] + pub fn toc(&self) -> TOC_R { + TOC_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Timeout Counter"] + #[inline(always)] + pub fn toc(&mut self) -> TOC_W { + TOC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Timeout Counter Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tocv](index.html) module"] +pub struct TOCV_SPEC; +impl crate::RegisterSpec for TOCV_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [tocv::R](R) reader structure"] +impl crate::Readable for TOCV_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [tocv::W](W) writer structure"] +impl crate::Writable for TOCV_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TOCV to value 0xffff"] +impl crate::Resettable for TOCV_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff + } +} diff --git a/pac/atsamc21n/src/can0/tscc.rs b/pac/atsamc21n/src/can0/tscc.rs new file mode 100644 index 000000000000..298084cc06b8 --- /dev/null +++ b/pac/atsamc21n/src/can0/tscc.rs @@ -0,0 +1,202 @@ +#[doc = "Register `TSCC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TSCC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Timestamp Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum TSS_A { + #[doc = "0: Timestamp counter value always 0x0000"] + ZERO = 0, + #[doc = "1: Timestamp counter value incremented by TCP"] + INC = 1, + #[doc = "2: External timestamp counter value used"] + EXT = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: TSS_A) -> Self { + variant as _ + } +} +#[doc = "Field `TSS` reader - Timestamp Select"] +pub struct TSS_R(crate::FieldReader); +impl TSS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TSS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(TSS_A::ZERO), + 1 => Some(TSS_A::INC), + 2 => Some(TSS_A::EXT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `ZERO`"] + #[inline(always)] + pub fn is_zero(&self) -> bool { + **self == TSS_A::ZERO + } + #[doc = "Checks if the value of the field is `INC`"] + #[inline(always)] + pub fn is_inc(&self) -> bool { + **self == TSS_A::INC + } + #[doc = "Checks if the value of the field is `EXT`"] + #[inline(always)] + pub fn is_ext(&self) -> bool { + **self == TSS_A::EXT + } +} +impl core::ops::Deref for TSS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSS` writer - Timestamp Select"] +pub struct TSS_W<'a> { + w: &'a mut W, +} +impl<'a> TSS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TSS_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Timestamp counter value always 0x0000"] + #[inline(always)] + pub fn zero(self) -> &'a mut W { + self.variant(TSS_A::ZERO) + } + #[doc = "Timestamp counter value incremented by TCP"] + #[inline(always)] + pub fn inc(self) -> &'a mut W { + self.variant(TSS_A::INC) + } + #[doc = "External timestamp counter value used"] + #[inline(always)] + pub fn ext(self) -> &'a mut W { + self.variant(TSS_A::EXT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u32 & 0x03); + self.w + } +} +#[doc = "Field `TCP` reader - Timestamp Counter Prescaler"] +pub struct TCP_R(crate::FieldReader); +impl TCP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TCP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCP` writer - Timestamp Counter Prescaler"] +pub struct TCP_W<'a> { + w: &'a mut W, +} +impl<'a> TCP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 16)) | ((value as u32 & 0x0f) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Timestamp Select"] + #[inline(always)] + pub fn tss(&self) -> TSS_R { + TSS_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bits 16:19 - Timestamp Counter Prescaler"] + #[inline(always)] + pub fn tcp(&self) -> TCP_R { + TCP_R::new(((self.bits >> 16) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Timestamp Select"] + #[inline(always)] + pub fn tss(&mut self) -> TSS_W { + TSS_W { w: self } + } + #[doc = "Bits 16:19 - Timestamp Counter Prescaler"] + #[inline(always)] + pub fn tcp(&mut self) -> TCP_W { + TCP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Timestamp Counter Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tscc](index.html) module"] +pub struct TSCC_SPEC; +impl crate::RegisterSpec for TSCC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [tscc::R](R) reader structure"] +impl crate::Readable for TSCC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [tscc::W](W) writer structure"] +impl crate::Writable for TSCC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TSCC to value 0"] +impl crate::Resettable for TSCC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/can0/tscv.rs b/pac/atsamc21n/src/can0/tscv.rs new file mode 100644 index 000000000000..7ba4561d588f --- /dev/null +++ b/pac/atsamc21n/src/can0/tscv.rs @@ -0,0 +1,53 @@ +#[doc = "Register `TSCV` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `TSC` reader - Timestamp Counter"] +pub struct TSC_R(crate::FieldReader); +impl TSC_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + TSC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:15 - Timestamp Counter"] + #[inline(always)] + pub fn tsc(&self) -> TSC_R { + TSC_R::new((self.bits & 0xffff) as u16) + } +} +#[doc = "Timestamp Counter Value\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tscv](index.html) module"] +pub struct TSCV_SPEC; +impl crate::RegisterSpec for TSCV_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [tscv::R](R) reader structure"] +impl crate::Readable for TSCV_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets TSCV to value 0"] +impl crate::Resettable for TSCV_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/can0/txbar.rs b/pac/atsamc21n/src/can0/txbar.rs new file mode 100644 index 000000000000..bd15a3f2bd29 --- /dev/null +++ b/pac/atsamc21n/src/can0/txbar.rs @@ -0,0 +1,1570 @@ +#[doc = "Register `TXBAR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TXBAR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `AR0` reader - Add Request 0"] +pub struct AR0_R(crate::FieldReader); +impl AR0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR0` writer - Add Request 0"] +pub struct AR0_W<'a> { + w: &'a mut W, +} +impl<'a> AR0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `AR1` reader - Add Request 1"] +pub struct AR1_R(crate::FieldReader); +impl AR1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR1` writer - Add Request 1"] +pub struct AR1_W<'a> { + w: &'a mut W, +} +impl<'a> AR1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `AR2` reader - Add Request 2"] +pub struct AR2_R(crate::FieldReader); +impl AR2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR2` writer - Add Request 2"] +pub struct AR2_W<'a> { + w: &'a mut W, +} +impl<'a> AR2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `AR3` reader - Add Request 3"] +pub struct AR3_R(crate::FieldReader); +impl AR3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR3` writer - Add Request 3"] +pub struct AR3_W<'a> { + w: &'a mut W, +} +impl<'a> AR3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `AR4` reader - Add Request 4"] +pub struct AR4_R(crate::FieldReader); +impl AR4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR4` writer - Add Request 4"] +pub struct AR4_W<'a> { + w: &'a mut W, +} +impl<'a> AR4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `AR5` reader - Add Request 5"] +pub struct AR5_R(crate::FieldReader); +impl AR5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR5` writer - Add Request 5"] +pub struct AR5_W<'a> { + w: &'a mut W, +} +impl<'a> AR5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `AR6` reader - Add Request 6"] +pub struct AR6_R(crate::FieldReader); +impl AR6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR6` writer - Add Request 6"] +pub struct AR6_W<'a> { + w: &'a mut W, +} +impl<'a> AR6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `AR7` reader - Add Request 7"] +pub struct AR7_R(crate::FieldReader); +impl AR7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR7` writer - Add Request 7"] +pub struct AR7_W<'a> { + w: &'a mut W, +} +impl<'a> AR7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `AR8` reader - Add Request 8"] +pub struct AR8_R(crate::FieldReader); +impl AR8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR8` writer - Add Request 8"] +pub struct AR8_W<'a> { + w: &'a mut W, +} +impl<'a> AR8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `AR9` reader - Add Request 9"] +pub struct AR9_R(crate::FieldReader); +impl AR9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR9` writer - Add Request 9"] +pub struct AR9_W<'a> { + w: &'a mut W, +} +impl<'a> AR9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `AR10` reader - Add Request 10"] +pub struct AR10_R(crate::FieldReader); +impl AR10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR10` writer - Add Request 10"] +pub struct AR10_W<'a> { + w: &'a mut W, +} +impl<'a> AR10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `AR11` reader - Add Request 11"] +pub struct AR11_R(crate::FieldReader); +impl AR11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR11` writer - Add Request 11"] +pub struct AR11_W<'a> { + w: &'a mut W, +} +impl<'a> AR11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `AR12` reader - Add Request 12"] +pub struct AR12_R(crate::FieldReader); +impl AR12_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR12_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR12_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR12` writer - Add Request 12"] +pub struct AR12_W<'a> { + w: &'a mut W, +} +impl<'a> AR12_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `AR13` reader - Add Request 13"] +pub struct AR13_R(crate::FieldReader); +impl AR13_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR13_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR13_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR13` writer - Add Request 13"] +pub struct AR13_W<'a> { + w: &'a mut W, +} +impl<'a> AR13_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `AR14` reader - Add Request 14"] +pub struct AR14_R(crate::FieldReader); +impl AR14_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR14_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR14_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR14` writer - Add Request 14"] +pub struct AR14_W<'a> { + w: &'a mut W, +} +impl<'a> AR14_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `AR15` reader - Add Request 15"] +pub struct AR15_R(crate::FieldReader); +impl AR15_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR15_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR15_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR15` writer - Add Request 15"] +pub struct AR15_W<'a> { + w: &'a mut W, +} +impl<'a> AR15_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `AR16` reader - Add Request 16"] +pub struct AR16_R(crate::FieldReader); +impl AR16_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR16_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR16_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR16` writer - Add Request 16"] +pub struct AR16_W<'a> { + w: &'a mut W, +} +impl<'a> AR16_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `AR17` reader - Add Request 17"] +pub struct AR17_R(crate::FieldReader); +impl AR17_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR17_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR17_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR17` writer - Add Request 17"] +pub struct AR17_W<'a> { + w: &'a mut W, +} +impl<'a> AR17_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `AR18` reader - Add Request 18"] +pub struct AR18_R(crate::FieldReader); +impl AR18_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR18_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR18_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR18` writer - Add Request 18"] +pub struct AR18_W<'a> { + w: &'a mut W, +} +impl<'a> AR18_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `AR19` reader - Add Request 19"] +pub struct AR19_R(crate::FieldReader); +impl AR19_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR19_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR19_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR19` writer - Add Request 19"] +pub struct AR19_W<'a> { + w: &'a mut W, +} +impl<'a> AR19_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `AR20` reader - Add Request 20"] +pub struct AR20_R(crate::FieldReader); +impl AR20_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR20_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR20_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR20` writer - Add Request 20"] +pub struct AR20_W<'a> { + w: &'a mut W, +} +impl<'a> AR20_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `AR21` reader - Add Request 21"] +pub struct AR21_R(crate::FieldReader); +impl AR21_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR21_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR21_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR21` writer - Add Request 21"] +pub struct AR21_W<'a> { + w: &'a mut W, +} +impl<'a> AR21_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `AR22` reader - Add Request 22"] +pub struct AR22_R(crate::FieldReader); +impl AR22_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR22_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR22_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR22` writer - Add Request 22"] +pub struct AR22_W<'a> { + w: &'a mut W, +} +impl<'a> AR22_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `AR23` reader - Add Request 23"] +pub struct AR23_R(crate::FieldReader); +impl AR23_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR23_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR23_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR23` writer - Add Request 23"] +pub struct AR23_W<'a> { + w: &'a mut W, +} +impl<'a> AR23_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `AR24` reader - Add Request 24"] +pub struct AR24_R(crate::FieldReader); +impl AR24_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR24_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR24_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR24` writer - Add Request 24"] +pub struct AR24_W<'a> { + w: &'a mut W, +} +impl<'a> AR24_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `AR25` reader - Add Request 25"] +pub struct AR25_R(crate::FieldReader); +impl AR25_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR25_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR25_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR25` writer - Add Request 25"] +pub struct AR25_W<'a> { + w: &'a mut W, +} +impl<'a> AR25_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `AR26` reader - Add Request 26"] +pub struct AR26_R(crate::FieldReader); +impl AR26_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR26_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR26_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR26` writer - Add Request 26"] +pub struct AR26_W<'a> { + w: &'a mut W, +} +impl<'a> AR26_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `AR27` reader - Add Request 27"] +pub struct AR27_R(crate::FieldReader); +impl AR27_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR27_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR27_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR27` writer - Add Request 27"] +pub struct AR27_W<'a> { + w: &'a mut W, +} +impl<'a> AR27_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +#[doc = "Field `AR28` reader - Add Request 28"] +pub struct AR28_R(crate::FieldReader); +impl AR28_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR28_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR28_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR28` writer - Add Request 28"] +pub struct AR28_W<'a> { + w: &'a mut W, +} +impl<'a> AR28_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Field `AR29` reader - Add Request 29"] +pub struct AR29_R(crate::FieldReader); +impl AR29_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR29_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR29_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR29` writer - Add Request 29"] +pub struct AR29_W<'a> { + w: &'a mut W, +} +impl<'a> AR29_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29); + self.w + } +} +#[doc = "Field `AR30` reader - Add Request 30"] +pub struct AR30_R(crate::FieldReader); +impl AR30_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR30_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR30_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR30` writer - Add Request 30"] +pub struct AR30_W<'a> { + w: &'a mut W, +} +impl<'a> AR30_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +#[doc = "Field `AR31` reader - Add Request 31"] +pub struct AR31_R(crate::FieldReader); +impl AR31_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AR31_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AR31_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AR31` writer - Add Request 31"] +pub struct AR31_W<'a> { + w: &'a mut W, +} +impl<'a> AR31_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bit 0 - Add Request 0"] + #[inline(always)] + pub fn ar0(&self) -> AR0_R { + AR0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Add Request 1"] + #[inline(always)] + pub fn ar1(&self) -> AR1_R { + AR1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Add Request 2"] + #[inline(always)] + pub fn ar2(&self) -> AR2_R { + AR2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Add Request 3"] + #[inline(always)] + pub fn ar3(&self) -> AR3_R { + AR3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Add Request 4"] + #[inline(always)] + pub fn ar4(&self) -> AR4_R { + AR4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Add Request 5"] + #[inline(always)] + pub fn ar5(&self) -> AR5_R { + AR5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Add Request 6"] + #[inline(always)] + pub fn ar6(&self) -> AR6_R { + AR6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Add Request 7"] + #[inline(always)] + pub fn ar7(&self) -> AR7_R { + AR7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Add Request 8"] + #[inline(always)] + pub fn ar8(&self) -> AR8_R { + AR8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Add Request 9"] + #[inline(always)] + pub fn ar9(&self) -> AR9_R { + AR9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Add Request 10"] + #[inline(always)] + pub fn ar10(&self) -> AR10_R { + AR10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Add Request 11"] + #[inline(always)] + pub fn ar11(&self) -> AR11_R { + AR11_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Add Request 12"] + #[inline(always)] + pub fn ar12(&self) -> AR12_R { + AR12_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Add Request 13"] + #[inline(always)] + pub fn ar13(&self) -> AR13_R { + AR13_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Add Request 14"] + #[inline(always)] + pub fn ar14(&self) -> AR14_R { + AR14_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Add Request 15"] + #[inline(always)] + pub fn ar15(&self) -> AR15_R { + AR15_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Add Request 16"] + #[inline(always)] + pub fn ar16(&self) -> AR16_R { + AR16_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Add Request 17"] + #[inline(always)] + pub fn ar17(&self) -> AR17_R { + AR17_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Add Request 18"] + #[inline(always)] + pub fn ar18(&self) -> AR18_R { + AR18_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Add Request 19"] + #[inline(always)] + pub fn ar19(&self) -> AR19_R { + AR19_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Add Request 20"] + #[inline(always)] + pub fn ar20(&self) -> AR20_R { + AR20_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Add Request 21"] + #[inline(always)] + pub fn ar21(&self) -> AR21_R { + AR21_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Add Request 22"] + #[inline(always)] + pub fn ar22(&self) -> AR22_R { + AR22_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Add Request 23"] + #[inline(always)] + pub fn ar23(&self) -> AR23_R { + AR23_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24 - Add Request 24"] + #[inline(always)] + pub fn ar24(&self) -> AR24_R { + AR24_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Add Request 25"] + #[inline(always)] + pub fn ar25(&self) -> AR25_R { + AR25_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Add Request 26"] + #[inline(always)] + pub fn ar26(&self) -> AR26_R { + AR26_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Add Request 27"] + #[inline(always)] + pub fn ar27(&self) -> AR27_R { + AR27_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28 - Add Request 28"] + #[inline(always)] + pub fn ar28(&self) -> AR28_R { + AR28_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Add Request 29"] + #[inline(always)] + pub fn ar29(&self) -> AR29_R { + AR29_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - Add Request 30"] + #[inline(always)] + pub fn ar30(&self) -> AR30_R { + AR30_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 31 - Add Request 31"] + #[inline(always)] + pub fn ar31(&self) -> AR31_R { + AR31_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Add Request 0"] + #[inline(always)] + pub fn ar0(&mut self) -> AR0_W { + AR0_W { w: self } + } + #[doc = "Bit 1 - Add Request 1"] + #[inline(always)] + pub fn ar1(&mut self) -> AR1_W { + AR1_W { w: self } + } + #[doc = "Bit 2 - Add Request 2"] + #[inline(always)] + pub fn ar2(&mut self) -> AR2_W { + AR2_W { w: self } + } + #[doc = "Bit 3 - Add Request 3"] + #[inline(always)] + pub fn ar3(&mut self) -> AR3_W { + AR3_W { w: self } + } + #[doc = "Bit 4 - Add Request 4"] + #[inline(always)] + pub fn ar4(&mut self) -> AR4_W { + AR4_W { w: self } + } + #[doc = "Bit 5 - Add Request 5"] + #[inline(always)] + pub fn ar5(&mut self) -> AR5_W { + AR5_W { w: self } + } + #[doc = "Bit 6 - Add Request 6"] + #[inline(always)] + pub fn ar6(&mut self) -> AR6_W { + AR6_W { w: self } + } + #[doc = "Bit 7 - Add Request 7"] + #[inline(always)] + pub fn ar7(&mut self) -> AR7_W { + AR7_W { w: self } + } + #[doc = "Bit 8 - Add Request 8"] + #[inline(always)] + pub fn ar8(&mut self) -> AR8_W { + AR8_W { w: self } + } + #[doc = "Bit 9 - Add Request 9"] + #[inline(always)] + pub fn ar9(&mut self) -> AR9_W { + AR9_W { w: self } + } + #[doc = "Bit 10 - Add Request 10"] + #[inline(always)] + pub fn ar10(&mut self) -> AR10_W { + AR10_W { w: self } + } + #[doc = "Bit 11 - Add Request 11"] + #[inline(always)] + pub fn ar11(&mut self) -> AR11_W { + AR11_W { w: self } + } + #[doc = "Bit 12 - Add Request 12"] + #[inline(always)] + pub fn ar12(&mut self) -> AR12_W { + AR12_W { w: self } + } + #[doc = "Bit 13 - Add Request 13"] + #[inline(always)] + pub fn ar13(&mut self) -> AR13_W { + AR13_W { w: self } + } + #[doc = "Bit 14 - Add Request 14"] + #[inline(always)] + pub fn ar14(&mut self) -> AR14_W { + AR14_W { w: self } + } + #[doc = "Bit 15 - Add Request 15"] + #[inline(always)] + pub fn ar15(&mut self) -> AR15_W { + AR15_W { w: self } + } + #[doc = "Bit 16 - Add Request 16"] + #[inline(always)] + pub fn ar16(&mut self) -> AR16_W { + AR16_W { w: self } + } + #[doc = "Bit 17 - Add Request 17"] + #[inline(always)] + pub fn ar17(&mut self) -> AR17_W { + AR17_W { w: self } + } + #[doc = "Bit 18 - Add Request 18"] + #[inline(always)] + pub fn ar18(&mut self) -> AR18_W { + AR18_W { w: self } + } + #[doc = "Bit 19 - Add Request 19"] + #[inline(always)] + pub fn ar19(&mut self) -> AR19_W { + AR19_W { w: self } + } + #[doc = "Bit 20 - Add Request 20"] + #[inline(always)] + pub fn ar20(&mut self) -> AR20_W { + AR20_W { w: self } + } + #[doc = "Bit 21 - Add Request 21"] + #[inline(always)] + pub fn ar21(&mut self) -> AR21_W { + AR21_W { w: self } + } + #[doc = "Bit 22 - Add Request 22"] + #[inline(always)] + pub fn ar22(&mut self) -> AR22_W { + AR22_W { w: self } + } + #[doc = "Bit 23 - Add Request 23"] + #[inline(always)] + pub fn ar23(&mut self) -> AR23_W { + AR23_W { w: self } + } + #[doc = "Bit 24 - Add Request 24"] + #[inline(always)] + pub fn ar24(&mut self) -> AR24_W { + AR24_W { w: self } + } + #[doc = "Bit 25 - Add Request 25"] + #[inline(always)] + pub fn ar25(&mut self) -> AR25_W { + AR25_W { w: self } + } + #[doc = "Bit 26 - Add Request 26"] + #[inline(always)] + pub fn ar26(&mut self) -> AR26_W { + AR26_W { w: self } + } + #[doc = "Bit 27 - Add Request 27"] + #[inline(always)] + pub fn ar27(&mut self) -> AR27_W { + AR27_W { w: self } + } + #[doc = "Bit 28 - Add Request 28"] + #[inline(always)] + pub fn ar28(&mut self) -> AR28_W { + AR28_W { w: self } + } + #[doc = "Bit 29 - Add Request 29"] + #[inline(always)] + pub fn ar29(&mut self) -> AR29_W { + AR29_W { w: self } + } + #[doc = "Bit 30 - Add Request 30"] + #[inline(always)] + pub fn ar30(&mut self) -> AR30_W { + AR30_W { w: self } + } + #[doc = "Bit 31 - Add Request 31"] + #[inline(always)] + pub fn ar31(&mut self) -> AR31_W { + AR31_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Tx Buffer Add Request\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txbar](index.html) module"] +pub struct TXBAR_SPEC; +impl crate::RegisterSpec for TXBAR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [txbar::R](R) reader structure"] +impl crate::Readable for TXBAR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [txbar::W](W) writer structure"] +impl crate::Writable for TXBAR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TXBAR to value 0"] +impl crate::Resettable for TXBAR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/can0/txbc.rs b/pac/atsamc21n/src/can0/txbc.rs new file mode 100644 index 000000000000..9545eaebf91d --- /dev/null +++ b/pac/atsamc21n/src/can0/txbc.rs @@ -0,0 +1,224 @@ +#[doc = "Register `TXBC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TXBC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TBSA` reader - Tx Buffers Start Address"] +pub struct TBSA_R(crate::FieldReader); +impl TBSA_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + TBSA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TBSA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TBSA` writer - Tx Buffers Start Address"] +pub struct TBSA_W<'a> { + w: &'a mut W, +} +impl<'a> TBSA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +#[doc = "Field `NDTB` reader - Number of Dedicated Transmit Buffers"] +pub struct NDTB_R(crate::FieldReader); +impl NDTB_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + NDTB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NDTB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NDTB` writer - Number of Dedicated Transmit Buffers"] +pub struct NDTB_W<'a> { + w: &'a mut W, +} +impl<'a> NDTB_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 16)) | ((value as u32 & 0x3f) << 16); + self.w + } +} +#[doc = "Field `TFQS` reader - Transmit FIFO/Queue Size"] +pub struct TFQS_R(crate::FieldReader); +impl TFQS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TFQS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TFQS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TFQS` writer - Transmit FIFO/Queue Size"] +pub struct TFQS_W<'a> { + w: &'a mut W, +} +impl<'a> TFQS_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 24)) | ((value as u32 & 0x3f) << 24); + self.w + } +} +#[doc = "Field `TFQM` reader - Tx FIFO/Queue Mode"] +pub struct TFQM_R(crate::FieldReader); +impl TFQM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TFQM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TFQM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TFQM` writer - Tx FIFO/Queue Mode"] +pub struct TFQM_W<'a> { + w: &'a mut W, +} +impl<'a> TFQM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Tx Buffers Start Address"] + #[inline(always)] + pub fn tbsa(&self) -> TBSA_R { + TBSA_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:21 - Number of Dedicated Transmit Buffers"] + #[inline(always)] + pub fn ndtb(&self) -> NDTB_R { + NDTB_R::new(((self.bits >> 16) & 0x3f) as u8) + } + #[doc = "Bits 24:29 - Transmit FIFO/Queue Size"] + #[inline(always)] + pub fn tfqs(&self) -> TFQS_R { + TFQS_R::new(((self.bits >> 24) & 0x3f) as u8) + } + #[doc = "Bit 30 - Tx FIFO/Queue Mode"] + #[inline(always)] + pub fn tfqm(&self) -> TFQM_R { + TFQM_R::new(((self.bits >> 30) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Tx Buffers Start Address"] + #[inline(always)] + pub fn tbsa(&mut self) -> TBSA_W { + TBSA_W { w: self } + } + #[doc = "Bits 16:21 - Number of Dedicated Transmit Buffers"] + #[inline(always)] + pub fn ndtb(&mut self) -> NDTB_W { + NDTB_W { w: self } + } + #[doc = "Bits 24:29 - Transmit FIFO/Queue Size"] + #[inline(always)] + pub fn tfqs(&mut self) -> TFQS_W { + TFQS_W { w: self } + } + #[doc = "Bit 30 - Tx FIFO/Queue Mode"] + #[inline(always)] + pub fn tfqm(&mut self) -> TFQM_W { + TFQM_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Tx Buffer Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txbc](index.html) module"] +pub struct TXBC_SPEC; +impl crate::RegisterSpec for TXBC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [txbc::R](R) reader structure"] +impl crate::Readable for TXBC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [txbc::W](W) writer structure"] +impl crate::Writable for TXBC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TXBC to value 0"] +impl crate::Resettable for TXBC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/can0/txbcf.rs b/pac/atsamc21n/src/can0/txbcf.rs new file mode 100644 index 000000000000..e592d4e90bea --- /dev/null +++ b/pac/atsamc21n/src/can0/txbcf.rs @@ -0,0 +1,673 @@ +#[doc = "Register `TXBCF` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `CF0` reader - Tx Buffer Cancellation Finished 0"] +pub struct CF0_R(crate::FieldReader); +impl CF0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF1` reader - Tx Buffer Cancellation Finished 1"] +pub struct CF1_R(crate::FieldReader); +impl CF1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF2` reader - Tx Buffer Cancellation Finished 2"] +pub struct CF2_R(crate::FieldReader); +impl CF2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF3` reader - Tx Buffer Cancellation Finished 3"] +pub struct CF3_R(crate::FieldReader); +impl CF3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF4` reader - Tx Buffer Cancellation Finished 4"] +pub struct CF4_R(crate::FieldReader); +impl CF4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF5` reader - Tx Buffer Cancellation Finished 5"] +pub struct CF5_R(crate::FieldReader); +impl CF5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF6` reader - Tx Buffer Cancellation Finished 6"] +pub struct CF6_R(crate::FieldReader); +impl CF6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF7` reader - Tx Buffer Cancellation Finished 7"] +pub struct CF7_R(crate::FieldReader); +impl CF7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF8` reader - Tx Buffer Cancellation Finished 8"] +pub struct CF8_R(crate::FieldReader); +impl CF8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF9` reader - Tx Buffer Cancellation Finished 9"] +pub struct CF9_R(crate::FieldReader); +impl CF9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF10` reader - Tx Buffer Cancellation Finished 10"] +pub struct CF10_R(crate::FieldReader); +impl CF10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF11` reader - Tx Buffer Cancellation Finished 11"] +pub struct CF11_R(crate::FieldReader); +impl CF11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF12` reader - Tx Buffer Cancellation Finished 12"] +pub struct CF12_R(crate::FieldReader); +impl CF12_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF12_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF12_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF13` reader - Tx Buffer Cancellation Finished 13"] +pub struct CF13_R(crate::FieldReader); +impl CF13_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF13_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF13_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF14` reader - Tx Buffer Cancellation Finished 14"] +pub struct CF14_R(crate::FieldReader); +impl CF14_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF14_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF14_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF15` reader - Tx Buffer Cancellation Finished 15"] +pub struct CF15_R(crate::FieldReader); +impl CF15_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF15_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF15_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF16` reader - Tx Buffer Cancellation Finished 16"] +pub struct CF16_R(crate::FieldReader); +impl CF16_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF16_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF16_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF17` reader - Tx Buffer Cancellation Finished 17"] +pub struct CF17_R(crate::FieldReader); +impl CF17_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF17_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF17_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF18` reader - Tx Buffer Cancellation Finished 18"] +pub struct CF18_R(crate::FieldReader); +impl CF18_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF18_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF18_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF19` reader - Tx Buffer Cancellation Finished 19"] +pub struct CF19_R(crate::FieldReader); +impl CF19_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF19_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF19_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF20` reader - Tx Buffer Cancellation Finished 20"] +pub struct CF20_R(crate::FieldReader); +impl CF20_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF20_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF20_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF21` reader - Tx Buffer Cancellation Finished 21"] +pub struct CF21_R(crate::FieldReader); +impl CF21_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF21_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF21_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF22` reader - Tx Buffer Cancellation Finished 22"] +pub struct CF22_R(crate::FieldReader); +impl CF22_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF22_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF22_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF23` reader - Tx Buffer Cancellation Finished 23"] +pub struct CF23_R(crate::FieldReader); +impl CF23_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF23_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF23_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF24` reader - Tx Buffer Cancellation Finished 24"] +pub struct CF24_R(crate::FieldReader); +impl CF24_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF24_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF24_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF25` reader - Tx Buffer Cancellation Finished 25"] +pub struct CF25_R(crate::FieldReader); +impl CF25_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF25_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF25_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF26` reader - Tx Buffer Cancellation Finished 26"] +pub struct CF26_R(crate::FieldReader); +impl CF26_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF26_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF26_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF27` reader - Tx Buffer Cancellation Finished 27"] +pub struct CF27_R(crate::FieldReader); +impl CF27_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF27_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF27_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF28` reader - Tx Buffer Cancellation Finished 28"] +pub struct CF28_R(crate::FieldReader); +impl CF28_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF28_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF28_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF29` reader - Tx Buffer Cancellation Finished 29"] +pub struct CF29_R(crate::FieldReader); +impl CF29_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF29_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF29_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF30` reader - Tx Buffer Cancellation Finished 30"] +pub struct CF30_R(crate::FieldReader); +impl CF30_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF30_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF30_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CF31` reader - Tx Buffer Cancellation Finished 31"] +pub struct CF31_R(crate::FieldReader); +impl CF31_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CF31_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CF31_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Tx Buffer Cancellation Finished 0"] + #[inline(always)] + pub fn cf0(&self) -> CF0_R { + CF0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Tx Buffer Cancellation Finished 1"] + #[inline(always)] + pub fn cf1(&self) -> CF1_R { + CF1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Tx Buffer Cancellation Finished 2"] + #[inline(always)] + pub fn cf2(&self) -> CF2_R { + CF2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Tx Buffer Cancellation Finished 3"] + #[inline(always)] + pub fn cf3(&self) -> CF3_R { + CF3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Tx Buffer Cancellation Finished 4"] + #[inline(always)] + pub fn cf4(&self) -> CF4_R { + CF4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Tx Buffer Cancellation Finished 5"] + #[inline(always)] + pub fn cf5(&self) -> CF5_R { + CF5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Tx Buffer Cancellation Finished 6"] + #[inline(always)] + pub fn cf6(&self) -> CF6_R { + CF6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Tx Buffer Cancellation Finished 7"] + #[inline(always)] + pub fn cf7(&self) -> CF7_R { + CF7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Tx Buffer Cancellation Finished 8"] + #[inline(always)] + pub fn cf8(&self) -> CF8_R { + CF8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Tx Buffer Cancellation Finished 9"] + #[inline(always)] + pub fn cf9(&self) -> CF9_R { + CF9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Tx Buffer Cancellation Finished 10"] + #[inline(always)] + pub fn cf10(&self) -> CF10_R { + CF10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Tx Buffer Cancellation Finished 11"] + #[inline(always)] + pub fn cf11(&self) -> CF11_R { + CF11_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Tx Buffer Cancellation Finished 12"] + #[inline(always)] + pub fn cf12(&self) -> CF12_R { + CF12_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Tx Buffer Cancellation Finished 13"] + #[inline(always)] + pub fn cf13(&self) -> CF13_R { + CF13_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Tx Buffer Cancellation Finished 14"] + #[inline(always)] + pub fn cf14(&self) -> CF14_R { + CF14_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Tx Buffer Cancellation Finished 15"] + #[inline(always)] + pub fn cf15(&self) -> CF15_R { + CF15_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Tx Buffer Cancellation Finished 16"] + #[inline(always)] + pub fn cf16(&self) -> CF16_R { + CF16_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Tx Buffer Cancellation Finished 17"] + #[inline(always)] + pub fn cf17(&self) -> CF17_R { + CF17_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Tx Buffer Cancellation Finished 18"] + #[inline(always)] + pub fn cf18(&self) -> CF18_R { + CF18_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Tx Buffer Cancellation Finished 19"] + #[inline(always)] + pub fn cf19(&self) -> CF19_R { + CF19_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Tx Buffer Cancellation Finished 20"] + #[inline(always)] + pub fn cf20(&self) -> CF20_R { + CF20_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Tx Buffer Cancellation Finished 21"] + #[inline(always)] + pub fn cf21(&self) -> CF21_R { + CF21_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Tx Buffer Cancellation Finished 22"] + #[inline(always)] + pub fn cf22(&self) -> CF22_R { + CF22_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Tx Buffer Cancellation Finished 23"] + #[inline(always)] + pub fn cf23(&self) -> CF23_R { + CF23_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24 - Tx Buffer Cancellation Finished 24"] + #[inline(always)] + pub fn cf24(&self) -> CF24_R { + CF24_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Tx Buffer Cancellation Finished 25"] + #[inline(always)] + pub fn cf25(&self) -> CF25_R { + CF25_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Tx Buffer Cancellation Finished 26"] + #[inline(always)] + pub fn cf26(&self) -> CF26_R { + CF26_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Tx Buffer Cancellation Finished 27"] + #[inline(always)] + pub fn cf27(&self) -> CF27_R { + CF27_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28 - Tx Buffer Cancellation Finished 28"] + #[inline(always)] + pub fn cf28(&self) -> CF28_R { + CF28_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Tx Buffer Cancellation Finished 29"] + #[inline(always)] + pub fn cf29(&self) -> CF29_R { + CF29_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - Tx Buffer Cancellation Finished 30"] + #[inline(always)] + pub fn cf30(&self) -> CF30_R { + CF30_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 31 - Tx Buffer Cancellation Finished 31"] + #[inline(always)] + pub fn cf31(&self) -> CF31_R { + CF31_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +#[doc = "Tx Buffer Cancellation Finished\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txbcf](index.html) module"] +pub struct TXBCF_SPEC; +impl crate::RegisterSpec for TXBCF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [txbcf::R](R) reader structure"] +impl crate::Readable for TXBCF_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets TXBCF to value 0"] +impl crate::Resettable for TXBCF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/can0/txbcie.rs b/pac/atsamc21n/src/can0/txbcie.rs new file mode 100644 index 000000000000..ca0c9c0a2822 --- /dev/null +++ b/pac/atsamc21n/src/can0/txbcie.rs @@ -0,0 +1,1570 @@ +#[doc = "Register `TXBCIE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TXBCIE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CFIE0` reader - Cancellation Finished Interrupt Enable 0"] +pub struct CFIE0_R(crate::FieldReader); +impl CFIE0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE0` writer - Cancellation Finished Interrupt Enable 0"] +pub struct CFIE0_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `CFIE1` reader - Cancellation Finished Interrupt Enable 1"] +pub struct CFIE1_R(crate::FieldReader); +impl CFIE1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE1` writer - Cancellation Finished Interrupt Enable 1"] +pub struct CFIE1_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CFIE2` reader - Cancellation Finished Interrupt Enable 2"] +pub struct CFIE2_R(crate::FieldReader); +impl CFIE2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE2` writer - Cancellation Finished Interrupt Enable 2"] +pub struct CFIE2_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CFIE3` reader - Cancellation Finished Interrupt Enable 3"] +pub struct CFIE3_R(crate::FieldReader); +impl CFIE3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE3` writer - Cancellation Finished Interrupt Enable 3"] +pub struct CFIE3_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CFIE4` reader - Cancellation Finished Interrupt Enable 4"] +pub struct CFIE4_R(crate::FieldReader); +impl CFIE4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE4` writer - Cancellation Finished Interrupt Enable 4"] +pub struct CFIE4_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `CFIE5` reader - Cancellation Finished Interrupt Enable 5"] +pub struct CFIE5_R(crate::FieldReader); +impl CFIE5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE5` writer - Cancellation Finished Interrupt Enable 5"] +pub struct CFIE5_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `CFIE6` reader - Cancellation Finished Interrupt Enable 6"] +pub struct CFIE6_R(crate::FieldReader); +impl CFIE6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE6` writer - Cancellation Finished Interrupt Enable 6"] +pub struct CFIE6_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `CFIE7` reader - Cancellation Finished Interrupt Enable 7"] +pub struct CFIE7_R(crate::FieldReader); +impl CFIE7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE7` writer - Cancellation Finished Interrupt Enable 7"] +pub struct CFIE7_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CFIE8` reader - Cancellation Finished Interrupt Enable 8"] +pub struct CFIE8_R(crate::FieldReader); +impl CFIE8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE8` writer - Cancellation Finished Interrupt Enable 8"] +pub struct CFIE8_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `CFIE9` reader - Cancellation Finished Interrupt Enable 9"] +pub struct CFIE9_R(crate::FieldReader); +impl CFIE9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE9` writer - Cancellation Finished Interrupt Enable 9"] +pub struct CFIE9_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `CFIE10` reader - Cancellation Finished Interrupt Enable 10"] +pub struct CFIE10_R(crate::FieldReader); +impl CFIE10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE10` writer - Cancellation Finished Interrupt Enable 10"] +pub struct CFIE10_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `CFIE11` reader - Cancellation Finished Interrupt Enable 11"] +pub struct CFIE11_R(crate::FieldReader); +impl CFIE11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE11` writer - Cancellation Finished Interrupt Enable 11"] +pub struct CFIE11_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `CFIE12` reader - Cancellation Finished Interrupt Enable 12"] +pub struct CFIE12_R(crate::FieldReader); +impl CFIE12_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE12_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE12_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE12` writer - Cancellation Finished Interrupt Enable 12"] +pub struct CFIE12_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE12_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `CFIE13` reader - Cancellation Finished Interrupt Enable 13"] +pub struct CFIE13_R(crate::FieldReader); +impl CFIE13_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE13_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE13_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE13` writer - Cancellation Finished Interrupt Enable 13"] +pub struct CFIE13_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE13_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `CFIE14` reader - Cancellation Finished Interrupt Enable 14"] +pub struct CFIE14_R(crate::FieldReader); +impl CFIE14_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE14_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE14_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE14` writer - Cancellation Finished Interrupt Enable 14"] +pub struct CFIE14_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE14_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `CFIE15` reader - Cancellation Finished Interrupt Enable 15"] +pub struct CFIE15_R(crate::FieldReader); +impl CFIE15_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE15_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE15_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE15` writer - Cancellation Finished Interrupt Enable 15"] +pub struct CFIE15_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE15_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `CFIE16` reader - Cancellation Finished Interrupt Enable 16"] +pub struct CFIE16_R(crate::FieldReader); +impl CFIE16_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE16_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE16_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE16` writer - Cancellation Finished Interrupt Enable 16"] +pub struct CFIE16_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE16_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `CFIE17` reader - Cancellation Finished Interrupt Enable 17"] +pub struct CFIE17_R(crate::FieldReader); +impl CFIE17_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE17_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE17_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE17` writer - Cancellation Finished Interrupt Enable 17"] +pub struct CFIE17_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE17_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `CFIE18` reader - Cancellation Finished Interrupt Enable 18"] +pub struct CFIE18_R(crate::FieldReader); +impl CFIE18_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE18_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE18_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE18` writer - Cancellation Finished Interrupt Enable 18"] +pub struct CFIE18_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE18_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `CFIE19` reader - Cancellation Finished Interrupt Enable 19"] +pub struct CFIE19_R(crate::FieldReader); +impl CFIE19_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE19_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE19_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE19` writer - Cancellation Finished Interrupt Enable 19"] +pub struct CFIE19_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE19_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `CFIE20` reader - Cancellation Finished Interrupt Enable 20"] +pub struct CFIE20_R(crate::FieldReader); +impl CFIE20_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE20_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE20_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE20` writer - Cancellation Finished Interrupt Enable 20"] +pub struct CFIE20_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE20_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `CFIE21` reader - Cancellation Finished Interrupt Enable 21"] +pub struct CFIE21_R(crate::FieldReader); +impl CFIE21_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE21_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE21_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE21` writer - Cancellation Finished Interrupt Enable 21"] +pub struct CFIE21_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE21_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `CFIE22` reader - Cancellation Finished Interrupt Enable 22"] +pub struct CFIE22_R(crate::FieldReader); +impl CFIE22_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE22_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE22_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE22` writer - Cancellation Finished Interrupt Enable 22"] +pub struct CFIE22_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE22_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `CFIE23` reader - Cancellation Finished Interrupt Enable 23"] +pub struct CFIE23_R(crate::FieldReader); +impl CFIE23_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE23_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE23_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE23` writer - Cancellation Finished Interrupt Enable 23"] +pub struct CFIE23_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE23_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `CFIE24` reader - Cancellation Finished Interrupt Enable 24"] +pub struct CFIE24_R(crate::FieldReader); +impl CFIE24_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE24_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE24_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE24` writer - Cancellation Finished Interrupt Enable 24"] +pub struct CFIE24_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE24_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `CFIE25` reader - Cancellation Finished Interrupt Enable 25"] +pub struct CFIE25_R(crate::FieldReader); +impl CFIE25_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE25_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE25_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE25` writer - Cancellation Finished Interrupt Enable 25"] +pub struct CFIE25_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE25_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `CFIE26` reader - Cancellation Finished Interrupt Enable 26"] +pub struct CFIE26_R(crate::FieldReader); +impl CFIE26_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE26_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE26_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE26` writer - Cancellation Finished Interrupt Enable 26"] +pub struct CFIE26_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE26_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `CFIE27` reader - Cancellation Finished Interrupt Enable 27"] +pub struct CFIE27_R(crate::FieldReader); +impl CFIE27_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE27_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE27_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE27` writer - Cancellation Finished Interrupt Enable 27"] +pub struct CFIE27_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE27_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +#[doc = "Field `CFIE28` reader - Cancellation Finished Interrupt Enable 28"] +pub struct CFIE28_R(crate::FieldReader); +impl CFIE28_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE28_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE28_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE28` writer - Cancellation Finished Interrupt Enable 28"] +pub struct CFIE28_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE28_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Field `CFIE29` reader - Cancellation Finished Interrupt Enable 29"] +pub struct CFIE29_R(crate::FieldReader); +impl CFIE29_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE29_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE29_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE29` writer - Cancellation Finished Interrupt Enable 29"] +pub struct CFIE29_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE29_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29); + self.w + } +} +#[doc = "Field `CFIE30` reader - Cancellation Finished Interrupt Enable 30"] +pub struct CFIE30_R(crate::FieldReader); +impl CFIE30_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE30_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE30_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE30` writer - Cancellation Finished Interrupt Enable 30"] +pub struct CFIE30_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE30_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +#[doc = "Field `CFIE31` reader - Cancellation Finished Interrupt Enable 31"] +pub struct CFIE31_R(crate::FieldReader); +impl CFIE31_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFIE31_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFIE31_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFIE31` writer - Cancellation Finished Interrupt Enable 31"] +pub struct CFIE31_W<'a> { + w: &'a mut W, +} +impl<'a> CFIE31_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bit 0 - Cancellation Finished Interrupt Enable 0"] + #[inline(always)] + pub fn cfie0(&self) -> CFIE0_R { + CFIE0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Cancellation Finished Interrupt Enable 1"] + #[inline(always)] + pub fn cfie1(&self) -> CFIE1_R { + CFIE1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Cancellation Finished Interrupt Enable 2"] + #[inline(always)] + pub fn cfie2(&self) -> CFIE2_R { + CFIE2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Cancellation Finished Interrupt Enable 3"] + #[inline(always)] + pub fn cfie3(&self) -> CFIE3_R { + CFIE3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Cancellation Finished Interrupt Enable 4"] + #[inline(always)] + pub fn cfie4(&self) -> CFIE4_R { + CFIE4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Cancellation Finished Interrupt Enable 5"] + #[inline(always)] + pub fn cfie5(&self) -> CFIE5_R { + CFIE5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Cancellation Finished Interrupt Enable 6"] + #[inline(always)] + pub fn cfie6(&self) -> CFIE6_R { + CFIE6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Cancellation Finished Interrupt Enable 7"] + #[inline(always)] + pub fn cfie7(&self) -> CFIE7_R { + CFIE7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Cancellation Finished Interrupt Enable 8"] + #[inline(always)] + pub fn cfie8(&self) -> CFIE8_R { + CFIE8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Cancellation Finished Interrupt Enable 9"] + #[inline(always)] + pub fn cfie9(&self) -> CFIE9_R { + CFIE9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Cancellation Finished Interrupt Enable 10"] + #[inline(always)] + pub fn cfie10(&self) -> CFIE10_R { + CFIE10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Cancellation Finished Interrupt Enable 11"] + #[inline(always)] + pub fn cfie11(&self) -> CFIE11_R { + CFIE11_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Cancellation Finished Interrupt Enable 12"] + #[inline(always)] + pub fn cfie12(&self) -> CFIE12_R { + CFIE12_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Cancellation Finished Interrupt Enable 13"] + #[inline(always)] + pub fn cfie13(&self) -> CFIE13_R { + CFIE13_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Cancellation Finished Interrupt Enable 14"] + #[inline(always)] + pub fn cfie14(&self) -> CFIE14_R { + CFIE14_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Cancellation Finished Interrupt Enable 15"] + #[inline(always)] + pub fn cfie15(&self) -> CFIE15_R { + CFIE15_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Cancellation Finished Interrupt Enable 16"] + #[inline(always)] + pub fn cfie16(&self) -> CFIE16_R { + CFIE16_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Cancellation Finished Interrupt Enable 17"] + #[inline(always)] + pub fn cfie17(&self) -> CFIE17_R { + CFIE17_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Cancellation Finished Interrupt Enable 18"] + #[inline(always)] + pub fn cfie18(&self) -> CFIE18_R { + CFIE18_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Cancellation Finished Interrupt Enable 19"] + #[inline(always)] + pub fn cfie19(&self) -> CFIE19_R { + CFIE19_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Cancellation Finished Interrupt Enable 20"] + #[inline(always)] + pub fn cfie20(&self) -> CFIE20_R { + CFIE20_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Cancellation Finished Interrupt Enable 21"] + #[inline(always)] + pub fn cfie21(&self) -> CFIE21_R { + CFIE21_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Cancellation Finished Interrupt Enable 22"] + #[inline(always)] + pub fn cfie22(&self) -> CFIE22_R { + CFIE22_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Cancellation Finished Interrupt Enable 23"] + #[inline(always)] + pub fn cfie23(&self) -> CFIE23_R { + CFIE23_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24 - Cancellation Finished Interrupt Enable 24"] + #[inline(always)] + pub fn cfie24(&self) -> CFIE24_R { + CFIE24_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Cancellation Finished Interrupt Enable 25"] + #[inline(always)] + pub fn cfie25(&self) -> CFIE25_R { + CFIE25_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Cancellation Finished Interrupt Enable 26"] + #[inline(always)] + pub fn cfie26(&self) -> CFIE26_R { + CFIE26_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Cancellation Finished Interrupt Enable 27"] + #[inline(always)] + pub fn cfie27(&self) -> CFIE27_R { + CFIE27_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28 - Cancellation Finished Interrupt Enable 28"] + #[inline(always)] + pub fn cfie28(&self) -> CFIE28_R { + CFIE28_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Cancellation Finished Interrupt Enable 29"] + #[inline(always)] + pub fn cfie29(&self) -> CFIE29_R { + CFIE29_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - Cancellation Finished Interrupt Enable 30"] + #[inline(always)] + pub fn cfie30(&self) -> CFIE30_R { + CFIE30_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 31 - Cancellation Finished Interrupt Enable 31"] + #[inline(always)] + pub fn cfie31(&self) -> CFIE31_R { + CFIE31_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Cancellation Finished Interrupt Enable 0"] + #[inline(always)] + pub fn cfie0(&mut self) -> CFIE0_W { + CFIE0_W { w: self } + } + #[doc = "Bit 1 - Cancellation Finished Interrupt Enable 1"] + #[inline(always)] + pub fn cfie1(&mut self) -> CFIE1_W { + CFIE1_W { w: self } + } + #[doc = "Bit 2 - Cancellation Finished Interrupt Enable 2"] + #[inline(always)] + pub fn cfie2(&mut self) -> CFIE2_W { + CFIE2_W { w: self } + } + #[doc = "Bit 3 - Cancellation Finished Interrupt Enable 3"] + #[inline(always)] + pub fn cfie3(&mut self) -> CFIE3_W { + CFIE3_W { w: self } + } + #[doc = "Bit 4 - Cancellation Finished Interrupt Enable 4"] + #[inline(always)] + pub fn cfie4(&mut self) -> CFIE4_W { + CFIE4_W { w: self } + } + #[doc = "Bit 5 - Cancellation Finished Interrupt Enable 5"] + #[inline(always)] + pub fn cfie5(&mut self) -> CFIE5_W { + CFIE5_W { w: self } + } + #[doc = "Bit 6 - Cancellation Finished Interrupt Enable 6"] + #[inline(always)] + pub fn cfie6(&mut self) -> CFIE6_W { + CFIE6_W { w: self } + } + #[doc = "Bit 7 - Cancellation Finished Interrupt Enable 7"] + #[inline(always)] + pub fn cfie7(&mut self) -> CFIE7_W { + CFIE7_W { w: self } + } + #[doc = "Bit 8 - Cancellation Finished Interrupt Enable 8"] + #[inline(always)] + pub fn cfie8(&mut self) -> CFIE8_W { + CFIE8_W { w: self } + } + #[doc = "Bit 9 - Cancellation Finished Interrupt Enable 9"] + #[inline(always)] + pub fn cfie9(&mut self) -> CFIE9_W { + CFIE9_W { w: self } + } + #[doc = "Bit 10 - Cancellation Finished Interrupt Enable 10"] + #[inline(always)] + pub fn cfie10(&mut self) -> CFIE10_W { + CFIE10_W { w: self } + } + #[doc = "Bit 11 - Cancellation Finished Interrupt Enable 11"] + #[inline(always)] + pub fn cfie11(&mut self) -> CFIE11_W { + CFIE11_W { w: self } + } + #[doc = "Bit 12 - Cancellation Finished Interrupt Enable 12"] + #[inline(always)] + pub fn cfie12(&mut self) -> CFIE12_W { + CFIE12_W { w: self } + } + #[doc = "Bit 13 - Cancellation Finished Interrupt Enable 13"] + #[inline(always)] + pub fn cfie13(&mut self) -> CFIE13_W { + CFIE13_W { w: self } + } + #[doc = "Bit 14 - Cancellation Finished Interrupt Enable 14"] + #[inline(always)] + pub fn cfie14(&mut self) -> CFIE14_W { + CFIE14_W { w: self } + } + #[doc = "Bit 15 - Cancellation Finished Interrupt Enable 15"] + #[inline(always)] + pub fn cfie15(&mut self) -> CFIE15_W { + CFIE15_W { w: self } + } + #[doc = "Bit 16 - Cancellation Finished Interrupt Enable 16"] + #[inline(always)] + pub fn cfie16(&mut self) -> CFIE16_W { + CFIE16_W { w: self } + } + #[doc = "Bit 17 - Cancellation Finished Interrupt Enable 17"] + #[inline(always)] + pub fn cfie17(&mut self) -> CFIE17_W { + CFIE17_W { w: self } + } + #[doc = "Bit 18 - Cancellation Finished Interrupt Enable 18"] + #[inline(always)] + pub fn cfie18(&mut self) -> CFIE18_W { + CFIE18_W { w: self } + } + #[doc = "Bit 19 - Cancellation Finished Interrupt Enable 19"] + #[inline(always)] + pub fn cfie19(&mut self) -> CFIE19_W { + CFIE19_W { w: self } + } + #[doc = "Bit 20 - Cancellation Finished Interrupt Enable 20"] + #[inline(always)] + pub fn cfie20(&mut self) -> CFIE20_W { + CFIE20_W { w: self } + } + #[doc = "Bit 21 - Cancellation Finished Interrupt Enable 21"] + #[inline(always)] + pub fn cfie21(&mut self) -> CFIE21_W { + CFIE21_W { w: self } + } + #[doc = "Bit 22 - Cancellation Finished Interrupt Enable 22"] + #[inline(always)] + pub fn cfie22(&mut self) -> CFIE22_W { + CFIE22_W { w: self } + } + #[doc = "Bit 23 - Cancellation Finished Interrupt Enable 23"] + #[inline(always)] + pub fn cfie23(&mut self) -> CFIE23_W { + CFIE23_W { w: self } + } + #[doc = "Bit 24 - Cancellation Finished Interrupt Enable 24"] + #[inline(always)] + pub fn cfie24(&mut self) -> CFIE24_W { + CFIE24_W { w: self } + } + #[doc = "Bit 25 - Cancellation Finished Interrupt Enable 25"] + #[inline(always)] + pub fn cfie25(&mut self) -> CFIE25_W { + CFIE25_W { w: self } + } + #[doc = "Bit 26 - Cancellation Finished Interrupt Enable 26"] + #[inline(always)] + pub fn cfie26(&mut self) -> CFIE26_W { + CFIE26_W { w: self } + } + #[doc = "Bit 27 - Cancellation Finished Interrupt Enable 27"] + #[inline(always)] + pub fn cfie27(&mut self) -> CFIE27_W { + CFIE27_W { w: self } + } + #[doc = "Bit 28 - Cancellation Finished Interrupt Enable 28"] + #[inline(always)] + pub fn cfie28(&mut self) -> CFIE28_W { + CFIE28_W { w: self } + } + #[doc = "Bit 29 - Cancellation Finished Interrupt Enable 29"] + #[inline(always)] + pub fn cfie29(&mut self) -> CFIE29_W { + CFIE29_W { w: self } + } + #[doc = "Bit 30 - Cancellation Finished Interrupt Enable 30"] + #[inline(always)] + pub fn cfie30(&mut self) -> CFIE30_W { + CFIE30_W { w: self } + } + #[doc = "Bit 31 - Cancellation Finished Interrupt Enable 31"] + #[inline(always)] + pub fn cfie31(&mut self) -> CFIE31_W { + CFIE31_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Tx Buffer Cancellation Finished Interrupt Enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txbcie](index.html) module"] +pub struct TXBCIE_SPEC; +impl crate::RegisterSpec for TXBCIE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [txbcie::R](R) reader structure"] +impl crate::Readable for TXBCIE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [txbcie::W](W) writer structure"] +impl crate::Writable for TXBCIE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TXBCIE to value 0"] +impl crate::Resettable for TXBCIE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/can0/txbcr.rs b/pac/atsamc21n/src/can0/txbcr.rs new file mode 100644 index 000000000000..e5d0e61de8c9 --- /dev/null +++ b/pac/atsamc21n/src/can0/txbcr.rs @@ -0,0 +1,1570 @@ +#[doc = "Register `TXBCR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TXBCR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CR0` reader - Cancellation Request 0"] +pub struct CR0_R(crate::FieldReader); +impl CR0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR0` writer - Cancellation Request 0"] +pub struct CR0_W<'a> { + w: &'a mut W, +} +impl<'a> CR0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `CR1` reader - Cancellation Request 1"] +pub struct CR1_R(crate::FieldReader); +impl CR1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR1` writer - Cancellation Request 1"] +pub struct CR1_W<'a> { + w: &'a mut W, +} +impl<'a> CR1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CR2` reader - Cancellation Request 2"] +pub struct CR2_R(crate::FieldReader); +impl CR2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR2` writer - Cancellation Request 2"] +pub struct CR2_W<'a> { + w: &'a mut W, +} +impl<'a> CR2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CR3` reader - Cancellation Request 3"] +pub struct CR3_R(crate::FieldReader); +impl CR3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR3` writer - Cancellation Request 3"] +pub struct CR3_W<'a> { + w: &'a mut W, +} +impl<'a> CR3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CR4` reader - Cancellation Request 4"] +pub struct CR4_R(crate::FieldReader); +impl CR4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR4` writer - Cancellation Request 4"] +pub struct CR4_W<'a> { + w: &'a mut W, +} +impl<'a> CR4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `CR5` reader - Cancellation Request 5"] +pub struct CR5_R(crate::FieldReader); +impl CR5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR5` writer - Cancellation Request 5"] +pub struct CR5_W<'a> { + w: &'a mut W, +} +impl<'a> CR5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `CR6` reader - Cancellation Request 6"] +pub struct CR6_R(crate::FieldReader); +impl CR6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR6` writer - Cancellation Request 6"] +pub struct CR6_W<'a> { + w: &'a mut W, +} +impl<'a> CR6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `CR7` reader - Cancellation Request 7"] +pub struct CR7_R(crate::FieldReader); +impl CR7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR7` writer - Cancellation Request 7"] +pub struct CR7_W<'a> { + w: &'a mut W, +} +impl<'a> CR7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CR8` reader - Cancellation Request 8"] +pub struct CR8_R(crate::FieldReader); +impl CR8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR8` writer - Cancellation Request 8"] +pub struct CR8_W<'a> { + w: &'a mut W, +} +impl<'a> CR8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `CR9` reader - Cancellation Request 9"] +pub struct CR9_R(crate::FieldReader); +impl CR9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR9` writer - Cancellation Request 9"] +pub struct CR9_W<'a> { + w: &'a mut W, +} +impl<'a> CR9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `CR10` reader - Cancellation Request 10"] +pub struct CR10_R(crate::FieldReader); +impl CR10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR10` writer - Cancellation Request 10"] +pub struct CR10_W<'a> { + w: &'a mut W, +} +impl<'a> CR10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `CR11` reader - Cancellation Request 11"] +pub struct CR11_R(crate::FieldReader); +impl CR11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR11` writer - Cancellation Request 11"] +pub struct CR11_W<'a> { + w: &'a mut W, +} +impl<'a> CR11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `CR12` reader - Cancellation Request 12"] +pub struct CR12_R(crate::FieldReader); +impl CR12_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR12_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR12_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR12` writer - Cancellation Request 12"] +pub struct CR12_W<'a> { + w: &'a mut W, +} +impl<'a> CR12_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `CR13` reader - Cancellation Request 13"] +pub struct CR13_R(crate::FieldReader); +impl CR13_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR13_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR13_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR13` writer - Cancellation Request 13"] +pub struct CR13_W<'a> { + w: &'a mut W, +} +impl<'a> CR13_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `CR14` reader - Cancellation Request 14"] +pub struct CR14_R(crate::FieldReader); +impl CR14_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR14_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR14_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR14` writer - Cancellation Request 14"] +pub struct CR14_W<'a> { + w: &'a mut W, +} +impl<'a> CR14_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `CR15` reader - Cancellation Request 15"] +pub struct CR15_R(crate::FieldReader); +impl CR15_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR15_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR15_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR15` writer - Cancellation Request 15"] +pub struct CR15_W<'a> { + w: &'a mut W, +} +impl<'a> CR15_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `CR16` reader - Cancellation Request 16"] +pub struct CR16_R(crate::FieldReader); +impl CR16_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR16_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR16_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR16` writer - Cancellation Request 16"] +pub struct CR16_W<'a> { + w: &'a mut W, +} +impl<'a> CR16_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `CR17` reader - Cancellation Request 17"] +pub struct CR17_R(crate::FieldReader); +impl CR17_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR17_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR17_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR17` writer - Cancellation Request 17"] +pub struct CR17_W<'a> { + w: &'a mut W, +} +impl<'a> CR17_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `CR18` reader - Cancellation Request 18"] +pub struct CR18_R(crate::FieldReader); +impl CR18_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR18_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR18_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR18` writer - Cancellation Request 18"] +pub struct CR18_W<'a> { + w: &'a mut W, +} +impl<'a> CR18_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `CR19` reader - Cancellation Request 19"] +pub struct CR19_R(crate::FieldReader); +impl CR19_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR19_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR19_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR19` writer - Cancellation Request 19"] +pub struct CR19_W<'a> { + w: &'a mut W, +} +impl<'a> CR19_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `CR20` reader - Cancellation Request 20"] +pub struct CR20_R(crate::FieldReader); +impl CR20_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR20_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR20_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR20` writer - Cancellation Request 20"] +pub struct CR20_W<'a> { + w: &'a mut W, +} +impl<'a> CR20_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `CR21` reader - Cancellation Request 21"] +pub struct CR21_R(crate::FieldReader); +impl CR21_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR21_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR21_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR21` writer - Cancellation Request 21"] +pub struct CR21_W<'a> { + w: &'a mut W, +} +impl<'a> CR21_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `CR22` reader - Cancellation Request 22"] +pub struct CR22_R(crate::FieldReader); +impl CR22_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR22_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR22_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR22` writer - Cancellation Request 22"] +pub struct CR22_W<'a> { + w: &'a mut W, +} +impl<'a> CR22_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `CR23` reader - Cancellation Request 23"] +pub struct CR23_R(crate::FieldReader); +impl CR23_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR23_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR23_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR23` writer - Cancellation Request 23"] +pub struct CR23_W<'a> { + w: &'a mut W, +} +impl<'a> CR23_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `CR24` reader - Cancellation Request 24"] +pub struct CR24_R(crate::FieldReader); +impl CR24_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR24_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR24_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR24` writer - Cancellation Request 24"] +pub struct CR24_W<'a> { + w: &'a mut W, +} +impl<'a> CR24_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `CR25` reader - Cancellation Request 25"] +pub struct CR25_R(crate::FieldReader); +impl CR25_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR25_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR25_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR25` writer - Cancellation Request 25"] +pub struct CR25_W<'a> { + w: &'a mut W, +} +impl<'a> CR25_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `CR26` reader - Cancellation Request 26"] +pub struct CR26_R(crate::FieldReader); +impl CR26_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR26_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR26_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR26` writer - Cancellation Request 26"] +pub struct CR26_W<'a> { + w: &'a mut W, +} +impl<'a> CR26_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `CR27` reader - Cancellation Request 27"] +pub struct CR27_R(crate::FieldReader); +impl CR27_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR27_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR27_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR27` writer - Cancellation Request 27"] +pub struct CR27_W<'a> { + w: &'a mut W, +} +impl<'a> CR27_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +#[doc = "Field `CR28` reader - Cancellation Request 28"] +pub struct CR28_R(crate::FieldReader); +impl CR28_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR28_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR28_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR28` writer - Cancellation Request 28"] +pub struct CR28_W<'a> { + w: &'a mut W, +} +impl<'a> CR28_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Field `CR29` reader - Cancellation Request 29"] +pub struct CR29_R(crate::FieldReader); +impl CR29_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR29_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR29_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR29` writer - Cancellation Request 29"] +pub struct CR29_W<'a> { + w: &'a mut W, +} +impl<'a> CR29_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29); + self.w + } +} +#[doc = "Field `CR30` reader - Cancellation Request 30"] +pub struct CR30_R(crate::FieldReader); +impl CR30_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR30_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR30_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR30` writer - Cancellation Request 30"] +pub struct CR30_W<'a> { + w: &'a mut W, +} +impl<'a> CR30_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +#[doc = "Field `CR31` reader - Cancellation Request 31"] +pub struct CR31_R(crate::FieldReader); +impl CR31_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CR31_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR31_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR31` writer - Cancellation Request 31"] +pub struct CR31_W<'a> { + w: &'a mut W, +} +impl<'a> CR31_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bit 0 - Cancellation Request 0"] + #[inline(always)] + pub fn cr0(&self) -> CR0_R { + CR0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Cancellation Request 1"] + #[inline(always)] + pub fn cr1(&self) -> CR1_R { + CR1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Cancellation Request 2"] + #[inline(always)] + pub fn cr2(&self) -> CR2_R { + CR2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Cancellation Request 3"] + #[inline(always)] + pub fn cr3(&self) -> CR3_R { + CR3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Cancellation Request 4"] + #[inline(always)] + pub fn cr4(&self) -> CR4_R { + CR4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Cancellation Request 5"] + #[inline(always)] + pub fn cr5(&self) -> CR5_R { + CR5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Cancellation Request 6"] + #[inline(always)] + pub fn cr6(&self) -> CR6_R { + CR6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Cancellation Request 7"] + #[inline(always)] + pub fn cr7(&self) -> CR7_R { + CR7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Cancellation Request 8"] + #[inline(always)] + pub fn cr8(&self) -> CR8_R { + CR8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Cancellation Request 9"] + #[inline(always)] + pub fn cr9(&self) -> CR9_R { + CR9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Cancellation Request 10"] + #[inline(always)] + pub fn cr10(&self) -> CR10_R { + CR10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Cancellation Request 11"] + #[inline(always)] + pub fn cr11(&self) -> CR11_R { + CR11_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Cancellation Request 12"] + #[inline(always)] + pub fn cr12(&self) -> CR12_R { + CR12_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Cancellation Request 13"] + #[inline(always)] + pub fn cr13(&self) -> CR13_R { + CR13_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Cancellation Request 14"] + #[inline(always)] + pub fn cr14(&self) -> CR14_R { + CR14_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Cancellation Request 15"] + #[inline(always)] + pub fn cr15(&self) -> CR15_R { + CR15_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Cancellation Request 16"] + #[inline(always)] + pub fn cr16(&self) -> CR16_R { + CR16_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Cancellation Request 17"] + #[inline(always)] + pub fn cr17(&self) -> CR17_R { + CR17_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Cancellation Request 18"] + #[inline(always)] + pub fn cr18(&self) -> CR18_R { + CR18_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Cancellation Request 19"] + #[inline(always)] + pub fn cr19(&self) -> CR19_R { + CR19_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Cancellation Request 20"] + #[inline(always)] + pub fn cr20(&self) -> CR20_R { + CR20_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Cancellation Request 21"] + #[inline(always)] + pub fn cr21(&self) -> CR21_R { + CR21_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Cancellation Request 22"] + #[inline(always)] + pub fn cr22(&self) -> CR22_R { + CR22_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Cancellation Request 23"] + #[inline(always)] + pub fn cr23(&self) -> CR23_R { + CR23_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24 - Cancellation Request 24"] + #[inline(always)] + pub fn cr24(&self) -> CR24_R { + CR24_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Cancellation Request 25"] + #[inline(always)] + pub fn cr25(&self) -> CR25_R { + CR25_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Cancellation Request 26"] + #[inline(always)] + pub fn cr26(&self) -> CR26_R { + CR26_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Cancellation Request 27"] + #[inline(always)] + pub fn cr27(&self) -> CR27_R { + CR27_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28 - Cancellation Request 28"] + #[inline(always)] + pub fn cr28(&self) -> CR28_R { + CR28_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Cancellation Request 29"] + #[inline(always)] + pub fn cr29(&self) -> CR29_R { + CR29_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - Cancellation Request 30"] + #[inline(always)] + pub fn cr30(&self) -> CR30_R { + CR30_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 31 - Cancellation Request 31"] + #[inline(always)] + pub fn cr31(&self) -> CR31_R { + CR31_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Cancellation Request 0"] + #[inline(always)] + pub fn cr0(&mut self) -> CR0_W { + CR0_W { w: self } + } + #[doc = "Bit 1 - Cancellation Request 1"] + #[inline(always)] + pub fn cr1(&mut self) -> CR1_W { + CR1_W { w: self } + } + #[doc = "Bit 2 - Cancellation Request 2"] + #[inline(always)] + pub fn cr2(&mut self) -> CR2_W { + CR2_W { w: self } + } + #[doc = "Bit 3 - Cancellation Request 3"] + #[inline(always)] + pub fn cr3(&mut self) -> CR3_W { + CR3_W { w: self } + } + #[doc = "Bit 4 - Cancellation Request 4"] + #[inline(always)] + pub fn cr4(&mut self) -> CR4_W { + CR4_W { w: self } + } + #[doc = "Bit 5 - Cancellation Request 5"] + #[inline(always)] + pub fn cr5(&mut self) -> CR5_W { + CR5_W { w: self } + } + #[doc = "Bit 6 - Cancellation Request 6"] + #[inline(always)] + pub fn cr6(&mut self) -> CR6_W { + CR6_W { w: self } + } + #[doc = "Bit 7 - Cancellation Request 7"] + #[inline(always)] + pub fn cr7(&mut self) -> CR7_W { + CR7_W { w: self } + } + #[doc = "Bit 8 - Cancellation Request 8"] + #[inline(always)] + pub fn cr8(&mut self) -> CR8_W { + CR8_W { w: self } + } + #[doc = "Bit 9 - Cancellation Request 9"] + #[inline(always)] + pub fn cr9(&mut self) -> CR9_W { + CR9_W { w: self } + } + #[doc = "Bit 10 - Cancellation Request 10"] + #[inline(always)] + pub fn cr10(&mut self) -> CR10_W { + CR10_W { w: self } + } + #[doc = "Bit 11 - Cancellation Request 11"] + #[inline(always)] + pub fn cr11(&mut self) -> CR11_W { + CR11_W { w: self } + } + #[doc = "Bit 12 - Cancellation Request 12"] + #[inline(always)] + pub fn cr12(&mut self) -> CR12_W { + CR12_W { w: self } + } + #[doc = "Bit 13 - Cancellation Request 13"] + #[inline(always)] + pub fn cr13(&mut self) -> CR13_W { + CR13_W { w: self } + } + #[doc = "Bit 14 - Cancellation Request 14"] + #[inline(always)] + pub fn cr14(&mut self) -> CR14_W { + CR14_W { w: self } + } + #[doc = "Bit 15 - Cancellation Request 15"] + #[inline(always)] + pub fn cr15(&mut self) -> CR15_W { + CR15_W { w: self } + } + #[doc = "Bit 16 - Cancellation Request 16"] + #[inline(always)] + pub fn cr16(&mut self) -> CR16_W { + CR16_W { w: self } + } + #[doc = "Bit 17 - Cancellation Request 17"] + #[inline(always)] + pub fn cr17(&mut self) -> CR17_W { + CR17_W { w: self } + } + #[doc = "Bit 18 - Cancellation Request 18"] + #[inline(always)] + pub fn cr18(&mut self) -> CR18_W { + CR18_W { w: self } + } + #[doc = "Bit 19 - Cancellation Request 19"] + #[inline(always)] + pub fn cr19(&mut self) -> CR19_W { + CR19_W { w: self } + } + #[doc = "Bit 20 - Cancellation Request 20"] + #[inline(always)] + pub fn cr20(&mut self) -> CR20_W { + CR20_W { w: self } + } + #[doc = "Bit 21 - Cancellation Request 21"] + #[inline(always)] + pub fn cr21(&mut self) -> CR21_W { + CR21_W { w: self } + } + #[doc = "Bit 22 - Cancellation Request 22"] + #[inline(always)] + pub fn cr22(&mut self) -> CR22_W { + CR22_W { w: self } + } + #[doc = "Bit 23 - Cancellation Request 23"] + #[inline(always)] + pub fn cr23(&mut self) -> CR23_W { + CR23_W { w: self } + } + #[doc = "Bit 24 - Cancellation Request 24"] + #[inline(always)] + pub fn cr24(&mut self) -> CR24_W { + CR24_W { w: self } + } + #[doc = "Bit 25 - Cancellation Request 25"] + #[inline(always)] + pub fn cr25(&mut self) -> CR25_W { + CR25_W { w: self } + } + #[doc = "Bit 26 - Cancellation Request 26"] + #[inline(always)] + pub fn cr26(&mut self) -> CR26_W { + CR26_W { w: self } + } + #[doc = "Bit 27 - Cancellation Request 27"] + #[inline(always)] + pub fn cr27(&mut self) -> CR27_W { + CR27_W { w: self } + } + #[doc = "Bit 28 - Cancellation Request 28"] + #[inline(always)] + pub fn cr28(&mut self) -> CR28_W { + CR28_W { w: self } + } + #[doc = "Bit 29 - Cancellation Request 29"] + #[inline(always)] + pub fn cr29(&mut self) -> CR29_W { + CR29_W { w: self } + } + #[doc = "Bit 30 - Cancellation Request 30"] + #[inline(always)] + pub fn cr30(&mut self) -> CR30_W { + CR30_W { w: self } + } + #[doc = "Bit 31 - Cancellation Request 31"] + #[inline(always)] + pub fn cr31(&mut self) -> CR31_W { + CR31_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Tx Buffer Cancellation Request\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txbcr](index.html) module"] +pub struct TXBCR_SPEC; +impl crate::RegisterSpec for TXBCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [txbcr::R](R) reader structure"] +impl crate::Readable for TXBCR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [txbcr::W](W) writer structure"] +impl crate::Writable for TXBCR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TXBCR to value 0"] +impl crate::Resettable for TXBCR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/can0/txbrp.rs b/pac/atsamc21n/src/can0/txbrp.rs new file mode 100644 index 000000000000..9be5da39419d --- /dev/null +++ b/pac/atsamc21n/src/can0/txbrp.rs @@ -0,0 +1,673 @@ +#[doc = "Register `TXBRP` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `TRP0` reader - Transmission Request Pending 0"] +pub struct TRP0_R(crate::FieldReader); +impl TRP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP1` reader - Transmission Request Pending 1"] +pub struct TRP1_R(crate::FieldReader); +impl TRP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP2` reader - Transmission Request Pending 2"] +pub struct TRP2_R(crate::FieldReader); +impl TRP2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP3` reader - Transmission Request Pending 3"] +pub struct TRP3_R(crate::FieldReader); +impl TRP3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP4` reader - Transmission Request Pending 4"] +pub struct TRP4_R(crate::FieldReader); +impl TRP4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP5` reader - Transmission Request Pending 5"] +pub struct TRP5_R(crate::FieldReader); +impl TRP5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP6` reader - Transmission Request Pending 6"] +pub struct TRP6_R(crate::FieldReader); +impl TRP6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP7` reader - Transmission Request Pending 7"] +pub struct TRP7_R(crate::FieldReader); +impl TRP7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP8` reader - Transmission Request Pending 8"] +pub struct TRP8_R(crate::FieldReader); +impl TRP8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP9` reader - Transmission Request Pending 9"] +pub struct TRP9_R(crate::FieldReader); +impl TRP9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP10` reader - Transmission Request Pending 10"] +pub struct TRP10_R(crate::FieldReader); +impl TRP10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP11` reader - Transmission Request Pending 11"] +pub struct TRP11_R(crate::FieldReader); +impl TRP11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP12` reader - Transmission Request Pending 12"] +pub struct TRP12_R(crate::FieldReader); +impl TRP12_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP12_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP12_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP13` reader - Transmission Request Pending 13"] +pub struct TRP13_R(crate::FieldReader); +impl TRP13_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP13_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP13_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP14` reader - Transmission Request Pending 14"] +pub struct TRP14_R(crate::FieldReader); +impl TRP14_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP14_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP14_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP15` reader - Transmission Request Pending 15"] +pub struct TRP15_R(crate::FieldReader); +impl TRP15_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP15_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP15_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP16` reader - Transmission Request Pending 16"] +pub struct TRP16_R(crate::FieldReader); +impl TRP16_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP16_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP16_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP17` reader - Transmission Request Pending 17"] +pub struct TRP17_R(crate::FieldReader); +impl TRP17_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP17_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP17_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP18` reader - Transmission Request Pending 18"] +pub struct TRP18_R(crate::FieldReader); +impl TRP18_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP18_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP18_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP19` reader - Transmission Request Pending 19"] +pub struct TRP19_R(crate::FieldReader); +impl TRP19_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP19_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP19_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP20` reader - Transmission Request Pending 20"] +pub struct TRP20_R(crate::FieldReader); +impl TRP20_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP20_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP20_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP21` reader - Transmission Request Pending 21"] +pub struct TRP21_R(crate::FieldReader); +impl TRP21_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP21_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP21_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP22` reader - Transmission Request Pending 22"] +pub struct TRP22_R(crate::FieldReader); +impl TRP22_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP22_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP22_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP23` reader - Transmission Request Pending 23"] +pub struct TRP23_R(crate::FieldReader); +impl TRP23_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP23_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP23_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP24` reader - Transmission Request Pending 24"] +pub struct TRP24_R(crate::FieldReader); +impl TRP24_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP24_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP24_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP25` reader - Transmission Request Pending 25"] +pub struct TRP25_R(crate::FieldReader); +impl TRP25_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP25_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP25_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP26` reader - Transmission Request Pending 26"] +pub struct TRP26_R(crate::FieldReader); +impl TRP26_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP26_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP26_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP27` reader - Transmission Request Pending 27"] +pub struct TRP27_R(crate::FieldReader); +impl TRP27_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP27_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP27_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP28` reader - Transmission Request Pending 28"] +pub struct TRP28_R(crate::FieldReader); +impl TRP28_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP28_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP28_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP29` reader - Transmission Request Pending 29"] +pub struct TRP29_R(crate::FieldReader); +impl TRP29_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP29_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP29_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP30` reader - Transmission Request Pending 30"] +pub struct TRP30_R(crate::FieldReader); +impl TRP30_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP30_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP30_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRP31` reader - Transmission Request Pending 31"] +pub struct TRP31_R(crate::FieldReader); +impl TRP31_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRP31_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRP31_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Transmission Request Pending 0"] + #[inline(always)] + pub fn trp0(&self) -> TRP0_R { + TRP0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmission Request Pending 1"] + #[inline(always)] + pub fn trp1(&self) -> TRP1_R { + TRP1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Transmission Request Pending 2"] + #[inline(always)] + pub fn trp2(&self) -> TRP2_R { + TRP2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Transmission Request Pending 3"] + #[inline(always)] + pub fn trp3(&self) -> TRP3_R { + TRP3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Transmission Request Pending 4"] + #[inline(always)] + pub fn trp4(&self) -> TRP4_R { + TRP4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Transmission Request Pending 5"] + #[inline(always)] + pub fn trp5(&self) -> TRP5_R { + TRP5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Transmission Request Pending 6"] + #[inline(always)] + pub fn trp6(&self) -> TRP6_R { + TRP6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Transmission Request Pending 7"] + #[inline(always)] + pub fn trp7(&self) -> TRP7_R { + TRP7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Transmission Request Pending 8"] + #[inline(always)] + pub fn trp8(&self) -> TRP8_R { + TRP8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Transmission Request Pending 9"] + #[inline(always)] + pub fn trp9(&self) -> TRP9_R { + TRP9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Transmission Request Pending 10"] + #[inline(always)] + pub fn trp10(&self) -> TRP10_R { + TRP10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Transmission Request Pending 11"] + #[inline(always)] + pub fn trp11(&self) -> TRP11_R { + TRP11_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Transmission Request Pending 12"] + #[inline(always)] + pub fn trp12(&self) -> TRP12_R { + TRP12_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Transmission Request Pending 13"] + #[inline(always)] + pub fn trp13(&self) -> TRP13_R { + TRP13_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Transmission Request Pending 14"] + #[inline(always)] + pub fn trp14(&self) -> TRP14_R { + TRP14_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Transmission Request Pending 15"] + #[inline(always)] + pub fn trp15(&self) -> TRP15_R { + TRP15_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Transmission Request Pending 16"] + #[inline(always)] + pub fn trp16(&self) -> TRP16_R { + TRP16_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Transmission Request Pending 17"] + #[inline(always)] + pub fn trp17(&self) -> TRP17_R { + TRP17_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Transmission Request Pending 18"] + #[inline(always)] + pub fn trp18(&self) -> TRP18_R { + TRP18_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Transmission Request Pending 19"] + #[inline(always)] + pub fn trp19(&self) -> TRP19_R { + TRP19_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Transmission Request Pending 20"] + #[inline(always)] + pub fn trp20(&self) -> TRP20_R { + TRP20_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Transmission Request Pending 21"] + #[inline(always)] + pub fn trp21(&self) -> TRP21_R { + TRP21_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Transmission Request Pending 22"] + #[inline(always)] + pub fn trp22(&self) -> TRP22_R { + TRP22_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Transmission Request Pending 23"] + #[inline(always)] + pub fn trp23(&self) -> TRP23_R { + TRP23_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24 - Transmission Request Pending 24"] + #[inline(always)] + pub fn trp24(&self) -> TRP24_R { + TRP24_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Transmission Request Pending 25"] + #[inline(always)] + pub fn trp25(&self) -> TRP25_R { + TRP25_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Transmission Request Pending 26"] + #[inline(always)] + pub fn trp26(&self) -> TRP26_R { + TRP26_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Transmission Request Pending 27"] + #[inline(always)] + pub fn trp27(&self) -> TRP27_R { + TRP27_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28 - Transmission Request Pending 28"] + #[inline(always)] + pub fn trp28(&self) -> TRP28_R { + TRP28_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Transmission Request Pending 29"] + #[inline(always)] + pub fn trp29(&self) -> TRP29_R { + TRP29_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - Transmission Request Pending 30"] + #[inline(always)] + pub fn trp30(&self) -> TRP30_R { + TRP30_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 31 - Transmission Request Pending 31"] + #[inline(always)] + pub fn trp31(&self) -> TRP31_R { + TRP31_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +#[doc = "Tx Buffer Request Pending\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txbrp](index.html) module"] +pub struct TXBRP_SPEC; +impl crate::RegisterSpec for TXBRP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [txbrp::R](R) reader structure"] +impl crate::Readable for TXBRP_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets TXBRP to value 0"] +impl crate::Resettable for TXBRP_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/can0/txbtie.rs b/pac/atsamc21n/src/can0/txbtie.rs new file mode 100644 index 000000000000..ed808faba7a1 --- /dev/null +++ b/pac/atsamc21n/src/can0/txbtie.rs @@ -0,0 +1,1570 @@ +#[doc = "Register `TXBTIE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TXBTIE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TIE0` reader - Transmission Interrupt Enable 0"] +pub struct TIE0_R(crate::FieldReader); +impl TIE0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE0` writer - Transmission Interrupt Enable 0"] +pub struct TIE0_W<'a> { + w: &'a mut W, +} +impl<'a> TIE0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `TIE1` reader - Transmission Interrupt Enable 1"] +pub struct TIE1_R(crate::FieldReader); +impl TIE1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE1` writer - Transmission Interrupt Enable 1"] +pub struct TIE1_W<'a> { + w: &'a mut W, +} +impl<'a> TIE1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `TIE2` reader - Transmission Interrupt Enable 2"] +pub struct TIE2_R(crate::FieldReader); +impl TIE2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE2` writer - Transmission Interrupt Enable 2"] +pub struct TIE2_W<'a> { + w: &'a mut W, +} +impl<'a> TIE2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `TIE3` reader - Transmission Interrupt Enable 3"] +pub struct TIE3_R(crate::FieldReader); +impl TIE3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE3` writer - Transmission Interrupt Enable 3"] +pub struct TIE3_W<'a> { + w: &'a mut W, +} +impl<'a> TIE3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `TIE4` reader - Transmission Interrupt Enable 4"] +pub struct TIE4_R(crate::FieldReader); +impl TIE4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE4` writer - Transmission Interrupt Enable 4"] +pub struct TIE4_W<'a> { + w: &'a mut W, +} +impl<'a> TIE4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `TIE5` reader - Transmission Interrupt Enable 5"] +pub struct TIE5_R(crate::FieldReader); +impl TIE5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE5` writer - Transmission Interrupt Enable 5"] +pub struct TIE5_W<'a> { + w: &'a mut W, +} +impl<'a> TIE5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `TIE6` reader - Transmission Interrupt Enable 6"] +pub struct TIE6_R(crate::FieldReader); +impl TIE6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE6` writer - Transmission Interrupt Enable 6"] +pub struct TIE6_W<'a> { + w: &'a mut W, +} +impl<'a> TIE6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `TIE7` reader - Transmission Interrupt Enable 7"] +pub struct TIE7_R(crate::FieldReader); +impl TIE7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE7` writer - Transmission Interrupt Enable 7"] +pub struct TIE7_W<'a> { + w: &'a mut W, +} +impl<'a> TIE7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `TIE8` reader - Transmission Interrupt Enable 8"] +pub struct TIE8_R(crate::FieldReader); +impl TIE8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE8` writer - Transmission Interrupt Enable 8"] +pub struct TIE8_W<'a> { + w: &'a mut W, +} +impl<'a> TIE8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `TIE9` reader - Transmission Interrupt Enable 9"] +pub struct TIE9_R(crate::FieldReader); +impl TIE9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE9` writer - Transmission Interrupt Enable 9"] +pub struct TIE9_W<'a> { + w: &'a mut W, +} +impl<'a> TIE9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `TIE10` reader - Transmission Interrupt Enable 10"] +pub struct TIE10_R(crate::FieldReader); +impl TIE10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE10` writer - Transmission Interrupt Enable 10"] +pub struct TIE10_W<'a> { + w: &'a mut W, +} +impl<'a> TIE10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `TIE11` reader - Transmission Interrupt Enable 11"] +pub struct TIE11_R(crate::FieldReader); +impl TIE11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE11` writer - Transmission Interrupt Enable 11"] +pub struct TIE11_W<'a> { + w: &'a mut W, +} +impl<'a> TIE11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `TIE12` reader - Transmission Interrupt Enable 12"] +pub struct TIE12_R(crate::FieldReader); +impl TIE12_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE12_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE12_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE12` writer - Transmission Interrupt Enable 12"] +pub struct TIE12_W<'a> { + w: &'a mut W, +} +impl<'a> TIE12_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `TIE13` reader - Transmission Interrupt Enable 13"] +pub struct TIE13_R(crate::FieldReader); +impl TIE13_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE13_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE13_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE13` writer - Transmission Interrupt Enable 13"] +pub struct TIE13_W<'a> { + w: &'a mut W, +} +impl<'a> TIE13_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `TIE14` reader - Transmission Interrupt Enable 14"] +pub struct TIE14_R(crate::FieldReader); +impl TIE14_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE14_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE14_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE14` writer - Transmission Interrupt Enable 14"] +pub struct TIE14_W<'a> { + w: &'a mut W, +} +impl<'a> TIE14_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `TIE15` reader - Transmission Interrupt Enable 15"] +pub struct TIE15_R(crate::FieldReader); +impl TIE15_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE15_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE15_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE15` writer - Transmission Interrupt Enable 15"] +pub struct TIE15_W<'a> { + w: &'a mut W, +} +impl<'a> TIE15_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `TIE16` reader - Transmission Interrupt Enable 16"] +pub struct TIE16_R(crate::FieldReader); +impl TIE16_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE16_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE16_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE16` writer - Transmission Interrupt Enable 16"] +pub struct TIE16_W<'a> { + w: &'a mut W, +} +impl<'a> TIE16_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `TIE17` reader - Transmission Interrupt Enable 17"] +pub struct TIE17_R(crate::FieldReader); +impl TIE17_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE17_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE17_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE17` writer - Transmission Interrupt Enable 17"] +pub struct TIE17_W<'a> { + w: &'a mut W, +} +impl<'a> TIE17_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `TIE18` reader - Transmission Interrupt Enable 18"] +pub struct TIE18_R(crate::FieldReader); +impl TIE18_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE18_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE18_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE18` writer - Transmission Interrupt Enable 18"] +pub struct TIE18_W<'a> { + w: &'a mut W, +} +impl<'a> TIE18_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `TIE19` reader - Transmission Interrupt Enable 19"] +pub struct TIE19_R(crate::FieldReader); +impl TIE19_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE19_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE19_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE19` writer - Transmission Interrupt Enable 19"] +pub struct TIE19_W<'a> { + w: &'a mut W, +} +impl<'a> TIE19_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `TIE20` reader - Transmission Interrupt Enable 20"] +pub struct TIE20_R(crate::FieldReader); +impl TIE20_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE20_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE20_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE20` writer - Transmission Interrupt Enable 20"] +pub struct TIE20_W<'a> { + w: &'a mut W, +} +impl<'a> TIE20_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `TIE21` reader - Transmission Interrupt Enable 21"] +pub struct TIE21_R(crate::FieldReader); +impl TIE21_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE21_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE21_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE21` writer - Transmission Interrupt Enable 21"] +pub struct TIE21_W<'a> { + w: &'a mut W, +} +impl<'a> TIE21_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `TIE22` reader - Transmission Interrupt Enable 22"] +pub struct TIE22_R(crate::FieldReader); +impl TIE22_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE22_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE22_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE22` writer - Transmission Interrupt Enable 22"] +pub struct TIE22_W<'a> { + w: &'a mut W, +} +impl<'a> TIE22_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `TIE23` reader - Transmission Interrupt Enable 23"] +pub struct TIE23_R(crate::FieldReader); +impl TIE23_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE23_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE23_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE23` writer - Transmission Interrupt Enable 23"] +pub struct TIE23_W<'a> { + w: &'a mut W, +} +impl<'a> TIE23_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `TIE24` reader - Transmission Interrupt Enable 24"] +pub struct TIE24_R(crate::FieldReader); +impl TIE24_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE24_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE24_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE24` writer - Transmission Interrupt Enable 24"] +pub struct TIE24_W<'a> { + w: &'a mut W, +} +impl<'a> TIE24_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `TIE25` reader - Transmission Interrupt Enable 25"] +pub struct TIE25_R(crate::FieldReader); +impl TIE25_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE25_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE25_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE25` writer - Transmission Interrupt Enable 25"] +pub struct TIE25_W<'a> { + w: &'a mut W, +} +impl<'a> TIE25_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `TIE26` reader - Transmission Interrupt Enable 26"] +pub struct TIE26_R(crate::FieldReader); +impl TIE26_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE26_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE26_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE26` writer - Transmission Interrupt Enable 26"] +pub struct TIE26_W<'a> { + w: &'a mut W, +} +impl<'a> TIE26_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `TIE27` reader - Transmission Interrupt Enable 27"] +pub struct TIE27_R(crate::FieldReader); +impl TIE27_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE27_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE27_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE27` writer - Transmission Interrupt Enable 27"] +pub struct TIE27_W<'a> { + w: &'a mut W, +} +impl<'a> TIE27_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +#[doc = "Field `TIE28` reader - Transmission Interrupt Enable 28"] +pub struct TIE28_R(crate::FieldReader); +impl TIE28_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE28_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE28_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE28` writer - Transmission Interrupt Enable 28"] +pub struct TIE28_W<'a> { + w: &'a mut W, +} +impl<'a> TIE28_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Field `TIE29` reader - Transmission Interrupt Enable 29"] +pub struct TIE29_R(crate::FieldReader); +impl TIE29_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE29_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE29_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE29` writer - Transmission Interrupt Enable 29"] +pub struct TIE29_W<'a> { + w: &'a mut W, +} +impl<'a> TIE29_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29); + self.w + } +} +#[doc = "Field `TIE30` reader - Transmission Interrupt Enable 30"] +pub struct TIE30_R(crate::FieldReader); +impl TIE30_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE30_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE30_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE30` writer - Transmission Interrupt Enable 30"] +pub struct TIE30_W<'a> { + w: &'a mut W, +} +impl<'a> TIE30_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +#[doc = "Field `TIE31` reader - Transmission Interrupt Enable 31"] +pub struct TIE31_R(crate::FieldReader); +impl TIE31_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE31_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE31_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE31` writer - Transmission Interrupt Enable 31"] +pub struct TIE31_W<'a> { + w: &'a mut W, +} +impl<'a> TIE31_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bit 0 - Transmission Interrupt Enable 0"] + #[inline(always)] + pub fn tie0(&self) -> TIE0_R { + TIE0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmission Interrupt Enable 1"] + #[inline(always)] + pub fn tie1(&self) -> TIE1_R { + TIE1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Transmission Interrupt Enable 2"] + #[inline(always)] + pub fn tie2(&self) -> TIE2_R { + TIE2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Transmission Interrupt Enable 3"] + #[inline(always)] + pub fn tie3(&self) -> TIE3_R { + TIE3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Transmission Interrupt Enable 4"] + #[inline(always)] + pub fn tie4(&self) -> TIE4_R { + TIE4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Transmission Interrupt Enable 5"] + #[inline(always)] + pub fn tie5(&self) -> TIE5_R { + TIE5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Transmission Interrupt Enable 6"] + #[inline(always)] + pub fn tie6(&self) -> TIE6_R { + TIE6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Transmission Interrupt Enable 7"] + #[inline(always)] + pub fn tie7(&self) -> TIE7_R { + TIE7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Transmission Interrupt Enable 8"] + #[inline(always)] + pub fn tie8(&self) -> TIE8_R { + TIE8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Transmission Interrupt Enable 9"] + #[inline(always)] + pub fn tie9(&self) -> TIE9_R { + TIE9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Transmission Interrupt Enable 10"] + #[inline(always)] + pub fn tie10(&self) -> TIE10_R { + TIE10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Transmission Interrupt Enable 11"] + #[inline(always)] + pub fn tie11(&self) -> TIE11_R { + TIE11_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Transmission Interrupt Enable 12"] + #[inline(always)] + pub fn tie12(&self) -> TIE12_R { + TIE12_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Transmission Interrupt Enable 13"] + #[inline(always)] + pub fn tie13(&self) -> TIE13_R { + TIE13_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Transmission Interrupt Enable 14"] + #[inline(always)] + pub fn tie14(&self) -> TIE14_R { + TIE14_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Transmission Interrupt Enable 15"] + #[inline(always)] + pub fn tie15(&self) -> TIE15_R { + TIE15_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Transmission Interrupt Enable 16"] + #[inline(always)] + pub fn tie16(&self) -> TIE16_R { + TIE16_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Transmission Interrupt Enable 17"] + #[inline(always)] + pub fn tie17(&self) -> TIE17_R { + TIE17_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Transmission Interrupt Enable 18"] + #[inline(always)] + pub fn tie18(&self) -> TIE18_R { + TIE18_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Transmission Interrupt Enable 19"] + #[inline(always)] + pub fn tie19(&self) -> TIE19_R { + TIE19_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Transmission Interrupt Enable 20"] + #[inline(always)] + pub fn tie20(&self) -> TIE20_R { + TIE20_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Transmission Interrupt Enable 21"] + #[inline(always)] + pub fn tie21(&self) -> TIE21_R { + TIE21_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Transmission Interrupt Enable 22"] + #[inline(always)] + pub fn tie22(&self) -> TIE22_R { + TIE22_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Transmission Interrupt Enable 23"] + #[inline(always)] + pub fn tie23(&self) -> TIE23_R { + TIE23_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24 - Transmission Interrupt Enable 24"] + #[inline(always)] + pub fn tie24(&self) -> TIE24_R { + TIE24_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Transmission Interrupt Enable 25"] + #[inline(always)] + pub fn tie25(&self) -> TIE25_R { + TIE25_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Transmission Interrupt Enable 26"] + #[inline(always)] + pub fn tie26(&self) -> TIE26_R { + TIE26_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Transmission Interrupt Enable 27"] + #[inline(always)] + pub fn tie27(&self) -> TIE27_R { + TIE27_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28 - Transmission Interrupt Enable 28"] + #[inline(always)] + pub fn tie28(&self) -> TIE28_R { + TIE28_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Transmission Interrupt Enable 29"] + #[inline(always)] + pub fn tie29(&self) -> TIE29_R { + TIE29_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - Transmission Interrupt Enable 30"] + #[inline(always)] + pub fn tie30(&self) -> TIE30_R { + TIE30_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 31 - Transmission Interrupt Enable 31"] + #[inline(always)] + pub fn tie31(&self) -> TIE31_R { + TIE31_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Transmission Interrupt Enable 0"] + #[inline(always)] + pub fn tie0(&mut self) -> TIE0_W { + TIE0_W { w: self } + } + #[doc = "Bit 1 - Transmission Interrupt Enable 1"] + #[inline(always)] + pub fn tie1(&mut self) -> TIE1_W { + TIE1_W { w: self } + } + #[doc = "Bit 2 - Transmission Interrupt Enable 2"] + #[inline(always)] + pub fn tie2(&mut self) -> TIE2_W { + TIE2_W { w: self } + } + #[doc = "Bit 3 - Transmission Interrupt Enable 3"] + #[inline(always)] + pub fn tie3(&mut self) -> TIE3_W { + TIE3_W { w: self } + } + #[doc = "Bit 4 - Transmission Interrupt Enable 4"] + #[inline(always)] + pub fn tie4(&mut self) -> TIE4_W { + TIE4_W { w: self } + } + #[doc = "Bit 5 - Transmission Interrupt Enable 5"] + #[inline(always)] + pub fn tie5(&mut self) -> TIE5_W { + TIE5_W { w: self } + } + #[doc = "Bit 6 - Transmission Interrupt Enable 6"] + #[inline(always)] + pub fn tie6(&mut self) -> TIE6_W { + TIE6_W { w: self } + } + #[doc = "Bit 7 - Transmission Interrupt Enable 7"] + #[inline(always)] + pub fn tie7(&mut self) -> TIE7_W { + TIE7_W { w: self } + } + #[doc = "Bit 8 - Transmission Interrupt Enable 8"] + #[inline(always)] + pub fn tie8(&mut self) -> TIE8_W { + TIE8_W { w: self } + } + #[doc = "Bit 9 - Transmission Interrupt Enable 9"] + #[inline(always)] + pub fn tie9(&mut self) -> TIE9_W { + TIE9_W { w: self } + } + #[doc = "Bit 10 - Transmission Interrupt Enable 10"] + #[inline(always)] + pub fn tie10(&mut self) -> TIE10_W { + TIE10_W { w: self } + } + #[doc = "Bit 11 - Transmission Interrupt Enable 11"] + #[inline(always)] + pub fn tie11(&mut self) -> TIE11_W { + TIE11_W { w: self } + } + #[doc = "Bit 12 - Transmission Interrupt Enable 12"] + #[inline(always)] + pub fn tie12(&mut self) -> TIE12_W { + TIE12_W { w: self } + } + #[doc = "Bit 13 - Transmission Interrupt Enable 13"] + #[inline(always)] + pub fn tie13(&mut self) -> TIE13_W { + TIE13_W { w: self } + } + #[doc = "Bit 14 - Transmission Interrupt Enable 14"] + #[inline(always)] + pub fn tie14(&mut self) -> TIE14_W { + TIE14_W { w: self } + } + #[doc = "Bit 15 - Transmission Interrupt Enable 15"] + #[inline(always)] + pub fn tie15(&mut self) -> TIE15_W { + TIE15_W { w: self } + } + #[doc = "Bit 16 - Transmission Interrupt Enable 16"] + #[inline(always)] + pub fn tie16(&mut self) -> TIE16_W { + TIE16_W { w: self } + } + #[doc = "Bit 17 - Transmission Interrupt Enable 17"] + #[inline(always)] + pub fn tie17(&mut self) -> TIE17_W { + TIE17_W { w: self } + } + #[doc = "Bit 18 - Transmission Interrupt Enable 18"] + #[inline(always)] + pub fn tie18(&mut self) -> TIE18_W { + TIE18_W { w: self } + } + #[doc = "Bit 19 - Transmission Interrupt Enable 19"] + #[inline(always)] + pub fn tie19(&mut self) -> TIE19_W { + TIE19_W { w: self } + } + #[doc = "Bit 20 - Transmission Interrupt Enable 20"] + #[inline(always)] + pub fn tie20(&mut self) -> TIE20_W { + TIE20_W { w: self } + } + #[doc = "Bit 21 - Transmission Interrupt Enable 21"] + #[inline(always)] + pub fn tie21(&mut self) -> TIE21_W { + TIE21_W { w: self } + } + #[doc = "Bit 22 - Transmission Interrupt Enable 22"] + #[inline(always)] + pub fn tie22(&mut self) -> TIE22_W { + TIE22_W { w: self } + } + #[doc = "Bit 23 - Transmission Interrupt Enable 23"] + #[inline(always)] + pub fn tie23(&mut self) -> TIE23_W { + TIE23_W { w: self } + } + #[doc = "Bit 24 - Transmission Interrupt Enable 24"] + #[inline(always)] + pub fn tie24(&mut self) -> TIE24_W { + TIE24_W { w: self } + } + #[doc = "Bit 25 - Transmission Interrupt Enable 25"] + #[inline(always)] + pub fn tie25(&mut self) -> TIE25_W { + TIE25_W { w: self } + } + #[doc = "Bit 26 - Transmission Interrupt Enable 26"] + #[inline(always)] + pub fn tie26(&mut self) -> TIE26_W { + TIE26_W { w: self } + } + #[doc = "Bit 27 - Transmission Interrupt Enable 27"] + #[inline(always)] + pub fn tie27(&mut self) -> TIE27_W { + TIE27_W { w: self } + } + #[doc = "Bit 28 - Transmission Interrupt Enable 28"] + #[inline(always)] + pub fn tie28(&mut self) -> TIE28_W { + TIE28_W { w: self } + } + #[doc = "Bit 29 - Transmission Interrupt Enable 29"] + #[inline(always)] + pub fn tie29(&mut self) -> TIE29_W { + TIE29_W { w: self } + } + #[doc = "Bit 30 - Transmission Interrupt Enable 30"] + #[inline(always)] + pub fn tie30(&mut self) -> TIE30_W { + TIE30_W { w: self } + } + #[doc = "Bit 31 - Transmission Interrupt Enable 31"] + #[inline(always)] + pub fn tie31(&mut self) -> TIE31_W { + TIE31_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Tx Buffer Transmission Interrupt Enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txbtie](index.html) module"] +pub struct TXBTIE_SPEC; +impl crate::RegisterSpec for TXBTIE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [txbtie::R](R) reader structure"] +impl crate::Readable for TXBTIE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [txbtie::W](W) writer structure"] +impl crate::Writable for TXBTIE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TXBTIE to value 0"] +impl crate::Resettable for TXBTIE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/can0/txbto.rs b/pac/atsamc21n/src/can0/txbto.rs new file mode 100644 index 000000000000..54bc8f1295ad --- /dev/null +++ b/pac/atsamc21n/src/can0/txbto.rs @@ -0,0 +1,673 @@ +#[doc = "Register `TXBTO` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `TO0` reader - Transmission Occurred 0"] +pub struct TO0_R(crate::FieldReader); +impl TO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO1` reader - Transmission Occurred 1"] +pub struct TO1_R(crate::FieldReader); +impl TO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO2` reader - Transmission Occurred 2"] +pub struct TO2_R(crate::FieldReader); +impl TO2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO3` reader - Transmission Occurred 3"] +pub struct TO3_R(crate::FieldReader); +impl TO3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO4` reader - Transmission Occurred 4"] +pub struct TO4_R(crate::FieldReader); +impl TO4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO5` reader - Transmission Occurred 5"] +pub struct TO5_R(crate::FieldReader); +impl TO5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO6` reader - Transmission Occurred 6"] +pub struct TO6_R(crate::FieldReader); +impl TO6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO7` reader - Transmission Occurred 7"] +pub struct TO7_R(crate::FieldReader); +impl TO7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO8` reader - Transmission Occurred 8"] +pub struct TO8_R(crate::FieldReader); +impl TO8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO9` reader - Transmission Occurred 9"] +pub struct TO9_R(crate::FieldReader); +impl TO9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO10` reader - Transmission Occurred 10"] +pub struct TO10_R(crate::FieldReader); +impl TO10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO11` reader - Transmission Occurred 11"] +pub struct TO11_R(crate::FieldReader); +impl TO11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO12` reader - Transmission Occurred 12"] +pub struct TO12_R(crate::FieldReader); +impl TO12_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO12_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO12_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO13` reader - Transmission Occurred 13"] +pub struct TO13_R(crate::FieldReader); +impl TO13_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO13_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO13_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO14` reader - Transmission Occurred 14"] +pub struct TO14_R(crate::FieldReader); +impl TO14_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO14_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO14_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO15` reader - Transmission Occurred 15"] +pub struct TO15_R(crate::FieldReader); +impl TO15_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO15_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO15_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO16` reader - Transmission Occurred 16"] +pub struct TO16_R(crate::FieldReader); +impl TO16_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO16_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO16_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO17` reader - Transmission Occurred 17"] +pub struct TO17_R(crate::FieldReader); +impl TO17_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO17_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO17_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO18` reader - Transmission Occurred 18"] +pub struct TO18_R(crate::FieldReader); +impl TO18_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO18_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO18_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO19` reader - Transmission Occurred 19"] +pub struct TO19_R(crate::FieldReader); +impl TO19_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO19_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO19_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO20` reader - Transmission Occurred 20"] +pub struct TO20_R(crate::FieldReader); +impl TO20_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO20_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO20_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO21` reader - Transmission Occurred 21"] +pub struct TO21_R(crate::FieldReader); +impl TO21_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO21_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO21_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO22` reader - Transmission Occurred 22"] +pub struct TO22_R(crate::FieldReader); +impl TO22_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO22_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO22_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO23` reader - Transmission Occurred 23"] +pub struct TO23_R(crate::FieldReader); +impl TO23_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO23_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO23_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO24` reader - Transmission Occurred 24"] +pub struct TO24_R(crate::FieldReader); +impl TO24_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO24_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO24_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO25` reader - Transmission Occurred 25"] +pub struct TO25_R(crate::FieldReader); +impl TO25_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO25_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO25_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO26` reader - Transmission Occurred 26"] +pub struct TO26_R(crate::FieldReader); +impl TO26_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO26_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO26_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO27` reader - Transmission Occurred 27"] +pub struct TO27_R(crate::FieldReader); +impl TO27_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO27_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO27_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO28` reader - Transmission Occurred 28"] +pub struct TO28_R(crate::FieldReader); +impl TO28_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO28_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO28_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO29` reader - Transmission Occurred 29"] +pub struct TO29_R(crate::FieldReader); +impl TO29_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO29_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO29_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO30` reader - Transmission Occurred 30"] +pub struct TO30_R(crate::FieldReader); +impl TO30_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO30_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO30_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO31` reader - Transmission Occurred 31"] +pub struct TO31_R(crate::FieldReader); +impl TO31_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO31_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO31_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Transmission Occurred 0"] + #[inline(always)] + pub fn to0(&self) -> TO0_R { + TO0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmission Occurred 1"] + #[inline(always)] + pub fn to1(&self) -> TO1_R { + TO1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Transmission Occurred 2"] + #[inline(always)] + pub fn to2(&self) -> TO2_R { + TO2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Transmission Occurred 3"] + #[inline(always)] + pub fn to3(&self) -> TO3_R { + TO3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Transmission Occurred 4"] + #[inline(always)] + pub fn to4(&self) -> TO4_R { + TO4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Transmission Occurred 5"] + #[inline(always)] + pub fn to5(&self) -> TO5_R { + TO5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Transmission Occurred 6"] + #[inline(always)] + pub fn to6(&self) -> TO6_R { + TO6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Transmission Occurred 7"] + #[inline(always)] + pub fn to7(&self) -> TO7_R { + TO7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Transmission Occurred 8"] + #[inline(always)] + pub fn to8(&self) -> TO8_R { + TO8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Transmission Occurred 9"] + #[inline(always)] + pub fn to9(&self) -> TO9_R { + TO9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Transmission Occurred 10"] + #[inline(always)] + pub fn to10(&self) -> TO10_R { + TO10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Transmission Occurred 11"] + #[inline(always)] + pub fn to11(&self) -> TO11_R { + TO11_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Transmission Occurred 12"] + #[inline(always)] + pub fn to12(&self) -> TO12_R { + TO12_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Transmission Occurred 13"] + #[inline(always)] + pub fn to13(&self) -> TO13_R { + TO13_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Transmission Occurred 14"] + #[inline(always)] + pub fn to14(&self) -> TO14_R { + TO14_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Transmission Occurred 15"] + #[inline(always)] + pub fn to15(&self) -> TO15_R { + TO15_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Transmission Occurred 16"] + #[inline(always)] + pub fn to16(&self) -> TO16_R { + TO16_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Transmission Occurred 17"] + #[inline(always)] + pub fn to17(&self) -> TO17_R { + TO17_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Transmission Occurred 18"] + #[inline(always)] + pub fn to18(&self) -> TO18_R { + TO18_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Transmission Occurred 19"] + #[inline(always)] + pub fn to19(&self) -> TO19_R { + TO19_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Transmission Occurred 20"] + #[inline(always)] + pub fn to20(&self) -> TO20_R { + TO20_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Transmission Occurred 21"] + #[inline(always)] + pub fn to21(&self) -> TO21_R { + TO21_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Transmission Occurred 22"] + #[inline(always)] + pub fn to22(&self) -> TO22_R { + TO22_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Transmission Occurred 23"] + #[inline(always)] + pub fn to23(&self) -> TO23_R { + TO23_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24 - Transmission Occurred 24"] + #[inline(always)] + pub fn to24(&self) -> TO24_R { + TO24_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Transmission Occurred 25"] + #[inline(always)] + pub fn to25(&self) -> TO25_R { + TO25_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Transmission Occurred 26"] + #[inline(always)] + pub fn to26(&self) -> TO26_R { + TO26_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Transmission Occurred 27"] + #[inline(always)] + pub fn to27(&self) -> TO27_R { + TO27_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28 - Transmission Occurred 28"] + #[inline(always)] + pub fn to28(&self) -> TO28_R { + TO28_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Transmission Occurred 29"] + #[inline(always)] + pub fn to29(&self) -> TO29_R { + TO29_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - Transmission Occurred 30"] + #[inline(always)] + pub fn to30(&self) -> TO30_R { + TO30_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 31 - Transmission Occurred 31"] + #[inline(always)] + pub fn to31(&self) -> TO31_R { + TO31_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +#[doc = "Tx Buffer Transmission Occurred\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txbto](index.html) module"] +pub struct TXBTO_SPEC; +impl crate::RegisterSpec for TXBTO_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [txbto::R](R) reader structure"] +impl crate::Readable for TXBTO_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets TXBTO to value 0"] +impl crate::Resettable for TXBTO_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/can0/txefa.rs b/pac/atsamc21n/src/can0/txefa.rs new file mode 100644 index 000000000000..c539b8fc3dc0 --- /dev/null +++ b/pac/atsamc21n/src/can0/txefa.rs @@ -0,0 +1,103 @@ +#[doc = "Register `TXEFA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TXEFA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EFAI` reader - Event FIFO Acknowledge Index"] +pub struct EFAI_R(crate::FieldReader); +impl EFAI_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EFAI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EFAI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EFAI` writer - Event FIFO Acknowledge Index"] +pub struct EFAI_W<'a> { + w: &'a mut W, +} +impl<'a> EFAI_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Event FIFO Acknowledge Index"] + #[inline(always)] + pub fn efai(&self) -> EFAI_R { + EFAI_R::new((self.bits & 0x1f) as u8) + } +} +impl W { + #[doc = "Bits 0:4 - Event FIFO Acknowledge Index"] + #[inline(always)] + pub fn efai(&mut self) -> EFAI_W { + EFAI_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Tx Event FIFO Acknowledge\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txefa](index.html) module"] +pub struct TXEFA_SPEC; +impl crate::RegisterSpec for TXEFA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [txefa::R](R) reader structure"] +impl crate::Readable for TXEFA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [txefa::W](W) writer structure"] +impl crate::Writable for TXEFA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TXEFA to value 0"] +impl crate::Resettable for TXEFA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/can0/txefc.rs b/pac/atsamc21n/src/can0/txefc.rs new file mode 100644 index 000000000000..0c9b658d285b --- /dev/null +++ b/pac/atsamc21n/src/can0/txefc.rs @@ -0,0 +1,177 @@ +#[doc = "Register `TXEFC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TXEFC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EFSA` reader - Event FIFO Start Address"] +pub struct EFSA_R(crate::FieldReader); +impl EFSA_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + EFSA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EFSA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EFSA` writer - Event FIFO Start Address"] +pub struct EFSA_W<'a> { + w: &'a mut W, +} +impl<'a> EFSA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +#[doc = "Field `EFS` reader - Event FIFO Size"] +pub struct EFS_R(crate::FieldReader); +impl EFS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EFS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EFS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EFS` writer - Event FIFO Size"] +pub struct EFS_W<'a> { + w: &'a mut W, +} +impl<'a> EFS_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 16)) | ((value as u32 & 0x3f) << 16); + self.w + } +} +#[doc = "Field `EFWM` reader - Event FIFO Watermark"] +pub struct EFWM_R(crate::FieldReader); +impl EFWM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EFWM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EFWM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EFWM` writer - Event FIFO Watermark"] +pub struct EFWM_W<'a> { + w: &'a mut W, +} +impl<'a> EFWM_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 24)) | ((value as u32 & 0x3f) << 24); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Event FIFO Start Address"] + #[inline(always)] + pub fn efsa(&self) -> EFSA_R { + EFSA_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:21 - Event FIFO Size"] + #[inline(always)] + pub fn efs(&self) -> EFS_R { + EFS_R::new(((self.bits >> 16) & 0x3f) as u8) + } + #[doc = "Bits 24:29 - Event FIFO Watermark"] + #[inline(always)] + pub fn efwm(&self) -> EFWM_R { + EFWM_R::new(((self.bits >> 24) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:15 - Event FIFO Start Address"] + #[inline(always)] + pub fn efsa(&mut self) -> EFSA_W { + EFSA_W { w: self } + } + #[doc = "Bits 16:21 - Event FIFO Size"] + #[inline(always)] + pub fn efs(&mut self) -> EFS_W { + EFS_W { w: self } + } + #[doc = "Bits 24:29 - Event FIFO Watermark"] + #[inline(always)] + pub fn efwm(&mut self) -> EFWM_W { + EFWM_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Tx Event FIFO Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txefc](index.html) module"] +pub struct TXEFC_SPEC; +impl crate::RegisterSpec for TXEFC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [txefc::R](R) reader structure"] +impl crate::Readable for TXEFC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [txefc::W](W) writer structure"] +impl crate::Writable for TXEFC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TXEFC to value 0"] +impl crate::Resettable for TXEFC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/can0/txefs.rs b/pac/atsamc21n/src/can0/txefs.rs new file mode 100644 index 000000000000..85cac75a7ad7 --- /dev/null +++ b/pac/atsamc21n/src/can0/txefs.rs @@ -0,0 +1,133 @@ +#[doc = "Register `TXEFS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `EFFL` reader - Event FIFO Fill Level"] +pub struct EFFL_R(crate::FieldReader); +impl EFFL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EFFL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EFFL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EFGI` reader - Event FIFO Get Index"] +pub struct EFGI_R(crate::FieldReader); +impl EFGI_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EFGI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EFGI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EFPI` reader - Event FIFO Put Index"] +pub struct EFPI_R(crate::FieldReader); +impl EFPI_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EFPI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EFPI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EFF` reader - Event FIFO Full"] +pub struct EFF_R(crate::FieldReader); +impl EFF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EFF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EFF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TEFL` reader - Tx Event FIFO Element Lost"] +pub struct TEFL_R(crate::FieldReader); +impl TEFL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TEFL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TEFL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:5 - Event FIFO Fill Level"] + #[inline(always)] + pub fn effl(&self) -> EFFL_R { + EFFL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 8:12 - Event FIFO Get Index"] + #[inline(always)] + pub fn efgi(&self) -> EFGI_R { + EFGI_R::new(((self.bits >> 8) & 0x1f) as u8) + } + #[doc = "Bits 16:20 - Event FIFO Put Index"] + #[inline(always)] + pub fn efpi(&self) -> EFPI_R { + EFPI_R::new(((self.bits >> 16) & 0x1f) as u8) + } + #[doc = "Bit 24 - Event FIFO Full"] + #[inline(always)] + pub fn eff(&self) -> EFF_R { + EFF_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Tx Event FIFO Element Lost"] + #[inline(always)] + pub fn tefl(&self) -> TEFL_R { + TEFL_R::new(((self.bits >> 25) & 0x01) != 0) + } +} +#[doc = "Tx Event FIFO Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txefs](index.html) module"] +pub struct TXEFS_SPEC; +impl crate::RegisterSpec for TXEFS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [txefs::R](R) reader structure"] +impl crate::Readable for TXEFS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets TXEFS to value 0"] +impl crate::Resettable for TXEFS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/can0/txesc.rs b/pac/atsamc21n/src/can0/txesc.rs new file mode 100644 index 000000000000..7d1339f7c1cb --- /dev/null +++ b/pac/atsamc21n/src/can0/txesc.rs @@ -0,0 +1,230 @@ +#[doc = "Register `TXESC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TXESC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Tx Buffer Data Field Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum TBDS_A { + #[doc = "0: 8 byte data field"] + DATA8 = 0, + #[doc = "1: 12 byte data field"] + DATA12 = 1, + #[doc = "2: 16 byte data field"] + DATA16 = 2, + #[doc = "3: 20 byte data field"] + DATA20 = 3, + #[doc = "4: 24 byte data field"] + DATA24 = 4, + #[doc = "5: 32 byte data field"] + DATA32 = 5, + #[doc = "6: 48 byte data field"] + DATA48 = 6, + #[doc = "7: 64 byte data field"] + DATA64 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: TBDS_A) -> Self { + variant as _ + } +} +#[doc = "Field `TBDS` reader - Tx Buffer Data Field Size"] +pub struct TBDS_R(crate::FieldReader); +impl TBDS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TBDS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TBDS_A { + match self.bits { + 0 => TBDS_A::DATA8, + 1 => TBDS_A::DATA12, + 2 => TBDS_A::DATA16, + 3 => TBDS_A::DATA20, + 4 => TBDS_A::DATA24, + 5 => TBDS_A::DATA32, + 6 => TBDS_A::DATA48, + 7 => TBDS_A::DATA64, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DATA8`"] + #[inline(always)] + pub fn is_data8(&self) -> bool { + **self == TBDS_A::DATA8 + } + #[doc = "Checks if the value of the field is `DATA12`"] + #[inline(always)] + pub fn is_data12(&self) -> bool { + **self == TBDS_A::DATA12 + } + #[doc = "Checks if the value of the field is `DATA16`"] + #[inline(always)] + pub fn is_data16(&self) -> bool { + **self == TBDS_A::DATA16 + } + #[doc = "Checks if the value of the field is `DATA20`"] + #[inline(always)] + pub fn is_data20(&self) -> bool { + **self == TBDS_A::DATA20 + } + #[doc = "Checks if the value of the field is `DATA24`"] + #[inline(always)] + pub fn is_data24(&self) -> bool { + **self == TBDS_A::DATA24 + } + #[doc = "Checks if the value of the field is `DATA32`"] + #[inline(always)] + pub fn is_data32(&self) -> bool { + **self == TBDS_A::DATA32 + } + #[doc = "Checks if the value of the field is `DATA48`"] + #[inline(always)] + pub fn is_data48(&self) -> bool { + **self == TBDS_A::DATA48 + } + #[doc = "Checks if the value of the field is `DATA64`"] + #[inline(always)] + pub fn is_data64(&self) -> bool { + **self == TBDS_A::DATA64 + } +} +impl core::ops::Deref for TBDS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TBDS` writer - Tx Buffer Data Field Size"] +pub struct TBDS_W<'a> { + w: &'a mut W, +} +impl<'a> TBDS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TBDS_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "8 byte data field"] + #[inline(always)] + pub fn data8(self) -> &'a mut W { + self.variant(TBDS_A::DATA8) + } + #[doc = "12 byte data field"] + #[inline(always)] + pub fn data12(self) -> &'a mut W { + self.variant(TBDS_A::DATA12) + } + #[doc = "16 byte data field"] + #[inline(always)] + pub fn data16(self) -> &'a mut W { + self.variant(TBDS_A::DATA16) + } + #[doc = "20 byte data field"] + #[inline(always)] + pub fn data20(self) -> &'a mut W { + self.variant(TBDS_A::DATA20) + } + #[doc = "24 byte data field"] + #[inline(always)] + pub fn data24(self) -> &'a mut W { + self.variant(TBDS_A::DATA24) + } + #[doc = "32 byte data field"] + #[inline(always)] + pub fn data32(self) -> &'a mut W { + self.variant(TBDS_A::DATA32) + } + #[doc = "48 byte data field"] + #[inline(always)] + pub fn data48(self) -> &'a mut W { + self.variant(TBDS_A::DATA48) + } + #[doc = "64 byte data field"] + #[inline(always)] + pub fn data64(self) -> &'a mut W { + self.variant(TBDS_A::DATA64) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Tx Buffer Data Field Size"] + #[inline(always)] + pub fn tbds(&self) -> TBDS_R { + TBDS_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Tx Buffer Data Field Size"] + #[inline(always)] + pub fn tbds(&mut self) -> TBDS_W { + TBDS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Tx Buffer Element Size Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txesc](index.html) module"] +pub struct TXESC_SPEC; +impl crate::RegisterSpec for TXESC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [txesc::R](R) reader structure"] +impl crate::Readable for TXESC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [txesc::W](W) writer structure"] +impl crate::Writable for TXESC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TXESC to value 0"] +impl crate::Resettable for TXESC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/can0/txfqs.rs b/pac/atsamc21n/src/can0/txfqs.rs new file mode 100644 index 000000000000..19ef5f5d3fe6 --- /dev/null +++ b/pac/atsamc21n/src/can0/txfqs.rs @@ -0,0 +1,113 @@ +#[doc = "Register `TXFQS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `TFFL` reader - Tx FIFO Free Level"] +pub struct TFFL_R(crate::FieldReader); +impl TFFL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TFFL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TFFL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TFGI` reader - Tx FIFO Get Index"] +pub struct TFGI_R(crate::FieldReader); +impl TFGI_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TFGI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TFGI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TFQPI` reader - Tx FIFO/Queue Put Index"] +pub struct TFQPI_R(crate::FieldReader); +impl TFQPI_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TFQPI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TFQPI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TFQF` reader - Tx FIFO/Queue Full"] +pub struct TFQF_R(crate::FieldReader); +impl TFQF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TFQF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TFQF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:5 - Tx FIFO Free Level"] + #[inline(always)] + pub fn tffl(&self) -> TFFL_R { + TFFL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 8:12 - Tx FIFO Get Index"] + #[inline(always)] + pub fn tfgi(&self) -> TFGI_R { + TFGI_R::new(((self.bits >> 8) & 0x1f) as u8) + } + #[doc = "Bits 16:20 - Tx FIFO/Queue Put Index"] + #[inline(always)] + pub fn tfqpi(&self) -> TFQPI_R { + TFQPI_R::new(((self.bits >> 16) & 0x1f) as u8) + } + #[doc = "Bit 21 - Tx FIFO/Queue Full"] + #[inline(always)] + pub fn tfqf(&self) -> TFQF_R { + TFQF_R::new(((self.bits >> 21) & 0x01) != 0) + } +} +#[doc = "Tx FIFO / Queue Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txfqs](index.html) module"] +pub struct TXFQS_SPEC; +impl crate::RegisterSpec for TXFQS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [txfqs::R](R) reader structure"] +impl crate::Readable for TXFQS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets TXFQS to value 0"] +impl crate::Resettable for TXFQS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/can0/xidam.rs b/pac/atsamc21n/src/can0/xidam.rs new file mode 100644 index 000000000000..8d78879a63be --- /dev/null +++ b/pac/atsamc21n/src/can0/xidam.rs @@ -0,0 +1,103 @@ +#[doc = "Register `XIDAM` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `XIDAM` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EIDM` reader - Extended ID Mask"] +pub struct EIDM_R(crate::FieldReader); +impl EIDM_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + EIDM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EIDM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EIDM` writer - Extended ID Mask"] +pub struct EIDM_W<'a> { + w: &'a mut W, +} +impl<'a> EIDM_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1fff_ffff) | (value as u32 & 0x1fff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:28 - Extended ID Mask"] + #[inline(always)] + pub fn eidm(&self) -> EIDM_R { + EIDM_R::new((self.bits & 0x1fff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:28 - Extended ID Mask"] + #[inline(always)] + pub fn eidm(&mut self) -> EIDM_W { + EIDM_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Extended ID AND Mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [xidam](index.html) module"] +pub struct XIDAM_SPEC; +impl crate::RegisterSpec for XIDAM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [xidam::R](R) reader structure"] +impl crate::Readable for XIDAM_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [xidam::W](W) writer structure"] +impl crate::Writable for XIDAM_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets XIDAM to value 0x1fff_ffff"] +impl crate::Resettable for XIDAM_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x1fff_ffff + } +} diff --git a/pac/atsamc21n/src/can0/xidfc.rs b/pac/atsamc21n/src/can0/xidfc.rs new file mode 100644 index 000000000000..57b31389a71f --- /dev/null +++ b/pac/atsamc21n/src/can0/xidfc.rs @@ -0,0 +1,140 @@ +#[doc = "Register `XIDFC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `XIDFC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FLESA` reader - Filter List Extended Start Address"] +pub struct FLESA_R(crate::FieldReader); +impl FLESA_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + FLESA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FLESA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLESA` writer - Filter List Extended Start Address"] +pub struct FLESA_W<'a> { + w: &'a mut W, +} +impl<'a> FLESA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +#[doc = "Field `LSE` reader - List Size Extended"] +pub struct LSE_R(crate::FieldReader); +impl LSE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LSE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LSE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LSE` writer - List Size Extended"] +pub struct LSE_W<'a> { + w: &'a mut W, +} +impl<'a> LSE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x7f << 16)) | ((value as u32 & 0x7f) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Filter List Extended Start Address"] + #[inline(always)] + pub fn flesa(&self) -> FLESA_R { + FLESA_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:22 - List Size Extended"] + #[inline(always)] + pub fn lse(&self) -> LSE_R { + LSE_R::new(((self.bits >> 16) & 0x7f) as u8) + } +} +impl W { + #[doc = "Bits 0:15 - Filter List Extended Start Address"] + #[inline(always)] + pub fn flesa(&mut self) -> FLESA_W { + FLESA_W { w: self } + } + #[doc = "Bits 16:22 - List Size Extended"] + #[inline(always)] + pub fn lse(&mut self) -> LSE_W { + LSE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Extended ID Filter Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [xidfc](index.html) module"] +pub struct XIDFC_SPEC; +impl crate::RegisterSpec for XIDFC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [xidfc::R](R) reader structure"] +impl crate::Readable for XIDFC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [xidfc::W](W) writer structure"] +impl crate::Writable for XIDFC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets XIDFC to value 0"] +impl crate::Resettable for XIDFC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/ccl.rs b/pac/atsamc21n/src/ccl.rs new file mode 100644 index 000000000000..30b1f41639c1 --- /dev/null +++ b/pac/atsamc21n/src/ccl.rs @@ -0,0 +1,24 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrl: crate::Reg, + _reserved1: [u8; 0x03], + #[doc = "0x04 - SEQ Control x"] + pub seqctrl: [crate::Reg; 2], + _reserved2: [u8; 0x02], + #[doc = "0x08..0x18 - LUT Control x"] + pub lutctrl: [crate::Reg; 4], +} +#[doc = "CTRL register accessor: an alias for `Reg`"] +pub type CTRL = crate::Reg; +#[doc = "Control"] +pub mod ctrl; +#[doc = "SEQCTRL register accessor: an alias for `Reg`"] +pub type SEQCTRL = crate::Reg; +#[doc = "SEQ Control x"] +pub mod seqctrl; +#[doc = "LUTCTRL register accessor: an alias for `Reg`"] +pub type LUTCTRL = crate::Reg; +#[doc = "LUT Control x"] +pub mod lutctrl; diff --git a/pac/atsamc21n/src/ccl/ctrl.rs b/pac/atsamc21n/src/ccl/ctrl.rs new file mode 100644 index 000000000000..5e515fe037ca --- /dev/null +++ b/pac/atsamc21n/src/ccl/ctrl.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"] +pub struct CTRL_SPEC; +impl crate::RegisterSpec for CTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrl::R](R) reader structure"] +impl crate::Readable for CTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"] +impl crate::Writable for CTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/ccl/lutctrl.rs b/pac/atsamc21n/src/ccl/lutctrl.rs new file mode 100644 index 000000000000..e1f8d4e05482 --- /dev/null +++ b/pac/atsamc21n/src/ccl/lutctrl.rs @@ -0,0 +1,728 @@ +#[doc = "Register `LUTCTRL[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `LUTCTRL[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - LUT Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - LUT Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Filter Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FILTSEL_A { + #[doc = "0: Filter disabled"] + DISABLE = 0, + #[doc = "1: Synchronizer enabled"] + SYNCH = 1, + #[doc = "2: Filter enabled"] + FILTER = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FILTSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `FILTSEL` reader - Filter Selection"] +pub struct FILTSEL_R(crate::FieldReader); +impl FILTSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FILTSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(FILTSEL_A::DISABLE), + 1 => Some(FILTSEL_A::SYNCH), + 2 => Some(FILTSEL_A::FILTER), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == FILTSEL_A::DISABLE + } + #[doc = "Checks if the value of the field is `SYNCH`"] + #[inline(always)] + pub fn is_synch(&self) -> bool { + **self == FILTSEL_A::SYNCH + } + #[doc = "Checks if the value of the field is `FILTER`"] + #[inline(always)] + pub fn is_filter(&self) -> bool { + **self == FILTSEL_A::FILTER + } +} +impl core::ops::Deref for FILTSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTSEL` writer - Filter Selection"] +pub struct FILTSEL_W<'a> { + w: &'a mut W, +} +impl<'a> FILTSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FILTSEL_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Filter disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(FILTSEL_A::DISABLE) + } + #[doc = "Synchronizer enabled"] + #[inline(always)] + pub fn synch(self) -> &'a mut W { + self.variant(FILTSEL_A::SYNCH) + } + #[doc = "Filter enabled"] + #[inline(always)] + pub fn filter(self) -> &'a mut W { + self.variant(FILTSEL_A::FILTER) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u32 & 0x03) << 4); + self.w + } +} +#[doc = "Field `EDGESEL` reader - Edge Selection"] +pub struct EDGESEL_R(crate::FieldReader); +impl EDGESEL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EDGESEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EDGESEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EDGESEL` writer - Edge Selection"] +pub struct EDGESEL_W<'a> { + w: &'a mut W, +} +impl<'a> EDGESEL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Input Selection 0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum INSEL0_A { + #[doc = "0: Masked input"] + MASK = 0, + #[doc = "1: Feedback input source"] + FEEDBACK = 1, + #[doc = "2: Linked LUT input source"] + LINK = 2, + #[doc = "3: Event in put source"] + EVENT = 3, + #[doc = "4: I/O pin input source"] + IO = 4, + #[doc = "5: AC input source"] + AC = 5, + #[doc = "6: TC input source"] + TC = 6, + #[doc = "7: Alternate TC input source"] + ALTTC = 7, + #[doc = "8: TCC input source"] + TCC = 8, + #[doc = "9: SERCOM inout source"] + SERCOM = 9, + #[doc = "10: Alternate 2 TC input source"] + ALT2TC = 10, + #[doc = "11: ASYNC EVENT input source. The EVENT input will bypass edge detection logic."] + ASYNCEVENT = 11, +} +impl From for u8 { + #[inline(always)] + fn from(variant: INSEL0_A) -> Self { + variant as _ + } +} +#[doc = "Field `INSEL0` reader - Input Selection 0"] +pub struct INSEL0_R(crate::FieldReader); +impl INSEL0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + INSEL0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(INSEL0_A::MASK), + 1 => Some(INSEL0_A::FEEDBACK), + 2 => Some(INSEL0_A::LINK), + 3 => Some(INSEL0_A::EVENT), + 4 => Some(INSEL0_A::IO), + 5 => Some(INSEL0_A::AC), + 6 => Some(INSEL0_A::TC), + 7 => Some(INSEL0_A::ALTTC), + 8 => Some(INSEL0_A::TCC), + 9 => Some(INSEL0_A::SERCOM), + 10 => Some(INSEL0_A::ALT2TC), + 11 => Some(INSEL0_A::ASYNCEVENT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `MASK`"] + #[inline(always)] + pub fn is_mask(&self) -> bool { + **self == INSEL0_A::MASK + } + #[doc = "Checks if the value of the field is `FEEDBACK`"] + #[inline(always)] + pub fn is_feedback(&self) -> bool { + **self == INSEL0_A::FEEDBACK + } + #[doc = "Checks if the value of the field is `LINK`"] + #[inline(always)] + pub fn is_link(&self) -> bool { + **self == INSEL0_A::LINK + } + #[doc = "Checks if the value of the field is `EVENT`"] + #[inline(always)] + pub fn is_event(&self) -> bool { + **self == INSEL0_A::EVENT + } + #[doc = "Checks if the value of the field is `IO`"] + #[inline(always)] + pub fn is_io(&self) -> bool { + **self == INSEL0_A::IO + } + #[doc = "Checks if the value of the field is `AC`"] + #[inline(always)] + pub fn is_ac(&self) -> bool { + **self == INSEL0_A::AC + } + #[doc = "Checks if the value of the field is `TC`"] + #[inline(always)] + pub fn is_tc(&self) -> bool { + **self == INSEL0_A::TC + } + #[doc = "Checks if the value of the field is `ALTTC`"] + #[inline(always)] + pub fn is_alttc(&self) -> bool { + **self == INSEL0_A::ALTTC + } + #[doc = "Checks if the value of the field is `TCC`"] + #[inline(always)] + pub fn is_tcc(&self) -> bool { + **self == INSEL0_A::TCC + } + #[doc = "Checks if the value of the field is `SERCOM`"] + #[inline(always)] + pub fn is_sercom(&self) -> bool { + **self == INSEL0_A::SERCOM + } + #[doc = "Checks if the value of the field is `ALT2TC`"] + #[inline(always)] + pub fn is_alt2tc(&self) -> bool { + **self == INSEL0_A::ALT2TC + } + #[doc = "Checks if the value of the field is `ASYNCEVENT`"] + #[inline(always)] + pub fn is_asyncevent(&self) -> bool { + **self == INSEL0_A::ASYNCEVENT + } +} +impl core::ops::Deref for INSEL0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INSEL0` writer - Input Selection 0"] +pub struct INSEL0_W<'a> { + w: &'a mut W, +} +impl<'a> INSEL0_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: INSEL0_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Masked input"] + #[inline(always)] + pub fn mask(self) -> &'a mut W { + self.variant(INSEL0_A::MASK) + } + #[doc = "Feedback input source"] + #[inline(always)] + pub fn feedback(self) -> &'a mut W { + self.variant(INSEL0_A::FEEDBACK) + } + #[doc = "Linked LUT input source"] + #[inline(always)] + pub fn link(self) -> &'a mut W { + self.variant(INSEL0_A::LINK) + } + #[doc = "Event in put source"] + #[inline(always)] + pub fn event(self) -> &'a mut W { + self.variant(INSEL0_A::EVENT) + } + #[doc = "I/O pin input source"] + #[inline(always)] + pub fn io(self) -> &'a mut W { + self.variant(INSEL0_A::IO) + } + #[doc = "AC input source"] + #[inline(always)] + pub fn ac(self) -> &'a mut W { + self.variant(INSEL0_A::AC) + } + #[doc = "TC input source"] + #[inline(always)] + pub fn tc(self) -> &'a mut W { + self.variant(INSEL0_A::TC) + } + #[doc = "Alternate TC input source"] + #[inline(always)] + pub fn alttc(self) -> &'a mut W { + self.variant(INSEL0_A::ALTTC) + } + #[doc = "TCC input source"] + #[inline(always)] + pub fn tcc(self) -> &'a mut W { + self.variant(INSEL0_A::TCC) + } + #[doc = "SERCOM inout source"] + #[inline(always)] + pub fn sercom(self) -> &'a mut W { + self.variant(INSEL0_A::SERCOM) + } + #[doc = "Alternate 2 TC input source"] + #[inline(always)] + pub fn alt2tc(self) -> &'a mut W { + self.variant(INSEL0_A::ALT2TC) + } + #[doc = "ASYNC EVENT input source. The EVENT input will bypass edge detection logic."] + #[inline(always)] + pub fn asyncevent(self) -> &'a mut W { + self.variant(INSEL0_A::ASYNCEVENT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 8)) | ((value as u32 & 0x0f) << 8); + self.w + } +} +#[doc = "Field `INSEL1` reader - Input Selection 1"] +pub struct INSEL1_R(crate::FieldReader); +impl INSEL1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + INSEL1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INSEL1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INSEL1` writer - Input Selection 1"] +pub struct INSEL1_W<'a> { + w: &'a mut W, +} +impl<'a> INSEL1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 12)) | ((value as u32 & 0x0f) << 12); + self.w + } +} +#[doc = "Field `INSEL2` reader - Input Selection 2"] +pub struct INSEL2_R(crate::FieldReader); +impl INSEL2_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + INSEL2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INSEL2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INSEL2` writer - Input Selection 2"] +pub struct INSEL2_W<'a> { + w: &'a mut W, +} +impl<'a> INSEL2_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 16)) | ((value as u32 & 0x0f) << 16); + self.w + } +} +#[doc = "Field `INVEI` reader - Input Event Invert"] +pub struct INVEI_R(crate::FieldReader); +impl INVEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEI` writer - Input Event Invert"] +pub struct INVEI_W<'a> { + w: &'a mut W, +} +impl<'a> INVEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `LUTEI` reader - Event Input Enable"] +pub struct LUTEI_R(crate::FieldReader); +impl LUTEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LUTEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LUTEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LUTEI` writer - Event Input Enable"] +pub struct LUTEI_W<'a> { + w: &'a mut W, +} +impl<'a> LUTEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `LUTEO` reader - Event Output Enable"] +pub struct LUTEO_R(crate::FieldReader); +impl LUTEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LUTEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LUTEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LUTEO` writer - Event Output Enable"] +pub struct LUTEO_W<'a> { + w: &'a mut W, +} +impl<'a> LUTEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `TRUTH` reader - Truth Value"] +pub struct TRUTH_R(crate::FieldReader); +impl TRUTH_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TRUTH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRUTH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRUTH` writer - Truth Value"] +pub struct TRUTH_W<'a> { + w: &'a mut W, +} +impl<'a> TRUTH_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 24)) | ((value as u32 & 0xff) << 24); + self.w + } +} +impl R { + #[doc = "Bit 1 - LUT Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 4:5 - Filter Selection"] + #[inline(always)] + pub fn filtsel(&self) -> FILTSEL_R { + FILTSEL_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bit 7 - Edge Selection"] + #[inline(always)] + pub fn edgesel(&self) -> EDGESEL_R { + EDGESEL_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:11 - Input Selection 0"] + #[inline(always)] + pub fn insel0(&self) -> INSEL0_R { + INSEL0_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - Input Selection 1"] + #[inline(always)] + pub fn insel1(&self) -> INSEL1_R { + INSEL1_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:19 - Input Selection 2"] + #[inline(always)] + pub fn insel2(&self) -> INSEL2_R { + INSEL2_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Input Event Invert"] + #[inline(always)] + pub fn invei(&self) -> INVEI_R { + INVEI_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Event Input Enable"] + #[inline(always)] + pub fn lutei(&self) -> LUTEI_R { + LUTEI_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Event Output Enable"] + #[inline(always)] + pub fn luteo(&self) -> LUTEO_R { + LUTEO_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bits 24:31 - Truth Value"] + #[inline(always)] + pub fn truth(&self) -> TRUTH_R { + TRUTH_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bit 1 - LUT Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 4:5 - Filter Selection"] + #[inline(always)] + pub fn filtsel(&mut self) -> FILTSEL_W { + FILTSEL_W { w: self } + } + #[doc = "Bit 7 - Edge Selection"] + #[inline(always)] + pub fn edgesel(&mut self) -> EDGESEL_W { + EDGESEL_W { w: self } + } + #[doc = "Bits 8:11 - Input Selection 0"] + #[inline(always)] + pub fn insel0(&mut self) -> INSEL0_W { + INSEL0_W { w: self } + } + #[doc = "Bits 12:15 - Input Selection 1"] + #[inline(always)] + pub fn insel1(&mut self) -> INSEL1_W { + INSEL1_W { w: self } + } + #[doc = "Bits 16:19 - Input Selection 2"] + #[inline(always)] + pub fn insel2(&mut self) -> INSEL2_W { + INSEL2_W { w: self } + } + #[doc = "Bit 20 - Input Event Invert"] + #[inline(always)] + pub fn invei(&mut self) -> INVEI_W { + INVEI_W { w: self } + } + #[doc = "Bit 21 - Event Input Enable"] + #[inline(always)] + pub fn lutei(&mut self) -> LUTEI_W { + LUTEI_W { w: self } + } + #[doc = "Bit 22 - Event Output Enable"] + #[inline(always)] + pub fn luteo(&mut self) -> LUTEO_W { + LUTEO_W { w: self } + } + #[doc = "Bits 24:31 - Truth Value"] + #[inline(always)] + pub fn truth(&mut self) -> TRUTH_W { + TRUTH_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "LUT Control x\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lutctrl](index.html) module"] +pub struct LUTCTRL_SPEC; +impl crate::RegisterSpec for LUTCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [lutctrl::R](R) reader structure"] +impl crate::Readable for LUTCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [lutctrl::W](W) writer structure"] +impl crate::Writable for LUTCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets LUTCTRL[%s] +to value 0"] +impl crate::Resettable for LUTCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/ccl/seqctrl.rs b/pac/atsamc21n/src/ccl/seqctrl.rs new file mode 100644 index 000000000000..e2597a1042f3 --- /dev/null +++ b/pac/atsamc21n/src/ccl/seqctrl.rs @@ -0,0 +1,192 @@ +#[doc = "Register `SEQCTRL[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SEQCTRL[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Sequential Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SEQSEL_A { + #[doc = "0: Sequential logic is disabled"] + DISABLE = 0, + #[doc = "1: D flip flop"] + DFF = 1, + #[doc = "2: JK flip flop"] + JK = 2, + #[doc = "3: D latch"] + LATCH = 3, + #[doc = "4: RS latch"] + RS = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEQSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `SEQSEL` reader - Sequential Selection"] +pub struct SEQSEL_R(crate::FieldReader); +impl SEQSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SEQSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEQSEL_A::DISABLE), + 1 => Some(SEQSEL_A::DFF), + 2 => Some(SEQSEL_A::JK), + 3 => Some(SEQSEL_A::LATCH), + 4 => Some(SEQSEL_A::RS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == SEQSEL_A::DISABLE + } + #[doc = "Checks if the value of the field is `DFF`"] + #[inline(always)] + pub fn is_dff(&self) -> bool { + **self == SEQSEL_A::DFF + } + #[doc = "Checks if the value of the field is `JK`"] + #[inline(always)] + pub fn is_jk(&self) -> bool { + **self == SEQSEL_A::JK + } + #[doc = "Checks if the value of the field is `LATCH`"] + #[inline(always)] + pub fn is_latch(&self) -> bool { + **self == SEQSEL_A::LATCH + } + #[doc = "Checks if the value of the field is `RS`"] + #[inline(always)] + pub fn is_rs(&self) -> bool { + **self == SEQSEL_A::RS + } +} +impl core::ops::Deref for SEQSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEQSEL` writer - Sequential Selection"] +pub struct SEQSEL_W<'a> { + w: &'a mut W, +} +impl<'a> SEQSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SEQSEL_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Sequential logic is disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(SEQSEL_A::DISABLE) + } + #[doc = "D flip flop"] + #[inline(always)] + pub fn dff(self) -> &'a mut W { + self.variant(SEQSEL_A::DFF) + } + #[doc = "JK flip flop"] + #[inline(always)] + pub fn jk(self) -> &'a mut W { + self.variant(SEQSEL_A::JK) + } + #[doc = "D latch"] + #[inline(always)] + pub fn latch(self) -> &'a mut W { + self.variant(SEQSEL_A::LATCH) + } + #[doc = "RS latch"] + #[inline(always)] + pub fn rs(self) -> &'a mut W { + self.variant(SEQSEL_A::RS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Sequential Selection"] + #[inline(always)] + pub fn seqsel(&self) -> SEQSEL_R { + SEQSEL_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Sequential Selection"] + #[inline(always)] + pub fn seqsel(&mut self) -> SEQSEL_W { + SEQSEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SEQ Control x\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [seqctrl](index.html) module"] +pub struct SEQCTRL_SPEC; +impl crate::RegisterSpec for SEQCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [seqctrl::R](R) reader structure"] +impl crate::Readable for SEQCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [seqctrl::W](W) writer structure"] +impl crate::Writable for SEQCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SEQCTRL[%s] +to value 0"] +impl crate::Resettable for SEQCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/dac.rs b/pac/atsamc21n/src/dac.rs new file mode 100644 index 000000000000..255af9263600 --- /dev/null +++ b/pac/atsamc21n/src/dac.rs @@ -0,0 +1,73 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + #[doc = "0x01 - Control B"] + pub ctrlb: crate::Reg, + #[doc = "0x02 - Event Control"] + pub evctrl: crate::Reg, + _reserved3: [u8; 0x01], + #[doc = "0x04 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x05 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x06 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x07 - Status"] + pub status: crate::Reg, + #[doc = "0x08 - Data"] + pub data: crate::Reg, + _reserved8: [u8; 0x02], + #[doc = "0x0c - Data Buffer"] + pub databuf: crate::Reg, + _reserved9: [u8; 0x02], + #[doc = "0x10 - Synchronization Busy"] + pub syncbusy: crate::Reg, + #[doc = "0x14 - Debug Control"] + pub dbgctrl: crate::Reg, +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "Control B"] +pub mod ctrlb; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "Data"] +pub mod data; +#[doc = "DATABUF register accessor: an alias for `Reg`"] +pub type DATABUF = crate::Reg; +#[doc = "Data Buffer"] +pub mod databuf; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Busy"] +pub mod syncbusy; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; diff --git a/pac/atsamc21n/src/dac/ctrla.rs b/pac/atsamc21n/src/dac/ctrla.rs new file mode 100644 index 000000000000..3ff2fbd9c4d5 --- /dev/null +++ b/pac/atsamc21n/src/dac/ctrla.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/dac/ctrlb.rs b/pac/atsamc21n/src/dac/ctrlb.rs new file mode 100644 index 000000000000..ac7d537964e1 --- /dev/null +++ b/pac/atsamc21n/src/dac/ctrlb.rs @@ -0,0 +1,400 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EOEN` reader - External Output Enable"] +pub struct EOEN_R(crate::FieldReader); +impl EOEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EOEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EOEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EOEN` writer - External Output Enable"] +pub struct EOEN_W<'a> { + w: &'a mut W, +} +impl<'a> EOEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `IOEN` reader - Internal Output Enable"] +pub struct IOEN_R(crate::FieldReader); +impl IOEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IOEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IOEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IOEN` writer - Internal Output Enable"] +pub struct IOEN_W<'a> { + w: &'a mut W, +} +impl<'a> IOEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `LEFTADJ` reader - Left Adjusted Data"] +pub struct LEFTADJ_R(crate::FieldReader); +impl LEFTADJ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LEFTADJ_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LEFTADJ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LEFTADJ` writer - Left Adjusted Data"] +pub struct LEFTADJ_W<'a> { + w: &'a mut W, +} +impl<'a> LEFTADJ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `VPD` reader - Voltage Pump Disable"] +pub struct VPD_R(crate::FieldReader); +impl VPD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + VPD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VPD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VPD` writer - Voltage Pump Disable"] +pub struct VPD_W<'a> { + w: &'a mut W, +} +impl<'a> VPD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `DITHER` reader - Dither Enable"] +pub struct DITHER_R(crate::FieldReader); +impl DITHER_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DITHER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHER` writer - Dither Enable"] +pub struct DITHER_W<'a> { + w: &'a mut W, +} +impl<'a> DITHER_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Reference Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum REFSEL_A { + #[doc = "0: Internal 1.0V reference"] + INT1V = 0, + #[doc = "1: AVCC"] + AVCC = 1, + #[doc = "2: External reference"] + VREFP = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: REFSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `REFSEL` reader - Reference Selection"] +pub struct REFSEL_R(crate::FieldReader); +impl REFSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REFSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(REFSEL_A::INT1V), + 1 => Some(REFSEL_A::AVCC), + 2 => Some(REFSEL_A::VREFP), + _ => None, + } + } + #[doc = "Checks if the value of the field is `INT1V`"] + #[inline(always)] + pub fn is_int1v(&self) -> bool { + **self == REFSEL_A::INT1V + } + #[doc = "Checks if the value of the field is `AVCC`"] + #[inline(always)] + pub fn is_avcc(&self) -> bool { + **self == REFSEL_A::AVCC + } + #[doc = "Checks if the value of the field is `VREFP`"] + #[inline(always)] + pub fn is_vrefp(&self) -> bool { + **self == REFSEL_A::VREFP + } +} +impl core::ops::Deref for REFSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REFSEL` writer - Reference Selection"] +pub struct REFSEL_W<'a> { + w: &'a mut W, +} +impl<'a> REFSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: REFSEL_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Internal 1.0V reference"] + #[inline(always)] + pub fn int1v(self) -> &'a mut W { + self.variant(REFSEL_A::INT1V) + } + #[doc = "AVCC"] + #[inline(always)] + pub fn avcc(self) -> &'a mut W { + self.variant(REFSEL_A::AVCC) + } + #[doc = "External reference"] + #[inline(always)] + pub fn vrefp(self) -> &'a mut W { + self.variant(REFSEL_A::VREFP) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 6)) | ((value as u8 & 0x03) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - External Output Enable"] + #[inline(always)] + pub fn eoen(&self) -> EOEN_R { + EOEN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Internal Output Enable"] + #[inline(always)] + pub fn ioen(&self) -> IOEN_R { + IOEN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Left Adjusted Data"] + #[inline(always)] + pub fn leftadj(&self) -> LEFTADJ_R { + LEFTADJ_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Voltage Pump Disable"] + #[inline(always)] + pub fn vpd(&self) -> VPD_R { + VPD_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 5 - Dither Enable"] + #[inline(always)] + pub fn dither(&self) -> DITHER_R { + DITHER_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bits 6:7 - Reference Selection"] + #[inline(always)] + pub fn refsel(&self) -> REFSEL_R { + REFSEL_R::new(((self.bits >> 6) & 0x03) as u8) + } +} +impl W { + #[doc = "Bit 0 - External Output Enable"] + #[inline(always)] + pub fn eoen(&mut self) -> EOEN_W { + EOEN_W { w: self } + } + #[doc = "Bit 1 - Internal Output Enable"] + #[inline(always)] + pub fn ioen(&mut self) -> IOEN_W { + IOEN_W { w: self } + } + #[doc = "Bit 2 - Left Adjusted Data"] + #[inline(always)] + pub fn leftadj(&mut self) -> LEFTADJ_W { + LEFTADJ_W { w: self } + } + #[doc = "Bit 3 - Voltage Pump Disable"] + #[inline(always)] + pub fn vpd(&mut self) -> VPD_W { + VPD_W { w: self } + } + #[doc = "Bit 5 - Dither Enable"] + #[inline(always)] + pub fn dither(&mut self) -> DITHER_W { + DITHER_W { w: self } + } + #[doc = "Bits 6:7 - Reference Selection"] + #[inline(always)] + pub fn refsel(&mut self) -> REFSEL_W { + REFSEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/dac/data.rs b/pac/atsamc21n/src/dac/data.rs new file mode 100644 index 000000000000..d70d1a60e76f --- /dev/null +++ b/pac/atsamc21n/src/dac/data.rs @@ -0,0 +1,62 @@ +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` writer - Data value to be converted"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl W { + #[doc = "Bits 0:15 - Data value to be converted"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u16; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/dac/databuf.rs b/pac/atsamc21n/src/dac/databuf.rs new file mode 100644 index 000000000000..fc2aa61686cd --- /dev/null +++ b/pac/atsamc21n/src/dac/databuf.rs @@ -0,0 +1,62 @@ +#[doc = "Register `DATABUF` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATABUF` writer - Data Buffer"] +pub struct DATABUF_W<'a> { + w: &'a mut W, +} +impl<'a> DATABUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl W { + #[doc = "Bits 0:15 - Data Buffer"] + #[inline(always)] + pub fn databuf(&mut self) -> DATABUF_W { + DATABUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Buffer\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [databuf](index.html) module"] +pub struct DATABUF_SPEC; +impl crate::RegisterSpec for DATABUF_SPEC { + type Ux = u16; +} +#[doc = "`write(|w| ..)` method takes [databuf::W](W) writer structure"] +impl crate::Writable for DATABUF_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATABUF to value 0"] +impl crate::Resettable for DATABUF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/dac/dbgctrl.rs b/pac/atsamc21n/src/dac/dbgctrl.rs new file mode 100644 index 000000000000..53636eb2b339 --- /dev/null +++ b/pac/atsamc21n/src/dac/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Debug Run"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Debug Run"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/dac/evctrl.rs b/pac/atsamc21n/src/dac/evctrl.rs new file mode 100644 index 000000000000..1032a853887d --- /dev/null +++ b/pac/atsamc21n/src/dac/evctrl.rs @@ -0,0 +1,207 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `STARTEI` reader - Start Conversion Event Input"] +pub struct STARTEI_R(crate::FieldReader); +impl STARTEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STARTEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STARTEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STARTEI` writer - Start Conversion Event Input"] +pub struct STARTEI_W<'a> { + w: &'a mut W, +} +impl<'a> STARTEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `EMPTYEO` reader - Data Buffer Empty Event Output"] +pub struct EMPTYEO_R(crate::FieldReader); +impl EMPTYEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EMPTYEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EMPTYEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EMPTYEO` writer - Data Buffer Empty Event Output"] +pub struct EMPTYEO_W<'a> { + w: &'a mut W, +} +impl<'a> EMPTYEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `INVEI` reader - Invert Event Input"] +pub struct INVEI_R(crate::FieldReader); +impl INVEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEI` writer - Invert Event Input"] +pub struct INVEI_W<'a> { + w: &'a mut W, +} +impl<'a> INVEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Start Conversion Event Input"] + #[inline(always)] + pub fn startei(&self) -> STARTEI_R { + STARTEI_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Data Buffer Empty Event Output"] + #[inline(always)] + pub fn emptyeo(&self) -> EMPTYEO_R { + EMPTYEO_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Invert Event Input"] + #[inline(always)] + pub fn invei(&self) -> INVEI_R { + INVEI_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Start Conversion Event Input"] + #[inline(always)] + pub fn startei(&mut self) -> STARTEI_W { + STARTEI_W { w: self } + } + #[doc = "Bit 1 - Data Buffer Empty Event Output"] + #[inline(always)] + pub fn emptyeo(&mut self) -> EMPTYEO_W { + EMPTYEO_W { w: self } + } + #[doc = "Bit 2 - Invert Event Input"] + #[inline(always)] + pub fn invei(&mut self) -> INVEI_W { + INVEI_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/dac/intenclr.rs b/pac/atsamc21n/src/dac/intenclr.rs new file mode 100644 index 000000000000..408feebf63ca --- /dev/null +++ b/pac/atsamc21n/src/dac/intenclr.rs @@ -0,0 +1,160 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `UNDERRUN` reader - Underrun Interrupt Enable"] +pub struct UNDERRUN_R(crate::FieldReader); +impl UNDERRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UNDERRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for UNDERRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `UNDERRUN` writer - Underrun Interrupt Enable"] +pub struct UNDERRUN_W<'a> { + w: &'a mut W, +} +impl<'a> UNDERRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `EMPTY` reader - Data Buffer Empty Interrupt Enable"] +pub struct EMPTY_R(crate::FieldReader); +impl EMPTY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EMPTY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EMPTY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EMPTY` writer - Data Buffer Empty Interrupt Enable"] +pub struct EMPTY_W<'a> { + w: &'a mut W, +} +impl<'a> EMPTY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - Underrun Interrupt Enable"] + #[inline(always)] + pub fn underrun(&self) -> UNDERRUN_R { + UNDERRUN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Data Buffer Empty Interrupt Enable"] + #[inline(always)] + pub fn empty(&self) -> EMPTY_R { + EMPTY_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Underrun Interrupt Enable"] + #[inline(always)] + pub fn underrun(&mut self) -> UNDERRUN_W { + UNDERRUN_W { w: self } + } + #[doc = "Bit 1 - Data Buffer Empty Interrupt Enable"] + #[inline(always)] + pub fn empty(&mut self) -> EMPTY_W { + EMPTY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/dac/intenset.rs b/pac/atsamc21n/src/dac/intenset.rs new file mode 100644 index 000000000000..db38e69ed2e5 --- /dev/null +++ b/pac/atsamc21n/src/dac/intenset.rs @@ -0,0 +1,160 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `UNDERRUN` reader - Underrun Interrupt Enable"] +pub struct UNDERRUN_R(crate::FieldReader); +impl UNDERRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UNDERRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for UNDERRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `UNDERRUN` writer - Underrun Interrupt Enable"] +pub struct UNDERRUN_W<'a> { + w: &'a mut W, +} +impl<'a> UNDERRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `EMPTY` reader - Data Buffer Empty Interrupt Enable"] +pub struct EMPTY_R(crate::FieldReader); +impl EMPTY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EMPTY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EMPTY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EMPTY` writer - Data Buffer Empty Interrupt Enable"] +pub struct EMPTY_W<'a> { + w: &'a mut W, +} +impl<'a> EMPTY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - Underrun Interrupt Enable"] + #[inline(always)] + pub fn underrun(&self) -> UNDERRUN_R { + UNDERRUN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Data Buffer Empty Interrupt Enable"] + #[inline(always)] + pub fn empty(&self) -> EMPTY_R { + EMPTY_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Underrun Interrupt Enable"] + #[inline(always)] + pub fn underrun(&mut self) -> UNDERRUN_W { + UNDERRUN_W { w: self } + } + #[doc = "Bit 1 - Data Buffer Empty Interrupt Enable"] + #[inline(always)] + pub fn empty(&mut self) -> EMPTY_W { + EMPTY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/dac/intflag.rs b/pac/atsamc21n/src/dac/intflag.rs new file mode 100644 index 000000000000..6779ed161d08 --- /dev/null +++ b/pac/atsamc21n/src/dac/intflag.rs @@ -0,0 +1,160 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `UNDERRUN` reader - Underrun"] +pub struct UNDERRUN_R(crate::FieldReader); +impl UNDERRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UNDERRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for UNDERRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `UNDERRUN` writer - Underrun"] +pub struct UNDERRUN_W<'a> { + w: &'a mut W, +} +impl<'a> UNDERRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `EMPTY` reader - Data Buffer Empty"] +pub struct EMPTY_R(crate::FieldReader); +impl EMPTY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EMPTY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EMPTY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EMPTY` writer - Data Buffer Empty"] +pub struct EMPTY_W<'a> { + w: &'a mut W, +} +impl<'a> EMPTY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - Underrun"] + #[inline(always)] + pub fn underrun(&self) -> UNDERRUN_R { + UNDERRUN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Data Buffer Empty"] + #[inline(always)] + pub fn empty(&self) -> EMPTY_R { + EMPTY_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Underrun"] + #[inline(always)] + pub fn underrun(&mut self) -> UNDERRUN_W { + UNDERRUN_W { w: self } + } + #[doc = "Bit 1 - Data Buffer Empty"] + #[inline(always)] + pub fn empty(&mut self) -> EMPTY_W { + EMPTY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/dac/status.rs b/pac/atsamc21n/src/dac/status.rs new file mode 100644 index 000000000000..9b5a27716dab --- /dev/null +++ b/pac/atsamc21n/src/dac/status.rs @@ -0,0 +1,53 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `READY` reader - Ready"] +pub struct READY_R(crate::FieldReader); +impl READY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + READY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for READY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Ready"] + #[inline(always)] + pub fn ready(&self) -> READY_R { + READY_R::new((self.bits & 0x01) != 0) + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/dac/syncbusy.rs b/pac/atsamc21n/src/dac/syncbusy.rs new file mode 100644 index 000000000000..490533dae28e --- /dev/null +++ b/pac/atsamc21n/src/dac/syncbusy.rs @@ -0,0 +1,113 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` reader - Data"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATABUF` reader - Data Buffer"] +pub struct DATABUF_R(crate::FieldReader); +impl DATABUF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DATABUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATABUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Data"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Data Buffer"] + #[inline(always)] + pub fn databuf(&self) -> DATABUF_R { + DATABUF_R::new(((self.bits >> 3) & 0x01) != 0) + } +} +#[doc = "Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/divas.rs b/pac/atsamc21n/src/divas.rs new file mode 100644 index 000000000000..dbc2f5f226da --- /dev/null +++ b/pac/atsamc21n/src/divas.rs @@ -0,0 +1,48 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrla: crate::Reg, + _reserved1: [u8; 0x03], + #[doc = "0x04 - Status"] + pub status: crate::Reg, + _reserved2: [u8; 0x03], + #[doc = "0x08 - Dividend"] + pub dividend: crate::Reg, + #[doc = "0x0c - Divisor"] + pub divisor: crate::Reg, + #[doc = "0x10 - Result"] + pub result: crate::Reg, + #[doc = "0x14 - Remainder"] + pub rem: crate::Reg, + #[doc = "0x18 - Square Root Input"] + pub sqrnum: crate::Reg, +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control"] +pub mod ctrla; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "DIVIDEND register accessor: an alias for `Reg`"] +pub type DIVIDEND = crate::Reg; +#[doc = "Dividend"] +pub mod dividend; +#[doc = "DIVISOR register accessor: an alias for `Reg`"] +pub type DIVISOR = crate::Reg; +#[doc = "Divisor"] +pub mod divisor; +#[doc = "RESULT register accessor: an alias for `Reg`"] +pub type RESULT = crate::Reg; +#[doc = "Result"] +pub mod result; +#[doc = "REM register accessor: an alias for `Reg`"] +pub type REM = crate::Reg; +#[doc = "Remainder"] +pub mod rem; +#[doc = "SQRNUM register accessor: an alias for `Reg`"] +pub type SQRNUM = crate::Reg; +#[doc = "Square Root Input"] +pub mod sqrnum; diff --git a/pac/atsamc21n/src/divas/ctrla.rs b/pac/atsamc21n/src/divas/ctrla.rs new file mode 100644 index 000000000000..7f79349da05c --- /dev/null +++ b/pac/atsamc21n/src/divas/ctrla.rs @@ -0,0 +1,160 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SIGNED` reader - Signed"] +pub struct SIGNED_R(crate::FieldReader); +impl SIGNED_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SIGNED_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SIGNED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SIGNED` writer - Signed"] +pub struct SIGNED_W<'a> { + w: &'a mut W, +} +impl<'a> SIGNED_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `DLZ` reader - Disable Leading Zero Optimization"] +pub struct DLZ_R(crate::FieldReader); +impl DLZ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DLZ_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DLZ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DLZ` writer - Disable Leading Zero Optimization"] +pub struct DLZ_W<'a> { + w: &'a mut W, +} +impl<'a> DLZ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - Signed"] + #[inline(always)] + pub fn signed(&self) -> SIGNED_R { + SIGNED_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Disable Leading Zero Optimization"] + #[inline(always)] + pub fn dlz(&self) -> DLZ_R { + DLZ_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Signed"] + #[inline(always)] + pub fn signed(&mut self) -> SIGNED_W { + SIGNED_W { w: self } + } + #[doc = "Bit 1 - Disable Leading Zero Optimization"] + #[inline(always)] + pub fn dlz(&mut self) -> DLZ_W { + DLZ_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/divas/dividend.rs b/pac/atsamc21n/src/divas/dividend.rs new file mode 100644 index 000000000000..215f44261a6c --- /dev/null +++ b/pac/atsamc21n/src/divas/dividend.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DIVIDEND` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIVIDEND` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIVIDEND` reader - DIVIDEND"] +pub struct DIVIDEND_R(crate::FieldReader); +impl DIVIDEND_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + DIVIDEND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIVIDEND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIVIDEND` writer - DIVIDEND"] +pub struct DIVIDEND_W<'a> { + w: &'a mut W, +} +impl<'a> DIVIDEND_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - DIVIDEND"] + #[inline(always)] + pub fn dividend(&self) -> DIVIDEND_R { + DIVIDEND_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - DIVIDEND"] + #[inline(always)] + pub fn dividend(&mut self) -> DIVIDEND_W { + DIVIDEND_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Dividend\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dividend](index.html) module"] +pub struct DIVIDEND_SPEC; +impl crate::RegisterSpec for DIVIDEND_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dividend::R](R) reader structure"] +impl crate::Readable for DIVIDEND_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dividend::W](W) writer structure"] +impl crate::Writable for DIVIDEND_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DIVIDEND to value 0"] +impl crate::Resettable for DIVIDEND_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/divas/divisor.rs b/pac/atsamc21n/src/divas/divisor.rs new file mode 100644 index 000000000000..b711870a5cd6 --- /dev/null +++ b/pac/atsamc21n/src/divas/divisor.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DIVISOR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIVISOR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIVISOR` reader - DIVISOR"] +pub struct DIVISOR_R(crate::FieldReader); +impl DIVISOR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + DIVISOR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIVISOR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIVISOR` writer - DIVISOR"] +pub struct DIVISOR_W<'a> { + w: &'a mut W, +} +impl<'a> DIVISOR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - DIVISOR"] + #[inline(always)] + pub fn divisor(&self) -> DIVISOR_R { + DIVISOR_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - DIVISOR"] + #[inline(always)] + pub fn divisor(&mut self) -> DIVISOR_W { + DIVISOR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Divisor\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [divisor](index.html) module"] +pub struct DIVISOR_SPEC; +impl crate::RegisterSpec for DIVISOR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [divisor::R](R) reader structure"] +impl crate::Readable for DIVISOR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [divisor::W](W) writer structure"] +impl crate::Writable for DIVISOR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DIVISOR to value 0"] +impl crate::Resettable for DIVISOR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/divas/rem.rs b/pac/atsamc21n/src/divas/rem.rs new file mode 100644 index 000000000000..76f3a90878ed --- /dev/null +++ b/pac/atsamc21n/src/divas/rem.rs @@ -0,0 +1,53 @@ +#[doc = "Register `REM` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `REM` reader - REM"] +pub struct REM_R(crate::FieldReader); +impl REM_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + REM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - REM"] + #[inline(always)] + pub fn rem(&self) -> REM_R { + REM_R::new(self.bits as u32) + } +} +#[doc = "Remainder\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rem](index.html) module"] +pub struct REM_SPEC; +impl crate::RegisterSpec for REM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rem::R](R) reader structure"] +impl crate::Readable for REM_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets REM to value 0"] +impl crate::Resettable for REM_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/divas/result.rs b/pac/atsamc21n/src/divas/result.rs new file mode 100644 index 000000000000..85fc1a025f9e --- /dev/null +++ b/pac/atsamc21n/src/divas/result.rs @@ -0,0 +1,53 @@ +#[doc = "Register `RESULT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `RESULT` reader - RESULT"] +pub struct RESULT_R(crate::FieldReader); +impl RESULT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + RESULT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESULT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - RESULT"] + #[inline(always)] + pub fn result(&self) -> RESULT_R { + RESULT_R::new(self.bits as u32) + } +} +#[doc = "Result\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [result](index.html) module"] +pub struct RESULT_SPEC; +impl crate::RegisterSpec for RESULT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [result::R](R) reader structure"] +impl crate::Readable for RESULT_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets RESULT to value 0"] +impl crate::Resettable for RESULT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/divas/sqrnum.rs b/pac/atsamc21n/src/divas/sqrnum.rs new file mode 100644 index 000000000000..cc0ce6806beb --- /dev/null +++ b/pac/atsamc21n/src/divas/sqrnum.rs @@ -0,0 +1,103 @@ +#[doc = "Register `SQRNUM` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SQRNUM` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SQRNUM` reader - Square Root Input"] +pub struct SQRNUM_R(crate::FieldReader); +impl SQRNUM_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + SQRNUM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SQRNUM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SQRNUM` writer - Square Root Input"] +pub struct SQRNUM_W<'a> { + w: &'a mut W, +} +impl<'a> SQRNUM_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Square Root Input"] + #[inline(always)] + pub fn sqrnum(&self) -> SQRNUM_R { + SQRNUM_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Square Root Input"] + #[inline(always)] + pub fn sqrnum(&mut self) -> SQRNUM_W { + SQRNUM_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Square Root Input\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sqrnum](index.html) module"] +pub struct SQRNUM_SPEC; +impl crate::RegisterSpec for SQRNUM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [sqrnum::R](R) reader structure"] +impl crate::Readable for SQRNUM_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [sqrnum::W](W) writer structure"] +impl crate::Writable for SQRNUM_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SQRNUM to value 0"] +impl crate::Resettable for SQRNUM_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/divas/status.rs b/pac/atsamc21n/src/divas/status.rs new file mode 100644 index 000000000000..feffbccec659 --- /dev/null +++ b/pac/atsamc21n/src/divas/status.rs @@ -0,0 +1,160 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BUSY` reader - DIVAS Accelerator Busy"] +pub struct BUSY_R(crate::FieldReader); +impl BUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSY` writer - DIVAS Accelerator Busy"] +pub struct BUSY_W<'a> { + w: &'a mut W, +} +impl<'a> BUSY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `DBZ` reader - Writing a one to this bit clears DBZ to zero"] +pub struct DBZ_R(crate::FieldReader); +impl DBZ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBZ_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBZ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBZ` writer - Writing a one to this bit clears DBZ to zero"] +pub struct DBZ_W<'a> { + w: &'a mut W, +} +impl<'a> DBZ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - DIVAS Accelerator Busy"] + #[inline(always)] + pub fn busy(&self) -> BUSY_R { + BUSY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Writing a one to this bit clears DBZ to zero"] + #[inline(always)] + pub fn dbz(&self) -> DBZ_R { + DBZ_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - DIVAS Accelerator Busy"] + #[inline(always)] + pub fn busy(&mut self) -> BUSY_W { + BUSY_W { w: self } + } + #[doc = "Bit 1 - Writing a one to this bit clears DBZ to zero"] + #[inline(always)] + pub fn dbz(&mut self) -> DBZ_W { + DBZ_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/dmac.rs b/pac/atsamc21n/src/dmac.rs new file mode 100644 index 000000000000..c23d36697550 --- /dev/null +++ b/pac/atsamc21n/src/dmac.rs @@ -0,0 +1,148 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrl: crate::Reg, + #[doc = "0x02 - CRC Control"] + pub crcctrl: crate::Reg, + #[doc = "0x04 - CRC Data Input"] + pub crcdatain: crate::Reg, + #[doc = "0x08 - CRC Checksum"] + pub crcchksum: crate::Reg, + #[doc = "0x0c - CRC Status"] + pub crcstatus: crate::Reg, + #[doc = "0x0d - Debug Control"] + pub dbgctrl: crate::Reg, + #[doc = "0x0e - QOS Control"] + pub qosctrl: crate::Reg, + _reserved7: [u8; 0x01], + #[doc = "0x10 - Software Trigger Control"] + pub swtrigctrl: crate::Reg, + #[doc = "0x14 - Priority Control 0"] + pub prictrl0: crate::Reg, + _reserved9: [u8; 0x08], + #[doc = "0x20 - Interrupt Pending"] + pub intpend: crate::Reg, + _reserved10: [u8; 0x02], + #[doc = "0x24 - Interrupt Status"] + pub intstatus: crate::Reg, + #[doc = "0x28 - Busy Channels"] + pub busych: crate::Reg, + #[doc = "0x2c - Pending Channels"] + pub pendch: crate::Reg, + #[doc = "0x30 - Active Channel and Levels"] + pub active: crate::Reg, + #[doc = "0x34 - Descriptor Memory Section Base Address"] + pub baseaddr: crate::Reg, + #[doc = "0x38 - Write-Back Memory Section Base Address"] + pub wrbaddr: crate::Reg, + _reserved16: [u8; 0x03], + #[doc = "0x3f - Channel ID"] + pub chid: crate::Reg, + #[doc = "0x40 - Channel Control A"] + pub chctrla: crate::Reg, + _reserved18: [u8; 0x03], + #[doc = "0x44 - Channel Control B"] + pub chctrlb: crate::Reg, + _reserved19: [u8; 0x04], + #[doc = "0x4c - Channel Interrupt Enable Clear"] + pub chintenclr: crate::Reg, + #[doc = "0x4d - Channel Interrupt Enable Set"] + pub chintenset: crate::Reg, + #[doc = "0x4e - Channel Interrupt Flag Status and Clear"] + pub chintflag: crate::Reg, + #[doc = "0x4f - Channel Status"] + pub chstatus: crate::Reg, +} +#[doc = "CTRL register accessor: an alias for `Reg`"] +pub type CTRL = crate::Reg; +#[doc = "Control"] +pub mod ctrl; +#[doc = "CRCCTRL register accessor: an alias for `Reg`"] +pub type CRCCTRL = crate::Reg; +#[doc = "CRC Control"] +pub mod crcctrl; +#[doc = "CRCDATAIN register accessor: an alias for `Reg`"] +pub type CRCDATAIN = crate::Reg; +#[doc = "CRC Data Input"] +pub mod crcdatain; +#[doc = "CRCCHKSUM register accessor: an alias for `Reg`"] +pub type CRCCHKSUM = crate::Reg; +#[doc = "CRC Checksum"] +pub mod crcchksum; +#[doc = "CRCSTATUS register accessor: an alias for `Reg`"] +pub type CRCSTATUS = crate::Reg; +#[doc = "CRC Status"] +pub mod crcstatus; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "QOSCTRL register accessor: an alias for `Reg`"] +pub type QOSCTRL = crate::Reg; +#[doc = "QOS Control"] +pub mod qosctrl; +#[doc = "SWTRIGCTRL register accessor: an alias for `Reg`"] +pub type SWTRIGCTRL = crate::Reg; +#[doc = "Software Trigger Control"] +pub mod swtrigctrl; +#[doc = "PRICTRL0 register accessor: an alias for `Reg`"] +pub type PRICTRL0 = crate::Reg; +#[doc = "Priority Control 0"] +pub mod prictrl0; +#[doc = "INTPEND register accessor: an alias for `Reg`"] +pub type INTPEND = crate::Reg; +#[doc = "Interrupt Pending"] +pub mod intpend; +#[doc = "INTSTATUS register accessor: an alias for `Reg`"] +pub type INTSTATUS = crate::Reg; +#[doc = "Interrupt Status"] +pub mod intstatus; +#[doc = "BUSYCH register accessor: an alias for `Reg`"] +pub type BUSYCH = crate::Reg; +#[doc = "Busy Channels"] +pub mod busych; +#[doc = "PENDCH register accessor: an alias for `Reg`"] +pub type PENDCH = crate::Reg; +#[doc = "Pending Channels"] +pub mod pendch; +#[doc = "ACTIVE register accessor: an alias for `Reg`"] +pub type ACTIVE = crate::Reg; +#[doc = "Active Channel and Levels"] +pub mod active; +#[doc = "BASEADDR register accessor: an alias for `Reg`"] +pub type BASEADDR = crate::Reg; +#[doc = "Descriptor Memory Section Base Address"] +pub mod baseaddr; +#[doc = "WRBADDR register accessor: an alias for `Reg`"] +pub type WRBADDR = crate::Reg; +#[doc = "Write-Back Memory Section Base Address"] +pub mod wrbaddr; +#[doc = "CHID register accessor: an alias for `Reg`"] +pub type CHID = crate::Reg; +#[doc = "Channel ID"] +pub mod chid; +#[doc = "CHCTRLA register accessor: an alias for `Reg`"] +pub type CHCTRLA = crate::Reg; +#[doc = "Channel Control A"] +pub mod chctrla; +#[doc = "CHCTRLB register accessor: an alias for `Reg`"] +pub type CHCTRLB = crate::Reg; +#[doc = "Channel Control B"] +pub mod chctrlb; +#[doc = "CHINTENCLR register accessor: an alias for `Reg`"] +pub type CHINTENCLR = crate::Reg; +#[doc = "Channel Interrupt Enable Clear"] +pub mod chintenclr; +#[doc = "CHINTENSET register accessor: an alias for `Reg`"] +pub type CHINTENSET = crate::Reg; +#[doc = "Channel Interrupt Enable Set"] +pub mod chintenset; +#[doc = "CHINTFLAG register accessor: an alias for `Reg`"] +pub type CHINTFLAG = crate::Reg; +#[doc = "Channel Interrupt Flag Status and Clear"] +pub mod chintflag; +#[doc = "CHSTATUS register accessor: an alias for `Reg`"] +pub type CHSTATUS = crate::Reg; +#[doc = "Channel Status"] +pub mod chstatus; diff --git a/pac/atsamc21n/src/dmac/active.rs b/pac/atsamc21n/src/dmac/active.rs new file mode 100644 index 000000000000..c3cc5a0420bc --- /dev/null +++ b/pac/atsamc21n/src/dmac/active.rs @@ -0,0 +1,173 @@ +#[doc = "Register `ACTIVE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `LVLEX0` reader - Level 0 Channel Trigger Request Executing"] +pub struct LVLEX0_R(crate::FieldReader); +impl LVLEX0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LVLEX0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEX0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLEX1` reader - Level 1 Channel Trigger Request Executing"] +pub struct LVLEX1_R(crate::FieldReader); +impl LVLEX1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LVLEX1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEX1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLEX2` reader - Level 2 Channel Trigger Request Executing"] +pub struct LVLEX2_R(crate::FieldReader); +impl LVLEX2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LVLEX2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEX2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLEX3` reader - Level 3 Channel Trigger Request Executing"] +pub struct LVLEX3_R(crate::FieldReader); +impl LVLEX3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LVLEX3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEX3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ID` reader - Active Channel ID"] +pub struct ID_R(crate::FieldReader); +impl ID_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ID_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ID_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ABUSY` reader - Active Channel Busy"] +pub struct ABUSY_R(crate::FieldReader); +impl ABUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ABUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ABUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BTCNT` reader - Active Channel Block Transfer Count"] +pub struct BTCNT_R(crate::FieldReader); +impl BTCNT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BTCNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BTCNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Level 0 Channel Trigger Request Executing"] + #[inline(always)] + pub fn lvlex0(&self) -> LVLEX0_R { + LVLEX0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Level 1 Channel Trigger Request Executing"] + #[inline(always)] + pub fn lvlex1(&self) -> LVLEX1_R { + LVLEX1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Level 2 Channel Trigger Request Executing"] + #[inline(always)] + pub fn lvlex2(&self) -> LVLEX2_R { + LVLEX2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Level 3 Channel Trigger Request Executing"] + #[inline(always)] + pub fn lvlex3(&self) -> LVLEX3_R { + LVLEX3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bits 8:12 - Active Channel ID"] + #[inline(always)] + pub fn id(&self) -> ID_R { + ID_R::new(((self.bits >> 8) & 0x1f) as u8) + } + #[doc = "Bit 15 - Active Channel Busy"] + #[inline(always)] + pub fn abusy(&self) -> ABUSY_R { + ABUSY_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:31 - Active Channel Block Transfer Count"] + #[inline(always)] + pub fn btcnt(&self) -> BTCNT_R { + BTCNT_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[doc = "Active Channel and Levels\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [active](index.html) module"] +pub struct ACTIVE_SPEC; +impl crate::RegisterSpec for ACTIVE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [active::R](R) reader structure"] +impl crate::Readable for ACTIVE_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets ACTIVE to value 0"] +impl crate::Resettable for ACTIVE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/dmac/baseaddr.rs b/pac/atsamc21n/src/dmac/baseaddr.rs new file mode 100644 index 000000000000..cec8c8cf0777 --- /dev/null +++ b/pac/atsamc21n/src/dmac/baseaddr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `BASEADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BASEADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BASEADDR` reader - Descriptor Memory Base Address"] +pub struct BASEADDR_R(crate::FieldReader); +impl BASEADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + BASEADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BASEADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BASEADDR` writer - Descriptor Memory Base Address"] +pub struct BASEADDR_W<'a> { + w: &'a mut W, +} +impl<'a> BASEADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Descriptor Memory Base Address"] + #[inline(always)] + pub fn baseaddr(&self) -> BASEADDR_R { + BASEADDR_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Descriptor Memory Base Address"] + #[inline(always)] + pub fn baseaddr(&mut self) -> BASEADDR_W { + BASEADDR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Descriptor Memory Section Base Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baseaddr](index.html) module"] +pub struct BASEADDR_SPEC; +impl crate::RegisterSpec for BASEADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [baseaddr::R](R) reader structure"] +impl crate::Readable for BASEADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baseaddr::W](W) writer structure"] +impl crate::Writable for BASEADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BASEADDR to value 0"] +impl crate::Resettable for BASEADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/dmac/busych.rs b/pac/atsamc21n/src/dmac/busych.rs new file mode 100644 index 000000000000..6f9419d5828b --- /dev/null +++ b/pac/atsamc21n/src/dmac/busych.rs @@ -0,0 +1,273 @@ +#[doc = "Register `BUSYCH` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `BUSYCH0` reader - Busy Channel 0"] +pub struct BUSYCH0_R(crate::FieldReader); +impl BUSYCH0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH1` reader - Busy Channel 1"] +pub struct BUSYCH1_R(crate::FieldReader); +impl BUSYCH1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH2` reader - Busy Channel 2"] +pub struct BUSYCH2_R(crate::FieldReader); +impl BUSYCH2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH3` reader - Busy Channel 3"] +pub struct BUSYCH3_R(crate::FieldReader); +impl BUSYCH3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH4` reader - Busy Channel 4"] +pub struct BUSYCH4_R(crate::FieldReader); +impl BUSYCH4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH5` reader - Busy Channel 5"] +pub struct BUSYCH5_R(crate::FieldReader); +impl BUSYCH5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH6` reader - Busy Channel 6"] +pub struct BUSYCH6_R(crate::FieldReader); +impl BUSYCH6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH7` reader - Busy Channel 7"] +pub struct BUSYCH7_R(crate::FieldReader); +impl BUSYCH7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH8` reader - Busy Channel 8"] +pub struct BUSYCH8_R(crate::FieldReader); +impl BUSYCH8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH9` reader - Busy Channel 9"] +pub struct BUSYCH9_R(crate::FieldReader); +impl BUSYCH9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH10` reader - Busy Channel 10"] +pub struct BUSYCH10_R(crate::FieldReader); +impl BUSYCH10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH11` reader - Busy Channel 11"] +pub struct BUSYCH11_R(crate::FieldReader); +impl BUSYCH11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSYCH11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Busy Channel 0"] + #[inline(always)] + pub fn busych0(&self) -> BUSYCH0_R { + BUSYCH0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Busy Channel 1"] + #[inline(always)] + pub fn busych1(&self) -> BUSYCH1_R { + BUSYCH1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Busy Channel 2"] + #[inline(always)] + pub fn busych2(&self) -> BUSYCH2_R { + BUSYCH2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Busy Channel 3"] + #[inline(always)] + pub fn busych3(&self) -> BUSYCH3_R { + BUSYCH3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Busy Channel 4"] + #[inline(always)] + pub fn busych4(&self) -> BUSYCH4_R { + BUSYCH4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Busy Channel 5"] + #[inline(always)] + pub fn busych5(&self) -> BUSYCH5_R { + BUSYCH5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Busy Channel 6"] + #[inline(always)] + pub fn busych6(&self) -> BUSYCH6_R { + BUSYCH6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Busy Channel 7"] + #[inline(always)] + pub fn busych7(&self) -> BUSYCH7_R { + BUSYCH7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Busy Channel 8"] + #[inline(always)] + pub fn busych8(&self) -> BUSYCH8_R { + BUSYCH8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Busy Channel 9"] + #[inline(always)] + pub fn busych9(&self) -> BUSYCH9_R { + BUSYCH9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Busy Channel 10"] + #[inline(always)] + pub fn busych10(&self) -> BUSYCH10_R { + BUSYCH10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Busy Channel 11"] + #[inline(always)] + pub fn busych11(&self) -> BUSYCH11_R { + BUSYCH11_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +#[doc = "Busy Channels\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [busych](index.html) module"] +pub struct BUSYCH_SPEC; +impl crate::RegisterSpec for BUSYCH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [busych::R](R) reader structure"] +impl crate::Readable for BUSYCH_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets BUSYCH to value 0"] +impl crate::Resettable for BUSYCH_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/dmac/chctrla.rs b/pac/atsamc21n/src/dmac/chctrla.rs new file mode 100644 index 000000000000..22e8d456e05c --- /dev/null +++ b/pac/atsamc21n/src/dmac/chctrla.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CHCTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHCTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Channel Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Channel Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Channel Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Channel Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Channel run in standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Channel run in standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - Channel Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 6 - Channel run in standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Channel Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 6 - Channel run in standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chctrla](index.html) module"] +pub struct CHCTRLA_SPEC; +impl crate::RegisterSpec for CHCTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [chctrla::R](R) reader structure"] +impl crate::Readable for CHCTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chctrla::W](W) writer structure"] +impl crate::Writable for CHCTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHCTRLA to value 0"] +impl crate::Resettable for CHCTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/dmac/chctrlb.rs b/pac/atsamc21n/src/dmac/chctrlb.rs new file mode 100644 index 000000000000..2af4d09ad193 --- /dev/null +++ b/pac/atsamc21n/src/dmac/chctrlb.rs @@ -0,0 +1,1487 @@ +#[doc = "Register `CHCTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHCTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Event Input Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EVACT_A { + #[doc = "0: No action"] + NOACT = 0, + #[doc = "1: Transfer and periodic transfer trigger"] + TRIG = 1, + #[doc = "2: Conditional transfer trigger"] + CTRIG = 2, + #[doc = "3: Conditional block transfer"] + CBLOCK = 3, + #[doc = "4: Channel suspend operation"] + SUSPEND = 4, + #[doc = "5: Channel resume operation"] + RESUME = 5, + #[doc = "6: Skip next block suspend action"] + SSKIP = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EVACT_A) -> Self { + variant as _ + } +} +#[doc = "Field `EVACT` reader - Event Input Action"] +pub struct EVACT_R(crate::FieldReader); +impl EVACT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(EVACT_A::NOACT), + 1 => Some(EVACT_A::TRIG), + 2 => Some(EVACT_A::CTRIG), + 3 => Some(EVACT_A::CBLOCK), + 4 => Some(EVACT_A::SUSPEND), + 5 => Some(EVACT_A::RESUME), + 6 => Some(EVACT_A::SSKIP), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NOACT`"] + #[inline(always)] + pub fn is_noact(&self) -> bool { + **self == EVACT_A::NOACT + } + #[doc = "Checks if the value of the field is `TRIG`"] + #[inline(always)] + pub fn is_trig(&self) -> bool { + **self == EVACT_A::TRIG + } + #[doc = "Checks if the value of the field is `CTRIG`"] + #[inline(always)] + pub fn is_ctrig(&self) -> bool { + **self == EVACT_A::CTRIG + } + #[doc = "Checks if the value of the field is `CBLOCK`"] + #[inline(always)] + pub fn is_cblock(&self) -> bool { + **self == EVACT_A::CBLOCK + } + #[doc = "Checks if the value of the field is `SUSPEND`"] + #[inline(always)] + pub fn is_suspend(&self) -> bool { + **self == EVACT_A::SUSPEND + } + #[doc = "Checks if the value of the field is `RESUME`"] + #[inline(always)] + pub fn is_resume(&self) -> bool { + **self == EVACT_A::RESUME + } + #[doc = "Checks if the value of the field is `SSKIP`"] + #[inline(always)] + pub fn is_sskip(&self) -> bool { + **self == EVACT_A::SSKIP + } +} +impl core::ops::Deref for EVACT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT` writer - Event Input Action"] +pub struct EVACT_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EVACT_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn noact(self) -> &'a mut W { + self.variant(EVACT_A::NOACT) + } + #[doc = "Transfer and periodic transfer trigger"] + #[inline(always)] + pub fn trig(self) -> &'a mut W { + self.variant(EVACT_A::TRIG) + } + #[doc = "Conditional transfer trigger"] + #[inline(always)] + pub fn ctrig(self) -> &'a mut W { + self.variant(EVACT_A::CTRIG) + } + #[doc = "Conditional block transfer"] + #[inline(always)] + pub fn cblock(self) -> &'a mut W { + self.variant(EVACT_A::CBLOCK) + } + #[doc = "Channel suspend operation"] + #[inline(always)] + pub fn suspend(self) -> &'a mut W { + self.variant(EVACT_A::SUSPEND) + } + #[doc = "Channel resume operation"] + #[inline(always)] + pub fn resume(self) -> &'a mut W { + self.variant(EVACT_A::RESUME) + } + #[doc = "Skip next block suspend action"] + #[inline(always)] + pub fn sskip(self) -> &'a mut W { + self.variant(EVACT_A::SSKIP) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Field `EVIE` reader - Channel Event Input Enable"] +pub struct EVIE_R(crate::FieldReader); +impl EVIE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVIE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVIE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVIE` writer - Channel Event Input Enable"] +pub struct EVIE_W<'a> { + w: &'a mut W, +} +impl<'a> EVIE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `EVOE` reader - Channel Event Output Enable"] +pub struct EVOE_R(crate::FieldReader); +impl EVOE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVOE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVOE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVOE` writer - Channel Event Output Enable"] +pub struct EVOE_W<'a> { + w: &'a mut W, +} +impl<'a> EVOE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Channel Arbitration Level\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum LVL_A { + #[doc = "0: Channel Priority Level 0"] + LVL0 = 0, + #[doc = "1: Channel Priority Level 1"] + LVL1 = 1, + #[doc = "2: Channel Priority Level 2"] + LVL2 = 2, + #[doc = "3: Channel Priority Level 3"] + LVL3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LVL_A) -> Self { + variant as _ + } +} +#[doc = "Field `LVL` reader - Channel Arbitration Level"] +pub struct LVL_R(crate::FieldReader); +impl LVL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LVL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> LVL_A { + match self.bits { + 0 => LVL_A::LVL0, + 1 => LVL_A::LVL1, + 2 => LVL_A::LVL2, + 3 => LVL_A::LVL3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `LVL0`"] + #[inline(always)] + pub fn is_lvl0(&self) -> bool { + **self == LVL_A::LVL0 + } + #[doc = "Checks if the value of the field is `LVL1`"] + #[inline(always)] + pub fn is_lvl1(&self) -> bool { + **self == LVL_A::LVL1 + } + #[doc = "Checks if the value of the field is `LVL2`"] + #[inline(always)] + pub fn is_lvl2(&self) -> bool { + **self == LVL_A::LVL2 + } + #[doc = "Checks if the value of the field is `LVL3`"] + #[inline(always)] + pub fn is_lvl3(&self) -> bool { + **self == LVL_A::LVL3 + } +} +impl core::ops::Deref for LVL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVL` writer - Channel Arbitration Level"] +pub struct LVL_W<'a> { + w: &'a mut W, +} +impl<'a> LVL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: LVL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Channel Priority Level 0"] + #[inline(always)] + pub fn lvl0(self) -> &'a mut W { + self.variant(LVL_A::LVL0) + } + #[doc = "Channel Priority Level 1"] + #[inline(always)] + pub fn lvl1(self) -> &'a mut W { + self.variant(LVL_A::LVL1) + } + #[doc = "Channel Priority Level 2"] + #[inline(always)] + pub fn lvl2(self) -> &'a mut W { + self.variant(LVL_A::LVL2) + } + #[doc = "Channel Priority Level 3"] + #[inline(always)] + pub fn lvl3(self) -> &'a mut W { + self.variant(LVL_A::LVL3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 5)) | ((value as u32 & 0x03) << 5); + self.w + } +} +#[doc = "Trigger Source\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum TRIGSRC_A { + #[doc = "0: Only software/event triggers"] + DISABLE = 0, + #[doc = "1: TSENS Result Ready Trigger"] + TSENS = 1, + #[doc = "2: SERCOM0 RX Trigger"] + SERCOM0_RX = 2, + #[doc = "3: SERCOM0 TX Trigger"] + SERCOM0_TX = 3, + #[doc = "4: SERCOM1 RX Trigger"] + SERCOM1_RX = 4, + #[doc = "5: SERCOM1 TX Trigger"] + SERCOM1_TX = 5, + #[doc = "6: SERCOM2 RX Trigger"] + SERCOM2_RX = 6, + #[doc = "7: SERCOM2 TX Trigger"] + SERCOM2_TX = 7, + #[doc = "8: SERCOM3 RX Trigger"] + SERCOM3_RX = 8, + #[doc = "9: SERCOM3 TX Trigger"] + SERCOM3_TX = 9, + #[doc = "10: SERCOM4 RX Trigger"] + SERCOM4_RX = 10, + #[doc = "11: SERCOM4 TX Trigger"] + SERCOM4_TX = 11, + #[doc = "12: SERCOM5 RX Trigger"] + SERCOM5_RX = 12, + #[doc = "13: SERCOM5 TX Trigger"] + SERCOM5_TX = 13, + #[doc = "14: CAN0 Debug Trigger Reserved"] + CAN0_DEBUG = 14, + #[doc = "15: CAN1 Debug Trigger Reserved"] + CAN1_DEBUG = 15, + #[doc = "16: TCC0 Overflow Trigger"] + TCC0_OVF = 16, + #[doc = "17: TCC0 Match/Compare 0 Trigger"] + TCC0_MC0 = 17, + #[doc = "18: TCC0 Match/Compare 1 Trigger"] + TCC0_MC1 = 18, + #[doc = "19: TCC0 Match/Compare 2 Trigger"] + TCC0_MC2 = 19, + #[doc = "20: TCC0 Match/Compare 3 Trigger"] + TCC0_MC3 = 20, + #[doc = "21: TCC1 Overflow Trigger"] + TCC1_OVF = 21, + #[doc = "22: TCC1 Match/Compare 0 Trigger"] + TCC1_MC0 = 22, + #[doc = "23: TCC1 Match/Compare 1 Trigger"] + TCC1_MC1 = 23, + #[doc = "24: TCC2 Overflow Trigger"] + TCC2_OVF = 24, + #[doc = "25: TCC2 Match/Compare 0 Trigger"] + TCC2_MC0 = 25, + #[doc = "26: TCC2 Match/Compare 1 Trigger"] + TCC2_MC1 = 26, + #[doc = "27: TC0 Overflow Trigger"] + TC0_OVF = 27, + #[doc = "28: TC0 Match/Compare 0 Trigger"] + TC0_MC0 = 28, + #[doc = "29: TC0 Match/Compare 1 Trigger"] + TC0_MC1 = 29, + #[doc = "30: TC1 Overflow Trigger"] + TC1_OVF = 30, + #[doc = "31: TC1 Match/Compare 0 Trigger"] + TC1_MC0 = 31, + #[doc = "32: TC1 Match/Compare 1 Trigger"] + TC1_MC1 = 32, + #[doc = "33: TC2 Overflow Trigger"] + TC2_OVF = 33, + #[doc = "34: TC2 Match/Compare 0 Trigger"] + TC2_MC0 = 34, + #[doc = "35: TC2 Match/Compare 1 Trigger"] + TC2_MC1 = 35, + #[doc = "36: TC3 Overflow Trigger"] + TC3_OVF = 36, + #[doc = "37: TC3 Match/Compare 0 Trigger"] + TC3_MC0 = 37, + #[doc = "38: TC3 Match/Compare 1 Trigger"] + TC3_MC1 = 38, + #[doc = "39: TC4 Overflow Trigger"] + TC4_OVF = 39, + #[doc = "40: TC4 Match/Compare 0 Trigger"] + TC4_MC0 = 40, + #[doc = "41: TC4 Match/Compare 1 Trigger"] + TC4_MC1 = 41, + #[doc = "42: ADC0 Result Ready Trigger"] + ADC0_RESRDY = 42, + #[doc = "43: ADC1 Result Ready Trigger"] + ADC1_RESRDY = 43, + #[doc = "44: SDADC Result Ready Trigger"] + SDADC_RESRDY = 44, + #[doc = "45: DAC Empty Trigger"] + DAC_EMPTY = 45, + #[doc = "46: PTC End of Conversion Trigger"] + PTC_EOC = 46, + #[doc = "47: PTC Window Compare Trigger"] + PTC_WCOMP = 47, + #[doc = "48: PTC Sequence Trigger"] + PTC_SEQ = 48, + #[doc = "49: SERCOM6 RX Trigger"] + SERCOM6_RX = 49, + #[doc = "50: SERCOM6 TX Trigger"] + SERCOM6_TX = 50, + #[doc = "51: SERCOM7 RX Trigger"] + SERCOM7_RX = 51, + #[doc = "52: SERCOM7 TX Trigger"] + SERCOM7_TX = 52, + #[doc = "53: TC5 Overflow Trigger"] + TC5_OVF = 53, + #[doc = "54: TC5 Match/Compare 0 Trigger"] + TC5_MC0 = 54, + #[doc = "55: TC5 Match/Compare 1 Trigger"] + TC5_MC1 = 55, + #[doc = "56: TC6 Overflow Trigger"] + TC6_OVF = 56, + #[doc = "57: TC6 Match/Compare 0 Trigger"] + TC6_MC0 = 57, + #[doc = "58: TC6 Match/Compare 1 Trigger"] + TC6_MC1 = 58, + #[doc = "59: TC7 Overflow Trigger"] + TC7_OVF = 59, + #[doc = "60: TC7 Match/Compare 0 Trigger"] + TC7_MC0 = 60, + #[doc = "61: TC7 Match/Compare 1 Trigger"] + TC7_MC1 = 61, +} +impl From for u8 { + #[inline(always)] + fn from(variant: TRIGSRC_A) -> Self { + variant as _ + } +} +#[doc = "Field `TRIGSRC` reader - Trigger Source"] +pub struct TRIGSRC_R(crate::FieldReader); +impl TRIGSRC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TRIGSRC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(TRIGSRC_A::DISABLE), + 1 => Some(TRIGSRC_A::TSENS), + 2 => Some(TRIGSRC_A::SERCOM0_RX), + 3 => Some(TRIGSRC_A::SERCOM0_TX), + 4 => Some(TRIGSRC_A::SERCOM1_RX), + 5 => Some(TRIGSRC_A::SERCOM1_TX), + 6 => Some(TRIGSRC_A::SERCOM2_RX), + 7 => Some(TRIGSRC_A::SERCOM2_TX), + 8 => Some(TRIGSRC_A::SERCOM3_RX), + 9 => Some(TRIGSRC_A::SERCOM3_TX), + 10 => Some(TRIGSRC_A::SERCOM4_RX), + 11 => Some(TRIGSRC_A::SERCOM4_TX), + 12 => Some(TRIGSRC_A::SERCOM5_RX), + 13 => Some(TRIGSRC_A::SERCOM5_TX), + 14 => Some(TRIGSRC_A::CAN0_DEBUG), + 15 => Some(TRIGSRC_A::CAN1_DEBUG), + 16 => Some(TRIGSRC_A::TCC0_OVF), + 17 => Some(TRIGSRC_A::TCC0_MC0), + 18 => Some(TRIGSRC_A::TCC0_MC1), + 19 => Some(TRIGSRC_A::TCC0_MC2), + 20 => Some(TRIGSRC_A::TCC0_MC3), + 21 => Some(TRIGSRC_A::TCC1_OVF), + 22 => Some(TRIGSRC_A::TCC1_MC0), + 23 => Some(TRIGSRC_A::TCC1_MC1), + 24 => Some(TRIGSRC_A::TCC2_OVF), + 25 => Some(TRIGSRC_A::TCC2_MC0), + 26 => Some(TRIGSRC_A::TCC2_MC1), + 27 => Some(TRIGSRC_A::TC0_OVF), + 28 => Some(TRIGSRC_A::TC0_MC0), + 29 => Some(TRIGSRC_A::TC0_MC1), + 30 => Some(TRIGSRC_A::TC1_OVF), + 31 => Some(TRIGSRC_A::TC1_MC0), + 32 => Some(TRIGSRC_A::TC1_MC1), + 33 => Some(TRIGSRC_A::TC2_OVF), + 34 => Some(TRIGSRC_A::TC2_MC0), + 35 => Some(TRIGSRC_A::TC2_MC1), + 36 => Some(TRIGSRC_A::TC3_OVF), + 37 => Some(TRIGSRC_A::TC3_MC0), + 38 => Some(TRIGSRC_A::TC3_MC1), + 39 => Some(TRIGSRC_A::TC4_OVF), + 40 => Some(TRIGSRC_A::TC4_MC0), + 41 => Some(TRIGSRC_A::TC4_MC1), + 42 => Some(TRIGSRC_A::ADC0_RESRDY), + 43 => Some(TRIGSRC_A::ADC1_RESRDY), + 44 => Some(TRIGSRC_A::SDADC_RESRDY), + 45 => Some(TRIGSRC_A::DAC_EMPTY), + 46 => Some(TRIGSRC_A::PTC_EOC), + 47 => Some(TRIGSRC_A::PTC_WCOMP), + 48 => Some(TRIGSRC_A::PTC_SEQ), + 49 => Some(TRIGSRC_A::SERCOM6_RX), + 50 => Some(TRIGSRC_A::SERCOM6_TX), + 51 => Some(TRIGSRC_A::SERCOM7_RX), + 52 => Some(TRIGSRC_A::SERCOM7_TX), + 53 => Some(TRIGSRC_A::TC5_OVF), + 54 => Some(TRIGSRC_A::TC5_MC0), + 55 => Some(TRIGSRC_A::TC5_MC1), + 56 => Some(TRIGSRC_A::TC6_OVF), + 57 => Some(TRIGSRC_A::TC6_MC0), + 58 => Some(TRIGSRC_A::TC6_MC1), + 59 => Some(TRIGSRC_A::TC7_OVF), + 60 => Some(TRIGSRC_A::TC7_MC0), + 61 => Some(TRIGSRC_A::TC7_MC1), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == TRIGSRC_A::DISABLE + } + #[doc = "Checks if the value of the field is `TSENS`"] + #[inline(always)] + pub fn is_tsens(&self) -> bool { + **self == TRIGSRC_A::TSENS + } + #[doc = "Checks if the value of the field is `SERCOM0_RX`"] + #[inline(always)] + pub fn is_sercom0_rx(&self) -> bool { + **self == TRIGSRC_A::SERCOM0_RX + } + #[doc = "Checks if the value of the field is `SERCOM0_TX`"] + #[inline(always)] + pub fn is_sercom0_tx(&self) -> bool { + **self == TRIGSRC_A::SERCOM0_TX + } + #[doc = "Checks if the value of the field is `SERCOM1_RX`"] + #[inline(always)] + pub fn is_sercom1_rx(&self) -> bool { + **self == TRIGSRC_A::SERCOM1_RX + } + #[doc = "Checks if the value of the field is `SERCOM1_TX`"] + #[inline(always)] + pub fn is_sercom1_tx(&self) -> bool { + **self == TRIGSRC_A::SERCOM1_TX + } + #[doc = "Checks if the value of the field is `SERCOM2_RX`"] + #[inline(always)] + pub fn is_sercom2_rx(&self) -> bool { + **self == TRIGSRC_A::SERCOM2_RX + } + #[doc = "Checks if the value of the field is `SERCOM2_TX`"] + #[inline(always)] + pub fn is_sercom2_tx(&self) -> bool { + **self == TRIGSRC_A::SERCOM2_TX + } + #[doc = "Checks if the value of the field is `SERCOM3_RX`"] + #[inline(always)] + pub fn is_sercom3_rx(&self) -> bool { + **self == TRIGSRC_A::SERCOM3_RX + } + #[doc = "Checks if the value of the field is `SERCOM3_TX`"] + #[inline(always)] + pub fn is_sercom3_tx(&self) -> bool { + **self == TRIGSRC_A::SERCOM3_TX + } + #[doc = "Checks if the value of the field is `SERCOM4_RX`"] + #[inline(always)] + pub fn is_sercom4_rx(&self) -> bool { + **self == TRIGSRC_A::SERCOM4_RX + } + #[doc = "Checks if the value of the field is `SERCOM4_TX`"] + #[inline(always)] + pub fn is_sercom4_tx(&self) -> bool { + **self == TRIGSRC_A::SERCOM4_TX + } + #[doc = "Checks if the value of the field is `SERCOM5_RX`"] + #[inline(always)] + pub fn is_sercom5_rx(&self) -> bool { + **self == TRIGSRC_A::SERCOM5_RX + } + #[doc = "Checks if the value of the field is `SERCOM5_TX`"] + #[inline(always)] + pub fn is_sercom5_tx(&self) -> bool { + **self == TRIGSRC_A::SERCOM5_TX + } + #[doc = "Checks if the value of the field is `CAN0_DEBUG`"] + #[inline(always)] + pub fn is_can0_debug(&self) -> bool { + **self == TRIGSRC_A::CAN0_DEBUG + } + #[doc = "Checks if the value of the field is `CAN1_DEBUG`"] + #[inline(always)] + pub fn is_can1_debug(&self) -> bool { + **self == TRIGSRC_A::CAN1_DEBUG + } + #[doc = "Checks if the value of the field is `TCC0_OVF`"] + #[inline(always)] + pub fn is_tcc0_ovf(&self) -> bool { + **self == TRIGSRC_A::TCC0_OVF + } + #[doc = "Checks if the value of the field is `TCC0_MC0`"] + #[inline(always)] + pub fn is_tcc0_mc0(&self) -> bool { + **self == TRIGSRC_A::TCC0_MC0 + } + #[doc = "Checks if the value of the field is `TCC0_MC1`"] + #[inline(always)] + pub fn is_tcc0_mc1(&self) -> bool { + **self == TRIGSRC_A::TCC0_MC1 + } + #[doc = "Checks if the value of the field is `TCC0_MC2`"] + #[inline(always)] + pub fn is_tcc0_mc2(&self) -> bool { + **self == TRIGSRC_A::TCC0_MC2 + } + #[doc = "Checks if the value of the field is `TCC0_MC3`"] + #[inline(always)] + pub fn is_tcc0_mc3(&self) -> bool { + **self == TRIGSRC_A::TCC0_MC3 + } + #[doc = "Checks if the value of the field is `TCC1_OVF`"] + #[inline(always)] + pub fn is_tcc1_ovf(&self) -> bool { + **self == TRIGSRC_A::TCC1_OVF + } + #[doc = "Checks if the value of the field is `TCC1_MC0`"] + #[inline(always)] + pub fn is_tcc1_mc0(&self) -> bool { + **self == TRIGSRC_A::TCC1_MC0 + } + #[doc = "Checks if the value of the field is `TCC1_MC1`"] + #[inline(always)] + pub fn is_tcc1_mc1(&self) -> bool { + **self == TRIGSRC_A::TCC1_MC1 + } + #[doc = "Checks if the value of the field is `TCC2_OVF`"] + #[inline(always)] + pub fn is_tcc2_ovf(&self) -> bool { + **self == TRIGSRC_A::TCC2_OVF + } + #[doc = "Checks if the value of the field is `TCC2_MC0`"] + #[inline(always)] + pub fn is_tcc2_mc0(&self) -> bool { + **self == TRIGSRC_A::TCC2_MC0 + } + #[doc = "Checks if the value of the field is `TCC2_MC1`"] + #[inline(always)] + pub fn is_tcc2_mc1(&self) -> bool { + **self == TRIGSRC_A::TCC2_MC1 + } + #[doc = "Checks if the value of the field is `TC0_OVF`"] + #[inline(always)] + pub fn is_tc0_ovf(&self) -> bool { + **self == TRIGSRC_A::TC0_OVF + } + #[doc = "Checks if the value of the field is `TC0_MC0`"] + #[inline(always)] + pub fn is_tc0_mc0(&self) -> bool { + **self == TRIGSRC_A::TC0_MC0 + } + #[doc = "Checks if the value of the field is `TC0_MC1`"] + #[inline(always)] + pub fn is_tc0_mc1(&self) -> bool { + **self == TRIGSRC_A::TC0_MC1 + } + #[doc = "Checks if the value of the field is `TC1_OVF`"] + #[inline(always)] + pub fn is_tc1_ovf(&self) -> bool { + **self == TRIGSRC_A::TC1_OVF + } + #[doc = "Checks if the value of the field is `TC1_MC0`"] + #[inline(always)] + pub fn is_tc1_mc0(&self) -> bool { + **self == TRIGSRC_A::TC1_MC0 + } + #[doc = "Checks if the value of the field is `TC1_MC1`"] + #[inline(always)] + pub fn is_tc1_mc1(&self) -> bool { + **self == TRIGSRC_A::TC1_MC1 + } + #[doc = "Checks if the value of the field is `TC2_OVF`"] + #[inline(always)] + pub fn is_tc2_ovf(&self) -> bool { + **self == TRIGSRC_A::TC2_OVF + } + #[doc = "Checks if the value of the field is `TC2_MC0`"] + #[inline(always)] + pub fn is_tc2_mc0(&self) -> bool { + **self == TRIGSRC_A::TC2_MC0 + } + #[doc = "Checks if the value of the field is `TC2_MC1`"] + #[inline(always)] + pub fn is_tc2_mc1(&self) -> bool { + **self == TRIGSRC_A::TC2_MC1 + } + #[doc = "Checks if the value of the field is `TC3_OVF`"] + #[inline(always)] + pub fn is_tc3_ovf(&self) -> bool { + **self == TRIGSRC_A::TC3_OVF + } + #[doc = "Checks if the value of the field is `TC3_MC0`"] + #[inline(always)] + pub fn is_tc3_mc0(&self) -> bool { + **self == TRIGSRC_A::TC3_MC0 + } + #[doc = "Checks if the value of the field is `TC3_MC1`"] + #[inline(always)] + pub fn is_tc3_mc1(&self) -> bool { + **self == TRIGSRC_A::TC3_MC1 + } + #[doc = "Checks if the value of the field is `TC4_OVF`"] + #[inline(always)] + pub fn is_tc4_ovf(&self) -> bool { + **self == TRIGSRC_A::TC4_OVF + } + #[doc = "Checks if the value of the field is `TC4_MC0`"] + #[inline(always)] + pub fn is_tc4_mc0(&self) -> bool { + **self == TRIGSRC_A::TC4_MC0 + } + #[doc = "Checks if the value of the field is `TC4_MC1`"] + #[inline(always)] + pub fn is_tc4_mc1(&self) -> bool { + **self == TRIGSRC_A::TC4_MC1 + } + #[doc = "Checks if the value of the field is `ADC0_RESRDY`"] + #[inline(always)] + pub fn is_adc0_resrdy(&self) -> bool { + **self == TRIGSRC_A::ADC0_RESRDY + } + #[doc = "Checks if the value of the field is `ADC1_RESRDY`"] + #[inline(always)] + pub fn is_adc1_resrdy(&self) -> bool { + **self == TRIGSRC_A::ADC1_RESRDY + } + #[doc = "Checks if the value of the field is `SDADC_RESRDY`"] + #[inline(always)] + pub fn is_sdadc_resrdy(&self) -> bool { + **self == TRIGSRC_A::SDADC_RESRDY + } + #[doc = "Checks if the value of the field is `DAC_EMPTY`"] + #[inline(always)] + pub fn is_dac_empty(&self) -> bool { + **self == TRIGSRC_A::DAC_EMPTY + } + #[doc = "Checks if the value of the field is `PTC_EOC`"] + #[inline(always)] + pub fn is_ptc_eoc(&self) -> bool { + **self == TRIGSRC_A::PTC_EOC + } + #[doc = "Checks if the value of the field is `PTC_WCOMP`"] + #[inline(always)] + pub fn is_ptc_wcomp(&self) -> bool { + **self == TRIGSRC_A::PTC_WCOMP + } + #[doc = "Checks if the value of the field is `PTC_SEQ`"] + #[inline(always)] + pub fn is_ptc_seq(&self) -> bool { + **self == TRIGSRC_A::PTC_SEQ + } + #[doc = "Checks if the value of the field is `SERCOM6_RX`"] + #[inline(always)] + pub fn is_sercom6_rx(&self) -> bool { + **self == TRIGSRC_A::SERCOM6_RX + } + #[doc = "Checks if the value of the field is `SERCOM6_TX`"] + #[inline(always)] + pub fn is_sercom6_tx(&self) -> bool { + **self == TRIGSRC_A::SERCOM6_TX + } + #[doc = "Checks if the value of the field is `SERCOM7_RX`"] + #[inline(always)] + pub fn is_sercom7_rx(&self) -> bool { + **self == TRIGSRC_A::SERCOM7_RX + } + #[doc = "Checks if the value of the field is `SERCOM7_TX`"] + #[inline(always)] + pub fn is_sercom7_tx(&self) -> bool { + **self == TRIGSRC_A::SERCOM7_TX + } + #[doc = "Checks if the value of the field is `TC5_OVF`"] + #[inline(always)] + pub fn is_tc5_ovf(&self) -> bool { + **self == TRIGSRC_A::TC5_OVF + } + #[doc = "Checks if the value of the field is `TC5_MC0`"] + #[inline(always)] + pub fn is_tc5_mc0(&self) -> bool { + **self == TRIGSRC_A::TC5_MC0 + } + #[doc = "Checks if the value of the field is `TC5_MC1`"] + #[inline(always)] + pub fn is_tc5_mc1(&self) -> bool { + **self == TRIGSRC_A::TC5_MC1 + } + #[doc = "Checks if the value of the field is `TC6_OVF`"] + #[inline(always)] + pub fn is_tc6_ovf(&self) -> bool { + **self == TRIGSRC_A::TC6_OVF + } + #[doc = "Checks if the value of the field is `TC6_MC0`"] + #[inline(always)] + pub fn is_tc6_mc0(&self) -> bool { + **self == TRIGSRC_A::TC6_MC0 + } + #[doc = "Checks if the value of the field is `TC6_MC1`"] + #[inline(always)] + pub fn is_tc6_mc1(&self) -> bool { + **self == TRIGSRC_A::TC6_MC1 + } + #[doc = "Checks if the value of the field is `TC7_OVF`"] + #[inline(always)] + pub fn is_tc7_ovf(&self) -> bool { + **self == TRIGSRC_A::TC7_OVF + } + #[doc = "Checks if the value of the field is `TC7_MC0`"] + #[inline(always)] + pub fn is_tc7_mc0(&self) -> bool { + **self == TRIGSRC_A::TC7_MC0 + } + #[doc = "Checks if the value of the field is `TC7_MC1`"] + #[inline(always)] + pub fn is_tc7_mc1(&self) -> bool { + **self == TRIGSRC_A::TC7_MC1 + } +} +impl core::ops::Deref for TRIGSRC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRIGSRC` writer - Trigger Source"] +pub struct TRIGSRC_W<'a> { + w: &'a mut W, +} +impl<'a> TRIGSRC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TRIGSRC_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Only software/event triggers"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(TRIGSRC_A::DISABLE) + } + #[doc = "TSENS Result Ready Trigger"] + #[inline(always)] + pub fn tsens(self) -> &'a mut W { + self.variant(TRIGSRC_A::TSENS) + } + #[doc = "SERCOM0 RX Trigger"] + #[inline(always)] + pub fn sercom0_rx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM0_RX) + } + #[doc = "SERCOM0 TX Trigger"] + #[inline(always)] + pub fn sercom0_tx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM0_TX) + } + #[doc = "SERCOM1 RX Trigger"] + #[inline(always)] + pub fn sercom1_rx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM1_RX) + } + #[doc = "SERCOM1 TX Trigger"] + #[inline(always)] + pub fn sercom1_tx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM1_TX) + } + #[doc = "SERCOM2 RX Trigger"] + #[inline(always)] + pub fn sercom2_rx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM2_RX) + } + #[doc = "SERCOM2 TX Trigger"] + #[inline(always)] + pub fn sercom2_tx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM2_TX) + } + #[doc = "SERCOM3 RX Trigger"] + #[inline(always)] + pub fn sercom3_rx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM3_RX) + } + #[doc = "SERCOM3 TX Trigger"] + #[inline(always)] + pub fn sercom3_tx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM3_TX) + } + #[doc = "SERCOM4 RX Trigger"] + #[inline(always)] + pub fn sercom4_rx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM4_RX) + } + #[doc = "SERCOM4 TX Trigger"] + #[inline(always)] + pub fn sercom4_tx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM4_TX) + } + #[doc = "SERCOM5 RX Trigger"] + #[inline(always)] + pub fn sercom5_rx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM5_RX) + } + #[doc = "SERCOM5 TX Trigger"] + #[inline(always)] + pub fn sercom5_tx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM5_TX) + } + #[doc = "CAN0 Debug Trigger Reserved"] + #[inline(always)] + pub fn can0_debug(self) -> &'a mut W { + self.variant(TRIGSRC_A::CAN0_DEBUG) + } + #[doc = "CAN1 Debug Trigger Reserved"] + #[inline(always)] + pub fn can1_debug(self) -> &'a mut W { + self.variant(TRIGSRC_A::CAN1_DEBUG) + } + #[doc = "TCC0 Overflow Trigger"] + #[inline(always)] + pub fn tcc0_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC0_OVF) + } + #[doc = "TCC0 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tcc0_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC0_MC0) + } + #[doc = "TCC0 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tcc0_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC0_MC1) + } + #[doc = "TCC0 Match/Compare 2 Trigger"] + #[inline(always)] + pub fn tcc0_mc2(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC0_MC2) + } + #[doc = "TCC0 Match/Compare 3 Trigger"] + #[inline(always)] + pub fn tcc0_mc3(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC0_MC3) + } + #[doc = "TCC1 Overflow Trigger"] + #[inline(always)] + pub fn tcc1_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC1_OVF) + } + #[doc = "TCC1 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tcc1_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC1_MC0) + } + #[doc = "TCC1 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tcc1_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC1_MC1) + } + #[doc = "TCC2 Overflow Trigger"] + #[inline(always)] + pub fn tcc2_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC2_OVF) + } + #[doc = "TCC2 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tcc2_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC2_MC0) + } + #[doc = "TCC2 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tcc2_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC2_MC1) + } + #[doc = "TC0 Overflow Trigger"] + #[inline(always)] + pub fn tc0_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC0_OVF) + } + #[doc = "TC0 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tc0_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC0_MC0) + } + #[doc = "TC0 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tc0_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC0_MC1) + } + #[doc = "TC1 Overflow Trigger"] + #[inline(always)] + pub fn tc1_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC1_OVF) + } + #[doc = "TC1 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tc1_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC1_MC0) + } + #[doc = "TC1 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tc1_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC1_MC1) + } + #[doc = "TC2 Overflow Trigger"] + #[inline(always)] + pub fn tc2_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC2_OVF) + } + #[doc = "TC2 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tc2_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC2_MC0) + } + #[doc = "TC2 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tc2_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC2_MC1) + } + #[doc = "TC3 Overflow Trigger"] + #[inline(always)] + pub fn tc3_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC3_OVF) + } + #[doc = "TC3 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tc3_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC3_MC0) + } + #[doc = "TC3 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tc3_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC3_MC1) + } + #[doc = "TC4 Overflow Trigger"] + #[inline(always)] + pub fn tc4_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC4_OVF) + } + #[doc = "TC4 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tc4_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC4_MC0) + } + #[doc = "TC4 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tc4_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC4_MC1) + } + #[doc = "ADC0 Result Ready Trigger"] + #[inline(always)] + pub fn adc0_resrdy(self) -> &'a mut W { + self.variant(TRIGSRC_A::ADC0_RESRDY) + } + #[doc = "ADC1 Result Ready Trigger"] + #[inline(always)] + pub fn adc1_resrdy(self) -> &'a mut W { + self.variant(TRIGSRC_A::ADC1_RESRDY) + } + #[doc = "SDADC Result Ready Trigger"] + #[inline(always)] + pub fn sdadc_resrdy(self) -> &'a mut W { + self.variant(TRIGSRC_A::SDADC_RESRDY) + } + #[doc = "DAC Empty Trigger"] + #[inline(always)] + pub fn dac_empty(self) -> &'a mut W { + self.variant(TRIGSRC_A::DAC_EMPTY) + } + #[doc = "PTC End of Conversion Trigger"] + #[inline(always)] + pub fn ptc_eoc(self) -> &'a mut W { + self.variant(TRIGSRC_A::PTC_EOC) + } + #[doc = "PTC Window Compare Trigger"] + #[inline(always)] + pub fn ptc_wcomp(self) -> &'a mut W { + self.variant(TRIGSRC_A::PTC_WCOMP) + } + #[doc = "PTC Sequence Trigger"] + #[inline(always)] + pub fn ptc_seq(self) -> &'a mut W { + self.variant(TRIGSRC_A::PTC_SEQ) + } + #[doc = "SERCOM6 RX Trigger"] + #[inline(always)] + pub fn sercom6_rx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM6_RX) + } + #[doc = "SERCOM6 TX Trigger"] + #[inline(always)] + pub fn sercom6_tx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM6_TX) + } + #[doc = "SERCOM7 RX Trigger"] + #[inline(always)] + pub fn sercom7_rx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM7_RX) + } + #[doc = "SERCOM7 TX Trigger"] + #[inline(always)] + pub fn sercom7_tx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM7_TX) + } + #[doc = "TC5 Overflow Trigger"] + #[inline(always)] + pub fn tc5_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC5_OVF) + } + #[doc = "TC5 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tc5_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC5_MC0) + } + #[doc = "TC5 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tc5_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC5_MC1) + } + #[doc = "TC6 Overflow Trigger"] + #[inline(always)] + pub fn tc6_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC6_OVF) + } + #[doc = "TC6 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tc6_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC6_MC0) + } + #[doc = "TC6 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tc6_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC6_MC1) + } + #[doc = "TC7 Overflow Trigger"] + #[inline(always)] + pub fn tc7_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC7_OVF) + } + #[doc = "TC7 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tc7_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC7_MC0) + } + #[doc = "TC7 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tc7_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC7_MC1) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 8)) | ((value as u32 & 0x3f) << 8); + self.w + } +} +#[doc = "Trigger Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum TRIGACT_A { + #[doc = "0: One trigger required for each block transfer"] + BLOCK = 0, + #[doc = "2: One trigger required for each beat transfer"] + BEAT = 2, + #[doc = "3: One trigger required for each transaction"] + TRANSACTION = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: TRIGACT_A) -> Self { + variant as _ + } +} +#[doc = "Field `TRIGACT` reader - Trigger Action"] +pub struct TRIGACT_R(crate::FieldReader); +impl TRIGACT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TRIGACT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(TRIGACT_A::BLOCK), + 2 => Some(TRIGACT_A::BEAT), + 3 => Some(TRIGACT_A::TRANSACTION), + _ => None, + } + } + #[doc = "Checks if the value of the field is `BLOCK`"] + #[inline(always)] + pub fn is_block(&self) -> bool { + **self == TRIGACT_A::BLOCK + } + #[doc = "Checks if the value of the field is `BEAT`"] + #[inline(always)] + pub fn is_beat(&self) -> bool { + **self == TRIGACT_A::BEAT + } + #[doc = "Checks if the value of the field is `TRANSACTION`"] + #[inline(always)] + pub fn is_transaction(&self) -> bool { + **self == TRIGACT_A::TRANSACTION + } +} +impl core::ops::Deref for TRIGACT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRIGACT` writer - Trigger Action"] +pub struct TRIGACT_W<'a> { + w: &'a mut W, +} +impl<'a> TRIGACT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TRIGACT_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "One trigger required for each block transfer"] + #[inline(always)] + pub fn block(self) -> &'a mut W { + self.variant(TRIGACT_A::BLOCK) + } + #[doc = "One trigger required for each beat transfer"] + #[inline(always)] + pub fn beat(self) -> &'a mut W { + self.variant(TRIGACT_A::BEAT) + } + #[doc = "One trigger required for each transaction"] + #[inline(always)] + pub fn transaction(self) -> &'a mut W { + self.variant(TRIGACT_A::TRANSACTION) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 22)) | ((value as u32 & 0x03) << 22); + self.w + } +} +#[doc = "Software Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NOACT = 0, + #[doc = "1: Channel suspend operation"] + SUSPEND = 1, + #[doc = "2: Channel resume operation"] + RESUME = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Software Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NOACT), + 1 => Some(CMD_A::SUSPEND), + 2 => Some(CMD_A::RESUME), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NOACT`"] + #[inline(always)] + pub fn is_noact(&self) -> bool { + **self == CMD_A::NOACT + } + #[doc = "Checks if the value of the field is `SUSPEND`"] + #[inline(always)] + pub fn is_suspend(&self) -> bool { + **self == CMD_A::SUSPEND + } + #[doc = "Checks if the value of the field is `RESUME`"] + #[inline(always)] + pub fn is_resume(&self) -> bool { + **self == CMD_A::RESUME + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Software Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn noact(self) -> &'a mut W { + self.variant(CMD_A::NOACT) + } + #[doc = "Channel suspend operation"] + #[inline(always)] + pub fn suspend(self) -> &'a mut W { + self.variant(CMD_A::SUSPEND) + } + #[doc = "Channel resume operation"] + #[inline(always)] + pub fn resume(self) -> &'a mut W { + self.variant(CMD_A::RESUME) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 24)) | ((value as u32 & 0x03) << 24); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Event Input Action"] + #[inline(always)] + pub fn evact(&self) -> EVACT_R { + EVACT_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 3 - Channel Event Input Enable"] + #[inline(always)] + pub fn evie(&self) -> EVIE_R { + EVIE_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Channel Event Output Enable"] + #[inline(always)] + pub fn evoe(&self) -> EVOE_R { + EVOE_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bits 5:6 - Channel Arbitration Level"] + #[inline(always)] + pub fn lvl(&self) -> LVL_R { + LVL_R::new(((self.bits >> 5) & 0x03) as u8) + } + #[doc = "Bits 8:13 - Trigger Source"] + #[inline(always)] + pub fn trigsrc(&self) -> TRIGSRC_R { + TRIGSRC_R::new(((self.bits >> 8) & 0x3f) as u8) + } + #[doc = "Bits 22:23 - Trigger Action"] + #[inline(always)] + pub fn trigact(&self) -> TRIGACT_R { + TRIGACT_R::new(((self.bits >> 22) & 0x03) as u8) + } + #[doc = "Bits 24:25 - Software Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 24) & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Event Input Action"] + #[inline(always)] + pub fn evact(&mut self) -> EVACT_W { + EVACT_W { w: self } + } + #[doc = "Bit 3 - Channel Event Input Enable"] + #[inline(always)] + pub fn evie(&mut self) -> EVIE_W { + EVIE_W { w: self } + } + #[doc = "Bit 4 - Channel Event Output Enable"] + #[inline(always)] + pub fn evoe(&mut self) -> EVOE_W { + EVOE_W { w: self } + } + #[doc = "Bits 5:6 - Channel Arbitration Level"] + #[inline(always)] + pub fn lvl(&mut self) -> LVL_W { + LVL_W { w: self } + } + #[doc = "Bits 8:13 - Trigger Source"] + #[inline(always)] + pub fn trigsrc(&mut self) -> TRIGSRC_W { + TRIGSRC_W { w: self } + } + #[doc = "Bits 22:23 - Trigger Action"] + #[inline(always)] + pub fn trigact(&mut self) -> TRIGACT_W { + TRIGACT_W { w: self } + } + #[doc = "Bits 24:25 - Software Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chctrlb](index.html) module"] +pub struct CHCTRLB_SPEC; +impl crate::RegisterSpec for CHCTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [chctrlb::R](R) reader structure"] +impl crate::Readable for CHCTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chctrlb::W](W) writer structure"] +impl crate::Writable for CHCTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHCTRLB to value 0"] +impl crate::Resettable for CHCTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/dmac/chid.rs b/pac/atsamc21n/src/dmac/chid.rs new file mode 100644 index 000000000000..19151d8e10b0 --- /dev/null +++ b/pac/atsamc21n/src/dmac/chid.rs @@ -0,0 +1,103 @@ +#[doc = "Register `CHID` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHID` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ID` reader - Channel ID"] +pub struct ID_R(crate::FieldReader); +impl ID_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ID_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ID_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ID` writer - Channel ID"] +pub struct ID_W<'a> { + w: &'a mut W, +} +impl<'a> ID_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Channel ID"] + #[inline(always)] + pub fn id(&self) -> ID_R { + ID_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Channel ID"] + #[inline(always)] + pub fn id(&mut self) -> ID_W { + ID_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel ID\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chid](index.html) module"] +pub struct CHID_SPEC; +impl crate::RegisterSpec for CHID_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [chid::R](R) reader structure"] +impl crate::Readable for CHID_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chid::W](W) writer structure"] +impl crate::Writable for CHID_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHID to value 0"] +impl crate::Resettable for CHID_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/dmac/chintenclr.rs b/pac/atsamc21n/src/dmac/chintenclr.rs new file mode 100644 index 000000000000..5ae3096f9ab8 --- /dev/null +++ b/pac/atsamc21n/src/dmac/chintenclr.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CHINTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHINTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TERR` reader - Channel Transfer Error Interrupt Enable"] +pub struct TERR_R(crate::FieldReader); +impl TERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TERR` writer - Channel Transfer Error Interrupt Enable"] +pub struct TERR_W<'a> { + w: &'a mut W, +} +impl<'a> TERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TCMPL` reader - Channel Transfer Complete Interrupt Enable"] +pub struct TCMPL_R(crate::FieldReader); +impl TCMPL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCMPL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCMPL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCMPL` writer - Channel Transfer Complete Interrupt Enable"] +pub struct TCMPL_W<'a> { + w: &'a mut W, +} +impl<'a> TCMPL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SUSP` reader - Channel Suspend Interrupt Enable"] +pub struct SUSP_R(crate::FieldReader); +impl SUSP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SUSP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SUSP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SUSP` writer - Channel Suspend Interrupt Enable"] +pub struct SUSP_W<'a> { + w: &'a mut W, +} +impl<'a> SUSP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Channel Transfer Error Interrupt Enable"] + #[inline(always)] + pub fn terr(&self) -> TERR_R { + TERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel Transfer Complete Interrupt Enable"] + #[inline(always)] + pub fn tcmpl(&self) -> TCMPL_R { + TCMPL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel Suspend Interrupt Enable"] + #[inline(always)] + pub fn susp(&self) -> SUSP_R { + SUSP_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel Transfer Error Interrupt Enable"] + #[inline(always)] + pub fn terr(&mut self) -> TERR_W { + TERR_W { w: self } + } + #[doc = "Bit 1 - Channel Transfer Complete Interrupt Enable"] + #[inline(always)] + pub fn tcmpl(&mut self) -> TCMPL_W { + TCMPL_W { w: self } + } + #[doc = "Bit 2 - Channel Suspend Interrupt Enable"] + #[inline(always)] + pub fn susp(&mut self) -> SUSP_W { + SUSP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chintenclr](index.html) module"] +pub struct CHINTENCLR_SPEC; +impl crate::RegisterSpec for CHINTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [chintenclr::R](R) reader structure"] +impl crate::Readable for CHINTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chintenclr::W](W) writer structure"] +impl crate::Writable for CHINTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHINTENCLR to value 0"] +impl crate::Resettable for CHINTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/dmac/chintenset.rs b/pac/atsamc21n/src/dmac/chintenset.rs new file mode 100644 index 000000000000..2e7daef20a6f --- /dev/null +++ b/pac/atsamc21n/src/dmac/chintenset.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CHINTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHINTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TERR` reader - Channel Transfer Error Interrupt Enable"] +pub struct TERR_R(crate::FieldReader); +impl TERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TERR` writer - Channel Transfer Error Interrupt Enable"] +pub struct TERR_W<'a> { + w: &'a mut W, +} +impl<'a> TERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TCMPL` reader - Channel Transfer Complete Interrupt Enable"] +pub struct TCMPL_R(crate::FieldReader); +impl TCMPL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCMPL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCMPL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCMPL` writer - Channel Transfer Complete Interrupt Enable"] +pub struct TCMPL_W<'a> { + w: &'a mut W, +} +impl<'a> TCMPL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SUSP` reader - Channel Suspend Interrupt Enable"] +pub struct SUSP_R(crate::FieldReader); +impl SUSP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SUSP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SUSP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SUSP` writer - Channel Suspend Interrupt Enable"] +pub struct SUSP_W<'a> { + w: &'a mut W, +} +impl<'a> SUSP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Channel Transfer Error Interrupt Enable"] + #[inline(always)] + pub fn terr(&self) -> TERR_R { + TERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel Transfer Complete Interrupt Enable"] + #[inline(always)] + pub fn tcmpl(&self) -> TCMPL_R { + TCMPL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel Suspend Interrupt Enable"] + #[inline(always)] + pub fn susp(&self) -> SUSP_R { + SUSP_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel Transfer Error Interrupt Enable"] + #[inline(always)] + pub fn terr(&mut self) -> TERR_W { + TERR_W { w: self } + } + #[doc = "Bit 1 - Channel Transfer Complete Interrupt Enable"] + #[inline(always)] + pub fn tcmpl(&mut self) -> TCMPL_W { + TCMPL_W { w: self } + } + #[doc = "Bit 2 - Channel Suspend Interrupt Enable"] + #[inline(always)] + pub fn susp(&mut self) -> SUSP_W { + SUSP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chintenset](index.html) module"] +pub struct CHINTENSET_SPEC; +impl crate::RegisterSpec for CHINTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [chintenset::R](R) reader structure"] +impl crate::Readable for CHINTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chintenset::W](W) writer structure"] +impl crate::Writable for CHINTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHINTENSET to value 0"] +impl crate::Resettable for CHINTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/dmac/chintflag.rs b/pac/atsamc21n/src/dmac/chintflag.rs new file mode 100644 index 000000000000..4e61d6510c30 --- /dev/null +++ b/pac/atsamc21n/src/dmac/chintflag.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CHINTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHINTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TERR` reader - Channel Transfer Error"] +pub struct TERR_R(crate::FieldReader); +impl TERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TERR` writer - Channel Transfer Error"] +pub struct TERR_W<'a> { + w: &'a mut W, +} +impl<'a> TERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TCMPL` reader - Channel Transfer Complete"] +pub struct TCMPL_R(crate::FieldReader); +impl TCMPL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCMPL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCMPL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCMPL` writer - Channel Transfer Complete"] +pub struct TCMPL_W<'a> { + w: &'a mut W, +} +impl<'a> TCMPL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SUSP` reader - Channel Suspend"] +pub struct SUSP_R(crate::FieldReader); +impl SUSP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SUSP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SUSP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SUSP` writer - Channel Suspend"] +pub struct SUSP_W<'a> { + w: &'a mut W, +} +impl<'a> SUSP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Channel Transfer Error"] + #[inline(always)] + pub fn terr(&self) -> TERR_R { + TERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel Transfer Complete"] + #[inline(always)] + pub fn tcmpl(&self) -> TCMPL_R { + TCMPL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel Suspend"] + #[inline(always)] + pub fn susp(&self) -> SUSP_R { + SUSP_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel Transfer Error"] + #[inline(always)] + pub fn terr(&mut self) -> TERR_W { + TERR_W { w: self } + } + #[doc = "Bit 1 - Channel Transfer Complete"] + #[inline(always)] + pub fn tcmpl(&mut self) -> TCMPL_W { + TCMPL_W { w: self } + } + #[doc = "Bit 2 - Channel Suspend"] + #[inline(always)] + pub fn susp(&mut self) -> SUSP_W { + SUSP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chintflag](index.html) module"] +pub struct CHINTFLAG_SPEC; +impl crate::RegisterSpec for CHINTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [chintflag::R](R) reader structure"] +impl crate::Readable for CHINTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chintflag::W](W) writer structure"] +impl crate::Writable for CHINTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHINTFLAG to value 0"] +impl crate::Resettable for CHINTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/dmac/chstatus.rs b/pac/atsamc21n/src/dmac/chstatus.rs new file mode 100644 index 000000000000..98a84345d4f7 --- /dev/null +++ b/pac/atsamc21n/src/dmac/chstatus.rs @@ -0,0 +1,93 @@ +#[doc = "Register `CHSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PEND` reader - Channel Pending"] +pub struct PEND_R(crate::FieldReader); +impl PEND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSY` reader - Channel Busy"] +pub struct BUSY_R(crate::FieldReader); +impl BUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FERR` reader - Channel Fetch Error"] +pub struct FERR_R(crate::FieldReader); +impl FERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Channel Pending"] + #[inline(always)] + pub fn pend(&self) -> PEND_R { + PEND_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel Busy"] + #[inline(always)] + pub fn busy(&self) -> BUSY_R { + BUSY_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel Fetch Error"] + #[inline(always)] + pub fn ferr(&self) -> FERR_R { + FERR_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +#[doc = "Channel Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chstatus](index.html) module"] +pub struct CHSTATUS_SPEC; +impl crate::RegisterSpec for CHSTATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [chstatus::R](R) reader structure"] +impl crate::Readable for CHSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CHSTATUS to value 0"] +impl crate::Resettable for CHSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/dmac/crcchksum.rs b/pac/atsamc21n/src/dmac/crcchksum.rs new file mode 100644 index 000000000000..89eb5b38a093 --- /dev/null +++ b/pac/atsamc21n/src/dmac/crcchksum.rs @@ -0,0 +1,103 @@ +#[doc = "Register `CRCCHKSUM` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CRCCHKSUM` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CRCCHKSUM` reader - CRC Checksum"] +pub struct CRCCHKSUM_R(crate::FieldReader); +impl CRCCHKSUM_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CRCCHKSUM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CRCCHKSUM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCCHKSUM` writer - CRC Checksum"] +pub struct CRCCHKSUM_W<'a> { + w: &'a mut W, +} +impl<'a> CRCCHKSUM_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - CRC Checksum"] + #[inline(always)] + pub fn crcchksum(&self) -> CRCCHKSUM_R { + CRCCHKSUM_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - CRC Checksum"] + #[inline(always)] + pub fn crcchksum(&mut self) -> CRCCHKSUM_W { + CRCCHKSUM_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CRC Checksum\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [crcchksum](index.html) module"] +pub struct CRCCHKSUM_SPEC; +impl crate::RegisterSpec for CRCCHKSUM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [crcchksum::R](R) reader structure"] +impl crate::Readable for CRCCHKSUM_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [crcchksum::W](W) writer structure"] +impl crate::Writable for CRCCHKSUM_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CRCCHKSUM to value 0"] +impl crate::Resettable for CRCCHKSUM_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/dmac/crcctrl.rs b/pac/atsamc21n/src/dmac/crcctrl.rs new file mode 100644 index 000000000000..b8daf7b8259d --- /dev/null +++ b/pac/atsamc21n/src/dmac/crcctrl.rs @@ -0,0 +1,337 @@ +#[doc = "Register `CRCCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CRCCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "CRC Beat Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CRCBEATSIZE_A { + #[doc = "0: 8-bit bus transfer"] + BYTE = 0, + #[doc = "1: 16-bit bus transfer"] + HWORD = 1, + #[doc = "2: 32-bit bus transfer"] + WORD = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CRCBEATSIZE_A) -> Self { + variant as _ + } +} +#[doc = "Field `CRCBEATSIZE` reader - CRC Beat Size"] +pub struct CRCBEATSIZE_R(crate::FieldReader); +impl CRCBEATSIZE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CRCBEATSIZE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CRCBEATSIZE_A::BYTE), + 1 => Some(CRCBEATSIZE_A::HWORD), + 2 => Some(CRCBEATSIZE_A::WORD), + _ => None, + } + } + #[doc = "Checks if the value of the field is `BYTE`"] + #[inline(always)] + pub fn is_byte(&self) -> bool { + **self == CRCBEATSIZE_A::BYTE + } + #[doc = "Checks if the value of the field is `HWORD`"] + #[inline(always)] + pub fn is_hword(&self) -> bool { + **self == CRCBEATSIZE_A::HWORD + } + #[doc = "Checks if the value of the field is `WORD`"] + #[inline(always)] + pub fn is_word(&self) -> bool { + **self == CRCBEATSIZE_A::WORD + } +} +impl core::ops::Deref for CRCBEATSIZE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCBEATSIZE` writer - CRC Beat Size"] +pub struct CRCBEATSIZE_W<'a> { + w: &'a mut W, +} +impl<'a> CRCBEATSIZE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CRCBEATSIZE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8-bit bus transfer"] + #[inline(always)] + pub fn byte(self) -> &'a mut W { + self.variant(CRCBEATSIZE_A::BYTE) + } + #[doc = "16-bit bus transfer"] + #[inline(always)] + pub fn hword(self) -> &'a mut W { + self.variant(CRCBEATSIZE_A::HWORD) + } + #[doc = "32-bit bus transfer"] + #[inline(always)] + pub fn word(self) -> &'a mut W { + self.variant(CRCBEATSIZE_A::WORD) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u16 & 0x03); + self.w + } +} +#[doc = "CRC Polynomial Type\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CRCPOLY_A { + #[doc = "0: CRC-16 (CRC-CCITT)"] + CRC16 = 0, + #[doc = "1: CRC32 (IEEE 802.3)"] + CRC32 = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CRCPOLY_A) -> Self { + variant as _ + } +} +#[doc = "Field `CRCPOLY` reader - CRC Polynomial Type"] +pub struct CRCPOLY_R(crate::FieldReader); +impl CRCPOLY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CRCPOLY_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CRCPOLY_A::CRC16), + 1 => Some(CRCPOLY_A::CRC32), + _ => None, + } + } + #[doc = "Checks if the value of the field is `CRC16`"] + #[inline(always)] + pub fn is_crc16(&self) -> bool { + **self == CRCPOLY_A::CRC16 + } + #[doc = "Checks if the value of the field is `CRC32`"] + #[inline(always)] + pub fn is_crc32(&self) -> bool { + **self == CRCPOLY_A::CRC32 + } +} +impl core::ops::Deref for CRCPOLY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCPOLY` writer - CRC Polynomial Type"] +pub struct CRCPOLY_W<'a> { + w: &'a mut W, +} +impl<'a> CRCPOLY_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CRCPOLY_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "CRC-16 (CRC-CCITT)"] + #[inline(always)] + pub fn crc16(self) -> &'a mut W { + self.variant(CRCPOLY_A::CRC16) + } + #[doc = "CRC32 (IEEE 802.3)"] + #[inline(always)] + pub fn crc32(self) -> &'a mut W { + self.variant(CRCPOLY_A::CRC32) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u16 & 0x03) << 2); + self.w + } +} +#[doc = "CRC Input Source\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CRCSRC_A { + #[doc = "0: No action"] + NOACT = 0, + #[doc = "1: I/O interface"] + IO = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CRCSRC_A) -> Self { + variant as _ + } +} +#[doc = "Field `CRCSRC` reader - CRC Input Source"] +pub struct CRCSRC_R(crate::FieldReader); +impl CRCSRC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CRCSRC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CRCSRC_A::NOACT), + 1 => Some(CRCSRC_A::IO), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NOACT`"] + #[inline(always)] + pub fn is_noact(&self) -> bool { + **self == CRCSRC_A::NOACT + } + #[doc = "Checks if the value of the field is `IO`"] + #[inline(always)] + pub fn is_io(&self) -> bool { + **self == CRCSRC_A::IO + } +} +impl core::ops::Deref for CRCSRC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCSRC` writer - CRC Input Source"] +pub struct CRCSRC_W<'a> { + w: &'a mut W, +} +impl<'a> CRCSRC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CRCSRC_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn noact(self) -> &'a mut W { + self.variant(CRCSRC_A::NOACT) + } + #[doc = "I/O interface"] + #[inline(always)] + pub fn io(self) -> &'a mut W { + self.variant(CRCSRC_A::IO) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 8)) | ((value as u16 & 0x3f) << 8); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - CRC Beat Size"] + #[inline(always)] + pub fn crcbeatsize(&self) -> CRCBEATSIZE_R { + CRCBEATSIZE_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bits 2:3 - CRC Polynomial Type"] + #[inline(always)] + pub fn crcpoly(&self) -> CRCPOLY_R { + CRCPOLY_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bits 8:13 - CRC Input Source"] + #[inline(always)] + pub fn crcsrc(&self) -> CRCSRC_R { + CRCSRC_R::new(((self.bits >> 8) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - CRC Beat Size"] + #[inline(always)] + pub fn crcbeatsize(&mut self) -> CRCBEATSIZE_W { + CRCBEATSIZE_W { w: self } + } + #[doc = "Bits 2:3 - CRC Polynomial Type"] + #[inline(always)] + pub fn crcpoly(&mut self) -> CRCPOLY_W { + CRCPOLY_W { w: self } + } + #[doc = "Bits 8:13 - CRC Input Source"] + #[inline(always)] + pub fn crcsrc(&mut self) -> CRCSRC_W { + CRCSRC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CRC Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [crcctrl](index.html) module"] +pub struct CRCCTRL_SPEC; +impl crate::RegisterSpec for CRCCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [crcctrl::R](R) reader structure"] +impl crate::Readable for CRCCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [crcctrl::W](W) writer structure"] +impl crate::Writable for CRCCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CRCCTRL to value 0"] +impl crate::Resettable for CRCCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/dmac/crcdatain.rs b/pac/atsamc21n/src/dmac/crcdatain.rs new file mode 100644 index 000000000000..ca0879a12136 --- /dev/null +++ b/pac/atsamc21n/src/dmac/crcdatain.rs @@ -0,0 +1,103 @@ +#[doc = "Register `CRCDATAIN` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CRCDATAIN` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CRCDATAIN` reader - CRC Data Input"] +pub struct CRCDATAIN_R(crate::FieldReader); +impl CRCDATAIN_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CRCDATAIN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CRCDATAIN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCDATAIN` writer - CRC Data Input"] +pub struct CRCDATAIN_W<'a> { + w: &'a mut W, +} +impl<'a> CRCDATAIN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - CRC Data Input"] + #[inline(always)] + pub fn crcdatain(&self) -> CRCDATAIN_R { + CRCDATAIN_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - CRC Data Input"] + #[inline(always)] + pub fn crcdatain(&mut self) -> CRCDATAIN_W { + CRCDATAIN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CRC Data Input\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [crcdatain](index.html) module"] +pub struct CRCDATAIN_SPEC; +impl crate::RegisterSpec for CRCDATAIN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [crcdatain::R](R) reader structure"] +impl crate::Readable for CRCDATAIN_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [crcdatain::W](W) writer structure"] +impl crate::Writable for CRCDATAIN_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CRCDATAIN to value 0"] +impl crate::Resettable for CRCDATAIN_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/dmac/crcstatus.rs b/pac/atsamc21n/src/dmac/crcstatus.rs new file mode 100644 index 000000000000..a132e9d5cd03 --- /dev/null +++ b/pac/atsamc21n/src/dmac/crcstatus.rs @@ -0,0 +1,160 @@ +#[doc = "Register `CRCSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CRCSTATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CRCBUSY` reader - CRC Module Busy"] +pub struct CRCBUSY_R(crate::FieldReader); +impl CRCBUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CRCBUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CRCBUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCBUSY` writer - CRC Module Busy"] +pub struct CRCBUSY_W<'a> { + w: &'a mut W, +} +impl<'a> CRCBUSY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `CRCZERO` reader - CRC Zero"] +pub struct CRCZERO_R(crate::FieldReader); +impl CRCZERO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CRCZERO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CRCZERO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCZERO` writer - CRC Zero"] +pub struct CRCZERO_W<'a> { + w: &'a mut W, +} +impl<'a> CRCZERO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - CRC Module Busy"] + #[inline(always)] + pub fn crcbusy(&self) -> CRCBUSY_R { + CRCBUSY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - CRC Zero"] + #[inline(always)] + pub fn crczero(&self) -> CRCZERO_R { + CRCZERO_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - CRC Module Busy"] + #[inline(always)] + pub fn crcbusy(&mut self) -> CRCBUSY_W { + CRCBUSY_W { w: self } + } + #[doc = "Bit 1 - CRC Zero"] + #[inline(always)] + pub fn crczero(&mut self) -> CRCZERO_W { + CRCZERO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CRC Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [crcstatus](index.html) module"] +pub struct CRCSTATUS_SPEC; +impl crate::RegisterSpec for CRCSTATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [crcstatus::R](R) reader structure"] +impl crate::Readable for CRCSTATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [crcstatus::W](W) writer structure"] +impl crate::Writable for CRCSTATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CRCSTATUS to value 0"] +impl crate::Resettable for CRCSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/dmac/ctrl.rs b/pac/atsamc21n/src/dmac/ctrl.rs new file mode 100644 index 000000000000..fabae9d82a6c --- /dev/null +++ b/pac/atsamc21n/src/dmac/ctrl.rs @@ -0,0 +1,395 @@ +#[doc = "Register `CTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `DMAENABLE` reader - DMA Enable"] +pub struct DMAENABLE_R(crate::FieldReader); +impl DMAENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DMAENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DMAENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DMAENABLE` writer - DMA Enable"] +pub struct DMAENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> DMAENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CRCENABLE` reader - CRC Enable"] +pub struct CRCENABLE_R(crate::FieldReader); +impl CRCENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CRCENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CRCENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCENABLE` writer - CRC Enable"] +pub struct CRCENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> CRCENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `LVLEN0` reader - Priority Level 0 Enable"] +pub struct LVLEN0_R(crate::FieldReader); +impl LVLEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LVLEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLEN0` writer - Priority Level 0 Enable"] +pub struct LVLEN0_W<'a> { + w: &'a mut W, +} +impl<'a> LVLEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `LVLEN1` reader - Priority Level 1 Enable"] +pub struct LVLEN1_R(crate::FieldReader); +impl LVLEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LVLEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLEN1` writer - Priority Level 1 Enable"] +pub struct LVLEN1_W<'a> { + w: &'a mut W, +} +impl<'a> LVLEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `LVLEN2` reader - Priority Level 2 Enable"] +pub struct LVLEN2_R(crate::FieldReader); +impl LVLEN2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LVLEN2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEN2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLEN2` writer - Priority Level 2 Enable"] +pub struct LVLEN2_W<'a> { + w: &'a mut W, +} +impl<'a> LVLEN2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u16 & 0x01) << 10); + self.w + } +} +#[doc = "Field `LVLEN3` reader - Priority Level 3 Enable"] +pub struct LVLEN3_R(crate::FieldReader); +impl LVLEN3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LVLEN3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEN3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLEN3` writer - Priority Level 3 Enable"] +pub struct LVLEN3_W<'a> { + w: &'a mut W, +} +impl<'a> LVLEN3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u16 & 0x01) << 11); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - DMA Enable"] + #[inline(always)] + pub fn dmaenable(&self) -> DMAENABLE_R { + DMAENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - CRC Enable"] + #[inline(always)] + pub fn crcenable(&self) -> CRCENABLE_R { + CRCENABLE_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 8 - Priority Level 0 Enable"] + #[inline(always)] + pub fn lvlen0(&self) -> LVLEN0_R { + LVLEN0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Priority Level 1 Enable"] + #[inline(always)] + pub fn lvlen1(&self) -> LVLEN1_R { + LVLEN1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Priority Level 2 Enable"] + #[inline(always)] + pub fn lvlen2(&self) -> LVLEN2_R { + LVLEN2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Priority Level 3 Enable"] + #[inline(always)] + pub fn lvlen3(&self) -> LVLEN3_R { + LVLEN3_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - DMA Enable"] + #[inline(always)] + pub fn dmaenable(&mut self) -> DMAENABLE_W { + DMAENABLE_W { w: self } + } + #[doc = "Bit 2 - CRC Enable"] + #[inline(always)] + pub fn crcenable(&mut self) -> CRCENABLE_W { + CRCENABLE_W { w: self } + } + #[doc = "Bit 8 - Priority Level 0 Enable"] + #[inline(always)] + pub fn lvlen0(&mut self) -> LVLEN0_W { + LVLEN0_W { w: self } + } + #[doc = "Bit 9 - Priority Level 1 Enable"] + #[inline(always)] + pub fn lvlen1(&mut self) -> LVLEN1_W { + LVLEN1_W { w: self } + } + #[doc = "Bit 10 - Priority Level 2 Enable"] + #[inline(always)] + pub fn lvlen2(&mut self) -> LVLEN2_W { + LVLEN2_W { w: self } + } + #[doc = "Bit 11 - Priority Level 3 Enable"] + #[inline(always)] + pub fn lvlen3(&mut self) -> LVLEN3_W { + LVLEN3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"] +pub struct CTRL_SPEC; +impl crate::RegisterSpec for CTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrl::R](R) reader structure"] +impl crate::Readable for CTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"] +impl crate::Writable for CTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/dmac/dbgctrl.rs b/pac/atsamc21n/src/dmac/dbgctrl.rs new file mode 100644 index 000000000000..53636eb2b339 --- /dev/null +++ b/pac/atsamc21n/src/dmac/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Debug Run"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Debug Run"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/dmac/intpend.rs b/pac/atsamc21n/src/dmac/intpend.rs new file mode 100644 index 000000000000..a107c4c32e66 --- /dev/null +++ b/pac/atsamc21n/src/dmac/intpend.rs @@ -0,0 +1,385 @@ +#[doc = "Register `INTPEND` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTPEND` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ID` reader - Channel ID"] +pub struct ID_R(crate::FieldReader); +impl ID_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ID_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ID_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ID` writer - Channel ID"] +pub struct ID_W<'a> { + w: &'a mut W, +} +impl<'a> ID_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u16 & 0x0f); + self.w + } +} +#[doc = "Field `TERR` reader - Transfer Error"] +pub struct TERR_R(crate::FieldReader); +impl TERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TERR` writer - Transfer Error"] +pub struct TERR_W<'a> { + w: &'a mut W, +} +impl<'a> TERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `TCMPL` reader - Transfer Complete"] +pub struct TCMPL_R(crate::FieldReader); +impl TCMPL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCMPL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCMPL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCMPL` writer - Transfer Complete"] +pub struct TCMPL_W<'a> { + w: &'a mut W, +} +impl<'a> TCMPL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `SUSP` reader - Channel Suspend"] +pub struct SUSP_R(crate::FieldReader); +impl SUSP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SUSP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SUSP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SUSP` writer - Channel Suspend"] +pub struct SUSP_W<'a> { + w: &'a mut W, +} +impl<'a> SUSP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u16 & 0x01) << 10); + self.w + } +} +#[doc = "Field `FERR` reader - Fetch Error"] +pub struct FERR_R(crate::FieldReader); +impl FERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FERR` writer - Fetch Error"] +pub struct FERR_W<'a> { + w: &'a mut W, +} +impl<'a> FERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u16 & 0x01) << 13); + self.w + } +} +#[doc = "Field `BUSY` reader - Busy"] +pub struct BUSY_R(crate::FieldReader); +impl BUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSY` writer - Busy"] +pub struct BUSY_W<'a> { + w: &'a mut W, +} +impl<'a> BUSY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u16 & 0x01) << 14); + self.w + } +} +#[doc = "Field `PEND` reader - Pending"] +pub struct PEND_R(crate::FieldReader); +impl PEND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEND` writer - Pending"] +pub struct PEND_W<'a> { + w: &'a mut W, +} +impl<'a> PEND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Channel ID"] + #[inline(always)] + pub fn id(&self) -> ID_R { + ID_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 8 - Transfer Error"] + #[inline(always)] + pub fn terr(&self) -> TERR_R { + TERR_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Transfer Complete"] + #[inline(always)] + pub fn tcmpl(&self) -> TCMPL_R { + TCMPL_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Channel Suspend"] + #[inline(always)] + pub fn susp(&self) -> SUSP_R { + SUSP_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 13 - Fetch Error"] + #[inline(always)] + pub fn ferr(&self) -> FERR_R { + FERR_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Busy"] + #[inline(always)] + pub fn busy(&self) -> BUSY_R { + BUSY_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Pending"] + #[inline(always)] + pub fn pend(&self) -> PEND_R { + PEND_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Channel ID"] + #[inline(always)] + pub fn id(&mut self) -> ID_W { + ID_W { w: self } + } + #[doc = "Bit 8 - Transfer Error"] + #[inline(always)] + pub fn terr(&mut self) -> TERR_W { + TERR_W { w: self } + } + #[doc = "Bit 9 - Transfer Complete"] + #[inline(always)] + pub fn tcmpl(&mut self) -> TCMPL_W { + TCMPL_W { w: self } + } + #[doc = "Bit 10 - Channel Suspend"] + #[inline(always)] + pub fn susp(&mut self) -> SUSP_W { + SUSP_W { w: self } + } + #[doc = "Bit 13 - Fetch Error"] + #[inline(always)] + pub fn ferr(&mut self) -> FERR_W { + FERR_W { w: self } + } + #[doc = "Bit 14 - Busy"] + #[inline(always)] + pub fn busy(&mut self) -> BUSY_W { + BUSY_W { w: self } + } + #[doc = "Bit 15 - Pending"] + #[inline(always)] + pub fn pend(&mut self) -> PEND_W { + PEND_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Pending\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intpend](index.html) module"] +pub struct INTPEND_SPEC; +impl crate::RegisterSpec for INTPEND_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intpend::R](R) reader structure"] +impl crate::Readable for INTPEND_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intpend::W](W) writer structure"] +impl crate::Writable for INTPEND_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTPEND to value 0"] +impl crate::Resettable for INTPEND_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/dmac/intstatus.rs b/pac/atsamc21n/src/dmac/intstatus.rs new file mode 100644 index 000000000000..74a836f4a2ff --- /dev/null +++ b/pac/atsamc21n/src/dmac/intstatus.rs @@ -0,0 +1,273 @@ +#[doc = "Register `INTSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `CHINT0` reader - Channel 0 Pending Interrupt"] +pub struct CHINT0_R(crate::FieldReader); +impl CHINT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT1` reader - Channel 1 Pending Interrupt"] +pub struct CHINT1_R(crate::FieldReader); +impl CHINT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT2` reader - Channel 2 Pending Interrupt"] +pub struct CHINT2_R(crate::FieldReader); +impl CHINT2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT3` reader - Channel 3 Pending Interrupt"] +pub struct CHINT3_R(crate::FieldReader); +impl CHINT3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT4` reader - Channel 4 Pending Interrupt"] +pub struct CHINT4_R(crate::FieldReader); +impl CHINT4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT5` reader - Channel 5 Pending Interrupt"] +pub struct CHINT5_R(crate::FieldReader); +impl CHINT5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT6` reader - Channel 6 Pending Interrupt"] +pub struct CHINT6_R(crate::FieldReader); +impl CHINT6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT7` reader - Channel 7 Pending Interrupt"] +pub struct CHINT7_R(crate::FieldReader); +impl CHINT7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT8` reader - Channel 8 Pending Interrupt"] +pub struct CHINT8_R(crate::FieldReader); +impl CHINT8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT9` reader - Channel 9 Pending Interrupt"] +pub struct CHINT9_R(crate::FieldReader); +impl CHINT9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT10` reader - Channel 10 Pending Interrupt"] +pub struct CHINT10_R(crate::FieldReader); +impl CHINT10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT11` reader - Channel 11 Pending Interrupt"] +pub struct CHINT11_R(crate::FieldReader); +impl CHINT11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHINT11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Channel 0 Pending Interrupt"] + #[inline(always)] + pub fn chint0(&self) -> CHINT0_R { + CHINT0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel 1 Pending Interrupt"] + #[inline(always)] + pub fn chint1(&self) -> CHINT1_R { + CHINT1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel 2 Pending Interrupt"] + #[inline(always)] + pub fn chint2(&self) -> CHINT2_R { + CHINT2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Channel 3 Pending Interrupt"] + #[inline(always)] + pub fn chint3(&self) -> CHINT3_R { + CHINT3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Channel 4 Pending Interrupt"] + #[inline(always)] + pub fn chint4(&self) -> CHINT4_R { + CHINT4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Channel 5 Pending Interrupt"] + #[inline(always)] + pub fn chint5(&self) -> CHINT5_R { + CHINT5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Channel 6 Pending Interrupt"] + #[inline(always)] + pub fn chint6(&self) -> CHINT6_R { + CHINT6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Channel 7 Pending Interrupt"] + #[inline(always)] + pub fn chint7(&self) -> CHINT7_R { + CHINT7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Channel 8 Pending Interrupt"] + #[inline(always)] + pub fn chint8(&self) -> CHINT8_R { + CHINT8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Channel 9 Pending Interrupt"] + #[inline(always)] + pub fn chint9(&self) -> CHINT9_R { + CHINT9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Channel 10 Pending Interrupt"] + #[inline(always)] + pub fn chint10(&self) -> CHINT10_R { + CHINT10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Channel 11 Pending Interrupt"] + #[inline(always)] + pub fn chint11(&self) -> CHINT11_R { + CHINT11_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +#[doc = "Interrupt Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intstatus](index.html) module"] +pub struct INTSTATUS_SPEC; +impl crate::RegisterSpec for INTSTATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intstatus::R](R) reader structure"] +impl crate::Readable for INTSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets INTSTATUS to value 0"] +impl crate::Resettable for INTSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/dmac/pendch.rs b/pac/atsamc21n/src/dmac/pendch.rs new file mode 100644 index 000000000000..8bb68ff8fa5d --- /dev/null +++ b/pac/atsamc21n/src/dmac/pendch.rs @@ -0,0 +1,273 @@ +#[doc = "Register `PENDCH` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PENDCH0` reader - Pending Channel 0"] +pub struct PENDCH0_R(crate::FieldReader); +impl PENDCH0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH1` reader - Pending Channel 1"] +pub struct PENDCH1_R(crate::FieldReader); +impl PENDCH1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH2` reader - Pending Channel 2"] +pub struct PENDCH2_R(crate::FieldReader); +impl PENDCH2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH3` reader - Pending Channel 3"] +pub struct PENDCH3_R(crate::FieldReader); +impl PENDCH3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH4` reader - Pending Channel 4"] +pub struct PENDCH4_R(crate::FieldReader); +impl PENDCH4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH5` reader - Pending Channel 5"] +pub struct PENDCH5_R(crate::FieldReader); +impl PENDCH5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH6` reader - Pending Channel 6"] +pub struct PENDCH6_R(crate::FieldReader); +impl PENDCH6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH7` reader - Pending Channel 7"] +pub struct PENDCH7_R(crate::FieldReader); +impl PENDCH7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH8` reader - Pending Channel 8"] +pub struct PENDCH8_R(crate::FieldReader); +impl PENDCH8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH9` reader - Pending Channel 9"] +pub struct PENDCH9_R(crate::FieldReader); +impl PENDCH9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH10` reader - Pending Channel 10"] +pub struct PENDCH10_R(crate::FieldReader); +impl PENDCH10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH11` reader - Pending Channel 11"] +pub struct PENDCH11_R(crate::FieldReader); +impl PENDCH11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDCH11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Pending Channel 0"] + #[inline(always)] + pub fn pendch0(&self) -> PENDCH0_R { + PENDCH0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Pending Channel 1"] + #[inline(always)] + pub fn pendch1(&self) -> PENDCH1_R { + PENDCH1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Pending Channel 2"] + #[inline(always)] + pub fn pendch2(&self) -> PENDCH2_R { + PENDCH2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Pending Channel 3"] + #[inline(always)] + pub fn pendch3(&self) -> PENDCH3_R { + PENDCH3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Pending Channel 4"] + #[inline(always)] + pub fn pendch4(&self) -> PENDCH4_R { + PENDCH4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Pending Channel 5"] + #[inline(always)] + pub fn pendch5(&self) -> PENDCH5_R { + PENDCH5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Pending Channel 6"] + #[inline(always)] + pub fn pendch6(&self) -> PENDCH6_R { + PENDCH6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Pending Channel 7"] + #[inline(always)] + pub fn pendch7(&self) -> PENDCH7_R { + PENDCH7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Pending Channel 8"] + #[inline(always)] + pub fn pendch8(&self) -> PENDCH8_R { + PENDCH8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Pending Channel 9"] + #[inline(always)] + pub fn pendch9(&self) -> PENDCH9_R { + PENDCH9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Pending Channel 10"] + #[inline(always)] + pub fn pendch10(&self) -> PENDCH10_R { + PENDCH10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Pending Channel 11"] + #[inline(always)] + pub fn pendch11(&self) -> PENDCH11_R { + PENDCH11_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +#[doc = "Pending Channels\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pendch](index.html) module"] +pub struct PENDCH_SPEC; +impl crate::RegisterSpec for PENDCH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pendch::R](R) reader structure"] +impl crate::Readable for PENDCH_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PENDCH to value 0"] +impl crate::Resettable for PENDCH_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/dmac/prictrl0.rs b/pac/atsamc21n/src/dmac/prictrl0.rs new file mode 100644 index 000000000000..618e54ad23f2 --- /dev/null +++ b/pac/atsamc21n/src/dmac/prictrl0.rs @@ -0,0 +1,449 @@ +#[doc = "Register `PRICTRL0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PRICTRL0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `LVLPRI0` reader - Level 0 Channel Priority Number"] +pub struct LVLPRI0_R(crate::FieldReader); +impl LVLPRI0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LVLPRI0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLPRI0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLPRI0` writer - Level 0 Channel Priority Number"] +pub struct LVLPRI0_W<'a> { + w: &'a mut W, +} +impl<'a> LVLPRI0_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Level 0 Round-Robin Scheduling Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RRLVLEN0_A { + #[doc = "0: Static arbitration scheme for channels with level 3 priority"] + STATIC_LVL = 0, + #[doc = "1: Round-robin arbitration scheme for channels with level 3 priority"] + ROUND_ROBIN_LVL = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RRLVLEN0_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RRLVLEN0` reader - Level 0 Round-Robin Scheduling Enable"] +pub struct RRLVLEN0_R(crate::FieldReader); +impl RRLVLEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RRLVLEN0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RRLVLEN0_A { + match self.bits { + false => RRLVLEN0_A::STATIC_LVL, + true => RRLVLEN0_A::ROUND_ROBIN_LVL, + } + } + #[doc = "Checks if the value of the field is `STATIC_LVL`"] + #[inline(always)] + pub fn is_static_lvl(&self) -> bool { + **self == RRLVLEN0_A::STATIC_LVL + } + #[doc = "Checks if the value of the field is `ROUND_ROBIN_LVL`"] + #[inline(always)] + pub fn is_round_robin_lvl(&self) -> bool { + **self == RRLVLEN0_A::ROUND_ROBIN_LVL + } +} +impl core::ops::Deref for RRLVLEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RRLVLEN0` writer - Level 0 Round-Robin Scheduling Enable"] +pub struct RRLVLEN0_W<'a> { + w: &'a mut W, +} +impl<'a> RRLVLEN0_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RRLVLEN0_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Static arbitration scheme for channels with level 3 priority"] + #[inline(always)] + pub fn static_lvl(self) -> &'a mut W { + self.variant(RRLVLEN0_A::STATIC_LVL) + } + #[doc = "Round-robin arbitration scheme for channels with level 3 priority"] + #[inline(always)] + pub fn round_robin_lvl(self) -> &'a mut W { + self.variant(RRLVLEN0_A::ROUND_ROBIN_LVL) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `LVLPRI1` reader - Level 1 Channel Priority Number"] +pub struct LVLPRI1_R(crate::FieldReader); +impl LVLPRI1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LVLPRI1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLPRI1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLPRI1` writer - Level 1 Channel Priority Number"] +pub struct LVLPRI1_W<'a> { + w: &'a mut W, +} +impl<'a> LVLPRI1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 8)) | ((value as u32 & 0x0f) << 8); + self.w + } +} +#[doc = "Field `RRLVLEN1` reader - Level 1 Round-Robin Scheduling Enable"] +pub struct RRLVLEN1_R(crate::FieldReader); +impl RRLVLEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RRLVLEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RRLVLEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RRLVLEN1` writer - Level 1 Round-Robin Scheduling Enable"] +pub struct RRLVLEN1_W<'a> { + w: &'a mut W, +} +impl<'a> RRLVLEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `LVLPRI2` reader - Level 2 Channel Priority Number"] +pub struct LVLPRI2_R(crate::FieldReader); +impl LVLPRI2_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LVLPRI2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLPRI2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLPRI2` writer - Level 2 Channel Priority Number"] +pub struct LVLPRI2_W<'a> { + w: &'a mut W, +} +impl<'a> LVLPRI2_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 16)) | ((value as u32 & 0x0f) << 16); + self.w + } +} +#[doc = "Field `RRLVLEN2` reader - Level 2 Round-Robin Scheduling Enable"] +pub struct RRLVLEN2_R(crate::FieldReader); +impl RRLVLEN2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RRLVLEN2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RRLVLEN2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RRLVLEN2` writer - Level 2 Round-Robin Scheduling Enable"] +pub struct RRLVLEN2_W<'a> { + w: &'a mut W, +} +impl<'a> RRLVLEN2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `LVLPRI3` reader - Level 3 Channel Priority Number"] +pub struct LVLPRI3_R(crate::FieldReader); +impl LVLPRI3_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LVLPRI3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLPRI3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLPRI3` writer - Level 3 Channel Priority Number"] +pub struct LVLPRI3_W<'a> { + w: &'a mut W, +} +impl<'a> LVLPRI3_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Field `RRLVLEN3` reader - Level 3 Round-Robin Scheduling Enable"] +pub struct RRLVLEN3_R(crate::FieldReader); +impl RRLVLEN3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RRLVLEN3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RRLVLEN3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RRLVLEN3` writer - Level 3 Round-Robin Scheduling Enable"] +pub struct RRLVLEN3_W<'a> { + w: &'a mut W, +} +impl<'a> RRLVLEN3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Level 0 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri0(&self) -> LVLPRI0_R { + LVLPRI0_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 7 - Level 0 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen0(&self) -> RRLVLEN0_R { + RRLVLEN0_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:11 - Level 1 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri1(&self) -> LVLPRI1_R { + LVLPRI1_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 15 - Level 1 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen1(&self) -> RRLVLEN1_R { + RRLVLEN1_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:19 - Level 2 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri2(&self) -> LVLPRI2_R { + LVLPRI2_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 23 - Level 2 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen2(&self) -> RRLVLEN2_R { + RRLVLEN2_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bits 24:27 - Level 3 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri3(&self) -> LVLPRI3_R { + LVLPRI3_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 31 - Level 3 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen3(&self) -> RRLVLEN3_R { + RRLVLEN3_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Level 0 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri0(&mut self) -> LVLPRI0_W { + LVLPRI0_W { w: self } + } + #[doc = "Bit 7 - Level 0 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen0(&mut self) -> RRLVLEN0_W { + RRLVLEN0_W { w: self } + } + #[doc = "Bits 8:11 - Level 1 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri1(&mut self) -> LVLPRI1_W { + LVLPRI1_W { w: self } + } + #[doc = "Bit 15 - Level 1 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen1(&mut self) -> RRLVLEN1_W { + RRLVLEN1_W { w: self } + } + #[doc = "Bits 16:19 - Level 2 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri2(&mut self) -> LVLPRI2_W { + LVLPRI2_W { w: self } + } + #[doc = "Bit 23 - Level 2 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen2(&mut self) -> RRLVLEN2_W { + RRLVLEN2_W { w: self } + } + #[doc = "Bits 24:27 - Level 3 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri3(&mut self) -> LVLPRI3_W { + LVLPRI3_W { w: self } + } + #[doc = "Bit 31 - Level 3 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen3(&mut self) -> RRLVLEN3_W { + RRLVLEN3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Priority Control 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [prictrl0](index.html) module"] +pub struct PRICTRL0_SPEC; +impl crate::RegisterSpec for PRICTRL0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [prictrl0::R](R) reader structure"] +impl crate::Readable for PRICTRL0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [prictrl0::W](W) writer structure"] +impl crate::Writable for PRICTRL0_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PRICTRL0 to value 0"] +impl crate::Resettable for PRICTRL0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/dmac/qosctrl.rs b/pac/atsamc21n/src/dmac/qosctrl.rs new file mode 100644 index 000000000000..016fcaa221ef --- /dev/null +++ b/pac/atsamc21n/src/dmac/qosctrl.rs @@ -0,0 +1,402 @@ +#[doc = "Register `QOSCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `QOSCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Write-Back Quality of Service\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WRBQOS_A { + #[doc = "0: Background (no sensitive operation)"] + DISABLE = 0, + #[doc = "1: Sensitive Bandwidth"] + LOW = 1, + #[doc = "2: Sensitive Latency"] + MEDIUM = 2, + #[doc = "3: Critical Latency"] + HIGH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WRBQOS_A) -> Self { + variant as _ + } +} +#[doc = "Field `WRBQOS` reader - Write-Back Quality of Service"] +pub struct WRBQOS_R(crate::FieldReader); +impl WRBQOS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WRBQOS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> WRBQOS_A { + match self.bits { + 0 => WRBQOS_A::DISABLE, + 1 => WRBQOS_A::LOW, + 2 => WRBQOS_A::MEDIUM, + 3 => WRBQOS_A::HIGH, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == WRBQOS_A::DISABLE + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == WRBQOS_A::LOW + } + #[doc = "Checks if the value of the field is `MEDIUM`"] + #[inline(always)] + pub fn is_medium(&self) -> bool { + **self == WRBQOS_A::MEDIUM + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == WRBQOS_A::HIGH + } +} +impl core::ops::Deref for WRBQOS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WRBQOS` writer - Write-Back Quality of Service"] +pub struct WRBQOS_W<'a> { + w: &'a mut W, +} +impl<'a> WRBQOS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WRBQOS_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Background (no sensitive operation)"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(WRBQOS_A::DISABLE) + } + #[doc = "Sensitive Bandwidth"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(WRBQOS_A::LOW) + } + #[doc = "Sensitive Latency"] + #[inline(always)] + pub fn medium(self) -> &'a mut W { + self.variant(WRBQOS_A::MEDIUM) + } + #[doc = "Critical Latency"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(WRBQOS_A::HIGH) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u8 & 0x03); + self.w + } +} +#[doc = "Fetch Quality of Service\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FQOS_A { + #[doc = "0: Background (no sensitive operation)"] + DISABLE = 0, + #[doc = "1: Sensitive Bandwidth"] + LOW = 1, + #[doc = "2: Sensitive Latency"] + MEDIUM = 2, + #[doc = "3: Critical Latency"] + HIGH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FQOS_A) -> Self { + variant as _ + } +} +#[doc = "Field `FQOS` reader - Fetch Quality of Service"] +pub struct FQOS_R(crate::FieldReader); +impl FQOS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FQOS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FQOS_A { + match self.bits { + 0 => FQOS_A::DISABLE, + 1 => FQOS_A::LOW, + 2 => FQOS_A::MEDIUM, + 3 => FQOS_A::HIGH, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == FQOS_A::DISABLE + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == FQOS_A::LOW + } + #[doc = "Checks if the value of the field is `MEDIUM`"] + #[inline(always)] + pub fn is_medium(&self) -> bool { + **self == FQOS_A::MEDIUM + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == FQOS_A::HIGH + } +} +impl core::ops::Deref for FQOS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FQOS` writer - Fetch Quality of Service"] +pub struct FQOS_W<'a> { + w: &'a mut W, +} +impl<'a> FQOS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FQOS_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Background (no sensitive operation)"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(FQOS_A::DISABLE) + } + #[doc = "Sensitive Bandwidth"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(FQOS_A::LOW) + } + #[doc = "Sensitive Latency"] + #[inline(always)] + pub fn medium(self) -> &'a mut W { + self.variant(FQOS_A::MEDIUM) + } + #[doc = "Critical Latency"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(FQOS_A::HIGH) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u8 & 0x03) << 2); + self.w + } +} +#[doc = "Data Transfer Quality of Service\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DQOS_A { + #[doc = "0: Background (no sensitive operation)"] + DISABLE = 0, + #[doc = "1: Sensitive Bandwidth"] + LOW = 1, + #[doc = "2: Sensitive Latency"] + MEDIUM = 2, + #[doc = "3: Critical Latency"] + HIGH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DQOS_A) -> Self { + variant as _ + } +} +#[doc = "Field `DQOS` reader - Data Transfer Quality of Service"] +pub struct DQOS_R(crate::FieldReader); +impl DQOS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DQOS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DQOS_A { + match self.bits { + 0 => DQOS_A::DISABLE, + 1 => DQOS_A::LOW, + 2 => DQOS_A::MEDIUM, + 3 => DQOS_A::HIGH, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == DQOS_A::DISABLE + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == DQOS_A::LOW + } + #[doc = "Checks if the value of the field is `MEDIUM`"] + #[inline(always)] + pub fn is_medium(&self) -> bool { + **self == DQOS_A::MEDIUM + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == DQOS_A::HIGH + } +} +impl core::ops::Deref for DQOS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DQOS` writer - Data Transfer Quality of Service"] +pub struct DQOS_W<'a> { + w: &'a mut W, +} +impl<'a> DQOS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DQOS_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Background (no sensitive operation)"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(DQOS_A::DISABLE) + } + #[doc = "Sensitive Bandwidth"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(DQOS_A::LOW) + } + #[doc = "Sensitive Latency"] + #[inline(always)] + pub fn medium(self) -> &'a mut W { + self.variant(DQOS_A::MEDIUM) + } + #[doc = "Critical Latency"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(DQOS_A::HIGH) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u8 & 0x03) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Write-Back Quality of Service"] + #[inline(always)] + pub fn wrbqos(&self) -> WRBQOS_R { + WRBQOS_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bits 2:3 - Fetch Quality of Service"] + #[inline(always)] + pub fn fqos(&self) -> FQOS_R { + FQOS_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bits 4:5 - Data Transfer Quality of Service"] + #[inline(always)] + pub fn dqos(&self) -> DQOS_R { + DQOS_R::new(((self.bits >> 4) & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Write-Back Quality of Service"] + #[inline(always)] + pub fn wrbqos(&mut self) -> WRBQOS_W { + WRBQOS_W { w: self } + } + #[doc = "Bits 2:3 - Fetch Quality of Service"] + #[inline(always)] + pub fn fqos(&mut self) -> FQOS_W { + FQOS_W { w: self } + } + #[doc = "Bits 4:5 - Data Transfer Quality of Service"] + #[inline(always)] + pub fn dqos(&mut self) -> DQOS_W { + DQOS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "QOS Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [qosctrl](index.html) module"] +pub struct QOSCTRL_SPEC; +impl crate::RegisterSpec for QOSCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [qosctrl::R](R) reader structure"] +impl crate::Readable for QOSCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [qosctrl::W](W) writer structure"] +impl crate::Writable for QOSCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets QOSCTRL to value 0x2a"] +impl crate::Resettable for QOSCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x2a + } +} diff --git a/pac/atsamc21n/src/dmac/swtrigctrl.rs b/pac/atsamc21n/src/dmac/swtrigctrl.rs new file mode 100644 index 000000000000..8590fef852dc --- /dev/null +++ b/pac/atsamc21n/src/dmac/swtrigctrl.rs @@ -0,0 +1,630 @@ +#[doc = "Register `SWTRIGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SWTRIGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWTRIG0` reader - Channel 0 Software Trigger"] +pub struct SWTRIG0_R(crate::FieldReader); +impl SWTRIG0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG0` writer - Channel 0 Software Trigger"] +pub struct SWTRIG0_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `SWTRIG1` reader - Channel 1 Software Trigger"] +pub struct SWTRIG1_R(crate::FieldReader); +impl SWTRIG1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG1` writer - Channel 1 Software Trigger"] +pub struct SWTRIG1_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SWTRIG2` reader - Channel 2 Software Trigger"] +pub struct SWTRIG2_R(crate::FieldReader); +impl SWTRIG2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG2` writer - Channel 2 Software Trigger"] +pub struct SWTRIG2_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SWTRIG3` reader - Channel 3 Software Trigger"] +pub struct SWTRIG3_R(crate::FieldReader); +impl SWTRIG3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG3` writer - Channel 3 Software Trigger"] +pub struct SWTRIG3_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `SWTRIG4` reader - Channel 4 Software Trigger"] +pub struct SWTRIG4_R(crate::FieldReader); +impl SWTRIG4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG4` writer - Channel 4 Software Trigger"] +pub struct SWTRIG4_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `SWTRIG5` reader - Channel 5 Software Trigger"] +pub struct SWTRIG5_R(crate::FieldReader); +impl SWTRIG5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG5` writer - Channel 5 Software Trigger"] +pub struct SWTRIG5_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `SWTRIG6` reader - Channel 6 Software Trigger"] +pub struct SWTRIG6_R(crate::FieldReader); +impl SWTRIG6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG6` writer - Channel 6 Software Trigger"] +pub struct SWTRIG6_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `SWTRIG7` reader - Channel 7 Software Trigger"] +pub struct SWTRIG7_R(crate::FieldReader); +impl SWTRIG7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG7` writer - Channel 7 Software Trigger"] +pub struct SWTRIG7_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `SWTRIG8` reader - Channel 8 Software Trigger"] +pub struct SWTRIG8_R(crate::FieldReader); +impl SWTRIG8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG8` writer - Channel 8 Software Trigger"] +pub struct SWTRIG8_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `SWTRIG9` reader - Channel 9 Software Trigger"] +pub struct SWTRIG9_R(crate::FieldReader); +impl SWTRIG9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG9` writer - Channel 9 Software Trigger"] +pub struct SWTRIG9_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `SWTRIG10` reader - Channel 10 Software Trigger"] +pub struct SWTRIG10_R(crate::FieldReader); +impl SWTRIG10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG10` writer - Channel 10 Software Trigger"] +pub struct SWTRIG10_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `SWTRIG11` reader - Channel 11 Software Trigger"] +pub struct SWTRIG11_R(crate::FieldReader); +impl SWTRIG11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG11` writer - Channel 11 Software Trigger"] +pub struct SWTRIG11_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +impl R { + #[doc = "Bit 0 - Channel 0 Software Trigger"] + #[inline(always)] + pub fn swtrig0(&self) -> SWTRIG0_R { + SWTRIG0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel 1 Software Trigger"] + #[inline(always)] + pub fn swtrig1(&self) -> SWTRIG1_R { + SWTRIG1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel 2 Software Trigger"] + #[inline(always)] + pub fn swtrig2(&self) -> SWTRIG2_R { + SWTRIG2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Channel 3 Software Trigger"] + #[inline(always)] + pub fn swtrig3(&self) -> SWTRIG3_R { + SWTRIG3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Channel 4 Software Trigger"] + #[inline(always)] + pub fn swtrig4(&self) -> SWTRIG4_R { + SWTRIG4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Channel 5 Software Trigger"] + #[inline(always)] + pub fn swtrig5(&self) -> SWTRIG5_R { + SWTRIG5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Channel 6 Software Trigger"] + #[inline(always)] + pub fn swtrig6(&self) -> SWTRIG6_R { + SWTRIG6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Channel 7 Software Trigger"] + #[inline(always)] + pub fn swtrig7(&self) -> SWTRIG7_R { + SWTRIG7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Channel 8 Software Trigger"] + #[inline(always)] + pub fn swtrig8(&self) -> SWTRIG8_R { + SWTRIG8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Channel 9 Software Trigger"] + #[inline(always)] + pub fn swtrig9(&self) -> SWTRIG9_R { + SWTRIG9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Channel 10 Software Trigger"] + #[inline(always)] + pub fn swtrig10(&self) -> SWTRIG10_R { + SWTRIG10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Channel 11 Software Trigger"] + #[inline(always)] + pub fn swtrig11(&self) -> SWTRIG11_R { + SWTRIG11_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel 0 Software Trigger"] + #[inline(always)] + pub fn swtrig0(&mut self) -> SWTRIG0_W { + SWTRIG0_W { w: self } + } + #[doc = "Bit 1 - Channel 1 Software Trigger"] + #[inline(always)] + pub fn swtrig1(&mut self) -> SWTRIG1_W { + SWTRIG1_W { w: self } + } + #[doc = "Bit 2 - Channel 2 Software Trigger"] + #[inline(always)] + pub fn swtrig2(&mut self) -> SWTRIG2_W { + SWTRIG2_W { w: self } + } + #[doc = "Bit 3 - Channel 3 Software Trigger"] + #[inline(always)] + pub fn swtrig3(&mut self) -> SWTRIG3_W { + SWTRIG3_W { w: self } + } + #[doc = "Bit 4 - Channel 4 Software Trigger"] + #[inline(always)] + pub fn swtrig4(&mut self) -> SWTRIG4_W { + SWTRIG4_W { w: self } + } + #[doc = "Bit 5 - Channel 5 Software Trigger"] + #[inline(always)] + pub fn swtrig5(&mut self) -> SWTRIG5_W { + SWTRIG5_W { w: self } + } + #[doc = "Bit 6 - Channel 6 Software Trigger"] + #[inline(always)] + pub fn swtrig6(&mut self) -> SWTRIG6_W { + SWTRIG6_W { w: self } + } + #[doc = "Bit 7 - Channel 7 Software Trigger"] + #[inline(always)] + pub fn swtrig7(&mut self) -> SWTRIG7_W { + SWTRIG7_W { w: self } + } + #[doc = "Bit 8 - Channel 8 Software Trigger"] + #[inline(always)] + pub fn swtrig8(&mut self) -> SWTRIG8_W { + SWTRIG8_W { w: self } + } + #[doc = "Bit 9 - Channel 9 Software Trigger"] + #[inline(always)] + pub fn swtrig9(&mut self) -> SWTRIG9_W { + SWTRIG9_W { w: self } + } + #[doc = "Bit 10 - Channel 10 Software Trigger"] + #[inline(always)] + pub fn swtrig10(&mut self) -> SWTRIG10_W { + SWTRIG10_W { w: self } + } + #[doc = "Bit 11 - Channel 11 Software Trigger"] + #[inline(always)] + pub fn swtrig11(&mut self) -> SWTRIG11_W { + SWTRIG11_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Software Trigger Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [swtrigctrl](index.html) module"] +pub struct SWTRIGCTRL_SPEC; +impl crate::RegisterSpec for SWTRIGCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [swtrigctrl::R](R) reader structure"] +impl crate::Readable for SWTRIGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [swtrigctrl::W](W) writer structure"] +impl crate::Writable for SWTRIGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SWTRIGCTRL to value 0"] +impl crate::Resettable for SWTRIGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/dmac/wrbaddr.rs b/pac/atsamc21n/src/dmac/wrbaddr.rs new file mode 100644 index 000000000000..ccf2a376b853 --- /dev/null +++ b/pac/atsamc21n/src/dmac/wrbaddr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `WRBADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WRBADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WRBADDR` reader - Write-Back Memory Base Address"] +pub struct WRBADDR_R(crate::FieldReader); +impl WRBADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + WRBADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WRBADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WRBADDR` writer - Write-Back Memory Base Address"] +pub struct WRBADDR_W<'a> { + w: &'a mut W, +} +impl<'a> WRBADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Write-Back Memory Base Address"] + #[inline(always)] + pub fn wrbaddr(&self) -> WRBADDR_R { + WRBADDR_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Write-Back Memory Base Address"] + #[inline(always)] + pub fn wrbaddr(&mut self) -> WRBADDR_W { + WRBADDR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Write-Back Memory Section Base Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wrbaddr](index.html) module"] +pub struct WRBADDR_SPEC; +impl crate::RegisterSpec for WRBADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [wrbaddr::R](R) reader structure"] +impl crate::Readable for WRBADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wrbaddr::W](W) writer structure"] +impl crate::Writable for WRBADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WRBADDR to value 0"] +impl crate::Resettable for WRBADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/dsu.rs b/pac/atsamc21n/src/dsu.rs new file mode 100644 index 000000000000..14b78f6abfde --- /dev/null +++ b/pac/atsamc21n/src/dsu.rs @@ -0,0 +1,158 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrl: crate::Reg, + #[doc = "0x01 - Status A"] + pub statusa: crate::Reg, + #[doc = "0x02 - Status B"] + pub statusb: crate::Reg, + _reserved3: [u8; 0x01], + #[doc = "0x04 - Address"] + pub addr: crate::Reg, + #[doc = "0x08 - Length"] + pub length: crate::Reg, + #[doc = "0x0c - Data"] + pub data: crate::Reg, + #[doc = "0x10..0x18 - Debug Communication Channel n"] + pub dcc: [crate::Reg; 2], + #[doc = "0x18 - Device Identification"] + pub did: crate::Reg, + _reserved8: [u8; 0xd4], + #[doc = "0xf0..0xf8 - Device Configuration"] + pub dcfg: [crate::Reg; 2], + _reserved9: [u8; 0x0f08], + #[doc = "0x1000 - CoreSight ROM Table Entry 0"] + pub entry0: crate::Reg, + #[doc = "0x1004 - CoreSight ROM Table Entry 1"] + pub entry1: crate::Reg, + #[doc = "0x1008 - CoreSight ROM Table End"] + pub end: crate::Reg, + _reserved12: [u8; 0x0fc0], + #[doc = "0x1fcc - CoreSight ROM Table Memory Type"] + pub memtype: crate::Reg, + #[doc = "0x1fd0 - Peripheral Identification 4"] + pub pid4: crate::Reg, + #[doc = "0x1fd4 - Peripheral Identification 5"] + pub pid5: crate::Reg, + #[doc = "0x1fd8 - Peripheral Identification 6"] + pub pid6: crate::Reg, + #[doc = "0x1fdc - Peripheral Identification 7"] + pub pid7: crate::Reg, + #[doc = "0x1fe0 - Peripheral Identification 0"] + pub pid0: crate::Reg, + #[doc = "0x1fe4 - Peripheral Identification 1"] + pub pid1: crate::Reg, + #[doc = "0x1fe8 - Peripheral Identification 2"] + pub pid2: crate::Reg, + #[doc = "0x1fec - Peripheral Identification 3"] + pub pid3: crate::Reg, + #[doc = "0x1ff0 - Component Identification 0"] + pub cid0: crate::Reg, + #[doc = "0x1ff4 - Component Identification 1"] + pub cid1: crate::Reg, + #[doc = "0x1ff8 - Component Identification 2"] + pub cid2: crate::Reg, + #[doc = "0x1ffc - Component Identification 3"] + pub cid3: crate::Reg, +} +#[doc = "CTRL register accessor: an alias for `Reg`"] +pub type CTRL = crate::Reg; +#[doc = "Control"] +pub mod ctrl; +#[doc = "STATUSA register accessor: an alias for `Reg`"] +pub type STATUSA = crate::Reg; +#[doc = "Status A"] +pub mod statusa; +#[doc = "STATUSB register accessor: an alias for `Reg`"] +pub type STATUSB = crate::Reg; +#[doc = "Status B"] +pub mod statusb; +#[doc = "ADDR register accessor: an alias for `Reg`"] +pub type ADDR = crate::Reg; +#[doc = "Address"] +pub mod addr; +#[doc = "LENGTH register accessor: an alias for `Reg`"] +pub type LENGTH = crate::Reg; +#[doc = "Length"] +pub mod length; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "Data"] +pub mod data; +#[doc = "DCC register accessor: an alias for `Reg`"] +pub type DCC = crate::Reg; +#[doc = "Debug Communication Channel n"] +pub mod dcc; +#[doc = "DID register accessor: an alias for `Reg`"] +pub type DID = crate::Reg; +#[doc = "Device Identification"] +pub mod did; +#[doc = "DCFG register accessor: an alias for `Reg`"] +pub type DCFG = crate::Reg; +#[doc = "Device Configuration"] +pub mod dcfg; +#[doc = "ENTRY0 register accessor: an alias for `Reg`"] +pub type ENTRY0 = crate::Reg; +#[doc = "CoreSight ROM Table Entry 0"] +pub mod entry0; +#[doc = "ENTRY1 register accessor: an alias for `Reg`"] +pub type ENTRY1 = crate::Reg; +#[doc = "CoreSight ROM Table Entry 1"] +pub mod entry1; +#[doc = "END register accessor: an alias for `Reg`"] +pub type END = crate::Reg; +#[doc = "CoreSight ROM Table End"] +pub mod end; +#[doc = "MEMTYPE register accessor: an alias for `Reg`"] +pub type MEMTYPE = crate::Reg; +#[doc = "CoreSight ROM Table Memory Type"] +pub mod memtype; +#[doc = "PID4 register accessor: an alias for `Reg`"] +pub type PID4 = crate::Reg; +#[doc = "Peripheral Identification 4"] +pub mod pid4; +#[doc = "PID5 register accessor: an alias for `Reg`"] +pub type PID5 = crate::Reg; +#[doc = "Peripheral Identification 5"] +pub mod pid5; +#[doc = "PID6 register accessor: an alias for `Reg`"] +pub type PID6 = crate::Reg; +#[doc = "Peripheral Identification 6"] +pub mod pid6; +#[doc = "PID7 register accessor: an alias for `Reg`"] +pub type PID7 = crate::Reg; +#[doc = "Peripheral Identification 7"] +pub mod pid7; +#[doc = "PID0 register accessor: an alias for `Reg`"] +pub type PID0 = crate::Reg; +#[doc = "Peripheral Identification 0"] +pub mod pid0; +#[doc = "PID1 register accessor: an alias for `Reg`"] +pub type PID1 = crate::Reg; +#[doc = "Peripheral Identification 1"] +pub mod pid1; +#[doc = "PID2 register accessor: an alias for `Reg`"] +pub type PID2 = crate::Reg; +#[doc = "Peripheral Identification 2"] +pub mod pid2; +#[doc = "PID3 register accessor: an alias for `Reg`"] +pub type PID3 = crate::Reg; +#[doc = "Peripheral Identification 3"] +pub mod pid3; +#[doc = "CID0 register accessor: an alias for `Reg`"] +pub type CID0 = crate::Reg; +#[doc = "Component Identification 0"] +pub mod cid0; +#[doc = "CID1 register accessor: an alias for `Reg`"] +pub type CID1 = crate::Reg; +#[doc = "Component Identification 1"] +pub mod cid1; +#[doc = "CID2 register accessor: an alias for `Reg`"] +pub type CID2 = crate::Reg; +#[doc = "Component Identification 2"] +pub mod cid2; +#[doc = "CID3 register accessor: an alias for `Reg`"] +pub type CID3 = crate::Reg; +#[doc = "Component Identification 3"] +pub mod cid3; diff --git a/pac/atsamc21n/src/dsu/addr.rs b/pac/atsamc21n/src/dsu/addr.rs new file mode 100644 index 000000000000..412f874d6b15 --- /dev/null +++ b/pac/atsamc21n/src/dsu/addr.rs @@ -0,0 +1,140 @@ +#[doc = "Register `ADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `AMOD` reader - Access Mode"] +pub struct AMOD_R(crate::FieldReader); +impl AMOD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + AMOD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AMOD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AMOD` writer - Access Mode"] +pub struct AMOD_W<'a> { + w: &'a mut W, +} +impl<'a> AMOD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u32 & 0x03); + self.w + } +} +#[doc = "Field `ADDR` reader - Address"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - Address"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3fff_ffff << 2)) | ((value as u32 & 0x3fff_ffff) << 2); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Access Mode"] + #[inline(always)] + pub fn amod(&self) -> AMOD_R { + AMOD_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bits 2:31 - Address"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new(((self.bits >> 2) & 0x3fff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:1 - Access Mode"] + #[inline(always)] + pub fn amod(&mut self) -> AMOD_W { + AMOD_W { w: self } + } + #[doc = "Bits 2:31 - Address"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [addr](index.html) module"] +pub struct ADDR_SPEC; +impl crate::RegisterSpec for ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [addr::R](R) reader structure"] +impl crate::Readable for ADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [addr::W](W) writer structure"] +impl crate::Writable for ADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ADDR to value 0"] +impl crate::Resettable for ADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/dsu/cid0.rs b/pac/atsamc21n/src/dsu/cid0.rs new file mode 100644 index 000000000000..b3c2373dfc99 --- /dev/null +++ b/pac/atsamc21n/src/dsu/cid0.rs @@ -0,0 +1,53 @@ +#[doc = "Register `CID0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PREAMBLEB0` reader - Preamble Byte 0"] +pub struct PREAMBLEB0_R(crate::FieldReader); +impl PREAMBLEB0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PREAMBLEB0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PREAMBLEB0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:7 - Preamble Byte 0"] + #[inline(always)] + pub fn preambleb0(&self) -> PREAMBLEB0_R { + PREAMBLEB0_R::new((self.bits & 0xff) as u8) + } +} +#[doc = "Component Identification 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid0](index.html) module"] +pub struct CID0_SPEC; +impl crate::RegisterSpec for CID0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid0::R](R) reader structure"] +impl crate::Readable for CID0_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID0 to value 0x0d"] +impl crate::Resettable for CID0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0d + } +} diff --git a/pac/atsamc21n/src/dsu/cid1.rs b/pac/atsamc21n/src/dsu/cid1.rs new file mode 100644 index 000000000000..3628ceac64a7 --- /dev/null +++ b/pac/atsamc21n/src/dsu/cid1.rs @@ -0,0 +1,73 @@ +#[doc = "Register `CID1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PREAMBLE` reader - Preamble"] +pub struct PREAMBLE_R(crate::FieldReader); +impl PREAMBLE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PREAMBLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PREAMBLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCLASS` reader - Component Class"] +pub struct CCLASS_R(crate::FieldReader); +impl CCLASS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CCLASS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCLASS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:3 - Preamble"] + #[inline(always)] + pub fn preamble(&self) -> PREAMBLE_R { + PREAMBLE_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Component Class"] + #[inline(always)] + pub fn cclass(&self) -> CCLASS_R { + CCLASS_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +#[doc = "Component Identification 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid1](index.html) module"] +pub struct CID1_SPEC; +impl crate::RegisterSpec for CID1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid1::R](R) reader structure"] +impl crate::Readable for CID1_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID1 to value 0x10"] +impl crate::Resettable for CID1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x10 + } +} diff --git a/pac/atsamc21n/src/dsu/cid2.rs b/pac/atsamc21n/src/dsu/cid2.rs new file mode 100644 index 000000000000..714078d5c430 --- /dev/null +++ b/pac/atsamc21n/src/dsu/cid2.rs @@ -0,0 +1,53 @@ +#[doc = "Register `CID2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PREAMBLEB2` reader - Preamble Byte 2"] +pub struct PREAMBLEB2_R(crate::FieldReader); +impl PREAMBLEB2_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PREAMBLEB2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PREAMBLEB2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:7 - Preamble Byte 2"] + #[inline(always)] + pub fn preambleb2(&self) -> PREAMBLEB2_R { + PREAMBLEB2_R::new((self.bits & 0xff) as u8) + } +} +#[doc = "Component Identification 2\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid2](index.html) module"] +pub struct CID2_SPEC; +impl crate::RegisterSpec for CID2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid2::R](R) reader structure"] +impl crate::Readable for CID2_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID2 to value 0x05"] +impl crate::Resettable for CID2_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x05 + } +} diff --git a/pac/atsamc21n/src/dsu/cid3.rs b/pac/atsamc21n/src/dsu/cid3.rs new file mode 100644 index 000000000000..a345af7b5166 --- /dev/null +++ b/pac/atsamc21n/src/dsu/cid3.rs @@ -0,0 +1,53 @@ +#[doc = "Register `CID3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PREAMBLEB3` reader - Preamble Byte 3"] +pub struct PREAMBLEB3_R(crate::FieldReader); +impl PREAMBLEB3_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PREAMBLEB3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PREAMBLEB3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:7 - Preamble Byte 3"] + #[inline(always)] + pub fn preambleb3(&self) -> PREAMBLEB3_R { + PREAMBLEB3_R::new((self.bits & 0xff) as u8) + } +} +#[doc = "Component Identification 3\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid3](index.html) module"] +pub struct CID3_SPEC; +impl crate::RegisterSpec for CID3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid3::R](R) reader structure"] +impl crate::Readable for CID3_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID3 to value 0xb1"] +impl crate::Resettable for CID3_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xb1 + } +} diff --git a/pac/atsamc21n/src/dsu/ctrl.rs b/pac/atsamc21n/src/dsu/ctrl.rs new file mode 100644 index 000000000000..0a19db5a5239 --- /dev/null +++ b/pac/atsamc21n/src/dsu/ctrl.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `CRC` writer - 32-bit Cyclic Redundancy Code"] +pub struct CRC_W<'a> { + w: &'a mut W, +} +impl<'a> CRC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `MBIST` writer - Memory built-in self-test"] +pub struct MBIST_W<'a> { + w: &'a mut W, +} +impl<'a> MBIST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CE` writer - Chip-Erase"] +pub struct CE_W<'a> { + w: &'a mut W, +} +impl<'a> CE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `ARR` writer - Auxiliary Row Read"] +pub struct ARR_W<'a> { + w: &'a mut W, +} +impl<'a> ARR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +#[doc = "Field `SMSA` writer - Start Memory Stream Access"] +pub struct SMSA_W<'a> { + w: &'a mut W, +} +impl<'a> SMSA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 2 - 32-bit Cyclic Redundancy Code"] + #[inline(always)] + pub fn crc(&mut self) -> CRC_W { + CRC_W { w: self } + } + #[doc = "Bit 3 - Memory built-in self-test"] + #[inline(always)] + pub fn mbist(&mut self) -> MBIST_W { + MBIST_W { w: self } + } + #[doc = "Bit 4 - Chip-Erase"] + #[inline(always)] + pub fn ce(&mut self) -> CE_W { + CE_W { w: self } + } + #[doc = "Bit 6 - Auxiliary Row Read"] + #[inline(always)] + pub fn arr(&mut self) -> ARR_W { + ARR_W { w: self } + } + #[doc = "Bit 7 - Start Memory Stream Access"] + #[inline(always)] + pub fn smsa(&mut self) -> SMSA_W { + SMSA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"] +pub struct CTRL_SPEC; +impl crate::RegisterSpec for CTRL_SPEC { + type Ux = u8; +} +#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"] +impl crate::Writable for CTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/dsu/data.rs b/pac/atsamc21n/src/dsu/data.rs new file mode 100644 index 000000000000..193cc49a07fd --- /dev/null +++ b/pac/atsamc21n/src/dsu/data.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Data"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Data"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/dsu/dcc.rs b/pac/atsamc21n/src/dsu/dcc.rs new file mode 100644 index 000000000000..354323a499ef --- /dev/null +++ b/pac/atsamc21n/src/dsu/dcc.rs @@ -0,0 +1,104 @@ +#[doc = "Register `DCC[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DCC[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Data"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Data"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Communication Channel n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dcc](index.html) module"] +pub struct DCC_SPEC; +impl crate::RegisterSpec for DCC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dcc::R](R) reader structure"] +impl crate::Readable for DCC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dcc::W](W) writer structure"] +impl crate::Writable for DCC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DCC[%s] +to value 0"] +impl crate::Resettable for DCC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/dsu/dcfg.rs b/pac/atsamc21n/src/dsu/dcfg.rs new file mode 100644 index 000000000000..c6d61d0b496e --- /dev/null +++ b/pac/atsamc21n/src/dsu/dcfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `DCFG[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DCFG[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DCFG` reader - Device Configuration"] +pub struct DCFG_R(crate::FieldReader); +impl DCFG_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + DCFG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DCFG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DCFG` writer - Device Configuration"] +pub struct DCFG_W<'a> { + w: &'a mut W, +} +impl<'a> DCFG_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Device Configuration"] + #[inline(always)] + pub fn dcfg(&self) -> DCFG_R { + DCFG_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Device Configuration"] + #[inline(always)] + pub fn dcfg(&mut self) -> DCFG_W { + DCFG_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Device Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dcfg](index.html) module"] +pub struct DCFG_SPEC; +impl crate::RegisterSpec for DCFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dcfg::R](R) reader structure"] +impl crate::Readable for DCFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dcfg::W](W) writer structure"] +impl crate::Writable for DCFG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DCFG[%s] +to value 0"] +impl crate::Resettable for DCFG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/dsu/did.rs b/pac/atsamc21n/src/dsu/did.rs new file mode 100644 index 000000000000..1cddc9b5fb48 --- /dev/null +++ b/pac/atsamc21n/src/dsu/did.rs @@ -0,0 +1,279 @@ +#[doc = "Register `DID` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `DEVSEL` reader - Device Select"] +pub struct DEVSEL_R(crate::FieldReader); +impl DEVSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DEVSEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DEVSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REVISION` reader - Revision Number"] +pub struct REVISION_R(crate::FieldReader); +impl REVISION_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REVISION_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REVISION_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIE` reader - Die Number"] +pub struct DIE_R(crate::FieldReader); +impl DIE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DIE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Series\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SERIES_A { + #[doc = "0: Cortex-M0+ processor, basic feature set"] + _0 = 0, + #[doc = "1: Cortex-M0+ processor, USB"] + _1 = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SERIES_A) -> Self { + variant as _ + } +} +#[doc = "Field `SERIES` reader - Series"] +pub struct SERIES_R(crate::FieldReader); +impl SERIES_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SERIES_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SERIES_A::_0), + 1 => Some(SERIES_A::_1), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_0`"] + #[inline(always)] + pub fn is_0(&self) -> bool { + **self == SERIES_A::_0 + } + #[doc = "Checks if the value of the field is `_1`"] + #[inline(always)] + pub fn is_1(&self) -> bool { + **self == SERIES_A::_1 + } +} +impl core::ops::Deref for SERIES_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Family\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FAMILY_A { + #[doc = "0: General purpose microcontroller"] + _0 = 0, + #[doc = "1: PicoPower"] + _1 = 1, + #[doc = "2: 5V Industrial"] + _2 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FAMILY_A) -> Self { + variant as _ + } +} +#[doc = "Field `FAMILY` reader - Family"] +pub struct FAMILY_R(crate::FieldReader); +impl FAMILY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FAMILY_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(FAMILY_A::_0), + 1 => Some(FAMILY_A::_1), + 2 => Some(FAMILY_A::_2), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_0`"] + #[inline(always)] + pub fn is_0(&self) -> bool { + **self == FAMILY_A::_0 + } + #[doc = "Checks if the value of the field is `_1`"] + #[inline(always)] + pub fn is_1(&self) -> bool { + **self == FAMILY_A::_1 + } + #[doc = "Checks if the value of the field is `_2`"] + #[inline(always)] + pub fn is_2(&self) -> bool { + **self == FAMILY_A::_2 + } +} +impl core::ops::Deref for FAMILY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Processor\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PROCESSOR_A { + #[doc = "0: Cortex-M0"] + _0 = 0, + #[doc = "1: Cortex-M0+"] + _1 = 1, + #[doc = "2: Cortex-M3"] + _2 = 2, + #[doc = "3: Cortex-M4"] + _3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PROCESSOR_A) -> Self { + variant as _ + } +} +#[doc = "Field `PROCESSOR` reader - Processor"] +pub struct PROCESSOR_R(crate::FieldReader); +impl PROCESSOR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PROCESSOR_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PROCESSOR_A::_0), + 1 => Some(PROCESSOR_A::_1), + 2 => Some(PROCESSOR_A::_2), + 3 => Some(PROCESSOR_A::_3), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_0`"] + #[inline(always)] + pub fn is_0(&self) -> bool { + **self == PROCESSOR_A::_0 + } + #[doc = "Checks if the value of the field is `_1`"] + #[inline(always)] + pub fn is_1(&self) -> bool { + **self == PROCESSOR_A::_1 + } + #[doc = "Checks if the value of the field is `_2`"] + #[inline(always)] + pub fn is_2(&self) -> bool { + **self == PROCESSOR_A::_2 + } + #[doc = "Checks if the value of the field is `_3`"] + #[inline(always)] + pub fn is_3(&self) -> bool { + **self == PROCESSOR_A::_3 + } +} +impl core::ops::Deref for PROCESSOR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:7 - Device Select"] + #[inline(always)] + pub fn devsel(&self) -> DEVSEL_R { + DEVSEL_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:11 - Revision Number"] + #[inline(always)] + pub fn revision(&self) -> REVISION_R { + REVISION_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - Die Number"] + #[inline(always)] + pub fn die(&self) -> DIE_R { + DIE_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:21 - Series"] + #[inline(always)] + pub fn series(&self) -> SERIES_R { + SERIES_R::new(((self.bits >> 16) & 0x3f) as u8) + } + #[doc = "Bits 23:27 - Family"] + #[inline(always)] + pub fn family(&self) -> FAMILY_R { + FAMILY_R::new(((self.bits >> 23) & 0x1f) as u8) + } + #[doc = "Bits 28:31 - Processor"] + #[inline(always)] + pub fn processor(&self) -> PROCESSOR_R { + PROCESSOR_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +#[doc = "Device Identification\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [did](index.html) module"] +pub struct DID_SPEC; +impl crate::RegisterSpec for DID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [did::R](R) reader structure"] +impl crate::Readable for DID_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DID to value 0x1101_1420"] +impl crate::Resettable for DID_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x1101_1420 + } +} diff --git a/pac/atsamc21n/src/dsu/end.rs b/pac/atsamc21n/src/dsu/end.rs new file mode 100644 index 000000000000..cce2edea2bce --- /dev/null +++ b/pac/atsamc21n/src/dsu/end.rs @@ -0,0 +1,53 @@ +#[doc = "Register `END` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `END` reader - End Marker"] +pub struct END_R(crate::FieldReader); +impl END_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + END_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for END_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - End Marker"] + #[inline(always)] + pub fn end(&self) -> END_R { + END_R::new(self.bits as u32) + } +} +#[doc = "CoreSight ROM Table End\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [end](index.html) module"] +pub struct END_SPEC; +impl crate::RegisterSpec for END_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [end::R](R) reader structure"] +impl crate::Readable for END_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets END to value 0"] +impl crate::Resettable for END_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/dsu/entry0.rs b/pac/atsamc21n/src/dsu/entry0.rs new file mode 100644 index 000000000000..d8563990e827 --- /dev/null +++ b/pac/atsamc21n/src/dsu/entry0.rs @@ -0,0 +1,93 @@ +#[doc = "Register `ENTRY0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `EPRES` reader - Entry Present"] +pub struct EPRES_R(crate::FieldReader); +impl EPRES_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EPRES_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EPRES_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FMT` reader - Format"] +pub struct FMT_R(crate::FieldReader); +impl FMT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FMT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FMT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDOFF` reader - Address Offset"] +pub struct ADDOFF_R(crate::FieldReader); +impl ADDOFF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + ADDOFF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDOFF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Entry Present"] + #[inline(always)] + pub fn epres(&self) -> EPRES_R { + EPRES_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Format"] + #[inline(always)] + pub fn fmt(&self) -> FMT_R { + FMT_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 12:31 - Address Offset"] + #[inline(always)] + pub fn addoff(&self) -> ADDOFF_R { + ADDOFF_R::new(((self.bits >> 12) & 0x000f_ffff) as u32) + } +} +#[doc = "CoreSight ROM Table Entry 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [entry0](index.html) module"] +pub struct ENTRY0_SPEC; +impl crate::RegisterSpec for ENTRY0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [entry0::R](R) reader structure"] +impl crate::Readable for ENTRY0_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets ENTRY0 to value 0x9f0f_c002"] +impl crate::Resettable for ENTRY0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x9f0f_c002 + } +} diff --git a/pac/atsamc21n/src/dsu/entry1.rs b/pac/atsamc21n/src/dsu/entry1.rs new file mode 100644 index 000000000000..cec8fa367705 --- /dev/null +++ b/pac/atsamc21n/src/dsu/entry1.rs @@ -0,0 +1,31 @@ +#[doc = "Register `ENTRY1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "CoreSight ROM Table Entry 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [entry1](index.html) module"] +pub struct ENTRY1_SPEC; +impl crate::RegisterSpec for ENTRY1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [entry1::R](R) reader structure"] +impl crate::Readable for ENTRY1_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets ENTRY1 to value 0x5002"] +impl crate::Resettable for ENTRY1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x5002 + } +} diff --git a/pac/atsamc21n/src/dsu/length.rs b/pac/atsamc21n/src/dsu/length.rs new file mode 100644 index 000000000000..2dc771f74dfd --- /dev/null +++ b/pac/atsamc21n/src/dsu/length.rs @@ -0,0 +1,103 @@ +#[doc = "Register `LENGTH` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `LENGTH` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `LENGTH` reader - Length"] +pub struct LENGTH_R(crate::FieldReader); +impl LENGTH_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + LENGTH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LENGTH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LENGTH` writer - Length"] +pub struct LENGTH_W<'a> { + w: &'a mut W, +} +impl<'a> LENGTH_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3fff_ffff << 2)) | ((value as u32 & 0x3fff_ffff) << 2); + self.w + } +} +impl R { + #[doc = "Bits 2:31 - Length"] + #[inline(always)] + pub fn length(&self) -> LENGTH_R { + LENGTH_R::new(((self.bits >> 2) & 0x3fff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 2:31 - Length"] + #[inline(always)] + pub fn length(&mut self) -> LENGTH_W { + LENGTH_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Length\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [length](index.html) module"] +pub struct LENGTH_SPEC; +impl crate::RegisterSpec for LENGTH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [length::R](R) reader structure"] +impl crate::Readable for LENGTH_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [length::W](W) writer structure"] +impl crate::Writable for LENGTH_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets LENGTH to value 0"] +impl crate::Resettable for LENGTH_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/dsu/memtype.rs b/pac/atsamc21n/src/dsu/memtype.rs new file mode 100644 index 000000000000..3cc841e2ba78 --- /dev/null +++ b/pac/atsamc21n/src/dsu/memtype.rs @@ -0,0 +1,53 @@ +#[doc = "Register `MEMTYPE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SMEMP` reader - System Memory Present"] +pub struct SMEMP_R(crate::FieldReader); +impl SMEMP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SMEMP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SMEMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - System Memory Present"] + #[inline(always)] + pub fn smemp(&self) -> SMEMP_R { + SMEMP_R::new((self.bits & 0x01) != 0) + } +} +#[doc = "CoreSight ROM Table Memory Type\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [memtype](index.html) module"] +pub struct MEMTYPE_SPEC; +impl crate::RegisterSpec for MEMTYPE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [memtype::R](R) reader structure"] +impl crate::Readable for MEMTYPE_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets MEMTYPE to value 0"] +impl crate::Resettable for MEMTYPE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/dsu/pid0.rs b/pac/atsamc21n/src/dsu/pid0.rs new file mode 100644 index 000000000000..98028ea62838 --- /dev/null +++ b/pac/atsamc21n/src/dsu/pid0.rs @@ -0,0 +1,53 @@ +#[doc = "Register `PID0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PARTNBL` reader - Part Number Low"] +pub struct PARTNBL_R(crate::FieldReader); +impl PARTNBL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PARTNBL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PARTNBL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:7 - Part Number Low"] + #[inline(always)] + pub fn partnbl(&self) -> PARTNBL_R { + PARTNBL_R::new((self.bits & 0xff) as u8) + } +} +#[doc = "Peripheral Identification 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid0](index.html) module"] +pub struct PID0_SPEC; +impl crate::RegisterSpec for PID0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid0::R](R) reader structure"] +impl crate::Readable for PID0_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID0 to value 0xd0"] +impl crate::Resettable for PID0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xd0 + } +} diff --git a/pac/atsamc21n/src/dsu/pid1.rs b/pac/atsamc21n/src/dsu/pid1.rs new file mode 100644 index 000000000000..4f94b853507c --- /dev/null +++ b/pac/atsamc21n/src/dsu/pid1.rs @@ -0,0 +1,73 @@ +#[doc = "Register `PID1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PARTNBH` reader - Part Number High"] +pub struct PARTNBH_R(crate::FieldReader); +impl PARTNBH_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PARTNBH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PARTNBH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `JEPIDCL` reader - Low part of the JEP-106 Identity Code"] +pub struct JEPIDCL_R(crate::FieldReader); +impl JEPIDCL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + JEPIDCL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for JEPIDCL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:3 - Part Number High"] + #[inline(always)] + pub fn partnbh(&self) -> PARTNBH_R { + PARTNBH_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Low part of the JEP-106 Identity Code"] + #[inline(always)] + pub fn jepidcl(&self) -> JEPIDCL_R { + JEPIDCL_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +#[doc = "Peripheral Identification 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid1](index.html) module"] +pub struct PID1_SPEC; +impl crate::RegisterSpec for PID1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid1::R](R) reader structure"] +impl crate::Readable for PID1_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID1 to value 0xfc"] +impl crate::Resettable for PID1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xfc + } +} diff --git a/pac/atsamc21n/src/dsu/pid2.rs b/pac/atsamc21n/src/dsu/pid2.rs new file mode 100644 index 000000000000..d8f8ed10192e --- /dev/null +++ b/pac/atsamc21n/src/dsu/pid2.rs @@ -0,0 +1,93 @@ +#[doc = "Register `PID2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `JEPIDCH` reader - JEP-106 Identity Code High"] +pub struct JEPIDCH_R(crate::FieldReader); +impl JEPIDCH_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + JEPIDCH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for JEPIDCH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `JEPU` reader - JEP-106 Identity Code is used"] +pub struct JEPU_R(crate::FieldReader); +impl JEPU_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + JEPU_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for JEPU_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REVISION` reader - Revision Number"] +pub struct REVISION_R(crate::FieldReader); +impl REVISION_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REVISION_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REVISION_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:2 - JEP-106 Identity Code High"] + #[inline(always)] + pub fn jepidch(&self) -> JEPIDCH_R { + JEPIDCH_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 3 - JEP-106 Identity Code is used"] + #[inline(always)] + pub fn jepu(&self) -> JEPU_R { + JEPU_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bits 4:7 - Revision Number"] + #[inline(always)] + pub fn revision(&self) -> REVISION_R { + REVISION_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +#[doc = "Peripheral Identification 2\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid2](index.html) module"] +pub struct PID2_SPEC; +impl crate::RegisterSpec for PID2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid2::R](R) reader structure"] +impl crate::Readable for PID2_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID2 to value 0x09"] +impl crate::Resettable for PID2_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x09 + } +} diff --git a/pac/atsamc21n/src/dsu/pid3.rs b/pac/atsamc21n/src/dsu/pid3.rs new file mode 100644 index 000000000000..c0a8fb2d7f92 --- /dev/null +++ b/pac/atsamc21n/src/dsu/pid3.rs @@ -0,0 +1,73 @@ +#[doc = "Register `PID3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `CUSMOD` reader - ARM CUSMOD"] +pub struct CUSMOD_R(crate::FieldReader); +impl CUSMOD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CUSMOD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CUSMOD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REVAND` reader - Revision Number"] +pub struct REVAND_R(crate::FieldReader); +impl REVAND_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REVAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REVAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:3 - ARM CUSMOD"] + #[inline(always)] + pub fn cusmod(&self) -> CUSMOD_R { + CUSMOD_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Revision Number"] + #[inline(always)] + pub fn revand(&self) -> REVAND_R { + REVAND_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +#[doc = "Peripheral Identification 3\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid3](index.html) module"] +pub struct PID3_SPEC; +impl crate::RegisterSpec for PID3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid3::R](R) reader structure"] +impl crate::Readable for PID3_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID3 to value 0"] +impl crate::Resettable for PID3_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/dsu/pid4.rs b/pac/atsamc21n/src/dsu/pid4.rs new file mode 100644 index 000000000000..d3a1bd120f0b --- /dev/null +++ b/pac/atsamc21n/src/dsu/pid4.rs @@ -0,0 +1,73 @@ +#[doc = "Register `PID4` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `JEPCC` reader - JEP-106 Continuation Code"] +pub struct JEPCC_R(crate::FieldReader); +impl JEPCC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + JEPCC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for JEPCC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FKBC` reader - 4KB count"] +pub struct FKBC_R(crate::FieldReader); +impl FKBC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FKBC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FKBC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:3 - JEP-106 Continuation Code"] + #[inline(always)] + pub fn jepcc(&self) -> JEPCC_R { + JEPCC_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - 4KB count"] + #[inline(always)] + pub fn fkbc(&self) -> FKBC_R { + FKBC_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +#[doc = "Peripheral Identification 4\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid4](index.html) module"] +pub struct PID4_SPEC; +impl crate::RegisterSpec for PID4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid4::R](R) reader structure"] +impl crate::Readable for PID4_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID4 to value 0"] +impl crate::Resettable for PID4_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/dsu/pid5.rs b/pac/atsamc21n/src/dsu/pid5.rs new file mode 100644 index 000000000000..d343d4800b95 --- /dev/null +++ b/pac/atsamc21n/src/dsu/pid5.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID5` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 5\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid5](index.html) module"] +pub struct PID5_SPEC; +impl crate::RegisterSpec for PID5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid5::R](R) reader structure"] +impl crate::Readable for PID5_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID5 to value 0"] +impl crate::Resettable for PID5_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/dsu/pid6.rs b/pac/atsamc21n/src/dsu/pid6.rs new file mode 100644 index 000000000000..55cc2b8b5861 --- /dev/null +++ b/pac/atsamc21n/src/dsu/pid6.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID6` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 6\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid6](index.html) module"] +pub struct PID6_SPEC; +impl crate::RegisterSpec for PID6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid6::R](R) reader structure"] +impl crate::Readable for PID6_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID6 to value 0"] +impl crate::Resettable for PID6_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/dsu/pid7.rs b/pac/atsamc21n/src/dsu/pid7.rs new file mode 100644 index 000000000000..77664d4f2f95 --- /dev/null +++ b/pac/atsamc21n/src/dsu/pid7.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID7` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 7\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid7](index.html) module"] +pub struct PID7_SPEC; +impl crate::RegisterSpec for PID7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid7::R](R) reader structure"] +impl crate::Readable for PID7_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID7 to value 0"] +impl crate::Resettable for PID7_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/dsu/statusa.rs b/pac/atsamc21n/src/dsu/statusa.rs new file mode 100644 index 000000000000..c7b90a13e491 --- /dev/null +++ b/pac/atsamc21n/src/dsu/statusa.rs @@ -0,0 +1,301 @@ +#[doc = "Register `STATUSA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUSA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DONE` reader - Done"] +pub struct DONE_R(crate::FieldReader); +impl DONE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DONE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DONE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DONE` writer - Done"] +pub struct DONE_W<'a> { + w: &'a mut W, +} +impl<'a> DONE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `CRSTEXT` reader - CPU Reset Phase Extension"] +pub struct CRSTEXT_R(crate::FieldReader); +impl CRSTEXT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CRSTEXT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CRSTEXT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRSTEXT` writer - CPU Reset Phase Extension"] +pub struct CRSTEXT_W<'a> { + w: &'a mut W, +} +impl<'a> CRSTEXT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `BERR` reader - Bus Error"] +pub struct BERR_R(crate::FieldReader); +impl BERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BERR` writer - Bus Error"] +pub struct BERR_W<'a> { + w: &'a mut W, +} +impl<'a> BERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `FAIL` reader - Failure"] +pub struct FAIL_R(crate::FieldReader); +impl FAIL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAIL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAIL` writer - Failure"] +pub struct FAIL_W<'a> { + w: &'a mut W, +} +impl<'a> FAIL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PERR` reader - Protection Error"] +pub struct PERR_R(crate::FieldReader); +impl PERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERR` writer - Protection Error"] +pub struct PERR_W<'a> { + w: &'a mut W, +} +impl<'a> PERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +impl R { + #[doc = "Bit 0 - Done"] + #[inline(always)] + pub fn done(&self) -> DONE_R { + DONE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - CPU Reset Phase Extension"] + #[inline(always)] + pub fn crstext(&self) -> CRSTEXT_R { + CRSTEXT_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Bus Error"] + #[inline(always)] + pub fn berr(&self) -> BERR_R { + BERR_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Failure"] + #[inline(always)] + pub fn fail(&self) -> FAIL_R { + FAIL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Protection Error"] + #[inline(always)] + pub fn perr(&self) -> PERR_R { + PERR_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Done"] + #[inline(always)] + pub fn done(&mut self) -> DONE_W { + DONE_W { w: self } + } + #[doc = "Bit 1 - CPU Reset Phase Extension"] + #[inline(always)] + pub fn crstext(&mut self) -> CRSTEXT_W { + CRSTEXT_W { w: self } + } + #[doc = "Bit 2 - Bus Error"] + #[inline(always)] + pub fn berr(&mut self) -> BERR_W { + BERR_W { w: self } + } + #[doc = "Bit 3 - Failure"] + #[inline(always)] + pub fn fail(&mut self) -> FAIL_W { + FAIL_W { w: self } + } + #[doc = "Bit 4 - Protection Error"] + #[inline(always)] + pub fn perr(&mut self) -> PERR_W { + PERR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [statusa](index.html) module"] +pub struct STATUSA_SPEC; +impl crate::RegisterSpec for STATUSA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [statusa::R](R) reader structure"] +impl crate::Readable for STATUSA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [statusa::W](W) writer structure"] +impl crate::Writable for STATUSA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUSA to value 0"] +impl crate::Resettable for STATUSA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/dsu/statusb.rs b/pac/atsamc21n/src/dsu/statusb.rs new file mode 100644 index 000000000000..1e9374f8deae --- /dev/null +++ b/pac/atsamc21n/src/dsu/statusb.rs @@ -0,0 +1,133 @@ +#[doc = "Register `STATUSB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PROT` reader - Protected"] +pub struct PROT_R(crate::FieldReader); +impl PROT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PROT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PROT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGPRES` reader - Debugger Present"] +pub struct DBGPRES_R(crate::FieldReader); +impl DBGPRES_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGPRES_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGPRES_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DCCD0` reader - Debug Communication Channel 0 Dirty"] +pub struct DCCD0_R(crate::FieldReader); +impl DCCD0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DCCD0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DCCD0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DCCD1` reader - Debug Communication Channel 1 Dirty"] +pub struct DCCD1_R(crate::FieldReader); +impl DCCD1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DCCD1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DCCD1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HPE` reader - Hot-Plugging Enable"] +pub struct HPE_R(crate::FieldReader); +impl HPE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HPE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HPE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Protected"] + #[inline(always)] + pub fn prot(&self) -> PROT_R { + PROT_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Debugger Present"] + #[inline(always)] + pub fn dbgpres(&self) -> DBGPRES_R { + DBGPRES_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Debug Communication Channel 0 Dirty"] + #[inline(always)] + pub fn dccd0(&self) -> DCCD0_R { + DCCD0_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Debug Communication Channel 1 Dirty"] + #[inline(always)] + pub fn dccd1(&self) -> DCCD1_R { + DCCD1_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Hot-Plugging Enable"] + #[inline(always)] + pub fn hpe(&self) -> HPE_R { + HPE_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +#[doc = "Status B\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [statusb](index.html) module"] +pub struct STATUSB_SPEC; +impl crate::RegisterSpec for STATUSB_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [statusb::R](R) reader structure"] +impl crate::Readable for STATUSB_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUSB to value 0"] +impl crate::Resettable for STATUSB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/eic.rs b/pac/atsamc21n/src/eic.rs new file mode 100644 index 000000000000..08d0a8f18bbf --- /dev/null +++ b/pac/atsamc21n/src/eic.rs @@ -0,0 +1,83 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + #[doc = "0x01 - Non-Maskable Interrupt Control"] + pub nmictrl: crate::Reg, + #[doc = "0x02 - Non-Maskable Interrupt Flag Status and Clear"] + pub nmiflag: crate::Reg, + #[doc = "0x04 - Synchronization Busy"] + pub syncbusy: crate::Reg, + #[doc = "0x08 - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x0c - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x10 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x14 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x18 - External Interrupt Asynchronous Mode"] + pub asynch: crate::Reg, + #[doc = "0x1c..0x24 - External Interrupt Sense Configuration"] + pub config: [crate::Reg; 2], + _reserved10: [u8; 0x0c], + #[doc = "0x30 - Debouncer Enable"] + pub debouncen: crate::Reg, + #[doc = "0x34 - Debouncer Prescaler"] + pub dprescaler: crate::Reg, + #[doc = "0x38 - Pin State"] + pub pinstate: crate::Reg, +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "NMICTRL register accessor: an alias for `Reg`"] +pub type NMICTRL = crate::Reg; +#[doc = "Non-Maskable Interrupt Control"] +pub mod nmictrl; +#[doc = "NMIFLAG register accessor: an alias for `Reg`"] +pub type NMIFLAG = crate::Reg; +#[doc = "Non-Maskable Interrupt Flag Status and Clear"] +pub mod nmiflag; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Busy"] +pub mod syncbusy; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "ASYNCH register accessor: an alias for `Reg`"] +pub type ASYNCH = crate::Reg; +#[doc = "External Interrupt Asynchronous Mode"] +pub mod asynch; +#[doc = "CONFIG register accessor: an alias for `Reg`"] +pub type CONFIG = crate::Reg; +#[doc = "External Interrupt Sense Configuration"] +pub mod config; +#[doc = "DEBOUNCEN register accessor: an alias for `Reg`"] +pub type DEBOUNCEN = crate::Reg; +#[doc = "Debouncer Enable"] +pub mod debouncen; +#[doc = "DPRESCALER register accessor: an alias for `Reg`"] +pub type DPRESCALER = crate::Reg; +#[doc = "Debouncer Prescaler"] +pub mod dprescaler; +#[doc = "PINSTATE register accessor: an alias for `Reg`"] +pub type PINSTATE = crate::Reg; +#[doc = "Pin State"] +pub mod pinstate; diff --git a/pac/atsamc21n/src/eic/asynch.rs b/pac/atsamc21n/src/eic/asynch.rs new file mode 100644 index 000000000000..e8c893400684 --- /dev/null +++ b/pac/atsamc21n/src/eic/asynch.rs @@ -0,0 +1,152 @@ +#[doc = "Register `ASYNCH` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ASYNCH` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Asynchronous Edge Detection Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u16)] +pub enum ASYNCH_A { + #[doc = "0: Edge detection is clock synchronously operated"] + SYNC = 0, + #[doc = "1: Edge detection is clock asynchronously operated"] + ASYNC = 1, +} +impl From for u16 { + #[inline(always)] + fn from(variant: ASYNCH_A) -> Self { + variant as _ + } +} +#[doc = "Field `ASYNCH` reader - Asynchronous Edge Detection Mode"] +pub struct ASYNCH_R(crate::FieldReader); +impl ASYNCH_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + ASYNCH_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(ASYNCH_A::SYNC), + 1 => Some(ASYNCH_A::ASYNC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `SYNC`"] + #[inline(always)] + pub fn is_sync(&self) -> bool { + **self == ASYNCH_A::SYNC + } + #[doc = "Checks if the value of the field is `ASYNC`"] + #[inline(always)] + pub fn is_async(&self) -> bool { + **self == ASYNCH_A::ASYNC + } +} +impl core::ops::Deref for ASYNCH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ASYNCH` writer - Asynchronous Edge Detection Mode"] +pub struct ASYNCH_W<'a> { + w: &'a mut W, +} +impl<'a> ASYNCH_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: ASYNCH_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Edge detection is clock synchronously operated"] + #[inline(always)] + pub fn sync(self) -> &'a mut W { + self.variant(ASYNCH_A::SYNC) + } + #[doc = "Edge detection is clock asynchronously operated"] + #[inline(always)] + pub fn async_(self) -> &'a mut W { + self.variant(ASYNCH_A::ASYNC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Asynchronous Edge Detection Mode"] + #[inline(always)] + pub fn asynch(&self) -> ASYNCH_R { + ASYNCH_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Asynchronous Edge Detection Mode"] + #[inline(always)] + pub fn asynch(&mut self) -> ASYNCH_W { + ASYNCH_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "External Interrupt Asynchronous Mode\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [asynch](index.html) module"] +pub struct ASYNCH_SPEC; +impl crate::RegisterSpec for ASYNCH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [asynch::R](R) reader structure"] +impl crate::Readable for ASYNCH_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [asynch::W](W) writer structure"] +impl crate::Writable for ASYNCH_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ASYNCH to value 0"] +impl crate::Resettable for ASYNCH_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/eic/config.rs b/pac/atsamc21n/src/eic/config.rs new file mode 100644 index 000000000000..2235889ac17f --- /dev/null +++ b/pac/atsamc21n/src/eic/config.rs @@ -0,0 +1,1547 @@ +#[doc = "Register `CONFIG[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CONFIG[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Input Sense Configuration 0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE0_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE0_A) -> Self { + variant as _ + } +} +#[doc = "Field `SENSE0` reader - Input Sense Configuration 0"] +pub struct SENSE0_R(crate::FieldReader); +impl SENSE0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SENSE0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE0_A::NONE), + 1 => Some(SENSE0_A::RISE), + 2 => Some(SENSE0_A::FALL), + 3 => Some(SENSE0_A::BOTH), + 4 => Some(SENSE0_A::HIGH), + 5 => Some(SENSE0_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == SENSE0_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == SENSE0_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == SENSE0_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == SENSE0_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SENSE0_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SENSE0_A::LOW + } +} +impl core::ops::Deref for SENSE0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SENSE0` writer - Input Sense Configuration 0"] +pub struct SENSE0_W<'a> { + w: &'a mut W, +} +impl<'a> SENSE0_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SENSE0_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE0_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE0_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE0_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE0_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE0_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE0_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Field `FILTEN0` reader - Filter Enable 0"] +pub struct FILTEN0_R(crate::FieldReader); +impl FILTEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FILTEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTEN0` writer - Filter Enable 0"] +pub struct FILTEN0_W<'a> { + w: &'a mut W, +} +impl<'a> FILTEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Input Sense Configuration 1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE1_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE1_A) -> Self { + variant as _ + } +} +#[doc = "Field `SENSE1` reader - Input Sense Configuration 1"] +pub struct SENSE1_R(crate::FieldReader); +impl SENSE1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SENSE1_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE1_A::NONE), + 1 => Some(SENSE1_A::RISE), + 2 => Some(SENSE1_A::FALL), + 3 => Some(SENSE1_A::BOTH), + 4 => Some(SENSE1_A::HIGH), + 5 => Some(SENSE1_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == SENSE1_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == SENSE1_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == SENSE1_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == SENSE1_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SENSE1_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SENSE1_A::LOW + } +} +impl core::ops::Deref for SENSE1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SENSE1` writer - Input Sense Configuration 1"] +pub struct SENSE1_W<'a> { + w: &'a mut W, +} +impl<'a> SENSE1_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SENSE1_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE1_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE1_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE1_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE1_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE1_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE1_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 4)) | ((value as u32 & 0x07) << 4); + self.w + } +} +#[doc = "Field `FILTEN1` reader - Filter Enable 1"] +pub struct FILTEN1_R(crate::FieldReader); +impl FILTEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FILTEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTEN1` writer - Filter Enable 1"] +pub struct FILTEN1_W<'a> { + w: &'a mut W, +} +impl<'a> FILTEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Input Sense Configuration 2\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE2_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE2_A) -> Self { + variant as _ + } +} +#[doc = "Field `SENSE2` reader - Input Sense Configuration 2"] +pub struct SENSE2_R(crate::FieldReader); +impl SENSE2_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SENSE2_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE2_A::NONE), + 1 => Some(SENSE2_A::RISE), + 2 => Some(SENSE2_A::FALL), + 3 => Some(SENSE2_A::BOTH), + 4 => Some(SENSE2_A::HIGH), + 5 => Some(SENSE2_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == SENSE2_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == SENSE2_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == SENSE2_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == SENSE2_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SENSE2_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SENSE2_A::LOW + } +} +impl core::ops::Deref for SENSE2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SENSE2` writer - Input Sense Configuration 2"] +pub struct SENSE2_W<'a> { + w: &'a mut W, +} +impl<'a> SENSE2_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SENSE2_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE2_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE2_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE2_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE2_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE2_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE2_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +#[doc = "Field `FILTEN2` reader - Filter Enable 2"] +pub struct FILTEN2_R(crate::FieldReader); +impl FILTEN2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FILTEN2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTEN2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTEN2` writer - Filter Enable 2"] +pub struct FILTEN2_W<'a> { + w: &'a mut W, +} +impl<'a> FILTEN2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Input Sense Configuration 3\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE3_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE3_A) -> Self { + variant as _ + } +} +#[doc = "Field `SENSE3` reader - Input Sense Configuration 3"] +pub struct SENSE3_R(crate::FieldReader); +impl SENSE3_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SENSE3_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE3_A::NONE), + 1 => Some(SENSE3_A::RISE), + 2 => Some(SENSE3_A::FALL), + 3 => Some(SENSE3_A::BOTH), + 4 => Some(SENSE3_A::HIGH), + 5 => Some(SENSE3_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == SENSE3_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == SENSE3_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == SENSE3_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == SENSE3_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SENSE3_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SENSE3_A::LOW + } +} +impl core::ops::Deref for SENSE3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SENSE3` writer - Input Sense Configuration 3"] +pub struct SENSE3_W<'a> { + w: &'a mut W, +} +impl<'a> SENSE3_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SENSE3_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE3_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE3_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE3_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE3_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE3_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE3_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 12)) | ((value as u32 & 0x07) << 12); + self.w + } +} +#[doc = "Field `FILTEN3` reader - Filter Enable 3"] +pub struct FILTEN3_R(crate::FieldReader); +impl FILTEN3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FILTEN3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTEN3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTEN3` writer - Filter Enable 3"] +pub struct FILTEN3_W<'a> { + w: &'a mut W, +} +impl<'a> FILTEN3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Input Sense Configuration 4\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE4_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE4_A) -> Self { + variant as _ + } +} +#[doc = "Field `SENSE4` reader - Input Sense Configuration 4"] +pub struct SENSE4_R(crate::FieldReader); +impl SENSE4_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SENSE4_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE4_A::NONE), + 1 => Some(SENSE4_A::RISE), + 2 => Some(SENSE4_A::FALL), + 3 => Some(SENSE4_A::BOTH), + 4 => Some(SENSE4_A::HIGH), + 5 => Some(SENSE4_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == SENSE4_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == SENSE4_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == SENSE4_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == SENSE4_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SENSE4_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SENSE4_A::LOW + } +} +impl core::ops::Deref for SENSE4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SENSE4` writer - Input Sense Configuration 4"] +pub struct SENSE4_W<'a> { + w: &'a mut W, +} +impl<'a> SENSE4_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SENSE4_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE4_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE4_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE4_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE4_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE4_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE4_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 16)) | ((value as u32 & 0x07) << 16); + self.w + } +} +#[doc = "Field `FILTEN4` reader - Filter Enable 4"] +pub struct FILTEN4_R(crate::FieldReader); +impl FILTEN4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FILTEN4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTEN4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTEN4` writer - Filter Enable 4"] +pub struct FILTEN4_W<'a> { + w: &'a mut W, +} +impl<'a> FILTEN4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Input Sense Configuration 5\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE5_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE5_A) -> Self { + variant as _ + } +} +#[doc = "Field `SENSE5` reader - Input Sense Configuration 5"] +pub struct SENSE5_R(crate::FieldReader); +impl SENSE5_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SENSE5_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE5_A::NONE), + 1 => Some(SENSE5_A::RISE), + 2 => Some(SENSE5_A::FALL), + 3 => Some(SENSE5_A::BOTH), + 4 => Some(SENSE5_A::HIGH), + 5 => Some(SENSE5_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == SENSE5_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == SENSE5_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == SENSE5_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == SENSE5_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SENSE5_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SENSE5_A::LOW + } +} +impl core::ops::Deref for SENSE5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SENSE5` writer - Input Sense Configuration 5"] +pub struct SENSE5_W<'a> { + w: &'a mut W, +} +impl<'a> SENSE5_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SENSE5_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE5_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE5_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE5_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE5_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE5_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE5_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 20)) | ((value as u32 & 0x07) << 20); + self.w + } +} +#[doc = "Field `FILTEN5` reader - Filter Enable 5"] +pub struct FILTEN5_R(crate::FieldReader); +impl FILTEN5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FILTEN5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTEN5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTEN5` writer - Filter Enable 5"] +pub struct FILTEN5_W<'a> { + w: &'a mut W, +} +impl<'a> FILTEN5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Input Sense Configuration 6\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE6_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE6_A) -> Self { + variant as _ + } +} +#[doc = "Field `SENSE6` reader - Input Sense Configuration 6"] +pub struct SENSE6_R(crate::FieldReader); +impl SENSE6_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SENSE6_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE6_A::NONE), + 1 => Some(SENSE6_A::RISE), + 2 => Some(SENSE6_A::FALL), + 3 => Some(SENSE6_A::BOTH), + 4 => Some(SENSE6_A::HIGH), + 5 => Some(SENSE6_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == SENSE6_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == SENSE6_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == SENSE6_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == SENSE6_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SENSE6_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SENSE6_A::LOW + } +} +impl core::ops::Deref for SENSE6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SENSE6` writer - Input Sense Configuration 6"] +pub struct SENSE6_W<'a> { + w: &'a mut W, +} +impl<'a> SENSE6_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SENSE6_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE6_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE6_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE6_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE6_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE6_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE6_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 24)) | ((value as u32 & 0x07) << 24); + self.w + } +} +#[doc = "Field `FILTEN6` reader - Filter Enable 6"] +pub struct FILTEN6_R(crate::FieldReader); +impl FILTEN6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FILTEN6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTEN6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTEN6` writer - Filter Enable 6"] +pub struct FILTEN6_W<'a> { + w: &'a mut W, +} +impl<'a> FILTEN6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +#[doc = "Input Sense Configuration 7\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SENSE7_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE7_A) -> Self { + variant as _ + } +} +#[doc = "Field `SENSE7` reader - Input Sense Configuration 7"] +pub struct SENSE7_R(crate::FieldReader); +impl SENSE7_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SENSE7_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE7_A::NONE), + 1 => Some(SENSE7_A::RISE), + 2 => Some(SENSE7_A::FALL), + 3 => Some(SENSE7_A::BOTH), + 4 => Some(SENSE7_A::HIGH), + 5 => Some(SENSE7_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == SENSE7_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == SENSE7_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == SENSE7_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == SENSE7_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == SENSE7_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == SENSE7_A::LOW + } +} +impl core::ops::Deref for SENSE7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SENSE7` writer - Input Sense Configuration 7"] +pub struct SENSE7_W<'a> { + w: &'a mut W, +} +impl<'a> SENSE7_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SENSE7_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE7_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE7_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE7_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE7_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE7_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE7_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 28)) | ((value as u32 & 0x07) << 28); + self.w + } +} +#[doc = "Field `FILTEN7` reader - Filter Enable 7"] +pub struct FILTEN7_R(crate::FieldReader); +impl FILTEN7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FILTEN7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTEN7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTEN7` writer - Filter Enable 7"] +pub struct FILTEN7_W<'a> { + w: &'a mut W, +} +impl<'a> FILTEN7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Input Sense Configuration 0"] + #[inline(always)] + pub fn sense0(&self) -> SENSE0_R { + SENSE0_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 3 - Filter Enable 0"] + #[inline(always)] + pub fn filten0(&self) -> FILTEN0_R { + FILTEN0_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bits 4:6 - Input Sense Configuration 1"] + #[inline(always)] + pub fn sense1(&self) -> SENSE1_R { + SENSE1_R::new(((self.bits >> 4) & 0x07) as u8) + } + #[doc = "Bit 7 - Filter Enable 1"] + #[inline(always)] + pub fn filten1(&self) -> FILTEN1_R { + FILTEN1_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Input Sense Configuration 2"] + #[inline(always)] + pub fn sense2(&self) -> SENSE2_R { + SENSE2_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 11 - Filter Enable 2"] + #[inline(always)] + pub fn filten2(&self) -> FILTEN2_R { + FILTEN2_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bits 12:14 - Input Sense Configuration 3"] + #[inline(always)] + pub fn sense3(&self) -> SENSE3_R { + SENSE3_R::new(((self.bits >> 12) & 0x07) as u8) + } + #[doc = "Bit 15 - Filter Enable 3"] + #[inline(always)] + pub fn filten3(&self) -> FILTEN3_R { + FILTEN3_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:18 - Input Sense Configuration 4"] + #[inline(always)] + pub fn sense4(&self) -> SENSE4_R { + SENSE4_R::new(((self.bits >> 16) & 0x07) as u8) + } + #[doc = "Bit 19 - Filter Enable 4"] + #[inline(always)] + pub fn filten4(&self) -> FILTEN4_R { + FILTEN4_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bits 20:22 - Input Sense Configuration 5"] + #[inline(always)] + pub fn sense5(&self) -> SENSE5_R { + SENSE5_R::new(((self.bits >> 20) & 0x07) as u8) + } + #[doc = "Bit 23 - Filter Enable 5"] + #[inline(always)] + pub fn filten5(&self) -> FILTEN5_R { + FILTEN5_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bits 24:26 - Input Sense Configuration 6"] + #[inline(always)] + pub fn sense6(&self) -> SENSE6_R { + SENSE6_R::new(((self.bits >> 24) & 0x07) as u8) + } + #[doc = "Bit 27 - Filter Enable 6"] + #[inline(always)] + pub fn filten6(&self) -> FILTEN6_R { + FILTEN6_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bits 28:30 - Input Sense Configuration 7"] + #[inline(always)] + pub fn sense7(&self) -> SENSE7_R { + SENSE7_R::new(((self.bits >> 28) & 0x07) as u8) + } + #[doc = "Bit 31 - Filter Enable 7"] + #[inline(always)] + pub fn filten7(&self) -> FILTEN7_R { + FILTEN7_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Input Sense Configuration 0"] + #[inline(always)] + pub fn sense0(&mut self) -> SENSE0_W { + SENSE0_W { w: self } + } + #[doc = "Bit 3 - Filter Enable 0"] + #[inline(always)] + pub fn filten0(&mut self) -> FILTEN0_W { + FILTEN0_W { w: self } + } + #[doc = "Bits 4:6 - Input Sense Configuration 1"] + #[inline(always)] + pub fn sense1(&mut self) -> SENSE1_W { + SENSE1_W { w: self } + } + #[doc = "Bit 7 - Filter Enable 1"] + #[inline(always)] + pub fn filten1(&mut self) -> FILTEN1_W { + FILTEN1_W { w: self } + } + #[doc = "Bits 8:10 - Input Sense Configuration 2"] + #[inline(always)] + pub fn sense2(&mut self) -> SENSE2_W { + SENSE2_W { w: self } + } + #[doc = "Bit 11 - Filter Enable 2"] + #[inline(always)] + pub fn filten2(&mut self) -> FILTEN2_W { + FILTEN2_W { w: self } + } + #[doc = "Bits 12:14 - Input Sense Configuration 3"] + #[inline(always)] + pub fn sense3(&mut self) -> SENSE3_W { + SENSE3_W { w: self } + } + #[doc = "Bit 15 - Filter Enable 3"] + #[inline(always)] + pub fn filten3(&mut self) -> FILTEN3_W { + FILTEN3_W { w: self } + } + #[doc = "Bits 16:18 - Input Sense Configuration 4"] + #[inline(always)] + pub fn sense4(&mut self) -> SENSE4_W { + SENSE4_W { w: self } + } + #[doc = "Bit 19 - Filter Enable 4"] + #[inline(always)] + pub fn filten4(&mut self) -> FILTEN4_W { + FILTEN4_W { w: self } + } + #[doc = "Bits 20:22 - Input Sense Configuration 5"] + #[inline(always)] + pub fn sense5(&mut self) -> SENSE5_W { + SENSE5_W { w: self } + } + #[doc = "Bit 23 - Filter Enable 5"] + #[inline(always)] + pub fn filten5(&mut self) -> FILTEN5_W { + FILTEN5_W { w: self } + } + #[doc = "Bits 24:26 - Input Sense Configuration 6"] + #[inline(always)] + pub fn sense6(&mut self) -> SENSE6_W { + SENSE6_W { w: self } + } + #[doc = "Bit 27 - Filter Enable 6"] + #[inline(always)] + pub fn filten6(&mut self) -> FILTEN6_W { + FILTEN6_W { w: self } + } + #[doc = "Bits 28:30 - Input Sense Configuration 7"] + #[inline(always)] + pub fn sense7(&mut self) -> SENSE7_W { + SENSE7_W { w: self } + } + #[doc = "Bit 31 - Filter Enable 7"] + #[inline(always)] + pub fn filten7(&mut self) -> FILTEN7_W { + FILTEN7_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "External Interrupt Sense Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [config](index.html) module"] +pub struct CONFIG_SPEC; +impl crate::RegisterSpec for CONFIG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [config::R](R) reader structure"] +impl crate::Readable for CONFIG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [config::W](W) writer structure"] +impl crate::Writable for CONFIG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CONFIG[%s] +to value 0"] +impl crate::Resettable for CONFIG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/eic/ctrla.rs b/pac/atsamc21n/src/eic/ctrla.rs new file mode 100644 index 000000000000..4e119fc05c61 --- /dev/null +++ b/pac/atsamc21n/src/eic/ctrla.rs @@ -0,0 +1,254 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Clock Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CKSEL_A { + #[doc = "0: Clocked by GCLK"] + CLK_GCLK = 0, + #[doc = "1: Clocked by ULP32K"] + CLK_ULP32K = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CKSEL_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CKSEL` reader - Clock Selection"] +pub struct CKSEL_R(crate::FieldReader); +impl CKSEL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CKSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CKSEL_A { + match self.bits { + false => CKSEL_A::CLK_GCLK, + true => CKSEL_A::CLK_ULP32K, + } + } + #[doc = "Checks if the value of the field is `CLK_GCLK`"] + #[inline(always)] + pub fn is_clk_gclk(&self) -> bool { + **self == CKSEL_A::CLK_GCLK + } + #[doc = "Checks if the value of the field is `CLK_ULP32K`"] + #[inline(always)] + pub fn is_clk_ulp32k(&self) -> bool { + **self == CKSEL_A::CLK_ULP32K + } +} +impl core::ops::Deref for CKSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CKSEL` writer - Clock Selection"] +pub struct CKSEL_W<'a> { + w: &'a mut W, +} +impl<'a> CKSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CKSEL_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Clocked by GCLK"] + #[inline(always)] + pub fn clk_gclk(self) -> &'a mut W { + self.variant(CKSEL_A::CLK_GCLK) + } + #[doc = "Clocked by ULP32K"] + #[inline(always)] + pub fn clk_ulp32k(self) -> &'a mut W { + self.variant(CKSEL_A::CLK_ULP32K) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - Clock Selection"] + #[inline(always)] + pub fn cksel(&self) -> CKSEL_R { + CKSEL_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 4 - Clock Selection"] + #[inline(always)] + pub fn cksel(&mut self) -> CKSEL_W { + CKSEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/eic/debouncen.rs b/pac/atsamc21n/src/eic/debouncen.rs new file mode 100644 index 000000000000..4861c11a8f28 --- /dev/null +++ b/pac/atsamc21n/src/eic/debouncen.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DEBOUNCEN` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DEBOUNCEN` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DEBOUNCEN` reader - Debouncer Enable"] +pub struct DEBOUNCEN_R(crate::FieldReader); +impl DEBOUNCEN_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + DEBOUNCEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DEBOUNCEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DEBOUNCEN` writer - Debouncer Enable"] +pub struct DEBOUNCEN_W<'a> { + w: &'a mut W, +} +impl<'a> DEBOUNCEN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Debouncer Enable"] + #[inline(always)] + pub fn debouncen(&self) -> DEBOUNCEN_R { + DEBOUNCEN_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Debouncer Enable"] + #[inline(always)] + pub fn debouncen(&mut self) -> DEBOUNCEN_W { + DEBOUNCEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debouncer Enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [debouncen](index.html) module"] +pub struct DEBOUNCEN_SPEC; +impl crate::RegisterSpec for DEBOUNCEN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [debouncen::R](R) reader structure"] +impl crate::Readable for DEBOUNCEN_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [debouncen::W](W) writer structure"] +impl crate::Writable for DEBOUNCEN_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DEBOUNCEN to value 0"] +impl crate::Resettable for DEBOUNCEN_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/eic/dprescaler.rs b/pac/atsamc21n/src/eic/dprescaler.rs new file mode 100644 index 000000000000..9a0c93b3e3e5 --- /dev/null +++ b/pac/atsamc21n/src/eic/dprescaler.rs @@ -0,0 +1,676 @@ +#[doc = "Register `DPRESCALER` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DPRESCALER` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Debouncer Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER0_A { + #[doc = "0: EIC clock divided by 2"] + DIV2 = 0, + #[doc = "1: EIC clock divided by 4"] + DIV4 = 1, + #[doc = "2: EIC clock divided by 8"] + DIV8 = 2, + #[doc = "3: EIC clock divided by 16"] + DIV16 = 3, + #[doc = "4: EIC clock divided by 32"] + DIV32 = 4, + #[doc = "5: EIC clock divided by 64"] + DIV64 = 5, + #[doc = "6: EIC clock divided by 128"] + DIV128 = 6, + #[doc = "7: EIC clock divided by 256"] + DIV256 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER0_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER0` reader - Debouncer Prescaler"] +pub struct PRESCALER0_R(crate::FieldReader); +impl PRESCALER0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PRESCALER0_A { + match self.bits { + 0 => PRESCALER0_A::DIV2, + 1 => PRESCALER0_A::DIV4, + 2 => PRESCALER0_A::DIV8, + 3 => PRESCALER0_A::DIV16, + 4 => PRESCALER0_A::DIV32, + 5 => PRESCALER0_A::DIV64, + 6 => PRESCALER0_A::DIV128, + 7 => PRESCALER0_A::DIV256, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER0_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER0_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER0_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER0_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == PRESCALER0_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER0_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == PRESCALER0_A::DIV128 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER0_A::DIV256 + } +} +impl core::ops::Deref for PRESCALER0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER0` writer - Debouncer Prescaler"] +pub struct PRESCALER0_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER0_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER0_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "EIC clock divided by 2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER0_A::DIV2) + } + #[doc = "EIC clock divided by 4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER0_A::DIV4) + } + #[doc = "EIC clock divided by 8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER0_A::DIV8) + } + #[doc = "EIC clock divided by 16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER0_A::DIV16) + } + #[doc = "EIC clock divided by 32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(PRESCALER0_A::DIV32) + } + #[doc = "EIC clock divided by 64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER0_A::DIV64) + } + #[doc = "EIC clock divided by 128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(PRESCALER0_A::DIV128) + } + #[doc = "EIC clock divided by 256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER0_A::DIV256) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Debouncer number of states\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum STATES0_A { + #[doc = "0: 3 low frequency samples"] + LFREQ3 = 0, + #[doc = "1: 7 low frequency samples"] + LFREQ7 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: STATES0_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STATES0` reader - Debouncer number of states"] +pub struct STATES0_R(crate::FieldReader); +impl STATES0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STATES0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STATES0_A { + match self.bits { + false => STATES0_A::LFREQ3, + true => STATES0_A::LFREQ7, + } + } + #[doc = "Checks if the value of the field is `LFREQ3`"] + #[inline(always)] + pub fn is_lfreq3(&self) -> bool { + **self == STATES0_A::LFREQ3 + } + #[doc = "Checks if the value of the field is `LFREQ7`"] + #[inline(always)] + pub fn is_lfreq7(&self) -> bool { + **self == STATES0_A::LFREQ7 + } +} +impl core::ops::Deref for STATES0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STATES0` writer - Debouncer number of states"] +pub struct STATES0_W<'a> { + w: &'a mut W, +} +impl<'a> STATES0_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: STATES0_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "3 low frequency samples"] + #[inline(always)] + pub fn lfreq3(self) -> &'a mut W { + self.variant(STATES0_A::LFREQ3) + } + #[doc = "7 low frequency samples"] + #[inline(always)] + pub fn lfreq7(self) -> &'a mut W { + self.variant(STATES0_A::LFREQ7) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Debouncer Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER1_A { + #[doc = "0: EIC clock divided by 2"] + DIV2 = 0, + #[doc = "1: EIC clock divided by 4"] + DIV4 = 1, + #[doc = "2: EIC clock divided by 8"] + DIV8 = 2, + #[doc = "3: EIC clock divided by 16"] + DIV16 = 3, + #[doc = "4: EIC clock divided by 32"] + DIV32 = 4, + #[doc = "5: EIC clock divided by 64"] + DIV64 = 5, + #[doc = "6: EIC clock divided by 128"] + DIV128 = 6, + #[doc = "7: EIC clock divided by 256"] + DIV256 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER1_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER1` reader - Debouncer Prescaler"] +pub struct PRESCALER1_R(crate::FieldReader); +impl PRESCALER1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER1_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PRESCALER1_A { + match self.bits { + 0 => PRESCALER1_A::DIV2, + 1 => PRESCALER1_A::DIV4, + 2 => PRESCALER1_A::DIV8, + 3 => PRESCALER1_A::DIV16, + 4 => PRESCALER1_A::DIV32, + 5 => PRESCALER1_A::DIV64, + 6 => PRESCALER1_A::DIV128, + 7 => PRESCALER1_A::DIV256, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER1_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER1_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER1_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER1_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == PRESCALER1_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER1_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == PRESCALER1_A::DIV128 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER1_A::DIV256 + } +} +impl core::ops::Deref for PRESCALER1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER1` writer - Debouncer Prescaler"] +pub struct PRESCALER1_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER1_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER1_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "EIC clock divided by 2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER1_A::DIV2) + } + #[doc = "EIC clock divided by 4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER1_A::DIV4) + } + #[doc = "EIC clock divided by 8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER1_A::DIV8) + } + #[doc = "EIC clock divided by 16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER1_A::DIV16) + } + #[doc = "EIC clock divided by 32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(PRESCALER1_A::DIV32) + } + #[doc = "EIC clock divided by 64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER1_A::DIV64) + } + #[doc = "EIC clock divided by 128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(PRESCALER1_A::DIV128) + } + #[doc = "EIC clock divided by 256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER1_A::DIV256) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 4)) | ((value as u32 & 0x07) << 4); + self.w + } +} +#[doc = "Debouncer number of states\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum STATES1_A { + #[doc = "0: 3 low frequency samples"] + LFREQ3 = 0, + #[doc = "1: 7 low frequency samples"] + LFREQ7 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: STATES1_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STATES1` reader - Debouncer number of states"] +pub struct STATES1_R(crate::FieldReader); +impl STATES1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STATES1_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STATES1_A { + match self.bits { + false => STATES1_A::LFREQ3, + true => STATES1_A::LFREQ7, + } + } + #[doc = "Checks if the value of the field is `LFREQ3`"] + #[inline(always)] + pub fn is_lfreq3(&self) -> bool { + **self == STATES1_A::LFREQ3 + } + #[doc = "Checks if the value of the field is `LFREQ7`"] + #[inline(always)] + pub fn is_lfreq7(&self) -> bool { + **self == STATES1_A::LFREQ7 + } +} +impl core::ops::Deref for STATES1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STATES1` writer - Debouncer number of states"] +pub struct STATES1_W<'a> { + w: &'a mut W, +} +impl<'a> STATES1_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: STATES1_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "3 low frequency samples"] + #[inline(always)] + pub fn lfreq3(self) -> &'a mut W { + self.variant(STATES1_A::LFREQ3) + } + #[doc = "7 low frequency samples"] + #[inline(always)] + pub fn lfreq7(self) -> &'a mut W { + self.variant(STATES1_A::LFREQ7) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Pin Sampler frequency selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TICKON_A { + #[doc = "0: Clocked by GCLK"] + CLK_GCLK_EIC = 0, + #[doc = "1: Clocked by Low Frequency Clock"] + CLK_LFREQ = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TICKON_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TICKON` reader - Pin Sampler frequency selection"] +pub struct TICKON_R(crate::FieldReader); +impl TICKON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TICKON_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TICKON_A { + match self.bits { + false => TICKON_A::CLK_GCLK_EIC, + true => TICKON_A::CLK_LFREQ, + } + } + #[doc = "Checks if the value of the field is `CLK_GCLK_EIC`"] + #[inline(always)] + pub fn is_clk_gclk_eic(&self) -> bool { + **self == TICKON_A::CLK_GCLK_EIC + } + #[doc = "Checks if the value of the field is `CLK_LFREQ`"] + #[inline(always)] + pub fn is_clk_lfreq(&self) -> bool { + **self == TICKON_A::CLK_LFREQ + } +} +impl core::ops::Deref for TICKON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TICKON` writer - Pin Sampler frequency selection"] +pub struct TICKON_W<'a> { + w: &'a mut W, +} +impl<'a> TICKON_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TICKON_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Clocked by GCLK"] + #[inline(always)] + pub fn clk_gclk_eic(self) -> &'a mut W { + self.variant(TICKON_A::CLK_GCLK_EIC) + } + #[doc = "Clocked by Low Frequency Clock"] + #[inline(always)] + pub fn clk_lfreq(self) -> &'a mut W { + self.variant(TICKON_A::CLK_LFREQ) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Debouncer Prescaler"] + #[inline(always)] + pub fn prescaler0(&self) -> PRESCALER0_R { + PRESCALER0_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 3 - Debouncer number of states"] + #[inline(always)] + pub fn states0(&self) -> STATES0_R { + STATES0_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bits 4:6 - Debouncer Prescaler"] + #[inline(always)] + pub fn prescaler1(&self) -> PRESCALER1_R { + PRESCALER1_R::new(((self.bits >> 4) & 0x07) as u8) + } + #[doc = "Bit 7 - Debouncer number of states"] + #[inline(always)] + pub fn states1(&self) -> STATES1_R { + STATES1_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 16 - Pin Sampler frequency selection"] + #[inline(always)] + pub fn tickon(&self) -> TICKON_R { + TICKON_R::new(((self.bits >> 16) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Debouncer Prescaler"] + #[inline(always)] + pub fn prescaler0(&mut self) -> PRESCALER0_W { + PRESCALER0_W { w: self } + } + #[doc = "Bit 3 - Debouncer number of states"] + #[inline(always)] + pub fn states0(&mut self) -> STATES0_W { + STATES0_W { w: self } + } + #[doc = "Bits 4:6 - Debouncer Prescaler"] + #[inline(always)] + pub fn prescaler1(&mut self) -> PRESCALER1_W { + PRESCALER1_W { w: self } + } + #[doc = "Bit 7 - Debouncer number of states"] + #[inline(always)] + pub fn states1(&mut self) -> STATES1_W { + STATES1_W { w: self } + } + #[doc = "Bit 16 - Pin Sampler frequency selection"] + #[inline(always)] + pub fn tickon(&mut self) -> TICKON_W { + TICKON_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debouncer Prescaler\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dprescaler](index.html) module"] +pub struct DPRESCALER_SPEC; +impl crate::RegisterSpec for DPRESCALER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dprescaler::R](R) reader structure"] +impl crate::Readable for DPRESCALER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dprescaler::W](W) writer structure"] +impl crate::Writable for DPRESCALER_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DPRESCALER to value 0"] +impl crate::Resettable for DPRESCALER_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/eic/evctrl.rs b/pac/atsamc21n/src/eic/evctrl.rs new file mode 100644 index 000000000000..25adccf3558e --- /dev/null +++ b/pac/atsamc21n/src/eic/evctrl.rs @@ -0,0 +1,103 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EXTINTEO` reader - External Interrupt Event Output Enable"] +pub struct EXTINTEO_R(crate::FieldReader); +impl EXTINTEO_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + EXTINTEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINTEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINTEO` writer - External Interrupt Event Output Enable"] +pub struct EXTINTEO_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINTEO_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - External Interrupt Event Output Enable"] + #[inline(always)] + pub fn extinteo(&self) -> EXTINTEO_R { + EXTINTEO_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - External Interrupt Event Output Enable"] + #[inline(always)] + pub fn extinteo(&mut self) -> EXTINTEO_W { + EXTINTEO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/eic/intenclr.rs b/pac/atsamc21n/src/eic/intenclr.rs new file mode 100644 index 000000000000..3d2675e0dfb8 --- /dev/null +++ b/pac/atsamc21n/src/eic/intenclr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EXTINT` reader - External Interrupt Enable"] +pub struct EXTINT_R(crate::FieldReader); +impl EXTINT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + EXTINT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT` writer - External Interrupt Enable"] +pub struct EXTINT_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - External Interrupt Enable"] + #[inline(always)] + pub fn extint(&self) -> EXTINT_R { + EXTINT_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - External Interrupt Enable"] + #[inline(always)] + pub fn extint(&mut self) -> EXTINT_W { + EXTINT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/eic/intenset.rs b/pac/atsamc21n/src/eic/intenset.rs new file mode 100644 index 000000000000..e2ff6729d71f --- /dev/null +++ b/pac/atsamc21n/src/eic/intenset.rs @@ -0,0 +1,103 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EXTINT` reader - External Interrupt Enable"] +pub struct EXTINT_R(crate::FieldReader); +impl EXTINT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + EXTINT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT` writer - External Interrupt Enable"] +pub struct EXTINT_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - External Interrupt Enable"] + #[inline(always)] + pub fn extint(&self) -> EXTINT_R { + EXTINT_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - External Interrupt Enable"] + #[inline(always)] + pub fn extint(&mut self) -> EXTINT_W { + EXTINT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/eic/intflag.rs b/pac/atsamc21n/src/eic/intflag.rs new file mode 100644 index 000000000000..c4a3ff581110 --- /dev/null +++ b/pac/atsamc21n/src/eic/intflag.rs @@ -0,0 +1,103 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EXTINT` reader - External Interrupt"] +pub struct EXTINT_R(crate::FieldReader); +impl EXTINT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + EXTINT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTINT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTINT` writer - External Interrupt"] +pub struct EXTINT_W<'a> { + w: &'a mut W, +} +impl<'a> EXTINT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - External Interrupt"] + #[inline(always)] + pub fn extint(&self) -> EXTINT_R { + EXTINT_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - External Interrupt"] + #[inline(always)] + pub fn extint(&mut self) -> EXTINT_W { + EXTINT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/eic/nmictrl.rs b/pac/atsamc21n/src/eic/nmictrl.rs new file mode 100644 index 000000000000..b80743e9e3e6 --- /dev/null +++ b/pac/atsamc21n/src/eic/nmictrl.rs @@ -0,0 +1,345 @@ +#[doc = "Register `NMICTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `NMICTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Non-Maskable Interrupt Sense Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum NMISENSE_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising-edge detection"] + RISE = 1, + #[doc = "2: Falling-edge detection"] + FALL = 2, + #[doc = "3: Both-edges detection"] + BOTH = 3, + #[doc = "4: High-level detection"] + HIGH = 4, + #[doc = "5: Low-level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: NMISENSE_A) -> Self { + variant as _ + } +} +#[doc = "Field `NMISENSE` reader - Non-Maskable Interrupt Sense Configuration"] +pub struct NMISENSE_R(crate::FieldReader); +impl NMISENSE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + NMISENSE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(NMISENSE_A::NONE), + 1 => Some(NMISENSE_A::RISE), + 2 => Some(NMISENSE_A::FALL), + 3 => Some(NMISENSE_A::BOTH), + 4 => Some(NMISENSE_A::HIGH), + 5 => Some(NMISENSE_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == NMISENSE_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == NMISENSE_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == NMISENSE_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == NMISENSE_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == NMISENSE_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == NMISENSE_A::LOW + } +} +impl core::ops::Deref for NMISENSE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NMISENSE` writer - Non-Maskable Interrupt Sense Configuration"] +pub struct NMISENSE_W<'a> { + w: &'a mut W, +} +impl<'a> NMISENSE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: NMISENSE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(NMISENSE_A::NONE) + } + #[doc = "Rising-edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(NMISENSE_A::RISE) + } + #[doc = "Falling-edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(NMISENSE_A::FALL) + } + #[doc = "Both-edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(NMISENSE_A::BOTH) + } + #[doc = "High-level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(NMISENSE_A::HIGH) + } + #[doc = "Low-level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(NMISENSE_A::LOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +#[doc = "Field `NMIFILTEN` reader - Non-Maskable Interrupt Filter Enable"] +pub struct NMIFILTEN_R(crate::FieldReader); +impl NMIFILTEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NMIFILTEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NMIFILTEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NMIFILTEN` writer - Non-Maskable Interrupt Filter Enable"] +pub struct NMIFILTEN_W<'a> { + w: &'a mut W, +} +impl<'a> NMIFILTEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Asynchronous Edge Detection Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum NMIASYNCH_A { + #[doc = "0: Edge detection is clock synchronously operated"] + SYNC = 0, + #[doc = "1: Edge detection is clock asynchronously operated"] + ASYNC = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NMIASYNCH_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NMIASYNCH` reader - Asynchronous Edge Detection Mode"] +pub struct NMIASYNCH_R(crate::FieldReader); +impl NMIASYNCH_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NMIASYNCH_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> NMIASYNCH_A { + match self.bits { + false => NMIASYNCH_A::SYNC, + true => NMIASYNCH_A::ASYNC, + } + } + #[doc = "Checks if the value of the field is `SYNC`"] + #[inline(always)] + pub fn is_sync(&self) -> bool { + **self == NMIASYNCH_A::SYNC + } + #[doc = "Checks if the value of the field is `ASYNC`"] + #[inline(always)] + pub fn is_async(&self) -> bool { + **self == NMIASYNCH_A::ASYNC + } +} +impl core::ops::Deref for NMIASYNCH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NMIASYNCH` writer - Asynchronous Edge Detection Mode"] +pub struct NMIASYNCH_W<'a> { + w: &'a mut W, +} +impl<'a> NMIASYNCH_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: NMIASYNCH_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Edge detection is clock synchronously operated"] + #[inline(always)] + pub fn sync(self) -> &'a mut W { + self.variant(NMIASYNCH_A::SYNC) + } + #[doc = "Edge detection is clock asynchronously operated"] + #[inline(always)] + pub fn async_(self) -> &'a mut W { + self.variant(NMIASYNCH_A::ASYNC) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Non-Maskable Interrupt Sense Configuration"] + #[inline(always)] + pub fn nmisense(&self) -> NMISENSE_R { + NMISENSE_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 3 - Non-Maskable Interrupt Filter Enable"] + #[inline(always)] + pub fn nmifilten(&self) -> NMIFILTEN_R { + NMIFILTEN_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Asynchronous Edge Detection Mode"] + #[inline(always)] + pub fn nmiasynch(&self) -> NMIASYNCH_R { + NMIASYNCH_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Non-Maskable Interrupt Sense Configuration"] + #[inline(always)] + pub fn nmisense(&mut self) -> NMISENSE_W { + NMISENSE_W { w: self } + } + #[doc = "Bit 3 - Non-Maskable Interrupt Filter Enable"] + #[inline(always)] + pub fn nmifilten(&mut self) -> NMIFILTEN_W { + NMIFILTEN_W { w: self } + } + #[doc = "Bit 4 - Asynchronous Edge Detection Mode"] + #[inline(always)] + pub fn nmiasynch(&mut self) -> NMIASYNCH_W { + NMIASYNCH_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Non-Maskable Interrupt Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [nmictrl](index.html) module"] +pub struct NMICTRL_SPEC; +impl crate::RegisterSpec for NMICTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [nmictrl::R](R) reader structure"] +impl crate::Readable for NMICTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [nmictrl::W](W) writer structure"] +impl crate::Writable for NMICTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets NMICTRL to value 0"] +impl crate::Resettable for NMICTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/eic/nmiflag.rs b/pac/atsamc21n/src/eic/nmiflag.rs new file mode 100644 index 000000000000..a373bb4b8d9c --- /dev/null +++ b/pac/atsamc21n/src/eic/nmiflag.rs @@ -0,0 +1,113 @@ +#[doc = "Register `NMIFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `NMIFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `NMI` reader - Non-Maskable Interrupt"] +pub struct NMI_R(crate::FieldReader); +impl NMI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NMI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NMI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NMI` writer - Non-Maskable Interrupt"] +pub struct NMI_W<'a> { + w: &'a mut W, +} +impl<'a> NMI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Non-Maskable Interrupt"] + #[inline(always)] + pub fn nmi(&self) -> NMI_R { + NMI_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Non-Maskable Interrupt"] + #[inline(always)] + pub fn nmi(&mut self) -> NMI_W { + NMI_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Non-Maskable Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [nmiflag](index.html) module"] +pub struct NMIFLAG_SPEC; +impl crate::RegisterSpec for NMIFLAG_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [nmiflag::R](R) reader structure"] +impl crate::Readable for NMIFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [nmiflag::W](W) writer structure"] +impl crate::Writable for NMIFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets NMIFLAG to value 0"] +impl crate::Resettable for NMIFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/eic/pinstate.rs b/pac/atsamc21n/src/eic/pinstate.rs new file mode 100644 index 000000000000..da07c8f57423 --- /dev/null +++ b/pac/atsamc21n/src/eic/pinstate.rs @@ -0,0 +1,53 @@ +#[doc = "Register `PINSTATE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PINSTATE` reader - Pin State"] +pub struct PINSTATE_R(crate::FieldReader); +impl PINSTATE_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + PINSTATE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PINSTATE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:15 - Pin State"] + #[inline(always)] + pub fn pinstate(&self) -> PINSTATE_R { + PINSTATE_R::new((self.bits & 0xffff) as u16) + } +} +#[doc = "Pin State\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pinstate](index.html) module"] +pub struct PINSTATE_SPEC; +impl crate::RegisterSpec for PINSTATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pinstate::R](R) reader structure"] +impl crate::Readable for PINSTATE_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PINSTATE to value 0"] +impl crate::Resettable for PINSTATE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/eic/syncbusy.rs b/pac/atsamc21n/src/eic/syncbusy.rs new file mode 100644 index 000000000000..fb4e99bcbcb0 --- /dev/null +++ b/pac/atsamc21n/src/eic/syncbusy.rs @@ -0,0 +1,73 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy Status"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - Enable Synchronization Busy Status"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy Status"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable Synchronization Busy Status"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +#[doc = "Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/evsys.rs b/pac/atsamc21n/src/evsys.rs new file mode 100644 index 000000000000..664de5fe9cab --- /dev/null +++ b/pac/atsamc21n/src/evsys.rs @@ -0,0 +1,54 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrla: crate::Reg, + _reserved1: [u8; 0x0b], + #[doc = "0x0c - Channel Status"] + pub chstatus: crate::Reg, + #[doc = "0x10 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x14 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x18 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x1c - Software Event"] + pub swevt: crate::Reg, + #[doc = "0x20..0x50 - Channel n"] + pub channel: [crate::Reg; 12], + _reserved7: [u8; 0x30], + #[doc = "0x80..0x148 - User Multiplexer n"] + pub user: [crate::Reg; 50], +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control"] +pub mod ctrla; +#[doc = "CHSTATUS register accessor: an alias for `Reg`"] +pub type CHSTATUS = crate::Reg; +#[doc = "Channel Status"] +pub mod chstatus; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "SWEVT register accessor: an alias for `Reg`"] +pub type SWEVT = crate::Reg; +#[doc = "Software Event"] +pub mod swevt; +#[doc = "CHANNEL register accessor: an alias for `Reg`"] +pub type CHANNEL = crate::Reg; +#[doc = "Channel n"] +pub mod channel; +#[doc = "USER register accessor: an alias for `Reg`"] +pub type USER = crate::Reg; +#[doc = "User Multiplexer n"] +pub mod user; diff --git a/pac/atsamc21n/src/evsys/channel.rs b/pac/atsamc21n/src/evsys/channel.rs new file mode 100644 index 000000000000..20e3857da922 --- /dev/null +++ b/pac/atsamc21n/src/evsys/channel.rs @@ -0,0 +1,409 @@ +#[doc = "Register `CHANNEL[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHANNEL[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVGEN` reader - Event Generator Selection"] +pub struct EVGEN_R(crate::FieldReader); +impl EVGEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVGEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVGEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVGEN` writer - Event Generator Selection"] +pub struct EVGEN_W<'a> { + w: &'a mut W, +} +impl<'a> EVGEN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x7f) | (value as u32 & 0x7f); + self.w + } +} +#[doc = "Path Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PATH_A { + #[doc = "0: Synchronous path"] + SYNCHRONOUS = 0, + #[doc = "1: Resynchronized path"] + RESYNCHRONIZED = 1, + #[doc = "2: Asynchronous path"] + ASYNCHRONOUS = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PATH_A) -> Self { + variant as _ + } +} +#[doc = "Field `PATH` reader - Path Selection"] +pub struct PATH_R(crate::FieldReader); +impl PATH_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PATH_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PATH_A::SYNCHRONOUS), + 1 => Some(PATH_A::RESYNCHRONIZED), + 2 => Some(PATH_A::ASYNCHRONOUS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `SYNCHRONOUS`"] + #[inline(always)] + pub fn is_synchronous(&self) -> bool { + **self == PATH_A::SYNCHRONOUS + } + #[doc = "Checks if the value of the field is `RESYNCHRONIZED`"] + #[inline(always)] + pub fn is_resynchronized(&self) -> bool { + **self == PATH_A::RESYNCHRONIZED + } + #[doc = "Checks if the value of the field is `ASYNCHRONOUS`"] + #[inline(always)] + pub fn is_asynchronous(&self) -> bool { + **self == PATH_A::ASYNCHRONOUS + } +} +impl core::ops::Deref for PATH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PATH` writer - Path Selection"] +pub struct PATH_W<'a> { + w: &'a mut W, +} +impl<'a> PATH_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PATH_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Synchronous path"] + #[inline(always)] + pub fn synchronous(self) -> &'a mut W { + self.variant(PATH_A::SYNCHRONOUS) + } + #[doc = "Resynchronized path"] + #[inline(always)] + pub fn resynchronized(self) -> &'a mut W { + self.variant(PATH_A::RESYNCHRONIZED) + } + #[doc = "Asynchronous path"] + #[inline(always)] + pub fn asynchronous(self) -> &'a mut W { + self.variant(PATH_A::ASYNCHRONOUS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 8)) | ((value as u32 & 0x03) << 8); + self.w + } +} +#[doc = "Edge Detection Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EDGSEL_A { + #[doc = "0: No event output when using the resynchronized or synchronous path"] + NO_EVT_OUTPUT = 0, + #[doc = "1: Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path"] + RISING_EDGE = 1, + #[doc = "2: Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path"] + FALLING_EDGE = 2, + #[doc = "3: Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path"] + BOTH_EDGES = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EDGSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `EDGSEL` reader - Edge Detection Selection"] +pub struct EDGSEL_R(crate::FieldReader); +impl EDGSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EDGSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EDGSEL_A { + match self.bits { + 0 => EDGSEL_A::NO_EVT_OUTPUT, + 1 => EDGSEL_A::RISING_EDGE, + 2 => EDGSEL_A::FALLING_EDGE, + 3 => EDGSEL_A::BOTH_EDGES, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NO_EVT_OUTPUT`"] + #[inline(always)] + pub fn is_no_evt_output(&self) -> bool { + **self == EDGSEL_A::NO_EVT_OUTPUT + } + #[doc = "Checks if the value of the field is `RISING_EDGE`"] + #[inline(always)] + pub fn is_rising_edge(&self) -> bool { + **self == EDGSEL_A::RISING_EDGE + } + #[doc = "Checks if the value of the field is `FALLING_EDGE`"] + #[inline(always)] + pub fn is_falling_edge(&self) -> bool { + **self == EDGSEL_A::FALLING_EDGE + } + #[doc = "Checks if the value of the field is `BOTH_EDGES`"] + #[inline(always)] + pub fn is_both_edges(&self) -> bool { + **self == EDGSEL_A::BOTH_EDGES + } +} +impl core::ops::Deref for EDGSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EDGSEL` writer - Edge Detection Selection"] +pub struct EDGSEL_W<'a> { + w: &'a mut W, +} +impl<'a> EDGSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EDGSEL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "No event output when using the resynchronized or synchronous path"] + #[inline(always)] + pub fn no_evt_output(self) -> &'a mut W { + self.variant(EDGSEL_A::NO_EVT_OUTPUT) + } + #[doc = "Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path"] + #[inline(always)] + pub fn rising_edge(self) -> &'a mut W { + self.variant(EDGSEL_A::RISING_EDGE) + } + #[doc = "Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path"] + #[inline(always)] + pub fn falling_edge(self) -> &'a mut W { + self.variant(EDGSEL_A::FALLING_EDGE) + } + #[doc = "Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path"] + #[inline(always)] + pub fn both_edges(self) -> &'a mut W { + self.variant(EDGSEL_A::BOTH_EDGES) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 10)) | ((value as u32 & 0x03) << 10); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - Generic Clock On Demand"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - Generic Clock On Demand"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bits 0:6 - Event Generator Selection"] + #[inline(always)] + pub fn evgen(&self) -> EVGEN_R { + EVGEN_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bits 8:9 - Path Selection"] + #[inline(always)] + pub fn path(&self) -> PATH_R { + PATH_R::new(((self.bits >> 8) & 0x03) as u8) + } + #[doc = "Bits 10:11 - Edge Detection Selection"] + #[inline(always)] + pub fn edgsel(&self) -> EDGSEL_R { + EDGSEL_R::new(((self.bits >> 10) & 0x03) as u8) + } + #[doc = "Bit 14 - Run in standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Generic Clock On Demand"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:6 - Event Generator Selection"] + #[inline(always)] + pub fn evgen(&mut self) -> EVGEN_W { + EVGEN_W { w: self } + } + #[doc = "Bits 8:9 - Path Selection"] + #[inline(always)] + pub fn path(&mut self) -> PATH_W { + PATH_W { w: self } + } + #[doc = "Bits 10:11 - Edge Detection Selection"] + #[inline(always)] + pub fn edgsel(&mut self) -> EDGSEL_W { + EDGSEL_W { w: self } + } + #[doc = "Bit 14 - Run in standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 15 - Generic Clock On Demand"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [channel](index.html) module"] +pub struct CHANNEL_SPEC; +impl crate::RegisterSpec for CHANNEL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [channel::R](R) reader structure"] +impl crate::Readable for CHANNEL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [channel::W](W) writer structure"] +impl crate::Writable for CHANNEL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHANNEL[%s] +to value 0x8000"] +impl crate::Resettable for CHANNEL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x8000 + } +} diff --git a/pac/atsamc21n/src/evsys/chstatus.rs b/pac/atsamc21n/src/evsys/chstatus.rs new file mode 100644 index 000000000000..811089dfdeb8 --- /dev/null +++ b/pac/atsamc21n/src/evsys/chstatus.rs @@ -0,0 +1,513 @@ +#[doc = "Register `CHSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `USRRDY0` reader - Channel 0 User Ready"] +pub struct USRRDY0_R(crate::FieldReader); +impl USRRDY0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY1` reader - Channel 1 User Ready"] +pub struct USRRDY1_R(crate::FieldReader); +impl USRRDY1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY2` reader - Channel 2 User Ready"] +pub struct USRRDY2_R(crate::FieldReader); +impl USRRDY2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY3` reader - Channel 3 User Ready"] +pub struct USRRDY3_R(crate::FieldReader); +impl USRRDY3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY4` reader - Channel 4 User Ready"] +pub struct USRRDY4_R(crate::FieldReader); +impl USRRDY4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY5` reader - Channel 5 User Ready"] +pub struct USRRDY5_R(crate::FieldReader); +impl USRRDY5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY6` reader - Channel 6 User Ready"] +pub struct USRRDY6_R(crate::FieldReader); +impl USRRDY6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY7` reader - Channel 7 User Ready"] +pub struct USRRDY7_R(crate::FieldReader); +impl USRRDY7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY8` reader - Channel 8 User Ready"] +pub struct USRRDY8_R(crate::FieldReader); +impl USRRDY8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY9` reader - Channel 9 User Ready"] +pub struct USRRDY9_R(crate::FieldReader); +impl USRRDY9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY10` reader - Channel 10 User Ready"] +pub struct USRRDY10_R(crate::FieldReader); +impl USRRDY10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USRRDY11` reader - Channel 11 User Ready"] +pub struct USRRDY11_R(crate::FieldReader); +impl USRRDY11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USRRDY11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USRRDY11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY0` reader - Channel 0 Busy"] +pub struct CHBUSY0_R(crate::FieldReader); +impl CHBUSY0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY1` reader - Channel 1 Busy"] +pub struct CHBUSY1_R(crate::FieldReader); +impl CHBUSY1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY2` reader - Channel 2 Busy"] +pub struct CHBUSY2_R(crate::FieldReader); +impl CHBUSY2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY3` reader - Channel 3 Busy"] +pub struct CHBUSY3_R(crate::FieldReader); +impl CHBUSY3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY4` reader - Channel 4 Busy"] +pub struct CHBUSY4_R(crate::FieldReader); +impl CHBUSY4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY5` reader - Channel 5 Busy"] +pub struct CHBUSY5_R(crate::FieldReader); +impl CHBUSY5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY6` reader - Channel 6 Busy"] +pub struct CHBUSY6_R(crate::FieldReader); +impl CHBUSY6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY7` reader - Channel 7 Busy"] +pub struct CHBUSY7_R(crate::FieldReader); +impl CHBUSY7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY8` reader - Channel 8 Busy"] +pub struct CHBUSY8_R(crate::FieldReader); +impl CHBUSY8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY9` reader - Channel 9 Busy"] +pub struct CHBUSY9_R(crate::FieldReader); +impl CHBUSY9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY10` reader - Channel 10 Busy"] +pub struct CHBUSY10_R(crate::FieldReader); +impl CHBUSY10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHBUSY11` reader - Channel 11 Busy"] +pub struct CHBUSY11_R(crate::FieldReader); +impl CHBUSY11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHBUSY11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHBUSY11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Channel 0 User Ready"] + #[inline(always)] + pub fn usrrdy0(&self) -> USRRDY0_R { + USRRDY0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel 1 User Ready"] + #[inline(always)] + pub fn usrrdy1(&self) -> USRRDY1_R { + USRRDY1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel 2 User Ready"] + #[inline(always)] + pub fn usrrdy2(&self) -> USRRDY2_R { + USRRDY2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Channel 3 User Ready"] + #[inline(always)] + pub fn usrrdy3(&self) -> USRRDY3_R { + USRRDY3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Channel 4 User Ready"] + #[inline(always)] + pub fn usrrdy4(&self) -> USRRDY4_R { + USRRDY4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Channel 5 User Ready"] + #[inline(always)] + pub fn usrrdy5(&self) -> USRRDY5_R { + USRRDY5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Channel 6 User Ready"] + #[inline(always)] + pub fn usrrdy6(&self) -> USRRDY6_R { + USRRDY6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Channel 7 User Ready"] + #[inline(always)] + pub fn usrrdy7(&self) -> USRRDY7_R { + USRRDY7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Channel 8 User Ready"] + #[inline(always)] + pub fn usrrdy8(&self) -> USRRDY8_R { + USRRDY8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Channel 9 User Ready"] + #[inline(always)] + pub fn usrrdy9(&self) -> USRRDY9_R { + USRRDY9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Channel 10 User Ready"] + #[inline(always)] + pub fn usrrdy10(&self) -> USRRDY10_R { + USRRDY10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Channel 11 User Ready"] + #[inline(always)] + pub fn usrrdy11(&self) -> USRRDY11_R { + USRRDY11_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 16 - Channel 0 Busy"] + #[inline(always)] + pub fn chbusy0(&self) -> CHBUSY0_R { + CHBUSY0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Channel 1 Busy"] + #[inline(always)] + pub fn chbusy1(&self) -> CHBUSY1_R { + CHBUSY1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Channel 2 Busy"] + #[inline(always)] + pub fn chbusy2(&self) -> CHBUSY2_R { + CHBUSY2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Channel 3 Busy"] + #[inline(always)] + pub fn chbusy3(&self) -> CHBUSY3_R { + CHBUSY3_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Channel 4 Busy"] + #[inline(always)] + pub fn chbusy4(&self) -> CHBUSY4_R { + CHBUSY4_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Channel 5 Busy"] + #[inline(always)] + pub fn chbusy5(&self) -> CHBUSY5_R { + CHBUSY5_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Channel 6 Busy"] + #[inline(always)] + pub fn chbusy6(&self) -> CHBUSY6_R { + CHBUSY6_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Channel 7 Busy"] + #[inline(always)] + pub fn chbusy7(&self) -> CHBUSY7_R { + CHBUSY7_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24 - Channel 8 Busy"] + #[inline(always)] + pub fn chbusy8(&self) -> CHBUSY8_R { + CHBUSY8_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Channel 9 Busy"] + #[inline(always)] + pub fn chbusy9(&self) -> CHBUSY9_R { + CHBUSY9_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Channel 10 Busy"] + #[inline(always)] + pub fn chbusy10(&self) -> CHBUSY10_R { + CHBUSY10_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Channel 11 Busy"] + #[inline(always)] + pub fn chbusy11(&self) -> CHBUSY11_R { + CHBUSY11_R::new(((self.bits >> 27) & 0x01) != 0) + } +} +#[doc = "Channel Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chstatus](index.html) module"] +pub struct CHSTATUS_SPEC; +impl crate::RegisterSpec for CHSTATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [chstatus::R](R) reader structure"] +impl crate::Readable for CHSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CHSTATUS to value 0"] +impl crate::Resettable for CHSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/evsys/ctrla.rs b/pac/atsamc21n/src/evsys/ctrla.rs new file mode 100644 index 000000000000..1c24704395ad --- /dev/null +++ b/pac/atsamc21n/src/evsys/ctrla.rs @@ -0,0 +1,113 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/evsys/intenclr.rs b/pac/atsamc21n/src/evsys/intenclr.rs new file mode 100644 index 000000000000..6a6a0b2b94c5 --- /dev/null +++ b/pac/atsamc21n/src/evsys/intenclr.rs @@ -0,0 +1,1194 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVR0` reader - Channel 0 Overrun Interrupt Enable"] +pub struct OVR0_R(crate::FieldReader); +impl OVR0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR0` writer - Channel 0 Overrun Interrupt Enable"] +pub struct OVR0_W<'a> { + w: &'a mut W, +} +impl<'a> OVR0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `OVR1` reader - Channel 1 Overrun Interrupt Enable"] +pub struct OVR1_R(crate::FieldReader); +impl OVR1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR1` writer - Channel 1 Overrun Interrupt Enable"] +pub struct OVR1_W<'a> { + w: &'a mut W, +} +impl<'a> OVR1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `OVR2` reader - Channel 2 Overrun Interrupt Enable"] +pub struct OVR2_R(crate::FieldReader); +impl OVR2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR2` writer - Channel 2 Overrun Interrupt Enable"] +pub struct OVR2_W<'a> { + w: &'a mut W, +} +impl<'a> OVR2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `OVR3` reader - Channel 3 Overrun Interrupt Enable"] +pub struct OVR3_R(crate::FieldReader); +impl OVR3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR3` writer - Channel 3 Overrun Interrupt Enable"] +pub struct OVR3_W<'a> { + w: &'a mut W, +} +impl<'a> OVR3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `OVR4` reader - Channel 4 Overrun Interrupt Enable"] +pub struct OVR4_R(crate::FieldReader); +impl OVR4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR4` writer - Channel 4 Overrun Interrupt Enable"] +pub struct OVR4_W<'a> { + w: &'a mut W, +} +impl<'a> OVR4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `OVR5` reader - Channel 5 Overrun Interrupt Enable"] +pub struct OVR5_R(crate::FieldReader); +impl OVR5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR5` writer - Channel 5 Overrun Interrupt Enable"] +pub struct OVR5_W<'a> { + w: &'a mut W, +} +impl<'a> OVR5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `OVR6` reader - Channel 6 Overrun Interrupt Enable"] +pub struct OVR6_R(crate::FieldReader); +impl OVR6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR6` writer - Channel 6 Overrun Interrupt Enable"] +pub struct OVR6_W<'a> { + w: &'a mut W, +} +impl<'a> OVR6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `OVR7` reader - Channel 7 Overrun Interrupt Enable"] +pub struct OVR7_R(crate::FieldReader); +impl OVR7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR7` writer - Channel 7 Overrun Interrupt Enable"] +pub struct OVR7_W<'a> { + w: &'a mut W, +} +impl<'a> OVR7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `OVR8` reader - Channel 8 Overrun Interrupt Enable"] +pub struct OVR8_R(crate::FieldReader); +impl OVR8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR8` writer - Channel 8 Overrun Interrupt Enable"] +pub struct OVR8_W<'a> { + w: &'a mut W, +} +impl<'a> OVR8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `OVR9` reader - Channel 9 Overrun Interrupt Enable"] +pub struct OVR9_R(crate::FieldReader); +impl OVR9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR9` writer - Channel 9 Overrun Interrupt Enable"] +pub struct OVR9_W<'a> { + w: &'a mut W, +} +impl<'a> OVR9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `OVR10` reader - Channel 10 Overrun Interrupt Enable"] +pub struct OVR10_R(crate::FieldReader); +impl OVR10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR10` writer - Channel 10 Overrun Interrupt Enable"] +pub struct OVR10_W<'a> { + w: &'a mut W, +} +impl<'a> OVR10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `OVR11` reader - Channel 11 Overrun Interrupt Enable"] +pub struct OVR11_R(crate::FieldReader); +impl OVR11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR11` writer - Channel 11 Overrun Interrupt Enable"] +pub struct OVR11_W<'a> { + w: &'a mut W, +} +impl<'a> OVR11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `EVD0` reader - Channel 0 Event Detection Interrupt Enable"] +pub struct EVD0_R(crate::FieldReader); +impl EVD0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD0` writer - Channel 0 Event Detection Interrupt Enable"] +pub struct EVD0_W<'a> { + w: &'a mut W, +} +impl<'a> EVD0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `EVD1` reader - Channel 1 Event Detection Interrupt Enable"] +pub struct EVD1_R(crate::FieldReader); +impl EVD1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD1` writer - Channel 1 Event Detection Interrupt Enable"] +pub struct EVD1_W<'a> { + w: &'a mut W, +} +impl<'a> EVD1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `EVD2` reader - Channel 2 Event Detection Interrupt Enable"] +pub struct EVD2_R(crate::FieldReader); +impl EVD2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD2` writer - Channel 2 Event Detection Interrupt Enable"] +pub struct EVD2_W<'a> { + w: &'a mut W, +} +impl<'a> EVD2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `EVD3` reader - Channel 3 Event Detection Interrupt Enable"] +pub struct EVD3_R(crate::FieldReader); +impl EVD3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD3` writer - Channel 3 Event Detection Interrupt Enable"] +pub struct EVD3_W<'a> { + w: &'a mut W, +} +impl<'a> EVD3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `EVD4` reader - Channel 4 Event Detection Interrupt Enable"] +pub struct EVD4_R(crate::FieldReader); +impl EVD4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD4` writer - Channel 4 Event Detection Interrupt Enable"] +pub struct EVD4_W<'a> { + w: &'a mut W, +} +impl<'a> EVD4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `EVD5` reader - Channel 5 Event Detection Interrupt Enable"] +pub struct EVD5_R(crate::FieldReader); +impl EVD5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD5` writer - Channel 5 Event Detection Interrupt Enable"] +pub struct EVD5_W<'a> { + w: &'a mut W, +} +impl<'a> EVD5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `EVD6` reader - Channel 6 Event Detection Interrupt Enable"] +pub struct EVD6_R(crate::FieldReader); +impl EVD6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD6` writer - Channel 6 Event Detection Interrupt Enable"] +pub struct EVD6_W<'a> { + w: &'a mut W, +} +impl<'a> EVD6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `EVD7` reader - Channel 7 Event Detection Interrupt Enable"] +pub struct EVD7_R(crate::FieldReader); +impl EVD7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD7` writer - Channel 7 Event Detection Interrupt Enable"] +pub struct EVD7_W<'a> { + w: &'a mut W, +} +impl<'a> EVD7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `EVD8` reader - Channel 8 Event Detection Interrupt Enable"] +pub struct EVD8_R(crate::FieldReader); +impl EVD8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD8` writer - Channel 8 Event Detection Interrupt Enable"] +pub struct EVD8_W<'a> { + w: &'a mut W, +} +impl<'a> EVD8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `EVD9` reader - Channel 9 Event Detection Interrupt Enable"] +pub struct EVD9_R(crate::FieldReader); +impl EVD9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD9` writer - Channel 9 Event Detection Interrupt Enable"] +pub struct EVD9_W<'a> { + w: &'a mut W, +} +impl<'a> EVD9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `EVD10` reader - Channel 10 Event Detection Interrupt Enable"] +pub struct EVD10_R(crate::FieldReader); +impl EVD10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD10` writer - Channel 10 Event Detection Interrupt Enable"] +pub struct EVD10_W<'a> { + w: &'a mut W, +} +impl<'a> EVD10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `EVD11` reader - Channel 11 Event Detection Interrupt Enable"] +pub struct EVD11_R(crate::FieldReader); +impl EVD11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD11` writer - Channel 11 Event Detection Interrupt Enable"] +pub struct EVD11_W<'a> { + w: &'a mut W, +} +impl<'a> EVD11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +impl R { + #[doc = "Bit 0 - Channel 0 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr0(&self) -> OVR0_R { + OVR0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel 1 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr1(&self) -> OVR1_R { + OVR1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel 2 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr2(&self) -> OVR2_R { + OVR2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Channel 3 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr3(&self) -> OVR3_R { + OVR3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Channel 4 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr4(&self) -> OVR4_R { + OVR4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Channel 5 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr5(&self) -> OVR5_R { + OVR5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Channel 6 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr6(&self) -> OVR6_R { + OVR6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Channel 7 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr7(&self) -> OVR7_R { + OVR7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Channel 8 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr8(&self) -> OVR8_R { + OVR8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Channel 9 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr9(&self) -> OVR9_R { + OVR9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Channel 10 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr10(&self) -> OVR10_R { + OVR10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Channel 11 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr11(&self) -> OVR11_R { + OVR11_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 16 - Channel 0 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd0(&self) -> EVD0_R { + EVD0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Channel 1 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd1(&self) -> EVD1_R { + EVD1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Channel 2 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd2(&self) -> EVD2_R { + EVD2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Channel 3 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd3(&self) -> EVD3_R { + EVD3_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Channel 4 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd4(&self) -> EVD4_R { + EVD4_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Channel 5 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd5(&self) -> EVD5_R { + EVD5_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Channel 6 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd6(&self) -> EVD6_R { + EVD6_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Channel 7 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd7(&self) -> EVD7_R { + EVD7_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24 - Channel 8 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd8(&self) -> EVD8_R { + EVD8_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Channel 9 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd9(&self) -> EVD9_R { + EVD9_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Channel 10 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd10(&self) -> EVD10_R { + EVD10_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Channel 11 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd11(&self) -> EVD11_R { + EVD11_R::new(((self.bits >> 27) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel 0 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr0(&mut self) -> OVR0_W { + OVR0_W { w: self } + } + #[doc = "Bit 1 - Channel 1 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr1(&mut self) -> OVR1_W { + OVR1_W { w: self } + } + #[doc = "Bit 2 - Channel 2 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr2(&mut self) -> OVR2_W { + OVR2_W { w: self } + } + #[doc = "Bit 3 - Channel 3 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr3(&mut self) -> OVR3_W { + OVR3_W { w: self } + } + #[doc = "Bit 4 - Channel 4 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr4(&mut self) -> OVR4_W { + OVR4_W { w: self } + } + #[doc = "Bit 5 - Channel 5 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr5(&mut self) -> OVR5_W { + OVR5_W { w: self } + } + #[doc = "Bit 6 - Channel 6 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr6(&mut self) -> OVR6_W { + OVR6_W { w: self } + } + #[doc = "Bit 7 - Channel 7 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr7(&mut self) -> OVR7_W { + OVR7_W { w: self } + } + #[doc = "Bit 8 - Channel 8 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr8(&mut self) -> OVR8_W { + OVR8_W { w: self } + } + #[doc = "Bit 9 - Channel 9 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr9(&mut self) -> OVR9_W { + OVR9_W { w: self } + } + #[doc = "Bit 10 - Channel 10 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr10(&mut self) -> OVR10_W { + OVR10_W { w: self } + } + #[doc = "Bit 11 - Channel 11 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr11(&mut self) -> OVR11_W { + OVR11_W { w: self } + } + #[doc = "Bit 16 - Channel 0 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd0(&mut self) -> EVD0_W { + EVD0_W { w: self } + } + #[doc = "Bit 17 - Channel 1 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd1(&mut self) -> EVD1_W { + EVD1_W { w: self } + } + #[doc = "Bit 18 - Channel 2 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd2(&mut self) -> EVD2_W { + EVD2_W { w: self } + } + #[doc = "Bit 19 - Channel 3 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd3(&mut self) -> EVD3_W { + EVD3_W { w: self } + } + #[doc = "Bit 20 - Channel 4 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd4(&mut self) -> EVD4_W { + EVD4_W { w: self } + } + #[doc = "Bit 21 - Channel 5 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd5(&mut self) -> EVD5_W { + EVD5_W { w: self } + } + #[doc = "Bit 22 - Channel 6 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd6(&mut self) -> EVD6_W { + EVD6_W { w: self } + } + #[doc = "Bit 23 - Channel 7 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd7(&mut self) -> EVD7_W { + EVD7_W { w: self } + } + #[doc = "Bit 24 - Channel 8 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd8(&mut self) -> EVD8_W { + EVD8_W { w: self } + } + #[doc = "Bit 25 - Channel 9 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd9(&mut self) -> EVD9_W { + EVD9_W { w: self } + } + #[doc = "Bit 26 - Channel 10 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd10(&mut self) -> EVD10_W { + EVD10_W { w: self } + } + #[doc = "Bit 27 - Channel 11 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd11(&mut self) -> EVD11_W { + EVD11_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/evsys/intenset.rs b/pac/atsamc21n/src/evsys/intenset.rs new file mode 100644 index 000000000000..d84061297909 --- /dev/null +++ b/pac/atsamc21n/src/evsys/intenset.rs @@ -0,0 +1,1194 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVR0` reader - Channel 0 Overrun Interrupt Enable"] +pub struct OVR0_R(crate::FieldReader); +impl OVR0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR0` writer - Channel 0 Overrun Interrupt Enable"] +pub struct OVR0_W<'a> { + w: &'a mut W, +} +impl<'a> OVR0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `OVR1` reader - Channel 1 Overrun Interrupt Enable"] +pub struct OVR1_R(crate::FieldReader); +impl OVR1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR1` writer - Channel 1 Overrun Interrupt Enable"] +pub struct OVR1_W<'a> { + w: &'a mut W, +} +impl<'a> OVR1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `OVR2` reader - Channel 2 Overrun Interrupt Enable"] +pub struct OVR2_R(crate::FieldReader); +impl OVR2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR2` writer - Channel 2 Overrun Interrupt Enable"] +pub struct OVR2_W<'a> { + w: &'a mut W, +} +impl<'a> OVR2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `OVR3` reader - Channel 3 Overrun Interrupt Enable"] +pub struct OVR3_R(crate::FieldReader); +impl OVR3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR3` writer - Channel 3 Overrun Interrupt Enable"] +pub struct OVR3_W<'a> { + w: &'a mut W, +} +impl<'a> OVR3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `OVR4` reader - Channel 4 Overrun Interrupt Enable"] +pub struct OVR4_R(crate::FieldReader); +impl OVR4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR4` writer - Channel 4 Overrun Interrupt Enable"] +pub struct OVR4_W<'a> { + w: &'a mut W, +} +impl<'a> OVR4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `OVR5` reader - Channel 5 Overrun Interrupt Enable"] +pub struct OVR5_R(crate::FieldReader); +impl OVR5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR5` writer - Channel 5 Overrun Interrupt Enable"] +pub struct OVR5_W<'a> { + w: &'a mut W, +} +impl<'a> OVR5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `OVR6` reader - Channel 6 Overrun Interrupt Enable"] +pub struct OVR6_R(crate::FieldReader); +impl OVR6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR6` writer - Channel 6 Overrun Interrupt Enable"] +pub struct OVR6_W<'a> { + w: &'a mut W, +} +impl<'a> OVR6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `OVR7` reader - Channel 7 Overrun Interrupt Enable"] +pub struct OVR7_R(crate::FieldReader); +impl OVR7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR7` writer - Channel 7 Overrun Interrupt Enable"] +pub struct OVR7_W<'a> { + w: &'a mut W, +} +impl<'a> OVR7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `OVR8` reader - Channel 8 Overrun Interrupt Enable"] +pub struct OVR8_R(crate::FieldReader); +impl OVR8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR8` writer - Channel 8 Overrun Interrupt Enable"] +pub struct OVR8_W<'a> { + w: &'a mut W, +} +impl<'a> OVR8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `OVR9` reader - Channel 9 Overrun Interrupt Enable"] +pub struct OVR9_R(crate::FieldReader); +impl OVR9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR9` writer - Channel 9 Overrun Interrupt Enable"] +pub struct OVR9_W<'a> { + w: &'a mut W, +} +impl<'a> OVR9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `OVR10` reader - Channel 10 Overrun Interrupt Enable"] +pub struct OVR10_R(crate::FieldReader); +impl OVR10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR10` writer - Channel 10 Overrun Interrupt Enable"] +pub struct OVR10_W<'a> { + w: &'a mut W, +} +impl<'a> OVR10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `OVR11` reader - Channel 11 Overrun Interrupt Enable"] +pub struct OVR11_R(crate::FieldReader); +impl OVR11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR11` writer - Channel 11 Overrun Interrupt Enable"] +pub struct OVR11_W<'a> { + w: &'a mut W, +} +impl<'a> OVR11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `EVD0` reader - Channel 0 Event Detection Interrupt Enable"] +pub struct EVD0_R(crate::FieldReader); +impl EVD0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD0` writer - Channel 0 Event Detection Interrupt Enable"] +pub struct EVD0_W<'a> { + w: &'a mut W, +} +impl<'a> EVD0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `EVD1` reader - Channel 1 Event Detection Interrupt Enable"] +pub struct EVD1_R(crate::FieldReader); +impl EVD1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD1` writer - Channel 1 Event Detection Interrupt Enable"] +pub struct EVD1_W<'a> { + w: &'a mut W, +} +impl<'a> EVD1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `EVD2` reader - Channel 2 Event Detection Interrupt Enable"] +pub struct EVD2_R(crate::FieldReader); +impl EVD2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD2` writer - Channel 2 Event Detection Interrupt Enable"] +pub struct EVD2_W<'a> { + w: &'a mut W, +} +impl<'a> EVD2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `EVD3` reader - Channel 3 Event Detection Interrupt Enable"] +pub struct EVD3_R(crate::FieldReader); +impl EVD3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD3` writer - Channel 3 Event Detection Interrupt Enable"] +pub struct EVD3_W<'a> { + w: &'a mut W, +} +impl<'a> EVD3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `EVD4` reader - Channel 4 Event Detection Interrupt Enable"] +pub struct EVD4_R(crate::FieldReader); +impl EVD4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD4` writer - Channel 4 Event Detection Interrupt Enable"] +pub struct EVD4_W<'a> { + w: &'a mut W, +} +impl<'a> EVD4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `EVD5` reader - Channel 5 Event Detection Interrupt Enable"] +pub struct EVD5_R(crate::FieldReader); +impl EVD5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD5` writer - Channel 5 Event Detection Interrupt Enable"] +pub struct EVD5_W<'a> { + w: &'a mut W, +} +impl<'a> EVD5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `EVD6` reader - Channel 6 Event Detection Interrupt Enable"] +pub struct EVD6_R(crate::FieldReader); +impl EVD6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD6` writer - Channel 6 Event Detection Interrupt Enable"] +pub struct EVD6_W<'a> { + w: &'a mut W, +} +impl<'a> EVD6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `EVD7` reader - Channel 7 Event Detection Interrupt Enable"] +pub struct EVD7_R(crate::FieldReader); +impl EVD7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD7` writer - Channel 7 Event Detection Interrupt Enable"] +pub struct EVD7_W<'a> { + w: &'a mut W, +} +impl<'a> EVD7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `EVD8` reader - Channel 8 Event Detection Interrupt Enable"] +pub struct EVD8_R(crate::FieldReader); +impl EVD8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD8` writer - Channel 8 Event Detection Interrupt Enable"] +pub struct EVD8_W<'a> { + w: &'a mut W, +} +impl<'a> EVD8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `EVD9` reader - Channel 9 Event Detection Interrupt Enable"] +pub struct EVD9_R(crate::FieldReader); +impl EVD9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD9` writer - Channel 9 Event Detection Interrupt Enable"] +pub struct EVD9_W<'a> { + w: &'a mut W, +} +impl<'a> EVD9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `EVD10` reader - Channel 10 Event Detection Interrupt Enable"] +pub struct EVD10_R(crate::FieldReader); +impl EVD10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD10` writer - Channel 10 Event Detection Interrupt Enable"] +pub struct EVD10_W<'a> { + w: &'a mut W, +} +impl<'a> EVD10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `EVD11` reader - Channel 11 Event Detection Interrupt Enable"] +pub struct EVD11_R(crate::FieldReader); +impl EVD11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD11` writer - Channel 11 Event Detection Interrupt Enable"] +pub struct EVD11_W<'a> { + w: &'a mut W, +} +impl<'a> EVD11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +impl R { + #[doc = "Bit 0 - Channel 0 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr0(&self) -> OVR0_R { + OVR0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel 1 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr1(&self) -> OVR1_R { + OVR1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel 2 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr2(&self) -> OVR2_R { + OVR2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Channel 3 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr3(&self) -> OVR3_R { + OVR3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Channel 4 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr4(&self) -> OVR4_R { + OVR4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Channel 5 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr5(&self) -> OVR5_R { + OVR5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Channel 6 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr6(&self) -> OVR6_R { + OVR6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Channel 7 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr7(&self) -> OVR7_R { + OVR7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Channel 8 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr8(&self) -> OVR8_R { + OVR8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Channel 9 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr9(&self) -> OVR9_R { + OVR9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Channel 10 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr10(&self) -> OVR10_R { + OVR10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Channel 11 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr11(&self) -> OVR11_R { + OVR11_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 16 - Channel 0 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd0(&self) -> EVD0_R { + EVD0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Channel 1 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd1(&self) -> EVD1_R { + EVD1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Channel 2 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd2(&self) -> EVD2_R { + EVD2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Channel 3 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd3(&self) -> EVD3_R { + EVD3_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Channel 4 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd4(&self) -> EVD4_R { + EVD4_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Channel 5 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd5(&self) -> EVD5_R { + EVD5_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Channel 6 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd6(&self) -> EVD6_R { + EVD6_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Channel 7 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd7(&self) -> EVD7_R { + EVD7_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24 - Channel 8 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd8(&self) -> EVD8_R { + EVD8_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Channel 9 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd9(&self) -> EVD9_R { + EVD9_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Channel 10 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd10(&self) -> EVD10_R { + EVD10_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Channel 11 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd11(&self) -> EVD11_R { + EVD11_R::new(((self.bits >> 27) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel 0 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr0(&mut self) -> OVR0_W { + OVR0_W { w: self } + } + #[doc = "Bit 1 - Channel 1 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr1(&mut self) -> OVR1_W { + OVR1_W { w: self } + } + #[doc = "Bit 2 - Channel 2 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr2(&mut self) -> OVR2_W { + OVR2_W { w: self } + } + #[doc = "Bit 3 - Channel 3 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr3(&mut self) -> OVR3_W { + OVR3_W { w: self } + } + #[doc = "Bit 4 - Channel 4 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr4(&mut self) -> OVR4_W { + OVR4_W { w: self } + } + #[doc = "Bit 5 - Channel 5 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr5(&mut self) -> OVR5_W { + OVR5_W { w: self } + } + #[doc = "Bit 6 - Channel 6 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr6(&mut self) -> OVR6_W { + OVR6_W { w: self } + } + #[doc = "Bit 7 - Channel 7 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr7(&mut self) -> OVR7_W { + OVR7_W { w: self } + } + #[doc = "Bit 8 - Channel 8 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr8(&mut self) -> OVR8_W { + OVR8_W { w: self } + } + #[doc = "Bit 9 - Channel 9 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr9(&mut self) -> OVR9_W { + OVR9_W { w: self } + } + #[doc = "Bit 10 - Channel 10 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr10(&mut self) -> OVR10_W { + OVR10_W { w: self } + } + #[doc = "Bit 11 - Channel 11 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr11(&mut self) -> OVR11_W { + OVR11_W { w: self } + } + #[doc = "Bit 16 - Channel 0 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd0(&mut self) -> EVD0_W { + EVD0_W { w: self } + } + #[doc = "Bit 17 - Channel 1 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd1(&mut self) -> EVD1_W { + EVD1_W { w: self } + } + #[doc = "Bit 18 - Channel 2 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd2(&mut self) -> EVD2_W { + EVD2_W { w: self } + } + #[doc = "Bit 19 - Channel 3 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd3(&mut self) -> EVD3_W { + EVD3_W { w: self } + } + #[doc = "Bit 20 - Channel 4 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd4(&mut self) -> EVD4_W { + EVD4_W { w: self } + } + #[doc = "Bit 21 - Channel 5 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd5(&mut self) -> EVD5_W { + EVD5_W { w: self } + } + #[doc = "Bit 22 - Channel 6 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd6(&mut self) -> EVD6_W { + EVD6_W { w: self } + } + #[doc = "Bit 23 - Channel 7 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd7(&mut self) -> EVD7_W { + EVD7_W { w: self } + } + #[doc = "Bit 24 - Channel 8 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd8(&mut self) -> EVD8_W { + EVD8_W { w: self } + } + #[doc = "Bit 25 - Channel 9 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd9(&mut self) -> EVD9_W { + EVD9_W { w: self } + } + #[doc = "Bit 26 - Channel 10 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd10(&mut self) -> EVD10_W { + EVD10_W { w: self } + } + #[doc = "Bit 27 - Channel 11 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd11(&mut self) -> EVD11_W { + EVD11_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/evsys/intflag.rs b/pac/atsamc21n/src/evsys/intflag.rs new file mode 100644 index 000000000000..4d5cbe3950f6 --- /dev/null +++ b/pac/atsamc21n/src/evsys/intflag.rs @@ -0,0 +1,1194 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVR0` reader - Channel 0 Overrun"] +pub struct OVR0_R(crate::FieldReader); +impl OVR0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR0` writer - Channel 0 Overrun"] +pub struct OVR0_W<'a> { + w: &'a mut W, +} +impl<'a> OVR0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `OVR1` reader - Channel 1 Overrun"] +pub struct OVR1_R(crate::FieldReader); +impl OVR1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR1` writer - Channel 1 Overrun"] +pub struct OVR1_W<'a> { + w: &'a mut W, +} +impl<'a> OVR1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `OVR2` reader - Channel 2 Overrun"] +pub struct OVR2_R(crate::FieldReader); +impl OVR2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR2` writer - Channel 2 Overrun"] +pub struct OVR2_W<'a> { + w: &'a mut W, +} +impl<'a> OVR2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `OVR3` reader - Channel 3 Overrun"] +pub struct OVR3_R(crate::FieldReader); +impl OVR3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR3` writer - Channel 3 Overrun"] +pub struct OVR3_W<'a> { + w: &'a mut W, +} +impl<'a> OVR3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `OVR4` reader - Channel 4 Overrun"] +pub struct OVR4_R(crate::FieldReader); +impl OVR4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR4` writer - Channel 4 Overrun"] +pub struct OVR4_W<'a> { + w: &'a mut W, +} +impl<'a> OVR4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `OVR5` reader - Channel 5 Overrun"] +pub struct OVR5_R(crate::FieldReader); +impl OVR5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR5` writer - Channel 5 Overrun"] +pub struct OVR5_W<'a> { + w: &'a mut W, +} +impl<'a> OVR5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `OVR6` reader - Channel 6 Overrun"] +pub struct OVR6_R(crate::FieldReader); +impl OVR6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR6` writer - Channel 6 Overrun"] +pub struct OVR6_W<'a> { + w: &'a mut W, +} +impl<'a> OVR6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `OVR7` reader - Channel 7 Overrun"] +pub struct OVR7_R(crate::FieldReader); +impl OVR7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR7` writer - Channel 7 Overrun"] +pub struct OVR7_W<'a> { + w: &'a mut W, +} +impl<'a> OVR7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `OVR8` reader - Channel 8 Overrun"] +pub struct OVR8_R(crate::FieldReader); +impl OVR8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR8` writer - Channel 8 Overrun"] +pub struct OVR8_W<'a> { + w: &'a mut W, +} +impl<'a> OVR8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `OVR9` reader - Channel 9 Overrun"] +pub struct OVR9_R(crate::FieldReader); +impl OVR9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR9` writer - Channel 9 Overrun"] +pub struct OVR9_W<'a> { + w: &'a mut W, +} +impl<'a> OVR9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `OVR10` reader - Channel 10 Overrun"] +pub struct OVR10_R(crate::FieldReader); +impl OVR10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR10` writer - Channel 10 Overrun"] +pub struct OVR10_W<'a> { + w: &'a mut W, +} +impl<'a> OVR10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `OVR11` reader - Channel 11 Overrun"] +pub struct OVR11_R(crate::FieldReader); +impl OVR11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVR11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVR11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVR11` writer - Channel 11 Overrun"] +pub struct OVR11_W<'a> { + w: &'a mut W, +} +impl<'a> OVR11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `EVD0` reader - Channel 0 Event Detection"] +pub struct EVD0_R(crate::FieldReader); +impl EVD0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD0` writer - Channel 0 Event Detection"] +pub struct EVD0_W<'a> { + w: &'a mut W, +} +impl<'a> EVD0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `EVD1` reader - Channel 1 Event Detection"] +pub struct EVD1_R(crate::FieldReader); +impl EVD1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD1` writer - Channel 1 Event Detection"] +pub struct EVD1_W<'a> { + w: &'a mut W, +} +impl<'a> EVD1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `EVD2` reader - Channel 2 Event Detection"] +pub struct EVD2_R(crate::FieldReader); +impl EVD2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD2` writer - Channel 2 Event Detection"] +pub struct EVD2_W<'a> { + w: &'a mut W, +} +impl<'a> EVD2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `EVD3` reader - Channel 3 Event Detection"] +pub struct EVD3_R(crate::FieldReader); +impl EVD3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD3` writer - Channel 3 Event Detection"] +pub struct EVD3_W<'a> { + w: &'a mut W, +} +impl<'a> EVD3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `EVD4` reader - Channel 4 Event Detection"] +pub struct EVD4_R(crate::FieldReader); +impl EVD4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD4` writer - Channel 4 Event Detection"] +pub struct EVD4_W<'a> { + w: &'a mut W, +} +impl<'a> EVD4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `EVD5` reader - Channel 5 Event Detection"] +pub struct EVD5_R(crate::FieldReader); +impl EVD5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD5` writer - Channel 5 Event Detection"] +pub struct EVD5_W<'a> { + w: &'a mut W, +} +impl<'a> EVD5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `EVD6` reader - Channel 6 Event Detection"] +pub struct EVD6_R(crate::FieldReader); +impl EVD6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD6` writer - Channel 6 Event Detection"] +pub struct EVD6_W<'a> { + w: &'a mut W, +} +impl<'a> EVD6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `EVD7` reader - Channel 7 Event Detection"] +pub struct EVD7_R(crate::FieldReader); +impl EVD7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD7` writer - Channel 7 Event Detection"] +pub struct EVD7_W<'a> { + w: &'a mut W, +} +impl<'a> EVD7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `EVD8` reader - Channel 8 Event Detection"] +pub struct EVD8_R(crate::FieldReader); +impl EVD8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD8` writer - Channel 8 Event Detection"] +pub struct EVD8_W<'a> { + w: &'a mut W, +} +impl<'a> EVD8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `EVD9` reader - Channel 9 Event Detection"] +pub struct EVD9_R(crate::FieldReader); +impl EVD9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD9` writer - Channel 9 Event Detection"] +pub struct EVD9_W<'a> { + w: &'a mut W, +} +impl<'a> EVD9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `EVD10` reader - Channel 10 Event Detection"] +pub struct EVD10_R(crate::FieldReader); +impl EVD10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD10` writer - Channel 10 Event Detection"] +pub struct EVD10_W<'a> { + w: &'a mut W, +} +impl<'a> EVD10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `EVD11` reader - Channel 11 Event Detection"] +pub struct EVD11_R(crate::FieldReader); +impl EVD11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVD11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVD11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVD11` writer - Channel 11 Event Detection"] +pub struct EVD11_W<'a> { + w: &'a mut W, +} +impl<'a> EVD11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +impl R { + #[doc = "Bit 0 - Channel 0 Overrun"] + #[inline(always)] + pub fn ovr0(&self) -> OVR0_R { + OVR0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel 1 Overrun"] + #[inline(always)] + pub fn ovr1(&self) -> OVR1_R { + OVR1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel 2 Overrun"] + #[inline(always)] + pub fn ovr2(&self) -> OVR2_R { + OVR2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Channel 3 Overrun"] + #[inline(always)] + pub fn ovr3(&self) -> OVR3_R { + OVR3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Channel 4 Overrun"] + #[inline(always)] + pub fn ovr4(&self) -> OVR4_R { + OVR4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Channel 5 Overrun"] + #[inline(always)] + pub fn ovr5(&self) -> OVR5_R { + OVR5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Channel 6 Overrun"] + #[inline(always)] + pub fn ovr6(&self) -> OVR6_R { + OVR6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Channel 7 Overrun"] + #[inline(always)] + pub fn ovr7(&self) -> OVR7_R { + OVR7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Channel 8 Overrun"] + #[inline(always)] + pub fn ovr8(&self) -> OVR8_R { + OVR8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Channel 9 Overrun"] + #[inline(always)] + pub fn ovr9(&self) -> OVR9_R { + OVR9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Channel 10 Overrun"] + #[inline(always)] + pub fn ovr10(&self) -> OVR10_R { + OVR10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Channel 11 Overrun"] + #[inline(always)] + pub fn ovr11(&self) -> OVR11_R { + OVR11_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 16 - Channel 0 Event Detection"] + #[inline(always)] + pub fn evd0(&self) -> EVD0_R { + EVD0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Channel 1 Event Detection"] + #[inline(always)] + pub fn evd1(&self) -> EVD1_R { + EVD1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Channel 2 Event Detection"] + #[inline(always)] + pub fn evd2(&self) -> EVD2_R { + EVD2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Channel 3 Event Detection"] + #[inline(always)] + pub fn evd3(&self) -> EVD3_R { + EVD3_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Channel 4 Event Detection"] + #[inline(always)] + pub fn evd4(&self) -> EVD4_R { + EVD4_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Channel 5 Event Detection"] + #[inline(always)] + pub fn evd5(&self) -> EVD5_R { + EVD5_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Channel 6 Event Detection"] + #[inline(always)] + pub fn evd6(&self) -> EVD6_R { + EVD6_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Channel 7 Event Detection"] + #[inline(always)] + pub fn evd7(&self) -> EVD7_R { + EVD7_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24 - Channel 8 Event Detection"] + #[inline(always)] + pub fn evd8(&self) -> EVD8_R { + EVD8_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Channel 9 Event Detection"] + #[inline(always)] + pub fn evd9(&self) -> EVD9_R { + EVD9_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Channel 10 Event Detection"] + #[inline(always)] + pub fn evd10(&self) -> EVD10_R { + EVD10_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Channel 11 Event Detection"] + #[inline(always)] + pub fn evd11(&self) -> EVD11_R { + EVD11_R::new(((self.bits >> 27) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel 0 Overrun"] + #[inline(always)] + pub fn ovr0(&mut self) -> OVR0_W { + OVR0_W { w: self } + } + #[doc = "Bit 1 - Channel 1 Overrun"] + #[inline(always)] + pub fn ovr1(&mut self) -> OVR1_W { + OVR1_W { w: self } + } + #[doc = "Bit 2 - Channel 2 Overrun"] + #[inline(always)] + pub fn ovr2(&mut self) -> OVR2_W { + OVR2_W { w: self } + } + #[doc = "Bit 3 - Channel 3 Overrun"] + #[inline(always)] + pub fn ovr3(&mut self) -> OVR3_W { + OVR3_W { w: self } + } + #[doc = "Bit 4 - Channel 4 Overrun"] + #[inline(always)] + pub fn ovr4(&mut self) -> OVR4_W { + OVR4_W { w: self } + } + #[doc = "Bit 5 - Channel 5 Overrun"] + #[inline(always)] + pub fn ovr5(&mut self) -> OVR5_W { + OVR5_W { w: self } + } + #[doc = "Bit 6 - Channel 6 Overrun"] + #[inline(always)] + pub fn ovr6(&mut self) -> OVR6_W { + OVR6_W { w: self } + } + #[doc = "Bit 7 - Channel 7 Overrun"] + #[inline(always)] + pub fn ovr7(&mut self) -> OVR7_W { + OVR7_W { w: self } + } + #[doc = "Bit 8 - Channel 8 Overrun"] + #[inline(always)] + pub fn ovr8(&mut self) -> OVR8_W { + OVR8_W { w: self } + } + #[doc = "Bit 9 - Channel 9 Overrun"] + #[inline(always)] + pub fn ovr9(&mut self) -> OVR9_W { + OVR9_W { w: self } + } + #[doc = "Bit 10 - Channel 10 Overrun"] + #[inline(always)] + pub fn ovr10(&mut self) -> OVR10_W { + OVR10_W { w: self } + } + #[doc = "Bit 11 - Channel 11 Overrun"] + #[inline(always)] + pub fn ovr11(&mut self) -> OVR11_W { + OVR11_W { w: self } + } + #[doc = "Bit 16 - Channel 0 Event Detection"] + #[inline(always)] + pub fn evd0(&mut self) -> EVD0_W { + EVD0_W { w: self } + } + #[doc = "Bit 17 - Channel 1 Event Detection"] + #[inline(always)] + pub fn evd1(&mut self) -> EVD1_W { + EVD1_W { w: self } + } + #[doc = "Bit 18 - Channel 2 Event Detection"] + #[inline(always)] + pub fn evd2(&mut self) -> EVD2_W { + EVD2_W { w: self } + } + #[doc = "Bit 19 - Channel 3 Event Detection"] + #[inline(always)] + pub fn evd3(&mut self) -> EVD3_W { + EVD3_W { w: self } + } + #[doc = "Bit 20 - Channel 4 Event Detection"] + #[inline(always)] + pub fn evd4(&mut self) -> EVD4_W { + EVD4_W { w: self } + } + #[doc = "Bit 21 - Channel 5 Event Detection"] + #[inline(always)] + pub fn evd5(&mut self) -> EVD5_W { + EVD5_W { w: self } + } + #[doc = "Bit 22 - Channel 6 Event Detection"] + #[inline(always)] + pub fn evd6(&mut self) -> EVD6_W { + EVD6_W { w: self } + } + #[doc = "Bit 23 - Channel 7 Event Detection"] + #[inline(always)] + pub fn evd7(&mut self) -> EVD7_W { + EVD7_W { w: self } + } + #[doc = "Bit 24 - Channel 8 Event Detection"] + #[inline(always)] + pub fn evd8(&mut self) -> EVD8_W { + EVD8_W { w: self } + } + #[doc = "Bit 25 - Channel 9 Event Detection"] + #[inline(always)] + pub fn evd9(&mut self) -> EVD9_W { + EVD9_W { w: self } + } + #[doc = "Bit 26 - Channel 10 Event Detection"] + #[inline(always)] + pub fn evd10(&mut self) -> EVD10_W { + EVD10_W { w: self } + } + #[doc = "Bit 27 - Channel 11 Event Detection"] + #[inline(always)] + pub fn evd11(&mut self) -> EVD11_W { + EVD11_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/evsys/swevt.rs b/pac/atsamc21n/src/evsys/swevt.rs new file mode 100644 index 000000000000..df58fe290de2 --- /dev/null +++ b/pac/atsamc21n/src/evsys/swevt.rs @@ -0,0 +1,369 @@ +#[doc = "Register `SWEVT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHANNEL0` writer - Channel 0 Software Selection"] +pub struct CHANNEL0_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `CHANNEL1` writer - Channel 1 Software Selection"] +pub struct CHANNEL1_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CHANNEL2` writer - Channel 2 Software Selection"] +pub struct CHANNEL2_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CHANNEL3` writer - Channel 3 Software Selection"] +pub struct CHANNEL3_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CHANNEL4` writer - Channel 4 Software Selection"] +pub struct CHANNEL4_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `CHANNEL5` writer - Channel 5 Software Selection"] +pub struct CHANNEL5_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `CHANNEL6` writer - Channel 6 Software Selection"] +pub struct CHANNEL6_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `CHANNEL7` writer - Channel 7 Software Selection"] +pub struct CHANNEL7_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CHANNEL8` writer - Channel 8 Software Selection"] +pub struct CHANNEL8_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `CHANNEL9` writer - Channel 9 Software Selection"] +pub struct CHANNEL9_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `CHANNEL10` writer - Channel 10 Software Selection"] +pub struct CHANNEL10_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `CHANNEL11` writer - Channel 11 Software Selection"] +pub struct CHANNEL11_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +impl W { + #[doc = "Bit 0 - Channel 0 Software Selection"] + #[inline(always)] + pub fn channel0(&mut self) -> CHANNEL0_W { + CHANNEL0_W { w: self } + } + #[doc = "Bit 1 - Channel 1 Software Selection"] + #[inline(always)] + pub fn channel1(&mut self) -> CHANNEL1_W { + CHANNEL1_W { w: self } + } + #[doc = "Bit 2 - Channel 2 Software Selection"] + #[inline(always)] + pub fn channel2(&mut self) -> CHANNEL2_W { + CHANNEL2_W { w: self } + } + #[doc = "Bit 3 - Channel 3 Software Selection"] + #[inline(always)] + pub fn channel3(&mut self) -> CHANNEL3_W { + CHANNEL3_W { w: self } + } + #[doc = "Bit 4 - Channel 4 Software Selection"] + #[inline(always)] + pub fn channel4(&mut self) -> CHANNEL4_W { + CHANNEL4_W { w: self } + } + #[doc = "Bit 5 - Channel 5 Software Selection"] + #[inline(always)] + pub fn channel5(&mut self) -> CHANNEL5_W { + CHANNEL5_W { w: self } + } + #[doc = "Bit 6 - Channel 6 Software Selection"] + #[inline(always)] + pub fn channel6(&mut self) -> CHANNEL6_W { + CHANNEL6_W { w: self } + } + #[doc = "Bit 7 - Channel 7 Software Selection"] + #[inline(always)] + pub fn channel7(&mut self) -> CHANNEL7_W { + CHANNEL7_W { w: self } + } + #[doc = "Bit 8 - Channel 8 Software Selection"] + #[inline(always)] + pub fn channel8(&mut self) -> CHANNEL8_W { + CHANNEL8_W { w: self } + } + #[doc = "Bit 9 - Channel 9 Software Selection"] + #[inline(always)] + pub fn channel9(&mut self) -> CHANNEL9_W { + CHANNEL9_W { w: self } + } + #[doc = "Bit 10 - Channel 10 Software Selection"] + #[inline(always)] + pub fn channel10(&mut self) -> CHANNEL10_W { + CHANNEL10_W { w: self } + } + #[doc = "Bit 11 - Channel 11 Software Selection"] + #[inline(always)] + pub fn channel11(&mut self) -> CHANNEL11_W { + CHANNEL11_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Software Event\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [swevt](index.html) module"] +pub struct SWEVT_SPEC; +impl crate::RegisterSpec for SWEVT_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [swevt::W](W) writer structure"] +impl crate::Writable for SWEVT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SWEVT to value 0"] +impl crate::Resettable for SWEVT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/evsys/user.rs b/pac/atsamc21n/src/evsys/user.rs new file mode 100644 index 000000000000..848f9f599b79 --- /dev/null +++ b/pac/atsamc21n/src/evsys/user.rs @@ -0,0 +1,104 @@ +#[doc = "Register `USER[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `USER[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHANNEL` reader - Channel Event Selection"] +pub struct CHANNEL_R(crate::FieldReader); +impl CHANNEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CHANNEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHANNEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHANNEL` writer - Channel Event Selection"] +pub struct CHANNEL_W<'a> { + w: &'a mut W, +} +impl<'a> CHANNEL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Channel Event Selection"] + #[inline(always)] + pub fn channel(&self) -> CHANNEL_R { + CHANNEL_R::new((self.bits & 0x1f) as u8) + } +} +impl W { + #[doc = "Bits 0:4 - Channel Event Selection"] + #[inline(always)] + pub fn channel(&mut self) -> CHANNEL_W { + CHANNEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "User Multiplexer n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [user](index.html) module"] +pub struct USER_SPEC; +impl crate::RegisterSpec for USER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [user::R](R) reader structure"] +impl crate::Readable for USER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [user::W](W) writer structure"] +impl crate::Writable for USER_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets USER[%s] +to value 0"] +impl crate::Resettable for USER_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/freqm.rs b/pac/atsamc21n/src/freqm.rs new file mode 100644 index 000000000000..f0fc6fda975e --- /dev/null +++ b/pac/atsamc21n/src/freqm.rs @@ -0,0 +1,59 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control A Register"] + pub ctrla: crate::Reg, + #[doc = "0x01 - Control B Register"] + pub ctrlb: crate::Reg, + #[doc = "0x02 - Config A register"] + pub cfga: crate::Reg, + _reserved3: [u8; 0x04], + #[doc = "0x08 - Interrupt Enable Clear Register"] + pub intenclr: crate::Reg, + #[doc = "0x09 - Interrupt Enable Set Register"] + pub intenset: crate::Reg, + #[doc = "0x0a - Interrupt Flag Register"] + pub intflag: crate::Reg, + #[doc = "0x0b - Status Register"] + pub status: crate::Reg, + #[doc = "0x0c - Synchronization Busy Register"] + pub syncbusy: crate::Reg, + #[doc = "0x10 - Count Value Register"] + pub value: crate::Reg, +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A Register"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "Control B Register"] +pub mod ctrlb; +#[doc = "CFGA register accessor: an alias for `Reg`"] +pub type CFGA = crate::Reg; +#[doc = "Config A register"] +pub mod cfga; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear Register"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set Register"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Register"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status Register"] +pub mod status; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Busy Register"] +pub mod syncbusy; +#[doc = "VALUE register accessor: an alias for `Reg`"] +pub type VALUE = crate::Reg; +#[doc = "Count Value Register"] +pub mod value; diff --git a/pac/atsamc21n/src/freqm/cfga.rs b/pac/atsamc21n/src/freqm/cfga.rs new file mode 100644 index 000000000000..a63cf01f0b96 --- /dev/null +++ b/pac/atsamc21n/src/freqm/cfga.rs @@ -0,0 +1,150 @@ +#[doc = "Register `CFGA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CFGA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `REFNUM` reader - Number of Reference Clock Cycles"] +pub struct REFNUM_R(crate::FieldReader); +impl REFNUM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REFNUM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REFNUM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REFNUM` writer - Number of Reference Clock Cycles"] +pub struct REFNUM_W<'a> { + w: &'a mut W, +} +impl<'a> REFNUM_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u16 & 0xff); + self.w + } +} +#[doc = "Field `DIVREF` reader - Divide Reference Clock"] +pub struct DIVREF_R(crate::FieldReader); +impl DIVREF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIVREF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIVREF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIVREF` writer - Divide Reference Clock"] +pub struct DIVREF_W<'a> { + w: &'a mut W, +} +impl<'a> DIVREF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Number of Reference Clock Cycles"] + #[inline(always)] + pub fn refnum(&self) -> REFNUM_R { + REFNUM_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 15 - Divide Reference Clock"] + #[inline(always)] + pub fn divref(&self) -> DIVREF_R { + DIVREF_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - Number of Reference Clock Cycles"] + #[inline(always)] + pub fn refnum(&mut self) -> REFNUM_W { + REFNUM_W { w: self } + } + #[doc = "Bit 15 - Divide Reference Clock"] + #[inline(always)] + pub fn divref(&mut self) -> DIVREF_W { + DIVREF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Config A register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cfga](index.html) module"] +pub struct CFGA_SPEC; +impl crate::RegisterSpec for CFGA_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [cfga::R](R) reader structure"] +impl crate::Readable for CFGA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cfga::W](W) writer structure"] +impl crate::Writable for CFGA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CFGA to value 0"] +impl crate::Resettable for CFGA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/freqm/ctrla.rs b/pac/atsamc21n/src/freqm/ctrla.rs new file mode 100644 index 000000000000..b2cefdd45770 --- /dev/null +++ b/pac/atsamc21n/src/freqm/ctrla.rs @@ -0,0 +1,160 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/freqm/ctrlb.rs b/pac/atsamc21n/src/freqm/ctrlb.rs new file mode 100644 index 000000000000..7d350e71fbf3 --- /dev/null +++ b/pac/atsamc21n/src/freqm/ctrlb.rs @@ -0,0 +1,72 @@ +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `START` writer - Start Measurement"] +pub struct START_W<'a> { + w: &'a mut W, +} +impl<'a> START_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0 - Start Measurement"] + #[inline(always)] + pub fn start(&mut self) -> START_W { + START_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u8; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/freqm/intenclr.rs b/pac/atsamc21n/src/freqm/intenclr.rs new file mode 100644 index 000000000000..a224aa5500f6 --- /dev/null +++ b/pac/atsamc21n/src/freqm/intenclr.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DONE` reader - Measurement Done Interrupt Enable"] +pub struct DONE_R(crate::FieldReader); +impl DONE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DONE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DONE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DONE` writer - Measurement Done Interrupt Enable"] +pub struct DONE_W<'a> { + w: &'a mut W, +} +impl<'a> DONE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Measurement Done Interrupt Enable"] + #[inline(always)] + pub fn done(&self) -> DONE_R { + DONE_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Measurement Done Interrupt Enable"] + #[inline(always)] + pub fn done(&mut self) -> DONE_W { + DONE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/freqm/intenset.rs b/pac/atsamc21n/src/freqm/intenset.rs new file mode 100644 index 000000000000..53b3d0bef7c0 --- /dev/null +++ b/pac/atsamc21n/src/freqm/intenset.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DONE` reader - Measurement Done Interrupt Enable"] +pub struct DONE_R(crate::FieldReader); +impl DONE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DONE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DONE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DONE` writer - Measurement Done Interrupt Enable"] +pub struct DONE_W<'a> { + w: &'a mut W, +} +impl<'a> DONE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Measurement Done Interrupt Enable"] + #[inline(always)] + pub fn done(&self) -> DONE_R { + DONE_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Measurement Done Interrupt Enable"] + #[inline(always)] + pub fn done(&mut self) -> DONE_W { + DONE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/freqm/intflag.rs b/pac/atsamc21n/src/freqm/intflag.rs new file mode 100644 index 000000000000..3b8fdab47703 --- /dev/null +++ b/pac/atsamc21n/src/freqm/intflag.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DONE` reader - Measurement Done"] +pub struct DONE_R(crate::FieldReader); +impl DONE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DONE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DONE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DONE` writer - Measurement Done"] +pub struct DONE_W<'a> { + w: &'a mut W, +} +impl<'a> DONE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Measurement Done"] + #[inline(always)] + pub fn done(&self) -> DONE_R { + DONE_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Measurement Done"] + #[inline(always)] + pub fn done(&mut self) -> DONE_W { + DONE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/freqm/status.rs b/pac/atsamc21n/src/freqm/status.rs new file mode 100644 index 000000000000..8a81662f51b0 --- /dev/null +++ b/pac/atsamc21n/src/freqm/status.rs @@ -0,0 +1,160 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BUSY` reader - FREQM Status"] +pub struct BUSY_R(crate::FieldReader); +impl BUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSY` writer - FREQM Status"] +pub struct BUSY_W<'a> { + w: &'a mut W, +} +impl<'a> BUSY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `OVF` reader - Sticky Count Value Overflow"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Sticky Count Value Overflow"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - FREQM Status"] + #[inline(always)] + pub fn busy(&self) -> BUSY_R { + BUSY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Sticky Count Value Overflow"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - FREQM Status"] + #[inline(always)] + pub fn busy(&mut self) -> BUSY_W { + BUSY_W { w: self } + } + #[doc = "Bit 1 - Sticky Count Value Overflow"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/freqm/syncbusy.rs b/pac/atsamc21n/src/freqm/syncbusy.rs new file mode 100644 index 000000000000..54396368e817 --- /dev/null +++ b/pac/atsamc21n/src/freqm/syncbusy.rs @@ -0,0 +1,73 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +#[doc = "Synchronization Busy Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/freqm/value.rs b/pac/atsamc21n/src/freqm/value.rs new file mode 100644 index 000000000000..5b0f5dfd9b67 --- /dev/null +++ b/pac/atsamc21n/src/freqm/value.rs @@ -0,0 +1,53 @@ +#[doc = "Register `VALUE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `VALUE` reader - Measurement Value"] +pub struct VALUE_R(crate::FieldReader); +impl VALUE_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + VALUE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VALUE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:23 - Measurement Value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +#[doc = "Count Value Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [value](index.html) module"] +pub struct VALUE_SPEC; +impl crate::RegisterSpec for VALUE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [value::R](R) reader structure"] +impl crate::Readable for VALUE_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets VALUE to value 0"] +impl crate::Resettable for VALUE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/gclk.rs b/pac/atsamc21n/src/gclk.rs new file mode 100644 index 000000000000..b91b638be958 --- /dev/null +++ b/pac/atsamc21n/src/gclk.rs @@ -0,0 +1,31 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrla: crate::Reg, + _reserved1: [u8; 0x03], + #[doc = "0x04 - Synchronization Busy"] + pub syncbusy: crate::Reg, + _reserved2: [u8; 0x18], + #[doc = "0x20..0x44 - Generic Clock Generator Control"] + pub genctrl: [crate::Reg; 9], + _reserved3: [u8; 0x3c], + #[doc = "0x80..0x138 - Peripheral Clock Control"] + pub pchctrl: [crate::Reg; 46], +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control"] +pub mod ctrla; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Busy"] +pub mod syncbusy; +#[doc = "GENCTRL register accessor: an alias for `Reg`"] +pub type GENCTRL = crate::Reg; +#[doc = "Generic Clock Generator Control"] +pub mod genctrl; +#[doc = "PCHCTRL register accessor: an alias for `Reg`"] +pub type PCHCTRL = crate::Reg; +#[doc = "Peripheral Clock Control"] +pub mod pchctrl; diff --git a/pac/atsamc21n/src/gclk/ctrla.rs b/pac/atsamc21n/src/gclk/ctrla.rs new file mode 100644 index 000000000000..1c24704395ad --- /dev/null +++ b/pac/atsamc21n/src/gclk/ctrla.rs @@ -0,0 +1,113 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/gclk/genctrl.rs b/pac/atsamc21n/src/gclk/genctrl.rs new file mode 100644 index 000000000000..052b2915ca7f --- /dev/null +++ b/pac/atsamc21n/src/gclk/genctrl.rs @@ -0,0 +1,597 @@ +#[doc = "Register `GENCTRL[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GENCTRL[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Source Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SRC_A { + #[doc = "0: XOSC oscillator output"] + XOSC = 0, + #[doc = "1: Generator input pad"] + GCLKIN = 1, + #[doc = "2: Generic clock generator 1 output"] + GCLKGEN1 = 2, + #[doc = "3: OSCULP32K oscillator output"] + OSCULP32K = 3, + #[doc = "4: OSC32K oscillator output"] + OSC32K = 4, + #[doc = "5: XOSC32K oscillator output"] + XOSC32K = 5, + #[doc = "6: OSC48M oscillator output"] + OSC48M = 6, + #[doc = "7: DPLL96M output"] + DPLL96M = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SRC_A) -> Self { + variant as _ + } +} +#[doc = "Field `SRC` reader - Source Select"] +pub struct SRC_R(crate::FieldReader); +impl SRC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SRC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SRC_A { + match self.bits { + 0 => SRC_A::XOSC, + 1 => SRC_A::GCLKIN, + 2 => SRC_A::GCLKGEN1, + 3 => SRC_A::OSCULP32K, + 4 => SRC_A::OSC32K, + 5 => SRC_A::XOSC32K, + 6 => SRC_A::OSC48M, + 7 => SRC_A::DPLL96M, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `XOSC`"] + #[inline(always)] + pub fn is_xosc(&self) -> bool { + **self == SRC_A::XOSC + } + #[doc = "Checks if the value of the field is `GCLKIN`"] + #[inline(always)] + pub fn is_gclkin(&self) -> bool { + **self == SRC_A::GCLKIN + } + #[doc = "Checks if the value of the field is `GCLKGEN1`"] + #[inline(always)] + pub fn is_gclkgen1(&self) -> bool { + **self == SRC_A::GCLKGEN1 + } + #[doc = "Checks if the value of the field is `OSCULP32K`"] + #[inline(always)] + pub fn is_osculp32k(&self) -> bool { + **self == SRC_A::OSCULP32K + } + #[doc = "Checks if the value of the field is `OSC32K`"] + #[inline(always)] + pub fn is_osc32k(&self) -> bool { + **self == SRC_A::OSC32K + } + #[doc = "Checks if the value of the field is `XOSC32K`"] + #[inline(always)] + pub fn is_xosc32k(&self) -> bool { + **self == SRC_A::XOSC32K + } + #[doc = "Checks if the value of the field is `OSC48M`"] + #[inline(always)] + pub fn is_osc48m(&self) -> bool { + **self == SRC_A::OSC48M + } + #[doc = "Checks if the value of the field is `DPLL96M`"] + #[inline(always)] + pub fn is_dpll96m(&self) -> bool { + **self == SRC_A::DPLL96M + } +} +impl core::ops::Deref for SRC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SRC` writer - Source Select"] +pub struct SRC_W<'a> { + w: &'a mut W, +} +impl<'a> SRC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SRC_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "XOSC oscillator output"] + #[inline(always)] + pub fn xosc(self) -> &'a mut W { + self.variant(SRC_A::XOSC) + } + #[doc = "Generator input pad"] + #[inline(always)] + pub fn gclkin(self) -> &'a mut W { + self.variant(SRC_A::GCLKIN) + } + #[doc = "Generic clock generator 1 output"] + #[inline(always)] + pub fn gclkgen1(self) -> &'a mut W { + self.variant(SRC_A::GCLKGEN1) + } + #[doc = "OSCULP32K oscillator output"] + #[inline(always)] + pub fn osculp32k(self) -> &'a mut W { + self.variant(SRC_A::OSCULP32K) + } + #[doc = "OSC32K oscillator output"] + #[inline(always)] + pub fn osc32k(self) -> &'a mut W { + self.variant(SRC_A::OSC32K) + } + #[doc = "XOSC32K oscillator output"] + #[inline(always)] + pub fn xosc32k(self) -> &'a mut W { + self.variant(SRC_A::XOSC32K) + } + #[doc = "OSC48M oscillator output"] + #[inline(always)] + pub fn osc48m(self) -> &'a mut W { + self.variant(SRC_A::OSC48M) + } + #[doc = "DPLL96M output"] + #[inline(always)] + pub fn dpll96m(self) -> &'a mut W { + self.variant(SRC_A::DPLL96M) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Field `GENEN` reader - Generic Clock Generator Enable"] +pub struct GENEN_R(crate::FieldReader); +impl GENEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENEN` writer - Generic Clock Generator Enable"] +pub struct GENEN_W<'a> { + w: &'a mut W, +} +impl<'a> GENEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `IDC` reader - Improve Duty Cycle"] +pub struct IDC_R(crate::FieldReader); +impl IDC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IDC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IDC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IDC` writer - Improve Duty Cycle"] +pub struct IDC_W<'a> { + w: &'a mut W, +} +impl<'a> IDC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `OOV` reader - Output Off Value"] +pub struct OOV_R(crate::FieldReader); +impl OOV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OOV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OOV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OOV` writer - Output Off Value"] +pub struct OOV_W<'a> { + w: &'a mut W, +} +impl<'a> OOV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `OE` reader - Output Enable"] +pub struct OE_R(crate::FieldReader); +impl OE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OE` writer - Output Enable"] +pub struct OE_W<'a> { + w: &'a mut W, +} +impl<'a> OE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Divide Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum DIVSEL_A { + #[doc = "0: Divide input directly by divider factor"] + DIV1 = 0, + #[doc = "1: Divide input by 2^(divider factor+ 1)"] + DIV2 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DIVSEL_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DIVSEL` reader - Divide Selection"] +pub struct DIVSEL_R(crate::FieldReader); +impl DIVSEL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIVSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DIVSEL_A { + match self.bits { + false => DIVSEL_A::DIV1, + true => DIVSEL_A::DIV2, + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == DIVSEL_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == DIVSEL_A::DIV2 + } +} +impl core::ops::Deref for DIVSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIVSEL` writer - Divide Selection"] +pub struct DIVSEL_W<'a> { + w: &'a mut W, +} +impl<'a> DIVSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DIVSEL_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Divide input directly by divider factor"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(DIVSEL_A::DIV1) + } + #[doc = "Divide input by 2^(divider factor+ 1)"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(DIVSEL_A::DIV2) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `DIV` reader - Division Factor"] +pub struct DIV_R(crate::FieldReader); +impl DIV_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + DIV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIV` writer - Division Factor"] +pub struct DIV_W<'a> { + w: &'a mut W, +} +impl<'a> DIV_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xffff << 16)) | ((value as u32 & 0xffff) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Source Select"] + #[inline(always)] + pub fn src(&self) -> SRC_R { + SRC_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 8 - Generic Clock Generator Enable"] + #[inline(always)] + pub fn genen(&self) -> GENEN_R { + GENEN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Improve Duty Cycle"] + #[inline(always)] + pub fn idc(&self) -> IDC_R { + IDC_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Output Off Value"] + #[inline(always)] + pub fn oov(&self) -> OOV_R { + OOV_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Output Enable"] + #[inline(always)] + pub fn oe(&self) -> OE_R { + OE_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Divide Selection"] + #[inline(always)] + pub fn divsel(&self) -> DIVSEL_R { + DIVSEL_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bits 16:31 - Division Factor"] + #[inline(always)] + pub fn div(&self) -> DIV_R { + DIV_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:2 - Source Select"] + #[inline(always)] + pub fn src(&mut self) -> SRC_W { + SRC_W { w: self } + } + #[doc = "Bit 8 - Generic Clock Generator Enable"] + #[inline(always)] + pub fn genen(&mut self) -> GENEN_W { + GENEN_W { w: self } + } + #[doc = "Bit 9 - Improve Duty Cycle"] + #[inline(always)] + pub fn idc(&mut self) -> IDC_W { + IDC_W { w: self } + } + #[doc = "Bit 10 - Output Off Value"] + #[inline(always)] + pub fn oov(&mut self) -> OOV_W { + OOV_W { w: self } + } + #[doc = "Bit 11 - Output Enable"] + #[inline(always)] + pub fn oe(&mut self) -> OE_W { + OE_W { w: self } + } + #[doc = "Bit 12 - Divide Selection"] + #[inline(always)] + pub fn divsel(&mut self) -> DIVSEL_W { + DIVSEL_W { w: self } + } + #[doc = "Bit 13 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bits 16:31 - Division Factor"] + #[inline(always)] + pub fn div(&mut self) -> DIV_W { + DIV_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Generic Clock Generator Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [genctrl](index.html) module"] +pub struct GENCTRL_SPEC; +impl crate::RegisterSpec for GENCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [genctrl::R](R) reader structure"] +impl crate::Readable for GENCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [genctrl::W](W) writer structure"] +impl crate::Writable for GENCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets GENCTRL[%s] +to value 0"] +impl crate::Resettable for GENCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/gclk/pchctrl.rs b/pac/atsamc21n/src/gclk/pchctrl.rs new file mode 100644 index 000000000000..8001ffeaa1ee --- /dev/null +++ b/pac/atsamc21n/src/gclk/pchctrl.rs @@ -0,0 +1,338 @@ +#[doc = "Register `PCHCTRL[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PCHCTRL[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Generic Clock Generator\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum GEN_A { + #[doc = "0: Generic clock generator 0"] + GCLK0 = 0, + #[doc = "1: Generic clock generator 1"] + GCLK1 = 1, + #[doc = "2: Generic clock generator 2"] + GCLK2 = 2, + #[doc = "3: Generic clock generator 3"] + GCLK3 = 3, + #[doc = "4: Generic clock generator 4"] + GCLK4 = 4, + #[doc = "5: Generic clock generator 5"] + GCLK5 = 5, + #[doc = "6: Generic clock generator 6"] + GCLK6 = 6, + #[doc = "7: Generic clock generator 7"] + GCLK7 = 7, + #[doc = "8: Generic clock generator 8"] + GCLK8 = 8, +} +impl From for u8 { + #[inline(always)] + fn from(variant: GEN_A) -> Self { + variant as _ + } +} +#[doc = "Field `GEN` reader - Generic Clock Generator"] +pub struct GEN_R(crate::FieldReader); +impl GEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + GEN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(GEN_A::GCLK0), + 1 => Some(GEN_A::GCLK1), + 2 => Some(GEN_A::GCLK2), + 3 => Some(GEN_A::GCLK3), + 4 => Some(GEN_A::GCLK4), + 5 => Some(GEN_A::GCLK5), + 6 => Some(GEN_A::GCLK6), + 7 => Some(GEN_A::GCLK7), + 8 => Some(GEN_A::GCLK8), + _ => None, + } + } + #[doc = "Checks if the value of the field is `GCLK0`"] + #[inline(always)] + pub fn is_gclk0(&self) -> bool { + **self == GEN_A::GCLK0 + } + #[doc = "Checks if the value of the field is `GCLK1`"] + #[inline(always)] + pub fn is_gclk1(&self) -> bool { + **self == GEN_A::GCLK1 + } + #[doc = "Checks if the value of the field is `GCLK2`"] + #[inline(always)] + pub fn is_gclk2(&self) -> bool { + **self == GEN_A::GCLK2 + } + #[doc = "Checks if the value of the field is `GCLK3`"] + #[inline(always)] + pub fn is_gclk3(&self) -> bool { + **self == GEN_A::GCLK3 + } + #[doc = "Checks if the value of the field is `GCLK4`"] + #[inline(always)] + pub fn is_gclk4(&self) -> bool { + **self == GEN_A::GCLK4 + } + #[doc = "Checks if the value of the field is `GCLK5`"] + #[inline(always)] + pub fn is_gclk5(&self) -> bool { + **self == GEN_A::GCLK5 + } + #[doc = "Checks if the value of the field is `GCLK6`"] + #[inline(always)] + pub fn is_gclk6(&self) -> bool { + **self == GEN_A::GCLK6 + } + #[doc = "Checks if the value of the field is `GCLK7`"] + #[inline(always)] + pub fn is_gclk7(&self) -> bool { + **self == GEN_A::GCLK7 + } + #[doc = "Checks if the value of the field is `GCLK8`"] + #[inline(always)] + pub fn is_gclk8(&self) -> bool { + **self == GEN_A::GCLK8 + } +} +impl core::ops::Deref for GEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GEN` writer - Generic Clock Generator"] +pub struct GEN_W<'a> { + w: &'a mut W, +} +impl<'a> GEN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: GEN_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Generic clock generator 0"] + #[inline(always)] + pub fn gclk0(self) -> &'a mut W { + self.variant(GEN_A::GCLK0) + } + #[doc = "Generic clock generator 1"] + #[inline(always)] + pub fn gclk1(self) -> &'a mut W { + self.variant(GEN_A::GCLK1) + } + #[doc = "Generic clock generator 2"] + #[inline(always)] + pub fn gclk2(self) -> &'a mut W { + self.variant(GEN_A::GCLK2) + } + #[doc = "Generic clock generator 3"] + #[inline(always)] + pub fn gclk3(self) -> &'a mut W { + self.variant(GEN_A::GCLK3) + } + #[doc = "Generic clock generator 4"] + #[inline(always)] + pub fn gclk4(self) -> &'a mut W { + self.variant(GEN_A::GCLK4) + } + #[doc = "Generic clock generator 5"] + #[inline(always)] + pub fn gclk5(self) -> &'a mut W { + self.variant(GEN_A::GCLK5) + } + #[doc = "Generic clock generator 6"] + #[inline(always)] + pub fn gclk6(self) -> &'a mut W { + self.variant(GEN_A::GCLK6) + } + #[doc = "Generic clock generator 7"] + #[inline(always)] + pub fn gclk7(self) -> &'a mut W { + self.variant(GEN_A::GCLK7) + } + #[doc = "Generic clock generator 8"] + #[inline(always)] + pub fn gclk8(self) -> &'a mut W { + self.variant(GEN_A::GCLK8) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Field `CHEN` reader - Channel Enable"] +pub struct CHEN_R(crate::FieldReader); +impl CHEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHEN` writer - Channel Enable"] +pub struct CHEN_W<'a> { + w: &'a mut W, +} +impl<'a> CHEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `WRTLOCK` reader - Write Lock"] +pub struct WRTLOCK_R(crate::FieldReader); +impl WRTLOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WRTLOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WRTLOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WRTLOCK` writer - Write Lock"] +pub struct WRTLOCK_W<'a> { + w: &'a mut W, +} +impl<'a> WRTLOCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Generic Clock Generator"] + #[inline(always)] + pub fn gen(&self) -> GEN_R { + GEN_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 6 - Channel Enable"] + #[inline(always)] + pub fn chen(&self) -> CHEN_R { + CHEN_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&self) -> WRTLOCK_R { + WRTLOCK_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Generic Clock Generator"] + #[inline(always)] + pub fn gen(&mut self) -> GEN_W { + GEN_W { w: self } + } + #[doc = "Bit 6 - Channel Enable"] + #[inline(always)] + pub fn chen(&mut self) -> CHEN_W { + CHEN_W { w: self } + } + #[doc = "Bit 7 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&mut self) -> WRTLOCK_W { + WRTLOCK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Peripheral Clock Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pchctrl](index.html) module"] +pub struct PCHCTRL_SPEC; +impl crate::RegisterSpec for PCHCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pchctrl::R](R) reader structure"] +impl crate::Readable for PCHCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [pchctrl::W](W) writer structure"] +impl crate::Writable for PCHCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PCHCTRL[%s] +to value 0"] +impl crate::Resettable for PCHCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/gclk/syncbusy.rs b/pac/atsamc21n/src/gclk/syncbusy.rs new file mode 100644 index 000000000000..f21640440354 --- /dev/null +++ b/pac/atsamc21n/src/gclk/syncbusy.rs @@ -0,0 +1,233 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchroniation Busy bit"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENCTRL0` reader - Generic Clock Generator Control 0 Synchronization Busy bits"] +pub struct GENCTRL0_R(crate::FieldReader); +impl GENCTRL0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENCTRL0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENCTRL0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENCTRL1` reader - Generic Clock Generator Control 1 Synchronization Busy bits"] +pub struct GENCTRL1_R(crate::FieldReader); +impl GENCTRL1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENCTRL1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENCTRL1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENCTRL2` reader - Generic Clock Generator Control 2 Synchronization Busy bits"] +pub struct GENCTRL2_R(crate::FieldReader); +impl GENCTRL2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENCTRL2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENCTRL2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENCTRL3` reader - Generic Clock Generator Control 3 Synchronization Busy bits"] +pub struct GENCTRL3_R(crate::FieldReader); +impl GENCTRL3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENCTRL3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENCTRL3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENCTRL4` reader - Generic Clock Generator Control 4 Synchronization Busy bits"] +pub struct GENCTRL4_R(crate::FieldReader); +impl GENCTRL4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENCTRL4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENCTRL4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENCTRL5` reader - Generic Clock Generator Control 5 Synchronization Busy bits"] +pub struct GENCTRL5_R(crate::FieldReader); +impl GENCTRL5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENCTRL5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENCTRL5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENCTRL6` reader - Generic Clock Generator Control 6 Synchronization Busy bits"] +pub struct GENCTRL6_R(crate::FieldReader); +impl GENCTRL6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENCTRL6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENCTRL6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENCTRL7` reader - Generic Clock Generator Control 7 Synchronization Busy bits"] +pub struct GENCTRL7_R(crate::FieldReader); +impl GENCTRL7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENCTRL7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENCTRL7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENCTRL8` reader - Generic Clock Generator Control 8 Synchronization Busy bits"] +pub struct GENCTRL8_R(crate::FieldReader); +impl GENCTRL8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENCTRL8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENCTRL8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchroniation Busy bit"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 2 - Generic Clock Generator Control 0 Synchronization Busy bits"] + #[inline(always)] + pub fn genctrl0(&self) -> GENCTRL0_R { + GENCTRL0_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Generic Clock Generator Control 1 Synchronization Busy bits"] + #[inline(always)] + pub fn genctrl1(&self) -> GENCTRL1_R { + GENCTRL1_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Generic Clock Generator Control 2 Synchronization Busy bits"] + #[inline(always)] + pub fn genctrl2(&self) -> GENCTRL2_R { + GENCTRL2_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Generic Clock Generator Control 3 Synchronization Busy bits"] + #[inline(always)] + pub fn genctrl3(&self) -> GENCTRL3_R { + GENCTRL3_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Generic Clock Generator Control 4 Synchronization Busy bits"] + #[inline(always)] + pub fn genctrl4(&self) -> GENCTRL4_R { + GENCTRL4_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Generic Clock Generator Control 5 Synchronization Busy bits"] + #[inline(always)] + pub fn genctrl5(&self) -> GENCTRL5_R { + GENCTRL5_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Generic Clock Generator Control 6 Synchronization Busy bits"] + #[inline(always)] + pub fn genctrl6(&self) -> GENCTRL6_R { + GENCTRL6_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Generic Clock Generator Control 7 Synchronization Busy bits"] + #[inline(always)] + pub fn genctrl7(&self) -> GENCTRL7_R { + GENCTRL7_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Generic Clock Generator Control 8 Synchronization Busy bits"] + #[inline(always)] + pub fn genctrl8(&self) -> GENCTRL8_R { + GENCTRL8_R::new(((self.bits >> 10) & 0x01) != 0) + } +} +#[doc = "Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/generic.rs b/pac/atsamc21n/src/generic.rs new file mode 100644 index 000000000000..76159643acfa --- /dev/null +++ b/pac/atsamc21n/src/generic.rs @@ -0,0 +1,260 @@ +use core::marker; +#[doc = " Raw register type"] +pub trait RegisterSpec { + #[doc = " Raw register type (`u8`, `u16`, `u32`, ...)."] + type Ux: Copy; +} +#[doc = " Trait implemented by readable registers to enable the `read` method."] +#[doc = ""] +#[doc = " Registers marked with `Writable` can be also `modify`'ed."] +pub trait Readable: RegisterSpec { + #[doc = " Result from a call to `read` and argument to `modify`."] + type Reader: From> + core::ops::Deref>; +} +#[doc = " Trait implemented by writeable registers."] +#[doc = ""] +#[doc = " This enables the `write`, `write_with_zero` and `reset` methods."] +#[doc = ""] +#[doc = " Registers marked with `Readable` can be also `modify`'ed."] +pub trait Writable: RegisterSpec { + #[doc = " Writer type argument to `write`, et al."] + type Writer: From> + core::ops::DerefMut>; +} +#[doc = " Reset value of the register."] +#[doc = ""] +#[doc = " This value is the initial value for the `write` method. It can also be directly written to the"] +#[doc = " register by using the `reset` method."] +pub trait Resettable: RegisterSpec { + #[doc = " Reset value of the register."] + fn reset_value() -> Self::Ux; +} +#[doc = " This structure provides volatile access to registers."] +#[repr(transparent)] +pub struct Reg { + register: vcell::VolatileCell, + _marker: marker::PhantomData, +} +unsafe impl Send for Reg where REG::Ux: Send {} +impl Reg { + #[doc = " Returns the underlying memory address of register."] + #[doc = ""] + #[doc = " ```ignore"] + #[doc = " let reg_ptr = periph.reg.as_ptr();"] + #[doc = " ```"] + #[inline(always)] + pub fn as_ptr(&self) -> *mut REG::Ux { + self.register.as_ptr() + } +} +impl Reg { + #[doc = " Reads the contents of a `Readable` register."] + #[doc = ""] + #[doc = " You can read the raw contents of a register by using `bits`:"] + #[doc = " ```ignore"] + #[doc = " let bits = periph.reg.read().bits();"] + #[doc = " ```"] + #[doc = " or get the content of a particular field of a register:"] + #[doc = " ```ignore"] + #[doc = " let reader = periph.reg.read();"] + #[doc = " let bits = reader.field1().bits();"] + #[doc = " let flag = reader.field2().bit_is_set();"] + #[doc = " ```"] + #[inline(always)] + pub fn read(&self) -> REG::Reader { + REG::Reader::from(R { + bits: self.register.get(), + _reg: marker::PhantomData, + }) + } +} +impl Reg { + #[doc = " Writes the reset value to `Writable` register."] + #[doc = ""] + #[doc = " Resets the register to its initial state."] + #[inline(always)] + pub fn reset(&self) { + self.register.set(REG::reset_value()) + } + #[doc = " Writes bits to a `Writable` register."] + #[doc = ""] + #[doc = " You can write raw bits into a register:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.write(|w| unsafe { w.bits(rawbits) });"] + #[doc = " ```"] + #[doc = " or write only the fields you need:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.write(|w| w"] + #[doc = " .field1().bits(newfield1bits)"] + #[doc = " .field2().set_bit()"] + #[doc = " .field3().variant(VARIANT)"] + #[doc = " );"] + #[doc = " ```"] + #[doc = " In the latter case, other fields will be set to their reset value."] + #[inline(always)] + pub fn write(&self, f: F) + where + F: FnOnce(&mut REG::Writer) -> &mut W, + { + self.register.set( + f(&mut REG::Writer::from(W { + bits: REG::reset_value(), + _reg: marker::PhantomData, + })) + .bits, + ); + } +} +impl Reg +where + REG::Ux: Default, +{ + #[doc = " Writes 0 to a `Writable` register."] + #[doc = ""] + #[doc = " Similar to `write`, but unused bits will contain 0."] + #[inline(always)] + pub unsafe fn write_with_zero(&self, f: F) + where + F: FnOnce(&mut REG::Writer) -> &mut W, + { + self.register.set( + (*f(&mut REG::Writer::from(W { + bits: REG::Ux::default(), + _reg: marker::PhantomData, + }))) + .bits, + ); + } +} +impl Reg { + #[doc = " Modifies the contents of the register by reading and then writing it."] + #[doc = ""] + #[doc = " E.g. to do a read-modify-write sequence to change parts of a register:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.modify(|r, w| unsafe { w.bits("] + #[doc = " r.bits() | 3"] + #[doc = " ) });"] + #[doc = " ```"] + #[doc = " or"] + #[doc = " ```ignore"] + #[doc = " periph.reg.modify(|_, w| w"] + #[doc = " .field1().bits(newfield1bits)"] + #[doc = " .field2().set_bit()"] + #[doc = " .field3().variant(VARIANT)"] + #[doc = " );"] + #[doc = " ```"] + #[doc = " Other fields will have the value they had before the call to `modify`."] + #[inline(always)] + pub fn modify(&self, f: F) + where + for<'w> F: FnOnce(®::Reader, &'w mut REG::Writer) -> &'w mut W, + { + let bits = self.register.get(); + self.register.set( + f( + ®::Reader::from(R { + bits, + _reg: marker::PhantomData, + }), + &mut REG::Writer::from(W { + bits, + _reg: marker::PhantomData, + }), + ) + .bits, + ); + } +} +#[doc = " Register reader."] +#[doc = ""] +#[doc = " Result of the `read` methods of registers. Also used as a closure argument in the `modify`"] +#[doc = " method."] +pub struct R { + pub(crate) bits: REG::Ux, + _reg: marker::PhantomData, +} +impl R { + #[doc = " Reads raw bits from register."] + #[inline(always)] + pub fn bits(&self) -> REG::Ux { + self.bits + } +} +impl PartialEq for R +where + REG::Ux: PartialEq, + FI: Copy + Into, +{ + #[inline(always)] + fn eq(&self, other: &FI) -> bool { + self.bits.eq(&(*other).into()) + } +} +#[doc = " Register writer."] +#[doc = ""] +#[doc = " Used as an argument to the closures in the `write` and `modify` methods of the register."] +pub struct W { + #[doc = "Writable bits"] + pub(crate) bits: REG::Ux, + _reg: marker::PhantomData, +} +impl W { + #[doc = " Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = " Field reader."] +#[doc = ""] +#[doc = " Result of the `read` methods of fields."] +pub struct FieldReader { + pub(crate) bits: U, + _reg: marker::PhantomData, +} +impl FieldReader +where + U: Copy, +{ + #[doc = " Creates a new instance of the reader."] + #[allow(unused)] + #[inline(always)] + pub(crate) fn new(bits: U) -> Self { + Self { + bits, + _reg: marker::PhantomData, + } + } + #[doc = " Reads raw bits from field."] + #[inline(always)] + pub fn bits(&self) -> U { + self.bits + } +} +impl PartialEq for FieldReader +where + U: PartialEq, + FI: Copy + Into, +{ + #[inline(always)] + fn eq(&self, other: &FI) -> bool { + self.bits.eq(&(*other).into()) + } +} +impl FieldReader { + #[doc = " Value of the field as raw bits."] + #[inline(always)] + pub fn bit(&self) -> bool { + self.bits + } + #[doc = " Returns `true` if the bit is clear (0)."] + #[inline(always)] + pub fn bit_is_clear(&self) -> bool { + !self.bit() + } + #[doc = " Returns `true` if the bit is set (1)."] + #[inline(always)] + pub fn bit_is_set(&self) -> bool { + self.bit() + } +} diff --git a/pac/atsamc21n/src/hmatrixhs.rs b/pac/atsamc21n/src/hmatrixhs.rs new file mode 100644 index 000000000000..c8129ac89b6f --- /dev/null +++ b/pac/atsamc21n/src/hmatrixhs.rs @@ -0,0 +1,43 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00..0x40 - Master Configuration"] + pub mcfg: [crate::Reg; 16], + #[doc = "0x40..0x80 - Slave Configuration"] + pub scfg: [crate::Reg; 16], + #[doc = "0x80..0xa0 - PRS\\[%s\\]"] + pub prs: [PRS; 4], + _reserved3: [u8; 0x60], + #[doc = "0x100 - Master Remap Control"] + pub mrcr: crate::Reg, + _reserved4: [u8; 0x0c], + #[doc = "0x110..0x150 - Special Function"] + pub sfr: [crate::Reg; 16], +} +#[doc = r"Register block"] +#[repr(C)] +pub struct PRS { + #[doc = "0x00 - Priority A for Slave"] + pub pras: crate::Reg, + #[doc = "0x04 - Priority B for Slave"] + pub prbs: crate::Reg, +} +#[doc = r"Register block"] +#[doc = "PRS\\[%s\\]"] +pub mod prs; +#[doc = "MCFG register accessor: an alias for `Reg`"] +pub type MCFG = crate::Reg; +#[doc = "Master Configuration"] +pub mod mcfg; +#[doc = "SCFG register accessor: an alias for `Reg`"] +pub type SCFG = crate::Reg; +#[doc = "Slave Configuration"] +pub mod scfg; +#[doc = "MRCR register accessor: an alias for `Reg`"] +pub type MRCR = crate::Reg; +#[doc = "Master Remap Control"] +pub mod mrcr; +#[doc = "SFR register accessor: an alias for `Reg`"] +pub type SFR = crate::Reg; +#[doc = "Special Function"] +pub mod sfr; diff --git a/pac/atsamc21n/src/hmatrixhs/mcfg.rs b/pac/atsamc21n/src/hmatrixhs/mcfg.rs new file mode 100644 index 000000000000..454a39fabe13 --- /dev/null +++ b/pac/atsamc21n/src/hmatrixhs/mcfg.rs @@ -0,0 +1,192 @@ +#[doc = "Register `MCFG[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MCFG[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Undefined Length Burst Type\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum ULBT_A { + #[doc = "0: Infinite Length"] + INFINITE = 0, + #[doc = "1: Single Access"] + SINGLE = 1, + #[doc = "2: Four Beat Burst"] + FOUR_BEAT = 2, + #[doc = "3: Eight Beat Burst"] + EIGHT_BEAT = 3, + #[doc = "4: Sixteen Beat Burst"] + SIXTEEN_BEAT = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: ULBT_A) -> Self { + variant as _ + } +} +#[doc = "Field `ULBT` reader - Undefined Length Burst Type"] +pub struct ULBT_R(crate::FieldReader); +impl ULBT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ULBT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(ULBT_A::INFINITE), + 1 => Some(ULBT_A::SINGLE), + 2 => Some(ULBT_A::FOUR_BEAT), + 3 => Some(ULBT_A::EIGHT_BEAT), + 4 => Some(ULBT_A::SIXTEEN_BEAT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `INFINITE`"] + #[inline(always)] + pub fn is_infinite(&self) -> bool { + **self == ULBT_A::INFINITE + } + #[doc = "Checks if the value of the field is `SINGLE`"] + #[inline(always)] + pub fn is_single(&self) -> bool { + **self == ULBT_A::SINGLE + } + #[doc = "Checks if the value of the field is `FOUR_BEAT`"] + #[inline(always)] + pub fn is_four_beat(&self) -> bool { + **self == ULBT_A::FOUR_BEAT + } + #[doc = "Checks if the value of the field is `EIGHT_BEAT`"] + #[inline(always)] + pub fn is_eight_beat(&self) -> bool { + **self == ULBT_A::EIGHT_BEAT + } + #[doc = "Checks if the value of the field is `SIXTEEN_BEAT`"] + #[inline(always)] + pub fn is_sixteen_beat(&self) -> bool { + **self == ULBT_A::SIXTEEN_BEAT + } +} +impl core::ops::Deref for ULBT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ULBT` writer - Undefined Length Burst Type"] +pub struct ULBT_W<'a> { + w: &'a mut W, +} +impl<'a> ULBT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: ULBT_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Infinite Length"] + #[inline(always)] + pub fn infinite(self) -> &'a mut W { + self.variant(ULBT_A::INFINITE) + } + #[doc = "Single Access"] + #[inline(always)] + pub fn single(self) -> &'a mut W { + self.variant(ULBT_A::SINGLE) + } + #[doc = "Four Beat Burst"] + #[inline(always)] + pub fn four_beat(self) -> &'a mut W { + self.variant(ULBT_A::FOUR_BEAT) + } + #[doc = "Eight Beat Burst"] + #[inline(always)] + pub fn eight_beat(self) -> &'a mut W { + self.variant(ULBT_A::EIGHT_BEAT) + } + #[doc = "Sixteen Beat Burst"] + #[inline(always)] + pub fn sixteen_beat(self) -> &'a mut W { + self.variant(ULBT_A::SIXTEEN_BEAT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Undefined Length Burst Type"] + #[inline(always)] + pub fn ulbt(&self) -> ULBT_R { + ULBT_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Undefined Length Burst Type"] + #[inline(always)] + pub fn ulbt(&mut self) -> ULBT_W { + ULBT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Master Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mcfg](index.html) module"] +pub struct MCFG_SPEC; +impl crate::RegisterSpec for MCFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [mcfg::R](R) reader structure"] +impl crate::Readable for MCFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [mcfg::W](W) writer structure"] +impl crate::Writable for MCFG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets MCFG[%s] +to value 0x02"] +impl crate::Resettable for MCFG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x02 + } +} diff --git a/pac/atsamc21n/src/hmatrixhs/mrcr.rs b/pac/atsamc21n/src/hmatrixhs/mrcr.rs new file mode 100644 index 000000000000..0cf2a1fb01be --- /dev/null +++ b/pac/atsamc21n/src/hmatrixhs/mrcr.rs @@ -0,0 +1,1570 @@ +#[doc = "Register `MRCR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MRCR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Remap Command Bit for Master 0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB0_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB0_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB0` reader - Remap Command Bit for Master 0"] +pub struct RCB0_R(crate::FieldReader); +impl RCB0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB0_A { + match self.bits { + false => RCB0_A::DIS, + true => RCB0_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB0_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB0_A::ENA + } +} +impl core::ops::Deref for RCB0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB0` writer - Remap Command Bit for Master 0"] +pub struct RCB0_W<'a> { + w: &'a mut W, +} +impl<'a> RCB0_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB0_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB0_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB0_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Remap Command Bit for Master 1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB1_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB1_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB1` reader - Remap Command Bit for Master 1"] +pub struct RCB1_R(crate::FieldReader); +impl RCB1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB1_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB1_A { + match self.bits { + false => RCB1_A::DIS, + true => RCB1_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB1_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB1_A::ENA + } +} +impl core::ops::Deref for RCB1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB1` writer - Remap Command Bit for Master 1"] +pub struct RCB1_W<'a> { + w: &'a mut W, +} +impl<'a> RCB1_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB1_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB1_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB1_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Remap Command Bit for Master 2\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB2_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB2_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB2` reader - Remap Command Bit for Master 2"] +pub struct RCB2_R(crate::FieldReader); +impl RCB2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB2_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB2_A { + match self.bits { + false => RCB2_A::DIS, + true => RCB2_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB2_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB2_A::ENA + } +} +impl core::ops::Deref for RCB2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB2` writer - Remap Command Bit for Master 2"] +pub struct RCB2_W<'a> { + w: &'a mut W, +} +impl<'a> RCB2_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB2_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB2_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB2_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Remap Command Bit for Master 3\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB3_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB3_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB3` reader - Remap Command Bit for Master 3"] +pub struct RCB3_R(crate::FieldReader); +impl RCB3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB3_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB3_A { + match self.bits { + false => RCB3_A::DIS, + true => RCB3_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB3_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB3_A::ENA + } +} +impl core::ops::Deref for RCB3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB3` writer - Remap Command Bit for Master 3"] +pub struct RCB3_W<'a> { + w: &'a mut W, +} +impl<'a> RCB3_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB3_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB3_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB3_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Remap Command Bit for Master 4\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB4_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB4_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB4` reader - Remap Command Bit for Master 4"] +pub struct RCB4_R(crate::FieldReader); +impl RCB4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB4_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB4_A { + match self.bits { + false => RCB4_A::DIS, + true => RCB4_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB4_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB4_A::ENA + } +} +impl core::ops::Deref for RCB4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB4` writer - Remap Command Bit for Master 4"] +pub struct RCB4_W<'a> { + w: &'a mut W, +} +impl<'a> RCB4_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB4_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB4_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB4_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Remap Command Bit for Master 5\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB5_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB5_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB5` reader - Remap Command Bit for Master 5"] +pub struct RCB5_R(crate::FieldReader); +impl RCB5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB5_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB5_A { + match self.bits { + false => RCB5_A::DIS, + true => RCB5_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB5_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB5_A::ENA + } +} +impl core::ops::Deref for RCB5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB5` writer - Remap Command Bit for Master 5"] +pub struct RCB5_W<'a> { + w: &'a mut W, +} +impl<'a> RCB5_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB5_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB5_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB5_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Remap Command Bit for Master 6\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB6_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB6_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB6` reader - Remap Command Bit for Master 6"] +pub struct RCB6_R(crate::FieldReader); +impl RCB6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB6_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB6_A { + match self.bits { + false => RCB6_A::DIS, + true => RCB6_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB6_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB6_A::ENA + } +} +impl core::ops::Deref for RCB6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB6` writer - Remap Command Bit for Master 6"] +pub struct RCB6_W<'a> { + w: &'a mut W, +} +impl<'a> RCB6_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB6_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB6_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB6_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Remap Command Bit for Master 7\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB7_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB7_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB7` reader - Remap Command Bit for Master 7"] +pub struct RCB7_R(crate::FieldReader); +impl RCB7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB7_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB7_A { + match self.bits { + false => RCB7_A::DIS, + true => RCB7_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB7_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB7_A::ENA + } +} +impl core::ops::Deref for RCB7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB7` writer - Remap Command Bit for Master 7"] +pub struct RCB7_W<'a> { + w: &'a mut W, +} +impl<'a> RCB7_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB7_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB7_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB7_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Remap Command Bit for Master 8\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB8_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB8_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB8` reader - Remap Command Bit for Master 8"] +pub struct RCB8_R(crate::FieldReader); +impl RCB8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB8_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB8_A { + match self.bits { + false => RCB8_A::DIS, + true => RCB8_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB8_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB8_A::ENA + } +} +impl core::ops::Deref for RCB8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB8` writer - Remap Command Bit for Master 8"] +pub struct RCB8_W<'a> { + w: &'a mut W, +} +impl<'a> RCB8_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB8_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB8_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB8_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Remap Command Bit for Master 9\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB9_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB9_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB9` reader - Remap Command Bit for Master 9"] +pub struct RCB9_R(crate::FieldReader); +impl RCB9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB9_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB9_A { + match self.bits { + false => RCB9_A::DIS, + true => RCB9_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB9_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB9_A::ENA + } +} +impl core::ops::Deref for RCB9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB9` writer - Remap Command Bit for Master 9"] +pub struct RCB9_W<'a> { + w: &'a mut W, +} +impl<'a> RCB9_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB9_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB9_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB9_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Remap Command Bit for Master 10\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB10_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB10_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB10` reader - Remap Command Bit for Master 10"] +pub struct RCB10_R(crate::FieldReader); +impl RCB10_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB10_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB10_A { + match self.bits { + false => RCB10_A::DIS, + true => RCB10_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB10_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB10_A::ENA + } +} +impl core::ops::Deref for RCB10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB10` writer - Remap Command Bit for Master 10"] +pub struct RCB10_W<'a> { + w: &'a mut W, +} +impl<'a> RCB10_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB10_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB10_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB10_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Remap Command Bit for Master 11\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB11_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB11_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB11` reader - Remap Command Bit for Master 11"] +pub struct RCB11_R(crate::FieldReader); +impl RCB11_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB11_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB11_A { + match self.bits { + false => RCB11_A::DIS, + true => RCB11_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB11_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB11_A::ENA + } +} +impl core::ops::Deref for RCB11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB11` writer - Remap Command Bit for Master 11"] +pub struct RCB11_W<'a> { + w: &'a mut W, +} +impl<'a> RCB11_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB11_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB11_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB11_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Remap Command Bit for Master 12\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB12_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB12_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB12` reader - Remap Command Bit for Master 12"] +pub struct RCB12_R(crate::FieldReader); +impl RCB12_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB12_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB12_A { + match self.bits { + false => RCB12_A::DIS, + true => RCB12_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB12_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB12_A::ENA + } +} +impl core::ops::Deref for RCB12_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB12` writer - Remap Command Bit for Master 12"] +pub struct RCB12_W<'a> { + w: &'a mut W, +} +impl<'a> RCB12_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB12_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB12_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB12_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Remap Command Bit for Master 13\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB13_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB13_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB13` reader - Remap Command Bit for Master 13"] +pub struct RCB13_R(crate::FieldReader); +impl RCB13_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB13_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB13_A { + match self.bits { + false => RCB13_A::DIS, + true => RCB13_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB13_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB13_A::ENA + } +} +impl core::ops::Deref for RCB13_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB13` writer - Remap Command Bit for Master 13"] +pub struct RCB13_W<'a> { + w: &'a mut W, +} +impl<'a> RCB13_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB13_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB13_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB13_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Remap Command Bit for Master 14\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB14_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB14_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB14` reader - Remap Command Bit for Master 14"] +pub struct RCB14_R(crate::FieldReader); +impl RCB14_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB14_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB14_A { + match self.bits { + false => RCB14_A::DIS, + true => RCB14_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB14_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB14_A::ENA + } +} +impl core::ops::Deref for RCB14_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB14` writer - Remap Command Bit for Master 14"] +pub struct RCB14_W<'a> { + w: &'a mut W, +} +impl<'a> RCB14_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB14_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB14_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB14_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Remap Command Bit for Master 15\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RCB15_A { + #[doc = "0: Disable remapped address decoding for master"] + DIS = 0, + #[doc = "1: Enable remapped address decoding for master"] + ENA = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RCB15_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RCB15` reader - Remap Command Bit for Master 15"] +pub struct RCB15_R(crate::FieldReader); +impl RCB15_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCB15_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RCB15_A { + match self.bits { + false => RCB15_A::DIS, + true => RCB15_A::ENA, + } + } + #[doc = "Checks if the value of the field is `DIS`"] + #[inline(always)] + pub fn is_dis(&self) -> bool { + **self == RCB15_A::DIS + } + #[doc = "Checks if the value of the field is `ENA`"] + #[inline(always)] + pub fn is_ena(&self) -> bool { + **self == RCB15_A::ENA + } +} +impl core::ops::Deref for RCB15_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCB15` writer - Remap Command Bit for Master 15"] +pub struct RCB15_W<'a> { + w: &'a mut W, +} +impl<'a> RCB15_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RCB15_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Disable remapped address decoding for master"] + #[inline(always)] + pub fn dis(self) -> &'a mut W { + self.variant(RCB15_A::DIS) + } + #[doc = "Enable remapped address decoding for master"] + #[inline(always)] + pub fn ena(self) -> &'a mut W { + self.variant(RCB15_A::ENA) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Remap Command Bit for Master 0"] + #[inline(always)] + pub fn rcb0(&self) -> RCB0_R { + RCB0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Remap Command Bit for Master 1"] + #[inline(always)] + pub fn rcb1(&self) -> RCB1_R { + RCB1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Remap Command Bit for Master 2"] + #[inline(always)] + pub fn rcb2(&self) -> RCB2_R { + RCB2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Remap Command Bit for Master 3"] + #[inline(always)] + pub fn rcb3(&self) -> RCB3_R { + RCB3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Remap Command Bit for Master 4"] + #[inline(always)] + pub fn rcb4(&self) -> RCB4_R { + RCB4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Remap Command Bit for Master 5"] + #[inline(always)] + pub fn rcb5(&self) -> RCB5_R { + RCB5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Remap Command Bit for Master 6"] + #[inline(always)] + pub fn rcb6(&self) -> RCB6_R { + RCB6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Remap Command Bit for Master 7"] + #[inline(always)] + pub fn rcb7(&self) -> RCB7_R { + RCB7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Remap Command Bit for Master 8"] + #[inline(always)] + pub fn rcb8(&self) -> RCB8_R { + RCB8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Remap Command Bit for Master 9"] + #[inline(always)] + pub fn rcb9(&self) -> RCB9_R { + RCB9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Remap Command Bit for Master 10"] + #[inline(always)] + pub fn rcb10(&self) -> RCB10_R { + RCB10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Remap Command Bit for Master 11"] + #[inline(always)] + pub fn rcb11(&self) -> RCB11_R { + RCB11_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Remap Command Bit for Master 12"] + #[inline(always)] + pub fn rcb12(&self) -> RCB12_R { + RCB12_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Remap Command Bit for Master 13"] + #[inline(always)] + pub fn rcb13(&self) -> RCB13_R { + RCB13_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Remap Command Bit for Master 14"] + #[inline(always)] + pub fn rcb14(&self) -> RCB14_R { + RCB14_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Remap Command Bit for Master 15"] + #[inline(always)] + pub fn rcb15(&self) -> RCB15_R { + RCB15_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Remap Command Bit for Master 0"] + #[inline(always)] + pub fn rcb0(&mut self) -> RCB0_W { + RCB0_W { w: self } + } + #[doc = "Bit 1 - Remap Command Bit for Master 1"] + #[inline(always)] + pub fn rcb1(&mut self) -> RCB1_W { + RCB1_W { w: self } + } + #[doc = "Bit 2 - Remap Command Bit for Master 2"] + #[inline(always)] + pub fn rcb2(&mut self) -> RCB2_W { + RCB2_W { w: self } + } + #[doc = "Bit 3 - Remap Command Bit for Master 3"] + #[inline(always)] + pub fn rcb3(&mut self) -> RCB3_W { + RCB3_W { w: self } + } + #[doc = "Bit 4 - Remap Command Bit for Master 4"] + #[inline(always)] + pub fn rcb4(&mut self) -> RCB4_W { + RCB4_W { w: self } + } + #[doc = "Bit 5 - Remap Command Bit for Master 5"] + #[inline(always)] + pub fn rcb5(&mut self) -> RCB5_W { + RCB5_W { w: self } + } + #[doc = "Bit 6 - Remap Command Bit for Master 6"] + #[inline(always)] + pub fn rcb6(&mut self) -> RCB6_W { + RCB6_W { w: self } + } + #[doc = "Bit 7 - Remap Command Bit for Master 7"] + #[inline(always)] + pub fn rcb7(&mut self) -> RCB7_W { + RCB7_W { w: self } + } + #[doc = "Bit 8 - Remap Command Bit for Master 8"] + #[inline(always)] + pub fn rcb8(&mut self) -> RCB8_W { + RCB8_W { w: self } + } + #[doc = "Bit 9 - Remap Command Bit for Master 9"] + #[inline(always)] + pub fn rcb9(&mut self) -> RCB9_W { + RCB9_W { w: self } + } + #[doc = "Bit 10 - Remap Command Bit for Master 10"] + #[inline(always)] + pub fn rcb10(&mut self) -> RCB10_W { + RCB10_W { w: self } + } + #[doc = "Bit 11 - Remap Command Bit for Master 11"] + #[inline(always)] + pub fn rcb11(&mut self) -> RCB11_W { + RCB11_W { w: self } + } + #[doc = "Bit 12 - Remap Command Bit for Master 12"] + #[inline(always)] + pub fn rcb12(&mut self) -> RCB12_W { + RCB12_W { w: self } + } + #[doc = "Bit 13 - Remap Command Bit for Master 13"] + #[inline(always)] + pub fn rcb13(&mut self) -> RCB13_W { + RCB13_W { w: self } + } + #[doc = "Bit 14 - Remap Command Bit for Master 14"] + #[inline(always)] + pub fn rcb14(&mut self) -> RCB14_W { + RCB14_W { w: self } + } + #[doc = "Bit 15 - Remap Command Bit for Master 15"] + #[inline(always)] + pub fn rcb15(&mut self) -> RCB15_W { + RCB15_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Master Remap Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mrcr](index.html) module"] +pub struct MRCR_SPEC; +impl crate::RegisterSpec for MRCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [mrcr::R](R) reader structure"] +impl crate::Readable for MRCR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [mrcr::W](W) writer structure"] +impl crate::Writable for MRCR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets MRCR to value 0"] +impl crate::Resettable for MRCR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/hmatrixhs/prs.rs b/pac/atsamc21n/src/hmatrixhs/prs.rs new file mode 100644 index 000000000000..0313f3c4fc20 --- /dev/null +++ b/pac/atsamc21n/src/hmatrixhs/prs.rs @@ -0,0 +1,8 @@ +#[doc = "PRAS register accessor: an alias for `Reg`"] +pub type PRAS = crate::Reg; +#[doc = "Priority A for Slave"] +pub mod pras; +#[doc = "PRBS register accessor: an alias for `Reg`"] +pub type PRBS = crate::Reg; +#[doc = "Priority B for Slave"] +pub mod prbs; diff --git a/pac/atsamc21n/src/hmatrixhs/prs/pras.rs b/pac/atsamc21n/src/hmatrixhs/prs/pras.rs new file mode 100644 index 000000000000..ac4744a9e2a0 --- /dev/null +++ b/pac/atsamc21n/src/hmatrixhs/prs/pras.rs @@ -0,0 +1,362 @@ +#[doc = "Register `PRAS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PRAS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `M0PR` reader - Master 0 Priority"] +pub struct M0PR_R(crate::FieldReader); +impl M0PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M0PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M0PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M0PR` writer - Master 0 Priority"] +pub struct M0PR_W<'a> { + w: &'a mut W, +} +impl<'a> M0PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Field `M1PR` reader - Master 1 Priority"] +pub struct M1PR_R(crate::FieldReader); +impl M1PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M1PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M1PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M1PR` writer - Master 1 Priority"] +pub struct M1PR_W<'a> { + w: &'a mut W, +} +impl<'a> M1PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 4)) | ((value as u32 & 0x0f) << 4); + self.w + } +} +#[doc = "Field `M2PR` reader - Master 2 Priority"] +pub struct M2PR_R(crate::FieldReader); +impl M2PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M2PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M2PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M2PR` writer - Master 2 Priority"] +pub struct M2PR_W<'a> { + w: &'a mut W, +} +impl<'a> M2PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 8)) | ((value as u32 & 0x0f) << 8); + self.w + } +} +#[doc = "Field `M3PR` reader - Master 3 Priority"] +pub struct M3PR_R(crate::FieldReader); +impl M3PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M3PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M3PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M3PR` writer - Master 3 Priority"] +pub struct M3PR_W<'a> { + w: &'a mut W, +} +impl<'a> M3PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 12)) | ((value as u32 & 0x0f) << 12); + self.w + } +} +#[doc = "Field `M4PR` reader - Master 4 Priority"] +pub struct M4PR_R(crate::FieldReader); +impl M4PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M4PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M4PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M4PR` writer - Master 4 Priority"] +pub struct M4PR_W<'a> { + w: &'a mut W, +} +impl<'a> M4PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 16)) | ((value as u32 & 0x0f) << 16); + self.w + } +} +#[doc = "Field `M5PR` reader - Master 5 Priority"] +pub struct M5PR_R(crate::FieldReader); +impl M5PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M5PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M5PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M5PR` writer - Master 5 Priority"] +pub struct M5PR_W<'a> { + w: &'a mut W, +} +impl<'a> M5PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 20)) | ((value as u32 & 0x0f) << 20); + self.w + } +} +#[doc = "Field `M6PR` reader - Master 6 Priority"] +pub struct M6PR_R(crate::FieldReader); +impl M6PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M6PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M6PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M6PR` writer - Master 6 Priority"] +pub struct M6PR_W<'a> { + w: &'a mut W, +} +impl<'a> M6PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Field `M7PR` reader - Master 7 Priority"] +pub struct M7PR_R(crate::FieldReader); +impl M7PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M7PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M7PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M7PR` writer - Master 7 Priority"] +pub struct M7PR_W<'a> { + w: &'a mut W, +} +impl<'a> M7PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 28)) | ((value as u32 & 0x0f) << 28); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Master 0 Priority"] + #[inline(always)] + pub fn m0pr(&self) -> M0PR_R { + M0PR_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Master 1 Priority"] + #[inline(always)] + pub fn m1pr(&self) -> M1PR_R { + M1PR_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 8:11 - Master 2 Priority"] + #[inline(always)] + pub fn m2pr(&self) -> M2PR_R { + M2PR_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - Master 3 Priority"] + #[inline(always)] + pub fn m3pr(&self) -> M3PR_R { + M3PR_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:19 - Master 4 Priority"] + #[inline(always)] + pub fn m4pr(&self) -> M4PR_R { + M4PR_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bits 20:23 - Master 5 Priority"] + #[inline(always)] + pub fn m5pr(&self) -> M5PR_R { + M5PR_R::new(((self.bits >> 20) & 0x0f) as u8) + } + #[doc = "Bits 24:27 - Master 6 Priority"] + #[inline(always)] + pub fn m6pr(&self) -> M6PR_R { + M6PR_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bits 28:31 - Master 7 Priority"] + #[inline(always)] + pub fn m7pr(&self) -> M7PR_R { + M7PR_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Master 0 Priority"] + #[inline(always)] + pub fn m0pr(&mut self) -> M0PR_W { + M0PR_W { w: self } + } + #[doc = "Bits 4:7 - Master 1 Priority"] + #[inline(always)] + pub fn m1pr(&mut self) -> M1PR_W { + M1PR_W { w: self } + } + #[doc = "Bits 8:11 - Master 2 Priority"] + #[inline(always)] + pub fn m2pr(&mut self) -> M2PR_W { + M2PR_W { w: self } + } + #[doc = "Bits 12:15 - Master 3 Priority"] + #[inline(always)] + pub fn m3pr(&mut self) -> M3PR_W { + M3PR_W { w: self } + } + #[doc = "Bits 16:19 - Master 4 Priority"] + #[inline(always)] + pub fn m4pr(&mut self) -> M4PR_W { + M4PR_W { w: self } + } + #[doc = "Bits 20:23 - Master 5 Priority"] + #[inline(always)] + pub fn m5pr(&mut self) -> M5PR_W { + M5PR_W { w: self } + } + #[doc = "Bits 24:27 - Master 6 Priority"] + #[inline(always)] + pub fn m6pr(&mut self) -> M6PR_W { + M6PR_W { w: self } + } + #[doc = "Bits 28:31 - Master 7 Priority"] + #[inline(always)] + pub fn m7pr(&mut self) -> M7PR_W { + M7PR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Priority A for Slave\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pras](index.html) module"] +pub struct PRAS_SPEC; +impl crate::RegisterSpec for PRAS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pras::R](R) reader structure"] +impl crate::Readable for PRAS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [pras::W](W) writer structure"] +impl crate::Writable for PRAS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PRAS to value 0"] +impl crate::Resettable for PRAS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/hmatrixhs/prs/prbs.rs b/pac/atsamc21n/src/hmatrixhs/prs/prbs.rs new file mode 100644 index 000000000000..a2cc6bb9f6b0 --- /dev/null +++ b/pac/atsamc21n/src/hmatrixhs/prs/prbs.rs @@ -0,0 +1,362 @@ +#[doc = "Register `PRBS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PRBS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `M8PR` reader - Master 8 Priority"] +pub struct M8PR_R(crate::FieldReader); +impl M8PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M8PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M8PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M8PR` writer - Master 8 Priority"] +pub struct M8PR_W<'a> { + w: &'a mut W, +} +impl<'a> M8PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Field `M9PR` reader - Master 9 Priority"] +pub struct M9PR_R(crate::FieldReader); +impl M9PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M9PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M9PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M9PR` writer - Master 9 Priority"] +pub struct M9PR_W<'a> { + w: &'a mut W, +} +impl<'a> M9PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 4)) | ((value as u32 & 0x0f) << 4); + self.w + } +} +#[doc = "Field `M10PR` reader - Master 10 Priority"] +pub struct M10PR_R(crate::FieldReader); +impl M10PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M10PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M10PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M10PR` writer - Master 10 Priority"] +pub struct M10PR_W<'a> { + w: &'a mut W, +} +impl<'a> M10PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 8)) | ((value as u32 & 0x0f) << 8); + self.w + } +} +#[doc = "Field `M11PR` reader - Master 11 Priority"] +pub struct M11PR_R(crate::FieldReader); +impl M11PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M11PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M11PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M11PR` writer - Master 11 Priority"] +pub struct M11PR_W<'a> { + w: &'a mut W, +} +impl<'a> M11PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 12)) | ((value as u32 & 0x0f) << 12); + self.w + } +} +#[doc = "Field `M12PR` reader - Master 12 Priority"] +pub struct M12PR_R(crate::FieldReader); +impl M12PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M12PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M12PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M12PR` writer - Master 12 Priority"] +pub struct M12PR_W<'a> { + w: &'a mut W, +} +impl<'a> M12PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 16)) | ((value as u32 & 0x0f) << 16); + self.w + } +} +#[doc = "Field `M13PR` reader - Master 13 Priority"] +pub struct M13PR_R(crate::FieldReader); +impl M13PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M13PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M13PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M13PR` writer - Master 13 Priority"] +pub struct M13PR_W<'a> { + w: &'a mut W, +} +impl<'a> M13PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 20)) | ((value as u32 & 0x0f) << 20); + self.w + } +} +#[doc = "Field `M14PR` reader - Master 14 Priority"] +pub struct M14PR_R(crate::FieldReader); +impl M14PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M14PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M14PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M14PR` writer - Master 14 Priority"] +pub struct M14PR_W<'a> { + w: &'a mut W, +} +impl<'a> M14PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Field `M15PR` reader - Master 15 Priority"] +pub struct M15PR_R(crate::FieldReader); +impl M15PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + M15PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for M15PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `M15PR` writer - Master 15 Priority"] +pub struct M15PR_W<'a> { + w: &'a mut W, +} +impl<'a> M15PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 28)) | ((value as u32 & 0x0f) << 28); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Master 8 Priority"] + #[inline(always)] + pub fn m8pr(&self) -> M8PR_R { + M8PR_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Master 9 Priority"] + #[inline(always)] + pub fn m9pr(&self) -> M9PR_R { + M9PR_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 8:11 - Master 10 Priority"] + #[inline(always)] + pub fn m10pr(&self) -> M10PR_R { + M10PR_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - Master 11 Priority"] + #[inline(always)] + pub fn m11pr(&self) -> M11PR_R { + M11PR_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:19 - Master 12 Priority"] + #[inline(always)] + pub fn m12pr(&self) -> M12PR_R { + M12PR_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bits 20:23 - Master 13 Priority"] + #[inline(always)] + pub fn m13pr(&self) -> M13PR_R { + M13PR_R::new(((self.bits >> 20) & 0x0f) as u8) + } + #[doc = "Bits 24:27 - Master 14 Priority"] + #[inline(always)] + pub fn m14pr(&self) -> M14PR_R { + M14PR_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bits 28:31 - Master 15 Priority"] + #[inline(always)] + pub fn m15pr(&self) -> M15PR_R { + M15PR_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Master 8 Priority"] + #[inline(always)] + pub fn m8pr(&mut self) -> M8PR_W { + M8PR_W { w: self } + } + #[doc = "Bits 4:7 - Master 9 Priority"] + #[inline(always)] + pub fn m9pr(&mut self) -> M9PR_W { + M9PR_W { w: self } + } + #[doc = "Bits 8:11 - Master 10 Priority"] + #[inline(always)] + pub fn m10pr(&mut self) -> M10PR_W { + M10PR_W { w: self } + } + #[doc = "Bits 12:15 - Master 11 Priority"] + #[inline(always)] + pub fn m11pr(&mut self) -> M11PR_W { + M11PR_W { w: self } + } + #[doc = "Bits 16:19 - Master 12 Priority"] + #[inline(always)] + pub fn m12pr(&mut self) -> M12PR_W { + M12PR_W { w: self } + } + #[doc = "Bits 20:23 - Master 13 Priority"] + #[inline(always)] + pub fn m13pr(&mut self) -> M13PR_W { + M13PR_W { w: self } + } + #[doc = "Bits 24:27 - Master 14 Priority"] + #[inline(always)] + pub fn m14pr(&mut self) -> M14PR_W { + M14PR_W { w: self } + } + #[doc = "Bits 28:31 - Master 15 Priority"] + #[inline(always)] + pub fn m15pr(&mut self) -> M15PR_W { + M15PR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Priority B for Slave\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [prbs](index.html) module"] +pub struct PRBS_SPEC; +impl crate::RegisterSpec for PRBS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [prbs::R](R) reader structure"] +impl crate::Readable for PRBS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [prbs::W](W) writer structure"] +impl crate::Writable for PRBS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PRBS to value 0"] +impl crate::Resettable for PRBS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/hmatrixhs/scfg.rs b/pac/atsamc21n/src/hmatrixhs/scfg.rs new file mode 100644 index 000000000000..7180c043195a --- /dev/null +++ b/pac/atsamc21n/src/hmatrixhs/scfg.rs @@ -0,0 +1,334 @@ +#[doc = "Register `SCFG[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SCFG[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SLOT_CYCLE` reader - Maximum Number of Allowed Cycles for a Burst"] +pub struct SLOT_CYCLE_R(crate::FieldReader); +impl SLOT_CYCLE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SLOT_CYCLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SLOT_CYCLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLOT_CYCLE` writer - Maximum Number of Allowed Cycles for a Burst"] +pub struct SLOT_CYCLE_W<'a> { + w: &'a mut W, +} +impl<'a> SLOT_CYCLE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +#[doc = "Default Master Type\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DEFMSTR_TYPE_A { + #[doc = "0: No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst."] + NO_DEFAULT = 0, + #[doc = "1: Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave."] + LAST_DEFAULT = 1, + #[doc = "2: Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave."] + FIXED_DEFAULT = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DEFMSTR_TYPE_A) -> Self { + variant as _ + } +} +#[doc = "Field `DEFMSTR_TYPE` reader - Default Master Type"] +pub struct DEFMSTR_TYPE_R(crate::FieldReader); +impl DEFMSTR_TYPE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DEFMSTR_TYPE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(DEFMSTR_TYPE_A::NO_DEFAULT), + 1 => Some(DEFMSTR_TYPE_A::LAST_DEFAULT), + 2 => Some(DEFMSTR_TYPE_A::FIXED_DEFAULT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NO_DEFAULT`"] + #[inline(always)] + pub fn is_no_default(&self) -> bool { + **self == DEFMSTR_TYPE_A::NO_DEFAULT + } + #[doc = "Checks if the value of the field is `LAST_DEFAULT`"] + #[inline(always)] + pub fn is_last_default(&self) -> bool { + **self == DEFMSTR_TYPE_A::LAST_DEFAULT + } + #[doc = "Checks if the value of the field is `FIXED_DEFAULT`"] + #[inline(always)] + pub fn is_fixed_default(&self) -> bool { + **self == DEFMSTR_TYPE_A::FIXED_DEFAULT + } +} +impl core::ops::Deref for DEFMSTR_TYPE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DEFMSTR_TYPE` writer - Default Master Type"] +pub struct DEFMSTR_TYPE_W<'a> { + w: &'a mut W, +} +impl<'a> DEFMSTR_TYPE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DEFMSTR_TYPE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst."] + #[inline(always)] + pub fn no_default(self) -> &'a mut W { + self.variant(DEFMSTR_TYPE_A::NO_DEFAULT) + } + #[doc = "Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave."] + #[inline(always)] + pub fn last_default(self) -> &'a mut W { + self.variant(DEFMSTR_TYPE_A::LAST_DEFAULT) + } + #[doc = "Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave."] + #[inline(always)] + pub fn fixed_default(self) -> &'a mut W { + self.variant(DEFMSTR_TYPE_A::FIXED_DEFAULT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Field `FIXED_DEFMSTR` reader - Fixed Index of Default Master"] +pub struct FIXED_DEFMSTR_R(crate::FieldReader); +impl FIXED_DEFMSTR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FIXED_DEFMSTR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FIXED_DEFMSTR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FIXED_DEFMSTR` writer - Fixed Index of Default Master"] +pub struct FIXED_DEFMSTR_W<'a> { + w: &'a mut W, +} +impl<'a> FIXED_DEFMSTR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 18)) | ((value as u32 & 0x0f) << 18); + self.w + } +} +#[doc = "Arbitration Type\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ARBT_A { + #[doc = "0: Round-Robin Arbitration"] + ROUND_ROBIN = 0, + #[doc = "1: Fixed Priority Arbitration"] + FIXED_PRIORITY = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ARBT_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ARBT` reader - Arbitration Type"] +pub struct ARBT_R(crate::FieldReader); +impl ARBT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ARBT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ARBT_A { + match self.bits { + false => ARBT_A::ROUND_ROBIN, + true => ARBT_A::FIXED_PRIORITY, + } + } + #[doc = "Checks if the value of the field is `ROUND_ROBIN`"] + #[inline(always)] + pub fn is_round_robin(&self) -> bool { + **self == ARBT_A::ROUND_ROBIN + } + #[doc = "Checks if the value of the field is `FIXED_PRIORITY`"] + #[inline(always)] + pub fn is_fixed_priority(&self) -> bool { + **self == ARBT_A::FIXED_PRIORITY + } +} +impl core::ops::Deref for ARBT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ARBT` writer - Arbitration Type"] +pub struct ARBT_W<'a> { + w: &'a mut W, +} +impl<'a> ARBT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: ARBT_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Round-Robin Arbitration"] + #[inline(always)] + pub fn round_robin(self) -> &'a mut W { + self.variant(ARBT_A::ROUND_ROBIN) + } + #[doc = "Fixed Priority Arbitration"] + #[inline(always)] + pub fn fixed_priority(self) -> &'a mut W { + self.variant(ARBT_A::FIXED_PRIORITY) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Maximum Number of Allowed Cycles for a Burst"] + #[inline(always)] + pub fn slot_cycle(&self) -> SLOT_CYCLE_R { + SLOT_CYCLE_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 16:17 - Default Master Type"] + #[inline(always)] + pub fn defmstr_type(&self) -> DEFMSTR_TYPE_R { + DEFMSTR_TYPE_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bits 18:21 - Fixed Index of Default Master"] + #[inline(always)] + pub fn fixed_defmstr(&self) -> FIXED_DEFMSTR_R { + FIXED_DEFMSTR_R::new(((self.bits >> 18) & 0x0f) as u8) + } + #[doc = "Bit 24 - Arbitration Type"] + #[inline(always)] + pub fn arbt(&self) -> ARBT_R { + ARBT_R::new(((self.bits >> 24) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - Maximum Number of Allowed Cycles for a Burst"] + #[inline(always)] + pub fn slot_cycle(&mut self) -> SLOT_CYCLE_W { + SLOT_CYCLE_W { w: self } + } + #[doc = "Bits 16:17 - Default Master Type"] + #[inline(always)] + pub fn defmstr_type(&mut self) -> DEFMSTR_TYPE_W { + DEFMSTR_TYPE_W { w: self } + } + #[doc = "Bits 18:21 - Fixed Index of Default Master"] + #[inline(always)] + pub fn fixed_defmstr(&mut self) -> FIXED_DEFMSTR_W { + FIXED_DEFMSTR_W { w: self } + } + #[doc = "Bit 24 - Arbitration Type"] + #[inline(always)] + pub fn arbt(&mut self) -> ARBT_W { + ARBT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Slave Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [scfg](index.html) module"] +pub struct SCFG_SPEC; +impl crate::RegisterSpec for SCFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [scfg::R](R) reader structure"] +impl crate::Readable for SCFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [scfg::W](W) writer structure"] +impl crate::Writable for SCFG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SCFG[%s] +to value 0x10"] +impl crate::Resettable for SCFG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x10 + } +} diff --git a/pac/atsamc21n/src/hmatrixhs/sfr.rs b/pac/atsamc21n/src/hmatrixhs/sfr.rs new file mode 100644 index 000000000000..0a7e024f73c8 --- /dev/null +++ b/pac/atsamc21n/src/hmatrixhs/sfr.rs @@ -0,0 +1,104 @@ +#[doc = "Register `SFR[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SFR[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SFR` reader - Special Function Register"] +pub struct SFR_R(crate::FieldReader); +impl SFR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + SFR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SFR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SFR` writer - Special Function Register"] +pub struct SFR_W<'a> { + w: &'a mut W, +} +impl<'a> SFR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Special Function Register"] + #[inline(always)] + pub fn sfr(&self) -> SFR_R { + SFR_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Special Function Register"] + #[inline(always)] + pub fn sfr(&mut self) -> SFR_W { + SFR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Special Function\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sfr](index.html) module"] +pub struct SFR_SPEC; +impl crate::RegisterSpec for SFR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [sfr::R](R) reader structure"] +impl crate::Readable for SFR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [sfr::W](W) writer structure"] +impl crate::Writable for SFR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SFR[%s] +to value 0"] +impl crate::Resettable for SFR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/lib.rs b/pac/atsamc21n/src/lib.rs new file mode 100644 index 000000000000..270abec211c2 --- /dev/null +++ b/pac/atsamc21n/src/lib.rs @@ -0,0 +1,1875 @@ +#![doc = "Peripheral access API for ATSAMC21N microcontrollers (generated using svd2rust v0.20.0 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] +svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.20.0/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"] +#![deny(const_err)] +#![deny(dead_code)] +#![deny(improper_ctypes)] +#![deny(missing_docs)] +#![deny(no_mangle_generic_items)] +#![deny(non_shorthand_field_patterns)] +#![deny(overflowing_literals)] +#![deny(path_statements)] +#![deny(patterns_in_fns_without_body)] +#![deny(private_in_public)] +#![deny(unconditional_recursion)] +#![deny(unused_allocation)] +#![deny(unused_comparisons)] +#![deny(unused_parens)] +#![deny(while_true)] +#![allow(non_camel_case_types)] +#![allow(non_snake_case)] +#![allow(clippy::all)] +#![no_std] +use core::marker::PhantomData; +use core::ops::Deref; +#[doc = r"Number available in the NVIC for configuring priority"] +pub const NVIC_PRIO_BITS: u8 = 2; +#[cfg(feature = "rt")] +pub use self::Interrupt as interrupt; +pub use cortex_m::peripheral::Peripherals as CorePeripherals; +pub use cortex_m::peripheral::{CBP, CPUID, DCB, DWT, FPB, ITM, MPU, NVIC, SCB, SYST, TPIU}; +#[cfg(feature = "rt")] +pub use cortex_m_rt::interrupt; +#[allow(unused_imports)] +use generic::*; +#[doc = r"Common register and bit access and modify traits"] +pub mod generic; +#[cfg(feature = "rt")] +extern "C" { + fn WDT(); + fn RTC(); + fn EIC(); + fn FREQM(); + fn TSENS(); + fn NVMCTRL(); + fn DMAC(); + fn EVSYS(); + fn SERCOM2(); + fn SERCOM3(); + fn SERCOM4(); + fn SERCOM5(); + fn CAN0(); + fn CAN1(); + fn TCC0(); + fn TCC1(); + fn TCC2(); + fn TC3(); + fn TC4(); + fn ADC0(); + fn ADC1(); + fn AC(); + fn DAC(); + fn SDADC(); + fn PTC(); +} +#[doc(hidden)] +pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, +} +#[cfg(feature = "rt")] +#[doc(hidden)] +#[link_section = ".vector_table.interrupts"] +#[no_mangle] +pub static __INTERRUPTS: [Vector; 31] = [ + Vector { _reserved: 0 }, + Vector { _handler: WDT }, + Vector { _handler: RTC }, + Vector { _handler: EIC }, + Vector { _handler: FREQM }, + Vector { _handler: TSENS }, + Vector { _handler: NVMCTRL }, + Vector { _handler: DMAC }, + Vector { _handler: EVSYS }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SERCOM2 }, + Vector { _handler: SERCOM3 }, + Vector { _handler: SERCOM4 }, + Vector { _handler: SERCOM5 }, + Vector { _handler: CAN0 }, + Vector { _handler: CAN1 }, + Vector { _handler: TCC0 }, + Vector { _handler: TCC1 }, + Vector { _handler: TCC2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TC3 }, + Vector { _handler: TC4 }, + Vector { _handler: ADC0 }, + Vector { _handler: ADC1 }, + Vector { _handler: AC }, + Vector { _handler: DAC }, + Vector { _handler: SDADC }, + Vector { _handler: PTC }, +]; +#[doc = r"Enumeration of all the interrupts."] +#[derive(Copy, Clone, Debug, PartialEq, Eq)] +#[repr(u16)] +pub enum Interrupt { + #[doc = "1 - WDT"] + WDT = 1, + #[doc = "2 - RTC"] + RTC = 2, + #[doc = "3 - EIC"] + EIC = 3, + #[doc = "4 - FREQM"] + FREQM = 4, + #[doc = "5 - TSENS"] + TSENS = 5, + #[doc = "6 - NVMCTRL"] + NVMCTRL = 6, + #[doc = "7 - DMAC"] + DMAC = 7, + #[doc = "8 - EVSYS"] + EVSYS = 8, + #[doc = "11 - SERCOM2"] + SERCOM2 = 11, + #[doc = "12 - SERCOM3"] + SERCOM3 = 12, + #[doc = "13 - SERCOM4"] + SERCOM4 = 13, + #[doc = "14 - SERCOM5"] + SERCOM5 = 14, + #[doc = "15 - CAN0"] + CAN0 = 15, + #[doc = "16 - CAN1"] + CAN1 = 16, + #[doc = "17 - TCC0"] + TCC0 = 17, + #[doc = "18 - TCC1"] + TCC1 = 18, + #[doc = "19 - TCC2"] + TCC2 = 19, + #[doc = "23 - TC3"] + TC3 = 23, + #[doc = "24 - TC4"] + TC4 = 24, + #[doc = "25 - ADC0"] + ADC0 = 25, + #[doc = "26 - ADC1"] + ADC1 = 26, + #[doc = "27 - AC"] + AC = 27, + #[doc = "28 - DAC"] + DAC = 28, + #[doc = "29 - SDADC"] + SDADC = 29, + #[doc = "30 - PTC"] + PTC = 30, +} +unsafe impl cortex_m::interrupt::InterruptNumber for Interrupt { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } +} +#[doc = "Analog Comparators"] +pub struct AC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for AC {} +impl AC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const ac::RegisterBlock = 0x4200_5000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const ac::RegisterBlock { + Self::PTR + } +} +impl Deref for AC { + type Target = ac::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for AC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AC").finish() + } +} +#[doc = "Analog Comparators"] +pub mod ac; +#[doc = "Analog Digital Converter"] +pub struct ADC0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for ADC0 {} +impl ADC0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const adc0::RegisterBlock = 0x4200_4400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const adc0::RegisterBlock { + Self::PTR + } +} +impl Deref for ADC0 { + type Target = adc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for ADC0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ADC0").finish() + } +} +#[doc = "Analog Digital Converter"] +pub mod adc0; +#[doc = "Analog Digital Converter"] +pub struct ADC1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for ADC1 {} +impl ADC1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const adc0::RegisterBlock = 0x4200_4800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const adc0::RegisterBlock { + Self::PTR + } +} +impl Deref for ADC1 { + type Target = adc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for ADC1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ADC1").finish() + } +} +#[doc = "Analog Digital Converter"] +pub use adc0 as adc1; +#[doc = "Control Area Network"] +pub struct CAN0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for CAN0 {} +impl CAN0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const can0::RegisterBlock = 0x4200_1c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const can0::RegisterBlock { + Self::PTR + } +} +impl Deref for CAN0 { + type Target = can0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for CAN0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CAN0").finish() + } +} +#[doc = "Control Area Network"] +pub mod can0; +#[doc = "Control Area Network"] +pub struct CAN1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for CAN1 {} +impl CAN1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const can0::RegisterBlock = 0x4200_2000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const can0::RegisterBlock { + Self::PTR + } +} +impl Deref for CAN1 { + type Target = can0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for CAN1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CAN1").finish() + } +} +#[doc = "Control Area Network"] +pub use can0 as can1; +#[doc = "Configurable Custom Logic"] +pub struct CCL { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for CCL {} +impl CCL { + #[doc = r"Pointer to the register block"] + pub const PTR: *const ccl::RegisterBlock = 0x4200_5c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const ccl::RegisterBlock { + Self::PTR + } +} +impl Deref for CCL { + type Target = ccl::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for CCL { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CCL").finish() + } +} +#[doc = "Configurable Custom Logic"] +pub mod ccl; +#[doc = "Digital Analog Converter"] +pub struct DAC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for DAC {} +impl DAC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const dac::RegisterBlock = 0x4200_5400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const dac::RegisterBlock { + Self::PTR + } +} +impl Deref for DAC { + type Target = dac::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for DAC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DAC").finish() + } +} +#[doc = "Digital Analog Converter"] +pub mod dac; +#[doc = "Divide and Square Root Accelerator"] +pub struct DIVAS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for DIVAS {} +impl DIVAS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const divas::RegisterBlock = 0x4800_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const divas::RegisterBlock { + Self::PTR + } +} +impl Deref for DIVAS { + type Target = divas::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for DIVAS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DIVAS").finish() + } +} +#[doc = "Divide and Square Root Accelerator"] +pub mod divas; +#[doc = "Direct Memory Access Controller"] +pub struct DMAC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for DMAC {} +impl DMAC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const dmac::RegisterBlock = 0x4100_6000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const dmac::RegisterBlock { + Self::PTR + } +} +impl Deref for DMAC { + type Target = dmac::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for DMAC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DMAC").finish() + } +} +#[doc = "Direct Memory Access Controller"] +pub mod dmac; +#[doc = "Device Service Unit"] +pub struct DSU { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for DSU {} +impl DSU { + #[doc = r"Pointer to the register block"] + pub const PTR: *const dsu::RegisterBlock = 0x4100_2000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const dsu::RegisterBlock { + Self::PTR + } +} +impl Deref for DSU { + type Target = dsu::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for DSU { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DSU").finish() + } +} +#[doc = "Device Service Unit"] +pub mod dsu; +#[doc = "External Interrupt Controller"] +pub struct EIC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for EIC {} +impl EIC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const eic::RegisterBlock = 0x4000_2800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const eic::RegisterBlock { + Self::PTR + } +} +impl Deref for EIC { + type Target = eic::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for EIC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EIC").finish() + } +} +#[doc = "External Interrupt Controller"] +pub mod eic; +#[doc = "Event System Interface"] +pub struct EVSYS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for EVSYS {} +impl EVSYS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const evsys::RegisterBlock = 0x4200_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const evsys::RegisterBlock { + Self::PTR + } +} +impl Deref for EVSYS { + type Target = evsys::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for EVSYS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EVSYS").finish() + } +} +#[doc = "Event System Interface"] +pub mod evsys; +#[doc = "Frequency Meter"] +pub struct FREQM { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for FREQM {} +impl FREQM { + #[doc = r"Pointer to the register block"] + pub const PTR: *const freqm::RegisterBlock = 0x4000_2c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const freqm::RegisterBlock { + Self::PTR + } +} +impl Deref for FREQM { + type Target = freqm::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for FREQM { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FREQM").finish() + } +} +#[doc = "Frequency Meter"] +pub mod freqm; +#[doc = "Generic Clock Generator"] +pub struct GCLK { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for GCLK {} +impl GCLK { + #[doc = r"Pointer to the register block"] + pub const PTR: *const gclk::RegisterBlock = 0x4000_1c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const gclk::RegisterBlock { + Self::PTR + } +} +impl Deref for GCLK { + type Target = gclk::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for GCLK { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GCLK").finish() + } +} +#[doc = "Generic Clock Generator"] +pub mod gclk; +#[doc = "HSB Matrix"] +pub struct HMATRIXHS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for HMATRIXHS {} +impl HMATRIXHS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const hmatrixhs::RegisterBlock = 0x4100_a000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const hmatrixhs::RegisterBlock { + Self::PTR + } +} +impl Deref for HMATRIXHS { + type Target = hmatrixhs::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for HMATRIXHS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HMATRIXHS").finish() + } +} +#[doc = "HSB Matrix"] +pub mod hmatrixhs; +#[doc = "Main Clock"] +pub struct MCLK { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for MCLK {} +impl MCLK { + #[doc = r"Pointer to the register block"] + pub const PTR: *const mclk::RegisterBlock = 0x4000_0800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const mclk::RegisterBlock { + Self::PTR + } +} +impl Deref for MCLK { + type Target = mclk::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for MCLK { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MCLK").finish() + } +} +#[doc = "Main Clock"] +pub mod mclk; +#[doc = "Cortex-M0+ Micro-Trace Buffer"] +pub struct MTB { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for MTB {} +impl MTB { + #[doc = r"Pointer to the register block"] + pub const PTR: *const mtb::RegisterBlock = 0x4100_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const mtb::RegisterBlock { + Self::PTR + } +} +impl Deref for MTB { + type Target = mtb::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for MTB { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MTB").finish() + } +} +#[doc = "Cortex-M0+ Micro-Trace Buffer"] +pub mod mtb; +#[doc = "Non-Volatile Memory Controller"] +pub struct NVMCTRL { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for NVMCTRL {} +impl NVMCTRL { + #[doc = r"Pointer to the register block"] + pub const PTR: *const nvmctrl::RegisterBlock = 0x4100_4000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const nvmctrl::RegisterBlock { + Self::PTR + } +} +impl Deref for NVMCTRL { + type Target = nvmctrl::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for NVMCTRL { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("NVMCTRL").finish() + } +} +#[doc = "Non-Volatile Memory Controller"] +pub mod nvmctrl; +#[doc = "Oscillators Control"] +pub struct OSCCTRL { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for OSCCTRL {} +impl OSCCTRL { + #[doc = r"Pointer to the register block"] + pub const PTR: *const oscctrl::RegisterBlock = 0x4000_1000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const oscctrl::RegisterBlock { + Self::PTR + } +} +impl Deref for OSCCTRL { + type Target = oscctrl::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for OSCCTRL { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OSCCTRL").finish() + } +} +#[doc = "Oscillators Control"] +pub mod oscctrl; +#[doc = "32k Oscillators Control"] +pub struct OSC32KCTRL { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for OSC32KCTRL {} +impl OSC32KCTRL { + #[doc = r"Pointer to the register block"] + pub const PTR: *const osc32kctrl::RegisterBlock = 0x4000_1400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const osc32kctrl::RegisterBlock { + Self::PTR + } +} +impl Deref for OSC32KCTRL { + type Target = osc32kctrl::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for OSC32KCTRL { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OSC32KCTRL").finish() + } +} +#[doc = "32k Oscillators Control"] +pub mod osc32kctrl; +#[doc = "Peripheral Access Controller"] +pub struct PAC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PAC {} +impl PAC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const pac::RegisterBlock = 0x4000_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const pac::RegisterBlock { + Self::PTR + } +} +impl Deref for PAC { + type Target = pac::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PAC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PAC").finish() + } +} +#[doc = "Peripheral Access Controller"] +pub mod pac; +#[doc = "Power Manager"] +pub struct PM { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PM {} +impl PM { + #[doc = r"Pointer to the register block"] + pub const PTR: *const pm::RegisterBlock = 0x4000_0400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const pm::RegisterBlock { + Self::PTR + } +} +impl Deref for PM { + type Target = pm::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PM { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PM").finish() + } +} +#[doc = "Power Manager"] +pub mod pm; +#[doc = "Port Module"] +pub struct PORT { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PORT {} +impl PORT { + #[doc = r"Pointer to the register block"] + pub const PTR: *const port::RegisterBlock = 0x4100_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const port::RegisterBlock { + Self::PTR + } +} +impl Deref for PORT { + type Target = port::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PORT { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PORT").finish() + } +} +#[doc = "Port Module"] +pub mod port; +#[doc = "Port Module"] +pub struct PORT_IOBUS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PORT_IOBUS {} +impl PORT_IOBUS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const port::RegisterBlock = 0x6000_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const port::RegisterBlock { + Self::PTR + } +} +impl Deref for PORT_IOBUS { + type Target = port::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PORT_IOBUS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PORT_IOBUS").finish() + } +} +#[doc = "Port Module"] +pub use port as port_iobus; +#[doc = "Reset Controller"] +pub struct RSTC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for RSTC {} +impl RSTC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const rstc::RegisterBlock = 0x4000_0c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const rstc::RegisterBlock { + Self::PTR + } +} +impl Deref for RSTC { + type Target = rstc::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for RSTC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RSTC").finish() + } +} +#[doc = "Reset Controller"] +pub mod rstc; +#[doc = "Real-Time Counter"] +pub struct RTC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for RTC {} +impl RTC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const rtc::RegisterBlock = 0x4000_2400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const rtc::RegisterBlock { + Self::PTR + } +} +impl Deref for RTC { + type Target = rtc::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for RTC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RTC").finish() + } +} +#[doc = "Real-Time Counter"] +pub mod rtc; +#[doc = "Sigma-Delta Analog Digital Converter"] +pub struct SDADC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SDADC {} +impl SDADC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sdadc::RegisterBlock = 0x4200_4c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sdadc::RegisterBlock { + Self::PTR + } +} +impl Deref for SDADC { + type Target = sdadc::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SDADC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SDADC").finish() + } +} +#[doc = "Sigma-Delta Analog Digital Converter"] +pub mod sdadc; +#[doc = "Serial Communication Interface"] +pub struct SERCOM0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SERCOM0 {} +impl SERCOM0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sercom0::RegisterBlock = 0x4200_0400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sercom0::RegisterBlock { + Self::PTR + } +} +impl Deref for SERCOM0 { + type Target = sercom0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SERCOM0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SERCOM0").finish() + } +} +#[doc = "Serial Communication Interface"] +pub mod sercom0; +#[doc = "Serial Communication Interface"] +pub struct SERCOM1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SERCOM1 {} +impl SERCOM1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sercom0::RegisterBlock = 0x4200_0800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sercom0::RegisterBlock { + Self::PTR + } +} +impl Deref for SERCOM1 { + type Target = sercom0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SERCOM1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SERCOM1").finish() + } +} +#[doc = "Serial Communication Interface"] +pub use sercom0 as sercom1; +#[doc = "Serial Communication Interface"] +pub struct SERCOM2 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SERCOM2 {} +impl SERCOM2 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sercom0::RegisterBlock = 0x4200_0c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sercom0::RegisterBlock { + Self::PTR + } +} +impl Deref for SERCOM2 { + type Target = sercom0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SERCOM2 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SERCOM2").finish() + } +} +#[doc = "Serial Communication Interface"] +pub use sercom0 as sercom2; +#[doc = "Serial Communication Interface"] +pub struct SERCOM3 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SERCOM3 {} +impl SERCOM3 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sercom0::RegisterBlock = 0x4200_1000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sercom0::RegisterBlock { + Self::PTR + } +} +impl Deref for SERCOM3 { + type Target = sercom0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SERCOM3 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SERCOM3").finish() + } +} +#[doc = "Serial Communication Interface"] +pub use sercom0 as sercom3; +#[doc = "Serial Communication Interface"] +pub struct SERCOM4 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SERCOM4 {} +impl SERCOM4 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sercom0::RegisterBlock = 0x4200_1400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sercom0::RegisterBlock { + Self::PTR + } +} +impl Deref for SERCOM4 { + type Target = sercom0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SERCOM4 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SERCOM4").finish() + } +} +#[doc = "Serial Communication Interface"] +pub use sercom0 as sercom4; +#[doc = "Serial Communication Interface"] +pub struct SERCOM5 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SERCOM5 {} +impl SERCOM5 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sercom0::RegisterBlock = 0x4200_1800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sercom0::RegisterBlock { + Self::PTR + } +} +impl Deref for SERCOM5 { + type Target = sercom0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SERCOM5 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SERCOM5").finish() + } +} +#[doc = "Serial Communication Interface"] +pub use sercom0 as sercom5; +#[doc = "Serial Communication Interface"] +pub struct SERCOM6 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SERCOM6 {} +impl SERCOM6 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sercom0::RegisterBlock = 0x4300_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sercom0::RegisterBlock { + Self::PTR + } +} +impl Deref for SERCOM6 { + type Target = sercom0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SERCOM6 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SERCOM6").finish() + } +} +#[doc = "Serial Communication Interface"] +pub use sercom0 as sercom6; +#[doc = "Serial Communication Interface"] +pub struct SERCOM7 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SERCOM7 {} +impl SERCOM7 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sercom0::RegisterBlock = 0x4300_0400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sercom0::RegisterBlock { + Self::PTR + } +} +impl Deref for SERCOM7 { + type Target = sercom0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SERCOM7 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SERCOM7").finish() + } +} +#[doc = "Serial Communication Interface"] +pub use sercom0 as sercom7; +#[doc = "Supply Controller"] +pub struct SUPC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SUPC {} +impl SUPC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const supc::RegisterBlock = 0x4000_1800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const supc::RegisterBlock { + Self::PTR + } +} +impl Deref for SUPC { + type Target = supc::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SUPC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SUPC").finish() + } +} +#[doc = "Supply Controller"] +pub mod supc; +#[doc = "Basic Timer Counter"] +pub struct TC0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TC0 {} +impl TC0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tc0::RegisterBlock = 0x4200_3000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tc0::RegisterBlock { + Self::PTR + } +} +impl Deref for TC0 { + type Target = tc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TC0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TC0").finish() + } +} +#[doc = "Basic Timer Counter"] +pub mod tc0; +#[doc = "Basic Timer Counter"] +pub struct TC1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TC1 {} +impl TC1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tc0::RegisterBlock = 0x4200_3400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tc0::RegisterBlock { + Self::PTR + } +} +impl Deref for TC1 { + type Target = tc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TC1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TC1").finish() + } +} +#[doc = "Basic Timer Counter"] +pub use tc0 as tc1; +#[doc = "Basic Timer Counter"] +pub struct TC2 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TC2 {} +impl TC2 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tc0::RegisterBlock = 0x4200_3800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tc0::RegisterBlock { + Self::PTR + } +} +impl Deref for TC2 { + type Target = tc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TC2 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TC2").finish() + } +} +#[doc = "Basic Timer Counter"] +pub use tc0 as tc2; +#[doc = "Basic Timer Counter"] +pub struct TC3 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TC3 {} +impl TC3 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tc0::RegisterBlock = 0x4200_3c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tc0::RegisterBlock { + Self::PTR + } +} +impl Deref for TC3 { + type Target = tc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TC3 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TC3").finish() + } +} +#[doc = "Basic Timer Counter"] +pub use tc0 as tc3; +#[doc = "Basic Timer Counter"] +pub struct TC4 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TC4 {} +impl TC4 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tc0::RegisterBlock = 0x4200_4000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tc0::RegisterBlock { + Self::PTR + } +} +impl Deref for TC4 { + type Target = tc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TC4 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TC4").finish() + } +} +#[doc = "Basic Timer Counter"] +pub use tc0 as tc4; +#[doc = "Basic Timer Counter"] +pub struct TC5 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TC5 {} +impl TC5 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tc0::RegisterBlock = 0x4300_0800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tc0::RegisterBlock { + Self::PTR + } +} +impl Deref for TC5 { + type Target = tc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TC5 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TC5").finish() + } +} +#[doc = "Basic Timer Counter"] +pub use tc0 as tc5; +#[doc = "Basic Timer Counter"] +pub struct TC6 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TC6 {} +impl TC6 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tc0::RegisterBlock = 0x4300_0c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tc0::RegisterBlock { + Self::PTR + } +} +impl Deref for TC6 { + type Target = tc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TC6 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TC6").finish() + } +} +#[doc = "Basic Timer Counter"] +pub use tc0 as tc6; +#[doc = "Basic Timer Counter"] +pub struct TC7 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TC7 {} +impl TC7 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tc0::RegisterBlock = 0x4300_1000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tc0::RegisterBlock { + Self::PTR + } +} +impl Deref for TC7 { + type Target = tc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TC7 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TC7").finish() + } +} +#[doc = "Basic Timer Counter"] +pub use tc0 as tc7; +#[doc = "Timer Counter Control"] +pub struct TCC0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TCC0 {} +impl TCC0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tcc0::RegisterBlock = 0x4200_2400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tcc0::RegisterBlock { + Self::PTR + } +} +impl Deref for TCC0 { + type Target = tcc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TCC0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TCC0").finish() + } +} +#[doc = "Timer Counter Control"] +pub mod tcc0; +#[doc = "Timer Counter Control"] +pub struct TCC1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TCC1 {} +impl TCC1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tcc0::RegisterBlock = 0x4200_2800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tcc0::RegisterBlock { + Self::PTR + } +} +impl Deref for TCC1 { + type Target = tcc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TCC1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TCC1").finish() + } +} +#[doc = "Timer Counter Control"] +pub use tcc0 as tcc1; +#[doc = "Timer Counter Control"] +pub struct TCC2 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TCC2 {} +impl TCC2 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tcc0::RegisterBlock = 0x4200_2c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tcc0::RegisterBlock { + Self::PTR + } +} +impl Deref for TCC2 { + type Target = tcc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TCC2 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TCC2").finish() + } +} +#[doc = "Timer Counter Control"] +pub use tcc0 as tcc2; +#[doc = "Temperature Sensor"] +pub struct TSENS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TSENS {} +impl TSENS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tsens::RegisterBlock = 0x4000_3000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tsens::RegisterBlock { + Self::PTR + } +} +impl Deref for TSENS { + type Target = tsens::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TSENS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TSENS").finish() + } +} +#[doc = "Temperature Sensor"] +pub mod tsens; +#[doc = "Watchdog Timer"] +pub struct WDT { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for WDT {} +impl WDT { + #[doc = r"Pointer to the register block"] + pub const PTR: *const wdt::RegisterBlock = 0x4000_2000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const wdt::RegisterBlock { + Self::PTR + } +} +impl Deref for WDT { + type Target = wdt::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for WDT { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("WDT").finish() + } +} +#[doc = "Watchdog Timer"] +pub mod wdt; +#[doc = "System timer"] +pub struct SYSTICK { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SYSTICK {} +impl SYSTICK { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sys_tick::RegisterBlock = 0xe000_e010 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sys_tick::RegisterBlock { + Self::PTR + } +} +impl Deref for SYSTICK { + type Target = sys_tick::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SYSTICK { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SYSTICK").finish() + } +} +#[doc = "System timer"] +pub mod sys_tick; +#[doc = "System Control Registers"] +pub struct SYSTEMCONTROL { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SYSTEMCONTROL {} +impl SYSTEMCONTROL { + #[doc = r"Pointer to the register block"] + pub const PTR: *const system_control::RegisterBlock = 0xe000_e000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const system_control::RegisterBlock { + Self::PTR + } +} +impl Deref for SYSTEMCONTROL { + type Target = system_control::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SYSTEMCONTROL { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SYSTEMCONTROL").finish() + } +} +#[doc = "System Control Registers"] +pub mod system_control; +#[no_mangle] +static mut DEVICE_PERIPHERALS: bool = false; +#[doc = r"All the peripherals"] +#[allow(non_snake_case)] +pub struct Peripherals { + #[doc = "AC"] + pub AC: AC, + #[doc = "ADC0"] + pub ADC0: ADC0, + #[doc = "ADC1"] + pub ADC1: ADC1, + #[doc = "CAN0"] + pub CAN0: CAN0, + #[doc = "CAN1"] + pub CAN1: CAN1, + #[doc = "CCL"] + pub CCL: CCL, + #[doc = "DAC"] + pub DAC: DAC, + #[doc = "DIVAS"] + pub DIVAS: DIVAS, + #[doc = "DMAC"] + pub DMAC: DMAC, + #[doc = "DSU"] + pub DSU: DSU, + #[doc = "EIC"] + pub EIC: EIC, + #[doc = "EVSYS"] + pub EVSYS: EVSYS, + #[doc = "FREQM"] + pub FREQM: FREQM, + #[doc = "GCLK"] + pub GCLK: GCLK, + #[doc = "HMATRIXHS"] + pub HMATRIXHS: HMATRIXHS, + #[doc = "MCLK"] + pub MCLK: MCLK, + #[doc = "MTB"] + pub MTB: MTB, + #[doc = "NVMCTRL"] + pub NVMCTRL: NVMCTRL, + #[doc = "OSCCTRL"] + pub OSCCTRL: OSCCTRL, + #[doc = "OSC32KCTRL"] + pub OSC32KCTRL: OSC32KCTRL, + #[doc = "PAC"] + pub PAC: PAC, + #[doc = "PM"] + pub PM: PM, + #[doc = "PORT"] + pub PORT: PORT, + #[doc = "PORT_IOBUS"] + pub PORT_IOBUS: PORT_IOBUS, + #[doc = "RSTC"] + pub RSTC: RSTC, + #[doc = "RTC"] + pub RTC: RTC, + #[doc = "SDADC"] + pub SDADC: SDADC, + #[doc = "SERCOM0"] + pub SERCOM0: SERCOM0, + #[doc = "SERCOM1"] + pub SERCOM1: SERCOM1, + #[doc = "SERCOM2"] + pub SERCOM2: SERCOM2, + #[doc = "SERCOM3"] + pub SERCOM3: SERCOM3, + #[doc = "SERCOM4"] + pub SERCOM4: SERCOM4, + #[doc = "SERCOM5"] + pub SERCOM5: SERCOM5, + #[doc = "SERCOM6"] + pub SERCOM6: SERCOM6, + #[doc = "SERCOM7"] + pub SERCOM7: SERCOM7, + #[doc = "SUPC"] + pub SUPC: SUPC, + #[doc = "TC0"] + pub TC0: TC0, + #[doc = "TC1"] + pub TC1: TC1, + #[doc = "TC2"] + pub TC2: TC2, + #[doc = "TC3"] + pub TC3: TC3, + #[doc = "TC4"] + pub TC4: TC4, + #[doc = "TC5"] + pub TC5: TC5, + #[doc = "TC6"] + pub TC6: TC6, + #[doc = "TC7"] + pub TC7: TC7, + #[doc = "TCC0"] + pub TCC0: TCC0, + #[doc = "TCC1"] + pub TCC1: TCC1, + #[doc = "TCC2"] + pub TCC2: TCC2, + #[doc = "TSENS"] + pub TSENS: TSENS, + #[doc = "WDT"] + pub WDT: WDT, + #[doc = "SYSTICK"] + pub SYSTICK: SYSTICK, + #[doc = "SYSTEMCONTROL"] + pub SYSTEMCONTROL: SYSTEMCONTROL, +} +impl Peripherals { + #[doc = r"Returns all the peripherals *once*"] + #[inline] + pub fn take() -> Option { + cortex_m::interrupt::free(|_| { + if unsafe { DEVICE_PERIPHERALS } { + None + } else { + Some(unsafe { Peripherals::steal() }) + } + }) + } + #[doc = r"Unchecked version of `Peripherals::take`"] + #[inline] + pub unsafe fn steal() -> Self { + DEVICE_PERIPHERALS = true; + Peripherals { + AC: AC { + _marker: PhantomData, + }, + ADC0: ADC0 { + _marker: PhantomData, + }, + ADC1: ADC1 { + _marker: PhantomData, + }, + CAN0: CAN0 { + _marker: PhantomData, + }, + CAN1: CAN1 { + _marker: PhantomData, + }, + CCL: CCL { + _marker: PhantomData, + }, + DAC: DAC { + _marker: PhantomData, + }, + DIVAS: DIVAS { + _marker: PhantomData, + }, + DMAC: DMAC { + _marker: PhantomData, + }, + DSU: DSU { + _marker: PhantomData, + }, + EIC: EIC { + _marker: PhantomData, + }, + EVSYS: EVSYS { + _marker: PhantomData, + }, + FREQM: FREQM { + _marker: PhantomData, + }, + GCLK: GCLK { + _marker: PhantomData, + }, + HMATRIXHS: HMATRIXHS { + _marker: PhantomData, + }, + MCLK: MCLK { + _marker: PhantomData, + }, + MTB: MTB { + _marker: PhantomData, + }, + NVMCTRL: NVMCTRL { + _marker: PhantomData, + }, + OSCCTRL: OSCCTRL { + _marker: PhantomData, + }, + OSC32KCTRL: OSC32KCTRL { + _marker: PhantomData, + }, + PAC: PAC { + _marker: PhantomData, + }, + PM: PM { + _marker: PhantomData, + }, + PORT: PORT { + _marker: PhantomData, + }, + PORT_IOBUS: PORT_IOBUS { + _marker: PhantomData, + }, + RSTC: RSTC { + _marker: PhantomData, + }, + RTC: RTC { + _marker: PhantomData, + }, + SDADC: SDADC { + _marker: PhantomData, + }, + SERCOM0: SERCOM0 { + _marker: PhantomData, + }, + SERCOM1: SERCOM1 { + _marker: PhantomData, + }, + SERCOM2: SERCOM2 { + _marker: PhantomData, + }, + SERCOM3: SERCOM3 { + _marker: PhantomData, + }, + SERCOM4: SERCOM4 { + _marker: PhantomData, + }, + SERCOM5: SERCOM5 { + _marker: PhantomData, + }, + SERCOM6: SERCOM6 { + _marker: PhantomData, + }, + SERCOM7: SERCOM7 { + _marker: PhantomData, + }, + SUPC: SUPC { + _marker: PhantomData, + }, + TC0: TC0 { + _marker: PhantomData, + }, + TC1: TC1 { + _marker: PhantomData, + }, + TC2: TC2 { + _marker: PhantomData, + }, + TC3: TC3 { + _marker: PhantomData, + }, + TC4: TC4 { + _marker: PhantomData, + }, + TC5: TC5 { + _marker: PhantomData, + }, + TC6: TC6 { + _marker: PhantomData, + }, + TC7: TC7 { + _marker: PhantomData, + }, + TCC0: TCC0 { + _marker: PhantomData, + }, + TCC1: TCC1 { + _marker: PhantomData, + }, + TCC2: TCC2 { + _marker: PhantomData, + }, + TSENS: TSENS { + _marker: PhantomData, + }, + WDT: WDT { + _marker: PhantomData, + }, + SYSTICK: SYSTICK { + _marker: PhantomData, + }, + SYSTEMCONTROL: SYSTEMCONTROL { + _marker: PhantomData, + }, + } + } +} diff --git a/pac/atsamc21n/src/mclk.rs b/pac/atsamc21n/src/mclk.rs new file mode 100644 index 000000000000..2713af2692b7 --- /dev/null +++ b/pac/atsamc21n/src/mclk.rs @@ -0,0 +1,60 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved0: [u8; 0x01], + #[doc = "0x01 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x02 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x03 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x04 - CPU Clock Division"] + pub cpudiv: crate::Reg, + _reserved4: [u8; 0x0b], + #[doc = "0x10 - AHB Mask"] + pub ahbmask: crate::Reg, + #[doc = "0x14 - APBA Mask"] + pub apbamask: crate::Reg, + #[doc = "0x18 - APBB Mask"] + pub apbbmask: crate::Reg, + #[doc = "0x1c - APBC Mask"] + pub apbcmask: crate::Reg, + #[doc = "0x20 - APBD Mask"] + pub apbdmask: crate::Reg, +} +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "CPUDIV register accessor: an alias for `Reg`"] +pub type CPUDIV = crate::Reg; +#[doc = "CPU Clock Division"] +pub mod cpudiv; +#[doc = "AHBMASK register accessor: an alias for `Reg`"] +pub type AHBMASK = crate::Reg; +#[doc = "AHB Mask"] +pub mod ahbmask; +#[doc = "APBAMASK register accessor: an alias for `Reg`"] +pub type APBAMASK = crate::Reg; +#[doc = "APBA Mask"] +pub mod apbamask; +#[doc = "APBBMASK register accessor: an alias for `Reg`"] +pub type APBBMASK = crate::Reg; +#[doc = "APBB Mask"] +pub mod apbbmask; +#[doc = "APBCMASK register accessor: an alias for `Reg`"] +pub type APBCMASK = crate::Reg; +#[doc = "APBC Mask"] +pub mod apbcmask; +#[doc = "APBDMASK register accessor: an alias for `Reg`"] +pub type APBDMASK = crate::Reg; +#[doc = "APBD Mask"] +pub mod apbdmask; diff --git a/pac/atsamc21n/src/mclk/ahbmask.rs b/pac/atsamc21n/src/mclk/ahbmask.rs new file mode 100644 index 000000000000..32a115d88947 --- /dev/null +++ b/pac/atsamc21n/src/mclk/ahbmask.rs @@ -0,0 +1,724 @@ +#[doc = "Register `AHBMASK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `AHBMASK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `HPB0_` reader - HPB0 AHB Clock Mask"] +pub struct HPB0__R(crate::FieldReader); +impl HPB0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HPB0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HPB0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HPB0_` writer - HPB0 AHB Clock Mask"] +pub struct HPB0__W<'a> { + w: &'a mut W, +} +impl<'a> HPB0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `HPB1_` reader - HPB1 AHB Clock Mask"] +pub struct HPB1__R(crate::FieldReader); +impl HPB1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HPB1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HPB1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HPB1_` writer - HPB1 AHB Clock Mask"] +pub struct HPB1__W<'a> { + w: &'a mut W, +} +impl<'a> HPB1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `HPB2_` reader - HPB2 AHB Clock Mask"] +pub struct HPB2__R(crate::FieldReader); +impl HPB2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HPB2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HPB2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HPB2_` writer - HPB2 AHB Clock Mask"] +pub struct HPB2__W<'a> { + w: &'a mut W, +} +impl<'a> HPB2__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `DSU_` reader - DSU AHB Clock Mask"] +pub struct DSU__R(crate::FieldReader); +impl DSU__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DSU__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DSU__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DSU_` writer - DSU AHB Clock Mask"] +pub struct DSU__W<'a> { + w: &'a mut W, +} +impl<'a> DSU__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `HMATRIXHS_` reader - HMATRIXHS AHB Clock Mask"] +pub struct HMATRIXHS__R(crate::FieldReader); +impl HMATRIXHS__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HMATRIXHS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HMATRIXHS__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HMATRIXHS_` writer - HMATRIXHS AHB Clock Mask"] +pub struct HMATRIXHS__W<'a> { + w: &'a mut W, +} +impl<'a> HMATRIXHS__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `NVMCTRL_` reader - NVMCTRL AHB Clock Mask"] +pub struct NVMCTRL__R(crate::FieldReader); +impl NVMCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NVMCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NVMCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NVMCTRL_` writer - NVMCTRL AHB Clock Mask"] +pub struct NVMCTRL__W<'a> { + w: &'a mut W, +} +impl<'a> NVMCTRL__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `HSRAM_` reader - HSRAM AHB Clock Mask"] +pub struct HSRAM__R(crate::FieldReader); +impl HSRAM__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HSRAM__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HSRAM__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HSRAM_` writer - HSRAM AHB Clock Mask"] +pub struct HSRAM__W<'a> { + w: &'a mut W, +} +impl<'a> HSRAM__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `DMAC_` reader - DMAC AHB Clock Mask"] +pub struct DMAC__R(crate::FieldReader); +impl DMAC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DMAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DMAC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DMAC_` writer - DMAC AHB Clock Mask"] +pub struct DMAC__W<'a> { + w: &'a mut W, +} +impl<'a> DMAC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CAN0_` reader - CAN0 AHB Clock Mask"] +pub struct CAN0__R(crate::FieldReader); +impl CAN0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CAN0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CAN0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAN0_` writer - CAN0 AHB Clock Mask"] +pub struct CAN0__W<'a> { + w: &'a mut W, +} +impl<'a> CAN0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `CAN1_` reader - CAN1 AHB Clock Mask"] +pub struct CAN1__R(crate::FieldReader); +impl CAN1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CAN1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CAN1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAN1_` writer - CAN1 AHB Clock Mask"] +pub struct CAN1__W<'a> { + w: &'a mut W, +} +impl<'a> CAN1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `PAC_` reader - PAC AHB Clock Mask"] +pub struct PAC__R(crate::FieldReader); +impl PAC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PAC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PAC_` writer - PAC AHB Clock Mask"] +pub struct PAC__W<'a> { + w: &'a mut W, +} +impl<'a> PAC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `NVMCTRL_PICACHU_` reader - NVMCTRL_PICACHU AHB Clock Mask"] +pub struct NVMCTRL_PICACHU__R(crate::FieldReader); +impl NVMCTRL_PICACHU__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NVMCTRL_PICACHU__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NVMCTRL_PICACHU__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NVMCTRL_PICACHU_` writer - NVMCTRL_PICACHU AHB Clock Mask"] +pub struct NVMCTRL_PICACHU__W<'a> { + w: &'a mut W, +} +impl<'a> NVMCTRL_PICACHU__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `DIVAS_` reader - DIVAS AHB Clock Mask"] +pub struct DIVAS__R(crate::FieldReader); +impl DIVAS__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIVAS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIVAS__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIVAS_` writer - DIVAS AHB Clock Mask"] +pub struct DIVAS__W<'a> { + w: &'a mut W, +} +impl<'a> DIVAS__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `HPB3_` reader - HPB3 AHB Clock Mask"] +pub struct HPB3__R(crate::FieldReader); +impl HPB3__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HPB3__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HPB3__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HPB3_` writer - HPB3 AHB Clock Mask"] +pub struct HPB3__W<'a> { + w: &'a mut W, +} +impl<'a> HPB3__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +impl R { + #[doc = "Bit 0 - HPB0 AHB Clock Mask"] + #[inline(always)] + pub fn hpb0_(&self) -> HPB0__R { + HPB0__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - HPB1 AHB Clock Mask"] + #[inline(always)] + pub fn hpb1_(&self) -> HPB1__R { + HPB1__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - HPB2 AHB Clock Mask"] + #[inline(always)] + pub fn hpb2_(&self) -> HPB2__R { + HPB2__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - DSU AHB Clock Mask"] + #[inline(always)] + pub fn dsu_(&self) -> DSU__R { + DSU__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - HMATRIXHS AHB Clock Mask"] + #[inline(always)] + pub fn hmatrixhs_(&self) -> HMATRIXHS__R { + HMATRIXHS__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - NVMCTRL AHB Clock Mask"] + #[inline(always)] + pub fn nvmctrl_(&self) -> NVMCTRL__R { + NVMCTRL__R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - HSRAM AHB Clock Mask"] + #[inline(always)] + pub fn hsram_(&self) -> HSRAM__R { + HSRAM__R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - DMAC AHB Clock Mask"] + #[inline(always)] + pub fn dmac_(&self) -> DMAC__R { + DMAC__R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - CAN0 AHB Clock Mask"] + #[inline(always)] + pub fn can0_(&self) -> CAN0__R { + CAN0__R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - CAN1 AHB Clock Mask"] + #[inline(always)] + pub fn can1_(&self) -> CAN1__R { + CAN1__R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - PAC AHB Clock Mask"] + #[inline(always)] + pub fn pac_(&self) -> PAC__R { + PAC__R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - NVMCTRL_PICACHU AHB Clock Mask"] + #[inline(always)] + pub fn nvmctrl_picachu_(&self) -> NVMCTRL_PICACHU__R { + NVMCTRL_PICACHU__R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - DIVAS AHB Clock Mask"] + #[inline(always)] + pub fn divas_(&self) -> DIVAS__R { + DIVAS__R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - HPB3 AHB Clock Mask"] + #[inline(always)] + pub fn hpb3_(&self) -> HPB3__R { + HPB3__R::new(((self.bits >> 13) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - HPB0 AHB Clock Mask"] + #[inline(always)] + pub fn hpb0_(&mut self) -> HPB0__W { + HPB0__W { w: self } + } + #[doc = "Bit 1 - HPB1 AHB Clock Mask"] + #[inline(always)] + pub fn hpb1_(&mut self) -> HPB1__W { + HPB1__W { w: self } + } + #[doc = "Bit 2 - HPB2 AHB Clock Mask"] + #[inline(always)] + pub fn hpb2_(&mut self) -> HPB2__W { + HPB2__W { w: self } + } + #[doc = "Bit 3 - DSU AHB Clock Mask"] + #[inline(always)] + pub fn dsu_(&mut self) -> DSU__W { + DSU__W { w: self } + } + #[doc = "Bit 4 - HMATRIXHS AHB Clock Mask"] + #[inline(always)] + pub fn hmatrixhs_(&mut self) -> HMATRIXHS__W { + HMATRIXHS__W { w: self } + } + #[doc = "Bit 5 - NVMCTRL AHB Clock Mask"] + #[inline(always)] + pub fn nvmctrl_(&mut self) -> NVMCTRL__W { + NVMCTRL__W { w: self } + } + #[doc = "Bit 6 - HSRAM AHB Clock Mask"] + #[inline(always)] + pub fn hsram_(&mut self) -> HSRAM__W { + HSRAM__W { w: self } + } + #[doc = "Bit 7 - DMAC AHB Clock Mask"] + #[inline(always)] + pub fn dmac_(&mut self) -> DMAC__W { + DMAC__W { w: self } + } + #[doc = "Bit 8 - CAN0 AHB Clock Mask"] + #[inline(always)] + pub fn can0_(&mut self) -> CAN0__W { + CAN0__W { w: self } + } + #[doc = "Bit 9 - CAN1 AHB Clock Mask"] + #[inline(always)] + pub fn can1_(&mut self) -> CAN1__W { + CAN1__W { w: self } + } + #[doc = "Bit 10 - PAC AHB Clock Mask"] + #[inline(always)] + pub fn pac_(&mut self) -> PAC__W { + PAC__W { w: self } + } + #[doc = "Bit 11 - NVMCTRL_PICACHU AHB Clock Mask"] + #[inline(always)] + pub fn nvmctrl_picachu_(&mut self) -> NVMCTRL_PICACHU__W { + NVMCTRL_PICACHU__W { w: self } + } + #[doc = "Bit 12 - DIVAS AHB Clock Mask"] + #[inline(always)] + pub fn divas_(&mut self) -> DIVAS__W { + DIVAS__W { w: self } + } + #[doc = "Bit 13 - HPB3 AHB Clock Mask"] + #[inline(always)] + pub fn hpb3_(&mut self) -> HPB3__W { + HPB3__W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "AHB Mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ahbmask](index.html) module"] +pub struct AHBMASK_SPEC; +impl crate::RegisterSpec for AHBMASK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ahbmask::R](R) reader structure"] +impl crate::Readable for AHBMASK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ahbmask::W](W) writer structure"] +impl crate::Writable for AHBMASK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets AHBMASK to value 0x3cff"] +impl crate::Resettable for AHBMASK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x3cff + } +} diff --git a/pac/atsamc21n/src/mclk/apbamask.rs b/pac/atsamc21n/src/mclk/apbamask.rs new file mode 100644 index 000000000000..144b1163d5cb --- /dev/null +++ b/pac/atsamc21n/src/mclk/apbamask.rs @@ -0,0 +1,677 @@ +#[doc = "Register `APBAMASK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `APBAMASK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PAC_` reader - PAC APB Clock Enable"] +pub struct PAC__R(crate::FieldReader); +impl PAC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PAC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PAC_` writer - PAC APB Clock Enable"] +pub struct PAC__W<'a> { + w: &'a mut W, +} +impl<'a> PAC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `PM_` reader - PM APB Clock Enable"] +pub struct PM__R(crate::FieldReader); +impl PM__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PM__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PM__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PM_` writer - PM APB Clock Enable"] +pub struct PM__W<'a> { + w: &'a mut W, +} +impl<'a> PM__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MCLK_` reader - MCLK APB Clock Enable"] +pub struct MCLK__R(crate::FieldReader); +impl MCLK__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCLK__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCLK__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCLK_` writer - MCLK APB Clock Enable"] +pub struct MCLK__W<'a> { + w: &'a mut W, +} +impl<'a> MCLK__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RSTC_` reader - RSTC APB Clock Enable"] +pub struct RSTC__R(crate::FieldReader); +impl RSTC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RSTC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RSTC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RSTC_` writer - RSTC APB Clock Enable"] +pub struct RSTC__W<'a> { + w: &'a mut W, +} +impl<'a> RSTC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `OSCCTRL_` reader - OSCCTRL APB Clock Enable"] +pub struct OSCCTRL__R(crate::FieldReader); +impl OSCCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSCCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSCCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSCCTRL_` writer - OSCCTRL APB Clock Enable"] +pub struct OSCCTRL__W<'a> { + w: &'a mut W, +} +impl<'a> OSCCTRL__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `OSC32KCTRL_` reader - OSC32KCTRL APB Clock Enable"] +pub struct OSC32KCTRL__R(crate::FieldReader); +impl OSC32KCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC32KCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC32KCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC32KCTRL_` writer - OSC32KCTRL APB Clock Enable"] +pub struct OSC32KCTRL__W<'a> { + w: &'a mut W, +} +impl<'a> OSC32KCTRL__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `SUPC_` reader - SUPC APB Clock Enable"] +pub struct SUPC__R(crate::FieldReader); +impl SUPC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SUPC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SUPC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SUPC_` writer - SUPC APB Clock Enable"] +pub struct SUPC__W<'a> { + w: &'a mut W, +} +impl<'a> SUPC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `GCLK_` reader - GCLK APB Clock Enable"] +pub struct GCLK__R(crate::FieldReader); +impl GCLK__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GCLK__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GCLK__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GCLK_` writer - GCLK APB Clock Enable"] +pub struct GCLK__W<'a> { + w: &'a mut W, +} +impl<'a> GCLK__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `WDT_` reader - WDT APB Clock Enable"] +pub struct WDT__R(crate::FieldReader); +impl WDT__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WDT__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WDT__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WDT_` writer - WDT APB Clock Enable"] +pub struct WDT__W<'a> { + w: &'a mut W, +} +impl<'a> WDT__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `RTC_` reader - RTC APB Clock Enable"] +pub struct RTC__R(crate::FieldReader); +impl RTC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RTC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RTC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RTC_` writer - RTC APB Clock Enable"] +pub struct RTC__W<'a> { + w: &'a mut W, +} +impl<'a> RTC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `EIC_` reader - EIC APB Clock Enable"] +pub struct EIC__R(crate::FieldReader); +impl EIC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EIC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EIC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EIC_` writer - EIC APB Clock Enable"] +pub struct EIC__W<'a> { + w: &'a mut W, +} +impl<'a> EIC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `FREQM_` reader - FREQM APB Clock Enable"] +pub struct FREQM__R(crate::FieldReader); +impl FREQM__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FREQM__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FREQM__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FREQM_` writer - FREQM APB Clock Enable"] +pub struct FREQM__W<'a> { + w: &'a mut W, +} +impl<'a> FREQM__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `TSENS_` reader - TSENS APB Clock Enable"] +pub struct TSENS__R(crate::FieldReader); +impl TSENS__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSENS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSENS__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSENS_` writer - TSENS APB Clock Enable"] +pub struct TSENS__W<'a> { + w: &'a mut W, +} +impl<'a> TSENS__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +impl R { + #[doc = "Bit 0 - PAC APB Clock Enable"] + #[inline(always)] + pub fn pac_(&self) -> PAC__R { + PAC__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - PM APB Clock Enable"] + #[inline(always)] + pub fn pm_(&self) -> PM__R { + PM__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - MCLK APB Clock Enable"] + #[inline(always)] + pub fn mclk_(&self) -> MCLK__R { + MCLK__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - RSTC APB Clock Enable"] + #[inline(always)] + pub fn rstc_(&self) -> RSTC__R { + RSTC__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - OSCCTRL APB Clock Enable"] + #[inline(always)] + pub fn oscctrl_(&self) -> OSCCTRL__R { + OSCCTRL__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - OSC32KCTRL APB Clock Enable"] + #[inline(always)] + pub fn osc32kctrl_(&self) -> OSC32KCTRL__R { + OSC32KCTRL__R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - SUPC APB Clock Enable"] + #[inline(always)] + pub fn supc_(&self) -> SUPC__R { + SUPC__R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - GCLK APB Clock Enable"] + #[inline(always)] + pub fn gclk_(&self) -> GCLK__R { + GCLK__R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - WDT APB Clock Enable"] + #[inline(always)] + pub fn wdt_(&self) -> WDT__R { + WDT__R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - RTC APB Clock Enable"] + #[inline(always)] + pub fn rtc_(&self) -> RTC__R { + RTC__R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - EIC APB Clock Enable"] + #[inline(always)] + pub fn eic_(&self) -> EIC__R { + EIC__R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - FREQM APB Clock Enable"] + #[inline(always)] + pub fn freqm_(&self) -> FREQM__R { + FREQM__R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - TSENS APB Clock Enable"] + #[inline(always)] + pub fn tsens_(&self) -> TSENS__R { + TSENS__R::new(((self.bits >> 12) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - PAC APB Clock Enable"] + #[inline(always)] + pub fn pac_(&mut self) -> PAC__W { + PAC__W { w: self } + } + #[doc = "Bit 1 - PM APB Clock Enable"] + #[inline(always)] + pub fn pm_(&mut self) -> PM__W { + PM__W { w: self } + } + #[doc = "Bit 2 - MCLK APB Clock Enable"] + #[inline(always)] + pub fn mclk_(&mut self) -> MCLK__W { + MCLK__W { w: self } + } + #[doc = "Bit 3 - RSTC APB Clock Enable"] + #[inline(always)] + pub fn rstc_(&mut self) -> RSTC__W { + RSTC__W { w: self } + } + #[doc = "Bit 4 - OSCCTRL APB Clock Enable"] + #[inline(always)] + pub fn oscctrl_(&mut self) -> OSCCTRL__W { + OSCCTRL__W { w: self } + } + #[doc = "Bit 5 - OSC32KCTRL APB Clock Enable"] + #[inline(always)] + pub fn osc32kctrl_(&mut self) -> OSC32KCTRL__W { + OSC32KCTRL__W { w: self } + } + #[doc = "Bit 6 - SUPC APB Clock Enable"] + #[inline(always)] + pub fn supc_(&mut self) -> SUPC__W { + SUPC__W { w: self } + } + #[doc = "Bit 7 - GCLK APB Clock Enable"] + #[inline(always)] + pub fn gclk_(&mut self) -> GCLK__W { + GCLK__W { w: self } + } + #[doc = "Bit 8 - WDT APB Clock Enable"] + #[inline(always)] + pub fn wdt_(&mut self) -> WDT__W { + WDT__W { w: self } + } + #[doc = "Bit 9 - RTC APB Clock Enable"] + #[inline(always)] + pub fn rtc_(&mut self) -> RTC__W { + RTC__W { w: self } + } + #[doc = "Bit 10 - EIC APB Clock Enable"] + #[inline(always)] + pub fn eic_(&mut self) -> EIC__W { + EIC__W { w: self } + } + #[doc = "Bit 11 - FREQM APB Clock Enable"] + #[inline(always)] + pub fn freqm_(&mut self) -> FREQM__W { + FREQM__W { w: self } + } + #[doc = "Bit 12 - TSENS APB Clock Enable"] + #[inline(always)] + pub fn tsens_(&mut self) -> TSENS__W { + TSENS__W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "APBA Mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [apbamask](index.html) module"] +pub struct APBAMASK_SPEC; +impl crate::RegisterSpec for APBAMASK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [apbamask::R](R) reader structure"] +impl crate::Readable for APBAMASK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [apbamask::W](W) writer structure"] +impl crate::Writable for APBAMASK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets APBAMASK to value 0x0fff"] +impl crate::Resettable for APBAMASK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0fff + } +} diff --git a/pac/atsamc21n/src/mclk/apbbmask.rs b/pac/atsamc21n/src/mclk/apbbmask.rs new file mode 100644 index 000000000000..e1ec6b1f2323 --- /dev/null +++ b/pac/atsamc21n/src/mclk/apbbmask.rs @@ -0,0 +1,254 @@ +#[doc = "Register `APBBMASK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `APBBMASK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PORT_` reader - PORT APB Clock Enable"] +pub struct PORT__R(crate::FieldReader); +impl PORT__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PORT__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PORT__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PORT_` writer - PORT APB Clock Enable"] +pub struct PORT__W<'a> { + w: &'a mut W, +} +impl<'a> PORT__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `DSU_` reader - DSU APB Clock Enable"] +pub struct DSU__R(crate::FieldReader); +impl DSU__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DSU__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DSU__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DSU_` writer - DSU APB Clock Enable"] +pub struct DSU__W<'a> { + w: &'a mut W, +} +impl<'a> DSU__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `NVMCTRL_` reader - NVMCTRL APB Clock Enable"] +pub struct NVMCTRL__R(crate::FieldReader); +impl NVMCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NVMCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NVMCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NVMCTRL_` writer - NVMCTRL APB Clock Enable"] +pub struct NVMCTRL__W<'a> { + w: &'a mut W, +} +impl<'a> NVMCTRL__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `HMATRIXHS_` reader - HMATRIXHS APB Clock Enable"] +pub struct HMATRIXHS__R(crate::FieldReader); +impl HMATRIXHS__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HMATRIXHS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HMATRIXHS__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HMATRIXHS_` writer - HMATRIXHS APB Clock Enable"] +pub struct HMATRIXHS__W<'a> { + w: &'a mut W, +} +impl<'a> HMATRIXHS__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - PORT APB Clock Enable"] + #[inline(always)] + pub fn port_(&self) -> PORT__R { + PORT__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - DSU APB Clock Enable"] + #[inline(always)] + pub fn dsu_(&self) -> DSU__R { + DSU__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - NVMCTRL APB Clock Enable"] + #[inline(always)] + pub fn nvmctrl_(&self) -> NVMCTRL__R { + NVMCTRL__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 5 - HMATRIXHS APB Clock Enable"] + #[inline(always)] + pub fn hmatrixhs_(&self) -> HMATRIXHS__R { + HMATRIXHS__R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - PORT APB Clock Enable"] + #[inline(always)] + pub fn port_(&mut self) -> PORT__W { + PORT__W { w: self } + } + #[doc = "Bit 1 - DSU APB Clock Enable"] + #[inline(always)] + pub fn dsu_(&mut self) -> DSU__W { + DSU__W { w: self } + } + #[doc = "Bit 2 - NVMCTRL APB Clock Enable"] + #[inline(always)] + pub fn nvmctrl_(&mut self) -> NVMCTRL__W { + NVMCTRL__W { w: self } + } + #[doc = "Bit 5 - HMATRIXHS APB Clock Enable"] + #[inline(always)] + pub fn hmatrixhs_(&mut self) -> HMATRIXHS__W { + HMATRIXHS__W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "APBB Mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [apbbmask](index.html) module"] +pub struct APBBMASK_SPEC; +impl crate::RegisterSpec for APBBMASK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [apbbmask::R](R) reader structure"] +impl crate::Readable for APBBMASK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [apbbmask::W](W) writer structure"] +impl crate::Writable for APBBMASK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets APBBMASK to value 0x07"] +impl crate::Resettable for APBBMASK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x07 + } +} diff --git a/pac/atsamc21n/src/mclk/apbcmask.rs b/pac/atsamc21n/src/mclk/apbcmask.rs new file mode 100644 index 000000000000..04e63311c88e --- /dev/null +++ b/pac/atsamc21n/src/mclk/apbcmask.rs @@ -0,0 +1,1100 @@ +#[doc = "Register `APBCMASK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `APBCMASK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVSYS_` reader - EVSYS APB Clock Enable"] +pub struct EVSYS__R(crate::FieldReader); +impl EVSYS__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVSYS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVSYS__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVSYS_` writer - EVSYS APB Clock Enable"] +pub struct EVSYS__W<'a> { + w: &'a mut W, +} +impl<'a> EVSYS__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `SERCOM0_` reader - SERCOM0 APB Clock Enable"] +pub struct SERCOM0__R(crate::FieldReader); +impl SERCOM0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM0_` writer - SERCOM0 APB Clock Enable"] +pub struct SERCOM0__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SERCOM1_` reader - SERCOM1 APB Clock Enable"] +pub struct SERCOM1__R(crate::FieldReader); +impl SERCOM1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM1_` writer - SERCOM1 APB Clock Enable"] +pub struct SERCOM1__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SERCOM2_` reader - SERCOM2 APB Clock Enable"] +pub struct SERCOM2__R(crate::FieldReader); +impl SERCOM2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM2_` writer - SERCOM2 APB Clock Enable"] +pub struct SERCOM2__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM2__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `SERCOM3_` reader - SERCOM3 APB Clock Enable"] +pub struct SERCOM3__R(crate::FieldReader); +impl SERCOM3__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM3__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM3__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM3_` writer - SERCOM3 APB Clock Enable"] +pub struct SERCOM3__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM3__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `SERCOM4_` reader - SERCOM4 APB Clock Enable"] +pub struct SERCOM4__R(crate::FieldReader); +impl SERCOM4__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM4__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM4__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM4_` writer - SERCOM4 APB Clock Enable"] +pub struct SERCOM4__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM4__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `SERCOM5_` reader - SERCOM5 APB Clock Enable"] +pub struct SERCOM5__R(crate::FieldReader); +impl SERCOM5__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM5__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM5__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM5_` writer - SERCOM5 APB Clock Enable"] +pub struct SERCOM5__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM5__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `TCC0_` reader - TCC0 APB Clock Enable"] +pub struct TCC0__R(crate::FieldReader); +impl TCC0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCC0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCC0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCC0_` writer - TCC0 APB Clock Enable"] +pub struct TCC0__W<'a> { + w: &'a mut W, +} +impl<'a> TCC0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `TCC1_` reader - TCC1 APB Clock Enable"] +pub struct TCC1__R(crate::FieldReader); +impl TCC1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCC1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCC1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCC1_` writer - TCC1 APB Clock Enable"] +pub struct TCC1__W<'a> { + w: &'a mut W, +} +impl<'a> TCC1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `TCC2_` reader - TCC2 APB Clock Enable"] +pub struct TCC2__R(crate::FieldReader); +impl TCC2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCC2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCC2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCC2_` writer - TCC2 APB Clock Enable"] +pub struct TCC2__W<'a> { + w: &'a mut W, +} +impl<'a> TCC2__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `TC0_` reader - TC0 APB Clock Enable"] +pub struct TC0__R(crate::FieldReader); +impl TC0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC0_` writer - TC0 APB Clock Enable"] +pub struct TC0__W<'a> { + w: &'a mut W, +} +impl<'a> TC0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `TC1_` reader - TC1 APB Clock Enable"] +pub struct TC1__R(crate::FieldReader); +impl TC1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC1_` writer - TC1 APB Clock Enable"] +pub struct TC1__W<'a> { + w: &'a mut W, +} +impl<'a> TC1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `TC2_` reader - TC2 APB Clock Enable"] +pub struct TC2__R(crate::FieldReader); +impl TC2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC2_` writer - TC2 APB Clock Enable"] +pub struct TC2__W<'a> { + w: &'a mut W, +} +impl<'a> TC2__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `TC3_` reader - TC3 APB Clock Enable"] +pub struct TC3__R(crate::FieldReader); +impl TC3__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC3__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC3__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC3_` writer - TC3 APB Clock Enable"] +pub struct TC3__W<'a> { + w: &'a mut W, +} +impl<'a> TC3__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `TC4_` reader - TC4 APB Clock Enable"] +pub struct TC4__R(crate::FieldReader); +impl TC4__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC4__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC4__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC4_` writer - TC4 APB Clock Enable"] +pub struct TC4__W<'a> { + w: &'a mut W, +} +impl<'a> TC4__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `ADC0_` reader - ADC0 APB Clock Enable"] +pub struct ADC0__R(crate::FieldReader); +impl ADC0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ADC0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADC0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADC0_` writer - ADC0 APB Clock Enable"] +pub struct ADC0__W<'a> { + w: &'a mut W, +} +impl<'a> ADC0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `ADC1_` reader - ADC1 APB Clock Enable"] +pub struct ADC1__R(crate::FieldReader); +impl ADC1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ADC1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADC1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADC1_` writer - ADC1 APB Clock Enable"] +pub struct ADC1__W<'a> { + w: &'a mut W, +} +impl<'a> ADC1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `SDADC_` reader - SDADC APB Clock Enable"] +pub struct SDADC__R(crate::FieldReader); +impl SDADC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SDADC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SDADC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SDADC_` writer - SDADC APB Clock Enable"] +pub struct SDADC__W<'a> { + w: &'a mut W, +} +impl<'a> SDADC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `AC_` reader - AC APB Clock Enable"] +pub struct AC__R(crate::FieldReader); +impl AC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AC_` writer - AC APB Clock Enable"] +pub struct AC__W<'a> { + w: &'a mut W, +} +impl<'a> AC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `DAC_` reader - DAC APB Clock Enable"] +pub struct DAC__R(crate::FieldReader); +impl DAC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DAC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DAC_` writer - DAC APB Clock Enable"] +pub struct DAC__W<'a> { + w: &'a mut W, +} +impl<'a> DAC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `PTC_` reader - PTC APB Clock Enable"] +pub struct PTC__R(crate::FieldReader); +impl PTC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PTC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PTC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PTC_` writer - PTC APB Clock Enable"] +pub struct PTC__W<'a> { + w: &'a mut W, +} +impl<'a> PTC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `CCL_` reader - CCL APB Clock Enable"] +pub struct CCL__R(crate::FieldReader); +impl CCL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCL_` writer - CCL APB Clock Enable"] +pub struct CCL__W<'a> { + w: &'a mut W, +} +impl<'a> CCL__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +impl R { + #[doc = "Bit 0 - EVSYS APB Clock Enable"] + #[inline(always)] + pub fn evsys_(&self) -> EVSYS__R { + EVSYS__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM0 APB Clock Enable"] + #[inline(always)] + pub fn sercom0_(&self) -> SERCOM0__R { + SERCOM0__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - SERCOM1 APB Clock Enable"] + #[inline(always)] + pub fn sercom1_(&self) -> SERCOM1__R { + SERCOM1__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - SERCOM2 APB Clock Enable"] + #[inline(always)] + pub fn sercom2_(&self) -> SERCOM2__R { + SERCOM2__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - SERCOM3 APB Clock Enable"] + #[inline(always)] + pub fn sercom3_(&self) -> SERCOM3__R { + SERCOM3__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - SERCOM4 APB Clock Enable"] + #[inline(always)] + pub fn sercom4_(&self) -> SERCOM4__R { + SERCOM4__R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - SERCOM5 APB Clock Enable"] + #[inline(always)] + pub fn sercom5_(&self) -> SERCOM5__R { + SERCOM5__R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 9 - TCC0 APB Clock Enable"] + #[inline(always)] + pub fn tcc0_(&self) -> TCC0__R { + TCC0__R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - TCC1 APB Clock Enable"] + #[inline(always)] + pub fn tcc1_(&self) -> TCC1__R { + TCC1__R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - TCC2 APB Clock Enable"] + #[inline(always)] + pub fn tcc2_(&self) -> TCC2__R { + TCC2__R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - TC0 APB Clock Enable"] + #[inline(always)] + pub fn tc0_(&self) -> TC0__R { + TC0__R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - TC1 APB Clock Enable"] + #[inline(always)] + pub fn tc1_(&self) -> TC1__R { + TC1__R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - TC2 APB Clock Enable"] + #[inline(always)] + pub fn tc2_(&self) -> TC2__R { + TC2__R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - TC3 APB Clock Enable"] + #[inline(always)] + pub fn tc3_(&self) -> TC3__R { + TC3__R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - TC4 APB Clock Enable"] + #[inline(always)] + pub fn tc4_(&self) -> TC4__R { + TC4__R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - ADC0 APB Clock Enable"] + #[inline(always)] + pub fn adc0_(&self) -> ADC0__R { + ADC0__R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - ADC1 APB Clock Enable"] + #[inline(always)] + pub fn adc1_(&self) -> ADC1__R { + ADC1__R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - SDADC APB Clock Enable"] + #[inline(always)] + pub fn sdadc_(&self) -> SDADC__R { + SDADC__R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - AC APB Clock Enable"] + #[inline(always)] + pub fn ac_(&self) -> AC__R { + AC__R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - DAC APB Clock Enable"] + #[inline(always)] + pub fn dac_(&self) -> DAC__R { + DAC__R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - PTC APB Clock Enable"] + #[inline(always)] + pub fn ptc_(&self) -> PTC__R { + PTC__R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - CCL APB Clock Enable"] + #[inline(always)] + pub fn ccl_(&self) -> CCL__R { + CCL__R::new(((self.bits >> 23) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - EVSYS APB Clock Enable"] + #[inline(always)] + pub fn evsys_(&mut self) -> EVSYS__W { + EVSYS__W { w: self } + } + #[doc = "Bit 1 - SERCOM0 APB Clock Enable"] + #[inline(always)] + pub fn sercom0_(&mut self) -> SERCOM0__W { + SERCOM0__W { w: self } + } + #[doc = "Bit 2 - SERCOM1 APB Clock Enable"] + #[inline(always)] + pub fn sercom1_(&mut self) -> SERCOM1__W { + SERCOM1__W { w: self } + } + #[doc = "Bit 3 - SERCOM2 APB Clock Enable"] + #[inline(always)] + pub fn sercom2_(&mut self) -> SERCOM2__W { + SERCOM2__W { w: self } + } + #[doc = "Bit 4 - SERCOM3 APB Clock Enable"] + #[inline(always)] + pub fn sercom3_(&mut self) -> SERCOM3__W { + SERCOM3__W { w: self } + } + #[doc = "Bit 5 - SERCOM4 APB Clock Enable"] + #[inline(always)] + pub fn sercom4_(&mut self) -> SERCOM4__W { + SERCOM4__W { w: self } + } + #[doc = "Bit 6 - SERCOM5 APB Clock Enable"] + #[inline(always)] + pub fn sercom5_(&mut self) -> SERCOM5__W { + SERCOM5__W { w: self } + } + #[doc = "Bit 9 - TCC0 APB Clock Enable"] + #[inline(always)] + pub fn tcc0_(&mut self) -> TCC0__W { + TCC0__W { w: self } + } + #[doc = "Bit 10 - TCC1 APB Clock Enable"] + #[inline(always)] + pub fn tcc1_(&mut self) -> TCC1__W { + TCC1__W { w: self } + } + #[doc = "Bit 11 - TCC2 APB Clock Enable"] + #[inline(always)] + pub fn tcc2_(&mut self) -> TCC2__W { + TCC2__W { w: self } + } + #[doc = "Bit 12 - TC0 APB Clock Enable"] + #[inline(always)] + pub fn tc0_(&mut self) -> TC0__W { + TC0__W { w: self } + } + #[doc = "Bit 13 - TC1 APB Clock Enable"] + #[inline(always)] + pub fn tc1_(&mut self) -> TC1__W { + TC1__W { w: self } + } + #[doc = "Bit 14 - TC2 APB Clock Enable"] + #[inline(always)] + pub fn tc2_(&mut self) -> TC2__W { + TC2__W { w: self } + } + #[doc = "Bit 15 - TC3 APB Clock Enable"] + #[inline(always)] + pub fn tc3_(&mut self) -> TC3__W { + TC3__W { w: self } + } + #[doc = "Bit 16 - TC4 APB Clock Enable"] + #[inline(always)] + pub fn tc4_(&mut self) -> TC4__W { + TC4__W { w: self } + } + #[doc = "Bit 17 - ADC0 APB Clock Enable"] + #[inline(always)] + pub fn adc0_(&mut self) -> ADC0__W { + ADC0__W { w: self } + } + #[doc = "Bit 18 - ADC1 APB Clock Enable"] + #[inline(always)] + pub fn adc1_(&mut self) -> ADC1__W { + ADC1__W { w: self } + } + #[doc = "Bit 19 - SDADC APB Clock Enable"] + #[inline(always)] + pub fn sdadc_(&mut self) -> SDADC__W { + SDADC__W { w: self } + } + #[doc = "Bit 20 - AC APB Clock Enable"] + #[inline(always)] + pub fn ac_(&mut self) -> AC__W { + AC__W { w: self } + } + #[doc = "Bit 21 - DAC APB Clock Enable"] + #[inline(always)] + pub fn dac_(&mut self) -> DAC__W { + DAC__W { w: self } + } + #[doc = "Bit 22 - PTC APB Clock Enable"] + #[inline(always)] + pub fn ptc_(&mut self) -> PTC__W { + PTC__W { w: self } + } + #[doc = "Bit 23 - CCL APB Clock Enable"] + #[inline(always)] + pub fn ccl_(&mut self) -> CCL__W { + CCL__W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "APBC Mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [apbcmask](index.html) module"] +pub struct APBCMASK_SPEC; +impl crate::RegisterSpec for APBCMASK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [apbcmask::R](R) reader structure"] +impl crate::Readable for APBCMASK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [apbcmask::W](W) writer structure"] +impl crate::Writable for APBCMASK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets APBCMASK to value 0"] +impl crate::Resettable for APBCMASK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/mclk/apbdmask.rs b/pac/atsamc21n/src/mclk/apbdmask.rs new file mode 100644 index 000000000000..64592ea4d041 --- /dev/null +++ b/pac/atsamc21n/src/mclk/apbdmask.rs @@ -0,0 +1,301 @@ +#[doc = "Register `APBDMASK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `APBDMASK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SERCOM6_` reader - SERCOM6 APB Clock Enable"] +pub struct SERCOM6__R(crate::FieldReader); +impl SERCOM6__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM6__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM6__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM6_` writer - SERCOM6 APB Clock Enable"] +pub struct SERCOM6__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM6__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `SERCOM7_` reader - SERCOM7 APB Clock Enable"] +pub struct SERCOM7__R(crate::FieldReader); +impl SERCOM7__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM7__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM7__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM7_` writer - SERCOM7 APB Clock Enable"] +pub struct SERCOM7__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM7__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `TC5_` reader - TC5 APB Clock Enable"] +pub struct TC5__R(crate::FieldReader); +impl TC5__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC5__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC5__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC5_` writer - TC5 APB Clock Enable"] +pub struct TC5__W<'a> { + w: &'a mut W, +} +impl<'a> TC5__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `TC6_` reader - TC6 APB Clock Enable"] +pub struct TC6__R(crate::FieldReader); +impl TC6__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC6__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC6__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC6_` writer - TC6 APB Clock Enable"] +pub struct TC6__W<'a> { + w: &'a mut W, +} +impl<'a> TC6__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `TC7_` reader - TC7 APB Clock Enable"] +pub struct TC7__R(crate::FieldReader); +impl TC7__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC7__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC7__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC7_` writer - TC7 APB Clock Enable"] +pub struct TC7__W<'a> { + w: &'a mut W, +} +impl<'a> TC7__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +impl R { + #[doc = "Bit 0 - SERCOM6 APB Clock Enable"] + #[inline(always)] + pub fn sercom6_(&self) -> SERCOM6__R { + SERCOM6__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM7 APB Clock Enable"] + #[inline(always)] + pub fn sercom7_(&self) -> SERCOM7__R { + SERCOM7__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - TC5 APB Clock Enable"] + #[inline(always)] + pub fn tc5_(&self) -> TC5__R { + TC5__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - TC6 APB Clock Enable"] + #[inline(always)] + pub fn tc6_(&self) -> TC6__R { + TC6__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - TC7 APB Clock Enable"] + #[inline(always)] + pub fn tc7_(&self) -> TC7__R { + TC7__R::new(((self.bits >> 4) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - SERCOM6 APB Clock Enable"] + #[inline(always)] + pub fn sercom6_(&mut self) -> SERCOM6__W { + SERCOM6__W { w: self } + } + #[doc = "Bit 1 - SERCOM7 APB Clock Enable"] + #[inline(always)] + pub fn sercom7_(&mut self) -> SERCOM7__W { + SERCOM7__W { w: self } + } + #[doc = "Bit 2 - TC5 APB Clock Enable"] + #[inline(always)] + pub fn tc5_(&mut self) -> TC5__W { + TC5__W { w: self } + } + #[doc = "Bit 3 - TC6 APB Clock Enable"] + #[inline(always)] + pub fn tc6_(&mut self) -> TC6__W { + TC6__W { w: self } + } + #[doc = "Bit 4 - TC7 APB Clock Enable"] + #[inline(always)] + pub fn tc7_(&mut self) -> TC7__W { + TC7__W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "APBD Mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [apbdmask](index.html) module"] +pub struct APBDMASK_SPEC; +impl crate::RegisterSpec for APBDMASK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [apbdmask::R](R) reader structure"] +impl crate::Readable for APBDMASK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [apbdmask::W](W) writer structure"] +impl crate::Writable for APBDMASK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets APBDMASK to value 0"] +impl crate::Resettable for APBDMASK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/mclk/cpudiv.rs b/pac/atsamc21n/src/mclk/cpudiv.rs new file mode 100644 index 000000000000..a21fdae21357 --- /dev/null +++ b/pac/atsamc21n/src/mclk/cpudiv.rs @@ -0,0 +1,230 @@ +#[doc = "Register `CPUDIV` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CPUDIV` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "CPU Clock Division Factor\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CPUDIV_A { + #[doc = "1: Divide by 1"] + DIV1 = 1, + #[doc = "2: Divide by 2"] + DIV2 = 2, + #[doc = "4: Divide by 4"] + DIV4 = 4, + #[doc = "8: Divide by 8"] + DIV8 = 8, + #[doc = "16: Divide by 16"] + DIV16 = 16, + #[doc = "32: Divide by 32"] + DIV32 = 32, + #[doc = "64: Divide by 64"] + DIV64 = 64, + #[doc = "128: Divide by 128"] + DIV128 = 128, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CPUDIV_A) -> Self { + variant as _ + } +} +#[doc = "Field `CPUDIV` reader - CPU Clock Division Factor"] +pub struct CPUDIV_R(crate::FieldReader); +impl CPUDIV_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CPUDIV_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 1 => Some(CPUDIV_A::DIV1), + 2 => Some(CPUDIV_A::DIV2), + 4 => Some(CPUDIV_A::DIV4), + 8 => Some(CPUDIV_A::DIV8), + 16 => Some(CPUDIV_A::DIV16), + 32 => Some(CPUDIV_A::DIV32), + 64 => Some(CPUDIV_A::DIV64), + 128 => Some(CPUDIV_A::DIV128), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == CPUDIV_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == CPUDIV_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == CPUDIV_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == CPUDIV_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == CPUDIV_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == CPUDIV_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == CPUDIV_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == CPUDIV_A::DIV128 + } +} +impl core::ops::Deref for CPUDIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPUDIV` writer - CPU Clock Division Factor"] +pub struct CPUDIV_W<'a> { + w: &'a mut W, +} +impl<'a> CPUDIV_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CPUDIV_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Divide by 1"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV1) + } + #[doc = "Divide by 2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV2) + } + #[doc = "Divide by 4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV4) + } + #[doc = "Divide by 8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV8) + } + #[doc = "Divide by 16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV16) + } + #[doc = "Divide by 32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV32) + } + #[doc = "Divide by 64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV64) + } + #[doc = "Divide by 128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV128) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - CPU Clock Division Factor"] + #[inline(always)] + pub fn cpudiv(&self) -> CPUDIV_R { + CPUDIV_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - CPU Clock Division Factor"] + #[inline(always)] + pub fn cpudiv(&mut self) -> CPUDIV_W { + CPUDIV_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CPU Clock Division\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cpudiv](index.html) module"] +pub struct CPUDIV_SPEC; +impl crate::RegisterSpec for CPUDIV_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [cpudiv::R](R) reader structure"] +impl crate::Readable for CPUDIV_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cpudiv::W](W) writer structure"] +impl crate::Writable for CPUDIV_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CPUDIV to value 0x01"] +impl crate::Resettable for CPUDIV_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pac/atsamc21n/src/mclk/intenclr.rs b/pac/atsamc21n/src/mclk/intenclr.rs new file mode 100644 index 000000000000..14feb632dbb7 --- /dev/null +++ b/pac/atsamc21n/src/mclk/intenclr.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CKRDY` reader - Clock Ready Interrupt Enable"] +pub struct CKRDY_R(crate::FieldReader); +impl CKRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CKRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CKRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CKRDY` writer - Clock Ready Interrupt Enable"] +pub struct CKRDY_W<'a> { + w: &'a mut W, +} +impl<'a> CKRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Clock Ready Interrupt Enable"] + #[inline(always)] + pub fn ckrdy(&self) -> CKRDY_R { + CKRDY_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Clock Ready Interrupt Enable"] + #[inline(always)] + pub fn ckrdy(&mut self) -> CKRDY_W { + CKRDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/mclk/intenset.rs b/pac/atsamc21n/src/mclk/intenset.rs new file mode 100644 index 000000000000..f01fcc316d93 --- /dev/null +++ b/pac/atsamc21n/src/mclk/intenset.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CKRDY` reader - Clock Ready Interrupt Enable"] +pub struct CKRDY_R(crate::FieldReader); +impl CKRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CKRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CKRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CKRDY` writer - Clock Ready Interrupt Enable"] +pub struct CKRDY_W<'a> { + w: &'a mut W, +} +impl<'a> CKRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Clock Ready Interrupt Enable"] + #[inline(always)] + pub fn ckrdy(&self) -> CKRDY_R { + CKRDY_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Clock Ready Interrupt Enable"] + #[inline(always)] + pub fn ckrdy(&mut self) -> CKRDY_W { + CKRDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/mclk/intflag.rs b/pac/atsamc21n/src/mclk/intflag.rs new file mode 100644 index 000000000000..cf421d4ac61a --- /dev/null +++ b/pac/atsamc21n/src/mclk/intflag.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CKRDY` reader - Clock Ready"] +pub struct CKRDY_R(crate::FieldReader); +impl CKRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CKRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CKRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CKRDY` writer - Clock Ready"] +pub struct CKRDY_W<'a> { + w: &'a mut W, +} +impl<'a> CKRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Clock Ready"] + #[inline(always)] + pub fn ckrdy(&self) -> CKRDY_R { + CKRDY_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Clock Ready"] + #[inline(always)] + pub fn ckrdy(&mut self) -> CKRDY_W { + CKRDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0x01"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pac/atsamc21n/src/mtb.rs b/pac/atsamc21n/src/mtb.rs new file mode 100644 index 000000000000..01be005c0fb9 --- /dev/null +++ b/pac/atsamc21n/src/mtb.rs @@ -0,0 +1,158 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - MTB Position"] + pub position: crate::Reg, + #[doc = "0x04 - MTB Master"] + pub master: crate::Reg, + #[doc = "0x08 - MTB Flow"] + pub flow: crate::Reg, + #[doc = "0x0c - MTB Base"] + pub base: crate::Reg, + _reserved4: [u8; 0x0ef0], + #[doc = "0xf00 - MTB Integration Mode Control"] + pub itctrl: crate::Reg, + _reserved5: [u8; 0x9c], + #[doc = "0xfa0 - MTB Claim Set"] + pub claimset: crate::Reg, + #[doc = "0xfa4 - MTB Claim Clear"] + pub claimclr: crate::Reg, + _reserved7: [u8; 0x08], + #[doc = "0xfb0 - MTB Lock Access"] + pub lockaccess: crate::Reg, + #[doc = "0xfb4 - MTB Lock Status"] + pub lockstatus: crate::Reg, + #[doc = "0xfb8 - MTB Authentication Status"] + pub authstatus: crate::Reg, + #[doc = "0xfbc - MTB Device Architecture"] + pub devarch: crate::Reg, + _reserved11: [u8; 0x08], + #[doc = "0xfc8 - MTB Device Configuration"] + pub devid: crate::Reg, + #[doc = "0xfcc - MTB Device Type"] + pub devtype: crate::Reg, + #[doc = "0xfd0 - Peripheral Identification 4"] + pub pid4: crate::Reg, + #[doc = "0xfd4 - Peripheral Identification 5"] + pub pid5: crate::Reg, + #[doc = "0xfd8 - Peripheral Identification 6"] + pub pid6: crate::Reg, + #[doc = "0xfdc - Peripheral Identification 7"] + pub pid7: crate::Reg, + #[doc = "0xfe0 - Peripheral Identification 0"] + pub pid0: crate::Reg, + #[doc = "0xfe4 - Peripheral Identification 1"] + pub pid1: crate::Reg, + #[doc = "0xfe8 - Peripheral Identification 2"] + pub pid2: crate::Reg, + #[doc = "0xfec - Peripheral Identification 3"] + pub pid3: crate::Reg, + #[doc = "0xff0 - Component Identification 0"] + pub cid0: crate::Reg, + #[doc = "0xff4 - Component Identification 1"] + pub cid1: crate::Reg, + #[doc = "0xff8 - Component Identification 2"] + pub cid2: crate::Reg, + #[doc = "0xffc - Component Identification 3"] + pub cid3: crate::Reg, +} +#[doc = "POSITION register accessor: an alias for `Reg`"] +pub type POSITION = crate::Reg; +#[doc = "MTB Position"] +pub mod position; +#[doc = "MASTER register accessor: an alias for `Reg`"] +pub type MASTER = crate::Reg; +#[doc = "MTB Master"] +pub mod master; +#[doc = "FLOW register accessor: an alias for `Reg`"] +pub type FLOW = crate::Reg; +#[doc = "MTB Flow"] +pub mod flow; +#[doc = "BASE register accessor: an alias for `Reg`"] +pub type BASE = crate::Reg; +#[doc = "MTB Base"] +pub mod base; +#[doc = "ITCTRL register accessor: an alias for `Reg`"] +pub type ITCTRL = crate::Reg; +#[doc = "MTB Integration Mode Control"] +pub mod itctrl; +#[doc = "CLAIMSET register accessor: an alias for `Reg`"] +pub type CLAIMSET = crate::Reg; +#[doc = "MTB Claim Set"] +pub mod claimset; +#[doc = "CLAIMCLR register accessor: an alias for `Reg`"] +pub type CLAIMCLR = crate::Reg; +#[doc = "MTB Claim Clear"] +pub mod claimclr; +#[doc = "LOCKACCESS register accessor: an alias for `Reg`"] +pub type LOCKACCESS = crate::Reg; +#[doc = "MTB Lock Access"] +pub mod lockaccess; +#[doc = "LOCKSTATUS register accessor: an alias for `Reg`"] +pub type LOCKSTATUS = crate::Reg; +#[doc = "MTB Lock Status"] +pub mod lockstatus; +#[doc = "AUTHSTATUS register accessor: an alias for `Reg`"] +pub type AUTHSTATUS = crate::Reg; +#[doc = "MTB Authentication Status"] +pub mod authstatus; +#[doc = "DEVARCH register accessor: an alias for `Reg`"] +pub type DEVARCH = crate::Reg; +#[doc = "MTB Device Architecture"] +pub mod devarch; +#[doc = "DEVID register accessor: an alias for `Reg`"] +pub type DEVID = crate::Reg; +#[doc = "MTB Device Configuration"] +pub mod devid; +#[doc = "DEVTYPE register accessor: an alias for `Reg`"] +pub type DEVTYPE = crate::Reg; +#[doc = "MTB Device Type"] +pub mod devtype; +#[doc = "PID4 register accessor: an alias for `Reg`"] +pub type PID4 = crate::Reg; +#[doc = "Peripheral Identification 4"] +pub mod pid4; +#[doc = "PID5 register accessor: an alias for `Reg`"] +pub type PID5 = crate::Reg; +#[doc = "Peripheral Identification 5"] +pub mod pid5; +#[doc = "PID6 register accessor: an alias for `Reg`"] +pub type PID6 = crate::Reg; +#[doc = "Peripheral Identification 6"] +pub mod pid6; +#[doc = "PID7 register accessor: an alias for `Reg`"] +pub type PID7 = crate::Reg; +#[doc = "Peripheral Identification 7"] +pub mod pid7; +#[doc = "PID0 register accessor: an alias for `Reg`"] +pub type PID0 = crate::Reg; +#[doc = "Peripheral Identification 0"] +pub mod pid0; +#[doc = "PID1 register accessor: an alias for `Reg`"] +pub type PID1 = crate::Reg; +#[doc = "Peripheral Identification 1"] +pub mod pid1; +#[doc = "PID2 register accessor: an alias for `Reg`"] +pub type PID2 = crate::Reg; +#[doc = "Peripheral Identification 2"] +pub mod pid2; +#[doc = "PID3 register accessor: an alias for `Reg`"] +pub type PID3 = crate::Reg; +#[doc = "Peripheral Identification 3"] +pub mod pid3; +#[doc = "CID0 register accessor: an alias for `Reg`"] +pub type CID0 = crate::Reg; +#[doc = "Component Identification 0"] +pub mod cid0; +#[doc = "CID1 register accessor: an alias for `Reg`"] +pub type CID1 = crate::Reg; +#[doc = "Component Identification 1"] +pub mod cid1; +#[doc = "CID2 register accessor: an alias for `Reg`"] +pub type CID2 = crate::Reg; +#[doc = "Component Identification 2"] +pub mod cid2; +#[doc = "CID3 register accessor: an alias for `Reg`"] +pub type CID3 = crate::Reg; +#[doc = "Component Identification 3"] +pub mod cid3; diff --git a/pac/atsamc21n/src/mtb/authstatus.rs b/pac/atsamc21n/src/mtb/authstatus.rs new file mode 100644 index 000000000000..6fe441e0554d --- /dev/null +++ b/pac/atsamc21n/src/mtb/authstatus.rs @@ -0,0 +1,31 @@ +#[doc = "Register `AUTHSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "MTB Authentication Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [authstatus](index.html) module"] +pub struct AUTHSTATUS_SPEC; +impl crate::RegisterSpec for AUTHSTATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [authstatus::R](R) reader structure"] +impl crate::Readable for AUTHSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets AUTHSTATUS to value 0"] +impl crate::Resettable for AUTHSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/mtb/base.rs b/pac/atsamc21n/src/mtb/base.rs new file mode 100644 index 000000000000..f59b5a97a398 --- /dev/null +++ b/pac/atsamc21n/src/mtb/base.rs @@ -0,0 +1,31 @@ +#[doc = "Register `BASE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "MTB Base\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [base](index.html) module"] +pub struct BASE_SPEC; +impl crate::RegisterSpec for BASE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [base::R](R) reader structure"] +impl crate::Readable for BASE_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets BASE to value 0"] +impl crate::Resettable for BASE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/mtb/cid0.rs b/pac/atsamc21n/src/mtb/cid0.rs new file mode 100644 index 000000000000..e03bd35fa470 --- /dev/null +++ b/pac/atsamc21n/src/mtb/cid0.rs @@ -0,0 +1,31 @@ +#[doc = "Register `CID0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Component Identification 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid0](index.html) module"] +pub struct CID0_SPEC; +impl crate::RegisterSpec for CID0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid0::R](R) reader structure"] +impl crate::Readable for CID0_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID0 to value 0"] +impl crate::Resettable for CID0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/mtb/cid1.rs b/pac/atsamc21n/src/mtb/cid1.rs new file mode 100644 index 000000000000..1cafc8e0fb9a --- /dev/null +++ b/pac/atsamc21n/src/mtb/cid1.rs @@ -0,0 +1,31 @@ +#[doc = "Register `CID1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Component Identification 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid1](index.html) module"] +pub struct CID1_SPEC; +impl crate::RegisterSpec for CID1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid1::R](R) reader structure"] +impl crate::Readable for CID1_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID1 to value 0"] +impl crate::Resettable for CID1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/mtb/cid2.rs b/pac/atsamc21n/src/mtb/cid2.rs new file mode 100644 index 000000000000..6a91e4e23206 --- /dev/null +++ b/pac/atsamc21n/src/mtb/cid2.rs @@ -0,0 +1,31 @@ +#[doc = "Register `CID2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Component Identification 2\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid2](index.html) module"] +pub struct CID2_SPEC; +impl crate::RegisterSpec for CID2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid2::R](R) reader structure"] +impl crate::Readable for CID2_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID2 to value 0"] +impl crate::Resettable for CID2_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/mtb/cid3.rs b/pac/atsamc21n/src/mtb/cid3.rs new file mode 100644 index 000000000000..726290f4ffed --- /dev/null +++ b/pac/atsamc21n/src/mtb/cid3.rs @@ -0,0 +1,31 @@ +#[doc = "Register `CID3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Component Identification 3\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid3](index.html) module"] +pub struct CID3_SPEC; +impl crate::RegisterSpec for CID3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid3::R](R) reader structure"] +impl crate::Readable for CID3_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID3 to value 0"] +impl crate::Resettable for CID3_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/mtb/claimclr.rs b/pac/atsamc21n/src/mtb/claimclr.rs new file mode 100644 index 000000000000..7d0fa5d487b2 --- /dev/null +++ b/pac/atsamc21n/src/mtb/claimclr.rs @@ -0,0 +1,64 @@ +#[doc = "Register `CLAIMCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CLAIMCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MTB Claim Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [claimclr](index.html) module"] +pub struct CLAIMCLR_SPEC; +impl crate::RegisterSpec for CLAIMCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [claimclr::R](R) reader structure"] +impl crate::Readable for CLAIMCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [claimclr::W](W) writer structure"] +impl crate::Writable for CLAIMCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CLAIMCLR to value 0"] +impl crate::Resettable for CLAIMCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/mtb/claimset.rs b/pac/atsamc21n/src/mtb/claimset.rs new file mode 100644 index 000000000000..d5e8ffaa4846 --- /dev/null +++ b/pac/atsamc21n/src/mtb/claimset.rs @@ -0,0 +1,64 @@ +#[doc = "Register `CLAIMSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CLAIMSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MTB Claim Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [claimset](index.html) module"] +pub struct CLAIMSET_SPEC; +impl crate::RegisterSpec for CLAIMSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [claimset::R](R) reader structure"] +impl crate::Readable for CLAIMSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [claimset::W](W) writer structure"] +impl crate::Writable for CLAIMSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CLAIMSET to value 0"] +impl crate::Resettable for CLAIMSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/mtb/devarch.rs b/pac/atsamc21n/src/mtb/devarch.rs new file mode 100644 index 000000000000..b79480753d5e --- /dev/null +++ b/pac/atsamc21n/src/mtb/devarch.rs @@ -0,0 +1,31 @@ +#[doc = "Register `DEVARCH` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "MTB Device Architecture\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [devarch](index.html) module"] +pub struct DEVARCH_SPEC; +impl crate::RegisterSpec for DEVARCH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [devarch::R](R) reader structure"] +impl crate::Readable for DEVARCH_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DEVARCH to value 0"] +impl crate::Resettable for DEVARCH_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/mtb/devid.rs b/pac/atsamc21n/src/mtb/devid.rs new file mode 100644 index 000000000000..21c15d952032 --- /dev/null +++ b/pac/atsamc21n/src/mtb/devid.rs @@ -0,0 +1,31 @@ +#[doc = "Register `DEVID` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "MTB Device Configuration\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [devid](index.html) module"] +pub struct DEVID_SPEC; +impl crate::RegisterSpec for DEVID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [devid::R](R) reader structure"] +impl crate::Readable for DEVID_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DEVID to value 0"] +impl crate::Resettable for DEVID_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/mtb/devtype.rs b/pac/atsamc21n/src/mtb/devtype.rs new file mode 100644 index 000000000000..c00d66b98a2f --- /dev/null +++ b/pac/atsamc21n/src/mtb/devtype.rs @@ -0,0 +1,31 @@ +#[doc = "Register `DEVTYPE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "MTB Device Type\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [devtype](index.html) module"] +pub struct DEVTYPE_SPEC; +impl crate::RegisterSpec for DEVTYPE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [devtype::R](R) reader structure"] +impl crate::Readable for DEVTYPE_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DEVTYPE to value 0"] +impl crate::Resettable for DEVTYPE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/mtb/flow.rs b/pac/atsamc21n/src/mtb/flow.rs new file mode 100644 index 000000000000..1b94efdb89b8 --- /dev/null +++ b/pac/atsamc21n/src/mtb/flow.rs @@ -0,0 +1,197 @@ +#[doc = "Register `FLOW` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FLOW` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `AUTOSTOP` reader - Auto Stop Tracing"] +pub struct AUTOSTOP_R(crate::FieldReader); +impl AUTOSTOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AUTOSTOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AUTOSTOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AUTOSTOP` writer - Auto Stop Tracing"] +pub struct AUTOSTOP_W<'a> { + w: &'a mut W, +} +impl<'a> AUTOSTOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `AUTOHALT` reader - Auto Halt Request"] +pub struct AUTOHALT_R(crate::FieldReader); +impl AUTOHALT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AUTOHALT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AUTOHALT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AUTOHALT` writer - Auto Halt Request"] +pub struct AUTOHALT_W<'a> { + w: &'a mut W, +} +impl<'a> AUTOHALT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WATERMARK` reader - Watermark value"] +pub struct WATERMARK_R(crate::FieldReader); +impl WATERMARK_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + WATERMARK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WATERMARK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WATERMARK` writer - Watermark value"] +pub struct WATERMARK_W<'a> { + w: &'a mut W, +} +impl<'a> WATERMARK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1fff_ffff << 3)) | ((value as u32 & 0x1fff_ffff) << 3); + self.w + } +} +impl R { + #[doc = "Bit 0 - Auto Stop Tracing"] + #[inline(always)] + pub fn autostop(&self) -> AUTOSTOP_R { + AUTOSTOP_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Auto Halt Request"] + #[inline(always)] + pub fn autohalt(&self) -> AUTOHALT_R { + AUTOHALT_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 3:31 - Watermark value"] + #[inline(always)] + pub fn watermark(&self) -> WATERMARK_R { + WATERMARK_R::new(((self.bits >> 3) & 0x1fff_ffff) as u32) + } +} +impl W { + #[doc = "Bit 0 - Auto Stop Tracing"] + #[inline(always)] + pub fn autostop(&mut self) -> AUTOSTOP_W { + AUTOSTOP_W { w: self } + } + #[doc = "Bit 1 - Auto Halt Request"] + #[inline(always)] + pub fn autohalt(&mut self) -> AUTOHALT_W { + AUTOHALT_W { w: self } + } + #[doc = "Bits 3:31 - Watermark value"] + #[inline(always)] + pub fn watermark(&mut self) -> WATERMARK_W { + WATERMARK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MTB Flow\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [flow](index.html) module"] +pub struct FLOW_SPEC; +impl crate::RegisterSpec for FLOW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [flow::R](R) reader structure"] +impl crate::Readable for FLOW_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [flow::W](W) writer structure"] +impl crate::Writable for FLOW_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets FLOW to value 0"] +impl crate::Resettable for FLOW_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/mtb/itctrl.rs b/pac/atsamc21n/src/mtb/itctrl.rs new file mode 100644 index 000000000000..a48364e0b062 --- /dev/null +++ b/pac/atsamc21n/src/mtb/itctrl.rs @@ -0,0 +1,64 @@ +#[doc = "Register `ITCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ITCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MTB Integration Mode Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [itctrl](index.html) module"] +pub struct ITCTRL_SPEC; +impl crate::RegisterSpec for ITCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [itctrl::R](R) reader structure"] +impl crate::Readable for ITCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [itctrl::W](W) writer structure"] +impl crate::Writable for ITCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ITCTRL to value 0"] +impl crate::Resettable for ITCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/mtb/lockaccess.rs b/pac/atsamc21n/src/mtb/lockaccess.rs new file mode 100644 index 000000000000..0400690beade --- /dev/null +++ b/pac/atsamc21n/src/mtb/lockaccess.rs @@ -0,0 +1,64 @@ +#[doc = "Register `LOCKACCESS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `LOCKACCESS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MTB Lock Access\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lockaccess](index.html) module"] +pub struct LOCKACCESS_SPEC; +impl crate::RegisterSpec for LOCKACCESS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [lockaccess::R](R) reader structure"] +impl crate::Readable for LOCKACCESS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [lockaccess::W](W) writer structure"] +impl crate::Writable for LOCKACCESS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets LOCKACCESS to value 0"] +impl crate::Resettable for LOCKACCESS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/mtb/lockstatus.rs b/pac/atsamc21n/src/mtb/lockstatus.rs new file mode 100644 index 000000000000..0c68410c6944 --- /dev/null +++ b/pac/atsamc21n/src/mtb/lockstatus.rs @@ -0,0 +1,31 @@ +#[doc = "Register `LOCKSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "MTB Lock Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lockstatus](index.html) module"] +pub struct LOCKSTATUS_SPEC; +impl crate::RegisterSpec for LOCKSTATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [lockstatus::R](R) reader structure"] +impl crate::Readable for LOCKSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets LOCKSTATUS to value 0"] +impl crate::Resettable for LOCKSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/mtb/master.rs b/pac/atsamc21n/src/mtb/master.rs new file mode 100644 index 000000000000..0190ca1ce909 --- /dev/null +++ b/pac/atsamc21n/src/mtb/master.rs @@ -0,0 +1,385 @@ +#[doc = "Register `MASTER` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MASTER` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MASK` reader - Maximum Value of the Trace Buffer in SRAM"] +pub struct MASK_R(crate::FieldReader); +impl MASK_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MASK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MASK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MASK` writer - Maximum Value of the Trace Buffer in SRAM"] +pub struct MASK_W<'a> { + w: &'a mut W, +} +impl<'a> MASK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f); + self.w + } +} +#[doc = "Field `TSTARTEN` reader - Trace Start Input Enable"] +pub struct TSTARTEN_R(crate::FieldReader); +impl TSTARTEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSTARTEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSTARTEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSTARTEN` writer - Trace Start Input Enable"] +pub struct TSTARTEN_W<'a> { + w: &'a mut W, +} +impl<'a> TSTARTEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `TSTOPEN` reader - Trace Stop Input Enable"] +pub struct TSTOPEN_R(crate::FieldReader); +impl TSTOPEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSTOPEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSTOPEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSTOPEN` writer - Trace Stop Input Enable"] +pub struct TSTOPEN_W<'a> { + w: &'a mut W, +} +impl<'a> TSTOPEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `SFRWPRIV` reader - Special Function Register Write Privilege"] +pub struct SFRWPRIV_R(crate::FieldReader); +impl SFRWPRIV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SFRWPRIV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SFRWPRIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SFRWPRIV` writer - Special Function Register Write Privilege"] +pub struct SFRWPRIV_W<'a> { + w: &'a mut W, +} +impl<'a> SFRWPRIV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `RAMPRIV` reader - SRAM Privilege"] +pub struct RAMPRIV_R(crate::FieldReader); +impl RAMPRIV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RAMPRIV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RAMPRIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RAMPRIV` writer - SRAM Privilege"] +pub struct RAMPRIV_W<'a> { + w: &'a mut W, +} +impl<'a> RAMPRIV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `HALTREQ` reader - Halt Request"] +pub struct HALTREQ_R(crate::FieldReader); +impl HALTREQ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HALTREQ_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HALTREQ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HALTREQ` writer - Halt Request"] +pub struct HALTREQ_W<'a> { + w: &'a mut W, +} +impl<'a> HALTREQ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `EN` reader - Main Trace Enable"] +pub struct EN_R(crate::FieldReader); +impl EN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EN` writer - Main Trace Enable"] +pub struct EN_W<'a> { + w: &'a mut W, +} +impl<'a> EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Maximum Value of the Trace Buffer in SRAM"] + #[inline(always)] + pub fn mask(&self) -> MASK_R { + MASK_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bit 5 - Trace Start Input Enable"] + #[inline(always)] + pub fn tstarten(&self) -> TSTARTEN_R { + TSTARTEN_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Trace Stop Input Enable"] + #[inline(always)] + pub fn tstopen(&self) -> TSTOPEN_R { + TSTOPEN_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Special Function Register Write Privilege"] + #[inline(always)] + pub fn sfrwpriv(&self) -> SFRWPRIV_R { + SFRWPRIV_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - SRAM Privilege"] + #[inline(always)] + pub fn rampriv(&self) -> RAMPRIV_R { + RAMPRIV_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Halt Request"] + #[inline(always)] + pub fn haltreq(&self) -> HALTREQ_R { + HALTREQ_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 31 - Main Trace Enable"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Maximum Value of the Trace Buffer in SRAM"] + #[inline(always)] + pub fn mask(&mut self) -> MASK_W { + MASK_W { w: self } + } + #[doc = "Bit 5 - Trace Start Input Enable"] + #[inline(always)] + pub fn tstarten(&mut self) -> TSTARTEN_W { + TSTARTEN_W { w: self } + } + #[doc = "Bit 6 - Trace Stop Input Enable"] + #[inline(always)] + pub fn tstopen(&mut self) -> TSTOPEN_W { + TSTOPEN_W { w: self } + } + #[doc = "Bit 7 - Special Function Register Write Privilege"] + #[inline(always)] + pub fn sfrwpriv(&mut self) -> SFRWPRIV_W { + SFRWPRIV_W { w: self } + } + #[doc = "Bit 8 - SRAM Privilege"] + #[inline(always)] + pub fn rampriv(&mut self) -> RAMPRIV_W { + RAMPRIV_W { w: self } + } + #[doc = "Bit 9 - Halt Request"] + #[inline(always)] + pub fn haltreq(&mut self) -> HALTREQ_W { + HALTREQ_W { w: self } + } + #[doc = "Bit 31 - Main Trace Enable"] + #[inline(always)] + pub fn en(&mut self) -> EN_W { + EN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MTB Master\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [master](index.html) module"] +pub struct MASTER_SPEC; +impl crate::RegisterSpec for MASTER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [master::R](R) reader structure"] +impl crate::Readable for MASTER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [master::W](W) writer structure"] +impl crate::Writable for MASTER_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets MASTER to value 0"] +impl crate::Resettable for MASTER_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/mtb/pid0.rs b/pac/atsamc21n/src/mtb/pid0.rs new file mode 100644 index 000000000000..0a7183189fe5 --- /dev/null +++ b/pac/atsamc21n/src/mtb/pid0.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid0](index.html) module"] +pub struct PID0_SPEC; +impl crate::RegisterSpec for PID0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid0::R](R) reader structure"] +impl crate::Readable for PID0_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID0 to value 0"] +impl crate::Resettable for PID0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/mtb/pid1.rs b/pac/atsamc21n/src/mtb/pid1.rs new file mode 100644 index 000000000000..7d6381917f5d --- /dev/null +++ b/pac/atsamc21n/src/mtb/pid1.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid1](index.html) module"] +pub struct PID1_SPEC; +impl crate::RegisterSpec for PID1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid1::R](R) reader structure"] +impl crate::Readable for PID1_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID1 to value 0"] +impl crate::Resettable for PID1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/mtb/pid2.rs b/pac/atsamc21n/src/mtb/pid2.rs new file mode 100644 index 000000000000..74c230346b4c --- /dev/null +++ b/pac/atsamc21n/src/mtb/pid2.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 2\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid2](index.html) module"] +pub struct PID2_SPEC; +impl crate::RegisterSpec for PID2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid2::R](R) reader structure"] +impl crate::Readable for PID2_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID2 to value 0"] +impl crate::Resettable for PID2_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/mtb/pid3.rs b/pac/atsamc21n/src/mtb/pid3.rs new file mode 100644 index 000000000000..e9e922aa2f21 --- /dev/null +++ b/pac/atsamc21n/src/mtb/pid3.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 3\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid3](index.html) module"] +pub struct PID3_SPEC; +impl crate::RegisterSpec for PID3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid3::R](R) reader structure"] +impl crate::Readable for PID3_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID3 to value 0"] +impl crate::Resettable for PID3_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/mtb/pid4.rs b/pac/atsamc21n/src/mtb/pid4.rs new file mode 100644 index 000000000000..89074d3c2692 --- /dev/null +++ b/pac/atsamc21n/src/mtb/pid4.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID4` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 4\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid4](index.html) module"] +pub struct PID4_SPEC; +impl crate::RegisterSpec for PID4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid4::R](R) reader structure"] +impl crate::Readable for PID4_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID4 to value 0"] +impl crate::Resettable for PID4_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/mtb/pid5.rs b/pac/atsamc21n/src/mtb/pid5.rs new file mode 100644 index 000000000000..d343d4800b95 --- /dev/null +++ b/pac/atsamc21n/src/mtb/pid5.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID5` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 5\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid5](index.html) module"] +pub struct PID5_SPEC; +impl crate::RegisterSpec for PID5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid5::R](R) reader structure"] +impl crate::Readable for PID5_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID5 to value 0"] +impl crate::Resettable for PID5_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/mtb/pid6.rs b/pac/atsamc21n/src/mtb/pid6.rs new file mode 100644 index 000000000000..55cc2b8b5861 --- /dev/null +++ b/pac/atsamc21n/src/mtb/pid6.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID6` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 6\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid6](index.html) module"] +pub struct PID6_SPEC; +impl crate::RegisterSpec for PID6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid6::R](R) reader structure"] +impl crate::Readable for PID6_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID6 to value 0"] +impl crate::Resettable for PID6_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/mtb/pid7.rs b/pac/atsamc21n/src/mtb/pid7.rs new file mode 100644 index 000000000000..77664d4f2f95 --- /dev/null +++ b/pac/atsamc21n/src/mtb/pid7.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PID7` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 7\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid7](index.html) module"] +pub struct PID7_SPEC; +impl crate::RegisterSpec for PID7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid7::R](R) reader structure"] +impl crate::Readable for PID7_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID7 to value 0"] +impl crate::Resettable for PID7_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/mtb/position.rs b/pac/atsamc21n/src/mtb/position.rs new file mode 100644 index 000000000000..4bab0425b142 --- /dev/null +++ b/pac/atsamc21n/src/mtb/position.rs @@ -0,0 +1,150 @@ +#[doc = "Register `POSITION` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `POSITION` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WRAP` reader - Pointer Value Wraps"] +pub struct WRAP_R(crate::FieldReader); +impl WRAP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WRAP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WRAP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WRAP` writer - Pointer Value Wraps"] +pub struct WRAP_W<'a> { + w: &'a mut W, +} +impl<'a> WRAP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `POINTER` reader - Trace Packet Location Pointer"] +pub struct POINTER_R(crate::FieldReader); +impl POINTER_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + POINTER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for POINTER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `POINTER` writer - Trace Packet Location Pointer"] +pub struct POINTER_W<'a> { + w: &'a mut W, +} +impl<'a> POINTER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1fff_ffff << 3)) | ((value as u32 & 0x1fff_ffff) << 3); + self.w + } +} +impl R { + #[doc = "Bit 2 - Pointer Value Wraps"] + #[inline(always)] + pub fn wrap(&self) -> WRAP_R { + WRAP_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 3:31 - Trace Packet Location Pointer"] + #[inline(always)] + pub fn pointer(&self) -> POINTER_R { + POINTER_R::new(((self.bits >> 3) & 0x1fff_ffff) as u32) + } +} +impl W { + #[doc = "Bit 2 - Pointer Value Wraps"] + #[inline(always)] + pub fn wrap(&mut self) -> WRAP_W { + WRAP_W { w: self } + } + #[doc = "Bits 3:31 - Trace Packet Location Pointer"] + #[inline(always)] + pub fn pointer(&mut self) -> POINTER_W { + POINTER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MTB Position\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [position](index.html) module"] +pub struct POSITION_SPEC; +impl crate::RegisterSpec for POSITION_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [position::R](R) reader structure"] +impl crate::Readable for POSITION_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [position::W](W) writer structure"] +impl crate::Writable for POSITION_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets POSITION to value 0"] +impl crate::Resettable for POSITION_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/nvmctrl.rs b/pac/atsamc21n/src/nvmctrl.rs new file mode 100644 index 000000000000..2c017caaef9c --- /dev/null +++ b/pac/atsamc21n/src/nvmctrl.rs @@ -0,0 +1,76 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + _reserved1: [u8; 0x02], + #[doc = "0x04 - Control B"] + pub ctrlb: crate::Reg, + #[doc = "0x08 - NVM Parameter"] + pub param: crate::Reg, + #[doc = "0x0c - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + _reserved4: [u8; 0x03], + #[doc = "0x10 - Interrupt Enable Set"] + pub intenset: crate::Reg, + _reserved5: [u8; 0x03], + #[doc = "0x14 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved6: [u8; 0x03], + #[doc = "0x18 - Status"] + pub status: crate::Reg, + _reserved7: [u8; 0x02], + #[doc = "0x1c - Address"] + pub addr: crate::Reg, + #[doc = "0x20 - Lock Section"] + pub lock: crate::Reg, + _reserved9: [u8; 0x06], + #[doc = "0x28 - Page Buffer Load Data 0"] + pub pbldata0: crate::Reg, + #[doc = "0x2c - Page Buffer Load Data 1"] + pub pbldata1: crate::Reg, +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "Control B"] +pub mod ctrlb; +#[doc = "PARAM register accessor: an alias for `Reg`"] +pub type PARAM = crate::Reg; +#[doc = "NVM Parameter"] +pub mod param; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "ADDR register accessor: an alias for `Reg`"] +pub type ADDR = crate::Reg; +#[doc = "Address"] +pub mod addr; +#[doc = "LOCK register accessor: an alias for `Reg`"] +pub type LOCK = crate::Reg; +#[doc = "Lock Section"] +pub mod lock; +#[doc = "PBLDATA0 register accessor: an alias for `Reg`"] +pub type PBLDATA0 = crate::Reg; +#[doc = "Page Buffer Load Data 0"] +pub mod pbldata0; +#[doc = "PBLDATA1 register accessor: an alias for `Reg`"] +pub type PBLDATA1 = crate::Reg; +#[doc = "Page Buffer Load Data 1"] +pub mod pbldata1; diff --git a/pac/atsamc21n/src/nvmctrl/addr.rs b/pac/atsamc21n/src/nvmctrl/addr.rs new file mode 100644 index 000000000000..74ed27736dac --- /dev/null +++ b/pac/atsamc21n/src/nvmctrl/addr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `ADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ADDR` reader - NVM Address"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - NVM Address"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x003f_ffff) | (value as u32 & 0x003f_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:21 - NVM Address"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new((self.bits & 0x003f_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:21 - NVM Address"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [addr](index.html) module"] +pub struct ADDR_SPEC; +impl crate::RegisterSpec for ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [addr::R](R) reader structure"] +impl crate::Readable for ADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [addr::W](W) writer structure"] +impl crate::Writable for ADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ADDR to value 0"] +impl crate::Resettable for ADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/nvmctrl/ctrla.rs b/pac/atsamc21n/src/nvmctrl/ctrla.rs new file mode 100644 index 000000000000..89f175771e4d --- /dev/null +++ b/pac/atsamc21n/src/nvmctrl/ctrla.rs @@ -0,0 +1,394 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "2: Erase Row - Erases the row addressed by the ADDR register."] + ER = 2, + #[doc = "4: Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register."] + WP = 4, + #[doc = "5: Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row."] + EAR = 5, + #[doc = "6: Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row."] + WAP = 6, + #[doc = "10: Security Flow Command"] + SF = 10, + #[doc = "15: Write lockbits"] + WL = 15, + #[doc = "26: RWW EEPROM area Erase Row - Erases the row addressed by the ADDR register."] + RWWEEER = 26, + #[doc = "28: RWW EEPROM Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register."] + RWWEEWP = 28, + #[doc = "64: Lock Region - Locks the region containing the address location in the ADDR register."] + LR = 64, + #[doc = "65: Unlock Region - Unlocks the region containing the address location in the ADDR register."] + UR = 65, + #[doc = "66: Sets the power reduction mode."] + SPRM = 66, + #[doc = "67: Clears the power reduction mode."] + CPRM = 67, + #[doc = "68: Page Buffer Clear - Clears the page buffer."] + PBC = 68, + #[doc = "69: Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row."] + SSB = 69, + #[doc = "70: Invalidate all cache lines."] + INVALL = 70, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 2 => Some(CMD_A::ER), + 4 => Some(CMD_A::WP), + 5 => Some(CMD_A::EAR), + 6 => Some(CMD_A::WAP), + 10 => Some(CMD_A::SF), + 15 => Some(CMD_A::WL), + 26 => Some(CMD_A::RWWEEER), + 28 => Some(CMD_A::RWWEEWP), + 64 => Some(CMD_A::LR), + 65 => Some(CMD_A::UR), + 66 => Some(CMD_A::SPRM), + 67 => Some(CMD_A::CPRM), + 68 => Some(CMD_A::PBC), + 69 => Some(CMD_A::SSB), + 70 => Some(CMD_A::INVALL), + _ => None, + } + } + #[doc = "Checks if the value of the field is `ER`"] + #[inline(always)] + pub fn is_er(&self) -> bool { + **self == CMD_A::ER + } + #[doc = "Checks if the value of the field is `WP`"] + #[inline(always)] + pub fn is_wp(&self) -> bool { + **self == CMD_A::WP + } + #[doc = "Checks if the value of the field is `EAR`"] + #[inline(always)] + pub fn is_ear(&self) -> bool { + **self == CMD_A::EAR + } + #[doc = "Checks if the value of the field is `WAP`"] + #[inline(always)] + pub fn is_wap(&self) -> bool { + **self == CMD_A::WAP + } + #[doc = "Checks if the value of the field is `SF`"] + #[inline(always)] + pub fn is_sf(&self) -> bool { + **self == CMD_A::SF + } + #[doc = "Checks if the value of the field is `WL`"] + #[inline(always)] + pub fn is_wl(&self) -> bool { + **self == CMD_A::WL + } + #[doc = "Checks if the value of the field is `RWWEEER`"] + #[inline(always)] + pub fn is_rwweeer(&self) -> bool { + **self == CMD_A::RWWEEER + } + #[doc = "Checks if the value of the field is `RWWEEWP`"] + #[inline(always)] + pub fn is_rwweewp(&self) -> bool { + **self == CMD_A::RWWEEWP + } + #[doc = "Checks if the value of the field is `LR`"] + #[inline(always)] + pub fn is_lr(&self) -> bool { + **self == CMD_A::LR + } + #[doc = "Checks if the value of the field is `UR`"] + #[inline(always)] + pub fn is_ur(&self) -> bool { + **self == CMD_A::UR + } + #[doc = "Checks if the value of the field is `SPRM`"] + #[inline(always)] + pub fn is_sprm(&self) -> bool { + **self == CMD_A::SPRM + } + #[doc = "Checks if the value of the field is `CPRM`"] + #[inline(always)] + pub fn is_cprm(&self) -> bool { + **self == CMD_A::CPRM + } + #[doc = "Checks if the value of the field is `PBC`"] + #[inline(always)] + pub fn is_pbc(&self) -> bool { + **self == CMD_A::PBC + } + #[doc = "Checks if the value of the field is `SSB`"] + #[inline(always)] + pub fn is_ssb(&self) -> bool { + **self == CMD_A::SSB + } + #[doc = "Checks if the value of the field is `INVALL`"] + #[inline(always)] + pub fn is_invall(&self) -> bool { + **self == CMD_A::INVALL + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Erase Row - Erases the row addressed by the ADDR register."] + #[inline(always)] + pub fn er(self) -> &'a mut W { + self.variant(CMD_A::ER) + } + #[doc = "Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register."] + #[inline(always)] + pub fn wp(self) -> &'a mut W { + self.variant(CMD_A::WP) + } + #[doc = "Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row."] + #[inline(always)] + pub fn ear(self) -> &'a mut W { + self.variant(CMD_A::EAR) + } + #[doc = "Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row."] + #[inline(always)] + pub fn wap(self) -> &'a mut W { + self.variant(CMD_A::WAP) + } + #[doc = "Security Flow Command"] + #[inline(always)] + pub fn sf(self) -> &'a mut W { + self.variant(CMD_A::SF) + } + #[doc = "Write lockbits"] + #[inline(always)] + pub fn wl(self) -> &'a mut W { + self.variant(CMD_A::WL) + } + #[doc = "RWW EEPROM area Erase Row - Erases the row addressed by the ADDR register."] + #[inline(always)] + pub fn rwweeer(self) -> &'a mut W { + self.variant(CMD_A::RWWEEER) + } + #[doc = "RWW EEPROM Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register."] + #[inline(always)] + pub fn rwweewp(self) -> &'a mut W { + self.variant(CMD_A::RWWEEWP) + } + #[doc = "Lock Region - Locks the region containing the address location in the ADDR register."] + #[inline(always)] + pub fn lr(self) -> &'a mut W { + self.variant(CMD_A::LR) + } + #[doc = "Unlock Region - Unlocks the region containing the address location in the ADDR register."] + #[inline(always)] + pub fn ur(self) -> &'a mut W { + self.variant(CMD_A::UR) + } + #[doc = "Sets the power reduction mode."] + #[inline(always)] + pub fn sprm(self) -> &'a mut W { + self.variant(CMD_A::SPRM) + } + #[doc = "Clears the power reduction mode."] + #[inline(always)] + pub fn cprm(self) -> &'a mut W { + self.variant(CMD_A::CPRM) + } + #[doc = "Page Buffer Clear - Clears the page buffer."] + #[inline(always)] + pub fn pbc(self) -> &'a mut W { + self.variant(CMD_A::PBC) + } + #[doc = "Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row."] + #[inline(always)] + pub fn ssb(self) -> &'a mut W { + self.variant(CMD_A::SSB) + } + #[doc = "Invalidate all cache lines."] + #[inline(always)] + pub fn invall(self) -> &'a mut W { + self.variant(CMD_A::INVALL) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x7f) | (value as u16 & 0x7f); + self.w + } +} +#[doc = "Command Execution\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMDEX_A { + #[doc = "165: Execution Key"] + KEY = 165, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMDEX_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMDEX` reader - Command Execution"] +pub struct CMDEX_R(crate::FieldReader); +impl CMDEX_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMDEX_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 165 => Some(CMDEX_A::KEY), + _ => None, + } + } + #[doc = "Checks if the value of the field is `KEY`"] + #[inline(always)] + pub fn is_key(&self) -> bool { + **self == CMDEX_A::KEY + } +} +impl core::ops::Deref for CMDEX_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMDEX` writer - Command Execution"] +pub struct CMDEX_W<'a> { + w: &'a mut W, +} +impl<'a> CMDEX_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMDEX_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Execution Key"] + #[inline(always)] + pub fn key(self) -> &'a mut W { + self.variant(CMDEX_A::KEY) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u16 & 0xff) << 8); + self.w + } +} +impl R { + #[doc = "Bits 0:6 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bits 8:15 - Command Execution"] + #[inline(always)] + pub fn cmdex(&self) -> CMDEX_R { + CMDEX_R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:6 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Bits 8:15 - Command Execution"] + #[inline(always)] + pub fn cmdex(&mut self) -> CMDEX_W { + CMDEX_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/nvmctrl/ctrlb.rs b/pac/atsamc21n/src/nvmctrl/ctrlb.rs new file mode 100644 index 000000000000..6162d0d4ade0 --- /dev/null +++ b/pac/atsamc21n/src/nvmctrl/ctrlb.rs @@ -0,0 +1,447 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "NVM Read Wait States\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum RWS_A { + #[doc = "0: Single Auto Wait State"] + SINGLE = 0, + #[doc = "1: Half Auto Wait State"] + HALF = 1, + #[doc = "2: Dual Auto Wait State"] + DUAL = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RWS_A) -> Self { + variant as _ + } +} +#[doc = "Field `RWS` reader - NVM Read Wait States"] +pub struct RWS_R(crate::FieldReader); +impl RWS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RWS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(RWS_A::SINGLE), + 1 => Some(RWS_A::HALF), + 2 => Some(RWS_A::DUAL), + _ => None, + } + } + #[doc = "Checks if the value of the field is `SINGLE`"] + #[inline(always)] + pub fn is_single(&self) -> bool { + **self == RWS_A::SINGLE + } + #[doc = "Checks if the value of the field is `HALF`"] + #[inline(always)] + pub fn is_half(&self) -> bool { + **self == RWS_A::HALF + } + #[doc = "Checks if the value of the field is `DUAL`"] + #[inline(always)] + pub fn is_dual(&self) -> bool { + **self == RWS_A::DUAL + } +} +impl core::ops::Deref for RWS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RWS` writer - NVM Read Wait States"] +pub struct RWS_W<'a> { + w: &'a mut W, +} +impl<'a> RWS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RWS_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Single Auto Wait State"] + #[inline(always)] + pub fn single(self) -> &'a mut W { + self.variant(RWS_A::SINGLE) + } + #[doc = "Half Auto Wait State"] + #[inline(always)] + pub fn half(self) -> &'a mut W { + self.variant(RWS_A::HALF) + } + #[doc = "Dual Auto Wait State"] + #[inline(always)] + pub fn dual(self) -> &'a mut W { + self.variant(RWS_A::DUAL) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 1)) | ((value as u32 & 0x0f) << 1); + self.w + } +} +#[doc = "Field `MANW` reader - Manual Write"] +pub struct MANW_R(crate::FieldReader); +impl MANW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MANW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MANW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MANW` writer - Manual Write"] +pub struct MANW_W<'a> { + w: &'a mut W, +} +impl<'a> MANW_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Power Reduction Mode during Sleep\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SLEEPPRM_A { + #[doc = "0: NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access."] + WAKEONACCESS = 0, + #[doc = "1: NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep."] + WAKEUPINSTANT = 1, + #[doc = "3: Auto power reduction disabled."] + DISABLED = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SLEEPPRM_A) -> Self { + variant as _ + } +} +#[doc = "Field `SLEEPPRM` reader - Power Reduction Mode during Sleep"] +pub struct SLEEPPRM_R(crate::FieldReader); +impl SLEEPPRM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SLEEPPRM_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SLEEPPRM_A::WAKEONACCESS), + 1 => Some(SLEEPPRM_A::WAKEUPINSTANT), + 3 => Some(SLEEPPRM_A::DISABLED), + _ => None, + } + } + #[doc = "Checks if the value of the field is `WAKEONACCESS`"] + #[inline(always)] + pub fn is_wakeonaccess(&self) -> bool { + **self == SLEEPPRM_A::WAKEONACCESS + } + #[doc = "Checks if the value of the field is `WAKEUPINSTANT`"] + #[inline(always)] + pub fn is_wakeupinstant(&self) -> bool { + **self == SLEEPPRM_A::WAKEUPINSTANT + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + **self == SLEEPPRM_A::DISABLED + } +} +impl core::ops::Deref for SLEEPPRM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLEEPPRM` writer - Power Reduction Mode during Sleep"] +pub struct SLEEPPRM_W<'a> { + w: &'a mut W, +} +impl<'a> SLEEPPRM_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SLEEPPRM_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access."] + #[inline(always)] + pub fn wakeonaccess(self) -> &'a mut W { + self.variant(SLEEPPRM_A::WAKEONACCESS) + } + #[doc = "NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep."] + #[inline(always)] + pub fn wakeupinstant(self) -> &'a mut W { + self.variant(SLEEPPRM_A::WAKEUPINSTANT) + } + #[doc = "Auto power reduction disabled."] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(SLEEPPRM_A::DISABLED) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 8)) | ((value as u32 & 0x03) << 8); + self.w + } +} +#[doc = "NVMCTRL Read Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum READMODE_A { + #[doc = "0: The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance."] + NO_MISS_PENALTY = 0, + #[doc = "1: Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time."] + LOW_POWER = 1, + #[doc = "2: The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings."] + DETERMINISTIC = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: READMODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `READMODE` reader - NVMCTRL Read Mode"] +pub struct READMODE_R(crate::FieldReader); +impl READMODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + READMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(READMODE_A::NO_MISS_PENALTY), + 1 => Some(READMODE_A::LOW_POWER), + 2 => Some(READMODE_A::DETERMINISTIC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NO_MISS_PENALTY`"] + #[inline(always)] + pub fn is_no_miss_penalty(&self) -> bool { + **self == READMODE_A::NO_MISS_PENALTY + } + #[doc = "Checks if the value of the field is `LOW_POWER`"] + #[inline(always)] + pub fn is_low_power(&self) -> bool { + **self == READMODE_A::LOW_POWER + } + #[doc = "Checks if the value of the field is `DETERMINISTIC`"] + #[inline(always)] + pub fn is_deterministic(&self) -> bool { + **self == READMODE_A::DETERMINISTIC + } +} +impl core::ops::Deref for READMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `READMODE` writer - NVMCTRL Read Mode"] +pub struct READMODE_W<'a> { + w: &'a mut W, +} +impl<'a> READMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: READMODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance."] + #[inline(always)] + pub fn no_miss_penalty(self) -> &'a mut W { + self.variant(READMODE_A::NO_MISS_PENALTY) + } + #[doc = "Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time."] + #[inline(always)] + pub fn low_power(self) -> &'a mut W { + self.variant(READMODE_A::LOW_POWER) + } + #[doc = "The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings."] + #[inline(always)] + pub fn deterministic(self) -> &'a mut W { + self.variant(READMODE_A::DETERMINISTIC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Field `CACHEDIS` reader - Cache Disable"] +pub struct CACHEDIS_R(crate::FieldReader); +impl CACHEDIS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CACHEDIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CACHEDIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CACHEDIS` writer - Cache Disable"] +pub struct CACHEDIS_W<'a> { + w: &'a mut W, +} +impl<'a> CACHEDIS_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 18)) | ((value as u32 & 0x03) << 18); + self.w + } +} +impl R { + #[doc = "Bits 1:4 - NVM Read Wait States"] + #[inline(always)] + pub fn rws(&self) -> RWS_R { + RWS_R::new(((self.bits >> 1) & 0x0f) as u8) + } + #[doc = "Bit 7 - Manual Write"] + #[inline(always)] + pub fn manw(&self) -> MANW_R { + MANW_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:9 - Power Reduction Mode during Sleep"] + #[inline(always)] + pub fn sleepprm(&self) -> SLEEPPRM_R { + SLEEPPRM_R::new(((self.bits >> 8) & 0x03) as u8) + } + #[doc = "Bits 16:17 - NVMCTRL Read Mode"] + #[inline(always)] + pub fn readmode(&self) -> READMODE_R { + READMODE_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bits 18:19 - Cache Disable"] + #[inline(always)] + pub fn cachedis(&self) -> CACHEDIS_R { + CACHEDIS_R::new(((self.bits >> 18) & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 1:4 - NVM Read Wait States"] + #[inline(always)] + pub fn rws(&mut self) -> RWS_W { + RWS_W { w: self } + } + #[doc = "Bit 7 - Manual Write"] + #[inline(always)] + pub fn manw(&mut self) -> MANW_W { + MANW_W { w: self } + } + #[doc = "Bits 8:9 - Power Reduction Mode during Sleep"] + #[inline(always)] + pub fn sleepprm(&mut self) -> SLEEPPRM_W { + SLEEPPRM_W { w: self } + } + #[doc = "Bits 16:17 - NVMCTRL Read Mode"] + #[inline(always)] + pub fn readmode(&mut self) -> READMODE_W { + READMODE_W { w: self } + } + #[doc = "Bits 18:19 - Cache Disable"] + #[inline(always)] + pub fn cachedis(&mut self) -> CACHEDIS_W { + CACHEDIS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0x80"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x80 + } +} diff --git a/pac/atsamc21n/src/nvmctrl/intenclr.rs b/pac/atsamc21n/src/nvmctrl/intenclr.rs new file mode 100644 index 000000000000..6e7db4b52c9d --- /dev/null +++ b/pac/atsamc21n/src/nvmctrl/intenclr.rs @@ -0,0 +1,160 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `READY` reader - NVM Ready Interrupt Enable"] +pub struct READY_R(crate::FieldReader); +impl READY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + READY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for READY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `READY` writer - NVM Ready Interrupt Enable"] +pub struct READY_W<'a> { + w: &'a mut W, +} +impl<'a> READY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERROR` reader - Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - NVM Ready Interrupt Enable"] + #[inline(always)] + pub fn ready(&self) -> READY_R { + READY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - NVM Ready Interrupt Enable"] + #[inline(always)] + pub fn ready(&mut self) -> READY_W { + READY_W { w: self } + } + #[doc = "Bit 1 - Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/nvmctrl/intenset.rs b/pac/atsamc21n/src/nvmctrl/intenset.rs new file mode 100644 index 000000000000..ba8698e86c3e --- /dev/null +++ b/pac/atsamc21n/src/nvmctrl/intenset.rs @@ -0,0 +1,160 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `READY` reader - NVM Ready Interrupt Enable"] +pub struct READY_R(crate::FieldReader); +impl READY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + READY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for READY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `READY` writer - NVM Ready Interrupt Enable"] +pub struct READY_W<'a> { + w: &'a mut W, +} +impl<'a> READY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERROR` reader - Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - NVM Ready Interrupt Enable"] + #[inline(always)] + pub fn ready(&self) -> READY_R { + READY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - NVM Ready Interrupt Enable"] + #[inline(always)] + pub fn ready(&mut self) -> READY_W { + READY_W { w: self } + } + #[doc = "Bit 1 - Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/nvmctrl/intflag.rs b/pac/atsamc21n/src/nvmctrl/intflag.rs new file mode 100644 index 000000000000..1b30cdddf25d --- /dev/null +++ b/pac/atsamc21n/src/nvmctrl/intflag.rs @@ -0,0 +1,160 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `READY` reader - NVM Ready"] +pub struct READY_R(crate::FieldReader); +impl READY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + READY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for READY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `READY` writer - NVM Ready"] +pub struct READY_W<'a> { + w: &'a mut W, +} +impl<'a> READY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERROR` reader - Error"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Error"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - NVM Ready"] + #[inline(always)] + pub fn ready(&self) -> READY_R { + READY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Error"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - NVM Ready"] + #[inline(always)] + pub fn ready(&mut self) -> READY_W { + READY_W { w: self } + } + #[doc = "Bit 1 - Error"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/nvmctrl/lock.rs b/pac/atsamc21n/src/nvmctrl/lock.rs new file mode 100644 index 000000000000..dbcf37a8107f --- /dev/null +++ b/pac/atsamc21n/src/nvmctrl/lock.rs @@ -0,0 +1,103 @@ +#[doc = "Register `LOCK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `LOCK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `LOCK` reader - Region Lock Bits"] +pub struct LOCK_R(crate::FieldReader); +impl LOCK_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + LOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LOCK` writer - Region Lock Bits"] +pub struct LOCK_W<'a> { + w: &'a mut W, +} +impl<'a> LOCK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Region Lock Bits"] + #[inline(always)] + pub fn lock(&self) -> LOCK_R { + LOCK_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Region Lock Bits"] + #[inline(always)] + pub fn lock(&mut self) -> LOCK_W { + LOCK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Lock Section\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lock](index.html) module"] +pub struct LOCK_SPEC; +impl crate::RegisterSpec for LOCK_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [lock::R](R) reader structure"] +impl crate::Readable for LOCK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [lock::W](W) writer structure"] +impl crate::Writable for LOCK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets LOCK to value 0"] +impl crate::Resettable for LOCK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/nvmctrl/param.rs b/pac/atsamc21n/src/nvmctrl/param.rs new file mode 100644 index 000000000000..d9197cf16de4 --- /dev/null +++ b/pac/atsamc21n/src/nvmctrl/param.rs @@ -0,0 +1,304 @@ +#[doc = "Register `PARAM` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PARAM` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `NVMP` reader - NVM Pages"] +pub struct NVMP_R(crate::FieldReader); +impl NVMP_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + NVMP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NVMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NVMP` writer - NVM Pages"] +pub struct NVMP_W<'a> { + w: &'a mut W, +} +impl<'a> NVMP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +#[doc = "Page Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PSZ_A { + #[doc = "0: 8 bytes"] + _8 = 0, + #[doc = "1: 16 bytes"] + _16 = 1, + #[doc = "2: 32 bytes"] + _32 = 2, + #[doc = "3: 64 bytes"] + _64 = 3, + #[doc = "4: 128 bytes"] + _128 = 4, + #[doc = "5: 256 bytes"] + _256 = 5, + #[doc = "6: 512 bytes"] + _512 = 6, + #[doc = "7: 1024 bytes"] + _1024 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PSZ_A) -> Self { + variant as _ + } +} +#[doc = "Field `PSZ` reader - Page Size"] +pub struct PSZ_R(crate::FieldReader); +impl PSZ_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PSZ_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PSZ_A { + match self.bits { + 0 => PSZ_A::_8, + 1 => PSZ_A::_16, + 2 => PSZ_A::_32, + 3 => PSZ_A::_64, + 4 => PSZ_A::_128, + 5 => PSZ_A::_256, + 6 => PSZ_A::_512, + 7 => PSZ_A::_1024, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `_8`"] + #[inline(always)] + pub fn is_8(&self) -> bool { + **self == PSZ_A::_8 + } + #[doc = "Checks if the value of the field is `_16`"] + #[inline(always)] + pub fn is_16(&self) -> bool { + **self == PSZ_A::_16 + } + #[doc = "Checks if the value of the field is `_32`"] + #[inline(always)] + pub fn is_32(&self) -> bool { + **self == PSZ_A::_32 + } + #[doc = "Checks if the value of the field is `_64`"] + #[inline(always)] + pub fn is_64(&self) -> bool { + **self == PSZ_A::_64 + } + #[doc = "Checks if the value of the field is `_128`"] + #[inline(always)] + pub fn is_128(&self) -> bool { + **self == PSZ_A::_128 + } + #[doc = "Checks if the value of the field is `_256`"] + #[inline(always)] + pub fn is_256(&self) -> bool { + **self == PSZ_A::_256 + } + #[doc = "Checks if the value of the field is `_512`"] + #[inline(always)] + pub fn is_512(&self) -> bool { + **self == PSZ_A::_512 + } + #[doc = "Checks if the value of the field is `_1024`"] + #[inline(always)] + pub fn is_1024(&self) -> bool { + **self == PSZ_A::_1024 + } +} +impl core::ops::Deref for PSZ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PSZ` writer - Page Size"] +pub struct PSZ_W<'a> { + w: &'a mut W, +} +impl<'a> PSZ_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PSZ_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "8 bytes"] + #[inline(always)] + pub fn _8(self) -> &'a mut W { + self.variant(PSZ_A::_8) + } + #[doc = "16 bytes"] + #[inline(always)] + pub fn _16(self) -> &'a mut W { + self.variant(PSZ_A::_16) + } + #[doc = "32 bytes"] + #[inline(always)] + pub fn _32(self) -> &'a mut W { + self.variant(PSZ_A::_32) + } + #[doc = "64 bytes"] + #[inline(always)] + pub fn _64(self) -> &'a mut W { + self.variant(PSZ_A::_64) + } + #[doc = "128 bytes"] + #[inline(always)] + pub fn _128(self) -> &'a mut W { + self.variant(PSZ_A::_128) + } + #[doc = "256 bytes"] + #[inline(always)] + pub fn _256(self) -> &'a mut W { + self.variant(PSZ_A::_256) + } + #[doc = "512 bytes"] + #[inline(always)] + pub fn _512(self) -> &'a mut W { + self.variant(PSZ_A::_512) + } + #[doc = "1024 bytes"] + #[inline(always)] + pub fn _1024(self) -> &'a mut W { + self.variant(PSZ_A::_1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 16)) | ((value as u32 & 0x07) << 16); + self.w + } +} +#[doc = "Field `RWWEEP` reader - RWW EEPROM Pages"] +pub struct RWWEEP_R(crate::FieldReader); +impl RWWEEP_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + RWWEEP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RWWEEP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RWWEEP` writer - RWW EEPROM Pages"] +pub struct RWWEEP_W<'a> { + w: &'a mut W, +} +impl<'a> RWWEEP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0fff << 20)) | ((value as u32 & 0x0fff) << 20); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - NVM Pages"] + #[inline(always)] + pub fn nvmp(&self) -> NVMP_R { + NVMP_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:18 - Page Size"] + #[inline(always)] + pub fn psz(&self) -> PSZ_R { + PSZ_R::new(((self.bits >> 16) & 0x07) as u8) + } + #[doc = "Bits 20:31 - RWW EEPROM Pages"] + #[inline(always)] + pub fn rwweep(&self) -> RWWEEP_R { + RWWEEP_R::new(((self.bits >> 20) & 0x0fff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - NVM Pages"] + #[inline(always)] + pub fn nvmp(&mut self) -> NVMP_W { + NVMP_W { w: self } + } + #[doc = "Bits 16:18 - Page Size"] + #[inline(always)] + pub fn psz(&mut self) -> PSZ_W { + PSZ_W { w: self } + } + #[doc = "Bits 20:31 - RWW EEPROM Pages"] + #[inline(always)] + pub fn rwweep(&mut self) -> RWWEEP_W { + RWWEEP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "NVM Parameter\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [param](index.html) module"] +pub struct PARAM_SPEC; +impl crate::RegisterSpec for PARAM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [param::R](R) reader structure"] +impl crate::Readable for PARAM_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [param::W](W) writer structure"] +impl crate::Writable for PARAM_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PARAM to value 0"] +impl crate::Resettable for PARAM_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/nvmctrl/pbldata0.rs b/pac/atsamc21n/src/nvmctrl/pbldata0.rs new file mode 100644 index 000000000000..ff2effaf4d89 --- /dev/null +++ b/pac/atsamc21n/src/nvmctrl/pbldata0.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PBLDATA0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Page Buffer Load Data 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pbldata0](index.html) module"] +pub struct PBLDATA0_SPEC; +impl crate::RegisterSpec for PBLDATA0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pbldata0::R](R) reader structure"] +impl crate::Readable for PBLDATA0_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PBLDATA0 to value 0"] +impl crate::Resettable for PBLDATA0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/nvmctrl/pbldata1.rs b/pac/atsamc21n/src/nvmctrl/pbldata1.rs new file mode 100644 index 000000000000..9fc6404691c5 --- /dev/null +++ b/pac/atsamc21n/src/nvmctrl/pbldata1.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PBLDATA1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Page Buffer Load Data 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pbldata1](index.html) module"] +pub struct PBLDATA1_SPEC; +impl crate::RegisterSpec for PBLDATA1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pbldata1::R](R) reader structure"] +impl crate::Readable for PBLDATA1_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PBLDATA1 to value 0"] +impl crate::Resettable for PBLDATA1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/nvmctrl/status.rs b/pac/atsamc21n/src/nvmctrl/status.rs new file mode 100644 index 000000000000..ce849015560e --- /dev/null +++ b/pac/atsamc21n/src/nvmctrl/status.rs @@ -0,0 +1,348 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PRM` reader - Power Reduction Mode"] +pub struct PRM_R(crate::FieldReader); +impl PRM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PRM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PRM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRM` writer - Power Reduction Mode"] +pub struct PRM_W<'a> { + w: &'a mut W, +} +impl<'a> PRM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `LOAD` reader - NVM Page Buffer Active Loading"] +pub struct LOAD_R(crate::FieldReader); +impl LOAD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LOAD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOAD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LOAD` writer - NVM Page Buffer Active Loading"] +pub struct LOAD_W<'a> { + w: &'a mut W, +} +impl<'a> LOAD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PROGE` reader - Programming Error Status"] +pub struct PROGE_R(crate::FieldReader); +impl PROGE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PROGE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PROGE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PROGE` writer - Programming Error Status"] +pub struct PROGE_W<'a> { + w: &'a mut W, +} +impl<'a> PROGE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `LOCKE` reader - Lock Error Status"] +pub struct LOCKE_R(crate::FieldReader); +impl LOCKE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LOCKE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOCKE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LOCKE` writer - Lock Error Status"] +pub struct LOCKE_W<'a> { + w: &'a mut W, +} +impl<'a> LOCKE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `NVME` reader - NVM Error"] +pub struct NVME_R(crate::FieldReader); +impl NVME_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NVME_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NVME_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NVME` writer - NVM Error"] +pub struct NVME_W<'a> { + w: &'a mut W, +} +impl<'a> NVME_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `SB` reader - Security Bit Status"] +pub struct SB_R(crate::FieldReader); +impl SB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SB` writer - Security Bit Status"] +pub struct SB_W<'a> { + w: &'a mut W, +} +impl<'a> SB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +impl R { + #[doc = "Bit 0 - Power Reduction Mode"] + #[inline(always)] + pub fn prm(&self) -> PRM_R { + PRM_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - NVM Page Buffer Active Loading"] + #[inline(always)] + pub fn load(&self) -> LOAD_R { + LOAD_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Programming Error Status"] + #[inline(always)] + pub fn proge(&self) -> PROGE_R { + PROGE_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Lock Error Status"] + #[inline(always)] + pub fn locke(&self) -> LOCKE_R { + LOCKE_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - NVM Error"] + #[inline(always)] + pub fn nvme(&self) -> NVME_R { + NVME_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 8 - Security Bit Status"] + #[inline(always)] + pub fn sb(&self) -> SB_R { + SB_R::new(((self.bits >> 8) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Power Reduction Mode"] + #[inline(always)] + pub fn prm(&mut self) -> PRM_W { + PRM_W { w: self } + } + #[doc = "Bit 1 - NVM Page Buffer Active Loading"] + #[inline(always)] + pub fn load(&mut self) -> LOAD_W { + LOAD_W { w: self } + } + #[doc = "Bit 2 - Programming Error Status"] + #[inline(always)] + pub fn proge(&mut self) -> PROGE_W { + PROGE_W { w: self } + } + #[doc = "Bit 3 - Lock Error Status"] + #[inline(always)] + pub fn locke(&mut self) -> LOCKE_W { + LOCKE_W { w: self } + } + #[doc = "Bit 4 - NVM Error"] + #[inline(always)] + pub fn nvme(&mut self) -> NVME_W { + NVME_W { w: self } + } + #[doc = "Bit 8 - Security Bit Status"] + #[inline(always)] + pub fn sb(&mut self) -> SB_W { + SB_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/osc32kctrl.rs b/pac/atsamc21n/src/osc32kctrl.rs new file mode 100644 index 000000000000..263cd2f61d59 --- /dev/null +++ b/pac/atsamc21n/src/osc32kctrl.rs @@ -0,0 +1,64 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x04 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x08 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x0c - Power and Clocks Status"] + pub status: crate::Reg, + #[doc = "0x10 - Clock selection"] + pub rtcctrl: crate::Reg, + #[doc = "0x14 - 32kHz External Crystal Oscillator (XOSC32K) Control"] + pub xosc32k: crate::Reg, + #[doc = "0x16 - Clock Failure Detector Control"] + pub cfdctrl: crate::Reg, + #[doc = "0x17 - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x18 - 32kHz Internal Oscillator (OSC32K) Control"] + pub osc32k: crate::Reg, + #[doc = "0x1c - 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control"] + pub osculp32k: crate::Reg, +} +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Power and Clocks Status"] +pub mod status; +#[doc = "RTCCTRL register accessor: an alias for `Reg`"] +pub type RTCCTRL = crate::Reg; +#[doc = "Clock selection"] +pub mod rtcctrl; +#[doc = "XOSC32K register accessor: an alias for `Reg`"] +pub type XOSC32K = crate::Reg; +#[doc = "32kHz External Crystal Oscillator (XOSC32K) Control"] +pub mod xosc32k; +#[doc = "CFDCTRL register accessor: an alias for `Reg`"] +pub type CFDCTRL = crate::Reg; +#[doc = "Clock Failure Detector Control"] +pub mod cfdctrl; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "OSC32K register accessor: an alias for `Reg`"] +pub type OSC32K = crate::Reg; +#[doc = "32kHz Internal Oscillator (OSC32K) Control"] +pub mod osc32k; +#[doc = "OSCULP32K register accessor: an alias for `Reg`"] +pub type OSCULP32K = crate::Reg; +#[doc = "32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control"] +pub mod osculp32k; diff --git a/pac/atsamc21n/src/osc32kctrl/cfdctrl.rs b/pac/atsamc21n/src/osc32kctrl/cfdctrl.rs new file mode 100644 index 000000000000..492a86e1a5a7 --- /dev/null +++ b/pac/atsamc21n/src/osc32kctrl/cfdctrl.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CFDCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CFDCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CFDEN` reader - Clock Failure Detector Enable"] +pub struct CFDEN_R(crate::FieldReader); +impl CFDEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFDEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFDEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFDEN` writer - Clock Failure Detector Enable"] +pub struct CFDEN_W<'a> { + w: &'a mut W, +} +impl<'a> CFDEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SWBACK` reader - Clock Switch Back"] +pub struct SWBACK_R(crate::FieldReader); +impl SWBACK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWBACK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWBACK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWBACK` writer - Clock Switch Back"] +pub struct SWBACK_W<'a> { + w: &'a mut W, +} +impl<'a> SWBACK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CFDPRESC` reader - Clock Failure Detector Prescaler"] +pub struct CFDPRESC_R(crate::FieldReader); +impl CFDPRESC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFDPRESC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFDPRESC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFDPRESC` writer - Clock Failure Detector Prescaler"] +pub struct CFDPRESC_W<'a> { + w: &'a mut W, +} +impl<'a> CFDPRESC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Clock Failure Detector Enable"] + #[inline(always)] + pub fn cfden(&self) -> CFDEN_R { + CFDEN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Clock Switch Back"] + #[inline(always)] + pub fn swback(&self) -> SWBACK_R { + SWBACK_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Clock Failure Detector Prescaler"] + #[inline(always)] + pub fn cfdpresc(&self) -> CFDPRESC_R { + CFDPRESC_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Clock Failure Detector Enable"] + #[inline(always)] + pub fn cfden(&mut self) -> CFDEN_W { + CFDEN_W { w: self } + } + #[doc = "Bit 1 - Clock Switch Back"] + #[inline(always)] + pub fn swback(&mut self) -> SWBACK_W { + SWBACK_W { w: self } + } + #[doc = "Bit 2 - Clock Failure Detector Prescaler"] + #[inline(always)] + pub fn cfdpresc(&mut self) -> CFDPRESC_W { + CFDPRESC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Clock Failure Detector Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cfdctrl](index.html) module"] +pub struct CFDCTRL_SPEC; +impl crate::RegisterSpec for CFDCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [cfdctrl::R](R) reader structure"] +impl crate::Readable for CFDCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cfdctrl::W](W) writer structure"] +impl crate::Writable for CFDCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CFDCTRL to value 0"] +impl crate::Resettable for CFDCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/osc32kctrl/evctrl.rs b/pac/atsamc21n/src/osc32kctrl/evctrl.rs new file mode 100644 index 000000000000..e22ba62f0fe2 --- /dev/null +++ b/pac/atsamc21n/src/osc32kctrl/evctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CFDEO` reader - Clock Failure Detector Event Output Enable"] +pub struct CFDEO_R(crate::FieldReader); +impl CFDEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFDEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFDEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFDEO` writer - Clock Failure Detector Event Output Enable"] +pub struct CFDEO_W<'a> { + w: &'a mut W, +} +impl<'a> CFDEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Clock Failure Detector Event Output Enable"] + #[inline(always)] + pub fn cfdeo(&self) -> CFDEO_R { + CFDEO_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Clock Failure Detector Event Output Enable"] + #[inline(always)] + pub fn cfdeo(&mut self) -> CFDEO_W { + CFDEO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/osc32kctrl/intenclr.rs b/pac/atsamc21n/src/osc32kctrl/intenclr.rs new file mode 100644 index 000000000000..7e330c8de495 --- /dev/null +++ b/pac/atsamc21n/src/osc32kctrl/intenclr.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XOSC32KRDY` reader - XOSC32K Ready Interrupt Enable"] +pub struct XOSC32KRDY_R(crate::FieldReader); +impl XOSC32KRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSC32KRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSC32KRDY` writer - XOSC32K Ready Interrupt Enable"] +pub struct XOSC32KRDY_W<'a> { + w: &'a mut W, +} +impl<'a> XOSC32KRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `OSC32KRDY` reader - OSC32K Ready Interrupt Enable"] +pub struct OSC32KRDY_R(crate::FieldReader); +impl OSC32KRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC32KRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC32KRDY` writer - OSC32K Ready Interrupt Enable"] +pub struct OSC32KRDY_W<'a> { + w: &'a mut W, +} +impl<'a> OSC32KRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CLKFAIL` reader - XOSC32K Clock Failure Detector Interrupt Enable"] +pub struct CLKFAIL_R(crate::FieldReader); +impl CLKFAIL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKFAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKFAIL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKFAIL` writer - XOSC32K Clock Failure Detector Interrupt Enable"] +pub struct CLKFAIL_W<'a> { + w: &'a mut W, +} +impl<'a> CLKFAIL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - XOSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn xosc32krdy(&self) -> XOSC32KRDY_R { + XOSC32KRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - OSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn osc32krdy(&self) -> OSC32KRDY_R { + OSC32KRDY_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - XOSC32K Clock Failure Detector Interrupt Enable"] + #[inline(always)] + pub fn clkfail(&self) -> CLKFAIL_R { + CLKFAIL_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - XOSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn xosc32krdy(&mut self) -> XOSC32KRDY_W { + XOSC32KRDY_W { w: self } + } + #[doc = "Bit 1 - OSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn osc32krdy(&mut self) -> OSC32KRDY_W { + OSC32KRDY_W { w: self } + } + #[doc = "Bit 2 - XOSC32K Clock Failure Detector Interrupt Enable"] + #[inline(always)] + pub fn clkfail(&mut self) -> CLKFAIL_W { + CLKFAIL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/osc32kctrl/intenset.rs b/pac/atsamc21n/src/osc32kctrl/intenset.rs new file mode 100644 index 000000000000..e853d40049f2 --- /dev/null +++ b/pac/atsamc21n/src/osc32kctrl/intenset.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XOSC32KRDY` reader - XOSC32K Ready Interrupt Enable"] +pub struct XOSC32KRDY_R(crate::FieldReader); +impl XOSC32KRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSC32KRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSC32KRDY` writer - XOSC32K Ready Interrupt Enable"] +pub struct XOSC32KRDY_W<'a> { + w: &'a mut W, +} +impl<'a> XOSC32KRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `OSC32KRDY` reader - OSC32K Ready Interrupt Enable"] +pub struct OSC32KRDY_R(crate::FieldReader); +impl OSC32KRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC32KRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC32KRDY` writer - OSC32K Ready Interrupt Enable"] +pub struct OSC32KRDY_W<'a> { + w: &'a mut W, +} +impl<'a> OSC32KRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CLKFAIL` reader - XOSC32K Clock Failure Detector Interrupt Enable"] +pub struct CLKFAIL_R(crate::FieldReader); +impl CLKFAIL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKFAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKFAIL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKFAIL` writer - XOSC32K Clock Failure Detector Interrupt Enable"] +pub struct CLKFAIL_W<'a> { + w: &'a mut W, +} +impl<'a> CLKFAIL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - XOSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn xosc32krdy(&self) -> XOSC32KRDY_R { + XOSC32KRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - OSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn osc32krdy(&self) -> OSC32KRDY_R { + OSC32KRDY_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - XOSC32K Clock Failure Detector Interrupt Enable"] + #[inline(always)] + pub fn clkfail(&self) -> CLKFAIL_R { + CLKFAIL_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - XOSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn xosc32krdy(&mut self) -> XOSC32KRDY_W { + XOSC32KRDY_W { w: self } + } + #[doc = "Bit 1 - OSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn osc32krdy(&mut self) -> OSC32KRDY_W { + OSC32KRDY_W { w: self } + } + #[doc = "Bit 2 - XOSC32K Clock Failure Detector Interrupt Enable"] + #[inline(always)] + pub fn clkfail(&mut self) -> CLKFAIL_W { + CLKFAIL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/osc32kctrl/intflag.rs b/pac/atsamc21n/src/osc32kctrl/intflag.rs new file mode 100644 index 000000000000..9ca42439429d --- /dev/null +++ b/pac/atsamc21n/src/osc32kctrl/intflag.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XOSC32KRDY` reader - XOSC32K Ready"] +pub struct XOSC32KRDY_R(crate::FieldReader); +impl XOSC32KRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSC32KRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSC32KRDY` writer - XOSC32K Ready"] +pub struct XOSC32KRDY_W<'a> { + w: &'a mut W, +} +impl<'a> XOSC32KRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `OSC32KRDY` reader - OSC32K Ready"] +pub struct OSC32KRDY_R(crate::FieldReader); +impl OSC32KRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC32KRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC32KRDY` writer - OSC32K Ready"] +pub struct OSC32KRDY_W<'a> { + w: &'a mut W, +} +impl<'a> OSC32KRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CLKFAIL` reader - XOSC32K Clock Failure Detector"] +pub struct CLKFAIL_R(crate::FieldReader); +impl CLKFAIL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKFAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKFAIL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKFAIL` writer - XOSC32K Clock Failure Detector"] +pub struct CLKFAIL_W<'a> { + w: &'a mut W, +} +impl<'a> CLKFAIL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - XOSC32K Ready"] + #[inline(always)] + pub fn xosc32krdy(&self) -> XOSC32KRDY_R { + XOSC32KRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - OSC32K Ready"] + #[inline(always)] + pub fn osc32krdy(&self) -> OSC32KRDY_R { + OSC32KRDY_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - XOSC32K Clock Failure Detector"] + #[inline(always)] + pub fn clkfail(&self) -> CLKFAIL_R { + CLKFAIL_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - XOSC32K Ready"] + #[inline(always)] + pub fn xosc32krdy(&mut self) -> XOSC32KRDY_W { + XOSC32KRDY_W { w: self } + } + #[doc = "Bit 1 - OSC32K Ready"] + #[inline(always)] + pub fn osc32krdy(&mut self) -> OSC32KRDY_W { + OSC32KRDY_W { w: self } + } + #[doc = "Bit 2 - XOSC32K Clock Failure Detector"] + #[inline(always)] + pub fn clkfail(&mut self) -> CLKFAIL_W { + CLKFAIL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/osc32kctrl/osc32k.rs b/pac/atsamc21n/src/osc32kctrl/osc32k.rs new file mode 100644 index 000000000000..aa32cb287aa7 --- /dev/null +++ b/pac/atsamc21n/src/osc32kctrl/osc32k.rs @@ -0,0 +1,549 @@ +#[doc = "Register `OSC32K` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OSC32K` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Oscillator Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Oscillator Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `EN32K` reader - 32kHz Output Enable"] +pub struct EN32K_R(crate::FieldReader); +impl EN32K_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EN32K_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EN32K_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EN32K` writer - 32kHz Output Enable"] +pub struct EN32K_W<'a> { + w: &'a mut W, +} +impl<'a> EN32K_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `EN1K` reader - 1kHz Output Enable"] +pub struct EN1K_R(crate::FieldReader); +impl EN1K_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EN1K_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EN1K_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EN1K` writer - 1kHz Output Enable"] +pub struct EN1K_W<'a> { + w: &'a mut W, +} +impl<'a> EN1K_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - On Demand Control"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - On Demand Control"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Oscillator Start-Up Time\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum STARTUP_A { + #[doc = "0: 0.092 ms"] + CYCLE3 = 0, + #[doc = "1: 0.122 ms"] + CYCLE4 = 1, + #[doc = "2: 0.183 ms"] + CYCLE6 = 2, + #[doc = "3: 0.305 ms"] + CYCLE10 = 3, + #[doc = "4: 0.549 ms"] + CYCLE18 = 4, + #[doc = "5: 1.038 ms"] + CYCLE34 = 5, + #[doc = "6: 2.014 ms"] + CYCLE66 = 6, + #[doc = "7: 3.967 ms"] + CYCLE130 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: STARTUP_A) -> Self { + variant as _ + } +} +#[doc = "Field `STARTUP` reader - Oscillator Start-Up Time"] +pub struct STARTUP_R(crate::FieldReader); +impl STARTUP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + STARTUP_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STARTUP_A { + match self.bits { + 0 => STARTUP_A::CYCLE3, + 1 => STARTUP_A::CYCLE4, + 2 => STARTUP_A::CYCLE6, + 3 => STARTUP_A::CYCLE10, + 4 => STARTUP_A::CYCLE18, + 5 => STARTUP_A::CYCLE34, + 6 => STARTUP_A::CYCLE66, + 7 => STARTUP_A::CYCLE130, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `CYCLE3`"] + #[inline(always)] + pub fn is_cycle3(&self) -> bool { + **self == STARTUP_A::CYCLE3 + } + #[doc = "Checks if the value of the field is `CYCLE4`"] + #[inline(always)] + pub fn is_cycle4(&self) -> bool { + **self == STARTUP_A::CYCLE4 + } + #[doc = "Checks if the value of the field is `CYCLE6`"] + #[inline(always)] + pub fn is_cycle6(&self) -> bool { + **self == STARTUP_A::CYCLE6 + } + #[doc = "Checks if the value of the field is `CYCLE10`"] + #[inline(always)] + pub fn is_cycle10(&self) -> bool { + **self == STARTUP_A::CYCLE10 + } + #[doc = "Checks if the value of the field is `CYCLE18`"] + #[inline(always)] + pub fn is_cycle18(&self) -> bool { + **self == STARTUP_A::CYCLE18 + } + #[doc = "Checks if the value of the field is `CYCLE34`"] + #[inline(always)] + pub fn is_cycle34(&self) -> bool { + **self == STARTUP_A::CYCLE34 + } + #[doc = "Checks if the value of the field is `CYCLE66`"] + #[inline(always)] + pub fn is_cycle66(&self) -> bool { + **self == STARTUP_A::CYCLE66 + } + #[doc = "Checks if the value of the field is `CYCLE130`"] + #[inline(always)] + pub fn is_cycle130(&self) -> bool { + **self == STARTUP_A::CYCLE130 + } +} +impl core::ops::Deref for STARTUP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STARTUP` writer - Oscillator Start-Up Time"] +pub struct STARTUP_W<'a> { + w: &'a mut W, +} +impl<'a> STARTUP_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: STARTUP_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "0.092 ms"] + #[inline(always)] + pub fn cycle3(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE3) + } + #[doc = "0.122 ms"] + #[inline(always)] + pub fn cycle4(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE4) + } + #[doc = "0.183 ms"] + #[inline(always)] + pub fn cycle6(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE6) + } + #[doc = "0.305 ms"] + #[inline(always)] + pub fn cycle10(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE10) + } + #[doc = "0.549 ms"] + #[inline(always)] + pub fn cycle18(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE18) + } + #[doc = "1.038 ms"] + #[inline(always)] + pub fn cycle34(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE34) + } + #[doc = "2.014 ms"] + #[inline(always)] + pub fn cycle66(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE66) + } + #[doc = "3.967 ms"] + #[inline(always)] + pub fn cycle130(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE130) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +#[doc = "Field `WRTLOCK` reader - Write Lock"] +pub struct WRTLOCK_R(crate::FieldReader); +impl WRTLOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WRTLOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WRTLOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WRTLOCK` writer - Write Lock"] +pub struct WRTLOCK_W<'a> { + w: &'a mut W, +} +impl<'a> WRTLOCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `CALIB` reader - Oscillator Calibration"] +pub struct CALIB_R(crate::FieldReader); +impl CALIB_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CALIB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CALIB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CALIB` writer - Oscillator Calibration"] +pub struct CALIB_W<'a> { + w: &'a mut W, +} +impl<'a> CALIB_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x7f << 16)) | ((value as u32 & 0x7f) << 16); + self.w + } +} +impl R { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - 32kHz Output Enable"] + #[inline(always)] + pub fn en32k(&self) -> EN32K_R { + EN32K_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - 1kHz Output Enable"] + #[inline(always)] + pub fn en1k(&self) -> EN1K_R { + EN1K_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Oscillator Start-Up Time"] + #[inline(always)] + pub fn startup(&self) -> STARTUP_R { + STARTUP_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 12 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&self) -> WRTLOCK_R { + WRTLOCK_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bits 16:22 - Oscillator Calibration"] + #[inline(always)] + pub fn calib(&self) -> CALIB_R { + CALIB_R::new(((self.bits >> 16) & 0x7f) as u8) + } +} +impl W { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - 32kHz Output Enable"] + #[inline(always)] + pub fn en32k(&mut self) -> EN32K_W { + EN32K_W { w: self } + } + #[doc = "Bit 3 - 1kHz Output Enable"] + #[inline(always)] + pub fn en1k(&mut self) -> EN1K_W { + EN1K_W { w: self } + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Bits 8:10 - Oscillator Start-Up Time"] + #[inline(always)] + pub fn startup(&mut self) -> STARTUP_W { + STARTUP_W { w: self } + } + #[doc = "Bit 12 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&mut self) -> WRTLOCK_W { + WRTLOCK_W { w: self } + } + #[doc = "Bits 16:22 - Oscillator Calibration"] + #[inline(always)] + pub fn calib(&mut self) -> CALIB_W { + CALIB_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "32kHz Internal Oscillator (OSC32K) Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [osc32k](index.html) module"] +pub struct OSC32K_SPEC; +impl crate::RegisterSpec for OSC32K_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [osc32k::R](R) reader structure"] +impl crate::Readable for OSC32K_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [osc32k::W](W) writer structure"] +impl crate::Writable for OSC32K_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OSC32K to value 0x003f_0080"] +impl crate::Resettable for OSC32K_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x003f_0080 + } +} diff --git a/pac/atsamc21n/src/osc32kctrl/osculp32k.rs b/pac/atsamc21n/src/osc32kctrl/osculp32k.rs new file mode 100644 index 000000000000..1c351c406e59 --- /dev/null +++ b/pac/atsamc21n/src/osc32kctrl/osculp32k.rs @@ -0,0 +1,150 @@ +#[doc = "Register `OSCULP32K` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OSCULP32K` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CALIB` reader - Oscillator Calibration"] +pub struct CALIB_R(crate::FieldReader); +impl CALIB_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CALIB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CALIB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CALIB` writer - Oscillator Calibration"] +pub struct CALIB_W<'a> { + w: &'a mut W, +} +impl<'a> CALIB_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 8)) | ((value as u32 & 0x1f) << 8); + self.w + } +} +#[doc = "Field `WRTLOCK` reader - Write Lock"] +pub struct WRTLOCK_R(crate::FieldReader); +impl WRTLOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WRTLOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WRTLOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WRTLOCK` writer - Write Lock"] +pub struct WRTLOCK_W<'a> { + w: &'a mut W, +} +impl<'a> WRTLOCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bits 8:12 - Oscillator Calibration"] + #[inline(always)] + pub fn calib(&self) -> CALIB_R { + CALIB_R::new(((self.bits >> 8) & 0x1f) as u8) + } + #[doc = "Bit 15 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&self) -> WRTLOCK_R { + WRTLOCK_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 8:12 - Oscillator Calibration"] + #[inline(always)] + pub fn calib(&mut self) -> CALIB_W { + CALIB_W { w: self } + } + #[doc = "Bit 15 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&mut self) -> WRTLOCK_W { + WRTLOCK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [osculp32k](index.html) module"] +pub struct OSCULP32K_SPEC; +impl crate::RegisterSpec for OSCULP32K_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [osculp32k::R](R) reader structure"] +impl crate::Readable for OSCULP32K_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [osculp32k::W](W) writer structure"] +impl crate::Writable for OSCULP32K_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OSCULP32K to value 0"] +impl crate::Resettable for OSCULP32K_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/osc32kctrl/rtcctrl.rs b/pac/atsamc21n/src/osc32kctrl/rtcctrl.rs new file mode 100644 index 000000000000..1248024a03b9 --- /dev/null +++ b/pac/atsamc21n/src/osc32kctrl/rtcctrl.rs @@ -0,0 +1,204 @@ +#[doc = "Register `RTCCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RTCCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "RTC Clock Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum RTCSEL_A { + #[doc = "0: 1.024kHz from 32kHz internal ULP oscillator"] + ULP1K = 0, + #[doc = "1: 32.768kHz from 32kHz internal ULP oscillator"] + ULP32K = 1, + #[doc = "2: 1.024kHz from 32.768kHz internal oscillator"] + OSC1K = 2, + #[doc = "3: 32.768kHz from 32.768kHz internal oscillator"] + OSC32K = 3, + #[doc = "4: 1.024kHz from 32.768kHz internal oscillator"] + XOSC1K = 4, + #[doc = "5: 32.768kHz from 32.768kHz external crystal oscillator"] + XOSC32K = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RTCSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `RTCSEL` reader - RTC Clock Selection"] +pub struct RTCSEL_R(crate::FieldReader); +impl RTCSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RTCSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(RTCSEL_A::ULP1K), + 1 => Some(RTCSEL_A::ULP32K), + 2 => Some(RTCSEL_A::OSC1K), + 3 => Some(RTCSEL_A::OSC32K), + 4 => Some(RTCSEL_A::XOSC1K), + 5 => Some(RTCSEL_A::XOSC32K), + _ => None, + } + } + #[doc = "Checks if the value of the field is `ULP1K`"] + #[inline(always)] + pub fn is_ulp1k(&self) -> bool { + **self == RTCSEL_A::ULP1K + } + #[doc = "Checks if the value of the field is `ULP32K`"] + #[inline(always)] + pub fn is_ulp32k(&self) -> bool { + **self == RTCSEL_A::ULP32K + } + #[doc = "Checks if the value of the field is `OSC1K`"] + #[inline(always)] + pub fn is_osc1k(&self) -> bool { + **self == RTCSEL_A::OSC1K + } + #[doc = "Checks if the value of the field is `OSC32K`"] + #[inline(always)] + pub fn is_osc32k(&self) -> bool { + **self == RTCSEL_A::OSC32K + } + #[doc = "Checks if the value of the field is `XOSC1K`"] + #[inline(always)] + pub fn is_xosc1k(&self) -> bool { + **self == RTCSEL_A::XOSC1K + } + #[doc = "Checks if the value of the field is `XOSC32K`"] + #[inline(always)] + pub fn is_xosc32k(&self) -> bool { + **self == RTCSEL_A::XOSC32K + } +} +impl core::ops::Deref for RTCSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RTCSEL` writer - RTC Clock Selection"] +pub struct RTCSEL_W<'a> { + w: &'a mut W, +} +impl<'a> RTCSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RTCSEL_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "1.024kHz from 32kHz internal ULP oscillator"] + #[inline(always)] + pub fn ulp1k(self) -> &'a mut W { + self.variant(RTCSEL_A::ULP1K) + } + #[doc = "32.768kHz from 32kHz internal ULP oscillator"] + #[inline(always)] + pub fn ulp32k(self) -> &'a mut W { + self.variant(RTCSEL_A::ULP32K) + } + #[doc = "1.024kHz from 32.768kHz internal oscillator"] + #[inline(always)] + pub fn osc1k(self) -> &'a mut W { + self.variant(RTCSEL_A::OSC1K) + } + #[doc = "32.768kHz from 32.768kHz internal oscillator"] + #[inline(always)] + pub fn osc32k(self) -> &'a mut W { + self.variant(RTCSEL_A::OSC32K) + } + #[doc = "1.024kHz from 32.768kHz internal oscillator"] + #[inline(always)] + pub fn xosc1k(self) -> &'a mut W { + self.variant(RTCSEL_A::XOSC1K) + } + #[doc = "32.768kHz from 32.768kHz external crystal oscillator"] + #[inline(always)] + pub fn xosc32k(self) -> &'a mut W { + self.variant(RTCSEL_A::XOSC32K) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - RTC Clock Selection"] + #[inline(always)] + pub fn rtcsel(&self) -> RTCSEL_R { + RTCSEL_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - RTC Clock Selection"] + #[inline(always)] + pub fn rtcsel(&mut self) -> RTCSEL_W { + RTCSEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Clock selection\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rtcctrl](index.html) module"] +pub struct RTCCTRL_SPEC; +impl crate::RegisterSpec for RTCCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rtcctrl::R](R) reader structure"] +impl crate::Readable for RTCCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rtcctrl::W](W) writer structure"] +impl crate::Writable for RTCCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RTCCTRL to value 0"] +impl crate::Resettable for RTCCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/osc32kctrl/status.rs b/pac/atsamc21n/src/osc32kctrl/status.rs new file mode 100644 index 000000000000..f1f1483ac4e8 --- /dev/null +++ b/pac/atsamc21n/src/osc32kctrl/status.rs @@ -0,0 +1,113 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `XOSC32KRDY` reader - XOSC32K Ready"] +pub struct XOSC32KRDY_R(crate::FieldReader); +impl XOSC32KRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSC32KRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC32KRDY` reader - OSC32K Ready"] +pub struct OSC32KRDY_R(crate::FieldReader); +impl OSC32KRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC32KRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKFAIL` reader - XOSC32K Clock Failure Detector"] +pub struct CLKFAIL_R(crate::FieldReader); +impl CLKFAIL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKFAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKFAIL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKSW` reader - XOSC32K Clock switch"] +pub struct CLKSW_R(crate::FieldReader); +impl CLKSW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKSW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKSW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - XOSC32K Ready"] + #[inline(always)] + pub fn xosc32krdy(&self) -> XOSC32KRDY_R { + XOSC32KRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - OSC32K Ready"] + #[inline(always)] + pub fn osc32krdy(&self) -> OSC32KRDY_R { + OSC32KRDY_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - XOSC32K Clock Failure Detector"] + #[inline(always)] + pub fn clkfail(&self) -> CLKFAIL_R { + CLKFAIL_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - XOSC32K Clock switch"] + #[inline(always)] + pub fn clksw(&self) -> CLKSW_R { + CLKSW_R::new(((self.bits >> 3) & 0x01) != 0) + } +} +#[doc = "Power and Clocks Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/osc32kctrl/xosc32k.rs b/pac/atsamc21n/src/osc32kctrl/xosc32k.rs new file mode 100644 index 000000000000..93e42bba3c0e --- /dev/null +++ b/pac/atsamc21n/src/osc32kctrl/xosc32k.rs @@ -0,0 +1,559 @@ +#[doc = "Register `XOSC32K` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `XOSC32K` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Oscillator Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Oscillator Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `XTALEN` reader - Crystal Oscillator Enable"] +pub struct XTALEN_R(crate::FieldReader); +impl XTALEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XTALEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XTALEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XTALEN` writer - Crystal Oscillator Enable"] +pub struct XTALEN_W<'a> { + w: &'a mut W, +} +impl<'a> XTALEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `EN32K` reader - 32kHz Output Enable"] +pub struct EN32K_R(crate::FieldReader); +impl EN32K_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EN32K_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EN32K_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EN32K` writer - 32kHz Output Enable"] +pub struct EN32K_W<'a> { + w: &'a mut W, +} +impl<'a> EN32K_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `EN1K` reader - 1kHz Output Enable"] +pub struct EN1K_R(crate::FieldReader); +impl EN1K_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EN1K_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EN1K_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EN1K` writer - 1kHz Output Enable"] +pub struct EN1K_W<'a> { + w: &'a mut W, +} +impl<'a> EN1K_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - On Demand Control"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - On Demand Control"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Oscillator Start-Up Time\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum STARTUP_A { + #[doc = "0: 0.122 ms"] + CYCLE1 = 0, + #[doc = "1: 1.068 ms"] + CYCLE32 = 1, + #[doc = "2: 62.6 ms"] + CYCLE2048 = 2, + #[doc = "3: 125 ms"] + CYCLE4096 = 3, + #[doc = "4: 500 ms"] + CYCLE16384 = 4, + #[doc = "5: 1000 ms"] + CYCLE32768 = 5, + #[doc = "6: 2000 ms"] + CYCLE65536 = 6, + #[doc = "7: 4000 ms"] + CYCLE131072 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: STARTUP_A) -> Self { + variant as _ + } +} +#[doc = "Field `STARTUP` reader - Oscillator Start-Up Time"] +pub struct STARTUP_R(crate::FieldReader); +impl STARTUP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + STARTUP_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STARTUP_A { + match self.bits { + 0 => STARTUP_A::CYCLE1, + 1 => STARTUP_A::CYCLE32, + 2 => STARTUP_A::CYCLE2048, + 3 => STARTUP_A::CYCLE4096, + 4 => STARTUP_A::CYCLE16384, + 5 => STARTUP_A::CYCLE32768, + 6 => STARTUP_A::CYCLE65536, + 7 => STARTUP_A::CYCLE131072, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `CYCLE1`"] + #[inline(always)] + pub fn is_cycle1(&self) -> bool { + **self == STARTUP_A::CYCLE1 + } + #[doc = "Checks if the value of the field is `CYCLE32`"] + #[inline(always)] + pub fn is_cycle32(&self) -> bool { + **self == STARTUP_A::CYCLE32 + } + #[doc = "Checks if the value of the field is `CYCLE2048`"] + #[inline(always)] + pub fn is_cycle2048(&self) -> bool { + **self == STARTUP_A::CYCLE2048 + } + #[doc = "Checks if the value of the field is `CYCLE4096`"] + #[inline(always)] + pub fn is_cycle4096(&self) -> bool { + **self == STARTUP_A::CYCLE4096 + } + #[doc = "Checks if the value of the field is `CYCLE16384`"] + #[inline(always)] + pub fn is_cycle16384(&self) -> bool { + **self == STARTUP_A::CYCLE16384 + } + #[doc = "Checks if the value of the field is `CYCLE32768`"] + #[inline(always)] + pub fn is_cycle32768(&self) -> bool { + **self == STARTUP_A::CYCLE32768 + } + #[doc = "Checks if the value of the field is `CYCLE65536`"] + #[inline(always)] + pub fn is_cycle65536(&self) -> bool { + **self == STARTUP_A::CYCLE65536 + } + #[doc = "Checks if the value of the field is `CYCLE131072`"] + #[inline(always)] + pub fn is_cycle131072(&self) -> bool { + **self == STARTUP_A::CYCLE131072 + } +} +impl core::ops::Deref for STARTUP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STARTUP` writer - Oscillator Start-Up Time"] +pub struct STARTUP_W<'a> { + w: &'a mut W, +} +impl<'a> STARTUP_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: STARTUP_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "0.122 ms"] + #[inline(always)] + pub fn cycle1(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE1) + } + #[doc = "1.068 ms"] + #[inline(always)] + pub fn cycle32(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE32) + } + #[doc = "62.6 ms"] + #[inline(always)] + pub fn cycle2048(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE2048) + } + #[doc = "125 ms"] + #[inline(always)] + pub fn cycle4096(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE4096) + } + #[doc = "500 ms"] + #[inline(always)] + pub fn cycle16384(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE16384) + } + #[doc = "1000 ms"] + #[inline(always)] + pub fn cycle32768(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE32768) + } + #[doc = "2000 ms"] + #[inline(always)] + pub fn cycle65536(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE65536) + } + #[doc = "4000 ms"] + #[inline(always)] + pub fn cycle131072(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE131072) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u16 & 0x07) << 8); + self.w + } +} +#[doc = "Field `WRTLOCK` reader - Write Lock"] +pub struct WRTLOCK_R(crate::FieldReader); +impl WRTLOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WRTLOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WRTLOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WRTLOCK` writer - Write Lock"] +pub struct WRTLOCK_W<'a> { + w: &'a mut W, +} +impl<'a> WRTLOCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u16 & 0x01) << 12); + self.w + } +} +impl R { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Crystal Oscillator Enable"] + #[inline(always)] + pub fn xtalen(&self) -> XTALEN_R { + XTALEN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - 32kHz Output Enable"] + #[inline(always)] + pub fn en32k(&self) -> EN32K_R { + EN32K_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - 1kHz Output Enable"] + #[inline(always)] + pub fn en1k(&self) -> EN1K_R { + EN1K_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Oscillator Start-Up Time"] + #[inline(always)] + pub fn startup(&self) -> STARTUP_R { + STARTUP_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 12 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&self) -> WRTLOCK_R { + WRTLOCK_R::new(((self.bits >> 12) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - Crystal Oscillator Enable"] + #[inline(always)] + pub fn xtalen(&mut self) -> XTALEN_W { + XTALEN_W { w: self } + } + #[doc = "Bit 3 - 32kHz Output Enable"] + #[inline(always)] + pub fn en32k(&mut self) -> EN32K_W { + EN32K_W { w: self } + } + #[doc = "Bit 4 - 1kHz Output Enable"] + #[inline(always)] + pub fn en1k(&mut self) -> EN1K_W { + EN1K_W { w: self } + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Bits 8:10 - Oscillator Start-Up Time"] + #[inline(always)] + pub fn startup(&mut self) -> STARTUP_W { + STARTUP_W { w: self } + } + #[doc = "Bit 12 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&mut self) -> WRTLOCK_W { + WRTLOCK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "32kHz External Crystal Oscillator (XOSC32K) Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [xosc32k](index.html) module"] +pub struct XOSC32K_SPEC; +impl crate::RegisterSpec for XOSC32K_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [xosc32k::R](R) reader structure"] +impl crate::Readable for XOSC32K_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [xosc32k::W](W) writer structure"] +impl crate::Writable for XOSC32K_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets XOSC32K to value 0x80"] +impl crate::Resettable for XOSC32K_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x80 + } +} diff --git a/pac/atsamc21n/src/oscctrl.rs b/pac/atsamc21n/src/oscctrl.rs new file mode 100644 index 000000000000..e6dd0929927c --- /dev/null +++ b/pac/atsamc21n/src/oscctrl.rs @@ -0,0 +1,117 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x04 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x08 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x0c - Power and Clocks Status"] + pub status: crate::Reg, + #[doc = "0x10 - External Multipurpose Crystal Oscillator (XOSC) Control"] + pub xoscctrl: crate::Reg, + #[doc = "0x12 - Clock Failure Detector Prescaler"] + pub cfdpresc: crate::Reg, + #[doc = "0x13 - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x14 - 48MHz Internal Oscillator (OSC48M) Control"] + pub osc48mctrl: crate::Reg, + #[doc = "0x15 - OSC48M Divider"] + pub osc48mdiv: crate::Reg, + #[doc = "0x16 - OSC48M Startup Time"] + pub osc48mstup: crate::Reg, + _reserved10: [u8; 0x01], + #[doc = "0x18 - OSC48M Synchronization Busy"] + pub osc48msyncbusy: crate::Reg, + #[doc = "0x1c - DPLL Control"] + pub dpllctrla: crate::Reg, + _reserved12: [u8; 0x03], + #[doc = "0x20 - DPLL Ratio Control"] + pub dpllratio: crate::Reg, + #[doc = "0x24 - Digital Core Configuration"] + pub dpllctrlb: crate::Reg, + #[doc = "0x28 - DPLL Prescaler"] + pub dpllpresc: crate::Reg, + _reserved15: [u8; 0x03], + #[doc = "0x2c - DPLL Synchronization Busy"] + pub dpllsyncbusy: crate::Reg, + _reserved16: [u8; 0x03], + #[doc = "0x30 - DPLL Status"] + pub dpllstatus: crate::Reg, + _reserved17: [u8; 0x07], + #[doc = "0x38 - 48MHz Oscillator Calibration"] + pub cal48m: crate::Reg, +} +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Power and Clocks Status"] +pub mod status; +#[doc = "XOSCCTRL register accessor: an alias for `Reg`"] +pub type XOSCCTRL = crate::Reg; +#[doc = "External Multipurpose Crystal Oscillator (XOSC) Control"] +pub mod xoscctrl; +#[doc = "CFDPRESC register accessor: an alias for `Reg`"] +pub type CFDPRESC = crate::Reg; +#[doc = "Clock Failure Detector Prescaler"] +pub mod cfdpresc; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "OSC48MCTRL register accessor: an alias for `Reg`"] +pub type OSC48MCTRL = crate::Reg; +#[doc = "48MHz Internal Oscillator (OSC48M) Control"] +pub mod osc48mctrl; +#[doc = "OSC48MDIV register accessor: an alias for `Reg`"] +pub type OSC48MDIV = crate::Reg; +#[doc = "OSC48M Divider"] +pub mod osc48mdiv; +#[doc = "OSC48MSTUP register accessor: an alias for `Reg`"] +pub type OSC48MSTUP = crate::Reg; +#[doc = "OSC48M Startup Time"] +pub mod osc48mstup; +#[doc = "OSC48MSYNCBUSY register accessor: an alias for `Reg`"] +pub type OSC48MSYNCBUSY = crate::Reg; +#[doc = "OSC48M Synchronization Busy"] +pub mod osc48msyncbusy; +#[doc = "DPLLCTRLA register accessor: an alias for `Reg`"] +pub type DPLLCTRLA = crate::Reg; +#[doc = "DPLL Control"] +pub mod dpllctrla; +#[doc = "DPLLRATIO register accessor: an alias for `Reg`"] +pub type DPLLRATIO = crate::Reg; +#[doc = "DPLL Ratio Control"] +pub mod dpllratio; +#[doc = "DPLLCTRLB register accessor: an alias for `Reg`"] +pub type DPLLCTRLB = crate::Reg; +#[doc = "Digital Core Configuration"] +pub mod dpllctrlb; +#[doc = "DPLLPRESC register accessor: an alias for `Reg`"] +pub type DPLLPRESC = crate::Reg; +#[doc = "DPLL Prescaler"] +pub mod dpllpresc; +#[doc = "DPLLSYNCBUSY register accessor: an alias for `Reg`"] +pub type DPLLSYNCBUSY = crate::Reg; +#[doc = "DPLL Synchronization Busy"] +pub mod dpllsyncbusy; +#[doc = "DPLLSTATUS register accessor: an alias for `Reg`"] +pub type DPLLSTATUS = crate::Reg; +#[doc = "DPLL Status"] +pub mod dpllstatus; +#[doc = "CAL48M register accessor: an alias for `Reg`"] +pub type CAL48M = crate::Reg; +#[doc = "48MHz Oscillator Calibration"] +pub mod cal48m; diff --git a/pac/atsamc21n/src/oscctrl/cal48m.rs b/pac/atsamc21n/src/oscctrl/cal48m.rs new file mode 100644 index 000000000000..05d5cd2bbc92 --- /dev/null +++ b/pac/atsamc21n/src/oscctrl/cal48m.rs @@ -0,0 +1,177 @@ +#[doc = "Register `CAL48M` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CAL48M` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FCAL` reader - Frequency Calibration (48MHz)"] +pub struct FCAL_R(crate::FieldReader); +impl FCAL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FCAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FCAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FCAL` writer - Frequency Calibration (48MHz)"] +pub struct FCAL_W<'a> { + w: &'a mut W, +} +impl<'a> FCAL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +#[doc = "Field `FRANGE` reader - Frequency Range (48MHz)"] +pub struct FRANGE_R(crate::FieldReader); +impl FRANGE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FRANGE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FRANGE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FRANGE` writer - Frequency Range (48MHz)"] +pub struct FRANGE_W<'a> { + w: &'a mut W, +} +impl<'a> FRANGE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 8)) | ((value as u32 & 0x03) << 8); + self.w + } +} +#[doc = "Field `TCAL` reader - Temperature Calibration (48MHz)"] +pub struct TCAL_R(crate::FieldReader); +impl TCAL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TCAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCAL` writer - Temperature Calibration (48MHz)"] +pub struct TCAL_W<'a> { + w: &'a mut W, +} +impl<'a> TCAL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 16)) | ((value as u32 & 0x3f) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Frequency Calibration (48MHz)"] + #[inline(always)] + pub fn fcal(&self) -> FCAL_R { + FCAL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 8:9 - Frequency Range (48MHz)"] + #[inline(always)] + pub fn frange(&self) -> FRANGE_R { + FRANGE_R::new(((self.bits >> 8) & 0x03) as u8) + } + #[doc = "Bits 16:21 - Temperature Calibration (48MHz)"] + #[inline(always)] + pub fn tcal(&self) -> TCAL_R { + TCAL_R::new(((self.bits >> 16) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - Frequency Calibration (48MHz)"] + #[inline(always)] + pub fn fcal(&mut self) -> FCAL_W { + FCAL_W { w: self } + } + #[doc = "Bits 8:9 - Frequency Range (48MHz)"] + #[inline(always)] + pub fn frange(&mut self) -> FRANGE_W { + FRANGE_W { w: self } + } + #[doc = "Bits 16:21 - Temperature Calibration (48MHz)"] + #[inline(always)] + pub fn tcal(&mut self) -> TCAL_W { + TCAL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "48MHz Oscillator Calibration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cal48m](index.html) module"] +pub struct CAL48M_SPEC; +impl crate::RegisterSpec for CAL48M_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cal48m::R](R) reader structure"] +impl crate::Readable for CAL48M_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cal48m::W](W) writer structure"] +impl crate::Writable for CAL48M_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CAL48M to value 0"] +impl crate::Resettable for CAL48M_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/oscctrl/cfdpresc.rs b/pac/atsamc21n/src/oscctrl/cfdpresc.rs new file mode 100644 index 000000000000..029ae541eec5 --- /dev/null +++ b/pac/atsamc21n/src/oscctrl/cfdpresc.rs @@ -0,0 +1,230 @@ +#[doc = "Register `CFDPRESC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CFDPRESC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Clock Failure Detector Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CFDPRESC_A { + #[doc = "0: 48 MHz"] + DIV1 = 0, + #[doc = "1: 24 MHz"] + DIV2 = 1, + #[doc = "2: 12 MHz"] + DIV4 = 2, + #[doc = "3: 6 MHz"] + DIV8 = 3, + #[doc = "4: 3 MHz"] + DIV16 = 4, + #[doc = "5: 1.5 MHz"] + DIV32 = 5, + #[doc = "6: 0.75 MHz"] + DIV64 = 6, + #[doc = "7: 0.3125 MHz"] + DIV128 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CFDPRESC_A) -> Self { + variant as _ + } +} +#[doc = "Field `CFDPRESC` reader - Clock Failure Detector Prescaler"] +pub struct CFDPRESC_R(crate::FieldReader); +impl CFDPRESC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CFDPRESC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CFDPRESC_A { + match self.bits { + 0 => CFDPRESC_A::DIV1, + 1 => CFDPRESC_A::DIV2, + 2 => CFDPRESC_A::DIV4, + 3 => CFDPRESC_A::DIV8, + 4 => CFDPRESC_A::DIV16, + 5 => CFDPRESC_A::DIV32, + 6 => CFDPRESC_A::DIV64, + 7 => CFDPRESC_A::DIV128, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == CFDPRESC_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == CFDPRESC_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == CFDPRESC_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == CFDPRESC_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == CFDPRESC_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == CFDPRESC_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == CFDPRESC_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == CFDPRESC_A::DIV128 + } +} +impl core::ops::Deref for CFDPRESC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFDPRESC` writer - Clock Failure Detector Prescaler"] +pub struct CFDPRESC_W<'a> { + w: &'a mut W, +} +impl<'a> CFDPRESC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CFDPRESC_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "48 MHz"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(CFDPRESC_A::DIV1) + } + #[doc = "24 MHz"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(CFDPRESC_A::DIV2) + } + #[doc = "12 MHz"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(CFDPRESC_A::DIV4) + } + #[doc = "6 MHz"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(CFDPRESC_A::DIV8) + } + #[doc = "3 MHz"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(CFDPRESC_A::DIV16) + } + #[doc = "1.5 MHz"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(CFDPRESC_A::DIV32) + } + #[doc = "0.75 MHz"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(CFDPRESC_A::DIV64) + } + #[doc = "0.3125 MHz"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(CFDPRESC_A::DIV128) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Clock Failure Detector Prescaler"] + #[inline(always)] + pub fn cfdpresc(&self) -> CFDPRESC_R { + CFDPRESC_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Clock Failure Detector Prescaler"] + #[inline(always)] + pub fn cfdpresc(&mut self) -> CFDPRESC_W { + CFDPRESC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Clock Failure Detector Prescaler\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cfdpresc](index.html) module"] +pub struct CFDPRESC_SPEC; +impl crate::RegisterSpec for CFDPRESC_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [cfdpresc::R](R) reader structure"] +impl crate::Readable for CFDPRESC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cfdpresc::W](W) writer structure"] +impl crate::Writable for CFDPRESC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CFDPRESC to value 0"] +impl crate::Resettable for CFDPRESC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/oscctrl/dpllctrla.rs b/pac/atsamc21n/src/oscctrl/dpllctrla.rs new file mode 100644 index 000000000000..5a60a5087002 --- /dev/null +++ b/pac/atsamc21n/src/oscctrl/dpllctrla.rs @@ -0,0 +1,207 @@ +#[doc = "Register `DPLLCTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DPLLCTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - On Demand"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - On Demand"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - On Demand"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - On Demand"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DPLL Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dpllctrla](index.html) module"] +pub struct DPLLCTRLA_SPEC; +impl crate::RegisterSpec for DPLLCTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dpllctrla::R](R) reader structure"] +impl crate::Readable for DPLLCTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dpllctrla::W](W) writer structure"] +impl crate::Writable for DPLLCTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DPLLCTRLA to value 0x80"] +impl crate::Resettable for DPLLCTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x80 + } +} diff --git a/pac/atsamc21n/src/oscctrl/dpllctrlb.rs b/pac/atsamc21n/src/oscctrl/dpllctrlb.rs new file mode 100644 index 000000000000..8400b0572dd0 --- /dev/null +++ b/pac/atsamc21n/src/oscctrl/dpllctrlb.rs @@ -0,0 +1,580 @@ +#[doc = "Register `DPLLCTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DPLLCTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Proportional Integral Filter Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FILTER_A { + #[doc = "0: Default filter mode"] + DEFAULT = 0, + #[doc = "1: Low bandwidth filter"] + LBFILT = 1, + #[doc = "2: High bandwidth filter"] + HBFILT = 2, + #[doc = "3: High damping filter"] + HDFILT = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FILTER_A) -> Self { + variant as _ + } +} +#[doc = "Field `FILTER` reader - Proportional Integral Filter Selection"] +pub struct FILTER_R(crate::FieldReader); +impl FILTER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FILTER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FILTER_A { + match self.bits { + 0 => FILTER_A::DEFAULT, + 1 => FILTER_A::LBFILT, + 2 => FILTER_A::HBFILT, + 3 => FILTER_A::HDFILT, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DEFAULT`"] + #[inline(always)] + pub fn is_default(&self) -> bool { + **self == FILTER_A::DEFAULT + } + #[doc = "Checks if the value of the field is `LBFILT`"] + #[inline(always)] + pub fn is_lbfilt(&self) -> bool { + **self == FILTER_A::LBFILT + } + #[doc = "Checks if the value of the field is `HBFILT`"] + #[inline(always)] + pub fn is_hbfilt(&self) -> bool { + **self == FILTER_A::HBFILT + } + #[doc = "Checks if the value of the field is `HDFILT`"] + #[inline(always)] + pub fn is_hdfilt(&self) -> bool { + **self == FILTER_A::HDFILT + } +} +impl core::ops::Deref for FILTER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTER` writer - Proportional Integral Filter Selection"] +pub struct FILTER_W<'a> { + w: &'a mut W, +} +impl<'a> FILTER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FILTER_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Default filter mode"] + #[inline(always)] + pub fn default(self) -> &'a mut W { + self.variant(FILTER_A::DEFAULT) + } + #[doc = "Low bandwidth filter"] + #[inline(always)] + pub fn lbfilt(self) -> &'a mut W { + self.variant(FILTER_A::LBFILT) + } + #[doc = "High bandwidth filter"] + #[inline(always)] + pub fn hbfilt(self) -> &'a mut W { + self.variant(FILTER_A::HBFILT) + } + #[doc = "High damping filter"] + #[inline(always)] + pub fn hdfilt(self) -> &'a mut W { + self.variant(FILTER_A::HDFILT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u32 & 0x03); + self.w + } +} +#[doc = "Field `LPEN` reader - Low-Power Enable"] +pub struct LPEN_R(crate::FieldReader); +impl LPEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LPEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LPEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LPEN` writer - Low-Power Enable"] +pub struct LPEN_W<'a> { + w: &'a mut W, +} +impl<'a> LPEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `WUF` reader - Wake Up Fast"] +pub struct WUF_R(crate::FieldReader); +impl WUF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WUF` writer - Wake Up Fast"] +pub struct WUF_W<'a> { + w: &'a mut W, +} +impl<'a> WUF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Reference Clock Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum REFCLK_A { + #[doc = "0: XOSC32K clock reference"] + XOSC32K = 0, + #[doc = "1: XOSC clock reference"] + XOSC = 1, + #[doc = "2: GCLK clock reference"] + GCLK = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: REFCLK_A) -> Self { + variant as _ + } +} +#[doc = "Field `REFCLK` reader - Reference Clock Selection"] +pub struct REFCLK_R(crate::FieldReader); +impl REFCLK_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REFCLK_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(REFCLK_A::XOSC32K), + 1 => Some(REFCLK_A::XOSC), + 2 => Some(REFCLK_A::GCLK), + _ => None, + } + } + #[doc = "Checks if the value of the field is `XOSC32K`"] + #[inline(always)] + pub fn is_xosc32k(&self) -> bool { + **self == REFCLK_A::XOSC32K + } + #[doc = "Checks if the value of the field is `XOSC`"] + #[inline(always)] + pub fn is_xosc(&self) -> bool { + **self == REFCLK_A::XOSC + } + #[doc = "Checks if the value of the field is `GCLK`"] + #[inline(always)] + pub fn is_gclk(&self) -> bool { + **self == REFCLK_A::GCLK + } +} +impl core::ops::Deref for REFCLK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REFCLK` writer - Reference Clock Selection"] +pub struct REFCLK_W<'a> { + w: &'a mut W, +} +impl<'a> REFCLK_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: REFCLK_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "XOSC32K clock reference"] + #[inline(always)] + pub fn xosc32k(self) -> &'a mut W { + self.variant(REFCLK_A::XOSC32K) + } + #[doc = "XOSC clock reference"] + #[inline(always)] + pub fn xosc(self) -> &'a mut W { + self.variant(REFCLK_A::XOSC) + } + #[doc = "GCLK clock reference"] + #[inline(always)] + pub fn gclk(self) -> &'a mut W { + self.variant(REFCLK_A::GCLK) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u32 & 0x03) << 4); + self.w + } +} +#[doc = "Lock Time\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum LTIME_A { + #[doc = "0: No time-out. Automatic lock."] + DEFAULT = 0, + #[doc = "4: Time-out if no lock within 8ms"] + _8MS = 4, + #[doc = "5: Time-out if no lock within 9ms"] + _9MS = 5, + #[doc = "6: Time-out if no lock within 10ms"] + _10MS = 6, + #[doc = "7: Time-out if no lock within 11ms"] + _11MS = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LTIME_A) -> Self { + variant as _ + } +} +#[doc = "Field `LTIME` reader - Lock Time"] +pub struct LTIME_R(crate::FieldReader); +impl LTIME_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LTIME_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(LTIME_A::DEFAULT), + 4 => Some(LTIME_A::_8MS), + 5 => Some(LTIME_A::_9MS), + 6 => Some(LTIME_A::_10MS), + 7 => Some(LTIME_A::_11MS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DEFAULT`"] + #[inline(always)] + pub fn is_default(&self) -> bool { + **self == LTIME_A::DEFAULT + } + #[doc = "Checks if the value of the field is `_8MS`"] + #[inline(always)] + pub fn is_8ms(&self) -> bool { + **self == LTIME_A::_8MS + } + #[doc = "Checks if the value of the field is `_9MS`"] + #[inline(always)] + pub fn is_9ms(&self) -> bool { + **self == LTIME_A::_9MS + } + #[doc = "Checks if the value of the field is `_10MS`"] + #[inline(always)] + pub fn is_10ms(&self) -> bool { + **self == LTIME_A::_10MS + } + #[doc = "Checks if the value of the field is `_11MS`"] + #[inline(always)] + pub fn is_11ms(&self) -> bool { + **self == LTIME_A::_11MS + } +} +impl core::ops::Deref for LTIME_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LTIME` writer - Lock Time"] +pub struct LTIME_W<'a> { + w: &'a mut W, +} +impl<'a> LTIME_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: LTIME_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No time-out. Automatic lock."] + #[inline(always)] + pub fn default(self) -> &'a mut W { + self.variant(LTIME_A::DEFAULT) + } + #[doc = "Time-out if no lock within 8ms"] + #[inline(always)] + pub fn _8ms(self) -> &'a mut W { + self.variant(LTIME_A::_8MS) + } + #[doc = "Time-out if no lock within 9ms"] + #[inline(always)] + pub fn _9ms(self) -> &'a mut W { + self.variant(LTIME_A::_9MS) + } + #[doc = "Time-out if no lock within 10ms"] + #[inline(always)] + pub fn _10ms(self) -> &'a mut W { + self.variant(LTIME_A::_10MS) + } + #[doc = "Time-out if no lock within 11ms"] + #[inline(always)] + pub fn _11ms(self) -> &'a mut W { + self.variant(LTIME_A::_11MS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +#[doc = "Field `LBYPASS` reader - Lock Bypass"] +pub struct LBYPASS_R(crate::FieldReader); +impl LBYPASS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LBYPASS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LBYPASS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LBYPASS` writer - Lock Bypass"] +pub struct LBYPASS_W<'a> { + w: &'a mut W, +} +impl<'a> LBYPASS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `DIV` reader - Clock Divider"] +pub struct DIV_R(crate::FieldReader); +impl DIV_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + DIV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIV` writer - Clock Divider"] +pub struct DIV_W<'a> { + w: &'a mut W, +} +impl<'a> DIV_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07ff << 16)) | ((value as u32 & 0x07ff) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Proportional Integral Filter Selection"] + #[inline(always)] + pub fn filter(&self) -> FILTER_R { + FILTER_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bit 2 - Low-Power Enable"] + #[inline(always)] + pub fn lpen(&self) -> LPEN_R { + LPEN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Wake Up Fast"] + #[inline(always)] + pub fn wuf(&self) -> WUF_R { + WUF_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bits 4:5 - Reference Clock Selection"] + #[inline(always)] + pub fn refclk(&self) -> REFCLK_R { + REFCLK_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bits 8:10 - Lock Time"] + #[inline(always)] + pub fn ltime(&self) -> LTIME_R { + LTIME_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 12 - Lock Bypass"] + #[inline(always)] + pub fn lbypass(&self) -> LBYPASS_R { + LBYPASS_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bits 16:26 - Clock Divider"] + #[inline(always)] + pub fn div(&self) -> DIV_R { + DIV_R::new(((self.bits >> 16) & 0x07ff) as u16) + } +} +impl W { + #[doc = "Bits 0:1 - Proportional Integral Filter Selection"] + #[inline(always)] + pub fn filter(&mut self) -> FILTER_W { + FILTER_W { w: self } + } + #[doc = "Bit 2 - Low-Power Enable"] + #[inline(always)] + pub fn lpen(&mut self) -> LPEN_W { + LPEN_W { w: self } + } + #[doc = "Bit 3 - Wake Up Fast"] + #[inline(always)] + pub fn wuf(&mut self) -> WUF_W { + WUF_W { w: self } + } + #[doc = "Bits 4:5 - Reference Clock Selection"] + #[inline(always)] + pub fn refclk(&mut self) -> REFCLK_W { + REFCLK_W { w: self } + } + #[doc = "Bits 8:10 - Lock Time"] + #[inline(always)] + pub fn ltime(&mut self) -> LTIME_W { + LTIME_W { w: self } + } + #[doc = "Bit 12 - Lock Bypass"] + #[inline(always)] + pub fn lbypass(&mut self) -> LBYPASS_W { + LBYPASS_W { w: self } + } + #[doc = "Bits 16:26 - Clock Divider"] + #[inline(always)] + pub fn div(&mut self) -> DIV_W { + DIV_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Digital Core Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dpllctrlb](index.html) module"] +pub struct DPLLCTRLB_SPEC; +impl crate::RegisterSpec for DPLLCTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dpllctrlb::R](R) reader structure"] +impl crate::Readable for DPLLCTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dpllctrlb::W](W) writer structure"] +impl crate::Writable for DPLLCTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DPLLCTRLB to value 0"] +impl crate::Resettable for DPLLCTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/oscctrl/dpllpresc.rs b/pac/atsamc21n/src/oscctrl/dpllpresc.rs new file mode 100644 index 000000000000..9de662161f99 --- /dev/null +++ b/pac/atsamc21n/src/oscctrl/dpllpresc.rs @@ -0,0 +1,165 @@ +#[doc = "Register `DPLLPRESC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DPLLPRESC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Output Clock Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESC_A { + #[doc = "0: DPLL output is divided by 1"] + DIV1 = 0, + #[doc = "1: DPLL output is divided by 2"] + DIV2 = 1, + #[doc = "2: DPLL output is divided by 4"] + DIV4 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESC_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESC` reader - Output Clock Prescaler"] +pub struct PRESC_R(crate::FieldReader); +impl PRESC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESC_A::DIV1), + 1 => Some(PRESC_A::DIV2), + 2 => Some(PRESC_A::DIV4), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == PRESC_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESC_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESC_A::DIV4 + } +} +impl core::ops::Deref for PRESC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESC` writer - Output Clock Prescaler"] +pub struct PRESC_W<'a> { + w: &'a mut W, +} +impl<'a> PRESC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESC_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "DPLL output is divided by 1"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESC_A::DIV1) + } + #[doc = "DPLL output is divided by 2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESC_A::DIV2) + } + #[doc = "DPLL output is divided by 4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESC_A::DIV4) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u8 & 0x03); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Output Clock Prescaler"] + #[inline(always)] + pub fn presc(&self) -> PRESC_R { + PRESC_R::new((self.bits & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Output Clock Prescaler"] + #[inline(always)] + pub fn presc(&mut self) -> PRESC_W { + PRESC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DPLL Prescaler\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dpllpresc](index.html) module"] +pub struct DPLLPRESC_SPEC; +impl crate::RegisterSpec for DPLLPRESC_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dpllpresc::R](R) reader structure"] +impl crate::Readable for DPLLPRESC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dpllpresc::W](W) writer structure"] +impl crate::Writable for DPLLPRESC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DPLLPRESC to value 0"] +impl crate::Resettable for DPLLPRESC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/oscctrl/dpllratio.rs b/pac/atsamc21n/src/oscctrl/dpllratio.rs new file mode 100644 index 000000000000..93b39e30f1a5 --- /dev/null +++ b/pac/atsamc21n/src/oscctrl/dpllratio.rs @@ -0,0 +1,140 @@ +#[doc = "Register `DPLLRATIO` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DPLLRATIO` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `LDR` reader - Loop Divider Ratio"] +pub struct LDR_R(crate::FieldReader); +impl LDR_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + LDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LDR` writer - Loop Divider Ratio"] +pub struct LDR_W<'a> { + w: &'a mut W, +} +impl<'a> LDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0fff) | (value as u32 & 0x0fff); + self.w + } +} +#[doc = "Field `LDRFRAC` reader - Loop Divider Ratio Fractional Part"] +pub struct LDRFRAC_R(crate::FieldReader); +impl LDRFRAC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LDRFRAC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LDRFRAC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LDRFRAC` writer - Loop Divider Ratio Fractional Part"] +pub struct LDRFRAC_W<'a> { + w: &'a mut W, +} +impl<'a> LDRFRAC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 16)) | ((value as u32 & 0x0f) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:11 - Loop Divider Ratio"] + #[inline(always)] + pub fn ldr(&self) -> LDR_R { + LDR_R::new((self.bits & 0x0fff) as u16) + } + #[doc = "Bits 16:19 - Loop Divider Ratio Fractional Part"] + #[inline(always)] + pub fn ldrfrac(&self) -> LDRFRAC_R { + LDRFRAC_R::new(((self.bits >> 16) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:11 - Loop Divider Ratio"] + #[inline(always)] + pub fn ldr(&mut self) -> LDR_W { + LDR_W { w: self } + } + #[doc = "Bits 16:19 - Loop Divider Ratio Fractional Part"] + #[inline(always)] + pub fn ldrfrac(&mut self) -> LDRFRAC_W { + LDRFRAC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DPLL Ratio Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dpllratio](index.html) module"] +pub struct DPLLRATIO_SPEC; +impl crate::RegisterSpec for DPLLRATIO_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dpllratio::R](R) reader structure"] +impl crate::Readable for DPLLRATIO_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dpllratio::W](W) writer structure"] +impl crate::Writable for DPLLRATIO_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DPLLRATIO to value 0"] +impl crate::Resettable for DPLLRATIO_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/oscctrl/dpllstatus.rs b/pac/atsamc21n/src/oscctrl/dpllstatus.rs new file mode 100644 index 000000000000..931900212816 --- /dev/null +++ b/pac/atsamc21n/src/oscctrl/dpllstatus.rs @@ -0,0 +1,73 @@ +#[doc = "Register `DPLLSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `LOCK` reader - DPLL Lock Status"] +pub struct LOCK_R(crate::FieldReader); +impl LOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKRDY` reader - DPLL Clock Ready"] +pub struct CLKRDY_R(crate::FieldReader); +impl CLKRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - DPLL Lock Status"] + #[inline(always)] + pub fn lock(&self) -> LOCK_R { + LOCK_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - DPLL Clock Ready"] + #[inline(always)] + pub fn clkrdy(&self) -> CLKRDY_R { + CLKRDY_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +#[doc = "DPLL Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dpllstatus](index.html) module"] +pub struct DPLLSTATUS_SPEC; +impl crate::RegisterSpec for DPLLSTATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dpllstatus::R](R) reader structure"] +impl crate::Readable for DPLLSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DPLLSTATUS to value 0"] +impl crate::Resettable for DPLLSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/oscctrl/dpllsyncbusy.rs b/pac/atsamc21n/src/oscctrl/dpllsyncbusy.rs new file mode 100644 index 000000000000..f9fb880a5a59 --- /dev/null +++ b/pac/atsamc21n/src/oscctrl/dpllsyncbusy.rs @@ -0,0 +1,93 @@ +#[doc = "Register `DPLLSYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `ENABLE` reader - DPLL Enable Synchronization Status"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLRATIO` reader - DPLL Ratio Synchronization Status"] +pub struct DPLLRATIO_R(crate::FieldReader); +impl DPLLRATIO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLRATIO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLRATIO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLPRESC` reader - DPLL Prescaler Synchronization Status"] +pub struct DPLLPRESC_R(crate::FieldReader); +impl DPLLPRESC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLPRESC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLPRESC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 1 - DPLL Enable Synchronization Status"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - DPLL Ratio Synchronization Status"] + #[inline(always)] + pub fn dpllratio(&self) -> DPLLRATIO_R { + DPLLRATIO_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - DPLL Prescaler Synchronization Status"] + #[inline(always)] + pub fn dpllpresc(&self) -> DPLLPRESC_R { + DPLLPRESC_R::new(((self.bits >> 3) & 0x01) != 0) + } +} +#[doc = "DPLL Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dpllsyncbusy](index.html) module"] +pub struct DPLLSYNCBUSY_SPEC; +impl crate::RegisterSpec for DPLLSYNCBUSY_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dpllsyncbusy::R](R) reader structure"] +impl crate::Readable for DPLLSYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DPLLSYNCBUSY to value 0"] +impl crate::Resettable for DPLLSYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/oscctrl/evctrl.rs b/pac/atsamc21n/src/oscctrl/evctrl.rs new file mode 100644 index 000000000000..e22ba62f0fe2 --- /dev/null +++ b/pac/atsamc21n/src/oscctrl/evctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CFDEO` reader - Clock Failure Detector Event Output Enable"] +pub struct CFDEO_R(crate::FieldReader); +impl CFDEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFDEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFDEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFDEO` writer - Clock Failure Detector Event Output Enable"] +pub struct CFDEO_W<'a> { + w: &'a mut W, +} +impl<'a> CFDEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Clock Failure Detector Event Output Enable"] + #[inline(always)] + pub fn cfdeo(&self) -> CFDEO_R { + CFDEO_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Clock Failure Detector Event Output Enable"] + #[inline(always)] + pub fn cfdeo(&mut self) -> CFDEO_W { + CFDEO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/oscctrl/intenclr.rs b/pac/atsamc21n/src/oscctrl/intenclr.rs new file mode 100644 index 000000000000..0ea0034a0c02 --- /dev/null +++ b/pac/atsamc21n/src/oscctrl/intenclr.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XOSCRDY` reader - XOSC Ready Interrupt Enable"] +pub struct XOSCRDY_R(crate::FieldReader); +impl XOSCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSCRDY` writer - XOSC Ready Interrupt Enable"] +pub struct XOSCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> XOSCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `XOSCFAIL` reader - XOSC Clock Failure Detector Interrupt Enable"] +pub struct XOSCFAIL_R(crate::FieldReader); +impl XOSCFAIL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSCFAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCFAIL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSCFAIL` writer - XOSC Clock Failure Detector Interrupt Enable"] +pub struct XOSCFAIL_W<'a> { + w: &'a mut W, +} +impl<'a> XOSCFAIL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `OSC48MRDY` reader - OSC48M Ready Interrupt Enable"] +pub struct OSC48MRDY_R(crate::FieldReader); +impl OSC48MRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC48MRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC48MRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC48MRDY` writer - OSC48M Ready Interrupt Enable"] +pub struct OSC48MRDY_W<'a> { + w: &'a mut W, +} +impl<'a> OSC48MRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `DPLLLCKR` reader - DPLL Lock Rise Interrupt Enable"] +pub struct DPLLLCKR_R(crate::FieldReader); +impl DPLLLCKR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKR` writer - DPLL Lock Rise Interrupt Enable"] +pub struct DPLLLCKR_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLCKR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `DPLLLCKF` reader - DPLL Lock Fall Interrupt Enable"] +pub struct DPLLLCKF_R(crate::FieldReader); +impl DPLLLCKF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKF` writer - DPLL Lock Fall Interrupt Enable"] +pub struct DPLLLCKF_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLCKF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `DPLLLTO` reader - DPLL Time Out Interrupt Enable"] +pub struct DPLLLTO_R(crate::FieldReader); +impl DPLLLTO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLTO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLTO` writer - DPLL Time Out Interrupt Enable"] +pub struct DPLLLTO_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLTO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `DPLLLDRTO` reader - DPLL Ratio Ready Interrupt Enable"] +pub struct DPLLLDRTO_R(crate::FieldReader); +impl DPLLLDRTO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLDRTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLDRTO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLDRTO` writer - DPLL Ratio Ready Interrupt Enable"] +pub struct DPLLLDRTO_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLDRTO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +impl R { + #[doc = "Bit 0 - XOSC Ready Interrupt Enable"] + #[inline(always)] + pub fn xoscrdy(&self) -> XOSCRDY_R { + XOSCRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - XOSC Clock Failure Detector Interrupt Enable"] + #[inline(always)] + pub fn xoscfail(&self) -> XOSCFAIL_R { + XOSCFAIL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - OSC48M Ready Interrupt Enable"] + #[inline(always)] + pub fn osc48mrdy(&self) -> OSC48MRDY_R { + OSC48MRDY_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 8 - DPLL Lock Rise Interrupt Enable"] + #[inline(always)] + pub fn dplllckr(&self) -> DPLLLCKR_R { + DPLLLCKR_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - DPLL Lock Fall Interrupt Enable"] + #[inline(always)] + pub fn dplllckf(&self) -> DPLLLCKF_R { + DPLLLCKF_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - DPLL Time Out Interrupt Enable"] + #[inline(always)] + pub fn dplllto(&self) -> DPLLLTO_R { + DPLLLTO_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - DPLL Ratio Ready Interrupt Enable"] + #[inline(always)] + pub fn dpllldrto(&self) -> DPLLLDRTO_R { + DPLLLDRTO_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - XOSC Ready Interrupt Enable"] + #[inline(always)] + pub fn xoscrdy(&mut self) -> XOSCRDY_W { + XOSCRDY_W { w: self } + } + #[doc = "Bit 1 - XOSC Clock Failure Detector Interrupt Enable"] + #[inline(always)] + pub fn xoscfail(&mut self) -> XOSCFAIL_W { + XOSCFAIL_W { w: self } + } + #[doc = "Bit 4 - OSC48M Ready Interrupt Enable"] + #[inline(always)] + pub fn osc48mrdy(&mut self) -> OSC48MRDY_W { + OSC48MRDY_W { w: self } + } + #[doc = "Bit 8 - DPLL Lock Rise Interrupt Enable"] + #[inline(always)] + pub fn dplllckr(&mut self) -> DPLLLCKR_W { + DPLLLCKR_W { w: self } + } + #[doc = "Bit 9 - DPLL Lock Fall Interrupt Enable"] + #[inline(always)] + pub fn dplllckf(&mut self) -> DPLLLCKF_W { + DPLLLCKF_W { w: self } + } + #[doc = "Bit 10 - DPLL Time Out Interrupt Enable"] + #[inline(always)] + pub fn dplllto(&mut self) -> DPLLLTO_W { + DPLLLTO_W { w: self } + } + #[doc = "Bit 11 - DPLL Ratio Ready Interrupt Enable"] + #[inline(always)] + pub fn dpllldrto(&mut self) -> DPLLLDRTO_W { + DPLLLDRTO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/oscctrl/intenset.rs b/pac/atsamc21n/src/oscctrl/intenset.rs new file mode 100644 index 000000000000..2890541e4414 --- /dev/null +++ b/pac/atsamc21n/src/oscctrl/intenset.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XOSCRDY` reader - XOSC Ready Interrupt Enable"] +pub struct XOSCRDY_R(crate::FieldReader); +impl XOSCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSCRDY` writer - XOSC Ready Interrupt Enable"] +pub struct XOSCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> XOSCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `XOSCFAIL` reader - XOSC Clock Failure Detector Interrupt Enable"] +pub struct XOSCFAIL_R(crate::FieldReader); +impl XOSCFAIL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSCFAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCFAIL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSCFAIL` writer - XOSC Clock Failure Detector Interrupt Enable"] +pub struct XOSCFAIL_W<'a> { + w: &'a mut W, +} +impl<'a> XOSCFAIL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `OSC48MRDY` reader - OSC48M Ready Interrupt Enable"] +pub struct OSC48MRDY_R(crate::FieldReader); +impl OSC48MRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC48MRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC48MRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC48MRDY` writer - OSC48M Ready Interrupt Enable"] +pub struct OSC48MRDY_W<'a> { + w: &'a mut W, +} +impl<'a> OSC48MRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `DPLLLCKR` reader - DPLL Lock Rise Interrupt Enable"] +pub struct DPLLLCKR_R(crate::FieldReader); +impl DPLLLCKR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKR` writer - DPLL Lock Rise Interrupt Enable"] +pub struct DPLLLCKR_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLCKR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `DPLLLCKF` reader - DPLL Lock Fall Interrupt Enable"] +pub struct DPLLLCKF_R(crate::FieldReader); +impl DPLLLCKF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKF` writer - DPLL Lock Fall Interrupt Enable"] +pub struct DPLLLCKF_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLCKF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `DPLLLTO` reader - DPLL Time Out Interrupt Enable"] +pub struct DPLLLTO_R(crate::FieldReader); +impl DPLLLTO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLTO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLTO` writer - DPLL Time Out Interrupt Enable"] +pub struct DPLLLTO_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLTO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `DPLLLDRTO` reader - DPLL Ratio Ready Interrupt Enable"] +pub struct DPLLLDRTO_R(crate::FieldReader); +impl DPLLLDRTO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLDRTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLDRTO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLDRTO` writer - DPLL Ratio Ready Interrupt Enable"] +pub struct DPLLLDRTO_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLDRTO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +impl R { + #[doc = "Bit 0 - XOSC Ready Interrupt Enable"] + #[inline(always)] + pub fn xoscrdy(&self) -> XOSCRDY_R { + XOSCRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - XOSC Clock Failure Detector Interrupt Enable"] + #[inline(always)] + pub fn xoscfail(&self) -> XOSCFAIL_R { + XOSCFAIL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - OSC48M Ready Interrupt Enable"] + #[inline(always)] + pub fn osc48mrdy(&self) -> OSC48MRDY_R { + OSC48MRDY_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 8 - DPLL Lock Rise Interrupt Enable"] + #[inline(always)] + pub fn dplllckr(&self) -> DPLLLCKR_R { + DPLLLCKR_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - DPLL Lock Fall Interrupt Enable"] + #[inline(always)] + pub fn dplllckf(&self) -> DPLLLCKF_R { + DPLLLCKF_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - DPLL Time Out Interrupt Enable"] + #[inline(always)] + pub fn dplllto(&self) -> DPLLLTO_R { + DPLLLTO_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - DPLL Ratio Ready Interrupt Enable"] + #[inline(always)] + pub fn dpllldrto(&self) -> DPLLLDRTO_R { + DPLLLDRTO_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - XOSC Ready Interrupt Enable"] + #[inline(always)] + pub fn xoscrdy(&mut self) -> XOSCRDY_W { + XOSCRDY_W { w: self } + } + #[doc = "Bit 1 - XOSC Clock Failure Detector Interrupt Enable"] + #[inline(always)] + pub fn xoscfail(&mut self) -> XOSCFAIL_W { + XOSCFAIL_W { w: self } + } + #[doc = "Bit 4 - OSC48M Ready Interrupt Enable"] + #[inline(always)] + pub fn osc48mrdy(&mut self) -> OSC48MRDY_W { + OSC48MRDY_W { w: self } + } + #[doc = "Bit 8 - DPLL Lock Rise Interrupt Enable"] + #[inline(always)] + pub fn dplllckr(&mut self) -> DPLLLCKR_W { + DPLLLCKR_W { w: self } + } + #[doc = "Bit 9 - DPLL Lock Fall Interrupt Enable"] + #[inline(always)] + pub fn dplllckf(&mut self) -> DPLLLCKF_W { + DPLLLCKF_W { w: self } + } + #[doc = "Bit 10 - DPLL Time Out Interrupt Enable"] + #[inline(always)] + pub fn dplllto(&mut self) -> DPLLLTO_W { + DPLLLTO_W { w: self } + } + #[doc = "Bit 11 - DPLL Ratio Ready Interrupt Enable"] + #[inline(always)] + pub fn dpllldrto(&mut self) -> DPLLLDRTO_W { + DPLLLDRTO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/oscctrl/intflag.rs b/pac/atsamc21n/src/oscctrl/intflag.rs new file mode 100644 index 000000000000..71e452a1b571 --- /dev/null +++ b/pac/atsamc21n/src/oscctrl/intflag.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XOSCRDY` reader - XOSC Ready"] +pub struct XOSCRDY_R(crate::FieldReader); +impl XOSCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSCRDY` writer - XOSC Ready"] +pub struct XOSCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> XOSCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `XOSCFAIL` reader - XOSC Clock Failure Detector"] +pub struct XOSCFAIL_R(crate::FieldReader); +impl XOSCFAIL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSCFAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCFAIL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSCFAIL` writer - XOSC Clock Failure Detector"] +pub struct XOSCFAIL_W<'a> { + w: &'a mut W, +} +impl<'a> XOSCFAIL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `OSC48MRDY` reader - OSC48M Ready"] +pub struct OSC48MRDY_R(crate::FieldReader); +impl OSC48MRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC48MRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC48MRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC48MRDY` writer - OSC48M Ready"] +pub struct OSC48MRDY_W<'a> { + w: &'a mut W, +} +impl<'a> OSC48MRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `DPLLLCKR` reader - DPLL Lock Rise"] +pub struct DPLLLCKR_R(crate::FieldReader); +impl DPLLLCKR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKR` writer - DPLL Lock Rise"] +pub struct DPLLLCKR_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLCKR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `DPLLLCKF` reader - DPLL Lock Fall"] +pub struct DPLLLCKF_R(crate::FieldReader); +impl DPLLLCKF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKF` writer - DPLL Lock Fall"] +pub struct DPLLLCKF_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLCKF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `DPLLLTO` reader - DPLL Timeout"] +pub struct DPLLLTO_R(crate::FieldReader); +impl DPLLLTO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLTO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLTO` writer - DPLL Timeout"] +pub struct DPLLLTO_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLTO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `DPLLLDRTO` reader - DPLL Ratio Ready"] +pub struct DPLLLDRTO_R(crate::FieldReader); +impl DPLLLDRTO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLDRTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLDRTO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLDRTO` writer - DPLL Ratio Ready"] +pub struct DPLLLDRTO_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLDRTO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +impl R { + #[doc = "Bit 0 - XOSC Ready"] + #[inline(always)] + pub fn xoscrdy(&self) -> XOSCRDY_R { + XOSCRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - XOSC Clock Failure Detector"] + #[inline(always)] + pub fn xoscfail(&self) -> XOSCFAIL_R { + XOSCFAIL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - OSC48M Ready"] + #[inline(always)] + pub fn osc48mrdy(&self) -> OSC48MRDY_R { + OSC48MRDY_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 8 - DPLL Lock Rise"] + #[inline(always)] + pub fn dplllckr(&self) -> DPLLLCKR_R { + DPLLLCKR_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - DPLL Lock Fall"] + #[inline(always)] + pub fn dplllckf(&self) -> DPLLLCKF_R { + DPLLLCKF_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - DPLL Timeout"] + #[inline(always)] + pub fn dplllto(&self) -> DPLLLTO_R { + DPLLLTO_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - DPLL Ratio Ready"] + #[inline(always)] + pub fn dpllldrto(&self) -> DPLLLDRTO_R { + DPLLLDRTO_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - XOSC Ready"] + #[inline(always)] + pub fn xoscrdy(&mut self) -> XOSCRDY_W { + XOSCRDY_W { w: self } + } + #[doc = "Bit 1 - XOSC Clock Failure Detector"] + #[inline(always)] + pub fn xoscfail(&mut self) -> XOSCFAIL_W { + XOSCFAIL_W { w: self } + } + #[doc = "Bit 4 - OSC48M Ready"] + #[inline(always)] + pub fn osc48mrdy(&mut self) -> OSC48MRDY_W { + OSC48MRDY_W { w: self } + } + #[doc = "Bit 8 - DPLL Lock Rise"] + #[inline(always)] + pub fn dplllckr(&mut self) -> DPLLLCKR_W { + DPLLLCKR_W { w: self } + } + #[doc = "Bit 9 - DPLL Lock Fall"] + #[inline(always)] + pub fn dplllckf(&mut self) -> DPLLLCKF_W { + DPLLLCKF_W { w: self } + } + #[doc = "Bit 10 - DPLL Timeout"] + #[inline(always)] + pub fn dplllto(&mut self) -> DPLLLTO_W { + DPLLLTO_W { w: self } + } + #[doc = "Bit 11 - DPLL Ratio Ready"] + #[inline(always)] + pub fn dpllldrto(&mut self) -> DPLLLDRTO_W { + DPLLLDRTO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/oscctrl/osc48mctrl.rs b/pac/atsamc21n/src/oscctrl/osc48mctrl.rs new file mode 100644 index 000000000000..8314e21e5775 --- /dev/null +++ b/pac/atsamc21n/src/oscctrl/osc48mctrl.rs @@ -0,0 +1,207 @@ +#[doc = "Register `OSC48MCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OSC48MCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Oscillator Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Oscillator Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - On Demand Control"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - On Demand Control"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "48MHz Internal Oscillator (OSC48M) Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [osc48mctrl](index.html) module"] +pub struct OSC48MCTRL_SPEC; +impl crate::RegisterSpec for OSC48MCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [osc48mctrl::R](R) reader structure"] +impl crate::Readable for OSC48MCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [osc48mctrl::W](W) writer structure"] +impl crate::Writable for OSC48MCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OSC48MCTRL to value 0x82"] +impl crate::Resettable for OSC48MCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x82 + } +} diff --git a/pac/atsamc21n/src/oscctrl/osc48mdiv.rs b/pac/atsamc21n/src/oscctrl/osc48mdiv.rs new file mode 100644 index 000000000000..4ed854b09284 --- /dev/null +++ b/pac/atsamc21n/src/oscctrl/osc48mdiv.rs @@ -0,0 +1,334 @@ +#[doc = "Register `OSC48MDIV` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OSC48MDIV` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "OSC48M Division Factor\n\nValue on reset: 11"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DIV_A { + #[doc = "0: 48 MHz"] + DIV1 = 0, + #[doc = "1: 24 MHz"] + DIV2 = 1, + #[doc = "2: 16 MHz"] + DIV3 = 2, + #[doc = "3: 12 MHz"] + DIV4 = 3, + #[doc = "4: 9.6 MHz"] + DIV5 = 4, + #[doc = "5: 8 MHz"] + DIV6 = 5, + #[doc = "6: 6.86 MHz"] + DIV7 = 6, + #[doc = "7: 6 MHz"] + DIV8 = 7, + #[doc = "8: 5.33 MHz"] + DIV9 = 8, + #[doc = "9: 4.8 MHz"] + DIV10 = 9, + #[doc = "10: 4.36 MHz"] + DIV11 = 10, + #[doc = "11: 4 MHz"] + DIV12 = 11, + #[doc = "12: 3.69 MHz"] + DIV13 = 12, + #[doc = "13: 3.43 MHz"] + DIV14 = 13, + #[doc = "14: 3.2 MHz"] + DIV15 = 14, + #[doc = "15: 3 MHz"] + DIV16 = 15, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DIV_A) -> Self { + variant as _ + } +} +#[doc = "Field `DIV` reader - OSC48M Division Factor"] +pub struct DIV_R(crate::FieldReader); +impl DIV_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DIV_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DIV_A { + match self.bits { + 0 => DIV_A::DIV1, + 1 => DIV_A::DIV2, + 2 => DIV_A::DIV3, + 3 => DIV_A::DIV4, + 4 => DIV_A::DIV5, + 5 => DIV_A::DIV6, + 6 => DIV_A::DIV7, + 7 => DIV_A::DIV8, + 8 => DIV_A::DIV9, + 9 => DIV_A::DIV10, + 10 => DIV_A::DIV11, + 11 => DIV_A::DIV12, + 12 => DIV_A::DIV13, + 13 => DIV_A::DIV14, + 14 => DIV_A::DIV15, + 15 => DIV_A::DIV16, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == DIV_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == DIV_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV3`"] + #[inline(always)] + pub fn is_div3(&self) -> bool { + **self == DIV_A::DIV3 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == DIV_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV5`"] + #[inline(always)] + pub fn is_div5(&self) -> bool { + **self == DIV_A::DIV5 + } + #[doc = "Checks if the value of the field is `DIV6`"] + #[inline(always)] + pub fn is_div6(&self) -> bool { + **self == DIV_A::DIV6 + } + #[doc = "Checks if the value of the field is `DIV7`"] + #[inline(always)] + pub fn is_div7(&self) -> bool { + **self == DIV_A::DIV7 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == DIV_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV9`"] + #[inline(always)] + pub fn is_div9(&self) -> bool { + **self == DIV_A::DIV9 + } + #[doc = "Checks if the value of the field is `DIV10`"] + #[inline(always)] + pub fn is_div10(&self) -> bool { + **self == DIV_A::DIV10 + } + #[doc = "Checks if the value of the field is `DIV11`"] + #[inline(always)] + pub fn is_div11(&self) -> bool { + **self == DIV_A::DIV11 + } + #[doc = "Checks if the value of the field is `DIV12`"] + #[inline(always)] + pub fn is_div12(&self) -> bool { + **self == DIV_A::DIV12 + } + #[doc = "Checks if the value of the field is `DIV13`"] + #[inline(always)] + pub fn is_div13(&self) -> bool { + **self == DIV_A::DIV13 + } + #[doc = "Checks if the value of the field is `DIV14`"] + #[inline(always)] + pub fn is_div14(&self) -> bool { + **self == DIV_A::DIV14 + } + #[doc = "Checks if the value of the field is `DIV15`"] + #[inline(always)] + pub fn is_div15(&self) -> bool { + **self == DIV_A::DIV15 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == DIV_A::DIV16 + } +} +impl core::ops::Deref for DIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIV` writer - OSC48M Division Factor"] +pub struct DIV_W<'a> { + w: &'a mut W, +} +impl<'a> DIV_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DIV_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "48 MHz"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(DIV_A::DIV1) + } + #[doc = "24 MHz"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(DIV_A::DIV2) + } + #[doc = "16 MHz"] + #[inline(always)] + pub fn div3(self) -> &'a mut W { + self.variant(DIV_A::DIV3) + } + #[doc = "12 MHz"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(DIV_A::DIV4) + } + #[doc = "9.6 MHz"] + #[inline(always)] + pub fn div5(self) -> &'a mut W { + self.variant(DIV_A::DIV5) + } + #[doc = "8 MHz"] + #[inline(always)] + pub fn div6(self) -> &'a mut W { + self.variant(DIV_A::DIV6) + } + #[doc = "6.86 MHz"] + #[inline(always)] + pub fn div7(self) -> &'a mut W { + self.variant(DIV_A::DIV7) + } + #[doc = "6 MHz"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(DIV_A::DIV8) + } + #[doc = "5.33 MHz"] + #[inline(always)] + pub fn div9(self) -> &'a mut W { + self.variant(DIV_A::DIV9) + } + #[doc = "4.8 MHz"] + #[inline(always)] + pub fn div10(self) -> &'a mut W { + self.variant(DIV_A::DIV10) + } + #[doc = "4.36 MHz"] + #[inline(always)] + pub fn div11(self) -> &'a mut W { + self.variant(DIV_A::DIV11) + } + #[doc = "4 MHz"] + #[inline(always)] + pub fn div12(self) -> &'a mut W { + self.variant(DIV_A::DIV12) + } + #[doc = "3.69 MHz"] + #[inline(always)] + pub fn div13(self) -> &'a mut W { + self.variant(DIV_A::DIV13) + } + #[doc = "3.43 MHz"] + #[inline(always)] + pub fn div14(self) -> &'a mut W { + self.variant(DIV_A::DIV14) + } + #[doc = "3.2 MHz"] + #[inline(always)] + pub fn div15(self) -> &'a mut W { + self.variant(DIV_A::DIV15) + } + #[doc = "3 MHz"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(DIV_A::DIV16) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - OSC48M Division Factor"] + #[inline(always)] + pub fn div(&self) -> DIV_R { + DIV_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - OSC48M Division Factor"] + #[inline(always)] + pub fn div(&mut self) -> DIV_W { + DIV_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OSC48M Divider\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [osc48mdiv](index.html) module"] +pub struct OSC48MDIV_SPEC; +impl crate::RegisterSpec for OSC48MDIV_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [osc48mdiv::R](R) reader structure"] +impl crate::Readable for OSC48MDIV_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [osc48mdiv::W](W) writer structure"] +impl crate::Writable for OSC48MDIV_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OSC48MDIV to value 0x0b"] +impl crate::Resettable for OSC48MDIV_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0b + } +} diff --git a/pac/atsamc21n/src/oscctrl/osc48mstup.rs b/pac/atsamc21n/src/oscctrl/osc48mstup.rs new file mode 100644 index 000000000000..34da6bb7ef11 --- /dev/null +++ b/pac/atsamc21n/src/oscctrl/osc48mstup.rs @@ -0,0 +1,230 @@ +#[doc = "Register `OSC48MSTUP` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OSC48MSTUP` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Startup Time\n\nValue on reset: 7"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum STARTUP_A { + #[doc = "0: 166 ns"] + CYCLE8 = 0, + #[doc = "1: 333 ns"] + CYCLE16 = 1, + #[doc = "2: 667 ns"] + CYCLE32 = 2, + #[doc = "3: 1.333 us"] + CYCLE64 = 3, + #[doc = "4: 2.667 us"] + CYCLE128 = 4, + #[doc = "5: 5.333 us"] + CYCLE256 = 5, + #[doc = "6: 10.667 us"] + CYCLE512 = 6, + #[doc = "7: 21.333 us"] + CYCLE1024 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: STARTUP_A) -> Self { + variant as _ + } +} +#[doc = "Field `STARTUP` reader - Startup Time"] +pub struct STARTUP_R(crate::FieldReader); +impl STARTUP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + STARTUP_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STARTUP_A { + match self.bits { + 0 => STARTUP_A::CYCLE8, + 1 => STARTUP_A::CYCLE16, + 2 => STARTUP_A::CYCLE32, + 3 => STARTUP_A::CYCLE64, + 4 => STARTUP_A::CYCLE128, + 5 => STARTUP_A::CYCLE256, + 6 => STARTUP_A::CYCLE512, + 7 => STARTUP_A::CYCLE1024, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `CYCLE8`"] + #[inline(always)] + pub fn is_cycle8(&self) -> bool { + **self == STARTUP_A::CYCLE8 + } + #[doc = "Checks if the value of the field is `CYCLE16`"] + #[inline(always)] + pub fn is_cycle16(&self) -> bool { + **self == STARTUP_A::CYCLE16 + } + #[doc = "Checks if the value of the field is `CYCLE32`"] + #[inline(always)] + pub fn is_cycle32(&self) -> bool { + **self == STARTUP_A::CYCLE32 + } + #[doc = "Checks if the value of the field is `CYCLE64`"] + #[inline(always)] + pub fn is_cycle64(&self) -> bool { + **self == STARTUP_A::CYCLE64 + } + #[doc = "Checks if the value of the field is `CYCLE128`"] + #[inline(always)] + pub fn is_cycle128(&self) -> bool { + **self == STARTUP_A::CYCLE128 + } + #[doc = "Checks if the value of the field is `CYCLE256`"] + #[inline(always)] + pub fn is_cycle256(&self) -> bool { + **self == STARTUP_A::CYCLE256 + } + #[doc = "Checks if the value of the field is `CYCLE512`"] + #[inline(always)] + pub fn is_cycle512(&self) -> bool { + **self == STARTUP_A::CYCLE512 + } + #[doc = "Checks if the value of the field is `CYCLE1024`"] + #[inline(always)] + pub fn is_cycle1024(&self) -> bool { + **self == STARTUP_A::CYCLE1024 + } +} +impl core::ops::Deref for STARTUP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STARTUP` writer - Startup Time"] +pub struct STARTUP_W<'a> { + w: &'a mut W, +} +impl<'a> STARTUP_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: STARTUP_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "166 ns"] + #[inline(always)] + pub fn cycle8(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE8) + } + #[doc = "333 ns"] + #[inline(always)] + pub fn cycle16(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE16) + } + #[doc = "667 ns"] + #[inline(always)] + pub fn cycle32(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE32) + } + #[doc = "1.333 us"] + #[inline(always)] + pub fn cycle64(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE64) + } + #[doc = "2.667 us"] + #[inline(always)] + pub fn cycle128(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE128) + } + #[doc = "5.333 us"] + #[inline(always)] + pub fn cycle256(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE256) + } + #[doc = "10.667 us"] + #[inline(always)] + pub fn cycle512(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE512) + } + #[doc = "21.333 us"] + #[inline(always)] + pub fn cycle1024(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Startup Time"] + #[inline(always)] + pub fn startup(&self) -> STARTUP_R { + STARTUP_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Startup Time"] + #[inline(always)] + pub fn startup(&mut self) -> STARTUP_W { + STARTUP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OSC48M Startup Time\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [osc48mstup](index.html) module"] +pub struct OSC48MSTUP_SPEC; +impl crate::RegisterSpec for OSC48MSTUP_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [osc48mstup::R](R) reader structure"] +impl crate::Readable for OSC48MSTUP_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [osc48mstup::W](W) writer structure"] +impl crate::Writable for OSC48MSTUP_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OSC48MSTUP to value 0x07"] +impl crate::Resettable for OSC48MSTUP_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x07 + } +} diff --git a/pac/atsamc21n/src/oscctrl/osc48msyncbusy.rs b/pac/atsamc21n/src/oscctrl/osc48msyncbusy.rs new file mode 100644 index 000000000000..8d4410ae630a --- /dev/null +++ b/pac/atsamc21n/src/oscctrl/osc48msyncbusy.rs @@ -0,0 +1,53 @@ +#[doc = "Register `OSC48MSYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `OSC48MDIV` reader - OSC48MDIV Synchronization Status"] +pub struct OSC48MDIV_R(crate::FieldReader); +impl OSC48MDIV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC48MDIV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC48MDIV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 2 - OSC48MDIV Synchronization Status"] + #[inline(always)] + pub fn osc48mdiv(&self) -> OSC48MDIV_R { + OSC48MDIV_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +#[doc = "OSC48M Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [osc48msyncbusy](index.html) module"] +pub struct OSC48MSYNCBUSY_SPEC; +impl crate::RegisterSpec for OSC48MSYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [osc48msyncbusy::R](R) reader structure"] +impl crate::Readable for OSC48MSYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets OSC48MSYNCBUSY to value 0"] +impl crate::Resettable for OSC48MSYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/oscctrl/status.rs b/pac/atsamc21n/src/oscctrl/status.rs new file mode 100644 index 000000000000..3025966192a3 --- /dev/null +++ b/pac/atsamc21n/src/oscctrl/status.rs @@ -0,0 +1,193 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `XOSCRDY` reader - XOSC Ready"] +pub struct XOSCRDY_R(crate::FieldReader); +impl XOSCRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSCFAIL` reader - XOSC Clock Failure Detector"] +pub struct XOSCFAIL_R(crate::FieldReader); +impl XOSCFAIL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSCFAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCFAIL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSCCKSW` reader - XOSC Clock Switch"] +pub struct XOSCCKSW_R(crate::FieldReader); +impl XOSCCKSW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XOSCCKSW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCCKSW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC48MRDY` reader - OSC48M Ready"] +pub struct OSC48MRDY_R(crate::FieldReader); +impl OSC48MRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC48MRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC48MRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKR` reader - DPLL Lock Rise"] +pub struct DPLLLCKR_R(crate::FieldReader); +impl DPLLLCKR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKF` reader - DPLL Lock Fall"] +pub struct DPLLLCKF_R(crate::FieldReader); +impl DPLLLCKF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLTO` reader - DPLL Timeout"] +pub struct DPLLTO_R(crate::FieldReader); +impl DPLLTO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLTO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLDRTO` reader - DPLL Ratio Ready"] +pub struct DPLLLDRTO_R(crate::FieldReader); +impl DPLLLDRTO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DPLLLDRTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLDRTO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - XOSC Ready"] + #[inline(always)] + pub fn xoscrdy(&self) -> XOSCRDY_R { + XOSCRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - XOSC Clock Failure Detector"] + #[inline(always)] + pub fn xoscfail(&self) -> XOSCFAIL_R { + XOSCFAIL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - XOSC Clock Switch"] + #[inline(always)] + pub fn xosccksw(&self) -> XOSCCKSW_R { + XOSCCKSW_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 4 - OSC48M Ready"] + #[inline(always)] + pub fn osc48mrdy(&self) -> OSC48MRDY_R { + OSC48MRDY_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 8 - DPLL Lock Rise"] + #[inline(always)] + pub fn dplllckr(&self) -> DPLLLCKR_R { + DPLLLCKR_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - DPLL Lock Fall"] + #[inline(always)] + pub fn dplllckf(&self) -> DPLLLCKF_R { + DPLLLCKF_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - DPLL Timeout"] + #[inline(always)] + pub fn dpllto(&self) -> DPLLTO_R { + DPLLTO_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - DPLL Ratio Ready"] + #[inline(always)] + pub fn dpllldrto(&self) -> DPLLLDRTO_R { + DPLLLDRTO_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +#[doc = "Power and Clocks Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/oscctrl/xoscctrl.rs b/pac/atsamc21n/src/oscctrl/xoscctrl.rs new file mode 100644 index 000000000000..3a5319565c10 --- /dev/null +++ b/pac/atsamc21n/src/oscctrl/xoscctrl.rs @@ -0,0 +1,788 @@ +#[doc = "Register `XOSCCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `XOSCCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Oscillator Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Oscillator Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `XTALEN` reader - Crystal Oscillator Enable"] +pub struct XTALEN_R(crate::FieldReader); +impl XTALEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XTALEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XTALEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XTALEN` writer - Crystal Oscillator Enable"] +pub struct XTALEN_W<'a> { + w: &'a mut W, +} +impl<'a> XTALEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CFDEN` reader - Xosc Clock Failure Detector Enable"] +pub struct CFDEN_R(crate::FieldReader); +impl CFDEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFDEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFDEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFDEN` writer - Xosc Clock Failure Detector Enable"] +pub struct CFDEN_W<'a> { + w: &'a mut W, +} +impl<'a> CFDEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `SWBEN` reader - Xosc Clock Switch Enable"] +pub struct SWBEN_R(crate::FieldReader); +impl SWBEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWBEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWBEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWBEN` writer - Xosc Clock Switch Enable"] +pub struct SWBEN_W<'a> { + w: &'a mut W, +} +impl<'a> SWBEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - On Demand Control"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - On Demand Control"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Oscillator Gain\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum GAIN_A { + #[doc = "0: 2 MHz"] + GAIN2 = 0, + #[doc = "1: 4 MHz"] + GAIN4 = 1, + #[doc = "2: 8 MHz"] + GAIN8 = 2, + #[doc = "3: 16 MHz"] + GAIN16 = 3, + #[doc = "4: 30 MHz"] + GAIN30 = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: GAIN_A) -> Self { + variant as _ + } +} +#[doc = "Field `GAIN` reader - Oscillator Gain"] +pub struct GAIN_R(crate::FieldReader); +impl GAIN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + GAIN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(GAIN_A::GAIN2), + 1 => Some(GAIN_A::GAIN4), + 2 => Some(GAIN_A::GAIN8), + 3 => Some(GAIN_A::GAIN16), + 4 => Some(GAIN_A::GAIN30), + _ => None, + } + } + #[doc = "Checks if the value of the field is `GAIN2`"] + #[inline(always)] + pub fn is_gain2(&self) -> bool { + **self == GAIN_A::GAIN2 + } + #[doc = "Checks if the value of the field is `GAIN4`"] + #[inline(always)] + pub fn is_gain4(&self) -> bool { + **self == GAIN_A::GAIN4 + } + #[doc = "Checks if the value of the field is `GAIN8`"] + #[inline(always)] + pub fn is_gain8(&self) -> bool { + **self == GAIN_A::GAIN8 + } + #[doc = "Checks if the value of the field is `GAIN16`"] + #[inline(always)] + pub fn is_gain16(&self) -> bool { + **self == GAIN_A::GAIN16 + } + #[doc = "Checks if the value of the field is `GAIN30`"] + #[inline(always)] + pub fn is_gain30(&self) -> bool { + **self == GAIN_A::GAIN30 + } +} +impl core::ops::Deref for GAIN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GAIN` writer - Oscillator Gain"] +pub struct GAIN_W<'a> { + w: &'a mut W, +} +impl<'a> GAIN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: GAIN_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "2 MHz"] + #[inline(always)] + pub fn gain2(self) -> &'a mut W { + self.variant(GAIN_A::GAIN2) + } + #[doc = "4 MHz"] + #[inline(always)] + pub fn gain4(self) -> &'a mut W { + self.variant(GAIN_A::GAIN4) + } + #[doc = "8 MHz"] + #[inline(always)] + pub fn gain8(self) -> &'a mut W { + self.variant(GAIN_A::GAIN8) + } + #[doc = "16 MHz"] + #[inline(always)] + pub fn gain16(self) -> &'a mut W { + self.variant(GAIN_A::GAIN16) + } + #[doc = "30 MHz"] + #[inline(always)] + pub fn gain30(self) -> &'a mut W { + self.variant(GAIN_A::GAIN30) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u16 & 0x07) << 8); + self.w + } +} +#[doc = "Field `AMPGC` reader - Automatic Amplitude Gain Control"] +pub struct AMPGC_R(crate::FieldReader); +impl AMPGC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AMPGC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AMPGC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AMPGC` writer - Automatic Amplitude Gain Control"] +pub struct AMPGC_W<'a> { + w: &'a mut W, +} +impl<'a> AMPGC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u16 & 0x01) << 11); + self.w + } +} +#[doc = "Start-Up Time\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum STARTUP_A { + #[doc = "0: 31 us"] + CYCLE1 = 0, + #[doc = "1: 61 us"] + CYCLE2 = 1, + #[doc = "2: 122 us"] + CYCLE4 = 2, + #[doc = "3: 244 us"] + CYCLE8 = 3, + #[doc = "4: 488 us"] + CYCLE16 = 4, + #[doc = "5: 977 us"] + CYCLE32 = 5, + #[doc = "6: 1953 us"] + CYCLE64 = 6, + #[doc = "7: 3906 us"] + CYCLE128 = 7, + #[doc = "8: 7813 us"] + CYCLE256 = 8, + #[doc = "9: 15625 us"] + CYCLE512 = 9, + #[doc = "10: 31250 us"] + CYCLE1024 = 10, + #[doc = "11: 62500 us"] + CYCLE2048 = 11, + #[doc = "12: 125000 us"] + CYCLE4096 = 12, + #[doc = "13: 250000 us"] + CYCLE8192 = 13, + #[doc = "14: 500000 us"] + CYCLE16384 = 14, + #[doc = "15: 1000000 us"] + CYCLE32768 = 15, +} +impl From for u8 { + #[inline(always)] + fn from(variant: STARTUP_A) -> Self { + variant as _ + } +} +#[doc = "Field `STARTUP` reader - Start-Up Time"] +pub struct STARTUP_R(crate::FieldReader); +impl STARTUP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + STARTUP_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STARTUP_A { + match self.bits { + 0 => STARTUP_A::CYCLE1, + 1 => STARTUP_A::CYCLE2, + 2 => STARTUP_A::CYCLE4, + 3 => STARTUP_A::CYCLE8, + 4 => STARTUP_A::CYCLE16, + 5 => STARTUP_A::CYCLE32, + 6 => STARTUP_A::CYCLE64, + 7 => STARTUP_A::CYCLE128, + 8 => STARTUP_A::CYCLE256, + 9 => STARTUP_A::CYCLE512, + 10 => STARTUP_A::CYCLE1024, + 11 => STARTUP_A::CYCLE2048, + 12 => STARTUP_A::CYCLE4096, + 13 => STARTUP_A::CYCLE8192, + 14 => STARTUP_A::CYCLE16384, + 15 => STARTUP_A::CYCLE32768, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `CYCLE1`"] + #[inline(always)] + pub fn is_cycle1(&self) -> bool { + **self == STARTUP_A::CYCLE1 + } + #[doc = "Checks if the value of the field is `CYCLE2`"] + #[inline(always)] + pub fn is_cycle2(&self) -> bool { + **self == STARTUP_A::CYCLE2 + } + #[doc = "Checks if the value of the field is `CYCLE4`"] + #[inline(always)] + pub fn is_cycle4(&self) -> bool { + **self == STARTUP_A::CYCLE4 + } + #[doc = "Checks if the value of the field is `CYCLE8`"] + #[inline(always)] + pub fn is_cycle8(&self) -> bool { + **self == STARTUP_A::CYCLE8 + } + #[doc = "Checks if the value of the field is `CYCLE16`"] + #[inline(always)] + pub fn is_cycle16(&self) -> bool { + **self == STARTUP_A::CYCLE16 + } + #[doc = "Checks if the value of the field is `CYCLE32`"] + #[inline(always)] + pub fn is_cycle32(&self) -> bool { + **self == STARTUP_A::CYCLE32 + } + #[doc = "Checks if the value of the field is `CYCLE64`"] + #[inline(always)] + pub fn is_cycle64(&self) -> bool { + **self == STARTUP_A::CYCLE64 + } + #[doc = "Checks if the value of the field is `CYCLE128`"] + #[inline(always)] + pub fn is_cycle128(&self) -> bool { + **self == STARTUP_A::CYCLE128 + } + #[doc = "Checks if the value of the field is `CYCLE256`"] + #[inline(always)] + pub fn is_cycle256(&self) -> bool { + **self == STARTUP_A::CYCLE256 + } + #[doc = "Checks if the value of the field is `CYCLE512`"] + #[inline(always)] + pub fn is_cycle512(&self) -> bool { + **self == STARTUP_A::CYCLE512 + } + #[doc = "Checks if the value of the field is `CYCLE1024`"] + #[inline(always)] + pub fn is_cycle1024(&self) -> bool { + **self == STARTUP_A::CYCLE1024 + } + #[doc = "Checks if the value of the field is `CYCLE2048`"] + #[inline(always)] + pub fn is_cycle2048(&self) -> bool { + **self == STARTUP_A::CYCLE2048 + } + #[doc = "Checks if the value of the field is `CYCLE4096`"] + #[inline(always)] + pub fn is_cycle4096(&self) -> bool { + **self == STARTUP_A::CYCLE4096 + } + #[doc = "Checks if the value of the field is `CYCLE8192`"] + #[inline(always)] + pub fn is_cycle8192(&self) -> bool { + **self == STARTUP_A::CYCLE8192 + } + #[doc = "Checks if the value of the field is `CYCLE16384`"] + #[inline(always)] + pub fn is_cycle16384(&self) -> bool { + **self == STARTUP_A::CYCLE16384 + } + #[doc = "Checks if the value of the field is `CYCLE32768`"] + #[inline(always)] + pub fn is_cycle32768(&self) -> bool { + **self == STARTUP_A::CYCLE32768 + } +} +impl core::ops::Deref for STARTUP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STARTUP` writer - Start-Up Time"] +pub struct STARTUP_W<'a> { + w: &'a mut W, +} +impl<'a> STARTUP_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: STARTUP_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "31 us"] + #[inline(always)] + pub fn cycle1(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE1) + } + #[doc = "61 us"] + #[inline(always)] + pub fn cycle2(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE2) + } + #[doc = "122 us"] + #[inline(always)] + pub fn cycle4(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE4) + } + #[doc = "244 us"] + #[inline(always)] + pub fn cycle8(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE8) + } + #[doc = "488 us"] + #[inline(always)] + pub fn cycle16(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE16) + } + #[doc = "977 us"] + #[inline(always)] + pub fn cycle32(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE32) + } + #[doc = "1953 us"] + #[inline(always)] + pub fn cycle64(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE64) + } + #[doc = "3906 us"] + #[inline(always)] + pub fn cycle128(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE128) + } + #[doc = "7813 us"] + #[inline(always)] + pub fn cycle256(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE256) + } + #[doc = "15625 us"] + #[inline(always)] + pub fn cycle512(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE512) + } + #[doc = "31250 us"] + #[inline(always)] + pub fn cycle1024(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE1024) + } + #[doc = "62500 us"] + #[inline(always)] + pub fn cycle2048(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE2048) + } + #[doc = "125000 us"] + #[inline(always)] + pub fn cycle4096(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE4096) + } + #[doc = "250000 us"] + #[inline(always)] + pub fn cycle8192(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE8192) + } + #[doc = "500000 us"] + #[inline(always)] + pub fn cycle16384(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE16384) + } + #[doc = "1000000 us"] + #[inline(always)] + pub fn cycle32768(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE32768) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 12)) | ((value as u16 & 0x0f) << 12); + self.w + } +} +impl R { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Crystal Oscillator Enable"] + #[inline(always)] + pub fn xtalen(&self) -> XTALEN_R { + XTALEN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Xosc Clock Failure Detector Enable"] + #[inline(always)] + pub fn cfden(&self) -> CFDEN_R { + CFDEN_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Xosc Clock Switch Enable"] + #[inline(always)] + pub fn swben(&self) -> SWBEN_R { + SWBEN_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Oscillator Gain"] + #[inline(always)] + pub fn gain(&self) -> GAIN_R { + GAIN_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 11 - Automatic Amplitude Gain Control"] + #[inline(always)] + pub fn ampgc(&self) -> AMPGC_R { + AMPGC_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bits 12:15 - Start-Up Time"] + #[inline(always)] + pub fn startup(&self) -> STARTUP_R { + STARTUP_R::new(((self.bits >> 12) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - Crystal Oscillator Enable"] + #[inline(always)] + pub fn xtalen(&mut self) -> XTALEN_W { + XTALEN_W { w: self } + } + #[doc = "Bit 3 - Xosc Clock Failure Detector Enable"] + #[inline(always)] + pub fn cfden(&mut self) -> CFDEN_W { + CFDEN_W { w: self } + } + #[doc = "Bit 4 - Xosc Clock Switch Enable"] + #[inline(always)] + pub fn swben(&mut self) -> SWBEN_W { + SWBEN_W { w: self } + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Bits 8:10 - Oscillator Gain"] + #[inline(always)] + pub fn gain(&mut self) -> GAIN_W { + GAIN_W { w: self } + } + #[doc = "Bit 11 - Automatic Amplitude Gain Control"] + #[inline(always)] + pub fn ampgc(&mut self) -> AMPGC_W { + AMPGC_W { w: self } + } + #[doc = "Bits 12:15 - Start-Up Time"] + #[inline(always)] + pub fn startup(&mut self) -> STARTUP_W { + STARTUP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "External Multipurpose Crystal Oscillator (XOSC) Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [xoscctrl](index.html) module"] +pub struct XOSCCTRL_SPEC; +impl crate::RegisterSpec for XOSCCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [xoscctrl::R](R) reader structure"] +impl crate::Readable for XOSCCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [xoscctrl::W](W) writer structure"] +impl crate::Writable for XOSCCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets XOSCCTRL to value 0x80"] +impl crate::Resettable for XOSCCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x80 + } +} diff --git a/pac/atsamc21n/src/pac.rs b/pac/atsamc21n/src/pac.rs new file mode 100644 index 000000000000..6510f73b90c1 --- /dev/null +++ b/pac/atsamc21n/src/pac.rs @@ -0,0 +1,85 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Write control"] + pub wrctrl: crate::Reg, + #[doc = "0x04 - Event control"] + pub evctrl: crate::Reg, + _reserved2: [u8; 0x03], + #[doc = "0x08 - Interrupt enable clear"] + pub intenclr: crate::Reg, + #[doc = "0x09 - Interrupt enable set"] + pub intenset: crate::Reg, + _reserved4: [u8; 0x06], + #[doc = "0x10 - Bridge interrupt flag status"] + pub intflagahb: crate::Reg, + #[doc = "0x14 - Peripheral interrupt flag status - Bridge A"] + pub intflaga: crate::Reg, + #[doc = "0x18 - Peripheral interrupt flag status - Bridge B"] + pub intflagb: crate::Reg, + #[doc = "0x1c - Peripheral interrupt flag status - Bridge C"] + pub intflagc: crate::Reg, + #[doc = "0x20 - Peripheral interrupt flag status - Bridge D"] + pub intflagd: crate::Reg, + _reserved9: [u8; 0x10], + #[doc = "0x34 - Peripheral write protection status - Bridge A"] + pub statusa: crate::Reg, + #[doc = "0x38 - Peripheral write protection status - Bridge B"] + pub statusb: crate::Reg, + #[doc = "0x3c - Peripheral write protection status - Bridge C"] + pub statusc: crate::Reg, + #[doc = "0x40 - Peripheral write protection status - Bridge D"] + pub statusd: crate::Reg, +} +#[doc = "WRCTRL register accessor: an alias for `Reg`"] +pub type WRCTRL = crate::Reg; +#[doc = "Write control"] +pub mod wrctrl; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt enable clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt enable set"] +pub mod intenset; +#[doc = "INTFLAGAHB register accessor: an alias for `Reg`"] +pub type INTFLAGAHB = crate::Reg; +#[doc = "Bridge interrupt flag status"] +pub mod intflagahb; +#[doc = "INTFLAGA register accessor: an alias for `Reg`"] +pub type INTFLAGA = crate::Reg; +#[doc = "Peripheral interrupt flag status - Bridge A"] +pub mod intflaga; +#[doc = "INTFLAGB register accessor: an alias for `Reg`"] +pub type INTFLAGB = crate::Reg; +#[doc = "Peripheral interrupt flag status - Bridge B"] +pub mod intflagb; +#[doc = "INTFLAGC register accessor: an alias for `Reg`"] +pub type INTFLAGC = crate::Reg; +#[doc = "Peripheral interrupt flag status - Bridge C"] +pub mod intflagc; +#[doc = "INTFLAGD register accessor: an alias for `Reg`"] +pub type INTFLAGD = crate::Reg; +#[doc = "Peripheral interrupt flag status - Bridge D"] +pub mod intflagd; +#[doc = "STATUSA register accessor: an alias for `Reg`"] +pub type STATUSA = crate::Reg; +#[doc = "Peripheral write protection status - Bridge A"] +pub mod statusa; +#[doc = "STATUSB register accessor: an alias for `Reg`"] +pub type STATUSB = crate::Reg; +#[doc = "Peripheral write protection status - Bridge B"] +pub mod statusb; +#[doc = "STATUSC register accessor: an alias for `Reg`"] +pub type STATUSC = crate::Reg; +#[doc = "Peripheral write protection status - Bridge C"] +pub mod statusc; +#[doc = "STATUSD register accessor: an alias for `Reg`"] +pub type STATUSD = crate::Reg; +#[doc = "Peripheral write protection status - Bridge D"] +pub mod statusd; diff --git a/pac/atsamc21n/src/pac/evctrl.rs b/pac/atsamc21n/src/pac/evctrl.rs new file mode 100644 index 000000000000..630581b98c85 --- /dev/null +++ b/pac/atsamc21n/src/pac/evctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ERREO` reader - Peripheral acess error event output"] +pub struct ERREO_R(crate::FieldReader); +impl ERREO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERREO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERREO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERREO` writer - Peripheral acess error event output"] +pub struct ERREO_W<'a> { + w: &'a mut W, +} +impl<'a> ERREO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Peripheral acess error event output"] + #[inline(always)] + pub fn erreo(&self) -> ERREO_R { + ERREO_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Peripheral acess error event output"] + #[inline(always)] + pub fn erreo(&mut self) -> ERREO_W { + ERREO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/pac/intenclr.rs b/pac/atsamc21n/src/pac/intenclr.rs new file mode 100644 index 000000000000..609fe0fcf628 --- /dev/null +++ b/pac/atsamc21n/src/pac/intenclr.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ERR` reader - Peripheral access error interrupt disable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - Peripheral access error interrupt disable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Peripheral access error interrupt disable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Peripheral access error interrupt disable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt enable clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/pac/intenset.rs b/pac/atsamc21n/src/pac/intenset.rs new file mode 100644 index 000000000000..390545b588de --- /dev/null +++ b/pac/atsamc21n/src/pac/intenset.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ERR` reader - Peripheral access error interrupt enable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - Peripheral access error interrupt enable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Peripheral access error interrupt enable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Peripheral access error interrupt enable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt enable set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/pac/intflaga.rs b/pac/atsamc21n/src/pac/intflaga.rs new file mode 100644 index 000000000000..a1603451ad72 --- /dev/null +++ b/pac/atsamc21n/src/pac/intflaga.rs @@ -0,0 +1,677 @@ +#[doc = "Register `INTFLAGA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAGA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PAC_` reader - PAC"] +pub struct PAC__R(crate::FieldReader); +impl PAC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PAC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PAC_` writer - PAC"] +pub struct PAC__W<'a> { + w: &'a mut W, +} +impl<'a> PAC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `PM_` reader - PM"] +pub struct PM__R(crate::FieldReader); +impl PM__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PM__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PM__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PM_` writer - PM"] +pub struct PM__W<'a> { + w: &'a mut W, +} +impl<'a> PM__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MCLK_` reader - MCLK"] +pub struct MCLK__R(crate::FieldReader); +impl MCLK__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCLK__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCLK__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCLK_` writer - MCLK"] +pub struct MCLK__W<'a> { + w: &'a mut W, +} +impl<'a> MCLK__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RSTC_` reader - RSTC"] +pub struct RSTC__R(crate::FieldReader); +impl RSTC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RSTC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RSTC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RSTC_` writer - RSTC"] +pub struct RSTC__W<'a> { + w: &'a mut W, +} +impl<'a> RSTC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `OSCCTRL_` reader - OSCCTRL"] +pub struct OSCCTRL__R(crate::FieldReader); +impl OSCCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSCCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSCCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSCCTRL_` writer - OSCCTRL"] +pub struct OSCCTRL__W<'a> { + w: &'a mut W, +} +impl<'a> OSCCTRL__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `OSC32KCTRL_` reader - OSC32KCTRL"] +pub struct OSC32KCTRL__R(crate::FieldReader); +impl OSC32KCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC32KCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC32KCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC32KCTRL_` writer - OSC32KCTRL"] +pub struct OSC32KCTRL__W<'a> { + w: &'a mut W, +} +impl<'a> OSC32KCTRL__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `SUPC_` reader - SUPC"] +pub struct SUPC__R(crate::FieldReader); +impl SUPC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SUPC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SUPC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SUPC_` writer - SUPC"] +pub struct SUPC__W<'a> { + w: &'a mut W, +} +impl<'a> SUPC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `GCLK_` reader - GCLK"] +pub struct GCLK__R(crate::FieldReader); +impl GCLK__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GCLK__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GCLK__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GCLK_` writer - GCLK"] +pub struct GCLK__W<'a> { + w: &'a mut W, +} +impl<'a> GCLK__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `WDT_` reader - WDT"] +pub struct WDT__R(crate::FieldReader); +impl WDT__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WDT__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WDT__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WDT_` writer - WDT"] +pub struct WDT__W<'a> { + w: &'a mut W, +} +impl<'a> WDT__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `RTC_` reader - RTC"] +pub struct RTC__R(crate::FieldReader); +impl RTC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RTC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RTC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RTC_` writer - RTC"] +pub struct RTC__W<'a> { + w: &'a mut W, +} +impl<'a> RTC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `EIC_` reader - EIC"] +pub struct EIC__R(crate::FieldReader); +impl EIC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EIC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EIC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EIC_` writer - EIC"] +pub struct EIC__W<'a> { + w: &'a mut W, +} +impl<'a> EIC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `FREQM_` reader - FREQM"] +pub struct FREQM__R(crate::FieldReader); +impl FREQM__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FREQM__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FREQM__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FREQM_` writer - FREQM"] +pub struct FREQM__W<'a> { + w: &'a mut W, +} +impl<'a> FREQM__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `TSENS_` reader - TSENS"] +pub struct TSENS__R(crate::FieldReader); +impl TSENS__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSENS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSENS__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSENS_` writer - TSENS"] +pub struct TSENS__W<'a> { + w: &'a mut W, +} +impl<'a> TSENS__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +impl R { + #[doc = "Bit 0 - PAC"] + #[inline(always)] + pub fn pac_(&self) -> PAC__R { + PAC__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - PM"] + #[inline(always)] + pub fn pm_(&self) -> PM__R { + PM__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - MCLK"] + #[inline(always)] + pub fn mclk_(&self) -> MCLK__R { + MCLK__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - RSTC"] + #[inline(always)] + pub fn rstc_(&self) -> RSTC__R { + RSTC__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - OSCCTRL"] + #[inline(always)] + pub fn oscctrl_(&self) -> OSCCTRL__R { + OSCCTRL__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - OSC32KCTRL"] + #[inline(always)] + pub fn osc32kctrl_(&self) -> OSC32KCTRL__R { + OSC32KCTRL__R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - SUPC"] + #[inline(always)] + pub fn supc_(&self) -> SUPC__R { + SUPC__R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - GCLK"] + #[inline(always)] + pub fn gclk_(&self) -> GCLK__R { + GCLK__R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - WDT"] + #[inline(always)] + pub fn wdt_(&self) -> WDT__R { + WDT__R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - RTC"] + #[inline(always)] + pub fn rtc_(&self) -> RTC__R { + RTC__R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - EIC"] + #[inline(always)] + pub fn eic_(&self) -> EIC__R { + EIC__R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - FREQM"] + #[inline(always)] + pub fn freqm_(&self) -> FREQM__R { + FREQM__R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - TSENS"] + #[inline(always)] + pub fn tsens_(&self) -> TSENS__R { + TSENS__R::new(((self.bits >> 12) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - PAC"] + #[inline(always)] + pub fn pac_(&mut self) -> PAC__W { + PAC__W { w: self } + } + #[doc = "Bit 1 - PM"] + #[inline(always)] + pub fn pm_(&mut self) -> PM__W { + PM__W { w: self } + } + #[doc = "Bit 2 - MCLK"] + #[inline(always)] + pub fn mclk_(&mut self) -> MCLK__W { + MCLK__W { w: self } + } + #[doc = "Bit 3 - RSTC"] + #[inline(always)] + pub fn rstc_(&mut self) -> RSTC__W { + RSTC__W { w: self } + } + #[doc = "Bit 4 - OSCCTRL"] + #[inline(always)] + pub fn oscctrl_(&mut self) -> OSCCTRL__W { + OSCCTRL__W { w: self } + } + #[doc = "Bit 5 - OSC32KCTRL"] + #[inline(always)] + pub fn osc32kctrl_(&mut self) -> OSC32KCTRL__W { + OSC32KCTRL__W { w: self } + } + #[doc = "Bit 6 - SUPC"] + #[inline(always)] + pub fn supc_(&mut self) -> SUPC__W { + SUPC__W { w: self } + } + #[doc = "Bit 7 - GCLK"] + #[inline(always)] + pub fn gclk_(&mut self) -> GCLK__W { + GCLK__W { w: self } + } + #[doc = "Bit 8 - WDT"] + #[inline(always)] + pub fn wdt_(&mut self) -> WDT__W { + WDT__W { w: self } + } + #[doc = "Bit 9 - RTC"] + #[inline(always)] + pub fn rtc_(&mut self) -> RTC__W { + RTC__W { w: self } + } + #[doc = "Bit 10 - EIC"] + #[inline(always)] + pub fn eic_(&mut self) -> EIC__W { + EIC__W { w: self } + } + #[doc = "Bit 11 - FREQM"] + #[inline(always)] + pub fn freqm_(&mut self) -> FREQM__W { + FREQM__W { w: self } + } + #[doc = "Bit 12 - TSENS"] + #[inline(always)] + pub fn tsens_(&mut self) -> TSENS__W { + TSENS__W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Peripheral interrupt flag status - Bridge A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflaga](index.html) module"] +pub struct INTFLAGA_SPEC; +impl crate::RegisterSpec for INTFLAGA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflaga::R](R) reader structure"] +impl crate::Readable for INTFLAGA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflaga::W](W) writer structure"] +impl crate::Writable for INTFLAGA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAGA to value 0"] +impl crate::Resettable for INTFLAGA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/pac/intflagahb.rs b/pac/atsamc21n/src/pac/intflagahb.rs new file mode 100644 index 000000000000..72fe915eb008 --- /dev/null +++ b/pac/atsamc21n/src/pac/intflagahb.rs @@ -0,0 +1,489 @@ +#[doc = "Register `INTFLAGAHB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAGAHB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FLASH_` reader - FLASH"] +pub struct FLASH__R(crate::FieldReader); +impl FLASH__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FLASH__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FLASH__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLASH_` writer - FLASH"] +pub struct FLASH__W<'a> { + w: &'a mut W, +} +impl<'a> FLASH__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `HSRAMCM0P_` reader - HSRAMCM0P"] +pub struct HSRAMCM0P__R(crate::FieldReader); +impl HSRAMCM0P__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HSRAMCM0P__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HSRAMCM0P__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HSRAMCM0P_` writer - HSRAMCM0P"] +pub struct HSRAMCM0P__W<'a> { + w: &'a mut W, +} +impl<'a> HSRAMCM0P__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `HSRAMDSU_` reader - HSRAMDSU"] +pub struct HSRAMDSU__R(crate::FieldReader); +impl HSRAMDSU__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HSRAMDSU__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HSRAMDSU__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HSRAMDSU_` writer - HSRAMDSU"] +pub struct HSRAMDSU__W<'a> { + w: &'a mut W, +} +impl<'a> HSRAMDSU__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `HPB1_` reader - HPB1"] +pub struct HPB1__R(crate::FieldReader); +impl HPB1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HPB1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HPB1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HPB1_` writer - HPB1"] +pub struct HPB1__W<'a> { + w: &'a mut W, +} +impl<'a> HPB1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `HPB0_` reader - HPB0"] +pub struct HPB0__R(crate::FieldReader); +impl HPB0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HPB0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HPB0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HPB0_` writer - HPB0"] +pub struct HPB0__W<'a> { + w: &'a mut W, +} +impl<'a> HPB0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `HPB2_` reader - HPB2"] +pub struct HPB2__R(crate::FieldReader); +impl HPB2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HPB2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HPB2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HPB2_` writer - HPB2"] +pub struct HPB2__W<'a> { + w: &'a mut W, +} +impl<'a> HPB2__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `LPRAMDMAC_` reader - LPRAMDMAC"] +pub struct LPRAMDMAC__R(crate::FieldReader); +impl LPRAMDMAC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LPRAMDMAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LPRAMDMAC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LPRAMDMAC_` writer - LPRAMDMAC"] +pub struct LPRAMDMAC__W<'a> { + w: &'a mut W, +} +impl<'a> LPRAMDMAC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `DIVAS_` reader - DIVAS"] +pub struct DIVAS__R(crate::FieldReader); +impl DIVAS__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIVAS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIVAS__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIVAS_` writer - DIVAS"] +pub struct DIVAS__W<'a> { + w: &'a mut W, +} +impl<'a> DIVAS__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `HPB3_` reader - HPB3"] +pub struct HPB3__R(crate::FieldReader); +impl HPB3__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HPB3__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HPB3__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HPB3_` writer - HPB3"] +pub struct HPB3__W<'a> { + w: &'a mut W, +} +impl<'a> HPB3__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +impl R { + #[doc = "Bit 0 - FLASH"] + #[inline(always)] + pub fn flash_(&self) -> FLASH__R { + FLASH__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - HSRAMCM0P"] + #[inline(always)] + pub fn hsramcm0p_(&self) -> HSRAMCM0P__R { + HSRAMCM0P__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - HSRAMDSU"] + #[inline(always)] + pub fn hsramdsu_(&self) -> HSRAMDSU__R { + HSRAMDSU__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - HPB1"] + #[inline(always)] + pub fn hpb1_(&self) -> HPB1__R { + HPB1__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - HPB0"] + #[inline(always)] + pub fn hpb0_(&self) -> HPB0__R { + HPB0__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - HPB2"] + #[inline(always)] + pub fn hpb2_(&self) -> HPB2__R { + HPB2__R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - LPRAMDMAC"] + #[inline(always)] + pub fn lpramdmac_(&self) -> LPRAMDMAC__R { + LPRAMDMAC__R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - DIVAS"] + #[inline(always)] + pub fn divas_(&self) -> DIVAS__R { + DIVAS__R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - HPB3"] + #[inline(always)] + pub fn hpb3_(&self) -> HPB3__R { + HPB3__R::new(((self.bits >> 8) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - FLASH"] + #[inline(always)] + pub fn flash_(&mut self) -> FLASH__W { + FLASH__W { w: self } + } + #[doc = "Bit 1 - HSRAMCM0P"] + #[inline(always)] + pub fn hsramcm0p_(&mut self) -> HSRAMCM0P__W { + HSRAMCM0P__W { w: self } + } + #[doc = "Bit 2 - HSRAMDSU"] + #[inline(always)] + pub fn hsramdsu_(&mut self) -> HSRAMDSU__W { + HSRAMDSU__W { w: self } + } + #[doc = "Bit 3 - HPB1"] + #[inline(always)] + pub fn hpb1_(&mut self) -> HPB1__W { + HPB1__W { w: self } + } + #[doc = "Bit 4 - HPB0"] + #[inline(always)] + pub fn hpb0_(&mut self) -> HPB0__W { + HPB0__W { w: self } + } + #[doc = "Bit 5 - HPB2"] + #[inline(always)] + pub fn hpb2_(&mut self) -> HPB2__W { + HPB2__W { w: self } + } + #[doc = "Bit 6 - LPRAMDMAC"] + #[inline(always)] + pub fn lpramdmac_(&mut self) -> LPRAMDMAC__W { + LPRAMDMAC__W { w: self } + } + #[doc = "Bit 7 - DIVAS"] + #[inline(always)] + pub fn divas_(&mut self) -> DIVAS__W { + DIVAS__W { w: self } + } + #[doc = "Bit 8 - HPB3"] + #[inline(always)] + pub fn hpb3_(&mut self) -> HPB3__W { + HPB3__W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Bridge interrupt flag status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflagahb](index.html) module"] +pub struct INTFLAGAHB_SPEC; +impl crate::RegisterSpec for INTFLAGAHB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflagahb::R](R) reader structure"] +impl crate::Readable for INTFLAGAHB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflagahb::W](W) writer structure"] +impl crate::Writable for INTFLAGAHB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAGAHB to value 0"] +impl crate::Resettable for INTFLAGAHB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/pac/intflagb.rs b/pac/atsamc21n/src/pac/intflagb.rs new file mode 100644 index 000000000000..8359f7e11f30 --- /dev/null +++ b/pac/atsamc21n/src/pac/intflagb.rs @@ -0,0 +1,348 @@ +#[doc = "Register `INTFLAGB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAGB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PORT_` reader - PORT"] +pub struct PORT__R(crate::FieldReader); +impl PORT__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PORT__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PORT__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PORT_` writer - PORT"] +pub struct PORT__W<'a> { + w: &'a mut W, +} +impl<'a> PORT__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `DSU_` reader - DSU"] +pub struct DSU__R(crate::FieldReader); +impl DSU__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DSU__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DSU__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DSU_` writer - DSU"] +pub struct DSU__W<'a> { + w: &'a mut W, +} +impl<'a> DSU__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `NVMCTRL_` reader - NVMCTRL"] +pub struct NVMCTRL__R(crate::FieldReader); +impl NVMCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NVMCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NVMCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NVMCTRL_` writer - NVMCTRL"] +pub struct NVMCTRL__W<'a> { + w: &'a mut W, +} +impl<'a> NVMCTRL__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `DMAC_` reader - DMAC"] +pub struct DMAC__R(crate::FieldReader); +impl DMAC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DMAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DMAC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DMAC_` writer - DMAC"] +pub struct DMAC__W<'a> { + w: &'a mut W, +} +impl<'a> DMAC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `MTB_` reader - MTB"] +pub struct MTB__R(crate::FieldReader); +impl MTB__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MTB__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MTB__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MTB_` writer - MTB"] +pub struct MTB__W<'a> { + w: &'a mut W, +} +impl<'a> MTB__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `HMATRIXHS_` reader - HMATRIXHS"] +pub struct HMATRIXHS__R(crate::FieldReader); +impl HMATRIXHS__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HMATRIXHS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HMATRIXHS__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HMATRIXHS_` writer - HMATRIXHS"] +pub struct HMATRIXHS__W<'a> { + w: &'a mut W, +} +impl<'a> HMATRIXHS__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - PORT"] + #[inline(always)] + pub fn port_(&self) -> PORT__R { + PORT__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - DSU"] + #[inline(always)] + pub fn dsu_(&self) -> DSU__R { + DSU__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - NVMCTRL"] + #[inline(always)] + pub fn nvmctrl_(&self) -> NVMCTRL__R { + NVMCTRL__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - DMAC"] + #[inline(always)] + pub fn dmac_(&self) -> DMAC__R { + DMAC__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - MTB"] + #[inline(always)] + pub fn mtb_(&self) -> MTB__R { + MTB__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - HMATRIXHS"] + #[inline(always)] + pub fn hmatrixhs_(&self) -> HMATRIXHS__R { + HMATRIXHS__R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - PORT"] + #[inline(always)] + pub fn port_(&mut self) -> PORT__W { + PORT__W { w: self } + } + #[doc = "Bit 1 - DSU"] + #[inline(always)] + pub fn dsu_(&mut self) -> DSU__W { + DSU__W { w: self } + } + #[doc = "Bit 2 - NVMCTRL"] + #[inline(always)] + pub fn nvmctrl_(&mut self) -> NVMCTRL__W { + NVMCTRL__W { w: self } + } + #[doc = "Bit 3 - DMAC"] + #[inline(always)] + pub fn dmac_(&mut self) -> DMAC__W { + DMAC__W { w: self } + } + #[doc = "Bit 4 - MTB"] + #[inline(always)] + pub fn mtb_(&mut self) -> MTB__W { + MTB__W { w: self } + } + #[doc = "Bit 5 - HMATRIXHS"] + #[inline(always)] + pub fn hmatrixhs_(&mut self) -> HMATRIXHS__W { + HMATRIXHS__W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Peripheral interrupt flag status - Bridge B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflagb](index.html) module"] +pub struct INTFLAGB_SPEC; +impl crate::RegisterSpec for INTFLAGB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflagb::R](R) reader structure"] +impl crate::Readable for INTFLAGB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflagb::W](W) writer structure"] +impl crate::Writable for INTFLAGB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAGB to value 0"] +impl crate::Resettable for INTFLAGB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/pac/intflagc.rs b/pac/atsamc21n/src/pac/intflagc.rs new file mode 100644 index 000000000000..80ee48da5eeb --- /dev/null +++ b/pac/atsamc21n/src/pac/intflagc.rs @@ -0,0 +1,1194 @@ +#[doc = "Register `INTFLAGC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAGC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVSYS_` reader - EVSYS"] +pub struct EVSYS__R(crate::FieldReader); +impl EVSYS__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVSYS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVSYS__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVSYS_` writer - EVSYS"] +pub struct EVSYS__W<'a> { + w: &'a mut W, +} +impl<'a> EVSYS__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `SERCOM0_` reader - SERCOM0"] +pub struct SERCOM0__R(crate::FieldReader); +impl SERCOM0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM0_` writer - SERCOM0"] +pub struct SERCOM0__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SERCOM1_` reader - SERCOM1"] +pub struct SERCOM1__R(crate::FieldReader); +impl SERCOM1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM1_` writer - SERCOM1"] +pub struct SERCOM1__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SERCOM2_` reader - SERCOM2"] +pub struct SERCOM2__R(crate::FieldReader); +impl SERCOM2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM2_` writer - SERCOM2"] +pub struct SERCOM2__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM2__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `SERCOM3_` reader - SERCOM3"] +pub struct SERCOM3__R(crate::FieldReader); +impl SERCOM3__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM3__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM3__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM3_` writer - SERCOM3"] +pub struct SERCOM3__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM3__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `SERCOM4_` reader - SERCOM4"] +pub struct SERCOM4__R(crate::FieldReader); +impl SERCOM4__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM4__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM4__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM4_` writer - SERCOM4"] +pub struct SERCOM4__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM4__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `SERCOM5_` reader - SERCOM5"] +pub struct SERCOM5__R(crate::FieldReader); +impl SERCOM5__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM5__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM5__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM5_` writer - SERCOM5"] +pub struct SERCOM5__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM5__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `CAN0_` reader - CAN0"] +pub struct CAN0__R(crate::FieldReader); +impl CAN0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CAN0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CAN0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAN0_` writer - CAN0"] +pub struct CAN0__W<'a> { + w: &'a mut W, +} +impl<'a> CAN0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CAN1_` reader - CAN1"] +pub struct CAN1__R(crate::FieldReader); +impl CAN1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CAN1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CAN1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAN1_` writer - CAN1"] +pub struct CAN1__W<'a> { + w: &'a mut W, +} +impl<'a> CAN1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `TCC0_` reader - TCC0"] +pub struct TCC0__R(crate::FieldReader); +impl TCC0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCC0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCC0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCC0_` writer - TCC0"] +pub struct TCC0__W<'a> { + w: &'a mut W, +} +impl<'a> TCC0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `TCC1_` reader - TCC1"] +pub struct TCC1__R(crate::FieldReader); +impl TCC1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCC1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCC1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCC1_` writer - TCC1"] +pub struct TCC1__W<'a> { + w: &'a mut W, +} +impl<'a> TCC1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `TCC2_` reader - TCC2"] +pub struct TCC2__R(crate::FieldReader); +impl TCC2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCC2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCC2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCC2_` writer - TCC2"] +pub struct TCC2__W<'a> { + w: &'a mut W, +} +impl<'a> TCC2__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `TC0_` reader - TC0"] +pub struct TC0__R(crate::FieldReader); +impl TC0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC0_` writer - TC0"] +pub struct TC0__W<'a> { + w: &'a mut W, +} +impl<'a> TC0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `TC1_` reader - TC1"] +pub struct TC1__R(crate::FieldReader); +impl TC1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC1_` writer - TC1"] +pub struct TC1__W<'a> { + w: &'a mut W, +} +impl<'a> TC1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `TC2_` reader - TC2"] +pub struct TC2__R(crate::FieldReader); +impl TC2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC2_` writer - TC2"] +pub struct TC2__W<'a> { + w: &'a mut W, +} +impl<'a> TC2__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `TC3_` reader - TC3"] +pub struct TC3__R(crate::FieldReader); +impl TC3__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC3__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC3__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC3_` writer - TC3"] +pub struct TC3__W<'a> { + w: &'a mut W, +} +impl<'a> TC3__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `TC4_` reader - TC4"] +pub struct TC4__R(crate::FieldReader); +impl TC4__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC4__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC4__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC4_` writer - TC4"] +pub struct TC4__W<'a> { + w: &'a mut W, +} +impl<'a> TC4__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `ADC0_` reader - ADC0"] +pub struct ADC0__R(crate::FieldReader); +impl ADC0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ADC0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADC0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADC0_` writer - ADC0"] +pub struct ADC0__W<'a> { + w: &'a mut W, +} +impl<'a> ADC0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `ADC1_` reader - ADC1"] +pub struct ADC1__R(crate::FieldReader); +impl ADC1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ADC1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADC1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADC1_` writer - ADC1"] +pub struct ADC1__W<'a> { + w: &'a mut W, +} +impl<'a> ADC1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `SDADC_` reader - SDADC"] +pub struct SDADC__R(crate::FieldReader); +impl SDADC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SDADC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SDADC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SDADC_` writer - SDADC"] +pub struct SDADC__W<'a> { + w: &'a mut W, +} +impl<'a> SDADC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `AC_` reader - AC"] +pub struct AC__R(crate::FieldReader); +impl AC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AC_` writer - AC"] +pub struct AC__W<'a> { + w: &'a mut W, +} +impl<'a> AC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `DAC_` reader - DAC"] +pub struct DAC__R(crate::FieldReader); +impl DAC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DAC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DAC_` writer - DAC"] +pub struct DAC__W<'a> { + w: &'a mut W, +} +impl<'a> DAC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `PTC_` reader - PTC"] +pub struct PTC__R(crate::FieldReader); +impl PTC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PTC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PTC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PTC_` writer - PTC"] +pub struct PTC__W<'a> { + w: &'a mut W, +} +impl<'a> PTC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `CCL_` reader - CCL"] +pub struct CCL__R(crate::FieldReader); +impl CCL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCL_` writer - CCL"] +pub struct CCL__W<'a> { + w: &'a mut W, +} +impl<'a> CCL__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +impl R { + #[doc = "Bit 0 - EVSYS"] + #[inline(always)] + pub fn evsys_(&self) -> EVSYS__R { + EVSYS__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM0"] + #[inline(always)] + pub fn sercom0_(&self) -> SERCOM0__R { + SERCOM0__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - SERCOM1"] + #[inline(always)] + pub fn sercom1_(&self) -> SERCOM1__R { + SERCOM1__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - SERCOM2"] + #[inline(always)] + pub fn sercom2_(&self) -> SERCOM2__R { + SERCOM2__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - SERCOM3"] + #[inline(always)] + pub fn sercom3_(&self) -> SERCOM3__R { + SERCOM3__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - SERCOM4"] + #[inline(always)] + pub fn sercom4_(&self) -> SERCOM4__R { + SERCOM4__R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - SERCOM5"] + #[inline(always)] + pub fn sercom5_(&self) -> SERCOM5__R { + SERCOM5__R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - CAN0"] + #[inline(always)] + pub fn can0_(&self) -> CAN0__R { + CAN0__R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - CAN1"] + #[inline(always)] + pub fn can1_(&self) -> CAN1__R { + CAN1__R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - TCC0"] + #[inline(always)] + pub fn tcc0_(&self) -> TCC0__R { + TCC0__R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - TCC1"] + #[inline(always)] + pub fn tcc1_(&self) -> TCC1__R { + TCC1__R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - TCC2"] + #[inline(always)] + pub fn tcc2_(&self) -> TCC2__R { + TCC2__R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - TC0"] + #[inline(always)] + pub fn tc0_(&self) -> TC0__R { + TC0__R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - TC1"] + #[inline(always)] + pub fn tc1_(&self) -> TC1__R { + TC1__R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - TC2"] + #[inline(always)] + pub fn tc2_(&self) -> TC2__R { + TC2__R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - TC3"] + #[inline(always)] + pub fn tc3_(&self) -> TC3__R { + TC3__R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - TC4"] + #[inline(always)] + pub fn tc4_(&self) -> TC4__R { + TC4__R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - ADC0"] + #[inline(always)] + pub fn adc0_(&self) -> ADC0__R { + ADC0__R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - ADC1"] + #[inline(always)] + pub fn adc1_(&self) -> ADC1__R { + ADC1__R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - SDADC"] + #[inline(always)] + pub fn sdadc_(&self) -> SDADC__R { + SDADC__R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - AC"] + #[inline(always)] + pub fn ac_(&self) -> AC__R { + AC__R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - DAC"] + #[inline(always)] + pub fn dac_(&self) -> DAC__R { + DAC__R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - PTC"] + #[inline(always)] + pub fn ptc_(&self) -> PTC__R { + PTC__R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - CCL"] + #[inline(always)] + pub fn ccl_(&self) -> CCL__R { + CCL__R::new(((self.bits >> 23) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - EVSYS"] + #[inline(always)] + pub fn evsys_(&mut self) -> EVSYS__W { + EVSYS__W { w: self } + } + #[doc = "Bit 1 - SERCOM0"] + #[inline(always)] + pub fn sercom0_(&mut self) -> SERCOM0__W { + SERCOM0__W { w: self } + } + #[doc = "Bit 2 - SERCOM1"] + #[inline(always)] + pub fn sercom1_(&mut self) -> SERCOM1__W { + SERCOM1__W { w: self } + } + #[doc = "Bit 3 - SERCOM2"] + #[inline(always)] + pub fn sercom2_(&mut self) -> SERCOM2__W { + SERCOM2__W { w: self } + } + #[doc = "Bit 4 - SERCOM3"] + #[inline(always)] + pub fn sercom3_(&mut self) -> SERCOM3__W { + SERCOM3__W { w: self } + } + #[doc = "Bit 5 - SERCOM4"] + #[inline(always)] + pub fn sercom4_(&mut self) -> SERCOM4__W { + SERCOM4__W { w: self } + } + #[doc = "Bit 6 - SERCOM5"] + #[inline(always)] + pub fn sercom5_(&mut self) -> SERCOM5__W { + SERCOM5__W { w: self } + } + #[doc = "Bit 7 - CAN0"] + #[inline(always)] + pub fn can0_(&mut self) -> CAN0__W { + CAN0__W { w: self } + } + #[doc = "Bit 8 - CAN1"] + #[inline(always)] + pub fn can1_(&mut self) -> CAN1__W { + CAN1__W { w: self } + } + #[doc = "Bit 9 - TCC0"] + #[inline(always)] + pub fn tcc0_(&mut self) -> TCC0__W { + TCC0__W { w: self } + } + #[doc = "Bit 10 - TCC1"] + #[inline(always)] + pub fn tcc1_(&mut self) -> TCC1__W { + TCC1__W { w: self } + } + #[doc = "Bit 11 - TCC2"] + #[inline(always)] + pub fn tcc2_(&mut self) -> TCC2__W { + TCC2__W { w: self } + } + #[doc = "Bit 12 - TC0"] + #[inline(always)] + pub fn tc0_(&mut self) -> TC0__W { + TC0__W { w: self } + } + #[doc = "Bit 13 - TC1"] + #[inline(always)] + pub fn tc1_(&mut self) -> TC1__W { + TC1__W { w: self } + } + #[doc = "Bit 14 - TC2"] + #[inline(always)] + pub fn tc2_(&mut self) -> TC2__W { + TC2__W { w: self } + } + #[doc = "Bit 15 - TC3"] + #[inline(always)] + pub fn tc3_(&mut self) -> TC3__W { + TC3__W { w: self } + } + #[doc = "Bit 16 - TC4"] + #[inline(always)] + pub fn tc4_(&mut self) -> TC4__W { + TC4__W { w: self } + } + #[doc = "Bit 17 - ADC0"] + #[inline(always)] + pub fn adc0_(&mut self) -> ADC0__W { + ADC0__W { w: self } + } + #[doc = "Bit 18 - ADC1"] + #[inline(always)] + pub fn adc1_(&mut self) -> ADC1__W { + ADC1__W { w: self } + } + #[doc = "Bit 19 - SDADC"] + #[inline(always)] + pub fn sdadc_(&mut self) -> SDADC__W { + SDADC__W { w: self } + } + #[doc = "Bit 20 - AC"] + #[inline(always)] + pub fn ac_(&mut self) -> AC__W { + AC__W { w: self } + } + #[doc = "Bit 21 - DAC"] + #[inline(always)] + pub fn dac_(&mut self) -> DAC__W { + DAC__W { w: self } + } + #[doc = "Bit 22 - PTC"] + #[inline(always)] + pub fn ptc_(&mut self) -> PTC__W { + PTC__W { w: self } + } + #[doc = "Bit 23 - CCL"] + #[inline(always)] + pub fn ccl_(&mut self) -> CCL__W { + CCL__W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Peripheral interrupt flag status - Bridge C\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflagc](index.html) module"] +pub struct INTFLAGC_SPEC; +impl crate::RegisterSpec for INTFLAGC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflagc::R](R) reader structure"] +impl crate::Readable for INTFLAGC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflagc::W](W) writer structure"] +impl crate::Writable for INTFLAGC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAGC to value 0"] +impl crate::Resettable for INTFLAGC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/pac/intflagd.rs b/pac/atsamc21n/src/pac/intflagd.rs new file mode 100644 index 000000000000..9beeb48bdb72 --- /dev/null +++ b/pac/atsamc21n/src/pac/intflagd.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTFLAGD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAGD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SERCOM6_` reader - SERCOM6"] +pub struct SERCOM6__R(crate::FieldReader); +impl SERCOM6__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM6__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM6__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM6_` writer - SERCOM6"] +pub struct SERCOM6__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM6__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `SERCOM7_` reader - SERCOM7"] +pub struct SERCOM7__R(crate::FieldReader); +impl SERCOM7__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM7__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM7__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM7_` writer - SERCOM7"] +pub struct SERCOM7__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM7__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `TC5_` reader - TC5"] +pub struct TC5__R(crate::FieldReader); +impl TC5__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC5__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC5__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC5_` writer - TC5"] +pub struct TC5__W<'a> { + w: &'a mut W, +} +impl<'a> TC5__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `TC6_` reader - TC6"] +pub struct TC6__R(crate::FieldReader); +impl TC6__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC6__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC6__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC6_` writer - TC6"] +pub struct TC6__W<'a> { + w: &'a mut W, +} +impl<'a> TC6__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `TC7_` reader - TC7"] +pub struct TC7__R(crate::FieldReader); +impl TC7__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC7__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC7__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC7_` writer - TC7"] +pub struct TC7__W<'a> { + w: &'a mut W, +} +impl<'a> TC7__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +impl R { + #[doc = "Bit 0 - SERCOM6"] + #[inline(always)] + pub fn sercom6_(&self) -> SERCOM6__R { + SERCOM6__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM7"] + #[inline(always)] + pub fn sercom7_(&self) -> SERCOM7__R { + SERCOM7__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - TC5"] + #[inline(always)] + pub fn tc5_(&self) -> TC5__R { + TC5__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - TC6"] + #[inline(always)] + pub fn tc6_(&self) -> TC6__R { + TC6__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - TC7"] + #[inline(always)] + pub fn tc7_(&self) -> TC7__R { + TC7__R::new(((self.bits >> 4) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - SERCOM6"] + #[inline(always)] + pub fn sercom6_(&mut self) -> SERCOM6__W { + SERCOM6__W { w: self } + } + #[doc = "Bit 1 - SERCOM7"] + #[inline(always)] + pub fn sercom7_(&mut self) -> SERCOM7__W { + SERCOM7__W { w: self } + } + #[doc = "Bit 2 - TC5"] + #[inline(always)] + pub fn tc5_(&mut self) -> TC5__W { + TC5__W { w: self } + } + #[doc = "Bit 3 - TC6"] + #[inline(always)] + pub fn tc6_(&mut self) -> TC6__W { + TC6__W { w: self } + } + #[doc = "Bit 4 - TC7"] + #[inline(always)] + pub fn tc7_(&mut self) -> TC7__W { + TC7__W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Peripheral interrupt flag status - Bridge D\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflagd](index.html) module"] +pub struct INTFLAGD_SPEC; +impl crate::RegisterSpec for INTFLAGD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflagd::R](R) reader structure"] +impl crate::Readable for INTFLAGD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflagd::W](W) writer structure"] +impl crate::Writable for INTFLAGD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAGD to value 0"] +impl crate::Resettable for INTFLAGD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/pac/statusa.rs b/pac/atsamc21n/src/pac/statusa.rs new file mode 100644 index 000000000000..ca22aef2f1ce --- /dev/null +++ b/pac/atsamc21n/src/pac/statusa.rs @@ -0,0 +1,293 @@ +#[doc = "Register `STATUSA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PAC_` reader - PAC APB Protect Enable"] +pub struct PAC__R(crate::FieldReader); +impl PAC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PAC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PM_` reader - PM APB Protect Enable"] +pub struct PM__R(crate::FieldReader); +impl PM__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PM__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PM__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCLK_` reader - MCLK APB Protect Enable"] +pub struct MCLK__R(crate::FieldReader); +impl MCLK__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCLK__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCLK__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RSTC_` reader - RSTC APB Protect Enable"] +pub struct RSTC__R(crate::FieldReader); +impl RSTC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RSTC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RSTC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSCCTRL_` reader - OSCCTRL APB Protect Enable"] +pub struct OSCCTRL__R(crate::FieldReader); +impl OSCCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSCCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSCCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC32KCTRL_` reader - OSC32KCTRL APB Protect Enable"] +pub struct OSC32KCTRL__R(crate::FieldReader); +impl OSC32KCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC32KCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC32KCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SUPC_` reader - SUPC APB Protect Enable"] +pub struct SUPC__R(crate::FieldReader); +impl SUPC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SUPC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SUPC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GCLK_` reader - GCLK APB Protect Enable"] +pub struct GCLK__R(crate::FieldReader); +impl GCLK__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GCLK__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GCLK__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WDT_` reader - WDT APB Protect Enable"] +pub struct WDT__R(crate::FieldReader); +impl WDT__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WDT__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WDT__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RTC_` reader - RTC APB Protect Enable"] +pub struct RTC__R(crate::FieldReader); +impl RTC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RTC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RTC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EIC_` reader - EIC APB Protect Enable"] +pub struct EIC__R(crate::FieldReader); +impl EIC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EIC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EIC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FREQM_` reader - FREQM APB Protect Enable"] +pub struct FREQM__R(crate::FieldReader); +impl FREQM__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FREQM__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FREQM__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSENS_` reader - TSENS APB Protect Enable"] +pub struct TSENS__R(crate::FieldReader); +impl TSENS__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSENS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSENS__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - PAC APB Protect Enable"] + #[inline(always)] + pub fn pac_(&self) -> PAC__R { + PAC__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - PM APB Protect Enable"] + #[inline(always)] + pub fn pm_(&self) -> PM__R { + PM__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - MCLK APB Protect Enable"] + #[inline(always)] + pub fn mclk_(&self) -> MCLK__R { + MCLK__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - RSTC APB Protect Enable"] + #[inline(always)] + pub fn rstc_(&self) -> RSTC__R { + RSTC__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - OSCCTRL APB Protect Enable"] + #[inline(always)] + pub fn oscctrl_(&self) -> OSCCTRL__R { + OSCCTRL__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - OSC32KCTRL APB Protect Enable"] + #[inline(always)] + pub fn osc32kctrl_(&self) -> OSC32KCTRL__R { + OSC32KCTRL__R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - SUPC APB Protect Enable"] + #[inline(always)] + pub fn supc_(&self) -> SUPC__R { + SUPC__R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - GCLK APB Protect Enable"] + #[inline(always)] + pub fn gclk_(&self) -> GCLK__R { + GCLK__R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - WDT APB Protect Enable"] + #[inline(always)] + pub fn wdt_(&self) -> WDT__R { + WDT__R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - RTC APB Protect Enable"] + #[inline(always)] + pub fn rtc_(&self) -> RTC__R { + RTC__R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - EIC APB Protect Enable"] + #[inline(always)] + pub fn eic_(&self) -> EIC__R { + EIC__R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - FREQM APB Protect Enable"] + #[inline(always)] + pub fn freqm_(&self) -> FREQM__R { + FREQM__R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - TSENS APB Protect Enable"] + #[inline(always)] + pub fn tsens_(&self) -> TSENS__R { + TSENS__R::new(((self.bits >> 12) & 0x01) != 0) + } +} +#[doc = "Peripheral write protection status - Bridge A\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [statusa](index.html) module"] +pub struct STATUSA_SPEC; +impl crate::RegisterSpec for STATUSA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [statusa::R](R) reader structure"] +impl crate::Readable for STATUSA_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUSA to value 0"] +impl crate::Resettable for STATUSA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/pac/statusb.rs b/pac/atsamc21n/src/pac/statusb.rs new file mode 100644 index 000000000000..a022cc2f1d54 --- /dev/null +++ b/pac/atsamc21n/src/pac/statusb.rs @@ -0,0 +1,153 @@ +#[doc = "Register `STATUSB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PORT_` reader - PORT APB Protect Enable"] +pub struct PORT__R(crate::FieldReader); +impl PORT__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PORT__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PORT__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DSU_` reader - DSU APB Protect Enable"] +pub struct DSU__R(crate::FieldReader); +impl DSU__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DSU__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DSU__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NVMCTRL_` reader - NVMCTRL APB Protect Enable"] +pub struct NVMCTRL__R(crate::FieldReader); +impl NVMCTRL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NVMCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NVMCTRL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DMAC_` reader - DMAC APB Protect Enable"] +pub struct DMAC__R(crate::FieldReader); +impl DMAC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DMAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DMAC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MTB_` reader - MTB APB Protect Enable"] +pub struct MTB__R(crate::FieldReader); +impl MTB__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MTB__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MTB__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HMATRIXHS_` reader - HMATRIXHS APB Protect Enable"] +pub struct HMATRIXHS__R(crate::FieldReader); +impl HMATRIXHS__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HMATRIXHS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HMATRIXHS__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - PORT APB Protect Enable"] + #[inline(always)] + pub fn port_(&self) -> PORT__R { + PORT__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - DSU APB Protect Enable"] + #[inline(always)] + pub fn dsu_(&self) -> DSU__R { + DSU__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - NVMCTRL APB Protect Enable"] + #[inline(always)] + pub fn nvmctrl_(&self) -> NVMCTRL__R { + NVMCTRL__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - DMAC APB Protect Enable"] + #[inline(always)] + pub fn dmac_(&self) -> DMAC__R { + DMAC__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - MTB APB Protect Enable"] + #[inline(always)] + pub fn mtb_(&self) -> MTB__R { + MTB__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - HMATRIXHS APB Protect Enable"] + #[inline(always)] + pub fn hmatrixhs_(&self) -> HMATRIXHS__R { + HMATRIXHS__R::new(((self.bits >> 5) & 0x01) != 0) + } +} +#[doc = "Peripheral write protection status - Bridge B\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [statusb](index.html) module"] +pub struct STATUSB_SPEC; +impl crate::RegisterSpec for STATUSB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [statusb::R](R) reader structure"] +impl crate::Readable for STATUSB_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUSB to value 0x02"] +impl crate::Resettable for STATUSB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x02 + } +} diff --git a/pac/atsamc21n/src/pac/statusc.rs b/pac/atsamc21n/src/pac/statusc.rs new file mode 100644 index 000000000000..8c986ef451bb --- /dev/null +++ b/pac/atsamc21n/src/pac/statusc.rs @@ -0,0 +1,513 @@ +#[doc = "Register `STATUSC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `EVSYS_` reader - EVSYS APB Protect Enable"] +pub struct EVSYS__R(crate::FieldReader); +impl EVSYS__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EVSYS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVSYS__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM0_` reader - SERCOM0 APB Protect Enable"] +pub struct SERCOM0__R(crate::FieldReader); +impl SERCOM0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM1_` reader - SERCOM1 APB Protect Enable"] +pub struct SERCOM1__R(crate::FieldReader); +impl SERCOM1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM2_` reader - SERCOM2 APB Protect Enable"] +pub struct SERCOM2__R(crate::FieldReader); +impl SERCOM2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM3_` reader - SERCOM3 APB Protect Enable"] +pub struct SERCOM3__R(crate::FieldReader); +impl SERCOM3__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM3__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM3__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM4_` reader - SERCOM4 APB Protect Enable"] +pub struct SERCOM4__R(crate::FieldReader); +impl SERCOM4__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM4__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM4__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM5_` reader - SERCOM5 APB Protect Enable"] +pub struct SERCOM5__R(crate::FieldReader); +impl SERCOM5__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM5__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM5__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAN0_` reader - CAN0 APB Protect Enable"] +pub struct CAN0__R(crate::FieldReader); +impl CAN0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CAN0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CAN0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAN1_` reader - CAN1 APB Protect Enable"] +pub struct CAN1__R(crate::FieldReader); +impl CAN1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CAN1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CAN1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCC0_` reader - TCC0 APB Protect Enable"] +pub struct TCC0__R(crate::FieldReader); +impl TCC0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCC0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCC0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCC1_` reader - TCC1 APB Protect Enable"] +pub struct TCC1__R(crate::FieldReader); +impl TCC1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCC1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCC1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCC2_` reader - TCC2 APB Protect Enable"] +pub struct TCC2__R(crate::FieldReader); +impl TCC2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCC2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCC2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC0_` reader - TC0 APB Protect Enable"] +pub struct TC0__R(crate::FieldReader); +impl TC0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC1_` reader - TC1 APB Protect Enable"] +pub struct TC1__R(crate::FieldReader); +impl TC1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC2_` reader - TC2 APB Protect Enable"] +pub struct TC2__R(crate::FieldReader); +impl TC2__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC2__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC3_` reader - TC3 APB Protect Enable"] +pub struct TC3__R(crate::FieldReader); +impl TC3__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC3__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC3__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC4_` reader - TC4 APB Protect Enable"] +pub struct TC4__R(crate::FieldReader); +impl TC4__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC4__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC4__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADC0_` reader - ADC0 APB Protect Enable"] +pub struct ADC0__R(crate::FieldReader); +impl ADC0__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ADC0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADC0__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADC1_` reader - ADC1 APB Protect Enable"] +pub struct ADC1__R(crate::FieldReader); +impl ADC1__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ADC1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADC1__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SDADC_` reader - SDADC APB Protect Enable"] +pub struct SDADC__R(crate::FieldReader); +impl SDADC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SDADC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SDADC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AC_` reader - AC APB Protect Enable"] +pub struct AC__R(crate::FieldReader); +impl AC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DAC_` reader - DAC APB Protect Enable"] +pub struct DAC__R(crate::FieldReader); +impl DAC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DAC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PTC_` reader - PTC APB Protect Enable"] +pub struct PTC__R(crate::FieldReader); +impl PTC__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PTC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PTC__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCL_` reader - CCL APB Protect Enable"] +pub struct CCL__R(crate::FieldReader); +impl CCL__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCL__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - EVSYS APB Protect Enable"] + #[inline(always)] + pub fn evsys_(&self) -> EVSYS__R { + EVSYS__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM0 APB Protect Enable"] + #[inline(always)] + pub fn sercom0_(&self) -> SERCOM0__R { + SERCOM0__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - SERCOM1 APB Protect Enable"] + #[inline(always)] + pub fn sercom1_(&self) -> SERCOM1__R { + SERCOM1__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - SERCOM2 APB Protect Enable"] + #[inline(always)] + pub fn sercom2_(&self) -> SERCOM2__R { + SERCOM2__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - SERCOM3 APB Protect Enable"] + #[inline(always)] + pub fn sercom3_(&self) -> SERCOM3__R { + SERCOM3__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - SERCOM4 APB Protect Enable"] + #[inline(always)] + pub fn sercom4_(&self) -> SERCOM4__R { + SERCOM4__R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - SERCOM5 APB Protect Enable"] + #[inline(always)] + pub fn sercom5_(&self) -> SERCOM5__R { + SERCOM5__R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - CAN0 APB Protect Enable"] + #[inline(always)] + pub fn can0_(&self) -> CAN0__R { + CAN0__R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - CAN1 APB Protect Enable"] + #[inline(always)] + pub fn can1_(&self) -> CAN1__R { + CAN1__R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - TCC0 APB Protect Enable"] + #[inline(always)] + pub fn tcc0_(&self) -> TCC0__R { + TCC0__R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - TCC1 APB Protect Enable"] + #[inline(always)] + pub fn tcc1_(&self) -> TCC1__R { + TCC1__R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - TCC2 APB Protect Enable"] + #[inline(always)] + pub fn tcc2_(&self) -> TCC2__R { + TCC2__R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - TC0 APB Protect Enable"] + #[inline(always)] + pub fn tc0_(&self) -> TC0__R { + TC0__R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - TC1 APB Protect Enable"] + #[inline(always)] + pub fn tc1_(&self) -> TC1__R { + TC1__R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - TC2 APB Protect Enable"] + #[inline(always)] + pub fn tc2_(&self) -> TC2__R { + TC2__R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - TC3 APB Protect Enable"] + #[inline(always)] + pub fn tc3_(&self) -> TC3__R { + TC3__R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - TC4 APB Protect Enable"] + #[inline(always)] + pub fn tc4_(&self) -> TC4__R { + TC4__R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - ADC0 APB Protect Enable"] + #[inline(always)] + pub fn adc0_(&self) -> ADC0__R { + ADC0__R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - ADC1 APB Protect Enable"] + #[inline(always)] + pub fn adc1_(&self) -> ADC1__R { + ADC1__R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - SDADC APB Protect Enable"] + #[inline(always)] + pub fn sdadc_(&self) -> SDADC__R { + SDADC__R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - AC APB Protect Enable"] + #[inline(always)] + pub fn ac_(&self) -> AC__R { + AC__R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - DAC APB Protect Enable"] + #[inline(always)] + pub fn dac_(&self) -> DAC__R { + DAC__R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - PTC APB Protect Enable"] + #[inline(always)] + pub fn ptc_(&self) -> PTC__R { + PTC__R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - CCL APB Protect Enable"] + #[inline(always)] + pub fn ccl_(&self) -> CCL__R { + CCL__R::new(((self.bits >> 23) & 0x01) != 0) + } +} +#[doc = "Peripheral write protection status - Bridge C\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [statusc](index.html) module"] +pub struct STATUSC_SPEC; +impl crate::RegisterSpec for STATUSC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [statusc::R](R) reader structure"] +impl crate::Readable for STATUSC_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUSC to value 0x0200_0000"] +impl crate::Resettable for STATUSC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0200_0000 + } +} diff --git a/pac/atsamc21n/src/pac/statusd.rs b/pac/atsamc21n/src/pac/statusd.rs new file mode 100644 index 000000000000..69c78dd013e1 --- /dev/null +++ b/pac/atsamc21n/src/pac/statusd.rs @@ -0,0 +1,133 @@ +#[doc = "Register `STATUSD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SERCOM6_` reader - SERCOM6 APB Protect Enable"] +pub struct SERCOM6__R(crate::FieldReader); +impl SERCOM6__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM6__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM6__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM7_` reader - SERCOM7 APB Protect Enable"] +pub struct SERCOM7__R(crate::FieldReader); +impl SERCOM7__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SERCOM7__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM7__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC5_` reader - TC5 APB Protect Enable"] +pub struct TC5__R(crate::FieldReader); +impl TC5__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC5__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC5__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC6_` reader - TC6 APB Protect Enable"] +pub struct TC6__R(crate::FieldReader); +impl TC6__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC6__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC6__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC7_` reader - TC7 APB Protect Enable"] +pub struct TC7__R(crate::FieldReader); +impl TC7__R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TC7__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC7__R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - SERCOM6 APB Protect Enable"] + #[inline(always)] + pub fn sercom6_(&self) -> SERCOM6__R { + SERCOM6__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM7 APB Protect Enable"] + #[inline(always)] + pub fn sercom7_(&self) -> SERCOM7__R { + SERCOM7__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - TC5 APB Protect Enable"] + #[inline(always)] + pub fn tc5_(&self) -> TC5__R { + TC5__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - TC6 APB Protect Enable"] + #[inline(always)] + pub fn tc6_(&self) -> TC6__R { + TC6__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - TC7 APB Protect Enable"] + #[inline(always)] + pub fn tc7_(&self) -> TC7__R { + TC7__R::new(((self.bits >> 4) & 0x01) != 0) + } +} +#[doc = "Peripheral write protection status - Bridge D\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [statusd](index.html) module"] +pub struct STATUSD_SPEC; +impl crate::RegisterSpec for STATUSD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [statusd::R](R) reader structure"] +impl crate::Readable for STATUSD_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUSD to value 0"] +impl crate::Resettable for STATUSD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/pac/wrctrl.rs b/pac/atsamc21n/src/pac/wrctrl.rs new file mode 100644 index 000000000000..65773ea08d64 --- /dev/null +++ b/pac/atsamc21n/src/pac/wrctrl.rs @@ -0,0 +1,215 @@ +#[doc = "Register `WRCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WRCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PERID` reader - Peripheral identifier"] +pub struct PERID_R(crate::FieldReader); +impl PERID_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + PERID_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERID_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERID` writer - Peripheral identifier"] +pub struct PERID_W<'a> { + w: &'a mut W, +} +impl<'a> PERID_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +#[doc = "Peripheral access control key\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum KEY_A { + #[doc = "0: No action"] + OFF = 0, + #[doc = "1: Clear protection"] + CLR = 1, + #[doc = "2: Set protection"] + SET = 2, + #[doc = "3: Set and lock protection"] + SETLCK = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: KEY_A) -> Self { + variant as _ + } +} +#[doc = "Field `KEY` reader - Peripheral access control key"] +pub struct KEY_R(crate::FieldReader); +impl KEY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + KEY_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(KEY_A::OFF), + 1 => Some(KEY_A::CLR), + 2 => Some(KEY_A::SET), + 3 => Some(KEY_A::SETLCK), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == KEY_A::OFF + } + #[doc = "Checks if the value of the field is `CLR`"] + #[inline(always)] + pub fn is_clr(&self) -> bool { + **self == KEY_A::CLR + } + #[doc = "Checks if the value of the field is `SET`"] + #[inline(always)] + pub fn is_set(&self) -> bool { + **self == KEY_A::SET + } + #[doc = "Checks if the value of the field is `SETLCK`"] + #[inline(always)] + pub fn is_setlck(&self) -> bool { + **self == KEY_A::SETLCK + } +} +impl core::ops::Deref for KEY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `KEY` writer - Peripheral access control key"] +pub struct KEY_W<'a> { + w: &'a mut W, +} +impl<'a> KEY_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: KEY_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(KEY_A::OFF) + } + #[doc = "Clear protection"] + #[inline(always)] + pub fn clr(self) -> &'a mut W { + self.variant(KEY_A::CLR) + } + #[doc = "Set protection"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(KEY_A::SET) + } + #[doc = "Set and lock protection"] + #[inline(always)] + pub fn setlck(self) -> &'a mut W { + self.variant(KEY_A::SETLCK) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Peripheral identifier"] + #[inline(always)] + pub fn perid(&self) -> PERID_R { + PERID_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:23 - Peripheral access control key"] + #[inline(always)] + pub fn key(&self) -> KEY_R { + KEY_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:15 - Peripheral identifier"] + #[inline(always)] + pub fn perid(&mut self) -> PERID_W { + PERID_W { w: self } + } + #[doc = "Bits 16:23 - Peripheral access control key"] + #[inline(always)] + pub fn key(&mut self) -> KEY_W { + KEY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Write control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wrctrl](index.html) module"] +pub struct WRCTRL_SPEC; +impl crate::RegisterSpec for WRCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [wrctrl::R](R) reader structure"] +impl crate::Readable for WRCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wrctrl::W](W) writer structure"] +impl crate::Writable for WRCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WRCTRL to value 0"] +impl crate::Resettable for WRCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/pm.rs b/pac/atsamc21n/src/pm.rs new file mode 100644 index 000000000000..9da2b0e13288 --- /dev/null +++ b/pac/atsamc21n/src/pm.rs @@ -0,0 +1,18 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved0: [u8; 0x01], + #[doc = "0x01 - Sleep Configuration"] + pub sleepcfg: crate::Reg, + _reserved1: [u8; 0x06], + #[doc = "0x08 - Standby Configuration"] + pub stdbycfg: crate::Reg, +} +#[doc = "SLEEPCFG register accessor: an alias for `Reg`"] +pub type SLEEPCFG = crate::Reg; +#[doc = "Sleep Configuration"] +pub mod sleepcfg; +#[doc = "STDBYCFG register accessor: an alias for `Reg`"] +pub type STDBYCFG = crate::Reg; +#[doc = "Standby Configuration"] +pub mod stdbycfg; diff --git a/pac/atsamc21n/src/pm/sleepcfg.rs b/pac/atsamc21n/src/pm/sleepcfg.rs new file mode 100644 index 000000000000..9ff91fdee046 --- /dev/null +++ b/pac/atsamc21n/src/pm/sleepcfg.rs @@ -0,0 +1,204 @@ +#[doc = "Register `SLEEPCFG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SLEEPCFG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Sleep Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SLEEPMODE_A { + #[doc = "0: CPU clock is OFF"] + IDLE0 = 0, + #[doc = "1: AHB clock is OFF"] + IDLE1 = 1, + #[doc = "2: APB clock are OFF"] + IDLE2 = 2, + #[doc = "4: All Clocks are OFF"] + STANDBY = 4, + #[doc = "5: Only Backup domain is powered ON"] + BACKUP = 5, + #[doc = "6: All power domains are powered OFF"] + OFF = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SLEEPMODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `SLEEPMODE` reader - Sleep Mode"] +pub struct SLEEPMODE_R(crate::FieldReader); +impl SLEEPMODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SLEEPMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SLEEPMODE_A::IDLE0), + 1 => Some(SLEEPMODE_A::IDLE1), + 2 => Some(SLEEPMODE_A::IDLE2), + 4 => Some(SLEEPMODE_A::STANDBY), + 5 => Some(SLEEPMODE_A::BACKUP), + 6 => Some(SLEEPMODE_A::OFF), + _ => None, + } + } + #[doc = "Checks if the value of the field is `IDLE0`"] + #[inline(always)] + pub fn is_idle0(&self) -> bool { + **self == SLEEPMODE_A::IDLE0 + } + #[doc = "Checks if the value of the field is `IDLE1`"] + #[inline(always)] + pub fn is_idle1(&self) -> bool { + **self == SLEEPMODE_A::IDLE1 + } + #[doc = "Checks if the value of the field is `IDLE2`"] + #[inline(always)] + pub fn is_idle2(&self) -> bool { + **self == SLEEPMODE_A::IDLE2 + } + #[doc = "Checks if the value of the field is `STANDBY`"] + #[inline(always)] + pub fn is_standby(&self) -> bool { + **self == SLEEPMODE_A::STANDBY + } + #[doc = "Checks if the value of the field is `BACKUP`"] + #[inline(always)] + pub fn is_backup(&self) -> bool { + **self == SLEEPMODE_A::BACKUP + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == SLEEPMODE_A::OFF + } +} +impl core::ops::Deref for SLEEPMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLEEPMODE` writer - Sleep Mode"] +pub struct SLEEPMODE_W<'a> { + w: &'a mut W, +} +impl<'a> SLEEPMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SLEEPMODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "CPU clock is OFF"] + #[inline(always)] + pub fn idle0(self) -> &'a mut W { + self.variant(SLEEPMODE_A::IDLE0) + } + #[doc = "AHB clock is OFF"] + #[inline(always)] + pub fn idle1(self) -> &'a mut W { + self.variant(SLEEPMODE_A::IDLE1) + } + #[doc = "APB clock are OFF"] + #[inline(always)] + pub fn idle2(self) -> &'a mut W { + self.variant(SLEEPMODE_A::IDLE2) + } + #[doc = "All Clocks are OFF"] + #[inline(always)] + pub fn standby(self) -> &'a mut W { + self.variant(SLEEPMODE_A::STANDBY) + } + #[doc = "Only Backup domain is powered ON"] + #[inline(always)] + pub fn backup(self) -> &'a mut W { + self.variant(SLEEPMODE_A::BACKUP) + } + #[doc = "All power domains are powered OFF"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(SLEEPMODE_A::OFF) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Sleep Mode"] + #[inline(always)] + pub fn sleepmode(&self) -> SLEEPMODE_R { + SLEEPMODE_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Sleep Mode"] + #[inline(always)] + pub fn sleepmode(&mut self) -> SLEEPMODE_W { + SLEEPMODE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Sleep Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sleepcfg](index.html) module"] +pub struct SLEEPCFG_SPEC; +impl crate::RegisterSpec for SLEEPCFG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [sleepcfg::R](R) reader structure"] +impl crate::Readable for SLEEPCFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [sleepcfg::W](W) writer structure"] +impl crate::Writable for SLEEPCFG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SLEEPCFG to value 0"] +impl crate::Resettable for SLEEPCFG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/pm/stdbycfg.rs b/pac/atsamc21n/src/pm/stdbycfg.rs new file mode 100644 index 000000000000..9be67f240062 --- /dev/null +++ b/pac/atsamc21n/src/pm/stdbycfg.rs @@ -0,0 +1,202 @@ +#[doc = "Register `STDBYCFG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STDBYCFG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Voltage Regulator Standby mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum VREGSMOD_A { + #[doc = "0: Automatic mode"] + AUTO = 0, + #[doc = "1: Performance oriented"] + PERFORMANCE = 1, + #[doc = "2: Low Power oriented"] + LP = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: VREGSMOD_A) -> Self { + variant as _ + } +} +#[doc = "Field `VREGSMOD` reader - Voltage Regulator Standby mode"] +pub struct VREGSMOD_R(crate::FieldReader); +impl VREGSMOD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + VREGSMOD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(VREGSMOD_A::AUTO), + 1 => Some(VREGSMOD_A::PERFORMANCE), + 2 => Some(VREGSMOD_A::LP), + _ => None, + } + } + #[doc = "Checks if the value of the field is `AUTO`"] + #[inline(always)] + pub fn is_auto(&self) -> bool { + **self == VREGSMOD_A::AUTO + } + #[doc = "Checks if the value of the field is `PERFORMANCE`"] + #[inline(always)] + pub fn is_performance(&self) -> bool { + **self == VREGSMOD_A::PERFORMANCE + } + #[doc = "Checks if the value of the field is `LP`"] + #[inline(always)] + pub fn is_lp(&self) -> bool { + **self == VREGSMOD_A::LP + } +} +impl core::ops::Deref for VREGSMOD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VREGSMOD` writer - Voltage Regulator Standby mode"] +pub struct VREGSMOD_W<'a> { + w: &'a mut W, +} +impl<'a> VREGSMOD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: VREGSMOD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Automatic mode"] + #[inline(always)] + pub fn auto(self) -> &'a mut W { + self.variant(VREGSMOD_A::AUTO) + } + #[doc = "Performance oriented"] + #[inline(always)] + pub fn performance(self) -> &'a mut W { + self.variant(VREGSMOD_A::PERFORMANCE) + } + #[doc = "Low Power oriented"] + #[inline(always)] + pub fn lp(self) -> &'a mut W { + self.variant(VREGSMOD_A::LP) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 6)) | ((value as u16 & 0x03) << 6); + self.w + } +} +#[doc = "Field `BBIASHS` reader - Back Bias for HMCRAMCHS"] +pub struct BBIASHS_R(crate::FieldReader); +impl BBIASHS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BBIASHS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BBIASHS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BBIASHS` writer - Back Bias for HMCRAMCHS"] +pub struct BBIASHS_W<'a> { + w: &'a mut W, +} +impl<'a> BBIASHS_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 10)) | ((value as u16 & 0x03) << 10); + self.w + } +} +impl R { + #[doc = "Bits 6:7 - Voltage Regulator Standby mode"] + #[inline(always)] + pub fn vregsmod(&self) -> VREGSMOD_R { + VREGSMOD_R::new(((self.bits >> 6) & 0x03) as u8) + } + #[doc = "Bits 10:11 - Back Bias for HMCRAMCHS"] + #[inline(always)] + pub fn bbiashs(&self) -> BBIASHS_R { + BBIASHS_R::new(((self.bits >> 10) & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 6:7 - Voltage Regulator Standby mode"] + #[inline(always)] + pub fn vregsmod(&mut self) -> VREGSMOD_W { + VREGSMOD_W { w: self } + } + #[doc = "Bits 10:11 - Back Bias for HMCRAMCHS"] + #[inline(always)] + pub fn bbiashs(&mut self) -> BBIASHS_W { + BBIASHS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Standby Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [stdbycfg](index.html) module"] +pub struct STDBYCFG_SPEC; +impl crate::RegisterSpec for STDBYCFG_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [stdbycfg::R](R) reader structure"] +impl crate::Readable for STDBYCFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [stdbycfg::W](W) writer structure"] +impl crate::Writable for STDBYCFG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STDBYCFG to value 0x0400"] +impl crate::Resettable for STDBYCFG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0400 + } +} diff --git a/pac/atsamc21n/src/port.rs b/pac/atsamc21n/src/port.rs new file mode 100644 index 000000000000..b901dd415a91 --- /dev/null +++ b/pac/atsamc21n/src/port.rs @@ -0,0 +1,47 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00..0x60 - GROUP\\[%s\\]"] + pub group0: GROUP, + _reserved1: [u8; 0x20], + #[doc = "0x80..0xe0 - GROUP\\[%s\\]"] + pub group1: GROUP, + _reserved2: [u8; 0x20], + #[doc = "0x100..0x160 - GROUP\\[%s\\]"] + pub group2: GROUP, +} +#[doc = r"Register block"] +#[repr(C)] +pub struct GROUP { + #[doc = "0x00 - Data Direction"] + pub dir: crate::Reg, + #[doc = "0x04 - Data Direction Clear"] + pub dirclr: crate::Reg, + #[doc = "0x08 - Data Direction Set"] + pub dirset: crate::Reg, + #[doc = "0x0c - Data Direction Toggle"] + pub dirtgl: crate::Reg, + #[doc = "0x10 - Data Output Value"] + pub out: crate::Reg, + #[doc = "0x14 - Data Output Value Clear"] + pub outclr: crate::Reg, + #[doc = "0x18 - Data Output Value Set"] + pub outset: crate::Reg, + #[doc = "0x1c - Data Output Value Toggle"] + pub outtgl: crate::Reg, + #[doc = "0x20 - Data Input Value"] + pub in_: crate::Reg, + #[doc = "0x24 - Control"] + pub ctrl: crate::Reg, + #[doc = "0x28 - Write Configuration"] + pub wrconfig: crate::Reg, + #[doc = "0x2c - Event Input Control"] + pub evctrl: crate::Reg, + #[doc = "0x30..0x40 - Peripheral Multiplexing n"] + pub pmux: [crate::Reg; 16], + #[doc = "0x40..0x60 - Pin Configuration n"] + pub pincfg: [crate::Reg; 32], +} +#[doc = r"Register block"] +#[doc = "GROUP\\[%s\\]"] +pub mod group; diff --git a/pac/atsamc21n/src/port/group.rs b/pac/atsamc21n/src/port/group.rs new file mode 100644 index 000000000000..d1aabcd73380 --- /dev/null +++ b/pac/atsamc21n/src/port/group.rs @@ -0,0 +1,56 @@ +#[doc = "DIR register accessor: an alias for `Reg`"] +pub type DIR = crate::Reg; +#[doc = "Data Direction"] +pub mod dir; +#[doc = "DIRCLR register accessor: an alias for `Reg`"] +pub type DIRCLR = crate::Reg; +#[doc = "Data Direction Clear"] +pub mod dirclr; +#[doc = "DIRSET register accessor: an alias for `Reg`"] +pub type DIRSET = crate::Reg; +#[doc = "Data Direction Set"] +pub mod dirset; +#[doc = "DIRTGL register accessor: an alias for `Reg`"] +pub type DIRTGL = crate::Reg; +#[doc = "Data Direction Toggle"] +pub mod dirtgl; +#[doc = "OUT register accessor: an alias for `Reg`"] +pub type OUT = crate::Reg; +#[doc = "Data Output Value"] +pub mod out; +#[doc = "OUTCLR register accessor: an alias for `Reg`"] +pub type OUTCLR = crate::Reg; +#[doc = "Data Output Value Clear"] +pub mod outclr; +#[doc = "OUTSET register accessor: an alias for `Reg`"] +pub type OUTSET = crate::Reg; +#[doc = "Data Output Value Set"] +pub mod outset; +#[doc = "OUTTGL register accessor: an alias for `Reg`"] +pub type OUTTGL = crate::Reg; +#[doc = "Data Output Value Toggle"] +pub mod outtgl; +#[doc = "IN register accessor: an alias for `Reg`"] +pub type IN = crate::Reg; +#[doc = "Data Input Value"] +pub mod in_; +#[doc = "CTRL register accessor: an alias for `Reg`"] +pub type CTRL = crate::Reg; +#[doc = "Control"] +pub mod ctrl; +#[doc = "WRCONFIG register accessor: an alias for `Reg`"] +pub type WRCONFIG = crate::Reg; +#[doc = "Write Configuration"] +pub mod wrconfig; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Input Control"] +pub mod evctrl; +#[doc = "PMUX register accessor: an alias for `Reg`"] +pub type PMUX = crate::Reg; +#[doc = "Peripheral Multiplexing n"] +pub mod pmux; +#[doc = "PINCFG register accessor: an alias for `Reg`"] +pub type PINCFG = crate::Reg; +#[doc = "Pin Configuration n"] +pub mod pincfg; diff --git a/pac/atsamc21n/src/port/group/ctrl.rs b/pac/atsamc21n/src/port/group/ctrl.rs new file mode 100644 index 000000000000..4b57cd6fcd2b --- /dev/null +++ b/pac/atsamc21n/src/port/group/ctrl.rs @@ -0,0 +1,103 @@ +#[doc = "Register `CTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SAMPLING` reader - Input Sampling Mode"] +pub struct SAMPLING_R(crate::FieldReader); +impl SAMPLING_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + SAMPLING_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SAMPLING_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SAMPLING` writer - Input Sampling Mode"] +pub struct SAMPLING_W<'a> { + w: &'a mut W, +} +impl<'a> SAMPLING_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Input Sampling Mode"] + #[inline(always)] + pub fn sampling(&self) -> SAMPLING_R { + SAMPLING_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Input Sampling Mode"] + #[inline(always)] + pub fn sampling(&mut self) -> SAMPLING_W { + SAMPLING_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"] +pub struct CTRL_SPEC; +impl crate::RegisterSpec for CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrl::R](R) reader structure"] +impl crate::Readable for CTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"] +impl crate::Writable for CTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/port/group/dir.rs b/pac/atsamc21n/src/port/group/dir.rs new file mode 100644 index 000000000000..e04452fb5d35 --- /dev/null +++ b/pac/atsamc21n/src/port/group/dir.rs @@ -0,0 +1,64 @@ +#[doc = "Register `DIR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Direction\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dir](index.html) module"] +pub struct DIR_SPEC; +impl crate::RegisterSpec for DIR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dir::R](R) reader structure"] +impl crate::Readable for DIR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dir::W](W) writer structure"] +impl crate::Writable for DIR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DIR to value 0"] +impl crate::Resettable for DIR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/port/group/dirclr.rs b/pac/atsamc21n/src/port/group/dirclr.rs new file mode 100644 index 000000000000..5e6d73d032b2 --- /dev/null +++ b/pac/atsamc21n/src/port/group/dirclr.rs @@ -0,0 +1,64 @@ +#[doc = "Register `DIRCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIRCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Direction Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dirclr](index.html) module"] +pub struct DIRCLR_SPEC; +impl crate::RegisterSpec for DIRCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dirclr::R](R) reader structure"] +impl crate::Readable for DIRCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dirclr::W](W) writer structure"] +impl crate::Writable for DIRCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DIRCLR to value 0"] +impl crate::Resettable for DIRCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/port/group/dirset.rs b/pac/atsamc21n/src/port/group/dirset.rs new file mode 100644 index 000000000000..eaa86e14f15d --- /dev/null +++ b/pac/atsamc21n/src/port/group/dirset.rs @@ -0,0 +1,64 @@ +#[doc = "Register `DIRSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIRSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Direction Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dirset](index.html) module"] +pub struct DIRSET_SPEC; +impl crate::RegisterSpec for DIRSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dirset::R](R) reader structure"] +impl crate::Readable for DIRSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dirset::W](W) writer structure"] +impl crate::Writable for DIRSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DIRSET to value 0"] +impl crate::Resettable for DIRSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/port/group/dirtgl.rs b/pac/atsamc21n/src/port/group/dirtgl.rs new file mode 100644 index 000000000000..fbd021438b1b --- /dev/null +++ b/pac/atsamc21n/src/port/group/dirtgl.rs @@ -0,0 +1,64 @@ +#[doc = "Register `DIRTGL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIRTGL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Direction Toggle\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dirtgl](index.html) module"] +pub struct DIRTGL_SPEC; +impl crate::RegisterSpec for DIRTGL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dirtgl::R](R) reader structure"] +impl crate::Readable for DIRTGL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dirtgl::W](W) writer structure"] +impl crate::Writable for DIRTGL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DIRTGL to value 0"] +impl crate::Resettable for DIRTGL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/port/group/evctrl.rs b/pac/atsamc21n/src/port/group/evctrl.rs new file mode 100644 index 000000000000..ef0a35987f3d --- /dev/null +++ b/pac/atsamc21n/src/port/group/evctrl.rs @@ -0,0 +1,625 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PID0` reader - Port Event Pin Identifier 0"] +pub struct PID0_R(crate::FieldReader); +impl PID0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PID0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PID0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PID0` writer - Port Event Pin Identifier 0"] +pub struct PID0_W<'a> { + w: &'a mut W, +} +impl<'a> PID0_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f); + self.w + } +} +#[doc = "Port Event Action 0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EVACT0_A { + #[doc = "0: Event output to pin"] + OUT = 0, + #[doc = "1: Set output register of pin on event"] + SET = 1, + #[doc = "2: Clear output register of pin on event"] + CLR = 2, + #[doc = "3: Toggle output register of pin on event"] + TGL = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EVACT0_A) -> Self { + variant as _ + } +} +#[doc = "Field `EVACT0` reader - Port Event Action 0"] +pub struct EVACT0_R(crate::FieldReader); +impl EVACT0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVACT0_A { + match self.bits { + 0 => EVACT0_A::OUT, + 1 => EVACT0_A::SET, + 2 => EVACT0_A::CLR, + 3 => EVACT0_A::TGL, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `OUT`"] + #[inline(always)] + pub fn is_out(&self) -> bool { + **self == EVACT0_A::OUT + } + #[doc = "Checks if the value of the field is `SET`"] + #[inline(always)] + pub fn is_set(&self) -> bool { + **self == EVACT0_A::SET + } + #[doc = "Checks if the value of the field is `CLR`"] + #[inline(always)] + pub fn is_clr(&self) -> bool { + **self == EVACT0_A::CLR + } + #[doc = "Checks if the value of the field is `TGL`"] + #[inline(always)] + pub fn is_tgl(&self) -> bool { + **self == EVACT0_A::TGL + } +} +impl core::ops::Deref for EVACT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT0` writer - Port Event Action 0"] +pub struct EVACT0_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT0_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EVACT0_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Event output to pin"] + #[inline(always)] + pub fn out(self) -> &'a mut W { + self.variant(EVACT0_A::OUT) + } + #[doc = "Set output register of pin on event"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(EVACT0_A::SET) + } + #[doc = "Clear output register of pin on event"] + #[inline(always)] + pub fn clr(self) -> &'a mut W { + self.variant(EVACT0_A::CLR) + } + #[doc = "Toggle output register of pin on event"] + #[inline(always)] + pub fn tgl(self) -> &'a mut W { + self.variant(EVACT0_A::TGL) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 5)) | ((value as u32 & 0x03) << 5); + self.w + } +} +#[doc = "Field `PORTEI0` reader - Port Event Enable Input 0"] +pub struct PORTEI0_R(crate::FieldReader); +impl PORTEI0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PORTEI0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PORTEI0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PORTEI0` writer - Port Event Enable Input 0"] +pub struct PORTEI0_W<'a> { + w: &'a mut W, +} +impl<'a> PORTEI0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `PID1` reader - Port Event Pin Identifier 1"] +pub struct PID1_R(crate::FieldReader); +impl PID1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PID1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PID1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PID1` writer - Port Event Pin Identifier 1"] +pub struct PID1_W<'a> { + w: &'a mut W, +} +impl<'a> PID1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 8)) | ((value as u32 & 0x1f) << 8); + self.w + } +} +#[doc = "Field `EVACT1` reader - Port Event Action 1"] +pub struct EVACT1_R(crate::FieldReader); +impl EVACT1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVACT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT1` writer - Port Event Action 1"] +pub struct EVACT1_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 13)) | ((value as u32 & 0x03) << 13); + self.w + } +} +#[doc = "Field `PORTEI1` reader - Port Event Enable Input 1"] +pub struct PORTEI1_R(crate::FieldReader); +impl PORTEI1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PORTEI1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PORTEI1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PORTEI1` writer - Port Event Enable Input 1"] +pub struct PORTEI1_W<'a> { + w: &'a mut W, +} +impl<'a> PORTEI1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `PID2` reader - Port Event Pin Identifier 2"] +pub struct PID2_R(crate::FieldReader); +impl PID2_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PID2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PID2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PID2` writer - Port Event Pin Identifier 2"] +pub struct PID2_W<'a> { + w: &'a mut W, +} +impl<'a> PID2_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 16)) | ((value as u32 & 0x1f) << 16); + self.w + } +} +#[doc = "Field `EVACT2` reader - Port Event Action 2"] +pub struct EVACT2_R(crate::FieldReader); +impl EVACT2_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVACT2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT2` writer - Port Event Action 2"] +pub struct EVACT2_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT2_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 21)) | ((value as u32 & 0x03) << 21); + self.w + } +} +#[doc = "Field `PORTEI2` reader - Port Event Enable Input 2"] +pub struct PORTEI2_R(crate::FieldReader); +impl PORTEI2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PORTEI2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PORTEI2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PORTEI2` writer - Port Event Enable Input 2"] +pub struct PORTEI2_W<'a> { + w: &'a mut W, +} +impl<'a> PORTEI2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `PID3` reader - Port Event Pin Identifier 3"] +pub struct PID3_R(crate::FieldReader); +impl PID3_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PID3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PID3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PID3` writer - Port Event Pin Identifier 3"] +pub struct PID3_W<'a> { + w: &'a mut W, +} +impl<'a> PID3_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 24)) | ((value as u32 & 0x1f) << 24); + self.w + } +} +#[doc = "Field `EVACT3` reader - Port Event Action 3"] +pub struct EVACT3_R(crate::FieldReader); +impl EVACT3_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVACT3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT3` writer - Port Event Action 3"] +pub struct EVACT3_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT3_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 29)) | ((value as u32 & 0x03) << 29); + self.w + } +} +#[doc = "Field `PORTEI3` reader - Port Event Enable Input 3"] +pub struct PORTEI3_R(crate::FieldReader); +impl PORTEI3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PORTEI3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PORTEI3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PORTEI3` writer - Port Event Enable Input 3"] +pub struct PORTEI3_W<'a> { + w: &'a mut W, +} +impl<'a> PORTEI3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Port Event Pin Identifier 0"] + #[inline(always)] + pub fn pid0(&self) -> PID0_R { + PID0_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:6 - Port Event Action 0"] + #[inline(always)] + pub fn evact0(&self) -> EVACT0_R { + EVACT0_R::new(((self.bits >> 5) & 0x03) as u8) + } + #[doc = "Bit 7 - Port Event Enable Input 0"] + #[inline(always)] + pub fn portei0(&self) -> PORTEI0_R { + PORTEI0_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:12 - Port Event Pin Identifier 1"] + #[inline(always)] + pub fn pid1(&self) -> PID1_R { + PID1_R::new(((self.bits >> 8) & 0x1f) as u8) + } + #[doc = "Bits 13:14 - Port Event Action 1"] + #[inline(always)] + pub fn evact1(&self) -> EVACT1_R { + EVACT1_R::new(((self.bits >> 13) & 0x03) as u8) + } + #[doc = "Bit 15 - Port Event Enable Input 1"] + #[inline(always)] + pub fn portei1(&self) -> PORTEI1_R { + PORTEI1_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:20 - Port Event Pin Identifier 2"] + #[inline(always)] + pub fn pid2(&self) -> PID2_R { + PID2_R::new(((self.bits >> 16) & 0x1f) as u8) + } + #[doc = "Bits 21:22 - Port Event Action 2"] + #[inline(always)] + pub fn evact2(&self) -> EVACT2_R { + EVACT2_R::new(((self.bits >> 21) & 0x03) as u8) + } + #[doc = "Bit 23 - Port Event Enable Input 2"] + #[inline(always)] + pub fn portei2(&self) -> PORTEI2_R { + PORTEI2_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bits 24:28 - Port Event Pin Identifier 3"] + #[inline(always)] + pub fn pid3(&self) -> PID3_R { + PID3_R::new(((self.bits >> 24) & 0x1f) as u8) + } + #[doc = "Bits 29:30 - Port Event Action 3"] + #[inline(always)] + pub fn evact3(&self) -> EVACT3_R { + EVACT3_R::new(((self.bits >> 29) & 0x03) as u8) + } + #[doc = "Bit 31 - Port Event Enable Input 3"] + #[inline(always)] + pub fn portei3(&self) -> PORTEI3_R { + PORTEI3_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Port Event Pin Identifier 0"] + #[inline(always)] + pub fn pid0(&mut self) -> PID0_W { + PID0_W { w: self } + } + #[doc = "Bits 5:6 - Port Event Action 0"] + #[inline(always)] + pub fn evact0(&mut self) -> EVACT0_W { + EVACT0_W { w: self } + } + #[doc = "Bit 7 - Port Event Enable Input 0"] + #[inline(always)] + pub fn portei0(&mut self) -> PORTEI0_W { + PORTEI0_W { w: self } + } + #[doc = "Bits 8:12 - Port Event Pin Identifier 1"] + #[inline(always)] + pub fn pid1(&mut self) -> PID1_W { + PID1_W { w: self } + } + #[doc = "Bits 13:14 - Port Event Action 1"] + #[inline(always)] + pub fn evact1(&mut self) -> EVACT1_W { + EVACT1_W { w: self } + } + #[doc = "Bit 15 - Port Event Enable Input 1"] + #[inline(always)] + pub fn portei1(&mut self) -> PORTEI1_W { + PORTEI1_W { w: self } + } + #[doc = "Bits 16:20 - Port Event Pin Identifier 2"] + #[inline(always)] + pub fn pid2(&mut self) -> PID2_W { + PID2_W { w: self } + } + #[doc = "Bits 21:22 - Port Event Action 2"] + #[inline(always)] + pub fn evact2(&mut self) -> EVACT2_W { + EVACT2_W { w: self } + } + #[doc = "Bit 23 - Port Event Enable Input 2"] + #[inline(always)] + pub fn portei2(&mut self) -> PORTEI2_W { + PORTEI2_W { w: self } + } + #[doc = "Bits 24:28 - Port Event Pin Identifier 3"] + #[inline(always)] + pub fn pid3(&mut self) -> PID3_W { + PID3_W { w: self } + } + #[doc = "Bits 29:30 - Port Event Action 3"] + #[inline(always)] + pub fn evact3(&mut self) -> EVACT3_W { + EVACT3_W { w: self } + } + #[doc = "Bit 31 - Port Event Enable Input 3"] + #[inline(always)] + pub fn portei3(&mut self) -> PORTEI3_W { + PORTEI3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Input Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/port/group/in_.rs b/pac/atsamc21n/src/port/group/in_.rs new file mode 100644 index 000000000000..1c8e7396a83e --- /dev/null +++ b/pac/atsamc21n/src/port/group/in_.rs @@ -0,0 +1,31 @@ +#[doc = "Register `IN` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Data Input Value\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [in_](index.html) module"] +pub struct IN_SPEC; +impl crate::RegisterSpec for IN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [in_::R](R) reader structure"] +impl crate::Readable for IN_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets IN to value 0"] +impl crate::Resettable for IN_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/port/group/out.rs b/pac/atsamc21n/src/port/group/out.rs new file mode 100644 index 000000000000..092e8dbd8023 --- /dev/null +++ b/pac/atsamc21n/src/port/group/out.rs @@ -0,0 +1,64 @@ +#[doc = "Register `OUT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OUT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Output Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [out](index.html) module"] +pub struct OUT_SPEC; +impl crate::RegisterSpec for OUT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [out::R](R) reader structure"] +impl crate::Readable for OUT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [out::W](W) writer structure"] +impl crate::Writable for OUT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OUT to value 0"] +impl crate::Resettable for OUT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/port/group/outclr.rs b/pac/atsamc21n/src/port/group/outclr.rs new file mode 100644 index 000000000000..6e734396601f --- /dev/null +++ b/pac/atsamc21n/src/port/group/outclr.rs @@ -0,0 +1,64 @@ +#[doc = "Register `OUTCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OUTCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Output Value Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [outclr](index.html) module"] +pub struct OUTCLR_SPEC; +impl crate::RegisterSpec for OUTCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [outclr::R](R) reader structure"] +impl crate::Readable for OUTCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [outclr::W](W) writer structure"] +impl crate::Writable for OUTCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OUTCLR to value 0"] +impl crate::Resettable for OUTCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/port/group/outset.rs b/pac/atsamc21n/src/port/group/outset.rs new file mode 100644 index 000000000000..6d39122deb4b --- /dev/null +++ b/pac/atsamc21n/src/port/group/outset.rs @@ -0,0 +1,64 @@ +#[doc = "Register `OUTSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OUTSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Output Value Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [outset](index.html) module"] +pub struct OUTSET_SPEC; +impl crate::RegisterSpec for OUTSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [outset::R](R) reader structure"] +impl crate::Readable for OUTSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [outset::W](W) writer structure"] +impl crate::Writable for OUTSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OUTSET to value 0"] +impl crate::Resettable for OUTSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/port/group/outtgl.rs b/pac/atsamc21n/src/port/group/outtgl.rs new file mode 100644 index 000000000000..0f3d87d6476d --- /dev/null +++ b/pac/atsamc21n/src/port/group/outtgl.rs @@ -0,0 +1,64 @@ +#[doc = "Register `OUTTGL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OUTTGL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Output Value Toggle\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [outtgl](index.html) module"] +pub struct OUTTGL_SPEC; +impl crate::RegisterSpec for OUTTGL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [outtgl::R](R) reader structure"] +impl crate::Readable for OUTTGL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [outtgl::W](W) writer structure"] +impl crate::Writable for OUTTGL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OUTTGL to value 0"] +impl crate::Resettable for OUTTGL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/port/group/pincfg.rs b/pac/atsamc21n/src/port/group/pincfg.rs new file mode 100644 index 000000000000..920af6550361 --- /dev/null +++ b/pac/atsamc21n/src/port/group/pincfg.rs @@ -0,0 +1,255 @@ +#[doc = "Register `PINCFG[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PINCFG[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PMUXEN` reader - Select Peripheral Multiplexer"] +pub struct PMUXEN_R(crate::FieldReader); +impl PMUXEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PMUXEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PMUXEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PMUXEN` writer - Select Peripheral Multiplexer"] +pub struct PMUXEN_W<'a> { + w: &'a mut W, +} +impl<'a> PMUXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `INEN` reader - Input Enable"] +pub struct INEN_R(crate::FieldReader); +impl INEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INEN` writer - Input Enable"] +pub struct INEN_W<'a> { + w: &'a mut W, +} +impl<'a> INEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PULLEN` reader - Pull Enable"] +pub struct PULLEN_R(crate::FieldReader); +impl PULLEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PULLEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PULLEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PULLEN` writer - Pull Enable"] +pub struct PULLEN_W<'a> { + w: &'a mut W, +} +impl<'a> PULLEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `DRVSTR` reader - Output Driver Strength Selection"] +pub struct DRVSTR_R(crate::FieldReader); +impl DRVSTR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRVSTR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRVSTR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRVSTR` writer - Output Driver Strength Selection"] +pub struct DRVSTR_W<'a> { + w: &'a mut W, +} +impl<'a> DRVSTR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - Select Peripheral Multiplexer"] + #[inline(always)] + pub fn pmuxen(&self) -> PMUXEN_R { + PMUXEN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Input Enable"] + #[inline(always)] + pub fn inen(&self) -> INEN_R { + INEN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Pull Enable"] + #[inline(always)] + pub fn pullen(&self) -> PULLEN_R { + PULLEN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 6 - Output Driver Strength Selection"] + #[inline(always)] + pub fn drvstr(&self) -> DRVSTR_R { + DRVSTR_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Select Peripheral Multiplexer"] + #[inline(always)] + pub fn pmuxen(&mut self) -> PMUXEN_W { + PMUXEN_W { w: self } + } + #[doc = "Bit 1 - Input Enable"] + #[inline(always)] + pub fn inen(&mut self) -> INEN_W { + INEN_W { w: self } + } + #[doc = "Bit 2 - Pull Enable"] + #[inline(always)] + pub fn pullen(&mut self) -> PULLEN_W { + PULLEN_W { w: self } + } + #[doc = "Bit 6 - Output Driver Strength Selection"] + #[inline(always)] + pub fn drvstr(&mut self) -> DRVSTR_W { + DRVSTR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Pin Configuration n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pincfg](index.html) module"] +pub struct PINCFG_SPEC; +impl crate::RegisterSpec for PINCFG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [pincfg::R](R) reader structure"] +impl crate::Readable for PINCFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [pincfg::W](W) writer structure"] +impl crate::Writable for PINCFG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PINCFG[%s] +to value 0"] +impl crate::Resettable for PINCFG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/port/group/pmux.rs b/pac/atsamc21n/src/port/group/pmux.rs new file mode 100644 index 000000000000..79c991a99daf --- /dev/null +++ b/pac/atsamc21n/src/port/group/pmux.rs @@ -0,0 +1,141 @@ +#[doc = "Register `PMUX[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PMUX[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PMUXE` reader - Peripheral Multiplexing for Even-Numbered Pin"] +pub struct PMUXE_R(crate::FieldReader); +impl PMUXE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PMUXE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PMUXE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PMUXE` writer - Peripheral Multiplexing for Even-Numbered Pin"] +pub struct PMUXE_W<'a> { + w: &'a mut W, +} +impl<'a> PMUXE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +#[doc = "Field `PMUXO` reader - Peripheral Multiplexing for Odd-Numbered Pin"] +pub struct PMUXO_R(crate::FieldReader); +impl PMUXO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PMUXO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PMUXO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PMUXO` writer - Peripheral Multiplexing for Odd-Numbered Pin"] +pub struct PMUXO_W<'a> { + w: &'a mut W, +} +impl<'a> PMUXO_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 4)) | ((value as u8 & 0x0f) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Peripheral Multiplexing for Even-Numbered Pin"] + #[inline(always)] + pub fn pmuxe(&self) -> PMUXE_R { + PMUXE_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Peripheral Multiplexing for Odd-Numbered Pin"] + #[inline(always)] + pub fn pmuxo(&self) -> PMUXO_R { + PMUXO_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Peripheral Multiplexing for Even-Numbered Pin"] + #[inline(always)] + pub fn pmuxe(&mut self) -> PMUXE_W { + PMUXE_W { w: self } + } + #[doc = "Bits 4:7 - Peripheral Multiplexing for Odd-Numbered Pin"] + #[inline(always)] + pub fn pmuxo(&mut self) -> PMUXO_W { + PMUXO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Peripheral Multiplexing n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pmux](index.html) module"] +pub struct PMUX_SPEC; +impl crate::RegisterSpec for PMUX_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [pmux::R](R) reader structure"] +impl crate::Readable for PMUX_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [pmux::W](W) writer structure"] +impl crate::Writable for PMUX_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PMUX[%s] +to value 0"] +impl crate::Resettable for PMUX_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/port/group/wrconfig.rs b/pac/atsamc21n/src/port/group/wrconfig.rs new file mode 100644 index 000000000000..c87e4f174728 --- /dev/null +++ b/pac/atsamc21n/src/port/group/wrconfig.rs @@ -0,0 +1,268 @@ +#[doc = "Register `WRCONFIG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PINMASK` writer - Pin Mask for Multiple Pin Configuration"] +pub struct PINMASK_W<'a> { + w: &'a mut W, +} +impl<'a> PINMASK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +#[doc = "Field `PMUXEN` writer - Select Peripheral Multiplexer"] +pub struct PMUXEN_W<'a> { + w: &'a mut W, +} +impl<'a> PMUXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `INEN` writer - Input Enable"] +pub struct INEN_W<'a> { + w: &'a mut W, +} +impl<'a> INEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `PULLEN` writer - Pull Enable"] +pub struct PULLEN_W<'a> { + w: &'a mut W, +} +impl<'a> PULLEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `DRVSTR` writer - Output Driver Strength Selection"] +pub struct DRVSTR_W<'a> { + w: &'a mut W, +} +impl<'a> DRVSTR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `PMUX` writer - Peripheral Multiplexing Template"] +pub struct PMUX_W<'a> { + w: &'a mut W, +} +impl<'a> PMUX_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Field `WRPMUX` writer - Write PMUX Registers"] +pub struct WRPMUX_W<'a> { + w: &'a mut W, +} +impl<'a> WRPMUX_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Field `WRPINCFG` writer - Write PINCFG Registers"] +pub struct WRPINCFG_W<'a> { + w: &'a mut W, +} +impl<'a> WRPINCFG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +#[doc = "Field `HWSEL` writer - Half-Word Select"] +pub struct HWSEL_W<'a> { + w: &'a mut W, +} +impl<'a> HWSEL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl W { + #[doc = "Bits 0:15 - Pin Mask for Multiple Pin Configuration"] + #[inline(always)] + pub fn pinmask(&mut self) -> PINMASK_W { + PINMASK_W { w: self } + } + #[doc = "Bit 16 - Select Peripheral Multiplexer"] + #[inline(always)] + pub fn pmuxen(&mut self) -> PMUXEN_W { + PMUXEN_W { w: self } + } + #[doc = "Bit 17 - Input Enable"] + #[inline(always)] + pub fn inen(&mut self) -> INEN_W { + INEN_W { w: self } + } + #[doc = "Bit 18 - Pull Enable"] + #[inline(always)] + pub fn pullen(&mut self) -> PULLEN_W { + PULLEN_W { w: self } + } + #[doc = "Bit 22 - Output Driver Strength Selection"] + #[inline(always)] + pub fn drvstr(&mut self) -> DRVSTR_W { + DRVSTR_W { w: self } + } + #[doc = "Bits 24:27 - Peripheral Multiplexing Template"] + #[inline(always)] + pub fn pmux(&mut self) -> PMUX_W { + PMUX_W { w: self } + } + #[doc = "Bit 28 - Write PMUX Registers"] + #[inline(always)] + pub fn wrpmux(&mut self) -> WRPMUX_W { + WRPMUX_W { w: self } + } + #[doc = "Bit 30 - Write PINCFG Registers"] + #[inline(always)] + pub fn wrpincfg(&mut self) -> WRPINCFG_W { + WRPINCFG_W { w: self } + } + #[doc = "Bit 31 - Half-Word Select"] + #[inline(always)] + pub fn hwsel(&mut self) -> HWSEL_W { + HWSEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Write Configuration\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wrconfig](index.html) module"] +pub struct WRCONFIG_SPEC; +impl crate::RegisterSpec for WRCONFIG_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [wrconfig::W](W) writer structure"] +impl crate::Writable for WRCONFIG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WRCONFIG to value 0"] +impl crate::Resettable for WRCONFIG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/rstc.rs b/pac/atsamc21n/src/rstc.rs new file mode 100644 index 000000000000..327b511df28a --- /dev/null +++ b/pac/atsamc21n/src/rstc.rs @@ -0,0 +1,10 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Reset Cause"] + pub rcause: crate::Reg, +} +#[doc = "RCAUSE register accessor: an alias for `Reg`"] +pub type RCAUSE = crate::Reg; +#[doc = "Reset Cause"] +pub mod rcause; diff --git a/pac/atsamc21n/src/rstc/rcause.rs b/pac/atsamc21n/src/rstc/rcause.rs new file mode 100644 index 000000000000..3dc13496e74b --- /dev/null +++ b/pac/atsamc21n/src/rstc/rcause.rs @@ -0,0 +1,153 @@ +#[doc = "Register `RCAUSE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `POR` reader - Power On Reset"] +pub struct POR_R(crate::FieldReader); +impl POR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + POR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for POR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODCORE` reader - Brown Out CORE Detector Reset"] +pub struct BODCORE_R(crate::FieldReader); +impl BODCORE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODCORE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODCORE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODVDD` reader - Brown Out VDD Detector Reset"] +pub struct BODVDD_R(crate::FieldReader); +impl BODVDD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODVDD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODVDD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXT` reader - External Reset"] +pub struct EXT_R(crate::FieldReader); +impl EXT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WDT` reader - Watchdog Reset"] +pub struct WDT_R(crate::FieldReader); +impl WDT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WDT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WDT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYST` reader - System Reset Request"] +pub struct SYST_R(crate::FieldReader); +impl SYST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Power On Reset"] + #[inline(always)] + pub fn por(&self) -> POR_R { + POR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Brown Out CORE Detector Reset"] + #[inline(always)] + pub fn bodcore(&self) -> BODCORE_R { + BODCORE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Brown Out VDD Detector Reset"] + #[inline(always)] + pub fn bodvdd(&self) -> BODVDD_R { + BODVDD_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 4 - External Reset"] + #[inline(always)] + pub fn ext(&self) -> EXT_R { + EXT_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Watchdog Reset"] + #[inline(always)] + pub fn wdt(&self) -> WDT_R { + WDT_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - System Reset Request"] + #[inline(always)] + pub fn syst(&self) -> SYST_R { + SYST_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +#[doc = "Reset Cause\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rcause](index.html) module"] +pub struct RCAUSE_SPEC; +impl crate::RegisterSpec for RCAUSE_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [rcause::R](R) reader structure"] +impl crate::Readable for RCAUSE_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets RCAUSE to value 0"] +impl crate::Resettable for RCAUSE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/rtc.rs b/pac/atsamc21n/src/rtc.rs new file mode 100644 index 000000000000..62f424cb1a8e --- /dev/null +++ b/pac/atsamc21n/src/rtc.rs @@ -0,0 +1,120 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved_0_mode0: [u8; 0x25], +} +impl RegisterBlock { + #[doc = "0x00..0x25 - Clock/Calendar with Alarm"] + #[inline(always)] + pub fn mode2(&self) -> &MODE2 { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const MODE2) } + } + #[doc = "0x00..0x24 - 16-bit Counter with Two 16-bit Compares"] + #[inline(always)] + pub fn mode1(&self) -> &MODE1 { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const MODE1) } + } + #[doc = "0x00..0x24 - 32-bit Counter with Single 32-bit Compare"] + #[inline(always)] + pub fn mode0(&self) -> &MODE0 { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const MODE0) } + } +} +#[doc = r"Register block"] +#[repr(C)] +pub struct MODE0 { + #[doc = "0x00 - MODE0 Control A"] + pub ctrla: crate::Reg, + _reserved1: [u8; 0x02], + #[doc = "0x04 - MODE0 Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x08 - MODE0 Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x0a - MODE0 Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x0c - MODE0 Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x0e - Debug Control"] + pub dbgctrl: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x10 - MODE0 Synchronization Busy Status"] + pub syncbusy: crate::Reg, + #[doc = "0x14 - Frequency Correction"] + pub freqcorr: crate::Reg, + _reserved8: [u8; 0x03], + #[doc = "0x18 - MODE0 Counter Value"] + pub count: crate::Reg, + _reserved9: [u8; 0x04], + #[doc = "0x20 - MODE0 Compare n Value"] + pub comp: crate::Reg, +} +#[doc = r"Register block"] +#[doc = "32-bit Counter with Single 32-bit Compare"] +pub mod mode0; +#[doc = r"Register block"] +#[repr(C)] +pub struct MODE1 { + #[doc = "0x00 - MODE1 Control A"] + pub ctrla: crate::Reg, + _reserved1: [u8; 0x02], + #[doc = "0x04 - MODE1 Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x08 - MODE1 Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x0a - MODE1 Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x0c - MODE1 Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x0e - Debug Control"] + pub dbgctrl: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x10 - MODE1 Synchronization Busy Status"] + pub syncbusy: crate::Reg, + #[doc = "0x14 - Frequency Correction"] + pub freqcorr: crate::Reg, + _reserved8: [u8; 0x03], + #[doc = "0x18 - MODE1 Counter Value"] + pub count: crate::Reg, + _reserved9: [u8; 0x02], + #[doc = "0x1c - MODE1 Counter Period"] + pub per: crate::Reg, + _reserved10: [u8; 0x02], + #[doc = "0x20 - MODE1 Compare n Value"] + pub comp: [crate::Reg; 2], +} +#[doc = r"Register block"] +#[doc = "16-bit Counter with Two 16-bit Compares"] +pub mod mode1; +#[doc = r"Register block"] +#[repr(C)] +pub struct MODE2 { + #[doc = "0x00 - MODE2 Control A"] + pub ctrla: crate::Reg, + _reserved1: [u8; 0x02], + #[doc = "0x04 - MODE2 Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x08 - MODE2 Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x0a - MODE2 Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x0c - MODE2 Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x0e - Debug Control"] + pub dbgctrl: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x10 - MODE2 Synchronization Busy Status"] + pub syncbusy: crate::Reg, + #[doc = "0x14 - Frequency Correction"] + pub freqcorr: crate::Reg, + _reserved8: [u8; 0x03], + #[doc = "0x18 - MODE2 Clock Value"] + pub clock: crate::Reg, + _reserved9: [u8; 0x04], + #[doc = "0x20 - MODE2_ALARM Alarm n Value"] + pub alarm: crate::Reg, + #[doc = "0x24 - MODE2_ALARM Alarm n Mask"] + pub mask: crate::Reg, +} +#[doc = r"Register block"] +#[doc = "Clock/Calendar with Alarm"] +pub mod mode2; diff --git a/pac/atsamc21n/src/rtc/mode0.rs b/pac/atsamc21n/src/rtc/mode0.rs new file mode 100644 index 000000000000..9ce5c3808169 --- /dev/null +++ b/pac/atsamc21n/src/rtc/mode0.rs @@ -0,0 +1,40 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "MODE0 Control A"] +pub mod ctrla; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "MODE0 Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "MODE0 Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "MODE0 Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "MODE0 Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "MODE0 Synchronization Busy Status"] +pub mod syncbusy; +#[doc = "FREQCORR register accessor: an alias for `Reg`"] +pub type FREQCORR = crate::Reg; +#[doc = "Frequency Correction"] +pub mod freqcorr; +#[doc = "COUNT register accessor: an alias for `Reg`"] +pub type COUNT = crate::Reg; +#[doc = "MODE0 Counter Value"] +pub mod count; +#[doc = "COMP register accessor: an alias for `Reg`"] +pub type COMP = crate::Reg; +#[doc = "MODE0 Compare n Value"] +pub mod comp; diff --git a/pac/atsamc21n/src/rtc/mode0/comp.rs b/pac/atsamc21n/src/rtc/mode0/comp.rs new file mode 100644 index 000000000000..a909d3cea2d3 --- /dev/null +++ b/pac/atsamc21n/src/rtc/mode0/comp.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COMP` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COMP` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COMP` reader - Compare Value"] +pub struct COMP_R(crate::FieldReader); +impl COMP_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COMP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP` writer - Compare Value"] +pub struct COMP_W<'a> { + w: &'a mut W, +} +impl<'a> COMP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Compare Value"] + #[inline(always)] + pub fn comp(&self) -> COMP_R { + COMP_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Compare Value"] + #[inline(always)] + pub fn comp(&mut self) -> COMP_W { + COMP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE0 Compare n Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [comp](index.html) module"] +pub struct COMP_SPEC; +impl crate::RegisterSpec for COMP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [comp::R](R) reader structure"] +impl crate::Readable for COMP_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [comp::W](W) writer structure"] +impl crate::Writable for COMP_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COMP to value 0"] +impl crate::Resettable for COMP_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/rtc/mode0/count.rs b/pac/atsamc21n/src/rtc/mode0/count.rs new file mode 100644 index 000000000000..cf880b5e77a6 --- /dev/null +++ b/pac/atsamc21n/src/rtc/mode0/count.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE0 Counter Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count](index.html) module"] +pub struct COUNT_SPEC; +impl crate::RegisterSpec for COUNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [count::R](R) reader structure"] +impl crate::Readable for COUNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count::W](W) writer structure"] +impl crate::Writable for COUNT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT to value 0"] +impl crate::Resettable for COUNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/rtc/mode0/ctrla.rs b/pac/atsamc21n/src/rtc/mode0/ctrla.rs new file mode 100644 index 000000000000..423877bd087d --- /dev/null +++ b/pac/atsamc21n/src/rtc/mode0/ctrla.rs @@ -0,0 +1,569 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: Mode 0: 32-bit Counter"] + COUNT32 = 0, + #[doc = "1: Mode 1: 16-bit Counter"] + COUNT16 = 1, + #[doc = "2: Mode 2: Clock/Calendar"] + CLOCK = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::COUNT32), + 1 => Some(MODE_A::COUNT16), + 2 => Some(MODE_A::CLOCK), + _ => None, + } + } + #[doc = "Checks if the value of the field is `COUNT32`"] + #[inline(always)] + pub fn is_count32(&self) -> bool { + **self == MODE_A::COUNT32 + } + #[doc = "Checks if the value of the field is `COUNT16`"] + #[inline(always)] + pub fn is_count16(&self) -> bool { + **self == MODE_A::COUNT16 + } + #[doc = "Checks if the value of the field is `CLOCK`"] + #[inline(always)] + pub fn is_clock(&self) -> bool { + **self == MODE_A::CLOCK + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Mode 0: 32-bit Counter"] + #[inline(always)] + pub fn count32(self) -> &'a mut W { + self.variant(MODE_A::COUNT32) + } + #[doc = "Mode 1: 16-bit Counter"] + #[inline(always)] + pub fn count16(self) -> &'a mut W { + self.variant(MODE_A::COUNT16) + } + #[doc = "Mode 2: Clock/Calendar"] + #[inline(always)] + pub fn clock(self) -> &'a mut W { + self.variant(MODE_A::CLOCK) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u16 & 0x03) << 2); + self.w + } +} +#[doc = "Field `MATCHCLR` reader - Clear on Match"] +pub struct MATCHCLR_R(crate::FieldReader); +impl MATCHCLR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MATCHCLR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MATCHCLR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MATCHCLR` writer - Clear on Match"] +pub struct MATCHCLR_W<'a> { + w: &'a mut W, +} +impl<'a> MATCHCLR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: CLK_RTC_CNT = GCLK_RTC/1"] + OFF = 0, + #[doc = "1: CLK_RTC_CNT = GCLK_RTC/1"] + DIV1 = 1, + #[doc = "2: CLK_RTC_CNT = GCLK_RTC/2"] + DIV2 = 2, + #[doc = "3: CLK_RTC_CNT = GCLK_RTC/4"] + DIV4 = 3, + #[doc = "4: CLK_RTC_CNT = GCLK_RTC/8"] + DIV8 = 4, + #[doc = "5: CLK_RTC_CNT = GCLK_RTC/16"] + DIV16 = 5, + #[doc = "6: CLK_RTC_CNT = GCLK_RTC/32"] + DIV32 = 6, + #[doc = "7: CLK_RTC_CNT = GCLK_RTC/64"] + DIV64 = 7, + #[doc = "8: CLK_RTC_CNT = GCLK_RTC/128"] + DIV128 = 8, + #[doc = "9: CLK_RTC_CNT = GCLK_RTC/256"] + DIV256 = 9, + #[doc = "10: CLK_RTC_CNT = GCLK_RTC/512"] + DIV512 = 10, + #[doc = "11: CLK_RTC_CNT = GCLK_RTC/1024"] + DIV1024 = 11, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCALER_A::OFF), + 1 => Some(PRESCALER_A::DIV1), + 2 => Some(PRESCALER_A::DIV2), + 3 => Some(PRESCALER_A::DIV4), + 4 => Some(PRESCALER_A::DIV8), + 5 => Some(PRESCALER_A::DIV16), + 6 => Some(PRESCALER_A::DIV32), + 7 => Some(PRESCALER_A::DIV64), + 8 => Some(PRESCALER_A::DIV128), + 9 => Some(PRESCALER_A::DIV256), + 10 => Some(PRESCALER_A::DIV512), + 11 => Some(PRESCALER_A::DIV1024), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == PRESCALER_A::OFF + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == PRESCALER_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == PRESCALER_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == PRESCALER_A::DIV128 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV512`"] + #[inline(always)] + pub fn is_div512(&self) -> bool { + **self == PRESCALER_A::DIV512 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PRESCALER_A::DIV1024 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(PRESCALER_A::OFF) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV32) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV128) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/512"] + #[inline(always)] + pub fn div512(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV512) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 8)) | ((value as u16 & 0x0f) << 8); + self.w + } +} +#[doc = "Field `COUNTSYNC` reader - Count Read Synchronization Enable"] +pub struct COUNTSYNC_R(crate::FieldReader); +impl COUNTSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNTSYNC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNTSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNTSYNC` writer - Count Read Synchronization Enable"] +pub struct COUNTSYNC_W<'a> { + w: &'a mut W, +} +impl<'a> COUNTSYNC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:3 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bit 7 - Clear on Match"] + #[inline(always)] + pub fn matchclr(&self) -> MATCHCLR_R { + MATCHCLR_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:11 - Prescaler"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 15 - Count Read Synchronization Enable"] + #[inline(always)] + pub fn countsync(&self) -> COUNTSYNC_R { + COUNTSYNC_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:3 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 7 - Clear on Match"] + #[inline(always)] + pub fn matchclr(&mut self) -> MATCHCLR_W { + MATCHCLR_W { w: self } + } + #[doc = "Bits 8:11 - Prescaler"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Bit 15 - Count Read Synchronization Enable"] + #[inline(always)] + pub fn countsync(&mut self) -> COUNTSYNC_W { + COUNTSYNC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE0 Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/rtc/mode0/dbgctrl.rs b/pac/atsamc21n/src/rtc/mode0/dbgctrl.rs new file mode 100644 index 000000000000..0383e70d0429 --- /dev/null +++ b/pac/atsamc21n/src/rtc/mode0/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Run During Debug"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Run During Debug"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/rtc/mode0/evctrl.rs b/pac/atsamc21n/src/rtc/mode0/evctrl.rs new file mode 100644 index 000000000000..c73647759dbe --- /dev/null +++ b/pac/atsamc21n/src/rtc/mode0/evctrl.rs @@ -0,0 +1,536 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PEREO0` reader - Periodic Interval 0 Event Output Enable"] +pub struct PEREO0_R(crate::FieldReader); +impl PEREO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO0` writer - Periodic Interval 0 Event Output Enable"] +pub struct PEREO0_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `PEREO1` reader - Periodic Interval 1 Event Output Enable"] +pub struct PEREO1_R(crate::FieldReader); +impl PEREO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO1` writer - Periodic Interval 1 Event Output Enable"] +pub struct PEREO1_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PEREO2` reader - Periodic Interval 2 Event Output Enable"] +pub struct PEREO2_R(crate::FieldReader); +impl PEREO2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO2` writer - Periodic Interval 2 Event Output Enable"] +pub struct PEREO2_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PEREO3` reader - Periodic Interval 3 Event Output Enable"] +pub struct PEREO3_R(crate::FieldReader); +impl PEREO3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO3` writer - Periodic Interval 3 Event Output Enable"] +pub struct PEREO3_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PEREO4` reader - Periodic Interval 4 Event Output Enable"] +pub struct PEREO4_R(crate::FieldReader); +impl PEREO4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO4` writer - Periodic Interval 4 Event Output Enable"] +pub struct PEREO4_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PEREO5` reader - Periodic Interval 5 Event Output Enable"] +pub struct PEREO5_R(crate::FieldReader); +impl PEREO5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO5` writer - Periodic Interval 5 Event Output Enable"] +pub struct PEREO5_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PEREO6` reader - Periodic Interval 6 Event Output Enable"] +pub struct PEREO6_R(crate::FieldReader); +impl PEREO6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO6` writer - Periodic Interval 6 Event Output Enable"] +pub struct PEREO6_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PEREO7` reader - Periodic Interval 7 Event Output Enable"] +pub struct PEREO7_R(crate::FieldReader); +impl PEREO7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO7` writer - Periodic Interval 7 Event Output Enable"] +pub struct PEREO7_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CMPEO0` reader - Compare 0 Event Output Enable"] +pub struct CMPEO0_R(crate::FieldReader); +impl CMPEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMPEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMPEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMPEO0` writer - Compare 0 Event Output Enable"] +pub struct CMPEO0_W<'a> { + w: &'a mut W, +} +impl<'a> CMPEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `OVFEO` reader - Overflow Event Output Enable"] +pub struct OVFEO_R(crate::FieldReader); +impl OVFEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVFEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVFEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVFEO` writer - Overflow Event Output Enable"] +pub struct OVFEO_W<'a> { + w: &'a mut W, +} +impl<'a> OVFEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Event Output Enable"] + #[inline(always)] + pub fn pereo0(&self) -> PEREO0_R { + PEREO0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Event Output Enable"] + #[inline(always)] + pub fn pereo1(&self) -> PEREO1_R { + PEREO1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Event Output Enable"] + #[inline(always)] + pub fn pereo2(&self) -> PEREO2_R { + PEREO2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Event Output Enable"] + #[inline(always)] + pub fn pereo3(&self) -> PEREO3_R { + PEREO3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Event Output Enable"] + #[inline(always)] + pub fn pereo4(&self) -> PEREO4_R { + PEREO4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Event Output Enable"] + #[inline(always)] + pub fn pereo5(&self) -> PEREO5_R { + PEREO5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Event Output Enable"] + #[inline(always)] + pub fn pereo6(&self) -> PEREO6_R { + PEREO6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Event Output Enable"] + #[inline(always)] + pub fn pereo7(&self) -> PEREO7_R { + PEREO7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Compare 0 Event Output Enable"] + #[inline(always)] + pub fn cmpeo0(&self) -> CMPEO0_R { + CMPEO0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&self) -> OVFEO_R { + OVFEO_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Event Output Enable"] + #[inline(always)] + pub fn pereo0(&mut self) -> PEREO0_W { + PEREO0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1 Event Output Enable"] + #[inline(always)] + pub fn pereo1(&mut self) -> PEREO1_W { + PEREO1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2 Event Output Enable"] + #[inline(always)] + pub fn pereo2(&mut self) -> PEREO2_W { + PEREO2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3 Event Output Enable"] + #[inline(always)] + pub fn pereo3(&mut self) -> PEREO3_W { + PEREO3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4 Event Output Enable"] + #[inline(always)] + pub fn pereo4(&mut self) -> PEREO4_W { + PEREO4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5 Event Output Enable"] + #[inline(always)] + pub fn pereo5(&mut self) -> PEREO5_W { + PEREO5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6 Event Output Enable"] + #[inline(always)] + pub fn pereo6(&mut self) -> PEREO6_W { + PEREO6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7 Event Output Enable"] + #[inline(always)] + pub fn pereo7(&mut self) -> PEREO7_W { + PEREO7_W { w: self } + } + #[doc = "Bit 8 - Compare 0 Event Output Enable"] + #[inline(always)] + pub fn cmpeo0(&mut self) -> CMPEO0_W { + CMPEO0_W { w: self } + } + #[doc = "Bit 15 - Overflow Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&mut self) -> OVFEO_W { + OVFEO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE0 Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/rtc/mode0/freqcorr.rs b/pac/atsamc21n/src/rtc/mode0/freqcorr.rs new file mode 100644 index 000000000000..043ba6f88eb2 --- /dev/null +++ b/pac/atsamc21n/src/rtc/mode0/freqcorr.rs @@ -0,0 +1,150 @@ +#[doc = "Register `FREQCORR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FREQCORR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `VALUE` reader - Correction Value"] +pub struct VALUE_R(crate::FieldReader); +impl VALUE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + VALUE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VALUE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VALUE` writer - Correction Value"] +pub struct VALUE_W<'a> { + w: &'a mut W, +} +impl<'a> VALUE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x7f) | (value as u8 & 0x7f); + self.w + } +} +#[doc = "Field `SIGN` reader - Correction Sign"] +pub struct SIGN_R(crate::FieldReader); +impl SIGN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SIGN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SIGN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SIGN` writer - Correction Sign"] +pub struct SIGN_W<'a> { + w: &'a mut W, +} +impl<'a> SIGN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bits 0:6 - Correction Value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bit 7 - Correction Sign"] + #[inline(always)] + pub fn sign(&self) -> SIGN_R { + SIGN_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:6 - Correction Value"] + #[inline(always)] + pub fn value(&mut self) -> VALUE_W { + VALUE_W { w: self } + } + #[doc = "Bit 7 - Correction Sign"] + #[inline(always)] + pub fn sign(&mut self) -> SIGN_W { + SIGN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Frequency Correction\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [freqcorr](index.html) module"] +pub struct FREQCORR_SPEC; +impl crate::RegisterSpec for FREQCORR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [freqcorr::R](R) reader structure"] +impl crate::Readable for FREQCORR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [freqcorr::W](W) writer structure"] +impl crate::Writable for FREQCORR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets FREQCORR to value 0"] +impl crate::Resettable for FREQCORR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/rtc/mode0/intenclr.rs b/pac/atsamc21n/src/rtc/mode0/intenclr.rs new file mode 100644 index 000000000000..8be5e2c3920b --- /dev/null +++ b/pac/atsamc21n/src/rtc/mode0/intenclr.rs @@ -0,0 +1,536 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER0` reader - Periodic Interval 0 Interrupt Enable"] +pub struct PER0_R(crate::FieldReader); +impl PER0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER0` writer - Periodic Interval 0 Interrupt Enable"] +pub struct PER0_W<'a> { + w: &'a mut W, +} +impl<'a> PER0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PER1` reader - Periodic Interval 1 Interrupt Enable"] +pub struct PER1_R(crate::FieldReader); +impl PER1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER1` writer - Periodic Interval 1 Interrupt Enable"] +pub struct PER1_W<'a> { + w: &'a mut W, +} +impl<'a> PER1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PER2` reader - Periodic Interval 2 Interrupt Enable"] +pub struct PER2_R(crate::FieldReader); +impl PER2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER2` writer - Periodic Interval 2 Interrupt Enable"] +pub struct PER2_W<'a> { + w: &'a mut W, +} +impl<'a> PER2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PER3` reader - Periodic Interval 3 Interrupt Enable"] +pub struct PER3_R(crate::FieldReader); +impl PER3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER3` writer - Periodic Interval 3 Interrupt Enable"] +pub struct PER3_W<'a> { + w: &'a mut W, +} +impl<'a> PER3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PER4` reader - Periodic Interval 4 Interrupt Enable"] +pub struct PER4_R(crate::FieldReader); +impl PER4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER4` writer - Periodic Interval 4 Interrupt Enable"] +pub struct PER4_W<'a> { + w: &'a mut W, +} +impl<'a> PER4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PER5` reader - Periodic Interval 5 Interrupt Enable"] +pub struct PER5_R(crate::FieldReader); +impl PER5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER5` writer - Periodic Interval 5 Interrupt Enable"] +pub struct PER5_W<'a> { + w: &'a mut W, +} +impl<'a> PER5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PER6` reader - Periodic Interval 6 Interrupt Enable"] +pub struct PER6_R(crate::FieldReader); +impl PER6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER6` writer - Periodic Interval 6 Interrupt Enable"] +pub struct PER6_W<'a> { + w: &'a mut W, +} +impl<'a> PER6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PER7` reader - Periodic Interval 7 Interrupt Enable"] +pub struct PER7_R(crate::FieldReader); +impl PER7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER7` writer - Periodic Interval 7 Interrupt Enable"] +pub struct PER7_W<'a> { + w: &'a mut W, +} +impl<'a> PER7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CMP0` reader - Compare 0 Interrupt Enable"] +pub struct CMP0_R(crate::FieldReader); +impl CMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP0` writer - Compare 0 Interrupt Enable"] +pub struct CMP0_W<'a> { + w: &'a mut W, +} +impl<'a> CMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + pub fn per0(&self) -> PER0_R { + PER0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + pub fn per1(&self) -> PER1_R { + PER1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + pub fn per2(&self) -> PER2_R { + PER2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + pub fn per3(&self) -> PER3_R { + PER3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + pub fn per4(&self) -> PER4_R { + PER4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + pub fn per5(&self) -> PER5_R { + PER5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + pub fn per6(&self) -> PER6_R { + PER6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + pub fn per7(&self) -> PER7_R { + PER7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&self) -> CMP0_R { + CMP0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + pub fn per0(&mut self) -> PER0_W { + PER0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + pub fn per1(&mut self) -> PER1_W { + PER1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + pub fn per2(&mut self) -> PER2_W { + PER2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + pub fn per3(&mut self) -> PER3_W { + PER3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + pub fn per4(&mut self) -> PER4_W { + PER4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + pub fn per5(&mut self) -> PER5_W { + PER5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + pub fn per6(&mut self) -> PER6_W { + PER6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + pub fn per7(&mut self) -> PER7_W { + PER7_W { w: self } + } + #[doc = "Bit 8 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&mut self) -> CMP0_W { + CMP0_W { w: self } + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE0 Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/rtc/mode0/intenset.rs b/pac/atsamc21n/src/rtc/mode0/intenset.rs new file mode 100644 index 000000000000..7228f5d486f5 --- /dev/null +++ b/pac/atsamc21n/src/rtc/mode0/intenset.rs @@ -0,0 +1,536 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER0` reader - Periodic Interval 0 Interrupt Enable"] +pub struct PER0_R(crate::FieldReader); +impl PER0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER0` writer - Periodic Interval 0 Interrupt Enable"] +pub struct PER0_W<'a> { + w: &'a mut W, +} +impl<'a> PER0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PER1` reader - Periodic Interval 1 Interrupt Enable"] +pub struct PER1_R(crate::FieldReader); +impl PER1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER1` writer - Periodic Interval 1 Interrupt Enable"] +pub struct PER1_W<'a> { + w: &'a mut W, +} +impl<'a> PER1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PER2` reader - Periodic Interval 2 Interrupt Enable"] +pub struct PER2_R(crate::FieldReader); +impl PER2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER2` writer - Periodic Interval 2 Interrupt Enable"] +pub struct PER2_W<'a> { + w: &'a mut W, +} +impl<'a> PER2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PER3` reader - Periodic Interval 3 Interrupt Enable"] +pub struct PER3_R(crate::FieldReader); +impl PER3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER3` writer - Periodic Interval 3 Interrupt Enable"] +pub struct PER3_W<'a> { + w: &'a mut W, +} +impl<'a> PER3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PER4` reader - Periodic Interval 4 Interrupt Enable"] +pub struct PER4_R(crate::FieldReader); +impl PER4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER4` writer - Periodic Interval 4 Interrupt Enable"] +pub struct PER4_W<'a> { + w: &'a mut W, +} +impl<'a> PER4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PER5` reader - Periodic Interval 5 Interrupt Enable"] +pub struct PER5_R(crate::FieldReader); +impl PER5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER5` writer - Periodic Interval 5 Interrupt Enable"] +pub struct PER5_W<'a> { + w: &'a mut W, +} +impl<'a> PER5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PER6` reader - Periodic Interval 6 Interrupt Enable"] +pub struct PER6_R(crate::FieldReader); +impl PER6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER6` writer - Periodic Interval 6 Interrupt Enable"] +pub struct PER6_W<'a> { + w: &'a mut W, +} +impl<'a> PER6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PER7` reader - Periodic Interval 7 Interrupt Enable"] +pub struct PER7_R(crate::FieldReader); +impl PER7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER7` writer - Periodic Interval 7 Interrupt Enable"] +pub struct PER7_W<'a> { + w: &'a mut W, +} +impl<'a> PER7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CMP0` reader - Compare 0 Interrupt Enable"] +pub struct CMP0_R(crate::FieldReader); +impl CMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP0` writer - Compare 0 Interrupt Enable"] +pub struct CMP0_W<'a> { + w: &'a mut W, +} +impl<'a> CMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + pub fn per0(&self) -> PER0_R { + PER0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + pub fn per1(&self) -> PER1_R { + PER1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + pub fn per2(&self) -> PER2_R { + PER2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + pub fn per3(&self) -> PER3_R { + PER3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + pub fn per4(&self) -> PER4_R { + PER4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + pub fn per5(&self) -> PER5_R { + PER5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + pub fn per6(&self) -> PER6_R { + PER6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + pub fn per7(&self) -> PER7_R { + PER7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&self) -> CMP0_R { + CMP0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + pub fn per0(&mut self) -> PER0_W { + PER0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + pub fn per1(&mut self) -> PER1_W { + PER1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + pub fn per2(&mut self) -> PER2_W { + PER2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + pub fn per3(&mut self) -> PER3_W { + PER3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + pub fn per4(&mut self) -> PER4_W { + PER4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + pub fn per5(&mut self) -> PER5_W { + PER5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + pub fn per6(&mut self) -> PER6_W { + PER6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + pub fn per7(&mut self) -> PER7_W { + PER7_W { w: self } + } + #[doc = "Bit 8 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&mut self) -> CMP0_W { + CMP0_W { w: self } + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE0 Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/rtc/mode0/intflag.rs b/pac/atsamc21n/src/rtc/mode0/intflag.rs new file mode 100644 index 000000000000..f2dccdb04aa4 --- /dev/null +++ b/pac/atsamc21n/src/rtc/mode0/intflag.rs @@ -0,0 +1,536 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER0` reader - Periodic Interval 0"] +pub struct PER0_R(crate::FieldReader); +impl PER0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER0` writer - Periodic Interval 0"] +pub struct PER0_W<'a> { + w: &'a mut W, +} +impl<'a> PER0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PER1` reader - Periodic Interval 1"] +pub struct PER1_R(crate::FieldReader); +impl PER1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER1` writer - Periodic Interval 1"] +pub struct PER1_W<'a> { + w: &'a mut W, +} +impl<'a> PER1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PER2` reader - Periodic Interval 2"] +pub struct PER2_R(crate::FieldReader); +impl PER2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER2` writer - Periodic Interval 2"] +pub struct PER2_W<'a> { + w: &'a mut W, +} +impl<'a> PER2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PER3` reader - Periodic Interval 3"] +pub struct PER3_R(crate::FieldReader); +impl PER3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER3` writer - Periodic Interval 3"] +pub struct PER3_W<'a> { + w: &'a mut W, +} +impl<'a> PER3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PER4` reader - Periodic Interval 4"] +pub struct PER4_R(crate::FieldReader); +impl PER4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER4` writer - Periodic Interval 4"] +pub struct PER4_W<'a> { + w: &'a mut W, +} +impl<'a> PER4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PER5` reader - Periodic Interval 5"] +pub struct PER5_R(crate::FieldReader); +impl PER5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER5` writer - Periodic Interval 5"] +pub struct PER5_W<'a> { + w: &'a mut W, +} +impl<'a> PER5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PER6` reader - Periodic Interval 6"] +pub struct PER6_R(crate::FieldReader); +impl PER6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER6` writer - Periodic Interval 6"] +pub struct PER6_W<'a> { + w: &'a mut W, +} +impl<'a> PER6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PER7` reader - Periodic Interval 7"] +pub struct PER7_R(crate::FieldReader); +impl PER7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER7` writer - Periodic Interval 7"] +pub struct PER7_W<'a> { + w: &'a mut W, +} +impl<'a> PER7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CMP0` reader - Compare 0"] +pub struct CMP0_R(crate::FieldReader); +impl CMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP0` writer - Compare 0"] +pub struct CMP0_W<'a> { + w: &'a mut W, +} +impl<'a> CMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0"] + #[inline(always)] + pub fn per0(&self) -> PER0_R { + PER0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1"] + #[inline(always)] + pub fn per1(&self) -> PER1_R { + PER1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2"] + #[inline(always)] + pub fn per2(&self) -> PER2_R { + PER2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3"] + #[inline(always)] + pub fn per3(&self) -> PER3_R { + PER3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4"] + #[inline(always)] + pub fn per4(&self) -> PER4_R { + PER4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5"] + #[inline(always)] + pub fn per5(&self) -> PER5_R { + PER5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6"] + #[inline(always)] + pub fn per6(&self) -> PER6_R { + PER6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7"] + #[inline(always)] + pub fn per7(&self) -> PER7_R { + PER7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Compare 0"] + #[inline(always)] + pub fn cmp0(&self) -> CMP0_R { + CMP0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0"] + #[inline(always)] + pub fn per0(&mut self) -> PER0_W { + PER0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1"] + #[inline(always)] + pub fn per1(&mut self) -> PER1_W { + PER1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2"] + #[inline(always)] + pub fn per2(&mut self) -> PER2_W { + PER2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3"] + #[inline(always)] + pub fn per3(&mut self) -> PER3_W { + PER3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4"] + #[inline(always)] + pub fn per4(&mut self) -> PER4_W { + PER4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5"] + #[inline(always)] + pub fn per5(&mut self) -> PER5_W { + PER5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6"] + #[inline(always)] + pub fn per6(&mut self) -> PER6_W { + PER6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7"] + #[inline(always)] + pub fn per7(&mut self) -> PER7_W { + PER7_W { w: self } + } + #[doc = "Bit 8 - Compare 0"] + #[inline(always)] + pub fn cmp0(&mut self) -> CMP0_W { + CMP0_W { w: self } + } + #[doc = "Bit 15 - Overflow"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE0 Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/rtc/mode0/syncbusy.rs b/pac/atsamc21n/src/rtc/mode0/syncbusy.rs new file mode 100644 index 000000000000..518dea115a18 --- /dev/null +++ b/pac/atsamc21n/src/rtc/mode0/syncbusy.rs @@ -0,0 +1,153 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - Enable Bit Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FREQCORR` reader - FREQCORR Register Busy"] +pub struct FREQCORR_R(crate::FieldReader); +impl FREQCORR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FREQCORR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FREQCORR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` reader - COUNT Register Busy"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP0` reader - COMP 0 Register Busy"] +pub struct COMP0_R(crate::FieldReader); +impl COMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNTSYNC` reader - Count Read Synchronization Enable Bit Busy"] +pub struct COUNTSYNC_R(crate::FieldReader); +impl COUNTSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNTSYNC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNTSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable Bit Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - FREQCORR Register Busy"] + #[inline(always)] + pub fn freqcorr(&self) -> FREQCORR_R { + FREQCORR_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - COUNT Register Busy"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 5 - COMP 0 Register Busy"] + #[inline(always)] + pub fn comp0(&self) -> COMP0_R { + COMP0_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 15 - Count Read Synchronization Enable Bit Busy"] + #[inline(always)] + pub fn countsync(&self) -> COUNTSYNC_R { + COUNTSYNC_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +#[doc = "MODE0 Synchronization Busy Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/rtc/mode1.rs b/pac/atsamc21n/src/rtc/mode1.rs new file mode 100644 index 000000000000..9ea1bc17497c --- /dev/null +++ b/pac/atsamc21n/src/rtc/mode1.rs @@ -0,0 +1,44 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "MODE1 Control A"] +pub mod ctrla; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "MODE1 Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "MODE1 Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "MODE1 Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "MODE1 Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "MODE1 Synchronization Busy Status"] +pub mod syncbusy; +#[doc = "FREQCORR register accessor: an alias for `Reg`"] +pub type FREQCORR = crate::Reg; +#[doc = "Frequency Correction"] +pub mod freqcorr; +#[doc = "COUNT register accessor: an alias for `Reg`"] +pub type COUNT = crate::Reg; +#[doc = "MODE1 Counter Value"] +pub mod count; +#[doc = "PER register accessor: an alias for `Reg`"] +pub type PER = crate::Reg; +#[doc = "MODE1 Counter Period"] +pub mod per; +#[doc = "COMP register accessor: an alias for `Reg`"] +pub type COMP = crate::Reg; +#[doc = "MODE1 Compare n Value"] +pub mod comp; diff --git a/pac/atsamc21n/src/rtc/mode1/comp.rs b/pac/atsamc21n/src/rtc/mode1/comp.rs new file mode 100644 index 000000000000..6935385840f1 --- /dev/null +++ b/pac/atsamc21n/src/rtc/mode1/comp.rs @@ -0,0 +1,104 @@ +#[doc = "Register `COMP[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COMP[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COMP` reader - Compare Value"] +pub struct COMP_R(crate::FieldReader); +impl COMP_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + COMP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP` writer - Compare Value"] +pub struct COMP_W<'a> { + w: &'a mut W, +} +impl<'a> COMP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Compare Value"] + #[inline(always)] + pub fn comp(&self) -> COMP_R { + COMP_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Compare Value"] + #[inline(always)] + pub fn comp(&mut self) -> COMP_W { + COMP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Compare n Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [comp](index.html) module"] +pub struct COMP_SPEC; +impl crate::RegisterSpec for COMP_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [comp::R](R) reader structure"] +impl crate::Readable for COMP_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [comp::W](W) writer structure"] +impl crate::Writable for COMP_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COMP[%s] +to value 0"] +impl crate::Resettable for COMP_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/rtc/mode1/count.rs b/pac/atsamc21n/src/rtc/mode1/count.rs new file mode 100644 index 000000000000..2c41937b189c --- /dev/null +++ b/pac/atsamc21n/src/rtc/mode1/count.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Counter Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count](index.html) module"] +pub struct COUNT_SPEC; +impl crate::RegisterSpec for COUNT_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [count::R](R) reader structure"] +impl crate::Readable for COUNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count::W](W) writer structure"] +impl crate::Writable for COUNT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT to value 0"] +impl crate::Resettable for COUNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/rtc/mode1/ctrla.rs b/pac/atsamc21n/src/rtc/mode1/ctrla.rs new file mode 100644 index 000000000000..6e3e2042a9c4 --- /dev/null +++ b/pac/atsamc21n/src/rtc/mode1/ctrla.rs @@ -0,0 +1,522 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: Mode 0: 32-bit Counter"] + COUNT32 = 0, + #[doc = "1: Mode 1: 16-bit Counter"] + COUNT16 = 1, + #[doc = "2: Mode 2: Clock/Calendar"] + CLOCK = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::COUNT32), + 1 => Some(MODE_A::COUNT16), + 2 => Some(MODE_A::CLOCK), + _ => None, + } + } + #[doc = "Checks if the value of the field is `COUNT32`"] + #[inline(always)] + pub fn is_count32(&self) -> bool { + **self == MODE_A::COUNT32 + } + #[doc = "Checks if the value of the field is `COUNT16`"] + #[inline(always)] + pub fn is_count16(&self) -> bool { + **self == MODE_A::COUNT16 + } + #[doc = "Checks if the value of the field is `CLOCK`"] + #[inline(always)] + pub fn is_clock(&self) -> bool { + **self == MODE_A::CLOCK + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Mode 0: 32-bit Counter"] + #[inline(always)] + pub fn count32(self) -> &'a mut W { + self.variant(MODE_A::COUNT32) + } + #[doc = "Mode 1: 16-bit Counter"] + #[inline(always)] + pub fn count16(self) -> &'a mut W { + self.variant(MODE_A::COUNT16) + } + #[doc = "Mode 2: Clock/Calendar"] + #[inline(always)] + pub fn clock(self) -> &'a mut W { + self.variant(MODE_A::CLOCK) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u16 & 0x03) << 2); + self.w + } +} +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: CLK_RTC_CNT = GCLK_RTC/1"] + OFF = 0, + #[doc = "1: CLK_RTC_CNT = GCLK_RTC/1"] + DIV1 = 1, + #[doc = "2: CLK_RTC_CNT = GCLK_RTC/2"] + DIV2 = 2, + #[doc = "3: CLK_RTC_CNT = GCLK_RTC/4"] + DIV4 = 3, + #[doc = "4: CLK_RTC_CNT = GCLK_RTC/8"] + DIV8 = 4, + #[doc = "5: CLK_RTC_CNT = GCLK_RTC/16"] + DIV16 = 5, + #[doc = "6: CLK_RTC_CNT = GCLK_RTC/32"] + DIV32 = 6, + #[doc = "7: CLK_RTC_CNT = GCLK_RTC/64"] + DIV64 = 7, + #[doc = "8: CLK_RTC_CNT = GCLK_RTC/128"] + DIV128 = 8, + #[doc = "9: CLK_RTC_CNT = GCLK_RTC/256"] + DIV256 = 9, + #[doc = "10: CLK_RTC_CNT = GCLK_RTC/512"] + DIV512 = 10, + #[doc = "11: CLK_RTC_CNT = GCLK_RTC/1024"] + DIV1024 = 11, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCALER_A::OFF), + 1 => Some(PRESCALER_A::DIV1), + 2 => Some(PRESCALER_A::DIV2), + 3 => Some(PRESCALER_A::DIV4), + 4 => Some(PRESCALER_A::DIV8), + 5 => Some(PRESCALER_A::DIV16), + 6 => Some(PRESCALER_A::DIV32), + 7 => Some(PRESCALER_A::DIV64), + 8 => Some(PRESCALER_A::DIV128), + 9 => Some(PRESCALER_A::DIV256), + 10 => Some(PRESCALER_A::DIV512), + 11 => Some(PRESCALER_A::DIV1024), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == PRESCALER_A::OFF + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == PRESCALER_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == PRESCALER_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == PRESCALER_A::DIV128 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV512`"] + #[inline(always)] + pub fn is_div512(&self) -> bool { + **self == PRESCALER_A::DIV512 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PRESCALER_A::DIV1024 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(PRESCALER_A::OFF) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV32) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV128) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/512"] + #[inline(always)] + pub fn div512(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV512) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 8)) | ((value as u16 & 0x0f) << 8); + self.w + } +} +#[doc = "Field `COUNTSYNC` reader - Count Read Synchronization Enable"] +pub struct COUNTSYNC_R(crate::FieldReader); +impl COUNTSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNTSYNC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNTSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNTSYNC` writer - Count Read Synchronization Enable"] +pub struct COUNTSYNC_W<'a> { + w: &'a mut W, +} +impl<'a> COUNTSYNC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:3 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bits 8:11 - Prescaler"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 15 - Count Read Synchronization Enable"] + #[inline(always)] + pub fn countsync(&self) -> COUNTSYNC_R { + COUNTSYNC_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:3 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bits 8:11 - Prescaler"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Bit 15 - Count Read Synchronization Enable"] + #[inline(always)] + pub fn countsync(&mut self) -> COUNTSYNC_W { + COUNTSYNC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/rtc/mode1/dbgctrl.rs b/pac/atsamc21n/src/rtc/mode1/dbgctrl.rs new file mode 100644 index 000000000000..0383e70d0429 --- /dev/null +++ b/pac/atsamc21n/src/rtc/mode1/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Run During Debug"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Run During Debug"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/rtc/mode1/evctrl.rs b/pac/atsamc21n/src/rtc/mode1/evctrl.rs new file mode 100644 index 000000000000..e15624f828c7 --- /dev/null +++ b/pac/atsamc21n/src/rtc/mode1/evctrl.rs @@ -0,0 +1,583 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PEREO0` reader - Periodic Interval 0 Event Output Enable"] +pub struct PEREO0_R(crate::FieldReader); +impl PEREO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO0` writer - Periodic Interval 0 Event Output Enable"] +pub struct PEREO0_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `PEREO1` reader - Periodic Interval 1 Event Output Enable"] +pub struct PEREO1_R(crate::FieldReader); +impl PEREO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO1` writer - Periodic Interval 1 Event Output Enable"] +pub struct PEREO1_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PEREO2` reader - Periodic Interval 2 Event Output Enable"] +pub struct PEREO2_R(crate::FieldReader); +impl PEREO2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO2` writer - Periodic Interval 2 Event Output Enable"] +pub struct PEREO2_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PEREO3` reader - Periodic Interval 3 Event Output Enable"] +pub struct PEREO3_R(crate::FieldReader); +impl PEREO3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO3` writer - Periodic Interval 3 Event Output Enable"] +pub struct PEREO3_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PEREO4` reader - Periodic Interval 4 Event Output Enable"] +pub struct PEREO4_R(crate::FieldReader); +impl PEREO4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO4` writer - Periodic Interval 4 Event Output Enable"] +pub struct PEREO4_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PEREO5` reader - Periodic Interval 5 Event Output Enable"] +pub struct PEREO5_R(crate::FieldReader); +impl PEREO5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO5` writer - Periodic Interval 5 Event Output Enable"] +pub struct PEREO5_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PEREO6` reader - Periodic Interval 6 Event Output Enable"] +pub struct PEREO6_R(crate::FieldReader); +impl PEREO6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO6` writer - Periodic Interval 6 Event Output Enable"] +pub struct PEREO6_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PEREO7` reader - Periodic Interval 7 Event Output Enable"] +pub struct PEREO7_R(crate::FieldReader); +impl PEREO7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO7` writer - Periodic Interval 7 Event Output Enable"] +pub struct PEREO7_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CMPEO0` reader - Compare 0 Event Output Enable"] +pub struct CMPEO0_R(crate::FieldReader); +impl CMPEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMPEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMPEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMPEO0` writer - Compare 0 Event Output Enable"] +pub struct CMPEO0_W<'a> { + w: &'a mut W, +} +impl<'a> CMPEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `CMPEO1` reader - Compare 1 Event Output Enable"] +pub struct CMPEO1_R(crate::FieldReader); +impl CMPEO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMPEO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMPEO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMPEO1` writer - Compare 1 Event Output Enable"] +pub struct CMPEO1_W<'a> { + w: &'a mut W, +} +impl<'a> CMPEO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `OVFEO` reader - Overflow Event Output Enable"] +pub struct OVFEO_R(crate::FieldReader); +impl OVFEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVFEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVFEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVFEO` writer - Overflow Event Output Enable"] +pub struct OVFEO_W<'a> { + w: &'a mut W, +} +impl<'a> OVFEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Event Output Enable"] + #[inline(always)] + pub fn pereo0(&self) -> PEREO0_R { + PEREO0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Event Output Enable"] + #[inline(always)] + pub fn pereo1(&self) -> PEREO1_R { + PEREO1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Event Output Enable"] + #[inline(always)] + pub fn pereo2(&self) -> PEREO2_R { + PEREO2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Event Output Enable"] + #[inline(always)] + pub fn pereo3(&self) -> PEREO3_R { + PEREO3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Event Output Enable"] + #[inline(always)] + pub fn pereo4(&self) -> PEREO4_R { + PEREO4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Event Output Enable"] + #[inline(always)] + pub fn pereo5(&self) -> PEREO5_R { + PEREO5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Event Output Enable"] + #[inline(always)] + pub fn pereo6(&self) -> PEREO6_R { + PEREO6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Event Output Enable"] + #[inline(always)] + pub fn pereo7(&self) -> PEREO7_R { + PEREO7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Compare 0 Event Output Enable"] + #[inline(always)] + pub fn cmpeo0(&self) -> CMPEO0_R { + CMPEO0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Compare 1 Event Output Enable"] + #[inline(always)] + pub fn cmpeo1(&self) -> CMPEO1_R { + CMPEO1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&self) -> OVFEO_R { + OVFEO_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Event Output Enable"] + #[inline(always)] + pub fn pereo0(&mut self) -> PEREO0_W { + PEREO0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1 Event Output Enable"] + #[inline(always)] + pub fn pereo1(&mut self) -> PEREO1_W { + PEREO1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2 Event Output Enable"] + #[inline(always)] + pub fn pereo2(&mut self) -> PEREO2_W { + PEREO2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3 Event Output Enable"] + #[inline(always)] + pub fn pereo3(&mut self) -> PEREO3_W { + PEREO3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4 Event Output Enable"] + #[inline(always)] + pub fn pereo4(&mut self) -> PEREO4_W { + PEREO4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5 Event Output Enable"] + #[inline(always)] + pub fn pereo5(&mut self) -> PEREO5_W { + PEREO5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6 Event Output Enable"] + #[inline(always)] + pub fn pereo6(&mut self) -> PEREO6_W { + PEREO6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7 Event Output Enable"] + #[inline(always)] + pub fn pereo7(&mut self) -> PEREO7_W { + PEREO7_W { w: self } + } + #[doc = "Bit 8 - Compare 0 Event Output Enable"] + #[inline(always)] + pub fn cmpeo0(&mut self) -> CMPEO0_W { + CMPEO0_W { w: self } + } + #[doc = "Bit 9 - Compare 1 Event Output Enable"] + #[inline(always)] + pub fn cmpeo1(&mut self) -> CMPEO1_W { + CMPEO1_W { w: self } + } + #[doc = "Bit 15 - Overflow Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&mut self) -> OVFEO_W { + OVFEO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/rtc/mode1/freqcorr.rs b/pac/atsamc21n/src/rtc/mode1/freqcorr.rs new file mode 100644 index 000000000000..043ba6f88eb2 --- /dev/null +++ b/pac/atsamc21n/src/rtc/mode1/freqcorr.rs @@ -0,0 +1,150 @@ +#[doc = "Register `FREQCORR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FREQCORR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `VALUE` reader - Correction Value"] +pub struct VALUE_R(crate::FieldReader); +impl VALUE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + VALUE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VALUE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VALUE` writer - Correction Value"] +pub struct VALUE_W<'a> { + w: &'a mut W, +} +impl<'a> VALUE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x7f) | (value as u8 & 0x7f); + self.w + } +} +#[doc = "Field `SIGN` reader - Correction Sign"] +pub struct SIGN_R(crate::FieldReader); +impl SIGN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SIGN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SIGN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SIGN` writer - Correction Sign"] +pub struct SIGN_W<'a> { + w: &'a mut W, +} +impl<'a> SIGN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bits 0:6 - Correction Value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bit 7 - Correction Sign"] + #[inline(always)] + pub fn sign(&self) -> SIGN_R { + SIGN_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:6 - Correction Value"] + #[inline(always)] + pub fn value(&mut self) -> VALUE_W { + VALUE_W { w: self } + } + #[doc = "Bit 7 - Correction Sign"] + #[inline(always)] + pub fn sign(&mut self) -> SIGN_W { + SIGN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Frequency Correction\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [freqcorr](index.html) module"] +pub struct FREQCORR_SPEC; +impl crate::RegisterSpec for FREQCORR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [freqcorr::R](R) reader structure"] +impl crate::Readable for FREQCORR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [freqcorr::W](W) writer structure"] +impl crate::Writable for FREQCORR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets FREQCORR to value 0"] +impl crate::Resettable for FREQCORR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/rtc/mode1/intenclr.rs b/pac/atsamc21n/src/rtc/mode1/intenclr.rs new file mode 100644 index 000000000000..d3fc5b3df34b --- /dev/null +++ b/pac/atsamc21n/src/rtc/mode1/intenclr.rs @@ -0,0 +1,583 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER0` reader - Periodic Interval 0 Interrupt Enable"] +pub struct PER0_R(crate::FieldReader); +impl PER0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER0` writer - Periodic Interval 0 Interrupt Enable"] +pub struct PER0_W<'a> { + w: &'a mut W, +} +impl<'a> PER0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PER1` reader - Periodic Interval 1 Interrupt Enable"] +pub struct PER1_R(crate::FieldReader); +impl PER1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER1` writer - Periodic Interval 1 Interrupt Enable"] +pub struct PER1_W<'a> { + w: &'a mut W, +} +impl<'a> PER1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PER2` reader - Periodic Interval 2 Interrupt Enable"] +pub struct PER2_R(crate::FieldReader); +impl PER2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER2` writer - Periodic Interval 2 Interrupt Enable"] +pub struct PER2_W<'a> { + w: &'a mut W, +} +impl<'a> PER2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PER3` reader - Periodic Interval 3 Interrupt Enable"] +pub struct PER3_R(crate::FieldReader); +impl PER3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER3` writer - Periodic Interval 3 Interrupt Enable"] +pub struct PER3_W<'a> { + w: &'a mut W, +} +impl<'a> PER3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PER4` reader - Periodic Interval 4 Interrupt Enable"] +pub struct PER4_R(crate::FieldReader); +impl PER4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER4` writer - Periodic Interval 4 Interrupt Enable"] +pub struct PER4_W<'a> { + w: &'a mut W, +} +impl<'a> PER4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PER5` reader - Periodic Interval 5 Interrupt Enable"] +pub struct PER5_R(crate::FieldReader); +impl PER5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER5` writer - Periodic Interval 5 Interrupt Enable"] +pub struct PER5_W<'a> { + w: &'a mut W, +} +impl<'a> PER5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PER6` reader - Periodic Interval 6 Interrupt Enable"] +pub struct PER6_R(crate::FieldReader); +impl PER6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER6` writer - Periodic Interval 6 Interrupt Enable"] +pub struct PER6_W<'a> { + w: &'a mut W, +} +impl<'a> PER6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PER7` reader - Periodic Interval 7 Interrupt Enable"] +pub struct PER7_R(crate::FieldReader); +impl PER7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER7` writer - Periodic Interval 7 Interrupt Enable"] +pub struct PER7_W<'a> { + w: &'a mut W, +} +impl<'a> PER7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CMP0` reader - Compare 0 Interrupt Enable"] +pub struct CMP0_R(crate::FieldReader); +impl CMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP0` writer - Compare 0 Interrupt Enable"] +pub struct CMP0_W<'a> { + w: &'a mut W, +} +impl<'a> CMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `CMP1` reader - Compare 1 Interrupt Enable"] +pub struct CMP1_R(crate::FieldReader); +impl CMP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP1` writer - Compare 1 Interrupt Enable"] +pub struct CMP1_W<'a> { + w: &'a mut W, +} +impl<'a> CMP1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + pub fn per0(&self) -> PER0_R { + PER0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + pub fn per1(&self) -> PER1_R { + PER1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + pub fn per2(&self) -> PER2_R { + PER2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + pub fn per3(&self) -> PER3_R { + PER3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + pub fn per4(&self) -> PER4_R { + PER4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + pub fn per5(&self) -> PER5_R { + PER5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + pub fn per6(&self) -> PER6_R { + PER6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + pub fn per7(&self) -> PER7_R { + PER7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&self) -> CMP0_R { + CMP0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Compare 1 Interrupt Enable"] + #[inline(always)] + pub fn cmp1(&self) -> CMP1_R { + CMP1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + pub fn per0(&mut self) -> PER0_W { + PER0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + pub fn per1(&mut self) -> PER1_W { + PER1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + pub fn per2(&mut self) -> PER2_W { + PER2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + pub fn per3(&mut self) -> PER3_W { + PER3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + pub fn per4(&mut self) -> PER4_W { + PER4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + pub fn per5(&mut self) -> PER5_W { + PER5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + pub fn per6(&mut self) -> PER6_W { + PER6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + pub fn per7(&mut self) -> PER7_W { + PER7_W { w: self } + } + #[doc = "Bit 8 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&mut self) -> CMP0_W { + CMP0_W { w: self } + } + #[doc = "Bit 9 - Compare 1 Interrupt Enable"] + #[inline(always)] + pub fn cmp1(&mut self) -> CMP1_W { + CMP1_W { w: self } + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/rtc/mode1/intenset.rs b/pac/atsamc21n/src/rtc/mode1/intenset.rs new file mode 100644 index 000000000000..074cb377926a --- /dev/null +++ b/pac/atsamc21n/src/rtc/mode1/intenset.rs @@ -0,0 +1,583 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER0` reader - Periodic Interval 0 Interrupt Enable"] +pub struct PER0_R(crate::FieldReader); +impl PER0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER0` writer - Periodic Interval 0 Interrupt Enable"] +pub struct PER0_W<'a> { + w: &'a mut W, +} +impl<'a> PER0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PER1` reader - Periodic Interval 1 Interrupt Enable"] +pub struct PER1_R(crate::FieldReader); +impl PER1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER1` writer - Periodic Interval 1 Interrupt Enable"] +pub struct PER1_W<'a> { + w: &'a mut W, +} +impl<'a> PER1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PER2` reader - Periodic Interval 2 Interrupt Enable"] +pub struct PER2_R(crate::FieldReader); +impl PER2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER2` writer - Periodic Interval 2 Interrupt Enable"] +pub struct PER2_W<'a> { + w: &'a mut W, +} +impl<'a> PER2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PER3` reader - Periodic Interval 3 Interrupt Enable"] +pub struct PER3_R(crate::FieldReader); +impl PER3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER3` writer - Periodic Interval 3 Interrupt Enable"] +pub struct PER3_W<'a> { + w: &'a mut W, +} +impl<'a> PER3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PER4` reader - Periodic Interval 4 Interrupt Enable"] +pub struct PER4_R(crate::FieldReader); +impl PER4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER4` writer - Periodic Interval 4 Interrupt Enable"] +pub struct PER4_W<'a> { + w: &'a mut W, +} +impl<'a> PER4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PER5` reader - Periodic Interval 5 Interrupt Enable"] +pub struct PER5_R(crate::FieldReader); +impl PER5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER5` writer - Periodic Interval 5 Interrupt Enable"] +pub struct PER5_W<'a> { + w: &'a mut W, +} +impl<'a> PER5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PER6` reader - Periodic Interval 6 Interrupt Enable"] +pub struct PER6_R(crate::FieldReader); +impl PER6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER6` writer - Periodic Interval 6 Interrupt Enable"] +pub struct PER6_W<'a> { + w: &'a mut W, +} +impl<'a> PER6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PER7` reader - Periodic Interval 7 Interrupt Enable"] +pub struct PER7_R(crate::FieldReader); +impl PER7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER7` writer - Periodic Interval 7 Interrupt Enable"] +pub struct PER7_W<'a> { + w: &'a mut W, +} +impl<'a> PER7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CMP0` reader - Compare 0 Interrupt Enable"] +pub struct CMP0_R(crate::FieldReader); +impl CMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP0` writer - Compare 0 Interrupt Enable"] +pub struct CMP0_W<'a> { + w: &'a mut W, +} +impl<'a> CMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `CMP1` reader - Compare 1 Interrupt Enable"] +pub struct CMP1_R(crate::FieldReader); +impl CMP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP1` writer - Compare 1 Interrupt Enable"] +pub struct CMP1_W<'a> { + w: &'a mut W, +} +impl<'a> CMP1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + pub fn per0(&self) -> PER0_R { + PER0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + pub fn per1(&self) -> PER1_R { + PER1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + pub fn per2(&self) -> PER2_R { + PER2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + pub fn per3(&self) -> PER3_R { + PER3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + pub fn per4(&self) -> PER4_R { + PER4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + pub fn per5(&self) -> PER5_R { + PER5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + pub fn per6(&self) -> PER6_R { + PER6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + pub fn per7(&self) -> PER7_R { + PER7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&self) -> CMP0_R { + CMP0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Compare 1 Interrupt Enable"] + #[inline(always)] + pub fn cmp1(&self) -> CMP1_R { + CMP1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + pub fn per0(&mut self) -> PER0_W { + PER0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + pub fn per1(&mut self) -> PER1_W { + PER1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + pub fn per2(&mut self) -> PER2_W { + PER2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + pub fn per3(&mut self) -> PER3_W { + PER3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + pub fn per4(&mut self) -> PER4_W { + PER4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + pub fn per5(&mut self) -> PER5_W { + PER5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + pub fn per6(&mut self) -> PER6_W { + PER6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + pub fn per7(&mut self) -> PER7_W { + PER7_W { w: self } + } + #[doc = "Bit 8 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&mut self) -> CMP0_W { + CMP0_W { w: self } + } + #[doc = "Bit 9 - Compare 1 Interrupt Enable"] + #[inline(always)] + pub fn cmp1(&mut self) -> CMP1_W { + CMP1_W { w: self } + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/rtc/mode1/intflag.rs b/pac/atsamc21n/src/rtc/mode1/intflag.rs new file mode 100644 index 000000000000..25bce956f46b --- /dev/null +++ b/pac/atsamc21n/src/rtc/mode1/intflag.rs @@ -0,0 +1,583 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER0` reader - Periodic Interval 0"] +pub struct PER0_R(crate::FieldReader); +impl PER0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER0` writer - Periodic Interval 0"] +pub struct PER0_W<'a> { + w: &'a mut W, +} +impl<'a> PER0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PER1` reader - Periodic Interval 1"] +pub struct PER1_R(crate::FieldReader); +impl PER1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER1` writer - Periodic Interval 1"] +pub struct PER1_W<'a> { + w: &'a mut W, +} +impl<'a> PER1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PER2` reader - Periodic Interval 2"] +pub struct PER2_R(crate::FieldReader); +impl PER2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER2` writer - Periodic Interval 2"] +pub struct PER2_W<'a> { + w: &'a mut W, +} +impl<'a> PER2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PER3` reader - Periodic Interval 3"] +pub struct PER3_R(crate::FieldReader); +impl PER3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER3` writer - Periodic Interval 3"] +pub struct PER3_W<'a> { + w: &'a mut W, +} +impl<'a> PER3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PER4` reader - Periodic Interval 4"] +pub struct PER4_R(crate::FieldReader); +impl PER4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER4` writer - Periodic Interval 4"] +pub struct PER4_W<'a> { + w: &'a mut W, +} +impl<'a> PER4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PER5` reader - Periodic Interval 5"] +pub struct PER5_R(crate::FieldReader); +impl PER5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER5` writer - Periodic Interval 5"] +pub struct PER5_W<'a> { + w: &'a mut W, +} +impl<'a> PER5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PER6` reader - Periodic Interval 6"] +pub struct PER6_R(crate::FieldReader); +impl PER6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER6` writer - Periodic Interval 6"] +pub struct PER6_W<'a> { + w: &'a mut W, +} +impl<'a> PER6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PER7` reader - Periodic Interval 7"] +pub struct PER7_R(crate::FieldReader); +impl PER7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER7` writer - Periodic Interval 7"] +pub struct PER7_W<'a> { + w: &'a mut W, +} +impl<'a> PER7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CMP0` reader - Compare 0"] +pub struct CMP0_R(crate::FieldReader); +impl CMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP0` writer - Compare 0"] +pub struct CMP0_W<'a> { + w: &'a mut W, +} +impl<'a> CMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `CMP1` reader - Compare 1"] +pub struct CMP1_R(crate::FieldReader); +impl CMP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP1` writer - Compare 1"] +pub struct CMP1_W<'a> { + w: &'a mut W, +} +impl<'a> CMP1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0"] + #[inline(always)] + pub fn per0(&self) -> PER0_R { + PER0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1"] + #[inline(always)] + pub fn per1(&self) -> PER1_R { + PER1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2"] + #[inline(always)] + pub fn per2(&self) -> PER2_R { + PER2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3"] + #[inline(always)] + pub fn per3(&self) -> PER3_R { + PER3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4"] + #[inline(always)] + pub fn per4(&self) -> PER4_R { + PER4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5"] + #[inline(always)] + pub fn per5(&self) -> PER5_R { + PER5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6"] + #[inline(always)] + pub fn per6(&self) -> PER6_R { + PER6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7"] + #[inline(always)] + pub fn per7(&self) -> PER7_R { + PER7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Compare 0"] + #[inline(always)] + pub fn cmp0(&self) -> CMP0_R { + CMP0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Compare 1"] + #[inline(always)] + pub fn cmp1(&self) -> CMP1_R { + CMP1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0"] + #[inline(always)] + pub fn per0(&mut self) -> PER0_W { + PER0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1"] + #[inline(always)] + pub fn per1(&mut self) -> PER1_W { + PER1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2"] + #[inline(always)] + pub fn per2(&mut self) -> PER2_W { + PER2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3"] + #[inline(always)] + pub fn per3(&mut self) -> PER3_W { + PER3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4"] + #[inline(always)] + pub fn per4(&mut self) -> PER4_W { + PER4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5"] + #[inline(always)] + pub fn per5(&mut self) -> PER5_W { + PER5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6"] + #[inline(always)] + pub fn per6(&mut self) -> PER6_W { + PER6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7"] + #[inline(always)] + pub fn per7(&mut self) -> PER7_W { + PER7_W { w: self } + } + #[doc = "Bit 8 - Compare 0"] + #[inline(always)] + pub fn cmp0(&mut self) -> CMP0_W { + CMP0_W { w: self } + } + #[doc = "Bit 9 - Compare 1"] + #[inline(always)] + pub fn cmp1(&mut self) -> CMP1_W { + CMP1_W { w: self } + } + #[doc = "Bit 15 - Overflow"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/rtc/mode1/per.rs b/pac/atsamc21n/src/rtc/mode1/per.rs new file mode 100644 index 000000000000..c09b31fa30dd --- /dev/null +++ b/pac/atsamc21n/src/rtc/mode1/per.rs @@ -0,0 +1,103 @@ +#[doc = "Register `PER` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PER` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER` reader - Counter Period"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` writer - Counter Period"] +pub struct PER_W<'a> { + w: &'a mut W, +} +impl<'a> PER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Counter Period"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Counter Period"] + #[inline(always)] + pub fn per(&mut self) -> PER_W { + PER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Counter Period\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [per](index.html) module"] +pub struct PER_SPEC; +impl crate::RegisterSpec for PER_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [per::R](R) reader structure"] +impl crate::Readable for PER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [per::W](W) writer structure"] +impl crate::Writable for PER_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PER to value 0"] +impl crate::Resettable for PER_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/rtc/mode1/syncbusy.rs b/pac/atsamc21n/src/rtc/mode1/syncbusy.rs new file mode 100644 index 000000000000..b64c973bafff --- /dev/null +++ b/pac/atsamc21n/src/rtc/mode1/syncbusy.rs @@ -0,0 +1,193 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Bit Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - Enable Bit Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FREQCORR` reader - FREQCORR Register Busy"] +pub struct FREQCORR_R(crate::FieldReader); +impl FREQCORR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FREQCORR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FREQCORR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` reader - COUNT Register Busy"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` reader - PER Register Busy"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP0` reader - COMP 0 Register Busy"] +pub struct COMP0_R(crate::FieldReader); +impl COMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMP1` reader - COMP 1 Register Busy"] +pub struct COMP1_R(crate::FieldReader); +impl COMP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNTSYNC` reader - Count Read Synchronization Enable Bit Busy"] +pub struct COUNTSYNC_R(crate::FieldReader); +impl COUNTSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNTSYNC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNTSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Bit Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable Bit Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - FREQCORR Register Busy"] + #[inline(always)] + pub fn freqcorr(&self) -> FREQCORR_R { + FREQCORR_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - COUNT Register Busy"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - PER Register Busy"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - COMP 0 Register Busy"] + #[inline(always)] + pub fn comp0(&self) -> COMP0_R { + COMP0_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - COMP 1 Register Busy"] + #[inline(always)] + pub fn comp1(&self) -> COMP1_R { + COMP1_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 15 - Count Read Synchronization Enable Bit Busy"] + #[inline(always)] + pub fn countsync(&self) -> COUNTSYNC_R { + COUNTSYNC_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +#[doc = "MODE1 Synchronization Busy Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/rtc/mode2.rs b/pac/atsamc21n/src/rtc/mode2.rs new file mode 100644 index 000000000000..b0bc13e81dbc --- /dev/null +++ b/pac/atsamc21n/src/rtc/mode2.rs @@ -0,0 +1,44 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "MODE2 Control A"] +pub mod ctrla; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "MODE2 Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "MODE2 Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "MODE2 Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "MODE2 Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "MODE2 Synchronization Busy Status"] +pub mod syncbusy; +#[doc = "FREQCORR register accessor: an alias for `Reg`"] +pub type FREQCORR = crate::Reg; +#[doc = "Frequency Correction"] +pub mod freqcorr; +#[doc = "CLOCK register accessor: an alias for `Reg`"] +pub type CLOCK = crate::Reg; +#[doc = "MODE2 Clock Value"] +pub mod clock; +#[doc = "ALARM register accessor: an alias for `Reg`"] +pub type ALARM = crate::Reg; +#[doc = "MODE2_ALARM Alarm n Value"] +pub mod alarm; +#[doc = "MASK register accessor: an alias for `Reg`"] +pub type MASK = crate::Reg; +#[doc = "MODE2_ALARM Alarm n Mask"] +pub mod mask; diff --git a/pac/atsamc21n/src/rtc/mode2/alarm.rs b/pac/atsamc21n/src/rtc/mode2/alarm.rs new file mode 100644 index 000000000000..1242477ea69f --- /dev/null +++ b/pac/atsamc21n/src/rtc/mode2/alarm.rs @@ -0,0 +1,337 @@ +#[doc = "Register `ALARM` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ALARM` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SECOND` reader - Second"] +pub struct SECOND_R(crate::FieldReader); +impl SECOND_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SECOND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SECOND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SECOND` writer - Second"] +pub struct SECOND_W<'a> { + w: &'a mut W, +} +impl<'a> SECOND_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +#[doc = "Field `MINUTE` reader - Minute"] +pub struct MINUTE_R(crate::FieldReader); +impl MINUTE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MINUTE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MINUTE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MINUTE` writer - Minute"] +pub struct MINUTE_W<'a> { + w: &'a mut W, +} +impl<'a> MINUTE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 6)) | ((value as u32 & 0x3f) << 6); + self.w + } +} +#[doc = "Hour\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum HOUR_A { + #[doc = "0: Morning hour"] + AM = 0, + #[doc = "16: Afternoon hour"] + PM = 16, +} +impl From for u8 { + #[inline(always)] + fn from(variant: HOUR_A) -> Self { + variant as _ + } +} +#[doc = "Field `HOUR` reader - Hour"] +pub struct HOUR_R(crate::FieldReader); +impl HOUR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + HOUR_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(HOUR_A::AM), + 16 => Some(HOUR_A::PM), + _ => None, + } + } + #[doc = "Checks if the value of the field is `AM`"] + #[inline(always)] + pub fn is_am(&self) -> bool { + **self == HOUR_A::AM + } + #[doc = "Checks if the value of the field is `PM`"] + #[inline(always)] + pub fn is_pm(&self) -> bool { + **self == HOUR_A::PM + } +} +impl core::ops::Deref for HOUR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HOUR` writer - Hour"] +pub struct HOUR_W<'a> { + w: &'a mut W, +} +impl<'a> HOUR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: HOUR_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Morning hour"] + #[inline(always)] + pub fn am(self) -> &'a mut W { + self.variant(HOUR_A::AM) + } + #[doc = "Afternoon hour"] + #[inline(always)] + pub fn pm(self) -> &'a mut W { + self.variant(HOUR_A::PM) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 12)) | ((value as u32 & 0x1f) << 12); + self.w + } +} +#[doc = "Field `DAY` reader - Day"] +pub struct DAY_R(crate::FieldReader); +impl DAY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DAY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DAY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DAY` writer - Day"] +pub struct DAY_W<'a> { + w: &'a mut W, +} +impl<'a> DAY_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 17)) | ((value as u32 & 0x1f) << 17); + self.w + } +} +#[doc = "Field `MONTH` reader - Month"] +pub struct MONTH_R(crate::FieldReader); +impl MONTH_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MONTH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MONTH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MONTH` writer - Month"] +pub struct MONTH_W<'a> { + w: &'a mut W, +} +impl<'a> MONTH_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 22)) | ((value as u32 & 0x0f) << 22); + self.w + } +} +#[doc = "Field `YEAR` reader - Year"] +pub struct YEAR_R(crate::FieldReader); +impl YEAR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + YEAR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for YEAR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `YEAR` writer - Year"] +pub struct YEAR_W<'a> { + w: &'a mut W, +} +impl<'a> YEAR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 26)) | ((value as u32 & 0x3f) << 26); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Second"] + #[inline(always)] + pub fn second(&self) -> SECOND_R { + SECOND_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:11 - Minute"] + #[inline(always)] + pub fn minute(&self) -> MINUTE_R { + MINUTE_R::new(((self.bits >> 6) & 0x3f) as u8) + } + #[doc = "Bits 12:16 - Hour"] + #[inline(always)] + pub fn hour(&self) -> HOUR_R { + HOUR_R::new(((self.bits >> 12) & 0x1f) as u8) + } + #[doc = "Bits 17:21 - Day"] + #[inline(always)] + pub fn day(&self) -> DAY_R { + DAY_R::new(((self.bits >> 17) & 0x1f) as u8) + } + #[doc = "Bits 22:25 - Month"] + #[inline(always)] + pub fn month(&self) -> MONTH_R { + MONTH_R::new(((self.bits >> 22) & 0x0f) as u8) + } + #[doc = "Bits 26:31 - Year"] + #[inline(always)] + pub fn year(&self) -> YEAR_R { + YEAR_R::new(((self.bits >> 26) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - Second"] + #[inline(always)] + pub fn second(&mut self) -> SECOND_W { + SECOND_W { w: self } + } + #[doc = "Bits 6:11 - Minute"] + #[inline(always)] + pub fn minute(&mut self) -> MINUTE_W { + MINUTE_W { w: self } + } + #[doc = "Bits 12:16 - Hour"] + #[inline(always)] + pub fn hour(&mut self) -> HOUR_W { + HOUR_W { w: self } + } + #[doc = "Bits 17:21 - Day"] + #[inline(always)] + pub fn day(&mut self) -> DAY_W { + DAY_W { w: self } + } + #[doc = "Bits 22:25 - Month"] + #[inline(always)] + pub fn month(&mut self) -> MONTH_W { + MONTH_W { w: self } + } + #[doc = "Bits 26:31 - Year"] + #[inline(always)] + pub fn year(&mut self) -> YEAR_W { + YEAR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2_ALARM Alarm n Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [alarm](index.html) module"] +pub struct ALARM_SPEC; +impl crate::RegisterSpec for ALARM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [alarm::R](R) reader structure"] +impl crate::Readable for ALARM_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [alarm::W](W) writer structure"] +impl crate::Writable for ALARM_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ALARM to value 0"] +impl crate::Resettable for ALARM_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/rtc/mode2/clock.rs b/pac/atsamc21n/src/rtc/mode2/clock.rs new file mode 100644 index 000000000000..3f364ff8e57b --- /dev/null +++ b/pac/atsamc21n/src/rtc/mode2/clock.rs @@ -0,0 +1,337 @@ +#[doc = "Register `CLOCK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CLOCK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SECOND` reader - Second"] +pub struct SECOND_R(crate::FieldReader); +impl SECOND_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SECOND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SECOND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SECOND` writer - Second"] +pub struct SECOND_W<'a> { + w: &'a mut W, +} +impl<'a> SECOND_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +#[doc = "Field `MINUTE` reader - Minute"] +pub struct MINUTE_R(crate::FieldReader); +impl MINUTE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MINUTE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MINUTE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MINUTE` writer - Minute"] +pub struct MINUTE_W<'a> { + w: &'a mut W, +} +impl<'a> MINUTE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 6)) | ((value as u32 & 0x3f) << 6); + self.w + } +} +#[doc = "Hour\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum HOUR_A { + #[doc = "0: AM when CLKREP in 12-hour"] + AM = 0, + #[doc = "16: PM when CLKREP in 12-hour"] + PM = 16, +} +impl From for u8 { + #[inline(always)] + fn from(variant: HOUR_A) -> Self { + variant as _ + } +} +#[doc = "Field `HOUR` reader - Hour"] +pub struct HOUR_R(crate::FieldReader); +impl HOUR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + HOUR_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(HOUR_A::AM), + 16 => Some(HOUR_A::PM), + _ => None, + } + } + #[doc = "Checks if the value of the field is `AM`"] + #[inline(always)] + pub fn is_am(&self) -> bool { + **self == HOUR_A::AM + } + #[doc = "Checks if the value of the field is `PM`"] + #[inline(always)] + pub fn is_pm(&self) -> bool { + **self == HOUR_A::PM + } +} +impl core::ops::Deref for HOUR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HOUR` writer - Hour"] +pub struct HOUR_W<'a> { + w: &'a mut W, +} +impl<'a> HOUR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: HOUR_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "AM when CLKREP in 12-hour"] + #[inline(always)] + pub fn am(self) -> &'a mut W { + self.variant(HOUR_A::AM) + } + #[doc = "PM when CLKREP in 12-hour"] + #[inline(always)] + pub fn pm(self) -> &'a mut W { + self.variant(HOUR_A::PM) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 12)) | ((value as u32 & 0x1f) << 12); + self.w + } +} +#[doc = "Field `DAY` reader - Day"] +pub struct DAY_R(crate::FieldReader); +impl DAY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DAY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DAY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DAY` writer - Day"] +pub struct DAY_W<'a> { + w: &'a mut W, +} +impl<'a> DAY_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 17)) | ((value as u32 & 0x1f) << 17); + self.w + } +} +#[doc = "Field `MONTH` reader - Month"] +pub struct MONTH_R(crate::FieldReader); +impl MONTH_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MONTH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MONTH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MONTH` writer - Month"] +pub struct MONTH_W<'a> { + w: &'a mut W, +} +impl<'a> MONTH_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 22)) | ((value as u32 & 0x0f) << 22); + self.w + } +} +#[doc = "Field `YEAR` reader - Year"] +pub struct YEAR_R(crate::FieldReader); +impl YEAR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + YEAR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for YEAR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `YEAR` writer - Year"] +pub struct YEAR_W<'a> { + w: &'a mut W, +} +impl<'a> YEAR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 26)) | ((value as u32 & 0x3f) << 26); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Second"] + #[inline(always)] + pub fn second(&self) -> SECOND_R { + SECOND_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:11 - Minute"] + #[inline(always)] + pub fn minute(&self) -> MINUTE_R { + MINUTE_R::new(((self.bits >> 6) & 0x3f) as u8) + } + #[doc = "Bits 12:16 - Hour"] + #[inline(always)] + pub fn hour(&self) -> HOUR_R { + HOUR_R::new(((self.bits >> 12) & 0x1f) as u8) + } + #[doc = "Bits 17:21 - Day"] + #[inline(always)] + pub fn day(&self) -> DAY_R { + DAY_R::new(((self.bits >> 17) & 0x1f) as u8) + } + #[doc = "Bits 22:25 - Month"] + #[inline(always)] + pub fn month(&self) -> MONTH_R { + MONTH_R::new(((self.bits >> 22) & 0x0f) as u8) + } + #[doc = "Bits 26:31 - Year"] + #[inline(always)] + pub fn year(&self) -> YEAR_R { + YEAR_R::new(((self.bits >> 26) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - Second"] + #[inline(always)] + pub fn second(&mut self) -> SECOND_W { + SECOND_W { w: self } + } + #[doc = "Bits 6:11 - Minute"] + #[inline(always)] + pub fn minute(&mut self) -> MINUTE_W { + MINUTE_W { w: self } + } + #[doc = "Bits 12:16 - Hour"] + #[inline(always)] + pub fn hour(&mut self) -> HOUR_W { + HOUR_W { w: self } + } + #[doc = "Bits 17:21 - Day"] + #[inline(always)] + pub fn day(&mut self) -> DAY_W { + DAY_W { w: self } + } + #[doc = "Bits 22:25 - Month"] + #[inline(always)] + pub fn month(&mut self) -> MONTH_W { + MONTH_W { w: self } + } + #[doc = "Bits 26:31 - Year"] + #[inline(always)] + pub fn year(&mut self) -> YEAR_W { + YEAR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2 Clock Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clock](index.html) module"] +pub struct CLOCK_SPEC; +impl crate::RegisterSpec for CLOCK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [clock::R](R) reader structure"] +impl crate::Readable for CLOCK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [clock::W](W) writer structure"] +impl crate::Writable for CLOCK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CLOCK to value 0"] +impl crate::Resettable for CLOCK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/rtc/mode2/ctrla.rs b/pac/atsamc21n/src/rtc/mode2/ctrla.rs new file mode 100644 index 000000000000..fc4bfda16bd8 --- /dev/null +++ b/pac/atsamc21n/src/rtc/mode2/ctrla.rs @@ -0,0 +1,616 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: Mode 0: 32-bit Counter"] + COUNT32 = 0, + #[doc = "1: Mode 1: 16-bit Counter"] + COUNT16 = 1, + #[doc = "2: Mode 2: Clock/Calendar"] + CLOCK = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::COUNT32), + 1 => Some(MODE_A::COUNT16), + 2 => Some(MODE_A::CLOCK), + _ => None, + } + } + #[doc = "Checks if the value of the field is `COUNT32`"] + #[inline(always)] + pub fn is_count32(&self) -> bool { + **self == MODE_A::COUNT32 + } + #[doc = "Checks if the value of the field is `COUNT16`"] + #[inline(always)] + pub fn is_count16(&self) -> bool { + **self == MODE_A::COUNT16 + } + #[doc = "Checks if the value of the field is `CLOCK`"] + #[inline(always)] + pub fn is_clock(&self) -> bool { + **self == MODE_A::CLOCK + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Mode 0: 32-bit Counter"] + #[inline(always)] + pub fn count32(self) -> &'a mut W { + self.variant(MODE_A::COUNT32) + } + #[doc = "Mode 1: 16-bit Counter"] + #[inline(always)] + pub fn count16(self) -> &'a mut W { + self.variant(MODE_A::COUNT16) + } + #[doc = "Mode 2: Clock/Calendar"] + #[inline(always)] + pub fn clock(self) -> &'a mut W { + self.variant(MODE_A::CLOCK) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u16 & 0x03) << 2); + self.w + } +} +#[doc = "Field `CLKREP` reader - Clock Representation"] +pub struct CLKREP_R(crate::FieldReader); +impl CLKREP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKREP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKREP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKREP` writer - Clock Representation"] +pub struct CLKREP_W<'a> { + w: &'a mut W, +} +impl<'a> CLKREP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `MATCHCLR` reader - Clear on Match"] +pub struct MATCHCLR_R(crate::FieldReader); +impl MATCHCLR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MATCHCLR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MATCHCLR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MATCHCLR` writer - Clear on Match"] +pub struct MATCHCLR_W<'a> { + w: &'a mut W, +} +impl<'a> MATCHCLR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: CLK_RTC_CNT = GCLK_RTC/1"] + OFF = 0, + #[doc = "1: CLK_RTC_CNT = GCLK_RTC/1"] + DIV1 = 1, + #[doc = "2: CLK_RTC_CNT = GCLK_RTC/2"] + DIV2 = 2, + #[doc = "3: CLK_RTC_CNT = GCLK_RTC/4"] + DIV4 = 3, + #[doc = "4: CLK_RTC_CNT = GCLK_RTC/8"] + DIV8 = 4, + #[doc = "5: CLK_RTC_CNT = GCLK_RTC/16"] + DIV16 = 5, + #[doc = "6: CLK_RTC_CNT = GCLK_RTC/32"] + DIV32 = 6, + #[doc = "7: CLK_RTC_CNT = GCLK_RTC/64"] + DIV64 = 7, + #[doc = "8: CLK_RTC_CNT = GCLK_RTC/128"] + DIV128 = 8, + #[doc = "9: CLK_RTC_CNT = GCLK_RTC/256"] + DIV256 = 9, + #[doc = "10: CLK_RTC_CNT = GCLK_RTC/512"] + DIV512 = 10, + #[doc = "11: CLK_RTC_CNT = GCLK_RTC/1024"] + DIV1024 = 11, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCALER_A::OFF), + 1 => Some(PRESCALER_A::DIV1), + 2 => Some(PRESCALER_A::DIV2), + 3 => Some(PRESCALER_A::DIV4), + 4 => Some(PRESCALER_A::DIV8), + 5 => Some(PRESCALER_A::DIV16), + 6 => Some(PRESCALER_A::DIV32), + 7 => Some(PRESCALER_A::DIV64), + 8 => Some(PRESCALER_A::DIV128), + 9 => Some(PRESCALER_A::DIV256), + 10 => Some(PRESCALER_A::DIV512), + 11 => Some(PRESCALER_A::DIV1024), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == PRESCALER_A::OFF + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == PRESCALER_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == PRESCALER_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == PRESCALER_A::DIV128 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV512`"] + #[inline(always)] + pub fn is_div512(&self) -> bool { + **self == PRESCALER_A::DIV512 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PRESCALER_A::DIV1024 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(PRESCALER_A::OFF) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV32) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV128) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/512"] + #[inline(always)] + pub fn div512(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV512) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 8)) | ((value as u16 & 0x0f) << 8); + self.w + } +} +#[doc = "Field `CLOCKSYNC` reader - Clock Read Synchronization Enable"] +pub struct CLOCKSYNC_R(crate::FieldReader); +impl CLOCKSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLOCKSYNC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLOCKSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLOCKSYNC` writer - Clock Read Synchronization Enable"] +pub struct CLOCKSYNC_W<'a> { + w: &'a mut W, +} +impl<'a> CLOCKSYNC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:3 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bit 6 - Clock Representation"] + #[inline(always)] + pub fn clkrep(&self) -> CLKREP_R { + CLKREP_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Clear on Match"] + #[inline(always)] + pub fn matchclr(&self) -> MATCHCLR_R { + MATCHCLR_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:11 - Prescaler"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 15 - Clock Read Synchronization Enable"] + #[inline(always)] + pub fn clocksync(&self) -> CLOCKSYNC_R { + CLOCKSYNC_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:3 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 6 - Clock Representation"] + #[inline(always)] + pub fn clkrep(&mut self) -> CLKREP_W { + CLKREP_W { w: self } + } + #[doc = "Bit 7 - Clear on Match"] + #[inline(always)] + pub fn matchclr(&mut self) -> MATCHCLR_W { + MATCHCLR_W { w: self } + } + #[doc = "Bits 8:11 - Prescaler"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Bit 15 - Clock Read Synchronization Enable"] + #[inline(always)] + pub fn clocksync(&mut self) -> CLOCKSYNC_W { + CLOCKSYNC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2 Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/rtc/mode2/dbgctrl.rs b/pac/atsamc21n/src/rtc/mode2/dbgctrl.rs new file mode 100644 index 000000000000..0383e70d0429 --- /dev/null +++ b/pac/atsamc21n/src/rtc/mode2/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Run During Debug"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Run During Debug"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/rtc/mode2/evctrl.rs b/pac/atsamc21n/src/rtc/mode2/evctrl.rs new file mode 100644 index 000000000000..17bc3da4a79e --- /dev/null +++ b/pac/atsamc21n/src/rtc/mode2/evctrl.rs @@ -0,0 +1,536 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PEREO0` reader - Periodic Interval 0 Event Output Enable"] +pub struct PEREO0_R(crate::FieldReader); +impl PEREO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO0` writer - Periodic Interval 0 Event Output Enable"] +pub struct PEREO0_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `PEREO1` reader - Periodic Interval 1 Event Output Enable"] +pub struct PEREO1_R(crate::FieldReader); +impl PEREO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO1` writer - Periodic Interval 1 Event Output Enable"] +pub struct PEREO1_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PEREO2` reader - Periodic Interval 2 Event Output Enable"] +pub struct PEREO2_R(crate::FieldReader); +impl PEREO2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO2` writer - Periodic Interval 2 Event Output Enable"] +pub struct PEREO2_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PEREO3` reader - Periodic Interval 3 Event Output Enable"] +pub struct PEREO3_R(crate::FieldReader); +impl PEREO3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO3` writer - Periodic Interval 3 Event Output Enable"] +pub struct PEREO3_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PEREO4` reader - Periodic Interval 4 Event Output Enable"] +pub struct PEREO4_R(crate::FieldReader); +impl PEREO4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO4` writer - Periodic Interval 4 Event Output Enable"] +pub struct PEREO4_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PEREO5` reader - Periodic Interval 5 Event Output Enable"] +pub struct PEREO5_R(crate::FieldReader); +impl PEREO5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO5` writer - Periodic Interval 5 Event Output Enable"] +pub struct PEREO5_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PEREO6` reader - Periodic Interval 6 Event Output Enable"] +pub struct PEREO6_R(crate::FieldReader); +impl PEREO6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO6` writer - Periodic Interval 6 Event Output Enable"] +pub struct PEREO6_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PEREO7` reader - Periodic Interval 7 Event Output Enable"] +pub struct PEREO7_R(crate::FieldReader); +impl PEREO7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEREO7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEREO7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEREO7` writer - Periodic Interval 7 Event Output Enable"] +pub struct PEREO7_W<'a> { + w: &'a mut W, +} +impl<'a> PEREO7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `ALARMEO0` reader - Alarm 0 Event Output Enable"] +pub struct ALARMEO0_R(crate::FieldReader); +impl ALARMEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALARMEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALARMEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALARMEO0` writer - Alarm 0 Event Output Enable"] +pub struct ALARMEO0_W<'a> { + w: &'a mut W, +} +impl<'a> ALARMEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `OVFEO` reader - Overflow Event Output Enable"] +pub struct OVFEO_R(crate::FieldReader); +impl OVFEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVFEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVFEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVFEO` writer - Overflow Event Output Enable"] +pub struct OVFEO_W<'a> { + w: &'a mut W, +} +impl<'a> OVFEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Event Output Enable"] + #[inline(always)] + pub fn pereo0(&self) -> PEREO0_R { + PEREO0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Event Output Enable"] + #[inline(always)] + pub fn pereo1(&self) -> PEREO1_R { + PEREO1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Event Output Enable"] + #[inline(always)] + pub fn pereo2(&self) -> PEREO2_R { + PEREO2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Event Output Enable"] + #[inline(always)] + pub fn pereo3(&self) -> PEREO3_R { + PEREO3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Event Output Enable"] + #[inline(always)] + pub fn pereo4(&self) -> PEREO4_R { + PEREO4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Event Output Enable"] + #[inline(always)] + pub fn pereo5(&self) -> PEREO5_R { + PEREO5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Event Output Enable"] + #[inline(always)] + pub fn pereo6(&self) -> PEREO6_R { + PEREO6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Event Output Enable"] + #[inline(always)] + pub fn pereo7(&self) -> PEREO7_R { + PEREO7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Alarm 0 Event Output Enable"] + #[inline(always)] + pub fn alarmeo0(&self) -> ALARMEO0_R { + ALARMEO0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&self) -> OVFEO_R { + OVFEO_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Event Output Enable"] + #[inline(always)] + pub fn pereo0(&mut self) -> PEREO0_W { + PEREO0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1 Event Output Enable"] + #[inline(always)] + pub fn pereo1(&mut self) -> PEREO1_W { + PEREO1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2 Event Output Enable"] + #[inline(always)] + pub fn pereo2(&mut self) -> PEREO2_W { + PEREO2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3 Event Output Enable"] + #[inline(always)] + pub fn pereo3(&mut self) -> PEREO3_W { + PEREO3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4 Event Output Enable"] + #[inline(always)] + pub fn pereo4(&mut self) -> PEREO4_W { + PEREO4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5 Event Output Enable"] + #[inline(always)] + pub fn pereo5(&mut self) -> PEREO5_W { + PEREO5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6 Event Output Enable"] + #[inline(always)] + pub fn pereo6(&mut self) -> PEREO6_W { + PEREO6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7 Event Output Enable"] + #[inline(always)] + pub fn pereo7(&mut self) -> PEREO7_W { + PEREO7_W { w: self } + } + #[doc = "Bit 8 - Alarm 0 Event Output Enable"] + #[inline(always)] + pub fn alarmeo0(&mut self) -> ALARMEO0_W { + ALARMEO0_W { w: self } + } + #[doc = "Bit 15 - Overflow Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&mut self) -> OVFEO_W { + OVFEO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2 Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/rtc/mode2/freqcorr.rs b/pac/atsamc21n/src/rtc/mode2/freqcorr.rs new file mode 100644 index 000000000000..043ba6f88eb2 --- /dev/null +++ b/pac/atsamc21n/src/rtc/mode2/freqcorr.rs @@ -0,0 +1,150 @@ +#[doc = "Register `FREQCORR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FREQCORR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `VALUE` reader - Correction Value"] +pub struct VALUE_R(crate::FieldReader); +impl VALUE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + VALUE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VALUE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VALUE` writer - Correction Value"] +pub struct VALUE_W<'a> { + w: &'a mut W, +} +impl<'a> VALUE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x7f) | (value as u8 & 0x7f); + self.w + } +} +#[doc = "Field `SIGN` reader - Correction Sign"] +pub struct SIGN_R(crate::FieldReader); +impl SIGN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SIGN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SIGN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SIGN` writer - Correction Sign"] +pub struct SIGN_W<'a> { + w: &'a mut W, +} +impl<'a> SIGN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bits 0:6 - Correction Value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bit 7 - Correction Sign"] + #[inline(always)] + pub fn sign(&self) -> SIGN_R { + SIGN_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:6 - Correction Value"] + #[inline(always)] + pub fn value(&mut self) -> VALUE_W { + VALUE_W { w: self } + } + #[doc = "Bit 7 - Correction Sign"] + #[inline(always)] + pub fn sign(&mut self) -> SIGN_W { + SIGN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Frequency Correction\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [freqcorr](index.html) module"] +pub struct FREQCORR_SPEC; +impl crate::RegisterSpec for FREQCORR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [freqcorr::R](R) reader structure"] +impl crate::Readable for FREQCORR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [freqcorr::W](W) writer structure"] +impl crate::Writable for FREQCORR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets FREQCORR to value 0"] +impl crate::Resettable for FREQCORR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/rtc/mode2/intenclr.rs b/pac/atsamc21n/src/rtc/mode2/intenclr.rs new file mode 100644 index 000000000000..84aa17f78a0e --- /dev/null +++ b/pac/atsamc21n/src/rtc/mode2/intenclr.rs @@ -0,0 +1,536 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER0` reader - Periodic Interval 0 Interrupt Enable"] +pub struct PER0_R(crate::FieldReader); +impl PER0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER0` writer - Periodic Interval 0 Interrupt Enable"] +pub struct PER0_W<'a> { + w: &'a mut W, +} +impl<'a> PER0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PER1` reader - Periodic Interval 1 Interrupt Enable"] +pub struct PER1_R(crate::FieldReader); +impl PER1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER1` writer - Periodic Interval 1 Interrupt Enable"] +pub struct PER1_W<'a> { + w: &'a mut W, +} +impl<'a> PER1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PER2` reader - Periodic Interval 2 Interrupt Enable"] +pub struct PER2_R(crate::FieldReader); +impl PER2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER2` writer - Periodic Interval 2 Interrupt Enable"] +pub struct PER2_W<'a> { + w: &'a mut W, +} +impl<'a> PER2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PER3` reader - Periodic Interval 3 Interrupt Enable"] +pub struct PER3_R(crate::FieldReader); +impl PER3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER3` writer - Periodic Interval 3 Interrupt Enable"] +pub struct PER3_W<'a> { + w: &'a mut W, +} +impl<'a> PER3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PER4` reader - Periodic Interval 4 Interrupt Enable"] +pub struct PER4_R(crate::FieldReader); +impl PER4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER4` writer - Periodic Interval 4 Interrupt Enable"] +pub struct PER4_W<'a> { + w: &'a mut W, +} +impl<'a> PER4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PER5` reader - Periodic Interval 5 Interrupt Enable"] +pub struct PER5_R(crate::FieldReader); +impl PER5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER5` writer - Periodic Interval 5 Interrupt Enable"] +pub struct PER5_W<'a> { + w: &'a mut W, +} +impl<'a> PER5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PER6` reader - Periodic Interval 6 Interrupt Enable"] +pub struct PER6_R(crate::FieldReader); +impl PER6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER6` writer - Periodic Interval 6 Interrupt Enable"] +pub struct PER6_W<'a> { + w: &'a mut W, +} +impl<'a> PER6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PER7` reader - Periodic Interval 7 Interrupt Enable"] +pub struct PER7_R(crate::FieldReader); +impl PER7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER7` writer - Periodic Interval 7 Interrupt Enable"] +pub struct PER7_W<'a> { + w: &'a mut W, +} +impl<'a> PER7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `ALARM0` reader - Alarm 0 Interrupt Enable"] +pub struct ALARM0_R(crate::FieldReader); +impl ALARM0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALARM0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALARM0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALARM0` writer - Alarm 0 Interrupt Enable"] +pub struct ALARM0_W<'a> { + w: &'a mut W, +} +impl<'a> ALARM0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + pub fn per0(&self) -> PER0_R { + PER0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + pub fn per1(&self) -> PER1_R { + PER1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + pub fn per2(&self) -> PER2_R { + PER2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + pub fn per3(&self) -> PER3_R { + PER3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + pub fn per4(&self) -> PER4_R { + PER4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + pub fn per5(&self) -> PER5_R { + PER5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + pub fn per6(&self) -> PER6_R { + PER6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + pub fn per7(&self) -> PER7_R { + PER7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Alarm 0 Interrupt Enable"] + #[inline(always)] + pub fn alarm0(&self) -> ALARM0_R { + ALARM0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + pub fn per0(&mut self) -> PER0_W { + PER0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + pub fn per1(&mut self) -> PER1_W { + PER1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + pub fn per2(&mut self) -> PER2_W { + PER2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + pub fn per3(&mut self) -> PER3_W { + PER3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + pub fn per4(&mut self) -> PER4_W { + PER4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + pub fn per5(&mut self) -> PER5_W { + PER5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + pub fn per6(&mut self) -> PER6_W { + PER6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + pub fn per7(&mut self) -> PER7_W { + PER7_W { w: self } + } + #[doc = "Bit 8 - Alarm 0 Interrupt Enable"] + #[inline(always)] + pub fn alarm0(&mut self) -> ALARM0_W { + ALARM0_W { w: self } + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2 Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/rtc/mode2/intenset.rs b/pac/atsamc21n/src/rtc/mode2/intenset.rs new file mode 100644 index 000000000000..a41687fa1ee5 --- /dev/null +++ b/pac/atsamc21n/src/rtc/mode2/intenset.rs @@ -0,0 +1,536 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER0` reader - Periodic Interval 0 Enable"] +pub struct PER0_R(crate::FieldReader); +impl PER0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER0` writer - Periodic Interval 0 Enable"] +pub struct PER0_W<'a> { + w: &'a mut W, +} +impl<'a> PER0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PER1` reader - Periodic Interval 1 Enable"] +pub struct PER1_R(crate::FieldReader); +impl PER1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER1` writer - Periodic Interval 1 Enable"] +pub struct PER1_W<'a> { + w: &'a mut W, +} +impl<'a> PER1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PER2` reader - Periodic Interval 2 Enable"] +pub struct PER2_R(crate::FieldReader); +impl PER2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER2` writer - Periodic Interval 2 Enable"] +pub struct PER2_W<'a> { + w: &'a mut W, +} +impl<'a> PER2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PER3` reader - Periodic Interval 3 Enable"] +pub struct PER3_R(crate::FieldReader); +impl PER3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER3` writer - Periodic Interval 3 Enable"] +pub struct PER3_W<'a> { + w: &'a mut W, +} +impl<'a> PER3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PER4` reader - Periodic Interval 4 Enable"] +pub struct PER4_R(crate::FieldReader); +impl PER4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER4` writer - Periodic Interval 4 Enable"] +pub struct PER4_W<'a> { + w: &'a mut W, +} +impl<'a> PER4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PER5` reader - Periodic Interval 5 Enable"] +pub struct PER5_R(crate::FieldReader); +impl PER5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER5` writer - Periodic Interval 5 Enable"] +pub struct PER5_W<'a> { + w: &'a mut W, +} +impl<'a> PER5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PER6` reader - Periodic Interval 6 Enable"] +pub struct PER6_R(crate::FieldReader); +impl PER6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER6` writer - Periodic Interval 6 Enable"] +pub struct PER6_W<'a> { + w: &'a mut W, +} +impl<'a> PER6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PER7` reader - Periodic Interval 7 Enable"] +pub struct PER7_R(crate::FieldReader); +impl PER7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER7` writer - Periodic Interval 7 Enable"] +pub struct PER7_W<'a> { + w: &'a mut W, +} +impl<'a> PER7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `ALARM0` reader - Alarm 0 Interrupt Enable"] +pub struct ALARM0_R(crate::FieldReader); +impl ALARM0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALARM0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALARM0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALARM0` writer - Alarm 0 Interrupt Enable"] +pub struct ALARM0_W<'a> { + w: &'a mut W, +} +impl<'a> ALARM0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Enable"] + #[inline(always)] + pub fn per0(&self) -> PER0_R { + PER0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Enable"] + #[inline(always)] + pub fn per1(&self) -> PER1_R { + PER1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Enable"] + #[inline(always)] + pub fn per2(&self) -> PER2_R { + PER2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Enable"] + #[inline(always)] + pub fn per3(&self) -> PER3_R { + PER3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Enable"] + #[inline(always)] + pub fn per4(&self) -> PER4_R { + PER4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Enable"] + #[inline(always)] + pub fn per5(&self) -> PER5_R { + PER5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Enable"] + #[inline(always)] + pub fn per6(&self) -> PER6_R { + PER6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Enable"] + #[inline(always)] + pub fn per7(&self) -> PER7_R { + PER7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Alarm 0 Interrupt Enable"] + #[inline(always)] + pub fn alarm0(&self) -> ALARM0_R { + ALARM0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Enable"] + #[inline(always)] + pub fn per0(&mut self) -> PER0_W { + PER0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1 Enable"] + #[inline(always)] + pub fn per1(&mut self) -> PER1_W { + PER1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2 Enable"] + #[inline(always)] + pub fn per2(&mut self) -> PER2_W { + PER2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3 Enable"] + #[inline(always)] + pub fn per3(&mut self) -> PER3_W { + PER3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4 Enable"] + #[inline(always)] + pub fn per4(&mut self) -> PER4_W { + PER4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5 Enable"] + #[inline(always)] + pub fn per5(&mut self) -> PER5_W { + PER5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6 Enable"] + #[inline(always)] + pub fn per6(&mut self) -> PER6_W { + PER6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7 Enable"] + #[inline(always)] + pub fn per7(&mut self) -> PER7_W { + PER7_W { w: self } + } + #[doc = "Bit 8 - Alarm 0 Interrupt Enable"] + #[inline(always)] + pub fn alarm0(&mut self) -> ALARM0_W { + ALARM0_W { w: self } + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2 Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/rtc/mode2/intflag.rs b/pac/atsamc21n/src/rtc/mode2/intflag.rs new file mode 100644 index 000000000000..8de0f3efd1d0 --- /dev/null +++ b/pac/atsamc21n/src/rtc/mode2/intflag.rs @@ -0,0 +1,536 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER0` reader - Periodic Interval 0"] +pub struct PER0_R(crate::FieldReader); +impl PER0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER0` writer - Periodic Interval 0"] +pub struct PER0_W<'a> { + w: &'a mut W, +} +impl<'a> PER0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PER1` reader - Periodic Interval 1"] +pub struct PER1_R(crate::FieldReader); +impl PER1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER1` writer - Periodic Interval 1"] +pub struct PER1_W<'a> { + w: &'a mut W, +} +impl<'a> PER1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PER2` reader - Periodic Interval 2"] +pub struct PER2_R(crate::FieldReader); +impl PER2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER2` writer - Periodic Interval 2"] +pub struct PER2_W<'a> { + w: &'a mut W, +} +impl<'a> PER2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PER3` reader - Periodic Interval 3"] +pub struct PER3_R(crate::FieldReader); +impl PER3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER3` writer - Periodic Interval 3"] +pub struct PER3_W<'a> { + w: &'a mut W, +} +impl<'a> PER3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PER4` reader - Periodic Interval 4"] +pub struct PER4_R(crate::FieldReader); +impl PER4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER4` writer - Periodic Interval 4"] +pub struct PER4_W<'a> { + w: &'a mut W, +} +impl<'a> PER4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PER5` reader - Periodic Interval 5"] +pub struct PER5_R(crate::FieldReader); +impl PER5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER5` writer - Periodic Interval 5"] +pub struct PER5_W<'a> { + w: &'a mut W, +} +impl<'a> PER5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PER6` reader - Periodic Interval 6"] +pub struct PER6_R(crate::FieldReader); +impl PER6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER6` writer - Periodic Interval 6"] +pub struct PER6_W<'a> { + w: &'a mut W, +} +impl<'a> PER6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PER7` reader - Periodic Interval 7"] +pub struct PER7_R(crate::FieldReader); +impl PER7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER7` writer - Periodic Interval 7"] +pub struct PER7_W<'a> { + w: &'a mut W, +} +impl<'a> PER7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `ALARM0` reader - Alarm 0"] +pub struct ALARM0_R(crate::FieldReader); +impl ALARM0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALARM0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALARM0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALARM0` writer - Alarm 0"] +pub struct ALARM0_W<'a> { + w: &'a mut W, +} +impl<'a> ALARM0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Periodic Interval 0"] + #[inline(always)] + pub fn per0(&self) -> PER0_R { + PER0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1"] + #[inline(always)] + pub fn per1(&self) -> PER1_R { + PER1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2"] + #[inline(always)] + pub fn per2(&self) -> PER2_R { + PER2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3"] + #[inline(always)] + pub fn per3(&self) -> PER3_R { + PER3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4"] + #[inline(always)] + pub fn per4(&self) -> PER4_R { + PER4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5"] + #[inline(always)] + pub fn per5(&self) -> PER5_R { + PER5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6"] + #[inline(always)] + pub fn per6(&self) -> PER6_R { + PER6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7"] + #[inline(always)] + pub fn per7(&self) -> PER7_R { + PER7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Alarm 0"] + #[inline(always)] + pub fn alarm0(&self) -> ALARM0_R { + ALARM0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 15 - Overflow"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0"] + #[inline(always)] + pub fn per0(&mut self) -> PER0_W { + PER0_W { w: self } + } + #[doc = "Bit 1 - Periodic Interval 1"] + #[inline(always)] + pub fn per1(&mut self) -> PER1_W { + PER1_W { w: self } + } + #[doc = "Bit 2 - Periodic Interval 2"] + #[inline(always)] + pub fn per2(&mut self) -> PER2_W { + PER2_W { w: self } + } + #[doc = "Bit 3 - Periodic Interval 3"] + #[inline(always)] + pub fn per3(&mut self) -> PER3_W { + PER3_W { w: self } + } + #[doc = "Bit 4 - Periodic Interval 4"] + #[inline(always)] + pub fn per4(&mut self) -> PER4_W { + PER4_W { w: self } + } + #[doc = "Bit 5 - Periodic Interval 5"] + #[inline(always)] + pub fn per5(&mut self) -> PER5_W { + PER5_W { w: self } + } + #[doc = "Bit 6 - Periodic Interval 6"] + #[inline(always)] + pub fn per6(&mut self) -> PER6_W { + PER6_W { w: self } + } + #[doc = "Bit 7 - Periodic Interval 7"] + #[inline(always)] + pub fn per7(&mut self) -> PER7_W { + PER7_W { w: self } + } + #[doc = "Bit 8 - Alarm 0"] + #[inline(always)] + pub fn alarm0(&mut self) -> ALARM0_W { + ALARM0_W { w: self } + } + #[doc = "Bit 15 - Overflow"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2 Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/rtc/mode2/mask.rs b/pac/atsamc21n/src/rtc/mode2/mask.rs new file mode 100644 index 000000000000..53e0bb491a62 --- /dev/null +++ b/pac/atsamc21n/src/rtc/mode2/mask.rs @@ -0,0 +1,217 @@ +#[doc = "Register `MASK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MASK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Alarm Mask Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SEL_A { + #[doc = "0: Alarm Disabled"] + OFF = 0, + #[doc = "1: Match seconds only"] + SS = 1, + #[doc = "2: Match seconds and minutes only"] + MMSS = 2, + #[doc = "3: Match seconds, minutes, and hours only"] + HHMMSS = 3, + #[doc = "4: Match seconds, minutes, hours, and days only"] + DDHHMMSS = 4, + #[doc = "5: Match seconds, minutes, hours, days, and months only"] + MMDDHHMMSS = 5, + #[doc = "6: Match seconds, minutes, hours, days, months, and years"] + YYMMDDHHMMSS = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `SEL` reader - Alarm Mask Selection"] +pub struct SEL_R(crate::FieldReader); +impl SEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEL_A::OFF), + 1 => Some(SEL_A::SS), + 2 => Some(SEL_A::MMSS), + 3 => Some(SEL_A::HHMMSS), + 4 => Some(SEL_A::DDHHMMSS), + 5 => Some(SEL_A::MMDDHHMMSS), + 6 => Some(SEL_A::YYMMDDHHMMSS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == SEL_A::OFF + } + #[doc = "Checks if the value of the field is `SS`"] + #[inline(always)] + pub fn is_ss(&self) -> bool { + **self == SEL_A::SS + } + #[doc = "Checks if the value of the field is `MMSS`"] + #[inline(always)] + pub fn is_mmss(&self) -> bool { + **self == SEL_A::MMSS + } + #[doc = "Checks if the value of the field is `HHMMSS`"] + #[inline(always)] + pub fn is_hhmmss(&self) -> bool { + **self == SEL_A::HHMMSS + } + #[doc = "Checks if the value of the field is `DDHHMMSS`"] + #[inline(always)] + pub fn is_ddhhmmss(&self) -> bool { + **self == SEL_A::DDHHMMSS + } + #[doc = "Checks if the value of the field is `MMDDHHMMSS`"] + #[inline(always)] + pub fn is_mmddhhmmss(&self) -> bool { + **self == SEL_A::MMDDHHMMSS + } + #[doc = "Checks if the value of the field is `YYMMDDHHMMSS`"] + #[inline(always)] + pub fn is_yymmddhhmmss(&self) -> bool { + **self == SEL_A::YYMMDDHHMMSS + } +} +impl core::ops::Deref for SEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEL` writer - Alarm Mask Selection"] +pub struct SEL_W<'a> { + w: &'a mut W, +} +impl<'a> SEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SEL_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Alarm Disabled"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(SEL_A::OFF) + } + #[doc = "Match seconds only"] + #[inline(always)] + pub fn ss(self) -> &'a mut W { + self.variant(SEL_A::SS) + } + #[doc = "Match seconds and minutes only"] + #[inline(always)] + pub fn mmss(self) -> &'a mut W { + self.variant(SEL_A::MMSS) + } + #[doc = "Match seconds, minutes, and hours only"] + #[inline(always)] + pub fn hhmmss(self) -> &'a mut W { + self.variant(SEL_A::HHMMSS) + } + #[doc = "Match seconds, minutes, hours, and days only"] + #[inline(always)] + pub fn ddhhmmss(self) -> &'a mut W { + self.variant(SEL_A::DDHHMMSS) + } + #[doc = "Match seconds, minutes, hours, days, and months only"] + #[inline(always)] + pub fn mmddhhmmss(self) -> &'a mut W { + self.variant(SEL_A::MMDDHHMMSS) + } + #[doc = "Match seconds, minutes, hours, days, months, and years"] + #[inline(always)] + pub fn yymmddhhmmss(self) -> &'a mut W { + self.variant(SEL_A::YYMMDDHHMMSS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Alarm Mask Selection"] + #[inline(always)] + pub fn sel(&self) -> SEL_R { + SEL_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Alarm Mask Selection"] + #[inline(always)] + pub fn sel(&mut self) -> SEL_W { + SEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2_ALARM Alarm n Mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mask](index.html) module"] +pub struct MASK_SPEC; +impl crate::RegisterSpec for MASK_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [mask::R](R) reader structure"] +impl crate::Readable for MASK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [mask::W](W) writer structure"] +impl crate::Writable for MASK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets MASK to value 0"] +impl crate::Resettable for MASK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/rtc/mode2/syncbusy.rs b/pac/atsamc21n/src/rtc/mode2/syncbusy.rs new file mode 100644 index 000000000000..b517ee5ae8b2 --- /dev/null +++ b/pac/atsamc21n/src/rtc/mode2/syncbusy.rs @@ -0,0 +1,173 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Bit Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - Enable Bit Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FREQCORR` reader - FREQCORR Register Busy"] +pub struct FREQCORR_R(crate::FieldReader); +impl FREQCORR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FREQCORR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FREQCORR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLOCK` reader - CLOCK Register Busy"] +pub struct CLOCK_R(crate::FieldReader); +impl CLOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALARM0` reader - ALARM 0 Register Busy"] +pub struct ALARM0_R(crate::FieldReader); +impl ALARM0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALARM0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALARM0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MASK0` reader - MASK 0 Register Busy"] +pub struct MASK0_R(crate::FieldReader); +impl MASK0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MASK0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MASK0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLOCKSYNC` reader - Clock Read Synchronization Enable Bit Busy"] +pub struct CLOCKSYNC_R(crate::FieldReader); +impl CLOCKSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLOCKSYNC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLOCKSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Bit Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable Bit Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - FREQCORR Register Busy"] + #[inline(always)] + pub fn freqcorr(&self) -> FREQCORR_R { + FREQCORR_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - CLOCK Register Busy"] + #[inline(always)] + pub fn clock(&self) -> CLOCK_R { + CLOCK_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 5 - ALARM 0 Register Busy"] + #[inline(always)] + pub fn alarm0(&self) -> ALARM0_R { + ALARM0_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 11 - MASK 0 Register Busy"] + #[inline(always)] + pub fn mask0(&self) -> MASK0_R { + MASK0_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 15 - Clock Read Synchronization Enable Bit Busy"] + #[inline(always)] + pub fn clocksync(&self) -> CLOCKSYNC_R { + CLOCKSYNC_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +#[doc = "MODE2 Synchronization Busy Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sdadc.rs b/pac/atsamc21n/src/sdadc.rs new file mode 100644 index 000000000000..11e926a1d2de --- /dev/null +++ b/pac/atsamc21n/src/sdadc.rs @@ -0,0 +1,140 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + #[doc = "0x01 - Reference Control"] + pub refctrl: crate::Reg, + #[doc = "0x02 - Control B"] + pub ctrlb: crate::Reg, + #[doc = "0x04 - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x05 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x06 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x07 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x08 - Sequence Status"] + pub seqstatus: crate::Reg, + #[doc = "0x09 - Input Control"] + pub inputctrl: crate::Reg, + #[doc = "0x0a - Control C"] + pub ctrlc: crate::Reg, + #[doc = "0x0b - Window Monitor Control"] + pub winctrl: crate::Reg, + #[doc = "0x0c - Window Monitor Lower Threshold"] + pub winlt: crate::Reg, + #[doc = "0x10 - Window Monitor Upper Threshold"] + pub winut: crate::Reg, + #[doc = "0x14 - Offset Correction"] + pub offsetcorr: crate::Reg, + #[doc = "0x18 - Gain Correction"] + pub gaincorr: crate::Reg, + #[doc = "0x1a - Shift Correction"] + pub shiftcorr: crate::Reg, + _reserved16: [u8; 0x01], + #[doc = "0x1c - Software Trigger"] + pub swtrig: crate::Reg, + _reserved17: [u8; 0x03], + #[doc = "0x20 - Synchronization Busy"] + pub syncbusy: crate::Reg, + #[doc = "0x24 - Result"] + pub result: crate::Reg, + #[doc = "0x28 - Sequence Control"] + pub seqctrl: crate::Reg, + _reserved20: [u8; 0x03], + #[doc = "0x2c - Analog Control"] + pub anactrl: crate::Reg, + _reserved21: [u8; 0x01], + #[doc = "0x2e - Debug Control"] + pub dbgctrl: crate::Reg, +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "REFCTRL register accessor: an alias for `Reg`"] +pub type REFCTRL = crate::Reg; +#[doc = "Reference Control"] +pub mod refctrl; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "Control B"] +pub mod ctrlb; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "SEQSTATUS register accessor: an alias for `Reg`"] +pub type SEQSTATUS = crate::Reg; +#[doc = "Sequence Status"] +pub mod seqstatus; +#[doc = "INPUTCTRL register accessor: an alias for `Reg`"] +pub type INPUTCTRL = crate::Reg; +#[doc = "Input Control"] +pub mod inputctrl; +#[doc = "CTRLC register accessor: an alias for `Reg`"] +pub type CTRLC = crate::Reg; +#[doc = "Control C"] +pub mod ctrlc; +#[doc = "WINCTRL register accessor: an alias for `Reg`"] +pub type WINCTRL = crate::Reg; +#[doc = "Window Monitor Control"] +pub mod winctrl; +#[doc = "WINLT register accessor: an alias for `Reg`"] +pub type WINLT = crate::Reg; +#[doc = "Window Monitor Lower Threshold"] +pub mod winlt; +#[doc = "WINUT register accessor: an alias for `Reg`"] +pub type WINUT = crate::Reg; +#[doc = "Window Monitor Upper Threshold"] +pub mod winut; +#[doc = "OFFSETCORR register accessor: an alias for `Reg`"] +pub type OFFSETCORR = crate::Reg; +#[doc = "Offset Correction"] +pub mod offsetcorr; +#[doc = "GAINCORR register accessor: an alias for `Reg`"] +pub type GAINCORR = crate::Reg; +#[doc = "Gain Correction"] +pub mod gaincorr; +#[doc = "SHIFTCORR register accessor: an alias for `Reg`"] +pub type SHIFTCORR = crate::Reg; +#[doc = "Shift Correction"] +pub mod shiftcorr; +#[doc = "SWTRIG register accessor: an alias for `Reg`"] +pub type SWTRIG = crate::Reg; +#[doc = "Software Trigger"] +pub mod swtrig; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Busy"] +pub mod syncbusy; +#[doc = "RESULT register accessor: an alias for `Reg`"] +pub type RESULT = crate::Reg; +#[doc = "Result"] +pub mod result; +#[doc = "SEQCTRL register accessor: an alias for `Reg`"] +pub type SEQCTRL = crate::Reg; +#[doc = "Sequence Control"] +pub mod seqctrl; +#[doc = "ANACTRL register accessor: an alias for `Reg`"] +pub type ANACTRL = crate::Reg; +#[doc = "Analog Control"] +pub mod anactrl; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; diff --git a/pac/atsamc21n/src/sdadc/anactrl.rs b/pac/atsamc21n/src/sdadc/anactrl.rs new file mode 100644 index 000000000000..3261811c0348 --- /dev/null +++ b/pac/atsamc21n/src/sdadc/anactrl.rs @@ -0,0 +1,197 @@ +#[doc = "Register `ANACTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ANACTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CTRSDADC` reader - SDADC Control"] +pub struct CTRSDADC_R(crate::FieldReader); +impl CTRSDADC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CTRSDADC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRSDADC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRSDADC` writer - SDADC Control"] +pub struct CTRSDADC_W<'a> { + w: &'a mut W, +} +impl<'a> CTRSDADC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u8 & 0x3f); + self.w + } +} +#[doc = "Field `ONCHOP` reader - Chopper"] +pub struct ONCHOP_R(crate::FieldReader); +impl ONCHOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONCHOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONCHOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONCHOP` writer - Chopper"] +pub struct ONCHOP_W<'a> { + w: &'a mut W, +} +impl<'a> ONCHOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +#[doc = "Field `BUFTEST` reader - BUFTEST"] +pub struct BUFTEST_R(crate::FieldReader); +impl BUFTEST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUFTEST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUFTEST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUFTEST` writer - BUFTEST"] +pub struct BUFTEST_W<'a> { + w: &'a mut W, +} +impl<'a> BUFTEST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - SDADC Control"] + #[inline(always)] + pub fn ctrsdadc(&self) -> CTRSDADC_R { + CTRSDADC_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - Chopper"] + #[inline(always)] + pub fn onchop(&self) -> ONCHOP_R { + ONCHOP_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - BUFTEST"] + #[inline(always)] + pub fn buftest(&self) -> BUFTEST_R { + BUFTEST_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:5 - SDADC Control"] + #[inline(always)] + pub fn ctrsdadc(&mut self) -> CTRSDADC_W { + CTRSDADC_W { w: self } + } + #[doc = "Bit 6 - Chopper"] + #[inline(always)] + pub fn onchop(&mut self) -> ONCHOP_W { + ONCHOP_W { w: self } + } + #[doc = "Bit 7 - BUFTEST"] + #[inline(always)] + pub fn buftest(&mut self) -> BUFTEST_W { + BUFTEST_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Analog Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [anactrl](index.html) module"] +pub struct ANACTRL_SPEC; +impl crate::RegisterSpec for ANACTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [anactrl::R](R) reader structure"] +impl crate::Readable for ANACTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [anactrl::W](W) writer structure"] +impl crate::Writable for ANACTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ANACTRL to value 0"] +impl crate::Resettable for ANACTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sdadc/ctrla.rs b/pac/atsamc21n/src/sdadc/ctrla.rs new file mode 100644 index 000000000000..8fccdcb93995 --- /dev/null +++ b/pac/atsamc21n/src/sdadc/ctrla.rs @@ -0,0 +1,254 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - On Demand Control"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - On Demand Control"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sdadc/ctrlb.rs b/pac/atsamc21n/src/sdadc/ctrlb.rs new file mode 100644 index 000000000000..ee0dce613bc4 --- /dev/null +++ b/pac/atsamc21n/src/sdadc/ctrlb.rs @@ -0,0 +1,392 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Prescaler Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: Peripheral clock divided by 2"] + DIV2 = 0, + #[doc = "1: Peripheral clock divided by 4"] + DIV4 = 1, + #[doc = "2: Peripheral clock divided by 8"] + DIV8 = 2, + #[doc = "3: Peripheral clock divided by 16"] + DIV16 = 3, + #[doc = "4: Peripheral clock divided by 32"] + DIV32 = 4, + #[doc = "5: Peripheral clock divided by 64"] + DIV64 = 5, + #[doc = "6: Peripheral clock divided by 128"] + DIV128 = 6, + #[doc = "7: Peripheral clock divided by 256"] + DIV256 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler Configuration"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCALER_A::DIV2), + 1 => Some(PRESCALER_A::DIV4), + 2 => Some(PRESCALER_A::DIV8), + 3 => Some(PRESCALER_A::DIV16), + 4 => Some(PRESCALER_A::DIV32), + 5 => Some(PRESCALER_A::DIV64), + 6 => Some(PRESCALER_A::DIV128), + 7 => Some(PRESCALER_A::DIV256), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == PRESCALER_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == PRESCALER_A::DIV128 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler Configuration"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Peripheral clock divided by 2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "Peripheral clock divided by 4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "Peripheral clock divided by 8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "Peripheral clock divided by 16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "Peripheral clock divided by 32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV32) + } + #[doc = "Peripheral clock divided by 64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "Peripheral clock divided by 128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV128) + } + #[doc = "Peripheral clock divided by 256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u16 & 0xff); + self.w + } +} +#[doc = "Over Sampling Ratio\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum OSR_A { + #[doc = "0: Over Sampling Ratio is 64"] + OSR64 = 0, + #[doc = "1: Over Sampling Ratio is 128"] + OSR128 = 1, + #[doc = "2: Over Sampling Ratio is 256"] + OSR256 = 2, + #[doc = "3: Over Sampling Ratio is 512"] + OSR512 = 3, + #[doc = "4: Over Sampling Ratio is 1024"] + OSR1024 = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: OSR_A) -> Self { + variant as _ + } +} +#[doc = "Field `OSR` reader - Over Sampling Ratio"] +pub struct OSR_R(crate::FieldReader); +impl OSR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + OSR_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(OSR_A::OSR64), + 1 => Some(OSR_A::OSR128), + 2 => Some(OSR_A::OSR256), + 3 => Some(OSR_A::OSR512), + 4 => Some(OSR_A::OSR1024), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OSR64`"] + #[inline(always)] + pub fn is_osr64(&self) -> bool { + **self == OSR_A::OSR64 + } + #[doc = "Checks if the value of the field is `OSR128`"] + #[inline(always)] + pub fn is_osr128(&self) -> bool { + **self == OSR_A::OSR128 + } + #[doc = "Checks if the value of the field is `OSR256`"] + #[inline(always)] + pub fn is_osr256(&self) -> bool { + **self == OSR_A::OSR256 + } + #[doc = "Checks if the value of the field is `OSR512`"] + #[inline(always)] + pub fn is_osr512(&self) -> bool { + **self == OSR_A::OSR512 + } + #[doc = "Checks if the value of the field is `OSR1024`"] + #[inline(always)] + pub fn is_osr1024(&self) -> bool { + **self == OSR_A::OSR1024 + } +} +impl core::ops::Deref for OSR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSR` writer - Over Sampling Ratio"] +pub struct OSR_W<'a> { + w: &'a mut W, +} +impl<'a> OSR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: OSR_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Over Sampling Ratio is 64"] + #[inline(always)] + pub fn osr64(self) -> &'a mut W { + self.variant(OSR_A::OSR64) + } + #[doc = "Over Sampling Ratio is 128"] + #[inline(always)] + pub fn osr128(self) -> &'a mut W { + self.variant(OSR_A::OSR128) + } + #[doc = "Over Sampling Ratio is 256"] + #[inline(always)] + pub fn osr256(self) -> &'a mut W { + self.variant(OSR_A::OSR256) + } + #[doc = "Over Sampling Ratio is 512"] + #[inline(always)] + pub fn osr512(self) -> &'a mut W { + self.variant(OSR_A::OSR512) + } + #[doc = "Over Sampling Ratio is 1024"] + #[inline(always)] + pub fn osr1024(self) -> &'a mut W { + self.variant(OSR_A::OSR1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u16 & 0x07) << 8); + self.w + } +} +#[doc = "Field `SKPCNT` reader - Skip Sample Count"] +pub struct SKPCNT_R(crate::FieldReader); +impl SKPCNT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SKPCNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SKPCNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SKPCNT` writer - Skip Sample Count"] +pub struct SKPCNT_W<'a> { + w: &'a mut W, +} +impl<'a> SKPCNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 12)) | ((value as u16 & 0x0f) << 12); + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Prescaler Configuration"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:10 - Over Sampling Ratio"] + #[inline(always)] + pub fn osr(&self) -> OSR_R { + OSR_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bits 12:15 - Skip Sample Count"] + #[inline(always)] + pub fn skpcnt(&self) -> SKPCNT_R { + SKPCNT_R::new(((self.bits >> 12) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Prescaler Configuration"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Bits 8:10 - Over Sampling Ratio"] + #[inline(always)] + pub fn osr(&mut self) -> OSR_W { + OSR_W { w: self } + } + #[doc = "Bits 12:15 - Skip Sample Count"] + #[inline(always)] + pub fn skpcnt(&mut self) -> SKPCNT_W { + SKPCNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0x2000"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x2000 + } +} diff --git a/pac/atsamc21n/src/sdadc/ctrlc.rs b/pac/atsamc21n/src/sdadc/ctrlc.rs new file mode 100644 index 000000000000..320cfe4ec4aa --- /dev/null +++ b/pac/atsamc21n/src/sdadc/ctrlc.rs @@ -0,0 +1,113 @@ +#[doc = "Register `CTRLC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FREERUN` reader - Free Running Mode"] +pub struct FREERUN_R(crate::FieldReader); +impl FREERUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FREERUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FREERUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FREERUN` writer - Free Running Mode"] +pub struct FREERUN_W<'a> { + w: &'a mut W, +} +impl<'a> FREERUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Free Running Mode"] + #[inline(always)] + pub fn freerun(&self) -> FREERUN_R { + FREERUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Free Running Mode"] + #[inline(always)] + pub fn freerun(&mut self) -> FREERUN_W { + FREERUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control C\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlc](index.html) module"] +pub struct CTRLC_SPEC; +impl crate::RegisterSpec for CTRLC_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlc::R](R) reader structure"] +impl crate::Readable for CTRLC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlc::W](W) writer structure"] +impl crate::Writable for CTRLC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLC to value 0"] +impl crate::Resettable for CTRLC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sdadc/dbgctrl.rs b/pac/atsamc21n/src/sdadc/dbgctrl.rs new file mode 100644 index 000000000000..53636eb2b339 --- /dev/null +++ b/pac/atsamc21n/src/sdadc/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Debug Run"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Debug Run"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sdadc/evctrl.rs b/pac/atsamc21n/src/sdadc/evctrl.rs new file mode 100644 index 000000000000..2c50a979c544 --- /dev/null +++ b/pac/atsamc21n/src/sdadc/evctrl.rs @@ -0,0 +1,348 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FLUSHEI` reader - Flush Event Input Enable"] +pub struct FLUSHEI_R(crate::FieldReader); +impl FLUSHEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FLUSHEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FLUSHEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLUSHEI` writer - Flush Event Input Enable"] +pub struct FLUSHEI_W<'a> { + w: &'a mut W, +} +impl<'a> FLUSHEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `STARTEI` reader - Start Conversion Event Input Enable"] +pub struct STARTEI_R(crate::FieldReader); +impl STARTEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STARTEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STARTEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STARTEI` writer - Start Conversion Event Input Enable"] +pub struct STARTEI_W<'a> { + w: &'a mut W, +} +impl<'a> STARTEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `FLUSHINV` reader - Flush Event Invert Enable"] +pub struct FLUSHINV_R(crate::FieldReader); +impl FLUSHINV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FLUSHINV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FLUSHINV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLUSHINV` writer - Flush Event Invert Enable"] +pub struct FLUSHINV_W<'a> { + w: &'a mut W, +} +impl<'a> FLUSHINV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `STARTINV` reader - Satrt Event Invert Enable"] +pub struct STARTINV_R(crate::FieldReader); +impl STARTINV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STARTINV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STARTINV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STARTINV` writer - Satrt Event Invert Enable"] +pub struct STARTINV_W<'a> { + w: &'a mut W, +} +impl<'a> STARTINV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `RESRDYEO` reader - Result Ready Event Out"] +pub struct RESRDYEO_R(crate::FieldReader); +impl RESRDYEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESRDYEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESRDYEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESRDYEO` writer - Result Ready Event Out"] +pub struct RESRDYEO_W<'a> { + w: &'a mut W, +} +impl<'a> RESRDYEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `WINMONEO` reader - Window Monitor Event Out"] +pub struct WINMONEO_R(crate::FieldReader); +impl WINMONEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINMONEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINMONEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMONEO` writer - Window Monitor Event Out"] +pub struct WINMONEO_W<'a> { + w: &'a mut W, +} +impl<'a> WINMONEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Flush Event Input Enable"] + #[inline(always)] + pub fn flushei(&self) -> FLUSHEI_R { + FLUSHEI_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Start Conversion Event Input Enable"] + #[inline(always)] + pub fn startei(&self) -> STARTEI_R { + STARTEI_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Flush Event Invert Enable"] + #[inline(always)] + pub fn flushinv(&self) -> FLUSHINV_R { + FLUSHINV_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Satrt Event Invert Enable"] + #[inline(always)] + pub fn startinv(&self) -> STARTINV_R { + STARTINV_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Result Ready Event Out"] + #[inline(always)] + pub fn resrdyeo(&self) -> RESRDYEO_R { + RESRDYEO_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Window Monitor Event Out"] + #[inline(always)] + pub fn winmoneo(&self) -> WINMONEO_R { + WINMONEO_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Flush Event Input Enable"] + #[inline(always)] + pub fn flushei(&mut self) -> FLUSHEI_W { + FLUSHEI_W { w: self } + } + #[doc = "Bit 1 - Start Conversion Event Input Enable"] + #[inline(always)] + pub fn startei(&mut self) -> STARTEI_W { + STARTEI_W { w: self } + } + #[doc = "Bit 2 - Flush Event Invert Enable"] + #[inline(always)] + pub fn flushinv(&mut self) -> FLUSHINV_W { + FLUSHINV_W { w: self } + } + #[doc = "Bit 3 - Satrt Event Invert Enable"] + #[inline(always)] + pub fn startinv(&mut self) -> STARTINV_W { + STARTINV_W { w: self } + } + #[doc = "Bit 4 - Result Ready Event Out"] + #[inline(always)] + pub fn resrdyeo(&mut self) -> RESRDYEO_W { + RESRDYEO_W { w: self } + } + #[doc = "Bit 5 - Window Monitor Event Out"] + #[inline(always)] + pub fn winmoneo(&mut self) -> WINMONEO_W { + WINMONEO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sdadc/gaincorr.rs b/pac/atsamc21n/src/sdadc/gaincorr.rs new file mode 100644 index 000000000000..0f20d1cdef86 --- /dev/null +++ b/pac/atsamc21n/src/sdadc/gaincorr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `GAINCORR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GAINCORR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `GAINCORR` reader - Gain Correction Value"] +pub struct GAINCORR_R(crate::FieldReader); +impl GAINCORR_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + GAINCORR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GAINCORR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GAINCORR` writer - Gain Correction Value"] +pub struct GAINCORR_W<'a> { + w: &'a mut W, +} +impl<'a> GAINCORR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3fff) | (value as u16 & 0x3fff); + self.w + } +} +impl R { + #[doc = "Bits 0:13 - Gain Correction Value"] + #[inline(always)] + pub fn gaincorr(&self) -> GAINCORR_R { + GAINCORR_R::new((self.bits & 0x3fff) as u16) + } +} +impl W { + #[doc = "Bits 0:13 - Gain Correction Value"] + #[inline(always)] + pub fn gaincorr(&mut self) -> GAINCORR_W { + GAINCORR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Gain Correction\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gaincorr](index.html) module"] +pub struct GAINCORR_SPEC; +impl crate::RegisterSpec for GAINCORR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [gaincorr::R](R) reader structure"] +impl crate::Readable for GAINCORR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gaincorr::W](W) writer structure"] +impl crate::Writable for GAINCORR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets GAINCORR to value 0x01"] +impl crate::Resettable for GAINCORR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pac/atsamc21n/src/sdadc/inputctrl.rs b/pac/atsamc21n/src/sdadc/inputctrl.rs new file mode 100644 index 000000000000..e256cd3bbfc1 --- /dev/null +++ b/pac/atsamc21n/src/sdadc/inputctrl.rs @@ -0,0 +1,165 @@ +#[doc = "Register `INPUTCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INPUTCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "SDADC Input Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MUXSEL_A { + #[doc = "0: SDADC AIN0 Pin"] + AIN0 = 0, + #[doc = "1: SDADC AIN1 Pin"] + AIN1 = 1, + #[doc = "2: SDADC AIN2 Pin"] + AIN2 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MUXSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `MUXSEL` reader - SDADC Input Selection"] +pub struct MUXSEL_R(crate::FieldReader); +impl MUXSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MUXSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MUXSEL_A::AIN0), + 1 => Some(MUXSEL_A::AIN1), + 2 => Some(MUXSEL_A::AIN2), + _ => None, + } + } + #[doc = "Checks if the value of the field is `AIN0`"] + #[inline(always)] + pub fn is_ain0(&self) -> bool { + **self == MUXSEL_A::AIN0 + } + #[doc = "Checks if the value of the field is `AIN1`"] + #[inline(always)] + pub fn is_ain1(&self) -> bool { + **self == MUXSEL_A::AIN1 + } + #[doc = "Checks if the value of the field is `AIN2`"] + #[inline(always)] + pub fn is_ain2(&self) -> bool { + **self == MUXSEL_A::AIN2 + } +} +impl core::ops::Deref for MUXSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MUXSEL` writer - SDADC Input Selection"] +pub struct MUXSEL_W<'a> { + w: &'a mut W, +} +impl<'a> MUXSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MUXSEL_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "SDADC AIN0 Pin"] + #[inline(always)] + pub fn ain0(self) -> &'a mut W { + self.variant(MUXSEL_A::AIN0) + } + #[doc = "SDADC AIN1 Pin"] + #[inline(always)] + pub fn ain1(self) -> &'a mut W { + self.variant(MUXSEL_A::AIN1) + } + #[doc = "SDADC AIN2 Pin"] + #[inline(always)] + pub fn ain2(self) -> &'a mut W { + self.variant(MUXSEL_A::AIN2) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - SDADC Input Selection"] + #[inline(always)] + pub fn muxsel(&self) -> MUXSEL_R { + MUXSEL_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - SDADC Input Selection"] + #[inline(always)] + pub fn muxsel(&mut self) -> MUXSEL_W { + MUXSEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Input Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [inputctrl](index.html) module"] +pub struct INPUTCTRL_SPEC; +impl crate::RegisterSpec for INPUTCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [inputctrl::R](R) reader structure"] +impl crate::Readable for INPUTCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [inputctrl::W](W) writer structure"] +impl crate::Writable for INPUTCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INPUTCTRL to value 0"] +impl crate::Resettable for INPUTCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sdadc/intenclr.rs b/pac/atsamc21n/src/sdadc/intenclr.rs new file mode 100644 index 000000000000..b10f428d30b1 --- /dev/null +++ b/pac/atsamc21n/src/sdadc/intenclr.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RESRDY` reader - Result Ready Interrupt Disable"] +pub struct RESRDY_R(crate::FieldReader); +impl RESRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESRDY` writer - Result Ready Interrupt Disable"] +pub struct RESRDY_W<'a> { + w: &'a mut W, +} +impl<'a> RESRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `OVERRUN` reader - Overrun Interrupt Disable"] +pub struct OVERRUN_R(crate::FieldReader); +impl OVERRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVERRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVERRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVERRUN` writer - Overrun Interrupt Disable"] +pub struct OVERRUN_W<'a> { + w: &'a mut W, +} +impl<'a> OVERRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WINMON` reader - Window Monitor Interrupt Disable"] +pub struct WINMON_R(crate::FieldReader); +impl WINMON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINMON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINMON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMON` writer - Window Monitor Interrupt Disable"] +pub struct WINMON_W<'a> { + w: &'a mut W, +} +impl<'a> WINMON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Result Ready Interrupt Disable"] + #[inline(always)] + pub fn resrdy(&self) -> RESRDY_R { + RESRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Overrun Interrupt Disable"] + #[inline(always)] + pub fn overrun(&self) -> OVERRUN_R { + OVERRUN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Window Monitor Interrupt Disable"] + #[inline(always)] + pub fn winmon(&self) -> WINMON_R { + WINMON_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Result Ready Interrupt Disable"] + #[inline(always)] + pub fn resrdy(&mut self) -> RESRDY_W { + RESRDY_W { w: self } + } + #[doc = "Bit 1 - Overrun Interrupt Disable"] + #[inline(always)] + pub fn overrun(&mut self) -> OVERRUN_W { + OVERRUN_W { w: self } + } + #[doc = "Bit 2 - Window Monitor Interrupt Disable"] + #[inline(always)] + pub fn winmon(&mut self) -> WINMON_W { + WINMON_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sdadc/intenset.rs b/pac/atsamc21n/src/sdadc/intenset.rs new file mode 100644 index 000000000000..5ca93b05b859 --- /dev/null +++ b/pac/atsamc21n/src/sdadc/intenset.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RESRDY` reader - Result Ready Interrupt Enable"] +pub struct RESRDY_R(crate::FieldReader); +impl RESRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESRDY` writer - Result Ready Interrupt Enable"] +pub struct RESRDY_W<'a> { + w: &'a mut W, +} +impl<'a> RESRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `OVERRUN` reader - Overrun Interrupt Enable"] +pub struct OVERRUN_R(crate::FieldReader); +impl OVERRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVERRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVERRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVERRUN` writer - Overrun Interrupt Enable"] +pub struct OVERRUN_W<'a> { + w: &'a mut W, +} +impl<'a> OVERRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WINMON` reader - Window Monitor Interrupt Enable"] +pub struct WINMON_R(crate::FieldReader); +impl WINMON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINMON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINMON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMON` writer - Window Monitor Interrupt Enable"] +pub struct WINMON_W<'a> { + w: &'a mut W, +} +impl<'a> WINMON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Result Ready Interrupt Enable"] + #[inline(always)] + pub fn resrdy(&self) -> RESRDY_R { + RESRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Overrun Interrupt Enable"] + #[inline(always)] + pub fn overrun(&self) -> OVERRUN_R { + OVERRUN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Window Monitor Interrupt Enable"] + #[inline(always)] + pub fn winmon(&self) -> WINMON_R { + WINMON_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Result Ready Interrupt Enable"] + #[inline(always)] + pub fn resrdy(&mut self) -> RESRDY_W { + RESRDY_W { w: self } + } + #[doc = "Bit 1 - Overrun Interrupt Enable"] + #[inline(always)] + pub fn overrun(&mut self) -> OVERRUN_W { + OVERRUN_W { w: self } + } + #[doc = "Bit 2 - Window Monitor Interrupt Enable"] + #[inline(always)] + pub fn winmon(&mut self) -> WINMON_W { + WINMON_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sdadc/intflag.rs b/pac/atsamc21n/src/sdadc/intflag.rs new file mode 100644 index 000000000000..3cd74788b226 --- /dev/null +++ b/pac/atsamc21n/src/sdadc/intflag.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RESRDY` reader - Result Ready Interrupt Flag"] +pub struct RESRDY_R(crate::FieldReader); +impl RESRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESRDY` writer - Result Ready Interrupt Flag"] +pub struct RESRDY_W<'a> { + w: &'a mut W, +} +impl<'a> RESRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `OVERRUN` reader - Overrun Interrupt Flag"] +pub struct OVERRUN_R(crate::FieldReader); +impl OVERRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVERRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVERRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVERRUN` writer - Overrun Interrupt Flag"] +pub struct OVERRUN_W<'a> { + w: &'a mut W, +} +impl<'a> OVERRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WINMON` reader - Window Monitor Interrupt Flag"] +pub struct WINMON_R(crate::FieldReader); +impl WINMON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINMON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINMON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMON` writer - Window Monitor Interrupt Flag"] +pub struct WINMON_W<'a> { + w: &'a mut W, +} +impl<'a> WINMON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Result Ready Interrupt Flag"] + #[inline(always)] + pub fn resrdy(&self) -> RESRDY_R { + RESRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Overrun Interrupt Flag"] + #[inline(always)] + pub fn overrun(&self) -> OVERRUN_R { + OVERRUN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Window Monitor Interrupt Flag"] + #[inline(always)] + pub fn winmon(&self) -> WINMON_R { + WINMON_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Result Ready Interrupt Flag"] + #[inline(always)] + pub fn resrdy(&mut self) -> RESRDY_W { + RESRDY_W { w: self } + } + #[doc = "Bit 1 - Overrun Interrupt Flag"] + #[inline(always)] + pub fn overrun(&mut self) -> OVERRUN_W { + OVERRUN_W { w: self } + } + #[doc = "Bit 2 - Window Monitor Interrupt Flag"] + #[inline(always)] + pub fn winmon(&mut self) -> WINMON_W { + WINMON_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sdadc/offsetcorr.rs b/pac/atsamc21n/src/sdadc/offsetcorr.rs new file mode 100644 index 000000000000..7bda80d6fbfc --- /dev/null +++ b/pac/atsamc21n/src/sdadc/offsetcorr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `OFFSETCORR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OFFSETCORR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OFFSETCORR` reader - Offset Correction Value"] +pub struct OFFSETCORR_R(crate::FieldReader); +impl OFFSETCORR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + OFFSETCORR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OFFSETCORR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OFFSETCORR` writer - Offset Correction Value"] +pub struct OFFSETCORR_W<'a> { + w: &'a mut W, +} +impl<'a> OFFSETCORR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Offset Correction Value"] + #[inline(always)] + pub fn offsetcorr(&self) -> OFFSETCORR_R { + OFFSETCORR_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Offset Correction Value"] + #[inline(always)] + pub fn offsetcorr(&mut self) -> OFFSETCORR_W { + OFFSETCORR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Offset Correction\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [offsetcorr](index.html) module"] +pub struct OFFSETCORR_SPEC; +impl crate::RegisterSpec for OFFSETCORR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [offsetcorr::R](R) reader structure"] +impl crate::Readable for OFFSETCORR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [offsetcorr::W](W) writer structure"] +impl crate::Writable for OFFSETCORR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OFFSETCORR to value 0"] +impl crate::Resettable for OFFSETCORR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sdadc/refctrl.rs b/pac/atsamc21n/src/sdadc/refctrl.rs new file mode 100644 index 000000000000..89449071a49b --- /dev/null +++ b/pac/atsamc21n/src/sdadc/refctrl.rs @@ -0,0 +1,262 @@ +#[doc = "Register `REFCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `REFCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Reference Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum REFSEL_A { + #[doc = "0: Internal Bandgap Reference"] + INTREF = 0, + #[doc = "1: External Reference"] + AREFB = 1, + #[doc = "2: Internal DAC Output"] + DAC = 2, + #[doc = "3: VDDANA"] + INTVCC = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: REFSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `REFSEL` reader - Reference Selection"] +pub struct REFSEL_R(crate::FieldReader); +impl REFSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REFSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> REFSEL_A { + match self.bits { + 0 => REFSEL_A::INTREF, + 1 => REFSEL_A::AREFB, + 2 => REFSEL_A::DAC, + 3 => REFSEL_A::INTVCC, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `INTREF`"] + #[inline(always)] + pub fn is_intref(&self) -> bool { + **self == REFSEL_A::INTREF + } + #[doc = "Checks if the value of the field is `AREFB`"] + #[inline(always)] + pub fn is_arefb(&self) -> bool { + **self == REFSEL_A::AREFB + } + #[doc = "Checks if the value of the field is `DAC`"] + #[inline(always)] + pub fn is_dac(&self) -> bool { + **self == REFSEL_A::DAC + } + #[doc = "Checks if the value of the field is `INTVCC`"] + #[inline(always)] + pub fn is_intvcc(&self) -> bool { + **self == REFSEL_A::INTVCC + } +} +impl core::ops::Deref for REFSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REFSEL` writer - Reference Selection"] +pub struct REFSEL_W<'a> { + w: &'a mut W, +} +impl<'a> REFSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: REFSEL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Internal Bandgap Reference"] + #[inline(always)] + pub fn intref(self) -> &'a mut W { + self.variant(REFSEL_A::INTREF) + } + #[doc = "External Reference"] + #[inline(always)] + pub fn arefb(self) -> &'a mut W { + self.variant(REFSEL_A::AREFB) + } + #[doc = "Internal DAC Output"] + #[inline(always)] + pub fn dac(self) -> &'a mut W { + self.variant(REFSEL_A::DAC) + } + #[doc = "VDDANA"] + #[inline(always)] + pub fn intvcc(self) -> &'a mut W { + self.variant(REFSEL_A::INTVCC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u8 & 0x03); + self.w + } +} +#[doc = "Field `REFRANGE` reader - Reference Range"] +pub struct REFRANGE_R(crate::FieldReader); +impl REFRANGE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REFRANGE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REFRANGE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REFRANGE` writer - Reference Range"] +pub struct REFRANGE_W<'a> { + w: &'a mut W, +} +impl<'a> REFRANGE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u8 & 0x03) << 4); + self.w + } +} +#[doc = "Field `ONREFBUF` reader - Reference Buffer"] +pub struct ONREFBUF_R(crate::FieldReader); +impl ONREFBUF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONREFBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONREFBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONREFBUF` writer - Reference Buffer"] +pub struct ONREFBUF_W<'a> { + w: &'a mut W, +} +impl<'a> ONREFBUF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Reference Selection"] + #[inline(always)] + pub fn refsel(&self) -> REFSEL_R { + REFSEL_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bits 4:5 - Reference Range"] + #[inline(always)] + pub fn refrange(&self) -> REFRANGE_R { + REFRANGE_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bit 7 - Reference Buffer"] + #[inline(always)] + pub fn onrefbuf(&self) -> ONREFBUF_R { + ONREFBUF_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:1 - Reference Selection"] + #[inline(always)] + pub fn refsel(&mut self) -> REFSEL_W { + REFSEL_W { w: self } + } + #[doc = "Bits 4:5 - Reference Range"] + #[inline(always)] + pub fn refrange(&mut self) -> REFRANGE_W { + REFRANGE_W { w: self } + } + #[doc = "Bit 7 - Reference Buffer"] + #[inline(always)] + pub fn onrefbuf(&mut self) -> ONREFBUF_W { + ONREFBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Reference Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [refctrl](index.html) module"] +pub struct REFCTRL_SPEC; +impl crate::RegisterSpec for REFCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [refctrl::R](R) reader structure"] +impl crate::Readable for REFCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [refctrl::W](W) writer structure"] +impl crate::Writable for REFCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets REFCTRL to value 0"] +impl crate::Resettable for REFCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sdadc/result.rs b/pac/atsamc21n/src/sdadc/result.rs new file mode 100644 index 000000000000..3f88d8b60ca6 --- /dev/null +++ b/pac/atsamc21n/src/sdadc/result.rs @@ -0,0 +1,53 @@ +#[doc = "Register `RESULT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `RESULT` reader - Result Value"] +pub struct RESULT_R(crate::FieldReader); +impl RESULT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + RESULT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESULT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:23 - Result Value"] + #[inline(always)] + pub fn result(&self) -> RESULT_R { + RESULT_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +#[doc = "Result\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [result](index.html) module"] +pub struct RESULT_SPEC; +impl crate::RegisterSpec for RESULT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [result::R](R) reader structure"] +impl crate::Readable for RESULT_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets RESULT to value 0"] +impl crate::Resettable for RESULT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sdadc/seqctrl.rs b/pac/atsamc21n/src/sdadc/seqctrl.rs new file mode 100644 index 000000000000..c8d1103959ee --- /dev/null +++ b/pac/atsamc21n/src/sdadc/seqctrl.rs @@ -0,0 +1,103 @@ +#[doc = "Register `SEQCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SEQCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SEQEN` reader - Enable Positive Input in the Sequence"] +pub struct SEQEN_R(crate::FieldReader); +impl SEQEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SEQEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEQEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEQEN` writer - Enable Positive Input in the Sequence"] +pub struct SEQEN_W<'a> { + w: &'a mut W, +} +impl<'a> SEQEN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Enable Positive Input in the Sequence"] + #[inline(always)] + pub fn seqen(&self) -> SEQEN_R { + SEQEN_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Enable Positive Input in the Sequence"] + #[inline(always)] + pub fn seqen(&mut self) -> SEQEN_W { + SEQEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Sequence Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [seqctrl](index.html) module"] +pub struct SEQCTRL_SPEC; +impl crate::RegisterSpec for SEQCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [seqctrl::R](R) reader structure"] +impl crate::Readable for SEQCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [seqctrl::W](W) writer structure"] +impl crate::Writable for SEQCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SEQCTRL to value 0"] +impl crate::Resettable for SEQCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sdadc/seqstatus.rs b/pac/atsamc21n/src/sdadc/seqstatus.rs new file mode 100644 index 000000000000..db10e7ca448e --- /dev/null +++ b/pac/atsamc21n/src/sdadc/seqstatus.rs @@ -0,0 +1,73 @@ +#[doc = "Register `SEQSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SEQSTATE` reader - Sequence State"] +pub struct SEQSTATE_R(crate::FieldReader); +impl SEQSTATE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SEQSTATE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEQSTATE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEQBUSY` reader - Sequence Busy"] +pub struct SEQBUSY_R(crate::FieldReader); +impl SEQBUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SEQBUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEQBUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:3 - Sequence State"] + #[inline(always)] + pub fn seqstate(&self) -> SEQSTATE_R { + SEQSTATE_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 7 - Sequence Busy"] + #[inline(always)] + pub fn seqbusy(&self) -> SEQBUSY_R { + SEQBUSY_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +#[doc = "Sequence Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [seqstatus](index.html) module"] +pub struct SEQSTATUS_SPEC; +impl crate::RegisterSpec for SEQSTATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [seqstatus::R](R) reader structure"] +impl crate::Readable for SEQSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SEQSTATUS to value 0"] +impl crate::Resettable for SEQSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sdadc/shiftcorr.rs b/pac/atsamc21n/src/sdadc/shiftcorr.rs new file mode 100644 index 000000000000..a5940537700e --- /dev/null +++ b/pac/atsamc21n/src/sdadc/shiftcorr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `SHIFTCORR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SHIFTCORR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SHIFTCORR` reader - Shift Correction Value"] +pub struct SHIFTCORR_R(crate::FieldReader); +impl SHIFTCORR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SHIFTCORR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SHIFTCORR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SHIFTCORR` writer - Shift Correction Value"] +pub struct SHIFTCORR_W<'a> { + w: &'a mut W, +} +impl<'a> SHIFTCORR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Shift Correction Value"] + #[inline(always)] + pub fn shiftcorr(&self) -> SHIFTCORR_R { + SHIFTCORR_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Shift Correction Value"] + #[inline(always)] + pub fn shiftcorr(&mut self) -> SHIFTCORR_W { + SHIFTCORR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Shift Correction\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [shiftcorr](index.html) module"] +pub struct SHIFTCORR_SPEC; +impl crate::RegisterSpec for SHIFTCORR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [shiftcorr::R](R) reader structure"] +impl crate::Readable for SHIFTCORR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [shiftcorr::W](W) writer structure"] +impl crate::Writable for SHIFTCORR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SHIFTCORR to value 0"] +impl crate::Resettable for SHIFTCORR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sdadc/swtrig.rs b/pac/atsamc21n/src/sdadc/swtrig.rs new file mode 100644 index 000000000000..7656a614dd67 --- /dev/null +++ b/pac/atsamc21n/src/sdadc/swtrig.rs @@ -0,0 +1,160 @@ +#[doc = "Register `SWTRIG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SWTRIG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FLUSH` reader - SDADC Flush"] +pub struct FLUSH_R(crate::FieldReader); +impl FLUSH_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FLUSH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FLUSH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLUSH` writer - SDADC Flush"] +pub struct FLUSH_W<'a> { + w: &'a mut W, +} +impl<'a> FLUSH_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `START` reader - Start SDADC Conversion"] +pub struct START_R(crate::FieldReader); +impl START_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + START_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for START_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `START` writer - Start SDADC Conversion"] +pub struct START_W<'a> { + w: &'a mut W, +} +impl<'a> START_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - SDADC Flush"] + #[inline(always)] + pub fn flush(&self) -> FLUSH_R { + FLUSH_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Start SDADC Conversion"] + #[inline(always)] + pub fn start(&self) -> START_R { + START_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - SDADC Flush"] + #[inline(always)] + pub fn flush(&mut self) -> FLUSH_W { + FLUSH_W { w: self } + } + #[doc = "Bit 1 - Start SDADC Conversion"] + #[inline(always)] + pub fn start(&mut self) -> START_W { + START_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Software Trigger\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [swtrig](index.html) module"] +pub struct SWTRIG_SPEC; +impl crate::RegisterSpec for SWTRIG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [swtrig::R](R) reader structure"] +impl crate::Readable for SWTRIG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [swtrig::W](W) writer structure"] +impl crate::Writable for SWTRIG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SWTRIG to value 0"] +impl crate::Resettable for SWTRIG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sdadc/syncbusy.rs b/pac/atsamc21n/src/sdadc/syncbusy.rs new file mode 100644 index 000000000000..519fa5e8a57f --- /dev/null +++ b/pac/atsamc21n/src/sdadc/syncbusy.rs @@ -0,0 +1,273 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - SWRST Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - ENABLE Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLC` reader - CTRLC Synchronization Busy"] +pub struct CTRLC_R(crate::FieldReader); +impl CTRLC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INPUTCTRL` reader - INPUTCTRL Synchronization Busy"] +pub struct INPUTCTRL_R(crate::FieldReader); +impl INPUTCTRL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INPUTCTRL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INPUTCTRL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINCTRL` reader - WINCTRL Synchronization Busy"] +pub struct WINCTRL_R(crate::FieldReader); +impl WINCTRL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINCTRL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINCTRL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINLT` reader - WINLT Synchronization Busy"] +pub struct WINLT_R(crate::FieldReader); +impl WINLT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINLT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINLT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINUT` reader - WINUT Synchronization Busy"] +pub struct WINUT_R(crate::FieldReader); +impl WINUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OFFSETCORR` reader - OFFSETCTRL Synchronization Busy"] +pub struct OFFSETCORR_R(crate::FieldReader); +impl OFFSETCORR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OFFSETCORR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OFFSETCORR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GAINCORR` reader - GAINCORR Synchronization Busy"] +pub struct GAINCORR_R(crate::FieldReader); +impl GAINCORR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GAINCORR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GAINCORR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SHIFTCORR` reader - SHIFTCORR Synchronization Busy"] +pub struct SHIFTCORR_R(crate::FieldReader); +impl SHIFTCORR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SHIFTCORR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SHIFTCORR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG` reader - SWTRG Synchronization Busy"] +pub struct SWTRIG_R(crate::FieldReader); +impl SWTRIG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWTRIG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ANACTRL` reader - ANACTRL Synchronization Busy"] +pub struct ANACTRL_R(crate::FieldReader); +impl ANACTRL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ANACTRL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ANACTRL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - SWRST Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ENABLE Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - CTRLC Synchronization Busy"] + #[inline(always)] + pub fn ctrlc(&self) -> CTRLC_R { + CTRLC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - INPUTCTRL Synchronization Busy"] + #[inline(always)] + pub fn inputctrl(&self) -> INPUTCTRL_R { + INPUTCTRL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - WINCTRL Synchronization Busy"] + #[inline(always)] + pub fn winctrl(&self) -> WINCTRL_R { + WINCTRL_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - WINLT Synchronization Busy"] + #[inline(always)] + pub fn winlt(&self) -> WINLT_R { + WINLT_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - WINUT Synchronization Busy"] + #[inline(always)] + pub fn winut(&self) -> WINUT_R { + WINUT_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - OFFSETCTRL Synchronization Busy"] + #[inline(always)] + pub fn offsetcorr(&self) -> OFFSETCORR_R { + OFFSETCORR_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - GAINCORR Synchronization Busy"] + #[inline(always)] + pub fn gaincorr(&self) -> GAINCORR_R { + GAINCORR_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - SHIFTCORR Synchronization Busy"] + #[inline(always)] + pub fn shiftcorr(&self) -> SHIFTCORR_R { + SHIFTCORR_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - SWTRG Synchronization Busy"] + #[inline(always)] + pub fn swtrig(&self) -> SWTRIG_R { + SWTRIG_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - ANACTRL Synchronization Busy"] + #[inline(always)] + pub fn anactrl(&self) -> ANACTRL_R { + ANACTRL_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +#[doc = "Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sdadc/winctrl.rs b/pac/atsamc21n/src/sdadc/winctrl.rs new file mode 100644 index 000000000000..ed0d2d4fe006 --- /dev/null +++ b/pac/atsamc21n/src/sdadc/winctrl.rs @@ -0,0 +1,103 @@ +#[doc = "Register `WINCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WINCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WINMODE` reader - Window Monitor Mode"] +pub struct WINMODE_R(crate::FieldReader); +impl WINMODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WINMODE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMODE` writer - Window Monitor Mode"] +pub struct WINMODE_W<'a> { + w: &'a mut W, +} +impl<'a> WINMODE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Window Monitor Mode"] + #[inline(always)] + pub fn winmode(&self) -> WINMODE_R { + WINMODE_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Window Monitor Mode"] + #[inline(always)] + pub fn winmode(&mut self) -> WINMODE_W { + WINMODE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Window Monitor Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [winctrl](index.html) module"] +pub struct WINCTRL_SPEC; +impl crate::RegisterSpec for WINCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [winctrl::R](R) reader structure"] +impl crate::Readable for WINCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [winctrl::W](W) writer structure"] +impl crate::Writable for WINCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WINCTRL to value 0"] +impl crate::Resettable for WINCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sdadc/winlt.rs b/pac/atsamc21n/src/sdadc/winlt.rs new file mode 100644 index 000000000000..be16283e9e36 --- /dev/null +++ b/pac/atsamc21n/src/sdadc/winlt.rs @@ -0,0 +1,103 @@ +#[doc = "Register `WINLT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WINLT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WINLT` reader - Window Lower Threshold"] +pub struct WINLT_R(crate::FieldReader); +impl WINLT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + WINLT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINLT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINLT` writer - Window Lower Threshold"] +pub struct WINLT_W<'a> { + w: &'a mut W, +} +impl<'a> WINLT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Window Lower Threshold"] + #[inline(always)] + pub fn winlt(&self) -> WINLT_R { + WINLT_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Window Lower Threshold"] + #[inline(always)] + pub fn winlt(&mut self) -> WINLT_W { + WINLT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Window Monitor Lower Threshold\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [winlt](index.html) module"] +pub struct WINLT_SPEC; +impl crate::RegisterSpec for WINLT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [winlt::R](R) reader structure"] +impl crate::Readable for WINLT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [winlt::W](W) writer structure"] +impl crate::Writable for WINLT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WINLT to value 0"] +impl crate::Resettable for WINLT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sdadc/winut.rs b/pac/atsamc21n/src/sdadc/winut.rs new file mode 100644 index 000000000000..7dc20e7c5f9e --- /dev/null +++ b/pac/atsamc21n/src/sdadc/winut.rs @@ -0,0 +1,103 @@ +#[doc = "Register `WINUT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WINUT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WINUT` reader - Window Upper Threshold"] +pub struct WINUT_R(crate::FieldReader); +impl WINUT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + WINUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINUT` writer - Window Upper Threshold"] +pub struct WINUT_W<'a> { + w: &'a mut W, +} +impl<'a> WINUT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Window Upper Threshold"] + #[inline(always)] + pub fn winut(&self) -> WINUT_R { + WINUT_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Window Upper Threshold"] + #[inline(always)] + pub fn winut(&mut self) -> WINUT_W { + WINUT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Window Monitor Upper Threshold\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [winut](index.html) module"] +pub struct WINUT_SPEC; +impl crate::RegisterSpec for WINUT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [winut::R](R) reader structure"] +impl crate::Readable for WINUT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [winut::W](W) writer structure"] +impl crate::Writable for WINUT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WINUT to value 0"] +impl crate::Resettable for WINUT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sercom0.rs b/pac/atsamc21n/src/sercom0.rs new file mode 100644 index 000000000000..da7b62f750c6 --- /dev/null +++ b/pac/atsamc21n/src/sercom0.rs @@ -0,0 +1,327 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved_0_i2cm: [u8; 0x31], +} +impl RegisterBlock { + #[doc = "0x00..0x31 - USART INTERNAL CLOCK Mode"] + #[inline(always)] + pub fn usart_int(&self) -> &USART_INT { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const USART_INT) } + } + #[doc = "0x00..0x31 - USART EXTERNAL CLOCK Mode"] + #[inline(always)] + pub fn usart_ext(&self) -> &USART_EXT { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const USART_EXT) } + } + #[doc = "0x00..0x31 - SPI Master Mode"] + #[inline(always)] + pub fn spim(&self) -> &SPIM { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const SPIM) } + } + #[doc = "0x00..0x31 - SPI Slave Mode"] + #[inline(always)] + pub fn spis(&self) -> &SPIS { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const SPIS) } + } + #[doc = "0x00..0x29 - I2C Slave Mode"] + #[inline(always)] + pub fn i2cs(&self) -> &I2CS { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const I2CS) } + } + #[doc = "0x00..0x31 - I2C Master Mode"] + #[inline(always)] + pub fn i2cm(&self) -> &I2CM { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const I2CM) } + } +} +#[doc = r"Register block"] +#[repr(C)] +pub struct I2CM { + #[doc = "0x00 - I2CM Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - I2CM Control B"] + pub ctrlb: crate::Reg, + _reserved2: [u8; 0x04], + #[doc = "0x0c - I2CM Baud Rate"] + pub baud: crate::Reg, + _reserved3: [u8; 0x04], + #[doc = "0x14 - I2CM Interrupt Enable Clear"] + pub intenclr: crate::Reg, + _reserved4: [u8; 0x01], + #[doc = "0x16 - I2CM Interrupt Enable Set"] + pub intenset: crate::Reg, + _reserved5: [u8; 0x01], + #[doc = "0x18 - I2CM Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x1a - I2CM Status"] + pub status: crate::Reg, + #[doc = "0x1c - I2CM Synchronization Busy"] + pub syncbusy: crate::Reg, + _reserved8: [u8; 0x04], + #[doc = "0x24 - I2CM Address"] + pub addr: crate::Reg, + #[doc = "0x28 - I2CM Data"] + pub data: crate::Reg, + _reserved10: [u8; 0x07], + #[doc = "0x30 - I2CM Debug Control"] + pub dbgctrl: crate::Reg, +} +#[doc = r"Register block"] +#[doc = "I2C Master Mode"] +pub mod i2cm; +#[doc = r"Register block"] +#[repr(C)] +pub struct I2CS { + #[doc = "0x00 - I2CS Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - I2CS Control B"] + pub ctrlb: crate::Reg, + _reserved2: [u8; 0x0c], + #[doc = "0x14 - I2CS Interrupt Enable Clear"] + pub intenclr: crate::Reg, + _reserved3: [u8; 0x01], + #[doc = "0x16 - I2CS Interrupt Enable Set"] + pub intenset: crate::Reg, + _reserved4: [u8; 0x01], + #[doc = "0x18 - I2CS Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved5: [u8; 0x01], + #[doc = "0x1a - I2CS Status"] + pub status: crate::Reg, + #[doc = "0x1c - I2CS Synchronization Busy"] + pub syncbusy: crate::Reg, + _reserved7: [u8; 0x04], + #[doc = "0x24 - I2CS Address"] + pub addr: crate::Reg, + #[doc = "0x28 - I2CS Data"] + pub data: crate::Reg, +} +#[doc = r"Register block"] +#[doc = "I2C Slave Mode"] +pub mod i2cs; +#[doc = r"Register block"] +#[repr(C)] +pub struct SPIS { + #[doc = "0x00 - SPIS Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - SPIS Control B"] + pub ctrlb: crate::Reg, + _reserved2: [u8; 0x04], + #[doc = "0x0c - SPIS Baud Rate"] + pub baud: crate::Reg, + _reserved3: [u8; 0x07], + #[doc = "0x14 - SPIS Interrupt Enable Clear"] + pub intenclr: crate::Reg, + _reserved4: [u8; 0x01], + #[doc = "0x16 - SPIS Interrupt Enable Set"] + pub intenset: crate::Reg, + _reserved5: [u8; 0x01], + #[doc = "0x18 - SPIS Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x1a - SPIS Status"] + pub status: crate::Reg, + #[doc = "0x1c - SPIS Synchronization Busy"] + pub syncbusy: crate::Reg, + _reserved8: [u8; 0x04], + #[doc = "0x24 - SPIS Address"] + pub addr: crate::Reg, + #[doc = "0x28 - SPIS Data"] + pub data: crate::Reg, + _reserved10: [u8; 0x04], + #[doc = "0x30 - SPIS Debug Control"] + pub dbgctrl: crate::Reg, +} +#[doc = r"Register block"] +#[doc = "SPI Slave Mode"] +pub mod spis; +#[doc = r"Register block"] +#[repr(C)] +pub struct SPIM { + #[doc = "0x00 - SPIM Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - SPIM Control B"] + pub ctrlb: crate::Reg, + _reserved2: [u8; 0x04], + #[doc = "0x0c - SPIM Baud Rate"] + pub baud: crate::Reg, + _reserved3: [u8; 0x07], + #[doc = "0x14 - SPIM Interrupt Enable Clear"] + pub intenclr: crate::Reg, + _reserved4: [u8; 0x01], + #[doc = "0x16 - SPIM Interrupt Enable Set"] + pub intenset: crate::Reg, + _reserved5: [u8; 0x01], + #[doc = "0x18 - SPIM Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x1a - SPIM Status"] + pub status: crate::Reg, + #[doc = "0x1c - SPIM Synchronization Busy"] + pub syncbusy: crate::Reg, + _reserved8: [u8; 0x04], + #[doc = "0x24 - SPIM Address"] + pub addr: crate::Reg, + #[doc = "0x28 - SPIM Data"] + pub data: crate::Reg, + _reserved10: [u8; 0x04], + #[doc = "0x30 - SPIM Debug Control"] + pub dbgctrl: crate::Reg, +} +#[doc = r"Register block"] +#[doc = "SPI Master Mode"] +pub mod spim; +#[doc = r"Register block"] +#[repr(C)] +pub struct USART_EXT { + #[doc = "0x00 - USART_EXT Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - USART_EXT Control B"] + pub ctrlb: crate::Reg, + #[doc = "0x08 - USART_EXT Control C"] + pub ctrlc: crate::Reg, + _reserved_3_baud: [u8; 0x02], + #[doc = "0x0e - USART_EXT Receive Pulse Length"] + pub rxpl: crate::Reg, + _reserved5: [u8; 0x05], + #[doc = "0x14 - USART_EXT Interrupt Enable Clear"] + pub intenclr: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x16 - USART_EXT Interrupt Enable Set"] + pub intenset: crate::Reg, + _reserved7: [u8; 0x01], + #[doc = "0x18 - USART_EXT Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved8: [u8; 0x01], + #[doc = "0x1a - USART_EXT Status"] + pub status: crate::Reg, + #[doc = "0x1c - USART_EXT Synchronization Busy"] + pub syncbusy: crate::Reg, + _reserved10: [u8; 0x08], + #[doc = "0x28 - USART_EXT Data"] + pub data: crate::Reg, + _reserved11: [u8; 0x06], + #[doc = "0x30 - USART_EXT Debug Control"] + pub dbgctrl: crate::Reg, +} +impl USART_EXT { + #[doc = "0x0c - USART_EXT Baud Rate"] + #[inline(always)] + pub fn baud_usartfp_mode( + &self, + ) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } + #[doc = "0x0c - USART_EXT Baud Rate"] + #[inline(always)] + pub fn baud_fracfp_mode( + &self, + ) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } + #[doc = "0x0c - USART_EXT Baud Rate"] + #[inline(always)] + pub fn baud_frac_mode( + &self, + ) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } + #[doc = "0x0c - USART_EXT Baud Rate"] + #[inline(always)] + pub fn baud(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } +} +#[doc = r"Register block"] +#[doc = "USART EXTERNAL CLOCK Mode"] +pub mod usart_ext; +#[doc = r"Register block"] +#[repr(C)] +pub struct USART_INT { + #[doc = "0x00 - USART_INT Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - USART_INT Control B"] + pub ctrlb: crate::Reg, + #[doc = "0x08 - USART_INT Control C"] + pub ctrlc: crate::Reg, + _reserved_3_baud: [u8; 0x02], + #[doc = "0x0e - USART_INT Receive Pulse Length"] + pub rxpl: crate::Reg, + _reserved5: [u8; 0x05], + #[doc = "0x14 - USART_INT Interrupt Enable Clear"] + pub intenclr: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x16 - USART_INT Interrupt Enable Set"] + pub intenset: crate::Reg, + _reserved7: [u8; 0x01], + #[doc = "0x18 - USART_INT Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved8: [u8; 0x01], + #[doc = "0x1a - USART_INT Status"] + pub status: crate::Reg, + #[doc = "0x1c - USART_INT Synchronization Busy"] + pub syncbusy: crate::Reg, + _reserved10: [u8; 0x08], + #[doc = "0x28 - USART_INT Data"] + pub data: crate::Reg, + _reserved11: [u8; 0x06], + #[doc = "0x30 - USART_INT Debug Control"] + pub dbgctrl: crate::Reg, +} +impl USART_INT { + #[doc = "0x0c - USART_INT Baud Rate"] + #[inline(always)] + pub fn baud_usartfp_mode( + &self, + ) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } + #[doc = "0x0c - USART_INT Baud Rate"] + #[inline(always)] + pub fn baud_fracfp_mode( + &self, + ) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } + #[doc = "0x0c - USART_INT Baud Rate"] + #[inline(always)] + pub fn baud_frac_mode( + &self, + ) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } + #[doc = "0x0c - USART_INT Baud Rate"] + #[inline(always)] + pub fn baud(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } +} +#[doc = r"Register block"] +#[doc = "USART INTERNAL CLOCK Mode"] +pub mod usart_int; diff --git a/pac/atsamc21n/src/sercom0/i2cm.rs b/pac/atsamc21n/src/sercom0/i2cm.rs new file mode 100644 index 000000000000..8aa217da8b18 --- /dev/null +++ b/pac/atsamc21n/src/sercom0/i2cm.rs @@ -0,0 +1,44 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "I2CM Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "I2CM Control B"] +pub mod ctrlb; +#[doc = "BAUD register accessor: an alias for `Reg`"] +pub type BAUD = crate::Reg; +#[doc = "I2CM Baud Rate"] +pub mod baud; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "I2CM Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "I2CM Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "I2CM Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "I2CM Status"] +pub mod status; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "I2CM Synchronization Busy"] +pub mod syncbusy; +#[doc = "ADDR register accessor: an alias for `Reg`"] +pub type ADDR = crate::Reg; +#[doc = "I2CM Address"] +pub mod addr; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "I2CM Data"] +pub mod data; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "I2CM Debug Control"] +pub mod dbgctrl; diff --git a/pac/atsamc21n/src/sercom0/i2cm/addr.rs b/pac/atsamc21n/src/sercom0/i2cm/addr.rs new file mode 100644 index 000000000000..4efd19e824c6 --- /dev/null +++ b/pac/atsamc21n/src/sercom0/i2cm/addr.rs @@ -0,0 +1,281 @@ +#[doc = "Register `ADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ADDR` reader - Address Value"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - Address Value"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07ff) | (value as u32 & 0x07ff); + self.w + } +} +#[doc = "Field `LENEN` reader - Length Enable"] +pub struct LENEN_R(crate::FieldReader); +impl LENEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LENEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LENEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LENEN` writer - Length Enable"] +pub struct LENEN_W<'a> { + w: &'a mut W, +} +impl<'a> LENEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `HS` reader - High Speed Mode"] +pub struct HS_R(crate::FieldReader); +impl HS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HS` writer - High Speed Mode"] +pub struct HS_W<'a> { + w: &'a mut W, +} +impl<'a> HS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `TENBITEN` reader - Ten Bit Addressing Enable"] +pub struct TENBITEN_R(crate::FieldReader); +impl TENBITEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TENBITEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TENBITEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TENBITEN` writer - Ten Bit Addressing Enable"] +pub struct TENBITEN_W<'a> { + w: &'a mut W, +} +impl<'a> TENBITEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `LEN` reader - Length"] +pub struct LEN_R(crate::FieldReader); +impl LEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LEN` writer - Length"] +pub struct LEN_W<'a> { + w: &'a mut W, +} +impl<'a> LEN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:10 - Address Value"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new((self.bits & 0x07ff) as u16) + } + #[doc = "Bit 13 - Length Enable"] + #[inline(always)] + pub fn lenen(&self) -> LENEN_R { + LENEN_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - High Speed Mode"] + #[inline(always)] + pub fn hs(&self) -> HS_R { + HS_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Ten Bit Addressing Enable"] + #[inline(always)] + pub fn tenbiten(&self) -> TENBITEN_R { + TENBITEN_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:23 - Length"] + #[inline(always)] + pub fn len(&self) -> LEN_R { + LEN_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:10 - Address Value"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Bit 13 - Length Enable"] + #[inline(always)] + pub fn lenen(&mut self) -> LENEN_W { + LENEN_W { w: self } + } + #[doc = "Bit 14 - High Speed Mode"] + #[inline(always)] + pub fn hs(&mut self) -> HS_W { + HS_W { w: self } + } + #[doc = "Bit 15 - Ten Bit Addressing Enable"] + #[inline(always)] + pub fn tenbiten(&mut self) -> TENBITEN_W { + TENBITEN_W { w: self } + } + #[doc = "Bits 16:23 - Length"] + #[inline(always)] + pub fn len(&mut self) -> LEN_W { + LEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [addr](index.html) module"] +pub struct ADDR_SPEC; +impl crate::RegisterSpec for ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [addr::R](R) reader structure"] +impl crate::Readable for ADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [addr::W](W) writer structure"] +impl crate::Writable for ADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ADDR to value 0"] +impl crate::Resettable for ADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sercom0/i2cm/baud.rs b/pac/atsamc21n/src/sercom0/i2cm/baud.rs new file mode 100644 index 000000000000..7c98d3b5b0de --- /dev/null +++ b/pac/atsamc21n/src/sercom0/i2cm/baud.rs @@ -0,0 +1,214 @@ +#[doc = "Register `BAUD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +#[doc = "Field `BAUDLOW` reader - Baud Rate Value Low"] +pub struct BAUDLOW_R(crate::FieldReader); +impl BAUDLOW_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BAUDLOW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUDLOW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUDLOW` writer - Baud Rate Value Low"] +pub struct BAUDLOW_W<'a> { + w: &'a mut W, +} +impl<'a> BAUDLOW_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +#[doc = "Field `HSBAUD` reader - High Speed Baud Rate Value"] +pub struct HSBAUD_R(crate::FieldReader); +impl HSBAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + HSBAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HSBAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HSBAUD` writer - High Speed Baud Rate Value"] +pub struct HSBAUD_W<'a> { + w: &'a mut W, +} +impl<'a> HSBAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +#[doc = "Field `HSBAUDLOW` reader - High Speed Baud Rate Value Low"] +pub struct HSBAUDLOW_R(crate::FieldReader); +impl HSBAUDLOW_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + HSBAUDLOW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HSBAUDLOW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HSBAUDLOW` writer - High Speed Baud Rate Value Low"] +pub struct HSBAUDLOW_W<'a> { + w: &'a mut W, +} +impl<'a> HSBAUDLOW_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 24)) | ((value as u32 & 0xff) << 24); + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Baud Rate Value Low"] + #[inline(always)] + pub fn baudlow(&self) -> BAUDLOW_R { + BAUDLOW_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - High Speed Baud Rate Value"] + #[inline(always)] + pub fn hsbaud(&self) -> HSBAUD_R { + HSBAUD_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - High Speed Baud Rate Value Low"] + #[inline(always)] + pub fn hsbaudlow(&self) -> HSBAUDLOW_R { + HSBAUDLOW_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Bits 8:15 - Baud Rate Value Low"] + #[inline(always)] + pub fn baudlow(&mut self) -> BAUDLOW_W { + BAUDLOW_W { w: self } + } + #[doc = "Bits 16:23 - High Speed Baud Rate Value"] + #[inline(always)] + pub fn hsbaud(&mut self) -> HSBAUD_W { + HSBAUD_W { w: self } + } + #[doc = "Bits 24:31 - High Speed Baud Rate Value Low"] + #[inline(always)] + pub fn hsbaudlow(&mut self) -> HSBAUDLOW_W { + HSBAUDLOW_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud](index.html) module"] +pub struct BAUD_SPEC; +impl crate::RegisterSpec for BAUD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [baud::R](R) reader structure"] +impl crate::Readable for BAUD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud::W](W) writer structure"] +impl crate::Writable for BAUD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD to value 0"] +impl crate::Resettable for BAUD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sercom0/i2cm/ctrla.rs b/pac/atsamc21n/src/sercom0/i2cm/ctrla.rs new file mode 100644 index 000000000000..34fa668b7967 --- /dev/null +++ b/pac/atsamc21n/src/sercom0/i2cm/ctrla.rs @@ -0,0 +1,903 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: USART with external clock"] + USART_EXT_CLK = 0, + #[doc = "1: USART with internal clock"] + USART_INT_CLK = 1, + #[doc = "2: SPI in slave operation"] + SPI_SLAVE = 2, + #[doc = "3: SPI in master operation"] + SPI_MASTER = 3, + #[doc = "4: I2C slave operation"] + I2C_SLAVE = 4, + #[doc = "5: I2C master operation"] + I2C_MASTER = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::USART_EXT_CLK), + 1 => Some(MODE_A::USART_INT_CLK), + 2 => Some(MODE_A::SPI_SLAVE), + 3 => Some(MODE_A::SPI_MASTER), + 4 => Some(MODE_A::I2C_SLAVE), + 5 => Some(MODE_A::I2C_MASTER), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_EXT_CLK`"] + #[inline(always)] + pub fn is_usart_ext_clk(&self) -> bool { + **self == MODE_A::USART_EXT_CLK + } + #[doc = "Checks if the value of the field is `USART_INT_CLK`"] + #[inline(always)] + pub fn is_usart_int_clk(&self) -> bool { + **self == MODE_A::USART_INT_CLK + } + #[doc = "Checks if the value of the field is `SPI_SLAVE`"] + #[inline(always)] + pub fn is_spi_slave(&self) -> bool { + **self == MODE_A::SPI_SLAVE + } + #[doc = "Checks if the value of the field is `SPI_MASTER`"] + #[inline(always)] + pub fn is_spi_master(&self) -> bool { + **self == MODE_A::SPI_MASTER + } + #[doc = "Checks if the value of the field is `I2C_SLAVE`"] + #[inline(always)] + pub fn is_i2c_slave(&self) -> bool { + **self == MODE_A::I2C_SLAVE + } + #[doc = "Checks if the value of the field is `I2C_MASTER`"] + #[inline(always)] + pub fn is_i2c_master(&self) -> bool { + **self == MODE_A::I2C_MASTER + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART with external clock"] + #[inline(always)] + pub fn usart_ext_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_EXT_CLK) + } + #[doc = "USART with internal clock"] + #[inline(always)] + pub fn usart_int_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_INT_CLK) + } + #[doc = "SPI in slave operation"] + #[inline(always)] + pub fn spi_slave(self) -> &'a mut W { + self.variant(MODE_A::SPI_SLAVE) + } + #[doc = "SPI in master operation"] + #[inline(always)] + pub fn spi_master(self) -> &'a mut W { + self.variant(MODE_A::SPI_MASTER) + } + #[doc = "I2C slave operation"] + #[inline(always)] + pub fn i2c_slave(self) -> &'a mut W { + self.variant(MODE_A::I2C_SLAVE) + } + #[doc = "I2C master operation"] + #[inline(always)] + pub fn i2c_master(self) -> &'a mut W { + self.variant(MODE_A::I2C_MASTER) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 2)) | ((value as u32 & 0x07) << 2); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `PINOUT` reader - Pin Usage"] +pub struct PINOUT_R(crate::FieldReader); +impl PINOUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PINOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PINOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PINOUT` writer - Pin Usage"] +pub struct PINOUT_W<'a> { + w: &'a mut W, +} +impl<'a> PINOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "SDA Hold Time\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SDAHOLD_A { + #[doc = "0: Disabled"] + DISABLE = 0, + #[doc = "1: 50-100ns hold time"] + _75NS = 1, + #[doc = "2: 300-600ns hold time"] + _450NS = 2, + #[doc = "3: 400-800ns hold time"] + _600NS = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SDAHOLD_A) -> Self { + variant as _ + } +} +#[doc = "Field `SDAHOLD` reader - SDA Hold Time"] +pub struct SDAHOLD_R(crate::FieldReader); +impl SDAHOLD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SDAHOLD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SDAHOLD_A { + match self.bits { + 0 => SDAHOLD_A::DISABLE, + 1 => SDAHOLD_A::_75NS, + 2 => SDAHOLD_A::_450NS, + 3 => SDAHOLD_A::_600NS, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == SDAHOLD_A::DISABLE + } + #[doc = "Checks if the value of the field is `_75NS`"] + #[inline(always)] + pub fn is_75ns(&self) -> bool { + **self == SDAHOLD_A::_75NS + } + #[doc = "Checks if the value of the field is `_450NS`"] + #[inline(always)] + pub fn is_450ns(&self) -> bool { + **self == SDAHOLD_A::_450NS + } + #[doc = "Checks if the value of the field is `_600NS`"] + #[inline(always)] + pub fn is_600ns(&self) -> bool { + **self == SDAHOLD_A::_600NS + } +} +impl core::ops::Deref for SDAHOLD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SDAHOLD` writer - SDA Hold Time"] +pub struct SDAHOLD_W<'a> { + w: &'a mut W, +} +impl<'a> SDAHOLD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SDAHOLD_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(SDAHOLD_A::DISABLE) + } + #[doc = "50-100ns hold time"] + #[inline(always)] + pub fn _75ns(self) -> &'a mut W { + self.variant(SDAHOLD_A::_75NS) + } + #[doc = "300-600ns hold time"] + #[inline(always)] + pub fn _450ns(self) -> &'a mut W { + self.variant(SDAHOLD_A::_450NS) + } + #[doc = "400-800ns hold time"] + #[inline(always)] + pub fn _600ns(self) -> &'a mut W { + self.variant(SDAHOLD_A::_600NS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 20)) | ((value as u32 & 0x03) << 20); + self.w + } +} +#[doc = "Field `MEXTTOEN` reader - Master SCL Low Extend Timeout"] +pub struct MEXTTOEN_R(crate::FieldReader); +impl MEXTTOEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MEXTTOEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MEXTTOEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MEXTTOEN` writer - Master SCL Low Extend Timeout"] +pub struct MEXTTOEN_W<'a> { + w: &'a mut W, +} +impl<'a> MEXTTOEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `SEXTTOEN` reader - Slave SCL Low Extend Timeout"] +pub struct SEXTTOEN_R(crate::FieldReader); +impl SEXTTOEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SEXTTOEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEXTTOEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEXTTOEN` writer - Slave SCL Low Extend Timeout"] +pub struct SEXTTOEN_W<'a> { + w: &'a mut W, +} +impl<'a> SEXTTOEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Transfer Speed\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SPEED_A { + #[doc = "0: Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz"] + STANDARD_AND_FAST_MODE = 0, + #[doc = "1: Fast-mode Plus Upto 1MHz"] + FASTPLUS_MODE = 1, + #[doc = "2: High-speed mode Upto 3.4MHz"] + HIGH_SPEED_MODE = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SPEED_A) -> Self { + variant as _ + } +} +#[doc = "Field `SPEED` reader - Transfer Speed"] +pub struct SPEED_R(crate::FieldReader); +impl SPEED_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SPEED_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SPEED_A::STANDARD_AND_FAST_MODE), + 1 => Some(SPEED_A::FASTPLUS_MODE), + 2 => Some(SPEED_A::HIGH_SPEED_MODE), + _ => None, + } + } + #[doc = "Checks if the value of the field is `STANDARD_AND_FAST_MODE`"] + #[inline(always)] + pub fn is_standard_and_fast_mode(&self) -> bool { + **self == SPEED_A::STANDARD_AND_FAST_MODE + } + #[doc = "Checks if the value of the field is `FASTPLUS_MODE`"] + #[inline(always)] + pub fn is_fastplus_mode(&self) -> bool { + **self == SPEED_A::FASTPLUS_MODE + } + #[doc = "Checks if the value of the field is `HIGH_SPEED_MODE`"] + #[inline(always)] + pub fn is_high_speed_mode(&self) -> bool { + **self == SPEED_A::HIGH_SPEED_MODE + } +} +impl core::ops::Deref for SPEED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SPEED` writer - Transfer Speed"] +pub struct SPEED_W<'a> { + w: &'a mut W, +} +impl<'a> SPEED_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SPEED_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz"] + #[inline(always)] + pub fn standard_and_fast_mode(self) -> &'a mut W { + self.variant(SPEED_A::STANDARD_AND_FAST_MODE) + } + #[doc = "Fast-mode Plus Upto 1MHz"] + #[inline(always)] + pub fn fastplus_mode(self) -> &'a mut W { + self.variant(SPEED_A::FASTPLUS_MODE) + } + #[doc = "High-speed mode Upto 3.4MHz"] + #[inline(always)] + pub fn high_speed_mode(self) -> &'a mut W { + self.variant(SPEED_A::HIGH_SPEED_MODE) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 24)) | ((value as u32 & 0x03) << 24); + self.w + } +} +#[doc = "Field `SCLSM` reader - SCL Clock Stretch Mode"] +pub struct SCLSM_R(crate::FieldReader); +impl SCLSM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SCLSM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SCLSM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SCLSM` writer - SCL Clock Stretch Mode"] +pub struct SCLSM_W<'a> { + w: &'a mut W, +} +impl<'a> SCLSM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +#[doc = "Inactive Time-Out\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum INACTOUT_A { + #[doc = "0: Disabled"] + DISABLE = 0, + #[doc = "1: 5-6 SCL Time-Out(50-60us)"] + _55US = 1, + #[doc = "2: 10-11 SCL Time-Out(100-110us)"] + _105US = 2, + #[doc = "3: 20-21 SCL Time-Out(200-210us)"] + _205US = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: INACTOUT_A) -> Self { + variant as _ + } +} +#[doc = "Field `INACTOUT` reader - Inactive Time-Out"] +pub struct INACTOUT_R(crate::FieldReader); +impl INACTOUT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + INACTOUT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INACTOUT_A { + match self.bits { + 0 => INACTOUT_A::DISABLE, + 1 => INACTOUT_A::_55US, + 2 => INACTOUT_A::_105US, + 3 => INACTOUT_A::_205US, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == INACTOUT_A::DISABLE + } + #[doc = "Checks if the value of the field is `_55US`"] + #[inline(always)] + pub fn is_55us(&self) -> bool { + **self == INACTOUT_A::_55US + } + #[doc = "Checks if the value of the field is `_105US`"] + #[inline(always)] + pub fn is_105us(&self) -> bool { + **self == INACTOUT_A::_105US + } + #[doc = "Checks if the value of the field is `_205US`"] + #[inline(always)] + pub fn is_205us(&self) -> bool { + **self == INACTOUT_A::_205US + } +} +impl core::ops::Deref for INACTOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INACTOUT` writer - Inactive Time-Out"] +pub struct INACTOUT_W<'a> { + w: &'a mut W, +} +impl<'a> INACTOUT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: INACTOUT_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(INACTOUT_A::DISABLE) + } + #[doc = "5-6 SCL Time-Out(50-60us)"] + #[inline(always)] + pub fn _55us(self) -> &'a mut W { + self.variant(INACTOUT_A::_55US) + } + #[doc = "10-11 SCL Time-Out(100-110us)"] + #[inline(always)] + pub fn _105us(self) -> &'a mut W { + self.variant(INACTOUT_A::_105US) + } + #[doc = "20-21 SCL Time-Out(200-210us)"] + #[inline(always)] + pub fn _205us(self) -> &'a mut W { + self.variant(INACTOUT_A::_205US) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 28)) | ((value as u32 & 0x03) << 28); + self.w + } +} +#[doc = "Field `LOWTOUTEN` reader - SCL Low Timeout Enable"] +pub struct LOWTOUTEN_R(crate::FieldReader); +impl LOWTOUTEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LOWTOUTEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOWTOUTEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LOWTOUTEN` writer - SCL Low Timeout Enable"] +pub struct LOWTOUTEN_W<'a> { + w: &'a mut W, +} +impl<'a> LOWTOUTEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x07) as u8) + } + #[doc = "Bit 7 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 16 - Pin Usage"] + #[inline(always)] + pub fn pinout(&self) -> PINOUT_R { + PINOUT_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bits 20:21 - SDA Hold Time"] + #[inline(always)] + pub fn sdahold(&self) -> SDAHOLD_R { + SDAHOLD_R::new(((self.bits >> 20) & 0x03) as u8) + } + #[doc = "Bit 22 - Master SCL Low Extend Timeout"] + #[inline(always)] + pub fn mexttoen(&self) -> MEXTTOEN_R { + MEXTTOEN_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttoen(&self) -> SEXTTOEN_R { + SEXTTOEN_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bits 24:25 - Transfer Speed"] + #[inline(always)] + pub fn speed(&self) -> SPEED_R { + SPEED_R::new(((self.bits >> 24) & 0x03) as u8) + } + #[doc = "Bit 27 - SCL Clock Stretch Mode"] + #[inline(always)] + pub fn sclsm(&self) -> SCLSM_R { + SCLSM_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bits 28:29 - Inactive Time-Out"] + #[inline(always)] + pub fn inactout(&self) -> INACTOUT_R { + INACTOUT_R::new(((self.bits >> 28) & 0x03) as u8) + } + #[doc = "Bit 30 - SCL Low Timeout Enable"] + #[inline(always)] + pub fn lowtouten(&self) -> LOWTOUTEN_R { + LOWTOUTEN_R::new(((self.bits >> 30) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 7 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 16 - Pin Usage"] + #[inline(always)] + pub fn pinout(&mut self) -> PINOUT_W { + PINOUT_W { w: self } + } + #[doc = "Bits 20:21 - SDA Hold Time"] + #[inline(always)] + pub fn sdahold(&mut self) -> SDAHOLD_W { + SDAHOLD_W { w: self } + } + #[doc = "Bit 22 - Master SCL Low Extend Timeout"] + #[inline(always)] + pub fn mexttoen(&mut self) -> MEXTTOEN_W { + MEXTTOEN_W { w: self } + } + #[doc = "Bit 23 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttoen(&mut self) -> SEXTTOEN_W { + SEXTTOEN_W { w: self } + } + #[doc = "Bits 24:25 - Transfer Speed"] + #[inline(always)] + pub fn speed(&mut self) -> SPEED_W { + SPEED_W { w: self } + } + #[doc = "Bit 27 - SCL Clock Stretch Mode"] + #[inline(always)] + pub fn sclsm(&mut self) -> SCLSM_W { + SCLSM_W { w: self } + } + #[doc = "Bits 28:29 - Inactive Time-Out"] + #[inline(always)] + pub fn inactout(&mut self) -> INACTOUT_W { + INACTOUT_W { w: self } + } + #[doc = "Bit 30 - SCL Low Timeout Enable"] + #[inline(always)] + pub fn lowtouten(&mut self) -> LOWTOUTEN_W { + LOWTOUTEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sercom0/i2cm/ctrlb.rs b/pac/atsamc21n/src/sercom0/i2cm/ctrlb.rs new file mode 100644 index 000000000000..ce534463c0da --- /dev/null +++ b/pac/atsamc21n/src/sercom0/i2cm/ctrlb.rs @@ -0,0 +1,244 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SMEN` reader - Smart Mode Enable"] +pub struct SMEN_R(crate::FieldReader); +impl SMEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SMEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SMEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SMEN` writer - Smart Mode Enable"] +pub struct SMEN_W<'a> { + w: &'a mut W, +} +impl<'a> SMEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `QCEN` reader - Quick Command Enable"] +pub struct QCEN_R(crate::FieldReader); +impl QCEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + QCEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for QCEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `QCEN` writer - Quick Command Enable"] +pub struct QCEN_W<'a> { + w: &'a mut W, +} +impl<'a> QCEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Field `ACKACT` reader - Acknowledge Action"] +pub struct ACKACT_R(crate::FieldReader); +impl ACKACT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ACKACT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ACKACT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ACKACT` writer - Acknowledge Action"] +pub struct ACKACT_W<'a> { + w: &'a mut W, +} +impl<'a> ACKACT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +impl R { + #[doc = "Bit 8 - Smart Mode Enable"] + #[inline(always)] + pub fn smen(&self) -> SMEN_R { + SMEN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Quick Command Enable"] + #[inline(always)] + pub fn qcen(&self) -> QCEN_R { + QCEN_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bits 16:17 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bit 18 - Acknowledge Action"] + #[inline(always)] + pub fn ackact(&self) -> ACKACT_R { + ACKACT_R::new(((self.bits >> 18) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 8 - Smart Mode Enable"] + #[inline(always)] + pub fn smen(&mut self) -> SMEN_W { + SMEN_W { w: self } + } + #[doc = "Bit 9 - Quick Command Enable"] + #[inline(always)] + pub fn qcen(&mut self) -> QCEN_W { + QCEN_W { w: self } + } + #[doc = "Bits 16:17 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Bit 18 - Acknowledge Action"] + #[inline(always)] + pub fn ackact(&mut self) -> ACKACT_W { + ACKACT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sercom0/i2cm/data.rs b/pac/atsamc21n/src/sercom0/i2cm/data.rs new file mode 100644 index 000000000000..cf204596d3a6 --- /dev/null +++ b/pac/atsamc21n/src/sercom0/i2cm/data.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data Value"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data Value"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Data Value"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Value"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sercom0/i2cm/dbgctrl.rs b/pac/atsamc21n/src/sercom0/i2cm/dbgctrl.rs new file mode 100644 index 000000000000..0fffdb4c6e39 --- /dev/null +++ b/pac/atsamc21n/src/sercom0/i2cm/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGSTOP` reader - Debug Mode"] +pub struct DBGSTOP_R(crate::FieldReader); +impl DBGSTOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGSTOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGSTOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGSTOP` writer - Debug Mode"] +pub struct DBGSTOP_W<'a> { + w: &'a mut W, +} +impl<'a> DBGSTOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&self) -> DBGSTOP_R { + DBGSTOP_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&mut self) -> DBGSTOP_W { + DBGSTOP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sercom0/i2cm/intenclr.rs b/pac/atsamc21n/src/sercom0/i2cm/intenclr.rs new file mode 100644 index 000000000000..17f067a55656 --- /dev/null +++ b/pac/atsamc21n/src/sercom0/i2cm/intenclr.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MB` reader - Master On Bus Interrupt Disable"] +pub struct MB_R(crate::FieldReader); +impl MB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MB` writer - Master On Bus Interrupt Disable"] +pub struct MB_W<'a> { + w: &'a mut W, +} +impl<'a> MB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SB` reader - Slave On Bus Interrupt Disable"] +pub struct SB_R(crate::FieldReader); +impl SB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SB` writer - Slave On Bus Interrupt Disable"] +pub struct SB_W<'a> { + w: &'a mut W, +} +impl<'a> SB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Disable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Disable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Master On Bus Interrupt Disable"] + #[inline(always)] + pub fn mb(&self) -> MB_R { + MB_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Slave On Bus Interrupt Disable"] + #[inline(always)] + pub fn sb(&self) -> SB_R { + SB_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Master On Bus Interrupt Disable"] + #[inline(always)] + pub fn mb(&mut self) -> MB_W { + MB_W { w: self } + } + #[doc = "Bit 1 - Slave On Bus Interrupt Disable"] + #[inline(always)] + pub fn sb(&mut self) -> SB_W { + SB_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sercom0/i2cm/intenset.rs b/pac/atsamc21n/src/sercom0/i2cm/intenset.rs new file mode 100644 index 000000000000..a0cbf96b3aa0 --- /dev/null +++ b/pac/atsamc21n/src/sercom0/i2cm/intenset.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MB` reader - Master On Bus Interrupt Enable"] +pub struct MB_R(crate::FieldReader); +impl MB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MB` writer - Master On Bus Interrupt Enable"] +pub struct MB_W<'a> { + w: &'a mut W, +} +impl<'a> MB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SB` reader - Slave On Bus Interrupt Enable"] +pub struct SB_R(crate::FieldReader); +impl SB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SB` writer - Slave On Bus Interrupt Enable"] +pub struct SB_W<'a> { + w: &'a mut W, +} +impl<'a> SB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Master On Bus Interrupt Enable"] + #[inline(always)] + pub fn mb(&self) -> MB_R { + MB_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Slave On Bus Interrupt Enable"] + #[inline(always)] + pub fn sb(&self) -> SB_R { + SB_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Master On Bus Interrupt Enable"] + #[inline(always)] + pub fn mb(&mut self) -> MB_W { + MB_W { w: self } + } + #[doc = "Bit 1 - Slave On Bus Interrupt Enable"] + #[inline(always)] + pub fn sb(&mut self) -> SB_W { + SB_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sercom0/i2cm/intflag.rs b/pac/atsamc21n/src/sercom0/i2cm/intflag.rs new file mode 100644 index 000000000000..0fb0d2b9060c --- /dev/null +++ b/pac/atsamc21n/src/sercom0/i2cm/intflag.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MB` reader - Master On Bus Interrupt"] +pub struct MB_R(crate::FieldReader); +impl MB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MB` writer - Master On Bus Interrupt"] +pub struct MB_W<'a> { + w: &'a mut W, +} +impl<'a> MB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SB` reader - Slave On Bus Interrupt"] +pub struct SB_R(crate::FieldReader); +impl SB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SB` writer - Slave On Bus Interrupt"] +pub struct SB_W<'a> { + w: &'a mut W, +} +impl<'a> SB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Master On Bus Interrupt"] + #[inline(always)] + pub fn mb(&self) -> MB_R { + MB_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Slave On Bus Interrupt"] + #[inline(always)] + pub fn sb(&self) -> SB_R { + SB_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Master On Bus Interrupt"] + #[inline(always)] + pub fn mb(&mut self) -> MB_W { + MB_W { w: self } + } + #[doc = "Bit 1 - Slave On Bus Interrupt"] + #[inline(always)] + pub fn sb(&mut self) -> SB_W { + SB_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sercom0/i2cm/status.rs b/pac/atsamc21n/src/sercom0/i2cm/status.rs new file mode 100644 index 000000000000..95af23673ec4 --- /dev/null +++ b/pac/atsamc21n/src/sercom0/i2cm/status.rs @@ -0,0 +1,479 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BUSERR` reader - Bus Error"] +pub struct BUSERR_R(crate::FieldReader); +impl BUSERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSERR` writer - Bus Error"] +pub struct BUSERR_W<'a> { + w: &'a mut W, +} +impl<'a> BUSERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `ARBLOST` reader - Arbitration Lost"] +pub struct ARBLOST_R(crate::FieldReader); +impl ARBLOST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ARBLOST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ARBLOST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ARBLOST` writer - Arbitration Lost"] +pub struct ARBLOST_W<'a> { + w: &'a mut W, +} +impl<'a> ARBLOST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXNACK` reader - Received Not Acknowledge"] +pub struct RXNACK_R(crate::FieldReader); +impl RXNACK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXNACK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXNACK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXNACK` writer - Received Not Acknowledge"] +pub struct RXNACK_W<'a> { + w: &'a mut W, +} +impl<'a> RXNACK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `BUSSTATE` reader - Bus State"] +pub struct BUSSTATE_R(crate::FieldReader); +impl BUSSTATE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BUSSTATE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSSTATE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSSTATE` writer - Bus State"] +pub struct BUSSTATE_W<'a> { + w: &'a mut W, +} +impl<'a> BUSSTATE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u16 & 0x03) << 4); + self.w + } +} +#[doc = "Field `LOWTOUT` reader - SCL Low Timeout"] +pub struct LOWTOUT_R(crate::FieldReader); +impl LOWTOUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LOWTOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOWTOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LOWTOUT` writer - SCL Low Timeout"] +pub struct LOWTOUT_W<'a> { + w: &'a mut W, +} +impl<'a> LOWTOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `CLKHOLD` reader - Clock Hold"] +pub struct CLKHOLD_R(crate::FieldReader); +impl CLKHOLD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKHOLD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKHOLD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKHOLD` writer - Clock Hold"] +pub struct CLKHOLD_W<'a> { + w: &'a mut W, +} +impl<'a> CLKHOLD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `MEXTTOUT` reader - Master SCL Low Extend Timeout"] +pub struct MEXTTOUT_R(crate::FieldReader); +impl MEXTTOUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MEXTTOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MEXTTOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MEXTTOUT` writer - Master SCL Low Extend Timeout"] +pub struct MEXTTOUT_W<'a> { + w: &'a mut W, +} +impl<'a> MEXTTOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `SEXTTOUT` reader - Slave SCL Low Extend Timeout"] +pub struct SEXTTOUT_R(crate::FieldReader); +impl SEXTTOUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SEXTTOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEXTTOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEXTTOUT` writer - Slave SCL Low Extend Timeout"] +pub struct SEXTTOUT_W<'a> { + w: &'a mut W, +} +impl<'a> SEXTTOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `LENERR` reader - Length Error"] +pub struct LENERR_R(crate::FieldReader); +impl LENERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LENERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LENERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LENERR` writer - Length Error"] +pub struct LENERR_W<'a> { + w: &'a mut W, +} +impl<'a> LENERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u16 & 0x01) << 10); + self.w + } +} +impl R { + #[doc = "Bit 0 - Bus Error"] + #[inline(always)] + pub fn buserr(&self) -> BUSERR_R { + BUSERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Arbitration Lost"] + #[inline(always)] + pub fn arblost(&self) -> ARBLOST_R { + ARBLOST_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Received Not Acknowledge"] + #[inline(always)] + pub fn rxnack(&self) -> RXNACK_R { + RXNACK_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 4:5 - Bus State"] + #[inline(always)] + pub fn busstate(&self) -> BUSSTATE_R { + BUSSTATE_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bit 6 - SCL Low Timeout"] + #[inline(always)] + pub fn lowtout(&self) -> LOWTOUT_R { + LOWTOUT_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Clock Hold"] + #[inline(always)] + pub fn clkhold(&self) -> CLKHOLD_R { + CLKHOLD_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Master SCL Low Extend Timeout"] + #[inline(always)] + pub fn mexttout(&self) -> MEXTTOUT_R { + MEXTTOUT_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttout(&self) -> SEXTTOUT_R { + SEXTTOUT_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Length Error"] + #[inline(always)] + pub fn lenerr(&self) -> LENERR_R { + LENERR_R::new(((self.bits >> 10) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Bus Error"] + #[inline(always)] + pub fn buserr(&mut self) -> BUSERR_W { + BUSERR_W { w: self } + } + #[doc = "Bit 1 - Arbitration Lost"] + #[inline(always)] + pub fn arblost(&mut self) -> ARBLOST_W { + ARBLOST_W { w: self } + } + #[doc = "Bit 2 - Received Not Acknowledge"] + #[inline(always)] + pub fn rxnack(&mut self) -> RXNACK_W { + RXNACK_W { w: self } + } + #[doc = "Bits 4:5 - Bus State"] + #[inline(always)] + pub fn busstate(&mut self) -> BUSSTATE_W { + BUSSTATE_W { w: self } + } + #[doc = "Bit 6 - SCL Low Timeout"] + #[inline(always)] + pub fn lowtout(&mut self) -> LOWTOUT_W { + LOWTOUT_W { w: self } + } + #[doc = "Bit 7 - Clock Hold"] + #[inline(always)] + pub fn clkhold(&mut self) -> CLKHOLD_W { + CLKHOLD_W { w: self } + } + #[doc = "Bit 8 - Master SCL Low Extend Timeout"] + #[inline(always)] + pub fn mexttout(&mut self) -> MEXTTOUT_W { + MEXTTOUT_W { w: self } + } + #[doc = "Bit 9 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttout(&mut self) -> SEXTTOUT_W { + SEXTTOUT_W { w: self } + } + #[doc = "Bit 10 - Length Error"] + #[inline(always)] + pub fn lenerr(&mut self) -> LENERR_W { + LENERR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sercom0/i2cm/syncbusy.rs b/pac/atsamc21n/src/sercom0/i2cm/syncbusy.rs new file mode 100644 index 000000000000..87dd418d1cd3 --- /dev/null +++ b/pac/atsamc21n/src/sercom0/i2cm/syncbusy.rs @@ -0,0 +1,93 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - SERCOM Enable Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYSOP` reader - System Operation Synchronization Busy"] +pub struct SYSOP_R(crate::FieldReader); +impl SYSOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYSOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYSOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM Enable Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - System Operation Synchronization Busy"] + #[inline(always)] + pub fn sysop(&self) -> SYSOP_R { + SYSOP_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +#[doc = "I2CM Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sercom0/i2cs.rs b/pac/atsamc21n/src/sercom0/i2cs.rs new file mode 100644 index 000000000000..baf9513c6cc1 --- /dev/null +++ b/pac/atsamc21n/src/sercom0/i2cs.rs @@ -0,0 +1,36 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "I2CS Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "I2CS Control B"] +pub mod ctrlb; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "I2CS Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "I2CS Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "I2CS Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "I2CS Status"] +pub mod status; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "I2CS Synchronization Busy"] +pub mod syncbusy; +#[doc = "ADDR register accessor: an alias for `Reg`"] +pub type ADDR = crate::Reg; +#[doc = "I2CS Address"] +pub mod addr; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "I2CS Data"] +pub mod data; diff --git a/pac/atsamc21n/src/sercom0/i2cs/addr.rs b/pac/atsamc21n/src/sercom0/i2cs/addr.rs new file mode 100644 index 000000000000..c1b69ee22891 --- /dev/null +++ b/pac/atsamc21n/src/sercom0/i2cs/addr.rs @@ -0,0 +1,234 @@ +#[doc = "Register `ADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `GENCEN` reader - General Call Address Enable"] +pub struct GENCEN_R(crate::FieldReader); +impl GENCEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GENCEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GENCEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GENCEN` writer - General Call Address Enable"] +pub struct GENCEN_W<'a> { + w: &'a mut W, +} +impl<'a> GENCEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ADDR` reader - Address Value"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - Address Value"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03ff << 1)) | ((value as u32 & 0x03ff) << 1); + self.w + } +} +#[doc = "Field `TENBITEN` reader - Ten Bit Addressing Enable"] +pub struct TENBITEN_R(crate::FieldReader); +impl TENBITEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TENBITEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TENBITEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TENBITEN` writer - Ten Bit Addressing Enable"] +pub struct TENBITEN_W<'a> { + w: &'a mut W, +} +impl<'a> TENBITEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `ADDRMASK` reader - Address Mask"] +pub struct ADDRMASK_R(crate::FieldReader); +impl ADDRMASK_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + ADDRMASK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDRMASK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDRMASK` writer - Address Mask"] +pub struct ADDRMASK_W<'a> { + w: &'a mut W, +} +impl<'a> ADDRMASK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03ff << 17)) | ((value as u32 & 0x03ff) << 17); + self.w + } +} +impl R { + #[doc = "Bit 0 - General Call Address Enable"] + #[inline(always)] + pub fn gencen(&self) -> GENCEN_R { + GENCEN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bits 1:10 - Address Value"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new(((self.bits >> 1) & 0x03ff) as u16) + } + #[doc = "Bit 15 - Ten Bit Addressing Enable"] + #[inline(always)] + pub fn tenbiten(&self) -> TENBITEN_R { + TENBITEN_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 17:26 - Address Mask"] + #[inline(always)] + pub fn addrmask(&self) -> ADDRMASK_R { + ADDRMASK_R::new(((self.bits >> 17) & 0x03ff) as u16) + } +} +impl W { + #[doc = "Bit 0 - General Call Address Enable"] + #[inline(always)] + pub fn gencen(&mut self) -> GENCEN_W { + GENCEN_W { w: self } + } + #[doc = "Bits 1:10 - Address Value"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Bit 15 - Ten Bit Addressing Enable"] + #[inline(always)] + pub fn tenbiten(&mut self) -> TENBITEN_W { + TENBITEN_W { w: self } + } + #[doc = "Bits 17:26 - Address Mask"] + #[inline(always)] + pub fn addrmask(&mut self) -> ADDRMASK_W { + ADDRMASK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [addr](index.html) module"] +pub struct ADDR_SPEC; +impl crate::RegisterSpec for ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [addr::R](R) reader structure"] +impl crate::Readable for ADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [addr::W](W) writer structure"] +impl crate::Writable for ADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ADDR to value 0"] +impl crate::Resettable for ADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sercom0/i2cs/ctrla.rs b/pac/atsamc21n/src/sercom0/i2cs/ctrla.rs new file mode 100644 index 000000000000..ec93812b004f --- /dev/null +++ b/pac/atsamc21n/src/sercom0/i2cs/ctrla.rs @@ -0,0 +1,744 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: USART with external clock"] + USART_EXT_CLK = 0, + #[doc = "1: USART with internal clock"] + USART_INT_CLK = 1, + #[doc = "2: SPI in slave operation"] + SPI_SLAVE = 2, + #[doc = "3: SPI in master operation"] + SPI_MASTER = 3, + #[doc = "4: I2C slave operation"] + I2C_SLAVE = 4, + #[doc = "5: I2C master operation"] + I2C_MASTER = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::USART_EXT_CLK), + 1 => Some(MODE_A::USART_INT_CLK), + 2 => Some(MODE_A::SPI_SLAVE), + 3 => Some(MODE_A::SPI_MASTER), + 4 => Some(MODE_A::I2C_SLAVE), + 5 => Some(MODE_A::I2C_MASTER), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_EXT_CLK`"] + #[inline(always)] + pub fn is_usart_ext_clk(&self) -> bool { + **self == MODE_A::USART_EXT_CLK + } + #[doc = "Checks if the value of the field is `USART_INT_CLK`"] + #[inline(always)] + pub fn is_usart_int_clk(&self) -> bool { + **self == MODE_A::USART_INT_CLK + } + #[doc = "Checks if the value of the field is `SPI_SLAVE`"] + #[inline(always)] + pub fn is_spi_slave(&self) -> bool { + **self == MODE_A::SPI_SLAVE + } + #[doc = "Checks if the value of the field is `SPI_MASTER`"] + #[inline(always)] + pub fn is_spi_master(&self) -> bool { + **self == MODE_A::SPI_MASTER + } + #[doc = "Checks if the value of the field is `I2C_SLAVE`"] + #[inline(always)] + pub fn is_i2c_slave(&self) -> bool { + **self == MODE_A::I2C_SLAVE + } + #[doc = "Checks if the value of the field is `I2C_MASTER`"] + #[inline(always)] + pub fn is_i2c_master(&self) -> bool { + **self == MODE_A::I2C_MASTER + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART with external clock"] + #[inline(always)] + pub fn usart_ext_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_EXT_CLK) + } + #[doc = "USART with internal clock"] + #[inline(always)] + pub fn usart_int_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_INT_CLK) + } + #[doc = "SPI in slave operation"] + #[inline(always)] + pub fn spi_slave(self) -> &'a mut W { + self.variant(MODE_A::SPI_SLAVE) + } + #[doc = "SPI in master operation"] + #[inline(always)] + pub fn spi_master(self) -> &'a mut W { + self.variant(MODE_A::SPI_MASTER) + } + #[doc = "I2C slave operation"] + #[inline(always)] + pub fn i2c_slave(self) -> &'a mut W { + self.variant(MODE_A::I2C_SLAVE) + } + #[doc = "I2C master operation"] + #[inline(always)] + pub fn i2c_master(self) -> &'a mut W { + self.variant(MODE_A::I2C_MASTER) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 2)) | ((value as u32 & 0x07) << 2); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `PINOUT` reader - Pin Usage"] +pub struct PINOUT_R(crate::FieldReader); +impl PINOUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PINOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PINOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PINOUT` writer - Pin Usage"] +pub struct PINOUT_W<'a> { + w: &'a mut W, +} +impl<'a> PINOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "SDA Hold Time\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SDAHOLD_A { + #[doc = "0: Disabled"] + DISABLE = 0, + #[doc = "1: 50-100ns hold time"] + _75NS = 1, + #[doc = "2: 300-600ns hold time"] + _450NS = 2, + #[doc = "3: 400-800ns hold time"] + _600NS = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SDAHOLD_A) -> Self { + variant as _ + } +} +#[doc = "Field `SDAHOLD` reader - SDA Hold Time"] +pub struct SDAHOLD_R(crate::FieldReader); +impl SDAHOLD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SDAHOLD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SDAHOLD_A { + match self.bits { + 0 => SDAHOLD_A::DISABLE, + 1 => SDAHOLD_A::_75NS, + 2 => SDAHOLD_A::_450NS, + 3 => SDAHOLD_A::_600NS, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == SDAHOLD_A::DISABLE + } + #[doc = "Checks if the value of the field is `_75NS`"] + #[inline(always)] + pub fn is_75ns(&self) -> bool { + **self == SDAHOLD_A::_75NS + } + #[doc = "Checks if the value of the field is `_450NS`"] + #[inline(always)] + pub fn is_450ns(&self) -> bool { + **self == SDAHOLD_A::_450NS + } + #[doc = "Checks if the value of the field is `_600NS`"] + #[inline(always)] + pub fn is_600ns(&self) -> bool { + **self == SDAHOLD_A::_600NS + } +} +impl core::ops::Deref for SDAHOLD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SDAHOLD` writer - SDA Hold Time"] +pub struct SDAHOLD_W<'a> { + w: &'a mut W, +} +impl<'a> SDAHOLD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SDAHOLD_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(SDAHOLD_A::DISABLE) + } + #[doc = "50-100ns hold time"] + #[inline(always)] + pub fn _75ns(self) -> &'a mut W { + self.variant(SDAHOLD_A::_75NS) + } + #[doc = "300-600ns hold time"] + #[inline(always)] + pub fn _450ns(self) -> &'a mut W { + self.variant(SDAHOLD_A::_450NS) + } + #[doc = "400-800ns hold time"] + #[inline(always)] + pub fn _600ns(self) -> &'a mut W { + self.variant(SDAHOLD_A::_600NS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 20)) | ((value as u32 & 0x03) << 20); + self.w + } +} +#[doc = "Field `SEXTTOEN` reader - Slave SCL Low Extend Timeout"] +pub struct SEXTTOEN_R(crate::FieldReader); +impl SEXTTOEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SEXTTOEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEXTTOEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEXTTOEN` writer - Slave SCL Low Extend Timeout"] +pub struct SEXTTOEN_W<'a> { + w: &'a mut W, +} +impl<'a> SEXTTOEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Transfer Speed\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SPEED_A { + #[doc = "0: Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz"] + STANDARD_AND_FAST_MODE = 0, + #[doc = "1: Fast-mode Plus Upto 1MHz"] + FASTPLUS_MODE = 1, + #[doc = "2: High-speed mode Upto 3.4MHz"] + HIGH_SPEED_MODE = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SPEED_A) -> Self { + variant as _ + } +} +#[doc = "Field `SPEED` reader - Transfer Speed"] +pub struct SPEED_R(crate::FieldReader); +impl SPEED_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SPEED_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SPEED_A::STANDARD_AND_FAST_MODE), + 1 => Some(SPEED_A::FASTPLUS_MODE), + 2 => Some(SPEED_A::HIGH_SPEED_MODE), + _ => None, + } + } + #[doc = "Checks if the value of the field is `STANDARD_AND_FAST_MODE`"] + #[inline(always)] + pub fn is_standard_and_fast_mode(&self) -> bool { + **self == SPEED_A::STANDARD_AND_FAST_MODE + } + #[doc = "Checks if the value of the field is `FASTPLUS_MODE`"] + #[inline(always)] + pub fn is_fastplus_mode(&self) -> bool { + **self == SPEED_A::FASTPLUS_MODE + } + #[doc = "Checks if the value of the field is `HIGH_SPEED_MODE`"] + #[inline(always)] + pub fn is_high_speed_mode(&self) -> bool { + **self == SPEED_A::HIGH_SPEED_MODE + } +} +impl core::ops::Deref for SPEED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SPEED` writer - Transfer Speed"] +pub struct SPEED_W<'a> { + w: &'a mut W, +} +impl<'a> SPEED_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SPEED_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz"] + #[inline(always)] + pub fn standard_and_fast_mode(self) -> &'a mut W { + self.variant(SPEED_A::STANDARD_AND_FAST_MODE) + } + #[doc = "Fast-mode Plus Upto 1MHz"] + #[inline(always)] + pub fn fastplus_mode(self) -> &'a mut W { + self.variant(SPEED_A::FASTPLUS_MODE) + } + #[doc = "High-speed mode Upto 3.4MHz"] + #[inline(always)] + pub fn high_speed_mode(self) -> &'a mut W { + self.variant(SPEED_A::HIGH_SPEED_MODE) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 24)) | ((value as u32 & 0x03) << 24); + self.w + } +} +#[doc = "Field `SCLSM` reader - SCL Clock Stretch Mode"] +pub struct SCLSM_R(crate::FieldReader); +impl SCLSM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SCLSM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SCLSM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SCLSM` writer - SCL Clock Stretch Mode"] +pub struct SCLSM_W<'a> { + w: &'a mut W, +} +impl<'a> SCLSM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +#[doc = "Field `LOWTOUTEN` reader - SCL Low Timeout Enable"] +pub struct LOWTOUTEN_R(crate::FieldReader); +impl LOWTOUTEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LOWTOUTEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOWTOUTEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LOWTOUTEN` writer - SCL Low Timeout Enable"] +pub struct LOWTOUTEN_W<'a> { + w: &'a mut W, +} +impl<'a> LOWTOUTEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x07) as u8) + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 16 - Pin Usage"] + #[inline(always)] + pub fn pinout(&self) -> PINOUT_R { + PINOUT_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bits 20:21 - SDA Hold Time"] + #[inline(always)] + pub fn sdahold(&self) -> SDAHOLD_R { + SDAHOLD_R::new(((self.bits >> 20) & 0x03) as u8) + } + #[doc = "Bit 23 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttoen(&self) -> SEXTTOEN_R { + SEXTTOEN_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bits 24:25 - Transfer Speed"] + #[inline(always)] + pub fn speed(&self) -> SPEED_R { + SPEED_R::new(((self.bits >> 24) & 0x03) as u8) + } + #[doc = "Bit 27 - SCL Clock Stretch Mode"] + #[inline(always)] + pub fn sclsm(&self) -> SCLSM_R { + SCLSM_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 30 - SCL Low Timeout Enable"] + #[inline(always)] + pub fn lowtouten(&self) -> LOWTOUTEN_R { + LOWTOUTEN_R::new(((self.bits >> 30) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 16 - Pin Usage"] + #[inline(always)] + pub fn pinout(&mut self) -> PINOUT_W { + PINOUT_W { w: self } + } + #[doc = "Bits 20:21 - SDA Hold Time"] + #[inline(always)] + pub fn sdahold(&mut self) -> SDAHOLD_W { + SDAHOLD_W { w: self } + } + #[doc = "Bit 23 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttoen(&mut self) -> SEXTTOEN_W { + SEXTTOEN_W { w: self } + } + #[doc = "Bits 24:25 - Transfer Speed"] + #[inline(always)] + pub fn speed(&mut self) -> SPEED_W { + SPEED_W { w: self } + } + #[doc = "Bit 27 - SCL Clock Stretch Mode"] + #[inline(always)] + pub fn sclsm(&mut self) -> SCLSM_W { + SCLSM_W { w: self } + } + #[doc = "Bit 30 - SCL Low Timeout Enable"] + #[inline(always)] + pub fn lowtouten(&mut self) -> LOWTOUTEN_W { + LOWTOUTEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sercom0/i2cs/ctrlb.rs b/pac/atsamc21n/src/sercom0/i2cs/ctrlb.rs new file mode 100644 index 000000000000..b20f48581ed5 --- /dev/null +++ b/pac/atsamc21n/src/sercom0/i2cs/ctrlb.rs @@ -0,0 +1,328 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SMEN` reader - Smart Mode Enable"] +pub struct SMEN_R(crate::FieldReader); +impl SMEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SMEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SMEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SMEN` writer - Smart Mode Enable"] +pub struct SMEN_W<'a> { + w: &'a mut W, +} +impl<'a> SMEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `GCMD` reader - PMBus Group Command"] +pub struct GCMD_R(crate::FieldReader); +impl GCMD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GCMD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GCMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GCMD` writer - PMBus Group Command"] +pub struct GCMD_W<'a> { + w: &'a mut W, +} +impl<'a> GCMD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `AACKEN` reader - Automatic Address Acknowledge"] +pub struct AACKEN_R(crate::FieldReader); +impl AACKEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AACKEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AACKEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AACKEN` writer - Automatic Address Acknowledge"] +pub struct AACKEN_W<'a> { + w: &'a mut W, +} +impl<'a> AACKEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `AMODE` reader - Address Mode"] +pub struct AMODE_R(crate::FieldReader); +impl AMODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + AMODE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AMODE` writer - Address Mode"] +pub struct AMODE_W<'a> { + w: &'a mut W, +} +impl<'a> AMODE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 14)) | ((value as u32 & 0x03) << 14); + self.w + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Field `ACKACT` reader - Acknowledge Action"] +pub struct ACKACT_R(crate::FieldReader); +impl ACKACT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ACKACT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ACKACT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ACKACT` writer - Acknowledge Action"] +pub struct ACKACT_W<'a> { + w: &'a mut W, +} +impl<'a> ACKACT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +impl R { + #[doc = "Bit 8 - Smart Mode Enable"] + #[inline(always)] + pub fn smen(&self) -> SMEN_R { + SMEN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - PMBus Group Command"] + #[inline(always)] + pub fn gcmd(&self) -> GCMD_R { + GCMD_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Automatic Address Acknowledge"] + #[inline(always)] + pub fn aacken(&self) -> AACKEN_R { + AACKEN_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bits 14:15 - Address Mode"] + #[inline(always)] + pub fn amode(&self) -> AMODE_R { + AMODE_R::new(((self.bits >> 14) & 0x03) as u8) + } + #[doc = "Bits 16:17 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bit 18 - Acknowledge Action"] + #[inline(always)] + pub fn ackact(&self) -> ACKACT_R { + ACKACT_R::new(((self.bits >> 18) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 8 - Smart Mode Enable"] + #[inline(always)] + pub fn smen(&mut self) -> SMEN_W { + SMEN_W { w: self } + } + #[doc = "Bit 9 - PMBus Group Command"] + #[inline(always)] + pub fn gcmd(&mut self) -> GCMD_W { + GCMD_W { w: self } + } + #[doc = "Bit 10 - Automatic Address Acknowledge"] + #[inline(always)] + pub fn aacken(&mut self) -> AACKEN_W { + AACKEN_W { w: self } + } + #[doc = "Bits 14:15 - Address Mode"] + #[inline(always)] + pub fn amode(&mut self) -> AMODE_W { + AMODE_W { w: self } + } + #[doc = "Bits 16:17 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Bit 18 - Acknowledge Action"] + #[inline(always)] + pub fn ackact(&mut self) -> ACKACT_W { + ACKACT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sercom0/i2cs/data.rs b/pac/atsamc21n/src/sercom0/i2cs/data.rs new file mode 100644 index 000000000000..d8bfe070431a --- /dev/null +++ b/pac/atsamc21n/src/sercom0/i2cs/data.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data Value"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data Value"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Data Value"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Value"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sercom0/i2cs/intenclr.rs b/pac/atsamc21n/src/sercom0/i2cs/intenclr.rs new file mode 100644 index 000000000000..49f5191c8d63 --- /dev/null +++ b/pac/atsamc21n/src/sercom0/i2cs/intenclr.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PREC` reader - Stop Received Interrupt Disable"] +pub struct PREC_R(crate::FieldReader); +impl PREC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PREC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PREC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PREC` writer - Stop Received Interrupt Disable"] +pub struct PREC_W<'a> { + w: &'a mut W, +} +impl<'a> PREC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `AMATCH` reader - Address Match Interrupt Disable"] +pub struct AMATCH_R(crate::FieldReader); +impl AMATCH_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AMATCH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AMATCH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AMATCH` writer - Address Match Interrupt Disable"] +pub struct AMATCH_W<'a> { + w: &'a mut W, +} +impl<'a> AMATCH_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `DRDY` reader - Data Interrupt Disable"] +pub struct DRDY_R(crate::FieldReader); +impl DRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRDY` writer - Data Interrupt Disable"] +pub struct DRDY_W<'a> { + w: &'a mut W, +} +impl<'a> DRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Disable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Disable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Stop Received Interrupt Disable"] + #[inline(always)] + pub fn prec(&self) -> PREC_R { + PREC_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Address Match Interrupt Disable"] + #[inline(always)] + pub fn amatch(&self) -> AMATCH_R { + AMATCH_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Data Interrupt Disable"] + #[inline(always)] + pub fn drdy(&self) -> DRDY_R { + DRDY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Stop Received Interrupt Disable"] + #[inline(always)] + pub fn prec(&mut self) -> PREC_W { + PREC_W { w: self } + } + #[doc = "Bit 1 - Address Match Interrupt Disable"] + #[inline(always)] + pub fn amatch(&mut self) -> AMATCH_W { + AMATCH_W { w: self } + } + #[doc = "Bit 2 - Data Interrupt Disable"] + #[inline(always)] + pub fn drdy(&mut self) -> DRDY_W { + DRDY_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sercom0/i2cs/intenset.rs b/pac/atsamc21n/src/sercom0/i2cs/intenset.rs new file mode 100644 index 000000000000..97ea784d7476 --- /dev/null +++ b/pac/atsamc21n/src/sercom0/i2cs/intenset.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PREC` reader - Stop Received Interrupt Enable"] +pub struct PREC_R(crate::FieldReader); +impl PREC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PREC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PREC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PREC` writer - Stop Received Interrupt Enable"] +pub struct PREC_W<'a> { + w: &'a mut W, +} +impl<'a> PREC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `AMATCH` reader - Address Match Interrupt Enable"] +pub struct AMATCH_R(crate::FieldReader); +impl AMATCH_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AMATCH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AMATCH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AMATCH` writer - Address Match Interrupt Enable"] +pub struct AMATCH_W<'a> { + w: &'a mut W, +} +impl<'a> AMATCH_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `DRDY` reader - Data Interrupt Enable"] +pub struct DRDY_R(crate::FieldReader); +impl DRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRDY` writer - Data Interrupt Enable"] +pub struct DRDY_W<'a> { + w: &'a mut W, +} +impl<'a> DRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Stop Received Interrupt Enable"] + #[inline(always)] + pub fn prec(&self) -> PREC_R { + PREC_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Address Match Interrupt Enable"] + #[inline(always)] + pub fn amatch(&self) -> AMATCH_R { + AMATCH_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Data Interrupt Enable"] + #[inline(always)] + pub fn drdy(&self) -> DRDY_R { + DRDY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Stop Received Interrupt Enable"] + #[inline(always)] + pub fn prec(&mut self) -> PREC_W { + PREC_W { w: self } + } + #[doc = "Bit 1 - Address Match Interrupt Enable"] + #[inline(always)] + pub fn amatch(&mut self) -> AMATCH_W { + AMATCH_W { w: self } + } + #[doc = "Bit 2 - Data Interrupt Enable"] + #[inline(always)] + pub fn drdy(&mut self) -> DRDY_W { + DRDY_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sercom0/i2cs/intflag.rs b/pac/atsamc21n/src/sercom0/i2cs/intflag.rs new file mode 100644 index 000000000000..2eee333e4e59 --- /dev/null +++ b/pac/atsamc21n/src/sercom0/i2cs/intflag.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PREC` reader - Stop Received Interrupt"] +pub struct PREC_R(crate::FieldReader); +impl PREC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PREC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PREC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PREC` writer - Stop Received Interrupt"] +pub struct PREC_W<'a> { + w: &'a mut W, +} +impl<'a> PREC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `AMATCH` reader - Address Match Interrupt"] +pub struct AMATCH_R(crate::FieldReader); +impl AMATCH_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AMATCH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AMATCH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AMATCH` writer - Address Match Interrupt"] +pub struct AMATCH_W<'a> { + w: &'a mut W, +} +impl<'a> AMATCH_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `DRDY` reader - Data Interrupt"] +pub struct DRDY_R(crate::FieldReader); +impl DRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRDY` writer - Data Interrupt"] +pub struct DRDY_W<'a> { + w: &'a mut W, +} +impl<'a> DRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Stop Received Interrupt"] + #[inline(always)] + pub fn prec(&self) -> PREC_R { + PREC_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Address Match Interrupt"] + #[inline(always)] + pub fn amatch(&self) -> AMATCH_R { + AMATCH_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Data Interrupt"] + #[inline(always)] + pub fn drdy(&self) -> DRDY_R { + DRDY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Stop Received Interrupt"] + #[inline(always)] + pub fn prec(&mut self) -> PREC_W { + PREC_W { w: self } + } + #[doc = "Bit 1 - Address Match Interrupt"] + #[inline(always)] + pub fn amatch(&mut self) -> AMATCH_W { + AMATCH_W { w: self } + } + #[doc = "Bit 2 - Data Interrupt"] + #[inline(always)] + pub fn drdy(&mut self) -> DRDY_W { + DRDY_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sercom0/i2cs/status.rs b/pac/atsamc21n/src/sercom0/i2cs/status.rs new file mode 100644 index 000000000000..b3f6d218fa66 --- /dev/null +++ b/pac/atsamc21n/src/sercom0/i2cs/status.rs @@ -0,0 +1,489 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BUSERR` reader - Bus Error"] +pub struct BUSERR_R(crate::FieldReader); +impl BUSERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSERR` writer - Bus Error"] +pub struct BUSERR_W<'a> { + w: &'a mut W, +} +impl<'a> BUSERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `COLL` reader - Transmit Collision"] +pub struct COLL_R(crate::FieldReader); +impl COLL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COLL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COLL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COLL` writer - Transmit Collision"] +pub struct COLL_W<'a> { + w: &'a mut W, +} +impl<'a> COLL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXNACK` reader - Received Not Acknowledge"] +pub struct RXNACK_R(crate::FieldReader); +impl RXNACK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXNACK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXNACK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXNACK` writer - Received Not Acknowledge"] +pub struct RXNACK_W<'a> { + w: &'a mut W, +} +impl<'a> RXNACK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `DIR` reader - Read/Write Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Read/Write Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `SR` reader - Repeated Start"] +pub struct SR_R(crate::FieldReader); +impl SR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SR` writer - Repeated Start"] +pub struct SR_W<'a> { + w: &'a mut W, +} +impl<'a> SR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `LOWTOUT` reader - SCL Low Timeout"] +pub struct LOWTOUT_R(crate::FieldReader); +impl LOWTOUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LOWTOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOWTOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LOWTOUT` writer - SCL Low Timeout"] +pub struct LOWTOUT_W<'a> { + w: &'a mut W, +} +impl<'a> LOWTOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `CLKHOLD` reader - Clock Hold"] +pub struct CLKHOLD_R(crate::FieldReader); +impl CLKHOLD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKHOLD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKHOLD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKHOLD` writer - Clock Hold"] +pub struct CLKHOLD_W<'a> { + w: &'a mut W, +} +impl<'a> CLKHOLD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `SEXTTOUT` reader - Slave SCL Low Extend Timeout"] +pub struct SEXTTOUT_R(crate::FieldReader); +impl SEXTTOUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SEXTTOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEXTTOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEXTTOUT` writer - Slave SCL Low Extend Timeout"] +pub struct SEXTTOUT_W<'a> { + w: &'a mut W, +} +impl<'a> SEXTTOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `HS` reader - High Speed"] +pub struct HS_R(crate::FieldReader); +impl HS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HS` writer - High Speed"] +pub struct HS_W<'a> { + w: &'a mut W, +} +impl<'a> HS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u16 & 0x01) << 10); + self.w + } +} +impl R { + #[doc = "Bit 0 - Bus Error"] + #[inline(always)] + pub fn buserr(&self) -> BUSERR_R { + BUSERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Collision"] + #[inline(always)] + pub fn coll(&self) -> COLL_R { + COLL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Received Not Acknowledge"] + #[inline(always)] + pub fn rxnack(&self) -> RXNACK_R { + RXNACK_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Read/Write Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Repeated Start"] + #[inline(always)] + pub fn sr(&self) -> SR_R { + SR_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 6 - SCL Low Timeout"] + #[inline(always)] + pub fn lowtout(&self) -> LOWTOUT_R { + LOWTOUT_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Clock Hold"] + #[inline(always)] + pub fn clkhold(&self) -> CLKHOLD_R { + CLKHOLD_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 9 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttout(&self) -> SEXTTOUT_R { + SEXTTOUT_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - High Speed"] + #[inline(always)] + pub fn hs(&self) -> HS_R { + HS_R::new(((self.bits >> 10) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Bus Error"] + #[inline(always)] + pub fn buserr(&mut self) -> BUSERR_W { + BUSERR_W { w: self } + } + #[doc = "Bit 1 - Transmit Collision"] + #[inline(always)] + pub fn coll(&mut self) -> COLL_W { + COLL_W { w: self } + } + #[doc = "Bit 2 - Received Not Acknowledge"] + #[inline(always)] + pub fn rxnack(&mut self) -> RXNACK_W { + RXNACK_W { w: self } + } + #[doc = "Bit 3 - Read/Write Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 4 - Repeated Start"] + #[inline(always)] + pub fn sr(&mut self) -> SR_W { + SR_W { w: self } + } + #[doc = "Bit 6 - SCL Low Timeout"] + #[inline(always)] + pub fn lowtout(&mut self) -> LOWTOUT_W { + LOWTOUT_W { w: self } + } + #[doc = "Bit 7 - Clock Hold"] + #[inline(always)] + pub fn clkhold(&mut self) -> CLKHOLD_W { + CLKHOLD_W { w: self } + } + #[doc = "Bit 9 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttout(&mut self) -> SEXTTOUT_W { + SEXTTOUT_W { w: self } + } + #[doc = "Bit 10 - High Speed"] + #[inline(always)] + pub fn hs(&mut self) -> HS_W { + HS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sercom0/i2cs/syncbusy.rs b/pac/atsamc21n/src/sercom0/i2cs/syncbusy.rs new file mode 100644 index 000000000000..38e2509d9666 --- /dev/null +++ b/pac/atsamc21n/src/sercom0/i2cs/syncbusy.rs @@ -0,0 +1,73 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - SERCOM Enable Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM Enable Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +#[doc = "I2CS Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sercom0/spim.rs b/pac/atsamc21n/src/sercom0/spim.rs new file mode 100644 index 000000000000..528e38e1b811 --- /dev/null +++ b/pac/atsamc21n/src/sercom0/spim.rs @@ -0,0 +1,44 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "SPIM Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "SPIM Control B"] +pub mod ctrlb; +#[doc = "BAUD register accessor: an alias for `Reg`"] +pub type BAUD = crate::Reg; +#[doc = "SPIM Baud Rate"] +pub mod baud; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "SPIM Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "SPIM Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "SPIM Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "SPIM Status"] +pub mod status; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "SPIM Synchronization Busy"] +pub mod syncbusy; +#[doc = "ADDR register accessor: an alias for `Reg`"] +pub type ADDR = crate::Reg; +#[doc = "SPIM Address"] +pub mod addr; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "SPIM Data"] +pub mod data; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "SPIM Debug Control"] +pub mod dbgctrl; diff --git a/pac/atsamc21n/src/sercom0/spim/addr.rs b/pac/atsamc21n/src/sercom0/spim/addr.rs new file mode 100644 index 000000000000..7c25cd522ea2 --- /dev/null +++ b/pac/atsamc21n/src/sercom0/spim/addr.rs @@ -0,0 +1,140 @@ +#[doc = "Register `ADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ADDR` reader - Address Value"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - Address Value"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +#[doc = "Field `ADDRMASK` reader - Address Mask"] +pub struct ADDRMASK_R(crate::FieldReader); +impl ADDRMASK_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ADDRMASK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDRMASK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDRMASK` writer - Address Mask"] +pub struct ADDRMASK_W<'a> { + w: &'a mut W, +} +impl<'a> ADDRMASK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Address Value"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 16:23 - Address Mask"] + #[inline(always)] + pub fn addrmask(&self) -> ADDRMASK_R { + ADDRMASK_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Address Value"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Bits 16:23 - Address Mask"] + #[inline(always)] + pub fn addrmask(&mut self) -> ADDRMASK_W { + ADDRMASK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [addr](index.html) module"] +pub struct ADDR_SPEC; +impl crate::RegisterSpec for ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [addr::R](R) reader structure"] +impl crate::Readable for ADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [addr::W](W) writer structure"] +impl crate::Writable for ADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ADDR to value 0"] +impl crate::Resettable for ADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sercom0/spim/baud.rs b/pac/atsamc21n/src/sercom0/spim/baud.rs new file mode 100644 index 000000000000..6bec9ca74355 --- /dev/null +++ b/pac/atsamc21n/src/sercom0/spim/baud.rs @@ -0,0 +1,103 @@ +#[doc = "Register `BAUD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud](index.html) module"] +pub struct BAUD_SPEC; +impl crate::RegisterSpec for BAUD_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [baud::R](R) reader structure"] +impl crate::Readable for BAUD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud::W](W) writer structure"] +impl crate::Writable for BAUD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD to value 0"] +impl crate::Resettable for BAUD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sercom0/spim/ctrla.rs b/pac/atsamc21n/src/sercom0/spim/ctrla.rs new file mode 100644 index 000000000000..44028f8cbdd7 --- /dev/null +++ b/pac/atsamc21n/src/sercom0/spim/ctrla.rs @@ -0,0 +1,992 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: USART with external clock"] + USART_EXT_CLK = 0, + #[doc = "1: USART with internal clock"] + USART_INT_CLK = 1, + #[doc = "2: SPI in slave operation"] + SPI_SLAVE = 2, + #[doc = "3: SPI in master operation"] + SPI_MASTER = 3, + #[doc = "4: I2C slave operation"] + I2C_SLAVE = 4, + #[doc = "5: I2C master operation"] + I2C_MASTER = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::USART_EXT_CLK), + 1 => Some(MODE_A::USART_INT_CLK), + 2 => Some(MODE_A::SPI_SLAVE), + 3 => Some(MODE_A::SPI_MASTER), + 4 => Some(MODE_A::I2C_SLAVE), + 5 => Some(MODE_A::I2C_MASTER), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_EXT_CLK`"] + #[inline(always)] + pub fn is_usart_ext_clk(&self) -> bool { + **self == MODE_A::USART_EXT_CLK + } + #[doc = "Checks if the value of the field is `USART_INT_CLK`"] + #[inline(always)] + pub fn is_usart_int_clk(&self) -> bool { + **self == MODE_A::USART_INT_CLK + } + #[doc = "Checks if the value of the field is `SPI_SLAVE`"] + #[inline(always)] + pub fn is_spi_slave(&self) -> bool { + **self == MODE_A::SPI_SLAVE + } + #[doc = "Checks if the value of the field is `SPI_MASTER`"] + #[inline(always)] + pub fn is_spi_master(&self) -> bool { + **self == MODE_A::SPI_MASTER + } + #[doc = "Checks if the value of the field is `I2C_SLAVE`"] + #[inline(always)] + pub fn is_i2c_slave(&self) -> bool { + **self == MODE_A::I2C_SLAVE + } + #[doc = "Checks if the value of the field is `I2C_MASTER`"] + #[inline(always)] + pub fn is_i2c_master(&self) -> bool { + **self == MODE_A::I2C_MASTER + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART with external clock"] + #[inline(always)] + pub fn usart_ext_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_EXT_CLK) + } + #[doc = "USART with internal clock"] + #[inline(always)] + pub fn usart_int_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_INT_CLK) + } + #[doc = "SPI in slave operation"] + #[inline(always)] + pub fn spi_slave(self) -> &'a mut W { + self.variant(MODE_A::SPI_SLAVE) + } + #[doc = "SPI in master operation"] + #[inline(always)] + pub fn spi_master(self) -> &'a mut W { + self.variant(MODE_A::SPI_MASTER) + } + #[doc = "I2C slave operation"] + #[inline(always)] + pub fn i2c_slave(self) -> &'a mut W { + self.variant(MODE_A::I2C_SLAVE) + } + #[doc = "I2C master operation"] + #[inline(always)] + pub fn i2c_master(self) -> &'a mut W { + self.variant(MODE_A::I2C_MASTER) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 2)) | ((value as u32 & 0x07) << 2); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `IBON` reader - Immediate Buffer Overflow Notification"] +pub struct IBON_R(crate::FieldReader); +impl IBON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IBON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IBON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IBON` writer - Immediate Buffer Overflow Notification"] +pub struct IBON_W<'a> { + w: &'a mut W, +} +impl<'a> IBON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Data Out Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DOPO_A { + #[doc = "0: DO on PAD\\[0\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + PAD0 = 0, + #[doc = "1: DO on PAD\\[2\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + PAD1 = 1, + #[doc = "2: DO on PAD\\[3\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + PAD2 = 2, + #[doc = "3: DO on PAD\\[0\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + PAD3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DOPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `DOPO` reader - Data Out Pinout"] +pub struct DOPO_R(crate::FieldReader); +impl DOPO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DOPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DOPO_A { + match self.bits { + 0 => DOPO_A::PAD0, + 1 => DOPO_A::PAD1, + 2 => DOPO_A::PAD2, + 3 => DOPO_A::PAD3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == DOPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD1`"] + #[inline(always)] + pub fn is_pad1(&self) -> bool { + **self == DOPO_A::PAD1 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == DOPO_A::PAD2 + } + #[doc = "Checks if the value of the field is `PAD3`"] + #[inline(always)] + pub fn is_pad3(&self) -> bool { + **self == DOPO_A::PAD3 + } +} +impl core::ops::Deref for DOPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DOPO` writer - Data Out Pinout"] +pub struct DOPO_W<'a> { + w: &'a mut W, +} +impl<'a> DOPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DOPO_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "DO on PAD\\[0\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(DOPO_A::PAD0) + } + #[doc = "DO on PAD\\[2\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + #[inline(always)] + pub fn pad1(self) -> &'a mut W { + self.variant(DOPO_A::PAD1) + } + #[doc = "DO on PAD\\[3\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(DOPO_A::PAD2) + } + #[doc = "DO on PAD\\[0\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + #[inline(always)] + pub fn pad3(self) -> &'a mut W { + self.variant(DOPO_A::PAD3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Data In Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DIPO_A { + #[doc = "0: SERCOM PAD\\[0\\]"] + PAD0 = 0, + #[doc = "1: SERCOM PAD\\[1\\]"] + PAD1 = 1, + #[doc = "2: SERCOM PAD\\[2\\]"] + PAD2 = 2, + #[doc = "3: SERCOM PAD\\[3\\]"] + PAD3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DIPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `DIPO` reader - Data In Pinout"] +pub struct DIPO_R(crate::FieldReader); +impl DIPO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DIPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DIPO_A { + match self.bits { + 0 => DIPO_A::PAD0, + 1 => DIPO_A::PAD1, + 2 => DIPO_A::PAD2, + 3 => DIPO_A::PAD3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == DIPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD1`"] + #[inline(always)] + pub fn is_pad1(&self) -> bool { + **self == DIPO_A::PAD1 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == DIPO_A::PAD2 + } + #[doc = "Checks if the value of the field is `PAD3`"] + #[inline(always)] + pub fn is_pad3(&self) -> bool { + **self == DIPO_A::PAD3 + } +} +impl core::ops::Deref for DIPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIPO` writer - Data In Pinout"] +pub struct DIPO_W<'a> { + w: &'a mut W, +} +impl<'a> DIPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DIPO_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "SERCOM PAD\\[0\\]"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(DIPO_A::PAD0) + } + #[doc = "SERCOM PAD\\[1\\]"] + #[inline(always)] + pub fn pad1(self) -> &'a mut W { + self.variant(DIPO_A::PAD1) + } + #[doc = "SERCOM PAD\\[2\\]"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(DIPO_A::PAD2) + } + #[doc = "SERCOM PAD\\[3\\]"] + #[inline(always)] + pub fn pad3(self) -> &'a mut W { + self.variant(DIPO_A::PAD3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 20)) | ((value as u32 & 0x03) << 20); + self.w + } +} +#[doc = "Frame Format\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FORM_A { + #[doc = "0: SPI Frame"] + SPI_FRAME = 0, + #[doc = "2: SPI Frame with Addr"] + SPI_FRAME_WITH_ADDR = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FORM_A) -> Self { + variant as _ + } +} +#[doc = "Field `FORM` reader - Frame Format"] +pub struct FORM_R(crate::FieldReader); +impl FORM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FORM_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(FORM_A::SPI_FRAME), + 2 => Some(FORM_A::SPI_FRAME_WITH_ADDR), + _ => None, + } + } + #[doc = "Checks if the value of the field is `SPI_FRAME`"] + #[inline(always)] + pub fn is_spi_frame(&self) -> bool { + **self == FORM_A::SPI_FRAME + } + #[doc = "Checks if the value of the field is `SPI_FRAME_WITH_ADDR`"] + #[inline(always)] + pub fn is_spi_frame_with_addr(&self) -> bool { + **self == FORM_A::SPI_FRAME_WITH_ADDR + } +} +impl core::ops::Deref for FORM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FORM` writer - Frame Format"] +pub struct FORM_W<'a> { + w: &'a mut W, +} +impl<'a> FORM_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FORM_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "SPI Frame"] + #[inline(always)] + pub fn spi_frame(self) -> &'a mut W { + self.variant(FORM_A::SPI_FRAME) + } + #[doc = "SPI Frame with Addr"] + #[inline(always)] + pub fn spi_frame_with_addr(self) -> &'a mut W { + self.variant(FORM_A::SPI_FRAME_WITH_ADDR) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Clock Phase\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CPHA_A { + #[doc = "0: The data is sampled on a leading SCK edge and changed on a trailing SCK edge"] + LEADING_EDGE = 0, + #[doc = "1: The data is sampled on a trailing SCK edge and changed on a leading SCK edge"] + TRAILING_EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CPHA_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CPHA` reader - Clock Phase"] +pub struct CPHA_R(crate::FieldReader); +impl CPHA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPHA_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CPHA_A { + match self.bits { + false => CPHA_A::LEADING_EDGE, + true => CPHA_A::TRAILING_EDGE, + } + } + #[doc = "Checks if the value of the field is `LEADING_EDGE`"] + #[inline(always)] + pub fn is_leading_edge(&self) -> bool { + **self == CPHA_A::LEADING_EDGE + } + #[doc = "Checks if the value of the field is `TRAILING_EDGE`"] + #[inline(always)] + pub fn is_trailing_edge(&self) -> bool { + **self == CPHA_A::TRAILING_EDGE + } +} +impl core::ops::Deref for CPHA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPHA` writer - Clock Phase"] +pub struct CPHA_W<'a> { + w: &'a mut W, +} +impl<'a> CPHA_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CPHA_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "The data is sampled on a leading SCK edge and changed on a trailing SCK edge"] + #[inline(always)] + pub fn leading_edge(self) -> &'a mut W { + self.variant(CPHA_A::LEADING_EDGE) + } + #[doc = "The data is sampled on a trailing SCK edge and changed on a leading SCK edge"] + #[inline(always)] + pub fn trailing_edge(self) -> &'a mut W { + self.variant(CPHA_A::TRAILING_EDGE) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Clock Polarity\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CPOL_A { + #[doc = "0: SCK is low when idle"] + IDLE_LOW = 0, + #[doc = "1: SCK is high when idle"] + IDLE_HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CPOL_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CPOL` reader - Clock Polarity"] +pub struct CPOL_R(crate::FieldReader); +impl CPOL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPOL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CPOL_A { + match self.bits { + false => CPOL_A::IDLE_LOW, + true => CPOL_A::IDLE_HIGH, + } + } + #[doc = "Checks if the value of the field is `IDLE_LOW`"] + #[inline(always)] + pub fn is_idle_low(&self) -> bool { + **self == CPOL_A::IDLE_LOW + } + #[doc = "Checks if the value of the field is `IDLE_HIGH`"] + #[inline(always)] + pub fn is_idle_high(&self) -> bool { + **self == CPOL_A::IDLE_HIGH + } +} +impl core::ops::Deref for CPOL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPOL` writer - Clock Polarity"] +pub struct CPOL_W<'a> { + w: &'a mut W, +} +impl<'a> CPOL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CPOL_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "SCK is low when idle"] + #[inline(always)] + pub fn idle_low(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_LOW) + } + #[doc = "SCK is high when idle"] + #[inline(always)] + pub fn idle_high(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_HIGH) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29); + self.w + } +} +#[doc = "Data Order\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum DORD_A { + #[doc = "0: MSB is transferred first"] + MSB = 0, + #[doc = "1: LSB is transferred first"] + LSB = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DORD_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DORD` reader - Data Order"] +pub struct DORD_R(crate::FieldReader); +impl DORD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DORD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DORD_A { + match self.bits { + false => DORD_A::MSB, + true => DORD_A::LSB, + } + } + #[doc = "Checks if the value of the field is `MSB`"] + #[inline(always)] + pub fn is_msb(&self) -> bool { + **self == DORD_A::MSB + } + #[doc = "Checks if the value of the field is `LSB`"] + #[inline(always)] + pub fn is_lsb(&self) -> bool { + **self == DORD_A::LSB + } +} +impl core::ops::Deref for DORD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DORD` writer - Data Order"] +pub struct DORD_W<'a> { + w: &'a mut W, +} +impl<'a> DORD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DORD_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "MSB is transferred first"] + #[inline(always)] + pub fn msb(self) -> &'a mut W { + self.variant(DORD_A::MSB) + } + #[doc = "LSB is transferred first"] + #[inline(always)] + pub fn lsb(self) -> &'a mut W { + self.variant(DORD_A::LSB) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x07) as u8) + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&self) -> IBON_R { + IBON_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bits 16:17 - Data Out Pinout"] + #[inline(always)] + pub fn dopo(&self) -> DOPO_R { + DOPO_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bits 20:21 - Data In Pinout"] + #[inline(always)] + pub fn dipo(&self) -> DIPO_R { + DIPO_R::new(((self.bits >> 20) & 0x03) as u8) + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&self) -> FORM_R { + FORM_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 28 - Clock Phase"] + #[inline(always)] + pub fn cpha(&self) -> CPHA_R { + CPHA_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&self) -> CPOL_R { + CPOL_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&self) -> DORD_R { + DORD_R::new(((self.bits >> 30) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&mut self) -> IBON_W { + IBON_W { w: self } + } + #[doc = "Bits 16:17 - Data Out Pinout"] + #[inline(always)] + pub fn dopo(&mut self) -> DOPO_W { + DOPO_W { w: self } + } + #[doc = "Bits 20:21 - Data In Pinout"] + #[inline(always)] + pub fn dipo(&mut self) -> DIPO_W { + DIPO_W { w: self } + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&mut self) -> FORM_W { + FORM_W { w: self } + } + #[doc = "Bit 28 - Clock Phase"] + #[inline(always)] + pub fn cpha(&mut self) -> CPHA_W { + CPHA_W { w: self } + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&mut self) -> CPOL_W { + CPOL_W { w: self } + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&mut self) -> DORD_W { + DORD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sercom0/spim/ctrlb.rs b/pac/atsamc21n/src/sercom0/spim/ctrlb.rs new file mode 100644 index 000000000000..3d94f824ce83 --- /dev/null +++ b/pac/atsamc21n/src/sercom0/spim/ctrlb.rs @@ -0,0 +1,439 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Character Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CHSIZE_A { + #[doc = "0: 8 bits"] + _8_BIT = 0, + #[doc = "1: 9 bits"] + _9_BIT = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CHSIZE_A) -> Self { + variant as _ + } +} +#[doc = "Field `CHSIZE` reader - Character Size"] +pub struct CHSIZE_R(crate::FieldReader); +impl CHSIZE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CHSIZE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CHSIZE_A::_8_BIT), + 1 => Some(CHSIZE_A::_9_BIT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_8_BIT`"] + #[inline(always)] + pub fn is_8_bit(&self) -> bool { + **self == CHSIZE_A::_8_BIT + } + #[doc = "Checks if the value of the field is `_9_BIT`"] + #[inline(always)] + pub fn is_9_bit(&self) -> bool { + **self == CHSIZE_A::_9_BIT + } +} +impl core::ops::Deref for CHSIZE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHSIZE` writer - Character Size"] +pub struct CHSIZE_W<'a> { + w: &'a mut W, +} +impl<'a> CHSIZE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CHSIZE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8 bits"] + #[inline(always)] + pub fn _8_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_8_BIT) + } + #[doc = "9 bits"] + #[inline(always)] + pub fn _9_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_9_BIT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Field `PLOADEN` reader - Data Preload Enable"] +pub struct PLOADEN_R(crate::FieldReader); +impl PLOADEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PLOADEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PLOADEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PLOADEN` writer - Data Preload Enable"] +pub struct PLOADEN_W<'a> { + w: &'a mut W, +} +impl<'a> PLOADEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `SSDE` reader - Slave Select Low Detect Enable"] +pub struct SSDE_R(crate::FieldReader); +impl SSDE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SSDE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSDE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSDE` writer - Slave Select Low Detect Enable"] +pub struct SSDE_W<'a> { + w: &'a mut W, +} +impl<'a> SSDE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `MSSEN` reader - Master Slave Select Enable"] +pub struct MSSEN_R(crate::FieldReader); +impl MSSEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MSSEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MSSEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MSSEN` writer - Master Slave Select Enable"] +pub struct MSSEN_W<'a> { + w: &'a mut W, +} +impl<'a> MSSEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Address Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum AMODE_A { + #[doc = "0: SPI Address mask"] + MASK = 0, + #[doc = "1: Two unique Addressess"] + _2_ADDRESSES = 1, + #[doc = "2: Address Range"] + RANGE = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: AMODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `AMODE` reader - Address Mode"] +pub struct AMODE_R(crate::FieldReader); +impl AMODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + AMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(AMODE_A::MASK), + 1 => Some(AMODE_A::_2_ADDRESSES), + 2 => Some(AMODE_A::RANGE), + _ => None, + } + } + #[doc = "Checks if the value of the field is `MASK`"] + #[inline(always)] + pub fn is_mask(&self) -> bool { + **self == AMODE_A::MASK + } + #[doc = "Checks if the value of the field is `_2_ADDRESSES`"] + #[inline(always)] + pub fn is_2_addresses(&self) -> bool { + **self == AMODE_A::_2_ADDRESSES + } + #[doc = "Checks if the value of the field is `RANGE`"] + #[inline(always)] + pub fn is_range(&self) -> bool { + **self == AMODE_A::RANGE + } +} +impl core::ops::Deref for AMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AMODE` writer - Address Mode"] +pub struct AMODE_W<'a> { + w: &'a mut W, +} +impl<'a> AMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: AMODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "SPI Address mask"] + #[inline(always)] + pub fn mask(self) -> &'a mut W { + self.variant(AMODE_A::MASK) + } + #[doc = "Two unique Addressess"] + #[inline(always)] + pub fn _2_addresses(self) -> &'a mut W { + self.variant(AMODE_A::_2_ADDRESSES) + } + #[doc = "Address Range"] + #[inline(always)] + pub fn range(self) -> &'a mut W { + self.variant(AMODE_A::RANGE) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 14)) | ((value as u32 & 0x03) << 14); + self.w + } +} +#[doc = "Field `RXEN` reader - Receiver Enable"] +pub struct RXEN_R(crate::FieldReader); +impl RXEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXEN` writer - Receiver Enable"] +pub struct RXEN_W<'a> { + w: &'a mut W, +} +impl<'a> RXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&self) -> CHSIZE_R { + CHSIZE_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 6 - Data Preload Enable"] + #[inline(always)] + pub fn ploaden(&self) -> PLOADEN_R { + PLOADEN_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 9 - Slave Select Low Detect Enable"] + #[inline(always)] + pub fn ssde(&self) -> SSDE_R { + SSDE_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 13 - Master Slave Select Enable"] + #[inline(always)] + pub fn mssen(&self) -> MSSEN_R { + MSSEN_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bits 14:15 - Address Mode"] + #[inline(always)] + pub fn amode(&self) -> AMODE_R { + AMODE_R::new(((self.bits >> 14) & 0x03) as u8) + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&self) -> RXEN_R { + RXEN_R::new(((self.bits >> 17) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&mut self) -> CHSIZE_W { + CHSIZE_W { w: self } + } + #[doc = "Bit 6 - Data Preload Enable"] + #[inline(always)] + pub fn ploaden(&mut self) -> PLOADEN_W { + PLOADEN_W { w: self } + } + #[doc = "Bit 9 - Slave Select Low Detect Enable"] + #[inline(always)] + pub fn ssde(&mut self) -> SSDE_W { + SSDE_W { w: self } + } + #[doc = "Bit 13 - Master Slave Select Enable"] + #[inline(always)] + pub fn mssen(&mut self) -> MSSEN_W { + MSSEN_W { w: self } + } + #[doc = "Bits 14:15 - Address Mode"] + #[inline(always)] + pub fn amode(&mut self) -> AMODE_W { + AMODE_W { w: self } + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&mut self) -> RXEN_W { + RXEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sercom0/spim/data.rs b/pac/atsamc21n/src/sercom0/spim/data.rs new file mode 100644 index 000000000000..dc9cd020d2a5 --- /dev/null +++ b/pac/atsamc21n/src/sercom0/spim/data.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data Value"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data Value"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01ff) | (value as u32 & 0x01ff); + self.w + } +} +impl R { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new((self.bits & 0x01ff) as u16) + } +} +impl W { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sercom0/spim/dbgctrl.rs b/pac/atsamc21n/src/sercom0/spim/dbgctrl.rs new file mode 100644 index 000000000000..d9aa7495940c --- /dev/null +++ b/pac/atsamc21n/src/sercom0/spim/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGSTOP` reader - Debug Mode"] +pub struct DBGSTOP_R(crate::FieldReader); +impl DBGSTOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGSTOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGSTOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGSTOP` writer - Debug Mode"] +pub struct DBGSTOP_W<'a> { + w: &'a mut W, +} +impl<'a> DBGSTOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&self) -> DBGSTOP_R { + DBGSTOP_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&mut self) -> DBGSTOP_W { + DBGSTOP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sercom0/spim/intenclr.rs b/pac/atsamc21n/src/sercom0/spim/intenclr.rs new file mode 100644 index 000000000000..ccab3de4348d --- /dev/null +++ b/pac/atsamc21n/src/sercom0/spim/intenclr.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Disable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Disable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Disable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Disable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Disable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Disable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SSL` reader - Slave Select Low Interrupt Disable"] +pub struct SSL_R(crate::FieldReader); +impl SSL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SSL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSL` writer - Slave Select Low Interrupt Disable"] +pub struct SSL_W<'a> { + w: &'a mut W, +} +impl<'a> SSL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Disable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Disable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Slave Select Low Interrupt Disable"] + #[inline(always)] + pub fn ssl(&self) -> SSL_R { + SSL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Slave Select Low Interrupt Disable"] + #[inline(always)] + pub fn ssl(&mut self) -> SSL_W { + SSL_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sercom0/spim/intenset.rs b/pac/atsamc21n/src/sercom0/spim/intenset.rs new file mode 100644 index 000000000000..d9779cf897c2 --- /dev/null +++ b/pac/atsamc21n/src/sercom0/spim/intenset.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Enable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Enable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Enable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Enable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Enable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Enable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SSL` reader - Slave Select Low Interrupt Enable"] +pub struct SSL_R(crate::FieldReader); +impl SSL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SSL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSL` writer - Slave Select Low Interrupt Enable"] +pub struct SSL_W<'a> { + w: &'a mut W, +} +impl<'a> SSL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Slave Select Low Interrupt Enable"] + #[inline(always)] + pub fn ssl(&self) -> SSL_R { + SSL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Slave Select Low Interrupt Enable"] + #[inline(always)] + pub fn ssl(&mut self) -> SSL_W { + SSL_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sercom0/spim/intflag.rs b/pac/atsamc21n/src/sercom0/spim/intflag.rs new file mode 100644 index 000000000000..e9bc10c271b8 --- /dev/null +++ b/pac/atsamc21n/src/sercom0/spim/intflag.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SSL` reader - Slave Select Low Interrupt Flag"] +pub struct SSL_R(crate::FieldReader); +impl SSL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SSL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSL` writer - Slave Select Low Interrupt Flag"] +pub struct SSL_W<'a> { + w: &'a mut W, +} +impl<'a> SSL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Slave Select Low Interrupt Flag"] + #[inline(always)] + pub fn ssl(&self) -> SSL_R { + SSL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Slave Select Low Interrupt Flag"] + #[inline(always)] + pub fn ssl(&mut self) -> SSL_W { + SSL_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sercom0/spim/status.rs b/pac/atsamc21n/src/sercom0/spim/status.rs new file mode 100644 index 000000000000..9919460bf0e2 --- /dev/null +++ b/pac/atsamc21n/src/sercom0/spim/status.rs @@ -0,0 +1,113 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BUFOVF` reader - Buffer Overflow"] +pub struct BUFOVF_R(crate::FieldReader); +impl BUFOVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUFOVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUFOVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUFOVF` writer - Buffer Overflow"] +pub struct BUFOVF_W<'a> { + w: &'a mut W, +} +impl<'a> BUFOVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&self) -> BUFOVF_R { + BUFOVF_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&mut self) -> BUFOVF_W { + BUFOVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sercom0/spim/syncbusy.rs b/pac/atsamc21n/src/sercom0/spim/syncbusy.rs new file mode 100644 index 000000000000..bee13adf7084 --- /dev/null +++ b/pac/atsamc21n/src/sercom0/spim/syncbusy.rs @@ -0,0 +1,93 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - SERCOM Enable Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLB` reader - CTRLB Synchronization Busy"] +pub struct CTRLB_R(crate::FieldReader); +impl CTRLB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM Enable Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - CTRLB Synchronization Busy"] + #[inline(always)] + pub fn ctrlb(&self) -> CTRLB_R { + CTRLB_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +#[doc = "SPIM Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sercom0/spis.rs b/pac/atsamc21n/src/sercom0/spis.rs new file mode 100644 index 000000000000..eed10c90c460 --- /dev/null +++ b/pac/atsamc21n/src/sercom0/spis.rs @@ -0,0 +1,44 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "SPIS Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "SPIS Control B"] +pub mod ctrlb; +#[doc = "BAUD register accessor: an alias for `Reg`"] +pub type BAUD = crate::Reg; +#[doc = "SPIS Baud Rate"] +pub mod baud; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "SPIS Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "SPIS Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "SPIS Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "SPIS Status"] +pub mod status; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "SPIS Synchronization Busy"] +pub mod syncbusy; +#[doc = "ADDR register accessor: an alias for `Reg`"] +pub type ADDR = crate::Reg; +#[doc = "SPIS Address"] +pub mod addr; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "SPIS Data"] +pub mod data; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "SPIS Debug Control"] +pub mod dbgctrl; diff --git a/pac/atsamc21n/src/sercom0/spis/addr.rs b/pac/atsamc21n/src/sercom0/spis/addr.rs new file mode 100644 index 000000000000..5fca0a698bfe --- /dev/null +++ b/pac/atsamc21n/src/sercom0/spis/addr.rs @@ -0,0 +1,140 @@ +#[doc = "Register `ADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ADDR` reader - Address Value"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - Address Value"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +#[doc = "Field `ADDRMASK` reader - Address Mask"] +pub struct ADDRMASK_R(crate::FieldReader); +impl ADDRMASK_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ADDRMASK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDRMASK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDRMASK` writer - Address Mask"] +pub struct ADDRMASK_W<'a> { + w: &'a mut W, +} +impl<'a> ADDRMASK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Address Value"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 16:23 - Address Mask"] + #[inline(always)] + pub fn addrmask(&self) -> ADDRMASK_R { + ADDRMASK_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Address Value"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Bits 16:23 - Address Mask"] + #[inline(always)] + pub fn addrmask(&mut self) -> ADDRMASK_W { + ADDRMASK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [addr](index.html) module"] +pub struct ADDR_SPEC; +impl crate::RegisterSpec for ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [addr::R](R) reader structure"] +impl crate::Readable for ADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [addr::W](W) writer structure"] +impl crate::Writable for ADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ADDR to value 0"] +impl crate::Resettable for ADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sercom0/spis/baud.rs b/pac/atsamc21n/src/sercom0/spis/baud.rs new file mode 100644 index 000000000000..eeee4cf633e5 --- /dev/null +++ b/pac/atsamc21n/src/sercom0/spis/baud.rs @@ -0,0 +1,103 @@ +#[doc = "Register `BAUD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud](index.html) module"] +pub struct BAUD_SPEC; +impl crate::RegisterSpec for BAUD_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [baud::R](R) reader structure"] +impl crate::Readable for BAUD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud::W](W) writer structure"] +impl crate::Writable for BAUD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD to value 0"] +impl crate::Resettable for BAUD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sercom0/spis/ctrla.rs b/pac/atsamc21n/src/sercom0/spis/ctrla.rs new file mode 100644 index 000000000000..6151433a8529 --- /dev/null +++ b/pac/atsamc21n/src/sercom0/spis/ctrla.rs @@ -0,0 +1,992 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: USART with external clock"] + USART_EXT_CLK = 0, + #[doc = "1: USART with internal clock"] + USART_INT_CLK = 1, + #[doc = "2: SPI in slave operation"] + SPI_SLAVE = 2, + #[doc = "3: SPI in master operation"] + SPI_MASTER = 3, + #[doc = "4: I2C slave operation"] + I2C_SLAVE = 4, + #[doc = "5: I2C master operation"] + I2C_MASTER = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::USART_EXT_CLK), + 1 => Some(MODE_A::USART_INT_CLK), + 2 => Some(MODE_A::SPI_SLAVE), + 3 => Some(MODE_A::SPI_MASTER), + 4 => Some(MODE_A::I2C_SLAVE), + 5 => Some(MODE_A::I2C_MASTER), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_EXT_CLK`"] + #[inline(always)] + pub fn is_usart_ext_clk(&self) -> bool { + **self == MODE_A::USART_EXT_CLK + } + #[doc = "Checks if the value of the field is `USART_INT_CLK`"] + #[inline(always)] + pub fn is_usart_int_clk(&self) -> bool { + **self == MODE_A::USART_INT_CLK + } + #[doc = "Checks if the value of the field is `SPI_SLAVE`"] + #[inline(always)] + pub fn is_spi_slave(&self) -> bool { + **self == MODE_A::SPI_SLAVE + } + #[doc = "Checks if the value of the field is `SPI_MASTER`"] + #[inline(always)] + pub fn is_spi_master(&self) -> bool { + **self == MODE_A::SPI_MASTER + } + #[doc = "Checks if the value of the field is `I2C_SLAVE`"] + #[inline(always)] + pub fn is_i2c_slave(&self) -> bool { + **self == MODE_A::I2C_SLAVE + } + #[doc = "Checks if the value of the field is `I2C_MASTER`"] + #[inline(always)] + pub fn is_i2c_master(&self) -> bool { + **self == MODE_A::I2C_MASTER + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART with external clock"] + #[inline(always)] + pub fn usart_ext_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_EXT_CLK) + } + #[doc = "USART with internal clock"] + #[inline(always)] + pub fn usart_int_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_INT_CLK) + } + #[doc = "SPI in slave operation"] + #[inline(always)] + pub fn spi_slave(self) -> &'a mut W { + self.variant(MODE_A::SPI_SLAVE) + } + #[doc = "SPI in master operation"] + #[inline(always)] + pub fn spi_master(self) -> &'a mut W { + self.variant(MODE_A::SPI_MASTER) + } + #[doc = "I2C slave operation"] + #[inline(always)] + pub fn i2c_slave(self) -> &'a mut W { + self.variant(MODE_A::I2C_SLAVE) + } + #[doc = "I2C master operation"] + #[inline(always)] + pub fn i2c_master(self) -> &'a mut W { + self.variant(MODE_A::I2C_MASTER) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 2)) | ((value as u32 & 0x07) << 2); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `IBON` reader - Immediate Buffer Overflow Notification"] +pub struct IBON_R(crate::FieldReader); +impl IBON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IBON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IBON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IBON` writer - Immediate Buffer Overflow Notification"] +pub struct IBON_W<'a> { + w: &'a mut W, +} +impl<'a> IBON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Data Out Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DOPO_A { + #[doc = "0: DO on PAD\\[0\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + PAD0 = 0, + #[doc = "1: DO on PAD\\[2\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + PAD1 = 1, + #[doc = "2: DO on PAD\\[3\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + PAD2 = 2, + #[doc = "3: DO on PAD\\[0\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + PAD3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DOPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `DOPO` reader - Data Out Pinout"] +pub struct DOPO_R(crate::FieldReader); +impl DOPO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DOPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DOPO_A { + match self.bits { + 0 => DOPO_A::PAD0, + 1 => DOPO_A::PAD1, + 2 => DOPO_A::PAD2, + 3 => DOPO_A::PAD3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == DOPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD1`"] + #[inline(always)] + pub fn is_pad1(&self) -> bool { + **self == DOPO_A::PAD1 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == DOPO_A::PAD2 + } + #[doc = "Checks if the value of the field is `PAD3`"] + #[inline(always)] + pub fn is_pad3(&self) -> bool { + **self == DOPO_A::PAD3 + } +} +impl core::ops::Deref for DOPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DOPO` writer - Data Out Pinout"] +pub struct DOPO_W<'a> { + w: &'a mut W, +} +impl<'a> DOPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DOPO_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "DO on PAD\\[0\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(DOPO_A::PAD0) + } + #[doc = "DO on PAD\\[2\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + #[inline(always)] + pub fn pad1(self) -> &'a mut W { + self.variant(DOPO_A::PAD1) + } + #[doc = "DO on PAD\\[3\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(DOPO_A::PAD2) + } + #[doc = "DO on PAD\\[0\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + #[inline(always)] + pub fn pad3(self) -> &'a mut W { + self.variant(DOPO_A::PAD3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Data In Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DIPO_A { + #[doc = "0: SERCOM PAD\\[0\\]"] + PAD0 = 0, + #[doc = "1: SERCOM PAD\\[1\\]"] + PAD1 = 1, + #[doc = "2: SERCOM PAD\\[2\\]"] + PAD2 = 2, + #[doc = "3: SERCOM PAD\\[3\\]"] + PAD3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DIPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `DIPO` reader - Data In Pinout"] +pub struct DIPO_R(crate::FieldReader); +impl DIPO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DIPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DIPO_A { + match self.bits { + 0 => DIPO_A::PAD0, + 1 => DIPO_A::PAD1, + 2 => DIPO_A::PAD2, + 3 => DIPO_A::PAD3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == DIPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD1`"] + #[inline(always)] + pub fn is_pad1(&self) -> bool { + **self == DIPO_A::PAD1 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == DIPO_A::PAD2 + } + #[doc = "Checks if the value of the field is `PAD3`"] + #[inline(always)] + pub fn is_pad3(&self) -> bool { + **self == DIPO_A::PAD3 + } +} +impl core::ops::Deref for DIPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIPO` writer - Data In Pinout"] +pub struct DIPO_W<'a> { + w: &'a mut W, +} +impl<'a> DIPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DIPO_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "SERCOM PAD\\[0\\]"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(DIPO_A::PAD0) + } + #[doc = "SERCOM PAD\\[1\\]"] + #[inline(always)] + pub fn pad1(self) -> &'a mut W { + self.variant(DIPO_A::PAD1) + } + #[doc = "SERCOM PAD\\[2\\]"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(DIPO_A::PAD2) + } + #[doc = "SERCOM PAD\\[3\\]"] + #[inline(always)] + pub fn pad3(self) -> &'a mut W { + self.variant(DIPO_A::PAD3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 20)) | ((value as u32 & 0x03) << 20); + self.w + } +} +#[doc = "Frame Format\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FORM_A { + #[doc = "0: SPI Frame"] + SPI_FRAME = 0, + #[doc = "2: SPI Frame with Addr"] + SPI_FRAME_WITH_ADDR = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FORM_A) -> Self { + variant as _ + } +} +#[doc = "Field `FORM` reader - Frame Format"] +pub struct FORM_R(crate::FieldReader); +impl FORM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FORM_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(FORM_A::SPI_FRAME), + 2 => Some(FORM_A::SPI_FRAME_WITH_ADDR), + _ => None, + } + } + #[doc = "Checks if the value of the field is `SPI_FRAME`"] + #[inline(always)] + pub fn is_spi_frame(&self) -> bool { + **self == FORM_A::SPI_FRAME + } + #[doc = "Checks if the value of the field is `SPI_FRAME_WITH_ADDR`"] + #[inline(always)] + pub fn is_spi_frame_with_addr(&self) -> bool { + **self == FORM_A::SPI_FRAME_WITH_ADDR + } +} +impl core::ops::Deref for FORM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FORM` writer - Frame Format"] +pub struct FORM_W<'a> { + w: &'a mut W, +} +impl<'a> FORM_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FORM_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "SPI Frame"] + #[inline(always)] + pub fn spi_frame(self) -> &'a mut W { + self.variant(FORM_A::SPI_FRAME) + } + #[doc = "SPI Frame with Addr"] + #[inline(always)] + pub fn spi_frame_with_addr(self) -> &'a mut W { + self.variant(FORM_A::SPI_FRAME_WITH_ADDR) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Clock Phase\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CPHA_A { + #[doc = "0: The data is sampled on a leading SCK edge and changed on a trailing SCK edge"] + LEADING_EDGE = 0, + #[doc = "1: The data is sampled on a trailing SCK edge and changed on a leading SCK edge"] + TRAILING_EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CPHA_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CPHA` reader - Clock Phase"] +pub struct CPHA_R(crate::FieldReader); +impl CPHA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPHA_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CPHA_A { + match self.bits { + false => CPHA_A::LEADING_EDGE, + true => CPHA_A::TRAILING_EDGE, + } + } + #[doc = "Checks if the value of the field is `LEADING_EDGE`"] + #[inline(always)] + pub fn is_leading_edge(&self) -> bool { + **self == CPHA_A::LEADING_EDGE + } + #[doc = "Checks if the value of the field is `TRAILING_EDGE`"] + #[inline(always)] + pub fn is_trailing_edge(&self) -> bool { + **self == CPHA_A::TRAILING_EDGE + } +} +impl core::ops::Deref for CPHA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPHA` writer - Clock Phase"] +pub struct CPHA_W<'a> { + w: &'a mut W, +} +impl<'a> CPHA_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CPHA_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "The data is sampled on a leading SCK edge and changed on a trailing SCK edge"] + #[inline(always)] + pub fn leading_edge(self) -> &'a mut W { + self.variant(CPHA_A::LEADING_EDGE) + } + #[doc = "The data is sampled on a trailing SCK edge and changed on a leading SCK edge"] + #[inline(always)] + pub fn trailing_edge(self) -> &'a mut W { + self.variant(CPHA_A::TRAILING_EDGE) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Clock Polarity\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CPOL_A { + #[doc = "0: SCK is low when idle"] + IDLE_LOW = 0, + #[doc = "1: SCK is high when idle"] + IDLE_HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CPOL_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CPOL` reader - Clock Polarity"] +pub struct CPOL_R(crate::FieldReader); +impl CPOL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPOL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CPOL_A { + match self.bits { + false => CPOL_A::IDLE_LOW, + true => CPOL_A::IDLE_HIGH, + } + } + #[doc = "Checks if the value of the field is `IDLE_LOW`"] + #[inline(always)] + pub fn is_idle_low(&self) -> bool { + **self == CPOL_A::IDLE_LOW + } + #[doc = "Checks if the value of the field is `IDLE_HIGH`"] + #[inline(always)] + pub fn is_idle_high(&self) -> bool { + **self == CPOL_A::IDLE_HIGH + } +} +impl core::ops::Deref for CPOL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPOL` writer - Clock Polarity"] +pub struct CPOL_W<'a> { + w: &'a mut W, +} +impl<'a> CPOL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CPOL_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "SCK is low when idle"] + #[inline(always)] + pub fn idle_low(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_LOW) + } + #[doc = "SCK is high when idle"] + #[inline(always)] + pub fn idle_high(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_HIGH) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29); + self.w + } +} +#[doc = "Data Order\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum DORD_A { + #[doc = "0: MSB is transferred first"] + MSB = 0, + #[doc = "1: LSB is transferred first"] + LSB = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DORD_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DORD` reader - Data Order"] +pub struct DORD_R(crate::FieldReader); +impl DORD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DORD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DORD_A { + match self.bits { + false => DORD_A::MSB, + true => DORD_A::LSB, + } + } + #[doc = "Checks if the value of the field is `MSB`"] + #[inline(always)] + pub fn is_msb(&self) -> bool { + **self == DORD_A::MSB + } + #[doc = "Checks if the value of the field is `LSB`"] + #[inline(always)] + pub fn is_lsb(&self) -> bool { + **self == DORD_A::LSB + } +} +impl core::ops::Deref for DORD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DORD` writer - Data Order"] +pub struct DORD_W<'a> { + w: &'a mut W, +} +impl<'a> DORD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DORD_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "MSB is transferred first"] + #[inline(always)] + pub fn msb(self) -> &'a mut W { + self.variant(DORD_A::MSB) + } + #[doc = "LSB is transferred first"] + #[inline(always)] + pub fn lsb(self) -> &'a mut W { + self.variant(DORD_A::LSB) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x07) as u8) + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&self) -> IBON_R { + IBON_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bits 16:17 - Data Out Pinout"] + #[inline(always)] + pub fn dopo(&self) -> DOPO_R { + DOPO_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bits 20:21 - Data In Pinout"] + #[inline(always)] + pub fn dipo(&self) -> DIPO_R { + DIPO_R::new(((self.bits >> 20) & 0x03) as u8) + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&self) -> FORM_R { + FORM_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 28 - Clock Phase"] + #[inline(always)] + pub fn cpha(&self) -> CPHA_R { + CPHA_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&self) -> CPOL_R { + CPOL_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&self) -> DORD_R { + DORD_R::new(((self.bits >> 30) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&mut self) -> IBON_W { + IBON_W { w: self } + } + #[doc = "Bits 16:17 - Data Out Pinout"] + #[inline(always)] + pub fn dopo(&mut self) -> DOPO_W { + DOPO_W { w: self } + } + #[doc = "Bits 20:21 - Data In Pinout"] + #[inline(always)] + pub fn dipo(&mut self) -> DIPO_W { + DIPO_W { w: self } + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&mut self) -> FORM_W { + FORM_W { w: self } + } + #[doc = "Bit 28 - Clock Phase"] + #[inline(always)] + pub fn cpha(&mut self) -> CPHA_W { + CPHA_W { w: self } + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&mut self) -> CPOL_W { + CPOL_W { w: self } + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&mut self) -> DORD_W { + DORD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sercom0/spis/ctrlb.rs b/pac/atsamc21n/src/sercom0/spis/ctrlb.rs new file mode 100644 index 000000000000..ccb70582cf34 --- /dev/null +++ b/pac/atsamc21n/src/sercom0/spis/ctrlb.rs @@ -0,0 +1,439 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Character Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CHSIZE_A { + #[doc = "0: 8 bits"] + _8_BIT = 0, + #[doc = "1: 9 bits"] + _9_BIT = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CHSIZE_A) -> Self { + variant as _ + } +} +#[doc = "Field `CHSIZE` reader - Character Size"] +pub struct CHSIZE_R(crate::FieldReader); +impl CHSIZE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CHSIZE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CHSIZE_A::_8_BIT), + 1 => Some(CHSIZE_A::_9_BIT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_8_BIT`"] + #[inline(always)] + pub fn is_8_bit(&self) -> bool { + **self == CHSIZE_A::_8_BIT + } + #[doc = "Checks if the value of the field is `_9_BIT`"] + #[inline(always)] + pub fn is_9_bit(&self) -> bool { + **self == CHSIZE_A::_9_BIT + } +} +impl core::ops::Deref for CHSIZE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHSIZE` writer - Character Size"] +pub struct CHSIZE_W<'a> { + w: &'a mut W, +} +impl<'a> CHSIZE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CHSIZE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8 bits"] + #[inline(always)] + pub fn _8_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_8_BIT) + } + #[doc = "9 bits"] + #[inline(always)] + pub fn _9_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_9_BIT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Field `PLOADEN` reader - Data Preload Enable"] +pub struct PLOADEN_R(crate::FieldReader); +impl PLOADEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PLOADEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PLOADEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PLOADEN` writer - Data Preload Enable"] +pub struct PLOADEN_W<'a> { + w: &'a mut W, +} +impl<'a> PLOADEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `SSDE` reader - Slave Select Low Detect Enable"] +pub struct SSDE_R(crate::FieldReader); +impl SSDE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SSDE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSDE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSDE` writer - Slave Select Low Detect Enable"] +pub struct SSDE_W<'a> { + w: &'a mut W, +} +impl<'a> SSDE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `MSSEN` reader - Master Slave Select Enable"] +pub struct MSSEN_R(crate::FieldReader); +impl MSSEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MSSEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MSSEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MSSEN` writer - Master Slave Select Enable"] +pub struct MSSEN_W<'a> { + w: &'a mut W, +} +impl<'a> MSSEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Address Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum AMODE_A { + #[doc = "0: SPI Address mask"] + MASK = 0, + #[doc = "1: Two unique Addressess"] + _2_ADDRESSES = 1, + #[doc = "2: Address Range"] + RANGE = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: AMODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `AMODE` reader - Address Mode"] +pub struct AMODE_R(crate::FieldReader); +impl AMODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + AMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(AMODE_A::MASK), + 1 => Some(AMODE_A::_2_ADDRESSES), + 2 => Some(AMODE_A::RANGE), + _ => None, + } + } + #[doc = "Checks if the value of the field is `MASK`"] + #[inline(always)] + pub fn is_mask(&self) -> bool { + **self == AMODE_A::MASK + } + #[doc = "Checks if the value of the field is `_2_ADDRESSES`"] + #[inline(always)] + pub fn is_2_addresses(&self) -> bool { + **self == AMODE_A::_2_ADDRESSES + } + #[doc = "Checks if the value of the field is `RANGE`"] + #[inline(always)] + pub fn is_range(&self) -> bool { + **self == AMODE_A::RANGE + } +} +impl core::ops::Deref for AMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AMODE` writer - Address Mode"] +pub struct AMODE_W<'a> { + w: &'a mut W, +} +impl<'a> AMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: AMODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "SPI Address mask"] + #[inline(always)] + pub fn mask(self) -> &'a mut W { + self.variant(AMODE_A::MASK) + } + #[doc = "Two unique Addressess"] + #[inline(always)] + pub fn _2_addresses(self) -> &'a mut W { + self.variant(AMODE_A::_2_ADDRESSES) + } + #[doc = "Address Range"] + #[inline(always)] + pub fn range(self) -> &'a mut W { + self.variant(AMODE_A::RANGE) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 14)) | ((value as u32 & 0x03) << 14); + self.w + } +} +#[doc = "Field `RXEN` reader - Receiver Enable"] +pub struct RXEN_R(crate::FieldReader); +impl RXEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXEN` writer - Receiver Enable"] +pub struct RXEN_W<'a> { + w: &'a mut W, +} +impl<'a> RXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&self) -> CHSIZE_R { + CHSIZE_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 6 - Data Preload Enable"] + #[inline(always)] + pub fn ploaden(&self) -> PLOADEN_R { + PLOADEN_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 9 - Slave Select Low Detect Enable"] + #[inline(always)] + pub fn ssde(&self) -> SSDE_R { + SSDE_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 13 - Master Slave Select Enable"] + #[inline(always)] + pub fn mssen(&self) -> MSSEN_R { + MSSEN_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bits 14:15 - Address Mode"] + #[inline(always)] + pub fn amode(&self) -> AMODE_R { + AMODE_R::new(((self.bits >> 14) & 0x03) as u8) + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&self) -> RXEN_R { + RXEN_R::new(((self.bits >> 17) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&mut self) -> CHSIZE_W { + CHSIZE_W { w: self } + } + #[doc = "Bit 6 - Data Preload Enable"] + #[inline(always)] + pub fn ploaden(&mut self) -> PLOADEN_W { + PLOADEN_W { w: self } + } + #[doc = "Bit 9 - Slave Select Low Detect Enable"] + #[inline(always)] + pub fn ssde(&mut self) -> SSDE_W { + SSDE_W { w: self } + } + #[doc = "Bit 13 - Master Slave Select Enable"] + #[inline(always)] + pub fn mssen(&mut self) -> MSSEN_W { + MSSEN_W { w: self } + } + #[doc = "Bits 14:15 - Address Mode"] + #[inline(always)] + pub fn amode(&mut self) -> AMODE_W { + AMODE_W { w: self } + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&mut self) -> RXEN_W { + RXEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sercom0/spis/data.rs b/pac/atsamc21n/src/sercom0/spis/data.rs new file mode 100644 index 000000000000..4edf8089b29f --- /dev/null +++ b/pac/atsamc21n/src/sercom0/spis/data.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data Value"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data Value"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01ff) | (value as u32 & 0x01ff); + self.w + } +} +impl R { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new((self.bits & 0x01ff) as u16) + } +} +impl W { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sercom0/spis/dbgctrl.rs b/pac/atsamc21n/src/sercom0/spis/dbgctrl.rs new file mode 100644 index 000000000000..ec36bbd26057 --- /dev/null +++ b/pac/atsamc21n/src/sercom0/spis/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGSTOP` reader - Debug Mode"] +pub struct DBGSTOP_R(crate::FieldReader); +impl DBGSTOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGSTOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGSTOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGSTOP` writer - Debug Mode"] +pub struct DBGSTOP_W<'a> { + w: &'a mut W, +} +impl<'a> DBGSTOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&self) -> DBGSTOP_R { + DBGSTOP_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&mut self) -> DBGSTOP_W { + DBGSTOP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sercom0/spis/intenclr.rs b/pac/atsamc21n/src/sercom0/spis/intenclr.rs new file mode 100644 index 000000000000..e4c9ee0d506d --- /dev/null +++ b/pac/atsamc21n/src/sercom0/spis/intenclr.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Disable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Disable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Disable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Disable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Disable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Disable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SSL` reader - Slave Select Low Interrupt Disable"] +pub struct SSL_R(crate::FieldReader); +impl SSL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SSL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSL` writer - Slave Select Low Interrupt Disable"] +pub struct SSL_W<'a> { + w: &'a mut W, +} +impl<'a> SSL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Disable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Disable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Slave Select Low Interrupt Disable"] + #[inline(always)] + pub fn ssl(&self) -> SSL_R { + SSL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Slave Select Low Interrupt Disable"] + #[inline(always)] + pub fn ssl(&mut self) -> SSL_W { + SSL_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sercom0/spis/intenset.rs b/pac/atsamc21n/src/sercom0/spis/intenset.rs new file mode 100644 index 000000000000..99582a624ebc --- /dev/null +++ b/pac/atsamc21n/src/sercom0/spis/intenset.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Enable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Enable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Enable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Enable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Enable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Enable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SSL` reader - Slave Select Low Interrupt Enable"] +pub struct SSL_R(crate::FieldReader); +impl SSL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SSL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSL` writer - Slave Select Low Interrupt Enable"] +pub struct SSL_W<'a> { + w: &'a mut W, +} +impl<'a> SSL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Slave Select Low Interrupt Enable"] + #[inline(always)] + pub fn ssl(&self) -> SSL_R { + SSL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Slave Select Low Interrupt Enable"] + #[inline(always)] + pub fn ssl(&mut self) -> SSL_W { + SSL_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sercom0/spis/intflag.rs b/pac/atsamc21n/src/sercom0/spis/intflag.rs new file mode 100644 index 000000000000..589e73c2329f --- /dev/null +++ b/pac/atsamc21n/src/sercom0/spis/intflag.rs @@ -0,0 +1,301 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SSL` reader - Slave Select Low Interrupt Flag"] +pub struct SSL_R(crate::FieldReader); +impl SSL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SSL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSL` writer - Slave Select Low Interrupt Flag"] +pub struct SSL_W<'a> { + w: &'a mut W, +} +impl<'a> SSL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Slave Select Low Interrupt Flag"] + #[inline(always)] + pub fn ssl(&self) -> SSL_R { + SSL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Slave Select Low Interrupt Flag"] + #[inline(always)] + pub fn ssl(&mut self) -> SSL_W { + SSL_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sercom0/spis/status.rs b/pac/atsamc21n/src/sercom0/spis/status.rs new file mode 100644 index 000000000000..55c39c1a709f --- /dev/null +++ b/pac/atsamc21n/src/sercom0/spis/status.rs @@ -0,0 +1,113 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BUFOVF` reader - Buffer Overflow"] +pub struct BUFOVF_R(crate::FieldReader); +impl BUFOVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUFOVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUFOVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUFOVF` writer - Buffer Overflow"] +pub struct BUFOVF_W<'a> { + w: &'a mut W, +} +impl<'a> BUFOVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&self) -> BUFOVF_R { + BUFOVF_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&mut self) -> BUFOVF_W { + BUFOVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIS Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sercom0/spis/syncbusy.rs b/pac/atsamc21n/src/sercom0/spis/syncbusy.rs new file mode 100644 index 000000000000..ac2f2e2c27ec --- /dev/null +++ b/pac/atsamc21n/src/sercom0/spis/syncbusy.rs @@ -0,0 +1,93 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - SERCOM Enable Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLB` reader - CTRLB Synchronization Busy"] +pub struct CTRLB_R(crate::FieldReader); +impl CTRLB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM Enable Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - CTRLB Synchronization Busy"] + #[inline(always)] + pub fn ctrlb(&self) -> CTRLB_R { + CTRLB_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +#[doc = "SPIS Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sercom0/usart_ext.rs b/pac/atsamc21n/src/sercom0/usart_ext.rs new file mode 100644 index 000000000000..8c08b9efc1d5 --- /dev/null +++ b/pac/atsamc21n/src/sercom0/usart_ext.rs @@ -0,0 +1,60 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "USART_EXT Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "USART_EXT Control B"] +pub mod ctrlb; +#[doc = "CTRLC register accessor: an alias for `Reg`"] +pub type CTRLC = crate::Reg; +#[doc = "USART_EXT Control C"] +pub mod ctrlc; +#[doc = "BAUD register accessor: an alias for `Reg`"] +pub type BAUD = crate::Reg; +#[doc = "USART_EXT Baud Rate"] +pub mod baud; +#[doc = "BAUD_FRAC_MODE register accessor: an alias for `Reg`"] +pub type BAUD_FRAC_MODE = crate::Reg; +#[doc = "USART_EXT Baud Rate"] +pub mod baud_frac_mode; +#[doc = "BAUD_FRACFP_MODE register accessor: an alias for `Reg`"] +pub type BAUD_FRACFP_MODE = crate::Reg; +#[doc = "USART_EXT Baud Rate"] +pub mod baud_fracfp_mode; +#[doc = "BAUD_USARTFP_MODE register accessor: an alias for `Reg`"] +pub type BAUD_USARTFP_MODE = crate::Reg; +#[doc = "USART_EXT Baud Rate"] +pub mod baud_usartfp_mode; +#[doc = "RXPL register accessor: an alias for `Reg`"] +pub type RXPL = crate::Reg; +#[doc = "USART_EXT Receive Pulse Length"] +pub mod rxpl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "USART_EXT Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "USART_EXT Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "USART_EXT Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "USART_EXT Status"] +pub mod status; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "USART_EXT Synchronization Busy"] +pub mod syncbusy; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "USART_EXT Data"] +pub mod data; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "USART_EXT Debug Control"] +pub mod dbgctrl; diff --git a/pac/atsamc21n/src/sercom0/usart_ext/baud.rs b/pac/atsamc21n/src/sercom0/usart_ext/baud.rs new file mode 100644 index 000000000000..9558a8e1a52d --- /dev/null +++ b/pac/atsamc21n/src/sercom0/usart_ext/baud.rs @@ -0,0 +1,103 @@ +#[doc = "Register `BAUD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud](index.html) module"] +pub struct BAUD_SPEC; +impl crate::RegisterSpec for BAUD_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud::R](R) reader structure"] +impl crate::Readable for BAUD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud::W](W) writer structure"] +impl crate::Writable for BAUD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD to value 0"] +impl crate::Resettable for BAUD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sercom0/usart_ext/baud_frac_mode.rs b/pac/atsamc21n/src/sercom0/usart_ext/baud_frac_mode.rs new file mode 100644 index 000000000000..d7cdd4570e26 --- /dev/null +++ b/pac/atsamc21n/src/sercom0/usart_ext/baud_frac_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `BAUD_FRAC_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD_FRAC_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1fff) | (value as u16 & 0x1fff); + self.w + } +} +#[doc = "Field `FP` reader - Fractional Part"] +pub struct FP_R(crate::FieldReader); +impl FP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FP` writer - Fractional Part"] +pub struct FP_W<'a> { + w: &'a mut W, +} +impl<'a> FP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 13)) | ((value as u16 & 0x07) << 13); + self.w + } +} +impl R { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new((self.bits & 0x1fff) as u16) + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&self) -> FP_R { + FP_R::new(((self.bits >> 13) & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&mut self) -> FP_W { + FP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud_frac_mode](index.html) module"] +pub struct BAUD_FRAC_MODE_SPEC; +impl crate::RegisterSpec for BAUD_FRAC_MODE_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud_frac_mode::R](R) reader structure"] +impl crate::Readable for BAUD_FRAC_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud_frac_mode::W](W) writer structure"] +impl crate::Writable for BAUD_FRAC_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD_FRAC_MODE to value 0"] +impl crate::Resettable for BAUD_FRAC_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sercom0/usart_ext/baud_fracfp_mode.rs b/pac/atsamc21n/src/sercom0/usart_ext/baud_fracfp_mode.rs new file mode 100644 index 000000000000..c1dc50807677 --- /dev/null +++ b/pac/atsamc21n/src/sercom0/usart_ext/baud_fracfp_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `BAUD_FRACFP_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD_FRACFP_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1fff) | (value as u16 & 0x1fff); + self.w + } +} +#[doc = "Field `FP` reader - Fractional Part"] +pub struct FP_R(crate::FieldReader); +impl FP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FP` writer - Fractional Part"] +pub struct FP_W<'a> { + w: &'a mut W, +} +impl<'a> FP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 13)) | ((value as u16 & 0x07) << 13); + self.w + } +} +impl R { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new((self.bits & 0x1fff) as u16) + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&self) -> FP_R { + FP_R::new(((self.bits >> 13) & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&mut self) -> FP_W { + FP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud_fracfp_mode](index.html) module"] +pub struct BAUD_FRACFP_MODE_SPEC; +impl crate::RegisterSpec for BAUD_FRACFP_MODE_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud_fracfp_mode::R](R) reader structure"] +impl crate::Readable for BAUD_FRACFP_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud_fracfp_mode::W](W) writer structure"] +impl crate::Writable for BAUD_FRACFP_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD_FRACFP_MODE to value 0"] +impl crate::Resettable for BAUD_FRACFP_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sercom0/usart_ext/baud_usartfp_mode.rs b/pac/atsamc21n/src/sercom0/usart_ext/baud_usartfp_mode.rs new file mode 100644 index 000000000000..8d4db16e0245 --- /dev/null +++ b/pac/atsamc21n/src/sercom0/usart_ext/baud_usartfp_mode.rs @@ -0,0 +1,103 @@ +#[doc = "Register `BAUD_USARTFP_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD_USARTFP_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud_usartfp_mode](index.html) module"] +pub struct BAUD_USARTFP_MODE_SPEC; +impl crate::RegisterSpec for BAUD_USARTFP_MODE_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud_usartfp_mode::R](R) reader structure"] +impl crate::Readable for BAUD_USARTFP_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud_usartfp_mode::W](W) writer structure"] +impl crate::Writable for BAUD_USARTFP_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD_USARTFP_MODE to value 0"] +impl crate::Resettable for BAUD_USARTFP_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sercom0/usart_ext/ctrla.rs b/pac/atsamc21n/src/sercom0/usart_ext/ctrla.rs new file mode 100644 index 000000000000..535875ac8b25 --- /dev/null +++ b/pac/atsamc21n/src/sercom0/usart_ext/ctrla.rs @@ -0,0 +1,1171 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: USART with external clock"] + USART_EXT_CLK = 0, + #[doc = "1: USART with internal clock"] + USART_INT_CLK = 1, + #[doc = "2: SPI in slave operation"] + SPI_SLAVE = 2, + #[doc = "3: SPI in master operation"] + SPI_MASTER = 3, + #[doc = "4: I2C slave operation"] + I2C_SLAVE = 4, + #[doc = "5: I2C master operation"] + I2C_MASTER = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::USART_EXT_CLK), + 1 => Some(MODE_A::USART_INT_CLK), + 2 => Some(MODE_A::SPI_SLAVE), + 3 => Some(MODE_A::SPI_MASTER), + 4 => Some(MODE_A::I2C_SLAVE), + 5 => Some(MODE_A::I2C_MASTER), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_EXT_CLK`"] + #[inline(always)] + pub fn is_usart_ext_clk(&self) -> bool { + **self == MODE_A::USART_EXT_CLK + } + #[doc = "Checks if the value of the field is `USART_INT_CLK`"] + #[inline(always)] + pub fn is_usart_int_clk(&self) -> bool { + **self == MODE_A::USART_INT_CLK + } + #[doc = "Checks if the value of the field is `SPI_SLAVE`"] + #[inline(always)] + pub fn is_spi_slave(&self) -> bool { + **self == MODE_A::SPI_SLAVE + } + #[doc = "Checks if the value of the field is `SPI_MASTER`"] + #[inline(always)] + pub fn is_spi_master(&self) -> bool { + **self == MODE_A::SPI_MASTER + } + #[doc = "Checks if the value of the field is `I2C_SLAVE`"] + #[inline(always)] + pub fn is_i2c_slave(&self) -> bool { + **self == MODE_A::I2C_SLAVE + } + #[doc = "Checks if the value of the field is `I2C_MASTER`"] + #[inline(always)] + pub fn is_i2c_master(&self) -> bool { + **self == MODE_A::I2C_MASTER + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART with external clock"] + #[inline(always)] + pub fn usart_ext_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_EXT_CLK) + } + #[doc = "USART with internal clock"] + #[inline(always)] + pub fn usart_int_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_INT_CLK) + } + #[doc = "SPI in slave operation"] + #[inline(always)] + pub fn spi_slave(self) -> &'a mut W { + self.variant(MODE_A::SPI_SLAVE) + } + #[doc = "SPI in master operation"] + #[inline(always)] + pub fn spi_master(self) -> &'a mut W { + self.variant(MODE_A::SPI_MASTER) + } + #[doc = "I2C slave operation"] + #[inline(always)] + pub fn i2c_slave(self) -> &'a mut W { + self.variant(MODE_A::I2C_SLAVE) + } + #[doc = "I2C master operation"] + #[inline(always)] + pub fn i2c_master(self) -> &'a mut W { + self.variant(MODE_A::I2C_MASTER) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 2)) | ((value as u32 & 0x07) << 2); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `IBON` reader - Immediate Buffer Overflow Notification"] +pub struct IBON_R(crate::FieldReader); +impl IBON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IBON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IBON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IBON` writer - Immediate Buffer Overflow Notification"] +pub struct IBON_W<'a> { + w: &'a mut W, +} +impl<'a> IBON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Sample\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SAMPR_A { + #[doc = "0: 16x over-sampling using arithmetic baudrate generation"] + _16X_ARITHMETIC = 0, + #[doc = "1: 16x over-sampling using fractional baudrate generation"] + _16X_FRACTIONAL = 1, + #[doc = "2: 8x over-sampling using arithmetic baudrate generation"] + _8X_ARITHMETIC = 2, + #[doc = "3: 8x over-sampling using fractional baudrate generation"] + _8X_FRACTIONAL = 3, + #[doc = "4: 3x over-sampling using arithmetic baudrate generation"] + _3X_ARITHMETIC = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SAMPR_A) -> Self { + variant as _ + } +} +#[doc = "Field `SAMPR` reader - Sample"] +pub struct SAMPR_R(crate::FieldReader); +impl SAMPR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SAMPR_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SAMPR_A::_16X_ARITHMETIC), + 1 => Some(SAMPR_A::_16X_FRACTIONAL), + 2 => Some(SAMPR_A::_8X_ARITHMETIC), + 3 => Some(SAMPR_A::_8X_FRACTIONAL), + 4 => Some(SAMPR_A::_3X_ARITHMETIC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_16X_ARITHMETIC`"] + #[inline(always)] + pub fn is_16x_arithmetic(&self) -> bool { + **self == SAMPR_A::_16X_ARITHMETIC + } + #[doc = "Checks if the value of the field is `_16X_FRACTIONAL`"] + #[inline(always)] + pub fn is_16x_fractional(&self) -> bool { + **self == SAMPR_A::_16X_FRACTIONAL + } + #[doc = "Checks if the value of the field is `_8X_ARITHMETIC`"] + #[inline(always)] + pub fn is_8x_arithmetic(&self) -> bool { + **self == SAMPR_A::_8X_ARITHMETIC + } + #[doc = "Checks if the value of the field is `_8X_FRACTIONAL`"] + #[inline(always)] + pub fn is_8x_fractional(&self) -> bool { + **self == SAMPR_A::_8X_FRACTIONAL + } + #[doc = "Checks if the value of the field is `_3X_ARITHMETIC`"] + #[inline(always)] + pub fn is_3x_arithmetic(&self) -> bool { + **self == SAMPR_A::_3X_ARITHMETIC + } +} +impl core::ops::Deref for SAMPR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SAMPR` writer - Sample"] +pub struct SAMPR_W<'a> { + w: &'a mut W, +} +impl<'a> SAMPR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SAMPR_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "16x over-sampling using arithmetic baudrate generation"] + #[inline(always)] + pub fn _16x_arithmetic(self) -> &'a mut W { + self.variant(SAMPR_A::_16X_ARITHMETIC) + } + #[doc = "16x over-sampling using fractional baudrate generation"] + #[inline(always)] + pub fn _16x_fractional(self) -> &'a mut W { + self.variant(SAMPR_A::_16X_FRACTIONAL) + } + #[doc = "8x over-sampling using arithmetic baudrate generation"] + #[inline(always)] + pub fn _8x_arithmetic(self) -> &'a mut W { + self.variant(SAMPR_A::_8X_ARITHMETIC) + } + #[doc = "8x over-sampling using fractional baudrate generation"] + #[inline(always)] + pub fn _8x_fractional(self) -> &'a mut W { + self.variant(SAMPR_A::_8X_FRACTIONAL) + } + #[doc = "3x over-sampling using arithmetic baudrate generation"] + #[inline(always)] + pub fn _3x_arithmetic(self) -> &'a mut W { + self.variant(SAMPR_A::_3X_ARITHMETIC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 13)) | ((value as u32 & 0x07) << 13); + self.w + } +} +#[doc = "Transmit Data Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum TXPO_A { + #[doc = "0: SERCOM PAD\\[0\\] +is used for data transmission"] + PAD0 = 0, + #[doc = "1: SERCOM PAD\\[2\\] +is used for data transmission"] + PAD2 = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: TXPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `TXPO` reader - Transmit Data Pinout"] +pub struct TXPO_R(crate::FieldReader); +impl TXPO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TXPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(TXPO_A::PAD0), + 1 => Some(TXPO_A::PAD2), + _ => None, + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == TXPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == TXPO_A::PAD2 + } +} +impl core::ops::Deref for TXPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXPO` writer - Transmit Data Pinout"] +pub struct TXPO_W<'a> { + w: &'a mut W, +} +impl<'a> TXPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TXPO_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "SERCOM PAD\\[0\\] +is used for data transmission"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(TXPO_A::PAD0) + } + #[doc = "SERCOM PAD\\[2\\] +is used for data transmission"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(TXPO_A::PAD2) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Receive Data Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum RXPO_A { + #[doc = "0: SERCOM PAD\\[0\\] +is used for data reception"] + PAD0 = 0, + #[doc = "1: SERCOM PAD\\[1\\] +is used for data reception"] + PAD1 = 1, + #[doc = "2: SERCOM PAD\\[2\\] +is used for data reception"] + PAD2 = 2, + #[doc = "3: SERCOM PAD\\[3\\] +is used for data reception"] + PAD3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RXPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `RXPO` reader - Receive Data Pinout"] +pub struct RXPO_R(crate::FieldReader); +impl RXPO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RXPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RXPO_A { + match self.bits { + 0 => RXPO_A::PAD0, + 1 => RXPO_A::PAD1, + 2 => RXPO_A::PAD2, + 3 => RXPO_A::PAD3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == RXPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD1`"] + #[inline(always)] + pub fn is_pad1(&self) -> bool { + **self == RXPO_A::PAD1 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == RXPO_A::PAD2 + } + #[doc = "Checks if the value of the field is `PAD3`"] + #[inline(always)] + pub fn is_pad3(&self) -> bool { + **self == RXPO_A::PAD3 + } +} +impl core::ops::Deref for RXPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXPO` writer - Receive Data Pinout"] +pub struct RXPO_W<'a> { + w: &'a mut W, +} +impl<'a> RXPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RXPO_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "SERCOM PAD\\[0\\] +is used for data reception"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(RXPO_A::PAD0) + } + #[doc = "SERCOM PAD\\[1\\] +is used for data reception"] + #[inline(always)] + pub fn pad1(self) -> &'a mut W { + self.variant(RXPO_A::PAD1) + } + #[doc = "SERCOM PAD\\[2\\] +is used for data reception"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(RXPO_A::PAD2) + } + #[doc = "SERCOM PAD\\[3\\] +is used for data reception"] + #[inline(always)] + pub fn pad3(self) -> &'a mut W { + self.variant(RXPO_A::PAD3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 20)) | ((value as u32 & 0x03) << 20); + self.w + } +} +#[doc = "Field `SAMPA` reader - Sample Adjustment"] +pub struct SAMPA_R(crate::FieldReader); +impl SAMPA_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SAMPA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SAMPA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SAMPA` writer - Sample Adjustment"] +pub struct SAMPA_W<'a> { + w: &'a mut W, +} +impl<'a> SAMPA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 22)) | ((value as u32 & 0x03) << 22); + self.w + } +} +#[doc = "Frame Format\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FORM_A { + #[doc = "0: USART frame"] + USART_FRAME_NO_PARITY = 0, + #[doc = "1: USART frame with parity"] + USART_FRAME_WITH_PARITY = 1, + #[doc = "2: LIN Master - Break and sync generation"] + USART_FRAME_LIN_MASTER_MODE = 2, + #[doc = "4: Auto-baud - break detection and auto-baud"] + USART_FRAME_AUTO_BAUD_NO_PARITY = 4, + #[doc = "5: Auto-baud - break detection and auto-baud with parity"] + USART_FRAME_AUTO_BAUD_WITH_PARITY = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FORM_A) -> Self { + variant as _ + } +} +#[doc = "Field `FORM` reader - Frame Format"] +pub struct FORM_R(crate::FieldReader); +impl FORM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FORM_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(FORM_A::USART_FRAME_NO_PARITY), + 1 => Some(FORM_A::USART_FRAME_WITH_PARITY), + 2 => Some(FORM_A::USART_FRAME_LIN_MASTER_MODE), + 4 => Some(FORM_A::USART_FRAME_AUTO_BAUD_NO_PARITY), + 5 => Some(FORM_A::USART_FRAME_AUTO_BAUD_WITH_PARITY), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_FRAME_NO_PARITY`"] + #[inline(always)] + pub fn is_usart_frame_no_parity(&self) -> bool { + **self == FORM_A::USART_FRAME_NO_PARITY + } + #[doc = "Checks if the value of the field is `USART_FRAME_WITH_PARITY`"] + #[inline(always)] + pub fn is_usart_frame_with_parity(&self) -> bool { + **self == FORM_A::USART_FRAME_WITH_PARITY + } + #[doc = "Checks if the value of the field is `USART_FRAME_LIN_MASTER_MODE`"] + #[inline(always)] + pub fn is_usart_frame_lin_master_mode(&self) -> bool { + **self == FORM_A::USART_FRAME_LIN_MASTER_MODE + } + #[doc = "Checks if the value of the field is `USART_FRAME_AUTO_BAUD_NO_PARITY`"] + #[inline(always)] + pub fn is_usart_frame_auto_baud_no_parity(&self) -> bool { + **self == FORM_A::USART_FRAME_AUTO_BAUD_NO_PARITY + } + #[doc = "Checks if the value of the field is `USART_FRAME_AUTO_BAUD_WITH_PARITY`"] + #[inline(always)] + pub fn is_usart_frame_auto_baud_with_parity(&self) -> bool { + **self == FORM_A::USART_FRAME_AUTO_BAUD_WITH_PARITY + } +} +impl core::ops::Deref for FORM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FORM` writer - Frame Format"] +pub struct FORM_W<'a> { + w: &'a mut W, +} +impl<'a> FORM_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FORM_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART frame"] + #[inline(always)] + pub fn usart_frame_no_parity(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_NO_PARITY) + } + #[doc = "USART frame with parity"] + #[inline(always)] + pub fn usart_frame_with_parity(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_WITH_PARITY) + } + #[doc = "LIN Master - Break and sync generation"] + #[inline(always)] + pub fn usart_frame_lin_master_mode(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_LIN_MASTER_MODE) + } + #[doc = "Auto-baud - break detection and auto-baud"] + #[inline(always)] + pub fn usart_frame_auto_baud_no_parity(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_AUTO_BAUD_NO_PARITY) + } + #[doc = "Auto-baud - break detection and auto-baud with parity"] + #[inline(always)] + pub fn usart_frame_auto_baud_with_parity(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_AUTO_BAUD_WITH_PARITY) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Communication Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CMODE_A { + #[doc = "0: Asynchronous Communication"] + ASYNC = 0, + #[doc = "1: Synchronous Communication"] + SYNC = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CMODE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CMODE` reader - Communication Mode"] +pub struct CMODE_R(crate::FieldReader); +impl CMODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CMODE_A { + match self.bits { + false => CMODE_A::ASYNC, + true => CMODE_A::SYNC, + } + } + #[doc = "Checks if the value of the field is `ASYNC`"] + #[inline(always)] + pub fn is_async(&self) -> bool { + **self == CMODE_A::ASYNC + } + #[doc = "Checks if the value of the field is `SYNC`"] + #[inline(always)] + pub fn is_sync(&self) -> bool { + **self == CMODE_A::SYNC + } +} +impl core::ops::Deref for CMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMODE` writer - Communication Mode"] +pub struct CMODE_W<'a> { + w: &'a mut W, +} +impl<'a> CMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMODE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Asynchronous Communication"] + #[inline(always)] + pub fn async_(self) -> &'a mut W { + self.variant(CMODE_A::ASYNC) + } + #[doc = "Synchronous Communication"] + #[inline(always)] + pub fn sync(self) -> &'a mut W { + self.variant(CMODE_A::SYNC) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Clock Polarity\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CPOL_A { + #[doc = "0: TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge"] + IDLE_LOW = 0, + #[doc = "1: TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge"] + IDLE_HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CPOL_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CPOL` reader - Clock Polarity"] +pub struct CPOL_R(crate::FieldReader); +impl CPOL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPOL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CPOL_A { + match self.bits { + false => CPOL_A::IDLE_LOW, + true => CPOL_A::IDLE_HIGH, + } + } + #[doc = "Checks if the value of the field is `IDLE_LOW`"] + #[inline(always)] + pub fn is_idle_low(&self) -> bool { + **self == CPOL_A::IDLE_LOW + } + #[doc = "Checks if the value of the field is `IDLE_HIGH`"] + #[inline(always)] + pub fn is_idle_high(&self) -> bool { + **self == CPOL_A::IDLE_HIGH + } +} +impl core::ops::Deref for CPOL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPOL` writer - Clock Polarity"] +pub struct CPOL_W<'a> { + w: &'a mut W, +} +impl<'a> CPOL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CPOL_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge"] + #[inline(always)] + pub fn idle_low(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_LOW) + } + #[doc = "TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge"] + #[inline(always)] + pub fn idle_high(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_HIGH) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29); + self.w + } +} +#[doc = "Data Order\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum DORD_A { + #[doc = "0: MSB is transmitted first"] + MSB = 0, + #[doc = "1: LSB is transmitted first"] + LSB = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DORD_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DORD` reader - Data Order"] +pub struct DORD_R(crate::FieldReader); +impl DORD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DORD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DORD_A { + match self.bits { + false => DORD_A::MSB, + true => DORD_A::LSB, + } + } + #[doc = "Checks if the value of the field is `MSB`"] + #[inline(always)] + pub fn is_msb(&self) -> bool { + **self == DORD_A::MSB + } + #[doc = "Checks if the value of the field is `LSB`"] + #[inline(always)] + pub fn is_lsb(&self) -> bool { + **self == DORD_A::LSB + } +} +impl core::ops::Deref for DORD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DORD` writer - Data Order"] +pub struct DORD_W<'a> { + w: &'a mut W, +} +impl<'a> DORD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DORD_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "MSB is transmitted first"] + #[inline(always)] + pub fn msb(self) -> &'a mut W { + self.variant(DORD_A::MSB) + } + #[doc = "LSB is transmitted first"] + #[inline(always)] + pub fn lsb(self) -> &'a mut W { + self.variant(DORD_A::LSB) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x07) as u8) + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&self) -> IBON_R { + IBON_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bits 13:15 - Sample"] + #[inline(always)] + pub fn sampr(&self) -> SAMPR_R { + SAMPR_R::new(((self.bits >> 13) & 0x07) as u8) + } + #[doc = "Bits 16:17 - Transmit Data Pinout"] + #[inline(always)] + pub fn txpo(&self) -> TXPO_R { + TXPO_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bits 20:21 - Receive Data Pinout"] + #[inline(always)] + pub fn rxpo(&self) -> RXPO_R { + RXPO_R::new(((self.bits >> 20) & 0x03) as u8) + } + #[doc = "Bits 22:23 - Sample Adjustment"] + #[inline(always)] + pub fn sampa(&self) -> SAMPA_R { + SAMPA_R::new(((self.bits >> 22) & 0x03) as u8) + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&self) -> FORM_R { + FORM_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 28 - Communication Mode"] + #[inline(always)] + pub fn cmode(&self) -> CMODE_R { + CMODE_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&self) -> CPOL_R { + CPOL_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&self) -> DORD_R { + DORD_R::new(((self.bits >> 30) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&mut self) -> IBON_W { + IBON_W { w: self } + } + #[doc = "Bits 13:15 - Sample"] + #[inline(always)] + pub fn sampr(&mut self) -> SAMPR_W { + SAMPR_W { w: self } + } + #[doc = "Bits 16:17 - Transmit Data Pinout"] + #[inline(always)] + pub fn txpo(&mut self) -> TXPO_W { + TXPO_W { w: self } + } + #[doc = "Bits 20:21 - Receive Data Pinout"] + #[inline(always)] + pub fn rxpo(&mut self) -> RXPO_W { + RXPO_W { w: self } + } + #[doc = "Bits 22:23 - Sample Adjustment"] + #[inline(always)] + pub fn sampa(&mut self) -> SAMPA_W { + SAMPA_W { w: self } + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&mut self) -> FORM_W { + FORM_W { w: self } + } + #[doc = "Bit 28 - Communication Mode"] + #[inline(always)] + pub fn cmode(&mut self) -> CMODE_W { + CMODE_W { w: self } + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&mut self) -> CPOL_W { + CPOL_W { w: self } + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&mut self) -> DORD_W { + DORD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sercom0/usart_ext/ctrlb.rs b/pac/atsamc21n/src/sercom0/usart_ext/ctrlb.rs new file mode 100644 index 000000000000..37567555e842 --- /dev/null +++ b/pac/atsamc21n/src/sercom0/usart_ext/ctrlb.rs @@ -0,0 +1,651 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Character Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CHSIZE_A { + #[doc = "0: 8 Bits"] + _8_BIT = 0, + #[doc = "1: 9 Bits"] + _9_BIT = 1, + #[doc = "5: 5 Bits"] + _5_BIT = 5, + #[doc = "6: 6 Bits"] + _6_BIT = 6, + #[doc = "7: 7 Bits"] + _7_BIT = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CHSIZE_A) -> Self { + variant as _ + } +} +#[doc = "Field `CHSIZE` reader - Character Size"] +pub struct CHSIZE_R(crate::FieldReader); +impl CHSIZE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CHSIZE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CHSIZE_A::_8_BIT), + 1 => Some(CHSIZE_A::_9_BIT), + 5 => Some(CHSIZE_A::_5_BIT), + 6 => Some(CHSIZE_A::_6_BIT), + 7 => Some(CHSIZE_A::_7_BIT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_8_BIT`"] + #[inline(always)] + pub fn is_8_bit(&self) -> bool { + **self == CHSIZE_A::_8_BIT + } + #[doc = "Checks if the value of the field is `_9_BIT`"] + #[inline(always)] + pub fn is_9_bit(&self) -> bool { + **self == CHSIZE_A::_9_BIT + } + #[doc = "Checks if the value of the field is `_5_BIT`"] + #[inline(always)] + pub fn is_5_bit(&self) -> bool { + **self == CHSIZE_A::_5_BIT + } + #[doc = "Checks if the value of the field is `_6_BIT`"] + #[inline(always)] + pub fn is_6_bit(&self) -> bool { + **self == CHSIZE_A::_6_BIT + } + #[doc = "Checks if the value of the field is `_7_BIT`"] + #[inline(always)] + pub fn is_7_bit(&self) -> bool { + **self == CHSIZE_A::_7_BIT + } +} +impl core::ops::Deref for CHSIZE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHSIZE` writer - Character Size"] +pub struct CHSIZE_W<'a> { + w: &'a mut W, +} +impl<'a> CHSIZE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CHSIZE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8 Bits"] + #[inline(always)] + pub fn _8_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_8_BIT) + } + #[doc = "9 Bits"] + #[inline(always)] + pub fn _9_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_9_BIT) + } + #[doc = "5 Bits"] + #[inline(always)] + pub fn _5_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_5_BIT) + } + #[doc = "6 Bits"] + #[inline(always)] + pub fn _6_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_6_BIT) + } + #[doc = "7 Bits"] + #[inline(always)] + pub fn _7_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_7_BIT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Stop Bit Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SBMODE_A { + #[doc = "0: One Stop Bit"] + _1_BIT = 0, + #[doc = "1: Two Stop Bits"] + _2_BIT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SBMODE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SBMODE` reader - Stop Bit Mode"] +pub struct SBMODE_R(crate::FieldReader); +impl SBMODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SBMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SBMODE_A { + match self.bits { + false => SBMODE_A::_1_BIT, + true => SBMODE_A::_2_BIT, + } + } + #[doc = "Checks if the value of the field is `_1_BIT`"] + #[inline(always)] + pub fn is_1_bit(&self) -> bool { + **self == SBMODE_A::_1_BIT + } + #[doc = "Checks if the value of the field is `_2_BIT`"] + #[inline(always)] + pub fn is_2_bit(&self) -> bool { + **self == SBMODE_A::_2_BIT + } +} +impl core::ops::Deref for SBMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SBMODE` writer - Stop Bit Mode"] +pub struct SBMODE_W<'a> { + w: &'a mut W, +} +impl<'a> SBMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SBMODE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "One Stop Bit"] + #[inline(always)] + pub fn _1_bit(self) -> &'a mut W { + self.variant(SBMODE_A::_1_BIT) + } + #[doc = "Two Stop Bits"] + #[inline(always)] + pub fn _2_bit(self) -> &'a mut W { + self.variant(SBMODE_A::_2_BIT) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `COLDEN` reader - Collision Detection Enable"] +pub struct COLDEN_R(crate::FieldReader); +impl COLDEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COLDEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COLDEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COLDEN` writer - Collision Detection Enable"] +pub struct COLDEN_W<'a> { + w: &'a mut W, +} +impl<'a> COLDEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `SFDE` reader - Start of Frame Detection Enable"] +pub struct SFDE_R(crate::FieldReader); +impl SFDE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SFDE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SFDE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SFDE` writer - Start of Frame Detection Enable"] +pub struct SFDE_W<'a> { + w: &'a mut W, +} +impl<'a> SFDE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `ENC` reader - Encoding Format"] +pub struct ENC_R(crate::FieldReader); +impl ENC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENC` writer - Encoding Format"] +pub struct ENC_W<'a> { + w: &'a mut W, +} +impl<'a> ENC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Parity Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PMODE_A { + #[doc = "0: Even Parity"] + EVEN = 0, + #[doc = "1: Odd Parity"] + ODD = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PMODE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PMODE` reader - Parity Mode"] +pub struct PMODE_R(crate::FieldReader); +impl PMODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PMODE_A { + match self.bits { + false => PMODE_A::EVEN, + true => PMODE_A::ODD, + } + } + #[doc = "Checks if the value of the field is `EVEN`"] + #[inline(always)] + pub fn is_even(&self) -> bool { + **self == PMODE_A::EVEN + } + #[doc = "Checks if the value of the field is `ODD`"] + #[inline(always)] + pub fn is_odd(&self) -> bool { + **self == PMODE_A::ODD + } +} +impl core::ops::Deref for PMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PMODE` writer - Parity Mode"] +pub struct PMODE_W<'a> { + w: &'a mut W, +} +impl<'a> PMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PMODE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Even Parity"] + #[inline(always)] + pub fn even(self) -> &'a mut W { + self.variant(PMODE_A::EVEN) + } + #[doc = "Odd Parity"] + #[inline(always)] + pub fn odd(self) -> &'a mut W { + self.variant(PMODE_A::ODD) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `TXEN` reader - Transmitter Enable"] +pub struct TXEN_R(crate::FieldReader); +impl TXEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXEN` writer - Transmitter Enable"] +pub struct TXEN_W<'a> { + w: &'a mut W, +} +impl<'a> TXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `RXEN` reader - Receiver Enable"] +pub struct RXEN_R(crate::FieldReader); +impl RXEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXEN` writer - Receiver Enable"] +pub struct RXEN_W<'a> { + w: &'a mut W, +} +impl<'a> RXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `LINCMD` reader - LIN Command"] +pub struct LINCMD_R(crate::FieldReader); +impl LINCMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LINCMD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LINCMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LINCMD` writer - LIN Command"] +pub struct LINCMD_W<'a> { + w: &'a mut W, +} +impl<'a> LINCMD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 24)) | ((value as u32 & 0x03) << 24); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&self) -> CHSIZE_R { + CHSIZE_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 6 - Stop Bit Mode"] + #[inline(always)] + pub fn sbmode(&self) -> SBMODE_R { + SBMODE_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 8 - Collision Detection Enable"] + #[inline(always)] + pub fn colden(&self) -> COLDEN_R { + COLDEN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Start of Frame Detection Enable"] + #[inline(always)] + pub fn sfde(&self) -> SFDE_R { + SFDE_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Encoding Format"] + #[inline(always)] + pub fn enc(&self) -> ENC_R { + ENC_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 13 - Parity Mode"] + #[inline(always)] + pub fn pmode(&self) -> PMODE_R { + PMODE_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 16 - Transmitter Enable"] + #[inline(always)] + pub fn txen(&self) -> TXEN_R { + TXEN_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&self) -> RXEN_R { + RXEN_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bits 24:25 - LIN Command"] + #[inline(always)] + pub fn lincmd(&self) -> LINCMD_R { + LINCMD_R::new(((self.bits >> 24) & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&mut self) -> CHSIZE_W { + CHSIZE_W { w: self } + } + #[doc = "Bit 6 - Stop Bit Mode"] + #[inline(always)] + pub fn sbmode(&mut self) -> SBMODE_W { + SBMODE_W { w: self } + } + #[doc = "Bit 8 - Collision Detection Enable"] + #[inline(always)] + pub fn colden(&mut self) -> COLDEN_W { + COLDEN_W { w: self } + } + #[doc = "Bit 9 - Start of Frame Detection Enable"] + #[inline(always)] + pub fn sfde(&mut self) -> SFDE_W { + SFDE_W { w: self } + } + #[doc = "Bit 10 - Encoding Format"] + #[inline(always)] + pub fn enc(&mut self) -> ENC_W { + ENC_W { w: self } + } + #[doc = "Bit 13 - Parity Mode"] + #[inline(always)] + pub fn pmode(&mut self) -> PMODE_W { + PMODE_W { w: self } + } + #[doc = "Bit 16 - Transmitter Enable"] + #[inline(always)] + pub fn txen(&mut self) -> TXEN_W { + TXEN_W { w: self } + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&mut self) -> RXEN_W { + RXEN_W { w: self } + } + #[doc = "Bits 24:25 - LIN Command"] + #[inline(always)] + pub fn lincmd(&mut self) -> LINCMD_W { + LINCMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sercom0/usart_ext/ctrlc.rs b/pac/atsamc21n/src/sercom0/usart_ext/ctrlc.rs new file mode 100644 index 000000000000..5840d5c3bd06 --- /dev/null +++ b/pac/atsamc21n/src/sercom0/usart_ext/ctrlc.rs @@ -0,0 +1,177 @@ +#[doc = "Register `CTRLC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `GTIME` reader - RS485 Guard Time"] +pub struct GTIME_R(crate::FieldReader); +impl GTIME_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + GTIME_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GTIME_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GTIME` writer - RS485 Guard Time"] +pub struct GTIME_W<'a> { + w: &'a mut W, +} +impl<'a> GTIME_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Field `BRKLEN` reader - LIN Master Break Length"] +pub struct BRKLEN_R(crate::FieldReader); +impl BRKLEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BRKLEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BRKLEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BRKLEN` writer - LIN Master Break Length"] +pub struct BRKLEN_W<'a> { + w: &'a mut W, +} +impl<'a> BRKLEN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 8)) | ((value as u32 & 0x03) << 8); + self.w + } +} +#[doc = "Field `HDRDLY` reader - LIN Master Header Delay"] +pub struct HDRDLY_R(crate::FieldReader); +impl HDRDLY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + HDRDLY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HDRDLY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HDRDLY` writer - LIN Master Header Delay"] +pub struct HDRDLY_W<'a> { + w: &'a mut W, +} +impl<'a> HDRDLY_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 10)) | ((value as u32 & 0x03) << 10); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - RS485 Guard Time"] + #[inline(always)] + pub fn gtime(&self) -> GTIME_R { + GTIME_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bits 8:9 - LIN Master Break Length"] + #[inline(always)] + pub fn brklen(&self) -> BRKLEN_R { + BRKLEN_R::new(((self.bits >> 8) & 0x03) as u8) + } + #[doc = "Bits 10:11 - LIN Master Header Delay"] + #[inline(always)] + pub fn hdrdly(&self) -> HDRDLY_R { + HDRDLY_R::new(((self.bits >> 10) & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - RS485 Guard Time"] + #[inline(always)] + pub fn gtime(&mut self) -> GTIME_W { + GTIME_W { w: self } + } + #[doc = "Bits 8:9 - LIN Master Break Length"] + #[inline(always)] + pub fn brklen(&mut self) -> BRKLEN_W { + BRKLEN_W { w: self } + } + #[doc = "Bits 10:11 - LIN Master Header Delay"] + #[inline(always)] + pub fn hdrdly(&mut self) -> HDRDLY_W { + HDRDLY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Control C\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlc](index.html) module"] +pub struct CTRLC_SPEC; +impl crate::RegisterSpec for CTRLC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlc::R](R) reader structure"] +impl crate::Readable for CTRLC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlc::W](W) writer structure"] +impl crate::Writable for CTRLC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLC to value 0"] +impl crate::Resettable for CTRLC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sercom0/usart_ext/data.rs b/pac/atsamc21n/src/sercom0/usart_ext/data.rs new file mode 100644 index 000000000000..a54152c9571a --- /dev/null +++ b/pac/atsamc21n/src/sercom0/usart_ext/data.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data Value"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data Value"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01ff) | (value as u16 & 0x01ff); + self.w + } +} +impl R { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new((self.bits & 0x01ff) as u16) + } +} +impl W { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sercom0/usart_ext/dbgctrl.rs b/pac/atsamc21n/src/sercom0/usart_ext/dbgctrl.rs new file mode 100644 index 000000000000..6c844f3fe40d --- /dev/null +++ b/pac/atsamc21n/src/sercom0/usart_ext/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGSTOP` reader - Debug Mode"] +pub struct DBGSTOP_R(crate::FieldReader); +impl DBGSTOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGSTOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGSTOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGSTOP` writer - Debug Mode"] +pub struct DBGSTOP_W<'a> { + w: &'a mut W, +} +impl<'a> DBGSTOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&self) -> DBGSTOP_R { + DBGSTOP_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&mut self) -> DBGSTOP_W { + DBGSTOP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sercom0/usart_ext/intenclr.rs b/pac/atsamc21n/src/sercom0/usart_ext/intenclr.rs new file mode 100644 index 000000000000..a815553ce666 --- /dev/null +++ b/pac/atsamc21n/src/sercom0/usart_ext/intenclr.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Disable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Disable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Disable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Disable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Disable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Disable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RXS` reader - Receive Start Interrupt Disable"] +pub struct RXS_R(crate::FieldReader); +impl RXS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXS` writer - Receive Start Interrupt Disable"] +pub struct RXS_W<'a> { + w: &'a mut W, +} +impl<'a> RXS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CTSIC` reader - Clear To Send Input Change Interrupt Disable"] +pub struct CTSIC_R(crate::FieldReader); +impl CTSIC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTSIC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTSIC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTSIC` writer - Clear To Send Input Change Interrupt Disable"] +pub struct CTSIC_W<'a> { + w: &'a mut W, +} +impl<'a> CTSIC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RXBRK` reader - Break Received Interrupt Disable"] +pub struct RXBRK_R(crate::FieldReader); +impl RXBRK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXBRK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXBRK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXBRK` writer - Break Received Interrupt Disable"] +pub struct RXBRK_W<'a> { + w: &'a mut W, +} +impl<'a> RXBRK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Disable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Disable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Receive Start Interrupt Disable"] + #[inline(always)] + pub fn rxs(&self) -> RXS_R { + RXS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Disable"] + #[inline(always)] + pub fn ctsic(&self) -> CTSIC_R { + CTSIC_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Break Received Interrupt Disable"] + #[inline(always)] + pub fn rxbrk(&self) -> RXBRK_R { + RXBRK_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Receive Start Interrupt Disable"] + #[inline(always)] + pub fn rxs(&mut self) -> RXS_W { + RXS_W { w: self } + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Disable"] + #[inline(always)] + pub fn ctsic(&mut self) -> CTSIC_W { + CTSIC_W { w: self } + } + #[doc = "Bit 5 - Break Received Interrupt Disable"] + #[inline(always)] + pub fn rxbrk(&mut self) -> RXBRK_W { + RXBRK_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sercom0/usart_ext/intenset.rs b/pac/atsamc21n/src/sercom0/usart_ext/intenset.rs new file mode 100644 index 000000000000..e800681cf423 --- /dev/null +++ b/pac/atsamc21n/src/sercom0/usart_ext/intenset.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Enable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Enable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Enable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Enable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Enable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Enable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RXS` reader - Receive Start Interrupt Enable"] +pub struct RXS_R(crate::FieldReader); +impl RXS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXS` writer - Receive Start Interrupt Enable"] +pub struct RXS_W<'a> { + w: &'a mut W, +} +impl<'a> RXS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CTSIC` reader - Clear To Send Input Change Interrupt Enable"] +pub struct CTSIC_R(crate::FieldReader); +impl CTSIC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTSIC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTSIC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTSIC` writer - Clear To Send Input Change Interrupt Enable"] +pub struct CTSIC_W<'a> { + w: &'a mut W, +} +impl<'a> CTSIC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RXBRK` reader - Break Received Interrupt Enable"] +pub struct RXBRK_R(crate::FieldReader); +impl RXBRK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXBRK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXBRK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXBRK` writer - Break Received Interrupt Enable"] +pub struct RXBRK_W<'a> { + w: &'a mut W, +} +impl<'a> RXBRK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Receive Start Interrupt Enable"] + #[inline(always)] + pub fn rxs(&self) -> RXS_R { + RXS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Enable"] + #[inline(always)] + pub fn ctsic(&self) -> CTSIC_R { + CTSIC_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Break Received Interrupt Enable"] + #[inline(always)] + pub fn rxbrk(&self) -> RXBRK_R { + RXBRK_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Receive Start Interrupt Enable"] + #[inline(always)] + pub fn rxs(&mut self) -> RXS_W { + RXS_W { w: self } + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Enable"] + #[inline(always)] + pub fn ctsic(&mut self) -> CTSIC_W { + CTSIC_W { w: self } + } + #[doc = "Bit 5 - Break Received Interrupt Enable"] + #[inline(always)] + pub fn rxbrk(&mut self) -> RXBRK_W { + RXBRK_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sercom0/usart_ext/intflag.rs b/pac/atsamc21n/src/sercom0/usart_ext/intflag.rs new file mode 100644 index 000000000000..4b0be279a9ae --- /dev/null +++ b/pac/atsamc21n/src/sercom0/usart_ext/intflag.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RXS` reader - Receive Start Interrupt"] +pub struct RXS_R(crate::FieldReader); +impl RXS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXS` writer - Receive Start Interrupt"] +pub struct RXS_W<'a> { + w: &'a mut W, +} +impl<'a> RXS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CTSIC` reader - Clear To Send Input Change Interrupt"] +pub struct CTSIC_R(crate::FieldReader); +impl CTSIC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTSIC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTSIC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTSIC` writer - Clear To Send Input Change Interrupt"] +pub struct CTSIC_W<'a> { + w: &'a mut W, +} +impl<'a> CTSIC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RXBRK` reader - Break Received Interrupt"] +pub struct RXBRK_R(crate::FieldReader); +impl RXBRK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXBRK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXBRK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXBRK` writer - Break Received Interrupt"] +pub struct RXBRK_W<'a> { + w: &'a mut W, +} +impl<'a> RXBRK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Receive Start Interrupt"] + #[inline(always)] + pub fn rxs(&self) -> RXS_R { + RXS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt"] + #[inline(always)] + pub fn ctsic(&self) -> CTSIC_R { + CTSIC_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Break Received Interrupt"] + #[inline(always)] + pub fn rxbrk(&self) -> RXBRK_R { + RXBRK_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Receive Start Interrupt"] + #[inline(always)] + pub fn rxs(&mut self) -> RXS_W { + RXS_W { w: self } + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt"] + #[inline(always)] + pub fn ctsic(&mut self) -> CTSIC_W { + CTSIC_W { w: self } + } + #[doc = "Bit 5 - Break Received Interrupt"] + #[inline(always)] + pub fn rxbrk(&mut self) -> RXBRK_W { + RXBRK_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sercom0/usart_ext/rxpl.rs b/pac/atsamc21n/src/sercom0/usart_ext/rxpl.rs new file mode 100644 index 000000000000..174464dc16b5 --- /dev/null +++ b/pac/atsamc21n/src/sercom0/usart_ext/rxpl.rs @@ -0,0 +1,103 @@ +#[doc = "Register `RXPL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RXPL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RXPL` reader - Receive Pulse Length"] +pub struct RXPL_R(crate::FieldReader); +impl RXPL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RXPL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXPL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXPL` writer - Receive Pulse Length"] +pub struct RXPL_W<'a> { + w: &'a mut W, +} +impl<'a> RXPL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Receive Pulse Length"] + #[inline(always)] + pub fn rxpl(&self) -> RXPL_R { + RXPL_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Receive Pulse Length"] + #[inline(always)] + pub fn rxpl(&mut self) -> RXPL_W { + RXPL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Receive Pulse Length\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxpl](index.html) module"] +pub struct RXPL_SPEC; +impl crate::RegisterSpec for RXPL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [rxpl::R](R) reader structure"] +impl crate::Readable for RXPL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rxpl::W](W) writer structure"] +impl crate::Writable for RXPL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RXPL to value 0"] +impl crate::Resettable for RXPL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sercom0/usart_ext/status.rs b/pac/atsamc21n/src/sercom0/usart_ext/status.rs new file mode 100644 index 000000000000..a0c50c1bc2cf --- /dev/null +++ b/pac/atsamc21n/src/sercom0/usart_ext/status.rs @@ -0,0 +1,395 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PERR` reader - Parity Error"] +pub struct PERR_R(crate::FieldReader); +impl PERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERR` writer - Parity Error"] +pub struct PERR_W<'a> { + w: &'a mut W, +} +impl<'a> PERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `FERR` reader - Frame Error"] +pub struct FERR_R(crate::FieldReader); +impl FERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FERR` writer - Frame Error"] +pub struct FERR_W<'a> { + w: &'a mut W, +} +impl<'a> FERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `BUFOVF` reader - Buffer Overflow"] +pub struct BUFOVF_R(crate::FieldReader); +impl BUFOVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUFOVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUFOVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUFOVF` writer - Buffer Overflow"] +pub struct BUFOVF_W<'a> { + w: &'a mut W, +} +impl<'a> BUFOVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CTS` reader - Clear To Send"] +pub struct CTS_R(crate::FieldReader); +impl CTS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTS` writer - Clear To Send"] +pub struct CTS_W<'a> { + w: &'a mut W, +} +impl<'a> CTS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ISF` reader - Inconsistent Sync Field"] +pub struct ISF_R(crate::FieldReader); +impl ISF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ISF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ISF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ISF` writer - Inconsistent Sync Field"] +pub struct ISF_W<'a> { + w: &'a mut W, +} +impl<'a> ISF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `COLL` reader - Collision Detected"] +pub struct COLL_R(crate::FieldReader); +impl COLL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COLL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COLL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COLL` writer - Collision Detected"] +pub struct COLL_W<'a> { + w: &'a mut W, +} +impl<'a> COLL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `TXE` reader - Transmitter Empty"] +pub struct TXE_R(crate::FieldReader); +impl TXE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXE` writer - Transmitter Empty"] +pub struct TXE_W<'a> { + w: &'a mut W, +} +impl<'a> TXE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - Parity Error"] + #[inline(always)] + pub fn perr(&self) -> PERR_R { + PERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Frame Error"] + #[inline(always)] + pub fn ferr(&self) -> FERR_R { + FERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&self) -> BUFOVF_R { + BUFOVF_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Clear To Send"] + #[inline(always)] + pub fn cts(&self) -> CTS_R { + CTS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Inconsistent Sync Field"] + #[inline(always)] + pub fn isf(&self) -> ISF_R { + ISF_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Collision Detected"] + #[inline(always)] + pub fn coll(&self) -> COLL_R { + COLL_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Transmitter Empty"] + #[inline(always)] + pub fn txe(&self) -> TXE_R { + TXE_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Parity Error"] + #[inline(always)] + pub fn perr(&mut self) -> PERR_W { + PERR_W { w: self } + } + #[doc = "Bit 1 - Frame Error"] + #[inline(always)] + pub fn ferr(&mut self) -> FERR_W { + FERR_W { w: self } + } + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&mut self) -> BUFOVF_W { + BUFOVF_W { w: self } + } + #[doc = "Bit 3 - Clear To Send"] + #[inline(always)] + pub fn cts(&mut self) -> CTS_W { + CTS_W { w: self } + } + #[doc = "Bit 4 - Inconsistent Sync Field"] + #[inline(always)] + pub fn isf(&mut self) -> ISF_W { + ISF_W { w: self } + } + #[doc = "Bit 5 - Collision Detected"] + #[inline(always)] + pub fn coll(&mut self) -> COLL_W { + COLL_W { w: self } + } + #[doc = "Bit 6 - Transmitter Empty"] + #[inline(always)] + pub fn txe(&mut self) -> TXE_W { + TXE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_EXT Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sercom0/usart_ext/syncbusy.rs b/pac/atsamc21n/src/sercom0/usart_ext/syncbusy.rs new file mode 100644 index 000000000000..7c3b817bbb04 --- /dev/null +++ b/pac/atsamc21n/src/sercom0/usart_ext/syncbusy.rs @@ -0,0 +1,93 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - SERCOM Enable Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLB` reader - CTRLB Synchronization Busy"] +pub struct CTRLB_R(crate::FieldReader); +impl CTRLB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM Enable Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - CTRLB Synchronization Busy"] + #[inline(always)] + pub fn ctrlb(&self) -> CTRLB_R { + CTRLB_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +#[doc = "USART_EXT Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sercom0/usart_int.rs b/pac/atsamc21n/src/sercom0/usart_int.rs new file mode 100644 index 000000000000..157c8c4b4fdc --- /dev/null +++ b/pac/atsamc21n/src/sercom0/usart_int.rs @@ -0,0 +1,60 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "USART_INT Control A"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "USART_INT Control B"] +pub mod ctrlb; +#[doc = "CTRLC register accessor: an alias for `Reg`"] +pub type CTRLC = crate::Reg; +#[doc = "USART_INT Control C"] +pub mod ctrlc; +#[doc = "BAUD register accessor: an alias for `Reg`"] +pub type BAUD = crate::Reg; +#[doc = "USART_INT Baud Rate"] +pub mod baud; +#[doc = "BAUD_FRAC_MODE register accessor: an alias for `Reg`"] +pub type BAUD_FRAC_MODE = crate::Reg; +#[doc = "USART_INT Baud Rate"] +pub mod baud_frac_mode; +#[doc = "BAUD_FRACFP_MODE register accessor: an alias for `Reg`"] +pub type BAUD_FRACFP_MODE = crate::Reg; +#[doc = "USART_INT Baud Rate"] +pub mod baud_fracfp_mode; +#[doc = "BAUD_USARTFP_MODE register accessor: an alias for `Reg`"] +pub type BAUD_USARTFP_MODE = crate::Reg; +#[doc = "USART_INT Baud Rate"] +pub mod baud_usartfp_mode; +#[doc = "RXPL register accessor: an alias for `Reg`"] +pub type RXPL = crate::Reg; +#[doc = "USART_INT Receive Pulse Length"] +pub mod rxpl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "USART_INT Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "USART_INT Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "USART_INT Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "USART_INT Status"] +pub mod status; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "USART_INT Synchronization Busy"] +pub mod syncbusy; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "USART_INT Data"] +pub mod data; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "USART_INT Debug Control"] +pub mod dbgctrl; diff --git a/pac/atsamc21n/src/sercom0/usart_int/baud.rs b/pac/atsamc21n/src/sercom0/usart_int/baud.rs new file mode 100644 index 000000000000..a82df20712b3 --- /dev/null +++ b/pac/atsamc21n/src/sercom0/usart_int/baud.rs @@ -0,0 +1,103 @@ +#[doc = "Register `BAUD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud](index.html) module"] +pub struct BAUD_SPEC; +impl crate::RegisterSpec for BAUD_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud::R](R) reader structure"] +impl crate::Readable for BAUD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud::W](W) writer structure"] +impl crate::Writable for BAUD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD to value 0"] +impl crate::Resettable for BAUD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sercom0/usart_int/baud_frac_mode.rs b/pac/atsamc21n/src/sercom0/usart_int/baud_frac_mode.rs new file mode 100644 index 000000000000..b9c7fa4c4b2a --- /dev/null +++ b/pac/atsamc21n/src/sercom0/usart_int/baud_frac_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `BAUD_FRAC_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD_FRAC_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1fff) | (value as u16 & 0x1fff); + self.w + } +} +#[doc = "Field `FP` reader - Fractional Part"] +pub struct FP_R(crate::FieldReader); +impl FP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FP` writer - Fractional Part"] +pub struct FP_W<'a> { + w: &'a mut W, +} +impl<'a> FP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 13)) | ((value as u16 & 0x07) << 13); + self.w + } +} +impl R { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new((self.bits & 0x1fff) as u16) + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&self) -> FP_R { + FP_R::new(((self.bits >> 13) & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&mut self) -> FP_W { + FP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud_frac_mode](index.html) module"] +pub struct BAUD_FRAC_MODE_SPEC; +impl crate::RegisterSpec for BAUD_FRAC_MODE_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud_frac_mode::R](R) reader structure"] +impl crate::Readable for BAUD_FRAC_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud_frac_mode::W](W) writer structure"] +impl crate::Writable for BAUD_FRAC_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD_FRAC_MODE to value 0"] +impl crate::Resettable for BAUD_FRAC_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sercom0/usart_int/baud_fracfp_mode.rs b/pac/atsamc21n/src/sercom0/usart_int/baud_fracfp_mode.rs new file mode 100644 index 000000000000..0671db99cc9d --- /dev/null +++ b/pac/atsamc21n/src/sercom0/usart_int/baud_fracfp_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `BAUD_FRACFP_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD_FRACFP_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1fff) | (value as u16 & 0x1fff); + self.w + } +} +#[doc = "Field `FP` reader - Fractional Part"] +pub struct FP_R(crate::FieldReader); +impl FP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FP` writer - Fractional Part"] +pub struct FP_W<'a> { + w: &'a mut W, +} +impl<'a> FP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 13)) | ((value as u16 & 0x07) << 13); + self.w + } +} +impl R { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new((self.bits & 0x1fff) as u16) + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&self) -> FP_R { + FP_R::new(((self.bits >> 13) & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&mut self) -> FP_W { + FP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud_fracfp_mode](index.html) module"] +pub struct BAUD_FRACFP_MODE_SPEC; +impl crate::RegisterSpec for BAUD_FRACFP_MODE_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud_fracfp_mode::R](R) reader structure"] +impl crate::Readable for BAUD_FRACFP_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud_fracfp_mode::W](W) writer structure"] +impl crate::Writable for BAUD_FRACFP_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD_FRACFP_MODE to value 0"] +impl crate::Resettable for BAUD_FRACFP_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sercom0/usart_int/baud_usartfp_mode.rs b/pac/atsamc21n/src/sercom0/usart_int/baud_usartfp_mode.rs new file mode 100644 index 000000000000..b49a7ef5b84c --- /dev/null +++ b/pac/atsamc21n/src/sercom0/usart_int/baud_usartfp_mode.rs @@ -0,0 +1,103 @@ +#[doc = "Register `BAUD_USARTFP_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD_USARTFP_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud_usartfp_mode](index.html) module"] +pub struct BAUD_USARTFP_MODE_SPEC; +impl crate::RegisterSpec for BAUD_USARTFP_MODE_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud_usartfp_mode::R](R) reader structure"] +impl crate::Readable for BAUD_USARTFP_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud_usartfp_mode::W](W) writer structure"] +impl crate::Writable for BAUD_USARTFP_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD_USARTFP_MODE to value 0"] +impl crate::Resettable for BAUD_USARTFP_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sercom0/usart_int/ctrla.rs b/pac/atsamc21n/src/sercom0/usart_int/ctrla.rs new file mode 100644 index 000000000000..19d10ecf8e8f --- /dev/null +++ b/pac/atsamc21n/src/sercom0/usart_int/ctrla.rs @@ -0,0 +1,1171 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: USART with external clock"] + USART_EXT_CLK = 0, + #[doc = "1: USART with internal clock"] + USART_INT_CLK = 1, + #[doc = "2: SPI in slave operation"] + SPI_SLAVE = 2, + #[doc = "3: SPI in master operation"] + SPI_MASTER = 3, + #[doc = "4: I2C slave operation"] + I2C_SLAVE = 4, + #[doc = "5: I2C master operation"] + I2C_MASTER = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::USART_EXT_CLK), + 1 => Some(MODE_A::USART_INT_CLK), + 2 => Some(MODE_A::SPI_SLAVE), + 3 => Some(MODE_A::SPI_MASTER), + 4 => Some(MODE_A::I2C_SLAVE), + 5 => Some(MODE_A::I2C_MASTER), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_EXT_CLK`"] + #[inline(always)] + pub fn is_usart_ext_clk(&self) -> bool { + **self == MODE_A::USART_EXT_CLK + } + #[doc = "Checks if the value of the field is `USART_INT_CLK`"] + #[inline(always)] + pub fn is_usart_int_clk(&self) -> bool { + **self == MODE_A::USART_INT_CLK + } + #[doc = "Checks if the value of the field is `SPI_SLAVE`"] + #[inline(always)] + pub fn is_spi_slave(&self) -> bool { + **self == MODE_A::SPI_SLAVE + } + #[doc = "Checks if the value of the field is `SPI_MASTER`"] + #[inline(always)] + pub fn is_spi_master(&self) -> bool { + **self == MODE_A::SPI_MASTER + } + #[doc = "Checks if the value of the field is `I2C_SLAVE`"] + #[inline(always)] + pub fn is_i2c_slave(&self) -> bool { + **self == MODE_A::I2C_SLAVE + } + #[doc = "Checks if the value of the field is `I2C_MASTER`"] + #[inline(always)] + pub fn is_i2c_master(&self) -> bool { + **self == MODE_A::I2C_MASTER + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART with external clock"] + #[inline(always)] + pub fn usart_ext_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_EXT_CLK) + } + #[doc = "USART with internal clock"] + #[inline(always)] + pub fn usart_int_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_INT_CLK) + } + #[doc = "SPI in slave operation"] + #[inline(always)] + pub fn spi_slave(self) -> &'a mut W { + self.variant(MODE_A::SPI_SLAVE) + } + #[doc = "SPI in master operation"] + #[inline(always)] + pub fn spi_master(self) -> &'a mut W { + self.variant(MODE_A::SPI_MASTER) + } + #[doc = "I2C slave operation"] + #[inline(always)] + pub fn i2c_slave(self) -> &'a mut W { + self.variant(MODE_A::I2C_SLAVE) + } + #[doc = "I2C master operation"] + #[inline(always)] + pub fn i2c_master(self) -> &'a mut W { + self.variant(MODE_A::I2C_MASTER) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 2)) | ((value as u32 & 0x07) << 2); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `IBON` reader - Immediate Buffer Overflow Notification"] +pub struct IBON_R(crate::FieldReader); +impl IBON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IBON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IBON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IBON` writer - Immediate Buffer Overflow Notification"] +pub struct IBON_W<'a> { + w: &'a mut W, +} +impl<'a> IBON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Sample\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SAMPR_A { + #[doc = "0: 16x over-sampling using arithmetic baudrate generation"] + _16X_ARITHMETIC = 0, + #[doc = "1: 16x over-sampling using fractional baudrate generation"] + _16X_FRACTIONAL = 1, + #[doc = "2: 8x over-sampling using arithmetic baudrate generation"] + _8X_ARITHMETIC = 2, + #[doc = "3: 8x over-sampling using fractional baudrate generation"] + _8X_FRACTIONAL = 3, + #[doc = "4: 3x over-sampling using arithmetic baudrate generation"] + _3X_ARITHMETIC = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SAMPR_A) -> Self { + variant as _ + } +} +#[doc = "Field `SAMPR` reader - Sample"] +pub struct SAMPR_R(crate::FieldReader); +impl SAMPR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SAMPR_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SAMPR_A::_16X_ARITHMETIC), + 1 => Some(SAMPR_A::_16X_FRACTIONAL), + 2 => Some(SAMPR_A::_8X_ARITHMETIC), + 3 => Some(SAMPR_A::_8X_FRACTIONAL), + 4 => Some(SAMPR_A::_3X_ARITHMETIC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_16X_ARITHMETIC`"] + #[inline(always)] + pub fn is_16x_arithmetic(&self) -> bool { + **self == SAMPR_A::_16X_ARITHMETIC + } + #[doc = "Checks if the value of the field is `_16X_FRACTIONAL`"] + #[inline(always)] + pub fn is_16x_fractional(&self) -> bool { + **self == SAMPR_A::_16X_FRACTIONAL + } + #[doc = "Checks if the value of the field is `_8X_ARITHMETIC`"] + #[inline(always)] + pub fn is_8x_arithmetic(&self) -> bool { + **self == SAMPR_A::_8X_ARITHMETIC + } + #[doc = "Checks if the value of the field is `_8X_FRACTIONAL`"] + #[inline(always)] + pub fn is_8x_fractional(&self) -> bool { + **self == SAMPR_A::_8X_FRACTIONAL + } + #[doc = "Checks if the value of the field is `_3X_ARITHMETIC`"] + #[inline(always)] + pub fn is_3x_arithmetic(&self) -> bool { + **self == SAMPR_A::_3X_ARITHMETIC + } +} +impl core::ops::Deref for SAMPR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SAMPR` writer - Sample"] +pub struct SAMPR_W<'a> { + w: &'a mut W, +} +impl<'a> SAMPR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SAMPR_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "16x over-sampling using arithmetic baudrate generation"] + #[inline(always)] + pub fn _16x_arithmetic(self) -> &'a mut W { + self.variant(SAMPR_A::_16X_ARITHMETIC) + } + #[doc = "16x over-sampling using fractional baudrate generation"] + #[inline(always)] + pub fn _16x_fractional(self) -> &'a mut W { + self.variant(SAMPR_A::_16X_FRACTIONAL) + } + #[doc = "8x over-sampling using arithmetic baudrate generation"] + #[inline(always)] + pub fn _8x_arithmetic(self) -> &'a mut W { + self.variant(SAMPR_A::_8X_ARITHMETIC) + } + #[doc = "8x over-sampling using fractional baudrate generation"] + #[inline(always)] + pub fn _8x_fractional(self) -> &'a mut W { + self.variant(SAMPR_A::_8X_FRACTIONAL) + } + #[doc = "3x over-sampling using arithmetic baudrate generation"] + #[inline(always)] + pub fn _3x_arithmetic(self) -> &'a mut W { + self.variant(SAMPR_A::_3X_ARITHMETIC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 13)) | ((value as u32 & 0x07) << 13); + self.w + } +} +#[doc = "Transmit Data Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum TXPO_A { + #[doc = "0: SERCOM PAD\\[0\\] +is used for data transmission"] + PAD0 = 0, + #[doc = "1: SERCOM PAD\\[2\\] +is used for data transmission"] + PAD2 = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: TXPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `TXPO` reader - Transmit Data Pinout"] +pub struct TXPO_R(crate::FieldReader); +impl TXPO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TXPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(TXPO_A::PAD0), + 1 => Some(TXPO_A::PAD2), + _ => None, + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == TXPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == TXPO_A::PAD2 + } +} +impl core::ops::Deref for TXPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXPO` writer - Transmit Data Pinout"] +pub struct TXPO_W<'a> { + w: &'a mut W, +} +impl<'a> TXPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TXPO_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "SERCOM PAD\\[0\\] +is used for data transmission"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(TXPO_A::PAD0) + } + #[doc = "SERCOM PAD\\[2\\] +is used for data transmission"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(TXPO_A::PAD2) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Receive Data Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum RXPO_A { + #[doc = "0: SERCOM PAD\\[0\\] +is used for data reception"] + PAD0 = 0, + #[doc = "1: SERCOM PAD\\[1\\] +is used for data reception"] + PAD1 = 1, + #[doc = "2: SERCOM PAD\\[2\\] +is used for data reception"] + PAD2 = 2, + #[doc = "3: SERCOM PAD\\[3\\] +is used for data reception"] + PAD3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RXPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `RXPO` reader - Receive Data Pinout"] +pub struct RXPO_R(crate::FieldReader); +impl RXPO_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RXPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RXPO_A { + match self.bits { + 0 => RXPO_A::PAD0, + 1 => RXPO_A::PAD1, + 2 => RXPO_A::PAD2, + 3 => RXPO_A::PAD3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == RXPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD1`"] + #[inline(always)] + pub fn is_pad1(&self) -> bool { + **self == RXPO_A::PAD1 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == RXPO_A::PAD2 + } + #[doc = "Checks if the value of the field is `PAD3`"] + #[inline(always)] + pub fn is_pad3(&self) -> bool { + **self == RXPO_A::PAD3 + } +} +impl core::ops::Deref for RXPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXPO` writer - Receive Data Pinout"] +pub struct RXPO_W<'a> { + w: &'a mut W, +} +impl<'a> RXPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RXPO_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "SERCOM PAD\\[0\\] +is used for data reception"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(RXPO_A::PAD0) + } + #[doc = "SERCOM PAD\\[1\\] +is used for data reception"] + #[inline(always)] + pub fn pad1(self) -> &'a mut W { + self.variant(RXPO_A::PAD1) + } + #[doc = "SERCOM PAD\\[2\\] +is used for data reception"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(RXPO_A::PAD2) + } + #[doc = "SERCOM PAD\\[3\\] +is used for data reception"] + #[inline(always)] + pub fn pad3(self) -> &'a mut W { + self.variant(RXPO_A::PAD3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 20)) | ((value as u32 & 0x03) << 20); + self.w + } +} +#[doc = "Field `SAMPA` reader - Sample Adjustment"] +pub struct SAMPA_R(crate::FieldReader); +impl SAMPA_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SAMPA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SAMPA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SAMPA` writer - Sample Adjustment"] +pub struct SAMPA_W<'a> { + w: &'a mut W, +} +impl<'a> SAMPA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 22)) | ((value as u32 & 0x03) << 22); + self.w + } +} +#[doc = "Frame Format\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FORM_A { + #[doc = "0: USART frame"] + USART_FRAME_NO_PARITY = 0, + #[doc = "1: USART frame with parity"] + USART_FRAME_WITH_PARITY = 1, + #[doc = "2: LIN Master - Break and sync generation"] + USART_FRAME_LIN_MASTER_MODE = 2, + #[doc = "4: Auto-baud - break detection and auto-baud"] + USART_FRAME_AUTO_BAUD_NO_PARITY = 4, + #[doc = "5: Auto-baud - break detection and auto-baud with parity"] + USART_FRAME_AUTO_BAUD_WITH_PARITY = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FORM_A) -> Self { + variant as _ + } +} +#[doc = "Field `FORM` reader - Frame Format"] +pub struct FORM_R(crate::FieldReader); +impl FORM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FORM_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(FORM_A::USART_FRAME_NO_PARITY), + 1 => Some(FORM_A::USART_FRAME_WITH_PARITY), + 2 => Some(FORM_A::USART_FRAME_LIN_MASTER_MODE), + 4 => Some(FORM_A::USART_FRAME_AUTO_BAUD_NO_PARITY), + 5 => Some(FORM_A::USART_FRAME_AUTO_BAUD_WITH_PARITY), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_FRAME_NO_PARITY`"] + #[inline(always)] + pub fn is_usart_frame_no_parity(&self) -> bool { + **self == FORM_A::USART_FRAME_NO_PARITY + } + #[doc = "Checks if the value of the field is `USART_FRAME_WITH_PARITY`"] + #[inline(always)] + pub fn is_usart_frame_with_parity(&self) -> bool { + **self == FORM_A::USART_FRAME_WITH_PARITY + } + #[doc = "Checks if the value of the field is `USART_FRAME_LIN_MASTER_MODE`"] + #[inline(always)] + pub fn is_usart_frame_lin_master_mode(&self) -> bool { + **self == FORM_A::USART_FRAME_LIN_MASTER_MODE + } + #[doc = "Checks if the value of the field is `USART_FRAME_AUTO_BAUD_NO_PARITY`"] + #[inline(always)] + pub fn is_usart_frame_auto_baud_no_parity(&self) -> bool { + **self == FORM_A::USART_FRAME_AUTO_BAUD_NO_PARITY + } + #[doc = "Checks if the value of the field is `USART_FRAME_AUTO_BAUD_WITH_PARITY`"] + #[inline(always)] + pub fn is_usart_frame_auto_baud_with_parity(&self) -> bool { + **self == FORM_A::USART_FRAME_AUTO_BAUD_WITH_PARITY + } +} +impl core::ops::Deref for FORM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FORM` writer - Frame Format"] +pub struct FORM_W<'a> { + w: &'a mut W, +} +impl<'a> FORM_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FORM_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART frame"] + #[inline(always)] + pub fn usart_frame_no_parity(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_NO_PARITY) + } + #[doc = "USART frame with parity"] + #[inline(always)] + pub fn usart_frame_with_parity(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_WITH_PARITY) + } + #[doc = "LIN Master - Break and sync generation"] + #[inline(always)] + pub fn usart_frame_lin_master_mode(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_LIN_MASTER_MODE) + } + #[doc = "Auto-baud - break detection and auto-baud"] + #[inline(always)] + pub fn usart_frame_auto_baud_no_parity(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_AUTO_BAUD_NO_PARITY) + } + #[doc = "Auto-baud - break detection and auto-baud with parity"] + #[inline(always)] + pub fn usart_frame_auto_baud_with_parity(self) -> &'a mut W { + self.variant(FORM_A::USART_FRAME_AUTO_BAUD_WITH_PARITY) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Communication Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CMODE_A { + #[doc = "0: Asynchronous Communication"] + ASYNC = 0, + #[doc = "1: Synchronous Communication"] + SYNC = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CMODE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CMODE` reader - Communication Mode"] +pub struct CMODE_R(crate::FieldReader); +impl CMODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CMODE_A { + match self.bits { + false => CMODE_A::ASYNC, + true => CMODE_A::SYNC, + } + } + #[doc = "Checks if the value of the field is `ASYNC`"] + #[inline(always)] + pub fn is_async(&self) -> bool { + **self == CMODE_A::ASYNC + } + #[doc = "Checks if the value of the field is `SYNC`"] + #[inline(always)] + pub fn is_sync(&self) -> bool { + **self == CMODE_A::SYNC + } +} +impl core::ops::Deref for CMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMODE` writer - Communication Mode"] +pub struct CMODE_W<'a> { + w: &'a mut W, +} +impl<'a> CMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMODE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Asynchronous Communication"] + #[inline(always)] + pub fn async_(self) -> &'a mut W { + self.variant(CMODE_A::ASYNC) + } + #[doc = "Synchronous Communication"] + #[inline(always)] + pub fn sync(self) -> &'a mut W { + self.variant(CMODE_A::SYNC) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Clock Polarity\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CPOL_A { + #[doc = "0: TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge"] + IDLE_LOW = 0, + #[doc = "1: TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge"] + IDLE_HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CPOL_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CPOL` reader - Clock Polarity"] +pub struct CPOL_R(crate::FieldReader); +impl CPOL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPOL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CPOL_A { + match self.bits { + false => CPOL_A::IDLE_LOW, + true => CPOL_A::IDLE_HIGH, + } + } + #[doc = "Checks if the value of the field is `IDLE_LOW`"] + #[inline(always)] + pub fn is_idle_low(&self) -> bool { + **self == CPOL_A::IDLE_LOW + } + #[doc = "Checks if the value of the field is `IDLE_HIGH`"] + #[inline(always)] + pub fn is_idle_high(&self) -> bool { + **self == CPOL_A::IDLE_HIGH + } +} +impl core::ops::Deref for CPOL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPOL` writer - Clock Polarity"] +pub struct CPOL_W<'a> { + w: &'a mut W, +} +impl<'a> CPOL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CPOL_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge"] + #[inline(always)] + pub fn idle_low(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_LOW) + } + #[doc = "TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge"] + #[inline(always)] + pub fn idle_high(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_HIGH) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29); + self.w + } +} +#[doc = "Data Order\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum DORD_A { + #[doc = "0: MSB is transmitted first"] + MSB = 0, + #[doc = "1: LSB is transmitted first"] + LSB = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DORD_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DORD` reader - Data Order"] +pub struct DORD_R(crate::FieldReader); +impl DORD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DORD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DORD_A { + match self.bits { + false => DORD_A::MSB, + true => DORD_A::LSB, + } + } + #[doc = "Checks if the value of the field is `MSB`"] + #[inline(always)] + pub fn is_msb(&self) -> bool { + **self == DORD_A::MSB + } + #[doc = "Checks if the value of the field is `LSB`"] + #[inline(always)] + pub fn is_lsb(&self) -> bool { + **self == DORD_A::LSB + } +} +impl core::ops::Deref for DORD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DORD` writer - Data Order"] +pub struct DORD_W<'a> { + w: &'a mut W, +} +impl<'a> DORD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DORD_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "MSB is transmitted first"] + #[inline(always)] + pub fn msb(self) -> &'a mut W { + self.variant(DORD_A::MSB) + } + #[doc = "LSB is transmitted first"] + #[inline(always)] + pub fn lsb(self) -> &'a mut W { + self.variant(DORD_A::LSB) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x07) as u8) + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&self) -> IBON_R { + IBON_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bits 13:15 - Sample"] + #[inline(always)] + pub fn sampr(&self) -> SAMPR_R { + SAMPR_R::new(((self.bits >> 13) & 0x07) as u8) + } + #[doc = "Bits 16:17 - Transmit Data Pinout"] + #[inline(always)] + pub fn txpo(&self) -> TXPO_R { + TXPO_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bits 20:21 - Receive Data Pinout"] + #[inline(always)] + pub fn rxpo(&self) -> RXPO_R { + RXPO_R::new(((self.bits >> 20) & 0x03) as u8) + } + #[doc = "Bits 22:23 - Sample Adjustment"] + #[inline(always)] + pub fn sampa(&self) -> SAMPA_R { + SAMPA_R::new(((self.bits >> 22) & 0x03) as u8) + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&self) -> FORM_R { + FORM_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 28 - Communication Mode"] + #[inline(always)] + pub fn cmode(&self) -> CMODE_R { + CMODE_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&self) -> CPOL_R { + CPOL_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&self) -> DORD_R { + DORD_R::new(((self.bits >> 30) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&mut self) -> IBON_W { + IBON_W { w: self } + } + #[doc = "Bits 13:15 - Sample"] + #[inline(always)] + pub fn sampr(&mut self) -> SAMPR_W { + SAMPR_W { w: self } + } + #[doc = "Bits 16:17 - Transmit Data Pinout"] + #[inline(always)] + pub fn txpo(&mut self) -> TXPO_W { + TXPO_W { w: self } + } + #[doc = "Bits 20:21 - Receive Data Pinout"] + #[inline(always)] + pub fn rxpo(&mut self) -> RXPO_W { + RXPO_W { w: self } + } + #[doc = "Bits 22:23 - Sample Adjustment"] + #[inline(always)] + pub fn sampa(&mut self) -> SAMPA_W { + SAMPA_W { w: self } + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&mut self) -> FORM_W { + FORM_W { w: self } + } + #[doc = "Bit 28 - Communication Mode"] + #[inline(always)] + pub fn cmode(&mut self) -> CMODE_W { + CMODE_W { w: self } + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&mut self) -> CPOL_W { + CPOL_W { w: self } + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&mut self) -> DORD_W { + DORD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sercom0/usart_int/ctrlb.rs b/pac/atsamc21n/src/sercom0/usart_int/ctrlb.rs new file mode 100644 index 000000000000..d556e0c3cfc2 --- /dev/null +++ b/pac/atsamc21n/src/sercom0/usart_int/ctrlb.rs @@ -0,0 +1,651 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Character Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CHSIZE_A { + #[doc = "0: 8 Bits"] + _8_BIT = 0, + #[doc = "1: 9 Bits"] + _9_BIT = 1, + #[doc = "5: 5 Bits"] + _5_BIT = 5, + #[doc = "6: 6 Bits"] + _6_BIT = 6, + #[doc = "7: 7 Bits"] + _7_BIT = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CHSIZE_A) -> Self { + variant as _ + } +} +#[doc = "Field `CHSIZE` reader - Character Size"] +pub struct CHSIZE_R(crate::FieldReader); +impl CHSIZE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CHSIZE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CHSIZE_A::_8_BIT), + 1 => Some(CHSIZE_A::_9_BIT), + 5 => Some(CHSIZE_A::_5_BIT), + 6 => Some(CHSIZE_A::_6_BIT), + 7 => Some(CHSIZE_A::_7_BIT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_8_BIT`"] + #[inline(always)] + pub fn is_8_bit(&self) -> bool { + **self == CHSIZE_A::_8_BIT + } + #[doc = "Checks if the value of the field is `_9_BIT`"] + #[inline(always)] + pub fn is_9_bit(&self) -> bool { + **self == CHSIZE_A::_9_BIT + } + #[doc = "Checks if the value of the field is `_5_BIT`"] + #[inline(always)] + pub fn is_5_bit(&self) -> bool { + **self == CHSIZE_A::_5_BIT + } + #[doc = "Checks if the value of the field is `_6_BIT`"] + #[inline(always)] + pub fn is_6_bit(&self) -> bool { + **self == CHSIZE_A::_6_BIT + } + #[doc = "Checks if the value of the field is `_7_BIT`"] + #[inline(always)] + pub fn is_7_bit(&self) -> bool { + **self == CHSIZE_A::_7_BIT + } +} +impl core::ops::Deref for CHSIZE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHSIZE` writer - Character Size"] +pub struct CHSIZE_W<'a> { + w: &'a mut W, +} +impl<'a> CHSIZE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CHSIZE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8 Bits"] + #[inline(always)] + pub fn _8_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_8_BIT) + } + #[doc = "9 Bits"] + #[inline(always)] + pub fn _9_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_9_BIT) + } + #[doc = "5 Bits"] + #[inline(always)] + pub fn _5_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_5_BIT) + } + #[doc = "6 Bits"] + #[inline(always)] + pub fn _6_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_6_BIT) + } + #[doc = "7 Bits"] + #[inline(always)] + pub fn _7_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_7_BIT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Stop Bit Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SBMODE_A { + #[doc = "0: One Stop Bit"] + _1_BIT = 0, + #[doc = "1: Two Stop Bits"] + _2_BIT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SBMODE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SBMODE` reader - Stop Bit Mode"] +pub struct SBMODE_R(crate::FieldReader); +impl SBMODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SBMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SBMODE_A { + match self.bits { + false => SBMODE_A::_1_BIT, + true => SBMODE_A::_2_BIT, + } + } + #[doc = "Checks if the value of the field is `_1_BIT`"] + #[inline(always)] + pub fn is_1_bit(&self) -> bool { + **self == SBMODE_A::_1_BIT + } + #[doc = "Checks if the value of the field is `_2_BIT`"] + #[inline(always)] + pub fn is_2_bit(&self) -> bool { + **self == SBMODE_A::_2_BIT + } +} +impl core::ops::Deref for SBMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SBMODE` writer - Stop Bit Mode"] +pub struct SBMODE_W<'a> { + w: &'a mut W, +} +impl<'a> SBMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SBMODE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "One Stop Bit"] + #[inline(always)] + pub fn _1_bit(self) -> &'a mut W { + self.variant(SBMODE_A::_1_BIT) + } + #[doc = "Two Stop Bits"] + #[inline(always)] + pub fn _2_bit(self) -> &'a mut W { + self.variant(SBMODE_A::_2_BIT) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `COLDEN` reader - Collision Detection Enable"] +pub struct COLDEN_R(crate::FieldReader); +impl COLDEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COLDEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COLDEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COLDEN` writer - Collision Detection Enable"] +pub struct COLDEN_W<'a> { + w: &'a mut W, +} +impl<'a> COLDEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `SFDE` reader - Start of Frame Detection Enable"] +pub struct SFDE_R(crate::FieldReader); +impl SFDE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SFDE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SFDE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SFDE` writer - Start of Frame Detection Enable"] +pub struct SFDE_W<'a> { + w: &'a mut W, +} +impl<'a> SFDE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `ENC` reader - Encoding Format"] +pub struct ENC_R(crate::FieldReader); +impl ENC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENC` writer - Encoding Format"] +pub struct ENC_W<'a> { + w: &'a mut W, +} +impl<'a> ENC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Parity Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PMODE_A { + #[doc = "0: Even Parity"] + EVEN = 0, + #[doc = "1: Odd Parity"] + ODD = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PMODE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PMODE` reader - Parity Mode"] +pub struct PMODE_R(crate::FieldReader); +impl PMODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PMODE_A { + match self.bits { + false => PMODE_A::EVEN, + true => PMODE_A::ODD, + } + } + #[doc = "Checks if the value of the field is `EVEN`"] + #[inline(always)] + pub fn is_even(&self) -> bool { + **self == PMODE_A::EVEN + } + #[doc = "Checks if the value of the field is `ODD`"] + #[inline(always)] + pub fn is_odd(&self) -> bool { + **self == PMODE_A::ODD + } +} +impl core::ops::Deref for PMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PMODE` writer - Parity Mode"] +pub struct PMODE_W<'a> { + w: &'a mut W, +} +impl<'a> PMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PMODE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Even Parity"] + #[inline(always)] + pub fn even(self) -> &'a mut W { + self.variant(PMODE_A::EVEN) + } + #[doc = "Odd Parity"] + #[inline(always)] + pub fn odd(self) -> &'a mut W { + self.variant(PMODE_A::ODD) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `TXEN` reader - Transmitter Enable"] +pub struct TXEN_R(crate::FieldReader); +impl TXEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXEN` writer - Transmitter Enable"] +pub struct TXEN_W<'a> { + w: &'a mut W, +} +impl<'a> TXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `RXEN` reader - Receiver Enable"] +pub struct RXEN_R(crate::FieldReader); +impl RXEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXEN` writer - Receiver Enable"] +pub struct RXEN_W<'a> { + w: &'a mut W, +} +impl<'a> RXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `LINCMD` reader - LIN Command"] +pub struct LINCMD_R(crate::FieldReader); +impl LINCMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LINCMD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LINCMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LINCMD` writer - LIN Command"] +pub struct LINCMD_W<'a> { + w: &'a mut W, +} +impl<'a> LINCMD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 24)) | ((value as u32 & 0x03) << 24); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&self) -> CHSIZE_R { + CHSIZE_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 6 - Stop Bit Mode"] + #[inline(always)] + pub fn sbmode(&self) -> SBMODE_R { + SBMODE_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 8 - Collision Detection Enable"] + #[inline(always)] + pub fn colden(&self) -> COLDEN_R { + COLDEN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Start of Frame Detection Enable"] + #[inline(always)] + pub fn sfde(&self) -> SFDE_R { + SFDE_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Encoding Format"] + #[inline(always)] + pub fn enc(&self) -> ENC_R { + ENC_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 13 - Parity Mode"] + #[inline(always)] + pub fn pmode(&self) -> PMODE_R { + PMODE_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 16 - Transmitter Enable"] + #[inline(always)] + pub fn txen(&self) -> TXEN_R { + TXEN_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&self) -> RXEN_R { + RXEN_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bits 24:25 - LIN Command"] + #[inline(always)] + pub fn lincmd(&self) -> LINCMD_R { + LINCMD_R::new(((self.bits >> 24) & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&mut self) -> CHSIZE_W { + CHSIZE_W { w: self } + } + #[doc = "Bit 6 - Stop Bit Mode"] + #[inline(always)] + pub fn sbmode(&mut self) -> SBMODE_W { + SBMODE_W { w: self } + } + #[doc = "Bit 8 - Collision Detection Enable"] + #[inline(always)] + pub fn colden(&mut self) -> COLDEN_W { + COLDEN_W { w: self } + } + #[doc = "Bit 9 - Start of Frame Detection Enable"] + #[inline(always)] + pub fn sfde(&mut self) -> SFDE_W { + SFDE_W { w: self } + } + #[doc = "Bit 10 - Encoding Format"] + #[inline(always)] + pub fn enc(&mut self) -> ENC_W { + ENC_W { w: self } + } + #[doc = "Bit 13 - Parity Mode"] + #[inline(always)] + pub fn pmode(&mut self) -> PMODE_W { + PMODE_W { w: self } + } + #[doc = "Bit 16 - Transmitter Enable"] + #[inline(always)] + pub fn txen(&mut self) -> TXEN_W { + TXEN_W { w: self } + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&mut self) -> RXEN_W { + RXEN_W { w: self } + } + #[doc = "Bits 24:25 - LIN Command"] + #[inline(always)] + pub fn lincmd(&mut self) -> LINCMD_W { + LINCMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sercom0/usart_int/ctrlc.rs b/pac/atsamc21n/src/sercom0/usart_int/ctrlc.rs new file mode 100644 index 000000000000..e2182cc7f768 --- /dev/null +++ b/pac/atsamc21n/src/sercom0/usart_int/ctrlc.rs @@ -0,0 +1,177 @@ +#[doc = "Register `CTRLC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `GTIME` reader - RS485 Guard Time"] +pub struct GTIME_R(crate::FieldReader); +impl GTIME_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + GTIME_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GTIME_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GTIME` writer - RS485 Guard Time"] +pub struct GTIME_W<'a> { + w: &'a mut W, +} +impl<'a> GTIME_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Field `BRKLEN` reader - LIN Master Break Length"] +pub struct BRKLEN_R(crate::FieldReader); +impl BRKLEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BRKLEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BRKLEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BRKLEN` writer - LIN Master Break Length"] +pub struct BRKLEN_W<'a> { + w: &'a mut W, +} +impl<'a> BRKLEN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 8)) | ((value as u32 & 0x03) << 8); + self.w + } +} +#[doc = "Field `HDRDLY` reader - LIN Master Header Delay"] +pub struct HDRDLY_R(crate::FieldReader); +impl HDRDLY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + HDRDLY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HDRDLY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HDRDLY` writer - LIN Master Header Delay"] +pub struct HDRDLY_W<'a> { + w: &'a mut W, +} +impl<'a> HDRDLY_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 10)) | ((value as u32 & 0x03) << 10); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - RS485 Guard Time"] + #[inline(always)] + pub fn gtime(&self) -> GTIME_R { + GTIME_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bits 8:9 - LIN Master Break Length"] + #[inline(always)] + pub fn brklen(&self) -> BRKLEN_R { + BRKLEN_R::new(((self.bits >> 8) & 0x03) as u8) + } + #[doc = "Bits 10:11 - LIN Master Header Delay"] + #[inline(always)] + pub fn hdrdly(&self) -> HDRDLY_R { + HDRDLY_R::new(((self.bits >> 10) & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - RS485 Guard Time"] + #[inline(always)] + pub fn gtime(&mut self) -> GTIME_W { + GTIME_W { w: self } + } + #[doc = "Bits 8:9 - LIN Master Break Length"] + #[inline(always)] + pub fn brklen(&mut self) -> BRKLEN_W { + BRKLEN_W { w: self } + } + #[doc = "Bits 10:11 - LIN Master Header Delay"] + #[inline(always)] + pub fn hdrdly(&mut self) -> HDRDLY_W { + HDRDLY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Control C\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlc](index.html) module"] +pub struct CTRLC_SPEC; +impl crate::RegisterSpec for CTRLC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlc::R](R) reader structure"] +impl crate::Readable for CTRLC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlc::W](W) writer structure"] +impl crate::Writable for CTRLC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLC to value 0"] +impl crate::Resettable for CTRLC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sercom0/usart_int/data.rs b/pac/atsamc21n/src/sercom0/usart_int/data.rs new file mode 100644 index 000000000000..19d74c337d44 --- /dev/null +++ b/pac/atsamc21n/src/sercom0/usart_int/data.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data Value"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data Value"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01ff) | (value as u16 & 0x01ff); + self.w + } +} +impl R { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new((self.bits & 0x01ff) as u16) + } +} +impl W { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sercom0/usart_int/dbgctrl.rs b/pac/atsamc21n/src/sercom0/usart_int/dbgctrl.rs new file mode 100644 index 000000000000..0ac5b9c7b902 --- /dev/null +++ b/pac/atsamc21n/src/sercom0/usart_int/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGSTOP` reader - Debug Mode"] +pub struct DBGSTOP_R(crate::FieldReader); +impl DBGSTOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGSTOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGSTOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGSTOP` writer - Debug Mode"] +pub struct DBGSTOP_W<'a> { + w: &'a mut W, +} +impl<'a> DBGSTOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&self) -> DBGSTOP_R { + DBGSTOP_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&mut self) -> DBGSTOP_W { + DBGSTOP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sercom0/usart_int/intenclr.rs b/pac/atsamc21n/src/sercom0/usart_int/intenclr.rs new file mode 100644 index 000000000000..5ad23ad15636 --- /dev/null +++ b/pac/atsamc21n/src/sercom0/usart_int/intenclr.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Disable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Disable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Disable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Disable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Disable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Disable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RXS` reader - Receive Start Interrupt Disable"] +pub struct RXS_R(crate::FieldReader); +impl RXS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXS` writer - Receive Start Interrupt Disable"] +pub struct RXS_W<'a> { + w: &'a mut W, +} +impl<'a> RXS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CTSIC` reader - Clear To Send Input Change Interrupt Disable"] +pub struct CTSIC_R(crate::FieldReader); +impl CTSIC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTSIC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTSIC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTSIC` writer - Clear To Send Input Change Interrupt Disable"] +pub struct CTSIC_W<'a> { + w: &'a mut W, +} +impl<'a> CTSIC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RXBRK` reader - Break Received Interrupt Disable"] +pub struct RXBRK_R(crate::FieldReader); +impl RXBRK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXBRK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXBRK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXBRK` writer - Break Received Interrupt Disable"] +pub struct RXBRK_W<'a> { + w: &'a mut W, +} +impl<'a> RXBRK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Disable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Disable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Receive Start Interrupt Disable"] + #[inline(always)] + pub fn rxs(&self) -> RXS_R { + RXS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Disable"] + #[inline(always)] + pub fn ctsic(&self) -> CTSIC_R { + CTSIC_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Break Received Interrupt Disable"] + #[inline(always)] + pub fn rxbrk(&self) -> RXBRK_R { + RXBRK_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Receive Start Interrupt Disable"] + #[inline(always)] + pub fn rxs(&mut self) -> RXS_W { + RXS_W { w: self } + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Disable"] + #[inline(always)] + pub fn ctsic(&mut self) -> CTSIC_W { + CTSIC_W { w: self } + } + #[doc = "Bit 5 - Break Received Interrupt Disable"] + #[inline(always)] + pub fn rxbrk(&mut self) -> RXBRK_W { + RXBRK_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sercom0/usart_int/intenset.rs b/pac/atsamc21n/src/sercom0/usart_int/intenset.rs new file mode 100644 index 000000000000..457f440e13e9 --- /dev/null +++ b/pac/atsamc21n/src/sercom0/usart_int/intenset.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Enable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Enable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Enable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Enable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Enable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Enable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RXS` reader - Receive Start Interrupt Enable"] +pub struct RXS_R(crate::FieldReader); +impl RXS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXS` writer - Receive Start Interrupt Enable"] +pub struct RXS_W<'a> { + w: &'a mut W, +} +impl<'a> RXS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CTSIC` reader - Clear To Send Input Change Interrupt Enable"] +pub struct CTSIC_R(crate::FieldReader); +impl CTSIC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTSIC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTSIC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTSIC` writer - Clear To Send Input Change Interrupt Enable"] +pub struct CTSIC_W<'a> { + w: &'a mut W, +} +impl<'a> CTSIC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RXBRK` reader - Break Received Interrupt Enable"] +pub struct RXBRK_R(crate::FieldReader); +impl RXBRK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXBRK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXBRK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXBRK` writer - Break Received Interrupt Enable"] +pub struct RXBRK_W<'a> { + w: &'a mut W, +} +impl<'a> RXBRK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Receive Start Interrupt Enable"] + #[inline(always)] + pub fn rxs(&self) -> RXS_R { + RXS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Enable"] + #[inline(always)] + pub fn ctsic(&self) -> CTSIC_R { + CTSIC_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Break Received Interrupt Enable"] + #[inline(always)] + pub fn rxbrk(&self) -> RXBRK_R { + RXBRK_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Receive Start Interrupt Enable"] + #[inline(always)] + pub fn rxs(&mut self) -> RXS_W { + RXS_W { w: self } + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Enable"] + #[inline(always)] + pub fn ctsic(&mut self) -> CTSIC_W { + CTSIC_W { w: self } + } + #[doc = "Bit 5 - Break Received Interrupt Enable"] + #[inline(always)] + pub fn rxbrk(&mut self) -> RXBRK_W { + RXBRK_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sercom0/usart_int/intflag.rs b/pac/atsamc21n/src/sercom0/usart_int/intflag.rs new file mode 100644 index 000000000000..a6a26321b8c4 --- /dev/null +++ b/pac/atsamc21n/src/sercom0/usart_int/intflag.rs @@ -0,0 +1,395 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RXS` reader - Receive Start Interrupt"] +pub struct RXS_R(crate::FieldReader); +impl RXS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXS` writer - Receive Start Interrupt"] +pub struct RXS_W<'a> { + w: &'a mut W, +} +impl<'a> RXS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CTSIC` reader - Clear To Send Input Change Interrupt"] +pub struct CTSIC_R(crate::FieldReader); +impl CTSIC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTSIC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTSIC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTSIC` writer - Clear To Send Input Change Interrupt"] +pub struct CTSIC_W<'a> { + w: &'a mut W, +} +impl<'a> CTSIC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RXBRK` reader - Break Received Interrupt"] +pub struct RXBRK_R(crate::FieldReader); +impl RXBRK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXBRK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXBRK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXBRK` writer - Break Received Interrupt"] +pub struct RXBRK_W<'a> { + w: &'a mut W, +} +impl<'a> RXBRK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Receive Start Interrupt"] + #[inline(always)] + pub fn rxs(&self) -> RXS_R { + RXS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt"] + #[inline(always)] + pub fn ctsic(&self) -> CTSIC_R { + CTSIC_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Break Received Interrupt"] + #[inline(always)] + pub fn rxbrk(&self) -> RXBRK_R { + RXBRK_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Receive Start Interrupt"] + #[inline(always)] + pub fn rxs(&mut self) -> RXS_W { + RXS_W { w: self } + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt"] + #[inline(always)] + pub fn ctsic(&mut self) -> CTSIC_W { + CTSIC_W { w: self } + } + #[doc = "Bit 5 - Break Received Interrupt"] + #[inline(always)] + pub fn rxbrk(&mut self) -> RXBRK_W { + RXBRK_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sercom0/usart_int/rxpl.rs b/pac/atsamc21n/src/sercom0/usart_int/rxpl.rs new file mode 100644 index 000000000000..324cbac371c1 --- /dev/null +++ b/pac/atsamc21n/src/sercom0/usart_int/rxpl.rs @@ -0,0 +1,103 @@ +#[doc = "Register `RXPL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RXPL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RXPL` reader - Receive Pulse Length"] +pub struct RXPL_R(crate::FieldReader); +impl RXPL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RXPL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXPL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXPL` writer - Receive Pulse Length"] +pub struct RXPL_W<'a> { + w: &'a mut W, +} +impl<'a> RXPL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Receive Pulse Length"] + #[inline(always)] + pub fn rxpl(&self) -> RXPL_R { + RXPL_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Receive Pulse Length"] + #[inline(always)] + pub fn rxpl(&mut self) -> RXPL_W { + RXPL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Receive Pulse Length\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxpl](index.html) module"] +pub struct RXPL_SPEC; +impl crate::RegisterSpec for RXPL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [rxpl::R](R) reader structure"] +impl crate::Readable for RXPL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rxpl::W](W) writer structure"] +impl crate::Writable for RXPL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RXPL to value 0"] +impl crate::Resettable for RXPL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sercom0/usart_int/status.rs b/pac/atsamc21n/src/sercom0/usart_int/status.rs new file mode 100644 index 000000000000..1a92018a359b --- /dev/null +++ b/pac/atsamc21n/src/sercom0/usart_int/status.rs @@ -0,0 +1,395 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PERR` reader - Parity Error"] +pub struct PERR_R(crate::FieldReader); +impl PERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERR` writer - Parity Error"] +pub struct PERR_W<'a> { + w: &'a mut W, +} +impl<'a> PERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `FERR` reader - Frame Error"] +pub struct FERR_R(crate::FieldReader); +impl FERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FERR` writer - Frame Error"] +pub struct FERR_W<'a> { + w: &'a mut W, +} +impl<'a> FERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `BUFOVF` reader - Buffer Overflow"] +pub struct BUFOVF_R(crate::FieldReader); +impl BUFOVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUFOVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUFOVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUFOVF` writer - Buffer Overflow"] +pub struct BUFOVF_W<'a> { + w: &'a mut W, +} +impl<'a> BUFOVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CTS` reader - Clear To Send"] +pub struct CTS_R(crate::FieldReader); +impl CTS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTS` writer - Clear To Send"] +pub struct CTS_W<'a> { + w: &'a mut W, +} +impl<'a> CTS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ISF` reader - Inconsistent Sync Field"] +pub struct ISF_R(crate::FieldReader); +impl ISF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ISF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ISF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ISF` writer - Inconsistent Sync Field"] +pub struct ISF_W<'a> { + w: &'a mut W, +} +impl<'a> ISF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `COLL` reader - Collision Detected"] +pub struct COLL_R(crate::FieldReader); +impl COLL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COLL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COLL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COLL` writer - Collision Detected"] +pub struct COLL_W<'a> { + w: &'a mut W, +} +impl<'a> COLL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `TXE` reader - Transmitter Empty"] +pub struct TXE_R(crate::FieldReader); +impl TXE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXE` writer - Transmitter Empty"] +pub struct TXE_W<'a> { + w: &'a mut W, +} +impl<'a> TXE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - Parity Error"] + #[inline(always)] + pub fn perr(&self) -> PERR_R { + PERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Frame Error"] + #[inline(always)] + pub fn ferr(&self) -> FERR_R { + FERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&self) -> BUFOVF_R { + BUFOVF_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Clear To Send"] + #[inline(always)] + pub fn cts(&self) -> CTS_R { + CTS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Inconsistent Sync Field"] + #[inline(always)] + pub fn isf(&self) -> ISF_R { + ISF_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Collision Detected"] + #[inline(always)] + pub fn coll(&self) -> COLL_R { + COLL_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Transmitter Empty"] + #[inline(always)] + pub fn txe(&self) -> TXE_R { + TXE_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Parity Error"] + #[inline(always)] + pub fn perr(&mut self) -> PERR_W { + PERR_W { w: self } + } + #[doc = "Bit 1 - Frame Error"] + #[inline(always)] + pub fn ferr(&mut self) -> FERR_W { + FERR_W { w: self } + } + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&mut self) -> BUFOVF_W { + BUFOVF_W { w: self } + } + #[doc = "Bit 3 - Clear To Send"] + #[inline(always)] + pub fn cts(&mut self) -> CTS_W { + CTS_W { w: self } + } + #[doc = "Bit 4 - Inconsistent Sync Field"] + #[inline(always)] + pub fn isf(&mut self) -> ISF_W { + ISF_W { w: self } + } + #[doc = "Bit 5 - Collision Detected"] + #[inline(always)] + pub fn coll(&mut self) -> COLL_W { + COLL_W { w: self } + } + #[doc = "Bit 6 - Transmitter Empty"] + #[inline(always)] + pub fn txe(&mut self) -> TXE_W { + TXE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART_INT Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sercom0/usart_int/syncbusy.rs b/pac/atsamc21n/src/sercom0/usart_int/syncbusy.rs new file mode 100644 index 000000000000..5dea9a5a7bab --- /dev/null +++ b/pac/atsamc21n/src/sercom0/usart_int/syncbusy.rs @@ -0,0 +1,93 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - SERCOM Enable Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLB` reader - CTRLB Synchronization Busy"] +pub struct CTRLB_R(crate::FieldReader); +impl CTRLB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM Enable Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - CTRLB Synchronization Busy"] + #[inline(always)] + pub fn ctrlb(&self) -> CTRLB_R { + CTRLB_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +#[doc = "USART_INT Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/supc.rs b/pac/atsamc21n/src/supc.rs new file mode 100644 index 000000000000..0ad1d125bfd9 --- /dev/null +++ b/pac/atsamc21n/src/supc.rs @@ -0,0 +1,53 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x04 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x08 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x0c - Power and Clocks Status"] + pub status: crate::Reg, + #[doc = "0x10 - BODVDD Control"] + pub bodvdd: crate::Reg, + _reserved5: [u8; 0x04], + #[doc = "0x18 - VREG Control"] + pub vreg: crate::Reg, + #[doc = "0x1c - VREF Control"] + pub vref: crate::Reg, + #[doc = "0x20 - VREG33 Control"] + pub vreg33: crate::Reg, +} +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Power and Clocks Status"] +pub mod status; +#[doc = "BODVDD register accessor: an alias for `Reg`"] +pub type BODVDD = crate::Reg; +#[doc = "BODVDD Control"] +pub mod bodvdd; +#[doc = "VREG register accessor: an alias for `Reg`"] +pub type VREG = crate::Reg; +#[doc = "VREG Control"] +pub mod vreg; +#[doc = "VREF register accessor: an alias for `Reg`"] +pub type VREF = crate::Reg; +#[doc = "VREF Control"] +pub mod vref; +#[doc = "VREG33 register accessor: an alias for `Reg`"] +pub type VREG33 = crate::Reg; +#[doc = "VREG33 Control"] +pub mod vreg33; diff --git a/pac/atsamc21n/src/supc/bodvdd.rs b/pac/atsamc21n/src/supc/bodvdd.rs new file mode 100644 index 000000000000..f5cbfffb6453 --- /dev/null +++ b/pac/atsamc21n/src/supc/bodvdd.rs @@ -0,0 +1,705 @@ +#[doc = "Register `BODVDD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BODVDD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `HYST` reader - Hysteresis Enable"] +pub struct HYST_R(crate::FieldReader); +impl HYST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HYST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HYST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HYST` writer - Hysteresis Enable"] +pub struct HYST_W<'a> { + w: &'a mut W, +} +impl<'a> HYST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Action when Threshold Crossed\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum ACTION_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: The BODVDD generates a reset"] + RESET = 1, + #[doc = "2: The BODVDD generates an interrupt"] + INT = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: ACTION_A) -> Self { + variant as _ + } +} +#[doc = "Field `ACTION` reader - Action when Threshold Crossed"] +pub struct ACTION_R(crate::FieldReader); +impl ACTION_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ACTION_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(ACTION_A::NONE), + 1 => Some(ACTION_A::RESET), + 2 => Some(ACTION_A::INT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == ACTION_A::NONE + } + #[doc = "Checks if the value of the field is `RESET`"] + #[inline(always)] + pub fn is_reset(&self) -> bool { + **self == ACTION_A::RESET + } + #[doc = "Checks if the value of the field is `INT`"] + #[inline(always)] + pub fn is_int(&self) -> bool { + **self == ACTION_A::INT + } +} +impl core::ops::Deref for ACTION_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ACTION` writer - Action when Threshold Crossed"] +pub struct ACTION_W<'a> { + w: &'a mut W, +} +impl<'a> ACTION_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: ACTION_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(ACTION_A::NONE) + } + #[doc = "The BODVDD generates a reset"] + #[inline(always)] + pub fn reset(self) -> &'a mut W { + self.variant(ACTION_A::RESET) + } + #[doc = "The BODVDD generates an interrupt"] + #[inline(always)] + pub fn int(self) -> &'a mut W { + self.variant(ACTION_A::INT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 3)) | ((value as u32 & 0x03) << 3); + self.w + } +} +#[doc = "Field `STDBYCFG` reader - Configuration in Standby mode"] +pub struct STDBYCFG_R(crate::FieldReader); +impl STDBYCFG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STDBYCFG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STDBYCFG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STDBYCFG` writer - Configuration in Standby mode"] +pub struct STDBYCFG_W<'a> { + w: &'a mut W, +} +impl<'a> STDBYCFG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ACTCFG` reader - Configuration in Active mode"] +pub struct ACTCFG_R(crate::FieldReader); +impl ACTCFG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ACTCFG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ACTCFG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ACTCFG` writer - Configuration in Active mode"] +pub struct ACTCFG_W<'a> { + w: &'a mut W, +} +impl<'a> ACTCFG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Prescaler Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PSEL_A { + #[doc = "0: Divide clock by 2"] + DIV2 = 0, + #[doc = "1: Divide clock by 4"] + DIV4 = 1, + #[doc = "2: Divide clock by 8"] + DIV8 = 2, + #[doc = "3: Divide clock by 16"] + DIV16 = 3, + #[doc = "4: Divide clock by 32"] + DIV32 = 4, + #[doc = "5: Divide clock by 64"] + DIV64 = 5, + #[doc = "6: Divide clock by 128"] + DIV128 = 6, + #[doc = "7: Divide clock by 256"] + DIV256 = 7, + #[doc = "8: Divide clock by 512"] + DIV512 = 8, + #[doc = "9: Divide clock by 1024"] + DIV1024 = 9, + #[doc = "10: Divide clock by 2048"] + DIV2048 = 10, + #[doc = "11: Divide clock by 4096"] + DIV4096 = 11, + #[doc = "12: Divide clock by 8192"] + DIV8192 = 12, + #[doc = "13: Divide clock by 16384"] + DIV16384 = 13, + #[doc = "14: Divide clock by 32768"] + DIV32768 = 14, + #[doc = "15: Divide clock by 65536"] + DIV65536 = 15, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `PSEL` reader - Prescaler Select"] +pub struct PSEL_R(crate::FieldReader); +impl PSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PSEL_A { + match self.bits { + 0 => PSEL_A::DIV2, + 1 => PSEL_A::DIV4, + 2 => PSEL_A::DIV8, + 3 => PSEL_A::DIV16, + 4 => PSEL_A::DIV32, + 5 => PSEL_A::DIV64, + 6 => PSEL_A::DIV128, + 7 => PSEL_A::DIV256, + 8 => PSEL_A::DIV512, + 9 => PSEL_A::DIV1024, + 10 => PSEL_A::DIV2048, + 11 => PSEL_A::DIV4096, + 12 => PSEL_A::DIV8192, + 13 => PSEL_A::DIV16384, + 14 => PSEL_A::DIV32768, + 15 => PSEL_A::DIV65536, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PSEL_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PSEL_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PSEL_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PSEL_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == PSEL_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PSEL_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == PSEL_A::DIV128 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PSEL_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV512`"] + #[inline(always)] + pub fn is_div512(&self) -> bool { + **self == PSEL_A::DIV512 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PSEL_A::DIV1024 + } + #[doc = "Checks if the value of the field is `DIV2048`"] + #[inline(always)] + pub fn is_div2048(&self) -> bool { + **self == PSEL_A::DIV2048 + } + #[doc = "Checks if the value of the field is `DIV4096`"] + #[inline(always)] + pub fn is_div4096(&self) -> bool { + **self == PSEL_A::DIV4096 + } + #[doc = "Checks if the value of the field is `DIV8192`"] + #[inline(always)] + pub fn is_div8192(&self) -> bool { + **self == PSEL_A::DIV8192 + } + #[doc = "Checks if the value of the field is `DIV16384`"] + #[inline(always)] + pub fn is_div16384(&self) -> bool { + **self == PSEL_A::DIV16384 + } + #[doc = "Checks if the value of the field is `DIV32768`"] + #[inline(always)] + pub fn is_div32768(&self) -> bool { + **self == PSEL_A::DIV32768 + } + #[doc = "Checks if the value of the field is `DIV65536`"] + #[inline(always)] + pub fn is_div65536(&self) -> bool { + **self == PSEL_A::DIV65536 + } +} +impl core::ops::Deref for PSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PSEL` writer - Prescaler Select"] +pub struct PSEL_W<'a> { + w: &'a mut W, +} +impl<'a> PSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PSEL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Divide clock by 2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PSEL_A::DIV2) + } + #[doc = "Divide clock by 4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PSEL_A::DIV4) + } + #[doc = "Divide clock by 8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PSEL_A::DIV8) + } + #[doc = "Divide clock by 16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PSEL_A::DIV16) + } + #[doc = "Divide clock by 32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(PSEL_A::DIV32) + } + #[doc = "Divide clock by 64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PSEL_A::DIV64) + } + #[doc = "Divide clock by 128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(PSEL_A::DIV128) + } + #[doc = "Divide clock by 256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PSEL_A::DIV256) + } + #[doc = "Divide clock by 512"] + #[inline(always)] + pub fn div512(self) -> &'a mut W { + self.variant(PSEL_A::DIV512) + } + #[doc = "Divide clock by 1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PSEL_A::DIV1024) + } + #[doc = "Divide clock by 2048"] + #[inline(always)] + pub fn div2048(self) -> &'a mut W { + self.variant(PSEL_A::DIV2048) + } + #[doc = "Divide clock by 4096"] + #[inline(always)] + pub fn div4096(self) -> &'a mut W { + self.variant(PSEL_A::DIV4096) + } + #[doc = "Divide clock by 8192"] + #[inline(always)] + pub fn div8192(self) -> &'a mut W { + self.variant(PSEL_A::DIV8192) + } + #[doc = "Divide clock by 16384"] + #[inline(always)] + pub fn div16384(self) -> &'a mut W { + self.variant(PSEL_A::DIV16384) + } + #[doc = "Divide clock by 32768"] + #[inline(always)] + pub fn div32768(self) -> &'a mut W { + self.variant(PSEL_A::DIV32768) + } + #[doc = "Divide clock by 65536"] + #[inline(always)] + pub fn div65536(self) -> &'a mut W { + self.variant(PSEL_A::DIV65536) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 12)) | ((value as u32 & 0x0f) << 12); + self.w + } +} +#[doc = "Field `LEVEL` reader - Threshold Level for VDD"] +pub struct LEVEL_R(crate::FieldReader); +impl LEVEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LEVEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LEVEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LEVEL` writer - Threshold Level for VDD"] +pub struct LEVEL_W<'a> { + w: &'a mut W, +} +impl<'a> LEVEL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 16)) | ((value as u32 & 0x3f) << 16); + self.w + } +} +impl R { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Hysteresis Enable"] + #[inline(always)] + pub fn hyst(&self) -> HYST_R { + HYST_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 3:4 - Action when Threshold Crossed"] + #[inline(always)] + pub fn action(&self) -> ACTION_R { + ACTION_R::new(((self.bits >> 3) & 0x03) as u8) + } + #[doc = "Bit 5 - Configuration in Standby mode"] + #[inline(always)] + pub fn stdbycfg(&self) -> STDBYCFG_R { + STDBYCFG_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 8 - Configuration in Active mode"] + #[inline(always)] + pub fn actcfg(&self) -> ACTCFG_R { + ACTCFG_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bits 12:15 - Prescaler Select"] + #[inline(always)] + pub fn psel(&self) -> PSEL_R { + PSEL_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:21 - Threshold Level for VDD"] + #[inline(always)] + pub fn level(&self) -> LEVEL_R { + LEVEL_R::new(((self.bits >> 16) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - Hysteresis Enable"] + #[inline(always)] + pub fn hyst(&mut self) -> HYST_W { + HYST_W { w: self } + } + #[doc = "Bits 3:4 - Action when Threshold Crossed"] + #[inline(always)] + pub fn action(&mut self) -> ACTION_W { + ACTION_W { w: self } + } + #[doc = "Bit 5 - Configuration in Standby mode"] + #[inline(always)] + pub fn stdbycfg(&mut self) -> STDBYCFG_W { + STDBYCFG_W { w: self } + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 8 - Configuration in Active mode"] + #[inline(always)] + pub fn actcfg(&mut self) -> ACTCFG_W { + ACTCFG_W { w: self } + } + #[doc = "Bits 12:15 - Prescaler Select"] + #[inline(always)] + pub fn psel(&mut self) -> PSEL_W { + PSEL_W { w: self } + } + #[doc = "Bits 16:21 - Threshold Level for VDD"] + #[inline(always)] + pub fn level(&mut self) -> LEVEL_W { + LEVEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "BODVDD Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [bodvdd](index.html) module"] +pub struct BODVDD_SPEC; +impl crate::RegisterSpec for BODVDD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [bodvdd::R](R) reader structure"] +impl crate::Readable for BODVDD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [bodvdd::W](W) writer structure"] +impl crate::Writable for BODVDD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BODVDD to value 0"] +impl crate::Resettable for BODVDD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/supc/intenclr.rs b/pac/atsamc21n/src/supc/intenclr.rs new file mode 100644 index 000000000000..555165e5dcb2 --- /dev/null +++ b/pac/atsamc21n/src/supc/intenclr.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BODVDDRDY` reader - BODVDD Ready"] +pub struct BODVDDRDY_R(crate::FieldReader); +impl BODVDDRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODVDDRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODVDDRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODVDDRDY` writer - BODVDD Ready"] +pub struct BODVDDRDY_W<'a> { + w: &'a mut W, +} +impl<'a> BODVDDRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `BODVDDDET` reader - BODVDD Detection"] +pub struct BODVDDDET_R(crate::FieldReader); +impl BODVDDDET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODVDDDET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODVDDDET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODVDDDET` writer - BODVDD Detection"] +pub struct BODVDDDET_W<'a> { + w: &'a mut W, +} +impl<'a> BODVDDDET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `BVDDSRDY` reader - BODVDD Synchronization Ready"] +pub struct BVDDSRDY_R(crate::FieldReader); +impl BVDDSRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BVDDSRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BVDDSRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BVDDSRDY` writer - BODVDD Synchronization Ready"] +pub struct BVDDSRDY_W<'a> { + w: &'a mut W, +} +impl<'a> BVDDSRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `VREG33RDY` reader - VREG33 Ready"] +pub struct VREG33RDY_R(crate::FieldReader); +impl VREG33RDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + VREG33RDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VREG33RDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VREG33RDY` writer - VREG33 Ready"] +pub struct VREG33RDY_W<'a> { + w: &'a mut W, +} +impl<'a> VREG33RDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - BODVDD Ready"] + #[inline(always)] + pub fn bodvddrdy(&self) -> BODVDDRDY_R { + BODVDDRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - BODVDD Detection"] + #[inline(always)] + pub fn bodvdddet(&self) -> BODVDDDET_R { + BODVDDDET_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - BODVDD Synchronization Ready"] + #[inline(always)] + pub fn bvddsrdy(&self) -> BVDDSRDY_R { + BVDDSRDY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 6 - VREG33 Ready"] + #[inline(always)] + pub fn vreg33rdy(&self) -> VREG33RDY_R { + VREG33RDY_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - BODVDD Ready"] + #[inline(always)] + pub fn bodvddrdy(&mut self) -> BODVDDRDY_W { + BODVDDRDY_W { w: self } + } + #[doc = "Bit 1 - BODVDD Detection"] + #[inline(always)] + pub fn bodvdddet(&mut self) -> BODVDDDET_W { + BODVDDDET_W { w: self } + } + #[doc = "Bit 2 - BODVDD Synchronization Ready"] + #[inline(always)] + pub fn bvddsrdy(&mut self) -> BVDDSRDY_W { + BVDDSRDY_W { w: self } + } + #[doc = "Bit 6 - VREG33 Ready"] + #[inline(always)] + pub fn vreg33rdy(&mut self) -> VREG33RDY_W { + VREG33RDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/supc/intenset.rs b/pac/atsamc21n/src/supc/intenset.rs new file mode 100644 index 000000000000..a0adfbaffa74 --- /dev/null +++ b/pac/atsamc21n/src/supc/intenset.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BODVDDRDY` reader - BODVDD Ready"] +pub struct BODVDDRDY_R(crate::FieldReader); +impl BODVDDRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODVDDRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODVDDRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODVDDRDY` writer - BODVDD Ready"] +pub struct BODVDDRDY_W<'a> { + w: &'a mut W, +} +impl<'a> BODVDDRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `BODVDDDET` reader - BODVDD Detection"] +pub struct BODVDDDET_R(crate::FieldReader); +impl BODVDDDET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODVDDDET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODVDDDET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODVDDDET` writer - BODVDD Detection"] +pub struct BODVDDDET_W<'a> { + w: &'a mut W, +} +impl<'a> BODVDDDET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `BVDDSRDY` reader - BODVDD Synchronization Ready"] +pub struct BVDDSRDY_R(crate::FieldReader); +impl BVDDSRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BVDDSRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BVDDSRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BVDDSRDY` writer - BODVDD Synchronization Ready"] +pub struct BVDDSRDY_W<'a> { + w: &'a mut W, +} +impl<'a> BVDDSRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `VREG33RDY` reader - VREG33 Ready"] +pub struct VREG33RDY_R(crate::FieldReader); +impl VREG33RDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + VREG33RDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VREG33RDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VREG33RDY` writer - VREG33 Ready"] +pub struct VREG33RDY_W<'a> { + w: &'a mut W, +} +impl<'a> VREG33RDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - BODVDD Ready"] + #[inline(always)] + pub fn bodvddrdy(&self) -> BODVDDRDY_R { + BODVDDRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - BODVDD Detection"] + #[inline(always)] + pub fn bodvdddet(&self) -> BODVDDDET_R { + BODVDDDET_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - BODVDD Synchronization Ready"] + #[inline(always)] + pub fn bvddsrdy(&self) -> BVDDSRDY_R { + BVDDSRDY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 6 - VREG33 Ready"] + #[inline(always)] + pub fn vreg33rdy(&self) -> VREG33RDY_R { + VREG33RDY_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - BODVDD Ready"] + #[inline(always)] + pub fn bodvddrdy(&mut self) -> BODVDDRDY_W { + BODVDDRDY_W { w: self } + } + #[doc = "Bit 1 - BODVDD Detection"] + #[inline(always)] + pub fn bodvdddet(&mut self) -> BODVDDDET_W { + BODVDDDET_W { w: self } + } + #[doc = "Bit 2 - BODVDD Synchronization Ready"] + #[inline(always)] + pub fn bvddsrdy(&mut self) -> BVDDSRDY_W { + BVDDSRDY_W { w: self } + } + #[doc = "Bit 6 - VREG33 Ready"] + #[inline(always)] + pub fn vreg33rdy(&mut self) -> VREG33RDY_W { + VREG33RDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/supc/intflag.rs b/pac/atsamc21n/src/supc/intflag.rs new file mode 100644 index 000000000000..ae4c2e125b6f --- /dev/null +++ b/pac/atsamc21n/src/supc/intflag.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BODVDDRDY` reader - BODVDD Ready"] +pub struct BODVDDRDY_R(crate::FieldReader); +impl BODVDDRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODVDDRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODVDDRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODVDDRDY` writer - BODVDD Ready"] +pub struct BODVDDRDY_W<'a> { + w: &'a mut W, +} +impl<'a> BODVDDRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `BODVDDDET` reader - BODVDD Detection"] +pub struct BODVDDDET_R(crate::FieldReader); +impl BODVDDDET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODVDDDET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODVDDDET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODVDDDET` writer - BODVDD Detection"] +pub struct BODVDDDET_W<'a> { + w: &'a mut W, +} +impl<'a> BODVDDDET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `BVDDSRDY` reader - BODVDD Synchronization Ready"] +pub struct BVDDSRDY_R(crate::FieldReader); +impl BVDDSRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BVDDSRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BVDDSRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BVDDSRDY` writer - BODVDD Synchronization Ready"] +pub struct BVDDSRDY_W<'a> { + w: &'a mut W, +} +impl<'a> BVDDSRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `VREG33RDY` reader - VREG33 Ready"] +pub struct VREG33RDY_R(crate::FieldReader); +impl VREG33RDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + VREG33RDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VREG33RDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VREG33RDY` writer - VREG33 Ready"] +pub struct VREG33RDY_W<'a> { + w: &'a mut W, +} +impl<'a> VREG33RDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - BODVDD Ready"] + #[inline(always)] + pub fn bodvddrdy(&self) -> BODVDDRDY_R { + BODVDDRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - BODVDD Detection"] + #[inline(always)] + pub fn bodvdddet(&self) -> BODVDDDET_R { + BODVDDDET_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - BODVDD Synchronization Ready"] + #[inline(always)] + pub fn bvddsrdy(&self) -> BVDDSRDY_R { + BVDDSRDY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 6 - VREG33 Ready"] + #[inline(always)] + pub fn vreg33rdy(&self) -> VREG33RDY_R { + VREG33RDY_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - BODVDD Ready"] + #[inline(always)] + pub fn bodvddrdy(&mut self) -> BODVDDRDY_W { + BODVDDRDY_W { w: self } + } + #[doc = "Bit 1 - BODVDD Detection"] + #[inline(always)] + pub fn bodvdddet(&mut self) -> BODVDDDET_W { + BODVDDDET_W { w: self } + } + #[doc = "Bit 2 - BODVDD Synchronization Ready"] + #[inline(always)] + pub fn bvddsrdy(&mut self) -> BVDDSRDY_W { + BVDDSRDY_W { w: self } + } + #[doc = "Bit 6 - VREG33 Ready"] + #[inline(always)] + pub fn vreg33rdy(&mut self) -> VREG33RDY_W { + VREG33RDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/supc/status.rs b/pac/atsamc21n/src/supc/status.rs new file mode 100644 index 000000000000..b15a68212223 --- /dev/null +++ b/pac/atsamc21n/src/supc/status.rs @@ -0,0 +1,113 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `BODVDDRDY` reader - BODVDD Ready"] +pub struct BODVDDRDY_R(crate::FieldReader); +impl BODVDDRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODVDDRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODVDDRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BODVDDDET` reader - BODVDD Detection"] +pub struct BODVDDDET_R(crate::FieldReader); +impl BODVDDDET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BODVDDDET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BODVDDDET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BVDDSRDY` reader - BODVDD Synchronization Ready"] +pub struct BVDDSRDY_R(crate::FieldReader); +impl BVDDSRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BVDDSRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BVDDSRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VREG33RDY` reader - VREG33 Ready"] +pub struct VREG33RDY_R(crate::FieldReader); +impl VREG33RDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + VREG33RDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VREG33RDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - BODVDD Ready"] + #[inline(always)] + pub fn bodvddrdy(&self) -> BODVDDRDY_R { + BODVDDRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - BODVDD Detection"] + #[inline(always)] + pub fn bodvdddet(&self) -> BODVDDDET_R { + BODVDDDET_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - BODVDD Synchronization Ready"] + #[inline(always)] + pub fn bvddsrdy(&self) -> BVDDSRDY_R { + BVDDSRDY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 6 - VREG33 Ready"] + #[inline(always)] + pub fn vreg33rdy(&self) -> VREG33RDY_R { + VREG33RDY_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +#[doc = "Power and Clocks Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/supc/vref.rs b/pac/atsamc21n/src/supc/vref.rs new file mode 100644 index 000000000000..55e25e0ceb9f --- /dev/null +++ b/pac/atsamc21n/src/supc/vref.rs @@ -0,0 +1,353 @@ +#[doc = "Register `VREF` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `VREF` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TSEN` reader - Temperature Sensor Output Enable"] +pub struct TSEN_R(crate::FieldReader); +impl TSEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSEN` writer - Temperature Sensor Output Enable"] +pub struct TSEN_W<'a> { + w: &'a mut W, +} +impl<'a> TSEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `VREFOE` reader - Voltage Reference Output Enable"] +pub struct VREFOE_R(crate::FieldReader); +impl VREFOE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + VREFOE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VREFOE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VREFOE` writer - Voltage Reference Output Enable"] +pub struct VREFOE_W<'a> { + w: &'a mut W, +} +impl<'a> VREFOE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - On Demand Control"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - On Demand Control"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Voltage Reference Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SEL_A { + #[doc = "0: 1.024V voltage reference typical value"] + _1V024 = 0, + #[doc = "2: 2.048V voltage reference typical value"] + _2V048 = 2, + #[doc = "3: 4.096V voltage reference typical value"] + _4V096 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `SEL` reader - Voltage Reference Selection"] +pub struct SEL_R(crate::FieldReader); +impl SEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEL_A::_1V024), + 2 => Some(SEL_A::_2V048), + 3 => Some(SEL_A::_4V096), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_1V024`"] + #[inline(always)] + pub fn is_1v024(&self) -> bool { + **self == SEL_A::_1V024 + } + #[doc = "Checks if the value of the field is `_2V048`"] + #[inline(always)] + pub fn is_2v048(&self) -> bool { + **self == SEL_A::_2V048 + } + #[doc = "Checks if the value of the field is `_4V096`"] + #[inline(always)] + pub fn is_4v096(&self) -> bool { + **self == SEL_A::_4V096 + } +} +impl core::ops::Deref for SEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEL` writer - Voltage Reference Selection"] +pub struct SEL_W<'a> { + w: &'a mut W, +} +impl<'a> SEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SEL_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "1.024V voltage reference typical value"] + #[inline(always)] + pub fn _1v024(self) -> &'a mut W { + self.variant(SEL_A::_1V024) + } + #[doc = "2.048V voltage reference typical value"] + #[inline(always)] + pub fn _2v048(self) -> &'a mut W { + self.variant(SEL_A::_2V048) + } + #[doc = "4.096V voltage reference typical value"] + #[inline(always)] + pub fn _4v096(self) -> &'a mut W { + self.variant(SEL_A::_4V096) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 16)) | ((value as u32 & 0x0f) << 16); + self.w + } +} +impl R { + #[doc = "Bit 1 - Temperature Sensor Output Enable"] + #[inline(always)] + pub fn tsen(&self) -> TSEN_R { + TSEN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Voltage Reference Output Enable"] + #[inline(always)] + pub fn vrefoe(&self) -> VREFOE_R { + VREFOE_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 16:19 - Voltage Reference Selection"] + #[inline(always)] + pub fn sel(&self) -> SEL_R { + SEL_R::new(((self.bits >> 16) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bit 1 - Temperature Sensor Output Enable"] + #[inline(always)] + pub fn tsen(&mut self) -> TSEN_W { + TSEN_W { w: self } + } + #[doc = "Bit 2 - Voltage Reference Output Enable"] + #[inline(always)] + pub fn vrefoe(&mut self) -> VREFOE_W { + VREFOE_W { w: self } + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Bits 16:19 - Voltage Reference Selection"] + #[inline(always)] + pub fn sel(&mut self) -> SEL_W { + SEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "VREF Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [vref](index.html) module"] +pub struct VREF_SPEC; +impl crate::RegisterSpec for VREF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [vref::R](R) reader structure"] +impl crate::Readable for VREF_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [vref::W](W) writer structure"] +impl crate::Writable for VREF_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets VREF to value 0"] +impl crate::Resettable for VREF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/supc/vreg.rs b/pac/atsamc21n/src/supc/vreg.rs new file mode 100644 index 000000000000..fb5b12a185cf --- /dev/null +++ b/pac/atsamc21n/src/supc/vreg.rs @@ -0,0 +1,160 @@ +#[doc = "Register `VREG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `VREG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "VREG Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [vreg](index.html) module"] +pub struct VREG_SPEC; +impl crate::RegisterSpec for VREG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [vreg::R](R) reader structure"] +impl crate::Readable for VREG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [vreg::W](W) writer structure"] +impl crate::Writable for VREG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets VREG to value 0"] +impl crate::Resettable for VREG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/supc/vreg33.rs b/pac/atsamc21n/src/supc/vreg33.rs new file mode 100644 index 000000000000..dde6a2a14950 --- /dev/null +++ b/pac/atsamc21n/src/supc/vreg33.rs @@ -0,0 +1,254 @@ +#[doc = "Register `VREG33` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `VREG33` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - VREG33 Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - VREG33 Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ENRDY` reader - VREG33 Ready Enable"] +pub struct ENRDY_R(crate::FieldReader); +impl ENRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENRDY` writer - VREG33 Ready Enable"] +pub struct ENRDY_W<'a> { + w: &'a mut W, +} +impl<'a> ENRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `BYPASS` reader - VREG33 Bypass"] +pub struct BYPASS_R(crate::FieldReader); +impl BYPASS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BYPASS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYPASS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYPASS` writer - VREG33 Bypass"] +pub struct BYPASS_W<'a> { + w: &'a mut W, +} +impl<'a> BYPASS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ISOEN` reader - Isolation Enable"] +pub struct ISOEN_R(crate::FieldReader); +impl ISOEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ISOEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ISOEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ISOEN` writer - Isolation Enable"] +pub struct ISOEN_W<'a> { + w: &'a mut W, +} +impl<'a> ISOEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +impl R { + #[doc = "Bit 1 - VREG33 Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - VREG33 Ready Enable"] + #[inline(always)] + pub fn enrdy(&self) -> ENRDY_R { + ENRDY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - VREG33 Bypass"] + #[inline(always)] + pub fn bypass(&self) -> BYPASS_R { + BYPASS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Isolation Enable"] + #[inline(always)] + pub fn isoen(&self) -> ISOEN_R { + ISOEN_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 1 - VREG33 Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - VREG33 Ready Enable"] + #[inline(always)] + pub fn enrdy(&mut self) -> ENRDY_W { + ENRDY_W { w: self } + } + #[doc = "Bit 3 - VREG33 Bypass"] + #[inline(always)] + pub fn bypass(&mut self) -> BYPASS_W { + BYPASS_W { w: self } + } + #[doc = "Bit 4 - Isolation Enable"] + #[inline(always)] + pub fn isoen(&mut self) -> ISOEN_W { + ISOEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "VREG33 Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [vreg33](index.html) module"] +pub struct VREG33_SPEC; +impl crate::RegisterSpec for VREG33_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [vreg33::R](R) reader structure"] +impl crate::Readable for VREG33_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [vreg33::W](W) writer structure"] +impl crate::Writable for VREG33_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets VREG33 to value 0x10"] +impl crate::Resettable for VREG33_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x10 + } +} diff --git a/pac/atsamc21n/src/sys_tick.rs b/pac/atsamc21n/src/sys_tick.rs new file mode 100644 index 000000000000..b0fe7a59e5ed --- /dev/null +++ b/pac/atsamc21n/src/sys_tick.rs @@ -0,0 +1,28 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - SysTick Control and Status Register"] + pub csr: crate::Reg, + #[doc = "0x04 - SysTick Reload Value Register"] + pub rvr: crate::Reg, + #[doc = "0x08 - SysTick Current Value Register"] + pub cvr: crate::Reg, + #[doc = "0x0c - SysTick Calibration Value Register"] + pub calib: crate::Reg, +} +#[doc = "CSR register accessor: an alias for `Reg`"] +pub type CSR = crate::Reg; +#[doc = "SysTick Control and Status Register"] +pub mod csr; +#[doc = "RVR register accessor: an alias for `Reg`"] +pub type RVR = crate::Reg; +#[doc = "SysTick Reload Value Register"] +pub mod rvr; +#[doc = "CVR register accessor: an alias for `Reg`"] +pub type CVR = crate::Reg; +#[doc = "SysTick Current Value Register"] +pub mod cvr; +#[doc = "CALIB register accessor: an alias for `Reg`"] +pub type CALIB = crate::Reg; +#[doc = "SysTick Calibration Value Register"] +pub mod calib; diff --git a/pac/atsamc21n/src/sys_tick/calib.rs b/pac/atsamc21n/src/sys_tick/calib.rs new file mode 100644 index 000000000000..df7fd80f773a --- /dev/null +++ b/pac/atsamc21n/src/sys_tick/calib.rs @@ -0,0 +1,157 @@ +#[doc = "Register `CALIB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `TENMS` reader - Reload value to use for 10ms timing"] +pub struct TENMS_R(crate::FieldReader); +impl TENMS_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + TENMS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TENMS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "TENMS is rounded from non-integer ratio\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SKEW_A { + #[doc = "0: 10ms calibration value is exact"] + VALUE_0 = 0, + #[doc = "1: 10ms calibration value is inexact, because of the clock frequency"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SKEW_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SKEW` reader - TENMS is rounded from non-integer ratio"] +pub struct SKEW_R(crate::FieldReader); +impl SKEW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SKEW_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SKEW_A { + match self.bits { + false => SKEW_A::VALUE_0, + true => SKEW_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == SKEW_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == SKEW_A::VALUE_1 + } +} +impl core::ops::Deref for SKEW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "No Separate Reference Clock\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum NOREF_A { + #[doc = "0: The reference clock is provided"] + VALUE_0 = 0, + #[doc = "1: The reference clock is not provided"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NOREF_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NOREF` reader - No Separate Reference Clock"] +pub struct NOREF_R(crate::FieldReader); +impl NOREF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NOREF_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> NOREF_A { + match self.bits { + false => NOREF_A::VALUE_0, + true => NOREF_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == NOREF_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == NOREF_A::VALUE_1 + } +} +impl core::ops::Deref for NOREF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:23 - Reload value to use for 10ms timing"] + #[inline(always)] + pub fn tenms(&self) -> TENMS_R { + TENMS_R::new((self.bits & 0x00ff_ffff) as u32) + } + #[doc = "Bit 30 - TENMS is rounded from non-integer ratio"] + #[inline(always)] + pub fn skew(&self) -> SKEW_R { + SKEW_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 31 - No Separate Reference Clock"] + #[inline(always)] + pub fn noref(&self) -> NOREF_R { + NOREF_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +#[doc = "SysTick Calibration Value Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [calib](index.html) module"] +pub struct CALIB_SPEC; +impl crate::RegisterSpec for CALIB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [calib::R](R) reader structure"] +impl crate::Readable for CALIB_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CALIB to value 0"] +impl crate::Resettable for CALIB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sys_tick/csr.rs b/pac/atsamc21n/src/sys_tick/csr.rs new file mode 100644 index 000000000000..872d637f5a86 --- /dev/null +++ b/pac/atsamc21n/src/sys_tick/csr.rs @@ -0,0 +1,395 @@ +#[doc = "Register `CSR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CSR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "SysTick Counter Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ENABLE_A { + #[doc = "0: Counter disabled"] + VALUE_0 = 0, + #[doc = "1: Counter enabled"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ENABLE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ENABLE` reader - SysTick Counter Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ENABLE_A { + match self.bits { + false => ENABLE_A::VALUE_0, + true => ENABLE_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == ENABLE_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == ENABLE_A::VALUE_1 + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - SysTick Counter Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: ENABLE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Counter disabled"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(ENABLE_A::VALUE_0) + } + #[doc = "Counter enabled"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(ENABLE_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "SysTick Exception Request Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TICKINT_A { + #[doc = "0: Counting down to 0 does not assert the SysTick exception request"] + VALUE_0 = 0, + #[doc = "1: Counting down to 0 asserts the SysTick exception request"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TICKINT_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TICKINT` reader - SysTick Exception Request Enable"] +pub struct TICKINT_R(crate::FieldReader); +impl TICKINT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TICKINT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> TICKINT_A { + match self.bits { + false => TICKINT_A::VALUE_0, + true => TICKINT_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == TICKINT_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == TICKINT_A::VALUE_1 + } +} +impl core::ops::Deref for TICKINT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TICKINT` writer - SysTick Exception Request Enable"] +pub struct TICKINT_W<'a> { + w: &'a mut W, +} +impl<'a> TICKINT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TICKINT_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Counting down to 0 does not assert the SysTick exception request"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(TICKINT_A::VALUE_0) + } + #[doc = "Counting down to 0 asserts the SysTick exception request"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(TICKINT_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Clock Source 0=external, 1=processor\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CLKSOURCE_A { + #[doc = "0: External clock"] + VALUE_0 = 0, + #[doc = "1: Processor clock"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CLKSOURCE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CLKSOURCE` reader - Clock Source 0=external, 1=processor"] +pub struct CLKSOURCE_R(crate::FieldReader); +impl CLKSOURCE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKSOURCE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CLKSOURCE_A { + match self.bits { + false => CLKSOURCE_A::VALUE_0, + true => CLKSOURCE_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == CLKSOURCE_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == CLKSOURCE_A::VALUE_1 + } +} +impl core::ops::Deref for CLKSOURCE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKSOURCE` writer - Clock Source 0=external, 1=processor"] +pub struct CLKSOURCE_W<'a> { + w: &'a mut W, +} +impl<'a> CLKSOURCE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CLKSOURCE_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "External clock"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(CLKSOURCE_A::VALUE_0) + } + #[doc = "Processor clock"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(CLKSOURCE_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `COUNTFLAG` reader - Timer counted to 0 since last read of register"] +pub struct COUNTFLAG_R(crate::FieldReader); +impl COUNTFLAG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNTFLAG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNTFLAG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNTFLAG` writer - Timer counted to 0 since last read of register"] +pub struct COUNTFLAG_W<'a> { + w: &'a mut W, +} +impl<'a> COUNTFLAG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +impl R { + #[doc = "Bit 0 - SysTick Counter Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SysTick Exception Request Enable"] + #[inline(always)] + pub fn tickint(&self) -> TICKINT_R { + TICKINT_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Clock Source 0=external, 1=processor"] + #[inline(always)] + pub fn clksource(&self) -> CLKSOURCE_R { + CLKSOURCE_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 16 - Timer counted to 0 since last read of register"] + #[inline(always)] + pub fn countflag(&self) -> COUNTFLAG_R { + COUNTFLAG_R::new(((self.bits >> 16) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - SysTick Counter Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 1 - SysTick Exception Request Enable"] + #[inline(always)] + pub fn tickint(&mut self) -> TICKINT_W { + TICKINT_W { w: self } + } + #[doc = "Bit 2 - Clock Source 0=external, 1=processor"] + #[inline(always)] + pub fn clksource(&mut self) -> CLKSOURCE_W { + CLKSOURCE_W { w: self } + } + #[doc = "Bit 16 - Timer counted to 0 since last read of register"] + #[inline(always)] + pub fn countflag(&mut self) -> COUNTFLAG_W { + COUNTFLAG_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SysTick Control and Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [csr](index.html) module"] +pub struct CSR_SPEC; +impl crate::RegisterSpec for CSR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [csr::R](R) reader structure"] +impl crate::Readable for CSR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [csr::W](W) writer structure"] +impl crate::Writable for CSR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CSR to value 0x04"] +impl crate::Resettable for CSR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x04 + } +} diff --git a/pac/atsamc21n/src/sys_tick/cvr.rs b/pac/atsamc21n/src/sys_tick/cvr.rs new file mode 100644 index 000000000000..8a40b5f43b3a --- /dev/null +++ b/pac/atsamc21n/src/sys_tick/cvr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `CVR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CVR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CURRENT` reader - Current value at the time the register is accessed"] +pub struct CURRENT_R(crate::FieldReader); +impl CURRENT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CURRENT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CURRENT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CURRENT` writer - Current value at the time the register is accessed"] +pub struct CURRENT_W<'a> { + w: &'a mut W, +} +impl<'a> CURRENT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Current value at the time the register is accessed"] + #[inline(always)] + pub fn current(&self) -> CURRENT_R { + CURRENT_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Current value at the time the register is accessed"] + #[inline(always)] + pub fn current(&mut self) -> CURRENT_W { + CURRENT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SysTick Current Value Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cvr](index.html) module"] +pub struct CVR_SPEC; +impl crate::RegisterSpec for CVR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cvr::R](R) reader structure"] +impl crate::Readable for CVR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cvr::W](W) writer structure"] +impl crate::Writable for CVR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CVR to value 0"] +impl crate::Resettable for CVR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/sys_tick/rvr.rs b/pac/atsamc21n/src/sys_tick/rvr.rs new file mode 100644 index 000000000000..ac023ff75f36 --- /dev/null +++ b/pac/atsamc21n/src/sys_tick/rvr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `RVR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RVR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RELOAD` reader - Value to load into the SysTick Current Value Register when the counter reaches 0"] +pub struct RELOAD_R(crate::FieldReader); +impl RELOAD_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + RELOAD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RELOAD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RELOAD` writer - Value to load into the SysTick Current Value Register when the counter reaches 0"] +pub struct RELOAD_W<'a> { + w: &'a mut W, +} +impl<'a> RELOAD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Value to load into the SysTick Current Value Register when the counter reaches 0"] + #[inline(always)] + pub fn reload(&self) -> RELOAD_R { + RELOAD_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Value to load into the SysTick Current Value Register when the counter reaches 0"] + #[inline(always)] + pub fn reload(&mut self) -> RELOAD_W { + RELOAD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SysTick Reload Value Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rvr](index.html) module"] +pub struct RVR_SPEC; +impl crate::RegisterSpec for RVR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rvr::R](R) reader structure"] +impl crate::Readable for RVR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rvr::W](W) writer structure"] +impl crate::Writable for RVR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RVR to value 0"] +impl crate::Resettable for RVR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/system_control.rs b/pac/atsamc21n/src/system_control.rs new file mode 100644 index 000000000000..4894b22b258f --- /dev/null +++ b/pac/atsamc21n/src/system_control.rs @@ -0,0 +1,67 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved0: [u8; 0x0d00], + #[doc = "0xd00 - CPUID Base Register"] + pub cpuid: crate::Reg, + #[doc = "0xd04 - Interrupt Control and State Register"] + pub icsr: crate::Reg, + #[doc = "0xd08 - Vector Table Offset Register"] + pub vtor: crate::Reg, + #[doc = "0xd0c - Application Interrupt and Reset Control Register"] + pub aircr: crate::Reg, + #[doc = "0xd10 - System Control Register"] + pub scr: crate::Reg, + #[doc = "0xd14 - Configuration and Control Register"] + pub ccr: crate::Reg, + _reserved6: [u8; 0x04], + #[doc = "0xd1c - System Handler Priority Register 2"] + pub shpr2: crate::Reg, + #[doc = "0xd20 - System Handler Priority Register 3"] + pub shpr3: crate::Reg, + #[doc = "0xd24 - System Handler Control and State Register"] + pub shcsr: crate::Reg, + _reserved9: [u8; 0x08], + #[doc = "0xd30 - Debug Fault Status Register"] + pub dfsr: crate::Reg, +} +#[doc = "CPUID register accessor: an alias for `Reg`"] +pub type CPUID = crate::Reg; +#[doc = "CPUID Base Register"] +pub mod cpuid; +#[doc = "ICSR register accessor: an alias for `Reg`"] +pub type ICSR = crate::Reg; +#[doc = "Interrupt Control and State Register"] +pub mod icsr; +#[doc = "VTOR register accessor: an alias for `Reg`"] +pub type VTOR = crate::Reg; +#[doc = "Vector Table Offset Register"] +pub mod vtor; +#[doc = "AIRCR register accessor: an alias for `Reg`"] +pub type AIRCR = crate::Reg; +#[doc = "Application Interrupt and Reset Control Register"] +pub mod aircr; +#[doc = "SCR register accessor: an alias for `Reg`"] +pub type SCR = crate::Reg; +#[doc = "System Control Register"] +pub mod scr; +#[doc = "CCR register accessor: an alias for `Reg`"] +pub type CCR = crate::Reg; +#[doc = "Configuration and Control Register"] +pub mod ccr; +#[doc = "SHPR2 register accessor: an alias for `Reg`"] +pub type SHPR2 = crate::Reg; +#[doc = "System Handler Priority Register 2"] +pub mod shpr2; +#[doc = "SHPR3 register accessor: an alias for `Reg`"] +pub type SHPR3 = crate::Reg; +#[doc = "System Handler Priority Register 3"] +pub mod shpr3; +#[doc = "SHCSR register accessor: an alias for `Reg`"] +pub type SHCSR = crate::Reg; +#[doc = "System Handler Control and State Register"] +pub mod shcsr; +#[doc = "DFSR register accessor: an alias for `Reg`"] +pub type DFSR = crate::Reg; +#[doc = "Debug Fault Status Register"] +pub mod dfsr; diff --git a/pac/atsamc21n/src/system_control/aircr.rs b/pac/atsamc21n/src/system_control/aircr.rs new file mode 100644 index 000000000000..9453cc6f30bc --- /dev/null +++ b/pac/atsamc21n/src/system_control/aircr.rs @@ -0,0 +1,338 @@ +#[doc = "Register `AIRCR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `AIRCR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `VECTCLRACTIVE` reader - Debug: Clear state information"] +pub struct VECTCLRACTIVE_R(crate::FieldReader); +impl VECTCLRACTIVE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + VECTCLRACTIVE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VECTCLRACTIVE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VECTCLRACTIVE` writer - Debug: Clear state information"] +pub struct VECTCLRACTIVE_W<'a> { + w: &'a mut W, +} +impl<'a> VECTCLRACTIVE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "System Reset Request\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SYSRESETREQ_A { + #[doc = "0: No system reset request"] + VALUE_0 = 0, + #[doc = "1: Asserts a signal to the outer system that requests a reset"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SYSRESETREQ_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SYSRESETREQ` reader - System Reset Request"] +pub struct SYSRESETREQ_R(crate::FieldReader); +impl SYSRESETREQ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYSRESETREQ_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SYSRESETREQ_A { + match self.bits { + false => SYSRESETREQ_A::VALUE_0, + true => SYSRESETREQ_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == SYSRESETREQ_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == SYSRESETREQ_A::VALUE_1 + } +} +impl core::ops::Deref for SYSRESETREQ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYSRESETREQ` writer - System Reset Request"] +pub struct SYSRESETREQ_W<'a> { + w: &'a mut W, +} +impl<'a> SYSRESETREQ_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SYSRESETREQ_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "No system reset request"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(SYSRESETREQ_A::VALUE_0) + } + #[doc = "Asserts a signal to the outer system that requests a reset"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(SYSRESETREQ_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Data Endianness, 0=little, 1=big\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ENDIANNESS_A { + #[doc = "0: Little-endian"] + VALUE_0 = 0, + #[doc = "1: Big-endian"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ENDIANNESS_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ENDIANNESS` reader - Data Endianness, 0=little, 1=big"] +pub struct ENDIANNESS_R(crate::FieldReader); +impl ENDIANNESS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENDIANNESS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ENDIANNESS_A { + match self.bits { + false => ENDIANNESS_A::VALUE_0, + true => ENDIANNESS_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == ENDIANNESS_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == ENDIANNESS_A::VALUE_1 + } +} +impl core::ops::Deref for ENDIANNESS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENDIANNESS` writer - Data Endianness, 0=little, 1=big"] +pub struct ENDIANNESS_W<'a> { + w: &'a mut W, +} +impl<'a> ENDIANNESS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: ENDIANNESS_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Little-endian"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(ENDIANNESS_A::VALUE_0) + } + #[doc = "Big-endian"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(ENDIANNESS_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `VECTKEY` reader - Register key (0x05FA)"] +pub struct VECTKEY_R(crate::FieldReader); +impl VECTKEY_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + VECTKEY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VECTKEY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VECTKEY` writer - Register key (0x05FA)"] +pub struct VECTKEY_W<'a> { + w: &'a mut W, +} +impl<'a> VECTKEY_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xffff << 16)) | ((value as u32 & 0xffff) << 16); + self.w + } +} +impl R { + #[doc = "Bit 1 - Debug: Clear state information"] + #[inline(always)] + pub fn vectclractive(&self) -> VECTCLRACTIVE_R { + VECTCLRACTIVE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - System Reset Request"] + #[inline(always)] + pub fn sysresetreq(&self) -> SYSRESETREQ_R { + SYSRESETREQ_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 15 - Data Endianness, 0=little, 1=big"] + #[inline(always)] + pub fn endianness(&self) -> ENDIANNESS_R { + ENDIANNESS_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:31 - Register key (0x05FA)"] + #[inline(always)] + pub fn vectkey(&self) -> VECTKEY_R { + VECTKEY_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bit 1 - Debug: Clear state information"] + #[inline(always)] + pub fn vectclractive(&mut self) -> VECTCLRACTIVE_W { + VECTCLRACTIVE_W { w: self } + } + #[doc = "Bit 2 - System Reset Request"] + #[inline(always)] + pub fn sysresetreq(&mut self) -> SYSRESETREQ_W { + SYSRESETREQ_W { w: self } + } + #[doc = "Bit 15 - Data Endianness, 0=little, 1=big"] + #[inline(always)] + pub fn endianness(&mut self) -> ENDIANNESS_W { + ENDIANNESS_W { w: self } + } + #[doc = "Bits 16:31 - Register key (0x05FA)"] + #[inline(always)] + pub fn vectkey(&mut self) -> VECTKEY_W { + VECTKEY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Application Interrupt and Reset Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [aircr](index.html) module"] +pub struct AIRCR_SPEC; +impl crate::RegisterSpec for AIRCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [aircr::R](R) reader structure"] +impl crate::Readable for AIRCR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [aircr::W](W) writer structure"] +impl crate::Writable for AIRCR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets AIRCR to value 0"] +impl crate::Resettable for AIRCR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/system_control/ccr.rs b/pac/atsamc21n/src/system_control/ccr.rs new file mode 100644 index 000000000000..62516a7b60c8 --- /dev/null +++ b/pac/atsamc21n/src/system_control/ccr.rs @@ -0,0 +1,137 @@ +#[doc = "Register `CCR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Unaligned accesses generates a Hard Fault\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum UNALIGN_TRP_A { + #[doc = "0: Do not trap unaligned halfword and word accesses"] + VALUE_0 = 0, + #[doc = "1: Trap unaligned halfword and word accesses"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: UNALIGN_TRP_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `UNALIGN_TRP` reader - Unaligned accesses generates a Hard Fault"] +pub struct UNALIGN_TRP_R(crate::FieldReader); +impl UNALIGN_TRP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UNALIGN_TRP_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> UNALIGN_TRP_A { + match self.bits { + false => UNALIGN_TRP_A::VALUE_0, + true => UNALIGN_TRP_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == UNALIGN_TRP_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == UNALIGN_TRP_A::VALUE_1 + } +} +impl core::ops::Deref for UNALIGN_TRP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Stack 8-byte aligned on exception entry\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum STKALIGN_A { + #[doc = "0: 4-byte aligned"] + VALUE_0 = 0, + #[doc = "1: 8-byte aligned"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: STKALIGN_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STKALIGN` reader - Stack 8-byte aligned on exception entry"] +pub struct STKALIGN_R(crate::FieldReader); +impl STKALIGN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STKALIGN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STKALIGN_A { + match self.bits { + false => STKALIGN_A::VALUE_0, + true => STKALIGN_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == STKALIGN_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == STKALIGN_A::VALUE_1 + } +} +impl core::ops::Deref for STKALIGN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 3 - Unaligned accesses generates a Hard Fault"] + #[inline(always)] + pub fn unalign_trp(&self) -> UNALIGN_TRP_R { + UNALIGN_TRP_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 9 - Stack 8-byte aligned on exception entry"] + #[inline(always)] + pub fn stkalign(&self) -> STKALIGN_R { + STKALIGN_R::new(((self.bits >> 9) & 0x01) != 0) + } +} +#[doc = "Configuration and Control Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccr](index.html) module"] +pub struct CCR_SPEC; +impl crate::RegisterSpec for CCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ccr::R](R) reader structure"] +impl crate::Readable for CCR_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CCR to value 0x0204"] +impl crate::Resettable for CCR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0204 + } +} diff --git a/pac/atsamc21n/src/system_control/cpuid.rs b/pac/atsamc21n/src/system_control/cpuid.rs new file mode 100644 index 000000000000..4157d7a94e97 --- /dev/null +++ b/pac/atsamc21n/src/system_control/cpuid.rs @@ -0,0 +1,133 @@ +#[doc = "Register `CPUID` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `REVISION` reader - Minor revision number"] +pub struct REVISION_R(crate::FieldReader); +impl REVISION_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REVISION_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REVISION_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PARTNO` reader - Processor Part Number, 0xC60=Cortex-M0+"] +pub struct PARTNO_R(crate::FieldReader); +impl PARTNO_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + PARTNO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PARTNO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ARCHITECTURE` reader - Processor Architecture, 0xC=ARMv6-M"] +pub struct ARCHITECTURE_R(crate::FieldReader); +impl ARCHITECTURE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ARCHITECTURE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ARCHITECTURE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VARIANT` reader - Major revision number"] +pub struct VARIANT_R(crate::FieldReader); +impl VARIANT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + VARIANT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VARIANT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IMPLEMENTER` reader - Implementer code, ARM=0x41"] +pub struct IMPLEMENTER_R(crate::FieldReader); +impl IMPLEMENTER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + IMPLEMENTER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IMPLEMENTER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:3 - Minor revision number"] + #[inline(always)] + pub fn revision(&self) -> REVISION_R { + REVISION_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:15 - Processor Part Number, 0xC60=Cortex-M0+"] + #[inline(always)] + pub fn partno(&self) -> PARTNO_R { + PARTNO_R::new(((self.bits >> 4) & 0x0fff) as u16) + } + #[doc = "Bits 16:19 - Processor Architecture, 0xC=ARMv6-M"] + #[inline(always)] + pub fn architecture(&self) -> ARCHITECTURE_R { + ARCHITECTURE_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bits 20:23 - Major revision number"] + #[inline(always)] + pub fn variant(&self) -> VARIANT_R { + VARIANT_R::new(((self.bits >> 20) & 0x0f) as u8) + } + #[doc = "Bits 24:31 - Implementer code, ARM=0x41"] + #[inline(always)] + pub fn implementer(&self) -> IMPLEMENTER_R { + IMPLEMENTER_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[doc = "CPUID Base Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cpuid](index.html) module"] +pub struct CPUID_SPEC; +impl crate::RegisterSpec for CPUID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cpuid::R](R) reader structure"] +impl crate::Readable for CPUID_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CPUID to value 0x410c_c601"] +impl crate::Resettable for CPUID_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x410c_c601 + } +} diff --git a/pac/atsamc21n/src/system_control/dfsr.rs b/pac/atsamc21n/src/system_control/dfsr.rs new file mode 100644 index 000000000000..948899af0905 --- /dev/null +++ b/pac/atsamc21n/src/system_control/dfsr.rs @@ -0,0 +1,301 @@ +#[doc = "Register `DFSR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DFSR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `HALTED` reader - Halt request debug event active"] +pub struct HALTED_R(crate::FieldReader); +impl HALTED_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HALTED_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HALTED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HALTED` writer - Halt request debug event active"] +pub struct HALTED_W<'a> { + w: &'a mut W, +} +impl<'a> HALTED_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `BKPT` reader - Breakpoint debug event"] +pub struct BKPT_R(crate::FieldReader); +impl BKPT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BKPT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BKPT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BKPT` writer - Breakpoint debug event"] +pub struct BKPT_W<'a> { + w: &'a mut W, +} +impl<'a> BKPT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `DWTTRAP` reader - DWT debug event"] +pub struct DWTTRAP_R(crate::FieldReader); +impl DWTTRAP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DWTTRAP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DWTTRAP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DWTTRAP` writer - DWT debug event"] +pub struct DWTTRAP_W<'a> { + w: &'a mut W, +} +impl<'a> DWTTRAP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `VCATCH` reader - Vector catch debug event"] +pub struct VCATCH_R(crate::FieldReader); +impl VCATCH_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + VCATCH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VCATCH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VCATCH` writer - Vector catch debug event"] +pub struct VCATCH_W<'a> { + w: &'a mut W, +} +impl<'a> VCATCH_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `EXTERNAL` reader - EDBGRQ debug event"] +pub struct EXTERNAL_R(crate::FieldReader); +impl EXTERNAL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTERNAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTERNAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTERNAL` writer - EDBGRQ debug event"] +pub struct EXTERNAL_W<'a> { + w: &'a mut W, +} +impl<'a> EXTERNAL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +impl R { + #[doc = "Bit 0 - Halt request debug event active"] + #[inline(always)] + pub fn halted(&self) -> HALTED_R { + HALTED_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Breakpoint debug event"] + #[inline(always)] + pub fn bkpt(&self) -> BKPT_R { + BKPT_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - DWT debug event"] + #[inline(always)] + pub fn dwttrap(&self) -> DWTTRAP_R { + DWTTRAP_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Vector catch debug event"] + #[inline(always)] + pub fn vcatch(&self) -> VCATCH_R { + VCATCH_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - EDBGRQ debug event"] + #[inline(always)] + pub fn external(&self) -> EXTERNAL_R { + EXTERNAL_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Halt request debug event active"] + #[inline(always)] + pub fn halted(&mut self) -> HALTED_W { + HALTED_W { w: self } + } + #[doc = "Bit 1 - Breakpoint debug event"] + #[inline(always)] + pub fn bkpt(&mut self) -> BKPT_W { + BKPT_W { w: self } + } + #[doc = "Bit 2 - DWT debug event"] + #[inline(always)] + pub fn dwttrap(&mut self) -> DWTTRAP_W { + DWTTRAP_W { w: self } + } + #[doc = "Bit 3 - Vector catch debug event"] + #[inline(always)] + pub fn vcatch(&mut self) -> VCATCH_W { + VCATCH_W { w: self } + } + #[doc = "Bit 4 - EDBGRQ debug event"] + #[inline(always)] + pub fn external(&mut self) -> EXTERNAL_W { + EXTERNAL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Fault Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dfsr](index.html) module"] +pub struct DFSR_SPEC; +impl crate::RegisterSpec for DFSR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dfsr::R](R) reader structure"] +impl crate::Readable for DFSR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dfsr::W](W) writer structure"] +impl crate::Writable for DFSR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DFSR to value 0"] +impl crate::Resettable for DFSR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/system_control/icsr.rs b/pac/atsamc21n/src/system_control/icsr.rs new file mode 100644 index 000000000000..7fe5fd412116 --- /dev/null +++ b/pac/atsamc21n/src/system_control/icsr.rs @@ -0,0 +1,704 @@ +#[doc = "Register `ICSR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ICSR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `VECTACTIVE` reader - Debug: Exception number of currently executing exception, or 0 if thread mode"] +pub struct VECTACTIVE_R(crate::FieldReader); +impl VECTACTIVE_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + VECTACTIVE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VECTACTIVE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VECTACTIVE` writer - Debug: Exception number of currently executing exception, or 0 if thread mode"] +pub struct VECTACTIVE_W<'a> { + w: &'a mut W, +} +impl<'a> VECTACTIVE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01ff) | (value as u32 & 0x01ff); + self.w + } +} +#[doc = "Field `VECTPENDING` reader - Exception number of the highest priority pending enabled exception"] +pub struct VECTPENDING_R(crate::FieldReader); +impl VECTPENDING_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + VECTPENDING_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VECTPENDING_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VECTPENDING` writer - Exception number of the highest priority pending enabled exception"] +pub struct VECTPENDING_W<'a> { + w: &'a mut W, +} +impl<'a> VECTPENDING_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01ff << 12)) | ((value as u32 & 0x01ff) << 12); + self.w + } +} +#[doc = "Field `ISRPENDING` reader - Debug: NVIC interrupt pending"] +pub struct ISRPENDING_R(crate::FieldReader); +impl ISRPENDING_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ISRPENDING_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ISRPENDING_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ISRPENDING` writer - Debug: NVIC interrupt pending"] +pub struct ISRPENDING_W<'a> { + w: &'a mut W, +} +impl<'a> ISRPENDING_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `ISRPREEMPT` reader - Debug: Pending exception serviced on exit from debug halt"] +pub struct ISRPREEMPT_R(crate::FieldReader); +impl ISRPREEMPT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ISRPREEMPT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ISRPREEMPT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ISRPREEMPT` writer - Debug: Pending exception serviced on exit from debug halt"] +pub struct ISRPREEMPT_W<'a> { + w: &'a mut W, +} +impl<'a> ISRPREEMPT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "SysTick exception clear-pending bit\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PENDSTCLR_A { + #[doc = "0: No effect"] + VALUE_0 = 0, + #[doc = "1: Removes the pending state from the SysTick exception"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PENDSTCLR_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PENDSTCLR` reader - SysTick exception clear-pending bit"] +pub struct PENDSTCLR_R(crate::FieldReader); +impl PENDSTCLR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDSTCLR_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PENDSTCLR_A { + match self.bits { + false => PENDSTCLR_A::VALUE_0, + true => PENDSTCLR_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == PENDSTCLR_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == PENDSTCLR_A::VALUE_1 + } +} +impl core::ops::Deref for PENDSTCLR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDSTCLR` writer - SysTick exception clear-pending bit"] +pub struct PENDSTCLR_W<'a> { + w: &'a mut W, +} +impl<'a> PENDSTCLR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PENDSTCLR_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "No effect"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(PENDSTCLR_A::VALUE_0) + } + #[doc = "Removes the pending state from the SysTick exception"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(PENDSTCLR_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "SysTick exception set-pending bit\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PENDSTSET_A { + #[doc = "0: Write: no effect; read: SysTick exception is not pending"] + VALUE_0 = 0, + #[doc = "1: Write: changes SysTick exception state to pending; read: SysTick exception is pending"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PENDSTSET_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PENDSTSET` reader - SysTick exception set-pending bit"] +pub struct PENDSTSET_R(crate::FieldReader); +impl PENDSTSET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDSTSET_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PENDSTSET_A { + match self.bits { + false => PENDSTSET_A::VALUE_0, + true => PENDSTSET_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == PENDSTSET_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == PENDSTSET_A::VALUE_1 + } +} +impl core::ops::Deref for PENDSTSET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDSTSET` writer - SysTick exception set-pending bit"] +pub struct PENDSTSET_W<'a> { + w: &'a mut W, +} +impl<'a> PENDSTSET_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PENDSTSET_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Write: no effect; read: SysTick exception is not pending"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(PENDSTSET_A::VALUE_0) + } + #[doc = "Write: changes SysTick exception state to pending; read: SysTick exception is pending"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(PENDSTSET_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "PendSV clear-pending bit\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PENDSVCLR_A { + #[doc = "0: No effect"] + VALUE_0 = 0, + #[doc = "1: Removes the pending state from the PendSV exception"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PENDSVCLR_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PENDSVCLR` reader - PendSV clear-pending bit"] +pub struct PENDSVCLR_R(crate::FieldReader); +impl PENDSVCLR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDSVCLR_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PENDSVCLR_A { + match self.bits { + false => PENDSVCLR_A::VALUE_0, + true => PENDSVCLR_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == PENDSVCLR_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == PENDSVCLR_A::VALUE_1 + } +} +impl core::ops::Deref for PENDSVCLR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDSVCLR` writer - PendSV clear-pending bit"] +pub struct PENDSVCLR_W<'a> { + w: &'a mut W, +} +impl<'a> PENDSVCLR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PENDSVCLR_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "No effect"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(PENDSVCLR_A::VALUE_0) + } + #[doc = "Removes the pending state from the PendSV exception"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(PENDSVCLR_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +#[doc = "PendSV set-pending bit\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum PENDSVSET_A { + #[doc = "0: Write: no effect; read: PendSV exception is not pending"] + VALUE_0 = 0, + #[doc = "1: Write: changes PendSV exception state to pending; read: PendSV exception is pending"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PENDSVSET_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PENDSVSET` reader - PendSV set-pending bit"] +pub struct PENDSVSET_R(crate::FieldReader); +impl PENDSVSET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PENDSVSET_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PENDSVSET_A { + match self.bits { + false => PENDSVSET_A::VALUE_0, + true => PENDSVSET_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == PENDSVSET_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == PENDSVSET_A::VALUE_1 + } +} +impl core::ops::Deref for PENDSVSET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDSVSET` writer - PendSV set-pending bit"] +pub struct PENDSVSET_W<'a> { + w: &'a mut W, +} +impl<'a> PENDSVSET_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PENDSVSET_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Write: no effect; read: PendSV exception is not pending"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(PENDSVSET_A::VALUE_0) + } + #[doc = "Write: changes PendSV exception state to pending; read: PendSV exception is pending"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(PENDSVSET_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "NMI set-pending bit\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum NMIPENDSET_A { + #[doc = "0: Write: no effect; read: NMI exception is not pending"] + VALUE_0 = 0, + #[doc = "1: Write: changes NMI exception state to pending; read: NMI exception is pending"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NMIPENDSET_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NMIPENDSET` reader - NMI set-pending bit"] +pub struct NMIPENDSET_R(crate::FieldReader); +impl NMIPENDSET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NMIPENDSET_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> NMIPENDSET_A { + match self.bits { + false => NMIPENDSET_A::VALUE_0, + true => NMIPENDSET_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == NMIPENDSET_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == NMIPENDSET_A::VALUE_1 + } +} +impl core::ops::Deref for NMIPENDSET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NMIPENDSET` writer - NMI set-pending bit"] +pub struct NMIPENDSET_W<'a> { + w: &'a mut W, +} +impl<'a> NMIPENDSET_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: NMIPENDSET_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Write: no effect; read: NMI exception is not pending"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(NMIPENDSET_A::VALUE_0) + } + #[doc = "Write: changes NMI exception state to pending; read: NMI exception is pending"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(NMIPENDSET_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bits 0:8 - Debug: Exception number of currently executing exception, or 0 if thread mode"] + #[inline(always)] + pub fn vectactive(&self) -> VECTACTIVE_R { + VECTACTIVE_R::new((self.bits & 0x01ff) as u16) + } + #[doc = "Bits 12:20 - Exception number of the highest priority pending enabled exception"] + #[inline(always)] + pub fn vectpending(&self) -> VECTPENDING_R { + VECTPENDING_R::new(((self.bits >> 12) & 0x01ff) as u16) + } + #[doc = "Bit 22 - Debug: NVIC interrupt pending"] + #[inline(always)] + pub fn isrpending(&self) -> ISRPENDING_R { + ISRPENDING_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Debug: Pending exception serviced on exit from debug halt"] + #[inline(always)] + pub fn isrpreempt(&self) -> ISRPREEMPT_R { + ISRPREEMPT_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 25 - SysTick exception clear-pending bit"] + #[inline(always)] + pub fn pendstclr(&self) -> PENDSTCLR_R { + PENDSTCLR_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - SysTick exception set-pending bit"] + #[inline(always)] + pub fn pendstset(&self) -> PENDSTSET_R { + PENDSTSET_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - PendSV clear-pending bit"] + #[inline(always)] + pub fn pendsvclr(&self) -> PENDSVCLR_R { + PENDSVCLR_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28 - PendSV set-pending bit"] + #[inline(always)] + pub fn pendsvset(&self) -> PENDSVSET_R { + PENDSVSET_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 31 - NMI set-pending bit"] + #[inline(always)] + pub fn nmipendset(&self) -> NMIPENDSET_R { + NMIPENDSET_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:8 - Debug: Exception number of currently executing exception, or 0 if thread mode"] + #[inline(always)] + pub fn vectactive(&mut self) -> VECTACTIVE_W { + VECTACTIVE_W { w: self } + } + #[doc = "Bits 12:20 - Exception number of the highest priority pending enabled exception"] + #[inline(always)] + pub fn vectpending(&mut self) -> VECTPENDING_W { + VECTPENDING_W { w: self } + } + #[doc = "Bit 22 - Debug: NVIC interrupt pending"] + #[inline(always)] + pub fn isrpending(&mut self) -> ISRPENDING_W { + ISRPENDING_W { w: self } + } + #[doc = "Bit 23 - Debug: Pending exception serviced on exit from debug halt"] + #[inline(always)] + pub fn isrpreempt(&mut self) -> ISRPREEMPT_W { + ISRPREEMPT_W { w: self } + } + #[doc = "Bit 25 - SysTick exception clear-pending bit"] + #[inline(always)] + pub fn pendstclr(&mut self) -> PENDSTCLR_W { + PENDSTCLR_W { w: self } + } + #[doc = "Bit 26 - SysTick exception set-pending bit"] + #[inline(always)] + pub fn pendstset(&mut self) -> PENDSTSET_W { + PENDSTSET_W { w: self } + } + #[doc = "Bit 27 - PendSV clear-pending bit"] + #[inline(always)] + pub fn pendsvclr(&mut self) -> PENDSVCLR_W { + PENDSVCLR_W { w: self } + } + #[doc = "Bit 28 - PendSV set-pending bit"] + #[inline(always)] + pub fn pendsvset(&mut self) -> PENDSVSET_W { + PENDSVSET_W { w: self } + } + #[doc = "Bit 31 - NMI set-pending bit"] + #[inline(always)] + pub fn nmipendset(&mut self) -> NMIPENDSET_W { + NMIPENDSET_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Control and State Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [icsr](index.html) module"] +pub struct ICSR_SPEC; +impl crate::RegisterSpec for ICSR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [icsr::R](R) reader structure"] +impl crate::Readable for ICSR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [icsr::W](W) writer structure"] +impl crate::Writable for ICSR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ICSR to value 0"] +impl crate::Resettable for ICSR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/system_control/scr.rs b/pac/atsamc21n/src/system_control/scr.rs new file mode 100644 index 000000000000..db9c54fe6f6f --- /dev/null +++ b/pac/atsamc21n/src/system_control/scr.rs @@ -0,0 +1,348 @@ +#[doc = "Register `SCR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SCR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Sleep-On-Exit when exiting Handler mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SLEEPONEXIT_A { + #[doc = "0: O not sleep when returning to Thread mode"] + VALUE_0 = 0, + #[doc = "1: Enter sleep, or deep sleep, on return from an ISR"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SLEEPONEXIT_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SLEEPONEXIT` reader - Sleep-On-Exit when exiting Handler mode"] +pub struct SLEEPONEXIT_R(crate::FieldReader); +impl SLEEPONEXIT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLEEPONEXIT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SLEEPONEXIT_A { + match self.bits { + false => SLEEPONEXIT_A::VALUE_0, + true => SLEEPONEXIT_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == SLEEPONEXIT_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == SLEEPONEXIT_A::VALUE_1 + } +} +impl core::ops::Deref for SLEEPONEXIT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLEEPONEXIT` writer - Sleep-On-Exit when exiting Handler mode"] +pub struct SLEEPONEXIT_W<'a> { + w: &'a mut W, +} +impl<'a> SLEEPONEXIT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SLEEPONEXIT_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "O not sleep when returning to Thread mode"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(SLEEPONEXIT_A::VALUE_0) + } + #[doc = "Enter sleep, or deep sleep, on return from an ISR"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(SLEEPONEXIT_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Uses Deep Sleep as low power mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SLEEPDEEP_A { + #[doc = "0: Sleep"] + VALUE_0 = 0, + #[doc = "1: Deep sleep"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SLEEPDEEP_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SLEEPDEEP` reader - Uses Deep Sleep as low power mode"] +pub struct SLEEPDEEP_R(crate::FieldReader); +impl SLEEPDEEP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLEEPDEEP_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SLEEPDEEP_A { + match self.bits { + false => SLEEPDEEP_A::VALUE_0, + true => SLEEPDEEP_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == SLEEPDEEP_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == SLEEPDEEP_A::VALUE_1 + } +} +impl core::ops::Deref for SLEEPDEEP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLEEPDEEP` writer - Uses Deep Sleep as low power mode"] +pub struct SLEEPDEEP_W<'a> { + w: &'a mut W, +} +impl<'a> SLEEPDEEP_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SLEEPDEEP_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Sleep"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(SLEEPDEEP_A::VALUE_0) + } + #[doc = "Deep sleep"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(SLEEPDEEP_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Send Event on Pending bit\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum SEVONPEND_A { + #[doc = "0: Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded"] + VALUE_0 = 0, + #[doc = "1: Enabled events and all interrupts, including disabled interrupts, can wakeup the processor"] + VALUE_1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SEVONPEND_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SEVONPEND` reader - Send Event on Pending bit"] +pub struct SEVONPEND_R(crate::FieldReader); +impl SEVONPEND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SEVONPEND_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SEVONPEND_A { + match self.bits { + false => SEVONPEND_A::VALUE_0, + true => SEVONPEND_A::VALUE_1, + } + } + #[doc = "Checks if the value of the field is `VALUE_0`"] + #[inline(always)] + pub fn is_value_0(&self) -> bool { + **self == SEVONPEND_A::VALUE_0 + } + #[doc = "Checks if the value of the field is `VALUE_1`"] + #[inline(always)] + pub fn is_value_1(&self) -> bool { + **self == SEVONPEND_A::VALUE_1 + } +} +impl core::ops::Deref for SEVONPEND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEVONPEND` writer - Send Event on Pending bit"] +pub struct SEVONPEND_W<'a> { + w: &'a mut W, +} +impl<'a> SEVONPEND_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SEVONPEND_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded"] + #[inline(always)] + pub fn value_0(self) -> &'a mut W { + self.variant(SEVONPEND_A::VALUE_0) + } + #[doc = "Enabled events and all interrupts, including disabled interrupts, can wakeup the processor"] + #[inline(always)] + pub fn value_1(self) -> &'a mut W { + self.variant(SEVONPEND_A::VALUE_1) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +impl R { + #[doc = "Bit 1 - Sleep-On-Exit when exiting Handler mode"] + #[inline(always)] + pub fn sleeponexit(&self) -> SLEEPONEXIT_R { + SLEEPONEXIT_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Uses Deep Sleep as low power mode"] + #[inline(always)] + pub fn sleepdeep(&self) -> SLEEPDEEP_R { + SLEEPDEEP_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 4 - Send Event on Pending bit"] + #[inline(always)] + pub fn sevonpend(&self) -> SEVONPEND_R { + SEVONPEND_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 1 - Sleep-On-Exit when exiting Handler mode"] + #[inline(always)] + pub fn sleeponexit(&mut self) -> SLEEPONEXIT_W { + SLEEPONEXIT_W { w: self } + } + #[doc = "Bit 2 - Uses Deep Sleep as low power mode"] + #[inline(always)] + pub fn sleepdeep(&mut self) -> SLEEPDEEP_W { + SLEEPDEEP_W { w: self } + } + #[doc = "Bit 4 - Send Event on Pending bit"] + #[inline(always)] + pub fn sevonpend(&mut self) -> SEVONPEND_W { + SEVONPEND_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "System Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [scr](index.html) module"] +pub struct SCR_SPEC; +impl crate::RegisterSpec for SCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [scr::R](R) reader structure"] +impl crate::Readable for SCR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [scr::W](W) writer structure"] +impl crate::Writable for SCR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SCR to value 0"] +impl crate::Resettable for SCR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/system_control/shcsr.rs b/pac/atsamc21n/src/system_control/shcsr.rs new file mode 100644 index 000000000000..bfba26ac06ad --- /dev/null +++ b/pac/atsamc21n/src/system_control/shcsr.rs @@ -0,0 +1,113 @@ +#[doc = "Register `SHCSR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SHCSR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SVCALLPENDED` reader - "] +pub struct SVCALLPENDED_R(crate::FieldReader); +impl SVCALLPENDED_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SVCALLPENDED_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SVCALLPENDED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SVCALLPENDED` writer - "] +pub struct SVCALLPENDED_W<'a> { + w: &'a mut W, +} +impl<'a> SVCALLPENDED_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 15"] + #[inline(always)] + pub fn svcallpended(&self) -> SVCALLPENDED_R { + SVCALLPENDED_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 15"] + #[inline(always)] + pub fn svcallpended(&mut self) -> SVCALLPENDED_W { + SVCALLPENDED_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "System Handler Control and State Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [shcsr](index.html) module"] +pub struct SHCSR_SPEC; +impl crate::RegisterSpec for SHCSR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [shcsr::R](R) reader structure"] +impl crate::Readable for SHCSR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [shcsr::W](W) writer structure"] +impl crate::Writable for SHCSR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SHCSR to value 0"] +impl crate::Resettable for SHCSR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/system_control/shpr2.rs b/pac/atsamc21n/src/system_control/shpr2.rs new file mode 100644 index 000000000000..5665d6a5e8a9 --- /dev/null +++ b/pac/atsamc21n/src/system_control/shpr2.rs @@ -0,0 +1,103 @@ +#[doc = "Register `SHPR2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SHPR2` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PRI_11` reader - Priority of system handler 11, SVCall"] +pub struct PRI_11_R(crate::FieldReader); +impl PRI_11_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRI_11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PRI_11_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRI_11` writer - Priority of system handler 11, SVCall"] +pub struct PRI_11_W<'a> { + w: &'a mut W, +} +impl<'a> PRI_11_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 24)) | ((value as u32 & 0xff) << 24); + self.w + } +} +impl R { + #[doc = "Bits 24:31 - Priority of system handler 11, SVCall"] + #[inline(always)] + pub fn pri_11(&self) -> PRI_11_R { + PRI_11_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 24:31 - Priority of system handler 11, SVCall"] + #[inline(always)] + pub fn pri_11(&mut self) -> PRI_11_W { + PRI_11_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "System Handler Priority Register 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [shpr2](index.html) module"] +pub struct SHPR2_SPEC; +impl crate::RegisterSpec for SHPR2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [shpr2::R](R) reader structure"] +impl crate::Readable for SHPR2_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [shpr2::W](W) writer structure"] +impl crate::Writable for SHPR2_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SHPR2 to value 0"] +impl crate::Resettable for SHPR2_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/system_control/shpr3.rs b/pac/atsamc21n/src/system_control/shpr3.rs new file mode 100644 index 000000000000..cb5a92c53503 --- /dev/null +++ b/pac/atsamc21n/src/system_control/shpr3.rs @@ -0,0 +1,140 @@ +#[doc = "Register `SHPR3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SHPR3` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PRI_14` reader - Priority of system handler 14, PendSV"] +pub struct PRI_14_R(crate::FieldReader); +impl PRI_14_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRI_14_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PRI_14_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRI_14` writer - Priority of system handler 14, PendSV"] +pub struct PRI_14_W<'a> { + w: &'a mut W, +} +impl<'a> PRI_14_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +#[doc = "Field `PRI_15` reader - Priority of system handler 15, SysTick exception"] +pub struct PRI_15_R(crate::FieldReader); +impl PRI_15_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRI_15_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PRI_15_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRI_15` writer - Priority of system handler 15, SysTick exception"] +pub struct PRI_15_W<'a> { + w: &'a mut W, +} +impl<'a> PRI_15_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 24)) | ((value as u32 & 0xff) << 24); + self.w + } +} +impl R { + #[doc = "Bits 16:23 - Priority of system handler 14, PendSV"] + #[inline(always)] + pub fn pri_14(&self) -> PRI_14_R { + PRI_14_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Priority of system handler 15, SysTick exception"] + #[inline(always)] + pub fn pri_15(&self) -> PRI_15_R { + PRI_15_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 16:23 - Priority of system handler 14, PendSV"] + #[inline(always)] + pub fn pri_14(&mut self) -> PRI_14_W { + PRI_14_W { w: self } + } + #[doc = "Bits 24:31 - Priority of system handler 15, SysTick exception"] + #[inline(always)] + pub fn pri_15(&mut self) -> PRI_15_W { + PRI_15_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "System Handler Priority Register 3\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [shpr3](index.html) module"] +pub struct SHPR3_SPEC; +impl crate::RegisterSpec for SHPR3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [shpr3::R](R) reader structure"] +impl crate::Readable for SHPR3_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [shpr3::W](W) writer structure"] +impl crate::Writable for SHPR3_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SHPR3 to value 0"] +impl crate::Resettable for SHPR3_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/system_control/vtor.rs b/pac/atsamc21n/src/system_control/vtor.rs new file mode 100644 index 000000000000..0ee4c7817817 --- /dev/null +++ b/pac/atsamc21n/src/system_control/vtor.rs @@ -0,0 +1,103 @@ +#[doc = "Register `VTOR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `VTOR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TBLOFF` reader - Vector table base offset"] +pub struct TBLOFF_R(crate::FieldReader); +impl TBLOFF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + TBLOFF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TBLOFF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TBLOFF` writer - Vector table base offset"] +pub struct TBLOFF_W<'a> { + w: &'a mut W, +} +impl<'a> TBLOFF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01ff_ffff << 7)) | ((value as u32 & 0x01ff_ffff) << 7); + self.w + } +} +impl R { + #[doc = "Bits 7:31 - Vector table base offset"] + #[inline(always)] + pub fn tbloff(&self) -> TBLOFF_R { + TBLOFF_R::new(((self.bits >> 7) & 0x01ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 7:31 - Vector table base offset"] + #[inline(always)] + pub fn tbloff(&mut self) -> TBLOFF_W { + TBLOFF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Vector Table Offset Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [vtor](index.html) module"] +pub struct VTOR_SPEC; +impl crate::RegisterSpec for VTOR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [vtor::R](R) reader structure"] +impl crate::Readable for VTOR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [vtor::W](W) writer structure"] +impl crate::Writable for VTOR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets VTOR to value 0"] +impl crate::Resettable for VTOR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/tc0.rs b/pac/atsamc21n/src/tc0.rs new file mode 100644 index 000000000000..86e973b276e7 --- /dev/null +++ b/pac/atsamc21n/src/tc0.rs @@ -0,0 +1,146 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved_0_count8: [u8; 0x38], +} +impl RegisterBlock { + #[doc = "0x00..0x38 - 32-bit Counter Mode"] + #[inline(always)] + pub fn count32(&self) -> &COUNT32 { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const COUNT32) } + } + #[doc = "0x00..0x34 - 16-bit Counter Mode"] + #[inline(always)] + pub fn count16(&self) -> &COUNT16 { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const COUNT16) } + } + #[doc = "0x00..0x32 - 8-bit Counter Mode"] + #[inline(always)] + pub fn count8(&self) -> &COUNT8 { + unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const COUNT8) } + } +} +#[doc = r"Register block"] +#[repr(C)] +pub struct COUNT8 { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - Control B Clear"] + pub ctrlbclr: crate::Reg, + #[doc = "0x05 - Control B Set"] + pub ctrlbset: crate::Reg, + #[doc = "0x06 - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x08 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x09 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x0a - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x0b - Status"] + pub status: crate::Reg, + #[doc = "0x0c - Waveform Generation Control"] + pub wave: crate::Reg, + #[doc = "0x0d - Control C"] + pub drvctrl: crate::Reg, + _reserved10: [u8; 0x01], + #[doc = "0x0f - Debug Control"] + pub dbgctrl: crate::Reg, + #[doc = "0x10 - Synchronization Status"] + pub syncbusy: crate::Reg, + #[doc = "0x14 - COUNT8 Count"] + pub count: crate::Reg, + _reserved13: [u8; 0x06], + #[doc = "0x1b - COUNT8 Period"] + pub per: crate::Reg, + #[doc = "0x1c - COUNT8 Compare and Capture"] + pub cc: [crate::Reg; 2], + _reserved15: [u8; 0x11], + #[doc = "0x2f - COUNT8 Period Buffer"] + pub perbuf: crate::Reg, + #[doc = "0x30 - COUNT8 Compare and Capture Buffer"] + pub ccbuf: [crate::Reg; 2], +} +#[doc = r"Register block"] +#[doc = "8-bit Counter Mode"] +pub mod count8; +#[doc = r"Register block"] +#[repr(C)] +pub struct COUNT16 { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - Control B Clear"] + pub ctrlbclr: crate::Reg, + #[doc = "0x05 - Control B Set"] + pub ctrlbset: crate::Reg, + #[doc = "0x06 - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x08 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x09 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x0a - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x0b - Status"] + pub status: crate::Reg, + #[doc = "0x0c - Waveform Generation Control"] + pub wave: crate::Reg, + #[doc = "0x0d - Control C"] + pub drvctrl: crate::Reg, + _reserved10: [u8; 0x01], + #[doc = "0x0f - Debug Control"] + pub dbgctrl: crate::Reg, + #[doc = "0x10 - Synchronization Status"] + pub syncbusy: crate::Reg, + #[doc = "0x14 - COUNT16 Count"] + pub count: crate::Reg, + _reserved13: [u8; 0x06], + #[doc = "0x1c - COUNT16 Compare and Capture"] + pub cc: [crate::Reg; 2], + _reserved14: [u8; 0x10], + #[doc = "0x30 - COUNT16 Compare and Capture Buffer"] + pub ccbuf: [crate::Reg; 2], +} +#[doc = r"Register block"] +#[doc = "16-bit Counter Mode"] +pub mod count16; +#[doc = r"Register block"] +#[repr(C)] +pub struct COUNT32 { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - Control B Clear"] + pub ctrlbclr: crate::Reg, + #[doc = "0x05 - Control B Set"] + pub ctrlbset: crate::Reg, + #[doc = "0x06 - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x08 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x09 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x0a - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x0b - Status"] + pub status: crate::Reg, + #[doc = "0x0c - Waveform Generation Control"] + pub wave: crate::Reg, + #[doc = "0x0d - Control C"] + pub drvctrl: crate::Reg, + _reserved10: [u8; 0x01], + #[doc = "0x0f - Debug Control"] + pub dbgctrl: crate::Reg, + #[doc = "0x10 - Synchronization Status"] + pub syncbusy: crate::Reg, + #[doc = "0x14 - COUNT32 Count"] + pub count: crate::Reg, + _reserved13: [u8; 0x04], + #[doc = "0x1c..0x24 - COUNT32 Compare and Capture"] + pub cc: [crate::Reg; 2], + _reserved14: [u8; 0x0c], + #[doc = "0x30..0x38 - COUNT32 Compare and Capture Buffer"] + pub ccbuf: [crate::Reg; 2], +} +#[doc = r"Register block"] +#[doc = "32-bit Counter Mode"] +pub mod count32; diff --git a/pac/atsamc21n/src/tc0/count16.rs b/pac/atsamc21n/src/tc0/count16.rs new file mode 100644 index 000000000000..5bd1e88c7efb --- /dev/null +++ b/pac/atsamc21n/src/tc0/count16.rs @@ -0,0 +1,60 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "CTRLBCLR register accessor: an alias for `Reg`"] +pub type CTRLBCLR = crate::Reg; +#[doc = "Control B Clear"] +pub mod ctrlbclr; +#[doc = "CTRLBSET register accessor: an alias for `Reg`"] +pub type CTRLBSET = crate::Reg; +#[doc = "Control B Set"] +pub mod ctrlbset; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "WAVE register accessor: an alias for `Reg`"] +pub type WAVE = crate::Reg; +#[doc = "Waveform Generation Control"] +pub mod wave; +#[doc = "DRVCTRL register accessor: an alias for `Reg`"] +pub type DRVCTRL = crate::Reg; +#[doc = "Control C"] +pub mod drvctrl; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Status"] +pub mod syncbusy; +#[doc = "COUNT register accessor: an alias for `Reg`"] +pub type COUNT = crate::Reg; +#[doc = "COUNT16 Count"] +pub mod count; +#[doc = "CC register accessor: an alias for `Reg`"] +pub type CC = crate::Reg; +#[doc = "COUNT16 Compare and Capture"] +pub mod cc; +#[doc = "CCBUF register accessor: an alias for `Reg`"] +pub type CCBUF = crate::Reg; +#[doc = "COUNT16 Compare and Capture Buffer"] +pub mod ccbuf; diff --git a/pac/atsamc21n/src/tc0/count16/cc.rs b/pac/atsamc21n/src/tc0/count16/cc.rs new file mode 100644 index 000000000000..b6f975905e31 --- /dev/null +++ b/pac/atsamc21n/src/tc0/count16/cc.rs @@ -0,0 +1,104 @@ +#[doc = "Register `CC[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CC[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CC` reader - Counter/Compare Value"] +pub struct CC_R(crate::FieldReader); +impl CC_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + CC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC` writer - Counter/Compare Value"] +pub struct CC_W<'a> { + w: &'a mut W, +} +impl<'a> CC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Counter/Compare Value"] + #[inline(always)] + pub fn cc(&self) -> CC_R { + CC_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Counter/Compare Value"] + #[inline(always)] + pub fn cc(&mut self) -> CC_W { + CC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT16 Compare and Capture\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc](index.html) module"] +pub struct CC_SPEC; +impl crate::RegisterSpec for CC_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [cc::R](R) reader structure"] +impl crate::Readable for CC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cc::W](W) writer structure"] +impl crate::Writable for CC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CC[%s] +to value 0"] +impl crate::Resettable for CC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/tc0/count16/ccbuf.rs b/pac/atsamc21n/src/tc0/count16/ccbuf.rs new file mode 100644 index 000000000000..2f922bba8d31 --- /dev/null +++ b/pac/atsamc21n/src/tc0/count16/ccbuf.rs @@ -0,0 +1,104 @@ +#[doc = "Register `CCBUF[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CCBUF[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CCBUF` reader - Counter/Compare Buffer Value"] +pub struct CCBUF_R(crate::FieldReader); +impl CCBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + CCBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUF` writer - Counter/Compare Buffer Value"] +pub struct CCBUF_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Counter/Compare Buffer Value"] + #[inline(always)] + pub fn ccbuf(&self) -> CCBUF_R { + CCBUF_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Counter/Compare Buffer Value"] + #[inline(always)] + pub fn ccbuf(&mut self) -> CCBUF_W { + CCBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT16 Compare and Capture Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccbuf](index.html) module"] +pub struct CCBUF_SPEC; +impl crate::RegisterSpec for CCBUF_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ccbuf::R](R) reader structure"] +impl crate::Readable for CCBUF_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ccbuf::W](W) writer structure"] +impl crate::Writable for CCBUF_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CCBUF[%s] +to value 0"] +impl crate::Resettable for CCBUF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/tc0/count16/count.rs b/pac/atsamc21n/src/tc0/count16/count.rs new file mode 100644 index 000000000000..5d26b509abb1 --- /dev/null +++ b/pac/atsamc21n/src/tc0/count16/count.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = value as u16; + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(self.bits as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT16 Count\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count](index.html) module"] +pub struct COUNT_SPEC; +impl crate::RegisterSpec for COUNT_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [count::R](R) reader structure"] +impl crate::Readable for COUNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count::W](W) writer structure"] +impl crate::Writable for COUNT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT to value 0"] +impl crate::Resettable for COUNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/tc0/count16/ctrla.rs b/pac/atsamc21n/src/tc0/count16/ctrla.rs new file mode 100644 index 000000000000..e1be912fdfcd --- /dev/null +++ b/pac/atsamc21n/src/tc0/count16/ctrla.rs @@ -0,0 +1,1049 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Timer Counter Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: Counter in 16-bit mode"] + COUNT16 = 0, + #[doc = "1: Counter in 8-bit mode"] + COUNT8 = 1, + #[doc = "2: Counter in 32-bit mode"] + COUNT32 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Timer Counter Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::COUNT16), + 1 => Some(MODE_A::COUNT8), + 2 => Some(MODE_A::COUNT32), + _ => None, + } + } + #[doc = "Checks if the value of the field is `COUNT16`"] + #[inline(always)] + pub fn is_count16(&self) -> bool { + **self == MODE_A::COUNT16 + } + #[doc = "Checks if the value of the field is `COUNT8`"] + #[inline(always)] + pub fn is_count8(&self) -> bool { + **self == MODE_A::COUNT8 + } + #[doc = "Checks if the value of the field is `COUNT32`"] + #[inline(always)] + pub fn is_count32(&self) -> bool { + **self == MODE_A::COUNT32 + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Timer Counter Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Counter in 16-bit mode"] + #[inline(always)] + pub fn count16(self) -> &'a mut W { + self.variant(MODE_A::COUNT16) + } + #[doc = "Counter in 8-bit mode"] + #[inline(always)] + pub fn count8(self) -> &'a mut W { + self.variant(MODE_A::COUNT8) + } + #[doc = "Counter in 32-bit mode"] + #[inline(always)] + pub fn count32(self) -> &'a mut W { + self.variant(MODE_A::COUNT32) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u32 & 0x03) << 2); + self.w + } +} +#[doc = "Prescaler and Counter Synchronization\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCSYNC_A { + #[doc = "0: Reload or reset the counter on next generic clock"] + GCLK = 0, + #[doc = "1: Reload or reset the counter on next prescaler clock"] + PRESC = 1, + #[doc = "2: Reload or reset the counter on next generic clock and reset the prescaler counter"] + RESYNC = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCSYNC_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCSYNC` reader - Prescaler and Counter Synchronization"] +pub struct PRESCSYNC_R(crate::FieldReader); +impl PRESCSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCSYNC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCSYNC_A::GCLK), + 1 => Some(PRESCSYNC_A::PRESC), + 2 => Some(PRESCSYNC_A::RESYNC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `GCLK`"] + #[inline(always)] + pub fn is_gclk(&self) -> bool { + **self == PRESCSYNC_A::GCLK + } + #[doc = "Checks if the value of the field is `PRESC`"] + #[inline(always)] + pub fn is_presc(&self) -> bool { + **self == PRESCSYNC_A::PRESC + } + #[doc = "Checks if the value of the field is `RESYNC`"] + #[inline(always)] + pub fn is_resync(&self) -> bool { + **self == PRESCSYNC_A::RESYNC + } +} +impl core::ops::Deref for PRESCSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCSYNC` writer - Prescaler and Counter Synchronization"] +pub struct PRESCSYNC_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCSYNC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCSYNC_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Reload or reset the counter on next generic clock"] + #[inline(always)] + pub fn gclk(self) -> &'a mut W { + self.variant(PRESCSYNC_A::GCLK) + } + #[doc = "Reload or reset the counter on next prescaler clock"] + #[inline(always)] + pub fn presc(self) -> &'a mut W { + self.variant(PRESCSYNC_A::PRESC) + } + #[doc = "Reload or reset the counter on next generic clock and reset the prescaler counter"] + #[inline(always)] + pub fn resync(self) -> &'a mut W { + self.variant(PRESCSYNC_A::RESYNC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u32 & 0x03) << 4); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - Clock On Demand"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - Clock On Demand"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: Prescaler: GCLK_TC"] + DIV1 = 0, + #[doc = "1: Prescaler: GCLK_TC/2"] + DIV2 = 1, + #[doc = "2: Prescaler: GCLK_TC/4"] + DIV4 = 2, + #[doc = "3: Prescaler: GCLK_TC/8"] + DIV8 = 3, + #[doc = "4: Prescaler: GCLK_TC/16"] + DIV16 = 4, + #[doc = "5: Prescaler: GCLK_TC/64"] + DIV64 = 5, + #[doc = "6: Prescaler: GCLK_TC/256"] + DIV256 = 6, + #[doc = "7: Prescaler: GCLK_TC/1024"] + DIV1024 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PRESCALER_A { + match self.bits { + 0 => PRESCALER_A::DIV1, + 1 => PRESCALER_A::DIV2, + 2 => PRESCALER_A::DIV4, + 3 => PRESCALER_A::DIV8, + 4 => PRESCALER_A::DIV16, + 5 => PRESCALER_A::DIV64, + 6 => PRESCALER_A::DIV256, + 7 => PRESCALER_A::DIV1024, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == PRESCALER_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PRESCALER_A::DIV1024 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Prescaler: GCLK_TC"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1) + } + #[doc = "Prescaler: GCLK_TC/2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "Prescaler: GCLK_TC/4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "Prescaler: GCLK_TC/8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "Prescaler: GCLK_TC/16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "Prescaler: GCLK_TC/64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "Prescaler: GCLK_TC/256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = "Prescaler: GCLK_TC/1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +#[doc = "Field `ALOCK` reader - Auto Lock"] +pub struct ALOCK_R(crate::FieldReader); +impl ALOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALOCK` writer - Auto Lock"] +pub struct ALOCK_W<'a> { + w: &'a mut W, +} +impl<'a> ALOCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `CAPTEN0` reader - Capture Channel 0 Enable"] +pub struct CAPTEN0_R(crate::FieldReader); +impl CAPTEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CAPTEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CAPTEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAPTEN0` writer - Capture Channel 0 Enable"] +pub struct CAPTEN0_W<'a> { + w: &'a mut W, +} +impl<'a> CAPTEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `CAPTEN1` reader - Capture Channel 1 Enable"] +pub struct CAPTEN1_R(crate::FieldReader); +impl CAPTEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CAPTEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CAPTEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAPTEN1` writer - Capture Channel 1 Enable"] +pub struct CAPTEN1_W<'a> { + w: &'a mut W, +} +impl<'a> CAPTEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `COPEN0` reader - Capture On Pin 0 Enable"] +pub struct COPEN0_R(crate::FieldReader); +impl COPEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COPEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COPEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COPEN0` writer - Capture On Pin 0 Enable"] +pub struct COPEN0_W<'a> { + w: &'a mut W, +} +impl<'a> COPEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `COPEN1` reader - Capture On Pin 1 Enable"] +pub struct COPEN1_R(crate::FieldReader); +impl COPEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COPEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COPEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COPEN1` writer - Capture On Pin 1 Enable"] +pub struct COPEN1_W<'a> { + w: &'a mut W, +} +impl<'a> COPEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Capture Mode Channel 0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CAPTMODE0_A { + #[doc = "0: Default capture"] + DEFAULT = 0, + #[doc = "1: Minimum capture"] + CAPTMIN = 1, + #[doc = "2: Maximum capture"] + CAPTMAX = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CAPTMODE0_A) -> Self { + variant as _ + } +} +#[doc = "Field `CAPTMODE0` reader - Capture Mode Channel 0"] +pub struct CAPTMODE0_R(crate::FieldReader); +impl CAPTMODE0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CAPTMODE0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CAPTMODE0_A::DEFAULT), + 1 => Some(CAPTMODE0_A::CAPTMIN), + 2 => Some(CAPTMODE0_A::CAPTMAX), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DEFAULT`"] + #[inline(always)] + pub fn is_default(&self) -> bool { + **self == CAPTMODE0_A::DEFAULT + } + #[doc = "Checks if the value of the field is `CAPTMIN`"] + #[inline(always)] + pub fn is_captmin(&self) -> bool { + **self == CAPTMODE0_A::CAPTMIN + } + #[doc = "Checks if the value of the field is `CAPTMAX`"] + #[inline(always)] + pub fn is_captmax(&self) -> bool { + **self == CAPTMODE0_A::CAPTMAX + } +} +impl core::ops::Deref for CAPTMODE0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAPTMODE0` writer - Capture Mode Channel 0"] +pub struct CAPTMODE0_W<'a> { + w: &'a mut W, +} +impl<'a> CAPTMODE0_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CAPTMODE0_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Default capture"] + #[inline(always)] + pub fn default(self) -> &'a mut W { + self.variant(CAPTMODE0_A::DEFAULT) + } + #[doc = "Minimum capture"] + #[inline(always)] + pub fn captmin(self) -> &'a mut W { + self.variant(CAPTMODE0_A::CAPTMIN) + } + #[doc = "Maximum capture"] + #[inline(always)] + pub fn captmax(self) -> &'a mut W { + self.variant(CAPTMODE0_A::CAPTMAX) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 24)) | ((value as u32 & 0x03) << 24); + self.w + } +} +#[doc = "Capture mode Channel 1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CAPTMODE1_A { + #[doc = "0: Default capture"] + DEFAULT = 0, + #[doc = "1: Minimum capture"] + CAPTMIN = 1, + #[doc = "2: Maximum capture"] + CAPTMAX = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CAPTMODE1_A) -> Self { + variant as _ + } +} +#[doc = "Field `CAPTMODE1` reader - Capture mode Channel 1"] +pub struct CAPTMODE1_R(crate::FieldReader); +impl CAPTMODE1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CAPTMODE1_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CAPTMODE1_A::DEFAULT), + 1 => Some(CAPTMODE1_A::CAPTMIN), + 2 => Some(CAPTMODE1_A::CAPTMAX), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DEFAULT`"] + #[inline(always)] + pub fn is_default(&self) -> bool { + **self == CAPTMODE1_A::DEFAULT + } + #[doc = "Checks if the value of the field is `CAPTMIN`"] + #[inline(always)] + pub fn is_captmin(&self) -> bool { + **self == CAPTMODE1_A::CAPTMIN + } + #[doc = "Checks if the value of the field is `CAPTMAX`"] + #[inline(always)] + pub fn is_captmax(&self) -> bool { + **self == CAPTMODE1_A::CAPTMAX + } +} +impl core::ops::Deref for CAPTMODE1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAPTMODE1` writer - Capture mode Channel 1"] +pub struct CAPTMODE1_W<'a> { + w: &'a mut W, +} +impl<'a> CAPTMODE1_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CAPTMODE1_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Default capture"] + #[inline(always)] + pub fn default(self) -> &'a mut W { + self.variant(CAPTMODE1_A::DEFAULT) + } + #[doc = "Minimum capture"] + #[inline(always)] + pub fn captmin(self) -> &'a mut W { + self.variant(CAPTMODE1_A::CAPTMIN) + } + #[doc = "Maximum capture"] + #[inline(always)] + pub fn captmax(self) -> &'a mut W { + self.variant(CAPTMODE1_A::CAPTMAX) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 27)) | ((value as u32 & 0x03) << 27); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:3 - Timer Counter Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bits 4:5 - Prescaler and Counter Synchronization"] + #[inline(always)] + pub fn prescsync(&self) -> PRESCSYNC_R { + PRESCSYNC_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Clock On Demand"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 11 - Auto Lock"] + #[inline(always)] + pub fn alock(&self) -> ALOCK_R { + ALOCK_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 16 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn capten0(&self) -> CAPTEN0_R { + CAPTEN0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn capten1(&self) -> CAPTEN1_R { + CAPTEN1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 20 - Capture On Pin 0 Enable"] + #[inline(always)] + pub fn copen0(&self) -> COPEN0_R { + COPEN0_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Capture On Pin 1 Enable"] + #[inline(always)] + pub fn copen1(&self) -> COPEN1_R { + COPEN1_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bits 24:25 - Capture Mode Channel 0"] + #[inline(always)] + pub fn captmode0(&self) -> CAPTMODE0_R { + CAPTMODE0_R::new(((self.bits >> 24) & 0x03) as u8) + } + #[doc = "Bits 27:28 - Capture mode Channel 1"] + #[inline(always)] + pub fn captmode1(&self) -> CAPTMODE1_R { + CAPTMODE1_R::new(((self.bits >> 27) & 0x03) as u8) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:3 - Timer Counter Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bits 4:5 - Prescaler and Counter Synchronization"] + #[inline(always)] + pub fn prescsync(&mut self) -> PRESCSYNC_W { + PRESCSYNC_W { w: self } + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - Clock On Demand"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Bit 11 - Auto Lock"] + #[inline(always)] + pub fn alock(&mut self) -> ALOCK_W { + ALOCK_W { w: self } + } + #[doc = "Bit 16 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn capten0(&mut self) -> CAPTEN0_W { + CAPTEN0_W { w: self } + } + #[doc = "Bit 17 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn capten1(&mut self) -> CAPTEN1_W { + CAPTEN1_W { w: self } + } + #[doc = "Bit 20 - Capture On Pin 0 Enable"] + #[inline(always)] + pub fn copen0(&mut self) -> COPEN0_W { + COPEN0_W { w: self } + } + #[doc = "Bit 21 - Capture On Pin 1 Enable"] + #[inline(always)] + pub fn copen1(&mut self) -> COPEN1_W { + COPEN1_W { w: self } + } + #[doc = "Bits 24:25 - Capture Mode Channel 0"] + #[inline(always)] + pub fn captmode0(&mut self) -> CAPTMODE0_W { + CAPTMODE0_W { w: self } + } + #[doc = "Bits 27:28 - Capture mode Channel 1"] + #[inline(always)] + pub fn captmode1(&mut self) -> CAPTMODE1_W { + CAPTMODE1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/tc0/count16/ctrlbclr.rs b/pac/atsamc21n/src/tc0/count16/ctrlbclr.rs new file mode 100644 index 000000000000..76265674036a --- /dev/null +++ b/pac/atsamc21n/src/tc0/count16/ctrlbclr.rs @@ -0,0 +1,345 @@ +#[doc = "Register `CTRLBCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Counter Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `LUPD` reader - Lock Update"] +pub struct LUPD_R(crate::FieldReader); +impl LUPD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LUPD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LUPD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LUPD` writer - Lock Update"] +pub struct LUPD_W<'a> { + w: &'a mut W, +} +impl<'a> LUPD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ONESHOT` reader - One-Shot on Counter"] +pub struct ONESHOT_R(crate::FieldReader); +impl ONESHOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONESHOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONESHOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONESHOT` writer - One-Shot on Counter"] +pub struct ONESHOT_W<'a> { + w: &'a mut W, +} +impl<'a> ONESHOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Force a start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force a stop"] + STOP = 2, + #[doc = "3: Force update of double-buffered register"] + UPDATE = 3, + #[doc = "4: Force a read synchronization of COUNT"] + READSYNC = 4, + #[doc = "5: One-shot DMA trigger"] + DMAOS = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NONE), + 1 => Some(CMD_A::RETRIGGER), + 2 => Some(CMD_A::STOP), + 3 => Some(CMD_A::UPDATE), + 4 => Some(CMD_A::READSYNC), + 5 => Some(CMD_A::DMAOS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == CMD_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == CMD_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == CMD_A::STOP + } + #[doc = "Checks if the value of the field is `UPDATE`"] + #[inline(always)] + pub fn is_update(&self) -> bool { + **self == CMD_A::UPDATE + } + #[doc = "Checks if the value of the field is `READSYNC`"] + #[inline(always)] + pub fn is_readsync(&self) -> bool { + **self == CMD_A::READSYNC + } + #[doc = "Checks if the value of the field is `DMAOS`"] + #[inline(always)] + pub fn is_dmaos(&self) -> bool { + **self == CMD_A::DMAOS + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMD_A::NONE) + } + #[doc = "Force a start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMD_A::RETRIGGER) + } + #[doc = "Force a stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMD_A::STOP) + } + #[doc = "Force update of double-buffered register"] + #[inline(always)] + pub fn update(self) -> &'a mut W { + self.variant(CMD_A::UPDATE) + } + #[doc = "Force a read synchronization of COUNT"] + #[inline(always)] + pub fn readsync(self) -> &'a mut W { + self.variant(CMD_A::READSYNC) + } + #[doc = "One-shot DMA trigger"] + #[inline(always)] + pub fn dmaos(self) -> &'a mut W { + self.variant(CMD_A::DMAOS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 5)) | ((value as u8 & 0x07) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&self) -> LUPD_R { + LUPD_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 5) & 0x07) as u8) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&mut self) -> LUPD_W { + LUPD_W { w: self } + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&mut self) -> ONESHOT_W { + ONESHOT_W { w: self } + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbclr](index.html) module"] +pub struct CTRLBCLR_SPEC; +impl crate::RegisterSpec for CTRLBCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbclr::R](R) reader structure"] +impl crate::Readable for CTRLBCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbclr::W](W) writer structure"] +impl crate::Writable for CTRLBCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLBCLR to value 0"] +impl crate::Resettable for CTRLBCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/tc0/count16/ctrlbset.rs b/pac/atsamc21n/src/tc0/count16/ctrlbset.rs new file mode 100644 index 000000000000..610914c9c7c8 --- /dev/null +++ b/pac/atsamc21n/src/tc0/count16/ctrlbset.rs @@ -0,0 +1,345 @@ +#[doc = "Register `CTRLBSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Counter Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `LUPD` reader - Lock Update"] +pub struct LUPD_R(crate::FieldReader); +impl LUPD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LUPD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LUPD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LUPD` writer - Lock Update"] +pub struct LUPD_W<'a> { + w: &'a mut W, +} +impl<'a> LUPD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ONESHOT` reader - One-Shot on Counter"] +pub struct ONESHOT_R(crate::FieldReader); +impl ONESHOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONESHOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONESHOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONESHOT` writer - One-Shot on Counter"] +pub struct ONESHOT_W<'a> { + w: &'a mut W, +} +impl<'a> ONESHOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Force a start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force a stop"] + STOP = 2, + #[doc = "3: Force update of double-buffered register"] + UPDATE = 3, + #[doc = "4: Force a read synchronization of COUNT"] + READSYNC = 4, + #[doc = "5: One-shot DMA trigger"] + DMAOS = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NONE), + 1 => Some(CMD_A::RETRIGGER), + 2 => Some(CMD_A::STOP), + 3 => Some(CMD_A::UPDATE), + 4 => Some(CMD_A::READSYNC), + 5 => Some(CMD_A::DMAOS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == CMD_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == CMD_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == CMD_A::STOP + } + #[doc = "Checks if the value of the field is `UPDATE`"] + #[inline(always)] + pub fn is_update(&self) -> bool { + **self == CMD_A::UPDATE + } + #[doc = "Checks if the value of the field is `READSYNC`"] + #[inline(always)] + pub fn is_readsync(&self) -> bool { + **self == CMD_A::READSYNC + } + #[doc = "Checks if the value of the field is `DMAOS`"] + #[inline(always)] + pub fn is_dmaos(&self) -> bool { + **self == CMD_A::DMAOS + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMD_A::NONE) + } + #[doc = "Force a start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMD_A::RETRIGGER) + } + #[doc = "Force a stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMD_A::STOP) + } + #[doc = "Force update of double-buffered register"] + #[inline(always)] + pub fn update(self) -> &'a mut W { + self.variant(CMD_A::UPDATE) + } + #[doc = "Force a read synchronization of COUNT"] + #[inline(always)] + pub fn readsync(self) -> &'a mut W { + self.variant(CMD_A::READSYNC) + } + #[doc = "One-shot DMA trigger"] + #[inline(always)] + pub fn dmaos(self) -> &'a mut W { + self.variant(CMD_A::DMAOS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 5)) | ((value as u8 & 0x07) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&self) -> LUPD_R { + LUPD_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 5) & 0x07) as u8) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&mut self) -> LUPD_W { + LUPD_W { w: self } + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&mut self) -> ONESHOT_W { + ONESHOT_W { w: self } + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbset](index.html) module"] +pub struct CTRLBSET_SPEC; +impl crate::RegisterSpec for CTRLBSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbset::R](R) reader structure"] +impl crate::Readable for CTRLBSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbset::W](W) writer structure"] +impl crate::Writable for CTRLBSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLBSET to value 0"] +impl crate::Resettable for CTRLBSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/tc0/count16/dbgctrl.rs b/pac/atsamc21n/src/tc0/count16/dbgctrl.rs new file mode 100644 index 000000000000..0383e70d0429 --- /dev/null +++ b/pac/atsamc21n/src/tc0/count16/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Run During Debug"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Run During Debug"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/tc0/count16/drvctrl.rs b/pac/atsamc21n/src/tc0/count16/drvctrl.rs new file mode 100644 index 000000000000..323926b4b22d --- /dev/null +++ b/pac/atsamc21n/src/tc0/count16/drvctrl.rs @@ -0,0 +1,160 @@ +#[doc = "Register `DRVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DRVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INVEN0` reader - Output Waveform Invert Enable 0"] +pub struct INVEN0_R(crate::FieldReader); +impl INVEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN0` writer - Output Waveform Invert Enable 0"] +pub struct INVEN0_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `INVEN1` reader - Output Waveform Invert Enable 1"] +pub struct INVEN1_R(crate::FieldReader); +impl INVEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN1` writer - Output Waveform Invert Enable 1"] +pub struct INVEN1_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - Output Waveform Invert Enable 0"] + #[inline(always)] + pub fn inven0(&self) -> INVEN0_R { + INVEN0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Output Waveform Invert Enable 1"] + #[inline(always)] + pub fn inven1(&self) -> INVEN1_R { + INVEN1_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Output Waveform Invert Enable 0"] + #[inline(always)] + pub fn inven0(&mut self) -> INVEN0_W { + INVEN0_W { w: self } + } + #[doc = "Bit 1 - Output Waveform Invert Enable 1"] + #[inline(always)] + pub fn inven1(&mut self) -> INVEN1_W { + INVEN1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control C\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [drvctrl](index.html) module"] +pub struct DRVCTRL_SPEC; +impl crate::RegisterSpec for DRVCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [drvctrl::R](R) reader structure"] +impl crate::Readable for DRVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [drvctrl::W](W) writer structure"] +impl crate::Writable for DRVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DRVCTRL to value 0"] +impl crate::Resettable for DRVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/tc0/count16/evctrl.rs b/pac/atsamc21n/src/tc0/count16/evctrl.rs new file mode 100644 index 000000000000..7d4c38d486c1 --- /dev/null +++ b/pac/atsamc21n/src/tc0/count16/evctrl.rs @@ -0,0 +1,465 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Event Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EVACT_A { + #[doc = "0: Event action disabled"] + OFF = 0, + #[doc = "1: Start, restart or retrigger TC on event"] + RETRIGGER = 1, + #[doc = "2: Count on event"] + COUNT = 2, + #[doc = "3: Start TC on event"] + START = 3, + #[doc = "4: Time stamp capture"] + STAMP = 4, + #[doc = "5: Period catured in CC0, pulse width in CC1"] + PPW = 5, + #[doc = "6: Period catured in CC1, pulse width in CC0"] + PWP = 6, + #[doc = "7: Pulse width capture"] + PW = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EVACT_A) -> Self { + variant as _ + } +} +#[doc = "Field `EVACT` reader - Event Action"] +pub struct EVACT_R(crate::FieldReader); +impl EVACT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVACT_A { + match self.bits { + 0 => EVACT_A::OFF, + 1 => EVACT_A::RETRIGGER, + 2 => EVACT_A::COUNT, + 3 => EVACT_A::START, + 4 => EVACT_A::STAMP, + 5 => EVACT_A::PPW, + 6 => EVACT_A::PWP, + 7 => EVACT_A::PW, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == EVACT_A::OFF + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == EVACT_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `COUNT`"] + #[inline(always)] + pub fn is_count(&self) -> bool { + **self == EVACT_A::COUNT + } + #[doc = "Checks if the value of the field is `START`"] + #[inline(always)] + pub fn is_start(&self) -> bool { + **self == EVACT_A::START + } + #[doc = "Checks if the value of the field is `STAMP`"] + #[inline(always)] + pub fn is_stamp(&self) -> bool { + **self == EVACT_A::STAMP + } + #[doc = "Checks if the value of the field is `PPW`"] + #[inline(always)] + pub fn is_ppw(&self) -> bool { + **self == EVACT_A::PPW + } + #[doc = "Checks if the value of the field is `PWP`"] + #[inline(always)] + pub fn is_pwp(&self) -> bool { + **self == EVACT_A::PWP + } + #[doc = "Checks if the value of the field is `PW`"] + #[inline(always)] + pub fn is_pw(&self) -> bool { + **self == EVACT_A::PW + } +} +impl core::ops::Deref for EVACT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT` writer - Event Action"] +pub struct EVACT_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EVACT_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Event action disabled"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(EVACT_A::OFF) + } + #[doc = "Start, restart or retrigger TC on event"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(EVACT_A::RETRIGGER) + } + #[doc = "Count on event"] + #[inline(always)] + pub fn count(self) -> &'a mut W { + self.variant(EVACT_A::COUNT) + } + #[doc = "Start TC on event"] + #[inline(always)] + pub fn start(self) -> &'a mut W { + self.variant(EVACT_A::START) + } + #[doc = "Time stamp capture"] + #[inline(always)] + pub fn stamp(self) -> &'a mut W { + self.variant(EVACT_A::STAMP) + } + #[doc = "Period catured in CC0, pulse width in CC1"] + #[inline(always)] + pub fn ppw(self) -> &'a mut W { + self.variant(EVACT_A::PPW) + } + #[doc = "Period catured in CC1, pulse width in CC0"] + #[inline(always)] + pub fn pwp(self) -> &'a mut W { + self.variant(EVACT_A::PWP) + } + #[doc = "Pulse width capture"] + #[inline(always)] + pub fn pw(self) -> &'a mut W { + self.variant(EVACT_A::PW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u16 & 0x07); + self.w + } +} +#[doc = "Field `TCINV` reader - TC Event Input Polarity"] +pub struct TCINV_R(crate::FieldReader); +impl TCINV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCINV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCINV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCINV` writer - TC Event Input Polarity"] +pub struct TCINV_W<'a> { + w: &'a mut W, +} +impl<'a> TCINV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `TCEI` reader - TC Event Enable"] +pub struct TCEI_R(crate::FieldReader); +impl TCEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCEI` writer - TC Event Enable"] +pub struct TCEI_W<'a> { + w: &'a mut W, +} +impl<'a> TCEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `OVFEO` reader - Event Output Enable"] +pub struct OVFEO_R(crate::FieldReader); +impl OVFEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVFEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVFEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVFEO` writer - Event Output Enable"] +pub struct OVFEO_W<'a> { + w: &'a mut W, +} +impl<'a> OVFEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `MCEO0` reader - MC Event Output Enable 0"] +pub struct MCEO0_R(crate::FieldReader); +impl MCEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO0` writer - MC Event Output Enable 0"] +pub struct MCEO0_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u16 & 0x01) << 12); + self.w + } +} +#[doc = "Field `MCEO1` reader - MC Event Output Enable 1"] +pub struct MCEO1_R(crate::FieldReader); +impl MCEO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO1` writer - MC Event Output Enable 1"] +pub struct MCEO1_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u16 & 0x01) << 13); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Event Action"] + #[inline(always)] + pub fn evact(&self) -> EVACT_R { + EVACT_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 4 - TC Event Input Polarity"] + #[inline(always)] + pub fn tcinv(&self) -> TCINV_R { + TCINV_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - TC Event Enable"] + #[inline(always)] + pub fn tcei(&self) -> TCEI_R { + TCEI_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 8 - Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&self) -> OVFEO_R { + OVFEO_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 12 - MC Event Output Enable 0"] + #[inline(always)] + pub fn mceo0(&self) -> MCEO0_R { + MCEO0_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - MC Event Output Enable 1"] + #[inline(always)] + pub fn mceo1(&self) -> MCEO1_R { + MCEO1_R::new(((self.bits >> 13) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Event Action"] + #[inline(always)] + pub fn evact(&mut self) -> EVACT_W { + EVACT_W { w: self } + } + #[doc = "Bit 4 - TC Event Input Polarity"] + #[inline(always)] + pub fn tcinv(&mut self) -> TCINV_W { + TCINV_W { w: self } + } + #[doc = "Bit 5 - TC Event Enable"] + #[inline(always)] + pub fn tcei(&mut self) -> TCEI_W { + TCEI_W { w: self } + } + #[doc = "Bit 8 - Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&mut self) -> OVFEO_W { + OVFEO_W { w: self } + } + #[doc = "Bit 12 - MC Event Output Enable 0"] + #[inline(always)] + pub fn mceo0(&mut self) -> MCEO0_W { + MCEO0_W { w: self } + } + #[doc = "Bit 13 - MC Event Output Enable 1"] + #[inline(always)] + pub fn mceo1(&mut self) -> MCEO1_W { + MCEO1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/tc0/count16/intenclr.rs b/pac/atsamc21n/src/tc0/count16/intenclr.rs new file mode 100644 index 000000000000..af01ef5b7dca --- /dev/null +++ b/pac/atsamc21n/src/tc0/count16/intenclr.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - OVF Interrupt Disable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - OVF Interrupt Disable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - ERR Interrupt Disable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - ERR Interrupt Disable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MC0` reader - MC Interrupt Disable 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - MC Interrupt Disable 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - MC Interrupt Disable 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - MC Interrupt Disable 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - OVF Interrupt Disable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ERR Interrupt Disable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - MC Interrupt Disable 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - MC Interrupt Disable 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - OVF Interrupt Disable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - ERR Interrupt Disable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 4 - MC Interrupt Disable 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - MC Interrupt Disable 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/tc0/count16/intenset.rs b/pac/atsamc21n/src/tc0/count16/intenset.rs new file mode 100644 index 000000000000..0e1883a2f20a --- /dev/null +++ b/pac/atsamc21n/src/tc0/count16/intenset.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - OVF Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - OVF Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - ERR Interrupt Enable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - ERR Interrupt Enable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MC0` reader - MC Interrupt Enable 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - MC Interrupt Enable 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - MC Interrupt Enable 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - MC Interrupt Enable 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - OVF Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ERR Interrupt Enable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - MC Interrupt Enable 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - MC Interrupt Enable 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - OVF Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - ERR Interrupt Enable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 4 - MC Interrupt Enable 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - MC Interrupt Enable 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/tc0/count16/intflag.rs b/pac/atsamc21n/src/tc0/count16/intflag.rs new file mode 100644 index 000000000000..1dddffaf8e7f --- /dev/null +++ b/pac/atsamc21n/src/tc0/count16/intflag.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - OVF Interrupt Flag"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - OVF Interrupt Flag"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - ERR Interrupt Flag"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - ERR Interrupt Flag"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MC0` reader - MC Interrupt Flag 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - MC Interrupt Flag 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - MC Interrupt Flag 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - MC Interrupt Flag 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - OVF Interrupt Flag"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ERR Interrupt Flag"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - MC Interrupt Flag 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - MC Interrupt Flag 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - OVF Interrupt Flag"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - ERR Interrupt Flag"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 4 - MC Interrupt Flag 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - MC Interrupt Flag 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/tc0/count16/status.rs b/pac/atsamc21n/src/tc0/count16/status.rs new file mode 100644 index 000000000000..5088af446830 --- /dev/null +++ b/pac/atsamc21n/src/tc0/count16/status.rs @@ -0,0 +1,301 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `STOP` reader - Stop Status Flag"] +pub struct STOP_R(crate::FieldReader); +impl STOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STOP` writer - Stop Status Flag"] +pub struct STOP_W<'a> { + w: &'a mut W, +} +impl<'a> STOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SLAVE` reader - Slave Status Flag"] +pub struct SLAVE_R(crate::FieldReader); +impl SLAVE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLAVE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SLAVE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLAVE` writer - Slave Status Flag"] +pub struct SLAVE_W<'a> { + w: &'a mut W, +} +impl<'a> SLAVE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PERBUFV` reader - Synchronization Busy Status"] +pub struct PERBUFV_R(crate::FieldReader); +impl PERBUFV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PERBUFV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERBUFV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERBUFV` writer - Synchronization Busy Status"] +pub struct PERBUFV_W<'a> { + w: &'a mut W, +} +impl<'a> PERBUFV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CCBUFV0` reader - Compare channel buffer 0 valid"] +pub struct CCBUFV0_R(crate::FieldReader); +impl CCBUFV0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBUFV0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUFV0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUFV0` writer - Compare channel buffer 0 valid"] +pub struct CCBUFV0_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUFV0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `CCBUFV1` reader - Compare channel buffer 1 valid"] +pub struct CCBUFV1_R(crate::FieldReader); +impl CCBUFV1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBUFV1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUFV1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUFV1` writer - Compare channel buffer 1 valid"] +pub struct CCBUFV1_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUFV1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Stop Status Flag"] + #[inline(always)] + pub fn stop(&self) -> STOP_R { + STOP_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Slave Status Flag"] + #[inline(always)] + pub fn slave(&self) -> SLAVE_R { + SLAVE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 3 - Synchronization Busy Status"] + #[inline(always)] + pub fn perbufv(&self) -> PERBUFV_R { + PERBUFV_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Compare channel buffer 0 valid"] + #[inline(always)] + pub fn ccbufv0(&self) -> CCBUFV0_R { + CCBUFV0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Compare channel buffer 1 valid"] + #[inline(always)] + pub fn ccbufv1(&self) -> CCBUFV1_R { + CCBUFV1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Stop Status Flag"] + #[inline(always)] + pub fn stop(&mut self) -> STOP_W { + STOP_W { w: self } + } + #[doc = "Bit 1 - Slave Status Flag"] + #[inline(always)] + pub fn slave(&mut self) -> SLAVE_W { + SLAVE_W { w: self } + } + #[doc = "Bit 3 - Synchronization Busy Status"] + #[inline(always)] + pub fn perbufv(&mut self) -> PERBUFV_W { + PERBUFV_W { w: self } + } + #[doc = "Bit 4 - Compare channel buffer 0 valid"] + #[inline(always)] + pub fn ccbufv0(&mut self) -> CCBUFV0_W { + CCBUFV0_W { w: self } + } + #[doc = "Bit 5 - Compare channel buffer 1 valid"] + #[inline(always)] + pub fn ccbufv1(&mut self) -> CCBUFV1_W { + CCBUFV1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0x01"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pac/atsamc21n/src/tc0/count16/syncbusy.rs b/pac/atsamc21n/src/tc0/count16/syncbusy.rs new file mode 100644 index 000000000000..7ad8d91a84de --- /dev/null +++ b/pac/atsamc21n/src/tc0/count16/syncbusy.rs @@ -0,0 +1,193 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - swrst"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLB` reader - CTRLB"] +pub struct CTRLB_R(crate::FieldReader); +impl CTRLB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STATUS` reader - STATUS"] +pub struct STATUS_R(crate::FieldReader); +impl STATUS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STATUS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STATUS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` reader - Counter"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` reader - Period"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC0` reader - Compare Channel 0"] +pub struct CC0_R(crate::FieldReader); +impl CC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC1` reader - Compare Channel 1"] +pub struct CC1_R(crate::FieldReader); +impl CC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - swrst"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - CTRLB"] + #[inline(always)] + pub fn ctrlb(&self) -> CTRLB_R { + CTRLB_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - STATUS"] + #[inline(always)] + pub fn status(&self) -> STATUS_R { + STATUS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Counter"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Period"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Compare Channel 0"] + #[inline(always)] + pub fn cc0(&self) -> CC0_R { + CC0_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Compare Channel 1"] + #[inline(always)] + pub fn cc1(&self) -> CC1_R { + CC1_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +#[doc = "Synchronization Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/tc0/count16/wave.rs b/pac/atsamc21n/src/tc0/count16/wave.rs new file mode 100644 index 000000000000..46061b24b75d --- /dev/null +++ b/pac/atsamc21n/src/tc0/count16/wave.rs @@ -0,0 +1,178 @@ +#[doc = "Register `WAVE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WAVE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Waveform Generation Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WAVEGEN_A { + #[doc = "0: Normal frequency"] + NFRQ = 0, + #[doc = "1: Match frequency"] + MFRQ = 1, + #[doc = "2: Normal PWM"] + NPWM = 2, + #[doc = "3: Match PWM"] + MPWM = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WAVEGEN_A) -> Self { + variant as _ + } +} +#[doc = "Field `WAVEGEN` reader - Waveform Generation Mode"] +pub struct WAVEGEN_R(crate::FieldReader); +impl WAVEGEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WAVEGEN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> WAVEGEN_A { + match self.bits { + 0 => WAVEGEN_A::NFRQ, + 1 => WAVEGEN_A::MFRQ, + 2 => WAVEGEN_A::NPWM, + 3 => WAVEGEN_A::MPWM, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NFRQ`"] + #[inline(always)] + pub fn is_nfrq(&self) -> bool { + **self == WAVEGEN_A::NFRQ + } + #[doc = "Checks if the value of the field is `MFRQ`"] + #[inline(always)] + pub fn is_mfrq(&self) -> bool { + **self == WAVEGEN_A::MFRQ + } + #[doc = "Checks if the value of the field is `NPWM`"] + #[inline(always)] + pub fn is_npwm(&self) -> bool { + **self == WAVEGEN_A::NPWM + } + #[doc = "Checks if the value of the field is `MPWM`"] + #[inline(always)] + pub fn is_mpwm(&self) -> bool { + **self == WAVEGEN_A::MPWM + } +} +impl core::ops::Deref for WAVEGEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAVEGEN` writer - Waveform Generation Mode"] +pub struct WAVEGEN_W<'a> { + w: &'a mut W, +} +impl<'a> WAVEGEN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WAVEGEN_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Normal frequency"] + #[inline(always)] + pub fn nfrq(self) -> &'a mut W { + self.variant(WAVEGEN_A::NFRQ) + } + #[doc = "Match frequency"] + #[inline(always)] + pub fn mfrq(self) -> &'a mut W { + self.variant(WAVEGEN_A::MFRQ) + } + #[doc = "Normal PWM"] + #[inline(always)] + pub fn npwm(self) -> &'a mut W { + self.variant(WAVEGEN_A::NPWM) + } + #[doc = "Match PWM"] + #[inline(always)] + pub fn mpwm(self) -> &'a mut W { + self.variant(WAVEGEN_A::MPWM) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u8 & 0x03); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Waveform Generation Mode"] + #[inline(always)] + pub fn wavegen(&self) -> WAVEGEN_R { + WAVEGEN_R::new((self.bits & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Waveform Generation Mode"] + #[inline(always)] + pub fn wavegen(&mut self) -> WAVEGEN_W { + WAVEGEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Waveform Generation Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wave](index.html) module"] +pub struct WAVE_SPEC; +impl crate::RegisterSpec for WAVE_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [wave::R](R) reader structure"] +impl crate::Readable for WAVE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wave::W](W) writer structure"] +impl crate::Writable for WAVE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WAVE to value 0"] +impl crate::Resettable for WAVE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/tc0/count32.rs b/pac/atsamc21n/src/tc0/count32.rs new file mode 100644 index 000000000000..9062acfbbd7f --- /dev/null +++ b/pac/atsamc21n/src/tc0/count32.rs @@ -0,0 +1,60 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "CTRLBCLR register accessor: an alias for `Reg`"] +pub type CTRLBCLR = crate::Reg; +#[doc = "Control B Clear"] +pub mod ctrlbclr; +#[doc = "CTRLBSET register accessor: an alias for `Reg`"] +pub type CTRLBSET = crate::Reg; +#[doc = "Control B Set"] +pub mod ctrlbset; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "WAVE register accessor: an alias for `Reg`"] +pub type WAVE = crate::Reg; +#[doc = "Waveform Generation Control"] +pub mod wave; +#[doc = "DRVCTRL register accessor: an alias for `Reg`"] +pub type DRVCTRL = crate::Reg; +#[doc = "Control C"] +pub mod drvctrl; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Status"] +pub mod syncbusy; +#[doc = "COUNT register accessor: an alias for `Reg`"] +pub type COUNT = crate::Reg; +#[doc = "COUNT32 Count"] +pub mod count; +#[doc = "CC register accessor: an alias for `Reg`"] +pub type CC = crate::Reg; +#[doc = "COUNT32 Compare and Capture"] +pub mod cc; +#[doc = "CCBUF register accessor: an alias for `Reg`"] +pub type CCBUF = crate::Reg; +#[doc = "COUNT32 Compare and Capture Buffer"] +pub mod ccbuf; diff --git a/pac/atsamc21n/src/tc0/count32/cc.rs b/pac/atsamc21n/src/tc0/count32/cc.rs new file mode 100644 index 000000000000..512a1e01ffd4 --- /dev/null +++ b/pac/atsamc21n/src/tc0/count32/cc.rs @@ -0,0 +1,104 @@ +#[doc = "Register `CC[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CC[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CC` reader - Counter/Compare Value"] +pub struct CC_R(crate::FieldReader); +impl CC_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC` writer - Counter/Compare Value"] +pub struct CC_W<'a> { + w: &'a mut W, +} +impl<'a> CC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Counter/Compare Value"] + #[inline(always)] + pub fn cc(&self) -> CC_R { + CC_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Counter/Compare Value"] + #[inline(always)] + pub fn cc(&mut self) -> CC_W { + CC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT32 Compare and Capture\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc](index.html) module"] +pub struct CC_SPEC; +impl crate::RegisterSpec for CC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cc::R](R) reader structure"] +impl crate::Readable for CC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cc::W](W) writer structure"] +impl crate::Writable for CC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CC[%s] +to value 0"] +impl crate::Resettable for CC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/tc0/count32/ccbuf.rs b/pac/atsamc21n/src/tc0/count32/ccbuf.rs new file mode 100644 index 000000000000..9fb2d9f8f66c --- /dev/null +++ b/pac/atsamc21n/src/tc0/count32/ccbuf.rs @@ -0,0 +1,104 @@ +#[doc = "Register `CCBUF[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CCBUF[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CCBUF` reader - Counter/Compare Buffer Value"] +pub struct CCBUF_R(crate::FieldReader); +impl CCBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CCBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUF` writer - Counter/Compare Buffer Value"] +pub struct CCBUF_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Counter/Compare Buffer Value"] + #[inline(always)] + pub fn ccbuf(&self) -> CCBUF_R { + CCBUF_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Counter/Compare Buffer Value"] + #[inline(always)] + pub fn ccbuf(&mut self) -> CCBUF_W { + CCBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT32 Compare and Capture Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccbuf](index.html) module"] +pub struct CCBUF_SPEC; +impl crate::RegisterSpec for CCBUF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ccbuf::R](R) reader structure"] +impl crate::Readable for CCBUF_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ccbuf::W](W) writer structure"] +impl crate::Writable for CCBUF_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CCBUF[%s] +to value 0"] +impl crate::Resettable for CCBUF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/tc0/count32/count.rs b/pac/atsamc21n/src/tc0/count32/count.rs new file mode 100644 index 000000000000..9aea527a8b3c --- /dev/null +++ b/pac/atsamc21n/src/tc0/count32/count.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = value as u32; + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(self.bits as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT32 Count\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count](index.html) module"] +pub struct COUNT_SPEC; +impl crate::RegisterSpec for COUNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [count::R](R) reader structure"] +impl crate::Readable for COUNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count::W](W) writer structure"] +impl crate::Writable for COUNT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT to value 0"] +impl crate::Resettable for COUNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/tc0/count32/ctrla.rs b/pac/atsamc21n/src/tc0/count32/ctrla.rs new file mode 100644 index 000000000000..e1be912fdfcd --- /dev/null +++ b/pac/atsamc21n/src/tc0/count32/ctrla.rs @@ -0,0 +1,1049 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Timer Counter Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: Counter in 16-bit mode"] + COUNT16 = 0, + #[doc = "1: Counter in 8-bit mode"] + COUNT8 = 1, + #[doc = "2: Counter in 32-bit mode"] + COUNT32 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Timer Counter Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::COUNT16), + 1 => Some(MODE_A::COUNT8), + 2 => Some(MODE_A::COUNT32), + _ => None, + } + } + #[doc = "Checks if the value of the field is `COUNT16`"] + #[inline(always)] + pub fn is_count16(&self) -> bool { + **self == MODE_A::COUNT16 + } + #[doc = "Checks if the value of the field is `COUNT8`"] + #[inline(always)] + pub fn is_count8(&self) -> bool { + **self == MODE_A::COUNT8 + } + #[doc = "Checks if the value of the field is `COUNT32`"] + #[inline(always)] + pub fn is_count32(&self) -> bool { + **self == MODE_A::COUNT32 + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Timer Counter Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Counter in 16-bit mode"] + #[inline(always)] + pub fn count16(self) -> &'a mut W { + self.variant(MODE_A::COUNT16) + } + #[doc = "Counter in 8-bit mode"] + #[inline(always)] + pub fn count8(self) -> &'a mut W { + self.variant(MODE_A::COUNT8) + } + #[doc = "Counter in 32-bit mode"] + #[inline(always)] + pub fn count32(self) -> &'a mut W { + self.variant(MODE_A::COUNT32) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u32 & 0x03) << 2); + self.w + } +} +#[doc = "Prescaler and Counter Synchronization\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCSYNC_A { + #[doc = "0: Reload or reset the counter on next generic clock"] + GCLK = 0, + #[doc = "1: Reload or reset the counter on next prescaler clock"] + PRESC = 1, + #[doc = "2: Reload or reset the counter on next generic clock and reset the prescaler counter"] + RESYNC = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCSYNC_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCSYNC` reader - Prescaler and Counter Synchronization"] +pub struct PRESCSYNC_R(crate::FieldReader); +impl PRESCSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCSYNC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCSYNC_A::GCLK), + 1 => Some(PRESCSYNC_A::PRESC), + 2 => Some(PRESCSYNC_A::RESYNC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `GCLK`"] + #[inline(always)] + pub fn is_gclk(&self) -> bool { + **self == PRESCSYNC_A::GCLK + } + #[doc = "Checks if the value of the field is `PRESC`"] + #[inline(always)] + pub fn is_presc(&self) -> bool { + **self == PRESCSYNC_A::PRESC + } + #[doc = "Checks if the value of the field is `RESYNC`"] + #[inline(always)] + pub fn is_resync(&self) -> bool { + **self == PRESCSYNC_A::RESYNC + } +} +impl core::ops::Deref for PRESCSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCSYNC` writer - Prescaler and Counter Synchronization"] +pub struct PRESCSYNC_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCSYNC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCSYNC_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Reload or reset the counter on next generic clock"] + #[inline(always)] + pub fn gclk(self) -> &'a mut W { + self.variant(PRESCSYNC_A::GCLK) + } + #[doc = "Reload or reset the counter on next prescaler clock"] + #[inline(always)] + pub fn presc(self) -> &'a mut W { + self.variant(PRESCSYNC_A::PRESC) + } + #[doc = "Reload or reset the counter on next generic clock and reset the prescaler counter"] + #[inline(always)] + pub fn resync(self) -> &'a mut W { + self.variant(PRESCSYNC_A::RESYNC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u32 & 0x03) << 4); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - Clock On Demand"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - Clock On Demand"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: Prescaler: GCLK_TC"] + DIV1 = 0, + #[doc = "1: Prescaler: GCLK_TC/2"] + DIV2 = 1, + #[doc = "2: Prescaler: GCLK_TC/4"] + DIV4 = 2, + #[doc = "3: Prescaler: GCLK_TC/8"] + DIV8 = 3, + #[doc = "4: Prescaler: GCLK_TC/16"] + DIV16 = 4, + #[doc = "5: Prescaler: GCLK_TC/64"] + DIV64 = 5, + #[doc = "6: Prescaler: GCLK_TC/256"] + DIV256 = 6, + #[doc = "7: Prescaler: GCLK_TC/1024"] + DIV1024 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PRESCALER_A { + match self.bits { + 0 => PRESCALER_A::DIV1, + 1 => PRESCALER_A::DIV2, + 2 => PRESCALER_A::DIV4, + 3 => PRESCALER_A::DIV8, + 4 => PRESCALER_A::DIV16, + 5 => PRESCALER_A::DIV64, + 6 => PRESCALER_A::DIV256, + 7 => PRESCALER_A::DIV1024, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == PRESCALER_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PRESCALER_A::DIV1024 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Prescaler: GCLK_TC"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1) + } + #[doc = "Prescaler: GCLK_TC/2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "Prescaler: GCLK_TC/4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "Prescaler: GCLK_TC/8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "Prescaler: GCLK_TC/16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "Prescaler: GCLK_TC/64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "Prescaler: GCLK_TC/256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = "Prescaler: GCLK_TC/1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +#[doc = "Field `ALOCK` reader - Auto Lock"] +pub struct ALOCK_R(crate::FieldReader); +impl ALOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALOCK` writer - Auto Lock"] +pub struct ALOCK_W<'a> { + w: &'a mut W, +} +impl<'a> ALOCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `CAPTEN0` reader - Capture Channel 0 Enable"] +pub struct CAPTEN0_R(crate::FieldReader); +impl CAPTEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CAPTEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CAPTEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAPTEN0` writer - Capture Channel 0 Enable"] +pub struct CAPTEN0_W<'a> { + w: &'a mut W, +} +impl<'a> CAPTEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `CAPTEN1` reader - Capture Channel 1 Enable"] +pub struct CAPTEN1_R(crate::FieldReader); +impl CAPTEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CAPTEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CAPTEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAPTEN1` writer - Capture Channel 1 Enable"] +pub struct CAPTEN1_W<'a> { + w: &'a mut W, +} +impl<'a> CAPTEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `COPEN0` reader - Capture On Pin 0 Enable"] +pub struct COPEN0_R(crate::FieldReader); +impl COPEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COPEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COPEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COPEN0` writer - Capture On Pin 0 Enable"] +pub struct COPEN0_W<'a> { + w: &'a mut W, +} +impl<'a> COPEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `COPEN1` reader - Capture On Pin 1 Enable"] +pub struct COPEN1_R(crate::FieldReader); +impl COPEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COPEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COPEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COPEN1` writer - Capture On Pin 1 Enable"] +pub struct COPEN1_W<'a> { + w: &'a mut W, +} +impl<'a> COPEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Capture Mode Channel 0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CAPTMODE0_A { + #[doc = "0: Default capture"] + DEFAULT = 0, + #[doc = "1: Minimum capture"] + CAPTMIN = 1, + #[doc = "2: Maximum capture"] + CAPTMAX = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CAPTMODE0_A) -> Self { + variant as _ + } +} +#[doc = "Field `CAPTMODE0` reader - Capture Mode Channel 0"] +pub struct CAPTMODE0_R(crate::FieldReader); +impl CAPTMODE0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CAPTMODE0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CAPTMODE0_A::DEFAULT), + 1 => Some(CAPTMODE0_A::CAPTMIN), + 2 => Some(CAPTMODE0_A::CAPTMAX), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DEFAULT`"] + #[inline(always)] + pub fn is_default(&self) -> bool { + **self == CAPTMODE0_A::DEFAULT + } + #[doc = "Checks if the value of the field is `CAPTMIN`"] + #[inline(always)] + pub fn is_captmin(&self) -> bool { + **self == CAPTMODE0_A::CAPTMIN + } + #[doc = "Checks if the value of the field is `CAPTMAX`"] + #[inline(always)] + pub fn is_captmax(&self) -> bool { + **self == CAPTMODE0_A::CAPTMAX + } +} +impl core::ops::Deref for CAPTMODE0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAPTMODE0` writer - Capture Mode Channel 0"] +pub struct CAPTMODE0_W<'a> { + w: &'a mut W, +} +impl<'a> CAPTMODE0_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CAPTMODE0_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Default capture"] + #[inline(always)] + pub fn default(self) -> &'a mut W { + self.variant(CAPTMODE0_A::DEFAULT) + } + #[doc = "Minimum capture"] + #[inline(always)] + pub fn captmin(self) -> &'a mut W { + self.variant(CAPTMODE0_A::CAPTMIN) + } + #[doc = "Maximum capture"] + #[inline(always)] + pub fn captmax(self) -> &'a mut W { + self.variant(CAPTMODE0_A::CAPTMAX) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 24)) | ((value as u32 & 0x03) << 24); + self.w + } +} +#[doc = "Capture mode Channel 1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CAPTMODE1_A { + #[doc = "0: Default capture"] + DEFAULT = 0, + #[doc = "1: Minimum capture"] + CAPTMIN = 1, + #[doc = "2: Maximum capture"] + CAPTMAX = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CAPTMODE1_A) -> Self { + variant as _ + } +} +#[doc = "Field `CAPTMODE1` reader - Capture mode Channel 1"] +pub struct CAPTMODE1_R(crate::FieldReader); +impl CAPTMODE1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CAPTMODE1_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CAPTMODE1_A::DEFAULT), + 1 => Some(CAPTMODE1_A::CAPTMIN), + 2 => Some(CAPTMODE1_A::CAPTMAX), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DEFAULT`"] + #[inline(always)] + pub fn is_default(&self) -> bool { + **self == CAPTMODE1_A::DEFAULT + } + #[doc = "Checks if the value of the field is `CAPTMIN`"] + #[inline(always)] + pub fn is_captmin(&self) -> bool { + **self == CAPTMODE1_A::CAPTMIN + } + #[doc = "Checks if the value of the field is `CAPTMAX`"] + #[inline(always)] + pub fn is_captmax(&self) -> bool { + **self == CAPTMODE1_A::CAPTMAX + } +} +impl core::ops::Deref for CAPTMODE1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAPTMODE1` writer - Capture mode Channel 1"] +pub struct CAPTMODE1_W<'a> { + w: &'a mut W, +} +impl<'a> CAPTMODE1_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CAPTMODE1_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Default capture"] + #[inline(always)] + pub fn default(self) -> &'a mut W { + self.variant(CAPTMODE1_A::DEFAULT) + } + #[doc = "Minimum capture"] + #[inline(always)] + pub fn captmin(self) -> &'a mut W { + self.variant(CAPTMODE1_A::CAPTMIN) + } + #[doc = "Maximum capture"] + #[inline(always)] + pub fn captmax(self) -> &'a mut W { + self.variant(CAPTMODE1_A::CAPTMAX) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 27)) | ((value as u32 & 0x03) << 27); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:3 - Timer Counter Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bits 4:5 - Prescaler and Counter Synchronization"] + #[inline(always)] + pub fn prescsync(&self) -> PRESCSYNC_R { + PRESCSYNC_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Clock On Demand"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 11 - Auto Lock"] + #[inline(always)] + pub fn alock(&self) -> ALOCK_R { + ALOCK_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 16 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn capten0(&self) -> CAPTEN0_R { + CAPTEN0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn capten1(&self) -> CAPTEN1_R { + CAPTEN1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 20 - Capture On Pin 0 Enable"] + #[inline(always)] + pub fn copen0(&self) -> COPEN0_R { + COPEN0_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Capture On Pin 1 Enable"] + #[inline(always)] + pub fn copen1(&self) -> COPEN1_R { + COPEN1_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bits 24:25 - Capture Mode Channel 0"] + #[inline(always)] + pub fn captmode0(&self) -> CAPTMODE0_R { + CAPTMODE0_R::new(((self.bits >> 24) & 0x03) as u8) + } + #[doc = "Bits 27:28 - Capture mode Channel 1"] + #[inline(always)] + pub fn captmode1(&self) -> CAPTMODE1_R { + CAPTMODE1_R::new(((self.bits >> 27) & 0x03) as u8) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:3 - Timer Counter Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bits 4:5 - Prescaler and Counter Synchronization"] + #[inline(always)] + pub fn prescsync(&mut self) -> PRESCSYNC_W { + PRESCSYNC_W { w: self } + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - Clock On Demand"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Bit 11 - Auto Lock"] + #[inline(always)] + pub fn alock(&mut self) -> ALOCK_W { + ALOCK_W { w: self } + } + #[doc = "Bit 16 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn capten0(&mut self) -> CAPTEN0_W { + CAPTEN0_W { w: self } + } + #[doc = "Bit 17 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn capten1(&mut self) -> CAPTEN1_W { + CAPTEN1_W { w: self } + } + #[doc = "Bit 20 - Capture On Pin 0 Enable"] + #[inline(always)] + pub fn copen0(&mut self) -> COPEN0_W { + COPEN0_W { w: self } + } + #[doc = "Bit 21 - Capture On Pin 1 Enable"] + #[inline(always)] + pub fn copen1(&mut self) -> COPEN1_W { + COPEN1_W { w: self } + } + #[doc = "Bits 24:25 - Capture Mode Channel 0"] + #[inline(always)] + pub fn captmode0(&mut self) -> CAPTMODE0_W { + CAPTMODE0_W { w: self } + } + #[doc = "Bits 27:28 - Capture mode Channel 1"] + #[inline(always)] + pub fn captmode1(&mut self) -> CAPTMODE1_W { + CAPTMODE1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/tc0/count32/ctrlbclr.rs b/pac/atsamc21n/src/tc0/count32/ctrlbclr.rs new file mode 100644 index 000000000000..76265674036a --- /dev/null +++ b/pac/atsamc21n/src/tc0/count32/ctrlbclr.rs @@ -0,0 +1,345 @@ +#[doc = "Register `CTRLBCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Counter Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `LUPD` reader - Lock Update"] +pub struct LUPD_R(crate::FieldReader); +impl LUPD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LUPD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LUPD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LUPD` writer - Lock Update"] +pub struct LUPD_W<'a> { + w: &'a mut W, +} +impl<'a> LUPD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ONESHOT` reader - One-Shot on Counter"] +pub struct ONESHOT_R(crate::FieldReader); +impl ONESHOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONESHOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONESHOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONESHOT` writer - One-Shot on Counter"] +pub struct ONESHOT_W<'a> { + w: &'a mut W, +} +impl<'a> ONESHOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Force a start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force a stop"] + STOP = 2, + #[doc = "3: Force update of double-buffered register"] + UPDATE = 3, + #[doc = "4: Force a read synchronization of COUNT"] + READSYNC = 4, + #[doc = "5: One-shot DMA trigger"] + DMAOS = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NONE), + 1 => Some(CMD_A::RETRIGGER), + 2 => Some(CMD_A::STOP), + 3 => Some(CMD_A::UPDATE), + 4 => Some(CMD_A::READSYNC), + 5 => Some(CMD_A::DMAOS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == CMD_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == CMD_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == CMD_A::STOP + } + #[doc = "Checks if the value of the field is `UPDATE`"] + #[inline(always)] + pub fn is_update(&self) -> bool { + **self == CMD_A::UPDATE + } + #[doc = "Checks if the value of the field is `READSYNC`"] + #[inline(always)] + pub fn is_readsync(&self) -> bool { + **self == CMD_A::READSYNC + } + #[doc = "Checks if the value of the field is `DMAOS`"] + #[inline(always)] + pub fn is_dmaos(&self) -> bool { + **self == CMD_A::DMAOS + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMD_A::NONE) + } + #[doc = "Force a start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMD_A::RETRIGGER) + } + #[doc = "Force a stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMD_A::STOP) + } + #[doc = "Force update of double-buffered register"] + #[inline(always)] + pub fn update(self) -> &'a mut W { + self.variant(CMD_A::UPDATE) + } + #[doc = "Force a read synchronization of COUNT"] + #[inline(always)] + pub fn readsync(self) -> &'a mut W { + self.variant(CMD_A::READSYNC) + } + #[doc = "One-shot DMA trigger"] + #[inline(always)] + pub fn dmaos(self) -> &'a mut W { + self.variant(CMD_A::DMAOS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 5)) | ((value as u8 & 0x07) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&self) -> LUPD_R { + LUPD_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 5) & 0x07) as u8) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&mut self) -> LUPD_W { + LUPD_W { w: self } + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&mut self) -> ONESHOT_W { + ONESHOT_W { w: self } + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbclr](index.html) module"] +pub struct CTRLBCLR_SPEC; +impl crate::RegisterSpec for CTRLBCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbclr::R](R) reader structure"] +impl crate::Readable for CTRLBCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbclr::W](W) writer structure"] +impl crate::Writable for CTRLBCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLBCLR to value 0"] +impl crate::Resettable for CTRLBCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/tc0/count32/ctrlbset.rs b/pac/atsamc21n/src/tc0/count32/ctrlbset.rs new file mode 100644 index 000000000000..610914c9c7c8 --- /dev/null +++ b/pac/atsamc21n/src/tc0/count32/ctrlbset.rs @@ -0,0 +1,345 @@ +#[doc = "Register `CTRLBSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Counter Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `LUPD` reader - Lock Update"] +pub struct LUPD_R(crate::FieldReader); +impl LUPD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LUPD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LUPD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LUPD` writer - Lock Update"] +pub struct LUPD_W<'a> { + w: &'a mut W, +} +impl<'a> LUPD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ONESHOT` reader - One-Shot on Counter"] +pub struct ONESHOT_R(crate::FieldReader); +impl ONESHOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONESHOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONESHOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONESHOT` writer - One-Shot on Counter"] +pub struct ONESHOT_W<'a> { + w: &'a mut W, +} +impl<'a> ONESHOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Force a start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force a stop"] + STOP = 2, + #[doc = "3: Force update of double-buffered register"] + UPDATE = 3, + #[doc = "4: Force a read synchronization of COUNT"] + READSYNC = 4, + #[doc = "5: One-shot DMA trigger"] + DMAOS = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NONE), + 1 => Some(CMD_A::RETRIGGER), + 2 => Some(CMD_A::STOP), + 3 => Some(CMD_A::UPDATE), + 4 => Some(CMD_A::READSYNC), + 5 => Some(CMD_A::DMAOS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == CMD_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == CMD_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == CMD_A::STOP + } + #[doc = "Checks if the value of the field is `UPDATE`"] + #[inline(always)] + pub fn is_update(&self) -> bool { + **self == CMD_A::UPDATE + } + #[doc = "Checks if the value of the field is `READSYNC`"] + #[inline(always)] + pub fn is_readsync(&self) -> bool { + **self == CMD_A::READSYNC + } + #[doc = "Checks if the value of the field is `DMAOS`"] + #[inline(always)] + pub fn is_dmaos(&self) -> bool { + **self == CMD_A::DMAOS + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMD_A::NONE) + } + #[doc = "Force a start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMD_A::RETRIGGER) + } + #[doc = "Force a stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMD_A::STOP) + } + #[doc = "Force update of double-buffered register"] + #[inline(always)] + pub fn update(self) -> &'a mut W { + self.variant(CMD_A::UPDATE) + } + #[doc = "Force a read synchronization of COUNT"] + #[inline(always)] + pub fn readsync(self) -> &'a mut W { + self.variant(CMD_A::READSYNC) + } + #[doc = "One-shot DMA trigger"] + #[inline(always)] + pub fn dmaos(self) -> &'a mut W { + self.variant(CMD_A::DMAOS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 5)) | ((value as u8 & 0x07) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&self) -> LUPD_R { + LUPD_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 5) & 0x07) as u8) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&mut self) -> LUPD_W { + LUPD_W { w: self } + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&mut self) -> ONESHOT_W { + ONESHOT_W { w: self } + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbset](index.html) module"] +pub struct CTRLBSET_SPEC; +impl crate::RegisterSpec for CTRLBSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbset::R](R) reader structure"] +impl crate::Readable for CTRLBSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbset::W](W) writer structure"] +impl crate::Writable for CTRLBSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLBSET to value 0"] +impl crate::Resettable for CTRLBSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/tc0/count32/dbgctrl.rs b/pac/atsamc21n/src/tc0/count32/dbgctrl.rs new file mode 100644 index 000000000000..0383e70d0429 --- /dev/null +++ b/pac/atsamc21n/src/tc0/count32/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Run During Debug"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Run During Debug"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/tc0/count32/drvctrl.rs b/pac/atsamc21n/src/tc0/count32/drvctrl.rs new file mode 100644 index 000000000000..323926b4b22d --- /dev/null +++ b/pac/atsamc21n/src/tc0/count32/drvctrl.rs @@ -0,0 +1,160 @@ +#[doc = "Register `DRVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DRVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INVEN0` reader - Output Waveform Invert Enable 0"] +pub struct INVEN0_R(crate::FieldReader); +impl INVEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN0` writer - Output Waveform Invert Enable 0"] +pub struct INVEN0_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `INVEN1` reader - Output Waveform Invert Enable 1"] +pub struct INVEN1_R(crate::FieldReader); +impl INVEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN1` writer - Output Waveform Invert Enable 1"] +pub struct INVEN1_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - Output Waveform Invert Enable 0"] + #[inline(always)] + pub fn inven0(&self) -> INVEN0_R { + INVEN0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Output Waveform Invert Enable 1"] + #[inline(always)] + pub fn inven1(&self) -> INVEN1_R { + INVEN1_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Output Waveform Invert Enable 0"] + #[inline(always)] + pub fn inven0(&mut self) -> INVEN0_W { + INVEN0_W { w: self } + } + #[doc = "Bit 1 - Output Waveform Invert Enable 1"] + #[inline(always)] + pub fn inven1(&mut self) -> INVEN1_W { + INVEN1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control C\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [drvctrl](index.html) module"] +pub struct DRVCTRL_SPEC; +impl crate::RegisterSpec for DRVCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [drvctrl::R](R) reader structure"] +impl crate::Readable for DRVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [drvctrl::W](W) writer structure"] +impl crate::Writable for DRVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DRVCTRL to value 0"] +impl crate::Resettable for DRVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/tc0/count32/evctrl.rs b/pac/atsamc21n/src/tc0/count32/evctrl.rs new file mode 100644 index 000000000000..7d4c38d486c1 --- /dev/null +++ b/pac/atsamc21n/src/tc0/count32/evctrl.rs @@ -0,0 +1,465 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Event Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EVACT_A { + #[doc = "0: Event action disabled"] + OFF = 0, + #[doc = "1: Start, restart or retrigger TC on event"] + RETRIGGER = 1, + #[doc = "2: Count on event"] + COUNT = 2, + #[doc = "3: Start TC on event"] + START = 3, + #[doc = "4: Time stamp capture"] + STAMP = 4, + #[doc = "5: Period catured in CC0, pulse width in CC1"] + PPW = 5, + #[doc = "6: Period catured in CC1, pulse width in CC0"] + PWP = 6, + #[doc = "7: Pulse width capture"] + PW = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EVACT_A) -> Self { + variant as _ + } +} +#[doc = "Field `EVACT` reader - Event Action"] +pub struct EVACT_R(crate::FieldReader); +impl EVACT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVACT_A { + match self.bits { + 0 => EVACT_A::OFF, + 1 => EVACT_A::RETRIGGER, + 2 => EVACT_A::COUNT, + 3 => EVACT_A::START, + 4 => EVACT_A::STAMP, + 5 => EVACT_A::PPW, + 6 => EVACT_A::PWP, + 7 => EVACT_A::PW, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == EVACT_A::OFF + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == EVACT_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `COUNT`"] + #[inline(always)] + pub fn is_count(&self) -> bool { + **self == EVACT_A::COUNT + } + #[doc = "Checks if the value of the field is `START`"] + #[inline(always)] + pub fn is_start(&self) -> bool { + **self == EVACT_A::START + } + #[doc = "Checks if the value of the field is `STAMP`"] + #[inline(always)] + pub fn is_stamp(&self) -> bool { + **self == EVACT_A::STAMP + } + #[doc = "Checks if the value of the field is `PPW`"] + #[inline(always)] + pub fn is_ppw(&self) -> bool { + **self == EVACT_A::PPW + } + #[doc = "Checks if the value of the field is `PWP`"] + #[inline(always)] + pub fn is_pwp(&self) -> bool { + **self == EVACT_A::PWP + } + #[doc = "Checks if the value of the field is `PW`"] + #[inline(always)] + pub fn is_pw(&self) -> bool { + **self == EVACT_A::PW + } +} +impl core::ops::Deref for EVACT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT` writer - Event Action"] +pub struct EVACT_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EVACT_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Event action disabled"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(EVACT_A::OFF) + } + #[doc = "Start, restart or retrigger TC on event"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(EVACT_A::RETRIGGER) + } + #[doc = "Count on event"] + #[inline(always)] + pub fn count(self) -> &'a mut W { + self.variant(EVACT_A::COUNT) + } + #[doc = "Start TC on event"] + #[inline(always)] + pub fn start(self) -> &'a mut W { + self.variant(EVACT_A::START) + } + #[doc = "Time stamp capture"] + #[inline(always)] + pub fn stamp(self) -> &'a mut W { + self.variant(EVACT_A::STAMP) + } + #[doc = "Period catured in CC0, pulse width in CC1"] + #[inline(always)] + pub fn ppw(self) -> &'a mut W { + self.variant(EVACT_A::PPW) + } + #[doc = "Period catured in CC1, pulse width in CC0"] + #[inline(always)] + pub fn pwp(self) -> &'a mut W { + self.variant(EVACT_A::PWP) + } + #[doc = "Pulse width capture"] + #[inline(always)] + pub fn pw(self) -> &'a mut W { + self.variant(EVACT_A::PW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u16 & 0x07); + self.w + } +} +#[doc = "Field `TCINV` reader - TC Event Input Polarity"] +pub struct TCINV_R(crate::FieldReader); +impl TCINV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCINV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCINV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCINV` writer - TC Event Input Polarity"] +pub struct TCINV_W<'a> { + w: &'a mut W, +} +impl<'a> TCINV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `TCEI` reader - TC Event Enable"] +pub struct TCEI_R(crate::FieldReader); +impl TCEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCEI` writer - TC Event Enable"] +pub struct TCEI_W<'a> { + w: &'a mut W, +} +impl<'a> TCEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `OVFEO` reader - Event Output Enable"] +pub struct OVFEO_R(crate::FieldReader); +impl OVFEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVFEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVFEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVFEO` writer - Event Output Enable"] +pub struct OVFEO_W<'a> { + w: &'a mut W, +} +impl<'a> OVFEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `MCEO0` reader - MC Event Output Enable 0"] +pub struct MCEO0_R(crate::FieldReader); +impl MCEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO0` writer - MC Event Output Enable 0"] +pub struct MCEO0_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u16 & 0x01) << 12); + self.w + } +} +#[doc = "Field `MCEO1` reader - MC Event Output Enable 1"] +pub struct MCEO1_R(crate::FieldReader); +impl MCEO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO1` writer - MC Event Output Enable 1"] +pub struct MCEO1_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u16 & 0x01) << 13); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Event Action"] + #[inline(always)] + pub fn evact(&self) -> EVACT_R { + EVACT_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 4 - TC Event Input Polarity"] + #[inline(always)] + pub fn tcinv(&self) -> TCINV_R { + TCINV_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - TC Event Enable"] + #[inline(always)] + pub fn tcei(&self) -> TCEI_R { + TCEI_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 8 - Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&self) -> OVFEO_R { + OVFEO_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 12 - MC Event Output Enable 0"] + #[inline(always)] + pub fn mceo0(&self) -> MCEO0_R { + MCEO0_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - MC Event Output Enable 1"] + #[inline(always)] + pub fn mceo1(&self) -> MCEO1_R { + MCEO1_R::new(((self.bits >> 13) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Event Action"] + #[inline(always)] + pub fn evact(&mut self) -> EVACT_W { + EVACT_W { w: self } + } + #[doc = "Bit 4 - TC Event Input Polarity"] + #[inline(always)] + pub fn tcinv(&mut self) -> TCINV_W { + TCINV_W { w: self } + } + #[doc = "Bit 5 - TC Event Enable"] + #[inline(always)] + pub fn tcei(&mut self) -> TCEI_W { + TCEI_W { w: self } + } + #[doc = "Bit 8 - Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&mut self) -> OVFEO_W { + OVFEO_W { w: self } + } + #[doc = "Bit 12 - MC Event Output Enable 0"] + #[inline(always)] + pub fn mceo0(&mut self) -> MCEO0_W { + MCEO0_W { w: self } + } + #[doc = "Bit 13 - MC Event Output Enable 1"] + #[inline(always)] + pub fn mceo1(&mut self) -> MCEO1_W { + MCEO1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/tc0/count32/intenclr.rs b/pac/atsamc21n/src/tc0/count32/intenclr.rs new file mode 100644 index 000000000000..af01ef5b7dca --- /dev/null +++ b/pac/atsamc21n/src/tc0/count32/intenclr.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - OVF Interrupt Disable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - OVF Interrupt Disable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - ERR Interrupt Disable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - ERR Interrupt Disable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MC0` reader - MC Interrupt Disable 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - MC Interrupt Disable 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - MC Interrupt Disable 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - MC Interrupt Disable 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - OVF Interrupt Disable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ERR Interrupt Disable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - MC Interrupt Disable 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - MC Interrupt Disable 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - OVF Interrupt Disable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - ERR Interrupt Disable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 4 - MC Interrupt Disable 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - MC Interrupt Disable 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/tc0/count32/intenset.rs b/pac/atsamc21n/src/tc0/count32/intenset.rs new file mode 100644 index 000000000000..0e1883a2f20a --- /dev/null +++ b/pac/atsamc21n/src/tc0/count32/intenset.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - OVF Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - OVF Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - ERR Interrupt Enable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - ERR Interrupt Enable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MC0` reader - MC Interrupt Enable 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - MC Interrupt Enable 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - MC Interrupt Enable 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - MC Interrupt Enable 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - OVF Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ERR Interrupt Enable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - MC Interrupt Enable 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - MC Interrupt Enable 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - OVF Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - ERR Interrupt Enable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 4 - MC Interrupt Enable 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - MC Interrupt Enable 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/tc0/count32/intflag.rs b/pac/atsamc21n/src/tc0/count32/intflag.rs new file mode 100644 index 000000000000..1dddffaf8e7f --- /dev/null +++ b/pac/atsamc21n/src/tc0/count32/intflag.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - OVF Interrupt Flag"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - OVF Interrupt Flag"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - ERR Interrupt Flag"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - ERR Interrupt Flag"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MC0` reader - MC Interrupt Flag 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - MC Interrupt Flag 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - MC Interrupt Flag 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - MC Interrupt Flag 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - OVF Interrupt Flag"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ERR Interrupt Flag"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - MC Interrupt Flag 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - MC Interrupt Flag 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - OVF Interrupt Flag"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - ERR Interrupt Flag"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 4 - MC Interrupt Flag 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - MC Interrupt Flag 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/tc0/count32/status.rs b/pac/atsamc21n/src/tc0/count32/status.rs new file mode 100644 index 000000000000..5088af446830 --- /dev/null +++ b/pac/atsamc21n/src/tc0/count32/status.rs @@ -0,0 +1,301 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `STOP` reader - Stop Status Flag"] +pub struct STOP_R(crate::FieldReader); +impl STOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STOP` writer - Stop Status Flag"] +pub struct STOP_W<'a> { + w: &'a mut W, +} +impl<'a> STOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SLAVE` reader - Slave Status Flag"] +pub struct SLAVE_R(crate::FieldReader); +impl SLAVE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLAVE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SLAVE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLAVE` writer - Slave Status Flag"] +pub struct SLAVE_W<'a> { + w: &'a mut W, +} +impl<'a> SLAVE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PERBUFV` reader - Synchronization Busy Status"] +pub struct PERBUFV_R(crate::FieldReader); +impl PERBUFV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PERBUFV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERBUFV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERBUFV` writer - Synchronization Busy Status"] +pub struct PERBUFV_W<'a> { + w: &'a mut W, +} +impl<'a> PERBUFV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CCBUFV0` reader - Compare channel buffer 0 valid"] +pub struct CCBUFV0_R(crate::FieldReader); +impl CCBUFV0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBUFV0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUFV0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUFV0` writer - Compare channel buffer 0 valid"] +pub struct CCBUFV0_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUFV0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `CCBUFV1` reader - Compare channel buffer 1 valid"] +pub struct CCBUFV1_R(crate::FieldReader); +impl CCBUFV1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBUFV1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUFV1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUFV1` writer - Compare channel buffer 1 valid"] +pub struct CCBUFV1_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUFV1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Stop Status Flag"] + #[inline(always)] + pub fn stop(&self) -> STOP_R { + STOP_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Slave Status Flag"] + #[inline(always)] + pub fn slave(&self) -> SLAVE_R { + SLAVE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 3 - Synchronization Busy Status"] + #[inline(always)] + pub fn perbufv(&self) -> PERBUFV_R { + PERBUFV_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Compare channel buffer 0 valid"] + #[inline(always)] + pub fn ccbufv0(&self) -> CCBUFV0_R { + CCBUFV0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Compare channel buffer 1 valid"] + #[inline(always)] + pub fn ccbufv1(&self) -> CCBUFV1_R { + CCBUFV1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Stop Status Flag"] + #[inline(always)] + pub fn stop(&mut self) -> STOP_W { + STOP_W { w: self } + } + #[doc = "Bit 1 - Slave Status Flag"] + #[inline(always)] + pub fn slave(&mut self) -> SLAVE_W { + SLAVE_W { w: self } + } + #[doc = "Bit 3 - Synchronization Busy Status"] + #[inline(always)] + pub fn perbufv(&mut self) -> PERBUFV_W { + PERBUFV_W { w: self } + } + #[doc = "Bit 4 - Compare channel buffer 0 valid"] + #[inline(always)] + pub fn ccbufv0(&mut self) -> CCBUFV0_W { + CCBUFV0_W { w: self } + } + #[doc = "Bit 5 - Compare channel buffer 1 valid"] + #[inline(always)] + pub fn ccbufv1(&mut self) -> CCBUFV1_W { + CCBUFV1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0x01"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pac/atsamc21n/src/tc0/count32/syncbusy.rs b/pac/atsamc21n/src/tc0/count32/syncbusy.rs new file mode 100644 index 000000000000..7ad8d91a84de --- /dev/null +++ b/pac/atsamc21n/src/tc0/count32/syncbusy.rs @@ -0,0 +1,193 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - swrst"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLB` reader - CTRLB"] +pub struct CTRLB_R(crate::FieldReader); +impl CTRLB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STATUS` reader - STATUS"] +pub struct STATUS_R(crate::FieldReader); +impl STATUS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STATUS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STATUS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` reader - Counter"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` reader - Period"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC0` reader - Compare Channel 0"] +pub struct CC0_R(crate::FieldReader); +impl CC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC1` reader - Compare Channel 1"] +pub struct CC1_R(crate::FieldReader); +impl CC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - swrst"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - CTRLB"] + #[inline(always)] + pub fn ctrlb(&self) -> CTRLB_R { + CTRLB_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - STATUS"] + #[inline(always)] + pub fn status(&self) -> STATUS_R { + STATUS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Counter"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Period"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Compare Channel 0"] + #[inline(always)] + pub fn cc0(&self) -> CC0_R { + CC0_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Compare Channel 1"] + #[inline(always)] + pub fn cc1(&self) -> CC1_R { + CC1_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +#[doc = "Synchronization Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/tc0/count32/wave.rs b/pac/atsamc21n/src/tc0/count32/wave.rs new file mode 100644 index 000000000000..46061b24b75d --- /dev/null +++ b/pac/atsamc21n/src/tc0/count32/wave.rs @@ -0,0 +1,178 @@ +#[doc = "Register `WAVE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WAVE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Waveform Generation Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WAVEGEN_A { + #[doc = "0: Normal frequency"] + NFRQ = 0, + #[doc = "1: Match frequency"] + MFRQ = 1, + #[doc = "2: Normal PWM"] + NPWM = 2, + #[doc = "3: Match PWM"] + MPWM = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WAVEGEN_A) -> Self { + variant as _ + } +} +#[doc = "Field `WAVEGEN` reader - Waveform Generation Mode"] +pub struct WAVEGEN_R(crate::FieldReader); +impl WAVEGEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WAVEGEN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> WAVEGEN_A { + match self.bits { + 0 => WAVEGEN_A::NFRQ, + 1 => WAVEGEN_A::MFRQ, + 2 => WAVEGEN_A::NPWM, + 3 => WAVEGEN_A::MPWM, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NFRQ`"] + #[inline(always)] + pub fn is_nfrq(&self) -> bool { + **self == WAVEGEN_A::NFRQ + } + #[doc = "Checks if the value of the field is `MFRQ`"] + #[inline(always)] + pub fn is_mfrq(&self) -> bool { + **self == WAVEGEN_A::MFRQ + } + #[doc = "Checks if the value of the field is `NPWM`"] + #[inline(always)] + pub fn is_npwm(&self) -> bool { + **self == WAVEGEN_A::NPWM + } + #[doc = "Checks if the value of the field is `MPWM`"] + #[inline(always)] + pub fn is_mpwm(&self) -> bool { + **self == WAVEGEN_A::MPWM + } +} +impl core::ops::Deref for WAVEGEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAVEGEN` writer - Waveform Generation Mode"] +pub struct WAVEGEN_W<'a> { + w: &'a mut W, +} +impl<'a> WAVEGEN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WAVEGEN_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Normal frequency"] + #[inline(always)] + pub fn nfrq(self) -> &'a mut W { + self.variant(WAVEGEN_A::NFRQ) + } + #[doc = "Match frequency"] + #[inline(always)] + pub fn mfrq(self) -> &'a mut W { + self.variant(WAVEGEN_A::MFRQ) + } + #[doc = "Normal PWM"] + #[inline(always)] + pub fn npwm(self) -> &'a mut W { + self.variant(WAVEGEN_A::NPWM) + } + #[doc = "Match PWM"] + #[inline(always)] + pub fn mpwm(self) -> &'a mut W { + self.variant(WAVEGEN_A::MPWM) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u8 & 0x03); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Waveform Generation Mode"] + #[inline(always)] + pub fn wavegen(&self) -> WAVEGEN_R { + WAVEGEN_R::new((self.bits & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Waveform Generation Mode"] + #[inline(always)] + pub fn wavegen(&mut self) -> WAVEGEN_W { + WAVEGEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Waveform Generation Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wave](index.html) module"] +pub struct WAVE_SPEC; +impl crate::RegisterSpec for WAVE_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [wave::R](R) reader structure"] +impl crate::Readable for WAVE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wave::W](W) writer structure"] +impl crate::Writable for WAVE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WAVE to value 0"] +impl crate::Resettable for WAVE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/tc0/count8.rs b/pac/atsamc21n/src/tc0/count8.rs new file mode 100644 index 000000000000..777da5744358 --- /dev/null +++ b/pac/atsamc21n/src/tc0/count8.rs @@ -0,0 +1,68 @@ +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "CTRLBCLR register accessor: an alias for `Reg`"] +pub type CTRLBCLR = crate::Reg; +#[doc = "Control B Clear"] +pub mod ctrlbclr; +#[doc = "CTRLBSET register accessor: an alias for `Reg`"] +pub type CTRLBSET = crate::Reg; +#[doc = "Control B Set"] +pub mod ctrlbset; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "WAVE register accessor: an alias for `Reg`"] +pub type WAVE = crate::Reg; +#[doc = "Waveform Generation Control"] +pub mod wave; +#[doc = "DRVCTRL register accessor: an alias for `Reg`"] +pub type DRVCTRL = crate::Reg; +#[doc = "Control C"] +pub mod drvctrl; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Status"] +pub mod syncbusy; +#[doc = "COUNT register accessor: an alias for `Reg`"] +pub type COUNT = crate::Reg; +#[doc = "COUNT8 Count"] +pub mod count; +#[doc = "PER register accessor: an alias for `Reg`"] +pub type PER = crate::Reg; +#[doc = "COUNT8 Period"] +pub mod per; +#[doc = "CC register accessor: an alias for `Reg`"] +pub type CC = crate::Reg; +#[doc = "COUNT8 Compare and Capture"] +pub mod cc; +#[doc = "PERBUF register accessor: an alias for `Reg`"] +pub type PERBUF = crate::Reg; +#[doc = "COUNT8 Period Buffer"] +pub mod perbuf; +#[doc = "CCBUF register accessor: an alias for `Reg`"] +pub type CCBUF = crate::Reg; +#[doc = "COUNT8 Compare and Capture Buffer"] +pub mod ccbuf; diff --git a/pac/atsamc21n/src/tc0/count8/cc.rs b/pac/atsamc21n/src/tc0/count8/cc.rs new file mode 100644 index 000000000000..45f5c29c89af --- /dev/null +++ b/pac/atsamc21n/src/tc0/count8/cc.rs @@ -0,0 +1,104 @@ +#[doc = "Register `CC[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CC[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CC` reader - Counter/Compare Value"] +pub struct CC_R(crate::FieldReader); +impl CC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC` writer - Counter/Compare Value"] +pub struct CC_W<'a> { + w: &'a mut W, +} +impl<'a> CC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Counter/Compare Value"] + #[inline(always)] + pub fn cc(&self) -> CC_R { + CC_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Counter/Compare Value"] + #[inline(always)] + pub fn cc(&mut self) -> CC_W { + CC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT8 Compare and Capture\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc](index.html) module"] +pub struct CC_SPEC; +impl crate::RegisterSpec for CC_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [cc::R](R) reader structure"] +impl crate::Readable for CC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cc::W](W) writer structure"] +impl crate::Writable for CC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CC[%s] +to value 0"] +impl crate::Resettable for CC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/tc0/count8/ccbuf.rs b/pac/atsamc21n/src/tc0/count8/ccbuf.rs new file mode 100644 index 000000000000..cd81b1219860 --- /dev/null +++ b/pac/atsamc21n/src/tc0/count8/ccbuf.rs @@ -0,0 +1,104 @@ +#[doc = "Register `CCBUF[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CCBUF[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CCBUF` reader - Counter/Compare Buffer Value"] +pub struct CCBUF_R(crate::FieldReader); +impl CCBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CCBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUF` writer - Counter/Compare Buffer Value"] +pub struct CCBUF_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Counter/Compare Buffer Value"] + #[inline(always)] + pub fn ccbuf(&self) -> CCBUF_R { + CCBUF_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Counter/Compare Buffer Value"] + #[inline(always)] + pub fn ccbuf(&mut self) -> CCBUF_W { + CCBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT8 Compare and Capture Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccbuf](index.html) module"] +pub struct CCBUF_SPEC; +impl crate::RegisterSpec for CCBUF_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ccbuf::R](R) reader structure"] +impl crate::Readable for CCBUF_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ccbuf::W](W) writer structure"] +impl crate::Writable for CCBUF_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CCBUF[%s] +to value 0"] +impl crate::Resettable for CCBUF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/tc0/count8/count.rs b/pac/atsamc21n/src/tc0/count8/count.rs new file mode 100644 index 000000000000..0edbb0f17bb7 --- /dev/null +++ b/pac/atsamc21n/src/tc0/count8/count.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT8 Count\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count](index.html) module"] +pub struct COUNT_SPEC; +impl crate::RegisterSpec for COUNT_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [count::R](R) reader structure"] +impl crate::Readable for COUNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count::W](W) writer structure"] +impl crate::Writable for COUNT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT to value 0"] +impl crate::Resettable for COUNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/tc0/count8/ctrla.rs b/pac/atsamc21n/src/tc0/count8/ctrla.rs new file mode 100644 index 000000000000..e1be912fdfcd --- /dev/null +++ b/pac/atsamc21n/src/tc0/count8/ctrla.rs @@ -0,0 +1,1049 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Timer Counter Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: Counter in 16-bit mode"] + COUNT16 = 0, + #[doc = "1: Counter in 8-bit mode"] + COUNT8 = 1, + #[doc = "2: Counter in 32-bit mode"] + COUNT32 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Timer Counter Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::COUNT16), + 1 => Some(MODE_A::COUNT8), + 2 => Some(MODE_A::COUNT32), + _ => None, + } + } + #[doc = "Checks if the value of the field is `COUNT16`"] + #[inline(always)] + pub fn is_count16(&self) -> bool { + **self == MODE_A::COUNT16 + } + #[doc = "Checks if the value of the field is `COUNT8`"] + #[inline(always)] + pub fn is_count8(&self) -> bool { + **self == MODE_A::COUNT8 + } + #[doc = "Checks if the value of the field is `COUNT32`"] + #[inline(always)] + pub fn is_count32(&self) -> bool { + **self == MODE_A::COUNT32 + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Timer Counter Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Counter in 16-bit mode"] + #[inline(always)] + pub fn count16(self) -> &'a mut W { + self.variant(MODE_A::COUNT16) + } + #[doc = "Counter in 8-bit mode"] + #[inline(always)] + pub fn count8(self) -> &'a mut W { + self.variant(MODE_A::COUNT8) + } + #[doc = "Counter in 32-bit mode"] + #[inline(always)] + pub fn count32(self) -> &'a mut W { + self.variant(MODE_A::COUNT32) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u32 & 0x03) << 2); + self.w + } +} +#[doc = "Prescaler and Counter Synchronization\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCSYNC_A { + #[doc = "0: Reload or reset the counter on next generic clock"] + GCLK = 0, + #[doc = "1: Reload or reset the counter on next prescaler clock"] + PRESC = 1, + #[doc = "2: Reload or reset the counter on next generic clock and reset the prescaler counter"] + RESYNC = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCSYNC_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCSYNC` reader - Prescaler and Counter Synchronization"] +pub struct PRESCSYNC_R(crate::FieldReader); +impl PRESCSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCSYNC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCSYNC_A::GCLK), + 1 => Some(PRESCSYNC_A::PRESC), + 2 => Some(PRESCSYNC_A::RESYNC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `GCLK`"] + #[inline(always)] + pub fn is_gclk(&self) -> bool { + **self == PRESCSYNC_A::GCLK + } + #[doc = "Checks if the value of the field is `PRESC`"] + #[inline(always)] + pub fn is_presc(&self) -> bool { + **self == PRESCSYNC_A::PRESC + } + #[doc = "Checks if the value of the field is `RESYNC`"] + #[inline(always)] + pub fn is_resync(&self) -> bool { + **self == PRESCSYNC_A::RESYNC + } +} +impl core::ops::Deref for PRESCSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCSYNC` writer - Prescaler and Counter Synchronization"] +pub struct PRESCSYNC_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCSYNC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCSYNC_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Reload or reset the counter on next generic clock"] + #[inline(always)] + pub fn gclk(self) -> &'a mut W { + self.variant(PRESCSYNC_A::GCLK) + } + #[doc = "Reload or reset the counter on next prescaler clock"] + #[inline(always)] + pub fn presc(self) -> &'a mut W { + self.variant(PRESCSYNC_A::PRESC) + } + #[doc = "Reload or reset the counter on next generic clock and reset the prescaler counter"] + #[inline(always)] + pub fn resync(self) -> &'a mut W { + self.variant(PRESCSYNC_A::RESYNC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u32 & 0x03) << 4); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - Clock On Demand"] +pub struct ONDEMAND_R(crate::FieldReader); +impl ONDEMAND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - Clock On Demand"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: Prescaler: GCLK_TC"] + DIV1 = 0, + #[doc = "1: Prescaler: GCLK_TC/2"] + DIV2 = 1, + #[doc = "2: Prescaler: GCLK_TC/4"] + DIV4 = 2, + #[doc = "3: Prescaler: GCLK_TC/8"] + DIV8 = 3, + #[doc = "4: Prescaler: GCLK_TC/16"] + DIV16 = 4, + #[doc = "5: Prescaler: GCLK_TC/64"] + DIV64 = 5, + #[doc = "6: Prescaler: GCLK_TC/256"] + DIV256 = 6, + #[doc = "7: Prescaler: GCLK_TC/1024"] + DIV1024 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PRESCALER_A { + match self.bits { + 0 => PRESCALER_A::DIV1, + 1 => PRESCALER_A::DIV2, + 2 => PRESCALER_A::DIV4, + 3 => PRESCALER_A::DIV8, + 4 => PRESCALER_A::DIV16, + 5 => PRESCALER_A::DIV64, + 6 => PRESCALER_A::DIV256, + 7 => PRESCALER_A::DIV1024, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == PRESCALER_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PRESCALER_A::DIV1024 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Prescaler: GCLK_TC"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1) + } + #[doc = "Prescaler: GCLK_TC/2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "Prescaler: GCLK_TC/4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "Prescaler: GCLK_TC/8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "Prescaler: GCLK_TC/16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "Prescaler: GCLK_TC/64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "Prescaler: GCLK_TC/256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = "Prescaler: GCLK_TC/1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +#[doc = "Field `ALOCK` reader - Auto Lock"] +pub struct ALOCK_R(crate::FieldReader); +impl ALOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALOCK` writer - Auto Lock"] +pub struct ALOCK_W<'a> { + w: &'a mut W, +} +impl<'a> ALOCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `CAPTEN0` reader - Capture Channel 0 Enable"] +pub struct CAPTEN0_R(crate::FieldReader); +impl CAPTEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CAPTEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CAPTEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAPTEN0` writer - Capture Channel 0 Enable"] +pub struct CAPTEN0_W<'a> { + w: &'a mut W, +} +impl<'a> CAPTEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `CAPTEN1` reader - Capture Channel 1 Enable"] +pub struct CAPTEN1_R(crate::FieldReader); +impl CAPTEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CAPTEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CAPTEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAPTEN1` writer - Capture Channel 1 Enable"] +pub struct CAPTEN1_W<'a> { + w: &'a mut W, +} +impl<'a> CAPTEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `COPEN0` reader - Capture On Pin 0 Enable"] +pub struct COPEN0_R(crate::FieldReader); +impl COPEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COPEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COPEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COPEN0` writer - Capture On Pin 0 Enable"] +pub struct COPEN0_W<'a> { + w: &'a mut W, +} +impl<'a> COPEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `COPEN1` reader - Capture On Pin 1 Enable"] +pub struct COPEN1_R(crate::FieldReader); +impl COPEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COPEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COPEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COPEN1` writer - Capture On Pin 1 Enable"] +pub struct COPEN1_W<'a> { + w: &'a mut W, +} +impl<'a> COPEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Capture Mode Channel 0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CAPTMODE0_A { + #[doc = "0: Default capture"] + DEFAULT = 0, + #[doc = "1: Minimum capture"] + CAPTMIN = 1, + #[doc = "2: Maximum capture"] + CAPTMAX = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CAPTMODE0_A) -> Self { + variant as _ + } +} +#[doc = "Field `CAPTMODE0` reader - Capture Mode Channel 0"] +pub struct CAPTMODE0_R(crate::FieldReader); +impl CAPTMODE0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CAPTMODE0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CAPTMODE0_A::DEFAULT), + 1 => Some(CAPTMODE0_A::CAPTMIN), + 2 => Some(CAPTMODE0_A::CAPTMAX), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DEFAULT`"] + #[inline(always)] + pub fn is_default(&self) -> bool { + **self == CAPTMODE0_A::DEFAULT + } + #[doc = "Checks if the value of the field is `CAPTMIN`"] + #[inline(always)] + pub fn is_captmin(&self) -> bool { + **self == CAPTMODE0_A::CAPTMIN + } + #[doc = "Checks if the value of the field is `CAPTMAX`"] + #[inline(always)] + pub fn is_captmax(&self) -> bool { + **self == CAPTMODE0_A::CAPTMAX + } +} +impl core::ops::Deref for CAPTMODE0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAPTMODE0` writer - Capture Mode Channel 0"] +pub struct CAPTMODE0_W<'a> { + w: &'a mut W, +} +impl<'a> CAPTMODE0_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CAPTMODE0_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Default capture"] + #[inline(always)] + pub fn default(self) -> &'a mut W { + self.variant(CAPTMODE0_A::DEFAULT) + } + #[doc = "Minimum capture"] + #[inline(always)] + pub fn captmin(self) -> &'a mut W { + self.variant(CAPTMODE0_A::CAPTMIN) + } + #[doc = "Maximum capture"] + #[inline(always)] + pub fn captmax(self) -> &'a mut W { + self.variant(CAPTMODE0_A::CAPTMAX) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 24)) | ((value as u32 & 0x03) << 24); + self.w + } +} +#[doc = "Capture mode Channel 1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CAPTMODE1_A { + #[doc = "0: Default capture"] + DEFAULT = 0, + #[doc = "1: Minimum capture"] + CAPTMIN = 1, + #[doc = "2: Maximum capture"] + CAPTMAX = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CAPTMODE1_A) -> Self { + variant as _ + } +} +#[doc = "Field `CAPTMODE1` reader - Capture mode Channel 1"] +pub struct CAPTMODE1_R(crate::FieldReader); +impl CAPTMODE1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CAPTMODE1_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CAPTMODE1_A::DEFAULT), + 1 => Some(CAPTMODE1_A::CAPTMIN), + 2 => Some(CAPTMODE1_A::CAPTMAX), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DEFAULT`"] + #[inline(always)] + pub fn is_default(&self) -> bool { + **self == CAPTMODE1_A::DEFAULT + } + #[doc = "Checks if the value of the field is `CAPTMIN`"] + #[inline(always)] + pub fn is_captmin(&self) -> bool { + **self == CAPTMODE1_A::CAPTMIN + } + #[doc = "Checks if the value of the field is `CAPTMAX`"] + #[inline(always)] + pub fn is_captmax(&self) -> bool { + **self == CAPTMODE1_A::CAPTMAX + } +} +impl core::ops::Deref for CAPTMODE1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAPTMODE1` writer - Capture mode Channel 1"] +pub struct CAPTMODE1_W<'a> { + w: &'a mut W, +} +impl<'a> CAPTMODE1_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CAPTMODE1_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Default capture"] + #[inline(always)] + pub fn default(self) -> &'a mut W { + self.variant(CAPTMODE1_A::DEFAULT) + } + #[doc = "Minimum capture"] + #[inline(always)] + pub fn captmin(self) -> &'a mut W { + self.variant(CAPTMODE1_A::CAPTMIN) + } + #[doc = "Maximum capture"] + #[inline(always)] + pub fn captmax(self) -> &'a mut W { + self.variant(CAPTMODE1_A::CAPTMAX) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 27)) | ((value as u32 & 0x03) << 27); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:3 - Timer Counter Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bits 4:5 - Prescaler and Counter Synchronization"] + #[inline(always)] + pub fn prescsync(&self) -> PRESCSYNC_R { + PRESCSYNC_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Clock On Demand"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 11 - Auto Lock"] + #[inline(always)] + pub fn alock(&self) -> ALOCK_R { + ALOCK_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 16 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn capten0(&self) -> CAPTEN0_R { + CAPTEN0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn capten1(&self) -> CAPTEN1_R { + CAPTEN1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 20 - Capture On Pin 0 Enable"] + #[inline(always)] + pub fn copen0(&self) -> COPEN0_R { + COPEN0_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Capture On Pin 1 Enable"] + #[inline(always)] + pub fn copen1(&self) -> COPEN1_R { + COPEN1_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bits 24:25 - Capture Mode Channel 0"] + #[inline(always)] + pub fn captmode0(&self) -> CAPTMODE0_R { + CAPTMODE0_R::new(((self.bits >> 24) & 0x03) as u8) + } + #[doc = "Bits 27:28 - Capture mode Channel 1"] + #[inline(always)] + pub fn captmode1(&self) -> CAPTMODE1_R { + CAPTMODE1_R::new(((self.bits >> 27) & 0x03) as u8) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:3 - Timer Counter Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bits 4:5 - Prescaler and Counter Synchronization"] + #[inline(always)] + pub fn prescsync(&mut self) -> PRESCSYNC_W { + PRESCSYNC_W { w: self } + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - Clock On Demand"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Bit 11 - Auto Lock"] + #[inline(always)] + pub fn alock(&mut self) -> ALOCK_W { + ALOCK_W { w: self } + } + #[doc = "Bit 16 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn capten0(&mut self) -> CAPTEN0_W { + CAPTEN0_W { w: self } + } + #[doc = "Bit 17 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn capten1(&mut self) -> CAPTEN1_W { + CAPTEN1_W { w: self } + } + #[doc = "Bit 20 - Capture On Pin 0 Enable"] + #[inline(always)] + pub fn copen0(&mut self) -> COPEN0_W { + COPEN0_W { w: self } + } + #[doc = "Bit 21 - Capture On Pin 1 Enable"] + #[inline(always)] + pub fn copen1(&mut self) -> COPEN1_W { + COPEN1_W { w: self } + } + #[doc = "Bits 24:25 - Capture Mode Channel 0"] + #[inline(always)] + pub fn captmode0(&mut self) -> CAPTMODE0_W { + CAPTMODE0_W { w: self } + } + #[doc = "Bits 27:28 - Capture mode Channel 1"] + #[inline(always)] + pub fn captmode1(&mut self) -> CAPTMODE1_W { + CAPTMODE1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/tc0/count8/ctrlbclr.rs b/pac/atsamc21n/src/tc0/count8/ctrlbclr.rs new file mode 100644 index 000000000000..76265674036a --- /dev/null +++ b/pac/atsamc21n/src/tc0/count8/ctrlbclr.rs @@ -0,0 +1,345 @@ +#[doc = "Register `CTRLBCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Counter Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `LUPD` reader - Lock Update"] +pub struct LUPD_R(crate::FieldReader); +impl LUPD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LUPD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LUPD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LUPD` writer - Lock Update"] +pub struct LUPD_W<'a> { + w: &'a mut W, +} +impl<'a> LUPD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ONESHOT` reader - One-Shot on Counter"] +pub struct ONESHOT_R(crate::FieldReader); +impl ONESHOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONESHOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONESHOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONESHOT` writer - One-Shot on Counter"] +pub struct ONESHOT_W<'a> { + w: &'a mut W, +} +impl<'a> ONESHOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Force a start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force a stop"] + STOP = 2, + #[doc = "3: Force update of double-buffered register"] + UPDATE = 3, + #[doc = "4: Force a read synchronization of COUNT"] + READSYNC = 4, + #[doc = "5: One-shot DMA trigger"] + DMAOS = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NONE), + 1 => Some(CMD_A::RETRIGGER), + 2 => Some(CMD_A::STOP), + 3 => Some(CMD_A::UPDATE), + 4 => Some(CMD_A::READSYNC), + 5 => Some(CMD_A::DMAOS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == CMD_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == CMD_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == CMD_A::STOP + } + #[doc = "Checks if the value of the field is `UPDATE`"] + #[inline(always)] + pub fn is_update(&self) -> bool { + **self == CMD_A::UPDATE + } + #[doc = "Checks if the value of the field is `READSYNC`"] + #[inline(always)] + pub fn is_readsync(&self) -> bool { + **self == CMD_A::READSYNC + } + #[doc = "Checks if the value of the field is `DMAOS`"] + #[inline(always)] + pub fn is_dmaos(&self) -> bool { + **self == CMD_A::DMAOS + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMD_A::NONE) + } + #[doc = "Force a start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMD_A::RETRIGGER) + } + #[doc = "Force a stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMD_A::STOP) + } + #[doc = "Force update of double-buffered register"] + #[inline(always)] + pub fn update(self) -> &'a mut W { + self.variant(CMD_A::UPDATE) + } + #[doc = "Force a read synchronization of COUNT"] + #[inline(always)] + pub fn readsync(self) -> &'a mut W { + self.variant(CMD_A::READSYNC) + } + #[doc = "One-shot DMA trigger"] + #[inline(always)] + pub fn dmaos(self) -> &'a mut W { + self.variant(CMD_A::DMAOS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 5)) | ((value as u8 & 0x07) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&self) -> LUPD_R { + LUPD_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 5) & 0x07) as u8) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&mut self) -> LUPD_W { + LUPD_W { w: self } + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&mut self) -> ONESHOT_W { + ONESHOT_W { w: self } + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbclr](index.html) module"] +pub struct CTRLBCLR_SPEC; +impl crate::RegisterSpec for CTRLBCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbclr::R](R) reader structure"] +impl crate::Readable for CTRLBCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbclr::W](W) writer structure"] +impl crate::Writable for CTRLBCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLBCLR to value 0"] +impl crate::Resettable for CTRLBCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/tc0/count8/ctrlbset.rs b/pac/atsamc21n/src/tc0/count8/ctrlbset.rs new file mode 100644 index 000000000000..610914c9c7c8 --- /dev/null +++ b/pac/atsamc21n/src/tc0/count8/ctrlbset.rs @@ -0,0 +1,345 @@ +#[doc = "Register `CTRLBSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Counter Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `LUPD` reader - Lock Update"] +pub struct LUPD_R(crate::FieldReader); +impl LUPD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LUPD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LUPD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LUPD` writer - Lock Update"] +pub struct LUPD_W<'a> { + w: &'a mut W, +} +impl<'a> LUPD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ONESHOT` reader - One-Shot on Counter"] +pub struct ONESHOT_R(crate::FieldReader); +impl ONESHOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONESHOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONESHOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONESHOT` writer - One-Shot on Counter"] +pub struct ONESHOT_W<'a> { + w: &'a mut W, +} +impl<'a> ONESHOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Force a start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force a stop"] + STOP = 2, + #[doc = "3: Force update of double-buffered register"] + UPDATE = 3, + #[doc = "4: Force a read synchronization of COUNT"] + READSYNC = 4, + #[doc = "5: One-shot DMA trigger"] + DMAOS = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NONE), + 1 => Some(CMD_A::RETRIGGER), + 2 => Some(CMD_A::STOP), + 3 => Some(CMD_A::UPDATE), + 4 => Some(CMD_A::READSYNC), + 5 => Some(CMD_A::DMAOS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == CMD_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == CMD_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == CMD_A::STOP + } + #[doc = "Checks if the value of the field is `UPDATE`"] + #[inline(always)] + pub fn is_update(&self) -> bool { + **self == CMD_A::UPDATE + } + #[doc = "Checks if the value of the field is `READSYNC`"] + #[inline(always)] + pub fn is_readsync(&self) -> bool { + **self == CMD_A::READSYNC + } + #[doc = "Checks if the value of the field is `DMAOS`"] + #[inline(always)] + pub fn is_dmaos(&self) -> bool { + **self == CMD_A::DMAOS + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMD_A::NONE) + } + #[doc = "Force a start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMD_A::RETRIGGER) + } + #[doc = "Force a stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMD_A::STOP) + } + #[doc = "Force update of double-buffered register"] + #[inline(always)] + pub fn update(self) -> &'a mut W { + self.variant(CMD_A::UPDATE) + } + #[doc = "Force a read synchronization of COUNT"] + #[inline(always)] + pub fn readsync(self) -> &'a mut W { + self.variant(CMD_A::READSYNC) + } + #[doc = "One-shot DMA trigger"] + #[inline(always)] + pub fn dmaos(self) -> &'a mut W { + self.variant(CMD_A::DMAOS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 5)) | ((value as u8 & 0x07) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&self) -> LUPD_R { + LUPD_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 5) & 0x07) as u8) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&mut self) -> LUPD_W { + LUPD_W { w: self } + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&mut self) -> ONESHOT_W { + ONESHOT_W { w: self } + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbset](index.html) module"] +pub struct CTRLBSET_SPEC; +impl crate::RegisterSpec for CTRLBSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbset::R](R) reader structure"] +impl crate::Readable for CTRLBSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbset::W](W) writer structure"] +impl crate::Writable for CTRLBSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLBSET to value 0"] +impl crate::Resettable for CTRLBSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/tc0/count8/dbgctrl.rs b/pac/atsamc21n/src/tc0/count8/dbgctrl.rs new file mode 100644 index 000000000000..0383e70d0429 --- /dev/null +++ b/pac/atsamc21n/src/tc0/count8/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Run During Debug"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Run During Debug"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/tc0/count8/drvctrl.rs b/pac/atsamc21n/src/tc0/count8/drvctrl.rs new file mode 100644 index 000000000000..323926b4b22d --- /dev/null +++ b/pac/atsamc21n/src/tc0/count8/drvctrl.rs @@ -0,0 +1,160 @@ +#[doc = "Register `DRVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DRVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INVEN0` reader - Output Waveform Invert Enable 0"] +pub struct INVEN0_R(crate::FieldReader); +impl INVEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN0` writer - Output Waveform Invert Enable 0"] +pub struct INVEN0_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `INVEN1` reader - Output Waveform Invert Enable 1"] +pub struct INVEN1_R(crate::FieldReader); +impl INVEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN1` writer - Output Waveform Invert Enable 1"] +pub struct INVEN1_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - Output Waveform Invert Enable 0"] + #[inline(always)] + pub fn inven0(&self) -> INVEN0_R { + INVEN0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Output Waveform Invert Enable 1"] + #[inline(always)] + pub fn inven1(&self) -> INVEN1_R { + INVEN1_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Output Waveform Invert Enable 0"] + #[inline(always)] + pub fn inven0(&mut self) -> INVEN0_W { + INVEN0_W { w: self } + } + #[doc = "Bit 1 - Output Waveform Invert Enable 1"] + #[inline(always)] + pub fn inven1(&mut self) -> INVEN1_W { + INVEN1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control C\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [drvctrl](index.html) module"] +pub struct DRVCTRL_SPEC; +impl crate::RegisterSpec for DRVCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [drvctrl::R](R) reader structure"] +impl crate::Readable for DRVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [drvctrl::W](W) writer structure"] +impl crate::Writable for DRVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DRVCTRL to value 0"] +impl crate::Resettable for DRVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/tc0/count8/evctrl.rs b/pac/atsamc21n/src/tc0/count8/evctrl.rs new file mode 100644 index 000000000000..7d4c38d486c1 --- /dev/null +++ b/pac/atsamc21n/src/tc0/count8/evctrl.rs @@ -0,0 +1,465 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Event Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EVACT_A { + #[doc = "0: Event action disabled"] + OFF = 0, + #[doc = "1: Start, restart or retrigger TC on event"] + RETRIGGER = 1, + #[doc = "2: Count on event"] + COUNT = 2, + #[doc = "3: Start TC on event"] + START = 3, + #[doc = "4: Time stamp capture"] + STAMP = 4, + #[doc = "5: Period catured in CC0, pulse width in CC1"] + PPW = 5, + #[doc = "6: Period catured in CC1, pulse width in CC0"] + PWP = 6, + #[doc = "7: Pulse width capture"] + PW = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EVACT_A) -> Self { + variant as _ + } +} +#[doc = "Field `EVACT` reader - Event Action"] +pub struct EVACT_R(crate::FieldReader); +impl EVACT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVACT_A { + match self.bits { + 0 => EVACT_A::OFF, + 1 => EVACT_A::RETRIGGER, + 2 => EVACT_A::COUNT, + 3 => EVACT_A::START, + 4 => EVACT_A::STAMP, + 5 => EVACT_A::PPW, + 6 => EVACT_A::PWP, + 7 => EVACT_A::PW, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == EVACT_A::OFF + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == EVACT_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `COUNT`"] + #[inline(always)] + pub fn is_count(&self) -> bool { + **self == EVACT_A::COUNT + } + #[doc = "Checks if the value of the field is `START`"] + #[inline(always)] + pub fn is_start(&self) -> bool { + **self == EVACT_A::START + } + #[doc = "Checks if the value of the field is `STAMP`"] + #[inline(always)] + pub fn is_stamp(&self) -> bool { + **self == EVACT_A::STAMP + } + #[doc = "Checks if the value of the field is `PPW`"] + #[inline(always)] + pub fn is_ppw(&self) -> bool { + **self == EVACT_A::PPW + } + #[doc = "Checks if the value of the field is `PWP`"] + #[inline(always)] + pub fn is_pwp(&self) -> bool { + **self == EVACT_A::PWP + } + #[doc = "Checks if the value of the field is `PW`"] + #[inline(always)] + pub fn is_pw(&self) -> bool { + **self == EVACT_A::PW + } +} +impl core::ops::Deref for EVACT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT` writer - Event Action"] +pub struct EVACT_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EVACT_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Event action disabled"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(EVACT_A::OFF) + } + #[doc = "Start, restart or retrigger TC on event"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(EVACT_A::RETRIGGER) + } + #[doc = "Count on event"] + #[inline(always)] + pub fn count(self) -> &'a mut W { + self.variant(EVACT_A::COUNT) + } + #[doc = "Start TC on event"] + #[inline(always)] + pub fn start(self) -> &'a mut W { + self.variant(EVACT_A::START) + } + #[doc = "Time stamp capture"] + #[inline(always)] + pub fn stamp(self) -> &'a mut W { + self.variant(EVACT_A::STAMP) + } + #[doc = "Period catured in CC0, pulse width in CC1"] + #[inline(always)] + pub fn ppw(self) -> &'a mut W { + self.variant(EVACT_A::PPW) + } + #[doc = "Period catured in CC1, pulse width in CC0"] + #[inline(always)] + pub fn pwp(self) -> &'a mut W { + self.variant(EVACT_A::PWP) + } + #[doc = "Pulse width capture"] + #[inline(always)] + pub fn pw(self) -> &'a mut W { + self.variant(EVACT_A::PW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u16 & 0x07); + self.w + } +} +#[doc = "Field `TCINV` reader - TC Event Input Polarity"] +pub struct TCINV_R(crate::FieldReader); +impl TCINV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCINV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCINV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCINV` writer - TC Event Input Polarity"] +pub struct TCINV_W<'a> { + w: &'a mut W, +} +impl<'a> TCINV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `TCEI` reader - TC Event Enable"] +pub struct TCEI_R(crate::FieldReader); +impl TCEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCEI` writer - TC Event Enable"] +pub struct TCEI_W<'a> { + w: &'a mut W, +} +impl<'a> TCEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `OVFEO` reader - Event Output Enable"] +pub struct OVFEO_R(crate::FieldReader); +impl OVFEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVFEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVFEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVFEO` writer - Event Output Enable"] +pub struct OVFEO_W<'a> { + w: &'a mut W, +} +impl<'a> OVFEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `MCEO0` reader - MC Event Output Enable 0"] +pub struct MCEO0_R(crate::FieldReader); +impl MCEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO0` writer - MC Event Output Enable 0"] +pub struct MCEO0_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u16 & 0x01) << 12); + self.w + } +} +#[doc = "Field `MCEO1` reader - MC Event Output Enable 1"] +pub struct MCEO1_R(crate::FieldReader); +impl MCEO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO1` writer - MC Event Output Enable 1"] +pub struct MCEO1_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u16 & 0x01) << 13); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Event Action"] + #[inline(always)] + pub fn evact(&self) -> EVACT_R { + EVACT_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 4 - TC Event Input Polarity"] + #[inline(always)] + pub fn tcinv(&self) -> TCINV_R { + TCINV_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - TC Event Enable"] + #[inline(always)] + pub fn tcei(&self) -> TCEI_R { + TCEI_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 8 - Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&self) -> OVFEO_R { + OVFEO_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 12 - MC Event Output Enable 0"] + #[inline(always)] + pub fn mceo0(&self) -> MCEO0_R { + MCEO0_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - MC Event Output Enable 1"] + #[inline(always)] + pub fn mceo1(&self) -> MCEO1_R { + MCEO1_R::new(((self.bits >> 13) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Event Action"] + #[inline(always)] + pub fn evact(&mut self) -> EVACT_W { + EVACT_W { w: self } + } + #[doc = "Bit 4 - TC Event Input Polarity"] + #[inline(always)] + pub fn tcinv(&mut self) -> TCINV_W { + TCINV_W { w: self } + } + #[doc = "Bit 5 - TC Event Enable"] + #[inline(always)] + pub fn tcei(&mut self) -> TCEI_W { + TCEI_W { w: self } + } + #[doc = "Bit 8 - Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&mut self) -> OVFEO_W { + OVFEO_W { w: self } + } + #[doc = "Bit 12 - MC Event Output Enable 0"] + #[inline(always)] + pub fn mceo0(&mut self) -> MCEO0_W { + MCEO0_W { w: self } + } + #[doc = "Bit 13 - MC Event Output Enable 1"] + #[inline(always)] + pub fn mceo1(&mut self) -> MCEO1_W { + MCEO1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/tc0/count8/intenclr.rs b/pac/atsamc21n/src/tc0/count8/intenclr.rs new file mode 100644 index 000000000000..af01ef5b7dca --- /dev/null +++ b/pac/atsamc21n/src/tc0/count8/intenclr.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - OVF Interrupt Disable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - OVF Interrupt Disable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - ERR Interrupt Disable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - ERR Interrupt Disable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MC0` reader - MC Interrupt Disable 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - MC Interrupt Disable 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - MC Interrupt Disable 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - MC Interrupt Disable 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - OVF Interrupt Disable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ERR Interrupt Disable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - MC Interrupt Disable 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - MC Interrupt Disable 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - OVF Interrupt Disable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - ERR Interrupt Disable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 4 - MC Interrupt Disable 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - MC Interrupt Disable 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/tc0/count8/intenset.rs b/pac/atsamc21n/src/tc0/count8/intenset.rs new file mode 100644 index 000000000000..0e1883a2f20a --- /dev/null +++ b/pac/atsamc21n/src/tc0/count8/intenset.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - OVF Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - OVF Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - ERR Interrupt Enable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - ERR Interrupt Enable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MC0` reader - MC Interrupt Enable 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - MC Interrupt Enable 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - MC Interrupt Enable 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - MC Interrupt Enable 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - OVF Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ERR Interrupt Enable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - MC Interrupt Enable 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - MC Interrupt Enable 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - OVF Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - ERR Interrupt Enable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 4 - MC Interrupt Enable 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - MC Interrupt Enable 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/tc0/count8/intflag.rs b/pac/atsamc21n/src/tc0/count8/intflag.rs new file mode 100644 index 000000000000..1dddffaf8e7f --- /dev/null +++ b/pac/atsamc21n/src/tc0/count8/intflag.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - OVF Interrupt Flag"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - OVF Interrupt Flag"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - ERR Interrupt Flag"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - ERR Interrupt Flag"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MC0` reader - MC Interrupt Flag 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - MC Interrupt Flag 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - MC Interrupt Flag 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - MC Interrupt Flag 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - OVF Interrupt Flag"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ERR Interrupt Flag"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - MC Interrupt Flag 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - MC Interrupt Flag 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - OVF Interrupt Flag"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - ERR Interrupt Flag"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 4 - MC Interrupt Flag 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - MC Interrupt Flag 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/tc0/count8/per.rs b/pac/atsamc21n/src/tc0/count8/per.rs new file mode 100644 index 000000000000..c9ab52e247d8 --- /dev/null +++ b/pac/atsamc21n/src/tc0/count8/per.rs @@ -0,0 +1,103 @@ +#[doc = "Register `PER` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PER` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER` reader - Period Value"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` writer - Period Value"] +pub struct PER_W<'a> { + w: &'a mut W, +} +impl<'a> PER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Period Value"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Period Value"] + #[inline(always)] + pub fn per(&mut self) -> PER_W { + PER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT8 Period\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [per](index.html) module"] +pub struct PER_SPEC; +impl crate::RegisterSpec for PER_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [per::R](R) reader structure"] +impl crate::Readable for PER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [per::W](W) writer structure"] +impl crate::Writable for PER_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PER to value 0xff"] +impl crate::Resettable for PER_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xff + } +} diff --git a/pac/atsamc21n/src/tc0/count8/perbuf.rs b/pac/atsamc21n/src/tc0/count8/perbuf.rs new file mode 100644 index 000000000000..cbd500e2bbe1 --- /dev/null +++ b/pac/atsamc21n/src/tc0/count8/perbuf.rs @@ -0,0 +1,103 @@ +#[doc = "Register `PERBUF` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PERBUF` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PERBUF` reader - Period Buffer Value"] +pub struct PERBUF_R(crate::FieldReader); +impl PERBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PERBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERBUF` writer - Period Buffer Value"] +pub struct PERBUF_W<'a> { + w: &'a mut W, +} +impl<'a> PERBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Period Buffer Value"] + #[inline(always)] + pub fn perbuf(&self) -> PERBUF_R { + PERBUF_R::new(self.bits as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Period Buffer Value"] + #[inline(always)] + pub fn perbuf(&mut self) -> PERBUF_W { + PERBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT8 Period Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [perbuf](index.html) module"] +pub struct PERBUF_SPEC; +impl crate::RegisterSpec for PERBUF_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [perbuf::R](R) reader structure"] +impl crate::Readable for PERBUF_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [perbuf::W](W) writer structure"] +impl crate::Writable for PERBUF_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PERBUF to value 0xff"] +impl crate::Resettable for PERBUF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xff + } +} diff --git a/pac/atsamc21n/src/tc0/count8/status.rs b/pac/atsamc21n/src/tc0/count8/status.rs new file mode 100644 index 000000000000..5088af446830 --- /dev/null +++ b/pac/atsamc21n/src/tc0/count8/status.rs @@ -0,0 +1,301 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `STOP` reader - Stop Status Flag"] +pub struct STOP_R(crate::FieldReader); +impl STOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STOP` writer - Stop Status Flag"] +pub struct STOP_W<'a> { + w: &'a mut W, +} +impl<'a> STOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SLAVE` reader - Slave Status Flag"] +pub struct SLAVE_R(crate::FieldReader); +impl SLAVE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLAVE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SLAVE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLAVE` writer - Slave Status Flag"] +pub struct SLAVE_W<'a> { + w: &'a mut W, +} +impl<'a> SLAVE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PERBUFV` reader - Synchronization Busy Status"] +pub struct PERBUFV_R(crate::FieldReader); +impl PERBUFV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PERBUFV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERBUFV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERBUFV` writer - Synchronization Busy Status"] +pub struct PERBUFV_W<'a> { + w: &'a mut W, +} +impl<'a> PERBUFV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CCBUFV0` reader - Compare channel buffer 0 valid"] +pub struct CCBUFV0_R(crate::FieldReader); +impl CCBUFV0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBUFV0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUFV0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUFV0` writer - Compare channel buffer 0 valid"] +pub struct CCBUFV0_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUFV0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `CCBUFV1` reader - Compare channel buffer 1 valid"] +pub struct CCBUFV1_R(crate::FieldReader); +impl CCBUFV1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBUFV1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUFV1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUFV1` writer - Compare channel buffer 1 valid"] +pub struct CCBUFV1_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUFV1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Stop Status Flag"] + #[inline(always)] + pub fn stop(&self) -> STOP_R { + STOP_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Slave Status Flag"] + #[inline(always)] + pub fn slave(&self) -> SLAVE_R { + SLAVE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 3 - Synchronization Busy Status"] + #[inline(always)] + pub fn perbufv(&self) -> PERBUFV_R { + PERBUFV_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Compare channel buffer 0 valid"] + #[inline(always)] + pub fn ccbufv0(&self) -> CCBUFV0_R { + CCBUFV0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Compare channel buffer 1 valid"] + #[inline(always)] + pub fn ccbufv1(&self) -> CCBUFV1_R { + CCBUFV1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Stop Status Flag"] + #[inline(always)] + pub fn stop(&mut self) -> STOP_W { + STOP_W { w: self } + } + #[doc = "Bit 1 - Slave Status Flag"] + #[inline(always)] + pub fn slave(&mut self) -> SLAVE_W { + SLAVE_W { w: self } + } + #[doc = "Bit 3 - Synchronization Busy Status"] + #[inline(always)] + pub fn perbufv(&mut self) -> PERBUFV_W { + PERBUFV_W { w: self } + } + #[doc = "Bit 4 - Compare channel buffer 0 valid"] + #[inline(always)] + pub fn ccbufv0(&mut self) -> CCBUFV0_W { + CCBUFV0_W { w: self } + } + #[doc = "Bit 5 - Compare channel buffer 1 valid"] + #[inline(always)] + pub fn ccbufv1(&mut self) -> CCBUFV1_W { + CCBUFV1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0x01"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pac/atsamc21n/src/tc0/count8/syncbusy.rs b/pac/atsamc21n/src/tc0/count8/syncbusy.rs new file mode 100644 index 000000000000..7ad8d91a84de --- /dev/null +++ b/pac/atsamc21n/src/tc0/count8/syncbusy.rs @@ -0,0 +1,193 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - swrst"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLB` reader - CTRLB"] +pub struct CTRLB_R(crate::FieldReader); +impl CTRLB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STATUS` reader - STATUS"] +pub struct STATUS_R(crate::FieldReader); +impl STATUS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STATUS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STATUS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` reader - Counter"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` reader - Period"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC0` reader - Compare Channel 0"] +pub struct CC0_R(crate::FieldReader); +impl CC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC1` reader - Compare Channel 1"] +pub struct CC1_R(crate::FieldReader); +impl CC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - swrst"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - CTRLB"] + #[inline(always)] + pub fn ctrlb(&self) -> CTRLB_R { + CTRLB_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - STATUS"] + #[inline(always)] + pub fn status(&self) -> STATUS_R { + STATUS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Counter"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Period"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Compare Channel 0"] + #[inline(always)] + pub fn cc0(&self) -> CC0_R { + CC0_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Compare Channel 1"] + #[inline(always)] + pub fn cc1(&self) -> CC1_R { + CC1_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +#[doc = "Synchronization Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/tc0/count8/wave.rs b/pac/atsamc21n/src/tc0/count8/wave.rs new file mode 100644 index 000000000000..46061b24b75d --- /dev/null +++ b/pac/atsamc21n/src/tc0/count8/wave.rs @@ -0,0 +1,178 @@ +#[doc = "Register `WAVE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WAVE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Waveform Generation Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WAVEGEN_A { + #[doc = "0: Normal frequency"] + NFRQ = 0, + #[doc = "1: Match frequency"] + MFRQ = 1, + #[doc = "2: Normal PWM"] + NPWM = 2, + #[doc = "3: Match PWM"] + MPWM = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WAVEGEN_A) -> Self { + variant as _ + } +} +#[doc = "Field `WAVEGEN` reader - Waveform Generation Mode"] +pub struct WAVEGEN_R(crate::FieldReader); +impl WAVEGEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WAVEGEN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> WAVEGEN_A { + match self.bits { + 0 => WAVEGEN_A::NFRQ, + 1 => WAVEGEN_A::MFRQ, + 2 => WAVEGEN_A::NPWM, + 3 => WAVEGEN_A::MPWM, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NFRQ`"] + #[inline(always)] + pub fn is_nfrq(&self) -> bool { + **self == WAVEGEN_A::NFRQ + } + #[doc = "Checks if the value of the field is `MFRQ`"] + #[inline(always)] + pub fn is_mfrq(&self) -> bool { + **self == WAVEGEN_A::MFRQ + } + #[doc = "Checks if the value of the field is `NPWM`"] + #[inline(always)] + pub fn is_npwm(&self) -> bool { + **self == WAVEGEN_A::NPWM + } + #[doc = "Checks if the value of the field is `MPWM`"] + #[inline(always)] + pub fn is_mpwm(&self) -> bool { + **self == WAVEGEN_A::MPWM + } +} +impl core::ops::Deref for WAVEGEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAVEGEN` writer - Waveform Generation Mode"] +pub struct WAVEGEN_W<'a> { + w: &'a mut W, +} +impl<'a> WAVEGEN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WAVEGEN_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Normal frequency"] + #[inline(always)] + pub fn nfrq(self) -> &'a mut W { + self.variant(WAVEGEN_A::NFRQ) + } + #[doc = "Match frequency"] + #[inline(always)] + pub fn mfrq(self) -> &'a mut W { + self.variant(WAVEGEN_A::MFRQ) + } + #[doc = "Normal PWM"] + #[inline(always)] + pub fn npwm(self) -> &'a mut W { + self.variant(WAVEGEN_A::NPWM) + } + #[doc = "Match PWM"] + #[inline(always)] + pub fn mpwm(self) -> &'a mut W { + self.variant(WAVEGEN_A::MPWM) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u8 & 0x03); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Waveform Generation Mode"] + #[inline(always)] + pub fn wavegen(&self) -> WAVEGEN_R { + WAVEGEN_R::new((self.bits & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Waveform Generation Mode"] + #[inline(always)] + pub fn wavegen(&mut self) -> WAVEGEN_W { + WAVEGEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Waveform Generation Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wave](index.html) module"] +pub struct WAVE_SPEC; +impl crate::RegisterSpec for WAVE_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [wave::R](R) reader structure"] +impl crate::Readable for WAVE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wave::W](W) writer structure"] +impl crate::Writable for WAVE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WAVE to value 0"] +impl crate::Resettable for WAVE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/tcc0.rs b/pac/atsamc21n/src/tcc0.rs new file mode 100644 index 000000000000..6ce813a9e3d5 --- /dev/null +++ b/pac/atsamc21n/src/tcc0.rs @@ -0,0 +1,359 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control A"] + pub ctrla: crate::Reg, + #[doc = "0x04 - Control B Clear"] + pub ctrlbclr: crate::Reg, + #[doc = "0x05 - Control B Set"] + pub ctrlbset: crate::Reg, + _reserved3: [u8; 0x02], + #[doc = "0x08 - Synchronization Busy"] + pub syncbusy: crate::Reg, + #[doc = "0x0c - Recoverable Fault A Configuration"] + pub fctrla: crate::Reg, + #[doc = "0x10 - Recoverable Fault B Configuration"] + pub fctrlb: crate::Reg, + #[doc = "0x14 - Waveform Extension Configuration"] + pub wexctrl: crate::Reg, + #[doc = "0x18 - Driver Control"] + pub drvctrl: crate::Reg, + _reserved8: [u8; 0x02], + #[doc = "0x1e - Debug Control"] + pub dbgctrl: crate::Reg, + _reserved9: [u8; 0x01], + #[doc = "0x20 - Event Control"] + pub evctrl: crate::Reg, + #[doc = "0x24 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x28 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x2c - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + #[doc = "0x30 - Status"] + pub status: crate::Reg, + _reserved_14_count: [u8; 0x04], + #[doc = "0x38 - Pattern"] + pub patt: crate::Reg, + _reserved16: [u8; 0x02], + #[doc = "0x3c - Waveform Control"] + pub wave: crate::Reg, + _reserved_17_per: [u8; 0x04], + _reserved_18_cc: [u8; 0x10], + _reserved19: [u8; 0x10], + #[doc = "0x64 - Pattern Buffer"] + pub pattbuf: crate::Reg, + _reserved20: [u8; 0x06], + _reserved_20_perbuf: [u8; 0x04], + _reserved_21_ccbuf: [u8; 0x10], +} +impl RegisterBlock { + #[doc = "0x34 - Count"] + #[inline(always)] + pub fn count_dith6_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(52usize) + as *const crate::Reg) + } + } + #[doc = "0x34 - Count"] + #[inline(always)] + pub fn count_dith5_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(52usize) + as *const crate::Reg) + } + } + #[doc = "0x34 - Count"] + #[inline(always)] + pub fn count_dith4_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(52usize) + as *const crate::Reg) + } + } + #[doc = "0x34 - Count"] + #[inline(always)] + pub fn count(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(52usize) + as *const crate::Reg) + } + } + #[doc = "0x40 - Period"] + #[inline(always)] + pub fn per_dith6_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(64usize) + as *const crate::Reg) + } + } + #[doc = "0x40 - Period"] + #[inline(always)] + pub fn per_dith5_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(64usize) + as *const crate::Reg) + } + } + #[doc = "0x40 - Period"] + #[inline(always)] + pub fn per_dith4_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(64usize) + as *const crate::Reg) + } + } + #[doc = "0x40 - Period"] + #[inline(always)] + pub fn per(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(64usize) + as *const crate::Reg) + } + } + #[doc = "0x44..0x54 - Compare and Capture"] + #[inline(always)] + pub fn cc_dith6_mode(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(68usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x44..0x54 - Compare and Capture"] + #[inline(always)] + pub fn cc_dith5_mode(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(68usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x44..0x54 - Compare and Capture"] + #[inline(always)] + pub fn cc_dith4_mode(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(68usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x44..0x54 - Compare and Capture"] + #[inline(always)] + pub fn cc(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(68usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x6c - Period Buffer"] + #[inline(always)] + pub fn perbuf_dith6_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(108usize) + as *const crate::Reg) + } + } + #[doc = "0x6c - Period Buffer"] + #[inline(always)] + pub fn perbuf_dith5_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(108usize) + as *const crate::Reg) + } + } + #[doc = "0x6c - Period Buffer"] + #[inline(always)] + pub fn perbuf_dith4_mode(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(108usize) + as *const crate::Reg) + } + } + #[doc = "0x6c - Period Buffer"] + #[inline(always)] + pub fn perbuf(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(108usize) + as *const crate::Reg) + } + } + #[doc = "0x70..0x80 - Compare and Capture Buffer"] + #[inline(always)] + pub fn ccbuf_dith6_mode(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(112usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x70..0x80 - Compare and Capture Buffer"] + #[inline(always)] + pub fn ccbuf_dith5_mode(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(112usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x70..0x80 - Compare and Capture Buffer"] + #[inline(always)] + pub fn ccbuf_dith4_mode(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(112usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x70..0x80 - Compare and Capture Buffer"] + #[inline(always)] + pub fn ccbuf(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(112usize) + as *const [crate::Reg; 4]) + } + } +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "CTRLBCLR register accessor: an alias for `Reg`"] +pub type CTRLBCLR = crate::Reg; +#[doc = "Control B Clear"] +pub mod ctrlbclr; +#[doc = "CTRLBSET register accessor: an alias for `Reg`"] +pub type CTRLBSET = crate::Reg; +#[doc = "Control B Set"] +pub mod ctrlbset; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Busy"] +pub mod syncbusy; +#[doc = "FCTRLA register accessor: an alias for `Reg`"] +pub type FCTRLA = crate::Reg; +#[doc = "Recoverable Fault A Configuration"] +pub mod fctrla; +#[doc = "FCTRLB register accessor: an alias for `Reg`"] +pub type FCTRLB = crate::Reg; +#[doc = "Recoverable Fault B Configuration"] +pub mod fctrlb; +#[doc = "WEXCTRL register accessor: an alias for `Reg`"] +pub type WEXCTRL = crate::Reg; +#[doc = "Waveform Extension Configuration"] +pub mod wexctrl; +#[doc = "DRVCTRL register accessor: an alias for `Reg`"] +pub type DRVCTRL = crate::Reg; +#[doc = "Driver Control"] +pub mod drvctrl; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "COUNT register accessor: an alias for `Reg`"] +pub type COUNT = crate::Reg; +#[doc = "Count"] +pub mod count; +#[doc = "COUNT_DITH4_MODE register accessor: an alias for `Reg`"] +pub type COUNT_DITH4_MODE = crate::Reg; +#[doc = "Count"] +pub mod count_dith4_mode; +#[doc = "COUNT_DITH5_MODE register accessor: an alias for `Reg`"] +pub type COUNT_DITH5_MODE = crate::Reg; +#[doc = "Count"] +pub mod count_dith5_mode; +#[doc = "COUNT_DITH6_MODE register accessor: an alias for `Reg`"] +pub type COUNT_DITH6_MODE = crate::Reg; +#[doc = "Count"] +pub mod count_dith6_mode; +#[doc = "PATT register accessor: an alias for `Reg`"] +pub type PATT = crate::Reg; +#[doc = "Pattern"] +pub mod patt; +#[doc = "WAVE register accessor: an alias for `Reg`"] +pub type WAVE = crate::Reg; +#[doc = "Waveform Control"] +pub mod wave; +#[doc = "PER register accessor: an alias for `Reg`"] +pub type PER = crate::Reg; +#[doc = "Period"] +pub mod per; +#[doc = "PER_DITH4_MODE register accessor: an alias for `Reg`"] +pub type PER_DITH4_MODE = crate::Reg; +#[doc = "Period"] +pub mod per_dith4_mode; +#[doc = "PER_DITH5_MODE register accessor: an alias for `Reg`"] +pub type PER_DITH5_MODE = crate::Reg; +#[doc = "Period"] +pub mod per_dith5_mode; +#[doc = "PER_DITH6_MODE register accessor: an alias for `Reg`"] +pub type PER_DITH6_MODE = crate::Reg; +#[doc = "Period"] +pub mod per_dith6_mode; +#[doc = "CC register accessor: an alias for `Reg`"] +pub type CC = crate::Reg; +#[doc = "Compare and Capture"] +pub mod cc; +#[doc = "CC_DITH4_MODE register accessor: an alias for `Reg`"] +pub type CC_DITH4_MODE = crate::Reg; +#[doc = "Compare and Capture"] +pub mod cc_dith4_mode; +#[doc = "CC_DITH5_MODE register accessor: an alias for `Reg`"] +pub type CC_DITH5_MODE = crate::Reg; +#[doc = "Compare and Capture"] +pub mod cc_dith5_mode; +#[doc = "CC_DITH6_MODE register accessor: an alias for `Reg`"] +pub type CC_DITH6_MODE = crate::Reg; +#[doc = "Compare and Capture"] +pub mod cc_dith6_mode; +#[doc = "PATTBUF register accessor: an alias for `Reg`"] +pub type PATTBUF = crate::Reg; +#[doc = "Pattern Buffer"] +pub mod pattbuf; +#[doc = "PERBUF register accessor: an alias for `Reg`"] +pub type PERBUF = crate::Reg; +#[doc = "Period Buffer"] +pub mod perbuf; +#[doc = "PERBUF_DITH4_MODE register accessor: an alias for `Reg`"] +pub type PERBUF_DITH4_MODE = crate::Reg; +#[doc = "Period Buffer"] +pub mod perbuf_dith4_mode; +#[doc = "PERBUF_DITH5_MODE register accessor: an alias for `Reg`"] +pub type PERBUF_DITH5_MODE = crate::Reg; +#[doc = "Period Buffer"] +pub mod perbuf_dith5_mode; +#[doc = "PERBUF_DITH6_MODE register accessor: an alias for `Reg`"] +pub type PERBUF_DITH6_MODE = crate::Reg; +#[doc = "Period Buffer"] +pub mod perbuf_dith6_mode; +#[doc = "CCBUF register accessor: an alias for `Reg`"] +pub type CCBUF = crate::Reg; +#[doc = "Compare and Capture Buffer"] +pub mod ccbuf; +#[doc = "CCBUF_DITH4_MODE register accessor: an alias for `Reg`"] +pub type CCBUF_DITH4_MODE = crate::Reg; +#[doc = "Compare and Capture Buffer"] +pub mod ccbuf_dith4_mode; +#[doc = "CCBUF_DITH5_MODE register accessor: an alias for `Reg`"] +pub type CCBUF_DITH5_MODE = crate::Reg; +#[doc = "Compare and Capture Buffer"] +pub mod ccbuf_dith5_mode; +#[doc = "CCBUF_DITH6_MODE register accessor: an alias for `Reg`"] +pub type CCBUF_DITH6_MODE = crate::Reg; +#[doc = "Compare and Capture Buffer"] +pub mod ccbuf_dith6_mode; diff --git a/pac/atsamc21n/src/tcc0/cc.rs b/pac/atsamc21n/src/tcc0/cc.rs new file mode 100644 index 000000000000..c4d6df7a9a20 --- /dev/null +++ b/pac/atsamc21n/src/tcc0/cc.rs @@ -0,0 +1,104 @@ +#[doc = "Register `CC[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CC[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CC` reader - Channel Compare/Capture Value"] +pub struct CC_R(crate::FieldReader); +impl CC_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC` writer - Channel Compare/Capture Value"] +pub struct CC_W<'a> { + w: &'a mut W, +} +impl<'a> CC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&self) -> CC_R { + CC_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&mut self) -> CC_W { + CC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc](index.html) module"] +pub struct CC_SPEC; +impl crate::RegisterSpec for CC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cc::R](R) reader structure"] +impl crate::Readable for CC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cc::W](W) writer structure"] +impl crate::Writable for CC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CC[%s] +to value 0"] +impl crate::Resettable for CC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/tcc0/cc_dith4_mode.rs b/pac/atsamc21n/src/tcc0/cc_dith4_mode.rs new file mode 100644 index 000000000000..c45d8b6bac41 --- /dev/null +++ b/pac/atsamc21n/src/tcc0/cc_dith4_mode.rs @@ -0,0 +1,141 @@ +#[doc = "Register `CC_DITH4_MODE[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CC_DITH4_MODE[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHER` reader - Dithering Cycle Number"] +pub struct DITHER_R(crate::FieldReader); +impl DITHER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHER` writer - Dithering Cycle Number"] +pub struct DITHER_W<'a> { + w: &'a mut W, +} +impl<'a> DITHER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Field `CC` reader - Channel Compare/Capture Value"] +pub struct CC_R(crate::FieldReader); +impl CC_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC` writer - Channel Compare/Capture Value"] +pub struct CC_W<'a> { + w: &'a mut W, +} +impl<'a> CC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x000f_ffff << 4)) | ((value as u32 & 0x000f_ffff) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&self) -> DITHER_R { + DITHER_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&self) -> CC_R { + CC_R::new(((self.bits >> 4) & 0x000f_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:3 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&mut self) -> DITHER_W { + DITHER_W { w: self } + } + #[doc = "Bits 4:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&mut self) -> CC_W { + CC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc_dith4_mode](index.html) module"] +pub struct CC_DITH4_MODE_SPEC; +impl crate::RegisterSpec for CC_DITH4_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cc_dith4_mode::R](R) reader structure"] +impl crate::Readable for CC_DITH4_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cc_dith4_mode::W](W) writer structure"] +impl crate::Writable for CC_DITH4_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CC_DITH4_MODE[%s] +to value 0"] +impl crate::Resettable for CC_DITH4_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/tcc0/cc_dith5_mode.rs b/pac/atsamc21n/src/tcc0/cc_dith5_mode.rs new file mode 100644 index 000000000000..0592b923051a --- /dev/null +++ b/pac/atsamc21n/src/tcc0/cc_dith5_mode.rs @@ -0,0 +1,141 @@ +#[doc = "Register `CC_DITH5_MODE[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CC_DITH5_MODE[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHER` reader - Dithering Cycle Number"] +pub struct DITHER_R(crate::FieldReader); +impl DITHER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHER` writer - Dithering Cycle Number"] +pub struct DITHER_W<'a> { + w: &'a mut W, +} +impl<'a> DITHER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f); + self.w + } +} +#[doc = "Field `CC` reader - Channel Compare/Capture Value"] +pub struct CC_R(crate::FieldReader); +impl CC_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC` writer - Channel Compare/Capture Value"] +pub struct CC_W<'a> { + w: &'a mut W, +} +impl<'a> CC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0007_ffff << 5)) | ((value as u32 & 0x0007_ffff) << 5); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&self) -> DITHER_R { + DITHER_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&self) -> CC_R { + CC_R::new(((self.bits >> 5) & 0x0007_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:4 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&mut self) -> DITHER_W { + DITHER_W { w: self } + } + #[doc = "Bits 5:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&mut self) -> CC_W { + CC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc_dith5_mode](index.html) module"] +pub struct CC_DITH5_MODE_SPEC; +impl crate::RegisterSpec for CC_DITH5_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cc_dith5_mode::R](R) reader structure"] +impl crate::Readable for CC_DITH5_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cc_dith5_mode::W](W) writer structure"] +impl crate::Writable for CC_DITH5_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CC_DITH5_MODE[%s] +to value 0"] +impl crate::Resettable for CC_DITH5_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/tcc0/cc_dith6_mode.rs b/pac/atsamc21n/src/tcc0/cc_dith6_mode.rs new file mode 100644 index 000000000000..62a82a872426 --- /dev/null +++ b/pac/atsamc21n/src/tcc0/cc_dith6_mode.rs @@ -0,0 +1,141 @@ +#[doc = "Register `CC_DITH6_MODE[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CC_DITH6_MODE[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHER` reader - Dithering Cycle Number"] +pub struct DITHER_R(crate::FieldReader); +impl DITHER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHER` writer - Dithering Cycle Number"] +pub struct DITHER_W<'a> { + w: &'a mut W, +} +impl<'a> DITHER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +#[doc = "Field `CC` reader - Channel Compare/Capture Value"] +pub struct CC_R(crate::FieldReader); +impl CC_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC` writer - Channel Compare/Capture Value"] +pub struct CC_W<'a> { + w: &'a mut W, +} +impl<'a> CC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0003_ffff << 6)) | ((value as u32 & 0x0003_ffff) << 6); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&self) -> DITHER_R { + DITHER_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&self) -> CC_R { + CC_R::new(((self.bits >> 6) & 0x0003_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:5 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&mut self) -> DITHER_W { + DITHER_W { w: self } + } + #[doc = "Bits 6:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&mut self) -> CC_W { + CC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc_dith6_mode](index.html) module"] +pub struct CC_DITH6_MODE_SPEC; +impl crate::RegisterSpec for CC_DITH6_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cc_dith6_mode::R](R) reader structure"] +impl crate::Readable for CC_DITH6_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cc_dith6_mode::W](W) writer structure"] +impl crate::Writable for CC_DITH6_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CC_DITH6_MODE[%s] +to value 0"] +impl crate::Resettable for CC_DITH6_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/tcc0/ccbuf.rs b/pac/atsamc21n/src/tcc0/ccbuf.rs new file mode 100644 index 000000000000..a4db1135f095 --- /dev/null +++ b/pac/atsamc21n/src/tcc0/ccbuf.rs @@ -0,0 +1,104 @@ +#[doc = "Register `CCBUF[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CCBUF[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CCBUF` reader - Channel Compare/Capture Buffer Value"] +pub struct CCBUF_R(crate::FieldReader); +impl CCBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CCBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUF` writer - Channel Compare/Capture Buffer Value"] +pub struct CCBUF_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccbuf(&self) -> CCBUF_R { + CCBUF_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccbuf(&mut self) -> CCBUF_W { + CCBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccbuf](index.html) module"] +pub struct CCBUF_SPEC; +impl crate::RegisterSpec for CCBUF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ccbuf::R](R) reader structure"] +impl crate::Readable for CCBUF_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ccbuf::W](W) writer structure"] +impl crate::Writable for CCBUF_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CCBUF[%s] +to value 0"] +impl crate::Resettable for CCBUF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/tcc0/ccbuf_dith4_mode.rs b/pac/atsamc21n/src/tcc0/ccbuf_dith4_mode.rs new file mode 100644 index 000000000000..dfa16e936175 --- /dev/null +++ b/pac/atsamc21n/src/tcc0/ccbuf_dith4_mode.rs @@ -0,0 +1,141 @@ +#[doc = "Register `CCBUF_DITH4_MODE[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CCBUF_DITH4_MODE[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CCBUF` reader - Channel Compare/Capture Buffer Value"] +pub struct CCBUF_R(crate::FieldReader); +impl CCBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CCBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUF` writer - Channel Compare/Capture Buffer Value"] +pub struct CCBUF_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Field `DITHERBUF` reader - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_R(crate::FieldReader); +impl DITHERBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + DITHERBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHERBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHERBUF` writer - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_W<'a> { + w: &'a mut W, +} +impl<'a> DITHERBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x000f_ffff << 4)) | ((value as u32 & 0x000f_ffff) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccbuf(&self) -> CCBUF_R { + CCBUF_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:23 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&self) -> DITHERBUF_R { + DITHERBUF_R::new(((self.bits >> 4) & 0x000f_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:3 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccbuf(&mut self) -> CCBUF_W { + CCBUF_W { w: self } + } + #[doc = "Bits 4:23 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&mut self) -> DITHERBUF_W { + DITHERBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccbuf_dith4_mode](index.html) module"] +pub struct CCBUF_DITH4_MODE_SPEC; +impl crate::RegisterSpec for CCBUF_DITH4_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ccbuf_dith4_mode::R](R) reader structure"] +impl crate::Readable for CCBUF_DITH4_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ccbuf_dith4_mode::W](W) writer structure"] +impl crate::Writable for CCBUF_DITH4_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CCBUF_DITH4_MODE[%s] +to value 0"] +impl crate::Resettable for CCBUF_DITH4_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/tcc0/ccbuf_dith5_mode.rs b/pac/atsamc21n/src/tcc0/ccbuf_dith5_mode.rs new file mode 100644 index 000000000000..0c78ba3303c0 --- /dev/null +++ b/pac/atsamc21n/src/tcc0/ccbuf_dith5_mode.rs @@ -0,0 +1,141 @@ +#[doc = "Register `CCBUF_DITH5_MODE[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CCBUF_DITH5_MODE[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHERBUF` reader - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_R(crate::FieldReader); +impl DITHERBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHERBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHERBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHERBUF` writer - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_W<'a> { + w: &'a mut W, +} +impl<'a> DITHERBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f); + self.w + } +} +#[doc = "Field `CCBUF` reader - Channel Compare/Capture Buffer Value"] +pub struct CCBUF_R(crate::FieldReader); +impl CCBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CCBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUF` writer - Channel Compare/Capture Buffer Value"] +pub struct CCBUF_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0007_ffff << 5)) | ((value as u32 & 0x0007_ffff) << 5); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&self) -> DITHERBUF_R { + DITHERBUF_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:23 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccbuf(&self) -> CCBUF_R { + CCBUF_R::new(((self.bits >> 5) & 0x0007_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:4 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&mut self) -> DITHERBUF_W { + DITHERBUF_W { w: self } + } + #[doc = "Bits 5:23 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccbuf(&mut self) -> CCBUF_W { + CCBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccbuf_dith5_mode](index.html) module"] +pub struct CCBUF_DITH5_MODE_SPEC; +impl crate::RegisterSpec for CCBUF_DITH5_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ccbuf_dith5_mode::R](R) reader structure"] +impl crate::Readable for CCBUF_DITH5_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ccbuf_dith5_mode::W](W) writer structure"] +impl crate::Writable for CCBUF_DITH5_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CCBUF_DITH5_MODE[%s] +to value 0"] +impl crate::Resettable for CCBUF_DITH5_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/tcc0/ccbuf_dith6_mode.rs b/pac/atsamc21n/src/tcc0/ccbuf_dith6_mode.rs new file mode 100644 index 000000000000..8d19b8a9e595 --- /dev/null +++ b/pac/atsamc21n/src/tcc0/ccbuf_dith6_mode.rs @@ -0,0 +1,141 @@ +#[doc = "Register `CCBUF_DITH6_MODE[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CCBUF_DITH6_MODE[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHERBUF` reader - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_R(crate::FieldReader); +impl DITHERBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHERBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHERBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHERBUF` writer - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_W<'a> { + w: &'a mut W, +} +impl<'a> DITHERBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +#[doc = "Field `CCBUF` reader - Channel Compare/Capture Buffer Value"] +pub struct CCBUF_R(crate::FieldReader); +impl CCBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CCBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUF` writer - Channel Compare/Capture Buffer Value"] +pub struct CCBUF_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0003_ffff << 6)) | ((value as u32 & 0x0003_ffff) << 6); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&self) -> DITHERBUF_R { + DITHERBUF_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:23 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccbuf(&self) -> CCBUF_R { + CCBUF_R::new(((self.bits >> 6) & 0x0003_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:5 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&mut self) -> DITHERBUF_W { + DITHERBUF_W { w: self } + } + #[doc = "Bits 6:23 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccbuf(&mut self) -> CCBUF_W { + CCBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccbuf_dith6_mode](index.html) module"] +pub struct CCBUF_DITH6_MODE_SPEC; +impl crate::RegisterSpec for CCBUF_DITH6_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ccbuf_dith6_mode::R](R) reader structure"] +impl crate::Readable for CCBUF_DITH6_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ccbuf_dith6_mode::W](W) writer structure"] +impl crate::Writable for CCBUF_DITH6_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CCBUF_DITH6_MODE[%s] +to value 0"] +impl crate::Resettable for CCBUF_DITH6_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/tcc0/count.rs b/pac/atsamc21n/src/tcc0/count.rs new file mode 100644 index 000000000000..7628f2c0d5e1 --- /dev/null +++ b/pac/atsamc21n/src/tcc0/count.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Count\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count](index.html) module"] +pub struct COUNT_SPEC; +impl crate::RegisterSpec for COUNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [count::R](R) reader structure"] +impl crate::Readable for COUNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count::W](W) writer structure"] +impl crate::Writable for COUNT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT to value 0"] +impl crate::Resettable for COUNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/tcc0/count_dith4_mode.rs b/pac/atsamc21n/src/tcc0/count_dith4_mode.rs new file mode 100644 index 000000000000..fc058ae5efd5 --- /dev/null +++ b/pac/atsamc21n/src/tcc0/count_dith4_mode.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT_DITH4_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT_DITH4_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x000f_ffff << 4)) | ((value as u32 & 0x000f_ffff) << 4); + self.w + } +} +impl R { + #[doc = "Bits 4:23 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 4) & 0x000f_ffff) as u32) + } +} +impl W { + #[doc = "Bits 4:23 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Count\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count_dith4_mode](index.html) module"] +pub struct COUNT_DITH4_MODE_SPEC; +impl crate::RegisterSpec for COUNT_DITH4_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [count_dith4_mode::R](R) reader structure"] +impl crate::Readable for COUNT_DITH4_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count_dith4_mode::W](W) writer structure"] +impl crate::Writable for COUNT_DITH4_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT_DITH4_MODE to value 0"] +impl crate::Resettable for COUNT_DITH4_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/tcc0/count_dith5_mode.rs b/pac/atsamc21n/src/tcc0/count_dith5_mode.rs new file mode 100644 index 000000000000..e66e20310726 --- /dev/null +++ b/pac/atsamc21n/src/tcc0/count_dith5_mode.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT_DITH5_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT_DITH5_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0007_ffff << 5)) | ((value as u32 & 0x0007_ffff) << 5); + self.w + } +} +impl R { + #[doc = "Bits 5:23 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 5) & 0x0007_ffff) as u32) + } +} +impl W { + #[doc = "Bits 5:23 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Count\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count_dith5_mode](index.html) module"] +pub struct COUNT_DITH5_MODE_SPEC; +impl crate::RegisterSpec for COUNT_DITH5_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [count_dith5_mode::R](R) reader structure"] +impl crate::Readable for COUNT_DITH5_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count_dith5_mode::W](W) writer structure"] +impl crate::Writable for COUNT_DITH5_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT_DITH5_MODE to value 0"] +impl crate::Resettable for COUNT_DITH5_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/tcc0/count_dith6_mode.rs b/pac/atsamc21n/src/tcc0/count_dith6_mode.rs new file mode 100644 index 000000000000..5410fc6c9459 --- /dev/null +++ b/pac/atsamc21n/src/tcc0/count_dith6_mode.rs @@ -0,0 +1,103 @@ +#[doc = "Register `COUNT_DITH6_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT_DITH6_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - Counter Value"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0003_ffff << 6)) | ((value as u32 & 0x0003_ffff) << 6); + self.w + } +} +impl R { + #[doc = "Bits 6:23 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 6) & 0x0003_ffff) as u32) + } +} +impl W { + #[doc = "Bits 6:23 - Counter Value"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Count\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count_dith6_mode](index.html) module"] +pub struct COUNT_DITH6_MODE_SPEC; +impl crate::RegisterSpec for COUNT_DITH6_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [count_dith6_mode::R](R) reader structure"] +impl crate::Readable for COUNT_DITH6_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count_dith6_mode::W](W) writer structure"] +impl crate::Writable for COUNT_DITH6_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets COUNT_DITH6_MODE to value 0"] +impl crate::Resettable for COUNT_DITH6_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/tcc0/ctrla.rs b/pac/atsamc21n/src/tcc0/ctrla.rs new file mode 100644 index 000000000000..b717d1ac6ae0 --- /dev/null +++ b/pac/atsamc21n/src/tcc0/ctrla.rs @@ -0,0 +1,911 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Enhanced Resolution\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum RESOLUTION_A { + #[doc = "0: Dithering is disabled"] + NONE = 0, + #[doc = "1: Dithering is done every 16 PWM frames"] + DITH4 = 1, + #[doc = "2: Dithering is done every 32 PWM frames"] + DITH5 = 2, + #[doc = "3: Dithering is done every 64 PWM frames"] + DITH6 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RESOLUTION_A) -> Self { + variant as _ + } +} +#[doc = "Field `RESOLUTION` reader - Enhanced Resolution"] +pub struct RESOLUTION_R(crate::FieldReader); +impl RESOLUTION_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RESOLUTION_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RESOLUTION_A { + match self.bits { + 0 => RESOLUTION_A::NONE, + 1 => RESOLUTION_A::DITH4, + 2 => RESOLUTION_A::DITH5, + 3 => RESOLUTION_A::DITH6, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == RESOLUTION_A::NONE + } + #[doc = "Checks if the value of the field is `DITH4`"] + #[inline(always)] + pub fn is_dith4(&self) -> bool { + **self == RESOLUTION_A::DITH4 + } + #[doc = "Checks if the value of the field is `DITH5`"] + #[inline(always)] + pub fn is_dith5(&self) -> bool { + **self == RESOLUTION_A::DITH5 + } + #[doc = "Checks if the value of the field is `DITH6`"] + #[inline(always)] + pub fn is_dith6(&self) -> bool { + **self == RESOLUTION_A::DITH6 + } +} +impl core::ops::Deref for RESOLUTION_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESOLUTION` writer - Enhanced Resolution"] +pub struct RESOLUTION_W<'a> { + w: &'a mut W, +} +impl<'a> RESOLUTION_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RESOLUTION_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Dithering is disabled"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(RESOLUTION_A::NONE) + } + #[doc = "Dithering is done every 16 PWM frames"] + #[inline(always)] + pub fn dith4(self) -> &'a mut W { + self.variant(RESOLUTION_A::DITH4) + } + #[doc = "Dithering is done every 32 PWM frames"] + #[inline(always)] + pub fn dith5(self) -> &'a mut W { + self.variant(RESOLUTION_A::DITH5) + } + #[doc = "Dithering is done every 64 PWM frames"] + #[inline(always)] + pub fn dith6(self) -> &'a mut W { + self.variant(RESOLUTION_A::DITH6) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 5)) | ((value as u32 & 0x03) << 5); + self.w + } +} +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCALER_A { + #[doc = "0: No division"] + DIV1 = 0, + #[doc = "1: Divide by 2"] + DIV2 = 1, + #[doc = "2: Divide by 4"] + DIV4 = 2, + #[doc = "3: Divide by 8"] + DIV8 = 3, + #[doc = "4: Divide by 16"] + DIV16 = 4, + #[doc = "5: Divide by 64"] + DIV64 = 5, + #[doc = "6: Divide by 256"] + DIV256 = 6, + #[doc = "7: Divide by 1024"] + DIV1024 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCALER` reader - Prescaler"] +pub struct PRESCALER_R(crate::FieldReader); +impl PRESCALER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCALER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PRESCALER_A { + match self.bits { + 0 => PRESCALER_A::DIV1, + 1 => PRESCALER_A::DIV2, + 2 => PRESCALER_A::DIV4, + 3 => PRESCALER_A::DIV8, + 4 => PRESCALER_A::DIV16, + 5 => PRESCALER_A::DIV64, + 6 => PRESCALER_A::DIV256, + 7 => PRESCALER_A::DIV1024, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == PRESCALER_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESCALER_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESCALER_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == PRESCALER_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == PRESCALER_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == PRESCALER_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + **self == PRESCALER_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + **self == PRESCALER_A::DIV1024 + } +} +impl core::ops::Deref for PRESCALER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler"] +pub struct PRESCALER_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCALER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCALER_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "No division"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1) + } + #[doc = "Divide by 2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV2) + } + #[doc = "Divide by 4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV4) + } + #[doc = "Divide by 8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV8) + } + #[doc = "Divide by 16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV16) + } + #[doc = "Divide by 64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV64) + } + #[doc = "Divide by 256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV256) + } + #[doc = "Divide by 1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PRESCALER_A::DIV1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Prescaler and Counter Synchronization Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESCSYNC_A { + #[doc = "0: Reload or reset counter on next GCLK"] + GCLK = 0, + #[doc = "1: Reload or reset counter on next prescaler clock"] + PRESC = 1, + #[doc = "2: Reload or reset counter on next GCLK and reset prescaler counter"] + RESYNC = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCSYNC_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESCSYNC` reader - Prescaler and Counter Synchronization Selection"] +pub struct PRESCSYNC_R(crate::FieldReader); +impl PRESCSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRESCSYNC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCSYNC_A::GCLK), + 1 => Some(PRESCSYNC_A::PRESC), + 2 => Some(PRESCSYNC_A::RESYNC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `GCLK`"] + #[inline(always)] + pub fn is_gclk(&self) -> bool { + **self == PRESCSYNC_A::GCLK + } + #[doc = "Checks if the value of the field is `PRESC`"] + #[inline(always)] + pub fn is_presc(&self) -> bool { + **self == PRESCSYNC_A::PRESC + } + #[doc = "Checks if the value of the field is `RESYNC`"] + #[inline(always)] + pub fn is_resync(&self) -> bool { + **self == PRESCSYNC_A::RESYNC + } +} +impl core::ops::Deref for PRESCSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESCSYNC` writer - Prescaler and Counter Synchronization Selection"] +pub struct PRESCSYNC_W<'a> { + w: &'a mut W, +} +impl<'a> PRESCSYNC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESCSYNC_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Reload or reset counter on next GCLK"] + #[inline(always)] + pub fn gclk(self) -> &'a mut W { + self.variant(PRESCSYNC_A::GCLK) + } + #[doc = "Reload or reset counter on next prescaler clock"] + #[inline(always)] + pub fn presc(self) -> &'a mut W { + self.variant(PRESCSYNC_A::PRESC) + } + #[doc = "Reload or reset counter on next GCLK and reset prescaler counter"] + #[inline(always)] + pub fn resync(self) -> &'a mut W { + self.variant(PRESCSYNC_A::RESYNC) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 12)) | ((value as u32 & 0x03) << 12); + self.w + } +} +#[doc = "Field `ALOCK` reader - Auto Lock"] +pub struct ALOCK_R(crate::FieldReader); +impl ALOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALOCK` writer - Auto Lock"] +pub struct ALOCK_W<'a> { + w: &'a mut W, +} +impl<'a> ALOCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `MSYNC` reader - Master Synchronization (only for TCC Slave Instance)"] +pub struct MSYNC_R(crate::FieldReader); +impl MSYNC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MSYNC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MSYNC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MSYNC` writer - Master Synchronization (only for TCC Slave Instance)"] +pub struct MSYNC_W<'a> { + w: &'a mut W, +} +impl<'a> MSYNC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `DMAOS` reader - DMA One-shot Trigger Mode"] +pub struct DMAOS_R(crate::FieldReader); +impl DMAOS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DMAOS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DMAOS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DMAOS` writer - DMA One-shot Trigger Mode"] +pub struct DMAOS_W<'a> { + w: &'a mut W, +} +impl<'a> DMAOS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `CPTEN0` reader - Capture Channel 0 Enable"] +pub struct CPTEN0_R(crate::FieldReader); +impl CPTEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPTEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CPTEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPTEN0` writer - Capture Channel 0 Enable"] +pub struct CPTEN0_W<'a> { + w: &'a mut W, +} +impl<'a> CPTEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `CPTEN1` reader - Capture Channel 1 Enable"] +pub struct CPTEN1_R(crate::FieldReader); +impl CPTEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPTEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CPTEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPTEN1` writer - Capture Channel 1 Enable"] +pub struct CPTEN1_W<'a> { + w: &'a mut W, +} +impl<'a> CPTEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `CPTEN2` reader - Capture Channel 2 Enable"] +pub struct CPTEN2_R(crate::FieldReader); +impl CPTEN2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPTEN2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CPTEN2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPTEN2` writer - Capture Channel 2 Enable"] +pub struct CPTEN2_W<'a> { + w: &'a mut W, +} +impl<'a> CPTEN2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `CPTEN3` reader - Capture Channel 3 Enable"] +pub struct CPTEN3_R(crate::FieldReader); +impl CPTEN3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CPTEN3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CPTEN3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPTEN3` writer - Capture Channel 3 Enable"] +pub struct CPTEN3_W<'a> { + w: &'a mut W, +} +impl<'a> CPTEN3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 5:6 - Enhanced Resolution"] + #[inline(always)] + pub fn resolution(&self) -> RESOLUTION_R { + RESOLUTION_R::new(((self.bits >> 5) & 0x03) as u8) + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 11 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bits 12:13 - Prescaler and Counter Synchronization Selection"] + #[inline(always)] + pub fn prescsync(&self) -> PRESCSYNC_R { + PRESCSYNC_R::new(((self.bits >> 12) & 0x03) as u8) + } + #[doc = "Bit 14 - Auto Lock"] + #[inline(always)] + pub fn alock(&self) -> ALOCK_R { + ALOCK_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Master Synchronization (only for TCC Slave Instance)"] + #[inline(always)] + pub fn msync(&self) -> MSYNC_R { + MSYNC_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 23 - DMA One-shot Trigger Mode"] + #[inline(always)] + pub fn dmaos(&self) -> DMAOS_R { + DMAOS_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn cpten0(&self) -> CPTEN0_R { + CPTEN0_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn cpten1(&self) -> CPTEN1_R { + CPTEN1_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Capture Channel 2 Enable"] + #[inline(always)] + pub fn cpten2(&self) -> CPTEN2_R { + CPTEN2_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Capture Channel 3 Enable"] + #[inline(always)] + pub fn cpten3(&self) -> CPTEN3_R { + CPTEN3_R::new(((self.bits >> 27) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 5:6 - Enhanced Resolution"] + #[inline(always)] + pub fn resolution(&mut self) -> RESOLUTION_W { + RESOLUTION_W { w: self } + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&mut self) -> PRESCALER_W { + PRESCALER_W { w: self } + } + #[doc = "Bit 11 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bits 12:13 - Prescaler and Counter Synchronization Selection"] + #[inline(always)] + pub fn prescsync(&mut self) -> PRESCSYNC_W { + PRESCSYNC_W { w: self } + } + #[doc = "Bit 14 - Auto Lock"] + #[inline(always)] + pub fn alock(&mut self) -> ALOCK_W { + ALOCK_W { w: self } + } + #[doc = "Bit 15 - Master Synchronization (only for TCC Slave Instance)"] + #[inline(always)] + pub fn msync(&mut self) -> MSYNC_W { + MSYNC_W { w: self } + } + #[doc = "Bit 23 - DMA One-shot Trigger Mode"] + #[inline(always)] + pub fn dmaos(&mut self) -> DMAOS_W { + DMAOS_W { w: self } + } + #[doc = "Bit 24 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn cpten0(&mut self) -> CPTEN0_W { + CPTEN0_W { w: self } + } + #[doc = "Bit 25 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn cpten1(&mut self) -> CPTEN1_W { + CPTEN1_W { w: self } + } + #[doc = "Bit 26 - Capture Channel 2 Enable"] + #[inline(always)] + pub fn cpten2(&mut self) -> CPTEN2_W { + CPTEN2_W { w: self } + } + #[doc = "Bit 27 - Capture Channel 3 Enable"] + #[inline(always)] + pub fn cpten3(&mut self) -> CPTEN3_W { + CPTEN3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/tcc0/ctrlbclr.rs b/pac/atsamc21n/src/tcc0/ctrlbclr.rs new file mode 100644 index 000000000000..f96ce81ffde3 --- /dev/null +++ b/pac/atsamc21n/src/tcc0/ctrlbclr.rs @@ -0,0 +1,457 @@ +#[doc = "Register `CTRLBCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Counter Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `LUPD` reader - Lock Update"] +pub struct LUPD_R(crate::FieldReader); +impl LUPD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LUPD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LUPD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LUPD` writer - Lock Update"] +pub struct LUPD_W<'a> { + w: &'a mut W, +} +impl<'a> LUPD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ONESHOT` reader - One-Shot"] +pub struct ONESHOT_R(crate::FieldReader); +impl ONESHOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONESHOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONESHOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONESHOT` writer - One-Shot"] +pub struct ONESHOT_W<'a> { + w: &'a mut W, +} +impl<'a> ONESHOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Ramp Index Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum IDXCMD_A { + #[doc = "0: Command disabled: Index toggles between cycles A and B"] + DISABLE = 0, + #[doc = "1: Set index: cycle B will be forced in the next cycle"] + SET = 1, + #[doc = "2: Clear index: cycle A will be forced in the next cycle"] + CLEAR = 2, + #[doc = "3: Hold index: the next cycle will be the same as the current cycle"] + HOLD = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: IDXCMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `IDXCMD` reader - Ramp Index Command"] +pub struct IDXCMD_R(crate::FieldReader); +impl IDXCMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + IDXCMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> IDXCMD_A { + match self.bits { + 0 => IDXCMD_A::DISABLE, + 1 => IDXCMD_A::SET, + 2 => IDXCMD_A::CLEAR, + 3 => IDXCMD_A::HOLD, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == IDXCMD_A::DISABLE + } + #[doc = "Checks if the value of the field is `SET`"] + #[inline(always)] + pub fn is_set(&self) -> bool { + **self == IDXCMD_A::SET + } + #[doc = "Checks if the value of the field is `CLEAR`"] + #[inline(always)] + pub fn is_clear(&self) -> bool { + **self == IDXCMD_A::CLEAR + } + #[doc = "Checks if the value of the field is `HOLD`"] + #[inline(always)] + pub fn is_hold(&self) -> bool { + **self == IDXCMD_A::HOLD + } +} +impl core::ops::Deref for IDXCMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IDXCMD` writer - Ramp Index Command"] +pub struct IDXCMD_W<'a> { + w: &'a mut W, +} +impl<'a> IDXCMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: IDXCMD_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Command disabled: Index toggles between cycles A and B"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(IDXCMD_A::DISABLE) + } + #[doc = "Set index: cycle B will be forced in the next cycle"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(IDXCMD_A::SET) + } + #[doc = "Clear index: cycle A will be forced in the next cycle"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(IDXCMD_A::CLEAR) + } + #[doc = "Hold index: the next cycle will be the same as the current cycle"] + #[inline(always)] + pub fn hold(self) -> &'a mut W { + self.variant(IDXCMD_A::HOLD) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 3)) | ((value as u8 & 0x03) << 3); + self.w + } +} +#[doc = "TCC Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Clear start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force stop"] + STOP = 2, + #[doc = "3: Force update or double buffered registers"] + UPDATE = 3, + #[doc = "4: Force COUNT read synchronization"] + READSYNC = 4, + #[doc = "5: One-shot DMA trigger"] + DMAOS = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - TCC Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NONE), + 1 => Some(CMD_A::RETRIGGER), + 2 => Some(CMD_A::STOP), + 3 => Some(CMD_A::UPDATE), + 4 => Some(CMD_A::READSYNC), + 5 => Some(CMD_A::DMAOS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == CMD_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == CMD_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == CMD_A::STOP + } + #[doc = "Checks if the value of the field is `UPDATE`"] + #[inline(always)] + pub fn is_update(&self) -> bool { + **self == CMD_A::UPDATE + } + #[doc = "Checks if the value of the field is `READSYNC`"] + #[inline(always)] + pub fn is_readsync(&self) -> bool { + **self == CMD_A::READSYNC + } + #[doc = "Checks if the value of the field is `DMAOS`"] + #[inline(always)] + pub fn is_dmaos(&self) -> bool { + **self == CMD_A::DMAOS + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - TCC Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMD_A::NONE) + } + #[doc = "Clear start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMD_A::RETRIGGER) + } + #[doc = "Force stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMD_A::STOP) + } + #[doc = "Force update or double buffered registers"] + #[inline(always)] + pub fn update(self) -> &'a mut W { + self.variant(CMD_A::UPDATE) + } + #[doc = "Force COUNT read synchronization"] + #[inline(always)] + pub fn readsync(self) -> &'a mut W { + self.variant(CMD_A::READSYNC) + } + #[doc = "One-shot DMA trigger"] + #[inline(always)] + pub fn dmaos(self) -> &'a mut W { + self.variant(CMD_A::DMAOS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 5)) | ((value as u8 & 0x07) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&self) -> LUPD_R { + LUPD_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - One-Shot"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 3:4 - Ramp Index Command"] + #[inline(always)] + pub fn idxcmd(&self) -> IDXCMD_R { + IDXCMD_R::new(((self.bits >> 3) & 0x03) as u8) + } + #[doc = "Bits 5:7 - TCC Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 5) & 0x07) as u8) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&mut self) -> LUPD_W { + LUPD_W { w: self } + } + #[doc = "Bit 2 - One-Shot"] + #[inline(always)] + pub fn oneshot(&mut self) -> ONESHOT_W { + ONESHOT_W { w: self } + } + #[doc = "Bits 3:4 - Ramp Index Command"] + #[inline(always)] + pub fn idxcmd(&mut self) -> IDXCMD_W { + IDXCMD_W { w: self } + } + #[doc = "Bits 5:7 - TCC Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbclr](index.html) module"] +pub struct CTRLBCLR_SPEC; +impl crate::RegisterSpec for CTRLBCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbclr::R](R) reader structure"] +impl crate::Readable for CTRLBCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbclr::W](W) writer structure"] +impl crate::Writable for CTRLBCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLBCLR to value 0"] +impl crate::Resettable for CTRLBCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/tcc0/ctrlbset.rs b/pac/atsamc21n/src/tcc0/ctrlbset.rs new file mode 100644 index 000000000000..7002dd71efe7 --- /dev/null +++ b/pac/atsamc21n/src/tcc0/ctrlbset.rs @@ -0,0 +1,457 @@ +#[doc = "Register `CTRLBSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub struct DIR_R(crate::FieldReader); +impl DIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIR` writer - Counter Direction"] +pub struct DIR_W<'a> { + w: &'a mut W, +} +impl<'a> DIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `LUPD` reader - Lock Update"] +pub struct LUPD_R(crate::FieldReader); +impl LUPD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LUPD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LUPD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LUPD` writer - Lock Update"] +pub struct LUPD_W<'a> { + w: &'a mut W, +} +impl<'a> LUPD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ONESHOT` reader - One-Shot"] +pub struct ONESHOT_R(crate::FieldReader); +impl ONESHOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ONESHOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONESHOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONESHOT` writer - One-Shot"] +pub struct ONESHOT_W<'a> { + w: &'a mut W, +} +impl<'a> ONESHOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Ramp Index Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum IDXCMD_A { + #[doc = "0: Command disabled: Index toggles between cycles A and B"] + DISABLE = 0, + #[doc = "1: Set index: cycle B will be forced in the next cycle"] + SET = 1, + #[doc = "2: Clear index: cycle A will be forced in the next cycle"] + CLEAR = 2, + #[doc = "3: Hold index: the next cycle will be the same as the current cycle"] + HOLD = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: IDXCMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `IDXCMD` reader - Ramp Index Command"] +pub struct IDXCMD_R(crate::FieldReader); +impl IDXCMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + IDXCMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> IDXCMD_A { + match self.bits { + 0 => IDXCMD_A::DISABLE, + 1 => IDXCMD_A::SET, + 2 => IDXCMD_A::CLEAR, + 3 => IDXCMD_A::HOLD, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == IDXCMD_A::DISABLE + } + #[doc = "Checks if the value of the field is `SET`"] + #[inline(always)] + pub fn is_set(&self) -> bool { + **self == IDXCMD_A::SET + } + #[doc = "Checks if the value of the field is `CLEAR`"] + #[inline(always)] + pub fn is_clear(&self) -> bool { + **self == IDXCMD_A::CLEAR + } + #[doc = "Checks if the value of the field is `HOLD`"] + #[inline(always)] + pub fn is_hold(&self) -> bool { + **self == IDXCMD_A::HOLD + } +} +impl core::ops::Deref for IDXCMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IDXCMD` writer - Ramp Index Command"] +pub struct IDXCMD_W<'a> { + w: &'a mut W, +} +impl<'a> IDXCMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: IDXCMD_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Command disabled: Index toggles between cycles A and B"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(IDXCMD_A::DISABLE) + } + #[doc = "Set index: cycle B will be forced in the next cycle"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(IDXCMD_A::SET) + } + #[doc = "Clear index: cycle A will be forced in the next cycle"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(IDXCMD_A::CLEAR) + } + #[doc = "Hold index: the next cycle will be the same as the current cycle"] + #[inline(always)] + pub fn hold(self) -> &'a mut W { + self.variant(IDXCMD_A::HOLD) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 3)) | ((value as u8 & 0x03) << 3); + self.w + } +} +#[doc = "TCC Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Clear start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force stop"] + STOP = 2, + #[doc = "3: Force update or double buffered registers"] + UPDATE = 3, + #[doc = "4: Force COUNT read synchronization"] + READSYNC = 4, + #[doc = "5: One-shot DMA trigger"] + DMAOS = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - TCC Command"] +pub struct CMD_R(crate::FieldReader); +impl CMD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMD_A::NONE), + 1 => Some(CMD_A::RETRIGGER), + 2 => Some(CMD_A::STOP), + 3 => Some(CMD_A::UPDATE), + 4 => Some(CMD_A::READSYNC), + 5 => Some(CMD_A::DMAOS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + **self == CMD_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == CMD_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == CMD_A::STOP + } + #[doc = "Checks if the value of the field is `UPDATE`"] + #[inline(always)] + pub fn is_update(&self) -> bool { + **self == CMD_A::UPDATE + } + #[doc = "Checks if the value of the field is `READSYNC`"] + #[inline(always)] + pub fn is_readsync(&self) -> bool { + **self == CMD_A::READSYNC + } + #[doc = "Checks if the value of the field is `DMAOS`"] + #[inline(always)] + pub fn is_dmaos(&self) -> bool { + **self == CMD_A::DMAOS + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - TCC Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMD_A::NONE) + } + #[doc = "Clear start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMD_A::RETRIGGER) + } + #[doc = "Force stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMD_A::STOP) + } + #[doc = "Force update or double buffered registers"] + #[inline(always)] + pub fn update(self) -> &'a mut W { + self.variant(CMD_A::UPDATE) + } + #[doc = "Force COUNT read synchronization"] + #[inline(always)] + pub fn readsync(self) -> &'a mut W { + self.variant(CMD_A::READSYNC) + } + #[doc = "One-shot DMA trigger"] + #[inline(always)] + pub fn dmaos(self) -> &'a mut W { + self.variant(CMD_A::DMAOS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 5)) | ((value as u8 & 0x07) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&self) -> LUPD_R { + LUPD_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - One-Shot"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 3:4 - Ramp Index Command"] + #[inline(always)] + pub fn idxcmd(&self) -> IDXCMD_R { + IDXCMD_R::new(((self.bits >> 3) & 0x03) as u8) + } + #[doc = "Bits 5:7 - TCC Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 5) & 0x07) as u8) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&mut self) -> DIR_W { + DIR_W { w: self } + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&mut self) -> LUPD_W { + LUPD_W { w: self } + } + #[doc = "Bit 2 - One-Shot"] + #[inline(always)] + pub fn oneshot(&mut self) -> ONESHOT_W { + ONESHOT_W { w: self } + } + #[doc = "Bits 3:4 - Ramp Index Command"] + #[inline(always)] + pub fn idxcmd(&mut self) -> IDXCMD_W { + IDXCMD_W { w: self } + } + #[doc = "Bits 5:7 - TCC Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbset](index.html) module"] +pub struct CTRLBSET_SPEC; +impl crate::RegisterSpec for CTRLBSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbset::R](R) reader structure"] +impl crate::Readable for CTRLBSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbset::W](W) writer structure"] +impl crate::Writable for CTRLBSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLBSET to value 0"] +impl crate::Resettable for CTRLBSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/tcc0/dbgctrl.rs b/pac/atsamc21n/src/tcc0/dbgctrl.rs new file mode 100644 index 000000000000..313ebe3f5c18 --- /dev/null +++ b/pac/atsamc21n/src/tcc0/dbgctrl.rs @@ -0,0 +1,160 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Debug Running Mode"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Debug Running Mode"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `FDDBD` reader - Fault Detection on Debug Break Detection"] +pub struct FDDBD_R(crate::FieldReader); +impl FDDBD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FDDBD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FDDBD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FDDBD` writer - Fault Detection on Debug Break Detection"] +pub struct FDDBD_W<'a> { + w: &'a mut W, +} +impl<'a> FDDBD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Running Mode"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 2 - Fault Detection on Debug Break Detection"] + #[inline(always)] + pub fn fddbd(&self) -> FDDBD_R { + FDDBD_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Running Mode"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Bit 2 - Fault Detection on Debug Break Detection"] + #[inline(always)] + pub fn fddbd(&mut self) -> FDDBD_W { + FDDBD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/tcc0/drvctrl.rs b/pac/atsamc21n/src/tcc0/drvctrl.rs new file mode 100644 index 000000000000..316041e1e3be --- /dev/null +++ b/pac/atsamc21n/src/tcc0/drvctrl.rs @@ -0,0 +1,1268 @@ +#[doc = "Register `DRVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DRVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `NRE0` reader - Non-Recoverable State 0 Output Enable"] +pub struct NRE0_R(crate::FieldReader); +impl NRE0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRE0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRE0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRE0` writer - Non-Recoverable State 0 Output Enable"] +pub struct NRE0_W<'a> { + w: &'a mut W, +} +impl<'a> NRE0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `NRE1` reader - Non-Recoverable State 1 Output Enable"] +pub struct NRE1_R(crate::FieldReader); +impl NRE1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRE1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRE1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRE1` writer - Non-Recoverable State 1 Output Enable"] +pub struct NRE1_W<'a> { + w: &'a mut W, +} +impl<'a> NRE1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `NRE2` reader - Non-Recoverable State 2 Output Enable"] +pub struct NRE2_R(crate::FieldReader); +impl NRE2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRE2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRE2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRE2` writer - Non-Recoverable State 2 Output Enable"] +pub struct NRE2_W<'a> { + w: &'a mut W, +} +impl<'a> NRE2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `NRE3` reader - Non-Recoverable State 3 Output Enable"] +pub struct NRE3_R(crate::FieldReader); +impl NRE3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRE3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRE3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRE3` writer - Non-Recoverable State 3 Output Enable"] +pub struct NRE3_W<'a> { + w: &'a mut W, +} +impl<'a> NRE3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `NRE4` reader - Non-Recoverable State 4 Output Enable"] +pub struct NRE4_R(crate::FieldReader); +impl NRE4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRE4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRE4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRE4` writer - Non-Recoverable State 4 Output Enable"] +pub struct NRE4_W<'a> { + w: &'a mut W, +} +impl<'a> NRE4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `NRE5` reader - Non-Recoverable State 5 Output Enable"] +pub struct NRE5_R(crate::FieldReader); +impl NRE5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRE5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRE5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRE5` writer - Non-Recoverable State 5 Output Enable"] +pub struct NRE5_W<'a> { + w: &'a mut W, +} +impl<'a> NRE5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `NRE6` reader - Non-Recoverable State 6 Output Enable"] +pub struct NRE6_R(crate::FieldReader); +impl NRE6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRE6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRE6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRE6` writer - Non-Recoverable State 6 Output Enable"] +pub struct NRE6_W<'a> { + w: &'a mut W, +} +impl<'a> NRE6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `NRE7` reader - Non-Recoverable State 7 Output Enable"] +pub struct NRE7_R(crate::FieldReader); +impl NRE7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRE7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRE7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRE7` writer - Non-Recoverable State 7 Output Enable"] +pub struct NRE7_W<'a> { + w: &'a mut W, +} +impl<'a> NRE7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `NRV0` reader - Non-Recoverable State 0 Output Value"] +pub struct NRV0_R(crate::FieldReader); +impl NRV0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRV0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRV0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRV0` writer - Non-Recoverable State 0 Output Value"] +pub struct NRV0_W<'a> { + w: &'a mut W, +} +impl<'a> NRV0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `NRV1` reader - Non-Recoverable State 1 Output Value"] +pub struct NRV1_R(crate::FieldReader); +impl NRV1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRV1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRV1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRV1` writer - Non-Recoverable State 1 Output Value"] +pub struct NRV1_W<'a> { + w: &'a mut W, +} +impl<'a> NRV1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `NRV2` reader - Non-Recoverable State 2 Output Value"] +pub struct NRV2_R(crate::FieldReader); +impl NRV2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRV2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRV2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRV2` writer - Non-Recoverable State 2 Output Value"] +pub struct NRV2_W<'a> { + w: &'a mut W, +} +impl<'a> NRV2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `NRV3` reader - Non-Recoverable State 3 Output Value"] +pub struct NRV3_R(crate::FieldReader); +impl NRV3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRV3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRV3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRV3` writer - Non-Recoverable State 3 Output Value"] +pub struct NRV3_W<'a> { + w: &'a mut W, +} +impl<'a> NRV3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `NRV4` reader - Non-Recoverable State 4 Output Value"] +pub struct NRV4_R(crate::FieldReader); +impl NRV4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRV4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRV4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRV4` writer - Non-Recoverable State 4 Output Value"] +pub struct NRV4_W<'a> { + w: &'a mut W, +} +impl<'a> NRV4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `NRV5` reader - Non-Recoverable State 5 Output Value"] +pub struct NRV5_R(crate::FieldReader); +impl NRV5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRV5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRV5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRV5` writer - Non-Recoverable State 5 Output Value"] +pub struct NRV5_W<'a> { + w: &'a mut W, +} +impl<'a> NRV5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `NRV6` reader - Non-Recoverable State 6 Output Value"] +pub struct NRV6_R(crate::FieldReader); +impl NRV6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRV6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRV6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRV6` writer - Non-Recoverable State 6 Output Value"] +pub struct NRV6_W<'a> { + w: &'a mut W, +} +impl<'a> NRV6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `NRV7` reader - Non-Recoverable State 7 Output Value"] +pub struct NRV7_R(crate::FieldReader); +impl NRV7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NRV7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRV7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRV7` writer - Non-Recoverable State 7 Output Value"] +pub struct NRV7_W<'a> { + w: &'a mut W, +} +impl<'a> NRV7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `INVEN0` reader - Output Waveform 0 Inversion"] +pub struct INVEN0_R(crate::FieldReader); +impl INVEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN0` writer - Output Waveform 0 Inversion"] +pub struct INVEN0_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `INVEN1` reader - Output Waveform 1 Inversion"] +pub struct INVEN1_R(crate::FieldReader); +impl INVEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN1` writer - Output Waveform 1 Inversion"] +pub struct INVEN1_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `INVEN2` reader - Output Waveform 2 Inversion"] +pub struct INVEN2_R(crate::FieldReader); +impl INVEN2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN2` writer - Output Waveform 2 Inversion"] +pub struct INVEN2_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `INVEN3` reader - Output Waveform 3 Inversion"] +pub struct INVEN3_R(crate::FieldReader); +impl INVEN3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN3` writer - Output Waveform 3 Inversion"] +pub struct INVEN3_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `INVEN4` reader - Output Waveform 4 Inversion"] +pub struct INVEN4_R(crate::FieldReader); +impl INVEN4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN4` writer - Output Waveform 4 Inversion"] +pub struct INVEN4_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `INVEN5` reader - Output Waveform 5 Inversion"] +pub struct INVEN5_R(crate::FieldReader); +impl INVEN5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN5` writer - Output Waveform 5 Inversion"] +pub struct INVEN5_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `INVEN6` reader - Output Waveform 6 Inversion"] +pub struct INVEN6_R(crate::FieldReader); +impl INVEN6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN6` writer - Output Waveform 6 Inversion"] +pub struct INVEN6_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `INVEN7` reader - Output Waveform 7 Inversion"] +pub struct INVEN7_R(crate::FieldReader); +impl INVEN7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVEN7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVEN7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVEN7` writer - Output Waveform 7 Inversion"] +pub struct INVEN7_W<'a> { + w: &'a mut W, +} +impl<'a> INVEN7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `FILTERVAL0` reader - Non-Recoverable Fault Input 0 Filter Value"] +pub struct FILTERVAL0_R(crate::FieldReader); +impl FILTERVAL0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FILTERVAL0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTERVAL0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTERVAL0` writer - Non-Recoverable Fault Input 0 Filter Value"] +pub struct FILTERVAL0_W<'a> { + w: &'a mut W, +} +impl<'a> FILTERVAL0_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Field `FILTERVAL1` reader - Non-Recoverable Fault Input 1 Filter Value"] +pub struct FILTERVAL1_R(crate::FieldReader); +impl FILTERVAL1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FILTERVAL1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTERVAL1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTERVAL1` writer - Non-Recoverable Fault Input 1 Filter Value"] +pub struct FILTERVAL1_W<'a> { + w: &'a mut W, +} +impl<'a> FILTERVAL1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 28)) | ((value as u32 & 0x0f) << 28); + self.w + } +} +impl R { + #[doc = "Bit 0 - Non-Recoverable State 0 Output Enable"] + #[inline(always)] + pub fn nre0(&self) -> NRE0_R { + NRE0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Non-Recoverable State 1 Output Enable"] + #[inline(always)] + pub fn nre1(&self) -> NRE1_R { + NRE1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Non-Recoverable State 2 Output Enable"] + #[inline(always)] + pub fn nre2(&self) -> NRE2_R { + NRE2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Non-Recoverable State 3 Output Enable"] + #[inline(always)] + pub fn nre3(&self) -> NRE3_R { + NRE3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Non-Recoverable State 4 Output Enable"] + #[inline(always)] + pub fn nre4(&self) -> NRE4_R { + NRE4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Non-Recoverable State 5 Output Enable"] + #[inline(always)] + pub fn nre5(&self) -> NRE5_R { + NRE5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Non-Recoverable State 6 Output Enable"] + #[inline(always)] + pub fn nre6(&self) -> NRE6_R { + NRE6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Non-Recoverable State 7 Output Enable"] + #[inline(always)] + pub fn nre7(&self) -> NRE7_R { + NRE7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Non-Recoverable State 0 Output Value"] + #[inline(always)] + pub fn nrv0(&self) -> NRV0_R { + NRV0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Non-Recoverable State 1 Output Value"] + #[inline(always)] + pub fn nrv1(&self) -> NRV1_R { + NRV1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Non-Recoverable State 2 Output Value"] + #[inline(always)] + pub fn nrv2(&self) -> NRV2_R { + NRV2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Non-Recoverable State 3 Output Value"] + #[inline(always)] + pub fn nrv3(&self) -> NRV3_R { + NRV3_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Non-Recoverable State 4 Output Value"] + #[inline(always)] + pub fn nrv4(&self) -> NRV4_R { + NRV4_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Non-Recoverable State 5 Output Value"] + #[inline(always)] + pub fn nrv5(&self) -> NRV5_R { + NRV5_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Non-Recoverable State 6 Output Value"] + #[inline(always)] + pub fn nrv6(&self) -> NRV6_R { + NRV6_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Non-Recoverable State 7 Output Value"] + #[inline(always)] + pub fn nrv7(&self) -> NRV7_R { + NRV7_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Output Waveform 0 Inversion"] + #[inline(always)] + pub fn inven0(&self) -> INVEN0_R { + INVEN0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Output Waveform 1 Inversion"] + #[inline(always)] + pub fn inven1(&self) -> INVEN1_R { + INVEN1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Output Waveform 2 Inversion"] + #[inline(always)] + pub fn inven2(&self) -> INVEN2_R { + INVEN2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Output Waveform 3 Inversion"] + #[inline(always)] + pub fn inven3(&self) -> INVEN3_R { + INVEN3_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Output Waveform 4 Inversion"] + #[inline(always)] + pub fn inven4(&self) -> INVEN4_R { + INVEN4_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Output Waveform 5 Inversion"] + #[inline(always)] + pub fn inven5(&self) -> INVEN5_R { + INVEN5_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Output Waveform 6 Inversion"] + #[inline(always)] + pub fn inven6(&self) -> INVEN6_R { + INVEN6_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Output Waveform 7 Inversion"] + #[inline(always)] + pub fn inven7(&self) -> INVEN7_R { + INVEN7_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bits 24:27 - Non-Recoverable Fault Input 0 Filter Value"] + #[inline(always)] + pub fn filterval0(&self) -> FILTERVAL0_R { + FILTERVAL0_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bits 28:31 - Non-Recoverable Fault Input 1 Filter Value"] + #[inline(always)] + pub fn filterval1(&self) -> FILTERVAL1_R { + FILTERVAL1_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bit 0 - Non-Recoverable State 0 Output Enable"] + #[inline(always)] + pub fn nre0(&mut self) -> NRE0_W { + NRE0_W { w: self } + } + #[doc = "Bit 1 - Non-Recoverable State 1 Output Enable"] + #[inline(always)] + pub fn nre1(&mut self) -> NRE1_W { + NRE1_W { w: self } + } + #[doc = "Bit 2 - Non-Recoverable State 2 Output Enable"] + #[inline(always)] + pub fn nre2(&mut self) -> NRE2_W { + NRE2_W { w: self } + } + #[doc = "Bit 3 - Non-Recoverable State 3 Output Enable"] + #[inline(always)] + pub fn nre3(&mut self) -> NRE3_W { + NRE3_W { w: self } + } + #[doc = "Bit 4 - Non-Recoverable State 4 Output Enable"] + #[inline(always)] + pub fn nre4(&mut self) -> NRE4_W { + NRE4_W { w: self } + } + #[doc = "Bit 5 - Non-Recoverable State 5 Output Enable"] + #[inline(always)] + pub fn nre5(&mut self) -> NRE5_W { + NRE5_W { w: self } + } + #[doc = "Bit 6 - Non-Recoverable State 6 Output Enable"] + #[inline(always)] + pub fn nre6(&mut self) -> NRE6_W { + NRE6_W { w: self } + } + #[doc = "Bit 7 - Non-Recoverable State 7 Output Enable"] + #[inline(always)] + pub fn nre7(&mut self) -> NRE7_W { + NRE7_W { w: self } + } + #[doc = "Bit 8 - Non-Recoverable State 0 Output Value"] + #[inline(always)] + pub fn nrv0(&mut self) -> NRV0_W { + NRV0_W { w: self } + } + #[doc = "Bit 9 - Non-Recoverable State 1 Output Value"] + #[inline(always)] + pub fn nrv1(&mut self) -> NRV1_W { + NRV1_W { w: self } + } + #[doc = "Bit 10 - Non-Recoverable State 2 Output Value"] + #[inline(always)] + pub fn nrv2(&mut self) -> NRV2_W { + NRV2_W { w: self } + } + #[doc = "Bit 11 - Non-Recoverable State 3 Output Value"] + #[inline(always)] + pub fn nrv3(&mut self) -> NRV3_W { + NRV3_W { w: self } + } + #[doc = "Bit 12 - Non-Recoverable State 4 Output Value"] + #[inline(always)] + pub fn nrv4(&mut self) -> NRV4_W { + NRV4_W { w: self } + } + #[doc = "Bit 13 - Non-Recoverable State 5 Output Value"] + #[inline(always)] + pub fn nrv5(&mut self) -> NRV5_W { + NRV5_W { w: self } + } + #[doc = "Bit 14 - Non-Recoverable State 6 Output Value"] + #[inline(always)] + pub fn nrv6(&mut self) -> NRV6_W { + NRV6_W { w: self } + } + #[doc = "Bit 15 - Non-Recoverable State 7 Output Value"] + #[inline(always)] + pub fn nrv7(&mut self) -> NRV7_W { + NRV7_W { w: self } + } + #[doc = "Bit 16 - Output Waveform 0 Inversion"] + #[inline(always)] + pub fn inven0(&mut self) -> INVEN0_W { + INVEN0_W { w: self } + } + #[doc = "Bit 17 - Output Waveform 1 Inversion"] + #[inline(always)] + pub fn inven1(&mut self) -> INVEN1_W { + INVEN1_W { w: self } + } + #[doc = "Bit 18 - Output Waveform 2 Inversion"] + #[inline(always)] + pub fn inven2(&mut self) -> INVEN2_W { + INVEN2_W { w: self } + } + #[doc = "Bit 19 - Output Waveform 3 Inversion"] + #[inline(always)] + pub fn inven3(&mut self) -> INVEN3_W { + INVEN3_W { w: self } + } + #[doc = "Bit 20 - Output Waveform 4 Inversion"] + #[inline(always)] + pub fn inven4(&mut self) -> INVEN4_W { + INVEN4_W { w: self } + } + #[doc = "Bit 21 - Output Waveform 5 Inversion"] + #[inline(always)] + pub fn inven5(&mut self) -> INVEN5_W { + INVEN5_W { w: self } + } + #[doc = "Bit 22 - Output Waveform 6 Inversion"] + #[inline(always)] + pub fn inven6(&mut self) -> INVEN6_W { + INVEN6_W { w: self } + } + #[doc = "Bit 23 - Output Waveform 7 Inversion"] + #[inline(always)] + pub fn inven7(&mut self) -> INVEN7_W { + INVEN7_W { w: self } + } + #[doc = "Bits 24:27 - Non-Recoverable Fault Input 0 Filter Value"] + #[inline(always)] + pub fn filterval0(&mut self) -> FILTERVAL0_W { + FILTERVAL0_W { w: self } + } + #[doc = "Bits 28:31 - Non-Recoverable Fault Input 1 Filter Value"] + #[inline(always)] + pub fn filterval1(&mut self) -> FILTERVAL1_W { + FILTERVAL1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Driver Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [drvctrl](index.html) module"] +pub struct DRVCTRL_SPEC; +impl crate::RegisterSpec for DRVCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [drvctrl::R](R) reader structure"] +impl crate::Readable for DRVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [drvctrl::W](W) writer structure"] +impl crate::Writable for DRVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DRVCTRL to value 0"] +impl crate::Resettable for DRVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/tcc0/evctrl.rs b/pac/atsamc21n/src/tcc0/evctrl.rs new file mode 100644 index 000000000000..334a53924d61 --- /dev/null +++ b/pac/atsamc21n/src/tcc0/evctrl.rs @@ -0,0 +1,1211 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Timer/counter Input Event0 Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EVACT0_A { + #[doc = "0: Event action disabled"] + OFF = 0, + #[doc = "1: Start, restart or re-trigger counter on event"] + RETRIGGER = 1, + #[doc = "2: Count on event"] + COUNTEV = 2, + #[doc = "3: Start counter on event"] + START = 3, + #[doc = "4: Increment counter on event"] + INC = 4, + #[doc = "5: Count on active state of asynchronous event"] + COUNT = 5, + #[doc = "6: Stamp capture"] + STAMP = 6, + #[doc = "7: Non-recoverable fault"] + FAULT = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EVACT0_A) -> Self { + variant as _ + } +} +#[doc = "Field `EVACT0` reader - Timer/counter Input Event0 Action"] +pub struct EVACT0_R(crate::FieldReader); +impl EVACT0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVACT0_A { + match self.bits { + 0 => EVACT0_A::OFF, + 1 => EVACT0_A::RETRIGGER, + 2 => EVACT0_A::COUNTEV, + 3 => EVACT0_A::START, + 4 => EVACT0_A::INC, + 5 => EVACT0_A::COUNT, + 6 => EVACT0_A::STAMP, + 7 => EVACT0_A::FAULT, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == EVACT0_A::OFF + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == EVACT0_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `COUNTEV`"] + #[inline(always)] + pub fn is_countev(&self) -> bool { + **self == EVACT0_A::COUNTEV + } + #[doc = "Checks if the value of the field is `START`"] + #[inline(always)] + pub fn is_start(&self) -> bool { + **self == EVACT0_A::START + } + #[doc = "Checks if the value of the field is `INC`"] + #[inline(always)] + pub fn is_inc(&self) -> bool { + **self == EVACT0_A::INC + } + #[doc = "Checks if the value of the field is `COUNT`"] + #[inline(always)] + pub fn is_count(&self) -> bool { + **self == EVACT0_A::COUNT + } + #[doc = "Checks if the value of the field is `STAMP`"] + #[inline(always)] + pub fn is_stamp(&self) -> bool { + **self == EVACT0_A::STAMP + } + #[doc = "Checks if the value of the field is `FAULT`"] + #[inline(always)] + pub fn is_fault(&self) -> bool { + **self == EVACT0_A::FAULT + } +} +impl core::ops::Deref for EVACT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT0` writer - Timer/counter Input Event0 Action"] +pub struct EVACT0_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT0_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EVACT0_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Event action disabled"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(EVACT0_A::OFF) + } + #[doc = "Start, restart or re-trigger counter on event"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(EVACT0_A::RETRIGGER) + } + #[doc = "Count on event"] + #[inline(always)] + pub fn countev(self) -> &'a mut W { + self.variant(EVACT0_A::COUNTEV) + } + #[doc = "Start counter on event"] + #[inline(always)] + pub fn start(self) -> &'a mut W { + self.variant(EVACT0_A::START) + } + #[doc = "Increment counter on event"] + #[inline(always)] + pub fn inc(self) -> &'a mut W { + self.variant(EVACT0_A::INC) + } + #[doc = "Count on active state of asynchronous event"] + #[inline(always)] + pub fn count(self) -> &'a mut W { + self.variant(EVACT0_A::COUNT) + } + #[doc = "Stamp capture"] + #[inline(always)] + pub fn stamp(self) -> &'a mut W { + self.variant(EVACT0_A::STAMP) + } + #[doc = "Non-recoverable fault"] + #[inline(always)] + pub fn fault(self) -> &'a mut W { + self.variant(EVACT0_A::FAULT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Timer/counter Input Event1 Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EVACT1_A { + #[doc = "0: Event action disabled"] + OFF = 0, + #[doc = "1: Re-trigger counter on event"] + RETRIGGER = 1, + #[doc = "2: Direction control"] + DIR = 2, + #[doc = "3: Stop counter on event"] + STOP = 3, + #[doc = "4: Decrement counter on event"] + DEC = 4, + #[doc = "5: Period capture value in CC0 register, pulse width capture value in CC1 register"] + PPW = 5, + #[doc = "6: Period capture value in CC1 register, pulse width capture value in CC0 register"] + PWP = 6, + #[doc = "7: Non-recoverable fault"] + FAULT = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EVACT1_A) -> Self { + variant as _ + } +} +#[doc = "Field `EVACT1` reader - Timer/counter Input Event1 Action"] +pub struct EVACT1_R(crate::FieldReader); +impl EVACT1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EVACT1_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVACT1_A { + match self.bits { + 0 => EVACT1_A::OFF, + 1 => EVACT1_A::RETRIGGER, + 2 => EVACT1_A::DIR, + 3 => EVACT1_A::STOP, + 4 => EVACT1_A::DEC, + 5 => EVACT1_A::PPW, + 6 => EVACT1_A::PWP, + 7 => EVACT1_A::FAULT, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + **self == EVACT1_A::OFF + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + **self == EVACT1_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `DIR`"] + #[inline(always)] + pub fn is_dir(&self) -> bool { + **self == EVACT1_A::DIR + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + **self == EVACT1_A::STOP + } + #[doc = "Checks if the value of the field is `DEC`"] + #[inline(always)] + pub fn is_dec(&self) -> bool { + **self == EVACT1_A::DEC + } + #[doc = "Checks if the value of the field is `PPW`"] + #[inline(always)] + pub fn is_ppw(&self) -> bool { + **self == EVACT1_A::PPW + } + #[doc = "Checks if the value of the field is `PWP`"] + #[inline(always)] + pub fn is_pwp(&self) -> bool { + **self == EVACT1_A::PWP + } + #[doc = "Checks if the value of the field is `FAULT`"] + #[inline(always)] + pub fn is_fault(&self) -> bool { + **self == EVACT1_A::FAULT + } +} +impl core::ops::Deref for EVACT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT1` writer - Timer/counter Input Event1 Action"] +pub struct EVACT1_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT1_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EVACT1_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Event action disabled"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(EVACT1_A::OFF) + } + #[doc = "Re-trigger counter on event"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(EVACT1_A::RETRIGGER) + } + #[doc = "Direction control"] + #[inline(always)] + pub fn dir(self) -> &'a mut W { + self.variant(EVACT1_A::DIR) + } + #[doc = "Stop counter on event"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(EVACT1_A::STOP) + } + #[doc = "Decrement counter on event"] + #[inline(always)] + pub fn dec(self) -> &'a mut W { + self.variant(EVACT1_A::DEC) + } + #[doc = "Period capture value in CC0 register, pulse width capture value in CC1 register"] + #[inline(always)] + pub fn ppw(self) -> &'a mut W { + self.variant(EVACT1_A::PPW) + } + #[doc = "Period capture value in CC1 register, pulse width capture value in CC0 register"] + #[inline(always)] + pub fn pwp(self) -> &'a mut W { + self.variant(EVACT1_A::PWP) + } + #[doc = "Non-recoverable fault"] + #[inline(always)] + pub fn fault(self) -> &'a mut W { + self.variant(EVACT1_A::FAULT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 3)) | ((value as u32 & 0x07) << 3); + self.w + } +} +#[doc = "Timer/counter Output Event Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CNTSEL_A { + #[doc = "0: An interrupt/event is generated when a new counter cycle starts"] + START = 0, + #[doc = "1: An interrupt/event is generated when a counter cycle ends"] + END = 1, + #[doc = "2: An interrupt/event is generated when a counter cycle ends, except for the first and last cycles"] + BETWEEN = 2, + #[doc = "3: An interrupt/event is generated when a new counter cycle starts or a counter cycle ends"] + BOUNDARY = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CNTSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `CNTSEL` reader - Timer/counter Output Event Mode"] +pub struct CNTSEL_R(crate::FieldReader); +impl CNTSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CNTSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CNTSEL_A { + match self.bits { + 0 => CNTSEL_A::START, + 1 => CNTSEL_A::END, + 2 => CNTSEL_A::BETWEEN, + 3 => CNTSEL_A::BOUNDARY, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `START`"] + #[inline(always)] + pub fn is_start(&self) -> bool { + **self == CNTSEL_A::START + } + #[doc = "Checks if the value of the field is `END`"] + #[inline(always)] + pub fn is_end(&self) -> bool { + **self == CNTSEL_A::END + } + #[doc = "Checks if the value of the field is `BETWEEN`"] + #[inline(always)] + pub fn is_between(&self) -> bool { + **self == CNTSEL_A::BETWEEN + } + #[doc = "Checks if the value of the field is `BOUNDARY`"] + #[inline(always)] + pub fn is_boundary(&self) -> bool { + **self == CNTSEL_A::BOUNDARY + } +} +impl core::ops::Deref for CNTSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CNTSEL` writer - Timer/counter Output Event Mode"] +pub struct CNTSEL_W<'a> { + w: &'a mut W, +} +impl<'a> CNTSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CNTSEL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "An interrupt/event is generated when a new counter cycle starts"] + #[inline(always)] + pub fn start(self) -> &'a mut W { + self.variant(CNTSEL_A::START) + } + #[doc = "An interrupt/event is generated when a counter cycle ends"] + #[inline(always)] + pub fn end(self) -> &'a mut W { + self.variant(CNTSEL_A::END) + } + #[doc = "An interrupt/event is generated when a counter cycle ends, except for the first and last cycles"] + #[inline(always)] + pub fn between(self) -> &'a mut W { + self.variant(CNTSEL_A::BETWEEN) + } + #[doc = "An interrupt/event is generated when a new counter cycle starts or a counter cycle ends"] + #[inline(always)] + pub fn boundary(self) -> &'a mut W { + self.variant(CNTSEL_A::BOUNDARY) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 6)) | ((value as u32 & 0x03) << 6); + self.w + } +} +#[doc = "Field `OVFEO` reader - Overflow/Underflow Output Event Enable"] +pub struct OVFEO_R(crate::FieldReader); +impl OVFEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVFEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVFEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVFEO` writer - Overflow/Underflow Output Event Enable"] +pub struct OVFEO_W<'a> { + w: &'a mut W, +} +impl<'a> OVFEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `TRGEO` reader - Retrigger Output Event Enable"] +pub struct TRGEO_R(crate::FieldReader); +impl TRGEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRGEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRGEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRGEO` writer - Retrigger Output Event Enable"] +pub struct TRGEO_W<'a> { + w: &'a mut W, +} +impl<'a> TRGEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `CNTEO` reader - Timer/counter Output Event Enable"] +pub struct CNTEO_R(crate::FieldReader); +impl CNTEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CNTEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CNTEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CNTEO` writer - Timer/counter Output Event Enable"] +pub struct CNTEO_W<'a> { + w: &'a mut W, +} +impl<'a> CNTEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `TCINV0` reader - Inverted Event 0 Input Enable"] +pub struct TCINV0_R(crate::FieldReader); +impl TCINV0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCINV0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCINV0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCINV0` writer - Inverted Event 0 Input Enable"] +pub struct TCINV0_W<'a> { + w: &'a mut W, +} +impl<'a> TCINV0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `TCINV1` reader - Inverted Event 1 Input Enable"] +pub struct TCINV1_R(crate::FieldReader); +impl TCINV1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCINV1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCINV1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCINV1` writer - Inverted Event 1 Input Enable"] +pub struct TCINV1_W<'a> { + w: &'a mut W, +} +impl<'a> TCINV1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `TCEI0` reader - Timer/counter Event 0 Input Enable"] +pub struct TCEI0_R(crate::FieldReader); +impl TCEI0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCEI0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCEI0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCEI0` writer - Timer/counter Event 0 Input Enable"] +pub struct TCEI0_W<'a> { + w: &'a mut W, +} +impl<'a> TCEI0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `TCEI1` reader - Timer/counter Event 1 Input Enable"] +pub struct TCEI1_R(crate::FieldReader); +impl TCEI1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TCEI1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCEI1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCEI1` writer - Timer/counter Event 1 Input Enable"] +pub struct TCEI1_W<'a> { + w: &'a mut W, +} +impl<'a> TCEI1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `MCEI0` reader - Match or Capture Channel 0 Event Input Enable"] +pub struct MCEI0_R(crate::FieldReader); +impl MCEI0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEI0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEI0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEI0` writer - Match or Capture Channel 0 Event Input Enable"] +pub struct MCEI0_W<'a> { + w: &'a mut W, +} +impl<'a> MCEI0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `MCEI1` reader - Match or Capture Channel 1 Event Input Enable"] +pub struct MCEI1_R(crate::FieldReader); +impl MCEI1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEI1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEI1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEI1` writer - Match or Capture Channel 1 Event Input Enable"] +pub struct MCEI1_W<'a> { + w: &'a mut W, +} +impl<'a> MCEI1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `MCEI2` reader - Match or Capture Channel 2 Event Input Enable"] +pub struct MCEI2_R(crate::FieldReader); +impl MCEI2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEI2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEI2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEI2` writer - Match or Capture Channel 2 Event Input Enable"] +pub struct MCEI2_W<'a> { + w: &'a mut W, +} +impl<'a> MCEI2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `MCEI3` reader - Match or Capture Channel 3 Event Input Enable"] +pub struct MCEI3_R(crate::FieldReader); +impl MCEI3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEI3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEI3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEI3` writer - Match or Capture Channel 3 Event Input Enable"] +pub struct MCEI3_W<'a> { + w: &'a mut W, +} +impl<'a> MCEI3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `MCEO0` reader - Match or Capture Channel 0 Event Output Enable"] +pub struct MCEO0_R(crate::FieldReader); +impl MCEO0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO0` writer - Match or Capture Channel 0 Event Output Enable"] +pub struct MCEO0_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `MCEO1` reader - Match or Capture Channel 1 Event Output Enable"] +pub struct MCEO1_R(crate::FieldReader); +impl MCEO1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO1` writer - Match or Capture Channel 1 Event Output Enable"] +pub struct MCEO1_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `MCEO2` reader - Match or Capture Channel 2 Event Output Enable"] +pub struct MCEO2_R(crate::FieldReader); +impl MCEO2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO2` writer - Match or Capture Channel 2 Event Output Enable"] +pub struct MCEO2_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `MCEO3` reader - Match or Capture Channel 3 Event Output Enable"] +pub struct MCEO3_R(crate::FieldReader); +impl MCEO3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MCEO3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCEO3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCEO3` writer - Match or Capture Channel 3 Event Output Enable"] +pub struct MCEO3_W<'a> { + w: &'a mut W, +} +impl<'a> MCEO3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Timer/counter Input Event0 Action"] + #[inline(always)] + pub fn evact0(&self) -> EVACT0_R { + EVACT0_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bits 3:5 - Timer/counter Input Event1 Action"] + #[inline(always)] + pub fn evact1(&self) -> EVACT1_R { + EVACT1_R::new(((self.bits >> 3) & 0x07) as u8) + } + #[doc = "Bits 6:7 - Timer/counter Output Event Mode"] + #[inline(always)] + pub fn cntsel(&self) -> CNTSEL_R { + CNTSEL_R::new(((self.bits >> 6) & 0x03) as u8) + } + #[doc = "Bit 8 - Overflow/Underflow Output Event Enable"] + #[inline(always)] + pub fn ovfeo(&self) -> OVFEO_R { + OVFEO_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Retrigger Output Event Enable"] + #[inline(always)] + pub fn trgeo(&self) -> TRGEO_R { + TRGEO_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Timer/counter Output Event Enable"] + #[inline(always)] + pub fn cnteo(&self) -> CNTEO_R { + CNTEO_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 12 - Inverted Event 0 Input Enable"] + #[inline(always)] + pub fn tcinv0(&self) -> TCINV0_R { + TCINV0_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Inverted Event 1 Input Enable"] + #[inline(always)] + pub fn tcinv1(&self) -> TCINV1_R { + TCINV1_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Timer/counter Event 0 Input Enable"] + #[inline(always)] + pub fn tcei0(&self) -> TCEI0_R { + TCEI0_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Timer/counter Event 1 Input Enable"] + #[inline(always)] + pub fn tcei1(&self) -> TCEI1_R { + TCEI1_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Match or Capture Channel 0 Event Input Enable"] + #[inline(always)] + pub fn mcei0(&self) -> MCEI0_R { + MCEI0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Match or Capture Channel 1 Event Input Enable"] + #[inline(always)] + pub fn mcei1(&self) -> MCEI1_R { + MCEI1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Match or Capture Channel 2 Event Input Enable"] + #[inline(always)] + pub fn mcei2(&self) -> MCEI2_R { + MCEI2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Match or Capture Channel 3 Event Input Enable"] + #[inline(always)] + pub fn mcei3(&self) -> MCEI3_R { + MCEI3_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 24 - Match or Capture Channel 0 Event Output Enable"] + #[inline(always)] + pub fn mceo0(&self) -> MCEO0_R { + MCEO0_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Match or Capture Channel 1 Event Output Enable"] + #[inline(always)] + pub fn mceo1(&self) -> MCEO1_R { + MCEO1_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Match or Capture Channel 2 Event Output Enable"] + #[inline(always)] + pub fn mceo2(&self) -> MCEO2_R { + MCEO2_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Match or Capture Channel 3 Event Output Enable"] + #[inline(always)] + pub fn mceo3(&self) -> MCEO3_R { + MCEO3_R::new(((self.bits >> 27) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Timer/counter Input Event0 Action"] + #[inline(always)] + pub fn evact0(&mut self) -> EVACT0_W { + EVACT0_W { w: self } + } + #[doc = "Bits 3:5 - Timer/counter Input Event1 Action"] + #[inline(always)] + pub fn evact1(&mut self) -> EVACT1_W { + EVACT1_W { w: self } + } + #[doc = "Bits 6:7 - Timer/counter Output Event Mode"] + #[inline(always)] + pub fn cntsel(&mut self) -> CNTSEL_W { + CNTSEL_W { w: self } + } + #[doc = "Bit 8 - Overflow/Underflow Output Event Enable"] + #[inline(always)] + pub fn ovfeo(&mut self) -> OVFEO_W { + OVFEO_W { w: self } + } + #[doc = "Bit 9 - Retrigger Output Event Enable"] + #[inline(always)] + pub fn trgeo(&mut self) -> TRGEO_W { + TRGEO_W { w: self } + } + #[doc = "Bit 10 - Timer/counter Output Event Enable"] + #[inline(always)] + pub fn cnteo(&mut self) -> CNTEO_W { + CNTEO_W { w: self } + } + #[doc = "Bit 12 - Inverted Event 0 Input Enable"] + #[inline(always)] + pub fn tcinv0(&mut self) -> TCINV0_W { + TCINV0_W { w: self } + } + #[doc = "Bit 13 - Inverted Event 1 Input Enable"] + #[inline(always)] + pub fn tcinv1(&mut self) -> TCINV1_W { + TCINV1_W { w: self } + } + #[doc = "Bit 14 - Timer/counter Event 0 Input Enable"] + #[inline(always)] + pub fn tcei0(&mut self) -> TCEI0_W { + TCEI0_W { w: self } + } + #[doc = "Bit 15 - Timer/counter Event 1 Input Enable"] + #[inline(always)] + pub fn tcei1(&mut self) -> TCEI1_W { + TCEI1_W { w: self } + } + #[doc = "Bit 16 - Match or Capture Channel 0 Event Input Enable"] + #[inline(always)] + pub fn mcei0(&mut self) -> MCEI0_W { + MCEI0_W { w: self } + } + #[doc = "Bit 17 - Match or Capture Channel 1 Event Input Enable"] + #[inline(always)] + pub fn mcei1(&mut self) -> MCEI1_W { + MCEI1_W { w: self } + } + #[doc = "Bit 18 - Match or Capture Channel 2 Event Input Enable"] + #[inline(always)] + pub fn mcei2(&mut self) -> MCEI2_W { + MCEI2_W { w: self } + } + #[doc = "Bit 19 - Match or Capture Channel 3 Event Input Enable"] + #[inline(always)] + pub fn mcei3(&mut self) -> MCEI3_W { + MCEI3_W { w: self } + } + #[doc = "Bit 24 - Match or Capture Channel 0 Event Output Enable"] + #[inline(always)] + pub fn mceo0(&mut self) -> MCEO0_W { + MCEO0_W { w: self } + } + #[doc = "Bit 25 - Match or Capture Channel 1 Event Output Enable"] + #[inline(always)] + pub fn mceo1(&mut self) -> MCEO1_W { + MCEO1_W { w: self } + } + #[doc = "Bit 26 - Match or Capture Channel 2 Event Output Enable"] + #[inline(always)] + pub fn mceo2(&mut self) -> MCEO2_W { + MCEO2_W { w: self } + } + #[doc = "Bit 27 - Match or Capture Channel 3 Event Output Enable"] + #[inline(always)] + pub fn mceo3(&mut self) -> MCEO3_W { + MCEO3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/tcc0/fctrla.rs b/pac/atsamc21n/src/tcc0/fctrla.rs new file mode 100644 index 000000000000..77c7276fee23 --- /dev/null +++ b/pac/atsamc21n/src/tcc0/fctrla.rs @@ -0,0 +1,940 @@ +#[doc = "Register `FCTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FCTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Fault A Source\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SRC_A { + #[doc = "0: Fault input disabled"] + DISABLE = 0, + #[doc = "1: MCEx (x=0,1) event input"] + ENABLE = 1, + #[doc = "2: Inverted MCEx (x=0,1) event input"] + INVERT = 2, + #[doc = "3: Alternate fault (A or B) state at the end of the previous period"] + ALTFAULT = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SRC_A) -> Self { + variant as _ + } +} +#[doc = "Field `SRC` reader - Fault A Source"] +pub struct SRC_R(crate::FieldReader); +impl SRC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SRC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SRC_A { + match self.bits { + 0 => SRC_A::DISABLE, + 1 => SRC_A::ENABLE, + 2 => SRC_A::INVERT, + 3 => SRC_A::ALTFAULT, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == SRC_A::DISABLE + } + #[doc = "Checks if the value of the field is `ENABLE`"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + **self == SRC_A::ENABLE + } + #[doc = "Checks if the value of the field is `INVERT`"] + #[inline(always)] + pub fn is_invert(&self) -> bool { + **self == SRC_A::INVERT + } + #[doc = "Checks if the value of the field is `ALTFAULT`"] + #[inline(always)] + pub fn is_altfault(&self) -> bool { + **self == SRC_A::ALTFAULT + } +} +impl core::ops::Deref for SRC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SRC` writer - Fault A Source"] +pub struct SRC_W<'a> { + w: &'a mut W, +} +impl<'a> SRC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SRC_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Fault input disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(SRC_A::DISABLE) + } + #[doc = "MCEx (x=0,1) event input"] + #[inline(always)] + pub fn enable(self) -> &'a mut W { + self.variant(SRC_A::ENABLE) + } + #[doc = "Inverted MCEx (x=0,1) event input"] + #[inline(always)] + pub fn invert(self) -> &'a mut W { + self.variant(SRC_A::INVERT) + } + #[doc = "Alternate fault (A or B) state at the end of the previous period"] + #[inline(always)] + pub fn altfault(self) -> &'a mut W { + self.variant(SRC_A::ALTFAULT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u32 & 0x03); + self.w + } +} +#[doc = "Field `KEEP` reader - Fault A Keeper"] +pub struct KEEP_R(crate::FieldReader); +impl KEEP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + KEEP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for KEEP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `KEEP` writer - Fault A Keeper"] +pub struct KEEP_W<'a> { + w: &'a mut W, +} +impl<'a> KEEP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `QUAL` reader - Fault A Qualification"] +pub struct QUAL_R(crate::FieldReader); +impl QUAL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + QUAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for QUAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `QUAL` writer - Fault A Qualification"] +pub struct QUAL_W<'a> { + w: &'a mut W, +} +impl<'a> QUAL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Fault A Blanking Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum BLANK_A { + #[doc = "0: Blanking applied from start of the ramp"] + START = 0, + #[doc = "1: Blanking applied from rising edge of the output waveform"] + RISE = 1, + #[doc = "2: Blanking applied from falling edge of the output waveform"] + FALL = 2, + #[doc = "3: Blanking applied from each toggle of the output waveform"] + BOTH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: BLANK_A) -> Self { + variant as _ + } +} +#[doc = "Field `BLANK` reader - Fault A Blanking Mode"] +pub struct BLANK_R(crate::FieldReader); +impl BLANK_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BLANK_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> BLANK_A { + match self.bits { + 0 => BLANK_A::START, + 1 => BLANK_A::RISE, + 2 => BLANK_A::FALL, + 3 => BLANK_A::BOTH, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `START`"] + #[inline(always)] + pub fn is_start(&self) -> bool { + **self == BLANK_A::START + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == BLANK_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == BLANK_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == BLANK_A::BOTH + } +} +impl core::ops::Deref for BLANK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BLANK` writer - Fault A Blanking Mode"] +pub struct BLANK_W<'a> { + w: &'a mut W, +} +impl<'a> BLANK_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: BLANK_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Blanking applied from start of the ramp"] + #[inline(always)] + pub fn start(self) -> &'a mut W { + self.variant(BLANK_A::START) + } + #[doc = "Blanking applied from rising edge of the output waveform"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(BLANK_A::RISE) + } + #[doc = "Blanking applied from falling edge of the output waveform"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(BLANK_A::FALL) + } + #[doc = "Blanking applied from each toggle of the output waveform"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(BLANK_A::BOTH) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 5)) | ((value as u32 & 0x03) << 5); + self.w + } +} +#[doc = "Field `RESTART` reader - Fault A Restart"] +pub struct RESTART_R(crate::FieldReader); +impl RESTART_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESTART_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESTART_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESTART` writer - Fault A Restart"] +pub struct RESTART_W<'a> { + w: &'a mut W, +} +impl<'a> RESTART_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Fault A Halt Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum HALT_A { + #[doc = "0: Halt action disabled"] + DISABLE = 0, + #[doc = "1: Hardware halt action"] + HW = 1, + #[doc = "2: Software halt action"] + SW = 2, + #[doc = "3: Non-recoverable fault"] + NR = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: HALT_A) -> Self { + variant as _ + } +} +#[doc = "Field `HALT` reader - Fault A Halt Mode"] +pub struct HALT_R(crate::FieldReader); +impl HALT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + HALT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> HALT_A { + match self.bits { + 0 => HALT_A::DISABLE, + 1 => HALT_A::HW, + 2 => HALT_A::SW, + 3 => HALT_A::NR, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == HALT_A::DISABLE + } + #[doc = "Checks if the value of the field is `HW`"] + #[inline(always)] + pub fn is_hw(&self) -> bool { + **self == HALT_A::HW + } + #[doc = "Checks if the value of the field is `SW`"] + #[inline(always)] + pub fn is_sw(&self) -> bool { + **self == HALT_A::SW + } + #[doc = "Checks if the value of the field is `NR`"] + #[inline(always)] + pub fn is_nr(&self) -> bool { + **self == HALT_A::NR + } +} +impl core::ops::Deref for HALT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HALT` writer - Fault A Halt Mode"] +pub struct HALT_W<'a> { + w: &'a mut W, +} +impl<'a> HALT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: HALT_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Halt action disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(HALT_A::DISABLE) + } + #[doc = "Hardware halt action"] + #[inline(always)] + pub fn hw(self) -> &'a mut W { + self.variant(HALT_A::HW) + } + #[doc = "Software halt action"] + #[inline(always)] + pub fn sw(self) -> &'a mut W { + self.variant(HALT_A::SW) + } + #[doc = "Non-recoverable fault"] + #[inline(always)] + pub fn nr(self) -> &'a mut W { + self.variant(HALT_A::NR) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 8)) | ((value as u32 & 0x03) << 8); + self.w + } +} +#[doc = "Fault A Capture Channel\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CHSEL_A { + #[doc = "0: Capture value stored in channel 0"] + CC0 = 0, + #[doc = "1: Capture value stored in channel 1"] + CC1 = 1, + #[doc = "2: Capture value stored in channel 2"] + CC2 = 2, + #[doc = "3: Capture value stored in channel 3"] + CC3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CHSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `CHSEL` reader - Fault A Capture Channel"] +pub struct CHSEL_R(crate::FieldReader); +impl CHSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CHSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CHSEL_A { + match self.bits { + 0 => CHSEL_A::CC0, + 1 => CHSEL_A::CC1, + 2 => CHSEL_A::CC2, + 3 => CHSEL_A::CC3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `CC0`"] + #[inline(always)] + pub fn is_cc0(&self) -> bool { + **self == CHSEL_A::CC0 + } + #[doc = "Checks if the value of the field is `CC1`"] + #[inline(always)] + pub fn is_cc1(&self) -> bool { + **self == CHSEL_A::CC1 + } + #[doc = "Checks if the value of the field is `CC2`"] + #[inline(always)] + pub fn is_cc2(&self) -> bool { + **self == CHSEL_A::CC2 + } + #[doc = "Checks if the value of the field is `CC3`"] + #[inline(always)] + pub fn is_cc3(&self) -> bool { + **self == CHSEL_A::CC3 + } +} +impl core::ops::Deref for CHSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHSEL` writer - Fault A Capture Channel"] +pub struct CHSEL_W<'a> { + w: &'a mut W, +} +impl<'a> CHSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CHSEL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Capture value stored in channel 0"] + #[inline(always)] + pub fn cc0(self) -> &'a mut W { + self.variant(CHSEL_A::CC0) + } + #[doc = "Capture value stored in channel 1"] + #[inline(always)] + pub fn cc1(self) -> &'a mut W { + self.variant(CHSEL_A::CC1) + } + #[doc = "Capture value stored in channel 2"] + #[inline(always)] + pub fn cc2(self) -> &'a mut W { + self.variant(CHSEL_A::CC2) + } + #[doc = "Capture value stored in channel 3"] + #[inline(always)] + pub fn cc3(self) -> &'a mut W { + self.variant(CHSEL_A::CC3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 10)) | ((value as u32 & 0x03) << 10); + self.w + } +} +#[doc = "Fault A Capture Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CAPTURE_A { + #[doc = "0: No capture"] + DISABLE = 0, + #[doc = "1: Capture on fault"] + CAPT = 1, + #[doc = "2: Minimum capture"] + CAPTMIN = 2, + #[doc = "3: Maximum capture"] + CAPTMAX = 3, + #[doc = "4: Minimum local detection"] + LOCMIN = 4, + #[doc = "5: Maximum local detection"] + LOCMAX = 5, + #[doc = "6: Minimum and maximum local detection"] + DERIV0 = 6, + #[doc = "7: Capture with ramp index as MSB value"] + CAPTMARK = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CAPTURE_A) -> Self { + variant as _ + } +} +#[doc = "Field `CAPTURE` reader - Fault A Capture Action"] +pub struct CAPTURE_R(crate::FieldReader); +impl CAPTURE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CAPTURE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CAPTURE_A { + match self.bits { + 0 => CAPTURE_A::DISABLE, + 1 => CAPTURE_A::CAPT, + 2 => CAPTURE_A::CAPTMIN, + 3 => CAPTURE_A::CAPTMAX, + 4 => CAPTURE_A::LOCMIN, + 5 => CAPTURE_A::LOCMAX, + 6 => CAPTURE_A::DERIV0, + 7 => CAPTURE_A::CAPTMARK, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == CAPTURE_A::DISABLE + } + #[doc = "Checks if the value of the field is `CAPT`"] + #[inline(always)] + pub fn is_capt(&self) -> bool { + **self == CAPTURE_A::CAPT + } + #[doc = "Checks if the value of the field is `CAPTMIN`"] + #[inline(always)] + pub fn is_captmin(&self) -> bool { + **self == CAPTURE_A::CAPTMIN + } + #[doc = "Checks if the value of the field is `CAPTMAX`"] + #[inline(always)] + pub fn is_captmax(&self) -> bool { + **self == CAPTURE_A::CAPTMAX + } + #[doc = "Checks if the value of the field is `LOCMIN`"] + #[inline(always)] + pub fn is_locmin(&self) -> bool { + **self == CAPTURE_A::LOCMIN + } + #[doc = "Checks if the value of the field is `LOCMAX`"] + #[inline(always)] + pub fn is_locmax(&self) -> bool { + **self == CAPTURE_A::LOCMAX + } + #[doc = "Checks if the value of the field is `DERIV0`"] + #[inline(always)] + pub fn is_deriv0(&self) -> bool { + **self == CAPTURE_A::DERIV0 + } + #[doc = "Checks if the value of the field is `CAPTMARK`"] + #[inline(always)] + pub fn is_captmark(&self) -> bool { + **self == CAPTURE_A::CAPTMARK + } +} +impl core::ops::Deref for CAPTURE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAPTURE` writer - Fault A Capture Action"] +pub struct CAPTURE_W<'a> { + w: &'a mut W, +} +impl<'a> CAPTURE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CAPTURE_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "No capture"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(CAPTURE_A::DISABLE) + } + #[doc = "Capture on fault"] + #[inline(always)] + pub fn capt(self) -> &'a mut W { + self.variant(CAPTURE_A::CAPT) + } + #[doc = "Minimum capture"] + #[inline(always)] + pub fn captmin(self) -> &'a mut W { + self.variant(CAPTURE_A::CAPTMIN) + } + #[doc = "Maximum capture"] + #[inline(always)] + pub fn captmax(self) -> &'a mut W { + self.variant(CAPTURE_A::CAPTMAX) + } + #[doc = "Minimum local detection"] + #[inline(always)] + pub fn locmin(self) -> &'a mut W { + self.variant(CAPTURE_A::LOCMIN) + } + #[doc = "Maximum local detection"] + #[inline(always)] + pub fn locmax(self) -> &'a mut W { + self.variant(CAPTURE_A::LOCMAX) + } + #[doc = "Minimum and maximum local detection"] + #[inline(always)] + pub fn deriv0(self) -> &'a mut W { + self.variant(CAPTURE_A::DERIV0) + } + #[doc = "Capture with ramp index as MSB value"] + #[inline(always)] + pub fn captmark(self) -> &'a mut W { + self.variant(CAPTURE_A::CAPTMARK) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 12)) | ((value as u32 & 0x07) << 12); + self.w + } +} +#[doc = "Field `BLANKPRESC` reader - Fault A Blanking Prescaler"] +pub struct BLANKPRESC_R(crate::FieldReader); +impl BLANKPRESC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BLANKPRESC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BLANKPRESC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BLANKPRESC` writer - Fault A Blanking Prescaler"] +pub struct BLANKPRESC_W<'a> { + w: &'a mut W, +} +impl<'a> BLANKPRESC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `BLANKVAL` reader - Fault A Blanking Time"] +pub struct BLANKVAL_R(crate::FieldReader); +impl BLANKVAL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BLANKVAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BLANKVAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BLANKVAL` writer - Fault A Blanking Time"] +pub struct BLANKVAL_W<'a> { + w: &'a mut W, +} +impl<'a> BLANKVAL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +#[doc = "Field `FILTERVAL` reader - Fault A Filter Value"] +pub struct FILTERVAL_R(crate::FieldReader); +impl FILTERVAL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FILTERVAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTERVAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTERVAL` writer - Fault A Filter Value"] +pub struct FILTERVAL_W<'a> { + w: &'a mut W, +} +impl<'a> FILTERVAL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Fault A Source"] + #[inline(always)] + pub fn src(&self) -> SRC_R { + SRC_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bit 3 - Fault A Keeper"] + #[inline(always)] + pub fn keep(&self) -> KEEP_R { + KEEP_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Fault A Qualification"] + #[inline(always)] + pub fn qual(&self) -> QUAL_R { + QUAL_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bits 5:6 - Fault A Blanking Mode"] + #[inline(always)] + pub fn blank(&self) -> BLANK_R { + BLANK_R::new(((self.bits >> 5) & 0x03) as u8) + } + #[doc = "Bit 7 - Fault A Restart"] + #[inline(always)] + pub fn restart(&self) -> RESTART_R { + RESTART_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:9 - Fault A Halt Mode"] + #[inline(always)] + pub fn halt(&self) -> HALT_R { + HALT_R::new(((self.bits >> 8) & 0x03) as u8) + } + #[doc = "Bits 10:11 - Fault A Capture Channel"] + #[inline(always)] + pub fn chsel(&self) -> CHSEL_R { + CHSEL_R::new(((self.bits >> 10) & 0x03) as u8) + } + #[doc = "Bits 12:14 - Fault A Capture Action"] + #[inline(always)] + pub fn capture(&self) -> CAPTURE_R { + CAPTURE_R::new(((self.bits >> 12) & 0x07) as u8) + } + #[doc = "Bit 15 - Fault A Blanking Prescaler"] + #[inline(always)] + pub fn blankpresc(&self) -> BLANKPRESC_R { + BLANKPRESC_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:23 - Fault A Blanking Time"] + #[inline(always)] + pub fn blankval(&self) -> BLANKVAL_R { + BLANKVAL_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:27 - Fault A Filter Value"] + #[inline(always)] + pub fn filterval(&self) -> FILTERVAL_R { + FILTERVAL_R::new(((self.bits >> 24) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Fault A Source"] + #[inline(always)] + pub fn src(&mut self) -> SRC_W { + SRC_W { w: self } + } + #[doc = "Bit 3 - Fault A Keeper"] + #[inline(always)] + pub fn keep(&mut self) -> KEEP_W { + KEEP_W { w: self } + } + #[doc = "Bit 4 - Fault A Qualification"] + #[inline(always)] + pub fn qual(&mut self) -> QUAL_W { + QUAL_W { w: self } + } + #[doc = "Bits 5:6 - Fault A Blanking Mode"] + #[inline(always)] + pub fn blank(&mut self) -> BLANK_W { + BLANK_W { w: self } + } + #[doc = "Bit 7 - Fault A Restart"] + #[inline(always)] + pub fn restart(&mut self) -> RESTART_W { + RESTART_W { w: self } + } + #[doc = "Bits 8:9 - Fault A Halt Mode"] + #[inline(always)] + pub fn halt(&mut self) -> HALT_W { + HALT_W { w: self } + } + #[doc = "Bits 10:11 - Fault A Capture Channel"] + #[inline(always)] + pub fn chsel(&mut self) -> CHSEL_W { + CHSEL_W { w: self } + } + #[doc = "Bits 12:14 - Fault A Capture Action"] + #[inline(always)] + pub fn capture(&mut self) -> CAPTURE_W { + CAPTURE_W { w: self } + } + #[doc = "Bit 15 - Fault A Blanking Prescaler"] + #[inline(always)] + pub fn blankpresc(&mut self) -> BLANKPRESC_W { + BLANKPRESC_W { w: self } + } + #[doc = "Bits 16:23 - Fault A Blanking Time"] + #[inline(always)] + pub fn blankval(&mut self) -> BLANKVAL_W { + BLANKVAL_W { w: self } + } + #[doc = "Bits 24:27 - Fault A Filter Value"] + #[inline(always)] + pub fn filterval(&mut self) -> FILTERVAL_W { + FILTERVAL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Recoverable Fault A Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fctrla](index.html) module"] +pub struct FCTRLA_SPEC; +impl crate::RegisterSpec for FCTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [fctrla::R](R) reader structure"] +impl crate::Readable for FCTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [fctrla::W](W) writer structure"] +impl crate::Writable for FCTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets FCTRLA to value 0"] +impl crate::Resettable for FCTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/tcc0/fctrlb.rs b/pac/atsamc21n/src/tcc0/fctrlb.rs new file mode 100644 index 000000000000..4c1dfd1af93d --- /dev/null +++ b/pac/atsamc21n/src/tcc0/fctrlb.rs @@ -0,0 +1,940 @@ +#[doc = "Register `FCTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FCTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Fault B Source\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SRC_A { + #[doc = "0: Fault input disabled"] + DISABLE = 0, + #[doc = "1: MCEx (x=0,1) event input"] + ENABLE = 1, + #[doc = "2: Inverted MCEx (x=0,1) event input"] + INVERT = 2, + #[doc = "3: Alternate fault (A or B) state at the end of the previous period"] + ALTFAULT = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SRC_A) -> Self { + variant as _ + } +} +#[doc = "Field `SRC` reader - Fault B Source"] +pub struct SRC_R(crate::FieldReader); +impl SRC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SRC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SRC_A { + match self.bits { + 0 => SRC_A::DISABLE, + 1 => SRC_A::ENABLE, + 2 => SRC_A::INVERT, + 3 => SRC_A::ALTFAULT, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == SRC_A::DISABLE + } + #[doc = "Checks if the value of the field is `ENABLE`"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + **self == SRC_A::ENABLE + } + #[doc = "Checks if the value of the field is `INVERT`"] + #[inline(always)] + pub fn is_invert(&self) -> bool { + **self == SRC_A::INVERT + } + #[doc = "Checks if the value of the field is `ALTFAULT`"] + #[inline(always)] + pub fn is_altfault(&self) -> bool { + **self == SRC_A::ALTFAULT + } +} +impl core::ops::Deref for SRC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SRC` writer - Fault B Source"] +pub struct SRC_W<'a> { + w: &'a mut W, +} +impl<'a> SRC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SRC_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Fault input disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(SRC_A::DISABLE) + } + #[doc = "MCEx (x=0,1) event input"] + #[inline(always)] + pub fn enable(self) -> &'a mut W { + self.variant(SRC_A::ENABLE) + } + #[doc = "Inverted MCEx (x=0,1) event input"] + #[inline(always)] + pub fn invert(self) -> &'a mut W { + self.variant(SRC_A::INVERT) + } + #[doc = "Alternate fault (A or B) state at the end of the previous period"] + #[inline(always)] + pub fn altfault(self) -> &'a mut W { + self.variant(SRC_A::ALTFAULT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u32 & 0x03); + self.w + } +} +#[doc = "Field `KEEP` reader - Fault B Keeper"] +pub struct KEEP_R(crate::FieldReader); +impl KEEP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + KEEP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for KEEP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `KEEP` writer - Fault B Keeper"] +pub struct KEEP_W<'a> { + w: &'a mut W, +} +impl<'a> KEEP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `QUAL` reader - Fault B Qualification"] +pub struct QUAL_R(crate::FieldReader); +impl QUAL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + QUAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for QUAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `QUAL` writer - Fault B Qualification"] +pub struct QUAL_W<'a> { + w: &'a mut W, +} +impl<'a> QUAL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Fault B Blanking Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum BLANK_A { + #[doc = "0: Blanking applied from start of the ramp"] + START = 0, + #[doc = "1: Blanking applied from rising edge of the output waveform"] + RISE = 1, + #[doc = "2: Blanking applied from falling edge of the output waveform"] + FALL = 2, + #[doc = "3: Blanking applied from each toggle of the output waveform"] + BOTH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: BLANK_A) -> Self { + variant as _ + } +} +#[doc = "Field `BLANK` reader - Fault B Blanking Mode"] +pub struct BLANK_R(crate::FieldReader); +impl BLANK_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BLANK_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> BLANK_A { + match self.bits { + 0 => BLANK_A::START, + 1 => BLANK_A::RISE, + 2 => BLANK_A::FALL, + 3 => BLANK_A::BOTH, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `START`"] + #[inline(always)] + pub fn is_start(&self) -> bool { + **self == BLANK_A::START + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + **self == BLANK_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + **self == BLANK_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + **self == BLANK_A::BOTH + } +} +impl core::ops::Deref for BLANK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BLANK` writer - Fault B Blanking Mode"] +pub struct BLANK_W<'a> { + w: &'a mut W, +} +impl<'a> BLANK_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: BLANK_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Blanking applied from start of the ramp"] + #[inline(always)] + pub fn start(self) -> &'a mut W { + self.variant(BLANK_A::START) + } + #[doc = "Blanking applied from rising edge of the output waveform"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(BLANK_A::RISE) + } + #[doc = "Blanking applied from falling edge of the output waveform"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(BLANK_A::FALL) + } + #[doc = "Blanking applied from each toggle of the output waveform"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(BLANK_A::BOTH) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 5)) | ((value as u32 & 0x03) << 5); + self.w + } +} +#[doc = "Field `RESTART` reader - Fault B Restart"] +pub struct RESTART_R(crate::FieldReader); +impl RESTART_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESTART_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESTART_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESTART` writer - Fault B Restart"] +pub struct RESTART_W<'a> { + w: &'a mut W, +} +impl<'a> RESTART_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Fault B Halt Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum HALT_A { + #[doc = "0: Halt action disabled"] + DISABLE = 0, + #[doc = "1: Hardware halt action"] + HW = 1, + #[doc = "2: Software halt action"] + SW = 2, + #[doc = "3: Non-recoverable fault"] + NR = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: HALT_A) -> Self { + variant as _ + } +} +#[doc = "Field `HALT` reader - Fault B Halt Mode"] +pub struct HALT_R(crate::FieldReader); +impl HALT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + HALT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> HALT_A { + match self.bits { + 0 => HALT_A::DISABLE, + 1 => HALT_A::HW, + 2 => HALT_A::SW, + 3 => HALT_A::NR, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == HALT_A::DISABLE + } + #[doc = "Checks if the value of the field is `HW`"] + #[inline(always)] + pub fn is_hw(&self) -> bool { + **self == HALT_A::HW + } + #[doc = "Checks if the value of the field is `SW`"] + #[inline(always)] + pub fn is_sw(&self) -> bool { + **self == HALT_A::SW + } + #[doc = "Checks if the value of the field is `NR`"] + #[inline(always)] + pub fn is_nr(&self) -> bool { + **self == HALT_A::NR + } +} +impl core::ops::Deref for HALT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HALT` writer - Fault B Halt Mode"] +pub struct HALT_W<'a> { + w: &'a mut W, +} +impl<'a> HALT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: HALT_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Halt action disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(HALT_A::DISABLE) + } + #[doc = "Hardware halt action"] + #[inline(always)] + pub fn hw(self) -> &'a mut W { + self.variant(HALT_A::HW) + } + #[doc = "Software halt action"] + #[inline(always)] + pub fn sw(self) -> &'a mut W { + self.variant(HALT_A::SW) + } + #[doc = "Non-recoverable fault"] + #[inline(always)] + pub fn nr(self) -> &'a mut W { + self.variant(HALT_A::NR) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 8)) | ((value as u32 & 0x03) << 8); + self.w + } +} +#[doc = "Fault B Capture Channel\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CHSEL_A { + #[doc = "0: Capture value stored in channel 0"] + CC0 = 0, + #[doc = "1: Capture value stored in channel 1"] + CC1 = 1, + #[doc = "2: Capture value stored in channel 2"] + CC2 = 2, + #[doc = "3: Capture value stored in channel 3"] + CC3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CHSEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `CHSEL` reader - Fault B Capture Channel"] +pub struct CHSEL_R(crate::FieldReader); +impl CHSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CHSEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CHSEL_A { + match self.bits { + 0 => CHSEL_A::CC0, + 1 => CHSEL_A::CC1, + 2 => CHSEL_A::CC2, + 3 => CHSEL_A::CC3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `CC0`"] + #[inline(always)] + pub fn is_cc0(&self) -> bool { + **self == CHSEL_A::CC0 + } + #[doc = "Checks if the value of the field is `CC1`"] + #[inline(always)] + pub fn is_cc1(&self) -> bool { + **self == CHSEL_A::CC1 + } + #[doc = "Checks if the value of the field is `CC2`"] + #[inline(always)] + pub fn is_cc2(&self) -> bool { + **self == CHSEL_A::CC2 + } + #[doc = "Checks if the value of the field is `CC3`"] + #[inline(always)] + pub fn is_cc3(&self) -> bool { + **self == CHSEL_A::CC3 + } +} +impl core::ops::Deref for CHSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHSEL` writer - Fault B Capture Channel"] +pub struct CHSEL_W<'a> { + w: &'a mut W, +} +impl<'a> CHSEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CHSEL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Capture value stored in channel 0"] + #[inline(always)] + pub fn cc0(self) -> &'a mut W { + self.variant(CHSEL_A::CC0) + } + #[doc = "Capture value stored in channel 1"] + #[inline(always)] + pub fn cc1(self) -> &'a mut W { + self.variant(CHSEL_A::CC1) + } + #[doc = "Capture value stored in channel 2"] + #[inline(always)] + pub fn cc2(self) -> &'a mut W { + self.variant(CHSEL_A::CC2) + } + #[doc = "Capture value stored in channel 3"] + #[inline(always)] + pub fn cc3(self) -> &'a mut W { + self.variant(CHSEL_A::CC3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 10)) | ((value as u32 & 0x03) << 10); + self.w + } +} +#[doc = "Fault B Capture Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CAPTURE_A { + #[doc = "0: No capture"] + DISABLE = 0, + #[doc = "1: Capture on fault"] + CAPT = 1, + #[doc = "2: Minimum capture"] + CAPTMIN = 2, + #[doc = "3: Maximum capture"] + CAPTMAX = 3, + #[doc = "4: Minimum local detection"] + LOCMIN = 4, + #[doc = "5: Maximum local detection"] + LOCMAX = 5, + #[doc = "6: Minimum and maximum local detection"] + DERIV0 = 6, + #[doc = "7: Capture with ramp index as MSB value"] + CAPTMARK = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CAPTURE_A) -> Self { + variant as _ + } +} +#[doc = "Field `CAPTURE` reader - Fault B Capture Action"] +pub struct CAPTURE_R(crate::FieldReader); +impl CAPTURE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CAPTURE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CAPTURE_A { + match self.bits { + 0 => CAPTURE_A::DISABLE, + 1 => CAPTURE_A::CAPT, + 2 => CAPTURE_A::CAPTMIN, + 3 => CAPTURE_A::CAPTMAX, + 4 => CAPTURE_A::LOCMIN, + 5 => CAPTURE_A::LOCMAX, + 6 => CAPTURE_A::DERIV0, + 7 => CAPTURE_A::CAPTMARK, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == CAPTURE_A::DISABLE + } + #[doc = "Checks if the value of the field is `CAPT`"] + #[inline(always)] + pub fn is_capt(&self) -> bool { + **self == CAPTURE_A::CAPT + } + #[doc = "Checks if the value of the field is `CAPTMIN`"] + #[inline(always)] + pub fn is_captmin(&self) -> bool { + **self == CAPTURE_A::CAPTMIN + } + #[doc = "Checks if the value of the field is `CAPTMAX`"] + #[inline(always)] + pub fn is_captmax(&self) -> bool { + **self == CAPTURE_A::CAPTMAX + } + #[doc = "Checks if the value of the field is `LOCMIN`"] + #[inline(always)] + pub fn is_locmin(&self) -> bool { + **self == CAPTURE_A::LOCMIN + } + #[doc = "Checks if the value of the field is `LOCMAX`"] + #[inline(always)] + pub fn is_locmax(&self) -> bool { + **self == CAPTURE_A::LOCMAX + } + #[doc = "Checks if the value of the field is `DERIV0`"] + #[inline(always)] + pub fn is_deriv0(&self) -> bool { + **self == CAPTURE_A::DERIV0 + } + #[doc = "Checks if the value of the field is `CAPTMARK`"] + #[inline(always)] + pub fn is_captmark(&self) -> bool { + **self == CAPTURE_A::CAPTMARK + } +} +impl core::ops::Deref for CAPTURE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAPTURE` writer - Fault B Capture Action"] +pub struct CAPTURE_W<'a> { + w: &'a mut W, +} +impl<'a> CAPTURE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CAPTURE_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "No capture"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(CAPTURE_A::DISABLE) + } + #[doc = "Capture on fault"] + #[inline(always)] + pub fn capt(self) -> &'a mut W { + self.variant(CAPTURE_A::CAPT) + } + #[doc = "Minimum capture"] + #[inline(always)] + pub fn captmin(self) -> &'a mut W { + self.variant(CAPTURE_A::CAPTMIN) + } + #[doc = "Maximum capture"] + #[inline(always)] + pub fn captmax(self) -> &'a mut W { + self.variant(CAPTURE_A::CAPTMAX) + } + #[doc = "Minimum local detection"] + #[inline(always)] + pub fn locmin(self) -> &'a mut W { + self.variant(CAPTURE_A::LOCMIN) + } + #[doc = "Maximum local detection"] + #[inline(always)] + pub fn locmax(self) -> &'a mut W { + self.variant(CAPTURE_A::LOCMAX) + } + #[doc = "Minimum and maximum local detection"] + #[inline(always)] + pub fn deriv0(self) -> &'a mut W { + self.variant(CAPTURE_A::DERIV0) + } + #[doc = "Capture with ramp index as MSB value"] + #[inline(always)] + pub fn captmark(self) -> &'a mut W { + self.variant(CAPTURE_A::CAPTMARK) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 12)) | ((value as u32 & 0x07) << 12); + self.w + } +} +#[doc = "Field `BLANKPRESC` reader - Fault B Blanking Prescaler"] +pub struct BLANKPRESC_R(crate::FieldReader); +impl BLANKPRESC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BLANKPRESC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BLANKPRESC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BLANKPRESC` writer - Fault B Blanking Prescaler"] +pub struct BLANKPRESC_W<'a> { + w: &'a mut W, +} +impl<'a> BLANKPRESC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `BLANKVAL` reader - Fault B Blanking Time"] +pub struct BLANKVAL_R(crate::FieldReader); +impl BLANKVAL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BLANKVAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BLANKVAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BLANKVAL` writer - Fault B Blanking Time"] +pub struct BLANKVAL_W<'a> { + w: &'a mut W, +} +impl<'a> BLANKVAL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +#[doc = "Field `FILTERVAL` reader - Fault B Filter Value"] +pub struct FILTERVAL_R(crate::FieldReader); +impl FILTERVAL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FILTERVAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FILTERVAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTERVAL` writer - Fault B Filter Value"] +pub struct FILTERVAL_W<'a> { + w: &'a mut W, +} +impl<'a> FILTERVAL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Fault B Source"] + #[inline(always)] + pub fn src(&self) -> SRC_R { + SRC_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bit 3 - Fault B Keeper"] + #[inline(always)] + pub fn keep(&self) -> KEEP_R { + KEEP_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Fault B Qualification"] + #[inline(always)] + pub fn qual(&self) -> QUAL_R { + QUAL_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bits 5:6 - Fault B Blanking Mode"] + #[inline(always)] + pub fn blank(&self) -> BLANK_R { + BLANK_R::new(((self.bits >> 5) & 0x03) as u8) + } + #[doc = "Bit 7 - Fault B Restart"] + #[inline(always)] + pub fn restart(&self) -> RESTART_R { + RESTART_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:9 - Fault B Halt Mode"] + #[inline(always)] + pub fn halt(&self) -> HALT_R { + HALT_R::new(((self.bits >> 8) & 0x03) as u8) + } + #[doc = "Bits 10:11 - Fault B Capture Channel"] + #[inline(always)] + pub fn chsel(&self) -> CHSEL_R { + CHSEL_R::new(((self.bits >> 10) & 0x03) as u8) + } + #[doc = "Bits 12:14 - Fault B Capture Action"] + #[inline(always)] + pub fn capture(&self) -> CAPTURE_R { + CAPTURE_R::new(((self.bits >> 12) & 0x07) as u8) + } + #[doc = "Bit 15 - Fault B Blanking Prescaler"] + #[inline(always)] + pub fn blankpresc(&self) -> BLANKPRESC_R { + BLANKPRESC_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:23 - Fault B Blanking Time"] + #[inline(always)] + pub fn blankval(&self) -> BLANKVAL_R { + BLANKVAL_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:27 - Fault B Filter Value"] + #[inline(always)] + pub fn filterval(&self) -> FILTERVAL_R { + FILTERVAL_R::new(((self.bits >> 24) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Fault B Source"] + #[inline(always)] + pub fn src(&mut self) -> SRC_W { + SRC_W { w: self } + } + #[doc = "Bit 3 - Fault B Keeper"] + #[inline(always)] + pub fn keep(&mut self) -> KEEP_W { + KEEP_W { w: self } + } + #[doc = "Bit 4 - Fault B Qualification"] + #[inline(always)] + pub fn qual(&mut self) -> QUAL_W { + QUAL_W { w: self } + } + #[doc = "Bits 5:6 - Fault B Blanking Mode"] + #[inline(always)] + pub fn blank(&mut self) -> BLANK_W { + BLANK_W { w: self } + } + #[doc = "Bit 7 - Fault B Restart"] + #[inline(always)] + pub fn restart(&mut self) -> RESTART_W { + RESTART_W { w: self } + } + #[doc = "Bits 8:9 - Fault B Halt Mode"] + #[inline(always)] + pub fn halt(&mut self) -> HALT_W { + HALT_W { w: self } + } + #[doc = "Bits 10:11 - Fault B Capture Channel"] + #[inline(always)] + pub fn chsel(&mut self) -> CHSEL_W { + CHSEL_W { w: self } + } + #[doc = "Bits 12:14 - Fault B Capture Action"] + #[inline(always)] + pub fn capture(&mut self) -> CAPTURE_W { + CAPTURE_W { w: self } + } + #[doc = "Bit 15 - Fault B Blanking Prescaler"] + #[inline(always)] + pub fn blankpresc(&mut self) -> BLANKPRESC_W { + BLANKPRESC_W { w: self } + } + #[doc = "Bits 16:23 - Fault B Blanking Time"] + #[inline(always)] + pub fn blankval(&mut self) -> BLANKVAL_W { + BLANKVAL_W { w: self } + } + #[doc = "Bits 24:27 - Fault B Filter Value"] + #[inline(always)] + pub fn filterval(&mut self) -> FILTERVAL_W { + FILTERVAL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Recoverable Fault B Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fctrlb](index.html) module"] +pub struct FCTRLB_SPEC; +impl crate::RegisterSpec for FCTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [fctrlb::R](R) reader structure"] +impl crate::Readable for FCTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [fctrlb::W](W) writer structure"] +impl crate::Writable for FCTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets FCTRLB to value 0"] +impl crate::Resettable for FCTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/tcc0/intenclr.rs b/pac/atsamc21n/src/tcc0/intenclr.rs new file mode 100644 index 000000000000..a227a8405a3c --- /dev/null +++ b/pac/atsamc21n/src/tcc0/intenclr.rs @@ -0,0 +1,724 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `TRG` reader - Retrigger Interrupt Enable"] +pub struct TRG_R(crate::FieldReader); +impl TRG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRG` writer - Retrigger Interrupt Enable"] +pub struct TRG_W<'a> { + w: &'a mut W, +} +impl<'a> TRG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CNT` reader - Counter Interrupt Enable"] +pub struct CNT_R(crate::FieldReader); +impl CNT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CNT` writer - Counter Interrupt Enable"] +pub struct CNT_W<'a> { + w: &'a mut W, +} +impl<'a> CNT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `ERR` reader - Error Interrupt Enable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - Error Interrupt Enable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `UFS` reader - Non-Recoverable Update Fault Interrupt Enable"] +pub struct UFS_R(crate::FieldReader); +impl UFS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UFS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for UFS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `UFS` writer - Non-Recoverable Update Fault Interrupt Enable"] +pub struct UFS_W<'a> { + w: &'a mut W, +} +impl<'a> UFS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `DFS` reader - Non-Recoverable Debug Fault Interrupt Enable"] +pub struct DFS_R(crate::FieldReader); +impl DFS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFS` writer - Non-Recoverable Debug Fault Interrupt Enable"] +pub struct DFS_W<'a> { + w: &'a mut W, +} +impl<'a> DFS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `FAULTA` reader - Recoverable Fault A Interrupt Enable"] +pub struct FAULTA_R(crate::FieldReader); +impl FAULTA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTA` writer - Recoverable Fault A Interrupt Enable"] +pub struct FAULTA_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `FAULTB` reader - Recoverable Fault B Interrupt Enable"] +pub struct FAULTB_R(crate::FieldReader); +impl FAULTB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTB` writer - Recoverable Fault B Interrupt Enable"] +pub struct FAULTB_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `FAULT0` reader - Non-Recoverable Fault 0 Interrupt Enable"] +pub struct FAULT0_R(crate::FieldReader); +impl FAULT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT0` writer - Non-Recoverable Fault 0 Interrupt Enable"] +pub struct FAULT0_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `FAULT1` reader - Non-Recoverable Fault 1 Interrupt Enable"] +pub struct FAULT1_R(crate::FieldReader); +impl FAULT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT1` writer - Non-Recoverable Fault 1 Interrupt Enable"] +pub struct FAULT1_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `MC0` reader - Match or Capture Channel 0 Interrupt Enable"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - Match or Capture Channel 0 Interrupt Enable"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `MC1` reader - Match or Capture Channel 1 Interrupt Enable"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - Match or Capture Channel 1 Interrupt Enable"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `MC2` reader - Match or Capture Channel 2 Interrupt Enable"] +pub struct MC2_R(crate::FieldReader); +impl MC2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC2` writer - Match or Capture Channel 2 Interrupt Enable"] +pub struct MC2_W<'a> { + w: &'a mut W, +} +impl<'a> MC2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `MC3` reader - Match or Capture Channel 3 Interrupt Enable"] +pub struct MC3_R(crate::FieldReader); +impl MC3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC3` writer - Match or Capture Channel 3 Interrupt Enable"] +pub struct MC3_W<'a> { + w: &'a mut W, +} +impl<'a> MC3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +impl R { + #[doc = "Bit 0 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Retrigger Interrupt Enable"] + #[inline(always)] + pub fn trg(&self) -> TRG_R { + TRG_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Counter Interrupt Enable"] + #[inline(always)] + pub fn cnt(&self) -> CNT_R { + CNT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Error Interrupt Enable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 10 - Non-Recoverable Update Fault Interrupt Enable"] + #[inline(always)] + pub fn ufs(&self) -> UFS_R { + UFS_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Non-Recoverable Debug Fault Interrupt Enable"] + #[inline(always)] + pub fn dfs(&self) -> DFS_R { + DFS_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Recoverable Fault A Interrupt Enable"] + #[inline(always)] + pub fn faulta(&self) -> FAULTA_R { + FAULTA_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Recoverable Fault B Interrupt Enable"] + #[inline(always)] + pub fn faultb(&self) -> FAULTB_R { + FAULTB_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Non-Recoverable Fault 0 Interrupt Enable"] + #[inline(always)] + pub fn fault0(&self) -> FAULT0_R { + FAULT0_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Non-Recoverable Fault 1 Interrupt Enable"] + #[inline(always)] + pub fn fault1(&self) -> FAULT1_R { + FAULT1_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Match or Capture Channel 0 Interrupt Enable"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Match or Capture Channel 1 Interrupt Enable"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Match or Capture Channel 2 Interrupt Enable"] + #[inline(always)] + pub fn mc2(&self) -> MC2_R { + MC2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Match or Capture Channel 3 Interrupt Enable"] + #[inline(always)] + pub fn mc3(&self) -> MC3_R { + MC3_R::new(((self.bits >> 19) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - Retrigger Interrupt Enable"] + #[inline(always)] + pub fn trg(&mut self) -> TRG_W { + TRG_W { w: self } + } + #[doc = "Bit 2 - Counter Interrupt Enable"] + #[inline(always)] + pub fn cnt(&mut self) -> CNT_W { + CNT_W { w: self } + } + #[doc = "Bit 3 - Error Interrupt Enable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 10 - Non-Recoverable Update Fault Interrupt Enable"] + #[inline(always)] + pub fn ufs(&mut self) -> UFS_W { + UFS_W { w: self } + } + #[doc = "Bit 11 - Non-Recoverable Debug Fault Interrupt Enable"] + #[inline(always)] + pub fn dfs(&mut self) -> DFS_W { + DFS_W { w: self } + } + #[doc = "Bit 12 - Recoverable Fault A Interrupt Enable"] + #[inline(always)] + pub fn faulta(&mut self) -> FAULTA_W { + FAULTA_W { w: self } + } + #[doc = "Bit 13 - Recoverable Fault B Interrupt Enable"] + #[inline(always)] + pub fn faultb(&mut self) -> FAULTB_W { + FAULTB_W { w: self } + } + #[doc = "Bit 14 - Non-Recoverable Fault 0 Interrupt Enable"] + #[inline(always)] + pub fn fault0(&mut self) -> FAULT0_W { + FAULT0_W { w: self } + } + #[doc = "Bit 15 - Non-Recoverable Fault 1 Interrupt Enable"] + #[inline(always)] + pub fn fault1(&mut self) -> FAULT1_W { + FAULT1_W { w: self } + } + #[doc = "Bit 16 - Match or Capture Channel 0 Interrupt Enable"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 17 - Match or Capture Channel 1 Interrupt Enable"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Bit 18 - Match or Capture Channel 2 Interrupt Enable"] + #[inline(always)] + pub fn mc2(&mut self) -> MC2_W { + MC2_W { w: self } + } + #[doc = "Bit 19 - Match or Capture Channel 3 Interrupt Enable"] + #[inline(always)] + pub fn mc3(&mut self) -> MC3_W { + MC3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/tcc0/intenset.rs b/pac/atsamc21n/src/tcc0/intenset.rs new file mode 100644 index 000000000000..0125a220bd02 --- /dev/null +++ b/pac/atsamc21n/src/tcc0/intenset.rs @@ -0,0 +1,724 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `TRG` reader - Retrigger Interrupt Enable"] +pub struct TRG_R(crate::FieldReader); +impl TRG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRG` writer - Retrigger Interrupt Enable"] +pub struct TRG_W<'a> { + w: &'a mut W, +} +impl<'a> TRG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CNT` reader - Counter Interrupt Enable"] +pub struct CNT_R(crate::FieldReader); +impl CNT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CNT` writer - Counter Interrupt Enable"] +pub struct CNT_W<'a> { + w: &'a mut W, +} +impl<'a> CNT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `ERR` reader - Error Interrupt Enable"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - Error Interrupt Enable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `UFS` reader - Non-Recoverable Update Fault Interrupt Enable"] +pub struct UFS_R(crate::FieldReader); +impl UFS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UFS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for UFS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `UFS` writer - Non-Recoverable Update Fault Interrupt Enable"] +pub struct UFS_W<'a> { + w: &'a mut W, +} +impl<'a> UFS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `DFS` reader - Non-Recoverable Debug Fault Interrupt Enable"] +pub struct DFS_R(crate::FieldReader); +impl DFS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFS` writer - Non-Recoverable Debug Fault Interrupt Enable"] +pub struct DFS_W<'a> { + w: &'a mut W, +} +impl<'a> DFS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `FAULTA` reader - Recoverable Fault A Interrupt Enable"] +pub struct FAULTA_R(crate::FieldReader); +impl FAULTA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTA` writer - Recoverable Fault A Interrupt Enable"] +pub struct FAULTA_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `FAULTB` reader - Recoverable Fault B Interrupt Enable"] +pub struct FAULTB_R(crate::FieldReader); +impl FAULTB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTB` writer - Recoverable Fault B Interrupt Enable"] +pub struct FAULTB_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `FAULT0` reader - Non-Recoverable Fault 0 Interrupt Enable"] +pub struct FAULT0_R(crate::FieldReader); +impl FAULT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT0` writer - Non-Recoverable Fault 0 Interrupt Enable"] +pub struct FAULT0_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `FAULT1` reader - Non-Recoverable Fault 1 Interrupt Enable"] +pub struct FAULT1_R(crate::FieldReader); +impl FAULT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT1` writer - Non-Recoverable Fault 1 Interrupt Enable"] +pub struct FAULT1_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `MC0` reader - Match or Capture Channel 0 Interrupt Enable"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - Match or Capture Channel 0 Interrupt Enable"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `MC1` reader - Match or Capture Channel 1 Interrupt Enable"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - Match or Capture Channel 1 Interrupt Enable"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `MC2` reader - Match or Capture Channel 2 Interrupt Enable"] +pub struct MC2_R(crate::FieldReader); +impl MC2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC2` writer - Match or Capture Channel 2 Interrupt Enable"] +pub struct MC2_W<'a> { + w: &'a mut W, +} +impl<'a> MC2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `MC3` reader - Match or Capture Channel 3 Interrupt Enable"] +pub struct MC3_R(crate::FieldReader); +impl MC3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC3` writer - Match or Capture Channel 3 Interrupt Enable"] +pub struct MC3_W<'a> { + w: &'a mut W, +} +impl<'a> MC3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +impl R { + #[doc = "Bit 0 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Retrigger Interrupt Enable"] + #[inline(always)] + pub fn trg(&self) -> TRG_R { + TRG_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Counter Interrupt Enable"] + #[inline(always)] + pub fn cnt(&self) -> CNT_R { + CNT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Error Interrupt Enable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 10 - Non-Recoverable Update Fault Interrupt Enable"] + #[inline(always)] + pub fn ufs(&self) -> UFS_R { + UFS_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Non-Recoverable Debug Fault Interrupt Enable"] + #[inline(always)] + pub fn dfs(&self) -> DFS_R { + DFS_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Recoverable Fault A Interrupt Enable"] + #[inline(always)] + pub fn faulta(&self) -> FAULTA_R { + FAULTA_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Recoverable Fault B Interrupt Enable"] + #[inline(always)] + pub fn faultb(&self) -> FAULTB_R { + FAULTB_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Non-Recoverable Fault 0 Interrupt Enable"] + #[inline(always)] + pub fn fault0(&self) -> FAULT0_R { + FAULT0_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Non-Recoverable Fault 1 Interrupt Enable"] + #[inline(always)] + pub fn fault1(&self) -> FAULT1_R { + FAULT1_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Match or Capture Channel 0 Interrupt Enable"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Match or Capture Channel 1 Interrupt Enable"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Match or Capture Channel 2 Interrupt Enable"] + #[inline(always)] + pub fn mc2(&self) -> MC2_R { + MC2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Match or Capture Channel 3 Interrupt Enable"] + #[inline(always)] + pub fn mc3(&self) -> MC3_R { + MC3_R::new(((self.bits >> 19) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - Retrigger Interrupt Enable"] + #[inline(always)] + pub fn trg(&mut self) -> TRG_W { + TRG_W { w: self } + } + #[doc = "Bit 2 - Counter Interrupt Enable"] + #[inline(always)] + pub fn cnt(&mut self) -> CNT_W { + CNT_W { w: self } + } + #[doc = "Bit 3 - Error Interrupt Enable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 10 - Non-Recoverable Update Fault Interrupt Enable"] + #[inline(always)] + pub fn ufs(&mut self) -> UFS_W { + UFS_W { w: self } + } + #[doc = "Bit 11 - Non-Recoverable Debug Fault Interrupt Enable"] + #[inline(always)] + pub fn dfs(&mut self) -> DFS_W { + DFS_W { w: self } + } + #[doc = "Bit 12 - Recoverable Fault A Interrupt Enable"] + #[inline(always)] + pub fn faulta(&mut self) -> FAULTA_W { + FAULTA_W { w: self } + } + #[doc = "Bit 13 - Recoverable Fault B Interrupt Enable"] + #[inline(always)] + pub fn faultb(&mut self) -> FAULTB_W { + FAULTB_W { w: self } + } + #[doc = "Bit 14 - Non-Recoverable Fault 0 Interrupt Enable"] + #[inline(always)] + pub fn fault0(&mut self) -> FAULT0_W { + FAULT0_W { w: self } + } + #[doc = "Bit 15 - Non-Recoverable Fault 1 Interrupt Enable"] + #[inline(always)] + pub fn fault1(&mut self) -> FAULT1_W { + FAULT1_W { w: self } + } + #[doc = "Bit 16 - Match or Capture Channel 0 Interrupt Enable"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 17 - Match or Capture Channel 1 Interrupt Enable"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Bit 18 - Match or Capture Channel 2 Interrupt Enable"] + #[inline(always)] + pub fn mc2(&mut self) -> MC2_W { + MC2_W { w: self } + } + #[doc = "Bit 19 - Match or Capture Channel 3 Interrupt Enable"] + #[inline(always)] + pub fn mc3(&mut self) -> MC3_W { + MC3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/tcc0/intflag.rs b/pac/atsamc21n/src/tcc0/intflag.rs new file mode 100644 index 000000000000..b2d5088f4087 --- /dev/null +++ b/pac/atsamc21n/src/tcc0/intflag.rs @@ -0,0 +1,724 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - Overflow"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `TRG` reader - Retrigger"] +pub struct TRG_R(crate::FieldReader); +impl TRG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRG` writer - Retrigger"] +pub struct TRG_W<'a> { + w: &'a mut W, +} +impl<'a> TRG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CNT` reader - Counter"] +pub struct CNT_R(crate::FieldReader); +impl CNT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CNT` writer - Counter"] +pub struct CNT_W<'a> { + w: &'a mut W, +} +impl<'a> CNT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `ERR` reader - Error"] +pub struct ERR_R(crate::FieldReader); +impl ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - Error"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `UFS` reader - Non-Recoverable Update Fault"] +pub struct UFS_R(crate::FieldReader); +impl UFS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UFS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for UFS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `UFS` writer - Non-Recoverable Update Fault"] +pub struct UFS_W<'a> { + w: &'a mut W, +} +impl<'a> UFS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `DFS` reader - Non-Recoverable Debug Fault"] +pub struct DFS_R(crate::FieldReader); +impl DFS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFS` writer - Non-Recoverable Debug Fault"] +pub struct DFS_W<'a> { + w: &'a mut W, +} +impl<'a> DFS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `FAULTA` reader - Recoverable Fault A"] +pub struct FAULTA_R(crate::FieldReader); +impl FAULTA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTA` writer - Recoverable Fault A"] +pub struct FAULTA_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `FAULTB` reader - Recoverable Fault B"] +pub struct FAULTB_R(crate::FieldReader); +impl FAULTB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTB` writer - Recoverable Fault B"] +pub struct FAULTB_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `FAULT0` reader - Non-Recoverable Fault 0"] +pub struct FAULT0_R(crate::FieldReader); +impl FAULT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT0` writer - Non-Recoverable Fault 0"] +pub struct FAULT0_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `FAULT1` reader - Non-Recoverable Fault 1"] +pub struct FAULT1_R(crate::FieldReader); +impl FAULT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT1` writer - Non-Recoverable Fault 1"] +pub struct FAULT1_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `MC0` reader - Match or Capture 0"] +pub struct MC0_R(crate::FieldReader); +impl MC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - Match or Capture 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `MC1` reader - Match or Capture 1"] +pub struct MC1_R(crate::FieldReader); +impl MC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - Match or Capture 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `MC2` reader - Match or Capture 2"] +pub struct MC2_R(crate::FieldReader); +impl MC2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC2` writer - Match or Capture 2"] +pub struct MC2_W<'a> { + w: &'a mut W, +} +impl<'a> MC2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `MC3` reader - Match or Capture 3"] +pub struct MC3_R(crate::FieldReader); +impl MC3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MC3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC3` writer - Match or Capture 3"] +pub struct MC3_W<'a> { + w: &'a mut W, +} +impl<'a> MC3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +impl R { + #[doc = "Bit 0 - Overflow"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Retrigger"] + #[inline(always)] + pub fn trg(&self) -> TRG_R { + TRG_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Counter"] + #[inline(always)] + pub fn cnt(&self) -> CNT_R { + CNT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Error"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 10 - Non-Recoverable Update Fault"] + #[inline(always)] + pub fn ufs(&self) -> UFS_R { + UFS_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Non-Recoverable Debug Fault"] + #[inline(always)] + pub fn dfs(&self) -> DFS_R { + DFS_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Recoverable Fault A"] + #[inline(always)] + pub fn faulta(&self) -> FAULTA_R { + FAULTA_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Recoverable Fault B"] + #[inline(always)] + pub fn faultb(&self) -> FAULTB_R { + FAULTB_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Non-Recoverable Fault 0"] + #[inline(always)] + pub fn fault0(&self) -> FAULT0_R { + FAULT0_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Non-Recoverable Fault 1"] + #[inline(always)] + pub fn fault1(&self) -> FAULT1_R { + FAULT1_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Match or Capture 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Match or Capture 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Match or Capture 2"] + #[inline(always)] + pub fn mc2(&self) -> MC2_R { + MC2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Match or Capture 3"] + #[inline(always)] + pub fn mc3(&self) -> MC3_R { + MC3_R::new(((self.bits >> 19) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Overflow"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - Retrigger"] + #[inline(always)] + pub fn trg(&mut self) -> TRG_W { + TRG_W { w: self } + } + #[doc = "Bit 2 - Counter"] + #[inline(always)] + pub fn cnt(&mut self) -> CNT_W { + CNT_W { w: self } + } + #[doc = "Bit 3 - Error"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 10 - Non-Recoverable Update Fault"] + #[inline(always)] + pub fn ufs(&mut self) -> UFS_W { + UFS_W { w: self } + } + #[doc = "Bit 11 - Non-Recoverable Debug Fault"] + #[inline(always)] + pub fn dfs(&mut self) -> DFS_W { + DFS_W { w: self } + } + #[doc = "Bit 12 - Recoverable Fault A"] + #[inline(always)] + pub fn faulta(&mut self) -> FAULTA_W { + FAULTA_W { w: self } + } + #[doc = "Bit 13 - Recoverable Fault B"] + #[inline(always)] + pub fn faultb(&mut self) -> FAULTB_W { + FAULTB_W { w: self } + } + #[doc = "Bit 14 - Non-Recoverable Fault 0"] + #[inline(always)] + pub fn fault0(&mut self) -> FAULT0_W { + FAULT0_W { w: self } + } + #[doc = "Bit 15 - Non-Recoverable Fault 1"] + #[inline(always)] + pub fn fault1(&mut self) -> FAULT1_W { + FAULT1_W { w: self } + } + #[doc = "Bit 16 - Match or Capture 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 17 - Match or Capture 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Bit 18 - Match or Capture 2"] + #[inline(always)] + pub fn mc2(&mut self) -> MC2_W { + MC2_W { w: self } + } + #[doc = "Bit 19 - Match or Capture 3"] + #[inline(always)] + pub fn mc3(&mut self) -> MC3_W { + MC3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/tcc0/patt.rs b/pac/atsamc21n/src/tcc0/patt.rs new file mode 100644 index 000000000000..ea458642b182 --- /dev/null +++ b/pac/atsamc21n/src/tcc0/patt.rs @@ -0,0 +1,818 @@ +#[doc = "Register `PATT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PATT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PGE0` reader - Pattern Generator 0 Output Enable"] +pub struct PGE0_R(crate::FieldReader); +impl PGE0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGE0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGE0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGE0` writer - Pattern Generator 0 Output Enable"] +pub struct PGE0_W<'a> { + w: &'a mut W, +} +impl<'a> PGE0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PGE1` reader - Pattern Generator 1 Output Enable"] +pub struct PGE1_R(crate::FieldReader); +impl PGE1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGE1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGE1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGE1` writer - Pattern Generator 1 Output Enable"] +pub struct PGE1_W<'a> { + w: &'a mut W, +} +impl<'a> PGE1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PGE2` reader - Pattern Generator 2 Output Enable"] +pub struct PGE2_R(crate::FieldReader); +impl PGE2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGE2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGE2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGE2` writer - Pattern Generator 2 Output Enable"] +pub struct PGE2_W<'a> { + w: &'a mut W, +} +impl<'a> PGE2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PGE3` reader - Pattern Generator 3 Output Enable"] +pub struct PGE3_R(crate::FieldReader); +impl PGE3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGE3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGE3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGE3` writer - Pattern Generator 3 Output Enable"] +pub struct PGE3_W<'a> { + w: &'a mut W, +} +impl<'a> PGE3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PGE4` reader - Pattern Generator 4 Output Enable"] +pub struct PGE4_R(crate::FieldReader); +impl PGE4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGE4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGE4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGE4` writer - Pattern Generator 4 Output Enable"] +pub struct PGE4_W<'a> { + w: &'a mut W, +} +impl<'a> PGE4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PGE5` reader - Pattern Generator 5 Output Enable"] +pub struct PGE5_R(crate::FieldReader); +impl PGE5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGE5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGE5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGE5` writer - Pattern Generator 5 Output Enable"] +pub struct PGE5_W<'a> { + w: &'a mut W, +} +impl<'a> PGE5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PGE6` reader - Pattern Generator 6 Output Enable"] +pub struct PGE6_R(crate::FieldReader); +impl PGE6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGE6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGE6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGE6` writer - Pattern Generator 6 Output Enable"] +pub struct PGE6_W<'a> { + w: &'a mut W, +} +impl<'a> PGE6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PGE7` reader - Pattern Generator 7 Output Enable"] +pub struct PGE7_R(crate::FieldReader); +impl PGE7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGE7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGE7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGE7` writer - Pattern Generator 7 Output Enable"] +pub struct PGE7_W<'a> { + w: &'a mut W, +} +impl<'a> PGE7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `PGV0` reader - Pattern Generator 0 Output Value"] +pub struct PGV0_R(crate::FieldReader); +impl PGV0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGV0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGV0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGV0` writer - Pattern Generator 0 Output Value"] +pub struct PGV0_W<'a> { + w: &'a mut W, +} +impl<'a> PGV0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `PGV1` reader - Pattern Generator 1 Output Value"] +pub struct PGV1_R(crate::FieldReader); +impl PGV1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGV1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGV1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGV1` writer - Pattern Generator 1 Output Value"] +pub struct PGV1_W<'a> { + w: &'a mut W, +} +impl<'a> PGV1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `PGV2` reader - Pattern Generator 2 Output Value"] +pub struct PGV2_R(crate::FieldReader); +impl PGV2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGV2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGV2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGV2` writer - Pattern Generator 2 Output Value"] +pub struct PGV2_W<'a> { + w: &'a mut W, +} +impl<'a> PGV2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u16 & 0x01) << 10); + self.w + } +} +#[doc = "Field `PGV3` reader - Pattern Generator 3 Output Value"] +pub struct PGV3_R(crate::FieldReader); +impl PGV3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGV3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGV3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGV3` writer - Pattern Generator 3 Output Value"] +pub struct PGV3_W<'a> { + w: &'a mut W, +} +impl<'a> PGV3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u16 & 0x01) << 11); + self.w + } +} +#[doc = "Field `PGV4` reader - Pattern Generator 4 Output Value"] +pub struct PGV4_R(crate::FieldReader); +impl PGV4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGV4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGV4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGV4` writer - Pattern Generator 4 Output Value"] +pub struct PGV4_W<'a> { + w: &'a mut W, +} +impl<'a> PGV4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u16 & 0x01) << 12); + self.w + } +} +#[doc = "Field `PGV5` reader - Pattern Generator 5 Output Value"] +pub struct PGV5_R(crate::FieldReader); +impl PGV5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGV5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGV5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGV5` writer - Pattern Generator 5 Output Value"] +pub struct PGV5_W<'a> { + w: &'a mut W, +} +impl<'a> PGV5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u16 & 0x01) << 13); + self.w + } +} +#[doc = "Field `PGV6` reader - Pattern Generator 6 Output Value"] +pub struct PGV6_R(crate::FieldReader); +impl PGV6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGV6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGV6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGV6` writer - Pattern Generator 6 Output Value"] +pub struct PGV6_W<'a> { + w: &'a mut W, +} +impl<'a> PGV6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u16 & 0x01) << 14); + self.w + } +} +#[doc = "Field `PGV7` reader - Pattern Generator 7 Output Value"] +pub struct PGV7_R(crate::FieldReader); +impl PGV7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGV7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGV7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGV7` writer - Pattern Generator 7 Output Value"] +pub struct PGV7_W<'a> { + w: &'a mut W, +} +impl<'a> PGV7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Pattern Generator 0 Output Enable"] + #[inline(always)] + pub fn pge0(&self) -> PGE0_R { + PGE0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Pattern Generator 1 Output Enable"] + #[inline(always)] + pub fn pge1(&self) -> PGE1_R { + PGE1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Pattern Generator 2 Output Enable"] + #[inline(always)] + pub fn pge2(&self) -> PGE2_R { + PGE2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Pattern Generator 3 Output Enable"] + #[inline(always)] + pub fn pge3(&self) -> PGE3_R { + PGE3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Pattern Generator 4 Output Enable"] + #[inline(always)] + pub fn pge4(&self) -> PGE4_R { + PGE4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Pattern Generator 5 Output Enable"] + #[inline(always)] + pub fn pge5(&self) -> PGE5_R { + PGE5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Pattern Generator 6 Output Enable"] + #[inline(always)] + pub fn pge6(&self) -> PGE6_R { + PGE6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Pattern Generator 7 Output Enable"] + #[inline(always)] + pub fn pge7(&self) -> PGE7_R { + PGE7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Pattern Generator 0 Output Value"] + #[inline(always)] + pub fn pgv0(&self) -> PGV0_R { + PGV0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Pattern Generator 1 Output Value"] + #[inline(always)] + pub fn pgv1(&self) -> PGV1_R { + PGV1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Pattern Generator 2 Output Value"] + #[inline(always)] + pub fn pgv2(&self) -> PGV2_R { + PGV2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Pattern Generator 3 Output Value"] + #[inline(always)] + pub fn pgv3(&self) -> PGV3_R { + PGV3_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Pattern Generator 4 Output Value"] + #[inline(always)] + pub fn pgv4(&self) -> PGV4_R { + PGV4_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Pattern Generator 5 Output Value"] + #[inline(always)] + pub fn pgv5(&self) -> PGV5_R { + PGV5_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Pattern Generator 6 Output Value"] + #[inline(always)] + pub fn pgv6(&self) -> PGV6_R { + PGV6_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Pattern Generator 7 Output Value"] + #[inline(always)] + pub fn pgv7(&self) -> PGV7_R { + PGV7_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pattern Generator 0 Output Enable"] + #[inline(always)] + pub fn pge0(&mut self) -> PGE0_W { + PGE0_W { w: self } + } + #[doc = "Bit 1 - Pattern Generator 1 Output Enable"] + #[inline(always)] + pub fn pge1(&mut self) -> PGE1_W { + PGE1_W { w: self } + } + #[doc = "Bit 2 - Pattern Generator 2 Output Enable"] + #[inline(always)] + pub fn pge2(&mut self) -> PGE2_W { + PGE2_W { w: self } + } + #[doc = "Bit 3 - Pattern Generator 3 Output Enable"] + #[inline(always)] + pub fn pge3(&mut self) -> PGE3_W { + PGE3_W { w: self } + } + #[doc = "Bit 4 - Pattern Generator 4 Output Enable"] + #[inline(always)] + pub fn pge4(&mut self) -> PGE4_W { + PGE4_W { w: self } + } + #[doc = "Bit 5 - Pattern Generator 5 Output Enable"] + #[inline(always)] + pub fn pge5(&mut self) -> PGE5_W { + PGE5_W { w: self } + } + #[doc = "Bit 6 - Pattern Generator 6 Output Enable"] + #[inline(always)] + pub fn pge6(&mut self) -> PGE6_W { + PGE6_W { w: self } + } + #[doc = "Bit 7 - Pattern Generator 7 Output Enable"] + #[inline(always)] + pub fn pge7(&mut self) -> PGE7_W { + PGE7_W { w: self } + } + #[doc = "Bit 8 - Pattern Generator 0 Output Value"] + #[inline(always)] + pub fn pgv0(&mut self) -> PGV0_W { + PGV0_W { w: self } + } + #[doc = "Bit 9 - Pattern Generator 1 Output Value"] + #[inline(always)] + pub fn pgv1(&mut self) -> PGV1_W { + PGV1_W { w: self } + } + #[doc = "Bit 10 - Pattern Generator 2 Output Value"] + #[inline(always)] + pub fn pgv2(&mut self) -> PGV2_W { + PGV2_W { w: self } + } + #[doc = "Bit 11 - Pattern Generator 3 Output Value"] + #[inline(always)] + pub fn pgv3(&mut self) -> PGV3_W { + PGV3_W { w: self } + } + #[doc = "Bit 12 - Pattern Generator 4 Output Value"] + #[inline(always)] + pub fn pgv4(&mut self) -> PGV4_W { + PGV4_W { w: self } + } + #[doc = "Bit 13 - Pattern Generator 5 Output Value"] + #[inline(always)] + pub fn pgv5(&mut self) -> PGV5_W { + PGV5_W { w: self } + } + #[doc = "Bit 14 - Pattern Generator 6 Output Value"] + #[inline(always)] + pub fn pgv6(&mut self) -> PGV6_W { + PGV6_W { w: self } + } + #[doc = "Bit 15 - Pattern Generator 7 Output Value"] + #[inline(always)] + pub fn pgv7(&mut self) -> PGV7_W { + PGV7_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Pattern\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [patt](index.html) module"] +pub struct PATT_SPEC; +impl crate::RegisterSpec for PATT_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [patt::R](R) reader structure"] +impl crate::Readable for PATT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [patt::W](W) writer structure"] +impl crate::Writable for PATT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PATT to value 0"] +impl crate::Resettable for PATT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/tcc0/pattbuf.rs b/pac/atsamc21n/src/tcc0/pattbuf.rs new file mode 100644 index 000000000000..c9375e27645c --- /dev/null +++ b/pac/atsamc21n/src/tcc0/pattbuf.rs @@ -0,0 +1,818 @@ +#[doc = "Register `PATTBUF` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PATTBUF` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PGEB0` reader - Pattern Generator 0 Output Enable Buffer"] +pub struct PGEB0_R(crate::FieldReader); +impl PGEB0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGEB0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGEB0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGEB0` writer - Pattern Generator 0 Output Enable Buffer"] +pub struct PGEB0_W<'a> { + w: &'a mut W, +} +impl<'a> PGEB0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `PGEB1` reader - Pattern Generator 1 Output Enable Buffer"] +pub struct PGEB1_R(crate::FieldReader); +impl PGEB1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGEB1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGEB1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGEB1` writer - Pattern Generator 1 Output Enable Buffer"] +pub struct PGEB1_W<'a> { + w: &'a mut W, +} +impl<'a> PGEB1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PGEB2` reader - Pattern Generator 2 Output Enable Buffer"] +pub struct PGEB2_R(crate::FieldReader); +impl PGEB2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGEB2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGEB2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGEB2` writer - Pattern Generator 2 Output Enable Buffer"] +pub struct PGEB2_W<'a> { + w: &'a mut W, +} +impl<'a> PGEB2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PGEB3` reader - Pattern Generator 3 Output Enable Buffer"] +pub struct PGEB3_R(crate::FieldReader); +impl PGEB3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGEB3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGEB3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGEB3` writer - Pattern Generator 3 Output Enable Buffer"] +pub struct PGEB3_W<'a> { + w: &'a mut W, +} +impl<'a> PGEB3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PGEB4` reader - Pattern Generator 4 Output Enable Buffer"] +pub struct PGEB4_R(crate::FieldReader); +impl PGEB4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGEB4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGEB4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGEB4` writer - Pattern Generator 4 Output Enable Buffer"] +pub struct PGEB4_W<'a> { + w: &'a mut W, +} +impl<'a> PGEB4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PGEB5` reader - Pattern Generator 5 Output Enable Buffer"] +pub struct PGEB5_R(crate::FieldReader); +impl PGEB5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGEB5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGEB5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGEB5` writer - Pattern Generator 5 Output Enable Buffer"] +pub struct PGEB5_W<'a> { + w: &'a mut W, +} +impl<'a> PGEB5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PGEB6` reader - Pattern Generator 6 Output Enable Buffer"] +pub struct PGEB6_R(crate::FieldReader); +impl PGEB6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGEB6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGEB6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGEB6` writer - Pattern Generator 6 Output Enable Buffer"] +pub struct PGEB6_W<'a> { + w: &'a mut W, +} +impl<'a> PGEB6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PGEB7` reader - Pattern Generator 7 Output Enable Buffer"] +pub struct PGEB7_R(crate::FieldReader); +impl PGEB7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGEB7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGEB7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGEB7` writer - Pattern Generator 7 Output Enable Buffer"] +pub struct PGEB7_W<'a> { + w: &'a mut W, +} +impl<'a> PGEB7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `PGVB0` reader - Pattern Generator 0 Output Enable"] +pub struct PGVB0_R(crate::FieldReader); +impl PGVB0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGVB0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGVB0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGVB0` writer - Pattern Generator 0 Output Enable"] +pub struct PGVB0_W<'a> { + w: &'a mut W, +} +impl<'a> PGVB0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `PGVB1` reader - Pattern Generator 1 Output Enable"] +pub struct PGVB1_R(crate::FieldReader); +impl PGVB1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGVB1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGVB1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGVB1` writer - Pattern Generator 1 Output Enable"] +pub struct PGVB1_W<'a> { + w: &'a mut W, +} +impl<'a> PGVB1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `PGVB2` reader - Pattern Generator 2 Output Enable"] +pub struct PGVB2_R(crate::FieldReader); +impl PGVB2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGVB2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGVB2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGVB2` writer - Pattern Generator 2 Output Enable"] +pub struct PGVB2_W<'a> { + w: &'a mut W, +} +impl<'a> PGVB2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u16 & 0x01) << 10); + self.w + } +} +#[doc = "Field `PGVB3` reader - Pattern Generator 3 Output Enable"] +pub struct PGVB3_R(crate::FieldReader); +impl PGVB3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGVB3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGVB3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGVB3` writer - Pattern Generator 3 Output Enable"] +pub struct PGVB3_W<'a> { + w: &'a mut W, +} +impl<'a> PGVB3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u16 & 0x01) << 11); + self.w + } +} +#[doc = "Field `PGVB4` reader - Pattern Generator 4 Output Enable"] +pub struct PGVB4_R(crate::FieldReader); +impl PGVB4_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGVB4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGVB4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGVB4` writer - Pattern Generator 4 Output Enable"] +pub struct PGVB4_W<'a> { + w: &'a mut W, +} +impl<'a> PGVB4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u16 & 0x01) << 12); + self.w + } +} +#[doc = "Field `PGVB5` reader - Pattern Generator 5 Output Enable"] +pub struct PGVB5_R(crate::FieldReader); +impl PGVB5_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGVB5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGVB5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGVB5` writer - Pattern Generator 5 Output Enable"] +pub struct PGVB5_W<'a> { + w: &'a mut W, +} +impl<'a> PGVB5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u16 & 0x01) << 13); + self.w + } +} +#[doc = "Field `PGVB6` reader - Pattern Generator 6 Output Enable"] +pub struct PGVB6_R(crate::FieldReader); +impl PGVB6_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGVB6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGVB6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGVB6` writer - Pattern Generator 6 Output Enable"] +pub struct PGVB6_W<'a> { + w: &'a mut W, +} +impl<'a> PGVB6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u16 & 0x01) << 14); + self.w + } +} +#[doc = "Field `PGVB7` reader - Pattern Generator 7 Output Enable"] +pub struct PGVB7_R(crate::FieldReader); +impl PGVB7_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PGVB7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PGVB7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PGVB7` writer - Pattern Generator 7 Output Enable"] +pub struct PGVB7_W<'a> { + w: &'a mut W, +} +impl<'a> PGVB7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Pattern Generator 0 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb0(&self) -> PGEB0_R { + PGEB0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Pattern Generator 1 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb1(&self) -> PGEB1_R { + PGEB1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Pattern Generator 2 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb2(&self) -> PGEB2_R { + PGEB2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Pattern Generator 3 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb3(&self) -> PGEB3_R { + PGEB3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Pattern Generator 4 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb4(&self) -> PGEB4_R { + PGEB4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Pattern Generator 5 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb5(&self) -> PGEB5_R { + PGEB5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Pattern Generator 6 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb6(&self) -> PGEB6_R { + PGEB6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Pattern Generator 7 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb7(&self) -> PGEB7_R { + PGEB7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Pattern Generator 0 Output Enable"] + #[inline(always)] + pub fn pgvb0(&self) -> PGVB0_R { + PGVB0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Pattern Generator 1 Output Enable"] + #[inline(always)] + pub fn pgvb1(&self) -> PGVB1_R { + PGVB1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Pattern Generator 2 Output Enable"] + #[inline(always)] + pub fn pgvb2(&self) -> PGVB2_R { + PGVB2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Pattern Generator 3 Output Enable"] + #[inline(always)] + pub fn pgvb3(&self) -> PGVB3_R { + PGVB3_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Pattern Generator 4 Output Enable"] + #[inline(always)] + pub fn pgvb4(&self) -> PGVB4_R { + PGVB4_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Pattern Generator 5 Output Enable"] + #[inline(always)] + pub fn pgvb5(&self) -> PGVB5_R { + PGVB5_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Pattern Generator 6 Output Enable"] + #[inline(always)] + pub fn pgvb6(&self) -> PGVB6_R { + PGVB6_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Pattern Generator 7 Output Enable"] + #[inline(always)] + pub fn pgvb7(&self) -> PGVB7_R { + PGVB7_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pattern Generator 0 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb0(&mut self) -> PGEB0_W { + PGEB0_W { w: self } + } + #[doc = "Bit 1 - Pattern Generator 1 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb1(&mut self) -> PGEB1_W { + PGEB1_W { w: self } + } + #[doc = "Bit 2 - Pattern Generator 2 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb2(&mut self) -> PGEB2_W { + PGEB2_W { w: self } + } + #[doc = "Bit 3 - Pattern Generator 3 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb3(&mut self) -> PGEB3_W { + PGEB3_W { w: self } + } + #[doc = "Bit 4 - Pattern Generator 4 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb4(&mut self) -> PGEB4_W { + PGEB4_W { w: self } + } + #[doc = "Bit 5 - Pattern Generator 5 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb5(&mut self) -> PGEB5_W { + PGEB5_W { w: self } + } + #[doc = "Bit 6 - Pattern Generator 6 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb6(&mut self) -> PGEB6_W { + PGEB6_W { w: self } + } + #[doc = "Bit 7 - Pattern Generator 7 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb7(&mut self) -> PGEB7_W { + PGEB7_W { w: self } + } + #[doc = "Bit 8 - Pattern Generator 0 Output Enable"] + #[inline(always)] + pub fn pgvb0(&mut self) -> PGVB0_W { + PGVB0_W { w: self } + } + #[doc = "Bit 9 - Pattern Generator 1 Output Enable"] + #[inline(always)] + pub fn pgvb1(&mut self) -> PGVB1_W { + PGVB1_W { w: self } + } + #[doc = "Bit 10 - Pattern Generator 2 Output Enable"] + #[inline(always)] + pub fn pgvb2(&mut self) -> PGVB2_W { + PGVB2_W { w: self } + } + #[doc = "Bit 11 - Pattern Generator 3 Output Enable"] + #[inline(always)] + pub fn pgvb3(&mut self) -> PGVB3_W { + PGVB3_W { w: self } + } + #[doc = "Bit 12 - Pattern Generator 4 Output Enable"] + #[inline(always)] + pub fn pgvb4(&mut self) -> PGVB4_W { + PGVB4_W { w: self } + } + #[doc = "Bit 13 - Pattern Generator 5 Output Enable"] + #[inline(always)] + pub fn pgvb5(&mut self) -> PGVB5_W { + PGVB5_W { w: self } + } + #[doc = "Bit 14 - Pattern Generator 6 Output Enable"] + #[inline(always)] + pub fn pgvb6(&mut self) -> PGVB6_W { + PGVB6_W { w: self } + } + #[doc = "Bit 15 - Pattern Generator 7 Output Enable"] + #[inline(always)] + pub fn pgvb7(&mut self) -> PGVB7_W { + PGVB7_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Pattern Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pattbuf](index.html) module"] +pub struct PATTBUF_SPEC; +impl crate::RegisterSpec for PATTBUF_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [pattbuf::R](R) reader structure"] +impl crate::Readable for PATTBUF_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [pattbuf::W](W) writer structure"] +impl crate::Writable for PATTBUF_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PATTBUF to value 0"] +impl crate::Resettable for PATTBUF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/tcc0/per.rs b/pac/atsamc21n/src/tcc0/per.rs new file mode 100644 index 000000000000..9d8618631650 --- /dev/null +++ b/pac/atsamc21n/src/tcc0/per.rs @@ -0,0 +1,103 @@ +#[doc = "Register `PER` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PER` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER` reader - Period Value"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` writer - Period Value"] +pub struct PER_W<'a> { + w: &'a mut W, +} +impl<'a> PER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Period Value"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Period Value"] + #[inline(always)] + pub fn per(&mut self) -> PER_W { + PER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [per](index.html) module"] +pub struct PER_SPEC; +impl crate::RegisterSpec for PER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [per::R](R) reader structure"] +impl crate::Readable for PER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [per::W](W) writer structure"] +impl crate::Writable for PER_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PER to value 0xffff_ffff"] +impl crate::Resettable for PER_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pac/atsamc21n/src/tcc0/per_dith4_mode.rs b/pac/atsamc21n/src/tcc0/per_dith4_mode.rs new file mode 100644 index 000000000000..2f600552db84 --- /dev/null +++ b/pac/atsamc21n/src/tcc0/per_dith4_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PER_DITH4_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PER_DITH4_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHER` reader - Dithering Cycle Number"] +pub struct DITHER_R(crate::FieldReader); +impl DITHER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHER` writer - Dithering Cycle Number"] +pub struct DITHER_W<'a> { + w: &'a mut W, +} +impl<'a> DITHER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Field `PER` reader - Period Value"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` writer - Period Value"] +pub struct PER_W<'a> { + w: &'a mut W, +} +impl<'a> PER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x000f_ffff << 4)) | ((value as u32 & 0x000f_ffff) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&self) -> DITHER_R { + DITHER_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:23 - Period Value"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(((self.bits >> 4) & 0x000f_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:3 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&mut self) -> DITHER_W { + DITHER_W { w: self } + } + #[doc = "Bits 4:23 - Period Value"] + #[inline(always)] + pub fn per(&mut self) -> PER_W { + PER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [per_dith4_mode](index.html) module"] +pub struct PER_DITH4_MODE_SPEC; +impl crate::RegisterSpec for PER_DITH4_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [per_dith4_mode::R](R) reader structure"] +impl crate::Readable for PER_DITH4_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [per_dith4_mode::W](W) writer structure"] +impl crate::Writable for PER_DITH4_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PER_DITH4_MODE to value 0xffff_ffff"] +impl crate::Resettable for PER_DITH4_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pac/atsamc21n/src/tcc0/per_dith5_mode.rs b/pac/atsamc21n/src/tcc0/per_dith5_mode.rs new file mode 100644 index 000000000000..1906582e4c95 --- /dev/null +++ b/pac/atsamc21n/src/tcc0/per_dith5_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PER_DITH5_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PER_DITH5_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHER` reader - Dithering Cycle Number"] +pub struct DITHER_R(crate::FieldReader); +impl DITHER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHER` writer - Dithering Cycle Number"] +pub struct DITHER_W<'a> { + w: &'a mut W, +} +impl<'a> DITHER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f); + self.w + } +} +#[doc = "Field `PER` reader - Period Value"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` writer - Period Value"] +pub struct PER_W<'a> { + w: &'a mut W, +} +impl<'a> PER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0007_ffff << 5)) | ((value as u32 & 0x0007_ffff) << 5); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&self) -> DITHER_R { + DITHER_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:23 - Period Value"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(((self.bits >> 5) & 0x0007_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:4 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&mut self) -> DITHER_W { + DITHER_W { w: self } + } + #[doc = "Bits 5:23 - Period Value"] + #[inline(always)] + pub fn per(&mut self) -> PER_W { + PER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [per_dith5_mode](index.html) module"] +pub struct PER_DITH5_MODE_SPEC; +impl crate::RegisterSpec for PER_DITH5_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [per_dith5_mode::R](R) reader structure"] +impl crate::Readable for PER_DITH5_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [per_dith5_mode::W](W) writer structure"] +impl crate::Writable for PER_DITH5_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PER_DITH5_MODE to value 0xffff_ffff"] +impl crate::Resettable for PER_DITH5_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pac/atsamc21n/src/tcc0/per_dith6_mode.rs b/pac/atsamc21n/src/tcc0/per_dith6_mode.rs new file mode 100644 index 000000000000..67880e220a9c --- /dev/null +++ b/pac/atsamc21n/src/tcc0/per_dith6_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PER_DITH6_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PER_DITH6_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHER` reader - Dithering Cycle Number"] +pub struct DITHER_R(crate::FieldReader); +impl DITHER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHER` writer - Dithering Cycle Number"] +pub struct DITHER_W<'a> { + w: &'a mut W, +} +impl<'a> DITHER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +#[doc = "Field `PER` reader - Period Value"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` writer - Period Value"] +pub struct PER_W<'a> { + w: &'a mut W, +} +impl<'a> PER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0003_ffff << 6)) | ((value as u32 & 0x0003_ffff) << 6); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&self) -> DITHER_R { + DITHER_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:23 - Period Value"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(((self.bits >> 6) & 0x0003_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:5 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&mut self) -> DITHER_W { + DITHER_W { w: self } + } + #[doc = "Bits 6:23 - Period Value"] + #[inline(always)] + pub fn per(&mut self) -> PER_W { + PER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [per_dith6_mode](index.html) module"] +pub struct PER_DITH6_MODE_SPEC; +impl crate::RegisterSpec for PER_DITH6_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [per_dith6_mode::R](R) reader structure"] +impl crate::Readable for PER_DITH6_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [per_dith6_mode::W](W) writer structure"] +impl crate::Writable for PER_DITH6_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PER_DITH6_MODE to value 0xffff_ffff"] +impl crate::Resettable for PER_DITH6_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pac/atsamc21n/src/tcc0/perbuf.rs b/pac/atsamc21n/src/tcc0/perbuf.rs new file mode 100644 index 000000000000..169f17479616 --- /dev/null +++ b/pac/atsamc21n/src/tcc0/perbuf.rs @@ -0,0 +1,103 @@ +#[doc = "Register `PERBUF` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PERBUF` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PERBUF` reader - Period Buffer Value"] +pub struct PERBUF_R(crate::FieldReader); +impl PERBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + PERBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERBUF` writer - Period Buffer Value"] +pub struct PERBUF_W<'a> { + w: &'a mut W, +} +impl<'a> PERBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Period Buffer Value"] + #[inline(always)] + pub fn perbuf(&self) -> PERBUF_R { + PERBUF_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Period Buffer Value"] + #[inline(always)] + pub fn perbuf(&mut self) -> PERBUF_W { + PERBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [perbuf](index.html) module"] +pub struct PERBUF_SPEC; +impl crate::RegisterSpec for PERBUF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [perbuf::R](R) reader structure"] +impl crate::Readable for PERBUF_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [perbuf::W](W) writer structure"] +impl crate::Writable for PERBUF_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PERBUF to value 0xffff_ffff"] +impl crate::Resettable for PERBUF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pac/atsamc21n/src/tcc0/perbuf_dith4_mode.rs b/pac/atsamc21n/src/tcc0/perbuf_dith4_mode.rs new file mode 100644 index 000000000000..ccf96ecef185 --- /dev/null +++ b/pac/atsamc21n/src/tcc0/perbuf_dith4_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PERBUF_DITH4_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PERBUF_DITH4_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHERBUF` reader - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_R(crate::FieldReader); +impl DITHERBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHERBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHERBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHERBUF` writer - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_W<'a> { + w: &'a mut W, +} +impl<'a> DITHERBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Field `PERBUF` reader - Period Buffer Value"] +pub struct PERBUF_R(crate::FieldReader); +impl PERBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + PERBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERBUF` writer - Period Buffer Value"] +pub struct PERBUF_W<'a> { + w: &'a mut W, +} +impl<'a> PERBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x000f_ffff << 4)) | ((value as u32 & 0x000f_ffff) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&self) -> DITHERBUF_R { + DITHERBUF_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:23 - Period Buffer Value"] + #[inline(always)] + pub fn perbuf(&self) -> PERBUF_R { + PERBUF_R::new(((self.bits >> 4) & 0x000f_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:3 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&mut self) -> DITHERBUF_W { + DITHERBUF_W { w: self } + } + #[doc = "Bits 4:23 - Period Buffer Value"] + #[inline(always)] + pub fn perbuf(&mut self) -> PERBUF_W { + PERBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [perbuf_dith4_mode](index.html) module"] +pub struct PERBUF_DITH4_MODE_SPEC; +impl crate::RegisterSpec for PERBUF_DITH4_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [perbuf_dith4_mode::R](R) reader structure"] +impl crate::Readable for PERBUF_DITH4_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [perbuf_dith4_mode::W](W) writer structure"] +impl crate::Writable for PERBUF_DITH4_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PERBUF_DITH4_MODE to value 0xffff_ffff"] +impl crate::Resettable for PERBUF_DITH4_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pac/atsamc21n/src/tcc0/perbuf_dith5_mode.rs b/pac/atsamc21n/src/tcc0/perbuf_dith5_mode.rs new file mode 100644 index 000000000000..d55f6d52c5ba --- /dev/null +++ b/pac/atsamc21n/src/tcc0/perbuf_dith5_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PERBUF_DITH5_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PERBUF_DITH5_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHERBUF` reader - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_R(crate::FieldReader); +impl DITHERBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHERBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHERBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHERBUF` writer - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_W<'a> { + w: &'a mut W, +} +impl<'a> DITHERBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f); + self.w + } +} +#[doc = "Field `PERBUF` reader - Period Buffer Value"] +pub struct PERBUF_R(crate::FieldReader); +impl PERBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + PERBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERBUF` writer - Period Buffer Value"] +pub struct PERBUF_W<'a> { + w: &'a mut W, +} +impl<'a> PERBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0007_ffff << 5)) | ((value as u32 & 0x0007_ffff) << 5); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&self) -> DITHERBUF_R { + DITHERBUF_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:23 - Period Buffer Value"] + #[inline(always)] + pub fn perbuf(&self) -> PERBUF_R { + PERBUF_R::new(((self.bits >> 5) & 0x0007_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:4 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&mut self) -> DITHERBUF_W { + DITHERBUF_W { w: self } + } + #[doc = "Bits 5:23 - Period Buffer Value"] + #[inline(always)] + pub fn perbuf(&mut self) -> PERBUF_W { + PERBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [perbuf_dith5_mode](index.html) module"] +pub struct PERBUF_DITH5_MODE_SPEC; +impl crate::RegisterSpec for PERBUF_DITH5_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [perbuf_dith5_mode::R](R) reader structure"] +impl crate::Readable for PERBUF_DITH5_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [perbuf_dith5_mode::W](W) writer structure"] +impl crate::Writable for PERBUF_DITH5_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PERBUF_DITH5_MODE to value 0xffff_ffff"] +impl crate::Resettable for PERBUF_DITH5_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pac/atsamc21n/src/tcc0/perbuf_dith6_mode.rs b/pac/atsamc21n/src/tcc0/perbuf_dith6_mode.rs new file mode 100644 index 000000000000..983c849f9073 --- /dev/null +++ b/pac/atsamc21n/src/tcc0/perbuf_dith6_mode.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PERBUF_DITH6_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PERBUF_DITH6_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHERBUF` reader - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_R(crate::FieldReader); +impl DITHERBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DITHERBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DITHERBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DITHERBUF` writer - Dithering Buffer Cycle Number"] +pub struct DITHERBUF_W<'a> { + w: &'a mut W, +} +impl<'a> DITHERBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +#[doc = "Field `PERBUF` reader - Period Buffer Value"] +pub struct PERBUF_R(crate::FieldReader); +impl PERBUF_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + PERBUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERBUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERBUF` writer - Period Buffer Value"] +pub struct PERBUF_W<'a> { + w: &'a mut W, +} +impl<'a> PERBUF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0003_ffff << 6)) | ((value as u32 & 0x0003_ffff) << 6); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&self) -> DITHERBUF_R { + DITHERBUF_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:23 - Period Buffer Value"] + #[inline(always)] + pub fn perbuf(&self) -> PERBUF_R { + PERBUF_R::new(((self.bits >> 6) & 0x0003_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:5 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&mut self) -> DITHERBUF_W { + DITHERBUF_W { w: self } + } + #[doc = "Bits 6:23 - Period Buffer Value"] + #[inline(always)] + pub fn perbuf(&mut self) -> PERBUF_W { + PERBUF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [perbuf_dith6_mode](index.html) module"] +pub struct PERBUF_DITH6_MODE_SPEC; +impl crate::RegisterSpec for PERBUF_DITH6_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [perbuf_dith6_mode::R](R) reader structure"] +impl crate::Readable for PERBUF_DITH6_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [perbuf_dith6_mode::W](W) writer structure"] +impl crate::Writable for PERBUF_DITH6_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PERBUF_DITH6_MODE to value 0xffff_ffff"] +impl crate::Resettable for PERBUF_DITH6_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/pac/atsamc21n/src/tcc0/status.rs b/pac/atsamc21n/src/tcc0/status.rs new file mode 100644 index 000000000000..eecd909e6093 --- /dev/null +++ b/pac/atsamc21n/src/tcc0/status.rs @@ -0,0 +1,1147 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `STOP` reader - Stop"] +pub struct STOP_R(crate::FieldReader); +impl STOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STOP` writer - Stop"] +pub struct STOP_W<'a> { + w: &'a mut W, +} +impl<'a> STOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `IDX` reader - Ramp"] +pub struct IDX_R(crate::FieldReader); +impl IDX_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IDX_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IDX_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IDX` writer - Ramp"] +pub struct IDX_W<'a> { + w: &'a mut W, +} +impl<'a> IDX_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `UFS` reader - Non-recoverable Update Fault State"] +pub struct UFS_R(crate::FieldReader); +impl UFS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UFS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for UFS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `UFS` writer - Non-recoverable Update Fault State"] +pub struct UFS_W<'a> { + w: &'a mut W, +} +impl<'a> UFS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `DFS` reader - Non-Recoverable Debug Fault State"] +pub struct DFS_R(crate::FieldReader); +impl DFS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFS` writer - Non-Recoverable Debug Fault State"] +pub struct DFS_W<'a> { + w: &'a mut W, +} +impl<'a> DFS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `SLAVE` reader - Slave"] +pub struct SLAVE_R(crate::FieldReader); +impl SLAVE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SLAVE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SLAVE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SLAVE` writer - Slave"] +pub struct SLAVE_W<'a> { + w: &'a mut W, +} +impl<'a> SLAVE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `PATTBUFV` reader - Pattern Buffer Valid"] +pub struct PATTBUFV_R(crate::FieldReader); +impl PATTBUFV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PATTBUFV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PATTBUFV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PATTBUFV` writer - Pattern Buffer Valid"] +pub struct PATTBUFV_W<'a> { + w: &'a mut W, +} +impl<'a> PATTBUFV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PERBUFV` reader - Period Buffer Valid"] +pub struct PERBUFV_R(crate::FieldReader); +impl PERBUFV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PERBUFV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERBUFV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERBUFV` writer - Period Buffer Valid"] +pub struct PERBUFV_W<'a> { + w: &'a mut W, +} +impl<'a> PERBUFV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `FAULTAIN` reader - Recoverable Fault A Input"] +pub struct FAULTAIN_R(crate::FieldReader); +impl FAULTAIN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTAIN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTAIN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTAIN` writer - Recoverable Fault A Input"] +pub struct FAULTAIN_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTAIN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `FAULTBIN` reader - Recoverable Fault B Input"] +pub struct FAULTBIN_R(crate::FieldReader); +impl FAULTBIN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTBIN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTBIN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTBIN` writer - Recoverable Fault B Input"] +pub struct FAULTBIN_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTBIN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `FAULT0IN` reader - Non-Recoverable Fault0 Input"] +pub struct FAULT0IN_R(crate::FieldReader); +impl FAULT0IN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT0IN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT0IN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT0IN` writer - Non-Recoverable Fault0 Input"] +pub struct FAULT0IN_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT0IN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `FAULT1IN` reader - Non-Recoverable Fault1 Input"] +pub struct FAULT1IN_R(crate::FieldReader); +impl FAULT1IN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT1IN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT1IN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT1IN` writer - Non-Recoverable Fault1 Input"] +pub struct FAULT1IN_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT1IN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `FAULTA` reader - Recoverable Fault A State"] +pub struct FAULTA_R(crate::FieldReader); +impl FAULTA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTA` writer - Recoverable Fault A State"] +pub struct FAULTA_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `FAULTB` reader - Recoverable Fault B State"] +pub struct FAULTB_R(crate::FieldReader); +impl FAULTB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULTB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULTB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULTB` writer - Recoverable Fault B State"] +pub struct FAULTB_W<'a> { + w: &'a mut W, +} +impl<'a> FAULTB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `FAULT0` reader - Non-Recoverable Fault 0 State"] +pub struct FAULT0_R(crate::FieldReader); +impl FAULT0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT0` writer - Non-Recoverable Fault 0 State"] +pub struct FAULT0_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `FAULT1` reader - Non-Recoverable Fault 1 State"] +pub struct FAULT1_R(crate::FieldReader); +impl FAULT1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FAULT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FAULT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FAULT1` writer - Non-Recoverable Fault 1 State"] +pub struct FAULT1_W<'a> { + w: &'a mut W, +} +impl<'a> FAULT1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `CCBUFV0` reader - Compare Channel 0 Buffer Valid"] +pub struct CCBUFV0_R(crate::FieldReader); +impl CCBUFV0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBUFV0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUFV0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUFV0` writer - Compare Channel 0 Buffer Valid"] +pub struct CCBUFV0_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUFV0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `CCBUFV1` reader - Compare Channel 1 Buffer Valid"] +pub struct CCBUFV1_R(crate::FieldReader); +impl CCBUFV1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBUFV1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUFV1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUFV1` writer - Compare Channel 1 Buffer Valid"] +pub struct CCBUFV1_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUFV1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `CCBUFV2` reader - Compare Channel 2 Buffer Valid"] +pub struct CCBUFV2_R(crate::FieldReader); +impl CCBUFV2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBUFV2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUFV2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUFV2` writer - Compare Channel 2 Buffer Valid"] +pub struct CCBUFV2_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUFV2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `CCBUFV3` reader - Compare Channel 3 Buffer Valid"] +pub struct CCBUFV3_R(crate::FieldReader); +impl CCBUFV3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CCBUFV3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCBUFV3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCBUFV3` writer - Compare Channel 3 Buffer Valid"] +pub struct CCBUFV3_W<'a> { + w: &'a mut W, +} +impl<'a> CCBUFV3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `CMP0` reader - Compare Channel 0 Value"] +pub struct CMP0_R(crate::FieldReader); +impl CMP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP0` writer - Compare Channel 0 Value"] +pub struct CMP0_W<'a> { + w: &'a mut W, +} +impl<'a> CMP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `CMP1` reader - Compare Channel 1 Value"] +pub struct CMP1_R(crate::FieldReader); +impl CMP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP1` writer - Compare Channel 1 Value"] +pub struct CMP1_W<'a> { + w: &'a mut W, +} +impl<'a> CMP1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `CMP2` reader - Compare Channel 2 Value"] +pub struct CMP2_R(crate::FieldReader); +impl CMP2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP2` writer - Compare Channel 2 Value"] +pub struct CMP2_W<'a> { + w: &'a mut W, +} +impl<'a> CMP2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `CMP3` reader - Compare Channel 3 Value"] +pub struct CMP3_R(crate::FieldReader); +impl CMP3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CMP3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMP3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMP3` writer - Compare Channel 3 Value"] +pub struct CMP3_W<'a> { + w: &'a mut W, +} +impl<'a> CMP3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +impl R { + #[doc = "Bit 0 - Stop"] + #[inline(always)] + pub fn stop(&self) -> STOP_R { + STOP_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Ramp"] + #[inline(always)] + pub fn idx(&self) -> IDX_R { + IDX_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Non-recoverable Update Fault State"] + #[inline(always)] + pub fn ufs(&self) -> UFS_R { + UFS_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Non-Recoverable Debug Fault State"] + #[inline(always)] + pub fn dfs(&self) -> DFS_R { + DFS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Slave"] + #[inline(always)] + pub fn slave(&self) -> SLAVE_R { + SLAVE_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Pattern Buffer Valid"] + #[inline(always)] + pub fn pattbufv(&self) -> PATTBUFV_R { + PATTBUFV_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 7 - Period Buffer Valid"] + #[inline(always)] + pub fn perbufv(&self) -> PERBUFV_R { + PERBUFV_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Recoverable Fault A Input"] + #[inline(always)] + pub fn faultain(&self) -> FAULTAIN_R { + FAULTAIN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Recoverable Fault B Input"] + #[inline(always)] + pub fn faultbin(&self) -> FAULTBIN_R { + FAULTBIN_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Non-Recoverable Fault0 Input"] + #[inline(always)] + pub fn fault0in(&self) -> FAULT0IN_R { + FAULT0IN_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Non-Recoverable Fault1 Input"] + #[inline(always)] + pub fn fault1in(&self) -> FAULT1IN_R { + FAULT1IN_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Recoverable Fault A State"] + #[inline(always)] + pub fn faulta(&self) -> FAULTA_R { + FAULTA_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Recoverable Fault B State"] + #[inline(always)] + pub fn faultb(&self) -> FAULTB_R { + FAULTB_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Non-Recoverable Fault 0 State"] + #[inline(always)] + pub fn fault0(&self) -> FAULT0_R { + FAULT0_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Non-Recoverable Fault 1 State"] + #[inline(always)] + pub fn fault1(&self) -> FAULT1_R { + FAULT1_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Compare Channel 0 Buffer Valid"] + #[inline(always)] + pub fn ccbufv0(&self) -> CCBUFV0_R { + CCBUFV0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Compare Channel 1 Buffer Valid"] + #[inline(always)] + pub fn ccbufv1(&self) -> CCBUFV1_R { + CCBUFV1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Compare Channel 2 Buffer Valid"] + #[inline(always)] + pub fn ccbufv2(&self) -> CCBUFV2_R { + CCBUFV2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Compare Channel 3 Buffer Valid"] + #[inline(always)] + pub fn ccbufv3(&self) -> CCBUFV3_R { + CCBUFV3_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 24 - Compare Channel 0 Value"] + #[inline(always)] + pub fn cmp0(&self) -> CMP0_R { + CMP0_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Compare Channel 1 Value"] + #[inline(always)] + pub fn cmp1(&self) -> CMP1_R { + CMP1_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Compare Channel 2 Value"] + #[inline(always)] + pub fn cmp2(&self) -> CMP2_R { + CMP2_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Compare Channel 3 Value"] + #[inline(always)] + pub fn cmp3(&self) -> CMP3_R { + CMP3_R::new(((self.bits >> 27) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Stop"] + #[inline(always)] + pub fn stop(&mut self) -> STOP_W { + STOP_W { w: self } + } + #[doc = "Bit 1 - Ramp"] + #[inline(always)] + pub fn idx(&mut self) -> IDX_W { + IDX_W { w: self } + } + #[doc = "Bit 2 - Non-recoverable Update Fault State"] + #[inline(always)] + pub fn ufs(&mut self) -> UFS_W { + UFS_W { w: self } + } + #[doc = "Bit 3 - Non-Recoverable Debug Fault State"] + #[inline(always)] + pub fn dfs(&mut self) -> DFS_W { + DFS_W { w: self } + } + #[doc = "Bit 4 - Slave"] + #[inline(always)] + pub fn slave(&mut self) -> SLAVE_W { + SLAVE_W { w: self } + } + #[doc = "Bit 5 - Pattern Buffer Valid"] + #[inline(always)] + pub fn pattbufv(&mut self) -> PATTBUFV_W { + PATTBUFV_W { w: self } + } + #[doc = "Bit 7 - Period Buffer Valid"] + #[inline(always)] + pub fn perbufv(&mut self) -> PERBUFV_W { + PERBUFV_W { w: self } + } + #[doc = "Bit 8 - Recoverable Fault A Input"] + #[inline(always)] + pub fn faultain(&mut self) -> FAULTAIN_W { + FAULTAIN_W { w: self } + } + #[doc = "Bit 9 - Recoverable Fault B Input"] + #[inline(always)] + pub fn faultbin(&mut self) -> FAULTBIN_W { + FAULTBIN_W { w: self } + } + #[doc = "Bit 10 - Non-Recoverable Fault0 Input"] + #[inline(always)] + pub fn fault0in(&mut self) -> FAULT0IN_W { + FAULT0IN_W { w: self } + } + #[doc = "Bit 11 - Non-Recoverable Fault1 Input"] + #[inline(always)] + pub fn fault1in(&mut self) -> FAULT1IN_W { + FAULT1IN_W { w: self } + } + #[doc = "Bit 12 - Recoverable Fault A State"] + #[inline(always)] + pub fn faulta(&mut self) -> FAULTA_W { + FAULTA_W { w: self } + } + #[doc = "Bit 13 - Recoverable Fault B State"] + #[inline(always)] + pub fn faultb(&mut self) -> FAULTB_W { + FAULTB_W { w: self } + } + #[doc = "Bit 14 - Non-Recoverable Fault 0 State"] + #[inline(always)] + pub fn fault0(&mut self) -> FAULT0_W { + FAULT0_W { w: self } + } + #[doc = "Bit 15 - Non-Recoverable Fault 1 State"] + #[inline(always)] + pub fn fault1(&mut self) -> FAULT1_W { + FAULT1_W { w: self } + } + #[doc = "Bit 16 - Compare Channel 0 Buffer Valid"] + #[inline(always)] + pub fn ccbufv0(&mut self) -> CCBUFV0_W { + CCBUFV0_W { w: self } + } + #[doc = "Bit 17 - Compare Channel 1 Buffer Valid"] + #[inline(always)] + pub fn ccbufv1(&mut self) -> CCBUFV1_W { + CCBUFV1_W { w: self } + } + #[doc = "Bit 18 - Compare Channel 2 Buffer Valid"] + #[inline(always)] + pub fn ccbufv2(&mut self) -> CCBUFV2_W { + CCBUFV2_W { w: self } + } + #[doc = "Bit 19 - Compare Channel 3 Buffer Valid"] + #[inline(always)] + pub fn ccbufv3(&mut self) -> CCBUFV3_W { + CCBUFV3_W { w: self } + } + #[doc = "Bit 24 - Compare Channel 0 Value"] + #[inline(always)] + pub fn cmp0(&mut self) -> CMP0_W { + CMP0_W { w: self } + } + #[doc = "Bit 25 - Compare Channel 1 Value"] + #[inline(always)] + pub fn cmp1(&mut self) -> CMP1_W { + CMP1_W { w: self } + } + #[doc = "Bit 26 - Compare Channel 2 Value"] + #[inline(always)] + pub fn cmp2(&mut self) -> CMP2_W { + CMP2_W { w: self } + } + #[doc = "Bit 27 - Compare Channel 3 Value"] + #[inline(always)] + pub fn cmp3(&mut self) -> CMP3_W { + CMP3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0x01"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/pac/atsamc21n/src/tcc0/syncbusy.rs b/pac/atsamc21n/src/tcc0/syncbusy.rs new file mode 100644 index 000000000000..db0788c3f206 --- /dev/null +++ b/pac/atsamc21n/src/tcc0/syncbusy.rs @@ -0,0 +1,273 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Swrst Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - Enable Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLB` reader - Ctrlb Busy"] +pub struct CTRLB_R(crate::FieldReader); +impl CTRLB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTRLB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STATUS` reader - Status Busy"] +pub struct STATUS_R(crate::FieldReader); +impl STATUS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STATUS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STATUS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` reader - Count Busy"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PATT` reader - Pattern Busy"] +pub struct PATT_R(crate::FieldReader); +impl PATT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PATT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PATT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAVE` reader - Wave Busy"] +pub struct WAVE_R(crate::FieldReader); +impl WAVE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAVE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAVE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` reader - Period Busy"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC0` reader - Compare Channel 0 Busy"] +pub struct CC0_R(crate::FieldReader); +impl CC0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC1` reader - Compare Channel 1 Busy"] +pub struct CC1_R(crate::FieldReader); +impl CC1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC2` reader - Compare Channel 2 Busy"] +pub struct CC2_R(crate::FieldReader); +impl CC2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC3` reader - Compare Channel 3 Busy"] +pub struct CC3_R(crate::FieldReader); +impl CC3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Swrst Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Ctrlb Busy"] + #[inline(always)] + pub fn ctrlb(&self) -> CTRLB_R { + CTRLB_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Status Busy"] + #[inline(always)] + pub fn status(&self) -> STATUS_R { + STATUS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Count Busy"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Pattern Busy"] + #[inline(always)] + pub fn patt(&self) -> PATT_R { + PATT_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Wave Busy"] + #[inline(always)] + pub fn wave(&self) -> WAVE_R { + WAVE_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Period Busy"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Compare Channel 0 Busy"] + #[inline(always)] + pub fn cc0(&self) -> CC0_R { + CC0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Compare Channel 1 Busy"] + #[inline(always)] + pub fn cc1(&self) -> CC1_R { + CC1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Compare Channel 2 Busy"] + #[inline(always)] + pub fn cc2(&self) -> CC2_R { + CC2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Compare Channel 3 Busy"] + #[inline(always)] + pub fn cc3(&self) -> CC3_R { + CC3_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +#[doc = "Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/tcc0/wave.rs b/pac/atsamc21n/src/tcc0/wave.rs new file mode 100644 index 000000000000..8d092d429a91 --- /dev/null +++ b/pac/atsamc21n/src/tcc0/wave.rs @@ -0,0 +1,940 @@ +#[doc = "Register `WAVE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WAVE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Waveform Generation\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WAVEGEN_A { + #[doc = "0: Normal frequency"] + NFRQ = 0, + #[doc = "1: Match frequency"] + MFRQ = 1, + #[doc = "2: Normal PWM"] + NPWM = 2, + #[doc = "4: Dual-slope critical"] + DSCRITICAL = 4, + #[doc = "5: Dual-slope with interrupt/event condition when COUNT reaches ZERO"] + DSBOTTOM = 5, + #[doc = "6: Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP"] + DSBOTH = 6, + #[doc = "7: Dual-slope with interrupt/event condition when COUNT reaches TOP"] + DSTOP = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WAVEGEN_A) -> Self { + variant as _ + } +} +#[doc = "Field `WAVEGEN` reader - Waveform Generation"] +pub struct WAVEGEN_R(crate::FieldReader); +impl WAVEGEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WAVEGEN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(WAVEGEN_A::NFRQ), + 1 => Some(WAVEGEN_A::MFRQ), + 2 => Some(WAVEGEN_A::NPWM), + 4 => Some(WAVEGEN_A::DSCRITICAL), + 5 => Some(WAVEGEN_A::DSBOTTOM), + 6 => Some(WAVEGEN_A::DSBOTH), + 7 => Some(WAVEGEN_A::DSTOP), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NFRQ`"] + #[inline(always)] + pub fn is_nfrq(&self) -> bool { + **self == WAVEGEN_A::NFRQ + } + #[doc = "Checks if the value of the field is `MFRQ`"] + #[inline(always)] + pub fn is_mfrq(&self) -> bool { + **self == WAVEGEN_A::MFRQ + } + #[doc = "Checks if the value of the field is `NPWM`"] + #[inline(always)] + pub fn is_npwm(&self) -> bool { + **self == WAVEGEN_A::NPWM + } + #[doc = "Checks if the value of the field is `DSCRITICAL`"] + #[inline(always)] + pub fn is_dscritical(&self) -> bool { + **self == WAVEGEN_A::DSCRITICAL + } + #[doc = "Checks if the value of the field is `DSBOTTOM`"] + #[inline(always)] + pub fn is_dsbottom(&self) -> bool { + **self == WAVEGEN_A::DSBOTTOM + } + #[doc = "Checks if the value of the field is `DSBOTH`"] + #[inline(always)] + pub fn is_dsboth(&self) -> bool { + **self == WAVEGEN_A::DSBOTH + } + #[doc = "Checks if the value of the field is `DSTOP`"] + #[inline(always)] + pub fn is_dstop(&self) -> bool { + **self == WAVEGEN_A::DSTOP + } +} +impl core::ops::Deref for WAVEGEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAVEGEN` writer - Waveform Generation"] +pub struct WAVEGEN_W<'a> { + w: &'a mut W, +} +impl<'a> WAVEGEN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WAVEGEN_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Normal frequency"] + #[inline(always)] + pub fn nfrq(self) -> &'a mut W { + self.variant(WAVEGEN_A::NFRQ) + } + #[doc = "Match frequency"] + #[inline(always)] + pub fn mfrq(self) -> &'a mut W { + self.variant(WAVEGEN_A::MFRQ) + } + #[doc = "Normal PWM"] + #[inline(always)] + pub fn npwm(self) -> &'a mut W { + self.variant(WAVEGEN_A::NPWM) + } + #[doc = "Dual-slope critical"] + #[inline(always)] + pub fn dscritical(self) -> &'a mut W { + self.variant(WAVEGEN_A::DSCRITICAL) + } + #[doc = "Dual-slope with interrupt/event condition when COUNT reaches ZERO"] + #[inline(always)] + pub fn dsbottom(self) -> &'a mut W { + self.variant(WAVEGEN_A::DSBOTTOM) + } + #[doc = "Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP"] + #[inline(always)] + pub fn dsboth(self) -> &'a mut W { + self.variant(WAVEGEN_A::DSBOTH) + } + #[doc = "Dual-slope with interrupt/event condition when COUNT reaches TOP"] + #[inline(always)] + pub fn dstop(self) -> &'a mut W { + self.variant(WAVEGEN_A::DSTOP) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Ramp Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum RAMP_A { + #[doc = "0: RAMP1 operation"] + RAMP1 = 0, + #[doc = "1: Alternative RAMP2 operation"] + RAMP2A = 1, + #[doc = "2: RAMP2 operation"] + RAMP2 = 2, + #[doc = "3: Critical RAMP2 operation"] + RAMP2C = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RAMP_A) -> Self { + variant as _ + } +} +#[doc = "Field `RAMP` reader - Ramp Mode"] +pub struct RAMP_R(crate::FieldReader); +impl RAMP_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RAMP_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RAMP_A { + match self.bits { + 0 => RAMP_A::RAMP1, + 1 => RAMP_A::RAMP2A, + 2 => RAMP_A::RAMP2, + 3 => RAMP_A::RAMP2C, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `RAMP1`"] + #[inline(always)] + pub fn is_ramp1(&self) -> bool { + **self == RAMP_A::RAMP1 + } + #[doc = "Checks if the value of the field is `RAMP2A`"] + #[inline(always)] + pub fn is_ramp2a(&self) -> bool { + **self == RAMP_A::RAMP2A + } + #[doc = "Checks if the value of the field is `RAMP2`"] + #[inline(always)] + pub fn is_ramp2(&self) -> bool { + **self == RAMP_A::RAMP2 + } + #[doc = "Checks if the value of the field is `RAMP2C`"] + #[inline(always)] + pub fn is_ramp2c(&self) -> bool { + **self == RAMP_A::RAMP2C + } +} +impl core::ops::Deref for RAMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RAMP` writer - Ramp Mode"] +pub struct RAMP_W<'a> { + w: &'a mut W, +} +impl<'a> RAMP_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RAMP_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "RAMP1 operation"] + #[inline(always)] + pub fn ramp1(self) -> &'a mut W { + self.variant(RAMP_A::RAMP1) + } + #[doc = "Alternative RAMP2 operation"] + #[inline(always)] + pub fn ramp2a(self) -> &'a mut W { + self.variant(RAMP_A::RAMP2A) + } + #[doc = "RAMP2 operation"] + #[inline(always)] + pub fn ramp2(self) -> &'a mut W { + self.variant(RAMP_A::RAMP2) + } + #[doc = "Critical RAMP2 operation"] + #[inline(always)] + pub fn ramp2c(self) -> &'a mut W { + self.variant(RAMP_A::RAMP2C) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u32 & 0x03) << 4); + self.w + } +} +#[doc = "Field `CIPEREN` reader - Circular period Enable"] +pub struct CIPEREN_R(crate::FieldReader); +impl CIPEREN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CIPEREN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CIPEREN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CIPEREN` writer - Circular period Enable"] +pub struct CIPEREN_W<'a> { + w: &'a mut W, +} +impl<'a> CIPEREN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CICCEN0` reader - Circular Channel 0 Enable"] +pub struct CICCEN0_R(crate::FieldReader); +impl CICCEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CICCEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CICCEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CICCEN0` writer - Circular Channel 0 Enable"] +pub struct CICCEN0_W<'a> { + w: &'a mut W, +} +impl<'a> CICCEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `CICCEN1` reader - Circular Channel 1 Enable"] +pub struct CICCEN1_R(crate::FieldReader); +impl CICCEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CICCEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CICCEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CICCEN1` writer - Circular Channel 1 Enable"] +pub struct CICCEN1_W<'a> { + w: &'a mut W, +} +impl<'a> CICCEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `CICCEN2` reader - Circular Channel 2 Enable"] +pub struct CICCEN2_R(crate::FieldReader); +impl CICCEN2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CICCEN2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CICCEN2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CICCEN2` writer - Circular Channel 2 Enable"] +pub struct CICCEN2_W<'a> { + w: &'a mut W, +} +impl<'a> CICCEN2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `CICCEN3` reader - Circular Channel 3 Enable"] +pub struct CICCEN3_R(crate::FieldReader); +impl CICCEN3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CICCEN3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CICCEN3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CICCEN3` writer - Circular Channel 3 Enable"] +pub struct CICCEN3_W<'a> { + w: &'a mut W, +} +impl<'a> CICCEN3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `POL0` reader - Channel 0 Polarity"] +pub struct POL0_R(crate::FieldReader); +impl POL0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + POL0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for POL0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `POL0` writer - Channel 0 Polarity"] +pub struct POL0_W<'a> { + w: &'a mut W, +} +impl<'a> POL0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `POL1` reader - Channel 1 Polarity"] +pub struct POL1_R(crate::FieldReader); +impl POL1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + POL1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for POL1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `POL1` writer - Channel 1 Polarity"] +pub struct POL1_W<'a> { + w: &'a mut W, +} +impl<'a> POL1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `POL2` reader - Channel 2 Polarity"] +pub struct POL2_R(crate::FieldReader); +impl POL2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + POL2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for POL2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `POL2` writer - Channel 2 Polarity"] +pub struct POL2_W<'a> { + w: &'a mut W, +} +impl<'a> POL2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `POL3` reader - Channel 3 Polarity"] +pub struct POL3_R(crate::FieldReader); +impl POL3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + POL3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for POL3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `POL3` writer - Channel 3 Polarity"] +pub struct POL3_W<'a> { + w: &'a mut W, +} +impl<'a> POL3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `SWAP0` reader - Swap DTI Output Pair 0"] +pub struct SWAP0_R(crate::FieldReader); +impl SWAP0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWAP0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWAP0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWAP0` writer - Swap DTI Output Pair 0"] +pub struct SWAP0_W<'a> { + w: &'a mut W, +} +impl<'a> SWAP0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `SWAP1` reader - Swap DTI Output Pair 1"] +pub struct SWAP1_R(crate::FieldReader); +impl SWAP1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWAP1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWAP1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWAP1` writer - Swap DTI Output Pair 1"] +pub struct SWAP1_W<'a> { + w: &'a mut W, +} +impl<'a> SWAP1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `SWAP2` reader - Swap DTI Output Pair 2"] +pub struct SWAP2_R(crate::FieldReader); +impl SWAP2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWAP2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWAP2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWAP2` writer - Swap DTI Output Pair 2"] +pub struct SWAP2_W<'a> { + w: &'a mut W, +} +impl<'a> SWAP2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `SWAP3` reader - Swap DTI Output Pair 3"] +pub struct SWAP3_R(crate::FieldReader); +impl SWAP3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWAP3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWAP3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWAP3` writer - Swap DTI Output Pair 3"] +pub struct SWAP3_W<'a> { + w: &'a mut W, +} +impl<'a> SWAP3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Waveform Generation"] + #[inline(always)] + pub fn wavegen(&self) -> WAVEGEN_R { + WAVEGEN_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bits 4:5 - Ramp Mode"] + #[inline(always)] + pub fn ramp(&self) -> RAMP_R { + RAMP_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bit 7 - Circular period Enable"] + #[inline(always)] + pub fn ciperen(&self) -> CIPEREN_R { + CIPEREN_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Circular Channel 0 Enable"] + #[inline(always)] + pub fn ciccen0(&self) -> CICCEN0_R { + CICCEN0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Circular Channel 1 Enable"] + #[inline(always)] + pub fn ciccen1(&self) -> CICCEN1_R { + CICCEN1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Circular Channel 2 Enable"] + #[inline(always)] + pub fn ciccen2(&self) -> CICCEN2_R { + CICCEN2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Circular Channel 3 Enable"] + #[inline(always)] + pub fn ciccen3(&self) -> CICCEN3_R { + CICCEN3_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 16 - Channel 0 Polarity"] + #[inline(always)] + pub fn pol0(&self) -> POL0_R { + POL0_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Channel 1 Polarity"] + #[inline(always)] + pub fn pol1(&self) -> POL1_R { + POL1_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Channel 2 Polarity"] + #[inline(always)] + pub fn pol2(&self) -> POL2_R { + POL2_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Channel 3 Polarity"] + #[inline(always)] + pub fn pol3(&self) -> POL3_R { + POL3_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 24 - Swap DTI Output Pair 0"] + #[inline(always)] + pub fn swap0(&self) -> SWAP0_R { + SWAP0_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Swap DTI Output Pair 1"] + #[inline(always)] + pub fn swap1(&self) -> SWAP1_R { + SWAP1_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Swap DTI Output Pair 2"] + #[inline(always)] + pub fn swap2(&self) -> SWAP2_R { + SWAP2_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Swap DTI Output Pair 3"] + #[inline(always)] + pub fn swap3(&self) -> SWAP3_R { + SWAP3_R::new(((self.bits >> 27) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Waveform Generation"] + #[inline(always)] + pub fn wavegen(&mut self) -> WAVEGEN_W { + WAVEGEN_W { w: self } + } + #[doc = "Bits 4:5 - Ramp Mode"] + #[inline(always)] + pub fn ramp(&mut self) -> RAMP_W { + RAMP_W { w: self } + } + #[doc = "Bit 7 - Circular period Enable"] + #[inline(always)] + pub fn ciperen(&mut self) -> CIPEREN_W { + CIPEREN_W { w: self } + } + #[doc = "Bit 8 - Circular Channel 0 Enable"] + #[inline(always)] + pub fn ciccen0(&mut self) -> CICCEN0_W { + CICCEN0_W { w: self } + } + #[doc = "Bit 9 - Circular Channel 1 Enable"] + #[inline(always)] + pub fn ciccen1(&mut self) -> CICCEN1_W { + CICCEN1_W { w: self } + } + #[doc = "Bit 10 - Circular Channel 2 Enable"] + #[inline(always)] + pub fn ciccen2(&mut self) -> CICCEN2_W { + CICCEN2_W { w: self } + } + #[doc = "Bit 11 - Circular Channel 3 Enable"] + #[inline(always)] + pub fn ciccen3(&mut self) -> CICCEN3_W { + CICCEN3_W { w: self } + } + #[doc = "Bit 16 - Channel 0 Polarity"] + #[inline(always)] + pub fn pol0(&mut self) -> POL0_W { + POL0_W { w: self } + } + #[doc = "Bit 17 - Channel 1 Polarity"] + #[inline(always)] + pub fn pol1(&mut self) -> POL1_W { + POL1_W { w: self } + } + #[doc = "Bit 18 - Channel 2 Polarity"] + #[inline(always)] + pub fn pol2(&mut self) -> POL2_W { + POL2_W { w: self } + } + #[doc = "Bit 19 - Channel 3 Polarity"] + #[inline(always)] + pub fn pol3(&mut self) -> POL3_W { + POL3_W { w: self } + } + #[doc = "Bit 24 - Swap DTI Output Pair 0"] + #[inline(always)] + pub fn swap0(&mut self) -> SWAP0_W { + SWAP0_W { w: self } + } + #[doc = "Bit 25 - Swap DTI Output Pair 1"] + #[inline(always)] + pub fn swap1(&mut self) -> SWAP1_W { + SWAP1_W { w: self } + } + #[doc = "Bit 26 - Swap DTI Output Pair 2"] + #[inline(always)] + pub fn swap2(&mut self) -> SWAP2_W { + SWAP2_W { w: self } + } + #[doc = "Bit 27 - Swap DTI Output Pair 3"] + #[inline(always)] + pub fn swap3(&mut self) -> SWAP3_W { + SWAP3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Waveform Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wave](index.html) module"] +pub struct WAVE_SPEC; +impl crate::RegisterSpec for WAVE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [wave::R](R) reader structure"] +impl crate::Readable for WAVE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wave::W](W) writer structure"] +impl crate::Writable for WAVE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WAVE to value 0"] +impl crate::Resettable for WAVE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/tcc0/wexctrl.rs b/pac/atsamc21n/src/tcc0/wexctrl.rs new file mode 100644 index 000000000000..8eb0d29cbee5 --- /dev/null +++ b/pac/atsamc21n/src/tcc0/wexctrl.rs @@ -0,0 +1,365 @@ +#[doc = "Register `WEXCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WEXCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OTMX` reader - Output Matrix"] +pub struct OTMX_R(crate::FieldReader); +impl OTMX_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + OTMX_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OTMX_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OTMX` writer - Output Matrix"] +pub struct OTMX_W<'a> { + w: &'a mut W, +} +impl<'a> OTMX_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u32 & 0x03); + self.w + } +} +#[doc = "Field `DTIEN0` reader - Dead-time Insertion Generator 0 Enable"] +pub struct DTIEN0_R(crate::FieldReader); +impl DTIEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DTIEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DTIEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DTIEN0` writer - Dead-time Insertion Generator 0 Enable"] +pub struct DTIEN0_W<'a> { + w: &'a mut W, +} +impl<'a> DTIEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `DTIEN1` reader - Dead-time Insertion Generator 1 Enable"] +pub struct DTIEN1_R(crate::FieldReader); +impl DTIEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DTIEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DTIEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DTIEN1` writer - Dead-time Insertion Generator 1 Enable"] +pub struct DTIEN1_W<'a> { + w: &'a mut W, +} +impl<'a> DTIEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `DTIEN2` reader - Dead-time Insertion Generator 2 Enable"] +pub struct DTIEN2_R(crate::FieldReader); +impl DTIEN2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DTIEN2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DTIEN2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DTIEN2` writer - Dead-time Insertion Generator 2 Enable"] +pub struct DTIEN2_W<'a> { + w: &'a mut W, +} +impl<'a> DTIEN2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `DTIEN3` reader - Dead-time Insertion Generator 3 Enable"] +pub struct DTIEN3_R(crate::FieldReader); +impl DTIEN3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DTIEN3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DTIEN3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DTIEN3` writer - Dead-time Insertion Generator 3 Enable"] +pub struct DTIEN3_W<'a> { + w: &'a mut W, +} +impl<'a> DTIEN3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `DTLS` reader - Dead-time Low Side Outputs Value"] +pub struct DTLS_R(crate::FieldReader); +impl DTLS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DTLS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DTLS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DTLS` writer - Dead-time Low Side Outputs Value"] +pub struct DTLS_W<'a> { + w: &'a mut W, +} +impl<'a> DTLS_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +#[doc = "Field `DTHS` reader - Dead-time High Side Outputs Value"] +pub struct DTHS_R(crate::FieldReader); +impl DTHS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DTHS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DTHS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DTHS` writer - Dead-time High Side Outputs Value"] +pub struct DTHS_W<'a> { + w: &'a mut W, +} +impl<'a> DTHS_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 24)) | ((value as u32 & 0xff) << 24); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Output Matrix"] + #[inline(always)] + pub fn otmx(&self) -> OTMX_R { + OTMX_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bit 8 - Dead-time Insertion Generator 0 Enable"] + #[inline(always)] + pub fn dtien0(&self) -> DTIEN0_R { + DTIEN0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Dead-time Insertion Generator 1 Enable"] + #[inline(always)] + pub fn dtien1(&self) -> DTIEN1_R { + DTIEN1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Dead-time Insertion Generator 2 Enable"] + #[inline(always)] + pub fn dtien2(&self) -> DTIEN2_R { + DTIEN2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Dead-time Insertion Generator 3 Enable"] + #[inline(always)] + pub fn dtien3(&self) -> DTIEN3_R { + DTIEN3_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bits 16:23 - Dead-time Low Side Outputs Value"] + #[inline(always)] + pub fn dtls(&self) -> DTLS_R { + DTLS_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Dead-time High Side Outputs Value"] + #[inline(always)] + pub fn dths(&self) -> DTHS_R { + DTHS_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Output Matrix"] + #[inline(always)] + pub fn otmx(&mut self) -> OTMX_W { + OTMX_W { w: self } + } + #[doc = "Bit 8 - Dead-time Insertion Generator 0 Enable"] + #[inline(always)] + pub fn dtien0(&mut self) -> DTIEN0_W { + DTIEN0_W { w: self } + } + #[doc = "Bit 9 - Dead-time Insertion Generator 1 Enable"] + #[inline(always)] + pub fn dtien1(&mut self) -> DTIEN1_W { + DTIEN1_W { w: self } + } + #[doc = "Bit 10 - Dead-time Insertion Generator 2 Enable"] + #[inline(always)] + pub fn dtien2(&mut self) -> DTIEN2_W { + DTIEN2_W { w: self } + } + #[doc = "Bit 11 - Dead-time Insertion Generator 3 Enable"] + #[inline(always)] + pub fn dtien3(&mut self) -> DTIEN3_W { + DTIEN3_W { w: self } + } + #[doc = "Bits 16:23 - Dead-time Low Side Outputs Value"] + #[inline(always)] + pub fn dtls(&mut self) -> DTLS_W { + DTLS_W { w: self } + } + #[doc = "Bits 24:31 - Dead-time High Side Outputs Value"] + #[inline(always)] + pub fn dths(&mut self) -> DTHS_W { + DTHS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Waveform Extension Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wexctrl](index.html) module"] +pub struct WEXCTRL_SPEC; +impl crate::RegisterSpec for WEXCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [wexctrl::R](R) reader structure"] +impl crate::Readable for WEXCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wexctrl::W](W) writer structure"] +impl crate::Writable for WEXCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WEXCTRL to value 0"] +impl crate::Resettable for WEXCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/tsens.rs b/pac/atsamc21n/src/tsens.rs new file mode 100644 index 000000000000..3156dee6d87f --- /dev/null +++ b/pac/atsamc21n/src/tsens.rs @@ -0,0 +1,100 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control A Register"] + pub ctrla: crate::Reg, + #[doc = "0x01 - Control B Register"] + pub ctrlb: crate::Reg, + #[doc = "0x02 - Control C Register"] + pub ctrlc: crate::Reg, + #[doc = "0x03 - Event Control Register"] + pub evctrl: crate::Reg, + #[doc = "0x04 - Interrupt Enable Clear Register"] + pub intenclr: crate::Reg, + #[doc = "0x05 - Interrupt Enable Set Register"] + pub intenset: crate::Reg, + #[doc = "0x06 - Interrupt Flag Status and Clear Register"] + pub intflag: crate::Reg, + #[doc = "0x07 - Status Register"] + pub status: crate::Reg, + #[doc = "0x08 - Synchronization Busy Register"] + pub syncbusy: crate::Reg, + #[doc = "0x0c - Value Register"] + pub value: crate::Reg, + #[doc = "0x10 - Window Monitor Lower Threshold Register"] + pub winlt: crate::Reg, + #[doc = "0x14 - Window Monitor Upper Threshold Register"] + pub winut: crate::Reg, + #[doc = "0x18 - Gain Register"] + pub gain: crate::Reg, + #[doc = "0x1c - Offset Register"] + pub offset: crate::Reg, + #[doc = "0x20 - Calibration Register"] + pub cal: crate::Reg, + #[doc = "0x24 - Debug Control Register"] + pub dbgctrl: crate::Reg, +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A Register"] +pub mod ctrla; +#[doc = "CTRLB register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "Control B Register"] +pub mod ctrlb; +#[doc = "CTRLC register accessor: an alias for `Reg`"] +pub type CTRLC = crate::Reg; +#[doc = "Control C Register"] +pub mod ctrlc; +#[doc = "EVCTRL register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control Register"] +pub mod evctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear Register"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set Register"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear Register"] +pub mod intflag; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status Register"] +pub mod status; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Busy Register"] +pub mod syncbusy; +#[doc = "VALUE register accessor: an alias for `Reg`"] +pub type VALUE = crate::Reg; +#[doc = "Value Register"] +pub mod value; +#[doc = "WINLT register accessor: an alias for `Reg`"] +pub type WINLT = crate::Reg; +#[doc = "Window Monitor Lower Threshold Register"] +pub mod winlt; +#[doc = "WINUT register accessor: an alias for `Reg`"] +pub type WINUT = crate::Reg; +#[doc = "Window Monitor Upper Threshold Register"] +pub mod winut; +#[doc = "GAIN register accessor: an alias for `Reg`"] +pub type GAIN = crate::Reg; +#[doc = "Gain Register"] +pub mod gain; +#[doc = "OFFSET register accessor: an alias for `Reg`"] +pub type OFFSET = crate::Reg; +#[doc = "Offset Register"] +pub mod offset; +#[doc = "CAL register accessor: an alias for `Reg`"] +pub type CAL = crate::Reg; +#[doc = "Calibration Register"] +pub mod cal; +#[doc = "DBGCTRL register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control Register"] +pub mod dbgctrl; diff --git a/pac/atsamc21n/src/tsens/cal.rs b/pac/atsamc21n/src/tsens/cal.rs new file mode 100644 index 000000000000..9b0d76eef9eb --- /dev/null +++ b/pac/atsamc21n/src/tsens/cal.rs @@ -0,0 +1,140 @@ +#[doc = "Register `CAL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CAL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FCAL` reader - Frequency Calibration"] +pub struct FCAL_R(crate::FieldReader); +impl FCAL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FCAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FCAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FCAL` writer - Frequency Calibration"] +pub struct FCAL_W<'a> { + w: &'a mut W, +} +impl<'a> FCAL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +#[doc = "Field `TCAL` reader - Temperature Calibration"] +pub struct TCAL_R(crate::FieldReader); +impl TCAL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TCAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCAL` writer - Temperature Calibration"] +pub struct TCAL_W<'a> { + w: &'a mut W, +} +impl<'a> TCAL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 8)) | ((value as u32 & 0x3f) << 8); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Frequency Calibration"] + #[inline(always)] + pub fn fcal(&self) -> FCAL_R { + FCAL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 8:13 - Temperature Calibration"] + #[inline(always)] + pub fn tcal(&self) -> TCAL_R { + TCAL_R::new(((self.bits >> 8) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - Frequency Calibration"] + #[inline(always)] + pub fn fcal(&mut self) -> FCAL_W { + FCAL_W { w: self } + } + #[doc = "Bits 8:13 - Temperature Calibration"] + #[inline(always)] + pub fn tcal(&mut self) -> TCAL_W { + TCAL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Calibration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cal](index.html) module"] +pub struct CAL_SPEC; +impl crate::RegisterSpec for CAL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cal::R](R) reader structure"] +impl crate::Readable for CAL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cal::W](W) writer structure"] +impl crate::Writable for CAL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CAL to value 0"] +impl crate::Resettable for CAL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/tsens/ctrla.rs b/pac/atsamc21n/src/tsens/ctrla.rs new file mode 100644 index 000000000000..6be7f2fc82f2 --- /dev/null +++ b/pac/atsamc21n/src/tsens/ctrla.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/tsens/ctrlb.rs b/pac/atsamc21n/src/tsens/ctrlb.rs new file mode 100644 index 000000000000..7d350e71fbf3 --- /dev/null +++ b/pac/atsamc21n/src/tsens/ctrlb.rs @@ -0,0 +1,72 @@ +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `START` writer - Start Measurement"] +pub struct START_W<'a> { + w: &'a mut W, +} +impl<'a> START_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0 - Start Measurement"] + #[inline(always)] + pub fn start(&mut self) -> START_W { + START_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u8; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/tsens/ctrlc.rs b/pac/atsamc21n/src/tsens/ctrlc.rs new file mode 100644 index 000000000000..82390cea825d --- /dev/null +++ b/pac/atsamc21n/src/tsens/ctrlc.rs @@ -0,0 +1,264 @@ +#[doc = "Register `CTRLC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Window Monitor Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WINMODE_A { + #[doc = "0: No window mode (default)"] + DISABLE = 0, + #[doc = "1: VALUE greater than WINLT"] + ABOVE = 1, + #[doc = "2: VALUE less than WINUT"] + BELOW = 2, + #[doc = "3: VALUE greater than WINLT and VALUE less than WINUT"] + INSIDE = 3, + #[doc = "4: VALUE less than WINLT or VALUE greater than WINUT"] + OUTSIDE = 4, + #[doc = "5: VALUE greater than WINUT with hysteresis to WINLT"] + HYST_ABOVE = 5, + #[doc = "6: VALUE less than WINLST with hysteresis to WINUT"] + HYST_BELOW = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WINMODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `WINMODE` reader - Window Monitor Mode"] +pub struct WINMODE_R(crate::FieldReader); +impl WINMODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WINMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(WINMODE_A::DISABLE), + 1 => Some(WINMODE_A::ABOVE), + 2 => Some(WINMODE_A::BELOW), + 3 => Some(WINMODE_A::INSIDE), + 4 => Some(WINMODE_A::OUTSIDE), + 5 => Some(WINMODE_A::HYST_ABOVE), + 6 => Some(WINMODE_A::HYST_BELOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == WINMODE_A::DISABLE + } + #[doc = "Checks if the value of the field is `ABOVE`"] + #[inline(always)] + pub fn is_above(&self) -> bool { + **self == WINMODE_A::ABOVE + } + #[doc = "Checks if the value of the field is `BELOW`"] + #[inline(always)] + pub fn is_below(&self) -> bool { + **self == WINMODE_A::BELOW + } + #[doc = "Checks if the value of the field is `INSIDE`"] + #[inline(always)] + pub fn is_inside(&self) -> bool { + **self == WINMODE_A::INSIDE + } + #[doc = "Checks if the value of the field is `OUTSIDE`"] + #[inline(always)] + pub fn is_outside(&self) -> bool { + **self == WINMODE_A::OUTSIDE + } + #[doc = "Checks if the value of the field is `HYST_ABOVE`"] + #[inline(always)] + pub fn is_hyst_above(&self) -> bool { + **self == WINMODE_A::HYST_ABOVE + } + #[doc = "Checks if the value of the field is `HYST_BELOW`"] + #[inline(always)] + pub fn is_hyst_below(&self) -> bool { + **self == WINMODE_A::HYST_BELOW + } +} +impl core::ops::Deref for WINMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMODE` writer - Window Monitor Mode"] +pub struct WINMODE_W<'a> { + w: &'a mut W, +} +impl<'a> WINMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WINMODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No window mode (default)"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(WINMODE_A::DISABLE) + } + #[doc = "VALUE greater than WINLT"] + #[inline(always)] + pub fn above(self) -> &'a mut W { + self.variant(WINMODE_A::ABOVE) + } + #[doc = "VALUE less than WINUT"] + #[inline(always)] + pub fn below(self) -> &'a mut W { + self.variant(WINMODE_A::BELOW) + } + #[doc = "VALUE greater than WINLT and VALUE less than WINUT"] + #[inline(always)] + pub fn inside(self) -> &'a mut W { + self.variant(WINMODE_A::INSIDE) + } + #[doc = "VALUE less than WINLT or VALUE greater than WINUT"] + #[inline(always)] + pub fn outside(self) -> &'a mut W { + self.variant(WINMODE_A::OUTSIDE) + } + #[doc = "VALUE greater than WINUT with hysteresis to WINLT"] + #[inline(always)] + pub fn hyst_above(self) -> &'a mut W { + self.variant(WINMODE_A::HYST_ABOVE) + } + #[doc = "VALUE less than WINLST with hysteresis to WINUT"] + #[inline(always)] + pub fn hyst_below(self) -> &'a mut W { + self.variant(WINMODE_A::HYST_BELOW) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +#[doc = "Field `FREERUN` reader - Free Running Measurement"] +pub struct FREERUN_R(crate::FieldReader); +impl FREERUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FREERUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FREERUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FREERUN` writer - Free Running Measurement"] +pub struct FREERUN_W<'a> { + w: &'a mut W, +} +impl<'a> FREERUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Window Monitor Mode"] + #[inline(always)] + pub fn winmode(&self) -> WINMODE_R { + WINMODE_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 4 - Free Running Measurement"] + #[inline(always)] + pub fn freerun(&self) -> FREERUN_R { + FREERUN_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Window Monitor Mode"] + #[inline(always)] + pub fn winmode(&mut self) -> WINMODE_W { + WINMODE_W { w: self } + } + #[doc = "Bit 4 - Free Running Measurement"] + #[inline(always)] + pub fn freerun(&mut self) -> FREERUN_W { + FREERUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control C Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlc](index.html) module"] +pub struct CTRLC_SPEC; +impl crate::RegisterSpec for CTRLC_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlc::R](R) reader structure"] +impl crate::Readable for CTRLC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlc::W](W) writer structure"] +impl crate::Writable for CTRLC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLC to value 0"] +impl crate::Resettable for CTRLC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/tsens/dbgctrl.rs b/pac/atsamc21n/src/tsens/dbgctrl.rs new file mode 100644 index 000000000000..dd129a857202 --- /dev/null +++ b/pac/atsamc21n/src/tsens/dbgctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Debug Run"] +pub struct DBGRUN_R(crate::FieldReader); +impl DBGRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Debug Run"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/tsens/evctrl.rs b/pac/atsamc21n/src/tsens/evctrl.rs new file mode 100644 index 000000000000..20d0f3497e37 --- /dev/null +++ b/pac/atsamc21n/src/tsens/evctrl.rs @@ -0,0 +1,207 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `STARTEI` reader - Start Conversion Event Input Enable"] +pub struct STARTEI_R(crate::FieldReader); +impl STARTEI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STARTEI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STARTEI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STARTEI` writer - Start Conversion Event Input Enable"] +pub struct STARTEI_W<'a> { + w: &'a mut W, +} +impl<'a> STARTEI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `STARTINV` reader - Start Conversion Event Invert Enable"] +pub struct STARTINV_R(crate::FieldReader); +impl STARTINV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STARTINV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STARTINV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STARTINV` writer - Start Conversion Event Invert Enable"] +pub struct STARTINV_W<'a> { + w: &'a mut W, +} +impl<'a> STARTINV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WINEO` reader - Window Monitor Event Out"] +pub struct WINEO_R(crate::FieldReader); +impl WINEO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINEO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINEO` writer - Window Monitor Event Out"] +pub struct WINEO_W<'a> { + w: &'a mut W, +} +impl<'a> WINEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Start Conversion Event Input Enable"] + #[inline(always)] + pub fn startei(&self) -> STARTEI_R { + STARTEI_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Start Conversion Event Invert Enable"] + #[inline(always)] + pub fn startinv(&self) -> STARTINV_R { + STARTINV_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Window Monitor Event Out"] + #[inline(always)] + pub fn wineo(&self) -> WINEO_R { + WINEO_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Start Conversion Event Input Enable"] + #[inline(always)] + pub fn startei(&mut self) -> STARTEI_W { + STARTEI_W { w: self } + } + #[doc = "Bit 1 - Start Conversion Event Invert Enable"] + #[inline(always)] + pub fn startinv(&mut self) -> STARTINV_W { + STARTINV_W { w: self } + } + #[doc = "Bit 2 - Window Monitor Event Out"] + #[inline(always)] + pub fn wineo(&mut self) -> WINEO_W { + WINEO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/tsens/gain.rs b/pac/atsamc21n/src/tsens/gain.rs new file mode 100644 index 000000000000..785bbef3b6a4 --- /dev/null +++ b/pac/atsamc21n/src/tsens/gain.rs @@ -0,0 +1,103 @@ +#[doc = "Register `GAIN` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GAIN` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `GAIN` reader - Time Amplifier Gain"] +pub struct GAIN_R(crate::FieldReader); +impl GAIN_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + GAIN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GAIN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GAIN` writer - Time Amplifier Gain"] +pub struct GAIN_W<'a> { + w: &'a mut W, +} +impl<'a> GAIN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Time Amplifier Gain"] + #[inline(always)] + pub fn gain(&self) -> GAIN_R { + GAIN_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Time Amplifier Gain"] + #[inline(always)] + pub fn gain(&mut self) -> GAIN_W { + GAIN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Gain Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gain](index.html) module"] +pub struct GAIN_SPEC; +impl crate::RegisterSpec for GAIN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gain::R](R) reader structure"] +impl crate::Readable for GAIN_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gain::W](W) writer structure"] +impl crate::Writable for GAIN_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets GAIN to value 0"] +impl crate::Resettable for GAIN_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/tsens/intenclr.rs b/pac/atsamc21n/src/tsens/intenclr.rs new file mode 100644 index 000000000000..2362cf7b512b --- /dev/null +++ b/pac/atsamc21n/src/tsens/intenclr.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RESRDY` reader - Result Ready Interrupt Enable"] +pub struct RESRDY_R(crate::FieldReader); +impl RESRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESRDY` writer - Result Ready Interrupt Enable"] +pub struct RESRDY_W<'a> { + w: &'a mut W, +} +impl<'a> RESRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `OVERRUN` reader - Overrun Interrupt Enable"] +pub struct OVERRUN_R(crate::FieldReader); +impl OVERRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVERRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVERRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVERRUN` writer - Overrun Interrupt Enable"] +pub struct OVERRUN_W<'a> { + w: &'a mut W, +} +impl<'a> OVERRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WINMON` reader - Window Monitor Interrupt Enable"] +pub struct WINMON_R(crate::FieldReader); +impl WINMON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINMON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINMON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMON` writer - Window Monitor Interrupt Enable"] +pub struct WINMON_W<'a> { + w: &'a mut W, +} +impl<'a> WINMON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +impl R { + #[doc = "Bit 0 - Result Ready Interrupt Enable"] + #[inline(always)] + pub fn resrdy(&self) -> RESRDY_R { + RESRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Overrun Interrupt Enable"] + #[inline(always)] + pub fn overrun(&self) -> OVERRUN_R { + OVERRUN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Window Monitor Interrupt Enable"] + #[inline(always)] + pub fn winmon(&self) -> WINMON_R { + WINMON_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 3) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Result Ready Interrupt Enable"] + #[inline(always)] + pub fn resrdy(&mut self) -> RESRDY_W { + RESRDY_W { w: self } + } + #[doc = "Bit 1 - Overrun Interrupt Enable"] + #[inline(always)] + pub fn overrun(&mut self) -> OVERRUN_W { + OVERRUN_W { w: self } + } + #[doc = "Bit 2 - Window Monitor Interrupt Enable"] + #[inline(always)] + pub fn winmon(&mut self) -> WINMON_W { + WINMON_W { w: self } + } + #[doc = "Bit 3 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/tsens/intenset.rs b/pac/atsamc21n/src/tsens/intenset.rs new file mode 100644 index 000000000000..51df8bb668f2 --- /dev/null +++ b/pac/atsamc21n/src/tsens/intenset.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RESRDY` reader - Result Ready Interrupt Enable"] +pub struct RESRDY_R(crate::FieldReader); +impl RESRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESRDY` writer - Result Ready Interrupt Enable"] +pub struct RESRDY_W<'a> { + w: &'a mut W, +} +impl<'a> RESRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `OVERRUN` reader - Overrun Interrupt Enable"] +pub struct OVERRUN_R(crate::FieldReader); +impl OVERRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVERRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVERRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVERRUN` writer - Overrun Interrupt Enable"] +pub struct OVERRUN_W<'a> { + w: &'a mut W, +} +impl<'a> OVERRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WINMON` reader - Window Monitor Interrupt Enable"] +pub struct WINMON_R(crate::FieldReader); +impl WINMON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINMON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINMON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMON` writer - Window Monitor Interrupt Enable"] +pub struct WINMON_W<'a> { + w: &'a mut W, +} +impl<'a> WINMON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +impl R { + #[doc = "Bit 0 - Result Ready Interrupt Enable"] + #[inline(always)] + pub fn resrdy(&self) -> RESRDY_R { + RESRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Overrun Interrupt Enable"] + #[inline(always)] + pub fn overrun(&self) -> OVERRUN_R { + OVERRUN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Window Monitor Interrupt Enable"] + #[inline(always)] + pub fn winmon(&self) -> WINMON_R { + WINMON_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 3) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Result Ready Interrupt Enable"] + #[inline(always)] + pub fn resrdy(&mut self) -> RESRDY_W { + RESRDY_W { w: self } + } + #[doc = "Bit 1 - Overrun Interrupt Enable"] + #[inline(always)] + pub fn overrun(&mut self) -> OVERRUN_W { + OVERRUN_W { w: self } + } + #[doc = "Bit 2 - Window Monitor Interrupt Enable"] + #[inline(always)] + pub fn winmon(&mut self) -> WINMON_W { + WINMON_W { w: self } + } + #[doc = "Bit 3 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/tsens/intflag.rs b/pac/atsamc21n/src/tsens/intflag.rs new file mode 100644 index 000000000000..5058a4f8712c --- /dev/null +++ b/pac/atsamc21n/src/tsens/intflag.rs @@ -0,0 +1,254 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RESRDY` reader - Result Ready"] +pub struct RESRDY_R(crate::FieldReader); +impl RESRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESRDY` writer - Result Ready"] +pub struct RESRDY_W<'a> { + w: &'a mut W, +} +impl<'a> RESRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `OVERRUN` reader - Overrun"] +pub struct OVERRUN_R(crate::FieldReader); +impl OVERRUN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVERRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVERRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVERRUN` writer - Overrun"] +pub struct OVERRUN_W<'a> { + w: &'a mut W, +} +impl<'a> OVERRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WINMON` reader - Window Monitor"] +pub struct WINMON_R(crate::FieldReader); +impl WINMON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WINMON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINMON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINMON` writer - Window Monitor"] +pub struct WINMON_W<'a> { + w: &'a mut W, +} +impl<'a> WINMON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `OVF` reader - Overflow"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - Overflow"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +impl R { + #[doc = "Bit 0 - Result Ready"] + #[inline(always)] + pub fn resrdy(&self) -> RESRDY_R { + RESRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Overrun"] + #[inline(always)] + pub fn overrun(&self) -> OVERRUN_R { + OVERRUN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Window Monitor"] + #[inline(always)] + pub fn winmon(&self) -> WINMON_R { + WINMON_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Overflow"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 3) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Result Ready"] + #[inline(always)] + pub fn resrdy(&mut self) -> RESRDY_W { + RESRDY_W { w: self } + } + #[doc = "Bit 1 - Overrun"] + #[inline(always)] + pub fn overrun(&mut self) -> OVERRUN_W { + OVERRUN_W { w: self } + } + #[doc = "Bit 2 - Window Monitor"] + #[inline(always)] + pub fn winmon(&mut self) -> WINMON_W { + WINMON_W { w: self } + } + #[doc = "Bit 3 - Overflow"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/tsens/offset.rs b/pac/atsamc21n/src/tsens/offset.rs new file mode 100644 index 000000000000..1796ac252c12 --- /dev/null +++ b/pac/atsamc21n/src/tsens/offset.rs @@ -0,0 +1,103 @@ +#[doc = "Register `OFFSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OFFSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OFFSETC` reader - Offset Correction"] +pub struct OFFSETC_R(crate::FieldReader); +impl OFFSETC_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + OFFSETC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OFFSETC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OFFSETC` writer - Offset Correction"] +pub struct OFFSETC_W<'a> { + w: &'a mut W, +} +impl<'a> OFFSETC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Offset Correction"] + #[inline(always)] + pub fn offsetc(&self) -> OFFSETC_R { + OFFSETC_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Offset Correction"] + #[inline(always)] + pub fn offsetc(&mut self) -> OFFSETC_W { + OFFSETC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Offset Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [offset](index.html) module"] +pub struct OFFSET_SPEC; +impl crate::RegisterSpec for OFFSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [offset::R](R) reader structure"] +impl crate::Readable for OFFSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [offset::W](W) writer structure"] +impl crate::Writable for OFFSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OFFSET to value 0"] +impl crate::Resettable for OFFSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/tsens/status.rs b/pac/atsamc21n/src/tsens/status.rs new file mode 100644 index 000000000000..42309f7dcb4c --- /dev/null +++ b/pac/atsamc21n/src/tsens/status.rs @@ -0,0 +1,53 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `OVF` reader - Result Overflow"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Result Overflow"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } +} +#[doc = "Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/tsens/syncbusy.rs b/pac/atsamc21n/src/tsens/syncbusy.rs new file mode 100644 index 000000000000..e4492e16ad3c --- /dev/null +++ b/pac/atsamc21n/src/tsens/syncbusy.rs @@ -0,0 +1,73 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - Enable Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +#[doc = "Synchronization Busy Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/tsens/value.rs b/pac/atsamc21n/src/tsens/value.rs new file mode 100644 index 000000000000..54232a992edf --- /dev/null +++ b/pac/atsamc21n/src/tsens/value.rs @@ -0,0 +1,53 @@ +#[doc = "Register `VALUE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `VALUE` reader - Measurement Value"] +pub struct VALUE_R(crate::FieldReader); +impl VALUE_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + VALUE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VALUE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:23 - Measurement Value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +#[doc = "Value Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [value](index.html) module"] +pub struct VALUE_SPEC; +impl crate::RegisterSpec for VALUE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [value::R](R) reader structure"] +impl crate::Readable for VALUE_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets VALUE to value 0"] +impl crate::Resettable for VALUE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/tsens/winlt.rs b/pac/atsamc21n/src/tsens/winlt.rs new file mode 100644 index 000000000000..85a1d01b4b34 --- /dev/null +++ b/pac/atsamc21n/src/tsens/winlt.rs @@ -0,0 +1,103 @@ +#[doc = "Register `WINLT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WINLT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WINLT` reader - Window Lower Threshold"] +pub struct WINLT_R(crate::FieldReader); +impl WINLT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + WINLT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINLT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINLT` writer - Window Lower Threshold"] +pub struct WINLT_W<'a> { + w: &'a mut W, +} +impl<'a> WINLT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Window Lower Threshold"] + #[inline(always)] + pub fn winlt(&self) -> WINLT_R { + WINLT_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Window Lower Threshold"] + #[inline(always)] + pub fn winlt(&mut self) -> WINLT_W { + WINLT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Window Monitor Lower Threshold Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [winlt](index.html) module"] +pub struct WINLT_SPEC; +impl crate::RegisterSpec for WINLT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [winlt::R](R) reader structure"] +impl crate::Readable for WINLT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [winlt::W](W) writer structure"] +impl crate::Writable for WINLT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WINLT to value 0"] +impl crate::Resettable for WINLT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/tsens/winut.rs b/pac/atsamc21n/src/tsens/winut.rs new file mode 100644 index 000000000000..7da0850f8e50 --- /dev/null +++ b/pac/atsamc21n/src/tsens/winut.rs @@ -0,0 +1,103 @@ +#[doc = "Register `WINUT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WINUT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WINUT` reader - Window Upper Threshold"] +pub struct WINUT_R(crate::FieldReader); +impl WINUT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + WINUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WINUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINUT` writer - Window Upper Threshold"] +pub struct WINUT_W<'a> { + w: &'a mut W, +} +impl<'a> WINUT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Window Upper Threshold"] + #[inline(always)] + pub fn winut(&self) -> WINUT_R { + WINUT_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Window Upper Threshold"] + #[inline(always)] + pub fn winut(&mut self) -> WINUT_W { + WINUT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Window Monitor Upper Threshold Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [winut](index.html) module"] +pub struct WINUT_SPEC; +impl crate::RegisterSpec for WINUT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [winut::R](R) reader structure"] +impl crate::Readable for WINUT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [winut::W](W) writer structure"] +impl crate::Writable for WINUT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WINUT to value 0"] +impl crate::Resettable for WINUT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/wdt.rs b/pac/atsamc21n/src/wdt.rs new file mode 100644 index 000000000000..22b5c2bb706f --- /dev/null +++ b/pac/atsamc21n/src/wdt.rs @@ -0,0 +1,54 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrla: crate::Reg, + #[doc = "0x01 - Configuration"] + pub config: crate::Reg, + #[doc = "0x02 - Early Warning Interrupt Control"] + pub ewctrl: crate::Reg, + _reserved3: [u8; 0x01], + #[doc = "0x04 - Interrupt Enable Clear"] + pub intenclr: crate::Reg, + #[doc = "0x05 - Interrupt Enable Set"] + pub intenset: crate::Reg, + #[doc = "0x06 - Interrupt Flag Status and Clear"] + pub intflag: crate::Reg, + _reserved6: [u8; 0x01], + #[doc = "0x08 - Synchronization Busy"] + pub syncbusy: crate::Reg, + #[doc = "0x0c - Clear"] + pub clear: crate::Reg, +} +#[doc = "CTRLA register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control"] +pub mod ctrla; +#[doc = "CONFIG register accessor: an alias for `Reg`"] +pub type CONFIG = crate::Reg; +#[doc = "Configuration"] +pub mod config; +#[doc = "EWCTRL register accessor: an alias for `Reg`"] +pub type EWCTRL = crate::Reg; +#[doc = "Early Warning Interrupt Control"] +pub mod ewctrl; +#[doc = "INTENCLR register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "SYNCBUSY register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Busy"] +pub mod syncbusy; +#[doc = "CLEAR register accessor: an alias for `Reg`"] +pub type CLEAR = crate::Reg; +#[doc = "Clear"] +pub mod clear; diff --git a/pac/atsamc21n/src/wdt/clear.rs b/pac/atsamc21n/src/wdt/clear.rs new file mode 100644 index 000000000000..61ee21f3246a --- /dev/null +++ b/pac/atsamc21n/src/wdt/clear.rs @@ -0,0 +1,85 @@ +#[doc = "Register `CLEAR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Watchdog Clear\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CLEAR_AW { + #[doc = "165: Clear Key"] + KEY = 165, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CLEAR_AW) -> Self { + variant as _ + } +} +#[doc = "Field `CLEAR` writer - Watchdog Clear"] +pub struct CLEAR_W<'a> { + w: &'a mut W, +} +impl<'a> CLEAR_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CLEAR_AW) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Clear Key"] + #[inline(always)] + pub fn key(self) -> &'a mut W { + self.variant(CLEAR_AW::KEY) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = value as u8; + self.w + } +} +impl W { + #[doc = "Bits 0:7 - Watchdog Clear"] + #[inline(always)] + pub fn clear(&mut self) -> CLEAR_W { + CLEAR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Clear\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clear](index.html) module"] +pub struct CLEAR_SPEC; +impl crate::RegisterSpec for CLEAR_SPEC { + type Ux = u8; +} +#[doc = "`write(|w| ..)` method takes [clear::W](W) writer structure"] +impl crate::Writable for CLEAR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CLEAR to value 0"] +impl crate::Resettable for CLEAR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/wdt/config.rs b/pac/atsamc21n/src/wdt/config.rs new file mode 100644 index 000000000000..c90f062b01f0 --- /dev/null +++ b/pac/atsamc21n/src/wdt/config.rs @@ -0,0 +1,498 @@ +#[doc = "Register `CONFIG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CONFIG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Time-Out Period\n\nValue on reset: 11"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PER_A { + #[doc = "0: 8 clock cycles"] + CYC8 = 0, + #[doc = "1: 16 clock cycles"] + CYC16 = 1, + #[doc = "2: 32 clock cycles"] + CYC32 = 2, + #[doc = "3: 64 clock cycles"] + CYC64 = 3, + #[doc = "4: 128 clock cycles"] + CYC128 = 4, + #[doc = "5: 256 clock cycles"] + CYC256 = 5, + #[doc = "6: 512 clock cycles"] + CYC512 = 6, + #[doc = "7: 1024 clock cycles"] + CYC1024 = 7, + #[doc = "8: 2048 clock cycles"] + CYC2048 = 8, + #[doc = "9: 4096 clock cycles"] + CYC4096 = 9, + #[doc = "10: 8192 clock cycles"] + CYC8192 = 10, + #[doc = "11: 16384 clock cycles"] + CYC16384 = 11, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PER_A) -> Self { + variant as _ + } +} +#[doc = "Field `PER` reader - Time-Out Period"] +pub struct PER_R(crate::FieldReader); +impl PER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PER_A::CYC8), + 1 => Some(PER_A::CYC16), + 2 => Some(PER_A::CYC32), + 3 => Some(PER_A::CYC64), + 4 => Some(PER_A::CYC128), + 5 => Some(PER_A::CYC256), + 6 => Some(PER_A::CYC512), + 7 => Some(PER_A::CYC1024), + 8 => Some(PER_A::CYC2048), + 9 => Some(PER_A::CYC4096), + 10 => Some(PER_A::CYC8192), + 11 => Some(PER_A::CYC16384), + _ => None, + } + } + #[doc = "Checks if the value of the field is `CYC8`"] + #[inline(always)] + pub fn is_cyc8(&self) -> bool { + **self == PER_A::CYC8 + } + #[doc = "Checks if the value of the field is `CYC16`"] + #[inline(always)] + pub fn is_cyc16(&self) -> bool { + **self == PER_A::CYC16 + } + #[doc = "Checks if the value of the field is `CYC32`"] + #[inline(always)] + pub fn is_cyc32(&self) -> bool { + **self == PER_A::CYC32 + } + #[doc = "Checks if the value of the field is `CYC64`"] + #[inline(always)] + pub fn is_cyc64(&self) -> bool { + **self == PER_A::CYC64 + } + #[doc = "Checks if the value of the field is `CYC128`"] + #[inline(always)] + pub fn is_cyc128(&self) -> bool { + **self == PER_A::CYC128 + } + #[doc = "Checks if the value of the field is `CYC256`"] + #[inline(always)] + pub fn is_cyc256(&self) -> bool { + **self == PER_A::CYC256 + } + #[doc = "Checks if the value of the field is `CYC512`"] + #[inline(always)] + pub fn is_cyc512(&self) -> bool { + **self == PER_A::CYC512 + } + #[doc = "Checks if the value of the field is `CYC1024`"] + #[inline(always)] + pub fn is_cyc1024(&self) -> bool { + **self == PER_A::CYC1024 + } + #[doc = "Checks if the value of the field is `CYC2048`"] + #[inline(always)] + pub fn is_cyc2048(&self) -> bool { + **self == PER_A::CYC2048 + } + #[doc = "Checks if the value of the field is `CYC4096`"] + #[inline(always)] + pub fn is_cyc4096(&self) -> bool { + **self == PER_A::CYC4096 + } + #[doc = "Checks if the value of the field is `CYC8192`"] + #[inline(always)] + pub fn is_cyc8192(&self) -> bool { + **self == PER_A::CYC8192 + } + #[doc = "Checks if the value of the field is `CYC16384`"] + #[inline(always)] + pub fn is_cyc16384(&self) -> bool { + **self == PER_A::CYC16384 + } +} +impl core::ops::Deref for PER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PER` writer - Time-Out Period"] +pub struct PER_W<'a> { + w: &'a mut W, +} +impl<'a> PER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PER_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8 clock cycles"] + #[inline(always)] + pub fn cyc8(self) -> &'a mut W { + self.variant(PER_A::CYC8) + } + #[doc = "16 clock cycles"] + #[inline(always)] + pub fn cyc16(self) -> &'a mut W { + self.variant(PER_A::CYC16) + } + #[doc = "32 clock cycles"] + #[inline(always)] + pub fn cyc32(self) -> &'a mut W { + self.variant(PER_A::CYC32) + } + #[doc = "64 clock cycles"] + #[inline(always)] + pub fn cyc64(self) -> &'a mut W { + self.variant(PER_A::CYC64) + } + #[doc = "128 clock cycles"] + #[inline(always)] + pub fn cyc128(self) -> &'a mut W { + self.variant(PER_A::CYC128) + } + #[doc = "256 clock cycles"] + #[inline(always)] + pub fn cyc256(self) -> &'a mut W { + self.variant(PER_A::CYC256) + } + #[doc = "512 clock cycles"] + #[inline(always)] + pub fn cyc512(self) -> &'a mut W { + self.variant(PER_A::CYC512) + } + #[doc = "1024 clock cycles"] + #[inline(always)] + pub fn cyc1024(self) -> &'a mut W { + self.variant(PER_A::CYC1024) + } + #[doc = "2048 clock cycles"] + #[inline(always)] + pub fn cyc2048(self) -> &'a mut W { + self.variant(PER_A::CYC2048) + } + #[doc = "4096 clock cycles"] + #[inline(always)] + pub fn cyc4096(self) -> &'a mut W { + self.variant(PER_A::CYC4096) + } + #[doc = "8192 clock cycles"] + #[inline(always)] + pub fn cyc8192(self) -> &'a mut W { + self.variant(PER_A::CYC8192) + } + #[doc = "16384 clock cycles"] + #[inline(always)] + pub fn cyc16384(self) -> &'a mut W { + self.variant(PER_A::CYC16384) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +#[doc = "Window Mode Time-Out Period\n\nValue on reset: 11"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WINDOW_A { + #[doc = "0: 8 clock cycles"] + CYC8 = 0, + #[doc = "1: 16 clock cycles"] + CYC16 = 1, + #[doc = "2: 32 clock cycles"] + CYC32 = 2, + #[doc = "3: 64 clock cycles"] + CYC64 = 3, + #[doc = "4: 128 clock cycles"] + CYC128 = 4, + #[doc = "5: 256 clock cycles"] + CYC256 = 5, + #[doc = "6: 512 clock cycles"] + CYC512 = 6, + #[doc = "7: 1024 clock cycles"] + CYC1024 = 7, + #[doc = "8: 2048 clock cycles"] + CYC2048 = 8, + #[doc = "9: 4096 clock cycles"] + CYC4096 = 9, + #[doc = "10: 8192 clock cycles"] + CYC8192 = 10, + #[doc = "11: 16384 clock cycles"] + CYC16384 = 11, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WINDOW_A) -> Self { + variant as _ + } +} +#[doc = "Field `WINDOW` reader - Window Mode Time-Out Period"] +pub struct WINDOW_R(crate::FieldReader); +impl WINDOW_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WINDOW_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(WINDOW_A::CYC8), + 1 => Some(WINDOW_A::CYC16), + 2 => Some(WINDOW_A::CYC32), + 3 => Some(WINDOW_A::CYC64), + 4 => Some(WINDOW_A::CYC128), + 5 => Some(WINDOW_A::CYC256), + 6 => Some(WINDOW_A::CYC512), + 7 => Some(WINDOW_A::CYC1024), + 8 => Some(WINDOW_A::CYC2048), + 9 => Some(WINDOW_A::CYC4096), + 10 => Some(WINDOW_A::CYC8192), + 11 => Some(WINDOW_A::CYC16384), + _ => None, + } + } + #[doc = "Checks if the value of the field is `CYC8`"] + #[inline(always)] + pub fn is_cyc8(&self) -> bool { + **self == WINDOW_A::CYC8 + } + #[doc = "Checks if the value of the field is `CYC16`"] + #[inline(always)] + pub fn is_cyc16(&self) -> bool { + **self == WINDOW_A::CYC16 + } + #[doc = "Checks if the value of the field is `CYC32`"] + #[inline(always)] + pub fn is_cyc32(&self) -> bool { + **self == WINDOW_A::CYC32 + } + #[doc = "Checks if the value of the field is `CYC64`"] + #[inline(always)] + pub fn is_cyc64(&self) -> bool { + **self == WINDOW_A::CYC64 + } + #[doc = "Checks if the value of the field is `CYC128`"] + #[inline(always)] + pub fn is_cyc128(&self) -> bool { + **self == WINDOW_A::CYC128 + } + #[doc = "Checks if the value of the field is `CYC256`"] + #[inline(always)] + pub fn is_cyc256(&self) -> bool { + **self == WINDOW_A::CYC256 + } + #[doc = "Checks if the value of the field is `CYC512`"] + #[inline(always)] + pub fn is_cyc512(&self) -> bool { + **self == WINDOW_A::CYC512 + } + #[doc = "Checks if the value of the field is `CYC1024`"] + #[inline(always)] + pub fn is_cyc1024(&self) -> bool { + **self == WINDOW_A::CYC1024 + } + #[doc = "Checks if the value of the field is `CYC2048`"] + #[inline(always)] + pub fn is_cyc2048(&self) -> bool { + **self == WINDOW_A::CYC2048 + } + #[doc = "Checks if the value of the field is `CYC4096`"] + #[inline(always)] + pub fn is_cyc4096(&self) -> bool { + **self == WINDOW_A::CYC4096 + } + #[doc = "Checks if the value of the field is `CYC8192`"] + #[inline(always)] + pub fn is_cyc8192(&self) -> bool { + **self == WINDOW_A::CYC8192 + } + #[doc = "Checks if the value of the field is `CYC16384`"] + #[inline(always)] + pub fn is_cyc16384(&self) -> bool { + **self == WINDOW_A::CYC16384 + } +} +impl core::ops::Deref for WINDOW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WINDOW` writer - Window Mode Time-Out Period"] +pub struct WINDOW_W<'a> { + w: &'a mut W, +} +impl<'a> WINDOW_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WINDOW_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8 clock cycles"] + #[inline(always)] + pub fn cyc8(self) -> &'a mut W { + self.variant(WINDOW_A::CYC8) + } + #[doc = "16 clock cycles"] + #[inline(always)] + pub fn cyc16(self) -> &'a mut W { + self.variant(WINDOW_A::CYC16) + } + #[doc = "32 clock cycles"] + #[inline(always)] + pub fn cyc32(self) -> &'a mut W { + self.variant(WINDOW_A::CYC32) + } + #[doc = "64 clock cycles"] + #[inline(always)] + pub fn cyc64(self) -> &'a mut W { + self.variant(WINDOW_A::CYC64) + } + #[doc = "128 clock cycles"] + #[inline(always)] + pub fn cyc128(self) -> &'a mut W { + self.variant(WINDOW_A::CYC128) + } + #[doc = "256 clock cycles"] + #[inline(always)] + pub fn cyc256(self) -> &'a mut W { + self.variant(WINDOW_A::CYC256) + } + #[doc = "512 clock cycles"] + #[inline(always)] + pub fn cyc512(self) -> &'a mut W { + self.variant(WINDOW_A::CYC512) + } + #[doc = "1024 clock cycles"] + #[inline(always)] + pub fn cyc1024(self) -> &'a mut W { + self.variant(WINDOW_A::CYC1024) + } + #[doc = "2048 clock cycles"] + #[inline(always)] + pub fn cyc2048(self) -> &'a mut W { + self.variant(WINDOW_A::CYC2048) + } + #[doc = "4096 clock cycles"] + #[inline(always)] + pub fn cyc4096(self) -> &'a mut W { + self.variant(WINDOW_A::CYC4096) + } + #[doc = "8192 clock cycles"] + #[inline(always)] + pub fn cyc8192(self) -> &'a mut W { + self.variant(WINDOW_A::CYC8192) + } + #[doc = "16384 clock cycles"] + #[inline(always)] + pub fn cyc16384(self) -> &'a mut W { + self.variant(WINDOW_A::CYC16384) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 4)) | ((value as u8 & 0x0f) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Time-Out Period"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Window Mode Time-Out Period"] + #[inline(always)] + pub fn window(&self) -> WINDOW_R { + WINDOW_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Time-Out Period"] + #[inline(always)] + pub fn per(&mut self) -> PER_W { + PER_W { w: self } + } + #[doc = "Bits 4:7 - Window Mode Time-Out Period"] + #[inline(always)] + pub fn window(&mut self) -> WINDOW_W { + WINDOW_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [config](index.html) module"] +pub struct CONFIG_SPEC; +impl crate::RegisterSpec for CONFIG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [config::R](R) reader structure"] +impl crate::Readable for CONFIG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [config::W](W) writer structure"] +impl crate::Writable for CONFIG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CONFIG to value 0xbb"] +impl crate::Resettable for CONFIG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xbb + } +} diff --git a/pac/atsamc21n/src/wdt/ctrla.rs b/pac/atsamc21n/src/wdt/ctrla.rs new file mode 100644 index 000000000000..895169d36aeb --- /dev/null +++ b/pac/atsamc21n/src/wdt/ctrla.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WEN` reader - Watchdog Timer Window Mode Enable"] +pub struct WEN_R(crate::FieldReader); +impl WEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WEN` writer - Watchdog Timer Window Mode Enable"] +pub struct WEN_W<'a> { + w: &'a mut W, +} +impl<'a> WEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `ALWAYSON` reader - Always-On"] +pub struct ALWAYSON_R(crate::FieldReader); +impl ALWAYSON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALWAYSON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALWAYSON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALWAYSON` writer - Always-On"] +pub struct ALWAYSON_W<'a> { + w: &'a mut W, +} +impl<'a> ALWAYSON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Watchdog Timer Window Mode Enable"] + #[inline(always)] + pub fn wen(&self) -> WEN_R { + WEN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 7 - Always-On"] + #[inline(always)] + pub fn alwayson(&self) -> ALWAYSON_R { + ALWAYSON_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - Watchdog Timer Window Mode Enable"] + #[inline(always)] + pub fn wen(&mut self) -> WEN_W { + WEN_W { w: self } + } + #[doc = "Bit 7 - Always-On"] + #[inline(always)] + pub fn alwayson(&mut self) -> ALWAYSON_W { + ALWAYSON_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/wdt/ewctrl.rs b/pac/atsamc21n/src/wdt/ewctrl.rs new file mode 100644 index 000000000000..94542e9897a9 --- /dev/null +++ b/pac/atsamc21n/src/wdt/ewctrl.rs @@ -0,0 +1,282 @@ +#[doc = "Register `EWCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EWCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Early Warning Interrupt Time Offset\n\nValue on reset: 11"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EWOFFSET_A { + #[doc = "0: 8 clock cycles"] + CYC8 = 0, + #[doc = "1: 16 clock cycles"] + CYC16 = 1, + #[doc = "2: 32 clock cycles"] + CYC32 = 2, + #[doc = "3: 64 clock cycles"] + CYC64 = 3, + #[doc = "4: 128 clock cycles"] + CYC128 = 4, + #[doc = "5: 256 clock cycles"] + CYC256 = 5, + #[doc = "6: 512 clock cycles"] + CYC512 = 6, + #[doc = "7: 1024 clock cycles"] + CYC1024 = 7, + #[doc = "8: 2048 clock cycles"] + CYC2048 = 8, + #[doc = "9: 4096 clock cycles"] + CYC4096 = 9, + #[doc = "10: 8192 clock cycles"] + CYC8192 = 10, + #[doc = "11: 16384 clock cycles"] + CYC16384 = 11, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EWOFFSET_A) -> Self { + variant as _ + } +} +#[doc = "Field `EWOFFSET` reader - Early Warning Interrupt Time Offset"] +pub struct EWOFFSET_R(crate::FieldReader); +impl EWOFFSET_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EWOFFSET_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(EWOFFSET_A::CYC8), + 1 => Some(EWOFFSET_A::CYC16), + 2 => Some(EWOFFSET_A::CYC32), + 3 => Some(EWOFFSET_A::CYC64), + 4 => Some(EWOFFSET_A::CYC128), + 5 => Some(EWOFFSET_A::CYC256), + 6 => Some(EWOFFSET_A::CYC512), + 7 => Some(EWOFFSET_A::CYC1024), + 8 => Some(EWOFFSET_A::CYC2048), + 9 => Some(EWOFFSET_A::CYC4096), + 10 => Some(EWOFFSET_A::CYC8192), + 11 => Some(EWOFFSET_A::CYC16384), + _ => None, + } + } + #[doc = "Checks if the value of the field is `CYC8`"] + #[inline(always)] + pub fn is_cyc8(&self) -> bool { + **self == EWOFFSET_A::CYC8 + } + #[doc = "Checks if the value of the field is `CYC16`"] + #[inline(always)] + pub fn is_cyc16(&self) -> bool { + **self == EWOFFSET_A::CYC16 + } + #[doc = "Checks if the value of the field is `CYC32`"] + #[inline(always)] + pub fn is_cyc32(&self) -> bool { + **self == EWOFFSET_A::CYC32 + } + #[doc = "Checks if the value of the field is `CYC64`"] + #[inline(always)] + pub fn is_cyc64(&self) -> bool { + **self == EWOFFSET_A::CYC64 + } + #[doc = "Checks if the value of the field is `CYC128`"] + #[inline(always)] + pub fn is_cyc128(&self) -> bool { + **self == EWOFFSET_A::CYC128 + } + #[doc = "Checks if the value of the field is `CYC256`"] + #[inline(always)] + pub fn is_cyc256(&self) -> bool { + **self == EWOFFSET_A::CYC256 + } + #[doc = "Checks if the value of the field is `CYC512`"] + #[inline(always)] + pub fn is_cyc512(&self) -> bool { + **self == EWOFFSET_A::CYC512 + } + #[doc = "Checks if the value of the field is `CYC1024`"] + #[inline(always)] + pub fn is_cyc1024(&self) -> bool { + **self == EWOFFSET_A::CYC1024 + } + #[doc = "Checks if the value of the field is `CYC2048`"] + #[inline(always)] + pub fn is_cyc2048(&self) -> bool { + **self == EWOFFSET_A::CYC2048 + } + #[doc = "Checks if the value of the field is `CYC4096`"] + #[inline(always)] + pub fn is_cyc4096(&self) -> bool { + **self == EWOFFSET_A::CYC4096 + } + #[doc = "Checks if the value of the field is `CYC8192`"] + #[inline(always)] + pub fn is_cyc8192(&self) -> bool { + **self == EWOFFSET_A::CYC8192 + } + #[doc = "Checks if the value of the field is `CYC16384`"] + #[inline(always)] + pub fn is_cyc16384(&self) -> bool { + **self == EWOFFSET_A::CYC16384 + } +} +impl core::ops::Deref for EWOFFSET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EWOFFSET` writer - Early Warning Interrupt Time Offset"] +pub struct EWOFFSET_W<'a> { + w: &'a mut W, +} +impl<'a> EWOFFSET_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EWOFFSET_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8 clock cycles"] + #[inline(always)] + pub fn cyc8(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC8) + } + #[doc = "16 clock cycles"] + #[inline(always)] + pub fn cyc16(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC16) + } + #[doc = "32 clock cycles"] + #[inline(always)] + pub fn cyc32(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC32) + } + #[doc = "64 clock cycles"] + #[inline(always)] + pub fn cyc64(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC64) + } + #[doc = "128 clock cycles"] + #[inline(always)] + pub fn cyc128(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC128) + } + #[doc = "256 clock cycles"] + #[inline(always)] + pub fn cyc256(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC256) + } + #[doc = "512 clock cycles"] + #[inline(always)] + pub fn cyc512(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC512) + } + #[doc = "1024 clock cycles"] + #[inline(always)] + pub fn cyc1024(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC1024) + } + #[doc = "2048 clock cycles"] + #[inline(always)] + pub fn cyc2048(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC2048) + } + #[doc = "4096 clock cycles"] + #[inline(always)] + pub fn cyc4096(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC4096) + } + #[doc = "8192 clock cycles"] + #[inline(always)] + pub fn cyc8192(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC8192) + } + #[doc = "16384 clock cycles"] + #[inline(always)] + pub fn cyc16384(self) -> &'a mut W { + self.variant(EWOFFSET_A::CYC16384) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Early Warning Interrupt Time Offset"] + #[inline(always)] + pub fn ewoffset(&self) -> EWOFFSET_R { + EWOFFSET_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Early Warning Interrupt Time Offset"] + #[inline(always)] + pub fn ewoffset(&mut self) -> EWOFFSET_W { + EWOFFSET_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Early Warning Interrupt Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ewctrl](index.html) module"] +pub struct EWCTRL_SPEC; +impl crate::RegisterSpec for EWCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ewctrl::R](R) reader structure"] +impl crate::Readable for EWCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ewctrl::W](W) writer structure"] +impl crate::Writable for EWCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EWCTRL to value 0x0b"] +impl crate::Resettable for EWCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0b + } +} diff --git a/pac/atsamc21n/src/wdt/intenclr.rs b/pac/atsamc21n/src/wdt/intenclr.rs new file mode 100644 index 000000000000..ed4021f96cce --- /dev/null +++ b/pac/atsamc21n/src/wdt/intenclr.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EW` reader - Early Warning Interrupt Enable"] +pub struct EW_R(crate::FieldReader); +impl EW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EW` writer - Early Warning Interrupt Enable"] +pub struct EW_W<'a> { + w: &'a mut W, +} +impl<'a> EW_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Early Warning Interrupt Enable"] + #[inline(always)] + pub fn ew(&self) -> EW_R { + EW_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Early Warning Interrupt Enable"] + #[inline(always)] + pub fn ew(&mut self) -> EW_W { + EW_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/wdt/intenset.rs b/pac/atsamc21n/src/wdt/intenset.rs new file mode 100644 index 000000000000..5a0928ff0532 --- /dev/null +++ b/pac/atsamc21n/src/wdt/intenset.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EW` reader - Early Warning Interrupt Enable"] +pub struct EW_R(crate::FieldReader); +impl EW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EW` writer - Early Warning Interrupt Enable"] +pub struct EW_W<'a> { + w: &'a mut W, +} +impl<'a> EW_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Early Warning Interrupt Enable"] + #[inline(always)] + pub fn ew(&self) -> EW_R { + EW_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Early Warning Interrupt Enable"] + #[inline(always)] + pub fn ew(&mut self) -> EW_W { + EW_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/wdt/intflag.rs b/pac/atsamc21n/src/wdt/intflag.rs new file mode 100644 index 000000000000..f2c9b858a199 --- /dev/null +++ b/pac/atsamc21n/src/wdt/intflag.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EW` reader - Early Warning"] +pub struct EW_R(crate::FieldReader); +impl EW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EW` writer - Early Warning"] +pub struct EW_W<'a> { + w: &'a mut W, +} +impl<'a> EW_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Early Warning"] + #[inline(always)] + pub fn ew(&self) -> EW_R { + EW_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Early Warning"] + #[inline(always)] + pub fn ew(&mut self) -> EW_W { + EW_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/pac/atsamc21n/src/wdt/syncbusy.rs b/pac/atsamc21n/src/wdt/syncbusy.rs new file mode 100644 index 000000000000..a3ecf7fbdb8a --- /dev/null +++ b/pac/atsamc21n/src/wdt/syncbusy.rs @@ -0,0 +1,113 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `ENABLE` reader - Enable Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WEN` reader - Window Enable Busy"] +pub struct WEN_R(crate::FieldReader); +impl WEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALWAYSON` reader - Always-On Busy"] +pub struct ALWAYSON_R(crate::FieldReader); +impl ALWAYSON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALWAYSON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALWAYSON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLEAR` reader - Clear Busy"] +pub struct CLEAR_R(crate::FieldReader); +impl CLEAR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLEAR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLEAR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 1 - Enable Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Window Enable Busy"] + #[inline(always)] + pub fn wen(&self) -> WEN_R { + WEN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Always-On Busy"] + #[inline(always)] + pub fn alwayson(&self) -> ALWAYSON_R { + ALWAYSON_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Clear Busy"] + #[inline(always)] + pub fn clear(&self) -> CLEAR_R { + CLEAR_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +#[doc = "Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/svd/ATSAMC20J18AU.svd b/svd/ATSAMC20J18AU.svd deleted file mode 100644 index 002c6a264508..000000000000 --- a/svd/ATSAMC20J18AU.svd +++ /dev/null @@ -1,21842 +0,0 @@ - - - - Microchip Technology - MCHP - ATSAMC20J18AU - SAMC20 - 0 - Microchip ATSAMC20J18AU Microcontroller - - CM0+ - r0p0 - selectable - true - false - 2 - false - - 8 - 32 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - AC - U22451.1.1 - Analog Comparators - AC - AC_ - 0x42005000 - - 0 - 0x24 - registers - - - AC - 27 - - - - CTRLA - Control A - 0x0 - 8 - 0x00 - - - SWRST - Software Reset - 0 - 1 - - - ENABLE - Enable - 1 - 1 - - - - - CTRLB - Control B - 0x1 - 8 - write-only - 0x00 - - - START0 - Comparator 0 Start Comparison - 0 - 1 - - - START1 - Comparator 1 Start Comparison - 1 - 1 - - - - - EVCTRL - Event Control - 0x2 - 16 - 0x0000 - - - COMPEO0 - Comparator 0 Event Output Enable - 0 - 1 - - - COMPEO1 - Comparator 1 Event Output Enable - 1 - 1 - - - WINEO0 - Window 0 Event Output Enable - 4 - 1 - - - COMPEI0 - Comparator 0 Event Input Enable - 8 - 1 - - - COMPEI1 - Comparator 1 Event Input Enable - 9 - 1 - - - INVEI0 - Comparator 0 Input Event Invert Enable - 12 - 1 - - - INVEI1 - Comparator 1 Input Event Invert Enable - 13 - 1 - - - - - INTENCLR - Interrupt Enable Clear - 0x4 - 8 - 0x00 - - - COMP0 - Comparator 0 Interrupt Enable - 0 - 1 - - - COMP1 - Comparator 1 Interrupt Enable - 1 - 1 - - - WIN0 - Window 0 Interrupt Enable - 4 - 1 - - - - - INTENSET - Interrupt Enable Set - 0x5 - 8 - 0x00 - - - COMP0 - Comparator 0 Interrupt Enable - 0 - 1 - - - COMP1 - Comparator 1 Interrupt Enable - 1 - 1 - - - WIN0 - Window 0 Interrupt Enable - 4 - 1 - - - - - INTFLAG - Interrupt Flag Status and Clear - 0x6 - 8 - 0x00 - - - COMP0 - Comparator 0 - 0 - 1 - - - COMP1 - Comparator 1 - 1 - 1 - - - WIN0 - Window 0 - 4 - 1 - - - - - STATUSA - Status A - 0x7 - 8 - read-only - 0x00 - - - STATE0 - Comparator 0 Current State - 0 - 1 - - - STATE1 - Comparator 1 Current State - 1 - 1 - - - WSTATE0 - Window 0 Current State - 4 - 2 - - WSTATE0Select - - ABOVE - Signal is above window - 0 - - - INSIDE - Signal is inside window - 1 - - - BELOW - Signal is below window - 2 - - - - - - - STATUSB - Status B - 0x8 - 8 - read-only - 0x00 - - - READY0 - Comparator 0 Ready - 0 - 1 - - - READY1 - Comparator 1 Ready - 1 - 1 - - - - - DBGCTRL - Debug Control - 0x9 - 8 - 0x00 - - - DBGRUN - Debug Run - 0 - 1 - - - - - WINCTRL - Window Control - 0xA - 8 - 0x00 - - - WEN0 - Window 0 Mode Enable - 0 - 1 - - - WINTSEL0 - Window 0 Interrupt Selection - 1 - 2 - - WINTSEL0Select - - ABOVE - Interrupt on signal above window - 0 - - - INSIDE - Interrupt on signal inside window - 1 - - - BELOW - Interrupt on signal below window - 2 - - - OUTSIDE - Interrupt on signal outside window - 3 - - - - - - - 4 - 1 - SCALER[%s] - Scaler n - 0xC - 8 - 0x00 - - - VALUE - Scaler Value - 0 - 6 - - - - - 4 - 4 - COMPCTRL[%s] - Comparator Control n - 0x10 - 32 - 0x00000000 - - - ENABLE - Enable - 1 - 1 - - - SINGLE - Single-Shot Mode - 2 - 1 - - - INTSEL - Interrupt Selection - 3 - 2 - - INTSELSelect - - TOGGLE - Interrupt on comparator output toggle - 0 - - - RISING - Interrupt on comparator output rising - 1 - - - FALLING - Interrupt on comparator output falling - 2 - - - EOC - Interrupt on end of comparison (single-shot mode only) - 3 - - - - - RUNSTDBY - Run in Standby - 6 - 1 - - - MUXNEG - Negative Input Mux Selection - 8 - 3 - - MUXNEGSelect - - PIN0 - I/O pin 0 - 0 - - - PIN1 - I/O pin 1 - 1 - - - PIN2 - I/O pin 2 - 2 - - - PIN3 - I/O pin 3 - 3 - - - GND - Ground - 4 - - - VSCALE - VDD scaler - 5 - - - BANDGAP - Internal bandgap voltage - 6 - - - - - MUXPOS - Positive Input Mux Selection - 12 - 3 - - MUXPOSSelect - - PIN0 - I/O pin 0 - 0 - - - PIN1 - I/O pin 1 - 1 - - - PIN2 - I/O pin 2 - 2 - - - PIN3 - I/O pin 3 - 3 - - - VSCALE - VDD Scaler - 4 - - - - - SWAP - Swap Inputs and Invert - 15 - 1 - - - SPEED - Speed Selection - 16 - 2 - - SPEEDSelect - - LOW - Low speed - 0 - - - HIGH - High speed - 3 - - - - - HYSTEN - Hysteresis Enable - 19 - 1 - - - FLEN - Filter Length - 24 - 3 - - FLENSelect - - OFF - No filtering - 0 - - - MAJ3 - 3-bit majority function (2 of 3) - 1 - - - MAJ5 - 5-bit majority function (3 of 5) - 2 - - - - - OUT - Output - 28 - 2 - - OUTSelect - - OFF - The output of COMPn is not routed to the COMPn I/O port - 0 - - - ASYNC - The asynchronous output of COMPn is routed to the COMPn I/O port - 1 - - - SYNC - The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port - 2 - - - - - - - SYNCBUSY - Synchronization Busy - 0x20 - 32 - read-only - 0x00000000 - - - SWRST - Software Reset Synchronization Busy - 0 - 1 - - - ENABLE - Enable Synchronization Busy - 1 - 1 - - - WINCTRL - WINCTRL Synchronization Busy - 2 - 1 - - - COMPCTRL0 - COMPCTRL 0 Synchronization Busy - 3 - 1 - - - COMPCTRL1 - COMPCTRL 1 Synchronization Busy - 4 - 1 - - - - - - - ADC0 - U22472.2.0 - Analog Digital Converter - ADC - ADC_ - 0x42004400 - - 0 - 0x2E - registers - - - ADC0 - 25 - - - - CTRLA - Control A - 0x0 - 8 - 0x00 - - - SWRST - Software Reset - 0 - 1 - - - ENABLE - Enable - 1 - 1 - - - SLAVEEN - Slave Enable - 5 - 1 - - - RUNSTDBY - Run During Standby - 6 - 1 - - - ONDEMAND - On Demand Control - 7 - 1 - - - - - CTRLB - Control B - 0x1 - 8 - 0x00 - - - PRESCALER - Prescaler Configuration - 0 - 3 - - PRESCALERSelect - - DIV2 - Peripheral clock / 2 - 0x0 - - - DIV4 - Peripheral clock / 4 - 0x1 - - - DIV8 - Peripheral clock / 8 - 0x2 - - - DIV16 - Peripheral clock / 16 - 0x3 - - - DIV32 - Peripheral clock / 32 - 0x4 - - - DIV64 - Peripheral clock / 64 - 0x5 - - - DIV128 - Peripheral clock / 128 - 0x6 - - - DIV256 - Peripheral clock / 256 - 0x7 - - - - - - - REFCTRL - Reference Control - 0x2 - 8 - 0x00 - - - REFSEL - Reference Selection - 0 - 4 - - REFSELSelect - - INTREF - Internal Bandgap Reference - 0x0 - - - INTVCC0 - 1/1.6 VDDANA - 0x1 - - - INTVCC1 - 1/2 VDDANA - 0x2 - - - AREFA - External Reference - 0x3 - - - INTVCC2 - VDDANA - 0x5 - - - - - REFCOMP - Reference Buffer Offset Compensation Enable - 7 - 1 - - - - - EVCTRL - Event Control - 0x3 - 8 - 0x00 - - - FLUSHEI - Flush Event Input Enable - 0 - 1 - - - STARTEI - Start Conversion Event Input Enable - 1 - 1 - - - FLUSHINV - Flush Event Invert Enable - 2 - 1 - - - STARTINV - Start Event Invert Enable - 3 - 1 - - - RESRDYEO - Result Ready Event Out - 4 - 1 - - - WINMONEO - Window Monitor Event Out - 5 - 1 - - - - - INTENCLR - Interrupt Enable Clear - 0x4 - 8 - 0x00 - - - RESRDY - Result Ready Interrupt Disable - 0 - 1 - - - OVERRUN - Overrun Interrupt Disable - 1 - 1 - - - WINMON - Window Monitor Interrupt Disable - 2 - 1 - - - - - INTENSET - Interrupt Enable Set - 0x5 - 8 - 0x00 - - - RESRDY - Result Ready Interrupt Enable - 0 - 1 - - - OVERRUN - Overrun Interrupt Enable - 1 - 1 - - - WINMON - Window Monitor Interrupt Enable - 2 - 1 - - - - - INTFLAG - Interrupt Flag Status and Clear - 0x6 - 8 - 0x00 - - - RESRDY - Result Ready Interrupt Flag - 0 - 1 - - - OVERRUN - Overrun Interrupt Flag - 1 - 1 - - - WINMON - Window Monitor Interrupt Flag - 2 - 1 - - - - - SEQSTATUS - Sequence Status - 0x7 - 8 - read-only - 0x00 - - - SEQSTATE - Sequence State - 0 - 5 - - - SEQBUSY - Sequence Busy - 7 - 1 - - - - - INPUTCTRL - Input Control - 0x8 - 16 - 0x0000 - - - MUXPOS - Positive Mux Input Selection - 0 - 5 - - MUXPOSSelect - - AIN0 - ADC AIN0 Pin - 0x0 - - - AIN1 - ADC AIN1 Pin - 0x1 - - - AIN2 - ADC AIN2 Pin - 0x2 - - - AIN3 - ADC AIN3 Pin - 0x3 - - - AIN4 - ADC AIN4 Pin - 0x4 - - - AIN5 - ADC AIN5 Pin - 0x5 - - - AIN6 - ADC AIN6 Pin - 0x6 - - - AIN7 - ADC AIN7 Pin - 0x7 - - - AIN8 - ADC AIN8 Pin - 0x8 - - - AIN9 - ADC AIN9 Pin - 0x9 - - - AIN10 - ADC AIN10 Pin - 0xA - - - AIN11 - ADC AIN11 Pin - 0xB - - - BANDGAP - Bandgap Voltage - 0x19 - - - SCALEDCOREVCC - 1/4 Scaled Core Supply - 0x1A - - - SCALEDIOVCC - 1/4 Scaled I/O Supply - 0x1B - - - - - MUXNEG - Negative Mux Input Selection - 8 - 5 - - MUXNEGSelect - - AIN0 - ADC AIN0 Pin - 0x0 - - - AIN1 - ADC AIN1 Pin - 0x1 - - - AIN2 - ADC AIN2 Pin - 0x2 - - - AIN3 - ADC AIN3 Pin - 0x3 - - - AIN4 - ADC AIN4 Pin - 0x4 - - - AIN5 - ADC AIN5 Pin - 0x5 - - - GND - Internal Ground - 0x18 - - - - - - - CTRLC - Control C - 0xA - 16 - 0x0000 - - - DIFFMODE - Differential Mode - 0 - 1 - - - LEFTADJ - Left-Adjusted Result - 1 - 1 - - - FREERUN - Free Running Mode - 2 - 1 - - - CORREN - Digital Correction Logic Enable - 3 - 1 - - - RESSEL - Conversion Result Resolution - 4 - 2 - - RESSELSelect - - 12BIT - 12-bit - 0x0 - - - 16BIT - 16-bit averaging mode - 0x1 - - - 10BIT - 10-bit - 0x2 - - - 8BIT - 8-bit - 0x3 - - - - - R2R - Rail-to-Rail mode enable - 7 - 1 - - - WINMODE - Window Monitor Mode - 8 - 3 - - WINMODESelect - - DISABLE - No window mode (default) - 0 - - - MODE1 - RESULT > WINLT - 1 - - - MODE2 - RESULT < WINUT - 2 - - - MODE3 - WINLT < RESULT < WINUT - 3 - - - MODE4 - !(WINLT < RESULT < WINUT) - 4 - - - - - - - AVGCTRL - Average Control - 0xC - 8 - 0x00 - - - SAMPLENUM - Number of Samples to be Collected - 0 - 4 - - SAMPLENUMSelect - - 1 - 1 sample - 0x0 - - - 2 - 2 samples - 0x1 - - - 4 - 4 samples - 0x2 - - - 8 - 8 samples - 0x3 - - - 16 - 16 samples - 0x4 - - - 32 - 32 samples - 0x5 - - - 64 - 64 samples - 0x6 - - - 128 - 128 samples - 0x7 - - - 256 - 256 samples - 0x8 - - - 512 - 512 samples - 0x9 - - - 1024 - 1024 samples - 0xA - - - - - ADJRES - Adjusting Result / Division Coefficient - 4 - 3 - - - - - SAMPCTRL - Sample Time Control - 0xD - 8 - 0x00 - - - SAMPLEN - Sampling Time Length - 0 - 6 - - - OFFCOMP - Comparator Offset Compensation Enable - 7 - 1 - - - - - WINLT - Window Monitor Lower Threshold - 0xE - 16 - 0x0000 - - - WINLT - Window Lower Threshold - 0 - 16 - - - - - WINUT - Window Monitor Upper Threshold - 0x10 - 16 - 0x0000 - - - WINUT - Window Upper Threshold - 0 - 16 - - - - - GAINCORR - Gain Correction - 0x12 - 16 - 0x0000 - - - GAINCORR - Gain Correction Value - 0 - 12 - - - - - OFFSETCORR - Offset Correction - 0x14 - 16 - 0x0000 - - - OFFSETCORR - Offset Correction Value - 0 - 12 - - - - - SWTRIG - Software Trigger - 0x18 - 8 - 0x00 - - - FLUSH - ADC Flush - 0 - 1 - - - START - Start ADC Conversion - 1 - 1 - - - - - DBGCTRL - Debug Control - 0x1C - 8 - 0x00 - - - DBGRUN - Debug Run - 0 - 1 - - - - - SYNCBUSY - Synchronization Busy - 0x20 - 16 - read-only - 0x0000 - - - SWRST - SWRST Synchronization Busy - 0 - 1 - - - ENABLE - ENABLE Synchronization Busy - 1 - 1 - - - INPUTCTRL - INPUTCTRL Synchronization Busy - 2 - 1 - - - CTRLC - CTRLC Synchronization Busy - 3 - 1 - - - AVGCTRL - AVGCTRL Synchronization Busy - 4 - 1 - - - SAMPCTRL - SAMPCTRL Synchronization Busy - 5 - 1 - - - WINLT - WINLT Synchronization Busy - 6 - 1 - - - WINUT - WINUT Synchronization Busy - 7 - 1 - - - GAINCORR - GAINCORR Synchronization Busy - 8 - 1 - - - OFFSETCORR - OFFSETCTRL Synchronization Busy - 9 - 1 - - - SWTRIG - SWTRG Synchronization Busy - 10 - 1 - - - - - RESULT - Result - 0x24 - 16 - read-only - 0x0000 - - - RESULT - Result Value - 0 - 16 - - - - - SEQCTRL - Sequence Control - 0x28 - 32 - 0x00000000 - - - SEQEN - Enable Positive Input in the Sequence - 0 - 32 - - - - - CALIB - Calibration - 0x2C - 16 - 0x0000 - - - BIASCOMP - Bias Comparator Scaling - 0 - 3 - - - BIASREFBUF - Bias Reference Buffer Scaling - 8 - 3 - - - - - - - CCL - U22251.0.1 - Configurable Custom Logic - CCL - CCL_ - 0x42005C00 - - 0 - 0x18 - registers - - - - CTRL - Control - 0x0 - 8 - 0x00 - - - SWRST - Software Reset - 0 - 1 - - - ENABLE - Enable - 1 - 1 - - - RUNSTDBY - Run during Standby - 6 - 1 - - - - - 2 - 1 - SEQCTRL[%s] - SEQ Control x - 0x4 - 8 - 0x00 - - - SEQSEL - Sequential Selection - 0 - 4 - - SEQSELSelect - - DISABLE - Sequential logic is disabled - 0 - - - DFF - D flip flop - 1 - - - JK - JK flip flop - 2 - - - LATCH - D latch - 3 - - - RS - RS latch - 4 - - - - - - - 4 - 4 - LUTCTRL[%s] - LUT Control x - 0x8 - 32 - 0x00000000 - - - ENABLE - LUT Enable - 1 - 1 - - - FILTSEL - Filter Selection - 4 - 2 - - FILTSELSelect - - DISABLE - Filter disabled - 0 - - - SYNCH - Synchronizer enabled - 1 - - - FILTER - Filter enabled - 2 - - - - - EDGESEL - Edge Selection - 7 - 1 - - - INSEL0 - Input Selection 0 - 8 - 4 - - INSEL0Select - - MASK - Masked input - 0 - - - FEEDBACK - Feedback input source - 1 - - - LINK - Linked LUT input source - 2 - - - EVENT - Event in put source - 3 - - - IO - I/O pin input source - 4 - - - AC - AC input source - 5 - - - TC - TC input source - 6 - - - ALTTC - Alternate TC input source - 7 - - - TCC - TCC input source - 8 - - - SERCOM - SERCOM inout source - 9 - - - - - INSEL1 - Input Selection 1 - 12 - 4 - - - INSEL2 - Input Selection 2 - 16 - 4 - - - INVEI - Input Event Invert - 20 - 1 - - - LUTEI - Event Input Enable - 21 - 1 - - - LUTEO - Event Output Enable - 22 - 1 - - - TRUTH - Truth Value - 24 - 8 - - - - - - - DIVAS - U22581.0.0 - Divide and Square Root Accelerator - DIVAS - DIVAS_ - 0x48000000 - - 0 - 0x1C - registers - - - - CTRLA - Control - 0x0 - 8 - 0x00 - - - SIGNED - Signed - 0 - 1 - - - DLZ - Disable Leading Zero Optimization - 1 - 1 - - - - - STATUS - Status - 0x4 - 8 - 0x00 - - - BUSY - DIVAS Accelerator Busy - 0 - 1 - - - DBZ - Writing a one to this bit clears DBZ to zero - 1 - 1 - - - - - DIVIDEND - Dividend - 0x8 - 32 - 0x00000000 - - - DIVIDEND - DIVIDEND - 0 - 32 - - - - - DIVISOR - Divisor - 0xC - 32 - 0x00000000 - - - DIVISOR - DIVISOR - 0 - 32 - - - - - RESULT - Result - 0x10 - 32 - read-only - 0x00000000 - - - RESULT - RESULT - 0 - 32 - - - - - REM - Remainder - 0x14 - 32 - read-only - 0x00000000 - - - REM - REM - 0 - 32 - - - - - SQRNUM - Square Root Input - 0x18 - 32 - 0x00000000 - - - SQRNUM - Square Root Input - 0 - 32 - - - - - - - DMAC - U22232.2.3 - Direct Memory Access Controller - DMAC - DMAC_ - 0x41006000 - - 0 - 0x50 - registers - - - DMAC - 7 - - - - CTRL - Control - 0x0 - 16 - 0x0000 - - - SWRST - Software Reset - 0 - 1 - - - DMAENABLE - DMA Enable - 1 - 1 - - - CRCENABLE - CRC Enable - 2 - 1 - - - LVLEN0 - Priority Level 0 Enable - 8 - 1 - - - LVLEN1 - Priority Level 1 Enable - 9 - 1 - - - LVLEN2 - Priority Level 2 Enable - 10 - 1 - - - LVLEN3 - Priority Level 3 Enable - 11 - 1 - - - - - CRCCTRL - CRC Control - 0x2 - 16 - 0x0000 - - - CRCBEATSIZE - CRC Beat Size - 0 - 2 - - CRCBEATSIZESelect - - BYTE - 8-bit bus transfer - 0x0 - - - HWORD - 16-bit bus transfer - 0x1 - - - WORD - 32-bit bus transfer - 0x2 - - - - - CRCPOLY - CRC Polynomial Type - 2 - 2 - - CRCPOLYSelect - - CRC16 - CRC-16 (CRC-CCITT) - 0x0 - - - CRC32 - CRC32 (IEEE 802.3) - 0x1 - - - - - CRCSRC - CRC Input Source - 8 - 6 - - CRCSRCSelect - - NOACT - No action - 0x00 - - - IO - I/O interface - 0x01 - - - - - - - CRCDATAIN - CRC Data Input - 0x4 - 32 - 0x00000000 - - - CRCDATAIN - CRC Data Input - 0 - 32 - - - - - CRCCHKSUM - CRC Checksum - 0x8 - 32 - 0x00000000 - - - CRCCHKSUM - CRC Checksum - 0 - 32 - - - - - CRCSTATUS - CRC Status - 0xC - 8 - 0x00 - - - CRCBUSY - CRC Module Busy - 0 - 1 - - - CRCZERO - CRC Zero - 1 - 1 - - - - - DBGCTRL - Debug Control - 0xD - 8 - 0x00 - - - DBGRUN - Debug Run - 0 - 1 - - - - - QOSCTRL - QOS Control - 0xE - 8 - 0x2A - - - WRBQOS - Write-Back Quality of Service - 0 - 2 - - WRBQOSSelect - - DISABLE - Background (no sensitive operation) - 0x0 - - - LOW - Sensitive Bandwidth - 0x1 - - - MEDIUM - Sensitive Latency - 0x2 - - - HIGH - Critical Latency - 0x3 - - - - - FQOS - Fetch Quality of Service - 2 - 2 - - FQOSSelect - - DISABLE - Background (no sensitive operation) - 0x0 - - - LOW - Sensitive Bandwidth - 0x1 - - - MEDIUM - Sensitive Latency - 0x2 - - - HIGH - Critical Latency - 0x3 - - - - - DQOS - Data Transfer Quality of Service - 4 - 2 - - DQOSSelect - - DISABLE - Background (no sensitive operation) - 0x0 - - - LOW - Sensitive Bandwidth - 0x1 - - - MEDIUM - Sensitive Latency - 0x2 - - - HIGH - Critical Latency - 0x3 - - - - - - - SWTRIGCTRL - Software Trigger Control - 0x10 - 32 - 0x00000000 - - - SWTRIG0 - Channel 0 Software Trigger - 0 - 1 - - - SWTRIG1 - Channel 1 Software Trigger - 1 - 1 - - - SWTRIG2 - Channel 2 Software Trigger - 2 - 1 - - - SWTRIG3 - Channel 3 Software Trigger - 3 - 1 - - - SWTRIG4 - Channel 4 Software Trigger - 4 - 1 - - - SWTRIG5 - Channel 5 Software Trigger - 5 - 1 - - - - - PRICTRL0 - Priority Control 0 - 0x14 - 32 - 0x00000000 - - - LVLPRI0 - Level 0 Channel Priority Number - 0 - 3 - - - RRLVLEN0 - Level 0 Round-Robin Scheduling Enable - 7 - 1 - - RRLVLEN0Select - - STATIC_LVL - Static arbitration scheme for channels with level 3 priority - 0x0 - - - ROUND_ROBIN_LVL - Round-robin arbitration scheme for channels with level 3 priority - 0x1 - - - - - LVLPRI1 - Level 1 Channel Priority Number - 8 - 3 - - - RRLVLEN1 - Level 1 Round-Robin Scheduling Enable - 15 - 1 - - - LVLPRI2 - Level 2 Channel Priority Number - 16 - 3 - - - RRLVLEN2 - Level 2 Round-Robin Scheduling Enable - 23 - 1 - - - LVLPRI3 - Level 3 Channel Priority Number - 24 - 3 - - - RRLVLEN3 - Level 3 Round-Robin Scheduling Enable - 31 - 1 - - - - - INTPEND - Interrupt Pending - 0x20 - 16 - 0x0000 - - - ID - Channel ID - 0 - 3 - - - TERR - Transfer Error - 8 - 1 - - - TCMPL - Transfer Complete - 9 - 1 - - - SUSP - Channel Suspend - 10 - 1 - - - FERR - Fetch Error - 13 - 1 - - - BUSY - Busy - 14 - 1 - - - PEND - Pending - 15 - 1 - - - - - INTSTATUS - Interrupt Status - 0x24 - 32 - read-only - 0x00000000 - - - CHINT0 - Channel 0 Pending Interrupt - 0 - 1 - - - CHINT1 - Channel 1 Pending Interrupt - 1 - 1 - - - CHINT2 - Channel 2 Pending Interrupt - 2 - 1 - - - CHINT3 - Channel 3 Pending Interrupt - 3 - 1 - - - CHINT4 - Channel 4 Pending Interrupt - 4 - 1 - - - CHINT5 - Channel 5 Pending Interrupt - 5 - 1 - - - - - BUSYCH - Busy Channels - 0x28 - 32 - read-only - 0x00000000 - - - BUSYCH0 - Busy Channel 0 - 0 - 1 - - - BUSYCH1 - Busy Channel 1 - 1 - 1 - - - BUSYCH2 - Busy Channel 2 - 2 - 1 - - - BUSYCH3 - Busy Channel 3 - 3 - 1 - - - BUSYCH4 - Busy Channel 4 - 4 - 1 - - - BUSYCH5 - Busy Channel 5 - 5 - 1 - - - - - PENDCH - Pending Channels - 0x2C - 32 - read-only - 0x00000000 - - - PENDCH0 - Pending Channel 0 - 0 - 1 - - - PENDCH1 - Pending Channel 1 - 1 - 1 - - - PENDCH2 - Pending Channel 2 - 2 - 1 - - - PENDCH3 - Pending Channel 3 - 3 - 1 - - - PENDCH4 - Pending Channel 4 - 4 - 1 - - - PENDCH5 - Pending Channel 5 - 5 - 1 - - - - - ACTIVE - Active Channel and Levels - 0x30 - 32 - read-only - 0x00000000 - - - LVLEX0 - Level 0 Channel Trigger Request Executing - 0 - 1 - - - LVLEX1 - Level 1 Channel Trigger Request Executing - 1 - 1 - - - LVLEX2 - Level 2 Channel Trigger Request Executing - 2 - 1 - - - LVLEX3 - Level 3 Channel Trigger Request Executing - 3 - 1 - - - ID - Active Channel ID - 8 - 5 - - - ABUSY - Active Channel Busy - 15 - 1 - - - BTCNT - Active Channel Block Transfer Count - 16 - 16 - - - - - BASEADDR - Descriptor Memory Section Base Address - 0x34 - 32 - 0x00000000 - - - BASEADDR - Descriptor Memory Base Address - 0 - 32 - - - - - WRBADDR - Write-Back Memory Section Base Address - 0x38 - 32 - 0x00000000 - - - WRBADDR - Write-Back Memory Base Address - 0 - 32 - - - - - CHID - Channel ID - 0x3F - 8 - 0x00 - - - ID - Channel ID - 0 - 3 - - - - - CHCTRLA - Channel Control A - 0x40 - 8 - 0x00 - - - SWRST - Channel Software Reset - 0 - 1 - - - ENABLE - Channel Enable - 1 - 1 - - - RUNSTDBY - Channel run in standby - 6 - 1 - - - - - CHCTRLB - Channel Control B - 0x44 - 32 - 0x00000000 - - - EVACT - Event Input Action - 0 - 3 - - EVACTSelect - - NOACT - No action - 0x0 - - - TRIG - Transfer and periodic transfer trigger - 0x1 - - - CTRIG - Conditional transfer trigger - 0x2 - - - CBLOCK - Conditional block transfer - 0x3 - - - SUSPEND - Channel suspend operation - 0x4 - - - RESUME - Channel resume operation - 0x5 - - - SSKIP - Skip next block suspend action - 0x6 - - - - - EVIE - Channel Event Input Enable - 3 - 1 - - - EVOE - Channel Event Output Enable - 4 - 1 - - - LVL - Channel Arbitration Level - 5 - 2 - - LVLSelect - - LVL0 - Channel Priority Level 0 - 0x0 - - - LVL1 - Channel Priority Level 1 - 0x1 - - - LVL2 - Channel Priority Level 2 - 0x2 - - - LVL3 - Channel Priority Level 3 - 0x3 - - - - - TRIGSRC - Trigger Source - 8 - 6 - - TRIGSRCSelect - - DISABLE - Only software/event triggers - 0x00 - - - SERCOM0_RX - SERCOM0 RX Trigger - 0x02 - - - SERCOM0_TX - SERCOM0 TX Trigger - 0x03 - - - SERCOM1_RX - SERCOM1 RX Trigger - 0x04 - - - SERCOM1_TX - SERCOM1 TX Trigger - 0x05 - - - SERCOM2_RX - SERCOM2 RX Trigger - 0x06 - - - SERCOM2_TX - SERCOM2 TX Trigger - 0x07 - - - SERCOM3_RX - SERCOM3 RX Trigger - 0x08 - - - SERCOM3_TX - SERCOM3 TX Trigger - 0x09 - - - TCC0_OVF - TCC0 Overflow Trigger - 0x10 - - - TCC0_MC0 - TCC0 Match/Compare 0 Trigger - 0x11 - - - TCC0_MC1 - TCC0 Match/Compare 1 Trigger - 0x12 - - - TCC0_MC2 - TCC0 Match/Compare 2 Trigger - 0x13 - - - TCC0_MC3 - TCC0 Match/Compare 3 Trigger - 0x14 - - - TCC1_OVF - TCC1 Overflow Trigger - 0x15 - - - TCC1_MC0 - TCC1 Match/Compare 0 Trigger - 0x16 - - - TCC1_MC1 - TCC1 Match/Compare 1 Trigger - 0x17 - - - TCC2_OVF - TCC2 Overflow Trigger - 0x18 - - - TCC2_MC0 - TCC2 Match/Compare 0 Trigger - 0x19 - - - TCC2_MC1 - TCC2 Match/Compare 1 Trigger - 0x1A - - - TC0_OVF - TC0 Overflow Trigger - 0x1B - - - TC0_MC0 - TC0 Match/Compare 0 Trigger - 0x1C - - - TC0_MC1 - TC0 Match/Compare 1 Trigger - 0x1D - - - TC1_OVF - TC1 Overflow Trigger - 0x1E - - - TC1_MC0 - TC1 Match/Compare 0 Trigger - 0x1F - - - TC1_MC1 - TC1 Match/Compare 1 Trigger - 0x20 - - - TC2_OVF - TC2 Overflow Trigger - 0x21 - - - TC2_MC0 - TC2 Match/Compare 0 Trigger - 0x22 - - - TC2_MC1 - TC2 Match/Compare 1 Trigger - 0x23 - - - TC3_OVF - TC3 Overflow Trigger - 0x24 - - - TC3_MC0 - TC3 Match/Compare 0 Trigger - 0x25 - - - TC3_MC1 - TC3 Match/Compare 1 Trigger - 0x26 - - - TC4_OVF - TC4 Overflow Trigger - 0x27 - - - TC4_MC0 - TC4 Match/Compare 0 Trigger - 0x28 - - - TC4_MC1 - TC4 Match/Compare 1 Trigger - 0x29 - - - ADC0_RESRDY - ADC0 Result Ready Trigger - 0x2A - - - PTC_EOC - PTC End of Conversion Trigger - 0x2E - - - PTC_WCOMP - PTC Window Compare Trigger - 0x2F - - - PTC_SEQ - PTC Sequence Trigger - 0x30 - - - - - TRIGACT - Trigger Action - 22 - 2 - - TRIGACTSelect - - BLOCK - One trigger required for each block transfer - 0x0 - - - BEAT - One trigger required for each beat transfer - 0x2 - - - TRANSACTION - One trigger required for each transaction - 0x3 - - - - - CMD - Software Command - 24 - 2 - - CMDSelect - - NOACT - No action - 0x0 - - - SUSPEND - Channel suspend operation - 0x1 - - - RESUME - Channel resume operation - 0x2 - - - - - - - CHINTENCLR - Channel Interrupt Enable Clear - 0x4C - 8 - 0x00 - - - TERR - Channel Transfer Error Interrupt Enable - 0 - 1 - - - TCMPL - Channel Transfer Complete Interrupt Enable - 1 - 1 - - - SUSP - Channel Suspend Interrupt Enable - 2 - 1 - - - - - CHINTENSET - Channel Interrupt Enable Set - 0x4D - 8 - 0x00 - - - TERR - Channel Transfer Error Interrupt Enable - 0 - 1 - - - TCMPL - Channel Transfer Complete Interrupt Enable - 1 - 1 - - - SUSP - Channel Suspend Interrupt Enable - 2 - 1 - - - - - CHINTFLAG - Channel Interrupt Flag Status and Clear - 0x4E - 8 - 0x00 - - - TERR - Channel Transfer Error - 0 - 1 - - - TCMPL - Channel Transfer Complete - 1 - 1 - - - SUSP - Channel Suspend - 2 - 1 - - - - - CHSTATUS - Channel Status - 0x4F - 8 - read-only - 0x00 - - - PEND - Channel Pending - 0 - 1 - - - BUSY - Channel Busy - 1 - 1 - - - FERR - Channel Fetch Error - 2 - 1 - - - - - - - DSU - U22092.5.0 - Device Service Unit - DSU - DSU_ - 0x41002000 - - 0 - 0x2000 - registers - - - - CTRL - Control - 0x0 - 8 - write-only - 0x00 - - - SWRST - Software Reset - 0 - 1 - - - CRC - 32-bit Cyclic Redundancy Code - 2 - 1 - - - MBIST - Memory built-in self-test - 3 - 1 - - - CE - Chip-Erase - 4 - 1 - - - ARR - Auxiliary Row Read - 6 - 1 - - - SMSA - Start Memory Stream Access - 7 - 1 - - - - - STATUSA - Status A - 0x1 - 8 - 0x00 - - - DONE - Done - 0 - 1 - - - CRSTEXT - CPU Reset Phase Extension - 1 - 1 - - - BERR - Bus Error - 2 - 1 - - - FAIL - Failure - 3 - 1 - - - PERR - Protection Error - 4 - 1 - - - - - STATUSB - Status B - 0x2 - 8 - read-only - 0x00 - - - PROT - Protected - 0 - 1 - - - DBGPRES - Debugger Present - 1 - 1 - - - DCCD0 - Debug Communication Channel 0 Dirty - 2 - 1 - - - DCCD1 - Debug Communication Channel 1 Dirty - 3 - 1 - - - HPE - Hot-Plugging Enable - 4 - 1 - - - - - STATUSC - Status C - 0x3 - 8 - read-only - 0x00 - - - STATE - State - 0 - 3 - - - - - ADDR - Address - 0x4 - 32 - 0x00000000 - - - AMOD - Access Mode - 0 - 2 - - - ADDR - Address - 2 - 30 - - - - - LENGTH - Length - 0x8 - 32 - 0x00000000 - - - LENGTH - Length - 2 - 30 - - - - - DATA - Data - 0xC - 32 - 0x00000000 - - - DATA - Data - 0 - 32 - - - - - 2 - 4 - DCC[%s] - Debug Communication Channel n - 0x10 - 32 - 0x00000000 - - - DATA - Data - 0 - 32 - - - - - DID - Device Identification - 0x18 - 32 - read-only - 0x1100050F - - - DEVSEL - Device Select - 0 - 8 - - - REVISION - Revision Number - 8 - 4 - - - DIE - Die Number - 12 - 4 - - - SERIES - Series - 16 - 6 - - SERIESSelect - - 0 - Cortex-M0+ processor, basic feature set - 0 - - - 1 - Cortex-M0+ processor, CAN - 1 - - - - - FAMILY - Family - 23 - 5 - - FAMILYSelect - - 0 - General purpose microcontroller - 0 - - - 1 - PicoPower - 1 - - - 2 - 5V Industrial - 2 - - - - - PROCESSOR - Processor - 28 - 4 - - PROCESSORSelect - - 0 - Cortex-M0 - 0 - - - 1 - Cortex-M0+ - 1 - - - 2 - Cortex-M3 - 2 - - - 3 - Cortex-M4 - 3 - - - - - - - 2 - 4 - DCFG[%s] - Device Configuration - 0xF0 - 32 - 0x00000000 - - - DCFG - Device Configuration - 0 - 32 - - - - - ENTRY0 - CoreSight ROM Table Entry 0 - 0x1000 - 32 - read-only - 0x9F0FC002 - - - EPRES - Entry Present - 0 - 1 - - - FMT - Format - 1 - 1 - - - ADDOFF - Address Offset - 12 - 20 - - - - - ENTRY1 - CoreSight ROM Table Entry 1 - 0x1004 - 32 - read-only - 0x00005002 - - - END - CoreSight ROM Table End - 0x1008 - 32 - read-only - 0x00000000 - - - END - End Marker - 0 - 32 - - - - - MEMTYPE - CoreSight ROM Table Memory Type - 0x1FCC - 32 - read-only - 0x00000000 - - - SMEMP - System Memory Present - 0 - 1 - - - - - PID4 - Peripheral Identification 4 - 0x1FD0 - 32 - read-only - 0x00000000 - - - JEPCC - JEP-106 Continuation Code - 0 - 4 - - - FKBC - 4KB count - 4 - 4 - - - - - PID5 - Peripheral Identification 5 - 0x1FD4 - 32 - read-only - 0x00000000 - - - PID6 - Peripheral Identification 6 - 0x1FD8 - 32 - read-only - 0x00000000 - - - PID7 - Peripheral Identification 7 - 0x1FDC - 32 - read-only - 0x00000000 - - - PID0 - Peripheral Identification 0 - 0x1FE0 - 32 - read-only - 0x000000D0 - - - PARTNBL - Part Number Low - 0 - 8 - - - - - PID1 - Peripheral Identification 1 - 0x1FE4 - 32 - read-only - 0x000000FC - - - PARTNBH - Part Number High - 0 - 4 - - - JEPIDCL - Low part of the JEP-106 Identity Code - 4 - 4 - - - - - PID2 - Peripheral Identification 2 - 0x1FE8 - 32 - read-only - 0x00000009 - - - JEPIDCH - JEP-106 Identity Code High - 0 - 3 - - - JEPU - JEP-106 Identity Code is used - 3 - 1 - - - REVISION - Revision Number - 4 - 4 - - - - - PID3 - Peripheral Identification 3 - 0x1FEC - 32 - read-only - 0x00000000 - - - CUSMOD - ARM CUSMOD - 0 - 4 - - - REVAND - Revision Number - 4 - 4 - - - - - CID0 - Component Identification 0 - 0x1FF0 - 32 - read-only - 0x0000000D - - - PREAMBLEB0 - Preamble Byte 0 - 0 - 8 - - - - - CID1 - Component Identification 1 - 0x1FF4 - 32 - read-only - 0x00000010 - - - PREAMBLE - Preamble - 0 - 4 - - - CCLASS - Component Class - 4 - 4 - - - - - CID2 - Component Identification 2 - 0x1FF8 - 32 - read-only - 0x00000005 - - - PREAMBLEB2 - Preamble Byte 2 - 0 - 8 - - - - - CID3 - Component Identification 3 - 0x1FFC - 32 - read-only - 0x000000B1 - - - PREAMBLEB3 - Preamble Byte 3 - 0 - 8 - - - - - - - EIC - U22542.0.4 - External Interrupt Controller - EIC - EIC_ - 0x40002800 - - 0 - 0x24 - registers - - - EIC - 3 - - - - CTRLA - Control - 0x0 - 8 - 0x00 - - - SWRST - Software Reset - 0 - 1 - - - ENABLE - Enable - 1 - 1 - - - CKSEL - Clock Selection - 4 - 1 - - CKSELSelect - - CLK_GCLK - Clocked by GCLK - 0 - - - CLK_ULP32K - Clocked by ULP32K - 1 - - - - - - - NMICTRL - NMI Control - 0x1 - 8 - 0x00 - - - NMISENSE - NMI Input Sense Configuration - 0 - 3 - - NMISENSESelect - - NONE - No detection - 0 - - - RISE - Rising-edge detection - 1 - - - FALL - Falling-edge detection - 2 - - - BOTH - Both-edges detection - 3 - - - HIGH - High-level detection - 4 - - - LOW - Low-level detection - 5 - - - - - NMIFILTEN - NMI Filter Enable - 3 - 1 - - - NMIASYNCH - NMI Asynchronous edge Detection Enable - 4 - 1 - - NMIASYNCHSelect - - SYNC - Edge detection is clock synchronously operated - 0 - - - ASYNC - Edge detection is clock asynchronously operated - 1 - - - - - - - NMIFLAG - NMI Interrupt Flag - 0x2 - 16 - 0x0000 - - - NMI - NMI Interrupt Flag - 0 - 1 - - - - - SYNCBUSY - Syncbusy register - 0x4 - 32 - read-only - 0x00000000 - - - SWRST - Software reset synchronisation - 0 - 1 - - - ENABLE - Enable synchronisation - 1 - 1 - - - - - EVCTRL - Event Control - 0x8 - 32 - 0x00000000 - - - EXTINTEO - External Interrupt Event Output Enable - 0 - 16 - - - - - INTENCLR - Interrupt Enable Clear - 0xC - 32 - 0x00000000 - - - EXTINT - External Interrupt Disable - 0 - 16 - - - - - INTENSET - Interrupt Enable Set - 0x10 - 32 - 0x00000000 - - - EXTINT - External Interrupt Enable - 0 - 16 - - - - - INTFLAG - Interrupt Flag Status and Clear - 0x14 - 32 - 0x00000000 - - - EXTINT - External Interrupt Flag - 0 - 16 - - - - - ASYNCH - EIC Asynchronous edge Detection Enable - 0x18 - 32 - 0x00000000 - - - ASYNCH - EIC Asynchronous edge Detection Enable - 0 - 16 - - ASYNCHSelect - - SYNC - Edge detection is clock synchronously operated - 0 - - - ASYNC - Edge detection is clock asynchronously operated - 1 - - - - - - - 2 - 4 - CONFIG[%s] - Configuration n - 0x1C - 32 - 0x00000000 - - - SENSE0 - Input Sense Configuration 0 - 0 - 3 - - SENSE0Select - - NONE - No detection - 0 - - - RISE - Rising edge detection - 1 - - - FALL - Falling edge detection - 2 - - - BOTH - Both edges detection - 3 - - - HIGH - High level detection - 4 - - - LOW - Low level detection - 5 - - - - - FILTEN0 - Filter Enable 0 - 3 - 1 - - - SENSE1 - Input Sense Configuration 1 - 4 - 3 - - SENSE1Select - - NONE - No detection - 0 - - - RISE - Rising edge detection - 1 - - - FALL - Falling edge detection - 2 - - - BOTH - Both edges detection - 3 - - - HIGH - High level detection - 4 - - - LOW - Low level detection - 5 - - - - - FILTEN1 - Filter Enable 1 - 7 - 1 - - - SENSE2 - Input Sense Configuration 2 - 8 - 3 - - SENSE2Select - - NONE - No detection - 0 - - - RISE - Rising edge detection - 1 - - - FALL - Falling edge detection - 2 - - - BOTH - Both edges detection - 3 - - - HIGH - High level detection - 4 - - - LOW - Low level detection - 5 - - - - - FILTEN2 - Filter Enable 2 - 11 - 1 - - - SENSE3 - Input Sense Configuration 3 - 12 - 3 - - SENSE3Select - - NONE - No detection - 0 - - - RISE - Rising edge detection - 1 - - - FALL - Falling edge detection - 2 - - - BOTH - Both edges detection - 3 - - - HIGH - High level detection - 4 - - - LOW - Low level detection - 5 - - - - - FILTEN3 - Filter Enable 3 - 15 - 1 - - - SENSE4 - Input Sense Configuration 4 - 16 - 3 - - SENSE4Select - - NONE - No detection - 0 - - - RISE - Rising edge detection - 1 - - - FALL - Falling edge detection - 2 - - - BOTH - Both edges detection - 3 - - - HIGH - High level detection - 4 - - - LOW - Low level detection - 5 - - - - - FILTEN4 - Filter Enable 4 - 19 - 1 - - - SENSE5 - Input Sense Configuration 5 - 20 - 3 - - SENSE5Select - - NONE - No detection - 0 - - - RISE - Rising edge detection - 1 - - - FALL - Falling edge detection - 2 - - - BOTH - Both edges detection - 3 - - - HIGH - High level detection - 4 - - - LOW - Low level detection - 5 - - - - - FILTEN5 - Filter Enable 5 - 23 - 1 - - - SENSE6 - Input Sense Configuration 6 - 24 - 3 - - SENSE6Select - - NONE - No detection - 0 - - - RISE - Rising edge detection - 1 - - - FALL - Falling edge detection - 2 - - - BOTH - Both edges detection - 3 - - - HIGH - High level detection - 4 - - - LOW - Low level detection - 5 - - - - - FILTEN6 - Filter Enable 6 - 27 - 1 - - - SENSE7 - Input Sense Configuration 7 - 28 - 3 - - SENSE7Select - - NONE - No detection - 0 - - - RISE - Rising edge detection - 1 - - - FALL - Falling edge detection - 2 - - - BOTH - Both edges detection - 3 - - - HIGH - High level detection - 4 - - - LOW - Low level detection - 5 - - - - - FILTEN7 - Filter Enable 7 - 31 - 1 - - - - - - - EVSYS - U22561.0.2 - Event System Interface - EVSYS - EVSYS_ - 0x42000000 - - 0 - 0x19C - registers - - - EVSYS - 8 - - - - CTRLA - Control - 0x0 - 8 - 0x00 - - - SWRST - Software Reset - 0 - 1 - - - - - CHSTATUS - Channel Status - 0xC - 32 - read-only - 0x00000000 - - - USRRDY0 - Channel 0 User Ready - 0 - 1 - - - USRRDY1 - Channel 1 User Ready - 1 - 1 - - - USRRDY2 - Channel 2 User Ready - 2 - 1 - - - USRRDY3 - Channel 3 User Ready - 3 - 1 - - - USRRDY4 - Channel 4 User Ready - 4 - 1 - - - USRRDY5 - Channel 5 User Ready - 5 - 1 - - - CHBUSY0 - Channel 0 Busy - 16 - 1 - - - CHBUSY1 - Channel 1 Busy - 17 - 1 - - - CHBUSY2 - Channel 2 Busy - 18 - 1 - - - CHBUSY3 - Channel 3 Busy - 19 - 1 - - - CHBUSY4 - Channel 4 Busy - 20 - 1 - - - CHBUSY5 - Channel 5 Busy - 21 - 1 - - - - - INTENCLR - Interrupt Enable Clear - 0x10 - 32 - 0x00000000 - - - OVR0 - Channel 0 Overrun Interrupt Enable - 0 - 1 - - - OVR1 - Channel 1 Overrun Interrupt Enable - 1 - 1 - - - OVR2 - Channel 2 Overrun Interrupt Enable - 2 - 1 - - - OVR3 - Channel 3 Overrun Interrupt Enable - 3 - 1 - - - OVR4 - Channel 4 Overrun Interrupt Enable - 4 - 1 - - - OVR5 - Channel 5 Overrun Interrupt Enable - 5 - 1 - - - EVD0 - Channel 0 Event Detection Interrupt Enable - 16 - 1 - - - EVD1 - Channel 1 Event Detection Interrupt Enable - 17 - 1 - - - EVD2 - Channel 2 Event Detection Interrupt Enable - 18 - 1 - - - EVD3 - Channel 3 Event Detection Interrupt Enable - 19 - 1 - - - EVD4 - Channel 4 Event Detection Interrupt Enable - 20 - 1 - - - EVD5 - Channel 5 Event Detection Interrupt Enable - 21 - 1 - - - - - INTENSET - Interrupt Enable Set - 0x14 - 32 - 0x00000000 - - - OVR0 - Channel 0 Overrun Interrupt Enable - 0 - 1 - - - OVR1 - Channel 1 Overrun Interrupt Enable - 1 - 1 - - - OVR2 - Channel 2 Overrun Interrupt Enable - 2 - 1 - - - OVR3 - Channel 3 Overrun Interrupt Enable - 3 - 1 - - - OVR4 - Channel 4 Overrun Interrupt Enable - 4 - 1 - - - OVR5 - Channel 5 Overrun Interrupt Enable - 5 - 1 - - - EVD0 - Channel 0 Event Detection Interrupt Enable - 16 - 1 - - - EVD1 - Channel 1 Event Detection Interrupt Enable - 17 - 1 - - - EVD2 - Channel 2 Event Detection Interrupt Enable - 18 - 1 - - - EVD3 - Channel 3 Event Detection Interrupt Enable - 19 - 1 - - - EVD4 - Channel 4 Event Detection Interrupt Enable - 20 - 1 - - - EVD5 - Channel 5 Event Detection Interrupt Enable - 21 - 1 - - - - - INTFLAG - Interrupt Flag Status and Clear - 0x18 - 32 - 0x00000000 - - - OVR0 - Channel 0 Overrun - 0 - 1 - - - OVR1 - Channel 1 Overrun - 1 - 1 - - - OVR2 - Channel 2 Overrun - 2 - 1 - - - OVR3 - Channel 3 Overrun - 3 - 1 - - - OVR4 - Channel 4 Overrun - 4 - 1 - - - OVR5 - Channel 5 Overrun - 5 - 1 - - - EVD0 - Channel 0 Event Detection - 16 - 1 - - - EVD1 - Channel 1 Event Detection - 17 - 1 - - - EVD2 - Channel 2 Event Detection - 18 - 1 - - - EVD3 - Channel 3 Event Detection - 19 - 1 - - - EVD4 - Channel 4 Event Detection - 20 - 1 - - - EVD5 - Channel 5 Event Detection - 21 - 1 - - - - - SWEVT - Software Event - 0x1C - 32 - write-only - 0x00000000 - - - CHANNEL0 - Channel 0 Software Selection - 0 - 1 - - - CHANNEL1 - Channel 1 Software Selection - 1 - 1 - - - CHANNEL2 - Channel 2 Software Selection - 2 - 1 - - - CHANNEL3 - Channel 3 Software Selection - 3 - 1 - - - CHANNEL4 - Channel 4 Software Selection - 4 - 1 - - - CHANNEL5 - Channel 5 Software Selection - 5 - 1 - - - - - 6 - 4 - CHANNEL[%s] - Channel n - 0x20 - 32 - 0x00008000 - - - EVGEN - Event Generator Selection - 0 - 7 - - - PATH - Path Selection - 8 - 2 - - PATHSelect - - SYNCHRONOUS - Synchronous path - 0 - - - RESYNCHRONIZED - Resynchronized path - 1 - - - ASYNCHRONOUS - Asynchronous path - 2 - - - - - EDGSEL - Edge Detection Selection - 10 - 2 - - EDGSELSelect - - NO_EVT_OUTPUT - No event output when using the resynchronized or synchronous path - 0 - - - RISING_EDGE - Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path - 1 - - - FALLING_EDGE - Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path - 2 - - - BOTH_EDGES - Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path - 3 - - - - - RUNSTDBY - Run in standby - 14 - 1 - - - ONDEMAND - Generic Clock On Demand - 15 - 1 - - - - - 47 - 4 - USER[%s] - User Multiplexer n - 0x80 - 32 - 0x00000000 - - - CHANNEL - Channel Event Selection - 0 - 4 - - - - - - - FREQM - U22571.0.1 - Frequency Meter - FREQM - FREQM_ - 0x40002C00 - - 0 - 0x14 - registers - - - FREQM - 4 - - - - CTRLA - Control A Register - 0x0 - 8 - 0x00 - - - SWRST - Software Reset - 0 - 1 - - - ENABLE - Enable - 1 - 1 - - - - - CTRLB - Control B Register - 0x1 - 8 - write-only - 0x00 - - - START - Start Measurement - 0 - 1 - - - - - CFGA - Config A register - 0x2 - 16 - 0x0000 - - - REFNUM - Number of Reference Clock Cycles - 0 - 8 - - - - - INTENCLR - Interrupt Enable Clear Register - 0x8 - 8 - 0x00 - - - DONE - Measurement Done Interrupt Enable - 0 - 1 - - - - - INTENSET - Interrupt Enable Set Register - 0x9 - 8 - 0x00 - - - DONE - Measurement Done Interrupt Enable - 0 - 1 - - - - - INTFLAG - Interrupt Flag Register - 0xA - 8 - 0x00 - - - DONE - Measurement Done - 0 - 1 - - - - - STATUS - Status Register - 0xB - 8 - 0x00 - - - BUSY - FREQM Status - 0 - 1 - - - OVF - Sticky Count Value Overflow - 1 - 1 - - - - - SYNCBUSY - Synchronization Busy Register - 0xC - 32 - read-only - 0x00000000 - - - SWRST - Software Reset - 0 - 1 - - - ENABLE - Enable - 1 - 1 - - - - - VALUE - Count Value Register - 0x10 - 32 - read-only - 0x00000000 - - - VALUE - Measurement Value - 0 - 24 - - - - - - - GCLK - U21221.1.1 - Generic Clock Generator - GCLK - GCLK_ - 0x40001C00 - - 0 - 0x184 - registers - - - - CTRLA - Control - 0x0 - 8 - 0x00 - - - SWRST - Software Reset - 0 - 1 - - - - - SYNCBUSY - Synchronization Busy - 0x4 - 32 - read-only - 0x00000000 - - - SWRST - Software Reset Synchroniation Busy bit - 0 - 1 - - - GENCTRL0 - Generic Clock Generator Control 0 Synchronization Busy bits - 2 - 1 - - GENCTRL0Select - - GCLK0 - Generic clock generator 0 - 0x1 - - - GCLK1 - Generic clock generator 1 - 0x2 - - - GCLK2 - Generic clock generator 2 - 0x4 - - - GCLK3 - Generic clock generator 3 - 0x8 - - - GCLK4 - Generic clock generator 4 - 0x10 - - - GCLK5 - Generic clock generator 5 - 0x20 - - - GCLK6 - Generic clock generator 6 - 0x40 - - - GCLK7 - Generic clock generator 7 - 0x80 - - - GCLK8 - Generic clock generator 8 - 0x100 - - - - - GENCTRL1 - Generic Clock Generator Control 1 Synchronization Busy bits - 3 - 1 - - GENCTRL1Select - - GCLK0 - Generic clock generator 0 - 0x1 - - - GCLK1 - Generic clock generator 1 - 0x2 - - - GCLK2 - Generic clock generator 2 - 0x4 - - - GCLK3 - Generic clock generator 3 - 0x8 - - - GCLK4 - Generic clock generator 4 - 0x10 - - - GCLK5 - Generic clock generator 5 - 0x20 - - - GCLK6 - Generic clock generator 6 - 0x40 - - - GCLK7 - Generic clock generator 7 - 0x80 - - - GCLK8 - Generic clock generator 8 - 0x100 - - - - - GENCTRL2 - Generic Clock Generator Control 2 Synchronization Busy bits - 4 - 1 - - GENCTRL2Select - - GCLK0 - Generic clock generator 0 - 0x1 - - - GCLK1 - Generic clock generator 1 - 0x2 - - - GCLK2 - Generic clock generator 2 - 0x4 - - - GCLK3 - Generic clock generator 3 - 0x8 - - - GCLK4 - Generic clock generator 4 - 0x10 - - - GCLK5 - Generic clock generator 5 - 0x20 - - - GCLK6 - Generic clock generator 6 - 0x40 - - - GCLK7 - Generic clock generator 7 - 0x80 - - - GCLK8 - Generic clock generator 8 - 0x100 - - - - - GENCTRL3 - Generic Clock Generator Control 3 Synchronization Busy bits - 5 - 1 - - GENCTRL3Select - - GCLK0 - Generic clock generator 0 - 0x1 - - - GCLK1 - Generic clock generator 1 - 0x2 - - - GCLK2 - Generic clock generator 2 - 0x4 - - - GCLK3 - Generic clock generator 3 - 0x8 - - - GCLK4 - Generic clock generator 4 - 0x10 - - - GCLK5 - Generic clock generator 5 - 0x20 - - - GCLK6 - Generic clock generator 6 - 0x40 - - - GCLK7 - Generic clock generator 7 - 0x80 - - - GCLK8 - Generic clock generator 8 - 0x100 - - - - - GENCTRL4 - Generic Clock Generator Control 4 Synchronization Busy bits - 6 - 1 - - GENCTRL4Select - - GCLK0 - Generic clock generator 0 - 0x1 - - - GCLK1 - Generic clock generator 1 - 0x2 - - - GCLK2 - Generic clock generator 2 - 0x4 - - - GCLK3 - Generic clock generator 3 - 0x8 - - - GCLK4 - Generic clock generator 4 - 0x10 - - - GCLK5 - Generic clock generator 5 - 0x20 - - - GCLK6 - Generic clock generator 6 - 0x40 - - - GCLK7 - Generic clock generator 7 - 0x80 - - - GCLK8 - Generic clock generator 8 - 0x100 - - - - - GENCTRL5 - Generic Clock Generator Control 5 Synchronization Busy bits - 7 - 1 - - GENCTRL5Select - - GCLK0 - Generic clock generator 0 - 0x1 - - - GCLK1 - Generic clock generator 1 - 0x2 - - - GCLK2 - Generic clock generator 2 - 0x4 - - - GCLK3 - Generic clock generator 3 - 0x8 - - - GCLK4 - Generic clock generator 4 - 0x10 - - - GCLK5 - Generic clock generator 5 - 0x20 - - - GCLK6 - Generic clock generator 6 - 0x40 - - - GCLK7 - Generic clock generator 7 - 0x80 - - - GCLK8 - Generic clock generator 8 - 0x100 - - - - - GENCTRL6 - Generic Clock Generator Control 6 Synchronization Busy bits - 8 - 1 - - GENCTRL6Select - - GCLK0 - Generic clock generator 0 - 0x1 - - - GCLK1 - Generic clock generator 1 - 0x2 - - - GCLK2 - Generic clock generator 2 - 0x4 - - - GCLK3 - Generic clock generator 3 - 0x8 - - - GCLK4 - Generic clock generator 4 - 0x10 - - - GCLK5 - Generic clock generator 5 - 0x20 - - - GCLK6 - Generic clock generator 6 - 0x40 - - - GCLK7 - Generic clock generator 7 - 0x80 - - - GCLK8 - Generic clock generator 8 - 0x100 - - - - - GENCTRL7 - Generic Clock Generator Control 7 Synchronization Busy bits - 9 - 1 - - GENCTRL7Select - - GCLK0 - Generic clock generator 0 - 0x1 - - - GCLK1 - Generic clock generator 1 - 0x2 - - - GCLK2 - Generic clock generator 2 - 0x4 - - - GCLK3 - Generic clock generator 3 - 0x8 - - - GCLK4 - Generic clock generator 4 - 0x10 - - - GCLK5 - Generic clock generator 5 - 0x20 - - - GCLK6 - Generic clock generator 6 - 0x40 - - - GCLK7 - Generic clock generator 7 - 0x80 - - - GCLK8 - Generic clock generator 8 - 0x100 - - - - - GENCTRL8 - Generic Clock Generator Control 8 Synchronization Busy bits - 10 - 1 - - GENCTRL8Select - - GCLK0 - Generic clock generator 0 - 0x1 - - - GCLK1 - Generic clock generator 1 - 0x2 - - - GCLK2 - Generic clock generator 2 - 0x4 - - - GCLK3 - Generic clock generator 3 - 0x8 - - - GCLK4 - Generic clock generator 4 - 0x10 - - - GCLK5 - Generic clock generator 5 - 0x20 - - - GCLK6 - Generic clock generator 6 - 0x40 - - - GCLK7 - Generic clock generator 7 - 0x80 - - - GCLK8 - Generic clock generator 8 - 0x100 - - - - - - - 9 - 4 - GENCTRL[%s] - Generic Clock Generator Control - 0x20 - 32 - 0x00000000 - - - SRC - Source Select - 0 - 3 - - SRCSelect - - XOSC - XOSC oscillator output - 0 - - - GCLKIN - Generator input pad - 1 - - - GCLKGEN1 - Generic clock generator 1 output - 2 - - - OSCULP32K - OSCULP32K oscillator output - 3 - - - OSC32K - OSC32K oscillator output - 4 - - - XOSC32K - XOSC32K oscillator output - 5 - - - OSC48M - OSC48M oscillator output - 6 - - - DPLL96M - DPLL96M output - 7 - - - - - GENEN - Generic Clock Generator Enable - 8 - 1 - - - IDC - Improve Duty Cycle - 9 - 1 - - - OOV - Output Off Value - 10 - 1 - - - OE - Output Enable - 11 - 1 - - - DIVSEL - Divide Selection - 12 - 1 - - DIVSELSelect - - DIV1 - Divide input directly by divider factor - 0x0 - - - DIV2 - Divide input by 2^(divider factor+ 1) - 0x1 - - - - - RUNSTDBY - Run in Standby - 13 - 1 - - - DIV - Division Factor - 16 - 16 - - - - - 41 - 4 - PCHCTRL[%s] - Peripheral Clock Control - 0x80 - 32 - 0x00000000 - - - GEN - Generic Clock Generator - 0 - 4 - - GENSelect - - GCLK0 - Generic clock generator 0 - 0x0 - - - GCLK1 - Generic clock generator 1 - 0x1 - - - GCLK2 - Generic clock generator 2 - 0x2 - - - GCLK3 - Generic clock generator 3 - 0x3 - - - GCLK4 - Generic clock generator 4 - 0x4 - - - GCLK5 - Generic clock generator 5 - 0x5 - - - GCLK6 - Generic clock generator 6 - 0x6 - - - GCLK7 - Generic clock generator 7 - 0x7 - - - GCLK8 - Generic clock generator 8 - 0x8 - - - - - CHEN - Channel Enable - 6 - 1 - - - WRTLOCK - Write Lock - 7 - 1 - - - - - - - HMATRIXHS - I76382.1.3 - HSB Matrix - HMATRIXB - HMATRIXB_ - 0x4100A000 - - 0 - 0x168 - registers - - - - 16 - 4 - MCFG[%s] - Master Configuration - 0x0 - 32 - 0x00000002 - - - ULBT - Undefined Length Burst Type - 0 - 3 - - ULBTSelect - - INFINITE - Infinite Length - 0 - - - SINGLE - Single Access - 1 - - - FOUR_BEAT - Four Beat Burst - 2 - - - EIGHT_BEAT - Eight Beat Burst - 3 - - - SIXTEEN_BEAT - Sixteen Beat Burst - 4 - - - - - - - 16 - 4 - SCFG[%s] - Slave Configuration - 0x40 - 32 - 0x00000010 - - - SLOT_CYCLE - Maximum Number of Allowed Cycles for a Burst - 0 - 8 - - - DEFMSTR_TYPE - Default Master Type - 16 - 2 - - DEFMSTR_TYPESelect - - NO_DEFAULT - No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. - 0 - - - LAST_DEFAULT - Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. - 1 - - - FIXED_DEFAULT - Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave. - 2 - - - - - FIXED_DEFMSTR - Fixed Index of Default Master - 18 - 4 - - - ARBT - Arbitration Type - 24 - 1 - - ARBTSelect - - ROUND_ROBIN - Round-Robin Arbitration - 0 - - - FIXED_PRIORITY - Fixed Priority Arbitration - 1 - - - - - - - 4 - 0x8 - PRS[%s] - - 0x080 - - PRAS - Priority A for Slave - 0x0 - 32 - 0x00000000 - - - M0PR - Master 0 Priority - 0 - 4 - - - M1PR - Master 1 Priority - 4 - 4 - - - M2PR - Master 2 Priority - 8 - 4 - - - M3PR - Master 3 Priority - 12 - 4 - - - M4PR - Master 4 Priority - 16 - 4 - - - M5PR - Master 5 Priority - 20 - 4 - - - M6PR - Master 6 Priority - 24 - 4 - - - M7PR - Master 7 Priority - 28 - 4 - - - - - PRBS - Priority B for Slave - 0x4 - 32 - 0x00000000 - - - M8PR - Master 8 Priority - 0 - 4 - - - M9PR - Master 9 Priority - 4 - 4 - - - M10PR - Master 10 Priority - 8 - 4 - - - M11PR - Master 11 Priority - 12 - 4 - - - M12PR - Master 12 Priority - 16 - 4 - - - M13PR - Master 13 Priority - 20 - 4 - - - M14PR - Master 14 Priority - 24 - 4 - - - M15PR - Master 15 Priority - 28 - 4 - - - - - - MRCR - Master Remap Control - 0x100 - 32 - 0x00000000 - - - RCB0 - Remap Command Bit for Master 0 - 0 - 1 - - RCB0Select - - DIS - Disable remapped address decoding for master - 0 - - - ENA - Enable remapped address decoding for master - 1 - - - - - RCB1 - Remap Command Bit for Master 1 - 1 - 1 - - RCB1Select - - DIS - Disable remapped address decoding for master - 0 - - - ENA - Enable remapped address decoding for master - 1 - - - - - RCB2 - Remap Command Bit for Master 2 - 2 - 1 - - RCB2Select - - DIS - Disable remapped address decoding for master - 0 - - - ENA - Enable remapped address decoding for master - 1 - - - - - RCB3 - Remap Command Bit for Master 3 - 3 - 1 - - RCB3Select - - DIS - Disable remapped address decoding for master - 0 - - - ENA - Enable remapped address decoding for master - 1 - - - - - RCB4 - Remap Command Bit for Master 4 - 4 - 1 - - RCB4Select - - DIS - Disable remapped address decoding for master - 0 - - - ENA - Enable remapped address decoding for master - 1 - - - - - RCB5 - Remap Command Bit for Master 5 - 5 - 1 - - RCB5Select - - DIS - Disable remapped address decoding for master - 0 - - - ENA - Enable remapped address decoding for master - 1 - - - - - RCB6 - Remap Command Bit for Master 6 - 6 - 1 - - RCB6Select - - DIS - Disable remapped address decoding for master - 0 - - - ENA - Enable remapped address decoding for master - 1 - - - - - RCB7 - Remap Command Bit for Master 7 - 7 - 1 - - RCB7Select - - DIS - Disable remapped address decoding for master - 0 - - - ENA - Enable remapped address decoding for master - 1 - - - - - RCB8 - Remap Command Bit for Master 8 - 8 - 1 - - RCB8Select - - DIS - Disable remapped address decoding for master - 0 - - - ENA - Enable remapped address decoding for master - 1 - - - - - RCB9 - Remap Command Bit for Master 9 - 9 - 1 - - RCB9Select - - DIS - Disable remapped address decoding for master - 0 - - - ENA - Enable remapped address decoding for master - 1 - - - - - RCB10 - Remap Command Bit for Master 10 - 10 - 1 - - RCB10Select - - DIS - Disable remapped address decoding for master - 0 - - - ENA - Enable remapped address decoding for master - 1 - - - - - RCB11 - Remap Command Bit for Master 11 - 11 - 1 - - RCB11Select - - DIS - Disable remapped address decoding for master - 0 - - - ENA - Enable remapped address decoding for master - 1 - - - - - RCB12 - Remap Command Bit for Master 12 - 12 - 1 - - RCB12Select - - DIS - Disable remapped address decoding for master - 0 - - - ENA - Enable remapped address decoding for master - 1 - - - - - RCB13 - Remap Command Bit for Master 13 - 13 - 1 - - RCB13Select - - DIS - Disable remapped address decoding for master - 0 - - - ENA - Enable remapped address decoding for master - 1 - - - - - RCB14 - Remap Command Bit for Master 14 - 14 - 1 - - RCB14Select - - DIS - Disable remapped address decoding for master - 0 - - - ENA - Enable remapped address decoding for master - 1 - - - - - RCB15 - Remap Command Bit for Master 15 - 15 - 1 - - RCB15Select - - DIS - Disable remapped address decoding for master - 0 - - - ENA - Enable remapped address decoding for master - 1 - - - - - - - 16 - 4 - SFR[%s] - Special Function - 0x110 - 32 - 0x00000000 - - - SFR - Special Function Register - 0 - 32 - - - - - - - MCLK - U22342.0.0 - Main Clock - MCLK - MCLK_ - 0x40000800 - - 0 - 0x20 - registers - - - - INTENCLR - Interrupt Enable Clear - 0x1 - 8 - 0x00 - - - CKRDY - Clock Ready Interrupt Enable - 0 - 1 - - - - - INTENSET - Interrupt Enable Set - 0x2 - 8 - 0x00 - - - CKRDY - Clock Ready Interrupt Enable - 0 - 1 - - - - - INTFLAG - Interrupt Flag Status and Clear - 0x3 - 8 - 0x01 - - - CKRDY - Clock Ready - 0 - 1 - - - - - CPUDIV - CPU Clock Division - 0x4 - 8 - 0x01 - - - CPUDIV - CPU Clock Division Factor - 0 - 8 - - CPUDIVSelect - - DIV1 - Divide by 1 - 0x01 - - - DIV2 - Divide by 2 - 0x02 - - - DIV4 - Divide by 4 - 0x04 - - - DIV8 - Divide by 8 - 0x08 - - - DIV16 - Divide by 16 - 0x10 - - - DIV32 - Divide by 32 - 0x20 - - - DIV64 - Divide by 64 - 0x40 - - - DIV128 - Divide by 128 - 0x80 - - - - - - - AHBMASK - AHB Mask - 0x10 - 32 - 0x00001CFF - - - HPB0_ - HPB0 AHB Clock Mask - 0 - 1 - - - HPB1_ - HPB1 AHB Clock Mask - 1 - 1 - - - HPB2_ - HPB2 AHB Clock Mask - 2 - 1 - - - DSU_ - DSU AHB Clock Mask - 3 - 1 - - - HMATRIXHS_ - HMATRIXHS AHB Clock Mask - 4 - 1 - - - NVMCTRL_ - NVMCTRL AHB Clock Mask - 5 - 1 - - - HSRAM_ - HSRAM AHB Clock Mask - 6 - 1 - - - DMAC_ - DMAC AHB Clock Mask - 7 - 1 - - - PAC_ - PAC AHB Clock Mask - 10 - 1 - - - NVMCTRL_PICACHU_ - NVMCTRL_PICACHU AHB Clock Mask - 11 - 1 - - - DIVAS_ - DIVAS AHB Clock Mask - 12 - 1 - - - - - APBAMASK - APBA Mask - 0x14 - 32 - 0x00000FFF - - - PAC_ - PAC APB Clock Enable - 0 - 1 - - - PM_ - PM APB Clock Enable - 1 - 1 - - - MCLK_ - MCLK APB Clock Enable - 2 - 1 - - - RSTC_ - RSTC APB Clock Enable - 3 - 1 - - - OSCCTRL_ - OSCCTRL APB Clock Enable - 4 - 1 - - - OSC32KCTRL_ - OSC32KCTRL APB Clock Enable - 5 - 1 - - - SUPC_ - SUPC APB Clock Enable - 6 - 1 - - - GCLK_ - GCLK APB Clock Enable - 7 - 1 - - - WDT_ - WDT APB Clock Enable - 8 - 1 - - - RTC_ - RTC APB Clock Enable - 9 - 1 - - - EIC_ - EIC APB Clock Enable - 10 - 1 - - - FREQM_ - FREQM APB Clock Enable - 11 - 1 - - - - - APBBMASK - APBB Mask - 0x18 - 32 - 0x00000007 - - - PORT_ - PORT APB Clock Enable - 0 - 1 - - - DSU_ - DSU APB Clock Enable - 1 - 1 - - - NVMCTRL_ - NVMCTRL APB Clock Enable - 2 - 1 - - - HMATRIXHS_ - HMATRIXHS APB Clock Enable - 5 - 1 - - - - - APBCMASK - APBC Mask - 0x1C - 32 - 0x00000000 - - - EVSYS_ - EVSYS APB Clock Enable - 0 - 1 - - - SERCOM0_ - SERCOM0 APB Clock Enable - 1 - 1 - - - SERCOM1_ - SERCOM1 APB Clock Enable - 2 - 1 - - - SERCOM2_ - SERCOM2 APB Clock Enable - 3 - 1 - - - SERCOM3_ - SERCOM3 APB Clock Enable - 4 - 1 - - - TCC0_ - TCC0 APB Clock Enable - 9 - 1 - - - TCC1_ - TCC1 APB Clock Enable - 10 - 1 - - - TCC2_ - TCC2 APB Clock Enable - 11 - 1 - - - TC0_ - TC0 APB Clock Enable - 12 - 1 - - - TC1_ - TC1 APB Clock Enable - 13 - 1 - - - TC2_ - TC2 APB Clock Enable - 14 - 1 - - - TC3_ - TC3 APB Clock Enable - 15 - 1 - - - TC4_ - TC4 APB Clock Enable - 16 - 1 - - - ADC0_ - ADC0 APB Clock Enable - 17 - 1 - - - AC_ - AC APB Clock Enable - 20 - 1 - - - PTC_ - PTC APB Clock Enable - 22 - 1 - - - CCL_ - CCL APB Clock Enable - 23 - 1 - - - - - - - MTB - U20021.0.0 - Cortex-M0+ Micro-Trace Buffer - MTB - MTB_ - 0x41008000 - - 0 - 0x1000 - registers - - - - POSITION - MTB Position - 0x0 - 32 - - - WRAP - Pointer Value Wraps - 2 - 1 - - - POINTER - Trace Packet Location Pointer - 3 - 29 - - - - - MASTER - MTB Master - 0x4 - 32 - 0x00000000 - - - MASK - Maximum Value of the Trace Buffer in SRAM - 0 - 5 - - - TSTARTEN - Trace Start Input Enable - 5 - 1 - - - TSTOPEN - Trace Stop Input Enable - 6 - 1 - - - SFRWPRIV - Special Function Register Write Privilege - 7 - 1 - - - RAMPRIV - SRAM Privilege - 8 - 1 - - - HALTREQ - Halt Request - 9 - 1 - - - EN - Main Trace Enable - 31 - 1 - - - - - FLOW - MTB Flow - 0x8 - 32 - 0x00000000 - - - AUTOSTOP - Auto Stop Tracing - 0 - 1 - - - AUTOHALT - Auto Halt Request - 1 - 1 - - - WATERMARK - Watermark value - 3 - 29 - - - - - BASE - MTB Base - 0xC - 32 - read-only - - - ITCTRL - MTB Integration Mode Control - 0xF00 - 32 - - - CLAIMSET - MTB Claim Set - 0xFA0 - 32 - - - CLAIMCLR - MTB Claim Clear - 0xFA4 - 32 - - - LOCKACCESS - MTB Lock Access - 0xFB0 - 32 - - - LOCKSTATUS - MTB Lock Status - 0xFB4 - 32 - read-only - - - AUTHSTATUS - MTB Authentication Status - 0xFB8 - 32 - read-only - - - DEVARCH - MTB Device Architecture - 0xFBC - 32 - read-only - - - DEVID - MTB Device Configuration - 0xFC8 - 32 - read-only - - - DEVTYPE - MTB Device Type - 0xFCC - 32 - read-only - - - PID4 - Peripheral Identification 4 - 0xFD0 - 32 - read-only - - - PID5 - Peripheral Identification 5 - 0xFD4 - 32 - read-only - - - PID6 - Peripheral Identification 6 - 0xFD8 - 32 - read-only - - - PID7 - Peripheral Identification 7 - 0xFDC - 32 - read-only - - - PID0 - Peripheral Identification 0 - 0xFE0 - 32 - read-only - - - PID1 - Peripheral Identification 1 - 0xFE4 - 32 - read-only - - - PID2 - Peripheral Identification 2 - 0xFE8 - 32 - read-only - - - PID3 - Peripheral Identification 3 - 0xFEC - 32 - read-only - - - CID0 - Component Identification 0 - 0xFF0 - 32 - read-only - - - CID1 - Component Identification 1 - 0xFF4 - 32 - read-only - - - CID2 - Component Identification 2 - 0xFF8 - 32 - read-only - - - CID3 - Component Identification 3 - 0xFFC - 32 - read-only - - - - - NVMCTRL - U22074.0.1.1 - Non-Volatile Memory Controller - NVMCTRL - NVMCTRL_ - 0x41004000 - - 0 - 0x30 - registers - - - NVMCTRL - 6 - - - - CTRLA - Control A - 0x0 - 16 - 0x0000 - - - CMD - Command - 0 - 7 - - CMDSelect - - ER - Erase Row - Erases the row addressed by the ADDR register. - 0x02 - - - WP - Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. - 0x04 - - - EAR - Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. - 0x05 - - - WAP - Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. - 0x06 - - - SF - Security Flow Command - 0x0A - - - WL - Write lockbits - 0x0F - - - RWWEEER - RWW EEPROM area Erase Row - Erases the row addressed by the ADDR register. - 0x1A - - - RWWEEWP - RWW EEPROM Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. - 0x1C - - - LR - Lock Region - Locks the region containing the address location in the ADDR register. - 0x40 - - - UR - Unlock Region - Unlocks the region containing the address location in the ADDR register. - 0x41 - - - SPRM - Sets the power reduction mode. - 0x42 - - - CPRM - Clears the power reduction mode. - 0x43 - - - PBC - Page Buffer Clear - Clears the page buffer. - 0x44 - - - SSB - Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row. - 0x45 - - - INVALL - Invalidate all cache lines. - 0x46 - - - - - CMDEX - Command Execution - 8 - 8 - - CMDEXSelect - - KEY - Execution Key - 0xA5 - - - - - - - CTRLB - Control B - 0x4 - 32 - 0x00000080 - - - RWS - NVM Read Wait States - 1 - 4 - - RWSSelect - - SINGLE - Single Auto Wait State - 0 - - - HALF - Half Auto Wait State - 1 - - - DUAL - Dual Auto Wait State - 2 - - - - - MANW - Manual Write - 7 - 1 - - - SLEEPPRM - Power Reduction Mode during Sleep - 8 - 2 - - SLEEPPRMSelect - - WAKEONACCESS - NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access. - 0 - - - WAKEUPINSTANT - NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep. - 1 - - - DISABLED - Auto power reduction disabled. - 3 - - - - - READMODE - NVMCTRL Read Mode - 16 - 2 - - READMODESelect - - NO_MISS_PENALTY - The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance. - 0x0 - - - LOW_POWER - Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time. - 0x1 - - - DETERMINISTIC - The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings. - 0x2 - - - - - CACHEDIS - Cache Disable - 18 - 2 - - - - - PARAM - NVM Parameter - 0x8 - 32 - 0x00000000 - - - NVMP - NVM Pages - 0 - 16 - - - PSZ - Page Size - 16 - 3 - - PSZSelect - - 8 - 8 bytes - 0x0 - - - 16 - 16 bytes - 0x1 - - - 32 - 32 bytes - 0x2 - - - 64 - 64 bytes - 0x3 - - - 128 - 128 bytes - 0x4 - - - 256 - 256 bytes - 0x5 - - - 512 - 512 bytes - 0x6 - - - 1024 - 1024 bytes - 0x7 - - - - - RWWEEP - RWW EEPROM Pages - 20 - 12 - - - - - INTENCLR - Interrupt Enable Clear - 0xC - 8 - 0x00 - - - READY - NVM Ready Interrupt Enable - 0 - 1 - - - ERROR - Error Interrupt Enable - 1 - 1 - - - - - INTENSET - Interrupt Enable Set - 0x10 - 8 - 0x00 - - - READY - NVM Ready Interrupt Enable - 0 - 1 - - - ERROR - Error Interrupt Enable - 1 - 1 - - - - - INTFLAG - Interrupt Flag Status and Clear - 0x14 - 8 - 0x00 - - - READY - NVM Ready - 0 - 1 - - - ERROR - Error - 1 - 1 - - - - - STATUS - Status - 0x18 - 16 - 0x0000 - - - PRM - Power Reduction Mode - 0 - 1 - - - LOAD - NVM Page Buffer Active Loading - 1 - 1 - - - PROGE - Programming Error Status - 2 - 1 - - - LOCKE - Lock Error Status - 3 - 1 - - - NVME - NVM Error - 4 - 1 - - - SB - Security Bit Status - 8 - 1 - - - - - ADDR - Address - 0x1C - 32 - 0x00000000 - - - ADDR - NVM Address - 0 - 22 - - - - - LOCK - Lock Section - 0x20 - 16 - 0x0000 - - - LOCK - Region Lock Bits - 0 - 16 - - - - - PBLDATA0 - Page Buffer Load Data 0 - 0x28 - 32 - read-only - 0x00000000 - - - PBLDATA1 - Page Buffer Load Data 1 - 0x2C - 32 - read-only - 0x00000000 - - - - - OSCCTRL - U21192.1.0 - Oscillators Control - OSCCTRL - OSCCTRL_ - 0x40001000 - - 0 - 0x3C - registers - - - - INTENCLR - Interrupt Enable Clear - 0x0 - 32 - 0x00000000 - - - XOSCRDY - XOSC Ready Interrupt Enable - 0 - 1 - - - XOSCFAIL - XOSC Clock Failure Detector Interrupt Enable - 1 - 1 - - - OSC48MRDY - OSC48M Ready Interrupt Enable - 4 - 1 - - - DPLLLCKR - DPLL Lock Rise Interrupt Enable - 8 - 1 - - - DPLLLCKF - DPLL Lock Fall Interrupt Enable - 9 - 1 - - - DPLLLTO - DPLL Time Out Interrupt Enable - 10 - 1 - - - DPLLLDRTO - DPLL Ratio Ready Interrupt Enable - 11 - 1 - - - - - INTENSET - Interrupt Enable Set - 0x4 - 32 - 0x00000000 - - - XOSCRDY - XOSC Ready Interrupt Enable - 0 - 1 - - - XOSCFAIL - XOSC Clock Failure Detector Interrupt Enable - 1 - 1 - - - OSC48MRDY - OSC48M Ready Interrupt Enable - 4 - 1 - - - DPLLLCKR - DPLL Lock Rise Interrupt Enable - 8 - 1 - - - DPLLLCKF - DPLL Lock Fall Interrupt Enable - 9 - 1 - - - DPLLLTO - DPLL Time Out Interrupt Enable - 10 - 1 - - - DPLLLDRTO - DPLL Ratio Ready Interrupt Enable - 11 - 1 - - - - - INTFLAG - Interrupt Flag Status and Clear - 0x8 - 32 - 0x00000000 - - - XOSCRDY - XOSC Ready - 0 - 1 - - - XOSCFAIL - XOSC Clock Failure Detector - 1 - 1 - - - OSC48MRDY - OSC48M Ready - 4 - 1 - - - DPLLLCKR - DPLL Lock Rise - 8 - 1 - - - DPLLLCKF - DPLL Lock Fall - 9 - 1 - - - DPLLLTO - DPLL Timeout - 10 - 1 - - - DPLLLDRTO - DPLL Ratio Ready - 11 - 1 - - - - - STATUS - Power and Clocks Status - 0xC - 32 - read-only - 0x00000000 - - - XOSCRDY - XOSC Ready - 0 - 1 - - - XOSCFAIL - XOSC Clock Failure Detector - 1 - 1 - - - XOSCCKSW - XOSC Clock Switch - 2 - 1 - - - OSC48MRDY - OSC48M Ready - 4 - 1 - - - DPLLLCKR - DPLL Lock Rise - 8 - 1 - - - DPLLLCKF - DPLL Lock Fall - 9 - 1 - - - DPLLTO - DPLL Timeout - 10 - 1 - - - DPLLLDRTO - DPLL Ratio Ready - 11 - 1 - - - - - XOSCCTRL - External Multipurpose Crystal Oscillator (XOSC) Control - 0x10 - 16 - 0x0080 - - - ENABLE - Oscillator Enable - 1 - 1 - - - XTALEN - Crystal Oscillator Enable - 2 - 1 - - - CFDEN - Xosc Clock Failure Detector Enable - 3 - 1 - - - SWBEN - Xosc Clock Switch Enable - 4 - 1 - - - RUNSTDBY - Run in Standby - 6 - 1 - - - ONDEMAND - On Demand Control - 7 - 1 - - - GAIN - Oscillator Gain - 8 - 3 - - GAINSelect - - GAIN2 - 2 MHz - 0 - - - GAIN4 - 4 MHz - 1 - - - GAIN8 - 8 MHz - 2 - - - GAIN16 - 16 MHz - 3 - - - GAIN30 - 30 MHz - 4 - - - - - AMPGC - Automatic Amplitude Gain Control - 11 - 1 - - - STARTUP - Start-Up Time - 12 - 4 - - STARTUPSelect - - CYCLE1 - 31 us - 0 - - - CYCLE2 - 61 us - 1 - - - CYCLE4 - 122 us - 2 - - - CYCLE8 - 244 us - 3 - - - CYCLE16 - 488 us - 4 - - - CYCLE32 - 977 us - 5 - - - CYCLE64 - 1953 us - 6 - - - CYCLE128 - 3906 us - 7 - - - CYCLE256 - 7813 us - 8 - - - CYCLE512 - 15625 us - 9 - - - CYCLE1024 - 31250 us - 10 - - - CYCLE2048 - 62500 us - 11 - - - CYCLE4096 - 125000 us - 12 - - - CYCLE8192 - 250000 us - 13 - - - CYCLE16384 - 500000 us - 14 - - - CYCLE32768 - 1000000 us - 15 - - - - - - - CFDPRESC - Clock Failure Detector Prescaler - 0x12 - 8 - 0x00 - - - CFDPRESC - Clock Failure Detector Prescaler - 0 - 3 - - CFDPRESCSelect - - DIV1 - 48 MHz - 0 - - - DIV2 - 24 MHz - 1 - - - DIV4 - 12 MHz - 2 - - - DIV8 - 6 MHz - 3 - - - DIV16 - 3 MHz - 4 - - - DIV32 - 1.5 MHz - 5 - - - DIV64 - 0.75 MHz - 6 - - - DIV128 - 0.3125 MHz - 7 - - - - - - - EVCTRL - Event Control - 0x13 - 8 - 0x00 - - - CFDEO - Clock Failure Detector Event Output Enable - 0 - 1 - - - - - OSC48MCTRL - 48MHz Internal Oscillator (OSC48M) Control - 0x14 - 8 - 0x82 - - - ENABLE - Oscillator Enable - 1 - 1 - - - RUNSTDBY - Run in Standby - 6 - 1 - - - ONDEMAND - On Demand Control - 7 - 1 - - - - - OSC48MDIV - OSC48M Divider - 0x15 - 8 - 0x0B - - - DIV - OSC48M Division Factor - 0 - 4 - - DIVSelect - - DIV1 - 48 MHz - 0 - - - DIV2 - 24 MHz - 1 - - - DIV3 - 16 MHz - 2 - - - DIV4 - 12 MHz - 3 - - - DIV5 - 9.6 MHz - 4 - - - DIV6 - 8 MHz - 5 - - - DIV7 - 6.86 MHz - 6 - - - DIV8 - 6 MHz - 7 - - - DIV9 - 5.33 MHz - 8 - - - DIV10 - 4.8 MHz - 9 - - - DIV11 - 4.36 MHz - 10 - - - DIV12 - 4 MHz - 11 - - - DIV13 - 3.69 MHz - 12 - - - DIV14 - 3.43 MHz - 13 - - - DIV15 - 3.2 MHz - 14 - - - DIV16 - 3 MHz - 15 - - - - - - - OSC48MSTUP - OSC48M Startup Time - 0x16 - 8 - 0x07 - - - STARTUP - Startup Time - 0 - 3 - - STARTUPSelect - - CYCLE8 - 166 ns - 0 - - - CYCLE16 - 333 ns - 1 - - - CYCLE32 - 667 ns - 2 - - - CYCLE64 - 1.333 us - 3 - - - CYCLE128 - 2.667 us - 4 - - - CYCLE256 - 5.333 us - 5 - - - CYCLE512 - 10.667 us - 6 - - - CYCLE1024 - 21.333 us - 7 - - - - - - - OSC48MSYNCBUSY - OSC48M Synchronization Busy - 0x18 - 32 - read-only - 0x00000000 - - - OSC48MDIV - OSC48MDIV Synchronization Status - 2 - 1 - - - - - DPLLCTRLA - DPLL Control - 0x1C - 8 - 0x80 - - - ENABLE - Enable - 1 - 1 - - - RUNSTDBY - Run in Standby - 6 - 1 - - - ONDEMAND - On Demand - 7 - 1 - - - - - DPLLRATIO - DPLL Ratio Control - 0x20 - 32 - 0x00000000 - - - LDR - Loop Divider Ratio - 0 - 12 - - - LDRFRAC - Loop Divider Ratio Fractional Part - 16 - 4 - - - - - DPLLCTRLB - Digital Core Configuration - 0x24 - 32 - 0x00000000 - - - FILTER - Proportional Integral Filter Selection - 0 - 2 - - FILTERSelect - - DEFAULT - Default filter mode - 0 - - - LBFILT - Low bandwidth filter - 1 - - - HBFILT - High bandwidth filter - 2 - - - HDFILT - High damping filter - 3 - - - - - LPEN - Low-Power Enable - 2 - 1 - - - WUF - Wake Up Fast - 3 - 1 - - - REFCLK - Reference Clock Selection - 4 - 2 - - REFCLKSelect - - XOSC32K - XOSC32K clock reference - 0 - - - XOSC - XOSC clock reference - 1 - - - GCLK - GCLK clock reference - 2 - - - - - LTIME - Lock Time - 8 - 3 - - LTIMESelect - - DEFAULT - No time-out. Automatic lock. - 0 - - - 8MS - Time-out if no lock within 8ms - 4 - - - 9MS - Time-out if no lock within 9ms - 5 - - - 10MS - Time-out if no lock within 10ms - 6 - - - 11MS - Time-out if no lock within 11ms - 7 - - - - - LBYPASS - Lock Bypass - 12 - 1 - - - DIV - Clock Divider - 16 - 11 - - - - - DPLLPRESC - DPLL Prescaler - 0x28 - 8 - 0x00 - - - PRESC - Output Clock Prescaler - 0 - 2 - - PRESCSelect - - DIV1 - DPLL output is divided by 1 - 0 - - - DIV2 - DPLL output is divided by 2 - 1 - - - DIV4 - DPLL output is divided by 4 - 2 - - - - - - - DPLLSYNCBUSY - DPLL Synchronization Busy - 0x2C - 8 - read-only - 0x00 - - - ENABLE - DPLL Enable Synchronization Status - 1 - 1 - - - DPLLRATIO - DPLL Ratio Synchronization Status - 2 - 1 - - - DPLLPRESC - DPLL Prescaler Synchronization Status - 3 - 1 - - - - - DPLLSTATUS - DPLL Status - 0x30 - 8 - read-only - 0x00 - - - LOCK - DPLL Lock Status - 0 - 1 - - - CLKRDY - DPLL Clock Ready - 1 - 1 - - - - - CAL48M - 48MHz Oscillator Calibration - 0x38 - 32 - 0x00000000 - - - FCAL - Frequency Calibration (48MHz) - 0 - 6 - - - FRANGE - Frequency Range (48MHz) - 8 - 2 - - - TCAL - Temperature Calibration (48MHz) - 16 - 6 - - - - - - - OSC32KCTRL - U22462.1.0 - 32k Oscillators Control - OSC32KCTRL - OSC32KCTRL_ - 0x40001400 - - 0 - 0x20 - registers - - - - INTENCLR - Interrupt Enable Clear - 0x0 - 32 - 0x00000000 - - - XOSC32KRDY - XOSC32K Ready Interrupt Enable - 0 - 1 - - - OSC32KRDY - OSC32K Ready Interrupt Enable - 1 - 1 - - - CLKFAIL - XOSC32K Clock Failure Detector Interrupt Enable - 2 - 1 - - - - - INTENSET - Interrupt Enable Set - 0x4 - 32 - 0x00000000 - - - XOSC32KRDY - XOSC32K Ready Interrupt Enable - 0 - 1 - - - OSC32KRDY - OSC32K Ready Interrupt Enable - 1 - 1 - - - CLKFAIL - XOSC32K Clock Failure Detector Interrupt Enable - 2 - 1 - - - - - INTFLAG - Interrupt Flag Status and Clear - 0x8 - 32 - 0x00000000 - - - XOSC32KRDY - XOSC32K Ready - 0 - 1 - - - OSC32KRDY - OSC32K Ready - 1 - 1 - - - CLKFAIL - XOSC32K Clock Failure Detector - 2 - 1 - - - - - STATUS - Power and Clocks Status - 0xC - 32 - read-only - 0x00000000 - - - XOSC32KRDY - XOSC32K Ready - 0 - 1 - - - OSC32KRDY - OSC32K Ready - 1 - 1 - - - CLKFAIL - XOSC32K Clock Failure Detector - 2 - 1 - - - CLKSW - XOSC32K Clock switch - 3 - 1 - - - - - RTCCTRL - Clock selection - 0x10 - 32 - 0x00000000 - - - RTCSEL - RTC Clock Selection - 0 - 3 - - RTCSELSelect - - ULP1K - 1.024kHz from 32kHz internal ULP oscillator - 0 - - - ULP32K - 32.768kHz from 32kHz internal ULP oscillator - 1 - - - OSC1K - 1.024kHz from 32.768kHz internal oscillator - 2 - - - OSC32K - 32.768kHz from 32.768kHz internal oscillator - 3 - - - XOSC1K - 1.024kHz from 32.768kHz internal oscillator - 4 - - - XOSC32K - 32.768kHz from 32.768kHz external crystal oscillator - 5 - - - - - - - XOSC32K - 32kHz External Crystal Oscillator (XOSC32K) Control - 0x14 - 16 - 0x0080 - - - ENABLE - Oscillator Enable - 1 - 1 - - - XTALEN - Crystal Oscillator Enable - 2 - 1 - - - EN32K - 32kHz Output Enable - 3 - 1 - - - EN1K - 1kHz Output Enable - 4 - 1 - - - RUNSTDBY - Run in Standby - 6 - 1 - - - ONDEMAND - On Demand Control - 7 - 1 - - - STARTUP - Oscillator Start-Up Time - 8 - 3 - - STARTUPSelect - - CYCLE1 - 0.122 ms - 0 - - - CYCLE32 - 1.068 ms - 1 - - - CYCLE2048 - 62.6 ms - 2 - - - CYCLE4096 - 125 ms - 3 - - - CYCLE16384 - 500 ms - 4 - - - CYCLE32768 - 1000 ms - 5 - - - CYCLE65536 - 2000 ms - 6 - - - CYCLE131072 - 4000 ms - 7 - - - - - WRTLOCK - Write Lock - 12 - 1 - - - - - CFDCTRL - Clock Failure Detector Control - 0x16 - 8 - 0x00 - - - CFDEN - Clock Failure Detector Enable - 0 - 1 - - - SWBACK - Clock Switch Back - 1 - 1 - - - CFDPRESC - Clock Failure Detector Prescaler - 2 - 1 - - - - - EVCTRL - Event Control - 0x17 - 8 - 0x00 - - - CFDEO - Clock Failure Detector Event Output Enable - 0 - 1 - - - - - OSC32K - 32kHz Internal Oscillator (OSC32K) Control - 0x18 - 32 - 0x003F0080 - - - ENABLE - Oscillator Enable - 1 - 1 - - - EN32K - 32kHz Output Enable - 2 - 1 - - - EN1K - 1kHz Output Enable - 3 - 1 - - - RUNSTDBY - Run in Standby - 6 - 1 - - - ONDEMAND - On Demand Control - 7 - 1 - - - STARTUP - Oscillator Start-Up Time - 8 - 3 - - STARTUPSelect - - CYCLE3 - 0.092 ms - 0 - - - CYCLE4 - 0.122 ms - 1 - - - CYCLE6 - 0.183 ms - 2 - - - CYCLE10 - 0.305 ms - 3 - - - CYCLE18 - 0.549 ms - 4 - - - CYCLE34 - 1.038 ms - 5 - - - CYCLE66 - 2.014 ms - 6 - - - CYCLE130 - 3.967 ms - 7 - - - - - WRTLOCK - Write Lock - 12 - 1 - - - CALIB - Oscillator Calibration - 16 - 7 - - - - - OSCULP32K - 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control - 0x1C - 32 - - - CALIB - Oscillator Calibration - 8 - 5 - - - WRTLOCK - Write Lock - 15 - 1 - - - - - - - PAC - U21201.1.0 - Peripheral Access Controller - PAC - PAC_ - 0x40000000 - - 0 - 0x40 - registers - - - - WRCTRL - Write control - 0x0 - 32 - 0x00000000 - - - PERID - Peripheral identifier - 0 - 16 - - - KEY - Peripheral access control key - 16 - 8 - - KEYSelect - - OFF - No action - 0 - - - CLR - Clear protection - 1 - - - SET - Set protection - 2 - - - SETLCK - Set and lock protection - 3 - - - - - - - EVCTRL - Event control - 0x4 - 8 - 0x00 - - - ERREO - Peripheral acess error event output - 0 - 1 - - - - - INTENCLR - Interrupt enable clear - 0x8 - 8 - 0x00 - - - ERR - Peripheral access error interrupt disable - 0 - 1 - - - - - INTENSET - Interrupt enable set - 0x9 - 8 - 0x00 - - - ERR - Peripheral access error interrupt enable - 0 - 1 - - - - - INTFLAGAHB - Bridge interrupt flag status - 0x10 - 32 - 0x00000000 - - - FLASH_ - FLASH - 0 - 1 - - - HSRAMCM0P_ - HSRAMCM0P - 1 - 1 - - - HSRAMDSU_ - HSRAMDSU - 2 - 1 - - - HPB1_ - HPB1 - 3 - 1 - - - HPB0_ - HPB0 - 4 - 1 - - - HPB2_ - HPB2 - 5 - 1 - - - LPRAMDMAC_ - LPRAMDMAC - 6 - 1 - - - DIVAS_ - DIVAS - 7 - 1 - - - - - INTFLAGA - Peripheral interrupt flag status - Bridge A - 0x14 - 32 - 0x00000000 - - - PAC_ - PAC - 0 - 1 - - - PM_ - PM - 1 - 1 - - - MCLK_ - MCLK - 2 - 1 - - - RSTC_ - RSTC - 3 - 1 - - - OSCCTRL_ - OSCCTRL - 4 - 1 - - - OSC32KCTRL_ - OSC32KCTRL - 5 - 1 - - - SUPC_ - SUPC - 6 - 1 - - - GCLK_ - GCLK - 7 - 1 - - - WDT_ - WDT - 8 - 1 - - - RTC_ - RTC - 9 - 1 - - - EIC_ - EIC - 10 - 1 - - - FREQM_ - FREQM - 11 - 1 - - - - - INTFLAGB - Peripheral interrupt flag status - Bridge B - 0x18 - 32 - 0x00000000 - - - PORT_ - PORT - 0 - 1 - - - DSU_ - DSU - 1 - 1 - - - NVMCTRL_ - NVMCTRL - 2 - 1 - - - DMAC_ - DMAC - 3 - 1 - - - MTB_ - MTB - 4 - 1 - - - HMATRIXHS_ - HMATRIXHS - 5 - 1 - - - - - INTFLAGC - Peripheral interrupt flag status - Bridge C - 0x1C - 32 - 0x00000000 - - - EVSYS_ - EVSYS - 0 - 1 - - - SERCOM0_ - SERCOM0 - 1 - 1 - - - SERCOM1_ - SERCOM1 - 2 - 1 - - - SERCOM2_ - SERCOM2 - 3 - 1 - - - SERCOM3_ - SERCOM3 - 4 - 1 - - - TCC0_ - TCC0 - 9 - 1 - - - TCC1_ - TCC1 - 10 - 1 - - - TCC2_ - TCC2 - 11 - 1 - - - TC0_ - TC0 - 12 - 1 - - - TC1_ - TC1 - 13 - 1 - - - TC2_ - TC2 - 14 - 1 - - - TC3_ - TC3 - 15 - 1 - - - TC4_ - TC4 - 16 - 1 - - - ADC0_ - ADC0 - 17 - 1 - - - AC_ - AC - 20 - 1 - - - PTC_ - PTC - 22 - 1 - - - CCL_ - CCL - 23 - 1 - - - - - STATUSA - Peripheral write protection status - Bridge A - 0x34 - 32 - read-only - 0x00000000 - - - PAC_ - PAC APB Protect Enable - 0 - 1 - - - PM_ - PM APB Protect Enable - 1 - 1 - - - MCLK_ - MCLK APB Protect Enable - 2 - 1 - - - RSTC_ - RSTC APB Protect Enable - 3 - 1 - - - OSCCTRL_ - OSCCTRL APB Protect Enable - 4 - 1 - - - OSC32KCTRL_ - OSC32KCTRL APB Protect Enable - 5 - 1 - - - SUPC_ - SUPC APB Protect Enable - 6 - 1 - - - GCLK_ - GCLK APB Protect Enable - 7 - 1 - - - WDT_ - WDT APB Protect Enable - 8 - 1 - - - RTC_ - RTC APB Protect Enable - 9 - 1 - - - EIC_ - EIC APB Protect Enable - 10 - 1 - - - FREQM_ - FREQM APB Protect Enable - 11 - 1 - - - - - STATUSB - Peripheral write protection status - Bridge B - 0x38 - 32 - read-only - 0x00000002 - - - PORT_ - PORT APB Protect Enable - 0 - 1 - - - DSU_ - DSU APB Protect Enable - 1 - 1 - - - NVMCTRL_ - NVMCTRL APB Protect Enable - 2 - 1 - - - DMAC_ - DMAC APB Protect Enable - 3 - 1 - - - MTB_ - MTB APB Protect Enable - 4 - 1 - - - HMATRIXHS_ - HMATRIXHS APB Protect Enable - 5 - 1 - - - - - STATUSC - Peripheral write protection status - Bridge C - 0x3C - 32 - read-only - 0x02000000 - - - EVSYS_ - EVSYS APB Protect Enable - 0 - 1 - - - SERCOM0_ - SERCOM0 APB Protect Enable - 1 - 1 - - - SERCOM1_ - SERCOM1 APB Protect Enable - 2 - 1 - - - SERCOM2_ - SERCOM2 APB Protect Enable - 3 - 1 - - - SERCOM3_ - SERCOM3 APB Protect Enable - 4 - 1 - - - TCC0_ - TCC0 APB Protect Enable - 9 - 1 - - - TCC1_ - TCC1 APB Protect Enable - 10 - 1 - - - TCC2_ - TCC2 APB Protect Enable - 11 - 1 - - - TC0_ - TC0 APB Protect Enable - 12 - 1 - - - TC1_ - TC1 APB Protect Enable - 13 - 1 - - - TC2_ - TC2 APB Protect Enable - 14 - 1 - - - TC3_ - TC3 APB Protect Enable - 15 - 1 - - - TC4_ - TC4 APB Protect Enable - 16 - 1 - - - ADC0_ - ADC0 APB Protect Enable - 17 - 1 - - - AC_ - AC APB Protect Enable - 20 - 1 - - - PTC_ - PTC APB Protect Enable - 22 - 1 - - - CCL_ - CCL APB Protect Enable - 23 - 1 - - - - - - - PM - U22402.1.0 - Power Manager - PM - PM_ - 0x40000400 - - 0 - 0xA - registers - - - - SLEEPCFG - Sleep Configuration - 0x1 - 8 - 0x00 - - - SLEEPMODE - Sleep Mode - 0 - 3 - - SLEEPMODESelect - - IDLE0 - CPU clock is OFF - 0 - - - IDLE1 - AHB clock is OFF - 1 - - - IDLE2 - APB clock are OFF - 2 - - - STANDBY - All Clocks are OFF - 4 - - - - - - - STDBYCFG - Standby Configuration - 0x8 - 16 - 0x0400 - - - VREGSMOD - Voltage Regulator Standby mode - 6 - 2 - - VREGSMODSelect - - AUTO - Automatic mode - 0 - - - PERFORMANCE - Performance oriented - 1 - - - LP - Low Power oriented - 2 - - - - - BBIASHS - Back Bias for HMCRAMCHS - 10 - 1 - - - - - - - PORT - U22102.1.1 - Port Module - PORT - PORT_ - 0x41000000 - - 0 - 0x100 - registers - - - - 2 - 0x80 - GROUP[%s] - - 0x00 - - DIR - Data Direction - 0x0 - 32 - 0x00000000 - - - DIRCLR - Data Direction Clear - 0x4 - 32 - 0x00000000 - - - DIRSET - Data Direction Set - 0x8 - 32 - 0x00000000 - - - DIRTGL - Data Direction Toggle - 0xC - 32 - 0x00000000 - - - OUT - Data Output Value - 0x10 - 32 - 0x00000000 - - - OUTCLR - Data Output Value Clear - 0x14 - 32 - 0x00000000 - - - OUTSET - Data Output Value Set - 0x18 - 32 - 0x00000000 - - - OUTTGL - Data Output Value Toggle - 0x1C - 32 - 0x00000000 - - - IN - Data Input Value - 0x20 - 32 - read-only - 0x00000000 - - - CTRL - Control - 0x24 - 32 - 0x00000000 - - - SAMPLING - Input Sampling Mode - 0 - 32 - - - - - WRCONFIG - Write Configuration - 0x28 - 32 - write-only - 0x00000000 - - - PINMASK - Pin Mask for Multiple Pin Configuration - 0 - 16 - - - PMUXEN - Select Peripheral Multiplexer - 16 - 1 - - - INEN - Input Enable - 17 - 1 - - - PULLEN - Pull Enable - 18 - 1 - - - DRVSTR - Output Driver Strength Selection - 22 - 1 - - - PMUX - Peripheral Multiplexing Template - 24 - 4 - - - WRPMUX - Write PMUX Registers - 28 - 1 - - - WRPINCFG - Write PINCFG Registers - 30 - 1 - - - HWSEL - Half-Word Select - 31 - 1 - - - - - EVCTRL - Event Input Control - 0x2C - 32 - 0x00000000 - - - PID0 - Port Event Pin Identifier 0 - 0 - 5 - - - EVACT0 - Port Event Action 0 - 5 - 2 - - EVACT0Select - - OUT - Event output to pin - 0x0 - - - SET - Set output register of pin on event - 0x1 - - - CLR - Clear output register of pin on event - 0x2 - - - TGL - Toggle output register of pin on event - 0x3 - - - - - PORTEI0 - Port Event Enable Input 0 - 7 - 1 - - - PID1 - Port Event Pin Identifier 1 - 8 - 5 - - - EVACT1 - Port Event Action 1 - 13 - 2 - - - PORTEI1 - Port Event Enable Input 1 - 15 - 1 - - - PID2 - Port Event Pin Identifier 2 - 16 - 5 - - - EVACT2 - Port Event Action 2 - 21 - 2 - - - PORTEI2 - Port Event Enable Input 2 - 23 - 1 - - - PID3 - Port Event Pin Identifier 3 - 24 - 5 - - - EVACT3 - Port Event Action 3 - 29 - 2 - - - PORTEI3 - Port Event Enable Input 3 - 31 - 1 - - - - - 16 - 1 - PMUX[%s] - Peripheral Multiplexing n - 0x30 - 8 - 0x00 - - - PMUXE - Peripheral Multiplexing for Even-Numbered Pin - 0 - 4 - - - PMUXO - Peripheral Multiplexing for Odd-Numbered Pin - 4 - 4 - - - - - 32 - 1 - PINCFG[%s] - Pin Configuration n - 0x40 - 8 - 0x00 - - - PMUXEN - Select Peripheral Multiplexer - 0 - 1 - - - INEN - Input Enable - 1 - 1 - - - PULLEN - Pull Enable - 2 - 1 - - - DRVSTR - Output Driver Strength Selection - 6 - 1 - - - - - - - - PORT_IOBUS - PORT_IOBUS_ - 0x60000000 - - - PTC - U22153.1.0 - Peripheral Touch Controller - PTC - PTC_ - 0x42005800 - - 0 - 0x1 - reserved - - - PTC - 30 - - - - RSTC - U22392.0.2 - Reset Controller - RSTC - RSTC_ - 0x40000C00 - - 0 - 0x1 - registers - - - - RCAUSE - Reset Cause - 0x0 - 8 - read-only - - - POR - Power On Reset - 0 - 1 - - - BODCORE - Brown Out CORE Detector Reset - 1 - 1 - - - BODVDD - Brown Out VDD Detector Reset - 2 - 1 - - - EXT - External Reset - 4 - 1 - - - WDT - Watchdog Reset - 5 - 1 - - - SYST - System Reset Request - 6 - 1 - - - - - - - RTC - U22501.1.1 - Real-Time Counter - RTC - RTC_ - 0x40002400 - - 0 - 0x25 - registers - - - RTC - 2 - - - - MODE0 - 32-bit Counter with Single 32-bit Compare - RtcMode0 - 0x0 - - CTRLA - MODE0 Control A - 0x0 - 16 - 0x0000 - - - SWRST - Software Reset - 0 - 1 - - - ENABLE - Enable - 1 - 1 - - - MODE - Operating Mode - 2 - 2 - - MODESelect - - COUNT32 - Mode 0: 32-bit Counter - 0x0 - - - COUNT16 - Mode 1: 16-bit Counter - 0x1 - - - CLOCK - Mode 2: Clock/Calendar - 0x2 - - - - - MATCHCLR - Clear on Match - 7 - 1 - - - PRESCALER - Prescaler - 8 - 4 - - PRESCALERSelect - - OFF - CLK_RTC_CNT = GCLK_RTC/1 - 0x0 - - - DIV1 - CLK_RTC_CNT = GCLK_RTC/1 - 0x1 - - - DIV2 - CLK_RTC_CNT = GCLK_RTC/2 - 0x2 - - - DIV4 - CLK_RTC_CNT = GCLK_RTC/4 - 0x3 - - - DIV8 - CLK_RTC_CNT = GCLK_RTC/8 - 0x4 - - - DIV16 - CLK_RTC_CNT = GCLK_RTC/16 - 0x5 - - - DIV32 - CLK_RTC_CNT = GCLK_RTC/32 - 0x6 - - - DIV64 - CLK_RTC_CNT = GCLK_RTC/64 - 0x7 - - - DIV128 - CLK_RTC_CNT = GCLK_RTC/128 - 0x8 - - - DIV256 - CLK_RTC_CNT = GCLK_RTC/256 - 0x9 - - - DIV512 - CLK_RTC_CNT = GCLK_RTC/512 - 0xA - - - DIV1024 - CLK_RTC_CNT = GCLK_RTC/1024 - 0xB - - - - - COUNTSYNC - Count Read Synchronization Enable - 15 - 1 - - - - - EVCTRL - MODE0 Event Control - 0x4 - 32 - 0x00000000 - - - PEREO0 - Periodic Interval 0 Event Output Enable - 0 - 1 - - - PEREO1 - Periodic Interval 1 Event Output Enable - 1 - 1 - - - PEREO2 - Periodic Interval 2 Event Output Enable - 2 - 1 - - - PEREO3 - Periodic Interval 3 Event Output Enable - 3 - 1 - - - PEREO4 - Periodic Interval 4 Event Output Enable - 4 - 1 - - - PEREO5 - Periodic Interval 5 Event Output Enable - 5 - 1 - - - PEREO6 - Periodic Interval 6 Event Output Enable - 6 - 1 - - - PEREO7 - Periodic Interval 7 Event Output Enable - 7 - 1 - - - CMPEO0 - Compare 0 Event Output Enable - 8 - 1 - - - OVFEO - Overflow Event Output Enable - 15 - 1 - - - - - INTENCLR - MODE0 Interrupt Enable Clear - 0x8 - 16 - 0x0000 - - - PER0 - Periodic Interval 0 Interrupt Enable - 0 - 1 - - - PER1 - Periodic Interval 1 Interrupt Enable - 1 - 1 - - - PER2 - Periodic Interval 2 Interrupt Enable - 2 - 1 - - - PER3 - Periodic Interval 3 Interrupt Enable - 3 - 1 - - - PER4 - Periodic Interval 4 Interrupt Enable - 4 - 1 - - - PER5 - Periodic Interval 5 Interrupt Enable - 5 - 1 - - - PER6 - Periodic Interval 6 Interrupt Enable - 6 - 1 - - - PER7 - Periodic Interval 7 Interrupt Enable - 7 - 1 - - - CMP0 - Compare 0 Interrupt Enable - 8 - 1 - - - OVF - Overflow Interrupt Enable - 15 - 1 - - - - - INTENSET - MODE0 Interrupt Enable Set - 0xA - 16 - 0x0000 - - - PER0 - Periodic Interval 0 Interrupt Enable - 0 - 1 - - - PER1 - Periodic Interval 1 Interrupt Enable - 1 - 1 - - - PER2 - Periodic Interval 2 Interrupt Enable - 2 - 1 - - - PER3 - Periodic Interval 3 Interrupt Enable - 3 - 1 - - - PER4 - Periodic Interval 4 Interrupt Enable - 4 - 1 - - - PER5 - Periodic Interval 5 Interrupt Enable - 5 - 1 - - - PER6 - Periodic Interval 6 Interrupt Enable - 6 - 1 - - - PER7 - Periodic Interval 7 Interrupt Enable - 7 - 1 - - - CMP0 - Compare 0 Interrupt Enable - 8 - 1 - - - OVF - Overflow Interrupt Enable - 15 - 1 - - - - - INTFLAG - MODE0 Interrupt Flag Status and Clear - 0xC - 16 - 0x0000 - - - PER0 - Periodic Interval 0 - 0 - 1 - - - PER1 - Periodic Interval 1 - 1 - 1 - - - PER2 - Periodic Interval 2 - 2 - 1 - - - PER3 - Periodic Interval 3 - 3 - 1 - - - PER4 - Periodic Interval 4 - 4 - 1 - - - PER5 - Periodic Interval 5 - 5 - 1 - - - PER6 - Periodic Interval 6 - 6 - 1 - - - PER7 - Periodic Interval 7 - 7 - 1 - - - CMP0 - Compare 0 - 8 - 1 - - - OVF - Overflow - 15 - 1 - - - - - DBGCTRL - Debug Control - 0xE - 8 - 0x00 - - - DBGRUN - Run During Debug - 0 - 1 - - - - - SYNCBUSY - MODE0 Synchronization Busy Status - 0x10 - 32 - read-only - 0x00000000 - - - SWRST - Software Reset Busy - 0 - 1 - - - ENABLE - Enable Bit Busy - 1 - 1 - - - FREQCORR - FREQCORR Register Busy - 2 - 1 - - - COUNT - COUNT Register Busy - 3 - 1 - - - COMP0 - COMP 0 Register Busy - 5 - 1 - - - COUNTSYNC - Count Read Synchronization Enable Bit Busy - 15 - 1 - - - - - FREQCORR - Frequency Correction - 0x14 - 8 - 0x00 - - - VALUE - Correction Value - 0 - 7 - - - SIGN - Correction Sign - 7 - 1 - - - - - COUNT - MODE0 Counter Value - 0x18 - 32 - 0x00000000 - - - COUNT - Counter Value - 0 - 32 - - - - - COMP - MODE0 Compare n Value - 0x20 - 32 - 0x00000000 - - - COMP - Compare Value - 0 - 32 - - - - - - MODE1 - 16-bit Counter with Two 16-bit Compares - MODE0 - RtcMode1 - 0x0 - - CTRLA - MODE1 Control A - 0x0 - 16 - 0x0000 - - - SWRST - Software Reset - 0 - 1 - - - ENABLE - Enable - 1 - 1 - - - MODE - Operating Mode - 2 - 2 - - MODESelect - - COUNT32 - Mode 0: 32-bit Counter - 0 - - - COUNT16 - Mode 1: 16-bit Counter - 1 - - - CLOCK - Mode 2: Clock/Calendar - 2 - - - - - PRESCALER - Prescaler - 8 - 4 - - PRESCALERSelect - - OFF - CLK_RTC_CNT = GCLK_RTC/1 - 0 - - - DIV1 - CLK_RTC_CNT = GCLK_RTC/1 - 1 - - - DIV2 - CLK_RTC_CNT = GCLK_RTC/2 - 2 - - - DIV4 - CLK_RTC_CNT = GCLK_RTC/4 - 3 - - - DIV8 - CLK_RTC_CNT = GCLK_RTC/8 - 4 - - - DIV16 - CLK_RTC_CNT = GCLK_RTC/16 - 5 - - - DIV32 - CLK_RTC_CNT = GCLK_RTC/32 - 6 - - - DIV64 - CLK_RTC_CNT = GCLK_RTC/64 - 7 - - - DIV128 - CLK_RTC_CNT = GCLK_RTC/128 - 8 - - - DIV256 - CLK_RTC_CNT = GCLK_RTC/256 - 9 - - - DIV512 - CLK_RTC_CNT = GCLK_RTC/512 - 0xA - - - DIV1024 - CLK_RTC_CNT = GCLK_RTC/1024 - 0xB - - - - - COUNTSYNC - Count Read Synchronization Enable - 15 - 1 - - - - - EVCTRL - MODE1 Event Control - 0x4 - 32 - 0x00000000 - - - PEREO0 - Periodic Interval 0 Event Output Enable - 0 - 1 - - - PEREO1 - Periodic Interval 1 Event Output Enable - 1 - 1 - - - PEREO2 - Periodic Interval 2 Event Output Enable - 2 - 1 - - - PEREO3 - Periodic Interval 3 Event Output Enable - 3 - 1 - - - PEREO4 - Periodic Interval 4 Event Output Enable - 4 - 1 - - - PEREO5 - Periodic Interval 5 Event Output Enable - 5 - 1 - - - PEREO6 - Periodic Interval 6 Event Output Enable - 6 - 1 - - - PEREO7 - Periodic Interval 7 Event Output Enable - 7 - 1 - - - CMPEO0 - Compare 0 Event Output Enable - 8 - 1 - - - CMPEO1 - Compare 1 Event Output Enable - 9 - 1 - - - OVFEO - Overflow Event Output Enable - 15 - 1 - - - - - INTENCLR - MODE1 Interrupt Enable Clear - 0x8 - 16 - 0x0000 - - - PER0 - Periodic Interval 0 Interrupt Enable - 0 - 1 - - - PER1 - Periodic Interval 1 Interrupt Enable - 1 - 1 - - - PER2 - Periodic Interval 2 Interrupt Enable - 2 - 1 - - - PER3 - Periodic Interval 3 Interrupt Enable - 3 - 1 - - - PER4 - Periodic Interval 4 Interrupt Enable - 4 - 1 - - - PER5 - Periodic Interval 5 Interrupt Enable - 5 - 1 - - - PER6 - Periodic Interval 6 Interrupt Enable - 6 - 1 - - - PER7 - Periodic Interval 7 Interrupt Enable - 7 - 1 - - - CMP0 - Compare 0 Interrupt Enable - 8 - 1 - - - CMP1 - Compare 1 Interrupt Enable - 9 - 1 - - - OVF - Overflow Interrupt Enable - 15 - 1 - - - - - INTENSET - MODE1 Interrupt Enable Set - 0xA - 16 - 0x0000 - - - PER0 - Periodic Interval 0 Interrupt Enable - 0 - 1 - - - PER1 - Periodic Interval 1 Interrupt Enable - 1 - 1 - - - PER2 - Periodic Interval 2 Interrupt Enable - 2 - 1 - - - PER3 - Periodic Interval 3 Interrupt Enable - 3 - 1 - - - PER4 - Periodic Interval 4 Interrupt Enable - 4 - 1 - - - PER5 - Periodic Interval 5 Interrupt Enable - 5 - 1 - - - PER6 - Periodic Interval 6 Interrupt Enable - 6 - 1 - - - PER7 - Periodic Interval 7 Interrupt Enable - 7 - 1 - - - CMP0 - Compare 0 Interrupt Enable - 8 - 1 - - - CMP1 - Compare 1 Interrupt Enable - 9 - 1 - - - OVF - Overflow Interrupt Enable - 15 - 1 - - - - - INTFLAG - MODE1 Interrupt Flag Status and Clear - 0xC - 16 - 0x0000 - - - PER0 - Periodic Interval 0 - 0 - 1 - - - PER1 - Periodic Interval 1 - 1 - 1 - - - PER2 - Periodic Interval 2 - 2 - 1 - - - PER3 - Periodic Interval 3 - 3 - 1 - - - PER4 - Periodic Interval 4 - 4 - 1 - - - PER5 - Periodic Interval 5 - 5 - 1 - - - PER6 - Periodic Interval 6 - 6 - 1 - - - PER7 - Periodic Interval 7 - 7 - 1 - - - CMP0 - Compare 0 - 8 - 1 - - - CMP1 - Compare 1 - 9 - 1 - - - OVF - Overflow - 15 - 1 - - - - - DBGCTRL - Debug Control - 0xE - 8 - 0x00 - - - DBGRUN - Run During Debug - 0 - 1 - - - - - SYNCBUSY - MODE1 Synchronization Busy Status - 0x10 - 32 - read-only - 0x00000000 - - - SWRST - Software Reset Bit Busy - 0 - 1 - - - ENABLE - Enable Bit Busy - 1 - 1 - - - FREQCORR - FREQCORR Register Busy - 2 - 1 - - - COUNT - COUNT Register Busy - 3 - 1 - - - PER - PER Register Busy - 4 - 1 - - - COMP0 - COMP 0 Register Busy - 5 - 1 - - - COMP1 - COMP 1 Register Busy - 6 - 1 - - - COUNTSYNC - Count Read Synchronization Enable Bit Busy - 15 - 1 - - - - - FREQCORR - Frequency Correction - 0x14 - 8 - 0x00 - - - VALUE - Correction Value - 0 - 7 - - - SIGN - Correction Sign - 7 - 1 - - - - - COUNT - MODE1 Counter Value - 0x18 - 16 - 0x0000 - - - COUNT - Counter Value - 0 - 16 - - - - - PER - MODE1 Counter Period - 0x1C - 16 - 0x0000 - - - PER - Counter Period - 0 - 16 - - - - - 2 - 2 - COMP[%s] - MODE1 Compare n Value - 0x20 - 16 - 0x0000 - - - COMP - Compare Value - 0 - 16 - - - - - - MODE2 - Clock/Calendar with Alarm - MODE0 - RtcMode2 - 0x0 - - CTRLA - MODE2 Control A - 0x0 - 16 - 0x0000 - - - SWRST - Software Reset - 0 - 1 - - - ENABLE - Enable - 1 - 1 - - - MODE - Operating Mode - 2 - 2 - - MODESelect - - COUNT32 - Mode 0: 32-bit Counter - 0 - - - COUNT16 - Mode 1: 16-bit Counter - 1 - - - CLOCK - Mode 2: Clock/Calendar - 2 - - - - - CLKREP - Clock Representation - 6 - 1 - - - MATCHCLR - Clear on Match - 7 - 1 - - - PRESCALER - Prescaler - 8 - 4 - - PRESCALERSelect - - OFF - CLK_RTC_CNT = GCLK_RTC/1 - 0x0 - - - DIV1 - CLK_RTC_CNT = GCLK_RTC/1 - 0x1 - - - DIV2 - CLK_RTC_CNT = GCLK_RTC/2 - 0x2 - - - DIV4 - CLK_RTC_CNT = GCLK_RTC/4 - 0x3 - - - DIV8 - CLK_RTC_CNT = GCLK_RTC/8 - 0x4 - - - DIV16 - CLK_RTC_CNT = GCLK_RTC/16 - 0x5 - - - DIV32 - CLK_RTC_CNT = GCLK_RTC/32 - 0x6 - - - DIV64 - CLK_RTC_CNT = GCLK_RTC/64 - 0x7 - - - DIV128 - CLK_RTC_CNT = GCLK_RTC/128 - 0x8 - - - DIV256 - CLK_RTC_CNT = GCLK_RTC/256 - 0x9 - - - DIV512 - CLK_RTC_CNT = GCLK_RTC/512 - 0xA - - - DIV1024 - CLK_RTC_CNT = GCLK_RTC/1024 - 0xB - - - - - CLOCKSYNC - Clock Read Synchronization Enable - 15 - 1 - - - - - EVCTRL - MODE2 Event Control - 0x4 - 32 - 0x00000000 - - - PEREO0 - Periodic Interval 0 Event Output Enable - 0 - 1 - - - PEREO1 - Periodic Interval 1 Event Output Enable - 1 - 1 - - - PEREO2 - Periodic Interval 2 Event Output Enable - 2 - 1 - - - PEREO3 - Periodic Interval 3 Event Output Enable - 3 - 1 - - - PEREO4 - Periodic Interval 4 Event Output Enable - 4 - 1 - - - PEREO5 - Periodic Interval 5 Event Output Enable - 5 - 1 - - - PEREO6 - Periodic Interval 6 Event Output Enable - 6 - 1 - - - PEREO7 - Periodic Interval 7 Event Output Enable - 7 - 1 - - - ALARMEO0 - Alarm 0 Event Output Enable - 8 - 1 - - - OVFEO - Overflow Event Output Enable - 15 - 1 - - - - - INTENCLR - MODE2 Interrupt Enable Clear - 0x8 - 16 - 0x0000 - - - PER0 - Periodic Interval 0 Interrupt Enable - 0 - 1 - - - PER1 - Periodic Interval 1 Interrupt Enable - 1 - 1 - - - PER2 - Periodic Interval 2 Interrupt Enable - 2 - 1 - - - PER3 - Periodic Interval 3 Interrupt Enable - 3 - 1 - - - PER4 - Periodic Interval 4 Interrupt Enable - 4 - 1 - - - PER5 - Periodic Interval 5 Interrupt Enable - 5 - 1 - - - PER6 - Periodic Interval 6 Interrupt Enable - 6 - 1 - - - PER7 - Periodic Interval 7 Interrupt Enable - 7 - 1 - - - ALARM0 - Alarm 0 Interrupt Enable - 8 - 1 - - - OVF - Overflow Interrupt Enable - 15 - 1 - - - - - INTENSET - MODE2 Interrupt Enable Set - 0xA - 16 - 0x0000 - - - PER0 - Periodic Interval 0 Enable - 0 - 1 - - - PER1 - Periodic Interval 1 Enable - 1 - 1 - - - PER2 - Periodic Interval 2 Enable - 2 - 1 - - - PER3 - Periodic Interval 3 Enable - 3 - 1 - - - PER4 - Periodic Interval 4 Enable - 4 - 1 - - - PER5 - Periodic Interval 5 Enable - 5 - 1 - - - PER6 - Periodic Interval 6 Enable - 6 - 1 - - - PER7 - Periodic Interval 7 Enable - 7 - 1 - - - ALARM0 - Alarm 0 Interrupt Enable - 8 - 1 - - - OVF - Overflow Interrupt Enable - 15 - 1 - - - - - INTFLAG - MODE2 Interrupt Flag Status and Clear - 0xC - 16 - 0x0000 - - - PER0 - Periodic Interval 0 - 0 - 1 - - - PER1 - Periodic Interval 1 - 1 - 1 - - - PER2 - Periodic Interval 2 - 2 - 1 - - - PER3 - Periodic Interval 3 - 3 - 1 - - - PER4 - Periodic Interval 4 - 4 - 1 - - - PER5 - Periodic Interval 5 - 5 - 1 - - - PER6 - Periodic Interval 6 - 6 - 1 - - - PER7 - Periodic Interval 7 - 7 - 1 - - - ALARM0 - Alarm 0 - 8 - 1 - - - OVF - Overflow - 15 - 1 - - - - - DBGCTRL - Debug Control - 0xE - 8 - 0x00 - - - DBGRUN - Run During Debug - 0 - 1 - - - - - SYNCBUSY - MODE2 Synchronization Busy Status - 0x10 - 32 - read-only - 0x00000000 - - - SWRST - Software Reset Bit Busy - 0 - 1 - - - ENABLE - Enable Bit Busy - 1 - 1 - - - FREQCORR - FREQCORR Register Busy - 2 - 1 - - - CLOCK - CLOCK Register Busy - 3 - 1 - - - ALARM0 - ALARM 0 Register Busy - 5 - 1 - - - MASK0 - MASK 0 Register Busy - 11 - 1 - - - CLOCKSYNC - Clock Read Synchronization Enable Bit Busy - 15 - 1 - - - - - FREQCORR - Frequency Correction - 0x14 - 8 - 0x00 - - - VALUE - Correction Value - 0 - 7 - - - SIGN - Correction Sign - 7 - 1 - - - - - CLOCK - MODE2 Clock Value - 0x18 - 32 - 0x00000000 - - - SECOND - Second - 0 - 6 - - - MINUTE - Minute - 6 - 6 - - - HOUR - Hour - 12 - 5 - - HOURSelect - - AM - AM when CLKREP in 12-hour - 0x00 - - - PM - PM when CLKREP in 12-hour - 0x10 - - - - - DAY - Day - 17 - 5 - - - MONTH - Month - 22 - 4 - - - YEAR - Year - 26 - 6 - - - - - ALARM - MODE2_ALARM Alarm n Value - 0x20 - 32 - 0x00000000 - - - SECOND - Second - 0 - 6 - - - MINUTE - Minute - 6 - 6 - - - HOUR - Hour - 12 - 5 - - HOURSelect - - AM - Morning hour - 0x00 - - - PM - Afternoon hour - 0x10 - - - - - DAY - Day - 17 - 5 - - - MONTH - Month - 22 - 4 - - - YEAR - Year - 26 - 6 - - - - - MASK - MODE2_ALARM Alarm n Mask - 0x24 - 8 - 0x00 - - - SEL - Alarm Mask Selection - 0 - 3 - - SELSelect - - OFF - Alarm Disabled - 0x0 - - - SS - Match seconds only - 0x1 - - - MMSS - Match seconds and minutes only - 0x2 - - - HHMMSS - Match seconds, minutes, and hours only - 0x3 - - - DDHHMMSS - Match seconds, minutes, hours, and days only - 0x4 - - - MMDDHHMMSS - Match seconds, minutes, hours, days, and months only - 0x5 - - - YYMMDDHHMMSS - Match seconds, minutes, hours, days, months, and years - 0x6 - - - - - - - - - - SERCOM0 - U22013.1.1 - Serial Communication Interface - SERCOM - SERCOM_ - 0x42000400 - - 0 - 0x31 - registers - - - SERCOM0 - 9 - - - - I2CM - I2C Master Mode - SercomI2cm - 0x0 - - CTRLA - I2CM Control A - 0x0 - 32 - 0x00000000 - - - SWRST - Software Reset - 0 - 1 - - - ENABLE - Enable - 1 - 1 - - - MODE - Operating Mode - 2 - 3 - - MODESelect - - USART_EXT_CLK - USART with external clock - 0x0 - - - USART_INT_CLK - USART with internal clock - 0x1 - - - SPI_SLAVE - SPI in slave operation - 0x2 - - - SPI_MASTER - SPI in master operation - 0x3 - - - I2C_SLAVE - I2C slave operation - 0x4 - - - I2C_MASTER - I2C master operation - 0x5 - - - - - RUNSTDBY - Run in Standby - 7 - 1 - - - PINOUT - Pin Usage - 16 - 1 - - - SDAHOLD - SDA Hold Time - 20 - 2 - - SDAHOLDSelect - - DISABLE - Disabled - 0x0 - - - 75NS - 50-100ns hold time - 0x1 - - - 450NS - 300-600ns hold time - 0x2 - - - 600NS - 400-800ns hold time - 0x3 - - - - - MEXTTOEN - Master SCL Low Extend Timeout - 22 - 1 - - - SEXTTOEN - Slave SCL Low Extend Timeout - 23 - 1 - - - SPEED - Transfer Speed - 24 - 2 - - SPEEDSelect - - STANDARD_AND_FAST_MODE - Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz - 0x0 - - - FASTPLUS_MODE - Fast-mode Plus Upto 1MHz - 0x1 - - - HIGH_SPEED_MODE - High-speed mode Upto 3.4MHz - 0x2 - - - - - SCLSM - SCL Clock Stretch Mode - 27 - 1 - - - INACTOUT - Inactive Time-Out - 28 - 2 - - INACTOUTSelect - - DISABLE - Disabled - 0x0 - - - 55US - 5-6 SCL Time-Out(50-60us) - 0x1 - - - 105US - 10-11 SCL Time-Out(100-110us) - 0x2 - - - 205US - 20-21 SCL Time-Out(200-210us) - 0x3 - - - - - LOWTOUTEN - SCL Low Timeout Enable - 30 - 1 - - - - - CTRLB - I2CM Control B - 0x4 - 32 - 0x00000000 - - - SMEN - Smart Mode Enable - 8 - 1 - - - QCEN - Quick Command Enable - 9 - 1 - - - CMD - Command - 16 - 2 - - - ACKACT - Acknowledge Action - 18 - 1 - - - - - BAUD - I2CM Baud Rate - 0xC - 32 - 0x00000000 - - - BAUD - Baud Rate Value - 0 - 8 - - - BAUDLOW - Baud Rate Value Low - 8 - 8 - - - HSBAUD - High Speed Baud Rate Value - 16 - 8 - - - HSBAUDLOW - High Speed Baud Rate Value Low - 24 - 8 - - - - - INTENCLR - I2CM Interrupt Enable Clear - 0x14 - 8 - 0x00 - - - MB - Master On Bus Interrupt Disable - 0 - 1 - - - SB - Slave On Bus Interrupt Disable - 1 - 1 - - - ERROR - Combined Error Interrupt Disable - 7 - 1 - - - - - INTENSET - I2CM Interrupt Enable Set - 0x16 - 8 - 0x00 - - - MB - Master On Bus Interrupt Enable - 0 - 1 - - - SB - Slave On Bus Interrupt Enable - 1 - 1 - - - ERROR - Combined Error Interrupt Enable - 7 - 1 - - - - - INTFLAG - I2CM Interrupt Flag Status and Clear - 0x18 - 8 - 0x00 - - - MB - Master On Bus Interrupt - 0 - 1 - - - SB - Slave On Bus Interrupt - 1 - 1 - - - ERROR - Combined Error Interrupt - 7 - 1 - - - - - STATUS - I2CM Status - 0x1A - 16 - 0x0000 - - - BUSERR - Bus Error - 0 - 1 - - - ARBLOST - Arbitration Lost - 1 - 1 - - - RXNACK - Received Not Acknowledge - 2 - 1 - - - BUSSTATE - Bus State - 4 - 2 - - - LOWTOUT - SCL Low Timeout - 6 - 1 - - - CLKHOLD - Clock Hold - 7 - 1 - - - MEXTTOUT - Master SCL Low Extend Timeout - 8 - 1 - - - SEXTTOUT - Slave SCL Low Extend Timeout - 9 - 1 - - - LENERR - Length Error - 10 - 1 - - - - - SYNCBUSY - I2CM Synchronization Busy - 0x1C - 32 - read-only - 0x00000000 - - - SWRST - Software Reset Synchronization Busy - 0 - 1 - - - ENABLE - SERCOM Enable Synchronization Busy - 1 - 1 - - - SYSOP - System Operation Synchronization Busy - 2 - 1 - - - - - ADDR - I2CM Address - 0x24 - 32 - 0x00000000 - - - ADDR - Address Value - 0 - 11 - - - LENEN - Length Enable - 13 - 1 - - - HS - High Speed Mode - 14 - 1 - - - TENBITEN - Ten Bit Addressing Enable - 15 - 1 - - - LEN - Length - 16 - 8 - - - - - DATA - I2CM Data - 0x28 - 8 - 0x00 - - - DATA - Data Value - 0 - 8 - - - - - DBGCTRL - I2CM Debug Control - 0x30 - 8 - 0x00 - - - DBGSTOP - Debug Mode - 0 - 1 - - - - - - I2CS - I2C Slave Mode - I2CM - SercomI2cs - 0x0 - - CTRLA - I2CS Control A - 0x0 - 32 - 0x00000000 - - - SWRST - Software Reset - 0 - 1 - - - ENABLE - Enable - 1 - 1 - - - MODE - Operating Mode - 2 - 3 - - MODESelect - - USART_EXT_CLK - USART with external clock - 0x0 - - - USART_INT_CLK - USART with internal clock - 0x1 - - - SPI_SLAVE - SPI in slave operation - 0x2 - - - SPI_MASTER - SPI in master operation - 0x3 - - - I2C_SLAVE - I2C slave operation - 0x4 - - - I2C_MASTER - I2C master operation - 0x5 - - - - - RUNSTDBY - Run during Standby - 7 - 1 - - - PINOUT - Pin Usage - 16 - 1 - - - SDAHOLD - SDA Hold Time - 20 - 2 - - SDAHOLDSelect - - DISABLE - Disabled - 0x0 - - - 75NS - 50-100ns hold time - 0x1 - - - 450NS - 300-600ns hold time - 0x2 - - - 600NS - 400-800ns hold time - 0x3 - - - - - SEXTTOEN - Slave SCL Low Extend Timeout - 23 - 1 - - - SPEED - Transfer Speed - 24 - 2 - - SPEEDSelect - - STANDARD_AND_FAST_MODE - Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz - 0x0 - - - FASTPLUS_MODE - Fast-mode Plus Upto 1MHz - 0x1 - - - HIGH_SPEED_MODE - High-speed mode Upto 3.4MHz - 0x2 - - - - - SCLSM - SCL Clock Stretch Mode - 27 - 1 - - - LOWTOUTEN - SCL Low Timeout Enable - 30 - 1 - - - - - CTRLB - I2CS Control B - 0x4 - 32 - 0x00000000 - - - SMEN - Smart Mode Enable - 8 - 1 - - - GCMD - PMBus Group Command - 9 - 1 - - - AACKEN - Automatic Address Acknowledge - 10 - 1 - - - AMODE - Address Mode - 14 - 2 - - - CMD - Command - 16 - 2 - - - ACKACT - Acknowledge Action - 18 - 1 - - - - - INTENCLR - I2CS Interrupt Enable Clear - 0x14 - 8 - 0x00 - - - PREC - Stop Received Interrupt Disable - 0 - 1 - - - AMATCH - Address Match Interrupt Disable - 1 - 1 - - - DRDY - Data Interrupt Disable - 2 - 1 - - - ERROR - Combined Error Interrupt Disable - 7 - 1 - - - - - INTENSET - I2CS Interrupt Enable Set - 0x16 - 8 - 0x00 - - - PREC - Stop Received Interrupt Enable - 0 - 1 - - - AMATCH - Address Match Interrupt Enable - 1 - 1 - - - DRDY - Data Interrupt Enable - 2 - 1 - - - ERROR - Combined Error Interrupt Enable - 7 - 1 - - - - - INTFLAG - I2CS Interrupt Flag Status and Clear - 0x18 - 8 - 0x00 - - - PREC - Stop Received Interrupt - 0 - 1 - - - AMATCH - Address Match Interrupt - 1 - 1 - - - DRDY - Data Interrupt - 2 - 1 - - - ERROR - Combined Error Interrupt - 7 - 1 - - - - - STATUS - I2CS Status - 0x1A - 16 - 0x0000 - - - BUSERR - Bus Error - 0 - 1 - - - COLL - Transmit Collision - 1 - 1 - - - RXNACK - Received Not Acknowledge - 2 - 1 - - - DIR - Read/Write Direction - 3 - 1 - - - SR - Repeated Start - 4 - 1 - - - LOWTOUT - SCL Low Timeout - 6 - 1 - - - CLKHOLD - Clock Hold - 7 - 1 - - - SEXTTOUT - Slave SCL Low Extend Timeout - 9 - 1 - - - HS - High Speed - 10 - 1 - - - - - SYNCBUSY - I2CS Synchronization Busy - 0x1C - 32 - read-only - 0x00000000 - - - SWRST - Software Reset Synchronization Busy - 0 - 1 - - - ENABLE - SERCOM Enable Synchronization Busy - 1 - 1 - - - - - ADDR - I2CS Address - 0x24 - 32 - 0x00000000 - - - GENCEN - General Call Address Enable - 0 - 1 - - - ADDR - Address Value - 1 - 10 - - - TENBITEN - Ten Bit Addressing Enable - 15 - 1 - - - ADDRMASK - Address Mask - 17 - 10 - - - - - DATA - I2CS Data - 0x28 - 8 - 0x00 - - - DATA - Data Value - 0 - 8 - - - - - - SPIS - SPI Slave Mode - I2CM - SercomSpis - 0x0 - - CTRLA - SPIS Control A - 0x0 - 32 - 0x00000000 - - - SWRST - Software Reset - 0 - 1 - - - ENABLE - Enable - 1 - 1 - - - MODE - Operating Mode - 2 - 3 - - MODESelect - - USART_EXT_CLK - USART with external clock - 0x0 - - - USART_INT_CLK - USART with internal clock - 0x1 - - - SPI_SLAVE - SPI in slave operation - 0x2 - - - SPI_MASTER - SPI in master operation - 0x3 - - - I2C_SLAVE - I2C slave operation - 0x4 - - - I2C_MASTER - I2C master operation - 0x5 - - - - - RUNSTDBY - Run during Standby - 7 - 1 - - - IBON - Immediate Buffer Overflow Notification - 8 - 1 - - - DOPO - Data Out Pinout - 16 - 2 - - DOPOSelect - - PAD0 - DO on PAD[0], SCK on PAD[1] and SS on PAD[2] - 0x0 - - - PAD1 - DO on PAD[2], SCK on PAD[3] and SS on PAD[1] - 0x1 - - - PAD2 - DO on PAD[3], SCK on PAD[1] and SS on PAD[2] - 0x2 - - - PAD3 - DO on PAD[0], SCK on PAD[3] and SS on PAD[1] - 0x3 - - - - - DIPO - Data In Pinout - 20 - 2 - - DIPOSelect - - PAD0 - SERCOM PAD[0] - 0x0 - - - PAD1 - SERCOM PAD[1] - 0x1 - - - PAD2 - SERCOM PAD[2] - 0x2 - - - PAD3 - SERCOM PAD[3] - 0x3 - - - - - FORM - Frame Format - 24 - 4 - - FORMSelect - - SPI_FRAME - SPI Frame - 0x0 - - - SPI_FRAME_WITH_ADDR - SPI Frame with Addr - 0x2 - - - - - CPHA - Clock Phase - 28 - 1 - - CPHASelect - - LEADING_EDGE - The data is sampled on a leading SCK edge and changed on a trailing SCK edge - 0x0 - - - TRAILING_EDGE - The data is sampled on a trailing SCK edge and changed on a leading SCK edge - 0x1 - - - - - CPOL - Clock Polarity - 29 - 1 - - CPOLSelect - - IDLE_LOW - SCK is low when idle - 0x0 - - - IDLE_HIGH - SCK is high when idle - 0x1 - - - - - DORD - Data Order - 30 - 1 - - DORDSelect - - MSB - MSB is transferred first - 0x0 - - - LSB - LSB is transferred first - 0x1 - - - - - - - CTRLB - SPIS Control B - 0x4 - 32 - 0x00000000 - - - CHSIZE - Character Size - 0 - 3 - - CHSIZESelect - - 8_BIT - 8 bits - 0x0 - - - 9_BIT - 9 bits - 0x1 - - - - - PLOADEN - Data Preload Enable - 6 - 1 - - - SSDE - Slave Select Low Detect Enable - 9 - 1 - - - MSSEN - Master Slave Select Enable - 13 - 1 - - - AMODE - Address Mode - 14 - 2 - - AMODESelect - - MASK - SPI Address mask - 0x0 - - - 2_ADDRESSES - Two unique Addressess - 0x1 - - - RANGE - Address Range - 0x2 - - - - - RXEN - Receiver Enable - 17 - 1 - - - - - BAUD - SPIS Baud Rate - 0xC - 8 - 0x00 - - - BAUD - Baud Rate Value - 0 - 8 - - - - - INTENCLR - SPIS Interrupt Enable Clear - 0x14 - 8 - 0x00 - - - DRE - Data Register Empty Interrupt Disable - 0 - 1 - - - TXC - Transmit Complete Interrupt Disable - 1 - 1 - - - RXC - Receive Complete Interrupt Disable - 2 - 1 - - - SSL - Slave Select Low Interrupt Disable - 3 - 1 - - - ERROR - Combined Error Interrupt Disable - 7 - 1 - - - - - INTENSET - SPIS Interrupt Enable Set - 0x16 - 8 - 0x00 - - - DRE - Data Register Empty Interrupt Enable - 0 - 1 - - - TXC - Transmit Complete Interrupt Enable - 1 - 1 - - - RXC - Receive Complete Interrupt Enable - 2 - 1 - - - SSL - Slave Select Low Interrupt Enable - 3 - 1 - - - ERROR - Combined Error Interrupt Enable - 7 - 1 - - - - - INTFLAG - SPIS Interrupt Flag Status and Clear - 0x18 - 8 - 0x00 - - - DRE - Data Register Empty Interrupt - 0 - 1 - - - TXC - Transmit Complete Interrupt - 1 - 1 - - - RXC - Receive Complete Interrupt - 2 - 1 - - - SSL - Slave Select Low Interrupt Flag - 3 - 1 - - - ERROR - Combined Error Interrupt - 7 - 1 - - - - - STATUS - SPIS Status - 0x1A - 16 - 0x0000 - - - BUFOVF - Buffer Overflow - 2 - 1 - - - - - SYNCBUSY - SPIS Synchronization Busy - 0x1C - 32 - read-only - 0x00000000 - - - SWRST - Software Reset Synchronization Busy - 0 - 1 - - - ENABLE - SERCOM Enable Synchronization Busy - 1 - 1 - - - CTRLB - CTRLB Synchronization Busy - 2 - 1 - - - - - ADDR - SPIS Address - 0x24 - 32 - 0x00000000 - - - ADDR - Address Value - 0 - 8 - - - ADDRMASK - Address Mask - 16 - 8 - - - - - DATA - SPIS Data - 0x28 - 32 - 0x00000000 - - - DATA - Data Value - 0 - 9 - - - - - DBGCTRL - SPIS Debug Control - 0x30 - 8 - 0x00 - - - DBGSTOP - Debug Mode - 0 - 1 - - - - - - SPIM - SPI Master Mode - I2CM - SercomSpim - 0x0 - - CTRLA - SPIM Control A - 0x0 - 32 - 0x00000000 - - - SWRST - Software Reset - 0 - 1 - - - ENABLE - Enable - 1 - 1 - - - MODE - Operating Mode - 2 - 3 - - MODESelect - - USART_EXT_CLK - USART with external clock - 0x0 - - - USART_INT_CLK - USART with internal clock - 0x1 - - - SPI_SLAVE - SPI in slave operation - 0x2 - - - SPI_MASTER - SPI in master operation - 0x3 - - - I2C_SLAVE - I2C slave operation - 0x4 - - - I2C_MASTER - I2C master operation - 0x5 - - - - - RUNSTDBY - Run during Standby - 7 - 1 - - - IBON - Immediate Buffer Overflow Notification - 8 - 1 - - - DOPO - Data Out Pinout - 16 - 2 - - DOPOSelect - - PAD0 - DO on PAD[0], SCK on PAD[1] and SS on PAD[2] - 0x0 - - - PAD1 - DO on PAD[2], SCK on PAD[3] and SS on PAD[1] - 0x1 - - - PAD2 - DO on PAD[3], SCK on PAD[1] and SS on PAD[2] - 0x2 - - - PAD3 - DO on PAD[0], SCK on PAD[3] and SS on PAD[1] - 0x3 - - - - - DIPO - Data In Pinout - 20 - 2 - - DIPOSelect - - PAD0 - SERCOM PAD[0] - 0x0 - - - PAD1 - SERCOM PAD[1] - 0x1 - - - PAD2 - SERCOM PAD[2] - 0x2 - - - PAD3 - SERCOM PAD[3] - 0x3 - - - - - FORM - Frame Format - 24 - 4 - - FORMSelect - - SPI_FRAME - SPI Frame - 0x0 - - - SPI_FRAME_WITH_ADDR - SPI Frame with Addr - 0x2 - - - - - CPHA - Clock Phase - 28 - 1 - - CPHASelect - - LEADING_EDGE - The data is sampled on a leading SCK edge and changed on a trailing SCK edge - 0x0 - - - TRAILING_EDGE - The data is sampled on a trailing SCK edge and changed on a leading SCK edge - 0x1 - - - - - CPOL - Clock Polarity - 29 - 1 - - CPOLSelect - - IDLE_LOW - SCK is low when idle - 0x0 - - - IDLE_HIGH - SCK is high when idle - 0x1 - - - - - DORD - Data Order - 30 - 1 - - DORDSelect - - MSB - MSB is transferred first - 0x0 - - - LSB - LSB is transferred first - 0x1 - - - - - - - CTRLB - SPIM Control B - 0x4 - 32 - 0x00000000 - - - CHSIZE - Character Size - 0 - 3 - - CHSIZESelect - - 8_BIT - 8 bits - 0x0 - - - 9_BIT - 9 bits - 0x1 - - - - - PLOADEN - Data Preload Enable - 6 - 1 - - - SSDE - Slave Select Low Detect Enable - 9 - 1 - - - MSSEN - Master Slave Select Enable - 13 - 1 - - - AMODE - Address Mode - 14 - 2 - - AMODESelect - - MASK - SPI Address mask - 0x0 - - - 2_ADDRESSES - Two unique Addressess - 0x1 - - - RANGE - Address Range - 0x2 - - - - - RXEN - Receiver Enable - 17 - 1 - - - - - BAUD - SPIM Baud Rate - 0xC - 8 - 0x00 - - - BAUD - Baud Rate Value - 0 - 8 - - - - - INTENCLR - SPIM Interrupt Enable Clear - 0x14 - 8 - 0x00 - - - DRE - Data Register Empty Interrupt Disable - 0 - 1 - - - TXC - Transmit Complete Interrupt Disable - 1 - 1 - - - RXC - Receive Complete Interrupt Disable - 2 - 1 - - - SSL - Slave Select Low Interrupt Disable - 3 - 1 - - - ERROR - Combined Error Interrupt Disable - 7 - 1 - - - - - INTENSET - SPIM Interrupt Enable Set - 0x16 - 8 - 0x00 - - - DRE - Data Register Empty Interrupt Enable - 0 - 1 - - - TXC - Transmit Complete Interrupt Enable - 1 - 1 - - - RXC - Receive Complete Interrupt Enable - 2 - 1 - - - SSL - Slave Select Low Interrupt Enable - 3 - 1 - - - ERROR - Combined Error Interrupt Enable - 7 - 1 - - - - - INTFLAG - SPIM Interrupt Flag Status and Clear - 0x18 - 8 - 0x00 - - - DRE - Data Register Empty Interrupt - 0 - 1 - - - TXC - Transmit Complete Interrupt - 1 - 1 - - - RXC - Receive Complete Interrupt - 2 - 1 - - - SSL - Slave Select Low Interrupt Flag - 3 - 1 - - - ERROR - Combined Error Interrupt - 7 - 1 - - - - - STATUS - SPIM Status - 0x1A - 16 - 0x0000 - - - BUFOVF - Buffer Overflow - 2 - 1 - - - - - SYNCBUSY - SPIM Synchronization Busy - 0x1C - 32 - read-only - 0x00000000 - - - SWRST - Software Reset Synchronization Busy - 0 - 1 - - - ENABLE - SERCOM Enable Synchronization Busy - 1 - 1 - - - CTRLB - CTRLB Synchronization Busy - 2 - 1 - - - - - ADDR - SPIM Address - 0x24 - 32 - 0x00000000 - - - ADDR - Address Value - 0 - 8 - - - ADDRMASK - Address Mask - 16 - 8 - - - - - DATA - SPIM Data - 0x28 - 32 - 0x00000000 - - - DATA - Data Value - 0 - 9 - - - - - DBGCTRL - SPIM Debug Control - 0x30 - 8 - 0x00 - - - DBGSTOP - Debug Mode - 0 - 1 - - - - - - USART_EXT - USART EXTERNAL CLOCK Mode - I2CM - SercomUsart_ext - 0x0 - - CTRLA - USART_EXT Control A - 0x0 - 32 - 0x00000000 - - - SWRST - Software Reset - 0 - 1 - - - ENABLE - Enable - 1 - 1 - - - MODE - Operating Mode - 2 - 3 - - MODESelect - - USART_EXT_CLK - USART with external clock - 0x0 - - - USART_INT_CLK - USART with internal clock - 0x1 - - - SPI_SLAVE - SPI in slave operation - 0x2 - - - SPI_MASTER - SPI in master operation - 0x3 - - - I2C_SLAVE - I2C slave operation - 0x4 - - - I2C_MASTER - I2C master operation - 0x5 - - - - - RUNSTDBY - Run during Standby - 7 - 1 - - - IBON - Immediate Buffer Overflow Notification - 8 - 1 - - - SAMPR - Sample - 13 - 3 - - SAMPRSelect - - 16X_ARITHMETIC - 16x over-sampling using arithmetic baudrate generation - 0x0 - - - 16X_FRACTIONAL - 16x over-sampling using fractional baudrate generation - 0x1 - - - 8X_ARITHMETIC - 8x over-sampling using arithmetic baudrate generation - 0x2 - - - 8X_FRACTIONAL - 8x over-sampling using fractional baudrate generation - 0x3 - - - 3X_ARITHMETIC - 3x over-sampling using arithmetic baudrate generation - 0x4 - - - - - TXPO - Transmit Data Pinout - 16 - 2 - - TXPOSelect - - PAD0 - SERCOM PAD[0] is used for data transmission - 0x0 - - - PAD2 - SERCOM PAD[2] is used for data transmission - 0x1 - - - - - RXPO - Receive Data Pinout - 20 - 2 - - RXPOSelect - - PAD0 - SERCOM PAD[0] is used for data reception - 0x0 - - - PAD1 - SERCOM PAD[1] is used for data reception - 0x1 - - - PAD2 - SERCOM PAD[2] is used for data reception - 0x2 - - - PAD3 - SERCOM PAD[3] is used for data reception - 0x3 - - - - - SAMPA - Sample Adjustment - 22 - 2 - - - FORM - Frame Format - 24 - 4 - - FORMSelect - - USART_FRAME_NO_PARITY - USART frame - 0x0 - - - USART_FRAME_WITH_PARITY - USART frame with parity - 0x1 - - - USART_FRAME_LIN_MASTER_MODE - LIN Master - Break and sync generation - 0x2 - - - USART_FRAME_AUTO_BAUD_NO_PARITY - Auto-baud - break detection and auto-baud - 0x4 - - - USART_FRAME_AUTO_BAUD_WITH_PARITY - Auto-baud - break detection and auto-baud with parity - 0x5 - - - - - CMODE - Communication Mode - 28 - 1 - - CMODESelect - - ASYNC - Asynchronous Communication - 0x0 - - - SYNC - Synchronous Communication - 0x1 - - - - - CPOL - Clock Polarity - 29 - 1 - - CPOLSelect - - IDLE_LOW - TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge - 0x0 - - - IDLE_HIGH - TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge - 0x1 - - - - - DORD - Data Order - 30 - 1 - - DORDSelect - - MSB - MSB is transmitted first - 0x0 - - - LSB - LSB is transmitted first - 0x1 - - - - - - - CTRLB - USART_EXT Control B - 0x4 - 32 - 0x00000000 - - - CHSIZE - Character Size - 0 - 3 - - CHSIZESelect - - 8_BIT - 8 Bits - 0x0 - - - 9_BIT - 9 Bits - 0x1 - - - 5_BIT - 5 Bits - 0x5 - - - 6_BIT - 6 Bits - 0x6 - - - 7_BIT - 7 Bits - 0x7 - - - - - SBMODE - Stop Bit Mode - 6 - 1 - - SBMODESelect - - 1_BIT - One Stop Bit - 0x0 - - - 2_BIT - Two Stop Bits - 0x1 - - - - - COLDEN - Collision Detection Enable - 8 - 1 - - - SFDE - Start of Frame Detection Enable - 9 - 1 - - - ENC - Encoding Format - 10 - 1 - - - PMODE - Parity Mode - 13 - 1 - - PMODESelect - - EVEN - Even Parity - 0x0 - - - ODD - Odd Parity - 0x1 - - - - - TXEN - Transmitter Enable - 16 - 1 - - - RXEN - Receiver Enable - 17 - 1 - - - LINCMD - LIN Command - 24 - 2 - - - - - CTRLC - USART_EXT Control C - 0x8 - 32 - 0x00000000 - - - GTIME - RS485 Guard Time - 0 - 3 - - - BRKLEN - LIN Master Break Length - 8 - 2 - - - HDRDLY - LIN Master Header Delay - 10 - 2 - - - - - BAUD - USART_EXT Baud Rate - 0xC - 16 - 0x0000 - - - BAUD - Baud Rate Value - 0 - 16 - - - - - BAUD_FRAC_MODE - USART_EXT Baud Rate - BAUD - 0xC - 16 - 0x0000 - - - BAUD - Baud Rate Value - 0 - 13 - - - FP - Fractional Part - 13 - 3 - - - - - BAUD_FRACFP_MODE - USART_EXT Baud Rate - BAUD - 0xC - 16 - 0x0000 - - - BAUD - Baud Rate Value - 0 - 13 - - - FP - Fractional Part - 13 - 3 - - - - - BAUD_USARTFP_MODE - USART_EXT Baud Rate - BAUD - 0xC - 16 - 0x0000 - - - BAUD - Baud Rate Value - 0 - 16 - - - - - RXPL - USART_EXT Receive Pulse Length - 0xE - 8 - 0x00 - - - RXPL - Receive Pulse Length - 0 - 8 - - - - - INTENCLR - USART_EXT Interrupt Enable Clear - 0x14 - 8 - 0x00 - - - DRE - Data Register Empty Interrupt Disable - 0 - 1 - - - TXC - Transmit Complete Interrupt Disable - 1 - 1 - - - RXC - Receive Complete Interrupt Disable - 2 - 1 - - - RXS - Receive Start Interrupt Disable - 3 - 1 - - - CTSIC - Clear To Send Input Change Interrupt Disable - 4 - 1 - - - RXBRK - Break Received Interrupt Disable - 5 - 1 - - - ERROR - Combined Error Interrupt Disable - 7 - 1 - - - - - INTENSET - USART_EXT Interrupt Enable Set - 0x16 - 8 - 0x00 - - - DRE - Data Register Empty Interrupt Enable - 0 - 1 - - - TXC - Transmit Complete Interrupt Enable - 1 - 1 - - - RXC - Receive Complete Interrupt Enable - 2 - 1 - - - RXS - Receive Start Interrupt Enable - 3 - 1 - - - CTSIC - Clear To Send Input Change Interrupt Enable - 4 - 1 - - - RXBRK - Break Received Interrupt Enable - 5 - 1 - - - ERROR - Combined Error Interrupt Enable - 7 - 1 - - - - - INTFLAG - USART_EXT Interrupt Flag Status and Clear - 0x18 - 8 - 0x00 - - - DRE - Data Register Empty Interrupt - 0 - 1 - - - TXC - Transmit Complete Interrupt - 1 - 1 - - - RXC - Receive Complete Interrupt - 2 - 1 - - - RXS - Receive Start Interrupt - 3 - 1 - - - CTSIC - Clear To Send Input Change Interrupt - 4 - 1 - - - RXBRK - Break Received Interrupt - 5 - 1 - - - ERROR - Combined Error Interrupt - 7 - 1 - - - - - STATUS - USART_EXT Status - 0x1A - 16 - 0x0000 - - - PERR - Parity Error - 0 - 1 - - - FERR - Frame Error - 1 - 1 - - - BUFOVF - Buffer Overflow - 2 - 1 - - - CTS - Clear To Send - 3 - 1 - - - ISF - Inconsistent Sync Field - 4 - 1 - - - COLL - Collision Detected - 5 - 1 - - - TXE - Transmitter Empty - 6 - 1 - - - - - SYNCBUSY - USART_EXT Synchronization Busy - 0x1C - 32 - read-only - 0x00000000 - - - SWRST - Software Reset Synchronization Busy - 0 - 1 - - - ENABLE - SERCOM Enable Synchronization Busy - 1 - 1 - - - CTRLB - CTRLB Synchronization Busy - 2 - 1 - - - - - DATA - USART_EXT Data - 0x28 - 16 - 0x0000 - - - DATA - Data Value - 0 - 9 - - - - - DBGCTRL - USART_EXT Debug Control - 0x30 - 8 - 0x00 - - - DBGSTOP - Debug Mode - 0 - 1 - - - - - - USART_INT - USART INTERNAL CLOCK Mode - I2CM - SercomUsart_int - 0x0 - - CTRLA - USART_INT Control A - 0x0 - 32 - 0x00000000 - - - SWRST - Software Reset - 0 - 1 - - - ENABLE - Enable - 1 - 1 - - - MODE - Operating Mode - 2 - 3 - - MODESelect - - USART_EXT_CLK - USART with external clock - 0x0 - - - USART_INT_CLK - USART with internal clock - 0x1 - - - SPI_SLAVE - SPI in slave operation - 0x2 - - - SPI_MASTER - SPI in master operation - 0x3 - - - I2C_SLAVE - I2C slave operation - 0x4 - - - I2C_MASTER - I2C master operation - 0x5 - - - - - RUNSTDBY - Run during Standby - 7 - 1 - - - IBON - Immediate Buffer Overflow Notification - 8 - 1 - - - SAMPR - Sample - 13 - 3 - - SAMPRSelect - - 16X_ARITHMETIC - 16x over-sampling using arithmetic baudrate generation - 0x0 - - - 16X_FRACTIONAL - 16x over-sampling using fractional baudrate generation - 0x1 - - - 8X_ARITHMETIC - 8x over-sampling using arithmetic baudrate generation - 0x2 - - - 8X_FRACTIONAL - 8x over-sampling using fractional baudrate generation - 0x3 - - - 3X_ARITHMETIC - 3x over-sampling using arithmetic baudrate generation - 0x4 - - - - - TXPO - Transmit Data Pinout - 16 - 2 - - TXPOSelect - - PAD0 - SERCOM PAD[0] is used for data transmission - 0x0 - - - PAD2 - SERCOM PAD[2] is used for data transmission - 0x1 - - - - - RXPO - Receive Data Pinout - 20 - 2 - - RXPOSelect - - PAD0 - SERCOM PAD[0] is used for data reception - 0x0 - - - PAD1 - SERCOM PAD[1] is used for data reception - 0x1 - - - PAD2 - SERCOM PAD[2] is used for data reception - 0x2 - - - PAD3 - SERCOM PAD[3] is used for data reception - 0x3 - - - - - SAMPA - Sample Adjustment - 22 - 2 - - - FORM - Frame Format - 24 - 4 - - FORMSelect - - USART_FRAME_NO_PARITY - USART frame - 0x0 - - - USART_FRAME_WITH_PARITY - USART frame with parity - 0x1 - - - USART_FRAME_LIN_MASTER_MODE - LIN Master - Break and sync generation - 0x2 - - - USART_FRAME_AUTO_BAUD_NO_PARITY - Auto-baud - break detection and auto-baud - 0x4 - - - USART_FRAME_AUTO_BAUD_WITH_PARITY - Auto-baud - break detection and auto-baud with parity - 0x5 - - - - - CMODE - Communication Mode - 28 - 1 - - CMODESelect - - ASYNC - Asynchronous Communication - 0x0 - - - SYNC - Synchronous Communication - 0x1 - - - - - CPOL - Clock Polarity - 29 - 1 - - CPOLSelect - - IDLE_LOW - TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge - 0x0 - - - IDLE_HIGH - TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge - 0x1 - - - - - DORD - Data Order - 30 - 1 - - DORDSelect - - MSB - MSB is transmitted first - 0x0 - - - LSB - LSB is transmitted first - 0x1 - - - - - - - CTRLB - USART_INT Control B - 0x4 - 32 - 0x00000000 - - - CHSIZE - Character Size - 0 - 3 - - CHSIZESelect - - 8_BIT - 8 Bits - 0x0 - - - 9_BIT - 9 Bits - 0x1 - - - 5_BIT - 5 Bits - 0x5 - - - 6_BIT - 6 Bits - 0x6 - - - 7_BIT - 7 Bits - 0x7 - - - - - SBMODE - Stop Bit Mode - 6 - 1 - - SBMODESelect - - 1_BIT - One Stop Bit - 0x0 - - - 2_BIT - Two Stop Bits - 0x1 - - - - - COLDEN - Collision Detection Enable - 8 - 1 - - - SFDE - Start of Frame Detection Enable - 9 - 1 - - - ENC - Encoding Format - 10 - 1 - - - PMODE - Parity Mode - 13 - 1 - - PMODESelect - - EVEN - Even Parity - 0x0 - - - ODD - Odd Parity - 0x1 - - - - - TXEN - Transmitter Enable - 16 - 1 - - - RXEN - Receiver Enable - 17 - 1 - - - LINCMD - LIN Command - 24 - 2 - - - - - CTRLC - USART_INT Control C - 0x8 - 32 - 0x00000000 - - - GTIME - RS485 Guard Time - 0 - 3 - - - BRKLEN - LIN Master Break Length - 8 - 2 - - - HDRDLY - LIN Master Header Delay - 10 - 2 - - - - - BAUD - USART_INT Baud Rate - 0xC - 16 - 0x0000 - - - BAUD - Baud Rate Value - 0 - 16 - - - - - BAUD_FRAC_MODE - USART_INT Baud Rate - BAUD - 0xC - 16 - 0x0000 - - - BAUD - Baud Rate Value - 0 - 13 - - - FP - Fractional Part - 13 - 3 - - - - - BAUD_FRACFP_MODE - USART_INT Baud Rate - BAUD - 0xC - 16 - 0x0000 - - - BAUD - Baud Rate Value - 0 - 13 - - - FP - Fractional Part - 13 - 3 - - - - - BAUD_USARTFP_MODE - USART_INT Baud Rate - BAUD - 0xC - 16 - 0x0000 - - - BAUD - Baud Rate Value - 0 - 16 - - - - - RXPL - USART_INT Receive Pulse Length - 0xE - 8 - 0x00 - - - RXPL - Receive Pulse Length - 0 - 8 - - - - - INTENCLR - USART_INT Interrupt Enable Clear - 0x14 - 8 - 0x00 - - - DRE - Data Register Empty Interrupt Disable - 0 - 1 - - - TXC - Transmit Complete Interrupt Disable - 1 - 1 - - - RXC - Receive Complete Interrupt Disable - 2 - 1 - - - RXS - Receive Start Interrupt Disable - 3 - 1 - - - CTSIC - Clear To Send Input Change Interrupt Disable - 4 - 1 - - - RXBRK - Break Received Interrupt Disable - 5 - 1 - - - ERROR - Combined Error Interrupt Disable - 7 - 1 - - - - - INTENSET - USART_INT Interrupt Enable Set - 0x16 - 8 - 0x00 - - - DRE - Data Register Empty Interrupt Enable - 0 - 1 - - - TXC - Transmit Complete Interrupt Enable - 1 - 1 - - - RXC - Receive Complete Interrupt Enable - 2 - 1 - - - RXS - Receive Start Interrupt Enable - 3 - 1 - - - CTSIC - Clear To Send Input Change Interrupt Enable - 4 - 1 - - - RXBRK - Break Received Interrupt Enable - 5 - 1 - - - ERROR - Combined Error Interrupt Enable - 7 - 1 - - - - - INTFLAG - USART_INT Interrupt Flag Status and Clear - 0x18 - 8 - 0x00 - - - DRE - Data Register Empty Interrupt - 0 - 1 - - - TXC - Transmit Complete Interrupt - 1 - 1 - - - RXC - Receive Complete Interrupt - 2 - 1 - - - RXS - Receive Start Interrupt - 3 - 1 - - - CTSIC - Clear To Send Input Change Interrupt - 4 - 1 - - - RXBRK - Break Received Interrupt - 5 - 1 - - - ERROR - Combined Error Interrupt - 7 - 1 - - - - - STATUS - USART_INT Status - 0x1A - 16 - 0x0000 - - - PERR - Parity Error - 0 - 1 - - - FERR - Frame Error - 1 - 1 - - - BUFOVF - Buffer Overflow - 2 - 1 - - - CTS - Clear To Send - 3 - 1 - - - ISF - Inconsistent Sync Field - 4 - 1 - - - COLL - Collision Detected - 5 - 1 - - - TXE - Transmitter Empty - 6 - 1 - - - - - SYNCBUSY - USART_INT Synchronization Busy - 0x1C - 32 - read-only - 0x00000000 - - - SWRST - Software Reset Synchronization Busy - 0 - 1 - - - ENABLE - SERCOM Enable Synchronization Busy - 1 - 1 - - - CTRLB - CTRLB Synchronization Busy - 2 - 1 - - - - - DATA - USART_INT Data - 0x28 - 16 - 0x0000 - - - DATA - Data Value - 0 - 9 - - - - - DBGCTRL - USART_INT Debug Control - 0x30 - 8 - 0x00 - - - DBGSTOP - Debug Mode - 0 - 1 - - - - - - - - SERCOM1 - 0x42000800 - - SERCOM1 - 10 - - - - SERCOM2 - 0x42000C00 - - SERCOM2 - 11 - - - - SERCOM3 - 0x42001000 - - SERCOM3 - 12 - - - - SUPC - U21172.1.1 - Supply Controller - SUPC - SUPC_ - 0x40001800 - - 0 - 0x20 - registers - - - - INTENCLR - Interrupt Enable Clear - 0x0 - 32 - 0x00000000 - - - BODVDDRDY - BODVDD Ready - 0 - 1 - - - BODVDDDET - BODVDD Detection - 1 - 1 - - - BVDDSRDY - BODVDD Synchronization Ready - 2 - 1 - - - BODCORERDY - BODCORE Ready - 3 - 1 - - - BODCOREDET - BODCORE Detection - 4 - 1 - - - BCORESRDY - BODCORE Synchronization Ready - 5 - 1 - - - - - INTENSET - Interrupt Enable Set - 0x4 - 32 - 0x00000000 - - - BODVDDRDY - BODVDD Ready - 0 - 1 - - - BODVDDDET - BODVDD Detection - 1 - 1 - - - BVDDSRDY - BODVDD Synchronization Ready - 2 - 1 - - - BODCORERDY - BODCORE Ready - 3 - 1 - - - BODCOREDET - BODCORE Detection - 4 - 1 - - - BCORESRDY - BODCORE Synchronization Ready - 5 - 1 - - - - - INTFLAG - Interrupt Flag Status and Clear - 0x8 - 32 - 0x00000000 - - - BODVDDRDY - BODVDD Ready - 0 - 1 - - - BODVDDDET - BODVDD Detection - 1 - 1 - - - BVDDSRDY - BODVDD Synchronization Ready - 2 - 1 - - - BODCORERDY - BODCORE Ready - 3 - 1 - - - BODCOREDET - BODCORE Detection - 4 - 1 - - - BCORESRDY - BODCORE Synchronization Ready - 5 - 1 - - - - - STATUS - Power and Clocks Status - 0xC - 32 - read-only - 0x00000000 - - - BODVDDRDY - BODVDD Ready - 0 - 1 - - - BODVDDDET - BODVDD Detection - 1 - 1 - - - BVDDSRDY - BODVDD Synchronization Ready - 2 - 1 - - - BODCORERDY - BODCORE Ready - 3 - 1 - - - BODCOREDET - BODCORE Detection - 4 - 1 - - - BCORESRDY - BODCORE Synchronization Ready - 5 - 1 - - - - - BODVDD - BODVDD Control - 0x10 - 32 - 0x00000000 - - - ENABLE - Enable - 1 - 1 - - - HYST - Hysteresis Enable - 2 - 1 - - - ACTION - Action when Threshold Crossed - 3 - 2 - - ACTIONSelect - - NONE - No action - 0x0 - - - RESET - The BODVDD generates a reset - 0x1 - - - INT - The BODVDD generates an interrupt - 0x2 - - - - - STDBYCFG - Configuration in Standby mode - 5 - 1 - - - RUNSTDBY - Run during Standby - 6 - 1 - - - ACTCFG - Configuration in Active mode - 8 - 1 - - - PSEL - Prescaler Select - 12 - 4 - - PSELSelect - - DIV2 - Divide clock by 2 - 0x0 - - - DIV4 - Divide clock by 4 - 0x1 - - - DIV8 - Divide clock by 8 - 0x2 - - - DIV16 - Divide clock by 16 - 0x3 - - - DIV32 - Divide clock by 32 - 0x4 - - - DIV64 - Divide clock by 64 - 0x5 - - - DIV128 - Divide clock by 128 - 0x6 - - - DIV256 - Divide clock by 256 - 0x7 - - - DIV512 - Divide clock by 512 - 0x8 - - - DIV1024 - Divide clock by 1024 - 0x9 - - - DIV2048 - Divide clock by 2048 - 0xA - - - DIV4096 - Divide clock by 4096 - 0xB - - - DIV8192 - Divide clock by 8192 - 0xC - - - DIV16384 - Divide clock by 16384 - 0xD - - - DIV32768 - Divide clock by 32768 - 0xE - - - DIV65536 - Divide clock by 65536 - 0xF - - - - - LEVEL - Threshold Level for VDD - 16 - 6 - - - - - BODCORE - BODCORE Control - 0x14 - 32 - 0x00000000 - - - ENABLE - Enable - 1 - 1 - - - HYST - Hysteresis Enable - 2 - 1 - - - ACTION - Action when Threshold Crossed - 3 - 2 - - ACTIONSelect - - NONE - No action - 0x0 - - - RESET - The BODCORE generates a reset - 0x1 - - - INT - The BODCORE generates an interrupt - 0x2 - - - - - STDBYCFG - Configuration in Standby mode - 5 - 1 - - - RUNSTDBY - Run during Standby - 6 - 1 - - - ACTCFG - Configuration in Active mode - 8 - 1 - - - PSEL - Prescaler Select - 12 - 4 - - PSELSelect - - DIV2 - Divide clock by 2 - 0x0 - - - DIV4 - Divide clock by 4 - 0x1 - - - DIV8 - Divide clock by 8 - 0x2 - - - DIV16 - Divide clock by 16 - 0x3 - - - DIV32 - Divide clock by 32 - 0x4 - - - DIV64 - Divide clock by 64 - 0x5 - - - DIV128 - Divide clock by 128 - 0x6 - - - DIV256 - Divide clock by 256 - 0x7 - - - DIV512 - Divide clock by 512 - 0x8 - - - DIV1024 - Divide clock by 1024 - 0x9 - - - DIV2048 - Divide clock by 2048 - 0xA - - - DIV4096 - Divide clock by 4096 - 0xB - - - DIV8192 - Divide clock by 8192 - 0xC - - - DIV16384 - Divide clock by 16384 - 0xD - - - DIV32768 - Divide clock by 32768 - 0xE - - - DIV65536 - Divide clock by 65536 - 0xF - - - - - LEVEL - Threshold Level - 16 - 6 - - - - - VREG - VREG Control - 0x18 - 32 - 0x00000000 - - - ENABLE - Enable - 1 - 1 - - - RUNSTDBY - Run during Standby - 6 - 1 - - - - - VREF - VREF Control - 0x1C - 32 - 0x00000000 - - - TSEN - Temperature Sensor Output Enable - 1 - 1 - - - VREFOE - Voltage Reference Output Enable - 2 - 1 - - - RUNSTDBY - Run during Standby - 6 - 1 - - - ONDEMAND - On Demand Contrl - 7 - 1 - - - SEL - Voltage Reference Selection - 16 - 4 - - SELSelect - - 1V024 - 1.024V voltage reference typical value - 0x0 - - - 2V048 - 2.048V voltage reference typical value - 0x2 - - - 4V096 - 4.096V voltage reference typical value - 0x3 - - - - - - - - - TC0 - U22492.0.0 - Basic Timer Counter - TC - TC_ - 0x42003000 - - 0 - 0x38 - registers - - - TC0 - 20 - - - - COUNT8 - 8-bit Counter Mode - TcCount8 - 0x0 - - CTRLA - Control A - 0x0 - 32 - 0x00000000 - - - SWRST - Software Reset - 0 - 1 - - - ENABLE - Enable - 1 - 1 - - - MODE - Timer Counter Mode - 2 - 2 - - MODESelect - - COUNT16 - Counter in 16-bit mode - 0 - - - COUNT8 - Counter in 8-bit mode - 1 - - - COUNT32 - Counter in 32-bit mode - 2 - - - - - PRESCSYNC - Prescaler and Counter Synchronization - 4 - 2 - - PRESCSYNCSelect - - GCLK - Reload or reset the counter on next generic clock - 0 - - - PRESC - Reload or reset the counter on next prescaler clock - 1 - - - RESYNC - Reload or reset the counter on next generic clock and reset the prescaler counter - 2 - - - - - RUNSTDBY - Run during Standby - 6 - 1 - - - ONDEMAND - Clock On Demand - 7 - 1 - - - PRESCALER - Prescaler - 8 - 3 - - PRESCALERSelect - - DIV1 - Prescaler: GCLK_TC - 0 - - - DIV2 - Prescaler: GCLK_TC/2 - 1 - - - DIV4 - Prescaler: GCLK_TC/4 - 2 - - - DIV8 - Prescaler: GCLK_TC/8 - 3 - - - DIV16 - Prescaler: GCLK_TC/16 - 4 - - - DIV64 - Prescaler: GCLK_TC/64 - 5 - - - DIV256 - Prescaler: GCLK_TC/256 - 6 - - - DIV1024 - Prescaler: GCLK_TC/1024 - 7 - - - - - ALOCK - Auto Lock - 11 - 1 - - - CAPTEN0 - Capture Channel 0 Enable - 16 - 1 - - - CAPTEN1 - Capture Channel 1 Enable - 17 - 1 - - - COPEN0 - Capture On Pin 0 Enable - 20 - 1 - - - COPEN1 - Capture On Pin 1 Enable - 21 - 1 - - - - - CTRLBCLR - Control B Clear - 0x4 - 8 - 0x00 - - - DIR - Counter Direction - 0 - 1 - - - LUPD - Lock Update - 1 - 1 - - - ONESHOT - One-Shot on Counter - 2 - 1 - - - CMD - Command - 5 - 3 - - CMDSelect - - NONE - No action - 0 - - - RETRIGGER - Force a start, restart or retrigger - 1 - - - STOP - Force a stop - 2 - - - UPDATE - Force update of double-buffered register - 3 - - - READSYNC - Force a read synchronization of COUNT - 4 - - - DMAOS - One-shot DMA trigger - 5 - - - - - - - CTRLBSET - Control B Set - 0x5 - 8 - 0x00 - - - DIR - Counter Direction - 0 - 1 - - - LUPD - Lock Update - 1 - 1 - - - ONESHOT - One-Shot on Counter - 2 - 1 - - - CMD - Command - 5 - 3 - - CMDSelect - - NONE - No action - 0 - - - RETRIGGER - Force a start, restart or retrigger - 1 - - - STOP - Force a stop - 2 - - - UPDATE - Force update of double-buffered register - 3 - - - READSYNC - Force a read synchronization of COUNT - 4 - - - DMAOS - One-shot DMA trigger - 5 - - - - - - - EVCTRL - Event Control - 0x6 - 16 - 0x0000 - - - EVACT - Event Action - 0 - 3 - - EVACTSelect - - OFF - Event action disabled - 0 - - - RETRIGGER - Start, restart or retrigger TC on event - 1 - - - COUNT - Count on event - 2 - - - START - Start TC on event - 3 - - - STAMP - Time stamp capture - 4 - - - PPW - Period catured in CC0, pulse width in CC1 - 5 - - - PWP - Period catured in CC1, pulse width in CC0 - 6 - - - PW - Pulse width capture - 7 - - - - - TCINV - TC Event Input Polarity - 4 - 1 - - - TCEI - TC Event Enable - 5 - 1 - - - OVFEO - Event Output Enable - 8 - 1 - - - MCEO0 - MC Event Output Enable 0 - 12 - 1 - - - MCEO1 - MC Event Output Enable 1 - 13 - 1 - - - - - INTENCLR - Interrupt Enable Clear - 0x8 - 8 - 0x00 - - - OVF - OVF Interrupt Disable - 0 - 1 - - - ERR - ERR Interrupt Disable - 1 - 1 - - - MC0 - MC Interrupt Disable 0 - 4 - 1 - - - MC1 - MC Interrupt Disable 1 - 5 - 1 - - - - - INTENSET - Interrupt Enable Set - 0x9 - 8 - 0x00 - - - OVF - OVF Interrupt Enable - 0 - 1 - - - ERR - ERR Interrupt Enable - 1 - 1 - - - MC0 - MC Interrupt Enable 0 - 4 - 1 - - - MC1 - MC Interrupt Enable 1 - 5 - 1 - - - - - INTFLAG - Interrupt Flag Status and Clear - 0xA - 8 - 0x00 - - - OVF - OVF Interrupt Flag - 0 - 1 - - - ERR - ERR Interrupt Flag - 1 - 1 - - - MC0 - MC Interrupt Flag 0 - 4 - 1 - - - MC1 - MC Interrupt Flag 1 - 5 - 1 - - - - - STATUS - Status - 0xB - 8 - 0x01 - - - STOP - Stop Status Flag - 0 - 1 - - - SLAVE - Slave Status Flag - 1 - 1 - - - PERBUFV - Synchronization Busy Status - 3 - 1 - - - CCBUFV0 - Compare channel buffer 0 valid - 4 - 1 - - - CCBUFV1 - Compare channel buffer 1 valid - 5 - 1 - - - - - WAVE - Waveform Generation Control - 0xC - 8 - 0x00 - - - WAVEGEN - Waveform Generation Mode - 0 - 2 - - WAVEGENSelect - - NFRQ - Normal frequency - 0 - - - MFRQ - Match frequency - 1 - - - NPWM - Normal PWM - 2 - - - MPWM - Match PWM - 3 - - - - - - - DRVCTRL - Control C - 0xD - 8 - 0x00 - - - INVEN0 - Output Waveform Invert Enable 0 - 0 - 1 - - - INVEN1 - Output Waveform Invert Enable 1 - 1 - 1 - - - - - DBGCTRL - Debug Control - 0xF - 8 - 0x00 - - - DBGRUN - Run During Debug - 0 - 1 - - - - - SYNCBUSY - Synchronization Status - 0x10 - 32 - read-only - 0x00000000 - - - SWRST - swrst - 0 - 1 - - - ENABLE - enable - 1 - 1 - - - CTRLB - CTRLB - 2 - 1 - - - STATUS - STATUS - 3 - 1 - - - COUNT - Counter - 4 - 1 - - - PER - Period - 5 - 1 - - - CC0 - Compare Channel 0 - 6 - 1 - - - CC1 - Compare Channel 1 - 7 - 1 - - - - - COUNT - COUNT8 Count - 0x14 - 8 - 0x00 - - - COUNT - Counter Value - 0 - 8 - - - - - PER - COUNT8 Period - 0x1B - 8 - 0xFF - - - PER - Period Value - 0 - 8 - - - - - 2 - 1 - CC[%s] - COUNT8 Compare and Capture - 0x1C - 8 - 0x00 - - - CC - Counter/Compare Value - 0 - 8 - - - - - PERBUF - COUNT8 Period Buffer - 0x2F - 8 - 0xFF - - - PERBUF - Period Buffer Value - 0 - 8 - - - - - 2 - 1 - CCBUF[%s] - COUNT8 Compare and Capture Buffer - 0x30 - 8 - 0x00 - - - CCBUF - Counter/Compare Buffer Value - 0 - 8 - - - - - - COUNT16 - 16-bit Counter Mode - COUNT8 - TcCount16 - 0x0 - - CTRLA - Control A - 0x0 - 32 - 0x00000000 - - - SWRST - Software Reset - 0 - 1 - - - ENABLE - Enable - 1 - 1 - - - MODE - Timer Counter Mode - 2 - 2 - - MODESelect - - COUNT16 - Counter in 16-bit mode - 0 - - - COUNT8 - Counter in 8-bit mode - 1 - - - COUNT32 - Counter in 32-bit mode - 2 - - - - - PRESCSYNC - Prescaler and Counter Synchronization - 4 - 2 - - PRESCSYNCSelect - - GCLK - Reload or reset the counter on next generic clock - 0 - - - PRESC - Reload or reset the counter on next prescaler clock - 1 - - - RESYNC - Reload or reset the counter on next generic clock and reset the prescaler counter - 2 - - - - - RUNSTDBY - Run during Standby - 6 - 1 - - - ONDEMAND - Clock On Demand - 7 - 1 - - - PRESCALER - Prescaler - 8 - 3 - - PRESCALERSelect - - DIV1 - Prescaler: GCLK_TC - 0 - - - DIV2 - Prescaler: GCLK_TC/2 - 1 - - - DIV4 - Prescaler: GCLK_TC/4 - 2 - - - DIV8 - Prescaler: GCLK_TC/8 - 3 - - - DIV16 - Prescaler: GCLK_TC/16 - 4 - - - DIV64 - Prescaler: GCLK_TC/64 - 5 - - - DIV256 - Prescaler: GCLK_TC/256 - 6 - - - DIV1024 - Prescaler: GCLK_TC/1024 - 7 - - - - - ALOCK - Auto Lock - 11 - 1 - - - CAPTEN0 - Capture Channel 0 Enable - 16 - 1 - - - CAPTEN1 - Capture Channel 1 Enable - 17 - 1 - - - COPEN0 - Capture On Pin 0 Enable - 20 - 1 - - - COPEN1 - Capture On Pin 1 Enable - 21 - 1 - - - - - CTRLBCLR - Control B Clear - 0x4 - 8 - 0x00 - - - DIR - Counter Direction - 0 - 1 - - - LUPD - Lock Update - 1 - 1 - - - ONESHOT - One-Shot on Counter - 2 - 1 - - - CMD - Command - 5 - 3 - - CMDSelect - - NONE - No action - 0 - - - RETRIGGER - Force a start, restart or retrigger - 1 - - - STOP - Force a stop - 2 - - - UPDATE - Force update of double-buffered register - 3 - - - READSYNC - Force a read synchronization of COUNT - 4 - - - DMAOS - One-shot DMA trigger - 5 - - - - - - - CTRLBSET - Control B Set - 0x5 - 8 - 0x00 - - - DIR - Counter Direction - 0 - 1 - - - LUPD - Lock Update - 1 - 1 - - - ONESHOT - One-Shot on Counter - 2 - 1 - - - CMD - Command - 5 - 3 - - CMDSelect - - NONE - No action - 0 - - - RETRIGGER - Force a start, restart or retrigger - 1 - - - STOP - Force a stop - 2 - - - UPDATE - Force update of double-buffered register - 3 - - - READSYNC - Force a read synchronization of COUNT - 4 - - - DMAOS - One-shot DMA trigger - 5 - - - - - - - EVCTRL - Event Control - 0x6 - 16 - 0x0000 - - - EVACT - Event Action - 0 - 3 - - EVACTSelect - - OFF - Event action disabled - 0 - - - RETRIGGER - Start, restart or retrigger TC on event - 1 - - - COUNT - Count on event - 2 - - - START - Start TC on event - 3 - - - STAMP - Time stamp capture - 4 - - - PPW - Period catured in CC0, pulse width in CC1 - 5 - - - PWP - Period catured in CC1, pulse width in CC0 - 6 - - - PW - Pulse width capture - 7 - - - - - TCINV - TC Event Input Polarity - 4 - 1 - - - TCEI - TC Event Enable - 5 - 1 - - - OVFEO - Event Output Enable - 8 - 1 - - - MCEO0 - MC Event Output Enable 0 - 12 - 1 - - - MCEO1 - MC Event Output Enable 1 - 13 - 1 - - - - - INTENCLR - Interrupt Enable Clear - 0x8 - 8 - 0x00 - - - OVF - OVF Interrupt Disable - 0 - 1 - - - ERR - ERR Interrupt Disable - 1 - 1 - - - MC0 - MC Interrupt Disable 0 - 4 - 1 - - - MC1 - MC Interrupt Disable 1 - 5 - 1 - - - - - INTENSET - Interrupt Enable Set - 0x9 - 8 - 0x00 - - - OVF - OVF Interrupt Enable - 0 - 1 - - - ERR - ERR Interrupt Enable - 1 - 1 - - - MC0 - MC Interrupt Enable 0 - 4 - 1 - - - MC1 - MC Interrupt Enable 1 - 5 - 1 - - - - - INTFLAG - Interrupt Flag Status and Clear - 0xA - 8 - 0x00 - - - OVF - OVF Interrupt Flag - 0 - 1 - - - ERR - ERR Interrupt Flag - 1 - 1 - - - MC0 - MC Interrupt Flag 0 - 4 - 1 - - - MC1 - MC Interrupt Flag 1 - 5 - 1 - - - - - STATUS - Status - 0xB - 8 - 0x01 - - - STOP - Stop Status Flag - 0 - 1 - - - SLAVE - Slave Status Flag - 1 - 1 - - - PERBUFV - Synchronization Busy Status - 3 - 1 - - - CCBUFV0 - Compare channel buffer 0 valid - 4 - 1 - - - CCBUFV1 - Compare channel buffer 1 valid - 5 - 1 - - - - - WAVE - Waveform Generation Control - 0xC - 8 - 0x00 - - - WAVEGEN - Waveform Generation Mode - 0 - 2 - - WAVEGENSelect - - NFRQ - Normal frequency - 0 - - - MFRQ - Match frequency - 1 - - - NPWM - Normal PWM - 2 - - - MPWM - Match PWM - 3 - - - - - - - DRVCTRL - Control C - 0xD - 8 - 0x00 - - - INVEN0 - Output Waveform Invert Enable 0 - 0 - 1 - - - INVEN1 - Output Waveform Invert Enable 1 - 1 - 1 - - - - - DBGCTRL - Debug Control - 0xF - 8 - 0x00 - - - DBGRUN - Run During Debug - 0 - 1 - - - - - SYNCBUSY - Synchronization Status - 0x10 - 32 - read-only - 0x00000000 - - - SWRST - swrst - 0 - 1 - - - ENABLE - enable - 1 - 1 - - - CTRLB - CTRLB - 2 - 1 - - - STATUS - STATUS - 3 - 1 - - - COUNT - Counter - 4 - 1 - - - PER - Period - 5 - 1 - - - CC0 - Compare Channel 0 - 6 - 1 - - - CC1 - Compare Channel 1 - 7 - 1 - - - - - COUNT - COUNT16 Count - 0x14 - 16 - 0x0000 - - - COUNT - Counter Value - 0 - 16 - - - - - 2 - 2 - CC[%s] - COUNT16 Compare and Capture - 0x1C - 16 - 0x0000 - - - CC - Counter/Compare Value - 0 - 16 - - - - - 2 - 2 - CCBUF[%s] - COUNT16 Compare and Capture Buffer - 0x30 - 16 - 0x0000 - - - CCBUF - Counter/Compare Buffer Value - 0 - 16 - - - - - - COUNT32 - 32-bit Counter Mode - COUNT8 - TcCount32 - 0x0 - - CTRLA - Control A - 0x0 - 32 - 0x00000000 - - - SWRST - Software Reset - 0 - 1 - - - ENABLE - Enable - 1 - 1 - - - MODE - Timer Counter Mode - 2 - 2 - - MODESelect - - COUNT16 - Counter in 16-bit mode - 0 - - - COUNT8 - Counter in 8-bit mode - 1 - - - COUNT32 - Counter in 32-bit mode - 2 - - - - - PRESCSYNC - Prescaler and Counter Synchronization - 4 - 2 - - PRESCSYNCSelect - - GCLK - Reload or reset the counter on next generic clock - 0 - - - PRESC - Reload or reset the counter on next prescaler clock - 1 - - - RESYNC - Reload or reset the counter on next generic clock and reset the prescaler counter - 2 - - - - - RUNSTDBY - Run during Standby - 6 - 1 - - - ONDEMAND - Clock On Demand - 7 - 1 - - - PRESCALER - Prescaler - 8 - 3 - - PRESCALERSelect - - DIV1 - Prescaler: GCLK_TC - 0 - - - DIV2 - Prescaler: GCLK_TC/2 - 1 - - - DIV4 - Prescaler: GCLK_TC/4 - 2 - - - DIV8 - Prescaler: GCLK_TC/8 - 3 - - - DIV16 - Prescaler: GCLK_TC/16 - 4 - - - DIV64 - Prescaler: GCLK_TC/64 - 5 - - - DIV256 - Prescaler: GCLK_TC/256 - 6 - - - DIV1024 - Prescaler: GCLK_TC/1024 - 7 - - - - - ALOCK - Auto Lock - 11 - 1 - - - CAPTEN0 - Capture Channel 0 Enable - 16 - 1 - - - CAPTEN1 - Capture Channel 1 Enable - 17 - 1 - - - COPEN0 - Capture On Pin 0 Enable - 20 - 1 - - - COPEN1 - Capture On Pin 1 Enable - 21 - 1 - - - - - CTRLBCLR - Control B Clear - 0x4 - 8 - 0x00 - - - DIR - Counter Direction - 0 - 1 - - - LUPD - Lock Update - 1 - 1 - - - ONESHOT - One-Shot on Counter - 2 - 1 - - - CMD - Command - 5 - 3 - - CMDSelect - - NONE - No action - 0 - - - RETRIGGER - Force a start, restart or retrigger - 1 - - - STOP - Force a stop - 2 - - - UPDATE - Force update of double-buffered register - 3 - - - READSYNC - Force a read synchronization of COUNT - 4 - - - DMAOS - One-shot DMA trigger - 5 - - - - - - - CTRLBSET - Control B Set - 0x5 - 8 - 0x00 - - - DIR - Counter Direction - 0 - 1 - - - LUPD - Lock Update - 1 - 1 - - - ONESHOT - One-Shot on Counter - 2 - 1 - - - CMD - Command - 5 - 3 - - CMDSelect - - NONE - No action - 0 - - - RETRIGGER - Force a start, restart or retrigger - 1 - - - STOP - Force a stop - 2 - - - UPDATE - Force update of double-buffered register - 3 - - - READSYNC - Force a read synchronization of COUNT - 4 - - - DMAOS - One-shot DMA trigger - 5 - - - - - - - EVCTRL - Event Control - 0x6 - 16 - 0x0000 - - - EVACT - Event Action - 0 - 3 - - EVACTSelect - - OFF - Event action disabled - 0 - - - RETRIGGER - Start, restart or retrigger TC on event - 1 - - - COUNT - Count on event - 2 - - - START - Start TC on event - 3 - - - STAMP - Time stamp capture - 4 - - - PPW - Period catured in CC0, pulse width in CC1 - 5 - - - PWP - Period catured in CC1, pulse width in CC0 - 6 - - - PW - Pulse width capture - 7 - - - - - TCINV - TC Event Input Polarity - 4 - 1 - - - TCEI - TC Event Enable - 5 - 1 - - - OVFEO - Event Output Enable - 8 - 1 - - - MCEO0 - MC Event Output Enable 0 - 12 - 1 - - - MCEO1 - MC Event Output Enable 1 - 13 - 1 - - - - - INTENCLR - Interrupt Enable Clear - 0x8 - 8 - 0x00 - - - OVF - OVF Interrupt Disable - 0 - 1 - - - ERR - ERR Interrupt Disable - 1 - 1 - - - MC0 - MC Interrupt Disable 0 - 4 - 1 - - - MC1 - MC Interrupt Disable 1 - 5 - 1 - - - - - INTENSET - Interrupt Enable Set - 0x9 - 8 - 0x00 - - - OVF - OVF Interrupt Enable - 0 - 1 - - - ERR - ERR Interrupt Enable - 1 - 1 - - - MC0 - MC Interrupt Enable 0 - 4 - 1 - - - MC1 - MC Interrupt Enable 1 - 5 - 1 - - - - - INTFLAG - Interrupt Flag Status and Clear - 0xA - 8 - 0x00 - - - OVF - OVF Interrupt Flag - 0 - 1 - - - ERR - ERR Interrupt Flag - 1 - 1 - - - MC0 - MC Interrupt Flag 0 - 4 - 1 - - - MC1 - MC Interrupt Flag 1 - 5 - 1 - - - - - STATUS - Status - 0xB - 8 - 0x01 - - - STOP - Stop Status Flag - 0 - 1 - - - SLAVE - Slave Status Flag - 1 - 1 - - - PERBUFV - Synchronization Busy Status - 3 - 1 - - - CCBUFV0 - Compare channel buffer 0 valid - 4 - 1 - - - CCBUFV1 - Compare channel buffer 1 valid - 5 - 1 - - - - - WAVE - Waveform Generation Control - 0xC - 8 - 0x00 - - - WAVEGEN - Waveform Generation Mode - 0 - 2 - - WAVEGENSelect - - NFRQ - Normal frequency - 0 - - - MFRQ - Match frequency - 1 - - - NPWM - Normal PWM - 2 - - - MPWM - Match PWM - 3 - - - - - - - DRVCTRL - Control C - 0xD - 8 - 0x00 - - - INVEN0 - Output Waveform Invert Enable 0 - 0 - 1 - - - INVEN1 - Output Waveform Invert Enable 1 - 1 - 1 - - - - - DBGCTRL - Debug Control - 0xF - 8 - 0x00 - - - DBGRUN - Run During Debug - 0 - 1 - - - - - SYNCBUSY - Synchronization Status - 0x10 - 32 - read-only - 0x00000000 - - - SWRST - swrst - 0 - 1 - - - ENABLE - enable - 1 - 1 - - - CTRLB - CTRLB - 2 - 1 - - - STATUS - STATUS - 3 - 1 - - - COUNT - Counter - 4 - 1 - - - PER - Period - 5 - 1 - - - CC0 - Compare Channel 0 - 6 - 1 - - - CC1 - Compare Channel 1 - 7 - 1 - - - - - COUNT - COUNT32 Count - 0x14 - 32 - 0x00000000 - - - COUNT - Counter Value - 0 - 32 - - - - - 2 - 4 - CC[%s] - COUNT32 Compare and Capture - 0x1C - 32 - 0x00000000 - - - CC - Counter/Compare Value - 0 - 32 - - - - - 2 - 4 - CCBUF[%s] - COUNT32 Compare and Capture Buffer - 0x30 - 32 - 0x00000000 - - - CCBUF - Counter/Compare Buffer Value - 0 - 32 - - - - - - - - TC1 - 0x42003400 - - TC1 - 21 - - - - TC2 - 0x42003800 - - TC2 - 22 - - - - TC3 - 0x42003C00 - - TC3 - 23 - - - - TC4 - 0x42004000 - - TC4 - 24 - - - - TCC0 - U22133.0.0 - Timer Counter Control - TCC - TCC_ - 0x42002400 - - 0 - 0x80 - registers - - - TCC0 - 17 - - - - CTRLA - Control A - 0x0 - 32 - 0x00000000 - - - SWRST - Software Reset - 0 - 1 - - - ENABLE - Enable - 1 - 1 - - - RESOLUTION - Enhanced Resolution - 5 - 2 - - RESOLUTIONSelect - - NONE - Dithering is disabled - 0 - - - DITH4 - Dithering is done every 16 PWM frames - 1 - - - DITH5 - Dithering is done every 32 PWM frames - 2 - - - DITH6 - Dithering is done every 64 PWM frames - 3 - - - - - PRESCALER - Prescaler - 8 - 3 - - PRESCALERSelect - - DIV1 - No division - 0 - - - DIV2 - Divide by 2 - 1 - - - DIV4 - Divide by 4 - 2 - - - DIV8 - Divide by 8 - 3 - - - DIV16 - Divide by 16 - 4 - - - DIV64 - Divide by 64 - 5 - - - DIV256 - Divide by 256 - 6 - - - DIV1024 - Divide by 1024 - 7 - - - - - RUNSTDBY - Run in Standby - 11 - 1 - - - PRESCSYNC - Prescaler and Counter Synchronization Selection - 12 - 2 - - PRESCSYNCSelect - - GCLK - Reload or reset counter on next GCLK - 0 - - - PRESC - Reload or reset counter on next prescaler clock - 1 - - - RESYNC - Reload or reset counter on next GCLK and reset prescaler counter - 2 - - - - - ALOCK - Auto Lock - 14 - 1 - - - MSYNC - Master Synchronization (only for TCC Slave Instance) - 15 - 1 - - - DMAOS - DMA One-shot Trigger Mode - 23 - 1 - - - CPTEN0 - Capture Channel 0 Enable - 24 - 1 - - - CPTEN1 - Capture Channel 1 Enable - 25 - 1 - - - CPTEN2 - Capture Channel 2 Enable - 26 - 1 - - - CPTEN3 - Capture Channel 3 Enable - 27 - 1 - - - - - CTRLBCLR - Control B Clear - 0x4 - 8 - 0x00 - - - DIR - Counter Direction - 0 - 1 - - - LUPD - Lock Update - 1 - 1 - - - ONESHOT - One-Shot - 2 - 1 - - - IDXCMD - Ramp Index Command - 3 - 2 - - IDXCMDSelect - - DISABLE - Command disabled: Index toggles between cycles A and B - 0 - - - SET - Set index: cycle B will be forced in the next cycle - 1 - - - CLEAR - Clear index: cycle A will be forced in the next cycle - 2 - - - HOLD - Hold index: the next cycle will be the same as the current cycle - 3 - - - - - CMD - TCC Command - 5 - 3 - - CMDSelect - - NONE - No action - 0 - - - RETRIGGER - Clear start, restart or retrigger - 1 - - - STOP - Force stop - 2 - - - UPDATE - Force update or double buffered registers - 3 - - - READSYNC - Force COUNT read synchronization - 4 - - - DMAOS - One-shot DMA trigger - 5 - - - - - - - CTRLBSET - Control B Set - 0x5 - 8 - 0x00 - - - DIR - Counter Direction - 0 - 1 - - - LUPD - Lock Update - 1 - 1 - - - ONESHOT - One-Shot - 2 - 1 - - - IDXCMD - Ramp Index Command - 3 - 2 - - IDXCMDSelect - - DISABLE - Command disabled: Index toggles between cycles A and B - 0 - - - SET - Set index: cycle B will be forced in the next cycle - 1 - - - CLEAR - Clear index: cycle A will be forced in the next cycle - 2 - - - HOLD - Hold index: the next cycle will be the same as the current cycle - 3 - - - - - CMD - TCC Command - 5 - 3 - - CMDSelect - - NONE - No action - 0 - - - RETRIGGER - Clear start, restart or retrigger - 1 - - - STOP - Force stop - 2 - - - UPDATE - Force update or double buffered registers - 3 - - - READSYNC - Force COUNT read synchronization - 4 - - - DMAOS - One-shot DMA trigger - 5 - - - - - - - SYNCBUSY - Synchronization Busy - 0x8 - 32 - read-only - 0x00000000 - - - SWRST - Swrst Busy - 0 - 1 - - - ENABLE - Enable Busy - 1 - 1 - - - CTRLB - Ctrlb Busy - 2 - 1 - - - STATUS - Status Busy - 3 - 1 - - - COUNT - Count Busy - 4 - 1 - - - PATT - Pattern Busy - 5 - 1 - - - WAVE - Wave Busy - 6 - 1 - - - PER - Period Busy - 7 - 1 - - - CC0 - Compare Channel 0 Busy - 8 - 1 - - - CC1 - Compare Channel 1 Busy - 9 - 1 - - - CC2 - Compare Channel 2 Busy - 10 - 1 - - - CC3 - Compare Channel 3 Busy - 11 - 1 - - - - - FCTRLA - Recoverable Fault A Configuration - 0xC - 32 - 0x00000000 - - - SRC - Fault A Source - 0 - 2 - - SRCSelect - - DISABLE - Fault input disabled - 0 - - - ENABLE - MCEx (x=0,1) event input - 1 - - - INVERT - Inverted MCEx (x=0,1) event input - 2 - - - ALTFAULT - Alternate fault (A or B) state at the end of the previous period - 3 - - - - - KEEP - Fault A Keeper - 3 - 1 - - - QUAL - Fault A Qualification - 4 - 1 - - - BLANK - Fault A Blanking Mode - 5 - 2 - - BLANKSelect - - START - Blanking applied from start of the ramp - 0 - - - RISE - Blanking applied from rising edge of the output waveform - 1 - - - FALL - Blanking applied from falling edge of the output waveform - 2 - - - BOTH - Blanking applied from each toggle of the output waveform - 3 - - - - - RESTART - Fault A Restart - 7 - 1 - - - HALT - Fault A Halt Mode - 8 - 2 - - HALTSelect - - DISABLE - Halt action disabled - 0 - - - HW - Hardware halt action - 1 - - - SW - Software halt action - 2 - - - NR - Non-recoverable fault - 3 - - - - - CHSEL - Fault A Capture Channel - 10 - 2 - - CHSELSelect - - CC0 - Capture value stored in channel 0 - 0 - - - CC1 - Capture value stored in channel 1 - 1 - - - CC2 - Capture value stored in channel 2 - 2 - - - CC3 - Capture value stored in channel 3 - 3 - - - - - CAPTURE - Fault A Capture Action - 12 - 3 - - CAPTURESelect - - DISABLE - No capture - 0 - - - CAPT - Capture on fault - 1 - - - CAPTMIN - Minimum capture - 2 - - - CAPTMAX - Maximum capture - 3 - - - LOCMIN - Minimum local detection - 4 - - - LOCMAX - Maximum local detection - 5 - - - DERIV0 - Minimum and maximum local detection - 6 - - - CAPTMARK - Capture with ramp index as MSB value - 7 - - - - - BLANKPRESC - Fault A Blanking Prescaler - 15 - 1 - - - BLANKVAL - Fault A Blanking Time - 16 - 8 - - - FILTERVAL - Fault A Filter Value - 24 - 4 - - - - - FCTRLB - Recoverable Fault B Configuration - 0x10 - 32 - 0x00000000 - - - SRC - Fault B Source - 0 - 2 - - SRCSelect - - DISABLE - Fault input disabled - 0 - - - ENABLE - MCEx (x=0,1) event input - 1 - - - INVERT - Inverted MCEx (x=0,1) event input - 2 - - - ALTFAULT - Alternate fault (A or B) state at the end of the previous period - 3 - - - - - KEEP - Fault B Keeper - 3 - 1 - - - QUAL - Fault B Qualification - 4 - 1 - - - BLANK - Fault B Blanking Mode - 5 - 2 - - BLANKSelect - - START - Blanking applied from start of the ramp - 0 - - - RISE - Blanking applied from rising edge of the output waveform - 1 - - - FALL - Blanking applied from falling edge of the output waveform - 2 - - - BOTH - Blanking applied from each toggle of the output waveform - 3 - - - - - RESTART - Fault B Restart - 7 - 1 - - - HALT - Fault B Halt Mode - 8 - 2 - - HALTSelect - - DISABLE - Halt action disabled - 0 - - - HW - Hardware halt action - 1 - - - SW - Software halt action - 2 - - - NR - Non-recoverable fault - 3 - - - - - CHSEL - Fault B Capture Channel - 10 - 2 - - CHSELSelect - - CC0 - Capture value stored in channel 0 - 0 - - - CC1 - Capture value stored in channel 1 - 1 - - - CC2 - Capture value stored in channel 2 - 2 - - - CC3 - Capture value stored in channel 3 - 3 - - - - - CAPTURE - Fault B Capture Action - 12 - 3 - - CAPTURESelect - - DISABLE - No capture - 0 - - - CAPT - Capture on fault - 1 - - - CAPTMIN - Minimum capture - 2 - - - CAPTMAX - Maximum capture - 3 - - - LOCMIN - Minimum local detection - 4 - - - LOCMAX - Maximum local detection - 5 - - - DERIV0 - Minimum and maximum local detection - 6 - - - CAPTMARK - Capture with ramp index as MSB value - 7 - - - - - BLANKPRESC - Fault B Blanking Prescaler - 15 - 1 - - - BLANKVAL - Fault B Blanking Time - 16 - 8 - - - FILTERVAL - Fault B Filter Value - 24 - 4 - - - - - WEXCTRL - Waveform Extension Configuration - 0x14 - 32 - 0x00000000 - - - OTMX - Output Matrix - 0 - 2 - - - DTIEN0 - Dead-time Insertion Generator 0 Enable - 8 - 1 - - - DTIEN1 - Dead-time Insertion Generator 1 Enable - 9 - 1 - - - DTIEN2 - Dead-time Insertion Generator 2 Enable - 10 - 1 - - - DTIEN3 - Dead-time Insertion Generator 3 Enable - 11 - 1 - - - DTLS - Dead-time Low Side Outputs Value - 16 - 8 - - - DTHS - Dead-time High Side Outputs Value - 24 - 8 - - - - - DRVCTRL - Driver Control - 0x18 - 32 - 0x00000000 - - - NRE0 - Non-Recoverable State 0 Output Enable - 0 - 1 - - - NRE1 - Non-Recoverable State 1 Output Enable - 1 - 1 - - - NRE2 - Non-Recoverable State 2 Output Enable - 2 - 1 - - - NRE3 - Non-Recoverable State 3 Output Enable - 3 - 1 - - - NRE4 - Non-Recoverable State 4 Output Enable - 4 - 1 - - - NRE5 - Non-Recoverable State 5 Output Enable - 5 - 1 - - - NRE6 - Non-Recoverable State 6 Output Enable - 6 - 1 - - - NRE7 - Non-Recoverable State 7 Output Enable - 7 - 1 - - - NRV0 - Non-Recoverable State 0 Output Value - 8 - 1 - - - NRV1 - Non-Recoverable State 1 Output Value - 9 - 1 - - - NRV2 - Non-Recoverable State 2 Output Value - 10 - 1 - - - NRV3 - Non-Recoverable State 3 Output Value - 11 - 1 - - - NRV4 - Non-Recoverable State 4 Output Value - 12 - 1 - - - NRV5 - Non-Recoverable State 5 Output Value - 13 - 1 - - - NRV6 - Non-Recoverable State 6 Output Value - 14 - 1 - - - NRV7 - Non-Recoverable State 7 Output Value - 15 - 1 - - - INVEN0 - Output Waveform 0 Inversion - 16 - 1 - - - INVEN1 - Output Waveform 1 Inversion - 17 - 1 - - - INVEN2 - Output Waveform 2 Inversion - 18 - 1 - - - INVEN3 - Output Waveform 3 Inversion - 19 - 1 - - - INVEN4 - Output Waveform 4 Inversion - 20 - 1 - - - INVEN5 - Output Waveform 5 Inversion - 21 - 1 - - - INVEN6 - Output Waveform 6 Inversion - 22 - 1 - - - INVEN7 - Output Waveform 7 Inversion - 23 - 1 - - - FILTERVAL0 - Non-Recoverable Fault Input 0 Filter Value - 24 - 4 - - - FILTERVAL1 - Non-Recoverable Fault Input 1 Filter Value - 28 - 4 - - - - - DBGCTRL - Debug Control - 0x1E - 8 - 0x00 - - - DBGRUN - Debug Running Mode - 0 - 1 - - - FDDBD - Fault Detection on Debug Break Detection - 2 - 1 - - - - - EVCTRL - Event Control - 0x20 - 32 - 0x00000000 - - - EVACT0 - Timer/counter Input Event0 Action - 0 - 3 - - EVACT0Select - - OFF - Event action disabled - 0 - - - RETRIGGER - Start, restart or re-trigger counter on event - 1 - - - COUNTEV - Count on event - 2 - - - START - Start counter on event - 3 - - - INC - Increment counter on event - 4 - - - COUNT - Count on active state of asynchronous event - 5 - - - STAMP - Stamp capture - 6 - - - FAULT - Non-recoverable fault - 7 - - - - - EVACT1 - Timer/counter Input Event1 Action - 3 - 3 - - EVACT1Select - - OFF - Event action disabled - 0 - - - RETRIGGER - Re-trigger counter on event - 1 - - - DIR - Direction control - 2 - - - STOP - Stop counter on event - 3 - - - DEC - Decrement counter on event - 4 - - - PPW - Period capture value in CC0 register, pulse width capture value in CC1 register - 5 - - - PWP - Period capture value in CC1 register, pulse width capture value in CC0 register - 6 - - - FAULT - Non-recoverable fault - 7 - - - - - CNTSEL - Timer/counter Output Event Mode - 6 - 2 - - CNTSELSelect - - START - An interrupt/event is generated when a new counter cycle starts - 0 - - - END - An interrupt/event is generated when a counter cycle ends - 1 - - - BETWEEN - An interrupt/event is generated when a counter cycle ends, except for the first and last cycles - 2 - - - BOUNDARY - An interrupt/event is generated when a new counter cycle starts or a counter cycle ends - 3 - - - - - OVFEO - Overflow/Underflow Output Event Enable - 8 - 1 - - - TRGEO - Retrigger Output Event Enable - 9 - 1 - - - CNTEO - Timer/counter Output Event Enable - 10 - 1 - - - TCINV0 - Inverted Event 0 Input Enable - 12 - 1 - - - TCINV1 - Inverted Event 1 Input Enable - 13 - 1 - - - TCEI0 - Timer/counter Event 0 Input Enable - 14 - 1 - - - TCEI1 - Timer/counter Event 1 Input Enable - 15 - 1 - - - MCEI0 - Match or Capture Channel 0 Event Input Enable - 16 - 1 - - - MCEI1 - Match or Capture Channel 1 Event Input Enable - 17 - 1 - - - MCEI2 - Match or Capture Channel 2 Event Input Enable - 18 - 1 - - - MCEI3 - Match or Capture Channel 3 Event Input Enable - 19 - 1 - - - MCEO0 - Match or Capture Channel 0 Event Output Enable - 24 - 1 - - - MCEO1 - Match or Capture Channel 1 Event Output Enable - 25 - 1 - - - MCEO2 - Match or Capture Channel 2 Event Output Enable - 26 - 1 - - - MCEO3 - Match or Capture Channel 3 Event Output Enable - 27 - 1 - - - - - INTENCLR - Interrupt Enable Clear - 0x24 - 32 - 0x00000000 - - - OVF - Overflow Interrupt Enable - 0 - 1 - - - TRG - Retrigger Interrupt Enable - 1 - 1 - - - CNT - Counter Interrupt Enable - 2 - 1 - - - ERR - Error Interrupt Enable - 3 - 1 - - - UFS - Non-Recoverable Update Fault Interrupt Enable - 10 - 1 - - - DFS - Non-Recoverable Debug Fault Interrupt Enable - 11 - 1 - - - FAULTA - Recoverable Fault A Interrupt Enable - 12 - 1 - - - FAULTB - Recoverable Fault B Interrupt Enable - 13 - 1 - - - FAULT0 - Non-Recoverable Fault 0 Interrupt Enable - 14 - 1 - - - FAULT1 - Non-Recoverable Fault 1 Interrupt Enable - 15 - 1 - - - MC0 - Match or Capture Channel 0 Interrupt Enable - 16 - 1 - - - MC1 - Match or Capture Channel 1 Interrupt Enable - 17 - 1 - - - MC2 - Match or Capture Channel 2 Interrupt Enable - 18 - 1 - - - MC3 - Match or Capture Channel 3 Interrupt Enable - 19 - 1 - - - - - INTENSET - Interrupt Enable Set - 0x28 - 32 - 0x00000000 - - - OVF - Overflow Interrupt Enable - 0 - 1 - - - TRG - Retrigger Interrupt Enable - 1 - 1 - - - CNT - Counter Interrupt Enable - 2 - 1 - - - ERR - Error Interrupt Enable - 3 - 1 - - - UFS - Non-Recoverable Update Fault Interrupt Enable - 10 - 1 - - - DFS - Non-Recoverable Debug Fault Interrupt Enable - 11 - 1 - - - FAULTA - Recoverable Fault A Interrupt Enable - 12 - 1 - - - FAULTB - Recoverable Fault B Interrupt Enable - 13 - 1 - - - FAULT0 - Non-Recoverable Fault 0 Interrupt Enable - 14 - 1 - - - FAULT1 - Non-Recoverable Fault 1 Interrupt Enable - 15 - 1 - - - MC0 - Match or Capture Channel 0 Interrupt Enable - 16 - 1 - - - MC1 - Match or Capture Channel 1 Interrupt Enable - 17 - 1 - - - MC2 - Match or Capture Channel 2 Interrupt Enable - 18 - 1 - - - MC3 - Match or Capture Channel 3 Interrupt Enable - 19 - 1 - - - - - INTFLAG - Interrupt Flag Status and Clear - 0x2C - 32 - 0x00000000 - - - OVF - Overflow - 0 - 1 - - - TRG - Retrigger - 1 - 1 - - - CNT - Counter - 2 - 1 - - - ERR - Error - 3 - 1 - - - UFS - Non-Recoverable Update Fault - 10 - 1 - - - DFS - Non-Recoverable Debug Fault - 11 - 1 - - - FAULTA - Recoverable Fault A - 12 - 1 - - - FAULTB - Recoverable Fault B - 13 - 1 - - - FAULT0 - Non-Recoverable Fault 0 - 14 - 1 - - - FAULT1 - Non-Recoverable Fault 1 - 15 - 1 - - - MC0 - Match or Capture 0 - 16 - 1 - - - MC1 - Match or Capture 1 - 17 - 1 - - - MC2 - Match or Capture 2 - 18 - 1 - - - MC3 - Match or Capture 3 - 19 - 1 - - - - - STATUS - Status - 0x30 - 32 - 0x00000001 - - - STOP - Stop - 0 - 1 - - - IDX - Ramp - 1 - 1 - - - UFS - Non-recoverable Update Fault State - 2 - 1 - - - DFS - Non-Recoverable Debug Fault State - 3 - 1 - - - SLAVE - Slave - 4 - 1 - - - PATTBUFV - Pattern Buffer Valid - 5 - 1 - - - PERBUFV - Period Buffer Valid - 7 - 1 - - - FAULTAIN - Recoverable Fault A Input - 8 - 1 - - - FAULTBIN - Recoverable Fault B Input - 9 - 1 - - - FAULT0IN - Non-Recoverable Fault0 Input - 10 - 1 - - - FAULT1IN - Non-Recoverable Fault1 Input - 11 - 1 - - - FAULTA - Recoverable Fault A State - 12 - 1 - - - FAULTB - Recoverable Fault B State - 13 - 1 - - - FAULT0 - Non-Recoverable Fault 0 State - 14 - 1 - - - FAULT1 - Non-Recoverable Fault 1 State - 15 - 1 - - - CCBUFV0 - Compare Channel 0 Buffer Valid - 16 - 1 - - - CCBUFV1 - Compare Channel 1 Buffer Valid - 17 - 1 - - - CCBUFV2 - Compare Channel 2 Buffer Valid - 18 - 1 - - - CCBUFV3 - Compare Channel 3 Buffer Valid - 19 - 1 - - - CMP0 - Compare Channel 0 Value - 24 - 1 - - - CMP1 - Compare Channel 1 Value - 25 - 1 - - - CMP2 - Compare Channel 2 Value - 26 - 1 - - - CMP3 - Compare Channel 3 Value - 27 - 1 - - - - - COUNT - Count - 0x34 - 32 - 0x00000000 - - - COUNT - Counter Value - 0 - 24 - - - - - COUNT_DITH4_MODE - Count - COUNT - 0x34 - 32 - 0x00000000 - - - COUNT - Counter Value - 4 - 20 - - - - - COUNT_DITH5_MODE - Count - COUNT - 0x34 - 32 - 0x00000000 - - - COUNT - Counter Value - 5 - 19 - - - - - COUNT_DITH6_MODE - Count - COUNT - 0x34 - 32 - 0x00000000 - - - COUNT - Counter Value - 6 - 18 - - - - - PATT - Pattern - 0x38 - 16 - 0x0000 - - - PGE0 - Pattern Generator 0 Output Enable - 0 - 1 - - - PGE1 - Pattern Generator 1 Output Enable - 1 - 1 - - - PGE2 - Pattern Generator 2 Output Enable - 2 - 1 - - - PGE3 - Pattern Generator 3 Output Enable - 3 - 1 - - - PGE4 - Pattern Generator 4 Output Enable - 4 - 1 - - - PGE5 - Pattern Generator 5 Output Enable - 5 - 1 - - - PGE6 - Pattern Generator 6 Output Enable - 6 - 1 - - - PGE7 - Pattern Generator 7 Output Enable - 7 - 1 - - - PGV0 - Pattern Generator 0 Output Value - 8 - 1 - - - PGV1 - Pattern Generator 1 Output Value - 9 - 1 - - - PGV2 - Pattern Generator 2 Output Value - 10 - 1 - - - PGV3 - Pattern Generator 3 Output Value - 11 - 1 - - - PGV4 - Pattern Generator 4 Output Value - 12 - 1 - - - PGV5 - Pattern Generator 5 Output Value - 13 - 1 - - - PGV6 - Pattern Generator 6 Output Value - 14 - 1 - - - PGV7 - Pattern Generator 7 Output Value - 15 - 1 - - - - - WAVE - Waveform Control - 0x3C - 32 - 0x00000000 - - - WAVEGEN - Waveform Generation - 0 - 3 - - WAVEGENSelect - - NFRQ - Normal frequency - 0 - - - MFRQ - Match frequency - 1 - - - NPWM - Normal PWM - 2 - - - DSCRITICAL - Dual-slope critical - 4 - - - DSBOTTOM - Dual-slope with interrupt/event condition when COUNT reaches ZERO - 5 - - - DSBOTH - Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP - 6 - - - DSTOP - Dual-slope with interrupt/event condition when COUNT reaches TOP - 7 - - - - - RAMP - Ramp Mode - 4 - 2 - - RAMPSelect - - RAMP1 - RAMP1 operation - 0 - - - RAMP2A - Alternative RAMP2 operation - 1 - - - RAMP2 - RAMP2 operation - 2 - - - RAMP2C - Critical RAMP2 operation - 3 - - - - - CIPEREN - Circular period Enable - 7 - 1 - - - CICCEN0 - Circular Channel 0 Enable - 8 - 1 - - - CICCEN1 - Circular Channel 1 Enable - 9 - 1 - - - CICCEN2 - Circular Channel 2 Enable - 10 - 1 - - - CICCEN3 - Circular Channel 3 Enable - 11 - 1 - - - POL0 - Channel 0 Polarity - 16 - 1 - - - POL1 - Channel 1 Polarity - 17 - 1 - - - POL2 - Channel 2 Polarity - 18 - 1 - - - POL3 - Channel 3 Polarity - 19 - 1 - - - SWAP0 - Swap DTI Output Pair 0 - 24 - 1 - - - SWAP1 - Swap DTI Output Pair 1 - 25 - 1 - - - SWAP2 - Swap DTI Output Pair 2 - 26 - 1 - - - SWAP3 - Swap DTI Output Pair 3 - 27 - 1 - - - - - PER - Period - 0x40 - 32 - 0xFFFFFFFF - - - PER - Period Value - 0 - 24 - - - - - PER_DITH4_MODE - Period - PER - 0x40 - 32 - 0xFFFFFFFF - - - DITHER - Dithering Cycle Number - 0 - 4 - - - PER - Period Value - 4 - 20 - - - - - PER_DITH5_MODE - Period - PER - 0x40 - 32 - 0xFFFFFFFF - - - DITHER - Dithering Cycle Number - 0 - 5 - - - PER - Period Value - 5 - 19 - - - - - PER_DITH6_MODE - Period - PER - 0x40 - 32 - 0xFFFFFFFF - - - DITHER - Dithering Cycle Number - 0 - 6 - - - PER - Period Value - 6 - 18 - - - - - 4 - 4 - CC[%s] - Compare and Capture - 0x44 - 32 - 0x00000000 - - - CC - Channel Compare/Capture Value - 0 - 24 - - - - - 4 - 4 - CC_DITH4_MODE[%s] - Compare and Capture - CC[%s] - 0x44 - 32 - 0x00000000 - - - DITHER - Dithering Cycle Number - 0 - 4 - - - CC - Channel Compare/Capture Value - 4 - 20 - - - - - 4 - 4 - CC_DITH5_MODE[%s] - Compare and Capture - CC[%s] - 0x44 - 32 - 0x00000000 - - - DITHER - Dithering Cycle Number - 0 - 5 - - - CC - Channel Compare/Capture Value - 5 - 19 - - - - - 4 - 4 - CC_DITH6_MODE[%s] - Compare and Capture - CC[%s] - 0x44 - 32 - 0x00000000 - - - DITHER - Dithering Cycle Number - 0 - 6 - - - CC - Channel Compare/Capture Value - 6 - 18 - - - - - PATTBUF - Pattern Buffer - 0x64 - 16 - 0x0000 - - - PGEB0 - Pattern Generator 0 Output Enable Buffer - 0 - 1 - - - PGEB1 - Pattern Generator 1 Output Enable Buffer - 1 - 1 - - - PGEB2 - Pattern Generator 2 Output Enable Buffer - 2 - 1 - - - PGEB3 - Pattern Generator 3 Output Enable Buffer - 3 - 1 - - - PGEB4 - Pattern Generator 4 Output Enable Buffer - 4 - 1 - - - PGEB5 - Pattern Generator 5 Output Enable Buffer - 5 - 1 - - - PGEB6 - Pattern Generator 6 Output Enable Buffer - 6 - 1 - - - PGEB7 - Pattern Generator 7 Output Enable Buffer - 7 - 1 - - - PGVB0 - Pattern Generator 0 Output Enable - 8 - 1 - - - PGVB1 - Pattern Generator 1 Output Enable - 9 - 1 - - - PGVB2 - Pattern Generator 2 Output Enable - 10 - 1 - - - PGVB3 - Pattern Generator 3 Output Enable - 11 - 1 - - - PGVB4 - Pattern Generator 4 Output Enable - 12 - 1 - - - PGVB5 - Pattern Generator 5 Output Enable - 13 - 1 - - - PGVB6 - Pattern Generator 6 Output Enable - 14 - 1 - - - PGVB7 - Pattern Generator 7 Output Enable - 15 - 1 - - - - - PERBUF - Period Buffer - 0x6C - 32 - 0xFFFFFFFF - - - PERBUF - Period Buffer Value - 0 - 24 - - - - - PERBUF_DITH4_MODE - Period Buffer - PERBUF - 0x6C - 32 - 0xFFFFFFFF - - - DITHERBUF - Dithering Buffer Cycle Number - 0 - 4 - - - PERBUF - Period Buffer Value - 4 - 20 - - - - - PERBUF_DITH5_MODE - Period Buffer - PERBUF - 0x6C - 32 - 0xFFFFFFFF - - - DITHERBUF - Dithering Buffer Cycle Number - 0 - 5 - - - PERBUF - Period Buffer Value - 5 - 19 - - - - - PERBUF_DITH6_MODE - Period Buffer - PERBUF - 0x6C - 32 - 0xFFFFFFFF - - - DITHERBUF - Dithering Buffer Cycle Number - 0 - 6 - - - PERBUF - Period Buffer Value - 6 - 18 - - - - - 4 - 4 - CCBUF[%s] - Compare and Capture Buffer - 0x70 - 32 - 0x00000000 - - - CCBUF - Channel Compare/Capture Buffer Value - 0 - 24 - - - - - 4 - 4 - CCBUF_DITH4_MODE[%s] - Compare and Capture Buffer - CCBUF[%s] - 0x70 - 32 - 0x00000000 - - - CCBUF - Channel Compare/Capture Buffer Value - 0 - 4 - - - DITHERBUF - Dithering Buffer Cycle Number - 4 - 20 - - - - - 4 - 4 - CCBUF_DITH5_MODE[%s] - Compare and Capture Buffer - CCBUF[%s] - 0x70 - 32 - 0x00000000 - - - DITHERBUF - Dithering Buffer Cycle Number - 0 - 5 - - - CCBUF - Channel Compare/Capture Buffer Value - 5 - 19 - - - - - 4 - 4 - CCBUF_DITH6_MODE[%s] - Compare and Capture Buffer - CCBUF[%s] - 0x70 - 32 - 0x00000000 - - - DITHERBUF - Dithering Buffer Cycle Number - 0 - 6 - - - CCBUF - Channel Compare/Capture Buffer Value - 6 - 18 - - - - - - - TCC1 - 0x42002800 - - TCC1 - 18 - - - - TCC2 - 0x42002C00 - - TCC2 - 19 - - - - WDT - U22511.0.1 - Watchdog Timer - WDT - WDT_ - 0x40002000 - - 0 - 0xD - registers - - - WDT - 1 - - - - CTRLA - Control - 0x0 - 8 - 0x00 - - - ENABLE - Enable - 1 - 1 - - - WEN - Watchdog Timer Window Mode Enable - 2 - 1 - - - ALWAYSON - Always-On - 7 - 1 - - - - - CONFIG - Configuration - 0x1 - 8 - 0xBB - - - PER - Time-Out Period - 0 - 4 - - PERSelect - - CYC8 - 8 clock cycles - 0x0 - - - CYC16 - 16 clock cycles - 0x1 - - - CYC32 - 32 clock cycles - 0x2 - - - CYC64 - 64 clock cycles - 0x3 - - - CYC128 - 128 clock cycles - 0x4 - - - CYC256 - 256 clock cycles - 0x5 - - - CYC512 - 512 clock cycles - 0x6 - - - CYC1024 - 1024 clock cycles - 0x7 - - - CYC2048 - 2048 clock cycles - 0x8 - - - CYC4096 - 4096 clock cycles - 0x9 - - - CYC8192 - 8192 clock cycles - 0xA - - - CYC16384 - 16384 clock cycles - 0xB - - - - - WINDOW - Window Mode Time-Out Period - 4 - 4 - - WINDOWSelect - - CYC8 - 8 clock cycles - 0x0 - - - CYC16 - 16 clock cycles - 0x1 - - - CYC32 - 32 clock cycles - 0x2 - - - CYC64 - 64 clock cycles - 0x3 - - - CYC128 - 128 clock cycles - 0x4 - - - CYC256 - 256 clock cycles - 0x5 - - - CYC512 - 512 clock cycles - 0x6 - - - CYC1024 - 1024 clock cycles - 0x7 - - - CYC2048 - 2048 clock cycles - 0x8 - - - CYC4096 - 4096 clock cycles - 0x9 - - - CYC8192 - 8192 clock cycles - 0xA - - - CYC16384 - 16384 clock cycles - 0xB - - - - - - - EWCTRL - Early Warning Interrupt Control - 0x2 - 8 - 0x0B - - - EWOFFSET - Early Warning Interrupt Time Offset - 0 - 4 - - EWOFFSETSelect - - CYC8 - 8 clock cycles - 0x0 - - - CYC16 - 16 clock cycles - 0x1 - - - CYC32 - 32 clock cycles - 0x2 - - - CYC64 - 64 clock cycles - 0x3 - - - CYC128 - 128 clock cycles - 0x4 - - - CYC256 - 256 clock cycles - 0x5 - - - CYC512 - 512 clock cycles - 0x6 - - - CYC1024 - 1024 clock cycles - 0x7 - - - CYC2048 - 2048 clock cycles - 0x8 - - - CYC4096 - 4096 clock cycles - 0x9 - - - CYC8192 - 8192 clock cycles - 0xA - - - CYC16384 - 16384 clock cycles - 0xB - - - - - - - INTENCLR - Interrupt Enable Clear - 0x4 - 8 - 0x00 - - - EW - Early Warning Interrupt Enable - 0 - 1 - - - - - INTENSET - Interrupt Enable Set - 0x5 - 8 - 0x00 - - - EW - Early Warning Interrupt Enable - 0 - 1 - - - - - INTFLAG - Interrupt Flag Status and Clear - 0x6 - 8 - 0x00 - - - EW - Early Warning - 0 - 1 - - - - - SYNCBUSY - Synchronization Busy - 0x8 - 32 - read-only - 0x00000000 - - - ENABLE - Enable Busy - 1 - 1 - - - WEN - Window Enable Busy - 2 - 1 - - - ALWAYSON - Always-On Busy - 3 - 1 - - - CLEAR - Clear Busy - 4 - 1 - - - - - CLEAR - Clear - 0xC - 8 - write-only - 0x00 - - - CLEAR - Watchdog Clear - 0 - 8 - - CLEARSelect - - KEY - Clear Key - 0xA5 - - - - - - - - - MPU - Memory Protection Unit - MPU - MPU_ - 0xE000ED90 - - 0 - 0x14 - registers - - - - TYPE - MPU Type Register - 0x0 - 32 - read-only - - - SEPARATE - Separate instruction and Data Memory MapsRegions - 0 - 1 - - - DREGION - Number of Data Regions - 8 - 8 - - - IREGION - Number of Instruction Regions - 16 - 8 - - - - - CTRL - MPU Control Register - 0x4 - 32 - - - ENABLE - MPU Enable - 0 - 1 - - - HFNMIENA - Enable Hard Fault and NMI handlers - 1 - 1 - - - PRIVDEFENA - Enables privileged software access to default memory map - 2 - 1 - - - - - RNR - MPU Region Number Register - 0x8 - 32 - - - REGION - Region referenced by RBAR and RASR - 0 - 8 - - - - - RBAR - MPU Region Base Address Register - 0xC - 32 - - - REGION - Region number - 0 - 4 - - - VALID - Region number valid - 4 - 1 - - - ADDR - Region base address - 5 - 27 - - - - - RASR - MPU Region Attribute and Size Register - 0x10 - 32 - - - ENABLE - Region Enable - 0 - 1 - - - SIZE - Region Size - 1 - 5 - - - SRD - Sub-region disable - 8 - 8 - - - B - Bufferable bit - 16 - 1 - - - C - Cacheable bit - 17 - 1 - - - S - Shareable bit - 18 - 1 - - - TEX - TEX bit - 19 - 3 - - - AP - Access Permission - 24 - 3 - - - XN - Execute Never Attribute - 28 - 1 - - - - - - - NVIC - Nested Vectored Interrupt Controller - NVIC - NVIC_ - 0xE000E100 - - 0 - 0x320 - registers - - - - ISER - Interrupt Set Enable Register - 0x0 - 32 - 0x00000000 - - - SETENA - Interrupt set enable bits - 0 - 31 - - - - - ICER - Interrupt Clear Enable Register - 0x80 - 32 - 0x00000000 - - - CLRENA - Interrupt clear-enable bits - 0 - 31 - - - - - ISPR - Interrupt Set Pending Register - 0x100 - 32 - 0x00000000 - - - SETPEND - Interrupt set-pending bits - 0 - 31 - - - - - ICPR - Interrupt Clear Pending Register - 0x180 - 32 - 0x00000000 - - - CLRPEND - Interrupt clear-pending bits - 0 - 31 - - - - - 8 - 4 - IPR[%s] - Interrupt Priority Register n - 0x300 - 32 - 0x00000000 - - - PRI0 - Priority of interrupt n - 0 - 2 - - - PRI1 - Priority of interrupt n - 8 - 2 - - - PRI2 - Priority of interrupt n - 16 - 2 - - - PRI3 - Priority of interrupt n - 24 - 2 - - - - - - - SysTick - System timer - SysTick - SysTick_ - 0xE000E010 - - 0 - 0x10 - registers - - - - CSR - SysTick Control and Status Register - 0x0 - 32 - 0x4 - - - ENABLE - SysTick Counter Enable - 0 - 1 - - ENABLESelect - - VALUE_0 - Counter disabled - 0 - - - VALUE_1 - Counter enabled - 1 - - - - - TICKINT - SysTick Exception Request Enable - 1 - 1 - - TICKINTSelect - - VALUE_0 - Counting down to 0 does not assert the SysTick exception request - 0 - - - VALUE_1 - Counting down to 0 asserts the SysTick exception request - 1 - - - - - CLKSOURCE - Clock Source 0=external, 1=processor - 2 - 1 - - CLKSOURCESelect - - VALUE_0 - External clock - 0 - - - VALUE_1 - Processor clock - 1 - - - - - COUNTFLAG - Timer counted to 0 since last read of register - 16 - 1 - - - - - RVR - SysTick Reload Value Register - 0x4 - 32 - - - RELOAD - Value to load into the SysTick Current Value Register when the counter reaches 0 - 0 - 24 - - - - - CVR - SysTick Current Value Register - 0x8 - 32 - - - CURRENT - Current value at the time the register is accessed - 0 - 24 - - - - - CALIB - SysTick Calibration Value Register - 0xC - 32 - read-only - 0 - - - TENMS - Reload value to use for 10ms timing - 0 - 24 - - - SKEW - TENMS is rounded from non-integer ratio - 30 - 1 - - SKEWSelect - - VALUE_0 - 10ms calibration value is exact - 0 - - - VALUE_1 - 10ms calibration value is inexact, because of the clock frequency - 1 - - - - - NOREF - No Separate Reference Clock - 31 - 1 - - NOREFSelect - - VALUE_0 - The reference clock is provided - 0 - - - VALUE_1 - The reference clock is not provided - 1 - - - - - - - - - SystemControl - System Control Registers - SystemControl - SystemControl_ - 0xE000E000 - - 0 - 0xD34 - registers - - - - CPUID - CPUID Base Register - 0xD00 - 32 - read-only - 0x410CC601 - - - REVISION - Minor revision number - 0 - 4 - - - PARTNO - Processor Part Number, 0xC60=Cortex-M0+ - 4 - 12 - - - ARCHITECTURE - Processor Architecture, 0xC=ARMv6-M - 16 - 4 - - - VARIANT - Major revision number - 20 - 4 - - - IMPLEMENTER - Implementer code, ARM=0x41 - 24 - 8 - - - - - ICSR - Interrupt Control and State Register - 0xD04 - 32 - 0x00000000 - - - VECTACTIVE - Debug: Exception number of currently executing exception, or 0 if thread mode - 0 - 9 - - - VECTPENDING - Exception number of the highest priority pending enabled exception - 12 - 9 - - - ISRPENDING - Debug: NVIC interrupt pending - 22 - 1 - - - ISRPREEMPT - Debug: Pending exception serviced on exit from debug halt - 23 - 1 - - - PENDSTCLR - SysTick exception clear-pending bit - 25 - 1 - - PENDSTCLRSelect - - VALUE_0 - No effect - 0 - - - VALUE_1 - Removes the pending state from the SysTick exception - 1 - - - - - PENDSTSET - SysTick exception set-pending bit - 26 - 1 - - PENDSTSETSelect - - VALUE_0 - Write: no effect; read: SysTick exception is not pending - 0 - - - VALUE_1 - Write: changes SysTick exception state to pending; read: SysTick exception is pending - 1 - - - - - PENDSVCLR - PendSV clear-pending bit - 27 - 1 - - PENDSVCLRSelect - - VALUE_0 - No effect - 0 - - - VALUE_1 - Removes the pending state from the PendSV exception - 1 - - - - - PENDSVSET - PendSV set-pending bit - 28 - 1 - - PENDSVSETSelect - - VALUE_0 - Write: no effect; read: PendSV exception is not pending - 0 - - - VALUE_1 - Write: changes PendSV exception state to pending; read: PendSV exception is pending - 1 - - - - - NMIPENDSET - NMI set-pending bit - 31 - 1 - - NMIPENDSETSelect - - VALUE_0 - Write: no effect; read: NMI exception is not pending - 0 - - - VALUE_1 - Write: changes NMI exception state to pending; read: NMI exception is pending - 1 - - - - - - - VTOR - Vector Table Offset Register - 0xD08 - 32 - 0x00000000 - - - TBLOFF - Vector table base offset - 7 - 25 - - - - - AIRCR - Application Interrupt and Reset Control Register - 0xD0C - 32 - 0x00000000 - - - VECTCLRACTIVE - Debug: Clear state information - 1 - 1 - - - SYSRESETREQ - System Reset Request - 2 - 1 - - SYSRESETREQSelect - - VALUE_0 - No system reset request - 0 - - - VALUE_1 - Asserts a signal to the outer system that requests a reset - 1 - - - - - ENDIANNESS - Data Endianness, 0=little, 1=big - 15 - 1 - - ENDIANNESSSelect - - VALUE_0 - Little-endian - 0 - - - VALUE_1 - Big-endian - 1 - - - - - VECTKEY - Register key (0x05FA) - 16 - 16 - - - - - SCR - System Control Register - 0xD10 - 32 - 0x00000000 - - - SLEEPONEXIT - Sleep-On-Exit when exiting Handler mode - 1 - 1 - - SLEEPONEXITSelect - - VALUE_0 - O not sleep when returning to Thread mode - 0 - - - VALUE_1 - Enter sleep, or deep sleep, on return from an ISR - 1 - - - - - SLEEPDEEP - Uses Deep Sleep as low power mode - 2 - 1 - - SLEEPDEEPSelect - - VALUE_0 - Sleep - 0 - - - VALUE_1 - Deep sleep - 1 - - - - - SEVONPEND - Send Event on Pending bit - 4 - 1 - - SEVONPENDSelect - - VALUE_0 - Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded - 0 - - - VALUE_1 - Enabled events and all interrupts, including disabled interrupts, can wakeup the processor - 1 - - - - - - - CCR - Configuration and Control Register - 0xD14 - 32 - read-only - 0x00000204 - - - UNALIGN_TRP - Unaligned accesses generates a Hard Fault - 3 - 1 - - UNALIGN_TRPSelect - - VALUE_0 - Do not trap unaligned halfword and word accesses - 0 - - - VALUE_1 - Trap unaligned halfword and word accesses - 1 - - - - - STKALIGN - Stack 8-byte aligned on exception entry - 9 - 1 - - STKALIGNSelect - - VALUE_0 - 4-byte aligned - 0 - - - VALUE_1 - 8-byte aligned - 1 - - - - - - - SHPR2 - System Handler Priority Register 2 - 0xD1C - 32 - 0x00000000 - - - PRI_11 - Priority of system handler 11, SVCall - 24 - 8 - - - - - SHPR3 - System Handler Priority Register 3 - 0xD20 - 32 - 0x00000000 - - - PRI_14 - Priority of system handler 14, PendSV - 16 - 8 - - - PRI_15 - Priority of system handler 15, SysTick exception - 24 - 8 - - - - - SHCSR - System Handler Control and State Register - 0xD24 - 32 - 0x00000000 - - - SVCALLPENDED - 15 - 1 - - - - - DFSR - Debug Fault Status Register - 0xD30 - 32 - 0x00000000 - - - HALTED - Halt request debug event active - 0 - 1 - - - BKPT - Breakpoint debug event - 1 - 1 - - - DWTTRAP - DWT debug event - 2 - 1 - - - VCATCH - Vector catch debug event - 3 - 1 - - - EXTERNAL - EDBGRQ debug event - 4 - 1 - - - - - - - diff --git a/svd/ATSAMC21J18AU.svd b/svd/ATSAMC21J18AU.svd deleted file mode 100644 index dd38920c0010..000000000000 --- a/svd/ATSAMC21J18AU.svd +++ /dev/null @@ -1,27996 +0,0 @@ - - - - Microchip Technology - MCHP - ATSAMC21J18AU - SAMC21 - 0 - Microchip ATSAMC21J18AU Microcontroller - - CM0+ - r0p0 - selectable - true - false - 2 - false - - 8 - 32 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - AC - U22451.1.1 - Analog Comparators - AC - AC_ - 0x42005000 - - 0 - 0x24 - registers - - - AC - 27 - - - - CTRLA - Control A - 0x0 - 8 - 0x00 - - - SWRST - Software Reset - 0 - 1 - - - ENABLE - Enable - 1 - 1 - - - - - CTRLB - Control B - 0x1 - 8 - write-only - 0x00 - - - START0 - Comparator 0 Start Comparison - 0 - 1 - - - START1 - Comparator 1 Start Comparison - 1 - 1 - - - START2 - Comparator 2 Start Comparison - 2 - 1 - - - START3 - Comparator 3 Start Comparison - 3 - 1 - - - - - EVCTRL - Event Control - 0x2 - 16 - 0x0000 - - - COMPEO0 - Comparator 0 Event Output Enable - 0 - 1 - - - COMPEO1 - Comparator 1 Event Output Enable - 1 - 1 - - - COMPEO2 - Comparator 2 Event Output Enable - 2 - 1 - - - COMPEO3 - Comparator 3 Event Output Enable - 3 - 1 - - - WINEO0 - Window 0 Event Output Enable - 4 - 1 - - - WINEO1 - Window 1 Event Output Enable - 5 - 1 - - - COMPEI0 - Comparator 0 Event Input Enable - 8 - 1 - - - COMPEI1 - Comparator 1 Event Input Enable - 9 - 1 - - - COMPEI2 - Comparator 2 Event Input Enable - 10 - 1 - - - COMPEI3 - Comparator 3 Event Input Enable - 11 - 1 - - - INVEI0 - Comparator 0 Input Event Invert Enable - 12 - 1 - - - INVEI1 - Comparator 1 Input Event Invert Enable - 13 - 1 - - - INVEI2 - Comparator 2 Input Event Invert Enable - 14 - 1 - - - INVEI3 - Comparator 3 Input Event Invert Enable - 15 - 1 - - - - - INTENCLR - Interrupt Enable Clear - 0x4 - 8 - 0x00 - - - COMP0 - Comparator 0 Interrupt Enable - 0 - 1 - - - COMP1 - Comparator 1 Interrupt Enable - 1 - 1 - - - COMP2 - Comparator 2 Interrupt Enable - 2 - 1 - - - COMP3 - Comparator 3 Interrupt Enable - 3 - 1 - - - WIN0 - Window 0 Interrupt Enable - 4 - 1 - - - WIN1 - Window 1 Interrupt Enable - 5 - 1 - - - - - INTENSET - Interrupt Enable Set - 0x5 - 8 - 0x00 - - - COMP0 - Comparator 0 Interrupt Enable - 0 - 1 - - - COMP1 - Comparator 1 Interrupt Enable - 1 - 1 - - - COMP2 - Comparator 2 Interrupt Enable - 2 - 1 - - - COMP3 - Comparator 3 Interrupt Enable - 3 - 1 - - - WIN0 - Window 0 Interrupt Enable - 4 - 1 - - - WIN1 - Window 1 Interrupt Enable - 5 - 1 - - - - - INTFLAG - Interrupt Flag Status and Clear - 0x6 - 8 - 0x00 - - - COMP0 - Comparator 0 - 0 - 1 - - - COMP1 - Comparator 1 - 1 - 1 - - - COMP2 - Comparator 2 - 2 - 1 - - - COMP3 - Comparator 3 - 3 - 1 - - - WIN0 - Window 0 - 4 - 1 - - - WIN1 - Window 1 - 5 - 1 - - - - - STATUSA - Status A - 0x7 - 8 - read-only - 0x00 - - - STATE0 - Comparator 0 Current State - 0 - 1 - - - STATE1 - Comparator 1 Current State - 1 - 1 - - - STATE2 - Comparator 2 Current State - 2 - 1 - - - STATE3 - Comparator 3 Current State - 3 - 1 - - - WSTATE0 - Window 0 Current State - 4 - 2 - - WSTATE0Select - - ABOVE - Signal is above window - 0 - - - INSIDE - Signal is inside window - 1 - - - BELOW - Signal is below window - 2 - - - - - WSTATE1 - Window 1 Current State - 6 - 2 - - WSTATE1Select - - ABOVE - Signal is above window - 0 - - - INSIDE - Signal is inside window - 1 - - - BELOW - Signal is below window - 2 - - - - - - - STATUSB - Status B - 0x8 - 8 - read-only - 0x00 - - - READY0 - Comparator 0 Ready - 0 - 1 - - - READY1 - Comparator 1 Ready - 1 - 1 - - - READY2 - Comparator 2 Ready - 2 - 1 - - - READY3 - Comparator 3 Ready - 3 - 1 - - - - - DBGCTRL - Debug Control - 0x9 - 8 - 0x00 - - - DBGRUN - Debug Run - 0 - 1 - - - - - WINCTRL - Window Control - 0xA - 8 - 0x00 - - - WEN0 - Window 0 Mode Enable - 0 - 1 - - - WINTSEL0 - Window 0 Interrupt Selection - 1 - 2 - - WINTSEL0Select - - ABOVE - Interrupt on signal above window - 0 - - - INSIDE - Interrupt on signal inside window - 1 - - - BELOW - Interrupt on signal below window - 2 - - - OUTSIDE - Interrupt on signal outside window - 3 - - - - - WEN1 - Window 1 Mode Enable - 4 - 1 - - - WINTSEL1 - Window 1 Interrupt Selection - 5 - 2 - - WINTSEL1Select - - ABOVE - Interrupt on signal above window - 0 - - - INSIDE - Interrupt on signal inside window - 1 - - - BELOW - Interrupt on signal below window - 2 - - - OUTSIDE - Interrupt on signal outside window - 3 - - - - - - - 4 - 1 - SCALER[%s] - Scaler n - 0xC - 8 - 0x00 - - - VALUE - Scaler Value - 0 - 6 - - - - - 4 - 4 - COMPCTRL[%s] - Comparator Control n - 0x10 - 32 - 0x00000000 - - - ENABLE - Enable - 1 - 1 - - - SINGLE - Single-Shot Mode - 2 - 1 - - - INTSEL - Interrupt Selection - 3 - 2 - - INTSELSelect - - TOGGLE - Interrupt on comparator output toggle - 0 - - - RISING - Interrupt on comparator output rising - 1 - - - FALLING - Interrupt on comparator output falling - 2 - - - EOC - Interrupt on end of comparison (single-shot mode only) - 3 - - - - - RUNSTDBY - Run in Standby - 6 - 1 - - - MUXNEG - Negative Input Mux Selection - 8 - 3 - - MUXNEGSelect - - PIN0 - I/O pin 0 - 0 - - - PIN1 - I/O pin 1 - 1 - - - PIN2 - I/O pin 2 - 2 - - - PIN3 - I/O pin 3 - 3 - - - GND - Ground - 4 - - - VSCALE - VDD scaler - 5 - - - BANDGAP - Internal bandgap voltage - 6 - - - DAC - DAC output - 7 - - - - - MUXPOS - Positive Input Mux Selection - 12 - 3 - - MUXPOSSelect - - PIN0 - I/O pin 0 - 0 - - - PIN1 - I/O pin 1 - 1 - - - PIN2 - I/O pin 2 - 2 - - - PIN3 - I/O pin 3 - 3 - - - VSCALE - VDD Scaler - 4 - - - - - SWAP - Swap Inputs and Invert - 15 - 1 - - - SPEED - Speed Selection - 16 - 2 - - SPEEDSelect - - LOW - Low speed - 0 - - - HIGH - High speed - 3 - - - - - HYSTEN - Hysteresis Enable - 19 - 1 - - - FLEN - Filter Length - 24 - 3 - - FLENSelect - - OFF - No filtering - 0 - - - MAJ3 - 3-bit majority function (2 of 3) - 1 - - - MAJ5 - 5-bit majority function (3 of 5) - 2 - - - - - OUT - Output - 28 - 2 - - OUTSelect - - OFF - The output of COMPn is not routed to the COMPn I/O port - 0 - - - ASYNC - The asynchronous output of COMPn is routed to the COMPn I/O port - 1 - - - SYNC - The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port - 2 - - - - - - - SYNCBUSY - Synchronization Busy - 0x20 - 32 - read-only - 0x00000000 - - - SWRST - Software Reset Synchronization Busy - 0 - 1 - - - ENABLE - Enable Synchronization Busy - 1 - 1 - - - WINCTRL - WINCTRL Synchronization Busy - 2 - 1 - - - COMPCTRL0 - COMPCTRL 0 Synchronization Busy - 3 - 1 - - - COMPCTRL1 - COMPCTRL 1 Synchronization Busy - 4 - 1 - - - COMPCTRL2 - COMPCTRL 2 Synchronization Busy - 5 - 1 - - - COMPCTRL3 - COMPCTRL 3 Synchronization Busy - 6 - 1 - - - - - - - ADC0 - U22472.2.0 - Analog Digital Converter - ADC - ADC_ - 0x42004400 - - 0 - 0x2E - registers - - - ADC0 - 25 - - - - CTRLA - Control A - 0x0 - 8 - 0x00 - - - SWRST - Software Reset - 0 - 1 - - - ENABLE - Enable - 1 - 1 - - - SLAVEEN - Slave Enable - 5 - 1 - - - RUNSTDBY - Run During Standby - 6 - 1 - - - ONDEMAND - On Demand Control - 7 - 1 - - - - - CTRLB - Control B - 0x1 - 8 - 0x00 - - - PRESCALER - Prescaler Configuration - 0 - 3 - - PRESCALERSelect - - DIV2 - Peripheral clock / 2 - 0x0 - - - DIV4 - Peripheral clock / 4 - 0x1 - - - DIV8 - Peripheral clock / 8 - 0x2 - - - DIV16 - Peripheral clock / 16 - 0x3 - - - DIV32 - Peripheral clock / 32 - 0x4 - - - DIV64 - Peripheral clock / 64 - 0x5 - - - DIV128 - Peripheral clock / 128 - 0x6 - - - DIV256 - Peripheral clock / 256 - 0x7 - - - - - - - REFCTRL - Reference Control - 0x2 - 8 - 0x00 - - - REFSEL - Reference Selection - 0 - 4 - - REFSELSelect - - INTREF - Internal Bandgap Reference - 0x0 - - - INTVCC0 - 1/1.6 VDDANA - 0x1 - - - INTVCC1 - 1/2 VDDANA - 0x2 - - - AREFA - External Reference - 0x3 - - - DAC - DAC - 0x4 - - - INTVCC2 - VDDANA - 0x5 - - - - - REFCOMP - Reference Buffer Offset Compensation Enable - 7 - 1 - - - - - EVCTRL - Event Control - 0x3 - 8 - 0x00 - - - FLUSHEI - Flush Event Input Enable - 0 - 1 - - - STARTEI - Start Conversion Event Input Enable - 1 - 1 - - - FLUSHINV - Flush Event Invert Enable - 2 - 1 - - - STARTINV - Start Event Invert Enable - 3 - 1 - - - RESRDYEO - Result Ready Event Out - 4 - 1 - - - WINMONEO - Window Monitor Event Out - 5 - 1 - - - - - INTENCLR - Interrupt Enable Clear - 0x4 - 8 - 0x00 - - - RESRDY - Result Ready Interrupt Disable - 0 - 1 - - - OVERRUN - Overrun Interrupt Disable - 1 - 1 - - - WINMON - Window Monitor Interrupt Disable - 2 - 1 - - - - - INTENSET - Interrupt Enable Set - 0x5 - 8 - 0x00 - - - RESRDY - Result Ready Interrupt Enable - 0 - 1 - - - OVERRUN - Overrun Interrupt Enable - 1 - 1 - - - WINMON - Window Monitor Interrupt Enable - 2 - 1 - - - - - INTFLAG - Interrupt Flag Status and Clear - 0x6 - 8 - 0x00 - - - RESRDY - Result Ready Interrupt Flag - 0 - 1 - - - OVERRUN - Overrun Interrupt Flag - 1 - 1 - - - WINMON - Window Monitor Interrupt Flag - 2 - 1 - - - - - SEQSTATUS - Sequence Status - 0x7 - 8 - read-only - 0x00 - - - SEQSTATE - Sequence State - 0 - 5 - - - SEQBUSY - Sequence Busy - 7 - 1 - - - - - INPUTCTRL - Input Control - 0x8 - 16 - 0x0000 - - - MUXPOS - Positive Mux Input Selection - 0 - 5 - - MUXPOSSelect - - AIN0 - ADC AIN0 Pin - 0x0 - - - AIN1 - ADC AIN1 Pin - 0x1 - - - AIN2 - ADC AIN2 Pin - 0x2 - - - AIN3 - ADC AIN3 Pin - 0x3 - - - AIN4 - ADC AIN4 Pin - 0x4 - - - AIN5 - ADC AIN5 Pin - 0x5 - - - AIN6 - ADC AIN6 Pin - 0x6 - - - AIN7 - ADC AIN7 Pin - 0x7 - - - AIN8 - ADC AIN8 Pin - 0x8 - - - AIN9 - ADC AIN9 Pin - 0x9 - - - AIN10 - ADC AIN10 Pin - 0xA - - - AIN11 - ADC AIN11 Pin - 0xB - - - BANDGAP - Bandgap Voltage - 0x19 - - - SCALEDCOREVCC - 1/4 Scaled Core Supply - 0x1A - - - SCALEDIOVCC - 1/4 Scaled I/O Supply - 0x1B - - - DAC - DAC Output - 0x1C - - - - - MUXNEG - Negative Mux Input Selection - 8 - 5 - - MUXNEGSelect - - AIN0 - ADC AIN0 Pin - 0x0 - - - AIN1 - ADC AIN1 Pin - 0x1 - - - AIN2 - ADC AIN2 Pin - 0x2 - - - AIN3 - ADC AIN3 Pin - 0x3 - - - AIN4 - ADC AIN4 Pin - 0x4 - - - AIN5 - ADC AIN5 Pin - 0x5 - - - GND - Internal Ground - 0x18 - - - - - - - CTRLC - Control C - 0xA - 16 - 0x0000 - - - DIFFMODE - Differential Mode - 0 - 1 - - - LEFTADJ - Left-Adjusted Result - 1 - 1 - - - FREERUN - Free Running Mode - 2 - 1 - - - CORREN - Digital Correction Logic Enable - 3 - 1 - - - RESSEL - Conversion Result Resolution - 4 - 2 - - RESSELSelect - - 12BIT - 12-bit - 0x0 - - - 16BIT - 16-bit averaging mode - 0x1 - - - 10BIT - 10-bit - 0x2 - - - 8BIT - 8-bit - 0x3 - - - - - R2R - Rail-to-Rail mode enable - 7 - 1 - - - WINMODE - Window Monitor Mode - 8 - 3 - - WINMODESelect - - DISABLE - No window mode (default) - 0 - - - MODE1 - RESULT > WINLT - 1 - - - MODE2 - RESULT < WINUT - 2 - - - MODE3 - WINLT < RESULT < WINUT - 3 - - - MODE4 - !(WINLT < RESULT < WINUT) - 4 - - - - - DUALSEL - Dual Mode Trigger Selection - 12 - 2 - - DUALSELSelect - - BOTH - Start event or software trigger will start a conversion on both ADCs - 0 - - - INTERLEAVE - START event or software trigger will alternately start a conversion on ADC0 and ADC1 - 1 - - - - - - - AVGCTRL - Average Control - 0xC - 8 - 0x00 - - - SAMPLENUM - Number of Samples to be Collected - 0 - 4 - - SAMPLENUMSelect - - 1 - 1 sample - 0x0 - - - 2 - 2 samples - 0x1 - - - 4 - 4 samples - 0x2 - - - 8 - 8 samples - 0x3 - - - 16 - 16 samples - 0x4 - - - 32 - 32 samples - 0x5 - - - 64 - 64 samples - 0x6 - - - 128 - 128 samples - 0x7 - - - 256 - 256 samples - 0x8 - - - 512 - 512 samples - 0x9 - - - 1024 - 1024 samples - 0xA - - - - - ADJRES - Adjusting Result / Division Coefficient - 4 - 3 - - - - - SAMPCTRL - Sample Time Control - 0xD - 8 - 0x00 - - - SAMPLEN - Sampling Time Length - 0 - 6 - - - OFFCOMP - Comparator Offset Compensation Enable - 7 - 1 - - - - - WINLT - Window Monitor Lower Threshold - 0xE - 16 - 0x0000 - - - WINLT - Window Lower Threshold - 0 - 16 - - - - - WINUT - Window Monitor Upper Threshold - 0x10 - 16 - 0x0000 - - - WINUT - Window Upper Threshold - 0 - 16 - - - - - GAINCORR - Gain Correction - 0x12 - 16 - 0x0000 - - - GAINCORR - Gain Correction Value - 0 - 12 - - - - - OFFSETCORR - Offset Correction - 0x14 - 16 - 0x0000 - - - OFFSETCORR - Offset Correction Value - 0 - 12 - - - - - SWTRIG - Software Trigger - 0x18 - 8 - 0x00 - - - FLUSH - ADC Flush - 0 - 1 - - - START - Start ADC Conversion - 1 - 1 - - - - - DBGCTRL - Debug Control - 0x1C - 8 - 0x00 - - - DBGRUN - Debug Run - 0 - 1 - - - - - SYNCBUSY - Synchronization Busy - 0x20 - 16 - read-only - 0x0000 - - - SWRST - SWRST Synchronization Busy - 0 - 1 - - - ENABLE - ENABLE Synchronization Busy - 1 - 1 - - - INPUTCTRL - INPUTCTRL Synchronization Busy - 2 - 1 - - - CTRLC - CTRLC Synchronization Busy - 3 - 1 - - - AVGCTRL - AVGCTRL Synchronization Busy - 4 - 1 - - - SAMPCTRL - SAMPCTRL Synchronization Busy - 5 - 1 - - - WINLT - WINLT Synchronization Busy - 6 - 1 - - - WINUT - WINUT Synchronization Busy - 7 - 1 - - - GAINCORR - GAINCORR Synchronization Busy - 8 - 1 - - - OFFSETCORR - OFFSETCTRL Synchronization Busy - 9 - 1 - - - SWTRIG - SWTRG Synchronization Busy - 10 - 1 - - - - - RESULT - Result - 0x24 - 16 - read-only - 0x0000 - - - RESULT - Result Value - 0 - 16 - - - - - SEQCTRL - Sequence Control - 0x28 - 32 - 0x00000000 - - - SEQEN - Enable Positive Input in the Sequence - 0 - 32 - - - - - CALIB - Calibration - 0x2C - 16 - 0x0000 - - - BIASCOMP - Bias Comparator Scaling - 0 - 3 - - - BIASREFBUF - Bias Reference Buffer Scaling - 8 - 3 - - - - - - - ADC1 - 0x42004800 - - ADC1 - 26 - - - - CAN0 - U20032.0.0 - Control Area Network - CAN - CAN_ - 0x42001C00 - - 0 - 0xFC - registers - - - CAN0 - 15 - - - - CREL - Core Release - 0x0 - 32 - read-only - 0x32100000 - - - SUBSTEP - Sub-step of Core Release - 20 - 4 - - - STEP - Step of Core Release - 24 - 4 - - - REL - Core Release - 28 - 4 - - - - - ENDN - Endian - 0x4 - 32 - read-only - 0x87654321 - - - ETV - Endianness Test Value - 0 - 32 - - - - - MRCFG - Message RAM Configuration - 0x8 - 32 - 0x00000002 - - - QOS - Quality of Service - 0 - 2 - - QOSSelect - - DISABLE - Background (no sensitive operation) - 0 - - - LOW - Sensitive Bandwidth - 1 - - - MEDIUM - Sensitive Latency - 2 - - - HIGH - Critical Latency - 3 - - - - - - - DBTP - Fast Bit Timing and Prescaler - 0xC - 32 - 0x00000A33 - - - DSJW - Data (Re)Synchronization Jump Width - 0 - 4 - - - DTSEG2 - Data time segment after sample point - 4 - 4 - - - DTSEG1 - Data time segment before sample point - 8 - 5 - - - DBRP - Data Baud Rate Prescaler - 16 - 5 - - - TDC - Tranceiver Delay Compensation - 23 - 1 - - - - - TEST - Test - 0x10 - 32 - 0x00000000 - - - LBCK - Loop Back Mode - 4 - 1 - - - TX - Control of Transmit Pin - 5 - 2 - - TXSelect - - CORE - TX controlled by CAN core - 0 - - - SAMPLE - TX monitoring sample point - 1 - - - DOMINANT - Dominant (0) level at pin CAN_TX - 2 - - - RECESSIVE - Recessive (1) level at pin CAN_TX - 3 - - - - - RX - Receive Pin - 7 - 1 - - - - - RWD - RAM Watchdog - 0x14 - 32 - 0x00000000 - - - WDC - Watchdog Configuration - 0 - 8 - - - WDV - Watchdog Value - 8 - 8 - - - - - CCCR - CC Control - 0x18 - 32 - 0x00000001 - - - INIT - Initialization - 0 - 1 - - - CCE - Configuration Change Enable - 1 - 1 - - - ASM - ASM Restricted Operation Mode - 2 - 1 - - - CSA - Clock Stop Acknowledge - 3 - 1 - - - CSR - Clock Stop Request - 4 - 1 - - - MON - Bus Monitoring Mode - 5 - 1 - - - DAR - Disable Automatic Retransmission - 6 - 1 - - - TEST - Test Mode Enable - 7 - 1 - - - FDOE - FD Operation Enable - 8 - 1 - - - BRSE - Bit Rate Switch Enable - 9 - 1 - - - PXHD - Protocol Exception Handling Disable - 12 - 1 - - - EFBI - Edge Filtering during Bus Integration - 13 - 1 - - - TXP - Transmit Pause - 14 - 1 - - - NISO - Non ISO Operation - 15 - 1 - - - - - NBTP - Nominal Bit Timing and Prescaler - 0x1C - 32 - 0x06000A03 - - - NTSEG2 - Nominal Time segment after sample point - 0 - 7 - - - NTSEG1 - Nominal Time segment before sample point - 8 - 8 - - - NBRP - Nominal Baud Rate Prescaler - 16 - 9 - - - NSJW - Nominal (Re)Synchronization Jump Width - 25 - 7 - - - - - TSCC - Timestamp Counter Configuration - 0x20 - 32 - 0x00000000 - - - TSS - Timestamp Select - 0 - 2 - - TSSSelect - - ZERO - Timestamp counter value always 0x0000 - 0 - - - INC - Timestamp counter value incremented by TCP - 1 - - - EXT - External timestamp counter value used - 2 - - - - - TCP - Timestamp Counter Prescaler - 16 - 4 - - - - - TSCV - Timestamp Counter Value - 0x24 - 32 - read-only - 0x00000000 - - - TSC - Timestamp Counter - 0 - 16 - - - - - TOCC - Timeout Counter Configuration - 0x28 - 32 - 0xFFFF0000 - - - ETOC - Enable Timeout Counter - 0 - 1 - - - TOS - Timeout Select - 1 - 2 - - TOSSelect - - CONT - Continuout operation - 0 - - - TXEF - Timeout controlled by TX Event FIFO - 1 - - - RXF0 - Timeout controlled by Rx FIFO 0 - 2 - - - RXF1 - Timeout controlled by Rx FIFO 1 - 3 - - - - - TOP - Timeout Period - 16 - 16 - - - - - TOCV - Timeout Counter Value - 0x2C - 32 - 0x0000FFFF - - - TOC - Timeout Counter - 0 - 16 - - - - - ECR - Error Counter - 0x40 - 32 - read-only - 0x00000000 - - - TEC - Transmit Error Counter - 0 - 8 - - - REC - Receive Error Counter - 8 - 7 - - - RP - Receive Error Passive - 15 - 1 - - - CEL - CAN Error Logging - 16 - 8 - - - - - PSR - Protocol Status - 0x44 - 32 - read-only - 0x00000707 - - - LEC - Last Error Code - 0 - 3 - - LECSelect - - NONE - No Error - 0 - - - STUFF - Stuff Error - 1 - - - FORM - Form Error - 2 - - - ACK - Ack Error - 3 - - - BIT1 - Bit1 Error - 4 - - - BIT0 - Bit0 Error - 5 - - - CRC - CRC Error - 6 - - - NC - No Change - 7 - - - - - ACT - Activity - 3 - 2 - - ACTSelect - - SYNC - Node is synchronizing on CAN communication - 0 - - - IDLE - Node is neither receiver nor transmitter - 1 - - - RX - Node is operating as receiver - 2 - - - TX - Node is operating as transmitter - 3 - - - - - EP - Error Passive - 5 - 1 - - - EW - Warning Status - 6 - 1 - - - BO - Bus_Off Status - 7 - 1 - - - DLEC - Data Phase Last Error Code - 8 - 3 - - DLECSelect - - NONE - No Error - 0 - - - STUFF - Stuff Error - 1 - - - FORM - Form Error - 2 - - - ACK - Ack Error - 3 - - - BIT1 - Bit1 Error - 4 - - - BIT0 - Bit0 Error - 5 - - - CRC - CRC Error - 6 - - - NC - No Change - 7 - - - - - RESI - ESI flag of last received CAN FD Message - 11 - 1 - - - RBRS - BRS flag of last received CAN FD Message - 12 - 1 - - - RFDF - Received a CAN FD Message - 13 - 1 - - - PXE - Protocol Exception Event - 14 - 1 - - - TDCV - Transmitter Delay Compensation Value - 16 - 7 - - - - - TDCR - Extended ID Filter Configuration - 0x48 - 32 - 0x00000000 - - - TDCF - Transmitter Delay Compensation Filter Length - 0 - 7 - - - TDCO - Transmitter Delay Compensation Offset - 8 - 7 - - - - - IR - Interrupt - 0x50 - 32 - 0x00000000 - - - RF0N - Rx FIFO 0 New Message - 0 - 1 - - - RF0W - Rx FIFO 0 Watermark Reached - 1 - 1 - - - RF0F - Rx FIFO 0 Full - 2 - 1 - - - RF0L - Rx FIFO 0 Message Lost - 3 - 1 - - - RF1N - Rx FIFO 1 New Message - 4 - 1 - - - RF1W - Rx FIFO 1 Watermark Reached - 5 - 1 - - - RF1F - Rx FIFO 1 FIFO Full - 6 - 1 - - - RF1L - Rx FIFO 1 Message Lost - 7 - 1 - - - HPM - High Priority Message - 8 - 1 - - - TC - Timestamp Completed - 9 - 1 - - - TCF - Transmission Cancellation Finished - 10 - 1 - - - TFE - Tx FIFO Empty - 11 - 1 - - - TEFN - Tx Event FIFO New Entry - 12 - 1 - - - TEFW - Tx Event FIFO Watermark Reached - 13 - 1 - - - TEFF - Tx Event FIFO Full - 14 - 1 - - - TEFL - Tx Event FIFO Element Lost - 15 - 1 - - - TSW - Timestamp Wraparound - 16 - 1 - - - MRAF - Message RAM Access Failure - 17 - 1 - - - TOO - Timeout Occurred - 18 - 1 - - - DRX - Message stored to Dedicated Rx Buffer - 19 - 1 - - - BEC - Bit Error Corrected - 20 - 1 - - - BEU - Bit Error Uncorrected - 21 - 1 - - - ELO - Error Logging Overflow - 22 - 1 - - - EP - Error Passive - 23 - 1 - - - EW - Warning Status - 24 - 1 - - - BO - Bus_Off Status - 25 - 1 - - - WDI - Watchdog Interrupt - 26 - 1 - - - PEA - Protocol Error in Arbitration Phase - 27 - 1 - - - PED - Protocol Error in Data Phase - 28 - 1 - - - ARA - Access to Reserved Address - 29 - 1 - - - - - IE - Interrupt Enable - 0x54 - 32 - 0x00000000 - - - RF0NE - Rx FIFO 0 New Message Interrupt Enable - 0 - 1 - - - RF0WE - Rx FIFO 0 Watermark Reached Interrupt Enable - 1 - 1 - - - RF0FE - Rx FIFO 0 Full Interrupt Enable - 2 - 1 - - - RF0LE - Rx FIFO 0 Message Lost Interrupt Enable - 3 - 1 - - - RF1NE - Rx FIFO 1 New Message Interrupt Enable - 4 - 1 - - - RF1WE - Rx FIFO 1 Watermark Reached Interrupt Enable - 5 - 1 - - - RF1FE - Rx FIFO 1 FIFO Full Interrupt Enable - 6 - 1 - - - RF1LE - Rx FIFO 1 Message Lost Interrupt Enable - 7 - 1 - - - HPME - High Priority Message Interrupt Enable - 8 - 1 - - - TCE - Timestamp Completed Interrupt Enable - 9 - 1 - - - TCFE - Transmission Cancellation Finished Interrupt Enable - 10 - 1 - - - TFEE - Tx FIFO Empty Interrupt Enable - 11 - 1 - - - TEFNE - Tx Event FIFO New Entry Interrupt Enable - 12 - 1 - - - TEFWE - Tx Event FIFO Watermark Reached Interrupt Enable - 13 - 1 - - - TEFFE - Tx Event FIFO Full Interrupt Enable - 14 - 1 - - - TEFLE - Tx Event FIFO Element Lost Interrupt Enable - 15 - 1 - - - TSWE - Timestamp Wraparound Interrupt Enable - 16 - 1 - - - MRAFE - Message RAM Access Failure Interrupt Enable - 17 - 1 - - - TOOE - Timeout Occurred Interrupt Enable - 18 - 1 - - - DRXE - Message stored to Dedicated Rx Buffer Interrupt Enable - 19 - 1 - - - BECE - Bit Error Corrected Interrupt Enable - 20 - 1 - - - BEUE - Bit Error Uncorrected Interrupt Enable - 21 - 1 - - - ELOE - Error Logging Overflow Interrupt Enable - 22 - 1 - - - EPE - Error Passive Interrupt Enable - 23 - 1 - - - EWE - Warning Status Interrupt Enable - 24 - 1 - - - BOE - Bus_Off Status Interrupt Enable - 25 - 1 - - - WDIE - Watchdog Interrupt Interrupt Enable - 26 - 1 - - - PEAE - Protocol Error in Arbitration Phase Enable - 27 - 1 - - - PEDE - Protocol Error in Data Phase Enable - 28 - 1 - - - ARAE - Access to Reserved Address Enable - 29 - 1 - - - - - ILS - Interrupt Line Select - 0x58 - 32 - 0x00000000 - - - RF0NL - Rx FIFO 0 New Message Interrupt Line - 0 - 1 - - - RF0WL - Rx FIFO 0 Watermark Reached Interrupt Line - 1 - 1 - - - RF0FL - Rx FIFO 0 Full Interrupt Line - 2 - 1 - - - RF0LL - Rx FIFO 0 Message Lost Interrupt Line - 3 - 1 - - - RF1NL - Rx FIFO 1 New Message Interrupt Line - 4 - 1 - - - RF1WL - Rx FIFO 1 Watermark Reached Interrupt Line - 5 - 1 - - - RF1FL - Rx FIFO 1 FIFO Full Interrupt Line - 6 - 1 - - - RF1LL - Rx FIFO 1 Message Lost Interrupt Line - 7 - 1 - - - HPML - High Priority Message Interrupt Line - 8 - 1 - - - TCL - Timestamp Completed Interrupt Line - 9 - 1 - - - TCFL - Transmission Cancellation Finished Interrupt Line - 10 - 1 - - - TFEL - Tx FIFO Empty Interrupt Line - 11 - 1 - - - TEFNL - Tx Event FIFO New Entry Interrupt Line - 12 - 1 - - - TEFWL - Tx Event FIFO Watermark Reached Interrupt Line - 13 - 1 - - - TEFFL - Tx Event FIFO Full Interrupt Line - 14 - 1 - - - TEFLL - Tx Event FIFO Element Lost Interrupt Line - 15 - 1 - - - TSWL - Timestamp Wraparound Interrupt Line - 16 - 1 - - - MRAFL - Message RAM Access Failure Interrupt Line - 17 - 1 - - - TOOL - Timeout Occurred Interrupt Line - 18 - 1 - - - DRXL - Message stored to Dedicated Rx Buffer Interrupt Line - 19 - 1 - - - BECL - Bit Error Corrected Interrupt Line - 20 - 1 - - - BEUL - Bit Error Uncorrected Interrupt Line - 21 - 1 - - - ELOL - Error Logging Overflow Interrupt Line - 22 - 1 - - - EPL - Error Passive Interrupt Line - 23 - 1 - - - EWL - Warning Status Interrupt Line - 24 - 1 - - - BOL - Bus_Off Status Interrupt Line - 25 - 1 - - - WDIL - Watchdog Interrupt Interrupt Line - 26 - 1 - - - PEAL - Protocol Error in Arbitration Phase Line - 27 - 1 - - - PEDL - Protocol Error in Data Phase Line - 28 - 1 - - - ARAL - Access to Reserved Address Line - 29 - 1 - - - - - ILE - Interrupt Line Enable - 0x5C - 32 - 0x00000000 - - - EINT0 - Enable Interrupt Line 0 - 0 - 1 - - - EINT1 - Enable Interrupt Line 1 - 1 - 1 - - - - - GFC - Global Filter Configuration - 0x80 - 32 - 0x00000000 - - - RRFE - Reject Remote Frames Extended - 0 - 1 - - - RRFS - Reject Remote Frames Standard - 1 - 1 - - - ANFE - Accept Non-matching Frames Extended - 2 - 2 - - ANFESelect - - RXF0 - Accept in Rx FIFO 0 - 0 - - - RXF1 - Accept in Rx FIFO 1 - 1 - - - REJECT - Reject - 2 - - - - - ANFS - Accept Non-matching Frames Standard - 4 - 2 - - ANFSSelect - - RXF0 - Accept in Rx FIFO 0 - 0 - - - RXF1 - Accept in Rx FIFO 1 - 1 - - - REJECT - Reject - 2 - - - - - - - SIDFC - Standard ID Filter Configuration - 0x84 - 32 - 0x00000000 - - - FLSSA - Filter List Standard Start Address - 0 - 16 - - - LSS - List Size Standard - 16 - 8 - - - - - XIDFC - Extended ID Filter Configuration - 0x88 - 32 - 0x00000000 - - - FLESA - Filter List Extended Start Address - 0 - 16 - - - LSE - List Size Extended - 16 - 7 - - - - - XIDAM - Extended ID AND Mask - 0x90 - 32 - 0x1FFFFFFF - - - EIDM - Extended ID Mask - 0 - 29 - - - - - HPMS - High Priority Message Status - 0x94 - 32 - read-only - 0x00000000 - - - BIDX - Buffer Index - 0 - 6 - - - MSI - Message Storage Indicator - 6 - 2 - - MSISelect - - NONE - No FIFO selected - 0 - - - LOST - FIFO message lost - 1 - - - FIFO0 - Message stored in FIFO 0 - 2 - - - FIFO1 - Message stored in FIFO 1 - 3 - - - - - FIDX - Filter Index - 8 - 7 - - - FLST - Filter List - 15 - 1 - - - - - NDAT1 - New Data 1 - 0x98 - 32 - 0x00000000 - - - ND0 - New Data 0 - 0 - 1 - - - ND1 - New Data 1 - 1 - 1 - - - ND2 - New Data 2 - 2 - 1 - - - ND3 - New Data 3 - 3 - 1 - - - ND4 - New Data 4 - 4 - 1 - - - ND5 - New Data 5 - 5 - 1 - - - ND6 - New Data 6 - 6 - 1 - - - ND7 - New Data 7 - 7 - 1 - - - ND8 - New Data 8 - 8 - 1 - - - ND9 - New Data 9 - 9 - 1 - - - ND10 - New Data 10 - 10 - 1 - - - ND11 - New Data 11 - 11 - 1 - - - ND12 - New Data 12 - 12 - 1 - - - ND13 - New Data 13 - 13 - 1 - - - ND14 - New Data 14 - 14 - 1 - - - ND15 - New Data 15 - 15 - 1 - - - ND16 - New Data 16 - 16 - 1 - - - ND17 - New Data 17 - 17 - 1 - - - ND18 - New Data 18 - 18 - 1 - - - ND19 - New Data 19 - 19 - 1 - - - ND20 - New Data 20 - 20 - 1 - - - ND21 - New Data 21 - 21 - 1 - - - ND22 - New Data 22 - 22 - 1 - - - ND23 - New Data 23 - 23 - 1 - - - ND24 - New Data 24 - 24 - 1 - - - ND25 - New Data 25 - 25 - 1 - - - ND26 - New Data 26 - 26 - 1 - - - ND27 - New Data 27 - 27 - 1 - - - ND28 - New Data 28 - 28 - 1 - - - ND29 - New Data 29 - 29 - 1 - - - ND30 - New Data 30 - 30 - 1 - - - ND31 - New Data 31 - 31 - 1 - - - - - NDAT2 - New Data 2 - 0x9C - 32 - 0x00000000 - - - ND32 - New Data 32 - 0 - 1 - - - ND33 - New Data 33 - 1 - 1 - - - ND34 - New Data 34 - 2 - 1 - - - ND35 - New Data 35 - 3 - 1 - - - ND36 - New Data 36 - 4 - 1 - - - ND37 - New Data 37 - 5 - 1 - - - ND38 - New Data 38 - 6 - 1 - - - ND39 - New Data 39 - 7 - 1 - - - ND40 - New Data 40 - 8 - 1 - - - ND41 - New Data 41 - 9 - 1 - - - ND42 - New Data 42 - 10 - 1 - - - ND43 - New Data 43 - 11 - 1 - - - ND44 - New Data 44 - 12 - 1 - - - ND45 - New Data 45 - 13 - 1 - - - ND46 - New Data 46 - 14 - 1 - - - ND47 - New Data 47 - 15 - 1 - - - ND48 - New Data 48 - 16 - 1 - - - ND49 - New Data 49 - 17 - 1 - - - ND50 - New Data 50 - 18 - 1 - - - ND51 - New Data 51 - 19 - 1 - - - ND52 - New Data 52 - 20 - 1 - - - ND53 - New Data 53 - 21 - 1 - - - ND54 - New Data 54 - 22 - 1 - - - ND55 - New Data 55 - 23 - 1 - - - ND56 - New Data 56 - 24 - 1 - - - ND57 - New Data 57 - 25 - 1 - - - ND58 - New Data 58 - 26 - 1 - - - ND59 - New Data 59 - 27 - 1 - - - ND60 - New Data 60 - 28 - 1 - - - ND61 - New Data 61 - 29 - 1 - - - ND62 - New Data 62 - 30 - 1 - - - ND63 - New Data 63 - 31 - 1 - - - - - RXF0C - Rx FIFO 0 Configuration - 0xA0 - 32 - 0x00000000 - - - F0SA - Rx FIFO 0 Start Address - 0 - 16 - - - F0S - Rx FIFO 0 Size - 16 - 7 - - - F0WM - Rx FIFO 0 Watermark - 24 - 7 - - - F0OM - FIFO 0 Operation Mode - 31 - 1 - - - - - RXF0S - Rx FIFO 0 Status - 0xA4 - 32 - read-only - 0x00000000 - - - F0FL - Rx FIFO 0 Fill Level - 0 - 7 - - - F0GI - Rx FIFO 0 Get Index - 8 - 6 - - - F0PI - Rx FIFO 0 Put Index - 16 - 6 - - - F0F - Rx FIFO 0 Full - 24 - 1 - - - RF0L - Rx FIFO 0 Message Lost - 25 - 1 - - - - - RXF0A - Rx FIFO 0 Acknowledge - 0xA8 - 32 - 0x00000000 - - - F0AI - Rx FIFO 0 Acknowledge Index - 0 - 6 - - - - - RXBC - Rx Buffer Configuration - 0xAC - 32 - 0x00000000 - - - RBSA - Rx Buffer Start Address - 0 - 16 - - - - - RXF1C - Rx FIFO 1 Configuration - 0xB0 - 32 - 0x00000000 - - - F1SA - Rx FIFO 1 Start Address - 0 - 16 - - - F1S - Rx FIFO 1 Size - 16 - 7 - - - F1WM - Rx FIFO 1 Watermark - 24 - 7 - - - F1OM - FIFO 1 Operation Mode - 31 - 1 - - - - - RXF1S - Rx FIFO 1 Status - 0xB4 - 32 - read-only - 0x00000000 - - - F1FL - Rx FIFO 1 Fill Level - 0 - 7 - - - F1GI - Rx FIFO 1 Get Index - 8 - 6 - - - F1PI - Rx FIFO 1 Put Index - 16 - 6 - - - F1F - Rx FIFO 1 Full - 24 - 1 - - - RF1L - Rx FIFO 1 Message Lost - 25 - 1 - - - DMS - Debug Message Status - 30 - 2 - - DMSSelect - - IDLE - Idle state - 0 - - - DBGA - Debug message A received - 1 - - - DBGB - Debug message A/B received - 2 - - - DBGC - Debug message A/B/C received, DMA request set - 3 - - - - - - - RXF1A - Rx FIFO 1 Acknowledge - 0xB8 - 32 - 0x00000000 - - - F1AI - Rx FIFO 1 Acknowledge Index - 0 - 6 - - - - - RXESC - Rx Buffer / FIFO Element Size Configuration - 0xBC - 32 - 0x00000000 - - - F0DS - Rx FIFO 0 Data Field Size - 0 - 3 - - F0DSSelect - - DATA8 - 8 byte data field - 0 - - - DATA12 - 12 byte data field - 1 - - - DATA16 - 16 byte data field - 2 - - - DATA20 - 20 byte data field - 3 - - - DATA24 - 24 byte data field - 4 - - - DATA32 - 32 byte data field - 5 - - - DATA48 - 48 byte data field - 6 - - - DATA64 - 64 byte data field - 7 - - - - - F1DS - Rx FIFO 1 Data Field Size - 4 - 3 - - F1DSSelect - - DATA8 - 8 byte data field - 0 - - - DATA12 - 12 byte data field - 1 - - - DATA16 - 16 byte data field - 2 - - - DATA20 - 20 byte data field - 3 - - - DATA24 - 24 byte data field - 4 - - - DATA32 - 32 byte data field - 5 - - - DATA48 - 48 byte data field - 6 - - - DATA64 - 64 byte data field - 7 - - - - - RBDS - Rx Buffer Data Field Size - 8 - 3 - - RBDSSelect - - DATA8 - 8 byte data field - 0 - - - DATA12 - 12 byte data field - 1 - - - DATA16 - 16 byte data field - 2 - - - DATA20 - 20 byte data field - 3 - - - DATA24 - 24 byte data field - 4 - - - DATA32 - 32 byte data field - 5 - - - DATA48 - 48 byte data field - 6 - - - DATA64 - 64 byte data field - 7 - - - - - - - TXBC - Tx Buffer Configuration - 0xC0 - 32 - 0x00000000 - - - TBSA - Tx Buffers Start Address - 0 - 16 - - - NDTB - Number of Dedicated Transmit Buffers - 16 - 6 - - - TFQS - Transmit FIFO/Queue Size - 24 - 6 - - - TFQM - Tx FIFO/Queue Mode - 30 - 1 - - - - - TXFQS - Tx FIFO / Queue Status - 0xC4 - 32 - read-only - 0x00000000 - - - TFFL - Tx FIFO Free Level - 0 - 6 - - - TFGI - Tx FIFO Get Index - 8 - 5 - - - TFQPI - Tx FIFO/Queue Put Index - 16 - 5 - - - TFQF - Tx FIFO/Queue Full - 21 - 1 - - - - - TXESC - Tx Buffer Element Size Configuration - 0xC8 - 32 - 0x00000000 - - - TBDS - Tx Buffer Data Field Size - 0 - 3 - - TBDSSelect - - DATA8 - 8 byte data field - 0 - - - DATA12 - 12 byte data field - 1 - - - DATA16 - 16 byte data field - 2 - - - DATA20 - 20 byte data field - 3 - - - DATA24 - 24 byte data field - 4 - - - DATA32 - 32 byte data field - 5 - - - DATA48 - 48 byte data field - 6 - - - DATA64 - 64 byte data field - 7 - - - - - - - TXBRP - Tx Buffer Request Pending - 0xCC - 32 - read-only - 0x00000000 - - - TRP0 - Transmission Request Pending 0 - 0 - 1 - - - TRP1 - Transmission Request Pending 1 - 1 - 1 - - - TRP2 - Transmission Request Pending 2 - 2 - 1 - - - TRP3 - Transmission Request Pending 3 - 3 - 1 - - - TRP4 - Transmission Request Pending 4 - 4 - 1 - - - TRP5 - Transmission Request Pending 5 - 5 - 1 - - - TRP6 - Transmission Request Pending 6 - 6 - 1 - - - TRP7 - Transmission Request Pending 7 - 7 - 1 - - - TRP8 - Transmission Request Pending 8 - 8 - 1 - - - TRP9 - Transmission Request Pending 9 - 9 - 1 - - - TRP10 - Transmission Request Pending 10 - 10 - 1 - - - TRP11 - Transmission Request Pending 11 - 11 - 1 - - - TRP12 - Transmission Request Pending 12 - 12 - 1 - - - TRP13 - Transmission Request Pending 13 - 13 - 1 - - - TRP14 - Transmission Request Pending 14 - 14 - 1 - - - TRP15 - Transmission Request Pending 15 - 15 - 1 - - - TRP16 - Transmission Request Pending 16 - 16 - 1 - - - TRP17 - Transmission Request Pending 17 - 17 - 1 - - - TRP18 - Transmission Request Pending 18 - 18 - 1 - - - TRP19 - Transmission Request Pending 19 - 19 - 1 - - - TRP20 - Transmission Request Pending 20 - 20 - 1 - - - TRP21 - Transmission Request Pending 21 - 21 - 1 - - - TRP22 - Transmission Request Pending 22 - 22 - 1 - - - TRP23 - Transmission Request Pending 23 - 23 - 1 - - - TRP24 - Transmission Request Pending 24 - 24 - 1 - - - TRP25 - Transmission Request Pending 25 - 25 - 1 - - - TRP26 - Transmission Request Pending 26 - 26 - 1 - - - TRP27 - Transmission Request Pending 27 - 27 - 1 - - - TRP28 - Transmission Request Pending 28 - 28 - 1 - - - TRP29 - Transmission Request Pending 29 - 29 - 1 - - - TRP30 - Transmission Request Pending 30 - 30 - 1 - - - TRP31 - Transmission Request Pending 31 - 31 - 1 - - - - - TXBAR - Tx Buffer Add Request - 0xD0 - 32 - 0x00000000 - - - AR0 - Add Request 0 - 0 - 1 - - - AR1 - Add Request 1 - 1 - 1 - - - AR2 - Add Request 2 - 2 - 1 - - - AR3 - Add Request 3 - 3 - 1 - - - AR4 - Add Request 4 - 4 - 1 - - - AR5 - Add Request 5 - 5 - 1 - - - AR6 - Add Request 6 - 6 - 1 - - - AR7 - Add Request 7 - 7 - 1 - - - AR8 - Add Request 8 - 8 - 1 - - - AR9 - Add Request 9 - 9 - 1 - - - AR10 - Add Request 10 - 10 - 1 - - - AR11 - Add Request 11 - 11 - 1 - - - AR12 - Add Request 12 - 12 - 1 - - - AR13 - Add Request 13 - 13 - 1 - - - AR14 - Add Request 14 - 14 - 1 - - - AR15 - Add Request 15 - 15 - 1 - - - AR16 - Add Request 16 - 16 - 1 - - - AR17 - Add Request 17 - 17 - 1 - - - AR18 - Add Request 18 - 18 - 1 - - - AR19 - Add Request 19 - 19 - 1 - - - AR20 - Add Request 20 - 20 - 1 - - - AR21 - Add Request 21 - 21 - 1 - - - AR22 - Add Request 22 - 22 - 1 - - - AR23 - Add Request 23 - 23 - 1 - - - AR24 - Add Request 24 - 24 - 1 - - - AR25 - Add Request 25 - 25 - 1 - - - AR26 - Add Request 26 - 26 - 1 - - - AR27 - Add Request 27 - 27 - 1 - - - AR28 - Add Request 28 - 28 - 1 - - - AR29 - Add Request 29 - 29 - 1 - - - AR30 - Add Request 30 - 30 - 1 - - - AR31 - Add Request 31 - 31 - 1 - - - - - TXBCR - Tx Buffer Cancellation Request - 0xD4 - 32 - 0x00000000 - - - CR0 - Cancellation Request 0 - 0 - 1 - - - CR1 - Cancellation Request 1 - 1 - 1 - - - CR2 - Cancellation Request 2 - 2 - 1 - - - CR3 - Cancellation Request 3 - 3 - 1 - - - CR4 - Cancellation Request 4 - 4 - 1 - - - CR5 - Cancellation Request 5 - 5 - 1 - - - CR6 - Cancellation Request 6 - 6 - 1 - - - CR7 - Cancellation Request 7 - 7 - 1 - - - CR8 - Cancellation Request 8 - 8 - 1 - - - CR9 - Cancellation Request 9 - 9 - 1 - - - CR10 - Cancellation Request 10 - 10 - 1 - - - CR11 - Cancellation Request 11 - 11 - 1 - - - CR12 - Cancellation Request 12 - 12 - 1 - - - CR13 - Cancellation Request 13 - 13 - 1 - - - CR14 - Cancellation Request 14 - 14 - 1 - - - CR15 - Cancellation Request 15 - 15 - 1 - - - CR16 - Cancellation Request 16 - 16 - 1 - - - CR17 - Cancellation Request 17 - 17 - 1 - - - CR18 - Cancellation Request 18 - 18 - 1 - - - CR19 - Cancellation Request 19 - 19 - 1 - - - CR20 - Cancellation Request 20 - 20 - 1 - - - CR21 - Cancellation Request 21 - 21 - 1 - - - CR22 - Cancellation Request 22 - 22 - 1 - - - CR23 - Cancellation Request 23 - 23 - 1 - - - CR24 - Cancellation Request 24 - 24 - 1 - - - CR25 - Cancellation Request 25 - 25 - 1 - - - CR26 - Cancellation Request 26 - 26 - 1 - - - CR27 - Cancellation Request 27 - 27 - 1 - - - CR28 - Cancellation Request 28 - 28 - 1 - - - CR29 - Cancellation Request 29 - 29 - 1 - - - CR30 - Cancellation Request 30 - 30 - 1 - - - CR31 - Cancellation Request 31 - 31 - 1 - - - - - TXBTO - Tx Buffer Transmission Occurred - 0xD8 - 32 - read-only - 0x00000000 - - - TO0 - Transmission Occurred 0 - 0 - 1 - - - TO1 - Transmission Occurred 1 - 1 - 1 - - - TO2 - Transmission Occurred 2 - 2 - 1 - - - TO3 - Transmission Occurred 3 - 3 - 1 - - - TO4 - Transmission Occurred 4 - 4 - 1 - - - TO5 - Transmission Occurred 5 - 5 - 1 - - - TO6 - Transmission Occurred 6 - 6 - 1 - - - TO7 - Transmission Occurred 7 - 7 - 1 - - - TO8 - Transmission Occurred 8 - 8 - 1 - - - TO9 - Transmission Occurred 9 - 9 - 1 - - - TO10 - Transmission Occurred 10 - 10 - 1 - - - TO11 - Transmission Occurred 11 - 11 - 1 - - - TO12 - Transmission Occurred 12 - 12 - 1 - - - TO13 - Transmission Occurred 13 - 13 - 1 - - - TO14 - Transmission Occurred 14 - 14 - 1 - - - TO15 - Transmission Occurred 15 - 15 - 1 - - - TO16 - Transmission Occurred 16 - 16 - 1 - - - TO17 - Transmission Occurred 17 - 17 - 1 - - - TO18 - Transmission Occurred 18 - 18 - 1 - - - TO19 - Transmission Occurred 19 - 19 - 1 - - - TO20 - Transmission Occurred 20 - 20 - 1 - - - TO21 - Transmission Occurred 21 - 21 - 1 - - - TO22 - Transmission Occurred 22 - 22 - 1 - - - TO23 - Transmission Occurred 23 - 23 - 1 - - - TO24 - Transmission Occurred 24 - 24 - 1 - - - TO25 - Transmission Occurred 25 - 25 - 1 - - - TO26 - Transmission Occurred 26 - 26 - 1 - - - TO27 - Transmission Occurred 27 - 27 - 1 - - - TO28 - Transmission Occurred 28 - 28 - 1 - - - TO29 - Transmission Occurred 29 - 29 - 1 - - - TO30 - Transmission Occurred 30 - 30 - 1 - - - TO31 - Transmission Occurred 31 - 31 - 1 - - - - - TXBCF - Tx Buffer Cancellation Finished - 0xDC - 32 - read-only - 0x00000000 - - - CF0 - Tx Buffer Cancellation Finished 0 - 0 - 1 - - - CF1 - Tx Buffer Cancellation Finished 1 - 1 - 1 - - - CF2 - Tx Buffer Cancellation Finished 2 - 2 - 1 - - - CF3 - Tx Buffer Cancellation Finished 3 - 3 - 1 - - - CF4 - Tx Buffer Cancellation Finished 4 - 4 - 1 - - - CF5 - Tx Buffer Cancellation Finished 5 - 5 - 1 - - - CF6 - Tx Buffer Cancellation Finished 6 - 6 - 1 - - - CF7 - Tx Buffer Cancellation Finished 7 - 7 - 1 - - - CF8 - Tx Buffer Cancellation Finished 8 - 8 - 1 - - - CF9 - Tx Buffer Cancellation Finished 9 - 9 - 1 - - - CF10 - Tx Buffer Cancellation Finished 10 - 10 - 1 - - - CF11 - Tx Buffer Cancellation Finished 11 - 11 - 1 - - - CF12 - Tx Buffer Cancellation Finished 12 - 12 - 1 - - - CF13 - Tx Buffer Cancellation Finished 13 - 13 - 1 - - - CF14 - Tx Buffer Cancellation Finished 14 - 14 - 1 - - - CF15 - Tx Buffer Cancellation Finished 15 - 15 - 1 - - - CF16 - Tx Buffer Cancellation Finished 16 - 16 - 1 - - - CF17 - Tx Buffer Cancellation Finished 17 - 17 - 1 - - - CF18 - Tx Buffer Cancellation Finished 18 - 18 - 1 - - - CF19 - Tx Buffer Cancellation Finished 19 - 19 - 1 - - - CF20 - Tx Buffer Cancellation Finished 20 - 20 - 1 - - - CF21 - Tx Buffer Cancellation Finished 21 - 21 - 1 - - - CF22 - Tx Buffer Cancellation Finished 22 - 22 - 1 - - - CF23 - Tx Buffer Cancellation Finished 23 - 23 - 1 - - - CF24 - Tx Buffer Cancellation Finished 24 - 24 - 1 - - - CF25 - Tx Buffer Cancellation Finished 25 - 25 - 1 - - - CF26 - Tx Buffer Cancellation Finished 26 - 26 - 1 - - - CF27 - Tx Buffer Cancellation Finished 27 - 27 - 1 - - - CF28 - Tx Buffer Cancellation Finished 28 - 28 - 1 - - - CF29 - Tx Buffer Cancellation Finished 29 - 29 - 1 - - - CF30 - Tx Buffer Cancellation Finished 30 - 30 - 1 - - - CF31 - Tx Buffer Cancellation Finished 31 - 31 - 1 - - - - - TXBTIE - Tx Buffer Transmission Interrupt Enable - 0xE0 - 32 - 0x00000000 - - - TIE0 - Transmission Interrupt Enable 0 - 0 - 1 - - - TIE1 - Transmission Interrupt Enable 1 - 1 - 1 - - - TIE2 - Transmission Interrupt Enable 2 - 2 - 1 - - - TIE3 - Transmission Interrupt Enable 3 - 3 - 1 - - - TIE4 - Transmission Interrupt Enable 4 - 4 - 1 - - - TIE5 - Transmission Interrupt Enable 5 - 5 - 1 - - - TIE6 - Transmission Interrupt Enable 6 - 6 - 1 - - - TIE7 - Transmission Interrupt Enable 7 - 7 - 1 - - - TIE8 - Transmission Interrupt Enable 8 - 8 - 1 - - - TIE9 - Transmission Interrupt Enable 9 - 9 - 1 - - - TIE10 - Transmission Interrupt Enable 10 - 10 - 1 - - - TIE11 - Transmission Interrupt Enable 11 - 11 - 1 - - - TIE12 - Transmission Interrupt Enable 12 - 12 - 1 - - - TIE13 - Transmission Interrupt Enable 13 - 13 - 1 - - - TIE14 - Transmission Interrupt Enable 14 - 14 - 1 - - - TIE15 - Transmission Interrupt Enable 15 - 15 - 1 - - - TIE16 - Transmission Interrupt Enable 16 - 16 - 1 - - - TIE17 - Transmission Interrupt Enable 17 - 17 - 1 - - - TIE18 - Transmission Interrupt Enable 18 - 18 - 1 - - - TIE19 - Transmission Interrupt Enable 19 - 19 - 1 - - - TIE20 - Transmission Interrupt Enable 20 - 20 - 1 - - - TIE21 - Transmission Interrupt Enable 21 - 21 - 1 - - - TIE22 - Transmission Interrupt Enable 22 - 22 - 1 - - - TIE23 - Transmission Interrupt Enable 23 - 23 - 1 - - - TIE24 - Transmission Interrupt Enable 24 - 24 - 1 - - - TIE25 - Transmission Interrupt Enable 25 - 25 - 1 - - - TIE26 - Transmission Interrupt Enable 26 - 26 - 1 - - - TIE27 - Transmission Interrupt Enable 27 - 27 - 1 - - - TIE28 - Transmission Interrupt Enable 28 - 28 - 1 - - - TIE29 - Transmission Interrupt Enable 29 - 29 - 1 - - - TIE30 - Transmission Interrupt Enable 30 - 30 - 1 - - - TIE31 - Transmission Interrupt Enable 31 - 31 - 1 - - - - - TXBCIE - Tx Buffer Cancellation Finished Interrupt Enable - 0xE4 - 32 - 0x00000000 - - - CFIE0 - Cancellation Finished Interrupt Enable 0 - 0 - 1 - - - CFIE1 - Cancellation Finished Interrupt Enable 1 - 1 - 1 - - - CFIE2 - Cancellation Finished Interrupt Enable 2 - 2 - 1 - - - CFIE3 - Cancellation Finished Interrupt Enable 3 - 3 - 1 - - - CFIE4 - Cancellation Finished Interrupt Enable 4 - 4 - 1 - - - CFIE5 - Cancellation Finished Interrupt Enable 5 - 5 - 1 - - - CFIE6 - Cancellation Finished Interrupt Enable 6 - 6 - 1 - - - CFIE7 - Cancellation Finished Interrupt Enable 7 - 7 - 1 - - - CFIE8 - Cancellation Finished Interrupt Enable 8 - 8 - 1 - - - CFIE9 - Cancellation Finished Interrupt Enable 9 - 9 - 1 - - - CFIE10 - Cancellation Finished Interrupt Enable 10 - 10 - 1 - - - CFIE11 - Cancellation Finished Interrupt Enable 11 - 11 - 1 - - - CFIE12 - Cancellation Finished Interrupt Enable 12 - 12 - 1 - - - CFIE13 - Cancellation Finished Interrupt Enable 13 - 13 - 1 - - - CFIE14 - Cancellation Finished Interrupt Enable 14 - 14 - 1 - - - CFIE15 - Cancellation Finished Interrupt Enable 15 - 15 - 1 - - - CFIE16 - Cancellation Finished Interrupt Enable 16 - 16 - 1 - - - CFIE17 - Cancellation Finished Interrupt Enable 17 - 17 - 1 - - - CFIE18 - Cancellation Finished Interrupt Enable 18 - 18 - 1 - - - CFIE19 - Cancellation Finished Interrupt Enable 19 - 19 - 1 - - - CFIE20 - Cancellation Finished Interrupt Enable 20 - 20 - 1 - - - CFIE21 - Cancellation Finished Interrupt Enable 21 - 21 - 1 - - - CFIE22 - Cancellation Finished Interrupt Enable 22 - 22 - 1 - - - CFIE23 - Cancellation Finished Interrupt Enable 23 - 23 - 1 - - - CFIE24 - Cancellation Finished Interrupt Enable 24 - 24 - 1 - - - CFIE25 - Cancellation Finished Interrupt Enable 25 - 25 - 1 - - - CFIE26 - Cancellation Finished Interrupt Enable 26 - 26 - 1 - - - CFIE27 - Cancellation Finished Interrupt Enable 27 - 27 - 1 - - - CFIE28 - Cancellation Finished Interrupt Enable 28 - 28 - 1 - - - CFIE29 - Cancellation Finished Interrupt Enable 29 - 29 - 1 - - - CFIE30 - Cancellation Finished Interrupt Enable 30 - 30 - 1 - - - CFIE31 - Cancellation Finished Interrupt Enable 31 - 31 - 1 - - - - - TXEFC - Tx Event FIFO Configuration - 0xF0 - 32 - 0x00000000 - - - EFSA - Event FIFO Start Address - 0 - 16 - - - EFS - Event FIFO Size - 16 - 6 - - - EFWM - Event FIFO Watermark - 24 - 6 - - - - - TXEFS - Tx Event FIFO Status - 0xF4 - 32 - read-only - 0x00000000 - - - EFFL - Event FIFO Fill Level - 0 - 6 - - - EFGI - Event FIFO Get Index - 8 - 5 - - - EFPI - Event FIFO Put Index - 16 - 5 - - - EFF - Event FIFO Full - 24 - 1 - - - TEFL - Tx Event FIFO Element Lost - 25 - 1 - - - - - TXEFA - Tx Event FIFO Acknowledge - 0xF8 - 32 - 0x00000000 - - - EFAI - Event FIFO Acknowledge Index - 0 - 5 - - - - - - - CAN1 - 0x42002000 - - CAN1 - 16 - - - - CCL - U22251.0.1 - Configurable Custom Logic - CCL - CCL_ - 0x42005C00 - - 0 - 0x18 - registers - - - - CTRL - Control - 0x0 - 8 - 0x00 - - - SWRST - Software Reset - 0 - 1 - - - ENABLE - Enable - 1 - 1 - - - RUNSTDBY - Run during Standby - 6 - 1 - - - - - 2 - 1 - SEQCTRL[%s] - SEQ Control x - 0x4 - 8 - 0x00 - - - SEQSEL - Sequential Selection - 0 - 4 - - SEQSELSelect - - DISABLE - Sequential logic is disabled - 0 - - - DFF - D flip flop - 1 - - - JK - JK flip flop - 2 - - - LATCH - D latch - 3 - - - RS - RS latch - 4 - - - - - - - 4 - 4 - LUTCTRL[%s] - LUT Control x - 0x8 - 32 - 0x00000000 - - - ENABLE - LUT Enable - 1 - 1 - - - FILTSEL - Filter Selection - 4 - 2 - - FILTSELSelect - - DISABLE - Filter disabled - 0 - - - SYNCH - Synchronizer enabled - 1 - - - FILTER - Filter enabled - 2 - - - - - EDGESEL - Edge Selection - 7 - 1 - - - INSEL0 - Input Selection 0 - 8 - 4 - - INSEL0Select - - MASK - Masked input - 0 - - - FEEDBACK - Feedback input source - 1 - - - LINK - Linked LUT input source - 2 - - - EVENT - Event in put source - 3 - - - IO - I/O pin input source - 4 - - - AC - AC input source - 5 - - - TC - TC input source - 6 - - - ALTTC - Alternate TC input source - 7 - - - TCC - TCC input source - 8 - - - SERCOM - SERCOM inout source - 9 - - - - - INSEL1 - Input Selection 1 - 12 - 4 - - - INSEL2 - Input Selection 2 - 16 - 4 - - - INVEI - Input Event Invert - 20 - 1 - - - LUTEI - Event Input Enable - 21 - 1 - - - LUTEO - Event Output Enable - 22 - 1 - - - TRUTH - Truth Value - 24 - 8 - - - - - - - DAC - U22142.0.1 - Digital Analog Converter - DAC - DAC_ - 0x42005400 - - 0 - 0x15 - registers - - - DAC - 28 - - - - CTRLA - Control A - 0x0 - 8 - 0x00 - - - SWRST - Software Reset - 0 - 1 - - - ENABLE - Enable - 1 - 1 - - - RUNSTDBY - Run in Standby - 6 - 1 - - - - - CTRLB - Control B - 0x1 - 8 - 0x00 - - - EOEN - External Output Enable - 0 - 1 - - - IOEN - Internal Output Enable - 1 - 1 - - - LEFTADJ - Left Adjusted Data - 2 - 1 - - - VPD - Voltage Pump Disable - 3 - 1 - - - DITHER - Dither Enable - 5 - 1 - - - REFSEL - Reference Selection - 6 - 2 - - REFSELSelect - - INT1V - Internal 1.0V reference - 0 - - - AVCC - AVCC - 1 - - - VREFP - External reference - 2 - - - - - - - EVCTRL - Event Control - 0x2 - 8 - 0x00 - - - STARTEI - Start Conversion Event Input - 0 - 1 - - - EMPTYEO - Data Buffer Empty Event Output - 1 - 1 - - - INVEI - Invert Event Input - 2 - 1 - - - - - INTENCLR - Interrupt Enable Clear - 0x4 - 8 - 0x00 - - - UNDERRUN - Underrun Interrupt Enable - 0 - 1 - - - EMPTY - Data Buffer Empty Interrupt Enable - 1 - 1 - - - - - INTENSET - Interrupt Enable Set - 0x5 - 8 - 0x00 - - - UNDERRUN - Underrun Interrupt Enable - 0 - 1 - - - EMPTY - Data Buffer Empty Interrupt Enable - 1 - 1 - - - - - INTFLAG - Interrupt Flag Status and Clear - 0x6 - 8 - 0x00 - - - UNDERRUN - Underrun - 0 - 1 - - - EMPTY - Data Buffer Empty - 1 - 1 - - - - - STATUS - Status - 0x7 - 8 - read-only - 0x00 - - - READY - Ready - 0 - 1 - - - - - DATA - Data - 0x8 - 16 - write-only - 0x0000 - - - DATA - Data value to be converted - 0 - 16 - - - - - DATABUF - Data Buffer - 0xC - 16 - write-only - 0x0000 - - - DATABUF - Data Buffer - 0 - 16 - - - - - SYNCBUSY - Synchronization Busy - 0x10 - 32 - read-only - 0x00000000 - - - SWRST - Software Reset - 0 - 1 - - - ENABLE - Enable - 1 - 1 - - - DATA - Data - 2 - 1 - - - DATABUF - Data Buffer - 3 - 1 - - - - - DBGCTRL - Debug Control - 0x14 - 8 - 0x00 - - - DBGRUN - Debug Run - 0 - 1 - - - - - - - DIVAS - U22581.0.0 - Divide and Square Root Accelerator - DIVAS - DIVAS_ - 0x48000000 - - 0 - 0x1C - registers - - - - CTRLA - Control - 0x0 - 8 - 0x00 - - - SIGNED - Signed - 0 - 1 - - - DLZ - Disable Leading Zero Optimization - 1 - 1 - - - - - STATUS - Status - 0x4 - 8 - 0x00 - - - BUSY - DIVAS Accelerator Busy - 0 - 1 - - - DBZ - Writing a one to this bit clears DBZ to zero - 1 - 1 - - - - - DIVIDEND - Dividend - 0x8 - 32 - 0x00000000 - - - DIVIDEND - DIVIDEND - 0 - 32 - - - - - DIVISOR - Divisor - 0xC - 32 - 0x00000000 - - - DIVISOR - DIVISOR - 0 - 32 - - - - - RESULT - Result - 0x10 - 32 - read-only - 0x00000000 - - - RESULT - RESULT - 0 - 32 - - - - - REM - Remainder - 0x14 - 32 - read-only - 0x00000000 - - - REM - REM - 0 - 32 - - - - - SQRNUM - Square Root Input - 0x18 - 32 - 0x00000000 - - - SQRNUM - Square Root Input - 0 - 32 - - - - - - - DMAC - U22232.2.3 - Direct Memory Access Controller - DMAC - DMAC_ - 0x41006000 - - 0 - 0x50 - registers - - - DMAC - 7 - - - - CTRL - Control - 0x0 - 16 - 0x0000 - - - SWRST - Software Reset - 0 - 1 - - - DMAENABLE - DMA Enable - 1 - 1 - - - CRCENABLE - CRC Enable - 2 - 1 - - - LVLEN0 - Priority Level 0 Enable - 8 - 1 - - - LVLEN1 - Priority Level 1 Enable - 9 - 1 - - - LVLEN2 - Priority Level 2 Enable - 10 - 1 - - - LVLEN3 - Priority Level 3 Enable - 11 - 1 - - - - - CRCCTRL - CRC Control - 0x2 - 16 - 0x0000 - - - CRCBEATSIZE - CRC Beat Size - 0 - 2 - - CRCBEATSIZESelect - - BYTE - 8-bit bus transfer - 0x0 - - - HWORD - 16-bit bus transfer - 0x1 - - - WORD - 32-bit bus transfer - 0x2 - - - - - CRCPOLY - CRC Polynomial Type - 2 - 2 - - CRCPOLYSelect - - CRC16 - CRC-16 (CRC-CCITT) - 0x0 - - - CRC32 - CRC32 (IEEE 802.3) - 0x1 - - - - - CRCSRC - CRC Input Source - 8 - 6 - - CRCSRCSelect - - NOACT - No action - 0x00 - - - IO - I/O interface - 0x01 - - - - - - - CRCDATAIN - CRC Data Input - 0x4 - 32 - 0x00000000 - - - CRCDATAIN - CRC Data Input - 0 - 32 - - - - - CRCCHKSUM - CRC Checksum - 0x8 - 32 - 0x00000000 - - - CRCCHKSUM - CRC Checksum - 0 - 32 - - - - - CRCSTATUS - CRC Status - 0xC - 8 - 0x00 - - - CRCBUSY - CRC Module Busy - 0 - 1 - - - CRCZERO - CRC Zero - 1 - 1 - - - - - DBGCTRL - Debug Control - 0xD - 8 - 0x00 - - - DBGRUN - Debug Run - 0 - 1 - - - - - QOSCTRL - QOS Control - 0xE - 8 - 0x2A - - - WRBQOS - Write-Back Quality of Service - 0 - 2 - - WRBQOSSelect - - DISABLE - Background (no sensitive operation) - 0x0 - - - LOW - Sensitive Bandwidth - 0x1 - - - MEDIUM - Sensitive Latency - 0x2 - - - HIGH - Critical Latency - 0x3 - - - - - FQOS - Fetch Quality of Service - 2 - 2 - - FQOSSelect - - DISABLE - Background (no sensitive operation) - 0x0 - - - LOW - Sensitive Bandwidth - 0x1 - - - MEDIUM - Sensitive Latency - 0x2 - - - HIGH - Critical Latency - 0x3 - - - - - DQOS - Data Transfer Quality of Service - 4 - 2 - - DQOSSelect - - DISABLE - Background (no sensitive operation) - 0x0 - - - LOW - Sensitive Bandwidth - 0x1 - - - MEDIUM - Sensitive Latency - 0x2 - - - HIGH - Critical Latency - 0x3 - - - - - - - SWTRIGCTRL - Software Trigger Control - 0x10 - 32 - 0x00000000 - - - SWTRIG0 - Channel 0 Software Trigger - 0 - 1 - - - SWTRIG1 - Channel 1 Software Trigger - 1 - 1 - - - SWTRIG2 - Channel 2 Software Trigger - 2 - 1 - - - SWTRIG3 - Channel 3 Software Trigger - 3 - 1 - - - SWTRIG4 - Channel 4 Software Trigger - 4 - 1 - - - SWTRIG5 - Channel 5 Software Trigger - 5 - 1 - - - SWTRIG6 - Channel 6 Software Trigger - 6 - 1 - - - SWTRIG7 - Channel 7 Software Trigger - 7 - 1 - - - SWTRIG8 - Channel 8 Software Trigger - 8 - 1 - - - SWTRIG9 - Channel 9 Software Trigger - 9 - 1 - - - SWTRIG10 - Channel 10 Software Trigger - 10 - 1 - - - SWTRIG11 - Channel 11 Software Trigger - 11 - 1 - - - - - PRICTRL0 - Priority Control 0 - 0x14 - 32 - 0x00000000 - - - LVLPRI0 - Level 0 Channel Priority Number - 0 - 4 - - - RRLVLEN0 - Level 0 Round-Robin Scheduling Enable - 7 - 1 - - RRLVLEN0Select - - STATIC_LVL - Static arbitration scheme for channels with level 3 priority - 0x0 - - - ROUND_ROBIN_LVL - Round-robin arbitration scheme for channels with level 3 priority - 0x1 - - - - - LVLPRI1 - Level 1 Channel Priority Number - 8 - 4 - - - RRLVLEN1 - Level 1 Round-Robin Scheduling Enable - 15 - 1 - - - LVLPRI2 - Level 2 Channel Priority Number - 16 - 4 - - - RRLVLEN2 - Level 2 Round-Robin Scheduling Enable - 23 - 1 - - - LVLPRI3 - Level 3 Channel Priority Number - 24 - 4 - - - RRLVLEN3 - Level 3 Round-Robin Scheduling Enable - 31 - 1 - - - - - INTPEND - Interrupt Pending - 0x20 - 16 - 0x0000 - - - ID - Channel ID - 0 - 4 - - - TERR - Transfer Error - 8 - 1 - - - TCMPL - Transfer Complete - 9 - 1 - - - SUSP - Channel Suspend - 10 - 1 - - - FERR - Fetch Error - 13 - 1 - - - BUSY - Busy - 14 - 1 - - - PEND - Pending - 15 - 1 - - - - - INTSTATUS - Interrupt Status - 0x24 - 32 - read-only - 0x00000000 - - - CHINT0 - Channel 0 Pending Interrupt - 0 - 1 - - - CHINT1 - Channel 1 Pending Interrupt - 1 - 1 - - - CHINT2 - Channel 2 Pending Interrupt - 2 - 1 - - - CHINT3 - Channel 3 Pending Interrupt - 3 - 1 - - - CHINT4 - Channel 4 Pending Interrupt - 4 - 1 - - - CHINT5 - Channel 5 Pending Interrupt - 5 - 1 - - - CHINT6 - Channel 6 Pending Interrupt - 6 - 1 - - - CHINT7 - Channel 7 Pending Interrupt - 7 - 1 - - - CHINT8 - Channel 8 Pending Interrupt - 8 - 1 - - - CHINT9 - Channel 9 Pending Interrupt - 9 - 1 - - - CHINT10 - Channel 10 Pending Interrupt - 10 - 1 - - - CHINT11 - Channel 11 Pending Interrupt - 11 - 1 - - - - - BUSYCH - Busy Channels - 0x28 - 32 - read-only - 0x00000000 - - - BUSYCH0 - Busy Channel 0 - 0 - 1 - - - BUSYCH1 - Busy Channel 1 - 1 - 1 - - - BUSYCH2 - Busy Channel 2 - 2 - 1 - - - BUSYCH3 - Busy Channel 3 - 3 - 1 - - - BUSYCH4 - Busy Channel 4 - 4 - 1 - - - BUSYCH5 - Busy Channel 5 - 5 - 1 - - - BUSYCH6 - Busy Channel 6 - 6 - 1 - - - BUSYCH7 - Busy Channel 7 - 7 - 1 - - - BUSYCH8 - Busy Channel 8 - 8 - 1 - - - BUSYCH9 - Busy Channel 9 - 9 - 1 - - - BUSYCH10 - Busy Channel 10 - 10 - 1 - - - BUSYCH11 - Busy Channel 11 - 11 - 1 - - - - - PENDCH - Pending Channels - 0x2C - 32 - read-only - 0x00000000 - - - PENDCH0 - Pending Channel 0 - 0 - 1 - - - PENDCH1 - Pending Channel 1 - 1 - 1 - - - PENDCH2 - Pending Channel 2 - 2 - 1 - - - PENDCH3 - Pending Channel 3 - 3 - 1 - - - PENDCH4 - Pending Channel 4 - 4 - 1 - - - PENDCH5 - Pending Channel 5 - 5 - 1 - - - PENDCH6 - Pending Channel 6 - 6 - 1 - - - PENDCH7 - Pending Channel 7 - 7 - 1 - - - PENDCH8 - Pending Channel 8 - 8 - 1 - - - PENDCH9 - Pending Channel 9 - 9 - 1 - - - PENDCH10 - Pending Channel 10 - 10 - 1 - - - PENDCH11 - Pending Channel 11 - 11 - 1 - - - - - ACTIVE - Active Channel and Levels - 0x30 - 32 - read-only - 0x00000000 - - - LVLEX0 - Level 0 Channel Trigger Request Executing - 0 - 1 - - - LVLEX1 - Level 1 Channel Trigger Request Executing - 1 - 1 - - - LVLEX2 - Level 2 Channel Trigger Request Executing - 2 - 1 - - - LVLEX3 - Level 3 Channel Trigger Request Executing - 3 - 1 - - - ID - Active Channel ID - 8 - 5 - - - ABUSY - Active Channel Busy - 15 - 1 - - - BTCNT - Active Channel Block Transfer Count - 16 - 16 - - - - - BASEADDR - Descriptor Memory Section Base Address - 0x34 - 32 - 0x00000000 - - - BASEADDR - Descriptor Memory Base Address - 0 - 32 - - - - - WRBADDR - Write-Back Memory Section Base Address - 0x38 - 32 - 0x00000000 - - - WRBADDR - Write-Back Memory Base Address - 0 - 32 - - - - - CHID - Channel ID - 0x3F - 8 - 0x00 - - - ID - Channel ID - 0 - 4 - - - - - CHCTRLA - Channel Control A - 0x40 - 8 - 0x00 - - - SWRST - Channel Software Reset - 0 - 1 - - - ENABLE - Channel Enable - 1 - 1 - - - RUNSTDBY - Channel run in standby - 6 - 1 - - - - - CHCTRLB - Channel Control B - 0x44 - 32 - 0x00000000 - - - EVACT - Event Input Action - 0 - 3 - - EVACTSelect - - NOACT - No action - 0x0 - - - TRIG - Transfer and periodic transfer trigger - 0x1 - - - CTRIG - Conditional transfer trigger - 0x2 - - - CBLOCK - Conditional block transfer - 0x3 - - - SUSPEND - Channel suspend operation - 0x4 - - - RESUME - Channel resume operation - 0x5 - - - SSKIP - Skip next block suspend action - 0x6 - - - - - EVIE - Channel Event Input Enable - 3 - 1 - - - EVOE - Channel Event Output Enable - 4 - 1 - - - LVL - Channel Arbitration Level - 5 - 2 - - LVLSelect - - LVL0 - Channel Priority Level 0 - 0x0 - - - LVL1 - Channel Priority Level 1 - 0x1 - - - LVL2 - Channel Priority Level 2 - 0x2 - - - LVL3 - Channel Priority Level 3 - 0x3 - - - - - TRIGSRC - Trigger Source - 8 - 6 - - TRIGSRCSelect - - DISABLE - Only software/event triggers - 0x00 - - - TSENS - TSENS Result Ready Trigger - 0x01 - - - SERCOM0_RX - SERCOM0 RX Trigger - 0x02 - - - SERCOM0_TX - SERCOM0 TX Trigger - 0x03 - - - SERCOM1_RX - SERCOM1 RX Trigger - 0x04 - - - SERCOM1_TX - SERCOM1 TX Trigger - 0x05 - - - SERCOM2_RX - SERCOM2 RX Trigger - 0x06 - - - SERCOM2_TX - SERCOM2 TX Trigger - 0x07 - - - SERCOM3_RX - SERCOM3 RX Trigger - 0x08 - - - SERCOM3_TX - SERCOM3 TX Trigger - 0x09 - - - SERCOM4_RX - SERCOM4 RX Trigger - 0x0A - - - SERCOM4_TX - SERCOM4 TX Trigger - 0x0B - - - SERCOM5_RX - SERCOM5 RX Trigger - 0x0C - - - SERCOM5_TX - SERCOM5 TX Trigger - 0x0D - - - CAN0_DEBUG - CAN0 Debug Trigger Reserved - 0x0E - - - CAN1_DEBUG - CAN1 Debug Trigger Reserved - 0x0F - - - TCC0_OVF - TCC0 Overflow Trigger - 0x10 - - - TCC0_MC0 - TCC0 Match/Compare 0 Trigger - 0x11 - - - TCC0_MC1 - TCC0 Match/Compare 1 Trigger - 0x12 - - - TCC0_MC2 - TCC0 Match/Compare 2 Trigger - 0x13 - - - TCC0_MC3 - TCC0 Match/Compare 3 Trigger - 0x14 - - - TCC1_OVF - TCC1 Overflow Trigger - 0x15 - - - TCC1_MC0 - TCC1 Match/Compare 0 Trigger - 0x16 - - - TCC1_MC1 - TCC1 Match/Compare 1 Trigger - 0x17 - - - TCC2_OVF - TCC2 Overflow Trigger - 0x18 - - - TCC2_MC0 - TCC2 Match/Compare 0 Trigger - 0x19 - - - TCC2_MC1 - TCC2 Match/Compare 1 Trigger - 0x1A - - - TC0_OVF - TC0 Overflow Trigger - 0x1B - - - TC0_MC0 - TC0 Match/Compare 0 Trigger - 0x1C - - - TC0_MC1 - TC0 Match/Compare 1 Trigger - 0x1D - - - TC1_OVF - TC1 Overflow Trigger - 0x1E - - - TC1_MC0 - TC1 Match/Compare 0 Trigger - 0x1F - - - TC1_MC1 - TC1 Match/Compare 1 Trigger - 0x20 - - - TC2_OVF - TC2 Overflow Trigger - 0x21 - - - TC2_MC0 - TC2 Match/Compare 0 Trigger - 0x22 - - - TC2_MC1 - TC2 Match/Compare 1 Trigger - 0x23 - - - TC3_OVF - TC3 Overflow Trigger - 0x24 - - - TC3_MC0 - TC3 Match/Compare 0 Trigger - 0x25 - - - TC3_MC1 - TC3 Match/Compare 1 Trigger - 0x26 - - - TC4_OVF - TC4 Overflow Trigger - 0x27 - - - TC4_MC0 - TC4 Match/Compare 0 Trigger - 0x28 - - - TC4_MC1 - TC4 Match/Compare 1 Trigger - 0x29 - - - ADC0_RESRDY - ADC0 Result Ready Trigger - 0x2A - - - ADC1_RESRDY - ADC1 Result Ready Trigger - 0x2B - - - SDADC_RESRDY - SDADC Result Ready Trigger - 0x2C - - - DAC_EMPTY - DAC Empty Trigger - 0x2D - - - PTC_EOC - PTC End of Conversion Trigger - 0x2E - - - PTC_WCOMP - PTC Window Compare Trigger - 0x2F - - - PTC_SEQ - PTC Sequence Trigger - 0x30 - - - - - TRIGACT - Trigger Action - 22 - 2 - - TRIGACTSelect - - BLOCK - One trigger required for each block transfer - 0x0 - - - BEAT - One trigger required for each beat transfer - 0x2 - - - TRANSACTION - One trigger required for each transaction - 0x3 - - - - - CMD - Software Command - 24 - 2 - - CMDSelect - - NOACT - No action - 0x0 - - - SUSPEND - Channel suspend operation - 0x1 - - - RESUME - Channel resume operation - 0x2 - - - - - - - CHINTENCLR - Channel Interrupt Enable Clear - 0x4C - 8 - 0x00 - - - TERR - Channel Transfer Error Interrupt Enable - 0 - 1 - - - TCMPL - Channel Transfer Complete Interrupt Enable - 1 - 1 - - - SUSP - Channel Suspend Interrupt Enable - 2 - 1 - - - - - CHINTENSET - Channel Interrupt Enable Set - 0x4D - 8 - 0x00 - - - TERR - Channel Transfer Error Interrupt Enable - 0 - 1 - - - TCMPL - Channel Transfer Complete Interrupt Enable - 1 - 1 - - - SUSP - Channel Suspend Interrupt Enable - 2 - 1 - - - - - CHINTFLAG - Channel Interrupt Flag Status and Clear - 0x4E - 8 - 0x00 - - - TERR - Channel Transfer Error - 0 - 1 - - - TCMPL - Channel Transfer Complete - 1 - 1 - - - SUSP - Channel Suspend - 2 - 1 - - - - - CHSTATUS - Channel Status - 0x4F - 8 - read-only - 0x00 - - - PEND - Channel Pending - 0 - 1 - - - BUSY - Channel Busy - 1 - 1 - - - FERR - Channel Fetch Error - 2 - 1 - - - - - - - DSU - U22092.5.0 - Device Service Unit - DSU - DSU_ - 0x41002000 - - 0 - 0x2000 - registers - - - - CTRL - Control - 0x0 - 8 - write-only - 0x00 - - - SWRST - Software Reset - 0 - 1 - - - CRC - 32-bit Cyclic Redundancy Code - 2 - 1 - - - MBIST - Memory built-in self-test - 3 - 1 - - - CE - Chip-Erase - 4 - 1 - - - ARR - Auxiliary Row Read - 6 - 1 - - - SMSA - Start Memory Stream Access - 7 - 1 - - - - - STATUSA - Status A - 0x1 - 8 - 0x00 - - - DONE - Done - 0 - 1 - - - CRSTEXT - CPU Reset Phase Extension - 1 - 1 - - - BERR - Bus Error - 2 - 1 - - - FAIL - Failure - 3 - 1 - - - PERR - Protection Error - 4 - 1 - - - - - STATUSB - Status B - 0x2 - 8 - read-only - 0x00 - - - PROT - Protected - 0 - 1 - - - DBGPRES - Debugger Present - 1 - 1 - - - DCCD0 - Debug Communication Channel 0 Dirty - 2 - 1 - - - DCCD1 - Debug Communication Channel 1 Dirty - 3 - 1 - - - HPE - Hot-Plugging Enable - 4 - 1 - - - - - STATUSC - Status C - 0x3 - 8 - read-only - 0x00 - - - STATE - State - 0 - 3 - - - - - ADDR - Address - 0x4 - 32 - 0x00000000 - - - AMOD - Access Mode - 0 - 2 - - - ADDR - Address - 2 - 30 - - - - - LENGTH - Length - 0x8 - 32 - 0x00000000 - - - LENGTH - Length - 2 - 30 - - - - - DATA - Data - 0xC - 32 - 0x00000000 - - - DATA - Data - 0 - 32 - - - - - 2 - 4 - DCC[%s] - Debug Communication Channel n - 0x10 - 32 - 0x00000000 - - - DATA - Data - 0 - 32 - - - - - DID - Device Identification - 0x18 - 32 - read-only - 0x1101050F - - - DEVSEL - Device Select - 0 - 8 - - - REVISION - Revision Number - 8 - 4 - - - DIE - Die Number - 12 - 4 - - - SERIES - Series - 16 - 6 - - SERIESSelect - - 0 - Cortex-M0+ processor, basic feature set - 0 - - - 1 - Cortex-M0+ processor, CAN - 1 - - - - - FAMILY - Family - 23 - 5 - - FAMILYSelect - - 0 - General purpose microcontroller - 0 - - - 1 - PicoPower - 1 - - - 2 - 5V Industrial - 2 - - - - - PROCESSOR - Processor - 28 - 4 - - PROCESSORSelect - - 0 - Cortex-M0 - 0 - - - 1 - Cortex-M0+ - 1 - - - 2 - Cortex-M3 - 2 - - - 3 - Cortex-M4 - 3 - - - - - - - 2 - 4 - DCFG[%s] - Device Configuration - 0xF0 - 32 - 0x00000000 - - - DCFG - Device Configuration - 0 - 32 - - - - - ENTRY0 - CoreSight ROM Table Entry 0 - 0x1000 - 32 - read-only - 0x9F0FC002 - - - EPRES - Entry Present - 0 - 1 - - - FMT - Format - 1 - 1 - - - ADDOFF - Address Offset - 12 - 20 - - - - - ENTRY1 - CoreSight ROM Table Entry 1 - 0x1004 - 32 - read-only - 0x00005002 - - - END - CoreSight ROM Table End - 0x1008 - 32 - read-only - 0x00000000 - - - END - End Marker - 0 - 32 - - - - - MEMTYPE - CoreSight ROM Table Memory Type - 0x1FCC - 32 - read-only - 0x00000000 - - - SMEMP - System Memory Present - 0 - 1 - - - - - PID4 - Peripheral Identification 4 - 0x1FD0 - 32 - read-only - 0x00000000 - - - JEPCC - JEP-106 Continuation Code - 0 - 4 - - - FKBC - 4KB count - 4 - 4 - - - - - PID5 - Peripheral Identification 5 - 0x1FD4 - 32 - read-only - 0x00000000 - - - PID6 - Peripheral Identification 6 - 0x1FD8 - 32 - read-only - 0x00000000 - - - PID7 - Peripheral Identification 7 - 0x1FDC - 32 - read-only - 0x00000000 - - - PID0 - Peripheral Identification 0 - 0x1FE0 - 32 - read-only - 0x000000D0 - - - PARTNBL - Part Number Low - 0 - 8 - - - - - PID1 - Peripheral Identification 1 - 0x1FE4 - 32 - read-only - 0x000000FC - - - PARTNBH - Part Number High - 0 - 4 - - - JEPIDCL - Low part of the JEP-106 Identity Code - 4 - 4 - - - - - PID2 - Peripheral Identification 2 - 0x1FE8 - 32 - read-only - 0x00000009 - - - JEPIDCH - JEP-106 Identity Code High - 0 - 3 - - - JEPU - JEP-106 Identity Code is used - 3 - 1 - - - REVISION - Revision Number - 4 - 4 - - - - - PID3 - Peripheral Identification 3 - 0x1FEC - 32 - read-only - 0x00000000 - - - CUSMOD - ARM CUSMOD - 0 - 4 - - - REVAND - Revision Number - 4 - 4 - - - - - CID0 - Component Identification 0 - 0x1FF0 - 32 - read-only - 0x0000000D - - - PREAMBLEB0 - Preamble Byte 0 - 0 - 8 - - - - - CID1 - Component Identification 1 - 0x1FF4 - 32 - read-only - 0x00000010 - - - PREAMBLE - Preamble - 0 - 4 - - - CCLASS - Component Class - 4 - 4 - - - - - CID2 - Component Identification 2 - 0x1FF8 - 32 - read-only - 0x00000005 - - - PREAMBLEB2 - Preamble Byte 2 - 0 - 8 - - - - - CID3 - Component Identification 3 - 0x1FFC - 32 - read-only - 0x000000B1 - - - PREAMBLEB3 - Preamble Byte 3 - 0 - 8 - - - - - - - EIC - U22542.0.4 - External Interrupt Controller - EIC - EIC_ - 0x40002800 - - 0 - 0x24 - registers - - - EIC - 3 - - - - CTRLA - Control - 0x0 - 8 - 0x00 - - - SWRST - Software Reset - 0 - 1 - - - ENABLE - Enable - 1 - 1 - - - CKSEL - Clock Selection - 4 - 1 - - CKSELSelect - - CLK_GCLK - Clocked by GCLK - 0 - - - CLK_ULP32K - Clocked by ULP32K - 1 - - - - - - - NMICTRL - NMI Control - 0x1 - 8 - 0x00 - - - NMISENSE - NMI Input Sense Configuration - 0 - 3 - - NMISENSESelect - - NONE - No detection - 0 - - - RISE - Rising-edge detection - 1 - - - FALL - Falling-edge detection - 2 - - - BOTH - Both-edges detection - 3 - - - HIGH - High-level detection - 4 - - - LOW - Low-level detection - 5 - - - - - NMIFILTEN - NMI Filter Enable - 3 - 1 - - - NMIASYNCH - NMI Asynchronous edge Detection Enable - 4 - 1 - - NMIASYNCHSelect - - SYNC - Edge detection is clock synchronously operated - 0 - - - ASYNC - Edge detection is clock asynchronously operated - 1 - - - - - - - NMIFLAG - NMI Interrupt Flag - 0x2 - 16 - 0x0000 - - - NMI - NMI Interrupt Flag - 0 - 1 - - - - - SYNCBUSY - Syncbusy register - 0x4 - 32 - read-only - 0x00000000 - - - SWRST - Software reset synchronisation - 0 - 1 - - - ENABLE - Enable synchronisation - 1 - 1 - - - - - EVCTRL - Event Control - 0x8 - 32 - 0x00000000 - - - EXTINTEO - External Interrupt Event Output Enable - 0 - 16 - - - - - INTENCLR - Interrupt Enable Clear - 0xC - 32 - 0x00000000 - - - EXTINT - External Interrupt Disable - 0 - 16 - - - - - INTENSET - Interrupt Enable Set - 0x10 - 32 - 0x00000000 - - - EXTINT - External Interrupt Enable - 0 - 16 - - - - - INTFLAG - Interrupt Flag Status and Clear - 0x14 - 32 - 0x00000000 - - - EXTINT - External Interrupt Flag - 0 - 16 - - - - - ASYNCH - EIC Asynchronous edge Detection Enable - 0x18 - 32 - 0x00000000 - - - ASYNCH - EIC Asynchronous edge Detection Enable - 0 - 16 - - ASYNCHSelect - - SYNC - Edge detection is clock synchronously operated - 0 - - - ASYNC - Edge detection is clock asynchronously operated - 1 - - - - - - - 2 - 4 - CONFIG[%s] - Configuration n - 0x1C - 32 - 0x00000000 - - - SENSE0 - Input Sense Configuration 0 - 0 - 3 - - SENSE0Select - - NONE - No detection - 0 - - - RISE - Rising edge detection - 1 - - - FALL - Falling edge detection - 2 - - - BOTH - Both edges detection - 3 - - - HIGH - High level detection - 4 - - - LOW - Low level detection - 5 - - - - - FILTEN0 - Filter Enable 0 - 3 - 1 - - - SENSE1 - Input Sense Configuration 1 - 4 - 3 - - SENSE1Select - - NONE - No detection - 0 - - - RISE - Rising edge detection - 1 - - - FALL - Falling edge detection - 2 - - - BOTH - Both edges detection - 3 - - - HIGH - High level detection - 4 - - - LOW - Low level detection - 5 - - - - - FILTEN1 - Filter Enable 1 - 7 - 1 - - - SENSE2 - Input Sense Configuration 2 - 8 - 3 - - SENSE2Select - - NONE - No detection - 0 - - - RISE - Rising edge detection - 1 - - - FALL - Falling edge detection - 2 - - - BOTH - Both edges detection - 3 - - - HIGH - High level detection - 4 - - - LOW - Low level detection - 5 - - - - - FILTEN2 - Filter Enable 2 - 11 - 1 - - - SENSE3 - Input Sense Configuration 3 - 12 - 3 - - SENSE3Select - - NONE - No detection - 0 - - - RISE - Rising edge detection - 1 - - - FALL - Falling edge detection - 2 - - - BOTH - Both edges detection - 3 - - - HIGH - High level detection - 4 - - - LOW - Low level detection - 5 - - - - - FILTEN3 - Filter Enable 3 - 15 - 1 - - - SENSE4 - Input Sense Configuration 4 - 16 - 3 - - SENSE4Select - - NONE - No detection - 0 - - - RISE - Rising edge detection - 1 - - - FALL - Falling edge detection - 2 - - - BOTH - Both edges detection - 3 - - - HIGH - High level detection - 4 - - - LOW - Low level detection - 5 - - - - - FILTEN4 - Filter Enable 4 - 19 - 1 - - - SENSE5 - Input Sense Configuration 5 - 20 - 3 - - SENSE5Select - - NONE - No detection - 0 - - - RISE - Rising edge detection - 1 - - - FALL - Falling edge detection - 2 - - - BOTH - Both edges detection - 3 - - - HIGH - High level detection - 4 - - - LOW - Low level detection - 5 - - - - - FILTEN5 - Filter Enable 5 - 23 - 1 - - - SENSE6 - Input Sense Configuration 6 - 24 - 3 - - SENSE6Select - - NONE - No detection - 0 - - - RISE - Rising edge detection - 1 - - - FALL - Falling edge detection - 2 - - - BOTH - Both edges detection - 3 - - - HIGH - High level detection - 4 - - - LOW - Low level detection - 5 - - - - - FILTEN6 - Filter Enable 6 - 27 - 1 - - - SENSE7 - Input Sense Configuration 7 - 28 - 3 - - SENSE7Select - - NONE - No detection - 0 - - - RISE - Rising edge detection - 1 - - - FALL - Falling edge detection - 2 - - - BOTH - Both edges detection - 3 - - - HIGH - High level detection - 4 - - - LOW - Low level detection - 5 - - - - - FILTEN7 - Filter Enable 7 - 31 - 1 - - - - - - - EVSYS - U22561.0.2 - Event System Interface - EVSYS - EVSYS_ - 0x42000000 - - 0 - 0x19C - registers - - - EVSYS - 8 - - - - CTRLA - Control - 0x0 - 8 - 0x00 - - - SWRST - Software Reset - 0 - 1 - - - - - CHSTATUS - Channel Status - 0xC - 32 - read-only - 0x00000000 - - - USRRDY0 - Channel 0 User Ready - 0 - 1 - - - USRRDY1 - Channel 1 User Ready - 1 - 1 - - - USRRDY2 - Channel 2 User Ready - 2 - 1 - - - USRRDY3 - Channel 3 User Ready - 3 - 1 - - - USRRDY4 - Channel 4 User Ready - 4 - 1 - - - USRRDY5 - Channel 5 User Ready - 5 - 1 - - - USRRDY6 - Channel 6 User Ready - 6 - 1 - - - USRRDY7 - Channel 7 User Ready - 7 - 1 - - - USRRDY8 - Channel 8 User Ready - 8 - 1 - - - USRRDY9 - Channel 9 User Ready - 9 - 1 - - - USRRDY10 - Channel 10 User Ready - 10 - 1 - - - USRRDY11 - Channel 11 User Ready - 11 - 1 - - - CHBUSY0 - Channel 0 Busy - 16 - 1 - - - CHBUSY1 - Channel 1 Busy - 17 - 1 - - - CHBUSY2 - Channel 2 Busy - 18 - 1 - - - CHBUSY3 - Channel 3 Busy - 19 - 1 - - - CHBUSY4 - Channel 4 Busy - 20 - 1 - - - CHBUSY5 - Channel 5 Busy - 21 - 1 - - - CHBUSY6 - Channel 6 Busy - 22 - 1 - - - CHBUSY7 - Channel 7 Busy - 23 - 1 - - - CHBUSY8 - Channel 8 Busy - 24 - 1 - - - CHBUSY9 - Channel 9 Busy - 25 - 1 - - - CHBUSY10 - Channel 10 Busy - 26 - 1 - - - CHBUSY11 - Channel 11 Busy - 27 - 1 - - - - - INTENCLR - Interrupt Enable Clear - 0x10 - 32 - 0x00000000 - - - OVR0 - Channel 0 Overrun Interrupt Enable - 0 - 1 - - - OVR1 - Channel 1 Overrun Interrupt Enable - 1 - 1 - - - OVR2 - Channel 2 Overrun Interrupt Enable - 2 - 1 - - - OVR3 - Channel 3 Overrun Interrupt Enable - 3 - 1 - - - OVR4 - Channel 4 Overrun Interrupt Enable - 4 - 1 - - - OVR5 - Channel 5 Overrun Interrupt Enable - 5 - 1 - - - OVR6 - Channel 6 Overrun Interrupt Enable - 6 - 1 - - - OVR7 - Channel 7 Overrun Interrupt Enable - 7 - 1 - - - OVR8 - Channel 8 Overrun Interrupt Enable - 8 - 1 - - - OVR9 - Channel 9 Overrun Interrupt Enable - 9 - 1 - - - OVR10 - Channel 10 Overrun Interrupt Enable - 10 - 1 - - - OVR11 - Channel 11 Overrun Interrupt Enable - 11 - 1 - - - EVD0 - Channel 0 Event Detection Interrupt Enable - 16 - 1 - - - EVD1 - Channel 1 Event Detection Interrupt Enable - 17 - 1 - - - EVD2 - Channel 2 Event Detection Interrupt Enable - 18 - 1 - - - EVD3 - Channel 3 Event Detection Interrupt Enable - 19 - 1 - - - EVD4 - Channel 4 Event Detection Interrupt Enable - 20 - 1 - - - EVD5 - Channel 5 Event Detection Interrupt Enable - 21 - 1 - - - EVD6 - Channel 6 Event Detection Interrupt Enable - 22 - 1 - - - EVD7 - Channel 7 Event Detection Interrupt Enable - 23 - 1 - - - EVD8 - Channel 8 Event Detection Interrupt Enable - 24 - 1 - - - EVD9 - Channel 9 Event Detection Interrupt Enable - 25 - 1 - - - EVD10 - Channel 10 Event Detection Interrupt Enable - 26 - 1 - - - EVD11 - Channel 11 Event Detection Interrupt Enable - 27 - 1 - - - - - INTENSET - Interrupt Enable Set - 0x14 - 32 - 0x00000000 - - - OVR0 - Channel 0 Overrun Interrupt Enable - 0 - 1 - - - OVR1 - Channel 1 Overrun Interrupt Enable - 1 - 1 - - - OVR2 - Channel 2 Overrun Interrupt Enable - 2 - 1 - - - OVR3 - Channel 3 Overrun Interrupt Enable - 3 - 1 - - - OVR4 - Channel 4 Overrun Interrupt Enable - 4 - 1 - - - OVR5 - Channel 5 Overrun Interrupt Enable - 5 - 1 - - - OVR6 - Channel 6 Overrun Interrupt Enable - 6 - 1 - - - OVR7 - Channel 7 Overrun Interrupt Enable - 7 - 1 - - - OVR8 - Channel 8 Overrun Interrupt Enable - 8 - 1 - - - OVR9 - Channel 9 Overrun Interrupt Enable - 9 - 1 - - - OVR10 - Channel 10 Overrun Interrupt Enable - 10 - 1 - - - OVR11 - Channel 11 Overrun Interrupt Enable - 11 - 1 - - - EVD0 - Channel 0 Event Detection Interrupt Enable - 16 - 1 - - - EVD1 - Channel 1 Event Detection Interrupt Enable - 17 - 1 - - - EVD2 - Channel 2 Event Detection Interrupt Enable - 18 - 1 - - - EVD3 - Channel 3 Event Detection Interrupt Enable - 19 - 1 - - - EVD4 - Channel 4 Event Detection Interrupt Enable - 20 - 1 - - - EVD5 - Channel 5 Event Detection Interrupt Enable - 21 - 1 - - - EVD6 - Channel 6 Event Detection Interrupt Enable - 22 - 1 - - - EVD7 - Channel 7 Event Detection Interrupt Enable - 23 - 1 - - - EVD8 - Channel 8 Event Detection Interrupt Enable - 24 - 1 - - - EVD9 - Channel 9 Event Detection Interrupt Enable - 25 - 1 - - - EVD10 - Channel 10 Event Detection Interrupt Enable - 26 - 1 - - - EVD11 - Channel 11 Event Detection Interrupt Enable - 27 - 1 - - - - - INTFLAG - Interrupt Flag Status and Clear - 0x18 - 32 - 0x00000000 - - - OVR0 - Channel 0 Overrun - 0 - 1 - - - OVR1 - Channel 1 Overrun - 1 - 1 - - - OVR2 - Channel 2 Overrun - 2 - 1 - - - OVR3 - Channel 3 Overrun - 3 - 1 - - - OVR4 - Channel 4 Overrun - 4 - 1 - - - OVR5 - Channel 5 Overrun - 5 - 1 - - - OVR6 - Channel 6 Overrun - 6 - 1 - - - OVR7 - Channel 7 Overrun - 7 - 1 - - - OVR8 - Channel 8 Overrun - 8 - 1 - - - OVR9 - Channel 9 Overrun - 9 - 1 - - - OVR10 - Channel 10 Overrun - 10 - 1 - - - OVR11 - Channel 11 Overrun - 11 - 1 - - - EVD0 - Channel 0 Event Detection - 16 - 1 - - - EVD1 - Channel 1 Event Detection - 17 - 1 - - - EVD2 - Channel 2 Event Detection - 18 - 1 - - - EVD3 - Channel 3 Event Detection - 19 - 1 - - - EVD4 - Channel 4 Event Detection - 20 - 1 - - - EVD5 - Channel 5 Event Detection - 21 - 1 - - - EVD6 - Channel 6 Event Detection - 22 - 1 - - - EVD7 - Channel 7 Event Detection - 23 - 1 - - - EVD8 - Channel 8 Event Detection - 24 - 1 - - - EVD9 - Channel 9 Event Detection - 25 - 1 - - - EVD10 - Channel 10 Event Detection - 26 - 1 - - - EVD11 - Channel 11 Event Detection - 27 - 1 - - - - - SWEVT - Software Event - 0x1C - 32 - write-only - 0x00000000 - - - CHANNEL0 - Channel 0 Software Selection - 0 - 1 - - - CHANNEL1 - Channel 1 Software Selection - 1 - 1 - - - CHANNEL2 - Channel 2 Software Selection - 2 - 1 - - - CHANNEL3 - Channel 3 Software Selection - 3 - 1 - - - CHANNEL4 - Channel 4 Software Selection - 4 - 1 - - - CHANNEL5 - Channel 5 Software Selection - 5 - 1 - - - CHANNEL6 - Channel 6 Software Selection - 6 - 1 - - - CHANNEL7 - Channel 7 Software Selection - 7 - 1 - - - CHANNEL8 - Channel 8 Software Selection - 8 - 1 - - - CHANNEL9 - Channel 9 Software Selection - 9 - 1 - - - CHANNEL10 - Channel 10 Software Selection - 10 - 1 - - - CHANNEL11 - Channel 11 Software Selection - 11 - 1 - - - - - 12 - 4 - CHANNEL[%s] - Channel n - 0x20 - 32 - 0x00008000 - - - EVGEN - Event Generator Selection - 0 - 7 - - - PATH - Path Selection - 8 - 2 - - PATHSelect - - SYNCHRONOUS - Synchronous path - 0 - - - RESYNCHRONIZED - Resynchronized path - 1 - - - ASYNCHRONOUS - Asynchronous path - 2 - - - - - EDGSEL - Edge Detection Selection - 10 - 2 - - EDGSELSelect - - NO_EVT_OUTPUT - No event output when using the resynchronized or synchronous path - 0 - - - RISING_EDGE - Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path - 1 - - - FALLING_EDGE - Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path - 2 - - - BOTH_EDGES - Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path - 3 - - - - - RUNSTDBY - Run in standby - 14 - 1 - - - ONDEMAND - Generic Clock On Demand - 15 - 1 - - - - - 47 - 4 - USER[%s] - User Multiplexer n - 0x80 - 32 - 0x00000000 - - - CHANNEL - Channel Event Selection - 0 - 5 - - - - - - - FREQM - U22571.0.1 - Frequency Meter - FREQM - FREQM_ - 0x40002C00 - - 0 - 0x14 - registers - - - FREQM - 4 - - - - CTRLA - Control A Register - 0x0 - 8 - 0x00 - - - SWRST - Software Reset - 0 - 1 - - - ENABLE - Enable - 1 - 1 - - - - - CTRLB - Control B Register - 0x1 - 8 - write-only - 0x00 - - - START - Start Measurement - 0 - 1 - - - - - CFGA - Config A register - 0x2 - 16 - 0x0000 - - - REFNUM - Number of Reference Clock Cycles - 0 - 8 - - - - - INTENCLR - Interrupt Enable Clear Register - 0x8 - 8 - 0x00 - - - DONE - Measurement Done Interrupt Enable - 0 - 1 - - - - - INTENSET - Interrupt Enable Set Register - 0x9 - 8 - 0x00 - - - DONE - Measurement Done Interrupt Enable - 0 - 1 - - - - - INTFLAG - Interrupt Flag Register - 0xA - 8 - 0x00 - - - DONE - Measurement Done - 0 - 1 - - - - - STATUS - Status Register - 0xB - 8 - 0x00 - - - BUSY - FREQM Status - 0 - 1 - - - OVF - Sticky Count Value Overflow - 1 - 1 - - - - - SYNCBUSY - Synchronization Busy Register - 0xC - 32 - read-only - 0x00000000 - - - SWRST - Software Reset - 0 - 1 - - - ENABLE - Enable - 1 - 1 - - - - - VALUE - Count Value Register - 0x10 - 32 - read-only - 0x00000000 - - - VALUE - Measurement Value - 0 - 24 - - - - - - - GCLK - U21221.1.1 - Generic Clock Generator - GCLK - GCLK_ - 0x40001C00 - - 0 - 0x184 - registers - - - - CTRLA - Control - 0x0 - 8 - 0x00 - - - SWRST - Software Reset - 0 - 1 - - - - - SYNCBUSY - Synchronization Busy - 0x4 - 32 - read-only - 0x00000000 - - - SWRST - Software Reset Synchroniation Busy bit - 0 - 1 - - - GENCTRL0 - Generic Clock Generator Control 0 Synchronization Busy bits - 2 - 1 - - GENCTRL0Select - - GCLK0 - Generic clock generator 0 - 0x1 - - - GCLK1 - Generic clock generator 1 - 0x2 - - - GCLK2 - Generic clock generator 2 - 0x4 - - - GCLK3 - Generic clock generator 3 - 0x8 - - - GCLK4 - Generic clock generator 4 - 0x10 - - - GCLK5 - Generic clock generator 5 - 0x20 - - - GCLK6 - Generic clock generator 6 - 0x40 - - - GCLK7 - Generic clock generator 7 - 0x80 - - - GCLK8 - Generic clock generator 8 - 0x100 - - - - - GENCTRL1 - Generic Clock Generator Control 1 Synchronization Busy bits - 3 - 1 - - GENCTRL1Select - - GCLK0 - Generic clock generator 0 - 0x1 - - - GCLK1 - Generic clock generator 1 - 0x2 - - - GCLK2 - Generic clock generator 2 - 0x4 - - - GCLK3 - Generic clock generator 3 - 0x8 - - - GCLK4 - Generic clock generator 4 - 0x10 - - - GCLK5 - Generic clock generator 5 - 0x20 - - - GCLK6 - Generic clock generator 6 - 0x40 - - - GCLK7 - Generic clock generator 7 - 0x80 - - - GCLK8 - Generic clock generator 8 - 0x100 - - - - - GENCTRL2 - Generic Clock Generator Control 2 Synchronization Busy bits - 4 - 1 - - GENCTRL2Select - - GCLK0 - Generic clock generator 0 - 0x1 - - - GCLK1 - Generic clock generator 1 - 0x2 - - - GCLK2 - Generic clock generator 2 - 0x4 - - - GCLK3 - Generic clock generator 3 - 0x8 - - - GCLK4 - Generic clock generator 4 - 0x10 - - - GCLK5 - Generic clock generator 5 - 0x20 - - - GCLK6 - Generic clock generator 6 - 0x40 - - - GCLK7 - Generic clock generator 7 - 0x80 - - - GCLK8 - Generic clock generator 8 - 0x100 - - - - - GENCTRL3 - Generic Clock Generator Control 3 Synchronization Busy bits - 5 - 1 - - GENCTRL3Select - - GCLK0 - Generic clock generator 0 - 0x1 - - - GCLK1 - Generic clock generator 1 - 0x2 - - - GCLK2 - Generic clock generator 2 - 0x4 - - - GCLK3 - Generic clock generator 3 - 0x8 - - - GCLK4 - Generic clock generator 4 - 0x10 - - - GCLK5 - Generic clock generator 5 - 0x20 - - - GCLK6 - Generic clock generator 6 - 0x40 - - - GCLK7 - Generic clock generator 7 - 0x80 - - - GCLK8 - Generic clock generator 8 - 0x100 - - - - - GENCTRL4 - Generic Clock Generator Control 4 Synchronization Busy bits - 6 - 1 - - GENCTRL4Select - - GCLK0 - Generic clock generator 0 - 0x1 - - - GCLK1 - Generic clock generator 1 - 0x2 - - - GCLK2 - Generic clock generator 2 - 0x4 - - - GCLK3 - Generic clock generator 3 - 0x8 - - - GCLK4 - Generic clock generator 4 - 0x10 - - - GCLK5 - Generic clock generator 5 - 0x20 - - - GCLK6 - Generic clock generator 6 - 0x40 - - - GCLK7 - Generic clock generator 7 - 0x80 - - - GCLK8 - Generic clock generator 8 - 0x100 - - - - - GENCTRL5 - Generic Clock Generator Control 5 Synchronization Busy bits - 7 - 1 - - GENCTRL5Select - - GCLK0 - Generic clock generator 0 - 0x1 - - - GCLK1 - Generic clock generator 1 - 0x2 - - - GCLK2 - Generic clock generator 2 - 0x4 - - - GCLK3 - Generic clock generator 3 - 0x8 - - - GCLK4 - Generic clock generator 4 - 0x10 - - - GCLK5 - Generic clock generator 5 - 0x20 - - - GCLK6 - Generic clock generator 6 - 0x40 - - - GCLK7 - Generic clock generator 7 - 0x80 - - - GCLK8 - Generic clock generator 8 - 0x100 - - - - - GENCTRL6 - Generic Clock Generator Control 6 Synchronization Busy bits - 8 - 1 - - GENCTRL6Select - - GCLK0 - Generic clock generator 0 - 0x1 - - - GCLK1 - Generic clock generator 1 - 0x2 - - - GCLK2 - Generic clock generator 2 - 0x4 - - - GCLK3 - Generic clock generator 3 - 0x8 - - - GCLK4 - Generic clock generator 4 - 0x10 - - - GCLK5 - Generic clock generator 5 - 0x20 - - - GCLK6 - Generic clock generator 6 - 0x40 - - - GCLK7 - Generic clock generator 7 - 0x80 - - - GCLK8 - Generic clock generator 8 - 0x100 - - - - - GENCTRL7 - Generic Clock Generator Control 7 Synchronization Busy bits - 9 - 1 - - GENCTRL7Select - - GCLK0 - Generic clock generator 0 - 0x1 - - - GCLK1 - Generic clock generator 1 - 0x2 - - - GCLK2 - Generic clock generator 2 - 0x4 - - - GCLK3 - Generic clock generator 3 - 0x8 - - - GCLK4 - Generic clock generator 4 - 0x10 - - - GCLK5 - Generic clock generator 5 - 0x20 - - - GCLK6 - Generic clock generator 6 - 0x40 - - - GCLK7 - Generic clock generator 7 - 0x80 - - - GCLK8 - Generic clock generator 8 - 0x100 - - - - - GENCTRL8 - Generic Clock Generator Control 8 Synchronization Busy bits - 10 - 1 - - GENCTRL8Select - - GCLK0 - Generic clock generator 0 - 0x1 - - - GCLK1 - Generic clock generator 1 - 0x2 - - - GCLK2 - Generic clock generator 2 - 0x4 - - - GCLK3 - Generic clock generator 3 - 0x8 - - - GCLK4 - Generic clock generator 4 - 0x10 - - - GCLK5 - Generic clock generator 5 - 0x20 - - - GCLK6 - Generic clock generator 6 - 0x40 - - - GCLK7 - Generic clock generator 7 - 0x80 - - - GCLK8 - Generic clock generator 8 - 0x100 - - - - - - - 9 - 4 - GENCTRL[%s] - Generic Clock Generator Control - 0x20 - 32 - 0x00000000 - - - SRC - Source Select - 0 - 3 - - SRCSelect - - XOSC - XOSC oscillator output - 0 - - - GCLKIN - Generator input pad - 1 - - - GCLKGEN1 - Generic clock generator 1 output - 2 - - - OSCULP32K - OSCULP32K oscillator output - 3 - - - OSC32K - OSC32K oscillator output - 4 - - - XOSC32K - XOSC32K oscillator output - 5 - - - OSC48M - OSC48M oscillator output - 6 - - - DPLL96M - DPLL96M output - 7 - - - - - GENEN - Generic Clock Generator Enable - 8 - 1 - - - IDC - Improve Duty Cycle - 9 - 1 - - - OOV - Output Off Value - 10 - 1 - - - OE - Output Enable - 11 - 1 - - - DIVSEL - Divide Selection - 12 - 1 - - DIVSELSelect - - DIV1 - Divide input directly by divider factor - 0x0 - - - DIV2 - Divide input by 2^(divider factor+ 1) - 0x1 - - - - - RUNSTDBY - Run in Standby - 13 - 1 - - - DIV - Division Factor - 16 - 16 - - - - - 41 - 4 - PCHCTRL[%s] - Peripheral Clock Control - 0x80 - 32 - 0x00000000 - - - GEN - Generic Clock Generator - 0 - 4 - - GENSelect - - GCLK0 - Generic clock generator 0 - 0x0 - - - GCLK1 - Generic clock generator 1 - 0x1 - - - GCLK2 - Generic clock generator 2 - 0x2 - - - GCLK3 - Generic clock generator 3 - 0x3 - - - GCLK4 - Generic clock generator 4 - 0x4 - - - GCLK5 - Generic clock generator 5 - 0x5 - - - GCLK6 - Generic clock generator 6 - 0x6 - - - GCLK7 - Generic clock generator 7 - 0x7 - - - GCLK8 - Generic clock generator 8 - 0x8 - - - - - CHEN - Channel Enable - 6 - 1 - - - WRTLOCK - Write Lock - 7 - 1 - - - - - - - HMATRIXHS - I76382.1.3 - HSB Matrix - HMATRIXB - HMATRIXB_ - 0x4100A000 - - 0 - 0x168 - registers - - - - 16 - 4 - MCFG[%s] - Master Configuration - 0x0 - 32 - 0x00000002 - - - ULBT - Undefined Length Burst Type - 0 - 3 - - ULBTSelect - - INFINITE - Infinite Length - 0 - - - SINGLE - Single Access - 1 - - - FOUR_BEAT - Four Beat Burst - 2 - - - EIGHT_BEAT - Eight Beat Burst - 3 - - - SIXTEEN_BEAT - Sixteen Beat Burst - 4 - - - - - - - 16 - 4 - SCFG[%s] - Slave Configuration - 0x40 - 32 - 0x00000010 - - - SLOT_CYCLE - Maximum Number of Allowed Cycles for a Burst - 0 - 8 - - - DEFMSTR_TYPE - Default Master Type - 16 - 2 - - DEFMSTR_TYPESelect - - NO_DEFAULT - No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. - 0 - - - LAST_DEFAULT - Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. - 1 - - - FIXED_DEFAULT - Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave. - 2 - - - - - FIXED_DEFMSTR - Fixed Index of Default Master - 18 - 4 - - - ARBT - Arbitration Type - 24 - 1 - - ARBTSelect - - ROUND_ROBIN - Round-Robin Arbitration - 0 - - - FIXED_PRIORITY - Fixed Priority Arbitration - 1 - - - - - - - 4 - 0x8 - PRS[%s] - - 0x080 - - PRAS - Priority A for Slave - 0x0 - 32 - 0x00000000 - - - M0PR - Master 0 Priority - 0 - 4 - - - M1PR - Master 1 Priority - 4 - 4 - - - M2PR - Master 2 Priority - 8 - 4 - - - M3PR - Master 3 Priority - 12 - 4 - - - M4PR - Master 4 Priority - 16 - 4 - - - M5PR - Master 5 Priority - 20 - 4 - - - M6PR - Master 6 Priority - 24 - 4 - - - M7PR - Master 7 Priority - 28 - 4 - - - - - PRBS - Priority B for Slave - 0x4 - 32 - 0x00000000 - - - M8PR - Master 8 Priority - 0 - 4 - - - M9PR - Master 9 Priority - 4 - 4 - - - M10PR - Master 10 Priority - 8 - 4 - - - M11PR - Master 11 Priority - 12 - 4 - - - M12PR - Master 12 Priority - 16 - 4 - - - M13PR - Master 13 Priority - 20 - 4 - - - M14PR - Master 14 Priority - 24 - 4 - - - M15PR - Master 15 Priority - 28 - 4 - - - - - - MRCR - Master Remap Control - 0x100 - 32 - 0x00000000 - - - RCB0 - Remap Command Bit for Master 0 - 0 - 1 - - RCB0Select - - DIS - Disable remapped address decoding for master - 0 - - - ENA - Enable remapped address decoding for master - 1 - - - - - RCB1 - Remap Command Bit for Master 1 - 1 - 1 - - RCB1Select - - DIS - Disable remapped address decoding for master - 0 - - - ENA - Enable remapped address decoding for master - 1 - - - - - RCB2 - Remap Command Bit for Master 2 - 2 - 1 - - RCB2Select - - DIS - Disable remapped address decoding for master - 0 - - - ENA - Enable remapped address decoding for master - 1 - - - - - RCB3 - Remap Command Bit for Master 3 - 3 - 1 - - RCB3Select - - DIS - Disable remapped address decoding for master - 0 - - - ENA - Enable remapped address decoding for master - 1 - - - - - RCB4 - Remap Command Bit for Master 4 - 4 - 1 - - RCB4Select - - DIS - Disable remapped address decoding for master - 0 - - - ENA - Enable remapped address decoding for master - 1 - - - - - RCB5 - Remap Command Bit for Master 5 - 5 - 1 - - RCB5Select - - DIS - Disable remapped address decoding for master - 0 - - - ENA - Enable remapped address decoding for master - 1 - - - - - RCB6 - Remap Command Bit for Master 6 - 6 - 1 - - RCB6Select - - DIS - Disable remapped address decoding for master - 0 - - - ENA - Enable remapped address decoding for master - 1 - - - - - RCB7 - Remap Command Bit for Master 7 - 7 - 1 - - RCB7Select - - DIS - Disable remapped address decoding for master - 0 - - - ENA - Enable remapped address decoding for master - 1 - - - - - RCB8 - Remap Command Bit for Master 8 - 8 - 1 - - RCB8Select - - DIS - Disable remapped address decoding for master - 0 - - - ENA - Enable remapped address decoding for master - 1 - - - - - RCB9 - Remap Command Bit for Master 9 - 9 - 1 - - RCB9Select - - DIS - Disable remapped address decoding for master - 0 - - - ENA - Enable remapped address decoding for master - 1 - - - - - RCB10 - Remap Command Bit for Master 10 - 10 - 1 - - RCB10Select - - DIS - Disable remapped address decoding for master - 0 - - - ENA - Enable remapped address decoding for master - 1 - - - - - RCB11 - Remap Command Bit for Master 11 - 11 - 1 - - RCB11Select - - DIS - Disable remapped address decoding for master - 0 - - - ENA - Enable remapped address decoding for master - 1 - - - - - RCB12 - Remap Command Bit for Master 12 - 12 - 1 - - RCB12Select - - DIS - Disable remapped address decoding for master - 0 - - - ENA - Enable remapped address decoding for master - 1 - - - - - RCB13 - Remap Command Bit for Master 13 - 13 - 1 - - RCB13Select - - DIS - Disable remapped address decoding for master - 0 - - - ENA - Enable remapped address decoding for master - 1 - - - - - RCB14 - Remap Command Bit for Master 14 - 14 - 1 - - RCB14Select - - DIS - Disable remapped address decoding for master - 0 - - - ENA - Enable remapped address decoding for master - 1 - - - - - RCB15 - Remap Command Bit for Master 15 - 15 - 1 - - RCB15Select - - DIS - Disable remapped address decoding for master - 0 - - - ENA - Enable remapped address decoding for master - 1 - - - - - - - 16 - 4 - SFR[%s] - Special Function - 0x110 - 32 - 0x00000000 - - - SFR - Special Function Register - 0 - 32 - - - - - - - MCLK - U22342.0.0 - Main Clock - MCLK - MCLK_ - 0x40000800 - - 0 - 0x20 - registers - - - - INTENCLR - Interrupt Enable Clear - 0x1 - 8 - 0x00 - - - CKRDY - Clock Ready Interrupt Enable - 0 - 1 - - - - - INTENSET - Interrupt Enable Set - 0x2 - 8 - 0x00 - - - CKRDY - Clock Ready Interrupt Enable - 0 - 1 - - - - - INTFLAG - Interrupt Flag Status and Clear - 0x3 - 8 - 0x01 - - - CKRDY - Clock Ready - 0 - 1 - - - - - CPUDIV - CPU Clock Division - 0x4 - 8 - 0x01 - - - CPUDIV - CPU Clock Division Factor - 0 - 8 - - CPUDIVSelect - - DIV1 - Divide by 1 - 0x01 - - - DIV2 - Divide by 2 - 0x02 - - - DIV4 - Divide by 4 - 0x04 - - - DIV8 - Divide by 8 - 0x08 - - - DIV16 - Divide by 16 - 0x10 - - - DIV32 - Divide by 32 - 0x20 - - - DIV64 - Divide by 64 - 0x40 - - - DIV128 - Divide by 128 - 0x80 - - - - - - - AHBMASK - AHB Mask - 0x10 - 32 - 0x00001CFF - - - HPB0_ - HPB0 AHB Clock Mask - 0 - 1 - - - HPB1_ - HPB1 AHB Clock Mask - 1 - 1 - - - HPB2_ - HPB2 AHB Clock Mask - 2 - 1 - - - DSU_ - DSU AHB Clock Mask - 3 - 1 - - - HMATRIXHS_ - HMATRIXHS AHB Clock Mask - 4 - 1 - - - NVMCTRL_ - NVMCTRL AHB Clock Mask - 5 - 1 - - - HSRAM_ - HSRAM AHB Clock Mask - 6 - 1 - - - DMAC_ - DMAC AHB Clock Mask - 7 - 1 - - - CAN0_ - CAN0 AHB Clock Mask - 8 - 1 - - - CAN1_ - CAN1 AHB Clock Mask - 9 - 1 - - - PAC_ - PAC AHB Clock Mask - 10 - 1 - - - NVMCTRL_PICACHU_ - NVMCTRL_PICACHU AHB Clock Mask - 11 - 1 - - - DIVAS_ - DIVAS AHB Clock Mask - 12 - 1 - - - - - APBAMASK - APBA Mask - 0x14 - 32 - 0x00000FFF - - - PAC_ - PAC APB Clock Enable - 0 - 1 - - - PM_ - PM APB Clock Enable - 1 - 1 - - - MCLK_ - MCLK APB Clock Enable - 2 - 1 - - - RSTC_ - RSTC APB Clock Enable - 3 - 1 - - - OSCCTRL_ - OSCCTRL APB Clock Enable - 4 - 1 - - - OSC32KCTRL_ - OSC32KCTRL APB Clock Enable - 5 - 1 - - - SUPC_ - SUPC APB Clock Enable - 6 - 1 - - - GCLK_ - GCLK APB Clock Enable - 7 - 1 - - - WDT_ - WDT APB Clock Enable - 8 - 1 - - - RTC_ - RTC APB Clock Enable - 9 - 1 - - - EIC_ - EIC APB Clock Enable - 10 - 1 - - - FREQM_ - FREQM APB Clock Enable - 11 - 1 - - - TSENS_ - TSENS APB Clock Enable - 12 - 1 - - - - - APBBMASK - APBB Mask - 0x18 - 32 - 0x00000007 - - - PORT_ - PORT APB Clock Enable - 0 - 1 - - - DSU_ - DSU APB Clock Enable - 1 - 1 - - - NVMCTRL_ - NVMCTRL APB Clock Enable - 2 - 1 - - - HMATRIXHS_ - HMATRIXHS APB Clock Enable - 5 - 1 - - - - - APBCMASK - APBC Mask - 0x1C - 32 - 0x00000000 - - - EVSYS_ - EVSYS APB Clock Enable - 0 - 1 - - - SERCOM0_ - SERCOM0 APB Clock Enable - 1 - 1 - - - SERCOM1_ - SERCOM1 APB Clock Enable - 2 - 1 - - - SERCOM2_ - SERCOM2 APB Clock Enable - 3 - 1 - - - SERCOM3_ - SERCOM3 APB Clock Enable - 4 - 1 - - - SERCOM4_ - SERCOM4 APB Clock Enable - 5 - 1 - - - SERCOM5_ - SERCOM5 APB Clock Enable - 6 - 1 - - - TCC0_ - TCC0 APB Clock Enable - 9 - 1 - - - TCC1_ - TCC1 APB Clock Enable - 10 - 1 - - - TCC2_ - TCC2 APB Clock Enable - 11 - 1 - - - TC0_ - TC0 APB Clock Enable - 12 - 1 - - - TC1_ - TC1 APB Clock Enable - 13 - 1 - - - TC2_ - TC2 APB Clock Enable - 14 - 1 - - - TC3_ - TC3 APB Clock Enable - 15 - 1 - - - TC4_ - TC4 APB Clock Enable - 16 - 1 - - - ADC0_ - ADC0 APB Clock Enable - 17 - 1 - - - ADC1_ - ADC1 APB Clock Enable - 18 - 1 - - - SDADC_ - SDADC APB Clock Enable - 19 - 1 - - - AC_ - AC APB Clock Enable - 20 - 1 - - - DAC_ - DAC APB Clock Enable - 21 - 1 - - - PTC_ - PTC APB Clock Enable - 22 - 1 - - - CCL_ - CCL APB Clock Enable - 23 - 1 - - - - - - - MTB - U20021.0.0 - Cortex-M0+ Micro-Trace Buffer - MTB - MTB_ - 0x41008000 - - 0 - 0x1000 - registers - - - - POSITION - MTB Position - 0x0 - 32 - - - WRAP - Pointer Value Wraps - 2 - 1 - - - POINTER - Trace Packet Location Pointer - 3 - 29 - - - - - MASTER - MTB Master - 0x4 - 32 - 0x00000000 - - - MASK - Maximum Value of the Trace Buffer in SRAM - 0 - 5 - - - TSTARTEN - Trace Start Input Enable - 5 - 1 - - - TSTOPEN - Trace Stop Input Enable - 6 - 1 - - - SFRWPRIV - Special Function Register Write Privilege - 7 - 1 - - - RAMPRIV - SRAM Privilege - 8 - 1 - - - HALTREQ - Halt Request - 9 - 1 - - - EN - Main Trace Enable - 31 - 1 - - - - - FLOW - MTB Flow - 0x8 - 32 - 0x00000000 - - - AUTOSTOP - Auto Stop Tracing - 0 - 1 - - - AUTOHALT - Auto Halt Request - 1 - 1 - - - WATERMARK - Watermark value - 3 - 29 - - - - - BASE - MTB Base - 0xC - 32 - read-only - - - ITCTRL - MTB Integration Mode Control - 0xF00 - 32 - - - CLAIMSET - MTB Claim Set - 0xFA0 - 32 - - - CLAIMCLR - MTB Claim Clear - 0xFA4 - 32 - - - LOCKACCESS - MTB Lock Access - 0xFB0 - 32 - - - LOCKSTATUS - MTB Lock Status - 0xFB4 - 32 - read-only - - - AUTHSTATUS - MTB Authentication Status - 0xFB8 - 32 - read-only - - - DEVARCH - MTB Device Architecture - 0xFBC - 32 - read-only - - - DEVID - MTB Device Configuration - 0xFC8 - 32 - read-only - - - DEVTYPE - MTB Device Type - 0xFCC - 32 - read-only - - - PID4 - Peripheral Identification 4 - 0xFD0 - 32 - read-only - - - PID5 - Peripheral Identification 5 - 0xFD4 - 32 - read-only - - - PID6 - Peripheral Identification 6 - 0xFD8 - 32 - read-only - - - PID7 - Peripheral Identification 7 - 0xFDC - 32 - read-only - - - PID0 - Peripheral Identification 0 - 0xFE0 - 32 - read-only - - - PID1 - Peripheral Identification 1 - 0xFE4 - 32 - read-only - - - PID2 - Peripheral Identification 2 - 0xFE8 - 32 - read-only - - - PID3 - Peripheral Identification 3 - 0xFEC - 32 - read-only - - - CID0 - Component Identification 0 - 0xFF0 - 32 - read-only - - - CID1 - Component Identification 1 - 0xFF4 - 32 - read-only - - - CID2 - Component Identification 2 - 0xFF8 - 32 - read-only - - - CID3 - Component Identification 3 - 0xFFC - 32 - read-only - - - - - NVMCTRL - U22074.0.1.1 - Non-Volatile Memory Controller - NVMCTRL - NVMCTRL_ - 0x41004000 - - 0 - 0x30 - registers - - - NVMCTRL - 6 - - - - CTRLA - Control A - 0x0 - 16 - 0x0000 - - - CMD - Command - 0 - 7 - - CMDSelect - - ER - Erase Row - Erases the row addressed by the ADDR register. - 0x02 - - - WP - Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. - 0x04 - - - EAR - Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. - 0x05 - - - WAP - Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. - 0x06 - - - SF - Security Flow Command - 0x0A - - - WL - Write lockbits - 0x0F - - - RWWEEER - RWW EEPROM area Erase Row - Erases the row addressed by the ADDR register. - 0x1A - - - RWWEEWP - RWW EEPROM Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. - 0x1C - - - LR - Lock Region - Locks the region containing the address location in the ADDR register. - 0x40 - - - UR - Unlock Region - Unlocks the region containing the address location in the ADDR register. - 0x41 - - - SPRM - Sets the power reduction mode. - 0x42 - - - CPRM - Clears the power reduction mode. - 0x43 - - - PBC - Page Buffer Clear - Clears the page buffer. - 0x44 - - - SSB - Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row. - 0x45 - - - INVALL - Invalidate all cache lines. - 0x46 - - - - - CMDEX - Command Execution - 8 - 8 - - CMDEXSelect - - KEY - Execution Key - 0xA5 - - - - - - - CTRLB - Control B - 0x4 - 32 - 0x00000080 - - - RWS - NVM Read Wait States - 1 - 4 - - RWSSelect - - SINGLE - Single Auto Wait State - 0 - - - HALF - Half Auto Wait State - 1 - - - DUAL - Dual Auto Wait State - 2 - - - - - MANW - Manual Write - 7 - 1 - - - SLEEPPRM - Power Reduction Mode during Sleep - 8 - 2 - - SLEEPPRMSelect - - WAKEONACCESS - NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access. - 0 - - - WAKEUPINSTANT - NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep. - 1 - - - DISABLED - Auto power reduction disabled. - 3 - - - - - READMODE - NVMCTRL Read Mode - 16 - 2 - - READMODESelect - - NO_MISS_PENALTY - The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance. - 0x0 - - - LOW_POWER - Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time. - 0x1 - - - DETERMINISTIC - The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings. - 0x2 - - - - - CACHEDIS - Cache Disable - 18 - 2 - - - - - PARAM - NVM Parameter - 0x8 - 32 - 0x00000000 - - - NVMP - NVM Pages - 0 - 16 - - - PSZ - Page Size - 16 - 3 - - PSZSelect - - 8 - 8 bytes - 0x0 - - - 16 - 16 bytes - 0x1 - - - 32 - 32 bytes - 0x2 - - - 64 - 64 bytes - 0x3 - - - 128 - 128 bytes - 0x4 - - - 256 - 256 bytes - 0x5 - - - 512 - 512 bytes - 0x6 - - - 1024 - 1024 bytes - 0x7 - - - - - RWWEEP - RWW EEPROM Pages - 20 - 12 - - - - - INTENCLR - Interrupt Enable Clear - 0xC - 8 - 0x00 - - - READY - NVM Ready Interrupt Enable - 0 - 1 - - - ERROR - Error Interrupt Enable - 1 - 1 - - - - - INTENSET - Interrupt Enable Set - 0x10 - 8 - 0x00 - - - READY - NVM Ready Interrupt Enable - 0 - 1 - - - ERROR - Error Interrupt Enable - 1 - 1 - - - - - INTFLAG - Interrupt Flag Status and Clear - 0x14 - 8 - 0x00 - - - READY - NVM Ready - 0 - 1 - - - ERROR - Error - 1 - 1 - - - - - STATUS - Status - 0x18 - 16 - 0x0000 - - - PRM - Power Reduction Mode - 0 - 1 - - - LOAD - NVM Page Buffer Active Loading - 1 - 1 - - - PROGE - Programming Error Status - 2 - 1 - - - LOCKE - Lock Error Status - 3 - 1 - - - NVME - NVM Error - 4 - 1 - - - SB - Security Bit Status - 8 - 1 - - - - - ADDR - Address - 0x1C - 32 - 0x00000000 - - - ADDR - NVM Address - 0 - 22 - - - - - LOCK - Lock Section - 0x20 - 16 - 0x0000 - - - LOCK - Region Lock Bits - 0 - 16 - - - - - PBLDATA0 - Page Buffer Load Data 0 - 0x28 - 32 - read-only - 0x00000000 - - - PBLDATA1 - Page Buffer Load Data 1 - 0x2C - 32 - read-only - 0x00000000 - - - - - OSCCTRL - U21192.1.0 - Oscillators Control - OSCCTRL - OSCCTRL_ - 0x40001000 - - 0 - 0x3C - registers - - - - INTENCLR - Interrupt Enable Clear - 0x0 - 32 - 0x00000000 - - - XOSCRDY - XOSC Ready Interrupt Enable - 0 - 1 - - - XOSCFAIL - XOSC Clock Failure Detector Interrupt Enable - 1 - 1 - - - OSC48MRDY - OSC48M Ready Interrupt Enable - 4 - 1 - - - DPLLLCKR - DPLL Lock Rise Interrupt Enable - 8 - 1 - - - DPLLLCKF - DPLL Lock Fall Interrupt Enable - 9 - 1 - - - DPLLLTO - DPLL Time Out Interrupt Enable - 10 - 1 - - - DPLLLDRTO - DPLL Ratio Ready Interrupt Enable - 11 - 1 - - - - - INTENSET - Interrupt Enable Set - 0x4 - 32 - 0x00000000 - - - XOSCRDY - XOSC Ready Interrupt Enable - 0 - 1 - - - XOSCFAIL - XOSC Clock Failure Detector Interrupt Enable - 1 - 1 - - - OSC48MRDY - OSC48M Ready Interrupt Enable - 4 - 1 - - - DPLLLCKR - DPLL Lock Rise Interrupt Enable - 8 - 1 - - - DPLLLCKF - DPLL Lock Fall Interrupt Enable - 9 - 1 - - - DPLLLTO - DPLL Time Out Interrupt Enable - 10 - 1 - - - DPLLLDRTO - DPLL Ratio Ready Interrupt Enable - 11 - 1 - - - - - INTFLAG - Interrupt Flag Status and Clear - 0x8 - 32 - 0x00000000 - - - XOSCRDY - XOSC Ready - 0 - 1 - - - XOSCFAIL - XOSC Clock Failure Detector - 1 - 1 - - - OSC48MRDY - OSC48M Ready - 4 - 1 - - - DPLLLCKR - DPLL Lock Rise - 8 - 1 - - - DPLLLCKF - DPLL Lock Fall - 9 - 1 - - - DPLLLTO - DPLL Timeout - 10 - 1 - - - DPLLLDRTO - DPLL Ratio Ready - 11 - 1 - - - - - STATUS - Power and Clocks Status - 0xC - 32 - read-only - 0x00000000 - - - XOSCRDY - XOSC Ready - 0 - 1 - - - XOSCFAIL - XOSC Clock Failure Detector - 1 - 1 - - - XOSCCKSW - XOSC Clock Switch - 2 - 1 - - - OSC48MRDY - OSC48M Ready - 4 - 1 - - - DPLLLCKR - DPLL Lock Rise - 8 - 1 - - - DPLLLCKF - DPLL Lock Fall - 9 - 1 - - - DPLLTO - DPLL Timeout - 10 - 1 - - - DPLLLDRTO - DPLL Ratio Ready - 11 - 1 - - - - - XOSCCTRL - External Multipurpose Crystal Oscillator (XOSC) Control - 0x10 - 16 - 0x0080 - - - ENABLE - Oscillator Enable - 1 - 1 - - - XTALEN - Crystal Oscillator Enable - 2 - 1 - - - CFDEN - Xosc Clock Failure Detector Enable - 3 - 1 - - - SWBEN - Xosc Clock Switch Enable - 4 - 1 - - - RUNSTDBY - Run in Standby - 6 - 1 - - - ONDEMAND - On Demand Control - 7 - 1 - - - GAIN - Oscillator Gain - 8 - 3 - - GAINSelect - - GAIN2 - 2 MHz - 0 - - - GAIN4 - 4 MHz - 1 - - - GAIN8 - 8 MHz - 2 - - - GAIN16 - 16 MHz - 3 - - - GAIN30 - 30 MHz - 4 - - - - - AMPGC - Automatic Amplitude Gain Control - 11 - 1 - - - STARTUP - Start-Up Time - 12 - 4 - - STARTUPSelect - - CYCLE1 - 31 us - 0 - - - CYCLE2 - 61 us - 1 - - - CYCLE4 - 122 us - 2 - - - CYCLE8 - 244 us - 3 - - - CYCLE16 - 488 us - 4 - - - CYCLE32 - 977 us - 5 - - - CYCLE64 - 1953 us - 6 - - - CYCLE128 - 3906 us - 7 - - - CYCLE256 - 7813 us - 8 - - - CYCLE512 - 15625 us - 9 - - - CYCLE1024 - 31250 us - 10 - - - CYCLE2048 - 62500 us - 11 - - - CYCLE4096 - 125000 us - 12 - - - CYCLE8192 - 250000 us - 13 - - - CYCLE16384 - 500000 us - 14 - - - CYCLE32768 - 1000000 us - 15 - - - - - - - CFDPRESC - Clock Failure Detector Prescaler - 0x12 - 8 - 0x00 - - - CFDPRESC - Clock Failure Detector Prescaler - 0 - 3 - - CFDPRESCSelect - - DIV1 - 48 MHz - 0 - - - DIV2 - 24 MHz - 1 - - - DIV4 - 12 MHz - 2 - - - DIV8 - 6 MHz - 3 - - - DIV16 - 3 MHz - 4 - - - DIV32 - 1.5 MHz - 5 - - - DIV64 - 0.75 MHz - 6 - - - DIV128 - 0.3125 MHz - 7 - - - - - - - EVCTRL - Event Control - 0x13 - 8 - 0x00 - - - CFDEO - Clock Failure Detector Event Output Enable - 0 - 1 - - - - - OSC48MCTRL - 48MHz Internal Oscillator (OSC48M) Control - 0x14 - 8 - 0x82 - - - ENABLE - Oscillator Enable - 1 - 1 - - - RUNSTDBY - Run in Standby - 6 - 1 - - - ONDEMAND - On Demand Control - 7 - 1 - - - - - OSC48MDIV - OSC48M Divider - 0x15 - 8 - 0x0B - - - DIV - OSC48M Division Factor - 0 - 4 - - DIVSelect - - DIV1 - 48 MHz - 0 - - - DIV2 - 24 MHz - 1 - - - DIV3 - 16 MHz - 2 - - - DIV4 - 12 MHz - 3 - - - DIV5 - 9.6 MHz - 4 - - - DIV6 - 8 MHz - 5 - - - DIV7 - 6.86 MHz - 6 - - - DIV8 - 6 MHz - 7 - - - DIV9 - 5.33 MHz - 8 - - - DIV10 - 4.8 MHz - 9 - - - DIV11 - 4.36 MHz - 10 - - - DIV12 - 4 MHz - 11 - - - DIV13 - 3.69 MHz - 12 - - - DIV14 - 3.43 MHz - 13 - - - DIV15 - 3.2 MHz - 14 - - - DIV16 - 3 MHz - 15 - - - - - - - OSC48MSTUP - OSC48M Startup Time - 0x16 - 8 - 0x07 - - - STARTUP - Startup Time - 0 - 3 - - STARTUPSelect - - CYCLE8 - 166 ns - 0 - - - CYCLE16 - 333 ns - 1 - - - CYCLE32 - 667 ns - 2 - - - CYCLE64 - 1.333 us - 3 - - - CYCLE128 - 2.667 us - 4 - - - CYCLE256 - 5.333 us - 5 - - - CYCLE512 - 10.667 us - 6 - - - CYCLE1024 - 21.333 us - 7 - - - - - - - OSC48MSYNCBUSY - OSC48M Synchronization Busy - 0x18 - 32 - read-only - 0x00000000 - - - OSC48MDIV - OSC48MDIV Synchronization Status - 2 - 1 - - - - - DPLLCTRLA - DPLL Control - 0x1C - 8 - 0x80 - - - ENABLE - Enable - 1 - 1 - - - RUNSTDBY - Run in Standby - 6 - 1 - - - ONDEMAND - On Demand - 7 - 1 - - - - - DPLLRATIO - DPLL Ratio Control - 0x20 - 32 - 0x00000000 - - - LDR - Loop Divider Ratio - 0 - 12 - - - LDRFRAC - Loop Divider Ratio Fractional Part - 16 - 4 - - - - - DPLLCTRLB - Digital Core Configuration - 0x24 - 32 - 0x00000000 - - - FILTER - Proportional Integral Filter Selection - 0 - 2 - - FILTERSelect - - DEFAULT - Default filter mode - 0 - - - LBFILT - Low bandwidth filter - 1 - - - HBFILT - High bandwidth filter - 2 - - - HDFILT - High damping filter - 3 - - - - - LPEN - Low-Power Enable - 2 - 1 - - - WUF - Wake Up Fast - 3 - 1 - - - REFCLK - Reference Clock Selection - 4 - 2 - - REFCLKSelect - - XOSC32K - XOSC32K clock reference - 0 - - - XOSC - XOSC clock reference - 1 - - - GCLK - GCLK clock reference - 2 - - - - - LTIME - Lock Time - 8 - 3 - - LTIMESelect - - DEFAULT - No time-out. Automatic lock. - 0 - - - 8MS - Time-out if no lock within 8ms - 4 - - - 9MS - Time-out if no lock within 9ms - 5 - - - 10MS - Time-out if no lock within 10ms - 6 - - - 11MS - Time-out if no lock within 11ms - 7 - - - - - LBYPASS - Lock Bypass - 12 - 1 - - - DIV - Clock Divider - 16 - 11 - - - - - DPLLPRESC - DPLL Prescaler - 0x28 - 8 - 0x00 - - - PRESC - Output Clock Prescaler - 0 - 2 - - PRESCSelect - - DIV1 - DPLL output is divided by 1 - 0 - - - DIV2 - DPLL output is divided by 2 - 1 - - - DIV4 - DPLL output is divided by 4 - 2 - - - - - - - DPLLSYNCBUSY - DPLL Synchronization Busy - 0x2C - 8 - read-only - 0x00 - - - ENABLE - DPLL Enable Synchronization Status - 1 - 1 - - - DPLLRATIO - DPLL Ratio Synchronization Status - 2 - 1 - - - DPLLPRESC - DPLL Prescaler Synchronization Status - 3 - 1 - - - - - DPLLSTATUS - DPLL Status - 0x30 - 8 - read-only - 0x00 - - - LOCK - DPLL Lock Status - 0 - 1 - - - CLKRDY - DPLL Clock Ready - 1 - 1 - - - - - CAL48M - 48MHz Oscillator Calibration - 0x38 - 32 - 0x00000000 - - - FCAL - Frequency Calibration (48MHz) - 0 - 6 - - - FRANGE - Frequency Range (48MHz) - 8 - 2 - - - TCAL - Temperature Calibration (48MHz) - 16 - 6 - - - - - - - OSC32KCTRL - U22462.1.0 - 32k Oscillators Control - OSC32KCTRL - OSC32KCTRL_ - 0x40001400 - - 0 - 0x20 - registers - - - - INTENCLR - Interrupt Enable Clear - 0x0 - 32 - 0x00000000 - - - XOSC32KRDY - XOSC32K Ready Interrupt Enable - 0 - 1 - - - OSC32KRDY - OSC32K Ready Interrupt Enable - 1 - 1 - - - CLKFAIL - XOSC32K Clock Failure Detector Interrupt Enable - 2 - 1 - - - - - INTENSET - Interrupt Enable Set - 0x4 - 32 - 0x00000000 - - - XOSC32KRDY - XOSC32K Ready Interrupt Enable - 0 - 1 - - - OSC32KRDY - OSC32K Ready Interrupt Enable - 1 - 1 - - - CLKFAIL - XOSC32K Clock Failure Detector Interrupt Enable - 2 - 1 - - - - - INTFLAG - Interrupt Flag Status and Clear - 0x8 - 32 - 0x00000000 - - - XOSC32KRDY - XOSC32K Ready - 0 - 1 - - - OSC32KRDY - OSC32K Ready - 1 - 1 - - - CLKFAIL - XOSC32K Clock Failure Detector - 2 - 1 - - - - - STATUS - Power and Clocks Status - 0xC - 32 - read-only - 0x00000000 - - - XOSC32KRDY - XOSC32K Ready - 0 - 1 - - - OSC32KRDY - OSC32K Ready - 1 - 1 - - - CLKFAIL - XOSC32K Clock Failure Detector - 2 - 1 - - - CLKSW - XOSC32K Clock switch - 3 - 1 - - - - - RTCCTRL - Clock selection - 0x10 - 32 - 0x00000000 - - - RTCSEL - RTC Clock Selection - 0 - 3 - - RTCSELSelect - - ULP1K - 1.024kHz from 32kHz internal ULP oscillator - 0 - - - ULP32K - 32.768kHz from 32kHz internal ULP oscillator - 1 - - - OSC1K - 1.024kHz from 32.768kHz internal oscillator - 2 - - - OSC32K - 32.768kHz from 32.768kHz internal oscillator - 3 - - - XOSC1K - 1.024kHz from 32.768kHz internal oscillator - 4 - - - XOSC32K - 32.768kHz from 32.768kHz external crystal oscillator - 5 - - - - - - - XOSC32K - 32kHz External Crystal Oscillator (XOSC32K) Control - 0x14 - 16 - 0x0080 - - - ENABLE - Oscillator Enable - 1 - 1 - - - XTALEN - Crystal Oscillator Enable - 2 - 1 - - - EN32K - 32kHz Output Enable - 3 - 1 - - - EN1K - 1kHz Output Enable - 4 - 1 - - - RUNSTDBY - Run in Standby - 6 - 1 - - - ONDEMAND - On Demand Control - 7 - 1 - - - STARTUP - Oscillator Start-Up Time - 8 - 3 - - STARTUPSelect - - CYCLE1 - 0.122 ms - 0 - - - CYCLE32 - 1.068 ms - 1 - - - CYCLE2048 - 62.6 ms - 2 - - - CYCLE4096 - 125 ms - 3 - - - CYCLE16384 - 500 ms - 4 - - - CYCLE32768 - 1000 ms - 5 - - - CYCLE65536 - 2000 ms - 6 - - - CYCLE131072 - 4000 ms - 7 - - - - - WRTLOCK - Write Lock - 12 - 1 - - - - - CFDCTRL - Clock Failure Detector Control - 0x16 - 8 - 0x00 - - - CFDEN - Clock Failure Detector Enable - 0 - 1 - - - SWBACK - Clock Switch Back - 1 - 1 - - - CFDPRESC - Clock Failure Detector Prescaler - 2 - 1 - - - - - EVCTRL - Event Control - 0x17 - 8 - 0x00 - - - CFDEO - Clock Failure Detector Event Output Enable - 0 - 1 - - - - - OSC32K - 32kHz Internal Oscillator (OSC32K) Control - 0x18 - 32 - 0x003F0080 - - - ENABLE - Oscillator Enable - 1 - 1 - - - EN32K - 32kHz Output Enable - 2 - 1 - - - EN1K - 1kHz Output Enable - 3 - 1 - - - RUNSTDBY - Run in Standby - 6 - 1 - - - ONDEMAND - On Demand Control - 7 - 1 - - - STARTUP - Oscillator Start-Up Time - 8 - 3 - - STARTUPSelect - - CYCLE3 - 0.092 ms - 0 - - - CYCLE4 - 0.122 ms - 1 - - - CYCLE6 - 0.183 ms - 2 - - - CYCLE10 - 0.305 ms - 3 - - - CYCLE18 - 0.549 ms - 4 - - - CYCLE34 - 1.038 ms - 5 - - - CYCLE66 - 2.014 ms - 6 - - - CYCLE130 - 3.967 ms - 7 - - - - - WRTLOCK - Write Lock - 12 - 1 - - - CALIB - Oscillator Calibration - 16 - 7 - - - - - OSCULP32K - 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control - 0x1C - 32 - - - CALIB - Oscillator Calibration - 8 - 5 - - - WRTLOCK - Write Lock - 15 - 1 - - - - - - - PAC - U21201.1.0 - Peripheral Access Controller - PAC - PAC_ - 0x40000000 - - 0 - 0x40 - registers - - - - WRCTRL - Write control - 0x0 - 32 - 0x00000000 - - - PERID - Peripheral identifier - 0 - 16 - - - KEY - Peripheral access control key - 16 - 8 - - KEYSelect - - OFF - No action - 0 - - - CLR - Clear protection - 1 - - - SET - Set protection - 2 - - - SETLCK - Set and lock protection - 3 - - - - - - - EVCTRL - Event control - 0x4 - 8 - 0x00 - - - ERREO - Peripheral acess error event output - 0 - 1 - - - - - INTENCLR - Interrupt enable clear - 0x8 - 8 - 0x00 - - - ERR - Peripheral access error interrupt disable - 0 - 1 - - - - - INTENSET - Interrupt enable set - 0x9 - 8 - 0x00 - - - ERR - Peripheral access error interrupt enable - 0 - 1 - - - - - INTFLAGAHB - Bridge interrupt flag status - 0x10 - 32 - 0x00000000 - - - FLASH_ - FLASH - 0 - 1 - - - HSRAMCM0P_ - HSRAMCM0P - 1 - 1 - - - HSRAMDSU_ - HSRAMDSU - 2 - 1 - - - HPB1_ - HPB1 - 3 - 1 - - - HPB0_ - HPB0 - 4 - 1 - - - HPB2_ - HPB2 - 5 - 1 - - - LPRAMDMAC_ - LPRAMDMAC - 6 - 1 - - - DIVAS_ - DIVAS - 7 - 1 - - - - - INTFLAGA - Peripheral interrupt flag status - Bridge A - 0x14 - 32 - 0x00000000 - - - PAC_ - PAC - 0 - 1 - - - PM_ - PM - 1 - 1 - - - MCLK_ - MCLK - 2 - 1 - - - RSTC_ - RSTC - 3 - 1 - - - OSCCTRL_ - OSCCTRL - 4 - 1 - - - OSC32KCTRL_ - OSC32KCTRL - 5 - 1 - - - SUPC_ - SUPC - 6 - 1 - - - GCLK_ - GCLK - 7 - 1 - - - WDT_ - WDT - 8 - 1 - - - RTC_ - RTC - 9 - 1 - - - EIC_ - EIC - 10 - 1 - - - FREQM_ - FREQM - 11 - 1 - - - TSENS_ - TSENS - 12 - 1 - - - - - INTFLAGB - Peripheral interrupt flag status - Bridge B - 0x18 - 32 - 0x00000000 - - - PORT_ - PORT - 0 - 1 - - - DSU_ - DSU - 1 - 1 - - - NVMCTRL_ - NVMCTRL - 2 - 1 - - - DMAC_ - DMAC - 3 - 1 - - - MTB_ - MTB - 4 - 1 - - - HMATRIXHS_ - HMATRIXHS - 5 - 1 - - - - - INTFLAGC - Peripheral interrupt flag status - Bridge C - 0x1C - 32 - 0x00000000 - - - EVSYS_ - EVSYS - 0 - 1 - - - SERCOM0_ - SERCOM0 - 1 - 1 - - - SERCOM1_ - SERCOM1 - 2 - 1 - - - SERCOM2_ - SERCOM2 - 3 - 1 - - - SERCOM3_ - SERCOM3 - 4 - 1 - - - SERCOM4_ - SERCOM4 - 5 - 1 - - - SERCOM5_ - SERCOM5 - 6 - 1 - - - CAN0_ - CAN0 - 7 - 1 - - - CAN1_ - CAN1 - 8 - 1 - - - TCC0_ - TCC0 - 9 - 1 - - - TCC1_ - TCC1 - 10 - 1 - - - TCC2_ - TCC2 - 11 - 1 - - - TC0_ - TC0 - 12 - 1 - - - TC1_ - TC1 - 13 - 1 - - - TC2_ - TC2 - 14 - 1 - - - TC3_ - TC3 - 15 - 1 - - - TC4_ - TC4 - 16 - 1 - - - ADC0_ - ADC0 - 17 - 1 - - - ADC1_ - ADC1 - 18 - 1 - - - SDADC_ - SDADC - 19 - 1 - - - AC_ - AC - 20 - 1 - - - DAC_ - DAC - 21 - 1 - - - PTC_ - PTC - 22 - 1 - - - CCL_ - CCL - 23 - 1 - - - - - STATUSA - Peripheral write protection status - Bridge A - 0x34 - 32 - read-only - 0x00000000 - - - PAC_ - PAC APB Protect Enable - 0 - 1 - - - PM_ - PM APB Protect Enable - 1 - 1 - - - MCLK_ - MCLK APB Protect Enable - 2 - 1 - - - RSTC_ - RSTC APB Protect Enable - 3 - 1 - - - OSCCTRL_ - OSCCTRL APB Protect Enable - 4 - 1 - - - OSC32KCTRL_ - OSC32KCTRL APB Protect Enable - 5 - 1 - - - SUPC_ - SUPC APB Protect Enable - 6 - 1 - - - GCLK_ - GCLK APB Protect Enable - 7 - 1 - - - WDT_ - WDT APB Protect Enable - 8 - 1 - - - RTC_ - RTC APB Protect Enable - 9 - 1 - - - EIC_ - EIC APB Protect Enable - 10 - 1 - - - FREQM_ - FREQM APB Protect Enable - 11 - 1 - - - TSENS_ - TSENS APB Protect Enable - 12 - 1 - - - - - STATUSB - Peripheral write protection status - Bridge B - 0x38 - 32 - read-only - 0x00000002 - - - PORT_ - PORT APB Protect Enable - 0 - 1 - - - DSU_ - DSU APB Protect Enable - 1 - 1 - - - NVMCTRL_ - NVMCTRL APB Protect Enable - 2 - 1 - - - DMAC_ - DMAC APB Protect Enable - 3 - 1 - - - MTB_ - MTB APB Protect Enable - 4 - 1 - - - HMATRIXHS_ - HMATRIXHS APB Protect Enable - 5 - 1 - - - - - STATUSC - Peripheral write protection status - Bridge C - 0x3C - 32 - read-only - 0x02000000 - - - EVSYS_ - EVSYS APB Protect Enable - 0 - 1 - - - SERCOM0_ - SERCOM0 APB Protect Enable - 1 - 1 - - - SERCOM1_ - SERCOM1 APB Protect Enable - 2 - 1 - - - SERCOM2_ - SERCOM2 APB Protect Enable - 3 - 1 - - - SERCOM3_ - SERCOM3 APB Protect Enable - 4 - 1 - - - SERCOM4_ - SERCOM4 APB Protect Enable - 5 - 1 - - - SERCOM5_ - SERCOM5 APB Protect Enable - 6 - 1 - - - CAN0_ - CAN0 APB Protect Enable - 7 - 1 - - - CAN1_ - CAN1 APB Protect Enable - 8 - 1 - - - TCC0_ - TCC0 APB Protect Enable - 9 - 1 - - - TCC1_ - TCC1 APB Protect Enable - 10 - 1 - - - TCC2_ - TCC2 APB Protect Enable - 11 - 1 - - - TC0_ - TC0 APB Protect Enable - 12 - 1 - - - TC1_ - TC1 APB Protect Enable - 13 - 1 - - - TC2_ - TC2 APB Protect Enable - 14 - 1 - - - TC3_ - TC3 APB Protect Enable - 15 - 1 - - - TC4_ - TC4 APB Protect Enable - 16 - 1 - - - ADC0_ - ADC0 APB Protect Enable - 17 - 1 - - - ADC1_ - ADC1 APB Protect Enable - 18 - 1 - - - SDADC_ - SDADC APB Protect Enable - 19 - 1 - - - AC_ - AC APB Protect Enable - 20 - 1 - - - DAC_ - DAC APB Protect Enable - 21 - 1 - - - PTC_ - PTC APB Protect Enable - 22 - 1 - - - CCL_ - CCL APB Protect Enable - 23 - 1 - - - - - - - PM - U22402.1.0 - Power Manager - PM - PM_ - 0x40000400 - - 0 - 0xA - registers - - - - SLEEPCFG - Sleep Configuration - 0x1 - 8 - 0x00 - - - SLEEPMODE - Sleep Mode - 0 - 3 - - SLEEPMODESelect - - IDLE0 - CPU clock is OFF - 0 - - - IDLE1 - AHB clock is OFF - 1 - - - IDLE2 - APB clock are OFF - 2 - - - STANDBY - All Clocks are OFF - 4 - - - - - - - STDBYCFG - Standby Configuration - 0x8 - 16 - 0x0400 - - - VREGSMOD - Voltage Regulator Standby mode - 6 - 2 - - VREGSMODSelect - - AUTO - Automatic mode - 0 - - - PERFORMANCE - Performance oriented - 1 - - - LP - Low Power oriented - 2 - - - - - BBIASHS - Back Bias for HMCRAMCHS - 10 - 1 - - - - - - - PORT - U22102.1.1 - Port Module - PORT - PORT_ - 0x41000000 - - 0 - 0x100 - registers - - - - 2 - 0x80 - GROUP[%s] - - 0x00 - - DIR - Data Direction - 0x0 - 32 - 0x00000000 - - - DIRCLR - Data Direction Clear - 0x4 - 32 - 0x00000000 - - - DIRSET - Data Direction Set - 0x8 - 32 - 0x00000000 - - - DIRTGL - Data Direction Toggle - 0xC - 32 - 0x00000000 - - - OUT - Data Output Value - 0x10 - 32 - 0x00000000 - - - OUTCLR - Data Output Value Clear - 0x14 - 32 - 0x00000000 - - - OUTSET - Data Output Value Set - 0x18 - 32 - 0x00000000 - - - OUTTGL - Data Output Value Toggle - 0x1C - 32 - 0x00000000 - - - IN - Data Input Value - 0x20 - 32 - read-only - 0x00000000 - - - CTRL - Control - 0x24 - 32 - 0x00000000 - - - SAMPLING - Input Sampling Mode - 0 - 32 - - - - - WRCONFIG - Write Configuration - 0x28 - 32 - write-only - 0x00000000 - - - PINMASK - Pin Mask for Multiple Pin Configuration - 0 - 16 - - - PMUXEN - Select Peripheral Multiplexer - 16 - 1 - - - INEN - Input Enable - 17 - 1 - - - PULLEN - Pull Enable - 18 - 1 - - - DRVSTR - Output Driver Strength Selection - 22 - 1 - - - PMUX - Peripheral Multiplexing Template - 24 - 4 - - - WRPMUX - Write PMUX Registers - 28 - 1 - - - WRPINCFG - Write PINCFG Registers - 30 - 1 - - - HWSEL - Half-Word Select - 31 - 1 - - - - - EVCTRL - Event Input Control - 0x2C - 32 - 0x00000000 - - - PID0 - Port Event Pin Identifier 0 - 0 - 5 - - - EVACT0 - Port Event Action 0 - 5 - 2 - - EVACT0Select - - OUT - Event output to pin - 0x0 - - - SET - Set output register of pin on event - 0x1 - - - CLR - Clear output register of pin on event - 0x2 - - - TGL - Toggle output register of pin on event - 0x3 - - - - - PORTEI0 - Port Event Enable Input 0 - 7 - 1 - - - PID1 - Port Event Pin Identifier 1 - 8 - 5 - - - EVACT1 - Port Event Action 1 - 13 - 2 - - - PORTEI1 - Port Event Enable Input 1 - 15 - 1 - - - PID2 - Port Event Pin Identifier 2 - 16 - 5 - - - EVACT2 - Port Event Action 2 - 21 - 2 - - - PORTEI2 - Port Event Enable Input 2 - 23 - 1 - - - PID3 - Port Event Pin Identifier 3 - 24 - 5 - - - EVACT3 - Port Event Action 3 - 29 - 2 - - - PORTEI3 - Port Event Enable Input 3 - 31 - 1 - - - - - 16 - 1 - PMUX[%s] - Peripheral Multiplexing n - 0x30 - 8 - 0x00 - - - PMUXE - Peripheral Multiplexing for Even-Numbered Pin - 0 - 4 - - - PMUXO - Peripheral Multiplexing for Odd-Numbered Pin - 4 - 4 - - - - - 32 - 1 - PINCFG[%s] - Pin Configuration n - 0x40 - 8 - 0x00 - - - PMUXEN - Select Peripheral Multiplexer - 0 - 1 - - - INEN - Input Enable - 1 - 1 - - - PULLEN - Pull Enable - 2 - 1 - - - DRVSTR - Output Driver Strength Selection - 6 - 1 - - - - - - - - PORT_IOBUS - PORT_IOBUS_ - 0x60000000 - - - PTC - U22153.1.0 - Peripheral Touch Controller - PTC - PTC_ - 0x42005800 - - 0 - 0x1 - reserved - - - PTC - 30 - - - - RSTC - U22392.0.2 - Reset Controller - RSTC - RSTC_ - 0x40000C00 - - 0 - 0x1 - registers - - - - RCAUSE - Reset Cause - 0x0 - 8 - read-only - - - POR - Power On Reset - 0 - 1 - - - BODCORE - Brown Out CORE Detector Reset - 1 - 1 - - - BODVDD - Brown Out VDD Detector Reset - 2 - 1 - - - EXT - External Reset - 4 - 1 - - - WDT - Watchdog Reset - 5 - 1 - - - SYST - System Reset Request - 6 - 1 - - - - - - - RTC - U22501.1.1 - Real-Time Counter - RTC - RTC_ - 0x40002400 - - 0 - 0x25 - registers - - - RTC - 2 - - - - MODE0 - 32-bit Counter with Single 32-bit Compare - RtcMode0 - 0x0 - - CTRLA - MODE0 Control A - 0x0 - 16 - 0x0000 - - - SWRST - Software Reset - 0 - 1 - - - ENABLE - Enable - 1 - 1 - - - MODE - Operating Mode - 2 - 2 - - MODESelect - - COUNT32 - Mode 0: 32-bit Counter - 0x0 - - - COUNT16 - Mode 1: 16-bit Counter - 0x1 - - - CLOCK - Mode 2: Clock/Calendar - 0x2 - - - - - MATCHCLR - Clear on Match - 7 - 1 - - - PRESCALER - Prescaler - 8 - 4 - - PRESCALERSelect - - OFF - CLK_RTC_CNT = GCLK_RTC/1 - 0x0 - - - DIV1 - CLK_RTC_CNT = GCLK_RTC/1 - 0x1 - - - DIV2 - CLK_RTC_CNT = GCLK_RTC/2 - 0x2 - - - DIV4 - CLK_RTC_CNT = GCLK_RTC/4 - 0x3 - - - DIV8 - CLK_RTC_CNT = GCLK_RTC/8 - 0x4 - - - DIV16 - CLK_RTC_CNT = GCLK_RTC/16 - 0x5 - - - DIV32 - CLK_RTC_CNT = GCLK_RTC/32 - 0x6 - - - DIV64 - CLK_RTC_CNT = GCLK_RTC/64 - 0x7 - - - DIV128 - CLK_RTC_CNT = GCLK_RTC/128 - 0x8 - - - DIV256 - CLK_RTC_CNT = GCLK_RTC/256 - 0x9 - - - DIV512 - CLK_RTC_CNT = GCLK_RTC/512 - 0xA - - - DIV1024 - CLK_RTC_CNT = GCLK_RTC/1024 - 0xB - - - - - COUNTSYNC - Count Read Synchronization Enable - 15 - 1 - - - - - EVCTRL - MODE0 Event Control - 0x4 - 32 - 0x00000000 - - - PEREO0 - Periodic Interval 0 Event Output Enable - 0 - 1 - - - PEREO1 - Periodic Interval 1 Event Output Enable - 1 - 1 - - - PEREO2 - Periodic Interval 2 Event Output Enable - 2 - 1 - - - PEREO3 - Periodic Interval 3 Event Output Enable - 3 - 1 - - - PEREO4 - Periodic Interval 4 Event Output Enable - 4 - 1 - - - PEREO5 - Periodic Interval 5 Event Output Enable - 5 - 1 - - - PEREO6 - Periodic Interval 6 Event Output Enable - 6 - 1 - - - PEREO7 - Periodic Interval 7 Event Output Enable - 7 - 1 - - - CMPEO0 - Compare 0 Event Output Enable - 8 - 1 - - - OVFEO - Overflow Event Output Enable - 15 - 1 - - - - - INTENCLR - MODE0 Interrupt Enable Clear - 0x8 - 16 - 0x0000 - - - PER0 - Periodic Interval 0 Interrupt Enable - 0 - 1 - - - PER1 - Periodic Interval 1 Interrupt Enable - 1 - 1 - - - PER2 - Periodic Interval 2 Interrupt Enable - 2 - 1 - - - PER3 - Periodic Interval 3 Interrupt Enable - 3 - 1 - - - PER4 - Periodic Interval 4 Interrupt Enable - 4 - 1 - - - PER5 - Periodic Interval 5 Interrupt Enable - 5 - 1 - - - PER6 - Periodic Interval 6 Interrupt Enable - 6 - 1 - - - PER7 - Periodic Interval 7 Interrupt Enable - 7 - 1 - - - CMP0 - Compare 0 Interrupt Enable - 8 - 1 - - - OVF - Overflow Interrupt Enable - 15 - 1 - - - - - INTENSET - MODE0 Interrupt Enable Set - 0xA - 16 - 0x0000 - - - PER0 - Periodic Interval 0 Interrupt Enable - 0 - 1 - - - PER1 - Periodic Interval 1 Interrupt Enable - 1 - 1 - - - PER2 - Periodic Interval 2 Interrupt Enable - 2 - 1 - - - PER3 - Periodic Interval 3 Interrupt Enable - 3 - 1 - - - PER4 - Periodic Interval 4 Interrupt Enable - 4 - 1 - - - PER5 - Periodic Interval 5 Interrupt Enable - 5 - 1 - - - PER6 - Periodic Interval 6 Interrupt Enable - 6 - 1 - - - PER7 - Periodic Interval 7 Interrupt Enable - 7 - 1 - - - CMP0 - Compare 0 Interrupt Enable - 8 - 1 - - - OVF - Overflow Interrupt Enable - 15 - 1 - - - - - INTFLAG - MODE0 Interrupt Flag Status and Clear - 0xC - 16 - 0x0000 - - - PER0 - Periodic Interval 0 - 0 - 1 - - - PER1 - Periodic Interval 1 - 1 - 1 - - - PER2 - Periodic Interval 2 - 2 - 1 - - - PER3 - Periodic Interval 3 - 3 - 1 - - - PER4 - Periodic Interval 4 - 4 - 1 - - - PER5 - Periodic Interval 5 - 5 - 1 - - - PER6 - Periodic Interval 6 - 6 - 1 - - - PER7 - Periodic Interval 7 - 7 - 1 - - - CMP0 - Compare 0 - 8 - 1 - - - OVF - Overflow - 15 - 1 - - - - - DBGCTRL - Debug Control - 0xE - 8 - 0x00 - - - DBGRUN - Run During Debug - 0 - 1 - - - - - SYNCBUSY - MODE0 Synchronization Busy Status - 0x10 - 32 - read-only - 0x00000000 - - - SWRST - Software Reset Busy - 0 - 1 - - - ENABLE - Enable Bit Busy - 1 - 1 - - - FREQCORR - FREQCORR Register Busy - 2 - 1 - - - COUNT - COUNT Register Busy - 3 - 1 - - - COMP0 - COMP 0 Register Busy - 5 - 1 - - - COUNTSYNC - Count Read Synchronization Enable Bit Busy - 15 - 1 - - - - - FREQCORR - Frequency Correction - 0x14 - 8 - 0x00 - - - VALUE - Correction Value - 0 - 7 - - - SIGN - Correction Sign - 7 - 1 - - - - - COUNT - MODE0 Counter Value - 0x18 - 32 - 0x00000000 - - - COUNT - Counter Value - 0 - 32 - - - - - COMP - MODE0 Compare n Value - 0x20 - 32 - 0x00000000 - - - COMP - Compare Value - 0 - 32 - - - - - - MODE1 - 16-bit Counter with Two 16-bit Compares - MODE0 - RtcMode1 - 0x0 - - CTRLA - MODE1 Control A - 0x0 - 16 - 0x0000 - - - SWRST - Software Reset - 0 - 1 - - - ENABLE - Enable - 1 - 1 - - - MODE - Operating Mode - 2 - 2 - - MODESelect - - COUNT32 - Mode 0: 32-bit Counter - 0 - - - COUNT16 - Mode 1: 16-bit Counter - 1 - - - CLOCK - Mode 2: Clock/Calendar - 2 - - - - - PRESCALER - Prescaler - 8 - 4 - - PRESCALERSelect - - OFF - CLK_RTC_CNT = GCLK_RTC/1 - 0 - - - DIV1 - CLK_RTC_CNT = GCLK_RTC/1 - 1 - - - DIV2 - CLK_RTC_CNT = GCLK_RTC/2 - 2 - - - DIV4 - CLK_RTC_CNT = GCLK_RTC/4 - 3 - - - DIV8 - CLK_RTC_CNT = GCLK_RTC/8 - 4 - - - DIV16 - CLK_RTC_CNT = GCLK_RTC/16 - 5 - - - DIV32 - CLK_RTC_CNT = GCLK_RTC/32 - 6 - - - DIV64 - CLK_RTC_CNT = GCLK_RTC/64 - 7 - - - DIV128 - CLK_RTC_CNT = GCLK_RTC/128 - 8 - - - DIV256 - CLK_RTC_CNT = GCLK_RTC/256 - 9 - - - DIV512 - CLK_RTC_CNT = GCLK_RTC/512 - 0xA - - - DIV1024 - CLK_RTC_CNT = GCLK_RTC/1024 - 0xB - - - - - COUNTSYNC - Count Read Synchronization Enable - 15 - 1 - - - - - EVCTRL - MODE1 Event Control - 0x4 - 32 - 0x00000000 - - - PEREO0 - Periodic Interval 0 Event Output Enable - 0 - 1 - - - PEREO1 - Periodic Interval 1 Event Output Enable - 1 - 1 - - - PEREO2 - Periodic Interval 2 Event Output Enable - 2 - 1 - - - PEREO3 - Periodic Interval 3 Event Output Enable - 3 - 1 - - - PEREO4 - Periodic Interval 4 Event Output Enable - 4 - 1 - - - PEREO5 - Periodic Interval 5 Event Output Enable - 5 - 1 - - - PEREO6 - Periodic Interval 6 Event Output Enable - 6 - 1 - - - PEREO7 - Periodic Interval 7 Event Output Enable - 7 - 1 - - - CMPEO0 - Compare 0 Event Output Enable - 8 - 1 - - - CMPEO1 - Compare 1 Event Output Enable - 9 - 1 - - - OVFEO - Overflow Event Output Enable - 15 - 1 - - - - - INTENCLR - MODE1 Interrupt Enable Clear - 0x8 - 16 - 0x0000 - - - PER0 - Periodic Interval 0 Interrupt Enable - 0 - 1 - - - PER1 - Periodic Interval 1 Interrupt Enable - 1 - 1 - - - PER2 - Periodic Interval 2 Interrupt Enable - 2 - 1 - - - PER3 - Periodic Interval 3 Interrupt Enable - 3 - 1 - - - PER4 - Periodic Interval 4 Interrupt Enable - 4 - 1 - - - PER5 - Periodic Interval 5 Interrupt Enable - 5 - 1 - - - PER6 - Periodic Interval 6 Interrupt Enable - 6 - 1 - - - PER7 - Periodic Interval 7 Interrupt Enable - 7 - 1 - - - CMP0 - Compare 0 Interrupt Enable - 8 - 1 - - - CMP1 - Compare 1 Interrupt Enable - 9 - 1 - - - OVF - Overflow Interrupt Enable - 15 - 1 - - - - - INTENSET - MODE1 Interrupt Enable Set - 0xA - 16 - 0x0000 - - - PER0 - Periodic Interval 0 Interrupt Enable - 0 - 1 - - - PER1 - Periodic Interval 1 Interrupt Enable - 1 - 1 - - - PER2 - Periodic Interval 2 Interrupt Enable - 2 - 1 - - - PER3 - Periodic Interval 3 Interrupt Enable - 3 - 1 - - - PER4 - Periodic Interval 4 Interrupt Enable - 4 - 1 - - - PER5 - Periodic Interval 5 Interrupt Enable - 5 - 1 - - - PER6 - Periodic Interval 6 Interrupt Enable - 6 - 1 - - - PER7 - Periodic Interval 7 Interrupt Enable - 7 - 1 - - - CMP0 - Compare 0 Interrupt Enable - 8 - 1 - - - CMP1 - Compare 1 Interrupt Enable - 9 - 1 - - - OVF - Overflow Interrupt Enable - 15 - 1 - - - - - INTFLAG - MODE1 Interrupt Flag Status and Clear - 0xC - 16 - 0x0000 - - - PER0 - Periodic Interval 0 - 0 - 1 - - - PER1 - Periodic Interval 1 - 1 - 1 - - - PER2 - Periodic Interval 2 - 2 - 1 - - - PER3 - Periodic Interval 3 - 3 - 1 - - - PER4 - Periodic Interval 4 - 4 - 1 - - - PER5 - Periodic Interval 5 - 5 - 1 - - - PER6 - Periodic Interval 6 - 6 - 1 - - - PER7 - Periodic Interval 7 - 7 - 1 - - - CMP0 - Compare 0 - 8 - 1 - - - CMP1 - Compare 1 - 9 - 1 - - - OVF - Overflow - 15 - 1 - - - - - DBGCTRL - Debug Control - 0xE - 8 - 0x00 - - - DBGRUN - Run During Debug - 0 - 1 - - - - - SYNCBUSY - MODE1 Synchronization Busy Status - 0x10 - 32 - read-only - 0x00000000 - - - SWRST - Software Reset Bit Busy - 0 - 1 - - - ENABLE - Enable Bit Busy - 1 - 1 - - - FREQCORR - FREQCORR Register Busy - 2 - 1 - - - COUNT - COUNT Register Busy - 3 - 1 - - - PER - PER Register Busy - 4 - 1 - - - COMP0 - COMP 0 Register Busy - 5 - 1 - - - COMP1 - COMP 1 Register Busy - 6 - 1 - - - COUNTSYNC - Count Read Synchronization Enable Bit Busy - 15 - 1 - - - - - FREQCORR - Frequency Correction - 0x14 - 8 - 0x00 - - - VALUE - Correction Value - 0 - 7 - - - SIGN - Correction Sign - 7 - 1 - - - - - COUNT - MODE1 Counter Value - 0x18 - 16 - 0x0000 - - - COUNT - Counter Value - 0 - 16 - - - - - PER - MODE1 Counter Period - 0x1C - 16 - 0x0000 - - - PER - Counter Period - 0 - 16 - - - - - 2 - 2 - COMP[%s] - MODE1 Compare n Value - 0x20 - 16 - 0x0000 - - - COMP - Compare Value - 0 - 16 - - - - - - MODE2 - Clock/Calendar with Alarm - MODE0 - RtcMode2 - 0x0 - - CTRLA - MODE2 Control A - 0x0 - 16 - 0x0000 - - - SWRST - Software Reset - 0 - 1 - - - ENABLE - Enable - 1 - 1 - - - MODE - Operating Mode - 2 - 2 - - MODESelect - - COUNT32 - Mode 0: 32-bit Counter - 0 - - - COUNT16 - Mode 1: 16-bit Counter - 1 - - - CLOCK - Mode 2: Clock/Calendar - 2 - - - - - CLKREP - Clock Representation - 6 - 1 - - - MATCHCLR - Clear on Match - 7 - 1 - - - PRESCALER - Prescaler - 8 - 4 - - PRESCALERSelect - - OFF - CLK_RTC_CNT = GCLK_RTC/1 - 0x0 - - - DIV1 - CLK_RTC_CNT = GCLK_RTC/1 - 0x1 - - - DIV2 - CLK_RTC_CNT = GCLK_RTC/2 - 0x2 - - - DIV4 - CLK_RTC_CNT = GCLK_RTC/4 - 0x3 - - - DIV8 - CLK_RTC_CNT = GCLK_RTC/8 - 0x4 - - - DIV16 - CLK_RTC_CNT = GCLK_RTC/16 - 0x5 - - - DIV32 - CLK_RTC_CNT = GCLK_RTC/32 - 0x6 - - - DIV64 - CLK_RTC_CNT = GCLK_RTC/64 - 0x7 - - - DIV128 - CLK_RTC_CNT = GCLK_RTC/128 - 0x8 - - - DIV256 - CLK_RTC_CNT = GCLK_RTC/256 - 0x9 - - - DIV512 - CLK_RTC_CNT = GCLK_RTC/512 - 0xA - - - DIV1024 - CLK_RTC_CNT = GCLK_RTC/1024 - 0xB - - - - - CLOCKSYNC - Clock Read Synchronization Enable - 15 - 1 - - - - - EVCTRL - MODE2 Event Control - 0x4 - 32 - 0x00000000 - - - PEREO0 - Periodic Interval 0 Event Output Enable - 0 - 1 - - - PEREO1 - Periodic Interval 1 Event Output Enable - 1 - 1 - - - PEREO2 - Periodic Interval 2 Event Output Enable - 2 - 1 - - - PEREO3 - Periodic Interval 3 Event Output Enable - 3 - 1 - - - PEREO4 - Periodic Interval 4 Event Output Enable - 4 - 1 - - - PEREO5 - Periodic Interval 5 Event Output Enable - 5 - 1 - - - PEREO6 - Periodic Interval 6 Event Output Enable - 6 - 1 - - - PEREO7 - Periodic Interval 7 Event Output Enable - 7 - 1 - - - ALARMEO0 - Alarm 0 Event Output Enable - 8 - 1 - - - OVFEO - Overflow Event Output Enable - 15 - 1 - - - - - INTENCLR - MODE2 Interrupt Enable Clear - 0x8 - 16 - 0x0000 - - - PER0 - Periodic Interval 0 Interrupt Enable - 0 - 1 - - - PER1 - Periodic Interval 1 Interrupt Enable - 1 - 1 - - - PER2 - Periodic Interval 2 Interrupt Enable - 2 - 1 - - - PER3 - Periodic Interval 3 Interrupt Enable - 3 - 1 - - - PER4 - Periodic Interval 4 Interrupt Enable - 4 - 1 - - - PER5 - Periodic Interval 5 Interrupt Enable - 5 - 1 - - - PER6 - Periodic Interval 6 Interrupt Enable - 6 - 1 - - - PER7 - Periodic Interval 7 Interrupt Enable - 7 - 1 - - - ALARM0 - Alarm 0 Interrupt Enable - 8 - 1 - - - OVF - Overflow Interrupt Enable - 15 - 1 - - - - - INTENSET - MODE2 Interrupt Enable Set - 0xA - 16 - 0x0000 - - - PER0 - Periodic Interval 0 Enable - 0 - 1 - - - PER1 - Periodic Interval 1 Enable - 1 - 1 - - - PER2 - Periodic Interval 2 Enable - 2 - 1 - - - PER3 - Periodic Interval 3 Enable - 3 - 1 - - - PER4 - Periodic Interval 4 Enable - 4 - 1 - - - PER5 - Periodic Interval 5 Enable - 5 - 1 - - - PER6 - Periodic Interval 6 Enable - 6 - 1 - - - PER7 - Periodic Interval 7 Enable - 7 - 1 - - - ALARM0 - Alarm 0 Interrupt Enable - 8 - 1 - - - OVF - Overflow Interrupt Enable - 15 - 1 - - - - - INTFLAG - MODE2 Interrupt Flag Status and Clear - 0xC - 16 - 0x0000 - - - PER0 - Periodic Interval 0 - 0 - 1 - - - PER1 - Periodic Interval 1 - 1 - 1 - - - PER2 - Periodic Interval 2 - 2 - 1 - - - PER3 - Periodic Interval 3 - 3 - 1 - - - PER4 - Periodic Interval 4 - 4 - 1 - - - PER5 - Periodic Interval 5 - 5 - 1 - - - PER6 - Periodic Interval 6 - 6 - 1 - - - PER7 - Periodic Interval 7 - 7 - 1 - - - ALARM0 - Alarm 0 - 8 - 1 - - - OVF - Overflow - 15 - 1 - - - - - DBGCTRL - Debug Control - 0xE - 8 - 0x00 - - - DBGRUN - Run During Debug - 0 - 1 - - - - - SYNCBUSY - MODE2 Synchronization Busy Status - 0x10 - 32 - read-only - 0x00000000 - - - SWRST - Software Reset Bit Busy - 0 - 1 - - - ENABLE - Enable Bit Busy - 1 - 1 - - - FREQCORR - FREQCORR Register Busy - 2 - 1 - - - CLOCK - CLOCK Register Busy - 3 - 1 - - - ALARM0 - ALARM 0 Register Busy - 5 - 1 - - - MASK0 - MASK 0 Register Busy - 11 - 1 - - - CLOCKSYNC - Clock Read Synchronization Enable Bit Busy - 15 - 1 - - - - - FREQCORR - Frequency Correction - 0x14 - 8 - 0x00 - - - VALUE - Correction Value - 0 - 7 - - - SIGN - Correction Sign - 7 - 1 - - - - - CLOCK - MODE2 Clock Value - 0x18 - 32 - 0x00000000 - - - SECOND - Second - 0 - 6 - - - MINUTE - Minute - 6 - 6 - - - HOUR - Hour - 12 - 5 - - HOURSelect - - AM - AM when CLKREP in 12-hour - 0x00 - - - PM - PM when CLKREP in 12-hour - 0x10 - - - - - DAY - Day - 17 - 5 - - - MONTH - Month - 22 - 4 - - - YEAR - Year - 26 - 6 - - - - - ALARM - MODE2_ALARM Alarm n Value - 0x20 - 32 - 0x00000000 - - - SECOND - Second - 0 - 6 - - - MINUTE - Minute - 6 - 6 - - - HOUR - Hour - 12 - 5 - - HOURSelect - - AM - Morning hour - 0x00 - - - PM - Afternoon hour - 0x10 - - - - - DAY - Day - 17 - 5 - - - MONTH - Month - 22 - 4 - - - YEAR - Year - 26 - 6 - - - - - MASK - MODE2_ALARM Alarm n Mask - 0x24 - 8 - 0x00 - - - SEL - Alarm Mask Selection - 0 - 3 - - SELSelect - - OFF - Alarm Disabled - 0x0 - - - SS - Match seconds only - 0x1 - - - MMSS - Match seconds and minutes only - 0x2 - - - HHMMSS - Match seconds, minutes, and hours only - 0x3 - - - DDHHMMSS - Match seconds, minutes, hours, and days only - 0x4 - - - MMDDHHMMSS - Match seconds, minutes, hours, days, and months only - 0x5 - - - YYMMDDHHMMSS - Match seconds, minutes, hours, days, months, and years - 0x6 - - - - - - - - - - SDADC - U22601.0.1 - Sigma-Delta Analog Digital Converter - SDADC - SDADC_ - 0x42004C00 - - 0 - 0x2F - registers - - - SDADC - 29 - - - - CTRLA - Control A - 0x0 - 8 - 0x00 - - - SWRST - Software Reset - 0 - 1 - - - ENABLE - Enable - 1 - 1 - - - RUNSTDBY - Run during Standby - 6 - 1 - - - ONDEMAND - On Demand Control - 7 - 1 - - - - - REFCTRL - Reference Control - 0x1 - 8 - 0x00 - - - REFSEL - Reference Selection - 0 - 2 - - REFSELSelect - - INTREF - Internal Bandgap Reference - 0 - - - AREFB - External Reference - 1 - - - DAC - Internal DAC Output - 2 - - - INTVCC - VDDANA - 3 - - - - - REFRANGE - Reference Range - 4 - 2 - - - ONREFBUF - Reference Buffer - 7 - 1 - - - - - CTRLB - Control B - 0x2 - 16 - 0x2000 - - - PRESCALER - Prescaler Configuration - 0 - 8 - - PRESCALERSelect - - DIV2 - Peripheral clock divided by 2 - 0x0 - - - DIV4 - Peripheral clock divided by 4 - 0x1 - - - DIV8 - Peripheral clock divided by 8 - 0x2 - - - DIV16 - Peripheral clock divided by 16 - 0x3 - - - DIV32 - Peripheral clock divided by 32 - 0x4 - - - DIV64 - Peripheral clock divided by 64 - 0x5 - - - DIV128 - Peripheral clock divided by 128 - 0x6 - - - DIV256 - Peripheral clock divided by 256 - 0x7 - - - - - OSR - Over Sampling Ratio - 8 - 3 - - OSRSelect - - OSR64 - Over Sampling Ratio is 64 - 0x0 - - - OSR128 - Over Sampling Ratio is 128 - 0x1 - - - OSR256 - Over Sampling Ratio is 256 - 0x2 - - - OSR512 - Over Sampling Ratio is 512 - 0x3 - - - OSR1024 - Over Sampling Ratio is 1024 - 0x4 - - - - - SKPCNT - Skip Sample Count - 12 - 4 - - - - - EVCTRL - Event Control - 0x4 - 8 - 0x00 - - - FLUSHEI - Flush Event Input Enable - 0 - 1 - - - STARTEI - Start Conversion Event Input Enable - 1 - 1 - - - FLUSHINV - Flush Event Invert Enable - 2 - 1 - - - STARTINV - Satrt Event Invert Enable - 3 - 1 - - - RESRDYEO - Result Ready Event Out - 4 - 1 - - - WINMONEO - Window Monitor Event Out - 5 - 1 - - - - - INTENCLR - Interrupt Enable Clear - 0x5 - 8 - 0x00 - - - RESRDY - Result Ready Interrupt Disable - 0 - 1 - - - OVERRUN - Overrun Interrupt Disable - 1 - 1 - - - WINMON - Window Monitor Interrupt Disable - 2 - 1 - - - - - INTENSET - Interrupt Enable Set - 0x6 - 8 - 0x00 - - - RESRDY - Result Ready Interrupt Enable - 0 - 1 - - - OVERRUN - Overrun Interrupt Enable - 1 - 1 - - - WINMON - Window Monitor Interrupt Enable - 2 - 1 - - - - - INTFLAG - Interrupt Flag Status and Clear - 0x7 - 8 - 0x00 - - - RESRDY - Result Ready Interrupt Flag - 0 - 1 - - - OVERRUN - Overrun Interrupt Flag - 1 - 1 - - - WINMON - Window Monitor Interrupt Flag - 2 - 1 - - - - - SEQSTATUS - Sequence Status - 0x8 - 8 - read-only - 0x00 - - - SEQSTATE - Sequence State - 0 - 4 - - - SEQBUSY - Sequence Busy - 7 - 1 - - - - - INPUTCTRL - Input Control - 0x9 - 8 - 0x00 - - - MUXSEL - SDADC Input Selection - 0 - 4 - - MUXSELSelect - - AIN0 - SDADC AIN0 Pin - 0x0 - - - AIN1 - SDADC AIN1 Pin - 0x1 - - - AIN2 - SDADC AIN2 Pin - 0x2 - - - - - - - CTRLC - Control C - 0xA - 8 - 0x00 - - - FREERUN - Free Running Mode - 0 - 1 - - - - - WINCTRL - Window Monitor Control - 0xB - 8 - 0x00 - - - WINMODE - Window Monitor Mode - 0 - 3 - - - - - WINLT - Window Monitor Lower Threshold - 0xC - 32 - 0x00000000 - - - WINLT - Window Lower Threshold - 0 - 24 - - - - - WINUT - Window Monitor Upper Threshold - 0x10 - 32 - 0x00000000 - - - WINUT - Window Upper Threshold - 0 - 24 - - - - - OFFSETCORR - Offset Correction - 0x14 - 32 - 0x00000000 - - - OFFSETCORR - Offset Correction Value - 0 - 24 - - - - - GAINCORR - Gain Correction - 0x18 - 16 - 0x0001 - - - GAINCORR - Gain Correction Value - 0 - 14 - - - - - SHIFTCORR - Shift Correction - 0x1A - 8 - 0x00 - - - SHIFTCORR - Shift Correction Value - 0 - 4 - - - - - SWTRIG - Software Trigger - 0x1C - 8 - 0x00 - - - FLUSH - SDADC Flush - 0 - 1 - - - START - Start SDADC Conversion - 1 - 1 - - - - - SYNCBUSY - Synchronization Busy - 0x20 - 32 - read-only - 0x00000000 - - - SWRST - SWRST Synchronization Busy - 0 - 1 - - - ENABLE - ENABLE Synchronization Busy - 1 - 1 - - - CTRLC - CTRLC Synchronization Busy - 2 - 1 - - - INPUTCTRL - INPUTCTRL Synchronization Busy - 3 - 1 - - - WINCTRL - WINCTRL Synchronization Busy - 4 - 1 - - - WINLT - WINLT Synchronization Busy - 5 - 1 - - - WINUT - WINUT Synchronization Busy - 6 - 1 - - - OFFSETCORR - OFFSETCTRL Synchronization Busy - 7 - 1 - - - GAINCORR - GAINCORR Synchronization Busy - 8 - 1 - - - SHIFTCORR - SHIFTCORR Synchronization Busy - 9 - 1 - - - SWTRIG - SWTRG Synchronization Busy - 10 - 1 - - - ANACTRL - ANACTRL Synchronization Busy - 11 - 1 - - - - - RESULT - Result - 0x24 - 32 - read-only - 0x00000000 - - - RESULT - Result Value - 0 - 24 - - - RESERVED - 24 - 8 - - - - - SEQCTRL - Sequence Control - 0x28 - 8 - 0x00 - - - SEQEN - Enable Positive Input in the Sequence - 0 - 3 - - - - - ANACTRL - Analog Control - 0x2C - 8 - 0x00 - - - CTRSDADC - SDADC Control - 0 - 6 - - - ONCHOP - Chopper - 6 - 1 - - - BUFTEST - BUFTEST - 7 - 1 - - - - - DBGCTRL - Debug Control - 0x2E - 8 - 0x00 - - - DBGRUN - Debug Run - 0 - 1 - - - - - - - SERCOM0 - U22013.1.1 - Serial Communication Interface - SERCOM - SERCOM_ - 0x42000400 - - 0 - 0x31 - registers - - - SERCOM0 - 9 - - - - I2CM - I2C Master Mode - SercomI2cm - 0x0 - - CTRLA - I2CM Control A - 0x0 - 32 - 0x00000000 - - - SWRST - Software Reset - 0 - 1 - - - ENABLE - Enable - 1 - 1 - - - MODE - Operating Mode - 2 - 3 - - MODESelect - - USART_EXT_CLK - USART with external clock - 0x0 - - - USART_INT_CLK - USART with internal clock - 0x1 - - - SPI_SLAVE - SPI in slave operation - 0x2 - - - SPI_MASTER - SPI in master operation - 0x3 - - - I2C_SLAVE - I2C slave operation - 0x4 - - - I2C_MASTER - I2C master operation - 0x5 - - - - - RUNSTDBY - Run in Standby - 7 - 1 - - - PINOUT - Pin Usage - 16 - 1 - - - SDAHOLD - SDA Hold Time - 20 - 2 - - SDAHOLDSelect - - DISABLE - Disabled - 0x0 - - - 75NS - 50-100ns hold time - 0x1 - - - 450NS - 300-600ns hold time - 0x2 - - - 600NS - 400-800ns hold time - 0x3 - - - - - MEXTTOEN - Master SCL Low Extend Timeout - 22 - 1 - - - SEXTTOEN - Slave SCL Low Extend Timeout - 23 - 1 - - - SPEED - Transfer Speed - 24 - 2 - - SPEEDSelect - - STANDARD_AND_FAST_MODE - Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz - 0x0 - - - FASTPLUS_MODE - Fast-mode Plus Upto 1MHz - 0x1 - - - HIGH_SPEED_MODE - High-speed mode Upto 3.4MHz - 0x2 - - - - - SCLSM - SCL Clock Stretch Mode - 27 - 1 - - - INACTOUT - Inactive Time-Out - 28 - 2 - - INACTOUTSelect - - DISABLE - Disabled - 0x0 - - - 55US - 5-6 SCL Time-Out(50-60us) - 0x1 - - - 105US - 10-11 SCL Time-Out(100-110us) - 0x2 - - - 205US - 20-21 SCL Time-Out(200-210us) - 0x3 - - - - - LOWTOUTEN - SCL Low Timeout Enable - 30 - 1 - - - - - CTRLB - I2CM Control B - 0x4 - 32 - 0x00000000 - - - SMEN - Smart Mode Enable - 8 - 1 - - - QCEN - Quick Command Enable - 9 - 1 - - - CMD - Command - 16 - 2 - - - ACKACT - Acknowledge Action - 18 - 1 - - - - - BAUD - I2CM Baud Rate - 0xC - 32 - 0x00000000 - - - BAUD - Baud Rate Value - 0 - 8 - - - BAUDLOW - Baud Rate Value Low - 8 - 8 - - - HSBAUD - High Speed Baud Rate Value - 16 - 8 - - - HSBAUDLOW - High Speed Baud Rate Value Low - 24 - 8 - - - - - INTENCLR - I2CM Interrupt Enable Clear - 0x14 - 8 - 0x00 - - - MB - Master On Bus Interrupt Disable - 0 - 1 - - - SB - Slave On Bus Interrupt Disable - 1 - 1 - - - ERROR - Combined Error Interrupt Disable - 7 - 1 - - - - - INTENSET - I2CM Interrupt Enable Set - 0x16 - 8 - 0x00 - - - MB - Master On Bus Interrupt Enable - 0 - 1 - - - SB - Slave On Bus Interrupt Enable - 1 - 1 - - - ERROR - Combined Error Interrupt Enable - 7 - 1 - - - - - INTFLAG - I2CM Interrupt Flag Status and Clear - 0x18 - 8 - 0x00 - - - MB - Master On Bus Interrupt - 0 - 1 - - - SB - Slave On Bus Interrupt - 1 - 1 - - - ERROR - Combined Error Interrupt - 7 - 1 - - - - - STATUS - I2CM Status - 0x1A - 16 - 0x0000 - - - BUSERR - Bus Error - 0 - 1 - - - ARBLOST - Arbitration Lost - 1 - 1 - - - RXNACK - Received Not Acknowledge - 2 - 1 - - - BUSSTATE - Bus State - 4 - 2 - - - LOWTOUT - SCL Low Timeout - 6 - 1 - - - CLKHOLD - Clock Hold - 7 - 1 - - - MEXTTOUT - Master SCL Low Extend Timeout - 8 - 1 - - - SEXTTOUT - Slave SCL Low Extend Timeout - 9 - 1 - - - LENERR - Length Error - 10 - 1 - - - - - SYNCBUSY - I2CM Synchronization Busy - 0x1C - 32 - read-only - 0x00000000 - - - SWRST - Software Reset Synchronization Busy - 0 - 1 - - - ENABLE - SERCOM Enable Synchronization Busy - 1 - 1 - - - SYSOP - System Operation Synchronization Busy - 2 - 1 - - - - - ADDR - I2CM Address - 0x24 - 32 - 0x00000000 - - - ADDR - Address Value - 0 - 11 - - - LENEN - Length Enable - 13 - 1 - - - HS - High Speed Mode - 14 - 1 - - - TENBITEN - Ten Bit Addressing Enable - 15 - 1 - - - LEN - Length - 16 - 8 - - - - - DATA - I2CM Data - 0x28 - 8 - 0x00 - - - DATA - Data Value - 0 - 8 - - - - - DBGCTRL - I2CM Debug Control - 0x30 - 8 - 0x00 - - - DBGSTOP - Debug Mode - 0 - 1 - - - - - - I2CS - I2C Slave Mode - I2CM - SercomI2cs - 0x0 - - CTRLA - I2CS Control A - 0x0 - 32 - 0x00000000 - - - SWRST - Software Reset - 0 - 1 - - - ENABLE - Enable - 1 - 1 - - - MODE - Operating Mode - 2 - 3 - - MODESelect - - USART_EXT_CLK - USART with external clock - 0x0 - - - USART_INT_CLK - USART with internal clock - 0x1 - - - SPI_SLAVE - SPI in slave operation - 0x2 - - - SPI_MASTER - SPI in master operation - 0x3 - - - I2C_SLAVE - I2C slave operation - 0x4 - - - I2C_MASTER - I2C master operation - 0x5 - - - - - RUNSTDBY - Run during Standby - 7 - 1 - - - PINOUT - Pin Usage - 16 - 1 - - - SDAHOLD - SDA Hold Time - 20 - 2 - - SDAHOLDSelect - - DISABLE - Disabled - 0x0 - - - 75NS - 50-100ns hold time - 0x1 - - - 450NS - 300-600ns hold time - 0x2 - - - 600NS - 400-800ns hold time - 0x3 - - - - - SEXTTOEN - Slave SCL Low Extend Timeout - 23 - 1 - - - SPEED - Transfer Speed - 24 - 2 - - SPEEDSelect - - STANDARD_AND_FAST_MODE - Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz - 0x0 - - - FASTPLUS_MODE - Fast-mode Plus Upto 1MHz - 0x1 - - - HIGH_SPEED_MODE - High-speed mode Upto 3.4MHz - 0x2 - - - - - SCLSM - SCL Clock Stretch Mode - 27 - 1 - - - LOWTOUTEN - SCL Low Timeout Enable - 30 - 1 - - - - - CTRLB - I2CS Control B - 0x4 - 32 - 0x00000000 - - - SMEN - Smart Mode Enable - 8 - 1 - - - GCMD - PMBus Group Command - 9 - 1 - - - AACKEN - Automatic Address Acknowledge - 10 - 1 - - - AMODE - Address Mode - 14 - 2 - - - CMD - Command - 16 - 2 - - - ACKACT - Acknowledge Action - 18 - 1 - - - - - INTENCLR - I2CS Interrupt Enable Clear - 0x14 - 8 - 0x00 - - - PREC - Stop Received Interrupt Disable - 0 - 1 - - - AMATCH - Address Match Interrupt Disable - 1 - 1 - - - DRDY - Data Interrupt Disable - 2 - 1 - - - ERROR - Combined Error Interrupt Disable - 7 - 1 - - - - - INTENSET - I2CS Interrupt Enable Set - 0x16 - 8 - 0x00 - - - PREC - Stop Received Interrupt Enable - 0 - 1 - - - AMATCH - Address Match Interrupt Enable - 1 - 1 - - - DRDY - Data Interrupt Enable - 2 - 1 - - - ERROR - Combined Error Interrupt Enable - 7 - 1 - - - - - INTFLAG - I2CS Interrupt Flag Status and Clear - 0x18 - 8 - 0x00 - - - PREC - Stop Received Interrupt - 0 - 1 - - - AMATCH - Address Match Interrupt - 1 - 1 - - - DRDY - Data Interrupt - 2 - 1 - - - ERROR - Combined Error Interrupt - 7 - 1 - - - - - STATUS - I2CS Status - 0x1A - 16 - 0x0000 - - - BUSERR - Bus Error - 0 - 1 - - - COLL - Transmit Collision - 1 - 1 - - - RXNACK - Received Not Acknowledge - 2 - 1 - - - DIR - Read/Write Direction - 3 - 1 - - - SR - Repeated Start - 4 - 1 - - - LOWTOUT - SCL Low Timeout - 6 - 1 - - - CLKHOLD - Clock Hold - 7 - 1 - - - SEXTTOUT - Slave SCL Low Extend Timeout - 9 - 1 - - - HS - High Speed - 10 - 1 - - - - - SYNCBUSY - I2CS Synchronization Busy - 0x1C - 32 - read-only - 0x00000000 - - - SWRST - Software Reset Synchronization Busy - 0 - 1 - - - ENABLE - SERCOM Enable Synchronization Busy - 1 - 1 - - - - - ADDR - I2CS Address - 0x24 - 32 - 0x00000000 - - - GENCEN - General Call Address Enable - 0 - 1 - - - ADDR - Address Value - 1 - 10 - - - TENBITEN - Ten Bit Addressing Enable - 15 - 1 - - - ADDRMASK - Address Mask - 17 - 10 - - - - - DATA - I2CS Data - 0x28 - 8 - 0x00 - - - DATA - Data Value - 0 - 8 - - - - - - SPIS - SPI Slave Mode - I2CM - SercomSpis - 0x0 - - CTRLA - SPIS Control A - 0x0 - 32 - 0x00000000 - - - SWRST - Software Reset - 0 - 1 - - - ENABLE - Enable - 1 - 1 - - - MODE - Operating Mode - 2 - 3 - - MODESelect - - USART_EXT_CLK - USART with external clock - 0x0 - - - USART_INT_CLK - USART with internal clock - 0x1 - - - SPI_SLAVE - SPI in slave operation - 0x2 - - - SPI_MASTER - SPI in master operation - 0x3 - - - I2C_SLAVE - I2C slave operation - 0x4 - - - I2C_MASTER - I2C master operation - 0x5 - - - - - RUNSTDBY - Run during Standby - 7 - 1 - - - IBON - Immediate Buffer Overflow Notification - 8 - 1 - - - DOPO - Data Out Pinout - 16 - 2 - - DOPOSelect - - PAD0 - DO on PAD[0], SCK on PAD[1] and SS on PAD[2] - 0x0 - - - PAD1 - DO on PAD[2], SCK on PAD[3] and SS on PAD[1] - 0x1 - - - PAD2 - DO on PAD[3], SCK on PAD[1] and SS on PAD[2] - 0x2 - - - PAD3 - DO on PAD[0], SCK on PAD[3] and SS on PAD[1] - 0x3 - - - - - DIPO - Data In Pinout - 20 - 2 - - DIPOSelect - - PAD0 - SERCOM PAD[0] - 0x0 - - - PAD1 - SERCOM PAD[1] - 0x1 - - - PAD2 - SERCOM PAD[2] - 0x2 - - - PAD3 - SERCOM PAD[3] - 0x3 - - - - - FORM - Frame Format - 24 - 4 - - FORMSelect - - SPI_FRAME - SPI Frame - 0x0 - - - SPI_FRAME_WITH_ADDR - SPI Frame with Addr - 0x2 - - - - - CPHA - Clock Phase - 28 - 1 - - CPHASelect - - LEADING_EDGE - The data is sampled on a leading SCK edge and changed on a trailing SCK edge - 0x0 - - - TRAILING_EDGE - The data is sampled on a trailing SCK edge and changed on a leading SCK edge - 0x1 - - - - - CPOL - Clock Polarity - 29 - 1 - - CPOLSelect - - IDLE_LOW - SCK is low when idle - 0x0 - - - IDLE_HIGH - SCK is high when idle - 0x1 - - - - - DORD - Data Order - 30 - 1 - - DORDSelect - - MSB - MSB is transferred first - 0x0 - - - LSB - LSB is transferred first - 0x1 - - - - - - - CTRLB - SPIS Control B - 0x4 - 32 - 0x00000000 - - - CHSIZE - Character Size - 0 - 3 - - CHSIZESelect - - 8_BIT - 8 bits - 0x0 - - - 9_BIT - 9 bits - 0x1 - - - - - PLOADEN - Data Preload Enable - 6 - 1 - - - SSDE - Slave Select Low Detect Enable - 9 - 1 - - - MSSEN - Master Slave Select Enable - 13 - 1 - - - AMODE - Address Mode - 14 - 2 - - AMODESelect - - MASK - SPI Address mask - 0x0 - - - 2_ADDRESSES - Two unique Addressess - 0x1 - - - RANGE - Address Range - 0x2 - - - - - RXEN - Receiver Enable - 17 - 1 - - - - - BAUD - SPIS Baud Rate - 0xC - 8 - 0x00 - - - BAUD - Baud Rate Value - 0 - 8 - - - - - INTENCLR - SPIS Interrupt Enable Clear - 0x14 - 8 - 0x00 - - - DRE - Data Register Empty Interrupt Disable - 0 - 1 - - - TXC - Transmit Complete Interrupt Disable - 1 - 1 - - - RXC - Receive Complete Interrupt Disable - 2 - 1 - - - SSL - Slave Select Low Interrupt Disable - 3 - 1 - - - ERROR - Combined Error Interrupt Disable - 7 - 1 - - - - - INTENSET - SPIS Interrupt Enable Set - 0x16 - 8 - 0x00 - - - DRE - Data Register Empty Interrupt Enable - 0 - 1 - - - TXC - Transmit Complete Interrupt Enable - 1 - 1 - - - RXC - Receive Complete Interrupt Enable - 2 - 1 - - - SSL - Slave Select Low Interrupt Enable - 3 - 1 - - - ERROR - Combined Error Interrupt Enable - 7 - 1 - - - - - INTFLAG - SPIS Interrupt Flag Status and Clear - 0x18 - 8 - 0x00 - - - DRE - Data Register Empty Interrupt - 0 - 1 - - - TXC - Transmit Complete Interrupt - 1 - 1 - - - RXC - Receive Complete Interrupt - 2 - 1 - - - SSL - Slave Select Low Interrupt Flag - 3 - 1 - - - ERROR - Combined Error Interrupt - 7 - 1 - - - - - STATUS - SPIS Status - 0x1A - 16 - 0x0000 - - - BUFOVF - Buffer Overflow - 2 - 1 - - - - - SYNCBUSY - SPIS Synchronization Busy - 0x1C - 32 - read-only - 0x00000000 - - - SWRST - Software Reset Synchronization Busy - 0 - 1 - - - ENABLE - SERCOM Enable Synchronization Busy - 1 - 1 - - - CTRLB - CTRLB Synchronization Busy - 2 - 1 - - - - - ADDR - SPIS Address - 0x24 - 32 - 0x00000000 - - - ADDR - Address Value - 0 - 8 - - - ADDRMASK - Address Mask - 16 - 8 - - - - - DATA - SPIS Data - 0x28 - 32 - 0x00000000 - - - DATA - Data Value - 0 - 9 - - - - - DBGCTRL - SPIS Debug Control - 0x30 - 8 - 0x00 - - - DBGSTOP - Debug Mode - 0 - 1 - - - - - - SPIM - SPI Master Mode - I2CM - SercomSpim - 0x0 - - CTRLA - SPIM Control A - 0x0 - 32 - 0x00000000 - - - SWRST - Software Reset - 0 - 1 - - - ENABLE - Enable - 1 - 1 - - - MODE - Operating Mode - 2 - 3 - - MODESelect - - USART_EXT_CLK - USART with external clock - 0x0 - - - USART_INT_CLK - USART with internal clock - 0x1 - - - SPI_SLAVE - SPI in slave operation - 0x2 - - - SPI_MASTER - SPI in master operation - 0x3 - - - I2C_SLAVE - I2C slave operation - 0x4 - - - I2C_MASTER - I2C master operation - 0x5 - - - - - RUNSTDBY - Run during Standby - 7 - 1 - - - IBON - Immediate Buffer Overflow Notification - 8 - 1 - - - DOPO - Data Out Pinout - 16 - 2 - - DOPOSelect - - PAD0 - DO on PAD[0], SCK on PAD[1] and SS on PAD[2] - 0x0 - - - PAD1 - DO on PAD[2], SCK on PAD[3] and SS on PAD[1] - 0x1 - - - PAD2 - DO on PAD[3], SCK on PAD[1] and SS on PAD[2] - 0x2 - - - PAD3 - DO on PAD[0], SCK on PAD[3] and SS on PAD[1] - 0x3 - - - - - DIPO - Data In Pinout - 20 - 2 - - DIPOSelect - - PAD0 - SERCOM PAD[0] - 0x0 - - - PAD1 - SERCOM PAD[1] - 0x1 - - - PAD2 - SERCOM PAD[2] - 0x2 - - - PAD3 - SERCOM PAD[3] - 0x3 - - - - - FORM - Frame Format - 24 - 4 - - FORMSelect - - SPI_FRAME - SPI Frame - 0x0 - - - SPI_FRAME_WITH_ADDR - SPI Frame with Addr - 0x2 - - - - - CPHA - Clock Phase - 28 - 1 - - CPHASelect - - LEADING_EDGE - The data is sampled on a leading SCK edge and changed on a trailing SCK edge - 0x0 - - - TRAILING_EDGE - The data is sampled on a trailing SCK edge and changed on a leading SCK edge - 0x1 - - - - - CPOL - Clock Polarity - 29 - 1 - - CPOLSelect - - IDLE_LOW - SCK is low when idle - 0x0 - - - IDLE_HIGH - SCK is high when idle - 0x1 - - - - - DORD - Data Order - 30 - 1 - - DORDSelect - - MSB - MSB is transferred first - 0x0 - - - LSB - LSB is transferred first - 0x1 - - - - - - - CTRLB - SPIM Control B - 0x4 - 32 - 0x00000000 - - - CHSIZE - Character Size - 0 - 3 - - CHSIZESelect - - 8_BIT - 8 bits - 0x0 - - - 9_BIT - 9 bits - 0x1 - - - - - PLOADEN - Data Preload Enable - 6 - 1 - - - SSDE - Slave Select Low Detect Enable - 9 - 1 - - - MSSEN - Master Slave Select Enable - 13 - 1 - - - AMODE - Address Mode - 14 - 2 - - AMODESelect - - MASK - SPI Address mask - 0x0 - - - 2_ADDRESSES - Two unique Addressess - 0x1 - - - RANGE - Address Range - 0x2 - - - - - RXEN - Receiver Enable - 17 - 1 - - - - - BAUD - SPIM Baud Rate - 0xC - 8 - 0x00 - - - BAUD - Baud Rate Value - 0 - 8 - - - - - INTENCLR - SPIM Interrupt Enable Clear - 0x14 - 8 - 0x00 - - - DRE - Data Register Empty Interrupt Disable - 0 - 1 - - - TXC - Transmit Complete Interrupt Disable - 1 - 1 - - - RXC - Receive Complete Interrupt Disable - 2 - 1 - - - SSL - Slave Select Low Interrupt Disable - 3 - 1 - - - ERROR - Combined Error Interrupt Disable - 7 - 1 - - - - - INTENSET - SPIM Interrupt Enable Set - 0x16 - 8 - 0x00 - - - DRE - Data Register Empty Interrupt Enable - 0 - 1 - - - TXC - Transmit Complete Interrupt Enable - 1 - 1 - - - RXC - Receive Complete Interrupt Enable - 2 - 1 - - - SSL - Slave Select Low Interrupt Enable - 3 - 1 - - - ERROR - Combined Error Interrupt Enable - 7 - 1 - - - - - INTFLAG - SPIM Interrupt Flag Status and Clear - 0x18 - 8 - 0x00 - - - DRE - Data Register Empty Interrupt - 0 - 1 - - - TXC - Transmit Complete Interrupt - 1 - 1 - - - RXC - Receive Complete Interrupt - 2 - 1 - - - SSL - Slave Select Low Interrupt Flag - 3 - 1 - - - ERROR - Combined Error Interrupt - 7 - 1 - - - - - STATUS - SPIM Status - 0x1A - 16 - 0x0000 - - - BUFOVF - Buffer Overflow - 2 - 1 - - - - - SYNCBUSY - SPIM Synchronization Busy - 0x1C - 32 - read-only - 0x00000000 - - - SWRST - Software Reset Synchronization Busy - 0 - 1 - - - ENABLE - SERCOM Enable Synchronization Busy - 1 - 1 - - - CTRLB - CTRLB Synchronization Busy - 2 - 1 - - - - - ADDR - SPIM Address - 0x24 - 32 - 0x00000000 - - - ADDR - Address Value - 0 - 8 - - - ADDRMASK - Address Mask - 16 - 8 - - - - - DATA - SPIM Data - 0x28 - 32 - 0x00000000 - - - DATA - Data Value - 0 - 9 - - - - - DBGCTRL - SPIM Debug Control - 0x30 - 8 - 0x00 - - - DBGSTOP - Debug Mode - 0 - 1 - - - - - - USART_EXT - USART EXTERNAL CLOCK Mode - I2CM - SercomUsart_ext - 0x0 - - CTRLA - USART_EXT Control A - 0x0 - 32 - 0x00000000 - - - SWRST - Software Reset - 0 - 1 - - - ENABLE - Enable - 1 - 1 - - - MODE - Operating Mode - 2 - 3 - - MODESelect - - USART_EXT_CLK - USART with external clock - 0x0 - - - USART_INT_CLK - USART with internal clock - 0x1 - - - SPI_SLAVE - SPI in slave operation - 0x2 - - - SPI_MASTER - SPI in master operation - 0x3 - - - I2C_SLAVE - I2C slave operation - 0x4 - - - I2C_MASTER - I2C master operation - 0x5 - - - - - RUNSTDBY - Run during Standby - 7 - 1 - - - IBON - Immediate Buffer Overflow Notification - 8 - 1 - - - SAMPR - Sample - 13 - 3 - - SAMPRSelect - - 16X_ARITHMETIC - 16x over-sampling using arithmetic baudrate generation - 0x0 - - - 16X_FRACTIONAL - 16x over-sampling using fractional baudrate generation - 0x1 - - - 8X_ARITHMETIC - 8x over-sampling using arithmetic baudrate generation - 0x2 - - - 8X_FRACTIONAL - 8x over-sampling using fractional baudrate generation - 0x3 - - - 3X_ARITHMETIC - 3x over-sampling using arithmetic baudrate generation - 0x4 - - - - - TXPO - Transmit Data Pinout - 16 - 2 - - TXPOSelect - - PAD0 - SERCOM PAD[0] is used for data transmission - 0x0 - - - PAD2 - SERCOM PAD[2] is used for data transmission - 0x1 - - - - - RXPO - Receive Data Pinout - 20 - 2 - - RXPOSelect - - PAD0 - SERCOM PAD[0] is used for data reception - 0x0 - - - PAD1 - SERCOM PAD[1] is used for data reception - 0x1 - - - PAD2 - SERCOM PAD[2] is used for data reception - 0x2 - - - PAD3 - SERCOM PAD[3] is used for data reception - 0x3 - - - - - SAMPA - Sample Adjustment - 22 - 2 - - - FORM - Frame Format - 24 - 4 - - FORMSelect - - USART_FRAME_NO_PARITY - USART frame - 0x0 - - - USART_FRAME_WITH_PARITY - USART frame with parity - 0x1 - - - USART_FRAME_LIN_MASTER_MODE - LIN Master - Break and sync generation - 0x2 - - - USART_FRAME_AUTO_BAUD_NO_PARITY - Auto-baud - break detection and auto-baud - 0x4 - - - USART_FRAME_AUTO_BAUD_WITH_PARITY - Auto-baud - break detection and auto-baud with parity - 0x5 - - - - - CMODE - Communication Mode - 28 - 1 - - CMODESelect - - ASYNC - Asynchronous Communication - 0x0 - - - SYNC - Synchronous Communication - 0x1 - - - - - CPOL - Clock Polarity - 29 - 1 - - CPOLSelect - - IDLE_LOW - TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge - 0x0 - - - IDLE_HIGH - TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge - 0x1 - - - - - DORD - Data Order - 30 - 1 - - DORDSelect - - MSB - MSB is transmitted first - 0x0 - - - LSB - LSB is transmitted first - 0x1 - - - - - - - CTRLB - USART_EXT Control B - 0x4 - 32 - 0x00000000 - - - CHSIZE - Character Size - 0 - 3 - - CHSIZESelect - - 8_BIT - 8 Bits - 0x0 - - - 9_BIT - 9 Bits - 0x1 - - - 5_BIT - 5 Bits - 0x5 - - - 6_BIT - 6 Bits - 0x6 - - - 7_BIT - 7 Bits - 0x7 - - - - - SBMODE - Stop Bit Mode - 6 - 1 - - SBMODESelect - - 1_BIT - One Stop Bit - 0x0 - - - 2_BIT - Two Stop Bits - 0x1 - - - - - COLDEN - Collision Detection Enable - 8 - 1 - - - SFDE - Start of Frame Detection Enable - 9 - 1 - - - ENC - Encoding Format - 10 - 1 - - - PMODE - Parity Mode - 13 - 1 - - PMODESelect - - EVEN - Even Parity - 0x0 - - - ODD - Odd Parity - 0x1 - - - - - TXEN - Transmitter Enable - 16 - 1 - - - RXEN - Receiver Enable - 17 - 1 - - - LINCMD - LIN Command - 24 - 2 - - - - - CTRLC - USART_EXT Control C - 0x8 - 32 - 0x00000000 - - - GTIME - RS485 Guard Time - 0 - 3 - - - BRKLEN - LIN Master Break Length - 8 - 2 - - - HDRDLY - LIN Master Header Delay - 10 - 2 - - - - - BAUD - USART_EXT Baud Rate - 0xC - 16 - 0x0000 - - - BAUD - Baud Rate Value - 0 - 16 - - - - - BAUD_FRAC_MODE - USART_EXT Baud Rate - BAUD - 0xC - 16 - 0x0000 - - - BAUD - Baud Rate Value - 0 - 13 - - - FP - Fractional Part - 13 - 3 - - - - - BAUD_FRACFP_MODE - USART_EXT Baud Rate - BAUD - 0xC - 16 - 0x0000 - - - BAUD - Baud Rate Value - 0 - 13 - - - FP - Fractional Part - 13 - 3 - - - - - BAUD_USARTFP_MODE - USART_EXT Baud Rate - BAUD - 0xC - 16 - 0x0000 - - - BAUD - Baud Rate Value - 0 - 16 - - - - - RXPL - USART_EXT Receive Pulse Length - 0xE - 8 - 0x00 - - - RXPL - Receive Pulse Length - 0 - 8 - - - - - INTENCLR - USART_EXT Interrupt Enable Clear - 0x14 - 8 - 0x00 - - - DRE - Data Register Empty Interrupt Disable - 0 - 1 - - - TXC - Transmit Complete Interrupt Disable - 1 - 1 - - - RXC - Receive Complete Interrupt Disable - 2 - 1 - - - RXS - Receive Start Interrupt Disable - 3 - 1 - - - CTSIC - Clear To Send Input Change Interrupt Disable - 4 - 1 - - - RXBRK - Break Received Interrupt Disable - 5 - 1 - - - ERROR - Combined Error Interrupt Disable - 7 - 1 - - - - - INTENSET - USART_EXT Interrupt Enable Set - 0x16 - 8 - 0x00 - - - DRE - Data Register Empty Interrupt Enable - 0 - 1 - - - TXC - Transmit Complete Interrupt Enable - 1 - 1 - - - RXC - Receive Complete Interrupt Enable - 2 - 1 - - - RXS - Receive Start Interrupt Enable - 3 - 1 - - - CTSIC - Clear To Send Input Change Interrupt Enable - 4 - 1 - - - RXBRK - Break Received Interrupt Enable - 5 - 1 - - - ERROR - Combined Error Interrupt Enable - 7 - 1 - - - - - INTFLAG - USART_EXT Interrupt Flag Status and Clear - 0x18 - 8 - 0x00 - - - DRE - Data Register Empty Interrupt - 0 - 1 - - - TXC - Transmit Complete Interrupt - 1 - 1 - - - RXC - Receive Complete Interrupt - 2 - 1 - - - RXS - Receive Start Interrupt - 3 - 1 - - - CTSIC - Clear To Send Input Change Interrupt - 4 - 1 - - - RXBRK - Break Received Interrupt - 5 - 1 - - - ERROR - Combined Error Interrupt - 7 - 1 - - - - - STATUS - USART_EXT Status - 0x1A - 16 - 0x0000 - - - PERR - Parity Error - 0 - 1 - - - FERR - Frame Error - 1 - 1 - - - BUFOVF - Buffer Overflow - 2 - 1 - - - CTS - Clear To Send - 3 - 1 - - - ISF - Inconsistent Sync Field - 4 - 1 - - - COLL - Collision Detected - 5 - 1 - - - TXE - Transmitter Empty - 6 - 1 - - - - - SYNCBUSY - USART_EXT Synchronization Busy - 0x1C - 32 - read-only - 0x00000000 - - - SWRST - Software Reset Synchronization Busy - 0 - 1 - - - ENABLE - SERCOM Enable Synchronization Busy - 1 - 1 - - - CTRLB - CTRLB Synchronization Busy - 2 - 1 - - - - - DATA - USART_EXT Data - 0x28 - 16 - 0x0000 - - - DATA - Data Value - 0 - 9 - - - - - DBGCTRL - USART_EXT Debug Control - 0x30 - 8 - 0x00 - - - DBGSTOP - Debug Mode - 0 - 1 - - - - - - USART_INT - USART INTERNAL CLOCK Mode - I2CM - SercomUsart_int - 0x0 - - CTRLA - USART_INT Control A - 0x0 - 32 - 0x00000000 - - - SWRST - Software Reset - 0 - 1 - - - ENABLE - Enable - 1 - 1 - - - MODE - Operating Mode - 2 - 3 - - MODESelect - - USART_EXT_CLK - USART with external clock - 0x0 - - - USART_INT_CLK - USART with internal clock - 0x1 - - - SPI_SLAVE - SPI in slave operation - 0x2 - - - SPI_MASTER - SPI in master operation - 0x3 - - - I2C_SLAVE - I2C slave operation - 0x4 - - - I2C_MASTER - I2C master operation - 0x5 - - - - - RUNSTDBY - Run during Standby - 7 - 1 - - - IBON - Immediate Buffer Overflow Notification - 8 - 1 - - - SAMPR - Sample - 13 - 3 - - SAMPRSelect - - 16X_ARITHMETIC - 16x over-sampling using arithmetic baudrate generation - 0x0 - - - 16X_FRACTIONAL - 16x over-sampling using fractional baudrate generation - 0x1 - - - 8X_ARITHMETIC - 8x over-sampling using arithmetic baudrate generation - 0x2 - - - 8X_FRACTIONAL - 8x over-sampling using fractional baudrate generation - 0x3 - - - 3X_ARITHMETIC - 3x over-sampling using arithmetic baudrate generation - 0x4 - - - - - TXPO - Transmit Data Pinout - 16 - 2 - - TXPOSelect - - PAD0 - SERCOM PAD[0] is used for data transmission - 0x0 - - - PAD2 - SERCOM PAD[2] is used for data transmission - 0x1 - - - - - RXPO - Receive Data Pinout - 20 - 2 - - RXPOSelect - - PAD0 - SERCOM PAD[0] is used for data reception - 0x0 - - - PAD1 - SERCOM PAD[1] is used for data reception - 0x1 - - - PAD2 - SERCOM PAD[2] is used for data reception - 0x2 - - - PAD3 - SERCOM PAD[3] is used for data reception - 0x3 - - - - - SAMPA - Sample Adjustment - 22 - 2 - - - FORM - Frame Format - 24 - 4 - - FORMSelect - - USART_FRAME_NO_PARITY - USART frame - 0x0 - - - USART_FRAME_WITH_PARITY - USART frame with parity - 0x1 - - - USART_FRAME_LIN_MASTER_MODE - LIN Master - Break and sync generation - 0x2 - - - USART_FRAME_AUTO_BAUD_NO_PARITY - Auto-baud - break detection and auto-baud - 0x4 - - - USART_FRAME_AUTO_BAUD_WITH_PARITY - Auto-baud - break detection and auto-baud with parity - 0x5 - - - - - CMODE - Communication Mode - 28 - 1 - - CMODESelect - - ASYNC - Asynchronous Communication - 0x0 - - - SYNC - Synchronous Communication - 0x1 - - - - - CPOL - Clock Polarity - 29 - 1 - - CPOLSelect - - IDLE_LOW - TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge - 0x0 - - - IDLE_HIGH - TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge - 0x1 - - - - - DORD - Data Order - 30 - 1 - - DORDSelect - - MSB - MSB is transmitted first - 0x0 - - - LSB - LSB is transmitted first - 0x1 - - - - - - - CTRLB - USART_INT Control B - 0x4 - 32 - 0x00000000 - - - CHSIZE - Character Size - 0 - 3 - - CHSIZESelect - - 8_BIT - 8 Bits - 0x0 - - - 9_BIT - 9 Bits - 0x1 - - - 5_BIT - 5 Bits - 0x5 - - - 6_BIT - 6 Bits - 0x6 - - - 7_BIT - 7 Bits - 0x7 - - - - - SBMODE - Stop Bit Mode - 6 - 1 - - SBMODESelect - - 1_BIT - One Stop Bit - 0x0 - - - 2_BIT - Two Stop Bits - 0x1 - - - - - COLDEN - Collision Detection Enable - 8 - 1 - - - SFDE - Start of Frame Detection Enable - 9 - 1 - - - ENC - Encoding Format - 10 - 1 - - - PMODE - Parity Mode - 13 - 1 - - PMODESelect - - EVEN - Even Parity - 0x0 - - - ODD - Odd Parity - 0x1 - - - - - TXEN - Transmitter Enable - 16 - 1 - - - RXEN - Receiver Enable - 17 - 1 - - - LINCMD - LIN Command - 24 - 2 - - - - - CTRLC - USART_INT Control C - 0x8 - 32 - 0x00000000 - - - GTIME - RS485 Guard Time - 0 - 3 - - - BRKLEN - LIN Master Break Length - 8 - 2 - - - HDRDLY - LIN Master Header Delay - 10 - 2 - - - - - BAUD - USART_INT Baud Rate - 0xC - 16 - 0x0000 - - - BAUD - Baud Rate Value - 0 - 16 - - - - - BAUD_FRAC_MODE - USART_INT Baud Rate - BAUD - 0xC - 16 - 0x0000 - - - BAUD - Baud Rate Value - 0 - 13 - - - FP - Fractional Part - 13 - 3 - - - - - BAUD_FRACFP_MODE - USART_INT Baud Rate - BAUD - 0xC - 16 - 0x0000 - - - BAUD - Baud Rate Value - 0 - 13 - - - FP - Fractional Part - 13 - 3 - - - - - BAUD_USARTFP_MODE - USART_INT Baud Rate - BAUD - 0xC - 16 - 0x0000 - - - BAUD - Baud Rate Value - 0 - 16 - - - - - RXPL - USART_INT Receive Pulse Length - 0xE - 8 - 0x00 - - - RXPL - Receive Pulse Length - 0 - 8 - - - - - INTENCLR - USART_INT Interrupt Enable Clear - 0x14 - 8 - 0x00 - - - DRE - Data Register Empty Interrupt Disable - 0 - 1 - - - TXC - Transmit Complete Interrupt Disable - 1 - 1 - - - RXC - Receive Complete Interrupt Disable - 2 - 1 - - - RXS - Receive Start Interrupt Disable - 3 - 1 - - - CTSIC - Clear To Send Input Change Interrupt Disable - 4 - 1 - - - RXBRK - Break Received Interrupt Disable - 5 - 1 - - - ERROR - Combined Error Interrupt Disable - 7 - 1 - - - - - INTENSET - USART_INT Interrupt Enable Set - 0x16 - 8 - 0x00 - - - DRE - Data Register Empty Interrupt Enable - 0 - 1 - - - TXC - Transmit Complete Interrupt Enable - 1 - 1 - - - RXC - Receive Complete Interrupt Enable - 2 - 1 - - - RXS - Receive Start Interrupt Enable - 3 - 1 - - - CTSIC - Clear To Send Input Change Interrupt Enable - 4 - 1 - - - RXBRK - Break Received Interrupt Enable - 5 - 1 - - - ERROR - Combined Error Interrupt Enable - 7 - 1 - - - - - INTFLAG - USART_INT Interrupt Flag Status and Clear - 0x18 - 8 - 0x00 - - - DRE - Data Register Empty Interrupt - 0 - 1 - - - TXC - Transmit Complete Interrupt - 1 - 1 - - - RXC - Receive Complete Interrupt - 2 - 1 - - - RXS - Receive Start Interrupt - 3 - 1 - - - CTSIC - Clear To Send Input Change Interrupt - 4 - 1 - - - RXBRK - Break Received Interrupt - 5 - 1 - - - ERROR - Combined Error Interrupt - 7 - 1 - - - - - STATUS - USART_INT Status - 0x1A - 16 - 0x0000 - - - PERR - Parity Error - 0 - 1 - - - FERR - Frame Error - 1 - 1 - - - BUFOVF - Buffer Overflow - 2 - 1 - - - CTS - Clear To Send - 3 - 1 - - - ISF - Inconsistent Sync Field - 4 - 1 - - - COLL - Collision Detected - 5 - 1 - - - TXE - Transmitter Empty - 6 - 1 - - - - - SYNCBUSY - USART_INT Synchronization Busy - 0x1C - 32 - read-only - 0x00000000 - - - SWRST - Software Reset Synchronization Busy - 0 - 1 - - - ENABLE - SERCOM Enable Synchronization Busy - 1 - 1 - - - CTRLB - CTRLB Synchronization Busy - 2 - 1 - - - - - DATA - USART_INT Data - 0x28 - 16 - 0x0000 - - - DATA - Data Value - 0 - 9 - - - - - DBGCTRL - USART_INT Debug Control - 0x30 - 8 - 0x00 - - - DBGSTOP - Debug Mode - 0 - 1 - - - - - - - - SERCOM1 - 0x42000800 - - SERCOM1 - 10 - - - - SERCOM2 - 0x42000C00 - - SERCOM2 - 11 - - - - SERCOM3 - 0x42001000 - - SERCOM3 - 12 - - - - SERCOM4 - 0x42001400 - - SERCOM4 - 13 - - - - SERCOM5 - 0x42001800 - - SERCOM5 - 14 - - - - SUPC - U21172.1.1 - Supply Controller - SUPC - SUPC_ - 0x40001800 - - 0 - 0x20 - registers - - - - INTENCLR - Interrupt Enable Clear - 0x0 - 32 - 0x00000000 - - - BODVDDRDY - BODVDD Ready - 0 - 1 - - - BODVDDDET - BODVDD Detection - 1 - 1 - - - BVDDSRDY - BODVDD Synchronization Ready - 2 - 1 - - - BODCORERDY - BODCORE Ready - 3 - 1 - - - BODCOREDET - BODCORE Detection - 4 - 1 - - - BCORESRDY - BODCORE Synchronization Ready - 5 - 1 - - - - - INTENSET - Interrupt Enable Set - 0x4 - 32 - 0x00000000 - - - BODVDDRDY - BODVDD Ready - 0 - 1 - - - BODVDDDET - BODVDD Detection - 1 - 1 - - - BVDDSRDY - BODVDD Synchronization Ready - 2 - 1 - - - BODCORERDY - BODCORE Ready - 3 - 1 - - - BODCOREDET - BODCORE Detection - 4 - 1 - - - BCORESRDY - BODCORE Synchronization Ready - 5 - 1 - - - - - INTFLAG - Interrupt Flag Status and Clear - 0x8 - 32 - 0x00000000 - - - BODVDDRDY - BODVDD Ready - 0 - 1 - - - BODVDDDET - BODVDD Detection - 1 - 1 - - - BVDDSRDY - BODVDD Synchronization Ready - 2 - 1 - - - BODCORERDY - BODCORE Ready - 3 - 1 - - - BODCOREDET - BODCORE Detection - 4 - 1 - - - BCORESRDY - BODCORE Synchronization Ready - 5 - 1 - - - - - STATUS - Power and Clocks Status - 0xC - 32 - read-only - 0x00000000 - - - BODVDDRDY - BODVDD Ready - 0 - 1 - - - BODVDDDET - BODVDD Detection - 1 - 1 - - - BVDDSRDY - BODVDD Synchronization Ready - 2 - 1 - - - BODCORERDY - BODCORE Ready - 3 - 1 - - - BODCOREDET - BODCORE Detection - 4 - 1 - - - BCORESRDY - BODCORE Synchronization Ready - 5 - 1 - - - - - BODVDD - BODVDD Control - 0x10 - 32 - 0x00000000 - - - ENABLE - Enable - 1 - 1 - - - HYST - Hysteresis Enable - 2 - 1 - - - ACTION - Action when Threshold Crossed - 3 - 2 - - ACTIONSelect - - NONE - No action - 0x0 - - - RESET - The BODVDD generates a reset - 0x1 - - - INT - The BODVDD generates an interrupt - 0x2 - - - - - STDBYCFG - Configuration in Standby mode - 5 - 1 - - - RUNSTDBY - Run during Standby - 6 - 1 - - - ACTCFG - Configuration in Active mode - 8 - 1 - - - PSEL - Prescaler Select - 12 - 4 - - PSELSelect - - DIV2 - Divide clock by 2 - 0x0 - - - DIV4 - Divide clock by 4 - 0x1 - - - DIV8 - Divide clock by 8 - 0x2 - - - DIV16 - Divide clock by 16 - 0x3 - - - DIV32 - Divide clock by 32 - 0x4 - - - DIV64 - Divide clock by 64 - 0x5 - - - DIV128 - Divide clock by 128 - 0x6 - - - DIV256 - Divide clock by 256 - 0x7 - - - DIV512 - Divide clock by 512 - 0x8 - - - DIV1024 - Divide clock by 1024 - 0x9 - - - DIV2048 - Divide clock by 2048 - 0xA - - - DIV4096 - Divide clock by 4096 - 0xB - - - DIV8192 - Divide clock by 8192 - 0xC - - - DIV16384 - Divide clock by 16384 - 0xD - - - DIV32768 - Divide clock by 32768 - 0xE - - - DIV65536 - Divide clock by 65536 - 0xF - - - - - LEVEL - Threshold Level for VDD - 16 - 6 - - - - - BODCORE - BODCORE Control - 0x14 - 32 - 0x00000000 - - - ENABLE - Enable - 1 - 1 - - - HYST - Hysteresis Enable - 2 - 1 - - - ACTION - Action when Threshold Crossed - 3 - 2 - - ACTIONSelect - - NONE - No action - 0x0 - - - RESET - The BODCORE generates a reset - 0x1 - - - INT - The BODCORE generates an interrupt - 0x2 - - - - - STDBYCFG - Configuration in Standby mode - 5 - 1 - - - RUNSTDBY - Run during Standby - 6 - 1 - - - ACTCFG - Configuration in Active mode - 8 - 1 - - - PSEL - Prescaler Select - 12 - 4 - - PSELSelect - - DIV2 - Divide clock by 2 - 0x0 - - - DIV4 - Divide clock by 4 - 0x1 - - - DIV8 - Divide clock by 8 - 0x2 - - - DIV16 - Divide clock by 16 - 0x3 - - - DIV32 - Divide clock by 32 - 0x4 - - - DIV64 - Divide clock by 64 - 0x5 - - - DIV128 - Divide clock by 128 - 0x6 - - - DIV256 - Divide clock by 256 - 0x7 - - - DIV512 - Divide clock by 512 - 0x8 - - - DIV1024 - Divide clock by 1024 - 0x9 - - - DIV2048 - Divide clock by 2048 - 0xA - - - DIV4096 - Divide clock by 4096 - 0xB - - - DIV8192 - Divide clock by 8192 - 0xC - - - DIV16384 - Divide clock by 16384 - 0xD - - - DIV32768 - Divide clock by 32768 - 0xE - - - DIV65536 - Divide clock by 65536 - 0xF - - - - - LEVEL - Threshold Level - 16 - 6 - - - - - VREG - VREG Control - 0x18 - 32 - 0x00000000 - - - ENABLE - Enable - 1 - 1 - - - RUNSTDBY - Run during Standby - 6 - 1 - - - - - VREF - VREF Control - 0x1C - 32 - 0x00000000 - - - TSEN - Temperature Sensor Output Enable - 1 - 1 - - - VREFOE - Voltage Reference Output Enable - 2 - 1 - - - RUNSTDBY - Run during Standby - 6 - 1 - - - ONDEMAND - On Demand Contrl - 7 - 1 - - - SEL - Voltage Reference Selection - 16 - 4 - - SELSelect - - 1V024 - 1.024V voltage reference typical value - 0x0 - - - 2V048 - 2.048V voltage reference typical value - 0x2 - - - 4V096 - 4.096V voltage reference typical value - 0x3 - - - - - - - - - TC0 - U22492.0.0 - Basic Timer Counter - TC - TC_ - 0x42003000 - - 0 - 0x38 - registers - - - TC0 - 20 - - - - COUNT8 - 8-bit Counter Mode - TcCount8 - 0x0 - - CTRLA - Control A - 0x0 - 32 - 0x00000000 - - - SWRST - Software Reset - 0 - 1 - - - ENABLE - Enable - 1 - 1 - - - MODE - Timer Counter Mode - 2 - 2 - - MODESelect - - COUNT16 - Counter in 16-bit mode - 0 - - - COUNT8 - Counter in 8-bit mode - 1 - - - COUNT32 - Counter in 32-bit mode - 2 - - - - - PRESCSYNC - Prescaler and Counter Synchronization - 4 - 2 - - PRESCSYNCSelect - - GCLK - Reload or reset the counter on next generic clock - 0 - - - PRESC - Reload or reset the counter on next prescaler clock - 1 - - - RESYNC - Reload or reset the counter on next generic clock and reset the prescaler counter - 2 - - - - - RUNSTDBY - Run during Standby - 6 - 1 - - - ONDEMAND - Clock On Demand - 7 - 1 - - - PRESCALER - Prescaler - 8 - 3 - - PRESCALERSelect - - DIV1 - Prescaler: GCLK_TC - 0 - - - DIV2 - Prescaler: GCLK_TC/2 - 1 - - - DIV4 - Prescaler: GCLK_TC/4 - 2 - - - DIV8 - Prescaler: GCLK_TC/8 - 3 - - - DIV16 - Prescaler: GCLK_TC/16 - 4 - - - DIV64 - Prescaler: GCLK_TC/64 - 5 - - - DIV256 - Prescaler: GCLK_TC/256 - 6 - - - DIV1024 - Prescaler: GCLK_TC/1024 - 7 - - - - - ALOCK - Auto Lock - 11 - 1 - - - CAPTEN0 - Capture Channel 0 Enable - 16 - 1 - - - CAPTEN1 - Capture Channel 1 Enable - 17 - 1 - - - COPEN0 - Capture On Pin 0 Enable - 20 - 1 - - - COPEN1 - Capture On Pin 1 Enable - 21 - 1 - - - - - CTRLBCLR - Control B Clear - 0x4 - 8 - 0x00 - - - DIR - Counter Direction - 0 - 1 - - - LUPD - Lock Update - 1 - 1 - - - ONESHOT - One-Shot on Counter - 2 - 1 - - - CMD - Command - 5 - 3 - - CMDSelect - - NONE - No action - 0 - - - RETRIGGER - Force a start, restart or retrigger - 1 - - - STOP - Force a stop - 2 - - - UPDATE - Force update of double-buffered register - 3 - - - READSYNC - Force a read synchronization of COUNT - 4 - - - DMAOS - One-shot DMA trigger - 5 - - - - - - - CTRLBSET - Control B Set - 0x5 - 8 - 0x00 - - - DIR - Counter Direction - 0 - 1 - - - LUPD - Lock Update - 1 - 1 - - - ONESHOT - One-Shot on Counter - 2 - 1 - - - CMD - Command - 5 - 3 - - CMDSelect - - NONE - No action - 0 - - - RETRIGGER - Force a start, restart or retrigger - 1 - - - STOP - Force a stop - 2 - - - UPDATE - Force update of double-buffered register - 3 - - - READSYNC - Force a read synchronization of COUNT - 4 - - - DMAOS - One-shot DMA trigger - 5 - - - - - - - EVCTRL - Event Control - 0x6 - 16 - 0x0000 - - - EVACT - Event Action - 0 - 3 - - EVACTSelect - - OFF - Event action disabled - 0 - - - RETRIGGER - Start, restart or retrigger TC on event - 1 - - - COUNT - Count on event - 2 - - - START - Start TC on event - 3 - - - STAMP - Time stamp capture - 4 - - - PPW - Period catured in CC0, pulse width in CC1 - 5 - - - PWP - Period catured in CC1, pulse width in CC0 - 6 - - - PW - Pulse width capture - 7 - - - - - TCINV - TC Event Input Polarity - 4 - 1 - - - TCEI - TC Event Enable - 5 - 1 - - - OVFEO - Event Output Enable - 8 - 1 - - - MCEO0 - MC Event Output Enable 0 - 12 - 1 - - - MCEO1 - MC Event Output Enable 1 - 13 - 1 - - - - - INTENCLR - Interrupt Enable Clear - 0x8 - 8 - 0x00 - - - OVF - OVF Interrupt Disable - 0 - 1 - - - ERR - ERR Interrupt Disable - 1 - 1 - - - MC0 - MC Interrupt Disable 0 - 4 - 1 - - - MC1 - MC Interrupt Disable 1 - 5 - 1 - - - - - INTENSET - Interrupt Enable Set - 0x9 - 8 - 0x00 - - - OVF - OVF Interrupt Enable - 0 - 1 - - - ERR - ERR Interrupt Enable - 1 - 1 - - - MC0 - MC Interrupt Enable 0 - 4 - 1 - - - MC1 - MC Interrupt Enable 1 - 5 - 1 - - - - - INTFLAG - Interrupt Flag Status and Clear - 0xA - 8 - 0x00 - - - OVF - OVF Interrupt Flag - 0 - 1 - - - ERR - ERR Interrupt Flag - 1 - 1 - - - MC0 - MC Interrupt Flag 0 - 4 - 1 - - - MC1 - MC Interrupt Flag 1 - 5 - 1 - - - - - STATUS - Status - 0xB - 8 - 0x01 - - - STOP - Stop Status Flag - 0 - 1 - - - SLAVE - Slave Status Flag - 1 - 1 - - - PERBUFV - Synchronization Busy Status - 3 - 1 - - - CCBUFV0 - Compare channel buffer 0 valid - 4 - 1 - - - CCBUFV1 - Compare channel buffer 1 valid - 5 - 1 - - - - - WAVE - Waveform Generation Control - 0xC - 8 - 0x00 - - - WAVEGEN - Waveform Generation Mode - 0 - 2 - - WAVEGENSelect - - NFRQ - Normal frequency - 0 - - - MFRQ - Match frequency - 1 - - - NPWM - Normal PWM - 2 - - - MPWM - Match PWM - 3 - - - - - - - DRVCTRL - Control C - 0xD - 8 - 0x00 - - - INVEN0 - Output Waveform Invert Enable 0 - 0 - 1 - - - INVEN1 - Output Waveform Invert Enable 1 - 1 - 1 - - - - - DBGCTRL - Debug Control - 0xF - 8 - 0x00 - - - DBGRUN - Run During Debug - 0 - 1 - - - - - SYNCBUSY - Synchronization Status - 0x10 - 32 - read-only - 0x00000000 - - - SWRST - swrst - 0 - 1 - - - ENABLE - enable - 1 - 1 - - - CTRLB - CTRLB - 2 - 1 - - - STATUS - STATUS - 3 - 1 - - - COUNT - Counter - 4 - 1 - - - PER - Period - 5 - 1 - - - CC0 - Compare Channel 0 - 6 - 1 - - - CC1 - Compare Channel 1 - 7 - 1 - - - - - COUNT - COUNT8 Count - 0x14 - 8 - 0x00 - - - COUNT - Counter Value - 0 - 8 - - - - - PER - COUNT8 Period - 0x1B - 8 - 0xFF - - - PER - Period Value - 0 - 8 - - - - - 2 - 1 - CC[%s] - COUNT8 Compare and Capture - 0x1C - 8 - 0x00 - - - CC - Counter/Compare Value - 0 - 8 - - - - - PERBUF - COUNT8 Period Buffer - 0x2F - 8 - 0xFF - - - PERBUF - Period Buffer Value - 0 - 8 - - - - - 2 - 1 - CCBUF[%s] - COUNT8 Compare and Capture Buffer - 0x30 - 8 - 0x00 - - - CCBUF - Counter/Compare Buffer Value - 0 - 8 - - - - - - COUNT16 - 16-bit Counter Mode - COUNT8 - TcCount16 - 0x0 - - CTRLA - Control A - 0x0 - 32 - 0x00000000 - - - SWRST - Software Reset - 0 - 1 - - - ENABLE - Enable - 1 - 1 - - - MODE - Timer Counter Mode - 2 - 2 - - MODESelect - - COUNT16 - Counter in 16-bit mode - 0 - - - COUNT8 - Counter in 8-bit mode - 1 - - - COUNT32 - Counter in 32-bit mode - 2 - - - - - PRESCSYNC - Prescaler and Counter Synchronization - 4 - 2 - - PRESCSYNCSelect - - GCLK - Reload or reset the counter on next generic clock - 0 - - - PRESC - Reload or reset the counter on next prescaler clock - 1 - - - RESYNC - Reload or reset the counter on next generic clock and reset the prescaler counter - 2 - - - - - RUNSTDBY - Run during Standby - 6 - 1 - - - ONDEMAND - Clock On Demand - 7 - 1 - - - PRESCALER - Prescaler - 8 - 3 - - PRESCALERSelect - - DIV1 - Prescaler: GCLK_TC - 0 - - - DIV2 - Prescaler: GCLK_TC/2 - 1 - - - DIV4 - Prescaler: GCLK_TC/4 - 2 - - - DIV8 - Prescaler: GCLK_TC/8 - 3 - - - DIV16 - Prescaler: GCLK_TC/16 - 4 - - - DIV64 - Prescaler: GCLK_TC/64 - 5 - - - DIV256 - Prescaler: GCLK_TC/256 - 6 - - - DIV1024 - Prescaler: GCLK_TC/1024 - 7 - - - - - ALOCK - Auto Lock - 11 - 1 - - - CAPTEN0 - Capture Channel 0 Enable - 16 - 1 - - - CAPTEN1 - Capture Channel 1 Enable - 17 - 1 - - - COPEN0 - Capture On Pin 0 Enable - 20 - 1 - - - COPEN1 - Capture On Pin 1 Enable - 21 - 1 - - - - - CTRLBCLR - Control B Clear - 0x4 - 8 - 0x00 - - - DIR - Counter Direction - 0 - 1 - - - LUPD - Lock Update - 1 - 1 - - - ONESHOT - One-Shot on Counter - 2 - 1 - - - CMD - Command - 5 - 3 - - CMDSelect - - NONE - No action - 0 - - - RETRIGGER - Force a start, restart or retrigger - 1 - - - STOP - Force a stop - 2 - - - UPDATE - Force update of double-buffered register - 3 - - - READSYNC - Force a read synchronization of COUNT - 4 - - - DMAOS - One-shot DMA trigger - 5 - - - - - - - CTRLBSET - Control B Set - 0x5 - 8 - 0x00 - - - DIR - Counter Direction - 0 - 1 - - - LUPD - Lock Update - 1 - 1 - - - ONESHOT - One-Shot on Counter - 2 - 1 - - - CMD - Command - 5 - 3 - - CMDSelect - - NONE - No action - 0 - - - RETRIGGER - Force a start, restart or retrigger - 1 - - - STOP - Force a stop - 2 - - - UPDATE - Force update of double-buffered register - 3 - - - READSYNC - Force a read synchronization of COUNT - 4 - - - DMAOS - One-shot DMA trigger - 5 - - - - - - - EVCTRL - Event Control - 0x6 - 16 - 0x0000 - - - EVACT - Event Action - 0 - 3 - - EVACTSelect - - OFF - Event action disabled - 0 - - - RETRIGGER - Start, restart or retrigger TC on event - 1 - - - COUNT - Count on event - 2 - - - START - Start TC on event - 3 - - - STAMP - Time stamp capture - 4 - - - PPW - Period catured in CC0, pulse width in CC1 - 5 - - - PWP - Period catured in CC1, pulse width in CC0 - 6 - - - PW - Pulse width capture - 7 - - - - - TCINV - TC Event Input Polarity - 4 - 1 - - - TCEI - TC Event Enable - 5 - 1 - - - OVFEO - Event Output Enable - 8 - 1 - - - MCEO0 - MC Event Output Enable 0 - 12 - 1 - - - MCEO1 - MC Event Output Enable 1 - 13 - 1 - - - - - INTENCLR - Interrupt Enable Clear - 0x8 - 8 - 0x00 - - - OVF - OVF Interrupt Disable - 0 - 1 - - - ERR - ERR Interrupt Disable - 1 - 1 - - - MC0 - MC Interrupt Disable 0 - 4 - 1 - - - MC1 - MC Interrupt Disable 1 - 5 - 1 - - - - - INTENSET - Interrupt Enable Set - 0x9 - 8 - 0x00 - - - OVF - OVF Interrupt Enable - 0 - 1 - - - ERR - ERR Interrupt Enable - 1 - 1 - - - MC0 - MC Interrupt Enable 0 - 4 - 1 - - - MC1 - MC Interrupt Enable 1 - 5 - 1 - - - - - INTFLAG - Interrupt Flag Status and Clear - 0xA - 8 - 0x00 - - - OVF - OVF Interrupt Flag - 0 - 1 - - - ERR - ERR Interrupt Flag - 1 - 1 - - - MC0 - MC Interrupt Flag 0 - 4 - 1 - - - MC1 - MC Interrupt Flag 1 - 5 - 1 - - - - - STATUS - Status - 0xB - 8 - 0x01 - - - STOP - Stop Status Flag - 0 - 1 - - - SLAVE - Slave Status Flag - 1 - 1 - - - PERBUFV - Synchronization Busy Status - 3 - 1 - - - CCBUFV0 - Compare channel buffer 0 valid - 4 - 1 - - - CCBUFV1 - Compare channel buffer 1 valid - 5 - 1 - - - - - WAVE - Waveform Generation Control - 0xC - 8 - 0x00 - - - WAVEGEN - Waveform Generation Mode - 0 - 2 - - WAVEGENSelect - - NFRQ - Normal frequency - 0 - - - MFRQ - Match frequency - 1 - - - NPWM - Normal PWM - 2 - - - MPWM - Match PWM - 3 - - - - - - - DRVCTRL - Control C - 0xD - 8 - 0x00 - - - INVEN0 - Output Waveform Invert Enable 0 - 0 - 1 - - - INVEN1 - Output Waveform Invert Enable 1 - 1 - 1 - - - - - DBGCTRL - Debug Control - 0xF - 8 - 0x00 - - - DBGRUN - Run During Debug - 0 - 1 - - - - - SYNCBUSY - Synchronization Status - 0x10 - 32 - read-only - 0x00000000 - - - SWRST - swrst - 0 - 1 - - - ENABLE - enable - 1 - 1 - - - CTRLB - CTRLB - 2 - 1 - - - STATUS - STATUS - 3 - 1 - - - COUNT - Counter - 4 - 1 - - - PER - Period - 5 - 1 - - - CC0 - Compare Channel 0 - 6 - 1 - - - CC1 - Compare Channel 1 - 7 - 1 - - - - - COUNT - COUNT16 Count - 0x14 - 16 - 0x0000 - - - COUNT - Counter Value - 0 - 16 - - - - - 2 - 2 - CC[%s] - COUNT16 Compare and Capture - 0x1C - 16 - 0x0000 - - - CC - Counter/Compare Value - 0 - 16 - - - - - 2 - 2 - CCBUF[%s] - COUNT16 Compare and Capture Buffer - 0x30 - 16 - 0x0000 - - - CCBUF - Counter/Compare Buffer Value - 0 - 16 - - - - - - COUNT32 - 32-bit Counter Mode - COUNT8 - TcCount32 - 0x0 - - CTRLA - Control A - 0x0 - 32 - 0x00000000 - - - SWRST - Software Reset - 0 - 1 - - - ENABLE - Enable - 1 - 1 - - - MODE - Timer Counter Mode - 2 - 2 - - MODESelect - - COUNT16 - Counter in 16-bit mode - 0 - - - COUNT8 - Counter in 8-bit mode - 1 - - - COUNT32 - Counter in 32-bit mode - 2 - - - - - PRESCSYNC - Prescaler and Counter Synchronization - 4 - 2 - - PRESCSYNCSelect - - GCLK - Reload or reset the counter on next generic clock - 0 - - - PRESC - Reload or reset the counter on next prescaler clock - 1 - - - RESYNC - Reload or reset the counter on next generic clock and reset the prescaler counter - 2 - - - - - RUNSTDBY - Run during Standby - 6 - 1 - - - ONDEMAND - Clock On Demand - 7 - 1 - - - PRESCALER - Prescaler - 8 - 3 - - PRESCALERSelect - - DIV1 - Prescaler: GCLK_TC - 0 - - - DIV2 - Prescaler: GCLK_TC/2 - 1 - - - DIV4 - Prescaler: GCLK_TC/4 - 2 - - - DIV8 - Prescaler: GCLK_TC/8 - 3 - - - DIV16 - Prescaler: GCLK_TC/16 - 4 - - - DIV64 - Prescaler: GCLK_TC/64 - 5 - - - DIV256 - Prescaler: GCLK_TC/256 - 6 - - - DIV1024 - Prescaler: GCLK_TC/1024 - 7 - - - - - ALOCK - Auto Lock - 11 - 1 - - - CAPTEN0 - Capture Channel 0 Enable - 16 - 1 - - - CAPTEN1 - Capture Channel 1 Enable - 17 - 1 - - - COPEN0 - Capture On Pin 0 Enable - 20 - 1 - - - COPEN1 - Capture On Pin 1 Enable - 21 - 1 - - - - - CTRLBCLR - Control B Clear - 0x4 - 8 - 0x00 - - - DIR - Counter Direction - 0 - 1 - - - LUPD - Lock Update - 1 - 1 - - - ONESHOT - One-Shot on Counter - 2 - 1 - - - CMD - Command - 5 - 3 - - CMDSelect - - NONE - No action - 0 - - - RETRIGGER - Force a start, restart or retrigger - 1 - - - STOP - Force a stop - 2 - - - UPDATE - Force update of double-buffered register - 3 - - - READSYNC - Force a read synchronization of COUNT - 4 - - - DMAOS - One-shot DMA trigger - 5 - - - - - - - CTRLBSET - Control B Set - 0x5 - 8 - 0x00 - - - DIR - Counter Direction - 0 - 1 - - - LUPD - Lock Update - 1 - 1 - - - ONESHOT - One-Shot on Counter - 2 - 1 - - - CMD - Command - 5 - 3 - - CMDSelect - - NONE - No action - 0 - - - RETRIGGER - Force a start, restart or retrigger - 1 - - - STOP - Force a stop - 2 - - - UPDATE - Force update of double-buffered register - 3 - - - READSYNC - Force a read synchronization of COUNT - 4 - - - DMAOS - One-shot DMA trigger - 5 - - - - - - - EVCTRL - Event Control - 0x6 - 16 - 0x0000 - - - EVACT - Event Action - 0 - 3 - - EVACTSelect - - OFF - Event action disabled - 0 - - - RETRIGGER - Start, restart or retrigger TC on event - 1 - - - COUNT - Count on event - 2 - - - START - Start TC on event - 3 - - - STAMP - Time stamp capture - 4 - - - PPW - Period catured in CC0, pulse width in CC1 - 5 - - - PWP - Period catured in CC1, pulse width in CC0 - 6 - - - PW - Pulse width capture - 7 - - - - - TCINV - TC Event Input Polarity - 4 - 1 - - - TCEI - TC Event Enable - 5 - 1 - - - OVFEO - Event Output Enable - 8 - 1 - - - MCEO0 - MC Event Output Enable 0 - 12 - 1 - - - MCEO1 - MC Event Output Enable 1 - 13 - 1 - - - - - INTENCLR - Interrupt Enable Clear - 0x8 - 8 - 0x00 - - - OVF - OVF Interrupt Disable - 0 - 1 - - - ERR - ERR Interrupt Disable - 1 - 1 - - - MC0 - MC Interrupt Disable 0 - 4 - 1 - - - MC1 - MC Interrupt Disable 1 - 5 - 1 - - - - - INTENSET - Interrupt Enable Set - 0x9 - 8 - 0x00 - - - OVF - OVF Interrupt Enable - 0 - 1 - - - ERR - ERR Interrupt Enable - 1 - 1 - - - MC0 - MC Interrupt Enable 0 - 4 - 1 - - - MC1 - MC Interrupt Enable 1 - 5 - 1 - - - - - INTFLAG - Interrupt Flag Status and Clear - 0xA - 8 - 0x00 - - - OVF - OVF Interrupt Flag - 0 - 1 - - - ERR - ERR Interrupt Flag - 1 - 1 - - - MC0 - MC Interrupt Flag 0 - 4 - 1 - - - MC1 - MC Interrupt Flag 1 - 5 - 1 - - - - - STATUS - Status - 0xB - 8 - 0x01 - - - STOP - Stop Status Flag - 0 - 1 - - - SLAVE - Slave Status Flag - 1 - 1 - - - PERBUFV - Synchronization Busy Status - 3 - 1 - - - CCBUFV0 - Compare channel buffer 0 valid - 4 - 1 - - - CCBUFV1 - Compare channel buffer 1 valid - 5 - 1 - - - - - WAVE - Waveform Generation Control - 0xC - 8 - 0x00 - - - WAVEGEN - Waveform Generation Mode - 0 - 2 - - WAVEGENSelect - - NFRQ - Normal frequency - 0 - - - MFRQ - Match frequency - 1 - - - NPWM - Normal PWM - 2 - - - MPWM - Match PWM - 3 - - - - - - - DRVCTRL - Control C - 0xD - 8 - 0x00 - - - INVEN0 - Output Waveform Invert Enable 0 - 0 - 1 - - - INVEN1 - Output Waveform Invert Enable 1 - 1 - 1 - - - - - DBGCTRL - Debug Control - 0xF - 8 - 0x00 - - - DBGRUN - Run During Debug - 0 - 1 - - - - - SYNCBUSY - Synchronization Status - 0x10 - 32 - read-only - 0x00000000 - - - SWRST - swrst - 0 - 1 - - - ENABLE - enable - 1 - 1 - - - CTRLB - CTRLB - 2 - 1 - - - STATUS - STATUS - 3 - 1 - - - COUNT - Counter - 4 - 1 - - - PER - Period - 5 - 1 - - - CC0 - Compare Channel 0 - 6 - 1 - - - CC1 - Compare Channel 1 - 7 - 1 - - - - - COUNT - COUNT32 Count - 0x14 - 32 - 0x00000000 - - - COUNT - Counter Value - 0 - 32 - - - - - 2 - 4 - CC[%s] - COUNT32 Compare and Capture - 0x1C - 32 - 0x00000000 - - - CC - Counter/Compare Value - 0 - 32 - - - - - 2 - 4 - CCBUF[%s] - COUNT32 Compare and Capture Buffer - 0x30 - 32 - 0x00000000 - - - CCBUF - Counter/Compare Buffer Value - 0 - 32 - - - - - - - - TC1 - 0x42003400 - - TC1 - 21 - - - - TC2 - 0x42003800 - - TC2 - 22 - - - - TC3 - 0x42003C00 - - TC3 - 23 - - - - TC4 - 0x42004000 - - TC4 - 24 - - - - TCC0 - U22133.0.0 - Timer Counter Control - TCC - TCC_ - 0x42002400 - - 0 - 0x80 - registers - - - TCC0 - 17 - - - - CTRLA - Control A - 0x0 - 32 - 0x00000000 - - - SWRST - Software Reset - 0 - 1 - - - ENABLE - Enable - 1 - 1 - - - RESOLUTION - Enhanced Resolution - 5 - 2 - - RESOLUTIONSelect - - NONE - Dithering is disabled - 0 - - - DITH4 - Dithering is done every 16 PWM frames - 1 - - - DITH5 - Dithering is done every 32 PWM frames - 2 - - - DITH6 - Dithering is done every 64 PWM frames - 3 - - - - - PRESCALER - Prescaler - 8 - 3 - - PRESCALERSelect - - DIV1 - No division - 0 - - - DIV2 - Divide by 2 - 1 - - - DIV4 - Divide by 4 - 2 - - - DIV8 - Divide by 8 - 3 - - - DIV16 - Divide by 16 - 4 - - - DIV64 - Divide by 64 - 5 - - - DIV256 - Divide by 256 - 6 - - - DIV1024 - Divide by 1024 - 7 - - - - - RUNSTDBY - Run in Standby - 11 - 1 - - - PRESCSYNC - Prescaler and Counter Synchronization Selection - 12 - 2 - - PRESCSYNCSelect - - GCLK - Reload or reset counter on next GCLK - 0 - - - PRESC - Reload or reset counter on next prescaler clock - 1 - - - RESYNC - Reload or reset counter on next GCLK and reset prescaler counter - 2 - - - - - ALOCK - Auto Lock - 14 - 1 - - - MSYNC - Master Synchronization (only for TCC Slave Instance) - 15 - 1 - - - DMAOS - DMA One-shot Trigger Mode - 23 - 1 - - - CPTEN0 - Capture Channel 0 Enable - 24 - 1 - - - CPTEN1 - Capture Channel 1 Enable - 25 - 1 - - - CPTEN2 - Capture Channel 2 Enable - 26 - 1 - - - CPTEN3 - Capture Channel 3 Enable - 27 - 1 - - - - - CTRLBCLR - Control B Clear - 0x4 - 8 - 0x00 - - - DIR - Counter Direction - 0 - 1 - - - LUPD - Lock Update - 1 - 1 - - - ONESHOT - One-Shot - 2 - 1 - - - IDXCMD - Ramp Index Command - 3 - 2 - - IDXCMDSelect - - DISABLE - Command disabled: Index toggles between cycles A and B - 0 - - - SET - Set index: cycle B will be forced in the next cycle - 1 - - - CLEAR - Clear index: cycle A will be forced in the next cycle - 2 - - - HOLD - Hold index: the next cycle will be the same as the current cycle - 3 - - - - - CMD - TCC Command - 5 - 3 - - CMDSelect - - NONE - No action - 0 - - - RETRIGGER - Clear start, restart or retrigger - 1 - - - STOP - Force stop - 2 - - - UPDATE - Force update or double buffered registers - 3 - - - READSYNC - Force COUNT read synchronization - 4 - - - DMAOS - One-shot DMA trigger - 5 - - - - - - - CTRLBSET - Control B Set - 0x5 - 8 - 0x00 - - - DIR - Counter Direction - 0 - 1 - - - LUPD - Lock Update - 1 - 1 - - - ONESHOT - One-Shot - 2 - 1 - - - IDXCMD - Ramp Index Command - 3 - 2 - - IDXCMDSelect - - DISABLE - Command disabled: Index toggles between cycles A and B - 0 - - - SET - Set index: cycle B will be forced in the next cycle - 1 - - - CLEAR - Clear index: cycle A will be forced in the next cycle - 2 - - - HOLD - Hold index: the next cycle will be the same as the current cycle - 3 - - - - - CMD - TCC Command - 5 - 3 - - CMDSelect - - NONE - No action - 0 - - - RETRIGGER - Clear start, restart or retrigger - 1 - - - STOP - Force stop - 2 - - - UPDATE - Force update or double buffered registers - 3 - - - READSYNC - Force COUNT read synchronization - 4 - - - DMAOS - One-shot DMA trigger - 5 - - - - - - - SYNCBUSY - Synchronization Busy - 0x8 - 32 - read-only - 0x00000000 - - - SWRST - Swrst Busy - 0 - 1 - - - ENABLE - Enable Busy - 1 - 1 - - - CTRLB - Ctrlb Busy - 2 - 1 - - - STATUS - Status Busy - 3 - 1 - - - COUNT - Count Busy - 4 - 1 - - - PATT - Pattern Busy - 5 - 1 - - - WAVE - Wave Busy - 6 - 1 - - - PER - Period Busy - 7 - 1 - - - CC0 - Compare Channel 0 Busy - 8 - 1 - - - CC1 - Compare Channel 1 Busy - 9 - 1 - - - CC2 - Compare Channel 2 Busy - 10 - 1 - - - CC3 - Compare Channel 3 Busy - 11 - 1 - - - - - FCTRLA - Recoverable Fault A Configuration - 0xC - 32 - 0x00000000 - - - SRC - Fault A Source - 0 - 2 - - SRCSelect - - DISABLE - Fault input disabled - 0 - - - ENABLE - MCEx (x=0,1) event input - 1 - - - INVERT - Inverted MCEx (x=0,1) event input - 2 - - - ALTFAULT - Alternate fault (A or B) state at the end of the previous period - 3 - - - - - KEEP - Fault A Keeper - 3 - 1 - - - QUAL - Fault A Qualification - 4 - 1 - - - BLANK - Fault A Blanking Mode - 5 - 2 - - BLANKSelect - - START - Blanking applied from start of the ramp - 0 - - - RISE - Blanking applied from rising edge of the output waveform - 1 - - - FALL - Blanking applied from falling edge of the output waveform - 2 - - - BOTH - Blanking applied from each toggle of the output waveform - 3 - - - - - RESTART - Fault A Restart - 7 - 1 - - - HALT - Fault A Halt Mode - 8 - 2 - - HALTSelect - - DISABLE - Halt action disabled - 0 - - - HW - Hardware halt action - 1 - - - SW - Software halt action - 2 - - - NR - Non-recoverable fault - 3 - - - - - CHSEL - Fault A Capture Channel - 10 - 2 - - CHSELSelect - - CC0 - Capture value stored in channel 0 - 0 - - - CC1 - Capture value stored in channel 1 - 1 - - - CC2 - Capture value stored in channel 2 - 2 - - - CC3 - Capture value stored in channel 3 - 3 - - - - - CAPTURE - Fault A Capture Action - 12 - 3 - - CAPTURESelect - - DISABLE - No capture - 0 - - - CAPT - Capture on fault - 1 - - - CAPTMIN - Minimum capture - 2 - - - CAPTMAX - Maximum capture - 3 - - - LOCMIN - Minimum local detection - 4 - - - LOCMAX - Maximum local detection - 5 - - - DERIV0 - Minimum and maximum local detection - 6 - - - CAPTMARK - Capture with ramp index as MSB value - 7 - - - - - BLANKPRESC - Fault A Blanking Prescaler - 15 - 1 - - - BLANKVAL - Fault A Blanking Time - 16 - 8 - - - FILTERVAL - Fault A Filter Value - 24 - 4 - - - - - FCTRLB - Recoverable Fault B Configuration - 0x10 - 32 - 0x00000000 - - - SRC - Fault B Source - 0 - 2 - - SRCSelect - - DISABLE - Fault input disabled - 0 - - - ENABLE - MCEx (x=0,1) event input - 1 - - - INVERT - Inverted MCEx (x=0,1) event input - 2 - - - ALTFAULT - Alternate fault (A or B) state at the end of the previous period - 3 - - - - - KEEP - Fault B Keeper - 3 - 1 - - - QUAL - Fault B Qualification - 4 - 1 - - - BLANK - Fault B Blanking Mode - 5 - 2 - - BLANKSelect - - START - Blanking applied from start of the ramp - 0 - - - RISE - Blanking applied from rising edge of the output waveform - 1 - - - FALL - Blanking applied from falling edge of the output waveform - 2 - - - BOTH - Blanking applied from each toggle of the output waveform - 3 - - - - - RESTART - Fault B Restart - 7 - 1 - - - HALT - Fault B Halt Mode - 8 - 2 - - HALTSelect - - DISABLE - Halt action disabled - 0 - - - HW - Hardware halt action - 1 - - - SW - Software halt action - 2 - - - NR - Non-recoverable fault - 3 - - - - - CHSEL - Fault B Capture Channel - 10 - 2 - - CHSELSelect - - CC0 - Capture value stored in channel 0 - 0 - - - CC1 - Capture value stored in channel 1 - 1 - - - CC2 - Capture value stored in channel 2 - 2 - - - CC3 - Capture value stored in channel 3 - 3 - - - - - CAPTURE - Fault B Capture Action - 12 - 3 - - CAPTURESelect - - DISABLE - No capture - 0 - - - CAPT - Capture on fault - 1 - - - CAPTMIN - Minimum capture - 2 - - - CAPTMAX - Maximum capture - 3 - - - LOCMIN - Minimum local detection - 4 - - - LOCMAX - Maximum local detection - 5 - - - DERIV0 - Minimum and maximum local detection - 6 - - - CAPTMARK - Capture with ramp index as MSB value - 7 - - - - - BLANKPRESC - Fault B Blanking Prescaler - 15 - 1 - - - BLANKVAL - Fault B Blanking Time - 16 - 8 - - - FILTERVAL - Fault B Filter Value - 24 - 4 - - - - - WEXCTRL - Waveform Extension Configuration - 0x14 - 32 - 0x00000000 - - - OTMX - Output Matrix - 0 - 2 - - - DTIEN0 - Dead-time Insertion Generator 0 Enable - 8 - 1 - - - DTIEN1 - Dead-time Insertion Generator 1 Enable - 9 - 1 - - - DTIEN2 - Dead-time Insertion Generator 2 Enable - 10 - 1 - - - DTIEN3 - Dead-time Insertion Generator 3 Enable - 11 - 1 - - - DTLS - Dead-time Low Side Outputs Value - 16 - 8 - - - DTHS - Dead-time High Side Outputs Value - 24 - 8 - - - - - DRVCTRL - Driver Control - 0x18 - 32 - 0x00000000 - - - NRE0 - Non-Recoverable State 0 Output Enable - 0 - 1 - - - NRE1 - Non-Recoverable State 1 Output Enable - 1 - 1 - - - NRE2 - Non-Recoverable State 2 Output Enable - 2 - 1 - - - NRE3 - Non-Recoverable State 3 Output Enable - 3 - 1 - - - NRE4 - Non-Recoverable State 4 Output Enable - 4 - 1 - - - NRE5 - Non-Recoverable State 5 Output Enable - 5 - 1 - - - NRE6 - Non-Recoverable State 6 Output Enable - 6 - 1 - - - NRE7 - Non-Recoverable State 7 Output Enable - 7 - 1 - - - NRV0 - Non-Recoverable State 0 Output Value - 8 - 1 - - - NRV1 - Non-Recoverable State 1 Output Value - 9 - 1 - - - NRV2 - Non-Recoverable State 2 Output Value - 10 - 1 - - - NRV3 - Non-Recoverable State 3 Output Value - 11 - 1 - - - NRV4 - Non-Recoverable State 4 Output Value - 12 - 1 - - - NRV5 - Non-Recoverable State 5 Output Value - 13 - 1 - - - NRV6 - Non-Recoverable State 6 Output Value - 14 - 1 - - - NRV7 - Non-Recoverable State 7 Output Value - 15 - 1 - - - INVEN0 - Output Waveform 0 Inversion - 16 - 1 - - - INVEN1 - Output Waveform 1 Inversion - 17 - 1 - - - INVEN2 - Output Waveform 2 Inversion - 18 - 1 - - - INVEN3 - Output Waveform 3 Inversion - 19 - 1 - - - INVEN4 - Output Waveform 4 Inversion - 20 - 1 - - - INVEN5 - Output Waveform 5 Inversion - 21 - 1 - - - INVEN6 - Output Waveform 6 Inversion - 22 - 1 - - - INVEN7 - Output Waveform 7 Inversion - 23 - 1 - - - FILTERVAL0 - Non-Recoverable Fault Input 0 Filter Value - 24 - 4 - - - FILTERVAL1 - Non-Recoverable Fault Input 1 Filter Value - 28 - 4 - - - - - DBGCTRL - Debug Control - 0x1E - 8 - 0x00 - - - DBGRUN - Debug Running Mode - 0 - 1 - - - FDDBD - Fault Detection on Debug Break Detection - 2 - 1 - - - - - EVCTRL - Event Control - 0x20 - 32 - 0x00000000 - - - EVACT0 - Timer/counter Input Event0 Action - 0 - 3 - - EVACT0Select - - OFF - Event action disabled - 0 - - - RETRIGGER - Start, restart or re-trigger counter on event - 1 - - - COUNTEV - Count on event - 2 - - - START - Start counter on event - 3 - - - INC - Increment counter on event - 4 - - - COUNT - Count on active state of asynchronous event - 5 - - - STAMP - Stamp capture - 6 - - - FAULT - Non-recoverable fault - 7 - - - - - EVACT1 - Timer/counter Input Event1 Action - 3 - 3 - - EVACT1Select - - OFF - Event action disabled - 0 - - - RETRIGGER - Re-trigger counter on event - 1 - - - DIR - Direction control - 2 - - - STOP - Stop counter on event - 3 - - - DEC - Decrement counter on event - 4 - - - PPW - Period capture value in CC0 register, pulse width capture value in CC1 register - 5 - - - PWP - Period capture value in CC1 register, pulse width capture value in CC0 register - 6 - - - FAULT - Non-recoverable fault - 7 - - - - - CNTSEL - Timer/counter Output Event Mode - 6 - 2 - - CNTSELSelect - - START - An interrupt/event is generated when a new counter cycle starts - 0 - - - END - An interrupt/event is generated when a counter cycle ends - 1 - - - BETWEEN - An interrupt/event is generated when a counter cycle ends, except for the first and last cycles - 2 - - - BOUNDARY - An interrupt/event is generated when a new counter cycle starts or a counter cycle ends - 3 - - - - - OVFEO - Overflow/Underflow Output Event Enable - 8 - 1 - - - TRGEO - Retrigger Output Event Enable - 9 - 1 - - - CNTEO - Timer/counter Output Event Enable - 10 - 1 - - - TCINV0 - Inverted Event 0 Input Enable - 12 - 1 - - - TCINV1 - Inverted Event 1 Input Enable - 13 - 1 - - - TCEI0 - Timer/counter Event 0 Input Enable - 14 - 1 - - - TCEI1 - Timer/counter Event 1 Input Enable - 15 - 1 - - - MCEI0 - Match or Capture Channel 0 Event Input Enable - 16 - 1 - - - MCEI1 - Match or Capture Channel 1 Event Input Enable - 17 - 1 - - - MCEI2 - Match or Capture Channel 2 Event Input Enable - 18 - 1 - - - MCEI3 - Match or Capture Channel 3 Event Input Enable - 19 - 1 - - - MCEO0 - Match or Capture Channel 0 Event Output Enable - 24 - 1 - - - MCEO1 - Match or Capture Channel 1 Event Output Enable - 25 - 1 - - - MCEO2 - Match or Capture Channel 2 Event Output Enable - 26 - 1 - - - MCEO3 - Match or Capture Channel 3 Event Output Enable - 27 - 1 - - - - - INTENCLR - Interrupt Enable Clear - 0x24 - 32 - 0x00000000 - - - OVF - Overflow Interrupt Enable - 0 - 1 - - - TRG - Retrigger Interrupt Enable - 1 - 1 - - - CNT - Counter Interrupt Enable - 2 - 1 - - - ERR - Error Interrupt Enable - 3 - 1 - - - UFS - Non-Recoverable Update Fault Interrupt Enable - 10 - 1 - - - DFS - Non-Recoverable Debug Fault Interrupt Enable - 11 - 1 - - - FAULTA - Recoverable Fault A Interrupt Enable - 12 - 1 - - - FAULTB - Recoverable Fault B Interrupt Enable - 13 - 1 - - - FAULT0 - Non-Recoverable Fault 0 Interrupt Enable - 14 - 1 - - - FAULT1 - Non-Recoverable Fault 1 Interrupt Enable - 15 - 1 - - - MC0 - Match or Capture Channel 0 Interrupt Enable - 16 - 1 - - - MC1 - Match or Capture Channel 1 Interrupt Enable - 17 - 1 - - - MC2 - Match or Capture Channel 2 Interrupt Enable - 18 - 1 - - - MC3 - Match or Capture Channel 3 Interrupt Enable - 19 - 1 - - - - - INTENSET - Interrupt Enable Set - 0x28 - 32 - 0x00000000 - - - OVF - Overflow Interrupt Enable - 0 - 1 - - - TRG - Retrigger Interrupt Enable - 1 - 1 - - - CNT - Counter Interrupt Enable - 2 - 1 - - - ERR - Error Interrupt Enable - 3 - 1 - - - UFS - Non-Recoverable Update Fault Interrupt Enable - 10 - 1 - - - DFS - Non-Recoverable Debug Fault Interrupt Enable - 11 - 1 - - - FAULTA - Recoverable Fault A Interrupt Enable - 12 - 1 - - - FAULTB - Recoverable Fault B Interrupt Enable - 13 - 1 - - - FAULT0 - Non-Recoverable Fault 0 Interrupt Enable - 14 - 1 - - - FAULT1 - Non-Recoverable Fault 1 Interrupt Enable - 15 - 1 - - - MC0 - Match or Capture Channel 0 Interrupt Enable - 16 - 1 - - - MC1 - Match or Capture Channel 1 Interrupt Enable - 17 - 1 - - - MC2 - Match or Capture Channel 2 Interrupt Enable - 18 - 1 - - - MC3 - Match or Capture Channel 3 Interrupt Enable - 19 - 1 - - - - - INTFLAG - Interrupt Flag Status and Clear - 0x2C - 32 - 0x00000000 - - - OVF - Overflow - 0 - 1 - - - TRG - Retrigger - 1 - 1 - - - CNT - Counter - 2 - 1 - - - ERR - Error - 3 - 1 - - - UFS - Non-Recoverable Update Fault - 10 - 1 - - - DFS - Non-Recoverable Debug Fault - 11 - 1 - - - FAULTA - Recoverable Fault A - 12 - 1 - - - FAULTB - Recoverable Fault B - 13 - 1 - - - FAULT0 - Non-Recoverable Fault 0 - 14 - 1 - - - FAULT1 - Non-Recoverable Fault 1 - 15 - 1 - - - MC0 - Match or Capture 0 - 16 - 1 - - - MC1 - Match or Capture 1 - 17 - 1 - - - MC2 - Match or Capture 2 - 18 - 1 - - - MC3 - Match or Capture 3 - 19 - 1 - - - - - STATUS - Status - 0x30 - 32 - 0x00000001 - - - STOP - Stop - 0 - 1 - - - IDX - Ramp - 1 - 1 - - - UFS - Non-recoverable Update Fault State - 2 - 1 - - - DFS - Non-Recoverable Debug Fault State - 3 - 1 - - - SLAVE - Slave - 4 - 1 - - - PATTBUFV - Pattern Buffer Valid - 5 - 1 - - - PERBUFV - Period Buffer Valid - 7 - 1 - - - FAULTAIN - Recoverable Fault A Input - 8 - 1 - - - FAULTBIN - Recoverable Fault B Input - 9 - 1 - - - FAULT0IN - Non-Recoverable Fault0 Input - 10 - 1 - - - FAULT1IN - Non-Recoverable Fault1 Input - 11 - 1 - - - FAULTA - Recoverable Fault A State - 12 - 1 - - - FAULTB - Recoverable Fault B State - 13 - 1 - - - FAULT0 - Non-Recoverable Fault 0 State - 14 - 1 - - - FAULT1 - Non-Recoverable Fault 1 State - 15 - 1 - - - CCBUFV0 - Compare Channel 0 Buffer Valid - 16 - 1 - - - CCBUFV1 - Compare Channel 1 Buffer Valid - 17 - 1 - - - CCBUFV2 - Compare Channel 2 Buffer Valid - 18 - 1 - - - CCBUFV3 - Compare Channel 3 Buffer Valid - 19 - 1 - - - CMP0 - Compare Channel 0 Value - 24 - 1 - - - CMP1 - Compare Channel 1 Value - 25 - 1 - - - CMP2 - Compare Channel 2 Value - 26 - 1 - - - CMP3 - Compare Channel 3 Value - 27 - 1 - - - - - COUNT - Count - 0x34 - 32 - 0x00000000 - - - COUNT - Counter Value - 0 - 24 - - - - - COUNT_DITH4_MODE - Count - COUNT - 0x34 - 32 - 0x00000000 - - - COUNT - Counter Value - 4 - 20 - - - - - COUNT_DITH5_MODE - Count - COUNT - 0x34 - 32 - 0x00000000 - - - COUNT - Counter Value - 5 - 19 - - - - - COUNT_DITH6_MODE - Count - COUNT - 0x34 - 32 - 0x00000000 - - - COUNT - Counter Value - 6 - 18 - - - - - PATT - Pattern - 0x38 - 16 - 0x0000 - - - PGE0 - Pattern Generator 0 Output Enable - 0 - 1 - - - PGE1 - Pattern Generator 1 Output Enable - 1 - 1 - - - PGE2 - Pattern Generator 2 Output Enable - 2 - 1 - - - PGE3 - Pattern Generator 3 Output Enable - 3 - 1 - - - PGE4 - Pattern Generator 4 Output Enable - 4 - 1 - - - PGE5 - Pattern Generator 5 Output Enable - 5 - 1 - - - PGE6 - Pattern Generator 6 Output Enable - 6 - 1 - - - PGE7 - Pattern Generator 7 Output Enable - 7 - 1 - - - PGV0 - Pattern Generator 0 Output Value - 8 - 1 - - - PGV1 - Pattern Generator 1 Output Value - 9 - 1 - - - PGV2 - Pattern Generator 2 Output Value - 10 - 1 - - - PGV3 - Pattern Generator 3 Output Value - 11 - 1 - - - PGV4 - Pattern Generator 4 Output Value - 12 - 1 - - - PGV5 - Pattern Generator 5 Output Value - 13 - 1 - - - PGV6 - Pattern Generator 6 Output Value - 14 - 1 - - - PGV7 - Pattern Generator 7 Output Value - 15 - 1 - - - - - WAVE - Waveform Control - 0x3C - 32 - 0x00000000 - - - WAVEGEN - Waveform Generation - 0 - 3 - - WAVEGENSelect - - NFRQ - Normal frequency - 0 - - - MFRQ - Match frequency - 1 - - - NPWM - Normal PWM - 2 - - - DSCRITICAL - Dual-slope critical - 4 - - - DSBOTTOM - Dual-slope with interrupt/event condition when COUNT reaches ZERO - 5 - - - DSBOTH - Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP - 6 - - - DSTOP - Dual-slope with interrupt/event condition when COUNT reaches TOP - 7 - - - - - RAMP - Ramp Mode - 4 - 2 - - RAMPSelect - - RAMP1 - RAMP1 operation - 0 - - - RAMP2A - Alternative RAMP2 operation - 1 - - - RAMP2 - RAMP2 operation - 2 - - - RAMP2C - Critical RAMP2 operation - 3 - - - - - CIPEREN - Circular period Enable - 7 - 1 - - - CICCEN0 - Circular Channel 0 Enable - 8 - 1 - - - CICCEN1 - Circular Channel 1 Enable - 9 - 1 - - - CICCEN2 - Circular Channel 2 Enable - 10 - 1 - - - CICCEN3 - Circular Channel 3 Enable - 11 - 1 - - - POL0 - Channel 0 Polarity - 16 - 1 - - - POL1 - Channel 1 Polarity - 17 - 1 - - - POL2 - Channel 2 Polarity - 18 - 1 - - - POL3 - Channel 3 Polarity - 19 - 1 - - - SWAP0 - Swap DTI Output Pair 0 - 24 - 1 - - - SWAP1 - Swap DTI Output Pair 1 - 25 - 1 - - - SWAP2 - Swap DTI Output Pair 2 - 26 - 1 - - - SWAP3 - Swap DTI Output Pair 3 - 27 - 1 - - - - - PER - Period - 0x40 - 32 - 0xFFFFFFFF - - - PER - Period Value - 0 - 24 - - - - - PER_DITH4_MODE - Period - PER - 0x40 - 32 - 0xFFFFFFFF - - - DITHER - Dithering Cycle Number - 0 - 4 - - - PER - Period Value - 4 - 20 - - - - - PER_DITH5_MODE - Period - PER - 0x40 - 32 - 0xFFFFFFFF - - - DITHER - Dithering Cycle Number - 0 - 5 - - - PER - Period Value - 5 - 19 - - - - - PER_DITH6_MODE - Period - PER - 0x40 - 32 - 0xFFFFFFFF - - - DITHER - Dithering Cycle Number - 0 - 6 - - - PER - Period Value - 6 - 18 - - - - - 4 - 4 - CC[%s] - Compare and Capture - 0x44 - 32 - 0x00000000 - - - CC - Channel Compare/Capture Value - 0 - 24 - - - - - 4 - 4 - CC_DITH4_MODE[%s] - Compare and Capture - CC[%s] - 0x44 - 32 - 0x00000000 - - - DITHER - Dithering Cycle Number - 0 - 4 - - - CC - Channel Compare/Capture Value - 4 - 20 - - - - - 4 - 4 - CC_DITH5_MODE[%s] - Compare and Capture - CC[%s] - 0x44 - 32 - 0x00000000 - - - DITHER - Dithering Cycle Number - 0 - 5 - - - CC - Channel Compare/Capture Value - 5 - 19 - - - - - 4 - 4 - CC_DITH6_MODE[%s] - Compare and Capture - CC[%s] - 0x44 - 32 - 0x00000000 - - - DITHER - Dithering Cycle Number - 0 - 6 - - - CC - Channel Compare/Capture Value - 6 - 18 - - - - - PATTBUF - Pattern Buffer - 0x64 - 16 - 0x0000 - - - PGEB0 - Pattern Generator 0 Output Enable Buffer - 0 - 1 - - - PGEB1 - Pattern Generator 1 Output Enable Buffer - 1 - 1 - - - PGEB2 - Pattern Generator 2 Output Enable Buffer - 2 - 1 - - - PGEB3 - Pattern Generator 3 Output Enable Buffer - 3 - 1 - - - PGEB4 - Pattern Generator 4 Output Enable Buffer - 4 - 1 - - - PGEB5 - Pattern Generator 5 Output Enable Buffer - 5 - 1 - - - PGEB6 - Pattern Generator 6 Output Enable Buffer - 6 - 1 - - - PGEB7 - Pattern Generator 7 Output Enable Buffer - 7 - 1 - - - PGVB0 - Pattern Generator 0 Output Enable - 8 - 1 - - - PGVB1 - Pattern Generator 1 Output Enable - 9 - 1 - - - PGVB2 - Pattern Generator 2 Output Enable - 10 - 1 - - - PGVB3 - Pattern Generator 3 Output Enable - 11 - 1 - - - PGVB4 - Pattern Generator 4 Output Enable - 12 - 1 - - - PGVB5 - Pattern Generator 5 Output Enable - 13 - 1 - - - PGVB6 - Pattern Generator 6 Output Enable - 14 - 1 - - - PGVB7 - Pattern Generator 7 Output Enable - 15 - 1 - - - - - PERBUF - Period Buffer - 0x6C - 32 - 0xFFFFFFFF - - - PERBUF - Period Buffer Value - 0 - 24 - - - - - PERBUF_DITH4_MODE - Period Buffer - PERBUF - 0x6C - 32 - 0xFFFFFFFF - - - DITHERBUF - Dithering Buffer Cycle Number - 0 - 4 - - - PERBUF - Period Buffer Value - 4 - 20 - - - - - PERBUF_DITH5_MODE - Period Buffer - PERBUF - 0x6C - 32 - 0xFFFFFFFF - - - DITHERBUF - Dithering Buffer Cycle Number - 0 - 5 - - - PERBUF - Period Buffer Value - 5 - 19 - - - - - PERBUF_DITH6_MODE - Period Buffer - PERBUF - 0x6C - 32 - 0xFFFFFFFF - - - DITHERBUF - Dithering Buffer Cycle Number - 0 - 6 - - - PERBUF - Period Buffer Value - 6 - 18 - - - - - 4 - 4 - CCBUF[%s] - Compare and Capture Buffer - 0x70 - 32 - 0x00000000 - - - CCBUF - Channel Compare/Capture Buffer Value - 0 - 24 - - - - - 4 - 4 - CCBUF_DITH4_MODE[%s] - Compare and Capture Buffer - CCBUF[%s] - 0x70 - 32 - 0x00000000 - - - CCBUF - Channel Compare/Capture Buffer Value - 0 - 4 - - - DITHERBUF - Dithering Buffer Cycle Number - 4 - 20 - - - - - 4 - 4 - CCBUF_DITH5_MODE[%s] - Compare and Capture Buffer - CCBUF[%s] - 0x70 - 32 - 0x00000000 - - - DITHERBUF - Dithering Buffer Cycle Number - 0 - 5 - - - CCBUF - Channel Compare/Capture Buffer Value - 5 - 19 - - - - - 4 - 4 - CCBUF_DITH6_MODE[%s] - Compare and Capture Buffer - CCBUF[%s] - 0x70 - 32 - 0x00000000 - - - DITHERBUF - Dithering Buffer Cycle Number - 0 - 6 - - - CCBUF - Channel Compare/Capture Buffer Value - 6 - 18 - - - - - - - TCC1 - 0x42002800 - - TCC1 - 18 - - - - TCC2 - 0x42002C00 - - TCC2 - 19 - - - - TSENS - U22611.0.1 - Temperature Sensor - TSENS - TSENS_ - 0x40003000 - - 0 - 0x25 - registers - - - TSENS - 5 - - - - CTRLA - Control A Register - 0x0 - 8 - 0x00 - - - SWRST - Software Reset - 0 - 1 - - - ENABLE - Enable - 1 - 1 - - - RUNSTDBY - Run in Standby - 6 - 1 - - - - - CTRLB - Control B Register - 0x1 - 8 - write-only - 0x00 - - - START - Start Measurement - 0 - 1 - - - - - CTRLC - Control C Register - 0x2 - 8 - 0x00 - - - WINMODE - Window Monitor Mode - 0 - 3 - - WINMODESelect - - DISABLE - No window mode (default) - 0 - - - ABOVE - VALUE greater than WINLT - 1 - - - BELOW - VALUE less than WINUT - 2 - - - INSIDE - VALUE greater than WINLT and VALUE less than WINUT - 3 - - - OUTSIDE - VALUE less than WINLT or VALUE greater than WINUT - 4 - - - HYST_ABOVE - VALUE greater than WINUT with hysteresis to WINLT - 5 - - - HYST_BELOW - VALUE less than WINLST with hysteresis to WINUT - 6 - - - - - FREERUN - Free Running Measurement - 4 - 1 - - - - - EVCTRL - Event Control Register - 0x3 - 8 - 0x00 - - - STARTEI - Start Conversion Event Input Enable - 0 - 1 - - - STARTINV - Start Conversion Event Invert Enable - 1 - 1 - - - WINEO - Window Monitor Event Out - 2 - 1 - - - - - INTENCLR - Interrupt Enable Clear Register - 0x4 - 8 - 0x00 - - - RESRDY - Result Ready Interrupt Enable - 0 - 1 - - - OVERRUN - Overrun Interrupt Enable - 1 - 1 - - - WINMON - Window Monitor Interrupt Enable - 2 - 1 - - - OVF - Overflow Interrupt Enable - 3 - 1 - - - - - INTENSET - Interrupt Enable Set Register - 0x5 - 8 - 0x00 - - - RESRDY - Result Ready Interrupt Enable - 0 - 1 - - - OVERRUN - Overrun Interrupt Enable - 1 - 1 - - - WINMON - Window Monitor Interrupt Enable - 2 - 1 - - - OVF - Overflow Interrupt Enable - 3 - 1 - - - - - INTFLAG - Interrupt Flag Status and Clear Register - 0x6 - 8 - 0x00 - - - RESRDY - Result Ready - 0 - 1 - - - OVERRUN - Overrun - 1 - 1 - - - WINMON - Window Monitor - 2 - 1 - - - OVF - Overflow - 3 - 1 - - - - - STATUS - Status Register - 0x7 - 8 - read-only - 0x00 - - - OVF - Result Overflow - 0 - 1 - - - - - SYNCBUSY - Synchronization Busy Register - 0x8 - 32 - read-only - 0x00000000 - - - SWRST - Software Reset Busy - 0 - 1 - - - ENABLE - Enable Busy - 1 - 1 - - - - - VALUE - Value Register - 0xC - 32 - read-only - 0x00000000 - - - VALUE - Measurement Value - 0 - 24 - - - - - WINLT - Window Monitor Lower Threshold Register - 0x10 - 32 - 0x00000000 - - - WINLT - Window Lower Threshold - 0 - 24 - - - - - WINUT - Window Monitor Upper Threshold Register - 0x14 - 32 - 0x00000000 - - - WINUT - Window Upper Threshold - 0 - 24 - - - - - GAIN - Gain Register - 0x18 - 32 - 0x00000000 - - - GAIN - Time Amplifier Gain - 0 - 24 - - - - - OFFSET - Offset Register - 0x1C - 32 - 0x00000000 - - - OFFSETC - Offset Correction - 0 - 24 - - - - - CAL - Calibration Register - 0x20 - 32 - 0x00000000 - - - FCAL - Frequency Calibration - 0 - 6 - - - TCAL - Temperature Calibration - 8 - 6 - - - - - DBGCTRL - Debug Control Register - 0x24 - 8 - 0x00 - - - DBGRUN - Debug Run - 0 - 1 - - - - - - - WDT - U22511.0.1 - Watchdog Timer - WDT - WDT_ - 0x40002000 - - 0 - 0xD - registers - - - WDT - 1 - - - - CTRLA - Control - 0x0 - 8 - 0x00 - - - ENABLE - Enable - 1 - 1 - - - WEN - Watchdog Timer Window Mode Enable - 2 - 1 - - - ALWAYSON - Always-On - 7 - 1 - - - - - CONFIG - Configuration - 0x1 - 8 - 0xBB - - - PER - Time-Out Period - 0 - 4 - - PERSelect - - CYC8 - 8 clock cycles - 0x0 - - - CYC16 - 16 clock cycles - 0x1 - - - CYC32 - 32 clock cycles - 0x2 - - - CYC64 - 64 clock cycles - 0x3 - - - CYC128 - 128 clock cycles - 0x4 - - - CYC256 - 256 clock cycles - 0x5 - - - CYC512 - 512 clock cycles - 0x6 - - - CYC1024 - 1024 clock cycles - 0x7 - - - CYC2048 - 2048 clock cycles - 0x8 - - - CYC4096 - 4096 clock cycles - 0x9 - - - CYC8192 - 8192 clock cycles - 0xA - - - CYC16384 - 16384 clock cycles - 0xB - - - - - WINDOW - Window Mode Time-Out Period - 4 - 4 - - WINDOWSelect - - CYC8 - 8 clock cycles - 0x0 - - - CYC16 - 16 clock cycles - 0x1 - - - CYC32 - 32 clock cycles - 0x2 - - - CYC64 - 64 clock cycles - 0x3 - - - CYC128 - 128 clock cycles - 0x4 - - - CYC256 - 256 clock cycles - 0x5 - - - CYC512 - 512 clock cycles - 0x6 - - - CYC1024 - 1024 clock cycles - 0x7 - - - CYC2048 - 2048 clock cycles - 0x8 - - - CYC4096 - 4096 clock cycles - 0x9 - - - CYC8192 - 8192 clock cycles - 0xA - - - CYC16384 - 16384 clock cycles - 0xB - - - - - - - EWCTRL - Early Warning Interrupt Control - 0x2 - 8 - 0x0B - - - EWOFFSET - Early Warning Interrupt Time Offset - 0 - 4 - - EWOFFSETSelect - - CYC8 - 8 clock cycles - 0x0 - - - CYC16 - 16 clock cycles - 0x1 - - - CYC32 - 32 clock cycles - 0x2 - - - CYC64 - 64 clock cycles - 0x3 - - - CYC128 - 128 clock cycles - 0x4 - - - CYC256 - 256 clock cycles - 0x5 - - - CYC512 - 512 clock cycles - 0x6 - - - CYC1024 - 1024 clock cycles - 0x7 - - - CYC2048 - 2048 clock cycles - 0x8 - - - CYC4096 - 4096 clock cycles - 0x9 - - - CYC8192 - 8192 clock cycles - 0xA - - - CYC16384 - 16384 clock cycles - 0xB - - - - - - - INTENCLR - Interrupt Enable Clear - 0x4 - 8 - 0x00 - - - EW - Early Warning Interrupt Enable - 0 - 1 - - - - - INTENSET - Interrupt Enable Set - 0x5 - 8 - 0x00 - - - EW - Early Warning Interrupt Enable - 0 - 1 - - - - - INTFLAG - Interrupt Flag Status and Clear - 0x6 - 8 - 0x00 - - - EW - Early Warning - 0 - 1 - - - - - SYNCBUSY - Synchronization Busy - 0x8 - 32 - read-only - 0x00000000 - - - ENABLE - Enable Busy - 1 - 1 - - - WEN - Window Enable Busy - 2 - 1 - - - ALWAYSON - Always-On Busy - 3 - 1 - - - CLEAR - Clear Busy - 4 - 1 - - - - - CLEAR - Clear - 0xC - 8 - write-only - 0x00 - - - CLEAR - Watchdog Clear - 0 - 8 - - CLEARSelect - - KEY - Clear Key - 0xA5 - - - - - - - - - MPU - Memory Protection Unit - MPU - MPU_ - 0xE000ED90 - - 0 - 0x14 - registers - - - - TYPE - MPU Type Register - 0x0 - 32 - read-only - - - SEPARATE - Separate instruction and Data Memory MapsRegions - 0 - 1 - - - DREGION - Number of Data Regions - 8 - 8 - - - IREGION - Number of Instruction Regions - 16 - 8 - - - - - CTRL - MPU Control Register - 0x4 - 32 - - - ENABLE - MPU Enable - 0 - 1 - - - HFNMIENA - Enable Hard Fault and NMI handlers - 1 - 1 - - - PRIVDEFENA - Enables privileged software access to default memory map - 2 - 1 - - - - - RNR - MPU Region Number Register - 0x8 - 32 - - - REGION - Region referenced by RBAR and RASR - 0 - 8 - - - - - RBAR - MPU Region Base Address Register - 0xC - 32 - - - REGION - Region number - 0 - 4 - - - VALID - Region number valid - 4 - 1 - - - ADDR - Region base address - 5 - 27 - - - - - RASR - MPU Region Attribute and Size Register - 0x10 - 32 - - - ENABLE - Region Enable - 0 - 1 - - - SIZE - Region Size - 1 - 5 - - - SRD - Sub-region disable - 8 - 8 - - - B - Bufferable bit - 16 - 1 - - - C - Cacheable bit - 17 - 1 - - - S - Shareable bit - 18 - 1 - - - TEX - TEX bit - 19 - 3 - - - AP - Access Permission - 24 - 3 - - - XN - Execute Never Attribute - 28 - 1 - - - - - - - NVIC - Nested Vectored Interrupt Controller - NVIC - NVIC_ - 0xE000E100 - - 0 - 0x320 - registers - - - - ISER - Interrupt Set Enable Register - 0x0 - 32 - 0x00000000 - - - SETENA - Interrupt set enable bits - 0 - 31 - - - - - ICER - Interrupt Clear Enable Register - 0x80 - 32 - 0x00000000 - - - CLRENA - Interrupt clear-enable bits - 0 - 31 - - - - - ISPR - Interrupt Set Pending Register - 0x100 - 32 - 0x00000000 - - - SETPEND - Interrupt set-pending bits - 0 - 31 - - - - - ICPR - Interrupt Clear Pending Register - 0x180 - 32 - 0x00000000 - - - CLRPEND - Interrupt clear-pending bits - 0 - 31 - - - - - 8 - 4 - IPR[%s] - Interrupt Priority Register n - 0x300 - 32 - 0x00000000 - - - PRI0 - Priority of interrupt n - 0 - 2 - - - PRI1 - Priority of interrupt n - 8 - 2 - - - PRI2 - Priority of interrupt n - 16 - 2 - - - PRI3 - Priority of interrupt n - 24 - 2 - - - - - - - SysTick - System timer - SysTick - SysTick_ - 0xE000E010 - - 0 - 0x10 - registers - - - - CSR - SysTick Control and Status Register - 0x0 - 32 - 0x4 - - - ENABLE - SysTick Counter Enable - 0 - 1 - - ENABLESelect - - VALUE_0 - Counter disabled - 0 - - - VALUE_1 - Counter enabled - 1 - - - - - TICKINT - SysTick Exception Request Enable - 1 - 1 - - TICKINTSelect - - VALUE_0 - Counting down to 0 does not assert the SysTick exception request - 0 - - - VALUE_1 - Counting down to 0 asserts the SysTick exception request - 1 - - - - - CLKSOURCE - Clock Source 0=external, 1=processor - 2 - 1 - - CLKSOURCESelect - - VALUE_0 - External clock - 0 - - - VALUE_1 - Processor clock - 1 - - - - - COUNTFLAG - Timer counted to 0 since last read of register - 16 - 1 - - - - - RVR - SysTick Reload Value Register - 0x4 - 32 - - - RELOAD - Value to load into the SysTick Current Value Register when the counter reaches 0 - 0 - 24 - - - - - CVR - SysTick Current Value Register - 0x8 - 32 - - - CURRENT - Current value at the time the register is accessed - 0 - 24 - - - - - CALIB - SysTick Calibration Value Register - 0xC - 32 - read-only - 0 - - - TENMS - Reload value to use for 10ms timing - 0 - 24 - - - SKEW - TENMS is rounded from non-integer ratio - 30 - 1 - - SKEWSelect - - VALUE_0 - 10ms calibration value is exact - 0 - - - VALUE_1 - 10ms calibration value is inexact, because of the clock frequency - 1 - - - - - NOREF - No Separate Reference Clock - 31 - 1 - - NOREFSelect - - VALUE_0 - The reference clock is provided - 0 - - - VALUE_1 - The reference clock is not provided - 1 - - - - - - - - - SystemControl - System Control Registers - SystemControl - SystemControl_ - 0xE000E000 - - 0 - 0xD34 - registers - - - - CPUID - CPUID Base Register - 0xD00 - 32 - read-only - 0x410CC601 - - - REVISION - Minor revision number - 0 - 4 - - - PARTNO - Processor Part Number, 0xC60=Cortex-M0+ - 4 - 12 - - - ARCHITECTURE - Processor Architecture, 0xC=ARMv6-M - 16 - 4 - - - VARIANT - Major revision number - 20 - 4 - - - IMPLEMENTER - Implementer code, ARM=0x41 - 24 - 8 - - - - - ICSR - Interrupt Control and State Register - 0xD04 - 32 - 0x00000000 - - - VECTACTIVE - Debug: Exception number of currently executing exception, or 0 if thread mode - 0 - 9 - - - VECTPENDING - Exception number of the highest priority pending enabled exception - 12 - 9 - - - ISRPENDING - Debug: NVIC interrupt pending - 22 - 1 - - - ISRPREEMPT - Debug: Pending exception serviced on exit from debug halt - 23 - 1 - - - PENDSTCLR - SysTick exception clear-pending bit - 25 - 1 - - PENDSTCLRSelect - - VALUE_0 - No effect - 0 - - - VALUE_1 - Removes the pending state from the SysTick exception - 1 - - - - - PENDSTSET - SysTick exception set-pending bit - 26 - 1 - - PENDSTSETSelect - - VALUE_0 - Write: no effect; read: SysTick exception is not pending - 0 - - - VALUE_1 - Write: changes SysTick exception state to pending; read: SysTick exception is pending - 1 - - - - - PENDSVCLR - PendSV clear-pending bit - 27 - 1 - - PENDSVCLRSelect - - VALUE_0 - No effect - 0 - - - VALUE_1 - Removes the pending state from the PendSV exception - 1 - - - - - PENDSVSET - PendSV set-pending bit - 28 - 1 - - PENDSVSETSelect - - VALUE_0 - Write: no effect; read: PendSV exception is not pending - 0 - - - VALUE_1 - Write: changes PendSV exception state to pending; read: PendSV exception is pending - 1 - - - - - NMIPENDSET - NMI set-pending bit - 31 - 1 - - NMIPENDSETSelect - - VALUE_0 - Write: no effect; read: NMI exception is not pending - 0 - - - VALUE_1 - Write: changes NMI exception state to pending; read: NMI exception is pending - 1 - - - - - - - VTOR - Vector Table Offset Register - 0xD08 - 32 - 0x00000000 - - - TBLOFF - Vector table base offset - 7 - 25 - - - - - AIRCR - Application Interrupt and Reset Control Register - 0xD0C - 32 - 0x00000000 - - - VECTCLRACTIVE - Debug: Clear state information - 1 - 1 - - - SYSRESETREQ - System Reset Request - 2 - 1 - - SYSRESETREQSelect - - VALUE_0 - No system reset request - 0 - - - VALUE_1 - Asserts a signal to the outer system that requests a reset - 1 - - - - - ENDIANNESS - Data Endianness, 0=little, 1=big - 15 - 1 - - ENDIANNESSSelect - - VALUE_0 - Little-endian - 0 - - - VALUE_1 - Big-endian - 1 - - - - - VECTKEY - Register key (0x05FA) - 16 - 16 - - - - - SCR - System Control Register - 0xD10 - 32 - 0x00000000 - - - SLEEPONEXIT - Sleep-On-Exit when exiting Handler mode - 1 - 1 - - SLEEPONEXITSelect - - VALUE_0 - O not sleep when returning to Thread mode - 0 - - - VALUE_1 - Enter sleep, or deep sleep, on return from an ISR - 1 - - - - - SLEEPDEEP - Uses Deep Sleep as low power mode - 2 - 1 - - SLEEPDEEPSelect - - VALUE_0 - Sleep - 0 - - - VALUE_1 - Deep sleep - 1 - - - - - SEVONPEND - Send Event on Pending bit - 4 - 1 - - SEVONPENDSelect - - VALUE_0 - Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded - 0 - - - VALUE_1 - Enabled events and all interrupts, including disabled interrupts, can wakeup the processor - 1 - - - - - - - CCR - Configuration and Control Register - 0xD14 - 32 - read-only - 0x00000204 - - - UNALIGN_TRP - Unaligned accesses generates a Hard Fault - 3 - 1 - - UNALIGN_TRPSelect - - VALUE_0 - Do not trap unaligned halfword and word accesses - 0 - - - VALUE_1 - Trap unaligned halfword and word accesses - 1 - - - - - STKALIGN - Stack 8-byte aligned on exception entry - 9 - 1 - - STKALIGNSelect - - VALUE_0 - 4-byte aligned - 0 - - - VALUE_1 - 8-byte aligned - 1 - - - - - - - SHPR2 - System Handler Priority Register 2 - 0xD1C - 32 - 0x00000000 - - - PRI_11 - Priority of system handler 11, SVCall - 24 - 8 - - - - - SHPR3 - System Handler Priority Register 3 - 0xD20 - 32 - 0x00000000 - - - PRI_14 - Priority of system handler 14, PendSV - 16 - 8 - - - PRI_15 - Priority of system handler 15, SysTick exception - 24 - 8 - - - - - SHCSR - System Handler Control and State Register - 0xD24 - 32 - 0x00000000 - - - SVCALLPENDED - 15 - 1 - - - - - DFSR - Debug Fault Status Register - 0xD30 - 32 - 0x00000000 - - - HALTED - Halt request debug event active - 0 - 1 - - - BKPT - Breakpoint debug event - 1 - 1 - - - DWTTRAP - DWT debug event - 2 - 1 - - - VCATCH - Vector catch debug event - 3 - 1 - - - EXTERNAL - EDBGRQ debug event - 4 - 1 - - - - - - - diff --git a/svd/devices/atsamc20e18a.xsl b/svd/devices/atsamc20e18a.xsl new file mode 100644 index 000000000000..06da3fbc23d8 --- /dev/null +++ b/svd/devices/atsamc20e18a.xsl @@ -0,0 +1,5 @@ + + + + + diff --git a/svd/devices/atsamc20g18a.xsl b/svd/devices/atsamc20g18a.xsl new file mode 100644 index 000000000000..06da3fbc23d8 --- /dev/null +++ b/svd/devices/atsamc20g18a.xsl @@ -0,0 +1,5 @@ + + + + + diff --git a/svd/devices/atsamc20j18a.xsl b/svd/devices/atsamc20j18a.xsl new file mode 100644 index 000000000000..06da3fbc23d8 --- /dev/null +++ b/svd/devices/atsamc20j18a.xsl @@ -0,0 +1,5 @@ + + + + + diff --git a/svd/devices/atsamc20n18a.xsl b/svd/devices/atsamc20n18a.xsl new file mode 100644 index 000000000000..06da3fbc23d8 --- /dev/null +++ b/svd/devices/atsamc20n18a.xsl @@ -0,0 +1,5 @@ + + + + + diff --git a/svd/devices/atsamc21e18a.xsl b/svd/devices/atsamc21e18a.xsl new file mode 100644 index 000000000000..06da3fbc23d8 --- /dev/null +++ b/svd/devices/atsamc21e18a.xsl @@ -0,0 +1,5 @@ + + + + + diff --git a/svd/devices/atsamc21g18a.xsl b/svd/devices/atsamc21g18a.xsl new file mode 100644 index 000000000000..06da3fbc23d8 --- /dev/null +++ b/svd/devices/atsamc21g18a.xsl @@ -0,0 +1,5 @@ + + + + + diff --git a/svd/devices/atsamc21j18a.xsl b/svd/devices/atsamc21j18a.xsl new file mode 100644 index 000000000000..06da3fbc23d8 --- /dev/null +++ b/svd/devices/atsamc21j18a.xsl @@ -0,0 +1,5 @@ + + + + + diff --git a/svd/devices/atsamc21n18a.xsl b/svd/devices/atsamc21n18a.xsl new file mode 100644 index 000000000000..06da3fbc23d8 --- /dev/null +++ b/svd/devices/atsamc21n18a.xsl @@ -0,0 +1,5 @@ + + + + + diff --git a/svd/devices/include/atsamc2x.xsl b/svd/devices/include/atsamc2x.xsl new file mode 100644 index 000000000000..cc0e5a7dbe51 --- /dev/null +++ b/svd/devices/include/atsamc2x.xsl @@ -0,0 +1,7 @@ + + + + + From 107cc240a126c1b8c6c90dcb264cae5c6ad2013c Mon Sep 17 00:00:00 2001 From: Jeremy Boynes Date: Sat, 14 Jan 2023 09:54:37 -0500 Subject: [PATCH 3/3] Add example using PAC directly to show something running on hardware --- boards/atsamc21_xpro/.cargo/config | 14 + boards/atsamc21_xpro/CHANGELOG.md | 7 + boards/atsamc21_xpro/Cargo.toml | 58 ++ boards/atsamc21_xpro/README.md | 30 + boards/atsamc21_xpro/SAMC21.yaml | 709 ++++++++++++++++++++ boards/atsamc21_xpro/build.rs | 16 + boards/atsamc21_xpro/examples/blinky_pac.rs | 29 + boards/atsamc21_xpro/memory.x | 36 + boards/atsamc21_xpro/src/lib.rs | 12 + 9 files changed, 911 insertions(+) create mode 100644 boards/atsamc21_xpro/.cargo/config create mode 100644 boards/atsamc21_xpro/CHANGELOG.md create mode 100644 boards/atsamc21_xpro/Cargo.toml create mode 100644 boards/atsamc21_xpro/README.md create mode 100644 boards/atsamc21_xpro/SAMC21.yaml create mode 100644 boards/atsamc21_xpro/build.rs create mode 100644 boards/atsamc21_xpro/examples/blinky_pac.rs create mode 100644 boards/atsamc21_xpro/memory.x create mode 100644 boards/atsamc21_xpro/src/lib.rs diff --git a/boards/atsamc21_xpro/.cargo/config b/boards/atsamc21_xpro/.cargo/config new file mode 100644 index 000000000000..fc515d391ff5 --- /dev/null +++ b/boards/atsamc21_xpro/.cargo/config @@ -0,0 +1,14 @@ +# samd21 is a Cortex-M0 and thus thumbv6m + +[build] +target = "thumbv6m-none-eabi" +rustflags = [ + # This is needed if your flash or ram addresses are not aligned to 0x10000 in memory.x + # See https://github.com/rust-embedded/cortex-m-quickstart/pull/95 + "-C", "link-arg=--nmagic", + "-C", "link-arg=-Tlink.x", +] + +[target.thumbv6m-none-eabi] +runner = 'arm-none-eabi-gdb' +#runner = 'probe-run --chip ATSAMC21J18A' diff --git a/boards/atsamc21_xpro/CHANGELOG.md b/boards/atsamc21_xpro/CHANGELOG.md new file mode 100644 index 000000000000..481f1e29f56d --- /dev/null +++ b/boards/atsamc21_xpro/CHANGELOG.md @@ -0,0 +1,7 @@ +# Unreleased + +- Initial version + +--- + +Changelog tracking started at v0.0.0 diff --git a/boards/atsamc21_xpro/Cargo.toml b/boards/atsamc21_xpro/Cargo.toml new file mode 100644 index 000000000000..675179b41b91 --- /dev/null +++ b/boards/atsamc21_xpro/Cargo.toml @@ -0,0 +1,58 @@ +[package] +name = "atsamc21_xpro" +version = "0.0.0" +authors = [ + "Jeremy Boynes " +] +description = "Board Support crate for the SAM C21 Xplained Pro Evaluation Kit" +keywords = ["no-std", "arm", "cortex-m", "embedded-hal"] +categories = ["embedded", "hardware-support", "no-std"] +license = "MIT OR Apache-2.0" +edition = "2021" +repository = "https://github.com/atsamd-rs/atsamd" +readme = "README.md" + +# for cargo flash +[package.metadata] +chip = "ATSAMC21J18A" + +[dependencies.cortex-m-rt] +version = "0.7" +optional = true + +[dependencies.atsamc21j] +path = "../../pac/atsamc21j" + + +#[dependencies.atsamd-hal] +#path = "../../hal" +#version = "0.15" +#default-features = false + +[dev-dependencies] +cortex-m = "0.7" +panic-halt = "0.2" +panic-semihosting = "0.6" + +[features] +#default = ["rt", "atsamd-hal/samc21j", "atsamd-hal/unproven"] +#rt = ["cortex-m-rt", "atsamd-hal/samc21j-rt"] +#unproven = ["atsamd-hal/unproven"] +default = ["rt", ] +rt = ["cortex-m-rt"] + +[profile.dev] +incremental = false +codegen-units = 1 +debug = true +lto = true + +[profile.release] +lto = true +opt-level = "s" + +[[example]] +name = "blinky_pac" + +#[[example]] +#name = "blinky_basic" diff --git a/boards/atsamc21_xpro/README.md b/boards/atsamc21_xpro/README.md new file mode 100644 index 000000000000..4db4a8ef7255 --- /dev/null +++ b/boards/atsamc21_xpro/README.md @@ -0,0 +1,30 @@ +# SAM C21 Xplained Pro Evaluation Kit Board Support Crate + +This crate provides a type-safe Rust API for working with the +[SAM C21 Xplained Pro Evaluation Kit](https://www.microchip.com/developmenttools/productdetails/atsamc21_xpro). + +## Board Features + +- Microchip [ATSAMC21J18A] Cortex-M0 microcontroller @ 48 MHz (32-bit, 3.3V or 5V logic and power) + - 256kB Flash + - 32kB SRAM + - CAN and LIN interfaces + +## Prerequisites +* Install the cross compile toolchain `rustup target add thumbv6m-none-eabi` + +## Uploading an example +Check out the repository for examples: + +https://github.com/atsamd-rs/atsamd/tree/master/boards/atsamc21_xpro/examples + +* Be in this directory `cd boards/atsamc21_xpro` +* Build and upload in one step +``` +$ cargo flash --example blinky_pac --chip-description-path SAMC21.yaml --chip ATSAMC21J18A + Finished dev [unoptimized + debuginfo] target(s) in 7.56s + Flashing .../boards/atsamc21_xpro/target/thumbv6m-none-eabi/debug/examples/blinky_pac + Erasing sectors ✔ [00:00:00] [#######################] 16.00 KiB/16.00 KiB @ 91.94 KiB/s (eta 0s ) + Programming pages ✔ [00:00:00] [##########################] 2.00 KiB/2.00 KiB @ 5.79 KiB/s (eta 0s ) Finished in 0.593s +$ +``` \ No newline at end of file diff --git a/boards/atsamc21_xpro/SAMC21.yaml b/boards/atsamc21_xpro/SAMC21.yaml new file mode 100644 index 000000000000..44b9449df6ff --- /dev/null +++ b/boards/atsamc21_xpro/SAMC21.yaml @@ -0,0 +1,709 @@ +name: SAMC21 +generated_from_pack: true +pack_file_release: 1.2.176 +variants: +- name: ATSAMC21E15A + cores: + - name: main + type: armv6m + core_access_options: + !Arm + ap: 0 + psel: 0 + memory_map: + - !Ram + name: IRAM1 + range: + start: 0x20000000 + end: 0x20001000 + cores: + - main + - !Nvm + name: IROM1 + range: + start: 0x0 + end: 0x8000 + is_boot_memory: true + cores: + - main + - !Generic + name: IROM2 + range: + start: 0x400000 + end: 0x400400 + cores: + - main + flash_algorithms: + - atsamc_32 + - atsamc_32_eeprom +- name: ATSAMC21E16A + cores: + - name: main + type: armv6m + core_access_options: + !Arm + ap: 0 + psel: 0 + memory_map: + - !Ram + name: IRAM1 + range: + start: 0x20000000 + end: 0x20002000 + cores: + - main + - !Nvm + name: IROM1 + range: + start: 0x0 + end: 0x10000 + is_boot_memory: true + cores: + - main + - !Generic + name: IROM2 + range: + start: 0x400000 + end: 0x400800 + cores: + - main + flash_algorithms: + - atsamc_64 + - atsamc_64_eeprom +- name: ATSAMC21E17A + cores: + - name: main + type: armv6m + core_access_options: + !Arm + ap: 0 + psel: 0 + memory_map: + - !Ram + name: IRAM1 + range: + start: 0x20000000 + end: 0x20004000 + cores: + - main + - !Nvm + name: IROM1 + range: + start: 0x0 + end: 0x20000 + is_boot_memory: true + cores: + - main + - !Generic + name: IROM2 + range: + start: 0x400000 + end: 0x401000 + cores: + - main + flash_algorithms: + - atsamc_128 + - atsamc_128_eeprom +- name: ATSAMC21E18A + cores: + - name: main + type: armv6m + core_access_options: + !Arm + ap: 0 + psel: 0 + memory_map: + - !Ram + name: IRAM1 + range: + start: 0x20000000 + end: 0x20008000 + cores: + - main + - !Nvm + name: IROM1 + range: + start: 0x0 + end: 0x40000 + is_boot_memory: true + cores: + - main + - !Generic + name: IROM2 + range: + start: 0x400000 + end: 0x402000 + cores: + - main + flash_algorithms: + - atsamc_256 + - atsamc_256_eeprom +- name: ATSAMC21G15A + cores: + - name: main + type: armv6m + core_access_options: + !Arm + ap: 0 + psel: 0 + memory_map: + - !Ram + name: IRAM1 + range: + start: 0x20000000 + end: 0x20001000 + cores: + - main + - !Nvm + name: IROM1 + range: + start: 0x0 + end: 0x8000 + is_boot_memory: true + cores: + - main + - !Generic + name: IROM2 + range: + start: 0x400000 + end: 0x400400 + cores: + - main + flash_algorithms: + - atsamc_32 + - atsamc_32_eeprom +- name: ATSAMC21G16A + cores: + - name: main + type: armv6m + core_access_options: + !Arm + ap: 0 + psel: 0 + memory_map: + - !Ram + name: IRAM1 + range: + start: 0x20000000 + end: 0x20002000 + cores: + - main + - !Nvm + name: IROM1 + range: + start: 0x0 + end: 0x10000 + is_boot_memory: true + cores: + - main + - !Generic + name: IROM2 + range: + start: 0x400000 + end: 0x400800 + cores: + - main + flash_algorithms: + - atsamc_64 + - atsamc_64_eeprom +- name: ATSAMC21G17A + cores: + - name: main + type: armv6m + core_access_options: + !Arm + ap: 0 + psel: 0 + memory_map: + - !Ram + name: IRAM1 + range: + start: 0x20000000 + end: 0x20004000 + cores: + - main + - !Nvm + name: IROM1 + range: + start: 0x0 + end: 0x20000 + is_boot_memory: true + cores: + - main + - !Generic + name: IROM2 + range: + start: 0x400000 + end: 0x401000 + cores: + - main + flash_algorithms: + - atsamc_128 + - atsamc_128_eeprom +- name: ATSAMC21G18A + cores: + - name: main + type: armv6m + core_access_options: + !Arm + ap: 0 + psel: 0 + memory_map: + - !Ram + name: IRAM1 + range: + start: 0x20000000 + end: 0x20008000 + cores: + - main + - !Nvm + name: IROM1 + range: + start: 0x0 + end: 0x40000 + is_boot_memory: true + cores: + - main + - !Generic + name: IROM2 + range: + start: 0x400000 + end: 0x402000 + cores: + - main + flash_algorithms: + - atsamc_256 + - atsamc_256_eeprom +- name: ATSAMC21J15A + cores: + - name: main + type: armv6m + core_access_options: + !Arm + ap: 0 + psel: 0 + memory_map: + - !Ram + name: IRAM1 + range: + start: 0x20000000 + end: 0x20001000 + cores: + - main + - !Nvm + name: IROM1 + range: + start: 0x0 + end: 0x8000 + is_boot_memory: true + cores: + - main + - !Generic + name: IROM2 + range: + start: 0x400000 + end: 0x400400 + cores: + - main + flash_algorithms: + - atsamc_32 + - atsamc_32_eeprom +- name: ATSAMC21J16A + cores: + - name: main + type: armv6m + core_access_options: + !Arm + ap: 0 + psel: 0 + memory_map: + - !Ram + name: IRAM1 + range: + start: 0x20000000 + end: 0x20002000 + cores: + - main + - !Nvm + name: IROM1 + range: + start: 0x0 + end: 0x10000 + is_boot_memory: true + cores: + - main + - !Generic + name: IROM2 + range: + start: 0x400000 + end: 0x400800 + cores: + - main + flash_algorithms: + - atsamc_64 + - atsamc_64_eeprom +- name: ATSAMC21J17A + cores: + - name: main + type: armv6m + core_access_options: + !Arm + ap: 0 + psel: 0 + memory_map: + - !Ram + name: IRAM1 + range: + start: 0x20000000 + end: 0x20004000 + cores: + - main + - !Nvm + name: IROM1 + range: + start: 0x0 + end: 0x20000 + is_boot_memory: true + cores: + - main + - !Generic + name: IROM2 + range: + start: 0x400000 + end: 0x401000 + cores: + - main + flash_algorithms: + - atsamc_128 + - atsamc_128_eeprom +- name: ATSAMC21J17AU + cores: + - name: main + type: armv6m + core_access_options: + !Arm + ap: 0 + psel: 0 + memory_map: + - !Ram + name: IRAM1 + range: + start: 0x20000000 + end: 0x20004000 + cores: + - main + - !Nvm + name: IROM1 + range: + start: 0x0 + end: 0x20000 + is_boot_memory: true + cores: + - main + - !Generic + name: IROM2 + range: + start: 0x400000 + end: 0x401000 + cores: + - main + flash_algorithms: + - atsamc_128 + - atsamc_128_eeprom +- name: ATSAMC21J18A + cores: + - name: main + type: armv6m + core_access_options: + !Arm + ap: 0 + psel: 0 + memory_map: + - !Ram + name: IRAM1 + range: + start: 0x20000000 + end: 0x20008000 + cores: + - main + - !Nvm + name: IROM1 + range: + start: 0x0 + end: 0x40000 + is_boot_memory: true + cores: + - main + - !Generic + name: IROM2 + range: + start: 0x400000 + end: 0x402000 + cores: + - main + flash_algorithms: + - atsamc_256 + - atsamc_256_eeprom +- name: ATSAMC21J18AU + cores: + - name: main + type: armv6m + core_access_options: + !Arm + ap: 0 + psel: 0 + memory_map: + - !Ram + name: IRAM1 + range: + start: 0x20000000 + end: 0x20008000 + cores: + - main + - !Nvm + name: IROM1 + range: + start: 0x0 + end: 0x40000 + is_boot_memory: true + cores: + - main + - !Generic + name: IROM2 + range: + start: 0x400000 + end: 0x402000 + cores: + - main + flash_algorithms: + - atsamc_256 + - atsamc_256_eeprom +- name: ATSAMC21N17A + cores: + - name: main + type: armv6m + core_access_options: + !Arm + ap: 0 + psel: 0 + memory_map: + - !Ram + name: IRAM1 + range: + start: 0x20000000 + end: 0x20004000 + cores: + - main + - !Nvm + name: IROM1 + range: + start: 0x0 + end: 0x20000 + is_boot_memory: true + cores: + - main + - !Generic + name: IROM2 + range: + start: 0x400000 + end: 0x401000 + cores: + - main + flash_algorithms: + - atsamc_128 + - atsamc_128_eeprom +- name: ATSAMC21N18A + cores: + - name: main + type: armv6m + core_access_options: + !Arm + ap: 0 + psel: 0 + memory_map: + - !Ram + name: IRAM1 + range: + start: 0x20000000 + end: 0x20008000 + cores: + - main + - !Nvm + name: IROM1 + range: + start: 0x0 + end: 0x40000 + is_boot_memory: true + cores: + - main + - !Generic + name: IROM2 + range: + start: 0x400000 + end: 0x402000 + cores: + - main + flash_algorithms: + - atsamc_256 + - atsamc_256_eeprom +flash_algorithms: +- name: atsamc_32 + description: ATSAMC 32kB Flash + default: true + instructions: LUlKBxFgLkosSVFgLUlJRAhgACBwRwAgcEcPIckCAUBCCA8ggAICQBC1JUjCYSZKAoACfdIH/NAjTAEiPzzSAosYDOBKCMJhBIACfdIH/NACfZIHAdUBIBC9/zEBMZlC8NMAIBC98LXJHIkIFkuJABNN2xwrgCt92wf80BJOPT4AKRbQA0ZAKQHZQCQF4AxGA+CAygkfgMMkHwAs+dEugEAwK33bB/zQK32bB+jVASDwvQAg8L0AACIAAQCeAAQAAEAAQQQAAABBpQAAAAAAAAAAAAA= + pc_init: 0x1 + pc_uninit: 0x17 + pc_program_page: 0x67 + pc_erase_sector: 0x1b + data_section_offset: 0xcc + flash_properties: + address_range: + start: 0x0 + end: 0x8000 + page_size: 0x400 + erased_byte_value: 0xff + program_page_timeout: 100 + erase_sector_timeout: 1000 + sectors: + - size: 0x800 + address: 0x0 +- name: atsamc_32_eeprom + description: ATSAMC 1kB Data EEPROM + default: true + instructions: HElKBxFgHUobSVFgHElJRAhgACBwRwAgcEdBCBdIwWEYSQGAAX3JB/zQAH2ABwHVASBwRwAgcEcQtRJMD0sqNByAHH3kB/zQyRyJCIkAAuAQygkfEMAAKfrRCkiAHBiAGH3AB/zQGH2ABwHVASAQvQAgEL0iAAEAngAEAABAAEEEAAAAGqUAAAAAAAAAAAAA + pc_init: 0x1 + pc_uninit: 0x17 + pc_program_page: 0x39 + pc_erase_sector: 0x1b + data_section_offset: 0x88 + flash_properties: + address_range: + start: 0x400000 + end: 0x400400 + page_size: 0x40 + erased_byte_value: 0xff + program_page_timeout: 100 + erase_sector_timeout: 1000 + sectors: + - size: 0x100 + address: 0x0 +- name: atsamc_64 + description: ATSAMC 64kB Flash + default: true + instructions: LUlKBxFgLkosSVFgLUlJRAhgACBwRwAgcEcPIQkDAUBCCA8gwAICQBC1JUjCYSZKAoACfdIH/NAjTAEiPzwSA4sYDOBKCMJhBIACfdIH/NACfZIHAdUBIBC9/zEBMZlC8NMAIBC98LXJHIkIFkuJABNN2xwrgCt92wf80BJOPT4AKRbQA0ZAKQHZQCQF4AxGA+CAygkfgMMkHwAs+dEugEAwK33bB/zQK32bB+jVASDwvQAg8L0AACIAAQCeAAQAAEAAQQQAAABBpQAAAAAAAAAAAAA= + pc_init: 0x1 + pc_uninit: 0x17 + pc_program_page: 0x67 + pc_erase_sector: 0x1b + data_section_offset: 0xcc + flash_properties: + address_range: + start: 0x0 + end: 0x10000 + page_size: 0x400 + erased_byte_value: 0xff + program_page_timeout: 100 + erase_sector_timeout: 1000 + sectors: + - size: 0x1000 + address: 0x0 +- name: atsamc_64_eeprom + description: ATSAMC 2kB Data EEPROM + default: true + instructions: HElKBxFgHUobSVFgHElJRAhgACBwRwAgcEdBCBdIwWEYSQGAAX3JB/zQAH2ABwHVASBwRwAgcEcQtRJMD0sqNByAHH3kB/zQyRyJCIkAAuAQygkfEMAAKfrRCkiAHBiAGH3AB/zQGH2ABwHVASAQvQAgEL0iAAEAngAEAABAAEEEAAAAGqUAAAAAAAAAAAAA + pc_init: 0x1 + pc_uninit: 0x17 + pc_program_page: 0x39 + pc_erase_sector: 0x1b + data_section_offset: 0x88 + flash_properties: + address_range: + start: 0x400000 + end: 0x400800 + page_size: 0x40 + erased_byte_value: 0xff + program_page_timeout: 100 + erase_sector_timeout: 1000 + sectors: + - size: 0x100 + address: 0x0 +- name: atsamc_128 + description: ATSAMC 128kB Flash + default: true + instructions: LUlKBxFgLkosSVFgLUlJRAhgACBwRwAgcEcPIUkDAUBCCA8gAAMCQBC1JUjCYSZKAoACfdIH/NAjTAEiPzxSA4sYDOBKCMJhBIACfdIH/NACfZIHAdUBIBC9/zEBMZlC8NMAIBC98LXJHIkIFkuJABNN2xwrgCt92wf80BJOPT4AKRbQA0ZAKQHZQCQF4AxGA+CAygkfgMMkHwAs+dEugEAwK33bB/zQK32bB+jVASDwvQAg8L0AACIAAQCeAAQAAEAAQQQAAABBpQAAAAAAAAAAAAA= + pc_init: 0x1 + pc_uninit: 0x17 + pc_program_page: 0x67 + pc_erase_sector: 0x1b + data_section_offset: 0xcc + flash_properties: + address_range: + start: 0x0 + end: 0x20000 + page_size: 0x400 + erased_byte_value: 0xff + program_page_timeout: 100 + erase_sector_timeout: 1000 + sectors: + - size: 0x2000 + address: 0x0 +- name: atsamc_128_eeprom + description: ATSAMC 4kB Data EEPROM + default: true + instructions: HElKBxFgHUobSVFgHElJRAhgACBwRwAgcEdBCBdIwWEYSQGAAX3JB/zQAH2ABwHVASBwRwAgcEcQtRJMD0sqNByAHH3kB/zQyRyJCIkAAuAQygkfEMAAKfrRCkiAHBiAGH3AB/zQGH2ABwHVASAQvQAgEL0iAAEAngAEAABAAEEEAAAAGqUAAAAAAAAAAAAA + pc_init: 0x1 + pc_uninit: 0x17 + pc_program_page: 0x39 + pc_erase_sector: 0x1b + data_section_offset: 0x88 + flash_properties: + address_range: + start: 0x400000 + end: 0x401000 + page_size: 0x40 + erased_byte_value: 0xff + program_page_timeout: 100 + erase_sector_timeout: 1000 + sectors: + - size: 0x100 + address: 0x0 +- name: atsamc_256 + description: ATSAMC 256kB Flash + default: true + instructions: LUlKBxFgLkosSVFgLUlJRAhgACBwRwAgcEcPIYkDAUBCCA8gQAMCQBC1JUjCYSZKAoACfdIH/NAjTAEiPzySA4sYDOBKCMJhBIACfdIH/NACfZIHAdUBIBC9/zEBMZlC8NMAIBC98LXJHIkIFkuJABNN2xwrgCt92wf80BJOPT4AKRbQA0ZAKQHZQCQF4AxGA+CAygkfgMMkHwAs+dEugEAwK33bB/zQK32bB+jVASDwvQAg8L0AACIAAQCeAAQAAEAAQQQAAABBpQAAAAAAAAAAAAA= + pc_init: 0x1 + pc_uninit: 0x17 + pc_program_page: 0x67 + pc_erase_sector: 0x1b + data_section_offset: 0xcc + flash_properties: + address_range: + start: 0x0 + end: 0x40000 + page_size: 0x400 + erased_byte_value: 0xff + program_page_timeout: 100 + erase_sector_timeout: 1000 + sectors: + - size: 0x4000 + address: 0x0 +- name: atsamc_256_eeprom + description: ATSAMC 8kB Data EEPROM + default: true + instructions: HElKBxFgHUobSVFgHElJRAhgACBwRwAgcEdBCBdIwWEYSQGAAX3JB/zQAH2ABwHVASBwRwAgcEcQtRJMD0sqNByAHH3kB/zQyRyJCIkAAuAQygkfEMAAKfrRCkiAHBiAGH3AB/zQGH2ABwHVASAQvQAgEL0iAAEAngAEAABAAEEEAAAAGqUAAAAAAAAAAAAA + pc_init: 0x1 + pc_uninit: 0x17 + pc_program_page: 0x39 + pc_erase_sector: 0x1b + data_section_offset: 0x88 + flash_properties: + address_range: + start: 0x400000 + end: 0x402000 + page_size: 0x40 + erased_byte_value: 0xff + program_page_timeout: 100 + erase_sector_timeout: 1000 + sectors: + - size: 0x100 + address: 0x0 diff --git a/boards/atsamc21_xpro/build.rs b/boards/atsamc21_xpro/build.rs new file mode 100644 index 000000000000..4bed4688f2c0 --- /dev/null +++ b/boards/atsamc21_xpro/build.rs @@ -0,0 +1,16 @@ +use std::env; +use std::fs::File; +use std::io::Write; +use std::path::PathBuf; +fn main() { + if env::var_os("CARGO_FEATURE_RT").is_some() { + let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap()); + File::create(out.join("memory.x")) + .unwrap() + .write_all(include_bytes!("memory.x")) + .unwrap(); + println!("cargo:rustc-link-search={}", out.display()); + println!("cargo:rerun-if-changed=memory.x"); + } + println!("cargo:rerun-if-changed=build.rs"); +} diff --git a/boards/atsamc21_xpro/examples/blinky_pac.rs b/boards/atsamc21_xpro/examples/blinky_pac.rs new file mode 100644 index 000000000000..7edb1929291a --- /dev/null +++ b/boards/atsamc21_xpro/examples/blinky_pac.rs @@ -0,0 +1,29 @@ +#![no_std] +#![no_main] + +use atsamc21_xpro as bsp; +use atsamc21j as pac; +use cortex_m::asm::delay as cycle_delay; + +#[cfg(not(feature = "use_semihosting"))] +use panic_halt as _; +#[cfg(feature = "use_semihosting")] +use panic_semihosting as _; + +use bsp::entry; + +#[entry] +fn main() -> ! { + let mut peripherals = pac::Peripherals::take().unwrap(); + let pa = &peripherals.PORT.group0; + unsafe { + pa.dirset.write(|w| w.bits(0x8000)); + } + loop { + // After reset clock runs at 4MHz + cycle_delay(4_000_000 / 2); + unsafe { + pa.outtgl.write(|w| w.bits(0x8000)); + } + } +} diff --git a/boards/atsamc21_xpro/memory.x b/boards/atsamc21_xpro/memory.x new file mode 100644 index 000000000000..9b85708b95de --- /dev/null +++ b/boards/atsamc21_xpro/memory.x @@ -0,0 +1,36 @@ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x40000 + RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000 +} + +/* TODO: Why is .vector_table 1kB? */ +/* TODO: Section for CAN message RAM */ + +/* This is where the call stack will be allocated. */ +/* The stack is of the full descending type. */ +/* You may want to use this variable to locate the call stack and static + variables in different memory regions. Below is shown the default value */ +/* _stack_start = ORIGIN(RAM) + LENGTH(RAM); */ + +/* You can use this symbol to customize the location of the .text section */ +/* If omitted the .text section will be placed right after the .vector_table + section */ +/* This is required only on microcontrollers that store some configuration right + after the vector table */ +/* _stext = ORIGIN(FLASH) + 0x400; */ + +/* Example of putting non-initialized variables into custom RAM locations. */ +/* This assumes you have defined a region RAM2 above, and in the Rust + sources added the attribute `#[link_section = ".ram2bss"]` to the data + you want to place there. */ +/* Note that the section will not be zero-initialized by the runtime! */ +/* SECTIONS { + .ram2bss (NOLOAD) : ALIGN(4) { + *(.ram2bss); + . = ALIGN(4); + } > RAM2 + } INSERT AFTER .bss; +*/ + + diff --git a/boards/atsamc21_xpro/src/lib.rs b/boards/atsamc21_xpro/src/lib.rs new file mode 100644 index 000000000000..856155de777b --- /dev/null +++ b/boards/atsamc21_xpro/src/lib.rs @@ -0,0 +1,12 @@ +#![no_std] +#![recursion_limit = "1024"] + +// pub use atsamd_hal as hal; +// pub use hal::pac; +// pub use pins::*; + +#[cfg(feature = "rt")] +pub use cortex_m_rt::entry; + +// pub mod devices; +// pub mod pins;